Semiconductor package structure and manufacturing method thereof

A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application Ser. No. 100144388, filed on Dec. 2, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a semiconductor package structure and a manufacturing method thereof.

2. Description of Related Art

A chip package serves to protect bare chips, lower chip contact density, and ensure favorable heat dissipation of chips. Conventional packaging methods include installing chips to lead frames or circuit boards through wire bonding or flip chip bonding, so that the contacts on the chips may be electrically connected to the lead frames or the circuit boards. Therefore, the contacts of the chips can be re-distributed through the lead frames or the circuit boards, so as to satisfy the contact distribution of external devices of next hierarchy.

However, dimensions of chips are reduced little by little due to the advancement of technology and the miniaturization of components. As the dimensions of chips are reduced, the distance between the chips and leads of the lead frames is relatively increased, and so is the length of bonding wires connecting the chips and the leads. Thereby, transmission signals of components may be degraded, electrical performance may be reduced, and manufacturing costs may be increased Moreover, the bonding wires with long length may encounter issues of wire collapse or wire sweep during the molding process, which may pose a negative impact on the reliability of products.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor package structure with favorable reliability.

The invention is further directed to a method of manufacturing a semiconductor package structure for manufacturing the aforesaid semiconductor package structure.

In an embodiment of the invention, a method of manufacturing a semiconductor package structure is provided. The method includes following steps. A conductive substrate is provided. Here, the conductive substrate has a first surface and a second surface opposite to the first surface. A heat-conductive block is adhered to a portion of the second surface of the conductive substrate via a first adhesive layer. A portion of the conductive substrate is removed by performing a half-etching process on the first surface of the conductive substrate, and an opening is formed on the first surface of the conductive substrate. The remaining conductive substrate is patterned to form a plurality of leads electrically insulated from one another, and a portion of the heat-conductive block is exposed. Each of the leads has a first portion and a second portion, a thickness of the first portion is greater than a thickness of the second portion, and a first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block. Here, the second portions of the leads neighbor and surround the chip, and the chip is electrically connected to the second portions of the leads. A molding compound is formed to encapsulate the chip, a portion of the leads, and the exposed portion of the heat-conductive block.

In an embodiment of the invention, a semiconductor package structure that includes a heat-conductive block, a plurality of leads, a first adhesive layer, a chip, and a molding compound is provided. The heat-conductive block has a first top surface and a first bottom surface opposite to the first top surface. The leads are disposed on the first top surface of the heat-conductive block and expose a portion of the first top surface. The leads are electrically insulated from one another, and each of the leads has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion, and a first lower surface of the first portion and a second lower surface of the second portion are coplanar. The first adhesive layer is disposed between the leads and the heat-conductive block. The chip is disposed on the exposed portion of the first top surface of the heat-conductive block. Here, the second portions of the leads neighbor and surround the chip, and the chip is electrically connected to the second portions of the leads. The molding compound encapsulates the chip, a portion of the leads, and the exposed portion of the heat-conductive block.

Based on the above, as described in the embodiments of the invention, the half-etching process and the patterning process are performed on the conductive substrate to form the leads having the first and second portions, and the first and second portions have different thicknesses. Accordingly, when the chip is disposed on the heat-conductive block, the semiconductor package structure described in an embodiment of the invention can have favorable heat dissipation performance; what is more, the distance of bonding wires between the chip and the leads may be reduced during wire bonding due to the second portions of the leads neighboring and surrounding the chip. Thereby, the conventional issues of collapse of long wires or wire sweep can be resolved, and product reliability can be effectively improved. Moreover, when the chip is electrically connected to the second portions of the leads through flip chip bonding, the thickness of the package can be effectively reduced, such that the semiconductor package structure can have a relatively small package thickness.

Other features and advantages of the invention will be further understood from the further technological features disclosed by the embodiments of the invention wherein there are shown and described embodiments of this invention, simply by way of illustration of modes best suited to carry out the invention.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a schematic top view illustrating a semiconductor package structure according to an embodiment of the invention.FIG. 2AtoFIG. 2Eare schematic cross-sectional views illustrating a method of manufacturing a semiconductor package structure according to an embodiment of the invention. With reference toFIG. 2A, the method of manufacturing the semiconductor package structure in the present embodiment includes following steps. A conductive substrate110is provided. The conductive substrate110has a first surface112and a second surface114opposite to the first surface112. Besides, the conductive substrate110is, for instance, made of metal, such as copper, copper alloy, Fe—Ni alloy, or any other appropriate metallic material. Certainly, the material of the conductive substrate110may be any other appropriate conductive material.

As indicated inFIG. 2A, a heat-conductive block130is adhered to a portion of the second surface114of the conductive substrate110via a first adhesive layer120. Here, the first adhesive layer120is located between the heat-conductive block130and the conductive substrate110, and the heat-conductive block130exposes a portion of the second surface114of the conductive substrate110. Specifically, the heat-conductive block130described in the present embodiment has a first top surface132and a first bottom surface134opposite to the first top surface132. The first top surface132connects the first adhesive layer120, and the heat-conductive block130is, for instance, made of metal, such as copper, copper alloy, aluminum alloy, Fe—Ni alloy, or any other appropriate conductive material.

With reference toFIG. 2B, a portion of the conductive substrate110is removed by performing a half-etching process on the first surface112of the conductive substrate110, and an opening113is formed on the first surface112of the conductive substrate110. Here, a thickness of a portion of the conductive substrate110in the opening is less than a thickness of the original conductive substrate110(on which no half-etching process is performed).

With reference toFIG. 1andFIG. 2C, the remaining conductive substrate110is patterned to form a plurality of leads140electrically insulated form one another, and a portion of the heat-conductive block130(i.e., a portion of the first top surface132of the heat-conductive block130) is exposed. Here, the remaining conductive substrate110is patterned through performing an etching process, for instance.

In particular, according to the present embodiment, each of the leads140has a first portion142and a second portion144. A thickness T1of the first portion142is greater than a thickness T2of the second portion144, and a first lower surface143of the first portion142and a second lower surface145of the second portion144are coplanar. Besides, in the present embodiment, a distance between the first portions142of any two adjacent leads140is P1, a distance between the second portions144of any two adjacent leads140is P2, and preferably 0.8 P1≦P2≦1.2 P1. Here, the distance P2between the second portions144of any two adjacent leads140, for instance, ranges from about 40 μm to about 60 μm, preferably from about 50 μm to about 60 μm. The distance P2may be adjusted according to the distance between pads152of a chip and should not be construed as a limitation to the invention.

With reference toFIG. 1andFIG. 2D, a chip150is disposed on the exposed portion of the heat-conductive block130(i.e., the exposed portion of the first top surface132of the heat-conductive block130). Here, the second portions144of the leads140neighbor and surround the chip150, and the chip150is electrically connected to the second portions144of the leads140. In the present embodiment, the chip150is fixed to the exposed portion of the heat-conductive block130via a second adhesive layer125. Namely, the second adhesive layer125is located between the exposed portion of the first top surface132of the heat-conductive block130and the chip150, and the chip150is electrically connected to the second portions144of the leads140via a plurality of bonding wires160.

With reference toFIG. 1andFIG. 2E, a molding compound170is formed to encapsulate the chip150, a portion of the leads140, and the exposed portion of the heat-conductive block130, and space between the leads140is filled with the molding compound170. The first bottom surface134of the heat-conductive block130and a second bottom surface172of the molding compound170are substantially coplanar. Certainly, in other embodiments not shown in the drawings, the first bottom surface134of the heat-conductive block130may be encapsulated by the molding compound170. Preferably, the molding compound170exposes parts of the first portions142of the leads140to form a normal lead frame (as shown inFIG. 2E), or the leads140may not be exposed based on actual demands, so as to form a Quad Flat Non-leaded (QFN) structure (not shown). So far, the semiconductor package structure100ais completely formed.

As shown inFIG. 2E, the semiconductor package structure100adescribed in the present embodiment structurally includes the first adhesive layer120, the second adhesive layer125, the heat-conductive block130, the leads140, the chip150, the bonding wires160, and the molding compound170. In particular, the heat-conductive block130has the first top surface132and the first bottom surface134opposite to the first top surface132. The leads140are disposed on the first top surface132of the heat-conductive block130and expose a portion of the first top surface132. In addition, the leads140are electrically insulated from one another, and each of the leads140has a first portion142and a second portion144. The thickness T1of the first portion142is greater than the thickness T2of the second portion144, and the first lower surface143of the first portion142and the second lower surface145of the second portion144are coplanar. The first adhesive layer120is disposed between the leads140and the heat-conductive block130, and the leads140are fixed to the heat-conductive block130via the first adhesive layer120. The chip150is disposed on the exposed portion of the first top surface132of the heat-conductive block130. Here, the second portions144of the leads140neighbor and surround the chip150. The chip150is fixed to the exposed portion of the first top surface132of the heat-conductive block130via the second adhesive layer125and is electrically connected to the second portions144of the leads140. The molding compound170encapsulates the chip150, a portion of the leads140, and the exposed portion of the heat-conductive block130. Here, the first bottom surface134of the heat-conductive block130is exposed by the molding compound170, and the first bottom surface134of the heat-conductive block130and the second bottom surface172of the molding compound170are substantially coplanar.

According to the present embodiment, the half-etching process and the patterning process are performed on the conductive substrate110to form the leads140having the first and second portions142and144, and the thickness T1of the first portions142is greater than the thickness T2of the second portions144. As a consequence, when the chip150is disposed on the heat-conductive block130, heat generated by the chip150may be rapidly transported to the external surroundings through the first bottom surface134of the heat-conductive block130, which guarantees the favorable heat dissipation performance of the semiconductor package structure100a described in the present embodiment. Moreover, owing to the design of the second portions144of the leads140neighboring and surrounding the chip150, the chip150may be electrically connected to the second portions144of the leads140via the bonding wires160through wire bonding. As such, the distance of bonding wires between the chip150and the leads140may be effectively reduced during wire bonding, so as to preclude collapse of long wires or wire sweep, and product reliability can be effectively improved.

FIG. 3AtoFIG. 3Bare schematic cross-sectional views illustrating a method of manufacturing a semiconductor package structure according to another embodiment of the invention. Same reference numbers representing the same or similar components described in the previous embodiment are applied in the present embodiment, and repetitive explanation in the previous embodiment and in the present embodiment is omitted. For a precise description of this section, references which can be found in the previous embodiment are not provided hereinafter.

With reference toFIG. 3B, the main difference between the semiconductor package structure100bdescribed in the present embodiment and the semiconductor package structure100adescribed in the previous embodiment lies in that the semiconductor package structure100bfurther includes a plurality of bumps165disposed between the chip150and the second portions144of the leads140. In addition, the chip150of the semiconductor package structure100bis electrically connected to the second portions144of the leads140via the bumps165through flip chip bonding. In the present embodiment, the chip150is electrically connected to the second portions144of the leads140through flip chip bonding, and the thickness T2of the second portions144of the leads140is less than the thickness T1of the first portions142. Hence, the thickness of the entire package can be effectively reduced, and thus the semiconductor package structure100bcan have a relatively small package thickness.

As to the manufacturing process, the semiconductor package structure100bdescribed in the present embodiment may be formed by conducting the manufacturing method similar to that of the semiconductor package structure100adescribed in the previous embodiment. Besides, after performing the step shown inFIG. 2C, i.e., after patterning the remaining conductive substrate110to form the leads140electrically insulated from one another, the chip150is electrically connected to the second portions144of the leads140via the bumps165through flip chip bonding. The step shown inFIG. 2Eis then carried out to complete the fabrication of the semiconductor package structure100b.

The manufacturing methods shown inFIG. 2AtoFIG. 2Eand inFIG. 3AtoFIG. 3Bare merely exemplary, and some steps in these manufacturing methods are common to people having ordinary skill in the art pertinent to package. Based on actual conditions, those who have ordinary skill in the art can adjust, omit, or add manufacturing steps. For instance, plural heat-conductive blocks130may be arranged in array on the conductive substrate110, and a singulation process is performed to form a plurality of semiconductor package structures100aor100bat the same time, so as to comply with the mass production requirement and the cost reduction demand. Detailed description thereof is omitted.

In light of the foregoing, as described in the embodiments of the invention, the half-etching process and the patterning process are performed on the conductive substrate to form the leads having the first and second portions, and the first and second portions have different thicknesses. Accordingly, when the chip is disposed on the heat-conductive block, the semiconductor package structure described in an embodiment of the invention can have favorable heat dissipation performance; what is more, the distance of bonding wires between the chip and the leads may be reduced during wire bonding due to the second portions of the leads neighboring and surrounding the chip. Thereby, the conventional issues of collapse of long wires or wire sweep can be resolved, and product reliability can be effectively improved. Moreover, when the chip is electrically connected to the second portions of the leads through flip chip bonding, the thickness of the package can be effectively reduced, such that the semiconductor package structure can have a relatively small package thickness.