Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system

A memory system includes a memory device configured to monitor a first oscillator count value for a write data strobe signal for sampling a data signal at a first temperature and a second oscillator count value for the write data strobe signal for sampling the data signal at a second temperature, and a memory controller configured to determine a weight based on the first oscillator count value and the second oscillator count value, wherein the memory device is configured to sample the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a change in temperature of the memory device based on the weight.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2020-0115516, filed on Sep. 9, 2020 and 10-2021-0004928, filed on Jan. 13, 2021, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety.

BACKGROUND

The inventive concept relates to a semiconductor device, and more particularly, to a memory device which is configured to adjust delays on a data clock path, a memory system including the memory device, and an operating method of the memory system.

Electronic devices including smartphones, graphic accelerators, artificial intelligence (AI) accelerators, etc. may process data by using memory devices such as dynamic random access memory (DRAM). Electronic devices may control internal or external memory devices through a memory controller. A memory controller may transmit various signals to a memory device to control the memory device.

A memory device and a memory controller may transmit and receive data through a data signal. A memory device may sample a data signal by using a data clock signal (or a write data strobe signal) provided from a memory controller. For example, a memory device may sample a data signal based on an edge timing of a data clock signal. To sample a data signal based on a data clock signal, a memory device may transfer the data clock signal to a circuit for sampling a data signal. A memory controller may perform trainings in relation to a data clock signal to compensate for a delay on a path for transferring a data clock signal (hereinafter, referred to as a data clock path).

A delay on a data clock path may vary according to a change in temperature of a memory device. When a sampling timing changes due to variations of a delay on a data clock path, a setup/hold (S/H) margin may decrease. A memory controller may perform retrainings to compensate for variations of delays according to temperature changes. Accordingly, a memory controller may adjust a delay on a data clock path. However, when a retraining is performed, resources used for the training may increase.

SUMMARY

The inventive concept provides a memory device configured to adjust delays on a data clock path without retrainings by a memory controller, a memory system including the memory device, and an operating method of the memory system.

According to an aspect of the inventive concept, there is provided a memory system including a memory device configured to monitor a first oscillator count value for a write data strobe signal for sampling a data signal at a first temperature and a second oscillator count value for the write data strobe signal for sampling the data signal at a second temperature, and a memory controller configured to determine a weight based on the first oscillator count value and the second oscillator count value, wherein the memory device is configured to sample the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a change in temperature of the memory device based on the weight.

According to another aspect of the inventive concept, there is provided an operating method of a memory system including a memory controller and a memory device configured to sample a data signal provided from the memory controller based on a write data strobe signal provided from the memory controller, wherein the method includes: requesting, by the memory controller, a first oscillator count value of the write data strobe signal at a first temperature from the memory device; transmitting, by the memory device, the first oscillator count value to the memory controller; requesting, by the memory controller, a second oscillator count value of the write data strobe signal at a second temperature from the memory device; transmitting, by the memory device, the second oscillator count value to the memory controller; setting, by the memory controller, a weight determined based on the first oscillator count value and the second oscillator count value to the memory device; and sampling, by the memory device, the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a change in temperature of the memory device based on the weight.

According to another aspect of the inventive concept, there is provided a memory device including a data sampler configured to sample a data signal based on a write data strobe signal, a storage circuit configured to store a weight representing an amount of variations of a delay on a transfer path of the write data strobe signal according to a temperature change, a temperature sensor configured to sense temperature, a temperature compensator configured to generate a delay code based on the sensed temperatures and a weight, a reference voltage generator configured to generate a reference voltage from a power supply voltage based on the delay code, a voltage regulator configured to generate a regulated voltage based on the reference voltage, and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler by using the regulated voltage.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept will be described clearly and with sufficient detail to the extent that a person with ordinary skill in the art would be able to carry out the inventive concept.

FIG.1is a block diagram illustrating a memory system10according to an embodiment. With reference toFIG.1, the memory system10may include a memory controller100and a memory device200. The memory controller100may control overall operations of the memory device200. For example, the memory controller100may control the memory device200so that data DATA is output from the memory device200, or stored in the memory device200.

The memory controller100may transmit various signals to the memory device200and receive various signals from the memory device200. For example, the memory controller100may transmit a command/address signal CA, a clock signal CK, a write data strobe signal WDQS, and a data signal DQ to the memory device200, and receive a data signal DQ from the memory device200. For example, the data signal DQ is a multi-bit signal. The command/address signal CA may include a command CMD and/or an address ADD, and a data signal DQ may include data DATA.

The memory controller100may be implemented in a host (not explicitly shown in the drawings) and access the memory device200according to a request of an internal processor (not explicitly shown in the drawings) of the host. For example, the memory controller100may access the memory device200in a direct memory access (DMA) manner. For example, the memory controller100may be implemented as a part of a System-on-Chip (SoC), but the implementation is not limited thereto.

The memory device200may operate as a buffer memory, a working memory, or a main memory for a host including the memory controller100. The memory device200may operate according to control by the memory controller100. For example, the memory device200may output data DATA stored according to control by the memory controller100, or store data DATA provided from the memory controller100.

The memory device200may receive various signals from the memory controller100and transmit various signals to the memory controller100. For example, the memory device200may receive a command/address signal CA, a clock signal CK, a write data strobe signal WDQS, and a data signal DQ from the memory controller100, and transmit a data signal DQ to the memory device200.

The memory controller100may include a phase locked loop110, a clock divider120, a first transmitter130, a second transmitter140, a phase controller150, a third transmitter160, and a fourth transmitter170. The phase locked loop110may generate a first internal clock signal ICS1. For example, the first internal clock signal ICS1may have a specific frequency and toggle between a high level and a low level. The clock divider120may divide the first internal clock signal ICS1to generate a divided internal clock signal dICS. For example, the frequency of the divided internal clock signal dICS may be half of the frequency of the first internal clock signal ICS1. Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim).

The first transmitter130may transmit the command/address signal CA to the memory device200based on the divided internal clock signals dICS. For example, the first transmitter130may transmit the command CMD and/or addresses ADD to the memory device200through the command/address signal CA at a rising edge and/or falling edge timing of the divided internal clock signal dICS. The command/address signals CA may be transmitted to the memory device200through a command/address pin CA_P′.

The second transmitter140may transmit divided internal clock signal dICS to the memory device200as a clock signal CK. For example, the divided internal clock signal dICS and the clock signal CK may have the same frequency and phase. A clock signal CK may be transmitted to the memory device200through a clock pin CK_P′.

The phase controller150may generate a second internal clock signal ICS2having a phase different from the phase of the first internal clock signal ICS1based on the first internal clock signal ICS1. For example, the phase difference between the first internal clock signal ICS1and the second internal clock signal ICS2may be 90 degrees.

The third transmitter160may transmit the first internal clock signal ICS1to the memory device200as a write data strobe signal WDQS. For example, the first internal clock signal ICS1and the write data strobe signal WDQS may have the same frequency and phase. For example, when the frequency of the first internal clock signal ICS1is twice the frequency of the divided internal clock signal dICS, the frequency of the write data strobe signal WDQS may be twice the frequency of the clock signal CK. The write data strobe signal WDQS may be transmitted to the memory device200through a write data strobe pin W_P′.

The fourth transmitter170may transmit a data signal DQ to the memory device200based on the second internal clock signal ICS2. For example, the fourth transmitter170may transmit data DATA to the memory device200through the data signal DQ at a rising edge and/or falling edge timing of the second internal clock signal ICS2. The data signal DQ may be transmitted to the memory device200through a data pin D_P′.

As described above, the clock signal CK and write data strobe signal WDQS may be generated through a single phase locked loop110. Accordingly, an operational current of the memory controller100may decrease. However, the inventive concept is not limited thereto, and each of the clock signal CK and the write data strobe signal WDQS may be generated through each separate phase locked loop.

The memory device200may include a command/address sampler210, a clock receiver220, a write data strobe signal WDQS transfer circuit230, and a data sampler240. The clock receiver220may receive a clock signal CK from the memory controller100through a clock pin CK_P. The clock signal CK received by the clock receiver220may be transmitted to the command/address sampler210.

The command/address sampler210may receive the command/address signal CA from the memory controller100through a command/address pin CA_P. The command/address sampler210may sample the command/address signal CA based on the clock signal CK. For example, the command/address sampler210may sample the command/address signal CA at a rising edge and/or falling edge timing of clock signal CK. Accordingly, the memory device200may obtain command and/or address CMD/ADD.

The WDQS transfer circuit230may receive write data strobe signal WDQS from the memory controller100through a write data strobe pin W_P. The WDQS transfer circuit230may transfer write data strobe signal WDQS to the data sampler240. In example embodiments, the WDQS transfer circuit230may include a write data strobe signal WDQS receiver and a write data strobe signal WDQS tree circuitry. For example, the write data strobe signal WDQS receiver may receive write data strobe signal WDQS provided through the write data strobe pin W_P. The write data strobe signal WDQS tree circuitry may include multiple repeaters configured to transfer the write data strobe signal WDQS output from the write data strobe signal WDQS receiver to the data sampler240. For example, each of the multiple repeaters may be implemented by at least one buffer or inverter.

The data sampler240may receive a data signal DQ from the memory controller100through a data pin D_P. The data sampler240may sample a data signal DQ based on a write data strobe signal WDQS. For example, the data sampler240may sample a data signal DQ at a rising edge and/or falling edge timing of a write data strobe signal WDQS. Accordingly, the memory device200may obtain data DATA.

As described above, the memory device200may sample a data signal DQ based on a write data strobe signal WDQS different from a clock signal CK. For example, a write data strobe signal WDQS may be a clock signal (i.e., a data clock signal) for data communication.

In example embodiments, trainings may be performed in relation to a write data strobe signal WDQS to compensate for a delay on a path transferring the write data strobe signal WDQS to the data sampler240in an initialization process of the memory device200. Accordingly, a transfer timing (i.e., a sampling timing) of the write data strobe signal WDQS may be determined to increase an S/H margin of the data sampler240.

In example embodiments, a path through which a write data strobe signal WDQS are transferred from the write data strobe pin W_P to the data sampler240(hereinafter, referred to as a WDQS path WDQS_P) may not match a path through which a data signal DQ is transferred from the data pin D_P to the data sampler240(hereinafter, referred to as a DQ path DQ_P). For example, circuits on the WDQS path WDQS_P and DQ path DQ_P may be arranged in an asymmetrical manner. For example, the number of transistors included in the WDQS path WDQS_P may be different from that of the number of transistors included in each DQ path DQ_P. In such case, even when trainings are performed in relation to a write data strobe signal WDQS in the initialization process of the memory device200, variations of delays on the WDQS path WDQS_P may be different from those on the DQ path DQ_P as a result temperature changes that may occur subsequent to when the trainings are performed. Accordingly, an arrival timing (i.e., a sampling timing) of a write data strobe signal WDQS transferred to the data sampler240may change. In particular, variations of delays on the WDQS path WDQS_P according to temperature changes may change based on characteristics of elements on the WDQS path WDQS_P. Accordingly, an S/H margin of the data sampler240may decrease.

According to some embodiments, variations of delays on the WDQS path WDQS_P according to temperature changes may be compensated without performing retrainings in relation to a write data strobe signal WDQS. The memory device200may adjust delays on the WDQS path WDQS_P according to temperature changes, which are detected in real time considering characteristics of circuits on the WDQS path WDQS_P. Accordingly, delays on the WDQS path WDQS_P based on trainings performed during the initialization process of the memory device200may be maintained. Therefore, an S/H margin of the data sampler240may increase regardless of temperature changes, and also data errors may be reduced.

FIG.2is a flowchart illustrating an operation example of the memory system ofFIG.1. In particular, the operation of adjusting delays on the WDQS path based on temperature changes, by the memory system10will be explained with reference toFIG.2. With reference toFIGS.1and2, in operation S11, the memory system10may determine a weight. The weight may represent an amount of variations of a delay on the WDQS path according to a temperature change. For example, the memory controller100may determine the weight in the initialization process of the memory device200or in the test process for the memory device200. The determined weight is stored in a register or fuse of the memory device200, and may be set to the memory device200. Embodiments describing the setting of the weight by the memory system10will be further explained in detail with reference toFIGS.3to6.

In operation S12, the memory system10may adjust a delay on the WDQS path according to real time temperature based on the set weight. For example, the memory device200may sense temperature in real time. The memory device200may adjust the delay on the WDQS path based on the sensed temperature. For example, the memory device200may regulate a voltage applied to the WDQS transfer circuit230to adjust the delay, or control delay cells of the WDQS transfer circuit230. The scale of delay to be adjusted may vary depending on the set weight. Accordingly, even when the temperature of the memory device200changes in real time, delays on the WDQS path may remain steady. For example, delays under the initialization state of the memory device200or delays at a reference temperature may be maintained consistently. Embodiments describing the adjusting of delays on the WDQS path by the memory device200will be further explained in detail with reference toFIGS.7to14.

In operation S13, the memory system10may sample a data signal DQ based on a write data strobe signal WDQS with an adjusted delay. For example, write data strobe signal WDQS may be transferred to the data sampler240through the WDQS transfer circuit230. In such case, an arrival timing at which the write data strobe signal WDQS reaches the data sampler240may remain constant regardless of changes in temperature of the memory device200. The data sampler240may sample the data signal DQ based on the write data strobe signal WDQS.

According to the memory system10of the inventive concept, the memory device200may compensate for variations of delays on the WDQS path according to real time temperature changes based on weights set in the initialization process or the test process. For example, delays on the WDQS path may remain constant without retrainings by the memory controller100. As a result, retrainings to compensate for variations of delays on the WDQS path according to temperature changes may not be performed, and thus, resources for retrainings may be reduced.

Hereinafter, embodiments describing the operation of setting weights by the memory system10will be further explained in detail with reference toFIGS.3to6.

FIG.3is a block diagram of the memory system ofFIG.2which is configured to set weights according to an embodiment. With reference toFIG.3, a memory system20may include a memory controller300and a memory device400. The memory controller300and the memory device400may correspond to the memory controller100and the memory device200ofFIG.1, respectively. Accordingly, repeated descriptions thereof are omitted hereinafter.

The memory controller300may include a weight determination circuit310. The weight determination circuit310may control an initialization operation or a test operation of the memory device400. The weight determination circuit310may determine weights in the initialization operation or test operation of the memory device400, and set the determined weights to the memory device400. For example, the weight determination circuit310may be implemented by a processor such as a CPU of the memory controller300, but the inventive concept is not limited thereto.

In example embodiments, the weight determination circuit310may request, from the memory device400, oscillation information regarding a write data strobe signal WDQS at each of two predetermined temperatures. The weight determination circuit310may receive oscillation information regarding the write data strobe signal WDQS from the memory device400. The weight determination circuit310may determine a weight based on oscillation information regarding the write data strobe signal WDQS at two temperatures. The weight determination circuit310may transmit the determined weight to the memory device400. For example, the memory controller300may further include a temperature sensor configured to sense temperature.

The memory device400may include a WDQS transfer circuit410, a data sampler420, a WDQS oscillator430, a counter440, and a storage circuit450. The WDQS transfer circuit410may transfer the write data strobe signal WDQS provided from the memory controller300to the data sampler420. The data sampler420may sample a data signal DQ provided from the memory controller300based on a write data strobe signal WDQS.

The WDQS oscillator430may be a replica of the WDQS transfer circuit410. The WDQS oscillator430may be configured to match the WDQS transfer circuit410. Accordingly, a delay in a signal output from the WDQS oscillator430may be substantially identical to a delay in a write data strobe signal output from the WDQS transfer circuit410. For example, a delay on the WDQS path may be substantially identical to a delay on a replica path. Terms such as “identical,” “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, compositions, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, composition, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, compositions, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

The WDQS oscillator430may generate a replica signal corresponding to the write data strobe signal WDQS. For example, the WDQS oscillator430may operate in response to a command or a control signal from the memory controller300. Because the WDQS oscillator430is a replica of the WDQS transfer circuit410, an oscillation value (e.g., the number of oscillations) of the replica signal may be substantially identical to an oscillation value (e.g., the number of oscillations) of the write data strobe signal WDQS. For example, the WDQS oscillator430may be implemented by a ring oscillator, but the inventive concept is not limited thereto.

The counter440may calculate an oscillator count value for a replica signal output from the WDQS oscillator430. For example, the counter440may count the number of oscillations of the replica signal. The oscillator count value for the replica signal calculated by the counter440may be substantially identical to the number of oscillations of the write data strobe signal WDQS. Accordingly, the oscillator count value calculated by the counter440may correspond to a delay on the WDQS path. The oscillator count value calculated by the counter440may be transmitted to the memory controller300as oscillation information regarding the write data strobe signal WDQS (i.e., delay information on the WDQS path).

The storage circuit450may store weights provided from the memory controller300. In example embodiments, the storage circuit450may be implemented by a register or fuse. For example, when a weight is set in the initialization process of the memory device400, the storage circuit450may be a mode register. For example, when a weight is set in the test process of the memory device400, the storage circuit450may be a test mode register or a fuse.

FIG.4is an exemplary flowchart illustrating the operation of setting a weight by the memory system ofFIG.3. With reference toFIGS.3and4, in operation S301, the memory controller300may determine whether the temperature of the memory system20(i.e. the memory controller300or the memory device400) is a first temperature. For example, the memory controller300may determine through an internal temperature sensor whether the temperature of the memory system20is equal to the first temperature. As another example, the memory device400may include an internal temperature sensor, the memory controller300may request temperature information from the memory device400and receive the temperature information regarding the memory system20from the memory device400. In some embodiments, in operation S301, the memory controller300may determine whether the temperature of the memory system20is equal to or higher than the first temperature. In some embodiments, in operation S301, the memory controller300may determine whether the temperature of the memory system20exceeds the first temperature.

When the temperature of the memory system20is equal to the first temperature, the memory controller300may transmit a WDQS oscillator enable command to the memory device400in operation S303. For example, the memory controller300may transmit a WDQS oscillator enable command to the memory device400through command/address signals CA. However, the inventive concept is not limited thereto, and the memory controller300may transmit a WDQS oscillator enable command to the memory device400through a separate control signal. In some embodiments, when the temperature of the memory system20is equal to or higher than the first temperature, the memory controller300may transmit a WDQS oscillator enable command to the memory device400in operation S303. In some embodiments, when the temperature of the memory system20exceeds the first temperature, the memory controller300may transmit a WDQS oscillator enable command to the memory device400in operation S303.

In operation S305, the memory device400may count the number of oscillations of a write data strobe signal WDQS in response to the WDQS oscillator enable command. For example, the memory device400may enable the WDQS oscillator430and the counter440in response to the WDQS oscillator enable command. Accordingly, the memory device400may count the number of oscillations of the write data strobe signal WDQS by counting the number of oscillations of a replica signal.

In operation S307, the memory controller300may request an oscillator count value from the memory device400. For example, the memory controller300may transmit a command to request an oscillator count value to the memory device400through command/address signals CA. However, the inventive concept is not limited thereto, and the memory controller300may request an oscillator count value from the memory device400through a separate control signal.

In operation S309, the memory device400may transmit the first oscillator count value CNT1to the memory controller300in response to a request from the memory controller300. For example, the first oscillator count value CNT1may be an oscillator count value for the write data strobe signal WDQS at the first temperature. For example, the memory device400may transmit the first oscillator count value CNT1to the memory controller300through the data signal DQ, but the inventive concept is not limited thereto.

In operation S311, the memory controller300may determine whether the temperature of the memory system20is equal to a second temperature. For example, the first temperature may be room temperature (e.g., approximately 20 degrees Celsius), and the second temperature may be a temperature hotter than room temperature. In some embodiments, in operation S311, the memory controller300may determine whether the temperature of the memory system20is equal to or higher than the second temperature. In some embodiments, in operation S311, the memory controller300may determine whether the temperature of the memory system20exceeds the second temperature. When the temperature of the memory system20is equal to the second temperature, the memory controller300may transmit a WDQS oscillator enable command to the memory device400in operation S313. In some embodiments, when the temperature of the memory system20is equal to or higher than the second temperature, the memory controller300may transmit a WDQS oscillator enable command to the memory device400in operation S313. In some embodiments, when the temperature of the memory system20exceeds the second temperature, the memory controller300may transmit a WDQS oscillator enable command to the memory device400in operation S313. In operation S315, the memory device400may count the number of oscillations of the write data strobe signal WDQS in response to a WDQS oscillator enable command. For example, the memory device400may count the number of oscillations of the write data strobe signal WDQS by counting the number of oscillations of replica signals. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range.

In operation S317, the memory controller300may request an oscillator count value from the memory device400. In operation S319, the memory device400may transmit the second oscillator count value CNT2to the memory controller300in response to a request from the memory controller300. For example, the second oscillator count value CNT2may be an oscillator count value for the write data strobe signal WDQS at the second temperature.

In operation S321, the memory controller300may determine a weight based on the first oscillator count value CNT1and the second oscillator count value CNT2. For example, the memory controller300may calculate the weight on the assumption that an oscillator count value for the write data strobe signals WDQS from the first temperature to the second temperature vary in a linear manner. The calculated weight may represent an amount of variations of a delay on the WDQS path according to changes in temperature of the memory system20.

In operation S323, the memory controller300may transmit a weight to the memory device400. For example, the memory controller300may transmit a weight to the memory device400along with a weight set command through a command/address signal CA. For example, the memory controller300may transmit a weight to the memory device400based on a mode register set (MRS) command. As another example, the memory controller300may transmit a weight to the memory device400based on a test mode register set (TMRS) command.

In operation S325, the memory device400may store a weight provided from the memory controller300. For example, the memory device400may store a weight in response to a weight set command (e.g., MRS commands or TMRS commands) from the memory controller300. The weight may be stored in the storage circuit450.

FIG.5is a graph showing an example of variations of delays on the WDQS path according to element characteristics of the memory device ofFIG.3. The horizontal axis of the graph inFIG.5represents a temperature, and the vertical axis represents a delay on the WDQS path. With reference toFIGS.3and5, an amount of variations of delays on the WDQS path according to temperature changes may vary according to element characteristics of the WDQS transfer circuit410. The element characteristics may be assorted by process corners of elements on the WDQS path (e.g., a transistor). For example, the element characteristics may be divided into a slow process corner, a typical process corner, and a fast process corner.

As illustrated inFIG.5, when elements of the WDQS transfer circuit410have a first element characteristic (e.g., when elements of the WDQS transfer circuit410correspond to a slow process corner) and when the temperature of the memory system20increases, a reduction in delays on the WDQS path may occur.

As also illustrated inFIG.5, when elements of the WDQS transfer circuit410have a second element characteristic (e.g., when elements of the WDQS transfer circuit410correspond to a typical process corner) and when the temperature of the memory system20increases, a reduction in delays on the WDQS path may occur. As illustrated inFIG.5, the delay reduction amount corresponding to the second element characteristic may be less than the delay reduction amount corresponding to the first element characteristic.

As further illustrated inFIG.5, when elements of the WDQS transfer circuit410have a third element characteristic (e.g., when elements of the WDQS transfer circuit410correspond to a fast process corner) and when the temperature of the memory system20increases, an increase in delays on the WDQS path may occur.

As described inFIG.5, delays on the WDQS path according to element characteristics of the WDQS transfer circuit410may vary in a linear manner (or approximately in a linear manner) according to temperature changes. Accordingly, weights reflecting element characteristics may be calculated based on delay values on the WDQS path corresponding to two temperatures. For example, a weight may be calculated by a slope of a variation of delays according to temperature changes. Therefore, when the memory device400compensates for variations of delays by using a weight calculated based on delay values at two temperatures, a temperature compensation reflecting element characteristics may be performed.

FIG.6illustrates an example of weight determination by the memory controller ofFIG.3according to the example indicated inFIG.5. In particular,FIG.6illustrates an example of operation determining each of a plurality of different weights according to element characteristics by the memory controller300.

With reference toFIGS.3,5, and6, the memory controller300may calculate weights based on delays corresponding to each of the first temperature T1and the second temperature T2. For example, the memory controller300may receive, as explained with reference toFIG.4, oscillator count values for a write data strobe signal WDQS at the first temperature T1and the second temperature T2, respectively from the memory device400. In this case, the oscillator count values corresponding to each of the first temperature T1and the second temperature T2may correspond to delay values corresponding to the first temperature T1and the second temperature T2, respectively.

When elements of the WDQS transfer circuit410have a first element characteristic, the memory controller300may calculate a first weight WT1based on a first delay D1corresponding to the first temperature T1and a second delay D2corresponding to the second temperature T2. For example, the first weight WT1may represent a slope of a delay variation according to a temperature change under the first element characteristic.

When elements of the WDQS transfer circuit410have a second element characteristic, the memory controller300may calculate a second weight WT2based on a third delay D3corresponding to the first temperature T1and a fourth delay D4corresponding to the second temperature T2. For example, the second weight WT2may represent a slope of a delay variation according to a temperature change under the second element characteristic.

When elements of the WDQS transfer circuit410have a third element characteristic, the memory controller300may calculate a third weight WT3based on a fifth delay D5corresponding to the first temperature T1and a sixth delay D6corresponding to the second temperature T2. For example, the third weight WT3may represent a slope of delay variation according to a temperature change under the third element characteristic.

As described above, the memory controller300may determine weights reflecting element characteristics of the WDQS transfer circuit410based on oscillator count values for write data strobe signals WDQS at two temperatures. The memory controller300may store weights reflecting element characteristics in the memory device400. Accordingly, the memory device400may adjust delays on the WDQS path according to temperature changes by reflecting element characteristics.

Hereinafter, embodiments describing adjustment of delays on the WDQS path by the memory system10will be further explained with reference toFIGS.7to14. In particular, embodiments describing adjustment of delays by changing a voltage applied to delay cells on the WDQS path by means of the voltage regulator and embodiments describing delay adjustment by controlling delay cells on the WDQS path, with reference toFIGS.7to11andFIGS.12to14, respectively.

FIG.7is a block diagram illustrating the memory device configured to adjust delays on the WDQS path according to an embodiment. With reference toFIG.7, the memory device500may correspond to the memory devices200and400described with reference toFIGS.1to6. Accordingly, repeated descriptions thereof are omitted hereinafter.

The memory device500may include a storage circuit510, a temperature sensor520, a temperature compensator530, a reference voltage generator540, a voltage regulator550, a WDQS transfer circuit560, and a data sampler570. The storage circuit510may correspond to the storage circuit450ofFIG.3, and the WDQS transfer circuit560and the data sampler570may correspond to the WDQS transfer circuit230and the data sampler240ofFIG.1, respectively.

The storage circuit510may store weights WT. As described with reference toFIGS.1to6, weights WT may be determined by the memory controllers100and300during the initialization process or the test process. For example, the storage circuit510may be implemented by one of a mode register, a test mode register, and a fuse.

The temperature sensor520may sense the temperature of the memory device500. The temperature sensor520may provide the sensed current temperature TP to the temperature compensator530.

The temperature compensator530may generate a delay code DCODE based on the current temperature TP and the weight WT. The delay code DCODE may correspond to a delay adjustment amount for adjusting delays on the WDQS path. For example, the temperature compensator530may calculate temperature changes based on a predetermined reference temperature and the current temperature TP, and generate a delay code DCODE for adjusting delays based on weights WT. For example, when delays on the WDQS path are adjusted according to a delay code DCODE, the delays on the WDQS path may remain constant regardless of temperature changes.

The reference voltage generator540may generate a reference voltage VREF from the power supply voltage VDDQ based on a delay code DCODE. The reference voltage generator540may generate a reference voltage VREF having a level corresponding to a delay code DCODE. For example, the reference voltage generator540may generate reference voltages VREF having different levels corresponding to each different delay code DCODE.

The voltage regulator550may generate a regulated voltage VLDO based on a reference voltage VREF. For example, the voltage regulator550may generate a regulated voltage VLDO having a level lower than that of a reference voltage VREF. The regulated voltage VLDO output from the voltage regulator550may be provided to the WDQS transfer circuit560.

The WDQS transfer circuit560may transfer write data strobe signals WDQS to the data sampler570. The WDQS transfer circuit560may transfer write data strobe signals WDQS to the data sampler570by using the power supply voltage VDDQ and the regulated voltage VLDO. For example, some of the repeaters (or inverters) of the WDQS transfer circuit560may operate by using the power supply voltage VDDQ, and the others may operate by using the regulated voltage VLDO. In this case, delays of write data strobe signals WDQS transferred through the repeaters operated by using the regulated voltage VLDO may be controlled according to a level of the regulated voltage VLDO.

The data sampler570may sample a data signal DQ based on a write data strobe signal WDQS. When delays on the WDQS path are adjusted based on a regulated voltage VLDO, an S/H margin of the data sampler570may increase regardless of the temperature. Accordingly, an error rate of data output from the data sampler570may decrease.

As described above, the memory device500may control a level of regulated voltages VLDO applied to the WDQS transfer circuit560through the voltage regulator550based on pre-stored weights WT and current temperature TP. Accordingly, the memory device500may adjust delays on the WDQS path according to a temperature sensed in real time without retrainings by the memory controllers100and300.

FIG.8illustrates an example operation of the temperature compensator ofFIG.7. With reference toFIGS.7and8, the temperature compensator530may calculate temperature changes by comparing the current temperature TP with a reference temperature TREF. For example, a reference temperature TREF may be stored in advance in the temperature compensator530.

The temperature compensator530may generate delay codes DCODE corresponding to weights WT based on temperature changes. For example, different delay codes DCODE may be generated according to the same temperature changes depending on weights WT. As illustrated inFIG.8, the temperature compensator530may generate a first delay code DCODE1corresponding to a first weight WT1, a second delay code DCODE2corresponding to a second weight WT2, and a third delay code DCODE3corresponding to a third weight WT3. As explained with reference toFIG.6, weights reflect element characteristics of the WDQS transfer circuit560, and thus, delay codes DCODE generated by the temperature compensator530may reflect element characteristics.

FIG.9illustrates an example operation of the reference voltage generator and the voltage regulator ofFIG.7. With reference toFIGS.7and9, the reference voltage generator540may generate a reference voltage VREF corresponding to a delay code DCODE. For example, as illustrated inFIG.9, the reference voltage generator540may generate first to third reference voltages VREF1to VREF3corresponding to first to third delay codes DCODE1to DCODE3, respectively.

The voltage regulator550may generate a regulated voltage VLDO corresponding to a reference voltage VREF. For example, as illustrated inFIG.9, the voltage regulator550may generate first to third regulated voltages VLDO1to VLDO3corresponding to first to third reference voltages VREF1to VREF3, respectively.

As described above, delay codes DCODE reflect element characteristics of the WDQS transfer circuit560, and thus, regulated voltages VLDO generated by the voltage regulator550may reflect the element characteristics. Accordingly, the memory device500may adjust delays on the WDQS path based on a regulated voltage VLDO having a level reflecting element characteristics.

FIG.10is an exemplary circuit diagram of the voltage regulator and the WDQS transfer circuit ofFIG.7. With reference toFIGS.7and10, the voltage regulator550may include an amplifier AMP, a transistor TR, a first resistor R1, and a second resistor R2. A reference voltage VREF may be input to a first input terminal of the amplifier AMP, and a feedback voltage VFDB may be input to a second input terminal thereof. The amplifier AMP may output a result of comparison between a reference voltage VREF and a feedback voltage VFDB to a gate terminal of the transistor TR. For example, according to the comparison result, the transistor TR may be turned on or turned off. Depending on the on/off state of the transistor TR, a voltage of an output node nd (i.e., a regulated voltage VLDO) may be controlled based on the power supply voltage VDDQ and the ground voltage VSS. When the transistor TR is turned on, the voltage of the output node nd may be increased by the power supply voltage VDDQ. As such, when the voltage of the output node nd is controlled, the level of the regulated voltage VLDO output from the output node nd may remain constant.

The WDQS transfer circuit560may include an inverter INV. The inverter INV may output delayed write data strobe signals rWDQS by delaying the write data strobe signals WDQS. Delays of write data strobe signals WDQS by the inverter INV may be controlled according to the regulated voltage VLDO. For example, when the regulated voltage VLDO increases, delays of write data strobe signals WDQS may be reduced. Accordingly, delays on the WDQS path may be adjusted based on the regulated voltage VLDO.

InFIG.10, the WDQS transfer circuit560is described as including a single inverter INV to transfer write data strobe signals WDQS to the data sampler570; however, the inventive concept is not limited thereto. For example, the WDQS transfer circuit560may include multiple inverters operating based on the regulated voltage VLDO. Alternatively, the WDQS transfer circuit560may further include at least one inverter operating based on the power supply voltage VDDQ.

FIG.11is an exemplary flowchart illustrating the operation of delay adjustment by the memory device ofFIG.7. With reference toFIGS.7and11, in operation S501, the memory device500may sense the temperature. For example, the memory device500may sense the temperature of the memory device500in real time through the temperature sensor520.

In operation S502, the memory device500may generate delay codes based on the sensed temperatures and weights. For example, the memory device500may calculate temperature changes by comparing a predetermined reference temperature and the sensed temperatures. The memory device500may generate delay codes corresponding to weights based on temperature changes. For example, delay codes may be generated differently according to temperature changes and weights.

In operation S503, the memory device500may control the regulated voltage applied to the WDQS transfer circuit560based on delay codes. The memory device500may adjust delays on the WDQS path by controlling the regulated voltage. For example, the memory device500may generate a reference voltage corresponding to a delay code, from the power supply voltage. The memory device500may generate a regulated voltage corresponding to a reference voltage. The WDQS transfer circuit560may transfer a write data strobe signal WDQS to the data sampler570based on the regulated voltage. The transfer timing of write data strobe signal WDQS may vary depending on the regulated voltage. Accordingly, delays on the WDQS path may be adjusted.

As described above, the memory device500according to an embodiment may adjust delays on the WDQS path by controlling, through the voltage regulator550, the level of regulated voltages applied to the circuits on the WDQS path.

FIG.12is a block diagram illustrating the memory device configured to adjust delays on the WDQS circuit according to an embodiment. With reference toFIG.12, the memory device600may correspond to the memory devices200and400described with reference toFIGS.1to6. Accordingly, repeated descriptions thereof are omitted hereinafter.

The memory device600may include a storage circuit610, a temperature sensor620, a temperature compensator630, a WDQS transfer circuit640, and a data sampler650. The storage circuit610, temperature sensor620, and temperature compensator630may correspond to the storage circuit510, temperature sensor520, and temperature compensator530ofFIG.7, respectively. The WDQS transfer circuit640and the data sampler650may correspond to the WDQS transfer circuit230and the data sampler240ofFIG.1, respectively. Accordingly, repeated descriptions thereof are omitted hereinafter.

The temperature compensator630may generate delay codes DCODE based on the weights WT from the storage circuit610and the current temperature TP from the temperature sensor620. For example, as described with reference toFIG.8, the temperature compensator630may generate delay codes DCODE corresponding to weights WT based on temperature changes. The temperature compensator630may control delay cells of the WDQS transfer circuit640based on delay codes DCODE.

The WDQS transfer circuit640may transfer write data strobe signal WDQS to the data sampler650. For example, the WDQS transfer circuit640may include delay cells (e.g. repeaters or inverters) for transferring write data strobe signal WDQS. The delay cells of the WDQS transfer circuit640may operate by using the power supply voltage VDDQ.

At least one delay cell of the WDQS transfer circuit640may be controlled based on delay codes DCODE. For example, an on/off state of transistors of delay cells may be controlled based on delay codes DCODE. Delays of the delay cells may be adjusted based on the on/off state of the transistors. Accordingly, delays of write data strobe signal WDQS output through the WDQS transfer circuit640may be adjusted according to delay codes DCODE.

The data sampler650may sample the data signal DQ based on the write data strobe signal WDQS. When delays on the WDQS path are adjusted by controlling delay cells, an S/H margin of the data sampler650may increase regardless of temperature changes. As a result, an error rate of data output from the data sampler650may decrease.

As described above, the memory device600does not include the voltage regulator550of the memory device500ofFIG.7, and therefore may adjust delays of write data strobe signal WDQS by controlling directly delay cells of the WDQS transfer circuit640. Accordingly, the memory device600may adjust delays on the WDQS path according to a temperature sensed in real time without retrainings by the memory controllers100and300.

FIGS.13A and13Bare illustrative circuit diagrams of the WDQS transfer circuit ofFIG.12. In particular, each ofFIGS.13A and13Billustrates a delay cell of the WDQS transfer circuit640. However, the inventive concept is not limited thereto, and the WDQS transfer circuit640may include a plurality of delay cells.

With reference toFIG.13A, the WDQS transfer circuit640amay include an inverter INVa, PMOS transistors PM1to PMn, and NMOS transistors NM1to NMn. For example, sizes of each PMOS transistor PM1to PMn may differ, and sizes of each NMOS transistor NM1to NMn may differ as well. However, the inventive concept is not limited thereto.

The inverter INVa may output delayed write data strobe signal rWDQS by delaying the write data strobe signal WDQS. Delays of write data strobe signal WDQS by the inverter INVa may be adjusted according to a first enable voltage VEN1and a second enable voltage VEN2. For example, when a voltage difference between the first enable voltage VEN1and the second enable voltage VEN2increases, delays of write data strobe signal WDQS may be reduced.

The first enable voltage VEN1may be controlled based on enable signals ES11to ES1nwhich control the on/off state of the PMOS transistors PM1to PMn. The second enable voltage VEN2may be controlled based on enable signals ES21to ES2nwhich control the on/off state of the NMOS transistors NM1to NMn. For example, the enable signals ES11to ES1nand the enable signals ES21to ES2nmay be in a complementary relation. In this case, the PMOS transistors PM1to PMn and the NMOS transistors NM1to NMn may operate in a symmetrical manner. For example, when the first PMOS transistor PM1is turned on, the first NMOS transistor NM1may be turned on.

The enable signals ES11to ES1nmay be generated based on delay codes DCODE. In example embodiments, delay codes DCODE may be used as the enable signals ES11to ES1nor the enable signals ES21to ES2n. For example, when delay codes DCODES are used as enable signals ES11to ES1n, the on/off state of PMOS transistors PM1to PMn may be controlled by the bits of the delay codes DCODE. In this case, the on/off state of NMOS transistors NM1to NMn may be controlled based on the complementary bits of the delay codes DCODE.

For example, when PMOS transistors PM1to PMn and NMOS transistors NM1to NMn in turn-on state are increased based on delay codes DCODE, the first enable voltage VEN1may be increased by the power supply voltage VDDQ and the second enable voltage VEN2may be decreased by the ground voltage VSS. Accordingly, delays of write data strobe signal WDQS by the inverter INVa may be reduced.

With reference toFIG.13B, a WDQS transfer circuit640bmay include an inverter INVb and transistors MO1to MOn. For example, each of the transistors MO1to MOn may be an NMOS transistor.

The inverter INVb may operate based on the power supply voltage VDDQ and the ground voltage VSS. The inverter INVb may output delayed write data strobe signal rWDQS by delaying the write data strobe signal WDQS. Delays of write data strobe signal WDQS by the inverter INVb may be adjusted according to loading by capacitors CP1to CPn connected to the output terminal of the inverter INVb. For example, when the loading by the capacitors CP1to CPn increases, delays of write data strobe signal WDQS may increase as well.

The loading by the capacitors CP1to CPn may be controlled based on enable signals ES31to ES3n, which control the on/off state of transistors MO1to MOn. For example, when the number of transistors MO1to MOn in turn-on state increases, the loading by the capacitors CP1to CPn may increase as well. Accordingly, delays of write data strobe signal WDQS by the inverter INVb may be increased.

The enable signals ES31to ES3nmay be generated based on delay codes DCODE. In example embodiments, delay codes DCODE may be used as enable signals ES31to ES3n. For example, when delay codes DCODE are used as enable signals ES31to ES3n, the on/off state of the transistors MO1to MOn may be controlled by the bits of the delay codes DCODE.

As described above, the transistors of delay cells of the WDQS transfer circuit640may be controlled based on delay codes DCODE. Accordingly, delays on the WDQS path may be adjusted based on the on/off state of the transistors of delay cells.

FIG.14is an exemplary flowchart illustrating the operation of delay adjustment by the memory device ofFIG.12. With reference toFIGS.12and14, in operation S601, the memory device600may sense the temperature. For example, the memory device600may sense the temperature of the memory device600in real time through the temperature sensor620.

In operation S602, the memory device600may generate delay codes based on the sensed temperatures and weights. For example, the memory device600may calculate temperature changes by comparing a predetermined reference temperature to sensed temperatures. The memory device600may generate delay codes corresponding to weights based on temperature changes.

In operation S603, the memory device600may control delay cells of the WDQS transfer circuit640based on delay codes. For example, as explained with reference toFIGS.13A and13B, the memory device600may control on/off states of transistors of delay cells based on delay codes. The memory device600may control enable voltages applied to the inverters of delay cells by controlling on/off states of the transistors. Alternatively, the memory device600may control the loading of the capacitors of delay cells by controlling on/off states of the transistors. Accordingly, delays of write data strobe signal WDQS through delay cells are adjusted, and delays on the WDQS path may be adjusted.

As described above, the memory device600according to an embodiment may adjust delays on the WDQS path without a voltage regulator by controlling the transistors of delay cells of the WDQS transfer circuit640.

FIG.15is a block diagram of the stacked memory device according to embodiments. With reference toFIG.15, a stacked memory device700may correspond to the memory devices200,400,500, and600described with reference toFIGS.1to14. The stacked memory device700may include a buffer die710and a plurality of core dies720to750. For example, the buffer die710may be referred to as an interface die, a base die, a logic die, a master die, etc., and each of the core dies720to750may be referred to as a memory die, a slave die, etc. InFIG.15, the stacked memory device700is described as including four core dies720to750; however, the number of core dies may be changed variously. For example, the stacked memory device700may include eight, twelve or sixteen core dies.

The buffer die710and the core dies720to750may be stacked and electrically connected by through silicon vias (TSVs). Accordingly, the stacked memory device700may have a three-dimensional memory structure in which multiple dies710to750are stacked. For example, the stacked memory device700may be implemented based on high bandwidth memory (HBM) or hybrid memory cube (HMC) standards.

The stacked memory device700may support multiple functionally independent channels (or vaults). For example, as illustrated inFIG.15, the stacked memory device700may support sixteen channels CH0to CH15. When each of the channels CH0to CH15supports 64 data transfer paths (i.e., when there are 64 data signal DQ pins corresponding to each of the channels CH0to CH15), the stacked memory device700including the16channels CH0to CH15may support 1,024 data transfer paths. However, the inventive concept is not limited thereto. The stacked memory device700may support 1,024 or more data transfer paths and various numbers of channels (e.g. eight channels). For example, when the stacked memory device700supports eight channels, and each of the channels supports 128 data transfer paths, the stacked memory device700may support 1,024 data transfer paths.

Each of the core dies720to750may support at least one channel. For example, as illustrated inFIG.15, each of the core dies720to750may support four channels CH0to CH3, CH4to CH7, CH8to CH11, CH12to CH15. In such case, the core dies720to750may each support different channels. However, the inventive concept is not limited thereto, and at least two of the core dies may support the same channel. For example, when the stacked memory device700includes eight core dies, one of the four core dies constituting a stack and one of the other four core dies constituting another stack may support the same channel. In this case, the core dies that support the same channel may be differentiated by a stack ID (SID).

Each of the channels may configure an independent command and data interface. For example, each channel may be independently clocked based on an independent timing requirement, or may not be synchronized with each other.

Each of the channels may include a plurality of memory banks701. Each of the memory banks701may include memory cells, a sense amplifier, etc. connected to word lines and bit lines. For example, each of the channels CH0to CH15may include 32 memory banks701. However, the inventive concept is not limited thereto, and each of the channels CH0to CH15may include eight or more memory banks701. InFIG.15, it is described that the memory banks701included in one channel are included in one core die; however, the memory banks701included in one channel may be dispersed into a plurality of core dies. For example, when two of the core dies support the first channel CH0, the memory banks701of the first channel CH0may be dispersed into two core dies.

In example embodiments, one channel may be divided into two pseudo channels which operate independently. For example, the pseudo channels may share commands and clock inputs (e.g. a clock signal CK, and/or a clock enable signal CKE) of the channel, but they also may independently decode and execute commands. For example, when one channel supports 64 data transfer paths, each of pseudo channels may support 32 data transfer paths. For example, when one channel includes 32 memory banks701, each pseudo channel may include 16 memory banks701.

The buffer die710and the core dies720to750may include a TSV area702. TSVs configured to penetrate the dies710to750may be located in the TSV area702. The buffer die710may transmit and receive various signals with the core dies720to750through the TSVs. Each of the core dies720to750may transmit and receive signals with the buffer die710and other core dies through the TSVs. In this case, the signals may be transmitted and received independently through the TSVs corresponding to each channel. For example, when an external host device (e.g. the memory controller100ofFIG.1) transmits a data signal to the first channel CH0to store data in the memory cell of the first channel CH0, the buffer die710may transmit a data signal to the first core die720through TSVs corresponding to the first channel CH0. In this manner, the data may be stored in the memory cell of the first channel CH0.

In example embodiments, the power supply voltage VDDQL may be used for transmission of signals through TSVs. The power supply voltage VDDQL may be less than the power supply voltage VDDQ used for overall operation of the buffer die710. For example, the power supply voltage VDDQ may be 1.1 V when the power supply voltage VDDQL is 0.4 V.

The buffer die710may include a physical layer PHY711. The physical layer711may include interface circuits to communicate with an external host device. In example embodiments, the physical layer711may include interface circuits corresponding to each of the channels CH0to CH15. For example, an interface circuit corresponding to one channel may include components210to240of the memory device200ofFIG.1. Signals received from the host device through the physical layer711may be transmitted to the core dies720to750through the TSVs.

In example embodiments, the buffer die710may include a channel controller corresponding to each of the channels. The channel controller may manage memory reference operations of a corresponding channel, and determine timing requirements of the corresponding channel.

In example embodiments, the buffer die710may include a plurality of pins configured to receive signals from an external host device. As described with reference toFIG.1, the buffer die710may receive a clock signal CK, a command/address signal CA, a write data strobe signal WDQS and a data signal DQ, and transmit a data signal DQ through a plurality of pins.

In example embodiments, the stacked memory device700may further include an error correction code (ECC) circuit for detecting and correcting data errors. For example, in a write operation, the ECC circuit may generate parity bits for data transferred from the host device. In a read operation, the ECC circuit may detect and correct errors in data transferred from one of the core dies720to750by using parity bits, and transmit to the host device the data whose errors have been corrected.

In example embodiments, the stacked memory device700may store weights to compensate for variations of delays on the WDQS path according to temperature changes, as described with reference toFIGS.1to14. For example, weights may be determined in the initialization process or test process of the stacked memory device700. The stacked memory device700may adjust delays on the WDQS path according to real time temperatures based on the stored weights. As a result, even when the temperature of the stacked memory device700changes, the stacked memory device700may maintain constant delays on the WDQS path without retrainings by the host device. Therefore, an S/H margin for sampling a data signal DQ may increase regardless of temperature changes.

FIG.16is a block diagram of the buffer die ofFIG.15. With reference toFIG.16, the buffer die710may support the first channel CHa and the second channel CHb. The buffer die710may include, corresponding to the first channel CHa, a first storage circuit712a, a first temperature sensor713a, a first temperature compensator714a, a first reference voltage generator715a, a first voltage regulator716a, a first WDQS divider717a, a first WDQS tree circuitry718a, and a first receiver719a. The buffer die710may include a first write data strobe pin W_P1and a first data pin D_P1to receive the first write data strobe signal WDQS1and the first data signal DQ1provided to the first channel CHa.

The buffer die710may include, corresponding to the second channel CHb, a second storage circuit712b, a second temperature sensor713b, a second temperature compensator714b, a second reference voltage generator715b, a second voltage regulator716b, a second WDQS divider717b, a second WDQS tree circuitry718b, and a second receiver719b. The buffer die710may include a second write data strobe pin W_P2and a second data pin D_P2to receive the second write data strobe signal WDQS2and the second data signal DQ2provided to the second channel CHb.

The components712bto719band the pins W_P2, D_P2corresponding to the second channel CHb may correspond to the components712ato719aand the pins W_P1, D_P1corresponding to the first channel CHa, respectively. Accordingly, hereinafter, the buffer die710will be described focusing on the components712ato719aand the pins W_P1, D_P1of the first channel CHa for the sake of convenient explanation.

The first storage circuit712a, the first temperature sensor713a, the first temperature compensator714a, the first reference voltage generator715a, and the first voltage regulator716amay correspond to the storage circuit510, the temperature sensor520, the temperature compensator530, the reference voltage generator540, and the voltage regulator550ofFIG.7, respectively. The first WDQS divider717aand the first WDQS tree circuitry718amay correspond to the WDQS transfer circuit560ofFIG.7, and the first receiver719amay correspond to the data sampler570ofFIG.7. Accordingly, repeated descriptions thereof are omitted hereinafter.

The first storage circuit712amay store a first weight WT1corresponding to the first channel CHa. The first weight WT1may be determined in the initialization process or test process for the first channel CHa. The first temperature sensor713amay be a temperature sensor located adjacent to interface circuits corresponding to the first channel CHa (e.g. the first WDQS divider717a, the first WDQS tree circuitry718a, and the first receiver719a). The first current temperature TP1sensed by the first temperature sensor713amay be provided to the first temperature compensator714a.

The first temperature compensator714amay generate a first delay code DCODE1based on the first weight WT1and the first current temperature TP1. The first reference voltage generator715amay generate a first reference voltage VREF1based on the first delay code DCODE1, and the first voltage regulator716amay generate a first regulated voltage VLDO1based on the first reference voltage VREF1.

The first WDQS divider717amay generate first internal write data strobe signals dWDQS1based on the first write data strobe signals WDQS1. For example, the first WDQS divider717amay divide the first write data strobe signal WDQS1and generate first internal write data strobe signal dWDQS1having different phases. In this case, the frequency of each first internal write data strobe signal dWDQS1may be less than the frequency of the first write data strobe signal WDQS1. In example embodiments, a separate receiver (or a buffer) configured to receive first write data strobe signal WDQS1may be arranged between the first WDQS divider717aand the first write data strobe pin W_P1.

The first WDQS tree circuitry718amay transfer the first internal write data strobe signal dWDQS1to the first receiver719athrough a plurality of repeaters (or inverters). In example embodiments, the first WDQS tree circuitry718amay transfer the first internal write data strobe signal dWDQS1based on the first regulated voltage VLDO1. For example, the first WDQS tree circuitry718amay include an inverter which operates based on the first regulated voltage VLDO1. When the first regulated voltage VLDO1is controlled according to the first delay code DCODE1, delays of each first internal write data strobe signal dWDQS1transferred through the first WDQS tree circuitry718amay be adjusted. Accordingly, the first WDQS tree circuitry718amay transfer the first internal write data strobe signal rWDQS1with adjusted delays to the first receiver719a.

The first receiver719amay sample the first data signal DQ1based on the first internal write data strobe signal rWDQS1. For example, the first receiver719amay sample the first data signal DQ1at a rising edge or falling edge timing of each first internal write data strobe signal rWDQS1.

As described above, the first regulated voltage VLDO1may be controlled based on the first weight WT1and the first current temperature TP1, and delays on a path through which the first write data strobe signal WDQS1is transferred to the first receiver719amay be adjusted based on the first regulated voltage VLDO1.

Similarly, the second regulated voltage VLDO2may be controlled based on the second weight WT2and the second current temperature TP2, and delays on a path through which the second write data strobe signal WDQS2is transferred to the second receiver719bmay be adjusted based on the second regulated voltage VLDO2.

The second weight WT2for controlling the second regulated voltage VLDO2may be determined in the initialization process or the test process for the second channel CHb. For example, the second weight WT2may be different from the first weight WT1. The second current temperature TP2for controlling the second regulated voltage VLDO2may be sensed by the second temperature sensor713blocated adjacent to interface circuits corresponding to the second channel CHb (e.g. the second WDQS divider717b, the second WDQS tree circuitry718b, and the second receiver719b). For example, the second current temperature TP2may be different from the first current temperature TP1. Accordingly, the second regulated voltage VLDO2may be different from the first regulated voltage VLDO1, and delays on the WDQS path adjusted based on the second regulated voltage VLDO2may be different from delays on the WDQS path adjusted based on the first regulated voltage VLDO1.

As described above, when the buffer die710supports a plurality of channels CHa, CHb, the buffer die710may independently adjust delays on the WDQS path corresponding to each of the channels CHa, CHb. Accordingly, even when characteristics of the elements on the WDQS path corresponding to the first channel CHa are different from those of the elements on the WDQS path corresponding to the second channel CHb, variations of delays on the WDQS path corresponding to each of the channels CHa, CHb can be compensated. Therefore, S/H margins for sampling a data signal in each channel may increase.

FIG.16illustrates embodiments in which the buffer die710adjusts delays on the WDQS path through the voltage regulators716a,716b, as explained with reference toFIGS.7to11; however, the inventive concept is not limited thereto. For example, the buffer die710may adjust delays by controlling the transistors of the delay cells of the WDQS tree circuitries718aand718b, as described with reference toFIGS.12to14.

FIG.17is an illustrative diagram of a semiconductor package according to an embodiment. With reference toFIG.17, the semiconductor package1000may include a stacked memory device1100, a System-on-Chip1200, an interposer1300, and a package substrate1400. The stacked memory device1100may include a buffer die1110and core dies1120to1150. The stacked memory device1100may correspond to the stacked memory device700described with reference toFIG.15.

Each of the core dies1120to1150may include memory cells for storing data. The buffer die1110may include a physical layer1111and a direct access area DAB1112. The physical layer1111may be electrically connected with the physical layer1210of the System-on-Chip1200through the interposer1300. The stacked memory device1100may receive signals from the System-on-Chip1200through the physical layer1111, or transmit signals to the System-on-Chip1200. The physical layer1111may include components of the buffer die710described with reference toFIGS.15and16.

The direct access area1112may provide an access path which enables testing of the stacked memory device1100without it being processed through the System-on-Chip1200. The direct access area1112may include a conductive means (e.g. a port or pin) capable of direct communication with an external test device. The test signals received through the direct access area1112may be transmitted to the core dies1120to1150through the TSVs. The data read from the core dies1120to1150may be transmitted to a test device through the TSVs and the direct access area1112for testing of the core dies1120to1150. In this manner, direct access tests may be performed in relation to the core dies1120to1150.

The buffer die1110and the core dies1120to1150may be electrically connected to each other via the TSVs1101and bumps1102. The buffer die1110may receive signals provided to each channel through the bumps1102allocated per channel from the System-on-Chip1200, or transmit the signals to the System-on-Chip1200through the bumps1102. For example, the bumps1102may be microbumps.

The System-on-Chip1200may execute applications supported by the semiconductor package1000by using the stacked memory device1100. For example, the System-on-Chip1200may include at least one of a central processing unit (CPU), application processor (AU), graphic processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), vision processing unit (VPU), image signal processor (ISP), and digital signal processor (DSP) to execute specialized operations.

The System-on-Chip1200may control overall operations of the stacked memory device1100. The System-on-Chip1200may correspond to the memory controllers100and300described above. The System-on-Chip1200may include the physical layer1210. The physical layer1210may include an interface circuit for transmitting and receiving signals with the physical layer1111of the stacked memory device1100. For example, the physical layer1210may include components of the memory controller100ofFIG.1. The System-on-Chip1200may provide various signals to the physical layer1111through the physical layer1210. The signals provided to the physical layer1111may be transferred to the core dies1120to1150through the interface circuit of the physical layer1111and the TSVs1101.

The interposer1300may connect the stacked memory device1100and the System-on-Chip1200. The interposer1300may connect the physical layer1111of the stacked memory device1100and the physical layer1210of the System-on-Chip1200, and provide physical paths formed by using conductive materials. Accordingly, the stacked memory device1100and the System-on-Chip1200may be stacked over the interposer1300to transmit and receive signals from each other.

The bumps1103may be attached to the top of the package substrate1400, and solder balls1104may be attached to the bottom of the package substrate1400. For example, the bumps1103may be flip chip bumps. The interposer1300may be stacked over the package substrate1400by the bumps1103. The semiconductor package1000may transmit and receive signals with other external packages or semiconductor devices through the solder balls1104. For example, the package substrate1400may be a printed circuit board (PCB).

In example embodiments, the physical layer1111of the buffer die1110may receive a write data strobe signal WDQS and a data signal DQ from the System-on-Chip1200through the bumps1102. The physical layer1111may sample a data signal DQ based on a write data strobe signal WDQS with adjusted delays, as described with reference toFIGS.1to16.

FIG.18is a diagram illustrating an implementation example of the semiconductor package according to an embodiment. With reference toFIG.18, the semiconductor package2000may include a plurality of stacked memory devices2100and the System-on-Chip2200. Each of the stacked memory devices2100may correspond to the stacked memory device1100ofFIG.17, and the System-on-Chip2200may correspond to the System-on-Chip1200ofFIG.17. The stacked memory devices2100and the System-on-Chip2200may be stacked over the interposer2300, and the interposer2300may be stacked over the package substrate2400. The semiconductor package2000may transmit and receive signals with other external packages or semiconductor devices through the solder balls2001attached to the bottom of the package substrate2400.

Each of the stacked memory devices2100may be implemented based on the HBM standard. However, the inventive concept is not limited thereto, and each of the stacked memory devices2100may be implemented based on the graphics double data rate (GDDR), HMC, or Wide input/output (I/O) standards.

The System-on-Chip2200may include at least one processor such as a CPU, AP, GPU, NPU, etc. and multiple memory controllers to control a plurality of stacked memory devices2100. The System-on-Chip2200may transmit and receive signals with corresponding stacked memory devices through memory controllers.

FIG.19is a diagram illustrating the semiconductor package according to another embodiment. With reference toFIG.19, the semiconductor package3000may include a stacked memory device3100, a host die3200, and a package substrate3300. The stacked memory device3100may include a buffer die3110and core dies3120to3150. The buffer die3110may include a physical layer3111configured to communicate with a host die3200, and each of the core dies3120to3150may include memory cells for storing data. The stacked memory device3100may correspond to the stacked memory device700described with reference toFIGS.15and16.

The host die3200may include a physical layer3210configured to communicate with the stacked memory device3100. The physical layer3111and the physical layer3210may communicate via the TSVs3001. The host die3200may correspond to the memory controllers100and300described above. The physical layer3111may include components of the memory device described with reference toFIGS.1to16. The host die3200may include a processor configured to control overall operations of the semiconductor package3000and to execute applications supported by the semiconductor package3000. For example, the host die3200may include at least one processor such as a CPU, AP, GPU, NPU, etc.

The stacked memory device3100may be located over the host die3200based on the TSVs3001to be stacked vertically on the host die3200. Accordingly, the buffer die3110, the core dies3120to3150, and the host die3200may be electrically connected to each other without an interposer through the TSVs3001and the bumps3002. For example, the bumps3002may be microbumps.

The bumps3003may be attached to the top of the package substrate3300, and the solder balls3004may be attached to the bottom of the package substrate3300. For example, the bumps3003may be flip chip bumps. The host die3200may be stacked over the package substrate3300by the bumps3003. The semiconductor package3000may transmit and receive signals with other external packages or semiconductor devices through the solder balls3004.

In example embodiments, the physical layer3111of the buffer die3110may receive a write data strobe signal WDQS and a data signal DQ from the host die3200through the TSVs3001. The physical layer3111may sample a data signal DQ based on a write data strobe signal WDQS with adjusted delays, as described with reference toFIGS.1to16.

In another embodiment, the stacked memory device3100may be implemented by only core dies3120to3150without a buffer die3110. In such case, each of the core dies3120to3150may further include an interface circuit configured to communicate with the host die3200. On this occasion, each of the core dies3120to3150may transmit and receive signals with the physical layer3210of the host die3200through the TSVs3001.