Input buffer circuit

An input buffer circuit comprised of MOS transistors includes an input terminal for receiving a tri-state input signal capable of taking any one of three potential levels, such as V.sub.pp, V.sub.cc and V.sub.ss. The input buffer circuit also includes a first detecting circuit having a first threshold level located between V.sub.pp and V.sub.cc and a second detecting circuit having a second threshold level located between V.sub.cc and V.sub.ss. Also provided is a third detecting circuit connected to the first and second detecting circuits to determine the level of the input signal applied to the input terminal.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention generally relates to an input buffer circuit which is 
provided at the input section of a digital circuit, and, in particular, to 
such an input buffer circuit comprised of MOSFETs. 
2. Description of the Prior Art 
In digital circuits such as programmable logic arrays (PLAs), programmable 
array logics (s) and programmable read only memories (PROMs), in 
addition to a two-level signal having low and high states, it is often 
required to use a signal of higher level, for example, for programming. In 
a circuit requiring an input signal of three or more levels, the number of 
input pins, when manufactured as a semiconductor device, is required to be 
increased corresponding to the number of levels of input signal. For this 
reason, the resulting device tends to become larger in size and higher in 
cost. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, there is provided an input buffer 
circuit having an input terminal to which a tri-level input signal having 
first, second and third levels, which become lower in level in the order 
mentioned, may be applied. The present input buffer circuit comprises 
first level detecting means having a first threshold which is between said 
first and second levels of said input signal, second level detecting means 
having a second threshold which is between said second and third levels of 
said input signal and determining means connected to said first and second 
level detecting means to determine the level of said input signal. 
It is therefore a primary object of the present invention to obviate the 
disadvantages of the prior art as described above and to provide an 
improved input buffer circuit. 
Another object of the present invention is to provide an input buffer 
circuit suitable for manufacture as a semiconductor device, which can be 
manufactured with ease at low cost. 
A further object of the present invention is to provide an input buffer 
circuit having an input terminal to which a tri-level signal can be 
applied. 
Other objects, advantages and novel features of the present invention will 
become apparent from the following detailed description of the invention 
when considered in conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to FIG. 1, there is shown an input buffer circuit constructed 
in accordance with one embodiment of the present invention employing 
MOSFETs. As shown, the circuit includes an input terminal 1 to which a 
tri-level input signal is applied. In the illustrated embodiment, such a 
tri-level input signal may take any one of the three levels including a 
high level V.sub.pp, an intermediate level V.sub.cc and a low level 
V.sub.ss. As is obvious for one skilled in the art, it may be easily 
understood that V.sub.ss indicates ground level and V.sub.cc indicates 
supply voltage level with V.sub.pp indicating programming voltage level. 
The input buffer circuit of FIG. 1 also comprises a first level detecting 
circuit 2 which has a threshold level which is lower than V.sub.pp but 
higher than V.sub.cc . In the embodiment of FIG. 1, the first level 
detecting circuit 2 includes a P-channel MOS transistor Q.sub.l and an 
N-channel MOS transistor Q.sub.2, which are connected in a CMOS structure. 
The NMOS transistor Q.sub.2 has an ON-resistance which is much larger than 
the ON-resistance of the PMOS transistor Q.sub.l. The PMOS transistor 
Q.sub.1 has its source connected to the source of a depletion type NMOS 
transistor Q.sub.3 and its drain connected to the drain of NMOS transistor 
Q.sub.2 whose source is grounded. The MOS transistors Q.sub.1, Q.sub.2 and 
Q.sub.3 have their gates commonly connected and also connected to supply 
voltage V.sub.cc, intermediate in level. The drain of depletion type NMOS 
transistor Q.sub.3 defines an input to the first level detecting circuit 2 
and it is connected to the input terminal 1 of the present input buffer 
circuit. The interconnection A between the transistors Q.sub.1 and Q.sub.2 
defines an output of the first level detecting circuit 2. 
The input buffer circuit of FIG. 1 also includes a second level detecting 
circuit 3 which is basically a CMOS inverter comprised of a P-channel MOS 
transistor Q.sub.4 and an N-channel MOS transistor Q.sub.5. Thus, the PMOS 
transistor Q.sub.4 has its source connected to supply voltage V.sub.cc and 
its drain connected to the drain of NMOS transistor Q.sub.5 whose source 
is grounded. Both of the transistors Q.sub.4 and Q.sub.5 have their gates 
commonly connected and also connected to the input terminal 1 to which a 
tri-level signal is applied. The interconnection between the two 
transistors Q.sub.4 and Q.sub.5 defines an output of the second level 
detecting circuit. 
Also provided is a 2-input NAND gate 5 which has its one input connected to 
receive an output signal from the first level detecting circuit 2 and the 
other input connected to receive an output signal from the second level 
detecting circuit 3 through an inverter 6, and the NAND gate 5 will 
provide a high level output signal in response to the high state of the 
input signal applied to the input terminal 1. Another 2-input NAND gate 7 
is provided to provide an intermediate level output signal in response to 
the intermediate state of the input signal applied to the input terminal 
1, and it has its one input connected to receive an output signal from the 
first level detecting circuit 2 through an inverter 8 and the other input 
connected to receive an output signal from the second level detecting 
circuit 3 through the inverter 6. Furthermore, there is also provided a 
further 2-input NAND gate 9 for providing a low level output signal in 
response to the low state of the input signal applied to the input 
terminal 1 and it has its one input connected to receive an output signal 
from the first level detecting circuit 2 through the inverter 8 and the 
other input connected to receive an output signal from the second level 
detecting circuit 3. 
In operation, if the input signal having the high level V.sub.pp is applied 
to the input terminal 1, the voltage at the drain of MOS transistor 
Q.sub.3 in the first level detecting circuit 2 starts to increase, and, at 
the same time, the voltage at the interconnection B between the 
transistors Q.sub.3 and Q.sub.1 also increases thereby causing the MOS 
transistor Q.sub.1 to turn on. When the voltage at the interconnection B 
has reached the voltage level of (V.sub.cc - (effective threshold voltage 
of Q.sub.3)), then the MOS transistor Q.sub.3 is turned off, and, thus, a 
further increase in the input signal causes no further changes in the 
voltage level at the interconnection A. Thus, the voltage at point B 
becomes fixed. Here, the term "effective threshold voltage" indicates a 
voltage which is obtained from a threshold voltage with a correction of 
the so-called body effect. Under the condition, both of the MOS 
transistors Q.sub.1 and Q.sub.2 are turned on so that the first level 
detecting circuit 2 supplies a high level output signal H. 
On the other hand, if the input signal having the intermediate level 
V.sub.cc or low level V.sub.ss is applied to the input terminal 1, the MOS 
transistor Q.sub.3 is turned on thereby causing the voltage level at the 
interconnection B to be lower than V.sub.cc so that the MOS transistor 
Q.sub.1 is turned off thereby causing the first level detecting circuit 2 
to supply a low level output signal L. 
If the input signal having the high level V.sub.pp or intermeditate level 
V.sub.cc is applied to the input terminal 1, the second level detecting 
circuit 3 supplies a low level output L; whereas, if the input signal 
applied to the input terminal 1 is at low level V.sub.ss, then the second 
level detecting circuit 3 supplies a high level output signal H as its 
output. 
In the embodiment illustrated in FIG. 1, if the input signal applied to the 
input terminal 1 is at high level V.sub.pp, the first level detecting 
circuit 2 supplies a high level output signal H and the second level 
detecting circuit 3 supplies a low level output signal L. Thus, only the 
NAND gate 5 is activated to supply a low level output. Under the 
circumstances, the other two NAND gates 7 and 9 remain inactivated thereby 
supplying a high level output H. 
If the input signal applied to the input terminal 1 is at intermediate 
level V.sub.cc, the first level detecting circuit 2 supplies a low level 
output signal L and the second level detecting circuit 3 also supplies a 
low level output signal L. Accordingly, only the NAND gate 7 is activated 
to supply a low level output signal L with the other two NAND gates 5 and 
9 held inactivated thereby supplying a high level output signal H. 
If the input signal applied to the input terminal 1 is at low level 
V.sub.ss, the first level detecting circuit 2 supplies a low level output 
signal L and the second level detecting circuit 3 supplies a high level 
output signal H. As a result, only the NAND gate 9 is activated to supply 
a low level output signal L at its output while the other two NAND gates 5 
and 7 remain inactivated thereby supplying a high level output signal H at 
their output. 
In this manner, in accordance with the present invention, in response to 
the input signal applied to the input terminal 1, only one of the NAND 
gates 5, 7 and 9 is activated to supply a low level output signal 
depending on the level of the input signal. It is to be noted that the 
first and second level detecting circuits 2 and 3 should not be limited 
only to the structure disclosed in FIG. 1 and they may take any other 
structure. 
FIG. 2 shows an alternative structure for the first level detecting circuit 
2 in the present input buffer circuit. In the alternative structure shown 
in FIG. 2, a series of diode-connected MOS transistors (only Q.sub.6 and 
Q.sub.7 are shown) is provided instead of the depletion type MOS 
transistor Q.sub.3 in the embodiment of FIG. 1. Such a diode-connected MOS 
transistor may be provided singularly or in plural in number. In this 
alternative embodiment, it is so structured that utilizing a voltage drop 
resulting from the threshold voltage of such diode-connected MOS 
transistor, if the input signal applied to the input terminal 1 is at high 
level V.sub.pp, the MOS transistor Q.sub.1 is turned on; whereas, if the 
input signal applied to the input terminal 1 is at intermediate level 
V.sub.cc or at low level V.sub.ss, the MOS transistor Q.sub.1 is turned 
off. 
It is to be noted as a further alternative structure that either of the 
first and second level detecting circuits 2 and 3 may be constructed using 
NMOS inverters as is obvious for one skilled in the art in view of the 
principle of the present invention. In this case, it is only necessary to 
set the threshold level of a driver transistor at an appropriate level. It 
is to be noted that the determining structure for receiving output signals 
from the first and second level detecting circuits 2 and 3 and to indicate 
the level of the input signal applied to the input terminal 1 should not 
be limited only to the example comprised of NAND gates and inverters shown 
in FIG. 1. Other structures may manifest themselves for one skilled in the 
art once the principle of the present invention has been fully understood. 
In addition, in the illustrated embodiment, the input signal to be applied 
to the input terminal 1 has been described to have three levels: V.sub.pp, 
V.sub.cc and V.sub.ss ; however, the input signal to be applied to the 
input terminal 1 should not be limited to a signal having these three 
levels but it can have any other levels. 
While the above provides a full and complete disclosure of the preferred 
embodiments of the present invention, various modifications, alternate 
constructions and equivalents may be employed without departing from the 
true spirit and scope of the invention. Therefore, the above description 
and illustration should not be construed as limiting the scope of the 
invention, which is defined by the appended claims.