Semiconductor device with terminals, and method of manufacturing the same

A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the closest solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device with a plurality of terminals and to a method of manufacturing the device.

2. Description of the Background Art

In association with recent miniaturization of a package, a semiconductor of ball grid array (BGA) type or land grid (LGA) type, in which external electrodes are arranged in a matrix pattern on the entire back surface of a substrate, has become pervasive.

A conventional semiconductor device and a method of manufacturing the device will be described hereinbelow by reference toFIGS. 9 through 17.

FIG. 9is a view showing a front surface of a conventional semiconductor device;FIG. 10is a cross-sectional view of the semiconductor device shown inFIG. 9;FIG. 11is a view showing the back surface of the semiconductor device shown inFIG. 9;FIG. 12is a perspective view showing an interior of a resin-sealed section shown inFIG. 9;FIG. 13is a cross-sectional view of the resin-sealed section taken along line b—b shown inFIG. 12;FIG. 14is a view showing areas of the resin-sealed section to be sliced;FIG. 15is an enlarged view of areas on the back side of the semiconductor device to be sliced;FIG. 16is a cross-sectional view of sliced semiconductor devices; andFIG. 17is a cross-sectional view of a neighborhood of a solder ball shown in FIG.16.

InFIGS. 9 through 17, reference numeral1designates a substrate for manufacturing semiconductor devices;2designates a resin-sealed section;3designates solder balls;4designates a semiconductor chip;5designates a wire;6designates an area to be sliced;8designates a package; and9designates a land.

First, a conventional semiconductor device will be described.

As shown inFIGS. 9 and 10, a plurality of resin-sealed sections2are formed on the surface of a substrate1. As shown inFIG. 11, a plurality of solder balls3are formed on the back surface of the substrate1so as to correspond to the respective resin-sealed sections2. Specifically, as shown inFIG. 17, the solder balls3are formed on the back surface of the substrate1via corresponding lands9.

As shown inFIGS. 12 and 13, a plurality of semiconductor chips4electrically connected to the substrate1by means of wires5are provided in the resin-sealed sections2.

As shown inFIGS. 14 through 16, an area to be sliced (hereinafter called a “slice area”)6is provided in each of the resin-sealed sections2located in a position between the adjacent semiconductor chips4(or packages8).

As shown inFIGS. 15 and 16, the plurality of solder balls3, which serve as terminals for external electrodes, are provided on each of the semiconductor chips4(or the packages8) at uniform pitches B of, e.g., 0.8 mm. An interval C between the corresponding solder balls3of the adjacent packages8(i.e., a package-to-package pitch) is a sum of a desired package size and the width of the slice area6. For instance, in a case where a package size is 8 mm×8 mm and the width of the slice area6is 0.35 mm, the package-to-package pitch C is 8.35 mm.

Next, there will now be described a method of manufacturing the above-mentioned semiconductor device.

First, the plurality of semiconductor chips4are mounted on the surface of the substrate1. The substrate1and the semiconductor chips4are electrically connected by use of the wires5.

Next, the plurality of semiconductor chips4are collectively sealed with resin, thus forming the resin-sealed sections2.

Further, the lands9to be used for mounting solder balls are formed on the back surface of the substrate1. The solder balls3are formed on the lands9. Here, in the case of a semiconductor device of LGA, formation of the solder balls3is obviated.

The resin-sealed sections2, which have been collectively molded, are sliced along the cut areas6by means of a dicing saw, whereby the resin-sealed sections2are divided into a plurality of packages (semiconductor devices)8.

Each of the packages8is subjected to an electrical test.

As mentioned above, when each of the packages8is subjected to an electrical test, a test tool such as a test contact pin must be prepared every time a package size is different. Therefore, cost of the test tool is too high.

Further, no electrical test can be carried out during a period in which a test tool is replaced with another test tool, thereby resulting in inefficient conduction of an electrical test; that is, occurrence of so-called package switching loss.

When a package is miniaturized to an extent to be called a chip-scale package (CSP), a resultant package becomes too small or lightweight. Such packages will fall during the course of a test or transport.

A method effective for solving the problem is to simultaneously subject the plurality of semiconductor chips4to a test while the semiconductor chips4(or packages8) are sliced into pieces or collectively sealed with resin on the substrate1.

However, a package size has already been determined by a standardization institution, such as a Japanese Electronics and Information Technology Industries Associations). The interval C between the corresponding solder balls3of the adjacent packages8(i.e., the package-to-package pitch C) is not necessarily an integral multiple of the interval B between the solder balls3in the package8(i.e., a ball pitch). Therefore, even in the case of a package of same size, a test tool must be prepared every time the intervals B and C are changed. Thus, costs for the tool cannot be curtailed.

Moreover, when packages of different sizes are manufactured, test tools for the respective packages must be prepared, thereby hindering curtailment of costs for the tools.

Accordingly, since commonality cannot be achieved in connection with positions of terminals (e.g., solder balls)3on the back side of the substrate1, a test tool must be prepared every time the interval C between the solder balls C of the adjacent packages8or a package size has become changed. For this reason, costs for the test tool cannot be diminished.

A necessity for replacement of test tools entails occurrence of so-called package switching loss.

SUMMARY OF THE INVENTION

The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful semiconductor device, and is to provide a novel and useful method of manufacturing the semiconductor device.

A more specific object of the present invention is to curtail costs for a test tool used for electrical test of semiconductor devices by establishing commonality in positions of terminals of semiconductor devices.

The above object of the present invention is attained by a following semiconductor device and a following method of manufacturing a semiconductor device.

According to one aspect of the present invention, the semiconductor device comprises a plurality of semiconductor chips mounted on a surface of a substrate. The plurality of semiconductor chips is collectively sealed with sealing resin. A plurality of terminals is formed on a back surface of the substrate, wherein an interval between the corresponding terminals of the adjacent semiconductor chips is an integral multiple of the interval between the terminals in the semiconductor chip.

According to another aspect of the present invention, in the method of manufacturing a semiconductor device, a plurality of semiconductor chips is mounted on a surface of a substrate. The plurality of semiconductor chips is collectively sealed with resin. A plurality of terminals is formed on a back surface of the substrate such that an interval between the corresponding terminals of the adjacent semiconductor chips is an integral multiple of the interval between the terminals in the semiconductor chip. The plurality of semiconductor chips is subjected to an electrical test. The resin and the substrate are sliced, thereby breaking the semiconductor chips into pieces.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, principles and embodiments of the present invention will be described with reference to the accompanying drawings. The members and steps that are common to some of the drawings are given the same reference numerals and redundant descriptions therefore may be omitted.

By reference toFIGS. 1 through 8, a semiconductor device according to an embodiment of the invention and a method of manufacturing the semiconductor device will be described. Here, the present embodiment describes an example in which a BGA substrate is used as a substrate for use in manufacturing a semiconductor device.

FIG. 1is a view showing a surface of a semiconductor device according to an embodiment;FIG. 2is a cross-sectional view of the semiconductor device shown inFIG. 1;FIG. 3is a view showing a back surface of the semiconductor device shown inFIG. 1;FIG. 4is a perspective view showing an interior of a resin-sealed section shown inFIG. 1;FIG. 5is a cross-sectional view of the resin-sealed section taken along a—a shown inFIG. 4;FIG. 6is a view showing areas of the resin-sealed section to be sliced;FIG. 7is an enlarged view of the sliced section on the back surface of the semiconductor device; andFIG. 8is across-sectional view of the sliced semiconductor device.

InFIGS. 1 through 8, reference numeral1designates a substrate for use in manufacturing a semiconductor device (hereinafter referred to as a “substrate”);2designates resin-sealed sections;3designates a solder ball (terminal);4designates a semiconductor chip;5designates a wire;6designates an area to be sliced (hereinafter referred to as a “slice area”);7designates a residual remainder;8designates a package (semiconductor device); and11designates a test contact pin.

First, a semiconductor device of the embodiment will be described.

As shown inFIGS. 1 and 2, a plurality of resin-sealed sections2are formed on the surface of the substrate1. Further, as shown inFIGS. 4 and 5, a plurality of semiconductor chips4electrically connected to the substrate1by means of wires5are provided in the resin sealed sections2.

As shown inFIGS. 3 and 5, a plurality of solder balls3serving as external electrode terminals are formed on the back surface of the substrate1so as to correspond to the semiconductor chips4provided in the resin-sealed sections2. Here, the solder balls3are arranged such that an interval A between the corresponding solder balls3of the adjacent semiconductor chips4(or the adjacent packages8) becomes “n” times (where “n” is an integer greater than 1) an interval B between the solder balls3provided in one semiconductor chip4(or one package8). For instance, a package size is 0.8 mm×0.8 mm, and the interval A assumes a value of 9.6 mm (=0.8 mm×12), and the interval B assumes a value of 0.8 mm. Each of the solder balls3is formed on the back surface of the substrate1through a land (9) electrically connected to the semiconductor chip4(see FIG.17). The value of “n” is usually set within a range of 2 to 20. In short, the interval A is set so as to become two to twenty times the interval B.

As shown inFIG. 5, the test contact pins11are arranged in a grid pattern at an interval identical with the interval B (e.g., 0.8 mm) between the solder balls3. A semiconductor device is subjected to an electrical test through use of the test contact pins11(which will be described later).

As shown inFIGS. 6 through 8, two slice areas6to be sliced by a dicing saw are formed between the adjacent semiconductor chips4in the resin-sealed section2and on the substrate1. An area defined between the two slice areas6; that is, a space between the semiconductor chips4(or packages8), corresponds to the residual remainder7. The size of the residual remainder7changes in accordance with a desired package size. In other words, a desired package is obtained by changing the size of the residual remainder7. For instance, in the case of the foregoing package size, the width of the slice area6assumes a value of 0.35 mm; and the width of the residual remainder7assumes a value of 0.9 mm.

A method of manufacturing the semiconductor device will now be described.

First, as shown inFIGS. 4 and 5, a plurality of semiconductor chips4are mounted on the surface of the substrate1. The substrate1is electrically connected to the semiconductor chips4by use of the wires5.

Next, the semiconductor chips4are collectively sealed with resin, thereby forming the resin-sealed sections2.

A plurality of lands9(see FIG.17), which are electrically connected to the semiconductor chips4and are to be used for mounting the solder balls, are formed on the back surface of the substrate1. The semiconductor balls3are formed on the lands. Here, the lands9, which act as terminals for external electrodes, and the solder balls3are arranged such that the interval A between the corresponding terminals of the adjacent semiconductor chips4becomes “n” times (where “n” is an integer greater than 1) the interval B between the terminals provided in one semiconductor chip4(or one package8). For instance, a package size is 8 mm×8 mm, and the lands and the solder balls3are formed such that the interval A assumes a value of 9.6 mm (=0.8 mm×12) and such that the interval B assumes a value of 0.8 mm.

The semiconductor chips4are simultaneously subjected to an electrical test while the chips4are mounted on the substrate1. As shown inFIG. 5, the electrical test is carried out by use of the test contact pins11arranged in a grid pattern at the same interval as the interval B (e.g., 0.8 mm) between the semiconductor balls3.

After the electrical test has been completed, the slice areas6formed on the resin-sealed sections2and the substrate1through use of a dicer. Here, in order to obtain a desired package size, the slice areas6are sliced twice such that the residual remainder7has a desired width of, e.g., 0.9 mm, between the adjacent semiconductor chips4(or the adjacent packages8). As a result, the packages8are separated into pieces.

As has been described, in the first embodiment, commonality has been established in connection with positions of terminals such that the interval A between the corresponding terminals (i.e. the lands9and the solder balls3) of the adjacent semiconductor chips4becomes “n” times (“n” is an integer greater than 1) the interval B between terminals of the semiconductor chip4. Hence, so long as there are prepared the test contact pins11of single type, which are arranged in a grid pattern at the same interval as that between the interval B between terminals of the semiconductor chip4, an electrical test can be carried out through use of the same test contact pins11even when the size of semiconductor packages fabricated in the resin-sealed section2is varied. Hence, costs for the test tool can be curtailed significantly.

Moreover, an electrical test can be efficiently carried out during a period of time required for replacing a test tool with another tool; that is, without involvement of occurrence of a packaging replacement loss.

Since the plurality of packages8(or the semiconductor chips4) can be simultaneously subjected to a test while remaining on the substrate, productivity of the electrical test can be improved considerably. In addition, even when a package is miniaturized, there can be prevented falling of packages, which would otherwise be caused during the course of an electrical test or during the course of transport.

In the embodiment, the residual remainders7are left at the time of separation of the packages8into pieces, thereby slicing the resin-sealed sections2and the substrate1twice. Hence, even when an attempt is made to achieve commonality in connection with the positions of terminals, a semiconductor device of a desired package size is obtained.

The embodiment has described a case where a BGA substrate is used as a substrate for use in manufacturing semiconductor devices; i.e., packages of BGA types. However, the invention is not limited to such an embodiment and may also be applied to a package of LGA. In such a case, the solder balls3must be formed as terminals.

This invention, when practiced illustratively in the manner described above, provides the following major effects:

According to the present invention, commonality has been established between positions of terminals of a semiconductor substrate, thereby curtailing costs for a test tool used for electrical test of the semiconductor device.

The entire disclosure of Japanese Patent Application No. 2002-200930 filed on Jul. 10, 2002 containing specification, claims, drawings and summary are incorporated herein by reference in its entirety.