Switching regulator control circuit and DC/DC converter

Provided is a DC/DC converter capable of providing overvoltage protection reliably without being affected by, for example, an external element connected to an output terminal. The DC/DC converter includes a comparator, an RS-FF circuit, a drive circuit, and an ON-timer circuit, and the ON-timer circuit includes: a current source circuit which provides an electric current based on a power supply voltage; a ripple generation circuit which generates a ripple voltage; an averaging circuit which averages the ripple voltage; a timer circuit which generates an ON-timer signal; and an overvoltage protection circuit (clamp circuit).

RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No. 2021-038802, filed on Mar. 11, 2021, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a switching regulator control circuit and a DC/DC converter, and more particularly, to overvoltage protection of an output voltage.

2. Description of the Related Art

FIG.6shows a DC/DC converter including an overvoltage protection circuit according to a related art.

The DC/DC converter ofFIG.6includes a chopper regulator2, a DC power source3, a Zener diode4, an inductor5, an output capacitor6, a voltage-dividing resistor7, a voltage-dividing resistor8, a resistor9, and a phase compensation capacitor10.

The chopper regulator2includes an input terminal11, an output terminal12, an adjustment terminal13, a compensation terminal14, a current amplifier15, a comparator16, an oscillator17, an inverter18, an SR flip-flop19, a NAND circuit20, a drive circuit21, a switching element22, an error amplifier23, a reference voltage source24, and a switching element25. The switching element25having a gate controlled with an output voltage from the error amplifier23forms the overvoltage protection circuit.

In the DC/DC converter including the overvoltage protection circuit of the related art, the switching element25is configured to turn ON, when detecting that an output voltage from the DC/DC converter reaches an overvoltage based on the output voltage from the error amplifier23, and to discharge the phase compensation capacitor10, to thereby prevent the overvoltage of the output voltage (see, for example, Japanese Patent Application Laid-open No. 2009-153278).

However, the DC/DC converter described above detects the overvoltage of the output terminal12based on an output voltage Vout, and therefore has problems in that the overvoltage is erroneously detected when a failure occurs in an external element connected to the output terminal12, and the overvoltage cannot be detected when the external element is physically disconnected.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above-mentioned problems, and therefore has an object to provide a DC/DC converter capable of providing overvoltage protection reliably without being affected by, for example, an external element connected to an output terminal12.

According to at least one aspect of the present invention, there is provided a switching regulator control circuit, including: a comparator configured to compare a divided voltage corresponding to an output voltage from a DC/DC converter and a reference voltage; an RS-FF circuit having a set terminal connected to an output terminal of the comparator, and an output terminal connected to an input terminal of a drive circuit; and an ON-timer circuit having an input terminal connected to the output terminal of the RS-FF circuit, and an output terminal connected to a reset terminal of the RS-FF circuit, the ON-timer circuit including: a current source circuit configured to provide an electric current based on a power supply voltage; a ripple generation circuit configured to generate a ripple voltage depending on the electric current of the current source circuit and an output signal from the RS-FF circuit; an averaging circuit configured to average the ripple voltage; a timer circuit configured to generate an ON-timer signal depending on the electric current of the current source circuit, the output signal from the RS-FF circuit, and the averaged ripple voltage; and a clamp circuit (overvoltage protection circuit) configured to clamp the ripple voltage to a predetermined voltage.

According to the switching regulator control circuit of the present invention, through provision of the overvoltage protection circuit to the ON-timer, overvoltage protection can be provided reliably without being affected by, for example, an external element connected to the output terminal12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, a switching regulator control circuit according to at least one embodiment of the present invention is described with reference to the drawings.

FIG.1is a block diagram for illustrating a DC/DC converter including the switching regulator control circuit according to the at least one embodiment of the present invention.

The DC/DC converter ofFIG.1includes a switching regulator control circuit100, resistors103and104forming a voltage divider circuit, a coil106, and a capacitor107. The switching regulator control circuit100includes an input terminal101, an output terminal102, a drive circuit110, an ON-timer circuit111including an overvoltage protection circuit, a comparator112, an RS-FF circuit113, a reference voltage circuit114, and NMOS transistors115and116which are switching transistors.

The resistor103and the resistor104are connected between an output terminal of the DC/DC converter and a ground terminal to form a feedback resistor circuit. The comparator112has an inverting input terminal connected to an output terminal of the feedback resistor circuit via the input terminal101, a non-inverting input terminal connected to a positive electrode of the reference voltage circuit114, and an output terminal connected to a set terminal S of the RS-FF circuit113. The RS-FF circuit113has a reset terminal R connected to an output terminal124of the ON-timer circuit111, and an output terminal Q connected to an input terminal of the drive circuit110and an input terminal121of the ON-timer circuit111. The drive circuit110has a first output terminal connected to a gate of the NMOS transistor115, and a second output terminal connected to a gate of the NMOS transistor116. The NMOS transistor115has a drain connected to a power supply terminal, and a source connected to one terminal of the coil106. The NMOS transistor116has a drain connected to the one terminal of the coil106, and a source connected to the ground terminal. The capacitor107has one terminal connected to the other terminal of the coil106, and the other terminal connected to the ground terminal.

The DC/DC converter configured as described above operates as follows.

The DC/DC converter provides an output voltage Vout when a power supply voltage is supplied thereto. The resistors103and104forming the feedback resistor circuit divide the output voltage Vout and provide a divided voltage VFB. The switching regulator control circuit100provides an output signal depending on the divided voltage VFB supplied via the input terminal101to the output terminal102.

The reference voltage circuit114provides a reference voltage Vref. The comparator112compares the reference voltage Vref supplied to a non-inverting input terminal+ and the divided voltage VFB supplied to an inverting input terminal−, and provides a signal VS from the output terminal. The RS-FF circuit113provides a signal VQ of a High level from the output terminal Q when the signal VS of a High level is supplied to the set terminal S. When the signal VQ of the High level is supplied thereto, the drive circuit110provides a drive signal of a High level from the first output terminal to the gate of the NMOS transistor115, and provides a drive signal of a Lo level from the second output terminal to the gate of the NMOS transistor116. The ON-timer circuit111receives an input of the signal VQ to the input terminal121, and provides an ON-time signal VR from the output terminal124to the reset terminal R of the RS-FF circuit113. When the signal VR of a High level is supplied to the reset terminal R, the RS-FF circuit113provides the signal VQ of a Lo level from the output terminal Q. When the signal VQ of the Lo level is supplied thereto, the drive circuit110provides the drive signal of the Lo level from the first output terminal to the gate of the NMOS transistor115, and provides the drive signal of the High level from the second output terminal to the gate of the NMOS transistor116.

First Embodiment

FIG.2is a block diagram for illustrating a configuration of the ON-timer circuit111including the overvoltage protection circuit in a first embodiment of the present invention.

The ON-timer circuit111includes a current source circuit220, a ripple generation circuit230, an averaging circuit240, a timer circuit250, and a clamp circuit260which is the overvoltage protection circuit.

The current source circuit220supplies an electric current I1which depends on the power supply voltage to the ripple generation circuit230and the timer circuit250. The ripple generation circuit230provides a voltage Vcref0which includes a ripple component and is proportional to the output voltage Vout depending on the electric current I1and the signal VQ which are supplied thereto. The averaging circuit240provides a voltage Vcref obtained by averaging the voltage Vcref0. The timer circuit250generates the signal VR to be provided to the reset terminal R of the RS-FF circuit113depending on the electric current I1and the voltage Vcref which are supplied to the timer circuit250.

FIG.3is a circuit diagram for illustrating an example of the ON-timer circuit111ofFIG.2.

The current source circuit220includes resistors202,201, and203, an amplifier204, an NMOS transistor205, and a PMOS transistor206. The ripple generation circuit230includes a PMOS transistor207, a switch circuit208, a capacitor209, and a resistor210. The averaging circuit240includes a resistor211and a capacitor212. The timer circuit250includes an inverter213, an NMOS transistor214, a capacitor215, a comparator216, and a PMOS transistor217. The clamp circuit260includes a PMOS transistor261, an amplifier262, and a reference voltage circuit263.

The current source circuit220generates the electric current I1as follows.

The amplifier204has a non-inverting input terminal to which a voltage V1obtained by dividing the power supply voltage by the resistor202and the resistor201is supplied, and therefore controls a gate voltage of the NMOS transistor205so that a connection point between a source of the NMOS transistor205and the resistor203becomes the voltage V1. Thus, the electric current I1which depends on the power supply voltage flows through the resistor203. The electric current I1is supplied from the PMOS transistor206to the ripple generation circuit230via the PMOS transistor207, and to the timer circuit250via the PMOS transistor217.

The ripple generation circuit230generates the voltage Vcref0as follows.

The capacitor209is charged with the electric current I1to generate the voltage Vcref0thereacross. The electric current I1is expressed as I1=VDD×K, where VDD represents the power supply voltage, and K represents a proportionality factor. An electric current I2which flows through the resistor210is expressed as I2=Vcref0/R2, where R2is a resistance value of the resistor210. When the signal VQ is at the High level, the switch circuit208is turned ON so that the capacitor209is charged with the electric current I1, and is discharged with the electric current I2. In contrast, when the signal VQ is at the Lo level, the switch circuit208is turned OFF so that the capacitor209is discharged with the electric current I2. A charge amount Q1to be charged is expressed as Q1=I1×Ton, where Ton is time discharge while the signal VQ is at the High level. A charge amount Q2is expressed as Q2=I2×TS, where TS is time from when the signal VQ becomes the High level to when the signal VQ becomes the High level again. When the output voltage Vout is controlled with a constant voltage, because Q1=Q2, Ton/TS=I2/I1=Vout/VDD. Developing the equation by substituting the electric currents I1and I2, the voltage Vcref0is expressed as Vcref0=Vout×R2×K. Consequently, the voltage Vcref0is a voltage which is synchronized with the signal VQ from the RS-FF circuit113, includes the ripple component, and is proportional to the output voltage Vout.

The averaging circuit240averages the voltage Vcref0by the resistor211and the capacitor212to remove the ripple component from the voltage Vcref0. Thus, the voltage Vcref is a voltage which is equivalent to the voltage Vcref0which does not include the ripple component.

The timer circuit250generates the signal VR as follows.

The NMOS transistor214has a gate to which the signal VQ is supplied via the inverter213, and thus is controlled to be turned OFF when the signal VQ is at the High level, that is, when the NMOS transistor115is turned ON. When the NMOS transistor214is turned OFF, the capacitor215is charged with the electric current I1so that a voltage Vcap thereacross is increased. The comparator216provides the signal VR of a Lo level to the output terminal124when the voltage Vcap is lower than the voltage Vcref, and provides the signal VR of the High level to the output terminal124when the voltage Vcap becomes higher than the voltage Vcref. The signal VQ becomes the Lo level with the signal VR of the High level, and the NMOS transistor115is controlled to be turned OFF. Then, the NMOS transistor214is turned ON when the signal VQ becomes the Lo level to discharge the capacitor215.

The ON time Ton in which the NMOS transistor115is ON is Ton=C2/I1×Vcref=C2×R2×Vout/VDD, where C2is a capacitance value of the capacitor215. In other words, in the ON time Ton, duty control expressed by Vout/VDD can be performed. In this manner, the ON-timer circuit111can control the output voltage Vout to a desired voltage with the voltage Vcref which is proportional to the output voltage Vout without directly using the output voltage Vout.

In the DC/DC converter which operates as described above, under an overvoltage state in which the output voltage Vout is increased over the desired voltage, the voltage Vcref is proportional to the output voltage Vout and is therefore increased similarly. The clamp circuit260suppresses an increase in voltage Vcref to prevent the overvoltage of the output voltage Vout.

The clamp circuit260includes the PMOS transistor261, the amplifier262, and the reference voltage circuit263. The amplifier262has an inverting input terminal− to which the voltage Vcref is supplied, and a non-inverting input terminal+ to which the reference voltage provided by the reference voltage circuit263is supplied. The PMOS transistor261has a source connected to the inverting input terminal− of the amplifier262, a gate connected to an output terminal of the amplifier262, and a drain connected to the ground terminal. The reference voltage, that is, a clamp voltage provided by the reference voltage circuit263is set to a value that is higher than the voltage Vcref=Vout×R2×K at the time of normal operation.

Under a normal state in which the voltage Vcref is lower than the reference voltage from the reference voltage circuit263, because the amplifier262provides a voltage of a High level, the PMOS transistor261is OFF. Thus, the clamp circuit260does not perform the clamp operation.

When the output voltage Vout becomes the overvoltage state and the voltage Vcref reaches the reference voltage from the reference voltage circuit263, the amplifier262controls a gate voltage of the PMOS transistor261so that the voltage Vcref does not exceed the reference voltage. Here, the ON time Ton is C2/I1×Vcref, and the output voltage Vout is Ton/TS×VDD. Consequently, the increase in output voltage Vout is suppressed, and the overvoltage protection operation can be performed.

As described above, the ON-timer circuit including the overvoltage protection circuit in the first embodiment controls the voltage Vcref so as not to exceed the clamp voltage from the clamp circuit260, and can therefore provide overvoltage protection reliably without being affected by, for example, an external element connected to the output terminal12.

FIG.4is a block diagram for illustrating another configuration of the ON-timer circuit in the first embodiment.

he ON-timer circuit111in this configuration is configured so that, in the ON-timer circuit111ofFIG.2, the clamp circuit260which is the overvoltage protection circuit is connected between the ripple generation circuit230and the averaging circuit240. Because the other components are similar to those of the ON-timer circuit111ofFIG.2, a detailed description thereof is omitted.

The ON-timer circuit including the overvoltage protection circuit configured as inFIG.4controls the voltage Vcref0so as not to exceed the clamp voltage from the clamp circuit260, and therefore provides effects similar to those obtained by the first embodiment.

Second Embodiment

FIG.5is a block diagram for illustrating a configuration of an ON-timer circuit including an overvoltage protection circuit in a second embodiment of the present invention.

An ON-timer circuit111in the second embodiment includes, in the ON-timer circuit111ofFIG.2, an overvoltage protection circuit270instead of the clamp circuit260which is the overvoltage protection circuit. The overvoltage protection circuit270includes an OR circuit271, a comparator272, and a reference voltage circuit273. A reference voltage from the reference voltage circuit273is set to a voltage that is higher than Vout×R2×K as with the clamp voltage from the clamp circuit260.

The comparator272has an inverting input terminal− connected to an output terminal of the reference voltage circuit273, and a non-inverting input terminal+connected to an output terminal of the averaging circuit240. The OR circuit271has a first input terminal connected to an output terminal of the timer circuit250, a second input terminal connected to an output terminal of the comparator272, and an output terminal connected to the output terminal124of the ON-timer circuit111.

When the output voltage Vout becomes the overvoltage state, the voltage Vcref is increased as well as the output voltage Vout. When the voltage Vcref reaches the reference voltage, the comparator272provides a signal of a High level. When receiving the signal of the High level from the comparator272, the OR circuit271provides a signal of a High level irrespective of an output signal from the timer circuit250. In other words, the ON-timer circuit111provides the signal VR of the High level from the output terminal124to turn OFF the NMOS transistor115and turn ON the NMOS transistor116. Consequently, the output voltage Vout can be reduced, and the overvoltage protection operation can be performed.

As described above, the ON-timer circuit including the overvoltage protection circuit in the second embodiment includes the comparator272which detects by the voltage Vcref that the output voltage Vout becomes the overvoltage state, and the OR circuit271which provides the signal from the comparator272, and can therefore perform the overvoltage protection operation as in the first embodiment.

The at least one embodiment of the present invention has been described above, but the present invention is not limited to the above-mentioned at least one embodiment, and various modifications can be made thereto without departing from the gist of the present invention. For example, the clamp circuit in the first embodiment is not limited to the circuit illustrated inFIG.3as long as the circuit can perform clamping to the desired voltage.