Method for making a semiconductor device including diffusion control

A process for making a MOS device on a silicon substrate includes the step of forming a buried layer of germanium-silicon alloy in the substrate, or, alternatively, a buried layer of silicon enclosed between thin, germanium-rich layers. This buried layer is doped with boron, and tends to confine the boron during annealing and oxidation steps. The process includes a step of exposing the substrate to an oxidizing atmosphere such that an oxide layer 10 .ANG.-500 .ANG. thick is grown on the substrate.

FIELD OF THE INVENTION 
This invention relates to processes for manufacturing MOS devices. More 
particularly, this invention relates to the control of boron diffusion 
during the manufacture of MOS devices that include boron-doped regions. 
ART BACKGROUND 
Boron has long been used as a dopant for semiconductor devices. However, 
boron atoms tend to diffuse during the annealing and oxidation steps of a 
fabrication sequence. As a result, it is difficult to manufacture devices, 
such as deep sub-micron NMOS and CMOS device, in which the boron 
distribution must have a steep profile. 
It has long been known that the presence of germanium as a co-dopant will 
retard the diffusion of boron. For example, U.S. Pat. No. 4,728,619, 
issued to J. R. Pfiester et al. on Mar. 1, 1988, describes a method for 
making a CMOS integrated circuit having boron-doped channel-stop regions. 
Germanium is implanted into these regions to retard the diffusion of 
boron. The germanium is implanted at a concentration of less than 1 at. %. 
After the germanium is implanted, a field oxide more than 6000 .ANG. thick 
is grown. 
We believe that the method of Pfiester for providing germanium-doped 
regions will only be of limited value for making deep sub-micron devices. 
In order to make boron profiles steep enough for, e.g., vertically 
engineered devices having buried boron-doped layers, it will be necessary 
to include more than 1 at. % germanium in the boron-doped regions. 
We believe that in the method of Pfiester, there is, in fact, some 
concentration of the implanted germanium during the subsequent field oxide 
growth. That is, the advancing oxidation front ejects germanium atoms into 
the underlying silicon. However, the improvements in device performance 
reported by Pfiester were measured in devices having more than 6000 .ANG. 
of field oxide, as noted above. In the manufacture of deep sub-micron 
devices, by contrast, it would generally be unacceptable to grow more than 
about 500 .ANG. of oxide at any time after the boron and germanium dopants 
have been incorporated in the water. That is because, according to at 
least some generally accepted manufacturing methods, the gross structure 
of the devices will already have been defined by, e.g., patterning an 
initial field oxide layer. Subsequent growth of a further oxide layer 
having a thickness even as small as 500 .ANG. could obliterate this gross 
structure. 
What practitioners in the art have hitherto failed to provide is a method 
for making MOS devices having germanium-containing regions that will 
control boron diffusion to such an extent that sharply defined structures 
such as pulse-shaped or retrograde boron-doped regions are readily 
incorporated. 
SUMMARY OF THE INVENTION 
We have invented a process for making a MOS device on a silicon substrate. 
This device includes a germanium-containing region that can exert tight 
control over boron diffusion. This process includes the step of forming a 
pseudomorphic, strained layer of Ge.sub.x Si.sub.1-x on the substrate, 
where the average local value of x at each depth within the strained layer 
is at least about 0.1, and the GeSi layer is overlain by a silicon layer. 
The process includes the further steps of lithographically patterning the 
GeSi and silicon layers such that at least one active region is 
collectively defined in them; doping the GeSi layer with boron at a 
concentration of at least about 10.sup.17 cm.sup.-3 but not more than 
about 10.sup.19 cm.sup.-3 ; maintaining the patterned and boron-doped 
substrate at a temperature of at least about 750.degree. C. and not more 
than about 950.degree. C.; and while maintaining the substrate at this 
elevated temperature, exposing the substrate to an oxidizing atmosphere 
such that an oxide layer at least about 10 .ANG. thick, but not more than 
about 500 .ANG. thick, is grown on the silicon layer. The purpose of this 
oxidation step is to induce boron to diffuse into the SiGe and the oxide 
layers, resulting in a sharper boron profile and reduced boron 
concentration in the channel region. The gate dielectric layer in the 
active device need not be formed by thermal oxidation.

DETAILED DESCRIPTION 
We now describe an illustrative fabrication process useful, inter alia, for 
making an MOS device having a pulse-shaped boron doping profile, or an MOS 
device having a retrograde boron doping profile. 
Turning to FIG. 1, a silicon water 10 is provided, suitable as a substrate 
for MOS device fabrication. Well-known methods of molecular beam epitaxy 
(MBE) or chemical vapor deposition (CVD) are used to grow an epitaxial, 
pseudomorphic, strained layer 20 of silicon-germanium alloy having the 
composition Ge.sub.x Si.sub.1-x. Layer 30 of silicon is then grown over 
layer 20. The germanium mole fraction x should be at least about 0.1. At 
each value of x, there will be a critical thickness for dislocation growth 
in the strained layer. The thickness of layer 20 should be less than this 
critical thickness. By way of example, at x=0.20, layer 20 can be made up 
to 300 .ANG. thick (or somewhat more), and will be about 200 .ANG. thick 
for typical applications that we currently envisage. The corresponding 
thickness of layer 30 will typically be about 500 .ANG.. 
It should be noted that x need not he constant within layer 20. Instead, 
useful embodiments of layer 20 can be made in which x varies, exemplarily 
according to a triangular or parabolic distribution that is greatest at 
the upper and lower interfaces and least at a depth internal to the layer. 
Another useful embodiment of layer 20 would consist of a Si/Si.sub.x 
Ge.sub.1-x superlattice, with values of x typically 0&lt;x&lt;0.5. 
Layer 20 is to be doped with boron at a concentration in the approximate 
range 10.sup.17 -10.sup.19 cm.sup.-3. According to one doping method, the 
boron is codeposited, together with silicon and germanium, during the 
growth of layer 20. According to an alternative method, the boron is 
incorporated by ion implantation, as discussed below. The ion implantation 
method is currently preferred, because by this method it is feasible to 
localize the distribution of (as-implanted) boron only in the areas where 
boron doping is desired. Thus, for example, implanted boron is readily 
excluded from those portions of a CMOS substrate that are intended for 
PMOS channel regions. 
As we discuss in greater detail below, alloy layer 20 is advantageously 
included because it tends to confine the boron dopant during subsequent 
annealing. We have found that an alternative structure is also useful in 
this regard. Such a structure is shown in FIG. 2. The alternative 
structure comprises a boron-doped, epitaxial, silicon layer 32 enclosed 
between upper and lower germanium-rich, epitaxial, boundary layers 34. 
Each of layers 34 will typically consist of at least 2, but fewer than 6, 
monolayers of substantially pure germanium. However, an admixture of 
silicon in these layers can also be tolerated, provided the layers are 
made thick enough to compensate for the presence of silicon. Thus, a 
boundary layer 34 will generally be useful if in thickness it is 
equivalent to 8 or fewer monolayers, and it has an average germanium mole 
fraction of at least 75%. The greatest permissible thickness, at any given 
germanium mole traction, will of course be limited by the critical 
thickness at that composition. 
A conventional sequence of steps is now performed in order to define the 
NMOS active regions on the wafer. Some of these steps are described below, 
with reference to the accompanying figures. Turning first to FIG. 3, if 
CMOS circuitry is being made, the wafer is subdivided into NMOS regions 40 
and PMOS regions 50. During this sequence of steps, patterned pad oxide 
layer 60 and patterned nitride layer 70 are formed. 
Turning next to FIG. 4, the active regions are conventionally isolated by 
growing thermal oxide features 80, and nitride layer 70 is removed. 
If layer 20 is to be doped by boron implantation, this implantation is next 
performed. As shown in FIG. 5, the implantation will lead to an 
as-implanted boron profile 90 that is relatively high throughout layers 20 
and 30, and falls off with increasing depth z into the substrate. Typical 
conditions for the implantation of boron in the form of boron difluoride 
(BF.sub.2) are: energy of 90 keV and areal dose of 10.sup.13 cm.sup.-2. 
(We currently prefer to implant boron difluoride because we find that it 
yields a sharper dopant profile than atomic boron.) If CMOS circuitry is 
being made, the intermediate processes leading to formation of the PMOS 
channels are also performed at this stage in the fabrication sequence. 
The as-implanted, or as-deposited, boron profile is then modified by 
maintaining the substrate at a temperature in the approximate range 
750.degree. C.-950.degree. C. At temperatures above this range, layer 20 
may experience thermally-induced damage. At temperatures below this range, 
the desired modification of the boron profiles will not take place within 
a reasonable amount of time. During at least a portion of this annealing 
step, an oxide layer at least about 10 .ANG. thick, but not more than 
about 500 .ANG. thick, is grown on layer 30. This oxide step allows boron 
profile to be adjusted according to the device requirements. The oxide 
layer is then etched away and a gate oxide is either thermally grown or 
deposited by established techniques. 
We have found that layer 20 tends to inhibit the diffusive broadening of 
the boron profile that would otherwise occur during the annealing step. As 
a consequence, boron profile 100 after annealing remains strongly confined 
in the neighborhood of layer 20, as shown in FIG. 6. We have further found 
that if oxidation takes place during the annealing step, boron atoms will 
preferentially diffuse from silicon layer 30 into the newly formed oxide. 
This provides a further method for enhancing the confinement of boron 
within layer 20. That is, a sacrificial oxide layer 110 is readily grown 
during the annealing step, but removed before the actual gate dielectric 
layer is either grown or deposited. By permitting boron to diffuse into 
the sacrificial oxide layer 110 and then removing that layer, the surface 
and near-surface concentrations of boron are further reduced. 
The use of a sacrificial layer to remove boron is particularly useful if 
the boron has been introduced by ion implantation. This is because it is 
simpler, and therefore advantageous, to introduce the boron by a shallow 
implant, rather than an implant designed to produce a peak boron 
concentration at a predetermined depth. However, the shallow implant will 
result in an as-implanted boron concentration that has an approximately 
constant, maximum value throughout layers 20 and 30. The preferential 
diffusion of boron into the sacrificial oxide helps to sharpen the 
initially flat profile within layer 30. 
Compared in FIG. 7 is a group of idealized concentration profiles: profile 
120 of co-deposited boron before annealing, the resulting profile 130 
after annealing, and profile 140 corresponding to profile 130 in the case 
where the boron-doped layer is otherwise pure silicon. Compared in FIG. 8 
is a further group of idealized concentration profiles: profile 150 of 
implanted boron before annealing, the resulting profile 160 after 
annealing, and profile 170 corresponding to profile 160 in the case where 
the boron-doped layer is otherwise pure silicon. The profiles of FIGS. 7 
and 8 are presented purely as a pedagogical aid, and are not intended to 
represent accurate theoretical or experimental results. According to our 
current belief, the annealing and oxidizing conditions are readily 
adjusted to make actual profiles, corresponding to profiles 130 and 160, 
in which the logarithmic boron concentration falls quite steeply (in the 
direction leading out of layer 20) within a region at least 100 .ANG. 
thick near each boundary of layer 20. We believe that an average slope can 
be achieved in these regions that is greater than one decade per 500 
.ANG.. 
According to our current belief, a decrease in the surface boron 
concentration (i.e., between layer 30 and the gate dielectric layer, which 
is not shown in the figure) in heterostructures incorporating Si-Ge alloy 
layers primarily reflects the drop at the interface between layers 20 and 
30. This drop is primarily due to lower chemical potential and, to a 
lesser extent, due to lower diffusivity of boron in strained 
(pseudo-morphic) SiGe. For those devices where low boron surface 
concentration (i.e., less than about 10.sup.16 cm.sup.-3) is needed, and 
therefore a very high germanium concentration would be required, the 
thermal and mechanical stability of the alloy layer would have to be 
carefully considered. In order to achieve desired doped-pulse widths in 
such devices without exceeding the alloy layer critical thickness, it 
might be desirable to adopt a germanium profile that has a parabolic, or 
other similar functional dependence, on the depth. This would reduce the 
average germanium concentration, while maintaining the necessary high 
concentration at the interfaces. In such heterostructures, the initial 
boron profile would also have to be adjusted to compensate for the dopant 
redistribution during oxidation and annealing. If necessary, the precise 
shape needed for the initial germanium and boron profiles could be readily 
determined through experimentation. 
EXAMPLE 
We obtained a 5-cm in diameter Si(100) wafer doped with boron to a 
resistivity of 30 ohm-cm. We cleaned this water by a chemical means and 
sublimated the remaining oxide, yielding a protective, carbon-free oxide 
that was subsequently desorbed at about 850.degree. C. in a molecular beam 
epitaxy (MBE) growth chamber (base pressure less than 2.times.10.sup.-11 
torr). We then deposited a 3000 .ANG. epilayer of pure silicon at a 
substrate temperature of 600.degree. C.-700.degree. C. We then deposited 
in succession, by MBE, a Si-25 at. % Ge layer 250 .ANG. thick, and a 
silicon cap layer 400 .ANG. thick. The growth temperatures were 
500.degree. C. for the Si-Ge layer, and 600.degree. C. for the cap layer. 
We implanted BF.sub.2 in the finished water at a dose of 10.sup.13 
cm.sup.-2 and an energy of 90 keV, and cleaned the implanted wafer by 
standard techniques. One half of the wafer was then reserved as a control 
sample. We oxidized the other half of the wafer in dry oxygen at 
800.degree. C. for 18 minutes, and then annealed it for 20 minutes in dry 
nitrogen at 800.degree. C. 
SIMS profiles of the control sample and the processed sample are shown in 
FIG. 9. It is apparent from the figure that the processed sample exhibits 
substantially greater boron confinement and lower boron concentration at 
the interface.