Through silicon via repair circuit of semiconductor apparatus

A through silicon via (TSV) repair circuit of a semiconductor apparatus is provided. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and an output logic circuit. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit transforms an input signal into a pending signal and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit prevents a leakage current produced by a first level voltage from entering the silicon substrate according to the short-circuit detection output signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 101144576, filed on Nov. 28, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The technical field relates to a through silicon via (TSV) repair circuit of a semiconductor apparatus adapted to a chip stacking technique.

BACKGROUND

Due to the constant increase in the number of transistors in each integrated circuit (IC), the surface area of each chip is increased. Accordingly, the delay time of each signal is prolonged, and the power consumption is increased. To effectively resolve this problem, a three-dimensional IC (3DIC) stacking technique is being developed for reducing the delay time of each signal and decreasing the power consumption. In the 3DIC stacking technique, multiple ICs are vertically stacked, and through silicon vias (TSVs) running through silicon substrates are formed for transmitting signals and supply voltages between different ICs, so that the size of the chip is effectively reduced.

The 3DIC stacking technique has three major steps. The first step is to form TSV channels and fill in a conductive metal, the second step is wafer thinning, and the third step is chip stacking and integration. In the first step, due to the limitation of existing fabrication techniques, the thin insulating film (for example, SiO2) serving as the sidewall of a TSV may be broken or contaminated with impurities during the fabrication process, and as a result, an open circuit of the TSV or a short circuit of the silicon substrate may be caused. Besides, in the third step, when multiple ICs are stacked and integrated, the TSV may be improperly connected and open-circuited (i.e., the TSV cannot provide a valid path for transmitting signals among different ICs) due to a small offset of the ICs.

In the conventional design of a 2DIC, multiple paths are formed for transmitting a same signal at the same time, so as to make sure that data is correctly transmitted. However, in the 3DIC stacking technique, if a TSV and the silicon substrate are short-circuited, the leakage current produced by the supply voltage will enter the silicon substrate through the TSV, and accordingly the voltage level of the entire silicon substrate will drift and become unstable. As a result, signals transmitted in other TSVs may not be correctly transmitted due to the drifted voltage level of the silicon substrate. Thereby, many manufacturers in the 3DIC field are trying to develop a data transmission path circuit which can automatically detect any TSV short circuit and comes with a data self-repair function.

SUMMARY

The disclosure is directed to a through silicon via (TSV) repair circuit of a semiconductor apparatus, in which a short circuit between a TSV and a silicon substrate is automatically detected to prevent a leakage current from entering the silicon substrate, and a transmitted signal is self-repaired into a correct output signal to allow a three-dimensional integrated circuit (3DIC) to work properly.

The disclosure provides a TSV repair circuit of a semiconductor apparatus. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and output logic circuit. The first chip and the at least one second chip are vertically stacked. The at least two TSVs run through a silicon substrate for transmitting data between the first chip and the at least one second chip. The at least two data path circuits are disposed at the first chip and are respectively connected to the at least two TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit receives an input signal, transforms the input signal into a pending signal according to a first level voltage and a second level voltage, and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit is connected to the first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the corresponding TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit is connected to the short-circuit detection circuit and the input driving circuit. The leakage current cancellation circuit prevents the leakage current produced by the first level voltage from entering the silicon substrate according to the short-circuit detection output signal. The output logic circuit is disposed at the at least one second chip. At least two input terminals of the output logic circuit are respectively connected to second terminals of at least one of the TSVs for respectively receiving a plurality of transmission signals, and the output logic circuit generates an output signal according to the transmission signals.

The disclosure provides a TSV repair circuit of a semiconductor apparatus. The TSV repair circuit includes a plurality of chips, at least two TSVs, at least two data path circuits, and an output logic circuit. The chips are stacked. The at least two TSVs run through a silicon substrate for transmitting data among the chips. The at least two data path circuits are disposed at any one of the chips, and the at least two data path circuits are respectively connected to the at least two TSVs. The chips not disposed with the at least two data path circuits and the adjacent chips transmit data to each other through the at least two TSVs running through the silicon substrate. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit receives an input signal, transforms the input signal into a pending signal according to a first level voltage and a second level voltage, and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit is connected to the first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and the silicon substrate according to the input signal and the first terminal of the corresponding TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit is connected to the short-circuit detection circuit and the input driving circuit. The leakage current cancellation circuit prevents a leakage current produced by the first level voltage from entering the silicon substrate according to the short-circuit detection output signal. The output logic circuit is disposed at at least one of the chips. At least two input terminals of the output logic circuit are respectively connected to second terminals of at least one of the TSVs for respectively receiving a plurality of transmission signals, and the output logic circuit generates an output signal according to the transmission signals.

The disclosure provides a TSV repair circuit of a semiconductor apparatus. The TSV repair circuit includes a plurality of chips, a plurality of TSVs, a plurality of data path circuits, and at least one output logic circuit. The chips are stacked. The TSVs run through a silicon substrate for transmitting data among the chips. The data path circuits are disposed at each of the chips and are respectively connected to the TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit receives an input signal, transforms the input signal into a pending signal according to a first level voltage and a second level voltage, and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit is connected to the first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and the silicon substrate according to the input signal and the first terminal of the corresponding TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit is connected to the short-circuit detection circuit and the input driving circuit. The leakage current cancellation circuit prevents a leakage current produced by the first level voltage from entering the silicon substrate according to the short-circuit detection output signal. The output logic circuit is disposed at the chips. An input terminal of the output logic circuit is respectively connected to second terminals of the TSVs for respectively receiving a plurality of transmission signals, and the output logic circuit generates an output signal according to the transmission signals. Input terminals of the data path circuits in the chips are connected to an output terminal of the output logic circuit in the chips.

As described above, in a TSV repair circuit provided by an embodiment of the disclosure, a short circuit between a TSV and a silicon substrate is detected according to an input signal and the voltage level on a first terminal of the TSV, and when the short circuit is detected, a supply voltage is instantly shut off and the first terminal of the TSV is connected to a ground voltage, so that a leakage current is prevented from entering the silicon substrate and the voltage level on the silicon substrate is prevented from drifting. In addition, an output logic circuit can restore a plurality of transmitted signals into correct signals so that a semiconductor apparatus (for example, a 3DIC) can work properly even when some TSVs are short-circuited.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

FIG. 1is a diagram of a through silicon via (TSV) repair circuit100of a semiconductor apparatus according to a first embodiment of the disclosure. As shown inFIG. 1, the TSV repair circuit100includes at least two vertically stacked chips CHIP1and CHIP2, at least two sets of TSVs110-111and112-113, at least two data path circuits120and121, and an output logic circuit140. In the present embodiment, the first set of TSVs110-111is corresponding to the data path circuit120, and the second set of TSVs112-113is corresponding to the data path circuit121.

In the embodiment illustrated inFIG. 1, only the first chip CHIP1and the second chip CHIP2are vertically stacked. However, the disclosure is not limited thereto. One implementing the present embodiment can vertically stack more chips to form a semiconductor apparatus (for example, a three-dimensional integrated circuit (3DIC)) and serve two of the chips which are about to transmit data respectively as the first chip CHIP1and the second chip CHIP2. Herein there may be one or more other chips between the first chip CHIP1and the second chip CHIP2, and there may also be one or more second chips CHIP2and all these second chips CHIP2receive an output signal Vout. In the present embodiment, the TSV repair circuit100is expected to properly and unidirectionally transmit an input signal Vin of the first chip CHIP1to one or more second chips CHIP2. Even though only the first chip CHIP1and the second chip CHIP2are vertically stacked inFIG. 1, in the present embodiment, more chips may be vertically stacked and two of the chips which are about to transmit data may be considered the first chip CHIP1and the second chip CHIP2. Herein one or more other chips may exist between the first chip CHIP1and the second chip CHIP2.

On the other hand, the first embodiment is described by assuming two data paths (i.e., the data path circuits120and121respectively corresponding to the first set of TSVs110-111and the second set of TSVs112-113). However, one implementing the present embodiment may also adopt another one or more data path circuits and corresponding TSVs to increase the data transmission accuracy.

The TSVs110-113run through a silicon substrate130for transmitting data between the first chip CHIP1and the second chip CHIP2. The data path circuit120is disposed at the first chip CHIP1and connected to the TSV110. The TSVs110-113inFIG. 1run through the silicon substrate130of the first chip CHIP1. If in the present embodiment, multiple chips are stacked to form a semiconductor apparatus (for example, a 3DIC), the TSV110runs through the silicon substrates of the corresponding chips in order to allow signals to be transmitted to the second chip CHIP2. The data path circuit120of the first chip CHIP1is connected to the first terminals of the first set of TSVs110-111to transmit the input signal Vin through the TSVs110-111. The data path circuit121is connected to the first terminals of the second set of TSVs112-113to transmit the input signal Vin through the TSVs112-113. The output logic circuit140of the second chip CHIP2is respectively connected to the second terminals of the first set of TSVs110-111and the second terminals of the second set of TSVs112-113and receives transmission signals St1and St2, so as to receive the output signal Vout through the output logic circuit140.

In a general application of the present embodiment, data is transmitted through a single data path circuit120corresponding to a single TSV110. However, because the sidewall of the TSV is made of a thin insulating film (SiO2) and due to the limitation of existing fabrication techniques, the sidewall of the TSV110may be broken or contaminated with impurities. As a result, the data transmission through the single TSV110may not be stable. Thus, those implementing the present embodiment can associate a single data path circuit120to multiple TSVs (for example, more than two TSVs) according to the actual requirement. For example, the TSVs111and113marked with dotted lines inFIG. 1are disposed as different paths for transmitting data. In addition, in other embodiments of the disclosure, the same input signal Vin may be transmitted at the same time through data path circuits120and121respectively corresponding to different TSVs, so that a data repair purpose can be accomplished.

FIG. 2is a schematic block diagram of the TSV repair circuit100of a semiconductor apparatus according to the first embodiment of the disclosure. In the present embodiment, the data path circuit120is corresponding to a single TSV110. However, those implementing the present embodiment may also adopt the TSV111marked with dotted lines inFIG. 2to increase the data transmission accuracy. Similarly, the data path circuit121is corresponding to the TSVs112and113. Because the data path circuits120and121have similar circuit structures, below, the data path circuit120will be described as an example, while the data path circuit121can be referred to related descriptions of the data path circuit120.

The data path circuit120includes an input driving circuit210, a short-circuit detection circuit220, a bias circuit330, and a leakage current cancellation circuit230. The input driving circuit210receives the input signal Vin and enhances the driving ability of the input signal Vin. The driving ability of the input signal Vin is enhanced to prevent any data error caused by signal attenuation when the input signal Vin is transmitted. The input driving circuit210transforms the input signal Vin into a pending signal Va according to a first level voltage (for example, a supply voltage VDD) and a second level voltage (for example, a ground voltage GND) and transmits the pending signal Va to the first terminal of the TSV110. The TSV110then transmits the pending signal Va to the second chip CHIP2as the output signal Vout. Herein the voltage level of the first level voltage (i.e., the supply voltage VDD) is higher than that of the second level voltage (i.e., the ground voltage GND).

However, if the insulation layer of the TSV110is broken or contaminated by impurities during the fabrication process and accordingly a short circuit is produced between the TSV110and the silicon substrate of the first chip CHIP1, in the present embodiment, the short-circuit detection circuit220is configured to automatically detect the short circuit between the TSV110and the silicon substrate, and the leakage current cancellation circuit230is configured to prevent the leakage current from entering the silicon substrate. To be specific, the short-circuit detection circuit220is connected to the first terminal of the TSV110. The short-circuit detection circuit220detects the short circuit between the TSV110and the silicon substrate according to the input signal Vin and the first terminal of the TSV110and generates a short-circuit detection output signal Sds.

The leakage current cancellation circuit230is connected to the short-circuit detection circuit220and the input driving circuit210. The leakage current cancellation circuit230prevents a leakage current produced by the first level voltage (i.e., the supply voltage VDD) from entering the silicon substrate according to the short-circuit detection output signal Sds. Namely, when the short-circuit detection circuit220determines that a short circuit occurs between the TSV110and the silicon substrate, the leakage current cancellation circuit230instantly shuts off the power supply through a power control circuit240and prevents the leakage current from entering the silicon substrate by, for example, connecting the first terminal of the TSV110to the ground voltage GND through a short-circuit protection circuit250, so as to prevent the voltage level on the silicon substrate from drifting.

The bias circuit330is connected to the short-circuit detection circuit220and the leakage current cancellation circuit230. The bias circuit330first turns on the power switch of the power control circuit240in the leakage current cancellation circuit230(i.e., enables the supply voltage VDD) when the TSV repair circuit100just starts working. When the input signal Vin is received, if the short-circuit detection circuit220detects a short circuit between the TSV110(or the TSV111) and the silicon substrate, the short-circuit detection circuit220adjusts the short-circuit detection output signal Sds to control the leakage current cancellation circuit230to turn off the power control circuit240in the leakage current cancellation circuit230and turn on the short-circuit protection circuit250.

In the present embodiment, the leakage current cancellation circuit230includes the power control circuit240and/or the short-circuit protection circuit250. In an application, both or only one of the power control circuit240and the short-circuit protection circuit250can be implemented. The power control circuit240is connected to the short-circuit detection circuit220. The power control circuit240receives the short-circuit detection output signal Sds and determines not to supply the first level voltage (i.e., the supply voltage VDD) to the input driving circuit210according to the short-circuit detection output signal Sds. Namely, when the short-circuit detection circuit220determines that a short circuit occurs between the TSV110and the silicon substrate, the power control circuit240stops supplying the first level voltage (i.e., the supply voltage VDD) to the input driving circuit210, so that the leakage current (for example, the leakage current I1inFIG. 2) produced by the supply voltage VDD when the input driving circuit210transmits the input signal Vin is not supplied to the TSV110and the leakage current is prevented from entering the silicon substrate of the TSV110.

The short-circuit protection circuit250is connected to the short-circuit detection circuit220and the first terminal of the TSV110. The short-circuit protection circuit250determines to connect the first terminal of the TSV110to the ground voltage GND according to the short-circuit detection output signal Sds. Namely, when the short-circuit detection circuit220determines that a short circuit occurs between the TSV110and the silicon substrate, the short-circuit protection circuit250connects the first terminal of the TSV110to the ground voltage GND, so that the leakage current (for example, the leakage current I2inFIG. 2) produced by the supply voltage VDD can be guided by the short-circuit protection circuit250to the ground and the leakage current is prevented from entering the silicon substrate of the TSV110. The input terminal of the output logic circuit140is respectively connected to the second terminals of the first set of TSVs110-111and the second terminals of the second set of TSVs112-113for respectively receiving transmission signals (for example, respectively receiving a first transmission signal St1from the first set of TSVs110-111and a second transmission signal St2from the second set of TSVs112-113). The output logic circuit140generates the output signal Vout according to the transmission signals St1and St2.

FIG. 3illustrates an example of the TSV repair circuit100of a semiconductor apparatus according to the first embodiment of the disclosure. Namely,FIG. 3illustrates the circuit structures of various devices inFIG. 2. Because the data path circuits120-121have the same circuit structure and the input driving circuits210and211, the short-circuit detection circuits220and221, the bias circuits330and331, and the leakage current cancellation circuits230and231are similar circuits, components of the data path circuit120will be described in detail as examples, and components of the data path circuit121can be understood by referring to following descriptions. The input driving circuit210includes a signal inverter310served as an input-stage circuit. The signal inverter310is composed of an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) N1and a P-type MOSFET P1. The control terminals (gates) of the transistors N1and P1receive an input signal and are served as a first terminal of the signal inverter310. The first terminal (source) of the P-type MOSFET P1receives a drain voltage (for example, the supply voltage VDD) from the power control circuit340and is served as a power supply terminal of the signal inverter310. The second terminal (drain) of the P-type MOSFET P1is connected to the first terminal (drain) of the N-type MOSFET N1and is served as an output terminal of the signal inverter310. The output terminal of the signal inverter310is connected to the first terminal of the TSV110(i.e., the node A inFIG. 3). The second terminal (source) of the N-type MOSFET N1receives the ground voltage GND. Thus, the pending signal Va is inverse to the input signal Vin.

The short-circuit detection circuit220includes a NOR gate320. A first receiving terminal of the NOR gate320is connected to the first terminal (i.e., the node A) of the TSV110, a second receiving terminal of the NOR gate320receives the input signal Vin, and an output terminal of the NOR gate320generates the short-circuit detection output signal Sds. The short-circuit detection circuit220further includes the bias circuit330. The first terminal of the bias circuit330is connected to the output terminal of the short-circuit detection circuit220(i.e., the output terminal of the NOR gate320) to maintain the bias of the short-circuit detection output signal Sds. In the present embodiment, the bias circuit330includes a biasing resistor R1. The first end of the biasing resistor R1is respectively connected to the output terminal of the short-circuit detection circuit220, and the second end of the biasing resistor R1receives the second level voltage (i.e., the ground voltage GND).

In other embodiments, the bias circuit330may also be implemented by using a P-type MOSFET or an N-type MOSFET or may even be omitted.FIG. 4AandFIG. 4Bare circuit diagrams of the bias circuit330inFIG. 3according to other embodiments. The bias circuit330inFIG. 4Aincludes an N-type MOSFET N2. The drain and gate of the N-type MOSFET N2are connected to the output terminal of the short-circuit detection circuit220inFIG. 3, and the source of the N-type MOSFET N2receives the ground voltage GND so that the bias circuit330can have sufficient biasing resistance. The bias circuit330inFIG. 4Bincludes a P-type MOSFET P2. The source of the P-type MOSFET P2is connected to the output terminal of the short-circuit detection circuit220inFIG. 3, and the drain and gate of the P-type MOSFET P2receive the ground voltage GND so that the bias circuit330can have sufficient biasing resistance.

Referring toFIG. 3, the power control circuit240includes a first switch340. In the present embodiment, the first switch340is implemented by using a P-type MOSFET P3. The source of the P-type MOSFET P3receives the supply voltage VDD, the drain of the P-type MOSFET P3is connected to the power supply terminal of the input driving circuit210, and the gate of the P-type MOSFET P3receives the short-circuit detection output signal Sds. In other embodiments, the power control circuit240may also be as that illustrated inFIG. 4C.FIG. 4Cis a circuit diagram of the power control circuit240inFIG. 3according to another embodiment. The power control circuit240further includes a first inverter1160and a second inverter1170. The input terminal of the first inverter1160receives the short-circuit detection output signal Sds, the output terminal of the first inverter1160is connected to the input terminal of the second inverter1170, and the output terminal of the second inverter1170is connected to the control terminal of the first switch340. Thus, the control terminal of the first switch340can receive the short-circuit detection output signal Sds through the first inverter1160and the second inverter1170, and accordingly the transmission accuracy of the short-circuit detection output signal Sds can be improved.

The short-circuit protection circuit250includes a second switch350. In the present embodiment, the second switch350is implemented by using an N-type MOSFET N3. The drain of the N-type MOSFET N3is connected to the first terminal of the TSV110(i.e., the node A), the source of the N-type MOSFET N3is connected to the ground voltage GND, and the gate of the N-type MOSFET N3receives the short-circuit detection output signal Sds.

Because the input driving circuit210inFIG. 3is implemented by using the signal inverter310, the input signal Vin is inversed when it is transformed into the pending signal Va. The output logic circuit140disposed at the second chip CHIP2includes an NOR gate360with two receiving terminals. The first receiving terminal and the second receiving terminal of the NOR gate360respectively receive the first transmission signal St1at the node C and the second transmission signal St2at the node D, and the NOR gate360outputs the corrected signal through the output terminal Vout.

The difference between the data path circuit120and the data path circuit121is that the input driving circuit311of the data path circuit121generates a pending signal Vb and transmits the pending signal Vb to the first terminal of the TSV112(i.e., the node B). The input driving circuit211of the data path circuit121is implemented by using a signal inverter311, and the signal inverter311is composed of an N-type MOSFET N4and a P-type MOSFET P4. The short-circuit detection circuit221is composed of a NOR gate321, and the bias circuit331is composed of a resistor R2. The first switch341of the power control circuit241is composed of a P-type MOSFET P5, and the second switch351of the short-circuit protection circuit251is composed of an N-type MOSFET N5.

Based on that described above, the operation of the TSV repair circuit100illustrated inFIG. 3can be reflected by following true value table (1):

Referring to bothFIG. 3and foregoing table (1), states 1 and 2 represent the normal state of the TSVs110and112(i.e., no short circuit is produced between the TSVs110and112and the silicon substrate). Herein due to the signal inverters310and311in the input driving circuits210and211, the pending signals Va and Vb are inverse to the input signal Vin.

In the state 1, the input signal Vin is logic “1”, and both the pending signals Va and Vb are logic “0”. Thus, the short-circuit detection output signals Sds1and Sds2respectively generated by the NOR gates320and321of the short-circuit detection circuits220and221are both logic “0”. Accordingly, the power control circuits240and241continue to supply a voltage (for example, the supply voltage VDD) to the input driving circuits310and311, and the short-circuit protection circuits250and251are turned off. To be specific, the P-type MOSFETs P3and P5served as the first switches340and341are turned on, so that the supply voltage VDD is guided to the input driving circuits210and211to continuously transform the input signal Vin into the pending signals Va and Vb. On the other hand, the N-type MOSFETs N3and N5served as the second switches350and351are turned off, so that the nodes A and B are not connected to the ground. Moreover, the NOR gate360of the output logic circuit140generates a correct output signal Vout (logic “1”) because both the transmission signals St1and St2are logic “0”.

In the state 2, the input signal Vin is logic “0”, and both the pending signals Va and Vb are logic “1”. Thus, the short-circuit detection output signals Sds1and Sds2respectively generated by the NOR gates320and321of the short-circuit detection circuits220and221are logic “0”. Accordingly, the first switches340and341are both turned on and the second switches350and351are both turned off. Because the two transmission signals St1and St2are both logic “1”, the output logic circuit140generates an output signal Vout (logic “0”).

States 3 and 4 represent a short-circuited state of the TSV110(i.e., a short circuit is produced between the TSV110and the silicon substrate while the TSV112is in a normal state). In this case, the voltage levels on the pending signal Va (node A) and the first transmission signal St1(node C) are pulled down to logic “0” due to the short circuit of the TSV110. In the state 3, the input signal Vin is logic “1”. Because the pending signal Va in state 3 is logic “0”, the operation of the TSV repair circuit100is the same as that in the state 1, and the output logic circuit140also generates a correct output signal Vout (logic “1”), just as in state 1.

In the state 4, the input signal Vin is logic “0”, and the voltage levels on the pending signal Va and the first transmission signal St1are pulled down to logic “0” due to the short circuit, and the pending signal Vb is still logic “1” (i.e., inverse to the input signal Vin). Thus, the short-circuit detection output signal Sds1generated by the NOR gate320is logic “1”, and the short-circuit detection output signal Sds2generated by the NOR gate321is logic “0”. Accordingly, the P-type MOSFET P3served as the first switch340is turned off, and the supply voltage VDD is not supplied to the input driving circuit210anymore to prevent the production of any leakage current. On the other hand, the N-type MOSFET N3served as the second switch350is turned on so that the leakage current which is about to enter the TSV110is guided to the ground. The operation of the first switch341and the second switch351are the same as that in the state 2. Thus, in the state 4, the NOR gate360of the output logic circuit140respectively receives the first transmission signal St1(logic “0”) and the second transmission signal St2(logic “1”) to allow the NOR gate360to generate a correct output signal Vout (logic “0”).

States 5 and 6 represent the normal state of the TSV110and the short-circuited state of the TSV112(i.e., a short circuit is produced between the TSV112and the silicon substrate only). Herein the voltage levels on the pending signal Vb (node B) and the second transmission signal St2(node D) are pulled down to logic “0” due to the short circuit of the TSV112. In the state 5, the input signal Vin is logic “1”. Because the pending signal Vb in the state 5 is logic “0” (i.e., inverse to the input signal Vin), the operation of the TSV repair circuit100is the same as that in the state 1, and the NOR gate360also generates a correct output signal Vout (logic “1”).

In the state 6, the input signal Vin is logic “0”, and the voltage levels on the pending signal Vb and the second transmission signal St2are pulled down to logic “0” due to the short circuit, and the pending signal Va is still logic “1” (i.e., inverse to the input signal Vin). Thus, the short-circuit detection output signal Sds2generated by the NOR gate321is logic “1”, and the P-type MOSFET P5served as the first switch341is turned off, so that the supply voltage VDD is not supplied to the input driving circuit211anymore. Accordingly, the N-type MOSFET N5served as the second switch351is turned on, so that the leakage current which is about to enter the TSV112is guided to the ground. The operation of the first switch340and the second switch350are the same as that in the state 2. Thus, the NOR gate360respectively receives the first transmission signal St1(logic “1”) and the second transmission signal St2(logic “0”) to allow the NOR gate360to generate a correct output signal Vout (logic “0”).

States 7 and 8 represent the short-circuited state of both the TSVs110and112. In the state 7, the input signal Vin is logic “1”. Because the pending signals Va and Vb are originally logic “0” (inverse to the input signal Vin), the operation of the TSV repair circuit100is the same as that in the state 1, and the output logic circuit140also generates a correct output signal Vout (logic “1”), just as that in state 1.

It should be noted that in the state 8, because the input signal Vin is logic “0” and the voltage levels on the pending signals Va and Vb and the transmission signals St1and St2are all pulled down to logic “0” due to the short circuit, the short-circuit detection output signals Sds1and Sds2respectively generated by the NOR gates320and321are both logic “1”. Accordingly the P-type MOSFETs P3and P5are turned off, and the supply voltage VDD is not supplied to the input driving circuits210and211anymore. On the other hand, the N-type MOSFETs N3and N5are turned on, so that the leakage current which is about to enter the TSVs110and112is guided to the ground. In addition, the NOR gate360respectively receive an incorrect first transmission signal St1(logic “0”) and an incorrect second transmission signal St2(logic “0”), so that the NOR gate360cannot self-repair and generates an incorrect output signal Vout (logic “1”). Even though the TSV repair circuit100inFIG. 3cannot perform a correct data self-repair mechanism regarding the state 8 in foregoing table (1), the problem mentioned above can be resolved by adding another data path circuit and corresponding TSVs.

FIG. 5is a diagram of a TSV repair circuit400of a semiconductor apparatus according to a second embodiment of the disclosure. The TSV repair circuit400in the present embodiment is similar to the TSV repair circuit100described in foregoing embodiment, and the major difference between the two embodiments is that the TSV repair circuit400is implemented with three or more data paths (i.e., three or more data path circuits120-122with TSVs110-112running through a silicon substrate730). Namely, in the present embodiment, the problem of short circuit between all the TSVs and the silicon substrate can be resolved by increasing the numbers of TSVs and data path circuits. In other words, in the present embodiment, the output logic circuit140can restore the output signal Vout through a NOR gate thereof as long as a correct signal is transmitted to the output logic circuit140through one of the data paths.

FIG. 6is a circuit diagram of the TSV repair circuit400of a semiconductor apparatus according to the second embodiment of the disclosure. In other words,FIG. 6is a circuit diagram of the TSV repair circuit400inFIG. 5. The TSV repair circuit400inFIG. 6has three data paths (i.e., three data path circuits120-122with corresponding TSVs110-112) for transmitting the input signal Vin, such that the second terminals of the TSVs110-112respectively generate a plurality of transmission signals St1-St3. The output logic circuit140includes a NOR gate660with three receiving terminals. The first, second, and third receiving terminal of the NOR gate660respectively receive the first, second, and third transmission signals St1-St3, and the output terminal of the NOR gate660generates the output signal Vout. Those operations and functions not mentioned in the third embodiment can be referred to the embodiments described above therefore will not be described herein.

FIG. 7is a circuit diagram of a TSV repair circuit700of a semiconductor apparatus according to a third embodiment of the disclosure. The difference between the embodiments respectively illustrated inFIG. 7andFIG. 6is that in the TSV repair circuit700, the data path circuits720-722further respectively include the first inverters1160-1162and the second inverters1170-1172besides the first switches1150-1152in the power control circuits1140-1142. The control terminals of the first switches1150-1152respectively receive the short-circuit detection output signals Sds1-Sds3through the first inverters1160-1162and the second inverters1170-1172, s that the transmission accuracy of the short-circuit detection output signals Sds1-Sds3is improved.

FIG. 8is a diagram of a TSV repair circuit800of a semiconductor apparatus according to a fourth embodiment of the disclosure. The TSV repair circuit800is very flexible in the application of the 3DIC technology and can be applied when multiple chips are stacked. For example, the data path circuits720and721in the TSV repair circuit800are not limited to being disposed on the topmost chip. Instead, they can be disposed on any chip. The output logic circuit740inFIG. 8can be disposed on the second chip CHIP2and a third chip CHIP3or on any number of chips, so that the output logic circuit740can generate a plurality of output signals Vout1-Vout3on different chips. Accordingly, the first chip CHIP1can properly transmit the input signal Vin to the second chip CHIP2, the third chip CHIP3, and/or any other chips. The second chip CHIP2not disposed with the data path circuits and the adjacent chips (for example, the third chip CHIP3) transmit data to each other through the TSVs710and711running through the silicon substrate.

FIG. 9is a diagram of a TSV repair circuit900according to a fifth embodiment of the disclosure. In the TSV repair circuit900of the present embodiment, the data path circuits720and721and the output logic circuit740are disposed on each chip, and the output logic circuits740on different chips respectively generate a plurality of output signals Vout1-Vout3. The circuit structure is illustrated inFIG. 9. Based on the circuit structure inFIG. 9, the input signal Vin can be properly transmitted from the first chip CHIP1to the chip CHIP2or CHIP3as long as the TSVs710and711disposed on the same CHIP1, CHIP2, or CHIP3are not short-circuited at the same time. If the TSVs710and711disposed on the same chip are both short-circuited, in the present embodiment, the problem of signal transmission error on both data paths can be resolved by disposing one or more additional data paths. The input terminals of the data path circuits720and721disposed in each chip are connected to the output terminal of the output logic circuit740in the chip.

As described above, in a data transmission apparatus provided by an embodiment of the disclosure, a short circuit between a TSV and a silicon substrate is detected according to an input signal and the voltage level on a first terminal of the TSV, and when the short circuit is detected, a supply voltage is instantly shut off and the first terminal of the TSV is connected to a ground voltage, so that a leakage current is prevented from entering the silicon substrate and the voltage level on the silicon substrate is prevented from drifting. In addition, in a TSV repair circuit provided by an embodiment of the disclosure, besides adopting the circuit structure of the data transmission apparatus described above to achieve the same purpose, an output logic circuit is further disposed on a receiving chip, so that a plurality of transmitted signals can be restored into correct signals, and a 3DIC can work properly even when some TSVs are short-circuited.