MRAM structure and method of fabricating the same

An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a magnetic random access memory (MRAM) structure and a method of fabricating the same, and more particularly to an MRAM without an MTJ deformation and a method of fabricating the same.

2. Description of the Prior Art

Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data only while it is powered, while non-volatile memory is able to store data when power is removed. MRAM is one promising candidate for next generation non-volatile memory technology. An MRAM cell includes a magnetic tunnel junction (MTJ) having a variable resistance, located between two electrodes disposed within back-end-of-the-line (BEOL) metallization layers.

An MTJ generally includes a layered structure comprising a reference layer, a free layer and a dielectric barrier in between. The reference layer of magnetic material has a magnetic vector that always points in the same direction. The magnetic vector of the free layer is free, but is determined by the physical dimensions of the element. The magnetic vector of the free layer points in either of two directions: parallel or anti-parallel with the magnetization direction of the reference layer.

Conventional MRAMs have some disadvantages, for example, the deformation of the MTJ because of the stress within the material layer around the MTJ. Therefore an improved MRAM structure is required in the field.

SUMMARY OF THE INVENTION

According to a first preferred embodiment of the present invention, an MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.

According to another preferred embodiment of the present intention, a method of fabricating an MRAM structure includes providing a dielectric layer, wherein a first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, the second MRAM are disposed between the first MRAM and the third MRAM, two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM and the second MRAM comprises an MTJ. Later, a first compressive stress layer is formed to cover the first MRAM, the second MRAM, the third MRAM and the dielectric layer. Subsequently, a tensile stress material layer is formed to cover the first compressive stress layer and fill in the two gaps. Next, the tensile stress material layer outside of the two gaps is removed to form two tensile stress pieces in each of the two gaps. Finally, a second compressive stress layer is formed to cover an opening of each of the two gaps and contacting the tensile stress pieces.

According to yet another preferred embodiment of the present intention, An MRAM structure includes a dielectric layer. A plurality of MRAMs are disposed on the dielectric layer and the plurality of MRAMs are arranged in one row, wherein the plurality of MRAMs include an end MRAM disposed at an end of the row. A dummy MRAM is disposed on the dielectric layer and at one side of the end MRAM. A gap is disposed between the end MRAM and the dummy MRAM. A first compressive stress layer contacts a sidewall of the gap. A tensile stress piece is disposed within the gap. A second compressive stress layer covers an opening of the gap and contacts the tensile stress piece. A plurality of metal interconnections respectively contacting each of the plurality of MRAMs.

DETAILED DESCRIPTION

FIG.1toFIG.6depict a fabricating method of an MRAM structure according to a preferred embodiment of the present invention.FIG.7depicts a fabricating stage of an etching back step according to a preferred embodiment of the present invention.FIG.8depicts another fabricating stage of an etching back step according to another preferred embodiment of the present invention.

As shown inFIG.1, a dielectric layer10is provided. The dielectric layer10is divided into a memory cell region A and a peripheral circuit region B. Numerous MRAMs are arranged in an array. For example, a first MRAM M1, a second MRAM M2and a third MRAM M3are disposed on the dielectric layer10from right to left in a row. The second MRAM M2is disposed between the first MRAM M1and the third MRAM M3. Moreover, the first MRAM M1is disposed at the end of the row. Therefore, the first MRAM M1is defined as an end MRAM in the row. Moreover, a dummy MRAM DM is disposed on the dielectric layer10and at one side of the first MRAM M1.

Furthermore, the first MRAM M1, the second MRAM M2, the third MRAM M3and the dummy MRAM DM are respectively includes a top electrode12, an MTJ14and a bottom electrode15. Numerous gaps18are respectively disposed between two adjacent MRAMs. For example, the gap18can be disposed between the dummy MRAM DM and the first MRAM M1, between the first MRAM M1and the second MRAM M2, or between the second MRAM M2and the third MRAM M3.

Moreover, numerous metal interconnections20are arranged within the dielectric layer10. The metal interconnections20electrically connect to the bottom electrode15of the first MRAM M1, the bottom electrode15of the second MRAM M2, the bottom electrode15of the third MRAM M3, and the bottom electrode15of the dummy MRAM DM through a bottom conductive line16.

Next, a first compressive stress layer22is formed to cover the first MTJ M1, the second MRAM M2, the third MRAM M3, the dummy MRAM DM and the dielectric layer10. The first compressive stress layer22contains compressive stress, therefore the first compressive stress layer22is smaller in porosity. In this way, the first compressive stress layer22can block moisture or oxygen. By forming the first compressive stress layer22to cover the first MTJ M1, the second MRAM M2, the third MRAM M3and the dummy MRAM DM, the moisture or oxygen can be prevented from getting into the first MTJ M1, the second MRAM M2, the third MRAM M3and the dummy MRAM DM. According to a preferred embodiment of the present invention, a thickness of the first compressive stress layer22greater than 50 angstroms is a thickness enough to block moisture or oxygen. The first compressive stress layer22can be silicon nitride, silicon oxide, silicon oxynitride or other insulating materials. In this embodiment, the first compressive stress layer22is preferably silicon nitride.

As shown inFIG.2, the first compressive stress layer22is etched back to thin the first compressive stress layer22and to remove part of the first compressive stress layer22. Moreover, the etching rate of the etching back can be adjusted based on different requirements. For example, inFIG.2, the first compressive stress layer22still entirely covers the first MTJ M1, the second MRAM M2, the third MRAM M3and the dummy MRAM DM after the etching back. In other words, the entire sidewall and the top surface of the first MRAM M1, the entire sidewall and the top surface of the second MRAM M2, the entire sidewall and the top surface of the third MRAM M3, and the entire sidewall and the top surface of the dummy MRAM DM are covered by the first compressive stress layer22. Moreover, all of the gaps18are also entirely covered by the first compressive stress layer22.

As shown inFIG.7, according to another preferred embodiment of the present invention, the first compressive stress layer22is etched back until the top surface of the first MRAM M1, the top surface of the second MRAM M2, the top surface of the first MRAM M3and the top surface of the dummy MRAM DM are exposed. The top surface mentioned above includes the top electrode12of the first MRAM M1, the top electrode12of the second MRAM M2, the top electrode12of the third MRAM M3and the top electrode12of the dummy MRAM DM.

As shown inFIG.8, according to yet another preferred embodiment of the present invention, the first compressive stress layer22is etched back until the top surface of the first MRAM M1, the top surface of the second MRAM M2, the top surface of the first MRAM M3, the top surface of the dummy MRAM DM and the bottoms of the gaps18are exposed. The etching back described inFIG.2,FIG.7andFIG.8features in that at least the first compressive stress layer22surrounding and contacting the entire sidewall of the first MRAM M1, the entire sidewall of the second MRAM M2, the entire sidewall of the third MRAM M3, and the entire sidewall of the dummy MRAM DM are kept. In this way, moisture and oxygen can be prevented from entering the MTJ14.

The free layer, the reference layer, the interlayer exchange coupling (IEC) material layer and the perpendicular magnetic anisotropic (PMA) material layer are formed by pure metal films. Because elastic modulus of the metal films are low, the free layer, the reference layer, the IEC material layer, the PMA material layer or other metal films in the sidewall of the MTJ14are deformed due to the contact of the first compressive stress layer22. However, the free layer, the reference layer, the IEC material layer, the PMA material layer or other metal films at the center of the MTJ14are not deformed because they are not contacted by the first compressive stress layer22. In this way, the shape of the MTJ14becomes asymmetric and lead to unstable performance of the MRAM structure.

Therefore, a solution for preventing the deformation will be provided in the following description. The following steps will be presented in continuous ofFIG.2. As shown inFIG.3, a tensile stress material layer24is formed to cover the first compressive stress layer22and fills in each of the gaps18. The tensile stress material layer24includes silicon nitride, silicon oxide, silicon oxynitride or other insulating materials. According to a preferred embodiment of the present invention, the tensile stress material layer24is silicon oxide. As shown inFIG.4, the tensile stress material layer24outside of the gaps18is removed. The tensile stress material layer24remains in each of the gaps18becomes a tensile stress piece26. There are three tensile stress pieces26shown in this embodiment as an example. The tensile stress pieces26and the tensile stress material layer24are made of the same material. Moreover, an absolute value of a tensile stress in each of the tensile stress pieces26is the same as an absolute value of a tensile stress in the first compressive stress layer22. In other way, a difference between the absolute value of the tensile stress in each of the tensile stress pieces26and the absolute value of the tensile stress in the first compressive stress layer24is smaller than a predetermined ratio. The predetermined ratio relates to deformation resistances of metal films in the MTJ14. The tensile stress in the tensile stress pieces26can decrease or neutralize the compressive stress applying to the sidewall of the MTJ14by the first compressive stress layer22, and prevents the metal films from deformation.

Please still refer toFIG.4, a second compressive stress layer28is formed to cover the opening of each of the gaps18, contact each of the tensile stress pieces26and cover the first MTJ M1, the second MRAM M2, the third MRAM M3, the dummy MRAM DM and the first compressive stress layer22at the peripheral circuit region B. Similar to the first compressive stress layer22, the second compressive stress layer28contains a compressive stress; therefore moisture or oxygen can be blocked by the second compressive stress layer28. In this way, the moisture or oxygen can be prevented from entering the tensile stress pieces26. Because if the tensile stress pieces26absorb moisture and oxygen, the tensile stress in the tensile stress pieces26decreases and even transform into a compressive stress. Therefore, it is essential to protect the tensile stress pieces26by the second compressive stress layer28. Furthermore, the thickness of the second compressive stress layer28is smaller than the thickness of the first compressive stress layer22. According to a preferred embodiment of the present invention, the thickness of the second compressive stress layer28is about 10 angstroms.

As shown inFIG.5, a photoresist30is formed to cover the memory cell region A. Then, an etching process is performed to remove the first compressive stress layer22and the second compressive stress layer28within the peripheral circuit region B. Based on different requirements, the steps of removing the first compressive stress layer22and the second compressive stress layer28within the peripheral circuit region B can be omitted. That is, the first compressive stress layer22and the second compressive stress layer28within the peripheral circuit region B are remained. The following description is presented by removing the first compressive stress layer22and the second compressive stress layer28within the peripheral circuit region B as an example.

As shown inFIG.6, the photoresist30is removed. Then, an interlayer dielectric32is formed to cover the memory cell region A and the peripheral circuit region B. Later, numerous metal interconnections34are formed to penetrate the interlayer dielectric32. The metal interconnections34respectively contact the top electrode12of the first MRAM M1, the top electrode12of the second MRAM M2and the top electrode12of the third MRAM M3. Moreover, the metal interconnections34are also formed within the peripheral circuit region B. It is noteworthy that there is no tensile stress piece26disposed at one side of the dummy MRAM DM. Therefore, one sidewall of the dummy MRAM DM sustained a compressive stress, but other sidewall of the dummy MRAM DM does not have any stress. Under this circumstance, the stress in two sides of the dummy MRAM DM is not match. This leads to unstable performance of the dummy MRAM DM. To solve this problem, the dummy MRAM DM is disabled on purpose to prevent the dummy MRAM DM to influence the efficiency of the MRAM structure. Therefore, in this embodiment, the dummy MRAM DM is disabled by not disposing any metal interconnections34on the top electrode14of the dummy MRAM DM. According to another preferred embodiment of the present invention, the dummy MRAM DM is disabled by not disposing any metal interconnections34below the bottom electrode15of the dummy MRAM DM.

As shown inFIG.6, a MRAM structure includes a dielectric layer10. numerous MRAMs are arranged in an array. For example, a first MRAM M1, a second MRAM M2and a third MRAM M3are disposed on the dielectric layer10from right to left in a row. The second MRAM M2is disposed between the first MRAM M1and the third MRAM M3. Moreover, the first MRAM M1is disposed at the end of the row. Therefore, the first MRAM M1is defined as an end MRAM in the row. Moreover, a dummy MRAM DM is disposed on the dielectric layer10and at one side of the first MRAM M1. Furthermore, the first MRAM M1, the second MRAM M2, the third MRAM M3and the dummy MRAM DM are respectively formed of a top electrode12, an MTJ14and a bottom electrode15. Numerous gaps18are respectively disposed between the dummy MRAM DM and the first MRAM M1, the first MRAM M1and the second MRAM M2, the second MRAM M2and the third MRAM M3.

Moreover, numerous metal interconnecting structures36respectively electrically connect to each of the MRAMs. In details, the metal interconnecting structures36includes metal interconnections20and metal interconnections34. The metal interconnections20are disposed within the dielectric layer10. The metal interconnections20respectively contact and electrically connect the bottom electrode15of the first MRAM M1, the bottom electrode15of the second MRAM M2, the bottom electrode15of the third MRAM M3and the bottom electrode15of the dummy MRAM DM through a bottom conductive line16.

Numerous metal interconnections34respectively contact the top electrode12of the first MRAM M1, the top electrode12of the second MRAM M2and the top electrode12of the third MRAM M3. It is noteworthy that there is no metal interconnection34on the top electrode12of the dummy MRAM DM.

As shown inFIG.8, a first compressive stress layer22surrounds the entire sidewall and the top surface of the first MRAM M1, the entire sidewall and the top surface of the second MRAM M2, the entire sidewall and the top surface of the third MRAM M3, and the entire sidewall and the top surface of the dummy MRAM DM. At this point, the top surface of the first MRAM M1is not covered by the first compressive stress layer22. Similarly, the top surface of the second MRAM M2and the top surface of the third MRAM M3are also not covered by the first compressive stress layer22. Furthermore, the bottom of the gaps18can be not covered by the first compressive stress layer22as well.

According to another preferred embodiment, as shown inFIG.7, the first compressive stress layer22not only surrounds the entire sidewall of the MTJ14, but also covers the bottom of the gaps18.

Please refer toFIG.6again, according to yet another preferred embodiment of the present invention, besides covering the entire sidewall of the MTJ14and the bottom electrode of the gaps18shown inFIG.7, as shown inFIG.6, the first compressive stress layer22can also cover the top surface of the first MRAM M1, the top surface of the second MRAM M2, the top surface of the first MRAM M3and the top surface of the dummy MRAM DM.

Please still refer toFIG.6, numerous tensile stress pieces26respectively disposed in each of the gaps18. The tensile stress in tensile stress pieces26can decreases or neutralizes the compressive stress applying to the sidewall of the MTJ14by the first compressive stress layer22, and prevents the sidewall of the MTJ14from deformation. The first compressive stress layer22covers the bottom of the tensile stress pieces26. An absolute value of a tensile stress in each of the tensile stress pieces26may be the same as an absolute value of a tensile stress in the first compressive stress layer22. In other way, a difference between the absolute value of the tensile stress in each of the tensile stress pieces26and the absolute value of the tensile stress in the first compressive stress layer24is smaller than a predetermined ratio. The predetermined ratio relates to deformation resistances of metal films in the MTJ14. For example, if the stress of the first compressive stress layer22is −100 MPa, the stress in each of the tensile stress pieces26can be between 70 and 130 Mpa, which means the difference between the absolute value of the tensile stress in each of the tensile stress pieces26and the absolute value of the tensile stress in the first compressive stress layer24is smaller than 30%. Base on the deformation resistances of metal films in the MTJ14, the top electrode12and the bottom electrode15, the difference can be between 0% and 50%. According to a preferred embodiment of the present invention, while the stresses in the first compressive stress layer22and in the tensile stress pieces26neutralize each other, there is no stress on the sidewall of the MTJ14.

A second compressive stress layer28covers the opening of each of the gaps18and contacts each tensile stress piece26. The thickness of the second compressive stress layer28is preferably not greater than the thickness of the first compressive stress layer22. A thickness of the first compressive stress layer22is preferably not smaller than 50 angstroms. A thickness of the second compressive stress layer28is preferably about 10 angstroms. The first compressive stress layer22, the second compressive stress layer28and the tensile stress pieces26can include silicon nitride, silicon oxide, silicon oxynitride or other insulating materials. According to a preferred embodiment of the present invention, the tensile stress pieces26are formed by silicon oxide. The first compressive stress layer22and the second compressive stress layer28are both formed by silicon nitride.

Please refer toFIG.9.FIG.9depicts an MRAM structure according to another preferred embodiment of the present invention, wherein elements which are substantially the same as those in the embodiment ofFIG.6are denoted by the same reference numerals; an accompanying explanation is therefore omitted. The difference between the MRAM structures inFIG.9and inFIG.6is that the first compressive stress layer22inFIG.9does not cover the top surface of the first MRAM M1, the top surface of the second MRAM M2, the top surface of the third MRAM M3and the top surface of the dummy MRAM DM. Other elements have the same positions and materials.

Please refer toFIG.10.FIG.10depicts an MRAM structure according to yet another preferred embodiment of the present invention, wherein elements which are substantially the same as those in the embodiment ofFIG.6are denoted by the same reference numerals; an accompanying explanation is therefore omitted. The difference between the MRAM structures inFIG.10and inFIG.6is that the first compressive stress layer22inFIG.10only surrounds the entire sidewall of the MTJ14. Other elements have the same positions and materials.