Polygon integrated circuit (IC) packaging

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

FIELD OF THE EMBODIMENTS

Embodiments of the present invention generally relate to integrated circuit (IC) device packages, and more particularly to an IC device package that includes a polygon IC device and/or a polygon IC carrier.

DESCRIPTION OF THE RELATED ART

Future requirements for data handling systems may force IC packaging design changes, such as reduction of size of IC packaging system, reduction of the number of input/output (I/O) between the IC device and the IC device carrier, etc. Typical IC device and IC carrier manufacturing has required or resulted in rectangular or square designs. However, the square corners of these designs typically do not allow for I/O therefrom.

SUMMARY

In an embodiment of the present invention, an electronic system is presented. The system includes a first integrated circuit (IC) device package, a second IC device package, and a package to package (PP) connector. The first IC device package includes a first carrier, a first IC device connected to a top surface of the first carrier (first carrier top surface), a first cover connected to the first IC device and connected to the first carrier top surface, and a first carrier connector connected to the first carrier top surface. The second IC device package includes a second carrier, a second IC device connected to a top surface of the second carrier (second carrier top surface), a second cover connected to the second IC device and connected to the second carrier top surface, a second carrier connector connected to the second carrier top surface. The PP connector includes cabling connected to a first cabling connector and a second cabling connector. The first cabling connector is seated to the first carrier connector and the second cabling connector is seated to the second carrier connector.

In another embodiment of the present invention, an electronic system fabrication method is presented. The method includes connecting a first integrated circuit (IC) device package to a system board, connecting a second IC device package to the system board, seating a first cabling connector of a package to package (PP) connector to the first carrier connector, and seating a second cabling connector of the PP connector to the second carrier connector. The first IC device package includes a first carrier, a first IC device connected to a top surface of the first carrier (first carrier top surface), a first cover connected to the first IC device and connected to the first carrier top surface, and a first carrier connector connected to the first carrier top surface. The second IC device package includes a second carrier, a second IC device connected to a top surface of the second carrier (second carrier top surface), a second cover connected to the second IC device and connected to the second carrier top surface, and a second carrier connector connected to the second carrier top surface. The PP connector includes cabling connected to the first cabling connector and the second cabling connector.

In another embodiment of the invention, a data output method is presented. The method includes receiving, with a first integrated circuit (IC) device package, a request to send data to a destination device. The method further includes sending, with the first IC device package, the data to a second IC device package that neighbors the first IC device package across a package to package (PP) connector. The method further includes sending, with the second IC device package, the data to the destination device.

These and other embodiments, features, aspects, and advantages will become better understood with reference to the following description, appended claims, and accompanying drawings.

DETAILED DESCRIPTION

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

FIG. 1depicts a normal view of an IC device carrier100, according to one or more embodiments of the present invention. Carrier100has a polygonal normal shape and may be an organic carrier and is configured to carry a single IC device200, exemplarity shown inFIG. 3B. For example, carrier100may have a hexagonal normal shape as depicted. Carrier100provides mechanical support for an IC device and includes electrical paths there within. For example, carrier100may include electrical paths101, exemplary shown inFIG. 3B, there within.

Carrier100includes an IC device region110and one or more connector regions120. IC device region110may be a footprint of the IC device which is supported by carrier100and may extend from the top surface102to the bottom surface104of carrier100. The surface area of region110may be relatively larger upon surface104relative to that upon surface102. IC device region110includes contacts112upon surface102and includes contacts112upon surface104. Contacts within region110may be associated with I/O between the IC device and a higher level system or mother board. Within region110, a path101may connect a contact112upon surface102with a contact112upon surface104. Region110may have a polygonal normal shape and may be the same polygonal shape as carrier100.

Connector region120may be a footprint of a connector of a package to package (PP) connector150, exemplary shown inFIG. 2, and may extend from the top surface102to the bottom surface104of carrier100. The surface area of region110may be relatively larger upon surface104relative to that upon surface102. Connector region120includes contacts112upon surface102and may further includes contacts112upon surface104. A contact within region120may be associated with I/O between the IC device and a neighboring IC device upon a different neighboring package. Another contact112within region120may be associated with I/O between the neighboring IC device and the higher level system or mother board. A path101may connect a contact112upon surface102within region120with a contact112upon surface102within region110. Another path101may connect a contact112upon surface102within region120with a contact112upon surface104within region120or within region110. Contact112is electrically conductive and may be a pad, pin, receptacle, socket, or the like.

FIG. 2depicts an isometric view of PP connector140, according to one or more embodiments of the present invention. PP connector140includes a pair of carrier connectors150, a pair of cabling connectors142, and cabling connecting the pair of cabling connectors142. A first carrier connector150is configured to mount to surface102of a first carrier100and the second carrier connector is configured to mount to surface102of a second different carrier100. Connector150may include numerous conductive interconnects, such as wires, or the like, as is known in the art. Each of these conductive interconnects may be electrically connected to a contact112or to a path101within region120of the associated carrier100. Cabling144may include numerous insulated wires, with each connected with a conductive interconnect within connector142. The connector142may be seated to connector150such that the interconnect within connector142becomes in contact with the interconnect within connector150. When the first connector142is seated upon the first connector150and when the second connector142is seated upon the second connector150, numerous electrical paths (provided by PP connector140) exist between paths101of the first carrier100and paths101of the second carrier100. Connector142may include a major planar top surface. The term “major planar top surface” is defined herein to mean that the majority of the top surface area is on the same plane. The major planar top surface of connector142may be parallel with the top surface102of carrier100.

FIG. 3AandFIG. 3Bdepicts views of an IC package at various fabrication stages, according to one or more embodiments of the present invention.FIG. 3Adepicts a normal view of IC package250at a fabrication stage where an IC device200is connected to IC device carrier100.FIG. 3Bdepicts a cross section view of IC package250at a fabrication stage where a cover252is connected to the IC device200and to the carrier100and where connector150is connected to carrier100.

IC device200may be an IC chip, die, processor, microchip, field programmable gate array, or other type of data processing or storage device, that is configured to be connected to its own carrier100. IC device200may be connected to carrier100by interconnects210. An interconnect210is conductive and is configured to electrically connects a contact204of IC device200with a contact112on the upper surface102of carrier100. Interconnect210may be a wire, solder, stud, conductive ball, conductive button, socket, receptacle, or the like. IC device200may have a polygonal normal shape and may be the same polygonal shape as carrier100.

IC device200may be further connected to carrier100by underfill211. Underfill211may be electrically-insulating, may substantially surround interconnects210, may isolate individual interconnects210, and may provide mechanical support between IC device200and carrier100. Underfill211may also prevent damage to individual interconnects210due to thermal expansion mismatches between IC device200and carrier100.

When IC device200is connected to carrier100, a reflow process may be performed to join interconnects112to electrical contacts204of IC device200and contacts112upon surface102of carrier100. When IC device200is connected to carrier100, an electrical or current path is formed from a path202within IC device200to a path101within carrier101.

Cover252may be connected to IC device200by thermal interface material (TIM)205that may be applied upon the top surface of IC device200or upon the underside of cover252. Cover252may be connected to carrier100by adhesive or seal band material. Cover252may have a polygonal normal shape and may be the same polygonal shape as carrier100.

Connector150may be connected to carrier100by solder interconnects, pin and hole interconnects, or the like. When connector150is connected to carrier100its conductive interconnects become electrically connected to a contact112or to a path101of carrier100.

Package250may be formed upon when the IC device200is connected to carrier100, cover252is connected to IC device200and to carrier100, and a desired number of connectors150are connected to carrier150.

FIG. 4depicts a cross section view of an electronic system300at a particular fabrication stage, according to one or more embodiments of the present invention. At the present fabrication stage, a plurality of packages250are connected to a system board301.

System board301may be the main system or mother board of system300. System board301may be fabricated as an organic system board, as is known in the art. System board301provides mechanical support for numerous IC packages250. Board301may further provide mechanical support for other computing devices such as hard drives, memory modules, and may include connectors so that peripheral devices may connect there to, or the like. System board301includes electrical paths306there within. For example, package2501may include electrical paths3061. Each electrical path306may be connected to a contact302on the upper surface of system board301. The electrical path306may be connected to the other computing devices such as hard drive, memory module, communication interface, or the like.

Package250may be connected to system board301by interconnects310. Interconnects310are conductive and connect contacts112on the lower surface104of carrier100to system board301contact302and may be a wire bond, solder bond, stud, conductive ball, conductive button, land grid array (LGA) of complaint pins, and the like. Interconnects310may be larger and thus more robust than interconnects210. When package250is connected to system board301, a second reflow process may be performed to join interconnects310to electrical contacts112on surface104of carrier100to contacts302of system board301. Alternately, a mechanical pressurized interconnect via an intervening socket may be established.

FIG. 5depicts a cross section view of electronic system300at a particular fabrication stage, according to one or more embodiments of the present invention. At the present fabrication stage, a connector1421is seated to connector1501and connector1422is seated to connector1502. When connector142is seated to connector140the top surface of connector142may be coplanar with the top surface of cover252. This way, a planar bottom surface of a heatsink340, exemplarily shown inFIG. 7, may contact both cover252and connector140to promote the transfer of heat away from package250.

When the connector1421is seated upon the connector1501and when the connector1422is seated upon the connector1502, electrical paths within the PP connector140exist between paths101of the first carrier100and paths101of the second carrier100.

In one type of I/O, data may be sent from an electrical path2021within IC device2001to an electrical path3061of system board302by way of an electrical path1011through carrier1001.

In another type of I/O, data may be sent from an electrical path2021within IC device2001to an electrical path2022within IC device2002by way of an electrical path1011through carrier1001by way of an electrical path through PP connector and by way of an electrical path1012through carrier1002. Such data may then be subsequently routed from an electrical path2022within IC device2002to an electrical path3062of system board302by way of an electrical path1012through carrier1002.

In another type of I/O, data may be sent from an electrical path2021within IC device2001to an electrical path3062of system board302by way of an electrical path1011through carrier1001by way of an electrical path through PP connector140and by way of an electrical path1012through carrier1002.

As such, with the addition of PP connector140, IC device2001has a relatively increased number of I/O routes to a second IC device2002and/or to system board301. As such, the number of I/O routes may be maintained or may increase even though the normal size of IC device200may be smaller than traditional IC devices.

In some embodiments, it may be desired that a package250not be connected with a neighboring package250by a PP connector140. In these implementations, connector150need not be connected to carrier100nearest to the neighboring package250. Alternatively, a filler310may be connected to connector150. Filler310does not have any electrical paths therein and may be a similar or same form factor as compared to connector142. Filler310may provide mechanical support between heatsink340and the carrier100to which it is connected.

FIG. 6depicts a normal view of electronic system300at a particular fabrication stage, according to one or more embodiments of the present invention. The depicted fabrication stage may be the same fabrication stage as that depicted inFIG. 5. Numerous packages250may be connected to system board301. For example, a central package250gis connected to system board301and one or more outer packages250a-250gmay be connected to system board301about the perimeter of central package250g. As depicted a side surface of the first package250may be parallel with a corresponding side surface of the neighboring second package250. Neighboring packages250may be connected by a PP connector140. For example, package250amay be connected to package250bby PP connected140ab, package250dmay be connected to package250eby PP connected140de, package250fmay be connected to package250gby PP connected140fg, and the like. In the depicted embodiment, the central package250gmay conduct the various types of I/O to system board301through its own carrier100, through its neighboring and interconnected carrier100(e.g. carrier100d, or the like), or through its neighboring and interconnected carrier100by way of that carrier's IC device200.

In some embodiments, it may be desired that a package250dnot be connected with a neighboring package250eby a PP connector140. In these implementations, a filler310dmay be connected to connector150dand a filler310emay be connected to connected150e.

FIG. 7depicts a cross section view of electronic system300at a particular fabrication stage, according to one or more embodiments of the present invention. At the depicted fabrication stage, heat sink340is connected to the top surface of the numerous covers252and to the top surface of connectors142.

To assist in the removal of heat from IC device200, heat sink340may be joined to each package250of device300. The heat sink340may be connected one or more of the various covers250via thermal interface material330that may be applied to the top surface of covers252and or to the underside of heat sink340. Heat sink304may be a passive heat exchanger that cools IC devices200by dissipating heat into the surrounding air. Heat sink304may be an active heat exchanger that cools IC devices200by dissipating heat into an actively cooled fluid or another actively cooled structure. In an implementation, a single heat sink340is connected to one package250. In another implementation, a single heat sink340is connected to multiple packages250. In another implantation, a single heat sink340is connected to all of the packages250of system300.

During operation of electronic device300, a thermal path may exist from IC device200to heat sink340through TIM205, to cover252, through TIM330, and into heat sink340. Heat sink340may be connected to system board301via one or more connection devices, frames, or the like.

FIG. 8depicts a detail cross section view of electronic system300, according to one or more embodiments of the present invention. In an implementation, heat sink340may include an underside recess342in locations above the PP connectors140. Within the recess342there may be one or more springs344. Under no compression, springs344may extend beyond the bottom surface of heat sink340. Under compression, when heat sink is connected to packages250, springs344may exert a predetermined force upon the top surface of connectors142of the PP connector140.

FIG. 9Adepicts a normal view of numerous IC devices502, according to one or more embodiments of the present invention. IC device502may be an IC chip, die, processor, microchip, field programmable gate array, or other type of data processing or storage device, that is configured to be connected a carrier400, exemplarily shown inFIG. 10, along with one or more other of the same type of IC devices502. IC devices502may have a polygonal normal shape.

In an implementation, there may be a central IC device502and one or more perimeter IC devices502arranged about the perimeter of the central IC devices502. As depicted a side surface of the central IC device502may be parallel with a corresponding side surface of the neighboring permitted IC device502. Neighboring IC devices502may be connected by a chip to chip (CC) bridge550, as is exemplarily shown inFIG. 11.

FIG. 9Bdepicts a cross section view of CC bridge550, according to one or more embodiments of the present invention. CC bridge550may be a glass, substrate, laminate, organic material (e.g., Silicon, etc.) based structure that includes electrically insulating or dielectric material that surrounds electrical paths551therein. CC bridge550may include a single or multiple electrical path levels. CC bridge550includes an IC device facing surface that may include contacts552. Contacts552are associated with I/O between two different IC devices502and may be connected to electrical paths551. For example, a path551amay connect a contact552aassociated with a first IC device502with a contact552dassociated with a second IC device502, a path551bmay connect a contact552bassociated with the first IC device502with a contact552eassociated with the second IC device502, a path551cmay connect a contact552cassociated with the first IC device502with a contact552eassociated with the second IC device, and the like. Contact552is electrically conductive and may be a pad, pin, receptacle, socket, or the like.

FIG. 10depicts a normal view of an IC device carrier400, according to one or more embodiments of the present invention. Carrier400has a polygonal normal shape and may be an organic carrier. For example, carrier400may have a hexagonal normal shape as depicted. Carrier400provides mechanical support for multiple IC devices502and includes electrical paths there within. For example, carrier400may include electrical paths401, exemplary shown inFIG. 13, there within.

Carrier400includes multiple IC device regions410. IC device region410may be a footprint of one IC device which is supported by carrier100and may extend from a top surface402of carrier400to the bottom surface404of carrier400. The surface area of region410may be relatively larger upon surface404relative to that upon surface402. IC device region410includes contacts412upon surface402and includes contacts412upon surface404.

Contacts412within region410are associated with I/O between that associated IC device and a higher level system or mother board. As such, within region410, a path401may connect a contact412upon surface402with a contact412upon surface404. Contact112is electrically conductive and may be a pad, pin, receptacle, socket, or the like.

FIG. 11depicts a cross section view of an IC package600at a particular fabrication stage, according to one or more embodiments of the present invention. At the present fabrication stage, CC bridge550is connected to neighboring IC devices502.

CC bridge550may be connected to neighboring IC device502by interconnects510. For example, CC bridge5501may be connected to IC device5021and to IC device5022by interconnects5101, CC bridge5502may be connected to IC device5022and IC device5023by interconnects5102. An interconnect510is conductive and is configured to electrically connect a contact506of IC device550with a contact552of CC bridge550. For example, an interconnect5101connects a contact5061of IC device5501or a contact5062of IC device5502with a contact5521of CC bridge5501, an interconnect5102connects a contact5062of IC device5502or a contact5063of IC device5503with a contact5522of CC bridge5502. Interconnect510is generally smaller in size, volume, or the like, relative to connector610, that connects the neighboring IC devices502to the carrier400, exemplarily shown inFIG. 6, and may be a miro-wire, miro-solder, miro-stud, miro-ball, or the like. A reflow process may be performed to join interconnects510to electrical contacts506of the neighboring IC devices502with contacts552of CC bridge550.

When CC bridge550is connected to the neighboring IC devices502, one or more electrical or current paths are formed from paths within the first IC device502to paths within the first IC device502through CC bridge550. For example, an electrical or current path is formed from path5081within IC device5021to path5082within IC device5022through CC bridge5501, an electrical or current path is formed from path5083within IC device5022to path5084within IC device5023through CC bridge5502.

FIG. 12depicts a cross section view of IC package600at a particular fabrication stage, according to one or more embodiments of the present invention. At the depicted fabrication stage, interconnects610are formed upon the IC devices502. For example, an interconnect6101is placed upon each contact5041of IC device5021, an interconnect6102is placed upon each contact5042of IC device5022, an interconnect6103is placed upon each contact5043of IC device5023.

Interconnect610is conductive and is configured to electrically connect a contact504of IC device502with a contact412on the upper surface402of carrier400. Interconnect210may be a wire, solder, stud, conductive ball, conductive button, socket, receptacle, or the like.

FIG. 13depicts a cross section view of IC package600at a particular fabrication stage, according to one or more embodiments of the present invention. At the current fabrication stage, IC device carrier400is connected to the IC devices502.

The IC devices502may be connected to carrier400by interconnects610. The IC devices502may be further connected to carrier400by underfill211. Underfill211may be electrically-insulating, may substantially surround interconnects610, may isolate individual interconnects610, and may provide mechanical support between the IC devices502and carrier400. Underfill211may also prevent damage to individual interconnects610due to thermal expansion mismatches between the IC devices502and carrier400. Underfill211may further substantially surround interconnects510, may isolate individual interconnects510, and may provide mechanical support around and surrounding CC bridge550. When carrier400is connected to the IC devices502, the CC bridge550is generally positioned between the top surface402of carrier400and the bottom surface of the IC devices502.

When the IC devices502are connected to carrier400, a reflow process may be performed to join interconnects610to electrical contacts504of the IC device502and contacts412upon surface402of carrier400.

Cover630may be connected to one or more of the IC devices502by TIM205that may be applied upon the top surface of each IC device502or upon the underside of cover630. Cover630may be connected to carrier400by adhesive or seal band material. Cover630may have a polygonal normal shape and may be the same polygonal shape as carrier400, as depicted inFIG. 15.

When IC device502is connected to carrier400, an electrical or current path is formed from a path508within IC device502to a path401within carrier101. For example, an interconnect610electrically connects an electrical path508awithin IC device5021with an electrical path401ain carrier400, an interconnect610electrically connects an electrical path508bwithin IC device5022with an electrical path401bin carrier400, an interconnect610electrically connects an electrical path508cwithin IC device5023with an electrical path401cin carrier400. These electrical paths may be associated with I/O between the associated IC device502and the higher level system board301through carrier400.

When IC device502is connected to carrier400, an electrical or current path is formed from a path508within the first IC device502to a path508within the second neighboring IC device502through CC bridge550. For example, CC bridge5501electrically connects an electrical path5081within IC device5021with an electrical path5082within IC device5022and CC bridge5502electrically connects an electrical path5083within IC device5021with an electrical path5084within IC device5023. These electrical paths may be associated with I/O between neighboring IC devices502. These electrical paths may further allow for indirect I/O between the first IC device502and the higher level system board301through carrier400by way of the neighboring second IC device502and CC bridge550. For example, an output may be generated within IC device5023and initially associated with path508cthere within to be outputted to the system board301through carrier400. Due to a failure, a fault, congestion, or the like, associated with the initially arbitrated path508c, that output may be routed to path5084through CC bridge5502, to path5083within the neighboring IC device5022. In turn, IC device5022may route that output from path5083to path508bwhere the output may pass through contact610into carrier400and ultimately to system board301.

As such, with the addition of CC bridge550, the first IC device502has a relatively increased number of I/O routes to a second IC device502and/or to system board301. As such, the number of I/O routes may be maintained or may increase even though the normal size of IC device502may be smaller than traditional IC devices.

FIG. 14depicts a normal view of IC package at a particular fabrication stage, according to one or more embodiments of the present invention.FIG. 14depicts the similar fabrication stage depicted inFIG. 11. In the depicted implementation, there may be a central IC device502gand perimeter IC devices502a-502farranged about the perimeter of the central IC device502g. A CC bridge550agmay connect IC device502awith IC device502g, a CC bridge550bgmay connect IC device502bwith IC device502g, CC bridge550cgmay connect IC device502cwith IC device502g, CC bridge550dgmay connect IC device502dwith IC device502g, CC bridge550egmay connect IC device502ewith IC device502g, and CC bridge550fgmay connect IC device502fwith IC device502g. Further, neighboring IC devices502need not be directly connected by a CC bridge550. For example, IC device502cis not directly electrically connected by a CC bridge550to neighboring IC device502d. Through one implementation is shown, other implementations where all or some neighboring IC devices are directly interconnected by respective CC bridges500are contemplated.

FIG. 16depicts a detail cross section view of an electronic system690at a particular fabrication stage, according to one or more embodiments of the present invention. At the depicted fabrication stage, heat sink340is connected to the top surface of the cover630.

To assist in the removal of heat from the IC devices502, heat sink340may be joined to the cover630. The heat sink340may be connected the cover630via TIM330that may be applied to the top surface of cover630and or to the underside of heat sink340. Heat sink304may be a passive heat exchanger that cools the IC devices502by dissipating heat into the surrounding air. Heat sink304may be an active heat exchanger that cools IC devices502by dissipating heat into an actively cooled fluid or another actively cooled structure. The normal shape of heatsink340may be the same underlying normal shape as cover630.

TIM205and/or TIM330may be a thermal grease, thermal gel, or the like, and may be dispensed, formed, applied, etc. upon an indicated surface in a predetermined pattern (e.g. star pattern, or the like) so as to substantially cover the surface area of the upper surface of the IC device, upper surface of the cover, respectively.

During operation of electronic device690, a thermal path may exist from each IC device502to heat sink340through TIM205, to cover630, through TIM330, and into heat sink340. Heat sink340may be connected to system board301via one or more connection devices, frames, or the like.

FIG. 17depicts an electronic system fabrication method700, according to one or more embodiments of the present invention. Method700may be utilized to fabricate electronic system300. Method700begins at block702and continues with connecting a first polygon IC package and a second polygon IC package to a system board such that the second polygon IC package is arranged next to or neighboring the first polygon IC package (block704). For example, first polygon IC package2501is connected to system board3011by interconnects310connecting contacts1121of package2501with contacts3021of system board301and a neighboring second polygon IC package2502is connected to system board301by interconnects3102connecting contacts1122of package2502with contacts3022of system board301.

Method700may continue with connecting the first polygon IC package and the second polygon IC package with a PP connector. For example, the first polygon IC package2501is connected to the neighboring second polygon IC package2502by seating connector1421of PP connector140into connector1501of the first polygon IC package2501and by seating connector1422of PP connector140into connector1502of the second polygon IC package2502.

Method700may continue with forming TIM upon the first polygon IC package and upon the second polygon IC package (block708). For example, TIM205is formed upon the top surface of cover2521of the first IC package2501and TIM205is formed upon the top surface of cover2522of the first IC package2502TIM205may alternatively be formed upon regions of the bottom surface of heat sink340that are aligned with the top surface of cover2521and the top surface of cover2522. The TIM205may be applied in a predetermined pattern such that the entire top surface of cover2521and the top surface of cover2522has TIM205formed thereupon when heat sink340is compressed thereupon.

Method700may continue with connecting the heat sink to the first polygon IC package, to the second polygon IC package, and to the PP connector. For example, heat sink340may be connected to the first IC package2501by the lower surface of heatsink340contacting the TIM250on the top surface of cover2521and may be connected to the second IC package2502by the lower surface of heatsink340contacting the TIM250on the top surface of cover2522. Heat sink340may be connected to PP connector140by the lower surface of heat sink340contacting the top surface of connector1421and the top surface of connector1422. Method700may end at block712.

FIG. 18depicts an electronic system fabrication method800, according to one or more embodiments of the present invention. Method800may be utilized to fabricate electronic system690. Method800begins at block802and may continue with connecting a first polygon IC device and a second polygon IC device to chip to chip (CC) bridge such that the second polygon IC device is arranged next to or neighboring the first polygon IC device (block804). For example, first polygon IC device5021is connected to second polygon IC device5022by CC bridge550. CC bridge550may be connected to IC device5021by interconnects5101connecting contacts5521of CC bridge550with contacts5061of IC device5021. CC bridge550may be connected to IC device5022by interconnects5102connecting contacts5522of CC bridge550with contacts5062of IC device5022.

Method800may continue with connecting the first polygon IC device and the second polygon IC device to a polygon IC device carrier (block806). For example, first polygon IC device5021and second polygon IC device5022are connected to IC device carrier400by interconnects610. First polygon IC device5021may be connected to IC device carrier400by interconnects6101connecting contacts5041of IC device5021with contacts4121of carrier400. Second polygon IC device5022may be connected to IC device carrier400by interconnects6102connecting contacts5042of IC device5022with contacts4122of carrier400. When the first polygon IC device and the second polygon IC device are connected to the polygon IC device carrier, the CC bridge connecting the first polygon IC device and the second polygon IC is generally between the respective lower surfaces of the first polygon IC device and the second polygon IC and the top surface of the polygon carrier.

Method800may continue with forming underfill between the first polygon IC device and the second polygon IC device and the polygon IC device carrier surrounding the CC bridge. For example, the IC devices502may be connected to carrier400by underfill211. Underfill211may be electrically-insulating, may substantially surround interconnects610, may isolate individual interconnects610, and may provide mechanical support between the IC devices502and carrier400. Underfill211may further substantially surround interconnects510, may isolate individual interconnects510, and may provide mechanical support around and surrounding CC bridge550.

Method800may continue with forming a first TIM upon the first polygon IC device and upon the second polygon IC device (block810). For example, TIM205may be applied upon the top surface of each IC device502or upon the underside of cover630. The TIM205may be applied in a predetermined pattern such that the entire top surface of each IC device502is covered by TIM205upon when the cover630is connected thereto.

Method800may continue with connecting a cover to the first polygon IC device, to the second polygon IC device, and to the carrier (block812). For example, cover630may be connected to the first IC device5021by the lower inner surface of cover630contacting the top surface of first IC device5021via the TIM2051and may be connected to the second IC device5022by the lower inner surface of cover630contacting the top surface of second IC device5022via the TIM2052. Cover630may be connected to the carrier400by the lower perimeter surface of cover630contacting carrier400via an adhesive, seal band, or the like.

Method800may continue with applying a second TIM upon the top surface of the cover (block816). For example, TIM330may be applied to the top surface of cover630and or to the underside of heat sink340. Method800may continue with connecting a heat sink to the cover (block818). For example, heat sink340may be connected to the cover630by the lower surface of heatsink340contacting the TIM330on the top surface of cover630. Method800may end at block820.

FIG. 19depicts a multiple IC device system data input method900, according to one or more embodiments of the present invention. Method900may be performed, for example, by electronic system300or electronic system690. Method900begins at block902and may continue with a first polygon IC device generating, receiving, etc., output data associated with an output request. For example, IC package2501or IC device5021may generate the output request and associated output data that is to be sent through system board301to a destination data handling device. The destination data handling device may be connected to system board301or communicatively connected to system board301.

Method900may continue with the first polygon IC device passing the output data to a neighboring second polygon IC device (block906). For example, IC package2501or IC device5021may determine that itself cannot satisfy the output request by directly passing the output data to the system board301. As such, IC package2501may send or pass the output data to the neighboring IC package2502through PP connector140. Similarly, IC device5021may send or pass the output data to the neighboring IC device5022through CC bridge550.

Method900may continue with the second polygon IC device receiving the output data from the first polygon IC device (block908). For example, IC package2502may receive the output data from the neighboring IC package2501from PP connector140. Similarly, IC device5022may receive the output data from the neighboring IC device5021from the CC bridge550.

Method900may continue with the second polygon IC device satisfying the output request. For example, the IC package2502may pass the output data directly from the IC package2502to the system board301through its associated carrier1002where, in turn, the system board301may pass the data to the destination device. Similarly, the IC device5022may pass the output data directly from the IC device5022to the system board301through carrier400where, in turn, the system board301may pass the data to the destination device. Method900may end at block912.

FIG. 20depicts a multiple IC device system data output method920, according to one or more embodiments of the present invention. Method920may be performed, for example, by electronic system300or electronic system690. Method920begins at block922and may continue with a first polygon IC device requesting input data associated with an input request (block924). For example, IC package2501or IC device5021may receive or generate the input request and request the input data from an external data handling device that will be received though system board301. This external data handling device may be connected or communicatively connected to the system board301.

Method920may continue with a neighboring second polygon IC device receiving the input data (block926). For example, IC package2501or IC device5021may determine that itself cannot directly receive the input data from the system board301. As such, IC package2502or IC device5022may directly receive the input data from system board301.

Method920may continue with the second polygon IC device passing the input data to the neighboring first polygon IC device (block928). For example, IC package2502may send or pass the input data to the neighboring IC package2501through PP connector140. Similarly, IC device5022may send or pass the input data to the neighboring IC device5021through CC bridge550.

Method920may continue with the first polygon IC device satisfying the input request (block930). For example, if an another data handling device made the input request, the IC package2501or the IC device5021may send the input data to the other data handling device to satisfy the input request. Similarly, if the first polygon IC device itself made the input request, the IC package2501or the IC device5021may satisfy its own input request upon receipt of the input data from the IC package2502or the IC device5022, respectively. Method920may end at block932.

The accompanying figures and this description depicted and described embodiments of the present invention, and features and components thereof. Those skilled in the art will appreciate that any particular program nomenclature used in this description was merely for convenience, and thus the invention should not be limited to use solely in any specific application identified and/or implied by such nomenclature.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. For example, the order of the fabrication stages listed in depicted blocks may occur out of turn relative to the order indicated in the Figures, may be repeated, and/or may be omitted partially or entirely. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

References herein to terms such as “vertical”, “horizontal”, and the like, are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the carrier100,400, etc., regardless of the actual spatial orientation of the carrier100,400. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, “top”, “under”, “beneath”, and the like, are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing the present invention without departing from the spirit and scope of the present invention.