Buffer device, an electronic system, and a method for operating a buffer device

Embodiments of a buffer device, an electronic system, and a method for operating a buffer device are disclosed. In an embodiment, a buffer device includes buffer bus connections, a peripheral bus interface connectable to a peripheral bus, a buffer memory module, and a buffer memory controller connected between the buffer bus connections, the peripheral bus interface, and the buffer memory module. Each of the buffer bus connections is connectable to a respective peripheral device. The buffer memory module comprises memory segments corresponding to the peripheral devices. The buffer memory controller is configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module.

BACKGROUND

Peripheral devices, such as communications devices or analog-to-digital converters (ADCs), and one or more corresponding controlling devices (e.g., microcontrollers) can communicate between each other through commonly accessible memory locations. Direct-memory access (DMA) is a memory access technology in which a peripheral device can directly transfer data to/from a memory location. Typically, this memory location is part of the main system memory, which also contains program code and data. However, allowing DMA to the main system memory may have disadvantages. For example, under DMA, wrong addressing (e.g., memory area overflow or buffer overflow) can pose a potential security threat as it is possible to inject executable code into the main system memory. In addition, under DMA, the main system memory typically stays active in low-power modes, causing power consumption to increase.

SUMMARY

Embodiments of a buffer device, an electronic system, and a method for operating a buffer device are disclosed. In an embodiment, a buffer device includes buffer bus connections, a peripheral bus interface connectable to a peripheral bus, a buffer memory module, and a buffer memory controller connected between the buffer bus connections, the peripheral bus interface, and the buffer memory module. Each of the buffer bus connections is connectable to a respective peripheral device. The buffer memory module comprises memory segments corresponding to the peripheral devices. The buffer memory controller is configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module.

In an embodiment, each of the memory segments stores input data received from a different peripheral device.

In an embodiment, the buffer memory controller is further configured to block access to the peripheral bus by the peripheral devices.

In an embodiment, the buffer device and a corresponding processor connected to the peripheral bus interface are located in different power domains.

In an embodiment, the buffer memory controller is further configured to set the size of each of the memory segments in response to an instruction received through the peripheral bus interface.

In an embodiment, the buffer memory controller is further configured to perform a full wipe of a memory segment of the buffer memory module and subsequently change the size of the memory segment.

In an embodiment, the buffer memory controller is further configured to define access information of the memory segments of the buffer memory module in response to the instruction received through the peripheral bus.

In an embodiment, the buffer memory controller is further configured to define read or write access information of the memory segments of the buffer memory module in response to the instruction received through the peripheral bus.

In an embodiment, an integrated circuit (IC) device includes the buffer device.

In an embodiment, an electronic system includes peripheral devices, a peripheral bus, a buffer device, and a processor connectable to the peripheral bus. The buffer device includes buffer bus connections, a peripheral bus interface connectable to the peripheral bus, a buffer memory module, and a buffer memory controller connected between the buffer bus connections, the peripheral bus interface. Each of the buffer bus connections is connectable to a respective peripheral device of the peripheral devices. The buffer memory module comprises memory segments corresponding to the peripheral devices. The buffer memory controller is connected between the buffer bus connections, the peripheral bus interface, and configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module.

In an embodiment, each of the memory segments stores input data received from a different peripheral device.

In an embodiment, the buffer memory controller is further configured to block access to the peripheral bus by the peripheral devices.

In an embodiment, the buffer device and the processor are located in different power domains.

In an embodiment, the buffer memory controller is further configured to set the size of each of the memory segments in response to an instruction received from the processor.

In an embodiment, the buffer memory controller is further configured to perform a full wipe of a memory segment of the buffer memory module and subsequently change the size of the memory segment.

In an embodiment, the buffer memory controller is further configured to define access information of the memory segments of the buffer memory module in response to the instruction received from the processor.

In an embodiment, the buffer memory controller is further configured to define read or write access information of the memory segments of the buffer memory module in response to the instruction received from the processor.

In an embodiment, the electronic system further includes a memory device connectable to the peripheral bus.

In an embodiment, an IC device includes the electronic system.

In an embodiment, a method for operating a buffer device involves receiving input data from a peripheral device through a corresponding buffer bus connection, storing the input data at a corresponding memory segment within a buffer memory module, and allowing an authorized access of the input data through a peripheral bus interface.

Other aspects and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1depicts a buffer device100in accordance with an embodiment of the invention. In the embodiment depicted inFIG. 1, the buffer device includes multiple buffer bus connections102-1, . . . ,102-N (where N is a positive integer that is larger than 1), a peripheral bus interface104, a buffer memory module106, and a buffer memory controller108. The buffer device may be an integrated circuit (IC) device, such as an IC module. The buffer device may be implemented in a microcontroller system. In some embodiments, the buffer device is implemented in an ADC microcontroller system. In the embodiment depicted inFIG. 1, the buffer device allows for buffering of data from, for example, communications peripheral devices or AD/DA converter peripheral devices. The buffer device is compatible with security features and ultra-low-power microcontrollers. Although the illustrated buffer device is shown with certain components and described with certain functionality herein, other embodiments of the buffer device may include fewer or more components to implement the same, less, or more functionality.

In the embodiment depicted inFIG. 1, each of the buffer bus connections102-1, . . . ,102-N of the buffer device100is connectable to a respective peripheral device. Each buffer bus connection is used to communicate with a particular peripheral device. The buffer bus connections are interface devices (e.g., input/output devices) that can be implemented in hardware such as logic circuits and/or memory. The buffer bus connections may include physical connections that connect to respective buffer bus connections.

The peripheral bus interface104of the buffer device100is connectable to a peripheral bus. The peripheral bus interface is an interface device (e.g., an input/output device) that can be implemented in hardware such as logic circuits and/or memory. The peripheral bus interface may include one or more physical connections that connect to the peripheral bus. The peripheral bus can be used for communications between peripheral devices, the buffer memory module106, and at least one control device (not shown), such as a microcontroller. In some embodiments, the peripheral devices act as slave devices and the control device acts as a master device.

The buffer memory module106of the buffer device100is used to buffer or temporarily store data for peripheral devices. The buffer memory module can be implemented using various memory technologies. For example, the buffer memory module may be a register file or a static random-access memory (SRAM). In some embodiments, the buffer memory module may be divided into memory segments110-1, . . . ,110-N corresponding to different peripheral devices. In some embodiments, each of the memory segments stores input data received from a different peripheral device.

In the embodiment depicted inFIG. 1, the buffer memory module106is separate from control devices connected to the peripheral bus interface104. Consequently, the buffer memory module and the corresponding control device can be set to different clocks or located in different power domains. Because the buffer memory module and the corresponding control device can have different clocks and/or different power supplies, the clock source and/or the power supply for the buffer memory module can be kept on while the clock source and/or the power supply for the corresponding control device is turned off. Consequently, power consumption by the corresponding control device can be reduced.

The buffer memory controller108of the buffer device100is connected between the buffer bus connections102-1, . . . ,102-N, the peripheral bus interface104, and the buffer memory module106. The buffer memory controller is configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module. The buffer memory controller can be implemented in hardware such as logic circuits and/or memory. In some embodiments, the buffer memory controller is implemented as a microcontroller. In some embodiments, the buffer memory controller is further configured to block access to the peripheral bus by the peripheral devices. In some embodiments, the buffer memory controller sets the size of the memory segments110-1, . . . ,110-N of the buffer memory module. In an embodiment, the buffer memory controller is further configured to set the size of each of the memory segments in response to an instruction received through the peripheral bus. In an embodiment, the buffer memory controller is further configured to perform a full wipe of a memory segment of the buffer memory module and subsequently change the size of the memory segment. In some embodiments, the buffer memory controller may define the access restrictions of the memory segments of the buffer memory module, including security access (e.g., read/write access) level of the memory segments of the buffer memory module, in response to an instruction received through the peripheral bus.

FIG. 2depicts an embodiment of the buffer memory module106of the buffer device100depicted inFIG. 1. In the embodiment depicted inFIG. 2, a buffer memory module206includes memory segments210-1, . . . ,210-N (where N is a positive integer that is larger than 1). In an embodiment, each memory segment is a continuous portion of memory. For example, the memory segment201-1occupies memory space between address 0x0000 and address 0x0010, the memory segment201-2occupies memory space between address 0x010 to 0x0020, the memory segment201-3occupies memory space between address 0x020 to 0x0030, and the memory segment201-N may occupy memory space between address 0x0N-10 to 0x00N0. However, the size of the memory segments of the buffer memory module is not limited to the examples described above. In some embodiments, the size of the memory segments of the buffer memory module is identical to each other (i.e., all of the memory segments of the buffer memory module are of the same size). In some embodiments, the sizes of the memory segments of the buffer memory module are different from each other (i.e., the size of one or more of the memory segments of the buffer memory module is different from the size of the rest of the memory segments of the buffer memory module.) The memory segments of the buffer memory module correspond to N different peripheral devices. The buffer memory module206depicted inFIG. 2is one possible embodiment of the buffer memory module106depicted inFIG. 1. However, the buffer memory module depicted inFIG. 1is not limited to the embodiment shown inFIG. 2.

In the embodiment depicted inFIG. 2, each memory segment210of the buffer memory module206stores input data received from a respective peripheral device. The buffer memory controller108(shown inFIG. 1) has access to all of the memory segments of the buffer memory module (e.g., continuous address space, starting from a base address). Each peripheral device has access to only one memory segment and addresses the memory segment relative to a respective segment base address (e.g., from 0x0 to 0xM, where M is the size of the particular memory element). Each memory segment of the buffer memory module may be configured to have cyclic (modulo) addressing. Alternatively, each memory segment of the buffer memory module may be configured to have non-cyclic addressing in which an out-of-range access results in an error condition (e.g., buffer overflow). Each memory segment of the buffer memory module may be set to be readable, writable, or readable/writable. Each pending data transaction can be marked as a secure transaction or an unsecure transaction. A secure data transaction can read/write to a secure memory segment or an unsecure memory segment while an unsecure data transaction can only read/write to an unsecure memory segment.

The buffer memory controller108can be used to set and adjust the properties of the memory segments210-1, . . . ,210-N of the buffer memory module206. In some embodiments, the buffer memory controller sets and/or changes the size of each memory segment of the buffer memory module. For example, the buffer memory controller sets each memory segment to sixteen bits. In some embodiments, the buffer memory controller performs a full wipe of a memory segment and subsequently changes the size of the memory segment. In some embodiments, the buffer memory controller sets and/or changes the access settings of the memory segments of the buffer memory module. For example, the buffer memory controller defines a set of interrupts for setting access information for the memory segments of the buffer memory module. Examples of the defined interrupts include, without being limited to, an interrupt to allow read access to a particular memory segment by a particular peripheral device, an interrupt to allow write access to a particular memory segment by peripheral, an interrupt to allow read access to one address section within a particular memory segment by a particular peripheral device, and an interrupt to allow write access to one address section within a particular memory segment by a particular peripheral device.

FIG. 3depicts an embodiment of an electronic system320that includes a buffer device300that is similar to the buffer device200described with reference toFIGS. 1 and 2. In the embodiment depicted inFIG. 3, the electronic system includes first and second peripheral devices312-1,321-2, the buffer device300, a bridge device314, a processor316, and a main memory device318. The electronic system may be an integrated circuit (IC) device, such as an IC module. The electronic system can be implemented in various applications. For example, the electronic system may be used in low power sensor applications as a sensor hub or an Internet of Things (IoT) node. In some embodiments, the electronic system includes an analog-to-digital converter (ADC) that captures sixty-four 16-bit samples of data, which can then be analyzed by the processor. In these embodiments, the processor instructs the buffer device to allocate a memory segment310of the buffer memory module306to the ADC and generates an interrupt when the last address within the allocated memory segment is written. The processor and the main memory device can enter a lower-power state while waiting for the interrupt so that the electronic system consumes less power while ADC data is being acquired.

In the embodiment depicted inFIG. 3, the buffer device300includes two buffer bus connections302-1,302-2, a peripheral bus interface304, a buffer memory module306having two memory segments310-1,310-2, and a buffer memory controller308. The buffer bus connections302-1,302-2, the peripheral bus interface304, the buffer memory module306, and the buffer memory controller308depicted inFIG. 3are embodiments of the buffer bus connections102-1, . . . ,102-N, the peripheral bus interface104, the buffer memory module106, and the buffer memory controller108depicted inFIG. 1. The buffer device300depicted inFIG. 3may be similar to or the same as the buffer device100depicted inFIG. 1. However, the buffer device depicted inFIG. 1is not limited to the embodiment shown inFIG. 3.

In the embodiment depicted inFIG. 3, each peripheral device312-1or321-2includes a peripheral bus interface324-1or324-2connectable to a peripheral bus330and a buffer bus interface326-1or326-2connectable to a respective buffer bus connection302-1or302-3of the buffer device300through a respective buffer bus322-1or322-2. In addition, the first peripheral device312-1includes an Inter-Integrated Circuit (I2C) module332and the second peripheral device312-2includes an ADC module334. Each peripheral device has only access to one memory segment310-1or310-2to prevent the peripheral device from modifying a memory segment allocated to another peripheral device. Specifically, the first peripheral device312-1has access to a first memory segment310-1but has no access to a second memory segment310-2. The second peripheral device312-2has access to the second memory segment310-2but has no access to the first memory segment310-2. The size and/or the access restriction (readable and/or writable by a corresponding peripheral device) of each memory segment can be dynamically adjusted by the processor316.

The bridge device314is configured to control data traffic on the peripheral bus330. In some embodiments, the bridge device is configured to transform data traffic received from the peripheral device312-1or321-2or from the buffer device300at a first data rate into data traffic going to the processor316or to the main memory device318at a second data rate. The second data rate may be higher than or lower than the first data rate. In some embodiments, the bridge device is configured to transform data traffic received from the processor or the main memory device at a first data rate into data traffic going to the peripheral device312-1or321-2or to the buffer device300at a second data rate. The second data rate may be higher than or lower than the first data rate.

The processor316is configured to process data received from the peripheral devices312-1,321-2and/or to control the buffer device300and the peripheral devices312-1,321-2. In some embodiments, the processor may be implemented as a microcontroller. In some embodiments, the peripheral devices act as slave devices and the processor acts as a master device. The processor may set the size of the memory segments310-1,310-2of the buffer memory module306of the buffer device. The processor may define the access restrictions of the memory segments of the buffer memory module, including security access (e.g., read/write access) level of the memory segments of the buffer memory module. The main memory device318is used to store data for processing.

In the electronic system320depicted inFIG. 3, the peripheral devices312-1,321-2use the buffer device300for data storage and do not have direct access to the main memory device318. Consequently, compared to a DMA system in which peripheral devices have direct access to main memories, the electronic system depicted inFIG. 3provides better protection of the main memory device318against potential unauthorized access. In addition, in the electronic system depicted inFIG. 3, the peripheral devices access the buffer device through respective buffer bus connections302-1,302-2. Consequently, compared to a DMA system in which peripheral devices access main memories through the peripheral bus, the electronic system depicted inFIG. 3provides compact/local memory access to peripheral devices. Further, in the electronic system depicted inFIG. 3, the buffer device can be on a different power domain from the processor316and the main memory device (i.e., the buffer device has a power supply that is different from the power supply of the processor and the main memory device). Compared to a DMA system in which a processor and the corresponding main memories are located in the same power domain, the electronic system depicted inFIG. 3allows the processor and the main memory device to enter the sleep mode while keeping the buffer device powered on. Consequently, the electronic system depicted inFIG. 3can consume less power than traditional DMA systems.

FIG. 4depicts a DMA system420that includes first and second peripheral devices412-1,412-2, a bridge device414, a DMA controller440, a processor416, and a main memory device418. In the embodiment depicted inFIG. 4, each peripheral device412-1or421-2includes a bus interface424-1or424-2connectable to a peripheral bus430and a DMA interface426-1or426-2. In addition, the first peripheral device412-1includes an Inter-Integrated Circuit (I2C) module432and the second peripheral device312-2includes an ADC module434. In the DMA system depicted inFIG. 4, each peripheral device has direct access to the main memory device. Specifically, each peripheral device can transfer data from a corresponding DMA interface to the main memory device through the DMA controller in the direction as shown by the arrow450. The DMA system depicted inFIG. 4does not differentiate between a secure access by the processor and an unsecure access by the peripheral devices.

Compared to the DMA system depicted inFIG. 4, the electronic system320depicted inFIG. 3does not allow the peripheral devices312-1,312-2to have direct access to the main memory device318. The electronic system supports secure code in the processor316and non-secure code such as drivers or applications in the peripheral devices. The electronic system300can restrict access to the main memory device by potentially non-secure peripheral devices and allow secure code in the processor to control data transfers to the main memory device.FIG. 5illustrates a data operation of the electronic system320depicted inFIG. 3. The peripheral device312-2controls the data flow from the peripheral device to the buffer device300in the direction as shown by the arrow550. The memory transfer from the buffer device to the main memory device is controlled by secure code in the processor in the direction as shown by the arrow560. Consequently, compared to the DMA system depicted inFIG. 4, the electronic system depicted inFIG. 3is more robust against potential unauthorized access from non-secure peripheral devices.

FIG. 6is a process flow diagram of a method for operating a buffer device in accordance with an embodiment of the invention. At block602, input data is received from a peripheral device through a corresponding buffer bus connection. At block604, the input data is stored at a corresponding memory segment within a buffer memory module. At block606, an authorized access of the input data through a peripheral bus interface is allowed. The buffer device may be the same or similar to the buffer device106depicted inFIG. 1and/or the buffer device206depicted inFIG. 2.