Phase change memory operation method and circuit

A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.

BACKGROUND

Phase-change memory (PCM) devices have resistance values that are altered by transitioning some or all of a material volume between a low-resistance crystalline phase and a high-resistance amorphous phase. In memory cell applications, targeted resistance values are usually divided into two groups corresponding to low and high logic levels.

In analog synapse applications, targeted resistance values typically include more than the two groups sufficient for memory cell applications. Analog synapse applications often include synapse arrays in which PCM devices act as weighting factors in layers of neural networks, e.g., multilayer perceptron (MLP) neural networks.

DETAILED DESCRIPTION

In various embodiments, crystalline/amorphous phase-based conductance values of a PCM device are controlled in a PCM circuit by applying a sequence of pulses including trailing edge durations longer than leading edge durations. Particularly in resetting operations in which crystalline and amorphous phases are controlled so that conductance is decreased toward a lowest conductance value, applying the sequence of pulses enables improved control of conductance values compared to approaches in which a sequence of pulses does not include a trailing edge duration longer than a leading edge duration.

FIG. 1is a diagram of a PCM circuit100, in accordance with some embodiments.FIG. 1depicts PCM circuit100including a pulse generation circuit110, a PCM device120, and a pulse Pn. Pulse generation circuit110includes a terminal111coupled to a terminal121of PCM device120, and a terminal113coupled to a terminal123of PCM device120. Pulse generation circuit110is configured to output a sequence of pulses Pn (1≤n≤N) on terminals111and113, the pulse sequence having the number of pulses N.

Two or more circuit elements are considered to be coupled based on a direct electrical connection or an electrical connection that includes one or more additional circuit elements and is thereby capable of being controlled, e.g., made resistive or open by a transistor or other switching device.

Pulse generation circuit110is one or more electronic and/or electromechanical circuits configured to generate and output the sequence of pulses Pn having the voltage and timing characteristics discussed below. In various embodiments, pulse generation circuit110includes one or more of a processing device, e.g., a processor702discussed below with respect toFIG. 7, a signal processing circuit, a logic device, a PCM device in addition to PCM device120, or another circuit suitable for generating output pulses Pn.

In some embodiments, PCM circuit100is some or all of a neural network, and pulse generation circuit110includes an analog synapse array, e.g. a synapse array310discussed below with respect toFIG. 3.

PCM device120is an electronic or electromechanical device including a material layer125positioned between electrodes127and129configured to receive an applied voltage Va. In some embodiments, in addition to material layer125and electrodes127and129, PCM device120includes a heating structure (not shown) positioned between or adjacent to electrodes127and129.

Material layer125includes one or more layers of one or more resistive materials, also referred to as PCM materials in some embodiments, capable of transitioning between a low-resistance crystalline phase and a high-resistance amorphous phase. In various embodiments, material layer125includes one or more of a chalcogenide material, e.g., germanium-antimony-tellurium (GeSbTe or GST), GeTe, GeSb, or Sb2Te3, or other suitable phase-change material, and, in some embodiments, one or more dopants, e.g., nitrogen (N), oxygen (O), carbon (C), indium (In), silicon (Si), tin (Sn), gallium (Ga), arsenic (As), selenium (Se), or other suitable dopant materials.

In various embodiments, electrodes127and129are planar, arranged in parallel, and have a same size and a same shape, e.g., a pillar arrangement of a PCM device400A discussed below with respect toFIG. 4A. In various embodiments, electrodes127and129are planar, arranged in parallel, and have differing sizes and/or shapes, e.g., a mushroom arrangement of a PCM device400B discussed below with respect toFIG. 4B. In various embodiments, electrodes127and129are otherwise configured, e.g., having concave or other nonplanar geometries, arranged in a non-parallel relationship, and/or having non-continuous shapes, such that material layer125is positioned between electrodes127and129.

In various embodiments, electrodes127and129include one or more of tungsten (W), copper (Cu), aluminum (Al), aluminum-copper, or other suitable conductive materials.

In the embodiment depicted inFIG. 1, electrodes127and129are electrically connected to respective terminals121and122such that applied voltage Va corresponds to a difference between a voltage V received at electrode127and a reference voltage Vr received at electrode129.

In various embodiments, PCM device120includes one or more circuit elements (not shown) coupled between electrode127and terminal121and/or between electrode129and terminal123, material layer125thereby being coupled in series with the one or more circuit elements between terminals121and122. In such embodiments, applied voltage Va corresponds to the difference between voltage V and reference voltage Vr reduced by one or more voltage drops across the one or more circuit elements. In various embodiments, the one or more circuit elements include one or more of a selection device, e.g., a transistor or other switching device or a diode, or a resistive device, e.g., a metal resistor.

In operation, PCM device120is thereby configured to generate a current I through material layer125responsive to applied voltage Va such that a resistance value of material layer125is measurable based on values of applied voltage Va and current I. In some embodiments, electrodes127and129are configured to receive applied voltage Va responsive to one or more signals, e.g., a selection signal, received by the one or more circuit elements in series with material layer125or by one or more circuit elements otherwise configured to selectively provide applied voltage Va across electrodes127and129.

In operation, responsive to sufficiently large values of applied voltage Va, current I flowing through material layer125and the heating structure, if present, induces self-heating, thereby causing an elevation in temperature. PCM device120is thereby configured to control a temperature range of material layer125responsive to a range of values of applied voltage Va.

The one or more materials of material layer125are configured to transition, at least in part, between a low-resistance crystalline phase and a high-resistance amorphous phase based on one or more temperature values within the temperature range controllable by applied voltage Va. In operation, a transition between the two phases is based on an initial phase type and a duration of one more temperatures within a range corresponding to forming the other phase type, i.e., melting the crystalline phase to form the amorphous phase or crystallizing the crystalline phase from the amorphous phase. Accordingly, at a specific time and at a given location within an overall volume of material layer125, the corresponding local volume of material is in one of the two phases based on a present temperature, a recent temperature history, and the initial phase type based on a phase history prior to the recent temperature history. In some embodiments, a recent temperature history corresponds to a length of a pulse waveform, e.g., pulse Pn, of applied voltage Va.

PCM device120is thereby configured such that portions of the overall volume are controllable by applied voltage Va to be in either one of the two phases, material layer125thereby being capable of having a range of phase configurations. The geometry and extent of the range of phase configurations are a function of the composition and geometry of material layer125, and of the arrangement, e.g., presence of a heating structure, and geometry of the specific embodiment of PCM device120.

A given phase configuration corresponds to a ratio of one or more volumes of material layer125in the crystalline phase to one or more volumes of material layer125in the amorphous phase. A lowest value of the ratio corresponds to a smallest volume of the crystalline phase and thereby a lowest conductance value of material layer125, and a highest value of the ratio corresponds to a largest volume of the crystalline phase and thereby a highest conductance value of material layer125.

In some embodiments, lowest ratio and conductance values correspond to a fully-amorphous material layer125and highest ratio and conductance values correspond to a fully-crystalline material layer125. In various embodiments, lowest ratio and conductance values correspond to at least a portion of material layer125being in the crystalline phase, and/or highest ratio and conductance values correspond to at least a portion of material layer125being in the amorphous phase.

In some embodiments, PCM device120corresponds to a specific analog synapse in an analog synapse array, e.g. a synapse320in synapse array310discussed below with respect toFIG. 3, and the ratio and conductance values correspond to a weight of the specific analog synapse.

A temperature profile within material layer125is a function of the arrangement and geometry of the specific embodiment of PCM device120, the value of applied voltage Va, the present phase configuration, and temperature profile and phase configuration histories at the time applied voltage Va is applied. Thus, at a given time, the temperature profile within material layer125is a function of the presently applied voltage Va, the recent temperature history as determined by the recent history of applied voltage Va, and the phase configuration prior to the recent histories of temperature and applied voltage Va.

In PCM circuit100, in operation, the presently applied and recent history of applied voltage Va correspond to a given pulse Pn of the sequence of pulses Pn, and the phase configuration of material layer125prior to the recent temperature and applied voltage Va histories is determined, at least in part, by the sequence of pulses Pn prior to the given pulse Pn. Accordingly, local temperature-based phase transitions leading to phase configuration changes in material layer125are a function of voltage and timing characteristics of the given pulse Pn and of the portion of the sequence of pulses Pn prior to the given pulse Pn.

FIG. 1depicts a representative one of the sequence of pulses Pn. The representation ofFIG. 1is simplified for the purpose of illustration, and does not include irregularities associated with non-ideal circuit elements, e.g., distortions due to rectification, bandwidth limitations, parasitic capacitance, resistance, or inductance, or the like.

Each pulse Pn is a signal having voltage V that varies over a time t between reference voltage Vr and an amplitude An relative to reference voltage Vr. In various embodiments, reference voltage Vr has a fixed value, e.g., a ground reference or other direct current (DC) level, or a variable value, e.g., a DC voltage capable of having one of multiple values as determined by one or more operating conditions.

A leading edge of pulse Pn has a leading edge duration Ln corresponding to a time over which voltage V transitions from reference voltage Vr to amplitude An; a pulse width PWn of pulse Pn corresponds to a time over which voltage V remains at amplitude An; and a trailing edge of pulse Pn has a trailing edge duration Tn corresponding to a time over which voltage V transitions from amplitude An to reference voltage Vr. Trailing edge duration Tn is longer than leading edge duration Ln.

In the embodiment depicted inFIG. 1, the voltage and timing characteristics of pulse Pn discussed above are defined at terminal pair111/113of pulse generation circuit110, and at terminal pair121/123of PCM device120. In various embodiments, one or more of the voltage and timing characteristics of pulse Pn are defined at one or more locations other than terminal pairs111/113and/or121/123, e.g., at electrodes127and129or one or more internal nodes (not shown) of pulse generation circuit110and/or PCM device120.

Amplitude An has one or more values corresponding to controlling the phase configuration of material layer125. In various embodiments, the one or more values correspond to values of applied voltage Va or to relatively larger values from which the values of applied voltage Va are derived, as discussed above with respect to reducing voltage V relative to reference voltage Vr to realize applied voltage Va.

In various embodiments, sequence of pulses Pn includes each pulse Pn having a same value of amplitude An or at least one value of amplitude An different from one or more other values of amplitude An. In some embodiments, amplitude An has one or more values ranging from 0.5 volts (V) to 10 V. In some embodiments, amplitude An has one or more values ranging from 1 V to 6 V.

Leading edge duration Ln has one or more values corresponding to speeds at which voltage V having amplitude An is provided to PCM device120in PCM circuit100. In some embodiments, PCM circuit100is configured in accordance with a minimum speed specification, and leading edge duration Ln has one or more values at or below a maximum duration corresponding to the minimum speed.

In various embodiments, sequence of pulses Pn includes each pulse Pn having a same value of leading edge duration Ln or at least one value of leading edge duration Ln different from one or more other values of leading edge duration Ln. In some embodiments, leading edge duration Ln is based on a constant slope of the leading edge of pulse Pn such that the value of leading edge duration Ln is a function of the value of amplitude An. In some embodiments, leading edge duration Ln has one or more values ranging from 1 nanosecond (ns) to 100 ns. In some embodiments, leading edge duration Ln has one or more values ranging from 5 ns to 20 ns.

Pulse width PWn has one or more values corresponding to controlling the phase configuration of material layer125based on amplitude An. In various embodiments, sequence of pulses Pn includes each pulse Pn having a same value of pulse width PWn or at least one value of pulse width PWn different from one or more other values of pulse width PWn. In some embodiments, pulse width PWn has one or more values ranging from 10 ns to 1000 ns. In some embodiments, pulse width PWn has one or more values ranging from 50 ns to 200 ns. In some embodiments, pulse width PWn has one or more values ranging from 80 ns to 120 ns.

Trailing edge duration Tn has one or more values corresponding to controlling the phase configuration of material layer125based on amplitude An. In some embodiments, the one or more values of trailing edge duration Tn are based on a crystallization temperature of a material of material layer125. In various embodiments, trailing edge duration Tn has the one or more values that increase with increasing crystallization temperature of the material of material layer125.

In various embodiments, sequence of pulses Pn includes each pulse Pn having a same value of trailing edge duration Tn or at least one value of trailing edge duration Tn different from one or more other values of trailing edge duration Tn. In some embodiments, trailing edge duration Tn has one or more values ranging from 10 ns to 1000 ns. In some embodiments, trailing edge duration Tn has one or more values ranging from 50 ns to 200 ns. In some embodiments, trailing edge duration Tn has one or more values ranging from 75 ns to 125 ns.

In some embodiments, sequence of pulses Pn includes each pulse Pn having same values of each of amplitude An, leading edge duration Ln, pulse width PWn, and trailing edge duration Tn, or at least one value of one or more of amplitude An, leading edge duration Ln, pulse width PWn, or trailing edge duration Tn different from one or more other values of the one or more of amplitude An, leading edge duration Ln, pulse width PWn, or trailing edge duration Tn. In various embodiments, sequence of pulses Pn includes one of pulse sequences200A-200D discussed below with respect toFIGS. 2A-2D.

By including trailing edge duration Tn longer than leading edge duration Ln, sequence of pulses Pn is capable of controlling a phase configuration of material layer125based at least in part on trailing edge duration Tn relative to leading edge duration Ln. Particularly in resetting operations in which the ratio of the phase configuration of material layer125is decreased toward the lowest conductance value, applying sequence of pulses Pn including trailing edge duration Tn longer than leading edge duration Ln enables improved phase configuration control compared to approaches in which a sequence of pulses does not include a trailing edge duration longer than a leading edge duration.

FIGS. 2A-2Dare diagrams of respective pulse sequences200A-200D, in accordance with some embodiments. As discussed below, pulse sequence200A includes identical pulses Pn, pulse sequence200B includes pulses Pn in which values of amplitude An increase with increasing pulse number, pulse sequence200C includes pulses Pn in which values of pulse width PWn increase with increasing pulse number, and pulse sequence200D includes pulses Pn in which values of trailing edge duration Tn increase with increasing pulse number.

FIG. 2Adepicts pulses Pn of pulse sequence200A corresponding to pulse numbers n=1, 2, and N. As depicted inFIG. 2A, pulses P1, P2, and PN have same values of each of amplitudes A1, A2, and AN, leading edge durations L1, L2, and LN, pulse widths PW1, PW2, and PWN, and trailing edge durations T1, T2, and TN for respective pulse numbers n=1, 2, and N. Pulses Pn of pulse sequence200A thereby have a waveform independent of pulse number n.

FIG. 2Bdepicts pulses Pn of pulse sequence200B corresponding to pulse numbers n=1, 2, and N. As depicted inFIG. 2B, pulses P1, P2, and PN have same values of each of leading edge durations L1, L2, and LN, pulse widths PW1, PW2, and PWN, and trailing edge durations T1, T2, and TN for respective pulse numbers n=1, 2, and N. Pulses Pn of pulse sequence200B have amplitudes A1, A2, and AN that increase in value with increasing pulse number n.

In some embodiments, values of amplitude An increase linearly with increasing pulse number n such that, for each pair of consecutive pulse numbers n of pulse sequence200B, a difference in values of amplitudes An is the same. In various embodiments, values of amplitudes An have one or more relationships to pulse number n of pulse sequence200B other than linear by which the values of amplitude An increase with increasing pulse number n.

FIG. 2Cdepicts pulses Pn of pulse sequence200C corresponding to pulse numbers n=1, 2, and N. As depicted inFIG. 2C, pulses P1, P2, and PN have same values of each of amplitudes A1, A2, and AN, leading edge durations L1, L2, and LN, and trailing edge durations T1, T2, and TN for respective pulse numbers n=1, 2, and N. Pulses Pn of pulse sequence200C have pulse widths PW1, PW2, and PWN that increase in value with increasing pulse number n.

In some embodiments, values of pulse width PWn increase linearly with increasing pulse number n such that, for each pair of consecutive pulse numbers n of pulse sequence200C, a difference in values of pulse widths PWn is the same. In various embodiments, values of pulse widths PWn have one or more relationships to pulse number n of pulse sequence200C other than linear by which the values of pulse width PWn increase with increasing pulse number n.

FIG. 2Ddepicts pulses Pn of pulse sequence200D corresponding to pulse numbers n=1, 2, and N. As depicted inFIG. 2D, pulses P1, P2, and PN have same values of each of amplitudes A1, A2, and AN, leading edge durations L1, L2, and LN, and pulse widths PW1, PW2, and PWN for respective pulse numbers n=1, 2, and N. Pulses Pn of pulse sequence200D have trailing edge durations T1, T2, and TN that increase in value with increasing pulse number n.

In some embodiments, values of trailing edge duration Tn increase linearly with increasing pulse number n such that, for each pair of consecutive pulse numbers n of pulse sequence200D, a difference in values of trailing edge durations Tn is the same. In various embodiments, values of trailing edge durations Tn have one or more relationships to pulse number n of pulse sequence200D other than linear by which the values of trailing edge duration Tn increase with increasing pulse number n.

In each of the embodiments discussed above, pulse sequences200A-200D include pulses Pn having trailing edge durations Tn longer than leading edge durations Ln, thereby obtaining the benefits discussed above with respect to sequence of pulses Pn.

FIG. 3is a diagram of a neural network layer300, in accordance with some embodiments. Neural network layer300is usable as PCM circuit100, and includes synapse array310usable as pulse generation circuit110and synapse320usable as PCM device120, each discussed above with respect toFIG. 1. Synapse array310includes terminals111and113coupled to respective terminals121and123of synapse320and is thereby configured to provide sequence of pulses Pn as voltage V relative to reference voltage Vr, discussed above with respect toFIG. 1.

Neural network layer300is some or all of a layer of a neural network, e.g., an MLP neural network, in which each of one or more layers is configured to perform one or more matrix computations on data signals, the one or more matrix computations including applying weights to some or all of the data signals. In various embodiments, neural network layer300is some or all of a hidden layer or an output layer of the neural network.

Neural network layer300includes a number m of rows corresponding to voltage signals V1-Vm and a number j of columns corresponding to current signals I1-Ij. Each intersection of a row and a column includes a PCM device configured as an analog synapse represented inFIG. 3as a resistor coupled between the corresponding row and column. Each resistor has a conductance Gjm corresponding to the weight of the analog synapse such that a given current signal Ij is the sum of currents based on each voltage signal V1-Vm multiplied by a respective conductance Gj1-Gjm.

In the non-limiting example depicted inFIG. 3, synapse320includes resistor325coupled between row2and column2having conductance G22, and synapse array310includes the remaining synapses in neural network layer300. The synapses in synapse array310are configured to, in operation, generate sequence of pulses Pn at terminals111/121and113/123, thereby controlling a phase configuration and conductance G22of resistor325in the manner discussed above with respect toFIG. 1. In various embodiments, synapse320corresponds to a resistor coupled elsewhere within neural network layer300and synapse array310corresponds to the remaining synapses accordingly.

In some embodiments, synapse array310includes one or more circuits (not shown) in addition to the remaining synapses and is thereby configured to generate sequence of pulses Pn at terminals111/121and113/123. In some embodiments, synapse320includes one or more circuit elements (not shown) in addition to resistor325such that sequence of pulses Pn is selectively applied to resistor325responsive to one or more control signals. In some embodiments, synapse array310and/or synapse320include one or more terminals (not shown) in addition to terminals111/121and113/123such that sequence of pulses Pn is applied to resistor325through electrical connections separate from those through which synapse320is integrated with synapse array310.

By being configured to control conductance G22of resistor325of synapse320by applying sequence of pulses Pn having trailing edge durations Tn longer than leading edge durations Ln, neural network layer300is capable of realizing the benefits discussed above with respect to sequence of pulses Pn.

FIGS. 4A and 4Bare diagrams of respective PCM devices400A and400B, in accordance with some embodiments. Each of PCM devices400A and400B is usable as PCM device120, includes terminals121and123, and is thereby configured to receive sequence of pulses Pn as voltage V relative to reference voltage Vr, discussed above with respect toFIG. 1. Each ofFIGS. 4A and 4Bdepicts a non-limiting example of a PCM device and is simplified for the purpose of illustration, e.g., by including only a cross-sectional representation based on a single plane.

As depicted inFIG. 4A, PCM device400A includes an electrode427A electrically connected to terminal121, an electrode429A electrically connected to terminal123, and a material layer425A positioned between electrodes427A and429A. Material layer425A includes a portion425AC having the crystalline phase and a portion425AA having the amorphous phase as discussed above with respect to PCM device120andFIG. 1.

Electrodes427A and429A are planar, arranged in parallel, and have a same size and a same shape (not shown), thereby having a pillar arrangement. Accordingly, portions425AC and425AA extend uniformly between electrodes427A and429A, and thereby have relative volumes corresponding to a phase distribution of PCM device400A.

As depicted inFIG. 4B, PCM device400B includes an electrode427B electrically connected to terminal121, an electrode429B electrically connected to terminal123, and a material layer425B positioned between electrodes427B and429B. Material layer425B includes a portion425BC having the crystalline phase and a portion425BA having the amorphous phase as discussed above with respect to PCM device120andFIG. 1.

Electrodes427B and429B are planar, arranged in parallel, and electrode429B is smaller than electrode427B, electrodes427B and429B thereby having an arrangement referred to as a mushroom arrangement in some embodiments. Accordingly, portion425BA extends across electrode429B and portion425BC extends across electrode427B and surrounds some or all of portion425BA. Portions425BC and425BA thereby have relative volumes corresponding to a phase distribution of PCM device400B.

By being configured to control phase distributions, and thereby conductance, of material layers425A and425B, by applying sequence of pulses Pn having trailing edge durations Tn longer than leading edge durations Ln, a PCM circuit, e.g., PCM circuit100discussed above with respect toFIG. 1, including a respective one of PCM devices400A or400B is capable of realizing the benefits discussed above with respect to sequence of pulses Pn.

FIG. 5is a flowchart of a method500of altering a conductance of a PCM device, in accordance with some embodiments. In some embodiments, altering the conductance of the PCM device includes altering the conductance of PCM device120discussed above with respect toFIG. 1.

In some embodiments, some or all of method500is executed by a processor of a computer. In some embodiments, some or all of method500is executed by processor702of pulse generation system700, discussed below with respect toFIG. 7.

In some embodiments, the operations of method500are performed in the order depicted inFIG. 5. In some embodiments, the operations of method500are performed simultaneously and/or in an order other than the order depicted inFIG. 5. In some embodiments, one or more operations are performed before, between, during, and/or after performing one or more operations of method500.

At operation510, a pulse sequence is applied to a PCM device, each pulse of the pulse sequence including a trailing edge having a duration longer than a duration of a leading edge of the pulse. In some embodiments, each pulse of the pulse sequence also includes a pulse number, an amplitude, and a pulse width, and applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration.

In some embodiments, applying the pulse sequence includes applying sequence of pulses Pn discussed above with respect toFIG. 1. In some embodiments, applying the pulse sequence includes applying one of pulse sequences200A-200D discussed above with respect to respectiveFIGS. 2A-2D.

In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing amplitude An discussed above with respect toFIGS. 1-2D. In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing the amplitude linearly with respect to the pulse number.

In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing pulse width PWn discussed above with respect toFIGS. 1-2D. In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing the pulse width linearly with respect to the pulse number.

In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing trailing edge duration Tn discussed above with respect toFIGS. 1-2D. In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing the trailing edge duration linearly with respect to the pulse number.

In some embodiments, applying the pulse sequence to the PCM device includes generating the pulse sequence with a pulse generation circuit. In some embodiments, generating the pulse sequence with the pulse generation circuit includes generating the pulse sequence with pulse generation circuit110discussed above with respect toFIG. 1.

In some embodiments, generating the pulse sequence with the pulse generation circuit includes generating the pulse sequence with an analog synapse array. In some embodiments, generating the pulse sequence with the pulse generation circuit includes generating the pulse sequence with analog synapse array310discussed above with respect toFIG. 3.

In some embodiments, generating the pulse sequence with the pulse generation circuit includes defining the pulse sequence using a processor. In some embodiments, defining the pulse sequence using a processor includes defining the pulse sequence using processor702discussed below with respect toFIG. 7.

In some embodiments, generating the pulse sequence with the pulse generation circuit includes using a processor to cause a pulse generation circuit to apply the pulse sequence to the PCM device. In some embodiments, causing the pulse generation circuit to apply the pulse sequence to the PCM device includes using processor702discussed below with respect toFIG. 7.

In some embodiments, applying the pulse sequence to the PCM device includes applying the pulse sequence to an analog synapse. In some embodiments, applying the pulse sequence to the analog synapse includes applying the pulse sequence to analog synapse320discussed above with respect toFIG. 3.

In some embodiments, applying the pulse sequence to the PCM device includes applying the pulse sequence to a material layer of the PCM device. In some embodiments, applying the pulse sequence to the PCM device includes applying the pulse sequence to material layer125of PCM device120discussed above with respect toFIG. 1. In some embodiments, applying the pulse sequence to the PCM device includes applying the pulse sequence to material layer425A of PCM device400A or material layer425B of PCM device400B discussed above with respect to respectiveFIGS. 4A and 4B.

In some embodiments, applying the pulse sequence includes applying each pulse having the corresponding trailing edge duration corresponding to a crystallization temperature of the material layer. In some embodiments, applying each pulse having the corresponding trailing edge duration corresponding to the crystallization temperature of the material layer includes defining the corresponding trailing edge duration using a processor. In some embodiments, defining the corresponding trailing edge duration using a processor includes using processor702discussed below with respect toFIG. 7.

At operation520, in response to applying the pulse sequence, a conductance level of the PCM device is altered. In some embodiments, altering the conductance level of the PCM device includes lowering the conductance level of the PCM device. In some embodiments, altering the conductance level of the PCM device includes altering the conductance level of PCM device120discussed above with respect toFIG. 1.

In some embodiments, altering the conductance level of the PCM device includes altering a phase configuration of a material layer of the PCM device. In some embodiments, altering the phase configuration includes decreasing a value of a ratio of a crystalline phase of a material layer to an amorphous phase of the material layer.

In some embodiments, altering the conductance level of the PCM device includes altering the phase configuration of material layer125discussed above with respect toFIG. 1. In some embodiments, altering the conductance level of the PCM device includes altering the phase configuration of material layer425A of PCM device400A or material layer425B of PCM device400B discussed above with respect to respectiveFIGS. 4A and 4B.

In some embodiments, altering the conductance level of the PCM device includes altering a weight of an analog synapse. In some embodiments, altering the weight of the analog synapse includes altering the weight of synapse320discussed above with respect toFIG. 3.

At operation530, in some embodiments, a read operation is performed after each pulse of the pulse sequence to determine a conductance value of the PCM device. In some embodiments, performing the read operation includes characterizing the PCM device. In some embodiments, characterizing the PCM device includes determining a relationship between increasing pulse numbers and decreasing conductance values.

In some embodiments, performing the read operation includes obtaining a measurement value of a current through the PCM device in response to a voltage applied to the PCM device. In some embodiments, performing the read operation includes obtaining a measurement value of current I in response to applied voltage Va discussed above with respect to PCM device120andFIG. 1.

By executing some or all of the operations of method500, a conductance level of a PCM device is altered by applying a sequence of pulses having trailing edge durations longer than leading edge durations, thereby controlling the PCM device conductance level so as to realize the benefits discussed above with respect to sequence of pulses Pn.

FIGS. 6A and 6Bdepict PCM device operating parameters, in accordance with some embodiments. Each ofFIGS. 6A and 6Bincludes a horizontal axis corresponding to pulse number n including values ranging from 1 to number of pulses N, and a vertical axis corresponding to a property (discussed below) of material layer125of PCM device120, each discussed above with respect to sequence of pulses Pn andFIGS. 1-2D. In some embodiments, the PCM device operating parameters depicted inFIGS. 6A and 6Bcorrespond to characterization data obtained by executing some or all of method500discussed above with respect toFIG. 5.

In the non-limiting example depicted inFIGS. 6A and 6B, sequence of pulses Pn corresponds to pulse sequence200B in which values of amplitude An increase with increasing pulse number n, discussed above with respect toFIG. 2B. Accordingly, increasing pulse number n along the horizontal axis corresponds to increasing values of amplitude An (not shown inFIGS. 6A and 6B) of pulse Pn along the horizontal axis. In some embodiments, PCM device operating parameters include increasing pulse number n along the horizontal axis corresponding to increasing values of pulse width PWn or trailing edge duration Tn of pulse Pn, discussed above with respect to respectiveFIGS. 2C and 2D.

FIG. 6Adepicts material layer125resistance values Rn as a function of pulse number n, with resistance values Rn plotted on a logarithmic scale. As depicted inFIG. 6A, application of first pulse P1having amplitude A1corresponding to pulse number n=1 is associated with a decrease in resistance value R1from resistance values Rn prior to application of first pulse P1. Application of pulses Pn corresponding to increasing pulse number n and amplitude An for n=2 through n=N is associated with continued decreases in resistance values Rn followed by increases in resistance values Rn.

FIG. 6Bdepicts material layer125conductance values Gn as a function of pulse number n, with conductance values Gn plotted on a linear scale. As depicted inFIG. 6B, application of pulses Pn corresponding to increasing pulse number n and amplitude An for n=1 through n=N is associated with initial increases in conductance values Gn followed by decreases in conductance values Gn, the distribution of conductance levels Gn as a function of pulse number n thereby having an approximately symmetrical shape.

Particularly with respect to the decreases in conductance values Gn,FIGS. 6A and 6Billustrate the ability to control conductance levels of a PCM device, e.g., PCM device120, by applying sequence of pulses Pn including trailing edge duration Tn longer than leading edge duration Ln, discussed above with respect toFIG. 1.

FIG. 7is a block diagram of a pulse generation system700, in accordance with some embodiments. Some or all of method500of altering a conductance of a PCM device, in accordance with one or more embodiments, is implementable, for example, using pulse generation system700, in accordance with some embodiments.

In some embodiments, pulse generation system700is a general purpose computing device including a processor702and a non-transitory, computer-readable storage medium704. Computer-readable storage medium704, amongst other things, is encoded with, i.e., stores, computer program code706, i.e., a set of executable instructions. Execution of computer program code706by processor702represents (at least in part) a pulse generation tool which implements a portion or all of a method according to an embodiment, e.g., method500described above with respect toFIG. 5(hereinafter, the noted processes and/or methods).

Processor702is electrically coupled to computer-readable storage medium704via a bus708. Processor702is also electrically coupled to an I/O interface710by bus708. A network interface712is also electrically connected to processor702via bus708. Network interface712is connected to a network714, so that processor702and computer-readable storage medium704are capable of connecting to external elements via network714. Processor702is configured to execute computer program code706encoded in computer-readable storage medium704in order to cause system700to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor702is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium704stores computer program code706configured to cause pulse generation system700(where such execution represents (at least in part) the pulse generation tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium704also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium704stores pulse sequence data707including pulse parameters, e.g., voltage and timing definitions corresponding to sequence of pulses Pn discussed above with respect toFIGS. 1-2D, and/or PCM device characterization data, e.g., as discussed above with respect toFIGS. 5-6B.

Pulse generation system700includes I/O interface710. I/O interface710is coupled to external circuitry. In one or more embodiments, I/O interface710includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor702.

Pulse generation system700also includes network interface712coupled to processor702. Network interface712allows system700to communicate with network714, to which one or more other computer systems are connected. Network interface712includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems700.

Pulse generation system700is configured to receive information through I/O interface710. The information received through I/O interface710includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor702. The information is transferred to processor702via bus708. Pulse generation system700is configured to receive information related to a UI through I/O interface710. The information is stored in computer-readable storage medium704as user interface (UI)742.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of a pulse generation tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by pulse generation system700.

By being configured to execute some or all of the operations of a method, e.g., method500, pulse generation system700is capable of altering a conductance level of a PCM device by applying a sequence of pulses having trailing edge durations longer than leading edge durations, thereby controlling the PCM device conductance level so as to realize the benefits discussed above with respect to sequence of pulses Pn.

In some embodiments, a method of altering a conductance of a PCM device includes applying a pulse sequence to the PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and, in response to applying the pulse sequence, altering a conductance level of the PCM device. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. In some embodiments, applying the pulse sequence to the PCM device includes applying the pulse sequence to a material layer of the PCM device. In some embodiments, applying the pulse sequence includes applying each pulse having the corresponding trailing edge duration corresponding to a crystallization temperature of the material layer. In some embodiments, altering the conductance level of the PCM device includes lowering the conductance level of the PCM device. In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing the amplitude linearly with respect to the pulse number. In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing the pulse width linearly with respect to the pulse number. In some embodiments, increasing the at least one of the amplitude, the pulse width, or the trailing edge duration includes increasing the trailing edge duration linearly with respect to the pulse number. In some embodiments, altering the conductance level of the PCM device includes decreasing a value of a ratio of a crystalline phase of a material layer to an amorphous phase of the material layer. In some embodiments, altering the conductance level of the PCM device includes altering a weight of an analog synapse. In some embodiments, the method includes performing a read operation after each pulse of the pulse sequence.

In some embodiments, a circuit includes a pulse generation circuit configured to output a pulse sequence, wherein each pulse of the pulse sequence includes a pulse number, at least one of an amplitude, a pulse width, or a trailing edge duration having a value that increases with the pulse number, and the trailing edge duration longer than a duration of a leading edge of the pulse. The circuit includes a PCM device configured to, responsive to the pulse sequence, reset from a first phase configuration having a first conductance value to a second phase configuration having a second conductance value. In some embodiments, the PCM device includes a PCM material, the first conductance value corresponds to a first value of a ratio of a crystalline phase of the PCM material to an amorphous phase of the PCM material, and the second conductance value corresponds to a second value of the ratio less than the first value of the ratio. In some embodiments, the PCM material includes a compound including two or more of germanium, antimony, or tellurium. In some embodiments, the PCM device includes a first analog synapse of a synapse array. In some embodiments, the pulse generation circuit includes a second analog synapse of the synapse array. In some embodiments, the PCM device comprises first and second electrodes configured to receive the pulse sequence, the first and second electrodes having a pillar or mushroom arrangement.

In some embodiments, a pulse generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the pulse generation system to define a pulse sequence having a number of pulses N, and, for each pulse of the pulse sequence, define a trailing edge having a duration longer than a duration of a leading edge, cause the pulse to be applied to a PCM device, and perform a read operation to determine a conductance value of the PCM device. In some embodiments, the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the pulse generation system to define the pulse sequence having the number of pulses N ranging from 20 to 80. In some embodiments, the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the pulse generation system to define the trailing edge duration of each pulse based on a crystallization temperature of a material layer of the PCM device. In some embodiments, each pulse of the pulse sequence includes a pulse number n (1≤n≤N), and the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the pulse generation system to define values of at least one of an amplitude, a pulse width, or the trailing edge duration of each pulse that increase as a linear function of the pulse number n.