Package carrier and manufacturing method thereof

A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 102135030, filed on Sep. 27, 2013. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

The present invention relates to a package structure and a manufacturing method thereof. More particularly, the present invention relates to a package carrier and a manufacturing method thereof.

DESCRIPTION OF RELATED ART

The purpose of chip packages is to protect exposed chips, to reduce contact density in a chip, and to provide good thermal dissipation for chips. The chip can be connected to the carrier by wire bonding or by flip chip bonding, such that the bonding pads on the chip can be electrically connected to contacts of the carrier, thereby forming a chip package. Therefore, the contacts on the chip can be re-distributed through the package carrier, so as to comply with contact distribution of external devices of next hierarchy.

Generally, in order to form the package carrier, a core dielectric layer often serves as a core material, and patterned circuit layers and patterned dielectric layers are alternately stacked on the core dielectric layer by performing a fully additive process, a semi-additive process, a subtractive process, or any other process. Consequently, the core accounts for a relative great proportion of the whole thickness of the package carrier. Therefore, if there is a bottleneck in reducing the thickness of the core dielectric layer, it will be hard for the whole thickness of the package structure to be remarkably reduced.

SUMMARY OF THE INVENTION

The present invention is directed to a package carrier capable of carrying a chip and the thickness of a package structure using the package carrier is reduced.

The present invention is directed to a manufacturing method of a package carrier for manufacturing the package carrier described above.

The present invention provides a manufacturing method of a package carrier including the following steps. Firstly, two base metal layers are bonded. Next, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal foil and a second metal foil separable from each other. Next, two patterned metal layer are formed on the release metal films respectively, wherein each of the patterned metal layers is capable of carrying and electrically connected to a chip. Afterward, the two base metal layers are separated from each other to form two package carriers independent from each other.

The present invention provides a package carrier capable of carrying a chip. The package carrier includes a supporting layer, a base metal layer, a release metal film and a patterned metal layer. The supporting layer includes a first surface and a second surface opposite to the first surface. The base metal layer is disposed on the first surface of the supporting layer. The release metal film is disposed on the second surface of the supporting layer. The release metal film includes a first metal foil and a second metal foil, and the second metal foil is bonded with the supporting layer. The patterned metal layer is disposed on the first metal foil, wherein the chip is adapted to be disposed on the patterned metal layer and electrically connected to the patterned metal layer.

In light of the foregoing descriptions, the manufacturing processes of the package carrier in the invention are symmetrically performed on two base metal layers bonded with each other. Therefore, two independent package carriers are formed simultaneously after the base metal layers are separated, so as to save the manufacturing time and improve the production efficiency. In addition, the package carrier of the invention adopts the patterned metal layer to carry and electrically connects the chip, and the release metal film is connected between the supporting layer and the patterned metal layer, such that the supporting layer can be easily removed after the molding process by adopting the separable characteristic of the release metal film. Therefore, comparing with the conventional package carrier composed of a plurality of patterned circuit layers and patterned dielectric layers alternately stacked on the core dielectric layer, the package carrier of the invention allows the package structure using said package carrier to have a thinner overall thickness.

To make the above features and advantages of the present invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A to 1Gare schematic cross-sectional views illustrating manufacturing steps of a package carrier according to an embodiment of the present invention. In the present embodiment, a manufacturing method of a package carrier includes the following steps. Firstly, referring toFIG. 1A, two base metal layers110are bonded. In the present embodiment, the two base metal layers110may be two copper foils, and is bonded by dispensing an adhesive layer105on edges of the two base metal layers110to form a sealing region at the edges of the two base metal layers110, such that the two base metal layers can be bonded together temporarily for preventing infiltration of chemicals or reagents used in subsequent processes.

Referring toFIG. 1B, two supporting layers120are laminated onto the base metal layers110respectively. Then, two release metal films130are disposed on the supporting layers120respectively, wherein each of the release metal films130includes a first metal foil132and a second metal foil134separable from each other. In one embodiment of the invention, the thickness of the second metal foil134is substantially greater than the thickness of the first metal foil132. To be specific, the thickness of the second metal foil134is about 18 micrometers (μm), and the thickness of the first metal foil132is about 5 micrometers. It is for sure that the present invention should not be construed as limited to the embodiments of the present invention.

Next, referring to bothFIG. 1CandFIG. 1D, two patterned photo-resist layers150shown inFIG. 1Care formed on the two release metal films130respectively, wherein each of the patterned photo-resist layers150may includes a plurality of openings152to expose a part of the corresponding release metal film130. Next, referring toFIG. 1D, the two patterned metal layers140are respectively formed in the openings152by using the patterned photo-resist layers150as masks, such that the two patterned metal layers140cover the part of the release metal films130exposed by the openings152. Each of the patterned metal layers140is capable of carrying and electrically connecting a chip. In the present embodiment, each of the patterned metal layers140may include a chip pad142and a plurality of bonding pads144shown inFIG. 1D. The chip may be, for example, disposed on the chip pad142and electrically connected to the bonding pads144by a plurality of conductive wires. In the present embodiment, the patterned metal layer140includes a plurality of circuits, and the width of each circuit of the patterned metal layer140is, for example, between 15 micrometers to 35 micrometers. That is, the circuits of the patterned metal layer140of the present embodiment may be seen as fine circuits. Moreover, the thickness of the patterned metal layer140formed by the method described above can be controlled according to the thickness of the patterned photo-resist layer150. Therefore, a user may adjust the thickness of the package carrier formed by said manufacturing method by controlling the thickness of the patterned metal layer140. Of course, in other embodiment, the patterned metal layers140may also be formed by subtractive process such as etching process.

In addition, in an embodiment of the invention, two etching stop layers160may be respectively formed on the parts of the release metal films exposed by the openings152before the patterned metal layers140are formed. The etching stop layers160are, for example, nickel layers, and may be formed in the openings152of the patterned photo-resist layers150by electroplating.

Afterward, two surface treatment layers170are formed on top surfaces of the two patterned metal layers140respectively as shown inFIG. 1E. In the present embodiment, each of the surface treatment layer170includes an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a chemical plated nickel-palladium-gold layer or an organic solderability preservatives (OSP) layer, etc. Of course, the embodiment is not limited thereto. After that, the patterned photo-resist layers150are removed, so as to form the two patterned metal layers140shown inFIG. 1Fon the two release metal films130respectively.

Afterward, the sealing region of the two base metal layers110are separated, such that the two base metal layers110are separated from each other to form two package carriers100independent from each other as shown inFIG. 1G. Accordingly, each of the package carriers100formed by the manufacturing method described above includes a base metal layer110, a supporting layer120, a release metal film130and a patterned metal layer140. The supporting layer120includes a first surface122and a second surface124opposite to the first surface122. The base metal layer110is disposed on the first surface122of the supporting layer120. The release metal film130is disposed on the second surface124of the supporting layer120, wherein the release metal film130includes a first metal foil132and a second metal foil134separable from each other. The second metal foil134is bonded with the supporting layer120and the patterned metal layer140is disposed on the first metal foil132. That is to say, the first metal foil132and the second metal foil134are respectively bonded with the patterned metal layer140and the supporting layer120.

It is noted that, in the present embodiment, the supporting layers120and the patterned metal layers140thereon are symmetrically formed, so the warp of the structure during the lamination process of the supporting layers120can be effectively avoided. Furthermore, the manufacturing processes of the package carrier of the embodiment are symmetrically performed on the two base metal layers bonded with each other, so two independent package carriers are formed simultaneously after the base metal layers are separated, such that the manufacturing time is saved and the production efficiency is improved.

FIGS. 2A to 2Dare schematic cross-sectional views illustrating manufacturing steps of the package carrier depicted inFIG. 1Gcarrying a chip. Referring toFIG. 2A, in the present embodiment, the package carrier100formed by the manufacturing method described above is capable of carrying and electrically connect a chip200. In the present embodiment, the chip200may be, for example, a single chip or a chip module. Hence, this embodiment does not restrict the types of the chip200. The chip200may be disposed on the chip pad142of the patterned metal layer140through an adhesive layer, and the chip200may be electrically connected to the bonding pads144of the patterned metal layer140by a plurality of conductive wires210. That is to say, the chip200of the present embodiment is electrically connected to the patterned metal layer140through wire bonding.

Next, referring toFIG. 2B, a molding process is performed to form a molding compound220on the package carrier100, wherein the molding compound200covers the chip200, the conductive wires210and the patterned metal layer140and covers a part of the first surface122of the supporting layer120. Afterward, referring toFIG. 2C, the first metal foil132and the second metal foil134are separated from, each other to remove the supporting layer120, and then the release metal film130such as the first metal foil132remaining on the patterned metal layer140is removed by etching process to expose the patterned metal layer140and a bottom surface of the molding compound220.

Herein, the etching stop layer160is firstly formed on the release metal film130before the patterned metal layer140is formed. That is, the etching stop layer160is located between the patterned metal layer140and the release metal film130. Therefore, when the release metal film130is removed by the etching process, the etching process would stop at the etching stop layer160so that the patterned metal layer140would not be subjected to damage. Finally, the etching stop layer160is removed to form the package structure10as shown inFIG. 2D. In the present embodiment, the package structure10is electrically connected to an external electronic device by, for example, a plurality of solder balls230.

It is noted that the invention does not limit the bonding method of the chip200and the package carrier100, even though the chip200is shown to be electrically connected to the package carrier100through wire bonding. However, in other embodiment, the chip200may also be electrically connected to the patterned metal layer140through flip chip bonding technique. That is, the aforesaid bonding methods of the chip200and the package carrier100are merely exemplary and should not be construed as limitations to the present invention.

In sum, the manufacturing processes of the package carrier of the invention are symmetrically performed on two base metal layers bonded with each other. Therefore, two independent package carriers are formed simultaneously after the base metal layers are separated, such that the manufacturing time can be saved and the production efficiency can be improved. In addition, the invention uses the patterned metal layer to carry and electrically connects the chip, and the release metal film is connected between the supporting layer and the patterned metal layer, such that the supporting layer can be easily removed after the molding process by taking advantage of the separable characteristic of the release metal film. Therefore, comparing with the conventional package carrier composed of a plurality of patterned circuit layers and patterned dielectric layers alternately stacked on the core dielectric layer, the package carrier of the invention allows the package structure using said package carrier to have a thinner overall thickness. Moreover, the heat generated by the chip can be quickly dissipated to external environment directly through the patterned metal layer since the chip is disposed on the patterned metal layer. That is, the package carrier of the invention not only can effectively reduce the overall thickness of the package structure, but also can improve the heat dissipation efficiency of the package structure.

Although the present invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims and not by the above detailed descriptions.