Bi-directional coupler with termination point for a test point

In one embodiment, an apparatus includes a bi-directional coupler for coupling an upstream signal and a downstream signal to a termination load. A test point detection mechanism is configured to detect when a test point device is inserted in a test point connector. The test point device is configured to perform a test of the upstream signal or the downstream signal. A switch is configured to switch from being coupled to the termination load to being coupled to the test point device when the test point device is detected as being inserted in the test point connector. The switch is configured to switch from being coupled to being coupled to the test point device to the termination load when the test point device is detected as being removed from being inserted in the test point connector.

BACKGROUND

A test point may be used to measure the performance of an upstream or downstream connection in a network. In one implementation, two separate directional couplers are used to connect two test points (TPs) to measure an upstream and a downstream signal. One directional coupler for a first test point is used for the downstream direction and a second directional coupler for a second test point is used for the upstream connection. This leaves an isolating port that is terminated by a termination load, such as a 75-ohm termination load if the test point also has a load of 75-ohms. The coupler directivity is limited by how good the isolating port is terminated and this achieves maximum directivity performance because the load of the isolating port is the same as the load of the test point.

In a full duplex node design, the use of two separate couplers may add too much of a loss at an output of a power amplifier connected to the coupler. With use of two separate couplers, the insertion loss will be doubled, from 1 dB in single coupler case to 2 dB in two coupler case. The output RF amplifier may already be running very close to its clipping point. With the use of a single coupler, the RF amplifier will not need to provide as much amplification compared to the two coupler case, which will improve the system level modulation error ration or bit error ratio (MER/BER) performance. Accordingly, a single bi-directional coupler may have to be used for both the upstream direction and the downstream direction. One advantage of using a bi-directional coupler is there is a lower insertion loss in the connection because only one coupler is used in both the upstream and the downstream directions. However, isolation between the upstream connection and the downstream connection may be an issue. The directivity of a coupler is defined as the power difference at any given coupling port when the same amount of power is injected into either the downstream direction or the upstream direction. A coupler may have around 25-30 decibels (dB) directivity, which means there may be 25-30 dB isolation between the upstream direction and the downstream direction at any given coupling port. However, this is based on an ideal 75-ohm termination at the isolating port. In a bi-directional coupler, the termination at the isolating port is typically not the perfect 75-ohm termination and thus will limit the isolation between the downstream and the upstream to the return loss of the isolating port. For example, the ideal isolation may not be achieved because one or both of the upstream test point and the downstream test point may not be connected to the bi-directional coupler. For example, a user may only be using one of the test points to test network traffic in one direction. This leaves an open test point port. In the full duplex node design, a 20 dB test point is required and a 10 dB coupler is used. The best return loss from the open test point port is 20 dB, which would limit the coupler directivity at 20 dB even when the coupler has 30 dB directivity by design when all ports are properly terminated. In the worst case, when two reflections are added in phase from two open test point ports, the total isolation between the downstream connection and the upstream connection could be as low as 16 dB.

In a network implementation, a physical (PHY) device can be located in the headend and converts packets on a digital interface, such as an Ethernet interface, to analog signals, such as radio frequency (RF) signals, on a hybrid fiber coaxial (HFC) network. The physical device sends the RF signals to modems located at a subscriber's premises. However, other implementations, such as a distribution access architecture (DAA), have moved the physical device to a location closer to the subscriber's premises, such as in a node located in the neighborhood where the subscribers are located. The relocated physical device is referred to as a remote physical device (RPD).

The DAA in the longer term may replace analog fiber with Internet protocol (IP) digital connections. However, many cable operators in the shorter term and in the early DAA deployment, envision an analog radio frequency (RF) overlay on top of the digital connections (e.g., the digital optical links) to continue to leverage the already-deployed analog broadcast channel assets (e.g., analog network deployments). Digital optical links are typically implemented via multi-source agreement (MSA) compliant digital small form pluggable (SFP) optical transceiver modules. Analog overlay solutions for DAA deployments also may leverage standard packaging design used in the MSA-compliant digital SFP optical transceiver modules. For example, an analog SFP transceiver module may look similar to the digital SFP transceiver module when viewed by a user. Further, both the digital and analog SFP modules leverage MSA specifications, such as a similar physical pin-out between a digital SFP module and analog SFP module may be similar or exactly the same. Also, both the digital SFP module and analog SFP module may use the same pin to receive a power supply voltage, such as pin #16. However, the digital SFP module and analog SFP module may use different power supply voltages, such as the analog SFP module may use a +5 volt (V) power supply voltage and the digital SFP module may use a +3.3V power supply voltage. Because the analog SFP module and digital SFP module may use the same pin for the power supply, when a digital SFP module is inadvertently inserted into an analog SFP module slot, the digital SFP module will be immediately damaged due to the +5V power supply being provided to the digital SFP module instead of the +3.3V power supply.

DETAILED DESCRIPTION

Described herein are techniques for a bi-directional coupler system. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of some embodiments. Some embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

Some embodiments include a first switch that is controlled to terminate a first port of a bi-directional coupler when a first test point is not connected to the first port. Also, some embodiments include a second switch that is controlled to terminate a second port of the bi-directional coupler when a second test point is not connected to the second port. The bi-directional coupler may couple an upstream signal in an upstream direction and a downstream signal in a downstream direction. The first switch is used at an upstream port and the second switch is used at a downstream port. The switches may toggle between a termination load and a test point. When the test point is inserted in a test point connector, the first switch connects the test point to the bi-directional coupler. However, when an upstream test point is not inserted in an upstream test point connector, the first switch switches to connect a first termination load to the upstream port. Also, when a downstream test point is not inserted in a downstream test point connector, the second switch switches to connect a second termination load to the downstream port.

The use of the switch and the termination loads improve the coupler directivity because there is not an open test point connection at one of the upstream port or downstream port when one of the upstream test point or the downstream test point is not inserted in a test point connector. For example, all ports of the bi-directional coupler are properly terminated at all times and the bi-directional coupler may have the maximum directivity afforded by the design of the bi-directional coupler.

System Overview

FIG.1depicts a simplified system100that terminates ports in a bi-directional coupler according to some embodiments. System100includes a node102, a head end104, and customer premise equipment (CPE)106. In some embodiments, node102is separate from headend104. However, components of node102may also be included in head end104. In some cases, an operator would like to have a test point inserted in both directions so that the operators can check system level performance without interrupting the operation of a live network. Although the following network is described, some embodiments may be used in other network configurations, such as WiFi or wireless networks.

In a full duplex design, the downstream connection and the upstream connection may use the same spectrum. A single bi-directional coupler108may be used to couple the downstream signal to downstream components for processing and also couple the upstream signal to the upstream components for processing. Using the bi-directional coupler108is different from using a separate coupler for the upstream direction and a separate coupler for the downstream direction as described in the Background.

In the downstream direction, head end104may send a signal to node102, such as a digital signal through a digital medium. In some embodiments, the signal may be programming for a cable television system; however, other content may be sent. In other examples, head end104may send an analog signal through an analog medium to node102.

A small-form pluggable transceiver (SFP)124may receive the downstream signal. In some embodiments, the transceiver may be a regular SFP digital transceiver or an enhanced SFP transceiver (SFP+) that may have more bandwidth capabilities then the regular SFP transceiver. Also, an analog signal may be received and processed by an analog receiver.

A field programmable logic gate array (FPGA)112receives the signal and can convert the downstream signal using a digital-to-analog converter (DAC) from the digital signal to an analog signal. An amplifier120-1, such as an RF amplifier, amplifies the analog signal and sends the analog signal to bi-directional coupler108. Bi-directional coupler108may then couple the downstream signal to CPE106, which may be a cable modem or other subscriber device. CPE106receives the signal and can output the signal, such as to a subscriber device.

In the upstream direction, CPE106may send an upstream signal to node102. The upstream signal may be an analog signal. Bi-directional coupler108may couple the upstream signal through a splitter126. Splitter126splits the signal and sends the signal to an amplifier, such as an RF amplifier120-2. After amplifying the analog signal, FPGA122may use an analog-to-digital converter (ADC) to convert the analog signal to a digital signal. The digital signal is sent through SFP124to head end104. In other examples, node102may send an analog signal.

In some embodiments, test points may be inserted into an upstream connection or a downstream connection in node102. For example, node102may have a test point connector (e.g., slot or other connection device) in which test points can be inserted. When the term inserted is used, the insertion may be any type of connection that can be made with a test point114. For example, test point114may be inserted in a slot, connected to a connection pad, etc. When inserted, test point114may be connected to a board, such as an integrated circuit board, in which test point114is now operational and powered on.

When inserted, the test points may be used to test the connection. An upstream test point (US TP)114-2may be used to test the connection (e.g., bandwidth or other performance metrics) in the upstream direction, which is from CPE106to head end104through node102. A downstream test point (DS TP)114-1may be used to test the connection of a downstream connection from head end104to CPE106through node102. Downstream test point114-1and upstream test point114-2may or may not be inserted into a test point connector. That is, both downstream test point114-1and upstream test point114-2may be connected, both downstream test point114-1and upstream test point114-2may not be connected, downstream test point114-1may be connected, but upstream test point114-2may not be connected, and upstream test point114-1may be connected, but downstream test point114-1may not be connected.

When downstream test point114-1is inserted into a downstream test point connector of bi-directional coupler108, bi-directional coupler108may couple to the downstream signal to downstream test point114-1at a downstream test point port. For example, bi-directional coupler108may couple the downstream signal through attenuator110-1, a switch112-1(e.g., an RF switch) to downstream test point114-1. Although attenuation of the signal may be performed, attenuation may not be needed.

When downstream test point114-1is not inserted in a test point connector, a termination load116-1is connected to bi-directional coupler108at the downstream test point port. For example, the downstream test point port is connected through attenuator110-1, switch112-1to termination load116-1, which may be a 75-ohm load. The 75-ohm load may match the load of upstream test point114-2or termination load116-2. The matching of the loads provides maximum directivity for bi-directional coupler108.

When an upstream test point114-2is inserted into an upstream test point connector of bi-directional coupler108, the upstream signal is sent from the upstream test point port of bi-directional coupler108through splitter126. Splitter126splits the signal and sends the signal to attenuator110-2and switch112-2to upstream test point114-2.

When upstream test point114-2is not connected to a test point connector, switch112-2switches to connect termination load116-2to the upstream test point port. For example, the upstream test point port is connected through attenuator110-2, switch112-2to termination load116-2, which may be a 75-ohm load. The 75-ohm load may match the load of downstream test point114-1or termination load116-1. The matching of the loads also provides maximum directivity for bi-directional coupler108.

A microprocessor118may control switch112-2to couple the upstream test point port to upstream test point114-2or termination load116-2. Also, microprocessor118may control switch112-1to couple downstream test point114-1and termination load116-1to the downstream test point port. Microprocessor118may analyze whether or not downstream test point114-1or upstream test point114-2is inserted in a respective test point connector to determine the position of switch112-1and112-2, respectively.

FIG.2depicts a more detailed example of bi-directional coupler108according to some embodiments. Bi-directional coupler108includes a first port202, a second port204, a downstream test point (TP) port206and an upstream test point (TP) port208. First port202and second port204may be both used for the upstream signal and the downstream signal. For example, when bi-directional coupler108is coupling the downstream signal downstream, first port202is an input downstream port that receives the downstream signal and second port204is an output downstream port that outputs the downstream signal. When bi-directional coupler108is coupling the upstream signal upstream, second port204is an input upstream port that receives the upstream signal and first port202is an output upstream port that outputs the upstream signal.

Switch112-2can switch between termination load116-2and upstream test point114-2. As shown, both upstream test point114-2and termination load116-2may have a 75-ohm load. Although a 75-ohm load is used, the load may be different values. For example, load impedance is 75 ohm for a 75 ohm system (e.g., cable television networks) and 50 ohm for a 50 ohm system (e.g., a WiFi or a wireless system). However, termination load116-2may have the same load (or very similar within a threshold) as downstream test point114-1to provide the maximum isolation and maximum directivity when upstream test point114-2is not connected to upstream test point port208.

Switch112-1may also switch between termination load116-1and downstream test point114-1. Similarly, termination load116-1and downstream test point114-1have the same load of 75-ohms. Termination load116-1may have the same load (or very similar within a threshold) as upstream test point114-2to provide the maximum isolation and directivity when test point114-1is not connected to downstream test point port206.

As discussed above, different combinations of which test points are inserted into test point connections may be appreciated.FIGS.3A,3B, and3Cshow different connections for bi-directional coupler108according to some embodiments.FIG.3Ashows the downstream connection without upstream test point114-2connected to bi-directional coupler108according to some embodiments. Downstream test point114-1has been inserted into a test point connector and is connected to bi-directional coupler108.

Input downstream port202receives a downstream signal and the downstream signal is coupled to output downstream port204. Also, the downstream signal is coupled to downstream test point port206because switch112-1is switched to downstream test point114-1. Accordingly, termination load116-1is not connected to bi-directional coupler108.

Upstream test point port208is also coupled to output downstream port204. This port needs to be properly terminated to provide maximum isolation in the downstream direction. In this example, upstream test point114-2is not inserted in a test point connector. Accordingly, switch112-2is switched to couple termination load116-2to upstream test point port208thereby terminating upstream test point port208and not leaving an open port. Termination load116-2is the same load as downstream test point114-1to provide maximum directivity.

FIG.3Bshows the upstream connection without downstream test point114-1connected to bi-directional coupler108according to some embodiments. Input upstream port204receives an upstream signal and couples the upstream signal to output upstream port202. Also, input upstream port204couples the upstream signal to upstream test point port208. Upstream test point114-2has been inserted into a test point connector and is connected to bi-directional coupler108via switch112-2. Accordingly, termination load116-2is not connected to bi-directional coupler108.

Also, output upstream port202is coupled to downstream test point port206. This port needs to be properly terminated to provide maximum isolation in the upstream direction. In this example, downstream test point114-1is not inserted in a test point connector. Accordingly, switch112-1is switched to couple termination load116-1to downstream test point port206thereby terminating downstream test point port206. Termination load116-1is the same load as upstream test point114-2to provide maximum directivity.

FIG.3Cshows a connection with both downstream test point114-1and upstream test point114-2connected to bi-directional coupler108according to some embodiments. Since both downstream test point114-1and upstream test point114-2are inserted into a respective test point connector, termination loads are not needed. Switch112-1connects downstream test point114-1to downstream test point port206and switch112-2connects upstream test point114-2to upstream test point port208. Both test points114-1and114-2are the same load and provide maximum directivity for bi-directional coupler108.

In some embodiments, both downstream test point114-1and upstream test point114-2may not be inserted into test point connectors. In this example, switch112-1is connected to termination load116-1and switch112-2is connected to termination load116-2.

Different Examples of Detection Mechanisms

The following describes some examples of detection mechanisms. Although these examples of detection mechanisms are described, other examples of detection mechanisms may be used.FIGS.4A and4Bshow a sensor402being used to detect when a test point is inserted into a test point connector408according to some embodiments. InFIG.4A, sensor402, such as a light sensor, can detect a signal, such as light. Sensor402may be located in test point connector408in which a test point114may be inserted. For example, sensor402may be on a circuit board in which test point114may be inserted to connect to test point connector408.

Node102includes an emitter, such as light emitter404, that emits the signal, such as light, which may be detected by sensor402. For example, light may reflect off a surface406in node102to sensor402. However, in other examples, the light may not need to be reflected off a surface. Rather, the light may be emitted directly to sensor402.

FIG.4Bshows an example when a test point114is inserted into test point connector408according to some embodiments. When test point114is inserted into test point connector408, test point114becomes operational as in test point114can test network characteristics for node102. However, test point114needs to be coupled to a port of bi-directional coupler108. When the light emitted by emitter404is blocked from reaching light sensor402, light sensor402may output a signal indicating that test point114has been inserted in test point connector408. In some embodiments, the light may be blocked test point114thereby blocking the light from reaching light emitter404. Microprocessor118uses the signal from light sensor402to change a position of switches112-1and/or112-2to couple a test point114to upstream test point port208and/or downstream test point port206as described above.

FIGS.5A and5Bdepict an example of a push-button switch according to some embodiments. InFIG.5A, push-button switch502may be a structure that can be actuated by contact. For example, the push-button switch may be pushed in a direction, such as downward or parallel to the insertion direction of test point114. Push-button switch502may be located at the bottom of test point connector408. However, push-button switch502may also be located at other locations, such as the side of test point connector408. Also, push-button switch502may be actuated in any direction, such as parallel to a circuit board or perpendicularly to test point114.

InFIG.5B, when test point114is inserted into test point connector408, push-button switch502is actuated in a downward direction. When push-button switch502is actuated, such as past a threshold, then push-button switch502outputs a signal indicating test point114has been inserted into test point connector408. The signal from push-button switch502may be used to change switches112-1and/or112-2to couple test point114to upstream test point port208and/or downstream test point port206as described above.

FIGS.6A and6Bdepict an example of a hinge roller lever switch according to some embodiments. InFIG.6A, hinge folder lever switch602may include a lever that can be actuated in a direction. Hinge folder lever switch602may be located on a side of test point connector1208. A lever with a roller is placed proximate to test point connector1208such that a test point114will contact the roller when inserted in test point connector1208.

InFIG.6B, test point114has been inserted into test point connector1208. At604, the lever of hinge folder lever switch has been moved in a direction that depresses a button. When inserted, test point114moves the roller lever in a direction to actuate a button, such as to depress a button on hinge roller lever switch602. When the button is depressed, hinge roller lever switch602outputs a signal indicating test point114has been inserted into test point connector1208. The signal from hinge folder lever switch602may be used to change switches112-1and/or112-2to couple test point114to upstream test point port1008and/or downstream test point port1006as described above.

Switch Control

As discussed above, each implementation sent a signal that caused a switch to couple test point114to bi-directional coupler108.FIG.7depicts the signaling to control switches112according to some embodiments. Node102includes a detection mechanism702-1that detects whether downstream test point114-1is inserted into test point connector408and a detection mechanism702-2that detects whether upstream test point114-2is inserted into test point connector408. Detection mechanism702-1or702-2may be one of the detection mechanisms described above or may be a different one. When either detection mechanism702-1or702-2detects the insertion of a test point114-1or114-2, respectively, detection mechanism702-1or702-2sends a signal to microprocessor118.

Microprocessor118processes the signal and determines that a test point has been inserted into a respective test point connector408. Once the test point is inserted into the test point connector408, microprocessor118communicates with switch112-1or switch112-2. For example, when downstream test point114-1is inserted into a test point connector408-1, microprocessor118sends a signal to switch112-1to couple downstream test point port206to downstream test point114-1. Similarly, when microprocessor118detects that test point114-2is inserted into a test point connector408-2, microprocessor118sends a signal to switch112-2to couple test point connector114-2to upstream test point port208.

FIG.8depicts a simplified flowchart800of a method for controlling switches according to some embodiments. At802, microprocessor118detects an insertion of a test point114in test point connector408. At804, microprocessor118determines which test point114has been inserted. For example, microprocessor118may determine whether an upstream test point114-2or a downstream test point114-1has been inserted. At806, when a downstream test point114-1has been inserted, microprocessor118changes switch112-1from termination load116-1to downstream test point114-1.

At808, when an upstream test point114-2has been inserted, microprocessor118changes switch112-2from termination load116-2to upstream test point114-2. Accordingly, instead of having an open port when a test point is not inserted in a test point connector, some embodiments couple a termination load to provide better isolation for bi-directional coupler108.

Some embodiments control a power supply voltage being applied to a slot in a node based on the type of module that is inserted into the slot. For example, the slot may be configured to receive a first type of module, such as an analog small-form pluggable (SFP) module. The analog SFP module may be configured to operate with a first power supply voltage, such as a +5V power supply. In some embodiments, a processor for the node may set the default power supply voltage to a second power supply voltage that is different from the first power supply voltage. For example, a lower power supply voltage, such as a +3.3V power supply voltage, may be set as the default power supply voltage to apply to the slot. The +3.3V power supply voltage may be the voltage that a second type of SFP module, such as a digital SFP module, is configured to use or may be a voltage that will not damage the digital SFP module. Thus, if a digital SFP module is accidentally plugged into the slot, the digital SFP module will not be damaged by the power supply voltage of 3.3V. However, if a +5V power supply voltage is being applied to the power supply pin of the digital SFP module, the voltage would damage the digital SFP module because the digital SFP module is not configured to operate with a +5V voltage. The higher voltage could damage some components of the digital SFP module.

To control the power supply voltage, when a module is inserted into a slot of the node, the processor detects the insertion of the module. Then, the processor communicates with the module to determine which type of module has been inserted into the slot. For example, the processor may receive information from the module and use the information to determine whether the module is a digital SFP module or an analog SFP module. Then, the processor may determine the appropriate power supply voltage for the module. For example, the processor can use the +3.3V power supply voltage for a digital SFP module and a +5V power supply voltage for an analog SFP module.

The processor adjusts the power supply voltage being supplied to the power supply pin of the slot to +5V when the analog SFP is detected. However, if the digital SFP module has been inserted into the slot, the processor does not change the power supply voltage.

FIG.9depicts a simplified system100for a network in which a power supply voltage is controlled according to some embodiments. System900includes a headend906, a node902, and customer premise equipment (CPE)904. Headend906and node902may be separated by a network, such as a digital network, (e.g., an Ethernet or an optical network) and/or analog network (e.g., a radio frequency (RF) network). Node902may be located closer to the premises of a subscriber compared to headend906. The premises of the subscriber includes a network device, such as a CPE904(e.g., a cable modem, subscriber device, set-top-box, gateway, etc.). Although this architecture is described, other distributed architectures may be used. Further, the components of node902could be located in headend906.

In a downstream direction, headend906sends a digital signal over a digital medium, such as Ethernet or a passive optical network (PON), to node902. The digital signal is received as electrical signals at a remote physical device in node902. The remote physical device may be considered the node902or be part of node902and include the components shown. However, for discussion purposes, the term node902will be used. Node902converts the digital signal to an analog signal, such as a radio frequency (RF) signal.

Node902may also receive an analog signal from headend106over an analog medium. Node902may then combine the analog signal from the analog medium with the analog signal that was converted from the digital signal from the digital medium. Node902sends the combined analog signal (e.g., an RF signal) over an analog medium, such as a coaxial network, to CPE904.

In an upstream direction, CPE104may also transmit an analog signal to node902via the analog medium. The analog signal may include portions for transmission through both the digital medium and the analog medium to headend106. Node902then converts at least a portion of the analog signal to a digital signal and sends the digital signal to headend906through the digital medium. Additionally, node902sends at least a portion of the analog signal to headend906through the analog medium.

The processing of the analog signal and digital signal within node902will now be discussed in more detail. Different SFP modules may be used to receive and transmit digital and analog signals. An SFP module is a module that can be inserted into a slot in node902. Although small form pluggable modules are described, other types of modules that can be inserted into areas of node902may be used. A first SFP module is configured to receive and send a digital signal and a second SFP module is configured to receive, process, and send an analog signal. In some examples, an analog SFP module cannot receive, process, and send a digital signal, and a digital SFP module cannot receive and send an analog signal.

In the downstream direction, node902may receive an analog signal at an analog SFP receiver, such as an SFP-RF receiver (Rx)908. Node902may also receive a digital signal at a digital SFP transceiver, such as an SFP transceiver110. The digital SFP may be a regular SFP or enhanced SFP+ and may send digital signals both upstream and downstream. A regular digital SFP may support a first amount of gigabits (Gbits) per second of communication. An enhanced SFP (SFP+) may be an enhanced version of the SFP and may support data rates that are higher than the regular SFP, such as 16 Gbit/s. Although the enhanced version will be used for discussion purposes, other SFP types may also be appreciated.

The digital signal is processed by a field programmable gate array (FPGA)914that sends the digital signal to a digital to analog converter (DAC)916that converts the digital signal to an analog signal. The analog signal from SFP-RF Rx908and the digital signal from DAC916may be combined in a combiner920. The analog signal is overlaid with the digital signal in the combined analog signal output by combiner920. The combined signal may then be amplified by an amplifier924and transferred through a device928that can then output the analog signal to CPE904. Transfer device928can combine an upstream signal with downstream signal. For example, device928may be a diplexer filter that can multiplex signals from two ports to a single port, such as the upstream bandwidth is from 5 to 42 or 85 MHz, and downstream is from 54 or 108 MHz to 0.12 GHz. Also, device928may be a coupler that can couple either the upstream signal or the downstream signal in either direction.

In the upstream direction, CPE904may transmit an analog signal to node902. Transfer device928sends the analog signal to amplifier926for amplification. The analog signal is input into a splitter922. The analog signal includes a digital portion and an analog portion that may be split at splitter922. The analog portion is sent to an analog SFP transmitter, such as SFP-RF transmitter (Tx)912. SFP-RF Tx912then sends the analog signal to head end906.

For the digital portion of the upstream signal, an analog-to-digital converter (ADC)918receives the digital portion of the upstream signal and converts the analog signal to digital. FPGA914receives the digital signal and provides the digital signal to digital SFP910. SFP910can then send the digital signal to head end906.

Although the above network configuration is described, it will be understood that other network configurations may be used. Also, other components not shown in node902may also be used to process the analog and digital signals.

FIG.10depicts a more detailed example of node902according to some embodiments. Node902includes multiple slots202-1to202-3. Although three slots are shown, node902may have a different number of slots, such as 2 slots, 4 slots, 5 slots, etc. Slots1002-1to1002-3may be specifically configured to operate with a specific type of SFP module. In some examples, slot1002-1is configured to operate with SFP-RF Rx908; slot1002-2is configured to operate with digital SFP+910; and slot1002-3is configured to operate with SFP-RF Tx912. By operate, each slot when receiving the correct SFP module, can communicate data appropriately in the upstream and/or downstream directions. When a wrong SFP module is inserted into a slot1002, that module will not process and transmit signals in node902properly. For example, a digital SFP module that is inserted into an analog SFP module slot will not properly process and transmit the analog signal that is received at that slot. Although this configuration is described, other configurations of slots may be appreciated.

Each slot1002includes pin connectors1004in which pins from an SFP module can be coupled, such as inserted. Pin connectors may be individual connection points that can receive and connect to pins of SFP modules. In some examples, the pin layout dimensions for each slot1002-1to1002-3is similar or the same. The same may be using identical dimensions when designing the pin layout. The pin layout may be the same dimension-wise, such as the pin connectors are in the same position in the layout, such as in the same spacing arrangement. The connectors are the same in that they can fit both the analog SFP module and the digital SFP module. That is, the number of the pins and layout of the pins and spacing of the pins can receive either the pins of the analog SFP module or the digital SFP module. Further, the connectors may be configured to receive the same type of pins. That is, at least a portion of the pins may be configured to perform similar functions, such as both the analog SFP module and the digital SFP module have a power supply pin in the same position. The packaging of the analog SFP module or the digital SFP module may also look similar. That is, a design of both packages may use similar or the same specifications.

FIG.11depicts a more detailed example of node102according to some embodiments. A processor1102may configure FPGA914, DAC916, ADC918, transfer device928, and other components in node902based on different requirements. Some embodiments leverage processor1102to adjust a power supply voltage based on what type of SFP module is inserted into a slot. For example, processor1102is configured to communicate with an SFP module1112that has been inserted into a slot1002. Processor1102controls a power supply310that can output a first power supply voltage or a second power supply voltage, such as a 5.0V or 3.3V power supply voltage, based on which type of SFP module has been inserted into slot1002. The described process may be performed for each slot that is configured to receive an analog SFP module.

When SFP module1112is inserted into slot202, processor1102senses the insertion via a status line. For example, the status line may be a MOD ABS line that senses when a SFP module1112is inserted into a slot1002. In some examples, the status line is coupled to a pin connector #6, and SFP module1112sends a signal through the status line to a module sensor1108. The signal indicates to module sensor908that an SFP module has been inserted into slot1002.

Module sensor1108detects the insertion and causes a power supply controller1106to determine which power supply voltage to supply to SFP module1112. In some examples, power supply controller1106communicates through a bus, such as an I2C bus that is connected to a connector of slot1002and pin of SFP module1112. In some examples, the bus is connected to a pin #3 of SFP module1112. Through the communication, power supply controller1106may receive information regarding the type of SFP module1112along with other information. For example, SFP module1112may send information in an address space of the bus, which may be divided into lower and upper 128 bytes. SFP module1112may send the information in one part of the address space, such as the lower 128 bytes of the address space. The information may include the SFP type (e.g., whether the SFP module312is a digital SFP/SFP+ module or an analog SFP module). Other information may include the name of the SFP manufacturer and bias voltage, such as whether the SFP module1112requires a power supply voltage of 5V or 3.3V.

FIG.12depicts a simplified flowchart1200of a method for determining whether a module inserted into a slot1002is an analog SFP module or a digital SFP module according to some embodiments. At1202, processor1102receives a signal that a module is inserted into slot1002. At1204, processor1102receives a status signal for the SFP module. At1206, processor1102may review a portion of the address space in the status signal. For example, information needed to determine whether the SFP module is an analog SFP module or a digital SFP module may be included in a portion of the 256 bytes of the bus address space. Processor302can detect the bytes in a 128 bit address space and determine whether the SFP module is a digital SFP module or an analog SFP module. Also, processor1102may determine the bias voltage specified for the SFP module. Determining the bias voltage may allow processor1102to use a specified power supply voltage for the SFP module1112. For example, processor1102may dynamically configure the power supply voltage for different SFP modules to multiple values (e.g., more than two values). This may allow more flexibility for configuring the power supply voltage rather than having two power supply voltages for an analog SFP and a digital SFP module.

Referring back toFIG.11, power supply controller1106may send a power supply control message to power supply1110when power supply controller1106detects that SFP module1112is an analog SFP module. This is because by default, power supply1110may output a 3.3V power supply voltage (or some other voltage lower than 5V or 3.3V) to SFP module1112. In some embodiments, the power supply voltage may be output to pin 16 of SFP module1112, which may be the power supply pin for both the analog SFP module and the digital SFP module. Power supply controller1106can send a signal to power supply1110to increase the power supply voltage being output from 3.3V to 5.0V. Power supply1110can then receive the input 5.3V signal and then output the 5.0V signal instead of the 3.3V signal. Then, the analog SFP module then receives the proper power supply voltage for its specification.

If the SFP module1112was a digital SFP module, then power supply controller1106may not change the voltage output by power supply1110. Although 3.3V voltage may be used as the default voltage, power supply1110may output other voltages as the default voltage. For example, in other examples, the default voltage may be lower than 3.3V and power supply controller1106can increase the voltage to 3.3V upon determining that the digital SFP module has been inserted into slot1002. In all cases, when an analog SFP module is inserted into slot1002, power supply controller1106can increase the default voltage to 5.0V (or whatever the specified voltage is for the analog SFP module).

Accordingly, when a digital SFP module1112is inserted into a slot that is configured for an analog SFP module, the digital SFP module will not be damaged by a power supply voltage that is higher than the digital SFP module is configured to receive. However, when an analog SFP module is correctly inserted into a slot for an analog SFP, processor1102can increase the power supply voltage to the configured amount for the analog SFP. Digital SFPs that have the same packaging as analog SFPs, and may be mistakenly inserted into analog SFP slots, are thus not damaged. In some examples, analog SFPs will not be damaged if inserted into a digital SFP slot. Thus, processor1102may not have a process to detect and change any power supply voltage for the slots configured to receive digital SFPs.

FIG.13depicts a simplified flowchart1300of a method for managing power supply voltages for a slot1002according to some embodiments. As discussed above, the digital slots may not need to be managed as an analog SFP module that is inserted into a digital slot may not be damaged by the power supply voltage provided to that slot202. At1302, processor1102sets the power supply voltage output by power supply1110to a default voltage, such as 3.3V. Then, at1304, processor1102detects insertion of an SFP module1112in slot1002. The detection may be through a status line that is connected to a pin of SFP module1112.

At1306, processor1102determines whether or not the SFP module inserted into slot1002is an analog SFP. If not, then at1308, processor1102keeps the power supply voltage at 3.3V. For example, processor1102may not perform any actions to change the power supply voltage.

If processor1102detects that an analog SFP module was inserted into slot1002, at1310, processor1102sends a signal to power supply1110to increase the voltage to 5.0V. Then, power supply1110increases the voltage from 3.3 V to 5.0V, which is the configured voltage for an analog SFP module. The analog SFP module may then transmit or receive the analog signal as configured.

At1312, processor1102monitors for removal of the SFP module1112. At1314, processor1102determines if SFP module312was removed. When the SFP module1112was removed, at1316, processor1102changes the power supply voltage back to 3.3V. The changing of the power supply voltage back to 3.3V may be immediately performed to ensure that another SFP module1112that is inserted into slot1002may not be a digital SFP module, which can be damaged by the higher power supply voltage.

Accordingly, some embodiments provide protection for a slot1002that may receive SFP modules that may not be configured for the slot. Due to having digital SFP modules and analog SFP modules being manufactured having similar packaging and a similar pin layout, it is possible that a slot1002may have an SFP module inserted into it that is not configured to be inserted into that slot. Since the power supply pin for both modules is connected to the same connector, the higher voltage for the analog SFP module may damage the digital SFP module. Not damaging an erroneously inserted digital SFP module will save large replacement costs. Leveraging processor1102to control power supply1110in node902requires minimal cost because processor1102is being used to configure other components of node102, but the control of power supply1110saves a large cost when mistakes are made by inserting a wrong SFP module into a slot1002.

System

FIG.14illustrates an example of special purpose computer systems900configured with node102according to one embodiment. Computer system1400includes a bus1402, network interface1404, a computer processor1406, a memory1408, a storage device1410, and a display1412.

Bus1402may be a communication mechanism for communicating information. Computer processor906may execute computer programs stored in memory1408or storage device1408. Any suitable programming language can be used to implement the routines of some embodiments including C, C++, Java, assembly language, etc. Different programming techniques can be employed such as procedural or object oriented. The routines can execute on a single computer system1400or multiple computer systems1400. Further, multiple computer processors1406may be used.

Memory1408may store instructions, such as source code or binary code, for performing the techniques described above. Memory1408may also be used for storing variables or other intermediate information during execution of instructions to be executed by processor1406. Examples of memory1408include random access memory (RAM), read only memory (ROM), or both.

Storage device1410may also store instructions, such as source code or binary code, for performing the techniques described above. Storage device1410may additionally store data used and manipulated by computer processor1406. For example, storage device1410may be a database that is accessed by computer system900. Other examples of storage device1410include random access memory (RAM), read only memory (ROM), a hard drive, a magnetic disk, an optical disk, a CD-ROM, a DVD, a flash memory, a USB memory card, or any other medium from which a computer can read.

Memory1408or storage device1410may be an example of a non-transitory computer-readable storage medium for use by or in connection with computer system1400. The non-transitory computer-readable storage medium contains instructions for controlling a computer system1400to be configured to perform functions described by some embodiments. The instructions, when executed by one or more computer processors1406, may be configured to perform that which is described in some embodiments.

Computer system1400includes a display1412for displaying information to a computer user. Display1412may display a user interface used by a user to interact with computer system1400.

Computer system1400also includes a network interface1404to provide data communication connection over a network, such as a local area network (LAN) or wide area network (WAN). Wireless networks may also be used. In any such implementation, network interface1404sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

Computer system1400can send and receive information through network interface1404across a network1414, which may be an Intranet or the Internet. Computer system1400may interact with other computer systems1400through network1414. In some examples, client-server communications occur through network1414. Also, implementations of some embodiments may be distributed across computer systems1400through network1414.

Some embodiments may be implemented in a non-transitory computer-readable storage medium for use by or in connection with the instruction execution system, apparatus, system, or machine. The computer-readable storage medium contains instructions for controlling a computer system to perform a method described by some embodiments. The computer system may include one or more computing devices. The instructions, when executed by one or more computer processors, may be configured to perform that which is described in some embodiments.

EMBODIMENTS

Some embodiments may include detecting, by a computing device that includes the first slot and a second slot, a module that is inserted into the first slot of the computing device, wherein the first slot is configured to operate with a first type of module and the second slot is configured to operate with a second type of module, the first slot and the second slot including a same pin position for receiving a power supply pin from the first type of module and the second type of module; communicating, by the computing device, with the module to determine whether the module is the first type of module or the second type of module, the first type of module configured to receive a first type of signal that is combined with a second type of signal from the second type of module at the computing device; and adjusting, by the computing device, a power supply voltage to the power supply pin of the first slot from a first value to a second value when the first type of module is detected.

Some embodiments disclosed herein may also or instead include setting the power supply voltage to the first value before detecting the module being inserted into the first slot. In some embodiments the first value is a default value when no module is inserted into the first slot. Some embodiments may also or instead include detecting when the module is removed from the first slot of the computing device; and changing the power supply voltage from the second value to the first value. In some embodiments the first type of module and the second type of module have a same pin type arrangement. In some embodiments the first type of module and the second type of module have the same pin layout dimensions. In some embodiments the first slot and the second slot have a same pin type arrangement. In some embodiments the first type of module and the second type of module have a same packaging design.

In some embodiments the first type of module uses a higher power supply voltage than the second type of module. In some embodiments the first type of module uses a 5 volt power supply voltage and the second type of module uses a 3.3 volt power supply voltage. In some embodiments the first type of module is configured to receive an analog signal; and the second type of module is configured to receive a digital signal. Some embodiments may include wherein the computing device overlays the analog signal over an analog signal that is converted from the digital signal, and outputs the combined signal. Some embodiments may include wherein adjusting the power supply voltage comprises: outputting a signal to a power supply to adjust the power supply voltage to the second value.

Some embodiments may include wherein detecting the module is inserted comprises receiving a signal from a pin connected to the module indicating the module is inserted into the first slot. Some embodiments may include wherein communicating with the module comprises: receiving a signal from the module indicating a device type; and analyzing the signal to determine that the device type is the first type of module. Some embodiments may include wherein the first slot is not configured to operate with the second type of module and process the second type of signal.

Some embodiments may include a non-transitory computer-readable storage medium containing instructions that, when executed, control a computer system to be configured for detecting, in the computer system that includes a first slot and a second slot, a module that is inserted into the first slot of the computer system, wherein the first slot is configured to operate with a first type of module and the second slot is configured to operate with a second type of module, the first slot and the second slot including a same pin position for receiving a power supply pin from the first type of module and the second type of module; communicating with the module to determine whether the module is the first type of module or the second type of module, the first type of module configured to receive a first type of signal that is combined with a second type of signal from the second type of module at the computer system; and adjusting a power supply voltage to the power supply pin of the first slot from a first value to a second value when the first type of module is detected. Some embodiments may include the non-transitory computer-readable storage medium configured for setting the power supply voltage to the first value before detecting the module being inserted into the first slot. Some embodiments may include the non-transitory computer-readable storage medium further configured for detecting when the module is removed from the first slot of the computing device; and changing the power supply voltage from the second value to the first value.

Some embodiments may include an apparatus comprising: one or more computer processors; and a non-transitory computer-readable storage medium comprising instructions, that when executed, control the one or more computer processors to be configured for: detecting, in the apparatus that includes a first slot and a second slot, a module that is inserted into the first slot of the apparatus, wherein the first slot is configured to operate with a first type of module and the second slot is configured to operate with a second type of module, the first slot and the second slot including a same pin position for receiving a power supply pin from the first type of module and the second type of module; communicating with the module to determine whether the module is the first type of module or the second type of module, the first type of module configured to receive a first type of signal that is combined with a second type of signal from the second type of module at the apparatus; and adjusting a power supply voltage to the power supply pin of the first slot from a first value to a second value when the first type of module is detected. Some embodiments may include an apparatus capable of performing the method disclosed herein, including the disclosed features alone or in some combination.