CERAMIC SUBSTRATE UNIT AND MANUFACTURING METHOD THEREOF

The present invention relates to a ceramic substrate unit comprising: a ceramic substrate including a ceramic basic material and a circuit pattern formed on the ceramic basic material; an electrode pattern portion included in the circuit pattern on the ceramic substrate and connected to an electrode of a semiconductor chip mounted on the ceramic substrate; and a spacer bonded to the electrode pattern portion of the ceramic substrate by means of a bonding layer, wherein the spacer is made of a metal or alloy having electrical conductivity and thermal conductivity. According to the present invention, a power semiconductor chip can be mounted on a substrate in a form similar to flip-chip bonding, and thus the bonding strength of the bonding surface between a spacer and the substrate is increased to improve the reliability thereof.

TECHNICAL FIELD

The present disclosure relates to a ceramic substrate unit and a method of manufacturing the same, and more particularly, to a ceramic substrate unit which is applied to a power module and includes a spacer that plays a role as an electric track, and a method of manufacturing the same.

BACKGROUND ART

A power module is used to supply a high voltage and current for driving a motor for a hybrid vehicle, an electric vehicle, etc.

The power module has a structure in which a power semiconductor chip made of silicon carbide (SiC), gallium nitride (GaN), etc. is mounted on a substrate and a wire made of an Al or Cu material, that is, an electric track for power conversion, is bonded to the power semiconductor chip.

However, in the power module, the wire bonding structure has a danger of a short circuit or a disconnection due to electrical energy having high power and a high current, which is a risk factor for the entire vehicle and becomes a problem.

The contents described in the Background Art are to help the understanding of the background of the disclosure, and may include contents that are not a disclosed conventional technology.

DISCLOSURE

Technical Problem

An object of the present disclosure is to provide a ceramic substrate unit, which can omit wire bonding because the ceramic substrate unit includes a spacer that plays a role as an electric track in a substrate so that the spacer plays a role as a power movement track for an electrical signal and power conversion and allows a power semiconductor chip to be mounted on the substrate in a form similar to flip chip bonding, and a method of manufacturing the same.

Furthermore, an object of the present disclosure is to provide a ceramic substrate unit having improved reliability by increasing an adhesive force of a bonding surface between a spacer and a substrate, and a method of manufacturing the same.

Technical Solution

A ceramic substrate unit according to an embodiment of the present disclosure for achieving the object includes a ceramic substrate including a ceramic base and a circuit pattern formed on the ceramic base, electrode pattern parts included on the circuit pattern of the ceramic substrate and connected to electrodes of a semiconductor chip mounted on the ceramic substrate, and a spacer bonded to the electrode pattern part of the ceramic substrate via a bonding layer. The spacer is made of metal or an alloy having electrical conductivity and thermal conductivity.

The circuit pattern may be made of one of Cu, Al, AlSiC, CuMo, CuW, Cu/CuMo/Cu, Cu/Mo/Cu, Cu/W/Cu alloys or a composite material thereof.

The bonding layer may be made of Ag sintering paste or made of an alloy material including AgCu or AgCuTi.

The thickness of the bonding layer may be in a range of 5 μm to 100 μm.

The spacer may be made of Cu, CuMo, or a CPC material in which Cu, CuMo, and Cu have been sequentially stacked.

Each spacer bonded to the electrode pattern part is connected to each electrode of the semiconductor chip.

The spacers bonded to the electrode pattern parts are bonded to a source electrode, drain electrode, and gate electrode of the semiconductor chip, respectively, through soldering or sintering.

The ceramic substrate unit may further include a plurality of spacers bonded to the remaining parts except the electrode pattern parts in the circuit pattern via the bonding layer.

The plurality of spacers bonded to the remaining parts except the electrode pattern parts in the circuit pattern via the bonding layer have a height greater than the sum of heights of the spacer bonded to the electrode pattern part and the semiconductor chip.

A method of manufacturing a ceramic substrate unit includes a step of preparing a ceramic substrate including a ceramic base, at least one circuit pattern formed on the ceramic base, and electrode pattern parts to be connected to electrodes of a semiconductor chip, respectively, on the circuit pattern, a step of disposing a spacer on the electrode pattern parts of the ceramic substrate via a bonding layer, a step of inserting and pre-heating the ceramic substrate in which the spacer has been disposed into a heating furnace, and a step of main-bonding the spacer to the ceramic substrate by raising a temperature of the heating furnace after the pre-heating step.

In the step of preparing the ceramic substrate, the circuit pattern may be formed by brazing-bonding metal foil made of one of Cu, Al, AlSiC, CuMo, CuW, Cu/CuMo/Cu, Cu/Mo/Cu, Cu/W/Cu alloys or a composite material thereof to the ceramic base and then etching the metal foil.

In the step of preparing the ceramic substrate, the electrode pattern parts may be formed to include a source electrode pattern part, a drain electrode pattern part, and a gate electrode pattern part corresponding to a source electrode, drain electrode, and gate electrode of the semiconductor chip.

In the step of disposing the spacer, the spacer made of a CuMo material or a CPC material in which Cu, CuMo, and Cu have been sequentially stacked may be disposed in the source electrode pattern part and the drain electrode pattern part via a brazing bonding layer.

The brazing bonding layer may be made of an alloy material including AgCu or AgCuTi.

In the step of disposing the spacer, the spacer made of a Cu material is disposed in the gate electrode pattern part via an Ag sintering bonding layer.

The method may further include a step of disposing a plurality of spacers in remaining parts except the electrode pattern parts in the circuit pattern via the bonding layer. The plurality of spacers may be made of a CuMo material or a CPC material in which Cu, CuMo, and Cu have been sequentially stacked.

The step of inserting the ceramic substrate in which the spacer has been disposed into the heating furnace and pre-heating the heating furnace may be performed at 700° C. to 900° C. for 10 minutes to 30 minutes.

The step of main-bonding the spacer to the ceramic substrate by raising the temperature of the heating furnace after the pre-heating step may be performed for 1 hour to 3 hours by making the heating furnace have a reduction atmosphere and raising the temperature of the heating furnace to 860° C. to 950° C.

After the step of main-bonding the spacer to the ceramic substrate by raising the temperature of the heating furnace, a step of processing some spacers bonded to the ceramic substrate in a predetermined shape by etching the some spacers may be performed.

After the step of main-bonding the spacer to the ceramic substrate by raising the temperature of the heating furnace, a step of disposing the spacer made of a Cu material in at least one of the electrode pattern parts via an Ag sintering bonding layer and performing pre-heating and the main bonding may be further performed.

Advantageous Effects

In the present disclosure, one or more spacers are bonded to both sides or one side of the ceramic substrate through brazing bonding or Ag sintering bonding so that the spacer plays a role for an electrical signal and plays a role as a power movement track for power conversion. Accordingly, the present disclosure has effects in that wire bonding can be omitted, both multiple multi-quantity connections and heat dissipation effect of the semiconductor chip can be secured by applying the present disclosure to a power module, and performance of the power module can be further improved because the present disclosure also contributes to miniaturization.

Furthermore, the present disclosure has an effect in that reliability can be improved by increasing an adhesive force between the spacer and the substrate because the ceramic substrate and the spacer are bonded through brazing bonding and Ag sintering.

MODE FOR INVENTION

A ceramic substrate unit of the present disclosure is characterized in that one or more spacers are bonded to both sides or one side of a ceramic substrate so that the spacer plays a role for an electrical signal and plays a role as a power movement track for power conversion.

FIG.1is a bottom view illustrating a ceramic substrate unit according to a first embodiment of the present disclosure.FIG.2is a plan view illustrating the ceramic substrate unit according to the first embodiment of the present disclosure.FIG.3is a cross-sectional view of a-a inFIG.1.FIG.4is a cross-sectional view of b-b inFIG.1.FIG.5is a cross-sectional view of c-c inFIG.1.FIG.6is a cross-sectional view of d-d inFIG.1. For reference, in the cross sections ofFIGS.3to6, a relative thickness or length or a relative size has been exaggerated and shown, for convenience and clarity of a description.

As illustrated inFIGS.1and2, a ceramic substrate unit10according to the first embodiment of the present disclosure includes a ceramic substrate100and a spacer200bonded to both sides of the ceramic substrate100.

The ceramic substrate100may be any one of an active metal brazing (AMB) substrate, a direct bonding copper (DBC) substrate, a thick printing copper (TPC) substrate, and a DBA substrate. The AMB substrate or the BDC substrate is most suitable in terms of durability and heat dissipation efficiency.

For example, the ceramic substrate100includes a ceramic base110and at least one circuit pattern120,130formed on the ceramic base110. The ceramic base110may be any one of alumina (Al2O3), AlN, SiN, and Si3N4, for example.

The circuit pattern120,130may be formed on both sides of the ceramic base110. The both sides of the ceramic base110may mean an upper surface and lower surface of the ceramic base110. The circuit pattern120,130may be made of one of Cu, Al, AlSiC, CuMo, CuW, Cu/CuMo/Cu, Cu/Mo/Cu, Cu/W/Cu alloys or a composite material thereof. The circuit pattern120,130may be formed by brazing-bonding metal foil made of one of Cu, Al, AlSiC, CuMo, CuW, Cu/CuMo/Cu, Cu/Mo/Cu, Cu/W/Cu alloys or a composite material thereof to the ceramic base110and then etching the metal foil. The thickness of the ceramic base110may be 0.32 t, and the thickness of each circuit pattern120,130may be 0.3 t. If the circuit pattern120,130is formed on both sides of the ceramic base110, it is preferred that the thicknesses of the circuit patterns120,130are the same so that the circuit patterns are not deformed upon brazing.

The circuit pattern120,130may be formed to include an electrode pattern part to be connected to an electrode of a semiconductor chip500that is mounted on the ceramic substrate100.

Specifically, the circuit pattern120,130may be formed to include a source electrode pattern part S, a drain electrode pattern part D, and a gate electrode pattern part G. A source terminal of the semiconductor chip is connected to the source electrode pattern part S of the circuit pattern120,130. A drain terminal of the semiconductor chip is connected to the drain electrode pattern part D of the circuit pattern120,130. A gate terminal of the semiconductor chip is connected to the gate electrode pattern part G of the circuit pattern120,130. The semiconductor chip may be a semiconductor chip that functions as a high power switch and a high speed switch, and may be any one of a Si chip, a SiC chip, or a gallium nitride (GaN) chip, for example. The source terminal and drain terminal of the semiconductor chip are terminals that are responsible for the input and output of a high current, and the gate terminal thereof is a terminal that turns on and off the semiconductor chip by using a low voltage.

The spacer200is bonded to the electrode pattern part of the circuit pattern on the ceramic substrate100for each location in a plural number, and plays a role for an electrical signal or plays a role as a power movement track for power conversion. The spacer200is made of metal or an alloy material having electrical conductivity and thermal conductivity so that the spacer plays a role for an electrical signal or plays a role as a power movement track for power conversion.

The spacer200may be made of one of Cu, CuMo, and CPC materials, which have a low coefficient of thermal expansion and excellent electrical conductivity and thermal conductivity. The CPC material has a form in which Cu, CuMo, and Cu have been sequentially stacked. For example, the spacers210and220made of the CuMo material or the CPC material may be bonded to the source electrode pattern part S and the drain electrode pattern part D. The spacer230made of a Cu material may be bonded to the gate electrode pattern part G. The spacers210and220that are bonded to the source electrode pattern part S and the drain electrode pattern part D may be fabricated by machine processing because each spacer has a predetermined size. The spacer230that is bonded to the gate electrode pattern part G may be formed to have a desired size and shape by bonding the spacer having a predetermined size, which is fabricated by machine processing, to the gate electrode pattern part and then etching the spacer because the size of the spacer needs to be small. For example, the spacer230that is bonded to the gate electrode pattern part G may be formed in a quadrangle block shape or a square pyramid shape a cross-sectional area of which becomes smaller toward an upper part thereof.

Furthermore, the spacer200may be bonded to both sides of the ceramic substrate100for each location depending on its function. For example, some spacer240, among all of the spacers200, may be bonded to the circuit pattern120,130except the electrode pattern parts, and may perform the function of a heat dissipation electrode that isolates the ceramic substrate and another ceramic substrate that is disposed over or under the ceramic substrate and that electrically connects the circuit pattern120of the ceramic substrate100and a circuit pattern of another ceramic substrate.

Furthermore, some spacer250may be bonded to the circuit pattern120,130except the electrode pattern parts, and may perform a function for increasing heat dissipation efficiency by isolating the ceramic substrate100and another ceramic substrate (not illustrated) that is disposed over or under the ceramic substrate. For example, if the circuit pattern120of the ceramic substrate100on which a semiconductor chip is mounted is connected to a circuit pattern of another ceramic substrate that is disposed under the ceramic substrate100by the spacer250having thermal conductivity, heat that is generated from the semiconductor chip can be rapidly discharged, and a function for stably protecting the semiconductor chip that is disposed between the ceramic substrate100and the underlying another ceramic substrate can also be performed. The spacer240,250that is bonded to the ceramic substrate100and that isolates the ceramic substrate100and another ceramic substrate100disposed over or under the ceramic substrate is preferably made of the CuMo material or the CPC material, and may be bonded to the ceramic substrate100after the spacer is fabricated by machine processing because the spacer has a predetermined size.

Specifically, some spacers210,220, and230are bonded to the drain electrode pattern part D, source electrode pattern part S, and gate electrode pattern part G of the ceramic substrate100, respectively, so that the semiconductor chip is mounted on the ceramic substrate100in a form similar to a flip chip. When the semiconductor chip is bonded to the ceramic substrate100by using the spacers210,220, and230, an electrical loss and load attributable to resistance on a power transfer path can be improved because a power transfer path is reduced. Furthermore, the spacers210,220, and230may play a role for an electrical signal and play a role as a power movement track for power conversion instead of conventional wire bonding. If wire bonding is omitted, there is an effect in that heat dissipation performance is improved because an inductance value can be reduced to the maximum.

Furthermore, some spacers240and250are bonded to the circuit pattern120except the electrode pattern parts of the ceramic substrate100, and can improve electrical characteristics by preventing an electrical loss and short because the spacers can electrically connect the circuit pattern120of the ceramic substrate100and a circuit pattern of another ceramic substrate. Furthermore, the spacer240,250that electrically connects the circuit pattern120of the ceramic substrate100and a circuit pattern of another ceramic substrate can improve an electrical loss and load attributable to resistance on a power transfer path because a power transfer path is reduced.

Referring toFIG.1, the spacers210,220, and230are bonded to the drain electrode pattern part D, the source electrode pattern part S, and the gate electrode pattern part G, respectively, on the lower surface of the ceramic substrate100. Multiple spacers240and250are bonded to the remaining parts of the circuit pattern120except the electrode pattern parts at predetermined intervals in order to increase isolation from another ceramic substrate100, a power movement, and heat dissipation efficiency.

The spacers210,220, and230may be bonded to the electrode pattern parts to be connected to electrodes of the semiconductor chip (reference numeral500inFIG.7) in the circuit pattern120. The spacers210,220, and230that are bonded to the electrode pattern parts are connected to the electrodes of the semiconductor chip, respectively, and may each play a role as a high current power movement track for power conversion or play a role for an electrical signal.

Referring toFIG.2, multiple spacers260and270may be bonded to the upper surface of the ceramic substrate100at predetermined intervals in order to isolate the ceramic substrate from another ceramic substrate100at the part of the circuit pattern130and to increase heat dissipation efficiency.

As illustrated inFIG.3, the spacer210that is bonded to the drain electrode pattern part D may be made of the CuMo material or may be made of the CPC material in which Cu, CuMo, and Cu have been sequentially stacked.

In an embodiment, the spacer200that is bonded to the ceramic substrate100is bonded to the circuit pattern120of the ceramic substrate100via a bonding layer310,320. The bonding layer300may be a brazing bonding layer310or an Ag sintering bonding layer320. The spacer210is bonded to the drain electrode pattern part D illustrated inFIG.3via the brazing bonding layer310.

The brazing bonding layer310may be made of an alloy material including AgCu or AgCuTi. The thickness of the brazing bonding layer310may be in the range of 5 μm to 100 μm. The thickness of the brazing bonding layer310is small to the extent that the thickness does not affect the height of the spacer210, and bonding strength thereof is great.

Furthermore, the spacer220that is bonded to the source electrode pattern part S ofFIG.1may be made of the CuMo material or the CPC material in which Cu, CuMo, and Cu have been sequentially stacked. Furthermore, the spacer220is bonded to the source electrode pattern part S via the brazing bonding layer310.

As illustrated inFIG.4, the spacer230that is bonded to the gate electrode part G may be made of the Cu material. Furthermore, the spacer230may be bonded to the gate electrode part G via the Ag sintering bonding layer320. The Ag sintering bonding layer320includes Ag nano particle powder, and has high bonding density and high thermal conductivity.

The Ag sintering bonding layer320having high bonding density is applied to the gate electrode part G that is difficult to be bonded because the gate electrode part has a small size in order to increase bonding strength between the circuit pattern120and the spacer200. Furthermore, Cu which can be relatively easily processed is applied to the spacer230of the gate electrode part G in order to increase the precision of the size so that the spacer plays a reliable role for an electrical signal. Particularly, the Ag sintering bonding layer320improves efficiency by reducing an electrical loss of an electrical signal connection part.

The spacers240,250,260, and270illustrated inFIGS.1and2are bonded to the remaining parts except the electrode pattern parts in the circuit pattern120,130. The spacers240,250,260, and270that are bonded to the remaining parts except the electrode pattern parts in the circuit pattern120,130are disposed at predetermined intervals in a plural number, and may each perform a heat dissipation function between a substrate and a substrate or play a role for an electrical signal.

As illustrated inFIG.5, the spacer240,260is bonded to the circuit pattern120,130, and may perform a function for electrifying the upper circuit pattern120and the lower electrode pattern130by connecting the upper circuit pattern120and the lower electrode pattern130in the drawing and for conducting a high current and distributing a high current. To this end, a via hole410is formed in the ceramic substrate100. The upper circuit pattern120, the lower electrode pattern130, and the spacer200may be electrically connected through the via hole410. The via hole410may be filled with a conductive material, and may be filled with an Ag alloy, for example.

The spacer240,260may be made of the CuMo material or may be made of the CPC material in which Cu, CuMo, and Cu have been sequentially stacked. The spacer240,260may be bonded to the circuit pattern120,130of the ceramic substrate100via the brazing bonding layer310that is made of an alloy material including AgCu or AgCuTi.

As illustrated inFIG.6, the spacer250,270is bonded to the circuit pattern120,130, and may perform a function of a heat dissipation electrode that isolates the ceramic substrate100and another ceramic substrate (not illustrated) that is disposed over or under the ceramic substrate in the drawing and that electrically connects the circuit pattern120,130of the ceramic substrate100and a circuit pattern of another ceramic substrate.

The spacer250,270may be made of the CuMo material or may be made of the CPC material in which Cu, CuMo, and Cu have been sequentially stacked. The spacer250,270may be bonded to the circuit pattern120,130of the ceramic substrate100via the brazing bonding layer310that is made of an alloy material including AgCu or AgCuTi.

The spacers240,250,260, and270illustrated inFIGS.5and6are bonded to the remaining parts except the electrode pattern parts in the circuit pattern120,130via the brazing bonding layer310, and each perform heat dissipation and support functions between two substrates. Accordingly, each spacer has a height greater than the sum of the heights of the spacers210,220, and230bonded to the electrode pattern parts and the semiconductor chip500.

FIG.7is a diagram illustrating a form in which the semiconductor chip has been attached to the ceramic substrate unit according to the first embodiment of the present disclosure.FIG.8is a cross-sectional view of e-e inFIG.7. In the cross section ofFIG.8, a relative thickness or length or a relative size has been exaggerated and shown, for convenience and clarity of a description.

As illustrated inFIGS.7and8, the drain electrode, source electrode, and gate electrode of the semiconductor chip500may be bonded to the drain electrode pattern part D, source electrode pattern part S, and gate electrode pattern part G of the ceramic substrate100, respectively. A bonding layer610that bonds the drain electrode, source electrode, and gate electrode of the semiconductor chip500to the drain electrode pattern part D, source electrode pattern part S, and gate electrode pattern part G of the ceramic substrate100, respectively, may be a solder or Ag sintering paste. SnAg, SnAgCu, etc., which have high bonding strength and excellent high-temperature reliability, may be used for soldering bonding through the solder. Ag sintering paste including Ag nano powder having high bonding density and high thermal conductivity may be used for Ag sintering using the Ag sintering paste.

A structure in which the semiconductor chip500is bonded to the ceramic substrate100through the spacers210,220, and230bonded to the ceramic substrate100can improve an electrical loss and load because the semiconductor chip500is mounted on the ceramic substrate100in a form similar to a flip chip and increase operation reliability by enabling the stable mounting of the semiconductor chip500.

In an embodiment, one or more semiconductor chips500may be mounted on the ceramic substrate100. The spacer200may be bonded to the ceramic substrate100by considering the number and locations of the drain electrode, source electrode, and gate electrode of the semiconductor chip500.

FIG.9is a flowchart illustrating a method of manufacturing a ceramic substrate unit according to a first embodiment of the present disclosure.FIG.10is a construction diagram illustrating the method of manufacturing a ceramic substrate unit according to the first embodiment of the present disclosure.

As illustrated inFIGS.9and10, the method of manufacturing a ceramic substrate unit according to the first embodiment of the present disclosure includes step S10of preparing the ceramic substrate100including the ceramic base110, at least one circuit pattern120,130formed on the ceramic base110, and electrode pattern parts to be connected to electrodes of the semiconductor chip500, respectively, on the circuit pattern120,130, step S20of disposing the spacers200on the electrode pattern parts of the ceramic substrate100via the bonding layer300, step S30of inserting and pre-heating the ceramic substrate100in which the spacers200have been disposed into a heating furnace, and step S40of main-bonding the spacers200to the ceramic substrate100by raising the temperature of the heating furnace after the pre-heating step.

In step S10of preparing the ceramic substrate100, the circuit pattern120,130may be formed by brazing-bonding metal foil made of one of Cu, Al, AlSiC, CuMo, CuW, Cu/CuMo/Cu, Cu/Mo/Cu, Cu/W/Cu alloys or a composite material thereof to the ceramic base110and then etching the metal foil.

In step S10of preparing the ceramic substrate100, the circuit pattern120,130may be formed to include a source electrode pattern part, a drain electrode pattern part, and a gate electrode pattern part corresponding to the source electrode, drain electrode, and gate electrode of the semiconductor chip500.

In step S20of disposing the spacer200in the electrode pattern parts of the ceramic substrate100via the bonding layer300, the spacer made of the CuMo material or the CPC material in which Cu, CuMo, and Cu have been sequentially stacked may be disposed in the source electrode pattern part and the drain electrode pattern part via a brazing bonding layer. The brazing bonding layer may be made of an alloy material including AgCu or AgCuTi.

In step S20of disposing the spacer200in the electrode pattern parts of the ceramic substrate100via the bonding layer300, the spacer made of the Cu material may be disposed in the gate electrode pattern part via the Ag sintering bonding layer. The Ag sintering bonding layer includes Ag nano powder. The Ag nano powder may be sintered in the brazing process, and can firmly bond the spacer200to the circuit pattern of the ceramic substrate100.

In step S20of disposing the spacer200in the electrode pattern parts of the ceramic substrate100via the bonding layer300, the brazing bonding layer310of the bonding layer300may be attached on one side of the spacer200through a transcription method and then temporarily attached to the circuit pattern120of the ceramic substrate100via the adhesive layer315.

Alternatively, the brazing bonding layer310of the bonding layer300may be formed by forming the brazing bonding layer on the circuit pattern120,130of the ceramic substrate100through sputtering and a plating method and then etching the brazing bonding layer. The spacer200may be temporarily attached to the bonding layer300formed on the circuit pattern120,130of the ceramic substrate100via the adhesive layer315.

Alternatively, the Ag sintering bonding layer320of the bonding layer300may be attached to one side of the spacer200through a method, such as transcription, application, or coating and then temporarily attached to the circuit pattern120of the ceramic substrate100via the adhesive layer315.

Step S30of inserting and pre-heating the ceramic substrate100in which the spacer200has been disposed into a heating furnace may be performed at 700° C. to 900° C. for 10 minutes to 30 minutes while passing the ceramic substrate100in which the spacer200has been disposed through a continuous furnace (heating furnace). The pre-heating step S30is for removing thermal stress and thermal deformation of the ceramic substrate100. The pre-heating step S30is for preventing a crack in or the bending of the ceramic substrate100by preventing a sudden thermal shock along with overall crack heating.

In the pre-heating step S30, when a pre-heating temperature is lower than the range, a pre-heating effect is not present. When the pre-heating temperature is higher than the range, it is difficult to remove thermal stress and thermal deformation. In the pre-heating step S30, a preferred pre-heating condition includes about 15 minutes to 20 minutes at 760° C. to 800° C.

Step S40of main-bonding the spacer200to the ceramic substrate100by raising the temperature of the heating furnace after the pre-heating step may be performed for 1 hour to 3 hours by making the atmosphere of the heating furnace have a reduction atmosphere and raising the temperature of the heating furnace to 860° C. to 950° C. In order to make the atmosphere of the heating furnace the reduction atmosphere, nitrogen may be injected into the heating furnace.

More preferably, after the ceramic substrate100to which the spacer200has been temporarily bonded is pre-heated, the spacer200is brazing-bonded to the ceramic substrate100while the ceramic substrate passes through a continuous furnace (the heating furnace) having a reduction atmosphere. The brazing bonding is performed on the ceramic substrate100to which the spacer200has been temporarily bonded in the continuous furnace having the reduction atmosphere, in a temperature range of 860° C. to 950° C. for 1 hour to 3 hours. In this case, both brazing bonding and cooling may be performed on the ceramic substrate100to which the spacer200has been temporarily bonded in a process of the ceramic substrate passing through the continuous furnace.

It is not preferred that in the main-bonding step S40, a main-bonding temperature is lower than the range because bonding strength is low and the main-bonding temperature is higher than the range because a crack, bending, etc. may occur in the ceramic substrate100. In the main-bonding step S40, a preferred main-bonding condition includes about 1 hour 30 minutes to 2 hours 10 minutes at 900° C. to 950° C.

The spacer200that has been temporarily bonded to the circuit pattern120,130of the ceramic substrate100via the brazing bonding layer310in the main-bonding process is bonded to the ceramic substrate100through brazing bonding. The spacer200that has been temporarily bonded to the circuit pattern120,130of the ceramic substrate100via the Ag sintering bonding layer320is bonded through Ag sintering. Alternatively, the adhesive layer315that temporarily bonds the spacer200to the ceramic substrate100becomes volatile and is removed in the brazing bonding process.

Alternatively, after one brazing bonding process of bonding the spacer200to the circuit pattern120,130of the ceramic substrate100via the brazing bonding layer310, the spacer200may be bonded to the circuit pattern120,130of the ceramic substrate100via the Ag sintering bonding layer320.

For example, after step S40of main-bonding the spacer to the circuit pattern of the ceramic substrate, a step of disposing one or more spacers230on the circuit pattern of the ceramic substrate100via the Ag sintering bonding layer (reference numeral320inFIG.4may be additionally performed. In the step of additionally performing the step of disposing the one or more spacers230on the circuit pattern120of the ceramic substrate100via the Ag sintering bonding layer320, a second brazing bonding process of disposing the spacer230made of the Cu material in the gate electrode pattern part G via the Ag sintering bonding layer320and additionally performing a pre-heating and main bonding process may be performed.

If the second brazing bonding process is performed, a void defect that occurs in a bonding surface of the spacer200and the ceramic substrate100in the first brazing bonding process may be removed. Furthermore, bonding strength between the ceramic substrate100and the spacer230may be increased by more accurately controlling a bonding temperature of the Ag sintering bonding layer320.

After the step S40of main-bonding the spacers200to the circuit pattern120,130of the ceramic substrate100by raising the temperature of the heating furnace, a step of processing some of the spacers200bonded to the ceramic substrate100in a predetermined shape by etching some of the spacers may be performed. For example, the spacer (reference numeral230inFIG.4) bonded to the gate electrode pattern part G may be made in a small shape by etching the spacer.

The ceramic substrate unit10that is manufactured by the method is bonded to both sides of the ceramic substrate100in a plural number for each location, and may play a role for an electrical signal and play a role as a power movement track for power conversion instead of wire bonding.

An example in which the spacer200is bonded to both sides of the ceramic substrate100for each location has been described, but the spacer may be bonded to only one side of the ceramic substrate100for each location.

Furthermore, the spacer200may be bonded to one side of the ceramic substrate100for each location, and may play a role for an electrical signal only.

FIG.11Ais a plan view of a ceramic substrate unit in which spacers have been bonded to a cross section of a ceramic substrate as a second embodiment of the present disclosure.FIG.11Bis a bottom view of the ceramic substrate unit in which spacers have been bonded to a cross section of the ceramic substrate as the second embodiment of the present disclosure.FIG.11Cis a front view of the ceramic substrate unit in which spacers have been bonded to a cross section of the ceramic substrate as the second embodiment of the present disclosure.

As illustrated inFIG.11A to11C, in a ceramic substrate unit10-1of the second embodiment, a plurality of spacers200′ may be bonded to one side of the ceramic substrate100at predetermined intervals. The spacer200′ may be bonded to a circuit pattern120′ of the ceramic substrate100via the brazing bonding layer or the Ag sintering bonding layer depending on its use. For example, the spacer200′ may be bonded to one side of the ceramic substrate100in a plural number at predetermined intervals, and may perform a function of a heat dissipation electrode that isolates the ceramic substrate100from another ceramic substrate that is disposed over and under the ceramic substrate100and electrically connects the circuit pattern120′ of the ceramic substrate100and a circuit pattern of another ceramic substrate.

In the first embodiment, an example in which the spacers are bonded to the drain electrode pattern part, source electrode pattern part, and gate electrode pattern part of the ceramic substrate100, respectively, and the semiconductor chip may be mounted has been described. In the second embodiment, an example in which the spacers200′ are bonded to only one side of the ceramic substrate100and each perform a heat dissipation function or play a role for an electrical signal has been described. However, in order to design a structure not having wire bonding, the spacer having various forms, such as a quadrangle block shape and a cylindrical shape, and various size may be bonded to the ceramic substrate for each location.

The present disclosure can improve reliability by increasing an adhesive force of a bonding surface because the spacer is bonded to one side or both sides of the ceramic substrate through brazing bonding or Ag sintering, can have an excellent heat dissipation characteristic because the spacer is made of a material having excellent thermal conductivity, and can stably play a role for an electrical signal and play a role as a power movement track for power conversion because the spacer has electrical conductivity. Furthermore, the present disclosure can remove an electrical risk factor in wire bonding because wire bonding is omitted, can simultaneously convert a rating voltage and current, and can improve reliability and efficiency of a part that is used in high power, particularly.

Furthermore, the ceramic substrate unit of the present disclosure can secure both multiple multi-quantity connections and a heat dissipation effect of a semiconductor chip by being applied to a power module, and can further improve performance of the power module because the ceramic substrate unit also contributes to miniaturization.

The ceramic substrate of the present disclosure may be applied to various module parts which are used in high power, in addition to a power module.

The above description is merely a description of the technical spirit of the present disclosure, and those skilled in the art may change and modify the present disclosure in various ways without departing from the essential characteristic of the present disclosure. Accordingly, the embodiments described in the present disclosure should not be construed as limiting the technical spirit of the present disclosure, but should be construed as describing the technical spirit of the present disclosure. The technical spirit of the present disclosure is not restricted by the embodiments. The range of protection of the present disclosure should be construed based on the following claims, and all of technical spirits within an equivalent range of the present disclosure should be construed as being included in the scope of rights of the present disclosure.