SEMICONDUCTOR APPARATUS

A first conductive pattern includes a first input region overlapping a first semiconductor device and a second input region overlapping a second semiconductor device. An output electrode of the first semiconductor device and an output electrode of the second semiconductor device are connected with each other by a first wiring member. The output electrode of the second semiconductor device and a second conductive pattern are connected with each other by a second wiring member. A ratio of a current flowing from the second input region to the second conductive pattern via the second semiconductor device, relative to a current flowing from the first input region to the second conductive pattern via the first semiconductor device, is equal to or greater than 0.90 and equal to or less than 1.10.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a semiconductor apparatus.

Description of Related Art

In related art, a technique has been developed in which in order to reduce a size and to obtain a large current in a semiconductor apparatus, semiconductor devices are arranged on a conductive pattern with a high area efficiency. For example, WO 2019/044748 discloses an arrangement in which a conductive pattern on an insulation substrate and semiconductor devices are aligned in one direction. In the semiconductor device, a first main electrode is formed on a back surface opposed to the insulation substrate, and a second main electrode is formed on a front surface. The second main electrodes of the semiconductor devices are connected together by stitch bonding of wires. The second main electrodes of the semiconductor devices and the conductive pattern are connected together by further stitch bonding of wires, which connect the second main electrodes of the semiconductor devices together, to the conductive pattern.

In the above-described related art, because wires which connect second main electrodes with a conductive pattern do not have to be individually provided for semiconductor devices, a mountable area of the semiconductor devices becomes large, and a large capacity of a semiconductor apparatus is realized. On the other hand, a resistance value in a path from the second main electrode of each of the semiconductor devices to the conductive pattern becomes non-uniform, and a current which flows through each of the semiconductor devices becomes non-uniform. Accordingly, a temperature of a wire joining portion becomes relatively high in the semiconductor device in which the current is relatively large, a power cycle tolerance (the number of destruction cycles by repetition of turning ON and OFF of a predetermined current), a short-circuit tolerance, an I2t tolerance, and so forth, of the semiconductor device are reduced. As a result, there is a possibility that long-term reliability of the semiconductor apparatus cannot be maintained.

SUMMARY

To solve the above problems, a semiconductor apparatus of the present disclosure includes: a conductive pattern having a first conductive pattern and a second conductive pattern; and a first semiconductor device and a second semiconductor device each arranged on the first conductive pattern, the first conductive pattern includes a first input region overlapping the first semiconductor device and a second input region overlapping the second semiconductor device, each of the first semiconductor device and the second semiconductor device includes: a first main electrode that is provided on a first main surface opposed to the first conductive pattern and is electrically connected with the first conductive pattern; and a second main electrode that is provided on a second main surface on an opposite side to the first main surface, the second main electrode of the first semiconductor device and the second main electrode of the second semiconductor device are connected to each other by a first wiring member formed with a wire or a ribbon cable, the second main electrode of the second semiconductor device and the second conductive pattern are connected with each other by a second wiring member formed with a wire or a ribbon cable, and a ratio (i2/i1) of a current (i2) flowing from the second input region to the second conductive pattern via the second semiconductor device, relative to a current (i1) flowing from the first input region to the second conductive pattern via the first semiconductor device, is equal to or greater than 0.90 and equal to or less than 1.10.

Furthermore, a semiconductor apparatus of the present disclosure includes: a conductive pattern having a first conductive pattern and a second conductive pattern; and a first semiconductor device and a second semiconductor device each arranged on the first conductive pattern, the first conductive pattern includes a first input region overlapping the first semiconductor device and a second input region overlapping the second semiconductor device, each of the first semiconductor device and the second semiconductor device includes: a first main electrode that is provided on a first main surface opposed to the first conductive pattern and is electrically connected with the first conductive pattern; and a second main electrode that is provided on a second main surface on an opposite side to the first main surface, the second main electrode of the first semiconductor device and the second main electrode of the second semiconductor device are connected with each other by a first wiring member formed with a wire or a ribbon cable, the second main electrode of the second semiconductor device and the second conductive pattern are connected with each other by a second wiring member formed with the wire or the ribbon cable, and a ratio (R1/R2) of a resistance (R1) of a first path relative to a resistance (R2) of a second path is equal to or greater than 0.90 and equal to or less than 1.10, the first path starting from the first input region and reaching a connection point between the second main electrode of the second semiconductor device and the second wiring member while passing through the first semiconductor device and the first wiring member, and the second path starting from the second input region and reaching the connection point between the second main electrode of the second semiconductor device and the second wiring member while passing through the second semiconductor device.

DESCRIPTION OF THE EMBODIMENTS

In the following, an embodiment according to the present disclosure will be described with reference to the drawings. It is to be noted that in the drawings, dimensions and scale of each part are appropriately different from actual dimensions and scale. Furthermore, the embodiment described in the following is a preferable specific example of the present disclosure. Thus, various limitations which are technically preferable are applied to the following embodiment. However, the scope of the present disclosure is not limited by these forms unless descriptions to limit the present disclosure are particularly given in the following description.

FIG.1is a plan view of a semiconductor apparatus10according to the embodiment. The semiconductor apparatus10has a heat dissipation substrate11and semiconductor units20ato20fthat are electrically connected together by bonding wires12ato12e. The heat dissipation substrate11is made of, for example, aluminum, iron, silver, or copper, which have excellent thermal conductivity, or an alloy including at least one of these. Furthermore, in order to improve corrosion resistance, a surface of the heat dissipation substrate11may be plated or the like, with a material, such as nickel. As the material to be used for the plating or the like, a nickel-phosphorus alloy, a nickel-boron alloy, or the like may be used instead of nickel. In the heat dissipation substrate11, attachment holes used for attachment to an external apparatus, contact regions for inputting and outputting a current to and from the semiconductor units20ato20f, and so forth, are appropriately formed.

The semiconductor units20ato20fare arranged in one line on a front surface of the heat dissipation substrate11via solder, silver solder, or the like. Semiconductor devices (for example, semiconductor devices25to28which will be described later) are arranged on each of the semiconductor units20ato20f, and the semiconductor units20ato20frealize needed functions. It is to be noted that the number of semiconductor units20ato20fwhich is indicated inFIG.1is one example, but a necessary number of semiconductor units can be installed. Furthermore, in the following, the semiconductor units20ato20fwill be referred to as a semiconductor unit in general, and details thereof will be described later. It is to be noted that the bonding wires12ato12eare formed of metal such as aluminum or copper, which has excellent electrical conductivity, an alloy including at least one type of these, or the like.

Next, a configuration of the semiconductor unit20will be described with reference toFIG.2toFIG.4.FIG.2is a plan view of the semiconductor unit20according to the embodiment, andFIG.3is a cross-sectional view of the semiconductor unit20according to the embodiment.

It is to be noted thatFIG.3illustrates a cross section taken along a one-dot chain line C-C inFIG.2. However,FIG.3does not illustrate bonding wires29. Furthermore,FIG.4is a circuit diagram of a circuit configured with the semiconductor unit20according to the embodiment.

In the present embodiment, the semiconductor unit20has a rectangular shape in plan view. More specifically, an insulation substrate22that constitutes the semiconductor unit20presents a rectangular shape with a pair of long sides opposed to each other and a pair of short sides opposed to each other in plan view, and the other components of the semiconductor unit20are arranged on the main surfaces (front surface and back surface) of the insulation substrate22. In the present embodiment, an X axis is placed along the short side of the semiconductor unit20in plan view, and a Y axis is placed along the long side. The Y axis is one example of a first axis. It is to be noted that in the present embodiment, a plan view has the same meaning as viewing a target object in a vertical direction to the front surface of the insulation substrate22.

The semiconductor unit20includes a first arm portion (upper arm portion) A and a second arm portion (lower arm portion) B, and upper and lower arm portions are formed. As illustrated inFIG.4, an external connection terminal P (input P) that is connected with a positive electrode of an external power source (not illustrated) is connected with the first arm portion A, and the first arm portion A constitutes a circuit that supplies a current from the positive electrode (high potential terminal) of the external power source to a load. It is to be noted that the load is connected with an external connection terminal U (output U). An external connection terminal N (input N) that is connected with a negative electrode of the external power source is connected with the second arm portion B, and the second arm portion B constitutes a circuit that draws a current from the load to the negative electrode (low potential terminal) of the external power source. As illustrated inFIG.2andFIG.3, the semiconductor unit20has a circuit substrate21, and the semiconductor devices25to28which are provided on a front surface of the circuit substrate21. The semiconductor devices26and27each are an example of a “first semiconductor device”, and the semiconductor devices25and28each are an example of a “second semiconductor device”. A back surface of the circuit substrate21is joined to the heat dissipation substrate11via solder, silver solder, or the like (not illustrated), and the semiconductor unit20is thereby arranged on the heat dissipation substrate11(seeFIG.1).

In the present embodiment, each of the semiconductor devices25to28includes silicon or silicon carbide and is a switching element of an RC-IGBT (reverse conducting insulated gate bipolar transistor) that includes an IGBT (insulated gate bipolar transistor) and an FWD (freewheeling diode) that are configured in one chip. An RC-IGBT has a circuit in which an IGBT and an FWD are connected together anti-parallel.

In the present embodiment, each of the semiconductor devices25to28has a rectangular shape in plan view. More specifically, when viewed in plan view, each of front surface and back surface of each of the semiconductor devices25to28presents a rectangular shape with a pair of long sides opposed to each other and a pair of short sides opposed to each other. Each of the semiconductor devices25to28is arranged such that its long sides extend along the X axis and its short sides extend along the Y axis.

For example, the semiconductor devices25to28each include an input electrode (collector electrodes, for example, an input electrode25dof the semiconductor device25and an input electrode26dof the semiconductor device26are illustrated inFIG.3) as a first main electrode on the back surface (first main surface). Furthermore, the semiconductor devices25to28include, on the respective front surface (second main surface), control electrodes, i.e., gate electrodes25ato28a, respectively, and output electrodes, i.e., emitter electrodes25bto28b, respectively. An output electrode is a second main electrode. The gate electrodes25ato28aeach are positioned adjacent to one of the long sides of the front surface of the corresponding semiconductor device25to28and around the center of the long side. Furthermore, the output electrodes25bto28beach are formed in a portion other than the corresponding gate electrode25ato28aof the front surface of the corresponding semiconductor device25to28. Furthermore, gate runners25cto28care each provided on the front surface of the corresponding semiconductor device25to28. The gate runners25cto28care electrically connected with the gate electrodes25ato28a, respectively. The gate runners25cto28care provided to transmit a gate control signal supplied to the corresponding gate electrode25ato28athroughout the corresponding semiconductor device25to28without delay. In the present embodiment, the gate runners25cto28ceach are arranged in parallel with the long sides of the corresponding semiconductor device25to28around the center of the short sides of the corresponding semiconductor device25to28.

The circuit substrate21has the insulation substrate22, and a metal plate23that is joined to the back surface of the insulation substrate22. The insulation substrate22is formed of ceramic with high thermal conductivity, such as aluminum oxide, aluminum nitride, or silicon nitride, which has excellent thermal conductivity. The metal plate23is formed of metal having excellent thermal conductivity, such as aluminum, iron, silver, copper or an alloy including at least one of these. In addition, the circuit substrate21has conductive patterns24ato24e, each of which is formed on the front surface of the insulation substrate22. The conductive patterns24ato24eare formed of metal such as copper or a copper alloy, which has excellent electrical conductivity. In order to improve corrosion resistance, for example, a plating using a material such as nickel may be applied to surfaces of the conductive patterns24ato24e. As the material other than nickel to be used for plating or the like, a nickel-phosphorus alloy, a nickel-boron alloy, or the like may be used. Furthermore, a thickness of each of the conductive patterns24ato24eis equal to or greater than 0.1 mm and equal to or less than 1 mm, for example. As the circuit substrate21having such a configuration, for example, a DCB (direct copper bonding) substrate or an AMB (active metal brazed) substrate can be used. The circuit substrate21can transmit heat produced in the semiconductor devices25to28to the heat dissipation substrate11via the conductive patterns24aand24c, the insulation substrate22, and the metal plate23. It is to be noted that the circuit substrate21may be a metal-based substrate or a lead frame in which a die pad is formed, for example.

The conductive pattern24acomprises a collector pattern of the first arm portion A. The conductive pattern24ais one example of a “first conductive pattern” in the first arm portion A. The collector pattern is a conductive pattern with which the input electrodes (collector electrodes) of the semiconductor devices (the semiconductor devices25and26in the first arm portion A) are connected. The conductive pattern24aforms a generally rectangular shape, and a portion including a contact region24a1protrudes on a lower side inFIG.2. As illustrated inFIG.4and so forth, the external connection terminal P to be connected with the positive electrode of the external power source is connected with the contact region24a1. On the conductive pattern24a, the semiconductor devices25and26are arranged at an interval along the Y axis. More specifically, each of the semiconductor devices25and26has a first long side and a second long side. The first long side of the semiconductor device25is arranged to be adjacent to the gate electrodes25aand is arranged to be adjacent to a connection region24b1of the conductive pattern24b, which will be described later. The first long side of the semiconductor device26is arranged to be adjacent to the gate electrode26aand is arranged to be adjacent to the connection region24b1. The second long side of the semiconductor device25is arranged in a position spaced away from the gate electrode25aand is arranged to be adjacent to a connection region24c3of the conductive pattern24c, which will be described later. The second long side of the semiconductor device26is arranged in a position spaced away from the gate electrode26aand is arranged to be adjacent to the connection region24c3. Consequently, the gate electrodes25aand26aare directed to the short side (on the lower side inFIG.2) of the insulation substrate22. The conductive pattern24aand the semiconductor devices25and26are joined together via solder layers30(30A and30B), respectively, and the collector electrodes which are formed on the respective back surfaces of the semiconductor devices25and26are electrically connected with the conductive pattern24a.

It is to be noted that three or more semiconductor devices may be arranged on the first arm portion A. In such a case also, the semiconductor devices are arranged such that the gate electrodes are arrayed in one line while being directed to the connection region24b1of the conductive pattern24bwith which the gate electrodes are connected.

The conductive pattern24bcomprises a control pattern of the first arm portion A. The control pattern is a conductive pattern with which the control electrodes (gate electrodes) of the semiconductor devices (the semiconductor devices25and26in the first arm portion A) are connected. The conductive pattern24bhas the connection region24b1which is positioned on an extended line of the gate electrodes25aand26aof the semiconductor devices25and26which are aligned along the Y axis. A bonding wire29athat is connected with the gate electrodes25aand26aof the semiconductor devices25and26is connected with the connection region24b1. Furthermore, the conductive pattern24bhas a contact region24b2with which an external connection terminal G1for the gate electrodes is connected. InFIG.2, the conductive pattern24bextends from a portion including the connection region24b1along the lower short side (X axis) of the insulation substrate22and vertically relative to an array of the semiconductor devices25and26.

The conductive pattern24ccomprises an emitter pattern of the first arm portion A and a collector pattern of the second arm portion B. The conductive pattern24cis one example of a “second conductive pattern” in the first arm portion A. Furthermore, the conductive pattern24cis one example of the “first conductive pattern” in the second arm portion B. The emitter pattern is a conductive pattern with which the output electrodes (emitter electrodes) of the semiconductor devices (the semiconductor devices25and26in the first arm portion A) are connected. The conductive pattern24chas a first region24c1that extends along the right long side of the insulation substrate22and has a generally rectangular shape, and a second region24c2that extends along the upper short side of the insulation substrate22and has a generally rectangular shape. The conductive pattern24cpresents a general L shape as a whole body.

The second region24c2comprises the emitter pattern of the first arm portion A. In the second region24c2, the connection region24c3is provided on an extended line from the semiconductor devices25and26along the Y axis. Bonding wires29cextending from the output electrodes25band26bof the semiconductor devices25and26and a single-bonding wire29cxextending from the output electrode25bof the semiconductor device25are connected with the connection region24c3. A contact region24c4is provided in the second region24c2, and the external connection terminal U to be connected with the load is connected with the contact region24c4.

The first region24c1comprises the collector pattern of the second arm portion B. On the first region24c1, the semiconductor devices27and28are arranged at an interval along the Y axis. More specifically, each of the semiconductor devices27and28has a third long side and a fourth long side. The third long side of the semiconductor device27is arranged to be adjacent to the gate electrode27a. The third long side of the semiconductor device28is arranged to be adjacent to the gate electrode28a. The fourth long side of the semiconductor device27is arranged adjacent to a connection region24d1of a conductive pattern24ddescribed later and is spaced away from the gate electrode27a. The fourth long side of the semiconductor device28is arranged adjacent to the connection region24d1and spaced away from the gate electrode28a. Consequently, the gate electrodes27aand28aare directed to the short side (on an upper side inFIG.2) of the insulation substrate22. The first region24c1of the conductive pattern24cand the semiconductor devices27and28are joined together via solder layers (not illustrated), and the collector electrodes formed on the back surfaces of the semiconductor devices27and28are electrically connected with the conductive pattern24c.

It is to be noted that three or more semiconductor devices may be arranged on the second arm portion B. In such a case also, the semiconductor devices are arranged such that the gate electrodes are arrayed in one line while being directed to a connection region24e1of the conductive pattern24ewith which the gate electrodes are connected.

The conductive pattern24dcomprises a control pattern of the second arm portion B. The conductive pattern24dhas the connection region24d1, and the connection region24d1is positioned on an extended line of the gate electrodes27aand28aof the semiconductor devices27and28aligned along the Y axis. Connected with the connection region24d1is a bonding wire29bconnected with the gate electrodes27aand28aof the semiconductor devices27and28. Furthermore, the conductive pattern24dhas a contact region24d2, and an external connection terminal G2for the gate electrodes is connected with the contact region24d2. InFIG.2, the conductive pattern24dextends from a portion including the connection region24d1along the upper short side (X axis) of the insulation substrate22and vertically to an array of the semiconductor devices27and28.

The conductive pattern24ecomprises an emitter pattern of the second arm portion B. The conductive pattern24eis one example of the “second conductive pattern” in the second arm portion B. In the conductive pattern24e, the connection region24e1is provided on an extended line from the semiconductor devices27and28along the Y axis. Bonding wires29dextending from the output electrodes27band28bof the semiconductor devices27and28and a single-bonding wire29dxextending from the output electrode28bof the semiconductor device28are connected with the connection region24e1. A contact region24e2is provided in the conductive pattern24e, and an external connection terminal (not illustrated) is connected with the contact region24e2. As illustrated inFIG.4and so forth, the external connection terminal N to be connected with the negative electrode of the external power source is connected with the contact region24e2.

The bonding wires29ato29d(including the single-bonding wires29cxand29dx) are examples of wiring members that connect the semiconductor devices25to28with the conductive patterns24. The bonding wires29ato29dare made of metal such as aluminum or copper, which has excellent electrical conductivity, or an alloy including at least one of these, or the like. Furthermore, it is preferable that a diameter of each of the bonding wires29ato29dbe equal to or greater than 100 μm and equal to or less than 1 mm.

In the present embodiment, although a wire is used as the wiring member, a ribbon cable (ribbon wire) may be used as the wiring member. A wire is a linear member, and a current flows one-dimensionally in the wire. A ribbon cable is a belt-shaped member with a predetermined width, and a current flows two-dimensionally in the ribbon cable. It is to be noted that other than these, a lead frame has been known as a wiring member in a semiconductor apparatus. A lead frame is a plate-shaped member, and a current flows three-dimensionally in the lead frame. A lead frame has an advantage such as low resistance compared to a wire and a ribbon cable, but has difficulty in application to the present embodiment due to complication of processes in connecting with the semiconductor devices25to28or the conductive patterns24. Thus, wires and ribbon cables are used as the wiring members in the present embodiment.

The bonding wire29ais formed with a single wire stitch bonded to the gate electrode25aof the semiconductor device25, the gate electrode26aof the semiconductor device26, and the connection region24b1. It is to be noted that, in stitch bonding, three or more points are bonded in such a manner that the points are successively connected by a single wire from first bonding to final bonding via bonding at one or more intermediate points. The bonding wire29ais successively joined to the gate electrode25a, the gate electrode26a, and the connection region24b1and electrically connects these together. The bonding wire29afunctions as a gate wire through which a control current to the gate electrodes25aand26aflows. As illustrated inFIG.2, the gate electrode25a, the gate electrode26a, and the connection region24b1are arranged in one line along the Y axis. Thus, the bonding wire29aalso extends along the Y axis.

The bonding wire29bis formed with a single wire stitch bonded to the gate electrode28aof the semiconductor device28, the gate electrode27aof the semiconductor device27, and the connection region24d1. The bonding wire29bis successively joined to the gate electrode28a, the gate electrode27a, and the connection region24d1and electrically connects these together. The bonding wire29bfunctions as a gate wire through which a control current to the gate electrodes27aand28aflows. As illustrated inFIG.2, the gate electrode28a, the gate electrode27a, and the connection region24d1are arranged in one line along the Y axis. Thus, the bonding wire29balso extends along the Y axis.

The bonding wire29celectrically connects together the output electrode25bof the semiconductor device25, the output electrode26bof the semiconductor device26, and the conductive pattern24c. The bonding wire29cfunctions as an emitter wire through which an output current from the output electrodes (emitter electrodes)25band26bflows. More specifically, one wire is stitch bonded to two points on the output electrode26b, to two points on the output electrode25b, and to one point on the connection region24c3, a total of five points, and the bonding wire29cis thereby formed. The points at which stitches are formed by stitch bonding (hereinafter, referred to as “stitch point”) are aligned along the short sides of the semiconductor devices25and26, that is, the Y axis, and the bonding wire29cthus extends along the Y axis similarly to the bonding wire29a. The stitch points in the output electrode25bare respectively positioned on opposite sides of the gate runner25c. The stitch points in the output electrode26bare respectively positioned on opposite sides of the gate runner26c.

FIG.5is a cross-sectional view in which a region Z in the cross-sectional view of the semiconductor unit illustrated inFIG.3is enlarged. For example, as illustrated inFIG.5, one bonding wire29chas five bonding points and is demarcated into four partial wires29c1to29c4while having three stitch points among the five stitch points as boundaries. The partial wire29c1is a portion, in the bonding wire29c, between a bonding point P1on the output electrode26bof the semiconductor device26and a stitch point P2on the output electrode26b, the stitch point P2being spaced away from the bonding point P1along the Y axis. The partial wire29c2is a portion, in the bonding wire29c, between the stitch point P2on the output electrode26bof the semiconductor device26and a stitch point P3on the output electrode25bof the semiconductor device25. The partial wire29c2is one example of a “first wiring member”. The partial wire29c3is a portion, in the bonding wire29c, between the stitch point P3on the output electrode25bof the semiconductor device25and a stitch point P4on the output electrode25b, the stitch point P4being spaced away from the stitch point P3along the Y axis. The partial wire29c4is a portion, in the bonding wire29c, between the stitch point P4on the output electrode25bof the semiconductor device25and a bonding point P5on the connection region24c3of the conductive pattern24c. The partial wire29c4is one example of a “second wiring member”. It is to be noted thatFIG.2illustrates a case in which four bonding wires29care provided, but any number of bonding wires29cmay be used.

Furthermore, inFIGS.2and5, stitch bonding is performed, by one wire (bonding wire29c), to two points on the output electrode26b, to two points on the output electrode25b, and to one point on the connection region24c3, a total of five points, but stitch bonding is not limited thereto. It is sufficient that stitch bonding be performed at one or more points on the output electrode26b, one or more points on the output electrode25b, and one or more points on the connection region24c3. In this case also, the “first wiring member” may be a partial wire between a bonding point on the output electrode26bwhich is closest to the output electrode25band a bonding point on the output electrode25bwhich is closest to the output electrode26b. Furthermore, the “second wiring member” may be a partial wire between a bonding point on the output electrode25bwhich is closest to the conductive pattern24c(connection region24c3) and a bonding point on the connection region24c3which is closest to the output electrode25b.

The bonding wire29delectrically connects together the output electrode27bof the semiconductor device27, the output electrode28b, and the conductive pattern24e. The bonding wire29dfunctions as an emitter wire through which an output current from the output electrodes (emitter electrodes)27band28bflows. More specifically, one wire is stitch bonded to two points on the output electrode27b, to two points on the output electrode28b, and to one point on the connection region24e1, a total of five points, and the bonding wire29dis thereby formed. The stitch points are aligned along the short sides of the semiconductor devices27and28, that is, the Y axis, and the bonding wire29dthus extends along the Y axis similarly to the bonding wire29b. The stitch points in the output electrode27bare respectively positioned on opposite sides of the gate runner27c. The stitch points in the output electrode28bare respectively positioned on opposite sides of the gate runner28c.

The single-bonding wire29cxis joined to one point on the output electrode25bof the semiconductor device25and one point on the connection region24c3of the conductive pattern24cand electrically connects together the output electrode25band the conductive pattern24c. The single-bonding wire29cxis one example of a “third wiring member”. The single-bonding wire29cxfunctions as an emitter wire through which an output current from the output electrode (emitter electrode)25bflows. The single-bonding wire29cxis bonded to a position, in the output electrode25b, on an opposite side of the gate runner25cfrom the gate electrode25aand is bonded to the connection region24c3. The bonding points are arranged along the short side of the semiconductor device25, that is, the Y axis, and the single-bonding wire29cxthus extends along the Y axis similarly to the bonding wire29c.FIG.2illustrates a case in which one single-bonding wire29cxis provided, but two or more single-bonding wires29cxmay be provided.

The single-bonding wire29dxis joined to one point on the output electrode28bof the semiconductor device28and one point on the connection region24e1of the conductive pattern24eand electrically connects together the output electrode28band the conductive pattern24e. The single-bonding wire29dxfunctions as an emitter wire through which an output current from the output electrode (emitter electrode)28bflows. The single-bonding wire29dxis bonded to a position, in the output electrode28b, on an opposite side of the gate runner28cfrom the gate electrode28aand is bonded to the connection region24e1. The bonding points are arranged along the short side of the semiconductor device28, that is, the Y axis, and the single-bonding wire29dxthus extends along the Y axis similarly to the bonding wire29d.FIG.2illustrates a case in which one single-bonding wire29dxis provided, but two or more single-bonding wires29dxmay be provided.

An inverter circuit illustrated inFIG.4is configured with the semiconductor devices25to28, the conductive patterns24ato24e, the bonding wires29a,29b,29c, and29d, and the single-bonding wires29cxand29dx. The first arm portion (upper arm portion) A is configured with the semiconductor devices25and26, the conductive patterns24a,24b, and24c, and the bonding wires29aand29c(including the single-bonding wire29cx). Furthermore, the second arm portion (lower arm portion) B is configured with the semiconductor devices27and28, the conductive patterns24c,24d, and24e, and the bonding wires29band29d(including the single-bonding wire29dx). Furthermore, in the semiconductor unit20, the external connection terminal P to be connected with the positive electrode of the external power source is connected with the contact region24a1, and the external connection terminal N to be connected with the negative electrode of the external power source is connected with the contact region24e2. Furthermore, in the semiconductor unit20, the external connection terminal U to be connected with the load on the outside of the semiconductor apparatus10is connected with the contact region24c4. Accordingly, the semiconductor unit20functions as an inverter. In the semiconductor unit20, for example, external connection terminals (not illustrated) are respectively joined to the contact regions24a1,24c4, and24e2, and the semiconductor devices25to28and the bonding wires29ato29don the circuit substrate21may be sealed by a sealing member. As the sealing member in this case, for example, a thermosetting resin such as a maleimide-modified epoxy resin, a maleimide-modified phenolic resin, or a maleimide resin can be used.

As described above, in the semiconductor unit20according to the present embodiment, the output electrode25bof the semiconductor device25, the output electrode26bof the semiconductor device26, and the connection region24c3of the conductive pattern24c, which constitute the first arm portion A, are arranged to be aligned in one line. These are connected together by the bonding wires29c, which are stitch bonded to the output electrode26b, the output electrode25b, and the connection region24c3of the conductive pattern24c. That is, in the semiconductor apparatus10, the semiconductor device25is arranged at an interval from the conductive pattern24calong the Y axis, the semiconductor device26is arranged at an interval from the semiconductor device25along the Y axis, and the partial wire29c2and the partial wire29c4extend along the Y axis. Thus, the bonding wire29cserves as both the emitter wire of the semiconductor device25and the emitter wire of the semiconductor device26. Accordingly, compared to a case in which connection between the output electrode25bof the semiconductor device25and the conductive pattern24cand connection between the output electrode26bof the semiconductor device26and the conductive pattern24care each made by separate wires, the connection region24c3can be reduced in size, and by the amount of reduction in size, mounting areas of the semiconductor devices25and26can be expanded.

Furthermore, in the present embodiment, the output electrode25bof the semiconductor device25, the output electrode26bof the semiconductor device26, and the connection region24c3of the conductive pattern24care connected together by stitch bonding of one bonding wire29c. That is, in the semiconductor apparatus10, the partial wire29c2and the partial wire29c4are formed with a single wire (bonding wire29c) that is stitch bonded to the output electrode26bof the semiconductor device26, the output electrode25bof the semiconductor device25, and the conductive pattern24c. Accordingly, the semiconductor devices25and26can simply be connected together, and manufacturing efficiency of the semiconductor apparatus10can be improved.

Furthermore, in the present embodiment, in addition to the bonding wires29c, the single-bonding wire29cxis provided which connects only the output electrode25bof the semiconductor device25and the conductive pattern24ctogether. That is, in the semiconductor apparatus10, in addition to the bonding wires29cincluding the partial wires29c2and the partial wires29c4, the single-bonding wire29cxis further provided which is a wire for connecting the output electrode25bof the semiconductor device25and the conductive pattern24ctogether. Accordingly, a part of a current that flows to the conductive pattern24cvia the semiconductor device25can be caused to flow through the single-bonding wire29cx, and a temperature rise in joining portions of the partial wires29c4to the semiconductor device25can thereby be controlled.

Furthermore, in the present embodiment, each of the semiconductor devices25and26presents a rectangular shape in plan view, and the semiconductor devices25and26are arranged along the short sides of the rectangular shapes. That is, in the semiconductor apparatus10, when viewed in plan view, each of the semiconductor device26and the semiconductor device25presents a rectangular shape which has a pair of long sides opposed to each other and a pair of short sides opposed to each other, and is arranged on the conductive pattern24asuch that the short sides are placed along the Y axis. As described above, the output electrode25bof the semiconductor device25, the output electrode26bof the semiconductor device26, and the connection region24c3of the conductive pattern24care arranged to be aligned in one line, and the bonding wires29care arranged therealong. Thus, the bonding wires29cextend in parallel with the short sides of the semiconductor devices25and26. Therefore, the bonding wires29ccan be arranged to be aligned along the long sides of the semiconductor devices25and26, and it is possible to increase the number of the bonding wires29ccompared to a case in which the bonding wires29care arranged to be aligned along the short sides.

Furthermore, in the present embodiment, the gate runners25cand26care provided on the respective front surfaces of the semiconductor devices25and26, and the gate runner25cis arranged in parallel with the long sides of the semiconductor device25, and the gate runner26cis arranged in parallel with the long sides of the semiconductor device26. That is, in the semiconductor apparatus10, the gate electrode26aand the gate runner26celectrically connected with the gate electrode26aare provided to the output electrode26bof the semiconductor device26, the gate electrode25aand the gate runner25celectrically connected with the gate electrode25aare provided to the output electrode25bof the semiconductor device25, and the gate runners26cand25care arranged in parallel with the long sides of the front surfaces. The gate runner25cis arranged in parallel with the long sides of the semiconductor device25, the gate runner26cis arranged in parallel with the long sides of the semiconductor device26, and transmission delay of a control current to each portion of the semiconductor devices25and26can thereby be reduced. Furthermore, the gate runner25cis arranged in parallel with the long sides of the semiconductor device25, the gate runner26cis arranged in parallel with the long sides of the semiconductor device26, and wires can thereby efficiently be arranged when the bonding wires29care arranged to be aligned along the long sides of the semiconductor devices25and26. It is to be noted that in the above, a description is made by taking the first arm portion A as an example, but the same applies to the second arm portion B.

Next, flow of a current in the semiconductor unit20will be described with reference toFIG.6toFIG.8. In the following description, description will be made by taking flow of a current in the first arm portion A as an example, but the same applies to flow of a current in the second arm portion B.

FIG.6is a diagram schematically illustrating flow of a current in the cross-sectional view inFIG.5.FIG.5andFIG.6illustrate the insulation substrate22, the conductive patterns24aand24cwhich are formed on the insulation substrate22, the semiconductor devices25and26which are arranged on the conductive pattern24a, the solder layer30A which joins the semiconductor device25and the conductive pattern24atogether, the solder layer30B which joins the semiconductor device26and the conductive pattern24atogether, and the bonding wire29c. The solder layers30A and30B are examples of a “connection layer”.

A current I that is input from the external connection terminal P to the contact region24a1of the conductive pattern24aflows through the conductive pattern24aand first reaches an input region24a2. The input region24a2is a region, in the conductive pattern24a, that overlaps the semiconductor device26present in a position relatively close to the contact region24a1(a position relatively far from the conductive pattern24c). The input region24a2is one example of a “first input region”. A current i1is a part of the current I that reaches the input region24a2, flows to the input electrode26dof the semiconductor device26via the solder layer30B and flows to the output electrode26bof the semiconductor device26. The current i1further flows to the partial wire29c2, which connects together the output electrode26band the output electrode25bof the semiconductor device25. It is to be noted that from the semiconductor device26to a connection point (the stitch point P2, a point ξ which will be described later) of the partial wire29c2, the current i1may flow through the partial wire29c1, which connects together internal portions of the output electrode26b. Subsequently, the current i1passes through the partial wire29c3which connects together multiple points of the output electrode25band reaches a connection point (the stitch point P4, a point θ which will be described later) on the output electrode25b, the connection point being closest to the conductive pattern24c(connection region24c3). It is to be noted that a part of the current i1may flow in the output electrode25binstead of the partial wire29c3. Then, the current i1is merged with a current i2(described later) at the output electrode25b, the merged current I passes through the partial wire29c4, which connects together the output electrode25band the connection region24c3of the conductive pattern24c, flows through the conductive pattern24c, and reaches the contact region24c4, which is connected with the external connection terminal U. Here, a flow path of the divided current i1will be referred to as path L1. That is, the path L1may range from the input region24a2, via the semiconductor device26, to the output electrode25bof the semiconductor device25. More specifically, the path L1may range from the input region24a2, via the solder layer30B, a portion between the electrodes (the input electrode26dand the output electrode26b) of the semiconductor device26, and the partial wire29c2which connects together the output electrode26bof the semiconductor device26and the output electrode25bof the semiconductor device25, to the stitch point P4, which is the connection point on the output electrode25bwith the partial wire29c4.

In the current I having reached the input region24a2, the current i2other than the current i1to be supplied to the semiconductor device26reaches an input region24a4via an intermediate region24a3. The input region24a4is one example of a “second input region”. The input region24a4is a region, in the conductive pattern24a, that overlaps the semiconductor device25present in a position relatively far from the contact region24a1(a position relatively close to the conductive pattern24c). The intermediate region24a3is a region, of the conductive pattern24a, between the input region24a2and the input region24a4. The current i2having reached the input region24a4flows to the input electrode25dof the semiconductor device25via the solder layer30A, flows to the output electrode25bof the semiconductor device25, and reaches the connection point (the stitch point P4, the point θ which will be described later) on the output electrode25b, the connection point being closest to the conductive pattern24c(connection region24c3). It is to be noted that from the semiconductor device25to the stitch point P4(the point θ described later), the current i2may flow through the partial wire29c3, which connects together internal portions of the output electrode25b. Then, the current i2is merged with the current i1at the output electrode25b. The merged current I passes through the partial wire29c4which connects together the output electrode25band the connection region24c3of the conductive pattern24c, flows through the conductive pattern24c, and reaches the contact region24c4which is connected with the external connection terminal U. Here, a flow path of the divided current i2will be referred to as path L2. That is, the path L2may range from the input region24a2, via the semiconductor device25, to the output electrode25bof the semiconductor device25. More specifically, the path L2may range from the input region24a2, via the intermediate region24a3, the input region24a4, the solder layer30A, and a portion between the electrodes (the input electrode25dand the output electrode25b) of the semiconductor device25, to the stitch point P4as the connection point on the output electrode25bwith the partial wire29c4.

InFIG.6, a point α may be a point adjacent to the contact region24a1, in the input region24a2, and may approximately be provided directly below the bonding point P1. A point β may be a point adjacent to the intermediate region24a3, in the input region24a2, and may be provided approximately directly below the stitch point P2. A point γ may be a point adjacent to the intermediate region24a3, in the input region24a4, and may be provided approximately directly below the stitch point P3. A point δ may be a point adjacent to the conductive pattern24c, in the input region24a4, and may be provided approximately directly below the stitch point P4.

InFIG.6, a point ε is a start point of the partial wire29c1and is the bonding point P1in the present embodiment. The point ξ is an end point of the partial wire29c1and a start point of the partial wire29c2(the first wiring member) and is the stitch point P2in the present embodiment. A point η is an end point of the partial wire29c2and a start point of the partial wire29c3and is the stitch point P3in the present embodiment. The point θ is an end point of the partial wire29c3and a start point of the partial wire29c4(the second wiring member) and is the stitch point P4in the present embodiment.

The above point α to point θ are respective conceptual points about which resistances in the input electrodes25dand26dand in the output electrodes25band26bof the semiconductor devices25and26are ignored.

A resistance between the contact region24a1and the point α is set as a resistance Rp1. A resistance between the point α and the point β is set as a resistance Rp2. A resistance between the point β and the point γ is set as a resistance Rp3. A resistance between the point γ and the point δ is set as a resistance Rp4. Consequently, the resistances Rp1to Rp4may be resistances in the conductive pattern24a. A resistance between the point α and the point δ is set as a resistance Rc1a. A resistance between the point β and the point ξ is set as a resistance Rc1b. Consequently, the resistances Rc1aand Rc1bmay be a resistance between the electrodes (a resistance between the input electrode26dand the output electrode26b) of the semiconductor device26and a resistance of the solder layer30B between the semiconductor device26and the conductive pattern24a. A resistance between the point γ and the point η is set as a resistance Rc2a. A resistance between the point δ and the point θ is set as a resistance Rc2b. Consequently, the resistances Rc2aand Rc2bmay be a resistance between the electrodes (a resistance between the input electrode25dand the output electrode25b) of the semiconductor device25and a resistance of the solder layer30A between the semiconductor device25and the conductive pattern24a. A resistance between the point ε and the point ξ is set as a resistance Rw1. A resistance between the point ξ and the point η is set as a resistance Rw2. A resistance between the point η and the point θ is set as a resistance Rw3. A resistance between the point θ and a point P5is set as a resistance Rw4. Consequently, the resistances Rw1to Rw4may be resistances in the partial wires29c1to29c4.

Here, when non-uniformity of a current that flows through the semiconductor devices25and26is discussed, resistances related to wiring in the same semiconductor devices, specifically, the resistances Rw1, Rp2, Rw3, and Rp4can be ignored. This is because the resistances related to the wiring in the same semiconductor devices hardly contribute to non-uniformity of a current between the semiconductor devices. Furthermore, the resistances Rc1aand Rc1b, which are the resistance between the electrodes of the same semiconductor device25and the resistance of the solder layer30A, can be considered to be the same. Thus, the resistances Rc1aand Rc1bare set as a resistance Rc1. Furthermore, the resistances Rc2aand Rc2b, which are the resistance between the electrodes of the same semiconductor device26and the resistance of the solder layer30B, can be considered to be the same. Thus, the resistances Rc2aand Rc2bare set as a resistance Rc2.

FIG.7is a diagram which results from removal of the resistances related to the wiring in the same semiconductor devices fromFIG.6. Furthermore,FIG.8is an equivalent circuit diagram ofFIG.7. As described above, in the first arm portion A, there flows the current i1flowing through the path L1, which starts from the input region24a2, passes through the semiconductor device26, and reaches the stitch point P4, and the current i2flowing through the path L2, which starts from the input region24a4, passes through the semiconductor device25, and reaches the stitch point P4. Referring toFIG.7andFIG.8, on the path L1, the resistance Rc1and the resistance Rw2are present. The resistance Rc1and the resistance Rw2contribute to non-uniformity of a current in the semiconductor devices25and26. Furthermore, on the path L2, the resistance Rp3and the resistance Rc2are present. The resistance Rp3and the resistance Rc2contribute to non-uniformity of a current in the semiconductor devices25and26. Thus, by Ohm's law and so forth, a ratio i2/i1of the current i2flowing through the path L2relative to the current i1flowing through the path L1can be expressed by the following Formula (1).

In the above Formula (1), the resistance Rc1includes the resistance between the electrodes (the resistance between the input electrode26dand the output electrode26b) of the semiconductor device26and the resistance of the solder layer30B. The resistance Rw2includes a resistance of the partial wire29c2, which is the first wiring member. The resistance Rc2includes the resistance between the electrodes (the resistance between the input electrode25dand the output electrode25b) of the semiconductor device25and the resistance of the solder layer30A. The resistance Rp3includes a resistance of the intermediate region24a3.

In general, a resistivity of the bonding wire29cis high compared to a resistivity of the conductive pattern24a. Furthermore, when it is assumed that the semiconductor devices25and26are elements of the same type to which properties such as materials or structures are the same, the resistance Rc1is equivalent to the resistance Rc2. Thus, in general design, the current i2which flows through the path L2is large compared to the current i1which flows through the path L1(current i1<current i2). When such non-uniformity of a current occurs, in the semiconductor device in which a flowing current is relatively large (the semiconductor device25in the present embodiment), a temperature of a portion in which the semiconductor device and the wire are joined together (hereinafter, referred to as “wire joining portion”) becomes relatively high, a power cycle tolerance, a short-circuit tolerance, an I2t tolerance, and so forth of the semiconductor device are reduced as a result, and furthermore, there is a possibility that long-term reliability of the semiconductor apparatus10cannot be maintained.

Here, a range of the current will be discussed that allows for prevention or reduction in lowering of various tolerances of the semiconductor devices25and26. As described above, lowering of various tolerances of the semiconductor devices25and26occurs due to a temperature rise in the wire joining portion. It is preferable that a temperature difference between the wire bonding portions in the semiconductor devices25and26fall within 20° C. That is, when between the semiconductor devices25and26which are connected in parallel, a temperature rise in the wire joining portion in the semiconductor device through which a larger current flows is set as T2and a temperature rise in the semiconductor device through which a smaller current flows is set as T1, it is preferable that T2−T1=ΔT≤20° C. hold true. In this case, for example, in a case of T1=100° C., T2has to be limited to 120° C. or less (in other words, T2≤T1×1.20). A temperature rise of the wire is proportional to the square of a current. The square root of 1.20 is about 1.10. Thus, the current i2in the semiconductor device in which the current is greater has to be limited to 110% or less (i2≤i1×1.10) relative to the current i1in the semiconductor device in which the current is less. Accordingly, in the present embodiment, the ratio i2/i1of the current i2flowing through the path L2relative to the current i1flowing through the path L1is set to a value which is equal to or greater than 0.90 and equal to or less than 1.10. For example, in the first arm portion A, the ratio i2/i1of the current i2, which flows from the input region24a4to the conductive pattern24cvia the semiconductor device25, relative to the current i1, which flows from the input region24a2to the conductive pattern24cvia the semiconductor device26, is equal to or greater than 0.90 and equal to or less than 1.10.

Further preferably, it is preferable that the temperature difference between the wire bonding portions in the semiconductor devices25and26fall within 15° C. That is, it is preferable that T2−T1=ΔT≤15° C. hold true. In this case, for example, in a case of T1=100° C., T2has to be limited to 115° C. or less (in other words, T2≤T1×1.15). The square root of 1.15 is about 1.07. Thus, in this case, the current i2in the semiconductor device in which the current is greater has to be limited to 107% or less (i2≤i1×1.07) relative to the current i1in the semiconductor device in which the current is less. That is, further preferably, the ratio i2/i1of the current i2flowing through the path L2relative to the current i1flowing through the path L1is set to a value which is equal to or greater than 0.93 and equal to or less than 1.07.

Still further preferably, it is preferable that the temperature difference between the wire bonding portions in the semiconductor devices25and26fall within 10° C. That is, it is preferable that T2−T1=ΔT 10° C. hold true. In this case, for example, in a case of T1=100° C., T2has to be limited to 110° C. or less (in other words, T2≤T1×1.10). The square root of 1.10 is about 1.05. Thus, in this case, the current i2in the semiconductor device in which the current is greater has to be limited to 105% or less (i2≤i1×1.05) relative to the current i1in the semiconductor device in which the current is less. That is, still further preferably, the ratio i2/i1of the current i2flowing through the path L2relative to the current i1flowing through the path L1is set to a value which is equal to or greater than 0.95 and equal to or less than 1.05.

Furthermore, as described above, when a resistance of the path L1is set as R1, R1=Rc1+Rw2holds true. Furthermore, when a resistance of the path L2is set as R2, R2=Rc2+Rp3holds true. Thus, it can be considered that the above formula (1) represents a ratio R1/R2of the resistance R1of the path L1relative to the resistance R2of the path L2. That is, in the present embodiment, when the ratio R1/R2of the resistance R1of the path L1relative to the resistance R2of the path L2is equal to or greater than 0.90 and equal to or less than 1.10, a similar effect can also be obtained.

In this case also, further preferably, it is desirable that the ratio R1/R2of the resistance R1relative to the resistance R2be equal to or greater than 0.93 and equal to or less than 1.07. Still further preferably, it is desirable that the ratio R1/R2of the resistance R1relative to the resistance R2be equal to or greater than 0.95 and equal to or less than 1.05.

In the present embodiment, values of parameters included in the above formula (1) are adjusted such that the current generally uniformly flows through the path L2and the path L1. Specifically, the values of the parameters included in the above formula (1) are set such that the ratio i2/i1of the current i2flowing through the path L2relative to the current i1flowing through the path L1becomes equal to or greater than 0.90 and equal to or less than 1.10. It is to be noted that, as described above, a further preferable ratio i2/i1is equal to or greater than 0.93 and equal to or less than 1.07, and a still further preferable ratio i2/i1is equal to or greater than 0.95 and equal to or less than 1.05.

In the following, methods of adjusting the values of the parameters included in the above formula (1) will be specifically described. As described above, because the resistivity of the bonding wire29cis high compared to the resistivity of the conductive pattern24a, in general design, the current i2which flows through the path L2is large compared to the current i1which flows through the path L1(current i1<current i2). Thus, in order to eliminate non-uniformity of the current, at least one of Method A for increasing the current i1or Method B for decreasing the current i2may be performed. It is to be noted that Method A and Method B may simultaneously be employed. That is, the current i1may be increased, and the current i2may be decreased.

Method A: Increasing Current i1

In order to increase the current i1, the resistance on the path L1may be reduced. Specifically, at least one of Method A-1 for reducing the resistance Rc1or Method A-2 for reducing the resistance Rw2may be performed.

The resistance Rc1includes the sum of the resistance of the solder layer30B and the resistance of the semiconductor device26(more specifically, the resistance between the electrodes of the semiconductor device26). Thus, in order to reduce the resistance Rc1, for example, a configuration is possible in which the resistance of the semiconductor device26is made low compared to a resistance of the semiconductor device25, or a configuration is possible in which the resistance of the solder layer30B is made low compared to the resistance of the solder layer30A.

Examples of methods for reducing the resistance Rc1may include the following:Example 1 As the semiconductor device26, a low-speed type RC-IGBT is used in which conduction loss is small compared to the semiconductor device25.Example 2 As the semiconductor device26, an RC-IGBT is used in which a saturation current density is high compared to the semiconductor device25.Example 3 As the semiconductor device26, an RC-IGBT is used in which a threshold voltage Vth is small compared to the semiconductor device25.Example 4 A thickness of the solder layer30B is made thinner than a thickness of the solder layer30A.

The resistance Rw2includes the resistance of the partial wire29c2, which is the first wiring member. In order to reduce the resistance Rw2, for example, a total cross-sectional area, i.e., the sum of cross-sectional areas of the bonding wires29c, may be increased. In this case, when the resistance Rw2is the same as the resistance Rp3including the resistance of the intermediate region24a3, the ratio i2/i1will be one, and the current i2will be equivalent to the current i1. It is to be noted that due to a factor such as a temperature, a value of resistance changes. Thus, the “same” in this case includes a case in which the resistances perfectly agree with each other and also a case in which the resistances substantially agree with each other. A case in which the resistances substantially agree with each other is a case such as one in which the resistances are predicted to be the same under a predetermined condition.

Examples of methods for reducing the resistance Rw2may include the following:Example 1 The number of bonding wires29cis increased.Example 2 A diameter of the bonding wire29cis thickened.Example 3 Instead of the wire, a ribbon cable formed of copper or the like is used as the wiring member.

In order to decrease the current i2, the resistance on the path L2may be made higher. Specifically, at least one of Method B-1 for increasing the resistance Rp3or Method B-2 for increasing the resistance Rc2may be performed.

The resistance Rp3includes the resistance of the intermediate region24a3. In order to increase the resistance Rp3, for example, a cross-sectional area of the intermediate region24a3may be decreased compared to the input region24a2which is present on an upstream side of the intermediate region24a3.

Specifically, for example, as illustrated inFIG.9, a trench T may be provided in which a part of the conductive pattern24cof the intermediate region24a3is removed. That is, in Method B-1, in the intermediate region, a trench may be provided in which a part of the first conductive pattern is removed. The trench T illustrated inFIG.9is formed between the long sides of the adjacent semiconductor devices25and26and along the long sides. Because central portions in the semiconductor devices25and26are likely to produce heat, it is preferable that the trench T be formed around central portions of the long sides of the semiconductor devices25and26. The trench T may be formed together when the conductive patterns24ato24eare formed, for example. That is, the conductive patterns24ato24eare formed by selective removal (for example, etching) of a metal layer formed on the insulation substrate22. Specifically, etching is performed, with portions to become the conductive patterns24ato24ein the metal layer being masked, for example. In this process, the metal layer is removed by etching a region corresponding to the trench T without the region being masked, and the trench T can thereby be formed. In the trench T, the insulation substrate22may be exposed by complete removal of the metal layer, or the metal layer may be removed to the extent that a thickness is thin compared to other regions (for example, the input region24a2) of the conductive pattern24c.

The resistance Rc2includes the resistance of the solder layer30A and the resistance of the semiconductor device25. In order to increase the resistance Rc2, for example, a configuration is possible in which the resistance of the semiconductor device25is made high compared to the resistance of the semiconductor device26, or a configuration is possible in which the resistance of the solder layer30A is increased compared to the resistance of the solder layer30B.

Examples of methods for increasing the resistance Rc2may include the following:Example 1 As the semiconductor device25, a high-speed type RC-IGBT is used in which conduction loss is large compared to the semiconductor device26.Example 2 As the semiconductor device25, an RC-IGBT is used in which the saturation current density is low compared to the semiconductor device26.Example 3 As the semiconductor device25, an RC-IGBT is used in which the threshold voltage Vth is large compared to the semiconductor device26.Example 4 The thickness of the solder layer30A is made thicker than the thickness of the solder layer30B.

Next, a range of each parameter in the above formula (1) will be discussed. First, the resistances Rc1and Rc2will be discussed. The resistance Rc1includes a resistance Re1between the electrodes of the semiconductor device26and a resistance Rs1of the solder layer30B. The resistance Rc2includes a resistance Re2between the electrodes of the semiconductor device25and a resistance Rs2of the solder layer30A.

FIG.10andFIG.11are graphs representing examples of I-V curves of the semiconductor device.FIG.10illustrates an I-V curve in a situation in which a device temperature is at room temperature (25° C.), andFIG.11illustrates an I-V curve at a device temperature of 175° C. In each of the graphs, the horizontal axis represents an applied voltage, and the vertical axis represents a current that flows through the semiconductor device. The semiconductor device used for measurement of the I-V curves is an RC-IGBT which is used for a semiconductor apparatus with a rated voltage of 1,700 V and a rated current of 2,200 A, a rated current of the semiconductor device is 183 A, and a chip size is 13.9 mm×13.5 mm Based on the I-V curves at an applied voltage of 1 V or greater, the resistance of this semiconductor device at room temperature is 3.9 mΩ, and the resistance at 175° C. is 7.5 mΩ. Thus, the resistance of this semiconductor device for 1 square centimeter is 2 mΩ/cm2at the room temperature and 4 mΩ/cm2at 175° C.

A current density of the semiconductor apparatus in which this semiconductor device is used is approximately 150 A/cm2. Furthermore, in general, current densities of an IGBT and an FWD with rated voltages of 650 V to 3.3 kV are from 75 A/cm2to 450 A/cm2. Thus, it is preferable that a resistance for 1 square centimeter of each of the semiconductor devices25to28to be used for the semiconductor apparatus10be in a range of 1 mΩ/cm2to 6 mΩ/cm2at room temperature and in a range of 2 mΩ/cm2to 12 mΩ/cm2at 175° C.

Next, the resistance Rw2and the resistance Rp3will be discussed. When the range (equal to or greater than 0.90 and equal to or less than 1.10) of the above ratio i2/i1is applied to the above Formula (1), the following Formula (2) is provided.

In the above Formula (2), when it is assumed that the semiconductor devices25and26are of the same type and the thicknesses of the solder layers30A and30B are the same, Rc1=Rc2=R can be set. When Rw2=y and Rp3=x are set, the above Formula (2) becomes the following Formula (3).

FIG.12illustrates a graph of the above Formula (3). Because a resistance takes a positive value, when Rw2and Rp3are caused to fall in a hatched range inFIG.12, the ratio i2/i1of the current i2relative to the current i1becomes equal to or greater than 0.90 and equal to or less than 1.10.

It is to be noted that, as described above, a further preferable ratio i2/i1is equal to or greater than 0.93 and equal to or less than 1.07. Thus, when Rc1=Rc2=R, Rw2=y, and Rp3=x are set, the further preferable range is expressed by the following Formula (4).

Furthermore, a still further preferable ratio i2/i1is equal to or greater than 0.95 and equal to or less than 1.05. Thus, when Rc1=Rc2=R, Rw2=y, and Rp3=x are set, the still further preferable range is expressed by the following formula (5).

As described above, the semiconductor apparatus10according to the embodiment is configured such that with respect to the pairs of semiconductor devices25,26and27,28which are connected in parallel, the ratio of currents which flow through each pair falls in a certain range. That is, taking the first arm portion A as an example, the semiconductor apparatus10includes the insulation substrate22, the conductive patterns which are provided on the main surface of the insulation substrate22and have the conductive pattern24aand the conductive pattern24c, and the semiconductor device26and the semiconductor device25which are each arranged on the conductive pattern24a. The conductive pattern24aincludes the input region24a2which overlaps the semiconductor device26and the input region24a4which overlaps the semiconductor device25. The semiconductor device26and the semiconductor device25respectively include the input electrodes26dand25dwhich are provided on the back surface opposed to the conductive pattern24aand are electrically connected with the conductive pattern24a, and the output electrodes26band25bwhich are provided on the front surface on the opposite side to the back surface. The output electrode26bof the semiconductor device26and the output electrode25bof the semiconductor device25are connected with each other by the partial wire29c2. The output electrode25bof the semiconductor device25and the conductive pattern24care connected to each other by the partial wire29c4. The ratio i2/i1of the current i2, which flows from the input region24a4to the conductive pattern24cvia the semiconductor device25, relative to the current i1, which flows from the input region24a2to the conductive pattern24cvia the semiconductor device26, is equal to or greater than 0.90 and equal to or less than 1.10. Accordingly, the semiconductor apparatus10can reduce degradation of the wire joining portion due to non-uniformity of the currents flowing through the semiconductor devices25and26and can improve the power cycle tolerance, the short-circuit tolerance, the I2t tolerance, and so forth of the semiconductor devices25and26. Furthermore, the semiconductor apparatus10can maintain long-term reliability.

The further preferable ratio i2/i1of the current i2relative to the current i1is equal to or greater than 0.93 and equal to or less than 1.07, and the still further preferable ratio i2/i1of the current i2relative to the current i1is equal to or greater than 0.95 and equal to or less than 1.05. Accordingly, the semiconductor apparatus10can make the currents flowing through the semiconductor devices25and26more uniform and can more reliably prevent degradation due to non-uniformity of the currents.

Furthermore, in the semiconductor apparatus according to the embodiment, the ratio R1/R2of the resistance R1of the path L1, which starts from the input region24a2, passes through the semiconductor device26and the partial wire29c2, and reaches the stitch point P4, relative to the resistance R2of the path L2, which starts from the input region24a4, passes through the semiconductor device25, and reaches the stitch point P4as the connection point between the output electrode25bof the semiconductor device25and the partial wire29c4, may be equal to or greater than 0.90 and equal to or less than 1.10. Accordingly, the semiconductor apparatus10can reduce degradation of the wire joining portion due to non-uniformity of the currents flowing through the semiconductor devices25and26and can improve the power cycle tolerance, the short-circuit tolerance, the I2t tolerance, and so forth of the semiconductor devices25and26. Furthermore, the semiconductor apparatus10can maintain long-term reliability.

A further preferable ratio R1/R2of the resistance R1relative to the resistance R2is equal to or greater than 0.93 and equal to or less than 1.07, and a still further preferable ratio R1/R2of the resistance R1relative to the resistance R2is equal to or greater than 0.95 and equal to or less than 1.05. Accordingly, the semiconductor apparatus10can make more uniform the currents flowing through the semiconductor devices25and26and can more certainly prevent degradation due to non-uniformity of the currents.

In order to cause the ratio i2/i1or the ratio R1/R2to fall in the above ranges, for example, the resistance Rc1as the sum of the resistance of the solder layer30B and the resistance of the semiconductor device26may be reduced. That is, in the semiconductor apparatus10, the sum of (i) the resistance between the input electrode26dand the output electrode26bin the semiconductor device26and (ii) the resistance of the solder layer30B which connects the semiconductor device26and the conductive pattern24atogether may be less than the sum of (i) the resistance between the input electrode25dand the output electrode25bin the semiconductor device25and (ii) the resistance of the solder layer30A which connects the semiconductor device25and the conductive pattern24atogether. Accordingly, the resistance of the path L1in which the resistance Rc1is positioned becomes small, and the current i1flowing through the path L1can thereby be increased.

Furthermore, in order to cause the ratio i2/i1or the ratio R1/R2to fall in the above ranges, for example, the resistance Rw2may be reduced which includes the resistance of the partial wire29c2(the first wiring member) connecting together the output electrode26bof the semiconductor device26and the output electrode25bof the semiconductor device25. In this case, it is preferable that the resistance R2is the same as the resistance Rp3including the resistance of the intermediate region24a3. That is, in the semiconductor apparatus10, the resistance Rw2of the partial wire29c2may be the same as the resistance Rp3of the intermediate region24a3which is the region, of the conductive pattern24a, between the input region24a2and the input region24a4. Accordingly, the resistance of the path L1in which the resistance Rw2is positioned becomes small, and the current i1flowing through the path L1can thereby be increased.

Furthermore, in order to cause the ratio i2/i1or the ratio R1/R2to fall in the above ranges, for example, the resistance Rp3as the resistance of the intermediate region24a3may be increased. Specifically, for example, as illustrated inFIG.9, the trench T may be provided in which a part of the conductive pattern24aof the intermediate region24a3is removed. That is, in the semiconductor apparatus10, the cross-sectional area of the intermediate region24a3which is the region, of the conductive pattern24a, between the input region24a2and the input region24a4may be smaller than a cross-sectional area of the input region24a2. In the intermediate region24a3, the trench T may be provided in which a part of the conductive pattern24ais removed. Accordingly, the resistance of the path L2in which the resistance Rp3is positioned becomes large, and the current i2flowing through the path L2can thereby be decreased.

Furthermore, in order to cause the ratio i2/i1or the ratio R1/R2to fall in the above ranges, for example, the resistance Rc2, which is the sum of the resistance of the solder layer30A and the resistance of the semiconductor device25, may be increased. That is, in the semiconductor apparatus10, the sum of the resistance between the input electrode25dand the output electrode25bin the semiconductor device25and the resistance of the solder layer30A which connects the semiconductor device25and the conductive pattern24atogether may be greater than the sum of the resistance between the input electrode26dand the output electrode26bin the semiconductor device26and the resistance of the solder layer30B which connects the semiconductor device26and the conductive pattern24atogether. Accordingly, the resistance of the path L2in which the resistance Rc2is positioned becomes large, and the current i2flowing through the path L2can thereby be decreased.

Furthermore, in the present embodiment, because the semiconductor devices25to28are RC-IGBTs, an FWD does not have to be used. An area in the semiconductor apparatus10on which the semiconductor devices are mountable can be increased, and a large capacity of the semiconductor apparatus10can be realized.

It is to be noted that in the present embodiment, it is assumed that the semiconductor devices25to28are RC-IGBTs, but this is not restrictive, and the semiconductor devices25to28may be other switching elements such as an IGBT and a power MOSFET. Furthermore, as the semiconductor devices25to28, diodes such as an SBD (Schottky Barrier Diode) and an FWD may be included as needed.

Furthermore, the number of semiconductor devices25to28of the semiconductor unit20is one example and is not limited to a case in which two semiconductor devices are arranged in each of the arm portions and the semiconductor unit20is configured with two arm portions. For example, three or more semiconductor devices may be arranged in each of the arm portions. In such a case also, ratios among currents which flow via the semiconductor devices are set to values which are equal to or greater than 0.90 and equal to or less than 1.10. Furthermore, for example, as the semiconductor devices, an IGBT chip and an FWD chip may be simultaneously arranged in each of the arm portions. In such a case also, IGBT chips are arranged such that gate electrodes are arrayed in one line while the gate electrodes are directed to one side that is parallel with an array of the IGBT chips. FWD chips may be arranged in another line in parallel with the line of the IGBT chips or may be arranged in the same line as the IGBT chips. Furthermore, for example, the semiconductor unit20may be configured with three or more arm portions. In such a case, three or more arm portions are arranged to be aligned vertically to an array of the semiconductor devices.

DESCRIPTION OF REFERENCE SIGNS