Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment

The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (Ccell) of the storage cell; measuring a local bitline capacitance (Cbl) of the storage cell; measuring a transfer device voltage (VT) of the storage cell; computing a transfer ratio (TR) for the storage cell; and measuring a data retention time for the storage cell.

FIELD OF THE INVENTION

The present invention is directed generally to DRAM cells, and, more particularly, monitoring process parameters related to dynamic random access memory (DRAM).

BACKGROUND OF THE INVENTION

The use of DRAM technology has become widespread, especially in higher end system designs, because of its superior performance, silicon-area savings, and low power compared with discrete-memory approaches. A highly integrated DRAM approach also simplifies board design, thereby reducing overall system cost and time to market. Even more important, embedding DRAM enables higher bandwidth by allowing larger on-chip memory and a wider on-chip bus and saves power by eliminating DRAM I/O buffers. Today, designers can take advantage of these capabilities as various high density DRAM technologies enter production. However, DRAM cells utilizing these technologies are susceptible to a large amount of process variation due to factors such as threshold voltage variation and mismatch. It is this process variation that creates limitations on the design and fabrication of the DRAM and the associated systems.

Thus, there is a need to provide monitoring for measuring statistics of important DRAM parameters in order to control the inherent process variation.

SUMMARY OF THE INVENTION

The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (Ccell) of the storage cell; measuring a local bitline capacitance (Cbl) of the storage cell; measuring a transfer device voltage (VT) of the storage cell; computing a transfer ratio (TR) for the storage cell; and computing a data retention time for the storage cell.

DETAILED DESCRIPTION OF THE INVENTION

Referring generally toFIG. 1a flowchart illustrating a method100for measuring statistics of dynamic random access memory (DRAM) process parameters in accordance with an exemplary embodiment of the present invention is shown. In a present embodiment, the method100includes sending a connection request102to a DRAM and specifically to a storage cell therein. The request then resulting in a connection to the storage cell requested. Upon establishing the connection the method includes measuring the storage cell capacitance (Ccell)104. For example, the method of measuring the storage cell capacitance (Ccell)104may be performed by charge-based capacitance measurement techniques whereby the step of measuring the storage cell capacitance includes activating a corresponding word-line of the storage cell of the DRAM while simultaneously de-activating all other word-lines in the DRAM array. The selected word-line is driven by a voltage much higher than Vddto guarantee full Vddtransition at the storage capacitance in a certain time-period. The local bitline and the selected storage cell capacitance are charged to a positive supply voltage (Vdd) by pulsing a corresponding write bitline (WBL) and discharged to ground by pulsing a corresponding read bitline (RBL). The capacitances are repeatedly charged and discharged and Cbl+Ccellis measured from the average current drawn from the power (Cbl+Ccell)×Vdd=(Iavg(WL-on)×TPeriod 2). Here, Tperiod2is the period of the pulses used to charge and discharge the capacitances. It should be chosen to allow full rail-to-rail transition at the bitline and the storage capacitance.

The method100further includes measuring a local bitline capacitance (Cbl)106. For example, the method of measuring the bitline capacitance (Cbl)106cell capacitance may be performed by Charge-Based Capacitance Measurement techniques whereby the step of measuring the bitline capacitance includes de-activating all word-lines of the DRAM. The selected bitline is charged to a positive supply voltage (Vdd) by pulsing a corresponding write bitline (WBL). The local bitline is then discharged to ground by pulsing the corresponding read bitline (RBL) and the Cblis then measured from the average current drawn from the power usage (Cbl×VDD)=(Iavg(wl-off)×TPeriod1). Tperiod1is the time period of the pulses used to charge and discharge the bitline and ensure full rail-to-rail transition.

The method100further includes the step of measuring the transfer device voltage threshold (VT)108of the storage cell. In a present embodiment the VTof the transfer device is measured by driving the selected word-line to VDD. The WBL and RBL are then pulsed and the average supply current is measured. The VT108is computed from the measured average current and the previously measured capacitances of Cbland Ccell. If the word-line is driven to Vdd, the Cblcharges all the way to VDD, while the Ccellcharges only up to (VDD−VT). The frequency is selected to ensure full transition at Cblwhile (VDD−VT) transition at the storage capacitance. Computation of the VT108from the measured average current and previously measured capacitances of Cbland Ccell(Cbl×VDD)+(Ccell×(VDD−VT))=(Iavg(WL=VDD)×TPeriod3). Here Tperiod3is time period of the pulses used to charge and discharge the bitline.

The method100further includes computing the transfer ratio (TR)110. In a present embodiment the transfer ratio which determines the amount of signal developed on LBL during read operation is computed as TR=Ccell/Ccell+Cbl.

The method100further includes computing the leakage rate114, data retention time112, and access time, etc from circuit simulation, such as from SPICE (simulation program with integrated circuit emphasis) where the VT110of the transfer device, the storage cell capacitance104, and the bitline capacitance106, are known.

Referring generally toFIG. 2is a circuit diagram illustrating a preferred embodiment of the present invention. Circuit200is comprised of a plurality of storage cells, wherein one storage cell204is identified for simplicity. A pulse generator206provides a charge to a micro sense amplifier202. The micro sense amplifier202is used to charge and discharge the local bitline capacitance by pulsing a corresponding write bitline210and read bitline208.

The micro sense amplifier is one particular implementation of the existing sense amplifier being used to charge and discharge the bitline and cell capacitance. In the present invention the micro sense amplifier is reconfigured for measurement. For example, the micro sense amplifier is reconfigured to open the connection of the source drain terminal where the read head device is connected to the WBL and RBL. In other embodiments of the present invention different micro sense amplifiers may require similar alterations to enable measurement processes. By using the existing sense amplifier devices there is no alteration of the bitline capacitance. Furthermore, using existing micro sense amplifier devices requires minimum perturbation in layout.

The present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. Furthermore, the invention may take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium may be any apparatus that may contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

It is understood that the specific order or hierarchy of steps in the foregoing disclosed methods are examples of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the method can be rearranged while remaining within the scope of the present invention. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.