Integrated circuit package system with interconnect support

An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.

TECHNICAL FIELD

The present invention relates generally to integrated circuit packaging, and more particularly to a system for packaging of flipchip integrated circuit die.

BACKGROUND ART

The integrated circuit has become indispensable in our daily life, including food, clothing, lodging, transportation, education, and entertainment. Product assembled using integrated circuit devices can be found everywhere. Sophisticated electronic products continue to be developed that are more user-friendly and have functions that are more complicated. In order to provide improving convenience and usage, product design trends are towards lighter, thinner, shorter, and smaller.

Higher integration can be achieved through chip scale package (CSP) applications such as flip chip technology. Flip chip technology can employ area arrays for bump pads including connections to a carrier, thereby reducing package area and shortening transmission paths. A flip chip is generally a semiconductor device, such as an integrated circuit, having bead-like terminals formed on one surface of the chip. The terminals serve to both secure the chip to a circuit board and electrically connect the flip chip's circuitry to a conductor pattern formed on the circuit board, which may be a ceramic substrate, printed wiring board, flexible circuit, or a silicon substrate. The typical flip chip is generally quite small, resulting in the terminals being crowded along the perimeter. As a result, conductor patterns are typically composed of numerous conductors often spaced closely.

Because of the fine patterns of the terminals and conductor pattern, soldering a flip chip to its conductor pattern requires a significant degree of precision. Reflow solder techniques are widely utilized in the soldering of flip chips. Such techniques typically involve forming solder bumps on the surface of the flip chip. Heating the solder above its melting temperature serves to form the characteristic solder bumps. The chip is then soldered to the conductor pattern by registering the solder bumps with their respective conductors, and reheating, or reflowing, the solder so as to metallurgically and electrically bond the chip to the conductor pattern.

Deposition and reflow of the solder must be precisely controlled not only to coincide with the spacing of the terminals and the size of the conductors, but also to control the height of the solder bumps after soldering. Controlling the height of solder bumps after reflow is necessary in order to provide proper positioning of the chip after reflow. Sufficient spacing between the chip and substrate is necessary for enabling stress relief during thermal cycles, providing electrical isolation, allowing cleaning solutions for removing undesirable residues during manufacturing, and enabling bonding and encapsulation materials between the chip and the substrate.

By properly limiting the degree to which the molten solder can laterally expand during reflow, the height of the solder bumps, and therefore the spacing between chip and substrate, can be closely controlled by depositing an appropriate amount of solder at each terminal location. Packaging processes are still plagued by conventional techniques that cannot closely control the height of a flip chip's solder bumps and suffer from excessive solder wetting, reduced collapse height, poor IC planarity, solder overflow and insufficient lead registration or locking.

Thus, a need still remains for an integrated circuit package system to provide improved package performance and manufacturing including control over solder bump reflow and package encapsulation. In view of the increasing demand for improved integrated circuits and particularly more functions in smaller products at lower costs, it is increasingly critical that answers be found to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides an integrated circuit package system with interconnect support comprising providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. The same numbers are used in all the drawing FIGs. to relate to the same elements.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “system” means the method and the apparatus of the present invention. The term “processing” as used herein includes stamping, forging, patterning, exposure, development, etching, cleaning, and/or removal of the material or laser trimming as required in forming a described structure.

Referring now toFIG. 1, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support100with interconnect support, in an embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support100includes an integrated circuit102having the electrical interconnects104, such as solder balls, solder columns, stud bumps, or the like. The integrated circuit102, such as a flipchip integrated circuit, is mounted on a lead frame having contact pads106, a chip support108and a paddle110. The integrated circuit102rests on the chip support108during the reflow process. The chip support108provides sufficient clearance between the integrated circuit102and the contact pads106to prevent the collapse of the electrical interconnects104. An epoxy molding compound112encapsulates the integrated circuit102, the electrical interconnects104, the chip support108, the surface of the paddle110and the surface of the contact pads106.

Referring now toFIG. 2, therein is shown a top view of the integrated circuit package system with interconnect support100with interconnect support, ofFIG. 1, with the epoxy molding compound112on the upper portion removed. The top view of the integrated circuit package system with interconnect support100depicts the integrated circuit102mounted within an array of the contact pads106. A cut line1-1indicates where the view ofFIG. 1was taken. A tie bar202runs diagonally under the integrated circuit102and provides corner stability. The epoxy molding compound112holds the structure of the package in place and protects the electrical interconnects104, ofFIG. 1.

Referring now toFIG. 3, therein is shown a top view of a leadframe300, ofFIG. 2. The top view of the leadframe300depicts an outer frame302with contact tabs304, such as half etched metal. The leadframe300is punched or forged from a sheet of metal, such as copper, tin or another conductive material. The contact tabs304support the contact pads106. One of the contact pads106on each side of the leadframe300may be coupled to the chip support108and further couple to the paddle110. This combination is known as fused leads, since all of the contact pads106are electrically connected through the paddle110.

The tie bar202has the chip support108and also connects to the paddle110. The tie bar202does not involve using any of the contact pads106and is therefore a preferred configuration. Since the tie bar202emanates from each corner of the leadframe300, they represent a stable platform for the integrated circuit102, ofFIG. 1, during the reflow process.

Referring now toFIG. 4, therein is shown a top view of an alternative leadframe400for the integrated circuit package system with interconnect support100, in an alternative embodiment of the present invention. The top view of the alternative leadframe400depicts an outer frame402with contact tabs404, such as half etched metal. The alternative leadframe400is punched or forged from a sheet of metal, such as copper, tin or another conductive material. The contact tabs404support the contact pads106. The tie bar202, which supports the paddle110, has the chip support108located proximate the paddle110.

Referring now toFIG. 5, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support500, in a second alternative embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support500depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. A chip support502couples the contact pads106to the paddle110in a fused contact configuration. The chip support502contacts the integrated circuit102substantially midway between the electrical interconnects104and the paddle110. This position may be useful to reduce the parasitic capacitance near the electrical interconnects104.

Referring now toFIG. 6, therein is shown a cross-sectional view of the integrated circuit package system with interconnect support600, in a third alternative embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support600depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. A chip support602couples the contact pads106to the paddle110in a fused contact configuration. The chip support602contacts the integrated circuit102substantially adjacent to the electrical interconnects104. This position may be useful in order to add parasitic capacitance to the signal path. The chip support602may also provide a thermal path to the paddle110allowing better thermal performance of the integrated circuit package system with interconnect support600.

Referring now toFIG. 7, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support700, in a fourth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support700depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. A chip support702couples the contact pads106to the paddle110in a fused contact configuration. The chip support702contacts the integrated circuit102substantially adjacent to the paddle110. This position may be useful in order to add parasitic capacitance to the signal path. The chip support702may also provide a thermal path to the paddle110allowing better thermal performance of the integrated circuit package system700.

Referring now toFIG. 8, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support800, in a fifth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support800depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. A chip support802couples the contact pads106to the paddle110in a fused contact configuration. The chip support802contacts the integrated circuit102substantially midway between the electrical interconnects104and the paddle110. This position may be useful to reduce the parasitic capacitance near the electrical interconnects104. The chip support802has a rounded contour which may substantially reduce the contact surface area with the integrated circuit102.

Referring now toFIG. 9, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support900, in a sixth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support900depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. A chip support902extends from one of the contact pads106on each side of the integrated circuit package system with interconnect support900. By placing the chip support902, on the integrated circuit102, adjacent to the electrical interconnects104, there is no need to have the tie bar202or the paddle110. During the reflow process, the integrated circuit102is lowered onto the chip support902. The chip support902then prevents the further collapse of the electrical interconnects104.

Referring now toFIG. 10, therein is shown a bottom view of the integrated circuit package system with interconnect support900, ofFIG. 9. The bottom view of the integrated circuit package system with interconnect support900depicts several of the contact pads106aligned around the outer edges of the integrated circuit package system with interconnect support900. The chip support902extends from the contact pads106located in the center of each side. The integrated circuit102rests on the chip support902after the reflow process. The structure of the chip support902prevents the collapse of the electrical interconnects, thus eliminating solder contamination of the outer leads and solder bridging. The epoxy molding compound112holds the integrated circuit102and the contact pads106in place. The cut line9-9indicates the view represented inFIG. 9.

Referring now toFIG. 11, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support1100, in a seventh alternative embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support1100depicts the integrated circuit102coupled to the contact pads106by the electrical interconnects104. The integrated circuit102is on a chip support1102that extends from the tie bar202. The epoxy molding compound112encapsulates the integrated circuit102, the electrical interconnects104, the contact pads106, the tie bar202, and the chip support1102.

Referring now toFIG. 12, therein is shown a bottom view of the integrated circuit package system with interconnect support1100, in the seventh alternative embodiment of the present invention. The bottom view of the integrated circuit package system with interconnect support1100depicts the cut line11-11, which starts on a diagonal through the tie bar202and the chip support1102, then turns to cut through the contact pads106. After the reflow process, the integrated circuit102rests on the chip support1102, positioned near the corner of the integrated circuit102die. The epoxy molding compound112encapsulates the integrated circuit102, the contact pads106, the tie bar202, and the chip support1102.

Referring now toFIG. 13, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support1300, in the eighth embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support1300depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. A chip support1302extends from one of the contact pads106on each side of the integrated circuit package system with interconnect support1300. The chip support1302has a protuberance1304on the upper surface. The protuberance1304may be a hemispherical, a cone, a pyramid shape, or any other shape that limits the contact area on the integrated circuit102. The protuberance1304is shown near the end of the chip support1302, but it is understood that it may be positioned on any structure beneath the integrated circuit102.

Referring now toFIG. 14A, therein is shown is a bottom view of the chip support1302having a recess1402. The bottom view of the chip support1302depicts the recess1402, such as a circular, cylindrical, conical, or pyramid-like recess, with a pass through1404. The pass through1404is an optional feature and is intended to minimize the contact area between the protuberance1304, ofFIG. 13, and the integrated circuit102, ofFIG. 1. A cut line14B-14B indicates the placement for the cross-sectional view ofFIG. 14B.

Referring now toFIG. 14B, therein is shown a cross-sectional view of the chip support1302, taken along the cut line14B-14B, ofFIG. 14A. The cross-sectional view of the chip support1302depicts the protuberance1304with the recess1402and the pass through1404. The pass through1404allows a path for the epoxy molding compound112, ofFIG. 1, to displace air that may be captured in the recess1402during the molding process. The protuberance1304may be forged, molded, punched or adhered on the chip support1302. For illustrative purposes, the protuberance1304is shown near the edge of the chip support1302, but it is understood that the protuberance1304may be positioned at any location beneath the integrated circuit102, ofFIG. 1. Further, the pass through1404is an optional feature and the protuberance1304may be formed without it.

Referring now toFIG. 14C, therein is shown a bottom view of the chip support1302, in an alternative embodiment, having the recess1402. The bottom view of the chip support1302depicts the alternative construction of the chip support1302, wherein a first width1406of the chip support1302is narrower than a second width1408of a recess area1410. The position of the recess area1410is for example only and the recess area1410may be positioned on the tie bar202, ofFIG. 2, on the paddle110, ofFIG. 1, or any structure that is beneath the integrated circuit102, ofFIG. 1.

Referring now toFIG. 15, therein is shown a cross-sectional view of an integrated circuit package system with interconnect support1500, in a ninth embodiment of the present invention. The cross-sectional view of the integrated circuit package system with interconnect support1500depicts the integrated circuit102having the electrical interconnects104coupled to the contact pads106. The contact pads106are supported by the contact tabs304, ofFIG. 3, and the outer frame302, ofFIG. 3. An elevated paddle1502, formed by the tie bar202bent upward, provides support for the integrated circuit102during the reflow process. As the electrical interconnects104deform due to the reflow process, the integrated circuit102is lowered onto the elevated paddle1502, which provides support for the integrated circuit102and prevents any further collapse of the electrical interconnects.

Referring now toFIG. 16, therein is shown a bottom view of the integrated circuit package system with interconnect support1500, using the tie bar202for the elevated paddle1502. The bottom view of the integrated circuit package system with interconnect support1500depicts the outer frame302having the tie bar202and the contact tabs304, which supports the contact pads106. The tie bar202has a bend region1602the transitions the tie bar202into the elevated paddle1502. The integrated circuit102rests on the elevated paddle1502after the reflow process has deformed the electrical interconnects104, ofFIG. 1.

Referring now toFIG. 17, therein is shown a bottom view of a leadframe1700for the integrated circuit package system with interconnect support1500, using fused leads1704for the elevated paddle1502. The bottom view of the leadframe1700depicts the outer frame302having the contact tabs304, which supports the contact pads106. The center of each side of the leadframe1700has the contact pads106coupled to a bent segment1702, which couples the fused leads1704in the position of the elevated paddle1502. The elevated paddle1502acts as a support for the integrated circuit102, ofFIG. 1, during the reflow process. As the electrical interconnects104, ofFIG. 1, start to deform the integrated circuit102rests on the elevated paddle1502. The support of the elevated paddle1502prevents further collapse of the electrical interconnects104.

Referring now toFIG. 18therein is shown a top view of a leadframe1800for the integrated circuit package system with interconnect support1500, using the tie bar202for the elevated paddle1502with the protuberance1304. The top view of the leadframe1800depicts the elevated paddle1502formed on the tie bar202, having the protuberance1304on each segment near the bend region1602and one of the protuberance1304at the vertex of the elevated paddle1502. The protuberance1304is shown with the pass through1404, ofFIG. 14B, though the pass through1404is optional and may be omitted. The addition of the protuberance1304provides a way to level the integrated circuit102, ofFIG. 1, while minimizing the contact area between the leadframe1800and the integrated circuit102.

Referring toFIG. 19, therein is shown a top view of a leadframe1900for the integrated circuit package system with interconnect support1500, using the fused leads1704for the elevated paddle1502, with the protuberance1304. The top view of the leadframe1900depicts the bent segment1702coupled to the fused leads1704. The protuberance1304is positioned on the fused leads near the bent segment1702and at the vertex of the fused leads1704. The combination of the fused leads and the protuberance1304forms the elevated paddle1502.

Referring toFIG. 20, therein is shown a top view of a leadframe2000for the integrated circuit package system with interconnect support1500, having the elevated paddle1502, with the protuberance1304. The top view of the leadframe2000depicts the elevated paddle1502comprising a ring support2002elevated on the bend region1602with the protuberance1304optionally formed at the tie points of the ring support2002. The ring support2002may be used without the protuberance1304formed at the tie points, if the contact area is not a concern.

Referring now toFIG. 21, therein is shown a flow chart of an integrated circuit package system with interconnect support2100for manufacturing the integrated circuit package system with interconnect support100in an embodiment of the present invention. The system2100includes providing an integrated circuit in a block2102; providing forming an electrical interconnect on the integrated circuit in a block2104; forming a contact pad having a chip support in a block2106; and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support in a block2108.

It has been discovered that the present invention thus has numerous aspects.

A principle aspect that has been unexpectedly discovered is that the present invention provides better chip planarity by regulation of the solder wetting and the collapse height.

Another aspect is present invention regulates solder contamination on the outer lead surface, and reduces solder bridging.

Thus, it has been discovered that the integrated circuit package system with interconnect support of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for packaging flip-chip QLP packages. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.