Semiconductor chip package and method of fabricating same

A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin, the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of the multi-layer wiring pattern; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the metal pattern.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor chip package, and more particularly to a semiconductor chip package and a method of fabricating a semiconductor chip package that reduces chip size package (CSP).

2. Description of the Related Art

There is an increasing demand for small-sized and lightweight electronic system units. In order to satisfy such demands, efforts have been made to reduce the size of semiconductor chips by decreasing circuit wire width and by reducing semiconductor chip package size. The structure and fabrication method of a conventional semiconductor chip package will now be explained with reference toFIGS. 1Ato1E.

As illustrated inFIG. 1E, a semiconductor chip12adheres to an upper center portion of a substrate10of a semiconductor chip package by an adhesive13. One side edge of a multi-layer wiring11, which is formed on the substrate10, is connected to a pad (not shown) on the semiconductor chip12by a wire14. A liquid sealing material17having a high viscosity surrounds the semiconductor chip12, the wire14and the one side edge of the multi-layer wiring11. A solder resist18covers an upper portion of the other side edge of the multi-layer wiring11, and a solder ball19is mounted on a predetermined portion thereof.

The fabrication method of the conventional semiconductor chip package as shown inFIG. 1Ewill now be explained.

First, as shown inFIG. 1A, the substrate10of the semiconductor chip package is prepared. The substrate10of the semiconductor chip package has a groove at its upper center portion. The multi-layer wiring11is formed on the substrate10outside the groove. The solder resist18covers the entire upper surface except for the one-side edge of the multi-layer wiring11. After the substrate10is thus prepared, the unit semiconductor chip12is separated (by sawing, for example) from a wafer and is mounted on the groove of the substrate10using the adhesive13.

As shown inFIG. 1B, the pad (not shown) on the upper surface of the semiconductor chip12is connected to the one side edge of the multi-layer wiring11by the wire14.

As shown inFIG. 1C, a dam16is formed with a liquid resin having a sufficiently high viscosity at a predetermined portion of the multi-layer wiring11using a dispenser15.

As shown inFIG. 1D, the semiconductor chip12, the wire14and one side edge of the multi-layer wiring11inside the dam16are sealed by the liquid sealing material17.

As shown inFIG. 1E, the solder resist18on the multi-layer wiring11is partially etched and removed, and a solder ball19is mounted thereon by a reflow process.

However, in the conventional package fabrication method, the substrate of the semiconductor package and the semiconductor chip are separately fabricated, and then the semiconductor chip is mounted on the substrate. As a result, the completed semiconductor chip package is thick and big. Thus, the semiconductor chip package does not provide small-sized and lightweight electronic systems. Also, the fabrication cost of the package also increases because the substrate for the semiconductor package is separately fabricated.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a semiconductor chip package and fabrication method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a semiconductor chip package having the same size as a semiconductor chip fabricated by spreading a thermosetting resin on a semiconductor chip and forming a printed circuit wiring thereon.

Another object of the present invention is to provide a fabrication method for a semiconductor chip package that improves productivity by simultaneously packaging a plurality of semiconductor chips.

Another object is to provide a fabrication method for a semiconductor chip package that is integral with a semiconductor chip.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor chip package comprises a semiconductor chip having an upper, a bottom, and side surfaces; a plurality of pads respectively disposed on portions of the upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface the semiconductor chip, the thermosetting resin defining through-holes to expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin, the multi-layer wiring pattern and the connecting unit, the solder-resist defining at least one through-hole to expose a portion of the multi-layer wiring pattern; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the metal pattern.

In another aspect, a method of fabricating a semiconductor chip package comprises the steps of preparing a wafer including a plurality of semiconductor chips having a plurality of pads on an upper surface of each semiconductor chip; spreading a thermosetting resin on the wafer; separating the respective plurality of semiconductor chips; providing a heat sink member including a metal ring frame having grooves at a side of the metal ring frame and a metal film disposed on a lower surface of the metal ring frame; mounting the semiconductor chip on the heat sink member; mounting a wiring member on the semiconductor chip, the wiring member defining openings such that the pads are exposed; filling a polymer resin between the semiconductor chip and the metal film; forming a wiring pattern by patterning the wiring member; exposing the pads; connecting the pads to the wiring pattern; spreading a solder resist on the semiconductor chip; removing a portion of the solder resist to expose a portion of the wiring pattern; and mounting a solder ball on the exposed portion of the wiring pattern.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2illustrates an embodiment of the semiconductor chip package in accordance with an embodiment of the present invention.

The semiconductor chip package ofFIG. 2includes a semiconductor chip20having a plurality of pads21at an upper center portion thereof, a thermosetting resin22formed on the semiconductor chip20except for the pads21, a multi-layer wiring pattern23formed on the thermosetting resin22having a stacked Al/Ni/Cu structure, a conductive layer pattern24stacked on the multi-layer wiring pattern23and the pads21to be electrically connected to each other, a polymer resin25surrounding both side and bottom portions of the semiconductor chip, a metal film to act as a heat sink26disposed at a lower portion of the polymer resin, a solder resist27covering an entire surface of the semiconductor substrate except for a predetermined portion of the conductive layer pattern24, and a solder ball28mounted at a predetermined portion of the conductive layer pattern24.

In an alternative embodiment shown inFIG. 3, the conductive layer pattern24may be replaced by a metal wire34in the semiconductor package. Here, a sealing unit35surrounding the pads21and the wire34is further provided. Except for the metal wire34and the sealing unit35, the configuration of the device ofFIG. 3is generally similar to that of FIG.2.

In yet another alternative embodiment shown inFIG. 4, the pads may be formed at an upper edge portion of the semiconductor chip, instead of its upper center portion. Here, the configuration of the device ofFIG. 4is generally similar to those ofFIGS. 2 and 3. Of course, other configurations and variations may be used in accordance with the present invention.

A method of fabricating the semiconductor chip package in accordance with the present invention will now be described. First, various members and devices used in fabricating the semiconductor chip package of the present invention will be explained.

FIGS. 5A and 5Brespectively show a plan view and a front view illustrating a structure of the wiring member300bto be prepared. Here, the wiring member300bincludes a ring-type frame50and an aluminum foil53adhered to an upper portion of the ring-type frame50and having a thickness of 0.5 to 10 μm. At least two grooves51,52are formed at a lower portion of the ring-type frame50. A plurality of openings54are formed on the aluminum foil53. The positions of the openings54correspond to those of the pads respectively formed at the upper portions of the semiconductor chips on the wafer, the openings54are sufficiently large to each respectively surround the pads of the semiconductor chips. That is, when the supporting member300band the wafer are aligned, each pad of the semiconductor chips can be shown through the openings54.

FIGS. 6A and 6Bare respectively plan and front views illustrating a heat sink member300c. A heat sink member300cas shown inFIGS. 6A and 6Bis fabricated and implemented into the semiconductor chip package. The heat sink member300cincludes a metal ring frame60and a metal film63, such as Al or Cu, having a thickness of 50 to 300 μm adhered to a lower portion of the metal ring frame60. At least two grooves61,62are formed at an upper portion of the ring-type frame60. Preferably, the positions of the grooves61,62correspond to the grooves51,52of the wiring member300b.

As depicted inFIG. 7, a heater block70is prepared. The heater block70will be used to fix and heat the semiconductor chip during the packaging process. Here, the heater block70includes an upper block71and a lower block72. A heating device721is provided in the lower block72. The upper bock71generally has a solid body711with a plurality of through holes712. Here, the upper edge portions of the through holes712are connected to a vacuum suction unit (not shown).

A method of fabricating the semiconductor chip package in accordance with the present invention will now be described with reference toFIGS. 8Ato8K.

First, a wafer300is prepared. A plurality of semiconductor chips300aare formed on the wafer300each having a plurality of pads310at its upper portion. As shown inFIG. 8A, in order to obtain a stress relaxation effect, a coating301, such as benzocyclo butene (BCB) or a silicone-group thermosetting resin, having a low elastic modulus and a high thermal expansive coefficient is spread over the wafer300having the plurality of semiconductor chips300awith a thickness of 50 to 200 μm using a spin-coating process. Here, if a thermosetting resin is used, a sol-type thermosetting resin is preferred. The sol-type thermosetting resin coating301is heated at a temperature of approximately 250° C. and softly cured to reach a B-stage state (30 to 50% of the resin is cured; gel type). Thereafter, a sawing process is used to cut the wafer300, and thus the semiconductor chips300a, into unit chips.

Referring toFIG. 8C, the heat sink member300cis provided on the lower block72of the heater block70. The wiring member300band the semiconductor chip300aare fixed to the upper block71of the heater block70. That is, the aluminum foil of the wiring member300band the semiconductor chip300aare fixed to the upper block71using vacuum suction through the through holes712. Here, the wiring member300band the semiconductor chip300aare also aligned so that the pads of the semiconductor chip300acan enter into the openings54.

Then, as further shown inFIG. 8C, the member for wiring300band the semiconductor chips300aare positioned on the heat sink member300c. The grooves51,52of the wiring member300band the grooves61,62of the heat sink member300care aligned in order to face each other in an identical position. As a result, a protrusion of the ring-type frame of the wiring member300bis connected to a protrusion of the metal ring frame of the heat sink member300c, and the grooves51,61and the grooves52,62are respectively connected to each other, thereby forming resin implanting holes85,86. A surface of the lower block72of the heater block70is larger than the member for the heat sink300c, thereby forming a space between a side wall of the lower block72of the heater block70and the heat sink member300c. The heater block70is heated at a temperature between 150 and 350° C. for 30 minutes to 5 hours using the heating device therein. Here, the thermosetting resin in the B-stage state spread on the semiconductor chip300ais completely cured by the heater block70and firmly adhered to the aluminum foil of the member for wiring. The vacuum suction is carried out from a space at one side, and the polymer resin, such as Ultem (brand name of a polymer sold by General Electrics) or silicone, is implanted via the space at the other side. The vacuum suction is used to remove air bubbles generated in the polymer resin. Here, the polymer resin flows to and fills the space between the semiconductor chip300aand the heat sink member300cthrough the resin implanting holes85,86by a capillary phenomenon.

As shown inFIG. 8D, a structure90having the wiring member300b, the semiconductor chip300a, and the heat sink member300cas a single body is taken out of the heater block70. Here, the metal film63of the heat sink member300cis positioned at the bottom surface, the polymer resin87is positioned on the metal film63, and the plurality of semiconductor chips300aare positioned in the polymer resin87. The aluminum foil53adheres to the upper portions of the semiconductor chips300aand the polymer resin87. The plurality of openings54are formed in the aluminum foil53.FIG. 8Eshows an enlarged perspective view of portion A of FIG.8D.

As shown inFIG. 8F, a nickel (Ni) layer88aand a copper (Cu) layer88bare formed on the aluminum foil53by an electroplating process.FIG. 8Gis a plan view of FIG.8F.

A photoresist pattern (not shown) is formed on the copper layer88b. The photoresist pattern corresponds to a pattern for wiring for adhering the solder ball. After the copper layer88b, the nickel layer88aand the aluminum foil53are sequentially etched using the photoresist pattern as a mask. The photoresist pattern is then removed, thereby forming a multi-layer pattern90as shown in FIG.8H and exposing the upper portion of the thermosetting resin on the semiconductor chip300a.

As shown inFIG. 8I, photo-lithography and etching are used to remove thermosetting resin on the pads310, thereby exposing the pads310.

A photoresist mask (not shown) is formed on the entire resultant structure ofFIG. 8Hexcept for the multi-layer wiring pattern90, the pads310, and spaces therebetween. A metal pattern91is formed on the multi-layer wiring pattern90and the pads310by accumulating a metal, such as Al or Au, using sputtering. The multi-layer wiring pattern90and the pads310are electrically connected by accumulation of the metal pattern91. The photoresist mask is then removed, thereby forming a structure as shown in FIG.8J.

As one alternative to the process ofFIG. 8J, as shown inFIG. 9A, the process of accumulating the metal pattern91may be replaced by a wiring process of connecting the upper portions of the pads310to the one side edge of the multi-layer wiring pattern90by a metal wire34. After the wiring process is finished, the wire35, the pads, and the one side edge of the multilayer wiring pattern90are covered with the liquid resin35having a high viscosity as shown in FIG.9B. Thus, the processes ofFIG. 8Jcan be replaced by the processes ofFIGS. 9A and 9B.

Thereafter, as shown inFIG. 8Ka solder resist film92is spread on the entire resultant structure of FIG.8J. Then, the solder resist film92is removed at predetermined portions of the metal patterns91by photo-lithography and etching, thereby exposing the predetermined portions of the metal patterns91. After the process as shown inFIG. 8Jis carried out on the plurality of semiconductor chips, a singulation process of dividing the semiconductor chips into the respective semiconductor chip packages by sawing is performed. Next, solder balls93are mounted on the predetermined exposed portions of the multi-layer wiring pattern90and reflowed. As a result, a semiconductor chip package as shown inFIG. 8Kis fabricated.

FIG. 10shows a vertical-sectional view taken along line X—X in FIG.8K. Hence, the semiconductor chip package in accordance with an embodiment of the present invention includes the semiconductor chip300ahaving the plurality of pads310at its upper center portion, the thermosetting resin301formed on the semiconductor chip300aexcept for the pads310, the multi-layer wiring pattern90formed on the thermosetting resin301and having a stacked Al/Ni/Cu structure, the metal patterns91disposed on the multi-layer wiring pattern90and the pads310to be electrically connected to each other, the polymer resin87surrounding both side and bottom portions of the semiconductor chip, the metal film using the heat sink63adhered to the lower portion of the polymer resin87, the solder resist92covering the entire semiconductor substrate except for a predetermined portion of the metal pattern91, and a solder ball93adhered to a predetermined portion of the metal pattern91.

The present invention provides a reduced chip package size, thereby reducing an area of the package on a printed wiring board. Hence, the present invention enables small-sized and lightweight electronic system units.

Moreover, the semiconductor chip package of the present invention allows considerably smaller sized solder balls as output terminals as compared to conventional devices. Thus, high pin density and a greater number of pins are enabled. Since the printed wiring board and the semiconductor chip pads are connected by the solder balls, a connection distance (conductive path) will be short, thereby improving electrical characteristics.

Furthermore, in accordance with embodiments of the present invention, because the semiconductor chips on the single wafer are packaged at one time, packaging speed is improved, thereby improving productivity.

In addition, the heat sink is provided at the lower portion of the package, thereby enabling high power applications.