Solid-state imaging apparatus and imaging system

Provided is a solid-state imaging apparatus, including amplifier units including: an amplifier having a first input terminal, a second input terminal, and an output terminal; an input capacitor having one terminal to which an output signal from a pixel is input, and another terminal connected to the second input terminal of the amplifier; a feedback switch connected between the second input terminal and the output terminal of the amplifier; and a feedback capacitor connected in parallel with the feedback switch and between the second input terminal and the output terminal of the amplifier, in which a driving current of the amplifier during a first period is smaller than a driving current of the amplifier during a second period in which the amplifier amplifies the output signal from the pixel, and the feedback switch is set to a connection state during the first period.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging apparatus and an imaging system.

2. Description of the Related Art

In Japanese Patent Application Laid-Open No. 2005-143078, there is disclosed a solid-state imaging apparatus having a configuration in which charge integrating amplifiers are arranged for respective columns of a pixel array including pixels arranged in matrix. The charge integrating amplifier of Japanese Patent Application Laid-Open No. 2005-143078 is set to a standby state while holding an image signal read out during a horizontal blanking period. When the signal is transferred to a horizontal signal line thereafter, among the plurality of charge integrating amplifiers, only the charge integrating amplifier for carrying out transfer is restored to a normal operation state from the standby state. In this manner, reduction in power consumption of the solid-state imaging apparatus is realized, which is described in Japanese Patent Application Laid-Open No. 2005-143078.

SUMMARY OF THE INVENTION

According to one embodiment of the present invention, there is provided a solid-state imaging apparatus including: a plurality of pixels constituting a pixel array including a plurality of pixel columns; and a plurality of amplifier units arranged respectively corresponding to the plurality of pixel columns of the pixel array, and configured to amplify a signal from corresponding one of the plurality of pixel columns, the plurality of amplifier units including: an amplifier having a first input terminal, a second input terminal, and an output terminal; an input capacitor having one terminal to which an output signal from corresponding one of the plurality of pixels is input, and another terminal connected to the second input terminal of the amplifier; a feedback switch connected between the second input terminal and the output terminal of the amplifier; and a feedback capacitor connected in parallel with the feedback switch and between the second input terminal and the output terminal of the amplifier, in which a driving current of the amplifier during a first period is smaller than a driving current of the amplifier during a second period in which the amplifier amplifies the output signal from the corresponding one of the plurality of pixels, and the feedback switch is set to a connection state during the first period.

DESCRIPTION OF THE EMBODIMENTS

Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings. Like components are denoted by like reference symbols throughout the drawings, and descriptions of overlapping components are sometimes omitted.

First Embodiment

FIG. 1is a block diagram for illustrating a configuration of a solid-state imaging apparatus according to a first embodiment of the present invention. The solid-state imaging apparatus includes a pixel array1, a vertical scanning circuit3, a column amplifier unit4, a first holding circuit5, and a horizontal scanning circuit6. The pixel array1includes a plurality of pixels2two-dimensionally arranged in matrix. The pixel2includes a photoelectric conversion element configured to generate charges in accordance with the intensity of irradiated light, and a transistor circuit configured to convert the charges generated in the photoelectric conversion element into a voltage signal to output the voltage signal. The pixel2is configured to output two types of signals, that is, an image signal with a voltage corresponding to the intensity of irradiated light, and a reset signal with a voltage corresponding to a noise generated in the pixel2during reset or the like.

The vertical scanning circuit3is connected to the pixels2of the pixel array1via wiring for each row, and outputs a control signal for selecting the row to read out the signal output from the pixel2. The column amplifier unit4is connected to the pixels2of the pixel array1via wiring for each column, and amplifies the output signal from the pixel2to output the amplified signal to the first holding circuit5. The first holding circuit5is a circuit configured to temporarily hold the signal input from the column amplifier unit4in a capacitor. The horizontal scanning circuit6outputs a control signal for selecting a column to output the signal to the first holding circuit5for each column.

FIG. 2is a circuit diagram for illustrating the column amplifier unit4and the first holding circuit5of the first embodiment in more detail. The column amplifier unit4includes input capacitors41, operational amplifiers42and45, feedback capacitors43, and feedback switches44. Note that, the “switch” herein refers to a circuit element that switches between on (connection state) and off (non-connection state) based on the control signal, and may be configured of a transistor, for example.

The operational amplifier42includes a non-inverting input terminal, an inverting input terminal, and an output terminal. A reference voltage VC0R is input to the non-inverting input terminal of the operational amplifier42. The image signal or the reset signal output from the pixel2of the pixel array1is input to the inverting input terminal of the operational amplifier42via the input capacitor41. Between the inverting input terminal and the output terminal of the operational amplifier42, the feedback switch44is connected. The on or off state of the feedback switch44is controlled by a signal PC0R. Between the inverting input terminal and the output terminal of the operational amplifier42, the feedback capacitor43is further connected, and the feedback capacitor43and the feedback switch44have a parallel connection relationship. The gain of the column amplifier unit4is determined depending on the ratio between the capacitance values of the input capacitor41and the feedback capacitor43.

The operational amplifier42further includes a terminal to which a signal VGN1is input. The signal VGN1is a voltage signal for controlling a current to be caused to flow through the operational amplifier42. By changing the voltage of the signal VGN1, the current amount that the operational amplifier42can output and the power consumption of the operational amplifier42can be changed.

The output signal of the operational amplifier42is input to a non-inverting input terminal of the operational amplifier45. An inverting input terminal of the operational amplifier45is connected to an output terminal thereof. Therefore, the operational amplifier45constitutes a voltage follower circuit configured to output a voltage corresponding to the output voltage of the operational amplifier42. The output terminal of the operational amplifier45is connected to the first holding circuit5. The voltage follower circuit including the operational amplifier45has a function of supplying a current when a capacitor in the first holding circuit5is caused to hold a voltage. The operational amplifier45may be omitted. However, particularly when the gain of the operational amplifier42is high, it is necessary to supply a large current to the first holding circuit5, and hence the configuration of this embodiment including the voltage follower including operational amplifier45is more suitable.

The operational amplifier45includes a terminal to which a signal VGN1_VF1is input. Similarly to the operational amplifier42, the voltage of the signal VGN1_VF1is changed so that the current amount that the operational amplifier45can output and the power consumption of the operational amplifier45can be changed.

In this embodiment, the voltage follower circuit including the operational amplifier45is connected to the output stage of the operational amplifier42, but the present invention is not limited thereto. As described above, the operational amplifier45is only required to be a buffer circuit for supplying a current to the first holding circuit5at the output stage, and may be replaced with a circuit element other than the voltage follower using the operational amplifier45. Further, the voltage amplification factor of the buffer circuit may be substantially1as in the voltage follower circuit exemplified in this embodiment, or may be other values.

The first holding circuit5includes holding capacitors51and52and switches53,54,55, and56. The switches53and54are controlled to be turned on or off by signals PTN and PTS, respectively. The switches55and56are controlled to be turned on or off by the control signals from the horizontal scanning circuit6. One terminal of each of the switches53and54is connected to the output terminal of the operational amplifier45. The other terminal of the switch53is connected to one terminal of the holding capacitor51and one terminal of the switch55. The other terminal of the holding capacitor51is connected to the ground. The other terminal of the switch55is connected to a horizontal signal line71. The other terminal of the switch54is connected to one terminal of the holding capacitor52and one terminal of the switch56. The other terminal of the holding capacitor52is connected to the ground. The other terminal of the switch56is connected to a horizontal signal line72.

When the switch53is turned on by the signal PTN, the reset signal voltage is held in the holding capacitor51. When the switch54is next turned on by the signal PTS, the image signal voltage is held in the holding capacitor52. After that, when the switches55and56are turned on by the control signals from the horizontal scanning circuit6, the reset signal and the image signal held in the holding capacitors51and52are output to the horizontal signal lines71and72, respectively.

The solid-state imaging apparatus of this embodiment can operate in a power saving mode for reducing the power consumption. In the power saving mode, the currents to be supplied to the operational amplifiers42and45have values smaller than the current during the signal read-out and within a range in which the operational amplifiers42and45are not turned off. By controlling the currents (driving currents) to be caused to flow through the operational amplifiers42and45with the signals VGN1and VGN1_VF1, the transition from the normal mode to the power saving mode and the transition from the power saving mode to the normal mode are carried out.

FIG. 3is a circuit diagram for illustrating the internal circuit of the operational amplifier42. The operational amplifier42constitutes a single-stage differential amplifier circuit. The operational amplifier42includes, as input/output terminals, a non-inverting input terminal In+, an inverting input terminal In−, an output terminal Out, and a driving current bias terminal VBias. The operational amplifier42includes transistors421,422,423,424, and425. The transistors421and422are each configured as a P-channel metal-oxide-semiconductor field effect transistor (MOSFET). The transistors423,424, and425are each configured as an N-channel MOSFET.

A power supply voltage VDD is input to a source terminal of each of the transistors421and422. Gate terminals of the transistors421and422are shared and connected to a drain terminal of the transistor421. Drain terminals of the transistors421and422are connected to drain terminals of the transistors423and424, respectively. Further, the drain terminal of the transistor424forms the output terminal Out. Gate terminals of the transistors423and424form the non-inverting input terminal In+ and the inverting input terminal In−, respectively. Source terminals of the transistors423and424are shared and connected to a drain terminal of the transistor425. A gate terminal of the transistor425forms the driving current bias terminal VBias. A source terminal of the transistor425is connected to the ground.

The signal VGN1is input to the driving current bias terminal VBias. Depending on the voltage of the signal VGN1, the value of the current that flows through the operational amplifier42is determined. In the power saving mode, the voltage value of the signal VGN1is a value smaller than that during the signal read-out and within a range in which the operational amplifier42is not turned off. Note that, the internal circuit of the operational amplifier45can be constituted by using a similar circuit, and hence description thereof is omitted herein.

FIG. 4is a timing chart for illustrating the operation of the solid-state imaging apparatus of the first embodiment.FIG. 4is an illustration of the operation timing of signals HD, PTN, PTS, PC0R, and PSAVE when three rows of the pixel array1are read out. Note that, it is supposed that every switch to be operated by each signal is turned on when the voltage level of the signal is High, and turned off when the voltage level of the signal is Low. The signal HD is a signal for controlling the timing to start read-out of one row. The signal PSAVE is a signal for changing the voltages of the signals VGN1and VGN1_VF1to switch the power saving mode and the normal read-out state. When the signal PSAVE is Low, the signals VGN1and VGN1_VF1are in a high voltage state, and the solid-state imaging apparatus is set to the normal read-out state. Further, when the signal PSAVE is High, the signals VGN1and VGN1_VF1are in a low voltage state. Thus, the currents (driving currents) to be caused to flow through the operational amplifiers42and45are reduced, and the solid-state imaging apparatus is set to the power saving mode.

At times t0and t8, the signal HD is set to High. When the signal HD is set to High, the read-out of the designated row is started, and hence a period between the times t0and t8corresponds to a read-out period for one row.

At the time t0, the signals PTN and PTS are set to Low, and the signal PC0R is set to High. Therefore, the switches53and54are turned off, and the feedback switch44is turned on. That is, at the point of the time t0, the column amplifier unit4is in a reset state.

At time t1, the signal PC0R is switched from High to Low, and thus the feedback switch44is turned off. With this, the reset of the column amplifier unit4is ended.

During a period between times t2and t5, the reset signal and the image signal are read out from the pixel2. At the time t2, the signal PTN is set to High, and thus the switch53is turned on, to thereby hold the reset signal voltage in the holding capacitor51. At time t3, the signal PTN is set to Low, and thus the switch53is turned off. Next, at time t4, the signal PTS is set to High, and thus the switch54is turned on, to thereby hold the image signal voltage in the holding capacitor52. At the time t5, the signal PTS is set to Low, and thus the switch54is turned off. With this operation, the reset signal and the image signal are read out from the pixel2, and are held in the holding capacitors51and52, respectively.

During a period between times t6and t10, the switches55and56of each column are sequentially turned on by the control signals from the horizontal scanning circuit6. With this, the pixel column is sequentially selected, and the reset signal and the image signal of each column are sequentially output to the horizontal signal lines71and72. During this period, the operational amplifiers42and45of the column amplifier unit4are not used. Therefore, by setting the column amplifier unit4to the power saving mode, power consumption of the operational amplifiers42and45can be reduced.

At the time t6, the signal PC0R is set to High, and thus the feedback switch44is turned on. With this, the inverting input terminal and the output terminal of the operational amplifier45are connected to each other, and the column amplifier unit4is reset. At time t7, the signal PSAVE is set to High, and thus the column amplifier unit4is set to the power saving mode. At time t8, the signal HD is set to High, and thus the next row is selected. It is necessary to restore the column amplifier unit4to the normal read-out state for read-out of the next row. Therefore, at time t9, the signal PSAVE is set to Low, and thus the power saving mode is ended. At the time t10, the signal PC0R is set to Low. Thus, the reset of the column amplifier unit4is ended, and the feedback switch44is turned off.

In the configuration of the solid-state imaging apparatus disclosed in Japanese Patent Application Laid-Open No. 2005-143078, when the charge integrating amplifier is set to the standby state (power saving mode), the voltage at each node of the charge integrating amplifier is indeterminate, and hence the voltage at each node becomes a voltage close to the ground voltage or the power supply voltage due to the leakage current or the like. Therefore, when the charge integrating amplifier is restored to the activation state, a charge/discharge time period for change from the ground voltage or the power supply voltage to the reset voltage is necessary. From such a reason, in the above-mentioned solid-state imaging apparatus, a restoring time period required for the charge integrating amplifier to restore to the normal state from the standby state is long. In contrast, in the configuration of this embodiment, during the period of the power saving mode, the feedback switch of the column amplifier is turned on so that the operational amplifier42has the configuration of the voltage follower. With this, the voltages of all terminals of the operational amplifier42are set to a voltage close to the reference voltage VC0R. That is, during the period of the power saving mode, the voltages of the input/output terminals of the operational amplifier42are fixed to a constant value close to the reference voltage VC0R. Therefore, a charge/discharge time period required for the operational amplifier42to restore to the normal read-out state from the power saving mode is reduced. Note that, the operational amplifier45also has the configuration of the voltage follower, and hence the charge/discharge time period is similarly reduced. Therefore, according to the configuration of this embodiment, in the solid-state imaging apparatus capable of operating in the power saving mode for reducing the power consumption of the column amplifier unit, the time period of restoring to the normal mode from the power saving mode can be reduced.

Second Embodiment

FIG. 5is a block diagram for illustrating a configuration of a solid-state imaging apparatus according to a second embodiment of the present invention. The solid-state imaging apparatus of the second embodiment further includes a second holding circuit8in addition to the configuration of the first embodiment. The second holding circuit8is connected between the column amplifier unit4and the first holding circuit5that have already been described as the first embodiment. The second holding circuit8has a function of holding a signal of the next row, which is read out in parallel, during the horizontal transfer period of outputting the signals from the first holding circuit5to the horizontal signal lines71and72.

FIG. 6is a circuit diagram of the column amplifier unit4, the first holding circuit5, and the second holding circuit8of the second embodiment. The second holding circuit8includes holding capacitors81and82, switches83,84,85, and86, and operational amplifiers87and88. The holding capacitor81, the switches83and85, and the operational amplifier87constitute a circuit for holding the reset signal. The holding capacitor82, the switches84and86, and the operational amplifier88constitute a circuit for holding the image signal.

One terminal of the switch83is connected to the output of the column amplifier unit4. The other terminal of the switch83is connected to one terminal of the holding capacitor81for holding the reset signal and one terminal of the switch85. The other terminal of the holding capacitor81is connected to the ground. The other terminal of the switch85is connected to an inverting input terminal of the operational amplifier87. A reference voltage VCLAMP is input to a non-inverting input terminal of the operational amplifier87. An inverting input terminal and an output terminal of the operational amplifier87are connected to each other via wiring, to thereby constitute a voltage follower circuit. Similarly to the operational amplifiers42and45, a signal VGN1N_VF2is input to a VBias terminal, to thereby control a current to be caused to flow through the operational amplifier87. As described above, the circuit for holding the reset signal is constituted. Note that, the voltage follower circuit to be constituted of the operational amplifier87is merely an example, and the present invention is not limited to this configuration. The function as the buffer circuit is only required similarly to the operational amplifier45.

The circuit for holding the image signal constituted of the holding capacitor82, the switches84and86, and the operational amplifier88has a configuration similar to that of the circuit for the reset signal, and hence the description thereof is omitted herein. The current to be caused to flow through the operational amplifier88is controlled by a signal VGN1S_VF2.

As described above, the currents to be caused to flow through the operational amplifiers87and88can be controlled. In the power saving mode, the voltage values of the signals VGN1N_VF2and VGN1S_VF2are decreased as compared to those during the signal read-out. In this manner, the currents to be caused to flow through the operational amplifiers87and88are decreased, and thus the power consumption is reduced.

Note that, the switches83and84are controlled by the signals PTN and PTS, respectively. Further, both of the switches85and53are controlled by a signal PTN2, and both of the switches86and54are controlled by a signal PTS2. Other control signals are similar to those in the first embodiment.

FIG. 7is a timing chart for illustrating the operation of the solid-state imaging apparatus of the second embodiment.FIG. 7is an illustration of the operation timing of signals HD, PTN, PTS, PTN2, PTS2, PC0R, PSAVE, and VF2_PSAVE. The signal VF2_PSAVE is a signal for switching the power saving mode and the normal read-out state of the operational amplifiers87and88of the second holding circuit8. Now, the operation of the second embodiment is described with reference toFIG. 7. In the following, description of the same operation as the first embodiment may be omitted.

At the time t0, the signal PTN is switched from High to Low, and thus the reset signal voltage is held in the holding capacitor81. At the time t1, the signal PTS is switched from High to Low, and thus the pixel signal voltage is held in the holding capacitor82.

At the time t2, the signal PC0R is set to High, and thus the feedback switch44of the column amplifier unit4is turned on. At the time t3, the signal PSAVE is set to High, and thus the column amplifier unit4is set to the power saving mode.

At the time t4, the signals PTN2and PTS2are switched from High to Low, and thus the transfer of the signals from the second holding circuit8to the first holding circuit5is ended. After that, at the time t5, the signal VF2_PSAVE is set to High, and thus the operational amplifiers87and88of the second holding circuit8are set to the power saving mode.

At the time6, the signal PSAVE is set to Low, and thus the power saving mode of the column amplifier unit4is cancelled. At the time t7, the signal PC0R is set to Low, and thus the feedback switch44of the column amplifier unit4is turned off. At the time t8, the signal VF2_PSAVE is set to Low, and thus the power saving mode of the operational amplifiers87and88of the second holding circuit8is cancelled.

As described above, during the period from the time t1, the operation of the column amplifier unit4, which includes signal output from the second holding circuit8to the first holding circuit5, a pixel reset operation, and the like, is unnecessary. Therefore, the column amplifier unit4is set to the power saving mode during the period between the times t3and t6after the pixel signal voltage is held in the second holding circuit8. At this time, the feedback switch44is turned on at the time t2before the power saving mode is set, and is turned off at the time t6after the power saving mode is cancelled. Thus, similarly to the first embodiment, during the period of the power saving mode, the voltages of the input/output terminals of the operational amplifier42are fixed to a constant value close to the reference voltage VC0R, and the charge/discharge time period required for the solid-state imaging apparatus to restore to the normal read-out state from the power saving mode is reduced. That is, also in the configuration of this embodiment, similarly to the first embodiment, in the solid-state imaging apparatus capable of operating in the power saving mode for reducing the power consumption of the column amplifier unit, the time period of restoring to the normal mode from the power saving mode can be reduced.

Further, in this embodiment, after the writing from the second holding circuit8to the first holding circuit5is ended, a non-use state is maintained until a timing at which the reset signal voltage is next written to the holding capacitor81. Therefore, the operational amplifiers87and88of the second holding circuit8are also set to the power saving mode during a period between the time t5and the time t8. In this case, the operational amplifiers87and88each have a voltage follower configuration in which the inverting input terminal and the non-inverting input terminal are short-circuited. Therefore, the voltages of the input/output terminals of the operational amplifiers87and88are fixed to a constant value close to the reference voltage VCLAMP. Therefore, also in the second holding circuit8, similarly to the first holding circuit5, a charge/discharge time period required for the operational amplifier to restore to the normal read-out state from the power saving mode is reduced.

Third Embodiment

FIG. 8is a circuit diagram of a solid-state imaging apparatus according to a third embodiment of the present invention. The solid-state imaging apparatus of this embodiment includes three input capacitors46,47, and48instead of the input capacitors41, and also includes addition switches94and95. Other configurations are similar to those in the circuit of the first embodiment of the present invention illustrated inFIG. 2. In this embodiment, a circuit formed across the column amplifier unit4and the first holding circuit5for one column corresponding to one pixel column of the pixel array1is called as a “column circuit”.FIG. 8is an illustration of column circuits91,92, and93. The column circuit92is adjacently arranged on the left side of the column circuit arranged at the center, and the column circuit93is adjacently arranged on the right side thereof.

The input capacitor46is connected to the pixel in the center column. The input capacitor47is connected to one terminal of the addition switch94, and the other terminal of the addition switch94is connected to the pixel in the left adjacent column. The input capacitor48is connected to one terminal of the addition switch95, and the other terminal of the addition switch95is connected to the pixel in the right adjacent column. Note that, the same is true for the column circuits in other columns, and the input capacitors are respectively connected to the three pixels of a corresponding column and columns adjacent thereto.

When a signal Add_mode is set to High, the addition switches94and95are turned on, and thus pixel signals of three columns are respectively input to the input capacitors46,47, and48connected to the center column circuit91. With this, the signals of the pixels of the three columns are added. Such a state that the signal Add_mode is set to High for addition is referred to as an “addition mode”.

In the addition mode, it is necessary to operate the operational amplifiers in the center column circuit91to which the signals are input. However, signals are not input to the operational amplifiers in the left and right column circuits92and93, and hence those operational amplifiers are not required to be operated. Therefore, in this embodiment, when the addition mode is used for the operation, the left and right column circuits92and93may be set to the power saving mode, to thereby realize power saving.

Note that, in this embodiment, the control signal for operating the feedback switch44is supplied to the center column and to the left and right columns by different signal lines. The control signal for controlling the feedback switch44of the center column circuit91is represented by a signal PC0R, and the control signal for controlling the feedback switches of the left and right column circuits92and93is represented by a signal PC0R2. Further, the signal for controlling the currents to be caused to flow through the operational amplifiers42and45is also supplied to the center column and to the left and right columns by different signal lines. In this manner, it is possible to operate the center column circuit91in the normal mode, and operate the left and right column circuits92and93in the power saving mode.

The control signals for the operational amplifiers42and45in the center column circuit91are respectively represented by signals VGN1and VGN1_VF1, and the control signals for the operational amplifiers42and in the left and right column circuits92and93are respectively represented by signals VGN2and VGN2_VF1. The signal for controlling the signals VGN2and VGN2_VF1to control switching between the normal mode and the power saving mode is represented by PSAVE2.

FIG. 9is a timing chart for illustrating the operation of the solid-state imaging apparatus of the third embodiment.FIG. 9is an illustration of the operation timing in a case where, in a certain column, the operation transitions from the non-addition mode to the addition mode, and then the operation returns to the non-addition mode again. The center column circuit91carries out the same operation in both cases of the addition mode and the non-addition mode, and hence the signals HD, PTN, PTS, PC0R, and PSAVE to be controlled are operated at the same timing as the first embodiment. The left and right column circuits92and93carry out the same operation as the center column circuit91during the non-addition mode, and are operated at the same timing as the first embodiment as well. Therefore, description of the operation of the cases described above is omitted herein.

On the other hand, the left and right column circuits92and93are operated differently from the first embodiment during the addition mode. At the time t0, the signal PC0R2is set to High, and thus the feedback switch44is turned on. At the time t1, the signal PSAVE2is set to High, and thus the operational amplifier42is set to the power saving mode. At the time t2, the signal Add_mode is set to High, and thus the addition mode is set.

At the time t3, the signal Add_mode is set to Low, and thus the operation returns to the non-addition mode. At the time t4, the signal PSAVE2is set to Low, and thus the power saving mode of the column circuits92and93is cancelled. At the time t5, the signal PC0R2is set to Low, and thus the feedback switch44is turned off.

As described above, in the column circuits92and93, the feedback switch44is turned on during a period from the time t0before the power saving mode is set to the time t5after the power saving mode is cancelled. With this, similarly to the first embodiment, the voltages of the input/output terminals of the operational amplifier42are fixed to a constant value close to the reference voltage VC0R. Therefore, also in the solid-state imaging apparatus that operates in the addition mode for adding the signals of a plurality of columns, a charge/discharge time period required for the column circuits92and93, which are unused during the addition, to restore to the normal read-out state from the power saving mode is reduced. That is, also in the configuration of this embodiment, similarly to the first embodiment, in the solid-state imaging apparatus capable of operating in the power saving mode for reducing the power consumption of the column amplifier unit, the time period of restoring to the normal mode from the power saving mode can be reduced.

Fourth Embodiment

FIG. 10is a circuit diagram of a solid-state imaging apparatus according to a fourth embodiment of the present invention. The solid-state imaging apparatus of this embodiment is obtained by modifying the circuit of the second embodiment into the configuration including the three input capacitors and the addition switches94and95so as to enable an operation in an addition mode similar to that in the third embodiment. Similarly to the third embodiment, column circuits97and98are arranged on the left and right sides of a center column circuit96. When the signal Add_mode is set to High, signals of three columns are input to the column circuit96, and the signals are added. At this time, the left and right column circuits97and98may be set to the power saving mode, to thereby realize power saving. Note that, in this embodiment, a circuit formed across the column amplifier unit4, the first holding circuit5, and the second holding circuit8for one column corresponding to one pixel column of the pixel array1is called as a “column circuit”.

Note that, the control signals for the operational amplifiers87and88in the center column circuit96are respectively represented by signals VGN1N_VF2and VGN1S_VF2, and the control signals for the operational amplifiers87and88in the left and right column circuits97and98are respectively represented by signals VGN2N_VF2and VGN2S_VF2. The signal for controlling the signals VGN2N_VF2and VGN2S_VF2to control switching between the normal mode and the power saving mode is represented by VF2_PSAVE2.

FIG. 11is a timing chart for illustrating the operation of the solid-state imaging apparatus of the fourth embodiment. The operation of the center column circuit96is the same as that in the second embodiment. That is, the signals HD, PTN, PTS, PTN2, PTS2, PC0R, PSAVE, and VF2_PSAVE are operated similarly to the timing chart illustrated inFIG. 7. Further, also in the left and right column circuits97and98, the signals relating to components other than the second holding circuit8are operated at similar timings. Description of those signals is omitted herein.

At the time t2, the signal Add_mode is set to High, and thus the addition mode is set. At this time, the transfer of the signals from the second holding circuit8to the first holding circuit5is already ended, and hence the operational amplifiers87and88are unused. Therefore, at the time t2, the signal VF2_PSAVE2is set to High, and thus the operational amplifiers87and88are set to the power saving mode. After that, at the time t6, the signal VF2_PSAVE2is set to Low, and thus the power saving mode of the operational amplifiers87and88is cancelled.

Also in this embodiment, similarly to the first to third embodiments, the charge/discharge time period required for the operational amplifier to restore to the normal read-out state from the power saving mode is reduced. That is, similarly to the first embodiment, in the solid-state imaging apparatus capable of operating in the power saving mode for reducing the power consumption of the column amplifier unit, the time period of restoring to the normal mode from the power saving mode can be reduced.

In this embodiment, the addition or the like is carried out so as not to read out a part of columns. Thus, it is possible to skip reading of some columns to reduce the number of columns to be read out. When the vertical scanning circuit3vertically scans the pixel array1, it is possible to change the number of columns to be subjected to the read-out for each vertical scanning period. At this time, the column circuit to be subjected to the read-out is operated as normal, and the column circuit not to be subjected to the read-out is not operated. In this driving method, the feedback switch44of the non-operating column circuit is turned on and the power saving mode is set. With this, the power consumption of the column circuit not to be subjected to the read-out is reduced, and the time period of restoring the operation from the power saving mode is reduced.

Note that, in the third and fourth embodiments, a configuration enabling addition of three columns is exemplified, but the number of columns to be added is not limited thereto. A configuration in which a non-operating column is present is only required. That is, the number of columns to be added may be 2, or a plurality of columns such as four columns or more may be added.

Fifth Embodiment

FIG. 12is a diagram for illustrating a configuration of an imaging system according to a fifth embodiment of the present invention. An imaging system800includes an optical unit810, a solid-state imaging apparatus820, an image signal processing unit830, a record/communication unit840, a timing control unit850, a system control unit860, and a reproduction/display unit870. The solid-state imaging apparatus820is a solid-state imaging apparatus having the configuration illustrated in any one of the first to fourth embodiments. The optical unit810, which is an optical system such as a lens, causes light from an object to image on the pixel array1including the plurality of two-dimensionally arrayed pixels2of the solid-state imaging apparatus820, to thereby form an object image.

The solid-state imaging apparatus820outputs, at a timing based on a signal from the timing control unit850, a signal corresponding to the light imaged on the pixel array1. The signal output from the solid-state imaging apparatus820is subjected to processing such as AD conversion, and is then input to the image signal processing unit830. The image signal processing unit830carries out signal processing, such as conversion of the input signal into image data, based on a method determined by a program or the like. The signal obtained by the processing in the image signal processing unit830is transmitted to the record/communication unit840as the image data. The record/communication unit840transmits a signal for forming an image to the reproduction/display unit870, and causes the reproduction/display unit870to reproduce and display a moving image or a still image. The record/communication unit840further receives a signal from the image signal processing unit830, to thereby carry out communication with the system control unit860, and in addition, carry out an operation of recording the signal for forming the image in a recording medium (not shown).

The system control unit860carries out centralized control of the operation of the imaging system800, and controls the drive of the optical unit810, the timing control unit850, the record/communication unit840, and the reproduction/display unit870. Further, the system control unit860includes, for example, a storage device (not shown) that is the recording medium, and a program or the like, which is required for controlling the operation of the imaging system800, is stored in the storage device. Further, the system control unit860supplies, inside the imaging system, a signal for switching the driving mode in accordance with the operation of the user, for example. Specifically, a signal for changing a row to be read out or to be reset, a signal for changing an angle of view in accordance with an electronic zoom, and a signal for shifting an angle of view in accordance with electronic image stabilization are supplied. The timing control unit850controls the timing of driving the solid-state imaging apparatus820and the image signal processing unit830based on the control by the system control unit860.

In the solid-state imaging apparatus820used in this embodiment, the power consumption of the operational amplifier of the read-out circuit is reduced. Therefore, in this embodiment, by mounting the solid-state imaging apparatus820, the imaging system800whose power consumption is reduced can be realized.

This application claims the benefit of Japanese Patent Application No. 2014-165223, filed Aug. 14, 2014, which is hereby incorporated by reference herein in its entirety.