Power saving in a floating point unit using a multiplier and aligner bypass

The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.

TECHNICAL FIELD

The invention relates generally to a floating point unit and, more particularly, to decreasing power consumption in a floating point unit.

BACKGROUND

A floating point unit (FPU) is generally employed as a processor or co-processor for performing calculation intensive manipulations, found in floating point arithmetic, such as addition and multiplication. A first type of FPU has separate units for “multiply” operations and “add” operations. A second type of FPU comprises a single unit which performs both operations. In the FPU, the additive and multiplicative arithmetical operations can be expressed as “A times B plus C,” with “A,” “B” and “C” as separate inputs.

An FPU, such as the second type of FPU, has a large number of circuits. Two of these circuits are the “multiplier” and the “aligner.” Generally, the multiplier inputs two numbers, “A” and “B”, to be multiplied, and outputs two other numbers. The two numbers that are outputted, if added together, equal the multiplication of the first two numbers. The “aligner” circuit generally looks at the exponents of all three operands, and then shifts the fraction of the addend accordingly.

In conventional FPUs, the multiplier creates two values “A1” and “B1” from the inputs “A” and “B.” In other words, A times B equals A1 plus B1. Furthermore, for addition, the aligner is employed to have the added operand, comprising a mantissa and an exponent, to be expressed as the same order of magnitude as the product A times B. In other words, a C value of 3.04×103can be expressed as 3040. Therefore, the FPU generates internal values of A1, B1 and C1, wherein C1 is a compatible order of magnitude to A1 and B1. A1, B1 and C1 are input into a 3:2 adder, and two numbers result, D and E. D and E are added together, the result of which equals A times B plus C. This result is then sent to a normalizer and rounder. Furthermore, in many designs, the FPU is also used for the integer multiply operations, not just on floating point data.

However, employing the FPU in this manner can result in significant power demands, in part due to the extensive calculations performed. These power demands can then generate heat. Heat generated by an FPU can place design and use limitations upon the FPU. Therefore, what is needed is an FPU that solves at least some of the power use and heat generation disadvantages of conventional FPUs.

SUMMARY OF THE INVENTION

The present invention provides for saving power in a floating point unit employing operands of a defined value. Bypass logic is coupled to the input of an aligner and a multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. An adder is coupled to the output of the aligner bypass and the multiplier bypass. In one aspect, clock disable logic is employable to disable the multiplication as a function of the multiplier bypass signal. In another aspect, clock disable logic is employable to disable the aligner as a function of the aligner bypass signal.

DETAILED DESCRIPTION

In the remainder of this description, a processing unit (PU) may be a sole processor of computations in a device. In such a situation, the PU is typically referred to as a CPU (central processing unit). The processing unit may also be one of many processing units that share the computational load according to some methodology or algorithm developed for a given computational device. For the remainder of this description, all references to processors shall use the term PU whether the PU is the sole computational element in the device or whether the PU is sharing the computational element with other PUs.

It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor, such as a computer or an electronic data processor, in accordance with code, such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.

Turning toFIG. 1A, disclosed is a portion of a pipelined FPU100. Generally, clock disable logic (not shown) is employed by the FPU100and dynamically turns on and off stages of an aligner130and a multiplier140. The multiplier140can be a multiplier booth reduction tree. For the FPU100, control logic is employed to parse operation code to determine whether to enable or disable the entire FPU100for a given length of time of computer clock cycles. Furthermore, the control logic parses the operation code and the operands in order to determine whether to enable or disable the various stages of the aligner130and the multiplier140.

Employment of the aligner130is not necessary if the operands are integers, as the “C” value and the “A” and “B” values have the same alignment. Therefore, the aligner does not shift (align) the “C” value, and can therefore be bypassed. The multiplier140is not employed when either the “A” or “B” values are zero (“A times 0 plus C” or “0 times B plus C”). Furthermore, the multiplier140is not employed when performing a unity multiplication (that is, an add operation of A times 1 plus C, which equals A plus C). Instead, the “A,” “B” or “C” values, as appropriate, are bypassed further into the circuit without being processed by their respective input devices, thereby allowing the aligner130or the multiplier140to be disabled for an appropriate number of clock cycles. Disabling the aligner130or the multiplier140in turn saves power. Those of skill in the art understand that the aligner130or the multiplier140can still output a value if one or more stages of the aligner130or the multiplier140is disabled. However, the output value corresponding to the stage that is disabled for the clock cycle is not further employed by the FPU100.

The FPU100has three inputs. These are input “A,” input “B,” and input “C,” which correspond to the form “A times B plus C.” Inputs A and B are input into latch120, and input C is input into latch110. From the latch120, input values “A” and “B” are input into a 2:2 multiplier140. The output of the multiplier140is expressed as values “A1” and “B1,” which are input into the multiplier bypass173. Input “C” is input into the aligner130. The output of the aligner130is input into an aligner bypass174.

However, inputs “A” and “C” are also input into a bypass logic135. InFIG. 1, the output of the bypass logic135is input as signal “C3” into the aligner bypass174, and is also input as signal “A3” into the multiplier bypass173.

The bypass logic135also gets input signals “zero_a,” “zero_b” and “zero_c,” as illustrated inFIG. 1. These input signals indicate whether any of the floating-point operands of “A,” “B” or “C” are zero. Generally, a value of zero for any of these operands indicates that either the aligner130, the multiplier140, or both, are not to be employed for that computation, thereby saving power.

Depending on the operation and upon whether the “zero_a”, “zero_b” or “zero_c” condition is met, differing A3 or C3 values are transmitted into the aligner bypass174or the multiplier bypass173. The relations between the various inputs are disclosed in the following table. DC stands for the “do not care” state (that is, the output “A3” or “C3” does not matter because the output will not be used by either the aligner bypass174or the multiplier bypass173).

In the above table, if an integer operation is employed, in other words, if the “A”, “B” and “C” values are integers, the aligner bypass signal is active and the input C value is then forwarded as signal “C3” directly down to the aligner bypass174. However, the multiplier140is enabled by an inverted multiplier bypass signal, and the A3 value from the bypass logic135is not employed by the multiplier bypass unit.

In case of a floating point add/sub type “A*1+C”, if both the “C” input and the “A” input are zero, then both the “C3” and “A3” values are forced to zero, and both of these values are demultiplexed and employed by the aligner bypass174and the multiplier bypass173, respectively, and transmitted to the 3:2 adder160. Therefore, both the aligner130and the multiplier140are disabled for this operation by the aligner bypass signal and the multiplier bypass signal, respectively.

For a floating point add/sub of type “A*1+C”, if “C” is zero, but “A” is non-zero, zero is forwarded to and employed by the aligner bypass as value “C3,” and the “A3” value from the bypass logic135is employed by the multiplier bypass unit173. The multiplier bypass signal is active; thus, the multiplier is disabled, and the value “A3” is passed to the “A2” input of the 3:2 adder. The “B2” value is forced to zero using the demultiplexor177. The inputs “C2,” “A2” and “B2” of the 3:2 adder160then add up to the value “A.”

For a floating point add/sub type A*1+C, if “C” is non-zero, but “A” is zero, then the aligner and multiplier bypass signals are both active. The “C” value is passed down to the “C3” input of the aligner bypass174. The “A3” value is forced to zero and passed to “A2”; “B2” is also forced to zero. The aligner and multiplier are both disabled.

For a floating point add/sub type A*1+C, if both the “C” value and the “A” value are non-zero, then both the multiplier bypass173and the aligner bypass174employ signals “A1,” “B1” and “C1,” respectively. In other words, both the aligner130and the multiplier140are employed and powered for this operation, as a function of the aligner bypass and multiplier bypass signals.

In the case of a floating point multiply-add type A*B+C, the output of the bypass logic depends upon the inputs of A, B and C. If C is zero and the product is zero (that is, A or B is zero or both A and B are zero), the bypass logic135forces both outputs C3′ and A3 to zero. The aligner and multiplier bypass signals are active; that is, the aligner bypass passes C3 to output C2, the multiplier bypass passes A3 to A2 and forces B2 to zero. The aligner130and the multiplier140are turned off.

In the case of a floating point multiply-add type A*B+C, if C is zero, and A and B are non-zero, the bypass logic135forces output C3 to zero, and the value A3 does not matter. The aligner bypass signal is active; that is, the aligner130is turned off and the C3 value passes to C2. The multiplier bypass signal is inactive; that is, the multiplier140is active and the multiplier bypass passes A1 and B1 to A2 and B2.

In the case of a floating point multiply-add type A*B+C, if C is non-zero but the product is zero, the bypass logic135passes C to output C3 and forces A3 to zero. Both the aligner bypass signal and the multiplier bypass signal are active; that is, the aligner130and the multiplier140are turned off, C3 is passed to C2, A3 is passed to A2, and B2 is forced to zero.

In the case of a floating point multiply-add type A*B+C, if all three operands are non-zero, the bypass logic135is turned off, and the aligner130and the multiplier140are active. The aligner bypass174passes the output C1 to C2, and the multiplier140passes the multiplier results A1 and B1 to A2 and B2.

Furthermore, in a further embodiment, the bypass logic135itself can be selectively enabled or disabled by the aligner bypass and the multiplier bypass signals. If either of these signals are positive, the bypass control is enabled. Otherwise, the bypass control135is disabled.

The aligner bypass174comprises a demux. The aligner bypass174accepts an aligner bypass signal to determine whether to transmit the C1 value, received from the aligner130, to the 3:2 adder160, or whether to transmit the signal C3 to the 3:2 adder160. When the C3 value in Table 1 is a “DC” value, the aligner bypass signal equals “zero” and the value of C1 is transmitted as signal C2 from the aligner130to the adder160. When the C3 value in Table 1 is not a DC value, the aligner bypass signal equals “one” and the value of C3 is transmitted as signal C2 from the aligner bypass174to the adder160.

The multiplier bypass173comprises a demux175and a demux177. The demux175receives inputs A3 and A1, and the demux177receives input B1 and “0.” Demux175forwards the A3 value to the adder160as signal A2 if A3 is not a DC value, as indicated by the multiplier bypass signal (in other words, if the aligner bypass signal is equal to “one”). Otherwise, the A1 value is forwarded as A2 from the multiplier bypass173when the multiplier bypass signal equals zero. In other words, when the A3 value of Table 1 is a “DC,” the value of A1 is selected by the multiplier bypass signal to be transmitted as signal A2 to the adder160.

The demux177of the multiplier bypass173also employs the multiplier bypass signal. The multiplier bypass signal equals “0,” and the demux177transmits value B1 as B2 to the 3:2 adder160when the A3 value of Table 1 is a “DC.”However, if the A3 value of Table 1 is “0,” the multiplier bypass signal is a “1” and the value of “0” is instead chosen to be transmitted as signal B2 by the demux177to the adder160. By the transmittal of both of these values, the numbers of “0” are transmitted to the adder160for both A2 and B2.

In the case that either “A” or “B” equals a value of floating point “1.0 . . . ”, the multiplier bypass signal still enables the transmission of values A1 and B1 as A2 and B2 from the multiplier bypass173. However, as is understood by those of skill in the art, in an FPU, the sum of the A1 and B1 values generated by the multiplier140equals “A times B.” Therefore, the multiplier140is enabled for this unity multiplication, and no bypass occurs.

In one embodiment, the operand can be detected early enough that the operand “A” or “B” of a floating point multiply add type operation equals “1.0”. In that case, the multiplier140can be disabled. The operand which is not 1.0 is input to the bypass logic135as “A,” and passed to the multiplier bypass173as “A3.” The multiplier bypass signals equals “1”.

In a further embodiment, in the case of addition or subtraction (A+C or A−C, for example), the B operand could be evaluated as1.0. In this case, the multiplier bypass signal is generated and A is used, and B2 is forced to zero using the demultiplexor177. This can be done by checking the opcode.

The values of the C2, A2 and B2 are transmitted to the adder160. From the adder160, values D and E are input into a 2:1 reduction adder190, such that A2 plus B2 plus C2 equals D plus E. From the adder190, the output is transmitted.

Generally, employment of the aligner bypass signal, the multiplier bypass signal, and the bypass logic135allow for the selective and dynamic disablement of the aligner130and the multiplier140as a function of the operands to be processed, thereby saving power.

Turning now toFIG. 1B, disclosed is the portion of the FPU100, wherein the bypass logic135comprises two stages. The first stage is a demultiplexor (demux)170, the output of which is input, as signal “F”, into the late correction for zero logic150. In some embodiments, the signals zero A, zero B and zero C are not available early enough to control the first stage of bypass logic. Thus, the correction for zero operands must be delayed. The demux170selects between the “A” and “C” value based on an aligner Csel, which depends on the type of operation performed. The “A” value is only selected in case of a floating point add/sub operation. The second stage170then passes the value “F” to its outputs “C3” and “A3”, or forces one or both of its outputs to zero depending on the input signals zero A, zero B and zero C. This covers all the cases listed in Table 1 except for the addition A+C, where A is zero and C is non-zero. For a floating point add/sub type “A*1+C” with zero A operand and non-zero C operand, the aligner bypass is disabled, and the aligner is powered on and aligns the “C” operand, which is then passed as “C1” to the C2 input of the reduction adder160. The multiplier is disabled, the multiplier bypass is enabled, and the A2 and B2 values are forced to zero, using the bypass logic135and the multiplier bypass173.

Turning now toFIG. 2, depicted is an FPU having an aligner circuit230, a bypass logic250, a clock disable logic201, and a multiplier circuit240. Generally, the clock disable logic201employs the aligner bypass signal and the multiplier bypass signal to selectively and dynamically enable and disable stages of the aligner230and the multiplier240, thereby saving power. InFIG. 2, both the laches234and253of the clock disable logic201are powered by a clock, and are themselves not disabled (except when the whole FPU is turned off (hardware not shown)), so as to ensure that the appropriate stages of the bypass logic250, the aligner230and the multiplier240are dynamically enabled and disabled for the appropriate clock cycles.

InFIG. 2, the bypass logic250has a first stage logic220, a latch231, a second stage logic240, and a latch251. The demux170and the corrector150are generally distributed between the logic220and logic240.

The aligner bypass and the multiplier bypass signals are input into a bypass signal generator212. With the next clock cycle, if either the aligner bypass signal or the multiplier bypass signal are a “1” (in other words, either the aligner bypass signal or the multiplier bypass signal are enabled), a signal is sent from the OR gate282that enables latch231, thereby allowing the bypass logic250to function for that clock cycle. Because the bypass logic250is employed when either the aligner bypass signal or the multiplier bypass signal are equal to “1,” the bypass unit is powered on for the requisite number of clock cycles, thereby saving power. Similar enabling/disabling signals are made from the output of latch254to the latch251for the next cycle. If both the bypass signals are off, latch231is disabled, disabling that stage of the bypass logic250, thereby saving power for that clock cycle.

InFIG. 2, the aligner230has a first stage logic222, a latch232, a second stage logic242, a latch252, and a third stage logic257. The aligner signal of the clock disable logic201is inverted by an inverter and input into the aligner230via the latch232. In other words, if the aligner bypass is “1” (that is, an aligner bypass), this signal is inverted, and is then employed to disable the latch232. If the aligner bypass signal is “0” (that is, no aligner bypass), the signal is inverted to “1” and the latch232is enabled. Similar enabling/disabling signals are made from the latch253to the latch252for the next clock cycle.

InFIG. 2, the multiplier240has a first stage logic224, a latch236, a second stage logic246, a latch254, and a third stage logic258. The multiplier bypass signal of the clock disable logic201is inverted by an inverter and input into the multiplier240via the latch236. In other words, if the multiplier bypass is “1,” this signal is inverted, and then is employed to disable the latch236. If the multiplier bypass signal is “0” (that is, no bypass), the signal is inverted to “1” and the latch236is enabled. Similar enabling/disabling signals are made from the output of latch234to the latch254for the next clock cycle.

Generally, employment of the aligner bypass signal, the multiplier bypass signal, the clock disable logic201and the bypass logic135allow for the selective and dynamic disablement of the aligner130and the multiplier140as a function of the operands to be processed, thereby saving power. Generally, the clock disable logic201dynamically enables and disables latches in the aligner230, the multiplier240, and the bypass logic250.

Turning now toFIG. 3, illustrated are the inputs and outputs of a bypass signal generator212. The bypass signal generator receives opcode and a signal representing whether “A” operand, “B” operand and “C” operand are equal to zero (the “zero_A,” “zero_B” and “zero_C” values). These are processed by the bypass signal generator to generate the aligner bypass signal and the multiplier bypass signal.

It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built.