Vertical emitters with integrated final-stage transistor switch

An integrated emitter device incudes a silicon die, including an array of control circuits, and a plurality of integrated emitter modules disposed on the silicon die. Each integrated emitter module includes a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which define a vertical emitter including an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer, and a transistor in series with the vertical emitter and including a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal applied to the terminal by the respective one of the control circuits.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, and particularly to optoelectronic devices and methods for their manufacture.

BACKGROUND

In conventional, top-emitting optoelectronic devices, such as vertical-cavity surface-emitting lasers (VCSELs), the semiconductor substrate serves not only as the base for fabrication of the emitters, but also as the mechanical supporting carrier of the emitter devices after fabrication. The terms “top” and “front” are used synonymously in the present description and in the claims in the conventional sense in which these terms are used in the art, to refer to the side of the semiconductor substrate on which the VCSELs are formed (typically by epitaxial layer growth and etching). The terms “bottom” and “back” refer to the opposite side of the semiconductor substrate. These terms are arbitrary, since once fabricated, the VCSELs will emit light in any desired orientation.

Bottom-emitting VCSEL devices are also known in the art. In such devices, after fabrication of the epitaxial layers on a wafer substrate (typically a III-V semiconductor wafer, such as a GaAs wafer), the substrate is thinned away below the emitting bottom surfaces of the VCSELs. The top surfaces are typically attached to a heat sink, which can also provide mechanical support.

In some applications, an array of VCSELs is integrated with control circuits in a single chip by bonding together a III-V semiconductor substrate on which the VCSELs are fabricated with a silicon substrate on which control circuits for the VCSELs are fabricated. For example, PCT International Publication WO 2018/053378, whose disclosure is incorporated herein by reference, describes a method for manufacturing that includes fabricating an array of vertical emitters by deposition of multiple epitaxial layers on a III-V semiconductor substrate, and fabricating control circuits for the vertical emitters on a silicon substrate. Respective front sides of the vertical emitters are bonded to the silicon substrate in alignment with the control circuits. After bonding the respective front sides, the III-V semiconductor substrate is thinned away from respective back sides of the vertical emitters, and metal traces are deposited over the vertical emitters to connect the vertical emitters to the control circuits.

SUMMARY

Embodiments of the present invention that are described hereinbelow provide improved optoelectronic devices and methods for their production.

There is therefore provided, in accordance with an embodiment of the invention, an integrated emitter device, including a silicon die, which an array of control circuits, and a plurality of integrated emitter modules disposed on the silicon die. Each integrated emitter module includes a single epitaxial stack including multiple layers of III-V semiconductor compounds, which define a vertical emitter including an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer, and a transistor in series with the vertical emitter and including a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal applied to the terminal by the respective one of the control circuits.

In a disclosed embodiment, the transistor includes a heterojunction bipolar transistor (HBT). Alternatively, the transistor includes a bipolar junction transistor (BJT).

In one embodiment, the transistor includes a base, a collector, and an emitter, all of which are outside a cavity defined by the upper and lower DBRs. Alternatively, the base and the collector are disposed over the upper DBR, outside a cavity of the vertical emitter, while the emitter of the transistor is disposed between the optically active layer and one or more of the layers of the upper DBR.

In a disclosed embodiment, the optically active layer includes quantum wells. Additionally or alternatively, the vertical emitter is configured as a vertical-cavity surface-emitting laser (VCSEL).

In some embodiments, the vertical emitter in each of the integrated emitter modules includes a III-V semiconductor substrate, wherein the lower DBR is disposed on the substrate, the optically active layer is disposed over the lower DBR, and the upper DBR is disposed over the optically active layer, and wherein the vertical emitter is configured to emit optical radiation through the III-V semiconductor substrate when the control signal is applied to the terminal of the transistor. In a disclosed embodiment, the terminal of the transistor is bonded to a contact on the silicon die, whereby the vertical emitter emits the optical radiation through the III-V semiconductor substrate in a direction away from the silicon die.

There is also provided, in accordance with an embodiment of the invention, a method for manufacturing, which includes fabricating an array of control circuits on a silicon die. A plurality of integrated emitter modules are fabricated, each integrated emitter module including a single epitaxial stack including multiple layers of III-V semiconductor compounds, which define a vertical emitter including an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer, and a transistor in series with the vertical emitter and including a terminal. The terminal of the transistor in each of the integrated emitter modules is bonded to a respective one of the control circuits, whereby the vertical emitter is actuated in response to a control signal applied to the terminal by the respective one of the control circuits.

DETAILED DESCRIPTION OF EMBODIMENTS

In some integrated emitter devices, such as those described in the above-mentioned PCT International Publication WO 2018/053378, an array of vertical emitters, such as VCSELs, is bonded to a silicon substrate containing control and driver circuits for the emitters. For high output power and versatile wavelength selection, the emitters are typically made from a III-V semiconductor compound. The control circuits on the silicon substrate enable precise, individual control of the emitters in the array.

High-power pulsed emitters draw substantial peak currents during operation, at relatively high voltage. For example, a VCSEL emitting short, intense pulses may draw a peak current greater than 30 mA at a voltage of 4-5 V. To satisfy these needs, the control circuit for the emitter should have a high-power, high-voltage output stage, with a voltage supply in the range of 8 V or more to cover switching losses and other parasitics. Meeting these needs in control circuits that are implemented in CMOS logic on the silicon wafer generally calls for a large final-stage transistor with a large driver capacitor, operating at a high voltage that is outside the conventional CMOS operating range.

Embodiments of the present invention that are described herein address these difficulties by integrating a transistor in series with the vertical emitter, in the same III-V epitaxial stack as the vertical emitter. This transistor serves as the output stage in the drive circuit, thus obviating the need for a large final-stage transistor in the silicon control circuits and reducing the overall size, voltage, and power requirements of the control circuits. As a result, the silicon control circuits can operate at much lower voltage and power levels, for example at a standard voltage of 1-1.5 V and a base current of 100-200 μA.

In the disclosed embodiments, multiple integrated emitter modules implementing this principle are disposed on a silicon die comprising an array of control circuits. Each of these integrated emitter modules comprises a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which are deposited and patterned to define a vertical emitter and a transistor in series with the vertical emitter. The vertical emitter comprises an optically active layer, such as a quantum well layer, with upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer. One of the terminals of the transistor is mounted in electrical contact with a respective control circuit on the silicon die. To actuate the vertical emitter, the control circuit applies a control signal to the terminal, causing current to flow through the transistor, which then drives the vertical emitter to emit radiation.

In a disclosed embodiment, the III-V transistor comprises a heterojunction bipolar transistor (HBT), for example a GaAs HBT. Such transistors have high gain and fast frequency response, and thus can drive the vertical emitters to emit short, high-power optical pulses with sharp rising and falling edges. Because the HBT is current-controlled, it also obviates the need for a large driver capacitor in the silicon control circuit. Alternatively, for applications with lower power and speed requirements, the III-V transistor may comprise a bipolar junction transistor (BJT), made from a single semiconductor material with suitable doping of the regions of the transistor.

FIG.1is a block diagram that schematically illustrates an integrated emitter array device20, in accordance with an embodiment of the invention. Device20comprises a silicon die28, on which an array of control circuits30is formed. For the sake of simplicity, control circuits30are represented as switches, typically made from suitable CMOS transistors, which are controlled via a bus38by timing control logic32. Alternatively, more complex control circuits and topologies may be used.

A III-V semiconductor stamp22is bonded to silicon die28, in alignment with control circuits30. Stamp22may be produced by depositing and etching a stack of epitaxial layers on a III-V wafer, such as a GaAs wafer, as is described further hereinbelow. Stamp22in the pictured example comprises multiple integrated emitter modules34, each aligned with a respective control circuit30. Alternatively, each integrated emitter module on device20may be contained on a separate stamp. Each integrated emitter module34comprises a single epitaxial stack, comprising multiple layers of III-V semiconductor compounds, which define a vertical emitter, such as a VCSEL24, and a bipolar transistor26, such as an HBT, in series with the vertical emitter. In alternative embodiments, integrated emitter modules34may comprise other types of vertical emitters, such as resonant-cavity light-emitting diodes (RCLEDs).

One of the terminals of each transistor26, such as the base terminal, is in contact with a respective control circuit30. To actuate a given VCSEL26, timing control logic32(which may also be implemented on silicon die28) transmits a control pulse to the respective control circuit30via bus38. In response to the control pulse, control circuit30applies a control signal to the terminal of transistor26, which causes the corresponding VCSEL24to output a light pulse.

FIG.2is an electrical circuit diagram that schematically illustrates integrated emitter module34and an associated control circuit42, in accordance with an embodiment of the invention. Control circuit42is implemented on silicon die28and comprises a drive transistor46, such as an NMOS transistor in the present example. Drive transistor46is connected to the base terminal of bipolar transistor26in emitter module34, while the collector and emitter of transistor26are connected to the cathode of VCSEL24and to ground, respectively. The anode of VCSE24is connected to a positive drive voltage VDR. When transistor46receives an input pulse, it applies a voltage pulse to the base of transistor26, causing current to flow through emitter module34and thus actuating VCSEL24to emit a pulse of optical radiation.

Alternatively, other configurations of integrated emitter module34may be used. For example, the emitter of transistor26may be grounded, and a negative drive voltage applied to the cathode of VCSEL24. As another alternative, although transistor26is shown in the figures as an NPN device, this transistor may alternatively be implemented as a PNP device, with appropriate changes to the other elements of emitter module34and control circuit42. Although an HBT is advantageous in conveying high currents with fast frequency response, transistor26may alternatively comprise other types of bipolar junction transistors.

Similarly, the components of control circuit42may be replaced by other suitable sorts of silicon circuit components, including various sorts of bipolar CMOS (BiCMOS) circuit designs that are known in the art.

Reference is now made toFIGS.3A and3B, which schematically show details of emitter module34, including VCSEL24and transistor26, in accordance with an embodiment of the invention.FIG.3Ais a sectional view, whileFIG.3Bis a top view.

Emitter module34comprises a III-V semiconductor substrate48, for example a GaAs wafer. A lower distributed Bragg reflector (DBR)50comprises a stack of epitaxial layers of semiconductor compounds with alternating high and low refractive indexes, deposited on substrate48. An optically active layer52, comprising multiple quantum wells, for example, is deposited over lower DBR50, along with an oxide aperture56. An upper DBR54, similarly comprising a stack of epitaxial layers of semiconductor compounds with alternating high and low refractive indexes, is deposited over optically active layer52. In the present example, it is assumed that upper DBR54is n-doped, while lower DBR50is p-doped; but alternatively, other doping schemes may be used. When actuated by transistor26(in response to the control signal from control circuit42), VCSEL24emits optical radiation74through substrate48.

Transistor26comprises a set of epitaxial layers of semiconductor compounds, deposited over upper DBR54, to define an emitter58, a base62, and a collector60. In the present example, transistor26is configured as an NPN device, meaning that emitter58and collector60are n-doped, while base is p-doped. Alternatively, the doping may be reversed, so that transistor26is a PNP device (in which case, upper DBR54may be p-doped, while lower DBR50is n-doped). A base terminal64is deposited over base62and is bonded to a contact on silicon die28, so that VCSEL24will emit optical radiation74through substrate48in a direction away from the silicon die. A collector terminal66is deposited over collector60and connects via a conducting metal layer68to the drive voltage (as shown inFIG.2). Passivation layers70and72are formed over the mesa of emitter module34, on the inner and outer sides of metal layer68, respectively.

Reference is now made toFIGS.4A and4B, which schematically show details of an emitter module80, including a VCSEL82and transistor84, in accordance with an alternative embodiment of the invention.FIG.4Ais a sectional view, whileFIG.4Bis a top view. Most of the components of emitter module80are similar to those of emitter module34(FIG.3A/B) and are thus labeled with the same indicator numbers. In emitter module80, however, while base62and collector60of transistor84are deposited over upper DBR54, outside the cavity of VCSEL82, an emitter86of the transistor is deposited between optically active layer52and one or more of the layers of upper DBR54. This configuration adds resistance (due to the layers of upper DBR54) within transistor84and can thus be advantageous in circuit configurations in which such higher resistance is desirable.

FIGS.5A-5Iare schematic sectional views illustrating stages in fabrication of an integrated emitter array, in accordance with an embodiment of the invention. The result of this fabrication process, shown inFIG.5I, is a stamp22comprising an array of integrated emitter modules34. In describing this process, transistor26in module34is assumed to be an HBT. The process may be modified, mutatis mutandis, to form BJTs of other types.

The process begins with sequential deposition of lower DBR50, oxide aperture56, optically active layer52, and upper DBR54on III-V semiconductor substrate48, as shown inFIG.5A. Additional epitaxial layers are deposited to form emitter58, base62, and collector60, as shown inFIG.5B. Transistor26is then patterned by etching through an appropriate area of collector60to expose base62, as shown inFIG.5C.

Trenches90are etched through the epitaxial layers of transistor26and VCSEL24to create an array of mesas92, as shown inFIG.5D. (Only a single mesa is shown inFIGS.5D-5Ifor the sake of simplicity.) Alternatively, other, more complex mesa geometries may be created. Passivation layer70is formed over mesa92, for example by a suitable oxidation process, as shown inFIG.5E. Openings are etched through passivation layer70and then filled with metal, for example by deposition of a copper layer, to form base terminal64and collector terminal66, as shown inFIG.5F. Metal layer68is deposited over passivation layer70to connect collector terminal66to a drive voltage line94on substrate48, as shown inFIG.5G. Passivation layer72is then deposited over metal layer68, to isolate collector terminal66while leaving base terminal64exposed, as shown inFIG.5H.

Substrate48is thinned and diced to create stamps22, which are then flipped and bonded to respective silicon dies28, as shown inFIG.5I. (This step may be carried out before or after the silicon wafer is diced to create die28.) Base terminal64is connected to the respective control circuit on silicon die28, for example by a solder bump94or any other suitable type of conductive bond.