Device and method for protecting FEOL element and BEOL element

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

BACKGROUND

The present disclosure generally relates to semiconductor devices, and specifically relates to a device and method for protecting front-end-of-the-line (FEOL) elements and back-end-of-the-line (BEOL) elements.

FEOL elements are individual elements, e.g., transistors, diodes, resistors, which formed on the first portion of integrated circuit (IC) fabrication. BEOL elements are wiring elements which formed on the second portion of IC fabrication where the individual elements get interconnected with wiring on the IC wafer. More specifically, after the last FEOL process, there is a wafer with isolated elements (without any wires). In BEOL processes, contact pads, interconnect wires, vias and dielectric structures are formed to connect those isolated elements.

Complementary metal-oxide-semiconductor (CMOS) technology is the predominant fabrication technology for integrated circuit (IC). As technology advances, micro electromechanical system (MEMS) can be attached to a CMOS wafer to form a CMOS-MEMS device. Merely by way of example, the CMOS-MEMS device may include an accelerometer, a pressure sensor, an angular sensor, a microphone and others, and these micro devices include many advantages, such as low power consumption, short response time, and low drive voltage. However, while the size of the CMOS-MEMS device decreases, the FEOL elements and BEOL elements are apt to suffer from process damage, causing low yield in fabricating the CMOS-MEMS device.

DETAILED DESCRIPTION

A Complementary metal-oxide-semiconductor (CMOS)-micro electromechanical system (MEMS) device and method of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the CMOS-MEMS device are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1throughFIG. 8are cross-sectional views of intermediate stages in the manufacturing of a package including a CMOS-MEMS device in accordance with a first embodiment of the present disclosure. InFIG. 1, a semiconductor substrate100is provided. The semiconductor substrate100may be a silicon substrate or a semiconductor substrate formed of other semiconductor materials. In some embodiments, the semiconductor substrate100is lightly doped with a p-type impurity, but the present disclosure is not limited thereto.

As shown inFIG. 1, a plurality of front-end-of-the-line (FEOL) elements102are formed on the surface100aof the semiconductor substrate100. In some embodiments, the FEOL elements102may include transistors, resistors, diodes, CMOS devices, etc, but the present disclosure is not limited thereto.

InFIG. 2, a plurality of dielectric layers110a,110b,110cand110dare formed on the semiconductor substrate100in sequence. Furthermore, metal lines111, and vias112are formed in the dielectric layers110a,110b,110cand110d. The back-end-of-the-line (BEOL) elements114include the metal lines111and the vias112disposed in the dielectric layers110a,110b,110cand110d. In various embodiments, the BEOL elements114include capacitors, such as metal-insulator-metal (MIM) capacitors or metal-oxide-metal (MOM) capacitors, etc, but the present disclosure is not limited thereto. Furthermore, after forming the BEOL elements114, the formation of a CMOS wafer110that includes the FEOL elements102and the BEOL elements114is approximately finished. The BEOL elements114and the FEOL elements102are able to communicate with some other devices, such as a micro electromechanical system (MEMS) device, and to transmit or receive signals from the MEMS device.

With reference made toFIG. 2, a first interconnect structure118is formed through the dielectric layers110a,110b,110cand110d. The first interconnect structure118includes a plurality of metal lines118aand vias118b. For example, inFIG. 2, after forming the dielectric layer110aon the semiconductor substrate100, an opening is formed in the dielectric layer110aby, for example, lithography and etching. Thereafter, a conductive material is filled in the opening by, for example, a deposition process. Through filling the conductive material in the opening, the via118bin the dielectric layer110ais formed. Then, the metal line118ais formed on the dielectric layer110aand the via118b. Similarly, the dielectric layer110bis formed on the dielectric layer110a, and an opening is formed in the dielectric layer110bto expose at least a part of the metal line118aformed on the dielectric layer110a. Thereafter, a conductive material is filled in the opening of the second dielectric layer110bto form the via118bin the dielectric layer110b. The rest can be done in the same manner. As a result, the resultant first interconnect structure118shown inFIG. 2is formed.

In various embodiments, the dielectric layers110a,110b,110cand110dcan be made of any organic or inorganic dielectric material. The dielectric layers110a,110b,110cand110dcan be formed by, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), chemical solution deposition, spin-on coating, evaporation, and the like. In some embodiments, the metal lines111and the vias112of the BEOL elements114, and the metal lines118aand the vias118bof the first interconnect structure118can be made of a conductive material, such as Cu, Al, Ta, TaN, W or alloys and silicides thereof. The metal lines111and the vias112of the BEOL elements114, and the metal lines118aand the vias118bof the first interconnect structure118can be formed by a deposition process, such as sputtering, plating, CVD, PECVD, evaporation, and the like.

With reference made toFIG. 2, a conductive shielding layer116is formed on the dielectric layer110d. Furthermore, the conductive shielding layer116is electrically connected to a ground contact119. The ground contact119is a contact portion on the surface100aof the semiconductor substrate100and in contact with the first interconnect structure118, and the conductive shielding layer116is electrically connected to the semiconductor substrate100through the first interconnect structure118and the ground contact119. In various embodiments, the ground contact119is grounded.

With reference made toFIG. 2, the conductive shielding layer116at least covers the FEOL elements102and the BEOL elements114, so as to protect the FEOL elements102and the BEOL elements114from some process damages. More specifically, during the etching, grinding or chemical-mechanical planarization (CMP) process, charges (such as electrons) may be accumulated on the conductive shielding layer116if the conductive shielding layer116is not electrically connected to the ground contact119. The accumulated charges may cause damage to the FEOL elements102and the BEOL elements114. For example, the accumulated charges may result in electromigration (EM) damage to the FEOL elements102and the BEOL elements114, causing unexpected shorts or opens to the FEOL elements102or the BEOL elements114.

More specifically, the effect of electromigration damage becomes a concern as the size of the FEOL elements102and the BEOL elements114decreases. That is, as the structure size in the FEOL elements102and the BEOL elements114decreases, the risk of occurrence of the electromigration damage increases. For example, when the electromigration damage happens on the BEOL elements114, the shape of the metal lines111and/or the vias112of the BEOL elements114may be deformed, thereby causing unexpected shorts or opens to the BEOL elements114. Therefore, in various embodiments, the conductive shielding layer116at least covers the FEOL elements102and the BEOL elements114. That is, an orthogonal projection of the conductive shielding layer116on the semiconductor substrate100overlaps with an orthogonal projection of the FEOL elements102on the semiconductor substrate100, and the orthogonal projection of the conductive shielding layer116on the semiconductor substrate100overlaps with an orthogonal projection of the BEOL elements114on the semiconductor substrate100. As a result, by electrically connecting the conductive shielding layer116to the semiconductor substrate100through the ground contact119, the conductive shielding layer116is grounded, and the accumulated charges, if any, are conducted to the semiconductor substrate100. Therefore, the risk of causing unexpected shorts or opens to the FEOL elements102or the BEOL elements114is eliminated.

In various embodiments, the conductive shielding layer116is made of a conductive material, such as Cu, Al, Ta, TaN, W or alloys and silicides thereof. The conductive shielding layer116is formed on the dielectric layer110dby a deposition process, such as CVD, PECVD, evaporation and the like.

InFIG. 3, an inter-layer dielectric (ILD) layer130is formed on the CMOS wafer110. More specifically, the ILD layer130is formed on the dielectric layer110dto cover the conductive shielding layer116and other metal layers117formed on the dielectric layer110d. The ILD layer130is patterned to form a plurality of openings132and a first cavity C1. The openings132and the first cavity C1expose at least a part of the conductive shielding layer116and the metal layers117, so that the CMOS wafer130can be connected to a MEMS wafer through the openings132, the first cavity C1, and the metal layers117.

The ILD layer130is made of any organic or inorganic material. The first cavity C1and openings132are formed by, for example, lithography and etching. Since the conductive shielding layer116covers the BEOL elements114and the FEOL elements102, and the conductive shielding layer116is electrically connected to the semiconductor substrate100, the conductive shielding layer116can protect the BEOL elements114and the FEOL elements102from the process damages because of etching the ILD layer130.

InFIG. 4, a MEMS wafer140is formed on the ILD layer130. The MEMS wafer140may be a silicon wafer. More specifically, the MEMS wafer140may be free from active devices, such as transistors therein, and may be, or may not be, free from passive devices, such as resistors, capacitors, and inductors therein.

InFIG. 5, the MEMS wafer140is then patterned by an etching process to form openings141and MEMS devices142. In the embodiment ofFIG. 5, the MEMS devices142may include at least one movable element143and springs144for supporting the movable element143. In some embodiments, the MEMS devices142may include other MEMS features. The MEMS devices142are aligned with the cavity C1formed in the ILD layer130, so that the movable element143of the MEMS devices142can move in the cavity C1.

Since the conductive shielding layer116covers the BEOL elements114and the FEOL elements102, and the conductive shielding layer116is electrically connected to the semiconductor substrate100, the conductive shielding layer116can protect the BEOL elements114and the FEOL elements102from the process damages because of etching the MEMS wafer140.

InFIG. 6, the MEMS wafer140is electrically connected to the CMOS wafer110. More specifically, a conductive material is filled in some of the openings141by, for example, a deposition process. Through filling the conductive material in some of the openings141, a plurality of second interconnect structures147are formed to electrically connect to the CMOS wafer110. Furthermore, one of the second interconnect structures147is electrically connected to the conductive shielding layer116formed in the CMOS wafer110. Since one of the second interconnect structures147is electrically connected to the conductive shielding layer116, the charges accumulated on the surface of the MEMS wafer140can be conducted to the semiconductor substrate100as well.

More specifically, the MEMS wafer140may include a first surface140aand a second surface140b, in which the first surface140aof the MEMS wafer140faces the CMOS wafer110. The second interconnect structures147of the MEMS wafer140extend across the first surface140aand the second surface140b. While other MEMS processes are performed on the MEMS wafer140, the second surface140bof the MEMS wafer140are more apt to receive or accumulate charges. Since one of the second interconnect structures147electrically connects the second surface140bto the conductive shielding layer116, the charges accumulated or received from the second surface140bcan be conducted to the semiconductor substrate100through the one of the second interconnect structures147, the conductive shielding layer116and the first interconnect structure118.

With reference made toFIG. 6, at least two openings141remain and expose the metal layers117formed in the CMOS wafer110. However, it should be understood that the number of the remaining openings141is not limited to two. In various embodiments, the number of the remaining openings141can be adjusted according to the actual requirements.

InFIG. 7, a cap wafer160is bonded to the CMOS wafer110through the two remaining openings141. The cap wafer160covers the MEMS wafer140. A second cavity C2is formed between the cap wafer160and the MEMS wafer140. More specifically, the second cavity C2is formed on or above the MEMS devices142of the MEMS wafer140. After bonding the cap wafer160to the CMOS wafer110, the MEMS devices142is located between the first cavity C1and the second cavity C2, so that the MEMS devices142can move in the first cavity C1and/or the second cavity C2. In various embodiments, the cap wafer160may be a silicon wafer although other types of semiconductor wafers may also be used.

With reference made toFIG. 7, the cap wafer160includes at least one residue portion160′. The residue portion160′ is a portion that will be removed, so that a portion of the MEMS wafer140is exposed to perform wire bonding on the exposed portion of the MEMS wafer140.

InFIG. 8, the residue portion160′ of the cap wafer160is removed by, for example, an etching process or a grinding process. As a result, an opening161is formed in the cap wafer160to expose a part of the MEMS wafer140. As shown inFIG. 8, at least two second interconnect structures147of the MEMS wafer140are exposed from the opening161of the cap wafer160. One of the exposed second interconnect structure147is electrically connected to the conductive shielding layer116, and the other exposed second interconnect structure147is electrically connected to the CMOS wafer110. The exposed second interconnect structure147that is not electrically connected to the conductive shielding layer116can be used to perform wire bonding, and thus the formation of the CMOS-MEMS-device-including package is finished.

Since at least one exposed second interconnect structure147is electrically connected to the conductive shielding layer116, when performing the grinding process or etching process to the cap wafer160, the conductive shielding layer116can protect the BEOL elements114and the FEOL elements102from the electromigration damage.

Furthermore, the MEMS wafer140covers the BEOL elements114and the FEOL elements102. In other words, an orthogonal projection of the MEMS wafer140on the CMOS wafer110overlaps with the BEOL elements114and the FEOL elements102. In some embodiments, when performing the grinding process, e.g. a chemical mechanical polishing (CMP) process, on the residue portion160′ of the cap wafer160to form the opening161, some fine particles may be sputtered along a direction that faces the BEOL elements114and the FEOL elements102. Since the MEMS wafer140covers the BEOL elements114and the FEOL elements102, the MEMS wafer140can protect the BEOL elements114and the FEOL elements102from the fine particles caused by the grinding process.

FIG. 9is a cross-sectional view of a CMOS-MEMS device in accordance with various embodiments of the present disclosure. The difference betweenFIG. 9andFIG. 8is that the conductive shielding layer116inFIG. 9does not cover the BEOL elements114and the FEOL elements102. In other words, the orthogonal projection of the conductive shielding layer116on the semiconductor substrate100is separated from the orthogonal projections of the BEOL elements114and the FEOL elements102on the semiconductor substrate100. In some embodiments, at least one of the openings141of the MEMS wafer140may not overlap with the BEOL elements114and the FEOL elements102. For example, in the embodiment ofFIG. 9, the leftmost opening141of the MEMS wafer140does not overlap with the BEOL elements114and the FEOL elements102. As a result, when performing the etching process (for patterning the MEMS wafer140and thus forming openings141) on the MEMS wafer140, the leftmost opening141of the MEMS wafer140does not cause damages to the BEOL elements114and the FEOL elements102. Therefore, in some embodiments, the conductive shielding layer116may no need to cover the BEOL elements114and the FEOL elements102if the openings141of the MEMS wafer140do not overlap with the BEOL elements114and the FEOL elements102.

InFIG. 9, the MEMS wafer140covers the BEOL elements114and the FEOL elements102. In other words, an orthogonal projection of the MEMS wafer140on the semiconductor substrate100overlaps with an orthogonal projection of the BEOL elements114and the FEOL elements102on the semiconductor substrate100. One of the second interconnect structures147formed in the MEMS wafer140exposed by the opening161of the cap wafer160is electrically connected to the conductive shielding layer160. As a result, when performing other MEMS related processes, e.g. a grinding process or an etching process, on the cap wafer160, the charges accumulated or received from the second surface140bof the MEMS wafer140can be conducted to the semiconductor substrate100through the second interconnect structures147, the conductive shielding layer146and the first interconnect structure118. Furthermore, in some embodiments, when performing the grinding process on the residue portion160′ of the cap wafer160, the MEMS wafer140can protect the BEOL elements114and the FEOL elements102from the fine particles caused by the grinding process.

FIG. 10is a cross-sectional view of a CMOS-MEMS device in accordance with various embodiments of the present disclosure. The difference betweenFIG. 10andFIG. 9is that the leftmost opening141of the MEMS wafer140inFIG. 10overlaps with at least one of the BEOL elements114and the FEOL elements102. More specifically, an orthogonal projection of the leftmost opening141on the CMOS wafer110overlaps with at least one of the BEOL elements114and the FEOL elements102. Furthermore, the conductive shielding layer116inFIG. 10covers the BEOL elements114and the FEOL elements102. Since the conductive shielding layer160covers the BEOL elements114and the FEOL elements102, and the conductive shielding layer160is electrically connected to the semiconductor substrate100, the charges accumulated or received from the second surface140bof the MEMS wafer140or from the surface131of the ILD layer130can be conducted to the semiconductor substrate100through the conductive shielding layer146. As a result, the BEOL elements114and the FEOL elements102can be protected from the electromigration damage.

In some embodiments, since the leftmost opening141of the MEMS wafer140inFIG. 10overlaps with the BEOL elements114and the FEOL elements102, when performing the etching process (for patterning the MEMS wafer140and thus forming openings141) on the MEMS wafer140, the BEOL elements114and the FEOL elements102may be damaged through the leftmost opening141of the MEMS wafer140. As a result, the conductive shielding layer116inFIG. 10needs to cover the BEOL elements114and the FEOL elements102. More specifically, an orthogonal projection of the conductive shielding layer116on the semiconductor substrate100overlaps with an orthogonal projection of the leftmost opening141on the semiconductor substrate100, thereby protecting the BEOL elements114and the FEOL elements102from the etching process of forming the leftmost opening141inFIG. 10.

FIG. 11is a cross-sectional view of a CMOS-MEMS device in accordance with various embodiments of the present disclosure. The difference betweenFIG. 11andFIG. 8is that there are two conductive shielding layers116a,116b, and the conductive shielding layers116a,116bare electrically connected to the ground contacts119a,119b, respectively. The ground contacts119a,119bare contact portions on the surface100aof the semiconductor substrate100. In various embodiments, the ground contacts119a,119bare contact portions that are grounded.

The conductive shielding layer116acovers the BEOL elements114, and the conductive shielding layer116bcovers the FEOL elements102. More specifically, in the embodiment ofFIG. 11, an orthogonal projection of the conductive shielding layer116aon the semiconductor substrate100overlaps with an orthogonal projection of the BEOL elements114on the semiconductor substrate100, and an orthogonal projection of the conductive shielding layer116bon the semiconductor substrate100overlaps with an orthogonal projection of the FEOL elements102on the semiconductor substrate100. Since the BEOL elements114and the FEOL elements102are covered by the conductive shielding layers116a,116b, separately. The BEOL elements114and the FEOL elements102can be protected from the MEMS related process damages.

FIG. 12is a cross-sectional view of a CMOS-MEMS device in accordance with various embodiments of the present disclosure. The difference betweenFIG. 12andFIG. 8is that the semiconductor substrate100ofFIG. 12includes a first dopant implant region104and a second dopant implant region105, in which the second dopant implant region105has a higher dopant concentration than the first dopant implant region104. In some embodiments, the first dopant implant region104has the same conductivity type as the second dopant implant region105. For example, the first dopant implant region104and the second dopant implant region105may be implanted with N-type dopants or P-type dopants. The conductive shielding layer116is electrically connected to the second dopant implant region105through the ground contact119. More specifically, in some embodiments, the ground contact119is a contact portion on the surface100aof the semiconductor substrate100that is electrically connected to the second dopant implant region10. Since the second dopant implant region105has a higher dopant concentration than the first dopant implant region104, the charges (such as electrons) can be conducted into the semiconductor substrate100and thus grounded. Therefore, the risk of the electromigration damage to the FEOL elements102and the BEOL elements114decreases.

In the embodiments, by forming a conductive shielding layer in the dielectric layers of the CMOS wafer, and electrically connecting the conductive shielding layer to a ground contact, the charges, plasma and electric arc can be shielded from the FEOL elements and the BEOL elements during the MEMS related process, e.g. etching process, grinding process, CMP process, etc. Accordingly, the electromigration damage to the FEOL elements102and the BEOL elements114can be avoided. In addition, in some embodiments, since the MEMS wafer or the conductive shielding layer covers the BEOL elements and the FEOL elements, when performing the grinding process on the residue portion of the cap wafer, the MEMS wafer can protect the BEOL elements and the FEOL elements from the fine particles caused by the grinding process, such that the yield in fabricating the CMOS-MEMS device can increase.

According to various embodiments of the present disclosure, a device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes at least one front-end-of-the-line (FEOL) element and at least one back-end-of-the-line (BEOL) element. The conductive shielding layer is disposed on a surface of the CMOS wafer and is electrically connected to a ground contact

According to various embodiments of the present disclosure, a device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

According to various embodiments of the present disclosure, a method includes forming a complementary metal-oxide-semiconductor (CMOS) wafer comprising at least one front-end-of-the-line (FEOL) element and at least one back-end-of-the-line (BEOL) element, forming a conductive shielding layer on the CMOS wafer, and electrically connecting the conductive shielding layer to a ground contact.