Described systems, methods, and circuitries use an interleaved multi-level converter to convert an input signal received at an input node into an output signal at an output node. In one example, a power conversion system includes a first multi-level switching circuit, a second multi-level switching circuit, and a control circuit. The first multi-level switching circuit and the second multi-level switching circuit are coupled to a switching node, the input node, and a reference node. The control circuit is configured to generate, based on the output signal, switching control signals as pulse width modulated signals having a duty cycle to control the output signal and provide the switching control signals to the first multi-level switching circuit and the second multi-level switching circuit.

BACKGROUND

High efficiency power supplies are desirable for battery-operated systems, including mobile phones, tablets, laptops and other devices. Buck, boost, and other DC/DC convertors use high and low side drivers to alternately connect a switching node to the input voltage or ground. As a result, the high and low side drivers are sized to withstand the input voltage level, and suffer from switching losses. Multi-level switching converter circuits use more switching stages and one or more flying capacitors, resulting in reduced switching loss and higher effective switching frequency. Multi-level switching converters enable the use of lower rated power devices that are not necessarily rated for the input voltage level, and the individual power devices in the converter can be run at a reduced frequency as compared to dual level converters, even while achieving a higher overall switching frequency.

SUMMARY

In one example, a power conversion system includes a first multi-level switching circuit, a second multi-level switching circuit, an inductor, and a control circuit. The first multi-level switching circuit is coupled to a switching node, the input node, and a reference node. The second multi-level switching circuit is coupled to the switching node, the input node, and the reference node, so the second multi-level switching circuit is arranged in parallel with the first multi-level switching circuit. The inductor is coupled between the switching node and the output node. The control circuit is configured to generate, based on the output signal, switching control signals as pulse width modulated signals having a duty cycle to control the output signal and provide the switching control signals to the first multi-level switching circuit and the second multi-level switching circuit.

In one example, a method to convert an input signal received at an input node into an output signal at an output node includes: providing the input signal to a first multi-level switching circuit coupled to a switching node, the input node, and a reference node; providing the input signal to a second multi-level switching circuit coupled to the switching node, the input node, and the reference node, so the second multi-level switching circuit is arranged in parallel with the first multi-level switching circuit; measuring the output signal; generating, based on the output signal, switching control signals as pulse width modulated signals having a duty cycle to control the output signal; and providing the switching control signals to the first multi-level switching circuit and the second multi-level switching circuit.

In one example, an integrated circuit includes a first multi-level switching circuit and a second multi-level switching circuitry coupled to a switching node, an input node, and a reference node, so the second multi-level switching circuit is arranged in parallel with the first multi-level switching circuit. Each of the first multi-level switching circuit and the second multi-level switching circuit includes a set of switches controlled by the switching control signals, the set of switches including a first switch coupled between the input node and a first internal node, a second switch coupled between the first internal node and the switching node, a third switch coupled between the switching node and a second internal node, and a fourth switch coupled between the second internal node and the reference node. Each of the first multi-level switching circuit and the second multi-level switching circuit includes a first capacitor connection feature coupled to the first internal node and a second capacitor connection feature coupled to the second internal node. The integrated circuit includes an inductor connection coupled to the switching node.

DETAILED DESCRIPTION

The drawings are not necessarily drawn to scale.

Multi-level converters exhibit many benefits including higher effective switching frequency, reduced switching losses, and an output current with less ripple. However, multi-level converters present design challenges in regulating the flying capacitor voltage and, because the input current is switched at half the switching frequency, multi-level converters may exhibit a tone for input current conducted electromagnetic interference (EMI) at one half of the switching frequency.

To overcome disadvantages described above, a power conversion system includes an interleaved multi-level converter having two parallel multi-level switching circuits. In the described architecture, the input current is switched at the same frequency as the switching frequency, which eliminates the half switching frequency tone concern for input current conducted EMI. The current density on the multi-stage converter components (besides the inductor) is halved. Radiated EMI is reduced due to the maximum voltage swing being reduced to half the input voltage as compared to a maximum voltage swing of the full input voltage in non-interleaved multi-level converters. The interleaved multi-level converter includes two multi-level switching circuits that share an input voltage node, a switch node, a reference node, and an inductor. The two multi-level power stages are driven by the same set of switching signals.

Throughout this description, components that are examples of a same or analogous component are assigned reference characters having the same value for the last two digits, while the initial digit(s) of reference characters are assigned based on the FIG. number in which they are first introduced.

FIG. 1is a block diagram of a power conversion system100that includes an interleaved multi-level converter101and a control circuit105. The power conversion system100is at least partially implemented on an integrated circuit (not shown for simplicity) that includes the interleaved multi-level converter101and the control circuit105. The IC also includes an input node102(e.g., IC pin or pad) to receive an input signal, such as an input voltage signal VIN and a reference node104(e.g., tied to a ground or other reference voltage). The IC includes a switching node103(e.g., IC pin or pad) to deliver a switched signal, such as a voltage or current, generated by the interleaved multi-level converter101to an inductor195. The inductor195, which may or may not be implemented on the IC, is coupled to an output node106that is configured to be coupled to a load being powered by the power conversion system.

In this example, the power conversion system100is a DC/DC converter. When powered, the system100converts an input signal VIN at the input node102to provide an output signal VOUT at the output node106. In one example, the system100operates to regulate the output signal according to a target signal or value that is provided to the control circuit105. The target value can be an internal signal or can be provided to the control circuit105from an external source.

The multi-level interleaved converter101includes a first multi-level switching circuit110and a second multi-level switching circuit150. Both the first multi-level switching circuit110and the second multi-level switching circuit150are coupled to the input node102, the switching node103, and the reference node104. As will be described in more detail below, each of the multi-level switching circuits110,150include switches, such as power transistors, coupled between the input node102and the reference node104. The switches are controlled by switching control signals generated by the control circuit105based on feedback signals from the inductor195and/or output node106(e.g., the output signal). The switching control signals are pulse width modulated signals having a duty cycle that is selected by the control circuit105to bring the output signal into equivalence with the target signal. Certain aspects of an example control circuit related to balancing control of flying capacitors in the multi-level switching circuits will be described with reference toFIGS. 8-11.

FIG. 2shows an example power conversion system200, including an example implementation of an interleaved multi-level converter201and a control circuit205. The interleaved multi-level converter201includes a first multi-level switching circuit210and a second multi-level switching circuit250. The first multi-level switching circuit210is a three level converter that includes a first switch212(labeled QAR), a second switch214(labeled QBR), a third switch216(labeled QCR), and a fourth switch218(labeled QDR) that are series-coupled between an input node202and a reference node204. These switches operate according to switching control signals D180, D0, D0′, and D180′ respectively, to provide a first voltage signal V1to the switching node203. In other examples, the first multi-level switching circuit210can include more or fewer switches to provide an N-level converter, where N is greater than 2. In this example, the switches212,214,216and218are power n-channel MOSFET (e.g., NMOS) transistors operative to turn on according to a corresponding active high switching control signal. In other examples, different types of switches may be used (e.g., PMOS, bipolar, IGBTs, and so on).

The first switch212of the first multi-level switching circuit210includes a drain coupled to the input node202and a source coupled to a first internal node211. The second switch214of the first multi-level switching circuit210includes a drain coupled to the first internal node211and a source coupled to the switching node203. The third switch216of the first multi-level switching circuit210includes a drain coupled to the switching node203and a source coupled to a second internal node219. The fourth switch218of the first multi-level switching circuit210includes a drain coupled to the second internal node219and a source coupled to a reference node204. The first multi-level switching circuit210also includes a capacitor215, referred to herein as a flying capacitor (labeled FC1). The capacitor215includes a high side plate213coupled to the first internal node211and a low side plate217coupled to the second internal node219. In one example, the IC includes the flying capacitor215as shown inFIG. 2. In another example, the IC includes capacitor connection features (e.g., pins or pads) (not shown) to allow connection of an external flying capacitor215.

The second multi-level switching circuit250is a three level converter that includes a first switch252(labeled QAL), a second switch254(labeled QBL), a third switch256(labeled QCL), and a fourth switch258(labeled QDL) in a series circuit between the input node202and the reference node204. These switches operate according to switching control signals D0, D180, D180′ and D0′ respectively, to provide a second voltage signal V2to the switching node203. In other examples, the second multi-level switching circuit250can include more or fewer switches to provide an N-level converter, where N is greater than 2. In this example, the number of levels in the first multi-level switching circuit250matches the number of levels in the second multi-level switching circuit250. In this example, the switches252,254,256, and258are power n-channel MOSFET (e.g., NMOS) transistors operative to turn on according to a corresponding active high switching control signal. In other examples, different types of switches may be used (e.g., PMOS, bipolar, IGBTs, and so on).

The first switch252of the second multi-level switching circuit250includes a drain coupled to the input node202and a source coupled to the first internal node251. The second switch254of the second multi-level switching circuit250includes a drain coupled to a first internal node251and a source coupled to the switching node203. The third switch256of the second multi-level switching circuit250includes a drain coupled to the switching node203and a source coupled to a second internal node259. The fourth switch258of the second multi-level switching circuit250includes a drain coupled to the second internal node259and a source coupled to the reference node204. The second multi-level switching circuit250also includes a flying capacitor255(labeled FC2). The flying capacitor255includes a high side plate253coupled to the first internal node251and a low side plate257coupled to the second internal node259. In one example, the IC includes the flying capacitor255as shown inFIG. 2. In another example, the IC includes pins or pads (not shown) to allow connection of an external flying capacitor255.

The output signals V1and V2from the multi-level switching circuits are provided to the inductor295coupled between the switching node203and an output node206. In this example, the IC includes an externally accessible inductor connection feature or features (e.g., pins or pads) for connection to the terminals of the inductor295, including a feature coupled to the switching node203and/or a feature coupled to the output node206. In other examples, the IC may include the output node202and/or inductor295. The configuration of the first multi-level switching circuit210and the second multi-level switching circuit250and the inductor295provides a buck-type DC/DC converter to provide a controlled output voltage VOUT at the output node206by converting input power from the input signal VIN. In this example, an output capacitor297(labeled C) is coupled between the output node206and the reference voltage. The output signal VOUT drives a load (not shown).

The control circuit205(which may be implemented as analog circuits, digital circuits, and/or firmware or software-executed program instructions) generates first switching control signal D0, second switching control signal D180, third switching control signal D0′, and fourth switching control signal D180′. The first switching control signal D0is 180 degrees out of phase with the second switching control signal D180. The third switching control signal D0′ is an inversion of the first switching control signal D0. The fourth switching control signal D180′ is an inversion of the second switching control signal D180. The control circuit205generates the switching control signals having a duty cycle that is based on the target signal and feedback signals including an inductor current IL(through inductor295) and, in some examples, also flying capacitor voltages VFC1and VFC2.

As shown inFIG. 2, in this example, the first switching control signal D0controls the first switch252in the second multi-level switching circuit250and the second switch214in the first multi-level switching circuit210. The second switching control signal D180controls the first switch212in the first multi-level switching circuit210and the second switch254in the second multi-level switching circuit250. The third switching control signal D0′ controls the third switch216in the first multi-level switching circuit210and the fourth switch258in the second multi-level switching circuit250. The fourth switching control signal D180′ controls the third switch256in the second multi-level switching circuit250and the fourth switch218in the first multi-level switching circuit210.

In this manner, the switching control signal sent to the first switch212is 180 degrees out of phase with the switching control signal sent to the first switch252, and this relationship is true for each pair of corresponding switches in the first multi-level converter210and the second multi-level converter250. Thus, the illustrated topology ensures that current is drawn from the input node202each time a D0or D180controlled switch (e.g.212,252) is activated. Although the D0and D180switching signals have half the frequency of the switching of the signal at the switching node203, the input current draw is at the same frequency as at the switching node203. This eliminates the EMI tone at half of the switching frequency experienced by other converters.

For proper operation, the voltages across flying capacitors215and255should be maintained at (or within some predetermined equivalence range of) VIN/2. The interleaved multi-level converter architecture illustrated inFIG. 2allows the flying capacitors to “self-balance” (e.g., without additional control measures) to VIN/2 when a valley-type control scheme is used by the control circuit205. This is because any deviation of the flying capacitor voltage from VIN/2 is counter-balanced by the dynamics of the valley current mode control forcing the allocated charge or discharge time of the flying capacitor to be corrected while maintaining the energizing and de-energizing current to the inductor. In this manner, VCMC provides an inherent negative feedback for flying capacitor voltage correction. However, when other control schemes (e.g., a peak-type control scheme) are used by the control circuit205, additional measures should be taken to regulate the voltages across the flying capacitors.

FIG. 3is a block diagram of a power conversion system300that includes an interleaved multi-level converter301, and a first balancing circuit330and a second balancing circuit360that are controlled by a control circuit (not shown) to selectively connect a flying capacitor FC1315in a first multi-level switching circuit310in parallel with a flying capacitor FC2355in a second multi-level switching circuit350. When the flying capacitors are coupled in parallel, after being series-coupled as dictated by switching stage commutation, the voltages across the flying capacitors are brought into equivalence with VIN/2 due to charge sharing.

FIG. 4illustrates an example implementation of a power conversion system400that includes first multi-level switching circuit410, second multi-level switching circuit450, first balancing circuit430, and second balancing circuit460. The first balancing circuit430includes a first balancing switch432and a second balancing switch434arranged in series between a first internal node411and a first internal node451. When both switches432,434are closed, a high side plate413of flying capacitor415is coupled to a high side plate453of flying capacitor455to place the flying capacitors into a parallel circuit arrangement with one another. The first balancing switch432and the second balancing switch434are controlled by a logical AND operation of the switching control signals D0′ and D180′, so the high side plates of the flying capacitors415,455are shorted only when both D180′ and D0′ overlap in high states. During this overlap interval, both switches418and458are turned ON, thereby placing the flying capacitors415and455in parallel circuit arrangement, as bottom plates417,457are pulled to the REF node404, and the top plates413,453are shorted through switches432,434in the first balancing circuit430.

The second balancing circuit460includes a first balancing switch462and a second balancing switch464arranged in series between a second internal node419and a second internal node459. When both switches462,464are closed, a low side plate417of flying capacitor415is coupled to a low side plate457of flying capacitor455, thereby placing the flying capacitors into a parallel circuit arrangement with one another. The first balancing switch462and the second balancing switch464are controlled by a result of a logical AND operation of the switching control signals D0and D180, so the low side plates of the flying capacitors415,455are shorted only when both D180and D0overlap in high states. During this overlap phase, both switches412and452are turned ON, thereby placing the flying capacitors415,455in parallel circuit arrangement, as top plates413,452are pulled to the input voltage at node402, and the bottom plates417,457are shorted through switches462,464in the second balancing circuit460. As shown inFIG. 4, the same switching control signals used to control the switches in the multi-level switching circuits410,450are also used to control the balancing circuits430,460. This simplifies the design significantly.

FIGS. 5A-5Dillustrate operation of an example power conversion system500during four intervals of a single switching period T when a duty cycle D of the switching control signals is less than 0.5 (a duty cycle of about 0.25 is shown). The power conversion system500includes an example interleaved multi-level converter501having balancing circuits530,560.

Referring toFIG. 5A, in a first interval, D0is high, D180is low, D0′ is low, and D180′ is high. (Only D0and D180are illustrated for simplicity). This combination of switching control signals will close switches514and518in the first multi-level switching circuit510and switches552and556in the second multi-level switching circuit550. In this configuration, an input voltage VIN charges a flying capacitor555of the second multi-level switching circuit550to V2, which induces a current ILthrough an inductor595and to the load. The low side of flying capacitor515of the first multi-level switching circuit510is tied to the reference node504, and a voltage across the flying capacitor515(V2) induces current ILthrough the inductor595. Both the first balancing circuit530and the second balancing circuit560are inactive, because D0and D180(and D0′ and D180′) are not both high. During this interval, the flying capacitors515,555are coupled in series circuit arrangement, with555coupled between the input node502and the switching node503, and515coupled between the switching node503and the REF node504.

Referring toFIG. 5B, in a second interval, D0and D180are both low and D0′ and D180′ are both high. This combination of switching signals will close switches516and518in the first multi-level switching circuit510and switches556and558in the second multi-level switching circuit550. First balancing circuit530is activated because both D0′ and D180′ are high, which closes both balancing switches532,534. In this configuration, current is drawn from the reference node through the closed switches to the inductor595. A high side plate513of flying capacitor515is coupled to a high side plate553of flying capacitor555, which places the flying capacitors into a parallel arrangement with one another, bringing the voltages VFC1, VFC2across the flying capacitors into equivalence with one another at approximately VIN/2.

Referring toFIG. 5C, in a third interval, D0is low, D180is high, D0′ is high, and D180′ is low. This combination of switching control signals will close switches512and516in the first multi-level switching circuit510and switches554and558in the second multi-level switching circuit550. In this configuration, an input voltage VIN charges the flying capacitor515of the first multi-level switching circuit510to V1, which induces a current ILthrough the inductor595and to the load. The low side of flying capacitor555of the second multi-level switching circuit550is tied to the reference node504, and a voltage across the flying capacitor555(V2) induces current ILthrough the inductor595. Both the first balancing circuit530and the second balancing circuit560are inactive because D0and D180(and D0″ and D180′) are not both high. During this interval, the flying capacitors515,555are coupled in series circuit arrangement, with515coupled between the input node502and the switching node503, and555coupled between the switching node503and the REF node504.

Referring toFIG. 5D, in a fourth interval, D0and D180are both low and D0′ and D180′ are both high. As described with reference toFIG. 5B, which illustrates the same switching control signal state, in this configuration, current is drawn from the reference node through the closed switches to the inductor595. A high side plate513of flying capacitor515is coupled to a high side plate553of flying capacitor555, which places the flying capacitors into a parallel arrangement with one another, bringing the voltages VFC1, VFC2across the flying capacitors into equivalence with one another at approximately VIN/2.

As shown inFIGS. 5A-5D, when the duty cycle is less than 0.5, the first balancing circuit530is activated during two “overlap” intervals in the switching cycle during which both switching control signals D0′ and D180′ are high, so the flying capacitors515and555can “self balance.” This balancing feature may be enabled or turned ON by default or might be activated selectively by the control circuitry, depending on the control scheme (e.g., peak or valley switching) and/or depending on monitored voltages across the flying capacitors515,555.

FIGS. 6A-6Dillustrate operation of an example power conversion system600during four intervals of a single switching period T when a duty cycle D of the switching control signals is greater than 0.5 (a duty cycle of about 0.6 is shown). The power conversion system600includes an example interleaved multi-level converter601having balancing circuits630,660.

Referring toFIG. 6A, in a first interval, D0and D180are both high and D0′ and D180′ are both low. This combination of switching signals will close switches612and614in the first multi-level switching circuit610and switches652and654in the second multi-level switching circuit650. Second balancing circuit660is activated because both D0and D180are high, which closes both balancing switches662,664. In this configuration, an input voltage VIN charges a flying capacitor615of the first multi-level switching circuitry610to V1and also charges a flying capacitor655of the second multi-level switching circuit650to V2, which induces a current ILthrough the inductor695and to the load. A low side plate617of flying capacitor615is coupled to a low side plate657of flying capacitor655, which places the flying capacitors into a parallel arrangement with one another, bringing the voltages VFC1, VFC2across the flying capacitors into equivalence with one another at VIN/2.

Referring toFIG. 6B, in a second interval, D0is high, D180is low, D0′ is low, and D180′ is high. This combination of switching control signals will close switches614and618in the first multi-level switching circuit610and switches652and656in the second multi-level switching circuit650. In this configuration, an input voltage VIN charges a flying capacitor655of the second multi-level switching circuit650to V2, which induces a current ILthrough the inductor695and to the load. The low side of flying capacitor615of the first multi-level switching circuit610is tied to the reference node604, and a voltage across the flying capacitor615(V2) induces current ILthrough the inductor695. Both the first balancing circuit630and the second balancing circuit660are inactive because D0and D180(and D0and D180′) are not both high. During this interval, the flying capacitors615,655are coupled in series circuit arrangement, with655coupled between the input node602and the switching node603, and615coupled between the switching node603and the REF node604.

Referring toFIG. 6C, in a third interval, D0and D180are both high and D0′ and D180′ are both low. As described with reference toFIG. 6A, which illustrates the same switching control signal state, both flying capacitors615,655are charged by VIN and induce a current through the inductor695. A low side plate617of flying capacitor615is coupled to a low side plate657of flying capacitor655, which places the flying capacitors into a parallel arrangement with one another, bringing the voltages VFC1, VFC2across the flying capacitors into equivalence with one another at VIN/2.

Referring toFIG. 6D, in a fourth interval, D0is low, D180is high, D0′ is high, and D180′ is low. This combination of switching control signals will close switches612and616in the first multi-level switching circuit610and switches654and658in the second multi-level switching circuit. In this configuration, an input voltage VIN charges the flying capacitor615of the first multi-level switching circuit610to V1, which induces a current ILthrough the inductor695and to the load. The low side of flying capacitor655of the second multi-level switching circuit650is tied to the reference node604, and a voltage across the flying capacitor655(V2) induces current ILthrough the inductor695. Both the first balancing circuit630and the second balancing circuit660are inactive because D0and D180(and D0′ and D180′) are not both high. During this interval, the flying capacitors615,655are coupled in series circuit arrangement, with615coupled between the input node602and the switching node603, and655coupled between the switching node603and the REF node604.

As shown inFIGS. 6A-6D, when the duty cycle is greater than 0.5, the second balancing circuit660is activated during two “overlap” intervals in the switching cycle during which both switching control signals D0and D180are high, so the flying capacitors615and655can “self balance.” This balancing feature may be enabled or turned ON by default or might be activated selectively by the control circuitry, depending on the control scheme (e.g., peak or valley switching) and/or depending on monitored voltages across the flying capacitors615,655.

FIGS. 7A-7Billustrate operation of an example power conversion system700during two intervals of a single switching period T when a duty cycle D of the switching control signals is equal to 0.5. The power conversion system700includes an example interleaved multi-level converter701having balancing circuits730,760. Because the duty cycle is equal to 0.5, only two different switching signal states occur in which D0and D180have opposite values.

Referring toFIG. 7A, in a first interval, D0is high, D180is low, D0′ is low, and D180′ is high. This combination of switching control signals will close switches714and718in the first multi-level switching circuit710and switches752and756in the second multi-level switching circuit750. In this configuration, an input voltage VIN charges a flying capacitor755of the second multi-level switching circuit750to V2, which induces a current ILthrough the inductor795and to the load. A low side717of flying capacitor715of the first multi-level switching circuit710is tied to the reference node704, and a voltage across the flying capacitor715(V2) induces current ILthrough the inductor795. Both the first balancing circuit730and the second balancing circuit760are inactive because D0and D180(and D0′ and D180′) are not both high. During this interval, the flying capacitors715,755are coupled in series circuit arrangement, with755coupled between the input node702and the switching node703, and715coupled between the switching node703and the REF node704.

Referring toFIG. 7B, in a second interval, D0is low, D180is high, D0′ is high, and D180′ is low. This combination of switching control signals will close switches712and716in the first multi-level switching circuit710and switches754and758in the second multi-level switching circuit. In this configuration, an input voltage VIN charges the flying capacitor715of the first multi-level switching circuit710to V1, which induces a current ILthrough the inductor795and to the load. The low side of flying capacitor755of the second multi-level switching circuit750is tied to the reference node704, and a voltage across the flying capacitor755(V2) induces current ILthrough the inductor795. Both the first balancing circuit730and the second balancing circuit760are inactive because D0and D180(and D0″ and D180′) are not both high. During this interval, the flying capacitors715,755are coupled in series circuit arrangement, with715coupled between the input node702and the switching node703, and755coupled between the switching node703and the REF node704.

As shown inFIGS. 7A-7B, when the duty cycle is equal to 0.5, no “overlap” interval exists in the switching cycle during which both switching control signals D0and D180or D0′ and D180′ are high, so the flying capacitors715and755will not be arranged in a parallel circuit for charge sharing and will not “self balance.”

Several techniques may be used to address this lack of self-balancing when the duty cycle is equal to 0.5. For example, steps may be taken to ensure that the interleaved multi-level converter cannot be started in a duty cycle of 0.5. In another example, a transient may be introduced into the system at start up. In another example, switching control signals may be adjusted to address a potential voltage imbalance on the flying capacitors (not shown) caused by a duty cycle of 0.5.

FIG. 8is a block diagram of a portion of an example control circuit805that generates the switching signals in a manner that prevents the voltage across flying capacitors in multi-level switching circuits from falling outside an equivalence range with VIN/2. The control circuit805includes an imbalance detection circuit870configured to determine whether a voltage across the flying capacitor in the first multi-level switching circuit or the flying capacitor in the second multi-level switching circuit falls outside an equivalence range with respect to half an input voltage at the input node. In response to determining that the voltage falls outside the equivalence range, the imbalance detection circuit870is configured to generate a balance signal. The control circuit805also includes a driver adjustment circuit configured to receive the balance signal and, in response to the balance signal, adjust a timing of at least one the switching control signals by an overlap duration (seeFIG. 11) to cause both the first balancing switch and the second balancing switch to close during the resulting overlap interval.

FIG. 9is a block diagram of a portion of an example control circuit905that generates the switching signals in a manner that maintains the voltage across flying capacitors in multi-level switching circuits within an equivalence range with VIN/2. The control circuit905includes an imbalance detection circuit970configured to determine whether a voltage across the flying capacitor in the first multi-level switching circuit or the flying capacitor in the second multi-level switching circuit falls outside an equivalence range with respect to half an input voltage at the input node. In response to determining that the voltage falls outside the equivalence range, the imbalance detection circuit970is configured to generate a balance signal. The control circuit905also includes a driver adjustment circuit980configured to receive the balance signal and, in response to the balance signal, adjust a timing of at least one the switching control signals by an overlap duration (seeFIG. 11), so both the first balancing switch and the second balancing switch close during the overlap duration.

The driver adjustment circuit980includes a driver state machine982configured to determine a desired duty cycle based on an output signal or signals of a power conversion system (e.g., output voltage, inductor current, and so on). The driver state machine982generates switching control signals D_PH0and D_PH180that are 180 degrees out of phase with one another and exhibit the determined the duty cycle. A driver delay circuit986generates a delayed version of the switching control signals to generate DPH0_Dly and DPH180_Dly respectively. A driver selection circuit990selects either delayed or non-delayed version of a switching control signal (D0in this example), depending on whether a balance signal has been generated by the imbalance detection circuit970.

FIG. 10is a block diagram of a portion of an example control circuit1005that generates the switching signals in a manner that maintains the voltage across flying capacitors in multi-level switching circuits within an equivalence range with VIN/2. The control circuit1005includes an imbalance detection circuit1070configured to determine whether a voltage across the flying capacitor in the first multi-level switching circuit or the flying capacitor in the second multi-level switching circuit falls outside an equivalence range with respect to half an input voltage at the input node. First and second voltage divider and clamps1012,1014measure a voltage between top and bottom plates of flying capacitors in first and second multi-level switching circuits respectively. The measured voltages are provided to comparators1016,1018when a fourth switch in the multi-level switching circuits (QDR, QDL inFIGS. 2-7) is closed, so a bottom plate of the flying capacitors is coupled to the reference voltage. These voltages are averaged, and the average is compared to VIN/2+/−ΔVhysΔVhysdefines an equivalence range about VIN/2. When comparator1016detects an under-voltage or comparator1018detects an over-voltage on the flying capacitors, a high value is stored in a latch1019, which may be an edge-triggered flip flop. The latch1019is clocked by a logical OR combination of the outputs of inverters1011and1013, which invert switching control signals D0′ and D180′ respectively. Thus, each time a logic LW to logic HIGH transition occurs on either of the D0or D180switching signals, the edge triggered flip flop 1019 samples the logical OR result of the over-voltage/under-voltage detection events and updates the balance signal accordingly. In this manner, whenever a flying capacitor over-voltage/under-voltage event occurs (so the flying capacitor voltages are moving away from VIN/2), the balance signal is set to logic HIGH.

The control circuit1005also includes a driver adjustment circuit980configured to receive the balance signal and, in response to the balance signal, adjust a timing of at least one the switching control signals by an overlap duration (seeFIG. 11) to cause both the first balancing switch and the second balancing switch to close during the overlap duration. The driver adjustment circuit1080includes a driver state machine1082configured to determine a desired duty cycle based on an output signal of a power conversion system and generate switching control signals D_PH0and D_PH180that are 180 degrees out of phase with one another and exhibit the determined the duty cycle. A driver delay circuit1086includes buffers1083that delay switching control signal DPH0to generate DPH0_Dly and buffers1084that delay switching control signal DPH180to generate DPH180_Dly. The number of buffers may be controlled to achieve a desired overlap duration.

A driver selection circuit1090includes a first multiplexer1092that outputs either delayed switching control signal DPH0_Dly or non-delayed switching control signal D_PH0, depending on whether a balance signal is high. A second multiplexer1096has the non-delayed switching control signal DPH180at both inputs. The path that includes buffers1084and multiplexer1096is provided to better synchronize the switching control signals DPH0, DPH0_Dly, and DPH180for having passed through similar sets of components. Logic1094generates switching control signal D0from the output of multiplexer1092, which will be either the delayed or non-delayed version of DPH0. Logic1094also generates switching control signal D0′ by inverting the selected switching control signal D0. Logic1098generates switching control signal D1800D180from the output of multiplexer1092. Logic1098also generates switching control signal D180′ by inverting switching control signal D180.

FIG. 11is a timing diagram of switching control signals D0and D180when the duty cycle is 0.5, and the duty cycle shifting technique described with reference toFIG. 10is used to maintain the voltage across flying capacitors. When the Balance signal is high, the delayed switching control signal DPH0_Dly is output by the control circuit instead of the non-delayed switching control signal DPH0. This causes “overlap” intervals (shaded) in which both D0and D180are high or both D0and D180are low. When D0and D180have the same value, balancing circuits (e.g.330or360,430or490,530or560,630or660,730or760ofFIGS. 3-7respectively) are activated to place the flying capacitors in a parallel arrangement. This allows the flying capacitors to can self-balance when the duty cycle is 0.5.

FIG. 12is a flow diagram outlining an example method1200to convert an input signal received at an input node into an output signal at an output node. The method1200may be performed by any of the power conversion systems100,200,300,400,500,600,700,800,900,1000described above or by a controller that is configured to control the various components of the power conversion systems. The controller may be implemented as a processor or machine executing stored computer-executable instructions, hardware, firmware, and so on.

The method1200includes: at1210, providing the input signal to a first multi-level switching circuit coupled to a switching node, the input node, and a reference node; and, at1220, providing the input signal to a second multi-level switching circuit coupled to the switching node, the input node, and the reference node, so the second multi-level switching circuit is arranged in parallel with the first multi-level switching circuit. At1230, an output signal is measured. The method includes, at1240, generating, based on the output signal, switching control signals as pulse width modulated signals having a duty cycle to control the output signal. The switching control signals are provided to the first multi-level switching circuit and the second multi-level switching circuit at1250.

As described above, an interleaved multi-level converter provides the benefits of a multi-level topology, autonomous balancing of flying capacitors, and elimination of the half switching frequency tone for conducted EMI.

The methods are illustrated and described above as a series of acts or events, but the illustrated ordering of such acts or events is not limiting. For example, some acts or events may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Also, some illustrated acts or events are optional to implement one or more aspects or embodiments of this description. Further, one or more of the acts or events depicted herein may be performed in one or more separate acts and/or phases. In some embodiments, the methods described above may be implemented in a computer readable medium using instructions stored in a memory.

In this description, the term “couple” may cover connections, communications or signal paths that enable a functional relationship consistent with this description. Accordingly, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled directly to device B; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.

Modifications are possible in the described examples, and other implementations are possible, within the scope of the claims.