Memory system which stores meta-data and meta-log, and operating method thereof

A memory system may include: a nonvolatile memory device suitable for storing write-requested data; and a controller including a first volatile memory region suitable for storing meta-data for the write-requested data and a second volatile memory region suitable for storing a meta-log for the meta-data, the controller may store the meta-data or the meta-log according to a logical address range of the meta-data.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0157117 filed on Nov. 24, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Exemplary embodiments relate to a memory system including a memory device, and an operating method thereof.

DISCUSSION OF THE RELATED ART

The computer environment paradigm has changed to ubiquitous computing systems that can be used anytime and anywhere. Due to this, use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having one or more memory devices for storing data. A memory system may be used as a main memory device or an auxiliary memory device of a portable electronic device.

Memory systems provide excellent stability, durability, high information access speed, and low power consumption because they have no moving parts. Examples of memory systems having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSD).

Conventional memory systems manage both meta-data corresponding to user data of the memory device and meta-logs representing changed records of the meta data, Generally, a memory system generates meta-logs reflecting changes of the meta data, and then updates the meta-data based on the meta logs. Significant resources are required to manage the meta-logs and the meta-data.

SUMMARY

Various embodiments of the present invention are directed to an improved memory system. The memory system may optimize the management of meta-data and meta-logs thus improving the use efficiency of a memory device employed by the memory system and making it possible to more rapidly and reliably process data to the memory device. Various embodiments of the present invention are directed to an operating method of the improved memory system.

In an embodiment, a memory system may include: a nonvolatile memory device suitable for storing write-requested data; and a controller including a first volatile memory region suitable for storing meta-data for the write-requested data and a second volatile memory region suitable for storing a meta-log for the meta-data, the controller may store the meta-data or the meta-log according to a logical address range of the meta-data.

The controller may store the meta-data or the meta-log by comparing the logical address range of the meta-data with a predetermined threshold range.

When the logical address range of the meta-data falls within the predetermined threshold range, the controller may store the meta-data in the first region.

When the logical address range of the meta-data does not fall within the predetermined threshold range, the controller may store the meta-log in the second region.

The meta-data stored in the first region may be divided into a plurality of meta-data groups each having logical address range within the predetermined threshold range and a suitable size for being stored to the nonvolatile memory device through a single storage operation, and when a number of meta-logs in the second region reaches a predetermined threshold number, the controller may further: select one or more meta-logs stored in the second region such that corresponding meta-data are included in a single one among the plurality of meta-data groups; update the meta-data based on the meta-logs stored in the second region; invalidate the meta-logs used for the update of the meta-data; store the updated meta-data, the invalidated meta-logs and remaining valid meta-logs in the nonvolatile memory device; and erase the invalidated meta-logs in the second region.

The respective meta-data may include a logical address mapped to a physical address of the write-requested data stored in the nonvolatile memory device, and the respective meta-logs may include a logical address mapped to a physical address of the write-requested data stored in the nonvolatile memory device.

When turning off the memory system, the controller may further: update the meta-data based on all of the meta-logs stored in the second region; invalidate all of the meta-logs stored in the second region; store all of the meta-data and all of the meta-logs in the nonvolatile memory device; and erase the invalidated meta-logs in the second region.

The respective meta-logs may represent change history of the respective meta-data stored in the first volatile memory region.

The controller may stores the meta-data in the nonvolatile memory device by units of the plurality of meta-data groups through a plurality of storage operations.

In an embodiment, an operating method for a memory system comprising a nonvolatile memory device, and first and second volatile memory regions, the operating method may include: storing write-requested data in the nonvolatile memory device; and storing meta-data for the write-requested data in the first volatile memory region or storing meta-logs for the meta-data according to a logical address range of the meta-data.

The storing meta-data or meta-logs may be performed by comparing the logical address range of the meta-data with a predetermined threshold range.

The storing meta-data may be performed when the logical address range of the meta-data falls within the predetermined threshold range.

The storing meta-logs may be performed when the logical address range of the meta-data does not fall within the predetermined threshold range.

The meta-data stored in the first region may be divided into a plurality of meta-data groups each having logical address range within the predetermined threshold range and a suitable size for being stored to the nonvolatile memory device through a single storage operation, and when a number of meta-logs in the second region reaches a predetermined threshold number, may further include: selecting one or more meta-logs stored in the second region such that corresponding meta-data are included in a single one among the plurality of meta-data groups; updating the meta-data based on the meta-logs stored in the second region; invalidating the meta-logs used for the update of the meta-data; storing the updated meta-data, the invalidated meta-logs and remaining valid meta-logs in the nonvolatile memory device; and erasing the invalidated meta-logs in the second region.

The respective meta-data may include a logical address mapped to a physical address of the write-requested data stored in the nonvolatile memory device, and the respective meta-logs may include a logical address mapped to a physical address of the write-requested data stored in the nonvolatile memory device.

When turning off the memory system, may further include: updating the meta-data based on all of the meta-logs stored in the second region; invalidating all of the meta-logs stored in the second region; storing all of the meta-data and all of the meta-logs in the nonvolatile memory device; and erasing the invalidated meta-logs in the second region.

The respective meta-logs may represent change history of the respective meta-data stored in the first volatile memory region.

The storing of the meta-data in the nonvolatile memory device may be performed by units of the plurality of meta-data groups through a plurality of storage operations.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in more detail with reference to the accompanying drawings. We note, however, that the present invention may be embodied in different other embodiments, forms and variations thereof and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art to which this invention pertains, Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate various features of the embodiments.

FIG. 1is a block diagram illustrating a data processing system100including a memory system110in accordance with an embodiment of the present invention.

Referring toFIG. 1, the data processing system100may include a host102and the memory system110.

The host102may include portable electronic devices such as a mobile phone, MP3 player and laptop computer or non-portable electronic devices such as a desktop computer, game machine, TV and projector.

The memory system110may operate to store data for the host102in response to a request of the host102. Non-limited examples of the memory system110may include a solid state drive (SSD), a multi-media card (MMC), a secure digital (SD) card, a universal storage bus (USB) device, a universal flash storage (UFS) device, compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card and memory stick. The MMC may include an embedded MMC (eMMC), reduced size MMC (RS-MMC) and micro-MMC. The SD card may include a mini-SD card and micro-SD card.

The memory system110may be embodied by various types of storage devices. Non-limited examples of storage devices included in the memory system110may include volatile memory devices such as a DRAM dynamic random access memory (DRAM) and a static RAM (SRAM) and nonvolatile memory devices such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM) an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM) and a flash memory. The flash memory may have a 3-dimensional (3D) stack structure.

The memory system110may include a memory device150and a controller130. The memory device150may store data for the host120and the controller130may control data storage into the memory device150.

The controller130and the memory device150may be integrated into a single semiconductor device, which may be included in the various types of memory systems as exemplified above.

Non-limited application examples of the memory system110may include a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book a Personal Digital Assistant (PDA), a portable computer, a web tablet, a tablet computer a wireless phone, a mobile phone, a smart phone, an e-book, a Portable Multimedia Player (PMP) a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting/receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a Radio Frequency Identification (RFID) device, or one of various components constituting a computing system.

The memory device150may be a nonvolatile memory device and may retain data stored therein even though power is not supplied. The memory device50may store data provided from the host102through a write operation, and provide data stored therein to the host102through a read operation. The memory device150may include a plurality of memory dies (not shown), each memory die including a plurality of planes (not shown), each plane including a plurality of memory blocks152to156, each of the memory blocks152to156may include a plurality of pages, and each of the pages may include a plurality of memory cells coupled to a word line.

The controller130may control the memory device150in response to a request from the host102, For example, the controller130may provide data read from the memory device150to the host102, and store data provided from the host102into the memory device150. For this operation, the controller130may control read, write, program and erase operations of the memory device150.

The controller130may include a host interface (I/F) unit132, a processor134, an error correction code (ECC) unit138, a Power Management Unit (PMU)140, a memory device controller (MDC)142and a memory144all operatively coupled via an internal bus.

The host interface unit132may be configured to process a command and data of the host102, and may communicate with the host102through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-E), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (BATA), parallel advanced technology attachment (PATA), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).

The ECC unit138may detect and correct an error contained in the data read from the memory device150. In other words, the ECC unit138may perform an error correction decoding process to the data read from the memory device150through an ECC code used during an ECC encoding process. According to a result of the error correction decoding process, the ECC unit138may output a signal, for example, an error correction success/fail signal. When the number of error bits is more than a threshold value of correctable error bits, the ECC unit138may not correct the error bits, and may output an error correction fail signal.

The ECC unit138may perform error correction through a coded modulation such as Low Density Parity Check (LDPC) code, Bose-Chaudhri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution code, Recursive Systematic Code (RSC), Trellis-Coded Modulation (TCM) and Block coded modulation (BCM). However, the ECC unit138is not limited thereto. The ECC unit138may include all circuits, modules, systems or devices for error correction.

The PMU140may provide and manage power of the controller130.

The MDC142may serve as a memory/storage interface for interfacing the controller130and the memory device150such that the controller130controls the memory device150in response to a request from the host102. When the memory device150is a flash memory or specifically a NAND flash memory, the MDC142may be a NAND flash controller and may generate a control signal for the memory device150and process data to be provided to the memory device150under the control of the processor134. The MDC142may work as an interface (e.g. a NAND flash interface) for processing a command and data between the controller130and the memory device150. Specifically, the MDC142may support data transfer between the controller130and the memory device150.

The memory144may serve as a working memory of the memory system110and the controller130, and store data for driving the memory system110and the controller130. The controller130may control the memory device150to perform read, write, program and erase operations in response to a request from the host102. The controller130may provide data read from the memory device150to the host102, may store data provided from the host102into the memory device150. The memory144may store data required for the controller130and the memory device150to perform these operations.

The memory144may be embodied by a volatile memory. For example, the memory144may be embodied by static random access memory (SRAM) or dynamic random access memory (DRAM). The memory144may be disposed within or out of the controller130.FIG. 1exemplifies the memory144disposed within the controller130. In an embodiment, the memory144may be embodied by an external volatile memory having a memory interface transferring data between the memory144and the controller130.

The processor134may control the overall operations of the memory system110. The processor134may drive firmware to control the overall operations of the memory system110. The firmware may be referred to as flash translation layer (FTL).

The processor134of the controller130may include a management unit (not illustrated) for performing a bad management operation of the memory device150. The management unit may perform a bad block management operation of checking a bad block, in which a program fail occurs due to the characteristic of a NAND flash memory during a program operation, among the plurality of memory blocks152to156included in the memory device150. The management unit may write the program-failed data of the bad block to a new memory block. In the memory device150having a 3D stack structure, the bad block management operation may reduce the use efficiency of the memory device150and the reliability of the memory system110. Thus, the bad block management operation needs to be performed with more reliability.

FIG. 2is a schematic diagram illustrating the memory device150.

Referring to FIC.2, the memory device150may include a plurality of memory blocks 0 to N−1 and each of the blocks 0 to N−1 may include a plurality of pages, for example, 2Mpages, the number of which may vary according to circuit design. Memory cells included in the respective memory blocks 0 to N−1 may be one or more of a single level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, a triple level cell (TLC) storing 3-bit data, a quadruple level cell (QLC) storing 4-bit level cell, a multiple level cell storing 5-or-more-bit data, and so forth.

FIG. 3is a circuit diagram illustrating n exemplary configuration of a memory cell array of a memory block in the memory device150.

Referring toFIG. 3, a memory block330which may correspond to any of the plurality of memory blocks152to156included in the memory device150of the memory system110may include a plurality of cell strings340coupled to a plurality of corresponding bit lines BL0to BLm-1. The cell string340of each column may include one or more drain select transistors DST and one or more source select transistors SST. Between the drain and select transistors DST and SST, a plurality of memory cells MC0to MCn-1may be coupled in series. In an embodiment, each of the memory cell transistors MC0to MCn-1may be embodied by an MLC capable of storing data information of a plurality of bits. Each of the cell strings340may be electrically coupled to a corresponding bit line among the plurality of bit lines BL0to BLm-1. For example, as illustrated inFIG. 3, the first cell string is coupled to the first bit line BL0, and the last cell string is coupled to the last bit line BLm-1.

AlthoughFIG. 3illustrates NAND flash memory cells, the invention is not limited in this way. It is noted that the memory cells may be NOR flash memory cells, or hybrid flash memory cells including two or more kinds of memory cells combined therein. Also, it is noted that the memory device150may be a flash memory device including a conductive floating gate as a charge storage layer or a charge trap flash (CTF) memory device including an insulation layer as a charge storage layer.

The memory device150may further include a voltage supply unit310which provides word line voltages including a program voltage, a read voltage and a pass voltage to supply to the word lines according to an operation mode. The voltage generation operation of the voltage supply unit310may be controlled by a control circuit (not illustrated). Under the control of the control circuit, the voltage supply unit310may select one of the memory blocks (or sectors) of the memory cell array, select one of the word lines of the selected memory block, and provide the word line voltages to the selected word line and the unselected word lines as may be needed.

The memory device150may include a read/write circuit320which is controlled by the control circuit. During a verification/normal read operation, the read/write circuit320may operate as a sense amplifier for reading data from the memory cell array. During a program operation the read/write circuit320may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit320may receive from a buffer (not illustrated) data to be stored into the memory cell array, and drive bit lines according to the received data. The read/write circuit320may include a plurality of page buffers322to326respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs), and each of the page buffers322to326may include a plurality of latches (not illustrated).

FIG. 4is a schematic diagram illustrating an exemplary 3D structure of the memory device150.

The memory device150may be embodied by a 2D or 3D memory device. Specifically, as illustrated inFIG. 4, the memory device150may be embodied by a nonvolatile memory device having a 3D stack structure. When the memory device150has a 3D structure, the memory device150may include a plurality of memory blocks BLK0to BLKN-1each having a 3D structure (or vertical structure).

FIG. 5is a diagram illustrating an operating method of the memory system130in accordance with an embodiment of the present invention.FIGS. 8 to 12are diagrams illustrating the operating method shown inFIG. 5.

When user data is written into the memory device150of the memory system130, meta-data corresponding to the user data are stored along with the user data in the memory device150.

The meta-data are data describing the user data, i.e., information about attributes of the user data and/or a mapping relationship between logical address and physical address of the user data.

Referring toFIG. 5, an operating method of the memory system110in accordance with an embodiment of the present invention may start by turning on the memory system110at step511. For example, based on a command received from the host102, the memory system110may be turned on.

If the memory system110is turned on, the controller130may enable a meta-region in the memory144. The meta-region may include a first region and a second region. The first region may store meta-data corresponding to user data written in the memory device150. For example, as shown inFIG. 8A, the first region may store the meta-data in a mapping table. In the mapping table, logical addresses are respectively mapped to physical addresses of the memory device150. When the memory system110is turned on, the controller130may access the memory device150and read meta-data corresponding to the user data stored in the memory device150.

The meta-data are stored in the memory device150, which is a nonvolatile memory device. The memory144of the controller130is a volatile memory and can only store the meta-data temporarily.

The meta-data includes logical addresses and physical addresses of the memory device150and generally has a relatively large size. The meta-data may also include additional information about the user data. Even when the memory144of the controller130is large enough to store all meta-data, it may not be possible to store all of the meta-data into the memory device150through a single storage operation. Hence, the meta-data may be divided into a plurality of groups each having a preset size, and the plurality of groups of the meta-data may be stored in the memory device150through a plurality of storage operations. For example, all of the meta-data may be divided into five groups and five data storage operations may be performed to store all of the meta-data into the memory device150.

In the case where the size of the memory144is not large enough for storing all of the meta-data, the entire meta-data are stored in only the memory device150, and only some of the meta-data may be stored in the memory144. In this case, it is possible to store all of the meta-data stored in the memory144in the memory device150through a single storage operation. However, a plurality of storage operations may also be performed when the entire meta-data is updated because the meta-data stored in the memory144is only some of the entire meta-data.

The second region may be allocated for storing a meta-log representing the history of changes of the respective meta-data stored in the first region. The meta-log may also be updated when the meta-data of the first region is updated. Therefore, as shown inFIG. 8Bthe second region may store the meta-log, in a mapping table. In a meta-log mapping table, a logical address and a physical address of the memory device150are mapped to each other. The addresses stored in the second region may represent meta-data which are changed. When the memory system110is turned on, the second region may be empty.

For example, a write request for user data may be received in operation513. The write request may include the size and logical address of user data. For example, the write request may include ‘logical value 3’ as the logical address of the user data. The controller130may assign ‘physical value 3’ as the physical address for the user data in the memory device150in correspondence with the logical address ‘logical value 3’. Thereby, in correspondence with the user data of the write request, meta-data may be generated to represent that ‘logical value 3’ and ‘physical value 3’ mapped to each other.

The controller130may analyze the write request in operation515to identify the logical address of the meta-data generated in correspondence with the user data requested to be written.

In operation517, the controller130may determine whether the write request meets a bypass condition. For example, the bypass condition may require that a range of the logical address of the meta-data corresponding to the write request is within a predetermined threshold range. Thereby, the processor134may compare a range of the logical address of the meta-data corresponding to the write request with the predetermined threshold range. That is, the controller130may determine whether the logical address range of the meta-data is within the predetermined threshold range.

For example, when respective logical address values of ten meta-data generated in correspondence with the user data requested to be written are checked, the ten meta-data may have successive values so that the logical address range thereof may be within the predetermined threshold range. In this case, the write request corresponding to the ten meta-data may be determined to meet the bypass condition.

On the other hand, when the ten meta-data may have distributed or widely scattered logical address values so that the logical address range thereof does not fall within the predetermined threshold range. In this case, the write request corresponding to the distributed or widely scattered ten meta-data may be determined not to meet the bypass condition.

As a result of operation517, when the write request meets the bypass condition, the controller130may update the meta-data to the first region in operation519but may not generate a meta-log of the meta-data resell ting from the update operation. Therefore, the meta-log may not be added to the second region. That is, the controller130updates the meta-data in the first region without adding the meta-log to the second region. For example as shown inFIG. 9the controller130may map the logical address (e.g. ‘logical value 3’) of the user data to the physical address (e.g., ‘physical value 3’) for the user data of the write request. When the ‘physical value 3’ corresponds to page 0 of block 1, the controller130may map the meta-data of the ‘logical value 3’ to the page 0 of block 1 of the ‘physical value 3’. In this way the meta-data may be updated in the first region in operation519.

As a result of operation517when the write request does not meet the bypass condition, the controller130may generate a meta log that is a newly changed meta-data and store the generated meta-log in the second region in operation521. That is, the controller130does not update the meta data in the first region when the logical address range of the meta data exceeds the threshold range. Instead, the controller130generates a meta log that is the newly changed meta data, and stores the meta log in the second region. For example, as shown inFIGS. 10A TO 10C, the controller130may generate a meta-log representing mapping relationship between the logical address and the physical address of the user data, and store the meta-log in the second region.

Referring toFIG. 6the controller130may add the meta-log to the second region of the memory144in operation611. For example, if the second region is empty, the controller130may add the meta-log as shown inFIG. 10A. Alternatively, if at least one other meta-log is present in the second region, the controller130may add a meta-log, as shown inFIG. 10B.

In operation613, the controller130may determine whether the second region meets an update condition. The update condition may require that a number of meta-logs stored in the second region reach a preset threshold number. Therefore, the processor134may, in operation613, compare the number of meta-logs stored in the second region with the preset threshold number and determine whether or not the number of meta-logs stored in the second region has reached the preset threshold number.

As a result of operation613, if it is determined that the second region meets the update condition, the controller130may update meta-data that are stored in the first region using at least one of the meta-logs that are stored in the second region in operation615. For example, if the number of meta-logs in the second region has reached the preset threshold number, the controller130may update the meta-data that are present in the first region using at least one of the meta-logs that are present in the second region. In an embodiment, when the number of meta-logs in the second region reaches the preset threshold number, the controller130updates the meta-data that are present in the first region using all of the meta-logs that are present in the second region.

For example, in the case where meta-logs are stored in the second region as shown inFIG. 10B, the controller130may use at least one of the meta-logs that are present in the second region to update corresponding meta-data of the first region, and invalidate the meta-log used for the update of the meta-data. For example, the controller130may use meta-logs corresponding to ‘logical value 3’, ‘physical value 3’, ‘logical value 10’ and ‘physical value 1’ in the second region to update corresponding meta-data of the first region, and invalidate these meta-logs. That is, when the controller130uses the meta-logs corresponding to ‘logical value 3’, ‘physical value 3’, ‘logical value 10’ and ‘physical value 1’ in the second region to update corresponding meta-data of the first region, as shown inFIG. 11A, the controller130may update the meta-data of the first region in such a way that ‘logical value 3’ is mapped to ‘physical value 3’ representing page 0 of block 1, and ‘logical value 10’ is mapped to ‘physical value 1’ representing page 1 of block 0.

Hence, in an embodiment, when the meta-data that are present in the first region are updated using the meta-logs that are present in the second region and the meta-logs corresponding to the updated meta-data are invalidated, some of the meta-logs may be used for the update of the meta-data and invalidated while the other meta-logs may not be used for the update of the meta-data or invalidated.

A criterion for selecting a eta-log for the updating of the meta-data and the invalidation of the meta-log is that the write requests corresponding to the meta-logs that are present in the second region do not meet the bypass condition as described with reference to operations517and521. That is, a range of the logical addresses of the meta-data corresponding to the meta-logs that are present in the second region is not within the predetermined threshold range.

As described above because the size of meta-data may be relatively large, a plurality of storage operations may be performed to store all of the meta-data in the memory device150. In an embodiment the meta-data that are present in the first region are divided into a plurality of groups each having a preset number of meta data (i.e., size) and are managed on a group basis. For example, the meta-data that are present in the first region may be divided based on the predetermined threshold range of logical addresses, i.e., the bypass condition as described with reference to operations517. For example, the meta-data that are present in the first region may be divided into five groups based on the threshold range of logical addresses. When a method is used which stores one group through a single storage operation, then five storage operations are employed for storing, in the memory device150, all of the meta-data that are present in the first region.

However, as described above with reference to operation517and521, a logical address range of the meta-data corresponding to the meta-logs that are present in the second region may not fail within the predetermined threshold range. That is, the meta-data corresponding to the meta-logs that are present in the second region may have distributed or widely scattered logical address values. Therefore, if it is assumed that the meta-data in the first region are updated using all of the meta-logs that are present in the second region, the plurality of meta-data groups in the first region may be updated simultaneously. The simultaneous update to the plurality of meta-data groups in the first region may cause a plurality of storage operation to be performed in order to store the plurality of meta-data groups, which include updated meta-data of the distributed logical address values in the first region, into the memory device150. However, this may be a less efficient operating method.

Therefore, in a preferred embodiment of the present invention, when updating the meta-data that are present in the first region based on the meta-logs that are present in the second region, meta-logs for the update of the meta-data and the invalidation may be selected by units of the respective meta-data groups stored in the first region. That is, meta-logs for the update of the meta-data and the invalidation may be selected in such a manner that corresponding meta-data to be updated are included in a single one among the plurality of meta-data groups in the first region. Therefore, the update of the meta-data may be performed by the units of the respective meta-data groups in the first region. When storing the meta-data of the first region into the memory device150after the update, it may not be all of the meta-data (i.e., all of the plurality of meta-data groups) but a single meta-data group including the updated meta-data that is required to be stored in the memory device150. Since meta-logs for the update of the meta-data and the invalidation is selected such that corresponding meta-data to be updated are included in a single one among the plurality of meta-data groups in the first region, only a single storage operation may be performed to reflect the update of the meta-data based on the meta-logs into the memory device150.

Hence, when the meta-data of the first region are updated based on the meta-logs of the second region and the meta-logs corresponding to the updated meta-data are invalidated, the meta-logs used for the update of the meta-data may be invalidated while the other meta-logs may not be invalidated. Stated otherwise, meta-logs that have been used to update the meta-data that are present in the first region, among the meta logs that are present in the second region, are converted into an invalid state, and meta-logs that have not been used are maintained in a valid state.

In operation617, the controller130may transmit the valid meta-logs of the second region to the memory device150. In operation619, the memory device150may store the valid meta-logs received from the controller130. For example, the memory device150may store the valid meta-logs in a region predetermined to store valid meta logs, for example, in a second space (not shown) of the memory device150.

In operation621, the controller130may transmit the invalidated meta-logs of the second region to the memory device150. In operation623, the memory device150may store the invalid meta-logs received from the controller130. For example, the memory device150may store the invalid meta-logs in a region predetermined to store invalid meta-logs, for example in a third space (not shown) of the memory device150.

In operation625, the controller130may remove the invalidated meta-logs from the second region of the memory144. In the case where all of the meta-logs in the second region are invalidated, the second region may be emptied as the controller130removes the invalid meta-logs from the second region. In the case where only some of the meta-logs in the second region are invalidated, the other valid meta-logs may remain in a valid state in the second region as the controller130removes the invalid meta-logs from the second region.

For example, when meta-logs are included in the second region as illustrated inFIG. 10B, a meta-log of a ‘logical value 3’ and ‘physical value 3’ and a meta-log of a ‘logical value 10’ and ‘physical value 1’ illustrated inFIG. 11Bmay be used to update the meta-data of the first region, the controller130may update the meta-data of the first region in such a way that logical value 3′ is mapped to ‘physical value 3’ representing page 0 of block 1, and ‘logical value 10’ is mapped to ‘physical value 1’ representing page 1 of block 0 as exemplified inFIG. 11A. Therefore, the meta-log of a ‘logical value 3’ and ‘physical value 3’ and the meta-log of a ‘logical value 10’ and ‘physical value 1’ may be invalidated in the second region. Accordingly, the two invalidated meta-logs may be stored in the memory device150and then removed from the second region, as shown inFIG. 11C. Also as shown inFIG. 11C, the one valid meta-log of ‘logical value 20’ and ‘physical value 2’ may remain in the second region as it is, rather than being removed, even after having been stored in the memory device150. Subsequently, the controller130may proceed to operation523ofFIG. 5.

When in operation613, it is determined that the second region does not meet the update condition, the controller130may proceed to operation523ofFIG. 5. For example, when the number of meta-logs that are present in the second region does not reach the threshold number, the controller130may maintain the meta logs that are present in the second region as is. In addition, the controller130may also maintain the meta data that are present in the first region as is.

Referring back toFIG. 5, when the memory system110is turned off, the controller130may detect the turn-off event of the memory system110in operation523. For example, based on a command of the host102, the controller130may detect the event for turning off the memory system110. In operation525the controller130may store, in the memory device150, meta-data that are present in the first region and meta-logs that are present in the second region. The controller130may update meta-data of the first region using all of the meta-logs that are present in the second region, invalidate all of the meta-logs that are present in the second region, store the invalidated meta-logs in the memory device150, erase the second region, and then store the meta-data of the first region that have been updated in the memory device150.

Referring toFIG. 7, in operation711the controller130may determine whether meta-logs are present in the second region of the memory144.

If, in operation711, it is determined that no meta-log is present in the second region, the controller130may proceed to operation527. If, in operation711, it is determined that meta-logs are present in the second region, the controller130may update meta-data that are present in the first region using all of the meta-logs that are present in the second region, in operation713.

The update scheme of the meta-data using the meta-logs may be the same as described with reference to operation615. For example, a shown inFIG. 10BorFIG. 11C, if meta-logs are present in the second region the controller130may update meta-data that are present in the first region using all of the meta-logs that are present in the second region. That is, if meta-logs are present in the second region in the form shown inFIG. 10B, the controller130may provide a meta-log mapped with ‘logical value 3’ and ‘physical value 3’, a meta-log mapped with ‘logical value 10’ and ‘physical value 1’, and a meta-log mapped with ‘logical value 20’ and ‘physical value 2’ to the first region. Thereby, as shown inFIG. 12, the controller130may map, of the meta data of the first region, ‘logical value 3’ in correspondence with ‘physical value 3’, for example, block 1 and page 0, ‘logical value 10’ in correspondence with ‘physical value 1’, for example, block 0 and page 1, and ‘logical value 20’ in correspondence with ‘physical value 2’, for example, block 2 and page 4. Alternatively, if a meta-log is present in the second region in the form ofFIG. 11C, the controller130may provide a meta-log mapped with ‘logical value 20’ and ‘physical value 2’ to the first region. Thereby, as shown inFIG. 12, the controller130may map, of the meta-data of the first region, ‘logical value 20’ in correspondence with ‘physical value 2’, for example, block 2 and page 4.

Subsequently, in operation715, the controller130may transmit the meta-data of the first region to the memory device150. In operation717, the memory device150may store the meta-data. Here, in the case where the updating of the meta data that are present in the first region has been performed for a plurality of meta-data groups of the first region, a plurality of storage operations may be performed by repeating operation715and operation717for the respective updated meta-data groups. Subsequently, the controller130may proceed to operation527ofFIG. 5.

Referring back toFIG. 5, in operation527, the controller130may turn off the memory system110. Thereby, the operation of the memory system110may be terminated.

In accordance with various embodiments, the memory system110may update meta-data in response to a write request of user data. In this regard, the memory system110may update the meta-data even without generating a meta-log. As a result, resources required to manage the meta-log and the meta-data in the memory system110may be reduced.

Hereinbelow, detailed descriptions will be made with reference toFIGS. 13 to 18for a data processing system and electronic appliances including the memory system110.

FIG. 13is a diagram illustrating a data processing system including the memory system according to an embodiment of the present invention.FIG. 13is a drawing schematically illustrating a memory card system to which the memory system according to an embodiment is applied.

Referring toFIG. 13, a memory card system6100includes a memory controller6120, a memory device6130, and a connector6110.

In detail the memory controller6120may be connected with the memory device6130and may access the memory device6130. In some embodiments, the memory device6130may be implemented with a nonvolatile memory (NVM). For example, the memory controller6120may control read, write, erase and background operations for the memory device6130. The memory controller6120may provide an interface between the memory device6130and a host (not shown), and may drive a firmware for controlling the memory device6130. For example, the memory controller6120may correspond to the controller130in the memory system110described above with reference toFIG. 1, and the memory device6130may correspond to the memory device150in the memory system110described above with reference toFIG. 1.

Therefore, the memory controller6120may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface and an error correction unit as shown inFIG. 1.

The memory controller6120may communicate with an external device (for example, the host102described above with reference toFIG. 1), through the connector6110. For example, as described above with reference toFIG. 1, the memory controller6120may be configured to communicate with the external device through at least one of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PIe), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, universal flash storage (UFS), wireless-fidelity (WI-FI) and Bluetooth. Accordingly, the memory system and the data processing system according to the embodiment may be applied to wired/wireless electronic appliances, for example, a mobile electronic appliance.

The memory device6130may be implemented with a nonvolatile memory. For example, the memory device6130may be implemented with various nonvolatile memory devices such as an electrically erasable and programmable ROM (EPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfer magnetic RAM (STT-MRAM).

The memory controller6120and the memory device6130may be integrated into a single semiconductor device. For example, the memory controller6120and the memory device6130may construct a solid state driver (SSD) by being integrated into a single semiconductor device. The memory controller6120and the memory device6130may construct a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash card (CF), a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro and eMMC), an SD card (e.g. SD, miniSD, microSD and SDHC) and a universal flash storage (UFS).

FIG. 14is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring toFIG. 14, a data processing system6200includes a memory device6230which may be implemented with at least one nonvolatile memory (NVM) and a memory controller6220for controlling the memory device6230. The data processing system6200may be a storage medium such as a memory card (e.g., CF, SD and microSD), as described above with reference toFIG. 1. The memory device6230may correspond to the memory device150in the memory system110described above with reference toFIG. 1, and the memory controller6220may correspond to the controller130in the memory system110described above with reference toFIG. 1.

The memory controller6220may control the operations, including the read, write and erase operations for the memory device6230in response to requests received from a host6210. The memory controller6220may include a central processing unit (CPU)6221, a random access memory (RAM) as a buffer memory6222, an error correction code (ECC) circuit6223, a host interface6224, and an NVM interface as a memory interface6225, all coupled via an internal bus.

The CPU6221may control the operations for the memory device6230such as read, write, file system management, bad page management, and so forth. The RAM6222may operate according to control of the CPU6221and may be used as a work memory, a buffer memory, a cache memory, or the like. In the case where the RAM6222is used as a work memory, data processed by the CPU6221is temporarily stored in the RAM6222. In the case where the RAM6222is used as a buffer memory, the RAM6222is used to buffer data to be transmitted from the host6210to the memory device6230or from the memory device6230to the host6210. In the case where the RAM6222is used as a cache memory, the RAM6222may be used to enable the memory device6230with a low speed to operate at a high speed.

The ECC circuit6223corresponds to the ECC unit138of the controller130described above with reference toFIG. 1. As described above with reference toFIG. 1, the ECC circuit6223may generate an error correction code (ECC) for correcting a fail bit or an error bit in the data received from the memory device6230. The ECC circuit6223may perform error correction encoding for data to be provided to the memory device6230, and may generate data added with parity bits. The parity bits may be stored in the memory device6230. The ECC circuit6223may perform error correction decoding for data outputted from the memory device6230. At this time, the ECC circuit6223may correct errors by using the parity bits. For example, as described above with reference toFIG. 1, the ECC circuit6223may correct errors by using various coded modulations such as of a low-density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a Trellis-coded modulation (TCM) and a Block coded modulation (BCM).

The memory controller6220transmits and receives data to and from the host6210through the host interface6224, and transmits and receives data to and from the memory device6230through the NVM interface6225. The host interface6224may be connected with the host6210through at least one of various interface protocol s such as a parallel advanced technology attachment (PATA) bus, a serial advanced technology attachment (SATA) bus, a small computer system interface (SCSI), a universal serial bus (USB), a peripheral component interconnection express (PCIe) or a NAND interface. Further, as a wireless communication function or a mobile communication protocol such as wireless fidelity (WI-FI) or long term evolution (LTE) is realized, the memory controller6220may transmit and receive data by being connected with an external device such as the host6210or another external device other than the host6210. Specifically, as the memory controller6220is configured to communicate with an external device through at least one among various communication protocols, the memory system and the data processing system according to the embodiment may be applied to wired/wireless electronic appliances, For example, a mobile electronic appliance.

FIG. 15is a diagram illustrating an example of a data processing system including a memory system according to an embodiment of the invention.FIG. 15may be a solid state drive (SSD).

Referring toFIG. 15, an SSD6300may include a memory device6340which may include a plurality of nonvolatile memories NVM and a controller6320. The controller6320may correspond to the controller130in the memory system110described above with reference toFIG. 1, and the memory device6340may correspond to the memory device150in the memory system110described above with reference toFIG. 1.

The controller6320may be connected with the memory device6340through a plurality of channels CH1to CHi. The controller6320may include a processor6321, a buffer memory6325, an error correction code (ECC) circuit6322, a host interface6324, and a nonvolatile memory (NVM) interface as a memory interface6326coupled via an internal bus.

The buffer memory6325temporarily stores data received from a host6310or data received from a plurality of nonvolatile memories NVMs included in the memory device6340, or temporarily stores metadata of the plurality of nonvolatile memories NVMs. For example, the metadata may include map data including mapping tables. The buffer memory6325may be implemented with a volatile memory such as, but not limited to, a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) SDRAM, a low power double data rate (LPDDR) SDRAM and a graphic random access memory (GRAM) or a nonvolatile memory such as, but not limited to, a ferroelectric random access memory (FRAM), a resistive random access memory (ReRAM), a spin-transfer torque magnetic random access memory (STT-MRAM) and a phase change random access memory (PRAM). While it is illustrated inFIG. 15, for the sake of convenience in explanation, that the buffer memory6325is disposed inside the controller6320, it is to be noted that the buffer memory6325may be disposed outside the controller6320.

The ECC circuit6322calculates error correction code values of data to be programmed in the memory device6340in a program operation, performs an error correction operation for data read from the memory device6340, based on the error correction code values, in a read operation, and performs an error correction operation for data recovered from the memory device6340in a recovery operation for failed data.

The host interface6324provides an interface function with respect to an external device such as the host6310. The nonvolatile memory interface6326provides an interface function with respect to the memory device6340which is connected through the plurality of channels CH1to CHi.

As a plurality of SSDs6300to each of which the memory system110described above with reference toFIG. 1is applied are used, a data processing system such as a redundant array of independent disks (RAID) system may be implemented. In the RAID system, the plurality of SSDs6300and an RAID controller for controlling the plurality of SSDs6300may be included. In the case of performing a program operation by receiving a write command from the host6310, the RAID controller may select at least one memory system (For example, at least one SSD6300) in response to the RAID level information of the write command received from the host6310, among a plurality of RAID levels (for example, the plurality of SSDs6300) and may output data corresponding to the write command, to the selected SSD6300, In the case of performing a read operation by receiving a read command from the host6310, the RAID controller may select at least one memory system (For example, at least one SSD6300) in response to the RAID level information of the write command received from the host6310, among the plurality of RAID levels (for example, the plurality of SSDs6300), and may provide data outputted from the selected SW6300, to the host6310.

FIG. 16is a diagram illustrating another example of a data processing system including the memory system according to an embodiment of the present invention.FIG. 16is a drawing schematically illustrating an embedded multimedia card (eMMC) to which a memory system according to an embodiment is applied.

Referring toFIG. 16, an eMMC6400includes a memory device6440which is implemented with at least one NAND flash memory, and a controller6430. The controller6430may correspond to the controller130in the memory system110described above with reference toFIG. 1, and the memory device6440may correspond to the memory device150in the memory system110described above with reference toFIG. 1.

In detail, the controller6430may be connected with the memory device6440through a plurality of channels. The controller6430may include a core6432, a host interface6431, and a memory interface such as a NAND interface6433.

The core6432may control the operations of the eMMC6400. The host interface6431may provide an interface function between the controller6430and a host6410. The NAND interface6433may provide an interface function between the memory device6440and the controller6430. For example, the host interface6431may be a parallel interface such as an MMC interface, as described above with reference toFIG. 1, or a serial interface such as an ultra-high speed class 1 (UHS-I)/UHS class 2 (UHS-II) and a universal flash storage (UFS) interface.

FIG. 17is a diagram illustrating another example of a data processing system including a memory system according to an embodiment of the present invention.FIG. 16is a drawing schematically illustrating a universal flash storage (UFS) to which the memory system, according to the embodiment is applied.

Referring toFIG. 17, a UFS system6500may include a UFS host6510, a plurality of UFS devices6520and6530, an embedded UFS device6540and a removable UFS card6550. The UFS host6510may be an application processor of wired/wireless electronic appliances, for example, a mobile electronic appliance.

The UFS host6510, the UFS devices6520and6530, the embedded UFS device6540and the removable UFS card6550may respectively communicate with external devices such as wired/wireless electronic appliances (for example, a mobile electronic appliance), through a UFS protocol. The UFS devices6520and6530, the embedded UFS device6540and the removable UFS card6550may be implemented with the memory system110described above with reference toFIG. 1, for example, as the memory card system6100described above with reference toFIG. 13. The embedded UFS device6540and the removable UFS card6550may communicate through another protocol other than the UFS protocol. For example, the embedded UFS device6540and the removable UFS card6550may communicate through various card protocols such as, but not limited to, USB flash drives (UFDs), multimedia card (MMC), secure digital (SD), mini SD and Micro SD.

FIG. 18is a diagram illustrating an example of a data processing system including the memory system according to an embodiment of the present invention.FIG. 18is a drawing schematically illustrating a user system to which the memory system according to the embodiment is applied.

Referring toFIG. 18, a user system6600may include an application processor6630, a memory module6620, a network module6640, a storage module6650, and a user interface6610.

The application processor6630may drive components included in the user system6600and an operating system (OS). For example, the application processor6630may include controllers for controlling the components included in the user system6600, interfaces, graphics engines, and so on. The application processor6630may be provided by a system-on-chip (SoC).

The memory module6620may operate as a main memory, a working memory, a buffer memory or a cache memory of the user system6600. The memory module6620may include a volatile random access memory such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a low power double data rate (LPDDR) SDRAM, an LPDDR2 SDRAM and an LPDDR3 SDRAM or a nonvolatile random access memory such as a phase change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM) and a ferroelectric random access memory (FRAM). For example, the application processor6630and the memory module6620may be mounted by being packaged on the basis of a package-on-package (POP).

The network module6640may communicate with external devices. For example, the network module6640may support not only wired communications but also various wireless communications such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (WiMAX), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), and so on, and may thereby communicate with wired/wireless electronic appliances, For example, a mobile electronic appliance. According to this fact, the memory system and the data processing system according to the embodiment may be applied to wired/wireless electronic appliances. The network module6640may be included in the application processor6630.

The storage module6650may store data such as data received from the application processor6530, and transmit data stored therein, to the application processor6530. The storage module6650may be realized by a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash memory, a NOR flash memory and a 3-dimensional NAND flash memory. The storage module6650may be provided as a removable storage medium such as a memory card of the user system6600and an external drive. For example, the storage module6650may correspond to the memory system110described above with reference toFIG. 1, and may be implemented with the SSD, eMMC and UFS described above with reference toFIGS. 15 to 17.

In the case where the memory system110described above with reference toFIG. 1is applied to the mobile electronic appliance of the user system6600according to an embodiment, the application processor6630may control the operations of the mobile electronic appliance, and the network module6640as a communication module may control wired/wireless communication with an external device, as described above. The user interface6610as the display/touch module of the mobile electronic appliance displays data processed by the application processor6630or supports input of data from a touch panel.

In accordance with various embodiments, the memory system may update the meta-data without generating a meta-log, Hence, resources required to manage meta-logs and the meta-data in the memory system may be reduced.

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the following claims.