Nonvolatile memory devices having control electrodes configured to inhibit parasitic coupling capacitance

Non-volatile memory devices include a substrate with first and second semiconductor active regions therein. These active regions are separated from each other by a trench isolation region, which has a recess therein that extends along its length. First and second floating gate electrodes are provided. These first and second floating gate electrodes extend on the first and second semiconductor active regions, respectively. A control electrode is provided that extends between the first and second floating gate electrodes and into the recess in the trench isolation region. The recess in the trench isolation region is sufficiently deep so that the control electrode, which extends into the recess, operates to reduce (e.g., block) a parasitic coupling capacitance between the first and second floating gate electrodes.

REFERENCE TO PRIORITY APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2006-101966, filed Oct. 19, 2006, the entire contents of which are hereby incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to memory devices and methods of forming same and, more particularly, to non-volatile memory devices and methods of forming non-volatile memory devices.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are generally classified as volatile memory devices and nonvolatile memory devices. Volatile memory devices lose stored data when power is turned off, but nonvolatile memory devices retain stored data even after power is turned off. Flash memory devices, like general nonvolatile memory devices, can be classified into a floating gate type and a charge trap type, depending on the kinds of data storage layers constituting a unit cell.

FIG. 1is a partial schematic perspective view of a floating gate type flash memory device, illustrating a relationship between a floating gate voltage (Vfg) and parasitic capacitances (CFGA, CFGW). Referring toFIG. 1, a tunnel oxide layer17, a floating gate19, an inter-gate insulating layer27and a control gate29are sequentially formed over an active region9to thereby define a device isolation layer13formed on a semiconductor substrate1. Here, the inter-gate insulating layer27may be formed as an oxide-nitride-oxide (ONO) layer. The active region9extends in a first direction (DA), which is a bitline direction, and the control gate29extends in a second direction (DW), which is a word line direction. An interlayer insulating layer27is interposed between the floating gates19, as illustrated.

Reference symbols V and C illustrated inFIG. 1show voltage and capacitance references. VFGdenotes a voltage of the floating gate disposed in a central position (hereinafter, the central floating gate) among nine floating gates. VAdenotes voltages of the floating gates adjacent in the first direction (DA) with respect to the central floating gate, and VWdenotes voltage of the floating gate adjacent in the second direction (DW) with respect to the central floating gate. CFGAdenotes a parasitic capacitance caused between the floating gates adjacent in the first direction (DA), and CFGWdenotes a parasitic capacitance caused between the floating gates adjacent in the second direction (DW). As understood by those skilled in the art, the parasitic capacitances increase as the high integration of the memory devices is increased. As a distance between the active region9and an inter-gate insulating layer27is shortened, charges in the active region9may be trapped in the inter-gate insulating layer27and cause malfunction of a memory cell. Therefore, reliability and operational characteristics of the memory device may be degraded.

SUMMARY OF THE INVENTION

Embodiments of the present invention include non-volatile memory devices that are configured to have reduced parasitic capacitance between floating gate electrodes. According to some of these embodiments, a non-volatile memory device is provided having a substrate with first and second semiconductor active regions therein. These active regions are separated from each other by a trench isolation region, which has a recess therein that extends along its length. First and second floating gate electrodes are also provided. These first and second floating gate electrodes extend on the first and second semiconductor active regions, respectively. A control electrode is provided that extends between the sidewalls of the first and second floating gate electrodes and into the recess in the trench isolation region. In particular, the recess in the trench isolation region is sufficiently deep so that the control electrode, which extends into the recess, operates to reduce (e.g., block) a parasitic coupling capacitance between the sidewalls of the first and second floating gate electrodes. For example, the recess may be sufficiently deep so that a first portion of the trench isolation region extends between a first sidewall of the control electrode (in the recess) and a sidewall of the first floating gate electrode and a second portion of the trench isolation region extends between a second sidewall of the control electrode (in the recess) and a sidewall of the second floating gate electrode.

According to aspects of these embodiments, a first sidewall of the trench isolation region defines an interface with a first sidewall of the first floating gate electrode and a width of the first floating gate electrode is tapered to be narrower at its top relative to its bottom. According to additional aspects of these embodiments, a width of the first floating gate electrode is greater than a width of the first semiconductor active region.

According to additional embodiments of the invention, a non-volatile memory device is provided with a semiconductor substrate having a trench therein that is at least partially filled with an electrically insulating trench isolation region. The trench isolation region has a trench-shaped recess therein that extends along its length. A first floating gate electrode extends on a first portion of the semiconductor substrate extending adjacent the trench isolation region and a control electrode is provided that extends in the trench-shaped recess and on the first floating gate electrode. A second floating gate electrode is also provided on a second portion of the semiconductor substrate, which extends adjacent the trench isolation region. According to aspects of these embodiments, the first and second floating gate electrodes have opposing sidewalls and a center of the trench-shaped recess is located about equidistant from the opposing sidewalls.

Still further embodiments of the present invention include methods of forming non-volatile memory devices. Some of these methods include forming first and second trench isolation regions at side-by-side locations in a semiconductor substrate to thereby define a semiconductor active region therebetween. A floating gate electrode is formed on an upper surface of the semiconductor active region and an electrically insulating layer is formed on sidewalls and an upper surface of the floating gate electrode. The electrically insulating layer is etched back to define sidewall insulating spacers on sidewalls of the floating gate electrode. The upper surfaces of the first and second trench isolation regions are selectively etched-back to define trench-shaped recesses therein. This etching step is performed using the sidewall insulating spacers as an etching mask. These methods also include removing the sidewall insulating spacers to expose the sidewalls of the floating gate electrode and etching back the sidewalls of the floating gate electrode for a sufficient duration so that the floating gate electrode is tapered to be narrower at its top relative to its bottom. Alternative methods may also include removing the sidewall insulating spacers to expose the sidewalls of the floating gate electrode and lining the trench-shaped recesses with an inter-gate dielectric layer. The trench-shaped recesses are filled with portions of a control electrode, which operates to block parasitic capacitance (in the word line direction) between adjacent floating gate electrodes.

Still further embodiments of the invention include forming a mask pattern on a surface of a semiconductor substrate and selectively etching the surface of the semiconductor substrate to thereby define first and second trenches at side-by-side locations in the semiconductor substrate, using the mask pattern as an etching mask. The first and second trenches and openings in the mask pattern are then filled with first and second trench isolation regions, respectively. The mask pattern is removed to expose sidewalls of the first and second trench isolation regions. The exposed sidewalls of the first and second trench isolation regions are then recessed. First and second floating gate electrodes are formed against the recessed sidewalls of the first and second trench isolation regions, respectively. The upper surfaces of the first and second trench isolation regions are etched-back to expose sidewalls of the first and second floating gate electrodes. An electrically insulating layer is formed on the exposed sidewalls and upper surfaces of the first and second floating gate electrodes. The electrically insulating layer is then etched back to define sidewall insulating spacers on sidewalls of the first and second floating gate electrodes. Upper surfaces of the first and second trench isolation regions are then selectively etched to define trench-shaped recesses therein. This etching step uses the sidewall insulating spacers as an etching mask. According to some additional embodiments of the invention, the sidewall insulating spacers are removed to expose the sidewalls of the floating gate electrode and the sidewalls of the floating gate electrode are etched back for a sufficient duration so that the floating gate electrode is tapered to be narrower at its top relative to its bottom.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

It will be understood that, although the terms first, second and the like may be used herein to describe various regions, layers, and the like, these regions, layers, and the likes should not be limited by these terms. These terms are only used to distinguish one region, layer, and the like from another region, layer, and the like. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or a third layer between intervening layers may also be present. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

FIG. 2is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention, taken along a word line direction. Referring toFIG. 2, a device isolation layer113in a semiconductor substrate101defines active regions109of the device. This device isolation layer113is illustrated as including a plurality of trench isolation regions that fill respective trenches107. A gate insulating layer117and a floating gate electrode119are formed on the active region109. A width of the floating gate119may be greater than an upper surface of the active region109. The gate insulating layer117may be formed as a tunnel oxide layer.

The device isolation layer113may include a lower insulating pattern111and an upper insulating pattern112. The lower insulating pattern111and the upper insulating pattern112may be formed of materials having different electrical, chemical or other physical characteristics. For example, the lower insulating pattern111may include a material having excellent gap-filling performance and the upper insulating pattern112may include a material that is highly resistant to wet etching using an etchant such as phosphoric acid and/or hydrofluoric acid.

The upper insulating pattern112includes a recess region125disposed between the floating gates119. As illustrated, the upper insulating pattern112is interposed between sidewalls of the recess region125and the floating gate119(or gate insulating layer117). A bottom surface of the upper insulating pattern112may be lower than that of the gate insulating layer117and a bottom surface of the recess region125may be lower than that of the floating gates119.

An inter-gate insulating layer127is disposed along both sidewalls and the bottom surface of the recess region125, an upper surface of the upper insulating pattern112, and sidewalls and upper surfaces of the floating gates119. A word line129crosses over the active regions109and extends on the inter-gate insulating layer127. The word line129extends downward between the floating gates119. A protrusion portion130of the word line129is inserted into the recess region125of the upper insulating pattern112. A bottom surface of the protrusion portion130may be lower than that of the floating gate119. The word line129functions as a control electrode with respect to the floating gate119.

This protrusion portion130of the word line129operates to reduce a parasitic coupling capacitance between adjacent floating gate electrodes119by blocking direct capacitive coupling between opposing sidewalls of adjacent floating gate electrodes119.

Furthermore, increased lifetime of the non-volatile memory device can be achieved by providing portions of the insulating pattern112between the recess125and the active regions109. These portions of the insulating pattern112operate to block parasitic charge transfer from the active regions109to the inter-gate insulating layer127during repeated program and erase operations.

Referring now toFIG. 3, a nonvolatile memory device according to an additional embodiment of the present invention is illustrated as being similar to the embodiment ofFIG. 2, however, the shape of the floating gate electrode119is modified to include a lower conductive pattern119_1and an upper conductive pattern119_2. As illustrated byFIG. 3, a width of the lower conductive pattern119_1is greater than a width of the active region109and greater than a width of the upper conductive pattern119_2. To sustain high performance device characteristics, a width of the upper conductive pattern119_2is in a range from about 0.5 times to about 0.7 times a width of the lower conductive pattern119_1. By forming the upper conductive patterns119_2to be narrower patterns, the parasitic gate-to-gate capacitance between adjacent floating gate electrodes119can be reduced without significantly reducing the inter-gate coupling between each floating gate electrode119and an overlapping word line/control gate129.

Referring now toFIG. 4, a nonvolatile memory device according to an additional embodiment of the present invention is illustrated as similar to the embodiment ofFIG. 3, however, a lower conductive pattern119_1is illustrated as having an equivalent width to the active region109. Moreover, the sidewalls of the active region109are self-aligned to the sidewalls of the lower conductive pattern119_1. This self-alignment is achieved using the fabrication techniques illustrated byFIGS. 16-20, which are described more fully hereinbelow.

Methods of forming the nonvolatile memory device ofFIG. 2will now be described more fully with reference toFIGS. 5-11. In particular,FIG. 5illustrates the steps of forming a pad oxide layer and a mask layer on a semiconductor substrate101and then photolithographically patterning these layers to define a pad oxide pattern103and a mask pattern105. The pad oxide layer may be formed as a thermal oxide layer, which operates to inhibit interface stress at a surface of the semiconductor substrate101. The mask layer may be formed as a polysilicon layer, an antireflective coating layer, a silicon nitride layer or a composite of these layers, for example. An etching step is then performed to define a plurality of isolation trenches107in the substrate101. These trenches107may be stripe-shaped trenches that extend in a third dimension (not shown). This etching step, which is preferably performed using the pad oxide pattern103and the mask pattern105as an etching mask, also results in the definition of a plurality of active regions109having expose sidewalls.

Referring now toFIG. 6, lower and upper electrically insulating patterns111and112are then deposited, in sequence, in the trenches107. These lower insulating patterns111may be formed of a material having good gap-filling characteristics (i.e., low tendency to void formation) and the upper insulating patterns112may be formed of a material that is highly resistant to etching (e.g., wet etching). Such etching steps may include exposing the upper insulating patterns112to a wet etchant such as phosphoric acid or hydrofluoric acid. The lower insulating patterns111may be formed by filling the isolation trenches107with an undoped silicate glass (USG) layer and then recessing (e.g., etching back) the USG layer to thereby define the lower insulating patterns112. A high density plasma (HDP) oxide layer may then be deposited on the lower insulating patterns111and then planarized for a sufficient duration to expose upper surfaces of the mask pattern105, and thereby define the upper insulating patterns112.

Referring now toFIG. 7, an etching process is performed to remove the mask pattern105and the pad oxide pattern103in sequence and thereby define a plurality of gap regions115that expose upper surfaces of the active regions109. As illustrated, this etching process may result in the lateral etching of the upper insulating patterns112, which means the gap regions115may have a larger width than the upper surfaces of the active regions109. Thereafter, as illustrated byFIG. 8, a plurality of gate insulating layers117(e.g., tunnel oxide layers) and a plurality of floating gate electrodes119are formed in the gap regions115. These gate insulating layers117may be formed by performing a thermal oxidation process on the exposed upper surfaces of the active regions109. The floating gate electrodes119may be formed by depositing a polysilicon layer into the gap regions115and then planarizing the polysilicon layer to expose the upper insulating patterns112.

As illustrated byFIG. 9, an etching step is then performed to etch-back the upper insulating patterns112so that upper sidewalls of the floating gate electrodes119are exposed. A molding insulating layer121is then conformally deposited on the upper surfaces and sidewalls of the floating gate electrodes119and on upper surfaces of recessed upper insulating patterns112. The molding insulating layer121may be formed of a material having an etching selectively with respect to the upper insulating patterns112. For example, the molding insulating layer121may be formed of a nitride layer or an oxide layer that is more susceptible to a wet etchant relative to the upper insulating patterns112.

Referring now toFIGS. 10-11, the molding insulating layer121ofFIG. 9is anisotropically etched to define a plurality of molding spacers122that cover portions of the sidewalls of the floating gate electrodes119. The definition of these molding spacers122also results in the exposure of the upper insulating patterns112. These exposed portions of the upper insulating patterns112are then etched using the molding spacers122as an etching mask. This etching results in the formation of recesses125in upper portions of the upper insulating patterns112. As illustrated, these recesses125may have bottoms that are below the lower surfaces of the floating gate electrodes119. The molding spacers122are then removed (at least partially) using an etching process that exposes the sidewalls of the floating gate electrodes119. This etching process is preferably performed using an etchant (e.g., isotropic wet etchant) that does not significantly etch sidewalls of the recesses125in the upper portions of the upper insulating patterns112. For example, in the event the molding spacers122are formed of a nitride layer, the etching process can include an etchant containing phosphoric acid and the upper insulating patterns112can include a material that is relatively resistant to phosphoric acid. However, in the event the molding spacers122are formed of an oxide layer, the etching process can include an etchant containing hydrofluoric acid and the upper insulating patterns112can include a material that is relatively resistant to hydrofluoric acid.

Referring again toFIG. 2, an inter-gate insulating layer127is then conformally deposited on the intermediate structure ofFIG. 11. As illustrated, this inter-gate insulating layer127is deposited on the floating gate electrodes119(upper surfaces and sidewalls) and the tipper insulating patterns112. This inter-gate insulating layer127also extends into the recesses125, as illustrated. The inter-gate insulating layer127may be formed as a composite of an oxide layer/nitride layer/oxide layer (i.e., ONO layer). A conductive layer is then deposited on the inter-gate insulating layer127and patterned to define a word line/control gate pattern129. This patterning of the word line/control gate pattern129may include patterning the floating gate pattern119into a plurality of floating gate electrodes119having dimensions that are self-aligned to the word line/control gate pattern129. As illustrated, the word line/control gate pattern129extends downward between the floating gates119. In particular, protruding portions130of the word line/control gate pattern129extend into the recesses125. The word line/control gate pattern129may be formed as a polysilicon layer, a metal layer and/or a silicide layer.

Alternatively, as illustrated byFIG. 12, the exposed sidewalls of the floating gate patterns119ofFIG. 11may be etched-back using an isotropic wet etching process. This etching process results in the formation of a floating gate pattern119having a lower conductive pattern119_1and an upper conductive pattern119_2having different widths. This etching process may include using an etchant (e.g., wet etchant) that does not appreciably etch the upper insulating patterns112or the sidewalls of the recesses125. Thereafter, as illustrated byFIG. 3, an inter-gate insulating layer127is conformally deposited on the intermediate structure ofFIG. 12. As illustrated, this inter-gate insulating layer127is deposited on the floating gate pattern119(upper surfaces and sidewalls) and the upper insulating patterns112. This inter-gate insulating layer127also extends into the recesses125, as illustrated. The inter-gate insulating layer127may be formed as a composite of an oxide layer/nitride layer/oxide layer (i.e., ONO layer). A conductive layer is then deposited on the inter-gate insulating layer127and patterned to define a word line/control gate pattern129. This patterning of the word line/control gate pattern129includes patterning the floating gate pattern119into a plurality of floating gate electrodes119having dimensions that are self-aligned to the word line/control gate pattern129. As illustrated, the word line/control gate pattern129extends downward between the floating gates119. In particular, protruding portions130of the word line/control gate pattern129extend into the recesses125. The word line/control gate pattern129may be formed as a polysilicon layer, a metal layer and/or silicide layer.

Referring now to FIGS.8and13-15, an alternative embodiment of a method of forming the device ofFIG. 3may include selectively etching back the upper insulating patterns112to expose sidewalls of the floating gate pattern119and then selectively etching the sidewalls of the floating gate pattern to define the lower conductive pattern119_1and the narrower upper conductive pattern119_2. Thereafter, as illustrated byFIGS. 14-15, a molding insulating layer121is then conformally deposited on the upper surfaces and sidewalls of the upper conductive pattern119_2and on upper surfaces of recessed upper insulating patterns112. The molding insulating layer121may be formed of a material having an etching selectively with respect to the upper insulating patterns112. For example, the molding insulating layer121may be formed of a nitride layer or an oxide layer that is more susceptible to a wet etchant relative to the upper insulating patterns112. Thereafter, as illustrated byFIG. 15, the molding insulating layer121is anisotropically etched to define a plurality of molding spacers122that cover portions of the sidewalls of the floating gate electrodes119. The definition of these molding spacers122also results in the exposure of the upper insulating patterns112. These exposed portions of the upper insulating patterns112are then etched using the molding spacers122as an etching mask. This etching results in the formation of recesses125in upper portions of the upper insulating patterns112. As illustrated, these recesses125may have bottoms that are below the lower surfaces of the floating gate electrodes119. The molding spacers122are then removed (at least partially) using an etching process that exposes the sidewalls of the floating gate electrodes119. This removal of the molding spacers122results in the definition of the intermediate structure ofFIG. 12, which can be further processed as illustrated byFIG. 3.

FIGS. 16-20are cross-sectional views of intermediate strictures that illustrate methods of forming the non-volatile memory device ofFIG. 4. As illustrated byFIG. 16, a gate insulating layer117and a floating gate pattern119are formed in sequence on a semiconductor substrate101. The floating gate pattern119is then used as etch mask to define a plurality of trenches107(e.g., stripe-shaped trenches) within the semiconductor substrate101. These trenches107define a plurality of semiconductor active regions therebetween, which extend opposite corresponding portions of the floating gate pattern119. By using the floating gate pattern119as an etching mask to define a plurality of trenches107, the active regions become self-aligned to the floating gate pattern119. Referring now toFIG. 17, a lower insulating pattern111is formed within lower portions of the trenches107and an upper insulating pattern112is formed on the lower insulating pattern111, as illustrated. The lower insulating pattern111may be formed of a material having good gap-filling characteristics (i.e., low tendency to void formation) and the upper insulating pattern112may be formed of a material that is highly resistant to etching (e.g., wet etching), as previously described. An undoped silicate glass (USG) layer may be used for the lower insulating pattern111and a high-density plasma (HDP) oxide layer may be used for the floating gate pattern119.

Referring now toFIG. 18, an etching process is performed on the intermediate structure ofFIG. 17in order to etch-back the upper insulating layer112and expose upper sidewalls of the floating gate pattern119. A molding insulating layer121is then conformally deposited on the exposed upper sidewalls and upper surfaces of the floating gate pattern119. The molding insulating layer121may be formed of a material having an etch selectivity with respect to the upper insulating pattern112. For example, the molding insulating layer121may be formed as a nitride layer or an oxide layer, depending on the material of the upper insulating pattern112.

An anisotropic etching step is then performed on the molding insulating layer121. This etching step is performed for a sufficient duration to thereby define molding spacers122on sidewalls of the floating gate pattern119, as illustrated byFIG. 19. These molding spacers122are then used as an etching mask to selectively etch back exposed portions of the upper insulating pattern112. This selective etching of the upper insulating pattern112results in the formation of recesses125within the upper surfaces of the upper insulating pattern112, which are self-aligned to the molding spacers122. As illustrated, these recesses125may have bottoms that are lower than the underside surfaces of the floating gate pattern119, which interface with the gate insulating layer117.

Referring now toFIG. 20, an etching process is performed on the intermediate structure ofFIG. 19to thereby remove the molding spacers122and expose sidewalls of the floating gate pattern119. This etching process (e.g., isotropic wet etching) is performed using an etchant that may selectively remove the molding spacers122and not substantially etch the upper insulating pattern112or widen the recesses125. For example, when the molding spacers122are formed of a nitride layer, the wet etching process can use an etchant containing phosphoric acid. Alternatively, when the molding spacers122are formed of an oxide layer, the wet etching process can use an etchant containing hydrofluoric acid.

Thereafter, as illustrated byFIG. 4, an inter-gate insulating layer127is conformally deposited on the intermediate structure ofFIG. 20. This inter-gate insulating layer127is deposited on the floating gate pattern119(upper surfaces and sidewalls) and the upper insulating patterns112. This inter-gate insulating layer127also extends into the recesses125, as illustrated. The inter-gate insulating layer127may be formed as a composite of an oxide layer/nitride layer/oxide layer (i.e., ONO layer). A conductive layer is then deposited on the inter-gate insulating layer127and patterned to define a word line/control gate pattern129. This patterning of the word line/control gate pattern129includes patterning the floating gate pattern119into a plurality of floating gate electrodes119having dimensions that are self-aligned to the word line/control gate pattern129. As illustrated, the word line/control gate pattern129extends downward between the floating gates119. In particular, protruding portions130of the word line/control gate pattern129extend into the recesses125. The word line/control gate pattern129may be formed as a polysilicon layer, a metal layer and/or silicide layer.