PROGRESSIVE ENVELOPE TRACKING WITH DELAY COMPENSATION

A progressive envelope tracking (ET) with delay compensation includes an ET integrated circuit (IC) (ETIC) that is a progressive ETIC that switches between different driver amplifiers having different associated offset voltages based on a tracking signal (e.g., Vramp) from a baseband transceiver. To make sure that desired changes to the offset voltage occur contemporaneously with an input signal for the driver amplifiers, a delay may be added to the input signal for the driver amplifiers. By adding and controlling this delay to the input to the driver amplifiers, the changes to the offset voltage will track the changes to the input signal at the driver amplifiers and overall efficiency of the ETIC may be improved.

FIELD OF THE DISCLOSURE

The technology of the disclosure relates generally to an envelope tracking (ET) radio frequency (RF) front-end circuit.

BACKGROUND

Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

A fifth-generation new radio (5G-NR) wireless communication system is widely regarded as a technological advancement that can achieve significantly higher data throughput, improved coverage range, enhanced signaling efficiency, and reduced latency compared to the existing third-generation (3G) and fourth-generation (4G) communication systems. A 5G-NR mobile communication device usually transmits and receives a radio frequency (RF) signal(s) in a millimeter wave (mmWave) RF spectrum that is typically above six gigahertz (6 GHz). Notably, the RF signal(s) transmitted in the mmWave RF spectrum may be more susceptible to propagation attenuation and interference that can result in substantial reduction in data throughput. To help mitigate propagation attenuation and maintain desirable data throughput, the 5G-NR mobile communication device may be configured to transmit the RF signal(s) simultaneously from multiple antennas using such spatial multiplexing schemes as multiple-input multiple-output (MIMO) and RF beamforming. As such, the 5G-NR mobile communication device needs to employ multiple RF power amplifiers in an RF front-end module (FEM) to amplify the RF signal(s) before feeding to the multiple antennas.

Envelope tracking (ET) is a power management technique designed to improve operating efficiency of the RF power amplifiers. Specifically, the power amplifiers simultaneously amplify the RF signal(s) based on multiple ET voltages that track a time-variant power envelope of the RF signal(s). Understandably, the better the ET voltages can track the time-variant power envelope, the more efficient the power amplifier can operate.

When there are a low number of resource blocks in the FEM, a very robust ET circuit may be over-engineered and inefficient from a power usage perspective. Various ways to improve efficiency have been proposed including modulation of an offset voltage within a conditioning circuit that generates the control signal for the RF power amplifiers. Room remains for improvements in such offset voltage modulation.

SUMMARY

Embodiments of the disclosure relate to progressive envelope tracking (ET) with delay compensation. In an exemplary aspect, an ET integrated circuit (IC) (ETIC) is a progressive ETIC that switches between different driver amplifiers having different associated offset voltages based on a tracking signal (e.g., Vramp) from a baseband transceiver. To make sure that desired changes to the offset voltage occur contemporaneously with an input signal for the driver amplifiers, a delay may be added to the input signal for the driver amplifiers. By adding and controlling this delay to the input to the driver amplifiers, the changes to the offset voltage will track the changes to the input signal at the driver amplifiers and overall efficiency of the ETIC may be improved.

In one aspect, an ETIC is provided. The ETIC comprises an input configured to receive a vramp signal from a baseband transceiver. The ETIC also comprises a first driver amplifier coupled to a first offset capacitor and a first variable feedback circuit. The ETIC also comprises a second driver amplifier coupled to a second offset capacitor, the first variable feedback circuit, and a second variable feedback circuit. The ETIC also comprises a controller circuit. The controller circuit is configured to switch between the first driver amplifier and the second driver amplifier. The controller circuit is also configured to adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable feedback circuit to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit.

In another aspect, a wireless device is provided. The wireless device comprises a baseband transceiver configured to produce a vramp signal. The wireless device also comprises an ETIC coupled to the baseband transceiver. The ETIC comprises an input configured to receive the vramp signal. The ETIC also comprises a first driver amplifier coupled to a first offset capacitor and a first variable feedback circuit. The ETIC also comprises a second driver amplifier coupled to a second offset capacitor, the first variable feedback circuit, and a second variable feedback circuit. The ETIC also comprises a controller circuit. The controller circuit is configured to switch between the first driver amplifier and the second driver amplifier. The controller circuit is also configured to adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable feedback circuit to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit.

DETAILED DESCRIPTION

Embodiments of the disclosure relate to progressive envelope tracking (ET) with delay compensation. In an exemplary aspect, an ET integrated circuit (IC) (ETIC) is a progressive ETIC that switches between different driver amplifiers having different associated offset voltages based on a tracking signal (e.g., Vramp) from a baseband transceiver. To make sure that desired changes to the offset voltage occur contemporaneously with an input signal for the driver amplifiers, a delay may be added to the input signal for the driver amplifiers. By adding and controlling this delay to the input to the driver amplifiers, the changes to the offset voltage will track the changes to the input signal at the driver amplifiers and overall efficiency of the ETIC may be improved.

Before addressing particular aspects of the present disclosure, an overview of a transmitter with a radio frequency (RF) front end circuit is provided inFIGS.1and2with a discussion of a conventional progressive ETIC provided inFIGS.3and4. A discussion of exemplary aspects of the present disclosure begins below with reference toFIG.5.

In this regard,FIG.1is a schematic diagram of an exemplary ET RF front-end circuit10configured according to an aspect of the present disclosure. The ET RF front-end circuit10is self-contained in a system-on-chip (SoC) or system-in-package (SiP), as an example, to provide all essential functions of an RF front-end module (FEM). Specifically, the ET RF front-end circuit10is configured to include an ETIC12, a target voltage circuit14, a local transceiver circuit16, and a number of power amplifiers18A(1)-18A(N). The ET RF front-end circuit10may also include a number of second power amplifiers18B(1)-18B(N). By packaging the ETIC12, the target voltage circuit14, the local transceiver circuit16, the power amplifiers18A(1)-18A(N), and the second power amplifiers18B(1)-18B(N) into the ET RF front-end circuit10, it is possible to reduce distance-related distortion in the aforementioned conventional implementation, thus helping to improve operating efficiency and linearity of the power amplifiers18A(1)-18A(N),18B(1)-18B(N).

The ETIC12is configured to generate a number of first ET voltages VCCOA-1-VCCOA-Nat a number of first output nodes NA1-1-NA1-N, respectively. The ETIC12is also configured to generate a second ET voltage VCCDAat a second output node NA2. The ETIC12generates both the first ET voltages VCCOA-1-VCCOA-Nand the second ET voltage VCCDAbased on a time-variant ET target voltage VTGTA, also sometimes referred to as Vramp. For a detailed description on specific embodiments of the ETIC12that generate the first ET voltages VCCOA-1-VCCOA-Nand the second ET voltage VCCDAbased on the time-variant ET target voltage VTGTA, please refer to U.S. patent application Ser. No. 17/142,507, entitled “ENVELOPE TRACKING POWER MANAGEMENT APPARATUS INCORPORATING MULTIPLE POWER AMPLIFIERS.”

The target voltage circuit14is configured to generate the time-variant ET target voltage VTGTAbased on an input signal20, which can be a modulated carrier signal at millimeter wave (mmWave) frequency, intermediate frequency (IF), or In-phase/Quadrature (I/Q) baseband frequency. In a non-limiting example, the target voltage circuit14includes an amplitude detection circuit22and an analog lookup table (LUT)24. The amplitude detection circuit22is configured to detect a number of time-variant amplitudes26of the input signal20, and the analog LUT24is configured to generate the time-variant ET target voltage VTGTAbased on the time-variant amplitudes26.

The local transceiver circuit16further produces RF signals62A(1)-62A(N) and62B(1)-62B(N) that are provided to the power amplifiers18A(1)-18A(N),18B(1)-18B(N), that are controlled by the various Vcc signals from the ETIC12. The power amplifiers18A(1)-18A(N) may include an array of amplifiers66,68as is well understood. Likewise, the power amplifiers18B(1)-18B(N) may include an array of amplifiers70,72as is well understood. A coupler circuit76may be used to provide a feedback signal78to a calibration circuit74, which helps the analog LUT24determine a correct VTGTA.

One or more of the ET RF front-end circuit10ofFIG.1can be provided in a wireless device (e.g., a smartphone) to help enhance RF performance and user experience. In this regard,FIG.2is a schematic diagram of a wireless device100that includes a number of ET RF front-end circuits102(1)-102(K), which can be any of the ET RF front-end circuit10ofFIG.1. Common elements betweenFIGS.1and2are shown therein with common element numbers and will not be re-described herein.

The wireless device100includes a baseband transceiver104that is separated from any of the ET RF front-end circuits102(1)-102(K). The baseband transceiver104is configured the generate the input signal20.

Each of the ET RF front-end circuits102(1)-102(K) is coupled to a first antenna array106and a second antenna array108. The first antenna array106includes a number of first antennas110(1)-110(N), each coupled to a respective one of antenna ports64A(1)-64A(N) and configured to radiate a respective one of RF signals62A(1)-62A(N) in a first polarization (e.g., horizontal polarization). The second antenna array108includes a number of second antennas112(1)-112(N), each coupled to a respective one of second antenna ports64B(1)-64B(N) and configured to radiate a respective one of second RF signals62B(1)-62B(N) in a second polarization (e.g., vertical polarization).

The ET RF front-end circuits102(1)-102(K) may be disposed in different locations in the wireless device100to help enhance RF performance and improve user experience. For example, some of the ET RF front-end circuits102(1)-102(K) may be provided on a top edge of the wireless device100, while some of the ET RF front-end circuits102(1)-102(K) are provided on a bottom edge of the wireless device100.

It should be appreciated that the ET RF front-end circuits are used to improve efficiency for the main power amplifier arrays used to transmit the signals. That is, by providing ‘just enough’ voltage Vcc to the power amplifiers at the times when the power amplifiers need the voltage, the power amplifiers do not ‘waste’ unneeded power from worst case, static Vcc levels. For example, if the power amplifier only needs three volts (3 V) to boost the transmit signal to a desired level, but Vcc is 5 V, the power amplifier has been provided excess voltage which is unused and wasted. By using ET, Vcc is controlled and the efficiency of the power amplifiers is improved.

While using ET does improve the efficiency of the system by improving the efficiency of the power amplifiers, the ETIC may introduce some inefficiencies. To assist in battery management for mobile computing devices, improving efficiency in the transceiver is generally considered desirable. One way to improve efficiency in the ETIC is through the use of progressive ET as better explained with reference toFIGS.3and4.

In this regard,FIG.3is a block diagram of an ETIC12that uses progressive ET. A target voltage (VTGTAalso referred to as Vramp) is provided to the ETIC12and received by a multiplexer130. The target voltage may initially be a differential signal, but the multiplexer130may transform the signal to a single-ended signal if desired. The multiplexer130may be coupled to a bandpass filter132, which blocks the signal at undesired frequencies. The bandpass filter132is coupled to an anti-aliasing filter (AAF)134which produces Vcc target. The Vcc target is provided to a first driver amplifier136(sometimes referred to as a horizontal amplifier H). The output of the first driver amplifier136may be coupled through a switch138to a ground140. When the switch138is open (i.e., not grounded), the first driver amplifier136outputs an amplified signal VparampHand is coupled to a first offset capacitor142. The first offset capacitor142also acts as a direct current (DC) block, allowing only alternating current (AC) signals to pass through. The first offset capacitor142is coupled to an output node144. The first offset capacitor142may be reasonably large, for example, on the order of two to three microfarads. A control signal Vcc is available at the output node144. The output node144is also coupled to a first feedback circuit146, which is coupled to the first driver amplifier136. The control signal Vcc is analogous to signals VCCOA-1-VCCOA-NofFIG.1.

With continued reference toFIG.3, the bandpass filter132is also coupled to a multiplier148which multiplies Vcc target by a factor K, where 0<K<1. K determines what percentage of Vcc is derived from the first driver amplifier136relative to the voltage provided at the first offset capacitor142as better explained below. The value K*Vcc target is provided to an adder150, which adds K*Vcc target with a signal Voffset0Target from a digital-to-analog converter (DAC)152to form a signal Voffset Target. The adder150is coupled to a controller circuit154. The controller circuit154has additional inputs from multiplexers156,158,160and provides an output to a multilevel boost charge pump162. The multilevel boost charge pump162may use one or more capacitors164(1)-164(M) to provide different levels of charge boost. The multilevel boost charge pump162may be connected to a voltage source such as Vbat. The multilevel boost charge pump162may also receive a signal VbatampH(voltage battery amplifier horizontal) and a feedback signal Vccfb from the output node144. The multilevel boost charge pump162may be coupled to a power inductor166through a switching circuit168. The power inductor166is coupled to the output node144to provide a base DC power level (albeit with some ripple) at the output node144. The multiplexer158receives and selects between voltage signals VparampHand VparampL. The multiplexer160receives and selects between current signals Iparamp_sense_Hand Iparamp_sense_L. The respective voltage and current values may be manipulated within the controller circuit154to help estimate a load seen by the output node144.

With continued reference toFIG.3, the AAF134is also coupled to a second driver amplifier170(sometimes referred to as the vertical amplifier, although L is used because V might be confused for voltage). The second driver amplifier170includes an output that is coupled to ground140through a switch172. When the switch172is open (e.g., not grounded), the second driver amplifier170produces a signal VparampL. In use, only one switch138or172will be open at a time. The second driver amplifier170is coupled to a second offset capacitor174, which is coupled to the output node144. The output node144is also coupled to a second feedback circuit176, which is coupled to an input of the second driver amplifier170. The second offset capacitor174is relatively smaller than the first offset capacitor142, and may be, for example on the order of twenty to forty nanofarad and thus, CoffsetL<<CoffsetH. The reduced capacitance of the second offset capacitor174may have some increase in the ripple voltage, but this can be offset by using a lower Vbatamp voltage. Both the first and second driver amplifiers136,170receive input signals Vbatamp1 and Vbatamp2.

In operation, the controller circuit154uses the switches138,172to control a signal path from the AAF134through one or the other of the driver amplifiers136,170to the output node144. It should be appreciated that Vcc at the output node144is the sum of an offset voltage created by the offset capacitors142,174and the Vparamp from the respective driver amplifiers136,170. This sum is better illustrated inFIG.4, where an output400of the second driver amplifier170is added to an offset voltage402from the second offset capacitor174to create Vcc signal404. Thus, the differently-valued offset capacitors142,174produce different offset voltages. Further, selection of a specific K allows the ratio of voltage provided by the driver amplifiers136,170relative to the offset capacitors142,174to be selected. A progressive ETIC12uses this difference to its advantage by switching between the driver amplifiers136,170based on which is more efficient. For more detail on a progressive ETIC, the interested reader is directed to U.S. Pat. No. 11,018,627, which is hereby incorporated by reference in its entirety.

While the ability to tune Vcc by changing with the offset voltage helps with the efficiency of driving the power amplifiers18A(1)-18A(N),18B(1)-18B(N), this solution raises other issues. Specifically, the signal entering the AAF134drives both the driver amplifiers136,170and is also provided to the controller circuit154. As illustrated inFIG.3, these two paths do not have the same length and thus have differing delays associated therewith. The delay through the driver amplifiers136,170is shown as Vcc_to_Vcctargetv_delay inFIG.3. Thus, changes in Vcc target from the bandpass filter132propagate fairly quickly to the output node144because only three elements (the AAF134, the driver amplifier136,170and the offset capacitor142,174) lie between the bandpass filter132and the output node144. In contrast, an offset loop delay (shown in dotted lines inFIG.3) goes through the multiplier148, the adder150, the controller circuit154, the multilevel boost charge pump162, the power inductor166, and back to the controller circuit154. The comparatively large number of elements through which this signal must pass before the switches138,172are controlled means that the delay for the offset loop delay is substantially larger than the Vcc_to_Vcctargetv_delay. This difference means that the driver amplifier136,170will be quite fast and will deliver most of the load current instead of the power inductor166, resulting in degraded operation.

In the abstract, there are a variety of ways to align the delays between the two paths, although two primary classifications exist. The first classification of solutions is to increase the bandwidth for the slow path as much as possible to speed up the data exchange. This increase in speed may be done by using a baseband controller in place of or in addition to a pulse width modulated (PWM) controller for the controller circuit154. While this approach may increase the bandwidth, such increases are not sufficient to offset the overall delay of the path. Alternatively, this increase in speed may be achieved by lowering the value of the power inductor166. However, changes in the power inductor166have other ramifications in terms of ripple. Another alternative is to decrease the value of the second offset capacitor174. Size constraints preclude the second offset capacitor174from being much less than the twenty to forty nanoFarads discussed above. Likewise, reducing the capacitance of the second offset capacitor174also has ripple ramifications. Another alternative is to increase the bandwidth within the controller circuit154by using a lower zero frequency for a loop filter. Again, this may decrease delay, but not enough. As still another option, the controller circuit154may try to use Vcc target instead of Vccfb to get a time advance equivalent of the Vccfb. However, since Vcc target is the target and not a feedback signal, this creates an open loop, which may not result in desired values. It should be appreciated that each of these possible ways to increase the bandwidth for the slow path comes with trade-offs, which under current design realities are unacceptable.

The second classification of solutions to align the delays is to reduce the bandwidth of the AAF134and the driver amplifier136,170. This approach proves to provide a more acceptable trade-off. Accordingly, exemplary aspects of the present disclosure provide time alignment between the paths by increasing a feedback capacitor and also adjusting the AAF to increase the delay from the bandpass filter to the driver amplifier. These changes also lower the output impedance for the amplifier and assist in ripple absorption. The feedback capacitor also acts like a pole in the driver amplifier transfer function.

In this regard,FIG.5illustrates a progressive ETIC200. Much of the structure of the progressive ETIC200is identical to the structure of ETIC12, with a few important modifications to provide delay compensation. A target voltage (VTGTAalso referred to as Vramp) is provided to the ETIC200and received by a multiplexer202. The target voltage may initially be a differential signal, but the multiplexer202may transform the signal to a single-ended signal if desired. The multiplexer202may be coupled to a bandpass filter204, which blocks the signal at undesired frequencies. The bandpass filter204is coupled to an AAF206with a node208therebetween. Vcc target is present at the node208, and the AAF206produces Vcc target. The Vcc target is provided to a first driver amplifier210(sometimes referred to as a horizontal amplifier H). The output of the first driver amplifier210may be coupled through a switch212to ground214. When the switch212is open (i.e., not grounded), the first driver amplifier210outputs an amplified signal VparampHand is coupled to a first offset capacitor216. The first offset capacitor216also acts as a DC block, allowing only AC signals to pass through. The first offset capacitor216is coupled to an output node218. The first offset capacitor216may be reasonably large, for example, on the order of two to three microfarads. A control signal Vcc is available at the output node218. The output node218is also coupled to a first variable feedback circuit220, which is coupled to the first driver amplifier210and to a second driver amplifier222.

With continued reference toFIG.5, the bandpass filter204provides a derivative of Vramp to a baseband controller (BBC)224A portion of a controller224circuit. The controller circuit224may further include a PWM controller224B, a Voffset loop controller224C, which allows programming of a bandwidth, and a dithering circuit224D. The bandpass filter204is also coupled to a multiplier226which multiplies Vcc target by a factor K, where 0<K<1. K determines what percentage of Vcc is derived from the driver amplifier210or222relative to the voltage provided at the first offset capacitor216as better explained below. The value K*Vcc target is provided to an adder228, which adds K*Vcc target with a signal Voffset0Target from a DAC230to form a signal Voffset Target. The value from the DAC230is a DC offset value. The adder228is coupled to the dithering circuit224D of the controller circuit224. The controller circuit224has additional inputs from a multiplexer232that selects between VparampHfrom the first driver amplifier210and VparampLfrom the second driver amplifier222. The controller circuit224also receives a sensed current signal Iparamp_sense from the driver amplifiers210,222. The PWM controller224B and the BBC224A output signals that are selected by a multiplexer234. The output of the multiplexer234is coupled to a multilevel boost charge pump236. The multilevel boost charge pump236may use one or more capacitors238(1)-238(P) to provide different levels of charge boost. The multilevel boost charge pump236may be coupled to a voltage source such as Vbat. The multilevel boost charge pump236may also receive a signal VbatampH(voltage battery amplifier horizontal). The multilevel boost charge pump236may be coupled to a power inductor240through a switching circuit242. The power inductor240is coupled to the output node218to provide a base DC power level at the output node218. The voltage and current values may be manipulated within the controller circuit224to help estimate a load seen by the output node218.

With continued reference toFIG.5, the AAF206is also coupled to a second variable feedback circuit244, which in turn is coupled to the second driver amplifier222(sometimes referred to as the vertical amplifier, although L is used because V might be confused for voltage). The second driver amplifier222produces the signal VparampL. While not shown, there may be a switch that couples the output of the second driver amplifier222to ground (analogous to the switch172inFIG.3). As with the ETIC12, these switches are used to toggle between the driver amplifiers210,222as desired. The second driver amplifier222is coupled to a second offset capacitor246, which is coupled to the output node218. The second offset capacitor246is relatively smaller than the first offset capacitor216, and may be, for example on the order of twenty to forty nanofarad and thus, CoffsetL<<CoffsetH. Delay paths250,252are illustrated inFIG.5as well. As previously explained, it is these different delay paths250,252which may create misalignment of control signals at the driver amplifier222.

Exemplary aspects of the present disclosure control the AAF206and the second variable feedback circuit244to control the delay of the Vcc_toVcctargetv_delay delay path250. Specifically, the controller circuit224may store, such as in a lookup table or the like, a modification to the second variable feedback circuit244based on frequency, voltage level, and/or other parameters. Then, when the controller circuit224receives the dVramp signal, the controller circuit224may send a signal to the second variable feedback circuit244to adjust one or more delay elements within the second variable feedback circuit244to cause the delay between the node208and the input of the second driver amplifier222(i.e., path250) to be equal to the delay between the node208and the change signal that causes the second offset capacitor246to be used (i.e., path252). Note further that the controller circuit224may also adjust the AAF206to introduce delay in path250.