Display backplane and fabrication method thereof, display panel and fabrication method thereof

The present disclosure provides a display backplane including an array substrate including at least one pixel unit each including at least one TFT; a planarization layer covering the array substrate; a pad layer including pads on the planarization layer, surface of the pad away from the planarization layer being first surface, each pixel unit being provided with one pad electrically coupled to a driving thin film transistor in a corresponding pixel unit through via hole penetrating through the planarization layer; a passivation layer covering the pad layer and including through holes, each pad corresponding to one through hole, such that the first surface of each pad is exposed through corresponding through hole, and area of top opening of through hole is smaller than area of bottom opening thereof. The present disclosure further provides a fabrication method of the display backplane, a display panel and a fabrication method thereof.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a National Phase Application filed under 35 U.S.C. 371 as a national stage of PCT/CN2020/122922 filed Oct. 22, 2020, the content of which is incorporated herein in its entirety by reference.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and particularly relates to a display backplane, a fabrication method of the display backplane, a display panel including the display backplane, and a fabrication method of the display panel.

BACKGROUND

Due to the advantages such as short response time, self-luminescence, and solid-state lighting, organic light-emitting diode (OLED) display panels are widely applied. With the consumers' pursuit of display effect, micro-light emitting diode (micro-LED) display panels have appeared on the basis of the OLED display panel.

How to improve the yield in fabricating micro-LED display panels becomes a technical problem to be solved urgently in the field.

SUMMARY

The purpose of the present disclosure is to provide a display backplane, a fabrication method of the display backplane, a display panel including the display backplane, and a fabrication method of the display panel.

As an aspect of the present disclosure, there is provided a display backplane, and the display backplane includes:

an array substrate including at least one pixel unit, and each pixel unit including at least one thin film transistor;

a planarization layer covering the array substrate;

a pad layer including a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to a driving thin film transistor in the pixel unit through a via hole which penetrates through the planarization layer; and

a passivation layer covering the pad layer and including a plurality of through holes, each of the pads corresponding to one through hole, such that the first surface of each of the pads is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole.

Optionally, an angle between a sidewall of the through hole and the first surface of the pad layer is between 10° and 80°.

Optionally, a material of the passivation layer is silicon nitride, and a thickness of the passivation layer is between 3000 angstroms and 4000 angstroms.

As a second aspect of the present disclosure, there is provided a display panel, including:

the display backplane according to the first aspect of the present disclosure;

an LED layer including at least one LED unit, wherein

each LED unit includes a plurality of LED pins, each of the plurality of LED pins corresponds to one pad, and a portion of each of the plurality of LED pins is arranged in a corresponding through hole and is electrically coupled to the pad.

Optionally, the LED pin includes a pin body and a flange disposed around the pin body, the flange being disposed in the corresponding through hole.

Optionally, the flange is disposed at an end of the pin body facing the pad, and a bottom surface of the flange and a bottom surface of the pin body are both soldered to a corresponding pad.

Optionally, a width of the flange is between 0.1 μm and 0.2 μm.

Optionally, the LED pin includes a pin core and a pin skin cladding the pin core, and a material of the pin skin is a material capable of realizing eutectic soldering.

Optionally, a material of the pin core is copper, and the material of the pin skin is selected from at least one of the following alloys: copper-nickel alloy, copper-tin alloy, and silver-tin alloy.

Optionally, a thickness of the pin skin is no more than one tenth of a diameter of the pin core.

Optionally, the pin core has a diameter between 5000 angstroms and 7000 angstroms.

Optionally, the LED is a micro-LED or a mini-LED.

As a third aspect of the present disclosure, there is provided a fabrication method of a display backplane, and the fabrication method includes:providing an array substrate, the array substrate including at least one pixel unit, each pixel unit including at least one thin film transistor, and the at least one thin film transistor including a driving thin film transistor;forming a planarization layer covering the array substrate, the planarization layer being formed with a plurality of via holes, each of the plurality of via holes corresponding to the driving thin film transistor in one pixel unit;forming a pad layer including a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to the driving thin film transistor in the pixel unit through the via hole which penetrates through the planarization layer; andforming a passivation layer covering the pad layer and including a plurality of through holes, each pad corresponding to one through hole, such that the first surface of the pad is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole.

As a fourth aspect of the present disclosure, there is provided a method of fabricating a display panel, and the method of fabricating the display panel includes:providing an array substrate, the array substrate including at least one pixel unit, each pixel unit including at least one thin film transistor, and the at least one thin film transistor including a driving thin film transistor;forming a planarization layer covering the array substrate and formed with a plurality of via holes, each of the plurality of via holes corresponding to the driving thin film transistor in one pixel unit;forming a pad layer including a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to the driving thin film transistor in the pixel unit through the via hole which penetrates through the planarization layer; andforming a passivation layer to obtain a display backplane, the passivation layer covering the pad layer and including a plurality of through holes, each pad corresponding to one through hole, such that the first surface of the pad is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole; andtransferring an LED layer onto the display backplane such that each LED pin of the LED layer falls into a corresponding through hole and contacts with a corresponding pad; andsoldering each LED of the LED layer with a corresponding pad through a corresponding LED pin.

DETAILED DESCRIPTION

The specific embodiments of the present disclosure are described in detail below in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not used to limit the present disclosure.

As a first aspect of the present disclosure, there is provided a display backplane, as shown inFIG.1, including a thin film transistor (TFT) substrate100, a planarization layer200, a pad layer, and a passivation layer400. It should be noted that the display backplane is a part of a display panel, and specifically, the display backplane may be combined with LEDs and packaged to finally form the display panel.

As shown inFIG.2, the array substrate100includes at least one pixel unit, and each pixel unit includes at least one thin film transistor. The at least one thin film transistor includes a driving thin film transistor.

The planarization layer200covers the array substrate100, and the pad layer is disposed on the planarization layer200. In addition, the pad layer includes a plurality of pads310, and each pad310of the pad layer is formed on the planarization layer200. It should be noted that, the sentence “the planarization layer200covers the array substrate100” here means that the planarization layer200and the array substrate100are stacked in a thickness direction of the display backplane, the array substrate100has a surface facing the planarization layer200, and the planarization layer200is fully distributed on the surface of the array substrate100facing the planarization layer200.

The function of the pad310is to provide a soldering point for the LED. Specifically, an anode of the LED is soldered to the pad310. A surface of the pad310facing away from the planarization layer is a first surface, each pixel unit corresponds to one pad310, and the pad310is electrically coupled to a driving thin film transistor in a corresponding pixel unit through a via hole penetrating through the planarization layer200. It is to be noted that the so-called “first surface” is the surface for soldering, the pins of the LED are soldered to the first surface, and electrical connection of the LED to the pad can be achieved. In the embodiment shown inFIG.1, the “first surface” of the pad310is the upper surface of the pad310.

The passivation layer400covers the pad layer, and the passivation layer400includes a plurality of through holes410, and each of the pads310corresponds to one through hole410, such that the first surface of the pad310is exposed through the corresponding through hole410. As shown inFIG.3, an area of the top opening of the through hole410is smaller than an area of the bottom opening of the through hole410. The sentence “each of the pads310corresponds to one through hole410” as described here means that the pads310and the through holes410are in pairs, and the number of the pads310is the same as the number of the through holes410in the display backplane. In the case that the pad310is present, the through hole410is present. If the display backplane includes N pads310, N through holes410are also provided in the display backplane, where N is a natural number.

The advantageous effects of the display backplane are described in detail below with reference toFIGS.4and5. When the LED is soldered to the pad310, LED pins510are required. Specifically, the LED pin510is soldered to the pad310. The opening of the through hole410is small at the top and large at the bottom, so that the LED pin510can be confined in the through hole410and cannot be easily removed from the through hole410. In the process of transferring the display backplane provided with the LED layer onto the welding equipment, the positions of the LED pins510are not changed in the case of not increasing additional constraint, so that the yield in fabricating the display panel can be improved.

In the present disclosure, the welding process for soldering the LED pins510to the pads310is not particularly limited. For example, the LED pins510may be soldered to the pads310by eutectic soldering.

Eutectic soldering is also known as low melting point alloy soldering. The basic property of eutectic alloys is: two different metals may be alloyed in a certain weight ratio at a temperature well below their respective melting points.

The display backplane according to the present disclosure is particularly suitable for micro-light emitting diode (micro-LED) display panels or mini-LED display panels.

In the micro-LED display panel, the LEDs are closely arranged. Thus, when the LED display panel is fabricated, the display backplane and the LED array need to be fabricated separately, then the closely arranged LED array is transferred onto the display backplane by using a laser-driven bulk transfer process. The LED array includes an LED layer and an LED pin layer. The LED layer includes a plurality of LEDs, and the LED pin layer includes a plurality of LED pins. Each LED corresponds to an LED pin, and the LED pin is electrically coupled to the anode of the LED. InFIGS.4and5, the reference numeral “510” indicates the LED pins.

After the LED array is transferred onto the display backplane, the LED pins510contact the first surfaces of the corresponding pads310and are confined in the through holes410, and cannot be easily released from the through holes410, thereby facilitating each LED in the LED array to be located at the correct position. When the subsequent soldering is carried out, the positions of the LEDs will not be changed, so that the yield in the fabricating the display panel can be improved.

As described above, the area of the top opening of the through hole410is smaller than the area of the bottom opening of the through hole410. For convenience of fabricating, “the area of the top opening of the through hole410can be smaller than the area of the bottom opening of the through hole410” by fabricating the through hole410having an inclined sidewall.

As an alternative embodiment, an angle α between the sidewall of the through hole410and the first surface of the pad310is between 10° and 80°.

It should be noted that the sidewall of the through hole410here may be a cylindrical surface, a flat surface, or a spherical surface.

If the through hole410is a frustum hole with a small top and a large bottom (i.e., the longitudinal cross section of the through hole410is trapezoidal and the transverse cross section thereof is circular), the sidewall of the through hole410is a cylindrical surface. In a cross-sectional view, the sidewall of the through hole410appear as a straight line (as shown inFIG.3a).

Of course, the sidewall of the through hole410is not strictly a cylindrical surface, but may be a spherical surface, as long as the area of the top opening of the through hole410is ensured to be smaller than that of the bottom opening thereof.FIG.3bshows the case where the sidewall of the through hole410is a spherical surface. In this case, “the angle α between the sidewall of the through hole410and the first surface of the pad310” refers to the angle between the tangent T of the sidewall of the through hole410and the first surface of the pad310.

In the present disclosure, a specific material of the passivation layer400is not particularly limited, and optionally, the material of the passivation layer400is silicon nitride, and the thickness of the passivation layer400is between 3000 angstroms and 4000 angstroms.

Of course, the present disclosure is not limited thereto, and the passivation layer400may be made of silicon oxide, or a mixture of silicon nitride and silicon oxide.

In the present disclosure, the specific structure of the array substrate100is not particularly limited. In the embodiment shown inFIG.2, the thin film transistor in the array substrate100is a top gate type thin film transistor. Accordingly, the thin film transistor100includes an active pattern layer including an active layer131, a first gate insulating layer140, a gate pattern layer including a gate electrode132, a second gate insulating layer150, an interlayer insulating layer160, and a source and drain pattern layer including a source electrode133and a drain electrode134.

The source electrode133is coupled to the corresponding active layer131through a source via penetrating the interlayer insulating layer160, the second gate insulating layer150, and the first gate insulating layer140, and the drain electrode134is coupled to the corresponding active layer131through a source via penetrating the interlayer insulating layer160, the second gate insulating layer150, and the first gate insulating layer140.

It should be noted that a pattern layer for forming a capacitor plate or the like is also formed between the second gate insulating layer150and the interlayer insulating layer160.

In the present disclosure, the first and second gate insulating layers140and150may each be made of silicon oxide, and the interlayer insulating layer160may include a silicon oxide layer and a silicon nitride layer, which are stacked.

As a second aspect of the present disclosure, a display panel is provided, and the display panel includes a display backplane, and an LED layer. The display backplane is the display backplane according to the first aspect of the present disclosure.

The LED layer includes at least one LED unit. Each LED unit includes a plurality of LED pins510, as shown inFIG.4, each LED pin510corresponds to one pad310, and a portion of the LED pin510is disposed in the corresponding through hole410and is soldered to the pad310.

Some of the plurality of LED pins510in one LED unit may serve as cathode pins and the other of the plurality of LED pins510may serve as anode pins, so that the LEDs in the LED unit may be lighted when the array substrate is powered on.

The sentence “each LED pin510corresponds to one pad310” means that the LED pins510and the pads310are paired; when there are N LED pins510in the display panel, there are N pads310; and the LED pin510can only be soldered to the pad310paired with the LED pin510.

As described above, after the LED array is transferred onto the display backplane, and the LED pins510contact the first surfaces of the corresponding pads310and are confined in the through holes410. When the display backplane provided with the LED layer is transferred onto a welding equipment, the LED pins510cannot be easily released from the through holes410, so that each LED in the LED array is located at the correct position. When the subsequent welding process is carried out, the positions of the LEDs will not be changed, so that the yield in fabricating the display panel can be improved.

To further avoid the LED pin510from being displaced during the welding process, optionally, as shown inFIG.5, the LED pin510includes a pin body511and a flange512disposed around the pin body511, and the flange512is disposed in the corresponding through hole.

If the LED pin510moves in a left-right direction inFIG.4, the flange512is inserted into the gap between the sidewall of the through hole410and the first surface of the pad, so that the flange512is limited by the upper edge of the through hole410. In this case, the LED pin510will not be released from the through hole410. Further, when the display backplane provided with the LED layer is transferred onto a welding equipment, the LED pins510cannot be easily released from the through holes410.

In the present disclosure, the specific location of the flange512on the pin body511is not particularly limited as long as the flange512is located in the corresponding through hole410. In the embodiment shown inFIGS.4and5, the flange512is disposed at an end of the pin body511facing the pad310, and a bottom surface of the flange512and a bottom surface of the pin body510are both soldered to the corresponding pad.

In the present disclosure, the size of the flange512is not particularly limited, and as an optional embodiment, a width W of the flange may be between 0.1 μm and 0.2 μm. It is noted that “the width of the flange” refers to a distance between a sidewall of the flange and a sidewall of the pin body510. As described above, the LED pins510are soldered to the pads310by eutectic soldering. In order to facilitate the eutectic soldering, as shown inFIG.6, the LED pin510may optionally include a pin core510aand a pin skin510bcladding the pin core510a, and the material of the pin skin510bis a material capable of achieving eutectic soldering.

As an optional embodiment, the material of the pin core510ais copper, and the material of the pin skin510bis selected from at least one of the following alloys: copper-nickel alloy, copper-tin alloy, and silver-tin alloy.

In the present disclosure, the specific thickness of the pin skin510bis not particularly limited, and optionally, the thickness of the pin skin510bdoes not exceed one tenth of the diameter of the pin core510a.

As an optional embodiment, the thickness of the pin skin510bmay be between 500 and 700 angstroms, and the diameter of the pin core510amay be between 5000 and 7000 angstroms.

FIG.10shows a scanned image of the LED pin510, and in the embodiment shown inFIG.10, the pin core510ais made of copper and the pin skin510bis made of a copper alloy.

In the present disclosure, a cylindrical pin core510amay be formed first, and then a pin skin510bmay be formed through a patterning process, and inFIG.10, the portion circled by an ellipse is the flange.

In the present disclosure, the specific type of the LEDs is not particularly limited, and optionally, the LEDs are micro-LEDs.

Optionally, the display panel may further include an encapsulation cover plate encapsulating the display substrate, and other structures.

As described above, in the micro-LED display panel, the LEDs are closely arranged, and thus, when the LED display panel is fabricated, the display backplane and the LED array need to be fabricated separately. Then the closely arranged LED array is transferred onto the display backplane by using a laser-driven bulk transfer process. The LED array includes an LED layer and an LED pin layer, the LED layer includes a plurality of LEDs, and the LED pin layer includes a plurality of LED pins. Each LED corresponds to an LED pin, and the LED pin is electrically coupled to the anode of the LED.

After the LED array is transferred onto the display backplane, the LED pins510contact the first surfaces of the corresponding pads310, are confined in the through holes410, and cannot be easily released from the through holes410, thereby facilitating each LED in the LED array to be located at the correct position. When the subsequent soldering is carried out, the positions of the LEDs will not be changed, so that the yield in fabricating the display panel is improved.

Since the micro-LEDs have a response time in the order of nanoseconds (1000 times that of a general OLED display panel), the display panel is particularly suitable for use in a virtual display device. In addition, the micro-LED also has the advantages of high contrast, wide color gamut and applicability to flexible display, which further expands the application range of the display panel.

Of course, the present disclosure is not limited thereto, and the LED may also be a mini-LED.

As a third aspect of the present disclosure, there is provided a fabrication method of a display backplane. As shown inFIG.7, the fabrication method includes the following steps.

In step S310, an array substrate is provided, the array substrate includes at least one pixel unit, and each pixel unit includes at least one thin film transistor.

In step S320, a planarization layer is formed, the planarization layer covers the array substrate, a plurality of via holes are formed on the planarization layer, and each via hole corresponds to a driving thin film transistor in one pixel unit.

In step S330, a pad layer is formed, the pad layer includes a plurality of pads, the pads are disposed on the planarization layer, a surface of the pad facing away from the planarization layer is a first surface, each pixel unit corresponds to one pad, and the pad is electrically connected to the driving thin film transistor in the pixel unit through a via hole penetrating through the planarization layer.

In step S340, a passivation layer is formed, the passivation layer covers the pad layer, and the passivation layer includes a plurality of through holes, and each of the pads corresponds to one through hole, such that the first surface of the pad is exposed through the corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole.

The fabrication method provided by the present disclosure can be used to fabricate the display backplane according to the first aspect of the present disclosure.

In the present disclosure, the specific steps of step S340are not particularly limited, and optionally, step S340may include: forming a passivation material layer, and performing a patterning process on the passivation material layer to form a passivation layer with a plurality of through holes.

In particular, in the step of performing the patterning process on the passivation material layer, a dry etching process may be employed. The through holes can be formed in the passivation material layer by controlling the amount of process gas, the voltages of the upper electrode and the lower electrode of the etching equipment and other process parameters.

FIG.9shows a scanning electron microscope image of the display backplane at the through hole, and the angle between the sidewall of the through hole and the first surface of the pad can be clearly seen from the portions circled by two ellipses in the image.

As a fourth aspect of the present disclosure, there is provided a method of fabricating a display panel, and as shown inFIG.8, the method of fabricating a display panel includes the following steps.

In step S410, an array substrate is provided, the array substrate includes at least one pixel unit, and each pixel unit includes at least one thin film transistor. In step S420, a planarization layer is formed, the planarization layer covers the array substrate and has a plurality of via holes formed therein, and each via hole corresponds to a driving thin film transistor in one pixel unit.

In step S430, a pad layer is formed, the pad layer includes a plurality of pads, the pads are disposed on the planarization layer, a surface of the pad facing away from the planarization layer is a first surface, each pixel unit is provided with one pad, and the pad is electrically connected to the driving thin film transistor in the pixel unit through the via hole penetrating through the planarization layer;

In step S440, a passivation layer is formed to obtain the display backplane, the passivation layer covers the pad layer and includes a plurality of through holes, each of the pads corresponds one through hole, so that the first surface of the pad is exposed through the corresponding through hole, and the area of top opening of the through hole is smaller than the area of the bottom opening of the through hole.

In step S450, the LED array is transferred onto the display backplane, such that each LED pin of the LED layer falls into a corresponding through hole and contacts with a corresponding pad;

In step S460, each LED of the LED layer is soldered to the corresponding pad through the corresponding LED pin.

As described above, the opening of the through hole is small at the top and large at the bottom, so that the LED pin510can be confined in the through hole410and cannot be easily released from the through hole410. In the process of transferring the display backplane provided with the LED layer onto the welding equipment, the positions of the LED pins510are not changed under the condition of not increasing additional constraint, so that the yield in fabricating the display panel can be improved.

In the present disclosure, when the LED is a micro-LED or a mini-LED, the step S450may be implemented by a laser-driven bulk transfer process.

It could be understood that the above embodiments are merely exemplary embodiments adopted for describing the principle of the present disclosure, but the present disclosure is not limited thereto. Various variations and improvements may be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these variations and improvements shall also be regarded as falling into the protection scope of the present disclosure.