DLL calibration method for fast frequency change without re-locking

A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.

RELATED APPLICATIONS

The present application is related to U.S. application Ser. No. 13/687,423, entitled “Delayed Locked Loop,” filed on Nov. 28, 2012, now U.S. Pat. No. 8,754,685, and the entirety of which is herein incorporated by reference.

BACKGROUND

DDR stands for double data rate. Physical DDR interfaces (PHYs) are implemented using accurate timing when various signals, such as clock, command, address, and data signals are each launched. Incoming signals are also delayed to be captured. In some existing approaches, delay lines are used to delay such signals. The delay lines are compensated against manufacturing process variation, supply voltage variation, and temperature (PVT) variation.

In high speed operations of the DDR PHYs, such as operations in the range of Giga-bits per second, delay locked loops are used to calibrate the delay lines. Different ways of calibration are used. For example, calibration is performed once when the circuit is initialized or is performed continuously during operations of the circuits when the signals drift during circuit operations. Further, when semiconductor chips that have DDR interfaces and related circuits are manufactured on a printed circuit board, board artifacts, such as trace length mismatches, are also compensated for.

In some applications, switching between high performance and low power modes involves changing operating frequencies. When operating frequencies of DDR interfaces change, delay locked loops relock to the new clock frequency and the operation of locking to the new clock frequency can take hundreds of clock cycles.

DETAILED DESCRIPTION

A digitally controlled oscillator (DCO) and a phase alignment mechanism are used in a delay locked loop (DLL). The DLL includes a fast frequency calibration method that enables the DLL to change delays based on the operating frequency without performing a frequency relocking operation. This calibration method allows the DLL to be locked to a first clock frequency and quickly switch to a second clock frequency, thereby allowing the device to enter and exit different performance modes to conserve power. Further, because the DLL does not require a frequency relocking operation, there are increased opportunities for a system to utilize low power modes without negatively impacting performance.

FIG. 1is a block diagram of a delay circuit100, in accordance with some embodiments. Circuit100is also called a DLL circuit because circuit100includes a DLL130. InFIG. 1, a signal path is depicted as a single line for clarity. In some embodiments, a signal path inFIG. 1is implemented by one or more corresponding signal lines.

Delay circuit100includes a digitally controlled delay line (DCDL)110that receives an input signal IN on an input terminal and outputs an output signal OUT from an output terminal. DCDL110is also coupled to an arithmetic unit (AU)115via signal path118. In some embodiments, delay circuit100includes more than one DCDL110, each of which is coupled to AU115. Delay circuit100also includes a controller120coupled to DLL130via signal paths122,124, and126. In some embodiments, controller120is an application processor for controlling operations of a system. In some embodiments, controller120is another circuit capable of controlling DLL130via signal paths122,124, and126.

DLL130includes a logic device140, a digitally controlled oscillator (DCO)150, a first divider160, a second divider170, and a frequency detector180. A first output terminal of logic device140is coupled to a first input terminal of DCO150via signal path142. A second output terminal of logic device140is coupled to a second input terminal of DCO150, a first input terminal of divider160, a first input terminal of divider170, and a first input terminal of frequency detector180via signal path144. Logic device140is coupled to AU115through signal paths132,134, and136.

An output terminal of DCO150is coupled to a second input terminal of divider160and to a third input terminal of DCO150via signal path152. An output terminal of divider160is coupled to a second input terminal of frequency detector180via signal path162. A second input terminal of divider170and a third input terminal of frequency detector180are coupled to a clock input terminal of DLL130via signal path172. An output terminal of divider170is coupled to a fourth input terminal of frequency detector180via signal path174. An output terminal of frequency detector180is coupled to an input terminal of logic device140via signal path182.

DCDL110is configured to receive an input signal IN and to output an output signal OUT by imposing a predetermined delay on input signal IN. To impose the predetermined delay, DCDL110is configurable based on a digital control code CDDCDL received via signal path118from AU115. In some embodiments, the electrical characteristics of DCDL110vary due to manufacturing process, supply voltage, and temperature. Effectively, by adjusting digital control code CDDCDL, circuit100is able to delay input signal IN by the predetermined delay regardless of manufacturing process, supply voltage, and temperature.

DLL130is configured to generate a reference signal FDCO on signal path152having a frequency to be synchronized (i.e., locked) with a frequency FDLLof a clock signal CLK that is received on the clock input terminal of DLL130and coupled to signal path172. The frequency locking operation is an iterative feedback process that adjusts reference signal FDCO until synchronized with the clock signal CLK. A general description of an iterative feedback process for adjusting reference signal FDCO is provided below. A more detailed description of an iterative feedback process applicable to adjusting reference signal FDCO is provided in U.S. Pat. No. 8,754,685.

To generate reference signal FDCO, DCO150is configured as a ring oscillator by having the output terminal coupled to the third input terminal via signal path152. Otherwise, DCO150is a replica of DCDL110. Because DCO150is a replica of DCDL110, control code CODE1 and control CODE2 generated based on locking reference signal FDCO to clock signal CLK are usable by AU115to generate control code CDDCDL for calibrated control of DCDL110.

Logic device140is a circuit configured to control operation of DLL130by responding to signals SUSPEND, RESUME, UP, and DOWN, and by generating signals CDDCO, START, STOP, CALC, CODE1, and CODE2, as discussed below. In some embodiments, logic device140is a finite state machine (FSM).

Logic device140is configured to control operation of DLL130by transmitting a start signal START or a stop signal STOP to DCO150, divider160, divider170, and frequency detector180via line144. In response to the stop signal STOP, DCO150, divider160, divider170, and frequency detector180are configured to be inactive. In response to the start signal START, DCO150, divider160, divider170, and frequency detector180are configured to be active to lock reference signal FDCO to clock signal CLK.

When DCO150, divider160, divider170, and frequency detector180are activated by logic device140, logic device140receives an up signal UP or a down signal DOWN from frequency detector180via signal path182. In response to the up signal UP or the down signal DOWN, logic device140adjusts a control code CDDCO that corresponds to a value of a reference signal FDCO at signal path152. Logic device140transmits the control code CDDCO to DCO150via signal path142.

When activated by logic device140, divider160is configured to receive the reference signal FDCO via signal path152. Divider160also receives a division integer M from controller120on signal path124. In response to receiving the reference signal FDCO and division integer M, divider160is configured to divide the reference signal FDCO by division integer M, thereby generating a divided reference signal FDCODIVM. Divider160outputs the divided reference signal FDCODIVM to frequency detector180via signal path162.

When activated by logic device140, divider170is configured to receive the clock signal CLK via signal path172. Divider170also receives a division integer N from controller120on signal path126. In response to receiving the clock signal CLK and division integer N, divider170is configured to divide the clock signal CLK by the division integer N, thereby generating a divided clock signal FCLKDIVN. Divider170outputs the divided reference signal FCLKDIVN to frequency detector180via signal path174.

When activated by logic device140, frequency detector180is configured to receive the divided reference signal FDCODIVM and divided clock signal FCLKDIVN. Frequency detector180compares signal FDCODIVM and signal FCLKDIVN to determine their frequency relationship to control the output phase of the DLL130. Based on the frequency relationship of signal FDCODIVM and signal FCLKDIVN, frequency detector180transmits the up signal UP, the down signal DOWN, or no signal to logic device140, thereby controlling the reference signal FDCO output by the DCO150. In particular, in response to the up signal UP or the down signal DOWN, logic device140adjusts the control code CDDCO on signal path142based on the up signal UP or the down signal DOWN to change the reference signal FDCO that is generated by DCO150.

In some embodiments, control code CODE1 corresponds to a first locked condition where DLL130is locked when the clock signal CLK is divided by a first predetermined value of division integer N, and control code CODE2 corresponds to a second locked condition where DLL130is locked when the clock signal CLK is divided by a second predetermined value of division integer N different from the first predetermined value. Various embodiments of the present disclosure are not limited by how control codes CODE1 and CODE2 are generated.

In particular, the time delay associated with CODE1 is based on TLOW=(NLOW/M)*TDLLand the time delay associated with CODE2 is based on THIGH=(NHIGH/M)*TDLL, where TLOWis the time delay for control code CODE1 based on the frequency FDLLof the clock signal CLK, THIGHis the time delay for control code CODE2 based on the frequency FDLLof the clock signal CLK, M is a predetermined integer based on the frequency FDLLof the clock signal CLK, NLOWis a division integer related to the control code CODE1, NHIGHis a division integer related to control code CODE2, and TDLLis a time period associated with a frequency FDLLof clock signal CLK.

The DLL130is configured to continuously generate control codes CODE1 and CODE2 through iterations of a delay locking operation in which a first iteration of a delay locking operation is followed by a second iteration of a delay locking operation, which is in turn followed by the first iteration. The first iteration corresponds to one of CODE1 and TLOWbased on division integer NLOWor CODE2 and THIGHbased on division integer NHIGH. The second iteration corresponds to the other of CODE1 and TLOWbased on division integer NLOWor CODE2 and THIGHbased on division integer NHIGH.

Control codes CODE1 and CODE2 therefore represent two calibration points that define a linear relationship independent of the frequency used to obtain CODE1 and CODE2. Thus, when the frequency FDLLof the clock signal CLK changes, calibration at the new frequency can be achieved by setting the division integer M to be linearly related to the frequency FDLLof the clock signal, thereby allowing DLL130to continue operation without relocking to the new frequency. Table 1 illustrates example division integers for values NLOW, NHIGH, and M, and corresponding time delays TLOWand THIGH.

When the clock signal CLK is set to change from a first frequency F1to a second frequency F2due to a different operation mode, DLL130is reconfigured based on the second frequency F2without the frequency locking operation. In particular, DLL130, initially configured based on division integers M1, NLOW1, and NHIGH1, is configured to suspend operations and receive reconfiguration integers M2, NLOW2, and NHIGH2related to the second frequency F2. After receiving the reconfiguration integers related to the second frequency F2, DLL130is reconfigured based on the second frequency. After reconfiguring the DLL130, the DLL130resumes operation while contemporaneously being synchronized to the second frequency F2without performing a relocking operation. The reconfiguration process of the DLL130based on the second frequency F2of the clock signal CLK will now be described using the devices of DLL130and controller120.

After logic device140has locked to the first frequency F1of the clock signal CLK, logic device140is configured to generate and transmit control code CODE1 and control code CODE2 to AU115. Logic device140is also configured to generate signal CALC, which is used by the AU115to trigger generation of control code CDDCDL based on control code CODE1 and control code CODE2 and parameters X and P. Logic device140transmits signal CALC to AU115via signal path132, transmits control code CODE1 to AU115via signal path134, and transmits control code CODE2 to AU115via signal path136.

Logic device140is configured to receive a suspend signal SUSPEND or a permit signal RESUME from controller120via line122. In response to receiving the suspend signal SUSPEND, logic device140is configured to finish any current iteration of a delay locking operation, and then suspend operation of DLL130. In some embodiments, after receiving the suspend signal SUSPEND and finishing a current iteration of a delay locking operation, logic device140transmits stop signal STOP to DCO150, divider160, divider170, and frequency detector180via signal path144. In response to receiving stop signal STOP, divider160is configured to receive reconfiguration integer M2from controller120via signal path124. In response to receiving stop signal STOP, divider170is configured to receive reconfiguration integers NLOW2and NHIGH2from controller120via signal path126.

Controller120is configured to control and reconfigure DLL130when clock signal CLK changes due to a change in performance mode. Specifically, controller120is configured to reconfigure DLL130when the clock signal CLK is to change from the first frequency F1to the second frequency F2, thereby entering a different performance mode. When the frequency of clock signal CLK changes, controller120is configured to deactivate logic device140by transmitting suspend signal SUSPEND via line122.

After suspending logic device140, controller120waits for the clock signal CLK to operate at the second frequency F2. When the clock signal CLK is operating at the second frequency F2, controller120is configured to provide a new division integer M2and new division integers NLOW2and NHIGH2. In some embodiments, controller120is configured to determine new division integer M2and new division integers NLOW2and NHIGH2. In some embodiments, controller120is configured to receive new division integer M2and new division integers NLOW2and NHIGH2from a system of which circuit100is a part. Specifically, controller120provides division integer M2to load into divider160based on the second frequency F2. The division integer M2is linearly related to the second frequency F2. In addition, controller120is configured to provide division integers NLOW2and NHIGH2to load into divider170based on the second frequency F2. Controller120is configured to provide division integer M2to divider160via signal path124and to provide division integers NLOW2and NHIGH2to divider170via signal path126.

After providing division integer M2to divider160and division integers NLOW2and NHIGH2to divider170, controller120transmits resume signal RESUME to logic device140via line122. In response to the resume signal RESUME, logic device140is reactivated, thereby causing logic device140to retransmit control codes CODE1 and CODE2 and signal CALC to AU115based on the frequency F2. In response to receiving the delay codes, AU115recalculates the digital control code CDDCDL based on updated values of X and P, and transmits the updated control code CDDCDL to DCDL110.

Once reactivated, logic device140transmits the start signal START to DCO150, divider160, divider170, and frequency detector180via line144. DCO150continues to generate the reference signal FDCO. Divider160receives and divides the reference signal FDCO by the division integer M2to generate the divided reference signal FDCODIVM. Divider170receives the updated clock signal CLK operating at the second frequency F2and divides the second frequency F2by division integers NLOW2and NHIGH2to generate the divided clock signal FCLKDIVN. Because the division integer M1and the division integer M2are linearly related to the second frequency F2, the divided reference signal FDCODIVM from divider160for second frequency F2is substantially similar to the divided reference signal FDCODIVM from divider160for first frequency F1.

Frequency detector180continues to receive divided reference signal FDCODIVM and divided clock signal FCLKDIVN and provide appropriate feedback to logic device140as described above.

Thus, the controller120is configured to keep DLL130locked to the clock signal CLK without performing a relocking operation to synchronize the DLL130to the second clock frequency F2. Because the DLL130does not need to perform the relocking operation, which could take hundreds of clock cycles, power is saved by bypassing such an operation. Further, in some embodiments, power is conserved because DLL130quickly enters into a power savings mode, further conserving power.

FIG. 2is a flowchart of a method200of controlling a DLL circuit to synchronize to a second frequency, in accordance with some embodiments. The method ofFIG. 2is usable by a controller, e.g., controller120(FIG. 1), in conjunction with a DLL, e.g., DLL130.

Initially, the method200starts at operation205, where a DLL, e.g., DLL130, connected to a controller, e.g., controller120, is operating based on a clock signal CLK that oscillates at frequency F1and with division integer M1being loaded into a first divider, e.g., divider160, and division integers NLOW1and NHIGH1being loaded into a second divider, e.g., divider170. At operation210, the method determines if the clock signal CLK will change from the first frequency F1to a second frequency F2. If the clock signal CLK will not change from the first frequency F1to the second frequency F2at operation210, the method returns to operation205to continue operating based on the first frequency F1.

If the clock signal CLK will change from the first frequency F1to the second frequency F2at operation210, the method proceeds to operation215, where the method transmits a suspend signal to the DLL. After transmitting the suspend signal, the method proceeds to operation220, where the method determines if the clock signal CLK has changed to frequency F2. If the clock signal CLK has not changed to the frequency F2, the method returns to operation220and waits until the clock signal is changed to the frequency F2.

After the clock signal is changed to the frequency F2, the method proceeds to operation225where the method provides a new division integer M2, new division integers NLOW2and NHIGH2, and transmits the division integers M2, NLOW2, and NHIGH2to the DLL, e.g., DLL130. The new division integers M2, NLOW2, and NHIGH2are based on the frequency F2and are related to delays that will be incurred when the DLL, e.g., DLL130, operates at the frequency F2. After transmitting the division integers M2, NLOW2, and NHIGH2in operation225, the method continues to operation230, where the method transmits a resume signal to a logic device, e.g., logic device140, of the DLL, thereby causing the DLL to resume operation with the division integers M2, NLOW2, and NHIGH2.

FIG. 3is a flowchart of a method300implemented by a DLL to synchronize to a second frequency, in accordance with some embodiments. The method ofFIG. 3is usable by a DLL, e.g., DLL130(FIG. 1), in conjunction with a controller, e.g., controller120.

Initially, the method starts at operation305, where a DLL is operating based on a clock signal CLK that oscillates at frequency F1and with division integer M1being loaded into a first divider, e.g., divider160, and division integers NLOW1and NHIGH1being loaded into a second divider, e.g., divider170. At operation305, the DLL continues to adjust a DCO, e.g., DCO150, to have a frequency and phase that is based on the clock frequency F1, thereby continually causing an AU, e.g., AU115, to update a DCDL, e.g., DCDL110, to have delays based on the DCO, e.g., DCO150. At operation310, the method determines if a suspend signal has been received from a controller, e.g., controller120. If a suspend signal has not been received at operation310, the method returns to operation305to continue operating at frequency F1.

If a suspend signal has been received at operation310, the method suspends the DLL at operation315. In some embodiments, suspending the DLL includes sending a stop signal, e.g., stop signal STOP, to a DCO, e.g., DCO150, a first divider, e.g., divider160, a second divider, e.g., divider170, and a frequency detector, e.g., frequency detector180via signal path144. After suspending the operation of the DLL, the DLL receives and loads division integer M2into the first divider and receives and loads division integers NLOW2and NHIGH2into the second divider at operation320. The method proceeds to operation325, where the method determines if a resume signal has been received. If the resume signal has not been received, the method returns to operation325to continue waiting until the resume signal is received.

When the resume signal is received at operation325, the method proceeds to operation330where the DLL restarts operation of the DLL and transmits a CALC signal to the AU. In some embodiments, restarting operation of the DLL includes transmitting a start signal, e.g., start signal START, to a DCO, e.g., DCO150, a first divider, e.g., divider160, a second divider, e.g., divider170, and a frequency detector, e.g., frequency detector180via signal path144. After the DLL resumes operation, the method proceeds to operation335where the DLL operates at frequency F2based on the division integer M2in the first divider and division integers NLOW2and NHIGH2in the second divider. At operation335, DLL continues to adjust the DCO to have a frequency that is based on the clock frequency F2, thereby continually causing the AU to update a DCDL based on the DCO.

FIG. 4is a graph of waveforms of various signals in the DLL circuit ofFIG. 1, in accordance with some embodiments.

At time T0, the clock signal CLK is operating at frequency F1and divided reference signal FDCODIV and divided clock signal FCLKDIV operate at a fraction of frequency F1, each having substantially equal frequency and phase with respect to the clock signal CLK. In particular, divided reference signal FDCODIV and divided clock signal FCLKDIV each have a time period λ1, corresponding the time period of frequency F1divided by a first division integer.

At time T1, the controller determines that the clock signal CLK is to change from frequency F1to frequency F2. Accordingly, the controller suspends the operation of DLL at time T1until the clock signal CLK has stabilized to operate at frequency F2. At time T2, the controller determines that the clock signal CLK has stabilized to operate at frequency F2. In response to the clock signal stabilizing at time T2, the controller updates the DLL based on the division integers associated with the second frequency F2. After updating the DLL with the division integers associated with the second frequency F2, the controller transmits a resume signal RESUME to the DLL to resume operations based on the division integers associated with the second frequency F2.

At time T2, the clock signal CLK is operating at frequency F2and divided reference signal FDCODIV and divided clock signal FCLKDIV operate at a fraction of frequency F2, with both reference clock FDCODIV and divided clock signal FCLKDIV having substantially equal frequency and phase with respect to the clock signal CLK. In particular, divided reference signal FDCODIV and divided clock signal FCLKDIV each have a time period λ2, corresponding the time period of frequency F2divided by a second division integer. The time delay TDELAYfor the DLL to change operating frequencies is substantially equal to the amount of time delay incurred to change the clock frequency from the first frequency F1to the second frequency F2.

In some embodiments, a value of control code CDDCO is loaded to DCO150. In response, DCO150oscillates at a frequency corresponding to the value of control code CDDCO loaded to DCO150. When a value of control code CDDCO is to be adjusted, logic device140provides the adjusted value of control code CDDCO based on signals UP and DOWN generated by DET170. For example, when logic device140receives signal UP, logic device140increases a value of control code CDDCO. In contrast, when logic device140receives signal DOWN, logic device140decreases a value of control code CDDCO. When logic device140does not receive signal UP or signal DOWN, and a time-out circuit (not shown) of the logic device140indicates a time out, frequency FDCODIVM and frequency FCLKDIVN are equal or are at least substantially close to one another. In such a condition, logic device140considers frequency FCLKDIVN and frequency FDCODIVM to be equal.

One aspect of this description relates to a delay circuit. The delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency.

Another aspect of this description relates to a method of operating a delay locked loop (DLL) in a delay circuit. The method includes suspending the DLL when a clock signal operates at a first frequency. The method further includes reconfiguring the DLL based on a first value and a second value corresponding to the clock signal operating at a second frequency different from the first frequency. The method further includes activating the DLL based on the first value and the second value after the clock signal operates at the second frequency.

Still another aspect of this description relates to a delay locked loop (DLL) configured to operate based on a clock signal having a first frequency or a second frequency. The DLL includes a logic device configured to generate a frequency control value, to generate delay codes based on the first frequency or the second frequency, to generate a first value, a second value, a third value, and a fourth value, and to suspend operations for a time duration responsive to a signal indicating changing the clock signal from the first frequency to the second frequency. The DLL further includes a digitally controlled oscillator (DCO) configured to generate a reference signal based on the frequency control value. The DLL further includes a first divider configured to divide the reference signal based on a first value when the clock signal having the first frequency and based on the third value when the clock signal having the second frequency. The DLL further includes a second divider configured to divide the clock signal based on a second value when the clock signal having the first frequency and based on the fourth value when the clock signal having the second frequency. The DLL further includes a frequency detector configured to compare the divided reference signal and the divided clock signal.