Test apparatus and test method

Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.

BACKGROUND

1. Technical Field

The present invention relates to a test apparatus and a test method.

2. Related Art

A test apparatus of a semiconductor memory such as DRAM and SRAM writes data to a memory under test, and reads the written data from the memory under test. The test apparatus then compares the read data with an expected value, for detecting a failed cell of the memory under test.

Recent years have seen growing attention to the problem of power consumption increase of these memories as they have a higher speed and a larger capacity. Semiconductor memories operable to switch whether to receive bit inverted addresses and receive non-bit inverted addresses appear on the market in response to this trend. A controller accessing this type of semiconductor memory can provide it with addresses with less change in bits. Accordingly, this type of semiconductor memory can have reduced power consumption inherent in address processing can be reduced with.

The test apparatus writes data to or read data from a predetermined address of a memory under test, by executing a test program created in advance. Therefore, when testing such a semiconductor memory, it has been necessary to create the test program taking into consideration whether the address should undergo bit inversion or not in advance. This makes creation of the test program for testing semiconductor memories difficult and troublesome.

SUMMARY

To solve the above problems, according to an aspect related to the innovations herein, provided are a test apparatus and a test method that can solve the above-mentioned problems. This is achieved by the combination of the features recited in the claims. According to a first aspect related to the innovations herein, provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1shows the structure of a test apparatus10according to the present embodiment, together with a memory under test200.

The memory under test200is accessed from an external controller through a DDR (Double Data Rate) interface. The DDR interface transfers, in parallel, a plurality of data signals DQ and a clock signal DQS that shows a timing at which the data signals DQ are sampled. A plurality of data signals and a clock signal at a rate which is double the rate of the data signal are transported in parallel between the memory under test200and the external controller. The memory under test200uses such a DDR interface, and one example of which is a GDDR5 (Graphics Double Data Rate 5) memory.

The memory under test200receives data to be written, from the external controller via the DDR interface for data transfer. The memory under test200also outputs data called for reading, to the external controller via the data-transfer DDR interface.

The memory under test200receives an address from the external controller via the address-transfer DDR interface. The memory under test200writes data to and reads data from a recording region designated by the received address.

The memory under test200receives a command from the external controller. The memory under test200performs such processing as writing of data, reading of data, and no-operation (NOP), according to the contents indicated by the received command.

In addition, the memory under test200receives an inversion cycle signal from the external controller. The inversion cycle signal is transferred to the memory under test200from the external controller, together with the address transferred from the external controller to the memory under test200. The inversion cycle signal indicates whether the address transferred synchronously has undergone bit inversion or not.

For example, if it is H logic, the inversion cycle signal shows that the address transferred synchronously has undergone bit inversion. If it is L logic, on the other hand, the inversion cycle signal shows that the address transferred synchronously has not undergone bit conversion.

When the inversion cycle signal indicates bit inversion, the memory under test200converts the value of the address received from the external controller to a bit inverted value, and writes data to or reads data from a recording region of the converted address. On the contrary, when the inversion cycle signal indicates that it has not undergone bit inversion, the memory under test200writes data to or reads data from a recording region indicated by the value of the address received from the external controller.

The external controller that writes data to and reads data from the memory under test200performs bit inversion to the values of the addresses sequentially transferred to the memory under test200, so that the amount of change in logic values of the bits becomes smaller. Then, the memory under test200supplies, to the memory under test200, the inversion cycle signal together with the address to which inversion control has been performed. According to this operation, the memory under test200can restrain power consumption incurred by change in the logic value of each bit of an address.

The test apparatus10includes a pattern generator20, a supply section22, an acquiring section24, and a comparing section26. The test apparatus10according to the present embodiment tests the memory under test200.

The pattern generator20runs a test program, and sequentially generates a command, an address, an inversion cycle signal, and data to be written, which are to be supplied to the memory under test200. Furthermore, the pattern generator20runs a test program, to sequentially generate expected values of data to be read, which are to be outputted from the memory under test200.

The supply section22supplies, to the memory under test200, the command, the address, the inversion cycle signal, and the data to be written, having been generated by the pattern generator20. The acquiring section24acquires the data to be read, after outputted from the memory under test200.

The comparing section26compares the data to be read, having been acquired by the acquiring section24, with the expected value generated by the pattern generator20. Subsequently, the comparing section26outputs the comparison result between the data to be read and the expected value.

The test apparatus10as described above writes data to the memory under test200prior to shipping of the memory under test200, and later reads the written data from the memory under test200. Then, by comparing the read data with the expected value, the test apparatus10detects any failed cell that exists in the memory under test200. By doing so, the test apparatus10can conduct a test to the memory under test200.

FIG. 2shows the structure of a pattern generator20according to the present embodiment. The pattern generator20includes a pattern memory32, a sequencer34, a command generator36, an address generator38, a data generator40, and an inversion control section42.

The pattern generator20records a test instruction sequence (test program) including a plurality of test instructions sequentially executed by the sequencer34. In addition, the pattern generator20records test patterns in correspondence with test instructions. A test pattern can be defined as a pattern of data that includes a command, an address, and data to be written, which are to be supplied to the memory under test200, as well as data to be read, which is to be outputted from the memory under test200.

The sequencer34sequentially executes test instructions included in a test instruction sequence so that one instruction is executed in each test cycle. The sequencer34designates the position at which the test instruction is to be executed in the next test cycle, according to the contents of the executed test instruction and the execution result.

In an example, when having executed no operation (NOP), the sequencer34designates the next position of the test instruction in the test sequence, as the position of the test instruction to be executed in the next test cycle. In an example, when having executed a branch instruction, the sequencer34switches the position of the test instruction to be executed in the next test cycle according to the branch condition. In this way, the sequencer34sequentially executes each test instruction included in a test instruction sequence.

The command generator36acquires the test patterns corresponded with the test instructions executed by the sequencer34in each test cycle, and generates a command included in the acquired test pattern. Then, the command generator36outputs the generated command to the supply section22.

The address generator38acquires the test patterns corresponded with the test instructions executed by the sequencer34in each cycle, and generates an address included in the acquired test pattern. Then, the address generator38outputs the generated address to the inversion control section42.

The data generator40acquires the test patterns corresponded with the test instructions executed by the sequencer34in each cycle, and generates data to be written and an expected value included in the acquired test pattern. Then, the data generator40outputs the generated data to be written, to the supply section22. The data generating section40also outputs the generated expected value to the comparing section26.

The inversion control section42acquires the address generated by the address generating section38, and judges whether to perform bit inversion on the address. When it has been judged to perform bit inversion, the inversion control section42performs bit inversion on the address generated by the address generator38, and outputs the bit inverted address to the supply section22. When it has been judged not to perform bit inversion, the inversion control section42outputs, to the supply section22, the address generated by the address generator38without performing bit inversion.

The inversion control section42also outputs an inversion cycle signal whose logic value switches depending on whether the address generated by the address generator38has been judged to undergo bit inversion. As explained above, the inversion control section42can output the inversion controlled address and the inversion cycle signal indicating whether the outputted address has undergone bit inversion, to the supply section22.

FIG. 3shows a first example of the configuration of an inversion control section42according to the present embodiment. The inversion control section42includes a number-of-bits setting section50, a selector52, and an inversion processing section54.

Prior to a test, the number-of-bits setting section50sets, to the selector52, the bit smaller than or equal to the bit width of the address supplied to the memory under test200. An example of the number-of-bits setting section50is a register to which a value is written from an external control apparatus prior to a test. A value is written to the number-of-bits setting section50by the external control apparatus.

The number of bits set by the number-of-bits setting section50may be equivalent to or more than ½ the bit width of the address supplied to the memory under test200. In an example, the number-of-bits setting section50sets 4 bits if the bit width of the address supplied to the memory under test200corresponds to 8 bits, and 5 bits if the bid width of the address supplied to the memory under test200is 9 bits.

The selector52receives the address generated by the address generator38, as well as the comparison address set in advance to a register or the like. For example, the comparison address is a fixed value written to the register or the like in advance. In the present embodiment, the value of the comparison address is equivalent to the value outputted from the address generator38during a period in which no effective address is supplied to the memory under test200. In an exemplary comparison address, all the bits are rendered as L logic (or zero).

Based on the address generated by the address generator38and the comparison address, the selector52selects whether to perform bit inversion on the address generated by the address generator38, before supplying the address to the memory under test200. To be specific, the selector52selects to perform bit inversion on the address, when the address generated by the address generator38is changed from the comparison address at least by the number of bits pre-set by the number-of-bits setting section50. The selector52selects not to perform bit inversion on the address, when the address generated by the address generator38is not changed from the comparison address by the number of bits pre-set by the number-of-bits setting section50.

In an example, the selector52selects to perform bit inversion on the address, when the change of the address generated by the address generator38from the comparison address is equal to or larger than the number of bits corresponding to ½ the bit width of the address. For example, the selector52decides to perform bit inversion on the address, when the address generated by the address generator38is changed from the comparison address by 4 bits or more when the bit width of the address is 8 bits or by 5 bits or more when the bit width of the address is 9 bits.

For example, the selector52includes a non-matching circuit62and a judging section64. The non-matching circuit62compares the address generated by the address generator38and the comparison address for each bit, as to whether they do not match for each bit. The judging section64selects to perform bit inversion on the address when the number of bits judged not to match by the non-matching circuit62is the pre-set number of bits or more (e.g., ½ the bid width of the address or more). The judging section64selects not to perform bit inversion when the number of bits judged not to match by the non-matching circuit62is less than the pre-set number of bits.

The judging section64then outputs the inversion cycle signal of the logical value according to the selection result. For example, when having selected to perform bit inversion on the address, the judging section64outputs an inversion cycle signal of H logic, and outputs an inversion cycle signal of L logic when having selected not to perform bit inversion on the address.

The selector52supplies such an inversion cycle signal to the inversion processing section54. The selector52also outputs the inversion cycle signal to the supply section22.

The inversion processing section54receives an address generated by the address generator38. When the selector52has selected to perform bit inversion on the address, the inversion processing section54performs bit inversion on the address generated by the address generator38, and outputs the address having undergone the bit inversion. On the contrary, when the selector52has selected not to perform bit inversion on the address, the inversion processing section54outputs the address generated by the address generator38without performing thereto bit inversion.

To be more specific, the inversion processing section54switches between performing bit inversion and not performing bit inversion before outputting the address generated by the address generator38, depending on the logic value of the inversion cycle signal. The inversion processing section54outputs the address whose inversion has been controlled in the above manner, to the supply section22.

The inversion control section42explained above can select the one having a smaller amount of change from the comparison address, from between the address pattern whose address has been bit converted and the address pattern whose address has not been bit converted, and outputs the selected address. Accordingly, the inversion control section42can pursue bit inversion in an adequate manner, even without changing the test program executed by the address generator38.

FIG. 4shows a second example of the configuration of the inversion control section42according to the present embodiment. The inversion control section42according to the second example is roughly the same in function and configuration as the inversion control section42in the first example shown inFIG. 3. Therefore, there will be no explanation provided below for the common function and configuration to those of the inversion control section42shown inFIG. 3.

Each bit in an address of the memory under test200is different in content depending on the contents of each command. With this in view, the test apparatus10selects and rearranges the address patterns included in the pattern data, depending on the contents of the command supplied to the memory under test200, before supplying it to the memory under test200.

The inversion control section42in the second example selects and rearranges each bit in the address pattern outputted from the address generator38, together with the invertion processing on the address. The inversion control section42in the second example further includes a first register72, a first rearranging section74, a second register76, and a second rearranging section78.

The first register72acquires a selecting signal outputted from the address generator38in each test cycle, and retains it. The selecting signal includes information to designate which of the plurality of bits included in the address generated by the address generator38to be selected and how it is to be rearranged.

The first rearranging section74selects the bits designated by the selecting signal, from among the plurality of bits included in the address generated by the address generator38, and rearranges the selected bits in the order designated by the selecting signal. An exemplary first rearranging section74converts a 24-bit address generated by the address generator38into either an 8-bit address or a 9-bit address. Then, the first rearranging section74outputs the selected and rearranged address to the selector52.

The second register76acquires the selecting signal outputted from the address generator38in each test cycle and retains it. The second rearranging section78selects the bits designated by the selecting signal, from among the plurality of bits included in the address generated by the address generator38, and rearranges the selected bits in the places designated by the selecting signal. In this example, the second rearranging section78pursues the rearrangement to adjust to each address pin of the memory under test200. Then, the second rearranging section78outputs the selected and rearranged address to the inversion processing section54.

The inversion control section42according to the second example can perform the inversion processing appropriately even when the contents indicated by bits of the address are different from each other according to the contents of each command.

FIG. 5shows an example of an operating clock, a clock signal, a command, an address, and a selection signal of the memory under test200. As shown in (A) and (B) inFIG. 5, the memory under test200operates in synchronization with the operating clock having a rate twice the rate of the clock signal. Therefore, the test apparatus10outputs an address at a rate twice the rate of the clock signal.

Also as shown in (C) ofFIG. 5, the memory under test200executes the processing according to the command received in synchronization with the operating clock. The memory under test200may receive a bank active command (ACT), a read command (RD), a write command (WR), a no-operation command (NOP) and so on, and perform the corresponding operation. Accordingly, the command generator36of the pattern generator20sequentially outputs these various types of commands according to each test program.

Also as shown in (D) ofFIG. 5, when receiving a command for accessing a particular recording region, the memory under test200receives, in addition to the command, two addresses included in consecutive two cycles. Then, the memory under test200accesses the recording region designated by the two addresses included in the consecutive two cycles. This means that when outputting a command to access a particular recording region, the address generator38of the pattern generator20outputs the consecutive two addresses to designate the recording region of the memory under test200to be accessed.

Also as (D) inFIG. 5shows, the memory under test200receives addresses having bits different in contents for different commands. The memory under test200interprets an address taking into consideration the contents of the received command, and accesses the designated recording region. Accordingly, the inversion control section42of the pattern generator20selects and rearranges the value of each bit of the address outputted from the address generator38, according to the contents of the command outputted to the memory under test200and at each output timing of the address.

The memory under test200does not receive any address unless it has received the command to access a particular recording region. Therefore, the address generator38of the pattern generator20supplies a predetermined fixed address to the memory under test200, during a period in which no address is received by the memory under test200. For example, the address generator38of the pattern generator20outputs the address in which all the bits are set to L logic (or zero) during a period in which no address is received by the memory under test200.

The inversion control section42of the pattern generator20executes bit inversion control of an address, by setting, as the comparison address, the fixed address generated during a period in which no address is received by the memory under test200. By doing so, the test apparatus10can minimize the amount of change in the unit of bit between the leading address and the address immediately therebefore, when it outputs two consecutive addresses together with a command. Also when the test apparatus10outputs two consecutive addresses together with a command, it can minimize the amount of change in the unit of bit between the trailing address and the address immediately thereafter.

FIG. 6shows an example of the timing chart of each signal of the test apparatus10and of the memory under test200according to the present embodiment. (A) inFIG. 6shows the address generated by the address generator38(i.e., selected and rearranged address). (B) inFIG. 6shows a comparison address. (C) inFIG. 6shows an output from the non-matching circuit62. (D) inFIG. 6shows the address generated by the address generator38(i.e., selected and arranged address), similar to (A) ofFIG. 6. (E) inFIG. 6shows an inversion cycle signal. (F) inFIG. 6shows an inversion controlled address.

(G) inFIG. 6shows a clock signal received by the memory under test200. (H) inFIG. 6shows an operating clock of the memory under test200. (I) inFIG. 6shows a command received by the memory under test200. (J) inFIG. 6shows an inversion cycle signal received by the memory under test200. (K) inFIG. 6shows an address received by the memory under test200. (L) inFIG. 6shows an address inside the memory under test200.

In an example, the test apparatus10outputs an address of 9 bits, to the memory under test200. In this case, if the address generated by the address generator38has changed by 5 bits or more from the comparison address, the inversion control section42sets the inversion cycle signal to H logic, and inverts the address supplied to the memory under test200. If the address generated by the address generator38has experienced change from the comparison address which is less than by 5 bits or more, the inversion control section42sets the inversion cycle signal to L logic, and does not perform inversion on the address supplied to the memory under test200.

The memory under test200receives the address and the inversion cycle signal from the test apparatus10. When the inversion cycle signal is L logic, the controller inside the memory under test200acquires the inputted address in the non-inverted state, and accesses the recording region. When the inversion cycle signal is H logic, the controller inside the memory under test200acquires the inputted address after inverting it, and accesses the recording region.

The explained test apparatus10can reduce the amount of change of the address outputted to the memory under test200. By doing so, the test apparatus10can restrain the power consumption incident to address transfer.

FIG. 7shows a third example of the configuration of the inversion control section42according to the present embodiment. The inversion control section42according to the third example is roughly the same in function and configuration as the inversion control section42in the first example shown inFIG. 3and as the inversion control section42in the second example shown inFIG. 4. Therefore, there will be no explanation provided below for the common function and configuration to those of the inversion control section42shown inFIG. 3and the inversion control section42shown inFIG. 4.

The inversion control section42according to the third example further includes an address retaining section90. The address retaining section90receives the address supplied to the memory under test200in the cycle immediately before it, as a comparison address, and retains one cycle of the address. When the address generated by the address generator38has been changed from the comparison address retained in the address retaining section90by the predetermined number of bits or more, the selector52selects to perform bit inversion on the address. By doing so, the inversion control section42can reduce the amount of change for each bit of an address, even when it attempts to consecutively output addresses over a plurality of cycle periods.

In addition, the inversion processing section54can switch between outputting of inversion controlled addresses or addresses not subjected to inversion control, in each mode set from outside. In such a case, in response to setting of the mode from outside which calls for outputting the address not subjected to inversion control, the inversion processing section54can stop the function of performing bit inversion to the address, and outputs the address not subjected to inversion. This embodiment enables the inversion processing section54to test the memory under test200in the setting not to perform inversion control to an address.