Fabrication method of leadframe-based semiconductor package

A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

FIELD OF THE INVENTION

The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a leadframe-based flip-chip type semiconductor package and a method of fabricating the semiconductor package.

BACKGROUND OF THE INVENTION

Conventionally, a semiconductor package using a leadframe as a chip carrier, which is referred to as a leadframe-based semiconductor package, is formed by attaching a non-active surface of a semiconductor chip to a die pad of the leadframe, electrically connecting the semiconductor chip to a plurality of leads of the leadframe via a plurality of bonding wires, and forming an encapsulant to encapsulate the semiconductor chip, the bonding wires and a part of the leadframe. However, this type of semiconductor package usually encounters problems that, for example, electronic signals become weakened due to the length of the bonding wires, and during a molding process of forming the encapsulant, wire loops of the bonding wires tend to be swept or sagged due to impact of mold flow of an encapsulating resin, thereby leading to undesirable contact and short circuit between adjacent bonding wires. Moreover, the leadframe-based semiconductor package cannot be further reduced in thickness as the height of the wire loops of the bonding wires must be considered.

Accordingly, there has been proposed another leadframe-based semiconductor package using a flip-chip technology. In this semiconductor package, a semiconductor chip is mounted on a leadframe in an upside-down manner that a plurality of conductive bumps implanted to an active surface of the semiconductor chip are bonded and electrically connected to corresponding leads of the leadframe. Consequently, without the use of bonding wires, a path for transmitting electronic signals in the semiconductor package is shortened through the conductive bumps and the quality of electronic signals during transmission is not adversely affected, and further, the semiconductor package can be effectively reduced in height as not having to consider the loop height of the bonding wires.

However, in the above leadframe-based flip-chip type semiconductor package, the leads of the leadframe are disposed at a peripheral portion of the leadframe, and there is no electrical connection provided at a central portion of the leadframe, such that an issue of not having a sufficient number of electrical connections may arise.

In order to solve the aforementioned problem, U.S. Pat. No. 6,815,833 proposes a semiconductor package1having electrical connections formed at a central portion of a leadframe. As shown inFIGS. 1A and 1B, the semiconductor package1comprises: a leadframe17having a plurality of leads14and a die pad15; a semiconductor chip11having an active surface112, the semiconductor chip11being mounted and electrically connected to the die pad15and the leads14of the leadframe17by a plurality of conductive bumps12formed on the active surface112of the semiconductor chip11; and an encapsulant16for encapsulating a part of the leadframe17, the conductive bumps12and the semiconductor chip11, wherein bottom surfaces of the leads14and the die pad15are exposed from the encapsulant16. By this arrangement, the leads14of the leadframe17serve as input/output (I/O) connections, and the die pad15of the leadframe17serves as, for example, an additional power or grounding connection.

U.S. Pat. No. 6,597,059 also proposes a semiconductor package2with an increased number of electrical connections. As shown inFIGS. 2A and 2B, the semiconductor package2comprises: a leadframe27having a plurality of leads24and two die pads25; a semiconductor chip21having an active surface212, the semiconductor chip21being electrically connected to the corresponding leads24and the two die pads25by a plurality of conductive bumps22formed on the active surface212of the semiconductor chip21; and an encapsulant26for encapsulating a part of the leadframe27, the conductive bumps22and the semiconductor chip21, wherein bottom surfaces of the leads24and the die pads25are exposed from the encapsulant26. By such arrangement, the leads24of the leadframe27serve as I/O connections, and the two die pads25of the leadframe27serve as, for example, two additional power and/or grounding connections.

Although in the above-mentioned packages, it seems beneficial of having the die pad(s) provide one or two additional electrical connections besides the leads of the lead frame, the die pad(s) may only serve as power or grounding connection(s) but not I/O connection(s) because a plurality of conductive bumps are electrically connected thereto, such that this arrangement still does not fulfill the need of sufficient I/O connections for a highly integrated semiconductor chip with high electrical performance and multi-functionality. Therefore, the problem to be solved here is to provide a semiconductor package with an increased number of I/O connections so as to enhance the electrical performance of the semiconductor package.

SUMMARY OF THE INVENTION

In view of the foregoing drawbacks of the prior art, a primary objective of the present invention is to provide a leadframe-based semiconductor package and a fabrication method thereof, which can increase the number of I/O connections of the semiconductor package.

Another objective of the present invention is to provide a leadframe-based semiconductor package and a fabrication method thereof, which can enhance the heat dissipating efficiency, improve the electrical performance and increase the number of I/O connections of the semiconductor package.

In order to achieve the foregoing and other objectives, the present invention proposes a leadframe-based semiconductor package, comprising: a leadframe having a plurality of leads; a chip mounted on the leadframe, wherein the chip has an active surface defined with a first region and a second region surrounded by the first region; a plurality of first conductive bumps implanted to the first region of the active surface of the chip, for electrically connecting the chip to the leads of the leadframe; a plurality of second conductive bumps implanted to the second region of the active surface of the chip, for electrically connecting the chip directly to an external device; and an encapsulant for encapsulating the chip, the first conductive bumps, the second conductive bumps and the leadframe, wherein a bottom surface of each of the leads and a bottom end of each of the second conductive bumps are exposed from the encapsulant. The bottom ends of the second conductive bumps may be exposed by performing a grinding process on the encapsulant and the bottom surfaces of the leads, such that the second conductive bumps act as additional electrical connections for the semiconductor package.

As such, the chip can be electrically connected to the external device via the first conductive bumps and the leads of the leadframe, and may further be electrically connected directly to the external device by the second conductive bumps, such that the number of electrical connections for the semiconductor package is increased by means of the second conductive bumps. The additional electrical connections provided by the second conductive bumps implanted to the second region of the active surface of the chip not only may serve as grounding or power connections but also may function as signal I/O connections for the chip, thereby desirably increasing the number of I/O connections for the semiconductor package. This solves the problem of not able to increase the number of I/O connections as in the prior art.

Further, the chip in the semiconductor package may have a redistribution layer for redistributing bond pads of the chip to the first and second regions of the active surface of the chip, such that the first conductive bumps can be implanted to the first region of the active surface of the chip and the second conductive bumps can be implanted to the second region of the active surface of the chip, so as to desirably increase the overall number of I/O connections for the semiconductor package.

Moreover, besides the plurality of leads, the leadframe of the semiconductor package can also comprise a conductive pad (die pad), such that a portion of the second conductive bumps implanted to the second region of the chip can be attached to and electrically connected to the conductive pad to serve as grounding or power connections. The rest of the second conductive bumps, which are not attached to the conductive pad, are exposed from the encapsulant and serve as I/O connections.

The present invention also proposes a fabrication method of the foregoing leadframe-based semiconductor package, comprising the steps of: preparing a leadframe and a chip, the leadframe having a plurality of leads and the chip having an active surface defined with a first region and a second region surrounded by the first region, wherein a plurality of first conductive bumps are implanted on the first region of the active surface of chip and a plurality of second conductive bumps are implanted on the second region of the active surface of the chip; attaching and electrically connecting the first conductive bumps on the chip to the corresponding leads of the leadframe; forming an encapsulant to encapsulate the chip, the first and second conductive bumps and the leadframe; and performing a grinding process on the encapsulant and bottom surfaces of the leads so as to expose the second conductive bumps from the encapsulant.

The above fabrication method of the semiconductor package further comprises: forming a redistribution layer on the active surface of the chip, for redistributing bond pads of the chip to the first region and the second region of the chip. This allows the bond pads, if not disposed at proper positions on the chip originally, to be redistributed to the proper positions where the first conductive bumps can be implanted to the first region of the chip and correspond in position to the leads and the second conductive bumps can be implanted to the second region of the chip and subsequently exposed from the encapsulant to serve as additional I/O connections for the semiconductor package.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of a semiconductor package and a fabrication method thereof as proposed in the present invention are described as follows with reference toFIGS. 3A to 3B,4A to4F and5A to5B.

The following embodiments are exemplified by a Flip-Chip Quad Flat Non-Leads (FC-QFN) semiconductor package and a fabrication method thereof. It should be understood that the drawings are simplified schematic diagrams only showing the elements relevant to the present invention, and the layout of elements could be more complicated in practical implementation.

First Preferred Embodiment

FIGS. 3A and 38are respectively a plan view and a cross-sectional view of a semiconductor package3according to a first preferred embodiment of the present invention. As shown inFIGS. 3A and 38, the semiconductor package3comprises: a leadframe30, a chip31mounted on the leadframe30, and an encapsulant32for encapsulating the leadframe30and the chip31. The leadframe30comprises a plurality of leads300, wherein an inner end300aof each of the leads300is directed toward a center of the leadframe30, and the inner ends300aof the leads300define and surround a spacing300b. Each of the leads300further has a top surface300cand an opposite bottom surface300d. The leadframe30may be made of a metallic material, such as copper or an alloy thereof. The leadframe30can be formed by any suitable conventional method such as punching, etching, or the like.

The chip31has an active surface310on which a redistribution layer (RDL, not shown) is formed. The redistribution layer is used to redistribute a plurality of electrical connections such as bond pads311on the chip31to desirable positions on the active surface310. As the formation of the redistribution layer is conventional and well known to persons skilled in the art, detailed description thereto and physical indication thereof in the drawings are herein omitted. The active surface310of the chip31is further defined with a first region310a(e.g. a peripheral region as shown) and a second region310b(e.g. a central region as shown) surrounded by the first region310a, such that a portion of the bond pads311are positioned within the first region310aand the rest of the bond pads311are positioned within the second region310b.

A plurality of first conductive bumps33, for serving as I/O connections for the chip31, are implanted to the corresponding bond pads311located within the first region310aof the active surface310of the chip31, such that when the chip31is mounted on the leadframe30, each of the first conductive bumps33is bonded to the top surface300cof a corresponding one of the leads300. Accordingly, the chip31is electrically connected to the leads300of the leadframe30by the first conductive bumps33.

In addition to the first conductive bumps33, a plurality of second conductive bumps34are implanted to the corresponding bond pads311located within the second region310band are received in the spacing300bof the leadframe30. The second conductive bumps34are used for serving as power connections, grounding connections, heat-dissipating connections, and/or I/O connections for the chip31, such that the chip31can be directly electrically connected to an external device, such as a printed circuit board (not shown), by the second conductive bumps34. In order to establish the direct connection relationship with the external device, the second conductive bumps34are required to be exposed from the encapsulant32. Accordingly, an exposed portion (e.g. a bottom end) of each of the second conductive bumps34is made to be flush with the bottom surfaces300dof the leads300and a lower surface320of the encapsulant32. This thus allows the exposed portions of the second conductive bumps34and the bottom surfaces300dof the leads300to be electrically connected to the external device in a coplanar manner.

Further, the height of each of the second conductive bumps34has to be greater than that of each of the first conductive bumps33, so as for the second conductive bumps34to be exposed from the encapsulant32. That is, the height of each of the second conductive bumps34has to be equal to the sum of the height of each of the first conductive bumps33and the thickness of each of the leads300.

Also, for the sake of further enhancing the bonding strength between the leadframe30and the encapsulant32, the inner end300aof each of the leads300may additionally be etched or punched from the bottom surface300dto form a recess300e. Thus, the leads300can be anchored into the encapsulant32by allowing the encapsulant32to fill the recesses300eof the leads300.

It is thus clear that the semiconductor package3of the present invention, with provision of the second conductive bumps34bonded to the chip31, has an increased number of I/O connections than that of the prior art, such that the electrical performance of the semiconductor package3is enhanced.

The semiconductor package3of the present invention can be fabricated by a method shown inFIGS. 4A to 4F.

As shown inFIGS. 4A and 4B, a semiconductor chip31having an active surface310is prepared. A plurality of bond pads311, such as I/O connections, power connections, grounding connections and so on, are formed on the active surface310of the chip31. The active surface310is defined with a first region310aand a second region310bsurrounded by the first region310a, wherein a portion of the bond pads311are disposed within the first region310aand the rest of the bond pads311are disposed within the second region310bby means of a redistribution technology. As shown inFIG. 4C, a plurality of first conductive bumps33are implanted on the bond pads311formed in the first region310aof the active surface310of the chip31to serve as I/O connections for the chip31, and a plurality of second conductive bumps34are implanted on the bond pads311formed in the second region310bof the active surface310of the chip31to serve as electrical connections such as power connections, grounding connections and/or I/O connections. The height of each of the second conductive bumps34is greater than that of each of the first conductive bumps33.

As shown inFIG. 4D, a leadframe30, which can be made of copper or an alloy thereof, is provided. The leadframe30comprises a plurality of leads300, wherein each of the leads300has an inner end300adirected toward a center of the leadframe30, with a spacing300bbeing defined and surrounded by the inner ends300aof the leads300. Further, each of the leads300has a top surface300cand an opposite bottom surface300d. The chip31is mounted to the leadframe30by having each of the first conductive bumps33bonded to the top surface300cof a corresponding one of the leads300. As shown inFIG. 4E, an encapsulant32is formed for encapsulating the chip31, the first conductive bumps33, the second conductive bumps34and the leadframe30, with the bottom surfaces300dof the leads300being exposed from the encapsulant32.

As shown inFIG. 4F, a grinding process is carried out to grind the bottom surfaces300dof the leads300and a lower surface320of the encapsulant32until a desired portion (e.g. a bottom end340) of each of the second conductive bumps34is exposed from the encapsulant32. By such processing, the bottom ends340of the second conductive bumps34are flush with the bottom surfaces300dof the leads300and the lower surface320of the encapsulant32. This thus completes the fabrication of the semiconductor package3shown inFIGS. 3A and 3B. Since the grinding process is performed, the final thickness of the fabricated semiconductor package3can be reduced to a desired extent.

The foregoing fabrication method of the semiconductor package of the present invention may optionally comprise a step of plating the bottom surfaces300dof the leads300with a solder layer (not shown) following the completion of the grinding process, such that the semiconductor package3can be electrically connected to an external device such as a printed circuit board via the solder layer and the second conductive bumps34exposed from the encapsulant32.

Second Preferred Embodiment

FIGS. 5A and 5Bare respectively a plane view and a cross-sectional view of a semiconductor package according to a second preferred embodiment of the present invention. The semiconductor package of the second embodiment is similar to that of the first embodiment, with a primary difference in that the leadframe further comprises at least one conductive pad (die pad) formed in a central portion of the leadframe and spaced apart from a plurality of leads formed in a peripheral portion of the leadframe.

Particularly, as shown inFIGS. 5A and 5B, the semiconductor package5of the second embodiment comprises: a leadframe50, a chip51attached to the leadframe50, and an encapsulant52for encapsulating the leadframe50and the chip51. The leadframe50includes a plurality of leads500, and a die pad501spaced apart from and surrounded by the plurality of leads500. Each of the leads500has a top surface500aand an opposite bottom surface500b, and the die pad501has a top surface501aand an opposite bottom surface501b. And between the leads500and the die pad501there is formed a spacing502with a predetermined width.

The chip51has an active surface510, wherein the active surface510is defined with a first region510a, a second region510bwithin the first region510a, and a third region510cwithin the second region510b. A plurality of bond pads511are formed on the active surface510and disposed within the first region510a, the second region510b, and the third region510c. By such arrangement, a plurality of first conductive bumps53can be implanted on the bond pads511located within the first region510a, a plurality of second conductive bumps54can be implanted on the bond pads511located within the second region510b, and a plurality of third conductive bumps55can be implanted on the bond pads511located within the third region510c. The chip51is attached to the leadframe50via the active surface510in a manner that the first conductive bumps53are bonded to the top surfaces500aof the leads500, the second conductive bumps54are received in the spacing502, and the third conductive bumps55are bonded to the top surface501aof the die pad501. Thus, the chip51is electrically connected to the leadframe50by the first conductive bumps53and the third conductive bumps55.

The second conductive bumps54are greater in height than the first and third conductive bumps53,55respectively, such that subsequent to the formation of the encapsulant52, bottom ends540of the second conductive bumps54are exposed from the encapsulant52and are used to electrically connect the chip51to an external device such as a printed circuit board. Likewise, the bottom surfaces500bof the leads500and the bottom surface501bof the die pad501are also exposed from the encapsulant52and are coplanar with the bottom ends540of the second conductive bumps54. Thus, the die pad501may act as a power connection, a grounding connection and/or a heat-dissipating connection for the chip51, and the second conductive bumps54may act as I/O connections for the chip51. As such, desired multi-functionality, electrical performance and heat dissipating efficiency for the semiconductor package5can be achieved.

The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. For example, a non-active surface of the chip opposing to the active surface thereof may be exposed from an upper surface of the encapsulant opposing to the lower surface thereof, allowing the exposed non-active surface of the chip to be optionally adhered to a heat spreader in order to enhance the heat dissipating performance of the semiconductor package. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.