SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A semiconductor device includes a substrate. A 2-D material channel layer is over the substrate, in which the 2-D material channel layer includes a channel region and source/drain regions on opposite sides of the channel region. Source/drain metals are over of the source/drain regions of the 2-D material channel layer. A gate metal is over the substrate and non-overlapping the 2-D material channel layer along a vertical direction, in which the gate metal is laterally separated from the 2-D material channel layer by an air gap.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

FIGS.1A to5Cillustrate a semiconductor device in various stages of fabrication in accordance with some embodiments of the present disclosure. Although the views shown inFIGS.1A to5Care described with reference to a method, it will be appreciated that the structures shown inFIGS.1A to5Care not limited to the method but rather may stand alone separate of the method. AlthoughFIGS.1A to5Care described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

Reference is made toFIGS.1A to1C, in whichFIG.1Ais a top view of a semiconductor device,FIG.1Bis a cross-sectional view along line B-B ofFIG.1A, andFIG.1Cis a cross-sectional view along line C-C ofFIG.1A. Shown there is a substrate100. In some embodiments, the substrate100may function to provide mechanical and/or structure support for features or structures that are formed in the subsequent steps of the process flow illustrated inFIGS.1A to5C. These features or structures may be parts or portions of an integrated circuit (e.g., transistor, interconnect structure, etc.) that may be formed on or over the substrate100.

Generally, the substrate100illustrated inFIGS.1A to1Cmay include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulator layer below a thin semiconductor layer that is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include the crystalline semiconductor material silicon, but may include one or more other semiconductor materials such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like) or combinations thereof. The semiconductor materials may be doped or undoped. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. In some other embodiments, the substrate100may include sapphire (e.g. crystalline Al2O3), e.g. a large grain or a single crystalline layer of sapphire or a coating of sapphire. As another example, the substrate100may be a sapphire substrate, e.g. a transparent sapphire substrate comprising, as an example, α-Al2O3. Other elementary semiconductors like germanium may also be used for substrate100.

A 2-D material layer110is formed over the substrate100. In some embodiments, the 2-D material layer110is in direct contact with the top surface of the substrate100. As used herein, consistent with the accepted definition within solid state material art, a “2-D material” may refer to a crystalline material consisting of a single layer of atoms. As widely accepted in the art, “2-D material” may also be referred to as a “monolayer” material. In this disclosure, “2-D material” and “monolayer” material are used interchangeably without differentiation in meanings, unless specifically pointed out otherwise. The 2-D material layer110may be 2-D materials of suitable thickness. In some embodiments, a 2-D material includes a single layer of atoms in each of its monolayer structure, so the thickness of the 2-D material refers to a number of monolayers of the 2-D material, which can be one monolayer or more than one monolayer. The coupling between two adjacent monolayers of 2-D material includes van der Waals forces, which are weaker than the chemical bonds between/among atoms within the single monolayer.

In some embodiments, the 2-D material layer110is made of graphene. In some embodiments, the 2-D material layer110is made of a single monolayer graphene. In some embodiments, exemplary technique for forming a graphene layer utilizes CVD (chemical vapor deposition) directly on the substrate100. In some embodiments, the graphene layer may be formed by epitaxial graphene growth. For example, a silicon carbide dielectric is used as a seed layer to promote the epitaxial growth of the graphene on the substrate100. In some other embodiments, graphene layer may be formed on a backing material (such as an adhesive tape), the backing material can be adhered to the substrate100. Then, the backing material can be removed while leaving the graphene layer on the substrate100. In some other embodiments, graphene is formed by reacting a metal film with silicon carbide to form a metal carbide. The metal carbide is annealed to produce a metal silicide and graphene from the remaining carbon. In yet other exemplary embodiments, graphene layer is deposited using an aqueous solution of graphene oxide. In other embodiments, the 2-D material layer110can also be made of silicene, germanene, and stanene. In other embodiments, the 2-D material layer110can also be made of molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or the like.

FIG.1Dillustrates a molecular diagram300of graphene (e.g., the 2-D material layer110) according to some embodiments of the present disclosure. Graphene is an arrangement of carbon atoms302in mono-layers aligned along a single plane304. As pure graphene has a high conductivity, it may be doped with one or more impurities to control mobility and induce a semiconductor-like response to a gate voltage. In various embodiments, the graphene may be doped with titanium, chromium, iron, NH3, potassium, and/or NO2.

Reference is made toFIGS.2A to2C, in whichFIG.2Ais a top view of a semiconductor device,FIG.2Bis a cross-sectional view along line B-B ofFIG.2A, andFIG.2Cis a cross-sectional view along line C-C ofFIG.2A. A contact electrode layer120is formed over the 2-D material layer110. The contact electrode layer120may include a gate contact electrode120G and source/drain contact electrodes120SD. In some embodiments, top surface of the 2-D material layer110may be exposed from the gate contact electrode120G and the source/drain contact electrodes120SD. In some embodiments, top surface of the gate contact electrode120G may be level with top surfaces of the source/drain contact electrodes120SD. In some embodiments, bottom surface of the gate contact electrode120G may be level with bottom surfaces of the source/drain contact electrodes120SD.

In greater details, as shown in the top view ofFIG.2A, the gate contact electrode120G may encloses the source/drain contact electrodes120SD. For example, the gate contact electrode120G may include a rectangular ring-shape portion120G-1and two extension portions120G-2connected to an inner sidewall of the ring-shape portion120G-1. In some embodiments, the extension portions120G-2may extend toward each other along the Y-direction. Stated another way, the extension portions120G-2may align with each other along the Y-direction. On the other hand, the source/drain contact electrodes120SD may align with each other along the X-direction.

In some embodiments, the contact electrode layer120may include conductive material, such as metal. Exemplary metal may include copper (Cu), ruthenium (Ru), iridium (Ir), rhodium (Rh), gold (Au), silver (Ag), platinum (Pt), tungsten (W), or other suitable metals. In some embodiments, the contact electrode layer120may be made of elemental 2-D material such as antimonene, stanine, or the like.

In some embodiments, the contact electrode layer120may be formed by, for example, depositing a conductive layer blanket over the 2-D material layer110, and then performing a lithography process to pattern the conductive layer according to a pre-determined pattern. In some embodiments, the conductive layer may be deposited using thermal evaporation, e-beam deposition, e-gun evaporation, sputtering, or other suitable deposition methods. In some embodiments, the lithography process may be e-beam lithography, or other suitable lithography processes.

In some other embodiments, the contact electrode layer120may be formed by, for example, forming a patterned mask, such as photoresist, over the 2-D material layer110, in which the patterned mask includes openings which define the positions and profiles of the contact electrode layer120. A conductive layer is deposited over the patterned mask and filling the openings of the patterned mask. Then, the patterned mask is removed through a suitable process (e.g., a lift-off process), and the portions of the conductive layer in the openings of the patterned mask remain over the 2-D material layer110and serve as the contact electrode layer120.

Reference is made toFIGS.3A to3C, in whichFIG.3Ais a top view of a semiconductor device,FIG.3Bis a cross-sectional view along line B-B ofFIG.3A, andFIG.3Cis a cross-sectional view along line C-C ofFIG.3A. A metal layer130is formed over the substrate100and covering portions of the 2-D material layer110and the contact electrode layer120. In some embodiments, the metal layer130may include gate metals130G and source/drain metals130SD. In some embodiments, top surfaces of the gate metals130G may be level with top surfaces of the source/drain metal130SD. In some embodiments, bottom surfaces of the gate metals130G may be level with bottom surfaces of the source/drain metal130SD.

As shown inFIG.3A, with respect to the source/drain metals130SD, the source/drain metals130SD may extend along the X-direction, and may align with each other along the X-direction. Moreover, the width of each source/drain metal130SD along the Y-direction is less than the maximal width of the corresponding source/drain contact electrode120SD along the Y-direction. In some embodiments, the shortest distance between the source/drain metals130SD along the X-direction is less than the shortest distance between the source/drain contact electrodes120SD along the X-direction.

As shown inFIG.3B, with respect to the source/drain metals130SD, each of the source/drain metals130SD may extend from top surface of a corresponding source/drain contact electrode120SD, through sidewall of the corresponding source/drain contact electrode120SD, to top surface of the 2-D material layer110. Accordingly, each of the source/drain metals130SD may include a stepped top surface profile and a stepped bottom surface profile.

As shown inFIG.3A, with respect to the gate metals130G, the gate metals130G may extend along the Y-direction, and may align with each other along the Y-direction. Moreover, the width of each gate metals130G along the X-direction is less than the maximal width of the corresponding extension portion120G-2of the gate contact electrode120G along the X-direction. In some embodiments, the shortest distance between the gate metals130G along the Y-direction is less than the shortest distance between the extension portions120G-2of the gate contact electrode120G along the Y-direction.

As shown inFIG.3C, with respect to the gate metals130G, each of the gate metals130G may extend from top surface of a corresponding extension portion120G-2of the gate contact electrode120G, through sidewall of the corresponding extension portion120G-2of the gate contact electrode120G, to top surface of the 2-D material layer110. Accordingly, each of the gate metals130G may include a stepped top surface profile and a stepped bottom surface profile.

In some embodiments, the metal layer130may include conductive material, such as metal. Exemplary metal may include copper (Cu), ruthenium (Ru), iridium (Ir), rhodium (Rh), gold (Au), silver (Ag), platinum (Pt), tungsten (W), or other suitable metals.

In some embodiments, the metal layer130may be formed by, for example, depositing a conductive layer blanket over the substrate100and covering the 2-D material layer110and the contact electrode layer120, and then performing a lithography process to pattern the conductive layer according to a pre-determined pattern. In some embodiments, the conductive layer may be deposited using thermal evaporation, e-beam deposition, e-gun evaporation, sputtering, or other suitable deposition methods. In some embodiments, the lithography process may be e-beam lithography, or other suitable lithography processes.

In some other embodiments, the metal layer130may be formed by, for example, forming a patterned mask, such as photoresist, covering the 2-D material layer110and the contact electrode layer120, in which the patterned mask includes openings which define the positions and profiles of the metal layer130. A conductive layer is deposited over the patterned mask and filling the openings of the patterned mask. Then, the patterned mask is removed through a suitable process (e.g., a lifting process), and the portions of the conductive layer in the openings of the patterned mask remain over the 2-D material layer110and the contact electrode layer120and serve as the metal layer130.

Reference is made toFIGS.4A to4C, in whichFIG.4Ais a top view of a semiconductor device,FIG.4Bis a cross-sectional view along line B-B ofFIG.4A, andFIG.4Cis a cross-sectional view along line C-C ofFIG.4A. A patterned mask MA1is formed over the substrate100and covering portions of the metal layer130and the 2-D material layer110.

As shown in the cross-section view ofFIG.4B, the patterned mask MA1is in contact with top surface of the 2-D material layer110. Moreover, the patterned mask MA1is in contact with top surface of the source/drain metals130SD and sidewalls of the source/drain metals130SD. In some embodiments, the patterned mask MA1may vertically overlap portions of the source/drain metals130SD. However, the patterned mask MA1may not overlap the source/drain contact electrodes120SD. That is, the patterned mask MA1may be laterally separated from the source/drain contact electrodes120SD by a non-zero distance.

As shown in the cross-section view ofFIG.4C, the patterned mask MA1is in contact with top surface of the 2-D material layer110. However, the patterned mask MA1may not overlap the gate metals130G and the gate contact electrode120G. That is, the patterned mask MA1may be laterally separated from the gate metals130G and the gate contact electrode120G by a non-zero distance. InFIG.4C, the lateral distance D1(along the Y-direction) between the patterned mask MA1and each gate metal130G is in a range from about 1 nm to 300 nm. The lateral distance D1is tuned to achieve desired device performance, which will be discussed later.

In some embodiments, the patterned mask MA1may be a photoresist layer. In some embodiments, the photoresist layer may be formed by spinning, spray coating, or other applicable techniques. The photoresist layer may include a light sensitive material such that properties, such as solubility, of the photoresist layer are affected by light.

Reference is made toFIGS.5A to5C, in whichFIG.5Ais a top view of a semiconductor device,FIG.5Bis a cross-sectional view along line B-B ofFIG.5A, andFIG.5Cis a cross-sectional view along line C-C ofFIG.5A. An etching process is performed to remove portions of the 2-D material layer110that are exposed by the patterned mask MA1, the metal layer130, and the contact electrode layer120. After the etching process is completed, the patterned mask MA1is removed.

In some embodiments, the etched 2-D material layer110may include a remaining portion110A and a remaining portion110B, in which the remaining portion120A is spatially separated from the remaining portion110B. The remaining portions110A and110B of the 2-D material layer110can also be referred to as 2-D material layers110A and110B. InFIG.5B, the 2-D material layer110A is covered at least in part by the source/drain metals130SD and the source/drain contact electrodes120SD, and a portion of the 2-D material layer110A is exposed by the source/drain metals130SD and the source/drain contact electrodes120SD. On the other hand, inFIG.5C, the 2-D material layer110B is under the gate contact electrode120G and the gate metals130G. In some embodiments, an entirety of the 2-D material layer110B is under the gate contact electrode120G and the gate metals130G. In some embodiments, the 2-D material layer110A is free of coverage by the gate contact electrode120G and the gate metals130G. That is, the gate contact electrode120G and the gate metals130G do not vertically overlap the 2-D material layer110A.

In some embodiments, the gate metals130G, the source/drain metals130SD, and the 2-D material layer110A may collectively serve as a transistor. The transistor is an in-plane gate transistor (IPGT). The 2-D material layer110A may act as a channel layer of the transistor, and can also be referred to as a 2-D material channel layer. In some embodiments, the portion of the 2-D material layer110A under the source/drain metals130SD (and/or under the source/drain contact electrode120SD) can be referred to as source/drain regions of the 2-D material layer110A. On the other hand, the portion of the 2-D material layer110A exposed by the source/drain metals130SD (and/or exposed by the source/drain contact electrode120SD) can be referred to as channel region of the 2-D material layer110A.

As shown inFIGS.5A and5C, air gaps AR1may present between the channel region of the 2-D material layer110A and the corresponding one of the gate metals130G. In some embodiments, the air gaps AR1can act as gate dielectric layers of the transistor, which laterally separate the channel region of the 2-D material layer110A from the gate metals130G. The lateral width W1of the air gap AR1(along the Y-direction) between the channel region of the 2-D material layer110A and the corresponding gate metals130G is in a range from about 1 nm to about 300 nm. In some embodiments, the lateral width W1of each air gap AR1can be determined by the profile of the patterned mask MA1(seeFIGS.4A to4C). In some embodiments, if the lateral width W1is too large (e.g., greater than 1000 nm), the air gaps AR1may be too large and the transistor may not work due to large gate-channel separation. On the other hand, if the lateral width W1is too small, the air gaps AR1may be too small and may not be able to obtain a desired device performance.

Reference is made toFIG.6A. To demonstrate the feasibility of 2-D material on the architecture of in-plane gate transistor, a graphene film grown directly on sapphire substrate is prepared. The Raman spectrum of the sample is shown inFIG.6A. InFIG.6A, the ratio of D/G peak is around 0.4, which indicates that a continuous graphene film could be grown directly on sapphire substrate using CVD. Compared with the counterpart where a graphene film is grown on copper foils, the graphene film grown on sapphire substrate requires no transferring processes and can further simplify the device fabrication. Therefore, the growth scheme is suitable for the architecture of in-plane gate transistor.

Reference is made toFIG.6B. The voltage-current transfer curves of the device (e.g., the transistor shown ofFIGS.5A to5C) under forward and reverse biases at VDS=0.5 V are shown. Standard characteristics of graphene transistor with the Dirac point located at about 30 V gate biases are observed for the device. The derived hole mobility and the derived electron mobility of the device are 90.0 and 77.0 cm2/V·s, respectively. The hole mobility is close to that commonly observed for the directly grown graphene films via the Hall measurement (p-type, 100-200 cm2/V·s). The result supports the architecture of in-plane gate transistor for 2-D material and shows the potential for abandoning gate dielectrics (e.g., using air gap as gate dielectric).

FIGS.7A to11Cillustrate a semiconductor device in various stages of fabrication in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.7A to11Care similar to or the same as those described inFIGS.1A to5C, such elements are labeled the same, and relevant details will not be repeated for brevity.

Reference is made toFIGS.7A to7C, in whichFIG.7Ais a top view of a semiconductor device,FIG.7Bis a cross-sectional view along line B-B ofFIG.7A, andFIG.7Cis a cross-sectional view along line C-C ofFIG.7A. A 2-D material layer110is formed over the substrate100, which has been described inFIGS.1A to1C. After the 2-D material layer110is formed, a passivation layer200is formed over the 2-D material layer110. In some embodiments, the passivation layer200may be vertically separated from the substrate100through the 2-D material layer110.

In some embodiments, the passivation layer200may be made of a 2-D material, and thus the passivation layer200can also be referred to as a 2-D material passivation layer200. In some embodiments, the 2-D material passivation layer200is made of a different 2-D material than the 2-D material layer110. For example, the 2-D material passivation layer200may be made of transition metal dichalcogenides (TMDs). In some embodiments, the 2-D material passivation layer200contains metal element, while the 2-D material layer110is free of metal element. In some embodiments, the 2-D material passivation layer200is a less conductive 2-D material layer, while the 2-D material layer110is a conductive 2-D material layer (e.g., graphene).

FIG.7Dillustrates a schematic view of a mono-layer400of an example TMD in accordance with some example embodiments. InFIG.7D, the one-molecule thick TMD material layer includes transition metal atoms402and chalcogen atoms404. The transition metal atoms402may form a layer in a middle region of the one-molecule thick TMD material layer, and the chalcogen atoms404may form a first layer over the layer of transition metal atoms402, and a second layer underlying the layer of transition metal atoms402. The transition metal atoms402may be W atoms or Mo atoms, while the chalcogen atoms404may be S atoms, Se atoms, or Te atoms. Throughout the description, the illustrated cross-bonded layers including one layer of transition metal atoms402and two layers of chalcogen atoms404in combination are referred to as a mono-layer400of TMD.

In some embodiment where the 2-D material passivation layer200includes TMD monolayers, the TMD monolayers include molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or the like.

In some embodiments where the 2-D material passivation layer200is made of MoS2, a MoO3film may be deposited over a graphene layer (e.g., the 2-D material layer110) by using thermal evaporation. After the MoO3is deposited, a sulfurization procedure is performed. The substrate (e.g., the substrate100) is placed in the center of a furnace for sulfurization. In some other embodiments, other physical deposition techniques such as molecular beam epitaxy (MBE), e-gun evaporation, RF sputtering and pulse laser deposition (PLD) may also be adopted for the depositions of the transition metals. In some embodiments, the 2-D material passivation layer200can be deposited with a temperature under 400° C.

In some other embodiments, the passivation layer200may be made of a dielectric material. For example, the dielectric material may be an oxide, such as aluminum oxide (Al2O3), silicon oxide (SiO2), or the like.

Reference is made toFIGS.8A to8C, in whichFIG.8Ais a top view of a semiconductor device,FIG.8Bis a cross-sectional view along line B-B ofFIG.8A, andFIG.8Cis a cross-sectional view along line C-C ofFIG.8A. A contact electrode layer120is formed over the passivation layer200. In some embodiments, top surface of the passivation layer200may be exposed from the gate contact electrode120G and the source/drain contact electrodes120SD of the contact electrode layer120.

Reference is made toFIGS.9A to9C, in whichFIG.9Ais a top view of a semiconductor device,FIG.9Bis a cross-sectional view along line B-B ofFIG.9A, andFIG.9Cis a cross-sectional view along line C-C ofFIG.9A. A metal layer130is deposited over the substrate100and covering portions of the passivation layer200and the contact electrode layer120. In some embodiments, the metal layer130may include gate metals130G and source/drain metals130SD.

As shown inFIG.9B, with respect to the source/drain metals130SD, each of the source/drain metals130SD may extend from top surface of a corresponding source/drain contact electrode120SD, through sidewall of the corresponding source/drain contact electrode120SD, to top surface of the passivation layer200.

As shown inFIG.9C, with respect to the gate metals130G, each of the gate metals130G may extend from top surface of a corresponding extension portion120G-2of the gate contact electrode120G, through sidewall of the corresponding gate contact electrode120G, to top surface of the passivation layer200.

Reference is made toFIGS.10A to10C, in whichFIG.10Ais a top view of a semiconductor device,FIG.10Bis a cross-sectional view along line B-B ofFIG.10A, andFIG.10Cis a cross-sectional view along line C-C ofFIG.10A. A patterned mask MA1is formed over the substrate100and covering portions of the metal layer130and the passivation layer200. As shown in the cross-section views ofFIGS.10B and10C, the patterned mask MA1is in contact with top surface of the passivation layer200. InFIG.10C, the lateral distance D1(along the Y-direction) between the patterned mask MA1and each gate metal130G is in a range from about 1 nm to 300 nm.

Reference is made toFIGS.11A to11C, in whichFIG.11Ais a top view of a semiconductor device,FIG.11Bis a cross-sectional view along line B-B ofFIG.11A, andFIG.11Cis a cross-sectional view along line C-C ofFIG.11A. An etching process is performed to remove portions of the 2-D material layer110and the passivation layer200that are exposed by the patterned mask MA1, the metal layer130, and the contact electrode layer120. After the etching process is completed, the patterned mask MA1is removed. In some embodiments, air gaps AR1are formed. The lateral width W1of the air gap AR1(along the Y-direction) between the channel region of the 2-D material layer110A and the corresponding gate metals130G is in a range from about 1 nm to 300 nm.

Similar to the etched 2-D material layer110as described inFIGS.5A to5C, the etched passivation layer200may include a remaining portion200A and a remaining portion200B, in which the remaining portion200A is spatially separated from the remaining portion200B. The remaining portions200A and200B of the passivation layer200can also be referred to as passivation layers200A and200B. In some embodiments, the passivation layer200A is covered at least in part by the source/drain metals130SD and the source/drain contact electrodes120SD, and a portion of the passivation layer200A is exposed by the source/drain metals130SD and the source/drain contact electrodes120SD. On the other hand, the passivation layer200B is under the gate contact electrode120G and the gate metals130G. In some embodiments, an entirety of the passivation layer200B is under the gate contact electrode120G and the gate metals130G. In some embodiments, each air gap AR1is laterally between the passivation layer200A and a corresponding passivation layer200B.

In some embodiments, the top surface of the 2-D material layer110A is covered by the passivation layer200A, while the sidewalls of the 2-D material layer110A may be exposed through the air gaps AR1(seeFIG.11C). Similarly, the top surface of the 2-D material layer110B is covered by the passivation layer200B, while the sidewalls of the 2-D material layer110B may be exposed through the air gaps AR1(seeFIG.11C). That is, the 2-D material layer110A is vertically separated from the source/drain metals130SD and the source/drain metals130SD through the passivation layer200A, and the 2-D material layer110B is vertically separated from the gate contact electrode120G and the gate metals130G through the passivation layer200B. In some embodiments, because the 2-D material layer110and the passivation layer200are etched using a same mask, the 2-D material layers110A and110B may include substantially the same patterns as the passivation layers200A and200B, respectively. For example, inFIG.11C, sidewalls of the 2-D material layer110A may be vertically aligned with sidewalls of the passivation layer200A, and sidewalls of the 2-D material layers110B may be vertically aligned with sidewalls of the passivation layers200B. respectively.

In some embodiments where the passivation layer200is made of 2-D material, the passivation layer200may include few mono-layers. Accordingly, the passivation layer200may be thin enough and would not affect the electrical connection between the 2-D material layer110and the overlying layer, such as the contact electrode layer and the metal layer.

In the embodiments of the present disclosure, when a graphene channel layer is exposed (e.g., the 2-D material layer110ofFIGS.5A to5C), water and gas molecules may affect the property of the graphene channel layer, which will also affect the device performance. For example, for an in-plane gate transistor where graphene channel layer is exposed, the Dirac point shifts to −4.0 V under reverse gate bias (seeFIG.6B), indicating that the water and gas molecules may influence the device performance under the ambient condition. An approach to prevent the attachment of water or gas molecules to the graphene channel layer is to passivate the graphene cannel layer. Since dielectric materials for gates may bring additional influence to the graphene channel and do not conform to the concept behind in-plane gate transistors, one promising candidate for passivation layer can be other 2-D material layer (e.g., the 2-D material passivation layer200). The van der Waal forces instead of chemical bonds between the 2-D material channel layer and the 2-D material passivation layer is the main mechanism why the 2-D material passivation layer is a beneficial choice than other materials.

Reference is made toFIG.12A. The Raman spectra of the MoS2/graphene hetero-structure corresponding to the characteristic peaks of graphene and MoS2are shown, respectively The observation of both the graphene and MoS2Raman peaks indicates that the MoS2/graphene hetero-structure is formed after the sequential growth of graphene and MoS2. The difference delta k between the two Raman peaks of MoS2is 21.3 cm−1, indicating the presence of bi-layer MoS2after the sulfurization procedure. On the other hand, the similar D/G peak ratios of graphene before and after the MoS2growth (around 0.4) suggest that by using the thermal evaporator, a limited amount of damage was introduced to the graphene film during the deposition of MoO3.

Reference is made toFIG.12B. The transfer curves of the device under forward and reverse biases at VDS=1.0 V are shown. Similar to the graphene in-plane gate transistor, the device behaves as a typical graphene transistor. The Dirac point at a positive VGS=10.0 V indicates a p-type graphene channel under forward biases. The weak hysteresis on the transfer curves suggests that the MoS2layer can effectively protect the channel from contaminants in environments. The derived hole mobility and the derived electron mobility of the device are 61.0 and 31.0 cm2/V·s, respectively. Compared with the hole mobility 100-200 cm2/V·s of the graphene film on sapphire from Hall measurements, the field-effect mobility is lower. The derived field-effect mobility values are also lower than the standalone graphene in-plane gate transistors discussed above.

FIGS.13A to20Cillustrate a semiconductor device in various stages of fabrication in accordance with some embodiments of the present disclosure. It is noted that some elements described inFIGS.13A to20Care similar to or the same as those described inFIGS.1A to5Cand inFIGS.7A to11C, such elements are labeled the same, and relevant details will not be repeated for brevity.

Reference is made toFIGS.13A to13C, in whichFIG.13Ais a top view of a semiconductor device,FIG.13Bis a cross-sectional view along line B-B ofFIG.13A, andFIG.13Cis a cross-sectional view along line C-C ofFIG.13A. A 2-D material layer110is formed over the substrate100. After the 2-D material layer110is formed, a passivation layer200is formed over the 2-D material layer110.

Reference is made toFIGS.14A to14C, in whichFIG.14Ais a top view of a semiconductor device,FIG.14Bis a cross-sectional view along line B-B ofFIG.14A, andFIG.14Cis a cross-sectional view along line C-C ofFIG.14A. A patterned mask MA2is formed over the substrate100and covering the passivation layer200. The pattern mask MA2may include openings O1, O2, and O3that expose top surface of the passivation layer200.

In some embodiments, the openings O1, O2, and O3may define the positions and profiles of the gate contact electrode120G (seeFIGS.16A to17C) and the source/drain contact electrodes120SD (seeFIGS.16A to17C), respectively. For example, the opening O1may enclose the openings O2and O3. Moreover, similar to those described with respect to the contact electrode layer120ofFIG.2A, the opening O1may also include a rectangular ring-shape portion and two extension portions connected to an inner sidewall of the ring-shape portion.

In some embodiments, the patterned mask MA2may be a photoresist layer. In some embodiments, the photoresist layer may be formed by spinning, spray coating, or other applicable techniques. The photoresist layer may include a light sensitive material such that properties, such as solubility, of the photoresist layer are affected by light.

Reference is made toFIGS.15A to15C, in whichFIG.15Ais a top view of a semiconductor device,FIG.15Bis a cross-sectional view along line B-B ofFIG.15A, andFIG.15Cis a cross-sectional view along line C-C ofFIG.15A. An etching process is performed to remove portions of the passivation layer200exposed by the openings O1, O2, and O3. As a result, portions of the underlying 2-D material layer110are exposed after the etching process is completed.

In some embodiments, the etching process may include an atomic layer etching (ALE) process. In some embodiments where the passivation layer200is made of MoS2. the ALE process is a layered removal mechanism of MoS2using low-power oxygen plasma. Each ALE cycle includes a low-power oxygen plasma treatment, a dipping procedure, and a re-sulfurization procedure. During the low-power oxygen plasma treatment, the topmost MoS2mono-layer is oxidized. This will result in a weaker adhesion of Mo oxides with underlying MoS2surfaces, which may lead to detachment of the topmost oxidized MoS2layer from the underlying MoS2films. Afterward, the dipping procedure is performed to remove the topmost oxidized MoS2layer. Since MoS2is insoluble and Mo oxides are soluble in water, the dipping procedure of the sample in de-ionized water will help with the complete detachment of the topmost oxidized MoS2layer. In some embodiments, each ALE cycle may remove one mono-layer of the passivation layer200. For example, if the passivation layer200includes 2 mono-layer of MoS2, the ALE cycle may be performed 2 times to remove the exposed passivation layer200, so as to expose the underlying 2-D material layer110. In some embodiments, if the passivation layer200has n mono-layers of 2-D material (e.g., MoS2), the ALE cycles of the etching process may be performed n times.

Reference is made toFIGS.16A to16C, in whichFIG.16Ais a top view of a semiconductor device,FIG.16Bis a cross-sectional view along line B-B ofFIG.16A, andFIG.16Cis a cross-sectional view along line C-C ofFIG.16A. A contact electrode layer120is deposited over the patterned mask MA2and filling the openings O1, O2. and O3. Portions of the contact electrode layer120in the openings O1, O2, and O3may be in contact with top surface of the 2-D material layer110.

In some embodiments, the contact electrode layer120may be formed by a physical deposition process, such as a physical vapor deposition (PVD), an e-gun evaporation deposition, or the like. In some embodiments, the contact electrode layer120has a higher deposition rate on a horizontal surface than on a vertical surface. Accordingly, the contact electrode layer120may include higher deposition rate on the top surface of the patterned mask MA2and the top surface of the exposed 2-D material layer110than on the sidewalls of the patterned mask MA2. In some embodiments, portions of the contact electrode layer120formed in the openings O1, O2, and O3may be in contact with sidewalls of the passivation layer200and sidewalls of the patterned mask MA2. In some embodiments, the portions of the contact electrode layer120formed in the openings O1, O2, and O3may include higher top surfaces than the top surface of the passivation layer200and the bottom surface of the patterned mask MA2.

Reference is made toFIGS.17A to17C, in whichFIG.17Ais a top view of a semiconductor device,FIG.17Bis a cross-sectional view along line B-B ofFIG.17A, andFIG.17Cis a cross-sectional view along line C-C ofFIG.17A. The patterned mask MA2is removed, while leaving portions of the contact electrode layer120in the openings O1, O2, and O3(seeFIGS.16A to16C) remain over the 2-D material layer110. In some embodiments where the patterned mask MA2is made of photoresist, the patterned mask MA2can be removed using a lift-off process. In some embodiments, portions of the contact electrode layer120over the top surface of the patterned mask MA2may be removed together with the patterned mask MA2.

The contact electrode layer120may include a gate contact electrode120G and source/drain contact electrodes120SD. In some embodiments, the gate contact electrode120G may be the portion of the contact electrode layer120formed in the opening O1of the patterned mask MA2, and the source/drain contact electrodes120SD may be the portions of the contact electrode layer120formed in the openings O2and O3of the patterned mask MA2, respectively.

Reference is made toFIGS.18A to18C, in whichFIG.18Ais a top view of a semiconductor device,FIG.18Bis a cross-sectional view along line B-B ofFIG.18A, andFIG.18Cis a cross-sectional view along line C-C ofFIG.18A. A metal layer130is deposited over the substrate100and covering portions of the passivation layer200and the contact electrode layer120. In some embodiments, the metal layer130may include gate metals130G and source/drain metals130SD.

As shown inFIG.18B, with respect to the source/drain metals130SD, the bottommost surface of each of the source/drain metals130SD is higher than the bottom surface of the source/drain contact electrode120SD. The source/drain contact electrodes120SD may be in contact with the 2-D material layer110, while the source/drain metals130SD are vertically separated from the 2-D material layer110through the source/drain contact electrodes120SD and the passivation layer200.

As shown inFIG.18C, with respect to the gate metals130G, the bottommost surface of each of the gate metals130G is higher than the bottom surface of the gate contact electrode120G. The gate contact electrode120G may be in contact with the 2-D material layer110, while the gate metals130G are vertically separated from the 2-D material layer110through the gate contact electrode120G and the passivation layer200.

Reference is made toFIGS.19A to19C, in whichFIG.19Ais a top view of a semiconductor device,FIG.19Bis a cross-sectional view along line B-B ofFIG.19A, andFIG.19Cis a cross-sectional view along line C-C ofFIG.19A. A patterned mask MA1is formed over the substrate100and covering portions of the metal layer130and the passivation layer200. As shown in the cross-section views ofFIGS.19B and19C, the patterned mask MA1is in contact with top surface of the passivation layer200. InFIG.19C, the lateral distance D1(along the Y-direction) between the patterned mask MA1and each gate metal130G is in a range from about 1 nm to 300 nm.

Reference is made toFIGS.20A to20C, in whichFIG.20Ais a top view of a semiconductor device,FIG.20Bis a cross-sectional view along line B-B ofFIG.20A, andFIG.20Cis a cross-sectional view along line C-C ofFIG.20A. An etching process is performed to remove portions of the 2-D material layer110and the passivation layer200that are exposed by the patterned mask MA1, the metal layer130, and the contact electrode layer120. After the etching process is completed, the patterned mask MA1is removed. In some embodiments, air gaps AR1are formed. The lateral width W1of the air gap AR1(along the Y-direction) between the channel region of the 2-D material layer110A and the corresponding gate metals130G is in a range from about 1 nm to 300 nm.

The etched passivation layer200may include a remaining portion200A and a remaining portion200B, in which the remaining portion200A is spatially separated from the remaining portion200B. The remaining portions200A and200B of the passivation layer200can also be referred to as passivation layers200A and200B.

In the cross-sectional view ofFIG.20B, the passivation layer200A is covered at least in part by the source/drain metals130SD. Different from the embodiments shown inFIGS.7A to11C, the source/drain contact electrodes120SD are in contact with sidewalls of the passivation layer200A, while top surface of the passivation layer200A is free of coverage by the source/drain contact electrodes120SD. In some embodiments. the bottom surface of the passivation layer200A may be substantially level with the bottom surfaces of the source/drain contact electrodes120SD.

In the cross-sectional view ofFIG.20C, the passivation layer200B is covered by the gate metals130G. Different from the embodiments shown inFIGS.7A to11C. the gate contact electrode120G is in contact with sidewalls of the passivation layer200B, while top surface of the passivation layer200B is in contact with the gate metals130G, and is free of coverage by the gate contact electrode120G. In some embodiments, the bottom surface of the passivation layer200B may be substantially level with the bottom surfaces of the gate contact electrode120G.

In the embodiments of the present disclosure, when the graphene channel layer and the contact electrode layer/the metal layer (e.g., the contact electrode layer120and/or the metal layer130) are separated by a passivation layer (e.g., the passivation layer200), the interfaces between the passivation layer and the contact electrode layer/the metal layer may include high contact resistance, which may hinder the supply of carriers as the gate voltage is changed. To examine the effect of contact resistance at the electrode/passivation layer interfaces, the passivation layer beneath the contact electrodes is removed before the electrode deposition, and the resulting structure is shown inFIGS.20A to20C.

Reference is made toFIG.21. The transfer curve of the device ofFIGS.20A to20Cat VDS=1.0 V is shown. The Dirac point of the device is around VGS=20 V. Also shown in the figure is a current enhancement as compared to that inFIG.12Bin the same range of gate voltage. This indicates that with the removal of MoS2beneath the electrodes, the contact resistance becomes lower. The hole mobility and electron mobility of the device are 328.0 and 187.0 cm2/V·s, respectively. In addition to the current enhancement due to the more significant accumulation of the carrier in the channel, the field-effect mobilities become 2 to 3 times higher than the Hall-effect ones from graphene grown on the sapphire. It is noted that the mobility extracted from the Hall measurement reflects the transport properties without altering the intrinsic carrier density of graphene on sapphire. As a result, without being screened at low-density level, the scatterings due to lattice imperfections such as charged impurities or structural defects can all impede carrier drifting. In contrast, after the issue of contact resistance is resolved, the in-plane gates may easily attract more carriers into the graphene channel. The Coulomb effect from these additionally provided carriers can screen the interactions between lattice imperfections and drifted carriers. The scattering in the channel is screened more in the presence of the higher carrier density. Therefore. by increasing the carrier density through gating, not only the drain current but also the mobility is enhanced.

Reference is made toFIG.22A. The transfer curves of the device ofFIGS.20A to20Cunder dark and light-irradiation conditions are shown. The light source is a white light source equipped with the microscope of the probe station. The Dirac point shift from 20.0 to 15.0 V suggests that photo-excited electrons in the MoS2layer are attracted by the positive drain voltage to the graphene channel and change the Fermi level. The results revealed that with more complicated 2-D material structures such as MoS2/graphene hetero-structure, different device applications such as photo-transistors can be demonstrated. The derived hole mobility and electron mobility of the device reach 1210.0 and 205.0 cm2/V·s, respectively, under light illumination. The increment of field-effect mobility may be also attributed to the enhanced screening effect mentioned earlier in the presence of photo-excited carriers. On the other hand, the potential of scalability and reproducibility of the device is important for practical applications.

Reference is made toFIGS.22B and22C. Transfer curves of two more devices ofFIGS.20A to20Cwith the same device architecture under dark and light-irradiation conditions are shown. The similar device performances have demonstrated that the scalability and reproducibility of the in-plane gate graphene transistors can be achieved through the fabrication procedure as discussed inFIGS.13A to20C.

According to the aforementioned embodiments, it can be seen that the present disclosure offers advantages in fabricating integrated circuits. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. Embodiments of the present disclosure provide an in-plane gate transistor by using 2-D material as channel layer. The result supports the architecture of in-plane gate transistors for 2-D materials and shows the potential for abandoning gate dielectrics. Another embodiment of the present disclosure provide an in-plane gate transistor by using 2-D material as channel layer, in which a passivation layer is formed over the 2-D material channel layer. The result shows that the passivation layer can effectively protect the 2-D material channel layer from contaminants, and will further improve device performance. Yet another embodiment of the present disclosure provide an in-plane gate transistor by using 2-D material as channel layer, in which a passivation layer is formed over the 2-D material channel layer, and portions of the passivation layer is removed prior to forming the electrode layer. The result shows that removal of the passivation layer can reduce the contact resistance, and will further improve device performance.

In some embodiments of the present disclosure, a semiconductor device includes a substrate. A 2-D material channel layer is over the substrate, in which the 2-D material channel layer includes a channel region and source/drain regions on opposite sides of the channel region. Source/drain metals are over of the source/drain regions of the 2-D material channel layer. A gate metal is over the substrate and non-overlapping the 2-D material channel layer along a vertical direction, in which the gate metal is laterally separated from the 2-D material channel layer by an air gap.

In some embodiments, the semiconductor device further includes a 2-D material layer in contact with a top surface of the substrate and a bottom surface of the gate metal.

In some embodiments, the 2-D material channel layer and the 2-D material layer are made of a same material.

In some embodiments, the semiconductor device further includes a 2-D material passivation layer in contact with a top surface of the 2-D material channel layer, in which the 2-D material passivation layer and the 2-D material channel layer are made of different 2-D materials.

In some embodiments, the 2-D material channel layer is made of a conductive 2-D material and the 2-D material passivation layer is made of a less conductive 2-D material.

In some embodiments, the semiconductor device further includes source/drain contact electrodes over the source/drain regions of the 2-D material channel layer, in which each of the source/drain metals extends from a top surface of a corresponding one of the source/drain contact electrodes to a sidewall of the corresponding one of the source/drain contact electrodes. A gate contact electrode is over the substrate, in which the gate metal extends from a top surface of the gate contact electrode to a sidewall of the gate contact electrode.

In some embodiments, a lateral width of the air gap between the 2-D material channel layer and the gate metal is from about 1 nm to 300 nm.

In some embodiments of the present disclosure, a semiconductor device includes a substrate. A 2-D material channel layer is over the substrate, in which the 2-D material channel layer includes a channel region and source/drain regions on opposite sides of the channel region. A 2-D material passivation layer has a first portion covering a top surface of the 2-D material channel layer. Source/drain contact electrodes are over of the source/drain regions of the 2-D material channel layer. A gate contact electrode is over the substrate and non-overlapping the 2-D material channel layer along a vertical direction.

In some embodiments, the 2-D material channel layer is made of graphene, and the 2-D material passivation layer is made of transition metal dichalcogenides.

In some embodiments, the first portion of the first portion is in contact with sidewalls of the source/drain contact electrodes.

In some embodiments, the source/drain contact electrodes are in contact with a top surface of the 2-D material channel layer.

In some embodiments, the 2-D material passivation layer having a second portion in contact with a sidewall of the gate contact electrode, and the first portion of the 2-D material passivation layer is laterally separated from the second portion of the 2-D material passivation layer.

In some embodiments, the semiconductor device further includes a 2-D material layer between the substrate and the gate contact electrode, in which the 2-D material layer is laterally separated from the 2-D material channel layer.

In some embodiments, the 2-D material layer is laterally separated from the 2-D material channel layer by an air gap.

In some embodiments of the present disclosure, a method includes forming a 2-D material layer over a substrate; forming a gate contact electrode and source/drain contact electrodes over the 2-D material layer; forming a first patterned mask covering a channel region of the 2-D material layer, in which the first patterned mask non-overlaps the gate contact electrode along a vertical direction; etching portions of the 2-D material layer uncovered by the first patterned mask, such that the channel region of the 2-D material layer is laterally separated from the gate contact electrode; and removing the first patterned mask.

In some embodiments, the method further includes forming a 2-D material passivation layer over the 2-D material layer prior to forming the gate contact electrode and the source/drain contact electrodes.

In some embodiments, forming the gate contact electrode and the source/drain contact electrodes includes forming a second patterned mask over the 2-D material passivation layer, in which the second patterned mask includes openings exposing the 2-D material passivation layer; and depositing a conductive material in the openings of the second patterned mask, in which the method further includes etching the 2-D material passivation layer through the openings of the second patterned mask prior to depositing the conductive material.

In some embodiments, the method further includes forming a gate metal extending from a top surface of the gate contact electrode to a sidewall of the gate contact electrode, in which a lateral distance between the gate metal and the channel region of the 2-D material layer is less than a lateral distance between the gate contact electrode and the channel region of the 2-D material layer.

In some embodiments, the first patterned mask non-overlaps the gate metal along the vertical direction.

In some embodiments, the 2-D material layer includes a remaining portion under the gate contact electrode after etching the portions of the 2-D material layer, in which the remaining portion of the 2-D material layer is laterally separated from the channel region of the 2-D material layer.