High power FET switch

Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state.

FIELD OF THE DISCLOSURE

This disclosure relates to field effect transistor (FET) switches and methods of operating the same. More particularly, the disclosure relates to stacked FET switches and methods of operating the same.

BACKGROUND

A prior art stacked field effect transistor (FET) switch10connected to an RF line12is depicted inFIG. 1. The stacked FET switch10has an FET device stack14that is formed by a plurality of FET devices16coupled in series. Each of the plurality of FET devices16includes a drain contact, D, a source contact, S, a gate contact, G, and a body contact, B. When the FET device stack14operates in a closed state, the FET device stack14presents a low impedance to the RF line12. This provides a shunt path for a radio frequency (RF) signal18to ground. On the other hand, when the FET device stack operates in the open state, a high impedance is presented to the RF line12and thus, theoretically, the FET device stack14does not conduct any of the time-variant RF signal18. Of course, in practice, some leakage currents are conducted through the FET device stack14during the open state, but generally are low enough so as to be negligible. By stacking the plurality of FET devices16, the time-variant RF signal18can be distributed across the plurality of FET devices16of the FET device stack14allowing the FET device stack14to handle higher voltage RF signals18.

To provide the appropriate biasing voltages for operating the FET device stack14, the stacked FET switch10includes a prior art control circuit20having a DC voltage source22, a negative voltage generator24, a plurality of switches26A,26B,26C,26D, and26E (referred to collectively as “switches26”), and a bias control device28that controls the switches26. The bias control device22controls the plurality of switches26to bias a gate voltage at gate contacts and a body voltage at the body contacts, B, in accordance with Table I below.

The drain and sources contacts, D, S, of the FET devices16are biased at ground or possibly at an RF port that provides a reference voltage during both the open state and the closed state. The voltage at the drain and sources contacts, D, S, does not change with respect the reference voltage. However, by biasing the gate contacts, G, at the voltage −Vbias, the channels of the FET devices16are pinched off and a buffer voltage is provided that ensures that the time-variant RF signal18does not turn on the plurality of FET devices16during the open state. To prevent reverse bias diodes from being formed between the body of each of the plurality of FET devices16and the drain and sources of each of the plurality of FET devices16, the body contacts are also biased at the voltage −Vbias.

One of the problems with this approach is that it requires a negative voltage generator24to maintain the gate contacts, G, at the negative bias voltage −Vbiasrelative to ground during the open state. The negative voltage generator24may be implemented using negative charge pumps that add additional complexity to the control circuit20and may generate spurs. Furthermore, an additional DC voltage source22is required to provide a positive bias, +Vbias, to the gate contacts, G, and operate the FET device stack14in a closed state, which also adds complexity to the control circuit20. If the negative voltage generator24is implemented by the negative charge pumps, the finite output impedance of the negative charge pumps also causes problems during transitions from different states as connections to the gates and body are charged and discharged.

Another problem with the prior art design is that it requires a bias swing of |2Vbias| to turn the FET device stack14from the open state to the closed state, and vice versa. During steady state operation, the bias voltage −Vbias, has been selected so that voltage from the time-variant RF signal18does not cause the voltage at the gate contacts to exceed the breakdown voltage, given the maximum and minimum voltage peaks of the time-variant RF signal18. However, transition states are required so that the voltage between the gate contact, G, and the other drain and source contact, D, S, of the FET devices16do not exceed the voltage handling capabilities of the FET devices16from the open and closed states. Of course this adds additional complexity to the control circuit20, as switches26B-26E and/or logic level shifters, are required to provide the appropriate gate and body voltages during each of these states. These switches26B-26E of control device28must be appropriately timed to avoid stressing the FET devices16during these transitions.

In addition, another disadvantage of the prior art design is that the body contacts, B, must also be negatively biased if the plurality of FET devices16are the type of FET devices that require body biasing. For example, in certain types of FET devices16, internal reverse bias diodes are activated between the body contact, B, and the drain and source contracts, D, S during the open state that prevent the FET device stack14from operating appropriately. If the internal reverse bias diodes are activated and a bias voltage, −Vbias, is not provided at the body contacts, B during the open state, then the voltage drop from the drain contact, D, to the source contacts, S, of each of the plurality of FET devices16would be limited to the voltage of a reverse bias diode, around 0.6 Volts. Thus, the prior art design requires negatively biasing the body contacts, B, to −Vbiasso that the reverse biased diodes are not reverse biased (or at least are not significantly reverse biased) during the open state. Also, the body contacts, B, must be transitioned back to ground when the FET device stack14operates in the closed state. This requires the control circuit20to have switches26C,26D and for the bias control device28to time these switches26C,26D appropriately. Other prior art embodiments use floating body designs and may not include body contacts, B and use self-biasing. However, prior art floating body designs suffer from poor linearity.

Accordingly, there is a need to develop a stacked FET switch with a control circuit that does not require excessive bias swings and negative biasing voltages.

SUMMARY

Embodiments in the detailed description describe a stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. The FET device stack is configured to operate in an open state and in closed state. During the closed state, the plurality of FET devices is turned on and thus a time-variant input signal can be transmitted through the FET device stack. On the other hand, in the closed state, the plurality of FET devices is turned off and the time-variant input signal is blocked from being transmitted through the FET device stack.

Each FET device includes a gate contact, a drain contact, and a source contact. In one embodiment, an FET device in the stack has a source contact at one end of the FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path is provided for one of the end FET device which is configured to pass the time-variant input signal. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The first decoupling path may be connected to one of the end FET devices so that the time-variant input signal bypasses the FET device stack from the gate contact to the source contact of the end FET device during the open state. Consequently, the time-variant input signal either does not cause a voltage drop during the open state from the gate contact of the end FET device to the source contact of the end FET device or the voltage drop is at least substantially reduced.

By decoupling the end FET device from the gate contact to the source contact with respect to the time-variant input signal during the open state, the end FET device is not turned on during large signal conditions while the FET device stack is operating in the open state. In this manner, any chain reaction which forces one or more of the FET devices to be turned on does not force the FET device stack out of the open state.

Alternatively, the first decoupling path may be connected so that the time-variant input signal bypasses the FET device stack from the drain contact to the source contact of the end FET device. Also, as explained in this disclosure, the first decoupling path may instead be connected to another FET device having a drain contact at the oppositely disposed end of the FET device stack. The first decoupling path may be connected so that the time-variant input signal bypasses the FET device stack from the drain contact to the gate contact or from the drain contact to the source contact of this other end FET device. Embodiments having multiple decoupling paths are also disclosed herein.

DETAILED DESCRIPTION

The described devices, systems, and methods include topologies that prevent and/or impede a stacked field effect transistor (FET) switch from being forced out of the open state during large signal conditions. Also, devices, systems, and methods are described that greatly reduce biasing swings caused when a stacked field effect transistor (FET) switch transitions from an open state to a closed state and vice versa. Furthermore, no negative charge pumps are needed to force the negative biasing of FET devices during the open state.

FIG. 2illustrates one embodiment of a stacked FET switch30. The stacked FET switch30includes a plurality of FET devices (referred to generically as elements32and to a specific FET device as elements Q1-Q5) that are coupled in series to one another to form an FET device stack34. In this embodiment, the FET device stack34has five (5) FET devices32. However, as explained in further detail below, the FET device stack34may have any number of FET devices32greater than one (1). Each of the plurality of FET devices32has a source, a drain, and a gate. To make electrical connections to the sources, drains, and gates, each of the plurality of FET devices32include source contacts, S, drain contacts, D, and gate contacts, G. In this example, each of the FET devices32also includes a body contact, B, to connect to a body of the FET device32. However floating body embodiments that do not include a body contact, B, and have bodies that are self-biased can also be implemented in accordance with this disclosure.

The plurality of FET devices32of the stack are coupled in series to form a chain that has a first FET device (Q1), a second FET device (Q2), a third FET device (Q3), a fourth FET device (Q4), and a fifth FET device (Q5). The second FET device, (Q2), the third FET device (Q3), and the fourth FET device (Q4) are middle FET devices (Q2-Q4) which are coupled between the first FET device (Q1) and the fifth FET device (Q5). In the illustrated FET device stack34, the drain contact, D, of the first FET device (Q1) is positioned at the first end38of the FET device stack34and is connected to an input terminal40for receiving a time-variant input signal42, such as a radio frequency (RF) signal. At a second end44of the FET device stack34, the fifth FET device (Q5) has a source contact, S, that is directly connected to an output terminal46which connects to ground.

The FET device stack34may be formed, for example, on a silicon-on-insulator (SOI) type substrate, a silicon-on-sapphire (SOS) type substrate, a Galium Arsenide (GaAs) type substrate, or the like. Each of the plurality of FET devices32in the FET device stack may be a complementary metal-oxide-semiconductor (CMOS) type transistor, such as a metal-oxide-semiconductor field effect transistor (MOSFET). The FET devices32may also be metal semiconductor field effect transistors (MESFET), a high mobility field effect transistor (HFET), or the like. Utilizing SOI type substrates, SOS type substrates, and GaAs type substrates, may be advantageous in some applications because of the high degree of insulation provided by their internal layers. For example, in an SOI type substrate, the FET devices are formed on a device layer and an insulating layer (also known as a Buried Oxide layer “BOX”) may be provided between a handle layer and the device layer. The insulating layer is typically made from an insulating or dielectric type oxide material such as SiO2while the handle layer is typically made from a semiconductor, such as silicon (Si). The degradation in bandwidth normally associated with the stacking of FET devices32and the increased parasitic capacitances of the extra components can be reduced utilizing SOI, SOS, or GaAs type substrates. Other techniques provided in this disclosure may also be utilized to suppress the loading effects of these parasitic capacitances. However, SOI type substrates, silicon-on-sapphire type substrates, and GaAs type substrates are not required and the particular substrate utilized to form the plurality of FET devices32should be determined in accordance with factors for associated with a particular desired application, such as, a required bandwidth response, distortion tolerances, cost, and the like. Also, the sources and drains between one of the plurality of FET devices32and another one of the plurality of FET devices32may be independent of one another or may be merged into a single drain/source having drain and source contacts, D, S for each FET device32.

During an open state of the FET device stack34, the plurality of FET devices32are off and the FET device stack34presents a high impedance between the first end38and the second end44. Consequently, very little current, if any, is transmitted from the FET device stack34to the output terminal46. On the other hand, in the closed state, the plurality of FET devices32have a low impedance and thus transmit the time-variant input signal42to the output terminal46.

To switch the FET device stack34between the open state and the closed state, the stacked FET switch30has a control circuit48that is operably associated with the FET device stack34. In this embodiment, the control circuit48has a DC voltage source50, a first switch52, a second switch54, and a bias control device56. The first switch52and the second switch54may be any type of suitable switch for providing the desired bias voltages. For example, the first switch52and second switch54may be transistor switches or inverters. The control circuit48is connected to each of the gate contacts, G, and to the first end38of the FET device stack34through the resistor Rds_common. Since the drain contact, D, is at the first end38of the FET device stack34, one could also state that the control circuit48is connected to the drain contact, D, of the first FET device (Q1), through the resistor, Rds_common. The middle FET devices (Q2-Q4) each have a resistor, Rds, coupled between the drain contact, D, and the source contact, S. The fifth FET device (Q5) has a resistor Rds1connected to the drain contact, D. The resistors, Rds1, Rds_common, may provide power dissipation, and impedance matching for the FET devices32.

The stacked FET switch30may include a DC blocking device, such as a first capacitor58, coupled in series between the input terminal40and the first end38of the FET device stack34. The first capacitor58may help distribute the time-variant input signal42across the FET device stack34. A DC blocking device, such as a second capacitor60, is coupled between the bottom of resistor, Rds1, and a grounded terminal61. The first capacitor58and the second capacitor60may hold the bias applied by the control circuit48so that the source contacts, S, and drain contacts, D, of the first FET device (Q1) and the middle FET devices (Q2-Q4) are biased appropriately. In addition, the second capacitor60also operates to block the bias applied by the control circuit48and, in this manner, the source contact, S, of the fifth FET device (Q5) experiences no or very little biasing from the control circuit48. The resistors, Rds1, Rds_common, the first capacitor58, and the second capacitor60are connected to each of the plurality of FET devices32so that the voltage stress of the time-variant input signal42is appropriately distributed across the FET device stack34during the open state and so that the appropriate drain and source contacts, D, S, are biased by the control circuit48. This distribution may be done in conjunction with the parasitic coupling afforded by the parasitic capacitances of the FET devices32between the gate to source, gate to drain, body to source, gate to body, and/or body to drain. These parasitic capacitances may occur at high frequencies above the high pass filter poles of the stacked FET switch30.

By applying the bias to the drain contact, D, of the first FET device (Q1), the control circuit48ofFIG. 2is connected to bias the drain contact, D and the source contact, S, of each of the FET devices (Q1-Q4). In this embodiment, the source contact, S, of the fourth FET device (Q4) and the drain contact, D, of the fifth FET device (Q5) are directly connected to one another and thus biasing the drain contact, D and the source contact, S, of each of the FET devices (Q1-Q4) also biases the drain contact, D, of the fifth FET device (Q5). Consequently, all of the drain and source contacts S, D, between the drain contact, D, of the first FET device (Q1) and the drain contact, D, of the fifth FET device (Q5) are biased by the control circuit48. However, the second capacitor60operates as a DC block which prevents the control circuit48from biasing the source contact, S, of the fifth FET device (Q5).

While the control circuit48is connected to the drain contact, D, of the first FET device (Q1), through a resistor, Rds_common, the control circuit48may be connected, either directly or indirectly, to any one, more than one, or all of the to the drain contact, D, of the fifth FET device (Q5), through the drain contact, D, and/or source contacts, S, of the FET devices (Q1) to provide the appropriate bias voltages. In the illustrated embodiment, the control circuit48may be connected anywhere to the FET device stack34where the bias of the FET device stack34is not blocked by the first capacitor58and the second capacitor60. For example, the control circuit48may be connected to apply the bias between the bottom of resistor, Rds1, and the top of the second capacitor60. Different connection topologies between the control circuit48and FET device stack34may be advantageous or disadvantageous for different reasons. Sensitivity to turn-on times may be considered when determining the particular circuit topology for connecting the control circuit48with the FET device stack34. Also, loading effects may be considered for the particular application. For example, the path that connect the control circuit48to the drain contact, D of the first FET device (Q1) has resistors, Rds_common, which may present a load at the first end38of the FET device stack34. While this connection topology may be advantageous in reducing distortion, the connection topology may also cause leakage currents. In addition, different types of filtering devices (not shown) and the like may be connected between the control circuit48and the FET device stack34to prevent the time-variant input signal42from leaking into and damaging the control circuit48. These and other circuit topologies for connecting the control circuit48to the FET device stack34would be apparent to one of ordinary skill in the art in light of this disclosure.

To place the FET device stack34in the closed state, the control circuit48biases the gate contacts, G, of each of the plurality of FET devices32at a first voltage, +Vbias, relative to a reference voltage. In this example, the reference voltage is ground. In alternative embodiments, the reference voltage may be at other voltage levels depending on the design requirements of the stacked FET switch30or the external nodes that are connected to the stacked FET switch30. If the plurality of FET devices32are depletion mode type FET devices32, the plurality of FET devices32have a reverse biased pinch-off voltage (−Vp). Since the first voltage, +Vbias, is positive relative to the reference voltage (ground in this case) and has a magnitude greater than a reverse biased pinch-off voltage, (−Vp), the plurality of FET devices32are turned on by the first voltage, +Vbias. For a depletion-mode type FET device32, the pinch-off voltage (−Vp) is the voltage at the gate contact, G, relative to a voltage of the source contact, S, at which a channel of the FET device32is pinched off. In other words, if a reverse bias greater than the pinch-off voltage, (−Vp), is applied between the gate contact, G, and the source contact, S, of the FET device32, the FET device32is turned off and placed in the open state. On the other hand, the plurality of FET devices32may also be enhancement mode type FET devices32. In this case, a forward-biased pinch-off voltage, (+Vp), (also known as a threshold voltage) is required to turn on the channel of the FET device32. As a result, if a forward bias less than the pinch-off voltage, (+Vp), is applied between the gate contact, G, and the source contact, S, of the enhancement mode type FET device32, the enhancement mode FET device32is turned off and placed in the open state. Accordingly, the FET devices32are placed in the closed state by the first voltage, +Vbias, because the first voltage is greater than the pinch-off voltage, (+Vp) or (−Vp) depending on the type of FET device32.

In the illustrated embodiment ofFIG. 2, the plurality of FET devices32are the same type of FET device32and have essentially the same characteristics. For example, the FET devices may all be considered to have relatively the same reverse biased pinch-off voltage, (−Vp). It should be noted that this is not required. In other embodiments, each or some of the plurality of FET devices32may be of different types and have different characteristics. In these alternative embodiments, the first voltage, +Vbias, should be selected accordingly to provide the appropriate voltage for the channels of each of the FET devices32and place FET device stack34in the closed state.

Referring again toFIG. 2, the control circuit48applies a second voltage to the drain contact, D of the first FET device (Q1) during the closed state. The second voltage should be less than the first voltage but non-negative relative to the reference voltage. In this embodiment, the second voltage is the same as the reference voltage, which in this case is ground; however, in other embodiments, higher voltages having a voltage level between the reference voltage and the first voltage may be selected. By applying the second voltage at the drain contact, D of the first FET device (Q1), each of drain contacts, D, and source contacts, S, from the drain contact, D, of the first FET device (Q1), through the drain contact, D, of the fifth FET device (Q5) are also biased to ground. The source contact of the fifth FET device (Q5) is coupled to ground through the output terminal46. Accordingly, the control circuit48biases the gate contacts, G, of the plurality of FET devices32at the first voltage relative to the source contacts, S, which are at ground. In this manner, each of the gate contacts, G, of the FET device32are above the reverse biased pinch-off voltage, (−Vp) relative to their respective source contacts, S, and the FET devices32are each turned on. Accordingly, the FET device stack34is switched into the closed state and the time-variant input signal42is transmitted through the FET device stack34.

The control circuit48is also operable to place the FET device stack34in the open state by biasing the gate contacts, G, of the plurality of FET devices32at the second voltage (in this case ground) relative to a reference voltage (in this case ground). Also, the control circuit48applies a bias to the drain contact, D, of the first FET device (Q1) at the first end38at the first voltage, +Vbias, during the open state. This in turn causes each of drain contacts, D, and source contacts, S, from the first FET device (Q1) through the fourth FET device (Q4), to be positively biased at the first voltage, +Vbias, relative to the reference voltage. The drain contact, D, of the fifth FET device (Q5) is also biased at +Vbiassince it is directly connected to the source contact, S, of the fourth FET device (Q4). The second capacitor60holds the bias +Vbiasfor each of drain contacts, D, and source contacts, S, from the first FET device (Q1) through the fourth FET device (Q4) and for the drain contact, D, of the fifth FET device (Q5). The second capacitor60also blocks the bias so that the source contact, S, of the fifth FET device (Q5) is not biased by the control circuit48at +Vbias. As discussed above, the second voltage of the illustrated embodiment is the same as reference voltage, which is ground, and thus the gate contacts, G, of each of the plurality of FET devices32are biased at zero (0) volts relative to ground during the open state. Notice that while each of the gate contacts, G, of the plurality of FET devices32are non-negatively biased relative to the reference voltage, the gate contacts, G, are negatively biased at −Vbiasrelative to each of drain contacts, D, and source contacts, S, from the first to the fourth FET device (Q1-Q4) through the fourth FET device (Q4) and the drain contact, D, of the fifth FET device (Q5).

As discussed above, the first capacitor58and the second capacitor60are configured to block the bias applied by the control circuit48and thus, the source contact, S, of the fifth FET device (Q5) is not biased (or at least not significantly biased) at the first voltage, +Vbias, during the open state by the control circuit48. To prevent the time-variant input signal42from activating the gate to source of the fifth FET device (Q5), a first decoupling path62is provided and configured to pass the time-variant input signal42during the open state. In this embodiment, the first decoupling path62has a first decoupling capacitor64. The first decoupling capacitor64is configured to pass the time-variant input signal42by presenting a low impedance to the time-variant input signal42relative to the impedance of the fifth FET device (Q5) during the open state. In this manner, the time-variant input signal42does not present a (significant) voltage load between the gate contact, G, and the source contact, S, of the fifth FET device (Q5).

In the illustrated embodiment, the drains and sources of the FET devices32are congruent and the impedance characteristics between the drain contact, D, and the gate contact, G, and the source contact, S, and the gate contact, G, of each of the FET devices32are essentially the same. Thus, the voltage drop of the time-variant input signal42from the drain contact, D, to the gate contact, G, and from the gate contact, G, to the source contact, S, for each of the first through fourth FET devices (Q1-Q4) is essentially the same when the FET device stack34reaches steady state conditions. Thus half of the voltage drop for the time-variant input signal42across each of the first through fourth FET devices (Q1-Q4) occurs from the drain contact, D, to the gate contact, G, and the other half occurs from the gate contact, G, to the source contact, S during the open state. As explained in further detail below, the voltage drop of the time-variant input signal42from the drain contact, D, to the gate contact, G, of the fifth FET device (Q5) is the same as the voltage drop from one of the gate contact, G, to drain contact, D, or gate contact, G, to source contact, S, of voltage drops of the first through fourth FET devices (Q1-Q4) during the open state. In other words, the voltage drop of the time-variant input signal42across the fifth FET device (Q5) is half of the voltage drop across one of the middle FET devices (Q2-Q4) during the open state.

To prevent the gate to source of the fifth FET device (Q5) from being activated during the open state, the first decoupling path62is connected to the FET device stack34such that the time-variant input signal42bypasses the FET device stack34from the gate contact, G, to the source contact, S, of the fifth FET device (Q5). In the illustrated embodiment, the first decoupling path62is connected directly to the gate contact, G, and the source contact, S. In this manner, the time-variant input signal42does not present a (significant) voltage load from the gate contact, G, to the source contact, S, of the fifth FET device (Q5).

By selecting the magnitude of, the first voltage, +Vbias, with respect to the pinch-off voltage, in this case, (−Vp), prevents the time-variant input signal42from forcing the FET device stack34out of the open state. This is because the first voltage +Vbias, creates a buffer that prevents the activation of FET device stack34from the source contact, S, of the first FET device (Q1), through the drain contact, D, of the fifth FET device (Q5). This buffer can be expressed as the bias voltage +Vbiasplus the pinch-off voltage, (−Vp), as shown below:
Vbuffer=+Vbias+(−Vp)

Since the time-variant input signal42must cause a voltage greater than +Vbias+(−Vp), at the gate contacts, G, to turn on the FET devices (Q1-Q4) during the open state, the buffer of Vbuffer=+Vbias+(−Vp) prevents the FET device stack34from being forced out of the open state. The FET devices32may have congruent drains and sources that have similar activation and deactivation characteristics between the gate contact, G and the drain contact, D, and the gate contact, G, and the source contact, S. In this case, biasing the drain contact, D, of the FET devices32also provides a buffer of +Vbias+(−Vp) that prevents the drain to gate of the FET devices32from being activated in the open state of the FET device stack34. Accordingly, biasing the drain contact, D, of the fifth FET device (Q5) also provides the same buffer of +Vbias+(−Vp) that prevents the drain to gate of the fifth FET device (Q5) from being activated in the open state of the FET device stack34.

For depletion mode type FET devices32, the buffer is less than the magnitude of the bias voltage +Vbias. However, for enhancement mode type FET devices32, the buffer is greater than the magnitude of +Vbias, i.e. Vbuffer=+Vbias+(+Vp). Also note that, if in the alternative, the drains and sources of one or more of the FET devices32is not congruent then the buffer may be different between the gate contact, G, and the drain contact, D, and the source contact, S, and the gate contact, G, of the FET device32.

The buffer, Vbuffer, is provided by the control circuit48without requiring the use of a negative voltage source, such as a negative-charge pump. In addition, the bias swing from the open state to the closed state and vice versa at the gate contacts, G, of each of the plurality of FET devices is only the first voltage minus the second voltage. In this case, the first voltage is at +Vbiasand the second voltage is at ground and thus the bias swing created by the control circuit is only |Vbias|. Since the voltage swing is not greater than |Vbias|, transition states are not needed to prevent the voltage between the drain and gate contacts, D, G, of the FET devices32from exceeding the voltage handling capabilities of the FET devices32when transitioning to and from the open and closed states.

The FET device stack34is also prevented from being forced out of the open state by the first decoupling path62. The first decoupling path62is configured to pass the time-variant input signal42during the open state so that the time-variant input signal42causes no or a small voltage drop from the gate contact, G, to the source contact, S of fifth FET device (Q5) during the open state. Utilizing the first decoupling path62instead of simply biasing the source contact, S, of the fifth FET device (Q5) may have certain advantages during large signal conditions when the time-variant input signal42can create very high voltages where the buffer, Vbuffer, may be insufficient to prevent the activation of the FET device (Q1-Q4) and the fifth FET device (Q5) from the drain contact, D, to the source contact, S. Since the first decoupling path62bypasses the time-variant input signal42, no or a small voltage load is presented by the time-variant input signal42from the gate contact, G, to the source contact, S, of the fifth FET device (Q5). Thus, the gate to source of the fifth FET device (Q5) remains off and any chain reaction caused by the activation of any of the other the drain to gate contacts, D, S, or gate to source contacts, G, S, of the FET devices32may be stopped to maintain the FET device stack34in the open state. While the FET device stack34may lose half of the load handling capabilities of the fifth FET device (Q5) due to the first decoupling path62, the first decoupling path62prevents the FET device stack34from being forced out of the open state during large signal conditions.

Note that in the illustrated embodiment, the plurality of FET devices32have essentially the same characteristics and it was also assumed that the impedance characteristics between both the gate contacts, G, and the drain contact, D, and the gate contact, G and the source contacts, S, of each of the FET devices32are substantially congruent at the frequencies of interest. However, this is not necessarily the case, and in other embodiments, each or some of the plurality of FET devices32may be of different types having different characteristics. In these alternative embodiments, the first voltage, +Vbias, should be selected accordingly to place FET device stack34in the open state and provide the appropriate buffer without causing excessive bias swings. Also, the FET device stack34should distribute the voltage of the time-variant input signal42across the FET device stack34in accordance with the impedance characteristics of the FET devices32to reduce the probability of damaging the FET devices32or creating excessive leakage currents. For example, in certain applications, the fifth FET device (Q5) may be formed to be wider than the middle FET devices (Q2-Q4) to help reduce leakage currents.

To help ensure that the voltage drop of the time-variant input signal42is appropriately distributed across the FET device stack34, a distribution network may be provided on the FET device stack34. One example of such a distribution network is shown inFIG. 2, as the first capacitor58, the second capacitor60, and resistors, Rds, Rds1, and Rds_common. The first capacitors58and second capacitor60operate as DC blocks and may help evenly distribute the time-variant input signal42. Also, the first capacitor58and second capacitor60behave as high-pass filters by blocking the bias voltages from the control circuit48but presenting a low impedance to the time-variant input signal42in the open state. Note that the bottom of the resistor Rds1is connected to the top of the second capacitor60. As a result, the voltage drop of the time-variant input signal42across the resistor Rds1, is the same as the voltage drop from the drain contact, D, to the gate contact, G. In essence, the resistor Rds1and the drain to gate of the fifth FET device (Q5) appear essentially in parallel to the time-variant input signal42during the open state and thus experience the same voltage drop with respect to the time-variant input signal42. The voltage drop from the drain contact, D, to the source contact, S, of each of the FET devices (Q1-Q4) is about the same as the voltage drop across the resistors, Rds.

As discussed above, each of the FET devices32ofFIG. 2may have congruent drains and sources and thus have the same impedance characteristics from the gate contact, G, to the drain contact, D, and from the gate contact, G, to the source contact, S. Since the time-variant input signal42bypasses the FET device stack34from the gate contact, G, to the source contact, S, of the fifth FET device (Q5), the distribution network may be configured to evenly distribute the time-variant input signal42across the remaining gate to source contacts, G to S, and gate to drain contacts, G to D of the FET device stack34during the open state. Accordingly, the resistive value of Rds1may be about half of the resistive value of the resistors, Rds, since as explained above, the first decoupling path62prevents a significant voltage drop of the time-variant input signal42from the gate contact, G, to the source contact, S, of the fifth FET device (Q5). The resistor, Rds_common, may also be utilized to prevent currents from leaking into the control circuit48for the FET device stack34.

It should be noted however that this is simply one example of a distribution network for distributing the time-variant input signal42across the FET device stack34and the distribution network may have any other suitable circuit topology. For instance, active components, such as transistors, may be utilized to replace one or more of the passive resistors, Rds_common, Rds1, and Rds, and/or the first and second capacitors58,60. In addition, if the FET devices32are different types of devices and are not substantially similar to one another, the relationship between the resistance values of the resistors Rds_common, Rds1, and Rds, may vary in accordance to the impedance characteristics of each of the FET devices32or the voltage loading desired across any one of the FET devices32. For example the resistance of resistors Rds_common, Rds1, and Rdsmay vary if one or more of FET devices32have dissimilar impedance characteristics to the other FET devices32or if one or more of the FET devices32do not have congruent drains and sources. Other circuit components in addition to resistors, Rds, such as capacitors, may also couple across the drain contacts, D, and source contacts, S, to help ensure a more even distribution of the time-variant input signal42across the FET device stack34. The capacitors may be implemented utilizing metal-insulator-metal (MIM) capacitors or parasitic capacitors if desired. In addition, variations in the voltage loading across the FET device stack34caused by practical considerations, such as leakage currents, may require circuit topologies for the distribution network to correct for non-ideal behavior.

Next, the plurality of FET devices32in the stacked FET switch30ofFIG. 2each have a body and a body contact, B, to bias the body of the FET device32. The body contacts, B, of the plurality of FET devices32are biased to a bias voltage, in this case ground, whether the FET device stack34is in the open state or in the closed state. Biasing the body contact, B, of the plurality of FET devices32may be utilized to help define the voltages in the bodies of the plurality of FET devices32and reduce distortion. However, in the alternative, the plurality of FET devices32may not have body biasing. For example, alternative embodiments may have floating body designs even if the FET devices32are the type of FET devices32that require a negative bias between the transistor bodies and the drain and source contacts, D, S, to prevent the activation of reverse-body diodes when the FET device stack34is operating in the open state. While the body contacts, B, of the plurality of FET devices32inFIG. 2may be biased to ground, the drain contacts, D, and source contacts, S, of the first through fourth FET devices (Q1-Q4) and the drain contact of the fifth FET device (Q5) are biased to the first voltage, +Vbias, during the open state. Thus, the voltage bias seen between the body contacts, B, and the drain and source contacts, D, S, is a negative voltage, in this case −Vbias. Accordingly, a negative voltage is presented at the body contacts, B, relative to the drain and source contacts, D, S, without requiring a negative voltage source, such as a negative-charge pump. As a result, floating body topologies may be utilized even if the FET devices32are the type of FET devices32that require a negative bias to prevent the activation of reverse-body diodes.

The stacked FET switch30may also include a resistive circuit66coupled to body contacts, B, of the FET devices (Q1-Q4). The resistive circuit66includes a resistor, Rb_common, and a resistor, Rb, coupled in series with each of the plurality of body contacts, B. The resistance presented by the resistive circuit66at the body contacts, B, may be high relative to the parasitic capacitances between the bodies the FET devices (Q1-Q4) and the source and drain contacts, S, D at the frequency of interest. Other alternative circuit topologies provide the high resistance at the body terminals, B. For example and without limitation, all of the high resistance may be provided by a single resistor, such as, Rb_common, or alternatively, Rb_common, may not be provided at all. Active devices, such as transistors, may also be utilized. These and other circuit topologies for the resistive circuit would be apparent to one of ordinary skill in the art in light of this disclosure.

The stacked FET switch30inFIG. 2also includes a second decoupling path68coupled directly to the body contact, B, of the fifth FET device (Q5) and to ground. Thus, the time-variant input signal42does not present a voltage load at the body contact, B, of the fifth FET device (Q5) and the voltage at the body contact, B, of the fifth FET device (Q5) is well defined at ground which may help prevent the reverse-body diodes in the body of the fifth FET device (Q5) from being turned on by the time-variant input signal42.

It should be noted that, if the FET devices32are CMOS type transistors built having a deep nwell, it may be desirable for the bias voltage at the body contacts, B, to be greater than the reference voltage to help avoid the activation of the reverse-body under large signal conditions. To do this, the body contacts, B, may be coupled to the positive terminal of the DC voltage source,50, or to another internal or external voltage source, instead of ground. In other embodiments, the bodies of the FET devices32may be left floating and the deep nwell may be biased through a high value resistor to allow the deep nwell to self-bias under large signal conditions.

The stacked FET switch30shown byFIG. 2includes a resistive circuit70that is coupled to the gate contacts, G, of the plurality of FET devices32. In this embodiment, the resistive circuit66includes a common resistor, Rg_common, and resistors, Rg, coupled in series to each one of the gate contacts, G. The resistive circuit70should present a high resistance at each of the gate contacts, G, relative to an impedance of the parasitic capacitances between the gates of the plurality of FET devices32and the drains and sources, such that the parasitic capacitances are rendered negligible at the frequency of interest. In this manner, the resistive circuit70does not load the FET device stack34and the FET device stack34has less distortion while preserving bandwidth. Other alternative circuit topologies may be utilized to provide the high resistance. For example and without limitation, all of the high resistance may be provided by a single resistor, such as, Rg_common, or alternatively, Rg_common, may not be provided at all. Active devices, such as transistors, may also be utilized. These and other circuit topologies for the resistive circuit66would be apparent to one of ordinary skill in the art, in light of this disclosure.

As mentioned above, the control circuit48ofFIG. 2is operably associated with the gate contacts, G of each of the FET devices32, the drain contacts, D, and source contacts, S, of the first through fourth FET devices (Q1-Q4), and the drain contact, D, of the fifth FET device (Q5) to provide the appropriate bias voltages relative to the reference voltage. The bias voltage at the gate contacts, G, may be referred to as VGwhile the bias voltage provided to the drain contacts, D, and source contacts, S, of the first through fourth FET devices (Q1-Q4), and the drain contact, D, of the fifth FET device (Q5) is referred to as Vstack. The bias voltages, VG, and Vstackare presented in the Table II below.

As mentioned above, the first voltage is positive relative to the reference voltage and the second voltage is non-negative relative to the reference voltage but lower than the first voltage. For the illustrated embodiment discussed above forFIG. 2, the specific bias voltages VG, Vstackare shown in the Table III below.

The control circuit48of the stacked FET switch30may be configured in any manner to provide the above mentioned bias voltages, VG, and Vstackin Tables II, III. The control circuit48may include, for example, logic controllers, sequential controllers, feedback controllers, and/or linear controllers. The control circuit48may also receive and transmit control signals and/or have internal programming and memory to determine when to switch the FET device stack34to and from the open and the closed states. In addition, while the DC voltage source50is included within the illustrated embodiment of the control circuit48, but in alternative embodiments, the control circuit48may simply connect to an external voltage source(s) to provide the appropriate bias voltage.

The stacked FET switch30described above forFIG. 2does not require transition states when switching to and from the open state and the closed state, as shown by Tables II and III. Note, however, that this may not always be the case and alternative embodiments, fast-switch, high stress, or high voltage applications for the FET device stack34may require transition states to prevent excessive loading of the FET devices32or to ensure that the stacked FET switch30functions appropriately with external devices. Thus, the topology and control functions of the control circuit48may vary in accordance with the particular application for the stacked FET switch30. Also, while the second voltage should be non-negative relative to the reference voltage, practical considerations and non-ideal circuit behavior may cause the second voltage to be slightly negative with respect to the reference voltage. Although the second voltage would still remain substantially non-negative relative to reference voltage (in this case ground), the second voltage may have a small negative difference between around (−0.1 V to −0.2V) relative to the reference voltage. In any case, the small negative difference needs to have a magnitude less than 10% of the magnitude of the first voltage relative to the reference voltage.

Next, the control circuit48illustrated inFIG. 2is configured to provide the bias voltages utilizing the DC voltage source50, the first switch52, the second switch54, and the bias control device56. The positive terminal of the DC voltage source50provides the first voltage, +Vbias, and the grounded terminal provides the second voltage at ground. Connected to the positive terminal and the negative terminal of the DC voltage source50are the first and second switches52,54, which are operated by the bias control device56. The first switch52connects to the gate contacts, G, of the plurality of FET devices32to provide the bias voltage, VGat the gate contacts, G. The second switch54is connected to the drain contact, D, of the first FET device (Q1) apply the bias voltage, Vstack. The bias control device56controls the first and second switches52,54, in accordance with Table III above and switch the FET device stack34to and from the open and closed states.

The first and second capacitors58,60may be utilized to appropriately biased the FET device stack34such that the drain contacts, D, and source contacts, S, of the first through fourth FET devices (Q1-Q4), and the drain contact, D, of the fifth FET device (Q5) are biased by Vstackin accordance with Table III, while the second end44and thus the source contact, S, of the fifth FET device (Q5) are not biased by the control circuit48during the open and closed states.

The stacked FET switch30may be useful in building shunt and series coupled RF switches where the input terminal40is connected to an RF line. Additionally, the stacked FET switch30may be useful in building programmable capacitor arrays (not shown). As is known in the art, programmable capacitor arrays, also known as digitally tunable capacitors, contain switches that open and close paths to different capacitors and thereby vary the capacitance of the programmable capacitor array. These programmable capacitor arrays are often utilized in RF circuits, such as antenna tuners. The stacked FET switch30inFIG. 2already has the first capacitor58coupled in series between the input terminal40and the first end38to help distribute the time-variant input signal42more evenly across the FET device stack34. If a plurality of stacked FET switches, each like the stacked FET switch30inFIG. 2, were utilized and coupled accordingly, then the first capacitor58in each of the plurality of stacked FET switches could also provide the capacitance for the programmable capacitor array without any additional overhead or loss. Thus, proper calibration of the first capacitor58in an array of stacked FET switches, each like the stacked FET switch30inFIG. 2, may allow one or more control circuits48to vary the capacitance of the programmable capacitor array by selecting which of the stacked FET switches to open and close. Note that while the embodiment inFIG. 2has the output terminal46coupled to ground. Consequently, the stacked FET switch30may be utilized as a shunt switch for an RF line. However, in the alternative, the FET device stack34may be coupled in series in an RF line so that the output terminal46is an RF port.

FIG. 3illustrates another embodiment of a stacked FET switch74. The stacked FET switch74is similar to the stacked FET switch30described above, inFIG. 2. However, inFIG. 3, a first decoupling path76is configured to pass the time-variant input signal42during the open state through a first decoupling transistor78which is operably associated and controlled by a control circuit80. The first decoupling transistor78is a FET device, as illustrated inFIG. 3, or, in the alternative, any other suitable type of transistor. Resistors, Rpath, may be provided to provide a high resistance so that the first decoupling transistor78does not load the FET device stack34.

In the stacked FET switch74ofFIG. 3, the control circuit80is connected to the gate contact, G, of the first decoupling transistor78so that it is biased in accordance with Vstackfrom Table II and Table III above. Thus, the first decoupling path76is configured to pass the time-variant input signal42by having the first decoupling transistor78being turned on during the open state of the FET device stack34. In this manner, a low impedance relative to the impedance of the fifth FET device (Q5) is presented to the time-variant input signal42and the time-variant input signal42bypasses the FET device stack34from the gate contact, G, of the fifth FET device (Q5) to the source contact, S, of the fifth FET device (Q5) during the open state. Consequently, the time-variant input signal42drop no or a small voltage from the gate contact, G, of the fifth FET device (Q5) to the source contact, S, of the fifth FET device (Q5) when the FET device stack34is in the open state. On the other hand, the first decoupling transistor78is turned off during the closed state of the FET device stack34so that the time-variant input signal42is transmitted through and does not bypass the FET device stack34from the gate contact, G, of the fifth FET device (Q5) to the source contact, S, of the fifth FET device (Q5). In this case, the first decoupling transistor78is coupled directly from the gate contact, G, of the fifth FET device (Q5) to the output terminal46so that when the first decoupling transistor78is on the FET device stack34is bypassed from gate contact, G, to the source contact, S, of the fifth FET device (Q5). Note that the output terminal46in the stacked FET switch74is coupled to ground. In this embodiment, the reference voltage for measuring the first and second voltage of Table II above is ground and the second voltage is +0V with relative to ground.

FIG. 4illustrates another embodiment of a stacked FET switch82in which decoupling is provided at the first FET device (Q1) rather than the fifth FET device (Q5). As in the previous embodiments, the stacked FET switch82includes a plurality of FET devices (referred to generically as elements84and to a specific FET device as elements Q1-Q5) that are coupled in series to one another to form an FET device stack86. Also, as in the previous embodiments, the FET device stack86has five (5) FET devices84. Each of the plurality of FET devices84has a source, a drain, a gate, and a body. To electrically connect to the sources, drains, gates, and bodies, each of the plurality of FET devices84include source contacts, S, drain contacts, D, gate contacts, G, and body contacts, B. The plurality of FET devices84are coupled in series to form a chain that has a first FET device (Q1), a second FET device (Q2), a third FET device (Q3), a fourth FET device (Q4), and a fifth FET device (Q5). The second FET device, (Q2), the third FET device (Q3), and the fourth FET device (Q4) are middle FET devices (Q2-Q4) which are coupled between the first FET device (Q1) and the fifth FET device (Q5). In the illustrated FET device stack86, the drain contact, D, of the first FET device (Q1) is positioned at the first end88of the FET device stack86and is directly connected to an input terminal90for receiving the time-variant input signal42. At a second end92of the FET device stack86, the fifth FET device (Q5) has a source contact, S.

In this embodiment, a first decoupling path96is connected directly from the gate contact, G, of the first FET device (Q1) to the input terminal90. The first decoupling path96has a first decoupling capacitor98that is configured to pass the time-variant input signal42during the open state. The first decoupling path96is connected to the FET device stack86so that the time-variant input signal42bypasses the FET device stack86from the drain contact, D, of the first FET device (Q1) to the gate contact, G, of the first FET device (Q1) during the open state. Thus, when the FET device stack86is in the open state, no or a small voltage drop is experienced by the time-variant input signal42from the drain contact, D, of the first FET device (Q1) to the gate contact, G, of the first FET device (Q1).

In this embodiment, a control circuit100is operably associated with the FET device stack86to provide the bias voltages, VG, and Vstack, in accordance with Table II above. A distribution network is provided having resistors, Rds_common, Rds, Rds1, a first capacitor102, and a second capacitor104. The first capacitor102is connected from the input terminal90to the top of the resistor, Rds1. Accordingly, the voltage drop from the drain contact, D, to the source contact, S, of the first FET device (Q1) is the same as the voltage drop across resistor, Rds1with respect to the time-variant input signal42. However, the first decoupling path96decouples the first FET device (Q1) from the drain contact, D, to the gate contact, G with respect to the time-variant input signal42. Thus, the voltage dropped by the time-variant input signal42in the first FET device (Q1) is from the gate contact, G, to the source contact, S. Assuming that the FET devices84all have similar characteristics and are substantially symmetrical, the first FET device (Q1) provides about half of the voltage drop as across the other FET devices (Q2-Q5) in the FET device stack86. Accordingly, Rds1is provided to have about half of the resistance value as the other resistors, Rds.

In this arrangement of the distribution network, the connection of first capacitor102allows for the drain contact, D, of the first FET device (Q1) to be directly connected to the input terminal90. The second capacitor104is coupled in series between the source contact, S, of the fifth FET device (Q5) at the second end92and the output terminal94. The first capacitor102and second capacitor104help hold the bias applied by the control circuit100while blocking the DC bias from the control circuit100.

Note that in this embodiment, the input terminal90and the output terminal94are RF ports and may be coupled in series within an RF line. The voltages at the input terminal90and the output terminal94are the RF voltages Vinand Vout. Thus, in this embodiment, the reference voltage is Voutrather than ground. The first voltage and the second voltage are thus measured with respect to Voutinstead of ground but have the same relationships discussed above in Table II.

FIG. 5illustrates yet another embodiment of a stacked FET switch108. As in the previous embodiments, the stacked FET switch108includes a plurality of FET devices (referred to generically as elements110and to a specific FET device as elements Q1-Q5) that are coupled in series to one another to form an FET device stack112. Also, as in the previous embodiments, the FET device stack112has five (5) FET devices110. Each of the plurality of FET devices110has a source, a drain, a gate, and a body. To electrically connect to the sources, drains, gates, and bodies, each of the plurality of FET devices110include source contacts, S, drain contacts, D, gate contacts, G, and body contacts, B. The plurality of FET devices110are coupled in series to form a chain that has a first FET device (Q1), a second FET device (Q2), a third FET device (Q3), a fourth FET device (Q4), and a fifth FET device (Q5). The second FET device, (Q2), the third FET device (Q3), and the fourth FET device (Q4) are middle FET devices (Q2-Q4) which are coupled between the first FET device (Q1) and the fifth FET device (Q5). In the illustrated FET device stack112, the drain contact, D, of the first FET device (Q1) is positioned at the first end114of the FET device stack112and is connected to an input terminal116for receiving the time-variant input signal42through a first capacitor117. At a second end118of the FET device stack112, the fifth FET device (Q5) has a source contact, S, that is directly connected to an output terminal120which connects to ground.

The stacked FET switch108has a first decoupling path122and a second decoupling path124connected to the FET device stack112at the first FET device (Q1). The first decoupling path122and the second decoupling path124, each have a first decoupling capacitor,126, and a second decoupling capacitor,128, respectively. A distribution network is provided that includes resistors, Rds, the first capacitor117, and the second decoupling capacitor128. The first decoupling capacitor126and the second decoupling capacitor128are configured to pass the time-variant input signal42when the FET device stack112is in the open state. The first decoupling path122is connected between the gate contact, G, and the source contact, S, of the fifth FET device (Q5) which configures the FET device stack112so that the time-variant input signal42bypasses the FET device stack112from the gate contact, G, to the source contact, S, of the fifth FET device (Q5) during the open state. The second decoupling path124is connected directly to the drain contact, D, of the fifth FET device (Q5) and to the output terminal120. In this manner, the FET device stack112is configured so that the time-variant input signal42bypasses the FET device stack112from the drain contact, D, to the source contact, S, of the fifth FET device (Q5) during the open state. Thus, the fifth FET device (Q5) does not handle or handles only a small amount of the voltage load caused by the time-variant input signal42during the open state.

Note that while the second decoupling path124alone causes the time-variant input signal42to bypass the fifth FET device (Q5), providing both the first and second decoupling paths122,124, at the fifth FET device (Q5) may help reduce the effects of impact ionization in the internal drain-source junction of the fifth FET device (Q5) during the open state of the FET device stack112. In the illustrated embodiment ofFIG. 5, a control circuit130operates the FET device stack112in accordance with Table III above, which biases the drain contact, D of the fifth FET device (Q5) at the bias voltage +Vbiasduring the open state of the FET device stack112while the source contact, S, of the fifth FET device (Q5) is not biased due to the DC block of the second decoupling capacitor128. As a result, a voltage difference of around +Vbiasmay be seen across the internal drain-source junctions of the fifth FET device (Q5). In certain applications of the FET device stack112, the voltage difference may be close to the drain-source voltage at which impact ionization occurs. Also, this voltage difference in combination with large signal conditions may cause impact ionization around the peaks of the time-variant input signal42. In turn, the voltage difference may cause a leakage current to flow across the fifth FET device (Q5) which in turn may cause a drop in the bias voltage, +Vbias, as seen by the first through fourth FET devices (Q1-Q4). This impact ionization problem can be suppressed by providing both the first and second decoupling paths122,124at the first FET device (Q1) thereby reducing the voltage drop across the internal drain-source junction of the fifth FET device (Q5).

A control circuit130is operably associated with the gate contacts, G, of the FET devices110that switches the FET device stack112from and to the open state and closed state in accordance with Tables II and III above. In this embodiment, the control circuit130applies the bias voltage, Vstack, to the drain contact, D, of the fifth FET device (Q5) which, in turn, also biases the drain contacts, D, and the source contacts, S of the first through fourth FET devices (Q1-Q4).

To decouple the body contact, B, of the fifth FET device (Q5) inFIG. 5a third decoupling path132may be provided in the stacked FET switch108. In this embodiment, the third decoupling path132decouples the body contact, B, of the fifth FET device (Q5) by short-circuiting the body contact, B. In this manner, the time-variant input signal42is prevented from loading the body contact, B, of the fifth FET device (Q5).

Note that different combinations of the decoupling paths disclosed herein may be operably associated with either the first FET device (Q1) or the fifth FET device (Q5) so that the time-variant input signal42bypasses a desired part of a FET device stack in a stacked FET switch during the open state and/or to help reduce the effects of impact ionization. For example and referring again toFIG. 5, in other alternative embodiments, the FET device stack112may be connected to have the second decoupling path124and not the first decoupling path122so that the time-variant input signal42bypasses the FET device stack112from the drain contact, D, to the source contact, S, of the fifth FET device (Q5). This configuration may be advantageous if impact ionization is not a problem or is kept within acceptable tolerance limits. Also, other embodiments may instead connect the first decoupling path122and the second decoupling path124to the first FET device (Q1) so that the time-variant input signal42bypasses the FET device stack112from the drain contact, D, to the source contact, S, of the first FET device (Q1) rather than the fifth FET device (Q5). In this case, the first decoupling path122may be connected so that the FET device stack112is configured to bypass the FET device stack112from the drain contact, D, to the gate contact, G, of the first FET device (Q1) during the open state. The second decoupling path124is connected to the first FET device (Q1) so that the FET device stack112is configured to bypass the FET device stack112from the drain contact, D, to the source contact, S, of the first FET device (Q1). Furthermore, in this case, the first capacitor117may be provided to be connected in series between the source contact, S, of the fifth FET device (Q5) and the output terminal120. Also, the fifth FET device (Q5) could then be connected with a resistor, Rds, across the drain contact, D, and source contact, S and help handle the load of the time-variant input signal42during the open state. These and other combinations for connecting one or more decoupling paths to decouple a desired portion of an FET device stack during the open state are within the scope of this disclosure.

FIG. 6is still yet another embodiment of a stacked FET switch134. The stacked FET switch134is similar to the stacked FET switch108inFIG. 5. However, a resistive circuit136, has each resistors, Rg, coupled between the gate contact, G, of one of the FET devices110, and the gate contact, G, of another one of the FET devices110. Similarly, a resistive circuit138has resistors, Rb, coupled between the body contact, B, of one of the FET devices110, and the body contact, B, of another one of the FET devices110. The circuit topology for the stacked FET switch134may be desirable, if the stacked FET switch134is being utilized to shunt an RF line of an RF circuit. One benefit of the illustrated topology of resistive circuits136,138is that the open state loading of the resistors, Rg, and Rb, may be substantially reduced. As a result, the circuit topology of resistive circuits136,138allows resistors Rg, and Rbto be substantially reduced in size.

The embodiment illustrated inFIG. 6has a first decoupling path158and a second decoupling path160. The first decoupling path158is configured to bypass the time-variant input signal42from the gate contact, G, to the source contact, S of the fifth FET device (Q5). In this example, the first decoupling path158is connected directly between the gate contact, G, and the source contact, S of the fifth FET device (Q5). The second decoupling path160includes a decoupling capacitor that is configured to bypass the FET device stack112from the drain contact, D, to the source contact, S of the fifth FET device (Q5) and is connected from the drain contact, D, to the output terminal, which is at ground.

Referring now toFIG. 7, a stacked FET switch140may have any plurality of FET devices (referred to generically as elements142and to a specific FET device as elements Q1-QM) coupled in series to form an FET device stack144. M is the number of FET devices142and may be any integer greater than 1. The FET device stack144inFIG. 7is stacked from a first FET device (Q1) to a last FET device (QM) and middle FET device (Q2-QM-1) are connected in the FET device stack144between the first FET device (Q1) to a last FET device (QM). In the illustrated embodiment, the stacked FET switch140has an input terminal146connected to a signal line148that transmits the time-variant input signal42, which may be an RF signal. During the closed state, the FET device stack144shunts the signal line148and transmits the time-variant input signal42to the output terminal150, which are connected to a reference voltage for the FET device stack144, in this case ground. In the open state, the FET device stack144prevents the time-variant input signal42from being shunted to ground. A control circuit152provides a first voltage and second voltage, in accordance with Tables II and III, discussed above.

In this example, the last FET device (QM) has a first decoupling path76similar to the one illustrated inFIG. 3. The first decoupling path76has a first decoupling transistor78that is configured to bypass the time-variant input signal42from the gate contact, G, to the source contact, S of the last FET device (QM). The first decoupling path76is connected from the gate contact, G, of the last FET device (QM) directly to the output terminal150. When the FET device stack144is in the open state, the first decoupling transistor78is turned on so that the time-variant input signal42bypasses the gate to source of the last FET device (QM). A second decoupling path160similar to the one illustrated inFIG. 6is also provided. This second decoupling path160includes a decoupling capacitor that is configured to bypass the FET device stack144from the drain contact, D, to the source contact, S of the last FET device (QM) and is connected from the drain contact, D, of the last FET device (QM) to the output terminal150.

Referring now toFIGS. 7 and 8, one type of time-variant input signal42is illustrated. The time-variant input signal42shown inFIG. 8is a sinusoidal voltage having a maximum positive peak voltage, Vmaxp, and a minimum negative peak voltage Vmaxn, relative to a reference voltage,154, in this case ground. The time-variant input signal42is illustrated as a simplified sinusoidal voltage to help discuss the operation of the stacked FET switch140. Accordingly, the maximum positive peak voltage, Vmaxp, and the minimum negative peak voltage Vmaxnhave the same magnitude. Thus, the maximum peak voltage may be referred to as a maximum peak voltage, Vmax. However, the time-variant input signal42may be any type of signal, such as, for example an RF signal, in which the time-variant input signal42would be more or even less complex than the signal shown inFIG. 8, may actually consist of a plurality of combined signals, and may not be symmetrical. For example, the maximum positive peak voltage, Vmaxp, and the minimum negative peak voltage Vmaxnmay have a different magnitude in the positive and negative cycles. Some time-variant input signals42may not have either a positive or a negative cycle and thus may be unicyclical and others may actually not be periodic at all. These and other considerations should be taken into account when determining maximum peak voltage, Vmaxas would be apparent to one of ordinary skill in the art, in light of this disclosure.

The plurality of FET devices142inFIG. 7may each be associated with a reverse biased pinch-off voltage, (−Vp) and a breakdown voltage, −VBreak. The pinch-off voltage, (−Vp), of a depletion mode FET device142is the reverse bias voltage at the gate contact, G, relative to a voltage of the source contact, S, at which the FET device142is opened. If a reverse bias less than or equal to the pinch-off voltage, (−Vp), is applied between the gate contact, G, and the source contact, S, of the FET device142, a channel of the FET device142is pinched off and the FET device142is deactivated. If the FET devices have congruent drains and sources, the pinch-off voltage, (−Vp), is applicable to the activation voltage from the gate contact, G, to the source contact, S for the FET device142, as well. The breakdown voltage, −VBreak, is the negative voltage between the drain contact, D, and the gate contact, G at which the FET device142begins to conduct when in the open state. In other words, if a negative voltage equal to or greater than the breakdown voltage, −VBreak, is applied between the drain contact, D, and the gate contact, G, the FET device142breaks down and begins to conduct. InFIG. 7, the plurality of FET devices142all have essentially the same characteristics and thus are associated with the same pinch-off voltage, (−Vp), and breakdown voltages, −VBreak. However, as discussed above, in other embodiments, the characteristics of the FET devices142may be different and thus each may be associated with different pinch-off voltages and/or breakdown voltages.

Referring now toFIGS. 7 and 9,FIG. 9is a graph of a voltage signal156at the drain contacts, D of the first through to the second-to-last FET devices (Q1-QM-1) relative to their source contact, S, during the open state of the FET device stack144. Note that the last FET device (QM) has been decoupled during the open state. A first decoupling path158and a second decoupling path160are configured to pass the time-variant input signal42during the open state. The first decoupling path158is connected directly to ground so that the FET device stack144is configured to bypass the FET device stack144from the drain contact, D, of the last FET device (QM) to the gate contact, G, of the last FET device (QM). The second decoupling path160is also connected directly to ground so that the FET device stack144is configured to bypass the FET device stack144from the drain contact, D, of the last FET device (QM) to the source contact, S, of the last FET device (QM). Thus, the voltage of the time-variant input signal42is not dropped across the last FET device (QM).

As discussed above, different decoupling paths may be connected to the FET device stack144to bypass a desired portion of the FET device stack144during the open state. For example, in alternative embodiments, the first FET device (Q1) may be decoupled from the drain contact, D, to the gate contact, G, and/or from the drain contact, D, to the source contact, S, during the open state while the last FET device (QM) remains coupled and helps handle the voltage load of the time-variant input signal42. Alternatively, the FET device stack144may only be decoupled from the gate contact, G, to the source contact, S, of the last FET device (QM), similar to the embodiment explained above forFIG. 2. In this case, if the last FET device (QM) is only decoupled from the gate contact, G, to the source contact, S, and if we assume that the FET devices142have congruent drain and sources that have similar impedance characteristics, the voltage drop of the time-variant input signal42across the last FET device devices (QM) for the time-variant input signal42is about half of the voltage drop across each of the other FET devices (Q1-QM-1) during the open state.

In another alternative embodiment, the FET device stack144may only be decoupled from the drain contact, D, to the gate contact, G, of the first FET device (Q1) similar to the embodiment described inFIG. 4. In this case, if the first FET device (Q1) is only decoupled from the drain contact, D, to the gate contact, G, and if we assume that the FET devices142have congruent drains and sources, the voltage drop of the time-variant input signal42across the first FET device devices (Q1) for the time-variant input signal42is about half of the voltage drop across each of the other FET devices (Q2-QM). In the embodiment illustrated inFIG. 7, however, the last FET device (QM) is decoupled from the drain contact, D, to the source contact, S by the second decoupling path160and thus none or very little of the voltage of the time-variant input signal42is dropped across last FET device (QM).

The voltage drop of the time-variant input signal42may be distributed evenly across each of the drain to gate and gate to source junctions of the other FET devices (Q1-QM-1) during the open state. This helps to maximize the load handling capabilities of the FET device stack144assuming that the FET devices have congruent drains and sources that have similar impedance characteristics. Finally, in certain applications, the last FET device (QM) may be formed to be wider than the other FET devices (Q1-QM-1) to help suppress leakage currents caused by the voltage stress from the time-variant input signal42during the open state. Similarly, for embodiments as inFIG. 4in which the first FET device (Q1) has been decoupled, the first FET device (Q1) may be formed to be wider than the other FET devices (Q2-QM) to help suppress leakage currents.

Referring again toFIGS. 7 and 9, note that the voltage signal156inFIG. 9is measured relative to the source contact, S, of the FET devices (Q1-QM-1) and not to ground. The voltages signal for each of the drain contacts, D, of the FET devices (Q1-QM-1) relative to ground, is clearly different for each of the FET devices (Q1-QM-1). The FET devices (Q1-QM-1) positioned higher in the stack would have a drain voltage with greater positive and negative voltage peaks plus a bias voltage, +Vbiasrelative to ground during the open state of the FET device stack144. The drain voltage of the second-to-last FET device (QM-1) would be essentially the same as the time-variant input signal42(shown inFIG. 7) plus a biasing voltage, +Vbias, relative to ground during the open state. However, since the time-variant input signal42may be evenly distributed across each of the FET devices (Q1-QM-1), the drain voltages are relatively uniform relative to their source contact, S. Also, the biasing voltage, +Vbias, cancels out for voltage signal156since both of the drain contact, D, and the source contact, S, of the FET devices (Q1-QM-1) are biased by the biasing voltage, +Vbias, during the open state.

As illustrated, the voltage signal156has a maximum positive peak voltage, VFETmaxp, and the minimum negative peak voltage VFETmaxn. Since, in this case, the voltage signal is symmetrical, the magnitude of the maximum peak voltage, |VFETmax|, can be represented as:

The integer one (1) is subtracted from M because, as discussed above, in this embodiment, last FET device (QM) has been completely decoupled from the stack with respect to the time-variant input signal42during the open state. However, if in the alternative, the FET device stack144is only decoupled from the gate contact, G, to the source contact, S, of the last FET device (QM), and then the last FET device (QM) may contribute half of its load handling capabilities to the FET device stack144. Accordingly, in this case, the integer one (1) would be replaced by one-half

Referring now toFIG. 7andFIG. 10,FIG. 10illustrates a voltage signal162at the gate contact, G, of each of the FET devices (Q1-QM-1), relative to their source contact, S, during the open state of the FET device stack144. Note that the gate contact, G, of each of the middle FET devices (Q2-QM-1) appears negatively biased at, −Vbias, since the drain and source contacts, D, S, of each of the FET devices (Q1-QM-1) are positively biased by the first voltage, +Vbias. For each of the FET devices (Q1-QM-1) shown inFIG. 6, half of the voltage drop for the voltage signal156(shown inFIG. 9) occurs between the drain contact, D, and the gate contact, G, and the other half occurs between the gate contact, G, and the source contact, S. Consequently, the voltage signal162is centered at the negative bias, −Vbias, and has a maximum positive-cycle peak voltage,

-Vbias+VFETma⁢⁢x2,
and a maximum negative-cycle peak voltage,

-Vbias-VFETmax2
relative to the source contact, S. To maintain the FET devices (Q1-QM-1) in the open state, the voltage signal162must not be greater than the pinch-off voltage, (−Vp), during the positive cycle. The upper limit of the maximum peak voltage,

-Vbias+VFETmax2,
can thus be expressed as:

Since the voltage between the drain contacts, D, and the gate contacts, G, at the minimum peak voltage,

-Vbias-VFETmax2,
cannot exceed the negative breakdown voltage, −VBreak, the lower limit of the minimum peak voltage,

-Vbias-VFETmax2,
can be expressed as:

From these two equations, the highest allowable value of the maximum peak voltage, VFETmax, can be solved as
VFETmax=|VBreak|+(−Vp)

Also, from the two equations, we can also solve for the magnitude of the first voltage, Vbias, relative to ground which may be expressed as:

If the maximum peak voltage, Vmax, of the time-variant input signal42is reaches a maximum voltage, Vpk, then the number, M, of FET devices142needed to safely utilize the FET device stack144may be expressed as:

The number M of FET devices142thus may determine the maximum rated voltage that can be handled by the FET device stack144.

It should be noted that the equations shown above are estimations for the described values of the stacked FET switch140illustrated inFIG. 6. In actual practice, these values may vary from the aforementioned equations as a result of non-ideal behavior of the electronic components in the stacked FET switch140. In other embodiments, the relationships described by the aforementioned equations may be different depending on the particular circuit topology and electronic components utilized for the stacked FET switch140. For example, the aforementioned equations have been determined under the assumption that the FET devices142are depletion mode type FET devices142. However, enhancement mode type FET devices142may also be utilized in the stacked FET switch140. In addition, it was assumed that the FET devices142have congruent drains and sources and in the alternative, one or more of the FET devices142may not have congruent drains and sources. Also, as discussed above, alternative embodiments may not completely decouple the first FET device (Q1) and the last FET device (QM) and thus, for example, the first FET device (Q1) and the last FET device (QM) may contribute half of their load handling capabilities to the FET device stack144. One of ordinary skill in the art would be able to reformulate the relationships expressed by the aforementioned equations in accordance with non-ideal circuit behavior and the particular circuit topology and electronic components utilized to form the stacked FET switch140in light of this disclosure.