Display panel, gate driver and control method

A display panel, a gate driver and a control method are disclosed herein. The gate driver includes series-coupled driving stages. One of the driving stages includes an input unit and a shift register circuit. The input unit outputs a shift signal to a control node according to a gate driving signal from the previous driving stage and the gate driving signal from the next driving stage. The shift register circuit is electrically coupled to the control node, and outputs the gate driving signal. During the enabling period of the gate driving signal from the previous driving stage and the enabling period of the gate driving signal from the current driving stage, the shift register circuit keeps the voltage level of the control node being at a first voltage.

This application claims priority to Taiwan Application Serial Number, 103104128, filed Feb. 7, 2014, which is herein incorporated by reference.

BACKGROUND

Technical Field

The present disclosure relates to a display panel. More particularly, the present disclosure relates to a gate driver of a display panel.

Description of Related Art

Recently, liquid crystal displays (LCDs) have been widely applied in various kinds of products. To increase a visible area of LCD, new techniques about a slim border in the LCD keep coming out.

Reference is made toFIG. 1.FIG. 1is a schematic diagram of a conventional shift register circuit100which is a commonly used circuit of the shift register. As shown inFIG. 1, the shifter register circuit100is configured to receive a scan control signal CS to change the voltage level of a control node A, so as to generate a gate driving circuit SR_OUT.

Explained in a detailed way, when a previous stage of the shift register circuit100outputs the gate driving signal SR_OUT, the control node A in the current stage of the shift register circuit100is pulled up to a high level voltage by the scan control signal CS. When the current stage of the shift register circuit100outputs the gate driving signal SR_OUT, the control node A is floating. In this present time, the control node A may be charged only by a clock signal CLK/XLCLK through certain parasitic capacitances, and thus the current stage of the shift register circuit100can correctly output the gate driving signal SR_OUT.

However, if the threshold voltages of the switches N1-N3are reduced and the leakage current of the switches N1-N3are increased due to device aging and/or process variations, the voltage level of the control node A, which is floating, may be not correctly kept at the high level voltage. In other words, when the current stage of the shift register circuit100outputs the gate driving signal SR_OUT, the voltage level of the control node A may be changed to a voltage with a higher level by the clock signal CLK/XCLK. Alternatively, the voltage level of the control node A may be pulled down to the low level voltage when the leakage current is too large. As a result, the operations of the shift register circuit100are failure.

Therefore, a heretofore-unaddressed need exists to address the aforementioned deficiencies and inadequacies.

SUMMARY

An aspect of the present disclosure is to provide a display panel. The display panel includes gate lines and a gate driver. The gate driver includes series-connected driving stages. Each of the driving stages is configured to output a gate driving signal to the corresponding one of the gate lines, in which a N-th driving stage of the driving stages includes an input unit and a shift register circuit. The input unit is configured to output a shift signal to a control node according to the gate driving signal outputted from a (N−1)th driving stage and the gate driving signal outputted from a (N+1)th driving stage, in which N is a positive integer. The shift register circuit is electrically coupled to the control node, and configured to receive the shift signal to output the gate driving signal. The shift register circuit keeps the voltage level of the control node being at a first voltage during the enabling period of the gate driving signal outputted from the (N−1)th driving stage and the enabling period of the gate driving signal outputted from the N-th driving stage.

Another aspect of the present disclosure is to provide a gate driver. The gate driver includes series-connected driving stages. Each of the driving stage includes an input unit having an output terminal, and a shift register circuit. The shift register circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an output unit. A control terminal of the first switch is electrically coupled to the output terminal of the input unit, and a first terminal of the first switch is configured to receive a first voltage. A control terminal of the second switch is electrically coupled to the second terminal of the first switch, and a first terminal of the second switch is electrically coupled to the first terminal of the first switch. A control terminal of the third switch is electrically coupled to the output terminal of the input unit, a first terminal of the third switch is electrically coupled to the second terminal of the first switch, and a second terminal of the third switch is configured to receive a second voltage. A control terminal of the fourth switch is electrically coupled to the output terminal of the input unit, a first terminal of the fourth switch is electrically coupled to the second terminal of the second switch, and a second terminal of the fourth switch is configured to receive the second voltage. A control terminal of the fifth switch is electrically coupled to the second terminal of the first switch, a first terminal of the fifth switch is electrically coupled to the first terminal of the first switch, and a second terminal of the fifth switch is electrically coupled to the output terminal of the input unit. A control terminal of the sixth switch is electrically coupled to the second terminal of the second switch, a first terminal of the sixth switch is electrically coupled to the output terminal of the input unit, and a second terminal of the sixth switch is configured to receive the second voltage. A control terminal of the seventh switch is electrically coupled to the first terminal of the fourth switch, a first terminal of the seventh switch is configured to output a gate driving signal, and a second terminal of the seventh switch is configured to receive a power signal. An input terminal of the output unit is electrically coupled to the output terminal of the input unit, and an output terminal of the output unit is electrically coupled to the first terminal of the seventh switch.

Another aspect of the present disclosure is to provide a control method, which is suitable for a gate driver. The gate driver includes series-connected driving stages, and each of the driving stages includes an input unit and a shift register circuit, the input unit and the shift register circuit are electrically coupled to a control node, and the shift register circuit is configured to output a gate driving signal. The control method includes following steps: turning on the input unit to transmit a downshift signal to the control node by the gate driving signal outputted from a previous driving stage; turning on a first switch of the shift register circuit to transmit a first voltage to turn on a second switch by the downshift signal; pulling up the voltage level of the control node to a second voltage through the second switch during the enabling period of the gate driving signal outputted from the previous driving stage; and keeping the voltage level of the control node being at the second voltage through the second switch during the enabling period of the gate driving signal outputted from a current driving stage.

In summary, the display panel, the gate driver, and the control method of the present disclosure can make the nodes of the internal circuits of the gate driver keep at a specific voltage during the operations, and the failed operation caused by floating voltage is thus prevented.

DETAILED DESCRIPTION

In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

FIG. 2is a schematic diagram of a display panel according to one embodiment of the present disclosure. As shown inFIG. 2, the display panel200includes a video display area220, a source driver240and a gate driver260. The display area220includes a pixel array222, which is formed by data lines (e.g., N data lines DL1-DLN) and gate lines (e.g., M gate lines GL1-GLM) and pixels224that are disposed in the pixel array222.

The source driver240is coupled to the data lines DL1-DLN, and is configured to transmit data signals to the corresponding pixel224of the video display area220through the data lines DL1-DLN. The gate driver260is coupled to the gate lines GL1-GLM, and is configure to sequentially transmit gate-driving signals to the corresponding pixel224of the video display area220through the gate lines GL1-GLM.

FIG. 3is a schematic diagram illustrating the configuration of the video display area and the gate driver of a display panel according one embodiment of the present disclosure. The illustrated configuration can be applied to the display panel200shown inFIG. 2, but not limited thereto. As shown inFIG. 3, the gate driver260includes driving stages320. In this embodiment, the driving stages320are disposed at the left side of the video display area300. In another embodiment, the driving stages320are disposed at the right side of the video display area300. In this embodiment, the driving stages320sequentially output the gate driving signals from top to bottom to drive the gate lines GL1-GLM. In another embodiment, the driving stages320sequentially output the gate driving signals from bottom to top to drive the gate lines GL1-GLM.

FIG. 4is a schematic diagram illustrating the configuration of the video display area and the gate driver of a display panel according another one embodiment of the present disclosure. The illustrated configuration can be applied to the display panel200shown inFIG. 2, but not limited thereto. As shown inFIG. 4, the gate driver includes driving stages420, in which some of the driving stages420are disposed at the left side of the video display area400, and the rest of the driving stages420are disposed at the right side of the video display area400. Both sides of the driving stages420are configured to alternatively output the gate driving signals to drive the gate lines. This configuration is called as a dual-sided driving. In one embodiment, both sides of the driving stages420are configured to alternatively output the gate driving signals from top to bottom to drive the gate lines GL1-GLM. In another embodiment, both sides of the driving stages420are configured to alternatively output the gate driving signals from bottom to top to drive the gate lines GL1-GLM.

FIG. 5is a schematic diagram of the N-th driving stage of a gate driver according to one embodiment of the present disclosure. As shown inFIG. 5, the N-th driving stage500can be applied to one of the driving stages shown inFIG. 3orFIG. 4, but not limited thereto. The N-th driving stage500includes an input unit520and a shift register circuit540, in which N is a positive integer.

The input unit520is configured to output a shift signal SS to a control node N1(e.g., an output terminal of the input unit520), according to the gate driving signal SR[n−1] outputted from the (N−1)th driving stage500and the gate driving signal SR[n+1] outputted from the (N+1)th driving stage500.

The shift register circuit540is electrically coupled to the control node N1, and is configured to output the gate driving signal SR[n]. In this embodiment, the shift register circuit540can keep the voltage level of the control node N1being at the voltage VGH during the enabling period (e.g. time T1illustrated inFIG. 7) of the gate driving signal SR[n−1] outputted from the (N−1)th driving stage500, and the enabling period (e.g. time T2illustrated inFIG. 7) of the gate driving signal SR[n+1] outputted from the (N+1)th driving stage500. As a result, the driving stages500can correctly perform driving operations even the leakage currents of the driving stages500are increased by the device aging and/or process variations.

The following paragraphs provide certain embodiments related to the driving stage500to illustrate functions and applications thereof. However, the present disclosure is not limited to the following embodiments.

In one embodiment, as shown inFIG. 5, the shift register circuit540includes a control unit542, a reset switch MR, and an output unit544. The control unit542is configured to pull up the control node N1to the voltage VGH or pull down the control node N1to the voltage VGL according to the shift signal SS. The reset switch is electrically coupled to the control unit542. In a normal operation, the power signal XDONB is a low voltage level signal (e.g. the level of the voltage VGL). In a power-off state, the power signal XDONB switches to a high voltage level signal (e.g. the level of the voltage VGH), and the reset switch MR switches the gate driving signal SR[n] to the high voltage level signal according to the power signal XDONB, and the pixels224are thus reset.

In addition, the voltage VGH and the voltage VGL shown inFIG. 5are different, and the level of the voltage VGH is higher than the level of the voltage VGL. The clock signal CLK received by the (N−1)th driving stage500and the (N+1)th driving stage500, e.g., the clock signal CLK shown inFIG. 7later, and the clock signal XCLK received by the N-th driving stage500have opposite-phase.

Specifically, as shown inFIG. 5, a first terminal of the reset switch MR is configured to output the gate driving signal SR[n], a second terminal of the reset switch MR is configured to receive the power signal XDONB. The control unit542includes a switch M1, a switch M2, a switch M3, a switch M4, a switch M5, and a switch M6. A control terminal of the switch M1is electrically coupled to the control node N1, and a first terminal of the switch M1is configured to receive the voltage VGH. A control terminal of the switch M2is electrically coupled to a second terminal of the switch M1, a first terminal of the switch M2is electrically coupled to the first terminal of the switch M1, and a second terminal of the switch M2is electrically coupled to the control terminal of the reset switch MR. A control terminal of the switch M3is electrically coupled to the control node N1, a first terminal of the switch M3is electrically coupled to the second terminal of the switch M1, and a second terminal of the switch M3is configured to receive the voltage VGL. A control terminal of the switch M4is electrically coupled to the control node N1, a first terminal of the switch M4is electrically coupled to the second terminal of the switch M2, and a second terminal of the switch M4is configured to receive the voltage VGL. A control terminal of the switch M5is electrically coupled to the second terminal of the switch M1, a first terminal of the switch M5is electrically coupled to the first terminal of the switch M1, and a second terminal of the switch M5is electrically coupled to the control node N1. A control terminal of the switch M6is electrically coupled to the second terminal of the switch M2, a first terminal of the switch M6is electrically coupled to the control node N1, and a second terminal of the switch M6is configured to receive the voltage VGL.

Furthermore, the output unit544includes a switch M7and a switch M8. A control terminal (i.e., the input terminal of the output unit544) of the switch M7is electrically coupled to the control node N1, a first terminal of the switch M7is configured to receive the clock signal XCLK, and a second terminal (i.e., the output terminal of the output unit544) of the switch M7is electrically coupled to the first terminal of the reset switch MR. A control terminal of the switch M8is electrically coupled to the second terminal of the switch M1, a first terminal of the switch M8is configured to receive the clock signal XCLK, and a second terminal of the switch M6is electrically coupled to the first terminal of the reset switch MR.

In this embodiment, the input unit520includes a switch Q1and a switch Q2. A control terminal of the switch Q1is configured to receive the gate driving signal SR[n−1] outputted from the (N−1)th driving stage500, a first terminal of the switch Q1is configured to receive a downshift signal U2D, and a second terminal of the switch Q1is configured to output the shift signal SS to the control node N1. A control terminal of the switch Q2is configured to receive the gate driving signal SR[n+1] outputted from the (N+1)th driving stage500, a first terminal of the switch Q2is electrically coupled to the second terminal of the switch Q1, and a second terminal of the switch Q2is configured to receive a upshift signal D2U.

In practical applications, the operation of sequentially driving the gate lines from bottom to top illustrated inFIG. 3and the operation of sequentially driving the gate lines from top to bottom illustrated inFIG. 4can be performed by configuring the downshift signal U2D and the upshift signal D2U according to the requirements of the practical applications. In this embodiment, the downshift signal U2D is a high level voltage signal, and the upshift signal D2U is a low level voltage signal, but the present disclosure is not limited thereto. One of person having ordinary skill in the art can adjust the downshift signal U2D and the upshift signal D2U according to the circuit architecture.

FIG. 6is a flow chart of a control method600according to one embodiment of the present disclosure. The control method600can be applied to the gate driver260and the driving stages500thereof, but not limited thereto.FIG. 7is a timing diagram of the signals when the driving stage500operates the control method600according to one embodiment of the present disclosure.FIG. 8Ais a schematic diagram of the state of each switch of the driving stage inFIG. 5during time T1according to one embodiment of the present disclosure. For simplifying description, reference is made toFIG. 6,FIG. 7, andFIG. 8A, and the operations of the driving stages500are described with the control method600.

The control method600includes step S610, step S620, step S630, and step S640. In step610, the input unit520is turned on by the gate driving signal SR[n−1] outputted from the (N−1)th driving stage500, so as to transmit the downshift signal U2D to the control node N1.

In step S620, the switch M3of the shift register circuit540is turned by the downshift signal U2D, and the voltage VGL is thus transmitted to turn on the switch M5.

In step S630, during the enabling period T1of the gate driving signal SR[n−1] outputted from the (N−1)th driving stage500, the voltage level of the control node N1is pulled up to the voltage VGH through the switch M5.

In the step S640, during the enabling period T2of the gate driving signal SR[n] outputted from the N-th driving stage500, the voltage level of the control node N1is kept at the voltage VGH through the switch M5.

For illustration, as shown inFIG. 7andFIG. 8A, during time T1, the gate driving signal SR[n−1] outputted from (N−1)th driving stage is at the enabling period (i.e., the time of being at the high level voltage), and the gate driving signal SR[n+1] outputted from (N+1)th driving stage is at the disabling period (i.e., the time of being at the low level voltage). Therefore, the switch Q1of the input unit520is turned on, and the switch Q2of the input unit520is turned off, and the downshift signal U2D is outputted to the control node as the shift signal SS.

As mentioned above, as the downshift signal U2D is the high level voltage signal (not shown), the shift signal SS also is the high level voltage signal in this time. Therefore, the switch M1is turned off, and the switch M3, the switch M4, and the switch M7are turned on. The voltage VGL is transmitted to the control terminals of the switch M6and the reset switch MR through the switch M4, and the switch M6and the reset switch MR are thus turned off. The voltage VGL is also transmitted to the control terminals of the switch M5and the switch M8through the switch M3, and the switch M5and the switch M8are thus turned on. The gate driving signal SR[n] outputted from the N-th driving stage500follows the clock signal XCLK to be the low level voltage signal. Moreover, during time T1, the voltage level of the control node N1can be steadily pulled up to the voltage VGH through the switch M5.

FIG. 8Bis a schematic diagram of the state of each switch of the driving stage inFIG. 5during time T2according to one embodiment of the present disclosure.

During time T2, as shown inFIG. 7andFIG. 8B, the gate driving signal SR[n−1] outputted from (N−1)th driving stage switches to the disabling period (i.e., switches to the low level voltage signal), and the gate driving signal SR[n+1] outputted from (N+1)th driving stage still keeps at the disabling period. Therefore, the switch Q1and the switch Q2are turned off. As the voltage level of the control node N1is already pulled up to the voltage VGH during time T1, the switch M3, the switch M4, and the switch M7are kept being turned on. Thus, the voltage VGL keeps turning on the switch M5through the switch M3, and keeps turning off the switch M6and the reset switch MR through the switch M4. Accordingly, during time T2, the voltage level of the control node N1can be kept the voltage VGH through the switch M5. Further, as the output unit544is turned on, the gate driving signal SR[n] outputted from the N-th driving stage500follows the clock signal XCLK to switch to the high level voltage signal.

FIG. 8Cis a schematic diagram of the state of each switch of the driving stage inFIG. 5during time T3according to one embodiment of the present disclosure.

During time T3, as shown inFIG. 7andFIG. 8C, the gate driving signal SR[n−1] outputted from (N−1)th driving stage switches to the low level voltage signal, and the gate driving signal SR[n+1] outputted from (N+1)th driving stage enters the enabling period (i.e., switches to the high voltage level signal). Meantime, the switch Q1of the N-th driving stage500is turned off, the switch Q2of the N-th driving stage500is turned on, and the upshift signal is outputted to the control node N1as the shift signal SS.

As mentioned above, as the upshift signal D2U is the low level voltage signal, the shift signal SS also is the low level voltage signal by this time. Therefore, the switch M3and the switch M4are turned off, and the switch M1is turned on. The voltage VGH is transmitted to the control terminal of the switch M2through the switch M2, and thus the switch M2is turned on. The voltage VGH is further transmitted to the control terminals of the switch M6and the reset switch MR, and thus the switch M6and the reset switch MR are turned on. During time T3, the voltage level of the control node N1is steadily pulled down to the voltage VGL through the switch M6, and the switch M7and the switch M8are thus turned off. As mentioned above, in the normal operation, the power signal XDONB is the low level voltage signal. Therefore, during time T3, the gate driving signal SR[n] outputted from the N-th driving stage500follows the power signal XDONB to be the low level voltage signal.

As described above, during the enabling period of the gate driving signal SR[n−1] outputted from (N−1)th driving stage and the enabling period of the gate driving signal SR[n] outputted from N-th driving stage (i.e., time T1and time T2shown inFIG. 7), the voltage level of the control node N1can be kept at the voltage VGH. During the enabling period of the gate driving signal SR[n+1] outputted from (N+1)th driving stage (i.e., time T3shown inFIG. 7), the voltage level of the control node N1can be switched and be kept at the voltage VGL. In other words, during the operating process, the voltage level of the control node N1of the N-th driving stage500can be switched to and kept at a specific voltage, e.g., the voltage VGH or the voltage VGL, and thus the floating of the internal nodes of the circuit is prevented from impacts caused by process variations, aging, leakage current, or parasitic capacitances.

FIG. 9is a schematic diagram of a driving stage900according to one embodiment of the present disclosure. Compared with the driving stage500shown inFIG. 5, the driving stage900further includes a buffer920. The buffer920is configured to generate an output signal SR_out[n] having a better driving ability to the corresponding gate line according to the gate driving signal SR[n]. The buffer920can be arranged in the aforementioned driving stage500as well.

Compared with the driving stage500shown inFIG. 5, the input unit520of the driving stage900further includes a switch Q3and a switch Q4. The switch Q3is electrically coupled to the switch Q1in parallel, and is configured to be selectively turned on according to a control signal SR/[n−1]. The switch Q4is electrically coupled to the switch Q2in parallel, and is configured to be selectively turned on according to a control signal SR/[n+1]. The control signal SR/[n−1] and the control signal SR/[n+1] can be generated from the buffer920(i.e., control signal SR/[n] shown inFIG. 9), in which the control signal SR/[n−1] and the gate driving signal SR[n−1] outputted from the (N−1)th driving stage900have opposite-phase, and the control signal SR/[n+1] and the gate driving signal SR[n+1] outputted from the (N+)th driving stage900have opposite-phase. The switch Q1and the switch Q3form a complementary switching unit, and the switch Q2and the switch Q3form another one complementary switching unit. The operations of the driving stage900are similar with the operations of the driving stage500, and the repetitious descriptions are not given here.

In various embodiments of the present disclosure, each switch can be any type of transistors, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a bottom-gate transistor, a top-gate transistor, a thin film transistor, etc. The types of transistor are for illustrative purposes, and the present disclosure is not limited thereto.

Table 1 shows the simulated results of the power consumption and the threshold voltage of the conventional shift register circuit100. In the table 1, Vtn indicates the threshold voltage of N type transistors in the conventional shift register circuit100, Vtp indicates the threshold voltage of N type transistors in the conventional shift register circuit100, and PW indicates the total power consumption of the conventional shift register circuit100. in which the unit of the power consumption is milliwatts (mW).

Table 2 shows the simulated results of the power consumption and the threshold voltage of the driving stage500inFIG. 5. In the table 2, Vtn indicates the threshold voltage of N type transistors in the driving stage500, Vtp indicates the threshold voltage of N type transistors in the driving stage500, and PW indicates the total power consumption of the driving stage500, in which the unit of the power consumption is milliwatts (mW).

According to the table 1 and the table 2, compared with the conventional shift register circuit100, the power consumption of the driving stage500of the present disclosure and the power consumption of the conventional shift register circuit100are about the same when the threshold voltage is slightly varied. When the threshold voltage is significantly varied, e.g., Vtn is −1V and Vtp is 1V, the power consumption of the driving stage500is about 6.83 mW, and the power consumption of the conventional shift register circuit100is about 11.47 mW. In other words, compared with the conventional shift register circuit100, the driving stage500can have more stable and much lower power consumption when the switches are varied.

In summary, the display panel, the gate driver, and the control method of the present disclosure can make the nodes of the internal circuits of the gate driver keep at a specific voltage during the entire operations, and the failed operations caused by floating voltage are thus prevented.