Chip-scale monolithic load switch for portable applications

A chip-scale package houses a monolithic semiconductor die containing first and second lateral metal oxide semiconductor field effect transistors (MOSFETs) formed on a surface of the semiconductor die. The MOSFETs are formed using a lateral double diffused metal oxide semiconductor structure. The first MOSFET has a first conduction terminal coupled to a first package terminal and a second conduction terminal coupled to a second package terminal. The second MOSFET has a first conduction terminal coupled to a control terminal of the first MOSFET, a second conduction terminal coupled to a third package terminal, and a control terminal coupled to a fourth package terminal. A resistor is coupled between the first package terminal and the control terminal of the first MOSFET. A logic level enable signal controls the first MOSFET to enable the second MOSFET to connect a DC voltage from the first package terminal to the second package terminal.

FIELD OF THE INVENTION

The present invention relates in general to electronic circuits and semiconductor devices and, more particularly, to an integrated or monolithic load switching circuit for portable applications.

BACKGROUND OF THE INVENTION

Portable electronic devices, such as cellular phones, two-way pagers, laptop computers, personal digital assistants (PDAs), and music players, are popular and have many uses with consumers and businesses alike. Most portable electronic devices are designed to be small, compact, battery powered, and yet still provide a host of features and conveniences. The typical portable electronic device contains components, such as integrated circuits, discrete semiconductor devices, passive devices, piezoelectric devices, liquid crystal display (LCD), and mechanical devices, encased within a plastic or metal housing.

Many of the components in the portable electronic device require a direct current (DC) operating potential to function. Some components are continuously connected to the DC power supply voltage. Other components, such as the LCD and piezoelectric devices, receive the DC power supply voltage only when activated. For such components, a load switching circuit is used to connect the DC power supply to the load component to activate the device. The load switching circuit receives an enable signal which couples the DC operating potential through the load switch to the load component to allow it to function.

The load switching circuit is typically implemented with discrete transistors and discrete passive devices. The default state of the load switching circuit is to disconnect the DC power supply from the load component. A discrete pass transistor is rendered conductive in response to the enable signal to couple the DC operating potential to the load component.

Component size and level of integration are important factors in the design of the portable electronic devices. The space available on the printed circuit boards of portable electronic devices is usually a premium design consideration. The designers and manufacturers of portable electronic devices continuously demand faster speed, more functionality, less power consumption, smaller size, and higher integration when selecting electronic component parts for their systems. The discrete components used to implement the load switching circuit consumes more area of the printed circuit board than many portable electronic device manufacturers may prefer.

A need exists for semiconductor devices and packages which consume less area in portable electronic devices having limited board space.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a chip-scale package housing a monolithic semiconductor die and having first, second, third, and fourth package terminals. The monolithic semiconductor die consists essentially of a first lateral metal oxide semiconductor field effect transistor (MOSFET) formed on a surface of the semiconductor die. The first lateral MOSFET has a first conduction terminal coupled to the first package terminal and a second conduction terminal coupled to the second package terminal. A second lateral MOSFET is formed on the surface of the semiconductor die. The second lateral MOSFET has a first conduction terminal coupled to a control terminal of the first lateral MOSFET, a second conduction terminal coupled to the third package terminal, and a control terminal coupled to the fourth package terminal. A resistor is coupled between the first package terminal and the control terminal of the first lateral MOSFET.

In another embodiment, the present invention is a monolithic semiconductor die housed within semiconductor package, comprising a first lateral metal oxide semiconductor field effect transistor (MOSFET) formed on a surface of the semiconductor die. The first lateral MOSFET has a first conduction terminal coupled to a first package terminal and a second conduction terminal coupled to a second package terminal. A second lateral MOSFET is formed on the surface of the semiconductor die. The second lateral MOSFET has a first conduction terminal coupled to a control terminal of the first lateral MOSFET, a second conduction terminal coupled to a third package terminal, and a control terminal coupled to a fourth package terminal.

In another embodiment, the present invention is a cellular telephone, comprising a first semiconductor die for providing communication signal processing and a second semiconductor die for performing load switching to the first semiconductor die. The second semiconductor die is housed in a chip-scale package and includes a first lateral metal oxide semiconductor field effect transistor (MOSFET) formed on a surface of the semiconductor die. The first lateral MOSFET has a first conduction terminal coupled to a first package terminal and a second conduction terminal coupled to a second package terminal. A second lateral MOSFET is formed on the surface of the semiconductor die. The second lateral MOSFET has a first conduction terminal coupled to a control terminal of the first lateral MOSFET, a second conduction terminal coupled to a third package terminal, and a control terminal coupled to a fourth package terminal.

In another embodiment, the present invention is a method of making a monolithic semiconductor die housed within a semiconductor package, comprising the steps of forming a first lateral metal oxide semiconductor field effect transistor (MOSFET) on a surface of the semiconductor die, the first lateral MOSFET having a first conduction terminal coupled to a first package terminal and a second conduction terminal coupled to a second package terminal, and forming a second lateral MOSFET on the surface of the semiconductor die, the second lateral MOSFET having a first conduction terminal coupled to a control terminal of the first lateral MOSFET, a second conduction terminal coupled to a third package terminal, and a control terminal coupled to a fourth package terminal.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring toFIG. 1, a cellular phone10is shown having a front body12housing keyboard14and liquid crystal display (LCD)16. Cell phone10further includes a rear body20housing PCB22. PCB22is separated into radio frequency (RF) signal processing section24and baseband signal processing section26, separated by shielding. The RF signal processing section24includes electronic components such as RF amplifier stage, modulator, demodulator, oscillator, and power management. The RF signal processing section receives RF signals, downconverts, and demodulates the signals to baseband signals. The baseband signal processing section24includes electronic components and devices such as microprocessor, analog to digital converter, digital to analog converter, memory, control logic, and analog amplifier. The baseband signal processing section24further includes electro-mechanical devices such as LCD, piezoelectric vibrator, microphone, and speaker. The baseband signal processing section26processes the baseband information so the user can speak and hear over the cell phone.

Most if not all of the electrical components and devices on PCB22require a direct current (DC) operating potential to function. Cell phone10has one lithium-ion battery source, e.g. 3.6 volts DC, attached to rear body20. Many of the electronic devices are hard-wired or continuously connected to the requisite DC operating voltage. Other electrical components, such as LCD backlight, piezoelectric vibrator, microphone, speaker, and certain amplifier stages, are connected to the DC power supply only when activated. In such cases, a load switching circuit is used to activate the electrical components or devices which are needed at the time by connecting each to the DC power supply. By the same token, the load switching circuit is used to de-activate the electrical components or devices which are not being used by disconnecting each from the requisite DC power supply.

For example, the piezoelectric vibrator may be activated by a load switching circuit connecting the DC power supply to the vibrator. The piezoelectric vibrator is deactivated by the load switching circuit blocking the DC power supply to the vibrator. Likewise, the microphone and speaker may be enabled for operation by a load switching circuit. The load switching circuit routes the DC operating voltage to the component and enables its electrical/mechanical operation, or blocks the DC operating voltage from reaching the component to disable its operation. The backlight of LCD16is illuminated by connecting it to the DC power supply through a load switching circuit, and turned off by causing the load switching circuit to electrically disconnect the DC power supply. When using a multi-band cell phone, the amplifier stages in the selected band are enabled by a load switching circuit connecting the selected amplifier stages to the DC power supply, while other amplifier stages supporting the non-selected bands are not needed and are disconnected from the DC power supply by load switching circuits. In battery driven applications, the load switching circuit conserves power by supplying the DC operating voltage to the electronic device only when needed and isolates the electronic device from its operating voltage when not in use.

One embodiment of the load switching circuit is shown inFIG. 2. Load switching circuit30receives DC voltage VINon terminal32. A p-channel transistor34has a source coupled to terminal32and a drain coupled to terminal36. P-channel transistor34is a 12-20 volt lateral metal oxide semiconductor field effect transistor (MOSFET) having a drain-source on resistance RDSonof 0.1 ohms with gate voltage of 2.5 volts. The gate of transistor34is coupled to the drain of n-channel transistor40. N-channel transistor40is a 12-20 volt MOSFET having a much higher RDSonthan transistor34. The gate of transistor40receives an enable control signal on terminal42. The enable signal is a logic level control signal. The source of transistor40is coupled to terminal44, which is a ground terminal. Resistor46is coupled between terminal32and the gate of transistor34. Resistor46is selected to have a typical value of several to several hundreds Kohms.

Assume a DC operating voltage VIN, say 3.6 VDC, is applied to terminal32. When the enable signal is a high voltage or logic one, transistor40is operating in a conductive state. Transistor40conducts current through resistor46and pulls the gate voltage of transistor34to a low value. The conduction path through transistor34is enabled to pass the operating voltage VIN, less the drain-source voltage drop across transistor34, to terminal36as output voltage VOUT. Load50is connected to terminal36and activates upon receiving the output voltage VOUT. Load50represents electrical components and devices on PCB22which are activated by load switching circuit30. For example, load50may be the piezoelectric vibrator which buzzes to notify the user of an incoming call or message or to signal an alarm. Load50may also be a speaker, microphone, LCD backlight, amplifier, or other active semiconductor device in cell phone10. The high voltage level of VOUTenables the operation of load50. Transistor34is a power MOSFET having sufficient current carrying capacity to supply the power requirements of load50.

When the enable signal is a low voltage or logic zero, transistor40rendered non-conductive. Resistor46operates as a pull-up resistor to apply the high DC voltage from terminal32to the gate of p-channel transistor34. Transistor34turns off and blocks the operating voltage VINfrom terminal36. The low voltage level of VOUTdisables the operation of load50. Accordingly, load switching circuit30enables or disables the operation of load50based on the logic level of the enable signal. Transistor40operating in response to the logic state of the enable signal represents a logic level control circuit to the power transistor34. By disconnecting load50from its DC power supply, the system consumes less power which is desirable in battery driven applications.

The space limitations of PCB22in cell phone10dictate that the use of discrete components should be minimized and eliminated where possible. The semiconductor die or device within each discrete component is small compared to its overall package size. The same issue exists with other portable electronic systems having space limitations, such as radios, two-way pagers, digital recorders, laptop computers, personal digital assistants (PDAs), compact disk players, compact video players, and the like. To support this design preference, in the following description, load switching circuit30is integrated into a single monolithic chip-scale package. The advantage of integrating the load switching circuit30is magnified by the multiple instances of the load switch typically found on PCB22. Load switching circuits like30may be used in several places on PCB22, e.g., to switch on and off each of the LCD backlight, piezoelectric vibrator, speakers, microphone, power amplifier stages, etc.

In addition, other electronic systems that do not necessarily have space limitations or portable applications, e.g. personal computers, energy systems, telecommunication systems, audio-video equipment, consumer electronics, and automotive components, can benefit from the cost savings and design efficiencies associated with the integration of discrete components.

In the present embodiment, the electrical components of load switching circuit30are integrated into a single monolithic package60having a 1.15×1.15 square millimeter (mm2) footprint. The height of package60is 0.8 mm to accommodate the low profile requirement. The power P-MOS transistor34occupies about 99% of the die area (1.3 mm2), while the N-MOS transistor40occupies about 1% of the die area (0.13 mm2).

As shown inFIG. 3, semiconductor package60is a four-terminal chip-scale or ball grid array package housing a monolithic semiconductor die which contains load switching circuit30. Bumps62-68are formed on the chip-scale package. Bump62is electrically coupled to the source of transistor34; bump64is electrically coupled to drain of transistor34; bump66is electrically coupled to the source of transistor40; bump68is electrically coupled to the gate of transistor40. Alternatively, in an IC package with external pins, e.g., SOP or DIP, the external connections from the semiconductor die to the package terminals can be made by wire bonds.

Semiconductor package60occupies significantly less space than conventional discrete components providing the same function. In fact, semiconductor package60uses 68% less space on PCB22as compared to a conventional discrete power p-channel MOSFET alone. The difference is more pronounced when taking into account a discrete n-channel transistor and pull-up resistor and interconnecting PCB tracks. The small footprint and low profile of semiconductor package60is applicable to portable electronic devices requiring efficient and compact components, such as load switching circuits used in cellular phones. The load switching circuit30contained within semiconductor package60provides a convenient and space efficient level shifting control function in response to a logic level control signal, as an integrated chip-scale solution, for connecting and disconnecting the DC power supply to electrical and electro-mechanical devices in portable electronic applications.

Further detail of the monolithic semiconductor device78is shown inFIG. 4including the transistors34and40portion of load switching circuit30. The device components are not necessarily drawn to scale. The semiconductor device uses lateral MOSFET structures for the P-MOS power device and N-MOS transistor. The lateral transistors are formed on the surface of semiconductor device78. Alternately transistor34and/or40can use a lateral double diffused MOS structure.

In the cross-sectional view, substrate80is made of N-type semiconductor material and provides structural support. The following regions and layers are formed on substrate80using semiconductor manufacturing processes understood by those skilled in the art. The manufacturing process includes layering, patterning, doping, and heat treatment. In the layering process, materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Patterning involves use of photolithography to mask areas of the surface and etch away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.

Using the above semiconductor manufacturing processes, N+ body region82and P+ source region84are formed along the surface of substrate80. Metal layer86is formed over P+ source region84to provide the source terminal of P-MOS transistor34. Metal layer86electrically connects to bump62. P− well region88is formed along the surface of substrate80. P+ drain region90is formed along the surface of P− well region88. Metal layer92is formed over P+ drain region90to provide the drain terminal of P− MOS transistor34. Metal layer92electrically connects to bump64. Oxide layer96is formed over P+ source region84, N-substrate80, and P− well region88. Gate region98is formed over oxide layer96. Metal layer99is formed over gate region98to provide the gate terminal of P-MOS transistor34. P-MOS transistor34is the power device used to source operating current to load50and is given a larger proportion of the die area of semiconductor device78as compared to N-MOS transistor40.

Using the above semiconductor manufacturing processes, P− well region100and P− well region102are formed along the surface of substrate80. P+ body region104and N+ source region106are formed along the surface of P− well region100. Metal layer108is formed over N+ source region106to provide the source terminal of N-MOS transistor40. Metal layer108electrically connects to bump66. N− drift region110and N+ drain region112are formed along the surface of P− well region102. Metal layer114is formed over N+ drain region112to provide the drain terminal of N− MOS transistor40. Oxide layer116is formed over N+ source region106, P− wells100-102, and N− drift region110. Gate region118is formed over oxide layer116. Metal layer119is formed over gate region118to provide the gate terminal of N-MOS transistor40. Metal layer119electrically connects to bump68. Metal layer114electrically connects to metal layer99. P− well region100and P− well region102merge together under oxide layer116and gate region118. For other connections not shown, terminal92would be connected to terminal119and resistor46would be coupled between terminal92and terminal108.

Another embodiment of the transistors34and40portion of load switching circuit30is shown in the cross-sectional view ofFIG. 5. The device components are not necessarily drawn to scale. Using the above semiconductor manufacturing processes, N− well region120is formed along the surface of P− substrate122. N+ body region124and P+ source region126are formed along the surface of N− well region120. Metal layer128is formed over P+ source region126to provide the source terminal of P-MOS transistor34. Metal layer128electrically connects to bump62. P− drift region130and P+ drain region132are formed along the surface of N− well region120. Metal layer134is connected to P+ drain region132to provide the drain terminal of P-MOS transistor34. Metal layer134electrically connects to bump64. Oxide layer136is formed over P+ source region126, N− well region120, and P− drift region130. Gate region138is formed over oxide layer136. Metal layer129is formed over gate region128to provide the gate terminal of P-MOS transistor34. Again, P-MOS transistor34is the power device used to source operating current to load50and is given a larger portion of the die area as compared to N-MOS transistor40.

Using the above semiconductor manufacturing processes, P+ body region140and N+ source region142are formed along the surface of P− substrate122. Metal layer144is formed over N+ source region142to provide the source terminal of N-MOS transistor40. Metal layer144electrically connects to bump66. N− drift region146and N+ drain region148are formed along the surface of P− substrate122. Metal layer150is formed over N+ drain region148to provide the drain terminal of N-MOS transistor40. Oxide layer152is formed over N+ source region142, P− substrate122, and N− drift region146. Gate region154is formed over oxide layer152. Metal layer156is formed over gate region154to provide the gate terminal of N-MOS transistor40. Metal layer156electrically connects to bump68. Metal layer150electrically connects to metal layer129. For other connections not shown, terminal134would be connected to terminal156and resistor46would be coupled between terminal134and terminal144.

One advantage of integrating load switching circuit in the chip-scale package is that the monolithic device occupies significantly less space than conventional discrete components providing the same function. The lateral device layout keeps the construction of the semiconductor die relatively thin, using a small number of mask layers, and permits ready connection from the key circuit nodes to the ball grid array bumps. The small footprint and low profile of the semiconductor package is particularly applicable to portable electric devices requiring efficient and compact components. The load switching circuit contained within the semiconductor package provides a convenient and space efficient level shifting control function in response to a logic level control signal for connecting and disconnecting the DC power supply to electrical and electro-mechanical devices in portable electronic applications.