Thin film transistor array substrate having improved electrical characteristics and method of manufacturing the same

A thin film transistor array substrate, which can have high mobility of charge and can achieve uniform electrical characteristics for wide display devices, and a method of manufacturing the thin film transistor array substrate, are provided. The thin film transistor array substrate includes an oxide semiconductor layer having a channel and formed on an insulating substrate, a gate electrode overlapping the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the gate electrode, and a passivation film formed on the oxide semiconductor layer and the gate electrode. At least one of the gate insulating film and the passivation film contains fluorine-containing silicon.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2008-0005833 filed on Jan. 18, 2008 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor array substrate and a method of manufacturing the same, and more particularly relates to a thin film transistor array substrate that improves electrical characteristics of an oxide semiconductor layer and a method of manufacturing the same.

2. Description of the Related Art

A liquid crystal display device, one of the most widely used types of flat panel displays in recent years, typically includes two substrates with electrodes, and a liquid crystal layer between the substrates. The substrates adjust the amount of light passing through the liquid crystal layer by re-arranging liquid crystal molecules in the liquid crystal layer using a voltage applied to the electrodes.

In many contemporary liquid crystal display devices, an electric field generating electrode is provided to first and second substrates, respectively. In this configuration, a plurality of pixel electrodes are arranged in a matrix form on the first substrate (i.e., a thin film transistor array substrate), and one common electrode covers the entire surface of the second substrate.

In this liquid crystal display device, images are displayed by applying an individual voltage to each pixel electrode. To accomplish this, a thin film transistor, a three-terminal element switching the voltages that are applied to the pixel electrodes, is connected with the pixel electrodes. Also connected to the pixel electrodes are a plurality of wires including gate lines that transmit signals for controlling the thin film transistor, and data lines that transmit voltages for the pixel electrodes. These devices are all formed on the substrate.

This switching element can be divided into an amorphous silicon thin film transistor and a polycrystalline silicon thin film transistor, depending on the materials that form the channel region. As for the amorphous silicon thin film transistor, the mobility of charge is low at about 0.5 cm2/Vs, but it can achieve uniform electrical characteristics for wide display devices. Further, as for the polycrystalline silicon thin film transistor, the mobility of charge is high at about a few hundred cm2/Vs, but it is difficult to achieve uniform electrical characteristics for wide display devices.

SUMMARY OF THE INVENTION

An object of the invention is to provide a thin film transistor array substrate that has high mobility of charge and can achieve uniform electrical characteristics for wide display devices.

Another object of the invention is to provide a method of manufacturing the thin film transistor array substrate.

However, the aspects, features and advantages of the present invention are not restricted to the ones set forth herein. The above and other aspects, features, objects, and advantages of the present invention will become more apparent to one of ordinary skill in the art to which the present invention pertains by referencing a detailed description of the present invention given below.

According to an exemplary embodiment of the present invention, a thin film transistor array substrate includes an oxide semiconductor layer, a gate electrode overlapping the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the gate electrode, and a passivation film formed on the oxide semiconductor layer and the gate electrode. At least one of the gate insulating film and the passivation film contains fluorine-containing silicon.

According to another exemplary embodiment of the present invention, a method of manufacturing a thin film transistor array substrate includes forming a thin film transistor structure having an oxide semiconductor layer, a gate electrode overlapping the oxide semiconductor layer, and a gate insulating film therebetween, and forming a passivation film on the oxide semiconductor layer and the gate electrode. At least one of the gate insulating film and the passivation film contains fluorine-containing silicon.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views of the invention. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the embodiments of the invention are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Additionally, regions exemplified in figures have schematic properties and shapes of regions shown in figures exemplify specific shapes of regions of elements and not limiting aspects of the invention.

A thin film transistor array substrate according to a first embodiment of the invention is described in detail hereafter with reference toFIGS. 1A and 1B.FIG. 1Ais a layout of a thin film transistor array substrate according to a first embodiment of the invention andFIG. 1Bis a cross-sectional view of the thin film transistor array substrate ofFIG. 1A, taken along the line A-A′.

Referring toFIGS. 1A and 1B, a gate wiring22,26that transmits gate signals is formed on an insulating substrate10. The gate wiring22,26includes a gate line22that transversely extends, and a gate electrode26of a thin film transistor that is a protrusion connected with the gate line22.

Further, a storage wiring27,28that transmits a storage voltage is formed on the insulating substrate10. The storage wiring27,28includes a storage line28that is substantially parallel with the gate line22across a pixel region, and a storage electrode27that has a width larger than the storage line28and that is connected to the storage line28. The storage electrode27forms a storage capacitor that improves performance of charge preservation of the pixel, overlapping a drain electrode extender67connected with a pixel electrode28(described below). The shape and arrangement of the storage electrode27and the storage line28may be modified into various types, and when storage capacitance that is generated by the overlap of the pixel electrode82and the gate line22is sufficient, the storage electrode27and the storage line28may not be provided.

The gate wiring22,26and the storage wiring27,28may be formed of an aluminum-based metal, such as aluminum (Al) or an aluminum alloy, a silver-based metal, such as silver (Ag) or a silver alloy, a copper-based metal, such as copper (Cu) or a copper alloy, a molybdenum-based metal, such as molybdenum (Mo) or a molybdenum alloy, chrome (Cr), Titanium (Ti), or tantalum (Ta). Further, the gate wiring22,26and the storage wiring27,28may each have a multi-film structure including two conductive films with different physical properties (not shown). One of the two conductive films can be formed of a low-resistivity metal, such as an aluminum-based metal, silver-based metal, or copper-based metal, to decrease signal delay or voltage drop of the gate wiring22,26and the storage wiring27,28. On the other hand, the other conductive film can be formed of another material, particularly a material that has good adhesiveness to ZnO (Zinc Oxide), ITO (Indium Tin Oxide), or IZO (Indium Zinc Oxide), such as a molybdenum-based metal, chrome, titanium, and tantalum. A lower chrome film with an upper aluminum film and a lower aluminum film with an upper molybdenum film may be good examples of the multi-film structure. However, the present invention is not limited to this configuration, and the gate wiring22,26and the storage wiring27,28may be formed of a variety of metals and conductive materials.

A gate insulating film30is formed on the gate wiring22,26and the insulating substrate10. The gate insulating film30may be formed of fluorine-containing silicon. The fluorine-containing silicon may be fluorine-containing silicon nitride, fluorine-containing silicon oxide, or fluorine-containing silicon oxynitride, such as SiOF, SiNF, SiONF, or SiOCF. When the gate insulating film30is formed of fluorine-containing silicon, a low level of hydrogen is contained the gate insulating film30, such that it is possible to prevent deterioration of the electrical characteristics of an oxide semiconductor layer40.

The oxide semiconductor layer40, which can be an oxide of a material selected from Zn, In, Ga, Sn, and their combination, is formed on the gate insulating film30. For example, for the oxide semiconductor layer40, a mixed oxide, such as ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, or GalnZnO, may be used. The oxide semiconductor layer40can be two to one hundred times larger in the effective mobility of charge than hydrogenated amorphous silicon and have a 105to 108on/off current ratio, such that its semiconductor characteristics are good. Further, for the oxide semiconductor layer40, the band gap is about 3.0 to 3.5 eV, such that photocurrent does not leak with respect to visible light. Therefore, it is possible to prevent a second afterimage of an oxide thin film transistor and increase the aperture ratio of the liquid crystal display device as well, because no light shielding film need be provided under the oxide thin film transistor. The group 3, 4, 5 elements or transition elements in the periodic table may be additionally included to improve the characteristics of the oxide semiconductor. Further, the materials for the oxide semiconductor layer40have good ohmic contact characteristics to data wiring62,65,66,67(described below), such that an ohmic contact layer is not needed and it is possible to reduce the process time. Further, the oxide semiconductor layer40is in amorphous state, but has high effective mobility of charge, and it is possible to apply the manufacturing process for amorphous silicon to the oxide semiconductor layer. Therefore, the oxide semiconductor layer may be applied to wide display devices.

For the oxide thin film transistor of this embodiment, the oxide semiconductor layer40and the data wiring62,65,66,67are different in pattern. However, when a four-sheet mask process is applied, the oxide semiconductor layer40may be patterned substantially the same as the data wiring62,65,66,67, except for the channel region of the oxide thin film transistor, because the oxide semiconductor layer40and the data wiring62,65,66,67are patterned by one etching mask. Although a structure formed by a five-sheet mask process is exemplified in this embodiment, it is apparent to the person skilled in the art that other processes, such as three-sheet or four-sheet mask processes, may be used without departing from the primary aspects of the present invention.

The data wiring62,65,66,67is formed on the oxide semiconductor layer40and the gate insulating film30. The data wiring62,65,66,67includes a data line62that is longitudinally formed across the gate line22and defines a pixel, and a source electrode65that branches off from the data line62and extends to the upper portion of the oxide semiconductor layer40. The data wiring62,65,66,67also includes a drain electrode66that is separated from the source electrode65(facing the source electrode65, across the gate electrode26or the channel of the oxide thin film transistor, on the oxide semiconductor layer40), and an electrode extender67that has a large area and extends from the drain electrode66, overlapping the storage electrode27.

The data wiring62,65,66,67may be formed of a material that forms an ohmic contact by contacting directly with the oxide semiconductor layer40. When the data wiring62,65,66,67is formed of a material that has a work function smaller than the material of the oxide semiconductor layer40, ohmic contact may be made between the two layers. Therefore, when the work function of the oxide semiconductor layer40is above approximately 5 eV, for example, about 5.1 to 5.3 eV, the data wiring62,65,66,67may be formed of a material with about 5.3 eV or less work function. Further, it may be appropriate that the difference in work function of the data wiring62,65,66,67and the oxide semiconductor layer40is about 1.5 eV or less, in order to improve characteristics of contact resistance. Therefore, for the ohmic contact with the oxide semiconductor layer40, the data wiring62,65,66,67, as shown in the following Table 1, may be formed of a single film or multi-film of Ni, Co, Ti, Ag, Cu, Mo, Al, Be, Nb, Au, Fe, Se, or Ta. Furthermore, alloys containing the above metals and one or more elements selected from Ti, Zr, W, Ta, Nb, Pt, Hf, O, N may be applied.

Work functions of materials used for the data wiring62,65,66,67are shown in Table 1.

On the other hand, when the oxide semiconductor layer40directly contacts a metal, such as Al, Cu, Ag, the characteristics of the oxide thin film transistor with the data wiring62,65,66,67formed on the above metals and/or the characteristics of ohmic contact with ITO or IZO that is generally used for the pixel electrode82may be deteriorated by inter-reaction and diffusion. Therefore, the data wiring62,65,66,67may be formed in a double film or triple film structure.

On the other hand, when the data wiring62,65,66,67is formed of Cu or a Cu alloy, because the characteristics of ohmic contact between the data wiring62,65,66,67and the pixel electrode82are not practically affected, the data wiring62,65,66,67may be formed in a double film with a film containing Mo, Ti, or Ta between the oxide semiconductor layer40and a film of Cu or Cu alloy. For example, a double film, such as Mo(Mo alloy)/Cu, Ti(Ti alloy)/Cu, TiN(TiN alloy)/Cu, Ta(Ta alloy)/Cu, or TiOx/Cu may be applied.

The source electrode65overlaps at least a portion of the oxide semiconductor layer40and the drain electrode66overlaps at least a portion of the oxide semiconductor layer40, facing the source electrode65across the channel of the oxide thin film transistor.

The drain electrode extender67overlaps the storage electrode27and a storage capacitor is formed by the drain electrode extender67, the storage electrode27, and the intervening gate insulating film30formed between them. The drain electrode extender67may not be formed when the storage electrode27is not formed.

A passivation film70is formed on the data wiring62,65,66,67and exposed portions of the oxide semiconductor layer40. Because the passivation film70is in contact with the oxide semiconductor layer40, similar to the gate insulating film30, it may be formed of fluorine-containing silicon. The fluorine-containing silicon may be fluorine-containing silicon nitride, fluorine-containing silicon oxide, or fluorine-containing silicon oxynitride, such as SiOF, SiNF, SiONF, or SiOCF. When fluorine-containing silicon is used for the passivation film70, a low level of hydrogen is contained the passivation film70, such that it is possible to prevent deterioration of the electrical characteristics of the oxide semiconductor layer40.

A contact hole77that exposes the drain electrode extender67is formed through the passivation film70. The pixel electrode82is formed on the passivation film70, electrically connected with the drain electrode66through the contact hole77. The pixel electrode82may be formed of a transparent conductive material, such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a reflective conductive material, such as aluminum.

When a data voltage is applied, the pixel electrode82generates an electric field together with the common electrode (not shown) of the upper substrate (also not shown) facing the thin film transistor array substrate, such that the liquid crystal molecules are arranged in a predetermined pattern between the pixel electrode82and the common electrode.

In the above embodiments, the insulating films contacting the oxide semiconductor layer40, i.e., both the gate insulating film30and passivation film70, are formed of fluorine-containing silicon, but the invention is not limited to this material. In particular, one of the gate insulating film30and passivation film70may also be formed of fluorine-containing silicon and the other may be formed of silicon nitride or silicon oxide.

A method of producing fluorine-containing silicon for the insulating film contacting the oxide semiconductor layer40, i.e., the gate insulating film30or the passivation film70, will now be described. Fabricating these films of fluorine-containing silicon helps to prevent deterioration of the electrical characteristics of the oxide semiconductor layer40.

Hydrogen generally deoxidizes oxide, generating oxygen vacancy in the oxide. This oxygen vacancy increases the carrier concentration of the channel of the oxide semiconductor layer40. Therefore, as a high level of hydrogen is contained in the gate insulating film30or the passivation film70, the carrier concentration increases, such that the threshold voltage Vth of the oxide thin film transistor may shift in the negative direction, rendering the oxide semiconductor layer40conductive. Therefore, it is important to reduce the level of hydrogen in the gate insulating film30and the passivation film70, because they are in contact with the oxide semiconductor layer40.

According to an embodiment of the invention, a fluorine-containing silicon may be produced by the reaction of a first reaction gas containing Si and F without hydrogen, and a second reaction gas containing O, N, or F, also without hydrogen. This allows for production of fluorine-containing silicon with no hydrogen, preventing deterioration of electrical characteristics of the oxide semiconductor layer40(i.e., preventing the oxide semiconductor layer40from becoming a conductive layer). For example, the first reaction gas includes SiF, SiF2, SiF3, or SiF4, etc., and the second reaction gas includes NO, N2O, O2, NF, NF2, or NF3.

The following reaction formulae 1 to 4 represent examples of producing fluorine-containing silicon using a first reaction gas containing Si and F and a second reaction gas containing O, N, or F.
2SiF4(g)+2N2O(g)→2SiOF(s)+2N2(g)+3F2(g)  [Reaction Formula 1]
2SiF4(g)+2N2O(g)→2SiONF(s)+N2(g)+3F2(g)  [Reaction Formula 2]
2SiF4(g)+2O2(g)→2SiOF(s)+O2(g)+3F2(g)  [Reaction Formula 3]
2SiF4(g)+2CO2(g)→2SiOCF(s)+O2(g)+3F2(g)  [Reaction Formula 4]

The following reaction formulae 5 and 6 represent examples of producing fluorine-containing silicon, in which a first reaction gas contains fluorine (F) and a second reaction gas contains hydrogen (H).
2SiF4(g)+2NH3(g)→2SiF(s)+3H2(g)+3F2(g)  [Reaction Formula 5]
SiH4(g)+NF3(g)→SiNF(s)+2N2(g)+F2(g)  [Reaction Formula 6]

Referring to Reaction Formula 5, for example, the first reaction gas contains SiF, SiF2, SiF3, or SiF4and the second reaction gas contains NH2or NH3. Further, referring to Reaction Formula 6, for example, the first reaction gas contains NF, NF2, or NF3and the second reaction gas contains SiH4.

When the gate insulating film30is formed of fluorine-containing silicon as described above, the level of hydrogen in the gate insulating film30is prevented from increasing and the electrical characteristics of the oxide semiconductor layer40do not deteriorate. Further, when the passivation film70is formed of fluorine-containing silicon, the level of hydrogen in the passivation film70is also prevented from increasing and the electrical characteristics of the oxide semiconductor layer40do not deteriorate.

A method of manufacturing a thin film transistor array substrate according to a first embodiment of the invention is described hereafter in detail with reference toFIGS. 1A to 6. In particular,FIGS. 2 to 6are cross-sectional views of sequential processes illustrating a method of manufacturing a thin film transistor array substrate, or structure, according to a first embodiment of the invention.

The first process is to form the gate line22, gate electrode26, storage electrode27, and storage line28on the insulating substrate10as shown inFIGS. 1A and 2.

The insulating film10may be formed of a glass, such as soda lime glass or boro-silicate glass, or a plastic. Sputtering may be used to form the gate wiring22,26. Wet etching or dry etching may be used for patterning the gate wiring22,26. Etchant, such as phosphoric acid, nitric acid, or acetic acid, may be used for the wet etching, whereas a chlorine-containing etching gas, such as Cl2or BCl3, may be used for the dry etching.

Referring toFIGS. 1A and 3, the gate insulating film30(as above, made of fluorine-containing silicon) is formed on the insulating substrate10and gate wiring22,26by PECVD (Plasma Enhanced Chemical Vapor Deposition) or reactive sputtering. Further, the oxide semiconductor layer40is formed on the gate insulating film30.

Referring toFIGS. 1A and 4, the data wiring62,65,66,67is formed on the gate insulating film30and oxide semiconductor layer40, by sputtering for example. The source electrode65and drain electrode66are spaced at a predetermined distance from the gate electrode26, facing each other, and the electrode extender67extends from the drain electrode66to overlap the storage electrode27.

As shown inFIG. 5, the passivation film70of fluorine-containing silicon is formed by PECVD or reactive sputtering. The contact hole77that exposes the drain electrode extender67is formed by patterning the passivation film70using photo etching.

Referring toFIG. 6, a conductive film81for the pixel electrode is formed on the passivation film70. The conductive film81is connected to a portion of the data wiring62,65,66,67, and may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a reflective conductive material such as aluminum.

Referring toFIGS. 1B and 6, the pixel electrode82is formed by patterning the conductive film81.

A thin film transistor array substrate according to a second embodiment of the invention is described hereafter in detail with reference toFIG. 7.FIG. 7is a cross-sectional view of a thin film transistor array substrate according to a second embodiment of the invention. For the sake of convenience, components having the same function as previously-described components are represented by the same reference numerals, and accordingly are not described.

Referring toFIG. 7, a passivation film170is composed of a lower passivation film172that contacts the oxide semiconductor layer40, and an upper passivation film174that contacts the pixel electrode82(and does not contact the oxide semiconductor layer40). The lower passivation film172may be formed of fluorine-containing silicon to keep the electrical characteristics of the oxide semiconductor layer40. The upper passivation film174may be formed of an inorganic material containing silicon nitride or silicon oxide, an organic material having good planarization and photosensitivity, or a low dielectric constant material that is formed by PECVD, such as a-Si:C:O or a-Si:O:F. It is possible to prevent reduction of the hydrogen in the upper passivation film174with the oxide semiconductor layer40by forming the lower passivation film172in a thickness of about 3 nm or more.

A thin film transistor array substrate according to a third embodiment of the invention is described hereafter in detail with reference toFIG. 8.FIG. 8is a cross-sectional view of a thin film transistor array substrate according to a third embodiment of the invention. For the sake of convenience, components having the same function as previously-described components are represented by the same reference numerals, and accordingly are not described.

Referring toFIG. 8, a gate insulating film230is composed of a lower insulating film232that contacts the gate line22(and does not contact the oxide semiconductor layer40) and an upper insulating film234that contacts the oxide semiconductor layer40. The lower insulating film232may be formed of silicon nitride or silicon oxide, and the upper insulating film234may be formed of fluorine-containing silicon, to keep the electrical characteristics of the oxide semiconductor layer40. It is possible to prevent reduction of the hydrogen in the lower insulating film232with the oxide semiconductor layer40by forming the upper insulating film234in a thickness of about 3 nm or more.

A bottom gate structure with the gate electrode disposed under the oxide semiconductor layer was described in the above embodiments, but the present invention is not limited thereto and may be applied to a top gate structure with the gate electrode disposed on the oxide semiconductor layer. A thin film transistor array substrate of a top gate structure according to embodiments of the invention is described hereafter with reference toFIGS. 9 and 10.

A thin film transistor array substrate according to a fourth embodiment of the invention is described in detail with reference toFIG. 9.FIG. 9is a cross-sectional view of a thin film transistor array substrate according to a fourth embodiment of the invention.

Referring toFIG. 9, a buffer layer312of silicon oxide or silicon nitride is formed on an insulating substrate310. The buffer layer312, however, may be formed of fluorine-containing silicon to reduce hydrogen that is contained in the buffer layer312. The buffer layer312may not be provided, depending on process conditions.

An oxide semiconductor layer320of an oxide of a material selected from Zn, In, Ga, Sn, and their combination is then formed. For example, a composite oxide, such as ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, or GalnZnO, may be used for the oxide semiconductor layer320.

A gate insulating film330is formed on the insulating film310and oxide semiconductor layer320. The gate insulating film330may be formed of fluorine-containing silicon. The fluorine-containing silicon may be fluorine-containing silicon nitride, fluorine-containing silicon oxide, or fluorine-containing silicon oxynitride, such as SiOF, SiNF, SiONF, or SiOCF. When the gate insulating film330is formed of fluorine-containing silicon, a low level of hydrogen is contained the gate insulating film330, such that it is possible to prevent deterioration of the electrical characteristics of the oxide semiconductor layer320.

A gate electrode344is formed on the gate insulating film330, overlapping the oxide semiconductor layer320.

A first interlayer insulating film370is formed on the gate insulating film330and gate electrode344. The first interlayer insulating film370may be generally formed of a silicon oxide film, silicon nitride film, or silicon oxynitride film, using chemical vapor deposition. A pair of contact holes372,374exposes a portion of the oxide semiconductor layer320and is formed through the first interlayer insulating film370and the gate insulating film330, at both sides of the gate electrode344, respectively.

A source electrode382and a drain electrode384that are electrically connected with the oxide semiconductor layer320through the contact holes372,374are formed on the first interlayer insulating film370.

A second interlayer insulating film390formed of an organic material having good planarization and photosensitivity is formed on the source electrode382, drain electrode384, and first interlayer insulating film370. For example, the second interlayer insulating film390may be formed of an organic material such as acryl resin, using spin coating. A contact hole392that exposes the drain electrode374is formed in the second interlayer insulating film390.

A pixel electrode395of a transparent material that is electrically connected with the drain electrode374through the contact hole392is formed on second interlayer insulating film390.

A thin film transistor array substrate according to a fifth embodiment of the invention is described with reference toFIG. 10.FIG. 10is a cross-sectional view of a thin film transistor array substrate according to a fifth embodiment of the invention. For the sake of convenience, components having the same function as the components shown in the figure (FIG. 9) are represented by the same reference numerals, and accordingly are not described.

Referring toFIG. 10, a gate insulating film430in this embodiment is composed of two passivation films: a lower insulating film432that contacts the oxide semiconductor layer320, and an upper insulating film434that contacts the gate electrode344(and does not contact the oxide semiconductor layer320). The lower insulating film432may be formed of fluorine-containing silicon to keep the electrical characteristics of the oxide semiconductor layer40, and the upper insulating film434may be formed of silicon nitride or silicon oxide. It is possible to prevent reduction of the hydrogen in the upper insulating film434with the oxide semiconductor layer320by forming the lower insulating film432in a thickness of about 3 nm or more.

Although the present invention has been described in connection with the exemplary embodiments of the present invention with reference to the accompanying drawings, it will be apparent to those skilled in the art that various modifications and changes may be made thereto without departing from the scope and spirit of the invention. Therefore, it should be understood that the above embodiments are not limitative, but illustrative in all aspects.