Method for manufacturing non-volatile memory

A method for forming a non-volatile memory having a floating gate electrode arranged therein. The floating gate electrode being formed by alternatingly laminating on a silicon substrate a polysilicon layer and a tungsten silicide layer with a tunnel oxide sandwiched between said substrate and said polysilicon layer. The tungsten silicide layer is formed with a CVD technique reducing WF.sub.6 gas with SiH.sub.2 Cl.sub.2 gas.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to a method for forming a non-volatile memory, and 
more particularly to a method for forming a floating gate electrode. 
2. Description of the Prior Art 
Conventionally known is a non-volatile memory having a floating gate 
electrode arranged therein, said floating gate electrode being formed by 
laminating on a silicon substrate either a polysilicon layer or by 
alternatingly laminating a polysilicon layer and a tungsten silicide layer 
with a tunnel oxide sandwiched between said substrate and said polysilicon 
layer. 
As a method for forming a floating gate electrode formed by laminating a 
polysilicon layer or by alternatingly laminating a polysilicon and a 
tungsten silicide layer with a tunnel oxide sandwiched between said 
substrate and said polysilicon layer, known is a method wherein a tungsten 
silicide layer is laminated on a polysilicon layer with a CVD technique of 
reducing WF.sub.6 gas with SiH.sub.4 gas at 300.degree. C. to 400.degree. 
C. under reduced pressure. 
In a conventional method for forming a floating gate electrode formed by 
alternatingly laminating a polysilicon layer and a tungsten silicide 
layer, the laminated electrode has approximately 1/10 of the specific 
resistance compared to a floating gate electrode formed of only a 
polysilicon layer. Thus the laminated floating gate electrode is favorably 
used in devices that require a high response speed compared to the 
response speed of devices having floating gate electrodes formed of only a 
polysilicon layer. However, even such a laminated floating gate electrode 
formed by alternatingly laminating a polysilicon layer and a tungsten 
silicide layer is liable to tear at the tunnel oxide because of to the 
operation of rewriting memory contents. 
SUMMARY OF THE INVENTION 
It is an object of the invention to overcome the above drawback. This 
invention provides a method for forming a non-volatile memory small in 
specific resistance and high in response speed while prolonging the 
life-span of the tunnel oxide to the degree almost identical to that of 
the polysilicon layer while minimizing the fragility in the operation of 
rewriting memory contents. 
This invention provides a method for forming a non-volatile memory having a 
floating gate electrode arranged therein. The floating gate electrode 
being formed by alternatingly laminating on a silicon substrate a 
polysilicon layer and a tungsten silicide layer with a tunnel oxide 
sandwiched between the substrate and a polysilicon layer, wherein the 
tungsten silicide layer is formed with a chemical vapour deposition (CVD) 
technique reducing WF.sub.6 gas with SiH.sub.2 Cl.sub.2 gas.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
According to this invention, a floating gate electrode is arranged in the 
non-volatile memory, the electrode is formed by alternatingly laminating 
on a silicon substrate a polysilicon layer and a tungsten silicide layer 
with a tunnel oxide sandwiched between the substrate and polysilicon 
layer. 
The purpose of providing a tunnel oxide is two-fold; One is to transfer 
electric charge with a tunnel effect between the source/drain and the 
floating gate electrode when a high voltage is applied for writing in and 
rewriting the memory content. The other is to insulate the floating gate 
electrode when a high voltage is not applied. A 60 to 120 .ANG. thick 
silicon oxide is usually provided for forming the tunnel oxide. 
The floating gate electrode is provided for accepting and discharging 
electric charges through the tunnel oxide in accordance with the memory 
content to either write in or call at a high response speed the memory 
content. The specific resistance of the floating gate electrode is 
preferably small. It is formed by alternatingly laminating on a tunnel 
oxide a polysilicon layer and a tungsten silicide layer. Either a N.sup.+ 
or P.sup.+ impurity-doped layer may be formed on the tunnel insulating 
film surface in the actual usage of the polysilicon layer. The thickness 
of the polysilicon layer is usually 0.1 .mu.m to 0.3 .mu.m. 
The tungsten silicide layer is provided for reducing the specific 
resistance of the floating gate electrode. It is laminated on the 
polysilicon layer to form together a floating gate electrode. 
The tungsten silicide layer is formed in the following manner. A silicon 
substrate whose surface is coated with a polysilicon layer with a tunnel 
oxide sandwiched therebetween is arranged in a CVD apparatus. It is heated 
to a predetermined temperature, followed by supplying a predetermined 
amount of WF.sub.6 gas and SiH.sub.2 Cl.sub.2 gas to reduce WF.sub.6 gas 
with SiH.sub.2 Cl.sub.2 gas for laminating a predetermined amount of 
tungsten silicide layer to a predetermined thickness. 
The predetermined temperature in the above process is usually 450 to 
650.degree. C., or preferably 500 to 600.degree. C. In supplying gas to 
the CVD device, the flow rate of WF.sub.6 gas is usually determined to be 
1 to 5 sccm while SiH.sub.2 Cl.sub.2 gas is usually 100 to 200 sccm. 
Supplying WF.sub.6 gas and SiH.sub.2 Cl.sub.2 gas usually provides the 
pressure of 0.01 to 1 Torr, or preferably 0.07 to 0.1 Torr in the CVD 
device. WF.sub.6 gas in the amount preferably corresponding to the partial 
pressure of 0.001 to 0.003 Torr is reduced with SiH.sub.2 Cl.sub.2 gas in 
the amount preferably corresponding to the partial pressure of 0.07 to 0.1 
Torr. The tungsten silicide layer thus obtained usually contains 
approximately 1.times.10.sup.19 atoms/cm.sup.3 of fluorine. Preferably the 
amount is 1.times.10.sup.20 atoms/cm.sup.3 or less. Besides the thickness 
of the tungsten silicide layer is preferably 0.1 to 0.3 .mu.m. 
In this invention, a laminated region of the tungsten silicide layer and 
the polysilicon layer are etched into a predetermined patterns. The etched 
surface is coated with an insulating layer to form a floating gate 
electrode. Subsequently, a source/drain and a metal electrode are formed 
to form a non-volatile memory in the same manner with the method of 
forming known EEPROMs. 
This invention is described in further detail by way of example with 
respect to the drawings. 
Embodiment 
Referring initially to FIG. 1, on a silicon substrate 1, a field oxide film 
2 is formed to isolate device regions. After forming an ion implantation 
layer in the silicon substrate below a tunnel oxide formation region 
within the memory cell, a gate oxide is formed in the thickness of 
approximately 200 .ANG. in this device region. 
Following this process, a window is formed with a photolithographic 
technique in a tunnel oxide formation region. 
As shown in FIG. 2, an approximately 80 .ANG. thick tunnel oxide 4 is 
formed to deposit thereon an approximately 0.15 .mu.m thick (thickness 
above the gate oxide 3) phosphorus-doped polysilicon layer. 
As shown in FIG. 3, approximately 0.2 .mu.m thick tungsten silicide layer 6 
is formed at 500 to 600.degree. C. with a LPCVD technique using both 
SiH.sub.2 Cl.sub.2 and WF.sub.6 gas. However the amount of SiH.sub.2 
Cl.sub.2 gas and WF.sub.6 gas to be supplied in the CVD device is 
respectively 100 to 200 sccm and 1 to 5 sccm. The CVD device is applied 
with the pressure (reaction pressure) of 0.07 Torr to 0.1 Torr. 
In the next process, as shown in FIG. 4, a tungsten silicide layer 6 and a 
polysilicon layer 5 are etched into a predetermined pattern. On the 
surface, silicon oxide layer is formed to provide a floating gate 
electrode 8. Later, a source 9, a drain 10 and a metal electrode is 
provided to form a non-volatile device in a manner similar to those used 
in conventional techniques of forming EEPROMs. 
Comparison 1 
Unlike Embodiment 1, in Comparison 1 a phosphorus-doped polysilicon layer 
is formed with a thickness of 0.15 .mu.m. On the surface, a floating gate 
electrode is formed only with the polysilicon layer without forming a 
tungsten silicide layer. Thus, a non-volatile DRAM is formed in the same 
manner with Embodiment 1 except for the above point. 
Comparison 2 
Unlike Embodiment 1, in Comparison 2 SiH.sub.4 gas is used in the place of 
SiH.sub.2 Cl.sub.2 to form a tungsten silicide layer with a liquid phase 
chemical vapour deposition (LPCVD) technique at 300 to 400.degree. C. 
Thus, a non-volatile memory is formed in the same manner with Embodiment 1 
except for this point. 
The average time of the tunnel oxide breakdown in Example 1, Comparison 1 
and Comparison 2 is determined by measuring the fluorine content and the 
specific resistance of the floating gate electrode and by measuring the 
time dependent dielectric breakdown (TDDB) of constant current. 
TABLE 1 
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Tunnel Oxide 
Floating Gate Electrode 
Embodiment 
Average Fluorine Specific 
and Breakdown Time Content Resistance 
Comparison * (atoms/cm.sup.3) (.mu..OMEGA. .multidot. cm) 
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E 1 80 1 .times. 10.sup.19 
100 
C 1 100 0 1000 
C 2 15 1 .times. 10.sup.21 100 
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* Comparison 1 is determined to be 100. 
As is shown in Table 1, it is proven that the non-volatile memory obtained 
in the embodiment of the invention has a floating gate electrode with a 
small specific resistance free from a large decrease in the average 
breakdown time of the tunnel oxide. 
Operation 
SiH.sub.2 Cl.sub.2 reduces WF.sub.6 gas to form a tungsten silicide layer 
containing only a minimal amount of fluorine as an impurity. The tungsten 
silicide layer containing only a minimal amount of fluorine inhibits the 
breakage of the tunnel oxide due to the operation of rewriting the memory 
content. 
Effect of the Invention 
This invention provides a process for forming a non-volatile memory 
provided with a floating gate electrode small in specific resistance and 
high in response speed without shrinking the life-span of the tunnel oxide 
owing to the operation of rewriting the memory content.