Semiconductor packaging structure having electromagnetic shielding function and method for manufacturing the same

A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor packaging structure, and more particular, to a semiconductor packaging structure having electromagnetic shielding function.

2. Description of the Prior Art

Semiconductor packaging processes typically involve electrical connections between chips and substrates via die bonding and wire bonding, external housing fabrication, and sawing processes to form a plurality of semiconductor packages.

FIG. 1illustrates a cross-section view of a semiconductor packaging structure according to the prior art. As shown inFIG. 1, a semiconductor packaging structure100includes a carrier101and a semiconductor substrate110disposed on the carrier101. A micro-electromechanical system, such as a micro-electromechanical microphone can be placed on the semiconductor substrate110. The carrier101has a first surface101aand a second surface101bopposite to the first surface101a, in which a plurality of pads102and a grounding pad103are disposed on the first surface101a. In one embodiment, a grounding layer104can be formed in the interior of the carrier101for electrically connecting the grounding pad103.

The semiconductor substrate110is disposed on the surface101aof the carrier101, in which the semiconductor substrate110includes a top surface110ahaving a plurality of pads112thereon and a bottom surface110bopposite to the top surface110a. A micro-electromechanical system, such as a micro-electromechanical microphone is disposed on the semiconductor substrate110. The pads102formed on the carrier101are electrically connected to the pads112disposed on the semiconductor substrate110through the wires150. A housing130is provided to surround the semiconductor substrate110. The housing130is composed of conductive material, and another conductive material132is disposed between the bottom of the housing130and the grounding pad103of the carrier101to provide electromagnetic shielding ability for the semiconductor packaging structure100and reduce the interference of electromagnetic wave for improving the sound quality of micro-electromechanical microphone.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a semiconductor packaging structure having electromagnetic shielding function. The semiconductor packaging structure preferably includes a carrier and a semiconductor substrate disposed on the carrier. A patterned passivation layer and a patterned metal layer are formed on the semiconductor substrate, in which the patterned metal layer is electrically connected to at least a grounding pad on the substrate via a wire, thus providing an electromagnetic shielding function for the package.

It is another objective of the present invention to provide a method for fabricating a semiconductor packaging structure having electromagnetic shielding function. The method involves forming a patterned passivation layer and a patterned metal layer on a semiconductor substrate and utilizing a wire to electrically connect the patterned metal layer and a grounding pad on the substrate, thus providing the electromagnetic shielding function for the package.

A semiconductor packaging structure having electromagnetic shielding function is also provided according to the aforementioned fabrication processes. The semiconductor packaging structure has a carrier, a semiconductor substrate disposed on the carrier, a patterned passivation layer disposed on the semiconductor substrate, a patterned metal layer disposed on the patterned passivation layer, and a wire. At least a grounding pad is disposed on the carrier, and the wire is electrically connected to the patterned metal layer and the grounding pad of the carrier. The carrier has at least a first surface and a second surface opposite to the first surface, in which the first surface has a plurality of first pads and at least one grounding pad thereon. The semiconductor substrate is disposed on the first surface of the carrier. The semiconductor substrate has a top surface and a bottom surface opposite to the top surface, in which the top surface is electrically connected to the first pads of the carrier. The patterned passivation layer is disposed on the top surface of the semiconductor substrate and the patterned metal layer is disposed on the patterned passivation layer.

According to an embodiment of the present invention, the aforementioned first patterned passivation layer is formed to expose a plurality of second pads disposed on the top surface of the semiconductor substrate, and a second wire is used to electrically connect the second pads and the first pads disposed on the carrier.

According to an embodiment of the present invention, a redistributing layer and a second patterned passivation layer are formed on the aforementioned first patterned passivation layer. The redistributing layer is electrically connected to the second pads of the semiconductor substrate, and the second patterned passivation layer is formed to expose a portion of the redistribution layer, in which the exposed portion of the redistributing layer is electrically connected to the first pads of the carrier through the second wire.

It is another objective of the present invention to provide a method for fabricating semiconductor packaging structures. First, a semiconductor wafer having a top surface and a bottom surface opposite to the top surface is provided, in which the top surface has a plurality of first pads and at least a grounding pad. Next, a first patterned passivation layer is formed on the top surface of the semiconductor wafer, and a patterned metal layer is formed on the first patterned passivation layer. The semiconductor wafer is then sawed to form a plurality of semiconductor substrates, in which the top surface of every semiconductor substrate has a portion of the first pads. The semiconductor substrate is then placed on a first surface of a carrier. The carrier has a first surface and a second surface opposite to the first surface. A plurality of second pads and at least a grounding pad are disposed on the first surface of the carrier, in which the second pads are electrically connected to every portion of the first pads. A wire is then formed to electrically connect the patterned metal layer and the grounding pad.

Specifically, the semiconductor package structure of the present invention is fabricated by first forming a patterned metal layer on the patterned passivation layer and utilizing wires to electrically connect the patterned metal layer and the grounding pads of the carrier. The fabricated semiconductor package structure would then have electromagnetic shielding ability capable of reducing interference of electromagnetic waves and increase the sound quality of micro-electromechanical microphones.

DETAILED DESCRIPTION

It is an objective of the present invention to provide a semiconductor packaging structure having electromagnetic shielding function for reducing interference caused by electromagnetic waves and improving the sound quality of the product, such as micro-electromechanical microphones. Several embodiments are discussed below to illustrate the highlight of the present invention.

Please refer toFIG. 2A.FIG. 2Aillustrates a top-view of a semiconductor packaging structure according to the preferred embodiment of the present invention. The semiconductor packaging structure200includes a carrier201and a semiconductor substrate210disposed on the carrier201. A patterned passivation layer220, a patterned metal layer230and a plurality of pads212are formed on the semiconductor substrate210, in which the patterned metal layer230exposes the pads212. A plurality of pads (not shown) and at least a grounding pad (not shown) are also disposed on the carrier. The patterned metal layer230is electrically connected to the grounding pad of the carrier201, and the pads212of the semiconductor substrate210are electrically connected to the pads (not shown) of the carrier201.

Please refer toFIG. 2B.FIG. 2Billustrates a cross-section of the semiconductor packaging structure along the sectional line A-A′ ofFIG. 2A. Specifically, the semiconductor packaging structure200includes a carrier201and a semiconductor substrate201dispose on the carrier201. A patterned passivation layer220, a patterned metal layer230, and a plurality of pads212are formed on the semiconductor substrate210. At least a grounding pad202is disposed on the carrier201. The patterned metal layer230is electrically connected to the ground pad203of the carrier through the wire240, thus providing an electromagnetic shielding ability for the semiconductor packaging structure200.

Preferably, a carrier201having a surface201aand a surface201bopposite to the surface201ais first provided. A plurality of pads202and at least a grounding pad203are disposed on the surface201a. According to an embodiment of the present invention, a grounding layer204is pre-formed within the carrier201for electrically connecting the grounding pad203. Additionally, a grounding ring (not shown) can be formed on the surface201aof the carrier201to electrically connect the grounding pad203, which is also within the scope of the present invention. Preferably, this grounding ring is formed to surround every semiconductor substrate fabricated in the later process.

The semiconductor substrate210can be attached to the surface201aof the carrier201by typical adhesion process. In the present invention, the semiconductor substrate210can be composed of integrated circuit chips or semiconductor substrates having micro-electromechanical systems such as micro-electromechanical microphones, but not limited thereto. According to an embodiment of the present invention, the semiconductor substrate210is formed by sawing a semiconductor wafer (not shown). The semiconductor wafer preferably has a top surface210aand a bottom surface210bopposite to the top surface210a. A plurality of pads212is also disposed on the top surface210a.

Subsequently, a patterned passivation layer220is formed on the top surface210aof the semiconductor wafer, in which the patterned passivation layer220can be composed of polyimide or benzocyclobutane. According to an embodiment of the present invention, the patterned passivation layer220is formed to expose the pads212disposed on the top surface210aof the semiconductor substrate210, such that these pads212can be electrically connected to the pads202of the carrier201through the wires250thereafter. Next, an electroplating process or a sputtering process can be performed to form the patterned metal layer230on the patterned passivation layer220, in which the patterned metal layer230exposes the aforementioned pads212. The patterned metal layer230is composed of material having electromagnetic shielding capability, such as metals including copper or aluminum. Thereafter, the semiconductor wafer is sawed to form a plurality of semiconductor substrates210, in which the top surface210aof each semiconductor substrate210has a portion of the pads212. Each of the semiconductor substrates210is then attached onto the carrier201. The carrier201has a surface201aand a surface201bopposite to the surface201a, in which each of the semiconductor substrates210is disposed on the surface201aof the carrier201. A plurality of pads202and at least a grounding pad203are also formed on the surface201aof the carrier201. The pads202are electrically connected to the pads212of each semiconductor substrate210through the wires250. A wire240is then formed to electrically connect the patterned metal layer230and the grounding pad203.

Please refer toFIG. 2C.FIG. 2Cillustrates a cross-section view of a semiconductor packaging structure taken along the line AA′ ofFIG. 2A. After the patterned passivation layer220is formed, a redistribution layer224is formed on the pads212. The redistribution layer224is composed of metal, which can be used to establish an electrical connection for the pads212and redistribute the location of the pads212accordingly. Next, another patterned passivation layer226is formed on the patterned passivation layer220and the redistribution layer224, in which the patterned passivation layer226exposes a portion of the redistribution layer224. The patterned passivation layer226is composed of polyimide or benzocyclobutane. Thereafter, the patterned metal layer230is formed on the patterned passivation layer226to expose a portion of the redistribution layer224, in which the formation and the material of the patterned metal layer230is according to the method and material described previously. The semiconductor wafer is then sawed to form a plurality of semiconductor substrates210, in which a portion of the redistribution layer224is exposed from the top surface210aof each of the semiconductor substrates210. Next, each semiconductor substrate210is attached to the carrier201. The carrier201has a surface201aand a surface201bopposite to the surface201a, in which each semiconductor substrate210is disposed on the surface201aof the carrier201. The portion of the redistribution layer224exposed from the semiconductor substrate210is electrically connected to the pads202of the carrier201via the wires250. A plurality of wires240is then formed to electrically connect the patterned metal layer230and the grounding pad203.

Please refer toFIG. 3A.FIG. 3Aillustrates a top view of a semiconductor packaging structure according to an embodiment of the present invention. As shown inFIG. 3A, the semiconductor packaging structure300includes a carrier301and a semiconductor substrate310disposed on the carrier301. A patterned passivation layer320, a patterned metal layer330, and a plurality of pads212are disposed on the semiconductor substrate310, in which the patterned metal layer330is formed to expose the pads212and a portion of the patterned passivation layer320. A plurality of pads (not shown) and at least a grounding pad (not shown) are disposed on the carrier301. The patterned metal layer330is electrically connected to the grounding pad (not shown) of the carrier301, and the pads312of the semiconductor substrate310are electrically connected to the pads (not shown) of the carrier301. In contrast toFIG. 2A, the pads312of the semiconductor substrate310shown inFIG. 3Aare covered by the patterned passivation layer320, and the patterned metal layer330on the pads312are formed corresponding to the shape of a comb to expose a portion of the patterned passivation layer320disposed on the pads312.

Please refer toFIG. 3B.FIG. 3Billustrates a cross-section view of the semiconductor packaging structure taken along line BB′ ofFIG. 3A. As shown inFIG. 3B, the semiconductor packaging structure300has a carrier301and a semiconductor substrate310disposed thereon. A patterned passivation layer320and a patterned metal layer330are formed on the semiconductor substrate310. A grounding pad302is disposed on the carrier301, and the patterned metal layer330formed on the semiconductor substrate310is electrically connected to the grounding pad303of the carrier301for providing electromagnetic shielding ability of the semiconductor packaging structure300.

Preferably, a carrier301having a surface301aand a surface301bopposite to the surface301ais first provided. A plurality of pads302and at least a grounding pad303are disposed on the surface301a. According to an embodiment of the present invention, a grounding layer304is pre-formed within the carrier301for electrically connecting the grounding pad303. Additionally, a grounding ring (not shown) can be formed on the surface301aof the carrier301to electrically connect the grounding pad303, which is also within the scope of the present invention. Specifically, this grounding ring is formed to surround every semiconductor substrate fabricated in the later processes.

The semiconductor substrate310can be attached to the surface301aof the carrier301by typical adhesion process. In the present invention, the semiconductor substrate310can be composed of integrated circuit chips or semiconductor substrates having micro-electromechanical systems such as micro-electromechanical microphones, but not limited thereto. According to an embodiment of the present invention, the semiconductor substrate310is formed by sawing a semiconductor wafer (not shown). The semiconductor wafer preferably has a top surface310aand a bottom surface310bopposite to the top surface310a. A plurality of pads312is also disposed on the top surface310aof the wafer.

Thereafter, a patterned passivation layer320is formed on the top surface310aof the semiconductor wafer, in which the patterned passivation layer320can be composed of polyimide or benzocyclobutane. According to an embodiment of the present invention, the patterned passivation layer320is disposed on the pads312, in which the pads312are electrically connected to the pads302of the carrier301through the wires350thereafter. Next, an electroplating process or a sputtering process is performed to form the patterned metal layer330on the patterned passivation layer320, in which the patterned metal layer330disposed on the pads312is formed corresponding to the shape of a comb for exposing a portion of the patterned passivation layer320. Preferably, the patterned metal layer330is composed of metals having electromagnetic shielding ability, such as copper or aluminum. Thereafter, the semiconductor wafer is sawed to form a plurality of semiconductor substrates310, in which the top surface310aof each semiconductor substrate310has a portion of the pads312covered by the patterned passivation layer320. Each of the semiconductor substrates310is then attached to the carrier301. The carrier310has a surface301aand a surface301bopposite to the surface301a, in which each of the semiconductor substrates310is disposed on the surface301aof the carrier301. A plurality of pads302and at least a grounding pad303are disposed on the surface301aof the carrier301. The pads302are electrically connected to the pads312of each semiconductor substrate310through the redistribution layer324and the wires350. The wires340are then formed to electrically connect the patterned metal layer330and the grounding pad303.

Depending on the design of the product, a housing can be fabricated on the semiconductor packaging structure of the present invention thereafter. In contrast to the conventional semiconductor packaging structures of using conductive housings to electrically connect the grounding pad of the carrier thereby providing electromagnetic shielding ability, the present invention specifically forms a patterned metal layer on the semiconductor substrate and utilizes wires to electrically connect this patterned metal layer to at least a grounding pad disposed on the carrier for providing electromagnetic shielding ability for the package. Hence, the housing of the present invention is not limited to the conductive housing utilized in the conventional art. Housings composed of other non-conductive material can also be applied in the present invention.

According to the aforementioned embodiments, the semiconductor package structure and fabrication method thereof have several advantages. Specifically, the semiconductor package structure of the present invention is fabricated by first forming a patterned metal layer on the patterned passivation layer and utilizing wires to electrically connect the patterned metal layer and the grounding pads of the carrier. The fabricated semiconductor package structure would then have electromagnetic shielding ability capable of reducing interference of electromagnetic waves and increase the sound quality of micro-electromechanical microphones.