Bias voltage generation circuit and driver integrated circuit

A bias voltage generation circuit includes a data holding section, a correction value storage section, a computing circuit, a voltage dividing circuit and a selection circuit. The data holding section holds a variable n-bit data value that is set from an exterior, wherein n is a positive integer. The correction value storage section stores an n-bit correction value for correcting the n-bit data value. The computing circuit computes the n-bit data value and the n-bit correction value, and outputs an n-bit computing result. The voltage dividing circuit divides a reference voltage into 2n voltages, and outputs 2n levels of divided voltages. The selection circuit selects one level of a divided voltage from the 2n levels of divided voltages on the basis of the n-bit computing result and outputs the selected divided voltage as a bias voltage, the output bias voltage having a variation over 2n levels.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 from Japanese Patent Application No. 2008-209660 filed on Aug. 18, 2008, the disclosure of which is incorporated by reference herein.

RELATED ART

1. Field of the Invention

The present disclosure relates to a bias voltage generation circuit that generates plural levels of reference voltages (i.e., bias voltages) based on data or value set from an exterior, and a driver integrated circuit including the bias voltage generation circuit, for example, a driver integrated circuit (hereinafter, referred to as a “driver IC”) for driving a display device such as a liquid crystal display.

2. Description of the Related Art

Conventionally, techniques relating to a bias voltage generation circuit that generates a reference voltage (i.e., bias voltage) used for an internal circuit in a semiconductor integrated circuit or the like are disclosed, for example, in the following documents. Japanese Patent Application Laid-Open (JP-A) No. 3-172906 discloses a technique of a trimming circuit in which, due to a program setting for plural fuses, an output voltage is outputted based on one voltage selected from a group of plural voltages divided by resistors. JP-A No. 2001-216034 discloses a technique of an internal power supply voltage generation circuit in which a selection circuit is controlled by an on-demand variable control signal or a fixed control signal such as a read only memory (hereinafter, referred to as “ROM”), and a second reference voltage is generated based on a divided voltage that results from the controlling of the selected circuit.

These techniques may be suitable for generating one level of a bias voltage or several levels of bias voltages. However, when a bias voltage generation circuit is provided inside a driver IC driving a display panel such as a liquid crystal display (hereinafter, referred to as “LCD”), it is necessary to generate a number of levels of bias voltages. Therefore, it has been difficult to reduce circuitry scale and electric power consumption. Accordingly, there has been proposed a bias voltage generation circuit, for example as shown inFIG. 10, which may be provided inside an LCD driver.

FIG. 10is a schematic block diagram of a bias voltage generation circuit in the related art.

The bias voltage generation circuit has a register1that holds a variable n-bit (e.g., 8-bit) register value set under control of a control IC (which includes a microprocessor (hereinafter, referred to as “MPU”)) for controlling a driver IC, and a resistance-voltage dividing circuit2that divides a reference voltage VRS and outputs 28(=256) levels of divided voltages. A selection circuit3is connected to the output sides of both the register1and the resistance-voltage dividing circuit2. The selection circuit3is a circuit that selects one level of a divided voltage from 256 levels of the divided voltages based on the 8-bit register value and outputs the divided voltage DV having a variation over 256 levels. An amplifier circuit4is connected to the output side of the selection circuit3. The amplifier circuit4is a circuit that amplifies the divided voltage DV and outputs a bias voltage BV.

In this bias voltage generation circuit, one level divided voltage DV is selected at the selection circuit3, based on a setting of the register1, from plural levels of voltages divided by the resistance-voltage dividing circuit2based on the reference voltage VRS, amplified at the amplifier4, and as a result the bias voltage BV having a variation over 256 levels is outputted. By varying the register value, the bias voltage BV having a variation over plural levels can be generated by a relatively simple circuit configuration, and thus it is possible to reduce circuitry scale and electric power consumption.

FIG. 11is a workflow of conventional mass-production and shipping of a driver IC.

For example, a case will be explained in which a driver IC having the bias voltage generation circuit ofFIG. 10is produced at Driver IC-manufacturing company A, and the mass-produced driver IC is shipped to Panel module assembly company B by which panel module is assembled, and the assembled panel module is sold to Panel module purchase company C, and thereafter, delivered to User D such as an equipment manufacturer.

Panel module purchase company C finishes a display panel such as an LCD by combining the purchased panel module with a control IC or the like for controlling a driver IC, and delivers the display panel to User D.

Firstly, Driver IC manufacturing company A prepares various register values for the register1inFIG. 10taking into consideration a type of display panel with which the driver IC is combined, and mass-produces the driver ICs and ships the driver ICs to Panel module assembly company B. Since Panel module assembly company B does not prepare a control IC for controlling the driver IC, Panel module assembly company B is not able to change (correct) the register value set for the register1inFIG. 10. Therefore, Panel module assembly company B assembles panel module by simply combining the purchased driver IC with the display panel, and sells the panel module to Panel module purchasing company C.

Panel module purchasing company C sets the register value for the register1inFIG. 10by combining the purchased panel module with a control IC for controlling the driver IC. In this regard, a relatively complicated task of correcting the register value considering a characteristic difference of each display panel is needed. In other words, although a register value is prepared by Driver IC manufacturing company A according to the type of the display panel, it is still necessary to make a slight correction (adjustment) of the register value for each display panel.

Slight adjustment is necessary to the bias voltage for driving (displaying) display panel, for each display panel. Conventionally, this adjustment of the bias voltage is realized by Panel module purchasing company C by changing (correcting) the register value corresponding to each display panel. Thereafter, the finished display panel is delivered to User D.

Thus, in the conventional bias voltage generation circuit as shown inFIG. 10, it is necessary to make an adjustment to the bias voltage required for displaying a display panel, corresponding to each display panel. Accordingly, a complicated task of changing the register value for each display panel was necessary.

INTRODUCTION TO THE INVENTION

An aspect of the disclosure is a bias voltage generation circuit including: a data holding section that holds a variable n-bit data value that is set from an exterior, wherein n is a positive integer; a correction value storage section that stores an n-bit correction value for correcting the n-bit data value; a computing circuit that computes the n-bit data value and the n-bit correction value, and outputs an n-bit computing result; a voltage dividing circuit that divides a reference voltage into 2nvoltages, and outputs 2nlevels of divided voltages; and a selection circuit that selects one level of a divided voltage from the 2nlevels of divided voltages on the basis of the n-bit computing result, and outputs the selected divided voltage as a bias voltage, the output bias voltage having a variation over 2nlevels.

DETAILED DESCRIPTION

The exemplary embodiments of the present disclosure are described and illustrated below to encompass bias voltage generation circuits, methods of manufacturing the same, and devices incorporating bias voltage generation circuits. Of course, it will be apparent to those of ordinary skill in the art that the preferred embodiments discussed below are exemplary in nature and may be reconfigured without departing from the scope and spirit of the present invention. However, for clarity and precision, the exemplary embodiments as discussed below may include optional steps, methods, and features that one of ordinary skill should recognize as not being a requisite to fall within the scope of the present disclosure. It should be noted that the drawings are solely for description and are not to limit the technical scope of the present invention.

Configuration of Driver IC of Exemplary Embodiment

FIG. 2is a schematic block diagram of a driver IC having a bias voltage generation circuit according to the exemplary embodiment.

A driver IC10is a circuit that is controlled by a control IC30having an MPU or the like and that drives a display panel40such as an LCD. In the driver IC10, there is provided an MPU interface11that transmits and receives both display data and a control signal between the MPU interface11and the control IC30. A bus12is connected to the MPU interface11. A command decoder13that decodes a program is connected between the bus12and the MPU interface11.

To the bus12are connected a column-address circuit14that selects a column-address, a line-address circuit15that selects a line-address, a page-address circuit16that selects a page-address, and an input/output (hereinafter, referred to as “I/O”) buffer17. A display data RAM18(with 136×132×2 bit structure, for example), which is a random access memory that is writable/readable any time and for storing display data. Further, the driver IC10is provided with an oscillation circuit20. A synchronized clock signal generated by the oscillation circuit20is supplied to a display timing generation circuit21. A display timing signal generated by the display timing generation circuit21is supplied to the line -address circuit15, a display data latch circuit19, a common output state selection circuit24, and the bus12. The display timing signal supplied to the bus12is sent to a power supply circuit22and the like.

The power supply circuit22is a circuit that generates plural levels of voltages for driving the display panel40and is provided with a bias voltage generation circuit according to the embodiment. The plural levels of voltages generated from the power supply circuit22are supplied to a segment driver23and a common driver25. The output state of the common driver25is selected by the common output state selection circuit24. Plural segment lines (SEG)41-0to41-n in the display panel40are driven by the segment driver23, and plural common lines (COM)42-0to42-n in the display panel40are driven by the common driver25.

Configuration of Bias Voltage Generation Circuit of Exemplary Embodiment

FIG. 1is a schematic block diagram showing the bias voltage generation circuit according to the exemplary embodiment.

The bias voltage generation circuit50is provided inside the power supply circuit22inFIG. 2, and includes a data holding section51(for example, a register) and a correction value storage section52(for example, a non-volatile memory such as an erasable programmable ROM (EPROM)). The data holding section51holds a variable n-bit (wherein n is a positive integer, for example 8-bit) data value (for example a register value) RV set from an external device (such as the control IC30). The correction value storage section52stores an 8-bit correction value in which each one bit of the 8 bits are respectively referred to as CV0to CV7for correcting the 8-bit register value RV. A computing circuit60is connected to the output sides of the register51and the non-volatile memory52. The computing circuit60is a circuit that computes the 8-bit register value RVs and the 8-bit correction value CV0to CV7(by an add-subtract operation using a complementary operation of 2) and outputs an 8-bit computing result in which each one bit of the 8 bits are respectively referred to as S0to S7.

A voltage dividing circuit (for example, a resistance voltage dividing circuit)70is provided in the bias voltage generation circuit50. The resistance-voltage dividing circuit70is a circuit that divides a reference voltage VRS (3V, for example) into 28(=256) voltages using plural voltage-dividing resistors71-0to71-p that are connected in series, and outputs 256 levels of divided voltages DV0to DV255. A selection circuit80is connected to the resistance-voltage dividing circuit70and the computing circuit60at the output sides thereof. The selection circuit80is a circuit that selects one level of a divided voltage DV from the 256 levels of divided voltages DV0to DV255based on the 8-bit computing result S0to S7.

An amplifier circuit (positive-phase amplifier circuit, for example)90is connected to the selection circuit80at the output side thereof as necessary. The amplifier circuit90is a circuit that amplifies the divided voltage DV and outputs a variable bias voltage BV having a variation over 256 levels, and includes an operational amplifier (hereinafter, referred to as “OP-amp”)91, an input resistor92, and a feedback resistor93.

FIG. 3is a block diagram of one example of the computing circuit60inFIG. 1.

The computing circuit60performs an add-subtract operation using a complementary operation of2with respect to the 8-bit register value RV and the 8-bit correction value CV0to CV7and outputs the 8-bit computing result S0to S7. The computing circuit60is arranged such that a half-adder61at the 1ststage and full -adders62to68from the 2ndto the 8thstages are connected in a cascade (tandem) connection.

FIG. 4is a block diagram showing one example of the selection circuit80inFIG. 1.

The selection circuit80includes plural negative AND gates (hereinafter, referred to “NAND” gates)81-0to81-255that decode the 8-bit computing result S0to S7and plural signal inverters82-0to82-255that generate complementary signals from output signals of the NAND gates81-0to81-255. Plural analog switches83-0to83-255are connected to the output side of the inverters82-0to82-255. Each of the analog switches83-0to83-255is arranged such that a P-channel MOS transistor (hereinafter, referred to “PMOS”) and an N-channel MOS transistor (hereinafter, referred to as “NMOS”), which on/off operations are performed in response to the complementary signals outputted from the inverters82-0to82-255, are connected in parallel.

In response to the complementary signals outputted from the inverters82-0to82-255, the analog switches83-0to83-255perform on/off operations to select one level of the divided voltage DV from the 256 levels of the divided voltages DV0to DV255which are outputs of the resistance-voltage dividing circuit70.

Operation of Driver IC of Exemplary Embodiment

A schematic operation of the driver IC10shown inFIG. 2is as follows.

When the driver IC receives display data for image display, and signals such as a control signal from the control IC30to the driver IC, the control signal is decoded by the command decoder13via the MPU interface11, and is transmitted to the display timing generation circuit21, the column-address circuit14, the line-address circuit15, the page-address circuit16, and the power supply circuit22via the bus12. The display data transmitted from the control IC30is sent to the MPU interface11, the bus12, and the I/O buffer17, and is stored in the display data RAM18that is assigned by an address selected by the column-address circuit14and the line-address circuit15.

Display data stored in the display data RAM18is latched at the display data latch circuit19and sent to the segment driver23. In the power supply circuit22, plural levels of the bias voltages BV are outputted from the bias voltage generation circuit50inFIG. 1. The output bias voltages BV are converted by a resistance-voltage dividing circuit and an amplifier circuit which are not shown, to different voltages, and sent to the segment driver23and the common driver25at a given timing in response to a display timing signal outputted from the display timing generation circuit21. Plural levels of voltages are transmitted from the segment driver23and the common driver25to the segment lines41-0to41-n and the common lines42-0to42-n in the display panel40and the segment lines41-0to41-n and the common lines42-0to42-n are driven, whereby a desired image display is performed.

Operation of Bias Voltage Generation Circuit of Exemplary Embodiment

FIG. 5is a table showing a relationship between the non-volatile memory52values and computation of the computing circuit60inFIG. 1.FIGS. 6 to 8respectively show first to third computing examples in the circuit ofFIG. 1. Further,FIG. 9is a graph showing the bias voltages BV which are outputted in correspondence with to the register values set at the circuit ofFIG. 1.

When the control IC30sets the 8-bit register value RV to the register51, as shown inFIG. 5, the computing circuit60performs an add-subtract operation using a complementary operation of 2 with respect to the 8-bit register value RV and the 8-bit correction value CV0to CV7stored in the non-volatile memory52, and outputs the 8-bit computing result S0to S7.

In the first computing example shown inFIG. 6, for example, when the correction value CV0to CV7of the non-volatile memory52is 00000000, the register value RV set at the register51are simply outputted as the computing result S0to S7. In the second computing example shown inFIG. 7, when the correction value CV0to CV7of the non-volatile memory52is 00010000, a value in which 16 is added (+16) to the register value RV set at the register51, is outputted as the computing result S0to S7. In the third computing example3shown inFIG. 8, when the correction value CV0to CV7of the non-volatile memory52is 11110000, a value in which 16 is subtracted (−16) from the register value RV set at the register51is outputted as the computing result S0to S7.

On the basis of the 8-bit computing result S0to S7, the selection circuit80selects one level of a divided voltage DV from the 256 levels of divided voltages DV0to DV255outputted from the resistance-voltage dividing circuit70, and outputs the selected divided voltage DV having a variation over 256 levels. The divided voltage DV is amplified by the amplifier circuit90, and the bias voltage BV having a variation over 256 levels is outputted as shown inFIG. 9.

Thus, although before the mass-production and shipping of the driver IC10, the non-volatile memory51is set to an empty state (blank state), since the correction value CV0to CV7can be stored (set) in the non-volatile memory52after completing the mass-production and shipping of the non-volatile memory51, the bias voltage BV to be outputted can easily be changed by the same register value RV being set at the register51.

The exemplary embodiment may realize the following operations (1) and (2):

By setting the correction value CV0to CV7in the non-volatile memory52in accordance with the display panel40to be used, a same register value RV can be set regardless of the display panel40, and the required bias voltage BV can be outputted simply and accurately from the bias voltage generation circuit50.

A particular operation which can be realized by the exemplary embodiment will be explained with reference toFIG. 11showing the conventional operation.

Driver IC manufacturing company A can improve its production efficiency because the same register value RV can be set regardless, of the type of the display panel40with which the driver IC10is to be combined. Diver IC manufacturing company A may mass-produce the driver IC10in which the non-volatile memory52is set to be blank state and may ship them to Panel module assembly company B.

Panel module assembly company B sets the correction value CV0to CV7at the blank non-volatile memory52in the purchased driver IC10on the basis of the characteristics of the display panel40with which the driver IC10is combined, and may sale the obtained panel modules to Panel module purchase company C.

Panel module purchase company C may purchase the panel modules in which the bias voltage values have been already corrected, thereby the complicated task in the conventional workflow of changing the register value for each display panels will be unnecessary.

Modifications

The invention is not limited to the exemplary embodiment described above, and various embodiments and modifications are possible. Examples thereof include, but are not limited to, the following (a) and (b):

The bias voltage generation circuit50inFIG. 1can be modified to another circuit configuration which is different from that shown in the drawings. For example, the amplifier circuit90may be omitted if it is unnecessary. Further, although the computation circuit60has been described as using the complementary computation of2, even when adding circuit or subtracting circuit may be used for the computation circuit60, substantially same operation can be achieved as in the exemplary embodiment

The circuit configuration of the driver IC10shown inFIG. 2may be modified to another which is different from that shown in the drawings. Further, the bias voltage generation circuit50according to the exemplary embodiment may be used in various circuits or devices other than the driver IC10.

As described above, in accordance with the exemplary embodiment, data value set at the data holding section can be corrected easily and precisely on the basis of correction value stored in the correction value storage section. Accordingly, it is possible to generate corrected variable bias voltages easily with a comparatively simple circuit configuration.

Following from the above description, it should be apparent to those of ordinary skill in the art that, while the methods and apparatuses herein described constitute exemplary embodiments of the present disclosure and that changes may be made to such embodiments without departing from the scope of the invention as defined by the claims. Additionally, it is to be understood that the invention is defined by the claims and it is not intended that any limitations or elements describing the exemplary embodiments set forth herein are to be incorporated into the interpretation of any claim element unless such limitation or element is explicitly stated. Likewise, it is to be understood that it is not necessary to meet any or all of the identified advantages or objects of the disclosure in order to fall within the scope of any claims, since the invention is defined by the claims and since inherent and/or unforeseen advantages of the present invention may exist even though they may not have been explicitly discussed herein.