Semiconductor apparatus and test system including the same

A semiconductor apparatus includes an input/output pad configured to exchange signals with an external device; a control pad configured to be inputted with a discharge signal from the external device; and a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2014-0126883, filed on Sep. 23, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor apparatus and a test system including the same, and more particularly, to a test system capable of simultaneously testing a plurality of semiconductor apparatuses.

2. Related Art

Integrated circuits, semiconductor-based electronic devices, are used for a variety of devices, including semiconductor memories. There are two types of semiconductor memories: a nonvolatile type and a volatile type.

In a nonvolatile memory device, stored data may be retained even in absence of power supply. Nonvolatile memory devices include flash memory devices, FeRAM (ferroelectric random access memory) devices, PCRAM (phase change random access memory) devices, MRAM (magnetic random access memory) devices, and ReRAM (resistive random access memory) devices.

In contrast, a volatile memory device requires power to maintain the stored data. The volatile memory device, which is generally faster, may be used in a data processing system as a buffer memory device, a cache memory device, or a working memory device. Volatile memory devices include SRAM (static random access memory) devices and DRAM (dynamic random access memory) devices.

SUMMARY

In an embodiment of the invention, a semiconductor apparatus may include an input/output pad configured to exchange signals with an external device. The semiconductor apparatus may also include a control pad configured to be inputted with a discharge signal from the external device. Further, the semiconductor apparatus may include a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.

In an embodiment of the invention, a semiconductor apparatus may include an input/output pad configured to exchange signals with an external device. The semiconductor apparatus may also include a control pad configured to be inputted with a control signal from the external device in a test mode. Further, the semiconductor apparatus may include a discharge signal output unit configured to output a discharge signal according to the control signal. The semiconductor apparatus may also include a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.

In an embodiment of the invention, a test system may include a plurality of semiconductor apparatuses. The test system may also include a test device configured to test the plurality of semiconductor apparatuses. Each of the plurality of semiconductor apparatuses comprise: an input/output pad configured to exchange signals with the test device; a control pad configured to be inputted with a discharge signal from the test device; and an electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a voltage supply line according to the discharge signal.

DETAILED DESCRIPTION

Hereinafter, a semiconductor apparatus and a test system including the same will be described below with reference to the accompanying drawings through various embodiments.

Referring toFIG. 1, a block diagram schematically illustrating a representation of an example of a semiconductor apparatus10in accordance with an embodiment is shown.

The semiconductor apparatus10may include an input/output pad100, a control pad200, and a first electrostatic protection unit300.

The input/output pad100may be configured to exchange signals with an external device. The input/output pad100may be inputted with a signal from the external device. The input/output pad100may output a signal to the external device. As will be described later, in the case where the signal inputted through the input/output pad100is within a normal voltage level range, the signal may be transmitted to an internal circuit500.

The control pad200may be configured to be inputted with a discharge signal DCH from the external device. The discharge signal DCH inputted through the control pad200may be transmitted to the first electrostatic protection unit300.

The first electrostatic protection unit300may be configured to form an electrostatic discharge path from the input/output pad100to a first voltage supply line11in response to the discharge signal DCH. The first electrostatic protection unit300may form a single directional current path from the input/output pad100to the first voltage supply line11in response to the discharge signal DCH. The first electrostatic protection unit300may also thereby remove the static electricity generated in the input/output pad100. The first electrostatic protection unit300may electrically decouple the input/output pad100and the first voltage supply line11in response to the discharge signal DCH which is disabled.

The first voltage supply line11may be configured to be supplied with a positive voltage, for example, a power supply voltage VCC, through a first voltage pad.

The semiconductor apparatus10may further include a second electrostatic protection unit400. The second electrostatic protection unit400may be configured to form an electrostatic discharge path from a second voltage supply line12to the input/output pad100. The second electrostatic protection unit400may form a single directional current path from the second voltage supply line12to the input/output pad100. The second electrostatic protection unit400may also thereby remove the static electricity generated in the input/output pad100.

The second voltage supply line12may be configured to be supplied with a ground voltage VSS through a second voltage pad.

The semiconductor apparatus10may further include the internal circuit500. The internal circuit500may be transferred with a signal from the input/output pad100. The internal circuit500may perform a predetermined internal operation in response to the transferred signal. The internal circuit500may transmit an internal signal generated as a result of performing the internal operation, to the input/output pad100, such that the internal signal may be outputted to the external device.

Referring toFIG. 2a, a circuit diagram illustrating in detail a representation of an embodiment300A of the first electrostatic protection unit300shown inFIG. 1is described.

The first electrostatic protection unit300A may include a transfer section310A electrically coupled between the input/output pad100and a transfer node TRND. The first electrostatic protection unit300A may also include a discharge control section320A electrically coupled between the transfer node TRND and the first voltage supply line11.

The transfer section310A may be configured to transfer the static electricity generated in the input/output pad100, to the transfer node TRND. The transfer section310A may form a single directional current path from the input/output pad100to the transfer node TRND according to the voltage between the input/output pad100and the transfer node TRND.

The discharge control section320A may be configured to discharge the static electricity transferred to the transfer node TRND, to the first voltage supply line11, in response to the discharge signal DCH. The discharge control section320A may discharge the static electricity from the transfer node TRND to the first voltage supply line11in response to the discharge signal DCH which is enabled. The first electrostatic protection unit300A may electrically decouple the transfer node TRND and the first voltage supply line11in response to the discharge signal DCH that is disabled. For example, the discharge signal DCH may be enabled to a logic high and may be disabled to a logic low.

The transfer section310A may include a first diode D1. The first diode D1has the anode which may be electrically coupled to the input/output pad100. The first diode D1also has the cathode which may be electrically coupled to the transfer node TRND.

The discharge control section320A may include a first NMOS transistor N1. The first NMOS transistor N1has the source and the drain which may be electrically coupled to the transfer node TRND and the first voltage supply line11, respectively. The first NMOS transistor N1also has the gate which may be applied with the discharge signal DCH.

Referring toFIG. 2b, a circuit diagram illustrating in detail a representation of an embodiment of300B of the first electrostatic protection unit300shown inFIG. 1is described.

The first electrostatic protection unit300B ofFIG. 2bmay be configured similarly to the first electrostatic protection unit300A ofFIG. 2aexcept that a transfer section3106includes a PMOS transistor P1instead of the first diode D1(seeFIG. 2a), and may operate similarly.

The first electrostatic protection unit300B may include the transfer section3106and a discharge control section320B. The transfer section3106may include the PMOS transistor P1. The PMOS transistor P1has the source and the drain which may be electrically coupled to a transfer node TRND and the input/output pad100, respectively. The PMOS transistor P1also has the gate which may be electrically coupled to the transfer node TRND. The discharge control section320B may include a second NMOS transistor N2.

Referring toFIG. 3a, a circuit diagram illustrating in detail a representation of an embodiment400A of the second electrostatic protection unit400shown inFIG. 1is described.

The second electrostatic protection unit400A may be configured to form an electrostatic discharge path from the second voltage supply line12to the input/output pad100. The second electrostatic protection unit400A may form a single directional current path from the second voltage supply line12to the input/output pad100according to the voltage between the second voltage supply line12and the input/output pad100.

The second electrostatic protection unit400A may include a second diode D2. The second diode D2has the anode which may be electrically coupled to the second voltage supply line12. The second diode D2also has the cathode which may be electrically coupled to the input/output pad100.

Referring toFIG. 3b, a circuit diagram illustrating in detail a representation of an embodiment400B of the second electrostatic protection unit400shown inFIG. 1is described.

The second electrostatic protection unit400B ofFIG. 3bmay be configured similarly to the second electrostatic protection unit400A ofFIG. 3aexcept that it includes a third NMOS transistor N3instead of the second diode D2(seeFIG. 3a), and may operate similarly.

The second electrostatic protection unit400B may include the third NMOS transistor N3. The third NMOS transistor N3has the source and the drain which may be electrically coupled to the input/output pad100and the second voltage supply line12. The third NMOS transistor N3also has the gate which may be electrically coupled to the second voltage supply line12.

Hereafter, a method to operate the semiconductor apparatus10in accordance with an embodiment will be described in detail with reference toFIGS. 1, 2aand3a.

The operations of the semiconductor apparatus10may be divided into a first case where the first electrostatic protection unit300is activated in response to the discharge signal DCH which is enabled, to form the electrostatic discharge path from the input/output pad100to the first voltage supply line11. The operations of the semiconductor apparatus10may include a second case where the first electrostatic protection unit300is deactivated in response to the discharge signal DCH which is disabled. The discharge signal DCH may be inputted in an enabled state through the control pad200according to whether the semiconductor apparatus10is supplied with a voltage through the first voltage supply line11.

First, the operation of the semiconductor apparatus10in the case where the first electrostatic protection unit300is activated in response to the enabled discharge signal DCH is described below.

The semiconductor apparatus10may be supplied with the power supply voltage VCC through the first voltage supply line11from the external device. The semiconductor apparatus10may be supplied with the ground voltage VSS through the second voltage supply line12. The semiconductor apparatus10may be inputted with the enabled discharge signal DCH through the control pad200from the external device. The semiconductor apparatus10may exchange signals through the input/output pad100with the external device.

The first electrostatic protection unit300may form the electrostatic discharge path from the input/output pad100to the first voltage supply line11in response to the enabled discharge signal DCH.

More specifically, the first NMOS transistor N1ofFIG. 2amay electrically couple the transfer node TRND and the first voltage supply line11in response to the discharge signal DCH which is enabled to the logic high. The first diode D1may transfer the static electricity generated in the input/output pad100, to the transfer node TRND. For example, in the case where the level of the signal transmitted between the input/output pad100and the internal circuit500is equal to or lower than the level of the power supply voltage VCC, that is, in the case where static electricity is not generated, the first diode D1may be turned off since it is a state in which a reverse bias voltage is applied. The first diode D1may be turned on in the case where a voltage with a level higher than the power supply voltage VCC is applied to the input/output pad100, that is, in the case where static electricity is generated, and may then transfer the static electricity to the transfer node TRND. The static electricity transferred to the transfer node TRND may be discharged to the first voltage supply line11through the first NMOS transistor N1.

As a result, the internal circuit500may accordingly be protected from static electricity.

The second electrostatic protection unit400may form the electrostatic discharge path from the second voltage supply line12to the input/output pad100.

In detail, where the level of the signal transmitted between the input/output pad100and the internal circuit500is equal to or higher than the level of the ground voltage VSS, that is, in the case where static electricity is not generated, the second diode D2ofFIG. 3amay be turned off since it is a state in which a reverse bias voltage is applied. The second diode D2may be turned on where a voltage with a level lower than the ground voltage VSS is applied to the input/output pad100, that is, in the case where static electricity is generated. The static electricity may be discharged through the second diode D2.

Accordingly, the internal circuit500may be protected from static electricity.

Second, the operation of the semiconductor apparatus10where the first electrostatic protection unit300is deactivated in response to the disabled discharge signal DCH is as follows.

The semiconductor apparatus10may not be supplied with the power supply voltage VCC through the first voltage supply line11from the external device. In this case, the semiconductor apparatus10may be inputted with the disabled discharge signal DCH through the control pad200from the external device.

The first electrostatic protection unit300may block the electrostatic discharge path from the input/output pad100to the first voltage supply line11in response to the disabled discharge signal DCH.

More specifically, the first NMOS transistor N1ofFIG. 2amay electrically decouple the transfer node TRND and the first voltage supply line11in response to the discharge signal DCH which is disabled to the logic low. Since the first NMOS transistor N1is turned off, it is possible to prevent a forward bias voltage from being applied to the first diode D1as the power supply voltage VCC is not applied to the first voltage supply line11. In this instance, discharge from the input/output pad100to the first voltage supply line11may be prevented.

Referring toFIG. 4, a block diagram schematically illustrating a representation of an example of a test system1000in accordance with an embodiment is described.

The test system1000may include a first semiconductor apparatus10A, a second semiconductor apparatus10B, and a test device1100.

Each of the first and second semiconductor apparatuses10A and10B may be configured and operate in substantially the same manner as the semiconductor apparatus10ofFIG. 1. The respective first and second semiconductor apparatuses10A and10B may include input/output pads100A and100B for being applied with a test signal TEST. The first and second semiconductor apparatuses10A and10B may also include control pads200A and200B for being respectively applied with discharge signals DCH1and DCH2. Further, the first and second semiconductor apparatuses10A and10B may include voltage pads600A and600B for being supplied with a power supply voltage VCC. The voltage pads600A and600B may be electrically coupled with the first voltage supply line11shown inFIG. 1. The first and second semiconductor apparatuses10A and10B electrically coupled to the test device1100may be in a test mode.

The test device1100may include a probe card. The test device1100may be electrically coupled to the input/output pads100A and100B of the first and second semiconductor apparatuses10A and10B through a test pin1110of the probe card. The first and second semiconductor apparatuses10A and10B may share the test pin1110. Accordingly, the test device1100may simultaneously test the first and second semiconductor apparatuses10A and10B.

The test device1100may supply the power supply voltage VCC to the first and second semiconductor apparatuses10A and10B through the voltage pads600A and600B. The test device1100may apply the discharge signals DCH1and DCH2to the first and second semiconductor apparatuses10A and10B through the control pads200A and200B, respectively. The test device1100may apply the test signal TEST to the first and second semiconductor apparatuses10A and10B through the input/output pads100A and100B.

The test device1100may determine whether the first and second semiconductor apparatuses10A and10B have failed or not. The test device1100may also interrupt the supply of the power supply voltage VCC to a failed semiconductor apparatus. The test device1100may retain the supply of the power supply voltage VCC to a remaining semiconductor apparatus.

The test device1100may input a discharge signal in an enabled state to each of the first and second semiconductor apparatuses10A and10B according to whether the power supply voltage VCC is supplied or not. For example, the test device1100may apply a disabled discharge signal to the semiconductor apparatus to which the supply of the power supply voltage VCC is interrupted, that is, the semiconductor apparatus determined as a fail. The test device1100may apply an enabled discharge signal to the remaining semiconductor apparatus to which the power supply voltage VCC is supplied.

As a result, when the first and second semiconductor apparatuses10A and10B are simultaneously tested by sharing the test pin1110, in the semiconductor apparatus which is determined as a fail and to which the supply of the power supply voltage VCC is thus interrupted, discharge from an input/output pad to the first voltage supply line11is blocked in response to the disabled discharge signal. Further, an influence may not be exerted on the remaining semiconductor apparatus which is being tested.

While it is shown that the test system1000ofFIG. 4simultaneously tests two semiconductor apparatuses, it is to be noted that the number of semiconductor apparatuses to be simultaneously tested is not limited to such. In addition, while it is shown inFIG. 4that two semiconductor apparatuses share the test pin1110, it is to be noted that the number of semiconductor apparatuses which share the test pin1110is not limited to such.

Referring toFIG. 5, a representation of an example of a flow chart to assist in the explanation of a test method in the test system1000shown inFIG. 4is described.

Hereinbelow, the test method in the test system1000will be described in detail with reference toFIGS. 4 and 5.

In step S110, the test device1100may start a test for the first and second semiconductor apparatuses10A and10B. The first and second semiconductor apparatuses10A and10B may share the test pin1110through the input/output pads100A and100B.

In step S120, the test device1100may supply the power supply voltage VCC to the first and second semiconductor apparatuses10A and10B.

In step S130, the test device1100may determine a certain semiconductor apparatus as a fail while performing the test. For example, the test device1100may determine the first semiconductor apparatus10A as a fail.

In step S140, the test device1100may interrupt the supply of the power supply voltage VCC to the failed semiconductor apparatus. For example, the test device1100may interrupt the supply of the power supply voltage VCC to the first semiconductor apparatus10A which is determined as a fail (see the reference symbol OFF inFIG. 4). The test device1100may retain the supply of the power supply voltage VCC to the second semiconductor apparatus10B (see the reference symbol ON inFIG. 4).

In step S150, the test device1100may apply a disabled discharge signal to the failed semiconductor apparatus to which the supply of the power supply voltage VCC is interrupted. For instance, the test device1100may apply the discharge signal DCH1that is disabled to the first semiconductor apparatus10A. The first electrostatic protection unit300of the first semiconductor apparatus10A may block the electrostatic discharge path from the input/output pad100A to the first voltage supply line11in response to the disabled discharge signal DCH1.

In step S160, the test device1100may apply an enabled discharge signal to a remaining semiconductor apparatus except the failed semiconductor apparatus. For instance, the test device1100may apply the discharge signal DCH2which is enabled to the second semiconductor apparatus10B. The first electrostatic protection unit300of the second semiconductor apparatus10B may form the electrostatic discharge path from the input/output pad100B to the first voltage supply line11in response to the enabled discharge signal DCH2.

In step S170, the test device1100may apply the test signal TEST through the test pin1110. The test signal TEST may be inputted to the first and second semiconductor apparatuses10A and10B through the input/output pads100A and100B. For example, even though the test signal TEST is applied through the test pin1110shared by the first semiconductor apparatus10A determined as a fail and the second semiconductor apparatus10B being continuously tested, the voltage level of the test signal TEST may be normally retained because a current path in the first semiconductor apparatus10A determined as a fail is blocked. Therefore, the test device1100may normally perform the test for the second semiconductor apparatus10B.

In summary, the test system1000may efficiently test simultaneously a plurality of semiconductor apparatuses by electrically coupling the plurality of semiconductor apparatuses to share the test pin1110. The test system1000may interrupt the supply of a voltage to a semiconductor apparatus determined as a fail while performing a test. The test system1000also prevents discharge through the first electrostatic protection unit of the corresponding failed semiconductor apparatus from the test pin1110, whereby it is possible to prevent the voltage level of the test signal TEST applied from the test pin1110, from dropping. Accordingly, the test system1000may normally perform the test for a remaining semiconductor apparatus.

A semiconductor apparatus, which is determined as a pass as a test mode is ended and operates in a normal mode, may be applied with an enabled discharge signal through a control pad. In addition, the first electrostatic protection unit thereof may be retained in an activated state and may effectively form an electrostatic discharge path.

Referring toFIG. 6, a block diagram schematically illustrating a representation of an example of a semiconductor apparatus20in accordance with an embodiment is described. InFIG. 6, the same reference numerals as inFIG. 1will be used to refer to substantially the same component elements as the component elements of the semiconductor apparatus10described above with reference toFIG. 1. In addition, detailed descriptions for the corresponding component elements will be omitted herein.

The semiconductor apparatus20may include an input/output pad100, a control pad700, a discharge signal output unit800, a first electrostatic protection unit300, a second electrostatic protection unit400, and an internal circuit500.

The control pad700may be configured to transfer a control signal CTR inputted from an external device, to the discharge signal output unit800, in a test mode in which a test for the semiconductor apparatus20is performed. In the test mode, the control signal CTR may be enabled according to whether a voltage is supplied to a first voltage supply line11or not. In the test mode, the control signal CTR may correspond to the discharge signal DCH ofFIG. 1. The control pad700may be floated when the test mode is ended.

The discharge signal output unit800may be configured to output a discharge signal DCH in response to the control signal CTR in the test mode. For example, the discharge signal output unit800may output the discharge signal DCH which is enabled according to the control signal CTR which is enabled in the test mode. The discharge signal output unit800may output the discharge signal DCH which is disabled according to the control signal CTR which is disabled in the test mode. The discharge signal output unit800may retain the level of the discharge signal DCH in an enabled state when the test mode is ended. More specifically, the discharge signal output unit800may output the enabled discharge signal DCH in the case where the control pad700is floated.

Accordingly, the semiconductor apparatus20ofFIG. 6may use the control pad700only in the test mode unlike the semiconductor apparatus10ofFIG. 1. The discharge signal output unit800may output the discharge signal DCH to activate the first electrostatic protection unit300in response to the control signal CTR in the test mode. The control pad700may be floated when the test mode is ended. For example, the control pad700may be floated where the semiconductor apparatus20is in a state in which it passes the test and is placed on the market. In this case, the discharge signal output unit800may output the enabled discharge signal DCH by itself such that the first electrostatic protection unit300normally retains an activated state.

As is apparent from the above descriptions, the test system in accordance with an embodiment may efficiently test simultaneously a plurality of semiconductor apparatuses.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor apparatus and the test system including the same described should not be limited based on the described embodiments.