Power control circuit, semiconductor device and transceiver circuit using the same

There is provided a power control circuit having a stable high-speed operation, and a semiconductor device and a transceiver circuit using it. The power control circuit controls the gain of an amplifier so that power outputted from the amplifier reaches a desired value according to a digital control signal. The power control circuit includes a digital feedback loop which converts a detected signal obtained by detecting a value of the output power of the amplifier to a digital signal, determines a differential between the digital signal and the digital control signal, converts the differential to an analog signal and outputs a first feedback signal, an analog feedback loop which outputs a high frequency element corresponding to a differential between an analog signal to which the digital control signal is converted and the detected signal, as a second feedback signal, and an adder which determines the sum of the first and the second feedback signal and outputs a gain control signal for controlling the gain of the amplifier.

CLAIM OF PRIORITY

The present patent application claims priority from Japanese application JP 2004-337266 filed on Nov. 22, 2004, the content of which is hereby incorporated by reference into this application.

FIELD OF THE INVENTION

The present invention relates to a technique which controls output power at a mobile wireless communication terminal or wireless communication devices such as a transmitter of a base station for wireless communication, etc., and particularly to a power control circuit suitable for application to wireless communication devices adapted to a plurality of frequency bands and a plurality of systems.

BACKGROUND OF THE INVENTION

A mobile communication system typified by a cellular phone has been increased in penetration on a global scale. Several communication systems have been used according to the locality. As one of important techniques used in the mobile communication system, there is known a technique called APC (Auto Power Control) which controls transmitted power of a terminal according to received power at a terminal and a base station. A first reason why APC is required, resides in a reduction in power consumption. When the terminal is located near the base station, the transmitted power of the terminal is lowered to make it possible to achieve a reduction in power consumption of the terminal as compared with the case in which transmitted power is constant. A second reason is a near-far problem at a CDMA (Code Division Multiple Access) system.

In the CDMA, a plurality of terminals perform spread spectrum modulation on signals according to a spread spectrum using codes different from one another and transmit them. Thus, the same frequency band can be shared among the plurality of terminals. When, for example, a terminal B that exists at a distance far away from a base station A and a terminal C that exists at a distance near from the base station A are considered, a signal (desired wave) from the terminal B is subjected to level interference due to a signal (undesired wave) of the terminal C, thus resulting in the difficulty of accurate reception. In order to solve this problem, it is essential to precisely control power transmitted by each terminal and keep received power at the base station constant.

As an example of a power control circuit for realizing APC, an example that detects part of output power of a transmitted power amplifier and controls the transmitted power amplifier in such a manner that the result of detection reaches an ordered power level from a base station has been disclosed in a patent document 1: Japanese Patent Laid-Open No. H5(1993)-291854 (Page 3-4, FIG. 1). As another example, an example that detects part of output power of a power amplifier, and controls an available attenuator for changing an input level of the power amplifier to thereby sample and hold a control voltage of the available attenuator when the result of detection reaches a desired value has been disclosed in a patent document 2: Japanese Patent Laid-Open No. H8 (1996)-274560 (Page 5-6, FIG. 1). As a further example, an example has been disclosed in a patent document 3: Japanese Patent Laid-Open No. 2004-7443 (Page 11, FIG. 1), wherein in a wireless communication equipment having a phase control loop for controlling the phase of a carrier of a transmitted signal and an amplitude control loop for controlling output amplitude of a power amplifier circuit, an available gain amplifier circuit is disposed at the midpoint of a feedback circuit of the amplitude control loop, and the gain of the same amplifier circuit is controlled by a digital circuit to thereby control the output power of the power amplifier. As a still further example, an example has been disclosed in a patent document 4: Japanese Patent Laid-Open No. 2000-228646 (Page 4-5, FIG. 1), wherein two available gain devices are disposed ahead of a power amplifier section, and the result of detection of power outputted from the power amplifier section results in a value corresponding to control from a base station and the two available gain devices are controlled such that a change in phase does not occur. As a still further example, an example that detects part of output power of a transmitted power amplifier and controls the transmitted power amplifier by a digital circuit such that the result of detection complies with instructions given from a base station has been disclosed in a patent document 5: Japanese Patent Laid-Open No. H8 (1996)-274559 (Page 3, FIG. 3).

SUMMARY OF THE INVENTION

In the technique disclosed in the patent document 1, a feedback circuit is susceptible to temperature changes and a variation in power supply because it is constituted of an analog circuit, and hence stability and accuracy thereof become insufficient unavoidably. Further, since only closed loop control is made, the action of suppressing a change (envelope) in amplitude value due to modulation is continued even though the average value of the amplitude of a signal transmitted within a feedback circuit converges, where the output signal of the transmitted power amplifier is of a signal with amplitude modulation. Therefore, the suppression of this change is fed back to the transmitted power amplifier as noise. As a result, it is not possible to avoid degradation of the output signal of the transmitted power amplifier. Thus, there is a limit to a communication system to which the present technique is applicable.

In the technique disclosed in the patent document 2, a sample hold leak (phenomenon that varies in voltage for holding a capacitor due to the leak of an electrical charge of a capacitor constituting a sample and hold circuit) occurs because the sample and hold circuit is similarly realized by an analog circuit, so that it is difficult to hold the output signal of the power amplifier at a constant value.

In contrast, the techniques disclosed in the patent documents 4 and 5 are capable of controlling the relative value of the output power of the power amplifier in detail because digital signal processing is used. When, however, high-speed power control in a burst mode such as GSM (Global System for Mobile Communication) or the like being in widespread use in Europe is performed, there is a possibility that a feedback circuit will be brought into in stabilization or oscillations because the phase of a feedback signal corresponding to a clock frequency is turned 180° due to a clock delay contained in the digital signal processing.

Now, a plurality of communication systems exist in mobile communication typified by a cellular phone. For example, a W-CDMA (Wide-band Code Division Multiple Access) corresponding to a wireless communication system for 3rd generation having come into service in recent years is known in Europe in addition to above GSN being in widespread use as a wireless communication system for 2nd generation, and EDGE (Enhanced Data rates for GSM Evolution) improved in data communication speed or rate of GSM. Further, cdmalx corresponding to the wireless communication system for 3rd generation is in widespread use in North America in addition to a PCS (Personal Communication System) corresponding to the wireless communication system for 2nd generation.

Further, a plurality of frequency bands are used in the respective communication systems. For example, an 800 to 900 MHz band called “low band” and an 1800 to 1900 MHz band called “high band” are used in GSM.

Thus, since the plurality of communication systems (modes) and the plurality of frequency bands become existent in mixed form in the same region, a cellular phone needs to be brought into multi-band/multi-mode form. For instance, a cellular phone adapted to GSM/EDGE/W-CDMA is required in Europe. Even though the cellular phone is brought into multi-band/multi-mode form, it is not allowed to become large in size and high in cost. It is needless to say that it is also essential to bring parts and circuits constituting the cellular phone into multi-band/multi-mode form if reductions in size and cost of the cellular phone are taken into consideration. That is, even the power control circuit for the above APC needs to be adapted to multi-band/multi-mode form.

On the other hand, when, for example, the sharing of GSM in which a channel band width is 400 kHz and W-CDMA in which a channel band width is 5 MHz is taken into consideration, the channel band widths are widely different from each other in the technique disclosed in the patent document 3. Therefore, circuit design adapted to both systems becomes difficult unavoidably.

An object of the present invention is to provide a power control circuit having a stable high-speed operation or provide a semiconductor device using the same power control circuit or provide a transceiver circuit using the same power control circuit.

According to one aspect of the present invention, for attaining the above object, there is provided a power control circuit that controls a gain of an amplifier in such a manner that output power of the amplifier reaches a desired power value according to a power control signal, comprising: a digital feedback loop which converts a detected signal obtained by detecting a power value of the output power of the amplifier to a digital signal, determines a first differential between the detected signal converted to the digital signal and the power control signal, and converts the first differential to a first analog signal and outputs a first feedback signal; an analog feedback loop which outputs a high frequency element of a second differential between the power control signal converted to a second analog signal and the detected signal as a second feedback signal; and an adder which determines the sum of the first feedback signal and the second feedback signal and outputs a gain control signal for controlling the gain of the amplifier. Since the analog feedback loop does not include a delay based on digital signal processing, it is capable of high-speed operation. Thus, the operation of allowing the power value to converge constantly is principally performed by the digital feedback loop, and the second feedback signal corresponding to the high frequency element of the feedback signal is generated by the analog feedback loop capable of high-speed operation. Therefore, stabilization at the high-speed operation of the power control circuit is enabled. Accordingly, the power control circuit of the present invention can be shared among a plurality of frequency bands and a plurality of systems.

According to another aspect of the present invention, for achieving the above object, there is provided a semiconductor device comprising: a circuit block including, a receiver circuit which amplifies a received first signal; a first frequency conversion circuit which converts the frequency of the first signal of post-amplification outputted from the receiver circuit to output a second signal; a second frequency conversion circuit which inputs a third signal to be transmitted and converts the frequency of the third signal to output a fourth signal; a first amplifier which amplifies the fourth signal outputted from the second frequency conversion circuit and whose gain is controlled by a second power control signal; and the above-mentioned power control circuit which controls output power of an external second amplifier amplifying the fourth signal by use of a first power control signal in such a manner that the output power reaches a desired power value, wherein the circuit block is formed over the same semiconductor substrate. The semiconductor device having the above configuration is equipped with the power control circuit which can be shared among a plurality of frequency bands and a plurality of systems because it is capable of stable high-speed operation. Thus, the use of the semiconductor device of the present invention allows realization of reductions in size and cost of a communication device such as a multi-band/multi-mode-capable cellular phone or the like.

According to a further aspect of the present invention, for attaining the above object, there is provided a transceiver circuit comprising: a circuit block including, a first receiver circuit which amplifies a 1 ath signal of a first communication system, which is received by an antenna; a second receiver circuit which amplifies a 1 bth signal of a second communication system, which is received by the antenna; a first frequency conversion circuit which converts the frequency of the 1 ath or 1 bth signals of post-amplification outputted from the first or second receiver circuits to thereby output a second signal; a second frequency conversion circuit which inputs a 3 ath signal to be transmitted of the first communication system or a 3 bth signal to be transmitted of the second communication system and executes frequency conversion to the same to thereby output a fourth signal; a first amplifier which amplifies the fourth signal outputted from the second frequency conversion circuit and whose gain is controlled by a second power control signal; a second amplifier which power-amplifies the fourth signal of post-amplification outputted from the first amplifier; a detector which detects a power value of an output signal of the second amplifier to output a detected signal; and the above-mentioned power control circuit which controls an output power of the second amplifier by use of a first power control signal in such a manner that the output power reaches a desired power value. The transceiver circuit having the above configuration is equipped with the power control circuit capable of being shared for a plurality of frequency bands and a plurality of systems because it is capable of stable high-speed operation. Accordingly, the use of the transceiver circuit of the present invention allows realization of reductions in size and cost of a communication device such as a multi-band/multi-mode-adaptable cellular phone or the like.

These and other objects and many of the attendant advantages of the invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A power control circuit according to the present invention, a semiconductor device and a transceiver circuit using the same will hereinafter be described in detail by reference to several preferred embodiments illustrated in the drawings. Incidentally, components each having the same or similar function are given the same reference numerals in all drawings for describing the embodiments and their repetitive descriptions will therefore be omitted.

First Preferred Embodiment

A first embodiment illustrative of a power control circuit of the present invention is shown inFIG. 1. As one example, a case is indicated, in which the present invention is applied to a cellular phone appropriate to GSM and W-CDMA, in order to simply describe the structure, operation and effects of the power control circuit according to the present embodiment.FIG. 1is a circuit configuration diagram showing a transmitter block of a cellular phone equipped with the power control circuit according to the present embodiment.

InFIG. 1, reference numeral10indicates a base band signal processor (BB), reference numeral20aindicates a frequency conversion circuit (MIX), reference numeral30indicates an available gain amplifier, reference numeral40aindicates a power amplifier, reference numeral50aindicates a directional coupler, reference numeral60aindicates a detector (DET), reference numeral70indicates an analog to digital (A/D) converter, reference numerals80aand80bindicate digital to analog (D/A) converters, reference numerals90aand90bindicate comparators, reference numeral100indicates an adder, reference numeral110indicates a high pass filter, reference numeral120indicates a front-end circuit (FE), and reference numeral130aindicates an antenna, respectively. The front-end circuit120principally comprises high frequency parts such as an antenna switch, a duplexer or diplexer, etc.

In the above configuration, reference numeral200indicates a digital feedback loop comprising the A/D converter70, the comparator (first comparator)90aand the D/A converter (first D/A converter)80a. Reference numeral210indicates an analog feedback loop comprising the D/A converter (second D/A converter)80b, the comparator (second comparator)90band the high pass filter110. Further, reference numeral220indicates a power control circuit which comprises the digital feedback loop200, the analog feedback loop210and the adder100.

The operation of the transmitter block of the cellular phone equipped with the power control circuit220according to the present embodiment will first be described. Upon the respective modes of GSM and W-CDMA, the frequency of a transmitted signal (third signal) of the base band signal processor10is converted to a desired frequency at the frequency conversion circuit20a, followed by being amplified to desired power by the available gain amplifier30. Further, it is converted to desired power by the power amplifier40a, which in turn is transmitted from the antenna130avia the directional coupler50aand the front-end circuit120. The base band signal processor10further outputs a digital power control signal (power control signal or first power control signal) detected from a received signal sent from a base station (not shown).

On the other hand, part of the output signal of the power amplifier40a, which has been taken out by the directional coupler50a, is inputted to the detector60a, where it is converted to a voltage value. Although a half wave detector may preferably be convenient for the detector60a, a full wave detector may be used.

The power control circuit220is used when the GSM mode is performed. Part of the output signal of the detector60ais converted to a digital signal by the A/D converter70, which in turn is inputted to the comparator90a. Further, the part of the output signal of the detector60ais inputted to the comparator90b.

The comparator90aoutputs a differential between the output signal of the A/D converter70and the power control signal outputted from the base band signal processor10. The output signal of the comparator90ais converted to an analog signal by the D/A converter80a, which results in a first feedback signal, after which it is inputted to the adder100. On the other hand, the comparator90boutputs a differential between the part of the output signal of the detector60aand the power control signal outputted from the base band signal processor10, which has been converted to an analog signal through the D/A converter80b. The output signal of the comparator90bis brought to a second feedback signal through the high pass filter110, which in turn is inputted to the adder100. The adder100outputs the sum of the first feedback signal outputted from the D/A converter80aand the second feedback signal outputted from the high pass filter110. The output signal of the adder100is applied to a gain control terminal of the power amplifier40aas a gain control signal (Vapc). With the above circuit configuration, a power value of the output signal of the power amplifier40ais controlled so as to converge on a value corresponding to the power control signal outputted from the base band signal processor10.

According to the power control circuit of the present embodiment shown inFIG. 1, since the analog feedback loop210is equipped with the high pass filter110, the signal outputted from the analog feedback loop210has a high frequency element alone. Further, since the analog feedback loop210does not include a delay produced in the case of execution of digital signal processing, a high speed operation is enabled. Thus, since the operation of allowing the power value to converge constantly is principally performed by the digital feedback loop200, and the high frequency element of each signal in the power control circuit220is fed back by the analog feedback loop210capable of high-speed operation, stabilization of the power control circuit220is enabled.

Incidentally, when the transmitter block performs the W-CDMA mode, a signal outputted from the detector60ais converted to a digital signal by the A/D converter70, which in turn is inputted to the base band signal processor10. In the case of W-CDMA in this way, the A/D converter70of the power control circuit220is shared for GSM.

The base band signal processor10compares the output signal of the A/D converter70and a power control signal detected by a received signal from the corresponding base station and controls the power value of an output signal of the available gain amplifier30in such a manner that the power value of an output signal of the power amplifier40is brought to a desired value. Since the dynamic range of the power value of a transmitted signal required in W-CDMA is very large like about 70 dB, the power value of an input signal is varied in a state in which a bias point of the power amplifier40ais held constant, where the W-CDMA mode is performed, whereby the power value of the output signal is determined. With the above circuit configuration, the power value of the output signal of the power amplifier40ais thus controlled so as to converge on a value corresponding to a power control signal (second power control signal) outputted from the base band signal processor10. Since the base band signal processor10generates a power control signal for the available gain amplifier30by digital signal processing in the case of the W-CDMA mode, detailed power control is enabled.

Second Preferred Embodiment

A second embodiment illustrative of a power control circuit of the present invention is shown inFIG. 2A.FIG. 2Ais a circuit configuration diagram showing a transmitter block of a cellular phone equipped with the power control circuit according to the present embodiment. The cellular phone, to which the present invention is applied, corresponds even to EDGE in addition to GSM and W-CDMA. Thus, the power control circuit according to the present embodiment is applied to GSM and EDGE modes and serves as a multi-mode power control circuit.

When the transmitter block performs the EDGE mode, its basic operation is similar to the GSM mode in the first embodiment. Points different from the GSM mode will next be explained.

FIG. 3is a graph showing time responses of a transmitted signal power value transmitted from an antenna130aand normalized time masks where GSM and EDGE modes are performed.

InFIG. 3, the horizontal axis indicates time, and the vertical axis indicates power value. Reference numeral300aindicates transmitted signal power transmitted from the antenna130ain the case of the GSM mode, reference numerals310aand310bindicate time masks which define the transmitted signal power transmitted from the antenna130ain the case of the GSM mode, reference numeral400aindicates one slot in the case of the GSM mode, reference numeral410aindicates ramp up, reference numeral420aindicates a burst, and reference numeral430aindicates ramp down, respectively. Reference numeral300bindicates transmitted signal power transmitted from the antenna130ain the case of the EDGE mode, reference numerals310cand310dindicate time masks which define the transmitted signal power transmitted from the antenna130ain the case of the EDGE mode, reference numeral400bindicates one slot in the case of the EDGE mode, reference numeral410bindicates ramp up, reference numeral420bindicates a burst, and reference numeral430bindicates ramp down, respectively. Further, reference numerals440aand440brespectively indicate buffer periods set to the beginning and end of the burst420bin the case of the EDGE mode.

When the GSM mode is performed as shown inFIG. 3, the signal transmitted from the antenna130ais constant power at the burst420a. Thus, since the power of an output signal of a power amplifier40ais also constant, the power control circuit220is capable of closed loop operation at all times during one slot400a.

On the other hand, when the EDGE mode is performed, the transmitted signal sent out from the antenna130ais being amplitude-modulated during a modulated signal output period450excluding the buffer periods440aand440bof the burst420b, and hence the envelope of the transmitted signal changes. Therefore, a sample hold function during the modulated signal output period450is required. Owing to a gain control voltage held at a constant value during this period, the gain of the power amplifier40ais kept constant regardless of the change in the envelope of the transmitted signal.

InFIG. 2A, reference numerals140a,140band140crespectively indicate sample and hold circuits disposed on the output side of a detector60a, the input side of an A/D converter80band the input side of the A/D converter80a(they corresponds to first, second and third sample and hold circuits respectively).

The operation of the sample hold function in the EDGE mode of the present embodiment will be explained usingFIG. 2A. The sample and hold circuits140athrough140care first turned off at the ramp up410b.

Now, in the present specification, the turning off of the sample and hold circuit140indicates that a switch S1shown inFIG. 2Bis held on or a switch S2shown inFIG. 2Cis being connected to the side of a terminal a. The turning on of the sample and hold circuit140indicates that the switch S1is held off or the switch S2is being connected to the side of a terminal b.

InFIG. 2B, BA1and BA2indicate buffer amplifiers respectively, and C1indicates a capacitor. When S1is ON(i.e., the sample and hold circuit140is turned OFF), C1is charged so that the sample and hold circuit140outputs an input signal as it is (sample state). When S1is OFF (i.e., the sample and hold circuit140is turned ON), a signal corresponding to the amount of charge of the capacitor C1is supplied to the buffer amplifier BA2(hold state), whereby a sample hold function is realized. On the other hand, a sample and hold circuit body1400is of, for example, a one clock delay circuit inFIG. 2C. When S2is connected to the side of a terminal a (i.e., the sample and hold circuit140is turned OFF), the sample and hold circuit140outputs an input signal as it is (sample state). When S2is connected to the side of a terminal b (i.e., the sample and hold circuit140is turned ON), the sample and hold circuit140always outputs a signal preceding one clock inputted to the sample and hold circuit body1400(hold state), whereby a sample hold function is realized.

Thus, when the sample and hold circuits140athrough140care turned OFF,FIG. 2Abecomes similar toFIG. 1, and the power control circuit220is closed loop operated in a manner similar to the GSM mode in such a manner that the power of the output signal of the power amplifier40aconverges on a desired value. Next, the sample and hold circuits140athrough140care simultaneously turned ON during the buffer period440aset to the beginning of the burst420bso that signal values (voltage values or power value) at the respective sample and hold circuits are memorized and held. Further, the respective sample and hold circuits140athrough140crespectively output their memorized and held signal values during the modulated signal output period450. Furthermore, the power value of the output signal of the power amplifier40ais restored to a value equal to the interval of the buffer period440aduring the buffer period440bset to the end of the burst420b(the input signal of the power amplifier40ais restored to a constant amplitude value). Thereafter, the sample and hold circuits140athrough140care simultaneously turned OFF. Finally, the sample and hold circuits140athrough140care turned OFF at the ramp down430b, so that the power control circuit220is closed-loop operated in a manner similar to the GSM mode in such a manner that the power value of the output signal of the power amplifier40aconverges on a desired value.

According to the present embodiment, since the sample and hold circuits140band140care constituted of digital circuits, there is no problem about a sample hold leak. While the sample and hold circuit140ais configured of an analog circuit, any of the detector60a, comparator90band A/D converter70is operated with being inputted with the voltage, and a current flowing into a system is small. Therefore, the deterioration of a sample hold function due to the sample hold leak is low. Thus, the sample hold function substantially free of the sample hold leak can be realized during the modulated signal output period450in the EDGE mode owing to the above circuit configuration.

Incidentally, by turning OFF the adder100at the ramp down430b, the power amplifier40aperforms closed-loop operation, whereby the power value of the output signal of the power amplifier40amay be reduced to a desired value. Alternatively, by turning OFF the D/A converters80aand80b, the power amplifier40aperforms open-loop control, whereby the power value may be reduced to a desired power value. Since there is no need to consider spurious generation due to a differential in sample holding value at switching from a sample holding state to a closed loop at the buffer period440bin this case, design can easily be performed.

As an alternative to the above, the closed loop operation may be applied during the first half of the ramp down430band the open loop operation may be selected during the latter half thereof. In this case, the open loop operation makes it possible to allow the power value to converge on a desired value even in the case where the power value does not converge on the desired value due to a loop gain reduction caused by non-linearity of the power amplifier40a.

Incidentally, loop filters may suitably be disposed depending upon the characteristic of a closed loop. An example configured in this way is shown inFIG. 4. Loop filters150a,150band150care respectively disposed on the output sides of an adder100, an A/D converter80aand a comparator90a.

Furthermore, when the GSM or EDGE mode is performed, the multi-mode power control circuit according to the present embodiment adjusts the gain control voltage of the power amplifier40ato control the power value of the output signal of the power amplifier40a. However, the power value of an output signal from a frequency conversion circuit20aor an available gain amplifier30may be adjusted as needed. In this case, such a configuration as to adjust the power value of the output signal from the frequency conversion circuit20aor the available gain amplifier30is newly required. Since, however, the gain of the power amplifier40amay be fixed, low power consumption and high linearization of the power amplifier40aare enabled.

The characteristic of the above power control circuit according to the present embodiment was obtained by simulation.FIG. 5is a circuit diagram for describing the GSM and EDGE modes employed in the simulation.

InFIG. 5, reference numeral160indicates a logarithm/antilogarithm conversion function, reference numeral170indicates an antilogarithm/logarithm conversion function, and reference numeral180indicates a monitor (MT) which detects the power value of a signal outputted from the power amplifier40a. A function representing the relationship between a gain control voltage and an output voltage with respect to the power amplifier40awas applied to a ramp signal arbitrarily created by the base band signal processor10. A low pass filter having a primary transfer function, whose cutoff frequency is 150 kHz, was applied to the loop filter150a, a lag reed filter having a secondary transfer function, in which a cutoff frequency is 150 kHz and a=3 (a: frequency ratio between a pole having a transfer function and a zero point), was applied to the loop filter150b, and a high pass filter having a primary transfer function, whose cutoff frequency is 200 kHz, was applied to the high pass filter110, respectively. Furthermore, the sampling frequency of the A/D converter70was set to 25 MHz, a quantizing step was set as 0.2, and the sampling frequencies of the D/A converters80aand80bwere set to 25 MHz. Incidentally, the detector60awas assumed to be a diode having a sufficient dynamic range and a linear function was applied thereto. Clock delays based on digital signal processing corresponding to three clocks have been taken into consideration with respect to the A/D converter70and the D/A converters80aand80b.

FIG. 6is a graph showing the result of above simulation. As the power of the output signal of the power amplifier40a, 34.5 dBm is taken as an example in the GSM mode, and 27.0 dBm is taken as an example in the EDGE mode. It was demonstrated fromFIG. 6that control on the power of the output signal of the power amplifier40ain each of the GSM and EDGE modes satisfied each time mask and the power control circuit220was operated stably.

Incidentally, the loop filter may be configured as a digital loop filter150cin which the transfer function of the loop filter150bis bilinearly converted in the above simulation. Any of the orders of the transfer functions of the loop filters150athrough150cand the high pass filter110and their cutoff frequencies, the sampling frequency and quantizing step of the A/D converter70and the sampling frequencies of the D/A converters80aand80bmay suitably be changed according to design. Although the number of clocks necessary for each of the A/D converter70and the D/A converters80aand80bis set to three in the above simulation, the number of clocks is not limited to it. An appropriate number of clocks corresponding to design may be adopted.

Owing to the present embodiment as described above, the power control circuit capable of performing stable power control on each of GSM and EDGE can be realized. Thus, since the power control circuit can be shared for a plurality of systems, the downsizing of a multi-band and multi-mode power control circuit is enabled and its cost reduction is enabled.

Third Preferred Embodiment

A third embodiment illustrative of a power control circuit of the present invention is shown inFIG. 7.FIG. 7is a circuit configuration diagram showing a transmitter block of a cellular phone equipped with the power control circuit according to the present embodiment. The cellular phone to which the present invention is applied, is adapted to each of GSM, W-CDMA and EDGE in a manner similar to the second embodiment. The power control circuit according to the present embodiment is used where a comparator90bcan be turned OFF during the modulated signal output period450. Only a sample and hold circuit140cis disposed on the input side of an A/D converter80a. Thus, as compared with the second embodiment, the power control circuit220is reduced in size by a reduction in the number of sample and hold circuits.

A basic operation of the power control circuit220adapted to GSM and EDGE is similar to the second embodiment but the operation of the sample and hold circuit in the EDGE mode is different therefrom.

The operation of a sample hold function at the EDGE mode of the multi-band and multi-mode power control circuit of the present invention will be explained usingFIG. 7. The sample and hold circuit140cis first turned OFF at the ramp up410b. The power control circuit220performs closed-loop operation in a mode similar to the GSM mode in such a manner that the power value of an output signal of a power amplifier40aconverges on a desired value. Next, the sample and hold circuit140cis turned ON during the buffer period440aset to the beginning of the burst420bto memorize and hold a signal value (voltage value or power value) therein. Simultaneously, the comparator90bis turned OFF. Further, the sample and hold circuit140coutputs its memorized and held signal value during the modulated signal output period450. An output signal value of the comparator90bis 0. Furthermore, the power value of the output signal of the power amplifier40ais restored to a value equal to the interval of the buffer period440aduring the buffer period440bset to the end of the burst420b(the input signal of the power amplifier40ais restored to a constant amplitude value). Thereafter, the sample and hold circuit140cis turned OFF and the comparator90bis turned ON. Finally, the sample and hold circuit140cis turned OFF at the ramp down430b, so that the power control circuit220performs closed loop operation in a manner similar to the GSM mode in such a manner that the power value of the output signal of the power amplifier40aconverges on a desired value.

Since the sample and hold circuit140is constituted of a digital circuit in the present embodiment, there is no problem of a sample hold leak. Since a high pass filter110is disposed between the comparator90band an adder100, each signal that passes through an analog feedback loop210results in a high frequency element alone. Therefore, the output signal value (voltage value or power value) of the comparator90bis approximately 0 where the power value of the output signal of the power amplifier40ahas converged on a constant value. Thus, the output signal value of the analog feedback loop210can be retained by turning OFF of the comparator90b. Accordingly, a sample hold function free of the sample hold leak can be realized during the modulated signal output period450in the EDGE mode owing to the above circuit configuration.

Incidentally, the adder100is turned OFF with an initial suitable timing of the ramp down430bto open-loop control the power amplifier40a, whereby the power value of the output signal of the power amplifier40amay be reduced to a desired value. Alternatively, the D/A converters80aand80bare turned OFF to open-loop control the power amplifier40a, whereby the power value may be reduced to a desired power value. Since there is no need to consider spurious generation due to a differential in sample holding value at switching from a sample holding state to a closed loop operation at the buffer period440bin this case, design can be facilitated.

As an alternative to the above, the closed loop operation may be applied during the first half of the ramp down430band the open loop operation may be selected during the latter half thereof. In this case, the open loop operation makes it possible to allow the power value to converge on a desired value even in the case where the power value does not converge on the desired value due to a loop gain reduction caused by non-linearity of the power amplifier40a.

Incidentally, loop filters may suitably be disposed depending upon the characteristic of a closed loop. An example configured in this way is shown inFIG. 8. Loop filters150a,150band150care respectively disposed on the output sides of an adder100, an A/D converter80aand a comparator90a. The loop filter150amay preferably be a low pass filter to suppress switching noise at the turning ON and OFF of the comparator90b.

Since the signal that passes through the analog feedback loop210results in the high frequency element alone as mentioned above, a soft switching operation can be applied to the comparator90b. Thus, the ON and OFF operations of the comparator90bmay preferably be a soft switching operation switched by taking time without using an instantaneous switching operation.

Fourth Preferred Embodiment

A fourth embodiment illustrating a power control circuit of the present invention is shown inFIG. 9.FIG. 9is a circuit configuration diagram showing a transmitter block of a cellular phone equipped with the power control circuit according to the present embodiment. The power control circuit according to the present embodiment is used where the sample and hold circuit140ashown inFIG. 2Acan be shared with a first-stage sample and hold circuit140dconstituting an A/D converter70. As compared with the second embodiment, the power control circuit220is scaled down by the omission of the sample and hold circuit140a.

The power control circuit220corresponding to GSM and EDGE is similar in basic operation to the second embodiment.

The operation of a sample hold function at the EDGE mode of the present embodiment will be explained usingFIG. 9. Sample and hold circuits140bthrough140dare first turned OFF at the ramp up410b. The power control circuit220is operated in a mode similar to the GSM mode in such a manner that the power value of an output signal of a power amplifier40aconverges on a desired value. Next, the sample and hold circuits140bthrough140dare simultaneously turned ON and opened there among during the buffer period440aset at the beginning of the burst420b, and memorize and hold signal values (voltage values or power value) at the respective sample and hold circuits therein. Further, the sample and hold circuits140bthrough140doutput their memorized and held signal values during the modulated signal output period450. Furthermore, the power value of an output signal of a power amplifier40ais restored to a value equal to the interval of the buffer period440aduring the buffer period440bset at the end of the burst420b(the input signal of the power amplifier40ais restored to a constant amplitude value). Thereafter, the sample and hold circuits140bthrough140dare simultaneously turned OFF. Finally, the sample and hold circuits140bthrough140dare turned OFF at the ramp down430b, so that the power control circuit220is operated in the same manner as the GSM mode in such a manner that the power value of the output signal of the power amplifier40aconverges on a desired value.

Since each of the sample and hold circuits140bthrough140dis constituted of a digital circuit in the present embodiment, there is no problem of a sample hold leak.

Incidentally, a loop filter (not shown) may suitably be disposed between an adder100and the power amplifier40a, between the adder100and a D/A converter80aor between a comparator90aand the sample and hold circuit140c.

Fifth Preferred Embodiment

A fifth embodiment illustrative of a semiconductor device and a transceiver circuit of the present invention is shown inFIG. 10. The present embodiment is used for a cellular phone adapted to, for example, GSM and EDGE (hereinafter abbreviated as “GSM/EDGE”) (second communication system) and W-CDMA (first communication system) and is equipped with the power control circuit220selected from the second to fourth embodiments.

InFIG. 10, reference numeral500indicates an isolator, reference numeral510indicates a duplexer, reference numeral520aindicates a transmitter filter, reference numeral530aindicates an antenna switch, reference numeral540aindicates a W-CDMA receiver circuit, reference numeral550aindicates a GSM/EDGE receiver circuit, and reference numeral20bindicates a frequency conversion circuit (MIX), respectively. Reference numeral610indicates a first circuit block configured including a power amplifier40a, a directional coupler50a, a detector60a, the isolator500, the duplexer510, the transmitter filter520a, and the antenna switch530a. The first circuit block610can be constituted as a first module610. Further, reference numeral620indicates a second circuit block configured including a frequency conversion circuit (first frequency conversion circuit)20a, the frequency conversion circuit (second frequency conversion circuit)20b, an available gain amplifier30, the power control circuit (APC)220, the W-CDMA receiver circuit (Rx) (first receiver circuit)540a, and the GSM/EDGE receiver circuit (Rx) (second receiver circuit)550a. The second circuit block620can be configured as a semiconductor device620or a second module620. Reference numeral600indicates a third circuit block configured including the first circuit block610and the second circuit block600. The third circuit block600corresponds to the transceiver circuit according to the present embodiment and can be configured as a third module600.

Incidentally, the circuit blocks in the same range, the modules and the semiconductor device will given the same reference numerals as described above in the present specification.

The operation of the transceiver circuit according to the present embodiment will be explained usingFIG. 10. An audio signal or a data signal inputted to a base band signal processor10is converted to an in-phase component signal (I signal) and a quadrature component signal (Q signal) corresponding to either GSM, EDGE or W-CDMA, after which it is outputted. The I signal and the Q signal are hereinafter abbreviated as “I/Q signals”. The I/Q signal for W-CDMA is defined as a 3 ath signal, whereas the I/Q signal for GSM or EDGE is defined as a 3 bth signal. The 3 ath signal or the 3 bth signal is modulated by the frequency conversion circuit (second frequency conversion circuit)20a, thus resulting in a fourth signal. The fourth signal is inputted to the power amplifier (second amplifier)40avia the available gain amplifier (first amplifier)30.

When a W-CDMA mode is performed, the signal amplified by the power amplifier40ais inputted via the isolator500, the duplexer510and the antenna switch530ato an antenna130afrom which it is transmitted. On the other hand, when a GSM or EDGE mode is performed, the signal amplified by the power amplifier40ais inputted via the transmitter filer520aand the antenna switch530ato the antenna130afrom which it is transmitted.

A signal (1 ath signal) adapted to W-CDMA, which is received by the antenna130a, is inputted to the W-CDMA receiver circuit540avia the antenna switch530aand the duplexer510. The W-CDMA receiver circuit540aamplifies the received signal to a desired power value. Further, the frequency conversion circuit20bconverts the same to an I/Q signal (second signal). The I/Q signal is inputted to the base band signal processor10where it is converted to an audio signal or data signal, after which it is outputted therefrom.

On the other hand, a signal (1 bth signal) adapted to GSM or EDGE, which is received by the antenna130a, is inputted to the GSM/EDGE receiver circuit550avia the antenna switch530a. The GSM/EDGE receiver circuit550aamplifies the received signal to a desired power value. Further, the frequency conversion circuit20bconverts the same to an I/Q signal (second signal). The I/Q signal is inputted to the base band signal processor10where it is converted to an audio signal or data signal, after which it is outputted therefrom.

Configurations and operations of the directional coupler50aand the detector60aare similar to the second through fourth embodiments. As described above, the power control circuit220is equivalent to one selected from the second through fourth embodiments, and its configuration and operation are as already mentioned above.

The cellular phone equipped with the present embodiment is capable of performing operations adapted to GSM/EDGE and W-CDMA by having the configuration and operation referred to above.

Now, the semiconductor device620is realized as an RF-IC (Radio Frequency Integrated Circuit) by forming the frequency conversion circuits20aand20b, the available gain amplifier30, the power control circuit220, the W-CDMA receiver circuit540aand the GSM/EDGE receiver circuit550aover the same semiconductor substrate. Thus, downsizing of the second circuit block620and reduction in its cost are achieved. Semiconductor elements that constitute the frequency conversion circuits20aand20band the like may preferably be BiCMOSs (Bipolar Complementary Metal Oxide Semiconductors) where a reduction in the size thereof, reduction in their power consumption and reduction in their costs are taken into consideration. However, when further reduction in their costs is taken into consideration, the semiconductor elements may preferably be CMOSs (Complementary Metal Oxide Semiconductors).

Incidentally, the power amplifier40aand the detector60ain the first circuit block610are formed over the same semiconductor substrate and can be configured as a semiconductor device. Thus, it is possible to allow temperature characteristics of a power amplifying transistor (not shown) that constitutes the power amplifier40a, and that of a diode (not shown) that constitutes the detector60ato coincide with each other, so the detector60acan be brought into high precision. However, the detector60amay be formed on the semiconductor element (CMOS or BiCMOS) containing the frequency conversion circuit20aor the like. In this case, the CMOS (or BiCMOS) brings about advantageous effects in that since a complex arithmetic circuit is easy to form in small size and at low cost, the degree of freedom of a circuit configuration of the detector60ais made wide and the dynamic range of the detector60acan be expanded. Forming the power amplifier40a, directional coupler50a, detector60a, isolator500, duplexer510, transmitter filter520aand antenna switch530aon the same module like the first module610or the third module630makes it possible to arbitrarily set impedance matching between the respective circuit parts, thus enabling reductions in power consumption and size.

Each of semiconductor elements for the semiconductor device equipped with the power amplifier40aand the detector60amay preferably be an HBT (Heterojunction Bipolar Transistor) composed principally of GaAs where a reduction in size, high linearization and an improvement in withstand voltage are taken into consideration. The same semiconductor element may be an HBT, an HEMT (High Electron Mobility Transistor) or an Si-MOSFET (Silicon Metal Oxide Semiconductor Field Effect Transistor) composed principally of SiGe.

Incidentally, the isolator500may not be disposed depending upon design for impedance matching between the power amplifier40aand the duplexer510. As an alternative to the isolator500, a circulator may be used.

The semiconductor device including the power amplifier40aand the semiconductor device including the frequency conversion unit20aare distinguished as chips different from each other to thereby suppress injection lock due to leakage of a signal from the power amplifier40ato the frequency conversion circuit20a.

Although a description has been made above up to now, of the embodiment in which the present invention is applied to the semiconductor devices and the modules employed in the cellular phone adapted to GSM/EDGE and W-CDMA, the present invention is not limited to the cellular phone. It is needless to say that the present invention can be applied to cellular phones and wireless communication devices adapted to various multi modes. The configurations of the receiver circuits540aand550aare changed in association with the respective multi modes. Incidentally, when the cellular phone is not adapted to W-CDMA, such a constitution as to control the available gain amplifier30may be omitted. Further, when the cellular phone is not adapted to EDGE, the power control circuit according to the first embodiment shown inFIG. 1can be adopted as the power control circuit220.

Sixth Preferred Embodiment

A sixth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 11. In the present embodiment, module configurations are changed with respect to the transceiver circuit according to the fifth embodiment.

A fourth module630is configured with a base band signal processor10included in the third module600shown inFIG. 10.

When the transceiver circuit according to the present embodiment is constituted of two modules, it is divided into a fifth module640and a sixth module650. The fifth module640is configured including a frequency conversion circuit20a, an available gain amplifier30, a power amplifier40a, a directional coupler50a, a detector60a, a power control circuit220, an isolator500, a duplexer510, a transmitter filter520aand an antenna switch530a. The sixth module650is configured including a W-CDMA receiver circuit540a, a GSM/EDGE receiver circuit550aand a frequency conversion circuit20b.

The present embodiment is basically similar to the fifth embodiment in operation and effect but the two module configurations are set as the fifth module640and the sixth module650. Thus, the scale of the fifth module640becomes large. On the other hand, however, the isolation between a transmitted signal in the frequency conversion circuit20aand a received signal in the frequency conversion circuit20bcan be increased, thus making it possible to improve reception sensitivity. Also the receiver circuits are simplified.

Further, when the transceiver circuit of the transceiver circuit type cellular phone is configured by one fourth module630, the cellular phone can be reduced in size as compared with the case in which it is configured of the modules600,610and620or the case in which it is constituted of the modules640and650.

Seventh Preferred Embodiment

A seventh embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 12. In the present embodiment, the configuration set between a frequency conversion circuit20aand a power amplifier40ais changed with respect to the semiconductor device and the transceiver circuit according to each of the fifth and sixth embodiments, and a path including an available gain amplifier30and a path excluding it are provided therebetween.

While the present embodiment is basically similar to the fifth and sixth embodiments in operation and effect for transmission/reception, different points thereof are as follows.

In the present embodiment, a signal outputted from the frequency conversion circuit20ais inputted to the power amplifier40avia the available gain amplifier30where a W-CDMA mode is performed. However, when a GSM or EDGE mode is performed, the output signal of the frequency conversion circuit20ais inputted to the power amplifier40awithout via the available gain amplifier30. Therefore, the power amplifier40ais inputted with the two signals and hence increases in complexity. However, the frequency conversion circuit20acan be disposed for W-CDMA and GSM/EDGE on an individual basis. Hence, a reduction in power consumption of the frequency conversion circuit20aand the facilitation of its design are enabled.

As the semiconductor device and the modules according to the present embodiment, any of the configurations described in the fifth and sixth embodiments may be selected. That is, inFIG. 12, a semiconductor device620or a second module620is configured including the frequency conversion circuit20a, the frequency conversion circuit20b, the available gain amplifier30, a power control circuit220, a W-CDMA receiver circuit540aand a GSM/EDGE receiver circuit550a. Also a third module600is constituted of respective circuits other than an antenna130aand a base band signal processor10. A fourth module630is configured including the base band signal processor10within the same module. Further, a first module610is configured including the power amplifier40a, a directional coupler50a, a detector60a, an isolator500, a duplexer510, a transmitter filter520aand an antenna switch530a. A fifth module640is configured including the frequency conversion circuit20a, available gain amplifier30, power amplifier40a, directional coupler50a, detector60a, power control circuit220, isolator500, duplexer510, transmitter filter520aand antenna switch530a. The configuration of a fourth module650is identical to the sixth embodiment.

Incidentally, no available gain amplifier is disposed in the path adapted to the GSM/EDGE mode in the present embodiment On the contrary, however, an available gain amplifier controlled by the base band signal processor10may be disposed in isolation even in the path adapted to the GSM/EDGE mode in a manner similar to the path adapted to the W-CDMA mode. In this case, part of a variable width of the power value of the signal outputted from the frequency conversion circuit20a, corresponding to GSM/EDGE can be charged to the available gain amplifier. Further, a reduction in power consumption of the frequency conversion circuit20a, a reduction in its size and the facilitation of its design are made possible.

Eighth Preferred Embodiment

An eighth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 13. In the present embodiment, power amplifiers are disposed every paths extending from a frequency conversion circuit20awith respect to the semiconductor device and wireless communication modules of the seventh embodiment. InFIG. 13, reference numeral40bindicates the power amplifier for W-CDMA and reference numeral40cindicates the power amplifier for GSM/EDGE, respectively. Thus, since the power amplifiers are separately provided for W-CDMA and GSM/EDGE in the present embodiment, a power control circuit220performs control only on the power amplifier40cfor GSM/EDGE correspondingly.

The present embodiment is basically similar to the seventh embodiment in operation and effect for transmission/reception. Since, however, the two power amplifiers are disposed in the present embodiment, the present embodiment becomes largish in scale as a whole. On the other hand, however, the power amplifiers40band40ccan respectively be designed separately for W-CDMA and GSM/EDGE. Hence, the power amplifiers40band40ccan be reduced in power consumption, enhanced in linearity and facilitated in design.

Any of the configurations described in the seventh embodiment may be selected for the semiconductor device and modules according to the present embodiment. That is, inFIG. 13, a third module600is constituted of respective circuits other than an antenna130aand a base band signal processor10. A fourth module630is configured including the base band signal processor10within the same module. A first module610is configured including the power amplifier40b, the power amplifier40c, a directional coupler50a, a detector60a, an isolator500, a duplexer510, a transmitter filter520aand an antenna switch530a. A fifth module640is configured including the frequency conversion circuit20a, an available gain amplifier30, the power amplifier40b, the power amplifier40c, the directional coupler50a, the detector60a, the power control circuit220, the isolator500, the duplexer510, the transmitter filter520aand the antenna switch530a. The configurations of a semiconductor device620or a second module620, and a sixth module650are identical to the seventh embodiment.

Ninth Preferred Embodiment

A ninth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 14. In the present embodiment, directional couplers are respectively provided for power amplifiers40band40cwith respect to the semiconductor device and the transceiver circuit according to the eighth embodiment. InFIG. 14, reference numeral50bindicates the directional coupler disposed between the power amplifier40bfor W-CDMA and an isolator500, and reference numeral50cindicates the directional coupler disposed between the power amplifier40cfor GSM/EDGE and a transmitter filter520a, respectively. With such a configuration, an independent path is formed for W-CDMA between a frequency conversion circuit20aand a duplexer510, and an independent path is formed for GSM/EDGE between the frequency conversion circuit20aand an antenna switch530a.

The present embodiment is basically similar to the eighth embodiment in operation and effect for transmission/reception. Since, however, the paths on the transmitting side are separately provided for W-CDMA and GSM/EDGE in the present embodiment, the present embodiment becomes slightly complex in configuration as a whole. On the contrary, however, the frequency conversion circuit20acan be disposed for W-CDMA and GSM/EDGE on an individual basis. Hence, the frequency conversion circuit20acan be reduced in power consumption and facilitated in design. Further, circuits extending from the power amplifiers40band40cto an antenna130acan individually be designed for W-CDMA and GSM/EDGE. As compared with the eighth embodiment, the power amplifiers40band40ccan be reduced in power consumption, enhanced in linearity and facilitated in design.

Any of the configurations described in the eighth embodiment may be selected for the semiconductor device and modules according to the present embodiment. That is, inFIG. 14, a third module600is constituted of respective circuits other than the antenna130aand base band signal processor10. A fourth module630is configured including the base band signal processor10within the same module. A first module610is configured including the power amplifier40b, power amplifier40c, directional coupler50b, directional coupler50c, detector60a, isolator500, duplexer510, transmitter filter520aand antenna switch530a. Further, a fifth module640is configured including the frequency conversion circuit20a, available gain amplifier30, power amplifier40b, power amplifier40c, directional coupler50b, directional coupler50c, detector60a, power control circuit220, isolator500, duplexer510, transmitter filter520aand antenna switch530a. The configurations of a semiconductor device620or a second module620, and a sixth module650are identical to the seventh embodiment.

Tenth Preferred Embodiment

A tenth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 15. In the present embodiment, detectors are respectively provided for directional couplers50band50cwith the semiconductor device and transceiver circuit according to the ninth embodiment. InFIG. 15, reference numeral60bindicates the detector for W-CDMA disposed between the directional coupler50band a power control circuit220, and reference numeral60cindicates the detector for GSM/EDGE disposed between the directional coupler50cand the power control circuit220, respectively.

The present embodiment is basically similar to the ninth embodiment in operation and effect for transmission/reception. Since, however, the detectors60band60care individually provided for W-CDMA and GSM/EDGE in the present embodiment, the present embodiment becomes slightly complex in configuration as a whole. On the contrary, however, the detectors60band60ccan individually be designed for W-CDMA and GSM/EDGE and hence the detectors can be facilitated in design.

Any of the configurations described in the ninth embodiment may be selected for the semiconductor device and modules according to the present embodiment. That is, inFIG. 15, a third module600is constituted of respective circuits other than the antenna130aand base band signal processor10. A fourth module630is configured including the base band signal processor10within the same module. A first module610is configured including the power amplifier40b, power amplifier40c, directional coupler50b, directional coupler50c, detector60b, detector60c, isolator500, duplexer510, transmitter filter520aand antenna switch530a. Further, a fifth module640is configured including the frequency conversion circuit20a, available gain amplifier30, power amplifier40b, power amplifier40c, directional coupler50b, directional coupler50c, detector60b, detector60c, power control circuit220, isolator500, duplexer510, transmitter filter520aand antenna switch530a. The configurations of a semiconductor device620or a second module620, and a sixth module650are identical to the seventh embodiment.

Eleventh Preferred Embodiment

An eleventh embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 16. The present embodiment is used for a cellular phone adapted to respective systems of low band GSM, low band EDGE, high band GSM, high band EDGE and W-CDMA and is equipped with the power control circuit220selected from the second through fourth embodiments. The frequencies lying in a low band and a high band are as mentioned above, that is, the low band is an 800 to 900 MHz band, and the high band is a 1800 to 1900 MHz band. Further, the frequency for W-CDMA is set to an 1800 to 1900 MHz band in consideration of simplification of description.

InFIG. 16, reference numeral40dindicates a power amplifier for W-CDMA and high band GSM/EDGE, reference numeral40eindicates a power amplifier for low band GSM/EDGE, reference numerals50dand50eindicate directional couplers, reference numeral60dindicates a detector, reference numeral520bindicates a transmitter filter adapted to the high band GSM/EDGE, reference numeral520cindicates a transmitter filter adapted to the low band GSM/EDGE, reference numeral530cindicates an antenna switch, reference numeral550aindicates a high band GSM/EDGE receiver circuit, and reference numeral550bindicates a low band GSM/EDGE receiver circuit, respectively.

The operation of the transceiver circuit according to the present embodiment will be explained usingFIG. 16. An audio signal or a data signal inputted to a base band signal processor10is converted to I/Q signals adapted to any of the systems of the low band GSM, low band EDGE, high band GSM, high band EDGE and W-CDMA, after which they are outputted therefrom and modulated at a frequency conversion circuit20a.

When a high band GSM mode, a high band EDGE mode or a W-CDMA mode is performed, the output signal of the frequency conversion circuit20ais inputted to the power amplifier40dvia an available gain amplifier30. Further, when the W-CDMA mode is performed, the signal amplified by the power amplifier40dis inputted via an isolator500, a duplexer510and the antenna switch530cto an antenna130afrom which it is transmitted. On the other hand, when the high band GSM mode or the high band EDGE mode is performed, the signal amplified by the power amplifier40dis inputted via the transmitter filter520band the antenna switch530cto the antenna130afrom which it is transmitted.

On the other hand, when a low band GSM mode or a low band EDGE mode is performed, the output signal of the frequency conversion circuit20ais inputted to the power amplifier40ewhere it is amplified, after which it is inputted via the directional coupler50e, the transmitter filter520cand the antenna switch530cto the antenna130afrom which it is transmitted.

A W-CDMA-based received signal received at the antenna130ais inputted via the antenna switch530cand the duplexer510to a W-CDMA receiver circuit540awhere it is amplified to a desired power value and further converted to I/Q signals at a frequency conversion circuit20b. The I/Q signals are inputted to the base band signal processor10where they are converted to an audio signal or a data signal, after which it is outputted therefrom.

On the other hand, a high band GSM-based or a high band EDGE-based received signal received at the antenna130ais inputted via the antenna switch530cto the high band GSM/EDGE receiver circuit550awhere it is amplified to a desired power value and further converted to I/Q signals at the frequency conversion circuit20b. The I/Q signals are inputted to the base band signal processor10where they are converted to an audio signal or a data signal, after which it is outputted therefrom.

Similarly, a low band GSM-based or a low band EDGE-based received signal received at the antenna130ais inputted via the antenna switch530cto the low band GSM/EDGE receiver circuit550bwhere it is amplified to a desired power value and further converted to I/Q signals at the frequency conversion circuit20b. The I/O signals are inputted to the base band signal processor10where they are converted to an audio signal or a data signal, after which it is outputted therefrom.

The directional couplers50dand50eand the detector60dare similar to those in the first through tenth embodiments in configuration and operation. The configuration and operation of the power control circuit220may select any of those employed in the second through fourth embodiments.

According to the transceiver circuit of the cellular phone having the multi-band and multi-mode power control circuit corresponding to one embodiment of the present invention shown inFIG. 16, the modes adapted to the low band GSM, low band EDGE, high band GSM, high band EDGE and W-CDMA are made possible with the configurations and operations referred to above, and hence the transceiver circuit can be brought into multi-band/multi-mode form.

Incidentally, although the configurations of circuit blocks adapted to the high band GSM, high band EDGE and W-CDMA, in the transceiver circuit according to the present embodiment are set similar to the fifth embodiment, the present embodiment is not limited to them. Any of other sixth through tenth embodiments may be selected.

As the semiconductor device and modules according to the present embodiment, any of the configurations described in the fifth and sixth embodiments may be selected. That is, inFIG. 16, a semiconductor device620or a second module620is configured including the frequency conversion circuit20a, frequency conversion circuit20b, available gain amplifier30, power control circuit220, W-CDMA receiver circuit540a, high band GSM/EDGE receiver circuit550aand low band GSM/EDGE receiver circuit550b. Also a third module600is constituted of respective circuits other than the antenna130aand the base band signal processor10. A fourth module630is configured including the base band signal processor10within the same module. Further, a first module610is configured including the power amplifier40d, power amplifier40e, directional coupler50d, directional coupler50e, detector60d, isolator500, duplexer510, transmitter filter520b, transmitter filter520cand antenna switch530c. A fifth module640is configured including the frequency conversion circuit20a, available gain amplifier30, power amplifier40d, power amplifier40e, directional coupler50d, directional coupler50e, detector60d, power control circuit220, isolator500, duplexer510, transmitter filter520b, transmitter filter520cand antenna switch530c. A fourth module650is configured including the frequency conversion circuit20b, W-CDMA receiver circuit540a, high band GSM/EDGE receiver circuit550aand low band GSM/EDGE receiver circuit550b.

The present embodiment shows an example in which the present invention is applied to a cellular phone of 3-frequency bands (3 bands) and 3 systems (3 modes) adapted to the low band GSM, low band EDGE, high band GSM, high band EDGE and W-CDMA. However, the number of the frequency bands and the number of the systems to which the present invention is applied, are not limited to above, and an arbitrary number of bands and an arbitrary number of systems may be adopted.

Twelfth Preferred Embodiment

A twelfth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown in each ofFIGS. 17A and 17B. Antennas are separately provided for W-CDMA and GSM/EDGE in the present embodiment.

InFIG. 17A, reference numeral530bindicates an antenna switch, reference numeral130bindicates a W-CDMA antenna, and reference numeral130cindicates a GSM/EDGE antenna, respectively. InFIG. 17B, reference numeral530dindicates an antenna switch and reference numeral130dindicates an antenna shared for high band GSM/EDGE and low band GSM/EDGE, respectively.

InFIG. 17A, the transceiver circuit according to the present embodiment, whose overall configuration is not shown in the drawing, is constituted similarly to the fifth embodiment to provide simplification of explanation. InFIG. 17B, the transceiver circuit whose overall configuration is not shown in the drawing, is constituted similarly to the eleventh embodiment for simplification of explanation.

An antenna peripheral circuit120of the present embodiment, which is shown inFIG. 17A, is different from the fifth through tenth embodiments in that it includes the antenna130bconnected to its corresponding duplexer510and the antenna130cconnected to the antenna switch530b.

An antenna peripheral circuit120of the present invention, which is shown inFIG. 17B, is different from the eleventh embodiment in that it includes the antenna130bconnected to its corresponding duplexer510and the antenna130dconnected to the antenna switch530d.

The operation of the antenna peripheral circuit120of the present embodiment, which is shown inFIG. 17A, will be explained.

When a W-CDMA mode is performed, a W-CDMA-based signal inputted to an isolator500is inputted via the duplexer510to the antenna130bfrom which it is transmitted. A W-CDMA-based received signal received at the antenna130bis inputted to its corresponding W-CDMA receiver circuit540avia the duplexer510.

On the other hand, when a GSM or EDGE mode is performed, a GSM or EDGE-based signal inputted to a transmitter filter520ais transmitted from the antenna130cthrough the antenna switch530b. A GSM or EDGE-based received signal received at the antenna130cis inputted to its corresponding GSM or EDGE receiver circuit550avia the antenna switch530b.

The operation of the antenna peripheral circuit120of the present embodiment, which is shown inFIG. 17B, will be described.

When a W-CDMA mode is performed, its operation is similar to that of the antenna peripheral circuit120shown inFIG. 17A.

On the other hand, when a high band GSM mode or a high band EDGE mode is performed, a GSM or EDGE-based signal inputted to its corresponding transmitter filter520bis transmitted from the antenna130dvia the antenna switch530d. A high band GSM or high-band EDGE-based received signal received at the antenna130dis inputted to its corresponding high band GSM/EDGE receiver circuit550avia the antenna switch530d.

Further, when a low band GSM mode or a low band EDGE mode is performed, a GSM or EDGE-based signal inputted to its corresponding transmitter filter520cis transmitted from the antenna130dvia the antenna switch530d. A low band GSM or low band EDGE-based received signal received at the antenna130dis inputted to its corresponding low band GSM/EDGE receiver circuit550bvia the antenna switch530d.

According to the present embodiment, since a signal outputted from a power amplifier40ais transmitted from the antenna130bwithout via the antenna switch where the W-CDMA mode is performed, a circuit loss produced between the power amplifier40aand the antenna130bcan be reduced and hence the power amplifier40acan be reduced in power consumption, size and cost.

Incidentally, although the transceiver circuit120of the present embodiment unillustrated as to its overall configuration is made similar to the fifth embodiment inFIG. 17A, the present invention is not limited to it. Any of the fifth through tenth embodiments may be selected. Although the constitutions of circuit blocks adapted to high band GSM, high band EDGE and W-CDMA in the transceiver circuit120of the present embodiment whose overall configuration is not shown inFIG. 17B, are made similar to part of the circuit according to the fourth embodiment, the present invention is not limited to it, and any of the fifth through tenth embodiments may be selected.

Thirteenth Preferred Embodiment

A thirteenth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 18. In the present embodiment, a circuit for adjusting a power supply voltage of a power amplifier40is added.

InFIG. 18, reference numeral560indicates a battery (BT), reference numeral190indicates a DC-DC converter (DD), reference numeral40findicates a power amplifier and reference numeral50findicates a directional coupler, respectively.

InFIG. 18, any of the fifth through twelfth embodiments may be selected for the transceiver circuit of the present embodiment whose overall is not shown in the drawing.

The operation of adjusting the power supply voltage of the power amplifier in the transceiver circuit according to the present embodiment will be explained.

A voltage supplied from the battery560is inputted to the DC-DC converter190where it is converted to a desired voltage value, which in turn is applied to a power supply voltage terminal (point A inFIG. 18) of the power amplifier40f. A voltage transfer ratio of the DC-DC converter190is adjusted based on a control signal from a base band signal processor10. The power supply voltage terminal A serves as a collector where a power amplifying transistor that constitutes the power amplifier40fis configured of a bipolar transistor such as an HBT. When the power amplifying transistor is constituted of a field effect transistor such as a MOSFET, an HEMT or the like, the power supply voltage terminal A serves as a drain.

In general, the output power of a transistor depends upon input power, a gain adjustment or control voltage or current, load impedance and a power supply voltage.

Thus, according to the present embodiment, the power value of a signal outputted from the power amplifier40fcan be controlled in further detail as compared with the first through twelfth embodiments.

A power supply voltage is applied to elements for feeding back and adjusting the output signal taken out at the directional coupler50fin addition to input power and a gain control voltage. Hence the number of elements increases. Therefore, the degree of freedom of a power control method is made wide, and the facilitation of design and an improvement in control accuracy are hence enabled.

Furthermore, since it is possible to reduce power consumption of the power amplifier for supplying equivalent output power by adjusting or controlling the power supply voltage, power consumption of the power amplifier40fcan be reduced.

Fourteenth Preferred Embodiment

A fourteenth embodiment illustrative of a semiconductor device and a transceiver circuit according to the present invention is shown inFIG. 19. Instead of obtaining the signal inputted to the power control circuit220by detecting the output signal of the power amplifier40in the case of the first through thirteenth embodiments, the present embodiment has changed a detecting method in such a manner that an input signal is obtained by detecting current consumption of the power amplifier40.

InFIG. 19, reference numeral40gindicates a power amplifier, reference numeral570indicates a replica transistor which detects current consumption of the power amplifier40gand reference numeral580indicates a current detector which detects current consumption of the replica transistor570and converts it to a voltage.

Incidentally, any of the first through fourth embodiments may be selected for the configuration and operation of the power control circuit220. InFIG. 19, any of the fifth through thirteenth embodiments may be selected for the transceiver circuit of the present embodiment whose whole span is not shown in the drawing.

The operation of detecting the current of the power amplifier in the transceiver circuit according to the present embodiment will be explained.

In general, the output power of a transistor and its collector current (drain current in the case of an FET) have a correlation therebetween. Therefore, the output power of the power amplifier can be detected by detecting current consumption of a final-stage power amplifying transistor that constitutes the power amplifier. However, the final-stage power amplifying transistor is assumed to be a final-stage power amplifying transistor for GSM, for example. When a power supply voltage is set to 3.5 V, output power is set to 35 dBm, power gain is set to 10 dB, and power added efficiency is set to 60%, current consumption results in about 1.5A and hence the current capacity of the current detector becomes very large. When a resistor is inserted in series with a collector wiring to detect the collector current of the power amplifying transistor, a problem arises in that the performance of the power amplifier is degraded due to the resistor.

Therefore, a replica transistor of a 1/n size of the power amplifying transistor is disposed near above a semiconductor element equivalent to the power amplifying transistor, and current consumption of the replica transistor is detected. Since the current consumption of the replica transistor becomes 1/n of the current consumption of the power amplifying transistor, the current capacity of the current detector can be designed low. Since this does not influence the power amplifying transistor, the degradation of the performance of the power amplifier can be suppressed.

On the basis of such principle as described above, the current consumption of the replica transistor570is detected by the current detector580, where it is converted to a voltage corresponding to the power value of a signal outputted from the power amplifier40g. Any of the first through fourth embodiments may be selected for the operation of the power control circuit220inputted with the output signal of the current detector580.

According to the present embodiment, the power value of the output signal of the power amplifier40gcan be detected by the replica transistor570generally smaller than a directional coupler in size. Therefore, a transmitter circuit of a cellular phone can be reduced in size and cost.

Fifteenth Preferred Embodiment

A fifteenth embodiment illustrative of a power control circuit of the present invention is shown inFIG. 20.FIG. 20is a circuit configuration diagram showing a transmitter block of a cellular phone equipped with the power control circuit according to the present embodiment. While the cellular phone to which the present invention is applied is adapted to the GSM system and W-CDMA system in a manner similar to the first embodiment, gain control is carried out by an available gain amplifier30without being performed by a power amplifier40.

The power control circuit according to the present embodiment is basically similar to the first embodiment in configuration. The present embodiment is however different from the first embodiment in that a signal outputted from a comparator100results in a control signal inputted to the available gain amplifier30without being inputted to the power amplifier40h.

The power control circuit according to the present embodiment is basically similar to the first embodiment in operation and effect. However, when a GSM mode is performed, the power amplifier40his operated in a state in which its bias point is constant (gain control voltage is constant), i.e., a state in which the gain thereof is constant. A signal outputted from the power control circuit220is applied to the available gain amplifier30as described above. Therefore, the output signal of the available gain amplifier30, i.e., the power value of the input signal of the power amplifier40his controlled. Thus, the present embodiment is different from the first embodiment in that the power value of a signal outputted from the power amplifier40his controlled.

Since circuit blocks that perform power control can be integrated or combined into the available gain amplifier30in the present embodiment, the facilitation of design is enabled. In the case of a system in which the effect of reducing power consumption or providing high linearization by control on the gain control voltage of the power amplifier40his low, the power control circuit according to the present embodiment brings about the effect in particular.

The power control circuit220according to the present embodiment can be brought to the power control circuit220having the sample and hold circuit140employed in the second through fourth embodiments. In such a case, the power control circuit220can be applied to each of the cellular phones of the GSM/EDGE system and the W-CDMA system in a manner similar to the second through fourth embodiments. The same cellular phone is configured such that its gain control is performed by the available gain amplifier30without being carried out by the power amplifier40. And the output signal of the power control circuit220is inputted to the available gain amplifier30.

The configuration of a transceiver circuit equipped with the power control circuit220may be constituted as any of the transceiver circuits according to the fifth through fourteenth embodiments. The same transceiver circuit is configured in such a manner that its gain control is performed by the available gain amplifier30without being carried out by the power amplifier40.

Sixteenth Preferred Embodiment

A sixteenth embodiment illustrative of a power control circuit of the present invention is shown inFIG. 21.FIG. 21is a circuit configuration diagram showing a transmitter block of a cellular phone equipped with the power control circuit according to the present embodiment. In a manner similar to the first embodiment, the cellular phone to which the present invention is applied is adapted to GSM and W-CDMA but configured in such a manner that its gain control is performed by a power amplifier40and an available gain amplifier30.

The power control circuit according to the present embodiment is basically similar to the first embodiment in configuration. However, the present embodiment is different from the first embodiment in that a power control signal outputted from a base band signal processor10is supplied to both the power amplifier40and the available gain amplifier30in a W-CDMA mode.

The power control circuit according to the present embodiment is basically similar to the first embodiment in operation and effect. However, the power amplifier40ais different from that employed in the first embodiment in that in a W-CDMA mode, its input power (output power of available gain amplifier30) is stepwise controlled and a gain control voltage is continuously controlled by a power control signal (third power control signal), whereby the output power of the power amplifier40ais controlled. Incidentally, even though the third power control signal for controlling the power amplifier40aand a second power control signal for controlling the available gain amplifier30are identical to each other, the effect of the present embodiment is similar.

Since the output power of the power amplifier40ais controlled by the gain control voltage in the W-CDMA mode, the present embodiment brings about the effect that a reduction in power consumption at low output can be realized.

Although the configurations, operations and effects of the power control circuits of the present invention have been described above while being divided into the sixteen embodiments, the sixteen embodiments may arbitrarily be utilized in combination.

Further, although the present invention is principally applied to the cellular phone and the configuration, operation and effects of its circuit have been described, the present invention is not limited to the cellular phone and brings about the effects at vehicle equipment, home appliances and other devices and apparatuses using wireless communications.

Furthermore, although GSM, EDGE and W-CDMA have been explained above as the systems for the cellular phone while being taken for instance, the present invention is not limited to above. Arbitrary systems such as a PDC (Personal Digital Cellular), cdmalx, a TD-SCDMA (Time Division Synchronous Code Division Multiple Access), etc. may be adopted.

According to the present invention, since the high frequency element of the feedback signal is generated by the analog feedback loop capable of high-speed operation, the high-speed operation of the power control circuit is stabilized.

It is further understood by those skilled in the art that the foregoing description is a preferred embodiment of the disclosed device and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.