Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a stepped pad, a plurality of first bonding wires and a second bonding wire. The first semiconductor chip is stacked on a substrate having a plurality of bonding pads, the first semiconductor chip having a plurality of first chips pads formed along a side portion of the first semiconductor chip. The second semiconductor chip is stacked like a step of a staircase on the first semiconductor chip to form a stepped portion through which the first chip pads are exposed on the first semiconductor chip, the second semiconductor chip having a plurality of second chip pads formed along a side portion of the first semiconductor chip. The stepped pad is arranged between the first chip pads on the stepped portion of the first semiconductor chip, the stepped pad including an adhesive pad adhered to the first semiconductor chip and a conductive pad formed on the adhesive pad. A plurality of the first bonding wires electrically connect between the one second chip pad and the one first chip pad and/or between the one first chip pad and the one bonding pad. The second bonding wire electrically connects between the one second chip pad and the one bonding pad using the stepped pad.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2009-90340, filed on Sep. 24, 2009 in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.

BACKGROUND

Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a semiconductor package including semiconductor chips that are stacked on a substrate and electrically connected to the substrate by a plurality of bonding wires and a method of manufacturing the semiconductor package.

2. Description of the Related Art

Generally, semiconductor devices are manufactured by a fabrication (“fab”) process for forming electrical circuits including electrical elements on a semiconductor substrate, e.g., a silicon wafer, an electrical die sorting (EDS) process for inspecting electrical properties of chips formed by the fab process, and a packaging process for sealing the chips with resin, e.g., epoxy, and sorting the chips.

Through the packaging process, the semiconductor device, e.g., a semiconductor chip, is electrically connected to a mounting substrate, and the semiconductor chip is sealed to be protected from the outside. The semiconductor package including the semiconductor chip mounted on the mounting substrate dissipates heat from the semiconductor chip outside through cooling functions thereof.

The semiconductor package may include the mounting substrate and a plurality of semiconductor chips mounted on the mounting substrate. The semiconductor chips may be electrically connected to the mounting substrate by a plurality of bonding wires.

Recently, as the number of input/output signal lines for the semiconductor chip is increased, dimensions of the wiring substrate and line widths between wiring patterns are reduced. In addition, as the number of the stacked semiconductor chips is increased, the height of the semiconductor package is increased.

Especially, because the length and loop height of the bonding wire for electrically connecting a chip pad of the uppermost semiconductor chip to a bonding pad of the mounting substrate are increased, contact failures between adjacent bonding wires or between the bonding wire and the semiconductor chips occur frequently. Accordingly, the semiconductor package may need to have a structure capable of providing a free wire route design without changing the routes and patterns of the existing bonding wires.

SUMMARY

Example embodiments provide a semiconductor package capable of providing a free wiring routing design.

Example embodiments provide a method of manufacturing the semiconductor package.

According to example embodiments, a semiconductor package includes a first semiconductor chip, a second semiconductor chip, a stepped pad, a plurality of first bonding wires and a second bonding wire. The first semiconductor chip is stacked on a substrate having a plurality of bonding pads, the first semiconductor chip having a plurality of first chip pads formed along a side portion of the first semiconductor chip. The second semiconductor chip is stacked like a step of a staircase on the first semiconductor chip to form a stepped portion through which the first chip pads are exposed on the first semiconductor chip, the second semiconductor chip having a plurality of second chip pads formed along a side portion of the first semiconductor chip. The stepped pad is arranged between the first chip pads on the stepped portion of the first semiconductor chip, the stepped pad including an adhesive pad adhered to the first semiconductor chip and a conductive pad formed on the adhesive pad. A plurality of the first bonding wires are electrically connected between the one second chip pad and the one first chip pad and/or between the one first chip pad and the one bonding pad. The second bonding wire is electrically connected between the one second chip pad and the one bonding pad using the stepped pad.

In an example embodiment, the adhesive pad of the stepped pad may include a nonconductive adhesive film and the conductive pad of the stepped pad may include a conductive material.

In another example embodiment, the stepped pad may be adhered to a dummy pad that is not electrically connected to a circuit element of the first semiconductor chip.

In still another example embodiment, the semiconductor package may further include at least one routing stepped pad arranged at a desired position on the second semiconductor chip, and the second bonding wire may be electrically connected between the one second chip pad and the one bonding pad using the stepped pad and the routing stepped pad.

In an example embodiment, the semiconductor package may further include at least one third semiconductor chip that is stacked like a step in a staircase between the first semiconductor chip and the substrate.

In an example embodiment, the first chip pads may be arranged in a direction substantially the same as the arrangement direction of the second chip pads.

In an example embodiment, the first and second bonding pads may extend substantially perpendicular to the side portion of the window.

In further still another example embodiment, the first and second semiconductor chips may be stacked on a lead frame.

In an example embodiment, the semiconductor package may further include a first adhesive layer between the first semiconductor chip and the substrate and a second adhesive layer between the second semiconductor chip and the first semiconductor chip.

In an example embodiment, the semiconductor package may further include a sealing member that is formed on the substrate to cover the first and second semiconductor chips.

According to example embodiments, in a method of manufacturing a semiconductor package, a first semiconductor chip is stacked on a substrate having a plurality of bonding pads, the first semiconductor chip having a plurality of first chip pads formed along a side portion of the first semiconductor chip. A second semiconductor chip is stacked like a step of a staircase on the first semiconductor chip to form a stepped portion through which the first chip pads are exposed on the first semiconductor chip, the second semiconductor chip having a plurality of second chip pads formed along a side portion of the first semiconductor chip. A stepped pad is adhered between the first chip pads on the stepped portion of the first semiconductor chip. A plurality of first bonding wires are electrically connected between the one second chip pad and the one first chip pad and/or between the one first chip pad and the one bonding pad. A second bonding wire is electrically connected between the one second chip pad and the one bonding pad using the stepped pad.

In an example embodiment, adhering the stepped pad may include adhering an adhesive pad on the stepped portion of the first semiconductor chip exposed from the side portion of the second semiconductor chip, and forming a conductive pad on the adhesive pad.

In an example embodiment, the adhesive pad may include a nonconductive adhesive film.

In an example embodiment, the method may further include stacking at least one third semiconductor chip like a step of a staircase between the first semiconductor chip and the substrate.

In an example embodiment, the method may further include forming a sealing member on the substrate to cover the first and second semiconductor chips.

In another example embodiment, adhering the stepped pad may include adhering the stepped pad to a dummy pad that is not electrically connected to a circuit element of the first semiconductor chip.

In still another example embodiment, the method may further include adhering at least one routing stepped pad at a desired position on the second semiconductor chip, and electrically connecting the second bonding wire between the second chip pad and the bonding pad may include connecting the second bonding wire between the second chip pad and the bonding pad using the stepped pad and the routing stepped pad.

In further still another example embodiment, stacking the first semiconductor chip may include stacking the first semiconductor chip on a lead frame.

According to example embodiments, a semiconductor package includes a plurality of semiconductor chips stacked on a substrate and stepped pads serving as “stepping stones” between the uppermost semiconductor chip and the substrate. The stepped pads may relay intermediate wires to electrically connect the uppermost semiconductor chip to a bonding pad of the substrate.

Accordingly, the stepped pads may provide a free wiring route design for a bonding wire. Additionally, the stepped pads may compensate for the height differences between the stacked semiconductor chips to decrease the loop height of the bonding wire to thereby miniaturize the semiconductor package. Further, the bonding wire may be prevented from making contact with the adjacent another bonding wire that is spaced apart by a relatively small distance or the semiconductor chips, to thereby improve reliability of the semiconductor package.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 1is a plan view illustrating a semiconductor package in accordance with a first example embodiment.FIG. 2is a cross-sectional view taken along the II-IP lined inFIG. 1.

Referring toFIGS. 1 and 2, a semiconductor package100includes a substrate110, first, second and third semiconductor chips200,300,400sequentially stacked on the substrate110, and a plurality of bonding wires electrically connecting the first, second and third semiconductor chips to the substrate110.

The substrate for mounting the first, second and third semiconductor chips200,300,400may have a first face112and a second face114opposite to the first face112. A plurality of bonding pads120may be formed on the first face112. A plurality of solder ball pads130may be formed on the second face114. For example, the substrate110may be a printed circuit board (PCB).

In a first example embodiment, the first, second and third semiconductor chips200,300,400may include a plurality of the circuit elements. The circuit element may include a plurality of memory devices. Examples of the memory devices may be a volatile memory device and a non-volatile memory device. Examples of the volatile memory device may be DRAM, SRAM, etc. Examples of the non-volatile memory device may be EPROM, EEPROM, Flash EEPROM, etc.

The first semiconductor chip200may be stacked on the first face112of the substrate110. For example, the first semiconductor chip200may be adhered to the substrate110via a first adhesive layer210.

A plurality of first chip pads220may be formed on an active surface of the first semiconductor chip200. In a first example embodiment, the first chip pads220may be formed along a side portion of the first semiconductor chip200. The first chip pads220may be arranged in a first direction along a peripheral region of the first semiconductor chip200.

The second semiconductor chip300may be stacked on the first semiconductor chip200. For example, the second semiconductor chip300may be adhered to the first semiconductor chip200via a second adhesive layer310.

A plurality of second chip pads320may be formed on an active surface of the second semiconductor chip300. In a first example embodiment, the second chip pads320may be arranged in a direction substantially the same as the first direction along a peripheral region of the second semiconductor chip300.

The third semiconductor chip400may be stacked on the second semiconductor chip300. For example, the third semiconductor chip400may be adhered to the second semiconductor chip300via a third adhesive layer410.

A plurality of third chip pads420may be formed on an active surface of the third semiconductor chip400. In a first example embodiment, the third chip pads420may be arranged in a direction substantially the same as the first direction along a peripheral region of the third semiconductor chip400.

In a first example embodiment, the second semiconductor chip300may be stacked like a step of a staircase to form a first stepped portion202on the first semiconductor chip200. In the first stepped portion202provided on the first semiconductor chip200, the first chip pads220of the first semiconductor chip200may be exposed through the side portion of the second semiconductor chip300.

The third semiconductor chip400may be stacked like a step of a staircase to form a second stepped portion302on the second semiconductor chip300. In the second stepped portion302provided on the second semiconductor chip300, the second chip pads320of the second semiconductor chip300may be exposed through the side portion of the third semiconductor chip400.

In a first example embodiment, a first stepped pad230may be arranged on the first stepped portion202of the first semiconductor chip200. The first stepped pad230may be arranged between the first chip pads220. Accordingly, the first stepped pad230on the first semiconductor chip200may be exposed through the side portion of the second semiconductor chip300.

In a first example embodiment, a second stepped pad330may be arranged on the second stepped portion302of the second semiconductor chip300. The second stepped portion330may be between the second chip pads320. Accordingly, the second stepped pad330on the second semiconductor chip300may be exposed through the side portion of the third semiconductor chip400.

The sizes of the first and second stepped portions230and330may be determined based on the distance between the adjacent chip pad and the thickness of the bonding wire. For example, the sizes of the first and second stepped pads230and330may be substantially the same as those of the first, second and third chip pads220,320,420. The heights of the first and second stepped pads230and330may be determined based on the loop height of the bonding wire and the thicknesses of the first to third semiconductor chips.

In a first example embodiment, the bonding wires may include a first bonding wire500and a second bonding wire600. The bonding pads120may be electrically connected to any one of the first, second and third chip pads220,320,420by the first bonding wires500and/or the second bonding wire600.

For example, the first bonding wire500may include a first wire510, a second wire520and a third wire530. The first wire510may electrically connect the one bonding pad120to the one first chip pad220. The second wire520may electrically connect the one first chip pad220to the one second chip pad320. The third wire530may electrically connect the one second chip pad320to the one third chip pad420. Accordingly, the bonding pad120may be electrically connected to the third chip pad420by the first to third wires510,520,530.

Alternatively, the first bonding wire500may include a first wire510and a second wire520. The first wire510may electrically connect the one bonding pad120to the one first chip pad220. The second wire520may electrically connect the one first chip pad220to the one second chip pad320. Accordingly, the bonding pad120may be electrically connected to the second chip pad320by the first and second wires510and520.

As illustrated inFIG. 2, in a first example embodiment, the second bonding wire600may electrically connect the one bonding pad120to the one third chip pad420using the first and second stepped portions230and330.

The second boding wire600may include a fourth wire610, a fifth wire620and a sixth wire630. The fourth wire610may electrically connect the one bonding pad120to a first conductive pad of the first stepped pad230. The fifth wire620may electrically connect the first conductive pad of the first stepped pad230to a second conductive pad (334, seeFIG. 3) of the second stepped pad330. The sixth wire630may electrically connect the second conductive pad334of the second stepped pad330to the third chip pad420. Accordingly, the bonding pad120may be electrically connected to the third chip pad420using the first and second stepped pads230and330.

FIG. 3is an enlarged view illustrating the stepped pad of the semiconductor package inFIG. 2.

Referring toFIG. 3, the second stepped pad330may include a second adhesive pad332and a second conductive pad334. The second adhesive pad332may be adhered to the second stepped portion302of the second semiconductor chip300. The second conductive pad334may be formed on the second adhesive pad332.

For example, the second adhesive pad332may include a nonconductive adhesive film. The second conductive pad334may include a conductive material. Examples of the conductive material may be gold (Au), silver (Ag), copper (Cu), aluminum (Al), etc. The conductive material may be selected from the material having a great adhesive strength for the bonding wire.

The second stepped pad330may be disposed on the second stepped portion302of the second semiconductor chip300. The second stepped pad330may be arranged between the second chip pads (320, seeFIG. 1). The second adhesive pad332of the second steppe pad330may be adhered to the second stepped portion302of the second semiconductor chip300. The second conductive pad334may be formed on the second adhesive pad332.

The first stepped pad may be substantially the same as the second stepped pad330. For example, the first stepped pad may include a first adhesive pad and a first conductive pad. The first adhesive pad may be adhered to the first stepped portion of the first semiconductor chip200. The first conductive pad may be formed on the first adhesive pad.

For example, the first adhesive pad may include a nonconductive adhesive film. The first conductive pad may include a conductive material. The first conductive pad may be formed using a material the same as the bonding wire or a material having a great adhesive strength for the bonding wire.

Referring again toFIGS. 1 and 3, the fourth wire610of the second bonding wire600may electrically connect the one bonding pad120to the first conductive pad of the first stepped pad230. The fifth wire620of the second bonding wire600may electrically connect the first conductive pad of the first stepped pad230to the second conductive pad334of the second stepped pad330. The fifth wire630of the second bonding wire600may electrically connect the second conductive pad of the second stepped pad330to the third chip pad420. Accordingly, the bonding pad120may be electrically connected to the third chip pad420using the first and second stepped pads230and330.

In a first example embodiment, the first stepped pad230may be arranged at a desired position between the first chip pads220on the first stepped portion202of the first semiconductor chip200. The second stepped pad330may be arranged at a desired position between the second chip pads320on the second stepped portion302of the second semiconductor chip300. For example, the first and second stepped portion230and330may be easily adhered at desired positions using their adhesive strengths during the package manufacturing process.

Accordingly, the first and second stepped pads230and330may relay the fourth, fifth and sixth wires610,620,630of the second bonding wire600to electrically connect the third chip pad420of the uppermost semiconductor chip400to the bonding pad120. Thus, the first and second stepped pads230and330may provide a free wiring route design for the second bonding wire600.

The heights of the first and second stepped pads230and330may be determined based on the height differences between the stacked semiconductor chips200,300,400. Accordingly, the first and second stepped pads230and330may compensate the height differences between the stacked semiconductor chips200,300,400to decrease the loop height of the second bonding wire600to thereby miniaturize the semiconductor package100.

Further, the first and second stepped pads230,330may be arranged to have selected heights at desired positions between the first and second chips pads220,320. Accordingly, the second bonding wire600may be prevented from making contact with the adjacent first bonding wire500that is spaced apart by a relatively small distance or the first to third semiconductor chips200,300,400, to thereby improve reliability of the semiconductor package.

In a first example embodiment, a sealing member (not illustrated) may be formed on the first face112of the substrate110to protect the first, second and third semiconductor chips protect them from the outside.

A plurality of the solder ball pads130may be formed on the second face114of the substrate110. A solder ball140may be disposed on the solder ball pad130exposed by an insulation layer132, and the semiconductor package100may be mounted on a module substrate (not illustrated) via the solder balls140to provide a memory module (not illustrated).

FIG. 4is a plan view illustrating a semiconductor package in accordance with a second example embodiment.FIG. 5is a cross-sectional view taken along the V-V′ line inFIG. 4. The semiconductor package of the present embodiment is substantially the same as in the embodiment ofFIG. 1except arrangement of the stepped pads. Thus, the same reference numerals will be used to refer to the same or like elements as those described in the embodiment ofFIG. 1and any further repetitive explanation concerning the above elements will be omitted.

Referring toFIGS. 4 and 5, a semiconductor package101in accordance with a second example embodiment includes a substrate110, first, second and third semiconductor chips200,300,400sequentially stacked on the substrate110, and a plurality of bonding wires electrically connecting the first, second and third semiconductor chips to the substrate110.

A plurality of bonding pads120may be formed on the first face112. The first, second and third semiconductor chips200,300,400may include a plurality of the circuit elements therein.

The first semiconductor chip200may be adhered to the substrate110via a first adhesive layer210. A plurality of first chip pads220may be formed on an active surface of the first semiconductor chip200. The first chip pads220may be formed along a side portion of the first semiconductor chip200. The first chip pads220may be arranged in a first direction along a peripheral region of the first semiconductor chip200.

The second semiconductor chip300may be adhered to the first semiconductor chip200via a second adhesive layer310. A plurality of second chip pads320may be formed on an active surface of the second semiconductor chip300. The second chip pads320may be arranged in a direction substantially the same as the first direction along a peripheral region of the second semiconductor chip300.

The third semiconductor chip400may be adhered to the second semiconductor chip300via a third adhesive layer410. A plurality of third chip pads420may be formed on an active surface of the third semiconductor chip400. The third chip pads420may be arranged in a direction substantially the same as the first direction along a peripheral region of the third semiconductor chip400.

In a second example embodiment, a first dummy pad222may be formed on an active surface of the first semiconductor chip200. The first dummy pad222may be arranged between the first chip pads220. A second dummy pad322may be formed on an active surface of the second semiconductor chip300. The second dummy pad322may be arranged between the second chip pads320. In this case, the first dummy pad222may not be electrically connected to the circuit element of the first semiconductor chip200. The second dummy pad322may not be electrically connected to the circuit element of the second semiconductor chip300.

In a second example embodiment, the second semiconductor chip300may be stacked like a step of a staircase to form a first stepped portion202on the first semiconductor chip200. In the first stepped portion202provided on the first semiconductor chip200, the first chip pads220and the first dummy pad222of the first semiconductor chip200may be exposed through the side portion of the second semiconductor chip300.

The third semiconductor chip400may be stacked like a step of a staircase to form a second stepped portion302on the second semiconductor chip300. In the second stepped portion302provided on the second semiconductor chip300, the second chip pads320and the second dummy pad322of the second semiconductor chip300may be exposed through the side portion of the third semiconductor chip400.

In a second example embodiment, a first stepped pad230may be arranged on the first dummy pad232of the first semiconductor chip200. Accordingly, the first stepped pad230on the first semiconductor chip200may be exposed through the side portion of the second semiconductor chip300.

A second stepped pad330may be arranged on the second dummy pad322of the second semiconductor chip300. Accordingly, the second stepped pad330on the second semiconductor chip300may be exposed through the side portion of the third semiconductor chip400.

The second bonding wire600may electrically connect the one bonding pad120to the one third chip pad420using the first and second stepped portions230and330.

For example, the second boding wire600may include a fourth wire610, a fifth wire620and a sixth wire630. The fourth wire610may electrically connect the one bonding pad210to a first conductive pad of the first stepped pad230. The fifth wire620may electrically connect the first conductive pad of the first stepped pad230to a second conductive pad of the second stepped pad330. The sixth wire630may electrically connect the second conductive pad of the second stepped pad330to the third chip pad420. Accordingly, the bonding pad120may be electrically connected to the third chip pad420using the first and second stepped pads230and330.

In a second example embodiment, the first stepped pad230and the second stepped portion330may be easily adhered at desired positions using adhesive strengths of the first and second stepped portions during the package manufacturing process. Accordingly, the first and second stepped pads230and330may be arranged on the first and second dummy pads222and322to serve as stepping stones for electrically connecting the third chip pad420of the uppermost semiconductor chip400to the bonding pad120. Thus, the first and second stepped portion230and300may provide a free wiring route design for the second bonding wire600.

FIG. 6is a plan view illustrating a semiconductor package in accordance with a third example embodiment. The semiconductor package of the present embodiment is substantially the same as in the embodiment ofFIG. 1except arrangement of the stepped pads. Thus, the same reference numerals will be used to refer to the same or like elements as those described in the embodiment ofFIG. 1and any further repetitive explanation concerning the above elements will be omitted.

Referring toFIG. 6, a semiconductor package102in accordance with a third example embodiment includes a substrate110, first, second and third semiconductor chips200,300,400sequentially stacked on the substrate110, and a plurality of bonding wires electrically connecting the first, second and third semiconductor chips to the substrate110.

The second semiconductor chip300may be stacked like a step of a staircase to form a first stepped portion202on the first semiconductor chip200. In the first stepped portion202provided on the first semiconductor chip200, the first chip pads220of the first semiconductor chip200may be exposed through the side portion of the second semiconductor chip300.

The third semiconductor chip400may be stacked like a step of a staircase to form a second stepped portion302on the second semiconductor chip300. In the second stepped portion302provided on the second semiconductor chip300, the second chip pads320of the second semiconductor chip300may be exposed through the side portion of the third semiconductor chip400.

A first stepped pad230may be arranged on the first stepped portion202of the first semiconductor chip200. The first stepped pad230may be arranged between the first chip pads220. A first adhesive pad of the first stepped pad230may be adhered to the first stepped portion202of the first semiconductor chip200. A first conductive pad may be formed on the first adhesive pad.

A second stepped pad330may be arranged on the second stepped portion302of the second semiconductor chip300. The second stepped pad330may be arranged between the second chip pads320. A second adhesive pad of the second stepped pad330may be adhered to the second stepped portion302of the second semiconductor chip300. A second conductive pad may be formed on the second adhesive pad.

In a third example embodiment, at least one routing stepped pad430may be arranged on the third semiconductor chip400. As illustrated inFIG. 6, five routing stepped pads430may be arranged at desired positions between the third chip pads420on the third semiconductor chip400to thereby provide a free wiring route for a second bonding wire600.

The first and second stepped pads230,330and the routing stepped pads430may be easily adhered on each of the semiconductor chips at desired positions using their adhesive strengths during the package manufacturing process. The second bonding wire600may electrically connect the one bonding pad120to the one third chip pad420using the first and second stepped portions230and330and the routing stepped pads430.

Thus, the first and second stepped pads230and330and the routing stepped pads430may serve as stepping stones for electrically connecting the third chip pad420of the uppermost semiconductor chip400to the bonding pad120to thereby provide a free wiring route design.

FIG. 7is a cross-sectional view illustrating a semiconductor package in accordance with a fourth example embodiment. The semiconductor package of the present embodiment is substantially the same as in the embodiment ofFIG. 1except the number of stacked semiconductor chips and an element for mounting the semiconductor chips. Thus, the same reference numerals will be used to refer to the same or like elements as those described in the embodiment ofFIG. 1and any further repetitive explanation concerning the above elements will be omitted.

Referring toFIG. 7, a semiconductor package103in accordance with a fourth example embodiment includes a lead frame700, first, second, third and fourth semiconductor chips200,300,400,800sequentially stacked on the lead frame700, and a plurality of bonding wires electrically connecting the first, second, third and fourth semiconductor chips to the lead frame700.

In a fourth example embodiment, the first, second, third and fourth semiconductor chips200,300,400,800may be stacked like steps of a staircase on a stage portion702of the lead frame700.

A fourth chip pad820of the uppermost fourth semiconductor chip800may be electrically connected to a bonding pad portion704of the lead frame700by a second bonding wire600. The second bonding wire600may electrically connect the one bonding pad portion704to one fourth chip pad820of the fourth semiconductor chip800using first, second and third stepped pads230,330,430provided respectively on the stepped portions of the first, second and third semiconductor chips200,300,400.

A sealing member900may be formed to cover the first to fourth semiconductor chips, and an outer lead portion706of the lead frame700may extend outwardly to be mounted on a module substrate (not illustrated) to provide a memory module (not illustrated).

Hereinafter, a method of manufacturing a semiconductor package in accordance with a first example embodiment will be explained.

FIGS. 8 to 11are cross-sectional views illustrating a method of manufacturing the semiconductor package inFIG. 1.

Referring toFIG. 8, a substrate110having a plurality of bonding pads120is prepared. A first semiconductor chip200is stacked on a first face of the substrate110. The first semiconductor chip200has a plurality of first chip pads along a side portion thereof. For example, the first semiconductor chip200may be adhered to the substrate110via a first adhesive layer210.

A second semiconductor chip300is stacked on the first semiconductor chip200. The second semiconductor chip300has a plurality of second chip pads along a side portion thereof. For example, the second semiconductor chip300may be adhered to the first semiconductor chip200via a second adhesive layer310.

The second semiconductor chip300is stacked like a step of a staircase to form a first stepped portion202on the first semiconductor chip200. In the first stepped portion202provided on the first semiconductor chip200, the first chip pads are exposed through the side portion of the second semiconductor chip300.

A third semiconductor chip300is stacked on the second semiconductor chip300. The third semiconductor chip400has a plurality of third chip pads420along a side portion thereof. For example, the third semiconductor chip400may be adhered to the second semiconductor chip300via a third adhesive layer410.

The third semiconductor chip400is stacked like a step of a staircase to form a second stepped portion302on the second semiconductor chip300. In the second stepped portion302provided on the second semiconductor chip300, the second chip pads are exposed through the side portion of the third semiconductor chip400.

Referring toFIG. 9, a first stepped pad230is disposed on the first stepped portion202of the first semiconductor chip200and a second stepped pad330is disposed on the second stepped portion302of the second semiconductor chip300. The first stepped pad230may be arranged between the first chip pads. The second stepped pad330may be arranged between the second chip pads.

The first stepped pad230may include a first adhesive pad and a first conductive pad. The second stepped pad330may include a second adhesive pad and a second conductive pad. For example, the first and second adhesive pads may include a nonconductive adhesive film. The first and second conductive pad may include a conductive material. Examples of the conductive material may be gold (Au), silver (Ag), copper (Cu), aluminum (Al), etc. The conductive material may be selected from the material having a great adhesive strength for the bonding wire. The first and second stepped pads may be easily adhered using adhesive strengths of the first and second adhesive pads on the first and second semiconductor chips200and300, respectively.

Referring toFIGS. 1 and 10, the third chip pads420of the third semiconductor chip400are electrically connected to the bonding pads120using a plurality of first bonding wires500. Another third chip pad420of the third semiconductor chip400is electrically connected to the bonding pad120using a second bonding wire600.

For example, a first wire510of the first bonding wire500electrically connects the one bonding pad210to the one first chip pad220. A second wire520of the first bonding wire500electrically connects the one first chip pad220to the one second chip pad320. A third wire530electrically connects the one second chip pad320to the one third chip pad420. Accordingly, the bonding pad120may be electrically connected to the third chip pad420by the first bonding wire500.

The second bonding wire600may electrically connect the one bonding pad120to the one third chip pad420using the first and second stepped portions230and330.

As illustrated inFIG. 10, while a capillary1000of a bonding apparatus moves from the third chip pad420to the second stepped pad330, a file metal line is extended out of the capillary1000. Accordingly, a sixth wire630of the second bonding wire600electrically connects the second conductive pad of the second stepped pad330to the third chip pad420.

While the capillary1000moves from the second stepped pad330to the first stepped pad230, a file metal line is extended out of the capillary1000. Accordingly, a fifth wire620of the second bonding wire600electrically connects the first conductive pad of the first stepped pad230to the second conductive pad of the second stepped pad330.

While the capillary1000moves from the first stepped pad230to the bonding pad120, a file metal line is extended out of the capillary1000. Accordingly, a fourth wire610of the second bonding wire600electrically connects the first conductive pad of the first stepped pad230to the bonding pad120. Accordingly, the bonding pad120may be electrically connected to the third chip pad420using the first and second stepped pads230and330.

Referring toFIG. 11, a sealing member900is formed on the substrate110to cover the first, second and third semiconductor chips200,300,400.

Then, a solder ball140is disposed on a solder ball pad130exposed by an insulation layer132on a second face114of the substrate110. The substrate is mounted on a module substrate (not illustrated) via the solder balls140to complete a memory module (not illustrated).

As mentioned above, a semiconductor package in accordance with example embodiments includes a plurality of semiconductor chips stacked on a substrate and stepped pads serving as stepping stones between the uppermost semiconductor chip and the substrate. The stepped pads may relay intermediate wires to electrically connect the uppermost semiconductor chip to a bonding pad of the substrate.

Accordingly, the stepped pads may provide a free wiring route design for a bonding wire. Additionally, the stepped pads may compensate the height differences between the stacked semiconductor chips to decrease the loop height of the bonding wire to thereby miniaturize the semiconductor package. Further, the bonding wire may be prevented from making contact with the adjacent another bonding wire that is spaced apart by a relatively small distance or the semiconductor chips, to thereby improve reliability of the semiconductor package.