Fabric interconnect for distributed fabric architecture

A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port.

FIELD OF THE INVENTION

The invention relates generally to data centers and data processing. More particularly, the invention relates to an interconnect system used by network line cards and scaled-out fabric couplers in a distributed fabric system.

BACKGROUND

Data centers are generally centralized facilities that provide Internet and intranet services needed to support businesses and organizations. A typical data center can house various types of electronic equipment, such as computers, servers (e.g., email servers, proxy servers, and DNS servers), switches, routers, data storage devices, and other associated components. The infrastructure of the data center, specifically, the layers of switches in the switch fabric, plays a central role in the support of the services. Interconnection among the various switches can be instrumental to scalability, that is, the ability to grow the size of the data center

SUMMARY

In one aspect, the invention features a distributed line card (DLC) comprising a plurality of network ports receiving packets over a network and a plurality of network processors. Each network processor has a fabric interface that provides a plurality of SerDes (Serializer/Deserializer) channels. Each network processor divides each packet received over the network ports into a plurality of cells and distributes the cells of each received packet across the SerDes channels. The DLC further comprises a plurality of fabric ports through which the DLC is in communication with scaled-out fabric couplers. Each fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane of each pluggable interface is mapped to one of the SerDes channels of the fabric interfaces of the plurality of network processors such that an equal number of SerDes channels of each fabric interface is mapped to each of the fabric ports.

In another aspect, the invention features an interconnect system including a plurality of scaled-out fabric coupler (SFC) boxes and a plurality of distributed line card (DLC) boxes. Each SFC box has a plurality of fabric ports and a cell-based switch fabric element for switching cells among the SFC fabric ports. Each DLC box is in communication with every one of the SFC boxes. Each DLC box has a plurality of network ports receiving packets over a network and a plurality of network processors. Each network processor has a fabric interface that provides a plurality of SerDes (Serializer/Deserializer) channels. The network processors divide each packet received over the network ports into a plurality of cells and distribute the cells of each received packet across the SerDes channels. Each DLC box further comprises a plurality of DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane of each pluggable interface is mapped to one of the SerDes channels of the fabric interfaces of the plurality of network processors such that an equal number of SerDes channels of each fabric interface is mapped to each of the DLC fabric ports.

In still another aspect, the invention features an interconnect system between a plurality of network switching elements and scaled-out fabric couplers. The interconnect system comprises a plurality of fabric ports through which the network switching elements are in communication with the scaled-out fabric couplers. Each fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane of each pluggable interface is mapped to a SerDes channel provided by one of the network switching elements. An equal number of SerDes channels of each network switching element is mapped to each of the fabric ports.

DETAILED DESCRIPTION

Data centers described herein use standard form-factor pluggable interfaces, preferably standard IB CXP interfaces, to provide an interconnection between distributed line cards (DLC) chasses and scaled-out fabric couplers (SFC) chasses in a distributed chasses architecture. Through these standard pluggable interfaces, network switching elements of the DLCs transmit and receive proprietary cell-based payload over SerDes (serialization/deserialization) channels. Each pluggable interface provides a given number of lanes over which to transmit and receive the cells, with each lane of each pluggable interface being mapped to one of the SerDes channels provided by the network switching elements. Preferably, an equal number of SerDes channels of each network switching element of a given DLC is mapped to each of the pluggable interfaces. Accordingly, any given pluggable interface is connected to each of the network switching elements of the DLC by the same number of lanes. This configuration facilitates scalability, that is, the growth of the data center through an increase in the number of DLCs and/or number of networking switching elements in the DLCs.

FIG. 1shows an embodiment of a distributed chassis architecture10that may be implemented in a data center. The distributed chassis architecture10has a plurality of switch SFC chasses or boxes12-1,12-M (generally,12) in communication with a plurality of DLC chasses or boxes14-1,14-2,14-N (generally,14). This example embodiment has four SFC boxes (M=4) and N DLC boxes. The number, N, of DLCs can range in the hundreds and thousands. The SFCs and DLCs are part of a single cell-based switched domain.

Each SFC12includes one or more cell-based switch fabric elements (FE)16in communication with N fabric ports18, there being at least as many fabric ports18in each SFC12as the number of DLC boxes14in the distributed chassis architecture10. Each fabric element16of an SFC switches cells between fabric ports18based on the destination information in the cell header.

Each DLC box14has a plurality of network ports20and a plurality of fabric ports22. The network ports20are in communication with a network external to the switched domain, such as the Internet. In one embodiment, each DLC14has 40 network ports20, with each of the network ports20being configured as a 10 Gbps Ethernet port; the aggregate bandwidth of these DLCs is 400 Gbps.

Each DLC box14further includes a plurality of network processors (i.e., network switching elements)24-1,24-2(generally,24). Each network processor24is in communication with every fabric port22and a subset of the network ports20(for example, each network processor24can switch cells derived from packet traffic received on 20 of the 40 network ports). An example implementation of the network processor24is the BCM 88650, a 20-port, 10 GbE switch device produced by Broadcom, of Irvine, Calif.

Preferably, each fabric port22includes a 120 Gbps CXP interface. In one embodiment, the CXP interface has twelve lanes (12×), each lane providing a 10 Gbps channel. An example specification of the 120 Gbps 12×CXP interface can be found in the “Supplement to InfiniBand™ Architecture Specification Volume 2 Release 1.2.1”, published by the InfiniBand™ Trade Association. This embodiment of 12-lane CXP is referred to as standard Infiniband (IB) CXP. In another embodiment, the CXP interface has 10 lanes (10×) for supporting 10-lane applications, such as 100 Gigabit Ethernet. This embodiment of 10-lane CXP is referred to as Ethernet CXP.

The distributed chassis architecture10is for a full-mesh configuration: each DLC14is in communication with each of the SFCs12; more specifically, each of the fabric ports22of a given DLC14is in electrical communication with a fabric port18of a different one of the SFCs12over a communication link26. Referring to the DLC14-1as a representative example, the DLC fabric port22-1of the DLC14-1is in communication with the fabric port18-1of the SFC12-1, the DLC fabric port22-2with the fabric port18-2of the SFC12-2, the DLC fabric port22-3with the fabric port18-3of the SFC12-3, and the DLC fabric port22-4with the fabric port18-4of the SFC12-4. Connected in this full-mesh configuration, the DLCs and SFCs form a distributed virtual chassis, with the DLCs acting as line cards in the distributed chassis. The distributed virtual chassis is modular; that is, DLCs can be added to or removed from the distributed virtual chassis, one at a time, like line cards added to or removed from a chassis.

The communication link26between each DLC fabric port22and an SFC fabric port18can be a wired connection. Interconnect variants include Direct Attached Cable (DAC) or optical cable. DAC provides five to seven meters of cable length; whereas the optical cable offers up to 100 meters of connectivity within the data center, (standard optical connectivity can exceed 10 km). Alternatively, the communication link26can be a direct physical connection (i.e., electrical connectors of the DLC fabric ports22physically connect directly to electrical connectors of the SFC fabric ports18).

During operation of the distributed virtual chassis, a packet arrives at a network port20of one of the DLCs14. The network processor24of the DLC14that is in communication with the network port20upon which the packet arrives partitions the packet into smaller cells, adding a pre-classification header and a cell header (used in ordering of cells) to each cell. The network processor24sends the cells out through the fabric ports22to each of the SFCs12, sending different cells to different SFCs12. For example, consider an incoming packet with a length of 1600 bits. The receiving network processor24of the DLC14can split the packet into four cells of 400 bits (before adding header information to those cells). The network processor24then sends a different cell to each of the four SFCs12, in effect, achieving a load balancing of the cells across the SFCs12.

A cell-based switch fabric element16of each SFC12receiving a cell examines the header of that cell, determines its destination, and sends the cell out through the appropriate one of the fabric ports18of that SFC to the destination DLC14. The destination DLC14receives all cells related to the original packet from the SFCs, reconstructs the original packet (i.e., removing the added headers), and sends the reconstructed packet out through the appropriate one of its network ports22. Continuing with the previous four-cell example, consider that each SFC determines that the destination DLC is DLC14-2. Each SFC12sends its cell out through its fabric port18-2to the DLC14-2. The DLC14-2reassembles the packet from the four received cells (the added packet headers providing an order) and sends the packet out of the appropriate network port22. The pre-classification header information in the cells determines the appropriate network port.

The full-mesh configuration ofFIG. 1, having the four SFCs, is a full-line rate configuration, that is, the aggregate bandwidth for transmitting cells from a given DLC to the SLCs (i.e., 480 Gpbs) is greater than the aggregate bandwidth of packets arriving at the given DLC on the network ports22(i.e., 400 Gpbs). The configuration can also be adapted to support various oversubscription permutations for DLCs14. For example, instead of having four SFCs, the distributed chassis architecture10may have only two SFCs12-1,12-2, with each DLC14using only two fabric ports22for communicating with the SFCs, one fabric port22for each of the SFCs12. This permutation of oversubscription has, for example, each DLC on its network side with an aggregate ingress 400 Gbps bandwidth (40 10 Gbps Ethernet Ports) and an aggregate egress 240 Gbps cell-switching bandwidth on its two 120 Gbps fabric ports22for communicating with the two SFCs. Other oversubscription permutations can be practiced.

FIG. 2shows an embodiment of the DLC14including the network ports20in communication with the network processors24-1,24-2through a PHY interface30. In one embodiment, the PHY interface30includes an XFI electrical interface (of a 10 Gigabit Small Form Factor Pluggable Module (XFP)) for each of the network ports22. Each network processor24has a fabric interface (UF)32in communication with buffer memory34over memory channels36. In one embodiment, the buffer memory34is implemented with DDR3 SDRAM (double data rate synchronous dynamic random access memory) devices.

The fabric interface32of each network processor24includes a serializer/deserializer (SerDes), not shown, that preferably provides 24 channels38. The SerDes includes a pair of functional blocks used to convert data between serial and parallel interfaces in each direction. In one embodiment, each SerDes channel 38 operates at a 10.3 Gbps bandwidth; the aggregate bandwidth of the 24 channels being approximately 240 Gbps (or 480 Gbps when taking both fabric interfaces). In another embodiment, each SerDes channel operates at a 25 Gbps bandwidth. The 24 SerDes channels38are grouped into four sets of six channels each.

The DLC14further includes PHYs40-1,40-2,40-3,40-4(generally40) in communication with the four (e.g., standard IB CXP) fabric ports22-1,22-2,22-3,22-4, respectively, of the DLC14. Each of the PHYs40is also in communication with a group of six SerDes channels38from each of the two network processors24-1,24-2(thus, each of the PHYs40supports 12 SerDes channels38).

FIG. 3shows an embodiment of the interface connections between the fabric interfaces32-1,32-2(generally,32) of the two network processors24-1,24-2, respectively, and the standard IB CXP fabric ports22of the DLC14. InFIG. 3, the PHYs40are incorporated into the standard IB CXP fabric ports22. In this embodiment, each standard IB CXP fabric port22supports12lanes, which map to six SerDes channels from each of the two fabric interfaces32-1,32-2. Each fabric interface32provides 24 SerDes channels38divided into four groups of six channels. For each of the fabric interfaces32, one group of six SerDes channels38passes to a different one of the four standard IB CXP fabric ports22. For example, one group of 6 SerDes channels from each fabric interface32-1,32-2maps to the PHYs40-1of the standard IB CXP fabric port22-1, a second group of 6 SerDes channels from each fabric interface32-1,32-maps to standard IB CXP22-2, a third group of 6 SerDes channels from each fabric interface32-1,32-2maps to standard IB CXP22-3, and a fourth group of 6 SerDes channels from each fabric interface32-1,32-2maps to standard IB CXP22-4.

The principles illustrated by the interface connections ofFIG. 3apply to other embodiments of the DLC14. For example, consider an example embodiment of a DLC having four network processors and eight standard IB CXP/PHYs, each supporting 12 lanes.FIG. 4shows an embodiment of the interface connections between the fabric interfaces32-1,32-2,32-3, and32-4of the four network processors and the eight standard IB CXP/PHYs22-1to22-8(generally,22). Further, in this example, the 24 SerDes channels provided by each fabric interface32are partitioned into eight groups of three SerDes channels each. Each group of three SerDes channels of a given fabric interface32is mapped to a different one of the eight standard IB CXP fabric ports22. In addition, three SerDes channels from each of the four fabric interfaces32are mapped to each standard IB CXP fabric port22.

As another example, consider that the DLC14has six network processors (with, accordingly, six fabric interfaces). Each fabric interface provides 24 SerDes channels, which can be partitioned into six groups of two SerDes channels each. Each standard IB CXP fabric port22supports12lanes mapped to 12 SerDes channels, two SerDes channels coming from each of the six fabric interfaces.

Aspects of the described invention may be implemented in one or more integrated circuit (IC) chips manufactured with semiconductor-fabrication processes. The maker of the IC chips can distribute them in raw wafer form (on a single wafer with multiple unpackaged chips), as bare die, or in packaged form. When in packaged form, the IC chip is mounted in a single chip package, for example, a plastic carrier with leads affixed to a motherboard or other higher level carrier, or in a multichip package, for example, a ceramic carrier having surface and/or buried interconnections. The IC chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or of an end product. The end product can be any product that includes IC chips, ranging from electronic gaming systems and other low-end applications to advanced computer products having a display, an input device, and a central processor.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method, and computer program product. Thus, aspects of the present invention may be embodied entirely in hardware, entirely in software (including, but not limited to, firmware, program code, resident software, microcode), or in a combination of hardware and software. All such embodiments may generally be referred to herein as a circuit, a module, or a system. In addition, aspects of the present invention may be in the form of a computer program product embodied in one or more computer readable media having computer readable program code embodied thereon.

The computer readable medium may be a computer readable storage medium, examples of which include, but are not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. As used herein, a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, device, computer, computing system, computer system, or any programmable machine or device that inputs, processes, and outputs instructions, commands, or data. A non-exhaustive list of specific examples of a computer readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), a USB flash drive, an non-volatile RAM (NVRAM or NOVRAM), an erasable programmable read-only memory (EPROM or Flash memory), a flash memory card, an electrically erasable programmable read-only memory (EEPROM), an optical fiber, a portable compact disc read-only memory (CD-ROM), a DVD-ROM, an optical storage device, a magnetic storage device, or any suitable combination thereof.

Program code may be embodied as computer-readable instructions stored on or in a computer readable storage medium as, for example, source code, object code, interpretive code, executable code, or combinations thereof. Any standard or proprietary, programming or interpretive language can be used to produce the computer-executable instructions. Examples of such languages include C, C++, Pascal, JAVA, BASIC, Smalltalk, Visual Basic, and Visual C++.

Transmission of program code embodied on a computer readable medium can occur using any appropriate medium including, but not limited to, wireless, wired, optical fiber cable, radio frequency (RF), or any suitable combination thereof.

The program code may execute entirely on a user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on a remote computer or server. Any such remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).