System and method for optimizing fault tolerant storage controllers

A system and method for optimizing fault tolerant storage controllers includes a fault tolerant hardware component comprised of an input interface, at least two output interfaces and, if necessary, a power source connection. The fault tolerant hardware component may be embedded in a storage controller or separately housed within an enclosure. The fault tolerant hardware component may couple with a host information handling system and with two or more storage controllers, which are connected to mass storage devices to form storage arrays. Multiple fault tolerant hardware components can be coupled with a single host information handling system when it includes multiple host ports. Further, the fault tolerant hardware component may be coupled with other fault tolerant hardware components.

FIELD OF THE INVENTION

The present invention pertains to the field of storage systems. More particularly, the present invention relates to devices, which control data flow between one or more host processing systems and one or more data storage subsystems, wherein the data controller provides decreased host transfer latency and faultless data availability.

BACKGROUND OF THE INVENTION

Storage system users are looking for “fault-less,” one hundred percent availability to their data. To accomplish this, storage systems are designed with redundant components to minimize or eliminate unrecoverable failures. However, current practice is to receive host data, copy it to redundant storage and then notify the host of successful data transfer. This additional data copy step introduces latency into the host transfer, reducing host input/output (I/O) performance and throughput. Consequently, it is a common practice in attempting to eliminate this latency to introduce “dual ported memory” of some sort. While this may decrease latency, it violates the “no single point of failure” goal because the path to the two memories is in itself a single point of failure.

It is common to store large volumes of data on storage systems, which utilize nonvolatile mass storage devices, such as magnetic or optical disks. These storage systems sometimes handle valuable or irreplaceable data. Data maintained by these storage systems may be of vital importance, for example, in business application such as airline reservations, bank account management, electronic fund transfers, shipping and receiving, inventory control, and the like. Consequently, there is also a need to ensure that the valuable data contained in these storage systems is adequately protected against loss or damage.

Therefore, it would be desirable to provide a fault tolerant hardware component, which provides data protection and reduces host transfer latency, increasing host I/O performance and throughput.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a fault tolerant hardware component that includes a single input interface, at least two or more output interfaces and control circuitry (e.g., a processor). The present invention can be embedded within a storage controller subsystem or placed at a distance from the storage controllers within an enclosure. In operation, the fault tolerant hardware component of the present invention allows a host processing system to transfer data to a storage system, one interface mirrors the data to one storage controller while a separate pass through interface, which maximizes I/O performance and throughput, sends the unaltered protocol and host data to a second storage controller.

DETAILED DESCRIPTION OF THE INVENTION

A system and method for optimizing fault tolerant storage controllers includes a fault tolerant hardware component comprised of an input interface, at least two output interfaces and, if necessary, a power source connection. The fault tolerant hardware component may be embedded in a storage controller or separately housed within an enclosure. The fault tolerant hardware component may couple with a host information handling system and with two or more storage controllers, which are connected to mass storage devices to form storage arrays. Multiple fault tolerant hardware components can be coupled with a single host information handling system when it includes multiple host ports. Further, the fault tolerant hardware component may be coupled with other fault tolerant hardware components.

FIGS. 1A and 1Billustrate a fault tolerant hardware component enclosure100. Enclosure100includes an input interface102, a first output interface104and a second output interface106. Further, enclosure100may include a power source connector110, as shown, for connecting enclosure100with an external power source. A variety of power sources may be used such as 12V outlets, battery packs, and the like. Further, a variety of connectors such as hard-wired power cords with adapters or even a hard wired enclosure100may be used. It is also contemplated that a power source may be disposed within enclosure100, such as individual battery slots, battery pack slots and the like.

Input interface102communicatively couples enclosure100with a host information handling system utilizing a Fibre Channel protocol. Input interface102is a universal serial bus port and connects with a host port, also a universal serial bus port, located on the host information handling system. This connection may be provided by using serial ports, IEEE 1394 ports (firewire), IrDA (infrared) ports, and the like, as may be contemplated by one of ordinary skill in the art. This coupling opens a communication link using standard SCSI (Small Computer Systems Interface) protocols. Consequently, operation of the fault tolerant hardware component of the present invention does not depend upon the particular hardware or software configuration of any host information handling system as long as the host information handling system is SCSI compatible. Coupling may occur using a variety of industry standard protocols such as serial SCSI, ESCON and the like.

Enclosure100may include more than one input interface enabling the fault tolerant hardware component to couple with more than one host information handling system.

First output interface104and second output interface106communicatively couple fault tolerant hardware component enclosure100with two separate storage controllers utilizing a Fibre Channel protocol. These interfaces provide data protection through data redundancy and reduce data transfer latency by separating data copy from data processing. These output interfaces may be an Ethernet, ATM, T1, T3, FDDI adapter or any other suitable device, depending upon the nature of the communication links as will be discussed in FIG.2. Coupling may occur using a variety of industry standard protocols such as serial SCSI, ESCON and the like.

First output interface104is a “pass through” interface, which couples with a primary storage controller. This pass through interface allows unaltered protocol and host data to flow freely to the primary storage controller. The primary storage controller is not aware that the fault tolerant hardware component enclosure100is installed between it and the host information handling system does not include a data copy function. Thus, there is no data copy latency through this port and host I/O performance and throughput are not decreased.

Second interface port106is a data “mirror” port. It connects with a second storage controller and mirrors data from the host information handling system to the second storage controller. Consequently, as the second storage controller monitors the host data through the mirror port, the second storage controller places the host data into a cache resulting in data protection through duplication and provides for faultless data availability to the operator of the host information handling system. Even if the primary storage controller should experience a total failure and lose all data, there is a full and complete backup copy of all data accessible through the second storage controller.

Fault tolerant hardware component enclosure100may include more than two output interfaces. Another interface would communicatively couple another storage controller and thus increase data protection through further data redundancy. Fault tolerant hardware component enclosure100includes hardware architecture as described inFIGS. 2A and 2B.

FIGS. 2A and 2Billustrate logical block diagrams of the hardware architecture of the fault tolerant hardware component200and the processor204. Fault tolerant hardware component200includes an input interface202, a processor/control circuitry204, a first output interface206, a second output interface208and a power source210. The power source may be located internally or be peripheral and connected to the fault tolerant hardware component200as discussed in FIG.1. Processor/control circuitry204includes a central processing unit (CPU)218, a random-access memory (RAM)220and a non-volatile storage facility (NVSF)222, each of which is coupled to a bus224. Bus224may represent multiple physical or logical buses, which may be interconnected by various adapters and/or controllers. NVSF222may be, or may include, a read-only memory (ROM), a programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM) and the like. Also coupled to bus224are a input interface212, a primary output interface214and a second output interface216.

Input interface202connects communication path2to fault tolerant hardware component200. This allows fault tolerant hardware component200to communicatively couple with a host information handling system. In this way data transfer from the host information handling system to fault tolerant hardware component200is enabled.

Communication path16enables input interface202to transmit the data to processor204. Input interface212of processor204connects communication path16to processor204. Bus224enables the data received at input interface212to be controlled by CPU218. CPU218includes operational instructions with regards to receipt of data from a host information handling system and directs the flow of data. CPU218operatively enabled through RAM220, through bus224, directs the data to the primary output interface214and the second output interface216.

Primary output interface214connects a communication path18to processor204. Communication path18enables processor204to connect with output interface206. Output interface206, the pass through interface, connects communication path4to fault tolerant hardware component200. Communication path4enables fault tolerant hardware component200to communicatively couple with the primary storage controller. Consequently, unaltered protocol and host data from the host information handling system is passed through to the primary storage controller.

Second output interface216connects a communication path20to processor204. Communication path20enables processor204to connect with output interface208. Output interface208, the data mirror interface, connects communication path6to fault tolerant hardware component200. Communication path6enables fault tolerant hardware component200to communicatively couple with the second storage controller. Consequently, the host data is mirrored to the second storage controller providing data protection through redundancy.

FIG. 3illustrates the hardware architecture of a storage controller300of the present invention according to one embodiment. Storage controller300includes a CPU310, a RAM312, a NVSF314, a mass storage device (MSD)308, each of which is coupled to a bus320. Bus320may represent multiple physical or logical buses, which may be interconnected by various adapters and/or controllers. NVSF314may be, or may include, a read-only memory (ROM), a programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM) and the like. MSD308may be any conventional device that is suitable for non-volatile storage of large volumes of data such as a magnetic disk or tape, an optical storage device such as CD-ROM (Compact Disc-ROM), CD-R (CD-recordable), DVD (Digital Versatile Disc), a magneto-optical (MO) device and the like. Also coupled to bus320are a storage device interface306, a controller device interface304and input/output (I/O) device interfaces316and318. I/O device interfaces316and318are also coupled to separate, external connectors on storage controller300. A host device interface302is coupled to bus320as well as fault tolerant hardware component200via communication link4.

In the preferred embodiment fault tolerant hardware component200is embedded in storage controller300. Consequently, fault tolerant hardware component200connects communication path2to storage controller300, which enables a host information handling system to be connected to storage controller300. It may be contemplated that host device interface302may connect a host information handling system directly to storage controller300and then connect a communication path to fault tolerant hardware component200. In such an instance bus320would be connected to fault tolerant hardware component200.

In the present embodiment fault tolerant hardware component200is also coupled to a separate, external connector on storage controller300, which connects communication path6to fault tolerant hardware component200. Communication path6can connect other storage controllers to fault tolerant hardware component200. Consequently, other storage controllers may be locally or remotely located with respect to storage controller300in which fault tolerant hardware component200is embedded. The connector for communication path6may be an Ethernet, ATM, T1, T3, FDDI adapter or any other suitable device, depending upon the nature of communication path6. Communication path6allows connected storage controllers to signal successful receipt of data, and successful or unsuccessful destage of the data. Additionally, in the case of one storage controller failing, one of the other storage controllers may signal fault tolerant hardware component200to transfer the pass through communication path4(or return it to the original storage controller once it has been repaired).

Controller device interface304connects communication path8to bus320in order to connect a remote storage controller. Controller device interface304may be an Ethernet, ATM, T1, T3, FDDI adapter or any other suitable device, depending upon the nature of the communication path8.

Storage device interfaced306connects communication path10to bus320in order to connect external storage devices. Storage device interface306may be an Ethernet, ATM, T1, T3, FDDI adapter or any other suitable device, depending upon the nature of the communication path10.

I/O device interfaces316and318may be used to connect a keyboard and a monitor to bus320. I/O interface316and318may therefore be used by a systems administrator to perform various functions, such as initially configuring storage controller300, inputting commands and control information to storage controller300or obtaining status information from storage controller300. Further, these interfaces316and318can be used to remotely perform these same functions on a remote storage controller via (local) storage controller300and communication path8.

FIG. 4generally illustrates the storage controller described inFIG. 3except that in this preferred embodiment the fault tolerant hardware component is fault tolerant hardware component enclosure100and is located externally of storage controller400. The ability to place fault tolerant hardware component enclosure100some distance from storage controller400provides a measure of facility protection. Further, it potentially eliminates electrical coupling among the host information handling system and storage controller400. This provides another measure of protection.

FIG. 5illustrates a fault tolerant hardware component100with multiple output interfaces connecting multiple communication paths4,6and12. These communication paths connect multiple storage controllers500-1,500-2through500-N. It is contemplated that any number of output interfaces may be included within fault tolerant hardware component100connecting any number of storage controllers. Fault tolerant hardware component100may also be embedded fault tolerant hardware component200(as shown and described in FIG.3). Storage controller300, ofFIG. 3, may include any number of separate, external connectors, which can couple any number of other storage controllers to fault tolerant hardware component200.

Communication path8communicatively couples the storage controllers to one another. The primary use of communication path8is for secondary storage controller(s) to signal the primary storage controller of successful receipt of mirrored data. The present invention provides a system where the host writes data, which is mirrored to the secondary storage controller(s). The secondary controller(s) will signal the primary controller that the data has been successfully received. Upon receipt of this signal the primary controller sends an “end of operation” to the host. However, if the secondary controller(s) do not signal successful receipt in an expected period of time, the primary controller treats the transfer as synchronous, holding off completion until the data is destaged into physical storage. This prevents multiple-failure data loss as the host does not proceed until the data is in the physical storage device, if the state of the mirrors cannot be ascertained. A similar operation occurs if the secondary controllers signal unsuccessful receipt of data.

FIG. 6illustrates a computing system600in which multiple fault tolerant hardware component enclosures100-1through100-N are connected to a single host information handling system600-1with multiple host ports. Communication path2connects multiple fault tolerant hardware component enclosures100-1through100-N with the host information handling system600-1. The connector for communication path2may be an Ethernet, ATM, T1, T3, FDDI adapter or any other suitable device, depending upon the nature of communication path2.

Each fault tolerant hardware component enclosure, of the present embodiment, is coupled to another fault tolerant hardware component enclosure via a communication link14through an external connector. A portion of a communication link14between two geographically separated fault tolerant hardware components may be provided by a local area network (LAN), such as a Fast Ethernet while other portions of the link14can be implemented as an ATM (Asynchronous Transfer Mode) link, a T1 or T3 link, and FDDI (Fiber Distributed Data Interface) link, Ir (Infrared), or any other suitable type of link. Additionally, each fault tolerant hardware component enclosure is coupled to at least two storage controllers via communication links4and6. These links may follow the same guidelines as mentioned above.

Any number of fault tolerant hardware component enclosures may be connected to a host information handling system. They may be connected in a daisy chain configuration or another configuration as contemplated by one of ordinary skill in the art. Such multiplicity provides redundancy in case of failure of one of the fault tolerant hardware component enclosures.

FIG. 7illustrates a computing system in which a number of fault tolerant hardware components of the present invention provide a number of host information handling systems with access to a number of storage arrays. Specifically, the computing system includes N fault tolerant hardware components,100-1through100-N; N host information handling systems,600-1through600-N, which are coupled to fault tolerant hardware components100-1through100-N, respectively. The computing system further includes N storage controllers,500-1through500-N, which are coupled to fault tolerant hardware components100-1through100-N, respectively; and N storage arrays,700-1through700-N, which are coupled to storage controllers,500-1through500-N, respectively. Each of the storage arrays includes a number of mass storage devices (MSDs) coupled to a storage controller in a daisy chain configuration. Specifically, storage array700-1includes O MSDs,700-1-1through700-1-O; storage array700-2includes P MSDs,700-2-1through700-2-P; storage array700-3includes Q MSDs,700-3-1through700-3-Q; storage array700-4includes R MSDs,700-4-1through700-4-R; storage array700-M includes M MSDs,700-M-1through700-M-S; and storage array700-N includes N MSDs,700-N-1through700-N-T.

As discussed inFIG. 6each fault tolerant hardware component enclosure is coupled to another fault tolerant hardware component enclosure via a communication link14. A portion of a communication link14between two geographically separated fault tolerant hardware components may be provided by a local area network (LAN), such as a Fast Ethernet while other portions of the link14can be implemented as an ATM (Asynchronous Transfer Mode) link, a T1 or T3 link, and FDDI (Fiber Distributed Data Interface) link, Ir (Infrared), or any other suitable type of link. Additionally, each fault tolerant hardware component enclosure is coupled to at least two storage controllers via communication links4and6. These links may follow the same guidelines as mentioned above.

A use of communication path14is for secondary storage controller(s) to signal the primary storage controller of successful receipt of mirrored data. The present invention provides a system where the host writes data, which is mirrored to the secondary storage controller(s). The secondary controller(s) will signal the primary controller that the data has been successfully received. Upon receipt of this signal the primary controller sends an “end of operation” to the host. However, if the secondary controller(s) do not signal successful receipt in an expected period of time, the primary controller treats the transfer as synchronous, holding off completion until the data is destaged into physical storage. This prevents multiple-failure data loss as the host does not proceed until the data is in the physical storage device, if the state of the mirrors cannot be ascertained. A similar operation occurs if the secondary controllers signal unsuccessful receipt of data.

Note that any of the data communication paths2,4,6,8,10and14may actually include two or more redundant, physical paths. Therefore, a failure of any single physical connection does not affect the ability to access any stored data. Communication pathways2,4,6,8,10and14in other embodiments, may be configured for a variety of protocols and standards, such as serial SCSI, Fiber Channel, DAFS (direct access file system), CIFS (common internet file system/services), AppleTalk, Netware, NFS (networked file system), ESCON (enterprise system connection) and the like. Communication pathway12, as discussed inFIG. 5, may also be configured for a similar variety of protocols and standards.

Each of the storage controllers is coupled to another storage controller via a communication link8. This is an independent pathway of communication and allows them to signal successful receipt of data and successful or unsuccessful destage of data. Further, in the case of one storage controller failing, one of the others can signal the fault tolerant hardware component to transfer the “pass through” path (or return it to the original storage controller once it has been repaired). These links may follow the guidelines mentioned above, in this figure, in the discussion of the fault tolerant hardware components.

Each of the host information handling systems may be any conventional information handling system such as a personal computer, a mini-computer, a mainframe and the like. In addition, any of the host information handling systems may function as a server for one or more client information handling systems (not shown).

Each MSD may include a non-volatile facility for storing large volumes of data, such as a magnetic disk or tape, an optical storage device such as CD-ROM (Compact Disc-ROM), CD-R (CD-recordable), DVD (Digital Versatile Disc), a magneto-optical (MO) device and the like. The MSDs within the computing system need not be of the same device type. That is, the MSDs in any given storage array may use a different type of storage medium from those in any other storage array.

Each storage array may be located geographically distant from the other storage arrays. Multiple copies are generally maintained on different, geographically-separated storage arrays. Hence, the loss of one or more MSDs in a given storage array will not result in the complete loss of data. With respect to a given (local) fault tolerant hardware component, any or all of the other (remote) fault tolerant hardware components and storage controllers, host information handling systems and storage arrays may therefore be located at distant locations to the local storage controller.

Each fault tolerant hardware component communicates with its local host information handling system, storage controller and storage array utilizing standard SCSI (Small Computer Systems Interface) protocols. Consequently, operation of a fault tolerant hardware component of the present invention in the manner described herein is not dependent upon the particular hardware of software configuration of any local host information handling system, storage controller or storage array, as long as those devices are SCSI-compatible. However, the data communication links2,4,6,8,10and14may conform to other protocols and standards, such as serial SCSI, Fiber Channel, ESCON and the like. Thus, because data communication links2,4,6,8,10and14are conventional interfaces, a fault tolerant hardware component of the present invention can be used concurrently with host information handling systems, storage controllers and MSDs having different configurations. For instance, one host information handling system in the system may be a mainframe computer while another host information handling system is a personal computer. Similarly, one storage array in the system may include conventional magnetic hard disk drives while another storage array includes CD-ROM drives. Further, the storage controllers themselves may be of dissimilar configuration in order to accommodate the different storage arrays.

The fault tolerant hardware components, communicatively linked, operate in peer-to-peer relationships with each other when responding to the operational environment. For instance, any fault tolerant hardware component can be designated as the local system. Meaning that in the case of failure of the original local fault tolerant hardware component another, which is communicatively linked can take over its functions permanently or until repairs are made and the original is functioning properly again.

The present invention is not limited to the specific configuration shown in FIG.7. For example, the system configuration might alternatively include only a single host information handling system, which is coupled to multiple geographically separated fault tolerant hardware components. The fault tolerant components may be a mixture of embedded fault tolerant hardware component within a storage controller and separate fault tolerant hardware component enclosures. It may be contemplated that the storage controller may have a direct link to the host information handling system and then route the data through the fault tolerant hardware component. Other configurations as contemplated by one of ordinary skill in the art do not depart from the spirit and scope of the present invention.