Gate potential control circuit

A gate potential control circuit includes a driving switching element, a first gate potential supply part, a first switching element, a first resistor, and a first operational amplifier. The first operational amplifier includes an output portion connected to a gate of the first switching element, an inverting input into which a first reference potential is input, and a non-inverting input into which a closer one of a first value and a second value to a potential of the first gate potential supply part is input. The first value is based on a potential difference obtained by subtracting a potential of a terminal of the first resistor on a driving switching element side from a potential of a terminal of the first resistor on a first gate potential supply part side. The second value is based on a potential of a terminal of the first switching element.

INCORPORATION BY REFERENCE

The disclosure of Japanese Patent Application No. 2014-116072 filed on Jun. 4, 2014 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit that controls the potential of a gate of a switching element.

2. Description of Related Art

A circuit that controls the potential of a gate of IGBT is disclosed in International Publication WO2012/014314. This circuit has a pMOS and a resistor that are connected in series between the gate of the IGBT and a driving power supply. An operational amplifier is connected to a gate of the pMOS. The pMOS is controlled by the operational amplifier so that the pMOS can have a constant drain voltage. As a result, the potential of the gate of the IGBT is increased to a predetermined value.

In the technique that is disclosed in International Publication WO2012/014314, the rate of increase of the gate potential of the IGBT is determined by the slew rate of the operational amplifier. Because the slew rate considerably varies among operational amplifiers, the rate of increase of the gate potential of the IGBT varies among the gate potential control circuits of International Publication WO2012/014314.

SUMMARY OF THE INVENTION

The present invention provides a gate potential control circuit that can suppress the influence of the slew rate of an operational amplifier while controlling the gate potential of a switching element using the operational amplifier.

A gate potential control circuit according to a first aspect of the present invention includes a driving switching element, a first gate potential supply part, a first switching element, a first resistor, and a first operational amplifier. The first switching element and the first resistor are connected in series between a gate of the driving switching element and the first gate potential supply part. The first operational amplifier includes an output portion connected to a gate of the first switching element, an inverting input into which a first reference potential is input, and a non-inverting input into which a closer one of a first value and a second value to a potential of the first gate potential supply part is input. The first value is based on a potential difference obtained by subtracting a potential of a terminal of the first resistor on a driving switching element side from a potential of a terminal of the first resistor on a first gate potential supply part side. The second value is based on a potential of a terminal of the first switching element.

According to the first aspect of the present invention, the operational amplifier can accurately control the rate of change of the gate potential of the driving switching element.

A gate potential control circuit according to a second aspect of the present invention includes a driving switching element, a first gate potential supply part, a first switching element, a first resistor, and a first operational amplifier. The first switching element is connected between a gate of the driving switching element and the first gate potential supply part. The first resistor is connected between the driving switching element and the first switching element. The first operational amplifier includes an output portion connected to a gate of the first switching element, a non-inverting input into which a potential of a terminal of the first switching element on a driving switching element side is input, and an inverting input into which a farther one of a first potential and a fourth reference potential from a potential of the first gate potential supply part is input. The first potential is obtained by adding a third reference potential to a potential of a terminal of the first resistor on a driving switching element side.

According to the second aspect of the present invention, the operational amplifier can accurately control the rate of change of the gate potential of the driving switching element.

A gate potential control circuit according to a third aspect of the present invention includes a driving switching element, a first gate potential supply part, a first switching element, a first resistor, and a first operational amplifier. The first switching element and the first resistor are connected in series between a gate of the driving switching element and the first gate potential supply part. The first operational amplifier includes an output portion connected to a gate of the first switching element, and is configured to control a potential of the gate of the first switching element such that an absolute value of a potential difference between both ends of the first resistor is a seventh reference potential or lower and a potential of a terminal of the first switching element on a driving switching element side changes to an eighth reference potential.

According to the third aspect of the present invention, the operational amplifier can accurately control the rate of change of the gate potential of the driving switching element.

DETAILED DESCRIPTION OF EMBODIMENTS

A gate potential control circuit10aof a first embodiment that is shown inFIG. 1controls the potential of a gate12aof an IGBT12. The IGBT12is a switching element for current control that is used in an inverter, DC-DC converter, or the like. It should be noted that an IGBT is used as a driving switching element in this embodiment whereas another type of switching element (such as an MOS) may be used as a driving switching element in other embodiments. The gate potential control circuit10ahas a gate charge circuit20, a gate discharge circuit40, an insulation power supply60, and a controller70.

The insulation power supply60outputs a potential Vout to an output terminal60a. The potential Vout is the highest potential in the gate potential control circuit10a.

The gate charge circuit20is a circuit that supplies electric charge to the gate12aof the IGBT12to turn on the IGBT12. The gate charge circuit20has a pMOS22, a first resistor24, a subtractor26, an amplifier28, a first reference power supply30, a first operational amplifier IC32, and a switch34.

The pMOS22and the first resistor24are connected in series between the gate12aof the IGBT12and the output terminal60aof the insulation power supply60. The pMOS22is connected at a location closer to the insulation power supply60than the first resistor24. The pMOS22has a source22bthat is connected to the output terminal60aof the insulation power supply60. The pMOS22has a drain22athat is connected to a terminal24aof the first resistor24. The first resistor24also has a terminal24bthat is connected to the gate12aof the IGBT12. A potential Va that is shown inFIG. 1is the potential of the terminal24aof the first resistor24, which is equal to the potential of the drain22aof the pMOS22. A potential Vb that is shown inFIG. 1is the potential of the terminal24bof the first resistor24, which is equal to the potential of the gate12aof the IGBT12.

The subtractor26has a plus terminal that is connected to the terminal24aof the first resistor24. The subtractor26has a minus terminal that is connected to the terminal24bof the first resistor24. The subtractor26has an output terminal that is connected to the amplifier28. The subtractor26outputs a potential Va−Vb that is obtained by subtracting the potential Vb of the terminal24bfrom the potential Va of the terminal24a(i.e., the potential difference between both ends of the first resistor24) to the output terminal.

The amplifier28has an input terminal that is connected to the output terminal of the subtractor26. The amplifier28has an output terminal that is connected to the first operational amplifier IC32. The amplifier28outputs a potential that is obtained by multiplying the output potential Va−Vb from the subtractor26by A, which is a constant that is greater than 1. The output potential A(Va−Vb) from the amplifier28is input into the first operational amplifier IC32.

The first reference power supply30has a positive electrode that is connected to the first operational amplifier IC32. The first reference power supply30has a negative electrode that is connected to the ground. The first reference power supply30outputs a first reference potential Vref1.

The first operational amplifier IC32is an IC that has a first operational amplifier32aand a first selector32b. Into the first selector32b, the potential Va of the terminal24aof the first resistor24and the output potential A(Va−Vb) from the amplifier28are input. The first selector32boutputs a higher one of the potential Va and the potential A(Va−Vb).

The first operational amplifier32ahas a non-inverting input, into which the output potential from the first selector32b(i.e., the higher one of the potential Va and the potential A(Va−Vb)) is input. The first operational amplifier32ahas an inverting input, into which the first reference potential Vref1is input. The first operational amplifier32ahas an output portion that is connected to a gate22cof the pMOS22. The first operational amplifier32aoutputs a plus potential when the non-inverting input has a higher potential than the inverting input, and outputs a minus potential when the inverting input has a higher potential than the non-inverting input. In this way, the first operational amplifier32acontrols the potential of the gate22cof the pMOS22so that the potential that is input into the non-inverting input and the potential that is input into the inverting input can be equal to each other.

The switch34is connected between the source22band the gate22cof the pMOS22. The switch34switches a conducting state and a cutoff state between the source22band the gate22c. The switch34is controlled by a signal from the controller70.

The gate discharge circuit40has a second resistor44and an nMOS42. The second resistor44and the nMOS42are connected in series between the gate12aof the IGBT12and a ground80. The nMOS42is connected at a location closer to the ground80than the second resistor44. The nMOS42has a source42bthat is connected to the ground80. The nMOS42has a drain42athat is connected to a terminal44aof the second resistor44. The nMOS42has a gate42cthat is connected to the controller70. The nMOS42performs switching in response to a signal from the controller70. The second resistor44has a terminal44bthat is connected to the gate12aof the IGBT12.

The controller70controls the switch34and the nMOS42.

The operation of the gate potential control circuit10ais next described.FIG. 2shows how the potentials Va and Vb and the potential difference Va−Vb change when the IGBT12is switched from an off state (the state during period T0inFIG. 2) to an on state (the state during period T6inFIG. 2). When the IGBT12is in an off state (i.e., during period T0), the nMOS42is on and the switch34is on (i.e., the pMOS22is off). Thus, a ground potential (0 V) is being applied to the gate12aof the IGBT12. Thus, the potentials Va and Vb are both 0 V.

The controller70turns off the nMOS42and turns off the switch34at time t1inFIG. 2. When the switch34is turned off, the potential of the gate22cof the pMOS22becomes controllable by the first operational amplifier32a. At time t1, because the potential Va and the potential A(Va−Vb) are both generally 0 V (ground potential), the first selector32boutputs a generally 0 V. Thus, a generally 0 V is input into the non-inverting input of the first operational amplifier32a. Because the inverting input has a higher potential (Vref1) than the non-inverting input (0 V), the first operational amplifier32adecreases the potential of the output portion (i.e., the gate22cof the pMOS22). As a result, the pMOS22is turned on, and a gate current flows from the insulation power supply60via the pMOS22and the first resistor24toward the gate12aof the IGBT12. When the pMOS22is turned on at time t1, the gate current increases and the potential difference Va−Vb increases accordingly during the subsequent period T1. In addition, because electric charge is accumulated in the gate12aas the gate current flows, the potential of the gate12agradually increases. Thus, during period T1, the potentials Va and Vb increase. In addition, during period T1, because the potential that is input into the non-inverting input is low, the first operational amplifier32adecreases the output potential (i.e., the potential of the gate22c) according to its slew rate. Thus, during period T1, the potentials Va and Vb increase at a gradient that is determined by the slew rate of the first operational amplifier32a. During period T1, the potential A(Va−Vb) increases faster than the potential Va. Thus, during period T1, the potential A(Va−Vb) continues to be input into the non-inverting input of the first operational amplifier32a.

When the gate current increases during period T1, the potential difference Va−Vb reaches a value Vref1/A at time t2. In other words, A(Va−Vb)=Vref1is fulfilled at time t2. Then, the first operational amplifier32acontrols the potential of the gate22cso that A(Va−Vb)=Vref1can be maintained. Thus, during period T2after time t2, the potential difference Va−Vb is generally constant at Vref1/A. In other words, the gate current is generally constant. Thus, during period T2after time t2, the potentials Va and Vb increase at a gradient that is determined by the constant gate current. The potentials Va and Vb maintain a generally constant value during period T3after time t3. This is because electric charge is charged into the Miller capacity of the IGBT12. During period T3, the gate current (i.e., the potential difference Va−Vb) is still generally constant. After that, the charge of electric charge into the Miller capacity is completed at time t4. Thus, during period T4after time t4, the potentials Va and Vb increase again. Because the gate current is still generally constant during period T4, the potentials Va and Vb increase during period T4at generally the same gradient as that during period T2. When the potential Va reaches the first reference potential Vref1at time t5, the potential Va has become higher than the potential A(Va−Vb). Thus, the first selector32binputs the potential Va into the non-inverting input of the first operational amplifier32a. Then, the first operational amplifier32acontrols the potential of the gate22cso that the potential Va can be maintained at the first reference potential Vref1. As a result, the gate current decreases, and the potential difference Va−Vb decreases accordingly. Because the potential difference Va−Vb decreases in this way, the potential Va continues to be input into the non-inverting input of the first operational amplifier32aduring period T5after time t5. Thus, during period T5, the pMOS22is controlled so that the potential Va can be equal to the first reference potential Vref1. Thus, the gate current gradually decreases during period T5, and the gate current (i.e., the potential difference Va−Vb) becomes generally zero at time t6when the potential Vb increases to a potential equal to the first reference potential Vref1. After that, the first operational amplifier32amaintains a state where the potentials Va and Vb are equal to the first reference potential Vref1. Because the potential Vb is the potential of the gate12aof the IGBT12, the IGBT12is turned on when the potential Vb is controlled to the first reference potential Vref1.

To turn off the IGBT12, the controller70turns on the switch34and the nMOS42. When the switch34is turned on, the pMOS22is turned off and the supply of electric charge to the gate12ais stopped. In addition, when the nMOS42is turned on, electric charge is discharged from the gate12ato the ground80, and the potential of the gate12adecreases to the ground potential. As a result, the IGBT12is turned off.

As described above, in this gate potential control circuit10a, the pMOS22is controlled so that the potential difference Va−Vb between both ends of the first resistor24cannot exceed a predetermined potential Vref1/A when the IGBT12is turned on. Thus, during periods T2to T4, the potential difference Va−Vb (i.e., the gate current) is constant and the gradient at which the potentials Va and Vb increase is controlled to a gradient that is determined by the gate current. In other words, during periods T2and T4, the gradient at which the potentials Va and Vb increase is controlled to a generally constant gradient that is smaller than a gradient that is determined by the slew rate. Thus, when the IGBT12is turned on using this gate potential control circuit10a, the IGBT12can be turned on at a generally constant speed with little influence of the slew rate of the first operational amplifier32a. Thus, when this gate potential control circuits10aare produced on a large scale, the variation in switching speed among the gate potential control circuits10acan be reduced with little influence of the variation in slew rate among the first operational amplifiers32a. In addition, the potential Vb of the gate12aof the IGBT12can be accurately controlled to the potential Vref1during period T6by the first operational amplifier32a. In other words, with this gate potential control circuit10a, the turn-on speed of the IGBT12is unlikely to vary considerably and the potential of the gate12aof the IGBT12is unlikely to vary considerably.

A gate potential control circuit10bof a second embodiment that is shown inFIG. 3is different from the gate potential control circuit10aof the first embodiment in configuration of the insulation power supply60and the gate discharge circuit40.

The insulation power supply60of the second embodiment has an output terminal60b. To the output terminal60b, a minus potential V-out (a potential that is lower than that of the ground) is output. The potential V-out is the lowest potential in the gate potential control circuit10b.

The gate discharge circuit40of the second embodiment is a circuit that discharges electric charge from the gate12aof the IGBT12to turn off the IGBT12. The gate discharge circuit40has an nMOS42, a second resistor44, a subtractor46, an amplifier48, a second reference power supply50, a second operational amplifier IC52, and a switch54.

The nMOS42and the second resistor44are connected in series between the gate12aof the IGBT12and the minus side output terminal60bof the insulation power supply60. The nMOS42is connected at a location closer to the output terminal60bof the insulation power supply60than the second resistor44. The nMOS42has a source42bthat is connected to the output terminal60bof the insulation power supply60.

The nMOS42has a drain42athat is connected to a terminal44aof the second resistor44. The second resistor44has a terminal44bthat is connected to the gate12aof the IGBT12. A potential Vc that is shown inFIG. 3is the potential of the terminal44aof the second resistor44, which is equal to the potential of the drain42aof the nMOS42. The potential Vb is equal to the potential of the terminal44bof the second resistor44.

The subtractor46has a plus terminal that is connected to the terminal44aof the second resistor44. The subtractor46has a minus terminal that is connected to the terminal44bof the second resistor44. The subtractor46has an output terminal that is connected to the amplifier48. The subtractor46outputs a potential (Vc−Vb) that is obtained by subtracting the potential (Vb) of the terminal44bfrom the potential (Vc) of the terminal44ato the output terminal. Because Vc<Vb, the potential Vc−Vb is a minus potential.

The amplifier48has an input terminal that is connected to the output terminal of the subtractor46. The amplifier48has an output terminal that is connected to the second operational amplifier IC52. The amplifier48outputs a potential that is obtained by multiplying the output potential (Vc−Vb) from the subtractor46by A. The output potential A(Vc−Vb) from the amplifier48is input into the second operational amplifier IC52.

The second reference power supply50has a positive electrode that is connected to the ground. The second reference power supply50has a negative electrode that is connected to the second operational amplifier IC52. The second reference power supply50outputs a second reference potential Vref2. The second reference potential Vref2is a minus potential that is lower than that of the ground.

The second operational amplifier IC52is an IC that has a second operational amplifier52aand a second selector52b. Into the second selector52b, the potential Vc of the terminal44aof the second resistor44and the output potential A(Vc−Vb) from the amplifier48are input. The second selector52boutputs a lower one of the potential Vc and the potential A(Vc−Vb).

The second operational amplifier52ahas a non-inverting input, into which the output potential from the second selector52b(i.e., the lower one of the potential Vc and the potential A(Vc−Vb)) is input. The second operational amplifier52ahas an inverting input, into which the second reference potential Vref2is input. The second operational amplifier52ahas an output portion that is connected to the gate42cof the nMOS42. The second operational amplifier52aoutputs a plus potential when the non-inverting input has a higher potential than the inverting input, and outputs a minus potential when the inverting input has a higher potential than the non-inverting input. In this way, the second operational amplifier52acontrols the potential of the gate42cof the nMOS42so that the potential that is input into the non-inverting input and the potential that is input into the inverting input can be equal to each other.

The switch54is connected between the source42band the gate42cof the nMOS42. The switch54switches the state between the source42band the gate42cbetween a conducting state and a cutoff state. The switch54is controlled by a signal from the controller70.

The operation of the gate potential control circuit10bis next described.FIG. 4shows how the potentials Va and Vb and the potential difference Va−Vb change when the IGBT12is switched from an off state (the state during period T0inFIG. 4) to an on state (the state during period T6inFIG. 4). As shown inFIG. 4, during period T0when the IGBT12is off, the potentials Va and Vb are equal to the second reference potential Vref2(minus potential). In other words, the second reference potential Vref2is being applied to the gate12aof the IGBT12. To turn on the IGBT12, the controller70turns on the switch54and turns off the switch34. When the switch54is turned on, the nMOS42is turned off. When the switch34is turned off, the gate charge circuit20increases the potentials Va and Vb to the first reference potential Vref1. This operation is the same as the operation in the first embodiment except that the potential Vref2that is output when the IGBT12is off is a minus potential.

The operation that is performed in the gate potential control circuit10bwhen the IGBT12is turned off is next described.FIG. 5shows how the potentials Vb and Vc and the potential difference Vc−Vb change when the IGBT12is switched from an on state (the state during period T0inFIG. 5) to an off state (the state during period T6inFIG. 5). As described above, during the period when the IGBT12is on (period T0inFIG. 5), the switch54is on and the switch34is off. The controller70turns off the switch54and turns on the switch34at time t1inFIG. 5. When the switch34is turned on, the pMOS22is turned off. When the switch54is turned off, the potential of the gate42cof the nMOS42becomes controllable by the second operational amplifier52a. At time t1, the potential Vb and the potential Vc are both equal to the first reference potential Vref1. Thus, output potential A(Vc−Vb) from the amplifier48is generally 0 V. Thus, because the potential A(Vc−Vb) is lower than the potential Vc (=Vref1), the second selector52binputs the potential A(Vc−Vb) into the non-inverting input of the second operational amplifier52a. Because the non-inverting input has a higher potential (0 V) than the inverting input (Vref2: minus potential), the second operational amplifier52aincreases the potential of the output portion (i.e., the gate42cof the nMOS42). As a result, the nMOS42is turned on, and a gate current flows from the gate12aof the IGBT12via the second resistor44and the nMOS42toward the output terminal60bof the insulation power supply60. When the nMOS42is turned on at time t1, the gate current increases and potential difference Vc−Vb decreases (the absolute value of the potential difference Vc−Vb increases) accordingly during the subsequent period T1. In addition, because electric charge is discharged from the gate12aas the gate current flows, the potential of the gate12agradually decreases. Thus, during period T1, the potentials Vb and Vc decrease. In addition, during period T1, because the potential that is input into the non-inverting input is low, the first operational amplifier32adecreases the output potential (i.e., the potential of the gate42c) in accordance with its slew rate. Thus, during period T1, the potentials Vb and Vc decrease at a gradient that is determined by the slew rate of the second operational amplifier52a. During period T1, the potential A (Vc−Vb) decreases faster than the potential Vc. Thus, the potential A(Vc−Vb) continues to be input into the non-inverting input of the second operational amplifier52a.

When the gate current increases during period T1, the potential difference Vc−Vb reaches a value Vref2/A at time t2. In other words, A(Vc−Vb)=Vref2is fulfilled at time t2. Then, the second operational amplifier52acontrols the potential of the gate42cso that A(Vc−Vb)=Vref2can be maintained Thus, during period T2after time t2, the potential difference Vc−Vb is generally constant at Vref2/A. In other words, the gate current is generally constant. Thus, during period T2after time t2, the potentials Vb and Vc decrease at a gradient that is determined by the constant gate current. The potentials Vb and Vc maintain a generally constant value during period T3after time t3. This is because electric charge is discharged from the Miller capacity of the IGBT12. During period T3, the gate current (i.e., the potential difference Vc−Vb) is still generally constant. After that, the discharge of electric charge from the Miller capacity is completed at time t4. Thus, during period T4after time t4, the potentials Vb and Vc decrease again. Because the gate current is still generally constant during period T4, the potentials Vb and Vc decrease during period T4at generally the same gradient as that during period T2. When the potential Vc reaches the second reference potential Vref2at time t5, the potential Vc has become lower than the potential A(Vc−Vb). Thus, the potential Vc is input into the non-inverting input of the second operational amplifier52a. Then, the second operational amplifier52acontrols the potential of the gate42cso that the potential Vc can be maintained at the second reference potential Vref2. As a result, the gate current decreases, and the potential difference Vc−Vb increases (approaches 0 V) accordingly. Because the potential difference Vc−Vb increases in this way, the potential Vc continues to be input into the non-inverting input of the second operational amplifier52aduring period T5after time t5. Thus, during period T5, the nMOS42is controlled so that the potential Vc can be equal to the second reference potential Vref2. Thus, the gate current gradually decreases during period T5, and the gate current (i.e., the potential difference Vc−Vb) becomes generally zero at time t6when the potential Vb decreases to a potential equal to the second reference potential Vref2. After that, the second operational amplifier52amaintains a state where the potentials Vc and Vb are equal to the second reference potential Vref2. Because the potential Vb (i.e., the potential of the gate12aof the IGBT12) is controlled to the second reference potential Vref2(a low potential), the IGBT12is turned off.

As described above, in this gate potential control circuit10b, the nMOS42is controlled so that the potential difference Vc−Vb between both ends of the second resistor44cannot fall below a predetermined potential Vref2/A (i.e., the absolute value of the potential difference Vc−Vb cannot exceed the absolute value of the potential Vref2/A) when the IGBT12is turned off. Thus, during periods T2to T4, the potential difference Vc−Vb (i.e., the gate current) is constant and the gradient at which the potentials Vb and Vc decrease is controlled to a gradient that is determined by the gate current. In other words, during periods T2and T4, the gradient at which the potentials Vb and Vc decrease is controlled to a generally constant gradient that is smaller than a gradient that is determined by the slew rate. Thus, when the IGBT12is turned off using the gate potential control circuit10b, the IGBT12can be turned off at a generally constant speed with little influence of the slew rate of the second operational amplifier52a. In other words, with the gate potential control circuit10bof the second embodiment, the IGBT12can be turned on or off with little influence of the slew rate of the operational amplifier. As a result, the variation in switching speed among the IGBTs12can be reduced during mass production. In addition, the potentials Va, Vb and Vc can be accurately controlled in the gate potential control circuit10b.

The IGBT12of the first and second embodiments may be regarded as one example of the driving switching element of the present invention. The output terminal60aof the insulation power supply60of the first and second embodiments may be regarded as one example of the first gate potential supply part of the present invention. The first resistor24of the first and second embodiments may be regarded as one example of the first resistor of the present invention. The pMOS22of the first and second embodiments may be regarded as one example of the first switching element of the present invention. The first operational amplifier32aof the first and second embodiments may be regarded as one example of the first operational amplifier of the present invention. It should be noted that a greater one of the potential Va and the value A(Va−Vb) based on the potential difference Va−Vb (i.e., a value closer to the output potential Vout from the insulation power supply60), is input into the non-inverting input of the first operational amplifier32aof the first and second embodiments. The potential Vrefl/A of the first and second embodiments may be regarded as one example of the seventh reference potential of the present invention. The first reference potential Vref1of the first and second embodiments may be regarded as one example of the first reference potential of the present invention and also as one example of the eighth reference potential of the present invention. The output terminal60bof the insulation power supply60of the second embodiment may be regarded as one example of the second gate potential supply part of the present invention. The nMOS42of the second embodiment may be regarded as one example of the second switching element of the present invention. The second resistor44of the second embodiment may be regarded as one example of the second resistor of the present invention. The second operational amplifier52aof the second embodiment may be regarded as one example of the second operational amplifier of the present invention. The potential Vref2/A of the second embodiment may be regarded as one example of the ninth reference potential of the present invention. The second reference potential Vref2of the second embodiment may be regarded as one example of the second reference potential of the present invention and also as one example of the tenth reference potential of the present invention. The constituent elements of the second embodiment and the constituent elements of the present invention can also be recognized as follows. The IGBT12of the second embodiment may be regarded as one example of the driving switching element of the present invention. The output terminal60bof the insulation power supply60of the second embodiment may be regarded as one example of the first gate potential supply part of the present invention. The second resistor44of the second embodiment may be regarded as one example of the first resistor of the present invention. The nMOS42of the second embodiment may be regarded as one example of the first switching element of the present invention. The second operational amplifier52aof the second embodiment may be regarded as one example of the first operational amplifier of the present invention. It should be noted that a smaller one of the value A(Vc−Vb) based on the potential difference Vc−Vb and the potential Vc (i.e., a value closer to the output potential V-out from the insulation power supply60), is input into the non-inverting input of the second operational amplifier52aof the second embodiment. As described above, the first gate potential supply part of the present invention may be a gate-on potential (for example, the output potential Vout from the insulation power supply60of the first and second embodiments) that is used to turn on a driving switching element (i.e., to increase the gate potential of the IGBT), or may be a gate-off potential (for example, the output potential V-out from the insulation power supply60of the second embodiment) that is used to turn off a driving switching element (i.e., to decrease the gate potential of the IGBT). In this case, the potential Vref2/A of the second embodiment may be regarded as one example of the seventh reference potential of the present invention. The second reference potential Vref2of the second embodiment may be regarded as one example of the eighth reference potential of the present invention and also as one example of the first reference potential of the present invention.

In addition, third resistors101and102may be added to the configuration of the second embodiment as shown inFIG. 6. The third resistor101is connected between the first resistor24and the gate12aof the IGBT12. The third resistor102is connected between the gate12aof the IGBT12and the second resistor44. According to this configuration, there is no possibility that the potential difference between both ends of the third resistor101or102is input into the operational amplifier. Thus, even when the resistance values of the third resistors101and102are changed, the operation of the operational amplifier is hardly affected. Thus, gate resistance can be adjusted with little influence on the operation of the operational amplifier by replacing the third resistors101and102. This improves the design flexibility. Alternatively, an additional third resistor103may be added to a current pathway that is commonly used both in charging and discharging the gate12aof the IGBT12as shown inFIG. 7. Even with the configuration that is shown inFIG. 7, the gate resistance can be adjusted with little influence on the operation of the operational amplifier. In addition, a third resistor may be added between the terminal24band the gate12aof the gate potential control circuit10aof the first embodiment that is shown inFIG. 1in the same manner as the third resistor101that is shown inFIG. 6or the third resistor103that is shown inFIG. 7.

In the circuits of the first and second embodiments and the circuits that are shown inFIGS. 6 and 7, the positions of the first resistor24and the pMOS22may be swapped. In addition, in the circuit of the second embodiment and the circuits that are shown inFIGS. 6 and 7, the positions of the second resistor44and the nMOS42may be swapped. For example, the circuit that is shown inFIG. 6may be changed as shown inFIG. 8. In this circuit, a value A(Va−Vb) that is obtained by multiplying the potential difference between both ends of the first resistor24and a potential Va2of the drain22aof the pMOS22are input into the first selector32bas in the case of the circuits of the first and second embodiments and the circuits that are shown inFIGS. 6 and 7. In addition, in this circuit, the potential difference (Vc−Vb) between both ends of the second resistor44and a potential Vc2of the drain42aof the nMOS42are input into the second selector52bas in the case of the circuit of the second embodiment and the circuits that are shown inFIGS. 6 and 7. Even when the arrangement is changed as shown inFIG. 8, the same operation as that in the circuits of the first and second embodiments and the circuits that are shown inFIGS. 6 and 7is possible.

A gate potential control circuit10cof a third embodiment that is shown inFIG. 9controls the potential of the gate12aof the IGBT12. The gate potential control circuit10cof the third embodiment is the same in configuration as the circuit of the first embodiment except for the configuration of the gate charge circuit20.

In the third embodiment, the gate charge circuit20has a pMOS22, a first resistor24, an adder35, a third reference power supply36, a fourth reference power supply37, a first operational amplifier IC32, and a switch34.

The pMOS22and the first resistor24are connected in series between the gate12aof the IGBT12and the output terminal60aof the insulation power supply60as in the case of the first embodiment. A potential Vd that is shown inFIG. 9is the potential of the terminal24aof the first resistor24, which is equal to the potential of the drain22aof the pMOS22. A potential Ve that is shown inFIG. 9is the potential of the terminal24bof the first resistor24, which is equal to the potential of the gate12aof the IGBT12.

The third reference power supply36has a positive electrode that is connected to the adder35. The third reference power supply36has a negative electrode that is connected to the ground. The third reference power supply36outputs a third reference potential Vref3.

One of input terminals of the adder35is connected to the terminal24bof the first resistor24. The other input terminal of the adder35is connected to the positive electrode of the third reference power supply36. The adder35has an output terminal that is connected to the first operational amplifier IC32. The adder35outputs a potential Ve+Vref3that is obtained by adding the third reference potential Vref3to the potential Ve of the terminal24bto the output terminal.

The fourth reference power supply37has a positive electrode that is connected to the first operational amplifier IC32. The fourth reference power supply37has a negative electrode that is connected to the ground. The fourth reference power supply37outputs a fourth reference potential Vref4. The fourth reference potential Vref4is higher than the third reference potential Vref3.

The first operational amplifier IC32has a first operational amplifier32aand a first selector32b. Into the first selector32b, the potential Ve+Vref3that is output from the adder35and the fourth reference potential Vref4that is output from the fourth reference power supply37are input. The first selector32boutputs a lower one of the potential Ve+Vref3and the potential Vref4.

The first operational amplifier32ahas an inverting input, into which the output potential from the first selector32b(i.e., the lower one of the potential Ve+Vref3and the potential Vref4) is input. The first operational amplifier32ahas a non-inverting input, into which the potential Vd is input. The first operational amplifier32ahas an output portion that is connected to a gate22cof the pMOS22. The first operational amplifier32aoutputs a plus potential when the non-inverting input has a higher potential than the inverting input, and outputs a minus potential when the inverting input has a higher potential than the non-inverting input. In this way, the first operational amplifier32acontrols the potential of the gate22cof the pMOS22so that the potential that is input into the non-inverting input and the potential that is input into the inverting input can be equal to each other.

The switch34is connected between the source22band the gate22cof the pMOS22. The switch34switches the state between the source22band the gate22cbetween a conducting state and a cutoff state. The switch34is controlled by a signal from the controller70.

The operation of the gate potential control circuit10cis next described.FIG. 10shows how the potentials Vd and Ve and the potential difference Vd−Ve change when the IGBT12is switched from an off state (the state during period T0inFIG. 10) to an on state (the state during period T6inFIG. 10). When the IGBT12is in an off state (i.e., during period T0), the nMOS42is on and the switch34is on (i.e., the pMOS22is off). Thus, a ground potential (0 V) is being applied to the gate12aof the IGBT12. Thus, the potentials Vd and Ve are both 0 V.

The controller70turns off the nMOS42and turns off the switch34at time t1inFIG. 10. When the switch34is turned off, the potential of the gate22cof the pMOS22becomes controllable by the first operational amplifier32a. At time t1, because the potential Ve is generally 0 V (ground potential), the output potential Ve+Vref3from the adder35is equal to the third reference potential Vref3. Because the third reference potential Vref3is lower than the fourth reference potential Vref4, the first selector32binputs the third reference potential Vref3into the inverting input of the first operational amplifier32a. Because the inverting input has a higher potential (Vref3) than the non-inverting input (Vd=0 V), the first operational amplifier32adecreases the potential of the output portion (i.e., the gate22cof the pMOS22). As a result, the pMOS22is turned on, and a gate current flows from the insulation power supply60via the pMOS22and the first resistor24toward the gate12aof the IGBT12. When the pMOS22is turned on at time t1, the gate current increases and the potential difference Vd−Ve increases accordingly during the subsequent period T1. In addition, because electric charge is accumulated in the gate12aas the gate current flows, the potential of the gate12agradually increases. Thus, during period T1, the potentials Vd and Ve increase. In addition, during period T1, because the potential Vd that is input into the non-inverting input is low, the first operational amplifier32adecreases the output potential (i.e., the potential of the gate22c) in accordance with its slew rate. Thus, during period T1, the potentials Vd and Ve increase at a gradient that is determined by the slew rate of the first operational amplifier32a. Even after time t1, because the potential Ve+Vref3is still lower than the fourth reference potential Vref4, the potential Ve+Vref3continued to be input into the inverting input of the first operational amplifier32a.

When the gate current increases during period T1, the potential difference Vd−Ve reaches the third reference potential Vref3at time t2. In other words, Vd=Ve+Vref3is fulfilled at time t2. In other words, the inverting input and the non-inverting input of the first operational amplifier32ahave generally the same potential. Then, the first operational amplifier32acontrols the potential of the gate22cso that the relationship Vd=Ve+Vref3can be maintained. Thus, during period T2after time t2, the potential difference Vd−Ve is generally constant at the third reference potential Vref3. In other words, the gate current is generally constant. Thus, during period T2after time t2, the potentials Vd and Ve increase at a gradient that is determined by the constant gate current. The potentials Vd and Ve maintain a generally constant value during period T3after time t3. This is because electric charge is charged into the Miller capacity of the IGBT12. During period T3, the gate current (i.e., the potential difference Vd−Ve) is still generally constant. After that, the charge of electric charge into the Miller capacity is completed at time t4. Thus, during period T4after time t4, the potentials Vd and Ve increase again. Because the gate current is still generally constant during period T4, the potentials Vd and Ve increase during period T4at generally the same gradient as that during the period T2. When the potential Vd reaches the fourth reference potential Vref4at time t5, the potential Ve+Vref3has become higher than the fourth reference potential Vref4. Thus, the first selector32binputs the fourth reference potential Vref4into the inverting input of the first operational amplifier32a. Then, the first operational amplifier32acontrols the potential of the gate22cso that the potential Vd can be maintained at the fourth reference potential Vref4. As a result, the gate current decreases, and the potential difference Vd−Ve decreases accordingly. However, because the gate current continues to flow even after that, the potential Ve continues to increase during period T5. Thus, during period T5, the fourth reference potential Vref4continues to be input into the inverting input of the first operational amplifier32a. Thus, during period T5, the pMOS22is controlled so that the potential Vd can be equal to the fourth reference potential Vref4. Thus, the gate current gradually decreases during period T5, and the gate current (i.e., the potential difference Vd−Ve) becomes generally zero at time t6when the potential Ve increases to a potential equal to the fourth reference potential Vref4. After that, the first operational amplifier32amaintains a state where the potentials Vd and Ve are equal to the fourth reference potential Vref4. Thus, the IGBT12is turned on. After that, to turn off the IGBT12, the nMOS42is turned on and the pMOS22is turned off as in the case of the first embodiment.

As described above, in this gate potential control circuit10c, the pMOS22is controlled so that the potential difference Vd−Ve between both ends of the first resistor24cannot exceed a predetermined potential Vref3when the IGBT12is turned on. Thus, during periods T2to T4, the potential difference Vd−Ve (i.e., the gate current) is constant and the gradient at which the potentials Vd and Ve increase is controlled to a gradient that is determined by the gate current. In other words, during periods T2and T4, the gradient at which the potentials Vd and Ve increase is controlled to a generally constant gradient that is smaller than a gradient that is determined by the slew rate. Thus, with this gate potential control circuit10c, variation in switching speed is reduced. In addition, the potentials Vd and Ve can be accurately controlled by the first operational amplifier32a.

A gate potential control circuit10dof a fourth embodiment that is shown inFIG. 11is different from the gate potential control circuit10cof the third embodiment in configuration of the insulation power supply60and the gate discharge circuit40.

The insulation power supply60of the fourth embodiment has an output terminal60b. To the output terminal60b, a minus potential V-out (a potential that is lower than that of the ground) is output. The potential V-out is the lowest potential in the gate potential control circuit10d.

The gate discharge circuit40of the fourth embodiment has an nMOS42, a second resistor44, an adder55, a fifth reference power supply56, a sixth reference power supply57, a second operational amplifier IC52, and a switch54.

The nMOS42and the second resistor44are connected in series between the gate12aof the IGBT12and the minus side output terminal60bof the insulation power supply60as in the case of the second embodiment. A potential Vf that is shown inFIG. 11is the potential of the terminal44aof the second resistor44, which is equal to the potential of the drain42aof the nMOS42. The potential Ve is equal to the potential of the terminal44bof the second resistor44.

The fifth reference power supply56has a negative electrode that is connected to the adder55. The fifth reference power supply56has a positive electrode is connected to the ground. The fifth reference power supply56outputs a fifth reference potential Vref5. The fifth reference potential Vref5is a minus potential that is lower than that of the ground.

One of input terminals of the adder55is connected to the terminal44bof the second resistor44. The other input terminal of the adder55is connected to the negative electrode of the fifth reference power supply56. The adder55has an output terminal that is connected to the second operational amplifier IC52. The adder55outputs a potential Ve+Vref5that is obtained by adding the fifth reference potential Vref5to the potential Ve of the terminal44bto the output terminal.

The sixth reference power supply57has a negative electrode that is connected to the second operational amplifier IC52. The sixth reference power supply57has a positive electrode that is connected to the ground. The sixth reference power supply57outputs a sixth reference potential Vref6. The sixth reference potential Vref6is a minus potential that is lower than that of the ground. The sixth reference potential Vref6is lower than the fifth reference potential Vref5(i.e., the absolute value of the sixth reference potential Vref6is greater than the absolute value of the fifth reference potential Vref5).

The second operational amplifier IC52has a second operational amplifier52aand a second selector52b. Into the second selector52b, the potential Ve+Vref5that is output from the adder55and the sixth reference potential Vref6that is output from the sixth reference power supply57are input. The second selector52boutputs a higher one of the potential Ve+Vref5and the potential Vref6.

The second operational amplifier52ahas an inverting input, into which the output potential from the second selector52b(i.e., the higher one of the potential Ve+Vref5and the potential Vref6) is input. The second operational amplifier52ahas a non-inverting input, into which the potential Vf is input. The second operational amplifier52ahas an output portion that is connected to the gate42cof the nMOS42. The second operational amplifier52aoutputs a plus potential when the non-inverting input has a higher potential than the inverting input, and outputs a minus potential when the inverting input has a higher potential than the non-inverting input. In this way, the second operational amplifier52acontrols the potential of the gate42cof the nMOS42so that the potential that is input into the non-inverting input and the potential that is input into the inverting input can be equal to each other.

The switch54is connected between the source42band the gate42cof the nMOS42. The switch54switches the state between the source42band the gate42cbetween a conducting state and a cutoff state. The switch54is controlled by a signal from the controller70.

The operation of the gate potential control circuit10dis next described.FIG. 12shows how the potentials Vd and Ve and the potential difference Vd−Ve change when the IGBT12is switched from an off state (the state during period T0inFIG. 12) to an on state (the state during period T6inFIG. 12). As shown inFIG. 12, during period T0when the IGBT12is off, the potentials Vd and Ve are equal to the sixth reference potential Vref6(minus potential). In other words, the sixth reference potential Vref6is being applied to the gate12aof the IGBT12. To turn on the IGBT12, the controller70turns on the switch54and turns off the switch34. When the switch54is turned on, the nMOS42is turned off. When the switch34is turned off, the gate charge circuit20increases the potentials Vd and Ve to the fourth reference potential Vref4. This operation is the same as the operation in the first embodiment except that the potential Vref6that is output when the IGBT12is off is a minus potential.

The operation that is performed in the gate potential control circuit10dwhen the IGBT12is turned off is next described.FIG. 13shows how the potentials Ve and Vf and the potential difference Vf−Ve change when the IGBT12is switched from an on state (the state during period T0inFIG. 13) to an off state (the state during period T6inFIG. 13). As described above, during the period when the IGBT12is on (period T0inFIG. 13), the switch54is on and the switch34is off. The controller70turns off the switch54and turns on the switch34at time t1inFIG. 13. When the switch34is turned on, the pMOS22is turned off. When the switch54is turned off, the potential of the gate42cof the nMOS42becomes controllable by the second operational amplifier52a. At time t1, because the potential Ve is equal to the fourth reference potential Vref4, the output potential Ve+Vref5from the adder55is equal to the potential Vref4+Vref5. At this stage, the potential Vref4+Vref5is higher than the sixth reference potential Vref6. Thus, the second selector52binputs the potential Vref4+Vref5into the inverting input of the second operational amplifier52a. Because the non-inverting input has a higher potential (Vf=Vref4) than the inverting input (Vref4+Vref5), the second operational amplifier52aincreases the potential of the output portion (i.e., the gate42cof the nMOS42). As a result, the nMOS42is turned on, and a gate current flows from the gate12aof the IGBT12via the second resistor44and the nMOS42toward the output terminal60bof the insulation power supply60. When the nMOS42is turned on at time t1, the gate current increases and the potential difference Vf−Ve decreases (the absolute value of the potential difference Vf−Ve increases) accordingly during the subsequent period T1. In addition, because electric charge is discharged from the gate12aas the gate current flows, the potential of the gate12agradually decreases. Thus, during period T1, the potentials Ve and Vf decrease. During period T1, because the potential Vf that is input into the non-inverting input is high, the second operational amplifier52aincreases the output potential (i.e., the potential of the gate42c) in accordance with its slew rate. Thus, during period T1, the potentials Ve and Vf decrease at a gradient that is determined by the slew rate of the second operational amplifier52a. Even after time t1, because the potential Ve+Vref5is still higher than the sixth reference potential Vref6, the potential Ve+Vref5continues to be input into the inverting input of the second operational amplifier52a.

When the gate current increases during period T1, the potential difference Vf−Ve reaches the fifth reference potential Vref5at time t2. In other words, Vf =Ve+Vref5is fulfilled at time t2. In other words, the inverting input and the non-inverting input of the first operational amplifier32ahave generally the same potential. Then, the second operational amplifier52acontrols the potential of the gate42cso that the relationship Vf =Ve+Vref5can be maintained. Thus, during period T2after time t2, the potential difference Vf−Ve is generally constant at the fifth reference potential Vref5. In other words, the gate current is generally constant. Thus, during period T2after time t2, the potentials Ve and Vf decrease at a gradient that is determined by the constant gate current. The potentials Ve and Vf maintain a generally constant potential during period T3after time t3. This is because electric charge is discharged from the Miller capacity of the IGBT12. During period T3, the gate current (i.e., the potential difference Vf−Ve) is still generally constant. After that, the discharge of electric charge from the Miller capacity is completed at time t4. Thus, during period T4after time t4, the potentials Ve and Vf decrease again. Because the gate current is still generally constant during period T4, the potentials Ve and Vf decrease during period T4at generally the same gradient as that during period T2. When the potential Vf reaches the sixth reference potential Vref6at time t5, the potential Ve+Vref5has become lower than the sixth reference potential Vref6. Thus, the second selector52binputs the sixth reference potential Vref6into the inverting input of the second operational amplifier52a. Then, the second operational amplifier52acontrols the potential of the gate42cso that the potential Vf can be maintained at the sixth reference potential Vref6. As a result, the gate current decreases, and the potential difference Vf−Ve decreases accordingly. However, because the gate current continues to flow even after that, the potential Ve continues to decrease even during period T5. Thus, during period T5, the sixth reference potential Vref6continues to be input into the inverting input of the second operational amplifier52a. Thus, during period T5, the nMOS42is controlled so that the potential Vf can be equal to the sixth reference potential Vref6. Thus, the gate current gradually decreases during period T5, and the gate current (i.e., the potential difference Vf−Ve) becomes generally zero at time t6when the potential Ve decreases to a potential equal to the sixth reference potential Vref6. After that, the second operational amplifier52amaintains a state where the potentials Ve and Vf are equal to the sixth reference potential Vref6. As a result, the IGBT12is turned off.

As described above, in this gate potential control circuit10d, the nMOS42is controlled so that the potential difference Vf−Ve between both ends of the second resistor44cannot fall below a predetermined potential Vref5(i.e., the absolute value of the potential difference Vf−Ve cannot exceed the absolute value of the predetermined potential Vref5) when the IGBT12is turned off. Thus, during periods T2to T4, the potential difference Vf−Ve (i.e., the gate current) is constant and the gradient at which the potentials Ve and Vf decrease is controlled to a gradient that is determined by the gate current. In other words, during periods T2and T4, the gradient at which the potentials Ve and Vf decrease is controlled to a generally constant gradient that is smaller than the gradient that is determined by the slew rate. Thus, with this gate potential control circuit10d, variation in switching speed is reduced. In addition, the potentials Vd, Ye and Vf can be accurately controlled by the first operational amplifier32aand the second amplifier52a.

The relationship between the constituent elements of the third and fourth embodiments and the constituent elements of the present invention is next described. The IGBT12of the third and fourth embodiments may be regarded as one example of the driving switching element of the present invention. The output terminal60aof the insulation power supply60of the third and fourth embodiments may be regarded as one example of the first gate potential supply part of the present invention. The first resistor24of the third and fourth embodiments may be regarded as one example of the first resistor of the present invention. The pMOS22of the third and fourth embodiments may be regarded as one example of the first switching element of the present invention. The first operational amplifier32aof the third and fourth embodiments may be regarded as one example of the first operational amplifier of the present invention. It should be noted that the lower one of the potential Ve+Vref3and the potential Vref4(i.e., a farther value from the output potential Vout that is output from the insulation power supply60) is input into the inverting input of the first operational amplifier32aof the third and fourth embodiments. The farther value may be regarded as a value having a larger deviation from the output potential Vout. The third reference potential Vref3of the third and fourth embodiments may be regarded as one example of the third reference potential of the present invention and also as one example of the seventh reference potential of the present invention. The fourth reference potential Vref4of the third and fourth embodiments may be regarded as one example of the fourth reference potential of the present invention and also as one example of the eighth reference potential of the present invention. The output terminal60bof the insulation power supply60of the fourth embodiment may be regarded as one example of the second gate potential supply part of the present invention. The nMOS42of the fourth embodiment may be regarded as one example of the second switching element of the present invention. The second resistor44of the fourth embodiment may be regarded as one example of the second resistor of the present invention. The second operational amplifier52aof the fourth embodiment may be regarded as one example of the second operational amplifier of the present invention. The fifth reference potential Vref5of the fourth embodiment may be regarded as one example of the fifth reference potential of the present invention and also as one example of the ninth reference potential of the present invention. The sixth reference potential Vref6of the fourth embodiment may be regarded as one example of the sixth reference potential of the present invention and also as one example of the tenth reference potential of the present invention. The constituent elements of the fourth embodiment and the constituent elements of the present invention can also be recognized as follows. The IGBT12of the fourth embodiment may be regarded as one example of the driving switching element of the present invention. The output terminal60bof the insulation power supply60of the fourth embodiment may be regarded as one example of the first gate potential supply part of the present invention. The second resistor44of the fourth embodiment may be regarded as one example of the first resistor of the present invention. The nMOS42of the fourth embodiment may be regarded as one example of the first switching element of the present invention. The second operational amplifier52aof the fourth embodiment may be regarded as one example of the first operational amplifier of the present invention. It should be noted that the higher one of the potential Ve+Vref5and the potential Vref6(i.e., the farther value from the output potential V-out that is output from the insulation power supply60) is input into the non-inverting input of the second operational amplifier52aof the fourth embodiment. As described above, the first gate potential supply part of the present invention may be a gate-on potential (for example, the output potential Vout from the insulation power supply60of the third and fourth embodiments) that is used to turn on a driving switching element (i.e., to increase the gate potential of the IGBT), or may be a gate-off potential (for example, the output potential V-out from the insulation power supply60of the fourth embodiment) that is used to turn off a driving switching element (i.e., to decrease the gate potential of the IGBT). In this case, the fifth reference potential Vref5of the fourth embodiment may be regarded as one example of the third reference potential of the present invention and also as one example of the seventh reference potential of the present invention. Also, in this case, the sixth reference potential Vref6of the fourth embodiment may be regarded as one example of the fourth reference potential of the present invention and also as one example of the eighth reference potential of the present invention.

It should be noted that the third resistors101and102or the third resistor103may be added to the circuits of the third and fourth embodiments as in the case of the circuits that are shown inFIGS. 6 and 7.

While the fact that various potentials are input into the operational amplifier(s) is described in the first to fourth embodiments, potentials obtained by further processing the above-mentioned various potentials may be input into the operational amplifier(s). For example, potentials obtained by multiplying the above-mentioned various potential by a constant may be input into the operational amplifier(s).

While specific examples of the present invention have been described in detail above, these examples are for illustrative purposes only and are not intended to limit the present invention. The present invention includes various variations and modifications of the specific examples that are shown above.