Method of forming semiconductor device

A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a strained silicon layer.

2. Description of the Prior Art

With the trend of miniaturization of semiconductor device dimensions, the scale of the gate, source and drain of a transistor has decreased in accordance with the decrease in critical dimension (CD). Due to the physical limitation of the materials used, the decrease in scale of the gate, source and drain results in the decrease of carriers which determine the magnitude of the current in the transistor element, and this can adversely affect the performance of the transistor. Accordingly, in order to boost up a metal-oxide-semiconductor (MOS) transistor, increasing carrier mobility is an important consideration in the field of current semiconductor technique.

In the conventional technologies, a strained semiconductor substrate is used to provide biaxial tensile stress for increasing carrier mobility. A silicon-germanium (SiGe) layer is formed on the silicon substrate, and a silicon layer is further formed on the SiGe layer to constitute the strained semiconductor substrate. The lattice constant of silicon (Si) is 5.431 angstroms (A), and the lattice constant of germanium (Ge) is 5.646 A. When the silicon layer is disposed on the SiGe layer, lateral stress is formed in the silicon layer due to the lattice constant difference, so this silicon layer can serve as a strained silicon layer. The strained silicon layer facilitates the formation of a gate dielectric layer of high quality, and provides stress to the channel region of a transistor for enhancing carrier mobility.

The excessive thermal budget from other semiconductor process such as a thermal oxidation process performed during the formation of shallow trench isolations (STI) or an annealing process may cause defects such as dislocations, and even worse, the loss of stress in the strained silicon layer. Consequently, how to prevent side effects induced by these other semiconductor process while maintaining the normal function of the strained silicon layer is an important issue in this field.

SUMMARY OF THE INVENTION

It is therefore one of the objectives of the present invention to provide a method of fabricating a semiconductor device that sustains the stress of the strained silicon layer and improves the reliability of the semiconductor device performance.

An exemplary embodiment of the present invention provides a method for forming a semiconductor device that includes the following steps. First, a semiconductor substrate including a first strained silicon layer is provided. Then, at least an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed.

The formed strained silicon layer is commonly influenced by subsequent semiconductor processes. The heat produced during the STI process is transferred to the neighboring semiconductor substrate and alters the lattice constant of the semiconductor substrate. Accordingly, the stress of the formed strained silicon layer is affected. The present invention utilizes the later formed second strained silicon layer to replace the originally formed first strained silicon layer for ensuring the predetermined stress of the strained silicon layer, and a lattice constant of the second strained silicon layer is preferably the same as a lattice constant of the first strained silicon layer.

DETAILED DESCRIPTION

To provide a better understanding of the present invention, preferred exemplary embodiments will be described in detail. The preferred exemplary embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

Please refer toFIG. 1throughFIG. 6, which illustrate a method for forming a semiconductor device having a strained silicon layer according to a preferred exemplary embodiment of the present invention. At first, a semiconductor substrate, at least an epitaxial layer and a strained silicon layer are provided. As shown inFIG. 1, a semiconductor substrate10may be a silicon substrate or a silicon on insulator (SOI) substrate, and the semiconductor substrate10includes a first epitaxial layer12, a second epitaxial layer14and a first strained silicon layer16. The first epitaxial layer12and the second epitaxial layer14are disposed between the semiconductor substrate10and the first strained silicon layer16, and the second epitaxial layer14is disposed on the first epitaxial layer12. The first epitaxial layer12and the second epitaxial layer14respectively include a silicon-germanium epitaxial layer, where a material of the silicon-germanium epitaxial layer may be denoted as (Si(1-y)Gey), but is not limited thereto. For decreasing the surface defects such as dislocation in the first strained silicon layer16due to the germanium penetration, in this exemplary embodiment, the first epitaxial layer12has a graded germanium concentration distribution. In other words, a mole fraction (y) of germanium in the first epitaxial layer12increases progressively from an interface11between the semiconductor substrate10and the first epitaxial layer12towards an interface13between the first epitaxial layer12and the second epitaxial layer14. Furthermore, a mole fraction (y) of germanium in the second epitaxial layer14is substantially fixed and equal to the mole fraction (y) of germanium at the interface13between the first epitaxial layer12and the second epitaxial layer14. In another aspect, a lattice constant of the first epitaxial layer12is varied and ranges between a lattice constant of the semiconductor substrate10such as a lattice constant of silicon and a lattice constant of the second epitaxial layer14. A molecule arrangement of a silicon layer refers to a molecule arrangement of the second epitaxial layer14underneath the silicon layer. As the lattice constant of the second epitaxial layer14such as the lattice constant of silicon-germanium epitaxy is substantially larger than the lattice constant of silicon, the silicon layer disposed on the second epitaxial layer14can obtain a lateral stress; accordingly, the silicon layer having biaxial tensile strain can serve as the first strained silicon layer16.

Subsequently, as shown inFIG. 2andFIG. 3, at least an insulating region is formed in the semiconductor substrate10, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer16, but smaller than a depth of the second epitaxial layer14. In this exemplary embodiment, the insulating region may be a shallow trench isolation22(STI) having a depth of around 3000 angstroms (A). The method of forming the STI22includes the following steps. A patterned mask17is formed on the semiconductor substrate10for defining the location of the STI22. The material of the patterned mask17includes silicon nitride or a combination of silicon oxide and silicon nitride. Then, an etching process is performed to form at least a trench (not shown) in the semiconductor substrate10. Furthermore, a thermal oxidation process is performed to form an oxide layer18covering a bottom and inner sides of the trench, and a dielectric layer20which may be made of oxide is formed for filling the trench and overlapping the semiconductor substrate10through a chemical vapor deposition (CVD) process including high density plasma density CVD (HDPCVD) process, sub atmosphere CVD (SACVD) process, or spin on dielectric (SOD) process. Moreover, a chemical mechanical polishing (CMP) process is performed for the planarization of the dielectric layer20and the top of the patterned mask17is exposed. Finally, the patterned mask17is removed, and the formation of STI22including the oxide layer18and the dielectric layer20is completed. Please note that the STI process is not limited to the illustrated process.

It should be noted that the heat produced during the STI process will be transferred to the neighboring first strained silicon layer16and thereby alter the lattice constant of the first strained silicon layer16. Accordingly, the stress in the first strained silicon layer16may be changed. In other words, after receiving the thermal budget from the thermal oxidation process or the HDPCVD process of the STI process, the stress in the first strained silicon layer16may be lost.

In order to ensure the completeness of the stress in the strained silicon layer, the present invention includes a step of removing the regions where stress is changed or eliminated due to heat. As shown inFIG. 4, the first strained silicon layer16and a portion of the second epitaxial layer14is removed to form an opening24. This could be achieved through an etching process including a dry etching process or a wet etching process. For protecting the corner of the insulating region such as the STI22, the wet etching process having high etching selectivity is preferably used, and the etchant could be selected as diluted ammonia (NH4OH) or tetramethyl ammonium hydroxide (TMAH) solution, but is not limited thereto. In this exemplary embodiment, the wet etching process with the TMAH solution as etchant is performed to remove the first strained silicon layer16followed by removing a portion of the second epitaxial layer14to form the opening24. A depth of the opening24is preferably larger than a depth of the later formed source/drain region (not shown), but smaller than a depth of the STI22. Accordingly, the left second epitaxial layer14can still surround the bottom of the STI22, and the complete stress of the channel region between the later formed source/drain region can be guaranteed without the adverse effect of junction leakage. It should be appreciated that a depth of the removed second epitaxial layer14is preferably smaller than one fifth of an original depth of the second epitaxial layer14, and the bottom of the STI22should not be exposed by the opening24, but the present invention is not limited thereto.

As shown inFIG. 5, a third epitaxial layer26is formed on the left second epitaxial layer14, and a second strained silicon layer28is formed on the third epitaxial layer26in order. The third epitaxial layer26may be a silicon-germanium epitaxial layer, and a material of silicon-germanium epitaxial layer can be denoted as (Si(1-y)Gey). This could be completed through a selective epitaxial growth (SEG) process. For example, silicon-containing gas and germanium-containing gas flow into the chamber and the third epitaxial layer26grows, the germanium-containing gas is turned off when the third epitaxial layer26reaches a predetermined height, and the second strained silicon layer28is then formed on the third epitaxial layer26. It is appreciated that, a mole fraction (y) of germanium in the third epitaxial layer26is substantially equal to the mole fraction (y) of germanium in the second epitaxial layer14as a fixed value, furthermore, the second epitaxial layer14and the third epitaxial layer26have the same silicon-germanium molecule arrangement. The silicon molecule arrangement of the second strained silicon layer28may refer to the silicon-germanium molecule arrangement of the third epitaxial layer26underneath the second strained silicon layer28. The molecule arrangement is in accordance with the lattice constant; accordingly, a lattice constant of the second strained silicon layer28is substantially the same as a lattice constant of the third epitaxial layer26underneath the second strained silicon layer28, and the lattice constant of the third epitaxial layer26is substantially the same as the lattice constant of the second epitaxial layer14underneath the third epitaxial layer26. Consequently, the newly formed second strained silicon layer28and the removed first strained silicon layer16can have the same lattice constant as that of the second epitaxial layer14; that is, the second strained silicon layer28is able to provide an identical stress as the first strained silicon layer16. Therefore, STI22and the second strained silicon layer28having the complete stress without any impact caused by the formation process of STI22are formed in the semiconductor substrate10herein.

After those processes which may adversely affect the quality of the originally formed strained silicon layer are performed, the present invention removes the originally formed strained silicon layer, and refills the newly formed strained silicon layer for ensuring the complete stress in the strained silicon layer. Additionally, the present invention may be combined with various semiconductor processes to form a MOS transistor. As shown inFIG. 6, at least an active region30is defined in the semiconductor substrate10, and the active region30is used to dispose at least a transistor having a specific conductive type. The insulating region such as STI22surrounds the active region30. At least a first well32having a first conductive type is formed in the active region30by performing a first ion implantation process with the dopants having the first conductive type, where the first conductive type may be n-type or p-type. Subsequently, at least a gate structure34is formed on the first well32, and the gate structure34includes a gate dielectric layer36, a gate conductive layer38, a cap layer37and a spacer39. The gate dielectric layer36could be a low-k (low dielectric constant) gate dielectric layer made of silicon oxide, nitridation silicon oxide or other low-k material, or a high-k gate dielectric layer. The material of the high-k gate dielectric layer may be hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or combination thereof. The gate dielectric layer36made of silicon oxide can be formed through a thermal oxidation process, chemical vapor deposition (CVD) process, or atomic layer deposition (ALD) process. Furthermore, the gate conductive layer38may be made of undoped polysilicon, polysilicon having N+ dopants, or a metal layer having the specific work function. By performing a second ion implantation process with the dopants having the second conductive type, at least a source/drain region40having a second conductive type is formed in the first well32at two sides of the gate structure34. The second conductive type may be p-type or n-type, and the first conductive type is different from the second conductive type.

It should be appreciated that a depth of the source/drain region40is substantially larger or equal to a depth of the second strained silicon layer28for ensuring the predetermined stress provided to the channel region. Consequently, a transistor having the second conductive type is formed in the semiconductor substrate of the first well32having the first conductive type. It is also feasible to combine the present invention with various metal gate processes such as the high-k last process integrated into the gate-last process. That is, after the formation of the gate structure34having channel region in the second strained silicon layer28, an opening is formed between the spacer39by removing the gate dielectric layer36, the gate conductive layer38and the cap layer37of the gate structure34, and a high-k gate dielectric layer and a corresponding metal gate conductive layer are further formed to fill the opening for forming a metal gate structure.

In conclusion, the formed strained silicon layer is commonly influenced by subsequent semiconductor processes; for example, the heat produced during the STI process is transferred to the neighboring semiconductor substrate and alters the lattice constant of the semiconductor substrate. Accordingly, the stress of the formed strained silicon layer is affected. For this reason, after the STI process, the present invention utilizes the later formed second strained silicon layer to replace the originally formed first strained silicon layer for ensuring the predetermined stress of the strained silicon layer, and a lattice constant of the second strained silicon layer is preferably the same as a lattice constant of the first strained silicon layer.