INFORMATION PROCESSING APPARATUS, COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM, AND METHOD OF PROCESSING INFORMATION

An information processing apparatus includes: a processor; a first memory that is volatile and is coupled to the processor; a block device that is coupled to the processor; and at least one second memory that is nonvolatile, is coupled to the processor and that is configured to function as the first memory and the block device, and the processor controls a write method of the at least one second memory that functions as the block device in accordance with a usage status of the first memory so as to switch the function as the block device to the function as the first memory in the at least one second memory.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2020-154674, filed on Sep. 15, 2020, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is related to a processor, an information processing apparatus, a computer-readable recording medium storing a program, and a method of processing a program and information.

BACKGROUND

As a main memory in a server, a persistent memory (PMEM) may be used. Since the PMEM is nonvolatile similarly to a solid-state drive (SSD) or a hard disk drive (HDD), the PMEM is also usable as a persistent storage.

Japanese Laid-open Patent Publication No. 2017-130194 is disclosed as related art.

SUMMARY

According to an aspect of the embodiments, an information processing apparatus includes: a processor; a first memory that is volatile and is coupled to the processor; a block device that is coupled to the processor; and at least one second memory that is nonvolatile, is coupled to the processor and that is configured to function as the first memory and the block device, and the processor controls a write method of the at least one second memory that functions as the block device in accordance with a usage status of the first memory so as to switch the function as the block device to the function as the first memory in the at least one second memory.

DESCRIPTION OF EMBODIMENTS

The PMEM may be used as the main memory or the persistent storage in accordance with a usage status of the system. For example, when the memory capacity is insufficient, the PMEM is used as the main memory. Thus, the memory capacity is increased. In contrast, when load of the SSD or the HDD is high, the PMEM is used as the persistent storage. Thus, the input/output (I/O) performance is improved.

However, delay may occur in a function switching process from the persistent storage to the main memory due to a write back process for the dirty data in the PMEM.

In one aspect, overhead in switching the function of the PMEM may be reduced.

Hereinafter, an embodiment will be described with reference to the drawings. It is noted that the following embodiment is merely exemplary and not intended to exclude various modification examples and technical applications which are not explicitly described in the embodiment. For example, the present embodiment may be implemented with various modifications without departing from the gist of the present embodiment. Each of the drawings is not intended to indicate that only the drawn elements are provided, and the embodiment may include other functions and so on.

Since the same reference signs indicate the same elements in the drawings, the description thereof will be omitted below.

[A-1] Configuration Example

FIG. 1is a block diagram schematically illustrating an example of a hardware configuration of an information processing apparatus1according to an example of the embodiment.

As illustrated inFIG. 1, the information processing apparatus1has a server function and includes a central processing unit (CPU)11, a memory unit12, a display control unit13, a storage device14, an input interface (I/F)15, an external recording medium processing unit16, a communication I/F17, and persistent memories (PMEMs)18.

The memory unit12is an example of a storage unit and includes, for example, a read-only memory (ROM), a random-access memory (RAM), and so on. Programs such as a Basic Input/Output System (BIOS) may be written in the ROM of the memory unit12. The software programs stored in the memory unit12may be appropriately loaded into and executed by the CPU11. The RAM of the memory unit12may be used as a memory for temporary recording or as a working memory.

The storage device14is a storage device with high IO performance. For example, dynamic random-access memory (DRAM), a solid-state drive (SSD), storage class memory (SCM), or a hard disk drive (HDD) may be used as the storage device14.

The input I/F15may be coupled to input devices such as a mouse151and a keyboard152and control the input devices such as the mouse151and the keyboard152. The mouse151and the keyboard152are examples of the input device. The operator performs various input operations by using these input devices.

The external recording medium processing unit16is configured so that a recording medium160is attachable thereto. The external recording medium processing unit16is configured to be able to read information recorded in the recording medium160in a state in which the recording medium160is attached thereto. In the present example, the recording medium160is portable. For example, the recording medium160is a flexible disk, an optical disc, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like.

The communication I/F17is an interface that enables communication with an external apparatus.

The PMEMs18are storage devices that are mountable in a dual inline memory module (DIMM) slots and that allow byte access thereto. The PMEMs18are nonvolatile storage devices in which data is not deleted when the power supply is shut down. The PMEMs18are able to function as a block device103(described later with reference toFIG. 2).

The CPU11is an example of a processor and is a processing device that performs various controls and operations. The CPU11executes an operating system (OS) and the programs loaded into the memory unit12to realize various functions.

The device that controls the operations of the entire information processing apparatus1is not limited to the CPU11and may be, for example, any one of a microprocessor unit (MPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), and a field-programmable gate array (FPGA). The device that controls the operations of the entire information processing apparatus1may be a combination of two or more types of the CPU, the MPU, the DSP, the ASIC, the PLD, and the FPGA.

FIG. 2is a block diagram illustrating a switching process of the PMEM illustrated inFIG. 1.

As illustrated inFIG. 2, non-uniform memory access (NUMA) memories101, PMEM devices102, and the block device103are defined in the information processing apparatus1.

The NUMA memories101are examples of a first memory. A plurality of DRAM DIMMs are coupled to the NUMA memories101. The NUMA memories101are recognized as a single memory by the OS. The PMEM devices102are examples of a second memory, and a plurality of the PMEM DIMMs are coupled to the PMEM devices102. One or more persistent storage devices are coupled to the block device103.

In an example illustrated inFIG. 2, as indicated by a reference numeral A1, an identifier (ID) #0 of the PMEM devices102functions as a PMEM storage in the block device103. As indicated by a reference numeral A2, in the block device103, the PMEMs18functioning as PMEM storages exchange data with the SSD or the HDD corresponding to the storage device14illustrated inFIG. 1.

As indicated by a reference numeral A3, the IDs #1 to #3 of the PMEM devices102function as PMEM memories in the NUMA memories101. As indicated by a reference numeral A4, in the NUMA memories101, the PMEMs18functioning as the PMEM memories exchange data with the DRAM corresponding to the memory unit12illustrated inFIG. 1.

In an example of the embodiment, as indicated by the reference numerals A1and A3, the function of each of the PMEMs18is dynamically switched to a memory or a storage in accordance with the usage status of the system.

When the PMEMs18are used as the PMEM memories, data management is performed by a NUMA management function included in the OS. When DRAM capacity is insufficient, memory is secured from the PMEM memories. Data migration is performed between the DRAM and the PMEM memories.

When the PMEMs18are used as the PMEM storages, the PMEMs18function as a persistent cache of the SSD or the HDD.

Use of the PMEMs18as the PMEM memories may be given priority over the use of the PMEMs18as the PMEM storages. When memory capacity is likely to become insufficient, the function of the PMEM storages is switchable to that of the PMEM memories even during the use of the PMEM storages. In contrast, the PMEM memories in use are not switchable to the PMEM storages.

The reason why the use of the PMEMs18as the PMEM memories is given priority over the use as the PMEM storages as described above is that an application is significantly influenced when the memory capacity is insufficient. For example, when a swap area is usable, the performance of the application is significantly degraded by a swap process. In contrast, when the swap area is unusable, execution of the application is interrupted. When the PMEM storages are not usable, the performance of the application is only slightly degraded.

In the case where the memory capacity is likely to become insufficient, when the function of the PMEMs18is switched from the PMEM storages to the PMEM memories, dirty data in the PMEM storages used as the persistent cache is written back to the SSD or the HDD. Accordingly, when the amount of dirty data is large, it takes a long time to execute a write back process, and the switching process is not necessarily completed before timing at which the memory capacity actually becomes insufficient.

Thus, according to the example of the embodiment, a time interval of the write back process of the PMEM storages is set to be small so as to reduce the amount of dirty data in the PMEM storages.

The CPU11controls a write method of the PMEM devices102functioning as the block device103in accordance with a usage status of the NUMA memories101. The CPU11switches the function as the block device103in the PMEM devices102to the function as the NUMA memories101.

The CPU11may control the write method when there is a NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than a first threshold. The control of the write method may be performed by reducing the time interval of the write back process to the block device103in a PMEM device102the usage rate of which is the lowest among the PMEM devices102functioning as the block device103.

When there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than the first threshold, the CPU11may perform a deallocation process of the PMEM device102. The deallocation process may be performed by, in the PMEM device102which functions as the block device103and the usage rate of which is 0 within a predetermined period of time, writing back the data to the block device103and deallocating the function as the block device103.

When there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than a second threshold that is higher than the first threshold and there is no PMEM device102in an unallocated state, the CPU11may perform the switching process of the PMEM devices102. The switching process may be performed by switching the function as the block device103to the function as the NUMA memory101in the PMEM devices102having undergone the control of the write method.

[A-2] Operation Example

A function switching process of the PMEM according to the example of the embodiment will be described in accordance with a flowchart (steps S1to S5) illustrated inFIG. 3.

Processing is started when the system is started up, and a NUMA memory allocation (NMA) of the NUMA memories101and a block device utilization (BDU) of the block device103are obtained as the usage status of the system (step S1). The NMA may be referred to as a NUMA memory allocation rate and is a value obtained by dividing the allocated capacity of each of memories functioning as the NUMA memories101by the total capacity of the NUMA memories101. The BDU may be referred to as a block device usage rate and is a value indicating a ratio of a period of usage time per unit period of time of each of the storages that functions as the block device103.

The write back interval control of the PMEM storages is performed (step S2). The details of the process in step S2will be described later with reference toFIG. 4.

The deallocation process of the PMEM devices102is performed (step S3). The details of the process in step S3will be described later with reference toFIG. 5.

An allocation process of the PMEM devices102is performed (step S4). The details of the process in step S4will be described later with reference toFIG. 6.

After waiting for a certain period of time (step S5), the processing returns to step S1.

Next, the details of the write back interval control process of the PMEM storages illustrated inFIG. 3will be described in accordance with a flowchart (steps S21to S24) illustrated inFIG. 4.

It is determined whether the NMA of all the memories included in the NUMA memories101is greater than NMA_low_thr (step S21). NMA_low_thr is an example of the first threshold and is a threshold of the NMA for determining that the memory capacity is likely to become insufficient.

When the NMA of at least a subset of the memories included in the NUMA memories101is smaller than or equal to NMA_low_thr (see the NO route in step S21), the time interval of the write back process of all the PMEM storages is set to wb_long_delay (step S22). The write back interval control process of the PMEM storages ends.

In contrast, when the NMA of all the memories included in the NUMA memories101is greater than NMA_low_thr (see the YES route in step S21), the PMEM storage the BDU of which is the lowest is selected (step S23).

The time interval of the write back process of the selected PMEM storage is set to wb_short_delay (step S24). The write back interval control process of the PMEM storage ends. The time interval wb_short_delay of the write back process is smaller than wb_long_delay.

Next, the details of the deallocation process of the PMEM devices102illustrated inFIG. 3will be described in accordance with a flowchart (steps S31to S37) illustrated inFIG. 5.

It is determined whether there is a PMEM memory the NMA of which is 0 and the NMA of all the memories included in the other NUMA memories101is smaller than NMA_low_thr (step931).

When there is no PMEM memory the NMA of which is 0 or the NMA of all the memories included in the other NUMA memories101is greater than or equal to NMA_low_thr (see the NO route in step S31), it is determined whether there is the PMEM storage the BDU of which is 0 within a predetermined period of time (step S32).

When there is no PMEM storage the BDU of which is 0 (see the NO route in step S32), the deallocation process of the PMEM devices102ends.

When, in step931, there is the PMEM memory the NMA of which is 0 and the NMA of all the memories included in the other NUMA memories101is smaller than NMA_low_thr (see the YES route in step S31), the PMEM memory the NMA of which is 0 is deallocated (step S33).

The deallocated PMEM device102is added to an unallocated list (step934), and the processing proceeds to step932. The unallocated list stores the IDs of the PMEM devices102in an unallocated state. In the example illustrated inFIG. 1, in the PMEM devices102, the PMEMs18[#4, #5] allocated to neither the NUMA memories101nor the block device103are stored.

In step S32, when there is the PMEM storage the BDU of which is 0 (see the YES route in step S32), dirty data is written back from the PMEM storage to the SSD or the HDD (step S35).

The PMEM storage is deallocated (step S36).

The deallocated PMEM device102is added to the unallocated list (step S37). The deallocation process of the PMEM device102ends.

Next, the details of the allocation process of the PMEM devices102illustrated inFIG. 3will be described in accordance with a flowchart (steps S41to S51) illustrated inFIG. 6.

It is determined whether the NMA of all the NUMA memories101is greater than NMA_high_thr (step S41). NMA_high_thr is an example of the second threshold, a threshold of the NMA for determining that the memory capacity is likely to become insufficient, and greater than NMA_low_thr.

When the NMA18of at least a subset of the NUMA memories101is smaller than or equal to NMA_high_thr (see the NO route in step S41), it is determined whether there is a storage of the block device103the BDU of which is greater than the threshold (step S42).

When there is no storage of the block device103the BDU of which is greater than the threshold (see the NO route in step S42), the allocation process of the PMEM devices102ends.

In step S41, when the NMA of all the NUMA memories101is greater than NMA_high_thr (see the YES route in step S41), it is determined whether the unallocated list is empty (step S43).

When the unallocated list is not empty (see the NO route in step S43), the PMEM devices102are allocated as the PMEM memories (step S44).

The allocated PMEM devices102are deleted from the unallocated list (step S45). The processing proceeds to step S42.

In step S43, when the unallocated list is empty (see the YES route in step S43), it is determined whether there is the PMEM storage the time interval of the write back process for which is wb_short_delay (step S46).

When there is no PMEM storage the time interval of the write back process for which is wb_short_delay (see the NO route in step S46), the processing proceeds to step S42.

In contrast, when there is the PMEM storage the time interval of the write back process for which is wb_short_delay (see the YES route in step S46), dirty data is written back from the PMEM storage to the SSD or the HDD (step S47).

The PMEM storage is switched to the PMEM memory (step S48). The processing proceeds to step S42.

In step S42, when there is the storage of the block device103the BDU of which is greater than the threshold (see the YES route in step S42), it is determined whether the unallocated list is empty (step S49).

When the unallocated list is empty (see the YES route in step S49), the allocation process of the PMEM devices102ends.

In contrast, when the unallocated list is not empty (see the NO route in step S49), the PMEM devices102are allocated as the PMEM storages (step S50).

The allocated PMEM devices102are deleted from the unallocated list (step S51). The allocation process of the PMEM devices102ends.

[B] Modification Example

Although the time interval of the write back process of the PMEM storages is set to be small so as to reduce the amount of dirty data in the PMEM storage according to the above-described example of the embodiment, this in not limiting.

The updated data may be simultaneously written to the PMEM storages and the SSD or the HDD by switching the write method of the PMEM storages to write through. This sets all the data in the PMEM storages in an updated state (for example, a clean state). Accordingly, the dirty data in the PMEM storages may be reduced.

For example, the CPU11may control the write method when there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than the first threshold. The control of the write method may be performed by writing through to the block device103the data for the PMEM device102the usage rate of which is the lowest among the PMEM devices102functioning as the block device103.

The function switching process of the PMEM according to the modification example will be described in accordance with a flowchart (steps S6to S10) illustrated inFIG. 7.

Processing is started when the system is started up, and the NMA of the NUMA memories101and the BDU of the block device103are obtained as the usage status of the system (step S6).

The write method control of the PMEM storages is performed (step S7). The details of the process in step S7will be described later with reference toFIG. 8.

The deallocation process of the PMEM devices102is performed (step S8). The details of a process in step S8are similar to the process in the example of the embodiment having been described with reference toFIG. 5.

The allocation process of the PMEM devices102is performed (step S9). The details of the process in step S4will be described later with reference toFIG. 9.

After waiting for a certain period of time (step S10), the processing returns to step S6.

Next, the details of the write method control process of the PMEM storages illustrated InFIG. 7will be described in accordance with a flowchart (steps S71to S74) illustrated inFIG. 8.

It is determined whether the NMA of all the memories included in the NUMA memories101is greater than NMA_low_thr (step S71).

When the NMA of at least a subset of the memories included in the NUMA memories101is smaller than or equal to NMA_low_thr (see the NO route in step S71), the write method of all the PMEM storages is set to the write back (step S72). The write method control process of the PMEM storages ends.

In contrast, when the NMA of all the memories included in the NUMA memories101is greater than NMA_low_thr (see the YES route in step S71), the PMEM storage the BDU of which is the lowest is selected (step S73).

The write method for the selected PMEM storage is set to the write through (step S74). The write method control process of the PMEM storages ends.

Next, the details of the allocation process of the PMEM devices102illustrated inFIG. 7will be described in accordance with a flowchart (steps S91to S100) illustrated inFIG. 9.

It is determined whether the NMA of all the NUMA memories101is greater than NMA_high_thr (step S91).

When the NMA18of at least a subset of the NUMA memories101is smaller than or equal to NMA_high_thr (see the NO route in step S91), it is determined whether there is a storage of the block device103the BDU of which is greater than the threshold (step S92).

When there is no storage of the block device103the BDU of which is greater than the threshold (see the NO route in step S92), the allocation process of the PMEM devices102ends.

In step S91, when the NMA of all the NUMA memories101is greater than NMA_high_thr (see the YES route in step S91), it is determined whether the unallocated list is empty (step S93).

When the unallocated list is not empty (see the NO route in step S93), the PMEM devices102are allocated as the PMEM memories (step S94).

The allocated PMEM devices102are deleted from the unallocated list (step S95). The processing proceeds to step S92.

In step S93, when the unallocated list is empty (see the YES route in step S93), it is determined whether there is the PMEM storage the write method for which is the write through (step S96).

When there is no PMEM storage the write method for which is the write through (see the NO route in step S96), the processing proceeds to step S92.

In contrast, when there is the PMEM storage the write method for which is the write through (see the YES route in step S96), the PMEM storage is switched to the PMEM memory (step S97). The processing proceeds to step S92.

In step S92, when there is the storage of the block device103the BDU of which is greater than the threshold (see the YES route in step S92), it is determined whether the unallocated list is empty (step S98).

When the unallocated list is empty (see the YES route in step S98), the allocation process of the PMEM devices102ends.

In contrast, when the unallocated list is not empty (see the NO route in step S98), the PMEM devices102are allocated as the PMEM storages (step S99).

The allocated PMEM devices102are deleted from the unallocated list (step S100). The allocation process of the PMEM devices102ends.

With the example of the embodiment and the modification example, for example, the following effects may be obtained.

The CPU11controls the write method of the PMEM devices102functioning as the block device103in accordance with the usage status of the NUMA memories101. The CPU11switches the function as the block device103to the function as the NUMA memories101in the PMEM devices102.

This may reduce overhead in switching of the function of the PMEM. Flexible use of the PMEM devices102may be realized by increasing the memory capacity when the memory capacity is likely to become insufficient and improving the I/O performance when load of the SSD or the HDD is high.

The CPU11controls the write method when there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than the first threshold. The control of the write method is performed by reducing the time interval of the write back process to the block device103in the PMEM device102the usage rate of which is the lowest among the PMEM devices102functioning as the block device103. Accordingly, the amount of dirty data to be written back in switching the PMEM devices102may be reduced, and the delay time in the switching process may be reduced.

The CPU11controls the write method when there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than the first threshold. The control of the write method is performed by writing through to the block device103the data for the PMEM device102the usage rate of which is the lowest among the PMEM devices102functioning as the block device103. Accordingly, the amount of dirty data to be written back in switching the PMEM devices102may be further reduced, and the delay time in the switching process may be reduced.

When there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than the first threshold, the CPU11performs the deallocation process of the PMEM devices102. The deallocation process is performed by, in the PMEM device102which functions as the block device103and the usage rate of which is 0 within a predetermined period of time, writing back the data to the block device103and deallocating the function as the block device103. Accordingly, the PMEM devices102in the unallocated state may be secured before the memory capacity actually becomes insufficient.

When there is the NUMA memory101in which, as the usage status, the possibility that the memory capacity becomes insufficient is greater than the second threshold that is higher than the first threshold and there is no PMEM device102in the unallocated state, the CPU11performs the switching process of the PMEM devices102. The switching process is performed by switching the function as the block device103to the function as the NUMA memory101in the PMEM devices102having undergone the control of the write method. Accordingly, the PMEM devices102may be allocated as the NUMA memories101before the memory capacity actually becomes insufficient.

The disclosed technique is not limited to the above-described embodiment. The disclosed technique may be carried out with various modifications without departing from the gist of the present embodiment. The configurations and the processes of the present embodiment may be selected as desired or may be combined as appropriate.