Output buffer circuit

An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

TECHNICAL FIELD

The present invention relates generally to output buffers and more particularly to single ended output buffers.

BACKGROUND OF THE INVENTION

In an integrated circuit, output buffers are often used at output pins to transfer signals to the signal lines. The transmission of information across the signal lines can be subject to various problems such as impedance mismatch, signal reflection, or irregular output waveform. Typically, output buffers must meet specifications dictated by application, such as maintaining a smooth and robust output waveform.

FIG. 5shows a block diagram of a conventional output buffer500that can drive an output506between a high (e.g., VDD) and low (e.g., VSS) level in response to an input signal IN. The conventional output buffer500can include control logic503, a first driver512, a second driver514, a p-channel output transistor515and an n-channel output driver transistor517. In response to a logic output signal502from control logic503, first driver512can drive a gate of p-channel output transistor515between a high power supply level (e.g., VDD) to turn the transistor off, and a low power supply level (e.g., VSS) to turn the transistor on. In an opposite fashion, in response to a logic output signal504from control logic503, second driver514can drive a gate of n-channel output transistor515between a low power supply level (e.g., VSS) to turn the transistor off, and a high power supply level (e.g., VDD) to turn the transistor on. P-channel output transistor515and n-channel output transistor517can be large output driving devices and thus include relatively large gates that can present a significant capacitance to their respective drivers (512and514).

Control logic503can output signals to control the operation of the output buffer. For example, an output506can be driven high by turning on p-channel output transistor515and turning off n-channel output transistor517, or can be driven low by turning off p-channel output transistor515and turning on n-channel output transistor517. An output506could also be placed in a high impedance state (i.e., tristate) by turning off both output transistors (515and517).

A disadvantage of conventional output buffer500can be the limited flexibility in meeting variations arising from different applications. While a drive strength of a conventional output buffer500can be increased by adding additional driver devices in parallel, doing so may only just meet a minimum output impedance necessary to reduce signal reflections on a transmission line driven by the buffer.

Another disadvantage of conventional output buffer500can be sensitivity to operating conditions. While an output buffer500can be tuned to meet worst case load conditions, if an actual output transmission line is less than such worst case, it can be difficult to meet driving requirements, such as rise time and fall time, particularly across uncontrollable variations in manufacturing process, differing operating voltages, and/or temperatures.

DETAILED DESCRIPTION

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show output driver circuits that can vary drive strength according to supply voltage conditions and/or provide programmable drive strength. As a result, an output buffer can meet performance requirements over a range of operating voltages. Further, programmability of drive strength can enable the output buffer to be configured to provide a desired signal profile despite variations in transmission line load.

Referring now toFIG. 1, an output driver is shown in a block schematic diagram and designated by the general reference character100. An output buffer100can include control logic102, pull-up predriver circuit104, pull-down predriver circuit106, driver section108, and current control section110. Control logic102can receive an input signal IN, and in response, generate control output signals for controlling predriver circuits (106and104). In the particular example ofFIG. 1, such control output signals include a pull-up disable signal (PU_DIS), pull-up enable signal (PREPU), pull-down disable signal (PD_DIS), pull-down enable signal (PREPD).

A pull-up predriver circuit104can include a first switch element112-0, a second switch element112-1, and a first variable current source114-0. A first switch element112-0can provide a low or high impedance path between a high power supply node VDD and a first driver control node116-0in response to signal PU_DIS. A second switch element114-0can provide a high or low impedance path between first driver control node116-0and first variable current source114-0in response to signal PREPU. First variable current source114-0can provide a current that is controllable according to current control section110. More particularly, in response to a current control section110, a variable current source114-0can source a current from first control node116-0(provided switch element112-1is in a low impedance state) that can vary inversely with respect to a power supply voltage and/or can be programmable.

A pull-down predriver circuit106can include a third switch element112-2, a fourth switch element112-3, and a second variable current source114-1. A third switch element112-2can provide a low or high impedance path between a low power supply node VSS and a second driver control node116-1in response to signal PD_DIS. A fourth switch element112-3can provide a high or low impedance path between second driver control node116-1and second variable current source114-0in response to signal PREPD. Like first variable current source114-0, second variable current source114-1can provide a current controlled by current control section110that preferably varies inversely with respect to a power supply voltage and/or can be programmable.

A driver section108can include a p-channel insulated gate field effect transistor (hereinafter PFET) P10and an n-channel FET (NFET) N10. PFET P10can have a source-drain path connected between a high power supply node VDD and an output node118. A gate of PFET P10can be connected to first driver control node116-0. In such an arrangement, a rising edge of an output signal can be generated at output node118by disabling first switch element112-0and enabling second switch element112-1. This can cause a potential at the gate of PFET P10to fall according to the current drawn by first variable current source114-0. This is in contrast to conventional arrangements that can drive a gate of an output PFET P10by switching it to a low power supply VSS. PFET P10can be disabled by disabling second switch element112-1and enabling first switch element112-0, thereby connecting its gate to a high power supply node VDD. By providing a strong second switch element112-1, large crowbar currents through output driver can be reduced or avoided as output PFET P10can be turned off quickly.

NFET N10can have a source-drain path connected between a low power supply node VSS and an output node118. A gate of NFET N10can be connected to second driver control node116-1. In such an arrangement, a falling edge of an output signal can be generated at output node118by disabling third switch element112-2and enabling fourth switch element112-3. This can cause a potential at the gate of NFET N10to rise according to the current supplied by second variable current source114-1. This is in contrast to conventional arrangements that can drive a gate of an output NFET by switching its gate to a high power supply VDD. NFET P10can be disabled by disabling fourth switch element112-3and enabling third switch element112-2, thereby connecting its gate to a low power supply node VSS. As the case of PFET P10, providing a strong fourth switch element112-3can reduce or eliminate large crowbar currents through driver section108.

In this way, an output buffer can include output driver transistors that are enabled in response to current sources sinking or sourcing a current that can vary according to supply voltage and/or are programmable. Thus, drive strength of such devices can be varied without increasing or decreasing the number of driver devices, as is done in some conventional approaches.

Referring now toFIGS. 2A and 2Bportions of an output buffer circuit according to other embodiments are shown in block schematic diagrams.FIG. 2Ashows one way of conceptualizing a pull-up path of an output driver.FIG. 2Bshows one way of conceptualizing a pull-down path of an output driver.

Referring now toFIG. 2A, a pull-up path is shown in a block schematic diagram and designated by the general reference character200. A pull-up path200can include sections shown inFIG. 1, thus like sections are referred to by the same reference character but with the first digit being a “2” instead of “1”. A pull-up path200can include current control section210, switch element212-1, variable current source214-0, and output driver PFET P20. A current control section210can provide a current I_IN that varies in response to a power supply voltage. In the particular example shown, a current control section210can include a voltage compensation circuit220, a base current source222, and current mirror source224. A voltage compensation circuit220can provide a current IOUT that varies inversely with power supply voltage. That is, as a power supply voltage increases (e.g., VDD−VSS), current IOUT decreases. Conversely, as power supply decreases, current IOUT can increase. A current IOUT can be added with a constant current IBASE provided by base current source222, to create a current I_IN for current mirror source224.

A variable current source214-0can include a static section226and a programmable section228. A static section226can include a current source that mirrors the current passing through current mirror source224and draws current from a current control node230. Thus, a current drawn by static section226can also vary inversely with a power supply voltage. In a similar fashion, a programmable section228can include one or more current sources that mirror the current passing through current mirror source224. Such current sources can be arranged in parallel with one another with respect to current control node230. However, unlike static section226, current sources within programmable section228can be switched into current control node228to vary that amount of current drawn at current control node230. In the particular example shown, signals DRV0and DRV1can control the current sources of programmable section228.

A switch element212-1can selectively connect a driver control node216-0to variable current source214-0, to thereby drive a gate of PFET P20low, to pull output node218toward VDD.

In this way, a pull-up device in an output driver can be controlled by a variable current source sinking a current with a magnitude that is both programmable and inversely related to a power supply level.

Referring now toFIG. 2B, a pull-down path is shown in a block schematic diagram and designated by the general reference character250. A pull-down path250can include sections shown inFIG. 1, thus like sections are referred to by the same reference character but with the first digit being a “2” instead of “1”. A pull-down path250can include current control section210, switch element212-3, variable current source214-1, and output driver NFET N20.

A current control section210can provide a current I_IN in the same fashion as described with reference toFIG. 2A.

A variable current source214-1can have the same general configuration as variable current source214-0, except that current is sourced to a common current control node230′.

A switch element212-3can selectively connect a driver control node216-1to variable current source214-1, to thereby enable NFET N20, and drive output node218toward VSS.

In this way, a pull-down device in an output driver can be controlled by a variable current source sourcing a current with a magnitude that is both programmable and inversely related to a power supply level.

FIGS. 2A and 2Bthus show how can an output driver to be tuned for a given output transmission line by altering a current drive amount, and not the number of active drivers. Further, such a driving current can be inversely proportional to a power supply voltage and thus be capable of operating over a wide range of power supply levels.

Referring now toFIG. 3, a voltage compensation circuit is shown in a block schematic diagram and designated by the general reference character300. A voltage compensation circuit300can correspond to that shown as220inFIGS. 2A and 2B. A voltage compensation circuit300can include a current mirror formed by NFETs N30and N31, a reference load R30, and a current source302. NFET N31can have a source connected to a low power supply node VSS, a gate connected to its drain, and a drain connected to reference load R30. NFET N30can have a source connected to a low power supply node VSS, a gate connected to the gate of N31, and a drain connected to a current out node304.

As shown inFIG. 3, NFET N31can draw a current Iref. This current can be mirrored by NFET N30to draw a current Imirror. That is, if NFETs N30and N31are matched in size, such currents can be the same, and if NFETs N30and N31are scaled with respect to one another, such currents can vary according to their scaling factor. A current ISOURCE provided by current source302can be a constant current.

In the arrangement ofFIG. 3, as a power supply voltage increases, current Iref (and hence current Imirror) can increase. This can shunt current away from current out node304, reducing the magnitude of output current IOUT. On the other hand, as a power supply voltage decreases, current Iref (and hence current (mirror) can decrease. This can shunt less current away from current out node304, thus output current IOUT can increase in magnitude.

In this way a current can be provided that can be inversely proportional to a power supply voltage.

While the embodiments ofFIGS. 2A and 2Bshow one way of conceptualizing the current drivers, in a preferred embodiment a common voltage compensated current can be utilized to generate a drive current for both pull-up and pull-down devices by a series of current mirrors. An example of such an arrangement is shown inFIG. 4.

Referring toFIG. 4, an output driver tuning circuit is shown in a schematic diagram and designated by the general reference character400. A tuning circuit400can include an input current circuit402, a programmable switching section404, a current driver section406, a drive strength modulator408, pull-down current source410, pull-up current source412, pull-up switch element414-0, pull-down switch element414-1, output driver section416.

An input current section402can include a current mirror formed by NFETs N41and N42and load PFET P41. NFET N41can have a drain that receives a voltage compensated input current I_IN. In one particular arrangement, a current I_IN can be generated by circuits like those shown as210inFIGS. 2A and 2Band/or300inFIG. 3. That is, current I_IN can be inversely proportional to a supply voltage. Current I_IN can be mirrored by NFET N42and thus draw current at node418. Load PFET P41can be connected to node418in a “diode” configuration (its drain and gate connected to the node, its source connected to a high power supply node VDD).

Programmable switching section404can include one or more selectable legs to vary the amount of current drawn at node418. In the particular example ofFIG. 4, programmable switching section404includes two legs, one formed by series connected NFETs N43/N44, the other leg formed by series connected NFETs N45/N46. NFETs N44and N45within each leg can have gates connected to the gate of current mirror N41/N42, and thus can draw a current that mirrors input current I_IN (i.e., these currents are also supply voltage compensated). Each leg of programmable switching section404can be enabled by a corresponding drive select signal DRIVE0or DRIVE1. In such an arrangement, a current I1drawn at node418can include that drawn by NFET N42, and any additional current draw switched in by switching section404. Any of NFETs N42, N44and N46can be scaled with respect to NFET N41to provide a desired programmability range.

A current driver section406can include mirror PFET P42, a drive current mirror N47/N48, and a drive PFET P43. PFET P42can be connected in a current mirror fashion to load PFET P41, and thus can provide a current I2to node420that mirrors I1. Drive current mirror N47/N48can receive a current Id from node420, and mirror such current to generate a current Idrive that flows from PFET P43to NFET N48. A drive strength modulator408can include NFETs N49and N50arranged in series with one another between node420and a low power supply node408. In such an arrangement, when drive strength modulator is disabled (NFET N49off), current Idrive can essentially mirror current I2. In contrast, when drive strength modulator is enabled (NFET N49on), the scaling factor between the different legs of current driver section406can be changed, as NFET N50is added in parallel with NFET N47. As a result current Idrive can be reduced.

Pull-down current source410can include a PFET P44having a gate connected in a current mirror fashion to that of PFET43. Thus, PFET P44can source a current that mirrors current Idrive. Similarly, pull-up current source412can include an NFET N51having a gate connected in a current mirror fashion to a gate of NFET N47, and thus sink a current that mirrors current Id (and hence Idrive).

An output driver section416can have the same structure as that shown as108inFIG. 1, and include driver PFET P40and driver NFET N40.

Pull-up switch element414-0can be connected between a gate of driver PFET P40and pull-up current source412. Thus, when pull-up switch element414-0is enabled in response to signal PU, driver PFET P40can drive output node422high based on a current Id. In a similar fashion, pull-down switch element414-1can be connected between a gate of driver NFET N40and pull-down current source410. Thus, when pull-down switch element414-1is enabled in response to signal PD, driver NFET N40can drive output node422low based on current Idrive.

Again, due to the current mirroring of tuning circuit400currents Id/Idrive are inversely proportional to a power supply voltage.

Output driver circuits according to the embodiments can provide for rise and fall times that can meet a same specification under varying voltage supply conditions, as a drive strength is determined by sinking or sourcing a current that varies with power supply voltage levels.

In addition or alternatively, output driver circuits according to the embodiments can provide for a selectable rise and fall time, by enabling any of multiple current sources to increase and/or decrease a current that controls the drive strength of the output buffer. As but one example, for a worst case load condition, a first number of current sources can be enabled to provide a relatively fast switching speed. For load conditions less than a worst case, fewer current sources can be enabled, thus slowing down the rise/fall times appropriately. Such load-drive matching can reduce electromagnetic interference (EMI) in systems that drive signals between various locations.

Embodiments of the present invention can be employed as output drivers for various integrated circuits. As but one particular example, such an output driver may be particularly suitable for driving an output clock signal that can control the timing of other circuits in a larger system.

Embodiments of the present invention are well suited to performing various other steps or variations of the steps recited herein, and in a sequence other than that depicted and/or described herein. In one embodiment, such a process is carried out by processors and other electrical and electronic components, e.g., executing computer readable and computer executable instructions comprising code contained in a computer usable medium.

For purposes of clarity, many of the details of the improved solution and the methods of designing and manufacturing the same that are widely known and are not relevant to the present invention have been omitted from the following description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects.