Shallow trench isolation structure with converted liner layer

A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

BACKGROUND OF THE INVENTION

This application claims priority to Korean Patent Application No. 2004-006980, filed on Feb. 3, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates generally to IC (integrated circuit) fabrication, and more particularly, to a shallow trench isolation (STI) structure with a liner layer that is converted from an initial material to a subsequent material for preserving the integrity of IC structures associated with the STI structure.

2. Description of the Related Art

Isolation technology is important for electrically isolating adjacent IC (integrated circuit) devices fabricated in a semiconductor substrate, especially with demand for higher integration and capacity of IC devices. Shallow trench isolation (STI) is particularly suited for the fabrication of highly integrated IC devices.

For STI, a STI trench is formed to surround an active region of a semiconductor substrate, and the STI trench is filled with insulating material. Further for such STI, an oxide layer is formed on the walls of the STI trench formed in a silicon substrate. In addition, a liner layer typically comprised of thin silicon nitride is also formed at the walls of the STI trench. After formation of such layers at the walls of the STI trench, the STI trench is filled with oxide such as an HDP (high density plasma) oxide.

With such STI, 4-giga-bit NAND flash memory devices have been developed with an active region pitch that is less than 150 nm. In such a NAND flash memory device, the width of the STI trench is a few tens of nanometers (such as 76 nm for example). Since the active region pitch is less than 150 nm, the STI trench is not filled in a single fill step. Rather, a multi-step process is employed to fill such a narrow width STI trench in the flash memory device as well as in DRAM or SRAM memory devices with small critical dimensions.

In the multi-step process for filling the STI trench, a mask layer pattern is formed through masking layers typically comprised of a silicon nitride layer and an oxide layer formed on a semiconductor substrate. The mask layer pattern is used as an etch mask as the STI trench is etched through the semiconductor substrate by anisotropic dry etching.

Thereafter, a first oxide layer is formed on the walls of the STI trench by thermal oxidation. In addition, a liner layer comprised of silicon nitride is then deposited on any exposed surfaces. Thereafter, a medium temperature oxide (MTO) deposition is performed to deposit a second oxide layer on any exposed surfaces.

After deposition of such layers, the STI trench is filled with a first dielectric fill material comprised of HDP (high density plasma) oxide or undoped silicate glass (USG). Thereafter, a wet etch-back process is performed such that the first dielectric fill material partially fills the STI trench. Subsequently, a third oxide layer from medium temperature oxide (MTO) deposition is deposited. Thereafter, the STI trench is completely filled with a second dielectric fill material also comprised of HDP oxide or USG.

In summary, the STI structure is formed by the multi-step process for filling the STI trench as follows: (1) STI trench formation→(2) first oxide layer by thermal oxidation of STI trench sidewall→(3) liner layer of silicon nitride→(4) second oxide layer by MTO deposition→(5) first dielectric fill material of HDP oxide or USG→(6) wet etch-back of first dielectric fill material→(7) third oxide layer by MTO deposition (may be omitted)→(8) second dielectric fill material of HDP oxide layer or USG.

Unfortunately, with the STI liner of silicon nitride, a dent is formed in the STI structure of the prior art from wet etching of the nitride layer forming the mask layer pattern.FIG. 1Ashows an STI structure20of the prior art comprised of a dielectric fill material22within a STI trench24. The dielectric fill material22is typically comprised of multiple fill materials formed in separate deposition steps in the multi-step process for filling the STI trench24.

The STI trench24is patterned by etching through the semiconductor substrate28according to the opening in the mask layer pattern formed with an oxide layer30and a nitride layer32. For simplicity inFIG. 1A, assume that a first oxide layer34and a liner layer36of silicon nitride are formed at the walls of the STI trench24. Such layers34and36are formed at the walls of the STI trench24before the dielectric fill material22is deposited into the STI trench24.

Referring toFIG. 1B, as the nitride layer32of the mask layer pattern is etched away in a wet-etch process, the top portion of the liner layer36also comprised of nitride is etched away. Thus, during any subsequent etch process for etching oxide, the exposed sidewall of the dielectric fill material22is etched away to form dents38.

Such dents38cause deleterious effects and even failure in an adjacent transistor. Relative to DRAM or SRAM memory devices, a flash memory device is especially vulnerable to degradation of production yield from formation of such dents38.

More specifically, for the transistor formed adjacent to any of such dents38, the transistor exhibits a hump phenomenon whereby the transistor undesirably turns on, or whereby the threshold voltage of the transistor is decreased. In addition, bridging may occur in adjacent gate electrodes of transistors from residues of polysilicon comprising the gate electrodes of such transistors within the dents38. In any case, the dents38deteriorate the electrical characteristics of the integrated circuit.

Therefore, especially for flash memory devices, the STI structure is desired to be formed with the liner layer36not being comprised of silicon nitride. An example process for forming such a STI structure includes the following steps: (1) STI trench formation→(2) forming a first oxide layer from thermal oxidation at walls of the STI trench→(3) forming a second oxide layer from MTO deposition→(4) filling the STI trench with a first dielectric fill material of HDP oxide or USG→(5) wet etch-back such that the first dielectric fill material partially fills the ST trench→(6) forming a third oxide layer from MTO deposition (may be omitted)→(7) filling the STI trench with a second dielectric fill material of HDP oxide or USG.

Unfortunately, a disadvantage of using just the oxide layers at the walls of the STI trench is that during the wet-etch process of step (5) above, a high-voltage (HV) oxide layer is damaged by the wet etch as illustrated inFIGS. 2A and 2B. Elements having the same reference number inFIGS. 1A and 2Arefer to elements having similar structure and/or function.FIG. 2Ashows a STI structure40formed with an oxide layer42formed at walls of the STI trench24. The oxide layer42may be formed from multiple deposition processes with multiple oxide layers. A first dielectric fill material44is deposited to fill the STI trench24as in step (4) above.

Referring toFIGS. 2A and 2B, a wet etch-back is performed such that the first dielectric fill material44partially fills the STI trench24, as in step (5) above. Typically, the first dielectric fill material44is comprised of an oxide. Thus, during the wet etch-back for etching the first dielectric fill material44, the upper portion of the oxide layer42is also etched away. In addition, side portions46of the oxide layer30forming the mask layer pattern are also etched away from being exposed inFIG. 2B. The oxide layer30of the mask layer pattern may also form the HV (high voltage) gate dielectric for transistors in a peripheral circuit region of a memory device. In that case, such etching of the side portions46of the HV oxide layer30results in operational degradation of such transistors.

Thus, a mechanism for forming an STI structure is desired with preservation of the integrity of the IC structures22ofFIGS. 1B and 30ofFIG. 2B.

SUMMARY OF THE INVENTION

Accordingly, a STI structure is formed with a liner layer that is converted from an initial material to a subsequent material for preserving the integrity of IC structures associated with the STI structure.

In a general aspect of the present invention, for forming a STI (shallow trench isolation) structure, a STI opening is formed within a semiconductor substrate. In addition, a liner layer comprised of an initial material is formed at walls of the STI opening. The STI opening is then filled with a first dielectric fill material. An etch-back of the first dielectric fill material is performed to expose an upper portion of the liner layer and such that the first dielectric fill material partially fills the STI opening. The exposed upper portion of the liner layer is then converted to be comprised of a subsequent material different from the initial material.

In another embodiment of the present invention, the STI opening is filled with a second dielectric fill material such that the first and second dielectric fill materials completely fill the STI opening.

In a further embodiment of the present invention, a thermal oxidation process is performed to form a first oxide layer at the walls of the STI opening when the semiconductor substrate is comprised of silicon, before the step of forming the liner layer.

In one embodiment of the present invention, a second oxide layer is also formed on the first oxide layer in a medium temperature oxide (MTO) deposition process, before the step of forming the liner layer. In that case, the liner layer is deposited on the second oxide layer.

In another embodiment of the present invention, the second oxide layer is formed on the liner layer in a medium temperature oxide (MTO) deposition process, after the step of forming the liner layer.

In a further embodiment of the present invention, the STI opening is etched through masking layers comprised of a layer of nitride and a layer of oxide deposited on the semiconductor substrate.

In one example embodiment of the present invention, the initial material of the liner layer is nitride, and the subsequent material of the upper portion of the liner layer is oxide. In that case, the liner layer comprised of the initial material has a thickness in a range of from about 10 Å (angstroms) to about 100 Å (angstroms), and the upper portion of the liner layer comprised of the subsequent material has a thickness in a range of from about 50 Å (angstroms) to about 500 Å (angstroms).

Further in that case, the exposed upper portion of the liner layer is oxidized with a radical to convert the exposed upper portion of the liner layer into oxide from nitride. A source gas for the oxidizing radical includes one of a mixture of hydrogen and oxygen or a mixture of hydrogen, oxygen, and hydrogen chloride. In addition, the step of oxidizing the exposed upper portion of the liner layer with a radical is performed with a pressure in a range of from about 1 milli-Torr to about 50 Torr and at a temperature in a range of from about 600° Celsius to about 1100° Celsius.

In yet another embodiment of the present invention, each of the first and second dielectric fill materials is comprised of one of HDP (high density plasma) oxide or USG (undoped silicate glass). In that case, the etch-back of the first dielectric fill material is performed in a wet etch-back process using an etching solution comprised of LAL (low ammoniumfluoride liquid), SC-1 solution, or an HF solution.

In this manner, the liner layer is comprised of the initial material of nitride during the wet etch-back of the first dielectric fill material comprised of oxide. Such a liner layer of nitride protects any oxide layer comprising the masking layers on the semiconductor substrate during the wet etch-back of the first dielectric fill material. Thereafter, the exposed upper portion of the liner layer is converted into the subsequent material of oxide. Such a converted upper portion of the liner layer protects the sidewalls of the dielectric fill material within the STI opening during etching away of any nitride layer comprising the masking layers on the semiconductor substrate to prevent formation of dents for the STI structure.

The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number inFIGS. 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18, and19refer to elements having similar structure and/or function.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 3, an oxide (SiO2for example) layer105and a nitride (SiN for example) layer110form masking layers sequentially formed on a semiconductor substrate100. The oxide layer105and the nitride layer110are patterned by a photo etch process to form an opening102through such layers110and105. The layers110and105with the opening102form a mask layer pattern112for defining an active region on the semiconductor substrate100.

FIG. 3illustrates for example a cell region of a flash memory device or a peripheral circuit region of the flash memory device having the oxide layer105as a HV gate oxide layer on the semiconductor substrate100. Using the mask layer pattern112as an etch mask, the semiconductor substrate100is anisotropically dry-etched to form a STI opening102through the semiconductor substrate100. The STI opening102is formed as a STI trench in one embodiment of the present invention. However, the present invention may be practiced when the STI opening102is any other type of opening formed through the semiconductor substrate100.

In one embodiment of the present invention, the sidewalls of the STI trench102may have a positive slope depending on the etch characteristics. With such sloping of the sidewalls of the STI trench102, the upper width of the STI trench102is greater than the lower width of the STI trench102.

Referring toFIG. 4, a first oxide layer120is formed on the walls of the STI trench102. The first oxide layer120is formed by thermal oxidation at the walls of the STI trench102when the semiconductor substrate100is comprised of silicon, in one embodiment of the present invention. Such thermal oxidation may be by dry oxidation using O2, or by wet oxidation using H2O.

The first oxide layer120facilitates subsequent formation of another oxide layer or a nitride layer. In addition, the first oxide layer120repairs defects or damage on the silicon walls of the STI trench102resulting from a dry etching process for forming the STI trench102. As will be further described, if an oxide layer from MTO (medium temperature oxide) deposition is formed, the process of forming the first oxide layer120may be omitted.

Thereafter, referring toFIG. 5, a second oxide layer125is formed by MTO (medium temperature oxide) deposition in one embodiment of the present invention. The second oxide layer125is conformally deposited on exposed surfaces including on the first oxide layer120. Subsequently inFIG. 5, a liner layer130is deposited on the second oxide layer125. The liner layer130is comprised of silicon nitride having a thickness in a range of from about 10 Å (angstroms) to about 100 Å (angstroms), in one embodiment of the present invention.

Such a liner layer130prevents the silicon at the walls of the STI trench102from being further oxidized during subsequent processes. In addition, the liner layer130protects the oxide layer105which may be a HV gate oxide layer in the peripheral circuit region of a memory device. More specifically, during wet etch-back in the subsequent multi-step STI trench filling process, the liner layer130prevents etching of the HV gate oxide layer as will be illustrated and described later herein.

Referring toFIG. 6, a first dielectric fill material135is deposited on the liner layer130to fill the STI trench102. The first dielectric fill material135is comprised of an insulating material suitable for filling the STI trench102, which typically has a relatively narrow width and a high aspect ratio. Because of higher difficulty in filling the STI trench102with lower width and higher aspect ratio, the gap fill of the STI trench102is performed in a plurality of steps for the STI trench102that is relatively narrow. The first dielectric fill material135is comprised of USG (undoped silicate glass) or HDP (high density plasma) oxide, in one embodiment of the present invention.

Thereafter, referring toFIG. 7, a wet etch-back process is performed to etch away a top portion of the first dielectric fill material135. As a result, the first dielectric fill material135partially fills a bottom portion of the STI trench102, and a top portion of the liner layer130becomes exposed as illustrated inFIG. 7.

The etching solution used for the wet etch-back process inFIG. 7is comprised of SC-1 (standard cleaning-1) solution including H2O2, NH4OH and H2O, in one embodiment of the present invention. Alternatively, the etching solution used for the wet etch-back process inFIG. 7is comprised of a LAL (low ammoniumfluoride liquid) or a HF (hydrogen fluoride) solution.

Referring toFIG. 8, according to a general aspect of the present invention, an oxidation process using a radical is performed on the exposed upper portion131of the liner layer. As a result, initially inFIG. 7, the exposed upper portion of the liner layer130is comprised of the initial material of nitride (SiN for example). After the oxidation process using a radical inFIG. 8, the exposed upper portion131of the liner layer is converted to be comprised of a subsequent material of an oxide (SiO2for example).

The source gas for forming such a radical in the oxidation process for converting the exposed upper portion131includes a mixture of H2and O2, in one embodiment of the present invention. Alternatively, such a source gas includes a mixture of H2, Cl2, and O2. The oxidation process for converting the exposed upper portion131of the liner layer is performed under a pressure in a range of from about 1 milli-Torr to about 50 Torr and at a temperature in a range of from about 600° Celsius to about 110° Celsius, in one embodiment of the present invention.

A thickness of the converted exposed upper portion131of the liner layer is increased from before the oxidation process. For example, the liner layer130comprised of the initial material of nitride inFIG. 7has a thickness in a range of from about 10 Å to about 100 Å before the oxidation process using a radical. Thereafter, the converted upper portion131of the liner layer comprised of the subsequent material of oxide inFIG. 8has a thickness in a range of from about 50 Å to about 500 Å after the oxidation process using a radical.

The oxidation process using a radical is performed in a single type or a batch type process. In the single type process, one semiconductor substrate100is placed within a reaction chamber for the oxidation process using a radical. In the batch type process, a batch of multiple semiconductor substrates is placed within the reaction chamber for the oxidation process using a radical.

As will be described later herein, the oxidation of the exposed upper portion131of the liner layer inFIG. 8prevents generation of dents in the dielectric fill material within the STI trench102during a subsequent process of removing the mask layer pattern112. On the other hand, when the whole liner layer130is comprised of silicon nitride during the wet etch-back process inFIG. 7, the oxide layer105at the sidewalls of the STI trench102is protected by the liner layer130from the etch solution for etching oxide. Thus, the structural integrity of the oxide layer105which may be a HV gate oxide for a peripheral circuit in a memory device is preserved inFIG. 7.

Referring toFIG. 9, a second dielectric fill material140is conformally deposited to completely fill the STI trench102. In an alternative embodiment of the invention, a layer of oxide from MTO (medium temperature oxide) deposition may be formed before the second dielectric fill material140is deposited. Because the first dielectric fill material135partially fills the bottom portion of STI trench102, the aspect ratio of the STI trench102is lower such that the second dielectric fill material140more easily completely fills the STI trench102without generation of defects such as voids or the like.

The second dielectric fill material140is comprised of USG (undoped silicate glass) or HDP (high density plasma) oxide, in one embodiment of the present invention. Thereafter referring toFIG. 10, a planarization process such as a CMP (chemical mechanical polishing) process is performed. The nitride layer110of the mask layer pattern112acts as a polish stop in the CMP process.

Referring toFIG. 11, using etching solutions such as a phosphoric acid solution and a HF solution, the nitride layer110is etched away. InFIG. 11, the oxide layer105of the mask layer pattern112is etched away in the case the trench102surrounds core cells of a flash memory device. Note that during such etching, top portions of the dielectric fill material140, the second oxide layer125, and the converted upper portion of the liner layer131are also etched away. On the other hand, if the STI trench102surrounds a peripheral circuit region of the flash memory device with the oxide layer105forming a HV gate oxide layer, the oxide layer105would not be etched away.

Referring toFIG. 19, the phosphoric acid solution in such etching removes just the layer of nitride110of the mask layer pattern112. During such etching, because the upper portion131of the liner layer has been oxidized to be comprised of the subsequent material of oxide, the phosphoric acid solution does not etch such an oxidized upper portion131of the liner layer. Thus, the upper portion131of the liner layer remains to protect the side surfaces of the dielectric fill material140to prevent the generation of dents in the dielectric fill material140.

In this manner, since the liner layer130is comprised of the initial material of silicon nitride, the HV oxide layer (which may be formed as the oxide layer105) of a peripheral circuit of a memory device is protected from the wet etch-back ofFIG. 7. On the other hand, since the upper portion131of the liner layer is oxidized to the subsequent material of oxide, the generation of dents in the STI structure during the etching of the mask pattern layers112is prevented. Furthermore, using the first and second dielectric fill materials135and140in multiple fill steps, the STI trench102having narrow width and high aspect ratio is more easily filled without defects.

FIGS. 12 to 18show cross-sectional views for forming an STI structure according to another embodiment of the present invention. This alternative embodiment is different from the embodiment ofFIGS. 3-11in that the liner layer130of nitride is formed before the second oxide layer125is formed. The formation of first and second oxide layers120and125and liner layer130of nitride and the thicknesses thereof and the etching solution used for wet etch or wet etch-back processes are similar as those in the previous embodiment. Furthermore, the oxidation process using a radical for converting the upper portion131of the liner layer is similar as in the previous embodiment.

Referring toFIG. 12for this alternative embodiment, the mask layer pattern112including the oxide layer105and the nitride layer110is formed on the semiconductor substrate100. Then, an anisotropic dry etch process is performed using the mask pattern layer as an etch mask to form the STI trench102. Subsequently, the walls of the STI trench102comprised of silicon are thermally oxidized to form a first oxide layer120. Thereafter, the liner layer130comprised of silicon nitride is conformally deposited. Subsequently, the second oxide layer125is deposited on the liner layer130.

Referring toFIG. 13, the first dielectric fill material135is conformally deposited to fill the STI trench102. Then, as shown inFIG. 14, a wet etch-back process is performed using a LAL, SC-1 or HF solution as an etchant, thereby removing a top portion of the first dielectric fill material135comprised of USG (undoped silicate glass) or HDP oxide. Additionally during such an etch-back process, the upper portion of the second oxide layer125that was disposed under the removed portion of the first dielectric fill material135is also etched away. As a result, an upper portion of the liner layer130is exposed as illustrated inFIG. 14with the first dielectric fill material135partially filling the STI trench102.

Referring toFIG. 15, using a radical from a source gas consisting of a mixture of H2and O2or a mixture of H2, HCl and O2, the exposed upper portion131of the liner layer is oxidized to the subsequent material of oxide. Then, referring toFIG. 16, a second dielectric fill material140is conformally deposited to completely fill the STI trench102. Thereafter, referring toFIG. 17, a planarization process such as a CMP process is performed. Additionally referring toFIG. 18, a wet etch process is performed using a phosphoric acid solution and a HF solution to remove the mask layer pattern112and top portions of the dielectric fill material140, the second oxide layer125, and the converted upper portion of the liner layer131.

Similar to the previous embodiment ofFIGS. 3–11, in the alternative embodiment ofFIGS. 12–18, since the liner layer130is comprised of the initial material of silicon nitride, the HV oxide layer (which may be formed as the oxide layer105) of a peripheral circuit of a memory device is protected from the wet etch-back ofFIG. 14. On the other hand, since the upper portion131of the liner layer is oxidized to the subsequent material of oxide, the generation of dents in the STI structure during the etching of the mask pattern layers112inFIG. 18is prevented. Furthermore, using the first and second dielectric fill materials135and140in multiple fill steps, the STI trench102having narrow width and high aspect ratio is more easily filled without defects.