Program time adjustment as function of program voltage for improved programming speed in memory system

In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to U.S. patent application Ser. No. 11/392,265, entitled, “Program Time Adjustment as Function of Program Voltage for Improved Programming Speed in Programming Method”, filed on the same day as the present application; which application is incorporated in its entirety by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

This invention relates in general to non-volatile memory systems and, in particular, to a non-volatile memory system with programming time control.

The memory cells or charge storage elements (the two terms used herein interchangeably) of a non-volatile memory are typically programmed one partial or complete row of cells in parallel at a time. Programming voltage pulses are applied to the selected row of memory cells until the threshold voltage of each of the selected cells in the row has been programmed to a value within a predetermined voltage range (which may or may not be the final desired state of the cell) in a programming cycle. During each programming cycle, a time sequence of programming voltage pulses of voltage level or amplitude Vpgm are applied at predetermined time intervals, such as periodic time intervals, where the amplitude of each programming pulse has been incremented by a fixed voltage step ΔVpgm (e.g. 0.2 V) compared to the amplitude of the immediately preceding programming pulse in the sequence. An example of an array of memory cells or charge storage elements that are programmed in the above manner is a NAND cell array.

In time periods between the programming voltage pulses, program-verify operations are carried out. That is, the programmed level of each charge storage element (e.g. charge storage transistor) being programmed in parallel is read after each programming pulse to determine whether it is not less than the verify voltage level to which it is being programmed. If it is determined that the threshold voltage of a given charge storage element has exceeded the verify voltage level, programming of such charge storage element is stopped by raising the voltage of the bit line to which the particular charge storage element is connected to from a low voltage (typically 0 volts) to a high or inhibit level (typically Vdd). Programming of other charge storage elements being programmed in parallel continues until they in turn reach their verify voltage levels. After each program verify operation, if there still is one or more charge storage elements being programmed in parallel whose threshold voltage still has not reached the verify voltage level, the amplitude of the programming pulse is increased by the predetermined step size and applied again to the charge storage elements being programmed in parallel, which is followed again by a program-verify operation. If after the next programming operation the increased programming pulse still has not caused the threshold voltage of all of the charge storage elements being programmed in parallel to reach the verify voltage level, the amplitude of the programming pulse is increased yet again by the same predetermined step size during the next time interval and this process is repeated until threshold voltages of all of the charge storage elements being programmed in parallel have reached the verify voltage level. This marks the end of a particular programming cycle.

As will be evident from the above description, the above programming process requires repetitively programming the cells with a programming pulse followed by a program-verify operation. This process, therefore, can be time consuming. It is, therefore, desirable for the program time for the application of each programming pulse to have a short duration so that the memory cells or charge storage elements can be programmed to the desired threshold voltages in as short a time as possible.

The time sequence of programming pulses that are used to program charge storage elements is illustrated inFIG. 2A, where 13 such consecutive pulses are shown, although it is possible to employ a larger or fewer number of pulses for programming the elements to any particular threshold voltage. The voltage pulses may start at an initial program pulse level such as 15 volts and increase by a predetermined step size such as 0.2 volts for every pulse.

InFIG. 2A, the programming pulses in the sequence used to program charge storage elements are illustrated to have substantially vertical leading and trailing edges. In practice, the pulse shape of the programming pulses is different from those shown, because a charge pump typically requires a charge-up time to increase the voltage output from a reference voltage level to the required Vpgm level, and the pulse requires a time period to decrease back to the reference level at the trailing edge of the pulse. This is illustrated inFIGS. 1 and 2B.

As shown inFIG. 1, at time t0, the charge pump starts increasing the voltage output from a starting reference level such as the ground level, and applies the output to the selected control gate line or word line. However, it is not until the time t1that the output of the charge pump reaches the required voltage level Vpgm that is effective for altering transistor threshold voltage as shown inFIG. 1. After the output of the charge pump reaches the required voltage level at time t1, this voltage level is maintained until a time t2which marks the end of the time period in which the output of the charge pump is maintained at the required program voltage level Vpgm. Thereafter, the charge pump output declines back to the reference level by time t3. Thus the total program time allocated for programming the control gate line or word line is the sum of two of the three time periods: t0-t1(or T) and t1-t2, and the memory proceeds to the next program pulse or program verify after t3. The time period t0-t1or T is the charge-up time required for the charge pump in order to deliver the required program voltage level Vpgm. The time period t1-t2is the pulse width, which is the effective program time during which the voltage of the selected control gate line or word line is ramped up to the desired Vpgm level effective for altering the threshold voltage of charge storage elements.

Thus in reference toFIG. 2A, each of the 13 pulses labeled1through13actually has a shape similar to that shown inFIG. 1. As illustrated inFIG. 2A, the Vpgm level that is required to be delivered by the charge pump increases by ΔVpgm every time a new charge pump pulse is generated, so that the required program voltage or Vpgm level trends higher from pulse1to pulse13as shown inFIG. 2A. A higher Vpgm level requires a longer charge-up time compared to a lower Vpgm as illustrated inFIG. 2B.

In conventional designs for charge pump control, the total program time allocated for programming the selected control gate line or word line is fixed and does not change with the increasing program voltage level Vpgm required. This situation is illustrated inFIG. 2B. Thus in reference toFIGS. 2A and 2B, for pulse1inFIG. 2A, the voltage level required to be delivered by the charge pump at Vpgm1is still relatively low so that charge-up time T1is relatively short, leaving most of the fixed program time available in conventional schemes for the charge pump to ramp up the control gate line or word line to the required voltage level Vpgm1. For the pulse5, however, the Vpgm5level that needs to be delivered by the charge pump is higher than that for pulse1so that a longer charge-up time T5is required, leaving a shorter time available for applying the ramped up voltage at Vpgm5level to the selected control gate line or word line effective for altering the threshold voltage of the charge storage elements controlled by such line. For pulse10, the required voltage pump pulse level Vpgm10is even higher so that an even longer charge-up time T10is required leaving an even smaller portion of the fixed program time available for the charge pump output at Vpgm10for altering the threshold voltage of the charge storage elements. This means that as the required programming voltage of the charge pump pulse is increased, the effective program time or pulse width is becoming shorter and shorter and therefore less and less effective in programming the charge storage elements to reach the verify voltage level. The net result is that a larger number of programming pulses must be applied to program all the cells that are programmed in parallel. This is undesirable since it reduces performance of the memory system.

The above programming operation applies both to multi-level charge storage elements as well as binary-level charge storage elements or memory cells. An illustration of the above programming and program-verify operations to multi-level charge storage elements is described in U.S. Pat. No. 6,522,580, which is incorporated herein by reference in its entirety.

One solution to the above problem is to increase the fixed time allocated for the programming, so that even at high programming voltages, the increased program time allocated allows the charge pump output at the required high Vpgm level to stay at such level for an adequate time for altering charge storage element threshold voltages even after an increased charge-up time. As noted above, for increased performance it will be desirable to minimize the programming time of each programming cycle in which the programming pulses are applied. Since allocating a longer programming time is needed only at high programming voltages (i.e. at high Vpgm levels) but not at low programming voltages, increasing the fixed program time for the generation and application of all of the charge pump pulses during the programming cycle would also be undesirable since it also increases the total programming time. It is therefore desirable to provide a non-volatile memory system, where the above-described difficulties are alleviated.

SUMMARY OF THE INVENTION

Ideally, it is desirable for the program time period allocated to be as short as possible during the beginning portion of the program cycle when the charge pump is called upon to supply low to moderate voltage outputs for the program pulses. As the programming cycle progresses, when higher amplitude programming voltages are called for, it is desirable for longer program time periods to be used instead of the shorter time period used initially.

This invention is based on the recognition that the program time period allocated for the voltage pump pulses can be increased when the charge pump is called upon to supply high voltage output for the program pulses. In one embodiment, the program time allocated for application of the voltage pump pulses is adjusted a plurality of times to values that reduce the number of pulses for programming the charge storage elements to a predetermined state (i.e. a state where the elements are within a predetermined range of threshold voltages). In one implementation of this embodiment, the program time allocated is controlled as a function of the number of program pulses that have been generated by the charge pump during a particular programming cycle. In another implementation of this embodiment, the program time allocated is controlled as a function of the amplitude or amplitudes of pulses provided by the charge pump without using any output of the charge pump.

In a different embodiment, at least one program time allocated for application of the voltage pump pulses is generated in response to at least one indicator signal indicative of the amplitude or amplitudes of pulses provided by the charge pump. In this embodiment, the indicator signal or signals are being generated without using amplitude of any output of the charge pump. In one implementation of such embodiment, the indicator signal or signals are provided by a program voltage control logic which also controls the voltage level of the pump pulses provided by the charge pump, and which controls the program time allocated. In another implementation of this embodiment, the indicator signal or signals are indicative of the number of program pulses that have been generated by the charge pump during a particular programming cycle.

For simplicity in description, identical components are labeled by the same numerals in this application.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 3is a block diagram of a flash memory system20(which can be in the form of a plug-in card or module) in communication with a host device10(e.g. computer, camera, cellular phone, personal digital assistant, game controllers, and media players such as MP3 players) through system bus15. The flash memory system20includes a flash EEPROM module30and a controller40, which includes, in turn, memory41and a processor43. Controller40interprets the commands received from the host computer10and translates them into corresponding read, write and other operations for the flash EEPROM module30, in a manner transparent to the host computer10.

FIG. 4illustrates, as an example, a simplified block diagram of portions of the flash EEPROM system20related to the generation of the charge pump voltage pulses. In this application, the terms “voltage pump pulses”, “pump pulses”, “charge pump voltage pulses”, “programming pulses” and “program pulses” are used interchangeably. As shown inFIG. 4, the supply voltage Vsys is applied by the host10to controller40and through an optional voltage regulator45; a possibly different voltage level, Vdd, is applied to module30. Processor43applies commands and data to module30and the charge pump32generates the programming pulses from the voltage Vdd in response to the control signals from control logic58. In practice there is usually sufficient logic in the control logic58in the non-volatile memory30to control the detailed operation of the memory, relieving Processor43from this responsibility. Typically Decode Module56consists of sufficient logic to interpret commands from Processor43using a pre-defined protocol, and Control Logic58consists of a dedicated sequencer, a pulse counter a Vpgm control logic, possibly with some parameters stored in a separate ROM (not shown) within Array54and read out upon startup. The pulse counter in Control Logic58is reset to 0 at the beginning of each programming cycle and counts starting from 0 the number of program pulses launched by the sequencer. Using the pulse count output of the pulse counter, the Sequencer decides from which loop it starts program verifies and/or at which loop it terminates the program loop with a program fail status. The Vpgm control logic in Control Logic58calculates Vpgm level of each program pulse. However, the present invention does not depend on the physical location of the above circuit blocks or how they are connected and other arrangements may be used. The programming pulses are applied to a memory cell array54. Array54comprises rows and columns of memory cells. For simplicity in description, the various control circuits for row and column control, as well as other controls, for the memory array have been omitted fromFIG. 4.

Circuit52controls the programming time of the pulses generated by the charge pump32as a function of an indicator signal from control logic58indicating the amplitude of the pulses. The program time control circuit52generates program time control signals66or74and supplies such signals to Control Logic58to cause the program times allocated for application of the voltage pump pulses from the charge pump32to the charge storage elements in array54to be adjusted to reduce the number of pulses required for programming the charge storage elements to a predetermined charge state, such as to program charge storage transistors to threshold voltages within a certain predetermined range. These program time control signals are supplied to Control Logic58for controlling the length of program time allocated for application of the voltage pump pulses to array54.

FIG. 5is a schematic circuit diagram of one embodiment of the program time control scheme ofFIG. 4. Circuit52′ is one implementation of circuit52ofFIG. 4. Pulse counter64and sequencer68are parts of the control logic58ofFIG. 4. As explained above, the pulse counter64in logic58resets to 0 at the beginning of each programming cycle and counts starting from 0 the number of program pulses launched by the sequencer. The pulse counter64outputs a pulse count signal64aindicating the program pulse count from the beginning of such programming cycle. This pulse count signal is supplied to the program time control logic circuit52′ which may comprise logic circuits that implement a lookup table. This lookup table provides a value of program time corresponding to the pulse count number from counter64.

As illustrated inFIG. 2A, the charge pump increases the voltage level of the programming pulse by a voltage increment ΔVpgm above the voltage level of the immediately preceding programming pulse, so that if the total number of programming pulses that have been provided during a particular programming cycle is known, the desired Vpgm level can be calculated from such number. FromFIG. 1and the discussion in reference thereto above, it is clear that for any given programming voltage level Vpgm desired, there is a corresponding value for the sum of charge-up time (t0-t1) plus the desired effective program time or pulse width (t1-t2), and that the higher the desired Vpgm value, the larger will be the charge-up time (t0-t1). In order to compensate for the increase in the value of the charge-up time (t0-t1) as Vpgm is increased, the corresponding program time is increased by corresponding amounts, which can be obtained by means of calculation or calibration. By so adjusting the program time corresponding to any value of Vpgm, it is then possible to arrive at a set of program times corresponding to a set of Vpgm values, and therefore also a set of corresponding pulse count values, so as to maintain a substantially constant effective program time (or pulse width) during which the program voltage is maintained at the desired Vpgm for different Vpgm and pulse count values.

By the above described process, for every pulse count, there will be a unique corresponding program time that takes into account the charge-up time required for any particular programming pulse with a particular Vpgm value corresponding to such pulse count. This program time value is then provided in a program time control signal output66to sequencer68which in turn supplies such program time control signal to the charge pump32on line53. Charge pump32then provides the next pump pulse for a programming time period that corresponds to the signal53. This process is then repeated for generating one or more program time control signals for controlling the program times of one or more pump pulses from pump32. The effect of such pump pulse program time control is illustrated inFIGS. 7 and 8.

FIG. 7is a graphical plot of the threshold voltage (on the vertical axis) of the charge storage elements that is achieved by the application of a corresponding number (on the horizontal axis) of voltage pump pulses in the sequence of pulse programming pulses such as those illustrated inFIG. 2A. The target threshold voltage Vt for a particular charge state to be achieved is shown as a horizontal dotted line82. The dotted slanted line84illustrates the threshold voltage of the charge storage elements that can be achieved where the pulse width or effective program time (during which the pulse voltage is maintained at the desired program voltage) is maintained at a constant value as the program voltage Vpgm is increased so as to achieve an optimum programming speed. However, if the same amount of time is allocated for the programming pulses irrespective of the desired voltage level Vpgm, as performed in conventional programming control, the threshold voltage of the charge storage elements that can be achieved corresponding to the number of pulses is shown as the solid line curve86. As is illustrated inFIG. 7, line82intersects curve86at a point to the right of its intersection with line84, indicating that the programming speed achieved with a constant program time allocation requires the application of many more programming pulses and is thus slower compared to one where the effective program time or pulse width is maintained constant.

FIG. 8is a graphical plot of three different programming pulses at three different values of Vpgm. By means of embodiments such as those shown inFIGS. 5 and 6, it is possible to control the program time of the three pulses so that they have effectively the same pulse width as illustrated inFIG. 8. As shown graphically inFIG. 8, as the required program voltage level Vpgm is increased, the amount of program time allocated is also increased correspondingly, so that the effective program time or pulse width remains substantially constant. This allows the optimum programming speed to be achieved, using the fewest number of programming pulses to cause charge storage elements to reach the target threshold voltage Vt, along the dotted line84inFIG. 7.

Thus, when the program voltage Vpgm is increased from one programming pulse to the next, the optimum programming speed is achieved when the program time allocated for application of the voltage pump pulse is increased every time the amplitude of the pulse is increased as illustrated by line84inFIGS. 7 and 9, and labeled option1inFIG. 9. In this manner, the effective pulse width of the programming pulses can be maintained substantially constant to achieve the optimum programming speed.

However, having to adjust the program time allocated each time the programming voltage increases requires frequent program time adjustment. For some applications, it may not be necessary to increase the program time allocated by the application of the pump pulse each time the programming voltage is increased (such as after the application of every pulse). For example, instead of increasing the program time allocated for application of the voltage pump pulse after the application of every pulse, this can be done after every X number of pulses, where X is an integer equal to or greater than 2. InFIG. 9, this is illustrated by dotted line92and labeled option2inFIG. 9. In option2, the program time allocated for application of the voltage pump pulse is increased after the application of every X pulses.

As yet another option, labeled option3inFIG. 9, the program time allocated for the application of the voltage pump pulses is maintained at a constant value until Y number of pump pulses have been applied in the programming cycle. Thus as shown inFIG. 9, before Y number of pulses are applied, the threshold voltage that can be achieved is the same in option3and in curve86obtained in conventional methods ofFIG. 7. However, after the program time allocated for the application of pump pulses is increased once after Y number of pulses, the curve94of option3diverges from curve86so that the total number of pulses required to achieve the target threshold Vt is reduced as compared to conventional methods as illustrated inFIG. 9. As shown inFIG. 9, curve94intersects the horizontal line82at a point closer to the vertical axis compared to where curve86intersects line82.

As yet another possible option different from those above, program time allocated may be increased each time the programming voltage is increased (such as after the application of every pulse) only after Y number of pulses have been applied, but not before this happens. This option is therefore a combination of prior options1and3. The threshold voltage versus number of pulses plot for such combination will be along curve86of the conventional methods up to the point until Y number of pulses have been applied to the charge storage transistors, but along a line (not shown) that has substantially the same slope as line84inFIG. 9after such point. Since the charge-up time may not be significant when the Vpgm level is relatively low, the effect of increasing the program time for such Vpgm levels after every program pulse is not as significant, so that there is not a big gain in programming efficiency by increasing the program time over conventional methods as illustrated by curve86inFIGS. 7 and 9. However, as the desired Vpgm level is relatively high, the effect of increasing the program time for such Vpgm levels after every program pulse will be significant. Thus by increasing the program time for such Vpgm levels after every program pulse only after Y number of pulses have been applied will achieve a significant gain in programming efficiency, while reducing the number of times the program time is adjusted.

As still another possible option different from those above, program time allocated may be increased, after Y number of pump pulses have been applied but not before this happens, each time X number of the programming pulses have been applied, where X is an integer equal to or greater than 2. This option is therefore a combination of prior options2and3. This option has advantages similar to those when options1and3are combined, but has the additional advantage that the number of program time adjustments is further reduced. The threshold voltage versus number of pulses plot for such combination will be along curve86of the conventional methods up to the point until Y number of pulses have been applied to the charge storage transistors, but along a curve (not shown) that is of substantially the same shape and slope as curve92inFIG. 9after such point.

Instead of counting the number of pulses from the charge pump, the program time may be adjusted as a function of the desired Vpgm level, but without responding to any counting of the pump pulses at all. Circuit52″ ofFIG. 6is another embodiment of circuit52ofFIG. 4. The embodiment ofFIG. 6includes a program control logic72(in logic circuit58ofFIG. 4) which provides the program voltage level (Vpgm level) in an indicator signal72ato the program time control logic52″. Similar to program time control logic52′ ofFIG. 5, program time control logic52″ also implements a lookup table. Logic52″ provides a program time control signal74which indicates a program time corresponding to the input Vpgm level72a. This program control time signal74is provided to sequencer68(in logic circuit58ofFIG. 4) which provides such signal to the charge pump32along line53. Logic72also provides the same Vpgm level signal72ato charge pump32along signal line98(not shown inFIG. 4), so that the charge pump generates a voltage pump pulse with such Vpgm voltage level. Circuit52″ can also be used to implement the three different options illustrated inFIG. 9, except that instead of increasing the program time after the application of one or more pulses, the program time is increased according to the Vpgm level called for by logic72. In one implementation of the embodiment ofFIG. 6, the program time is increased for every n incremental increases (i.e. nΔVpgm), where n is an integer equal to or greater than 1. Where n is of the value 1, the programming speed will be the same as the case where the program time is increased after every pump pulse, that is, along line84inFIGS. 7 and 9. Where n is of a value greater than 1, the programming speed will be the same as the case where the program time is increased after every n pump pulses, that is, along dotted92inFIG. 9. Where the program time is increased only once after m incremental increases, the result is illustrated also by option3and line94inFIG. 9.

Similar to the combination of options1and3and of options2and3above for the embodiment ofFIG. 5, similar combinations may be implemented for the embodiment ofFIG. 6. Thus, the program time may be increased for every n incremental increases (i.e. nΔVpgm), where n is an integer equal to or greater than 1, but only after Y incremental increases, and not before this happens. Where n is of the value 1, the programming speed will be the same as the case where options1and3are combined above for the embodiment ofFIG. 5. Where n is of a value greater than 1, the programming speed will be the same as the case where options2and3are combined above for the embodiment ofFIG. 5. These combinations have substantially the same advantages as those explained above for the corresponding combinations in reference to the embodiment ofFIG. 5

In another implementation of the embodiment ofFIG. 6, the program time is increased at certain values of Vpgm, where these values may be selected to optimize the system, and may correspond to the options1-3and combinations thereof as explained above. Under option1, the program time can be increased every time Vpgm is increased. Under option2, the program time is set to values corresponding to certain values of Vpgm, where these values may correspond to every X number of pulses in option2. Alternatively, the program time may be set to values corresponding to certain values of Vpgm, where these values do not correspond to every X number of pulses in option2. Under option3, the program time may be held constant in the programming cycle until the Vpgm exceeds a particular predetermined value, at which point the program time is increased to another value which stays unchanged until the end of the programming cycle.

From the above, it is evident that where the program control signal is generated in response to the Vpgm level from logic72ofFIG. 6, the program control signal is thus provided without making use of the output of charge pump32. In the embodiment ofFIG. 6, the pump pulses are not supplied to circuit52″. This is also true in the embodiment ofFIG. 5, where the pump pulses are not supplied to circuit52′. Hence circuit52′ does not make use of or otherwise measure or sense either the number or the amplitude of the pulses from the charge pump output; instead it simply deduce the program time needed from the pulse count provided by the counter64in logic58. The advantage of adjusting the program time without having to measure either the number or the amplitude of the program pulses from the charge pump output simplifies the implementation of the program time control.

While the invention has been described above by reference to various embodiments, it will be understood that changes and modifications may be made without departing from the scope of the invention, which is to be defined only by the appended claims and their equivalent. All references referred to herein are incorporated by reference.