Method of fabricating semiconductor device

Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0045567, filed on May 14, 2010 with the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Example embodiments of the inventive concepts relate to a method of fabricating a semiconductor device.

2. Description of Related Art

Semiconductor devices include volatile memory devices (such as a dynamic random access memory (DRAM) device and a static random access memory (SRAM) device) and non-volatile memory devices. Non-volatile memory devices can retain data even when no power is supplied. Such a non-volatile memory device may include an electrically erasable and programmable ROM (EEPROM) capable of electrically inputting and outputting data and a flash memory device.

SUMMARY

Example embodiments of the inventive concepts relate to a method of fabricating a semiconductor device capable of forming a metal silicide having a relatively uniform thickness in a desired (or, alternatively, predetermined) upper region of a gate pattern.

The inventive concepts are not limited to the following example embodiments. It should be understood that other embodiments that are not expressly described herein would also be readily appreciated by those of ordinary skill in the art.

In accordance with a non-limiting aspect of the inventive concepts, a method of fabricating a semiconductor device may include forming a plurality of gate patterns on a substrate. Subsequently, a liner insulating layer may be formed on surfaces of the plurality of gate patterns so as to have a first thickness. Then, a gap fill layer filling a gap between adjacent gate patterns may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). In addition, the liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness (which is smaller than the first thickness) in desired (or, alternatively, predetermined) upper and side regions of the plurality of gate patterns. A metal layer may also be formed on the liner insulating layer and the gap fill layer. A metal silicide may be formed using the metal layer. In particular, the upper regions of the plurality of gate patterns may be transformed into a metal silicide using the metal layer.

The method may further include forming an interlayer insulating layer on the liner insulating layer and the gap fill layer.

The method may further include removing the metal layer remaining after the metal silicide is formed. A spacer may be formed on a side surface of the metal silicide. The method may further include forming an interlayer insulating layer on the liner insulating layer, the gap fill layer, and the spacer.

Forming the plurality of gate patterns may further include forming a first insulating layer on the substrate. Subsequently, a first silicon layer may be formed on the first insulating layer. Then, a second insulating layer may be formed on the first silicon layer. A second silicon layer may be formed on the second insulating layer. Then, the first insulating layer, the first silicon layer, the second insulating layer, and the second silicon layer may be etched to form the plurality of gate patterns.

The first and second silicon layers may be formed of polycrystalline silicon doped with impurities.

The method may include forming the second insulating layer of an oxide/nitride/oxide (ONO) layer.

The method may include forming the gap fill layer of a carbon-containing oxide layer.

The method may include simultaneously recessing the liner insulating layer and the gap fill layer such that the liner insulating layer has the second thickness in the desired (or, alternatively, predetermined) upper and side regions of the plurality of gate patterns.

In accordance with another non-limiting aspect of the inventive concepts, a method of fabricating a semiconductor device may include forming at least one cell gate pattern and at least one selection gate pattern on a substrate. Subsequently, a liner insulating layer may be formed on surfaces of the cell gate pattern and the selection gate pattern so as to have a first thickness. A gap fill layer filling gaps between adjacent cell gate patterns and between the cell gate pattern and the selection gate pattern may be formed on the liner insulating layer by FCVD or SOG. The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness (which is smaller than the first thickness) in desired (or, alternatively, predetermined) upper and side regions of the cell gate pattern and the selection gate pattern. Then, the gap fill layer may be partially or completely removed. A metal layer may be formed on the liner insulating layer. A metal silicide may be formed using the metal layer. In particular, the upper regions of the cell gate pattern and selection gate pattern may be transformed into a metal silicide using the metal layer.

The method may further include forming spacers on side surfaces of the cell gate pattern and the selection gate pattern after the metal silicide is formed.

The method may further include forming an interlayer insulating layer on the liner insulating layer and the spacers.

The method may include forming the liner insulating layer by one of thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD).

The method may further include forming a passivation layer on the metal layer, before the metal silicide is formed.

The method may further include performing chemical mechanical polishing after the gap fill layer is formed.

The method may include forming the liner insulating layer of a silicon oxide layer or a silicon nitride layer.

The method may include forming the metal layer of a material selected from the group consisting of cobalt, tungsten, titanium, nickel, and an alloy thereof.

In accordance with still another non-limiting aspect of the inventive concepts, a method of fabricating a semiconductor device may include forming at least one selection gate pattern on a substrate. Subsequently, a liner insulating layer may be formed on a surface of the selection gate pattern so as to have a first thickness. A gap fill layer may then be formed on the liner insulating layer by FCVD or SOG. The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness (which is smaller than the first thickness) in desired (or, alternatively, predetermined) upper and side regions of the selection gate pattern. The gap fill layer may be removed. A metal layer may be formed on the liner insulating layer. A metal silicide may be formed using the metal layer. In particular, the upper regions of the selection gate pattern may be transformed into a metal silicide using the metal layer. Subsequently, a spacer may be formed on a side surface of the selection gate pattern. A polishing stopper may be formed on the liner insulating layer and the spacer. An interlayer insulating layer may be formed on the polishing stopper.

In the method of fabricating the semiconductor device, after the liner insulating layer and the gap fill layer are recessed, a metal layer may be formed on the liner insulating layer and the gap fill layer. Afterwards, a metal silicide may be formed using the metal layer. A spacer may be formed on a side surface of the metal silicide.

The method may further include forming a cell gate pattern on the substrate so as to be spaced apart from the selection gate pattern. The cell gate pattern may include a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate. Metal silicides may be formed on both the selection gate pattern and cell gate pattern.

The at least one selection gate pattern may include a string selection gate pattern and a ground selection gate pattern.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. These inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are merely provided to ensure that this disclosure is thorough and complete and fully conveys the inventive concepts to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may have been exaggerated for clarity.

FIG. 1Ais a plan view of a semiconductor device fabricated according to a first example embodiment of the inventive concepts, andFIG. 1Bis a cross-sectional view taken along line I-I′ ofFIG. 1A.

Referring toFIGS. 1A and 1B, the semiconductor device fabricated by the method according to the first example embodiment of the inventive concepts may include a substrate100in which an active region ACT is defined by an isolation layer (not shown). The active region ACT may be repeatedly aligned in an X direction. The active region ACT may also extend in a Y direction perpendicular to the X direction.

The substrate100may further include a plurality of gate patterns101aand101b. Here, the active region ACT may include impurity regions (not shown) such as channel regions (not shown) disposed between and on a side surface of the adjacent gate patterns101aand101b.

The plurality of gate patterns101aand101bmay include a cell gate pattern101adisposed in a first region A of the substrate100and a selection gate pattern101bdisposed in a second region B of the substrate100. Here, the selection gate pattern101bmay include a ground selection gate pattern connected to a ground selection line GSL and a string selection gate pattern connected to a string selection line SSL.

The cell gate pattern101amay include a tunnel insulating layer110a, a floating gate120a, an inter-gate insulating layer130a, and a control gate140a. Here, in a desired (or, alternatively, predetermined) upper region d1of the control gate140a, a metal silicide180amay be formed.

The tunnel insulating layer110amay be formed of a silicon oxide layer or a silicon nitride layer. The inter-gate insulating layer130amay be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked layer thereof. In detail, the inter-gate insulating layer130amay be formed of an ONO layer having a stacked structure (oxide/nitride/oxide) of an oxide layer, a nitride layer, and an oxide layer.

The floating gate120aand a control gate140amay be formed of poly-silicon (P-Si). The P-Si may be doped with N- or P-type impurities. The control gate140amay configure a word line (W/L), which extends in the X direction and is repeatedly aligned in the Y direction.

The selection gate pattern101bmay include a gate insulating layer110b, a lower selection gate pattern120b, an inter-gate insulating pattern130b, and an upper selection gate pattern140b. In a desired (or, alternatively, predetermined) upper region d1of the upper selection gate pattern140b, a metal silicide180bmay be formed. Here, the desired (or, alternatively, predetermined) upper region d1of the selection gate pattern140bmay be the same as the desired (or, alternatively, predetermined) upper region d1of the cell gate pattern140a. In other words, the metal silicide180bof the selection gate pattern101bmay have the same thickness as the metal silicide180aof the cell gate pattern101a.

The gate insulating layer110b, the lower selection gate pattern120b, the inter-gate insulating pattern130b, and the upper selection gate pattern140bmay be formed of the same materials as the tunnel insulating layer110a, the floating gate120a, the inter-gate insulating layer130a, and the control gate140aof the cell gate pattern101a, respectively.

The upper selection gate pattern140bof the ground selection gate pattern may extend in the X direction to configure the ground selection line GSL. The upper selection gate pattern140bof the string selection gate pattern may extend in the X direction to configure the string selection line SSL.

A liner insulating layer160may be disposed on surfaces of the cell gate pattern101aand the selection gate pattern101b. The liner insulating layer160may be an oxide layer or a nitride layer. In detail, the liner insulating layer160may be formed of a thermal oxide layer such as a high temperature oxide (HTO) layer or a medium temperature oxide (MTO) layer, a silicon oxide layer, or a silicon nitride layer.

The liner insulating layer160may have a first thickness t1. However, the liner insulating layer160may have a second thickness t2that is smaller than the first thickness t1in the desired (or, alternatively, predetermined) upper and side regions of the cell gate pattern101aand the selection gate pattern101b. In other words, the cell gate pattern101aand the selection gate pattern101bon which the metal silicides180aand180bare disposed may be covered by the liner insulating layer160having the second thickness t2.

The first thickness t1may be a thickness capable of inhibiting the formation of the metal silicides180aand180b. Thus, the first thickness t1may exceed 30 Å. On the other hand, the second thickness t2may be a thickness allowing the metal silicides180aand180bto be formed. Thus, the second thickness t2may be 10 Å or less.

The semiconductor device fabricated by the method according to the first example embodiment of the inventive concepts may further include spacers190disposed on side surfaces of the cell gate pattern101aand the selection gate pattern101b, and an interlayer insulating layer194disposed on the liner insulating layer160and the spacer190.

Here, the spacer190and the interlayer insulating layer194may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked layer thereof. The spacer190and the interlayer insulating layer194may be formed of the same material as each other. The spacer190disposed between the adjacent cell gate pattern101amay fill a gap between the adjacent cell gate patterns101a.

The semiconductor device fabricated by the method according to the first example embodiment of the inventive concepts may further include a polishing stopper192disposed between the liner insulating layer160, the spacer190, and the interlayer insulating layer194. The polishing stopper192may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof. Here, the polishing stopper192may be formed of a material having a different etch rate from the interlayer insulating layer194.

FIGS. 2A to 2Hare cross-sectional views sequentially illustrating a method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts.

The method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts will be described with reference toFIGS. 1B and 2Ato2H. First, the method, as shown inFIG. 2A, may include preparing a substrate100having a first region A and a second region B.

Subsequently, a first insulating layer110, a first silicon layer120, a second insulating layer130, and a second silicon layer140may be sequentially formed on the substrate100. Here, the second insulating layer130may be patterned to connect the first silicon layer120to the second silicon layer140in the second region B. After the first silicon layer120is patterned in the same shape as the active region ACT ofFIG. 1A, the second insulating layer130and the second silicon layer140may be formed on the first silicon layer120.

The first insulating layer110may be formed by thermal oxidation. The second insulating layer130may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof. The first silicon layer120and the second silicon layer140may be formed of P-Si. The P-Si may be doped with N- or P-type impurities.

Afterwards, a hard mask pattern150may be formed on the second silicon layer140. The hard mask pattern150may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof. The hard mask pattern150may be formed by forming an insulating layer for a hard mask (not shown) on the second silicon layer140, and patterning the insulating layer.

Subsequently, as shown inFIG. 2B, the first insulating layer110, the first silicon layer120, the second insulating layer130, and the second silicon layer140may be etched using the hard mask pattern150as a mask, thereby forming a plurality of gate patterns101aand101b. The plurality of gate patterns101aand101bmay include a cell gate pattern101adisposed in the first region A and a selection gate pattern101bdisposed in the second region B.

The hard mask pattern150may be removed by cleaning according to the etching of the first insulating layer110, the first silicon layer120, the second insulating layer130, and the second silicon layer140. Here, the hard mask pattern150may be removed by subsequent recessing of the liner insulating layer160and the gap fill layer170or cleaning.

The method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts may include doping impurities between the adjacent cell gate patterns101a, between the cell gate pattern101aand the selection gate pattern101b, and into the active region ACT disposed on the periphery of the selection gate pattern101busing the hard mask pattern150so as to form impurity regions (not shown).

In the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the impurity regions may be formed before a subsequent spacer or interlayer insulating layer forming process.

In the cell gate pattern101a, the etched first insulating layer110, first silicon layer120, second insulating layer130and second silicon layer140may be used as a tunnel insulating layer110a, a floating gate120a, an inter-gate insulating layer130aand a control gate140a, respectively. In the selection gate pattern101b, the etched first insulating layer110, first silicon layer120, second insulating layer130, and second silicon layer140may be used as a gate insulating layer110b, a lower selection gate pattern120b, an inter-gate insulating pattern130b, and an upper selection gate pattern140b, respectively.

In other words, the first insulating layer110, the first silicon layer120, the second insulating layer130, and the second silicon layer140in the first region A may form the tunnel insulating layer110a, the floating gate120a, the inter-gate insulating layer130a, and the control gate140aof the cell gate pattern101a, respectively. Further, the first insulating layer110, the first silicon layer120, the second insulating layer130, and the second silicon layer140in the second region B may form the gate insulating layer110b, the lower selection gate pattern120b, the inter-gate insulating pattern130b, and the upper selection gate pattern140bof the selection gate pattern101b, respectively.

The cell gate pattern101aand the selection gate pattern101bmay be simultaneously formed on the substrate100. However, the cell gate pattern101aand the selection gate pattern101bmay be formed by separate processes. Thus, in the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the cell gate pattern101aand the selection gate pattern101bmay be formed by different processes from each other.

Subsequently, as shown inFIG. 2C, a liner insulating layer160having a first thickness t1may be formed on surfaces of the plurality of gate patterns101aand101b. The liner insulating layer160may be formed by one of thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD).

The first thickness t1may be a thickness capable of preventing formation of metal silicides180aand180bdue to a metal layer180to be formed in a subsequent process. In other words, the liner insulating layer160having the first thickness t1may inhibit a chemical reaction between the metal layer180and the control gate140aor the upper selection gate pattern140b. Thus, the first thickness t1of the liner insulating layer160may exceed 30 Å. Here, the first thickness t1of the liner insulating layer160may be 50 to 200 Å in consideration of subsequent processes such as recessing, cleaning and etching.

Subsequently, a gap fill layer170may be formed on the liner insulating layer160by FCVD or SOG. Generally, according to FCVD or SOG, an insulating layer may have high flowability. Thus, the gap fill layer170formed by FCVD or SOG may completely fill the gap between the adjacent gate patterns101aand101b.

Here, after the gap fill layer170is formed, it may be planarized. The planarization of the gap fill layer170may be accomplished by chemical mechanical polishing (CMP).

Subsequently, as shown inFIG. 2D, the liner insulating layer160and the gap fill layer170may be recessed such that the liner insulating layer160has a second thickness t2smaller than the first thickness t1in the desired (or, alternatively, predetermined) upper and side regions d1of the plurality of gate patterns101aand101b.

The recess process may be performed by a dry cleaning method using NH3and HF or a dry etching method. The recess process may include ashing and stripping. The stripping may include organic stripping and HS stripping.

The second thickness t2may be a thickness capable of inducing the formation of the metal silicides180aand180bby the chemical reaction between the metal layer180to be formed in a subsequent process and the control gate140aor the upper selection gate pattern140b. Thus, the second thickness t2may be 10 Å or less. Here, the second thickness t2of the liner insulating layer160may be 30 Å or less in consideration of subsequent processes such as cleaning and etching.

The gap fill layer170may be formed by FCVD or SOG to completely fill the gap between the adjacent gate patterns101aand101b. Accordingly, it can prevent a void in the insulating layer generated between the adjacent gate patterns101aand101bdue to an increase in aspect ratio of the gate pattern. Thus, in the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the liner insulating layer160disposed on the surfaces of the plurality of gate patterns101aand101bmay be uniformly recessed.

Here, the liner insulating layer160and the gap fill layer170may be simultaneously recessed. To this end, the gap fill layer170may be formed to have a higher etch rate than the liner insulating layer160.

In this case, when the liner insulating layer160and the gap fill layer170are simultaneously recessed, the gap fill layer170may be removed faster than the liner insulating layer160. As a result, while a part of the liner insulating layer160remains in the desired (or, alternatively, predetermined) upper and side regions d1of the plurality of gate patterns101aand101b, the gap fill layer170may be completely recessed.

Table 1 shows the etch rates of oxide layers formed according to various deposition processes. Here, the unit of the etch rate is Å/min. As previously noted, terms “SOG” and “FCVD” are acronyms for “spin-on-glass” and “flowable chemical vapor deposition,” respectively. Furthermore, the term “C-FCVD” refers to a FCVD forming a carbon-containing insulating layer.

Referring to Table 1, the oxide layers formed by FCVD and SOG have higher etch rates than the thermal oxide layer. Thus, when the liner insulating layer160is formed by thermal oxidation, the liner insulating layer160and the gap fill layer170may be simultaneously recessed.

Referring again to Table 1, the carbon-containing oxide layer formed by C-FCVD has a higher etch rate than the oxide layers formed by FCVD and SOG. Thus, when the gap fill layer170is formed by C-FCVD without taking the method of forming the liner insulating layer160into consideration, the liner insulating layer160and the gap fill layer170may be simultaneously recessed.

As noted above, the liner insulating layer160and the gap fill layer170may be sequentially recessed. In further detail, the gap fill layer170may be first recessed by dry cleaning or dry etching to expose the liner insulating layer160in the desired (or, alternatively, predetermined) upper and side regions d1of the plurality of gate patterns101aand101b. Then, the liner insulating layer160may be recessed to have the second thickness t2in the desired (or, alternatively, predetermined) upper and side regions d1of the plurality of gate patterns101aand101b.

Subsequently, as shown inFIG. 2E, the gap fill layer170disposed on the liner insulating layer160may be removed. Thus, the gap fill layer170may be formed to have a different etch characteristic from the liner insulating layer160. In addition, when the gap fill layer170is formed to have a higher etch rate than the liner insulating layer160, the gap fill layer170may be more easily removed.

The removal of the gap fill layer170may be accomplished by wet cleaning using HF and DSC or wet etching using O3HF.

In the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the gap fill layer170may be completely removed. Alternatively, the gap fill layer170may only be partially removed.

As shown inFIG. 2F, a metal layer180may be formed on the liner insulating layer160. The metal layer180may be formed of a material selected from the group consisting of cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), and an alloy thereof. The metal layer180may be formed by physical vapor deposition (PVD), CVD, or ALD.

A passivation layer185may be further formed on the meal layer180. The passivation layer185may prevent oxidation of the metal layer180. The passivation layer185may be formed of titanium nitride (TiNx). The passivation layer185may be formed by CVD or ALD.

As shown inFIG. 2G, metal silicides180aand180bmay be formed using the metal layer180. Here, as described above, the liner insulating layer160having the first thickness t1may inhibit the formation of the metal silicides180aand180b. Thus, the metal silicides180aand180bmay be formed only in the desired (or, alternatively, predetermined) upper regions d1of the cell gate pattern101aand the selection gate pattern101bcovered by the liner insulating layer160having the second thickness t2.

The metal silicides180aand180bmay be formed by thermally treating the substrate100. The thermal treatment may be performed by several processes.

As shown inFIG. 2H, spacers190may be formed on side surfaces of the cell gate pattern101aand the selection gate pattern101b. The spacer190may be formed of a middle temperature oxide (MTO) layer by thermal oxidation. Here, after the remaining metal layer180and passivation layer185are removed, the spacers190may be formed.

As shown inFIG. 1B, an interlayer insulating layer194may be formed on the liner insulating layer160and the spacers190, and thus the semiconductor device fabricated by the method according to the first example embodiment of the inventive concepts may be completed.

A polishing stopper192may also be formed between the liner insulating layer160, the spacers190, and the interlayer insulating layer194. The polishing stopper192may be formed of a material having a different etch rate from the interlayer insulating layer194. For instance, the polishing stopper192may be formed of a nitride layer, and the interlayer insulating layer194may be formed of an oxide layer, although example embodiments are not limited thereto.

FIG. 3Ais a virtual scanning electron microscope (VSEM) picture of a semiconductor device fabricated by a conventional method, andFIG. 3Bis a VSEM picture of a semiconductor device fabricated by the method according to the first example embodiment of the inventive concepts.

Referring toFIG. 3A, it can be seen that, in the semiconductor device formed according to a conventional method, the metal silicides S formed on the gate patterns have different thicknesses from each other. On the other hand, referring toFIG. 3B, it can be seen that, in the semiconductor device formed according to the first example embodiment of the inventive concepts, the metal silicides S′ formed on the gate patterns have relatively uniform thicknesses.

Thus, compared to a conventional method, it can be seen that the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts forms the metal silicides to have relatively uniform thicknesses in desired (or, alternatively, predetermined) upper regions of the gate patterns.

FIG. 4is a graph of initial threshold voltages of semiconductor devices (F1and F2) having a gap fill layer formed by C-FCVD, which are fabricated by the method according to the first example embodiment of the inventive concepts, and a semiconductor device (Ref) fabricated by a conventional method. Here, inFIG. 4, the initial threshold voltages of the semiconductor devices F1and F2according to the first example embodiment of the inventive concepts and the semiconductor device Ref according to the conventional method are measured from two different patterns P1and P2.

Referring toFIG. 4, regardless of the change in pattern, it can be seen that the semiconductor devices F1and F2formed by the method according to the first example embodiment of the inventive concepts and the semiconductor device Ref according to the conventional method have the same initial threshold voltage.

Thus, it can be seen that, although the gap fill layer may be formed by C-FCVD in the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the current characteristics of the semiconductor device are not deteriorated.

As a result, according to the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the liner insulating layer may be formed to have different thicknesses in the region in which the metal silicides are formed on surfaces of the plurality of gate patterns using the liner insulating layer and the gap fill layer formed by FCVD or SOG, and in the other regions. Thus, according to the method of fabricating the semiconductor device according to the first example embodiment of the inventive concepts, the metal silicides may be formed to relatively uniform thicknesses in the desired (or, alternatively, predetermined) upper regions of the plurality of gate patterns.

FIGS. 5A to 5Gare cross-sectional views sequentially illustrating a method of fabricating a semiconductor device according to a second example embodiment of the inventive concepts.

The method of fabricating the semiconductor device according to the second example embodiment of the inventive concepts will be described with reference toFIGS. 5A to 5G. First, in the method according to the second example embodiment of the inventive concepts, as shown inFIG. 5A, a substrate200having a first region A and a second region B may be prepared. Here, the first region A of the substrate200may be a region in which a cell gate pattern201ais formed by a subsequent process. In addition, the second region B of the substrate200may be a region in which a selection gate pattern201bis formed by a subsequent process.

A third insulating layer210may be formed on the substrate200. The third insulating layer210may be a silicon oxide layer or a silicon nitride layer. The third insulating layer210may be formed by thermal oxidation. However, it should be understood that example embodiments are not limited to the above materials or method of forming.

A third silicon layer220may be formed on the third insulating layer210. The third silicon layer220may be formed of P-Si. The P-Si may be doped with N- or P-type impurities.

Subsequently, a fourth insulating layer230may be formed on the third silicon layer220. The fourth insulating layer230may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof. For example, the fourth insulating layer230may be formed of an ONO layer having a stacked structure of an oxide layer, a nitride layer, and an oxide layer.

A fourth silicon layer240may be formed on the fourth insulating layer230. The fourth silicon layer240may be formed of P-Si doped with N- or P-type impurities. Here, the fourth insulating layer230in the second region B may be patterned such that the third silicon layer220is in contact with the fourth silicon layer240.

The third insulating layer210, the third silicon layer220, the fourth insulating layer230, and the fourth silicon layer240may be as described in connection with the first insulating layer110, the first silicon layer120, the second insulating layer130, and the second silicon layer140of the first example embodiment of the inventive concepts.

A hard mask pattern250may be formed on the fourth silicon layer240. The hard mask pattern250may be formed by forming an insulating layer for a hard mask (not shown) on the fourth silicon layer240, and patterning the insulating layer.

Subsequently, as shown inFIG. 5B, the third insulating layer210, the third silicon layer220, the fourth insulating layer230, and the fourth silicon layer240may be etched using the hard mask pattern250as a mask to form a plurality of gate patterns201aand201b. The plurality of gate patterns201aand201bmay include a cell gate pattern201adisposed in the first region A and a selection gate pattern201bdisposed in the second region B.

Here, the cell gate pattern201amay include a tunnel insulating layer210a, a floating gate220a, an inter-gate insulating layer230a, and a control gate240a. The selection gate pattern201bmay include a gate insulating layer210b, a lower selection gate pattern220b, an inter-gate insulating pattern230b, and an upper selection gate pattern240b.

Thus, the third insulating layer210, the third silicon layer220, the fourth insulating layer230, and the fourth silicon layer240in the first region A may form the tunnel insulating layer210a, the floating gate220a, the inter-gate insulating layer230a, and the control gate240aof the cell gate pattern201a, respectively. The third insulating layer210, the third silicon layer220, the fourth insulating layer230, and the fourth silicon layer240in the second region B may form the gate insulating layer210b, the lower selection gate pattern220b, the inter-gate insulating pattern230b, and the upper selection gate pattern240bof the selection gate pattern201b.

The cell gate pattern201aand the selection gate pattern201bmay be simultaneously formed on the substrate200. However, it should be understood that the cell gate pattern201aand the selection gate pattern201bmay be sequentially formed by separate processes, respectively. In the method of fabricating the semiconductor device according to the second example embodiment of the inventive concepts, the cell gate pattern201aand the selection gate pattern201bmay be formed by different processes from each other.

Subsequently, impurities may be doped between the adjacent cell gate patterns201a, between the cell gate pattern201aand the selection gate pattern201b, and into a peripheral active region (not shown) of the selection gate pattern201busing the hard mask pattern250, thereby forming impurity regions205.

As shown inFIG. 5C, a liner insulating layer260may be formed to a third thickness t3on the plurality of gate patterns201aand201b. The liner insulating layer260may be one of a thermal oxide layer such as an HTO layer or an MTO layer, a silicon oxide layer, and a silicon nitride layer. The liner insulating layer260may be formed by one of thermal oxidation, CVD, and ALD.

The third thickness t3(which corresponds to the first thickness t1described in the first example embodiment of the inventive concepts) may be a thickness capable of inhibiting formation of metal silicides280aand280b. Thus, the third thickness t3may exceed 30 Å like the first thickness t1. The third thickness t3of the liner insulating layer260may be 50 to 200 Å in consideration of subsequent processes such as recessing, cleaning, and etching.

Subsequently, a gap fill layer270may be formed on the liner insulating layer260by FCVD or SOG. As described above, the gap fill layer270formed by FCVD or SOG may completely fill a gap between the adjacent gate patterns201aand201b.

Here, after the gap fill layer270is formed, it may be planarized by CMP.

Subsequently, as shown inFIG. 5D, the liner insulating layer260and the gap fill layer270may be recessed such that the liner insulating layer260has a fourth thickness t4that is smaller than the third thickness t3in the desired (or, alternatively, predetermined) upper and side regions d2of the plurality of gate patterns201aand201b.

The fourth thickness t4(which corresponds to the second thickness t2described in the first example embodiment of the inventive concepts) may be a thickness capable of forming the metal silicides280aand280b. The fourth thickness t4may be 10 Å or less, which may be the same as the second thickness t2. The fourth thickness t4may be 30 Å or less in consideration of subsequent processes such as cleaning and etching.

The recess process may use dry cleaning using NH3and HF or dry etching. The recess process may also include ashing and stripping. For instance, the recess process may include organic stripping and HS stripping, although example embodiments are not limited thereto.

The liner insulating layer260and the gap fill layer270may be simultaneously recessed. To this end, the liner insulating layer260and the gap fill layer270may have different etch rates from each other.

As described in the first example embodiment of the inventive concepts, when the liner insulating layer260is formed by thermal oxidation, the liner insulating layer260and the gap fill layer270may be simultaneously recessed. When the gap fill layer270is formed by C-FCVD, regardless of the method of forming the liner insulating layer260, the liner insulating layer260and the gap fill layer270may be simultaneously recessed.

Alternatively, the liner insulating layer260and the gap fill layer270may be sequentially recessed.

Subsequently, as shown inFIG. 5E, a metal layer280may be formed on the liner insulating layer260and the gap fill layer270. The metal layer280may be formed from a material selected from the group consisting of cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), and an alloy thereof. The metal layer280may be formed by one of PVD, CVD, and ALD.

A passivation layer285may be further formed on the metal layer280. The passivation layer285may prevent oxidation of the metal layer280. The passivation layer285may be formed of titanium nitride (TiNx). The passivation layer285may be formed by CVD or ALD.

Subsequently, as shown inFIG. 5F, the metal silicides280aand280bmay be formed using the metal layer280. Here, as described in the first example embodiment of the inventive concepts, the metal silicides280aand280bmay be formed only in a desired (or, alternatively, predetermined) upper region d2of the cell gate pattern201aand the selection gate pattern201bcovered with the liner insulating layer260having the fourth thickness t4.

As shown inFIG. 5G, after the metal silicides280aand280bare formed, the remaining metal layer280and passivation layer285may be removed. Subsequently, spacers290may be formed on side surfaces of the metal silicides280aand280b. The spacers290may be formed of an MTO layer by thermal oxidation.

Although not shown, an interlayer insulating layer (not shown) may be formed on the liner insulating layer260, the gap fill layer270, and the spacers290, and thus the semiconductor device formed by the method according to the second example embodiment of the inventive concepts may be completed.

A polishing stopper (not shown) may be further formed between the liner insulating layer260, the gap fill layer270, the spacers290, and the interlayer insulating layer. The polishing stopper may be formed of a material having a different etch rate from the interlayer insulating layer.

As a result, the liner insulating layer may be formed to different thicknesses in the region in which the metal silicides are formed on the surfaces of the plurality of gate patterns and in the other regions. Further, the metal layer may be formed without removing the gap fill layer filling the gap between the adjacent gate patterns. Accordingly, the metal silicides having a relatively uniform thickness in the desired (or, alternatively, predetermined) upper regions of the plurality of gate patterns may be formed using a simpler process in the method of fabricating the semiconductor device according to the second example embodiment of the inventive concepts.

FIGS. 6A and 6Bare cross-sectional views illustrating a method of fabricating a semiconductor device according to a third example embodiment of the inventive concepts.

The method of fabricating the semiconductor device according to the third example embodiment of the inventive concepts will be described with reference toFIGS. 6A and 6B. First, as shown inFIG. 6A, a substrate300having a first region A and a second region B may be prepared. Here, the first region A of the substrate300may be a region in which a cell gate pattern301ais formed by a subsequent process. The second region B of the substrate300may be a region in which a selection gate pattern301bis formed by a subsequent process.

Subsequently, a fifth insulating layer (not shown), a fifth silicon layer (not shown), a sixth insulating layer (not shown), and a sixth silicon layer (not shown) may be sequentially formed on the substrate300. The fifth insulating layer, the fifth silicon layer, the sixth insulating layer, and the sixth silicon layer may correspond to the first insulating layer110, the first silicon layer120, the second insulating layer130, and the second silicon layer140described in the first example embodiment of the inventive concepts. Thus, the descriptions of the fifth insulating layer, the fifth silicon layer, the sixth insulating layer, and the sixth silicon layer will be omitted herein for purposes of brevity.

A hard mask pattern (not shown) may be formed on the sixth silicon layer. The hard mask pattern may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof. The hard mask pattern may be formed by forming an insulating layer for a hard mask (not shown) on the sixth silicon layer, and patterning the insulating layer.

Subsequently, the fifth insulating layer, the fifth silicon layer, the sixth insulating layer, and the sixth silicon layer may be etched using the hard mask pattern as a mask to form a plurality of gate patterns301aand301b. The plurality of gate patterns301aand301bmay include a cell gate pattern301adisposed in the first region A and a selection gate pattern301bdisposed in the second region B.

Here, the cell gate pattern301amay include a tunnel insulating layer310a, a floating gate320a, an inter-gate insulating layer330a, and a control gate340a. The selection gate pattern301bmay include a gate insulating layer310b, a lower selection gate pattern320b, an inter-gate insulating pattern330b, and an upper selection gate pattern340b.

The cell gate pattern301aand the selection gate pattern301bmay be simultaneously formed on the substrate300. However, it should be understood that the cell gate pattern301aand the selection gate pattern301bmay also be formed by separate processes, respectively. In the method of fabricating the semiconductor device according to the third example embodiment of the inventive concepts, the cell gate pattern301aand the selection gate pattern301bmay be formed by different processes from each other.

Impurities may be doped between the adjacent cell gate patterns301a, between the cell gate pattern301aand the selection gate pattern301b, and into a peripheral active region (not shown) of the selection gate pattern301busing the hard mask pattern, thereby forming impurity regions (not shown).

Subsequently, a liner insulating layer360may be formed to a fifth thickness t5on the plurality of gate patterns301aand301b. The liner insulating layer360may be formed of one of a thermal oxide layer such as an HTO layer or an MTO layer, a silicon oxide layer, and a silicon nitride layer. The liner insulating layer360may be formed by one of thermal oxidation, CVD, and ALD.

The fifth thickness t5(which corresponds to the first thickness t1according to the first example embodiment of the inventive concepts) may be a thickness capable of inhibiting the formation of metal silicides380aand380b. Thus, the fifth thickness t5may exceed 30 Å, which may be the same as the first thickness t1. For example, the fifth thickness t5may be 50 to 200 Å in consideration of processes such as recession, cleaning, and etching.

Subsequently, a gap fill layer (not shown) may be formed on the liner insulating layer360by FCVD or SOG. As described above, the gap fill layer formed by FCVD or SOG may completely fill a gap between the adjacent gate patterns301aand301b.

After the gap fill layer is formed, it may be planarized by CMP.

Subsequently, the liner insulating layer360and the gap fill layer may be recessed to expose the desired (or, alternatively, predetermined) upper and side regions d3of the plurality of gate patterns301aand301b.

Afterwards, a surface layer362may be formed to a sixth thickness t6on surfaces of the desired (or, alternatively, predetermined) upper and side regions d3of the plurality of gate patterns301aand301b.

The sixth thickness t6(which corresponds to the second thickness t2described according to the first example embodiment of the inventive concepts) may be a thickness capable of forming the metal silicides380aand380b. Thus, the sixth thickness t6, which may be the same as the second thickness t2, may be 10 Å or less. In a non-limiting embodiment, the sixth thickness t6may be 30 Å or less in consideration of subsequent processes such as cleaning and etching.

The recess process may use dry cleaning using NH3and HF or dry etching. The recess process may also include ashing and stripping. For instance, the stripping may include organic stripping and HS stripping.

The liner insulating layer360and the gap fill layer may be simultaneously recessed. To this end, the liner insulating layer360and the gap fill layer may have different etch rates from each other. In this case, as described in the first example embodiment of the inventive concepts, the liner insulating layer360may be formed by thermal oxidation. The gap fill layer may be formed by C-FCVD.

Alternatively, it should be understood that the liner insulating layer360and the gap fill layer may be sequentially recessed.

Then, the gap fill layer disposed on the liner insulating layer360may be removed. The removal of the gap fill layer may be accomplished by wet cleaning using HF and DSC or wet etching using HS or O3HF.

The gap fill layer may be completely removed. However, in the method of fabricating the semiconductor device according to the third example embodiment of the inventive concepts (as also described in connection with the first example embodiment of the inventive concepts), the gap fill layer may be partially removed.

Subsequently, referring toFIG. 6B, a metal layer (not shown) may be formed on the liner insulating layer360. The metal layer may be formed of a material selected from the group consisting of cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), and an alloy thereof. The metal layer may be formed by PVD, CVD, and ALD.

A passivation layer (not shown) may be further formed on the metal layer. The passivation layer may prevent oxidation of the metal layer. The passivation layer may be formed of titanium nitride (TiNx), although example embodiments are not limited thereto. The passivation layer may be formed by CVD or ALD.

Then, metal silicides380aand380bmay be formed using the metal layer. Here, as described above, the liner insulating layer360having the fifth thickness t5may inhibit formation of the metal silicides380aand380b. Thus, the metal silicides380aand380bmay be formed only in the desired (or, alternatively, predetermined) upper regions d3of the cell gate pattern301aand the selection gate pattern301bcovered with the surface layer362having the sixth thickness t6.

After the metal silicides380aand380bare formed, the remaining metal layer and passivation layer may be removed. Subsequently, spacers390may be formed on side surfaces of the cell gate pattern301aand the selection gate pattern301b. The spacers390may be formed of an MTO layer by thermal oxidation.

Subsequently, a polishing stopper392may be formed on the liner insulating layer360, the surface layer362, and the spacers390. The polishing stopper392may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof.

Then, an interlayer insulating layer394may be formed on the polishing stopper392, and thus the semiconductor device formed by the method according to the third example embodiment of the inventive concepts may be completed. Here, the interlayer insulating layer394may be formed of a material having a different etch rate from the polishing stopper392.

As a result, in the method of fabricating the semiconductor device according to the third example embodiment of the inventive concepts, a liner insulating layer may be formed to different thicknesses in the region in which the metal silicides are formed on the plurality of gate patterns using the liner insulating layer and the gap fill layer formed by FCVD or SOG and in the other regions. In detail, the liner insulating layer may be formed on the surfaces of the plurality of gate patterns in the region in which the metal silicides will be formed to have a smaller thickness than those in the other regions. Accordingly, the metal silicides may be formed to a relatively uniform thickness in the desired (or, alternatively, predetermined) upper region of the plurality of gate patterns using a difference in thickness of the liner insulating layer.

FIG. 7is a cross-sectional view illustrating a method of fabricating a semiconductor device according to a fourth example embodiment of the inventive concepts.

The method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts will be described with reference toFIG. 7. In the method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts, a substrate400including a first region A and a second region B may be prepared. Here, the first region A of the substrate400may be a region in which a cell gate pattern401ais formed by a subsequent process. The second region B of the substrate400may be a region in which a selection gate pattern401bis formed by a subsequent process.

Subsequently, a charge tunneling layer410, a charge trapping layer420, and a charge blocking layer430may be formed on the substrate400. Here, the charge tunneling layer410may be a layer in which a charge is tunneled.

The charge tunneling layer410may be formed of a high-k dielectric material such as Al2O3, HfO2, La2O3, Ta2O3, TiO2, SrTiO3(STO), or (Ba, Sr)TiO3(BST), or a combination layer in which these materials are stacked. The charge tunneling layer410may be formed by thermal oxidation, CVD, or ALD.

The charge trapping layer420may store the charges by trapping the tunneled charges. The charge trapping layer420may be formed of silicon nitride (SixNy), although example embodiments are not limited thereto. For instance, the charge trapping layer420may also be formed of a metal nitride or metal oxynitride.

The charge blocking layer430may insulate the charge trapping layer420from a gate electrode440formed by a subsequent process. The charge blocking layer430may be formed of a high-k dielectric material such as Al2O3, HfO2, La2O3, Ta2O3, TiO2, SrTiO3(STO), or (Ba, Sr)TiO3(BST), or a combination layer in which these materials are stacked. Here, the charge blocking layer430may be formed of a material having a higher dielectric constant than the charge tunneling layer410.

Then, the charge tunneling layer410, the charge trapping layer420, and the charge blocking layer430may be etched to form a plurality of trap structures415. In the method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts, the trap structures415may be formed in both the first and second regions A and B of the substrate400in the same manner.

Subsequently, a seventh silicon layer (not shown) may be formed on the trap structures415. The seventh silicon layer may be formed of P-Si doped with N- or P-type impurities.

A hard mask pattern (not shown) may be formed on the seventh silicon layer. The hard mask pattern may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof. The hard mask pattern may be formed by forming an insulating layer (not shown) for a hard mask on the seventh silicon layer, and patterning the insulating layer.

Afterwards, the seventh silicon layer may be etched using the hard mask pattern as a mask to form the gate electrode440on the trap structures415, thereby forming gate patterns401aand401bof a charge trap-type non-volatile memory device. The plurality of gate patterns401aand401bmay include the call gate pattern401adisposed in the first region A and the selection gate pattern401bdisposed in the second region B.

In the method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts, silicon/oxide/nitride/oxide/silicon (SONOS)-type gate patterns are formed as the charge trap-type gate patterns401aand401b. However, in the method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts, as the charge trap-type gate patterns401aand401b, it should be understood that metal/nitride/oxide/silicon (MNOS)- or metal/oxide/nitride/oxide/silicon (MONOS)-type gate patterns may also be formed.

Subsequently, impurities may be doped between the adjacent cell gate patterns401a, between the cell gate pattern401aand the selection gate pattern401b, and into a peripheral active region (not shown) of the selection gate pattern401busing the hard mask pattern, thereby forming impurity regions (not shown).

A liner insulating layer460may be formed on surfaces of the plurality of gate patterns401aand401bto have a seventh thickness t7. The liner insulating layer460may be formed of one of a thermal oxide layer such as an HTO layer or an MTO layer, a silicon oxide layer, and a silicon nitride layer. The liner insulating layer460may be formed by one of thermal oxidation, CVD, and ALD.

The seventh thickness t7(which corresponds to the first thickness t1according to the first example embodiment of the inventive concepts) may be a thickness capable of inhibiting formation of metal silicides480. Thus, the seventh thickness t7may exceed 30 Å, which may be the same as the first thickness t1. In a non-limiting embodiment, the seventh thickness t7may be 50 to 200 Å in consideration of processes such as recession, cleaning, and etching.

Subsequently, a gap fill layer (not shown) may be formed on the liner insulating layer460by FCVD or SOG. As described above, the gap fill layer formed by FCVD or SOG may fill a gap between the adjacent gate patterns401aand401b.

After the gap fill layer is formed, it may be planarized by CMP.

The liner insulating layer460and the gap fill layer may be recessed such that the liner insulating layer460has an eighth thickness t8, which is smaller than the seventh thickness t7, in the desired (or, alternatively, predetermined) upper and side regions d4of the plurality of gate patterns401aand401b.

The eighth thickness t8(which corresponds to the second thickness t2according to the first example embodiment of the inventive concepts) may be a thickness capable of forming the metal silicides480. Thus, the eighth thickness t8may be 10 Å or less like the second thickness t2. In addition, the eighth thickness t8may be 30 Å or less in consideration of subsequent processes such as cleaning and etching.

The recess process may use dry cleaning using NH3and HF or dry etching. The recess process may also include ashing and stripping. For instance, the stripping may include organic stripping and HS stripping.

The liner insulating layer460and the gap fill layer may be simultaneously recessed. To this end, the liner insulating layer460and the gap fill layer may have different etch rates from each other. In this case, as described in the first example embodiment of the inventive concepts, the liner insulating layer460may be formed by thermal oxidation. The gap fill layer may be formed by C-FCVD.

Alternatively, it should be understood that the liner insulating layer460and the gap fill layer may be sequentially recessed.

Subsequently, the gap fill layer disposed on the liner insulating layer460may be removed. The removal of the gap fill layer may be accomplished by wet cleaning using HF and DSC or wet etching using O3HF.

The gap fill layer may be completely removed. Alternatively, as described in the first example embodiment of the inventive concepts, the gap fill layer may be partially removed.

Subsequently, a metal layer (not shown) may be formed on the liner insulating layer460. The metal layer may be formed of a material selected from the group consisting of cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), and an alloy thereof. The metal layer may be formed by one of PVD, CVD, and ALD.

A passivation layer (not shown) may be further formed on the metal layer. The passivation layer may prevent oxidation of the metal layer. The passivation layer may be formed of a titanium nitride (TiNx), although example embodiments are not limited thereto. The passivation layer may be formed by CVD or ALD.

Then, the metal silicides480may be formed using the metal layer. Here, as described above, the liner insulating layer460having the seventh thickness t7may inhibit the formation of the metal silicides480. Thus, the metal silicides480may be formed only in the desired (or, alternatively, predetermined) upper regions d4of the cell gate pattern401aand the selection gate pattern401bcovered with a surface layer362having the eighth thickness t8.

After the metal silicides480are formed, the remaining metal layer and passivation layer may be removed. Subsequently, spacers490may be formed on side surfaces of the cell gate pattern401aand the selection gate pattern401b. The spacers490may be formed of an MTO layer by thermal oxidation.

A polishing stopper492may be formed on the liner insulating layer460and the spacers490. The polishing stopper492may be formed of a material selected from the group consisting of an oxide layer, a nitride layer, and a stacked combination layer thereof.

Subsequently, an interlayer insulating layer494may be formed on the polishing stopper492, and thus the semiconductor device formed by the method according to the fourth example embodiment of the inventive concepts may be completed. Here, the interlayer insulating layer494may be formed of a material having a different etch rate from the polishing stopper492.

As a result, in the method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts, the liner insulating layer may be formed to have different thicknesses on the surfaces of the gate patterns of the SONOS-type semiconductor device using the liner insulating layer and the gap fill layer formed by FCVD or SOG. In detail, the liner insulating layer may be formed to a smaller thickness in the region in which the metal silicides will be formed on the surfaces of the plurality of gate patterns than in the other regions. Accordingly, in the method of fabricating the semiconductor device according to the fourth example embodiment of the inventive concepts, the metal silicides may be formed in the desired (or, alternatively, predetermined) upper regions of the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

FIG. 8is a diagram of a device including a semiconductor device fabricated by one of the methods according to the example embodiments of the inventive concepts.

The device may be a data storage device such as a solid state disk (SSD)500.

The SSD500may be a device storing information using the semiconductor device. Compared to a hard disk drive (HDD), the SSD500processes data faster, and has less mechanical delay or failure, heat, and noise. In addition, the SSD500can be compact and light. The SSD500may be applied to laptop computers, desktop computers, MP3 players, or portable storage devices.

Referring toFIG. 8, the SSD500may include a non-volatile memory510, a buffer memory520, and a controller530. Here, the non-volatile memory510may be fabricated by one of the methods according to the example embodiments of the inventive concepts. The non-volatile memory510may be a resistive memory. The non-volatile memory510may include a data storage element such as one selected from the group consisting of a phase change material pattern, a magnetic tunnel junction (MTJ) pattern, a polymer pattern, and an oxide pattern.

The buffer memory520may include a volatile memory. The volatile memory may be DRAM or SRAM. The buffer memory520may exhibit a higher operating speed than the non-volatile memory510.

The controller530may include an interface535connected to a host550. The interface535may be in contact with the host500to transmit and receive electrical signals such as data. The interface535may be a device using one standard selected from the group consisting of SATA, IDE, SCSI, and a composition thereof.

The data processing rate of the interface535may be higher than the operating speed of the non-volatile memory510. Here, the buffer memory520may serve to temporarily store data. The data received by the interface535may be temporarily stored in the buffer memory520via the controller530, and then permanently stored in the non-volatile memory510at a data writing speed of the non-volatile memory510.

Furthermore, frequently-used data of the data stored in the non-volatile memory510may be temporarily stored in the buffer memory510through pre-reading. In other words, the buffer memory510may serve to increase an efficient operating speed and reduce an error rate of the SSD500.

The controller530may include a memory controller (not shown) and a buffer controller (not shown). The non-volatile memory510may be in electrical contact with the adjacent controller530. The data storage capacity of the SSD500may correspond to the non-volatile memory510. The buffer memory520may be in electrical contact with the adjacent controller530.

The non-volatile memory510may be in contact with the interface535via the controller530. The non-volatile memory510may serve to store the data received by the interface535. As a result, even when the power supplied to the SSD500is interrupted, the data stored in the non-volatile memory510may be conserved.

The data processing speed of the interface535may be higher than the operating speed of the non-volatile memory510. Here, the buffer memory520may serve to temporarily store data. The data received by the interface535may be temporarily stored in the buffer memory520via the controller530, and then permanently stored in the non-volatile memory510at the data writing speed of the non-volatile memory510. Furthermore, frequently-used data of the data stored in the non-volatile memory510may be temporarily stored in the buffer memory520by pre-reading. In other words, the buffer memory520may serve to increase an efficient operating speed and reduce an error rate of the SSD500.

FIG. 9is a diagram of an electronic system apparatus including a semiconductor device fabricated by one of the methods according to the example embodiments of the inventive concepts.

Referring toFIG. 9, an apparatus600including the semiconductor device fabricated by one of the methods according to the example embodiments of the inventive concepts may include a controller610, an input/output device620, a memory630, and an interface640.

Each of the components of the apparatus600may be in contact with each other by a bus650. The input/output device620may be a device such as a keyboard or display. The controller610may include at least one microprocessor, a digital processor, a microcontroller or a processor.

The memory630may store data and/or a command run by the controller610. The interface640may be used to transmit or receive data to or from another system such as a communication network.

The apparatus600may be a mobile system such as a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or other system capable of transmitting and/or receiving information.

In a method of fabricating a semiconductor device according to the inventive concepts, a liner insulating layer may be formed to have a first thickness on a surface of a gate pattern. The liner insulating layer may be then recessed to have a second thickness, which is smaller than the first thickness, in a desired (or, alternatively, predetermined) region of the gate pattern. Afterwards, a metal silicide may be formed to have a relatively uniform thickness on the plurality of gate patterns using the difference in thickness of the liner insulating layer. In other words, the liner insulating layer may be formed on the surface of the gate pattern to have the desired (or, alternatively, predetermined) difference in thickness, and the metal silicide may be formed to have a relatively uniform thickness.

The foregoing is merely illustrative of various embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages disclosed herein. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined in the claims. In the claims, any means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is merely illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.