Method for creating a fully self-aligned via

Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a liner that is selectively removable when compared to conductive lines. The liner may be selectively removed by utilizing one or more of a base (e.g. sodium hydroxide) and hydrogen peroxide.

TECHNICAL FIELD

Embodiments of the present disclosure pertain to the field of electronic device manufacturing, and in particular, to an integrated circuit (IC) manufacturing. More particularly, embodiments of the disclosure are directed to methods of vias or contacts which skip a layer.

BACKGROUND

Generally, an integrated circuit (IC) refers to a set of electronic devices, e.g., transistors formed on a small chip of semiconductor material, typically, silicon. Typically, the IC includes one or more layers of metallization having metal lines to connect the electronic devices of the IC to one another and to external connections. Typically, layers of the interlayer dielectric material are placed between the metallization layers of the IC for insulation.

As the size of the IC decreases, the spacing between the metal lines decreases. Typically, to manufacture an interconnect structure, a planar process is used that involves aligning and connecting one layer of metallization to another layer of metallization.

Typically, patterning of the metal lines in the metallization layer is performed independently from the vias above that metallization layer. Conventional via manufacturing techniques, however, cannot provide the full via self-alignment. In the conventional techniques, the vias formed to connect lines in an upper metallization layer to a lower metallization are often misaligned to the lines in the lower metallization layer. The via-line misalignment increases via resistance and leads to potential shorting to the wrong metal line. The via-line misalignment causes device failures, decreases yield, and increases manufacturing cost. Additionally, the conventional methods using a liner do not provide for methods of selectively removed the liner relative to the metal. Thus, there is a need for new methods of removing a liner.

SUMMARY

Apparatuses and methods to provide a fully self-aligned via are described. In one embodiment, a method of forming a self-aligned via is described. A substrate is provided having a first insulating layer thereon. The first insulating layer having a top surface and a plurality of trenches formed along a first direction. The plurality of trenches have recessed conductive lines extending along the first direction and have a first conductive surface below the top surface of the first insulating layer. A liner comprising tantalum is formed on the recessed first conductive lines. At least one pillar is formed on the recessed first conductive lines. The at least one pillar extends orthogonal to the top surface of the first insulating layer. A second insulating layer is deposited around the first pillars and on the top surface of the first insulating layer. At least one of the pillars is removed to form at least one opening in the second insulating layer, leaving at least one pillar on the recessed first conductive lines. The liner is removed from the recessed first conductive lines using one or more of a base and hydrogen peroxide.

One or more embodiments are directed to methods to provide a fully self-aligned via. A substrate is provided having a first insulating layer thereon. The first insulating layer has a top surface and a plurality of trenches formed along a first direction. The plurality of trenches have recessed first conductive lines extending along the first direction and have a first conductive surface below the top surface of the first insulating layer. The first insulating layer comprises ultra low-k and the recessed first conductive lines comprise copper or cobalt. A liner comprising tantalum is formed on the recessed first conductive lines. A metal film comprising tungsten is formed on the recessed first conductive lines. At least one pillar comprising tungsten oxide is grown from the metal film on the recessed first conductive lines. The at least one pillar extends orthogonal to the top surface of the first insulating layer. A second insulating layer is deposited on the first insulating layer, around the at least one pillar and on a top of the at least one pillar to form an overburden of the second insulating layer. The second insulating layer is planarized to remove the overburden of the second insulating layer and expose the top of the at least one pillar. At least one of the pillars is selectively removed to form at least one opening in the second insulating layer, leaving at least one pillar on the recessed first conductive lines. The liner is removed from the recessed first conductive lines using a base and hydrogen peroxide in a ratio of about 1:1 to about 5:1. The base is selected from one or more of sodium hydroxide, potassium hydroxide, aluminum hydroxide, lithium hydroxide, rubidium hydroxide, cesium hydroxide, pyridine, ammonium hydroxide, trimethylamine (TMA), trimethylamine (TEA), or tetramethylammonium hydroxide (TMAH). A third insulating layer is deposited through the at least one opening onto the recessed conductive lines. The third insulating is etched selectively relative to the second insulating layer to form at least one via opening to the first conductive lines. A second conductive material is deposited in the at least one opening to form a via and second conductive lines. The first via connects the recessed first conductive lines to the second conductive lines.

DETAILED DESCRIPTION

Apparatuses and methods to provide a fully self-aligned via are described. In one embodiment, a method of forming a self-aligned via is described. A substrate is provided having a first insulating layer thereon. The first insulating layer having a top surface and a plurality of trenches formed along a first direction. The plurality of trenches have recessed conductive lines extending along the first direction and have a first conductive surface below the top surface of the first insulating layer. A liner comprising tantalum is formed on the recessed first conductive lines. At least one pillar is formed on the recessed first conductive lines. The at least one pillar extends orthogonal to the top surface of the first insulating layer. A second insulating layer is deposited around the first pillars and on the top surface of the first insulating layer. At least one of the pillars is removed to form at least one opening in the second insulating layer, leaving at least one pillar on the recessed first conductive lines. The liner is removed from the recessed first conductive lines using one or more of a base and hydrogen peroxide.

In one or more embodiment, depositing the second insulating layer comprises depositing a second insulating material on the first insulating layer, around and on a top of the at least one pillar to form an overburden of the second insulating layer; and planarizing the second insulating layer to remove the overburden of the second insulating layer and expose the top of the at least one pillar.

In one embodiment, the bridging via is self-aligned along the first direction to one of the second conductive lines.

In one embodiment, a fully self-aligned via is the via that is self-aligned along at least two directions to the conductive lines in a lower and an upper metallization layer. In one embodiment, the fully self-aligned via is defined by a hard mask in one direction and the underlying insulating layer in another direction, as described in further detail below.

Comparing to the conventional techniques, some embodiments advantageously provide fully self-aligned vias that cause no damage to the dielectric material(s) and does not need a high aspect ratio dielectric etch. In some embodiments, the fully self-aligned vias provide lower via resistance and capacitance benefits over the conventional vias. Some embodiments of the self-aligned vias provide full alignment between the vias and the conductive lines of the metallization layers that is substantially error free that advantageously increase the device yield and reduce the device cost.

In the following description, numerous specific details, such as specific materials, chemistries, dimensions of the elements, etc. are set forth in order to provide thorough understanding of one or more of the embodiments of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor fabrication processes, techniques, materials, equipment, etc., have not been descried in great details to avoid unnecessarily obscuring of this description. Those of ordinary skill in the art, with the included description, will be able to implement appropriate functionality without undue experimentation.

While certain exemplary embodiments of the disclosure are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current disclosure, and that this disclosure is not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

Reference throughout the specification to “one embodiment”, “another embodiment”, or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in a least one embodiment of the present disclosure. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1Aillustrates a cross-sectional view100of an electronic device structure to provide a fully self-aligned via according to one embodiment.FIG. 1Bis a top view110of the electronic device depicted inFIG. 1A, andFIG. 1Cis a perspective view120of the electronic device depicted inFIG. 1A. A lower metallization layer (Mx) comprises a set of conductive lines103that extend along an X axis (direction)121on an insulating layer102on a substrate101. The X axis ofFIGS. 1A-1Cextends orthogonally to the plane of the Figure page. As shown inFIGS. 1A-1C, X axis (direction)121crosses Y axis (direction)122at an angle123. In one embodiment, angle123is about 90 degrees. In another embodiment, angle123is an angle that is other than the 90 degrees angle. The insulating layer102comprises trenches104. The conductive lines103are deposited in trenches104.

In an embodiment, the substrate101comprises a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide (InAlAs), other semiconductor material, or any combination thereof. In an embodiment, substrate101is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any material listed above, e.g., silicon. In various embodiments, the substrate101can be, e.g., an organic, a ceramic, a glass, or a semiconductor substrate. Although a few examples of materials from which the substrate101may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present disclosure.

In one embodiment, substrate101includes one or more metallization interconnect layers for integrated circuits. In at least some embodiments, the substrate101includes interconnects, for example, vias, configured to connect the metallization layers. In at least some embodiments, the substrate101includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of the electronic device manufacturing. In one embodiment, the substrate101includes one or more layers above substrate101to confine lattice dislocations and defects.

Insulating layer102can be any material suitable to insulate adjacent devices and prevent leakage. In one embodiment, electrically insulating layer102is an oxide layer, e.g., silicon dioxide, or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer102comprises an interlayer dielectric (ILD). In one embodiment, insulating layer102is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), e.g., carbon doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination thereof.

In one embodiment, insulating layer102includes a dielectric material having a k-value less than 5. In one embodiment, insulating layer102includes a dielectric material having a k-value less than 2. In at least some embodiments, insulating layer102includes oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof, other electrically insulating layer determined by an electronic device design, or any combination thereof. In at least some embodiments, insulating layer102may include polyimide, epoxy, photodefinable materials, such as benzocyclobutene (BCB), and WPR-series materials, or spin-on-glass.

In one embodiment, insulating layer102is a low-k interlayer dielectric to isolate one metal line from other metal lines on substrate101. In one embodiment, the thickness of the insulating layer102is in an approximate range from about 10 nanometers (nm) to about 2 microns (μm).

In an embodiment, insulating layer102is deposited using one of deposition techniques, such as but not limited to a chemical vapor deposition (“CVD”), a physical vapor deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), spin-on, or other insulating deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, the lower metallization layer Mx comprising conductive lines103(i.e., metal lines) is a part of a back end metallization of the electronic device. In one embodiment, the insulating layer102is patterned and etched using a hard mask to form trenches104using one or more patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the size of trenches104in the insulating layer102is determined by the size of conductive lines formed later on in a process.

In one embodiment, forming the conductive lines103involves filling the trenches104with a layer of conductive material. In one embodiment, a base layer (not shown) is first deposited on the internal sidewalls and bottom of the trenches104, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper (Cu), and the conductive barrier layer can include aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper or cobalt, into the insulating layer102. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

In one embodiment, to form the base layer, the conductive barrier layer is deposited onto the sidewalls and bottom of the trenches104, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited onto the sidewalls and bottom of the trenches104. Each of the conductive barrier layer and seed layer may be deposited using any thin film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a “self-forming barrier”.

In one embodiment, the conductive layer e.g., copper or cobalt, is deposited onto the seed layer of base layer of copper, by an electroplating process. In one embodiment, the conductive layer is deposited into the trenches104using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer in the trenches104using a selective deposition technique, such as but not limited to electroplating, electrolysis, CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, the choice of a material for conductive layer for the conductive lines103determines the choice of a material for the seed layer. For example, if the material for the conductive lines103includes copper, the material for the seed layer also includes copper. In one embodiment, the conductive lines103include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pd), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

In one embodiment, portions of the conductive layer and the base layer are removed to even out top portions of the conductive lines103with top portions of the insulating layer102using a chemical-mechanical polishing (“CMP”) technique known to one of ordinary skill in the art of microelectronic device manufacturing. Chemical mechanical polishing (CMP) is a sacrificial-resist etch-back process, which can rapidly remove a layer of film using a buffing wheel in connection with an abrasive slurry and a chemical etchant.

In one non-limiting example, the thickness (as measured along the z-axis ofFIGS. 1A-1C) of the conductive lines103is in an approximate range from about 15 nm to about 1000 nm. In one non-limiting example, the thickness of the conductive lines103is from about 20 nm to about 200 nm. In one non-limiting example, the width (as measured along the y-axis ofFIGS. 1A-1C) of the conductive lines103is in an approximate range from about 5 nm to about 500 nm. In one non-limiting example, the spacing (pitch) between the conductive lines103is from about 2 nm to about 500 nm. In more specific non-limiting example, the spacing (pitch) between the conductive lines103is from about 5 nm to about 50 nm.

In an embodiment, the lower metallization layer Mx is configured to connect to other metallization layers (not shown). In an embodiment, the metallization layer Mx is configured to provide electrical contact to electronic devices, e.g., transistor, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of electronic device manufacturing.

In one or more embodiments, the conductive lines103comprise one or more of copper or cobalt. In one or more embodiment, the conductive lines103comprise copper. In one or more embodiment, the conductive lines103comprise cobalt.

FIG. 2Ais a view200similar to cross-sectional view100ofFIG. 1A, after the conductive lines103are recessed according to one embodiment.FIG. 2Bis a top view210of the electronic device depicted inFIG. 2A, andFIG. 2Cis a perspective view220of the electronic device depicted inFIG. 2A. The conductive lines103are recessed to a predetermined depth to form recessed conductive lines201. As shown inFIGS. 2A-2C, trenches205are formed in the insulating layer102. Each trench205has sidewalls204that are portions of insulating layer102and a bottom that is a top surface203of the recessed conductive lines201.

In one embodiment, the depth of the trenches205is from about 10 nm to about 500 nm. In one embodiment, the depth of the trenches205is from about 10% to about 100% of the thickness of the recessed conductive lines201. In one embodiment, the conductive lines103are recessed using one or more of wet etching, dry etching, or a combination thereof techniques known to one of ordinary skill in the art of electronic device manufacturing.

FIG. 3Ais a view300similar toFIG. 2A, after a liner301is deposited on the recessed conductive lines201according to one embodiment. In some embodiments, the liner301is deposited on the sidewalls204of the trenches205and on the top surface203of the recessed conductive lines201.

In one embodiment, liner301is deposited to protect the recessed conductive lines201from changing properties later on in a process (e.g., during tungsten deposition, or other processes). In one embodiment, liner301is a conductive liner. In another embodiment, liner301is a non-conductive liner. In one embodiment, liner301includes titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), or any combination thereof. In one or more embodiment, the liner may further comprise one or more of ruthenium (Ru) or cobalt (Co). Tantalum nitride (TaN) is a copper barrier at film thicknesses greater than 10 Å, where the film is continuous. While tantalum nitride (TaN) can be conductive, TaN may be useful as a dielectric liner material when incorporated in sufficiently small amounts. In an embodiment, the liner301is deposited to the thickness from about 0.5 nm to about 10 nm.

In an embodiment, the liner301is deposited using an atomic layer deposition (ALD) technique. In one embodiment, the liner301is deposited using one of deposition techniques, such as but not limited to a CVD, PVD, MBE, MOCVD, spin-on, or other liner deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the liner301may be selectively removed using one or more of the dry and wet etching techniques described herein.

FIG. 4Ais a view400similar toFIG. 3A, after a gapfill layer401is deposited on the liner301on the recessed conductive lines201.FIG. 4Bis a top view410of the electronic device depicted inFIG. 4A, andFIG. 4Cis a perspective view420of the electronic device depicted inFIG. 4A. As shown inFIGS. 4A-4C, gapfill layer401is deposited on the liner301. In one embodiment, gapfill layer401is a tungsten (W) layer, or other gapfill layer to provide selective growth pillars. In some embodiments, gapfill layer401is a metal film or a metal containing film. Suitable metal films include, but are not limited to, films including one or more of cobalt (Co), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), lanthanum (La), or any combination thereof. In some embodiments, seed gapfill layer401comprises is a tungsten (W) seed gapfill layer.

In one embodiment, the gapfill layer401is deposited using one of deposition techniques, such as but not limited to an ALD, a CVD, PVD, MBE, MOCVD, spin-on or other liner deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In some embodiments, deposition of the gapfill layer401includes formation of a seed gapfill layer (not shown). As will be understood by the skilled artisan, a seed gapfill layer is a relatively thin layer of material that can increase the nucleation rate (i.e., growth rate) of the gapfill layer401. In some embodiments, the seed gapfill layer is the same material as the gapfill layer401deposited by a different technique. In some embodiments, the seed gapfill layer is a different material than the gapfill layer401.

The formation of the gapfill layer401may be described as using a bulk deposition of the gapfill material to form an overburden (not illustrate) on the top of the substrate followed by planarization to remove the overburden. In some embodiments, the gapfill layer401is formed by a selective deposition process that forms substantially no (e.g., <5% area) overburden on the insulating layer102.

Portions of the seed gapfill layer401may then be removed to expose top portions of the insulating layer102according to one embodiment, and as illustrated inFIGS. 4A-4C. In one embodiment, the portions of the seed gapfill layer401are removed using one of the chemical-mechanical planarization (CMP) techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 5Ais a view500similar toFIG. 4A, after self-aligned selective growth pillars501are formed using the seed gapfill layer401according to one embodiment.FIG. 5Bis a top view510of the electronic device depicted inFIG. 5A, andFIG. 5Cis a perspective view520of the electronic device depicted inFIG. 5A. As shown inFIGS. 5A-5C, an array of the self-aligned selective growth pillars501has the same pattern as the set of the recessed conductive lines201. As shown inFIGS. 5A-5C, the pillars501extend substantially orthogonally from the top surfaces of the liner301on the recessed conductive lines201. As shown inFIGS. 5A-5C, the pillars501extend along the same direction as the recessed conductive lines201. As shown inFIGS. 5A-5C, the pillars are separated by gaps502.

Referring toFIGS. 5A-5C, in one embodiment, the pillars501are selectively grown from the gapfill layer401on the liner301on the recessed conductive lines201. In one embodiment, portions of the gapfill layer401above the liner301are expanded for example, by oxidation, nitridation, or other process to grow pillars501. In one or more embodiment, the gapfill layer401is a metal film, and the metal film is used to grow at least one pillar501by one or more of oxidation, nitridation, or other process. In one embodiment, the gapfill layer401is oxidized by exposure to an oxidizing agent or oxidizing conditions to transform the metal or metal containing gapfill layer401to metal oxide pillars501. In one embodiment, pillars501include an oxide of one or more metals listed above. In more specific embodiment, pillars501include tungsten oxide (e.g., WO, WO3and other tungsten oxide).

In one embodiment, the pillars501are formed by oxidation of the seed gapfill layer at any suitable temperature depending on, for example, the composition of the seed gapfill layer and the oxidizing agent. In some embodiments, the oxidation occurs at a temperature in an approximate range of about 25° C. to about 800° C. In some embodiments, the oxidation occurs at a temperature greater than or equal to about 150° C.

In one embodiment, the height of the pillars501is in an approximate range from about 5 angstroms (Å) to about 10 microns (μm).

FIG. 6Ais a view600similar toFIG. 5A, and, after an insulating layer601is deposited to overfill the gaps502between the pillars5401according to one embodiment.FIG. 6Bis a top view610of the electronic device depicted inFIG. 6A, andFIG. 6Cis a perspective view620of the electronic device depicted inFIG. 6A. As shown inFIGS. 6A-6C, insulating layer601is deposited on and around the pillars501and through the gaps502on the portions of the insulating layer102between the pillars501.

In one embodiment, insulating layer601is a low-k gapfill layer. In one embodiment, insulating layer601is a flowable silicon oxide (FSiOx) layer. In at least some embodiments, insulating layer601is an oxide layer, e.g., silicon dioxide (SiO2), or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer601is an interlayer dielectric (ILD). In one embodiment, insulating layer601is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, a carbon based material, e.g., a porous carbon film, carbon doped oxide (“CDO”), e.g. carbon doped silicon dioxide, porous silicon dioxide, porous silicon oxide carbide hydride (SiOCH), silicon nitride, or any combination thereof. In one embodiment, insulating layer601is a dielectric material having k-value less than 3. In more specific embodiment, insulating layer601is a dielectric material having k-value in an approximate range from about 2.2 to about 2.7. In one embodiment, insulating layer601includes a dielectric material having k-value less than 2. In one embodiment, insulating layer601represents one of the insulating layers described above with respect to insulating layer102.

In one embodiment, insulating layer601is a low-k interlayer dielectric to isolate one metal line from other metal lines. In one embodiment, insulating layer601is deposited using one of deposition techniques, such as but not limited to a CVD, spin-on, an ALD, PVD. MBE, MOCVD, or other low-k insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 7Ais a view700similar toFIG. 6Aafter at least one self-aligned selectively grown pillars501is selectively removed to form opening701according to one embodiment.FIG. 7Bis a top view710of the electronic device depicted inFIG. 7A. As shown inFIGS. 7A-7B, the pillars501are removed selectively to the insulating layer601, insulating layer102, and recessed conductive lines201. In another embodiment, when liner301is a conductive liner, liner301remains in place, and at least one pillar501is removed selectively to the insulating layer601, insulating layer102, and liner301. As shown inFIGS. 7A-7B, opening701is formed in the insulating layers601and102. Opening701extends along the same axis as the recessed conductive lines201. As shown inFIGS. 7A-7B, each opening701has a bottom that is a top surface203of recessed conductive lines201. The bottom of the opening701is the top surface of liner301. Generally, the aspect ratio of the trench refers to the ratio of the depth of the trench to the width of the opening. In one embodiment, the aspect ratio of each opening701is in an approximate range from about 1:1 to about 200:1.

In one embodiment, the pillars501are selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the pillars501are selectively wet etched by e.g., 5 wt. % of ammonium hydroxide (NH4OH) aqueous solution at the temperature of about 80° C. In one embodiment, hydrogen peroxide (H2O2) is added to the 5 wt. % NH4OH aqueous solution to increase the etching rate of the pillars501. In one embodiment, the pillars501are selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO3) in a ratio of 1:1. In one embodiment, the pillars501are selectively wet etched using HF and HNO3in a ratio of 3:7 respectively. In one embodiment, the pillars501are selectively wet etched using HF and HNO3in a ratio of 4:1, respectively. In one embodiment, the pillars501are selectively wet etched using HF and HNO3in a ratio of 30%:70%, respectively. In one embodiment, the pillars501including tungsten (W), titanium (Ti), or both titanium and tungsten are selectively wet etched using NH4OH and H2O2in a ratio of 1:2, respectively. In one embodiment, the pillars501are selectively wet etched using 305 grams of potassium ferricyanide (K3Fe(CN)6), 44.5 grams of sodium hydroxide (NaOH) and 1000 ml of water (H2O). In one embodiment, the pillars501are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), nitric acid (HNO3), sulfuric acid (H2SO4), hydrogen fluoride (HF), and hydrogen peroxide (H2O2). In one or more embodiments, the pillars501are selectively etched using a solution of HF and HNO3, a solution of NH4OH and H2O2, WCl5, WF6, niobium fluoride (NbF5), chlorine with a hydrocarbon. In one or more embodiment, the hydrocarbon can be a monocarbon (e.g. CH4) or multicarbon-based hydrocarbon. In one embodiment, the pillars501are selectively wet etched using HF, HNO3, and acetic acid (CH3COOH) in a ratio of 4:4:3, respectively. In one embodiment, the pillars501are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment, the pillars501are selectively dry etched using chlorine-, fluorine-, bromine-, or any combination thereof, based chemistries. In one embodiment, the pillars501are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO3in a ratio of 3:1, respectively. In one embodiment, the pillars501are selectively etched using alkali with oxidizers (potassium nitrate (KNO3) and lead dioxide (PbO2)).

FIGS. 7A-7Bshow views of an embodiment in which at least one of the pillars501is removed and at least one of the pillars501remains. The skilled artisan will recognize that selective removal of some of the pillars can be effected by any suitable technique including, but not limited to, masking and lithography.

In one or more embodiment, the removal of liner301is selective, and recessed conductive lines201are not affected. Without intending to be bound by theory, it is thought that the wet etch process of one or more embodiment to remove liner301using a base and hydrogen peroxide is selective to copper. As recognized by one of skill in the art, it is not trivial to remove Ta, TaN, and copper separately. Once Ta, TaN, and copper are present together, as in the liner301and recessed conductive lines201of one or more embodiment, selective etch of Ta and TaN is extremely difficult, and the copper will also etch/be removed at the same time.

Referring toFIGS. 8A-8B, in one or more embodiment, liner301is removed from the recessed conductive lines201using one or more of a base or hydrogen peroxide. In one or more embodiment, a base is used in a concentration range of about 0.1 N to about 20 N. In one or more embodiment, both the base and hydrogen peroxide are used to remove liner301. When both a base and hydrogen peroxide are used to remove the liner301, they may be used in a ratio of base to hydrogen peroxide of about 1:2 to about 5:1, including a ratio of base to hydrogen peroxide of about 1:1. Without intending to be bound by theory, it is thought that by keeping the amount of hydrogen peroxide low, the damage to the insulating layer (e.g. ultra-low k) is minimized. In one or more embodiment, removal of the liner301occurs at a temperature in the range of about 25° C. to about 90° C., including a range of about 30° C. to about 85° C., about 35° C. to about 80° C., about 25° C. to about 85° C., about 25° C. to about 75° C., about 25° C. to about 70° C., about 25° C. to about 65° C., about 25° C. to about 65° C., about 25° C. to about 60° C., and about 40° C. to about 90° C. In one or more embodiments, removal of the liner301occurs at a temperature in the range of about 25° C. to about 400° C.

In one or more embodiments, the removal of the liner301requires heating the base (e.g. sodium hydroxide) to a temperature in the range of about 25° C. to about 90° C., then adding hydrogen peroxide. In one or more embodiments, the base may be selected from one or more of sodium hydroxide, potassium hydroxide, aluminum hydroxide, lithium hydroxide, rubidium hydroxide, cesium hydroxide, ammonium hydroxide, pyridine, trimethylamine (TMA), trimethylamine (TEA), tetramethylammonium hydroxide (TMAH), or the like. The hydrogen peroxide is added just before the substrate is dipped into the solution. The ratio of base to hydrogen peroxide is critical. A slight variation in the ratio can lead to too much etching of the copper or only partial removal of the liner301.

Without intending to be bound by theory, it is thought that the liner301comprising tantalum (Ta) or tantalum nitride (TaN) reacts upon oxidation to form Ta2O5.nH2O, which subsequently reacts with sodium hydroxide (NaOH) to form sodium tantalite, NaTaO3.

FIG. 9Ais a view900similar toFIG. 8A, and, after an insulating layer901is deposited to overfill and surround the pillars501according to one embodiment.FIG. 9Bis a top view910of the electronic device depicted inFIG. 9A. As shown inFIGS. 9A-9B, insulating layer901is deposited on and around the pillars501on the portions of the insulating layer601and metallization layer with recessed conductive lines201.

In one embodiment, insulating layer901is a low-k gapfill layer. In one embodiment, insulating layer901is a flowable silicon oxide (FSiOx) layer. In at least some embodiments, insulating layer901is an oxide layer, e.g., silicon dioxide (SiO2), or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer901is an interlayer dielectric (ILD). In one embodiment, insulating layer901is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, a carbon based material, e.g., a porous carbon film, carbon doped oxide (“CDO”), e.g. carbon doped silicon dioxide, porous silicon dioxide, porous silicon oxide carbide hydride (SiOCH), silicon nitride, or any combination thereof. In one embodiment, insulating layer901is a dielectric material having k-value less than 3. In more specific embodiment, insulating layer901is a dielectric material having k-value in an approximate range from about 2.2 to about 2.7. In one embodiment, insulating layer901includes a dielectric material having k-value less than 2. In one embodiment, insulating layer901represents one of the insulating layers described above with respect to insulating layer102.

In one embodiment, insulating layer901is a low-k interlayer dielectric to isolate one metal line from other metal lines. In one embodiment, insulating layer901is deposited using one of deposition techniques, such as but not limited to a CVD, spin-on, an ALD, PVD. MBE, MOCVD, or other low-k insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

FIG. 10Ais a view1000similar toFIG. 10Aafter the substrate101is etched to form openings1001according to one embodiment.FIG. 10Bis a top view1010of the electronic device depicted inFIG. 10A. As shown inFIGS. 10A-10B, insulating layer901is removed selectively to the insulating layer601, insulating layer102, and recessed conductive lines201. As shown inFIGS. 10A-10B, openings1001are formed in the insulating layers901,601, and102. Openings1001extend along the same axis as the recessed conductive lines201. As shown inFIGS. 10A-10B, each opening1001has a bottom that is a top surface203of recessed conductive lines201. Generally, the aspect ratio of the opening refers to the ratio of the depth of the opening to the width of the opening. In one embodiment, the aspect ratio of each opening1001is in an approximate range from about 1:1 to about 200:1.

In one embodiment, the insulating layer901is selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the insulating layer901is selectively wet etched by e.g., 5 wt. % of ammonium hydroxide (NH4OH) aqueous solution at the temperature of about 80° C. In one embodiment, hydrogen peroxide (H2O2) is added to the 5 wt. % NH4OH aqueous solution to increase the etching rate of the insulating layer901. In one embodiment, the insulating layer901is selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO3) in a ratio of 1:1. In one embodiment, the insulating layer901is selectively wet etched using HF and HNO3in a ratio of 3:7 respectively. In one embodiment, the insulating layer901is selectively wet etched using HF and HNO3in a ratio of 4:1, respectively. In one embodiment, the insulating layer901is selectively wet etched using HF and HNO3in a ratio of 30%:70%, respectively.

FIG. 11Ais a view1100that is similar toFIG. 10Aafter a metal film1101is deposited in the opening1001on recessed conductive lines201.FIG. 11Bis a top view1110of the electronic device depicted inFIG. 11A. Metal film1101comprises a set of conductive lines which extend along the first direction and aligned with the set of recessed conductive lines201.

In one embodiment, forming the conductive lines1101involves filling the opening1001with a layer of conductive material. In one embodiment, a base layer (not shown) is first deposited on the internal sidewalls and bottom of the opening1001onto the recessed conductive lines201, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper (Cu), and the conductive barrier layer can include aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper or cobalt, into the insulating layer102. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

In one embodiment, to form the base layer, the conductive barrier layer is deposited onto the sidewalls and bottom of the opening1001, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited onto the sidewalls and bottom of the opening1001. Each of the conductive barrier layer and seed layer may be deposited using any think film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a “self-forming barrier”.

In one embodiment, the conductive layer e.g., copper or cobalt, is deposited onto the seed layer of base layer of copper, by an electroplating process. In one embodiment, the conductive layer is deposited into the opening1001using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer in the opening1001using a selective deposition technique, such as but not limited to electroplating, electrolysis, CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, the choice of a material for conductive layer for the conductive lines1101determines the choice of a material for the seed layer. For example, if the material for the conductive lines1101includes copper, the material for the seed layer also includes copper. In one embodiment, the conductive lines1101include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pd), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

An upper metallization layer My includes a set of conductive lines in a metal film1101that extend on portions of insulating layer901. As shown inFIG. 11A-11B, conductive lines in a metal film1101extend along Y axis122. The fully self-aligned via filled with conductive lines in a metal film1101connects the lower metallization layer Mx comprising recessed conductive lines201that extend along X axis121and the upper metallization layer My comprising conductive lines in a metal film1101. As shown inFIGS. 11A-11B, the via filled with conductive lines in a metal film1101is self-aligned along the Y axis122to recessed conductive lines201.

In one embodiment, forming the filled via with conductive lines in a metal film1101involves depositing a layer of conductive material on the top surface of insulating layer901. In one embodiment, a base layer (not shown) is first deposited on the top surface of the insulating layer901, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper, and the conductive barrier layer can include aluminum, titanium, tantalum, tantalum nitride, and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper, into the insulating layer. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

In one embodiment, to form the base layer, the conductive barrier layer is deposited on the insulating layer901, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited on the insulating layer901. Each of the conductive barrier layer and seed layer may be deposited using any thin film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a “self-forming barrier”.

In one non-limiting example, the thickness of the conductive lines in a metal film1101is in an approximate range from about 15 nm to about 1000 nm. In one non-limiting example, the thickness of the conductive lines in a metal film1101is from about 20 nm to about 200 nm. In one non-limiting example, the width of the conductive lines in a metal film1101is in an approximate range from about 5 nm to about 500 nm. In one non-limiting example, the spacing (pitch) between the conductive lines in a metal film1101is from about 2 nm to about 500 nm. In more specific non-limiting example, the spacing (pitch) between the conductive lines in a metal film1101is from about 5 nm to about 50 nm.