Semiconductor device VDMOS having a gate insulating film having a high dielectric constant portion contacting the drift region for relaxing an electric field generated in the gate insulating film

A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

TECHNICAL FIELD

The present invention relates to a semiconductor device, and more detailedly, it relates to a power device employed in the field of power electronics.

BACKGROUND ART

In general, a high withstand voltage semiconductor device (a power device) to which high voltage is applied is employed in the field of power electronics.

A vertical structure capable of easily feeding high current and capable of easily ensuring high withstand voltage and low on-resistance is known as the structure of the power device (for example, Patent Document 1).

A power device of the vertical structure includes an n+-type substrate, an n−-type epitaxial layer stacked on the substrate, p-type body regions plurally formed on a surface layer portion of the epitaxial layer at an interval, and an n+-type source region formed on a surface layer portion of each body region, for example. A gate insulating film is formed to extend between adjacent body regions, and a gate electrode is formed on the gate insulating film. The gate electrode is opposed to each body region through the gate insulating film. A source electrode is electrically connected to the source region. On the other hand, a drain electrode is formed on the back surface of the substrate. Thus, the power device of the vertical structure in which the source electrode and the drain electrode are arranged in a vertical direction perpendicular to the major surface of the substrate is constituted.

Voltage of not less than a threshold is applied to the gate electrode in a state applying voltage between the source electrode and the drain electrode (between a source and a drain), whereby channels are formed in the vicinity of interfaces between the body regions and the gate insulating film due to an electric field from the gate electrode. Thus, current flows between the source electrode and the drain electrode, and the power device enters an ON-state.

PRIOR ART

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In a conventional vertical structure, however, it is difficult to manufacture a device excellent in withstand voltage with a high yield. In practice, there are cases where many products cannot satisfy withstand voltage standards as conforming articles but are determined as defectives when a high temperature reverse bias (HTRB) test which is one of quality assurance tests is conducted.

More specifically, there are extremely many cases where a spot on a portion of a gate insulating film between adjacent body regions dielectrically breaks down when voltage is continuously applied between a source and a drain in an HTRB test.

An object of the present invention is to provide a semiconductor device excellent in withstand voltage characteristics and manufacturable with a high yield.

Solutions to Problems

A semiconductor device according to the present invention for attaining the aforementioned object includes a semiconductor layer of a first conductivity type, body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval, a source region of the first conductivity type formed on a surface layer portion of each body region, a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other, a gate electrode provided on the gate insulating film and opposed to the body regions, and a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film.

In order to attain the aforementioned object, the inventors have deeply studied the factor of dielectric breakdown of a gate insulating film in a high temperature reverse bias (HTRB) test or in practical use. They have found that the factor is field concentration on the gate insulating film. The HTRB test is a test for confirming withstand voltage of a device by continuously applying voltage approximate to the withstand voltage of the device between a source and a drain under a high temperature in a state where the device is off.

More specifically, when voltage (about 900 V in the HTRB test, for example) rendering a semiconductor layer positive is applied between a source region and the semiconductor layer functioning as a drain (between a source and a drain) in a state where a semiconductor device is off (i.e., a state where gate voltage is 0 V), an electric field is applied to a gate insulating film interposed between a gate electrode and the semiconductor layer. The electric field results from potential difference between the gate electrode and the semiconductor layer. Equipotential surfaces of extremely high potential with reference (0 V) to the gate electrode are distributed between adjacent body regions in the semiconductor layer and the interval between the equipotential surfaces is small, whereby an extremely large electric field is generated. It is such a mechanism that, when the voltage approximate to the withstand voltage of the device is continuously applied between the source and the drain, therefore, a spot on a portion of the gate insulating film between the adjacent body regions cannot withstand the field concentration of the magnitude, but causes dielectric breakdown.

According to the inventive semiconductor device, on the other hand, the field relaxation portion relaxing the electric field generated in the gate insulating film is provided between the adjacent body regions in such a vertical structure that the source region and a region of the semiconductor layer functionable as the drain are arranged in the vertical direction through the body regions. Even if voltage approximate to the withstand voltage is continuously applied between the source and the drain, therefore, dielectric breakdown of the gate insulating film can be suppressed. According to the inventive structure, therefore, a semiconductor device excellent in withstand voltage can be manufactured with a high yield.

The inventors have further investigated a spot where dielectric breakdown is particularly easily caused in a gate insulating film every array pattern (cell layout) of body regions in a semiconductor device, to find the following common feature as to a specific array pattern:

More specifically, they have found that, when noting three body regions among a plurality of body regions arrayed in various patterns and assuming a plurality of straight lines extending between the respective ones of adjacent body regions, dielectric breakdown of a gate insulating film is particularly easily caused around the intersection point between two straight lines included in the straight lines.

When noting three of the body regions and assuming a plurality of straight lines extending between the respective ones of the body regions adjacent to each other, therefore, the field relaxation portion preferably includes a dotlike field relaxation portion provided on the intersection point between two straight lines included in the straight lines. When the field relaxation portion (the dotlike field relaxation portion) is provided on the intersection point between two straight lines included in the plurality of straight lines extending between the respective ones of the adjacent body regions, dielectric breakdown of the gate insulating film around the intersection point can be effectively suppressed.

The field relaxation portion may include a linear field relaxation portion provided on a portion along the straight lines extending between the respective ones of the three body regions arranged on the positions of the respective apexes of a triangle.

Thus, even if an electric field generated along the straight lines extending between the respective ones of the adjacent body regions acts on the gate insulating film, the electric field can be relaxed in the linear field relaxation portion. Consequently, the electric field generated in the gate insulating film can be uniformly relaxed.

The dotlike field relaxation portion may have a sectional area greater than the sectional area of the linear field relaxation portion in an orthogonal direction orthogonal to the straight lines extending between the respective ones of the adjacent body regions, and the dotlike field relaxation portion may overlap with the body regions in plan view. Further, the dotlike field relaxation portion may be in the form of a square in plan view.

The linear field relaxation portion may be formed integrally with the dotlike field relaxation portion, or may be formed to separate from the dotlike field relaxation portion.

When four body regions are arrayed in the form of a matrix of two rows and two columns in plan view, the dotlike field relaxation portion is preferably provided on a position overlapping with a region where a line region extending between the respective ones of the body regions in the form of the matrix in a row direction and a line region extending between the respective ones in a column direction intersect with each other in plan view.

When the four body regions are arrayed in the form of the matrix of two rows and two columns, dielectric breakdown of the gate insulating film is particularly easily caused around the region (an intersectional region) where the line regions extending between the respective ones of the body regions in the row direction and in the column direction respectively intersect with each other.

When the dotlike field relaxation portion is provided on the position overlapping with the region where the line regions extending in the row direction and in the column direction respectively intersect with each other in plan view, therefore, dielectric breakdown of the gate insulating film around the intersectional region can be effectively suppressed.

When the body regions are elongationally formed and arrayed along the width direction orthogonal to the longitudinal direction thereof, the field relaxation portion is preferably provided on a position overlapping with a longitudinal end portion of a line region extending between the adjacent body regions along the longitudinal direction in plan view.

When the body regions are elongationally formed and arrayed along the width direction orthogonal to the longitudinal direction thereof, dielectric breakdown of the gate insulating film is particularly easily caused around the longitudinal end portion of the line region extending between the adjacent body regions along the longitudinal direction. When the field relaxation portion is provided on the position overlapping with the longitudinal end portion of the line region extending between the adjacent body regions along the longitudinal direction in plan view, therefore, dielectric breakdown of the gate insulating film around the end portion can be effectively suppressed.

In the case where the body regions are elongationally formed, further, the field relaxation portion is preferably further provided also on a portion along the line region extending between the adjacent body regions along the longitudinal direction.

The plane area of the field relaxation portion may be smaller than the plane area of the body regions.

A field relaxation portion may include an implantation region formed by implanting a second conductivity type impurity between the body regions adjacent to each other on the semiconductor layer.

A depletion layer resulting from junction (p-n junction) between the implantation region and the semiconductor layer can be formed between the adjacent body regions on the semiconductor layer by forming the implantation region of the second conductivity type different from the conductivity type of the semiconductor layer. Equipotential surfaces of high potential with reference to the gate electrode can be separated from the gate insulating film, due to the presence of the depletion layer. Consequently, the electric field applied to the gate insulating film can be reduced, whereby dielectric breakdown can be suppressed.

The implantation region may be formed by implanting Al or B as the second conductivity type impurity.

The implantation region may be increased in resistance due to the implantation of the second conductivity type impurity into the semiconductor layer, and in this case, the same may be increased in resistance due to implantation of Al, B, Ar or V.

In a case where the gate insulating film has a relatively thin thin-film portion opposed to the body regions and a relatively thick thick-film portion opposed to a portion of the semiconductor layer located between the body regions, the field relaxation layer may include the thick-film portion as the field relaxation portion.

In the gate insulating film, the portion opposed to the portion of the semiconductor layer located between the body regions is so increased in thickness that dielectric breakdown withstand voltage of the portion (the thick-film portion) can be rendered greater than that of the remaining portion. Even if the electric field is applied to the thick-film portion, therefore, the thick-film portion does not dielectrically break down, but can relax the applied electric field therein. On the other hand, the portion opposed to the body regions is the thin-film portion in the gate insulating film, whereby an electric field generated by applying voltage to the gate electrode for forming channels in the body regions can be inhibited from weakening in the gate insulating film. Therefore, the withstand voltage can be improved while suppressing reduction of a transistor function of the semiconductor device.

In a case where the gate electrode has a through-hole in a portion opposed to the portion of the semiconductor layer located between the body regions and an interlayer dielectric film formed on the semiconductor layer to cover the gate electrode and having an embedded portion embedded in the through-hole is formed, the field relaxation layer may include the embedded portion of the interlayer dielectric film as the field relaxation portion.

Thus, it follows that the portion of the gate insulating film opposed to the portion of the semiconductor layer located between the body regions is interposed between the semiconductor layer and the insulating embedded portion. Even if an electric field results from the potential difference between the gate electrode and the semiconductor layer, therefore, the electric field can be rendered hardly applicable to the portion of the gate insulating film opposed to the portion located between the adjacent body regions. Consequently, a total electric field applied to the portion of the gate insulating film can be relaxed.

In a case where the gate insulating film has a low dielectric constant portion opposed to the body regions and a high dielectric constant portion opposed to the portion of the semiconductor layer located between the body regions, the field relaxation layer may include the high dielectric constant portion as the field relaxation portion.

The portion of the gate insulating film opposed to the portion of the semiconductor layer located between the body regions is so brought into the high dielectric constant portion that dielectric breakdown withstand voltage of the portion (the high dielectric constant portion) can be rendered greater than that of the remaining portion. Even if an electric field is applied to the high dielectric constant portion, therefore, the high dielectric constant portion does not dielectrically break down, but can relax the applied electric field therein. On the other hand, the portion of the gate insulating film opposed to the body regions is the low dielectric constant portion, whereby an electric field generated by applying voltage to the gate electrode for forming channels in the body regions can be inhibited from weakening in the gate insulating film. Therefore, the withstand voltage can be improved while suppressing reduction of the transistor function of the semiconductor device.

In a case where the semiconductor layer has a protrusion formed by raising the surface thereof between the body regions, the field relaxation layer may include the protrusion as the field relaxation portion.

The protrusion is so provided between the adjacent body regions that the distance from the back surface of the semiconductor layer up to the gate insulating film lengthens by the quantity of projection of the protrusion between the body regions. As compared with a case where no protrusion is provided, therefore, the semiconductor layer can sufficiently drop voltage applied to the gate insulation film. Therefore, voltage of equipotential surfaces distributed immediately under the gate insulating film between the body regions can be reduced. Consequently, the electric field applied to the gate insulating film can be relaxed.

The impurity of the second conductivity type is preferably implanted into the protrusion.

Thus, a depletion layer resulting from junction (p-n junction) between the protrusion and the remaining portion of the semiconductor layer can be formed between the body regions. Equipotential surfaces of high potential with reference to the gate electrode can be separated from the gate insulating film, due to the presence of the depletion layer. Consequently, the electric field applied to the gate insulating film can be further reduced.

In the case where the gate insulating film has the low dielectric constant portion and the high dielectric constant portion, the protrusion is preferably covered with the high dielectric constant portion, and in this case, the field relaxation portion includes both of the protrusion and the high dielectric constant portion.

According to the structure in which the protrusion is covered with the high dielectric constant portion, dielectric breakdown withstand voltage of the high dielectric constant portion can be rendered greater than that of the remaining portion of the gate insulating film. Therefore, an effect of field relaxation by the high dielectric constant portion can also be relished, in addition to an effect of field relaxation by the protrusion.

The high dielectric constant portion may be formed to cover the protrusion and to be opposed to the body regions. In that case, the low dielectric constant portion may be interposed between the body regions and a portion of the high dielectric constant portion opposed to the body regions.

In a case where the low dielectric constant portion is formed to be opposed to the body regions and to cover the protrusion, the high dielectric constant portion may be interposed between the protrusion and a portion of the low dielectric constant portion covering the protrusion.

In the case where the gate insulating film has the relatively thin thin-film portion opposed to the body regions and the relatively thick thick-film portion opposed to the implantation region in the semiconductor layer, the field relaxation portion may be constituted of the implantation region and the thick-film portion. Thus, effects of field relaxation by both of the implantation region and the thick-film portion can be relished.

In a case where the gate electrode has a through-hole in a portion opposed to the implantation region on the semiconductor layer and an interlayer dielectric film having an embedded portion embedded in the through-hole is formed on the semiconductor layer to cover the gate electrode, the field relaxation portion may be constituted of the implantation region and the embedded portion. Thus, effects of field relaxation by both of the implantation region and the embedded region can be relished.

In a case where the gate insulating film has a low dielectric constant portion opposed to the body regions and a high dielectric constant portion opposed to the implantation region on the semiconductor layer, the field relaxation portion may be constituted of the implantation region and the high dielectric constant portion. Thus, effects of field relaxation by both of the implantation region and the high dielectric constant portion can be relished.

The semiconductor layer preferably has a dielectric breakdown electric field of not less than 1 MV/cm, and is preferably made of SiC, for example. An electric field easily concentrates on the gate insulating film on the SiC semiconductor layer due to step punching on an SiC single-crystalline growth surface, and hence an effect at a time of applying the present invention is remarkable. As a semiconductor layer having a dielectric breakdown electric field of not less than 1 MV/cm, 3C—SiC (3.0 MV/cm), 6H—SiC (3.0 MV/cm), 4H—SiC (3.5 MV/cm), GaN (2.6 MV/cm), diamond (5.6 MV/cm) or the like can be listed, for example.

The body regions may be in the form of regular polygons in plan view, and may be in the form of squares in plan view, for example.

In a case where the body regions are in the form of regular hexagons in plan view, the body regions are preferably arrayed in the form of a honeycomb.

Further, the body regions may be in the form of circles in plan view.

MODES FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are now described in detail with reference to the attached drawings.

First Embodiment: Field Relaxation by Implantation Region

FIGS. 1A and 1Bare schematic plan views of a semiconductor device according to a first embodiment of the present invention, whileFIG. 1Ashows a general diagram andFIG. 1Bshows an enlarged internal diagram respectively.FIGS. 2A and 2Bare schematic sectional views of the semiconductor device according to the first embodiment of the present invention, whileFIG. 2Ashows a cutting plane along a cutting plane line IIa-IIa inFIG. 1AandFIG. 2Bshows a cutting plane along a cutting plane line IIb-IIb inFIG. 1Brespectively.

This semiconductor device1is a planar gate VDMOSFET employing SiC, and in the form of a chip square in plan view, as shown inFIG. 1A, for example. In the chip-shaped semiconductor device1, the lengths in the vertical and horizontal directions in the plane ofFIG. 1Aare about several mm respectively.

A source pad2is formed on the surface of the semiconductor device1. The source pad2is generally in the form of a square in plan view whose four corners are bent outward, and formed to cover generally the whole region of the surface of the semiconductor device1. In the source pad2, a removed region3generally square in plan view is formed around the center of one side thereof. The removed region3is a region where the source pad2is not formed.

A gate pad4is arranged on the removed region3. An interval is provided between the gate pad4and the source pad2, which are insulated from each other.

The internal structure of the semiconductor device1is now described.

The semiconductor device1includes an SiC substrate5of an n+-type (whose concentration is 1×1018to 1×1021cm−3, for example). According to the embodiment, the SiC substrate5functions as a drain of the semiconductor device1, while a surface6(upper surface) thereof is an Si plane, and a back surface7(lower surface) thereof is a C plane.

An epitaxial layer8made of SiC of an n−-type (whose concentration is 1×1015to 1×1017cm−3, for example) in a lower concentration than the SiC substrate5is stacked on the SiC substrate5. The epitaxial layer8as a semiconductor layer is formed on the SiC substrate5by the so-called epitaxial growth. The epitaxial layer8formed on the surface6which is the Si plane is grown with a major growth surface of an Si plane. Therefore, a surface9of the epitaxial layer8formed by the epitaxial growth is an Si plane, similarly to the surface6of the SiC substrate5.

An active region10arranged on a central portion of the epitaxial layer8in plan view to function as a field-effect transistor is formed on the semiconductor device1, as shown inFIG. 1A. A plurality of (in this embodiment, two) guard rings11are formed on the epitaxial layer8at an interval from the active region10, to surround the active region10.

The interval between the active region10and the guard rings11is generally constant universally over the whole periphery. The guard rings11are low-concentration regions of a p−-type (whose concentration is 1×1013to 1×1018cm−3, for example) formed by implanting a p-type impurity into the epitaxial layer8.

On the side (the Si plane side) of the surface9of the epitaxial layer8in the active region10, p-type body regions12are formed in a large number to be arrayed in the form of a matrix at a constant pitch in a row direction and a column direction. Each body region12is in the form of a square in plan view, and the lengths in the vertical and horizontal directions in the plane ofFIG. 1Bare about 7.2 μm respectively, for example. The depth of the body region12is about 0.65 μm, for example. The concentration in the body region12is about 1×1016to 1×1019cm−3, for example. On the other hand, a region of the epitaxial layer8closer to the SiC substrate5(closer to the C plane) than the body regions12is an n−-type drift region13where the state after the epitaxial growth is maintained.

On a surface layer portion of each body region12, a body contact region14is formed on a central portion thereof, and a source region15is formed to surround the body contact region14. The body contact region14is in the form of a square in plan view, and the lengths in the vertical and horizontal directions in the plane ofFIG. 1Bare about 1.6 μm respectively, for example. The depth of the body contact region14is 0.35 μm, for example.

The source region15is in the form of a square ring in plan view, and the lengths in the vertical and horizontal directions in the plane ofFIG. 1Bare about 5.7 μm respectively, for example. The depth of the source region15is about 0.25 μm, for example.

In the active region10, regions (interbody regions16held between side surfaces of adjacent body regions12) between the respective ones of the body regions12arrayed in the form of the matrix at the constant pitch are in the form of a lattice having a constant (2.8 μm, for example) width.

The interbody regions16include line regions17linearly extending in the respective ones of the row direction and the column direction along four side surfaces of each body region12and intersectional regions18where the line regions17extending in the row direction and the line regions17extending in the column direction intersect with one another. Noting body regions12arrayed in two rows and two columns in plan view, the intersectional region18is a square-shaped region surrounded by inner corners of the arrayed four body regions12and partitioned by extensions of four sides of the body regions12(a region surrounded by square broken lines inFIG. 1B.

On the interbody regions16, a latticed gate insulating film19is formed along the interbody regions16. The gate insulating film19extends over adjacent body regions12, and covers portions (peripheral edge portions of the body regions12) of the body regions12surrounding the source regions15and outer peripheral edges of the source regions15. The gate insulating film19is made of SiO2(silicon oxide), and the thickness thereof is about 400 Å and generally uniform. The gate insulating film19may be formed by an oxide film containing nitrogen, such as a silicon oxynitride film prepared by thermal oxidation employing gas containing nitrogen and oxygen, for example.

A gate electrode20is formed on the gate insulating film19. The gate electrode20is formed in a latticed manner along the latticed gate insulating film19, and opposed to the peripheral edge portion of each body region12through the gate insulating film19. The gate electrode20is made of polysilicon, and a p-type impurity is introduced thereinto in a high concentration, for example. The thickness of the gate electrode20is about 6000 Å, for example.

In the semiconductor device1, boundaries between unit cells are set at width-directional centers of the interbody regions16. In each unit cell, the lengths in the vertical and horizontal directions in the plane ofFIG. 1Bare about 10 μm respectively, for example. In each unit cell, the depth direction of the body regions12is a gate length direction, and the circumferential direction of the body regions12orthogonal to the gate length direction is a gate width direction. In each unit cell, drain current flowing toward the side of the surface9of the epitaxial layer8along four side surfaces of each body region12in the drift region13can be fed to the source region15by controlling voltage applied to the gate electrode20thereby forming annular channels in the peripheral edge portions of the body regions12of each unit cell.

A p−-type implantation region21as a field relaxation layer formed by implanting a p-type impurity into the epitaxial layer8is formed on the interbody regions16of the epitaxial layer8. The depth of the implantation region21is about 0.65 μm (shallower than the body regions12), for example. The concentration in the implantation region21is lower than the concentration in the body regions12, and 1×1013to 1×1018cm−3, for example. The implantation region21may be an i-type (intrinsic semiconductor) region whose impurity concentration is not more than 1×1016cm−3, of a region increased in resistance, for example. The concentration in the implantation region21may be higher than the concentration in the body regions12.

The implantation region21is in the form of a lattice formed over the whole areas of the interbody regions16, and integrally includes intersectional portions22formed on the intersectional regions18and linear portions23as linear field relaxation portions formed on the line regions17.

Each intersectional portion22is in the form of a square slightly larger than each intersectional region18in plan view, and the respective corners thereof enter corners of four body regions12facing the intersectional region18respectively. In a case of noting three body regions12(body regions12ato12cinFIG. 1B, for example) arranged on positions of respective apexes of a triangle among the large number of body regions12arrayed in the form of the matrix and assuming two straight lines24aand24bextending between the respective ones of the adjacent body regions12ato12c, it can be said that the intersectional region22is provided on the intersection point therebetween.

The linear portions23are in the form of straight lines of a constant width linking centers of respective sides of intersectional portions22adjacent to one another in plan view, and at intervals from side surfaces of the body regions12. The intervals are so provided between the linear portions23and the body regions12that a path of drain current flowing along four side surfaces of each body region12in an ON-state of the semiconductor device1can be ensured. Thus, increase in on-resistance can be suppressed, and an excellent transistor operation can be performed.

An interlayer dielectric film25made of SiO2is formed on the epitaxial layer8, to cover the gate electrode20. Contact holes26are formed in the interlayer dielectric film25. Central portions of the source regions15and the whole of the body contact regions14are exposed in the contact holes26.

A source electrode27is formed on the interlayer dielectric film25. The source electrode27is collectively in contact with the body contact regions14and the source regions15of all unit cells through the respective contact holes26. In other words, the source electrode27serves as a wire common to all unit cells. An interlayer dielectric film (not shown) is formed on the source electrode27, and the source electrode27is electrically connected to the source pad2(seeFIG. 1A) through the interlayer dielectric film (not shown). On the other hand, the gate pad4(seeFIG. 1A) is electrically connected to the gate electrode20through a gate wire (not shown) drawn onto the interlayer dielectric film (not shown).

The source electrode27has such a structure that a Ti/TiN layer28and an Al layer29are stacked successively from the side in contact with the epitaxial layer8.

A drain electrode30is formed on the back surface7of the SiC substrate5, to cover the whole area thereof. The drain electrode30serves as an electrode common to all unit cells. Such a multilayer structure (Ti/Ni/Au/Ag) that Ti, Ni, Au and Ag are stacked successively from the side of the SiC substrate5can be applied as the drain electrode30, for example.

FIGS. 3A to 3Kare schematic sectional views for illustrating a method of manufacturing the semiconductor device shown inFIG. 2B.

In order to manufacture the semiconductor device1, an SiC crystal is first grown on the surface6(the Si plane) of the Si substrate5by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy), for example, while introducing an n-type impurity (n (nitrogen) in this embodiment), as shown inFIG. 3A. Thus, the n−-type epitaxial layer8is formed on the SiC substrate5.

Then, a p-type impurity (Al (aluminum) in this embodiment) is implanted from the surface9of the epitaxial layer8into the epitaxial layer8by employing an SiO2mask31having openings in portions for forming the body regions12, as shown inFIG. 3B. While the implantation conditions at this time vary with the type of the p-type impurity, the dose is about 6×1013cm−2and acceleration energy is about 380 keV, for example. Thus, the body regions12are formed on the surface layer portion of the epitaxial layer8. Further, the drift region13maintaining the state after the epitaxial growth is formed on a base layer portion of the epitaxial layer8.

Then, an n-type impurity (P (phosphorus) in this embodiment) is implanted from the surface9of the epitaxial layer8into the epitaxial layer8by employing an SiO2mask32having openings in regions for forming the source regions15, as shown inFIG. 3C. While the implantation conditions at this time vary with the type of the n-type impurity, the dose is about 2.5×1015cm−2and acceleration energy is in four stages in the range of 30 keV to 160 keV, for example. Thus, the source regions15are formed on the surface layer portions of the body regions12.

Then, a p-type impurity (Al in this embodiment) is implanted from the surface9of the epitaxial layer8into the epitaxial layer8by employing an SiO2mask33having openings in regions for forming the implantation region21and the guard rings11, as shown inFIG. 3D. While the implantation conditions at this time vary with the type of the p-type impurity, the dose is about 2.7×1013cm−2and acceleration energy is about 380 keV, for example. Thus, the implantation region21and the guard rings11are simultaneously formed, and the active region10is partitioned. In a case of forming the implantation region21increased in resistance, Al, B, Ar or V may be implanted in conditions such as a dose of about 1×1013cm−2to 1×1015cm−2and acceleration energy of about 30 keV to 100 keV, for example.

Then, a p-type impurity (Al in this embodiment) is implanted from the surface9of the epitaxial layer8into the epitaxial layer8by employing an SiO2mask34having openings in regions for forming the body contact regions14, as shown inFIG. 3E. While the implantation conditions at this time vary with the type of the p-type impurity, the dose is about 3.7×1015cm−2and acceleration energy is in four stages in the range of 30 keV to 180 keV, for example. Thus, the body contact regions14are formed.

Then, the epitaxial layer8is annealed at 1400° C. to 2000° C. for 2 to 10 minutes, for example, as shown inFIG. 3F. Thus, ions of the individual n-type impurities and p-type impurities implanted into the surface layer portion of the epitaxial layer8are activated. The annealing of the epitaxial layer8can be performed by controlling a resistance heating furnace or a high-frequency induction heating furnace at a proper temperature, for example.

Then, the surface9of the epitaxial layer8is so thermally oxidized that the gate insulating film19covering the whole area of the surface9is formed, as shown inFIG. 3G.

Then, a polysilicon material35is deposited on the epitaxial layer8by CVD while introducing a p-type impurity (B (boron) in this embodiment), as shown inFIG. 3H.

Thereafter unnecessary portions (portions other than the gate electrode20) of the deposited polysilicon material35are removed by dry etching, as shown inFIG. 3I. Thus, the gate electrode20is formed.

Then, the interlayer dielectric film25made of SiO2is stacked on the epitaxial layer8by CVD, as shown inFIG. 3J.

Then, the interlayer dielectric film25and the gate insulating19are so continuously patterned that the contact holes26are formed, as shown inFIG. 3K.

Thereafter Ti, TiN and Al are successively sputtered on the interlayer dielectric film25to form the source electrode27, for example. Further, Ti, Ni, Au and Ag are successively sputtered on the back surface7of the SiC substrate5, so that the drain electrode30is formed.

Thereafter the interlayer insulating film (not shown), the source pad2, the gate pad4and the like are formed, whereby the semiconductor device1shown inFIG. 2Bis obtained.

In the semiconductor device1, annular channels are formed in the peripheral edge portions of the body regions12of each unit cell by applying drain voltage between the source pad2(the source electrode27) and the drain electrode30(between the source and the drain) and applying prescribed voltage (voltage of not more than gate threshold voltage) to the gate pad4(the gate electrode20) in a state grounding the source pad2(i.e., the source electrode27is at 0 V). Thus, current flows from the drain electrode30to the source electrode27, and each unit cell enters an ON-state.

When each unit cell is brought into an OFF-state (i.e., a state where the gate voltage is 0 V) and the voltage is kept being applied between the source and the drain, on the other hand, an electric field is applied to the gate insulating film19interposed between the gate electrode20and the epitaxial layer8. The electric field results from the potential difference between the gate electrode20and the epitaxial layer8. In the interbody regions16where the conductivity type (the n−-type) of the drift region13is kept, equipotential surfaces of extremely high potential with reference (0 V) to the gate electrode20are distributed while intervals between the equipotential surfaces are small, whereby an extremely large electric field is generated. If the drain voltage is 900 V, for example, equipotential surfaces of 900 V are distributed around the back surface7of the SiC substrate5in contact with the drain electrode30and a voltage drop is caused from the back surface7of the Si substrate5toward the surface9of the epitaxial layer8, while equipotential surfaces of about several 10 V are distributed in the interbody regions16. Therefore, an extremely large electric field directed toward the gate electrode20is generated in the interbody regions16.

In the semiconductor device1, however, the implantation region21of the reverse conductivity type (the p−-type) to the drift region13is formed over the whole areas of the interbody regions16. Therefore, depletion layers resulting from junction (p-n junction) between the implantation region21and the drift region13can be generated on the whole areas of the interbody regions16. The equipotential surfaces of high potential with reference to the gate electrode20can be lowered toward the side of SiC substrate5and separated from the gate insulating film19, due to the presence of the depletion layers. Consequently, the electric field applied to the gate insulating film19can be reduced. Therefore, dielectric breakdown of the gate insulating film19can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between the source and the drain, and further in practical use. Therefore, the semiconductor device1excellent in withstand voltage can be manufactured with a high yield.

In such a structure that the body regions12are in the form of the matrix and the interbody regions16are formed in the latticed manner, a particularly strong electric field is easily generated in the intersectional region18surrounded by the respective corners of the four body regions12arrayed in two rows and two columns. In the semiconductor device1, however, the implantation region21(the intersectional portion22) larger than the intersectional region18is formed on the intersectional region18, and the intersectional portion22enters the respective corners of the body regions12. Therefore, dielectric breakdown of portions of the gate insulating film19opposed to the intersectional regions18can be effectively suppressed. Further, the implantation region21(the linear portions23) is formed not only on the intersectional regions18but also on the line regions17, whereby dielectric breakdown of portions of the gate insulating film19opposed to the line regions17can also be effectively suppressed. As a result of these, the electric field applied to the gate insulating film19can be uniformly relaxed.

Modifications of First Embodiment

While a plurality of modifications of the semiconductor device1according to the first embodiment are now illustrated, the modifications are not restricted to these.

For example, the implantation region21may be formed only on the line regions17. Further, the implantation region21formed on the line regions17may not necessarily be linear, but may be in the form of a polygon such as a square or a triangle, for example.

In the semiconductor device1, the linear portions23of the implantation region21may not be integral with the intersectional portions22, but linear portions38of an implantation region36may be so formed that both longitudinal ends thereof separate from respective sides of intersectional portions37, as shown inFIG. 4A, for example.

In the semiconductor device1, the plane shape of the body regions12may not be square, but may be in the form of a regular hexagon, as in body regions39shown inFIG. 5A, for example.

An array pattern of the body regions39in this case is such a honeycomb pattern that the body regions39are so arrayed that single sides of adjacent body regions39are parallel to one another, for example.

Regions (interbody regions40) between the respective ones of the body regions39arrayed in the honeycomb pattern are in the form of a honeycomb having a constant width. The interbody regions40include line regions41linearly extending between the respective ones of the adjacent body regions39along six side surfaces of each body region39and intersectional regions42where three line regions41radially intersect with one another.

An implantation region43is in the form of a honeycomb formed over the whole area of the honeycomb region, for example, and integrally includes intersectional portions44(portions formed on the intersectional regions42) and linear portions45(portions formed on the line regions41).

Further, the plane shape of the body regions12arrayed in the form of the matrix may be circular, as in body regions46shown inFIG. 6, for example.

Further, the array pattern of the body regions12may not necessarily be the matrix pattern, but may be a zigzag array pattern, as shown inFIG. 7, for example. More specifically, body regions12square-shaped in plan view form a plurality of columns, and are arranged at a constant pitch in a column direction Y in each column. In two columns adjacent to each other in a row direction X orthogonal to the column direction Y, body regions12forming one of the columns and body regions12forming the other column have positional relation deviating from one another by half the pitch (half the pitch at which the body regions12are arranged in the column direction).

A region (an interbody region47) between each pair of body regions12in the zigzag array pattern integrally includes a first line region48linearly extending between two adjacent columns of body regions12along the column direction Y, a second line region49linearly extending between the respective ones of the body regions12of each column along the row direction X, and an intersectional region50where the first line region48and the second line region49intersect with each other in a T-shaped manner.

An implantation region51is formed over the whole area of the interbody region47, for example, and integrally includes an intersectional portion52(a portion formed on the intersectional region50) and a linear portion53(a portion formed on the first line region48and the second line region49).

In a case of noting three body regions12(body regions12ato12cinFIG. 7, for example) arranged on the positions of respective apexes of a triangle surrounding each T-shaped intersectional region50among the large number of body regions12arrayed in the zigzag array pattern and assuming two straight lines54aand54bextending between the adjacent body regions12aand12band the adjacent body regions12band12crespectively, it can be said that the intersectional portion52is provided on the intersection point (i.e., a point on the intersection point of a T-shaped path) between the two straight lines54aand54b.

The plane shape of the body regions12may be an elongational shape. For example, the plane shape may be oblong, as in body regions55shown inFIGS. 8A and 8B.

The oblong body regions55are arrayed at a constant pitch so that the long sides of body regions55adjacent to each other are parallel to each other, for example. In a surface layer portion of each body region55, a body contact region56is formed on a central portion thereof, and a source region57is formed to surround the body contact region56. The body contact region56has an oblong shape similar to that of the body region55in plan view. On the other hand, the source region57is in the form of a rectangular ring in plan view.

Regions (interbody regions58) between the respective ones of the body regions55arrayed in this manner are in the form of lines linearly extending between the respective ones along the longitudinal direction of the body regions55.

One implantation region59is provided every linear interbody region58, and in the form of a straight line along the longitudinal direction. Each implantation region59includes a pair of end portions60formed on both longitudinal end portions thereof and a linear portion61linking the pair of end portion regions with each other.

Each end portion60of the implantation region59is in the form of a rectangle in plan view, and two corners thereof closer to the body region55enter corners of the body region55respectively. On the other hand, the linear portion61is formed with a constant width at an interval from a side surface of the body region55.

The plane shape of the elongational body regions12may be a shape partitioned by meandering lines each formed by coupling a plurality of arcuate portions63with one another, as in body regions62shown inFIG. 9, for example. In this case, two body contact regions56may be formed on each body region62at an interval from each other in the longitudinal direction of the body regions62.

The plane shape of the elongational body regions12may be a shape partitioned by meandering lines each formed by coupling a plurality of bent portions65with one another, as in body regions64shown inFIG. 10, for example. Each bent portion65has a shape bent toward one side in the width direction at an interior angle of 120 degrees with respect to a portion extending in the longitudinal direction of the body regions64, extending in the longitudinal direction, and bent toward another side in the width direction at an interior angle of 120 degrees with respect to the portion extending in the longitudinal direction. Also in this case, two body contact regions14may be formed on each body region64at an interval from each other in the longitudinal direction of the body region64.

Second Embodiment: Field Relaxation by Partial Thickening of Gate Insulating Film

FIGS. 11A and 11Bare schematic plan views of a semiconductor device according to a second embodiment of the present invention, whileFIG. 11Ashows a general diagram andFIG. 11Bshows an enlarged internal diagram respectively.FIGS. 12A and 12Bare schematic sectional views of the semiconductor device according to the second embodiment of the present invention, whileFIG. 12Ashows a cutting plane along a cutting plane line XIIa-XIIa inFIG. 11BandFIG. 12Bshows a cutting plane along a cutting plane line XIIb-XIIb inFIG. 11Brespectively. Referring toFIGS. 11A and 11BandFIGS. 12A and 12B, portions corresponding to the respective portions shown in the aforementionedFIG. 1and the like are denoted by the same reference signs.

In a semiconductor device66according to the second embodiment, the thickness of a gate insulating film is not uniform, but the gate insulating film67integrally includes a relatively thick thick-film portion68as a field relaxation portion opposed to latticed interbody regions16and a relatively thin thin-film portion69opposed to body regions12surrounded by sides of the lattice of the interbody regions16.

The thick-film portion68is in the form of a lattice surrounding the body regions12in plan view along the interbody regions16, and integrally includes intersectional portions70opposed to intersectional regions18and linear portions71as linear field relaxation portions opposed to line regions17. The thickness of the thick-film portion68is 1000 Å to 3000 Å, for example.

Each intersectional portion70is in the form of a square slightly smaller than the intersectional region18in plan view, and respective corners thereof are opposed to corners of four body regions12facing the intersectional region18at intervals respectively. The intersectional region70may overlap with the body region12in plan view.

Each linear portion71is in the form of a straight line linking centers of respective sides of intersectional portions70adjacent to each other in plan view, and at an interval not to overlap with a peripheral edge portion of the body region12.

The thin-film portion69extends from the latticed thick-film portion68surrounding the body regions12in plan view toward the side of the body regions12with a constant width, and covers the peripheral edge portions of the body regions12and outer peripheral edges of source regions. The thickness of the thin-film portion69is 350 Å to 1000 Å, for example.

The remaining structure is similar to the case of the aforementioned first embodiment.

FIGS. 13A to 13Kare schematic sectional views for illustrating a method of manufacturing the semiconductor device shown inFIG. 12B.

In order to manufacture the semiconductor device66according to the second embodiment, steps similar to the steps shown inFIGS. 3A to 3F(on condition that no implantation region21is formed in the step shown inFIG. 3E) are carried out so that the body regions12, source regions15and body contact regions14are formed on an epitaxial layer8as shown inFIGS. 13A to 13E, for example, and impurities implanted into these regions are activated by heat treatment.

Then, a mask (not shown) having openings in regions (regions opposed to the interbody regions16) for forming the thick-film portion68is formed on a surface9of the epitaxial layer8. Thus, oxide films72are formed only on the regions for forming the thick-film portion68, as shown inFIG. 13F.

The surface9of the epitaxial layer8is thermally oxidized in the state where the oxide films72are formed, whereby the portions where the oxide films72are formed are so relatively thickened that the thick-film portion68is formed while the thin-film portion69is so formed on the remaining portions that the gate insulating film67is formed, as shown inFIG. 13G.

Thereafter steps similar to the steps shown inFIGS. 3H to 3Kare carried out as shown inFIGS. 13H to 13K, so that a gate electrode20and an interlayer dielectric film25are formed on the gate insulating film67. Thereafter a source electrode27, a drain electrode30, a source pad2and a gate pad4etc. are formed, whereby the semiconductor device66shown inFIG. 12Bis obtained.

In the semiconductor device66, annular channels are formed in the peripheral edge portions of the body regions12of each unit cell by applying drain voltage between the source pad2(the source electrode27) and the drain electrode30(between a source and a drain) and applying prescribed voltage (voltage of not less than gate threshold voltage) to the gate pad4(the gate electrode20) in a state grounding the source pad2(i.e., the source electrode27is at 0 V). Thus, current flows from the drain electrode30to the source electrode27, and each unit cell enters an ON-state.

When each unit cell is brought into an OFF-state (i.e., a state where gate voltage is 0 V) and the voltage is kept being applied between the source and the drain, on the other hand, an electric field is applied to the gate insulating film67interposed between the gate electrode20and the epitaxial layer8. The electric field results from potential difference between the gate electrode20and the epitaxial layer8. In the interbody regions16where the conductivity type (n−-type) of a drift region13is maintained, equipotential surfaces of extremely high potential with reference (0 V) to the gate electrode20are distributed and the intervals between the equipotential surfaces are small, whereby an extremely large electric field is generated. If the drain voltage is 900 V, for example, equipotential surfaces of 900 V are distributed around a back surface7of an SiC substrate5in contact with the drain electrode30and a voltage drop is caused from the back surface7of the Si substrate5toward the surface9of the epitaxial layer8, while equipotential surfaces of about several 10 V are distributed in the interbody regions16. Therefore, a large electric field directed toward the gate electrode20is generated in the interbody regions16.

In the semiconductor device66, however, the portion opposed to the interbody regions16is increased in thickness as the thick-film portion68in the gate insulating film67. Thus, dielectric breakdown voltage of the portion (the thick-film portion68) can be rendered greater than that of the remaining portion (the thin-film portion69). Even if a large electric field is applied to the thick-film portion68, therefore, the thick-film portion68does not dielectrically break down, but can relax the applied electric field therein. Therefore, dielectric breakdown of the gate insulating film19can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between the source and the drain and further in practical use. Therefore, the semiconductor device66excellent in withstand voltage can be manufactured with a high yield.

Further, the thick-film portion68(the intersectional portions70) is formed on the portion opposed to the intersectional regions18where a particularly strong electric field is easily generated. Therefore, dielectric breakdown of the portion of the gate insulating film67opposed to the intersectional regions18can be effectively suppressed. In addition, the thick-film portion68(the linear portions71) is formed not only on the portion opposed to the intersectional regions18but also on a portion opposed to the line regions17, whereby dielectric breakdown of the portion of the gate insulating film67opposed to the line regions17can also be effectively suppressed. Consequently, the electric field applied to the gate insulating film67can be uniformly relaxed.

On the other hand, a portion of the gate insulating film67opposed to the peripheral edge portions of the body regions12is the thin-film portion69, whereby the electric field generated by applying the voltage to the gate electrode20in order to form the channels in the peripheral edge portions of the body regions12can be inhibited from weakening in the gate insulating film67. Therefore, reduction of a transistor function of the semiconductor device66can be suppressed.

Modifications of Second Embodiment

While a plurality of modifications of the semiconductor device66according to the second embodiment are illustrated, modifications are not restricted to these.

Also in the semiconductor device66, the plane shape of the body regions12and the array pattern of the body regions12can be properly changed. While illustration is omitted, the plane shape of the body regions12may be in the form of a regular hexagon, a circle or an oblong, for example. Further, the array pattern of the body regions12may be a honeycomb pattern, a zigzag array pattern or the like.

While the thick-film portion68has been formed by CVD by depositing an insulating material only on the interbody regions16after thermally oxidizing the surface9of the epitaxial layer8in the above description, the thick-film portion68can also be formed by forming an insulating film on the whole area of the surface9of the epitaxial layer8by thermal oxidation so that the film thickness is greater than a normal one and thereafter etching only the portion (the region for forming the thin-film portion69) other than the region for forming the thick-film portion68, for example.

The thick-film portion68can also be formed by rendering the impurity concentration in the interbody regions16of the epitaxial layer8greater than the concentration in the remaining portion and increasing only the rate of oxidation in the interbody regions16. Thus, only the insulating film on the interbody regions16can be rapidly grown to be increased in thickness while the remaining portion can be slowly grown to be reduced in thickness, whereby the thick-film portion68and the thin-film portion69can be formed through only one thermal oxidation step.

Third Embodiment: Field Relaxation by Partial Removal of Gate Electrode

FIGS. 14A and 14Bare schematic plan views of a semiconductor device according to a third embodiment of the present invention, whileFIG. 14Ashows a general diagram andFIG. 14Bshows an enlarged internal diagram respectively.FIGS. 15A and 15Bare schematic sectional views of the semiconductor device according to the third embodiment of the present invention, whileFIG. 15Ashows a cutting plane line along a cutting plane line XVa-XVa inFIG. 14BandFIG. 15Bshows a cutting plane along a cutting plane line XVb-XVb inFIG. 14Brespectively. Referring toFIGS. 14A and 14BandFIGS. 15A and 15B, portions corresponding to the respective portions shown in the aforementionedFIG. 1and the like are denoted by the same reference signs.

In a semiconductor device73according to the third embodiment, a large number of through-holes74are formed in a gate electrode20by removing portions of the gate electrode20opposed to respective intersectional regions18of interbody regions16.

More specifically, each through-hole74is in the form of a square having sides smaller than the width of the gate electrode20on each intersectional portion of the latticed gate electrode20having a constant width in plan view. The lattice of the gate electrode20can be rendered continuous without cutting the same around the through-hole74by reducing each side of the through-hole74below the width of the gate electrode20.

In a case of noting three body regions12(body regions12ato12cinFIG. 14B, for example) arranged on the positions of respective apexes of a triangle among a large number of body regions12arrayed in the form of a matrix and assuming three straight lines24ato24cextending between the respective ones of the adjacent body regions12ato12c, it can be said that the through-hole74is provided on the intersection point between the two straight lines24aand24b(may be the intersection point between24aand24cor the intersection point between24band24c) among these straight lines.

An interlayer dielectric film25covering the gate electrode20enters each through-hole74as an embedded portion75. It follows that the embedded portion75is opposed to an intersectional region18of an interbody region16through a gate insulating film19.

The remaining structure is similar to the case of the aforementioned first embodiment.

FIGS. 16A to 16Kare schematic sectional views for illustrating a method of manufacturing the semiconductor device shown inFIG. 15B.

In order to manufacture the semiconductor device73according to the third embodiment, steps similar to the steps shown inFIGS. 3A to 3G(on condition that no implantation region21is formed in the step shown inFIG. 3E) are carried out so that the body regions12, source regions15and body contact regions14are formed on an epitaxial layer8as shown inFIGS. 16A to 16F, for example, and impurities implanted into these regions are activated by heat treatment so that the gate insulating film19is formed.

Then, a resist pattern76having openings in regions for forming the gate electrode20is formed, as shown inFIG. 16G. At this time, regions for forming the through-holes74are covered with the resist pattern76.

Then, a polysilicon material77is deposited from above the epitaxial layer8by CVD while introducing a p-type impurity (B (boron) in this embodiment), as shown inFIG. 16H.

Then, the resist pattern76is so removed that unnecessary portions (portions other than the gate electrode20) of the polysilicon material77are lifted off along with the resist pattern76, as shown inFIG. 16I. Thus, the gate electrode20having the through-holes74is formed.

Then, an interlayer dielectric film25made of SiO2is formed on the epitaxial layer8by CVD, as shown inFIG. 16J. The interlayer dielectric film25is partially embedded in the through-holes74of the gate electrode20.

Then, the interlayer dielectric film25and the gate insulating film19are so continuously patterned that contact holes26are formed, as shown inFIG. 16K.

Thereafter Ti, TiN and Al are successively sputtered on the interlayer dielectric film25so that a source electrode27is formed, for example. Further, Ti, Ni, Au and Ag are successively sputtered on a back surface7of an SiC substrate5, so that a drain electrode30is formed.

Thereafter an interlayer dielectric film (not shown), a source pad2, a gate pad4etc. are formed, whereby the semiconductor device73shown inFIG. 15Bis obtained.

In the semiconductor device73, annular channels are formed in peripheral edge portions of the body regions12of each unit cell by applying drain voltage between the source pad2(the source electrode27) and the drain electrode30(between a source and a drain) and applying prescribed voltage (voltage of not less than gate threshold voltage) to the gate pad4(the gate electrode20) in a state grounding the source pad2(i.e., the source electrode27is at 0 V), similarly to the first embodiment. Thus, current flows from the drain electrode30to the source electrode27, and each unit cell enters an ON-state.

When each unit cell is brought into an OFF-state (i.e., a state where gate voltage is 0 V) and the voltage is kept being applied between the source and the drain, on the other hand, an electric field is applied to the gate insulating film19interposed between the gate electrode20and the epitaxial layer8. The electric field results from potential difference between the gate electrode20and the epitaxial layer8. In the interbody regions16where the conductivity type (n−-type) of a drift region13is maintained, equipotential surfaces of extremely high potential with reference (0 V) to the gate electrode20are distributed and the intervals between the equipotential surfaces are small, whereby an extremely large electric field is generated. If the drain voltage is 900 V, for example, equipotential surfaces of 900 V are distributed around a back surface7of an SiC substrate5in contact with the drain electrode30and a voltage drop is caused from the back surface7of the Si substrate5toward the surface9of the epitaxial layer8, while equipotential surfaces of about several 10 V are distributed in the interbody regions16. Therefore, a large electric field directed toward the gate electrode20is generated in the interbody regions16.

In the semiconductor device73, however, the through-holes74are formed in portions of the gate electrode20opposed to the respective intersectional regions18where a particularly strong electric field is easily generated, and part (embedded portion75) of the interlayer dielectric film25enters each through-hole74. Therefore, it follows that portions of the gate insulating film19opposed to the interbody regions16are interposed between the epitaxial layer8and the insulating embedded portions75. Even if an electric field results from the potential difference between the gate electrode20and the epitaxial layer8, therefore, the electric field can be rendered hardly applicable to the portions of the gate insulating film19opposed to the interbody regions16. Consequently, a total electric field applied to the portions of the gate insulating film19opposed to the interbody regions16can be relaxed. Therefore, dielectric breakdown of the gate insulating film19can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between the source and the drain and further in practical use. Therefore, the semiconductor device73excellent in withstand voltage can be manufactured with a high yield.

Modifications of Third Embodiment

While a plurality of modifications of the semiconductor device73according to the third embodiment are now illustrated, modifications are not restricted to these.

For example, the through-holes74may be formed in portions opposed to line regions. Further, the through-holes74may not necessarily be square-shaped, but may be triangular, circular or the like.

In the semiconductor device73, the plane shape of the body regions12may not be square, but may be in the form of a regular hexagon, as in body regions78shown inFIG. 17, for example.

The array pattern of the body regions78in this case is such a honeycomb pattern that the body regions78are so arrayed that single sides of adjacent body regions78are parallel to one another, for example.

Regions (interbody regions79) between the respective ones of the body regions78arrayed in the honeycomb pattern are in the form of a honeycomb having a constant width. Each interbody region79includes a line region80linearly extending between the respective ones of the adjacent body regions78along six side surfaces of each body region78and an intersectional region81where three line regions80radially intersect with one another.

In this case, through-holes74can be formed in portions of a gate electrode20opposed to the intersectional regions81of the honeycomb interbody regions79, for example.

The plane shape of body regions82may be in the form of an elongational oblong, as in the body regions82shown inFIG. 18, for example.

The oblong body regions82are arrayed at a constant pitch so that the long sides of body regions82adjacent to one another are parallel to one another, for example. In a surface layer portion of each body region82, a body contact region83is formed on a central portion thereof, and a source region84is formed to surround the body contact region83. The body contact region83is in the form of an oblong similar to the body region82in plan view. On the other hand, the source region84is in the form of a rectangular ring in plan view.

Regions (interbody regions85) between the respective ones of the body regions82arrayed in this manner are in the form of lines linearly extending between the respective ones along the longitudinal direction of the body regions82.

In this case, through-holes74are formed in the form of grooves (through-grooves86) linearly extending along the interbody regions85, by removing portions of a gate electrode20opposed to the interbody regions85, for example.

Fourth Embodiment: Field Relaxation Employing High-k Film

FIG. 19is an enlarged sectional view of a principal portion of a semiconductor device according to a fourth embodiment of the present invention, and shows a section corresponding toFIG. 2A. Referring toFIG. 19, portions corresponding to the respective portions shown in the aforementionedFIG. 1and the like are denoted by the same reference signs.

In a semiconductor device87according to the fourth embodiment, a High-k (high dielectric constant) material is employed for a portion of a gate insulating film88opposed to an interbody region16. The High-k material is an insulating material whose dielectric constant is higher than that of SiO2, and HfO2(hafnium oxide), ZrO2(zirconium oxide), HfSiO (hafnium silicate), SiON, SiN, Al2O3or AlON can be listed, for example.

The gate insulating film88has an SiO2film89as a low dielectric constant portion whose dielectric constant is relatively low and a High-k film90as a high dielectric constant portion whose dielectric constant is relatively high.

Referring toFIG. 19, the SiO2film89is formed on a surface9of an epitaxial layer8, has an opening91in a portion opposed to the interbody region16, and is opposed to peripheral edge portions of body regions12and outer peripheral edges of source regions15.

The High-k film90is stacked on the SiO2film89, and part thereof fills up the opening91of the SiO2film89. In other words, the gate insulating film88having such a two-layer structure that the SiO2film89and the High-k film90are successively stacked from the surface9of the epitaxial layer8is formed inFIG. 19.

The gate insulating film88can be formed by thermally oxidizing the surface9of the epitaxial layer8following the step shown inFIG. 3Gthereby forming the SiO2film89, then forming the opening91in the SiO2film89by etching, and thereafter stacking the High-k material by CVD, for example.

In the semiconductor device87, a portion of the gate insulating film88opposed to the interbody region16is the High-k film90. Thus, dielectric breakdown voltage of the portion (the High-k film90) in the gate insulating film88can be rendered greater than that of the remaining portion (the SiO2film89). Even if a large electric field is applied to the High-k film90, therefore, the High-k film90does not dielectrically break down, but can relax the applied electric field therein. Therefore, dielectric breakdown of the gate insulating film88can be suppressed in an HTRB test in which voltage approximate to the withstand voltage of the device is continuously applied between a source and a drain and further in practical use. Therefore, the semiconductor device87excellent in withstand voltage can be manufactured with a high yield.

Modifications of Fourth Embodiment

While a plurality of modifications of the semiconductor device87according to the fourth embodiment are now illustrated, modifications are not restricted to these.

In the semiconductor device87, a single-layer structure of an SiO2film92may be employed as a substrate of a gate insulating film88, and a High-k film93may not be stacked on the SiO2film92but may simply be embedded in an opening91of the SiO2film92, as shown inFIG. 20, for example. Thus, it follows that only the SiO2film92is opposed to peripheral edge portions of body regions12, whereby an electric field generated by applying voltage to a gate electrode20in order to form channels in the peripheral edge portions of the body regions12can be inhibited from weakening in the gate insulating film88. Therefore, reduction of a transistor function of the semiconductor device87can be suppressed.

In the semiconductor device87, the gate insulating film88may be in a structure having a High-k film95formed on a surface9of an interbody region16and an SiO2film94stacked on an epitaxial layer8to cover the High-k film95, as shown inFIG. 21.

Fifth Embodiment: Field Relaxation by Enlargement of Interbody Region

FIG. 22is an enlarged sectional view of a principal portion of a semiconductor device according to a fifth embodiment of the present invention, and shows a section corresponding toFIG. 2A. Referring toFIG. 22, portions corresponding to the respective portions shown in the aforementionedFIG. 1and the like are denoted by the same reference signs.

In a semiconductor device96according to the fifth embodiment, only an interbody region97of an epitaxial layer8is enlarged toward the side of a gate insulating film19.

More specifically, the interbody region97has a protrusion98projecting from a surface9of the epitaxial layer8to be raised with respect to the surface9of the epitaxial layer8. As the conductivity type of the protrusion98, the conductivity type (n−-type) of the epitaxial layer8is maintained.

The gate insulating film19is formed on the surface9of the epitaxial layer8to cover the protrusion98.

The protrusion98can be formed by forming the epitaxial layer8following the step shown inFIG. 3A, thereafter forming a mask (not shown) covering only a region for forming the protrusion98, and etching an unnecessary portion (a portion other than the protrusion98) of the epitaxial layer8through the mask, for example.

In the semiconductor device96, the protrusion98is so provided on the interbody region97that the distance from a back surface7of an SiC substrate5up to the gate insulating film19lengthens by the quantity of projection of the protrusion98in the interbody region97. Therefore, voltage applied to a drain electrode30can be further dropped before the same is applied to the gate insulating film19as compared with a case where no protrusion98is present. Therefore, voltage of equipotential surfaces distributed immediately under the gate insulating film19in the interbody region97can be reduced. Consequently, an electric field applied to the gate insulating film19can be relaxed.

Modifications of Fifth Embodiment

While a plurality of modifications of the semiconductor device96according to the fifth embodiment are now illustrated, modifications are not restricted to these.

In the semiconductor device96, the conductivity type of the epitaxial layer8may not necessarily be maintained as the conductivity type of the protrusion98, but a p−-type may be employed, as shown inFIG. 23, for example. Thus, a depletion layer resulting from junction (p-n junction) between the protrusion98and a drift region13can be generated in the interbody region97. Further, equipotential surfaces of potential with reference to a gate electrode20can be lowered toward the side of an SiC substrate5and separated from the gate insulating film19, due to the presence of the depletion layer. Consequently, the electric field applied to the gate insulating film19can be further reduced.

In order to form the p−-type protrusion98, the protrusion98is formed by first forming the epitaxial layer8following the step shown inFIG. 3A, thereafter forming a mask (not shown) covering only a region for forming the protrusion98and etching an unnecessary portion (a portion other than the protrusion98) of the epitaxial layer8through the mask, for example. The p−-type protrusion98can be formed by forming a sidewall on the protrusion98after the formation of the protrusion98and thereafter implanting a p-type impurity also into the protrusion98in the step shown inFIG. 3B.

In the semiconductor device96, a gate insulating film may have an SiO2film and a High-k film, similarly to the fourth embodiment.

For example, a gate insulating film99may have an SiO2film101formed on a surface9of an epitaxial layer8, having an opening100exposing a protrusion98and opposed to peripheral edge portions of body regions12and outer peripheral edges of source regions15and a High-k film102stacked on the SiO2film101and formed to cover the protrusion98exposed from the opening100of the SiO2film101, as shown inFIG. 24.

Further, a High-k film103may not be stacked on an SiO2film104, but may be formed to cover a protrusion98exposed from an opening105of the SiO2film104, as shown inFIG. 25.

In addition, a gate insulating film99may be in a structure having a High-k film106formed to cover a protrusion98and an SiO2film107stacked on an epitaxial layer8to cover the High-k film106, as shown inFIG. 26.

In the modes shown inFIGS. 24 to 26, portions of the gate insulating films99opposed to the protrusions98are the High-k films102,103and106. Thus, dielectric breakdown voltage of these portions (the High-k films102,103and106) in the gate insulating films99can be rendered greater than that of the remaining portions (the SiO2films). Therefore, electric fields applied to the gate insulating films99can be further relaxed.

While the embodiments of the present invention have been described, the present invention may be embodied in other ways.

For example, a structure inverting the conductivity type of each semiconductor portion of each of the aforementioned semiconductor devices (1,66,73,87and96) may be employed. In the semiconductor device1, for example, the p-type portions may be of the n-type, and the n-type portions may be of the p-type.

While only the semiconductor devices employing SiC have been employed as examples of the present invention in the aforementioned embodiments, the present invention is also applicable to a power semiconductor device employing Si, for example.

The implantation region21in the first embodiment may be deeper than body regions12, as shown in a semiconductor device110ofFIG. 27, for example.

The components shown in the respective embodiments of the present invention can be combined with one another within the scope of the present invention.

For example, a semiconductor device111shown inFIG. 28can be prepared by combining the components of the semiconductor device1according to the first embodiment shown inFIGS. 2A and 2Band the components of the semiconductor device66according to the second embodiment shown inFIGS. 12A and 12Bwith one another. Referring toFIG. 28, portions corresponding to the respective portions shown inFIGS. 2A and 2B,FIGS. 12A and 12Betc. are denoted by the same reference signs.

A semiconductor device112shown inFIG. 29can be prepared by combining the components of the semiconductor device1according to the first embodiment shown inFIGS. 2A and 2Band the components of the semiconductor device73according to the third embodiment shown inFIGS. 15A and 15Bwith one another. Referring toFIG. 29, portions corresponding to the respective portions shown inFIGS. 2A and 2B,FIGS. 15A and 15Betc. are denoted by the same reference signs.

A semiconductor device113shown inFIG. 30can be prepared by combining the components of the semiconductor device1according to the first embodiment shown inFIGS. 2A and 2Band the components of the semiconductor device87according to the fourth embodiment shown inFIG. 19with one another. Referring toFIG. 30, portions corresponding to the respective portions shown inFIGS. 2A and 2B,FIG. 19etc. are denoted by the same reference signs.

The semiconductor device according to the present invention can be built into a power module employed for an inverter circuit constituting a driving circuit for driving an electric motor utilized as a power source for an electric automobile (including a hybrid car), a train, an industrial robot or the like, for example. Further, the same can also be built into a power module employed for an inverter circuit converting power generated by a solar cell, a wind turbine generator or still another power generator (particularly a private power generator) to match with power of a commercial power supply.

The embodiments of the present invention are merely illustrative of the technical principles of the present invention but not limitative of the invention, and the spirit and scope of the present invention are to be limited only by the appended claims.

The components shown in the respective embodiments of the present invention can be combined with one another within the scope of the present invention.

Example

While the present invention is now described with reference to Example and comparative example, the present invention is not limited by the following Example.

Example 1 and Comparative Example 1

22 semiconductor devices1in total each having the structure shown inFIG. 1were prepared following the steps shown inFIGS. 3A to 3K(Example 1). 22 semiconductor devices in total were prepared by a method similar to that for Example 1, except that no implantation regions were formed.

An HTRB test was conducted on the 22 semiconductor devices and the 22 semiconductor devices obtained according to Example 1 and comparative example 1 respectively. Conditions of the HTRB test were set identical (150° C./150 hours/600 V bias) as to all semiconductor devices.

Consequently, a gate insulating film dielectrically broke down in zero out of the 22 semiconductor devices according to Example 1 in which implantation regions were formed, dielectric breakdown of gate insulating films was caused in 17 out of the 22 semiconductor devices according to comparative example 1.

DESCRIPTION OF THE REFERENCE NUMERALS