Data memory address generation for time-slot interchange switches

Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methods of operating same, and more particularly to integrated circuit switches that receive and transmit serial data streams and methods of operating same.

BACKGROUND OF THE INVENTION

Conventional time-slot interchange switches utilize a data memory and a connection memory to control how data passes through the switch. Examples of time-slot interchange (TSI) switch include those described in U.S. Pat. No. 4,510,597 and U.S. Pat. No. 4,093,827. In particular, the connection memory provides addresses to read data from the data memory so as to control the flow of data from inputs of the TSI switch to outputs of the TSI switch.

A circuit for providing data memory addresses in a TSI switch is illustrated inFIG. 1. InFIG. 1, a connection memory read counter10and an MPU address buffer12provide address values to a multiplexer14. The MPU address buffer12is provided to allow microprocessor access to the connection memory22. The multiplexer14provides a selected one of the output of the connection memory read counter10and the MPU address buffer12to a predecoder circuit16. The predecoder provides an address which is clocked into the register18on a first clock cycle. The address stored in the register18is decoded by decoder20and a read of the connection memory22is initiated. The data read from the connection memory is stored in a temporary register24for use if a microprocessor access is being performed. The output of the connection memory22and the temporary register24are provided to the multiplexer26. The temporary register24output, however, is only used on a cycle following a microprocessor tick and is not selected by the multiplexer26on two subsequent clock cycles. The multiplexer26is, therefore, controlled to select the output of the connection memory22on cycles other than the cycle immediately following a microprocessor tick and to select the output of the temporary register24on the cycle after a clock tick corresponding to a microprocessor access (a microprocessor tick). The output of the mutliplexer26is provided to the mutliplexer30. The multiplexer30also receives the output of the MPU address buffer12. The multiplexer30is controlled to select the output of the MPU address buffer during the microprocessor tick and, otherwise, to select the output of the mutliplexer26.

During operations when a microprocessor access is not performed, the multiplexer26provides the direct output of the connection memory22or the output of the temporary register24to the multiplexer-30. The multiplexer32and the comparator34receive the output of the multiplexer30which provides either the output of a MPU Address buffer12or the selected output of the multiplexer26. For data memory write operations where a microprocessor access is not performed, the multiplexer32provides the output of the data memory counter28. For data memory read operations where a microprocessor access is not performed, the multiplexer32provides the output of multiplexer30to the register40.

The address comparator34compares the output of the connection memory22and the data memory counter28and provides a bank selection value that is stored in the bank register38. Similarly, the output of the connection memory22is provided to the register40that provides its contents to the predecoder36. The predecoder36provides a pre-decoded address to the decoder42. The bank register38and the register40are both clocked during a second clock cycle which is a next subsequent clock cycle to the first clock cycle during which the register18is clocked. Thus, the address decode, the connection memory read access and the address compare take less than one clock cycle.

The output of the register40is provided to the predecoder36that provides its output to a decoder42, the output of which is provided to the data memory44. The bank register38output is also provided to the data memory44for the read operation. The output of the data memory44is provided to a parallel-to-serial converter to provide the output of the TSI switch.

As seen inFIG. 1, the data memory read address generation circuit may be considered as including two pipeline stages50and60. As used herein, the term “pipeline stage” refers to operations that are performed between a clock which initiates operations of a first portion of a circuit and a separate clock that initiates operations of a second portion of the circuit. Thus, a pipeline stage may have a duration from a first clock that initiates operations of the pipeline stage to a second clock that initiations operations of the next subsequent pipeline stage. Operations of the pipeline stage are, therefore, initiated with each occurrence of the clock associated with the pipeline stage and terminated upon each occurrence of the clock of the next subsequent pipeline stage. Thus, inFIG. 1, a first pipeline stage50is provided between the register18and the bank register38and register40. A second pipeline stage60is provided from the bank register38and address40. Thus, the first pipeline stage50provides for the read of the connection memory, the address compare and the predecode of the data memory read address. The second pipeline stage60provides for the decode of the data memory read address and the read of the data memory.

Furthermore, in the system illustrated inFIG. 1, the clocks of the two pipeline stages are synchronized such that the two pipeline stages have equal duration corresponding to one period of the synchronized clocks.

While the system ofFIG. 1provides for reads of the data memory44based on the output of the connection memory22, as the speed and/or size of the TSI switch increases, the time provided for the operations of any of the particular pipeline stages, such as the first pipeline stage50, may decrease. Such timing constraints may limit the speed and/or size of the TSI switch. Thus, notwithstanding conventional techniques to provide data memory addresses from a connection memory, such techniques may be insufficient as the speed and/or size of TSI switches increase.

SUMMARY OF THE INVENTION

Time-slot interchange (TSI) switches according to embodiments of the present invention include a pipelined data memory address generation circuit. The pipelined data memory address generation circuit includes a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to a write pointer location to provide a bank selection value. A third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory.

In particular embodiments of the present invention, the first pipeline stage includes a first register that receives a read address and stores the read address during a first clock cycle and a decoder that decodes the read address stored in the first register and provides a decoded read address to the connection memory.

Additionally, the second pipeline stage can include a second register that receives an output of the connection memory and stores the output of the connection memory during a second clock cycle. An address comparator compares the output of the connection memory stored in the second register to a current write address value of the data memory and provides results of the comparison as a bank select value to the third pipeline stage. The second pipeline stage may also include a predecoder that predecodes the output of the connection memory stored in the second register and provides the predecoded results to the third pipeline stage.

In still further embodiments of the present invention, the third pipeline stage includes a bank select register that receives the bank select value and stores the bank select value during a third clock cycle and provides the stored bank select value to the data memory. A third register receives the predecoded results and stores the predecoded results during the third clock cycle. A decoder decodes the predecoded results stored in the third register to provide an address to the data memory.

In additional embodiments of the present invention, a timing circuit that provides the first clock cycle and the second clock cycle such that a duration between the first clock cycle and the second clock cycle is greater than a duration between a first occurrence of the first clock cycle and next subsequent occurrence of the first clock cycle. The timing circuit may also provide the first clock cycle, the second clock cycle and the third clock cycle such that a duration from the first clock cycle to the second clock cycle is greater than a duration from the second clock cycle to the third clock cycle. The third clock cycle may occur about two periods of the first clock cycle after initiation of the first clock cycle. Alternatively, the third clock cycle may be more than two periods of the first clock cycle after initiation of the first clock cycle.

In still further embodiments of the present invention, a temporary register receives and stores the output of the connection memory and selectively provides the stored output of the connection memory to the second register. A data memory counter may also provide the current write address of the data memory to the address comparator.

In additional embodiments of the present invention, a data memory address generation circuit of a time-slot interchange switch is provided that includes a connection memory, a data memory counter, an address comparator that compares a value read from the connection memory with a value from the data memory counter, a first register operably associated with the connection memory to store a value read from the connection memory and provide stored connection memory values on subsequent clock cycles to the address comparator, a second register operably associated with the first register that stores a value based on the value stored in the first register, a data memory address decode circuit operably associated with the second register to receive a value stored in the second register and a bank register operably associated with the address comparator that stores the output of the address comparator and provides the stored value to a data memory.

The data memory address generation circuit may also include a multiplexer operably associated with the data memory counter and the first register to selectively provide one of an output of the data memory counter and the value stored in the first register to provide a value on which the value stored in the second register is based. A predecoder operably associated with the multiplexer and the second register may also be provided to provide a predecode of the value stored in the second register.

In additional embodiments of the present invention, a connection memory address register that stores a connection memory address is also provided. The connection memory address may be provided by a connection memory read counter. A connection memory address decode circuit operably associated with the connection memory and the connection memory address register receives the stored connection memory address for reading the connection memory.

The address generation circuit may also include a clocking circuit that provides a first clock that clocks the connection memory address register, a second clock that clocks the first register and a third clock that clocks the second register. The clocking circuit may be configured so that a corresponding third clock clocks the second register about two periods of the first clock after initiation of a corresponding occurrence of the first clock. The clocking circuit may also be configured so that a time from initiation of a first occurrence of the first clock to a corresponding initiation of the second clock and is greater than a period of the first clock. Furthermore, the clocking circuit may be configured so that a time from the initiation of the second clock to a corresponding initiation of the third clock is less than the time from initiation of a first occurrence of the first clock to a corresponding initiation of the second clock and is greater than a period of the first clock. The clocking circuit may also be configured so that the time from the initiation of the second clock to a corresponding initiation of the third clock is less than a period of the first clock.

The data memory address generation circuit may also include a temporary register operably associated with the connection to store values read from the connection memory and a multiplexer configured to selectively provide an output of the temporary register or an output of the connection memory to the first register.

In further embodiments of the present invention, a method of generating an address for accessing a data memory of a time-slot interchange switch is provided by generating an address for accessing the data memory utilizing at least two pipeline stages, wherein a first of the at least two pipeline stages reads data from a connection memory and a second of the two pipeline stages provides a comparison of the data read from the connection with a current data memory write address.

In particular embodiments of the present invention, the first of the two pipeline stages stores a connection memory read address in a first register utilizing a first clock, decodes the connection memory read address stored in the first register during a period of the first clock to provide a decoded connection memory read address and reads data from the connection memory utilizing the decoded connection memory read address during the period of the first clock.

Furthermore, the second of the two pipeline stages may store data read from the connection memory in a second register utilizing a second clock and generate a bank select value by comparing the data stored in the second register with a current data memory write address. The second of the two pipeline stages may also predecode the data stored in the second register to provide a predecoded data memory read address. Storing data read from the connection memory in a second register utilizing a second clock may be provided by storing data read from the connection memory in a second register utilizing a second clock that is initiated more than the period of the first clock after initiation of the first clock.

In further embodiments of the present invention, a third pipeline stage stores the bank select value in a bank select register utilizing a third clock, stores the predecoded data memory read address in a third register utilizing the third clock, decodes the predecoded data memory read address stored in the third register to provide a decoded data memory read address during a period of the third clock and reads the data memory utilizing the stored bank select value and the decoded data memory read address during the period of the third clock.

Additionally, storing data read from the connection memory in a second register utilizing a second clock may be provided by storing data read from the connection memory in a second register utilizing a second clock that is initiated more than the period of the first clock after initiation of the first clock. Storing the bank select value and storing the predecoded data memory read address may be provided by storing the bank select value and the predecoded data memory read address utilizing a third clock that is initiated about two periods of the first clock after initiation of the first clock.

In still additional embodiments of the present invention, data read from the connection memory is stored in a temporary register and selectively provided to the second register.

Additionally, a duration of time of the first pipeline stage may be greater than a duration of time of the second pipeline stage.

In still further embodiments of the present invention, a time-slot interchange switch includes a connection memory and a data memory. A connection-to-data memory pipeline has at least first and second stages that are synchronized with a clock signal and consecutively traversed during first and second time intervals. The first and second time intervals having a duration greater than T and less that T respectively, where T is a period of the clock signal.

In certain embodiments of the present invention, the sum of the duration of the first time interval and the duration of the second time interval equals 2T. Furthermore, the connection-to-data memory pipeline may have three stages that are synchronized to the clock signal.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2illustrates a time-slot interchange (TSI) switch100according to embodiments of the present invention. As seen inFIG. 2, the TSI switch100includes a serial to parallel converter110which converts serial data received at the serial inputs RX0-RXn and provides the parallel data to a data memory120. The data is read from the data memory120based on data stored in the connection memory130. Such data stored in the connection memory130may be written to the connection memory through the microprocessor interface150. The connection memory130is read and provides address and/or mode information to the registers140. Mode information refers to values utilized to set the mode of operation of the TSI switch100as described further herein. The registers140provide a data memory read address to the data memory120based on the information read from the connection memory130. The data read from the data memory120is provided to the output multiplexer (MUX)180which provides the output data to a parallel to serial converter190to provide the outputs TX0-TXn.

Also illustrated inFIG. 2is a microprocessor interface150that provides access to the data memory120and the connection memory130by a microprocessor. A clocking unit160provides internal timing of the TSI switch100based on external clocks. A JTAG port170provides boundary scan test capabilites for the switch100.

With regard to specific inputs and outputs of the switch100, A0-A15are address lines to access all internal memories. While a 16 bit address has been illustrated inFIG. 2, other numbers of address bits may be utilized, for example, 32 or 64 bits. CLK is the serial clock for shifting data in/out on the serial data streams. The device may be programmed to accept different frequencies of the clock CLK.

CS is the chip select and is used by a microprocessor to activate the microprocessor port of the switch100. D0-D15are the data bus data bits of the microprocessor interface150. While 16 parallel bits of data are been illustrated inFIG. 2, other numbers of data bits may be utilized, for example, 32 or 64 bits. DS is the data strobe and works in conjunction with CS to enable the read and write operations and enables the data bus lines (D0-D15). DTA indicates that a data bus transfer is complete. WFPS is the wide frame pulse select input. When the WFPS pin is LOW, FE/HCLK is the frame measurement input. When the WFPS pin is HIGH, FE/HCLK is an input for receiving a clock for frame alignment in the wide frame pulse mode (WFPS). ODE is the output drive enable and provides the output enable control for the TX serial outputs. RESET places the switch100into a reset state that clears the device internal counters, registers and brings TX0-TXn and D0-D15into a high-impedance state. R/W controls the direction of the data bus lines (D0-D15) during a microprocessor access. TCK provides the clock to the JTAG test logic. TDI provides an input for JTAG serial test instructions and data. TDO provides an output for JTAG serial data on the falling edge of TCK. TMS is a JTAG signal that controls the state transitions of the TAP controller. TRST asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. FOi is the Frame Pulse and indicates the start of a frame.

In particular embodiments of a TSI switch100according to the present invention, the data passing through the TSI switch100may have a constant delay from frame to frame or a variable delay from frame to frame. The mode of operation may be selected through the microprocessor interface150by, for example, setting mode select bits in the connection memory to select between variable delay mode, constant delay mode and processor mode. Fixed and variable delays are illustrated inFIG. 3. As is seen inFIG. 3, with a variable delay, data from a particular location in a received frame, such as Frame i, may be provided to any location of a subsequently transmitted frame. Thus, for example, channel 0 of Frame i may be placed in channel 8 of an output frame. Similarly, data from channel 2 to Frame i is placed in channel 1 of a subsequent output frame. As can be seen inFIG. 3, the delay provided to channel 2 and to channel 0 of Frame i differ, thus providing a variable delay. The latest channel is always provided. In variable delay mode a minimum of 3 channel delays is provided.

Constant delay mode is also illustrated inFIG. 3. Constant delay mode ensures frame integrity by keeping a constant frame latency for all channels. Thus, in the constant delay mode example, channels received in Frame i are transmitted in Frame i+2. For example, channel 0 in Frame i may be transmitted in channel 1 (or any other channel) in Frame i+2.

To provide variable delay mode a comparator is provided between the connection memory and the data memory. The TSI switch may store multiple frames of received data and selectively transmits from these multiple frames of data. The comparator compares the most recent data memory write address to the data from the connection memory to select which of multiple stored frames of data should be accessed. Merely placing the comparator between the connection memory and the data memory as illustrated inFIG. 1, however, may result in timing difficulties as the connection memory is read and the address is compared in a single clock cycle.

FIG. 4illustrates a data memory address generation circuit that may provide for variable delay mode and for 3 frame latency in constant delay mode. As seen inFIG. 4, the data memory address is generated utilizing a first pipeline stage385which provides data from connection memory130and a second pipeline stage390which performs the address compare and, optionally, predecode of the data from the connection memory130. A third pipeline stage395is also illustrated inFIG. 4and provides for the access of the data memory120.

Turning to the specifics of the data memory address generation circuit ofFIG. 4, a connection memory read counter300and an MPU address buffer305provide address values to a multiplexer310. The MPU address buffer305is provided to allow microprocessor access to the connection memory130. The multiplexer310provides a selected one of the output of the connection memory read counter300and the MPU address buffer305to a predecoder circuit315. In particular embodiments of the present invention, the multiplexer310provides the address value from either connection memory read counter300and/or the output of the MPU address buffer305to the predecoder315depending on whether a microprocessor access is being performed.

The predecoder315provides an address which is clocked into the register320on a first clock cycle. The address stored in the register320is decoded by decoder325and a read of the connection memory130is initiated. The data of the read operation from the connection memory130is stored in a temporary register330if a microprocessor access is being performed. The output of the connection memory130and the temporary register330are provided to the multiplexer340. During operations when a microprocessor access is not performed, the multiplexer340provides the direct output of the connection memory130to the register345. The register345clocks the data in on a second clock cycle that is, typically, a next subsequent clock cycle to the first clock cycle that clocks the register320. The multiplexer340selects the output of the temporary register330for one clock cycle after a microprocessor access for a connection memory read operation. The select signal may also be active to select the temporary register330during a microprocessor access. Otherwise, the mutliplexer340selects the direct output of the connection memory130.

The output of the register345is provided to the multiplexer350. The multiplexer350also receives the output of the MPU address buffer305. The output of the multiplexer350is provided to the multiplexer360and to the address comparator355. The multiplexer360and the comparator355also receive the output of a data memory counter335. For normal read operations, the multiplexer350provides the output of the register345. Thus, the multiplexer350selects the output of the MPU address buffer305during a microprocessor and, otherwise, selects the output of the register345.

The address comparator355compares the output of the register345and the data memory counter335and provides a bank selection which is stored in the bank register370. Similarly, during a non-microprocessor read of the data memory, the multiplexer360provides the output of the register345, through the multiplexer350, to the predecoder365. The mutliplexer360selects the output of the data memory counter335(i.e. a current write pointer) for write operations and, otherwise, selects the output of the multiplexer350.

The predecoder365provides an address to the register375. The bank register370and the register375are both clocked with a third clock cycle that is, typically, a next subsequent clock cycle to the second clock cycle that clocks the register345. The output of the register375is provided to a decoder380, the output of which is provided to the data memory120. The bank register370output is also provided to the data memory120for the read operation. The output of the data memory120is provided to a parallel to serial converter to provide the output of the TSI switch, for example, through the multiplexer180ofFIG. 2.

The connection memory read counter300, the MPU address buffer305, the multiplexer310, the predecoder315, the register320, the temporary register330, the data memory counter335, the multiplexer340, the multiplexer350, the register345, the address comparator355, the multiplexer360, the predecoder365, the bank register370and the register375may be provided as part of the internal registers140and/or the microprocessor interface150illustrated inFIG. 2. Similarly, the decoder325and the decoder380may be provided as part of the respective connection memory130and/or data memory120and/or as part of the internal registers140ifFIG. 2. However, other distributions of circuits, functions and/or operations may also be utilized while still benefitting from the teachings of the present invention. Thus, the present invention should not be construed as limited to the particular configurations illustrated inFIG. 2and/orFIG. 4.

FIG. 5is a timing diagram illustrating address generation for non-microprocessor reads of the data memory120.FIG. 5illustrates such operations for embodiments of the present invention that provide 5 internal clock cycles for each external clock cycle. Furthermore, an initial one of the five clock cycles after the beginning of each external clock cycle is reserved for microprocessor access. InFIG. 5, the external clock is labeled CLK, the clock which clocks the register320is labeled CMRD CLK, the output of register320is labeled CMA, the clock for the register345is labeled CMOUT, the output of the register345is labeled Register Out, the clock for the bank register370and the register375is labeled DMRD CLK, the output of the register375is labeled DMA and the output of the bank register370is labeled Bank Sel.

Turning to the specifics ofFIG. 5, the CMRD CLK is substantially synchronized with the external CLK such that respective periods of the CMRD CLK have a constant relationship with the external clock CLK. Such synchronization may be provided by a phase or delay locked loop or may be periodically provided by, for example, resetting an oscillator. Thus, for example, an oscillator may be timed to an external clock and reset periodically, such as, for example, every 5 cycles. The period of the CMRD CLK is illustrated as t0 inFIG. 5. As is further seen inFIG. 5, the CMRD CLK clocks the register320every t0 to clock the connection memory address data CMA0. . . CMAn into the register320. The break in the data of CMA, for example, between CMA1and CMA2, is illustrated inFIG. 5to reflect the microprocessor access. When data is clocked into the register320the read of the connection memory130begins. Thus, the beginning of a period of CMRD CLK reflect the beginning of operations of the first pipeline stage385ofFIG. 4.

The second pipeline stage390begins with the beginning of a period of CMOUT which clocks the output of the connection memory130into the register345. CMOUT begins a time t1 after the initiation of a corresponding period of CMRD CLK. The CMOUT clock clocks the register345to clock the connection memory data CMD0. . . CMDn into the register345. The break in the data of Register Out, for example, between CMD1and CMD2, is illustrated inFIG. 5to reflect the microprocessor access. When data is clocked into the register345the address compare and the predecode of the data subsequently begins. As is seen inFIG. 5, the register345provides data to the address comparator370and the predecoder365(through the multiplexer360) on successive clock cycles of CMOUT.

The address compare of the address comparator355and the predecode of the predecoder365preferably take less time than the read of the connection memory130. Thus, the time allowed for operations in the second pipeline stage390may be reduced so as to increase the time provided for completion of operations of the first pipeline stage385. This may be accomplished by delaying the clock CMOUT with respect to CMRD CLK to increase the duration allowed for operations in the first pipeline stage385. Thus, as seen inFIG. 5, the period of CMOUT may be the same as the period of CMRD CLK, however CMOUT may be a delayed version of CMRD CLK so that the time t1 may be greater than the time t0. In such a way, the duration of the first pipeline stage385may be extended so as to provide additional time for the read of the connection memory130.

Furthermore, by the-addition of the second pipeline stage390, the predecode of the data memory address may be moved to before the data memory address register375. By moving the predecode the time required for the third pipeline stage395may be reduced, thus reducing the likelihood that the data memory access of the third pipeline stage395becomes a critical timing path.

The third pipeline stage395begins with the beginning of the clock DMRD CLK that clocks data into the bank register370and the register375. The clock DMRD CLK clocks the bank register370and the register375to clock the bank select BSEL0. . . BSELn into the bank select register370and the data memory address DMA0. . . DMAn into the register375. The break in the data of DMA, for example, between DMA1and DMA2, and the break in the data of Bank Sel, for example, between BSEL1and BSEL2, are illustrated inFIG. 5to reflect the microprocessor access. When data is clocked into the bank register370and the register375the read of the data memory120begins.

The clock DMRD CLK is not delayed with respect to the CMRD CLK and, thus, the time t2, which is the duration of the second pipeline stage390, may be less than the time t0. Thus, the duration of the time allowed for operations in the second pipeline stage390may be reduced, thereby increasing the time for operations in the first pipeline stage385, by delaying the start of the second pipeline stage390. Furthermore, the duration of the third pipeline stage395may be unaffected by such changes because the start of the third pipeline stage395may be maintained in relation to the start of the first pipeline stage385.

By providing an additional pipeline stage (provided by the register345), the cycle time of the TSI switch100may be improved as the internal cycle time of reads of the connection memory130may be increased while maintaining the overall cycle time of the address generation for reads of the data memory. By, in effect, starting the read operation a cycle before the data would otherwise be required at the data memory the allowable duration for the read may be increased without effecting the overall time to traverse the pipeline. Such techniques may also be utilized in combination with one or more of increasing the memory size to allow more parallel operations and/or delaying the data memory address clock (DMRD CLK) and/or parallel to serial conversion clocks to provide additional time for address generation. Delaying the DMRD CLK and/or the parallel to serial conversion clocks may, however, be limited by the timing margin available with respect to the external clock CLK.

While the present invention has been described with reference to data memory address generation utilizing a system which provides microprocessor access, the present invention should not be construed as limited to such embodiments. For example, if microprocessor access is not desired, or is provided by another mechanism, the multiplexers310,350and340may be eliminated from the circuit ofFIG. 4. Similarly, the MPU address buffer305and the temporary register330may also be eliminated. Furthermore, the temporary register330may also be eliminated by controlling access to the data memory during microprocessor accesses, for example, through the gating and/or control of clocks utilized for such accesses. Accordingly, embodiments of the present invention should not be construed as limited to the particular configurations illustrated inFIG. 4.