Solid-state imaging device

A first bias voltage to be applied to a drain portion of a MOS transistor and a pulse voltage pulsating with a predetermined potential difference are being generated by an apparatus incorporating the MOS transistor. Voltage generation means generates a second bias voltage to be applied to a gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated in the apparatus incorporating the MOS transistor, a value of the first bias voltage generated in the apparatus incorporating the MOS transistor, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor. Superposition means generate a voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation means.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a voltage generation device, and more particularly to a voltage generation device for generating a voltage to be applied to a gate portion of a MOS transistor when performing a reset by transferring a charge which is stored in a source portion to a drain portion of the MOS transistor.

2. Description of the Background Art

In the upper half ofFIG. 10is shown a conventional structure of a part of a horizontal transfer register (HCCD) of a CCD solid-state imaging device, as well as a charge detection section for detecting a signal charge having been transferred from the HCCD. The lower half ofFIG. 10shows potentials of the respective portions in the HCCD and the charge detection section. Hereinafter, the structure and operation of the conventional HCCD and charge detection section will be briefly described.

The HCCD includes electrodes1001to1003. The electrode1001is a transfer gate electrode, to which a clock voltage φH1is applied. The electrodes1002and1003are transfer gate electrodes, to which a clock voltage φH2is applied. The clock voltages φH1and φH2have the same clock frequency, but are opposite in phase. The clock voltages φH1and φH2applied to these electrodes create a potential difference of φh within the HCCD. Due to this potential difference φh, the signal charge is transferred from the left to right inFIG. 10.

The charge detection section comprises an electrode1004, a source portion1005, a reset gate portion1006, a drain portion1007, a channel portion1008, and an amplifier1009. A voltage VOG is applied to the electrode1004. The signal charge1010which has been transferred from the HCCD is stored in the source portion1005. The source portion1005is connected to the amplifier1009. The amplifier1009converts the signal charge1010to a voltage, and outputs the voltage to outside of the charge detection section.

In order to perform a reset by draining the signal charge1010stored in the source portion1005to the drain portion1007, a bias voltage Vb and a clock voltage φR as shown inFIG. 11are applied to the reset gate portion1006. The channel portion1008previously has a channel potential φch. The potential of the channel portion1008is increased by φb with the bias voltage Vb being applied to the gate electrode, and varies by φcl due to the clock voltage φR.

A predetermined voltage VRD is applied to the drain portion1007in order to drain out the signal charge which comes in from the source portion1005by the action of the reset gate portion1006.

Now, the operation of the conventional charge detection section having the above structure will be described with reference to the figures.FIG. 12is a diagram illustrating the potentials of the respective portions when the pulse voltage φR is applied to the reset gate portion1006of the conventional charge detection section.

As shown inFIG. 12, when the pulse voltage φR is applied to the reset gate portion1006, the channel portion1008has a potential of φch+φb+φcl, which is higher than the potential VRD of the drain portion1007. As a result of this, as shown inFIG. 12, the signal charge1010stored in the source portion1005is drained to the drain portion1007, whereby the charge detection section is reset.

The potential VRD and the pulse voltage φR, which are to be generated within an apparatus which incorporates the charge detection section, vary from apparatus to apparatus. Therefore, for example, if the potential VRD takes its maximum value and the pulse voltage φR takes its minimum value under given operating conditions of the apparatus, the potential φch+φb+φcl of the channel portion1008will have a smaller value than that of the potential VRD of the drain portion1007, as shown inFIG. 13. As a result, the charge detection section suffers from what is called a sub-threshold state in the field of MOS transistors, resulting in a reset residue3000. Thus, a proper reset is not performed in the charge detection section.

Therefore, in order to prevent the above problem, a relatively large value is chosen for the bias voltage Vb to be applied to the reset gate portion1006. As described in Japanese Patent Laid-Open Publication No. 2002-231889, for example, the bias voltage Vb having a relatively large prescribed value, may be stored in a storage section in a voltage generation circuit, which in itself is an external element connected to the charge detection section. The voltage generation circuit applies the bias voltage Vb stored in its storage section to the reset gate portion1006. In this manner, the aforementioned sub-threshold state can be prevented from occurring in the MOS transistor structure.

However, if the value of the bias voltage Vb is too large, as shown inFIG. 14, the reset gate portion1006will have an excessively high potential even when the pulse voltage φR is not applied thereto. As a result, a saturation-decrease signal charge4000occurs, thus deteriorating the saturation characteristics. Thus, in the conventional charge detection section, it is difficult to prescribe the value of the bias voltage Vb to be applied to the reset gate portion1006.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a voltage generation device which makes it possible to apply an optimum bias voltage to a gate portion of a MOS transistor even though the values of a bias voltage and a pulse voltage to be generated in an apparatus incorporating the MOS transistor may vary from apparatus to apparatus.

A voltage generation device according to the present invention is directed to a voltage generation device for generating a voltage to be applied to a gate portion of a MOS transistor when performing a reset by transferring a charge stored in a source portion to a drain portion of the MOS transistor, wherein a first bias voltage to be applied to the drain portion of the MOS transistor and a pulse voltage pulsating with a predetermined potential difference are generated in an apparatus incorporating the MOS transistor, the voltage generation device comprising: voltage generation means for generating a second bias voltage to be applied to the gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated in the apparatus incorporating the MOS transistor, a value of the first bias voltage generated in the apparatus incorporating the MOS transistor, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor; and superposition means for generating the voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation means.

The voltage generation means may comprise: potential detection means for detecting a potential appearing at the channel portion of the MOS transistor when the pulse voltage is applied to the gate portion of the MOS transistor; and voltage difference measurement means for measuring a voltage difference between the first bias voltage and the potential detected by the potential detection means, and the voltage generation means may generate the second bias voltage based on the voltage difference measured by the difference measurement means.

The voltage generation means may further comprise amplification means for generating the second bias voltage by multiplying the voltage difference measured by the voltage difference measurement means by a predetermined value.

The predetermined value may be equal to or greater than a ratio of a change in the potential of the channel portion of the MOS transistor when the pulse voltage is applied to the gate portion of the MOS transistor to the predetermined potential difference of the pulse voltage.

The voltage generation means may be composed of a dummy MOS transistor having substantially the same structure as that of the MOS transistor, the pulse voltage is applied to a gate portion of the dummy MOS transistor, a potential of a source portion of the dummy MOS transistor is controlled so as to be equal to a potential which appears at a channel portion provided beneath the gate portion of the dummy MOS transistor when the pulse voltage is applied to the gate portion of the dummy MOS transistor, and the potential detection means may detect the potential of the source portion of the dummy MOS transistor.

A gate length of the gate portion of the dummy MOS transistor may be longer than a gate length of the MOS transistor.

A gate width of the gate portion of the dummy MOS transistor may be narrower than a gate width of the MOS transistor.

A channel potential depth of the channel portion of the dummy MOS transistor may be shallower than a channel potential depth of the MOS transistor.

The channel portion of the MOS transistor and the channel portion of the dummy MOS transistor may be formed by implanting an n-type impurity thereto, and a p-type impurity is further implanted to the channel portion of the dummy MOS transistor.

The MOS transistor and the dummy MOS transistor may be formed on an identical semiconductor substrate through an identical step.

The source portion of the dummy MOS transistor may be shielded from light.

The gate portion of the MOS transistor and the gate portion of the dummy MOS transistor may be electrically connected to each other.

Another aspect of the present invention is directed to a signal charge transfer device comprising: transfer means for transferring a charge based on a clock signal; charge detection means composed of a MOS transistor for outputting an amount of the charge stored in a source portion; and any of the above-described voltage generation devices for generating a voltage to be applied to a gate portion of the charge detection means.

Yet another aspect of the present invention is directed to a solid-state imaging device comprising: imaging means for taking in an image and outputting information of the image as a signal charge; and the aforementioned signal charge transfer device for transferring and outputting the signal charge which is output from the imaging means.

Yet another aspect of the present invention is directed to a voltage generation device for generating a voltage to be applied to a gate portion of a MOS transistor when performing a reset by transferring a charge stored in a source portion to a drain portion of the MOS transistor, comprising: bias generation means for generating a first bias voltage to be applied to the drain portion of the MOS transistor; pulse voltage generation means for generating a pulse voltage pulsating with a predetermined potential difference; voltage generation means for generating a second bias voltage to be applied to the gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated by the pulse voltage generation means, a value of the first bias voltage generated by the bias generation means, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor; and superposition means for generating the voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation means.

Yet another aspect of the present invention is directed to a solid-state imaging system comprising: imaging means for taking in an image and outputting information of the image as a signal charge; transfer means for transferring the signal charge output from the imaging means based on a clock signal; charge detection means composed of a MOS transistor for outputting a size of the signal charge having been transferred from the transfer means and stored in a source portion; and the voltage generation device according to claim15for generating a voltage to be applied to a gate portion of the charge detection means.

Yet another aspect of the present invention is directed to a voltage generation method for generating a voltage to be applied to a gate portion of a MOS transistor when performing a reset by transferring a charge stored in a source portion to a drain portion of the MOS transistor, wherein a first bias voltage to be applied to the drain portion of the MOS transistor and a pulse voltage pulsating with a predetermined potential difference are generated in an apparatus incorporating the MOS transistor, the voltage generation method comprising: a voltage generation step of generating a second bias voltage to be applied to the gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated in the apparatus incorporating the MOS transistor, a value of the first bias voltage generated in the apparatus incorporating the MOS transistor, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor; and a superposition step of generating the voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation step.

A voltage generation device according to the present invention makes it possible to apply an optimum bias voltage to a gate portion of a MOS transistor even though the values of a bias voltage and a pulse voltage to be generated in an apparatus incorporating the MOS transistor may vary from apparatus to apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a voltage generation device according to one aspect of the present invention will be described with reference to the figures.FIG. 1is a structural diagram illustrating an apparatus including a horizontal transfer register1(HCCD1; only a part thereof is shown) for use in a CCD solid-state imaging device, a charge detection section2for detecting a signal charge having been transferred from the HCCD1, and a voltage generation device3for generating a voltage to be used in the charge detection section2.FIG. 2Ais a graph illustrating the change over time of a DC voltage VRD to be applied to an input terminal a of the voltage generation device3.FIG. 2Bis a graph illustrating the change over time of a pulse voltage φR to be applied to an input terminal b of the voltage generation device3.

The HCCD1, which includes electrodes11to13formed on a semiconductor substrate35, transfers a signal charge output from an imaging section of the solid-state imaging device, in a left-to-right direction over the surface of the semiconductor substrate35as shown inFIG. 1. The electrode11is a transfer gate electrode, to which a clock voltage φH1is applied. The electrodes12and13are transfer gate electrodes, to which a clock voltage φH2is applied. The clock voltages φH1and φH2have the same clock frequency, but are opposite in phase.

The DC voltage VRD as illustrated inFIG. 2Ais applied to the input terminal a, so as to be input to a drain portion17, a drain portion25, and a differential amplifier5(described later) The pulse voltage φR as illustrated inFIG. 2Bis applied to the input terminal b, so as to be input to a capacitor22and a reset gate portion24(described later).

Next, the voltage generation device3will be described. The voltage generation device3, which is a circuit for generating a voltage to be used in the charge detection section2, includes a superposition circuit4, the differential amplifier5, and a dummy element6.

The dummy element6and the differential amplifier5will be described with reference to the figures.FIG. 3is a diagram illustrating the structure of a dummy element according to the present embodiment of the invention, and potentials of various portions therein.FIG. 4Ais a graph illustrating the change over time of a DC voltage to be applied to a (−) terminal of the differential amplifier5.FIG. 4Bis a graph illustrating the change over time of a DC voltage output from the differential amplifier5. The dummy element6includes a source portion23, the reset gate portion24, the drain portion25, a channel portion26, a capacitor29, and a resistor30. Based on the DC voltage VRD and the pulse voltage φR, the dummy element6generates a DC voltage Vb′ to be applied to a reset gate portion16of the charge detection section2.

The resistor30is connected to the source portion23in order to supply a charge to the source portion23. Although the resistor30is an optional element, in the case where the potential of the source portion23becomes too high because of a temporary excessive decrease in the charge of the source portion23due to pulse noise or the like, for example, the resistor30will serve to supply a charge to stabilize the potential of the source portion23. The differential amplifier5is also connected to the source portion23, so that the potential of the source portion23is output to the (−) terminal of the differential amplifier5. The pulse voltage φR as illustrated inFIG. 2Bis applied to the reset gate portion24. The channel portion26has a channel potential φch. The potential of the channel portion26varies between φch and φcl+φch in a pulsating manner, due to the pulse voltage φR being applied to the reset gate portion24. It is assumed that φcl is proportional to φR such that φcl=n×φR, where n is a positive coefficient which depends on the physical properties of the channel portion26.

The capacitor29smoothes the pulse voltage which is output from the source portion23and outputs the resultant voltage to the differential amplifier5. Specifically, the capacitor29smoothes the output voltage from the source portion23(which varies between φch and φcl+φh) so as to stay at φcl+φch. Thus, a DC voltage as illustrated inFIG. 4Ais output to the (−) terminal of the differential amplifier5.

The DC voltage VRD as illustrated inFIG. 2Ais applied to the drain portion25, whereby the potential of the drain portion25is always maintained at VRD. The DC voltage VRD applied to the drain portion25is also input to the (+) terminal of the differential amplifier5.

The differential amplifier5generates a DC voltage as shown inFIG. 4Bby subtracting φcl+φch, which is applied to the (−) terminal, from the DC voltage VRD, which is applied to the (+) terminal, and multiplying the result by 1/k, where k is a positive number which is equal to or less than n. The differential amplifier5outputs the generated DC voltage to the superposition circuit4.

Next, the superposition circuit4will be described with reference to the figures.FIG. 5is a graph illustrating the change over time of a pulse voltage output from the superposition circuit4.

The superposition circuit4includes a diode20, a resistor21, and the capacitor22. The superposition circuit4generates the pulse voltage shown inFIG. 5by superposing the pulse voltage φR, which is input to the capacitor22, onto a DC voltage 1/k×{VRD−(φch+φcl)}, which is an input voltage to the diode20. The superposition circuit4outputs the generated pulse voltage to the charge detection section2. Note that the diode20is assumed to be an ideal diode which does not cause a drop in voltage. Instead of the diode20, a MOSFET which is designed to function as a diode between its source and drain may also be used. The aforementioned DC voltage 1/k×{VRD−(φch+φcl)} will hereinafter be referred to as a “bias voltage Vb′”.

Next, the charge detection section2will be described. The charge detection section2includes an electrode14, a source portion15, the reset gate portion16, the drain portion17, a channel portion18, and an amplifier19. A DC voltage VOG is applied to the electrode14. The signal charge which has been transferred from the HCCD1is stored in the source portion15. The source portion15is connected to the amplifier19. The amplifier19converts the signal charge stored in the source portion15to a voltage, and outputs the voltage to outside of the charge detection section2.

In order to perform a reset by draining the signal charge stored in the source portion15to the drain portion17, the bias voltage Vb′ and the pulse voltage φR obtained from the superposition circuit4are applied to the reset gate portion16. The channel portion18previously has a channel potential φch. The potential of the channel portion18is increased by φb′ with the bias voltage Vb′ being applied to the reset gate portion16, and varies by φcl due to the pulse voltage φR. Note that Vb′ and φb′ satisfy the relationship φb′=n×Vb′, and that φR and φcl satisfy the relationship φcl=n×φR. Herein, n is identical to the constant n which has been described with reference to the dummy element6because the transistor in the charge detection section2and the transistor in the dummy element6are formed simultaneously within the same chip by using the same technique.

A predetermined voltage VRD is applied to the drain portion17. If a voltage equal to or greater than a certain value is applied to the reset gate portion16, signal charge flows in from the source portion15via the channel portion18.

The operations of elements in the HCCD1, the charge detection section2, and the voltage generation device3will hereinafter be described. First, an operation in which the voltage generation device3generates the pulse voltage as shown inFIG. 5will be described.

The DC voltage VRD as shown inFIG. 2Ais input to the input terminal a. The DC voltage VRD is applied to the (+) terminal of the differential amplifier5and the drain portion25.

On the other hand, the pulse voltage φR as shown inFIG. 2Bis input to the input terminal b. The pulse voltage φR is applied to the reset gate portion24. In response, the potential of the channel portion26varies between φch and φch+φcl.

In response to such changes in the potential of the channel portion26, the charge stored in the source portion23moves to the drain portion25, in accordance with the potential of the channel portion26. As the changes in the potential of the channel portion26are repeated, the potential of the source portion23gradually approximates φch+φcl, so that the voltage φch+φcl is output from the source portion23.

Meanwhile, the capacitor29serves to smooth the voltage which is output from the source portion23, and output the resultant voltage to the differential amplifier5. As a result, the DC voltage φch+φcl as show inFIG. 4Ais input to the differential amplifier5. Therefore, the time constant which is defined by the resistor30and the capacitor29is to be prescribed to be sufficiently longer than the period of φR.

The differential amplifier5subtracts the DC voltage φch+φcl, which is output from the source portion23, from the DC voltage VRD obtained from the input terminal a. The result of the subtraction VRD−(φch+φcl) would represent a difference between the potential appearing at the channel portion18and the potential of the drain portion17in an imaginary case where only φR was applied to the channel portion18. The differential amplifier5multiplies the result of the subtraction VRD−(φch+φcl) by 1/k, and outputs the result of the multiplication as Vb′ to the superposition circuit4.

The superposition circuit4superposes the pulse voltage φR which is input to the input terminal b onto the bias voltage Vb′ which is output from the differential amplifier5. As a result, the pulse voltage as shown inFIG. 5is output from the superposition circuit4. Thus, the operation in which the voltage generation device3generates the pulse voltage as shown inFIG. 5has been described.

Next, a reset operation by the charge detection section2will be described.FIG. 6is a diagram showing potentials of various portions of the charge detection section2according to the present embodiment in the case where signal charge is stored in the source portion15.FIG. 7is a diagram showing potentials of various portions of the charge detection section2during a reset operation.

As described above, the voltage generation device3generates the pulse voltage as shown inFIG. 5by superposing the pulse voltage φR onto Vb′=1/k×{VRD−(φch+φcl)}, and outputs the pulse voltage to the reset gate portion16of the charge detection section2.

The pulse voltage as shown inFIG. 5being applied to the reset gate portion16causes the potential of the channel portion18to vary between φch+φb′ and φch+φb′+φcl. Hereinafter, the potentials of various portions in the case where the voltage Vb′+φR is applied to the reset gate portion16will be described.

When the voltage Vb′+φR is applied to the reset gate portion16, as shown inFIG. 7, the potential of the channel portion18shifts to φch+φb′+φcl.

Since φb′ and Vb′ satisfy the relationship φb′=nVb′ and the relationship Vb′=1/k×{VRD−(φch+φcl)}, the potential φch+φb′+φcl of the channel portion18can be reexpressed as n/k×VRD+(1−n/k)(φch+φcl) based on these two equations. Since k is a positive number which is equal to or less than n, the potential of the channel portion18is equal to or greater than the potential VRD of the drain portion17. Therefore, the signal charge in the source portion15is drained to the drain portion17, whereby the charge detection section2is reset.

Now, a method for setting k will be described, assuming the following exemplary operating conditions for the present embodiment: VRD=15V; and the frequency of the pulse voltage φR is 10 MHz. Under such operating conditions, in order for the charge detection section2to be reset, i.e., in order for the signal charge100stored in the source portion15to flow into the drain portion17, there must be about 0.1V of a difference Δφm between the potential VRD of the drain portion17and the potential φch+φb′+φcl of the channel portion18.

Therefore, in the voltage generation device3, n, φch, and φcl may be obtained through experimentation, and a k value may be calculated such that the difference between n/k×RD+(1−n/k) (φch+φcl) and VRD equals 0.1V. In the case where the frequency of the pulse voltage φR is 100 MHz, the k value shall be set so that Δφm equals about 0.5V.

Thus, in accordance with the charge detection section and the voltage generation device of the present embodiment, the bias voltage Vb′ is determined based on the actually-occurring DC voltage VRD, pulse voltage φR, and channel potential φch. Therefore, even if the DC voltage VRD or the pulse voltage φR varies, an optimum bias voltage Vb′ can be generated.

Moreover, in accordance with the charge detection section and the voltage generation device of the present embodiment, the bias voltage Vb′ is determined based on the DC voltage VRD and the pulse voltage φR, which may vary depending on the manner of use. Therefore, elements for storing the bias voltage Vb′ and the like can be eliminated.

The conventional practice has been to detect the channel potential φch during manufacture, determine the bias voltage Vb to be applied to the reset gate portion by using design values of the DC voltage VRD and the pulse voltage φR, and store the value of the bias voltage Vb in the storage section of the voltage generation circuit. Therefore, during manufacture of each device, it has conventionally been necessary to detect the channel potential φch of the device.

On the other hand, in the voltage generation device according to the present embodiment, the bias voltage Vb′ is generated while detecting the fluctuating channel potential φch in the charge detection section. Thus, it is unnecessary to detect the channel potential φch during manufacture, and an optimum bias voltage Vb′ can be generated even if the channel potential φch fluctuates.

Moreover, in accordance with the charge detection section and the voltage generation device of the present embodiment, an optimum bias voltage Vb′ can be generated in real time, by constantly detecting the DC voltage VRD and the pulse voltage φR.

Although the present embodiment illustrates an example where the bias voltage Vb′ is generated by employing the differential amplifier5to multiply the voltage output from the dummy element6by 1/k, the method for generating the bias voltage Vb′ is not limited thereto. Specifically, by prescribing the gate length of the reset gate portion24of the dummy element9to be longer than the gate length of the reset gate portion16of the charge detection section2, the potential of the source portion23can be reduced. As a result, the potential which is output from the source portion23to the differential amplifier becomes lower. In this manner, too, it is possible to ensure that the potential of the reset gate portion16of the charge detection section2during a reset is higher than the DC voltage VRD.

Similarly, by prescribing the gate width of the reset gate portion of the dummy element to be smaller than the gate width of the reset gate portion of the charge detection section, it is also possible to ensure that the potential of the gate portion of the charge detection section during a reset is higher than the DC voltage VRD.

Further similarly, another method for ensuring that the potential of the gate portion of the charge detection section during a reset is higher than the DC voltage VRD is to prescribe the channel potential depth of the channel portion of the dummy element6to be shallower than the channel potential depth of the reset gate portion16of the charge detection section2.

It is preferable that the source portion23of the dummy element6according to the present embodiment is shielded from light. More specifically, it is preferable to extend the width of a metal wire (e.g., aluminum) which is connected to the source portion23so as to cover the source portion. As a result, electron generation due to light being incident to the source portion can be prevented, whereby the potential of the source portion can be stabilized.

The channel portions18and26of the charge detection section2and the dummy element6, respectively, are generally created by implanting an n-type impurity to a p-type semiconductor. Therefore, by further implanting a p-type impurity in only the channel portion26of the dummy element6, the density of the channel portion26can be reduced, and the channel potential of the channel portion26of the dummy element6can be made lower than the channel potential of the channel portion18of the charge detection section2. Thus, the potential which is output from the source portion23to the differential amplifier5can also be lowered by lowering the channel potential of the channel portion26of the dummy element6, thus ensuring that the potential of the reset gate portion16of the charge detection section2during a reset is higher than the DC voltage VRD.

Although the present embodiment illustrates an example where the bias voltage Vb′ is calculated by employing the dummy element6, the method for calculating the bias voltage Vb is not limited thereto. In other words, the bias voltage Vb′ may be calculated by means of an electrical circuit or by software means, so long as the bias voltage Vb′ is calculated based on the DC voltage VRD applied to the drain portion25, the pulse voltage φR applied to the reset gate portion24and the channel potential of the channel portion18of the charge detection section2. Hereinafter, an example in which the bias voltage Vb′ is calculated by software means will be described with reference to the figures.FIG. 8is a block diagram illustrating the overall structure of a solid-state imaging system according to the present invention.

The solid-state imaging system comprises a solid-state imaging device51, an analog front-end processor (AFEP)52, a timing generator (TG)53, a signal processing section55, a control section56, a voltage generation circuit57, and a storage section58.

As shown inFIG. 9, the solid-state imaging device51comprises an imaging section60, an HCCD1, an amplifier19, and vertical charge transfer elements (VCCDs)63, and outputs a signal representing an imaged picture as a voltage signal to the AFEP52. Note that the charge detection section2and the superposition circuit4shown inFIG. 1are to be provided between the HCCD1and the amplifier19. In the solid-state imaging system, the operation of generating the bias voltage Vb′ is performed by the control section56; therefore, the differential amplifier5and the dummy element6are unnecessary.

The imaging section60is composed of a plurality of elements including photodiodes, each of which converts an input optical signal to a signal charge and outputs it to a corresponding VCCD63. Based on a clock signal, the VCCD63outputs the signal charge to the HCCD1. The HCCD1, which corresponds to the HCCD1shown inFIG. 1, transfers the signal charge in a right-to-left direction inFIG. 9. The charge detection section2composed of a MOS transistor is provided near an output section of the HCCD1. The amplifier19, which corresponds to the amplifier19shown inFIG. 1, converts the signal charge to a voltage value and outputs it to the AFEP52.

The AFEP52performs processes such as amplification for the input voltage signal, and converts it to a digital signal for output to the signal processing section55. The signal processing section55performs processes such as generating a video signal based on the output signal from the imaging section60. The TG53generates a pulse voltage φR for operating the AFEP52and the solid-state imaging device51. The pulse voltage φR is to be input to the input terminal b shown inFIG. 1. The voltage generation circuit57generates a DC voltage VRD to be applied to the drain portion17of the charge detection section2. The DC voltage VRD is to be input to the input terminal a shown inFIG. 1. The storage section58stores the channel potential φch of the channel portion18of the charge detection section2. Based on the DC voltage VRD, the pulse voltage φR, and the channel potential φch, the control section56calculates an optimum bias voltage Vb′ to be applied to the reset gate portion16of the charge detection section2.

In the solid-state imaging system having the above structure, an operation of generating the bias voltage Vb′ to be applied to the reset gate portion16will be described.

Once the solid-state imaging device51begins operating, the control section56acquires the channel potential φch from the storage section58, VRD from the voltage generation circuit57, and a pulse voltage φR from the TG53. Then, the control section56calculates the bias voltage Vb′ based on these acquired voltages.

Next, the control section56controls the voltage generation circuit57to generate the DC voltage VRD, and generate an optimum bias voltage Vb′. The TG53generates and outputs the pulse voltage φR. The charge detection section2in the solid-state imaging device51receives the bias voltage Vb′, the pulse voltage φR, and the DC voltage VRD. As a result, the charge detection section2can perform a reset operation by using the optimum bias voltage Vb′.

Although it is assumed in the present embodiment that the voltage generation device is a device for generating a voltage for a charge detection section which is connected to an HCCD of a solid-state imaging device, it will be appreciated that the voltage generation device may be used in conjunction with any element other than a charge detection section connected to an HCCD of a solid-state imaging device.