MANUFACTURING METHOD

An electronic device includes an insulating first layer covering a second layer made of a doped semiconductor material. A cavity is formed to cross through the first layer and reach the second layer. Insulating spacers are forming against lateral walls of the cavity. A first doped semiconductor region fills the cavity. The first doped semiconductor region has a doping concentration decreasing from the second layer.

PRIORITY CLAIM

This application claims the priority benefit of French Application for Patent No. 2211714, filed on Nov. 10, 2022, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The present disclosure generally concerns electronic devices and, in particular, to electronic devices comprising doped regions and their manufacturing methods.

BACKGROUND

A bipolar transistor is an electronic device based on a semiconductor of the family of transistors. Its operating principle is based on two PN junctions, one forward and the other reverse. The biasing of the reverse PN junction with a low electric current (sometimes called transistor effect) enables to “control” a much higher current, according to the current amplification principle.

The operation of bipolar transistors depends on a large number of characteristics of bipolar transistors. Such a characteristic of bipolar transistors is their maximum oscillation frequency.

There is a need in the art to overcome all or part of the disadvantages of known semiconductor region manufacturing methods.

SUMMARY

An embodiment provides an electronic device comprising an insulating first layer covering a second layer made of a doped semiconductor material, a cavity crossing the insulating first layer, spacers being located against the lateral walls of the cavity, the cavity comprising a doped first semiconductor region, the doped first semiconductor region having a doping concentration decreasing from the second layer.

According to an embodiment, the second layer and the doped first semiconductor region form part of a collector of a bipolar transistor.

Another embodiment provides a method of manufacturing an electronic device comprising: forming an insulating first layer covering a second layer made of a doped semiconductor material; forming a cavity crossing the first layer; forming spacers against lateral walls of the cavity; and epitaxially growing a first doped semiconductor region in the cavity, from the second layer, the first doped semiconductor region having a doping concentration decreasing from the second layer.

According to an embodiment, a portion of the collector of the transistor is manufactured by the previously-described method, the second layer and the first doped semiconductor region forming part of the collector.

According to an embodiment, the spacers have a profile decreasing from the first layer.

According to an embodiment, the spacers and the first doped semiconductor region fill the cavity.

According to an embodiment, the first doped semiconductor region comprises a first surface in contact with the second layer, and a second surface opposite to the first surface, the surface area of the second surface being greater than the surface area of the first surface.

According to an embodiment, the surface area of the second surface of the first region is twice greater than the surface area of the first surface of the first doped semiconductor region.

According to an embodiment, the method comprises forming the second layer in a semiconductor substrate, forming an insulating third layer covering the second layer, and forming a second doped semiconductor region forming part of the collector of the transistor flush with the upper surface of the substrate.

According to an embodiment, the method comprises etching to expose the upper surface of the second doped semiconductor region.

According to an embodiment, a stack of layers is formed on the substrate, the stack comprising an insulating fourth layer covering the third layer, a fifth layer made of the material of the base, and an insulating sixth layer, the third and fourth layers forming the first layer.

According to an embodiment, the cavity crosses the stack and the third layer to expose the second layer.

According to an embodiment, the spacers are formed in such a way as to at least partially cover the lateral walls of the fifth layer, the method comprising partially etching the spacers in such a way that the upper surface of the spacers is coplanar with the upper surface of the first layer.

According to an embodiment, the method comprises forming a seventh layer, forming part of the base of the transistor, the seventh layer covering the first doped semiconductor region.

According to an embodiment, the method comprises forming the emitter region in front of the first doped semiconductor region, separated from the first doped semiconductor region by the seventh layer.

DETAILED DESCRIPTION

For the sake of clarity, only the steps and elements that are useful for the understanding of the described embodiments have been illustrated and described in detail.

Unless specified otherwise, the expressions “about”, “approximately”, “substantially”, and “in the order of” signify plus or minus 10%, preferably of plus or minus 5%.

Unless specified otherwise, the expressions “insulating” or “conductive” signify “electrically-insulating” or “electrically-conductive”.

FIG.1shows an embodiment of a doped region1in a device2.

Device2comprises a layer4made of doped semiconductor material. Layer4is, for example, made of doped silicon, for example, of N-type doped silicon. The upper surface of layer4is preferably planar.

Layer4is covered with a layer6made of an insulating material. Layer6is, for example, made of silicon oxide. A cavity8is located in layer6. Cavity8crosses through layer6to expose layer4. In other words, cavity8extends from the level of the upper surface of layer6, that is, the surface of layer6most distant from layer4, to the upper surface of layer4, that is, the surface of layer4closest to layer6. Preferably, cavity8does not extend into layer4. Thus, the bottom of cavity comprises, preferably exclusively, a portion of the upper surface of layer4. The lateral walls of cavity8comprise, preferably exclusively, portions of layer6.

Spacers9, referred to as “inner” spacers, are located against the lateral walls of cavity8. Spacers9preferably cover all of the lateral walls of cavity8. Spacers9extend from the upper surface of layer4, preferably up to the level of the upper surface of layer6. Further, spacers9cover the periphery of the upper surface of layer4. Thus, the peripheral portion, that is, the closest to the lateral walls of cavity8, from the bottom of cavity8, is entirely covered with spacers9. A central portion of the bottom of cavity8is not covered with spacers9.

Spacers9have a profile decreasing in width from the upper surface of layer4. In other words, the larger the distance to layer4, the lower the distance between the lateral wall of cavity8and region1, that is, the width of the spacers. Thus, the width of the spacers is the lowest at the level of the upper surface of region1and is the stronger at the level of the lower face of region1.

Region1is located in cavity8. Region1fills, for example, cavity8. Region1covers, and is in contact with, the central portion of the bottom of cavity8, that is, the portion of the upper surface of layer4forming the bottom of the cavity. Region1covers, and is preferably in contact with, spacers9. Region1preferably extends from the upper surface of layer4up to the level of the upper surface of layer6.

Due to the decreasing profile of spacers9from the upper surface of layer4, region1has a profile increasing in area from the upper surface of layer4. In other words, the more the distance to the upper surface of layer4increases, the more the surface area of region1increases. In other words, region1comprises a first surface in contact with layer4, and a second surface opposite to the first surface, the surface area of the second surface being greater than the surface area of the first surface. For example, the surface area of the second surface is twice greater than the surface area of the first surface.

Region1is made of the same material as layer4. Region1is doped with the same doping type as layer4. For example, region1and layer4are N-type doped. More precisely, region1and layer4are doped with the same dopants.

The doping, that is, the dopant concentration, of region1forms a gradient from layer4. More precisely, the doping of region1forms a decreasing gradient from layer4. The larger the distance to the portion of layer4in contact with region1, the lower the doping. The doping gradient is schematically shown by dotted lines, indicating various portions of region1, each portion corresponding to a range, preferably continuous, of dopant concentration, preferably distinct from the ranges corresponding to the portions. The more the portion is distant from layer4, the more the range of values comprises low values. Thus, the peripheral region of the upper surface of region1has the lowest doping.

FIGS.2A,2B, and2Cshow steps, for example successive, of a method of manufacturing a doped region such as that shown inFIG.1.

FIG.2Ashows a device resulting from a step of a method of manufacturing the embodiment ofFIG.1.

During this step, layer6is formed above layer4. Layer6preferably covers the entire layer4. Layer6covers at least the location of cavity8and the contour of the location of cavity8.

The doping of layer4is preferably substantially equal, or greater than, the doping of the layer4ofFIG.1.

FIG.2Bshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.1.

During this step, cavity8is formed in layer6. For example, cavity8is formed by the etching of layer6at the location of cavity8to extend through layer6and reach layer4.

The step ofFIG.2Bfurther comprises the forming of spacers9. The forming of spacers9comprises, for example, the forming, conformally, of a layer made of the material of the spacers, for example over the entire structure resulting from the forming of cavity8. Said layer is then etched by an anisotropic etching, to only keep spacers9.

FIG.2Cshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.1.

The step ofFIG.2Ccomprises the epitaxial growth of region1from layer4, more precisely from the portion of the upper surface of layer4forming the bottom of cavity8and which is not covered with spacers.

The increasing profile of region1from layer4causes the decrease of the concentration with the increase of the distance to layer4comprising the dopants. The doping of region1thus forms a gradient.

FIG.3shows an embodiment of an electronic device10comprising a bipolar transistor12.

Bipolar transistor12is formed in a substrate14. More precisely, transistor12is formed in the substrate and on an upper surface of substrate14. The substrate is made of a semiconductor material, for example of silicon. Transistor12comprises a region16of substrate14. Region16is a buried region of substrate14. In other words, region16does not extend all the way to the upper surface of substrate14. Region16, preferably, is not doped.

Transistor12further comprises an insulating wall18. Wall16is made of an electrically-insulating material, for example of silicon oxide. Wall16extends in substrate14, for example from the upper surface. For example, wall18laterally surrounds region16. As a variant, the transistor may comprise a plurality of walls18, walls18laterally delimiting region16on at least certain sides.

Device10further comprises regions20of substrate14. Regions20are made of a material identical to region16. Preferably, regions20have the same doping as region16. For example, regions20are not doped. Regions20are partially separated from region16by wall(s)18. Regions20are physically and electrically coupled to region16under wall18. Thus, the biasing of region20causes the biasing of region16.

Device10comprises a conductive layer21. Layer21covers, preferably entirely, preferably only, the upper surface of region20. Layer21is made of an electrically-conductive material, for example of a metal. Layer21corresponds to the contact of the substrate of transistor12, for example enabling to bias regions20and region16.

Transistor12further comprises a region22in substrate14. Region22is located inside of wall18. Region22extends from the upper surface of substrate14to region16. Region22preferably extends along the lateral inner surface of wall18. Region22is thus preferably in contact with wall18.

Region22is made of the semiconductor material of substrate14, for example of silicon. Region22is doped with a first conductivity type, preferably n-type doped. Region22corresponds to a portion of transistor12.

Transistor12comprises a conductive layer23. Layer23covers, preferably entirely, preferably only, the upper surface of region22. Layer23is made of an electrically-conductive material, for example of a metal. Layer23corresponds to the contact of the collector of transistor12.

Region22laterally surrounds a portion of a region24of transistor12. Region24is located inside of wall18and inside of region22. Region24extends from the upper surface of region16and up to the upper surface of substrate14. Region24preferably extends along the lateral inner surface of region22. Region22is thus preferably in contact with region24. Region24extends in a plane parallel to the upper surface of region16. Region24is preferably a layer having a substantially constant thickness. The upper surface of region24is preferably planar. Region24extends in the entire area surrounded with region22. Region24extends over region16. The first portion is thus in contact with region16and with region22.

Region24is made of the semiconductor material of substrate14and of region22, for example made of silicon. Region24is doped with the same conductivity type as region22, for example of the first conductivity type, preferably n-type doped. Region24corresponds to another portion of the collector of transistor12.

Preferably, region24has a doping level, that is, a dopant concentration of the first type, smaller than the doping level, that is, than the dopant concentration, of region22.

Transistor12comprises a region26. Region26is made of an electrically-insulating material, for example silicon oxide. Region26extends over region24. Region26extends from the upper surface of region24up to a level higher than the level of the upper surface of layer23. Region26preferably extends over the entire periphery of region24, to form a cavity8substantially in front of the center of region24. Region26is thus preferably in contact with the lateral walls of layers23and of regions22. A portion of the upper surface of region24thus forms the bottom of cavity8.

Spacers9and region1, such as described in relation withFIG.1, are located in cavity8. Region24then corresponds to the layer4ofFIG.1. Region1is thus doped with the same doping type as region24, that is, type N. Regions1,24, and22thus form the collector of transistor12.

The upper surface of region24is preferably entirely covered with region1, with spacers9, and with region26.

Region26extends, on the external side, that is, the side most distant from region1, along a height greater than on the inner side. Region26thus forms, at the level of its upper surface, a step. The assembly comprising region26and region1thus comprises a cavity28, laterally delimited by region26, and more precisely the portion of region26having a height greater than the rest of region26. The bottom of cavity28is formed by region26, and more precisely by the portion of region26having the lowest height, and by the upper surface of region1.

Transistor12further comprises a region30. Region30is located in cavity28. Region30is, for example, located, preferably entirely, in front of cavity8. Region30preferably comprises a first portion31corresponding to a layer and a second portion33extending from first portion31to form a cavity31in region30. The bottom of cavity31is formed by the first portion of region30and the lateral walls of cavity31are formed by the second portion33of region30.

Region30covers, preferably entirely, the upper surface of region1. Region30does not, for example, cover the upper surface of region26. Region30is preferably located at the center of cavity28. The portion of the bottom of cavity28covered with region30is surrounded with a portion of the bottom of cavity28which is not covered with region30.

Region30is, for example, made of the semiconductor material of substrate14, for example of silicon. Region30is doped with a second conductivity type, that is, the conductivity type opposite to the first conductivity type, preferably p-type doped. Region30corresponds to a portion of the base of transistor12.

Transistor12comprises a region32located in cavity28. Region32covers the bottom of cavity28which is not covered with region30. Thus, region32laterally surrounds the first portion of region30. The bottom of cavity38is thus preferably entirely covered with regions30and32. Region32preferably does not cover the upper surface of region1. Region32has, for example, the same height as the first portion of region30.

Region32is, for example, made of polysilicon. Region32is doped with the same conductivity type as region30, that is, the second conductivity type, that is, the conductivity type opposite to the first conductivity type, preferably p-type doped. Region32corresponds to a portion of the base of transistor12. Regions30and32thus form the base of transistor12.

Preferably, region30has a doping level, that is, a dopant concentration of the second type, lower than the doping level, that is, than the dopant concentration, of region32.

Transistor12comprises a conductive layer34. Layer34covers, preferably entirely, preferably only, the upper surface of region32. Layer24is made of an electrically-conductive material, for example of a metal. Layer34corresponds to the contact of the base of transistor12.

Transistor12further comprises a layer36located in cavity31. In other words, layer36covers, preferably entirely, the bottom of cavity31. In other words, layer36extends over the first portion of region30, laterally surrounded with the second portion33of region30. The height of layer36is preferably smaller than the height of portion33. Layer36is, for example, made of the same material as substrate14, for example of silicon. The material of layer36is preferably not doped.

Transistor12comprises an insulating layer38. Layer38is, for example, made of silicon oxide. Layer38extends over a portion of layer36. Layer38extends over the periphery of layer36. Layer38is preferably in contact with portion33over the entire contour of cavity31and extends towards the center of layer36. Layer38does not entirely cover layer36. A central portion of layer36is not covered with layer38.

Transistor12further comprises a region40. Region40covers layer38and the central portion of layer36, that is, the portion which is not covered with layer38. Region40is thus in contact with layer36. For example, region40partially covers the portion33of region30. The lateral walls of region40are thus located in front of the portions33of region30.

Region40is made of polysilicon. Region40is doped with the same conductivity type as regions22and24. Region40is, for example, n-type doped. Region40forms the emitter of transistor12.

Transistor12comprises a conductive layer42. Layer42covers, preferably entirely, preferably only, the upper surface of region40. Layer42is made of an electrically-conductive material, for example, of a metal. Layer42corresponds to the contact of the emitter of transistor12.

Transistor12further comprises spacers44(referred to herein as “outer” spacers). Spacers44extend on the lateral walls of region40, preferably on all the lateral walls of region40. Spacers44extend, preferably, vertically from portion33to the upper level of region40. Spacers extend, preferably, horizontally, from the lateral walls of region40to the level of the interface between portion33and layer34.

The extrinsic base resistance and the base-collector capacitance are characteristics of bipolar transistors. The maximum oscillation frequency is such that the higher the extrinsic base resistance, the lower the frequency and conversely. Similarly, the maximum oscillation frequency is such that the higher the base-collector capacitance, the lower said frequency and conversely. It may be chosen to increase the doping, for example with boron, of region30, which would decrease the extrinsic base resistance. However, this would increase the base-collector resistance, in particular due to the diffusion of boron to the collector. The presence of a doping gradient in region1enables to decrease the doping at the level of the interface between the collector and the base. The probability of diffusion of boron is thus lower. The maximum oscillation frequency is thus increased.

FIGS.4A to4Ishow steps, for example successive, of a method of manufacturing a bipolar transistor such as that shown inFIG.3.

FIG.4Ashows a device resulting from a step of a method of manufacturing the embodiment ofFIG.3.

During this step, insulating walls18are formed in substrate14. Insulating walls18thus delimit an area where the base, the collector, and the emitter of transistor12will be formed. The height of walls18is smaller than the height of substrate14. Thus, a portion of substrate14, not shown, extends under walls18.

The step ofFIG.4Afurther comprises the forming of region22and of region24. Regions22and24are, for example, formed by doping of regions of substrate14. Regions22and24are preferably doped to have the doping levels described in relation withFIG.3.

The step ofFIG.4Acomprises the forming of an insulating region46in substrate14. Region46is made of the material of region26, for example of silicon oxide. Region46covers, preferably entirely, preferably only, region24. Thus, region46preferably extends from the upper surface of region24to the upper level of substrate14.

FIG.4Bshows a device resulting from another step of the method of manufacturing the embodiment ofFIG.3.

During this step, element48are formed. Elements48cover, preferably entirely, the locations of regions22. In other words, elements48cover the upper surface of substrate14directly around walls18. Elements48, for example, at least partially cover walls18. Elements48preferably do not cover regions22and region46.

Elements48are, for example, made of a conductive material. Elements48are, for example, made of polysilicon. Elements48are, for example, made of a non-doped material.

The step ofFIG.4Bfurther comprises the forming of a stack50of layers. Stack50entirely covers, for example, the structure resulting from the forming of elements48. In particular, stack50covers, preferably entirely, elements48, the portions of walls18not covered with elements48, regions22, and region24.

Stack50comprises a lower layer52. Layer52is thus the layer of the stack closest to substrate14. Layer52conformally covers the structure resulting from the forming of elements48. Layer52is made of an insulating material, for example the same material as region46, for example the same material as the region26ofFIG.3. Layer52is, for example, made of silicon oxide.

Stack50comprises a layer56covering layer54. Layer56covers, preferably entirely, preferably conformally, layer54. Layer56is made of an insulating material. Layer56is made of an insulating material different from the material of layer52. Layer56is, for example, made of silicon nitride.

Stack50comprises a layer58covering layer56. Layer58covers, preferably entirely, preferably conformally, layer56. Layer58is made of an insulating material. Layer56is, for example, made of the same material as layer52. Layer56is made of a material different from the material of layer56. Layer56is, for example, made of silicon oxide.

Stack50comprises a layer60covering layer58. Layer60covers, preferably entirely, preferably conformally, layer58. Layer60is made of an insulating material. Layer60is made of an insulating material different from the material of layer58. Layer60is, for example, made of the same material as layer56. Layer60is, for example, made of silicon nitride.

FIG.4Cshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3. This step substantially corresponds to the step ofFIG.2B.

During this step, a cavity62, corresponding to the cavity8ofFIG.2B, is formed. Cavity62extends from the upper surface of layer60to the upper surface of region24. In other words, the cavity crosses through the layers of stack50, that is, layers60,58,56,54,52, as well as region46.

Cavity62is located at the location of the region1and of the spacers9ofFIG.3. Thus, the lateral walls of cavity62partially correspond to the lateral walls of spacers9.

The step ofFIG.4Cfurther comprises the forming of spacers9in cavity62. The forming of spacers9comprises, for example, the forming, conformally, of a layer made of the material of the spacers, for example over the entire structure resulting from the forming of cavity62. Said layer is then etched by an anisotropic etching, to only keep spacers9. A portion of region24, preferably central, is thus exposed by the etch step.

Spacers9cover, preferably entirely, the lateral walls of at least layer46and layers52and54. In the example ofFIG.4C, spacers9at least partially cover the lateral walls of layers covering layer52. Thus, spacers9cover, for example at least partially, for example entirely, the lateral walls of layer54and for example at least partially the lateral walls of layer56.

FIG.4Dshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3.

The step ofFIG.4Dcomprises the epitaxial growth of region1from layer24, more precisely from the portion of the upper surface of layer24forming the bottom of cavity62and which is not covered with the spacers.

Region1extends from region24up to the level of the upper surface of layer52. The height of region1is thus smaller than the height along which extend spacers9in contact with the lateral walls of cavity62.

The increasing profile of region1from layer24causes the decrease of the concentration with the increase of the distance to layer24comprising the dopants. The doping of region1thus forms a gradient.

FIG.4Eshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3.

During this step, the portions of spacers9extending above the level of the upper surface of region1are etched. Thus, the upper surface of region1and the upper surface of spacers9are substantially coplanar with each other. Further, the upper surface of region1and the upper surface of spacers9are, preferably, substantially coplanar with the level of the upper surface of layer52.

In the case where spacers are formed at the step ofFIG.4Cto extend up to the level of the upper surface of layer52, it is possible for this step not to be implemented.

FIG.4Fshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3.

During this step, a region66is formed in cavity62. Region66corresponds to a portion of the region30ofFIG.3. Region66is, for example, formed by epitaxial growth, from region1. Region66covers, preferably entirely, the upper surface of region1and the upper surface of spacers9in cavity62. Region66thus fills the bottom of cavity62after the forming of the portion of region1. Region66preferably extends from the upper surface of region1up to the level of the upper surface of layer54.

Region66is made of the material of the region30ofFIG.3. Thus, region66is preferably made of n-type doped silicon, in the case of a PNP transistor. The doping level of region66is, for example, substantially equal to the doping level of the region30ofFIG.3. Alternatively, the transistor may be an NPN transistor, in which case region66is P-type doped.

The step ofFIG.4Ffurther comprises the forming of layer36. Layer36is formed on the upper surface of region66. Layer36covers, preferably entirely, preferably only, the upper surface of region66. Layer36is, for example, formed by epitaxial growth. The height of layer36is, for example, smaller than the thickness of layer54.

The step ofFIG.4Fcomprises the forming of an insulating layer68. Layer68conformally covers the structure resulting from the forming of layer36. Thus, layer68covers the upper surface of layer60, the lateral walls of cavity62, that is, the lateral surfaces of layers60,58, and56located in cavity62, and the upper surface of layer36. Layer68is thus in contact with the lateral surfaces of layers60,58, and56.

Layer68is, for example, made of the same material as layer58, for example of silicon oxide. The material of layer68is different from the material of layer60.

The step ofFIG.4Fcomprises the forming of an insulating layer70. Layer70conformally covers the structure resulting from the forming of layer68. Thus, layer68covers, preferably entirely, preferably only, the upper surface of layer68.

Layer70is made of a material different from the material of layer68. Layer70is, for example, made of the same material as layer60, for example a silicon nitride.

FIG.4Gshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3.

The step ofFIG.4Gcomprises a step of anisotropic etching of layer70. This etch step is preferably configured to only etch layer70(i.e., the etch is selective to the material of layer70). This etch step is, for example, configured not to etch layer68. Layer70is entirely etched during this etch step, except for spacers72. Spacers72are located at the level of the lateral walls of cavity62. Spacers cover portions74of layer68having, in cross-section view, an L shape. Spacers72do not entirely fill cavity62. Thus, a central portion of cavity62is not covered with spacers72.

The step ofFIG.4Gthen comprises a step of etching of layer68. Layer68is preferably entirely etched except for the portions74covered with spacers72. Portions74comprise a horizontal portion extending, under spacers72, on the upper surface of layer36, from the lateral surfaces of cavity62to the center of cavity62. The horizontal portion of portions74are such that a portion, for example a substantially central portion, of the upper surface of layer36is not covered with portions74. Portions74further comprise a vertical portion extending on the lateral walls of cavity62, for example from the upper surface of layer36to the upper surface of layer60.

FIG.4Hshows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3.

The step ofFIG.4Hcomprises a step of etching of layer60and spacers72. Spacers72are made of the same material as layer60. Spacers72and layer60can thus be etched by the same etching. The etching is, for example, a wet etching.

During this etch step, the vertical portion of portions74is at least partially etched. For example, the vertical portion of portions74is etched down to the level of the upper surface of layer68.

The step ofFIG.4Hfurther comprises the forming of a layer76on the structure resulting from the etching of layer60and of portions74. Layer76thus covers, preferably entirely, preferably only, layer58, portions74and the portion of layer36which is not covered with portions74.

Layer76is made of the material of region40ofFIG.1, that is, for example of n-type doped polysilicon. The doping of layer76is, for example, substantially equal, for example equal, to the doping of region40ofFIG.1.

The step ofFIG.4Hfurther comprises the forming of an insulating layer78. Layer78covers, preferably entirely, preferably only, layer76. Layer78is made of an insulating material, preferably the same material as layer58, for example silicon oxide.

FIG.4Ishows a device resulting from another step of a method of manufacturing the embodiment ofFIG.3.

During this step, layers76and78are etched to form region40covered with a portion of layer78. Layers76and78are, for example, etched simultaneously. Layers76and78are etched so that the remaining lateral walls of region40and of layer78are coplanar.

Further, layers76and78are preferably etched so that portions74are entirely covered with region40. Layers76and78preferably partially cover layer58.

The method further comprises additional steps, carried out after the step ofFIG.4I, to obtain the device ofFIG.3. In particular, the method comprises: the removal of the layer58which is not covered with region40; the encapsulation of region40in an electrically-insulating region; the partial etching of layers52and54to partially expose regions22; the removal of encapsulation layer80; the forming of spacers44on the lateral walls of region40; the growth of region66and the diffusion of the charges to form region30; and the forming of conductive layers21,23,34, and42.

According to another embodiment, the stack50ofFIG.4Bmay comprise an additional insulating layer, covering layer60. The thickness of the additional layer is, for example, substantially equal to the sum of the thicknesses of layer46and of layer52. The step of etching of stack50described in relation withFIG.4Cis such that the etching stops at the level of the upper surface of layer52. Spacers9are then formed as described in relation withFIG.4C. In other words, an insulating layer is formed over the entire structure. Said layer, the additional layer, and layers46and52are etched, by an anisotropic etching, to form spacers on the walls of cavity62.

An advantage of the described embodiments is that the base-collector capacitance is smaller than that of a known bipolar transistor. The maximum oscillation frequency is thus higher.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, the steps ofFIGS.2A to2Cmay be applied to other manufacturing methods, in particular other bipolar transistor manufacturing methods, said methods comprising: the forming of a stack comprising a doped region corresponding to a portion of the collector of the transistor and an insulating layer crossed by a cavity having another portion of the collector formed therein; and the forming of a portion of the base on the other portion of the collector.

Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove.