MOS transistor on SOI protected against overvoltages

A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

CROSS REFERENCE TO RELATED APPLICATION

This application is a translation of and claims the priority benefit of French patent application number 12/56762, filed on Jul. 13, 2012, entitled “MOS TRANSISTOR ON SOI PROTECTED AGAINST OVERVOLTAGES,” which is hereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND

The present disclosure relates to the protection against overvoltages of a MOS transistor formed in a semiconductor layer of SOI (“Silicon-On-Insulator”) type. The present disclosure more specifically relates to the protection of such a MOS transistor against overvoltages due to electrostatic discharges.

DISCUSSION OF THE RELATED ART

Generally, to protect a component against overvoltages, for example electrostatic discharges capable of occurring while the component is not connected, a protection device connected between the terminals where the overvoltage is capable of occurring is used. In the case of a one-way protection, this device may be an uncontrolled element such as an avalanche diode or a Shockley diode. This protection device may also be a controlled element such as a transistor or a bipolar thyristor or a field-effect-controlled thyristor.

In the case where the component to be protected is a MOS transistor formed in an SOI-type semiconductor layer of minimum dimension, the protection device is generally arranged next to the transistor to be protected, and the protection device may use a larger surface area than that taken up by the transistor.

There thus is a need for a device for protecting a MOS transistor formed in an SOI-type semiconductor layer against overvoltages, the assembly taking up a surface area little greater than that taken up by the transistor alone.

SUMMARY

An embodiment provides a MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer, itself arranged on a semiconductor substrate comprising a lateral field-effect-controlled thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

According to an embodiment, the field-effect turn-on region of the thyristor corresponds to its cathode gate region and extends under at least a portion of the drain region of the MOS transistor.

According to an embodiment, the field-effect turn-on region of the thyristor corresponds to its anode gate region and extends under at least a portion of the source region of the MOS transistor.

According to an embodiment, the MOS transistor protected against overvoltages comprises a first well of a first conductivity type and a second well of the second conductivity type extending next to each other in the upper portion of the substrate, at least partly under the MOS transistor. The MOS transistor protected against overvoltages further comprises first and second regions of the second conductivity type respectively extending at the surface of the first and second wells, the first and second regions being separated from each other by a portion of the first well corresponding to the field-effect turn-on region of the thyristor.

According to an embodiment, the first and second wells are respectively P-type and N-type doped. A cathode contact region of the thyristor corresponds to a third N-type region more heavily doped than the first region, extending at the surface of the first well next to the first region and in contact therewith. The anode region of the thyristor corresponds to a fourth heavily-doped P-type region extending at the surface of the second well next to the second region and in contact therewith.

According to an embodiment, the first and second wells are respectively P-type and N-type doped. A cathode contact region of the thyristor corresponds to a third N-type region more heavily doped than the first region, extending above the first region and in contact therewith. The anode region of the thyristor corresponds to a fourth heavily-doped P-type region extending above the second region and in contact therewith.

According to an embodiment, the substrate is P-type doped and the first and second wells are respectively N-type and P-type doped. An anode contact region of the thyristor corresponds to a third P-type region more heavily doped than the first region, extending at the surface of the first well next to the first region and in contact therewith. The cathode region of the thyristor corresponds to a fourth heavily-doped N-type region extending at the surface of the second well next to the second region and in contact therewith. An N-type buried layer extends at least under the second well.

According to an embodiment, a first terminal connected to the first well is connected to the cathode of the thyristor, and a second terminal connected to the second well is connected to the anode of the thyristor.

According to an embodiment, a first terminal connected to the first well is connected to the anode of the thyristor, and a second terminal connected to the second well is connected to the cathode of the thyristor.

According to an embodiment, the thickness of the SOI-type semiconductor layer ranges between 3 and 100 nm, and the thickness of the insulating layer ranges between 5 and 30 nm.

The foregoing and other features and benefits will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of semiconductor components,FIGS. 1A,2A, and3are not to scale.

DETAILED DESCRIPTION

FIG. 1Ais a cross-section view schematically showing a MOS transistor formed in an SOI-type semiconductor layer protected against overvoltages.

A MOS transistor T1is formed in an active area1of an SOI-type semiconductor layer3, for example, made of single-crystal silicon, arranged on an insulating layer5currently called BOX (“Buried OXide”), for example, made of silicon oxide, itself arranged on a semiconductor substrate7, for example, made of silicon. MOS transistor T1comprises a conductive gate9extending on semiconductor layer3and insulated therefrom by a gate insulator11. A source region13and a drain region15extend in semiconductor layer3on either side of gate9. Active area1of semiconductor layer3, having MOS transistor T1formed therein, is surrounded with an insulation region17, for example, made of silicon oxide, which extends from upper surface of layer3all the way to substrate7.

As an example of dimensions, semiconductor layer3for example has a thickness ranging between 3 and 100 nm, for example, on the order of 10 nm, and insulating layer5for example has a thickness ranging between 5 and 30 nm, for example, on the order of 25 nm.

Respectively call S1, D1, and G1the source, drain, and gate electrodes of MOS transistor T1.

To protect MOS transistor T1against positive overvoltages that may occur between its drain D1and its source S1while it is not connected, a lateral NPNP+thyristor is formed in substrate7, mainly under MOS transistor T1.

In the shown example, a P-type doped well20and an N-type doped well22are formed next to each other in the upper portion of substrate7, which is for example very lightly P-type doped. Junction19between wells20and22is in front of drain region15of MOS transistor T1, on the side of gate9. Starting from junction19between wells20and22, well20extends under drain region15of MOS transistor T1and beyond, and well22extends under the rest of MOS transistor T1and beyond.

N-type doped regions23and25, separated by a portion26of well20located in front of a portion of drain region15of MOS transistor T1, respectively extend at the surface of wells20and22, under MOS transistor T1and insulation region17. Portion26of well20is separated from drain region15of MOS transistor T1by insulating layer5.

In the shown example, region25extends under a portion of MOS transistor T1, from junction19between wells20and22, and under insulation region17. Region23extends at a distance d from junction19, under an end of drain region15of MOS transistor T1located on the side opposite to gate9, and under insulation region17. As shown, the length of drain region15may be greater than that of source region13so that this drain region covers region26located between regions23and25.

A contact region27, more heavily N-type doped than region23, extends at the surface of well20, next to region23and in contact therewith. An anode region29, heavily P-type doped, extends at the surface of well22next to region25and in contact therewith. Regions27and29may be covered with a metal silicide30and are accessible from the upper surface of the structure.

An insulation ring31, for example, made of silicon oxide, extending from the upper surface of semiconductor layer3all the way into substrate7, surrounds wells20and22.

Terminals PW and NW are preferably provided to bias wells20and22. An insulation region33is formed from the upper surface of semiconductor layer3all the way into well20, next to contact region27. Terminal PW for example corresponds to a region32of the surface of well20, more heavily P-type doped than well20, located between insulation regions31and33. Region32may be covered with metal silicide30at the same time as regions27and29. Terminal NW possibly similarly provided on well22is shown in dotted lines since it is not visible in the cross-section plane ofFIG. 1A.

Regions23,26,25, and29formed in substrate7partly under MOS transistor T1form the different regions of a lateral protection thyristor. Region23forms the cathode region of the thyristor, portion26of well20forms the cathode gate region of the thyristor, region25forms the anode gate region of the thyristor, and region29forms the anode region of the thyristor. Cathode gate region26of the thyristor, located between regions23and25, is located under drain region15of MOS transistor T1and is separated therefrom by insulating layer5.

Anode A and cathode K of the protection thyristor are respectively connected to drain D1and to source S1of MOS transistor T1.

FIG. 1Bis an electric circuit diagram corresponding to the association illustrated inFIG. 1Aof a MOS transistor formed in an SOI-type layer and of a field-effect turn-on thyristor Th1of protection against overvoltages.

When a positive overvoltage occurs between drain D1(anode A of the thyristor) and source S1(cathode K of the thyristor) of MOS transistor T1while it is not connected, as soon as the voltage of drain region15exceeds a given threshold, a conduction channel forms by field effect at the surface of turn-on region26of thyristor Th1. Thyristor Th1turns on, which protects MOS transistor T1.

To properly set the turn-on threshold of protection thyristor Th1, terminals PW and NW are preferably respectively connected to cathode K and to anode A of the thyristor. Similarly, the thickness and the nature of insulating layer5are selected to set this turn-on threshold to a value only slightly greater than normal transistor operating voltages. For example, if the normal transistor operating voltage is on the order of 1.5 V, the thyristor turn-on threshold may be on the order of 3 V.

When a positive overvoltage occurs between source S1and drain D1of MOS transistor T1, junction19between wells20and22turns on, which protects MOS transistor T1.

MOS transistor T1is protected in case of a positive or negative overvoltage between its drain and its source. In the case of a positive overvoltage, the thyristor protects the MOS transistor. In case of a negative overvoltage, the forward P-N junction between wells20and22protects the MOS transistor.

The different regions of the thyristor correspond to elements currently used in CMOS transistor and transistor-on-SOI manufacturing technologies. P-type well20and N-type well22respectively correspond to wells currently called PWell and NWell in the art. N-type doped regions23and25correspond to regions currently called N GP (“Ground Plane”) in the art, which are currently used to form the so-called back gate of dual-gate MOS transistors on SOI.

Thus, these different regions will for example have the following usual doping levels:for wells20and22: between 1016and 1017atoms/cm3;for regions23and25: between 1017and 1019atoms/cm3; andfor regions27and29: between 1019and 1021atoms/cm3.

An advantage of a device for protecting a MOS transistor against overvoltages of the type illustrated inFIGS. 1A and 1Bis that it may be manufactured by using steps currently used in a method for manufacturing an integrated circuit chip comprising CMOS transistors.

Another advantage of such a device for protecting a MOS transistor against overvoltages is that the assembly takes up a surface only slightly greater than that taken up by the transistor alone, since the protection device is partly located under the MOS transistor.

FIG. 2Ais a cross-section view schematically showing a variation of the device ofFIGS. 1A and 1B. In this variation, all the conductivity types of the regions and wells forming the thyristor are inverted. Each region of inverted conductivity type bears the same reference numeral as the corresponding region ofFIGS. 1A and 1B, preceded by 1.

In this variation, the field-effect control acts on the anode gate region of the thyristor and not on its cathode gate region.

Junction119between wells120and122is in front of source region13of MOS transistor T1.

In the shown example, region125extends under a portion of source region13of MOS transistor T1, from junction119between wells120and122under insulation region17. Region123extends at a distance from junction119, under an end of source region13of MOS transistor T1located on the side of gate9, under gate9, under drain region15, and under insulation region17. As shown, the length of source region13may be greater than that of drain region15so that this source region covers region126located between regions123and125.

Anode gate region126of the thyristor, located between regions123and125, is located under source region13of MOS transistor T1and is separated therefrom by insulating layer5.

An N-type buried layer121, extending at least under P-type well122, is preferably provided to insulate well122from the rest of substrate7.

FIG. 2Bis an electric circuit diagram corresponding to the association illustrated inFIG. 2Aof a MOS transistor formed in an SOI-type layer and of a field-effect turn-on thyristor Th2of protection against overvoltages.

Anode A and cathode K of protection thyristor Th2are respectively connected to drain D1and to source S1of MOS transistor T1.

When a positive overvoltage occurs between drain D1(anode A of the thyristor) and source S1(cathode K of the thyristor) of MOS transistor T1while said transistor is not connected, as soon as the voltage of source region13exceeds a given threshold (in absolute value), a conduction channel forms by field effect at the surface of turn-on region126of thyristor Th2. Thyristor Th2turns on, which protects MOS transistor T1.

FIG. 3is a cross-section view schematically showing a variation of the device ofFIG. 1A. The elements common with those ofFIG. 1Aare designated with the same reference numerals and will not be described again hereafter.

In this variation, N-type doped regions43and45, corresponding to regions23and25of the protection thyristor illustrated inFIG. 1A, separated by a portion26of well20located in front of a portion of drain region15of MOS transistor T1, extend under MOS transistor T1and insulation region17, and beyond insulation region17. Cathode contact region47and anode region49of the protection thyristor, respectively corresponding to cathode contact region27and to anode region29of the thyristor illustrated inFIG. 1A, are located partly above substrate7, on either side of MOS transistor T1surrounded with insulation region17.

To form cathode contact region47and anode region49of the protection thyristor, layers3and5have been partially removed to reach the upper surface of substrate7. The epitaxy has for example then been resumed from the upper surface of substrate7to the upper level of semiconductor layer3.

In this variation, cathode contact region47extends above a portion of region43and is in contact therewith, next to insulation region17. Anode region49extends above a portion of region45and is in contact therewith, next to insulation region17.

In this variation, terminals PW and NW, which may be provided to bias wells20and22, correspond to regions formed above wells20and22. To form terminal PW, after partial removal of layers3and5, a region52, corresponding to region32ofFIG. 1A, has for example been formed by resuming the epitaxy above substrate7, at the same time as regions47and49. Terminal NW is for example formed similarly.

The thyristor formed by regions43,26,45, and49enables to protect MOS transistor T1against positive overvoltages capable of occurring between its drain D1and its source S1. To achieve this, drain D1and source S1of MOS transistor T1are respectively connected to anode A and to cathode K of the thyristor.

Specific embodiments of the present invention have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art.

In particular, relating to the variation illustrated inFIG. 3of a device for protecting a MOS transistor against overvoltages, the conductivity types of wells20,22, and of regions43,45,26,47,49, and52may all be inverted.

In the case of a device of the type illustrated inFIG. 3, wells20and22may be omitted. In this case, field-effect turn-on region26of the protection thyristor corresponds to a portion of P-type substrate7, located between N-type regions43and45, located under at least a portion of drain region15of MOS transistor T1and separated therefrom by insulating layer5.

Relating to the device illustrated inFIG. 2A, substrate7may of course be of type N.