A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

This application is based on Japanese patent application No. 2008-318098 the content of which is incorporated hereinto by reference.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

2. Related Art

General semiconductor device is configured to have semiconductor elements such as transistors formed on a semiconductor substrate, and to have a plurality of interconnect layer formed over the transistors. In the semiconductor device thus configured, a layout of the semiconductor elements formed on the semiconductor substrate is determined based on functions required for the semiconductor device.

In recent years, investigations have been made on forming thin-film transistors using compound semiconductor layers, as described in the literatures (1) to (6):

If the functions of the semiconductor device may be modified while leaving the layout of the semiconductor elements formed on the semiconductor substrate unchanged, now a plurality of types of semiconductor devices having different functions may be manufactured using the same semiconductor substrate. In this case, costs for manufacturing the semiconductor device may be saved. On the other hand, the interconnect layers over the semiconductor substrate have included only interconnects, capacitor elements, fuses and so forth, so that functions of the semiconductor device have been changeable only to a limited degree, simply by modifying configuration of the interconnect layer. It is, therefore, expected to largely modify the functions of the semiconductor devices without changing the layout of the semiconductor elements formed on the semiconductor substrate, if any element having new function may be formed in the interconnect layer.

SUMMARY

In one embodiment, there is provided a semiconductor device which includes:

a semiconductor substrate;

a first interconnect layer which includes an insulating layer formed over the semiconductor substrate, and a first interconnect filled in a surficial portion of the insulating layer;

a semiconductor layer positioned over the first interconnect layer;

a gate insulating film positioned over or below the semiconductor layer; and

a gate electrode positioned on the opposite side of said semiconductor layer while placing the gate insulating film in between.

According to the present invention, an element which has a semiconductor layer, a gate insulating film, and a gate electrode is provided in the interconnect layer. The element functions typically as a transistor (switching element) or a memory element. Accordingly, an element having a new function may be provided to the interconnect layer, and thereby the functions of the semiconductor device may be modified to a large degree, without changing the layout of the semiconductor elements formed on the semiconductor substrate.

In another embodiment, there is provided also a method of manufacturing a semiconductor device which includes:

forming, over a semiconductor substrate, a first interconnect layer which includes an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer;

forming, over the first interconnect layer, a gate insulating film which is positioned over the first interconnect;

forming a semiconductor layer over the gate insulating film; and

forming source-and-drain regions in the semiconductor layer.

In another embodiment, there is provided still also a method of manufacturing a semiconductor device which includes:

forming, over a semiconductor substrate, a first interconnect layer which includes an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer;

forming a semiconductor layer over the first interconnect layer;

forming a gate insulating film over the semiconductor layer;

forming a gate electrode over the gate insulating film; and

forming source-and-drain regions in the semiconductor layer.

According to the present invention, an element having a new function may be provided to the interconnect layer, and thereby the functions of the semiconductor device may be modified to a large degree, without changing the layout of the semiconductor elements formed on the semiconductor substrate.

DETAILED DESCRIPTION

Embodiments of the present invention will be explained below, referring to the attached drawings. Note that any similar constituents will be given with the same reference numerals or symbols in all drawings, and explanations therefor will not be repeated.

FIG. 2is a sectional view illustrating a semiconductor device of a first embodiment.FIG. 1is an enlarged sectional view illustrating an essential portion of the configuration illustrated inFIG. 2, and more specifically, a configuration of a semiconductor element200owned by a semiconductor device illustrated inFIG. 2.FIG. 3is a plan view illustrating a planar layout of the semiconductor element200.

As illustrated inFIG. 2, the semiconductor device has a semiconductor substrate100, a first interconnect layer150, and a semiconductor element200. The first interconnect layer150has an insulating layer156formed over the semiconductor substrate100, and a first interconnect154filled in a surficial portion of the insulating layer156.

As illustrated inFIG. 1, the semiconductor element200has a semiconductor layer220, a gate insulating film160, and a gate electrode210. The semiconductor layer220is positioned over the first interconnect layer150. The gate insulating film160is positioned over or below the semiconductor layer220. The gate electrode210is positioned on the opposite side of the semiconductor layer220while placing the gate insulating film160in between. The semiconductor element200functions as a transistor.

In this embodiment, the gate insulating film160is positioned over the first interconnect layer150. In other words, the gate insulating film160is positioned between the first interconnect layer150and the semiconductor layer220. The gate electrode210is formed in the same layer with the first interconnect154. The first interconnect154and the gate electrode210are typically composed of a copper interconnect, and are filled in the insulating layer156by damascene process. The width of the gate electrode210is typically 50 nm or wider and 500 nm or narrower.

The insulating layer156is typically composed of a low-k insulating layer having a dielectric constant smaller than that of silicon oxide (for example, a dielectric constant of equal to or smaller than 2.7). The low-k insulating layer may be configured typically by a carbon-containing film such as SiOC(H) film or SiLK (registered trademark); HSQ (hydrogen silsesquioxane) film; MHSQ (methylated hydrogen silsesquioxane) film; MSQ (methyl silsesquioxane) film; or porous film of any of these materials.

The semiconductor layer220typically has a thickness of 50 nm or larger and 300 nm or smaller. The semiconductor layer220typically has an oxide semiconductor layer such as InGaZnO (IGZO) or ZnO layer. The semiconductor layer220may have a single-layer structure composed of the above-described oxide semiconductor layer, or may have a stacked structure of the above-described oxide semiconductor layer with other layer(s). The latter may be exemplified by a stacked film expressed by IGZO/Al2O3/IGZO/Al2O3. Alternatively, the semiconductor layer220may be a polysilicon layer or amorphous silicon layer. The semiconductor layer220is provided with source-and-drain regions222. For the case where the semiconductor layer220is an oxide semiconductor layer, the source-and-drain regions222may typically be formed by introducing oxygen vacancy, but may alternatively be formed by introducing an impurity. For the case where the semiconductor layer220is a polysilicon layer or amorphous silicon layer, the source-and-drain regions222may be formed by introducing an impurity. The width of the source-and-drain regions222is typically equal to or larger than 50 nm and equal to or smaller than 500 nm. The region of the semiconductor layer220which falls between the source-and-drain regions222, serves as a channel region224. The semiconductor conductivity type of the channel region224may be equal to those of the source-and-drain regions222.

Over the first interconnect layer150and the semiconductor layer220, an insulating layer170which configures a second interconnect layer is formed. The insulating layer170is typically composed of the above-described low-k insulating film. The gate insulating film160functions also as a diffusion blocking film, and is provided over the entire surface of the first interconnect layer150. The semiconductor layer220is formed over the gate insulating film160. The gate insulating film160, or the diffusion blocking film, is typically composed of a SiCN film, having a thickness of equal to or larger than 10 nm and equal to or smaller than 50 nm.

The insulating layer170has interconnects186,188(second interconnects) filled therein. The interconnects186are connected through vias184which are formed in the insulating layer170, to the source-and-drain regions222. In other words, the source-and-drain regions222of the semiconductor element200are electrically drawn out through the interconnects186which are formed in the interconnect layer over the semiconductor element200. The interconnect188is connected though a via189which is formed in the insulating layer170, to the first interconnect154. The vias184do not extend through the gate insulating film160, meanwhile the via189extends through the gate insulating film160. The vias184have a diameter larger than that of the via189. Each via184illustrated in this drawing is partially not aligned with the semiconductor layer220, but may alternatively be aligned therewith.

As illustrated inFIG. 2, a MOS transistor-type semiconductor element110is formed on the semiconductor substrate100. The semiconductor element110functions typically as a transistor or capacitor element, and has a gate insulating film112, a gate electrode114, and impurity diffused regions116which serve as the source-and-drain regions. Element-forming region having the semiconductor element110formed therein is electrically isolated by a device isolation film102. The semiconductor element110overlaps, at least in a portion thereof, with the semiconductor layer220in a plan view.

In the illustrated example in this drawing, a contact layer120and an interconnect layer130are formed between the first interconnect layer150and the semiconductor substrate100. The interconnect layer130is positioned over the contact layer120. The contact layer120has an insulating layer124and contacts122, and the interconnect layer130has an insulating layer134and interconnects132. The interconnects132are connected through the contact122to the semiconductor element110. The interconnect132is connected through a via152which is formed in the insulating layer156, to the first interconnect154.

The insulating layer124is typically composed of a silicon oxide layer, and the insulating layer134is typically composed of the above-described, low-k insulating layer. Between the interconnect layer130and the first interconnect layer150, there is formed a diffusion blocking film140such as a SiCN film. The semiconductor element110is electrically connected to the semiconductor element200.

Next, a method of manufacturing a semiconductor device according to this embodiment will be explained referring toFIGS. 1,2,4A,4B and5.FIGS. 4A and 4BandFIG. 5are drawings illustrating the portion corresponded toFIG. 1, in the semiconductor device illustrated inFIG. 2.

First, as illustrated inFIG. 2, the device isolation film102is formed in the semiconductor substrate100, and then the gate insulating film112, the gate electrode114, and the impurity diffused regions116are formed in this order. Next, the contact layer120, the interconnect layer130, and the diffusion blocking film140are formed.

Next, as illustrated inFIG. 4A, the insulating layer156is formed on the diffusion blocking film140. Next, the via152, the first interconnect154, and the gate electrode210are filled in the insulating layer156by single damascene process or dual damascene process. The first interconnect layer150is formed in this way.

Next, as illustrated inFIG. 4B, the gate insulating film160is formed on the first insulating layer150typically by plasma CVD. Since the gate insulating film160functions also as the diffusion blocking film as described in the above, so that the gate insulating film160is formed over the entire surface of the first insulating layer150.

Next, the semiconductor layer220is formed over the entire surface of the gate insulating film160, and the semiconductor layer220is then selectively removed by etching using a mask film. For the case where the semiconductor layer220contains an oxide semiconductor layer composed of ZnO, InGaZnO or the like, the semiconductor layer220may be formed typically by sputtering. In this case, the semiconductor substrate100is heated at a temperature of 400° C. or lower. For the case where the semiconductor layer220is a polysilicon layer or amorphous silicon layer, the semiconductor layer220may be formed typically by plasma CVD.

Next, as illustrated inFIG. 5, a mask pattern50is formed on the semiconductor layer220, and the semiconductor layer220is treated using the mask pattern50as a mask. The source-and-drain regions222are formed in the semiconductor layer220in this way. The treatment which takes place herein may be exemplified by a method of treating the semiconductor layer220with a reductive plasma (hydrogen plasma, for example), and a method of treating the semiconductor layer220with a nitrogen-containing plasma (ammonia plasma, for example). The former treatment gives the source-and-drain regions222in a form of an oxygen vacancy region, meanwhile the latter treatment causes selective introduction of nitrogen into the semiconductor layer220to give the source-and-drain regions222.

Now referring back toFIG. 1, the mask pattern50is then removed. Next, the insulating layer170is formed over the gate insulating film160and the semiconductor layer220, and the vias184,189and the interconnects186,188are formed in the insulating layer170. The vias184,189herein are formed in different processes. More specifically, the vias184are formed so as not to extend through the gate insulating film160, meanwhile the via189is formed so as to extend through the gate insulating film160.

It is now preferable to form a barrier film (not illustrated) between the vias184,189and the insulating layer170, between the interconnects186,188and the insulating layer170, and between the vias184and the source-and-drain regions222. The barrier film is a stacked film typically having a Ta film and a TaN film stacked in this order. If the semiconductor layer220is an oxide semiconductor layer, then a Ru film, MoN film, or W film may preliminarily be formed under the Ta film. In this case, the barrier film may be prevented from elevating in the resistivity, even if a portion thereof, brought into contact with the semiconductor layer220, is oxidized.

Next, operations and effects of this embodiment will be explained. According to this embodiment, the semiconductor element200may be formed in the interconnect layer. The semiconductor element200functions as a transistor which is categorized as a switching element. As a consequence, functions of the semiconductor element formed on the semiconductor substrate may be modified to a large degree, without changing the layout of the semiconductor elements formed on the semiconductor substrate.

The gate insulating film160is also given with a function of a diffusion blocking film. It is, therefore, no more necessary to separately provide the gate insulating film160and the diffusion blocking film, and thereby the semiconductor device may be prevented from being complicated in the configuration, and from increasing in the cost of manufacturing.

Since the gate electrode210of the semiconductor element200is provided in the same layer with the first interconnect154in the first interconnect layer150, so that the gate electrode210and the first interconnect154may be formed in the same process. Accordingly, the semiconductor device may be prevented from increasing in the cost of manufacturing.

For the case where the semiconductor layer220is configured by an oxide semiconductor layer, the temperature of heating of the semiconductor substrate100when the semiconductor layer220is formed may be set to 400° C. or lower, so that the interconnect layer positioned below the semiconductor layer220may be prevented from being thermally damaged. Accordingly, the low-k insulating film and the copper interconnect may be used for composing the interconnect layer.

In a plan view, the semiconductor elements110,200overlap with each other at least in a portion thereof. The degree of integration of the semiconductor device may therefore be elevated.

Since, the vias184,189are formed in separate processes, so that the gate insulating film160may be allowed to function as an etching stopper, when the vias184are formed, and thereby the vias184may be prevented from being excessively deepened.

FIG. 6is a sectional view illustrating a semiconductor device according to a second embodiment, and corresponds toFIG. 1in the first embodiment. The semiconductor device of this embodiment is similar to that of the first embodiment, except that the vias184,189are formed in the same process. More specifically, for the case where portions of the vias184fall outside the semiconductor layer220, such portions fallen outside extend through the gate insulating film160.

Also in this embodiment, effects similar to those in the first embodiment may be obtained, except that the gate insulating film160is not allowed to function as an etching stopper when the vias184are formed.

FIG. 7is a sectional view illustrating a semiconductor device according to a third embodiment, and corresponds toFIG. 1in the first embodiment. The semiconductor device of this embodiment is configured similarly to the semiconductor device of the first embodiment, except that a trapping film230and a back-gate electrode240are formed over the semiconductor layer220. The trapping film230and the back-gate electrode240overlap with the channel region224of the semiconductor layer220in a plan view. The semiconductor conductivity type of the channel region224may be equal to those of the source-and-drain regions222. Note that, in the example illustrated in this drawing, a mask pattern54, which was used when the back-gate electrode240was formed, remains unremoved on the back-gate electrode. The mask pattern54herein is typically a silicon oxide film, but may alternatively be a silicon nitride film or a silicon carbonitride film. A contact (not illustrated) connected to the back-gate electrode240extends through the mask pattern54.

The trapping film230is typically a SiN film, and has a thickness of 5 nm or larger and 50 nm or smaller. The back-gate electrode240is typically a TiN film. The back-gate electrode240is electrically connected typically through an unillustrated contact to an interconnect (not illustrated) which is formed in the same layer with the interconnects186,188.

In this embodiment, the semiconductor element200functions not only as a transistor, but also as a memory element. In the latter case, the semiconductor element110may be a part of a selector circuit of the semiconductor element200.

FIG. 8is a drawing explaining a principle of function of the semiconductor element200as a memory element. For the case where the semiconductor element200is allowed to function as a memory element, it may be acceptable enough to allow the trapping film230to be injected with (or to trap) electric charge (holes, for example), and to erase the trapped charge. This is because the threshold voltage (Vth) of the semiconductor element200, which is made function as a transistor, varies depending on the presence or absence of electric charge trapped in the trapping film230.

More specifically, voltage (VBG) of the back-gate electrode240at the initial state (having no information written in the semiconductor element200) is set to 0. In the process of write operation of information into the semiconductor element200, a negative voltage (−2.5 V, for example) is applied to the back-gate electrode240, so as to adjust the voltage (VG) of the gate electrode210to 0. Holes are then injected to the trapping film230, so as to shift the threshold voltage of the semiconductor element200to the negative side.

On the other hand, in the process of erasure of information from the semiconductor element200, a positive voltage (+2.5 V, for example) is applied to the back-gate electrode240, and a negative voltage (−2.5 V, for example) is applied to the gate electrode210. The holes, having been injected into the trapping film230are then erased, and the threshold voltage of the semiconductor element200returns back to the initial value.

Also for the case where the semiconductor element200is used as a transistor, not as a memory element, the threshold voltage of the transistor may be modified by injecting electric charge into the trapping film230.

Next, a method of manufacturing a semiconductor device according to this embodiment will be explained referring toFIGS. 9A,9B andFIGS. 10A,10B. The processes up to the formation of the gate insulating film160in the method of manufacturing a semiconductor device of this embodiment are same as those in the first embodiment, so that explanations for the processes will not be repeated.

As illustrated inFIG. 9A, after the gate insulating film160is formed, first the semiconductor layer220is formed over the gate insulating film160. Next, over the semiconductor layer220, the trapping film230and the back-gate electrode240are formed. The trapping film230is formed typically by plasma CVD, and the back-gate electrode240is formed typically by sputtering.

Next, as illustrated inFIG. 9B, a mask pattern52is formed on the back-gate electrode240. The back-gate electrode240, the trapping film230, and the semiconductor layer220are then etched by dry etching, using the mask pattern52as a mask. By this process, the semiconductor layer220is patterned to give the semiconductor element200. Geometries of the back-gate electrode240and the trapping film230are nearly equal to that of the semiconductor layer220.

Next, as illustrated inFIG. 10A, the mask pattern52is removed. The mask pattern54is then formed on the back-gate electrode240. The mask pattern54is formed typically by forming a silicon oxide film, and then selectively removing the silicon oxide film. Alternatively, the mask pattern54may be formed by selectively removing any other film such as a silicon nitride film or silicon carbonitride film. Next, the trapping film230and the back-gate electrode240are etched by dry etching, using the mask pattern54as a mask. By this process, the trapping film230and the back-gate electrode240may be patterned to give the semiconductor element200.

Thereafter, as illustrated inFIG. 10B, the semiconductor layer220is treated using the back-gate electrode240as a mask. The source-and-drain regions222are consequently formed in the semiconductor layer220. The treatment took place herein is the same as described in the first embodiment.

Next, the insulating layer170illustrated inFIG. 7is formed. The processes thereafter are same with those described in the first embodiment, and will not repetitively be explained.

Also in this embodiment, effects similar to those in the first embodiment may be obtained. The semiconductor element200may be used again as a memory element.

FIG. 11is a sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment, and corresponds toFIG. 7in the third embodiment. The semiconductor device is configured similarly to the semiconductor device of the third embodiment, except that the gate electrode210is not provided, and that a gate insulating film232and a gate electrode242are positioned over the semiconductor layer220.

The gate insulating film232is configured similarly to the trapping film230in the third embodiment, and the gate electrode242is configured similarly to the back-gate electrode240in the third embodiment.

On the first interconnect layer150, a diffusion blocking film162is provided. The configuration of the diffusion blocking film162is same as that of the gate insulating film160in the third embodiment.

A method of manufacturing a semiconductor device of this embodiment is same as the method of manufacturing a semiconductor device of the third embodiment, except that the gate electrode210is not formed when the interconnect154is formed.

Also by this embodiment, the semiconductor element200may be formed in the interconnect layer. As a consequence, functions of the semiconductor element formed on the semiconductor substrate may be modified to a large degree, without changing the layout of the semiconductor elements formed on the semiconductor substrate.

For the case where the semiconductor layer220is configured by an oxide semiconductor layer, the temperature of heating of the semiconductor substrate100when the semiconductor layer220is formed may be set to 400° C. or lower, so that the interconnect layer positioned below the semiconductor layer220may be prevented from being thermally damaged.

In a plan view, the semiconductor elements110,200overlap with each other at least in a portion thereof. The degree of integration of the semiconductor device may therefore be elevated.

Since, the vias184,189are formed in separate processes, so that the gate insulating film160may be allowed to function as an etching stopper, when the vias184are formed, and thereby the vias184may be prevented from being excessively deepened.

The embodiments of the present invention have been described referring to the attached drawings merely as examples of the present invention, without being precluded from adopting any configurations other than those described in the above. For example, the first interconnect154and the gate electrode210may preferably be composed of copper interconnects, and may preferably be filled in the insulating layer156by the damascene process, whereas other interconnects positioned in other interconnect layers, for example at least either the interconnect132, or the interconnects186,188, may be composed of any other metal material (Al or Al alloy, for example). In this case, also the vias152,184,189are formed using a metal other than copper. For example, the interconnects132,154, the via152, and gate electrode210may be composed of copper or copper alloy, and the interconnects186,188and vias184,189which are positioned in the upper layers of the semiconductor element200may be composed of Al or Al alloy.