Integration type and converter and device including same

An integration type A/D converter in which a dynamic range is enlarged while keeping a simple circuit configuration is provided. Offset potential of an integrator is to be variable. Specifically, offset potential in proportion to input potential is supplied to the integrator. Since an operation point of the integrator is changed in accordance with the input potential, a dynamic range can be enlarged. Further, reference potential input to the integrator in discharging is to be variable. Specifically, reference potential having a constant difference from the offset potential is input to the integrator. Accordingly, time necessary for discharging and the input potential are in proportion, so that a simple circuit configuration which is one feature of the integration type ADC can be maintained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integration type A/D converter (analog-to-digital converter). Further, the present invention relates to a semiconductor device including the A/D converter and an electronic device.

2. Description of the Related Art

The physical quantity of sound, light, heat, power, an electric field, and a magnetic field in the natural world can be expressed as an analog parameter. On the other hand, in the fields of measurement, control, communication, and the like, digitalization of data processing has been advanced. A digital camera or the like is a good example of consumer-electronic devices. When the physical quantity which is treated as the analog quantity originally is treated as the digital quantity, an A/D converter (an analog-to-digital converter, hereinafter referred to as an ADC) serves as an interface between analog data and digital data. That is, the ADC converts analog data to digital data. When various physical quantities as described above in the natural world are processed as data, the ADC is necessary in many cases. Therefore, the ADC can be applied to various fields and is very important.

There are various types of ADCs, typically, a successive-approximation type, a parallel-comparison type (also referred to as a flash type), a ΔΣ type (also referred to as a ΣΔ type), an integration type, and the like.

The integration type ADC has a low conversion rate compared to other types but a simple circuit configuration, and thus can be manufactured at low cost and is not easily influenced by noise. Therefore, the integration type ADC is used in noisy environment, for applications which do not require a high update rate, or the like.

The operating principle of a dual slope type ADC, which is one kind of integration type ADCs and often used, will be described with reference toFIGS. 2 and 3.FIG. 2illustrates a main portion of a circuit constituting the dual slope type ADC. The dual slope type ADC includes an integrator154having an operational amplifier151, a resistor152, and a capacitor153; a first switch156which initializes output potential Voutof the integrator154; a second switch158which serves as a charging switch for inputting input potential Vinto the integrator154; and a third switch160which serves as a discharging switch for inputting reference potential Vrefinto the integrator154.

Note that “potential” denotes relative potential energy when electric potential energy of a grounded electric node is set to be 0 here. This is also applied to the following description. However, it is sufficient that potential at an electric node which is a reference of an entire circuit can be clearly determined. It is not always necessary to set ground potential to be 0, and the spirit of the present invention hereinafter described is not limited thereto, either.

Operation of the conventional dual slope type ADC illustrated inFIG. 2will be described hereinafter. First, the first switch156is turned on to cause a short circuit between two terminals of the capacitor153, and the integrator154is initialized so that output potential Voutbecomes offset potential Voffset. Next, the first switch156is turned off and then the second switch158is turned on, and input signals are accumulated in the integrator154for a certain period of time, so that electric power is stored there. Finally, the second switch158is turned off and then the third switch160is turned on, and electric power is released so that the output potential Voutof the integrator154returns to a level in initialization, i.e., the offset potential Voffset. By counting a period for discharge (discharging period), A/D conversion can be performed.

The discharging period is counted as follows: a count-up operation is started at a time when the third switch160is turned on, and the count-up operation is finished at a time when the output potential Voutis equal to the offset potential Voffset. Known counter circuits may be used for the count-up operation. Since the count-up operation is started at 0, a value obtained by multiplying digital data stored in the counter circuit in completion of the count-up operation by a clock cycle becomes a discharging period. That is, reset signals and clock signals for a certain period of time are used to control the counter circuit. In addition, in order to detect a point at which the output potential Voutis equal to the offset potential Voffset, a known comparator circuit which is not illustrated here may be used. That is, the output potential Voutis input to one of two input terminals of the comparator circuit and the offset potential Voffsetis input to the other. Besides, a known circuit which combines logical gates may be used to control the first to third switches.

FIG. 3shows a change of the output potential Voutof the integrator154with time. The x axis represents time and the y axis represents the output potential Voutof the integrator154. In this case, the case is shown in which input voltage Vin1(a difference between the input potential Vinand the offset potential Voffset) and input voltage Vin2which is twice as large as Vin1(a difference between the input potential Vinand the offset potential Voffset) are input. The output potential Voutof the integrator154at a start of the charging period T1is equal to the offset potential Voffsetregardless of a value of the input voltage Vin1or the input voltage Vin2. In the charging period T1, the output potential Voutof the integrator154changes in accordance with a level of the input voltage Vin1or the input voltage Vin2in a linear manner. Therefore, output voltage Vout1(a difference between the output potential Voutand the offset potential Voffset) and output voltage Vout2(a difference between the output potential Voutand the offset potential Voffset) of the integrator154in completion of the charging period T1have a level which has changed in accordance with the input voltage Vin1or the input voltage Vin2in a linear manner. Next, reference voltage having opposite polarity to the input voltage Vin1or the input voltage Vin2is input to the integrator154, so that the output potential Voutof the integrator154is changed with a slope of opposite polarity to that in charging. At this time, since the reference voltage is constant, a slope of the output potential Voutchanging with time is constant regardless of the input voltage Vin1or the input voltage Vin2in charging. As a result, a period T21or a period T22, which is required until the output potential Voutof the integrator154returns to a level in initialization, is varied in accordance with a level of the input voltage Vin1or the input voltage Vin2in a linear manner.

Note that in the example ofFIG. 2, when the input voltage is Vin1, the output voltage and the discharging period are Vout1and T21, respectively. Further, when the input voltage is Vin2, the output voltage and the discharging period are Vout2and T22, respectively.

In general, the following equation (1) is obtained using the charging period T1, the discharging period T2, the input potential Vin, the reference potential Vref, and the offset potential Voffset.
(Vin−Voffset)*T1+(Vref−Voffset)*T2=0  (1)

Note that the integration type ADC is generally operated under the condition of Voffset=0, Vin>0, and Vref<0. However, the present invention is not limited thereto as long as (Vin−Voffset) and (Vref−Voffset) have opposite polarity, i.e., (Vin−Voffset)>0 and (Vref−Voffset)<0, or (Vin−Voffset)<0 and (Vref−Voffset)>0.

In order to operate the integration type ADC normally, it is necessary that the integrator154inside the ADC operates correctly. Specifically, the condition under which the output potential Voutof the integrator154is not saturated during operation is a condition under which the integration type ADC operates normally. That is, the condition under which the integration type ADC operates normally can be expressed by the following equation (2).

In the above equation, R represents resistance of the resistor152included in the integrator154, C represents capacitance of the capacitor153included in the integrator154, Vlimitrepresents the limit of the output potential which can operate the integrator154correctly, the left-hand side of the equation represents a change in output potential Voutof the integrator154in the charging period T1, and the right-hand side represents a range of a change in output potential Voutof the integrator154. In the case of Vin>Voffset, Vlimit<Voffset, and Vlimitrepresents the lower limit of the output potential in the range in which the integrator154can be operated correctly. Hereinafter, the case of Vin>Voffsetwill be described but the description also applies to the case of Vin<Voffset.

When the equation (2) is solved for Vin, the following equation (3) is obtained.

In the equation (3), the range of values of the input potential Vin(hereinafter referred to as a dynamic range) is limited by various parameters which determine the operation of the integrator. Accordingly, various methods have been provided to enlarge the dynamic range (e.g., Reference 1: Japanese Patent No. 3100457 and Reference 2: Japanese Patent No. 2550889).

SUMMARY OF THE INVENTION

As one method to enlarge the dynamic range, there is a method in which a time constant (R×C) of the integrator is changed depending on the input. However, in this method, the amount of hardware (an area of a circuit formed) is increased. Further, a technique called multi-sloping is known. Multi-sloping is a technique in which a power source that is neither an input potential nor a reference potential is prepared to compensate for the quantity of electric charge transmitted to the integrator, so that effective voltage amplitude larger than the physical limit of the integrator is obtained. However, when multi-sloping is used, there have been problems in that a new reference power source, switch, and the like are necessary and a peripheral circuit which controls the integrator gets complicated.

As another method, the charging period T1may be shortened; however, since resolving power that is a performance indicator of the ADC is influenced, there is a limitation.

Alternatively, by shortening a clock cycle for counting the discharging period T2, resolving power can be maintained theoretically while the charging period T1is shortened. However, the clock cycle is limited by the response speed of the peripheral circuit. Further, when the clock cycle is shortened, power consumption is increased; therefore, low power consumption cannot be easily achieved.

In view of the above problems, the present invention provides an integration type ADC in which a dynamic range is enlarged while keeping a simple circuit configuration. Specifically, the present invention focuses on a point that the above problems are caused by constant offset potential. In the integration type ADC, the output potential of the integrator returns to a level in initialization after charging operation and discharging operation. However, since offset potential Voffsetthat is an initialization potential at this time is fixed (Voffsetis constant), it is difficult to enlarge the dynamic range.

In an analog-to-digital converter of the present invention, offset potential Voffsetis to be variable. Specifically, with the use of offset potential Voffsetrepresented by the following equation (4), offset potential Voffsetin accordance with input potential Vinis supplied to the integrator.
Voffset=k*Vin(4)

Note that k is a constant where 0<k<1. Further, reference potential Vrefrepresented by the following equation (5) is used.
Voffset−Vref=Vconst(5)

Note that Vconstis a constant. The equation (1) is represented by the following equation (6), and an output period T2is in proportion to the input potential Vin.

Note that in this specification, a MOSFET (metal oxide silicon field effect transistor) and a TFT (thin film transistor), which are one kind of transistors, are not particularly distinguished. Therefore, the description “transistor” may also mean a TFT. Similarly, the description “TFT” may also mean a transistor.

In this specification, a semiconductor device means a device having a transistor and also includes a display device and the like.

With the use of the present invention, in the integration type ADC, a dynamic range can be enlarged compared to a conventional type, while keeping a simple circuit configuration. Further, various parameters which determine operation of the integration type ADC can be more freely set. Consequently, resolving power can be improved in the case of keeping a dynamic range. Further, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced.

Furthermore, an output period T2is a linear function of input potential Vinin the conventional type ADC; however, according to the present invention, the output period T2is in proportion to the input potential Vinregardless of offset potential Voffset. Accordingly, it is not necessary to consider the offset voltage in input and output, so that the output period T2is not varied and digital data that is obtained can be more precise.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiment modes of the present invention will be described with reference to the accompanying drawings. Note that the present invention can be implemented in various modes, and it is easily understood by those skilled in the art that modes and details thereof can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiment modes.

This embodiment mode will describe an example of a configuration of an analog-to-digital converter (ADC) according to the present invention with reference toFIG. 1.

FIG. 1is a circuit diagram illustrating an example of a configuration of an ADC according to the present invention. The ADC shown inFIG. 1includes an integrator104having an operational amplifier101, a resistor102, and a capacitor103; a first switch106which initializes output potential Voutof the integrator104; a second switch108which serves as a charging switch for inputting input potential Vininto the integrator104; a third switch110which serves as a discharging switch for inputting reference potential Vrefinto the integrator104; a multiplier circuit112for generating offset potential Voffsetfrom the input potential Vin; and a subtraction circuit113for generating reference potential Vreffrom the offset potential Voffset. An input potential Vinterminal and a reference potential Vrefterminal are connected to one terminal of the resistor102through the second switch108and the third switch110, respectively. The other terminal of the resistor102is connected to an inverted input terminal (−) of the operational amplifier101. The capacitor103is connected between the inverted input terminal (−) and an output terminal of the operational amplifier101.

In order to initialize the output potential Voutof the operation amplifier101, the first switch106is connected between two terminals of the capacitor103. The input potential Vinis input through the second switch108to the integrator104and the multiplier circuit112at the same time, and the offset potential Voffsetis output from the multiplier circuit112. Note that the offset potential Voffsetand the input potential Vinsatisfy the following equation (4).
Voffset=k*Vin(4)

The offset potential Voffsetis input to a non-inverted input terminal (+) of the operational amplifier101and the subtraction circuit113at the same time, and the reference potential Vrefis output from the subtraction circuit113. Note that the offset potential Voffsetand the reference potential Vrefsatisfy the following equation (5).
Voffset−Vref=Vconst(5)

The integration type ADC of the present invention illustrated inFIG. 1is greatly different from the conventional integration type ADC illustrated inFIG. 2in that it has the multiplier circuit112and the subtraction circuit113. In the conventional integration type ADC illustrated inFIG. 2, the offset potential Voffsetand the reference potential Vrefare fixed (have constant values); however, in the ADC illustrated inFIG. 1, the offset potential Voffsetand the reference potential Vrefare changed in accordance with the input potential Vin. Other than that, the ADC of the present invention operates in a similar manner to the conventional integration type ADC. Therefore, an input-output relation as represented by the following equation (6) is obtained.

FIG. 4illustrates an example of a circuit configuration of the multiplier circuit112. A resistor171and a resistor172are connected in series in the multiplier circuit112. The input potential Vinis input to series resistance thereof, and the offset potential Voffsetis taken out from a part where the resistors171and172are connected. At this time, by adjusting a voltage division ratio based on each resistance of the resistors171and172, a proportionality constant k of the equation (4) is determined. In this example, a proportionality constant k is represented by the following equation.

Note that R1and R2represent resistance of the resistors171and172, respectively.

FIGS. 5A and 5Billustrate examples of a circuit configuration of the subtraction circuit113. Here, the case where the input potential Vin, the offset potential Voffset, and the reference potential Vrefsatisfy Vin>Voffset>Vrefwill be described.FIG. 5Aillustrates an example using a source follower. The circuit illustrated inFIG. 5Aincludes a first transistor201(n-type) serving as an amplifying transistor and a second transistor202(n-type) serving as a constant current source load. A drain electrode of the first transistor201is connected to power source potential VDD, a source electrode of the second transistor202is connected to ground potential, and a source electrode of the first transistor201and a drain electrode of the second transistor202are connected to the reference potential Vrefand an output terminal205A. When the offset potential Voffsetis input to a gate electrode204A of the first transistor201in a state in which bias potential Vbiasis input to a gate electrode203of the second transistor202, potential of the output terminal205A is set in accordance with the offset potential Voffsetand the bias potential Vbias. For example, when electric characteristics (DC characteristics) of the first transistor201and the second transistor202are equal to each other, there is a relation of Vref=Voffset−Vbias. In this manner, a relation of the equation (5) is obtained. However, Vconst=Vbiasin this embodiment mode. In order to operate the above circuit normally, it is necessary to operate the first transistor201and the second transistor202in a saturation region. When the first transistor201and the second transistor202are enhancement type, it is enough to satisfy VDD>Voffset>Vref>Vbias.

FIG. 5Billustrates an example using a voltage follower. The circuit illustrated inFIG. 5Bincludes a voltage follower206, a first transistor207(p-type) connected as a diode, and a second transistor208(n-type) which performs reset to initialize input potential of the voltage follower206. Offset potential Voffsetis connected to a source electrode204B of the first transistor207, and a drain electrode and a gate electrode thereof are connected to an input terminal of the voltage follower206. Further, the input terminal of the voltage follower206is connected to a drain electrode of the second transistor208. First, potential input to a gate electrode209of the second transistor208is controlled as appropriate, so that input potential of the voltage follower206is initialized. When the second transistor208is turned on, current flows between the source electrode and the drain electrode of each of the first transistor207and the second transistor208. After that, the second transistor208is turned off. After the second transistor208is turned off, current flows continuously through the first transistor207until the channel is off. As a result, input potential of the voltage follower206becomes (Voffset−|Vth|). Note that Vthrepresents threshold voltage of the first transistor207where Vth<0. In other words, the first transistor207is to be enhancement type. The potential Vrefoutput from the output terminal205B of the voltage follower206with some delay time becomes (Voffset−|Vth|). In this manner, the equation (5) is achieved. Note that Vconst=|Vth| in this embodiment mode.

With the use of the present invention, in the integration type ADC, a dynamic range can be enlarged compared to a conventional type, while keeping a simple circuit configuration. Therefore, various parameters which determine operation of the integration type ADC can be more freely set. Consequently, resolving power can be improved in the case of keeping a dynamic range. In addition, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced.

In addition, an output period T2is a linear function of the input potential Vinin the conventional type ADC; however, according to the present invention, the output period T2is in proportion to the input potential Vinregardless of the offset potential Voffset. Accordingly, it is not necessary to consider the offset voltage, so that the output period T2is not varied and digital data that is obtained can be more precise.

This embodiment mode will describe a configuration of a semiconductor device capable of wireless communication and having the ADC described in Embodiment Mode 1.FIG. 6is a block diagram of the semiconductor device capable of wireless communication. The semiconductor device capable of wireless communication illustrated inFIG. 6transmits and receives data with radio signals using a reader/writer314.

A semiconductor device300illustrated inFIG. 6mainly includes a signal transmission/reception portion301, a signal intensity detection portion302, and a signal arithmetic portion303. The signal transmission/reception portion301includes an antenna304, a rectifier circuit305, a demodulation circuit306, and a modulation circuit307. The signal intensity detection portion302includes a rectifier circuit308, a power source circuit309, and an ADC310.

The antenna304receives electromagnetic waves sent from the reader/writer and generates AC induced voltage. This induced voltage serves as electric power for the semiconductor device300and includes data sent from the reader/writer.

Note that the shape of the antenna304which can be used for the semiconductor device300is not particularly limited. Therefore, an electromagnetic coupling method, an electromagnetic induction method, an electromagnetic wave method, and the like can be used for a method for transmitting and receiving signals in the semiconductor device300. The transmission method may be selected as appropriate by a practitioner in consideration of application use, and an antenna having optimal length and shape may be provided in accordance with the transmission method. In the present invention, as a transmission method of signals, an electromagnetic induction method with a communication frequency of 13.56 MHz is preferably used.

In the case of employing an electromagnetic coupling method or an electromagnetic induction method (e.g., a 13.56 MHz band) as the transmission method, electromagnetic induction caused by a change in magnetic field density is used. Therefore, a conductive film functioning as an antenna is formed into an annular shape (e.g., a loop antenna) or a spiral shape (e.g., a spiral antenna).

In the case of employing a microwave method (e.g., a UHF band (860 to 960 MHz band), a 2.45 GHz band, or the like) which is one kind of electromagnetic wave method as the transmission method, a length or a shape of the conductive film functioning as an antenna may be appropriately set in consideration of a wavelength of an electromagnetic wave used for signal transmission. The conductive film functioning as an antenna can be formed into, for example, a linear shape (e.g., a dipole antenna), a flat shape (e.g., a patch antenna), and the like. The shape of the conductive film functioning as an antenna is not limited to a linear shape, and the conductive film functioning as an antenna may be formed into a curved-line shape, a meander shape, or a combination thereof, in consideration of a wavelength of an electromagnetic wave.

Here, examples of shapes of the antenna304are shown inFIGS. 7A to 7E. An antenna321may be provided all around a chip320provided with a signal processing circuit (FIG. 7A). Alternatively, a thin antenna323may be provided so as to be around a chip322provided with a signal processing circuit (FIG. 7B). Further alternatively, an antenna325may have a shape for receiving high-frequency electromagnetic waves with respect to a chip324provided with a signal processing circuit (FIG. 7C). Furthermore, an antenna327may have a shape which is 180° omnidirectional (capable of receiving signals from any direction) with respect to a chip326provided with a signal processing circuit (FIG. 7D). Further, an antenna329may have a shape which is extended to be long like a stick with respect to a chip328provided with a signal processing circuit (FIG. 7E). As the antenna304, antennas with these shapes may be used in combination.

InFIGS. 7A to 7E, there is no particular limitation on a connection method of the chip320or the like provided with the signal processing circuit to the antenna321or the like, and a structure which can transmit and receive signals between the chip and the antenna may be used.FIG. 7Ais given as an example, and a method in which the antenna321is connected to the chip320provided with the signal processing circuit by wire bonding connection or bump connection, or a method in which a part of the chip is made to function as an electrode and is attached to the antenna321may be employed. In this method, the chip320can be attached to the antenna321with the use of ACF (anisotropic conductive film). A structure in which the chip and the antenna are electrically connected to each other to enable transmission/reception of signals may be used. The length which is needed for the antenna depends on a frequency of signals which are received. For example, in the case where the frequency is 2.45 GHz, the length of antenna may be approximately 60 mm (½ wavelength) or approximately 30 mm (¼ wavelength).

The rectifier circuit305half-wave rectifies and smoothes signals received at the antenna304.

The demodulation circuit306demodulates the AC electric signal converted by the rectifier circuit305and supplies the demodulation signal to the signal arithmetic portion303.

The modulation circuit307applies load modulation to the antenna304based on the signals supplied from the signal arithmetic portion303.

In the signal transmission/reception portion301, a signal received at the antenna304is input to the rectifier circuit305. An output signal from the rectifier circuit305is input to the demodulation circuit306. An output signal from the demodulation circuit306is input to the signal arithmetic portion303, and information on individual identification of the semiconductor device300is output to the modulation circuit307. An output signal from the modulation circuit307is output to the reader/writer314outside through the antenna304.

The signal intensity detection portion302includes the rectifier circuit308, the power source circuit309, and the ADC310. The signal intensity detection portion302detects intensity of a signal received by the semiconductor device300.

The signal arithmetic portion303includes a CPU311, a RAM312, and a ROM313. The signal arithmetic portion303calculates a distance between the reader/writer and the semiconductor device300based on the intensity of the signal received by the semiconductor device300. The signal transmission/reception portion301has a function to input the signal received by the semiconductor device300to the signal arithmetic portion303and read information on individual identification of the semiconductor device300from a storage circuit (such as the RAM312and the ROM313) of the signal arithmetic portion303to transmit the information to the reader/writer; and a function to transmit to the reader/writer information on the distance between the reader/writer and the semiconductor device300calculated by the signal arithmetic portion303.

In the signal intensity detection portion302, a signal received at the antenna304in the signal transmission/reception portion301is input to the rectifier circuit308. An output signal from the rectifier circuit308is input to the power source circuit309. An output from the power source circuit309is input to the ADC310. The output from the power source circuit309may also be supplied to each circuit of the semiconductor device300as electric power. The ADC310converts an analog signal output from the power source circuit309into a digital signal and outputs the digital signal to the signal arithmetic portion303.

The signal arithmetic portion303includes the CPU (central processing unit)311, the RAM (random access memory)312, and the ROM (read only memory)313. The signal arithmetic portion303includes the CPU311such as a logic circuit; the RAM312, which is a work region (a region which temporarily stores information necessary for arithmetic processing); and the ROM313, which stores program and the like used in the CPU311. A volatile memory (typically, SRAM) is used as the RAM312, and a nonvolatile memory (typically, EEPROM) is used as the ROM313.

In the signal arithmetic portion303, the distance between the reader/writer and the semiconductor device is calculated in accordance with the digital signal output from the ADC310of the signal intensity detection portion302. In the signal arithmetic portion303, calculation of the distance between the reader/writer and the semiconductor device may be processed using hardware or using both hardware and software, but is preferably processed using software. In a processing method using software, an arithmetic circuit is formed using the CPU311, the RAM312, and the ROM313, and a distance calculation program is executed by the CPU311. It is preferable to process using software since modification of a distance calculation method can be achieved by program modification and further, an occupation area of hardware in the semiconductor device300can be reduced. Note that data on the calculated distance is output to the reader/writer through the modulation circuit307and the antenna304in the signal transmission/reception portion301.

By the semiconductor device having the above configuration, the distance between the reader/writer and the semiconductor device300can be calculated.

By applying the ADC of the present invention described in Embodiment Mode 1 to the ADC310, various parameters which determine operation can be more freely set. Consequently, resolving power can be improved in the case of keeping a dynamic range. Alternatively, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced. Further, it is not necessary to consider the offset voltage, so that the output period T2is not varied and digital data that is obtained can be more precise. Note that it is advantageous for the semiconductor device capable of wireless communication to reduce power consumption.

This embodiment mode will describe a configuration of a sensor device having the ADC described in Embodiment Mode 1. Note that in this specification, also the sensor device is treated as one kind of so-called semiconductor devices.FIG. 8is a block diagram showing a semiconductor device capable of wireless communication. The semiconductor device capable of wireless communication transmits and receives data to/from a reader/writer with radio signals.

FIG. 8is a block diagram illustrating a configuration of a sensor device according to this embodiment mode. A sensor device340includes a signal arithmetic portion349, a sensor portion353, and a wireless communication portion352.

The signal arithmetic portion349includes a CPU (central processing unit)346, a RAM (random access memory)347, and a ROM (read only memory)348. That is, the signal arithmetic portion349includes the CPU346such as a logic circuit; the RAM347, which is a work region (a region which temporarily stores information necessary for arithmetic processing); and the ROM348, which stores program and the like used in the CPU346. A volatile memory (typically, SRAM) is used as the RAM347, and a nonvolatile memory (typically, EEPROM) is used as the ROM348.

The wireless communication portion352includes an antenna341, a rectifier circuit344A, a rectifier circuit344B, a power source circuit345, a demodulation circuit342, and a modulation circuit343. The antenna341may employ an antenna similar to the antenna304illustrated inFIG. 6and may be connected similarly toFIG. 6. The rectifier circuits344A and344B may employ a rectifier circuit similar to the rectifier circuit308illustrated inFIG. 6. The demodulation circuit342may employ a demodulation circuit similar to the demodulation circuit306illustrated inFIG. 6. The modulation circuit343may employ a modulation circuit similar to the modulation circuit307illustrated inFIG. 6.

In the sensor device340of this embodiment mode, an output from the power source circuit345is supplied to each circuit of the sensor device340as electric power. Note that the wireless communication portion352is not provided if not necessary.

The sensor portion353includes a sensor351and a sensor driving circuit350.

FIG. 9Aillustrates an example of a sensor that detects surrounding brightness or the presence or absence of light. A sensor369is formed using a photodiode, a phototransistor, or the like. A sensor driving circuit368includes a sensor driving portion360, a detecting portion361, and an ADC362.

FIG. 9Bis a circuit diagram illustrating the detecting portion361. When a reset transistor363is made conducting, reverse bias voltage is applied to the sensor369. Here, operation in which potential of a minus terminal of the sensor369is charged to the potential of power source voltage is referred to as “reset”. After that, the reset transistor363is made non-conducting. At this time, the potential state is changed by an electromotive force of the sensor369with the passage of time. In other words, the potential of the minus terminal of the sensor369that has been charged to the potential of the power source voltage is gradually decreased by electric charge generated by photoelectric conversion. When a bias transistor365is made conducting state after a certain period of time has passed, a signal is output to an output side through an amplifying transistor364. In this case, the amplifying transistor364and the bias transistor365operate as a so-called source follower circuit. Note that a plus terminal is electrically connected to ground potential.

InFIG. 9B, the example in which the source follower circuit is formed using an n-channel transistor is shown; however, it is needless to say that the source follower circuit can also be formed using a p-channel transistor. Power source voltage VDDis applied to an amplifying side power source line366. Reference Potential is applied to a bias side power source line367. A drain electrode of the amplifying transistor364is connected to the amplifying side power source line366, and a source electrode is connected to a drain electrode of the bias transistor365.

A source electrode of the bias transistor365is connected to the bias side power source line367. Bias voltage Vbis applied to a gate electrode of the bias transistor365and bias current Ibflows through this transistor. The bias transistor365basically operates as a constant current source. Input potential Vinis applied to a gate electrode of the amplifying transistor364, and the source electrode is connected to an output terminal. The input-output relationship of this source follower circuit is defined as Vout=Vin−Vbby equalizing the sizes of the amplifying transistor364and the bias transistor365. This output voltage Voutis converted into a digital signal by the ADC362. The digital signal is output to the CPU346.

The sensor and the sensor driving circuit can be achieved using the ADC362. The ADC of the present invention described in Embodiment Mode 1 can be applied to the ADC362. By applying the ADC of the present invention to the ADC362, various parameters which determine operation can be more freely set. Consequently, resolving power can be improved in the case of keeping a dynamic range. Alternatively, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced. Further, it is not necessary to consider the offset voltage, so that the output period T2is not varied and digital data that is obtained can be more precise.

This embodiment mode will describe a semiconductor device capable of wireless communication (referred to as an IC tag, an RF tag, or the like) having a configuration in which a power source is monitored by the integration type ADC of the present invention. The semiconductor device capable of wireless communication is a small-sized semiconductor device in which an element formation layer and an antenna layer are combined. As an application field of the semiconductor device capable of wireless communication, for example, merchandise management in the distribution industry can be given. In general, the semiconductor devices capable of wireless communication are roughly classified into an active type with a built-in power storage portion and a passive type which operates using an external energy source. Since even the active type has a limit on the capacity of the power storage portion, it is necessary to operate the semiconductor device with a limited power source. Under such a condition, it is useful to monitor the power source with the ADC.

FIG. 10is a block diagram illustrating a semiconductor device381capable of wireless communication of this embodiment mode. The semiconductor device381includes an antenna382, an ADC385, a signal processing portion386, and a power source portion388. The power source portion388includes a power storage portion383and a power source circuit384.

The antenna382can employ an antenna similar to the antenna304of Embodiment Mode 2.

A rectifier circuit387A and a rectifier circuit387B half-wave rectify and smooth signals received at the antenna382.

The ADC385can employ the ADC described in Embodiment Mode 1.

The power source portion388supplies electric power to each circuit included in the semiconductor device381.

The signal processing portion386includes a modulation circuit, a demodulation circuit, a CPU, a ROM, a RAM, and the like.

A signal received at the antenna382is transmitted to the power source portion388through the rectifier circuit387A and supplied as electric power. The electric power supplied to the power storage portion383is stored as storage power. The power storage portion383has a function of storing electric power and corresponds to a battery and the like.

Note that a battery refers to a battery whose continuous operating time can be restored by charging. A battery formed in a sheet-like form is preferably used. For example, reduction in size is possible with the use of a lithium battery, preferably a lithium polymer battery that uses a gel electrolyte, a lithium ion battery, or the like. It is needless to say that the battery is not limited to these as long as it can be charged, and a battery that can be charged and discharged, such as a nickel metal hydride battery or a nickel cadmium battery, may be used. Alternatively, a high-capacity capacitor or the like may be used.

The storage power is supplied to the ADC385and the signal processing portion386through the power source circuit384as power source voltage. The ADC385has a function of monitoring power source voltage and can employ the ADC described in Embodiment Mode 1. A monitoring result of the power source voltage (power source data) is sent from the ADC385to the signal processing portion386. The signal processing portion386dynamically controls its operation based on the power source data and feeds the data back to the power source circuit384so as to control the power source voltage supplied to the signal processing portion386. In this manner, control in accordance with operation conditions of the semiconductor device381is performed as appropriate.

Meanwhile, a signal received is transmitted to the signal processing portion386through the antenna382and demodulated (a demodulation signal is generated). Next, in the signal processing portion386, a response signal in accordance with the demodulation signal is generated and modulated (a modulation signal is generated). The modulation signal is transmitted to the outside through the antenna382(a transmission signal is output). In this manner, the semiconductor device381can function as a wireless communication device.

Data expressed by the transmission signal is to be determined in accordance with the application use of the semiconductor device381. For example, the power source data as described above may be included. Further, when the semiconductor device381generates the transmission signal with electric power stored in the power storage portion383as an energy source not in accordance with the reception signal, the semiconductor device381can function as a sensor which can voluntarily notify of change.

With the above configuration, a semiconductor device which can be controlled as appropriate can be provided. It is advantageous to apply the integration type ADC of the present invention to such a semiconductor device in terms of circuit size and power consumption.

Although this embodiment mode describes the semiconductor device capable of wireless communication using the integration type ADC of the present invention, the integration type ADC of the present invention can also be applied to general portable devices which are operated without an external power source.

This embodiment mode can be freely combined with Embodiment Modes 1 to 3.

In this embodiment mode, an example of a method for manufacturing the ADC described in Embodiment Mode 1 and a semiconductor device having the ADC will be described with reference to the drawings. In this embodiment mode, a structure in which an antenna, a battery, and a signal processing circuit in a semiconductor device are provided over the same substrate, using thin film transistors, will be described. Note that when the antenna, the battery, and the signal processing circuit are formed over the same substrate, miniaturization can be achieved. In addition, an example in which a thin film secondary battery is used for the battery will be described.

First, a separation layer403is formed over one surface of a substrate401with an insulating film402therebetween. Next, an insulating film404which serves as a base film and an amorphous semiconductor film405(e.g., a film which includes amorphous silicon) are stacked (FIG. 12A). Note that the insulating film402, the separation layer403, the insulating film404, and the amorphous semiconductor film405can be formed in succession. The separation layer403is not necessarily formed when separation is not needed.

The substrate401may be a glass substrate, a quartz substrate, a metal substrate (e.g., a ceramic substrate, a stainless steel substrate, or the like), a semiconductor substrate such as a Si substrate, or the like. Alternatively, a plastic substrate such as a substrate formed of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic, or the like can be used. Note that in this process, the separation layer403is provided over the entire surface of the substrate401with the insulating film402interposed therebetween; however, if necessary, after the separation layer is provided over the entire surface of the substrate401, the separation layer may be patterned by using a photolithography method.

The insulating film402and the insulating film404are formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, where x>y>0), or silicon nitride oxide (SiNxOy, where x>y>0), by a CVD method, a sputtering method, or the like. For example, when the insulating film402and the insulating film404have a two-layer stacked structure, preferably, a silicon nitride oxide film is formed as a first insulating film and a silicon oxynitride film is formed as a second insulating film. Alternatively, a silicon nitride film may be formed as a first insulating film and a silicon oxide film may be formed as a second insulating film. The insulating film402serves as a blocking layer which prevents an impurity element from the substrate401from being mixed into the separation layer403or an element formed thereover. The insulating film404serves as a blocking layer which prevents an impurity element from the substrate401and the separation layer403from being mixed into an element formed thereover. By forming the insulating films402and404which serve as blocking layers in this manner, an element formed thereover can be prevented from being adversely affected by an alkali metal such as sodium or an alkaline earth metal included in the substrate401, and an impurity element included in the separation layer403. Note that when quartz is used as the substrate401, the insulating films402and404may be omitted. This is because a quartz substrate does not include an alkali metal or an alkaline earth metal.

As the separation layer403, a metal film, a stacked-layer structure including a metal film and a metal oxide film, or the like can be used. As the metal film, a single-layer structure or a stacked-layer structure is formed using a film formed of tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, or iridium, or of an alloy material or a compound material containing such an element as its main component. These materials can be formed by a sputtering method, various CVD methods such as a plasma CVD method, or the like. The stacked-layer structure including a metal film and a metal oxide film is formed as follows: after the aforementioned metal film is formed, plasma treatment in an oxygen atmosphere or an N2O atmosphere, or heat treatment in an oxygen atmosphere or an N2O atmosphere is performed, so that an oxide or an oxynitride of the metal film is formed on the surface of the metal film. For example, when a tungsten film is formed as the metal film by a sputtering method, a CVD method, or the like, plasma treatment is performed on the tungsten film so that a metal oxide film formed of tungsten oxide can be formed on the surface of the tungsten film. Alternatively, for example, after a metal film (e.g., a tungsten film) is formed, an insulating film may be formed over the metal film using silicon oxide (SiO2) or the like by a sputtering method, whereby a metal oxide film may be formed on the metal film (e.g., a tungsten oxide film on the tungsten film). Further, for example, high-density plasma treatment as described above may be performed as plasma treatment. Furthermore, in addition to the metal oxide film, a metal nitride or a metal oxynitride may be used. In this case, the metal film may be subjected to plasma treatment or heat treatment in a nitrogen atmosphere or an atmosphere where nitrogen and oxygen are mixed.

The amorphous semiconductor film405is formed with a thickness of 10 nm to 200 nm, inclusive (preferably, 30 nm to 150 nm, inclusive) by a sputtering method, an LPCVD method, a plasma CVD method, or the like.

Next, the amorphous semiconductor film405is crystallized by being irradiated with a laser beam. The amorphous semiconductor film405may be crystallized by a method which combines laser beam irradiation with a thermal crystallization method which employs RTA (rapid thermal annealing) or an annealing furnace or a thermal crystallization method which employs a metal element for promoting crystallization, or the like. Then, the obtained crystalline semiconductor film is etched into a desired shape to form crystalline semiconductor films405ato405f,and a gate insulating film406is formed so as to cover the crystalline semiconductor films405ato405f(FIG. 12B). Note that the etching is preferably performed so that end portions of the crystalline semiconductor films have a tapered shape. With a tapered shape, the gate insulating film can be formed favorably.

Note that the gate insulating film406is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, where x>y>0), or silicon nitride oxide (SiNxOy, where x>y>0), by a CVD method, a sputtering method, or the like. For example, when the gate insulating film406has a two-layer stacked structure, preferably, a silicon oxynitride film is formed as a first insulating film and a silicon nitride oxide film is formed as a second insulating film. Alternatively, a silicon oxide film may be formed as the first insulating film and a silicon nitride film may be formed as the second insulating film.

Next, an example of a manufacturing step of the crystalline semiconductor films405ato405fis briefly described below. First, an amorphous semiconductor film with a thickness of 50 nm to 60 nm is formed by a plasma CVD method. Next, a solution containing nickel, which is a metal element for promoting crystallization, is retained on the amorphous semiconductor film, and then dehydrogenation treatment (at 500° C., for one hour) and thermal crystallization treatment (at 550° C., for four hours) are performed on the amorphous semiconductor film to form a crystalline semiconductor film. Then, the crystalline semiconductor film is irradiated with a laser beam, and the crystalline semiconductor films405ato405fare formed by etching using a photolithography method. Note that the amorphous semiconductor film may be crystallized just by laser beam irradiation, without performing thermal crystallization which employs a metal element for promoting crystallization. Note that the present invention is not limited to the above polycrystalline semiconductor film but a single crystal semiconductor film may also be used.

As a laser oscillator for crystallization, a continuous wave laser beam (a CW laser beam) or a pulsed wave laser beam (a pulsed laser beam) can be used. As a laser beam which can be used here, a laser beam emitted from one or more of the following can be used: a gas laser, such as an Ar laser, a Kr laser, or an excimer laser; a laser whose medium is single-crystal YAG, YVO4, forsterite (Mg2SiO4), YAlO3, or GdVO4, to which one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta has been added as a dopant, or polycrystalline (ceramic) YAG, Y2O3, YVO4, YAlO3, or GdVO4, to which one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta has been added as a dopant; a glass laser; a ruby laser; an alexandrite laser; a Ti:sapphire laser; a copper vapor laser; and a gold vapor laser. Crystals with a large grain size can be obtained by irradiation with fundamental waves of such laser beams or second to fourth harmonics of the fundamental waves. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd:YVO4laser (fundamental wave of 1064 nm) can be used. In this case, a power density of approximately 0.01 to 100 MW/cm2(preferably, 0.1 to 10 MW/cm2, inclusive) is necessary. Irradiation is conducted with a scanning rate of approximately 10 to 2000 cm/sec. Note that a beam of a laser using, as a medium, single-crystal YAG, YvO4, forsterite (Mg2SiO4), YAlO3, or GdVO4, to which one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta has been added as a dopant, or polycrystalline (ceramic) YAG, Y2O3, YVO4, YAlO3, or GdVO4, to which one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta has been added as a dopant; an Ar ion laser; or a Ti:sapphire laser, can be continuously emitted. Furthermore, pulse oscillation thereof can be performed at a repetition rate of greater than or equal to 10 MHz by performing Q-switch operation, mode locking, or the like. When a laser beam is emitted at a repetition rate of greater than or equal to 10 MHz, during the time in which a semiconductor film melts by the laser beam and then solidifies, the semiconductor film is irradiated with a beam of the next pulse. Accordingly, unlike in the case of using a pulsed laser with a low repetition rate, a solid-liquid interface can be continuously moved in the semiconductor film; therefore, crystal grains which have grown continuously in a scanning direction can be obtained.

Further, the foregoing high-density plasma treatment may be performed on the crystalline semiconductor films405ato405fto oxidize or nitride the surfaces thereof, to form the gate insulating film406. For example, the gate insulating film406is formed by a plasma treatment in which a mixed gas which contains a rare gas such as He, Ar, Kr, or Xe, and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, or the like, is introduced. When excitation of the plasma in this case is performed by introduction of a microwave, high-density plasma with a low electron temperature can be generated. The surface of the semiconductor film can be oxidized or nitrided by oxygen radicals (OH radicals may be included) or nitrogen radicals (NH radicals may be included) generated by this high-density plasma.

By treatment using such high-density plasma, an insulating film with a thickness of 1 nm to 20 nm, inclusive, typically 5 nm to 10 nm, inclusive is formed over the semiconductor film. Because the reaction in this case is a solid-phase reaction, interface state density between the insulating film and the semiconductor film can be made very low. Because such high-density plasma treatment oxidizes (or nitrides) the semiconductor film (crystalline silicon or polycrystalline silicon) directly, the insulating film can be formed, ideally, with very little unevenness in its thickness. In addition, since crystal grain boundaries of crystalline silicon are not strongly oxidized either, very favorable conditions result. That is, by the solid-phase oxidation of the surface of the semiconductor film by the high-density plasma treatment shown here, an insulating film with good uniformity and low interface state density can be formed without excessive oxidation at crystal grain boundaries.

Note that as the gate insulating film406, just an insulating film formed by the high-density plasma treatment may be used, or an insulating film of silicon oxide, silicon oxynitride, silicon nitride, or the like may be stacked thereover by a CVD method which employs plasma or a thermal reaction. In any case, when transistors include an insulating film formed by high-density plasma in a part of a gate insulating film or in the whole of a gate insulating film, unevenness in characteristics can be reduced.

Furthermore, in the crystalline semiconductor films405ato405fwhich are obtained by crystallizing the semiconductor film by irradiation with a continuous wave laser beam or a laser beam emitted at a repetition rate of greater than or equal to 10 MHz which is scanned in one direction, crystals can grow in the scanning direction of the laser beam. When transistors are disposed so that the scanning direction is aligned with the channel length direction (the direction in which a carrier flows when a channel formation region is formed) and the above-described gate insulating layer is used in combination with the transistors, thin film transistors with less variation in characteristics and high electric field-effect mobility can be obtained.

Next, a first conductive film and a second conductive film are stacked over the gate insulating film406. In this embodiment mode, the first conductive film is formed with a thickness of 20 nm to 100 nm, inclusive, using a CVD method, a sputtering method, or the like. The second conductive film is formed with a thickness of 100 nm to 400 nm, inclusive. The first conductive film and the second conductive film are formed using an element such as tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, or niobium, or using an alloy material or a compound material containing such an element as its main component. Alternatively, they are formed using a semiconductor material such as polycrystalline silicon having conductivity by being doped with an impurity element such as phosphorus. As examples of a combination of the first conductive film and the second conductive film, a tantalum nitride film and a tungsten film, a tungsten nitride film and a tungsten film, a molybdenum nitride film and a molybdenum film, and the like can be given. Because tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the first conductive film and the second conductive film are formed. In addition, in the case of using a three-layer stacked structure instead of a two-layer stacked structure, a stacked-layer structure in which an aluminum film is interposed between molybdenum films may be used.

Next, a resist mask is formed using a photolithography method, and etching treatment for forming a gate electrode and a gate line is conducted, to form gate electrodes407over the crystalline semiconductor films405ato405f.In this embodiment mode, an example in which the gate electrodes407have a stacked-layer structure which includes a first conductive film407aand a second conductive film407bis described.

Next, the gate electrodes407are used as masks, and an impurity element imparting n-type conductivity is added to the crystalline semiconductor films405ato405fat a low concentration by an ion doping method or an ion implantation method. Then, a resist mask is selectively formed by a photolithography method, and an impurity element imparting p-type conductivity is added at a high concentration. As an impurity element which exhibits n-type conductivity, phosphorus, arsenic, or the like can be used. As an impurity element which exhibits p-type conductivity, boron, aluminum, gallium, or the like can be used. Here, phosphorus is used as an impurity element which imparts n-type conductivity, and is selectively introduced into the crystalline semiconductor films405ato405fsuch that they contain phosphorus at a concentration of 1×1015to 1×1019/cm3. Thus, n-type impurity regions408are formed. Further, boron is used as an impurity element which imparts p-type conductivity, and is selectively introduced into the crystalline semiconductor films405cand405esuch that they contain boron at a concentration of 1×1019to 1×1020/cm3. Thus, p-type impurity regions409are formed (FIG. 12C).

Next, an insulating film is formed so as to cover the gate insulating film406and the gate electrodes407. The insulating film is formed as a single layer or stacked layers using a film containing an inorganic material such as silicon, an oxide of silicon, or a nitride of silicon, or a film containing an organic material such as an organic resin, by a plasma CVD method, a sputtering method, or the like. Next, the insulating film is selectively etched using anisotropic etching which etches mainly in a perpendicular direction, to form insulating films410(also referred to as side walls) which are in contact with the side surfaces of the gate electrodes407. The insulating films410are used as masks for doping when LDD (lightly doped drain) regions are formed.

Next, using a resist mask formed by a photolithography method, the gate electrodes407, and the insulating films410as masks, an impurity element which imparts n-type conductivity is added at a high concentration to the crystalline semiconductor films405a,405b,405d,and405f,to form n-type impurity regions411. Here, phosphorus is used as an impurity element which imparts n-type conductivity, and it is selectively introduced into the crystalline semiconductor films405a,405b,405d,and405fsuch that they contain phosphorus at a concentration of 1×1019to 1×1020/cm3. Thus, the n-type impurity regions411, which have a higher concentration than the impurity regions408, are formed.

In the n-channel thin film transistor400a,a channel formation region is formed in a region of the crystalline semiconductor film405awhich overlaps with the gate electrode407; the impurity regions411which each form either a source region or a drain region are formed in regions which do not overlap with the gate electrode407and the insulating films410; and lightly doped drain regions (LDD regions) are formed in regions which overlap with the insulating films410and which are between the channel formation region and the impurity regions411. Further, the n-channel thin film transistors400b,400d,and400fare similarly provided with channel formation regions, lightly doped drain regions, and impurity regions411.

In the p-channel thin film transistor400c,a channel formation region is formed in a region of the crystalline semiconductor film405cwhich overlaps with the gate electrode407, and the impurity regions409which each form either a source region or a drain region are formed in regions which do not overlap with the gate electrode407. Further, the p-channel thin film transistor400eis similarly provided with a channel formation region and the impurity regions409. Note that here, the p-channel thin film transistors400cand400eare not provided with LDD regions; however, the p-channel thin film transistors may be provided with an LDD region, and the n-channel thin film transistor may not be provided with an LDD region.

Next, an insulating film is formed as a single layer or stacked layers so as to cover the crystalline semiconductor films405ato405f,the gate electrodes407, and the like; and conductive films413, which are electrically connected to the impurity regions409and411which form the source regions and the drain regions of the thin film transistors400ato400f,are formed over the insulating film (FIG. 13A). The insulating film is formed as a single layer or stacked layers, using an inorganic material such as an oxide of silicon or a nitride of silicon, an organic material such as polyimide, polyamide, benzocyclobutene, acrylic, or epoxy, a siloxane material, or the like, by a CVD method, a sputtering method, an SOG method, a droplet discharging method, a screen printing method, or the like. Here, the insulating film has a two-layer structure. A silicon nitride oxide film is formed as a first insulating film412a,and a silicon oxynitride film is formed as a second insulating film412b.Further, the conductive films413can form source electrodes and drain electrodes of the thin film transistors400ato400f.

Note that before the insulating films412aand412bare formed or after one or more thin films of the insulating films412aand412bare formed, heat treatment is preferably conducted for recovering the crystallinity of the semiconductor film, for activating an impurity element which has been added to the semiconductor film, or for hydrogenating the semiconductor film. As the heat treatment, a thermal annealing method, a laser annealing method, an RTA method, or the like is preferably used.

The conductive films413are formed as a single layer or stacked layers, using an element such as aluminum, tungsten, titanium, tantalum, molybdenum, nickel, platinum, copper, gold, silver, manganese, neodymium, carbon, or silicon, or an alloy material or a compound material containing the element as its main component, by a CVD method, a sputtering method, or the like. An alloy material containing aluminum as its main component corresponds to, for example, a material which contains aluminum as its main component and also contains nickel, or an alloy material which contains aluminum as its main component and which also contains nickel and one or both of carbon and silicon. As for the stacked layer, the conductive films413preferably employ, for example, a stacked-layer structure including a barrier film, an aluminum-silicon film, and a barrier film, or a stacked-layer structure including a barrier film, an aluminum-silicon film, a titanium nitride film, and a barrier film. Note that a barrier film is provided by using a thin film formed from titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon, which have low resistance and are inexpensive, are ideal materials for forming the conductive films413. Further, generation of hillocks of aluminum or aluminum silicon can be prevented when upper and lower barrier layers are formed. Furthermore, when the barrier film is formed from titanium, which is a highly-reducible element, even if a thin natural oxide film is formed over the semiconductor film, the natural oxide film can reduced and removed, so good contact with the semiconductor film can be obtained.

Next, an insulating film414is formed so as to cover the conductive films413, and over the insulating film414, conductive films415aand415b,which are each electrically connected to the conductive film413which forms a source electrode or a drain electrode of the thin film transistors400aand400f,are formed. Further, a conductive film416, which is electrically connected to the conductive film413which forms a source electrode or a drain electrode of the thin film transistor400b,is formed. Note that the conductive films415a,415b,and416may be formed of the same material in the same step. The conductive films415aand415band the conductive film416can be formed using any of the materials that the conductive films413can be formed of, mentioned above.

Then, a conductive film417that serves as an antenna is formed so as to be electrically connected to the conductive film416(FIG. 13B).

The insulating film414can be provided by a CVD method, a sputtering method, or the like as a single-layer or stacked layers using an insulating film containing oxygen and/or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNywhere x>y), or silicon nitride oxide (SiNxOy, where x>y); a film containing carbon such as DLC (diamond-like carbon); an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or a siloxane material such as a siloxane resin. Note that a siloxane material corresponds to a material having a Si—O—Si bond. Siloxane has a skeleton structure formed of bonds of silicon and oxygen. As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or aromatic hydrocarbon) is given. A fluoro group can also be given as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be given as a substituent.

The conductive film417is formed from a conductive material using a CVD method, a sputtering method, a printing method, such as a screen printing method or a gravure printing method, a droplet discharging method, a dispensing method, a plating method, or the like. The conductive material is any of the elements of aluminum, titanium, silver, copper, gold, platinum, nickel, palladium, tantalum, and molybdenum, or an alloy material or a compound material containing the elements as its main component, and has a single-layer structure or a stacked-layer structure.

For example, in the case of using a screen printing method to form the conductive film417which serves as an antenna, the conductive film417can be provided by selectively printing a conductive paste in which conductive particles having a grain size of several nm to several tens of μm are dissolved or dispersed in an organic resin. As conductive particles, metal particles of one or more of any of silver, gold, copper, nickel, platinum, palladium, tantalum, molybdenum, titanium, and the like; fine particles of silver halide; or dispersive nanoparticles can be used. In addition, as the organic resin included in the conductive paste, one or more organic resins selected from organic resins which serve as a binder, a solvent, a dispersing agent, and a coating material for the metal particles can be used. An organic resin such as an epoxy resin or a silicon resin can be given as representative examples. Further, when the conductive film is formed, it is preferable to conduct baking after the conductive paste is applied. For example, in the case of using fine particles containing silver as a main component (e.g., the grain size is 1 nm to 100 nm, inclusive) as a material for the conductive paste, the conductive film can be obtained by curing by baking at a temperature in the range of 150° C. to 300° C. Alternatively, fine particles containing solder or lead-free solder as a main component may be used. In that case, preferably, fine particles having a grain size of less than or equal to 20 μm are used. Solder and lead-free solder have advantages such as low cost.

Further, the conductive films415aand415bcan each serve as a wiring which is electrically connected to a secondary battery included in the semiconductor device of the present invention in a subsequent process. Furthermore, when the conductive film417which serves as an antenna is formed, another conductive film may be separately formed such that it is electrically connected to the conductive films415aand415b,and that conductive film may be used as a wiring connected to the secondary battery.

Next, an insulating film418is formed so as to cover the conductive film417, and then a layer (hereinafter referred to as an element formation layer419) including the thin film transistors400ato400f,the conductive film417, and the like, is separated from the substrate401. Here, after using laser beam (e.g., UV light) irradiation to form openings in regions where the thin film transistors400ato400fare not formed (FIG. 13C), the element formation layer419can be separated from the substrate401using physical force. Alternatively, before the element formation layer419is separated from the substrate401, an etchant may be introduced into the formed openings to selectively remove the separation layer403. As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride is used as a gas containing halogen fluoride. Accordingly, the element formation layer419is separated from the substrate401. Note that the separation layer403may be partially left instead of being removed entirely. By removing the separation layer403while leaving a part thereof, consumption of the etchant and treatment time required for removing the separation layer can be reduced. Accordingly, throughput is improved and cost is reduced. Further, the element formation layer419can be retained over the substrate401after the separation layer403is removed. Furthermore, by reusing the substrate401which is separated, cost can be reduced.

The insulating film418can be formed by a CVD method, a sputtering method, or the like as a single-layer structure or a stacked-layer structure using an insulating film which contains oxygen and/or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNywhere x>y), or silicon nitride oxide (SiNxOywhere x>y); a film containing carbon such as DLC (diamond-like carbon); a film containing an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or a film containing a siloxane material such as a siloxane resin.

In this embodiment mode, the openings are formed in the element formation layer419by laser beam irradiation, and then a first sheet material420is attached to one surface of the element formation layer419(a surface where the insulating film418is exposed). Then, the element formation layer419is separated from the substrate401(FIG. 14A).

Next, after attaching a second sheet material421to the other surface of the element formation layer419(a surface exposed by separation), the first sheet material420and the second sheet material421are attached together by performing one or both of heat treatment and pressure treatment (FIG. 14B). As the first sheet material420and the second sheet material421, a hot-melt film or the like can be used.

As the first sheet material420and the second sheet material421, films on which antistatic treatment for preventing static electricity or the like has been performed (hereinafter referred to as antistatic films) can be used. Examples of antistatic films are films in which an antistatic material is dispersed in a resin, films to which an antistatic material is attached, and the like. A film provided with an antistatic material may be a film which has an antistatic material provided over one of its surfaces, or a film which has antistatic materials provided over both of its surfaces. Concerning the film which has an antistatic material provided over one of its surfaces, the film may be attached to the layer such that the antistatic material is on the inner side of the film or the outer side of the film. Note that the antistatic material may be provided over the entire surface of the film, or over a part of the film. As an antistatic material, a conductive material such as a metal, indium tin oxide (ITO), or a surfactant such as an amphoteric surfactant, a cationic surfactant, or a nonionic surfactant can be used. In addition to that, as an antistatic material, a resin material containing a cross-linked copolymer having a carboxyl group and a quaternary ammonium base on its side chain, or the like can be used. By attaching, mixing, or applying such a material to a film, an antistatic film can be formed. By performing sealing using the antistatic film, a semiconductor element can be prevented from being adversely affected by static electricity from outside and the like when dealt with as a product.

Note that a storage capacitor of a power source circuit is formed such that a thin film secondary battery is connected to the conductive films415aand415b.The connection with the secondary battery may be made before the element formation layer419is separated from the substrate401(at a stage shown inFIG. 13BorFIG. 13C), after the element formation layer419is separated from the substrate401(at a stage shown inFIG. 14A), or after the element formation layer419is sealed with the first sheet material and the second sheet material (at a stage shown inFIG. 14B). An example of the structure in which the element formation layer419and the secondary battery are connected to each other is described below with reference toFIGS. 15A to 16B.

InFIG. 13B, conductive films431a and431b, which are electrically connected to the conductive films415aand415b,respectively, are formed at the same time as the conductive film417which serves as an antenna. Next, the insulating film418is formed so as to cover the conductive film417and the conductive films431aand431b.Then, openings432aand432bare formed so as to expose the surfaces of the conductive films431aand431b.Then, after the openings are formed in the element formation layer419by laser beam irradiation, the first sheet material420is attached to one surface of the element formation layer419(the surface where the insulating film418is exposed); and then, the element formation layer419is separated from the substrate401(FIG. 15A).

Next, the second sheet material421is attached to the other surface (a surface exposed by separation) of the element formation layer419, and the element formation layer419is then separated from the first sheet material420. Accordingly, in this embodiment mode, a sheet material with weak adhesion is used as the first sheet material420. Then, conductive films434aand434b,which are electrically connected to the conductive films431aand431b,respectively, through the openings432aand432b,are selectively formed (FIG. 15B).

The conductive film434aand the conductive film434bare formed of a conductive material using a CVD method, a sputtering method, a printing method such as a screen printing method or a gravure printing method, a droplet discharging method, a dispensing method, a plating method, or the like. The conductive material is any of the elements of aluminum, titanium, silver, copper, gold, platinum, nickel, palladium, tantalum, and molybdenum, or an alloy material or a compound material containing the elements as its main component, and has a single-layer structure or a stacked-layer structure.

Note that in this embodiment mode, an example in which the conductive films434aand434bare formed after the element formation layer419is separated from the substrate401is described; however, the element formation layer419may be separated from the substrate401after the conductive films434aand434bare formed.

Next, in the case where a plurality of elements are formed over the substrate, the element formation layer419is separated into separate elements (FIG. 16A). A laser irradiation apparatus, a dicing apparatus, a scribing apparatus, or the like can be used for the separation. Here, the plurality of elements formed over one substrate are separated from one another by laser beam irradiation.

Next, the separated elements are electrically connected to the secondary battery (FIG. 16B). In this embodiment mode, a thin film secondary battery is used for the storage capacitor of the power source circuit, and the following thin films are sequentially stacked: a current-collecting thin film, a negative electrode active material layer, a solid electrolyte layer, a positive electrode active material layer, and a current-collecting thin film.

A conductive film436aand a conductive film436bare each formed of a conductive material by a CVD method; a sputtering method; a printing method such as screen-printing or gravure printing; a droplet discharging method, a dispensing method, or a plating method. The conductive material is formed into a single-layer structure or a stacked-layer structure using an element such as aluminum, titanium, silver, copper, gold, platinum, nickel, palladium, tantalum, or molybdenum, or an alloy material or compound material containing the element as its main component. The conductive material is desired to have good adhesion to a negative electrode active material and have low resistance. Aluminum, copper, nickel, vanadium, or the like is particularly preferable as the conductive material.

When the structure of the thin film secondary battery is described in detail, a negative electrode active material layer481is formed over the conductive film436a.In general, vanadium oxide (V2O5) or the like is used. Next, a solid electrolyte layer482is formed over the negative electrode active material layer481. In general, lithium phosphate (Li3PO4) or the like is used. Then, a positive electrode active material layer483is formed over the solid electrolyte layer482. In general, lithium manganate (LiMn2O4) or the like is used. Alternatively, lithium cobaltate (LiCoO2) or lithium nickelate (LiNiO2) may be used. Next, a current-collecting thin film484that becomes an electrode is formed over the positive electrode active material layer483. The current-collecting thin film484is desired to have good adhesion to the positive electrode active material layer483and have low resistance. Aluminum, copper, nickel, vanadium, or the like can be used as the current-collecting thin film484.

Each of the foregoing thin film layers, that is, the negative electrode active material layer481, the solid electrolyte layer482, the positive electrode active material layer483, and the current-collecting thin film484, may be formed using a sputtering technique or an evaporation technique. The thickness of each layer is desirably 0.1 μm to 3 μm.

Next, a resin film is formed by a spin coating method or the like to form an interlayer film485. Then, the interlayer film is etched to form a contact hole. The interlayer film is not limited to a resin, and the interlayer film may be another film such as an oxide film formed by a CVD method; however, a resin film is desirable in terms of flatness. Alternatively, the contact hole can be formed without etching by using a photosensitive resin. Then, by forming a wiring layer486over the interlayer film and connecting the wiring layer486to the conductive film434b,electrical connection with the secondary battery is obtained.

Here, the conductive films434aand434bprovided over the element formation layer419are connected to the conductive films436aand436bthat serve as connecting terminals of a thin film secondary battery489, respectively. The case is shown in which the conductive film434aand the conductive film436a,or the conductive film434band the conductive film436b,are pressure-bonded to each other with a material having an adhesive property such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP) interposed therebetween, so that they are electrically connected to each other. An example is shown in which conductive particles438contained in a resin437having an adhesive property are used for connection. Alternatively, connection can also be obtained using a conductive adhesive agent such as a silver paste, a copper paste, or a carbon paste, or using solder bonding, or the like.

Note that a structure of a transistor can be of various modes, and is not limited to the specific structure described in this embodiment mode. For example, a multi-gate structure in which there are two or more gate electrodes may be used. In a multi-gate structure, channel regions are connected in series; accordingly, the structure is that in which a plurality of transistors are connected in series. By having a multi-gate structure, off-current is reduced, and withstand voltage of the transistors is enhanced and reliability is improved, and even if voltage between the drain and source electrodes changes when operating in a saturation region, current between the drain and source electrodes does not change very much and a flat characteristic or the like can be obtained. In addition, the structure may be that in which gate electrodes are placed over and below a channel. With a structure in which gate electrodes are placed over and below the channel, the channel region increases; accordingly, a current value can be increased and a depletion layer is easily formed, thereby decreasing a subthreshold swing. When the gate electrodes are placed over and below the channel, the structure is like that in which a plurality of transistors are connected in parallel.

Alternatively, the transistor used in the present invention may have a structure in which a gate electrode is placed over the channel formation region, a structure in which a gate electrode is placed below the channel formation region, a staggered structure, or an inverted staggered structure. Further alternatively, the structure may be that in which a channel formation region is divided into a plurality of regions, and the plurality of channel formation regions may be connected in parallel or in series. Further, a source electrode or a drain electrode may overlap with the channel formation region (or a part thereof). By having a structure in which the source electrode or drain electrode overlaps with the channel formation region (or a part thereof), unstable operation due to accumulation of electric charge in a part of the channel formation region can be prevented. Further, there may also be an LDD (Lightly Doped Drain) region. By providing an LDD region, off-current is reduced, and withstand voltage of the transistors is enhanced and reliability is improved, and even if voltage between the drain and source electrodes changes when operating in a saturation region, current between the drain and source electrodes does not change very much and a flat characteristic or the like can be obtained.

The method for manufacturing the semiconductor device in this embodiment mode can be applied to the ADC and the semiconductor device having the ADC described in this specification. That is, according to this embodiment mode, a semiconductor device, in which various parameters which determine operation can be more freely set, can be formed. Consequently, resolving power can be improved in the case of keeping a dynamic range. Alternatively, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced. Further, it is not necessary to consider the offset voltage, so that the output period T2is not varied and digital data that is obtained can be more precise.

This embodiment mode will describe an example of a method for manufacturing the semiconductor device described in the preceding embodiment modes, with reference to the drawings. In this embodiment mode, a structure in which an antenna, a battery, and a signal processing circuit of the semiconductor device are formed over the same substrate will be explained. Note that an antenna, a battery, and a signal processing circuit are formed together over a single crystal substrate using transistors including channel formation regions. When transistors are formed using a single crystal substrate, a semiconductor device having transistors with few variations in electric characteristics can be formed, which is preferable. In addition, in this embodiment mode, an example is explained in which a thin-film secondary battery is used as a battery.

First, regions504and506are formed in a semiconductor substrate500by separating an element region (FIG. 17A). The regions504and506provided in the semiconductor substrate500are insulated from each other by an insulating film (also referred to as a field oxide film)502. The example shown here is the case where a single crystal Si substrate having n-type conductivity is used as the semiconductor substrate500, and a p-well507is formed in the region506of the semiconductor substrate500.

Any substrate can be used as the semiconductor substrate500as long as it is a semiconductor substrate. For example, a single crystal Si substrate having n-type or p-type conductivity, a compound semiconductor substrate (e.g., a GaAs substrate, an InP substrate, a GaN substrate, a SiC substrate, a sapphire substrate, or a ZnSe substrate), an SOI (silicon on insulator) substrate formed by a bonding method or a SIMOX (separation by implanted oxygen) method, or the like can be used.

The regions504and506can be formed by a LOCOS (local oxidation of silicon) method, a trench isolation method, or the like.

In addition, the p-well507formed in the region506of the semiconductor substrate500can be formed by selective doping of the semiconductor substrate500with an impurity element imparting p-type conductivity. As an impurity element imparting p-type conductivity, boron, aluminum, gallium, or the like can be used.

In this embodiment mode, although the region504is not doped with an impurity element because an n-type semiconductor substrate is used as the semiconductor substrate500, an n-well may be formed in the region504by introduction of an impurity element imparting n-type conductivity. As an impurity element imparting n-type conductivity, phosphorus, arsenic, or the like can be used. When a p-type semiconductor substrate is used, on the other hand, the region504may be doped with an n-type impurity element to form an n-well, whereas the region506may not be doped with an impurity element.

Next, insulating films532and534are formed so as to cover the regions504and506, respectively (FIG. 17B).

For example, the surfaces of the regions504and506provided in the semiconductor substrate500are oxidized by heat treatment, so that the insulating films532and534can be formed of silicon oxide films. Alternatively, the insulating films532and534may be formed to have a stacked structure of a silicon oxide film and a film containing oxygen and nitrogen (a silicon oxynitride film) by the steps of forming a silicon oxide film by a thermal oxidation method and then nitriding the surface of the silicon oxide film by nitridation treatment.

Further alternatively, the insulating films532and534may be formed by plasma treatment as described above. For example, the insulating films532and534can be formed using a silicon oxide film or a silicon nitride film which is obtained by application of high-density plasma oxidation or high-density plasma nitridation treatment to the surfaces of the regions504and506provided in the semiconductor substrate500. Furthermore, after applying high-density plasma oxidation treatment to the surfaces of the regions504and506, high-density plasma nitridation treatment may be performed. In that case, silicon oxide films are formed on the surfaces of the regions504and506, and then silicon oxynitride films are formed on the silicon oxide films. Thus, the insulating films532and534are each formed to have a stacked structure of the silicon oxide film and the silicon oxynitride film. In addition, after silicon oxide films are formed on the surfaces of the regions504and506by a thermal oxidation method, high-density plasma oxidation or high-density plasma nitridation treatment may be applied to the silicon oxide films.

The insulating films532and534formed over the regions504and506of the semiconductor substrate500respectively function as gate insulating films of transistors which are completed later.

Next, a conductive film is formed so as to cover the insulating films532and534which are formed over the regions504and506, respectively (FIG. 17C). Here, an example is shown in which conductive films536and538are sequentially stacked as the conductive film. It is need less to say that the conductive film may be formed to have a single layer or a stacked structure of three or more layers.

As materials of the conductive films536and538, an element such as tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, or niobium, or an alloy material or a compound material containing such an element as its main component can be used. Alternatively, a metal nitride film obtained by nitridation of the above element can be used. Besides, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

In this embodiment mode, the conductive film536is formed using a tantalum nitride film and the conductive film538is formed thereover using a tungsten film. Alternatively, it is also possible to form the conductive film536using a single-layer film or a stacked film of a tungsten nitride film, a molybdenum nitride film, and/or a titanium nitride film and form the conductive film538using a single-layer film or a stacked film of a tantalum film, a molybdenum film, and/or a titanium film.

Next, the stacked conductive films536and538are selectively removed by etching, so that the conductive films536and538remain above desired parts of the regions504and506, respectively. Thus, gate electrodes540and542are formed (FIG. 18A).

Next, a resist mask548is selectively formed so as to cover the region504, and desired parts of the region506are doped with an impurity element, using the resist mask548and the gate electrode542as masks, so that impurity regions are formed (FIG. 18B). As an impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As an impurity element imparting n-type conductivity, phosphorus, arsenic, or the like can be used. As an impurity element imparting p-type conductivity, boron, aluminum, gallium, or the like can be used. Here, phosphorus is used as the impurity element.

InFIG. 18B, by introduction of the impurity element, impurity regions552which form source and drain regions and a channel formation region550are formed in the region506.

Next, a resist mask566is selectively formed so as to cover the region506, and the region504is doped with an impurity element, using the resist mask566and the gate electrode540as masks, so that impurity regions are formed (FIG. 18C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As an n-type impurity element, phosphorus, arsenic, or the like can be used. As a p-type impurity element, boron, aluminum, gallium, or the like can be used. At this time, an impurity element (e.g., boron) of a conductivity type different from that of the impurity element introduced into the region506inFIG. 18Bis used. As a result, impurity regions570which form source and drain regions and a channel formation region568are formed in the region504.

Next, an insulating film572is formed so as to cover the insulating films532and534and the gate electrodes540and542. Then, wirings574, which are electrically connected to the impurity regions552and570formed in the regions506and504respectively, are formed over the insulating film572(FIG. 19A).

The insulating film572can be formed with a single layer or a stacked layer of an insulating film containing oxygen and/or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNywhere x>y), or silicon nitride oxide (SiNxOywhere x>y); a film containing carbon such as DLC (diamond-like carbon); an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or a siloxane material such as a siloxane resin by a CVD method, a sputtering method, or the like. A siloxane material corresponds to a material having a bond of Si—O—Si. Siloxane has a skeleton structure with the bond of silicon and oxygen. As a substituent of siloxane, an organic group containing at least hydrogen (e.g., an alkyl group or aromatic hydrocarbon) is given. Also, a fluoro group may be given as the substituent, or both a fluoro group and an organic group containing at least hydrogen may be given.

The wirings574are formed with a single layer or a stacked layer of an element such as aluminum, tungsten, titanium, tantalum, molybdenum, nickel, platinum, copper, gold, silver, manganese, neodymium, carbon, or silicon, or an alloy material or a compound material containing such an element as its main component by a CVD method, a sputtering method, or the like. An alloy material containing aluminum as its main component corresponds to, for example, a material which contains aluminum as its main component and also contains nickel, or a material which contains aluminum as its main component and also contains nickel and one or both of carbon and silicon. The wirings574are preferably formed to have a stacked structure of a barrier film, an aluminum-silicon film, and a barrier film or a stacked structure of a barrier film, an aluminum silicon film, a titanium nitride film, and a barrier film. Note that the “barrier film” corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are suitable materials for forming the wirings574because they have low resistance and are inexpensive. When barrier films are provided as the top layer and the bottom layer, generation of hillocks of aluminum and aluminum silicon can be prevented. When a barrier film is formed of titanium which is an element having a high reducing property, even when there is a thin natural oxide film formed on the crystalline semiconductor film, the natural oxide film can be reduced, and a favorable contact with the crystalline semiconductor film can be obtained.

Note that the structure of transistors used in the present invention is not limited to the one shown in the drawing. For example, a transistor with an inverted staggered structure, a FinFET structure, or the like can be used. A FinFET structure is preferable because it can suppress a short channel effect which occurs along with reduction in transistor size.

The semiconductor device of the present invention includes a battery which can store electric power and supply electric power to the signal processing circuit. As the battery, a capacitor such as an electric double layer capacitor or a thin-film secondary battery is preferably used. In this embodiment mode, a connection between the transistor and a thin-film secondary battery is explained.

In this embodiment mode, the secondary battery is stacked over the wiring574connected to the transistor. The secondary battery has a structure in which a current-collecting thin film, a negative electrode active material layer, a solid electrolyte layer, a positive electrode active material layer, and a current-collecting thin film are sequentially stacked (FIG. 19B). Therefore, the material of the wiring574which also has a function of the current-collecting thin film of the secondary battery should have high adhesion to the negative electrode active material and also low resistance. In particular, aluminum, copper, nickel, vanadium, and the like are preferably used.

Next, the structure of the thin-film secondary battery is described. A negative electrode active material layer591is formed over the wiring574. In general, vanadium oxide (V2O5) or the like is used. Next, a solid electrolyte layer592is formed over the negative electrode active material layer591. In general, lithium phosphate (Li3PO4) or the like is used. Next, a positive electrode active material layer593is formed over the solid electrolyte layer592. In general, lithium manganate (LiMn2O4) or the like is used. Lithium cobaltate (LiCoO2) or lithium nickel oxide (LiNiO2) may also be used. Next, a current-collecting thin film594to serve as an electrode is formed over the positive electrode active material layer593. The current-collecting thin film594should have high adhesion to the positive electrode active material layer593and also low resistance. For example, aluminum, copper, nickel, vanadium, or the like can be used.

Each of the above-described thin layers of the negative electrode active material layer591, the solid electrolyte layer592, the positive electrode active material layer593, and the current-collecting thin film594may be formed by a sputtering technique or an evaporation technique. In addition, the thickness of each layer is preferably 0.1 μm to 3 μm.

Next, a resin film is formed by a spin coating method or the like. Then, the resin film is etched to form a contact hole, so that an interlayer film596is formed. The interlayer film596is not limited to a resin film, and other films such as an oxide film formed by a CVD method may also be used; however, a resin is preferably used in terms of flatness. In addition, the contact hole can be formed without etching when a photosensitive resin is used. Next, a wiring layer595is formed over the interlayer film596and connected to a wiring597. Thus, electrical connection with the secondary battery is obtained.

With the above-described structure, the semiconductor device of the present invention can have a structure in which transistors are formed on a single crystal substrate and a thin-film secondary battery is formed thereover. Thus, in this embodiment mode, a semiconductor device which is very thin and small can be formed.

The method for manufacturing the semiconductor device in this embodiment mode can be applied to any of the semiconductor devices in this specification. That is, according to this embodiment mode, a semiconductor device, in which various parameters which determine operation can be more freely set, can be formed. Consequently, resolving power can be improved in the case of keeping a dynamic range. Alternatively, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced. Further, it is not necessary to consider the offset voltage, so that the output period T2is not varied and digital data that is obtained can be more precise.

This embodiment mode will describe an example of a method for manufacturing a semiconductor device, which is different from that described in the preceding embodiment mode, with reference to the drawings.

First, an insulating film is formed over a substrate600. Here, a single crystal silicon substrate having n-type conductivity is used as the substrate600, and insulating films602and604are formed over the substrate600(FIG. 20A). For example, a silicon oxide film is formed as the insulating film602by application of heat treatment to the substrate600, and then a silicon nitride film is formed over the insulating film602by a CVD method.

The substrate600is not limited to a silicon substrate as long as it is a semiconductor substrate. For example, a single crystal Si substrate having n-type or p-type conductivity, a compound semiconductor substrate (e.g., a GaAs substrate, an InP substrate, a GaN substrate, a SiC substrate, a sapphire substrate, or a ZnSe substrate), an SOI (silicon on insulator) substrate formed by a bonding method or a SIMOX (separation by implanted oxygen) method, or the like can be used.

Alternatively, after forming the insulating film602, the insulating film604may be formed by nitridation of the insulating film602by high-density plasma treatment. Note that the insulating film provided over the substrate600may have a single-layer structure or a stacked structure of three or more layers.

Next, patterns of a resist mask606are selectively formed over the insulating film604, and selective etching is performed using the resist mask606as a mask, so that recessed portions608are selectively formed in the substrate600(FIG. 20B). For the etching of the substrate600and the insulating films602and604, plasma dry etching can be conducted.

Next, the patterns of the resist mask606are removed, and then an insulating film610is formed so as to fill the recessed portions608formed in the substrate600(FIG. 20C).

The insulating film610is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, where x>y>0), or silicon nitride oxide (SiNxOy, where x>y>0) by a CVD method, a sputtering method, or the like. As the insulating film610, a silicon oxide film is formed by an atmospheric pressure CVD method or a low-pressure CVD method using a TEOS (tetraethyl orthosilicate) gas.

Next, the surface of the substrate600is exposed by grinding treatment or polishing treatment such as CMP (chemical mechanical polishing). Here, by exposure of the surface of the substrate600, regions612and613are formed between insulating films611which are formed in the recessed portions608of the substrate600. The insulating film610formed over the surface of the substrate600is removed by grinding treatment or polishing treatment such as CMP, so that the insulating films611are obtained. Then, by selective introduction of an impurity element imparting p-type conductivity, a p-well615is formed in the region613of the substrate600(FIG. 21A).

As an impurity element imparting p-type conductivity, boron, aluminum, gallium, or the like can be used. In this case, boron is introduced into the region613as the impurity element.

Further, in this embodiment mode, although the region612is not doped with an impurity element because an n-type semiconductor substrate is used as the substrate600, an n-well may be formed in the region612by introduction of an n-type impurity element. As an n-type impurity element, phosphorus, arsenic, or the like can be used.

When a p-type semiconductor substrate is used, on the other hand, the region612may be doped with an impurity element imparting n-type conductivity to form an n-well, whereas the region613may not be doped with an impurity element.

Next, insulating films632and634are formed over the surfaces of the regions612and613in the substrate600, respectively (FIG. 21B).

For example, the surfaces of the regions612and613provided in the substrate600are oxidized by heat treatment, so that the insulating films632and634of silicon oxide films can be formed. Alternatively, the insulating films632and634may each be formed to have a stacked structure of a silicon oxide film and a film containing oxygen and nitrogen (a silicon oxynitride film) by the steps of forming a silicon oxide film by a thermal oxidation method and then nitriding the surface of the silicon oxide film by nitridation treatment.

Further alternatively, the insulating films632and634may be formed by plasma treatment as described above. For example, the insulating films632and634can be formed with a silicon oxide film or a silicon nitride film which is obtained by application of high-density plasma oxidation or high-density plasma nitridation treatment to the surfaces of the regions612and613provided in the substrate600. In addition, after application of high-density plasma oxidation treatment to the surfaces of the regions612and613, high-density plasma nitridation treatment may be conducted. In that case, silicon oxide films are formed on the surfaces of the regions612and613and then silicon oxynitride films are formed on the silicon oxide films. Thus, the insulating films632and634are each formed to have a stacked structure of the silicon oxide film and the silicon oxynitride film. In addition, silicon oxide films are formed on the surfaces of the regions612and613by a thermal oxidation method, and then high-density plasma oxidation treatment or high-density plasma nitridation treatment may be performed to the silicon oxide films.

Note that the insulating films632and634formed over the regions612and613in the substrate600respectively function as gate insulating films of transistors which are completed later.

Next, a conductive film is formed so as to cover the insulating films632and634which are formed over the regions612and613provided in the substrate600, respectively (FIG. 21C). In this embodiment mode, an example is shown in which conductive films636and638are sequentially stacked as the conductive film. It is needless to say that the conductive film may be formed to have a single layer or a stacked structure of three or more layers.

As materials of the conductive films636and638, an element such as tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, or niobium, or an alloy material or a compound material containing such an element as its main component can be used. Alternatively, a metal nitride film obtained by nitridation of such an element can also be used. Furthermore, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can also be used.

In this case, a stacked structure is employed in which the conductive film636is formed using a tantalum nitride film and the conductive film638is formed thereover using a tungsten film. Alternatively, it is also possible to form the conductive film636using a single-layer film or a stacked film of tantalum nitride, tungsten nitride, molybdenum nitride, and/or titanium nitride and form the conductive film638using a single-layer film or a stacked film of tungsten, tantalum, molybdenum, and/or titanium.

Next, the stacked conductive films636and638are selectively removed by etching, so that the conductive films636and638remain above parts of the regions612and613of the substrate600. Thus, conductive films640and642functioning as gate electrodes are formed (FIG. 22A). Here, the surfaces of the regions612and613of the substrate600which do not overlap with the conductive films640and642respectively are exposed.

Specifically, in the region612of the substrate600, a part of the insulating film632formed below the conductive film640, which does not overlap with the conductive film640, is selectively removed, so that the ends of the conductive film640and the ends of the insulating film632are almost aligned with each other. In addition, in the region613of the substrate600, a part of the insulating film634formed below the conductive film642, which does not overlap with the conductive film642, is selectively removed, so that the ends of the conductive film642and the ends of the insulating film634are almost aligned with each other.

In this case, the parts of the insulating films and the like which do not overlap with the conductive films640and642may be removed at the same time as the formation of the conductive films640and642. Alternatively, the parts of the insulating films and the like which do not overlap with the conductive films640and642may be removed using resist masks which are left after the formation of the conductive films640and642or the conductive films640and642as masks.

Then, the regions612and613of the substrate600are selectively doped with an impurity element (FIG. 22B). At this time, the region613is selectively doped with an impurity element imparting n-type conductivity using the conductive film642as a mask, whereas the region612is selectively doped with an impurity element imparting p-type conductivity using the conductive film640as a mask. As an impurity element imparting n-type conductivity, phosphorus, arsenic, or the like can be used. As an impurity element imparting p-type conductivity, boron, aluminum, gallium, or the like can be used.

Next, sidewalls654which are in contact with the side surfaces of the conductive films640and642are formed. Specifically, the sidewalls are formed with a single layer or a stacked layer of a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, and/or a film containing an organic material such as an organic resin by a plasma CVD method, a sputtering method, or the like. Then, such an insulating film is selectively etched by anisotropic etching mainly in the perpendicular direction, so that the sidewalls654can be formed so as to be in contact with the side surfaces of the conductive films640and642. The sidewalls654are used as masks in doping for forming LDD (lightly doped drain) regions. In addition, the sidewalls654are formed to be in contact with the side surfaces of the insulating films formed below the conductive films640and642.

Next, the regions612and613of the substrate600are doped with an impurity element, using the sidewalls654and the conductive films640and642as masks, so that impurity regions which function as source and drain regions are formed (FIG. 22C). At this time, the region613of the substrate600is doped with an impurity element imparting n-type conductivity at higher concentration than in the LDD region, using the sidewalls654and the conductive film642as masks, whereas the region612is doped with an impurity element imparting p-type conductivity at higher concentration than in the LDD region, using the sidewalls654and the conductive film640as masks.

As a result, impurity regions658which form source and drain regions, low-concentration impurity regions660which form LDD regions, and a channel formation region656are formed in the region612of the substrate600. Meanwhile, impurity regions664which form source and drain regions, low-concentration impurity regions666which form LDD regions, and a channel formation region662are formed in the region613of the substrate600.

In this embodiment mode, the impurity elements are introduced under the condition that parts of the regions612and613of the substrate600which do not overlap with the conductive films640and642are exposed. Accordingly, the channel formation regions656and662which are formed in the regions612and613of the substrate600respectively can be formed in a self-aligned manner, using the conductive films640and642.

Next, an insulating film is formed so as to cover the insulating films, the conductive films, and the like which are provided over the regions612and613of the substrate600, and opening portions678are formed in the insulating film, so that an insulating film677is formed (FIG. 23A).

The insulating film677can be formed with a single layer or a stacked layer of an insulating film containing oxygen and/or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNywhere x>y), or silicon nitride oxide (SiNxOywhere x>y); a film containing carbon such as DLC (diamond-like carbon); an organic material such as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, or acrylic; or a siloxane material such as a siloxane resin, by a CVD method, a sputtering method, or the like. A siloxane material corresponds to a material having a bond of Si—O—Si. Siloxane has a skeleton structure with the bond of silicon and oxygen. As a substituent of siloxane, an organic group containing at least hydrogen (e.g., an alkyl group or aromatic hydrocarbon) is used. In addition, a fluoro group may be used as the substituent. Further, a fluoro group and an organic group containing at least hydrogen may be used as the substituent.

Next, conductive films680are formed in the opening portions678by a CVD method or the like. Then, conductive films682ato682dare selectively formed over the insulating film677so as to be electrically connected to the conductive films680(FIG. 23B).

The conductive films680and682ato682dare formed with a single layer or a stacked layer of an element such as aluminum, tungsten, titanium, tantalum, molybdenum, nickel, platinum, copper, gold, silver, manganese, neodymium, carbon, or silicon, or an alloy material or a compound material containing such an element as its main component by a CVD method, a sputtering method, or the like. An alloy material containing aluminum as its main component corresponds to, for example, a material which contains aluminum as its main component and also contains nickel, or a material which contains aluminum as its main component and also contains nickel and one or both of carbon and silicon. For example, each of the conductive films680and682ato682dis preferably formed to have a stacked structure of a barrier film, an aluminum-silicon film, and a barrier film or a stacked structure of a barrier film, an aluminum-silicon film, a titanium nitride film, and a barrier film. Note that the “barrier film” corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum-silicon are suitable materials for forming the conductive films680and682ato682dbecause they have low resistance and are inexpensive. When barrier films are provided as the top layer and the bottom layer, generation of hillocks of aluminum and aluminum silicon can be prevented. When a barrier film formed of titanium which is an element having a high reducing property is formed, even when there is a thin natural oxide film formed on the crystalline semiconductor film, the natural oxide film can be reduced, and a favorable contact with the crystalline semiconductor film can be obtained. Here, the conductive films680and682ato682dcan be formed by selective growth of tungsten by a CVD method.

Through the above steps, a p-channel transistor formed in the region612of the substrate600and an n-channel transistor formed in the region613of the substrate600can be obtained.

Note that the structure of transistors constituting the semiconductor device of the present invention is not limited to the one shown in the drawings. For example, a transistor with an inverted staggered structure, a FinFET structure, or the like can be used. A FinFET structure is preferable because it can suppress a short channel effect which occurs along with reduction in transistor size.

The semiconductor device of the present invention includes a battery which can store electric power in the signal processing circuit. As the battery, an electric double layer capacitor or a thin-film secondary battery is preferably used. In this embodiment mode, a connection between the transistor and the thin-film secondary battery is explained.

In this embodiment mode, a secondary battery is stacked over the conductive film682dconnected to the transistor. The secondary battery has a structure in which a current-collecting thin film, a negative electrode active material layer, a solid electrolyte layer, a positive electrode active material layer, and a current-collecting thin film are sequentially stacked (FIG. 23B). Therefore, the material of the conductive film682dwhich is also used as the current-collecting thin film of the secondary battery preferably has high adhesion to the negative electrode active material and also low resistance. In particular, aluminum, copper, nickel, vanadium, or the like is preferably used.

Then, the structure of the thin-film secondary battery is described in detail. A negative electrode active material layer691is formed over the conductive film682d.In general, vanadium oxide (V2O5) or the like is used. Next, a solid electrolyte layer692is formed over the negative electrode active material layer691. In general, lithium phosphate (Li3PO4) or the like is used. Next, a positive electrode active material layer693is formed over the solid electrolyte layer692. In general, lithium manganate (LiMn2O4) or the like is used. Lithium cobaltate (LiCoO2) or lithium nickel oxide (LiNiO2) can also be used. Next, a current-collecting thin film694to serve as an electrode is formed over the positive electrode active material layer693. The current-collecting thin film694should have high adhesion to the positive electrode active material layer693and also low resistance. For example, aluminum, copper, nickel, vanadium, or the like can be used.

Each of the above-described thin layers of the negative electrode active material layer691, the solid electrolyte layer692, the positive electrode active material layer693, and the current-collecting thin film694may be formed by a sputtering technique or an evaporation technique. In addition, the thickness of each layer is preferably 0.1 μm to 3 μm.

Next, a resin film is formed by a spin coating method. Then, the resin film is etched to form a contact hole, so that an interlayer film696is formed. The interlayer film696is not limited to a resin, and other films such as an oxide film formed by a CVD method may also be used; however, a resin film is preferably used in terms of flatness. In addition, the contact hole can be formed without etching when a photosensitive resin is used. Next, a wiring layer695is formed over the interlayer film696and connected to a wiring697. Thus, electrical connection with the secondary battery is obtained.

With the above-described structure, the semiconductor device of the present invention can have a structure in which the transistors are formed on the single crystal substrate and the thin-film secondary battery is formed thereover. Thus, according to the present invention, a very thin and small semiconductor device can be formed.

The method for manufacturing the semiconductor device in this embodiment mode can be applied to any of the semiconductor devices described in this specification. That is, according to this embodiment mode, a semiconductor device, in which various parameters which determine operation can be more freely set, can be formed. Consequently, resolving power can be improved in the case of keeping a dynamic range. Alternatively, by lengthening a clock cycle for counting a discharging period, power consumption can be reduced. Further, it is not necessary to consider the offset voltage, so that the output period T2is not varied and digital data that is obtained can be more precise.

A semiconductor device700to which the present invention is applied can be used for a variety of items and systems by utilizing a function of transmitting and receiving an electromagnetic wave. As the items, the following items are given: keys (seeFIG. 11A), paper money, coins, securities, bearer bonds, certificates (such as a driver's license or a resident's card, seeFIG. 11B), books, containers (such as a Petri dish, seeFIG. 11C), packaging containers (such as wrapping paper or bottles, seeFIGS. 11E and 11F), recording media (such as a disk or video tape), vehicles (such as a bicycle), personal accessories (such as bags or eyeglasses, seeFIG. 11D), food, clothing, livingware, electronic appliances (such as a liquid crystal display device, an EL display device, a television device, or a portable terminal), or the like. The semiconductor device of the present invention is fixed or mounted to items of a variety of forms such as those above by being attached to or embedded on the surface. Further, a system refers to a goods management system, an authentication function system, a distribution system, or the like. In addition, the semiconductor device700may be a sensor device.

In this manner, the semiconductor device to which the present invention is applied can be attached to a variety of items.

In this embodiment, dynamic ranges of the conventional integration type ADC illustrated inFIG. 2and the integration type ADC of the present invention illustrated inFIG. 1described in Embodiment Mode 1 are compared.

In this embodiment, it is supposed that the ADC is operated under the following required specification, that is, the ADC monitors the value of power source potential VDD, which is a DC power source. Further, the ADC is operated with only VDDand ground potential VGND.

FIG. 24is a graph which compares input-output characteristics of the integration type ADC of the present invention (hereinafter referred to as a first ADC) with the conventional integration type ADC (hereinafter referred to as a second ADC). Among legends in the graph, “conventional ideal” represents a second ideal straight line, “improved ideal” represents a first ideal straight line, “conventional simulation” represents a second circuit calculation result (VDDinput of 1.0 V to 8.0 V in increments of 0.1 V), and “improved simulation” represents a first circuit calculation result (VDDinput of 1.0 V to 8.0 V in increments of 0.1 V). In the second ADC, offset potential Voffset=1.8 V (generated from VDDwith the use of a regulator circuit, which monitors output voltage and controls the voltage to be constant) and reference potential Vref=0 V are set, and various parameters are determined to operate the ADC normally only in the case of 2.0 V<VDD<6.0V. On the other hand, although k=0.9 and Vconst=0.67 regarding the multiplier circuit112and the subtraction circuit113which generate the offset voltage Voffsetand the reference potential Vrefrespectively in the first ADC, the same values as in the second ADC are used regarding other circuits. Note that there is generated some deviations between the circuit calculation result and the ideal straight lines. This is because the calculation result includes delay of peripheral circuits.

When dynamic ranges of the first ADC and the second ADC are compared, 2.0V<VDD<6.0V in the second ADC as designed, but in the first ADC, it is found that the dynamic range of the first ADC has a wider range than the dynamic range of the second ADC with respect to both the lower limit and the upper limit. The dynamic range of the second ADC is limited to the range represented by the equation (3). On the other hand, in the first ADC at least in this example, there is no upper limit, and an element which determines the lower limit is the subtraction circuit113which generates the reference potential Vref. This shows that the equation (3) is always satisfied.

As described above, with the use of the present invention, the dynamic range of the integration type ADC can be more enlarged than in the conventional ADC. Further, it has become clear that various parameters which determine operation of the integration type ADC can be more freely set, and the effect of the present invention has been proved.

This application is based on Japanese Patent Application serial no. 2006-351791 filed with Japan Patent Office on Dec. 27, 2006, the entire contents of which are hereby incorporated by reference.