Display panel

A display panel including: pixels disposed in an active area of a substrate; data lines connected to the pixels; and a crack detection line disposed in a peripheral area of the active area in the substrate. The crack detection line includes a plurality of stacked conductive layers and at least one insulating layer disposed therebetween. At least one of the conductive layers is electrically connected to any one of the data lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2015-0016356, filed on Feb. 2, 2015, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

Exemplary embodiments relate to a flat panel display panel.

Discussion of the Background

Recently, with the development of semiconductor manufacturing technologies and image processing technologies, weight reduction and thinness of a display device may be easily achieved. Flat panel display devices, which may realize high image quality, have been commercialized and rapidly propagated.

A liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode display (OLED) are several popular examples of a flat panel display device.

Among these flat panel display devices, the weight reduction, thinness, and high image quality of the LCD and the OLED, and the like may be easily achieved. Therefore, the LCD and the OLED may be widely adopted in portable devices, for example, a mobile phone, a PDA, a portable computer, and the like.

In particular, an OLED, which is a self-emission device, does not require a backlight like an LCD. Therefore, an OLED may be manufactured to be much thinner and have a response speed on the order of tens of nanoseconds, a wide viewing angle, and good contrast. As a result, the OLED has drawn much attention as a next generation display.

However, as the display panel of the flat panel display evolves to be large, light, and thin, the display panel needs to have good durability against cracking, scratches, and breakage phenomena resulting from an external impact.

As a crack, etc., occur in the display panel, in particular, as a power supply applied to the display panel may be short-circuited, and thus, an overcurrent flows in the panel, a temperature rises and thus the display panel catch fire. Further, a DC-DC converter is in an overload condition due to the occurring short, which leads to a destruction of the DC-DC converter and its various peripheral circuits, such as an inductor.

Therefore, even though the display panel is partially damaged, processing to minimize the damage of the display panel is required so as to safely protect the display panel from overheating and the possibility of fire.

In particular, the power supply applied to the display panel may be shorted or opened as a result of the occurrence of cracks, and the like, in the display panel of the organic light emitting diode display. As a result, there is a need to rapidly solve the problem in that a screen is abnormally displayed or driving power is not supplied properly.

When errors occur in the display panel, it is difficult for a user to determine the errors in the early stage, and when the user confirms the errors with the naked eyes, the failure of the display device is likely to be considerably aggravated.

When the errors occur, since the image quality may be changed, a fire may break out due to the overheating, or an end user may be burned, there is a need to detect the errors of the display panel in the early stage.

SUMMARY

Exemplary embodiments provide a display panel capable of detecting damage to the display panel as a result of cracks and other defects.

An exemplary embodiment of the present disclosure discloses a display panel including: pixels disposed in an active area of a substrate; data lines connected to the pixels; and a crack detection line disposed in a peripheral area of the active area in the substrate. The crack detection line includes a plurality of stacked conductive layers and at least one insulating layer disposed therebetween. At least one of the conductive layers is electrically connected to any one of the data lines.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

First, a display panel according to exemplary embodiments of the present disclosure will be described with reference toFIG. 1.

FIG. 1is a schematic layout view of a display panel according to an exemplary embodiment of the present disclosure.

Referring toFIG. 1, a display panel1000includes pixels150formed on a substrate and signal lines connected thereto. The pixels150are formed in an active area AA of the substrate and at least some of the signal lines are formed in a peripheral area of the substrate.

The signal lines include a plurality of first test signal lines DC_R, DC_G, and DC_B, a plurality of second test signal lines TEST_DATA1and TEST_DATA2, a first test control signal line DC_GATE, a second test control signal line TEST_GATE, a plurality of data control signal lines CLA1, CLA2, CLB1, CLB2, CLC1, and CLC2, a plurality of data lines DAs, and a plurality of crack detection lines CD1and CD2.

The first test signal lines DC_R, DC_G, and DC_B, the first test control signal line DC_GATE, and the data lines DA are connected to a plurality of first switching elements Q1.

The data control signal lines CLA1, CLA2, CLB1, CLB2, CLC1, and CLC2and the data lines DAs are connected to a plurality of second switching elements Q2.

The second test signal lines TEST_DATA1and TEST_DATA2, the second test control signal line TEST_GATE, and the data lines DAs are connected to a plurality of third switching elements Q3.

The first and second crack detection lines CD1and CD2are signal lines for detecting damage due to a crack in the peripheral area enclosing the active area of the display panel1000.

The first and second crack detection lines CD1and CD2are formed to extend toward different outside areas of the display panel1000. For example, the first crack detection line CD1and the second crack detection line CD2are each disposed in the outside areas of both sides of the active area AA.

The first and second crack detection lines CD1and CD2each have a mufti-layered wiring structure in which a plurality of conductive layers (not illustrated) are stacked.

At least one of the conductive layers configuring the first crack detection line CD1is connected between the first test signal line DC_G and a data line DA1. At least one of the conductive layers configuring the first crack detection line CD1is connected to a signal line (e.g., ELVSS line) through which a signal having a predetermined voltage level is supplied.

At least one of the conductive layers configuring the second crack detection line CD2is connected between the first test signal line DC_G and a data line DA2. At least one of the conductive layers configuring the second crack detection line CD2is connected to a signal line (e.g., ELVSS line) through which a signal having a predetermined voltage level is supplied.

A detection signal for crack detection needs to be supplied to the corresponding data lines DAs through the crack detection lines CD1and CD2during the crack detection test. However, there is a need to cut off an electrical connection between the crack detection lines CD1and CD2and each data line DA whenever the crack detection test is not in progress. Therefore, the first crack detection line CD1is connected to the data line DA1through the switching element Q1.

That is, at least one of the conductive layers configuring each crack detection line CD1and CD2has one end electrically connected to the first test signal line DC_G and the other end connected to a drain electrode (or source electrode) of the first switching element Q1. Therefore, at least one of the conductive layers configuring each crack detection line CD1and CD2which is connected between the first test signal line DC_G and each data line DA1and DA2is electrically connected to the data lines DA1and DA2through the first switching element Q1.

The multi-layered wiring structure of the crack detection lines CD1and CD2will be described in detail with reference toFIGS. 5 to 10, as described below.

Hereinafter, a crack detection operation in the display panel according to the exemplary embodiments of the present disclosure will be described with reference toFIGS. 2A and 2B.

Referring toFIGS. 2A and 2B, an initialization control signal SCD_initial for initializing the plurality of pixels150is applied to the data control signal lines CLB1and CLB2. Further, a detection control signal SCD_write for applying a detection signal V2to the pixels150is applied to the first test control signal line DC_GATE.

The pixels150are initialized to display a white color prior to applying the detection signal V1to the crack detection lines CD1and CD2(S100).

In step S100, to initialize the pixels150, the initialization control signal SCD_initial is in an “on” state. Therefore, the second switching elements Q2, which are controlled by the data control signal lines CLB1and CLB2, are in an “on” state. Further, an “on” signal is applied to the second test control signal line TEST_GATE, and thus, the third switching element Q3is in an “on” state. Therefore, the initialization signal V1applied to the second test signal lines TEST_DATA1and TEST_DATA2is applied to each data line DA. The initialization signal V1is a signal for initializing the pixels150at a predetermined level and is a signal for allowing the pixels150to display a white color. The pixels150display a white color by applying the initialization signal V1to the data lines DAs.

An “off” signal is applied to the first test control signal line DC_GATE for a period H1in which the pixels150are initialized, and thus, the first switching elements Q1are in an “off” state.

When the initialization period H1ends, the initialization control signal SCD_initial is in an “off” state, and thus, the second switching elements Q2controlled by the data control signal lines CLB1and CLB2are in an “off” state.

When the initialization for the pixels150ends, the detection signal V2having a predetermined level is applied to the data lines DAs to allow the pixels150to display a black color (S110).

In step S110, to apply the detection signal V2to each data line DA, the detection control signal SCD_write is in an “on” state. Therefore, the first switching elements Q1controlled by the first test control signal line DC_GATE are in an “on” state and the detection signal V2applied to the first test signal lines DC_R, DC_G, and DC_B is applied to the data lines DAs through the first switching elements Q1. Further, the detection signal V2applied to the first test signal lines DC_R, DC_G, and DC_B is applied to DA1and DA2of the plurality of data lines DAs through the corresponding crack detection lines CD1and CD2and the first switching element Q1. The detection signal V2is a signal for charging the pixels150at a predetermined level and is a signal for allowing the pixels150to display a black color. The pixels150display a black color by applying the detection signal V2to the data lines DAs.

When a crack appears in the insulating layer in the peripheral area of the display panel1000and includes foreign particles, at least one of the conductive layers configuring the crack detection lines CD1and CD2, which is connected between the first test signal line DC_G and the data lines DA1and DA2, may be shorted from other conductive layers.

Therefore, the detection signal V2flowing from the first test signal line DC_G toward the crack detection lines CD1and CD2is supplied to the first data line DA1or the second data line DA2, while being distorted. Therefore, a voltage V_T applied to the pixel150connected to the first data line DA1or the second data line DA2is not charged up to the voltage level of the detection signal V2, and therefore, a voltage difference ΔV from the detection signal V2is generated.

The voltage difference ΔV is generated such that the pixel150connected to the first data line DA1and the second data line DA2does not display a black color and is displayed brightly. As such, a crack occurring in the peripheral area of the active area AA is sensed by the brightly displayed pixel150

Meanwhile,FIG. 2Aillustrates, for example, the case in which the initialization signal V1is applied to the second test data signal lines TEST_DATA1and TEST_DATA2, but the exemplary embodiment of the present disclosure is not limited thereto. In some of the exemplary embodiments of the present disclosure, the initialization signal V1may be applied to the first test data signal lines DC_R, DC_G, and DC_B. In this case, the initialization control signal SCD_initial for initializing the pixels150is applied to the first test control signal line DC_GATE.

Further,FIG. 2Aillustrates, for example, the case in which the detection signal V2is applied to the plurality of first test data signal lines DC_R, DC_G, and DC_B, but the exemplary embodiment of the present disclosure is not limited thereto. In some of the exemplary embodiments of the present disclosure, the detection signal V2may be applied to the plurality of second test data signal lines TEST_DATA1and TEST_DATA2. In this case, the detection control signal SCD_write for applying the detection signal to the plurality of pixels150may be applied to the second test control signal lines TEST_GATE or the data control signal lines CLB1and CLB2.

Hereinafter, prior to describing the multi-layered wiring structure of the crack detection lines CD1and CD2, the pixel150of the display panel1000according to the exemplary embodiments of the present disclosure will be described in more detail.

FIG. 3is a circuit diagram illustrating the pixel illustrated inFIG. 1.FIG. 4is a cross-sectional view illustrating the pixel circuit and the organic light emitting diode illustrated inFIG. 3.

As illustrated inFIGS. 3 and 4, the pixel150includes the organic light emitting diode (OLED) which is connected between a first power supply ELVDD and a second power supply ELVSS and a pixel circuit152which is connected between the first power supply ELVDD and the organic light emitting diode (OLED) to control the driving power supplied to the organic light emitting diode (OLED).

An anode of the organic light emitting diode (OLED) is connected to a driving power line ELVDDL connected to the first power supply ELVDD through the pixel circuit152and a cathode of the organic light emitting diode (OLED) is connected to the second power supply ELVSS. The organic light emitting diode (OLED) is supplied with the driving power from the first power supply ELVDD through the pixel circuit152and emits light at luminance corresponding to a driving current flowing in the organic light emitting diode (OLED) when common power is supplied from the second power supply ELVSS.

The pixel circuit152includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a first capacitor C1, and a second capacitor C2.

The first thin film transistor T1is connected between the driving power line ELVDDL and the organic light emitting diode (OLED) and supplies the driving power corresponding to the data signal from the first power supply ELVDD to the organic light emitting diode (OLED) for an emission period of the pixel150. That is, the first thin film transistor T1serves as a driving transistor of the pixel150. The first thin film transistor T1includes a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

The first active layer A1is positioned between a buffer layer BU formed on a substrate SUB and a first insulating layer GI1. When the first active layer A1is turned on by the first gate electrode G1, the first active layer A1connects between the driving power line ELVDDL among the signal lines DAs and the organic light emitting diode (OLED).

The first gate electrode G1is connected to a first capacitor electrode CE1of the first capacitor C1and is positioned on the same layer as the first capacitor electrode CE1. The first gate electrode G1is positioned on a channel region of the first active layer A1, having the first insulating layer Gl1and a second insulating layer G12, which are sequentially stacked on the first active layer A1, disposed therebetween. That is, the first insulating layer GI1and the second insulating layer GI2are positioned between the first gate electrode G1and the first active layer A1.

A first source electrode S1is connected to the driving power line ELVDDL through a fifth thin film transistor T5.

The first drain electrode D1is connected to the organic light emitting diode (OLED) through the sixth thin film transistor T6.

The second thin film transistor T2is connected between a data line DAm and the first thin film transistor T1, and when a scan signal is supplied from a first scan line SCn, the data signal supplied from the data line DAm is transferred into the pixel150. That is, the second thin film transistor T2serves as a switching transistor of the pixel150. The second thin film transistor T2includes a second active layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

The second active layer A2is positioned between the buffer layer BU formed on the substrate SUB and the first insulating layer GI1. When the second active layer A2is turned on by the second gate electrode G2, the second active layer A2connects between the data line DAm among the signal lines and the first thin film transistor T1.

The second gate electrode G2is connected to the first scan line SCn and is positioned on the channel region of the second active layer A2, having the first insulating layer GI1disposed therebetween. That is, the first insulating layer Gl1is positioned between the second gate electrode G2and the second active layer A2.

A second source electrode S2is connected to the data line DAm.

The second drain electrode D2is connected to the first source electrode S1of the first thin film transistor T1.

The third thin film transistor T3is connected between the first drain electrode D1and the first gate electrode G1of the first thin film transistor T1, and when the data signal is supplied to the pixel150, connects the first thin film transistor T1in a diode form to compensate for a threshold voltage of the first thin film transistor T1. That is, the third thin film transistor T3serves as a compensation transistor of the pixel150. The third thin film transistor T3includes a third active layer A3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3.

The third active layer A3is positioned between the buffer layer BU formed on the substrate SUB and the first insulating layer GI1.

The third gate electrode G3is connected to the first scan line SCn and is positioned on the same layer as the second gate electrode G2. That is, the first insulating layer Gl1is positioned between the third gate electrode G3and the third active layer A3.

The third source electrode S3is connected to the first gate electrode G1of the first thin film transistor T1.

The third drain electrode D3is connected to the first drain electrode D1of the first thin film transistor T1.

The fourth thin film transistor T4is connected between an initialization power line Vinit and the first gate electrode G1of the first thin film transistor T1and transfers the initialization power supplied from the initialization power line Vinit into the pixel150when the scan signal is supplied from a second scan line SCn−1 for an initialization period earlier than a data programming period to initialize the first thin film transistor T1so that the data signal may be smoothly supplied into the pixel150for the data programming period for which the data signal is input to the pixel150. That is, the fourth thin film transistor T4serves as the switching transistor of the pixel150. The fourth thin film transistor T4includes a fourth active layer A4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4.

The fourth active layer A4is positioned between the buffer layer BU formed on the substrate SUB and the first insulating layer GI1.

The fourth gate electrode G4is connected to the second scan line SCn−1 and is positioned on the same layer as the second gate electrode G2. That is, the first insulating layer Gl1is positioned between the fourth gate electrode G4and the fourth active layer A4.

A fourth source electrode S4is connected to the initialization power line Vinit.

The fourth drain electrode D4is connected to the first gate electrode G1of the first thin film transistor T1.

The fifth thin film transistor T5is connected between the driving power line ELVDDL and the first thin film transistor T1, cuts off the connection between the first power supply ELVDD and the first thin film transistor T1for a non-emission period of the pixel150, and connects the first power supply ELVDD and the first thin film transistor T1for the emission period of the pixel150. That is, the fifth thin film transistor T5serves as the switching transistor of the pixel150. The fifth thin film transistor T5includes a fifth active layer A5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5.

The fifth active layer A5is positioned between the buffer layer BU formed on the substrate SUB and the first insulating layer GI1.

The fifth gate electrode G5is connected to an emission control line En and is positioned on the same layer as the second gate electrode G2. That is, the fifth insulating layer Gl1is positioned between the fifth gate electrode G5and the fifth active layer A5.

The fifth source electrode S5is connected to the driving power line ELVDDL.

The fifth drain electrode D5is connected to the first source electrode S1of the first thin film transistor T1.

The sixth thin film transistor T6is connected between the first thin film transistor T1and the organic light emitting diode (OLED), cuts off the connection between the first thin film transistor T1and the organic light emitting diode (OLED) for the non-emission period of the pixel150, and connects between the first thin film transistor T1and the organic light emitting diode (OLED) for the emission period of the pixel150. That is, the sixth thin film transistor T6serves as the switching transistor of the pixel150. The sixth thin film transistor T6includes a sixth active layer A6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6.

The sixth active layer A6is positioned between the buffer layer BU formed on the substrate SUB and the first insulating layer GI1.

The sixth gate electrode G6is connected to the emission control line En and is positioned on the same layer as the second gate electrode G2. That is, the first insulating layer Gl1is positioned between the sixth gate electrode G6and the sixth active layer A6.

The sixth source electrode S6is connected to the first drain electrode D1of the first thin film transistor T1.

The sixth drain electrode D6is connected to the anode of the organic light emitting diode (OLED).

Each of the first source electrode S1to the sixth source electrode S6, and each of the first drain electrode D1to sixth drain electrode D6, of the first thin film transistor T1to sixth thin film transistor T6, respectively, of the display panel1000according to the exemplary embodiments of the present disclosure are formed on a layer different from the first active layer A1to the sixth active layer A6, respectively, to penetrate through the first insulating layer GI1, the second insulating layer GI2, the third insulating layer GI3, and the fourth insulating layer ILD so as to be connected to the first active layer A1to the sixth active layer A6, respectively. However, the exemplary embodiments of the present disclosure are not limited thereto, and each of the first source electrode to the sixth source electrode, and each of the first drain electrode to the sixth drain electrode, of the first thin film transistor to the sixth thin film transistor, respectively, of the organic light emitting diode display may be selectively formed on the same layer as the first active layer to the sixth active layer, respectively.

The first capacitor C1stores the data signal supplied into the pixel150for the data programming period and maintains the stored data signal for one frame, and is connected between the driving power line ELVDDL connected to the first power supply ELVDD and the first gate electrode G1of the first thin film transistor T1connected to the initialization power line Vinit. That is, the first capacitor C1serves as a storage capacitor. The first capacitor C1includes a first capacitor electrode CE1and a second capacitor electrode CE2.

The first capacitor electrode CE1is connected to the first gate electrode G1of the first thin film transistor T1connected to the initialization power line Vinit, and is positioned on the same layer as the first gate electrode G1.

The second capacitor electrode CE2is connected to the driving power line ELVDDL and is positioned on the first capacitor electrode CE1, having the third insulating layer G13stacked on the first gate electrode G1disposed therebetween. That is, the third insulating layer G13is positioned between the second capacitor electrode CE2and the first capacitor electrode CE1. As illustrated inFIG. 1, the second capacitor electrode CE2transverses the adjacent pixel150, and thus, may extend in a first direction.

The second capacitor C2compensates for a voltage drop due to a load in the display panel1000, and is connected between the first capacitor electrode CE1of the first capacitor C1and the first scan line SCn among gate wires GW. That is, the second capacitor C2increases a voltage of the first gate electrode G1of the first thin film transistor T1by a coupling action when the voltage level of the current scan signal is changed, in particular, when the supply of the current scan signal stops, and thus serves as a boosting capacitor compensating for the voltage drop due to the load in the display panel1000. The second capacitor C2includes a third capacitor electrode CE3and a fourth capacitor electrode CE4.

The third capacitor electrode CE3is connected to a first capacitor electrode CE1of the first capacitor C1and is positioned on the same layer as the first gate electrode G1.

The fourth capacitor electrode CE4is connected to the first scan line SCn among the gate wires GW and is positioned on the third capacitor electrode CE3, having the third insulating layer G13stacked on the first gate electrode G1disposed therebetween. That is, the third insulating layer G13is positioned between the fourth capacitor electrode CE4and the third capacitor electrode CE3.

As described above, the sixth drain electrode D6of the sixth thin film transistor T6of the pixel circuit152is connected to the organic light emitting diode (OLED).

The organic light emitting diode (OLED) includes an anode EL1which is positioned on the sixth drain electrode D6, having a fifth insulating layer PL disposed therebetween to be connected to the sixth drain electrode D6, an organic emission layer OL, and a cathode EL2connected to the second power supply ELVSS. A position of the organic emission layer OL may be determined by a pixel defined layer (PDL) and the cathode EL2may be positioned over the whole of the pixel defined layer (PDL).

In the display panel1000having the foregoing structure, the first gate electrode G1and the second gate electrode G2are disposed on different layers, having the second insulating layer GI2disposed therebetween.

The pixel circuit152of the display panel1000according to the exemplary embodiment of the present disclosure has a structure of six transistors and two capacitors. However, the exemplary embodiment of the present disclosure is not limited thereto, and the number of transistors and the number of capacitors may be different from the illustrated exemplary embodiment.

Hereinafter, the multi-layered wiring structure of the crack detection line according to the exemplary embodiments of the present disclosure will be described with reference toFIGS. 5 to 10.FIGS. 5 to 10are cross-sectional views schematically illustrating the crack detection line in a display panel according to the exemplary embodiment of the present disclosure.

Hereinafter, the multi-layered wiring structure of the first crack detection line CD1in the display panel1000ofFIG. 1will be described. The second crack detection line CD2has the multi-layered wiring structure having the same structure as the first crack detection line CD1, and therefore, the description thereof will be omitted.

FIG. 5is a cross-sectional view schematically illustrating the crack detection line according to an exemplary embodiment of the present disclosure.

Referring toFIG. 5, in the display panel1000according to an exemplary embodiment of the present disclosure, the crack detection line CD1includes a first conductive layer CD11, a second conductive layer CD12, a third conductive layer CD13, and a fourth conductive layer CD14that are stacked on different layers. Further, the crack detection line CD1includes a plurality of insulating layers IL11, IL12, and IL13, which are each disposed between the first conductive layer CD11and the second conductive layer CD12, between the second conductive layer CD12and the third conductive layer CD13, and between the third conductive layer CD13and the fourth conductive layer CD14.

The first and second conductive layers CD11and CD12form a conductive line and are stacked, having the insulating layer IL11disposed therebetween.

The first conductive layer CD11and the second conductive layer CD12are each formed on the same layer as the gate lines (not illustrated), which are each formed on different layers and are made of the same material as the gate electrode of the display panel1000.

Referring toFIG. 4as an example, the first conductive layer CD11is formed on the same layer as the second gate electrode G2in the pixel circuit152and is made of the same material as the second gate electrode G2. Further, the second conductive layer CD12is formed on the same layer as the first gate electrode G1in the pixel circuit152and is made of the same material as the first gate electrode G1. Further, the insulating layer IL11provided between the first conductive layer CD11and the second conductive layer CD12corresponds to the second insulating layer G12in the pixel circuit152ofFIG. 4.

The third conductive layer CD13is a conductive line and is stacked on the second conductive layer CD12, having the insulating layer IL12stacked on the second conductive layer CD12disposed therebetween.

The third conductive layer CD13is formed on the same layer as the data line (or source/drain electrode) (not illustrated) of the display panel1000and is made of the same material as the data line (or source/drain electrode).

Referring toFIG. 4as an example, the third conductive layer CD13is formed on the same layer as source/drain electrodes S1to S6and D1to D6in the pixel circuit152and is made of the same material as the source/drain electrodes S1to S6and D1to D6. Further, the insulating layer IL12provided between the second conductive layer CD12and the third conductive layer CD13corresponds to the third insulating layer GI3or the fourth insulating layer ILD in the circuit152.

The fourth conductive layer CD14is a conductive line and is stacked on the third conductive layer CD13, having the insulating layer IL13stacked on the third conductive layer CD13disposed therebetween.

The fourth conductive layer CD14is formed on the same layer as the cathode (not illustrated) of the organic light emitting diode (OLED) and is made of the same material as the cathode.

Referring toFIG. 4as an example, the fourth conductive layer CD14is formed on the same layer as the cathode EL2of the organic light emitting diode (OLED) and is made of the same material as the cathode EL2. Further, the insulating layer IL13provided between the third conductive layer CD13and the fourth conductive layer CD14corresponds to the fifth insulating layer PL or the pixel defined layer PDL.

When the cathode of the organic light emitting diode (OLED) is applied on the entire surface of the upper portion of the display panel1000, the fourth conductive layer CD14need not be formed as a separate wiring, and the cathode of the organic light emitting diode (OLED) may be used as the fourth conductive layer CD14.

The first conductive layer CD11and the third conductive layer CD13are electrically connected to each other through at least one contact hole (not illustrated).

The first conductive layer CD11and the third conductive layer CD13are connected between the first test signal line (see reference numeral DC_G ofFIG. 1) and the data line (see reference numeral DA1ofFIG. 1). That is, the first conductive layer CD11and the third conductive layer CD13have one end connected to the first test signal line DC_G and the other end connected to the data line DA1. Therefore, a first signal V11applied through the first test signal line DC_G is transferred to the data line DA1through the first conductive layer CD11and the third conductive layer CD13. The first signal V11is the detection signal V2ofFIG. 2and is a signal which light-emits the corresponding pixel black.

The first conductive layer CD11is formed on the same layer as the gate electrode, and is therefore formed on a different layer as the first test signal line DC_G and the data line DA1, which are formed on the same layer as the data line. Therefore, the first conductive layer CD11may be connected to the first test signal line DC_G and the data line DA1through at least one contact hole (not illustrated).

The third conductive layer CD13is formed on the same layer as the data line DA of the display panel1000and is therefore formed on the same layer as the first test signal line DC_G and the data line DA1. Therefore, the third conductive layer CD13may be directly connected to the first test signal line DC_G without a separate connecting member. Further, the third conductive layer CD13may be formed to intersect the remaining data lines DAs using a contact bridge (not illustrated) which is formed on a layer different from the data line DA so that the remaining data line DA which is not connected to the third conductive layer CD13is not connected to the third conductive layer CD13.

The second conductive layer CD12and the fourth conductive layer CD14are applied with the second signal V12having a different voltage level from the first signal V11.

The second signal V12may be a power signal that is applied from the second power supply ELVSS in the pixel circuit152ofFIG. 4. In this case, the cathode is connected to the second power supply ELVSS, and therefore, when the cathode of the organic light emitting diode (OLED) is used as the fourth conductive layer CD14, there is no need to additionally connect the fourth conductive layer CD14to the second power supply ELVSS. Further, the second conductive layer CD12may be connected to the fourth conductive layer CD14through at least one contact hole (not illustrated).

In the first crack detection line CD1of the multi-layered wiring structure illustrated inFIG. 5, when the first conductive layer CD11and the third conductive layer CD13that are connected to the data line DA1are damaged by a crack in the peripheral area of the display panel1000, a resistance of the crack detection line CD1is increased. Therefore, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel which is connected to the data line DA1through the crack detection line CD1is not charged up to the voltage level of the first signal V11. That is, the pixel connected to the data line DA1does not display a black color, but instead displays brightly.

Further, the insulating layers IL11, IL12, and IL13are destroyed as a result of the crack in the peripheral area of the display panel1000or when foreign particles are present in the insulating layers IL11, IL12, and IL13, and the first or third conductive layer CD11or CD13is shorted from the second or fourth conductive layer CD12or CD14adjacent thereto. Therefore, the first signal V11transferred to the data line DA1may be distorted, and thus, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel is not charged up to the voltage level of the first signal V11. That is, the pixel connected to the data line DA1does not display a black color, but instead displays brightly.

As described above, when the crack detection line CD1according to the exemplary embodiment of the present disclosure is applied, even in the case in which the crack detection line CD1is directly damaged due to a crack in the peripheral area of the display panel1000, as well as the insulating layer is destroyed or the foreign particles are present, it is possible for the crack detection line CD1to detect the defect in the display panel1000.

Meanwhile,FIG. 5illustrates, for example, the case in which the same signal V12applied to the second conductive layer CD12and the fourth conductive layer CD14, but exemplary embodiments of the present disclosure are not limited thereto. According to some of the exemplary embodiments of the present disclosure, as illustrated inFIG. 6, the second conductive layer CD12and the fourth conductive layer CD14may be applied with different signals V12and V13. In this case, the fourth conductive layer CD14is connected to the second power supply ELVSS to be applied with the second signal V12applied from the second power supply ELVSS. Further, the second conductive layer CD12is connected to a power pad (not illustrated) to be applied with the third signal V13from an external power supply through the power pad.

FIG. 7is a cross-sectional view schematically illustrating a crack detection line according to another exemplary embodiment of the present disclosure.

Referring toFIG. 7, in the display panel1000according to another exemplary embodiment of the present disclosure, the crack detection line CD1includes a first conductive layer CD31, a second conductive layer CD32, a third conductive layer CD33, and a fourth conductive layer CD34which are stacked on different layers. Further, the crack detection line CD1includes a plurality of insulating layers IL31, IL32, and IL33, which are each disposed between the first conductive layer CD31and the second conductive layer CD32, between the second conductive layer CD32and the third conductive layer CD33, and between the third conductive layer CD33and the fourth conductive layer CD34.

Meanwhile, an interlayer stacked structure of the crack detection line CD1ofFIG. 7is similar to that of the crack detection line according to the exemplary embodiment of the present disclosure illustrated inFIG. 5, and therefore, any redundant description thereof will be omitted below.

The first and second conductive layers CD31and CD32form a conductive line and are stacked, having the insulating layer IL31disposed therebetween.

The first conductive layer CD31and the second conductive layers CD31and CD32are each formed on the same layer as the gate electrodes (not illustrated), which are each formed on different layers in the display panel1000and are made of the same material as the gate electrode.

The third conductive layer CD33is a conductive line and is stacked on the second conductive layer CD32, having the insulating layer IL32stacked on the second conductive layer CD32disposed therebetween.

The third conductive layer CD33is formed on the same layer as the data line (or source/drain electrode) (not illustrated) of the display panel1000and is made of the same material as the data line (or source/drain electrode).

The fourth conductive layer CD34is a conductive line and is stacked on the third conductive layer CD33, having the insulating layer IL33stacked on the third conductive layer CD13disposed therebetween.

The fourth conductive layer CD34is formed on the same layer as the cathode (not illustrated) of the organic light emitting diode (OLED) and is made of the same material as the cathode.

The second conductive layer CD32is connected between the first test signal line (see reference numeral DC_G ofFIG. 1) and the data line (see reference numeral DA1ofFIG. 1). That is, the second conductive layer CD32has one end connected to the first test signal line DC_G and the other end connected to the data line DA1. Therefore, a first signal V31applied through the first test signal line DC_G is transferred to the data line DA1through the second conductive layer CD32. The first signal V31is the detection signal V2ofFIG. 2and is a signal which light-emits the corresponding pixel black.

The second conductive layer CD32is formed on the same layer as the gate electrode, and is therefore formed on a different layer from the first test signal line DC_G and the data line DA1, which are formed on the same layer as the data line. Therefore, the second conductive layer CD32may be connected to the first test signal line DC_G and the data line DA1through at least one contact hole (not illustrated).

The first conductive layer CD31and the third conductive layer CD33, which are formed on different layers, are electrically connected to each other through at least one contact hole (not illustrated). The first conductive layer CD31and the third conductive layer CD33are applied with the second signal V32having a different voltage level from the first signal V31.

The second signal V32may be a power signal which is applied from the second power supply ELVSS in the pixel circuit152ofFIG. 4. In this case, the first conductive layer CD31and the third conductive layer CD33are connected to the second power supply ELVSS through at least one contact hole (not illustrated) to be applied with the second signal V32from the second power supply ELVSS.

An external power supply may supply the second signal V32as a power signal. In this case, the first conductive layer CD31and the third conductive layer CD33are connected to the power pad (not illustrated) and receive the second signal V32applied from the external power supply through the power pad.

The fourth conductive layer CD34is applied with the third signal V33.

The third signal V33may be the same signal as the first signal V31. In this case, the fourth conductive layer CD34is connected to the second conductive layer CD32through at least one contact hole (not illustrated) to receive the first signal V31applied through the first test signal line DC_G.

The third signal V33may also be a power signal which is supplied from the second power supply ELVSS in the pixel circuit152ofFIG. 4. In this case, the cathode is connected to the second power supply ELVSS, and therefore, when the cathode of the organic light emitting diode (OLED) is used as the fourth conductive layer CD34, there is no need to additionally connect the fourth conductive layer CD34to the second power supply ELVSS.

The third signal V33may be a power signal applied from an external power supply. In this case, the third conductive layer CD33is connected to the power pad (not illustrated) through at least one contact hole and receives the third signal V33applied from the external power supply through the power pad.

In the first crack detection line CD1of the multi-layered wiring structure illustrated inFIG. 7, when the second conductive layer CD32, which is connected to the data line DA1, is damaged by the crack in the peripheral area of the display panel1000, the resistance of the crack detection line CD1is increased. Therefore, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel which is connected to the data line DA1is not charged up to the voltage level of the first signal V31. That is, the pixel connected to the data line DA1does not display a black color but instead displays brightly.

Further, the insulating layers IL31, IL32, and IL33are destroyed as a result of the crack in the peripheral area of the display panel1000or when the foreign particles are present in the insulating layers IL31, IL32, and IL33, and the second conductive layer CD32is shorted from the first or third conductive layer CD31or CD33adjacent thereto. Therefore, the first signal V31transferred to the data line DA1through the second conductive layer CD32may be distorted, and thus, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel is not charged up to the voltage level of the first signal V31. That is, the pixel connected to the data line DA1does not display a black color, but instead displays brightly.

As described above, when the crack detection line CD1having the structure illustrated inFIG. 7is applied, even in the case in which the crack detection line CD1is directly damaged due to the crack in the peripheral area of the display panel1000as well as the insulating layer is destroyed or the foreign particles are present, it is possible for the crack detection line CD1to detect of the defect in the display panel1000.

Meanwhile,FIG. 7illustrates, for example, the case in which the crack detection line CD1is the multi-layered wiring structure in which the four conductive layers and the three insulating layers are stacked, but the exemplary embodiment of the present disclosure is not limited thereto. According to some of the exemplary embodiments of the present disclosure, as illustrated inFIG. 8, the crack detection line CD1may be the multi-layered wiring structure in which the three conductive layers CD31, CD32, and CD33and the two insulating layers IL31and IL32are stacked.

FIG. 9is a cross-sectional view schematically illustrating a crack detection line according to another exemplary embodiment of the present disclosure.

Referring toFIG. 9, in the display panel1000according to another exemplary embodiment of the present disclosure, the crack detection line CD1includes a first conductive layer CD51, a second conductive layer CD52, a third conductive layer CD53, and a fourth conductive layer CD54, which are stacked on different layers. The crack detection line CD1includes a plurality of insulating layers IL51, IL52, and IL53, which are each disposed between the first conductive layer CD51and the second conductive layer CD52, between the second conductive layer CD52and the third conductive layer CD53, and between the third conductive layer CD53and the fourth conductive layer CD54.

Meanwhile, an interlayer stacked structure of the crack detection line CD1ofFIG. 9is similar to that of the crack detection line according to the exemplary embodiment of the present disclosure illustrated inFIG. 5, and therefore any redundant description thereof will be omitted below.

The first and second conductive layers CD51and CD52are a conductive line and are stacked, having the insulating layer IL51disposed therebetween.

The first conductive layer CD51and the second conductive layer CD52are each formed on the same layer as the gate electrodes (not illustrated) which are formed on different layers in the display panel1000and are made of the same material as the gate electrode.

The third conductive layer CD53is a conductive line and is stacked on the second conductive layer CD52, having the insulating layer IL52stacked on the second conductive layer CD52disposed therebetween.

The third conductive layer CD53is formed on the same layer as the data line (or source/drain electrode) (not illustrated) and is made of the same material as the data line (or source/drain electrode).

The fourth conductive layer CD54is a conductive line and is stacked on the third conductive layer CD53, having the insulating layer IL53stacked on the third conductive layer CD53disposed therebetween.

The fourth conductive layer CD54is formed on the same layer as the cathode (not illustrated) of the organic light emitting diode (OLED), and is made of the same material as the cathode. When the cathode of the organic light emitting diode (OLED) is applied over the entire surface of the upper portion of the display panel1000, the fourth conductive layer CD54may not be formed as a separate wiring, and the cathode of the organic light emitting diode (OLED) may be used as the fourth conductive layer CD54.

The second conductive layer CD52and the third conductive layer CD53, which are formed on different layers, are electrically connected to each other through the contact hole (not illustrated).

The second conductive layer CD52and the third conductive layer CD53are connected between the first test signal line (see reference numeral DC_G ofFIG. 1) and the data line (see reference numeral DA1ofFIG. 1). That is, the second conductive layer CD52and the third conductive layer CD53have one end connected to the first test signal line DC_G and the other end connected to the data line DA1. Therefore, a first signal V51applied through the first test signal line DC_G is transferred to the data line DA1through the second conductive layer CD52and the third conductive layer CD53. The first signal V51is the detection signal V2ofFIG. 2and is a signal which light-emits the corresponding pixel black.

The second conductive layer CD52is formed on the same layer as the gate electrode, and therefore, is formed on a different layer from the first test signal line DC_G and the data line DA1, which are formed on the same layer as the data line. Therefore, the second conductive layer CD52may be connected between the first test signal line DC_G and the data line DA1through at least one contact hole (not illustrated).

The third conductive layer CD53is formed on the same layer as the test signal line DC_G and the data line DA1. Therefore, the third conductive layer CD53may be directly connected to the first test signal line DC_G without a separate connecting member. Further, the third conductive layer CD53may be formed to intersect the data lines DAs using a contact bridge (not illustrated), which is formed on a layer different from the data line DA so that the remaining data line DA which is not connected to the third conductive layer CD53is not connected to the third conductive layer CD53.

The first conductive layer CD51and the fourth conductive layer CD54are applied with the second signal V52having a different voltage level from the first signal V51.

The second signal V51may be a power signal applied from an external power supply. In this case, the first conductive layer CD51and the fourth conductive layer CD54are connected to the power pad (not illustrated) and receive second signal V52applied from the external power supply through the power pad.

The second signal V52may also be a power signal which is supplied from the second power supply ELVSS in the pixel circuit152ofFIG. 4. In this case, the cathode is connected to the second power supply ELVSS, and therefore, when the cathode of the organic light emitting diode (OLED) is used as the fourth conductive layer CD54, there is no need to additionally connect the fourth conductive layer CD54to the second power supply ELVSS. Further, the first conductive layer CD51is connected to the fourth conductive layer CD54through the contact hole (not illustrated) to receive the second signal V52from the second power supply ELVSS.

In the first crack detection line CD1of the multi-layered wiring structure illustrated inFIG. 9, when the second conductive layer CD52and the third conductive layer CD53which are connected to the data line DA1are damaged by the crack in the peripheral area of the display panel1000, a resistance of the crack detection line CD1is increased. Therefore, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel which is connected to the data line DA1through the crack detection line CD1is not charged up to the voltage level of the first signal V51. That is, the pixel connected to the data line DA1does not display a black color but instead displays brightly.

Further, the insulating layers IL51, IL52, and IL53are destroyed due to the crack in the peripheral area of the display panel1000or when the foreign particles are present in the insulating layers IL51, IL52, and IL53, and the second conductive layer CD52or the third conductive layer CD53is shorted from the first or fourth conductive layer CD51or CD54adjacent thereto. Therefore, the first signal V51transferred to the data line DA1may be distorted, and thus, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel is not charged up to the voltage level of the first signal V51. That is, the pixel connected to the data line DA1does not display a black color, but instead displays brightly.

FIG. 10is a cross-sectional view schematically illustrating a crack detection line according to another exemplary embodiment of the present disclosure.

Referring toFIG. 10, in the display panel1000according to another exemplary embodiment of the present disclosure, the crack detection line CD1includes a first conductive layer CD71, a second conductive layer CD72, a third conductive layer CD73, and a fourth conductive layer CD74which are stacked on different layers. Further, the crack detection line CD1includes a plurality of insulating layers IL71, IL72, and IL73which are each disposed between the first conductive layer CD71and the second conductive layer CD72, between the second conductive layer CD72and the third conductive layer CD73, and between the third conductive layer CD73and the fourth conductive layer CD74.

Meanwhile, an interlayer stacked structure of the crack detection line CD1ofFIG. 10is similar to that of the crack detection line according to the exemplary embodiment of the present disclosure illustrated inFIG. 5, and therefore any redundant description thereof will be omitted below.

The first and second conductive layers CD71and CD72are a conductive line and are stacked, having the insulating layer IL71disposed therebetween.

The first conductive layer CD71and the second conductive layer CD72are each formed on the same layer as the gate electrodes (not illustrated), which are formed on different layers and are made of the same material as the gate electrode.

The third conductive layer CD73is a conductive line and is stacked on the second conductive layer CD72, having the insulating layer IL72stacked on the second conductive layer CD72disposed therebetween.

The third conductive layer CD73is formed on the same layer as the data line (or source/drain electrode) (not illustrated) and is made of the same material as the data line (or source/drain electrode).

The fourth conductive layer CD74is a conductive line and is stacked on the third conductive layer CD73, having the insulating layer IL73stacked on the third conductive layer CD73disposed therebetween.

The fourth conductive layer CD74is formed on the same layer as the cathode (not illustrated) of the organic light emitting diode (OLED), and is made of the same material as the cathode. When the cathode of the organic light emitting diode (OLED) is applied over the entire surface of the upper portion of the display panel1000, the fourth conductive layer CD74may not be formed as a separate wiring and the cathode of the organic light emitting diode (OLED) may be used as the fourth conductive layer CD74.

The first, second, and third conductive layers CD71, CD72, and CD73which are formed on different layers are electrically connected to one another through at least one contact hole (not illustrated). The first conductive layer CD71, the second conductive layer CD72, and the third conductive layer CD73are connected between the first test signal line (see reference numeral DC_G ofFIG. 1) and the data line (see reference numeral DA1ofFIG. 2). That is, the first, second, and third conductive layers CD71, CD72, and CD73have one end connected to the first test signal line DC_G and the other end connected to the data line DA1. Therefore, a first signal V71applied through the first test signal line DC_G is transferred to the data line DA1through the first, second, and third conductive layers CD71, CD72, and CD73. The first signal V71is the detection signal V2ofFIG. 2and is a signal which light-emits the corresponding pixel black.

The first and second conductive layers CD72are formed on the same layer as the gate electrode, and are therefore formed on a different layer from the first test signal line DC_G and the data line DA1, which are formed on the same layer as the data line. Therefore, the first and second conductive layers CD72may be connected between the first test signal line DC_G and the data line DA1through at least one contact hole (not illustrated).

The third conductive layer CD73is formed on the same layer as the test signal line DC_G and the data line DA1. Therefore, the third conductive layer CD73may be directly connected to the first test signal line DC_G without a separate connecting member. Further, the third conductive layer CD73may be formed to intersect the data lines DAs using a contact bridge (not illustrated) which is formed on a layer different from the data line DA so that the remaining data line DA which is not connected to the third conductive layer CD73is not connected to the third conductive layer CD73.

The fourth conductive layer CD74is applied with the second signal V72having a different voltage level from the first signal V71.

The second signal V72may be a power signal supplied from an external power supply. In this case, the fourth conductive layer CD74is connected to the power pad (not illustrated) and receives the second signal V72applied from the external power supply through the power pad.

The second signal V72may be a power signal which is supplied from the second power supply ELVSS in the pixel circuit152ofFIG. 4. In this case, the cathode is connected to the second power supply ELVSS, and therefore when the cathode of the organic light emitting diode (OLED) is used as the fourth conductive layer CD74, there is no need to additionally connect the fourth conductive layer CD74to the second power supply ELVSS.

In the crack detection line CD1having the multi-layered wiring structure illustrated inFIG. 10, when the first, second, and third conductive layers CD71, CD72, and CD73, which are connected to the data line DA1, are damaged by the crack in the peripheral area of the display panel1000, the resistance of the crack detection line CD1is increased.

Therefore, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel which is connected to the data line DA1is not charged up to the voltage level of the first signal V71. That is, the pixel connected to the data line DA1does not display a black color, but instead displays brightly.

Further, as the insulating layer IL73between the third conductive layer CD73and the fourth conductive layer CD74is destroyed as a result of the crack in the peripheral area of the display panel1000or includes foreign particles, when the third insulating layer CD73is shorted from the fourth conductive layer CD74, the first signal V71transferred to the data line DA1is distorted by the second signal V72.

Therefore, the voltage (see reference numeral V_T ofFIG. 2) applied to the pixel is not charged up to the voltage level of the first signal V71. That is, the pixel connected to the data line DA1does not display a black color, but instead displays brightly.

According to an exemplary embodiment of the present disclosure, it is possible to detect damage of the display panel occurring resulting from the case in which the crack detection line is directly damaged due to the occurrence of crack in the peripheral area of the display panel, the destruction of the insulating layer, or the presence of foreign particles between the layers.