Storage device, information processing system, method of activating storage device and program

A storage device includes a first memory which stores data including activation data necessary to activate a host device, a second memory, and a controller which performs writing and reading operation of data stored in the first memory based on a request from the host device; acquires address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, reads data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmits the data stored in the second memory to the host device.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Japanese Patent Application No. 2016-138348, filed on Jul. 13, 2016, the entire subject matter of which is incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a storage device which stores activation data necessary to activate a host device, an information processing system, an activation method of the storage device and a program.

BACKGROUND ART

A host device including an industrial device such as a Multi-Function Peripheral (MFP) includes therein or is connected via an external interface to a storage device which stores activation data such as boot loader necessary to activate the host device.

When the host device having the storage device connected thereto is activated, the host device transmits to the storage device a read request command of the activation data such as boot loader stored in the storage device, and the storage device reads the activation data stored therein and transmits the same to the host device, in response to the read request command.

Since an Operating System (OS) for controlling the host device, work data and the like are also usually stored in the storage device, the storage device is required to have a large capacity and to be non-volatile. Therefore, as the related-art storage device, a Hard Disc Drive (HDD) device or a Solid State Drive (SSD) device using a NAND flash memory is used. A read speed of the HDD device or the SSD device is slower than a volatile memory that is to be used for a Random Access Memory (RAM). For this reason, a certain length of time is required to activate the host device.

In particular, as processes of the NAND flash memory evolve, a capacity of one chip increases, so that the number of chips necessary for the SSD device having the same capacity tends to decrease. The reduction in the number of chips necessary for the SSD device may result in a decrease of a parallel processing speed using a plurality of chips (i.e. a simultaneous read processing speed). For this reason, it is required to shorten the activation time of the host device to which the storage device having the activation data stored therein is connected.

In the meantime, there has been suggested a method of transmitting the activation data such as boot loader stored in the storage device to the RAM of the host device at the activation of the host device (for example, refer to JP-A-2007-299242 or JP-A-2003-337746). According to the method disclosed in JP-A-2007-299242 or JP-A-2003-337746, a special configuration is added to an existing storage device, so that the activation data is transmitted to the RAM of the host device. Therefore, it is difficult to apply this method to the existing storage device.

SUMMARY

According to an aspect of the disclosure, there is provided a storage device including: a first memory configured to store data including activation data necessary to activate a host device, an access position of the data being managed based on an address; a second memory; and a controller configured to: perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device; acquire address information including the address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, read data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmit the data stored in the second memory to the host device.

According to another aspect of the disclosure, there is provided an information processing system including the host device configured to perform an activation operation by using activation data, and a storage device including: a first memory configured to store data including activation data necessary to activate a host device, an access position of the data being managed based on an address; a second memory; and a controller configured to: perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device; acquire address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, read data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmit the data stored in the second memory to the host device.

According to a further aspect of the disclosure, there is provided an activation method of a storage device including a first memory which stores therein data including activation data necessary to activate a host device, an access position of the data being managed based on an address, a second memory, and a controller configured to perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device. The method includes: acquiring address information including the address and a data amount of the data in the first memory, for which a read request is previously issued from the host device; at activation of the storage device, reading data including at least the activation data from the first memory based on the address information and storing the data in the second memory; and in response to a read request issued from the host device, transmitting the data stored in the second memory to the host device.

According to a still further aspect of the disclosure, there is provided a non-transitory computer-readable recording medium having a program stored therein, the program being executed by a computer including a first memory which stores therein activation data necessary to activate a host device, an access position of the data being managed based on an address, a second memory, and a controller configured to perform a writing operation and a reading operation of data stored in the first memory based on a request from the host device. When the program is executed by the computer, the program causes the controller to; acquire address information including the address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, read data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmit the data stored in the second memory to the host device.

DETAILED DESCRIPTION

The disclosure has been made in view of the above circumstances and provides a storage device that can be applied to an existing storage device and shorten an activation time of a host device, an information processing system, an activation method of the storage device and a program.

Illustrative Embodiment

Hereinafter, an illustrative embodiment of the disclosure will be described with reference to the drawings.

(Configuration of SSD Device of Illustrative Embodiment)

FIG. 1is a block diagram illustrating a schematic configuration of an illustrative embodiment in which the storage device of the disclosure is applied to an SSD device, andFIG. 2is a block diagram illustrating a functional configuration of the SSD device according to the illustrative embodiment.

InFIGS. 1 and 2, an SSD device10includes a controller11, a Random Access Memory (RAM)12, a Read Only Memory (ROM)13and a flash memory14. The SSD device10is connected to a host device20, which is an MFP in the illustrative embodiment, and is configured to store predetermined data therein in accordance with a write command from the host device20and to transmit the predetermined data in accordance with a read command.

The controller11is configured to control the SSD device10and has a Central Processing Unit (CPU)15, a host interface (I/F)16, a flash interface (I/F)17, a RAM interface (I/F)18and a ROM interface (I/F)19.

The CPU15is configured to control the controller11and the SSD device10as firmware (not shown inFIG. 1) stored in the ROM13is developed into the RAM12at the power-on and is executed and has functions indicated in respective functional units shown inFIG. 2. The respective functional units shown inFIG. 2will be described later. The host I/F16is connected to the host device20via a predetermined external interface and is configured to transmit and receive data to and from the host device20based on a protocol determined by the external interface and a command, under control of the CPU15. In the illustrative embodiment, the host I/F16and the host device20are connected to each other by an interface such as ATA and SCSI, which is used for an HDD and the like and has general versatility. The flash I/F17is connected to the flash memory14and is configured to perform operations of writing and reading data to and from the flash memory14under control of the CPU15. The RAM I/F18is connected to the RAM12and is configured to perform operations of writing and reading data to and from the RAM12under control of the CPU15. The ROM I/F19is connected to the ROM13and is configured to perform an operation of reading data from the ROM13under control of the CPU15.

The RAM12is used as a work memory of the controller11and is configured to temporarily store therein a variety of data. Also, the RAM12may store address information including an address of the flash memory14, for which a read request is previously issued from the host device20at the activation of the host device20, and a data amount of data for which the read request is previously issued, and data including activation data necessary to activate the host device20(not shown inFIG. 1). For this reason, preferably, the RAM12has a large capacity of about 200 MB. The address information and the activation data will be described later in detail. As described above, the ROM13stores the firmware for controlling the SSD device10.

In the illustrative embodiment, the flash memory14is a NAND-type flash memory. Also, a space in the flash memory14is perceived by a Logical Block Addressing (LBA) and a physical block, and the host device20is configured to access data in a specific area by directly designating the logical block addressing. When the logical block addressing is directly designated from the host device20, the controller11specifies a physical block, which is to be actually accessed, by referring to a logical block addressing-physical block conversion table (not shown) stored in the RAM12, and accesses the physical block. Meanwhile, in the descriptions of the illustrative embodiment, the logical block addressing may also be simply referred to as “address”.

Meanwhile, in the flash memory14according to the illustrative embodiment, one physical block has a plurality of pages, and a data writing operation is performed in a unit of a page and a data erasing operation is performed in a unit of a block. Also, each page consists of a plurality of sectors.

(Functional Configuration of SSD Device of Illustrative Embodiment)

FIG. 2is a block diagram illustrating a functional configuration of the SSD device10according to the illustrative embodiment. The SSD device10according to the illustrative embodiment has the controller11, a first memory, which is the flash memory14, a second memory, which is the RAM12, and a third memory, which is the ROM13.

The controller11is configured to mainly control reading and writing operations of data from and to the first memory14and is connected to the host device20via the interface such as ATA and SCSI, which has general versatility. The controller11is configured to receive a read request command, a writing request command and data to be written, which are to be transmitted from the host device20, and to read data stored in the first memory14, to write data and to transmit the read data to the host device20, based on the commands. The controller11is configured to control reading and writing operations of data from and to the second memory12and the third memory13connected to the controller11.

Particularly, the controller11according to the illustrative embodiment is configured to acquire address information31including an address of the first memory14, for which a read request is previously issued from the host device20at the activation of the host device20, and a data amount of data, for which the read request is previously issued. Also, the controller11is configured to read data, which includes at least activation data32, from the first memory14by using the address information31and to store the read data in the second memory12, at activation of the SSD device10. When a read request is issued from the host device20, the controller11transmits the data including the activation data32and stored in the second memory12to the host device20. The operations of the controller11will be again described later in detail.

Herein, preferably, the controller11is configured to store the address information31in the second memory12. More preferably, whenever the read request command is received from the host device20, the controller11is configured to store the address of the first memory14, for which the read request is previously issued from the host device20, and the data amount of data, for which the read request is previously issued, in the second memory12.

Preferably, the controller11is configured to store the address information31stored in the second memory12in a specific address of the first memory14at a predetermined timing. Also, preferably, the predetermined timing is a timing at which a writing request is issued from the host device20or a timing at which a predetermined amount of address information, for example, address information corresponding to thousands of commands is stored in the second memory12.

Also, the controller11is preferably configured to access the specific address of the first memory14at the activation of the SSD device10and to acquire the address information31. The specific address will be described later in detail.

In the first memory14, the address information31, the activation data32and work data33are stored.

As described above, the address information31includes the address of the first memory14for which the read request is previously issued from the host device20at the activation of the host device20and the data amount of data for which the read request is previously issued. Herein, the address information31is preferably configured so that sets of logical block addressing of read start positions of data and data amounts of data to be read from the logical block addressings are arranged in order of the read requests from the host device20. Also, the address information31is preferably configured so that sets of management unit addresses, in which the logical block addressing of the read start position of the data is delimited to a size of a management unit of the first memory14in the controller11, and management unit data amounts, in which the data amount of data to be read from the management unit address is delimited in a unit of the size, are arranged in order of the read requests from the host device20.

The address information31is preferably stored in a specific address of the first memory14. The specific address includes an address described in advance in a firmware34(which will be described later), an address in a non-user area (management area) of the first memory14, i.e., in an area under management of an Operating System (OS) of the host device20, and an address, which is not normally used by the OS of the host device20and an application program, of a user area. Also, as the address that is not normally used, an address corresponding to LBA 0x0001, which is a next address of a Master Boot Record (MBR), or a final LBA+1 may be exemplified.

As described above, the activation data32is data necessary to activate the host device20and includes at least boot loader and data, which is necessary at the activation of the host device20, of the OS. The activation data32is stored in a predetermined address of the first memory14, and the host device20can perceive the address of the first memory14in which the activation data32is stored and a read amount of data including the activation data32. The work data33is data that is to be stored at operation of the host device20.

The second memory12stores the address information31and the activation data32as necessary. However, the address information31and the like are temporarily stored in the second memory12at a predetermined timing and the activation data32is transmitted to the host device20at a predetermined timing, as described later in detail. Herein, a data read speed of the second memory12is preferably faster than a data read speed of the first memory14, and is more preferably close to a data transfer speed from the controller11to the host device20.

In the third memory13, the firmware34is stored.

In the above descriptions, the controller11is implemented by the CPU15, the first memory14is implemented by the flash memory14, the second memory12is implemented by the RAM12and the third memory13is implemented by the ROM13.

(Details of Address Information of Illustrative Embodiment)

In the below, the address information31that is to be stored in the first memory14and the second memory12of the SSD device10according to the illustrative embodiment is described with reference toFIGS. 8 to 10.

FIG. 8illustrates an example of the address information31of the SSD device10according to the illustrative embodiment. The address information31shown inFIG. 8includes a logical block addressing area31a, in which a read start Logical Block Addressing (LBA) of the first memory14in the read request command from the host device20is described, and a sector count area31bin which a read data amount of data from the read start logical block addressing is described as a number of sectors (SectorCount). In each area, a set of the read start logical block addressing and the number of sectors is stored in arrival order of the read request command from the host device20.

FIG. 9illustrates another example of the address information31of the SSD device10according to the illustrative embodiment. The address information31shown inFIG. 9includes a management address area31c, in which a management address (UnitAddress) where a read start logical block addressing of the first memory14in the read request command from the host device20is delimited to a management size unit (4 KB in the example ofFIG. 9) of the first memory14by the firmware34of the SSD device10is described, and a management size area31din which a read amount of data from the management address is described in the management size unit (Size). In each area, a set of the management address and the management size is stored in arrival order of the read request command from the host device20.

FIG. 10illustrates still another example of the address information31of the SSD device10according to the illustrative embodiment. Like the address information31shown inFIG. 9, the address information31shown inFIG. 10includes a management address area31e, in which a management address (UnitAddress) where a read start logical block addressing of the first memory14in the read request command from the host device20is delimited to a management size unit of the first memory14by the firmware34of the SSD device10is described, and a management size area31fin which a read amount of data from the management address is described in the management size unit (Size). In the address information31ofFIG. 10, when data is continuously or redundantly read from the read start address for which the read request is issued from the host device20, a management size of data to be read is increased to collectively describe the management addresses. For instance, in the example ofFIG. 10, when the read request, which is the same as the example ofFIG. 9, is issued from the host device20, since the management addresses ofFIG. 9are continuous addresses of7hto Ah, the management size, which is a data read amount from the management address7h, is described as4h, so that the management addresses to be described in the management address area31eare collectively described.

However, in the example ofFIG. 10, as described later, when temporarily storing the read request command from the host device20in the second memory12, it is checked whether the management addresses are continuous, and the management addresses are then collectively described when it is determined that the management addresses are continuous. Therefore, the determination as to whether the management addresses are redundant or continuous may be limited to two previous commands.

Also, in the address information31ofFIGS. 8 to 10, the read start address, the data amount and the like are described in arrival order of the read request command from the host device20. However, considering the efficiency of reading the activation data32from the first memory14, the read start address may be rearranged in ascending order (or in descending order). However, when the power of the SSD device10is cutoff while rearranging the address information31, the address information31itself may be damaged. Therefore, the read start address and the like are preferably stored in arrival order of the read request command from the host device20.

In the meantime, since the read data amount of the address information31ofFIGS. 8 to 10has the sector unit or the management size unit, the data read based on the address information31may include data, in addition to the activation data32. However, even when the read data includes data, in addition to the activation data32, a particular problem is not caused.

(Outline of Operations of SSD Device of Illustrative Embodiment)

Subsequently, an outline of operations of the SSD device10according to the illustrative embodiment is described with reference toFIGS. 3 and 4.FIGS. 3 and 4illustrate examples of the operations of the SSD device according to the illustrative embodiment, in whichFIG. 3illustrates the operations of the SSD device at an initial activation andFIG. 4illustrates the operations of the SSD device at a normal activation. Herein, the description “at the initial activation” indicates a state where collection of the address information31and storing of the same into the first memory14are not performed, and the description “at the normal activation” indicates a state where the address information31is already stored in the first memory14.

The operations ofFIG. 3are performed at the initial activations of the host device20and the SSD device10. First, as shown with an arrow A inFIG. 3, when the power is fed to the host device20and the operation of the host device20starts, a read request for the activation data32stored in the first memory14of the SSD device10is transmitted from the host device20to the SSD device10by the operations of the firmware and the like in the host device20.

The controller11of the SSD device10accesses the first memory14and reads the activation data32based on the read request from the host device20, as shown with an arrow B inFIG. 3, and transmits the activation data32to the host device20, as shown with an arrow C inFIG. 3. In parallel with the operations, as shown with an arrow D inFIG. 3, the controller11of the SSD device10arranges the address of the first memory14for which the read request is issued from the host device20and the data amount of data for which the read request is issued, in order of the read request from the host device20, and stores the same in the second memory12.

Then, when the predetermined timing comes, the controller11of the SSD device10stores the address information31stored in the second memory12in the specific address of the first memory14, as shown with an arrow E ofFIG. 3.

Subsequently, the operations ofFIG. 4are performed at the normal activations of the host device20and the SSD device10. First, w en the power is fed to the SSD device10and the operation of the SSD device10starts, the firmware34stored in the third memory13of the SSD device10is executed. By the operations of the firmware34, the controller11of the SSD device10reads the address information31stored in the specific address of the first memory14and stores the address information31in the second memory12, as shown with an arrow F inFIG. 4. Then, the controller11reads the address information31stored in the second memory12, as shown with an arrow G inFIG. 4, reads the activation data32stored in the first memory14, based on the address information31, as shown with an arrow H inFIG. 4, and stores the activation data32in the second memory12, as shown with an arrow J inFIG. 4.

Usually, the read request command from the host device20arrives at the SSD device10after the activation of the firmware of the host device20is over, for example (refer to an arrow K inFIG. 4). For this reason, the controller11of the SSD device10issues an instruction to transmit to the host device20data, which corresponds to the read request command from the host device20, of the activation data32read from the first memory14and stored in the second memory12, in response to the read request command from the host device20, as shown with an arrow L inFIG. 4, and transmits the data to the host device20, as shown with an arrow M inFIG. 4.

Since the first memory14according to the illustrative embodiment is a NAND-type flash memory and the second memory12is a RAM, which is a volatile memory, the data read speed of the second memory12is faster than the data read speed of the first memory14. As shown inFIG. 4, the activation data32is read in advance from the first memory14and is transmitted to the second memory12, so that when the read request command is received from the host device20, the activation data32stored in the second memory12is transmitted to the host device20. Thereby, as compared to a configuration where whenever the read request command from the host device20arrives, the first memory14is accessed and the activation data32is read, it is possible to transmit the activation data32to the host device20at a higher speed, so that it is possible to shorten the activation time of the host device20.

(Operations of SSD Device of Illustrative Embodiment)

Subsequently, the operations of the SSD device10according to the illustrative embodiment are described with reference to flowcharts shown inFIGS. 5 to 7.

First,FIG. 5is a flowchart for illustrating the operations of the SSD device10according to the illustrative embodiment at the initial activation.

The operations shown in the flowchart ofFIG. 5start when the power is fed to the SSD device10. First, in step S1, the controller11reads the firmware34stored in the third memory13, and develops and executes the firmware34into the second memory12.

In step S2, the controller11receives the read request command from the host device20. In step S3, the controller11stores the address of the first memory14for which the read request is issued from the host device20in step S2and the data amount of data for which the read request is issued, in the second memory12.

In step S4, the controller11accesses the first memory14and reads the activation data32therefrom in accordance with the read request command from the host device20. In step S5, the controller11transmits the activation data32read from the first memory14to the host device20.

In step S6, it is determined whether a writing request command from the host device20is arrived at the SSD device10. When it is determined that the writing request command is arrived (YES in step S6), the program proceeds to step S7, and when it is determined that the writing request command is not arrived (NO in step S6), the program returns to step S2and repeats the operations of steps S2to S6.

In step S7, the controller11stores a set of the address of the first memory14stored in the second memory12and the data amount of data for which the read request is issued, in the specific address of the first memory14. Thereby, the address information31in which the address of the first memory14for which the read request is issued from the host device20and the data amount of data for which the read request is issued are arranged in order of the read request from the host device20is stored in the specific address of the first memory14.

FIGS. 6 and 7are flowcharts for illustrating the operations of the SSD device10according to the illustrative embodiment at the normal activation.

The operations shown in the flowchart ofFIG. 6start when the power is fed to the SSD device10. First, in step S10, the controller11reads the firmware34stored in the third memory13, and develops and executes the firmware34into the second memory12.

In step S11, the controller11reads the address information31stored in the specific address of the first memory14. Then, in step S12, the controller11reads the activation data32from the first memory14based on the address information31read in step S11, and in step S13, stores the activation data32read in step S12in the second memory12.

In step S14, the controller11receives a read request command from the host device20. In step S15, the controller11stores the address of the first memory14for which the read request is issued from the host device20in step S2and the data amount of data for which the read request is issued, in the second memory12.

In step S16, the controller11accesses the second memory12and reads the activation data32in accordance with the read request command from the host device20. Then, in step S17, the controller11transmits the activation data32read from the second memory12to the host device20.

In step S18, it is determined whether the writing request command from the host device20is arrived at the SSD device10. When it is determined that the writing request command is arrived (YES in step S18), the program proceeds to step S19. When it is determined that the writing request command is not arrived (NO in step S18), the program returns to step S14and repeats the operations of steps S14to S18.

In step S19, the controller11stores a set of the address of the first memory14stored in the second memory12and the data amount of data for which the read request is issued, in the specific address of the first memory14.

Meanwhile, when the writing request command (step S14) from the host device20is at the SSD device10before the operation of storing the activation data32in the second memory12(step S13inFIG. 6), the read request command from the host device20is preferably preferentially processed.

(Effects of SSD Device of Illustrative Embodiment)

As described above in detail, the SSD device10according to the illustrative embodiment is configured to first read the activation data32stored in the first memory14at the activation of the SSD device10and to store the same in the second memory12. Then, when the read request command from the host device20to the SSD device10arrives, the SSD device10transmits the activation data32stored in the second memory12to the host device20, in response to the read request command. The timing at which the read request command from the host device20arrives is usually after the firmware of the host device20is activated and a predetermined time lag occurs after the SSD device10is activated. For this reason, the activation data32is read and written in the second memory12during the time lag, so that when the read request command from the host device20to the SSD device10arrives, the activation data32can be immediately transmitted to the host device20. Therefore, it is possible to shorten the activation time of the host device20.

In addition, since the data read speed of the second memory12is faster than the data read speed of the first memory14, it is possible to transmit the activation data32to the host device20at higher speed, as compared to a configuration where the first memory14is accessed and the activation data32is read whenever the read request command from the host device20arrives. As a result, it is possible to shorten the activation time of the host device20.

Further, the SSD device10according to the illustrative embodiment can shorten the activation time of the host device20without adding the special hardware to an existing SSD device.

From the above descriptions, according to the illustrative embodiment, it is possible to implement the SSD device10that can be applied to an existing storage device and can shorten the activation time of the host device.

Modified Embodiments

In the meantime, the storage device of the disclosure is not limited to the illustrative embodiment, and a variety of modified embodiments can be made. For example, in the illustrative embodiment, the address information31and the activation data32are stored in the RAM12, which is a volatile memory. However, a non-volatile memory such as a Magnetoresistive Random Access Memory (MRAM) may be prepared as the second memory, and the address information31and the activation data32may stored in the non-volatile memory.