Method and apparatus for a segmented on-chip digital interface block

A method and architecture for operating with distributed (or segmented) on-chip digital interfaces such as the Inter-Integrated Circuit protocol and a Serial Peripheral Interface protocol. This method and architecture, illustratively, divides the available address space of the digital interface register arrays of a device into one or more segments referred to as a fundamental digital interface circuit. Such segmentation allows for each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection and for exchanging communication in accordance with a plurality of inputs to the device.

TECHNICAL FIELD

The present invention relates generally to integrated circuits that utilize bus communications, and more particularly, to integrated circuits that utilize on-chip digital interface blocks operating in accordance with particular bus/protocol standards.

BACKGROUND

Today, in the digital era, modern electronic devices utilize a variety of integrated circuits (ICs) to deliver the powerful and myriad of functions and applications available from such devices. It is not uncommon for such devices to have numerous ICs configured therein to cooperate and communicate in an orderly way to exchange information (e.g., receive and/or transmit different types of data and/or information) among themselves and between other external devices and/or the user of the device.

Central to such communications between and among these ICs is the ability of one IC to send data or other information to another IC (or ICs) in response to, for example, a query signal from another IC. These point-to-point interfaces typically occur across a bus structure that serves as a common communication channel for a plurality of ICs configured within the device. This bus structure can be facilitated by either custom communications interfaces or standardized interfaces that provide a standardized communication link.

One such standardized bus system is the so-called Inter-Integrated Circuit bus or the I2C bus. The I2C is a multi-master, multi-slave, single-ended, serial computer bus protocol and system. The I2C bus operates on a protocol that allows a plurality of ICs to be connected to and in communication with one another over a common bus structure. More particularly, I2C is a serial bus protocol that allows various ICs or other components within a device to communicate with one another where each IC or component is assigned a unique address. As such, the I2C system grows as more types of ICs are uniquely registered. The I2C system then employs such unique addresses to send and/or receive data to and/or from a particular IC.

Another well-known bus communications standard is the so-called Serial Peripheral Interface (SPI) bus. The SPI bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems, by microcontrollers for communicating with one or more peripheral devices. In accordance with SPI, there is always one master device (typically a microcontroller) which controls the peripheral devices and there are typically three common lines and one line specific for each device. SPI is sometimes referred to as a so-called four-wire serial bus, contrasting it with three, two or one-wire serial bus architectures. SPI-compliant ICs or other devices communicate in a full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing whereby multiple slave ICs or other devices are supported through a selection with individual so-called slave select lines.

In distributed on-chip digital interfaces, such as I2C or SPI, the distribution of numerous digital control lines poses certain challenges such as routing, silicon footprint (i.e., potentially wasting expensive silicon area of an IC), and signal interference among devices (e.g., analog signal interference in analog signaling applications). As such, the design of densely packed, digitally-assisted application specific integrated circuits (ASICs) are known to exacerbate the aforementioned challenges.

Therefore, a need exists for an improved technique that addresses these types of IC design challenges with respect to such distributed on-chip digital interfaces.

BRIEF SUMMARY OF EMBODIMENTS

In accordance with various embodiments, an enhanced method and architecture is provided for operating with distributed on-chip digital interfaces such as I2C or SPI. This method and architecture, illustratively, divides the available address space of the digital interface register arrays into one or more segments (each such segment also referred to herein as a so-called “fundamental digital interface circuit”). Such segmentation allows for, in accordance with an embodiment, each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection and a common communication bus. For example, mixed-signal circuits (e.g., data converters, radio frequency integrated circuit (RFIC) radios, and phase-locked loops, to name just a few) which require digital calibration circuity may use a large number of digital lines (e.g., 100 or more) which can be placed in close proximity of the desired blocks without global IC routing.

In accordance with an embodiment, an integrated circuit is configured with a plurality of fundamental digital interface circuits wherein each such fundamental digital interface circuit has a set of inputs (e.g., a set of N inputs) and a set of outputs (e.g., a set of M outputs) where N and M are integers and M is greater than or equal to N, and a plurality of signal paths are routed from a particular externally accessible location on the integrated circuit to the corresponding input (or inputs) of a particular one (or ones) fundamental digital interface circuits of the plurality of fundamental digital interface circuits.

As such, the address space of the digital interface register arrays of the integrated circuits are divided into segments (i.e., the plurality of fundamental digital interface circuits). In accordance with the embodiment, each fundamental digital interface circuit has at least one input port associated with a unique address where such unique address corresponds to and defines a unique memory address associated with a particular one fundamental digital interface circuit. Each fundamental digital interface circuit, in accordance with an embodiment, is further configured with a local memory for storing certain data that is useful to facilitate adjusting one or more parameters of the fundamental digital interface circuit.

These configurations, in accordance with the various embodiments herein, facilitate a physical layout wherein each digital segment (i.e., each fundamental digital interface circuit) can be located proximally to the one or more digitally controlled circuits also resident on the integrated circuit (e.g., a plurality of analog circuits) while maintaining the external interface of the integrated circuit and internally daisy-chaining each fundamental digital interface circuit.

These and other advantages will be apparent to those of ordinary skill in the art by reference to the following detailed description and the accompanying drawings.

DETAILED DESCRIPTION

In accordance with various embodiments, an enhanced method and architecture is provided for operating with distributed on-chip digital interfaces such as I2C or SPI. This method and architecture, illustratively, divides the available address space of the digital interface register arrays into one or more segments (i.e., each fundamental digital interface circuit representing a segment). Such segmentation allows for, in accordance with an embodiment, each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection across a common communications bus.

FIG. 1shows a prior art distributed architecture for an integrated circuit configuration having a digital interface circuit. As will be appreciated, distributed architecture100may by utilized with either of the I2C or SPI protocols. The distributed architecture100is illustratively shown for integrated circuit105having digital interface circuit110having multiple inputs, namely, input130-1through130-N (forming “B” inputs, as shown) and multiple outputs, namely, output140-1,140-2,140-3,140-4through140-N (forming “A” outputs, as shown). Such outputs being internally connected to several analog circuits, namely, analog circuit120-1, analog circuit120-2, and analog circuit120-3, respectively. As will be appreciated, distributed architecture100may suffer from routing issues and/or signal interference with analog circuits120-1,120-2, or120-3. For example, global integrated circuit routing consumes valuable IC footprint in terms of layout which can be used for other purposes, and long digital interconnects on mixed signal integrated circuits are known to inject unwanted noise into sensitive analog and RF circuits. Also, high-speed RFIC circuits typically have stringent spacing and routing requirements which may prevent additional long digital routing throughout the IC footprint. As such, short distance connection of digital is typically preferred.

FIG. 2shows an illustrative distributed architecture for an integrated circuit configuration having a segmented digital interface block in accordance with an embodiment. In particular, distributed architecture200can be utilized with either of the I2C or SPI protocols (or other protocols and systems operating in substantially the same way). The distributed architecture200is illustratively shown for integrated circuit205having a plurality of fundamental digital interface circuits, namely, fundamental digital interface circuit210-1, fundamental digital interface circuit210-2, and fundamental digital interface circuit210-3, having multiple inputs, namely, input230-1through230-N. As shown inFIG. 2, input230-1through230-N forming a set of “N” input lines, where N is an integer value, communicated over and forming bus215. As will be appreciated, such input lines can be command/address lines, assert lines, clock lines, data response lines, and flag lines, to name just a few. Each respective fundamental digital interface circuit has a set of respective outputs. Illustratively, fundamental digital interface circuit210-1has a plurality of outputs, namely, output240-1,240-2,230-3through240-N, fundamental digital interface circuit210-2has a plurality of outputs, namely, output250-1,250-2,250-3through250-N multiple outputs, and fundamental digital interface circuit210-3has a plurality of outputs, namely, output260-1,260-2,260-3through260-N.

As shown inFIG. 2, each of these plurality of outputs from the respective fundamental digital interface circuit (i.e., fundamental digital interface circuit210-1, fundamental digital interface circuit210-2, and fundamental digital interface circuit210-3) form a set of “M” output lines where M is an integer value. Thus, integrated circuit205is configured with a plurality of fundamental digital interface circuits wherein each such fundamental digital interface circuit has a set of inputs (e.g., a set of N inputs such as input230-1through input230-N) and a set of outputs (e.g., a set of M outputs such as output240-1through240-N) where N and M are integers and M is greater than or equal to N, and a plurality of signal paths (i.e., input230-1through input230-N) are routed from a particular externally accessible location on the integrated circuit to the corresponding input (or inputs) of a particular one (or ones) fundamental digital interface circuit of the plurality of fundamental digital interface circuits. For example, inputs280-1through280-N of fundamental digital interface circuit210-1, inputs285-1through285-N of fundamental digital interface circuit210-2, and inputs290-1through290-N of fundamental digital interface circuit210-3. In accordance with the embodiment, it will be noted, that the selection of the integers M and N, respectively, must be such that the M number of outputs is greater than or equal to the N number of inputs.

Importantly, in accordance with the embodiment, distributed architecture200is, illustratively, divided such that the available address space is divided into the individual segments represented by fundamental digital interface circuit210-1, fundamental digital interface circuit210-2, and fundamental digital interface circuit210-3. Further, each of the fundamental digital interface circuits has an individual input port associated therewith, namely input port270-1associated with fundamental digital interface circuit210-1, input port270-2associated with fundamental digital interface circuit210-2, and input port270-3associated with fundamental digital interface circuit210-3whereby a unique value is applied to define a unique memory address space associated with the respective fundamental digital interface circuit. As such, in accordance with the embodiment, the localized digital blocks are in close proximity of the final block with which they must interface, and this interface to all the digital blocks employs a standard SPI or I2C interface. Such segmentation allows for, in accordance with the embodiment, each fundamental digital interface circuit to be placed proximal to and in close proximity of the digitally controlled circuit(s), that is, analog circuits220-1through220-3which are individual functional blocks of integrated circuit205, which share an operational connection. Also, in accordance with the embodiment, the configuration allows for such fundamental digital interface circuits and analog circuits to be internally daisy-chained. It will be appreciated that whileFIG. 2illustratively shows distributed architecture200with three fundamental digital interface circuits and three analog circuits, any number of such circuits can be configured in accordance with the distributed architecture and bus protocol as described herein for operating with distributed (or segmented) on-chip digital interfaces such as I2C or SPI.

FIG. 3shows an illustrative distributed architecture for an integrated circuit configuration having a segmented digital interface block in accordance with a further embodiment. In particular, distributed architecture300can again be utilized with either of the I2C or SPI protocols (or other protocols or systems operating in substantially the same way). The distributed architecture300is illustratively shown for integrated circuit305having a plurality of fundamental digital interface circuits, namely, fundamental digital interface circuit310-1, fundamental digital interface circuit310-2, and fundamental digital interface circuit310-3having multiple inputs, namely, input330-1through330-N. As shown inFIG. 3, input330-1through330-N forming a set of “N” input lines, where N is an integer value, communicated over and forming bus315. As will be appreciated, such input lines can be command/address lines, assert lines, clock lines, data response lines, and flag lines, to name just a few. Each respective fundamental digital interface circuit has a set of respective outputs. Illustratively, fundamental digital interface circuit310-1has a plurality of outputs, namely, output340-1,340-2,340-3through340-N, fundamental digital interface circuit310-2has a plurality of outputs, namely, output350-1,350-2,350-3through350-N, and fundamental digital interface circuit310-3has a plurality of outputs, namely, output360-1,360-2,360-3through360-N. In accordance with this further embodiment, each such fundamental digital interface circuit is further configured with a local memory, namely, memory395-1, memory395-2, and memory395-3which may be any type of well-known memory such as a random access memory. This localized memory allows for the storage of certain data useful in adjusting in operating the parameters of their respective fundamental digital interface circuit. For example, this localized memory can hold calibration data for analog circuits which may be unique to each integrated circuit and thus must be updated during normal integrated circuit operation. Localized memory can also hold dynamic configuration data which may be adjusted and may differ depending upon the operational mode of the integrated circuit.

As shown inFIG. 3, each of these plurality of outputs from the respective fundamental digital interface circuit (i.e., fundamental digital interface circuit310-1, fundamental digital interface circuit310-2, and fundamental digital interface circuit310-3) again form a set of “M” lines where M is an integer value. Thus, integrated circuit305is configured with a plurality of fundamental digital interface circuits wherein each such fundamental digital interface circuit has a set of inputs (e.g., a set of N inputs such as input330-1through input330-N) and a set of outputs (e.g., a set of M outputs such as output350-1through350-N) where N and M are again integers and M is greater than or equal to N, and a plurality of signal paths (i.e., input330-1through input330-N) are routed from a particular externally accessible location on the integrated circuit to the corresponding input (or inputs) of a particular one (or ones) fundamental digital interface circuit of the plurality of fundamental digital interface circuits. For example, inputs380-1through380-N of fundamental digital interface circuit310-1, inputs385-1through385-N of fundamental digital interface circuit310-2, and inputs390-1through390-N of fundamental digital interface circuit310-3. In accordance with the embodiment, it will be noted, that the selection of the integers M and N, respectively, must be such that the M number of outputs is greater than or equal to the N number of inputs.

Importantly, in accordance with this further embodiment, distributed architecture300is, illustratively, divided such that the available address space is divided into the individual segments represented by fundamental digital interface circuit310-1, fundamental digital interface circuit310-2, and fundamental digital interface circuit310-3. Further, each of the fundamental digital interface circuits has an input port associated therewith, namely input port370-1associated with fundamental digital interface circuit310-1, input port370-2associated with fundamental digital interface circuit310-2, and input port370-3associated with fundamental digital interface circuit310-3whereby a unique value is applied to define a unique memory address space associated with the respective fundamental digital interface circuit. Such segmentation allows for, in accordance with the embodiment, each fundamental digital interface circuit to be placed proximal to and in close proximity of the digitally controlled circuit(s), that is, analog circuits320-1,320-2, and320-3which are individual functional blocks of integrated circuit305, which share an operational connection. Also, in accordance with the embodiment, the configuration allows for such fundamental digital interface circuits and analog circuits to be internally daisy-chained. It will be appreciated that whileFIG. 3illustratively shows distributed architecture300with three fundamental digital interface circuits and three analog circuits, any number of such circuits can be configured in accordance with the distributed architecture and bus protocol as described herein for operating with distributed (or segmented) on-chip digital interfaces such as I2C or SPI.

FIG. 4shows a flowchart of illustrative operations400for providing distributed on-chip communications employing a digital interface circuit in accordance with an embodiment. In accordance with this embodiment, the segmenting of an address space of a digital interface register array is undertaken using a plurality of fundamental digital interface circuits (step410), as detailed herein above. Each fundamental digital interface circuit is assigned a unique memory address, in step420, utilizing the respective input port associated with that fundamental digital interface circuit. In accordance with the embodiment, the routing of a plurality of inputs to a device (e.g., an IC) between a plurality of functional blocks of such device, at step430, is done using the plurality of fundamental digital interface circuits. Further, if any adjusting (step440) of one or more of the fundamental digital interface circuits is necessary this is done utilizing, illustratively, local stored data as detailed herein above. Advantageously, the segmentation allows for, in accordance with the embodiment, each fundamental digital interface circuit to be placed proximal to and in close proximity of the digitally controlled circuit(s), for example, analog circuits which are individual functional blocks of an integrated circuit, which share an operational connection and common communications bus, for example the analog circuits shown in eitherFIG. 2orFIG. 3.

As detailed above, the various embodiments herein can be embodied in the form of methods and apparatuses for practicing those methods. The disclosed methods may be performed by a combination of hardware, software, firmware, middleware, and computer-readable medium (collectively “computer”) installed in and/or communicatively connected to a user device or network node, for example.FIG. 5is a high-level block diagram of an exemplary computer500that may be used for implementing a method for providing distributed on-chip communications employing a digital interface circuit in accordance with the various embodiments herein. Computer500comprises a processor510operatively coupled to a data storage device520and a memory530. Processor510controls the overall operation of computer500by executing computer program instructions that define such operations. Communications bus560facilitates the coupling and communication between the various components of computer500. The computer program instructions may be stored in data storage device520, or a non-transitory computer readable medium, and loaded into memory530when execution of the computer program instructions is desired. Thus, the steps of the disclosed method (see, e.g.,FIG. 4and the associated discussion herein above) can be defined by the computer program instructions stored in memory530and/or data storage device520and controlled by processor510executing the computer program instructions. For example, the computer program instructions can be implemented as computer executable code programmed by one skilled in the art to perform the illustrative operations defined by the disclosed method. Accordingly, by executing the computer program instructions, processor510executes an algorithm defined by the disclosed method. Computer500also includes one or more communication interfaces550for communicating with other devices via a network (e.g., a wireless communications network) or communications protocol (e.g., Bluetooth®). For example, such communication interfaces may be a receiver, transceiver or modem for exchanging wired or wireless communications in any number of well-known fashions. Computer500also includes one or more input/output devices540that enable user interaction with computer500(e.g., camera, display, keyboard, mouse, speakers, microphone, buttons, etc.).

Processor510may include both general and special purpose microprocessors, and may be the sole processor or one of multiple processors of computer500. Processor510may comprise one or more central processing units (CPUs), for example. Processor510, data storage device520, and/or memory530may include, be supplemented by, or incorporated in, one or more application-specific integrated circuits (ASICs) and/or one or more field programmable gate arrays (FPGAs).

Input/output devices540may include peripherals, such as a camera, printer, scanner, display screen, etc. For example, input/output devices540may include a display device such as a cathode ray tube (CRT), plasma or liquid crystal display (LCD) monitor for displaying information to the user, a keyboard, and a pointing device such as a mouse or a trackball by which the user can provide input to computer500.

It should be noted that for clarity of explanation, the illustrative embodiments described herein may be presented as comprising individual functional blocks or combinations of functional blocks. The functions these blocks represent may be provided through the use of either dedicated or shared hardware, including, but not limited to, hardware capable of executing software. Illustrative embodiments may comprise digital signal processor (“DSP”) hardware and/or software performing the operation described herein. Thus, for example, it will be appreciated by those skilled in the art that the block diagrams herein represent conceptual views of illustrative functions, operations and/or circuitry of the principles described in the various embodiments herein. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo code, program code and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer, machine or processor, whether or not such computer, machine or processor is explicitly shown. One skilled in the art will recognize that an implementation of an actual computer or computer system may have other structures and may contain other components as well, and that a high level representation of some of the components of such a computer is for illustrative purposes.