Integrated circuit packaging system with increased connectivity and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.

TECHNICAL FIELD

The present invention relates generally to an integrated circuit packaging system, and more particularly to a system for packaging multiple integrated circuits in a leaded package.

BACKGROUND ART

Many of today's highly integrated products have become exceedingly popular. These products include cell phones that include a camera, or a global positioning system that includes an audio player for personal music downloads. In order to integrate these diverse functions quickly, the electronics industry has pushed the boundaries of package technology in many directions.

Integrated circuit dice are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (PCB). The elements of such a package include a conductive lead frame, an integrated circuit die, bonding material to attach the integrated circuit die to the lead frame, bond wires which electrically connect pads on the integrated circuit die to individual leads of the lead frame, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package.

The lead frame is the central supporting structure of such a package. A portion of the lead frame is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the lead frame extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the lead frame also remains exposed within the exterior of the package for use as a heat sink.

One type of semiconductor package commonly known in the electronics field is referred to as a quad flat pack (QFP) package. A typical QFP package comprises a thin, generally square package body defining four peripheral sides of substantially equal length. Protruding from each of the four peripheral sides of the package body are a number of leads which each have a generally gull-wing configuration. Portions of the leads are internal to the package body, and are electrically connected to respective ones of the pads or terminals of a semiconductor die also encapsulated within the package body. The semiconductor die is itself mounted to a die pad of the QFP package lead frame.

There is a current need in the electronics industry for a QFP package which includes additional input/output capabilities than can be provided by the leads protruding from the sides of the package body. Thus, a need still remains for an integrated circuit packaging system with increased connectivity that can provide additional connection options for highly integrated electronic packages while maintaining a thin profile. In view of the rapid development of products that require high levels of integration, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides a method of manufacture of an integrated circuit packaging system including: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body, on the lead frame, the base integrated circuit, and the chip interconnects, includes having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.

The present invention provides an integrated circuit packaging system includes a package body having contact pads and connection leads exposed; a base integrated circuit coupled to the contact pads; chip interconnects between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; and a bottom surface on the package body with the connection leads formed coplanar to the bottom surface.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Where multiple embodiments are disclosed and described, having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit die, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes stamping, forging, patterning, exposure, development, etching, cleaning, and/or removal of the material or laser trimming as required in forming a described structure.

Referring now toFIG. 1, therein is shown a cross-sectional view of an integrated circuit packaging system100with increased connectivity, as viewed along the section line1-1ofFIG. 3, in an embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system100depicts a base integrated circuit102coupled to contact pads104by chip interconnects106, such as bond wires, solder balls, solder bumps, solder columns, or stud bumps. The contact pads104may extend from a tie bar108that may elevate to a level near that of the inactive side of the base integrated circuit102, such as a flip chip integrated circuit.

A wire bond integrated circuit110may be attached to the inactive side of the base integrated circuit102by an adhesive112, such as a die attach material. Electrical interconnects114, such as bond wires, may couple the wire bond integrated circuit110to a bond finger116, the tie bar108, or a combination thereof.

A package body118may be formed on the base integrated circuit102, the chip interconnects106, the wire bond integrated circuit110, the electrical interconnects114, the tie bars108, the bond fingers116, and the contact pads104. The package body118may be formed by injecting an epoxy molding compound that leaves a portion of the contact pads104exposed on the bottom surface.

Connection leads120may extend from the bond finger116, beyond the package body118, and are bent to be coplanar with a bottom surface122of the package body. The connection leads120may be formed so that they are coplanar with the exposed portion of the contact pads104and the bottom surface122of the package body118.

It has been discovered that the integrated circuit packaging system100may provide a significantly increased input/output capacity, multiple chip integration, and ease of assembly, without increasing the thickness of the package. This aspect can assist in the integration of dissimilar technologies such as memory and sequential logic integrated circuits.

Referring now toFIG. 2, therein is shown a top plan view of a lead frame assembly200segment for implementing the integrated circuit packaging system of the present invention. The top plan view of the lead frame assembly200depicts a lead frame202, having a dam bar204that joins the connection leads120, the bond fingers116, and the tie bars108prior to molding the package body118, ofFIG. 1.

The base integrated circuit102may be positioned over the contact pads104and coupled by the chip interconnects106. The wire bond integrated circuit110is attached to the base integrated circuit102by the adhesive112. While the wire bond integrated circuit110is shown to be smaller than the base integrated circuit102, this is an example only and the actual size of the wire bond integrated circuit110may differ.

The electrical interconnects114are shown coupled between a bonding pad206and the bond finger116or the tie bar108. This is also by way of an example and the bonding pad206may be coupled to the bond finger116, the tie bar108, or the combination thereof. By coupling the bonding pad206to the tie bar108, a signal may be shared between the base integrated circuit102and the wire bond integrated circuit110without the addition of interconnects outside the package body118.

The dam bar204may provide a sealing surface during the formation of the package body118, ofFIG. 1. The dam bar204may be removed, in a subsequent manufacturing step, once the package body118is formed to hold the tie bars108and the bond fingers116in place.

Referring now toFIG. 3, therein is shown a bottom view of the integrated circuit packaging system100ofFIG. 1. The bottom view of the integrated circuit packaging system100depicts the contact pads104positioned around a package bottom302of the package body118. The number and position of the contact pads104is an example only and the actual number and position may differ. While the package body118is shown having sloped edges on the package bottom302, this is an example only.

The connection leads120may be distributed along a package side304. The number of the connection leads120on the package side304may be equal for each of the sides. This configuration matches the definition of an industry standard quad flat pack (QFP) package. The number and position of the connection leads120formed on the package side304is an example only and the actual position and number may differ as long as all of the package sides304are the same. The section line1-1shows the position and viewing direction of the cross-sectional view ofFIG. 1.

Prior to forming the shape of the connection leads120, they extend straight out of the package side304. In the first embodiment of the present invention, the connection leads120are bent so to provide a coplanar connection surface between the contact pads104and the connection leads120, but other configurations are possible.

Referring now toFIG. 4, therein is shown a cross-sectional view, substantially similar toFIG. 1, of a package stack400application using an alternative embodiment402of the integrated circuit packaging system100, ofFIG. 1. The cross-sectional view of the package stack400depicts the alternative embodiment402, having the connection leads120bent away from the plane of the contact pads104. The connection leads120may be coplanar with a bottom surface406of the package body118.

An external integrated circuit package404may be coupled to the contact pads104by the chip interconnects106. The external integrated circuit package404may be a ball grid array, a wafer level chip scale package, a quad flat pack, a quad flat pack—no lead (QFN), or other leaded chip carrier. This configuration provides electrical connections between the connection leads120, the base integrated circuit102, the wire bond integrated circuit110, the external integrated circuit package404, or a combination thereof.

Referring now toFIG. 5, therein is shown a bottom view of an integrated circuit packaging system500, in a second alternative embodiment of the present invention including a section line6-6. The bottom view of the integrated circuit packaging system500depicts the package body118having the connection leads120extending from the package side304.

Contact pads502may be formed on a package bottom504in a double row configuration. A saw line506may be etched, by a singulating saw or laser, in order to isolate the contact pads502from a lead frame (not shown). A heat spreader508may optionally be embedded in the package bottom504. The section line6-6indicates the position and direction of view of the cross-section ofFIG. 6.

Referring now toFIG. 6, therein is shown a cross-sectional view of the integrated circuit packaging system500, along a section line6-6, ofFIG. 5. The cross-sectional view of the integrated circuit packaging system500depicts a base integrated circuit602, such as a flip chip integrated circuit, having inner pads604and outer pads606. The chip interconnects106may couple the inner pads604to inner contact pads608and the outer pads606to outer contact pads610. The saw line506may remove the connection between the inner contact pads608and the outer contact pads610after the package body118is molded in place.

A wire bond integrated circuit612may be mounted on the inactive surface of the base integrated circuit602by the adhesive112. The electrical interconnects114may couple the wire bond integrated circuit612to the inner contact pads608, the outer contact pads610, the bond fingers116, or a combination thereof. The heat spreader508may optionally be attached to the active side of the base integrated circuit602by a thermal adhesive614.

Referring now toFIG. 7, therein is shown a top plan view of a lead frame assembly700segment for implementing the integrated circuit packaging system500ofFIG. 5. The top plan view of the lead frame assembly700depicts a dam bar702establishing the spatial position of the bond fingers116and the connection leads120. A tie bar704may establish the spatial position of the inner contact pads608and the outer contact pads610. The base integrated circuit602may be coupled to the inner contact pads608and the outer contact pads610by the chip interconnects106.

The electrical interconnects114may be electrically connected to the inner contact pads608, the outer contact pads610, the bond finger116, the wire bond integrated circuit612, or a combination thereof. The position and size of the wire bond integrated circuit612is an example only and the actual size and position may differ. The number and position of bonding pads706on the wire bond integrated circuit612is also an example and may differ.

Referring now toFIG. 8, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system800, in a third alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system800is viewed along a section line substantially similar to the section line6-6. A base integrated circuit802, such as a flip chip integrated circuit, may be electrically connected to an inner lead group804and an outer lead group806. The inner lead group804is limited to coupling the base integrated circuit802to the next level system (not shown) only. The outer lead group806in contrast may be coupled to a wire bond integrated circuit808, the bond finger116, or a combination thereof.

The connection leads120may be formed in order to provide a coplanar connection surface with the inner lead group804and the outer lead group806. The package body118may be molded on the bond finger116, the inner lead group804and the outer lead group806while leaving the bottom surface of the inner lead group804and the outer lead group806exposed for electrical connection.

The saw line506may be etched, by the singulating saw or the laser, in order to isolate the contact pads502that form the inner lead group804and the outer lead group806. The base integrated circuit802may have any number of the contact pads coupled and may be configured with a different number than shown.

Referring now toFIG. 9, therein is shown a top plan view of a lead frame assembly900segment for implementing the integrated circuit packaging system ofFIG. 8. The top plan view of the lead frame assembly900depicts the inner lead group804and the outer lead group806connected to the tie bar704. The base integrated circuit802may be electrically connected to the contact pads502by the chip interconnects106.

The electrical interconnects114may be coupled between the outer lead group806, the wire bond integrated circuit808, the bond finger116, or a combination thereof. The number and position of the contact pads502in the inner lead group804and the outer lead group806is an example only and the number and position may differ. The size and position of the wire bond integrated circuit808is an example and may also differ.

Referring now toFIG. 10, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system1000, in a fourth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1000depicts a base integrated circuit1002, such as the wire bond integrated circuit, having a wafer backside coating1004mounted on the contact pads104. The wafer backside coating1004, such as an adhesive layer, may be applied to a wafer back side prior to singulating the base integrated circuit1002. The base integrated circuit1002is coupled to the contact pads104by the electrical interconnects114coupled to the tie bar108. The contact pads104may extend from the tie bar108that may elevate to a level near that of the top side of the base integrated circuit1002.

The wire bond integrated circuit110may be attached to the top side of the base integrated circuit1002by the adhesive112, such as a die attach material. The electrical interconnects114, such as bond wires, may couple the wire bond integrated circuit110to a bond finger116, the tie bar108, or a combination thereof.

The package body118may be formed on the base integrated circuit1002, the wire bond integrated circuit110, the electrical interconnects114, the tie bars108, the bond fingers116, and the contact pads104.

The connection leads120may extend from the bond finger116, beyond the package body118, and are bent in a pattern suitable for attaching the integrated circuit packaging system1000to a next level system (not shown). The connection leads120are formed so that they are coplanar with the exposed portion of the contact pads104and a bottom surface1006of the package body118.

Referring now toFIG. 11, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system1100, in a fifth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1100depicts the base integrated circuit1002, such as the wire bond integrated circuit having the wafer backside coating1004mounted on the contact pads104. The wafer backside coating1004, such as an adhesive layer, may be applied to the wafer back side prior to singulating the base integrated circuit1002. The base integrated circuit1002is coupled to the contact pads104by the electrical interconnects114coupled to the tie bar108. The contact pads104may extend from the tie bar108that may elevate to a level near that of the top side of the base integrated circuit1002.

A stacked heat sink1102may be attached to the top side of the base integrated circuit1002by an adhesive1104, such as a non-conductive epoxy. The electrical interconnects114, such as bond wires, may optionally couple the stacked heat sink1102to a bond finger116, the tie bar108, or a combination thereof for applying a ground potential. The heat spreader508may optionally be embedded below the wafer backside coating1004.

The package body118may be formed on the base integrated circuit1002, the stacked heat sink1102, the electrical interconnects114, the tie bars108, the bond fingers116, and the contact pads104.

The connection leads120may extend from the bond finger116, beyond the package body118, and are bent in a pattern suitable for attaching the integrated circuit packaging system1000to a next level system (not shown). The connection leads120are formed so that they are coplanar with the exposed portion of the contact pads104and the bottom of the package body118.

Referring now toFIG. 12, therein is shown a cross-sectional view, substantially similar toFIG. 6, of a package stack1200application using an alternative embodiment of the integrated circuit packaging system1000, ofFIG. 10. The cross-sectional view of the package stack1200depicts the alternative embodiment1202, having the connection leads120bent away from the plane of the contact pads104.

The external integrated circuit package410may be coupled to the contact pads104by the chip interconnects106. The external integrated circuit package410may be a ball grid array, a wafer level chip scale package, a quad flat pack, a quad flat pack—no lead (QFN), or other leaded chip carrier. This configuration provides electrical connections between the connection leads120, the base integrated circuit102, the wire bond integrated circuit110, the external integrated circuit package410, or a combination thereof.

Referring now toFIG. 13, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system1300, in a sixth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1300is viewed along a section line substantially similar to the section line6-6. A base integrated circuit1302may be electrically connected to the inner lead group804and the outer lead group806. The inner lead group804is limited to coupling the base integrated circuit1302to the next level system (not shown) only. The outer lead group806in contrast may be coupled to a wire bond integrated circuit808, the bond finger116, or a combination thereof.

The connection leads120may be formed in order to provide a coplanar connection surface with the inner lead group804and the outer lead group806. The package body118may be molded on the bond finger116, the inner lead group804and the outer lead group806while leaving the bottom surface of the inner lead group804and the outer lead group806exposed for electrical connection.

The saw line506may be etched, by the singulating saw or the laser, in order to isolate the contact pads502that form the inner lead group804and the outer lead group806. The base integrated circuit1302may have any number of the contact pads coupled and may be configured with a different number than shown.

Referring now toFIG. 14, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system1400, in a seventh alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1400depicts the base integrated circuit1002having the wafer backside coating1004positioned on the inner contact pads608. The chip interconnects106may couple the inner pads604to inner contact pads608and the outer pads606to outer contact pads610. The saw line506may remove the connection between the inner contact pads608and the outer contact pads610after the package body118is molded in place.

A wire bond integrated circuit612may be mounted on the base integrated circuit1002by the adhesive112. The electrical interconnects114may couple the wire bond integrated circuit612to the inner contact pads608, the outer contact pads610, the bond fingers116, or a combination thereof.

Referring now toFIG. 15, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system1500, in an eighth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1500depicts the base integrated circuit1002, such as the wire bond integrated circuit, having the wafer backside coating1004mounted on the contact pads104. The wafer backside coating1004, such as an adhesive layer, may be applied to the wafer back side prior to singulating the base integrated circuit1002. The base integrated circuit1002is coupled to the contact pads104by the chip interconnects106coupled to the tie bar108. The contact pads104may extend from the tie bar108that may elevate to a level near that of the top side of the base integrated circuit1002.

The package body118may be formed on the base integrated circuit1002, the chip interconnects106, the tie bars108, the bond fingers116, and the contact pads104. The connection leads120may extend from the bond finger116, beyond the package body118, and are bent in a pattern suitable for attaching the integrated circuit packaging system1500to a next level system (not shown). The connection leads120are formed so that they are coplanar with the exposed portion of the contact pads104and the bottom surface1006of the package body118. A heat spreader1502may optionally be attached in the package bottom.

Referring now toFIG. 16, therein is shown a cross-sectional view, substantially similar toFIG. 6, of an integrated circuit packaging system1600, in a ninth alternative embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system1600depicts the base integrated circuit1602having the wafer backside coating1004positioned on the inner contact pads608.

The chip interconnects106may couple inner bond pads1604to the bond finger116and outer bond pads1606to the inner contact pads608or the outer contact pads610. The saw line506may remove the connection between the inner contact pads608and the outer contact pads610after the package body118is molded in place. The chip interconnects106may couple the base integrated circuit1602to the inner contact pads608, the outer contact pads610, the bond fingers116, or a combination thereof.

Referring now toFIG. 17, therein is shown a flow chart of a method of manufacture of an integrated circuit packaging system100in an embodiment of the present invention. The method1700includes forming a lead frame having contact pads and connection leads in a block1702; coupling a base integrated circuit to the contact pads in a block1704: coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof in a block1706; molding a package body, on the lead frame, the base integrated circuit, and the chip interconnects, includes having the contact pads exposed in a block1708; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface in a block1710.

An aspect that has been unexpectedly discovered is that the present invention may simplify the design of the next level system, such as a printed circuit board, by reducing the number of electrical connections required outside the integrated circuit packaging system.

Another aspect is the overall package thickness may be reduced because no internal substrate is required while mounting the wire bond integrated circuit.

Thus, it has been discovered that the integrated circuit packaging system with increased connectivity of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for higher levels of integration in integrated circuit packages with leaded configurations. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit devices fully compatible with conventional manufacturing processes and technologies.