Highly reliable low cost structure for wafer-level ball grid array packaging

Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip, an insulating layer on the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit packaging technology, and more particularly to wafer-level ball grid array packages.

2. Background Art

Integrated circuit (IC) chips or dies are typically interfaced with other circuits using a package that can be attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder ball pads located on a bottom external surface of a package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the PCB.

An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have several names in industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solder balls are mounted directly to the IC chip when the IC chip has not yet been singulated from its fabrication wafer. Wafer-level BGA packages can therefore be made very small, with high pin out, relative to other IC package types including traditional BGA packages.

A current move to tighter fabrication tolerances, such as 65 nm, with a continuing need to meet strict customer reliability requirements and ongoing cost pressures, is causing difficulties in implementing wafer-level BGA package technology. During operating conditions or reliability assessment testing, external stresses are applied to the wafer-level BGA package. These stresses are transferred to the package through a solder interconnect. For wafer-level packaging, two polymer layers in the package are typically required to act as a stress buffer between the solder interconnect and the die. However, having two polymer layers present in a BGA package is expensive.

Thus, what is needed are improved wafer-level packaging fabrication techniques that can meet desired reliability requirements and ongoing cost pressures, while enabling even tighter fabrication tolerances and smaller packages sizes.

BRIEF SUMMARY OF THE INVENTION

Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. A routing interconnect is used to couple a chip terminal to a bump interconnect (or other package interconnect type). In one aspect, the routing interconnect directly connects (e.g., using solder) the chip terminal to the bump interconnect. In another aspect, another metal layer is added to the routing interconnect to mount the bump interconnect, to connect the chip terminal to the bump interconnect.

In another aspect, a single insulating layer is used to provide stress absorption for stresses applied to the bump interconnect, while enabling fewer manufacturing process steps than required in multiple polymer layer configurations.

In an example aspect of the present invention, an IC package includes an IC chip, an insulating layer on the surface of the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals through a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.

In another aspect of the present invention, a plurality of IC packages is formed. A wafer is received having a plurality of integrated circuit regions, each integrated circuit region having a plurality of terminals configured in an array on a surface of the wafer. An insulating layer is formed on the wafer. A plurality of vias is formed through the insulating layer to provide access to the plurality of terminals of each integrated circuit region. A plurality of routing interconnects is formed on the insulating layer such that each routing interconnect of the plurality of routing interconnects has a first portion in contact with a respective terminal through a respective via through the insulating layer and has a second portion that extends over the insulating layer. A plurality of bump interconnects are formed on the plurality of routing interconnects such that each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.

In still another aspect of the present invention, a wafer level integrated circuit package structure includes a wafer, an insulating layer on the surface of the wafer, a plurality of vias through the insulating layer, a plurality of routing interconnects on the insulating layer, and a plurality of bump interconnects on the plurality of routing interconnects. The wafer has a plurality of integrated circuits regions. Each integrated circuit region has a plurality of accessible terminals configured in an array on a surface of the wafer. The plurality of vias provides access to the plurality of terminals of each integrated circuit region. Each routing interconnect of the plurality of routing interconnects has a first portion in contact with a respective terminal through a respective via and a second portion that extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.

These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s).

DETAILED DESCRIPTION OF THE INVENTION

Introduction

Conventional Wafer-Level Processing

“Wafer-level packaging” is an integrated circuit packaging technology where all packaging-related interconnects are applied while the integrated circuit dies or chips are still in wafer form. After the packaging-related interconnects are applied, the wafer is then tested and singulated into individual devices and sent directly to customers for their use. Thus, individual packaging of discreet devices is not required. The size of the final package is essentially the size of the corresponding chip, resulting in a very small package solution. Wafer-level packaging is becoming increasingly popular as the demand for increased functionality in small form-factor devices increases. These applications include mobile devices such as cell phones, PDAs, and MP3 players, for example.

FIG. 1shows a flowchart100providing example steps for performing wafer-level package processing. Flowchart100begins with step102. In step102, a plurality of integrated circuits is fabricated on a surface of a wafer to define a plurality of integrated circuit regions. For example,FIG. 2shows a plan view of a wafer200. Wafer200may be silicon, gallium arsenide, or other wafer type. As shown inFIG. 2, wafer200has a surface202defined by a plurality of integrated circuit regions (shown as small rectangles inFIG. 2). Each integrated circuit region is configured to be packaged separately into a separate wafer-level ball grid array package according to the process of flowchart100.

In step104, front-end processing of the wafer is performed to attach an array of interconnect balls to the surface of the wafer for each of the plurality of integrated circuits regions. A critical part of wafer-level packaging is the front-end process of step104. In this step, appropriate interconnects and packaging materials are applied to the wafer. For example,FIG. 3shows a cross-sectional view of wafer200, highlighting an integrated circuit region300. As shown inFIG. 3, integrated circuit region300has a plurality of interconnect balls302a-302eattached thereto on surface202. Interconnect balls302a-302emay be solder, other metal, combination of metals/alloy, etc. Interconnect balls302are used to interface the BGA package resulting from integrated circuit region300with an external device, such as a PCB.

In step106, each of the plurality of integrated circuits regions is tested on the wafer. For example, each integrated circuit region can be interfaced with probes at interconnect balls302to provide ground, power, and test input signals, and to receive test output signals.

In step108, back-end processing of the wafer is performed to separate the wafer into a plurality of separate integrated circuit packages. Example back-end processing is described below.

In step110, the separate integrated circuit packages are shipped. For example, the separate integrated circuit packages may be shipped to a warehouse, to customers, to a site for assembly into devices, to a site for further processing, etc.

FIG. 4shows a flowchart400providing example steps for performing back-end processing of a wafer, according to step108of flowchart100. Not all steps of flowchart400are necessarily performed in all back-end processing applications. The steps of flowchart400need not necessarily be performed in the order shown. Flowchart400begins with step402. In step402, a backgrinding process is performed on the wafer. For example, the backgrinding process may be performed on wafer200to reduce a thickness of wafer200to a desired amount.

In step404, each of the plurality of integrated circuits regions is marked on the wafer. For example, each integrated circuit region may be marked with information that may be used to identify the particular type of ball grid array package, such as manufacturer identifying information, part number information, etc. For instance, integrated circuit region300may be marked on the side of wafer200that is opposite surface202shown inFIG. 3.

In step406, the wafer is singulated to separate the wafer into the plurality of separate integrated circuit packages. Wafer200may be singulated/diced in any appropriate manner to physically separate the integrated circuit regions from each other, as would be known to persons skilled in the relevant art(s).

In step408, the plurality of separate integrated circuit packages are packaged for shipping. For example, the separated integrated circuit packages may be placed in one or more tapes/reels, individual packaging, or other transport mechanism, for shipping packages to customers, etc.

Reliable performance of wafer-level packages is extremely important. In many applications using these types of packages, such as hand-held mobile devices, the interconnections between the packages and the devices in which they are incorporated, and the packages themselves, must be able to sustain various stresses. Example stresses include temperature cycles (e.g., environmental temperature changes or power on/off cycles) and mechanical shocks (e.g., dropping of a device). The structure of the wafer-level package plays a critical role in the reliability of the package and the reliability of the interconnections between the package and the system.

The front-end process of step104is critical to forming a reliable IC package. Aspects of the front-end process of step104may be performed differently, depending on factors such as the way the wafer is fabricated, etc. In some cases, the front-end process needs to deposit metal layers to provide circuitry/routing from chip terminals to external package terminals. Such metal layers are typically referred to as redistribution layers (RDLs).

There are three common approaches to the “front-end” process of step104. In the first approach, “redistribution layers” (RDLs), under bump metallization layers (UBMs), and bump interconnects (along with multiple polymer layers) are used to route electrical signals from chip terminals to external (e.g., PCB) terminals. An example of the first approach is described below with respect to flowchart500ofFIG. 5. In the second approach, RDLs are not used. Instead, a single polymer layer, UBMs, and bump interconnects are applied to route signals between on-chip terminals and external terminals. In the third approach, RDLs are not used. UBMs and bump interconnects are applied to route signals between on-chip terminals and external terminals. The second and third approaches are also described further below.

FIG. 5shows a flowchart500providing example steps for performing front-end processing of a wafer with redistribution layers and under bump metallization layers.

Flowchart500begins with step502. In step502, the wafer having the plurality of integrated circuit regions is received, each integrated circuit region having a plurality of accessible on-chip terminals configured in a ring. For instance,FIG. 6shows a bottom view of an integrated circuit region600of a wafer, such as wafer200shown inFIG. 2. As shown inFIG. 6, integrated circuit region600includes a ring602of terminals604(terminals604aand604bare individually indicated inFIG. 6). Terminals604are arranged in ring602on the bottom surface (e.g., surface202) of integrated circuit region600adjacent to a peripheral circumferential edge of integrated circuit region600. An integrated circuit region can include one or more of such rings602. Terminals604may be input, output, test, power, ground, etc., pads for an integrated circuit chip/die fabricated in, and defined by integrated circuit region600.

In step504, a first polymer layer is formed on the wafer over the plurality of integrated circuits regions.FIG. 7shows a cross-sectional view of a portion of integrated circuit region600, as processed according to flowchart500. As shown inFIG. 7, the portion of integrated circuit region600shown includes a chip portion702a, a terminal604aon a top surface704of chip portion702a, and a passivation layer706that covers the remainder of top surface704of chip portion702a. A first polymer layer708is formed on the wafer over integrated circuit region600(and other integrated circuit regions on the wafer), covering terminal604aand passivation layer706.

In step506, a plurality of first vias is formed through the first polymer layer to provide access to the plurality of accessible on-chip terminals. For example, as shown inFIG. 7, a first via710ais formed through first polymer layer708. Similarly to first via710a, a plurality of vias710are formed through first polymer layer708, each providing access to a respective terminal604of integrated circuit region600.

In step508, a plurality of redistribution layers is formed on the first polymer layer, each redistribution layer having a first portion in contact with a respective on-chip terminal through a respective first via and a second portion that extends over the first polymer layer. For example, as shown inFIG. 7, a redistribution layer712ais formed on first polymer layer708. As shown, a first portion714of redistribution layer712ais in contact with terminal604athrough first via710a, and a second portion716of redistribution layer712extends (e.g., laterally) over first polymer layer708. In this manner, a plurality of redistribution layers712are formed.

For instance,FIG. 8shows a plan view of a portion of integrated circuit region600at a left edge802of integrated circuit region600. As shown inFIG. 8, four redistribution layers712a-712dare formed on first polymer layer708, each redistribution layer having a first portion714and a second portion716. The first portions714of redistribution layers712a-712dare in contact with four corresponding terminals (not visible inFIG. 8) through four corresponding first vias (not visible inFIG. 8). The second portions716of redistribution layers712a-712dextend over first polymer layer708(e.g., in the right direction inFIG. 8).

Redistribution layers (RDL)712can be deposited to first polymer layer708according to many techniques (e.g., plating, sputtering, etc.) and can be processed (e.g., patterned) using many different lithography or other methods, as would be known to persons skilled in the relevant art(s). First portion714of redistribution layer712ais similar to standard via plating, and second portion716of redistribution layer712aextends from first portion714in a similar fashion as a standard metal trace formed on a substrate.

In step510, a second polymer layer is formed over the first polymer layer and plurality of redistribution layers. For example, as shown inFIG. 7, a second polymer layer718is formed on the wafer over integrated circuit region600(and other integrated circuit regions on the wafer), covering first polymer layer708and redistribution layer712a.

In step512, a plurality of second vias is formed through the second polymer layer to provide access to the second portion of each of the plurality of redistribution layers. For example, as shown inFIG. 7, a second via720ais formed through second polymer layer718to provide access to second portion716of redistribution layer712a. In this manner, a plurality of second vias720are formed through second polymer layer718, each providing access to a respective second portion716of a redistribution layer712. For instance,FIG. 8shows positions804a-804d(represented with dotted lines) where second vias720a-720dcorresponding to redistribution layers712a-712dcan be formed through second polymer layer718(not shown inFIG. 8).

In step514, a plurality of under bump metallization layers is formed on the second polymer layer, each under bump metallization layer being in contact with the second portion of a respective redistribution layer through a respective second via. For example, as shown inFIG. 7, an under bump metallization layer722ais in contact with second portion716of redistribution layer712athrough second via720a. In this manner, a plurality of under bump metallization layers722may be formed in contact with respective redistribution layers712through respective second vias720. For instance, inFIG. 8, under bump metallization layers722a-722d(not shown inFIG. 8) may be formed in positions804a-804dthrough respective second vias720a-720d(not shown inFIG. 8).

Under bump metallization (UBM) layers722are typically one or more metal layers formed (e.g., metal deposition—plating, sputtering, etc.) to provide a robust interface between redistribution layers722and a package interconnect mechanism (such as a bump interconnect, such as described in step516). A UBM layer serves as a solderable layer for a solder package interconnect mechanism. Furthermore, a UBM provides protection for underlying metal or circuitry from chemical/thermal/electrical interactions between the various metals/alloys used for the package interconnect mechanism. In an embodiment, UBM layers722are formed similarly to standard via plating.

In step516, a plurality of bump interconnects is formed on the plurality of under bump metallization layers. For example, as shown inFIG. 7, a bump interconnect724ais formed on under bump metallization layer722a. In this manner, a plurality of bump interconnects724may be formed in contact with respective under bump metallization layers722. For instance, inFIG. 8, bump interconnects724a-724d(not shown inFIG. 8) may be formed in positions804a-804d, each in contact with a respective one of under bump metallization layers722a-722d(not shown inFIG. 8). Bump interconnects724may be solder balls, for instance.

In this manner, an electrical connection is formed from each terminal604to a respective bump interconnect724(i.e., through a respective redistribution layer712and under bump metallization layer722). As just described with respect to flowchart500, multiple polymer layers (e.g., layers708and718) may be used to support the electrical connection. In many cases, single or multiple polymer material layers are deposited on the wafer below, above, or between the various applied RDL or UBM metal layers. The polymer layers serve multiple purposes. For example, they provide electrical isolation between the different circuitry/metal layers including between redistribution layers712and under bump metallization layers722and the circuitry within the chip (chip portion702a). The polymer layers are a relatively soft material that provides a layer between the package-to-system interconnect (e.g., bump interconnect724) and the chip to serve as a mechanical buffer to protect the chip, absorbing external stresses that are applied to the interconnect. The polymer layers further provide a layer between the package-to-system interconnect and the chip that can serve as a mechanical buffer to protect the interconnect from stresses that may result due to mismatches in material behavior of the various materials in the package and system (chip, PCB, solder, etc.)

The first front-end approach described with respect to flowchart500has disadvantages. For example, two polymer layers are needed, as well as deposition of an RDL layer, which require many process steps and additional materials, adding cost. Also, many new chips are being designed so that the RDL-type routing between the chip terminals and external terminals is not required. In other words, the chip terminals are designed to be coincident with the external terminals by performing the routing within the chip (e.g., during circuit fabrication in step102of flowchart100), rather than using chip-external RDLs. The second and third front-end approaches relate to packages having chip terminals that are coincident with the external terminals.

FIG. 9shows a flowchart900providing example steps for performing front-end processing of a wafer according to the second approach. Flowchart900begins with step902. In step902, the wafer having the plurality of integrated circuits regions is received, each integrated circuit region having a plurality of accessible on-chip terminals configured in an array. For instance,FIG. 10shows a bottom view of an integrated circuit region1000of a wafer, such as wafer200shown inFIG. 2. As shown inFIG. 10, integrated circuit region1000includes a rectangular array1002of terminals604(terminals604aand604bare individually indicated inFIG. 10). Terminals604are arranged in array1002on the bottom surface (e.g., surface202) of integrated circuit region1000.

In step904, a polymer layer is formed on the wafer over the plurality of integrated circuit regions.FIG. 11shows a cross-sectional view of a portion of integrated circuit region1100, as processed according to flowchart900. As shown inFIG. 11, the portion of integrated circuit region1000shown includes chip portion702a, terminal604aon a top surface704of chip portion702a, and passivation layer706that covers the top surface704of chip portion702a(other than terminal604a). Polymer layer708is formed on the wafer over integrated circuit region1000(and other integrated circuit regions on the wafer), covering terminal604aand passivation layer706.

In step906, a plurality of vias is formed through the polymer layer to provide access to the plurality of accessible on-chip terminals. For example, as shown inFIG. 11, a via710ais formed through polymer layer708. Similarly to via710a, a plurality of vias710is formed through polymer layer708, each via710providing access to a respective terminal604of integrated circuit region1000.

In step908, a plurality of under bump metallization layers is formed on the polymer layer, each under bump metallization layer being centered on a respective via, and in contact with a respective on-chip terminal through the respective via. For example, as shown inFIG. 11, an under bump metallization layer722ais in contact with terminal604athrough via710a. In this manner, a plurality of under bump metallization layers722may be formed in contact with respective terminals604through respective vias710.

In step910, a plurality of bump interconnects is formed on the plurality of under bump metallization layers. For example, as shown inFIG. 11, a bump interconnect724ais formed on under bump metallization layer722a. Similarly to bump interconnect724a, a plurality of bump interconnects724may be formed in contact with respective under bump metallization layers722. In this manner, an electrical connection is formed from each terminal604to a respective bump interconnect724(i.e., through a respective under bump metallization layer722).

The second front-end approach of flowchart900has disadvantages. The second approach is lower in cost relative to the first approach (flowchart500), since fewer steps are required, only a single polymer level (polymer layer708) is used, and a redistribution layer is not required. However, the chip terminals are coincident with the external terminals. During operating conditions or reliability assessment testing, external stresses are applied to the resulting IC package. The applied stresses transfer to the IC package through the bump interconnects724a. Although there is some polymer material (polymer layer708) between the chip (chip portion702a) and bump interconnect724a, a large portion of the interface is still a rigid connection (terminal604ato UBM722a). The second approach represents a significant risk of chip damage due to a transferred stress between bump interconnect724aand chip portion702athrough this rigid connection.

FIG. 12shows a flowchart1200providing example steps for performing front-end processing of a wafer according to the third approach. Flowchart1200begins with step1202. In step1202, the wafer having the plurality of integrated circuits regions is received, each integrated circuit region having a plurality of accessible on-chip terminals configured in an array. For instance, a wafer similar to wafer200shown inFIG. 2may be received, that has a plurality of integrated circuit regions similar to integrated circuit region1000shown inFIG. 10.

In step1204, a plurality of under bump metallization layers is formed, each under bump metallization layer being in contact with a respective on-chip terminal.FIG. 13shows a cross-sectional view of a portion of an integrated circuit region1300, as processed according to flowchart1200. As shown inFIG. 13, the portion of integrated circuit region1300shown includes chip portion702a, terminal604aon a top surface704of chip portion702a, and passivation layer706that covers the remainder of top surface704of chip portion702a. Also, as shown inFIG. 13, an under bump metallization layer722ais formed directly on terminal604a. In this manner, a plurality of under bump metallization layers722may be formed in contact with respective terminals604of the integrated circuit region.

In step1206, a plurality of bump interconnects is formed on the plurality of under bump metallization layers. For example, as shown inFIG. 13, a bump interconnect724ais formed on under bump metallization layer722a. Likewise, a plurality of bump interconnects724may be formed in contact with respective under bump metallization layers722.

In this manner, an electrical connection is formed from each terminal604to a respective bump interconnect724(i.e., through a respective under bump metallization layer722). The third front-end approach of flowchart1300has disadvantages. The third approach is lower in cost relative to the first and second approaches (flowcharts500and900), since fewer steps are required, a polymer level is not used, and a redistribution layer is not required. However, because a polymer layer is not present, the only interface between the chip (chip portion702) and bump interconnect724ais under bump metallization layer722a, which is typically rigid. Therefore, most stress received at bump interconnect724ais transferred directly to the chip. This represents a significant risk of causing chip damage. The risk is increased for advanced silicon process technologies which use low-k dielectric materials which are very fragile and easily damaged.

Example embodiments of the present invention are described in the following section that overcome the disadvantages of the three front-end processing approaches described above.

EXAMPLE EMBODIMENTS

The example embodiments described herein are provided for illustrative purposes, and are not limiting. The examples described herein may be adapted to a variety of types of integrated circuit packages. Further structural and operational embodiments, including modifications/alterations, will become apparent to persons skilled in the relevant art(s) from the teachings herein.

According to an embodiment, a routing interconnect for each chip terminal is used to couple the chip terminal to a bump interconnect (or other package interconnect type). In an embodiment, the routing interconnect directly connects the chip terminal to the bump interconnect. In another embodiment, an under bump metallization layer mounts the bump interconnect to the routing interconnect, and thus is also used to connect the chip terminal to the bump interconnect. In embodiments, an insulating layer between the routing interconnect and chip is used to provide stress absorption, while allowing for fewer manufacturing process steps than required in multiple polymer layer configurations.

FIG. 14shows a flowchart1400for forming integrated circuit packages, according to an embodiment of the present invention. Other structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the discussion provided herein.

Flowchart1400begins with step1402. In step1402, the wafer having the plurality of integrated circuits regions is received, each integrated circuit region having a plurality of accessible on-chip terminals configured in an array. For instance, a wafer similar to wafer200shown inFIG. 2may be received, that has a plurality of integrated circuit regions similar to integrated circuit region1000shown inFIG. 10. As shown inFIG. 10, integrated circuit region1000includes a rectangular array1002of terminals604(terminals604aand604bare individually indicated inFIG. 10). Terminals604are arranged in array1002on the bottom surface (e.g., surface202) of integrated circuit region1000. Array1002may be a regular rectangular array of terminals as shown inFIG. 10, or may have other terminal array patterns or arrangements, including a staggered array of terminals, etc. Array1002does not necessarily need to be a full array of terminals604.

In step1404, an insulating layer is formed on the wafer over the plurality of integrated circuit regions.FIG. 15shows a cross-sectional view of a portion of an integrated circuit region1500, as processed according to flowchart1400, according to an embodiment of the present invention. The portion of integrated circuit region1500shown inFIG. 15includes chip portion702a, terminal604aon a top surface704of chip portion702a, and passivation layer706that covers top surface704of chip portion702a(other than terminal604a). A layer1502of insulating material is formed on the wafer over integrated circuit region1500(and other integrated circuit regions on the wafer), covering terminal604aand passivation layer706. Insulating layer1502may be a shock absorbing and electrically insulating material, such as a polymer, a dielectric material, and/or other shock absorbing and electrically insulating material. Insulating layer1502may include one or more layers of material. Insulating layer1502may be applied in any manner, conventional or otherwise, as would be known to persons skilled in the relevant art(s).

In step1406, a plurality of vias is formed through the insulating layer to provide access to the plurality of accessible on-chip terminals. For example, as shown inFIG. 15, a via1504ais formed through insulating layer1502. A plurality of vias1504are formed through insulating layer1502, each providing access to a respective terminal604of integrated circuit region1500. For example,FIG. 16shows a plan view of a portion of integrated circuit region1500adjacent to a left edge1602of region1500, according to an example embodiment of the present invention. Four vias1504a-1504dare shown that are a portion of a larger array of vias1504. As shown inFIG. 16, vias1504a-1504dare formed through insulating layer1502, providing respective access to terminals604a-604d. Note that vias1504may have sloped walls, as shown inFIG. 15, may have straight vertical walls (e.g., via1504may have a cylindrical shape), or may have other shapes. Vias1504may be formed in any manner, including etching, drilling, etc., as would be known to persons skilled in the relevant art(s).

In step1408, a plurality of routing interconnects is formed on the insulating layer such that each routing interconnect of the plurality of routing interconnects has a first portion in contact with a respective terminal through a respective via through the insulating layer and has a second portion that extends over the insulating layer. For example, as shown inFIG. 15, a routing interconnect1506ais formed on insulating layer1502. Routing interconnect1506has a first portion1508and a second portion1510, similarly to routing distribution layer712ashown inFIG. 7. First portion1508of routing interconnect1506is in contact with terminal604athrough via1504a, and second portion1510of routing interconnect1506extends (e.g., laterally) over insulating layer1502. In this manner, a plurality of redistribution layers1502are formed for integrated circuit region1500.

For instance,FIG. 17shows a plan view of the portion of integrated circuit region1500shown inFIG. 16. InFIG. 17, four routing interconnects1506a-1506dare formed on insulating layer1502, each routing interconnect having a first portion1508and a second portion1510. The first portions1508a-1508dof routing interconnects1506a-1506dare in contact with a corresponding one of terminals604a-604d(shown inFIG. 16) through a corresponding one of vias1504a-1504d(shown inFIG. 16). The second portions1510a-1510dof routing interconnects1506a-1506dextend over insulating layer1502(e.g., in the right direction inFIG. 16).

Note that second portions1510of routing interconnects1506can have various shapes. For example, as shown inFIG. 17, second portions1508may be rectangular shaped. Alternatively, second portions1508may have rounded shapes, such as described in detail with respect to some examples below, or may have other shapes. For example, first portion1508of routing interconnect1506amay be similar to a standard via plating, and second portion1510of routing interconnect1506amay extend from first portion1508in a similar fashion as a standard metal trace formed on a substrate. Routing interconnects1506may be formed of any suitable electrically conductive material, including a metal such as a solder or solder alloy, copper, aluminum, gold, silver, nickel, tin, titanium, a combination of metals/alloy, etc. Routing interconnects1506may be formed in any manner, including sputtering, plating, lithographic processes, etc., as would be known to persons skilled in the relevant art(s).

In step1410, a plurality of bump interconnects is formed on the plurality of metallization layers, each bump interconnect being connected to the second portion of a respective metallization layer. For example, as shown inFIG. 15, a bump interconnect1512ais formed on routing interconnect1506a. In this manner, a plurality of bump interconnects1512may be formed in contact with respective routing interconnects1506. For instance, inFIG. 18, a plurality of bump interconnects1512a-1512dare formed as part of an array of bump interconnects1512, each in contact with a respective one of routing interconnects1506a-1506d. Bump interconnects1512may be formed of any suitable electrically conductive material, including a metal such as a solder or solder alloy, copper, aluminum, gold, silver, nickel, tin, titanium, a combination of metals/alloy, etc. Bump interconnects1512may have any size and pitch, as desired for a particular application. Bump interconnects1512may be formed in any manner, including sputtering, plating, lithographic processes, etc., as would be known to persons skilled in the relevant art(s).

In this manner, an electrical connection is formed from each terminal604to a respective bump interconnect1512using a respective routing interconnect1506. Any number of such electrical connections may be formed as dictated by a particular application, including forming electrical connections for tens, hundreds, or even larger arrays of terminals604. After the wafer is processed according to flowchart1400, further steps of flowchart100shown inFIG. 1may be applied to the wafer to process the integrated circuit regions into separate integrated circuit packages. For example, each integrated circuit region may be tested (step106), back end processing may be performed to separate the regions into separate integrated circuit packages (step108), and the separate packages can be processed for shipping (step110).

As shown inFIGS. 15 and 18, in an embodiment, bump interconnects1512are positioned so that they reside entirely on insulating layer1502(through routing interconnects1506). Insulating layer1502provides stress absorption for the chip of the resulting integrated circuit package with regard to stresses applied to bump interconnect1512. The second and third approaches described above with respect toFIGS. 9-13did not perform adequate stress absorption, which could lead to unwanted chip damage. Furthermore, as shown inFIG. 15, bump interconnect1512ais positioned entirely above insulating layer1502without the need for additional layers. The first approach described above with respect toFIGS. 5-8required two polymer layers, which is a more complicated and expensive technique. Thus, the embodiments described with respect toFIGS. 14-18provide advantages over the three approaches described in the prior section.

In an embodiment, a separate under bump metallization layer is not required for mounting a bump interconnect, as is required in the three conventional approaches described in the prior section. As shown inFIG. 15, bump interconnect1512ais attached directly to routing interconnect1506a. For example, bump interconnect1512amay be attached to routing interconnect1506aby soldering (e.g., reflow), etc.

FIG. 19shows a cross-sectional view of a portion of an integrated circuit region1900, according to another embodiment of the present invention. In the embodiment ofFIG. 19, routing interconnect1506aincludes a plurality of layers1902a-1902c. For example, plurality of layers1902a-1902cis formed of a stack or stack-up of layers of one or more different materials, such as different metals/metal alloys described elsewhere herein. InFIG. 19, outermost layer1902aof the plurality of layers1902a-1902cis removed in a region1904(using chemical etching, lithography, etc.) where bump interconnect1512ais connected to routing interconnect1506a. InFIG. 19, outermost layer1902ais a material that is not solderable, and bump interconnect1512ais a solder that does not stick to the material of outermost layer1902a. However, second layer1902bis a solderable material to which bump interconnect1512acan stick. Thus, the material of outermost layer1902ais removed from routing interconnect1506in region1904so that bump interconnect1512acan be attached to second layer1902b. Furthermore, because outermost layer1902ais not solderable, and is present on routing interconnect1506aoutside of region1904, outermost layer1902aprevents solder of bump interconnect1512afrom wetting toward via1504aand potentially damaging the chip at terminal604a.

FIG. 20shows a cross-sectional view of a portion of an integrated circuit region2000, according to another embodiment of the present invention. In the embodiment ofFIG. 20, an additional metal layer2002is formed on routing interconnect1506ain a region2004. InFIG. 20, bump interconnect1512ais a solder that does not stick to the material of routing interconnect1506a, which is not solderable. However, the material of additional metal layer2002is solderable, and thus bump interconnect1512acan stick to additional metal layer2002. Thus, additional metal layer2002is applied as an outermost solderable layer to routing interconnect1506ain region2004so that bump interconnect1512acan be attached to routing interconnect1506athrough layer2002. Furthermore, routing interconnect1506a, which is not solderable, prevents solder of bump interconnect1512afrom wetting toward via1504aand potentially damaging the chip.

In embodiments, bump interconnects1512can be positioned and/or sized in various ways. For example,FIG. 21shows the cross-sectional view of integrated circuit region2000shown inFIG. 20. InFIG. 21, an opening of via1504ahas an edge position2102nearest bump interconnect1512a. Bump interconnect1512ahas a base edge position2104nearest via1504a(e.g., coincident with an edge of additional metal layer2002, when present). In the embodiment ofFIG. 21, bump interconnect1512adoes not overlap via1504a(e.g., does not overhang via1504ainFIG. 21). Furthermore, a distance2106between via edge position2102and bump interconnect base edge position2104is greater than zero. Thus, via1504aand bump interconnect1512aare spaced apart.

In another embodiment, a via and bump interconnect may be separated by a zero distance, or may even overlap. For example,FIG. 22shows a cross-sectional view of an integrated circuit region2200, where a bump interconnect2202ais attached to routing interconnect1506a, and overlaps via1504a. In fact, inFIG. 22, bump interconnect2202acompletely overlaps via1504a. As shown inFIG. 22, an opening of via1504ahas a center point2204. A base of bump interconnect2202ahas a center point2206. Center point2204of via1504ais separated from center point2206of the base of bump interconnect2202aby a distance2208that is greater than zero. Thus, in an embodiment, via1504aand bump interconnect2202amay be overlapping, but are not co-centered in integrated circuit region2200, and instead their centers are offset from each other.

Furthermore, when overlapping, a bump interconnect may partially or entirely fill the respective via. For example, in the embodiment ofFIG. 22, bump interconnect2202afills via1504a.

In another embodiment, a via and respective bump interconnect may be separated by a distance, but the routing interconnect may be configured to allow solder to flow from the bump interconnect to the via (such as during solder reflow of the bump interconnect). For example,FIG. 23shows a cross-sectional view of an integrated circuit region2300, where a bump interconnect2302ais attached to routing interconnect2304a. Bump interconnect2302adoes not overlap with via1504ainFIG. 23. As shown inFIG. 23, routing interconnect2304aincludes a first portion2306, a second portion2308, and a third portion2310. First portion2306is in contact with terminal604athrough via1504a. First bump interconnect2302ais connected to second portion2308. Third portion2310is similar to a trace routed on insulating layer1502, and connects together first and second portions2306and2308. Third portion2310is configured to allow solder applied to second portion2308of routing interconnect2304ato flow into via1504a(e.g., during reflow of bump interconnect2302a). Thus, third portion2310functions as a conduit for solder from second portion2308to first portion2306.

Third portion2310can be configured in various ways to control a rate of solder flow from second portion2308to first portion2306. For example,FIGS. 24 and 25show example embodiments for third portion2310.FIG. 24shows a plan view of routing interconnect2304a, where third portion2310has a width2402greater than a diameter2404of via1504a.FIG. 25shows a plan view of an alternative routing interconnect2304a, where third portion2310has a width2502less than diameter2404of via1504a. Thus, in the embodiment ofFIG. 24, a higher rate of solder flow is enabled because third portion2310is wider relative to third portion2310inFIG. 25. InFIG. 25, a lower rate of solder flow is enabled because third portion2310is narrower relative to third portion2310inFIG. 24. The width of third portion2310can be increasingly narrowed until solder is essentially prevented from flowing into via1504a.

CONCLUSION