Dielectric mesh isolated phase change structure for phase change memory

A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

PARTIES TO A JOINT RESEARCH AGREEMENT

International Business Machines Corporation, a New York corporation, and Macronix International Corporation, Ltd., a Taiwan corporation, are parties to a Joint Research Agreement.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to memory devices based on chalcogenide materials, and methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.

The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.

However, attempts to reduce the size of the phase change material element and/or the electrodes can result in electrical and mechanical reliability issues of the cell because of failures associated with the small contact surface therebetween. For example, because GST has two stable crystalline states that have different densities, modulation between the two crystalline states and the amorphous state can cause stresses at the interface and within the GST material.

The magnitude of the reset current needed to induce a phase change can be affected by doping the phase change material. Chalcogenides and other phase change materials can be doped with impurities to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon oxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, e.g., U.S. Pat. No. 6,800,504 (metal doping), and U.S. Patent Application Publication No. U.S. 2005/0029502 (nitrogen doping).

U.S. Pat. No. 6,087,674, and its parent U.S. Pat. No. 5,825,046 by Ovshinsky et al., describe forming composite memory material in which phase change material is mixed with relatively high concentrations of dielectric material in order to manage the resistance of the composite memory material. The nature of the composite memory material described in these patents is not clear, because it describes composites as layered structures as well as mixed structures. The dielectric materials described in these patents cover a very broad range.

A number of researchers have investigated the use of silicon oxide doping of chalcogenide material for the purposes of reducing the reset current needed for operation of the memory devices. See, Ryu, et al., “SiO2Incorporation Effects in Ge2Sb2Te5Films Prepared by Magnetron Sputtering for Phase Change Random Access Memory Devices”, Electrochemical and Solid-State Letters, 9 (8) G259-G261, (2006); Lee et al., “Separate domain formation in Ge2Sb2Te5—SiOxmixed layer”, Applied Physics Letters 89, 163503 (2006); Czubatyj et al., “Current Reduction in Ovonic Memory Devices”, E*PCOS06 (2006); and Noh et al., “Modification of Ge2Sb2Te5by the Addition of SiOxfor Improved Operation of Phase Change Random Access Memory”, Mater. Res. Soc. Symp. Proc. Vol. 888 (2006). These references suggest that relatively low concentrations of silicon oxide doping in Ge2Sb2Te5result in substantial increases in resistance and corresponding reductions in reset current. The Czubatyj et al. article suggests that the improvement in resistance in a silicon oxide doped GST alloy saturates at about 10 vol % (6.7 at %), and reports that doping concentrations up to 30 vol % silicon oxide had been tested, without providing details. The Lee et al. publication describes a phenomenon at relatively high doping concentrations around 8.4 at %, by which the silicon oxide appears to separate from the GST after high-temperature annealing to form domains of GST surrounded by boundaries that are primarily silicon oxide.

Research has progressed to provide memory devices that operate with low reset current by adjusting a doping concentration in phase change material, and by providing structures with very small dimensions. One problem with very small dimension phase change devices involves endurance. Specifically, memory cells made using phase change materials can fail as the composition of the phase change material slowly changes with time because of the instability of the amorphous versus crystalline state. For example, a memory cell in which the active region has been reset to a generally amorphous state may over time develop a distribution of crystalline regions in the active region. If these crystalline regions connect to form a low resistance path through the active region, when the memory cell is read a lower resistance state will be detected and result in a data error. See, Gleixner, “Phase Change Memory Reliability”, tutorial. 22nd NVSMW, 2007.

It is therefore desirable to provide memory cells having a small reset current and addressing the issues of data retention discussed above, as well as addressing the reliability issues of small contact surfaces between electrodes and phase change material discussed above.

SUMMARY OF THE INVENTION

A method for manufacturing a memory device is described using silicon oxide doped chalcogenide material which results in an improved memory cell. The method comprises forming a first electrode having a contact surface, a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material. The phase change memory material comprises a chalcogenide material doped with a dielectric material. The process includes melting and solidifying the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. This cycling causes formation of a mesh of the dielectric material in the active region with at least one domain of chalcogenide material, without formation of the mesh outside the active region. The method has been demonstrated for silicon oxide doped for GexSbyTez, where x=2, y=2 and z=5, doped with 10 to 20 atomic % silicon oxide, and the resulting device demonstrates substantial improvement. However, the process can be extended to other chalcogenide materials and dielectric doping materials which are characterized by mesh formation as a result of melting and cooling cycles, reduced grain size in the polycrystalline state, and suppression of the formation of at least one of a plurality of crystalline phases in the polycrystalline state.

For a chalcogenide material used which is characterized by a plurality of solid crystalline phases, such as GexSbyTez, where x=2, y=2 and z=5, which has an FCC solid crystalline phase and an HCP solid crystalline phase, the chalcogenide material is doped with a concentration of dielectric material sufficient to prevent formation of at least one of the solid crystalline phases, such as the HCP solid crystalline phase, in the body of material outside the active region. Thus, the chalcogenide material used in the phase change memory material, when not doped with the dielectric is characterized by a first solid crystalline phase (e.g. HCP) having first volume and by a second solid crystalline phase (e.g. FCC) having second volume, the phase change memory material having a volume in the amorphous phase which is closer to the second volume than the first volume, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to promote formation of the second solid crystalline phase. By suppressing formation of the HCP phase, and thus limiting the structure in the set state to only or substantially only the FCC phase, the amount of change in volume that occurs in the transition from the amorphous phase to the crystalline phase is reduced, improving reliability of the memory. Also, the set operation occurs more quickly, when it is limited to only or substantially only the FCC phase.

Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

A manufacturing process described herein includes forming circuitry on the memory device to apply set and reset pulses to the memory cell for writing data, and performing said melting and cooling cycling in the active region of the memory cell by applying a sequence of reset pulses, or in the alternative, a sequence of set and reset pulses, to the memory cell.

A phase change memory device is provided that comprises a first electrode and a second electrode, and a body of phase change memory material in contact with the first and second electrodes, the phase change memory material comprising a silicon oxide (or other dielectric material) doped chalcogenide material. The body of phase change material has an active region between the first and second electrodes, the active region comprising a mesh of dielectric material with at least one domain of chalcogenide material, and has a region outside of the active region without the mesh and in which the phase change memory material has a polycrystalline state with a small grain size.

Other features, combinations of features, aspects and advantages of the technology described herein can be seen in the drawings, the detailed description and the claims which follow.

DETAILED DESCRIPTION

The following description of the disclosure will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the disclosure to the specifically disclosed embodiments and methods, but that the disclosure may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present disclosure, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals.

In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline phases.FIG. 1is a graph of memory cells having one of two states (storing a single bit of data), a low resistance set (programmed) state100and a high resistance reset (erased) state102each having non-overlapping resistance ranges.

The difference between the highest resistance R1of the low resistance set state100and the lowest resistance R2of the high resistance reset state102defines a read margin101used to distinguish cells in the set state100from those in the reset state102. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the low resistance state100or to the high resistance state102, for example by measuring whether the resistance of the memory cell is above or below a threshold resistance value RSA103within the read margin101.

In order to reliably distinguish between the reset state102and the set state100, it is important to maintain a relatively large read margin101. However, it has been observed that some phase change memory cells in the reset state102can experience an erratic “tailing bit” effect in which the resistance of the memory cell decreases over time to below the threshold resistance value RSA103, resulting in data retention problems and bit errors for those memory cells.

FIGS. 2A-2Cillustrate schematic diagrams of three prior art phase change memory cells each having a phase change material memory element220(represented in the Figures by a variable resistor) and coupled to a select device such as a transistor or diode.

FIG. 2Aillustrates a schematic diagram of a prior art memory cell200including a field effect transistor (FET)210as the select device. A word line240extending in a first direction is coupled to the gate of the FET210and a memory element220couples the drain of the FET210to a bit line230extending in a second direction.

FIG. 2Billustrates a schematic diagram of memory cell202similar to that ofFIG. 2Aexcept that the access device is implemented as a bipolar junction transistor (BJT)212, whileFIG. 2Cillustrates a schematic diagram of a memory cell204similar to that ofFIG. 2Aexcept the access device is implemented as a diode214.

Reading or writing can be achieved by applying suitable voltages to the word line240and bit line230to induce a current through the memory element220. The level and duration of the voltages applied is dependent upon the operation performed, e.g. a reading operation or a writing operation.

In a reset (or erase) operation of a memory cell having memory element220, a reset pulse is applied to the word line240and bit line230of suitable amplitude and duration to induce a current sufficient to cause a transition of an active region of the phase change material into an amorphous phase, thereby setting the phase change material to a resistance within a resistive value range associated with the reset state. The reset pulse is a relatively high energy pulse, sufficient to raise the temperature of at least the active region of the memory element220above the transition (crystallization) temperature of the phase change material and also above the melting temperature to place at least the active region in a liquid state. The reset pulse is then quickly terminated, resulting in a relatively quick quenching time as the active region quickly cools to below the transition temperature so that at least the active region stabilizes to an amorphous phase.

In a set (or program) operation of a memory cell having memory element220, a program pulse is applied to the word line240and bit line230of suitable amplitude and duration to induce a current sufficient to raise the temperature of at least a portion of the active region above the transition temperature and cause a transition of at least a portion of the active region from the amorphous phase into a crystalline phase, this transition lowering the resistance of the memory element220and setting the memory cell to the desired state.

In a read (or sense) operation of a memory cell having memory element220, a read pulse is applied to the word line240and bit line230of suitable amplitude and duration to induce a current to flow that does not result in the memory element220undergoing a change in resistive state. The current through the memory cell is dependent upon the resistance of the memory element220and thus the data value stored in the memory cell.

As was described above, in an array some of the memory cells in the high resistance reset state can experience a tailing bit effect in which those memory cells undergo a reduction in resistance over time, resulting in data retention issues and bit errors.

Illustrated inFIGS. 3 and 4is a possible early-fail model for the trailing bit effect of memory cells in reset. Since the initial reset resistance of memory cells experiencing the tailing bit effect is high, a small or otherwise defective active region is not believed to be the likely cause. Instead, in the early fail model illustrated inFIGS. 3 and 4a random distribution of crystallized regions within the generally amorphous active region will undergo growth over time. For memory cells experiencing the tailing bit effect the random arrangement of the crystallized regions results in the need for very little growth before a low resistance path through the active region is formed.

FIG. 3Aillustrates a prior art “mushroom type” memory cell300having a first electrode314extending through dielectric315, a memory element220comprising phase change material, and a second electrode312on the memory element220. The first electrode314may, for example, be coupled to a terminal of an access device such as a diode or transistor, while the second electrode312may be coupled to a bit line. The first electrode314has a width316less than the width of the second electrode312and memory element220. Because of this difference in width, in operation the current density is largest in the region adjacent the first electrode314, resulting in the active region310having a “mushroom” shape as shown in the Figure.

It is desirable to minimize the width (which in some examples is a diameter) of the first electrode314so that higher current densities are achieved with small absolute current values through the memory element220. However, attempts to reduce the width of the first electrode314can result in issues in the electrical and mechanical reliability of the interface between the first electrode314and the memory element220due to the small contact surface therebetween.

In reset, the memory element220has a generally amorphous active region310and a random distribution of crystalline regions320within the active region310. As shown inFIG. 3B, over time the crystalline regions320within the active region310will experience growth but do not form a complete low resistance path through the active region310. Thus, although the memory cell illustrated inFIGS. 3A-3Bmay experience some reduction in resistance, it does not experience the tailing bit effect.

FIGS. 4A-4Billustrate a memory cell400having a random distribution of crystallized regions420within the active region410such that over time a low resistance path450is formed through the active region410as shown inFIG. 4B, resulting in the memory cell ofFIGS. 4A-4Bexperiencing the tailing bit effect.

FIGS. 5A-5Billustrate cross-sectional views of a memory cell500having an active region510comprising phase change domains511within a dielectric-rich mesh512, the memory cell500addressing the tailing bit and reliability issues described above and resulting in improved data retention, reduced bit errors and higher speed operation.

The memory cell500includes a first electrode520extending through dielectric530to contact a bottom surface of the memory element516, and a second electrode540on the memory element516consisting of a body of dielectric doped phase change material. The first and second electrodes520,540may comprise, for example, TiN or TaN. Alternatively, the first and second electrodes520,540may each be W, WN, TiAlN or TaAlN, or comprise, for further examples, one or more elements selected from the group consisting of doped-Si, Si, C, Ge, Cr, Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru and combinations thereof.

In the illustrated embodiment the dielectric530comprises SiN. Alternatively, other dielectric materials may be used.

The phase change material of memory element516in this example comprises Ge2Sb2Te5material doped with 10 to 20 atomic percent (at %) silicon oxide. Other chalcogenides and dielectric materials characterized by the mesh formation may be used as well. As can be seen in the Figures the width522(which in some embodiments is a diameter) of the first electrode520is less than that of the memory element516and top electrode540, and thus current is concentrated in the portion of the memory element516adjacent the first electrode520, resulting in the active region510as shown. The memory element516also includes an inactive region513outside the active region510, the inactive region513in a polycrystalline state with small grain size, without dielectric mesh formation.

The active region510comprises phase change domains511within a dielectric-rich mesh512. The dielectric-rich mesh512comprises a higher concentration of silicon oxide material than that of the inactive region513, and the phase change domains511comprise a higher concentration of chalcogenide material than that of the inactive region513.

FIG. 5Aillustrates heuristically, the memory cell500in the high resistance reset state. In a reset operation of the memory cell500, bias circuitry (See, for example, bias circuitry voltage and current sources1736ofFIG. 17with the accompanying controller1734) coupled to the first and second electrodes520,540induces a current to flow between the first and second electrodes520,540via the memory element516sufficient to induce a high resistance generally amorphous phase in the phase change domains511of the active region510to establish a high resistance reset state in the memory cell500. In the inactive region513outside the active region, the body of dielectric doped chalcogenide remains in the polycrystalline state, with a small grain size.

FIG. 5Billustrates heuristically, the memory cell500in the low resistance set state. In a set operation of the memory cell500, bias circuitry coupled to the first and second electrodes520,540induces a current to flow between the first and second electrodes520,540via the memory element516sufficient to induce a low resistance generally crystalline phase in the phase change domains511of the active region510to establish a low resistance set state in the memory cell500. The sizes of the domains in the low resistance state may be different than in the high resistance state, as suggested byFIGS. 5A and 5B. However, this has not been clearly demonstrated by experiment.

FIG. 6illustrates an expanded view of the memory cell500in the reset state ofFIG. 5A, with reference to which one theory under which the improved endurance of cells made as described herein is offered. Since the dielectric mesh512surrounds and separates the phase change domains511, the memory cell500can still maintain a high resistance state even if crystalline regions within the generally amorphous phase change domains511provide a low resistance path600through some of the domains511. Thus, the dielectric mesh512limits the re-growth of the crystalline regions over time and thereby limits the formation of a low resistance path through the active region510. Therefore the tailing bit failure rate is significantly reduced, resulting in improved data retention and reduced bit errors.

FIG. 7illustrates a graph of the failure time versus temperature and illustrates the improved retention of memory cells as described herein. Line700represents an extrapolation of measured data of memory cells comprising Ge2Sb2Te5material doped with 10 to 20 at % silicon oxide and having an active region comprising phase change domains within a dielectric-rich mesh as described herein.

FIG. 7also includes line710representing an extrapolation of measured data of memory cells comprising undoped GST material. As can be seen inFIG. 7, a significant improvement in the failure time is achieved for the memory cells having an active region comprising phase change domains within a dielectric-rich mesh.

FIGS. 8A-8Billustrate x-ray diffraction XRD spectra data upon annealing of undoped Ge2Sb2Te5phase change material. GST based memory materials generally include two crystalline phases, a lower transition temperature FCC (face-centered cubic) phase and a higher transition temperature HCP (hexagonal close-packed) phase, the HCP phase having a higher density than the FCC phase. In general the transition from the FCC phase to the HCP phase is not desirable since the resulting decrease in memory material volume causes stresses within the memory material and at the interfaces between electrodes and the memory material. Also, the volume change from the amorphous phase to the crystalline phase is smaller for FCC phase material, and the transition will occur at higher speed.

FIGS. 8A and 8Billustrate that the transition of undoped Ge2Sb2Te5from the FCC phase to the HCP phase occurs below an anneal temperature of 400 degrees C. Since a memory cell comprising undoped Ge2Sb2Te5may experience a temperature of 400 degrees C. or more during set operations, issues can arise in the reliability of the memory cell due to this transition to the HCP state. Also, the speed of transition to the HCP phase will be slower.

FIGS. 8A-8Balso illustrate XRD spectra data of doped Ge2Sb2Te5material having 10 at % and 20 at % silicon oxide as described herein, illustrating that the crystalline structure of the doped material remains in the FCC state at an anneal temperature of up to 400 degrees C.

Moreover, since inFIGS. 8A-8Bthe widths of the diffraction peaks of doped Ge2Sb2Te5material having 10 at % and 20 at % silicon oxide are wider than that of undoped Ge2Sb2Te5, the doped Ge2Sb2Te5has a smaller grain size than undoped Ge2Sb2Te5.

As a result, memory cells as described herein comprising doped Ge2Sb2Te5material having 10 to 20 at % silicon oxide annealed at temperatures as high as 400 degrees C. during set operations avoid the higher density HCP state, and thus experience less mechanical stress and have increased reliability and higher switching speed, compared to memory cells comprising undoped Ge2Sb2Te5.

Prior art techniques include the doping of GST material with Nitrogen to modify properties of memory elements, andFIG. 9illustrates XRD data of Ge2Sb2Te5material doped with various atomic percentages of Nitrogen.FIG. 9shows that the transition of Nitrogen doped Ge2Sb2Te5from the FCC state to the HCP occurs below an anneal temperature of 400 degrees C. Therefore, memory cells as described herein comprising doped Ge2Sb2Te5material having 10 to 20 at % silicon oxide will experience less mechanical stress and have increased reliability and speed compared to memory cells comprising Nitrogen doped Ge2Sb2Te5.

FIG. 10illustrates a process flow diagram andFIGS. 11A-11Dillustrate steps in a manufacturing process for manufacturing a memory cell comprising Ge2Sb2Te5material doped with 10 to 20 at % silicon oxide and having an active region comprising phase change domains within a dielectric-rich mesh as described herein.

At step1000the first electrode520having a width or diameter522is formed extending through dielectric530, resulting in the structure illustrated in the cross-sectional view ofFIG. 11A. In the illustrated embodiment the first electrode520comprises TiN and the dielectric530comprises SiN. In some embodiments the first electrode520has a sublithographic width or diameter522.

The first electrode520extends through dielectric530to underlying access circuitry (not shown). The underlying access circuitry can be formed by standard processes as known in the art, and the configuration of elements of the access circuitry depends upon the array configuration in which the memory cells described herein are implemented. Generally, the access circuitry may include access devices such as transistors and diodes, word lines and sources lines, conductive plugs, and doped regions within a semiconductor substrate.

The first electrode520and the dielectric layer530can be formed, for example, using methods, materials, and processes as disclosed in U.S. patent application Ser. No. 11/764,678 filed on 18 Jun. 2007 entitled “Method for Manufacturing a Phase Change Memory Device with Pillar Bottom Electrode”, which is incorporated by reference herein. For example, a layer of electrode material can be formed on the top surface of access circuitry (not shown), followed by patterning of a layer of photoresist on the electrode layer using standard photo lithographic techniques so as to form a mask of photoresist overlying the location of the first electrode520. Next the mask of photoresist is trimmed, using for example oxygen plasma, to form a mask structure having sublithographic dimensions overlying the location of the first electrode520. Then the layer of electrode material is etched using the trimmed mask of photoresist, thereby forming the first electrode520having a sublithographic diameter522. Next dielectric material530is formed and planarized, resulting in the structure illustrated inFIG. 11A.

As another example, the first electrode520and dielectric530can be formed using methods, materials, and processes as disclosed in U.S. patent application Ser. No. 11/855,979 filed on 14 Sep. 2007 entitled “Phase Change Memory Cell in Via Array with Self-Aligned, Self-Converged Bottom Electrode and Method for Manufacturing”, which is incorporated by reference herein. For example, the dielectric530can be formed on the top surface of access circuitry followed by sequentially forming an isolation layer and a sacrificial layer. Next, a mask having openings close to or equal to the minimum feature size of the process used to create the mask is formed on the sacrificial layer, the openings overlying the location of the first electrode520. The isolation layer and the sacrificial layers are then selectively etched using the mask, thereby forming a via in the isolation and sacrificial layers and exposing a top surface of the dielectric layer530. After removal of the mask, a selective undercutting etch is performed on the via such that the isolation layer is etched while leaving the sacrificial layer and the dielectric layer530intact. A fill material is then formed in the via, which due to the selective undercutting etch process results in a self-aligned void in the fill material being formed within the via. Next, an anisotropic etching process is performed on the fill material to open the void, and etching continues until the dielectric layer530is exposed in the region below the void, thereby forming a sidewall spacer comprising fill material within the via. The sidewall spacer has an opening dimension substantially determined by the dimensions of the void, and thus can be less than the minimum feature size of a lithographic process. Next, the dielectric layer530is etched using the sidewall spacers as an etch mask, thereby forming an opening in the dielectric layer530having a diameter less than the minimum feature size. Next, an electrode layer is formed within the openings in the dielectric layer530. A planarizing process, such as chemical mechanical polishing CMP, is then performed to remove the isolation layer and the sacrificial layer and to form the first electrode520, resulting in the structure illustrated inFIG. 11A.

At step1010a layer of phase change material1100comprising doped Ge2Sb2Te5material having 10 to 20 at % silicon oxide is deposited on the first electrode520and dielectric530ofFIG. 11A, resulting in the structure illustrated inFIG. 11B. The deposition of Ge2Sb2Te5and silicon oxide may be carried out by co-sputtering of a GST target with for one example, a DC power of 10 Watts and a SiO2target with an RF power of 10 to 115 Watts in an argon atmosphere.

Next, at step1020annealing is performed to crystallize the phase change material. In the illustrated embodiment the thermal annealing step is carried out at 300 degrees C. for 100 seconds in a nitrogen ambient. Alternatively, since subsequent back-end-of-line processes performed to complete the device may include high temperature cycles and or a thermal annealing step depending upon the manufacturing techniques used to complete the device, in some embodiments the annealing at step1020may accomplished by following processes, and no separate annealing step is added to the manufacturing line.

Next, at step1030second electrode540is formed, resulting in the structure illustrated inFIG. 11C. In the illustrated embodiment the second electrode540comprises TiN.

Next, at step1040back-end-of-line (BEOL) processing is performed to complete the semiconductor process steps of the chip. The BEOL processes can be standard processes as known in the art, and the processes performed depend upon the configuration of the chip in which the memory cell is implemented. Generally, the structures formed by BEOL processes may include contacts, inter-layer dielectrics and various metal layers for interconnections on the chip including circuitry to couple the memory cell to periphery circuitry. These BEOL processes may include deposition of dielectric material at elevated temperatures, such as depositing SiN at 400 degrees C. or high density plasma HDP oxide deposition at temperatures of 500 degrees C. or greater. As a result of these processes, control circuits and biasing circuits as shown inFIG. 17are formed on the device.

Next, at step1050current is applied to the memory cells in the array to melt the active region, and allow cooling to form the dielectric mesh, such as by reset cycling (or set/reset cycling) on the memory cell500using the control circuits and bias circuits to melt and cool the active regions at least once, or enough times, to cause formation of the dielectric mesh. The number of cycles needed to form the active region510comprising phase change domains511within a dielectric-rich mesh512, may be for example 1 to 100 times. The resulting structure is illustrated inFIG. 11D. The cycling consists of applying appropriate voltage pulses to the first and second electrodes520,540to induce a current in the memory element sufficient to melt the material in the active region, and followed by an interval with no or small current allowing the active region to cool. The melting/cooling cycling can be implemented using the set/reset circuitry on the device, by applying one or more reset pulses sufficient to melt the active region, or a sequence of set and reset pulses. In addition, the control circuits and bias circuits may be implemented to execute a mesh forming mode, using voltage levels and pulse lengths that differ from the normal set/reset cycling used during device operation. In yet another alternative, the melting/cooling cycling may be executed using equipment in the manufacturing line that connects to the chips during manufacture, such as test equipment, to set voltage magnitudes and pulse heights.

FIGS. 12-14also illustrate memory cells comprising Ge2Sb2Te5material doped with 10 to 20 at % silicon oxide, having an active region comprising phase change domains within a dielectric-rich mesh. The materials described above with reference to the elements ofFIGS. 5A-5Bmay be implemented in the memory cells ofFIGS. 12-14, and thus a detailed description of these materials is not repeated.

FIG. 12illustrates a cross-sectional view of a second memory cell1200having an active region1210comprising phase change domains1211within a dielectric-rich mesh1212.

The memory cell1200includes a dielectric spacer1215separating first and second electrodes1220,1240. Memory element1216extends across the dielectric spacer1215to contact the first and second electrodes1220,1240, thereby defining an inter-electrode current path between the first and second electrodes1220,1240having a path length defined by the width1217of the dielectric spacer1215. In operation, as current passes between the first and second electrodes1220,1240and through the memory element1216, the active region1210heats up more quickly than the remainder1213of the memory element1216.

FIG. 13illustrates a cross-sectional view of a third memory cell1300having an active region1310comprising phase change domains1311within a dielectric-rich mesh1312.

The memory cell1300includes a pillar shaped memory element1316contacting first and second electrodes1320,1340at top and bottom surfaces1322,1324respectively. The memory element1316has a width1317substantially the same as that of the first and second electrodes1320,1340to define a multi-layer pillar surrounded by dielectric (not shown). As used herein, the term “substantially” is intended to accommodate manufacturing tolerances. In operation, as current passes between the first and second electrodes1320,1340and through the memory element1316, the active region1310heats up more quickly than the remainder1313of the memory element.

FIG. 14illustrates a cross-sectional view of a fourth memory cell1400having an active region1410comprising phase change domains1411within a dielectric-rich mesh1412.

The memory cell1400includes a pore-type memory element1416surrounded by dielectric (not shown) contacting first and second electrodes1420,1440at top and bottom surfaces respectively. The memory element has a width less than that of the first and second electrodes, and in operation as current passes between the first and second electrodes and through the memory element the active region heats up more quickly than the remainder of the memory element.

As will be understood, the present invention is not limited to the memory cell structures described herein and generally includes memory cells having an active region comprising phase change domains within a dielectric-rich mesh.

FIGS. 15A and 15Bare transmission electron microscope (TEM) images of a cross-section of a mushroom type memory cell comprising silicon oxide doped phase change material as described herein in the reset and set states respectively after cycling of 10 times. The memory cell ofFIGS. 15A-15Bwas formed as described above with reference toFIGS. 10-11, and thus comprises Ge2Sb2Te5material doped with 10 to 20 at % silicon oxide and has an active region comprising phase change domains within a dielectric-rich mesh. As can be seen inFIGS. 15A-15B, in both the reset and set state the phase change domains of the active region can be seen. In the photographs, the doped phase change material appears as a medium gray horizontal bar in the center having a top electrode of darker gray overlying the phase change material, and with bottom electrode pillars vaguely visible, extending through a black bar beneath the phase change material. Dome shaped active regions having radii just smaller than the thickness of the layer, are visible on close inspection with a different physical order than the body of material outside the active regions. The bodies of phase change material show very uniform boundaries, characteristic of small grain size polycrystalline structure.

FIGS. 16A-16Care additional TEM images of the memory cell ofFIGS. 15A-15Bin the reset state.FIG. 16Ais an expanded image of the active region (within rectangle) of the memory element showing the boundaries between the phase change domains. InFIG. 16A, domains within the dielectric mesh are seen.FIGS. 16B-16Care images of the electron energy loss spectroscopy (EELS) of Si and O respectively.FIGS. 16B and 16Cshow a clear correlation of the locations of Si and O and show the Si and O between the boundaries of the phase change domains that are visible inFIG. 16A. Also, the phase change domains appear to be empty of Si and O.

FIG. 17is a simplified block diagram of an integrated circuit1710including a memory array1712implemented using memory cells having an active region comprising phase change domains within a dielectric-rich mesh as described herein. A word line decoder1714having read, set and reset modes is coupled to and in electrical communication with a plurality of word lines1716arranged along rows in the memory array1712. A bit line (column) decoder1718is in electrical communication with a plurality of bit lines1720arranged along columns in the array1712for reading, setting, and resetting the phase change memory cells (not shown) in array1712. Addresses are supplied on bus1722to word line decoder and drivers1714and bit line decoder1718. Sense circuitry (Sense amplifiers) and data-in structures in block1724, including voltage and/or current sources for the read, set, and reset modes are coupled to bit line decoder1718via data bus1726. Data is supplied via a data-in line1728from input/output ports on integrated circuit1710, or from other data sources internal or external to integrated circuit1710, to data-in structures in block1724. Other circuitry1730may be included on integrated circuit1710, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array1712. Data is supplied via a data-out line1732from the sense amplifiers in block1724to input/output ports on integrated circuit1710, or to other data destinations internal or external to integrated circuit1710.

A controller1734implemented in this example, using a bias arrangement state machine, controls the application of bias circuitry voltage and current sources1736for the application of bias arrangements including read, program, erase, erase verify and program verify voltages and/or currents for the word lines and bit lines. In addition, bias arrangements for melting/cooling cycling may be implemented as mentioned above. Controller1734may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller1734comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller1734.

As shown inFIG. 18, each of the memory cells of array1712includes an access transistor (or other access device such as a diode) and memory element having an active region comprising phase change domains within a dielectric-rich mesh. InFIG. 18four memory cells1830,1832,1834,1836having respective memory elements1840,1842,1844,1846are illustrated, representing a small section of an array that can include millions of memory cells.

Sources of each of the access transistors of memory cells1830,1832,1834,1836are connected in common to source line1854that terminates in a source line termination circuit1855, such as a ground terminal. In another embodiment the source lines of the access devices are not electrically connected, but independently controllable. The source line termination circuit1855may include bias circuitry such as voltage sources and current sources, and decoding circuits for applying bias arrangements, other than ground, to the source line1854in some embodiments.

A plurality of word lines including word lines1856,1858extend in parallel along a first direction. Word lines1856,1858are in electrical communication with word line decoder1714. The gates of access transistors of memory cells1830and1834are connected to word line1856, and the gates of access transistors of memory cells1832and1836are connected in common to word line1858.

A plurality of bit lines including bit lines1860,1862extend in parallel in a second direction and are in electrical communication with bit line decoder1718. In the illustrated embodiment each of the memory elements are arranged between the drain of the corresponding access device and the corresponding bit line. Alternatively, the memory elements may be on the source side of the corresponding access device.

It will be understood that the memory array1712is not limited to the array configuration illustrated inFIG. 18, and additional array configurations can also be used. Additionally, instead of MOS transistors bipolar transistors or diodes may be used as access devices in some embodiments.

In operation each of the memory cells in the array1712store data depending upon the resistance of the corresponding memory element. The data value may be determined, for example, by comparison of current on a bit line for a selected memory cell to that of a suitable reference current by sense amplifiers of sense circuitry1724. The reference current can be established to that a predetermined range of currents correspond to a logical “0”, and a differing range of current correspond to a logical “1”.

Reading or writing to a memory cell of array1712, therefore, can be achieved by applying a suitable voltage to one of word lines1858,1856and coupling one of bit lines1860,1862to a voltage source so that current flows through the selected memory cell. For example, a current path1880through a selected memory cell (in this example memory cell1830and corresponding memory element1840) is established by applying voltages to the bit line1860, word line1856, and source line1854sufficient to turn on the access transistor of memory cell1830and induce current in path1880to flow from the bit line1860to the source line1854, or vice-versa. The level and duration of the voltages applied is dependent upon the operation performed, e.g. a reading operation or a writing operation.

In a reset (or erase) operation of the memory cell1830, word line decoder1714facilitates providing word line1856with a suitable voltage pulse to turn on the access transistor of the memory cell1830. Bit line decoder1718facilitates supplying a voltage pulse to bit line1860of suitable amplitude and duration to induce a current to flow though the memory element1840, the current raising the temperature of the active region of the memory element1840above the transition temperature of the phase change material and also above the melting temperature to place the phase change material of the active region in a liquid state. The current is then terminated, for example by terminating the voltage pulses on the bit line1860and on the word line1856, resulting in a relatively quick quenching time as the active region cools to a high resistance generally amorphous phase in the phase change domains of the active region to establish a high resistance reset state in the memory cell1830. The reset operation can also comprise more than one pulse, for example using a pair of pulses.

In a set (or program) operation of the selected memory cell1830, word line decoder1714facilitates providing word line1856with a suitable voltage pulse to turn on the access transistor of the memory cell1830. Bit line decoder1718facilitates supplying a voltage pulse to bit line1860of suitable amplitude and duration to induce a current to flow through the memory element1840, the current pulse sufficient to raise the temperature of the active region above the transition temperature and cause a transition in the phase change domains of the active region from the high resistance generally amorphous condition into a low resistance generally crystalline condition, this transition lowering the resistance of all of the memory element1840and setting the memory cell1530to the low resistance state.

In a read (or sense) operation of the data value stored in the memory cell1830, word line decoder1714facilitates providing word line1856with a suitable voltage pulse to turn on the access transistor of the memory cell1830. Bit line decoder1718facilitates supplying a voltage to bit line1860of suitable amplitude and duration to induce current to flow through the memory element1840that does not result in the memory element undergoing a change in resistive state. The current on the bit line1860and through the memory cell1830is dependent upon the resistance of, and therefore the data state associated with, the memory cell. Thus, the data state of the memory cell may be determined by detecting whether the resistance of the memory cell1830corresponds to the high resistance state or the low resistance state, for example by comparison of the current on bit line1860with a suitable reference current by sense amplifiers of sense circuitry1724.

The materials used in the embodiment described herein consist of silicon oxide and G2S2T5. Other chalcogenides may be used as well. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VIA of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IVA of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky U.S. Pat. No. 5,687,112, cols. 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4and GeSb4Te7(Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.