Chip scale package semiconductor device and method of manufacture

A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims foreign priority to Chinese Patent Application No. 2017113834698 filed on Dec. 20, 2017, the entirety of which is incorporated by reference hereby.

FIELD

The present disclosure relates to a semiconductor device and method of manufacture. In particular the present disclosure relates to a chip scale package semiconductor device and associated method of manufacture.

BACKGROUND

Chip scale package (CSPs) semiconductor devices are becoming increasingly important for applications which require a small footprint. CSPs are commonly used, for instance, in mobile communications devices such as mobile telephones and portable electronic devices. When a CSP incorporates a power semiconductor device, such as a transistor or diode, they require high performance thermal capacity and heat dissipation because they are required to drain large currents to ground or other rails, to protect devices connected thereto from being damaged. On the other hand, the power devices face challenges to increase structural compactness, which requires on the one hand, to have a very small footprint and package height, and, on the other hand to be protected by a package material. The package material is necessary to protect the device from environmental factors such as moisture. In addition the package material prevents solder pastes used to mount the device to a printed circuit board from contacting and potentially short circuiting the body of the semiconductor die. Such arrangements typically have mold material on six sides of the device and are known as six-sided protected CSP devices.

FIG.1is a cross-sectional view of a conventional six sided protected CSP device100. The semiconductor device100has a top major surface102and an opposing bottom major surface104. On the bottom major surface104, the CSP semiconductor device100includes multiple contacts106,108. The contacts106,108electrically connect to a bottom surface of a semiconductor die110to external circuit components, such as a printed circuit board (PCB) (not illustrated). The contacts106,108are formed on a surface of the semiconductor die110.

The semiconductor device100is packaged in a mold material116using any appropriate mold compound such as an epoxy based material. The mold material116is arranged to cover all six sides of the semiconductor die110, with the exception of the contacts106,108.

Compared to conventional CSP semiconductor devices without mold compound, conventional six sided protected CSP device suffer from the problem of how to dissipate heat generated in the semiconductor die during operation. This is of particular concern when the semiconductor die is a power device.

SUMMARY

According to an embodiment there is provided a chip scale package semiconductor device, comprising; a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.

The carrier may extend and be exposed through the molding material on opposing side walls of the device.

The first major surface of the carrier may be co-planar with the molding material on a top major surface of the device.

The opposing second major surface of the carrier may be arranged as a recess in the carrier. The recess may be arranged to mountably receive the semiconductor die. The recess may be arranged to receive an adhesive layer for mounting the semiconductor die to the carrier.

A top major surface of the package may comprise the carrier and a second opposing major surface of the package may comprise the terminals and the molding material.

According to an embodiment there is provided a method of manufacturing a chip scale package semiconductor device, the method comprising: providing a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; providing a carrier comprising a first major surface and an opposing second major surface; mounting the first major surface of the semiconductor die to the opposing second major surface of the carrier; partially encapsulating the semiconductor die and the carrier in a molding material, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.

The semiconductor die and the carrier may be encapsulated such that the first major surface of the carrier is co-planar with the molding material on a top major surface of the device.

The first major surface of the semiconductor die may be mounted in recess arranged on the opposing second major surface of the carrier.

The CSP semiconductor device according to the embodiments provides for improved heat dissipation and structural integrity, without increasing the height of the overall package. The CSP device according to embodiments is therefore suited to high power transistor devices.

DETAILED DESCRIPTION

FIG.2ais cross-sectional view of a six-sided Protected Chip Scale Package (CSP) semiconductor device200in accordance with an embodiment. The CSP semiconductor device200has a top major surface202and an opposing bottom major surface204. On the bottom major surface204, the CSP semiconductor device200includes multiple terminals or contacts206,208. The terminals206,208electrically connect to a bottom surface of a semiconductor die210of the CSP semiconductor device200to external circuit components, such as a printed circuit board (PCB), not illustrated. The contacts206,208are formed on a surface of the semiconductor die210.

The top major surface202of the CSP semiconductor device200includes a metal (or plastic) carrier212to support the semiconductor die210. The carrier212is fixedly mounted to a top surface of the semiconductor die210by any appropriate means, such as an epoxy based adhesive214.

WhilstFIG.2a, illustrates two contacts206,208formed on the bottom surface of the semiconductor die210, the skilled person will recognise that the any number of contacts may be provided dependent on the type and functionality of the semiconductor die210. For example, where the semiconductor die is a field effect transistor, the number of contacts may be three, with respective contacts connected to corresponding source, gate and drain terminals of the semiconductor die210. The semiconductor die210may alternatively be a bipolar junction transistor, thyristor or a two terminal diode. In addition a passivation layer217may be included on the surface of the semiconductor die210having the contacts206,208.

The CSP semiconductor device200is packaged in a mold material216using any appropriate mold compound such as an epoxy based material. The mold material may substantially cover the four minor sides of the CSP semiconductor device200. With the exception of the contacts206,208, the mold material216may also be formed to cover the bottom major surface of the device200. The mold material216may be arranged on the top major surface202of the device200so that a top surface of the carrier212is exposed.

The carrier212may also include one or more metal tabs218that extend from each side of the carrier212to protrude through the mold material216so as to be exposed at opposing sides of the CSP semiconductor device200. The tabs218are an artefact of the singulation process of the CSP semiconductor device200, which will be discussed in more detail below.

A side view of CSP semiconductor device200is illustrated inFIG.2b, which shows the tabs218, protruding through the mold material216on the side of the device200.FIG.2billustrates one side of the device200and the skilled person will appreciate that the corresponding opposing side will have the same arrangement of tabs218,220protruding through the mold material216, due to the matrix arrangement of the carrier as discussed below.

FIG.2cillustrates a bottom view of the CSP semiconductor device200and shows the contacts206,208and the mold material216arranged on the bottom surface204of the device200.FIG.2dillustrates a top view of the CSP semiconductor device200and shows the carrier212protrude through the mold material216such that the carrier is exposed on the top surface202of the device200. An optional chamfer222may be arranged on the carrier212, which may be used to indicate contact polarity and assist in device orientation when placing on PCB.

The arrangement of the carrier212to protrude through the top surface202of the device200and also through the opposing side walls provides improved thermal characteristics of the device200. The carrier, which acts as a heat sink is exposed, rather than covered by the mold material, and thus any heat generated in the die during operation of the device may be efficiently dissipated away from the semiconductor die210. This may be particularly advantageous where the device is a high power device.

Furthermore, and as discussed in more detail below with respect to the method of fabrication, the arrangement of the carrier212in the device200, when compared to conventional devices, is provided without increasing the overall package height of the device200.

Furthermore, the carrier212also provides mechanical strength to the device200by supporting the semiconductor die210. This is particularly advantageous where the device200is used in harsh environmental conditions such as in automotive applications.

FIG.3aillustrates a multi-die CSP semiconductor device300embodiment, whereby multiple semiconductor dies310a,310bare arranged in the CSP semiconductor device300. As with the previous embodiment, the dies will be fixed to a carrier312using, for example, an epoxy based adhesive. The mold material316is arranged to separate the multiple dies310a,310b.This arrangement may be advantageous, where the semiconductor dies310a,310bare arranged in, for example a cascode, or half-bridge configurations.

FIG.3billustrate an embodiments, whereby the carrier312includes as a recessed portion for accommodating the adhesive314and/or an upper portion of the semiconductor die310. In the embodiment ofFIG.3bthe recessed portion of the carrier312is sized to receive the semiconductor die310and the adhesive314arranged thereon. Alternatively, the recessed portion324of the carrier312may be sized to receive the adhesive314arranged on the semiconductor die310. The arrangement ofFIG.3bmay be advantageous in reducing the overall package height of the device300. In addition adhesive bleeds may be prevented by containing the adhesive314within the recess324of the carrier312. The skilled person will also understand that the embodiment ofFIG.3bis also amenable to multi-die arrangements such as the arrangement ofFIG.3a.

An example process flow for manufacturing the semiconductor device according to the above embodiments will now be described with reference toFIGS.4ato4hwhich illustrates example process steps.

With reference toFIG.4a, a metallic frame411is arranged on a carrier tape413. The carrier tape413prevents mold material from covering the carrier during the molding process and ensures that, as discussed above with reference toFIGS.2aand2dthat the carrier412is exposed and protrudes through the top surface402of the device400. The metallic frame comprises a repeating matrix of carriers412whereby neighbouring carriers are interconnected by connecting members418or tie bars. The matrix of carriers interconnected by the connecting members418may be a linear matrix. Alternatively, and as illustrated in the plan view ofFIG.4b, the matrix of carriers may be n×m matrix, where n is the number of rows in the matrix and m is the number of columns in the matrix, and where n and m are both positive integers, with adjacent carriers412connected by connecting members418. The example ofFIG.4billustrates one connecting member418connecting adjacent carriers in any row or column. However, consistent with the example ofFIG.2b, the skilled person will appreciate the number of connecting members418may be greater than one on any one side of the device.

As illustrated inFIG.4c, semiconductor dies410are then attached to respective carriers412using a die attach material414, such as an epoxy based adhesive as mentioned above, or any appropriate solder or glue. In certain applications the die attach material may be conductive to enable electrical connection from the carrier412to the semiconductor die410. It should be noted that the semiconductor dies410are attached top down to the carrier412. In other words the top major surface of the semiconductor die410, that is, the major surface opposing the surface having the contacts406,408is affixed to a respective carrier using the adhesive414. The adhesive may then be set or solidified by heat curing.

Following the semiconductor die410attach process discussed above, the arrangement of semiconductor dies attached to the carriers is then packaged.FIG.4dillustrates a packaging process known as film assisted molding (FAM), whereby a protective film417is applied over the matrix of attached or fixed dies. The matrix is then loaded into a molding machine whereby the liquefied molding material is forced into closed mold cavities formed by the protective film417and the carrier tape413. The molding material is then solidified by curing.

When the molded matrix is removed from the molding machine the protective film417is also removed. Following the molding process, the matrix may also undergo a process known as post mold curing to further cure and solidify the liquefied molding material.

Following molding and curing, the carrier tape is removed, by a process known as de-taping, from the molded matrix as illustrated inFIG.4e. When de-taping is completed, any excess mold material present on the contacts or on the exposed side of the carrier is removed, as illustrated inFIG.4fby a process known as deflashing. Once deflashing is completed the exposed side of the carrier may be marked with device details such as for example a product type, using for example a laser, as illustrated inFIG.4g.

As an alternative to the FAM process mentioned above, the molding may be achieved using an over-molding process as illustrated inFIGS.5aand5b. In the over-molding process, the mold material516is arranged to completely cover the semiconductor dies510, including the contacts arranged thereon. Following curing of the mold material516, the mold material is removed until the contacts are exposed using a grinding process.

Following marking, individual CSP semiconductor devices400are separated by singulation from the matrix arrangement. Singulation is carried out along the sidewall walls of the semiconductor devices400. The singulation process may be any appropriate cutting process, such as laser cutting, plasma cutting, saw cutting or any combination thereof, in order to separate the devices400. The step of singulation severs the connecting members418and the mold material416of adjacent devices400. This results in the tabs218as discussed above with respect toFIG.2aextending through mold material416at the side walls of the device400.

Following singulation, the devices may be electrically tested to ensure that they have not been damaged during the packaging process. Following testing the devices may be placed on a carrier tape and loaded on reel in preparation for shipping.

The CSP semiconductor device according to the embodiments provides for improved heat dissipation and structural integrity, without increasing the height of the overall package. The CSP device according to embodiments is therefore suited to high power transistor devices.

Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigate against any or all of the problems addressed by the present invention. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived there from. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

Term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.