Signal processor

A signal-processing unit according to the present invention comprises: an input line provided with a plurality of analog input signal lines; a multiplexer circuit transmitting the plurality of analog signals from this input line to one signal line in the subsequent stage in a desired sequence; an analog-digital conversion circuit that converts an analog signal into a digital signal and outputs it; and a cross talk compensation circuit that with respect to each of signals having been sequentially outputted from the analog-digital conversion circuit, a coefficient of an effect level between this signal and the other plural signals interfering with each other is calculated, and data obtained by multiplying the signals by these coefficients are added up.

TECHNICAL FIELD

The present invention relates to a signal-processing unit and, more particularly, to a signal-processing unit that is applied to, e.g., document reading devices and that converts a plurality of analog signals into digital signals to make a high-speed processing.

BACKGROUND ART

Recently, a document reading device for use in scanners, multifunction copying machines or the like, has become remarkably faster in reading speed per line. In a signal-processing unit to be applied to this document-reading device, it is necessary to divide one line into a plurality of blocks to make a parallel processing, as well as to process at higher speed each of the blocks having been divided. Moreover, a circuit for processing analog data read out individually in each of the plurality of blocks needs to operate at higher speed as a matter of course. On the other hand, conforming to document-reading devices being downsized, a signal-processing unit also tends to be downsized by, e.g., being formed into one chip.

Basically, each block in a signal-processing unit is connected through a switched capacitor of which ON/OFF is controlled at drive clock. Fetching data from each block, and transferring data to the subsequent block are processed by adjustment of a timing of drive clock so as to prevent interference between signals processed by each block.

In the conventional signal-processing unit, however, a problem exists in that a state in which outputs of adjacent signals are affected each other depending on timing of switching of each circuit block occurs when the signal-processing unit is driven at high speed by a high-speed clock, or that layout and wiring run of each circuit become hard as circuits are downsized, resulting in the interference of wiring with each other. Thus, the interference between signal data with each other, so-called cross talk, occurs between each of the circuits. Therefore, a further problem exists in that data after having been fetched in the signal-processing unit are changed or deteriorated as compared with data before being fetched in the signal-processing unit, and that correlation between data before signal processing and data after signal processing cannot be obtained. Furthermore, as document reading devices are downsized and operated at high speed, there arise situations in which wiring between plural lines of signals to be parallel-processed comes to be proximate, thus the cross talk between wirings may occur in early stage of the signal-processing unit.

As measures against these situations, to solve the problems as mentioned above, it has been attempted that the circuit layout in an internal part of a signal-processing unit, or switching timing between blocks are optimized; or wiring in the document reading device is designed to prevent the lines from being proximate to each other to a minimum. In actual, however, there remains the cross talk that is not eliminated even by those measures. For example, in the case of reading documents with the use of such a signal-processing unit for processing read data of the document reading device, the so-called “ghost phenomenon” in which a certain part of output data is seen in the other part like a thin shadow occurs, resulting in deterioration of picture quality.

The invention was made to solve the above-mentioned problems, and has an object of providing a signal-processing unit making it possible to effectively process the cross talk between signal data that occurs when a plurality of signal lines are processed in parallel.

DISCLOSURE OF INVENTION

A signal-processing unit according to the present invention comprises:

an input line that is provided with a plurality of analog input signal lines;

a multiplexer circuit that transmits a plurality of analog signals from the mentioned input line to one signal line in the subsequent stage in a desired sequence;

an analog-digital conversion circuit that converts an analog signal into a digital signal and outputs it; and

a cross talk compensation circuit that with respect to each of a plurality of signals having been synchronously inputted to a signal-processing unit out of signals having been sequentially outputted from the mentioned analog-digital conversion circuit, a coefficient of an effect level between each of a plurality of signals and the other plural signals interfering with each other is calculated, and data obtained by multiplying the signals by these coefficients are added up.

Another signal-processing unit according to the invention comprises:

an input line provided with a plurality of analog input signal lines;

a multiplexer circuit that transmits a plurality of analog signals from the mentioned input line into one signal line in the subsequent stage in a desired sequence;

an analog-digital conversion circuit that converts an analog signal into a digital signal and outputs it; and

a cross talk compensation circuit that with respect to one signal out of signals having been sequentially outputted from the mentioned analog-digital conversion circuit, a coefficient of an effect level between a plurality of signals before and after this signal and a plurality of signals interfering with each other is calculated, and data obtained by multiplying the signals by these coefficients are added up.

Further signal-processing unit according to the invention is provided with a communication processing circuit enabling to change cross talk elimination coefficients from outside of the device.

According to the invention, a signal-processing unit making it possible to suppress cross talk that occurs between wirings of signals of a document reading device, or cross talk that occurs in the analog signal processing section when a circuit for processing signals of the document reading device is constructed in one IC chip form such as ASIC to be downsized, can be provided easily as well as with high accuracy. In addition, a storage device for storing cross talk elimination coefficients has a communication function with outside of the device, whereby it comes to be possible to easily alter coefficients individually depending on a document reading device without necessity of adding or replacing any parts.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a first preferred embodiment according to the present invention is described referring toFIGS. 1 through 6.FIG. 1is a schematic diagram of an entire signal-processing unit according to the first embodiment. In the drawing, reference numeral1designates a document-reading device (for example, a contact image sensor) for use in scanners, multifunction copying machines and the like, and shows a state in which one line is divided into a plurality of blocks (six blocks1ato1fin the drawing). Numeral2shows a section of fetching analog input signals to be read out from each block, and the cross talk between signals as described above takes place in this section. Numeral3designates a multiplexer circuit that transmits the above-mentioned plural analog input signals to one signal line in a desired sequence. Numeral4designates an amplifier circuit that amplifies the above-mentioned multiplexed signals. Numeral5designates an analog-digital conversion circuit that converts analog signals having been amplified into digital signals. Numeral6designates a cross talk compensation circuit, being a subject of the invention. Numeral7designates a normal signal processing circuit that processes digital output signals of which cross talk has been compensated. In addition, numeral8designates a communication processing circuit enabling to externally control coefficients for controlling the above-mentioned cross talk compensation circuit6.

FIG. 2is a detailed circuit diagram of the above-mentioned cross talk compensation circuit6. In the drawing, numeral10designates a counter that counts the number of parallel signals of the above-mentioned data input. Numeral20designates a shift register circuit that consists of plural storage blocks21to27, and that sequentially transfers the above-mentioned data input Dinto the subsequent stage on a stage-by-stage basis conforming to a clock period. The block21stores a digital data input signal Dinto be input through the above-mentioned analog-digital conversion circuit5(FIG. 1). The block22stores a signal having been inputted to the foregoing cross talk compensation circuit6one clock before. The blocks23-28likewise store respective signals having been inputted to this cross talk compensation circuit6, 2-7 clocks before respectively. Numeral30designates a signal hold circuit consisting of 8 channels31to38that holds data until all signals are stored in the above-mentioned storage blocks21to28. Numeral40designates a multiplier that consists of eight channels41to48, and that multiplies data held in the above-mentioned signal hold circuits31to38by data obtained by the calculation of coefficients of signal interference levels between signals as described below. Numeral50designates an adder that adds up respective signals of each of the channels of the above-mentioned multiplier40to prepare a compensation data. Numeral51designates a circuit that prevents the overflow or underflow of the above-mentioned data based on the number of bits of data output. Doutshows a digital data output having been compensated. Numeral52designates a storage device that has preliminarily stored data obtained by the calculation of coefficients of signal interference levels between signals as described below. Numeral53designates a multiplexer circuit that makes the matching of data of the above-mentioned signal hold circuits31to38and coefficient data of the above-mentioned storage device52. Numeral54is a selection circuit that selects signals of which cross talk has to be compensated. The counter10outputs an active signal1, for example, when a count value comes to be x, and outputs 0 other than this time. Further, the counter10sends out a hold data of the signal hold circuit30every time an active signal1is outputted, and fetches the next value in the signal hold circuit30from the subsequent stage.

FIG. 3is an output signal waveform chart in which cross talk of a signal-processing unit according to the first embodiment has been compensated.FIG. 4is likewise an output signal waveform chart in which cross talk is not compensated.FIG. 5are output signal waveform charts showing states in which the above-mentioned cross talk is compensated with the use of the cross talk compensation circuit6ofFIG. 2. In the drawings, it is assumed that a plurality of analog input signals are a series of signals, and are transmitted in order of, for example, SIG1, SIG2, SIG3, SIG4; as well as a large input X (desired maximum value of digital data) is inputted to SIG2, and a small input Y is inputted to SIG1,3,4. Further, regions1to4correspond to respective blocks of the storage blocks22to28ofFIG. 2, and out of these blocks, input signals in adjacent2to4blocks are shown. For example, the region1may be replaced with the block25, the region2with the block24, the region3with the block23, and the region4with the block22. Now, the procedure of compensating an output waveform as shown inFIG. 4having been affected by cross talk is illustratively described with reference toFIG. 5. First, with reference toFIG. 5(a), when SIG2is fetched into the region1, a decreased amount of SIG1in the region2is compensated upward (indicated by an arrow). Moreover, as inFIG. 5(b), when SIG2is fetched into the region3, a decreased amount of SIG3in the region2is compensated downward (indicated by an arrow). Further, as shown inFIG. 5(c), when SIG2is fetched into the region4, a decreased amount of SIG4in the region2is compensated upward (indicated by an arrow). The above-mentioned compensation is made by multiplying data input signal Dinby plural types of coefficients, which are stored in the storage device52described referring toFIG. 2, at the multipliers41to48.

Now, the method of preparation and method of utilization of coefficients52by which data input signal Dinis multiplied at the multipliers41to48are described. First, in the document reading device1, a black document is placed on a reading surface in the state of a document illumination lamp being turned on, and data thereof is fetched in. A read region of a signal from the above-mentioned reading device1is divided into n parts, and this signal will be n lines of signals, which are inputted to the mentioned signal-processing unit. Next, the document illumination lamp is turned on, and data obtained by reading a white document only in a read region of the first block having been divided and by reading a black document in the other blocks, are fetched. Subsequently, data obtained by reading a white document only in a read region of the second block and by reading a black document in the other blocks, are fetched. The same operation is done in the third block, the fourth block, . . . , and the nth block. Out of data having been fetched, first in the data of the white document having been read in the first block, comparison is made between data of each of the blocks other than the first block and data having been fetched with black documents in all regions. Herein, an input signal of a white document is processed as a large input at the maximum value of output bit numbers of the analog-digital conversion circuit5, and an input signal of a black document is processed as a small input due to being a reference potential. A coefficient Cnxis obtained by the following expression.
CoefficientCnx={(black document data in thenthblock)−(data in the nthblock when a white document is read in thexthblock)}/(black document data in the nth block)  [Expression 1]
As to this coefficient, n×(n−1) numbers of operations are made in the case where a document read line is divided into n blocks, and these coefficients are stored in a coefficient table of the storage device52. These coefficients are stored in the storage device52, and assigned in the multipliers41to48through the multiplexer53based on the number of the counter10, whereby a document readout data Doutto be output from the signal-processing unit becomes a data that is not affected by cross talk.

FIG. 6is a timing chart schematically showing the flow of data processing of a signal-processing unit according to the invention. How to make the compensation actually using the coefficients obtained by the above-mentioned expression 1 is hereinafter described. A clock55is regularly inputted to a circuit according to the invention, and data Dinare inputted to a shift register circuit20in synchronization with the rise or fall of the clock. Data in the block21at a certain time point is shifted to the block22at the next clock. Data in the block22is shifted to the block23, data in the block23is shifted to the block24, and thereafter data are shifted likewise between the blocks in sequence.

Furthermore, a counter10counts up in synchronization with the above-mentioned clock as well. Subsequently, at a time point of a counter coming to be “x” (“6” in the drawing), data D0to D7in the blocks21to28are fetched into data holding blocks38to31respectively, and held therein. The data having been fetched in the above-mentioned signal hold circuit30are multiplied by coefficients that are stored in the storage device (memory)52conforming to values of the counter. For example, in the case where a counter value is 0, coefficients C12to C18obtained by the calculation of expression 1 are used; and letting data having been in the block31D0, data having been in the block32D1, . . . , and data having been in the block38D7, D0′, being a value of D0after the compensation of cross talk, is obtained by the following calculation.
D0′=D0×1+D1×C12+D2×C13+D3×C14+D4C15+D5×C16+D6×C17+D7×C18
In the case where a counter value is 1, D1′, being a value of D1after the compensation of cross talk, is obtained by the following calculation.
D1′=D0×C21+D1×1+D2×C23+D3×C24+D4×C25+D5×C26+D6×C27+D7×C28
Thereafter, every time clock is inputted, D2′, . . . , D7′ are obtained by the same calculation.

Thus, the first embodiment has such an advantage that each of a plurality of signals having been synchronously inputted to a signal-processing unit is multiplied by coefficients obtained by the calculation of effect levels between this signal and the other plural signals interfering with each other, thereby enabling to digitally solve cross talk, which occurs between the plurality of signals having been synchronously inputted to the signal-processing unit with reliability and high accuracy.

Additionally, with reference toFIG. 6, to compensate the cross talk between eight inputs, a counter is the one that counts 8, from 0 to 7, and digital data blocks are the one that prepares 8 blocks of blocks21to28. However, in case where an object of which cross talk is compensated is different, it is a matter of course that numbers counted with a counter, the number of digital data blocks and the like are varied based on the difference in object.

A second embodiment according to the invention is described referring toFIGS. 7 and 8.FIG. 7is a schematic diagram of a cross talk compensation circuit of a signal-processing unit according to the second embodiment.FIG. 8is a timing chart schematically showing the flow of data processing of the signal-processing unit according to the second embodiment. In the drawing, the same reference numerals indicate the same or like parts to those described in the first embodiment, and detailed description thereof is omitted.

In the above-mentioned cross talk compensation circuit according to the first embodiment, shown is an example in which each of a plurality of signals having been synchronously inputted to a signal-processing unit is multiplied by respective coefficients obtained by the calculation of effect levels between this signal and the other plural signals interfering with each other one-by-one. In a cross talk compensation circuit according to this second embodiment, shown is an example in which with respect to one signal out of signals having been sequentially outputted from the mentioned analog-digital conversion circuit, respective coefficients are obtained by the calculation of effect levels between signals before and after this signal and a plurality of signals interfering with each other.

In this example, it is assumed that the cross talk compensation is made with respect to data in a block25of a shift register20.

Every time circuit-driving clocks rise or fall, data are shifted in the circuit from21to22,23,24,25,26,27and28. As to data in the block25, the multiplication by a coefficient is not done, and the other seven data in the blocks21,22,23,24,26,27,28are multiplied by coefficient data to be outputted from a multiplexer circuit53using multipliers48,47,46,45,43,42,41respectively. These data are added up at an adder50, thereby data of which cross talk has been compensated being outputted as Dout. Coefficients are obtained by the same calculation as that in the first embodiment. Now, how to make the compensation actually using coefficients obtained with the expression 1 based on a timing chart ofFIG. 8is described. 55 clocks are regularly inputted to a circuit according to the invention, and data are inputted in synchronization with the rise or fall of the clocks. Data in the block21at a certain time point is transferred to the block22at the next clock. Data in the block22is shifted to the block23, data in the block23to the block24, data in the block24to the block25, data in the block25to the block26, data in the block26to the block27, and data in the block27to the block28. Furthermore, a counter10counts up in synchronization with the clocks as well. The data of which cross talk is to be compensated is data that is stored in the block25. Coefficients to be inputted to the multipliers41to48through a multiplexer53from a storage device52in which coefficient data are stored are varied as shown inFIG. 8based on counter values. Thus, with respect to data having been stored in the block25at a certain time point, the multiplication by coefficients C41to C43of the preceding 3 clocks and by coefficients C45to C48of the subsequent 4 clocks is made, thereby enabling to compensate the cross talk affected by signals having been inputted in respective blocks.

As a result, according to the second embodiment, there is such an advantage that with respect to one signal, respective coefficients are obtained by the calculation of effect levels between the signals before and after the one signal and a plurality of signals interfering with each other, thereby enabling to solve cross talk that occurs between a plurality of signals synchronously inputted to a signal-processing unit with a simple digital circuit.

A third embodiment according to the invention is described referring toFIG. 1. The third embodiment provides a signal-processing unit to which a communication processing circuit8that alters, from outside the storage device52, cross talk elimination coefficients stored in the storage device52according to the first embodiment or the second embodiment, is added. The use of this communication processing circuit8makes it possible to externally rewrite sequentially the coefficients of the storage device52.

The communication processing circuit8comprises a part that receives inputs from outside, a part that causes data having been received to be synchronous with clocks driving a cross talk compensation circuit6and a signal-processing circuit7, a part that converts data to those in format of the cross talk compensation circuit6capable of interpreting as needed, and a part that transmits inputs to a storage device52of the cross talk compensation circuit6(not shown in the drawing.) The above-mentioned part of receiving inputs may be a serial signal line consisting of four independent lines of an input signal line, an output signal line, a clock signal line, and a signal active/reactive indication signal line, or a parallel signal line that transmits input/output signals as parallel signal of an appropriate number of bits. In addition, a serial signal line is characterized in lower transmission speed, but a small number of lines; while a parallel signal line is characterized in a larger number of lines due to the increase of signal lines for input/output, but higher transmission speed. It is preferable to select an input receiving part based on applications from time to time.