METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, AND A CHIP ARRANGEMENT

A method for manufacturing a chip arrangement may include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip.

TECHNICAL FIELD

Various embodiments relate to a method for manufacturing a chip arrangement, and a chip arrangement.

BACKGROUND

Chip arrangements, for example chip packages, may include at least one chip (or die) embedded in a material (e.g. an encapsulant). Electrical and/or thermal and/or mechanical properties of a chip arrangement may depend on a process with which the chip arrangement is manufactured. Some manufacturing processes may adversely affect the electrical and/or thermal and/or mechanical properties of a chip arrangement and/or the at least one chip included in the chip arrangement. New ways of manufacturing chip arrangements may be needed.

DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practised. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Various embodiments are described for structures or devices, and various embodiments are described for methods. It may be understood that one or more (e.g. all) embodiments described in connection with structures or devices may be equally applicable to the methods, and vice versa.

The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer, may be formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer, may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.

In like manner, the word “cover”, used herein to describe a feature disposed over another, e.g. a layer “covering” a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed over, and in direct contact with, the implied side or surface. The word “cover”, used herein to describe a feature disposed over another, e.g. a layer “covering” a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed over, and in indirect contact with, the implied side or surface with one or more additional layers being arranged between the implied side or surface and the covering layer.

The terms “coupled” and/or “electrically coupled” and/or “connected” and/or “electrically connected”, used herein to describe a feature being connected to at least one other implied feature, are not meant to mean that the feature and the at least one other implied feature must be directly coupled or connected together; intervening features may be provided between the feature and at least one other implied feature.

Directional terminology, such as e.g. “upper”, “lower”, “top”, “bottom”, “left-hand”, “right-hand”, etc., may be used with reference to the orientation of figure(s) being described. Because components of the figure(s) may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that structural or logical changes may be made without departing from the scope of the invention.

Modem chip (or die) arrangements, e.g. chip (or die) packages, may include at least one chip (or die), which may be embedded in a material (e.g. an encapsulant).

FIG. 1AtoFIG. 1Gillustrate a conventional method for manufacturing a chip arrangement.

FIG. 1Ashows cross-sectional view100of a chip arrangement including a leadframe102and a chip104(or die). The chip104(or die) may include a front-side104aand a back-side104b. A metallization layer104cmay be formed at the back-side104bof the chip104and at least one contact104d(e.g. a bonding pad) may be formed at the front-side104aof the chip104. The chip104may be bonded to the leadframe102by means of a bonding process (indicated by arrows100a), which may be performed at a temperature in the range from about 200° C. to about 350° C.

As shown inFIG. 1Bin a view101, a surface of the leadframe102(e.g. copper leadframe) and/or the front-side104aof the chip104may be roughened (e.g. by means of a micro-etching process) in order to, for example, promote adhesion of subsequent layers that may be formed over the chip104and/or the leadframe102.

As shown inFIG. 1Cin a view103, the chip104may be inspected (e.g. optically inspected) to determine a relative spatial shift between adjacent chips104(or dies) bonded to the leadframe102. For example, the chip104on the left and the chip104on the right may be inspected (e.g. optically inspected) by an apparatus103a, and a relative position between the left chip104and the right chip104may be determined.

As shown inFIG. 1Din a view105, a layup105amay be formed over the chip104and the leadframe102. The layup105amay include a structured prepreg layer106, an insulating layer108(e.g. a resin and/or an uncured prepreg) and a conductive layer110. The structured prepreg layer106may be disposed over (e.g. disposed directly over) the leadframe102. The structured prepreg layer106may be configured to occupy a gap between adjacent chips104bonded to the leadframe102. For example, as shown inFIG. 1D, the structured prepreg layer106may occupy the gap between the chip104on the left and the chip104on the right. Additionally, the structured prepreg layer106may be configured to occupy a gap between a chip104and an edge of a leadframe102, as shown inFIG. 1D. The insulating layer108may be disposed over the structured prepreg layer106, and the conductive layer110may be disposed over the insulating layer108, as shown inFIG. 1D.

Heat and/or pressure (indicated by arrow105b) may be applied to the layup105aand the leadframe102to bond (e.g. by lamination) the structured prepreg106, the insulating layer (e.g. a resin)108and the conductive layer110to the leadframe102and the chip104. Bonding the layup105a(e.g. by lamination) may be performed over a plurality of leadframes102at one time. For example, in BLADE production, eight leadframes102may be laminated at one time, and each leadframe may be connected to another leadframe by means of a stencil that may be included in the layup105a.

As shown inFIG. 1Ein a view107, vias112may be formed in the conductive layer110(e.g. by means of an etching process).

As shown inFIG. 1Fin a view109, the vias112may be extended to expose a part of the leadframe102and/or a part of the chip104. For example, as shown inFIG. 1F, the vias112may be extended to expose at least one contact104c(e.g. a bonding pad) of the chip104. The vias112may be extended by means of a drilling process, for example a laser drilling process.

As shown inFIG. 1Gin a view111, the vias112may be filled with a conductive material114(e.g. copper or copper alloy or any other suitable metal or metal alloy such as e.g. tungsten). The conductive material114may subsequently be structured (e.g. patterned), for example by means of etching.

The conventional method for manufacturing a chip arrangement shown inFIG. 1AtoFIG. 1Gmay suffer from undesirable effects. For example, bonding the chip104to the leadframe102(e.g. a thick copper layer), for example as shown inFIG. 1A, may be performed at high temperatures (e.g. in the range from about 200° C. to about 350° C.).

High bonding temperatures may cause warpage of the leadframe102. Whilst it may be noted that a thicker leadframe102may reduce warpage caused by the high bonding temperatures, use of a thicker leadframe102may lead to a higher bill-of-materials (BOM).

High bonding temperatures may result in a coefficient-of-thermal-expansion (CTE) mismatch between the chip104and the leadframe102. Accordingly, the chip arrangement manufactured using the method shown inFIG. 1AtoFIG. 1Gmay suffer from high residual stress, which may affect the performance of the chip arrangement.

High bonding temperatures may also result in a high risk of failure caused by copper silicides that may be produced during the bonding process.

As described above in relation toFIG. 1D, heat and/or pressure (indicated by arrow105b) may be applied to the layup105aand the leadframe102to bond (e.g. by lamination) the structured prepreg106, the insulating layer (e.g. a resin)108and the conductive layer110to the leadframe102and the chip104. Bonding the layup105a(e.g. by lamination) may cause at least a part of the layup105a(e.g. the structured prepreg106and/or the insulating layer (e.g. a resin)108) to shrink. This may lead to warpage of the leadframe102.

The leadframe102, upon which the chip104is bonded to, may have a small size (e.g. about 165×68 mm2). As described above, a plurality of leadframes102may be connected to each other with stencil (e.g. additional PCB stencil) which may be included in the layup105a. This may lead to a complex layup structure, and a complex leadframe structure. The complex structure may result in poor aligning accuracy between the plurality of leadframes and may suffer from nonlinear dimension changes. For example, small changes in the dimension of a leadframe102and/or a chip104may lead to disproportionate changes in the dimensions of the stencil and/or layup105that may be formed over a plurality of leadframes102.

FIG. 1AtoFIG. 1Gillustrate one example of a conventional method for manufacturing a chip arrangement. In another example of a conventional method for manufacturing a chip arrangement, the chip104may be bonded to a foil (e.g. a copper foil) by means of a non-conductive adhesive and/or non-conductive paste. In such an example, the front-side104aof the chip104may face the leadframe102(which may include, or may be, a foil, e.g. copper foil). In other words, in such an example, a local non-conductive adhesive and/or non-conductive paste may be disposed between the front-side104aof the chip104and the leadframe102(e.g. foil, e.g. copper foil). Such a method for manufacturing a chip arrangement may suffer from a high risk of having voids in the non-conductive adhesive and/or non-conductive paste. These voids may consequently lead to yield loss during a patterning process that may be performed, e.g. patterning an electrical connection to and/or at the front-side104aof the chip104. Furthermore, the voids may result in delamination of the chip104from the leadframe102(e.g. foil) and/or HAST (Highly Accelerated Stress Test) problems (e.g. due to trapped plating chemistry). The voids may consequently lead to a loss of reliability of chip arrangements manufactured using such processes that may use a local non-conductive adhesive and/or non-conductive paste disposed between the front-side104aof the chip104and the leadframe102(e.g. foil, e.g. copper foil).

In another example of a conventional method for manufacturing a chip arrangement, an eWLB (embedded wafer level ball grid array) process may be used. In such an example, wafer level processes may be used to manufacture the chip arrangement. Furthermore, in an eWLB process, the chip104may be disposed (e.g. over a carrier) such that the front-side104aof the chip104may face a carrier during the manufacturing process. In other words, an eWLB process may not have the flexibility of placing the chip104in any other orientation (e.g. such that the back-side104bof the chip104may face the carrier).

In view of the above-mentioned features of the conventional method for manufacturing a chip arrangement, a method for manufacturing a chip arrangement is provided. One or more embodiments of the method for manufacturing the chip arrangement may have at least one of the following effects and/or aspects:

An aspect of one or more embodiments may be the use of simple PCB (printed circuit board) manufacturing processes and/or materials to manufacture a chip (or die) arrangement.

An aspect of one or more embodiments may be the use of a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.

An aspect of one or more embodiments may be replacement of at least a part of a layup (e.g. the layup105ashown inFIG. 1D) with a stabilizing structure that may not shrink during a lamination process.

An effect of one or more embodiments may be prevention or substantially reduction of warping in at least a part of a leadframe.

An effect of one or more embodiments may be prevention or substantial reduction of the formation of compounds (e.g. copper silicides) that may damage a chip.

An effect of one or more embodiments may be prevention or substantial reduction of CTE mismatch and/or high residual stress.

An effect of one or more embodiments may be manufacture of an interconnection (e.g. metallurgical interconnection) between a chip and a conductive layer in relatively low temperature.

An effect of one or more embodiments may be prevention or substantial reduction of warpage in a conductive layer and/or a chip.

An effect of one or more embodiments may be accurate alignment of a chip on a carrier, which may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.

The method200may, for example, be used to manufacture an embedded chip (or die) arrangement.

The method200for manufacturing the chip arrangement may include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier (in202); encapsulating the chip and the stabilizing structure by means of an encapsulating structure (in204); and forming an electrically conductive connection to the at least one contact of the chip (in206).

An effect provided by the method200may be prevention or substantially reduction of warping of at least a part of a leadframe.

An effect provided by the method200may be prevention or substantial reduction of the formation of compounds (e.g. copper silicides) that may damage a chip.

An effect provided by the method200may be prevention or substantial reduction of CTE mismatch and/or high residual stress.

An effect provided by the method200may be manufacture of an interconnection (e.g. metallurgical interconnection) between a chip and a conductive layer in relatively low temperature.

An effect provided by the method200may be prevention or substantial reduction of warpage in a conductive layer and/or a chip.

An effect provided by the method200may be accurate alignment of a chip on a carrier, which may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.

FIG. 3AtoFIG. 3Cshow that manufacturing a chip arrangement may include disposing a stabilizing structure304and a chip306next to each other and over a carrier302.

In the example shown inFIG. 3AtoFIG. 3C, the stabilizing structure304may be disposed over the carrier302(e.g. as shown inFIG. 3B), and the chip306may subsequently be disposed next to the stabilizing structure304and over the carrier302(e.g. as shown inFIG. 3C). In other words, the stabilizing structure304may be disposed over the carrier302prior to the chip306(e.g. as shown inFIG. 3BandFIG. 3C).

However, in another example, the chip306may be disposed over the carrier302, and the stabilizing structure304may subsequently be disposed next to the chip306and over the carrier302. In other words, in another example, the chip306may be disposed over the carrier302prior to the stabilizing structure304(e.g. see description below in respect ofFIG. 7BandFIG. 7C).

The carrier302may include, or may consist of, a plate302aand an adhesive layer302b. As shown inFIG. 3A, the adhesive layer302bmay be disposed over (e.g. disposed on) the plate302a. The adhesive layer302bof the carrier302may, for example, be formed over the plate302aof the carrier302by means of a lamination process (e.g. vacuum lamination process) and/or a deposition process, although other processes may be possible as well.

The carrier302(e.g. the plate302aof the carrier302) may include, or may be, a panel. The carrier302(e.g. the plate302aof the carrier302) may include, or may be, a foil (e.g. a conductive foil), e.g. that may be available commercially (e.g. a foil available from Metfoils AB).

The carrier302(e.g. the plate302aof the carrier302) may include, or may be, a panel measuring about 300×400 mm2that may be commonly used as a PCB (printed circuit board) material. By way of another example, the carrier302(e.g. the plate302aof the carrier302) may include, or may be, a panel that may have a large panel size (e.g. a panel measuring about 300×400 mm2or larger, for example about 500×600 mm2or larger, although other values may be possible as well).

Since the carrier302(e.g. the plate302aof the carrier302) may be a large panel (e.g. measuring about 300×400 mm2), the contraction and/or expansion of the carrier302may be more predictable over a whole panel area, as compared to, e.g., the leadframe102shown inFIG. 1AtoFIG. 1G, which may be of a smaller size, e.g. 165×68 mm2.

The carrier302(e.g. the plate302aof the carrier302) may include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: aluminium, iron, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the carrier302(e.g. the plate302aof the carrier302) may include, or may consist of, an alloy including, or consisting of, iron and at least one other element (e.g. carbon). For example, the carrier302(e.g. the plate302aof the carrier302) may include, or may consist of, steel.

The carrier302(e.g. the adhesive layer302bof the carrier302) may include, or may consist of, a non-conductive material. The carrier302(e.g. the adhesive layer302bof the carrier302) may include, or may consist of, a release tape (e.g. a thermal release tape, e.g. a temporary thermal release tape).

The carrier302(e.g. the adhesive layer302bof the carrier302) may include, or may consist of, a double-sided sticky tape with thermo-release properties (namely, elements and/or components may be separated and/or released from the double-sided sticky tape by means of heating and/or curing the double-sided sticky tape).

The carrier302may include at least one alignment mark302AL, which may be configured to align a structure and/or a component and/or a layer, which may be subsequently formed and/or disposed over the carrier302.

The stabilizing structure304may be disposed over the carrier302by means of a lamination process (e.g. vacuum lamination process), although other processes may be possible as well. For example, the stabilizing structure304may be laminated to the adhesive layer302bof the carrier302.

The stabilizing structure304may include at least one alignment mark304AL, which may be configured to align the stabilizing structure304to the carrier302. For example, the at least one alignment mark304AL of the stabilizing structure304may be aligned to the at least one alignment mark302AL of the carrier302, thus aligning the stabilizing structure304to the carrier302. In other words, disposing the stabilizing structure304over the carrier may include aligning the stabilizing structure304to the carrier302, e.g. by means of the at least one alignment mark304AL of the stabilizing structure304and the at least one alignment mark302AL of the carrier302.

The stabilizing structure304may include a thru-opening304O (e.g. one or more thru-openings), which may be formed by means of at least one of a punching process, a routing process, a drilling process, an etching process (e.g. a wet and/or dry etch process), and a laser structuring process, although other processes may be possible as well. The thru-opening304O may be formed prior to disposing the stabilizing structure304over the carrier302.

The stabilizing structure304may include a substrate layer304A and a bonding layer304BL disposed over the substrate layer304A. The bonding layer304BL may be formed over the substrate layer304A by means of a lamination process (e.g. vacuum lamination process), although other processes may be possible as well. The bonding layer304BL may be formed over the substrate layer304A prior to disposing the stabilizing structure304over the carrier302.

The bonding layer304BL of the stabilizing structure304may be configured to attach the substrate layer304A of the stabilizing structure304to the carrier302. In this regard, disposing the stabilizing structure304over the carrier302may include attaching the substrate layer304A of the stabilizing structure304to the carrier302(e.g. the adhesive layer302bof the carrier302) by means of the bonding layer304BL of the stabilizing structure304, as shown inFIG. 3B. For example, the bonding layer304BL of the stabilizing structure304may be disposed between the substrate layer304A of the stabilizing structure304and the carrier302(e.g. the adhesive layer302bof the carrier302), as shown inFIG. 3B.

The bonding layer304BL may include, or may be, a resin film (e.g. a B-stage resin film). By way of another example, the bonding layer304BL may include, or may consist of, a material that may be used for laminating PCB layers together, although other materials may be possible as well.

FIG. 4AandFIG. 4Bshow an example of a method for forming the bonding layer304BL and the thru-opening304O of the stabilizing structure304prior to disposing the stabilizing structure304over the carrier302.

As shown inFIG. 4Ain a view400, the bonding layer304BL may be disposed over the substrate layer304A. As described above, the bonding layer304BL may be formed over the substrate layer304A by means of a lamination process.

A thickness T1 of the bonding layer304BL may depend on a material of the bonding layer304BL. The thickness T1 of the bonding layer304BL may be in the range from about 5 μm to about 150 μm, e.g. in the range from about 10 μm to about 100 μm, e.g. in the range from about 20 μm to about 90 μm, e.g. in the range from about 20 μm to about 60 μm, e.g. in the range from about 20 μm to about 40 μm, e.g. about 30 μm.

As shown inFIG. 4Bin a view401, the thru-opening304O (e.g. at least one thru-opening) may be formed (e.g. through the substrate layer304A and the bonding layer304BL) subsequent to forming the bonding layer304BL over the substrate layer304A. As described above, the thru-opening304O may be formed by means of at least one of a punching process, a routing process, a drilling process, an etching process (e.g. a wet and/or dry etch process), and a laser structuring process, although other processes may be possible as well.

The thickness T1 of the bonding layer304BL may be determined such that there may be at least enough material of the bonding layer304BL that may fill an opening (e.g. a cavity) of the carrier302, in case the carrier302includes an opening (e.g. cavity). This is illustrated by way of an example inFIG. 5AandFIG. 5B.

FIG. 5AandFIG. 5Bshow the carrier302including at least one opening302O, which may be filled with material of the bonding layer304BL of the stabilizing structure304.

As shown inFIG. 5Ain a view500, the carrier302(e.g. the plate302aof the carrier302) may include at least one opening302O.FIG. 5Amay, for example, be a magnified view of a portion of the carrier302shown inFIG. 3A.

As shown inFIG. 5Bin a view501, the at least one opening302O of the carrier302may be filled with the bonding layer304BL of the stabilizing structure304.FIG. 5Bmay, for example, be a magnified view of a portion of the carrier302and the bonding layer304BL of the stabilizing structure304shown inFIG. 3B.

As shown inFIG. 5B, a first portion304BL-1of the bonding layer304BL may fill the at least one opening302O of the carrier302, and a second portion304BL-2of the bonding layer304BL may be disposed over at least a part of a surface of the carrier302outside the at least one opening302O. Accordingly, the thickness T1 of the bonding layer304BL may be determined such that there may be enough material to fill the at least one opening302O of the carrier and to line (e.g. coat) the part of the surface of the carrier302outside the at least one opening302O, as shown inFIG. 5B.

Accordingly, by determining the thickness T1 of the bonding layer304BL, the at least one opening302O of the carrier302may be filled with material of the bonding layer304BL, without having to depend on material of a subsequent layer and/or structure (e.g. an encapsulating structure) to fill the at least one opening302O of the carrier302. Consequently, material of a subsequent layer and/or structure (e.g. encapsulating structure) may only need to fill at least a part of the thru-opening304O of the stabilizing structure304, without having to fill the at least one opening302O of the carrier302.

In relation toFIG. 3B, disposing the stabilizing structure304over the carrier302may include disposing the stabilizing structure over the at least one opening302O of the carrier302, wherein the first portion304BL-1of the bonding layer304BL may fill the at least one opening302O of the carrier302, and wherein the a second portion304BL-2of the bonding layer304BL may be disposed over at least a part of the surface of the carrier302outside the at least one opening302O.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may be configured to prevent or substantially reduce warpage in a chip arrangement manufactured by means of the method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may be configured to prevent or substantially reduce CTE mismatch and/or high residual stress in a chip arrangement manufactured by means of the method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may be configured to prevent or substantially reduce shrinkage in a chip arrangement manufactured by means of the method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of the method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of the method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may be configured to cool a chip that may be included in a chip arrangement manufactured by means of the method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, a laminate material (e.g. a cured laminate material). For example, the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, a PCB laminate material (e.g. a cured PCB laminate material). By way of another example, the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, an FR4 laminate material (e.g. a cured FR4 laminate material).

The stabilizing structure304including, or consisting of, the laminate material may, for example, be configured to prevent or substantially reduce warpage and/or CTE mismatch and/or high residual stress and/or shrinkage in a chip arrangement manufactured by means of the method200. The stabilizing structure304including, or consisting of, the laminate material may, for example, be configured to improve (e.g. optimize) mechanical properties of a chip arrangement manufactured by means of the method200.

The stabilizing structure304may include at least one chip (or die) that may, for example, be embedded in the substrate layer304A of the stabilizing structure304. The at least one chip (or die) may, for example, be configured to operate in conjunction with a chip, which may be included in the stabilizing structure304(e.g. embedded in the substrate layer304A of the stabilizing structure) and/or which may be external to the stabilizing structure304. The stabilizing structure304including the at least one chip (or die) may, for example, be configured to improve (e.g. optimize) electrical properties of a chip arrangement manufactured by means of the method200.

The stabilizing structure304may include at least one via (e.g. a through-via, e.g. a matrix of through-vias) that may, for example, be embedded in the substrate layer304A of the stabilizing structure304. The stabilizing structure304including the at least one via (e.g. a matrix of through-vias) may, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include at least one electrically conductive layer (e.g. a copper layer), which may be suitable for routing and/or redistribution of electrical signals.

In an example where the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include one electrically conductive layer, the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may be, a single layer RDL (redistribution layer).

In another example where the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include a plurality of electrically conductive layers, the stabilizing structure304may include, or may be, a multi-layer RDL. In such an example, the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include at least one via extending through at least a portion of the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304). The at least one via may, for example, electrically connect a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers. In other words, at least two electrically conductive layers of the plurality of electrically conductive layers may be electrically connected to each other.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, a polymer material (e.g. a polyimide material). The stabilizing structure304including, or consisting of, the polymer material may, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of the method200. The stabilizing structure304including, or consisting of, the polymer material may, for example, be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, copper. The stabilizing structure304including, or consisting of, the metal or metal alloy may be configured to cool a chip that may be included in a chip arrangement manufactured by means of method200. The stabilizing structure304including, or consisting of, the metal or metal alloy may, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of method200.

The stabilizing structure304(e.g. the substrate layer304A of the stabilizing structure304) may include, or may consist of, a ceramic material. The stabilizing structure304including, or consisting of, the ceramic material may, for example, be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of method200. The stabilizing structure304including, or consisting of, the ceramic material may, for example, be configured to seal a chip that may be included in a chip arrangement manufactured by means of method200. The stabilizing structure304including, or consisting of, the ceramic material may, for example, be configured to optimize mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of method200.

FIG. 3Cshows a cross-sectional view303of a chip306disposed next to the stabilizing structure304and over the carrier302.

Only two chips306are shown as an example, however the number of chips may be less than two (e.g. one) or greater than two, and may, for example, be three, four, five, six, seven, eight, nine, or on the order of tens, or even more chips.

The chip306may, for example, be a chip used for MEMS and/or logic and/or memory and/or power applications, although chips used for other applications may be possible as well.

As shown inFIG. 3C, chip306may include a first side306aand a second side306bopposite the first side306a. The first side306aand the second side306bof the chip306may include, or may be, a frontside and a backside of the chip306, respectively. By way of another example, the first side306aof the chip306may include, or may be, an active side of the chip306.

The chip306may include at least one contact306c. The at least one contact306cof the chip306may, for example, provide an interface (e.g. an electrical and/or thermal interface) for the chip306. For example, signals (e.g. electrical signals, power supply potentials, ground potentials, etc.) may be exchanged with the chip306via the at least one contact306c. By way of another example, heat may be conducted away from the chip306by means of the at least one contact306c.

The at least one contact306cof the chip306may, for example, be disposed at the first side306a(e.g. active side), the second side306b(e.g. backside), or both. For example, the at least one contact306cmay include, or may be, a metallization layer which may, for example, be disposed over the second side306b(backside) of the chip306. In the example shown in FIG.3C, the at least one contact306cmay be disposed at the first side306a(e.g. active side) and the second side306b(e.g. backside) of the chip306(the at least one contact306cdisposed at the second side306bis not shown inFIG. 3C). In another example, the at least one contact306cmay be disposed at one of the first side306aand the second side306bof the chip306

In the example shown inFIG. 3C, the first side306a(e.g. active side) of the chip306may face the carrier302and/or may be in contact (e.g. physical contact) with the carrier302. Such an arrangement of the chip306may, for example, be referred to as a face-down arrangement of the chip306.

In another example, the second side306b(e.g. backside) of the chip306may face the carrier302and/or may be in contact (e.g. physical contact) with the carrier302(e.g. see description below in respect ofFIG. 6C). In this example, such an arrangement of the chip306may be referred to as a face-up arrangement of the chip306.

As shown inFIG. 3C, the chip306may be disposed over the adhesive layer302bof the carrier302. Accordingly, disposing the stabilizing structure304and the chip306next to each other and over the carrier302may include disposing the stabilizing structure304and the chip306next to each other and over the adhesive layer302bof the carrier302.

As described above, the stabilizing structure304may include the at least one alignment mark304AL and the carrier302may include the at least one alignment mark302AL. In this regard, disposing the chip306and the stabilizing structure304next to each other and over the carrier302may include aligning the chip306to the stabilizing structure304by means of the at least one alignment mark304AL and/or the at least one alignment mark302AL, and disposing the chip306next to the stabilizing structure304and over the carrier302. In other words, the chip306may be aligned (e.g. accurately aligned) by means of the at least one alignment mark304AL of the stabilizing structure304and/or the at least one alignment mark302AL of the carrier302.

In the example shown inFIG. 3C, each of the one or more chips306may be mounted on a large carrier302(e.g. 300×400 mm2) and aligned using same aligning marks (e.g. of the stabilizing structure304and/or the carrier302). Accordingly, the aligning accuracy may be good all over an entire area of the carrier302(e.g. the whole panel area).

As described above,FIG. 3AtoFIG. 3Cshow an example in which the stabilizing structure304may be disposed over the carrier302(e.g. as shown inFIG. 3B), and the chip306may subsequently be disposed next to the stabilizing structure304and over the carrier302(e.g. as shown inFIG. 3C). However, in another example, the chip306may be disposed over the carrier302, and the stabilizing structure304may subsequently be disposed next to the chip306and over the carrier302. In such an example, the chip306may be aligned to the carrier302by means of the at least one alignment mark302AL of the carrier302. The stabilizing structure304may subsequently be aligned to the chip306and/or the carrier302by means of the at least one alignment mark302AL of the carrier302and/or the at least one alignment mark304AL of the stabilizing structure304.

As described above, the stabilizing structure304may include the thru-opening304O. In this regard, disposing the chip306and the stabilizing structure304next to each other and over the carrier302may include disposing the chip306within the thru-opening304O of the stabilizing structure304and over the carrier302, as shown inFIG. 3C.

The examples shown inFIG. 3AtoFIG. 3Cmay, for example, be identified with “disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier” disclosed in202of method200.

The examples shown inFIG. 3DandFIG. 3Emay, for example, be identified with “encapsulating the chip and the stabilizing structure by means of an encapsulating structure” disclosed in204of method200.

As shown inFIG. 3Din a view305, encapsulating the chip306and the stabilizing structure304may include laying-up the encapsulating structure308over the chip306, the stabilizing structure304, and the carrier302.

The encapsulating structure308may include an insulating layer308a. The encapsulating structure308shown inFIG. 3Dmay additionally include a conductive layer308b. However, in another example, the encapsulating structure308may include the insulating layer308aonly. As illustrated in the example shown inFIG. 3D, the insulating layer308amay be disposed between the chip306and the conductive layer308b.

The encapsulating structure308(e.g. the insulating layer308aof the encapsulating structure308) may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material (e.g. an uncured laminate material), although other materials may be possible as well.

The encapsulating structure308(e.g. the conductive layer308bof the encapsulating structure308) may include, or may consist of, an electrically conductive material and/or a thermally conductive material. For example, the encapsulating structure308(e.g. the conductive layer308bof the encapsulating structure308) may include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the encapsulating structure308(e.g. the conductive layer308bof the encapsulating structure308) may include, or may consist of, copper or a copper alloy.

As described above in relation to the chip306shown inFIG. 3C, the at least one contact306cmay be disposed at the first side306a(e.g. active side) and/or the second side306b(e.g. backside) of the chip306. The conductive layer308bof the encapsulating structure308may be suitable for forming a subsequent electrical and/or thermal connection with the stabilizing structure304and/or the chip306. For example, the conductive layer308bof the encapsulating structure308may be at least a part of an electrical and/or thermal connection to the at least one contact306cdisposed at the second side306bof the chip306.

As shown inFIG. 3Ein a view307, encapsulating the chip306and the stabilizing structure304by means of the encapsulating structure308may include applying heat and pressure (indicated by arrows310) to fuse the encapsulating structure308, the chip306, and the stabilizing structure304together. Applying heat and pressure (indicated by arrows310) may include, or may be, a lamination process. In other words, encapsulating the chip306and the stabilizing structure304by means of the encapsulating structure308may include, or may consist of, a lamination process.

The applied heat and/or pressure (indicated by arrows310) may soften (e.g. melt) the encapsulating structure308(e.g. the insulating layer308aof the encapsulating structure308) such that the encapsulating structure308(e.g. the insulating layer308aof the encapsulating structure308) flows into and fills the thru-opening304O of the stabilizing structure304. At least a portion of the encapsulating structure308(e.g. at least a portion of the insulating layer308aand/or the conductive layer308bof the encapsulating structure308) may be additionally disposed over the chip306and the stabilizing structure304after the application of heat and/or pressure, as shown inFIG. 3E.

FIG. 3FtoFIG. 3Kshow cross-sectional views illustrating the forming of at least one electrically conductive connection to the at least one contact306cof the chip306.

The examples shown inFIG. 3FtoFIG. 3Kmay, for example, be identified with “forming an electrically conductive connection to the at least one contact of the chip” disclosed in206of method200.

As shown inFIG. 3Fin a view309, forming the at least one electrically conductive connection to the at least one contact306cof the chip306may include removing the carrier302e.g. to expose the at least one contact306cof the chip306. For example, the at least one contact306cof the chip306may be visible and/or exposed with the removal of the carrier302. In the example shown inFIG. 3F, the at least one contact306cdisposed at the first side306a(e.g. active side) of the chip306may be visible and/or exposed by the removal of the carrier302. In the example shown inFIG. 3F, the bonding layer304BL may be removed with the carrier302(e.g. by means of at least one of dissolving, peeling off, and curing).

As described above, the carrier302may include the plate302aand the adhesive layer302b. Accordingly, removing the carrier302may include removing the plate302aand the adhesive layer302bof the carrier302, e.g. to expose the at least one contact306cof the chip306. Removing the adhesive layer302bof the carrier302may include at least one of dissolving the adhesive layer302b(e.g. by means of a solvent), peeling off the adhesive layer302b, and curing the adhesive layer302b. For example, as described above, the carrier302(e.g. the adhesive layer302bof the carrier302) may include, or may consist of, a double-sided sticky tape with thermo-release properties (namely, elements may be separated and/or released from the double-sided sticky tape by means of heating and/or curing the double-sided sticky tape). In such an example, the adhesive layer302bmay be cured, thus separating the chip306and the stabilizing structure304from the carrier302. The stabilizing structure304and the chip306may be held in place by means of the encapsulating structure308(e.g. the insulating layer308aof the encapsulating structure308).

As shown inFIG. 3Gin a view311, forming the electrically conductive connection to the at least one contact306cof the chip306may include disposing a second conductive layer312bover the at least one contact306cof the chip306(e.g. the at least one exposed contact306cof the chip306). In the example shown inFIG. 3G, the second conductive layer312bmay be disposed over the at least one contact306cdisposed at the first side306aof the chip306, which may be exposed and/or visible (e.g. due to the removal of the carrier302). Since the stabilizing structure304is disposed next to the chip306, the second conductive layer312bmay be disposed over the stabilizing structure304as well.

The second conductive layer312bmay include, or may consist of, an electrically conductive material and/or a thermally conductive material. For example, the second conductive layer312bmay include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the second conductive layer312bmay include, or may consist of, copper or a copper alloy.

As shown inFIG. 3G, disposing the second conductive layer312bover the at least one contact306cof the chip306may include disposing a second insulating layer312abetween the second conductive layer312band the at least one contact306cof the chip306(e.g. the exposed contact of the chip, e.g. the at least one contact306cdisposed at the first side306aof the chip306).

The second insulating layer312amay include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material (e.g. an uncured laminate material), although other materials may be possible as well.

As described above in relation to the chip306shown inFIG. 3C, the at least one contact306cmay be disposed at the first side306a(e.g. active side) and/or the second side306b(e.g. backside) of the chip306. In the example shown inFIG. 3C, the second conductive layer312bmay be suitable for forming the electrically conductive connection with the stabilizing structure304and/or the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306).

As shown inFIG. 3Hin a view313, disposing the second conductive layer312bover the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306) may include applying heat and pressure (indicated by arrows314) to fuse the second conductive layer312b, the second insulating layer312a, the encapsulating structure308, the chip306, and the stabilizing structure304together. Applying heat and pressure (indicated by arrows314) may include, or may be, a lamination process. In other words, disposing the second conductive layer312bover the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306) may include, or may consist of, a lamination process.

A distance D between the at least one contact306cof the chip306(e.g. the at least one exposed contact306cof the chip306c) and the second conducting layer312bmay be at least substantially equal over a lateral extent of the chip arrangement shown inFIG. 3H. The distance D may be easily controlled by controlling a thickness of the second insulating layer312a.

As described above, an electrically conductive connection may be formed with the at least one contact306cof the chip306. As described above, the at least one contact306cof the chip306shown inFIG. 3CtoFIG. 3Kmay be disposed at the first side306aand the second side306bof the chip306. Accordingly, the electrically conductive connection may be formed with the first side306aand the second side306bof the chip306. In another example, the electrically conductive connection may be formed to the first side306aor the second side306bof the chip306, depending on where the at least one contact306cof the chip306may be disposed.

As shown inFIG. 3Iin a view315andFIG. 3Jin a view317, forming the electrically conductive connection to the at least one contact306cof the chip306may include forming at least one opening316in the encapsulating structure308to expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the second side306bof the chip306). For example, the at least one opening316may be formed in the conductive layer308bof the encapsulating structure308, as shown inFIG. 3I. The at least one opening316may be formed in the encapsulating structure308by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process).

The at least one opening316may be subsequently deepened (e.g. extended through the insulating layer308aof the encapsulating structure308) to expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the second side306bof the chip306), as shown inFIG. 3J. The at least one opening316may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process).

As shown inFIG. 3Iin a view315andFIG. 3Jin a view317, forming the electrically conductive connection to the at least one contact306cof the chip306may include forming at least one opening318in the second conductive layer312band the second insulating layer312ato expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306). For example, the at least one opening318may be formed in the second conductive layer312b, as shown inFIG. 3I. The at least one opening318may be formed in the second conductive layer312bby means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process).

The at least one opening318may be subsequently deepened (e.g. extended through the second insulating layer312a) to expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306), as shown inFIG. 3J. The at least one opening318may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process).

In the examples shown inFIG. 3IandFIG. 3J, at least one opening323may be formed to expose at least a part of the stabilizing structure304. The at least one opening323may be formed and/or deepened by means of similar processes used in relation to the at least one opening316and the at least one opening318. In another example, however, there may not be an opening that may expose at least a part of the stabilizing structure304.

Forming the at least one opening316and/or318and/or323(e.g. by means of an etching process and/or micro-via cleaning and/or drilling process) may include using the at least one alignment mark304AL of the stabilizing structure, which may improve accuracy and/or precision of the etching process and/or micro-via cleaning and/or drilling process.

As shown inFIG. 3Kin a view319, forming the electrically conductive connection to the at least one contact306cof the chip306may include a plating process (indicated by arrows320). In one or more examples, a seed metal or seed metal alloy (e.g. seed copper) may be sputtered prior to or as part of the plating process (indicated by arrows320). The plating process (indicated by arrows320) may, for example, fill the at least one opening316,318and/or323with an electrically conductive material.

In the example shown inFIG. 3K, the electrically conductive connection between the second conductive layer312band the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306) may be formed by means of the plating process (indicated by arrows320). By way of another example, the electrically conductive connection between the conductive layer308bof the encapsulating structure308and the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the second side306bof the chip306) may be formed by means of the plating process (indicated by arrows320).

In the example shown inFIG. 3K, an electrically conductive connection may also be formed between the conductive layer308bof the encapsulating structure308and the stabilizing structure304by means of the plating process (indicated by arrows320).

The plating process (indicated by arrows320) for forming the electrically conductive connection to the at least one contact306cof the chip306may include an electroless plating process or an electrochemical plating process or a direct metallization process.

Forming the electrically conductive connection to the at least one contact306cof the chip306may include patterning the conductive layer308aof the encapsulating structure308and/or the second conductive layer312b, e.g. subsequent to the plating process shown inFIG. 3K. Patterning the conductive layer308aof the encapsulating structure308and/or the second conductive layer312bmay include, or may consist of, an etching process (e.g. a dry and/or wet etch process). The patterning process may, for example, make use of at least one alignment mark, which may improve accuracy and/or precision of the patterning process. The at least one alignment mark may, for example, be disposed at the conductive layer308band/or the second conductive layer312b. This alignment mark may, for example, be formed by means of reproducing the at least one alignment mark304AL of the stabilizing structure304and/or the at least one alignment mark302AL of the carrier302, e.g. prior to the removal of the carrier302.

As described above, the patterning process may be performed subsequent to the plating process shown inFIG. 3K. However, in another example, the at least one opening316and/or318and/or323may be filled with electrically conductive material by means of a structured deposition process and/or a selective plating process. For example, a patterned resist material (e.g. a photo-resist material) may be formed over the conductive layer308bof the encapsulating structure308and/or the second conductive layer312b, wherein the at least one opening316and/or318and/or323may be left exposed (namely, not covered by the patterned resist material). Subsequently, a plating process may be performed, which may form the electrically conductive connection to the at least one contact306cof the chip306. In such an example, the electrically conductive connection may be formed (e.g. by means of selective deposition and/or selective plating) over a part of the chip306and/or the stabilizing structure304that is not covered by the patterned resist material.

Reference signs inFIG. 6AtoFIG. 6Ithat are the same as inFIG. 3AtoFIG. 3Kdenote the same or similar elements as inFIG. 3AtoFIG. 3K. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 6AtoFIG. 6IandFIG. 3AtoFIG. 3Kare described below.

As shown inFIG. 6Cin a view603, the chip306may be arranged in a face-up arrangement. In other words, the second side306b(e.g. backside) of the chip306may face and/or may be in contact (e.g. physical contact) with the carrier302.

As shown inFIG. 6Fin a view609, forming the at least one electrically conductive connection to the at least one contact306cof the chip306may include removing the carrier302e.g. to expose the at least one contact306cof the chip306. In the example shown inFIG. 6F, the at least one contact306cdisposed at the second side306b(e.g. backside) of the chip306may be exposed with the removal of the carrier302.

As described above, the at least one contact306cdisposed at the second side306b(e.g. backside) of the chip306may include, or may be, a metallization layer. Accordingly, in the example shown inFIG. 6F, the metallization layer of the chip306may be exposed with the removal of the carrier302.

As shown inFIG. 6Gin a view611andFIG. 6Hin a view613, forming the electrically conductive connection to the at least one contact306cof the chip306may include forming at least one opening316in the encapsulating structure308to expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306). For example, the at least one opening316may be formed in the conductive layer308bof the encapsulating structure308, as shown inFIG. 6G. The at least one opening316may be formed in the encapsulating structure308by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process).

The at least one opening316may be subsequently deepened (e.g. extended through the insulating layer308aof the encapsulating structure308) to expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306), as shown inFIG. 6H. The at least one opening316may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process).

In the example shown inFIG. 6GandFIG. 6H, there may not be an opening formed to expose at least a part of the stabilizing structure304. However, in another example, the at least one opening323may be formed to expose at least a part of the stabilizing structure304.

As shown inFIG. 6Iin a view615, forming the electrically conductive connection to the at least one contact306cof the chip306may include the plating process (indicated by arrows320). For example, the electrically conductive connection between the conductive layer308bof the encapsulating structure308and the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306) may be formed by means of the plating process (indicated by arrows320). By way of another example, the electrically conductive connection to the at least one contact306cdisposed at the second side306bof the chip306may be formed by means of the plating process (indicated by arrows320).

The plating process (indicated by arrows320) for forming the electrically conductive connection to the at least one contact306cof the chip306may include an electroless plating process or an electrochemical plating process or a direct metallization process.

As described above in relation to the example shown inFIG. 3AtoFIG. 3K, forming the electrically conductive connection to the at least one contact306cof the chip306may include patterning the plated electrically conductive connection. The features of the patterning process described above may be analogously applicable to the example shown inFIG. 6AtoFIG. 6I.

Reference signs inFIG. 7AtoFIG. 7Kthat are the same as inFIG. 3AtoFIG. 3Kdenote the same or similar elements as inFIG. 3AtoFIG. 3K. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 7AtoFIG. 7KandFIG. 3AtoFIG. 3Kare described below.

As shown inFIG. 7Bin a view701, the chip arrangement may include a plurality of chips306. At least one chip306may be arranged in a face-up arrangement (namely, the second side306bmay face and/or be in contact (e.g. physical contact) with the carrier302), and at least one other chip306may be arranged in a face-down arrangement (namely, the first side306amay face and/or be in contact (e.g. physical contact) with the carrier302).

As shown inFIG. 7B, the chip306may be disposed over the carrier302prior to the stabilizing structure304. In such an example, the at least one alignment mark302AL of the carrier may be used to align the chip306to the carrier302.

As shown inFIG. 7Cin a view703, the stabilizing structure304may be disposed subsequent to disposing the chip306. In such an example, the least one alignment mark302AL of the carrier may be used to align the stabilizing structure304. For example, the at least one alignment mark304AL of the stabilizing structure304and the at least one alignment mark302AL of the carrier302may be used to align the stabilizing structure304.

FIG. 7DtoFIG. 7Kshow a process-flow, which may be performed using processes described above in respect ofFIG. 3DtoFIG. 3K.

FIG. 8AtoFIG. 8Kshow a process-flow illustrating an example of the method200shown inFIG. 2applied to a manufacture of a three-dimensional (3D) chip arrangement.

Reference signs inFIG. 8AtoFIG. 8Kthat are the same as inFIG. 7AtoFIG. 7Kdenote the same or similar elements as inFIG. 7AtoFIG. 7K. Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 8AtoFIG. 8KandFIG. 7AtoFIG. 7Kare described below.

As shown inFIG. 8F, a first module802may be arranged over a second module804. A third insulating layer806may be disposed between the first module802and the second module804.

The first and second modules802,804may each include, or may be, the chip arrangement shown inFIG. 8E. Namely, each of the first and second modules802,804may include the carrier302, the chip306, the stabilizing structure304, and the encapsulating structure308(e.g. which may include the insulating layer308a, and which may be free from the conducting layer308b).

As shown inFIG. 8F, the first module802, the second module804, and the third insulating layer806may be disposed over a workpiece808. The first module802, the second module804, and the third insulating layer806may be aligned to each other by means of the at least one alignment mark302AL of the carrier302of the first module802and/or the second module804.

As shown inFIG. 8Gin a view811, the first module802, the second module804, and the third insulating layer806may be pressed together (indicated by arrows812) to form a 3D chip arrangement.

As shown inFIG. 8Hin a view813, the respective carriers of the first and second modules802,804may be removed to expose the at least one contact306cof the chip306of the first module802and the second module804.

As shown inFIG. 8Iin a view815, forming the electrically conductive connection to the at least one contact306cof the chip306may include disposing the second conductive layer312bover the at least one contact306cof the chip306of the first and second modules802,804. In the example shown inFIG. 8I, the second conductive layer312bmay be disposed over the at least one contact306cdisposed at the first side306aof the chip306of the first and second modules802,804. As shown inFIG. 8I, disposing the second conductive layer312bover the at least one contact306cof the chip306may include disposing the second insulating layer312abetween the second conductive layer312band the at least one contact306cof the chip306.

As shown inFIG. 8Jin a view817, forming the electrically conductive connection to the at least one contact306cof the chip306may include forming at least one opening318in the second conductive layer312band the second insulating layer312ato expose the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306). The at least one opening318may be formed and/or deepened by means of the processes described above in respect ofFIG. 3IandFIG. 3J.

Forming the electrically conductive connection to the at least one contact306cof the chip306may include forming at least one through-via814in the 3D chip arrangement. The at least one through-via814may be formed by means of similar or identical processes as those described above in respect of the at least one opening316,318and/or323.

As shown inFIG. 8Kin a view819, forming the electrically conductive connection to the at least one contact306cof the chip306may include a plating process (indicated by arrows320). For example, the electrically conductive connection between the conductive layer308bof the encapsulating structure308and the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306) of the first and second modules802,804may be formed by means of the plating process (indicated by arrows320). The plating process (indicated by arrows320) may line the at least one through-via814and/or fill the at least one opening318with an electrically conductive material.

The plated electrically conductive connection may be patterned, as described above in relation toFIG. 3K.

As described above, a conventional method for manufacturing a chip arrangement may include embedding a chip inside a prepreg, and may include bonding chips that may be disposed face-down on a copper foil with non-conductive adhesives. Compared with such an example, the method200may avoid the disadvantages of such a conventional method (e.g. HAST problems, delamination, etc.) since the second insulating layer312abetween the second conductive layer312band the at least one contact306cof the chip306(e.g. the at least one contact306cdisposed at the first side306aof the chip306) is formed after using vacuum lamination.

As described above, a conventional method for manufacturing a chip arrangement may include an eWLB manufacturing process. Compared with the eWLB manufacturing process, the method200may allow manufacturing double sided arrangements where the chip306may be arranged in a face-up and/or face-down arrangement. Compared with the eWLB manufacturing process, the method200may allow the forming of a plated electrical connection with the first side306aand/or the second side306bof the chip306. Compared with the eWLB manufacturing process, the method200may allow the forming of an electrical connection with the second side306b(e.g. backside) of the chip306by means of a plating process. Compared with the eWLB manufacturing process, the method200may allow the use of standard PCB material (e.g. standard reinforced PCB material), large panel size and low cost PCB manufacturing processes, instead of wafer level processes. This may be easy to incorporate and/or include in a standard PCB production.

As described above, a conventional method for manufacturing a chip arrangement may include the example shown inFIG. 1AtoFIG. 1G. Compared with this example, the method200may allow manufacturing double sided arrangements where the chip306may be arranged in a face-up and/or face-down arrangement. Compared with the example shown inFIG. 1AtoFIG. 1G, the method200may allow the forming of a plated electrical connection with the first side306aand/or the second side306bof the chip306. Compared with the example shown inFIG. 1AtoFIG. 1G, the method200may allow the forming of an electrical connection with the second side306b(e.g. backside) of the chip306by means of a plating process. Compared with the example shown inFIG. 1AtoFIG. 1G, the chip306may be aligned to the carrier302that may have a large size (e.g. same size as a production panel) using the at least one alignment mark302AL of the carrier302. Compared with the leadframe102shown inFIG. 1AtoFIG. 1Gwhich may, for example, be smaller (e.g. about 165×68 mm2), the method200may provide accurate alignment of the chip306to the carrier302. Since a plurality of leadframes102may not be needed compared with the example shown inFIG. 1AtoFIG. 1G, an effect of the method200may be reduction or prevention of additional tolerances between a plurality of leadframes102(which may also be referred to as sub-panels).

As described above, the chip306may be disposed in a face-down arrangement. In such an arrangement, a distance between the at least one contact306cof the chip306and the second conducting layer312bmay be at least substantially equal over a lateral extent of the chip arrangement. The distance may be easily controlled by controlling a thickness of the second insulating layer312a. This may allow for easier forming of the at least one opening316,318, and323.

As compared with a conventional method for manufacturing a chip arrangement, the method200may allow arrangement of the chip306in a face-up or face-down arrangement, or both, and forming of an electrically conductive connection to the chip306from the first side306aand/or the second side306b, thus enabling a manufacture of a 3D chip arrangement.

As an example, the flow diagram900shown inFIG. 9Ashows a process902, which may, for example, be identified with the process shown inFIG. 4AandFIG. 4B.

The process904shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the process shown inFIG. 6B.

The process906shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the process shown inFIG. 6C.

The process908shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the process shown inFIG. 6D.

The process910shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the process shown inFIG. 6E.

The process912shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the process shown inFIG. 6F.

The process914shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the processes shown inFIG. 6GandFIG. 6H.

The process916shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the seed metal or seed metal alloy (e.g. seed copper) described above, which may be sputtered prior to or as part of the plating process (indicated by arrows320).

The process918shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the process shown inFIG. 6I.

The process920shown in the flow diagram900ofFIG. 9Amay, for example, be identified with the patterning process described above.

As another example, the flow diagram901shown inFIG. 9Bshows a process901, which may, for example, be identified with the process shown inFIG. 4AandFIG. 4B.

The process922shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the process shown inFIG. 7B.

The process924shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the processes shown inFIG. 7CandFIG. 7D.

The process926shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the process shown inFIG. 7E.

The process928shown in the flow diagram901ofFIG. 9Bmay, for example, indicate that the at least one alignment mark302AL of the carrier302and/or the at least one alignment mark304AL of the stabilizing structure304may be reproduced at (e.g. reproduced over a surface of) the encapsulating structure308.

The process930shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the process shown inFIG. 7F.

The process932shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the processes shown inFIG. 7GandFIG. 7H.

The process934shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the processes shown inFIG. 7IandFIG. 7J.

The process936shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the process shown inFIG. 7K.

The process938shown in the flow diagram901ofFIG. 9Bmay, for example, be identified with the patterning process described above.

As yet another example, the flow diagram903shown inFIG. 9Cshows a process902, which may, for example, be identified with the process shown inFIG. 4AandFIG. 4B.

The process940shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the process shown inFIG. 3B.

The process942shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the process shown inFIG. 3C.

The process944shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the process shown inFIG. 3D.

The process946shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the process shown inFIG. 3E.

The process948shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the process shown inFIG. 3F.

The process950shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the processes shown inFIG. 3GandFIG. 3H.

The process952shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the processes shown inFIG. 3IandFIG. 3J.

The process954shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the process shown inFIG. 3K.

The process956shown in the flow diagram903ofFIG. 9Cmay, for example, be identified with the patterning process described above.

Reference signs inFIG. 10that are the same as inFIG. 3AtoFIG. 3Kdenote the same or similar elements as inFIG. 3AtoFIG. 3K. Thus, those elements will not be described in detail again here; reference is made to the description above.

The chip arrangement1000may, for example, be manufactured by means of the method200shown inFIG. 2.

The chip arrangement1000may include: a chip306, a stabilizing structure304disposed next to the chip306; and an encapsulating structure308encapsulating the chip306and the stabilizing structure304.

According to various examples presented herein, a chip arrangement may be manufactured using large panel sizes and standard PCB materials and/or processes.

According to various examples presented herein, a chip may be bonded to a temporary thermal release tape of a carrier in a face-up and/or face-down arrangement. After bonding the chip to the temporary release tape, an insulating layer may be manufactured with standard PCB prepreg foils or prepregs and laminates. The insulating layer may be laminated over the chip bonded to the temporary release tape e.g. by means of a lamination process.

After laminating the insulating layer, the carrier and the release tape may be removed and the whole top or bottom side of the chip may be visible. After removal of the carrier and the release tape, an insulation layer may be laminated over of the chip, and microvias may be manufactured on both side of the panel to contact the chip to conductor layers that may be laminated on the chip. Plating and patterning may be performed either with direct metallization and subtractive process or normal pattern plating process (e.g. standard PCB processes). Because the process uses standard low cost, high volume PCB materials and manufacturing equipment, the manufacturing process may be low cost and can be performed on large panels.

The manufacturing process may allow exposure of the whole front side and/or or backside of the chip. Furthermore, a distance between a side of the chip and a conducting layer (e.g. copper surface) can be accurately fixed and manufactured without any voids. By replacing the center prepreg with PCB laminate (cured FR4), the warpage of the chip arrangement is smaller. Furthermore, dimensional stability of the chip arrangement may be improved (e.g. since cured laminate has remarkable smaller shrinkage than prepreg). This PCB laminate can also be patterned (conductors and vias) to improve the routing capability. A foil (e.g. copper foil) with thick carrier (e.g. aluminium or copper) carrier instead of a thin foil can be used to reduce warpage that may occur during lamination. In case a laminate is used for the stabilizing structure instead of prepregs, the manufacture of at least one thru-opening of the stabilizing structure may be easier and cheaper because instead of slow and expensive laser cutting, a routing or punching process can be used. This may also reduce a potential risk caused by the carbon that may be formed on the prepregs during laser cutting. The properties of this core layer can also be selected to suit for application (e.g. low CTE, ultralow CTE).

According to various examples presented herein, a method for manufacturing a chip arrangement may be provided. The method may include disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip.

The stabilizing structure may include, or may consist of, at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.

The laminate material may include, or may consist of, a cured laminate material.

The stabilizing structure may include at least one electrically conductive layer.

The at least one electrically conductive layer may include a plurality of electrically conductive layers, and wherein the stabilizing structure may include at least one via extending through at least a portion of the stabilizing structure and electrically connecting a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers.

The stabilizing structure may include a bonding layer configured to attach the stabilizing structure to the carrier, wherein disposing the stabilizing structure and the chip may include the at least one contact next to each other and over the carrier may include attaching the stabilizing structure to the carrier by means of the bonding layer.

A thickness of the bonding layer of the stabilizing structure may be in the range from about 5 μm to about 150 μm.

The carrier may include at least one opening, wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier includes disposing the stabilizing structure over the at least one opening of the carrier, wherein a first portion of the bonding layer fills the at least one opening of the carrier, and wherein a second portion of the bonding layer is disposed over at least a part of a surface of the carrier outside the at least one opening.

Encapsulating the chip and the stabilizing structure may include a lamination process.

The encapsulating structure may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, a laminate material, an electrically conductive material, and a thermally conductive material.

The laminate material may include, or may consist of, an uncured laminate material.

The stabilizing structure may include a thru-opening, wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include disposing the chip within the thru-opening of the stabilizing structure and over the carrier.

The thru-opening may be formed by means of at least one of a punching process, a routing process, a drilling, an etching process, and a laser structuring process.

The chip may include a first side facing the carrier and a second side opposite the first side, and wherein the at least one contact of the chip is disposed at the first side of the chip or the second side of the chip, or both.

Forming the electrically conductive connection to the at least one contact of the chip may include forming at least one opening in the encapsulating structure to expose the at least one contact of the chip.

Forming the electrically conductive connection to the at least one contact of the chip may include removing the carrier to expose the at least one contact of the chip.

Forming the electrically conductive connection to the at least one contact of the chip may include a plating process.

Forming the electrically conductive connection to the at least one contact of the chip may include: disposing a conductive layer over the at least one contact of the chip; forming the electrically conductive connection between the conductive layer and the at least one contact of the chip; and patterning the conductive layer.

Patterning the conductive layer may include an etching process.

Forming the electrically conductive connection between the conductive layer and the at least one contact of the chip may include a plating process.

Disposing the conductive layer over the at least one contact of the chip may include a lamination process.

Disposing the conductive layer over the at least one contact of the chip may include: disposing an insulating layer between the conductive layer and the at least one contact of the chip.

Forming the electrically conductive connection between the conductive layer and the at least one contact of the chip may include forming at least one opening in the conductive layer and the insulating layer to expose the at least one contact of the chip.

The carrier may include a plate and an adhesive layer disposed over the plate, wherein the adhesive layer faces the stabilizing structure and the chip, and wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include disposing the stabilizing structure and the chip over the adhesive layer of the carrier.

Forming the electrically conductive connection to the at least one contact of the chip may include removing the plate and the adhesive layer of the carrier to expose the at least one contact of the chip.

Removing the adhesive layer of the carrier may include at least one of dissolving the adhesive layer, peeling off the adhesive layer, and curing the adhesive layer.

The adhesive layer may include, or may be, a release tape.

The stabilizing structure may include at least one alignment mark, and wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include: disposing the stabilizing structure over the carrier; aligning the chip to the stabilizing structure by means of the at least one alignment mark; and disposing the chip next to the stabilizing structure and over the carrier.

According to various examples presented herein, a chip arrangement may be provided. The chip arrangement may include: a chip; a stabilizing structure disposed next to the chip; and an encapsulating structure encapsulating the chip and the stabilizing structure.

The stabilizing structure may include at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.

The laminate material may include a cured laminate material.

The stabilizing structure may include at least one electrically conductive layer.

The at least one electrically conductive layer may include a plurality of electrically conductive layers, and wherein the stabilizing structure may include at least one via extending through at least a part of the stabilizing structure and electrically connecting an electrically conductive layer of the plurality of electrically conductive layers to another electrically conductive layer of the plurality of electrically conductive layers.

The encapsulating structure may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material.

The laminate material may include, or may consist of, an uncured laminate material.

Various examples and aspects described in the context of one of the chip arrangements or methods described herein may be analogously valid for the other chip arrangements or methods described herein.