Power overlay structure with leadframe connections

A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

BACKGROUND OF THE INVENTION

Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a power overlay (POL) packaging structure that incorporates a leadframe connection therein.

Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage. In use, high voltage power semiconductor devices are connected to an external circuit by way of a power overlay (POL) packaging and interconnect system, with the POL package also providing a way to remove the heat generated by the device and protect the device from the external environment.

A standard POL package manufacturing process typically begins with placement of one or more power semiconductor devices onto a dielectric layer by way of an adhesive. Metal interconnects (e.g., copper interconnects) are then electroplated onto the dielectric layer to form a direct metallic connection to the power semiconductor device(s). The metal interconnects may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system to and from the power semiconductor device(s).

For connecting to an external circuit, such as by making a second level interconnection to a printed circuit board for example, current POL packages use solder ball grid arrays (BGAs) or land grid arrays (LGAs). While the short stand-off height (˜5 to 20 mils) of these types of interconnections provides a low profile, such connections are susceptible to early failure in high stress conditions. That is, very large temperature cycling ranges, shock, and vibration can induce failures in these solder joints.

Therefore, it would be desirable to provide a POL package having interconnections that are resistive to failure in high stress conditions, so as to enhance interconnection reliability. It would further be desirable for such a POL package to provide such reliability while minimizing cost of the POL package.

BRIEF DESCRIPTION OF THE INVENTION

Embodiments of the invention overcome the aforementioned drawbacks by providing a semiconductor device package structure that eliminates the usage of solder ball grid arrays (BGAs) or land grid arrays (LGAs) to connect the POL package to an external circuit. A leadframe connection is provided for the POL package to provide a highly reliable interconnection structure usable in a variety of high stress environments.

In accordance with one aspect of the invention, a power overlay (POL) structure includes a POL sub-module, with the POL sub-module further including a dielectric layer, at least one semiconductor device attached to the dielectric layer that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

In accordance with another aspect of the invention, a power overlay (POL) packaging structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and including a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a first level interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the first level interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL packaging structure also includes a second level interconnect structure to electrically couple the POL sub-module to an external circuit structure, the second level interconnect structure comprising a leadframe configured to make an interconnection to the external circuit structure.

In accordance with yet another aspect of the invention, a method of forming a power overlay (POL) structure includes providing a POL sub-module including a dielectric layer, at least one semiconductor device attached to the dielectric layer, and a metallic interconnect structure extending through vias in the dielectric layer to electrically connect to the at least one semiconductor device. The method also includes providing a leadframe for the POL sub-module that is configured to make an interconnection between the POL sub-module and an external circuit structure, wherein the leadframe is electrically coupled to the POL sub-module based on one of a direct attachment of the leadframe to the POL sub-module and an attachment of the leadframe to a direct bond copper (DBC) substrate positioned between the POL sub-module and the leadframe. The method further includes encapsulating the POL sub-module and a portion of the leadframe with a polymeric material to provide structural rigidity to the POL structure.

These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention that is provided in connection with the accompanying drawings.

DETAILED DESCRIPTION

Embodiments of the present invention provide for a semiconductor device package having leadframe connections incorporated therein, as well as a method of forming such a semiconductor device package. The semiconductor device package is manufactured such that the leadframe connections form a highly reliable interconnection structure, usable in a variety of high stress environments, for attaching the semiconductor device package to an external circuit.

Referring toFIG. 1, a power overlay (POL) packaging and interconnect structure10is shown according to an embodiment of the invention. The POL structure10includes one or more semiconductor device(s)12therein that, according to various embodiments, may be in the form of a die, diode, or other power electronic device. As shown inFIG. 1, two semiconductor device(s)12are provided in POL structure10, however, it is recognized that a greater or lesser number of semiconductor devices12could be included in POL structure10. The semiconductor device(s)12are packaged within a POL sub-module14that, as will be explained in greater detail below, forms a direct metallic connection to the power semiconductor device(s)12, with the connection being in the form of a low profile, planar interconnect structure, for example, that provides for formation of an input/output (I/O) system to and from the power semiconductor device(s)12. According to one embodiment of the invention, a passive device/component16such as a resistor, a capacitor, or an inductor, is also included in POL structure10.

As shown inFIG. 1, POL structure10also includes a direct bond copper (DBC) substrate18or another similar substrate to which POL sub-module14and passive device16are attached. The DBC substrate18is composed of a ceramic tile (e.g., alumina)20with a sheet of copper22,24bonded to both sides thereof by a high-temperature joining process. According to embodiments of the invention, different brazing and direct bond technologies may be employed based on, for example, whether substrate18is composed of alumina or aluminum nitride and silicon nitride, etc. Both sides of DBC18are then typically etched after firing. The bottom copper layer24on the backside of the DBC substrate18is left fully or partially exposed to provide efficient heat transfer out from the POL structure10. While referred to above and here below as a “DBC substrate,” it is recognized that aluminum can be used instead of copper as the metal layer, and thus such an embodiment is considered within the scope of the invention. Thus, use of the term “DBC substrate” herebelow is meant to encompass a structure18that includes a ceramic tile (e.g., alumina)20with a sheet of any suitable metallic material22,24(such as copper or aluminum) bonded to both sides thereof.

As further shown inFIG. 1, the DBC substrate18includes a leadframe26attached thereto. According to embodiments of the invention, the leadframe26is pre-attached to the DBC substrate18prior to placement of the POL sub-module14thereon, such as by way of high temperature joining process like soldering, brazing, welding, or other similar method, although it is recognized that leadframe26could be post-attached instead (depending on the solder materials used), according to another embodiment of the invention. After attachment to the DBC substrate18, the leadframe26is subsequently cut and formed to enable surface mounting of the POL structure10to an external circuit such as a printed circuit board (PCB)27. The leadframe26is formed to include a number of leads28that are configured to be attached/affixed to the PCB to electrically couple the POL structure10to the PCB. The leadframe26provides a highly reliable interconnection structure that is resistive to failure in high stress conditions, such as an automotive environment that experiences temperature cycling ranges, shock, and vibration. A polymeric underfill or encapsulate or overmold29is provided on POL structure10that encapsulates the top of the POL sub-module14and the area of leadframe26connected to the DBC substrate18and fills in gaps in the POL structure10, so as to provide additional structural integrity to POL structure10. According to one embodiment, encapsulate29is also applied to at least a portion of a back surface of the DBC substrate18.

While POL structure10is shown inFIG. 1as including a DBC substrate18having a leadframe26attached thereto, it is recognized that additional embodiments of the invention are envisioned that do not include a DBC substrate18. That is, according to additional embodiments of the invention, a leadframe26is provided that is attached directly to a POL sub-module14, with the POL sub-module14being overmolded or encapsulated upon attaching to the leadframe26. The leadframe26is thus designed suitably to allow the routing and incorporation of the POL sub-module14.

Referring now toFIGS. 2-12, detailed views of the process steps for a technique of manufacturing the POL structure10ofFIG. 1are provided, according to an embodiment of the invention. As shown first inFIGS. 2-9, process steps for a build-up of the POL sub-module14are provided. Referring toFIG. 2, the build-up process of POL sub-module14begins with the placement and attachment of a dielectric layer30onto a frame structure32. The dielectric layer30is in the form of a lamination or film and is placed on frame structure32to provide stability during the build-up process of POL sub-module14. According to embodiments of the invention, the dielectric layer30may be formed of one a plurality of dielectric materials, such as Kapton®, Ultem®, polytetrafluoroethylene (PTFE), Upilex®, polysulfone materials (e.g., Udel®, Radel®), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide material.

As shown inFIG. 3, upon securing of dielectric layer30to frame structure32, an adhesive layer34is deposited onto dielectric layer30. A plurality of vias36is then formed through the adhesive layer34and dielectric lamination42, as illustrated inFIG. 4. According to embodiments of the invention, the vias36may be formed by way of a laser ablation or laser drilling process, plasma etching, photo-definition, or mechanical drilling processes. In a next step of technique, one or more semiconductor devices12are secured to dielectric layer30by way of adhesive layer34, as illustrated inFIG. 5. To secure the semiconductor devices12to dielectric layer30, the semiconductor devices12are placed onto adhesive layer34and the adhesive34is then cured to secure the semiconductor device12on the dielectric layer30.

While the formation of vias36through adhesive layer34and dielectric lamination30is shown inFIG. 4as being performed prior to placement of semiconductor devices12onto adhesive layer34, it is recognized that the placement of semiconductor devices12could occur prior to via formation. That is, depending on constraints imposed by via size, semiconductor devices12could first be placed on adhesive layer34and dielectric layer30, with the vias36subsequently being formed at locations corresponding to a plurality of metalized circuits and/or connection pads formed on semiconductor devices12. Furthermore, a combination of pre- and post-drilled vias could be employed as needed.

Referring now toFIGS. 6 and 7, upon securing of semiconductor devices12on the dielectric layer30and the formation of vias36, the vias36are cleaned (such as through a reactive ion etching (RIE) desoot process) and subsequently metalized to form interconnects38. The metal interconnects38are typically formed through a combination of sputtering and electroplating applications, although it is recognized that other electroless methods of metal deposition could also be used. For example, a titanium adhesion layer and copper seed layer may first be applied via a sputtering process, followed by an electroplating process that increases a thickness of the copper to a desired level. The applied metal material is then subsequently patterned into metal interconnects38(i.e., first level interconnects) having a desired shape and that function as vertical feed-throughs formed through dielectric layer30and adhesive layer34. As shown inFIG. 6, according to one embodiment, metal interconnects38form direct metallic and electrical connections to circuits/connection pads37on semiconductor devices12and that electrically connect the two semiconductor devices12. The metal interconnects38extend out from circuits and/or connection pads37of semiconductor devices12, through vias/opening36, and out across a top surface of dielectric layer30. As shown inFIG. 8, a solder mask layer40is applied over the patterned metal interconnects38to provide a protective coating for the copper shims thereof. It is recognized, however, that according to other embodiments of the invention, solder mask layer40need not be applied. That is, solder mask layer40is only needed if there is a plan to subsequently solder or leave that surface of POL sub-module14open. Additionally, the layer40could be composed of some metal material other than solder, such as Ni or Ni/Au, or bare copper which can then be encapsulated.

In completing the build-up of POL sub-module14, the POL sub-module14is singulated and removed from frame structure32, as illustrated inFIG. 9. A completed POL sub-module14is thus provided that includes semiconductor devices12, and metal interconnects38that function as metal vertical feed-throughs and top side interconnects. The POL sub-module14is handled as a component or multi-chip module. According to one embodiment, copper shims may also be provided in POL sub-module14and used as an electrical short. The copper shims are used like the semiconductor die12but are made of copper or a similar material. Ceramics like Alumina or aluminum nitride could also be used to provide mechanical support or act as a thermal conduit.

Referring now toFIG. 10, the technique of manufacturing POL structure10continues with the attaching of POL sub-module14and semiconductor devices12to a direct bond copper (DBC) substrate18, according to one embodiment of the invention. As shown inFIG. 10, POL sub-module14is attached to DBC substrate18by way of a solder material42, so as to secure the POL sub-module14and DBC substrate18together. According to one embodiment, a passive device/component16such as a resistor, a capacitor, or an inductor, is also solder attached to DBC substrate18.

As further shown inFIG. 10, the DBC substrate18includes a leadframe26attached thereto. The leadframe26can be pre-attached to DBC substrate18prior to attachment of the POL sub-module14(and passive device16), or post-attached, i.e., after attachment of POL sub-module14to DBC substrate18. According to embodiments of the invention, the leadframe26is pre-attached to the DBC substrate18by way of high temperature joining process such as soldering, brazing, welding, or another suitable method. A polymeric underfill or encapsulate44(e.g., epoxy) is provided on POL structure10that encapsulates the POL sub-module14and the portion of leadframe26connected to the DBC substrate18. The polymeric underfill/encapsulate44also fills in gaps in the POL structure10, as shown inFIG. 11, so as to provide additional structural integrity to the POL structure10. According to one embodiment, encapsulate44is also applied to at least a portion of a back surface of the DBC substrate18, on ceramic tile20.

As shown inFIG. 12, upon encapsulating the POL sub-module14with epoxy44, the leadframe26is subsequently cut and formed to enable surface mounting of the POL structure10to an external circuit, such as a PCB (not shown). The leadframe26is cut/formed to include a number of leads28that are configured to be attached/affixed to the PCB to electrically couple the POL structure10to the PCB, such that the leadframe26forms a second level interconnect for POL structure10. As can be seen inFIG. 12, leadframe26is electrically coupled to POL sub-module14by way of top copper layer22, such that an interconnect can be made between POL sub-module14and the PCB. Beneficially, the leadframe26provides a highly reliable interconnection structure that is resistive to failure in high stress conditions.

Referring now toFIG. 13, according to one embodiment of the invention, the process of manufacturing the POL structure10continues with positioning and securing of a cap46about POL sub-module14of POL structure10. Specifically, cap46is formed about and secured to DBC substrate and may or may not then be filled with polymer before sealing. According to embodiments of the invention, cap46may be in the form of a hermetic cap or a non-hermetic cap. When cap46is a hermetic cap, as DBC substrate18is itself a hermetic structure based on the inclusion of ceramic tile20therein, the hermetic cap46combines with DBC substrate18to hermetically seal POL sub-module14from the external environment. Such hermetic sealing is beneficial in high stress environments and conditions, such as an automotive environment that experiences temperature cycling ranges, shock, and vibration. In another embodiment, the cap46could be a non-hermetic plastic enclosure that is attached to the DBC substrate18and filled with polymer to avoid the use of a mold. The cap/lid46may possess fill holes through which the polymer can be applied and then sealed.

Beneficially, the POL structure10formed according to the process steps illustrated inFIGS. 2-13is constructed such that all connections are brought to the DBC substrate plane (as compared to the prior art where connections are brought to the POL copper plane) and such that the leadframe26is attached to the DBC substrate18, thereby increasing the reliability of POL structure10. POL structure10also provides for the attachment of passives16outside the POL sub-module14, allowing for the use of standard passives and smaller POL sub-modules14.

Referring now toFIG. 14, a POL structure50is shown according to another embodiment of the invention. As shown inFIG. 13, a leadframe52is provided that is attached directly to a POL sub-module54, without the presence of an intermediate DBC substrate therebetween. The POL sub-module54is similar to that of POL sub-module14shown inFIG. 9, for example, as it includes a dielectric layer56to which semiconductor devices58(and when required, shims58for vertical electrical or thermal interconnect) are secured by way of an adhesive layer60. Vias62are formed down through dielectric layer56to connection pads (not shown) on semiconductor devices/shims58and are subsequently metalized to form interconnects64having a desired shape, and top side interconnects.

According to the embodiment of POL structure50shown inFIG. 14, leadframe52is attached directly to a back surface of semiconductor devices58, such as by way of a solder material66, with the leadframe52being constructed to allow the routing and incorporation of the POL sub-module54thereon. After the solder attach of leadframe52to semiconductor devices58, a polymeric underfill, overmold, or encapsulate68is provided on POL structure50that encapsulates the POL sub-module54and a portion of leadframe52. The polymeric underfill/encapsulate68also fills in any gaps in the POL structure50, thus providing additional structural integrity to the POL structure50. Alternatively, the material68that fills the gap under the POL structure50could be different from the overmold/encapsulate68around the structure.

Therefore, according to one embodiment of the invention, a power overlay (POL) structure includes a POL sub-module, with the POL sub-module further including a dielectric layer, at least one semiconductor device attached to the dielectric layer that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

According to another embodiment of the invention, a power overlay (POL) packaging structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and including a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a first level interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the first level interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL packaging structure also includes a second level interconnect structure to electrically couple the POL sub-module to an external circuit structure, the second level interconnect structure comprising a leadframe configured to make an interconnection to the external circuit structure.

According to yet another embodiment of the invention, a method of forming a power overlay (POL) structure includes providing a POL sub-module including a dielectric layer, at least one semiconductor device attached to the dielectric layer, and a metallic interconnect structure extending through vias in the dielectric layer to electrically connect to the at least one semiconductor device. The method also includes providing a leadframe for the POL sub-module that is configured to make an interconnection between the POL sub-module and an external circuit structure, wherein the leadframe is electrically coupled to the POL sub-module based on one of a direct attachment of the leadframe to the POL sub-module and an attachment of the leadframe to a direct bond copper (DBC) substrate positioned between the POL sub-module and the leadframe. The method further includes encapsulating the POL sub-module and a portion of the leadframe with a polymeric material to provide structural rigidity to the POL structure.