Semiconductor packages

A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0100440, filed on Aug. 8, 2017, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Example embodiments of the present disclosure relate to semiconductor packages and, more specifically, to water level packages.

2. Discussion of Related Art

A semiconductor chip in a semiconductor package may malfunction due to electromagnetic interference (EMI). As electronic devices are downsized, a semiconductor package is highly integrated and downscaled. There are increasing demands for enhanced EMI shield and high heat dissipation performance in the highly integrated and downscaled semi conductor package.

SUMMARY

According to an example embodiment of the inventive concepts, a semiconductor package may include a heat spreading layer including a hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole.

According to an example embodiment of the inventive concepts, a semiconductor package may include a heat spreading layer including at least one chip portion, a shielding portion surrounding the at least one chip portion, and a hole portion outside the shielding portion and including a hole, at least one first semiconductor chip below the at least one chip portion of the heat spreading layer, at least one shielding wall in contact with and below the shielding portion of the heat spreading layer, a first conductive pillar passing through the hole included in the hole portion of the heat spreading layer, a second conductive pillar below the at least one first semiconductor chip, a first mold layer covering at least one sidewall of the shielding wall, a sidewall of the first conductive pillar, a sidewall of the at least one second conductive pillar, and a sidewall of the first semiconductor chip, and a redistribution structure below the first semiconductor chip and in contact with the at least one shielding wall, the first conductive pillar, and the second conductive pillar.

According to an example embodiment of the inventive concepts, a semiconductor package may include a first semiconductor package, a second semiconductor package on the first semiconductor package, and an inter-package connection between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a redistribution structure, a first semiconductor chip on the redistribution structure, a heat spreading layer on the first semiconductor chip and including a hole, a first mold layer between the heat spreading layer and the redistribution structure and covering a sidewall of the first semiconductor chip, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application.

FIGS. 1A and 1Bare a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment.

Referring toFIGS. 1A and 1B, a semiconductor package100may include a heat spreading layer110, a first semiconductor chip140A, a shielding wall130, a first conductive pillar120, a second conductive pillar160, a first mold layer170, a redistribution structure180, and an outer terminal190.

The heat spreading layer110may include a thermal and electrically conductive material. The heat spreading layer110may include, for example, Cu, Ni, Au, Ag, Al, or a combination thereof. In some embodiments, the heat spreading layer110may be formed of stacked layers. In some embodiments, the heat spreading layer110may include a laminate, such as a copper clad laminate (CCL).

The heat spreading layer110may include a chip portion112, a shielding portion114, and a hole portion116. The chip portion112may be located in a central region of the heat spreading layer110. The shielding portion114may surround the chip portion112. The hole portion116may be located outside the shielding portion114. The heat spreading layer110may include a hole H penetrating the heat spreading layer110in the hole portion116. In some embodiments, the hole portion116may include a plurality of spaced holes H arranged along sides (e.g., peripheral areas) of the heat spreading layer110.

The first semiconductor chip140A may be disposed below the chip portion112of the heat spreading layer110. The first semiconductor chip140A may be, for example, a logic or memory chip. The logic chip may be, for example, a central processing unit (CPU), a controller, an application processor (AP), or an application specific integrated circuit (ASIC). The memory chip may be, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change memory (PRAM), a resistive random access memory (RRAM), or a magnetic random access memory (MRAM).

The first semiconductor chip140A may be attached to an underside (e.g., a bottom surface) of the chip portion112of the heat spreading layer110by a chip adhesion layer150disposed between the first semiconductor chip140A and the chip portion112. The chip adhesion layer150may include, for example, a non-conductive adhesive, an anisotropic conductive adhesive, or an isotropic conductive adhesive. The non-conductive adhesive, the anisotropic conductive adhesive, and an isotropic conductive adhesive may be of a film or paste type. The non-conductive adhesive may include polymer resin. The anisotropic conductive adhesive and an isotropic conductive adhesive may include polymer resin and conductive particles. The conductive particles may include, for example, Ni, Au, Ag, and/or Cu. The polymer resin may include, for example, thermal curable resin, thermoplastic resin, and/or ultraviolet (UV) curable resin. The chip adhesion layer150may include, for example, epoxy resin, urethane resin, or acrylic resin.

The second conductive pillar160may be disposed below the first semiconductor chip140A. The second conductive pillar160may be electrically connected to the first semiconductor chip140A. The first semiconductor chip140A may be electrically connected to the redistribution structure180via the second conductive pillar160. The second conductive pillar160may include an electrically conductive material. For example, the second conductive pillar160may include metal (e.g., Cu, Ni, Al, Au, or Ag).

The shielding wall130may be disposed below the shielding portion114of the heat spreading layer110. The shielding wall130may vertically extend from the shielding portion114of the heat spreading layer110to the redistribution structure180. The shielding wall130may be spaced from first semiconductor chip140A and (continuously) extend along an outer perimeter of the chip portion112to surround the first semiconductor chip140A. A width of the shielding wall130may be about 5 μm to 100 μm. A height of the shielding wall130may be about 10 μm to 500 μm. The shielding wall130may be connected to the ground via the redistribution structure180. The shielding wall130may function as a electromagnetic interference (EMI) shield and a heat transfer medium for transmitting heat generated at the redistribution structure180to the heat spreading layer110. The shielding wall130may include metal (e. Cu, Al, Ni, Au, and/or Ag). The shielding wall130may include the same material as or a different material from the heat spreading layer110.

The first conductive pillar120may contact the redistribution structure180and extend into the hole H of the heat spreading layer110. A diameter of the first conductive pillar120may be smaller than a diameter of the hole H. A sidewall of the first conductive pillar120may be spaced from an inner sidewall of the hole H. An upper surface of the first conductive pillar120may be coplanar with an upper surface of the heat spreading layer110. A height of the first conductive pillar120may be greater than the height of the shielding wall130. A difference in the heights of the first conductive pillar120and the shielding wall130may be equal to thickness of the heat spreading layer110. The semiconductor package100may be connected to the same or different type of another semiconductor package via the first conductive pillar120. The first conductive pillar120may include an electrically conductive material. The first conductive pillar120may include, for example, Cu, Ni, Al, Au, Ag, or a combination thereof. The first conductive pillar120and the shielding wall130may be made of the same material. In some embodiments, the first conductive pillar120and the shielding wall130may be made of different materials. An upper portion of the first conductive pillar120may include, for example, organic solderability preservative (OSP), Ni/Au, electroless nickel immersion gold (EMG), or electroless nickel electroless palladium immersion gold (ENEPIG), to prevent or mitigate oxidation thereof.

A lower surface of the shielding wall130, a lower surface of the first conductive pillar120, and a lower surface of the second conductive pillar160may each be connected to the redistribution structure180. The lower surface of the shielding wall130, the lower surface of the first conductive pillar120, and the lower surface of the second conductive pillar160may be coplanar. The redistribution structure180may include an upper pad182, a redistribution pattern186, a lower pad188, and an insulating layer184. The upper pad182may be disposed on an upper side (e.g., a top surface) of the redistribution structure180and be electrically connected to the shielding wall130, the first conductive pillar120, and/or the second conductive pillar160. The lower pad188may be disposed on an underside of the redistribution structure180and be electrically connected to the outer terminal190. The redistribution pattern186may connect the upper pad182to the lower pad188. A shape or configuration of the redistribution pattern186is not limited to that shown inFIG. 1B, but may be variously modified. In some embodiments, the redistribution pattern186may be formed of a plurality of layers. The upper pad182, the lower pad188, and the redistribution pattern186may include an electrically conductive material, for example, Cu, Ni, Au, Ag, Al, W, Ti, Ta, TiN, or a combination thereof. The insulating layer184may include, for example, an organic insulating material (e.g., polyimide, polybenzoxazole (PBO), or benzocyclobutene (BCB)), or an inorganic insulating material (e.g., silicon nitride, silicon oxynitride, or silicon oxide).

The first mold layer170may fill a space between the redistribution structure180and the heat spreading layer110. The first mold layer170may cover at least a sidewall of the first semiconductor chip140A, a sidewall of the shielding wall130, and a sidewall of the second conductive pillar160. The first mold layer170may fill the hole H. The first mold layer170may fill a gap between the inner sidewall of the hole H and a sidewall of the first conductive pillar120. Thus, the first conductive pillar120and the heat spreading layer110may be separated from each other with the first mold layer170disposed therebetween. An upper surface of a portion of the first mold layer170filling the hole H, the upper surface of the first conductive pillar120, and the upper surface of the heat spreading layer110may be coplanar. The first mold layer170may include, for example, thermally curable resin, thermoplastic resin, or UV curable resin. The first mold layer170may include, for example, epoxy resin (e.g., epoxy mold compound (EMC)) or silicone resin.

The outer terminal190may be disposed below the redistribution structure180. The outer terminal190may be connected to the lower pad188of the redistribution structure180. The outer terminal190may include a bump, such as a metal bump or a solder bump. The metal bump may include an electrical conductive material (e.g., Cu, Al, and/or Au). The solder bump may include, for example, Sn/Pb or Sn/Ag/Cu. Although not shown, the outer terminal190may further include an under bump metal pattern disposed between the bump and the lower pad188of the redistribution structure180. The under bump metal pattern may include metal (e.g., Cr, W, Ti, Cu, Ni, Al, Pd, and/or Au).

According to an example embodiment of the inventive concepts, because the shielding wall130and the heat spreading layer110cover the first semiconductor chip140A, the first semiconductor chip140A may be shielded from electromagnetic interference (EMI). Additionally, heat generated from the first semiconductor chip140A and/or the redistribution structure180may be transmitted to the heat spreading layer110having a lager plane area, such that the semiconductor package100may have an enhanced heat dissipation performance.

The heat spreading layer110may be formed to have the plane area occupying or covering most of or an entirety of a plane area of the semiconductor package100. For example, an upper surface of the first mold layer170except for the portion filling the hole H may be covered by the heat spreading layer110. A plane area of the redistribution structure180may be substantially equal to a sum of the plane area of the heat spreading layer110and a plane area of the hole H. The semiconductor package100may have the enhanced heat dissipation property by the heat spreading layer110having the larger plane area.

Furthermore, because the heat spreading layer110and the redistribution structure180are disposed at the upper portion and lower portion, respectively, of the semiconductor package100, the warpage of the semiconductor package100, caused by a difference in coefficients of thermal expansion between elements of the semiconductor package100, may be reduced or prevented. By adjusting a thickness and material of the heat spreading layer110, the warpage of the semiconductor package100may be controlled.

FIG. 2Ais a cross-sectional view illustrating a semiconductor package according to an example embodiment. Hereinafter, differences between a semiconductor package200A according to the present example embodiment and the semiconductor package100according to the example embodiment described with reference toFIGS. 1A and 1Bwill be described.

Referring toFIG. 2A, the semiconductor package200A may further include a third conductive pillar210disposed between the chip portion112of the heat spreading layer110and the first semiconductor chip140A. The third conductive pillar210may extend from the chip portion112of the heat spreading layer110toward the first semiconductor chip140A. A height of the third conductive pillar210may be smaller than the height of the first conductive pillar120and the height of the shielding wall130. An upper surface of the third conductive pillar210may contact the chip portion112of the heat spreading layer110. A lower surface of the third conductive pillar210may not contact the first semiconductor chip140A. The chip adhesion layer150may be disposed between the first semiconductor chip140A and the heat spreading layer110and between the first semiconductor chip140A and the lower surface of the third conductive pillar210. The third conductive pillar210may include an electrically and thermally conductive material. The third conductive pillar210may include, for example, Cu, Ni, Au, Ag, Al, or a combination thereof. Because the semiconductor package200A includes the third conductive pillar210, the heat generated from the first semiconductor chip140A may be more rapidly transmitted to the heat spreading layer110. For example, the heat generated from the first semiconductor chip140A may be transmitted to the heat spreading layer110via a short thermal path of the chip adhesion layer150and the third conductive pillar210having the relatively high thermal conductivity. Thus, the semiconductor package200A may have an enhanced heat dissipation performance.

FIG. 2Bis a cross-sectional view illustrating a semiconductor package according to an example embodiment. Hereinafter, differences between a semiconductor package200B according to the present example embodiment and the semiconductor package200A according to the example embodiment described with reference toFIG. 2Awill be described.

Referring toFIG. 2B, the lower surface of the third conductive pillar210may contact the first semiconductor chip140A in the semiconductor package200B. The heat generated from the first semiconductor chip140A may be transmitted to the heat spreading layer110via the third conductive pillar210having relatively high thermal conductivity. Thus, the semiconductor package200B may have an enhanced heat dissipation performance.

FIGS. 3A and 3Bare a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment, Hereinafter, differences between a semiconductor package300according to the present example embodiment and the semiconductor package100according to the example embodiment described with reference toFIGS. 1A and 1Bwill be described.

Referring toFIGS. 3A and 3B, in the semiconductor package300, the heat spreading layer110may include a plurality of laterally spaced chip portions112A and112B. The shielding portion114may surround the plurality of chip portions112A and112B. A plurality of semiconductor chips140A and140B may be disposed below the plurality of chip portions112A and112B, respectively. For example, referring toFIG. 3B, the heat spreading layer110may include a first chip portion112A and a second chip portion112B. The plurality of semiconductor chips140A and140B may include the first semiconductor chip140A and a second semiconductor chip140B. The first semiconductor chip140A may be disposed below the first chip portion112A of the heat spreading layer110. The second semiconductor chip140B may be disposed below the second chip portion112B of the heat spreading layer110. The first semiconductor chip140A and the second semiconductor chip140B may each be a memory or logic device. The first semiconductor chip140A and the second semiconductor chip140B may be of the same type or different types. A plurality of shielding walls130A and130B may be disposed below the shielding portion114of the heat spreading layer110and respectively surround the plurality of semiconductor chips140A and140B. The plurality of shielding walls130A and130B may include a first shielding wall130A and a second shielding wall130B. The first shielding wall130A may surround the first semiconductor chip140A. The second shielding wall130B may surround the second semiconductor chip140B. As the plurality of shielding walls130A and130B surround the plurality of semiconductor chips140A and140B, respectively, EMI that may be generated between the plurality of semiconductor chips140A and140B may be prevented or reduced. In some embodiments, the semiconductor package300may be of a system in package (SIP) type.

FIGS. 4A and 4Bare a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment, Hereinafter, differences between a semiconductor package400according to the present example embodiment and the semiconductor package300according to the example embodiment described with reference toFIGS. 3A and 3Bwill be described.

Referring toFIGS. 4A and 4B, in the semiconductor package400, the plurality of semiconductor chips140A and140B may be disposed below one chip portion112of the heat spreading layer110. For example, the first semiconductor chip140A and the second semiconductor chip140B may be disposed below the one chip portion112of the heat spreading layer110. One shielding wall130disposed below the shielding portion114of the heat spreading layer110may surround the plurality of semiconductor chips140A and140B.

FIG. 5is a cross-sectional view illustrating a semiconductor package according to an example embodiment.

Referring toFIG. 5, a semiconductor package500may be of a package on package (POP) type. The semiconductor package500may include a first semiconductor package510, a second semiconductor package520on the first semiconductor package510, and an inter-package connection530between the first semiconductor package510and the second semiconductor package520.

The first semiconductor package510may be one of the semiconductor packages100,200A,200B,300, or400described above. For example, the first semiconductor package510may include the redistribution structure180, the outer terminal190below the redistribution structure180, the first semiconductor chip140A on the redistribution structure180, the heat spreading layer110disposed on the first semiconductor chip140A and having the hole H, the first mold layer170filling the space between the redistribution structure180and the heat spreading layer110and surrounding or covering the first semiconductor chip140A, the shielding wall130extending from the redistribution structure180to the heat spreading layer110and covering or surrounding at least a sidewall of the first semiconductor chip140A, and the first conductive pillar120extending from the redistribution structure180into the hole H of the heat spreading layer110. Further, the first semiconductor package510may further include the chip adhesion layer150disposed between the heat spreading layer110and the first semiconductor chip140A. In some embodiments, the first semiconductor package510may further include the third conductive pillar210between the heat spreading layer110and the first semiconductor chip140A, shown inFIG. 2A or 2B.

The second semiconductor package520may be the same as or different from the first semiconductor package510. The second semiconductor package520may include, for example, a second substrate522, a plurality of second semiconductor chips140B on the second substrate522, and a second mold layer526covering the second semiconductor chips140B.

The second mold layer526may protect the second semiconductor chips140B from physical or chemical damage. The second mold layer526may include thermally curable resin, thermoplastic resin, and/or UV curable resin. The second mold layer526may include silicon resin or epoxy resin (e.g., EMC). The second substrate522may include, for example, silicon, glass, ceramic, or plastics.

The second semiconductor chips140B may each be a memory or logic device. The second semiconductor chips140B may be of the same type as or different types from the first semiconductor chip140A. The number of the second semiconductor chips140B may not be limited to the number of those shown inFIG. 5.

The adhesion layer523may be disposed between the second semiconductor chips140B and between a lowermost one of the second semiconductor chips140B and the second substrate522such that the second semiconductor chips140B may be attached to each other and to the second substrate522. The adhesion layer523may include, for example, thermally curable resin, thermoplastic resin, and/or UV curable resin. The adhesion layer523may include, for example, epoxy resin, urethane resin, or acrylic resin. The second semiconductor chips140B may each include a through silicon via (TSV)524and an inner connection528. The second semiconductor chips140B and the second substrate522may be electrically connected via the TSV524and the inner connection528. The TSV524and the inner connection528may include an electrically conductive material.

The structure of the second semiconductor package520may not be limited to that shown inFIG. 5. For example, the second semiconductor chips140B may be connected to the second substrate522by a boding wire. In some embodiments, the second semiconductor package520may include one semiconductor chip. The one semiconductor chip and the second substrate522may be connected by a wire bonding method or a flip chip bonding method.

The inter-package connection530may electrically connect the first semiconductor package510to the second semiconductor package520. The inter-package connection530may contact the first conductive pillar120and not contact the heat spreading layer110. The inter-package connection530may include an electrically conductive material, for example, Al, Au, or solder.

As the semiconductor package500includes the shielding wall130and the heat spreading layer110, EMI that may be generated between the first semiconductor chip140A and the second semiconductor chips140B may be prevented or reduced.

FIGS. 6A, 6C, 6E, 6G, 6I, 6K, and 6Lare cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment.FIGS. 6B, 6D, 6F, 6H, and 6Jare plan views illustrating the same method of manufacturing a semiconductor package according to the same example embodiment.FIGS. 6B, 6D, 6F, 6H, and6J correspond toFIGS. 6A, 6C, 6E, 6G, 6I, respectively.

Referring toFIG. 6A, a carrier adhesion layer620and the heat spreading layer110may be formed on a carrier610. The carrier610may include, for example, glass, plastics, ceramic, or a semiconductor material (e.g., silicon or germanium). The carrier adhesion layer620may include, for example, thermally curable resin, thermoplastic resin, or UV curable resin. The carrier adhesion layer620may be an adhesive tape including acrylic resin or epoxy resin. In some embodiments, the heat spreading layer110may be formed by attaching copper clad laminate (CCL) to the carrier610using the carrier adhesion layer620. When using the method of attaching the CCL, the heat spreading layer110that is relatively thick may be quickly formed on the carrier610. Thus, the semiconductor package having improved EMI shielding effect may be manufactured, and its manufacturing time may be reduced.

Referring toFIG. 6B, the heat spreading layer110may include the chip portion112, the shielding portion114, and the hole portion116.

Referring toFIGS. 6C and 6D, the hole H may be formed in the hole portion116of the heat spreading layer110. The hole H may be formed by a photolithography process. For example, the hole H may be formed by forming a photoresist pattern (not shown) on the heat spreading layer110, etching the hole portion116of the heat spreading layer110exposed by the photoresist pattern, and removing the photoresist pattern. The heat spreading layer110may be etched by dry or wet etch. In some embodiments, the hole H may be formed by mechanical drilling.

In some embodiments, unlike those shown inFIGS. 6A to 6D, the hole H in the heat spreading layer110may be formed first, and then the heat spreading layer110including the hole H may be attached to the carrier adhesion layer620.

In some embodiments, unlike those shown inFIGS. 6A to 6D, the heat spreading layer110including the hole H may be formed by a photolithography process and an electric plating process. For example, the heat spreading layer110including the hole H may be formed by forming a mask pattern on the carrier adhesion layer620by the photolithography process, and then forming a material layer on the resulting structure having the mask pattern by lectric plating process and removing the mask pattern.

Referring toFIGS. 6E and 6F, the first conductive pillar120extending from the inside of the hole H and the shielding wall130extending from the shielding portion114of the heat spreading layer110may be formed. The first conductive pillar120and the shielding wall130may be formed at the same time. For example, the first conductive pillar120and the shielding wall130may be concurrently formed by forming a photoresist pattern on the heat spreading layer110, forming a metal layer on the resulting structure having the photoresist pattern by an electric plating process, and removing the photoresist pattern. Because the first conductive pillar120and the shielding wall130may be concurrently formed, its manufacturing time and cost may be reduced.

Referring toFIGS. 6G and 6H, the first semiconductor chip140A having the second conductive pillar160connected thereto may be attached to the chip portion112of the heat spreading layer110. To attach the first semiconductor chip140A to the heat spreading layer110, the chip adhesion layer150may be used.

Referring toFIGS. 6I and 6J, the first mold layer170may be formed on the heat spreading layer110to encapsulate the first semiconductor chip140A, the first conductive pillar120, the shielding wall130, and the second conductive pillar160. The first mold layer170may fill the hole H to insulate the first conductive pillar120from an inner surface of the hole H. Thereafter, the first mold layer170may be ground to expose the first conductive pillar120, the shielding wall130, and the second conductive pillar160.

Referring toFIG. 6K, the redistribution structure180may be formed on the first mold layer170. The outer terminal190may be formed on the redistribution structure180. The redistribution structure180may include the insulating layer184, the redistribution pattern186, the upper pad182, and the lower pad188. The insulating layer184may be formed by, for example, a spin coating process, a physical vapor deposition process, or a chemical vapor deposition process, or an atomic layer deposition process. The redistribution pattern186may be formed by, for example, photolithography process and an electric plating process. The upper pad182and the lower pad188may be formed by, for example, a sputtering process or an electric plating process. The outer terminal190may be formed by, for example, attaching a solder ball on the lower pad188and performing a reflowing process.

Referring toFIG. 6L, the carrier610and the carrier adhesion layer620may be removed. The carrier adhesion layer620may be removed along with the carrier610or separately removed. Thereafter, a cutting process may be performed such that the semiconductor package100shown inFIGS. 1A and 1Bmay be completed. The cutting process may include a sawing process or a laser cutting process.

FIGS. 7A, 7B, and 7Care cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. Hereinafter, differences between the present example embodiment and the example embodiment described with reference toFIG. 6A to 6Iwill be described.

Referring toFIG. 7A, after performing the same processes as described with reference toFIGS. 6A to 6D, the third conductive pillar210may be formed on the heat spreading layer110. For example, the third conductive pillar210may be formed by forming a photoresist pattern on the heat spreading layer110to have an opening exposing a portion of the heat spreading layer110, forming a conductive material layer on the resulting structure having the photoresist pattern by an electric plating process, and removing the photoresist pattern.

Referring toFIG. 7B, the first conductive pillar120extending from the inside of the hole H and the shielding wall130extending from the heat spreading layer110may be formed. For example, the first conductive pillar120and the shielding wall130may be concurrently formed by forming a photoresist pattern on the heat spreading layer110to have an opening exposing the hole H and another portion of the heat spreading layer110, forming a conductive material layer on the resulting structure having the photoresist pattern by an electric plating process, and removing the photoresist pattern.

In some embodiments, the order of the process described with reference toFIG. 7Aand the process described with reference toFIG. 7Bmay be inverted. For example, after forming the first conductive pillar120and the shielding wall130using a first photolithography process and a first electric plating process, the third conductive pillar210may be formed using a second photolithography process and a second electric plating process.

Referring toFIG. 7C, the first semiconductor chip140A may be attached to the third conductive pillar210using the chip adhesion layer150coated on the first semiconductor chip140A. The chip adhesion layer150may contact the heat spreading layer110by pressing the first semiconductor chip140A. The chip adhesion layer150may or may not remain between the first semiconductor chip140A and the third conductive pillar210depending on a pressing pressure against the first semiconductor chip140A. In some embodiments, after coating the chip adhesion layer150on the third conductive pillar210and the heat spreading layer110, the first semiconductor chip140A may be attached to the third conductive pillar210.

Thereafter, the same processes as described with reference toFIGS. 6I to 6Lmay be reformed to complete the semiconductor package200A or200B shown inFIG. 2A or 2B.

FIGS. 8A and 8Bare cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. Hereinafter, differences between the present example embodiment and the example embodiment described with reference toFIG. 7A to 7Cwill be described.

Referring toFIG. 8A, after performing the same processes as described with reference toFIGS. 6A to 6D, a first portion120A of the first conductive pillar120, a first portion130-1of the shielding wall130, and the third conductive pillar210may be formed. The first portion120A of the first conductive pillar120, the first portion130-1of the shielding wall130, and the third conductive pillar210may be concurrently formed by a first photolithography process and a first electric plating process.

Referring toFIG. 8B, a second portion120B of the first conductive pillar120and a second portion130-2of the shielding wall130may be concurrently formed on the first portion120A of the first conductive pillar120and the first portion130-1of the shielding wall130, respectively, by a second photolithography process and a second electric plating process.

Thereafter, the same processes as described with reference toFIGS. 7C and 6I to 6Lmay be performed to complete the semiconductor packages200A and200B shown inFIG. 2A or 2B.