IC wafer for identification of circuit dies after dicing

Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

BACKGROUND

The subject matter disclosed herein relates to integrated circuit (IC) wafer structures and methods for identifying the location of a particular die after dicing of the wafer. More specifically, aspects of the invention relate to structures which include identification features for indicating the original location of a circuit die on an IC wafer, methods of forming such features, and methods of using such features.

Integrated circuit manufacturing includes fabricating the structure of multiple circuit dies together on a single semiconductor wafer. After forming one semiconductor wafer, the wafer may be split into multiple circuit dies. Wafer dicing refers to the process of dicing (i.e., splitting) the single semiconductor wafer into a plurality of circuit dies for conversion into end products. The dicing of a wafer includes defining a set of scribe lines, alternatively known as kerf lines, for separating various regions of the wafer, such that each region includes the structure of a particular die bounded by a corresponding set of scribe lines. The dicing process may include the mechanical splitting of the wafer, e.g., by laser cutting and/or other procedures for separating semiconductor material and elements formed therein into smaller pieces.

One underlying characteristic of wafer dicing is the loss of materials included at or near the set of scribe lines. These materials and regions may be known as the IC wafer's kerf region. Conventional testing methods may include forming various structures, features, etc., in the kerf region of an IC wafer to determine the quality of a wafer before it is diced. IC wafers that pass this stage of testing will then be diced, and the test structures included in the kerf regions of the wafer will be removed or otherwise disconnected from functional components of the individual circuit dies. Pre-dice testing of an IC wafer may not fully account for post-deployment characteristics of a particular product, e.g., functional failures of a fabricated unit. After a wafer is diced, the various wafer dies may be intermixed and/or distributed to different customers or sites without regard to which wafer, or portion of a wafer, may have been used to produce each circuit die. Conventional testing may be limited to evaluating the characteristics of the entire wafer prior to dicing, or examination of particular units after manufacture, without any ability to associate an end product or batch of products with a particular portion of the original wafer.

SUMMARY

A first aspect of the present disclosure provides an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines, the IC structure including: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies, wherein the reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies, the reference feature of each circuit die having a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

A second aspect of the present disclosure provides a method for manufacturing integrated circuit (IC) structures, the method including: forming a plurality of circuit dies in an IC wafer, each of the plurality of circuit dies being bounded by a set of scribe lines, wherein forming the plurality of circuit dies further includes: forming a reference feature in a first layer of each of the plurality of circuit dies, wherein the reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and forming an identification feature in a second layer of each of the plurality of circuit dies, the identification feature having an offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, wherein each of the plurality of circuit dies in the IC wafer includes a distinct offset vector for the identification feature relative to the identification feature of each other circuit die.

A third aspect of the present disclosure provides a method for identifying circuit dies, the method including: selecting one of a plurality of circuit dies for analysis, the plurality of circuit dies being diced from an IC wafer; measuring an offset vector between an identification feature of a first layer in the selected circuit die and a reference feature of a second layer in the selected circuit die, wherein each of the plurality of circuit dies includes the reference feature at a same location, and wherein each of the plurality of circuit dies includes a distinct offset vector indicative of a positional difference between the identification feature and the reference feature for one of the plurality of circuit dies, relative to the identification feature of each other circuit die; comparing the measured offset vector for the selected circuit die with an index of offset vectors for the IC wafer; and identifying a location of the selected circuit die in the plurality of circuit dies of the IC wafer, based on the comparing of the measured offset vector with the index of offset vectors for the IC wafer.

DETAILED DESCRIPTION

Referring toFIG. 1, embodiments of the disclosure provide an integrated circuit (IC) wafer100structured for the identifying of individual circuit dies after the dicing of IC wafer100. Technical challenges associated with the manufacture of IC product units include the tracing of functional failing products (i.e., products which operate in a manner other than intended) to specific regions of an IC wafer from which the products were manufactured. Functional failing products may include, e.g., defective chips and/or chips with functional failures. Conventional testing may be limited to evaluating the characteristics of the entire wafer prior to dicing, or examination of particular units after manufacture, without any ability to associate an end product or batch of products with a particular portion of the original wafer. To provide a more comprehensive model of quality management for IC product units, embodiments of IC wafer100discussed herein may allow users and/or manufacturers to identify a particular region of IC wafer100where individual dies, products, etc., originated before dicing occurred.

As shown inFIG. 1, IC wafer100(depicted via plan view in plane X-Y) may include a body102, e.g., one or more semiconductor materials, dielectric materials, conductive materials, manufactured to include the device architecture of several products. Body102more specifically may include multiple vertically separated layers therein, with at least two of those layers being separately identified herein as first and second layers (e.g., layers L1, L2ofFIG. 5). The various portions of IC wafer100to be separated into distinct products or groups of products may be identified as circuit dies104to be separated into individual units. Each circuit die104may be laterally separated from other circuit dies104on IC wafer100by a set of scribe lines106indicating the specific locations where body102of IC wafer100will be diced in subsequent processing. Scribe liens106may take the form of grooves formed within IC wafer100, and thus may be visible to an observer in some instances. As shown, scribe lines106may be arranged in the shape of a grid on body102, such that each circuit die104covers a uniform surface area on body102. Non-rectangular portions of body102may be positioned outside scribe lines106.

The various regions and components of IC wafer100may have distinct roles before and after IC wafer100is separated into individual circuit dies. IC wafer100may be configured for dicing via one or more mechanical instruments (e.g., dicing blades), and/or other currently known or later developed instruments such as laser dicing tools, etc. Prior to dicing, portions of body102located outside of scribe lines106may not include functional features of a product therein, and instead may include one or more test structures configured to analyze IC wafer100before dicing occurs. Thus, any materials used for testing of IC wafer100located outside scribe lines106may have no significant use after dicing concludes. As also noted above, each circuit die104may also include sets of metal wires, vias, device components, dielectric materials, etc., therein, though such components are omitted from the depiction of IC wafer100inFIG. 1solely for clarity of illustration. Such components in each circuit die104are conventionally structured only to yield the structural and operational features of each device formed from IC wafer100.

Turning now toFIG. 2, IC wafer100is shown with magnified views of three circuit dies104(identified separately as104A,104B,104C) to illustrate features of IC wafer100in various embodiments. Each circuit die104may include, e.g., one or more reference features110positioned in a first layer of a respective circuit die104. As shown in each magnified view of circuit dies104A,104B,104C, reference features110may be equidistant from one of a respective set of scribe lines106for each circuit die104. To illustrate the equidistant separation each reference feature110and each corresponding scribe line106, a separation distance E illustrates the same positional difference between each reference feature100and each scribe line106. Reference feature110may be composed of any material capable of being structurally identified from the remainder of circuit die104and/or components therein. For example, reference feature110may include one or more light-reflecting materials capable of detection within the structure of circuit die104before or after dicing occurs.

In various embodiments, reference feature(s)110may be composed of a metal wire, an insulative material (e.g., one or more photolithographic masks), and/or other components distinct from other materials included within circuit die104. Furthermore, reference features110may be distinct and/or other structurally disconnected from other portions of circuit die104for providing the operational structure and/or features of a particular product, despite being formed within a functional region of one circuit die104. Two reference features110are shown in each circuit die104for the sake of example, and it is understood that any desired number of reference features110may be formed therein. Reference features110may exhibit an identical appearance in each circuit die104, regardless of which individual circuit die (e.g., circuit die104A,104B,104C, etc.) is under analysis. Reference feature(s)110may be positioned below an uppermost terminal layer of circuit die104, and thus each reference feature110is depicted with phantom lines in each magnified view ofFIG. 2.

Additional structures may be configured to identify the location of each circuit die104on IC wafer100. Reference features110are shown to have the same position in each circuit die104. To provide an embedded form of identification, each circuit die104may include one or more identification features112positioned in a second (i.e., different) layer as compared to the layer where reference features110appear. Two identification features112are shown in each circuit die104for the sake of example, and it is understood that any desired number of identification features112may be formed therein. To emphasize the location of identification feature(s)112as being in a different layer from reference feature(s)110, identification features112are illustrated with different cross-hatching in circuit dies104A,104B,104C. Identification feature(s)112may each be formed from the same or similar material as reference feature(s)110, e.g., a metal wire, insulator (e.g., one or more masking materials), reflective films, and/or other components capable of being distinguished from other materials in each circuit die104.

The position of identification feature(s)112in embodiments of the disclosure varies across each circuit die104, thereby causing identification feature(s)112to be different in each circuit die104. The varying position of identification feature(s)112in each circuit die104can be expressed in terms of an offset vector from reference feature(s)110, due to the uniform location of reference feature(s)110in each circuit die104. The offset vector may be expressed as a vector or vector sum indicating the positional difference between two locations (i.e., the location of reference feature(s)110) and the location of identification feature(s)112). Magnified circuit dies104A,104B,104C illustrate how identification feature(s)112may distinguish between individual circuit dies104A,104B,104C. The offset vector for identification feature(s)112may be expressed in terms of its magnitude and direction. The magnitude may correspond to an amount of separation between identification feature(s)112and corresponding reference feature(s)110. The direction may correspond to one of several possible paths of separation between feature(s)110,112, e.g., latitudinal and/or longitudinal directions. In the example ofFIG. 2, the offset vector for each set of identification feature(s)112may be expressed as the sum of a latitudinal offset between one reference feature110and one identification feature112, and a longitudinal offset between the other reference feature110and other identification feature112. Beginning with circuit die104A, longitudinal-oriented identification feature112may be laterally separated from longitudinal-oriented reference feature110by a distance vector R (e.g., 100 micrometers (μm)) along the X-axis. Circuit die104A may also include latitudinal-oriented identification feature112separated from latitudinal-oriented reference feature110by a distance vector S (e.g., 100 micrometers (μm)) along Y-axis. Thus, the offset vector between identification features112and reference features110of circuit die104may be expressed as the sum of distance vectors R and S. In this case, the offset vector for identification features112of circuit die104A may not account for any vertical separation between the different layers of IC wafer100where reference features110and identification features112appear.

The positional difference between identification feature112and reference feature110in each circuit die104may be unique to one circuit die104of IC wafer100. The summed offset vector (e.g., latitudinal vector R plus longitudinal vector S) for features110,112in circuit die104A may be specific to only circuit die104A, regardless of whether its components vector R or vector S appear individually in another circuit die104. For instance, in circuit die104B, the offset vector between identification and reference features112,110may be the sum of vector2R (e.g., twice vector R, or approximately 200 μm, along X-axis) in the latitudinal direction, and vector S (e.g., approximately 100 μm) along Y-axis in the longitudinal direction. In circuit die104C, the offset vector between identification and reference features112,110may be the sum of vector R (approximately 100 μm) along X-axis in the latitudinal direction and vector2S (e.g., twice vector S, or approximately 200 μm, along Y-axis) in the longitudinal direction. The resulting vector may preserve the latitudinal or longitudinal orientation of its component vectors, e.g., by being expressed as a resultant vector having a corresponding angle relative to X or Y axis.

Using circuit die104C as an example, the offset vector for identification features112may be converted from vectors R and2S into a single vector having a magnitude of approximately 220 μm and an angle of approximately 63 degrees relative to X-axis, via Euclidean geometry. In other cases, the offset vectors may be computed and expressed in terms of their component vectors, rather than a resultant vector. Although circuit dies104A and104B share a longitudinal component (vector S) in their respective offset vectors, the total offset vector is different in each circuit die. Similarly, circuit dies104A,104C also have distinct offset vectors despite sharing a latitudinal component (vector R) in their respective offset vectors.

Turning toFIG. 3, embodiments of IC wafer100can be structured such that differences in the offset vector for each circuit die104follow a specific pattern. That is, identification features112in successive circuit dies104along one axis may be structured to follow a coordinate system. To illustrate this feature, another circuit die104D is magnified together with circuit dies104A,104B. As shown, each circuit die104A,104B,104D is positioned along a shared axis in the longitudinal direction. Thus, the offset vector between features110,112in each circuit die104A,104B,104D may include a same longitudinal component (i.e., vector S in the Y direction) but different latitudinal components (i.e., vectors R,2R,3R for regions104A,104B,104D, respectively). In this case, each latitudinal vector may increase by a predetermined multiple (e.g., approximately 100 μm) at each successive circuit die along the shared axis. Thus, according to this example, the offset vector for features110,112in circuit die104B may have twice the latitudinal offset distance as the offset vector for features110,112in circuit die104A. In the same example, the offset vector for features110,112in circuit die104D may have three times the latitudinal offset distance as the offset vector for features110,112, in circuit die104A. The amount of change thus may be the same for each successive circuit die104in IC wafer100along a shared latitudinal or longitudinal axis.

FIG. 4illustrates how features110,112may identify the initial location of a particular structure on IC wafer100(FIGS. 1-3), even after IC wafer100has been diced into individual pieces.FIG. 4shows a plurality of circuit dies204, each of which may have been previously diced from a single IC wafer (e.g., IC wafer100ofFIGS. 1-3). The various dies204may then be delivered to customers, third party fabricators, etc. In conventional settings, it may be impossible to determine the original location of a particular circuit die204on its corresponding IC wafer100. In embodiments of the disclosure, however, the various circuit dies204include the same structure of each circuit die104(FIGS. 1-3) of IC wafer100. Thus, it is possible to select one circuit die204for analysis and inspect the location of reference features110and identification features112in each circuit die. Circuit die204A, for example, can be matched with circuit die104A (FIGS. 2-3) by identifying the offset vector as being the sum of vector R in the latitudinal direction and vector S in the longitudinal direction. Circuit die204B similarly can be matched with circuit die104B (FIGS. 2-3) by calculating vectors2R and S therein. Circuit die204D can also be matched with circuit die104D (FIG. 3) by calculating vectors3R and S therein. As noted elsewhere herein, the offset vector between features110,112may correspond to only one circuit die104of a particular IC wafer100. In the case where a particular circuit die204is a functional failing device, it is possible to identify a portion of IC wafer100where the functional failure originated during fabrication. During implementation, a user and/or other recipient of circuit dies204may provide a functional failing circuit die204to the original manufacturer of IC wafer100. The method then allows each failing circuit die204to be traced back to the portion of IC wafer100where it was originally created. The manufacturer may then adjust one or more tools associated with the portion of IC wafer100where circuit die(s)204with functional failures originated.

Turning now toFIG. 5, a cross-sectional view of one circuit die104or circuit die204is shown to better illustrate the location of reference features110and identification features112. As a result of dicing along scribe lines106, the portions of circuit die104depicted inFIG. 5may also be present in corresponding circuit dies204. One scribe line106is shown by example inFIG. 5to illustrate its location in IC wafer(s)100(FIGS. 1-3), but it is understood that scribe lines106will not appear on circuit dies204that have already been diced from IC wafer100. Each circuit die104and/or circuit die204may include, e.g., a plurality of metal wires304, each of which can be composed of any currently known or later-developed electrically conductive material including, e.g., copper (Cu), aluminum (Al), silver (Ag), gold (Au), combinations thereof, etc. Metal wires304can be formed and positioned within a layer of electrically insulative or semiconductive material (e.g., a region of semiconductor material or an electrically insulating dielectric material), such that metal wires304transmit electricity between other electrically conductive structures in contact therewith. Metal wires304positioned within a lowermost terminal metal level M1can extend in a particular direction (e.g., along axis X). Metal wires304positioned within an uppermost terminal metal level MN can similarly extend along axis X in the same direction as metal wire(s)304in lowermost terminal metal level M1, or a different direction. Lowermost terminal metal level M1and uppermost terminal metal level MN can be vertically separated from each other (e.g., along axis “Z” shown inFIG. 5), either as directly adjacent metal levels or with intervening metal and insulator levels positioned therebetween.

Metal wires304within different metal levels (e.g., lowermost terminal metal level M1and uppermost terminal metal level MN) can be electrically connected to each other with vias306each extending vertically between lowermost terminal metal level M1and uppermost terminal metal level MN. Vias306can be composed of the same electrically conductive material(s) as each metal wire304, or can be composed of one or more different conductive materials. Each via306, in an embodiment, can comprise any standard conductive metal (for example, copper) with a lining material (not shown) thereon, such as tantalum nitride.

Lowermost and uppermost terminal metal levels M1, MN can be separated from one another by one or more intervening metal levels308(each labeled, e.g., as M2, M3, M4, M5, MN−1). As suggested by the notations MN and M1, the number of metal levels can vary depending on the chosen implementation and any requirements for back end of line (BEOL) processing. Circuit die104and/or circuit die204can also include interlayer dielectrics310positioned between each intervening metal level308. Each interlayer dielectric310can include one or more electrically insulative substances including, without limitation: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK (a polyarylene ether available from Dow Chemical Corporation), a spin-on silicon-carbon containing polymer material available from JSR Corporation, other low dielectric constant (<3.9) material, or layers thereof. In some embodiments, it is also understood that different interlayer dielectrics310can be composed of different materials with correspondingly different dielectric constants. In one embodiment, one or more vias308can extend from one metal level to an adjacent metal level, such that metal wire(s)304in lowermost terminal metal level M1can be electrically connected to metal wire(s)304in uppermost terminal metal level MN of circuit die104or circuit die204.

In the cross-sectional view of circuit die104or circuit die204, a first layer L1may be fabricated to include reference feature(s)110located near a corresponding metal wire308in the same level (e.g., metal level M4ofFIG. 5). Although metal level M4is shown by example to be level where reference feature(s)110is formed within circuit die104or circuit die204, it is understood that reference feature(s)110may be formed in any one of the various metal levels M1through MN. Any of the metal levels M1-MN may be separately identified as first layer L1, and may include reference feature(s)110therein. A second layer L2of circuit die104or circuit die204may include identification feature(s)112, e.g., formed on interlayer dielectric310of the same level and proximal to metal wire(s)304in the same metal level. As shown, second layer L2with identification feature(s)112therein may be uppermost terminal metal level MN. One benefit to forming identification feature(s)112in uppermost terminal metal level MN may be an improved ability to detect the location of identification feature(s)112in circuit die104or circuit die204. However, it is also understood that second layer L2may refer to any layer where identification feature(s)112appear, e.g., any of the various metal layer M1through MN in a particular circuit die104or circuit die204. To sense the position of reference feature(s)110and/or identification feature(s) located beneath other layers of circuit die104, any currently known or later-developed sensing instruments (e.g., electromagnetic sensors, thermal sensors, etc.) can be used to determine the location of specific underlying materials.

Turning toFIG. 6, process methodologies according to the disclosure may be implemented using an environment400having one or more computing devices402. Computing device402and example components thereof may be implemented in various systems and methods according to embodiments of the present disclosure. As discussed herein, computing device402can be in communication with IC wafer100and/or circuit dies204according to embodiments. To this extent, computing device402can perform various processes to identify a position on IC wafer100where circuit dies204originate, after dicing occurs. Although one IC wafer100and one plurality of circuit dies204are shown for the sake of example, it is understood that environment400may be configured to operate on and/or interact with multiple IC wafers100or pluralities of circuit dies204, sequentially and/or simultaneously.

Environment400shown to include computing device402including a processing unit (PU)404(e.g., one or more processors), a memory406(e.g., a storage hierarchy), an input/output (I/O) component408, an I/O device410(e.g., one or more I/O interfaces and/or devices), a storage system412and a communications pathway414. In general, PU404executes program code, such as a wafer identification system418at least partially fixed in memory406. While executing program code, PU404can process data, which can result in reading and/or writing transformed data from/to memory406and/or I/O device408for further processing. Pathway414provides a communications link between each of the components in computing device402. I/O component408can comprise one or more human I/O devices, which enable a human or system user to interact with computing device402and/or one or more communications devices to enable user(s) to communicate with computing device402using any type of communications link. To this extent, wafer identification system418can manage a set of interfaces (e.g., graphical user interface(s), application program interface, etc.) that enable user(s) to interact with wafer identification system418. Wafer identification system418may include a group of modules420to perform various functions as discussed herein. Further, wafer identification system418can manage (e.g., store, retrieve, create, manipulate, organize, present, etc.) a set of identification data430using any solution. Environment400may also include, e.g., a manufacturing device440in the form of one or more currently known or later developed tools for fabrication of IC wafer(s)100, and/or a dicing system450configured to dice IC wafer100into a plurality of circuit dies206(e.g., along scribe lines106(FIGS. 1-3).

Computing device402can comprise one or more computing devices, including specific-purpose computing articles of manufacture (e.g., computing devices) capable of executing program code, such as wafer identification system418installed thereon. As used herein, it is understood that “program code” means any collection of instructions, in any language, code or notation, that cause a computing device having an information processing capability to perform a particular function either directly or after any combination of the following: (a) conversion to another language, code or notation; (b) reproduction in a different material form; and/or (c) decompression. To this extent, wafer identification system418can be embodied as any combination of system software and/or application software.

Further, wafer identification system418can be implemented using a set of modules420, e.g., a calculator, comparator, a determinator, etc. In this case, each module can enable computing device402to perform a set of tasks used by wafer identification system418, and can be separately developed and/or implemented apart from other portions of wafer identification system418. One or more modules can display (e.g., via graphics, text, sounds, and/or combinations thereof) a particular user interface on a display component such as a monitor. When fixed in memory406of computing device402that includes PU404, each module can be module a substantial portion of a component that implements the functionality. Regardless, it is understood that two or more components, modules and/or systems may share some/all of their respective hardware and/or software. Further, it is understood that some of the functionality discussed herein may not be implemented or additional functionality may be included as part of computing device402.

As noted herein, wafer identification system418may include or otherwise have access to various forms of identification data430. Identification data430may be included within memory406as shown inFIG. 6, and in addition or alternatively may be provided within storage system412and/or other components within environment400or communicatively connected thereto. An IC wafer map432of identification data430may provide a listing, graphical depiction, etc., of all circuit dies104(FIGS. 1-3, 5) in one IC wafer100. Identification data430may also include, e.g., an offset index434correlating each circuit die104with the corresponding offset vectors for reference feature(s)110(FIGS. 1-5) and identification feature(s)112for each circuit die104in IC wafer100. As discussed elsewhere herein, identifying circuit die(s)204as corresponding to circuit die(s)104in one IC wafer may include measuring the offset vector of circuit die(s)204under analysis. These measurements may be take the form of measured offset(s)436in identification data430.

When computing device402comprises multiple computing devices, each computing device may have only a portion of wafer identification system418(e.g., one or more modules) thereon. However, it is understood that computing device402and wafer identification system418are only representative of various possible equivalent computer systems that may perform a process described herein. To this extent, in other embodiments, the functionality provided by computing device402and wafer identification system418can be at least partially implemented by one or more computing devices that include any combination of general and/or specific purpose hardware with or without program code. In each embodiment, the hardware and program code, if included, can be created using standard engineering and programming techniques, respectively.

Regardless, when computing device402includes multiple computing devices, the computing devices can communicate over any type of communications link. Further, while performing a process described herein, computing device402can communicate with one or more other computer systems using any type of communications link. In either case, the communications link can comprise any combination of various types of wired and/or wireless links; comprise any combination of one or more types of networks; and/or use any combination of various types of transmission techniques and protocols.

Referring concurrently toFIGS. 3-7, the disclosure includes various methodologies for manufacturing IC wafers100for identification, and/or identifying portions of IC wafer100where circuit dies204originate. Viewed generally, processes according to the disclosure may include methods for creating IC wafer100with identifying structures (e.g., reference features110and identification features112) therein for future analysis, and/or related methodologies for identifying the original location of a circuit die204in IC wafer100after dicing has completed. At process P1, the disclosure may include fabricating wafer100to include one or more reference features110in a first layer of each circuit die104, and one or more identification features112in a second layer of each circuit die104. As noted elsewhere herein, reference feature(s)110may have the same separation distance from corresponding scribe lines106in each circuit die, while identification feature(s)112may have a different offset vector from reference feature(s)110in each circuit die104. In conventional settings, manufacturing device440may be configured to create a uniform product design for the functional elements in all circuit dies104of IC wafer100. As noted elsewhere herein, forming IC wafer100according to the disclosure includes forming identification features112at different locations in each circuit die104. To form identification features112at a different location in each circuit die104, modules420of computing device402may automatically adjust the position where identification feature(s)112are formed in each circuit die, e.g., by adjusting the position of one or more masks, deposited metals, etc., along a set pattern. Such patterns, e.g., increasing the separation distance of identification feature(s)112from associated reference feature(s)110in each circuit die104by a predetermined multiple, e.g., as shown inFIG. 3and discussed elsewhere herein. Where identification feature(s)112are formed by deposition, the adjusting may be applied to a deposition tool for creating one or more metals in IC wafer100. In cases where identification feature(s)112are formed by combinations of masking, etching, etc., modules420of computing device402may adjust the position of such components to modify the location of identification feature(s)112. In all other respects, the fabrication of IC wafer100may proceed substantially in accordance with conventional wafer fabrication techniques. Additional sub-processes of process P1are shown inFIG. 8and discussed elsewhere herein.

Upon completion of process P1, the method may conclude (“Done”) in cases where IC wafer100is diced in an independent process. In other cases, the flow may continue to process P2of using dicing system450to dice IC wafer100into multiple circuit dies204. The dicing of IC wafer100may proceed substantially in accordance with conventional wafer dicing, despite the presence of reference features110and identification features112in each circuit die104. More specifically, reference features110and identification features112may not be located near or along scribe lines106, and thus will not affect the dicing of IC wafer100into circuit dies204.

Whether IC wafer100is diced into circuit dies204as part of a single process for identifying circuit dies, or a preliminary operation independent from identifying each circuit die, the disclosure may include process P3of identifying the original location of one or more circuit dies204on IC wafer100. Specific techniques, sub-processes, etc., for identifying the original location of circuit die(s)204on IC wafer100in process P3are shown in further detail inFIG. 9and described elsewhere herein. Identifying the original location of each circuit die204on IC wafer100may include, for example, measuring the offset vector for identification feature(s)112on each circuit die204and comparing the measured value to offset index434, and then determining the location based on which offset distance of index434matches the measured value. The flow may then conclude (“Done”) for the circuit dies204being identified.

Referring concurrently toFIGS. 3-6 and 8, an example group of sub-processes for process P1of fabricating a wafer with reference features110and identification features112in circuit dies104is provided. In a preliminary process P1-1, the disclosure may include defining the various circuit dies104of IC wafer100. Process P1-1is shown in phantom to emphasize that this process may not be included in all instances of process P1and/or may be executed by other entities. Process P1-1may occur, e.g., prior to the fabrication of IC wafer100by defining the location of scribe lines106in a design for IC wafer100and circuit dies204. Scribe lines106may also be formed directly on IC wafer100after the fabrication of IC wafer100and prior to dicing.

Regardless of how circuit dies104are defined, process P1-2according to the disclosure may include forming first layer L1(e.g., any predetermined metal level such as one or more of metal levels M1-MN ofFIG. 5) with reference feature(s)110therein. As noted previously, reference feature(s)110may have a uniform separation distance from corresponding sets of scribe lines106in each circuit die104of IC wafer100. Continued fabrication of IC wafer100can then proceed to process P1-3of forming second layer L2(e.g., any other predetermined metal level such as one or more of metal levels M1-MN ofFIG. 5) with identification feature(s)112therein.

After completing processes P1-2and P1-3, continued fabrication of IC wafer100may optionally include fabricating all other layers where features110,112do not appear. In alternative implementations, the various remaining layers may be formed before the layers designated as being first layer L1and second layer L2, and/or between the forming of first layer L1and second layer L2. In still further embodiments (e.g., forming second layer L2as lowermost terminal metal level M1), second layer L2may be formed before first layer L1. In any case, the method may include ending the fabrication of IC layer100in process P1-5, e.g., after forming the functional components and features110,112which constitute each circuit die104of IC wafer100. Upon completing the fabrication of IC wafer100, modules420of wafer identification system418can store IC wafer map(s)432for future use as identification data430. The generating and/or storing of IC wafer map(s)432for subsequent use may also occur as part of one of processes P1-1through P1-4, or a separate operation. In cases where another entity is responsible for identifying circuit dies204, the flow may conclude (“Done”) after process P1-5. In other situations, the method may continue to process P2of dicing IC wafer100into circuit dies204to be identified.

Referring concurrently toFIGS. 3-6 and 9, embodiments of the disclosure may include one or more sub-processes for identifying the original location of each circuit die204on IC wafer100. In process P3-1, for example, one or more circuit dies204(containing, e.g., one or more functional failures such as manufacturing defects or anomalies) may be selected for analysis based on examination and/or testing. At process P3-2, a user may examine circuit die(s)204under analysis (e.g., manually or automatically with the assistance of software, tools, etc.) to measure the offset vector between identification feature(s)112and reference feature(s)110located on circuit die(s)204under analysis. According to an example, an electromagnetic imaging tool may detect the position of one reference feature110and one identification feature112extending in parallel with the reference feature110. The imaging tool may then, e.g., with the aid of modules420, measure, calculate, etc., the separation distance between identification feature112and reference feature110along one axis. The imaging tool may subsequently, or concurrently, detect the position of other reference features110with different orientations and identification features112which share the different orientation, to calculate a separation distance between such features110,112along a different axis. The various differences in position for each pair of features110,112can then be combined with each other to yield an offset vector for one circuit die204under analysis. As noted elsewhere herein, the offset vector may indicate a separation distance between identification feature(s)112and reference feature(s)110, including both an amount of separation and a separation orientation (e.g., latitudinal or longitudinal separation) between features110,112on circuit die(s)204. The measured offset vector(s) for each circuit die204may be stored, e.g., in memory406, as measured offset(s)436in identification data430.

Further processes may include using measured offset(s)436and other forms of identification data430to determine a particular circuit die104from which circuit die204was created. At process P3-3, the method may include comparing measured offset(s)436for circuit dies204with known offset vectors in offset index434. More specifically, comparator modules420of wafer identification system418can match one or more measured offset(s)436with their corresponding values in offset index434. To account for errors in measurement and/or computation, a calculator of modules420may apply one or more tolerance thresholds in the comparison and/or find a best fit match between measured offset(s)436and one or more offset vectors in offset index434. In any case, process P3-3may pair each measured offset436to a corresponding offset vector in offset index434, e.g., by identifying offset vectors within a margin of error for the measured offsets436for a particular IC die204under analysis. Continuing to process P4-4, the method may include identifying the original location of each circuit die204on IC wafer100. According to an embodiment, IC wafer map(s)432of identification data430may include corresponding offset vectors for circuit die104of IC wafer100.

This formatting may allow each measured offset436previously matched with an offset vector in offset index434to automatically be matched with a particular circuit die104. At this point, modules420can communicate (e.g., via I/O device410) which circuit die(s)104of IC wafer100originated circuit die(s)204. In cases where a particular anomaly detected on one circuit die204, a portion of IC wafer100where circuit die204originated can be identified as originating the functional failure of a device. The manufacturing tools, design, and/or other components associated with such portions of circuit die204may then be modified to correct errors, compensate for unanticipated operating characteristics, etc. Subsequently, the process may end (“Done”) with respect to the particular circuit die(s)204under analysis. It is again noted that processes P1and P3may each take the form of an independent methodology, process, etc., to be implemented by independent entities, or may be implemented together with process P2as portions of a single, unified process.