Coordinated power sequencing to limit inrush currents and ensure optimum filtering

A regulated power supply apparatus and method is provided. A converter circuit is configured to generate a regulated voltage signal from an unregulated voltage signal. A power sequencing circuit includes an unregulated voltage source input terminal and is configured for coupling an unregulated voltage signal to an unregulated voltage signal input terminal of the converter circuit. The power sequencing circuit includes an enable output coupled to the enable signal input terminal and includes a power limiting circuit and a trigger circuit. The power limiting circuit includes a first cascade of discrete analog components as controls for a first switching element and the trigger circuit includes a second cascade of discrete analog components as controls for a second switching element. The first cascade is configured as a charge control circuit for controlling a rate of charge of a first filter network and includes a zener diode coupled in parallel. The second cascade is configured as a detector of voltage levels and generates the enable signal. The first and second switching elements are semiconductor switches. The first filter network is coupled upstream of the converter circuit and a second filter network is coupled downstream. In an exemplary embodiment, the converter circuit is a DC to DC bus converter circuit and the regulated power supply apparatus is a fan controller circuit.

FIELD OF THE INVENTION

The present invention relates to the field of power supplies. More particularly, the present invention relates to a power sequencing circuit for a power supply apparatus.

BACKGROUND

In many applications a voltage regulator is required to provide a voltage within a predetermined range. Some circuits are subject to uncertain and undesirable functioning and even irreparable damage if an input power supply falls outside a certain range.

Many power supplies include power sequencing circuits to control the initial stages of a power supply during turn-on. Power sequencers help control high inrush current and limit power converter turn-on noise. Conventional power sequencing circuits provide a converter enable signal for enabling power converter circuits included within the power supply. The disadvantage of conventional power sequencers include that the charging control signal is either on or off and when turning on does not limit inrushes of current experienced by power supply input circuits. The result is that the input inrush of current is delayed but peak amplitude and spikes are not otherwise limited.

Conventional power sequencers for DC input power supplies do not provide a way to delay the power converter turn-on until the charging of the upstream filter capacitor(s) is actually complete. This is because the conventional sequencers provide only a time-based delay function that does not account for the effect of different input voltages on the charging time of the upstream filter capacitor(s).

Conventional power sequencers also do not limit inrush current for a wide range of input voltages and function optimally only in a narrow range of input voltages. In addition conventional sequencers typically use costly power sequencing integrated circuits (ICs). IC sequencers are difficult to debug and require trial and error in the lab to find the optimal solution.

Accordingly, it is desirable to have a simple discrete analog control circuit that would provided a power sequencing solution that is much more economical, efficient and better suited for limiting inrush current to DC input power converters.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the present invention, a regulated power supply apparatus is provided. The apparatus includes a converter circuit configured to generate a regulated AC or DC output voltage signal from an unregulated DC input voltage signal. The unregulated input voltage signal is generated from an unregulated DC voltage source. The converter circuit includes an unregulated voltage signal input terminal and an enable signal input terminal. A power sequencing circuit includes an unregulated DC voltage source input terminal and is configured for coupling an unregulated voltage signal to the unregulated voltage signal input terminal. The power sequencing circuit includes an enable output coupled to the enable signal input terminal. The power sequencing circuit includes a power limiting circuit and a trigger circuit. The power sequencing circuit is configured to limit spikes of inrush current such as occur during hot swapping to only a few amps, for example 3 or 4 amps. Inrush current without the present power sequencing circuit typically can range between 1000 to 2000 amps for durations of 100s of microseconds.

The power limiting circuit includes a first cascade of discrete analog components as controls for a first switching element and the trigger circuit includes a second cascade of discrete analog components as controls for a second switching element. The first cascade includes a resistor and a capacitor in parallel coupled between a first and a second terminal of the first switching element. The first cascade is configured as a charge control circuit in the power limiting circuit for controlling a rate of charge of a first filter network. The first cascade includes a zener diode coupled in parallel. The second cascade includes a resistor and a capacitor in parallel coupled between a first and a second terminal of the second switching element. The first and second switching elements are semiconductor switches.

The first filter network is coupled upstream of the converter circuit and a second filter network may optionally be coupled downstream of the converter circuit. In an exemplary embodiment, the converter circuit is a DC to DC bus converter circuit and the regulated power supply apparatus is a fan controller circuit.

In other aspects of the present invention, a method of regulating a power supply apparatus in generating a regulated voltage signal is provided.

Other features of the present invention will become apparent from consideration of the following description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

In the following description, numerous details and alternatives are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.

Turning toFIG. 1, a functional block diagram is shown for a regulated power supply apparatus100according to an embodiment of the invention. The apparatus100is configured as a buck-type power supply, which includes a power sequencing function. The apparatus100facilitates proper sequencing during turn-on and limits voltage and current spikes during turn-on and during normal operation. The apparatus100generally includes an unregulated voltage source120, which may include an AC to DC converter, a motor/generator and/or an array of storage batteries, coupled with a power sequencing circuit140that is coupled with a converter circuit160. The converter circuit160is coupled to an output circuit or DC load180.

The unregulated voltage source120generally comprises a DC voltage source. The unregulated voltage source120can include an AC input terminal coupled with a bridge rectifier (not shown). The unregulated voltage source120can be configured to receive an AC input signal from an AC line or AC source. In one embodiment, the AC input signal can have a voltage potential at a “low-line” range (85VAC-132VAC). Alternatively, the AC input signal can have a voltage potential at a “high-line” (180VAC-264VAC) range. The AC input signal can be coupled from the AC input terminal to the bridge rectifier. The bridge rectifier can generate an unregulated voltage signal. In an exemplary embodiment, the unregulated voltage signal comprises a DC voltage signal. The unregulated voltage signal can be coupled to the power sequencing circuit140.

The power sequencing circuit140receives the unregulated voltage signal and generates an enable signal ENB that is coupled to the converter circuit160. The power sequencing circuit140limits current spikes during apparatus100turn-on. The power sequencing circuit140delays turn-on of the converter circuit160until turn-on voltage and current have properly stabilized. The power sequencing circuit140couples the unregulated voltage signal from the unregulated voltage source120to the converter circuit160. The power sequencing circuit140can include EMI filtering to reduce turn-on noise of the converter circuit160. The power sequencing circuit140is configured to limit spikes of inrush current such as occur during hot swapping to only a few amps, for example 3 or 4 amps. The spikes of inrush current are limited for a duration of approximately one microsecond. Inrush current and spikes without the present power sequencing circuit140typically can range between 1000 to 2000 amps for durations of 100s of microseconds.

The converter circuit160receives the enable signal from the power sequencing circuit140. The enabled converter circuit160receives the unregulated voltage signal from the power sequencing circuit140and then the converter circuit160generates a regulated voltage signal. The converter circuit160can be configured as a step down converter circuit. The converter circuit160couples the regulated voltage signal to the load circuit180. In an exemplary embodiment, a downstream filter can be included downstream of the converter circuit160coupled between the converter circuit160and the load circuit180. In one embodiment the load circuit180can be a logic board within a telecommunications equipment chassis. In another embodiment, the load can be a fan or fan tray such as is commonly used to cool a telecommunications equipment shelf or chassis. Other embodiments are not excluded.

FIG. 1Ashows an functional block diagram of an exemplary power sequencing circuit140. The power sequencing circuit140generally includes a power limiting circuit141coupled with a filter circuit146and a bus converter turn-on or trigger circuit148coupled with the filter circuit146. The power limiting circuit141can include a clipping circuit142coupled with a charging control circuit144. The clipping circuit142limits voltage spikes and current spikes applied to the low voltage devices in the charging control circuit144to a specified voltage level. The charging control circuit144is configured to control a flow of in rush current to limited levels by controlling a rate of charge of an input capacitor (FIG. 2). The charging control circuit144also controls the rate of charge of the filter circuit146. The filter circuit146is configured to reduce EMI noise generated during turn-on and operation of the bus converter circuit160. The filter circuit146can also remove undesirable harmonic noise contained in the AC input signal.

The trigger circuit148is coupled with the filter circuit146and includes an enable signal output terminal. The trigger circuit148couples the unregulated voltage signal to the converter circuit160. The trigger circuit148detects a level of charge of capacitive elements of the filter circuit146. The trigger circuit148generates the enable signal when the capacitive elements of the filter circuit146have fully charged. The enable signal is then coupled to the converter circuit160.

Turning toFIG. 2, a schematic diagram is shown for a regulated power supply apparatus200, which includes a novel power sequencing circuit. The apparatus200generally includes an unregulated voltage source202, which may include an AC to DC converter, a motor/generator and/or an array of storage batteries, coupled with a power sequencing circuit230that is coupled with a converter circuit260that is coupled with a load circuit280. The apparatus200can include an output filter270coupled downstream of the converter circuit260.

The unregulated voltage source202generally comprises a DC voltage source. The unregulated voltage source202can include an AC input terminal (not shown) coupled with a bridge rectifier (not shown), it may optionally include a motor/generator and/or an array of storage batteries. The unregulated voltage source202can be configured to receive an AC input signal from an AC line or AC source. In one embodiment, the AC input signal can have a voltage potential at a “low-line” range (85VAC-132VAC). Alternatively, the AC input signal can have a voltage potential at a “high-line” (180VAC-264VAC) range. The AC input signal can be coupled from the AC input terminal to the bridge rectifier. A fusible link or fuse element can be coupled between the AC input terminal and the bridge rectifier. The bridge rectifier can generate an unregulated voltage signal. In an exemplary embodiment, the unregulated voltage signal comprises a DC voltage signal of 32-75 volts DC at the output of an array of storage batteries in a telecommunications equipment facility. In still another embodiment, the unregulated voltage signal comprises a DC voltage signal of 48 volts DC which is the standard operating voltage of the array of batteries. The unregulated voltage signal can be coupled to the power sequencing circuit230.

The power sequencing circuit230generally comprises a power limiting circuit141coupled with a filter circuit146that is coupled with a bus converter turn-on or trigger circuit148. The power limiting circuit141comprises coupling a cathode of each semiconductor diode204,206to an input terminal ‘Vs’. In an exemplary embodiment, the semiconductor diode204comprises a zener diode. The anode of the semiconductor diode204is coupled to a first terminal of a resistor208. The anode of the semiconductor diode206is coupled to a first terminal of a resistor212. A second terminal of the resistor208is coupled with a first terminal of a resistor210. A second terminal of the resistor212is coupled with a first terminal of an input capacitor214and the first terminal of the resistor210. A cathode of a semiconductor diode218is coupled with the first terminal of the input capacitor214and a first terminal of a first switching element220. In an exemplary embodiment, the semiconductor diode218comprises a zener diode. An anode of the semiconductor diode218is coupled to a second terminal of the first switching element220and coupled to a second terminal of the resistor210and a second terminal of the input capacitor214. The first switching element220comprises a semiconductor switch. Any number of semiconductor switches known to a person of skill in the art can be used. In an exemplary embodiment, the first switching element220comprises a MOSFET (metal-oxide-semiconductor field-effect transistor) transistor. In the exemplary embodiment the values of the zener diodes204,218, the resistors208,210and the capacitor214are chosen to control and protect the gate charge of the MOSFET220so that it ramps up in a controlled manner through its activation phase of the controller operation and discharges rapidly during the shut-down phase. The operation of this circuit is similar to that described in co-pending patent application Ser. No. 11/938,098, filed on or about Nov. 9, 2007, and entitled “POWER FILTER,” which is hereby incorporated by reference in its entirety. It must be understood that the series circuit path through the zener diodes204,218interacts with the active gate voltage threshold of the switching element220to determine an input voltage range below which the switching element220will be turned off, and above which the switching220element will be turned on. The rate at which the switching element220turns on is controlled by the zener diode204, the resistors208,210and the capacitor214. The zener diode218limits the maximum control voltage applied to the switching device220. The diode206and resistor212serve to rapidly discharge capacitor214when the input voltage drops below a defined threshold, thereby turning off the switching element220.

The filter circuit146comprises a first terminal of an inductive element224coupled with the cathode of the semiconductor diode206and coupled with a first terminal of a filter capacitor222. A second terminal of an inductive element224is coupled with a first terminal of a filter capacitor226and coupled with a first terminal of a filter capacitor232. A second terminal of the filter capacitor222is coupled with a first terminal of an inductive element228and coupled with a third terminal of the first switching element220. The second terminal of the inductive element228and coupled with a second terminal of the filter capacitor226and a second terminal of the filter capacitor232.

The trigger circuit148comprises a first terminal of a resistor236coupled with the cathode of the semiconductor diode218and a second terminal of the resistor236coupled with an anode of a semiconductor diode238. A first terminal of a resistor242is coupled with the second terminal of the inductive element224and coupled with a first terminal of a resistor248. A second terminal of the resistor242is coupled with a cathode of a semiconductor diode244. A cathode of the semiconductor diode238and an anode of the semiconductor diode244are each coupled with a first terminal of a second switching element250. A second terminal of the resistor248is coupled with a second terminal of the second switching element250. A first terminal of a resistor240and a first terminal of a capacitor246are also each coupled with the first terminal of a second switching element250. A first terminal of the resistor240is coupled with the second terminal of the inductive element228and coupled with a second terminal of the capacitor246. The second terminal of the capacitor246is coupled with a third terminal of the second switching element250. The second switching element250comprises a semiconductor switch. Any number of semiconductor switches known to a person of skill in the art can be used. In an exemplary embodiment, the second switching element250comprises a MOSFET transistor. The connection between the gate of the first switching element220in the charging control circuit144and resistor236in the trigger circuit148coordinates the behavior between these two control elements to create the desired sequence of operation. The behavior of the combined circuits ensures that the second switching element250does not turn-on until after the first switching element has fully turned-on and the voltage across the capacitors222,226,232in the filter circuit146is close to the average unregulated input voltage. When the charge voltage in the filter circuit146approaches its stable value, capacitor246in the trigger circuit148will begin to charge. After the charging delay of capacitor246the control gate to switching element250is activated.

The converter circuit260comprises an isolated buck-type converter and generally includes a switching circuit262coupled with an isolation transformer264. The isolation transformer264is coupled with the load circuit280. The converter circuit260includes an unregulated voltage signal input terminal Vin, an enable signal input terminal ‘ENB’ and a regulated signal output terminal ‘Vout’. The second terminal of the inductive element224is coupled with a high line of the unregulated voltage signal input terminal Vin. The second terminal of the second switching element250is coupled with the enable signal input terminal ENB. The third terminal of the second switching element250is coupled with a low line of the unregulated voltage signal input terminal Vin.

The converter circuit260includes the high and low line unregulated voltage signal input terminals Vin+, Vin− coupled with the switching circuit262which is coupled with the isolation transformer264. The switching circuit262comprises a semiconductor switch. Any number of semiconductor switches known to a person of skill in the art can be used. In an exemplary embodiment, the switching circuit262comprises a MOSFET transistor. The converter circuit260can be provided with several different configurations. In an exemplary embodiment, the converter circuit260can be configured as a single switch forward converter. A person of skill in the art will appreciate that a two-switch and a four-switch configuration can be substituted for the switching circuit262. For example, the two-switch configuration (not shown) can comprise a half-bridge converter or even a push-pull converter. The four switch configuration (not shown) can comprise a full-bridge converter.

The isolation transformer264includes a primary264A and a secondary264B. A turns-ratio of the isolation transformer264can be a value that depends on a voltage value chosen for an output voltage Vout. A first terminal of the secondary264B is coupled with an output filter or downstream filter circuit270. A second terminal of the secondary264B is also coupled with the downstream filter circuit270.

Although the converter circuit260in the embodiment is described as an isolating buck-type converter, the reader will understand that any type of isolating or non-isolating DC converter or regulator can be employed when practicing the invention.

The downstream filter circuit270includes a first terminal of the filter capacitor272and a first terminal of the filter capacitor274coupled with a high line of the regulated signal output terminal. A second terminal of the filter capacitor272and a second terminal of the filter capacitor274are coupled with a low line of the regulated signal output terminal Vout−. In an alternative embodiment, the downstream filter circuit270can include inductive elements. In still another embodiment, the downstream filter circuit270can include additional filter capacitors. The value of the filter capacitors can be chosen depending on the application and desired value for Vout.

The load circuit280is coupled with the downstream filter circuit270and can comprise a variety of DC loads. In an exemplary embodiment, the load circuit comprises a fan or fan tray used for collong electronics equipment. In another exemplary embodiment the load circuit consists of a plurality of logic elements packaged as a circuit board or circuit pack.

The converter circuit260includes a pulse width modulation (PWM) module (not shown). The PWM module is used in controlling a duty cycle of the switching circuit262. The PWM module regulates the output voltage Vout by sampling the output voltage Vout and adjusting the duty cycle of the switching circuit262to a higher or lower frequency until the output voltage Vout is approximately equal to a target voltage for Vout. A feedback loop (not shown) can be utilized to provide sensing of the output voltage Vout to the PWM module. PWM modules are commonly used in this manner and a person of skill in the art will appreciate this means as well as other means to regulate the output voltage Vout.

FIG. 2Aillustrates a plot of a sample spice trace for the power supply apparatus200. The initial unregulated voltage signal Vs and an unregulated current signal ‘Is’ can be measured at the input terminal Vs. The unregulated voltage signal Vs increases rapidly at turn-on and the unregulated current signal Is lags behind Vs in relation to time. Initial spikes in voltage and current of Vs and ‘Is’ can be limited and filtered by the power sequencing circuit230. An unregulated voltage signal Vin and an unregulated current signal Iin can be measured at the unregulated voltage source input terminal Vin. The power sequencing circuit230provides a time delay to allow Vin and Iin to stabilize before the converter circuit is enabled. In an exemplary embodiment, the unregulated voltage signal comprises 32-75 volts DC and the unregulated current signal Is comprises 10-15 amps. A regulated voltage signal and current Vout, Iout can be measured at the high and low line of the regulated signal output terminal Vout. The converter circuit260operates to smooth and reduce voltage ripples in the unregulated voltage and current signals Vin, Iin. In an exemplary embodiment, the regulated voltage signal Vout comprises 24 volts and the regulated current signal Iout comprises 3.5 amps.

Turning toFIG. 3, with reference toFIG. 2, a process flow diagram300is shown for a method of regulating a power supply apparatus200in accordance with an embodiment of the invention. The power supply apparatus200is provided as a power sequencing regulated power converter. The method begins at the step305. At the step310an unregulated voltage signal is received at the unregulated voltage signal input terminal of the power sequencing circuit230. The power sequencing circuit230includes the power limiting circuit141, the filter circuit146and the trigger circuit148. The power sequencing circuit230includes an enable output and is configured to generate an enable signal.

At the step320, the power sequencing circuit230couples the unregulated voltage signal to an unregulated voltage signal input terminal of the converter circuit260. The converter circuit comprises the switching circuit262and the isolation transformer264. The converter circuit260is configured to generate the regulated voltage signal from the unregulated voltage signal that is generated from the unregulated voltage source202. The converter circuit260includes the unregulated voltage signal input terminal Vin, the enable signal input terminal ENB and the regulated signal output terminal Vout.

At the step330, an input current of the unregulated voltage signal is controlled and coupled to the converter circuit260using the power limiting circuit141. The power limiting circuit141includes the first cascade of discrete analog components as controls for the first switching element220. In an exemplary embodiment, the first cascade and the second cascade of discrete analog components are interconnected and configured so that they operate sequentially. The trigger circuit148includes the second cascade of discrete analog components as controls for the second switching element250. The power limiting circuit141reduces power spikes received by the converter circuit260. The power limiting circuit141also includes a charge control circuit comprising the first cascade of discrete analog components that controls a rate of charge of the filter circuit146with use of the input capacitor214. A charge rate of the input capacitor is dependent on the value chosen for the input capacitor214. The power sequencing circuit230is configured to limit spikes of in rush current such as occur during hot swapping to only a few amps, for example 3 or 4 amps. The spikes of in rush current are limited for a duration of approximately one microsecond. In rush current without the present power sequencing circuit230typically can range between 1000 to 2000 amps for durations of 100s of microseconds.

At the step332, the enable signal is generated to the converter circuit260using the power sequencing circuit230. The enable signal is generated when the trigger circuit148has detected a predetermined voltage value of the charging filter circuit146. The predetermined voltage value is reached when the filter circuit146has fully charged. The predetermined voltage value can be set depending on the values chosen for the components of the second cascade of discrete analog controls.

At the step335, the regulated voltage signal is generated as an output signal using the converter circuit260. The converter circuit260receives the enable signal from the trigger circuit148at the enable signal input terminal ENB. The regulated voltage signal is received at the downstream filter circuit270and the load circuit280.

At the step340, the first cascade of the discrete analog components is configured such that the input capacitor214rapidly discharges when the value of an input voltage of the unregulated voltage source202drops below a defined threshold. When the input voltage drops below the defined threshold, the first switching element220of the power limiting circuit141is turned off. The rapid discharge of capacitor214ensures the power limiting circuit141has very little delay in turning off. The step340serves to both rapidly discharge the filter capacitance of the filter circuit146through the bus converter260to the load280and then to shut-down the bus converter280. When the unregulated voltage source202input voltage drops below the operating range there are two important reasons for rapidly discharging the filter capacitance of the filter circuit146. Safety, since if the fan tray or circuit pack is removed from the shelf or chassis it is important to prevent hazardous voltages on an exposed module associated with the removed fan tray. Reliability, since it is important to prevent the load280from operating outside its proper operating range. The method terminates at the step350.