Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics

An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

BACKGROUND

In mixed mode integrated circuits with large analog blocks, such as high-speed serial interfaces, there is a need to analyze the health of the analog blocks of the integrated circuit while in operation. The joint test action group (JTAG) standard can be used to test a failure along the connectivity path between chips. However, this is limited to the interfacing circuits of the integrated circuit, specifically the input/output circuitry and routing, and does not provide access to voltages inside an analog block. Another drawback of the JTAG standard is the use of a scan chain which can only read out the voltages in a fixed sequence. The scan chain mechanism does not generally help test for timing or other dynamic operational errors that may occur. Additionally, it is desirable to keep the system running in place and being able to debug the system without having to shut it down. Faulty components in a system are often tested one at a time, which requires bringing down the system and debugging each component separately.

SUMMARY

Broadly speaking, the present invention fills these needs by providing a method and apparatus for selectively accessing analog voltages inside an analog block. It should be appreciated that the present invention can be implemented in numerous ways, including as a method, a system, or a device. Several inventive embodiments of the present invention are described below.

In accordance with one aspect of the invention, an integrated circuit capable of monitoring analog voltages inside an analog block, is provided. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs the selected analog voltage from the analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine. The analog state machine provides selection bits to the analog test multiplexer, enabling random or selective access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

In accordance with another aspect of the invention, a method of selectively analyzing analog voltages inside an analog block is detailed. The method begins when the analog test multiplexer receives the analog voltages from the analog block. In the next operation, the analog test multiplexer receives a selection signal from an analog monitor state machine. The selection signal from the analog monitor state machine selectively accesses any of the analog voltages connected to the voltage input of the analog test mux. The method also converts the selected accessed analog voltage from the analog test mux into a digital representation.

DETAILED DESCRIPTION

The following embodiments describe an apparatus and method for selectively accessing analog voltages inside an analog block. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

In one embodiment of the present invention described below, an analog test module with an analog test multiplexer and analog to digital converter enables selective probing into the analog portions of a mixed mode integrated circuit. The analog test module allows monitoring of the analog voltages inside the analog block to identify potential problems. This level of testing can be considered as a layer of diagnostic capability, which can be done in real time without interrupting operation of a system. The embodiments eliminate the need for a specialized tester, thereby enabling point of use testing with the system running. The critical analog voltages are predetermined and the required connections are added to the analog block in the integrated circuit.

FIG. 1illustrates a top view of an integrated circuit utilizing circuitry capable of monitoring analog voltages inside an analog block in accordance with one embodiment of the present invention. An integrated circuit100, such as a processor or an application specific integrated circuit (ASIC), consists of several analog blocks102, as well as the core logic104of the integrated circuit100. The analog blocks102may contain high speed interfaces, transceivers, as well as phase lock loops (PLL). In one embodiment, an analog test module110providing access to analog voltages inside the analog blocks102is contained in the core logic104of the integrated circuit100. The input/output (I/O) ring106contains circuits which transmit and receive signals between the core logic104and the analog blocks102, and the rest of the system. One skilled in the art will appreciate that any known I/O standards may be supported by the I/O circuitry, such as LVDS, TTL, etc. standards.

FIG. 2illustrates an analog test module enabling selective access to analog voltages inside an analog block in accordance with one embodiment of the present invention. The analog test module110includes an analog test multiplexer (mux)112and an analog monitor state machine114. The analog test multiplexer112multiplexes a plurality of analog voltages from an analog block102and enables random access to each of the analog voltages inside the analog block102. The voltage inputs122of an analog test multiplexer112are coupled to the plurality of voltages inside the analog block102. For example, the voltage inputs122of the analog test mux112may be connected to a loop filter control voltage. In another example, the analog test mux voltage inputs122may be coupled to a current source diode. The analog test multiplexer112also receives a plurality of selection bits, which dynamically control the analog test mux112. The output from the analog output124from the analog test multiplexer112can be processed to check if the analog voltages are within specified tolerances.

The analog monitor state machine114contains a digital logic circuit to generate an address associated with an analog voltage inside the analog block102and generates the plurality of selection bits from the address. The analog monitor state machine114transmits the selection bits to the analog test multiplexer112using a selection bus120, which is M bits wide. The number of bits of the selection bus120, M, corresponds to the number of selection bits needed to select any of the analog voltages inside the analog block102. In one embodiment, the analog monitor state machine114can be implemented off-chip via a microprocessor. In another embodiment, the analog monitor state machine114may have a control input118enabling user selection of one of the plurality of analog voltages to be transmitted to the output. In one example, a user may desire to monitor a specific voltage in the analog block102. By transmitting a signal to the control input118of the analog monitor state machine114, the user can configure the analog monitor state machine114to select a specific analog voltage to send to the output124and override the default sequence of accessing the analog voltages.

In one embodiment of the analog test module110, the analog test module110further includes an analog to digital converter (ADC)116converting the selected analog voltage from the analog test multiplexer112into a digital representation. The analog to digital converter116converts the analog voltage to a digital signal which can be processed by the system. In one embodiment, the analog to digital converter is located off-chip and the digital output of the analog to digital converter116routed back to the integrated circuit and is connected to the core logic of a programmable logic device, such as a field programmable gate array (FPGA). The digital representation from the analog to digital converter116is transmitted to the analog monitor state machine114, which monitors each analog voltage inside the analog block102in a default sequence. In another embodiment, the digital representation from the analog to digital converter116is transmitted to an input/output ring for analysis outside the integrated circuit.

In another embodiment, the analog test module110further includes a lookup table with pre-determined allowed values for each of the plurality of analog voltages inside the analog block. The digital representation of the values of analog voltages inside the analog block is compared to pre-determined allowed values or range stored in the lookup table. A pre-determined allowed value is associated with each analog voltage inside the analog block102, where each allowed value is indicative of proper operation of the circuits in the analog block102. For instance, a circuit designer designing an amplifier inside the analog block102to properly operate under certain bias conditions can store the bias conditions in the lookup table for real time comparison with the measured bias values from the analog block102.

In another example, the control voltage of a phase lock loop can be accessed to verify if the phase lock loop control voltage is stable. If the phase lock loop is locking properly, the control voltage should be stable. In addition, internal bias voltages of the phase lock loop can be accessed by the analog test mux112and compared with allowed values in the lookup table to verify the internal bias voltages are within the valid prescribed range.

In another embodiment, the lookup table is contained within the analog monitor state machine114. In yet another embodiment, the lookup table is implemented in the core logic of a FPGA. In other embodiments, the lookup table is implemented off-chip through a microprocessor. The lookup table may contain a plurality of diagnostic error messages, where each of the diagnostic error messages correspond to values of the analog voltages which are outside the stored allowed values. When the comparison of the digital representation to the pre-determined allowed voltage indicates the analog voltage is outside the allowed value, the analog state machine114can transmit an error message indicating which voltage is triggering the diagnostic error message. As in the above example, the circuit designer can associate a diagnostic error message with a situation indicating the bias of an amplifier is outside the bias the amplifier was designed to operate.

FIG. 3Aillustrates an analog test multiplexer enabling selective access to analog voltages in accordance with one embodiment of the present invention. The analog voltages inside the analog block are coupled to the plurality voltage inputs122of the analog test mux112. The analog test mux112further includes a selection bus120which allows multiplexing of the plurality of analog voltages to a single output124. The selection bus120receives a selection signal of M bits from the analog monitor state machine. The selection signal is configured to be wide enough to select any of the analog voltages coupled to the analog test mux112for transmission to the output124. Random access to any of the analog voltages inside the analog block is enabled by controlling the selection bits provided to the analog test mux112. In one embodiment, the dynamically controlled analog test multiplexer112is utilized to direct the selected analog voltages to an ADC.

FIG. 3Billustrates an analog test multiplexer implemented using complementary metal-oxide semiconductor pass gates in accordance with one embodiment of the present invention. The analog test multiplexer112is implemented using a plurality of complementary metal-oxide semiconductor (CMOS) pass gates126, where the number of CMOS pass gates126is equal to the number of bits of the selection bus120of the analog monitor state machine. The use of CMOS pass gates126enables the analog test multiplexer112to transmit analog voltages of any value between the power supply voltage and ground. In one embodiment, when a selection bit120is high (digital 1), the CMOS pass gate126associated with the particular selection bit120is activated. Activation of the CMOS pass gate126directs the voltage at the voltage input122associated with the CMOS pass gate126to the output of the analog test mux112. For a selection bit120that is low (digital 0), the CMOS pass gate126associated with the particular selection bit120will remain inactive.

Although a specific transistor configuration was used to illustrate one embodiment of the analog test multiplexer112, one with skill in the art will appreciate other transistor configurations can be used. That is, so long as the essential functions of receiving the plurality of analog voltages and selection bits, and selectively transmitting the selected voltage to the output of the analog test multiplexer are retained, other transistor configurations are possible.

FIG. 4is a flow chart diagram illustrating method operations for selectively accessing analog voltages inside an analog block in accordance with one embodiment of the present invention. The method200begins with operation202, where the analog test multiplexer receives the analog voltages from the analog block. As illustrated inFIG. 2, each voltage input of the analog test mux is coupled to a corresponding analog voltage in the analog block. In operation204, the analog test multiplexer receives the selection bits, i.e. selection signal, from an analog monitor state machine. In one embodiment, the logic of analog monitor state machine which generates the selection bits is implemented in the core logic of a field-programmable gate array. The method200advances to operation206, where through the selection bit input, the analog test mux selectively accesses any of the analog voltages inside the analog block. In one embodiment, the analog state machine selects each of the analog voltages in a default sequence. In another embodiment, the analog monitor state machine can be reconfigured, using the control input, to access the analog voltages in a different sequence than the default sequence.

Operation208of the method200, converts the selectively accessed analog voltage into a digital representation through the use of an analog to digital converter. In one embodiment, the digital representation is transmitted to the analog monitor state machine and compared with a pre-determined value stored in the lookup table of the associated analog voltage, as discussed with reference toFIG. 2. In another embodiment, a diagnostic error message is transmitted if the digital representation of the analog voltage is outside the pre-determined values, where the diagnostic error message is associated with a particular analog voltage from the analog block.

The method and apparatus described herein may be incorporated into any suitable circuit, including processors and programmable logic devices (PLDs). The PLDs can include programmable array logic (PAL), programmable logic array (PLA), field programmable logic array (FPLA), electrically programmable logic devices (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), field programmable gate array (FPGA), application specific standard product (ASSP), application specific integrated circuit (ASIC), just to name a few.