Semiconductor device and method

A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

BACKGROUND

DETAILED DESCRIPTION

Coupled pairs of source-degenerated transistors and the methods of forming the same are provided, in accordance with some embodiments. The source degeneration resistors are formed using the same processing steps as the transistors, which can decrease device size and manufacturing cost. For example, the resistors may be formed in the same fin as an adjacent FinFET. The resistors may include passive resistors or variable resistors that have a resistance controllable by an applied voltage. Some embodiments include coupled pairs of transistor devices, each transistor device comprising a transistor and resistor(s) coupled in a source-degenerated configuration. The pairs of transistor devices can be coupled in various configurations. By forming source-degeneration resistors as described herein, effects due to transistor noise (e.g., flicker noise) can be reduced.

FIG.1illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin52on a substrate50(e.g., a semiconductor substrate). Isolation regions56are disposed in the substrate50, and the fin52protrudes above and from between neighboring isolation regions56. Although the isolation regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin52is illustrated as a single, continuous material as the substrate50, the fin52and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fin52refers to the portion extending between the neighboring isolation regions56.

A gate dielectric layer92is along sidewalls and over a top surface of the fin52, and a gate electrode94is over the gate dielectric layer92. Source/drain regions82are disposed in opposite sides of the fin52with respect to the gate dielectric layer92and gate electrode94.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode94and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions82of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin52and in a direction of, for example, a current flow between the source/drain regions82of the FinFET. Cross-section D-D is parallel to cross-section A-A and extends through a source/drain region82of the FinFET. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like.

FIGS.2through15Care cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2through5are illustrated along reference cross-section A-A illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.6A,8A,9A,10A,11A,12A,13A,14A, and15Aare illustrated along reference cross-section A-A illustrated inFIG.1, andFIGS.6B,8B,9B,10B,11B,12B,13B,14B,14D, and15Bare illustrated along reference cross-section B-B illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.8C,10C,14C, and15Care plan views.FIGS.10D and10Eare illustrated along reference cross-section D-D illustrated inFIG.1, except for multiple fins/FinFETs.

The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as n-type diffusion resistors or NMOS transistors (e.g., n-type FinFETs). The p-type region50P can be for forming p-type devices, such as p-type diffusion resistors or PMOS transistors (e.g., p-type FinFETs). The n-type region50N may be physically separated from the p-type region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P.

InFIG.3, fins52are formed in the substrate50. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.

InFIG.4, an insulation material54is formed over the substrate50and between neighboring fins52. The insulation material54may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high-density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material54is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material54is formed such that excess insulation material54covers the fins52. Although the insulation material54is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not shown) may first be formed along a surface of the substrate50and the fins52. Thereafter, a fill material, such as those discussed above may be formed over the liner.

InFIG.5, a removal process is applied to the insulation material54to remove excess insulation material54over the fins52. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins52such that top surfaces of the fins52and the insulation material54are level after the planarization process is complete. In embodiments in which a mask remains on the fins52, the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the fins52, respectively, and the insulation material54are level after the planarization process is complete.

InFIGS.6A and6B, the insulation material54is recessed to form Shallow Trench Isolation (STI) regions56.FIG.6Aillustrates a cross-sectional view along reference cross-section A-A, andFIG.6Billustrates a cross-sectional view along reference cross-section B-B in the n-type region50N. The insulation material54may be recessed such that upper portions of fins52in the n-type region50N and in the p-type region50P protrude from between neighboring STI regions56. Further, the top surfaces of the STI regions56may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions56may be formed flat, convex, and/or concave by an appropriate etch. The STI regions56may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material54(e.g., etches the material of the insulation material54at a faster rate than the material of the fins52). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

The process described with respect toFIGS.2through6Bis just one example of how the fins52may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins52. For example, the fins52inFIG.5can be recessed, and a material different from the fins52may be epitaxially grown over the recessed fins52. In such embodiments, the fins52comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together.

Still further, it may be advantageous to epitaxially grow a material in n-type region50N (e.g., an NMOS region) different from the material in p-type region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins52may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

Further inFIGS.6A-6B, appropriate wells may be formed in the fins52and/or the substrate50. In some embodiments, one or more P-wells may be formed in the n-type region50N, and one or more N-wells may be formed in the p-type region50P. In some embodiments, both a P-well and an N-well are formed in the n-type region50N or the p-type region50P.

As an illustrative example,FIG.6Bshows a cross-sectional view of the n-type region50N along the reference cross-section B-B shown inFIG.6A, in accordance with some embodiments. As shown inFIG.6B, both N-wells53N and P-wells53P may be formed in the fins52. In some embodiments, P-wells53P may be formed in the fin52for an n-type device such as a FinFET (e.g., FinFETs120A-B inFIGS.14B-14C) or the like. In some embodiments, a channel region58of a FinFET may be formed within a P-well53P, such as channel regions58A-B inFIG.6B. In some embodiments, an N-well53N may be formed in the fin52for an active resistor (e.g., active resistor121inFIGS.14B-14C) and/or a passive resistor (e.g., passive resistor123inFIGS.17A-17C). For example, a conductive channel59of an active resistor may be formed within an N-well53N, such as conductive channels59A-B inFIG.6B. In some embodiments, a conductive channel259of a passive resistor is formed in addition to or instead of a conductive channel59, described in greater detail below forFIGS.17A-17D. In some embodiments, an N-well53N may be disposed between two P-wells53P, as shown inFIG.6B. Other configurations or arrangements are possible.

FIG.6Bis an illustration of the n-type region50N, but in some embodiments N-wells53N and/or P-wells53P may be formed in the p-type region50P for FinFETs, active resistors, passive resistors, other devices, or the like. In other embodiments, a region50N/50P may have a different number, configuration, or arrangement of N-wells53N or P-wells53P. The wells may have different sizes or shapes than shown, and may extend across multiple devices (e.g., across multiple FinFETs, active resistors, passive resistors, or other devices). An N-well53N may be adjacent to a P-well53P or separated from a P-well53P. In some cases, an N-well53N and a P-well53P may overlap.

In some embodiments, different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins52and the STI regions56in the n-type region50N. The photoresist is patterned to expose the p-type region50P of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. In some embodiments, the photoresist is patterned to allow n-type impurities to be implanted into portions of the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, the like, or a combination thereof implanted in the region to a concentration of equal to or less than about 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following the implanting of the p-type region50P, a photoresist is formed over the fins52and the STI regions56in the p-type region50P. The photoresist is patterned to expose the n-type region50N of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. In some embodiments, the photoresist is patterned to allow p-type impurities to be implanted into portions of the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than about 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

In other embodiments, the implants of the n-type region50N and the p-type region50P may be performed at a different stage in the manufacturing process than described above. For example, implants may be performed prior to forming the fins52in the substrate50and/or at another step. In some embodiments, multiple implants may be performed at different stages, and additional implants may be performed in addition to those described for the N-well53N and the P-well53P. For example, implants for lightly doped source/drain (LDD) regions may also be performed, described in greater detail below forFIGS.8A-8C. Any suitable combination or configuration of implants may be used to form FinFETs, active resistors, or passive resistors as described herein, and all such variations are considered within the scope of the present disclosure.

After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

InFIG.7, a dummy dielectric layer60is formed on the fins52. The dummy dielectric layer60may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer62is formed over the dummy dielectric layer60, and a mask layer64is formed over the dummy gate layer62. The dummy gate layer62may be deposited over the dummy dielectric layer60and then planarized, such as by a CMP. The mask layer64may be deposited over the dummy gate layer62. The dummy gate layer62may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer62may be made of other materials that have a high etching selectivity from the etching of isolation regions, e.g., the STI regions56and/or the dummy dielectric layer60. The mask layer64may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer62and a single mask layer64are formed across the n-type region50N and the p-type region50P. It is noted that the dummy dielectric layer60is shown covering only the fins52for illustrative purposes only. In some embodiments, the dummy dielectric layer60may be deposited such that the dummy dielectric layer60covers the STI regions56, extending over the STI regions and between the dummy gate layer62and the STI regions56.

FIGS.8A through15Cillustrate various additional steps in the manufacturing of embodiment devices.FIGS.8A through15Cillustrate features in the n-type region50N, but similar embodiments may be formed in the p-type region50P using appropriately different dopants. In some cases, the structures illustrated inFIGS.8A through15Cmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure.

InFIGS.8A,8B and8C, the mask layer64(seeFIG.7) may be patterned and gate seal spacers80may be formed, in accordance with some embodiments.FIG.8Aillustrates a cross-sectional view along reference cross-section A-A, andFIG.8Billustrates a cross-sectional view along reference cross-section B-B.FIG.8Cillustrates a plan view, though some features are not shown for clarity reasons. The mask layer64may be pattered using acceptable photolithography and etching techniques to form masks74. The pattern of the masks74may be transferred to the dummy gate layer62to form dummy gates72. A dummy gate72and its overlying mask74may be collectively referred to herein as a “dummy gate stack.” In some embodiments (not illustrated), the pattern of the masks74may also be transferred to the dummy dielectric layer60by an acceptable etching technique. The dummy gates72may cover respective channel regions58of the fins52, respective conductive channels59of the fins52, or respective conductive channels259of the fins52(seeFIG.17B). The pattern of the masks74may be used to physically separate each of the dummy gates72from adjacent dummy gates72. The dummy gates72may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective epitaxial fins52. In some embodiments, adjacent dummy gate stacks may be separated by a distance W1that is in the range of about 3 nm to about 1000 nm. The dummy gate stacks may be formed having a pitch P1that is in the range of about 16 nm to about 1500 nm. Other distances are possible.

Further inFIGS.8A-8C, gate seal spacers80can be formed on exposed surfaces of the dummy gates72, the masks74, and/or the fins52. A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers80. The gate seal spacers80may be formed of silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof.

After the formation of the gate seal spacers80, implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above inFIGS.6A-6B, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins52in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins52in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in the range of about 1015 cm−3to about 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities. In some embodiments, the n-type region50N or the p-type region50P may be implanted with both n-type and p-type impurities. In some embodiments, the LDD implants may be implanted as part of the formation of a conductive channel59or a conductive channel259(seeFIG.17B).

InFIGS.9A and9B, gate spacers86are formed on the gate seal spacers80along sidewalls of the dummy gates72and the masks74, in accordance with some embodiments. The gate spacers86may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers86may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like.

It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers80may not be etched prior to forming the gate spacers86, yielding “L-shaped” gate seal spacers), spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers80while the LDD regions for p-type devices may be formed after forming the gate seal spacers80.

InFIGS.10A through10E, epitaxial regions82are formed in the fins52, in accordance with some embodiments.FIG.10Aillustrates a cross-sectional view along reference cross-section A-A, andFIG.10Billustrates a cross-sectional view along reference cross-section B-B.FIG.10Cillustrates a plan view, though some features are not shown for clarity reasons.FIGS.10D and10Eare illustrated along reference cross-section D-D. The epitaxial regions82are formed in the fins52such that each dummy gate72is disposed between respective neighboring pairs of the epitaxial regions82. In some embodiments the epitaxial regions82may extend into, and may also penetrate through, the fins52. In some embodiments, the gate spacers86are used to separate the epitaxial regions82from the dummy gates72by an appropriate lateral distance so that the epitaxial regions82do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial regions82may be selected to exert stress in respective channel regions58, thereby improving performance.

The epitaxial regions82in the n-type region50N may be formed by masking the p-type region50P and etching source/drain regions of the fins52in the n-type region50N to form recesses in the fins52. Then, the epitaxial regions82in the n-type region50N are epitaxially grown in the recesses. The epitaxial regions82may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin52is silicon, the epitaxial regions82in the n-type region50N may include materials exerting a tensile strain in the channel region58, such as silicon, silicon carbide, phosphorous-doped silicon carbide, silicon phosphide, the like, or a combination thereof. The epitaxial regions82in the n-type region50N may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial regions82in the p-type region50P may be formed by masking the n-type region50N and etching source/drain regions of the fins52in the p-type region50P to form recesses in the fins52. Then, the epitaxial regions82in the p-type region50P are epitaxially grown in the recesses. The epitaxial regions82may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin52is silicon, the epitaxial regions82in the p-type region50P may comprise materials exerting a compressive strain in the channel region58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, the like, or a combination thereof. The epitaxial regions82in the p-type region50P may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial regions82and/or the fins52may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of about 1019cm−3to about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial regions82may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial regions82in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial regions have facets which expand laterally outward beyond sidewalls of the fins52. In some embodiments, these facets cause adjacent epitaxial regions82to merge, as illustrated byFIGS.10C and10D. In other embodiments, adjacent epitaxial regions82remain separated after the epitaxy process is completed, as illustrated byFIG.10E. In the embodiments illustrated inFIGS.10D and10E, gate spacers86are formed covering a portion of the sidewalls of the fins52that extend above the STI regions56, thereby blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers86may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region56.

InFIGS.11A and11B, a first interlayer dielectric (ILD)88is deposited over the structure illustrated inFIGS.10A and10B. The first ILD88may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)87is disposed between the first ILD88and the epitaxial regions82, the masks74, and the gate spacers86. The CESL87may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the overlying first ILD88.

InFIGS.12A and12B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD88with the top surfaces of the dummy gates72or the masks74. The planarization process may also remove the masks74on the dummy gates72, and portions of the gate seal spacers80and the gate spacers86along sidewalls of the masks74. After the planarization process, top surfaces of the dummy gates72, the gate seal spacers80, the gate spacers86, and the first ILD88are level. Accordingly, the top surfaces of the dummy gates72are exposed through the first ILD88. In some embodiments, the masks74may remain, in which case the planarization process levels the top surface of the first ILD88with the top surfaces of the masks74.

InFIGS.13A and13B, the dummy gates72, and the masks74if present, are removed in an etching step(s), so that recesses90are formed. Portions of the dummy dielectric layer60in the recesses90may also be removed. In some embodiments, only the dummy gates72are removed and the dummy dielectric layer60remains and is exposed by the recesses90. In some embodiments, the dummy dielectric layer60is removed from recesses90in a first region of a die (e.g., a core logic region) and remains in recesses90in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates72are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates72with little or no etching of the first ILD88or the gate spacers86. Each recess90may expose and/or overlie a channel region58of a respective fin52or a conductive channel59of a respective fin52. In this manner, each channel region58or conductive channel59is disposed between neighboring pairs of the epitaxial regions82. During the removal, the dummy dielectric layer60may be used as an etch stop layer when the dummy gates72are etched. The dummy dielectric layer60may then be optionally removed after the removal of the dummy gates72.

InFIGS.14A,14B,14C, and14D, gate dielectric layers92and gate electrodes94are formed in the recesses90to form gate structures110A and110B of FinFETs120A and120B and form control structures111A and111B of active resistors121A and121B, in accordance with some embodiments.FIG.14Aillustrates a cross-sectional view along reference cross-section A-A, andFIG.14Billustrates a cross-sectional view along reference cross-section B-B.FIG.14Cillustrates a plan view, though some features are not shown for clarity reasons.FIG.14Dillustrates a detailed view of region89ofFIG.14B.

The gate dielectric layers92may comprise one or more layers deposited in the recesses90, such as on the top surfaces and the sidewalls of the fins52and on sidewalls of the gate seal spacers80/gate spacers86. The gate dielectric layers92may also be formed on the top surface of the first ILD88. In some embodiments, the gate dielectric layers92comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers92include an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, the like, or combinations thereof. The gate dielectric layers92may include a dielectric layer having a k-value greater than about 7.0. The formation methods of the gate dielectric layers92may include Molecular-Beam Deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layer60remains in the recesses90, the gate dielectric layers92include a material of the dummy dielectric layer60(e.g., silicon oxide).

The gate electrodes94are deposited over the gate dielectric layers92, respectively and fill the remaining portions of the recesses90. The gate electrodes94may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, the like, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode94is illustrated inFIG.14B, the gate electrode94may comprise any number of liner layers94A, any number of work-function tuning layers94B, and a fill material94C, as illustrated byFIG.14DAfter filling the recesses90, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers92and the material of the gate electrodes94, which excess portions are over the top surface of the ILD88. The remaining portions of material of the gate electrodes94and the gate dielectric layers92thus form replacement structures of the resulting devices, such as gate structures110or control structures111, described in greater detail below.

The formation of the gate dielectric layers92in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers92in each region are formed from the same materials, and the formation of the gate electrodes94may occur simultaneously such that the gate electrodes94in each region are formed from the same materials. In some embodiments, the gate dielectric layers92in each region may be formed by distinct processes, such that the gate dielectric layers92may be different materials, and/or the gate electrodes94in each region may be formed by distinct processes, such that the gate electrodes94may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

The gate dielectric layers92and the gate electrodes94formed over a channel region58of a fin52may form a gate structure110of a FinFET120, in some embodiments. For example, in the embodiment shown inFIGS.14B-14C, a gate structure110A is formed over the channel region58A of a FinFET120A (seeFIGS.15B-15C), and a gate structure110B is formed over the channel region58B of a FinFET120B (seeFIGS.15B-15C). The gate electrodes94and the gate dielectric layers92over a channel region58are collectively referred to as a gate structure110herein, but may also be referred to as a “replacement gate,” a “gate stack,” or the like. The gate structure110may extend along sidewalls of the corresponding channel region58. The channel region58of a FinFET120may extend under the gate structure110and may be disposed between neighboring epitaxial regions82comprising the source/drain regions of the FinFET120. For example, as shown inFIG.14B, the channel region58A is disposed between an epitaxial source region82SA and an epitaxial drain region82DA, and the channel region58B is disposed between an epitaxial source region82SB and an epitaxial drain region82DB. A gate structure110may extend over one fin52or over multiple fins52, and accordingly, a FinFET120may have a single fin52or multiple fins52.

In some embodiments, the gate dielectric layers92and the gate electrodes94formed over a conductive channel59of a fin52may form a control structure111of an active resistor121(described in greater detail below forFIGS.15A-15C). For example, in the embodiment shown inFIGS.14B-14C, a gate structure110A is formed over the channel region58A of a FinFET120A (seeFIGS.15B-15C), and a gate structure110B is formed over the channel region58B of a FinFET120B (seeFIGS.15B-15C). The gate electrodes94and the gate dielectric layers92over a conductive channel59are collectively referred to as a control structure111herein, but may also be referred to as a “control terminal,” a “resistor control gate,” or the like. The control structure111may extend along sidewalls of the corresponding conductive channel59. The conductive channel59of an active resistor121may extend under the control structure111and be disposed between neighboring epitaxial regions82of the active resistor121. In some embodiments, one of the neighboring epitaxial regions82of an active resistor121is also a source/drain region of an adjacent FinFET120. For example, as shown inFIG.14B, the conductive channel59A is disposed between an epitaxial source region82SA and an epitaxial resistor region82R, and the conductive channel59B is disposed between an epitaxial source region82SB and the epitaxial resistor region82R. In some embodiments, one of the neighboring epitaxial regions82of an active resistor121is also an epitaxial region82of another adjacent active resistor121or is also an epitaxial region82of an adjacent passive resistor123(seeFIGS.17A-17D).

In some embodiments, some of the gate dielectric layers92and the gate electrodes94formed over a fin52may be dummy gate structures113. In some cases, the dummy gate structures113are not a functional part of an active or passive device, and may be electrically isolated from other structures. In some cases, the dummy gate structures113are disposed between adjacent devices. In some embodiments, portions of dummy gate structures113are subsequently removed and replaced with an insulating material (not illustrated).

InFIGS.15A,15B, and15C, various contacts are formed to epitaxial regions82, gate structures110, and control structures111to form a pair of source-degenerated transistor devices125A and125B, in accordance with some embodiments. Initially, a gate mask100may be formed over the gate dielectric layers92and corresponding gate electrodes94. In some embodiments, forming the gate mask100includes recessing the gate dielectric layers92and gate electrodes94so that a recess is formed between opposing portions of respective gate spacers86. The gate mask100may comprise one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD88. In other embodiments, the gate dielectric layers92and gate electrodes94are not recessed. In some embodiments, the gate structures110, the control structures111, or the dummy gate structures113may remain level with top surfaces of the first ILD88, as shown inFIG.15B. The gate mask100is optional and may be omitted in some embodiments.

As also illustrated inFIGS.15A and15B, a second ILD102is deposited over the first ILD88. In some embodiments, the second ILD102is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD102is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD.

Contacts such as gate contacts134, control contacts135, and epitaxial region contacts132/136may then be formed through the second ILD102and the first ILD88, in accordance with some embodiments. For example, openings for the epitaxial region contacts132/136may be formed through the first ILD88, the second ILD102, and the gate mask100(if present). Openings for the gate contacts134and control contacts135may be formed through the second ILD102and the gate mask100(if present). The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, the like, or a combination thereof. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD102. The remaining liner and conductive material form the gate contacts134, the control contacts135, and the epitaxial region contacts132/136in the openings. An anneal process may be performed to form a silicide (not shown) at the interface between the epitaxial regions82and the epitaxial region contacts132/136.

The epitaxial region contacts132/136are physically and electrically coupled to the epitaxial regions82, the gate contacts134are physically and electrically coupled to the gate electrodes94of the gate structures110, and the control contacts135are physically and electrically coupled to the gate electrodes94of the control structures111. The epitaxial region contacts132/136, the gate contacts134, and/or the control contacts135may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-section, it should be appreciated that each of the gate contacts134, control contacts135, and epitaxial region contacts132/136may be formed in different cross-sections, which may avoid shorting of the contacts. One or more epitaxial region contacts132/136may be formed on a epitaxial region82, one or more gate contacts134may be formed on a gate structure110, and one or more control contacts135may be formed on a control structure111.

In this manner, a coupled pair of source-degenerated transistor (SDT) devices125A and125B may be formed, in accordance with some embodiments.FIG.15Dillustrates a simplified circuit schematic of the SDT devices125A-B shown inFIGS.15A-15C. Each of the SDT devices125A-B shown inFIGS.15A-15Dincludes an active resistor121electrically coupled in series with the epitaxial source region82S of a FinFET120. For example, the SDT device125A includes a FinFET120A comprising a channel region58A between an epitaxial drain region82DA and an epitaxial source region82SA, and an active resistor121A comprising a conductive channel59A between the epitaxial source region82SA and an epitaxial region82C. The SDT device125B includes a FinFET120B comprising a channel region58B between an epitaxial drain region82DB and an epitaxial source region82SB, and an active resistor121B comprising a conductive channel59B between the epitaxial source region82SB and the epitaxial region82C. The epitaxial region82C is part of both the SDT device125A and the SDT device125B, and thus the SDT devices125A-B are electrically coupled together at the epitaxial region82C.

As shown inFIGS.15B-D, the epitaxial source regions82SA and82SB are free of contacts such that a current flowing through the FinFET120A also flows through the active resistor121A and a current flowing through the FinFET120B also flows through the active resistor121B. Accordingly, current flows through the SDT device125A between the epitaxial region contact132A of the epitaxial drain region82DA and the epitaxial region contact136of the epitaxial region82C, and current flows through the SDT device125B between the epitaxial region contact132B of the epitaxial drain region82DB and the epitaxial region contact136of the epitaxial region82C. In this manner, the active resistor121A and the FinFET120A together form a SDT device125A that is similar to a transistor with source-degeneration, in which the active resistor121A acts as a degeneration resistor. Similarly, the active resistor121B and the FinFET120B together form a SDT device125B in which the active resistor121B acts as a degeneration resistor. The techniques described herein allow for the formation of multiple SDT devices125that are electrically coupled at a single epitaxial region82, which can allow for the formation of source-degenerated transistors at a greater density and without requiring additional process steps.

The current in an active resistor121(e.g.,121A or121B) is conducted through the corresponding conductive channel59(e.g.,59A or59B). In this manner, an active resistor121may be similar to a dopant diffused resistor, in some cases. An active resistor121may include a single conductive channel59formed in one fin52or multiple conductive channels59formed in multiple fins52. In some embodiments, the resistance of an active resistor121can be controlled by applying a voltage to the control structure111of the active resistor121. The voltage may be applied to the control structure111through a corresponding control contact135. In some cases, applying a voltage to the control structure111may cause accumulation or depletion of the conductive channel59that changes the resistance of the active resistor121. For example, applying a more positive voltage to the control structure111of an active resistor121with an n-type conductive channel59can decrease the resistance of the active resistor121, and applying a more negative voltage to the control structure111of an active resistor121with an n-type conductive channel59can increase the resistance of the active resistor121. In this manner, an active resistor121may be similar to a depletion-mode MOSFET, in some cases. The formation of an active resistor121as a degeneration resistor as described herein can allow for improved device flexibility, device parameter tuning, or more efficient device operation.

In some embodiments, an active resistor121(e.g.,121A or121B) may provide a resistance that is in the range of about 150 ohms to about 2000 ohms, though other resistances are possible. In some embodiments, applying appropriate voltages to the control structure111of an active resistor121can change the resistance of that active resistor121between about 5% and about 100%, though other resistances are possible. In some embodiments, the resistance or range of resistances of an active resistor121may be controlled by controlling the doping of the corresponding conductive channel59. For example, in some cases, a conductive channel59with a higher doping concentration may result in the respective active resistor121having a smaller resistance. In some embodiments, the degeneration resistance of a SDT device125(e.g.,125A or125B) may be adjusted by forming more or fewer epitaxial region contacts136. For example, a smaller number of epitaxial region contacts136on the epitaxial region82C may provide a larger overall contact resistance than a larger number of epitaxial region contacts136on the epitaxial region82C. Thus, forming fewer epitaxial region contacts136can increase the degeneration resistance of the SDT device125due to an increase in contact resistance.

The active resistors121A and121B of a coupled pair of SDT devices125A-B may be similar or different. For example, the active resistors121A-B may have similar or different doping profiles. A voltage applied to the control structure111A of the active resistor121A may be the same or different from a voltage applied to the control structure111B of the active resistor121B. The active resistors121A-B of a coupled pair of SDT devices125A-B may have similar resistances or different resistances. In some embodiments, only one of the coupled pair of SDT devices125A-B includes an active resistor121(not illustrated), or the SDT device125A may have a different number of active resistors121than the SDT device125B. In this manner, the degeneration resistances of the SDT devices125A-B may be similar or different.

In some embodiments, the control structure111of an active resistor121is equidistant between a neighboring gate structure110and a neighboring dummy gate structure113. In some embodiments, the distance between the control structure111of an active resistor121and a neighboring gate structure110is approximately the distance W1(seeFIGS.8B-8C). In some embodiments, the distance between the control structure111of an active resistor121and a neighboring dummy gate structure113is also approximately the distance W1. In some embodiments, the control structures111A and111B of the coupled pair of SDT devices125A-B are separated by approximately the distance W1.

FIGS.15A-15Dshow an embodiment of SDT devices125A-B each having a single active resistor121(e.g.,121A and121B), but in other embodiments, a SDT device125may have more than one active resistor121(not illustrated). For example, a SDT device125may include two or more adjacent active resistors121disposed between the FinFET120and the epitaxial region contacts136. In this manner, two or more active resistors121may be connected in series to increase the degeneration resistance of the SDT device125. The conductive channel59of each respective active resistor121may be similar or may have different doping concentrations or doping profiles. A pair of neighboring active resistors121may share an epitaxial region82. The respective control structures111of multiple active resistors121may be collectively controlled (e.g., electrically coupled) or may be independently controlled. In some embodiments, the two SDT devices125of a coupled pair of SDT devices125may each have a different number or different configuration of active resistors121. Accordingly, the two SDT devices125of a coupled pair of SDT devices125may each have a different degeneration resistance, in some embodiments. In this manner, the characteristics or configuration of coupled SDT devices125as described herein may be controlled to provide desired degeneration resistances or desired ranges of degeneration resistance.

In some cases, forming a SDT device125comprising a transistor with source degeneration such as described herein can reduce the effects of noise. For example, in some cases, forming a SDT device125with an active resistor121as described herein can reduce the effects of flicker noise (e.g., 1/f noise). Turning toFIG.16, a simplified schematic of a MOSFET with source degeneration is shown. The MOSFET inFIG.16is analogous to the FinFET120A or120B in the schematic ofFIG.15D, and the source degeneration of the MOSFET is provided by a resistor Rs, which is analogous to the active resistor121A or121B in the schematic ofFIG.15D. As shown inFIG.16, the flicker noise of a MOSFET may be modeled as a voltage source (vn02) in series with the gate of the MOSFET, which corresponds to an equivalent noise current (in02) equal to (gm2vn02), where gm is the transconductance of the MOSFET. However, the transconductance Gm of the MOSFET with source degeneration resistor Rs is equal to (gm/(1+gm Rs)). Thus, the equivalent noise current (in12) of the MOSFET with source degeneration is equal to (gm2vn02/(1+gm Rs)2), or (in02/(1+gm Rs)2)). In other words, the presence of the source degeneration resistor Rs effectively reduces the magnitude of the MOSFET's flicker noise, with a larger resistance of Rs resulting in a smaller noise magnitude. Similarly, the presence of an active resistor121in a SDT device125can effectively reduce the magnitude of the flicker noise of the FinFET120in the SDT device125. In this manner, the use of coupled SDT devices125as described herein can reduce the effects of transistor noise and improve device performance.

The SDT devices125A-B shown inFIGS.15A-15Deach include an active resistor121(e.g.,121A and121B) that provides degeneration resistance, but in other embodiments the degeneration resistance of a SDT device125may be provided by a passive resistor123instead of or in addition to an active resistor121. As an example,FIGS.17A-17Cillustrate a coupled pair of SDT devices225A and225B including passive resistors123A and123B and active resistors121A and121B, in accordance with some embodiments.FIG.17Dillustrates a simplified circuit schematic of the coupled SDT devices225A-B shown inFIGS.17A-17C. The SDT devices225A-B shown inFIGS.17A-17Dare similar to the SDT devices125A-B shown inFIGS.15A-15D, except the SDT device225A includes a passive resistor123A formed in the fins52in addition to the active resistor121A, and the SDT device225B includes a passive resistor123B formed in the fins52in addition to the active resistor121B. Each passive resistor123A-B is electrically coupled in series with a corresponding active resistor121A-B, and thus the passive resistors123A-B add to the degeneration resistance of the SDT devices225A-B. A passive resistor123may be similar to an active resistor121as described herein, except that the resistance of the passive resistor123is substantially fixed and is not controlled by applying a control voltage.

A passive resistor123may be formed using a process similar to that described for an active resistor121, except that control contacts135are not formed for the passive resistor123. In this manner, the gate electrode94and the gate dielectric layer92over a passive resistor123may form a dummy gate structure113. A passive resistor123may comprise a conductive channel259between neighboring epitaxial regions82. For example, as shown inFIG.17B, the passive resistor123A includes a conductive channel259A between epitaxial resistor region82RA and epitaxial region82C and the passive resistor123B includes a conductive channel259B between epitaxial resistor region82RB and epitaxial region82C. A passive resistor123may include a single conductive channel259formed in one fin52or multiple conductive channels259formed in multiple fins52. In some embodiments, the conductive channel259of a passive resistor123may be similar to a conductive channel59of an active resistor121, described above. The conductive channel259of a passive resistor123may be similar to or different from a conductive channel59of an active resistor121in the same SDT device225, in some cases.

In some embodiments, one (or both) of the neighboring epitaxial regions82of a passive resistor123is also a neighboring epitaxial region82of an adjacent active resistor121(e.g. epitaxial resistor region82RA inFIGS.17B-17D), an adjacent FinFET120, or another passive resistor123. In some embodiments, a passive resistor123may provide a resistance that is in the range of about 150 ohms to about 2000 ohms, though other resistances are possible. In some embodiments, the distance between the dummy gate structure113over the passive resistor123and a neighboring control structure111is approximately the distance W1(seeFIGS.8B-8C).

The SDT devices225A-B shown inFIGS.17A-17Dare examples, and SDT devices225having other configurations of active resistors121or passive resistors123are possible. For example, in other embodiments, a SDT device225may have two or more active resistors121and/or two or more passive resistors123. The conductive channels59of the active resistors121and the conductive channels259of the passive resistors123may be similar or may be different (e.g., have different doping profiles). In this manner, a suitable number of active resistors121and/or passive resistors123may be formed to provide a suitable degeneration resistance. The active resistors121and passive resistors123in a SDT device225may be connected in any suitable series configuration to a FinFET120. Additionally, the active resistors121and passive resistors123may be arranged in any suitable series order between a FinFET120and an epitaxial region82C. In some embodiments of a coupled pair of SDT devices225A-B, the number, arrangement, or characteristics of the resistors121/123of the SDT device225A may be different from the number, arrangement, or characteristics of the resistors121/123of the SDT device225B. These variations can allow for flexibility in the operation, design, or layout of a coupled pair of SDT devices225A-B.

In some embodiments, the epitaxial regions82of the active resistors121, passive resistors123, and FinFET120of a SDT device225all have the same pitch. In some embodiments, a distance W2(seeFIGS.10B-10C) between neighboring epitaxial regions82may be controlled to control the lengths of the channel region58, conductive channel59, and conductive channel259. In some cases, controlling the width W2in this manner can also control the resistances of active resistors121and passive resistors123.

FIGS.18A-18Cillustrate a coupled pair of SDT devices325A and325B, in accordance with some embodiments.FIG.18Dillustrates a simplified circuit schematic of the coupled SDT devices325A-B shown inFIGS.18A-18C. The SDT devices325A-B shown inFIGS.18A-18Dare similar to the SDT devices225A-B shown inFIGS.17A-17D, except the SDT devices325A-B are coupled at an epitaxial drain region82D shared by both FinFETs120A-B instead of being coupled at an epitaxial region82C shared by two resistors121/123. For example, the SDT device325A comprises a FinFET120A including the epitaxial drain region82D and an epitaxial source region82SA, a passive resistor123A with a conductive channel259A between the epitaxial source region82SA and an epitaxial resistor region82RA, and an active resistor121A with a conductive channel59A between the epitaxial resistor region82RA and an epitaxial region82CA. The SDT device325B comprises a FinFET120B that includes the epitaxial drain region82D and an epitaxial source region82SB, a passive resistor123B with a conductive channel259B between the epitaxial source region82SB and an epitaxial resistor region82RB, and an active resistor121B with a conductive channel59B between the epitaxial resistor region82RB and an epitaxial region82CB. This is an example, and other numbers, arrangements, or configurations of FinFETs120, active resistors121, and passive resistors123are possible. For a non-limiting example, the resistors121/123of the SDT device325A may be different from the resistors121/123of the SDT device325B.

More than two SDT devices may be coupled in other embodiments. As an example,FIGS.19A-19Billustrate an embodiment in which four SDT devices425A,425B,425C, and425D are coupled together. In other embodiments, three SDT devices or more than four SDT devices may be coupled together. The SDT devices425A-D ofFIGS.19A-Bare similar to the SDT devices225A-B ofFIGS.17A-D. One or more of the SDT devices425A-D may be the same or may have a different configuration. For example, one or more of the SDT devices425A-D may be similar to the SDT devices325A-B ofFIGS.18A-D. All suitable combinations and configurations of coupled SDT devices and the FinFETs, active resistors, or passive resistors therein are within the scope of the present disclosure.

In the embodiment ofFIGS.19A-19B, the SDT devices425A and425B are coupled together, the SDT devices425B and425C are coupled together, and the SDT devices425C and425D are coupled together. The SDT devices425A-B are coupled at an epitaxial region82CA that neighbors both a passive resistor123A of the SDT device425A and a passive resistor123B of the SDT device425B. The SDT devices425B-C are coupled at an epitaxial drain region82D shared by both a FinFET120B of the SDT device425B and a FinFET120C of the SDT device425C. The SDT devices425C-D are coupled at an epitaxial region82CB that neighbors both a passive resistor123C of the SDT device425C and a passive resistor123D of the SDT device425D. In this manner, multiple SDT devices may be coupled together at the epitaxial regions of neighboring pairs.

The example SDT devices inFIGS.15A-15C,17A-17C,18A-18C, and19Aare described as being formed in the n-type region50N, but SDT devices may be formed in the p-type region50P. In some embodiments, a SDT device formed in the p-type region50P may comprise doped regions of different dopant types than a SDT device formed in the n-type region50N. For example, the FinFET120of a SDT device in the p-type region50P may be a p-type FinFET, and the conductive channels59/259of the resistors121/123may be doped with p-type dopants. In some embodiments, regions of STD devices in the n-type region50N and regions of STD devices in the p-type region50P are implanted in the same implant steps or comprise similar dopants. In some embodiments, a SDT device in the n-type region50N is coupled to a SDT device in the p-type region50P.

The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. A nanostructure device can be formed as disclosed in U.S. Pat. No. 9,647,071, which is incorporated herein by reference in its entirety.

Embodiments herein may achieve advantages. By forming coupled transistor devices that include one or more source degeneration resistors, the effects of transistor noise such as flicker noise can be reduced. This can improve the performance of devices such as RF devices or the like. By forming coupled source-degenerated transistors as described herein, multiple source-degenerated transistors may be formed at a high density. The source degeneration resistors may be formed using structures and process steps similar to those used for the transistors, which can reduce cost or manufacturing time and increase yield. The source degeneration resistors described herein include both passive resistors and variable resistors for which the resistance can be modulated with an applied voltage. The total degeneration resistance may be configured using a combination of one or more passive resistors and/or variable resistors, which allows for design flexibility. The source degeneration resistors described herein are formed using front-end-of-line (FEOL) processes, and may be formed having a smaller size than resistors formed using back-end-of-line (BEOL) processes, in some cases. For example, the source degeneration resistors may be formed in the same fins as an adjacent FinFET. Embodiments described herein also allow for source degeneration resistors to be formed without the addition of extra process steps. The features and techniques described herein may be used to form various coupled transistor devices with resistors such as common source-amplifiers, common-drain amplifiers, or the like.

In accordance with some embodiments of the present disclosure, a method includes forming a fin protruding from a substrate; forming a first transistor on the fin, including: forming a first epitaxial drain region and a first epitaxial source region on the fin; and forming a first gate structure on the fin between the first epitaxial drain region and the first epitaxial source region; forming a second transistor on the fin, including: forming a second epitaxial drain region and a second epitaxial source region on the fin; and forming a second gate structure on the fin between the second epitaxial drain region and the second epitaxial source region; forming a common epitaxial region in the fin between the first epitaxial source region and the second epitaxial source region; forming a first resistor in the fin between the first epitaxial source region and the common epitaxial region, wherein forming the first resistor includes implanting a first doped region of the fin that extends from the first epitaxial source region toward the epitaxial common region; forming a third gate structure on the first doped region of the fin; forming a second resistor in the fin between the second epitaxial source region and the common epitaxial region, wherein forming the second resistor includes implanting a second doped region of the fin that extends from the second epitaxial source region toward the epitaxial common region; and forming a fourth gate structure on the second doped region of the fin. In an embodiment, the method includes forming a first contact on the first epitaxial drain region, a second contact on the second epitaxial drain region, and a third contact on the common epitaxial region. In an embodiment, the first epitaxial source region and the second epitaxial source region are free of contacts. In an embodiment, the method includes forming a first gate contact on the first gate structure, a second gate contact on the second gate structure, and a third gate contact on the third gate structure. In an embodiment, the third gate structure is a dummy gate structure. In an embodiment, the first epitaxial source region is adjacent the epitaxial common region. In an embodiment, the method includes forming a third resistor in the fin between the first resistor and the epitaxial common region. In an embodiment, the fin, the first doped region, and the second doped region have the same doping type.

In accordance with some embodiments of the present disclosure, a method includes implanting a semiconductor fin to form a first doped region; implanting the semiconductor fin to form a second doped region and a third doped region adjacent opposite respective sides of the first doped region, wherein the first doped region is doped differently than the second doped region and the third doped region; forming epitaxial regions in the semiconductor fin, wherein the first doped region extends from a first epitaxial region to a second epitaxial region, wherein the second doped region extends from the first epitaxial region to a third epitaxial region neighboring the first epitaxial region, wherein the third doped region extends from the second epitaxial region to a fourth epitaxial region neighboring the second epitaxial region, wherein a fifth epitaxial region is between the first epitaxial region and the second epitaxial region; forming gate structures over the semiconductor fin, wherein each gate structure is disposed between a respective pair of neighboring epitaxial regions; and forming a first contact on the third epitaxial region, a second contact on the fourth epitaxial region, and a third contact on the fifth epitaxial region, wherein the epitaxial regions between the third epitaxial region and the fifth epitaxial region are free of contacts, and wherein the epitaxial regions between the fourth epitaxial region and the fifth epitaxial region are free of contacts. In an embodiment, the first doped region has the opposite doping type as the second doped region and the third doped region. In an embodiment, the method includes forming a gate contact to one gate structure disposed over the first doped region. In an embodiment, one gate structure disposed over the first doped region is a dummy gate structure. In an embodiment, the number of epitaxial regions between the third epitaxial region and the fifth epitaxial region is different than the number of epitaxial regions between the fourth epitaxial region and the fifth epitaxial region. In an embodiment, the gate structures have a pitch between 16 nm and 1500 nm. In an embodiment, the epitaxial regions and the first doped region have the same doping type.

In accordance with some embodiments of the present disclosure, a device includes a fin on a semiconductor substrate; a first transistor, including: a drain epitaxial region in the fin; a first epitaxial source region in the fin; and a first gate structure on the fin between the first epitaxial source region and the epitaxial drain region; a second transistor, including: the epitaxial drain region in the fin; a second epitaxial source region in the fin; and a second gate structure on the fin between the second epitaxial source region and the epitaxial drain region; a first resistor, including: the first epitaxial source region in the fin; a first epitaxial resistor region in the fin; and a third gate structure on the fin between the first epitaxial source region and the first epitaxial resistor region; and a second resistor, including: the second epitaxial source region in the fin; a second epitaxial resistor region in the fin; and a fourth gate structure on the fin between the second epitaxial source region and the second epitaxial resistor region. In an embodiment, the first resistor has a resistance between 150 ohms and 2000 ohms. In an embodiment, the device includes a first contact on the first gate structure, a second contact on the second gate structure, and a third contact on the third gate structure. In an embodiment, the device includes a drain contact on the epitaxial drain region, a first source contact on the first epitaxial resistor region, and a second source contact on the second epitaxial resistor region. In an embodiment, the first epitaxial source region and the second epitaxial source region are free of contacts.