Wiring structure having an intermediate layer between an upper conductive structure and conductive structure

A wiring structure includes an upper conductive structure, a lower conductive structure, a plurality of metallic structures and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The metallic structures are disposed between the upper conductive structure and the lower conductive structure, and electrically connecting the upper conductive structure and the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure, and covers the metallic structures.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a wiring structure, and a manufacturing method, and to a wiring structure including at least two conductive structures electrically connected to each other by at least one metallic structure therebetween, and a method for manufacturing the same.

2. Description of the Related Art

Along with the rapid development in electronics industry and the progress of semiconductor processing technologies, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functions. Accordingly, the semiconductor chips are provided with more input/output (I/O) connections. To manufacture semiconductor packages including semiconductor chips with an increased number of I/O connections, circuit layers of semiconductor substrates used for carrying the semiconductor chips may correspondingly increase in size. Thus, a thickness and a warpage of a semiconductor substrate may correspondingly increase, and a yield of the semiconductor substrate may decrease.

SUMMARY

In some embodiments, a wiring structure includes an upper conductive structure, a lower conductive structure, a plurality of metallic structures and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The metallic structures are disposed between the upper conductive structure and the lower conductive structure, and electrically connecting the upper conductive structure and the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure, and covers the metallic structures.

In some embodiments, a wiring structure includes a low-density stacked structure, a high-density stacked structure and a plurality of metallic structures. The low-density stacked structure includes at least one dielectric layer and at least one low-density circuit layer in contact with the dielectric layer. The high-density stacked structure includes at least one dielectric layer and at least one high-density circuit layer in contact with the dielectric layer. The metallic structures are disposed between the upper conductive structure and the lower conductive structure, and electrically connect the upper conductive structure and the lower conductive structure. A material of each of the metallic structures includes at least one build-up metal layer.

In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower conductive structure, an upper conductive structure and at least one dent structure, wherein the at least one dent structure is disposed between the upper conductive structure and the lower conductive structure to form a gap between the upper conductive structure and the lower conductive structure, wherein a portion of a circuit layer of the upper conductive structure and a portion of a circuit layer of the lower conductive structure are exposed in the gap and aligned with each other; and (b) concurrently forming a plurality of upper metallic portions in contact with the exposed portion of the circuit layer of the upper conductive structure, and a plurality of lower metallic portions in contact with the exposed portion of the circuit layer of the lower conductive structure, wherein the upper metallic portions connect the lower metallic portions to form a plurality of metallic structures.

DETAILED DESCRIPTION

To meet the specification of increasing I/O counts, a number of dielectric layers of a substrate should increase. In some comparative embodiments, a manufacturing process of a core substrate may include the following stages. Firstly, a core with two copper foils disposed on two sides thereof is provided. Then, a plurality of dielectric layers and a plurality of circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one corresponding dielectric layer. Therefore, the core substrate may include a plurality of stacked dielectric layers and a plurality of circuit layers embedded in the dielectric layers on both sides of the core. Since a line width/line space (L/S) of the circuit layers of such core substrate may be greater than or equal to 10 micrometers (μm)/10 μm, the number of the dielectric layers of such core substrate is relatively large. Although the manufacturing cost of such core substrate is low, the manufacturing yield for the circuit layers and the dielectric layers of such core substrate is also low, and, thus, the yield of such core substrate is low. In addition, each dielectric layer is relatively thick, and, thus, such core substrate is relatively thick. In some comparative embodiments, if a package has 10000 I/O counts, such core substrate may include twelve layers of circuit layers and dielectric layers. The manufacturing yield for one layer (including one circuit layer and one dielectric layer) of such core substrate may be 90%. Thus, the yield of such core substrate may be (0.9)12=28.24%. In addition, warpage of the twelve layers of circuit layers and dielectric layers may be accumulated, and, thus, the top several layers may have severe warpage. As a result, the yield of such core substrate may be further reduced.

To address the above concerns, in some comparative embodiments, a coreless substrate is provided. The coreless substrate may include a plurality of dielectric layers and a plurality of fan-out circuit layers. In some embodiments, a manufacturing process of a coreless substrate may include the following stages. Firstly, a carrier is provided. Then, a plurality of dielectric layers and a plurality of fan-out circuit layers are formed or stacked on a surface of the carrier. One fan-out circuit layer may be embedded in one corresponding dielectric layer. Then, the carrier is removed. Therefore, the coreless substrate may include a plurality of stacked dielectric layers and a plurality of fan-out circuit layers embedded in the dielectric layers. Since a line width/line space (L/S) of the fan-out circuit layers of such coreless substrate may be less than or equal to 2 μm/2 μm, the number of the dielectric layers of such coreless substrate can be reduced. Further, the manufacturing yield for the fan-out circuit layers and the dielectric layers of such coreless substrate is high. For example, the manufacturing yield for one layer (including one fan-out circuit layer and one dielectric layer) of such coreless substrate may be 99%. However, the manufacturing cost of such coreless substrate is relatively high.

At least some embodiments of the present disclosure provide for a wiring structure which has an advantageous compromise of yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure through a plurality of metallic structures. At least some embodiments of the present disclosure further provide for techniques for manufacturing the wiring structure.

FIG. 1illustrates a cross-sectional view of a wiring structure1according to some embodiments of the present disclosure.FIG. 1Aillustrates an enlarged view of an area “A” shown inFIG. 1. The wiring structure1includes an upper conductive structure2, a lower conductive structure3, an intermediate layer12and a plurality of metallic structures8.

The upper conductive structure2includes at least one dielectric layer (including, for example, two first dielectric layers20and a second dielectric layer26) and at least one circuit layer (including, for example, two first circuit layers24, a bottommost circuit layer24aand a second circuit layer28formed of a metal, a metal alloy, or other conductive material) in contact with the dielectric layer (e.g., the first dielectric layers20and the second dielectric layer26). In some embodiments, the upper conductive structure2may be similar to a coreless substrate, and may be in a wafer type, a panel type or a strip type. The upper conductive structure2may be also referred to as “a stacked structure” or “a high-density conductive structure” or “a high-density stacked structure”. The circuit layer (including, for example, the two circuit layers24) of the upper conductive structure2may be also referred to as “a high-density circuit layer”. In some embodiments, a density of a circuit line (including, for example, a trace or a pad) of the high-density circuit layer is greater than a density of a circuit line of a low-density circuit layer. That is, the count of the circuit line (including, for example, a trace or a pad) in a unit area of the high-density circuit layer is greater than the count of the circuit line in an equal unit area of the low-density circuit layer, such as about 1.2 times or greater, about 1.5 times or greater, or about 2 times or greater. Alternatively, or in combination, a line width/line space (L/S) of the high-density circuit layer is less than a L/S of the low-density circuit layer, such as about 90% or less, about 50% or less, or about 20% or less. Further, the conductive structure that includes the high-density circuit layer may be designated as the “high-density conductive structure”, and the conductive structure that includes the low-density circuit layer may be designated as a “low-density conductive structure”.

The upper conductive structure2has a top surface21and a bottom surface22opposite to the top surface21. The upper conductive structure2includes a plurality of dielectric layers (e.g., the two first dielectric layers20and the second dielectric layer26), a plurality of circuit layers (e.g., the two first circuit layers24, the bottommost circuit layer24aand the second circuit layer28) and at least one inner via25. The dielectric layers (e.g., the first dielectric layers20and the second dielectric layer26) are stacked on one another. For example, the second dielectric layer26is disposed on the first dielectric layers20, and, thus, the second dielectric layer26is the topmost dielectric layer. In some embodiments, a material of the dielectric layers (e.g., the first dielectric layers20and the second dielectric layer26) is transparent, and can be seen through by human eyes or machine. That is, a mark disposed adjacent to the bottom surface22of the upper conductive structure2can be recognized or detected from the top surface21of the upper conductive structure2by human eyes or machine. In some embodiments, a transparent material of the dielectric layers has a light transmission for a wavelength in the visible range (or other pertinent wavelength for detection of a mark) of at least about 60%, at least about 70%, or at least about 80%.

In addition, each of the first dielectric layers20has a top surface201and a bottom surface202opposite to the top surface201. The second dielectric layer26has a top surface261and a bottom surface262opposite to the top surface261. The bottom surface262of the second dielectric layer26is disposed on and contacts the top surface201of the adjacent first dielectric layer20. Thus, the top surface21of the upper conductive structure2is the top surface261of the second dielectric layer26, and the bottom surface22of the upper conductive structure2is the bottom surface202of the bottommost first dielectric layer20. The first dielectric layers20and the second dielectric layer26may include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof.

The first circuit layers24may be fan-out circuit layers or redistribution layers (RDLs), and an L/S of the first circuit layers24may be less than or equal to about 2 μm/about 2 or less than or equal to about 1.8 μm/about 1.8 Each of the first circuit layers24has a top surface241and a bottom surface242opposite to the top surface241. In some embodiments, the first circuit layer24is embedded in the corresponding first dielectric layer20, and the top surface241of the first circuit layer24may be substantially coplanar with the top surface201of the first dielectric layer20. In some embodiments, each first circuit layer24may include a seed layer243and a conductive metallic material244disposed on the seed layer243. As shown inFIG. 1, the bottommost circuit layer24ais disposed on and protrudes from the bottom surface22of the upper conductive structure2(e.g., the bottom surface202of the bottommost first dielectric layer20). An L/S of the bottommost circuit layer24amay be greater than or equal to the L/S of the first circuit layer24. In some embodiments, the bottommost circuit layer24amay include a plurality of traces and a plurality of pads245. However, in other embodiments, the bottommost circuit layer24amay solely include the pads245. In addition, the second circuit layer28is disposed on and protrudes from the top surface21of the upper conductive structure2(e.g., the top surface261of the second dielectric layer26). An L/S of the second circuit layer28may be greater than or equal to the L/S of the first circuit layer24. As illustrated in the embodiment ofFIG. 1, a horizontally connecting or extending circuit layer is omitted in the second dielectric layer26.

The upper conductive structure2further includes a plurality of inner vias25. Some of the inner vias25are disposed between two adjacent first circuit layers24for electrically connecting the two first circuit layers24. Some of the inner vias25are disposed between the first circuit layer24and the second circuit layer28for electrically connecting the first circuit layer24and the second circuit layer28. Some of the inner vias25are disposed between the first circuit layer24and the bottommost circuit layer24afor electrically connecting the first circuit layer24and the bottommost circuit layer24a. In some embodiments, each inner via25may include a seed layer251and a conductive metallic material252disposed on the seed layer251. In some embodiments, each inner via25and the corresponding first circuit layer24may be formed integrally as a monolithic or one-piece structure. Each inner via25tapers upwardly along a direction from the bottom surface22towards the top surface21of the upper conductive structure2. That is, a size (e.g., a width) of a top portion of the inner via25is less than a size (e.g., a width) of a bottom portion of the inner via25that is closer towards the bottom surface22. In some embodiments, a maximum width of the inner via25(e.g., at the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm about 15 μm or about 10 μm.

The lower conductive structure3includes at least one dielectric layer (including, for example, one first upper dielectric layer30, one second upper dielectric layer36, one first lower dielectric layer30aand one second lower dielectric layer36a) and at least one circuit layer (including, for example, one first upper circuit layer34, two second upper circuit layers38,38′, one first lower circuit layer34aand two second lower circuit layers38a,38a′ formed of a metal, a metal alloy, or other conductive material) in contact with the dielectric layer (e.g., the first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36a). In some embodiments, the lower conductive structure3may be similar to a core substrate that further includes a core portion37, and may be in a wafer type, a panel type or a strip type. The lower conductive structure3may be also referred to as “a stacked structure” or “a low-density conductive structure” or “a low-density stacked structure”. The circuit layer (including, for example, the first upper circuit layer34, the two second upper circuit layers38,38′, the first lower circuit layer34aand the two second lower circuit layers38a,38a′) of the lower conductive structure3may be also referred to as “a low-density circuit layer”. As shown inFIG. 1, the lower conductive structure3has a top surface31and a bottom surface32opposite to the top surface31. The lower conductive structure3includes a plurality of dielectric layers (for example, the first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36a), a plurality of circuit layers (for example, the first upper circuit layer34, the two second upper circuit layers38,38′, the first lower circuit layer34aand the two second lower circuit layers38a,38a′) and at least one inner via (including, for example, a plurality of upper interconnection vias35and a plurality of lower interconnection vias35a).

The core portion37has a top surface371and a bottom surface372opposite to the top surface371, and defines a plurality of through holes373extending through the core portion37. An interconnection via39is disposed or formed in each through hole373for vertical connection. In some embodiments, each interconnection via39includes a base metallic layer391and an insulation material392. The base metallic layer391is disposed or formed on a side wall of the through hole373, and defines a central through hole. The insulation material392fills the central through hole defined by the base metallic layer391. In some embodiments, the interconnection via39may omit an insulation material, and may include a bulk metallic material that fills the through hole373.

The first upper dielectric layer30is disposed on the top surface371of the core portion37, and has a top surface301and a bottom surface302opposite to the top surface301. Thus, the bottom surface302of the first upper dielectric layer30contacts the top surface371of the core portion37. The second upper dielectric layer36is stacked or disposed on the first upper dielectric layer30, and has a top surface361and a bottom surface362opposite to the top surface361. Thus, the bottom surface362of the second upper dielectric layer36contacts the top surface301of the first upper dielectric layer30, and the second upper dielectric layer36is the topmost dielectric layer. In addition, the first lower dielectric layer30ais disposed on the bottom surface372of the core portion37, and has a top surface301aand a bottom surface302aopposite to the top surface301a. Thus, the top surface301aof the first lower dielectric layer30acontacts the bottom surface372of the core portion37. The second lower dielectric layer36ais stacked or disposed on the first lower dielectric layer30a, and has a top surface361aand a bottom surface362aopposite to the top surface361a. Thus, the top surface361aof the second lower dielectric layer36acontacts the bottom surface302aof the first lower dielectric layer30a, and the second lower dielectric layer36ais the bottommost dielectric layer. As shown inFIG. 1, the top surface31of the lower conductive structure3is the top surface361of the second upper dielectric layer36, and the bottom surface32of the lower conductive structure3is the bottom surface362aof the second lower dielectric layer36a. The first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36amay include, or be formed from, a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material such as a polyamide (PA), an Ajinomoto build-up film (ABF), a bismaleimide-triazine (BT), a polyimide (PI), epoxy or polybenzoxazole (PBO), or a combination of two or more thereof.

A thickness of each of the dielectric layers (e.g., the first dielectric layers20and the second dielectric layer26) of the upper conductive structure2is less than or equal to about 40%, less than or equal to about 35%, less than or equal to about 30% of a thickness of each of the dielectric layers (e.g., the first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36a) of the lower conductive structure3. For example, a thickness of each of the dielectric layers (e.g., the first dielectric layers20and the second dielectric layer26) of the upper conductive structure2may be less than or equal to about 7 μm, and a thickness of each of the dielectric layers (e.g., the first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36a) of the lower conductive structure3may be about 40 μm.

An L/S of the first upper circuit layer34may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the first upper circuit layer34may be greater than or equal to about five times the L/S of the first circuit layers24of the upper conductive structure2. The first upper circuit layer34has a top surface341and a bottom surface342opposite to the top surface341. In some embodiments, the first upper circuit layer34is formed or disposed on the top surface371of the core portion37, and covered by the first upper dielectric layer30. The bottom surface342of the first upper circuit layer34contacts the top surface371of the core portion37. In some embodiments, the first upper circuit layer34may include a first metallic layer343, a second metallic layer344and a third metallic layer345. The first metallic layer343is disposed on the top surface371of the core portion37, and may be formed from a copper foil (e.g., may constitute a portion of the copper foil). The second metallic layer344is disposed on the first metallic layer343, and may be a plated copper layer. The third metallic layer345is disposed on the second metallic layer344, and may be another plated copper layer. In some embodiments, the third metallic layer345may be omitted.

An L/S of the second upper circuit layer38may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the second upper circuit layer38may be substantially equal to the L/S of the first upper circuit layer34, and may be greater than or equal to about five times the L/S of the first circuit layers24of the upper conductive structure2. The second upper circuit layer38has a top surface381and a bottom surface382opposite to the top surface381. In some embodiments, the second upper circuit layer38is formed or disposed on the top surface301of the first upper dielectric layer30, and covered by the second upper dielectric layer36. The bottom surface382of the second upper circuit layer38contacts the top surface301of the first upper dielectric layer30. In some embodiments, the second upper circuit layer38is electrically connected to the first upper circuit layer34through the upper interconnection vias35. In some embodiments, the second upper circuit layer38and the upper interconnection vias35are formed integrally as a monolithic or one-piece structure. Each upper interconnection via35tapers downwardly along a direction from the top surface31towards the bottom surface32of the lower conductive structure3.

In addition, in some embodiments, the second upper circuit layer38′ is disposed on and protrudes from the top surface361of the second upper dielectric layer36. In some embodiments, the second upper circuit layer38is electrically connected to the second upper circuit layer38′ through the upper interconnection vias35. As shown inFIG. 1, the second upper circuit layer38′ is the topmost circuit layer of the lower conductive structure3, and may include a plurality of traces and a plurality of pads385. However, in other embodiments, the second upper circuit layer38′ may solely include the pads385. In some embodiments, a size and a spacing of the pads385of the second upper circuit layer38′ of the lower conductive structure3is substantially equal to a size and a spacing of the pads245of the bottommost circuit layer24aof the upper conductive structure2. In addition, a position of each of the pads385of the second upper circuit layer38′ of the lower conductive structure3corresponds to a position of each of the pads245of the bottommost circuit layer24aof the upper conductive structure2. That is, each of the pads245of the bottommost circuit layer24aof the upper conductive structure2is disposed right above and aligned with each of the pads385of the second upper circuit layer38′ of the lower conductive structure3.

An L/S of the first lower circuit layer34amay be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the first lower circuit layer34amay be greater than or equal to about five times the L/S of the first circuit layers24of the upper conductive structure2. The first lower circuit layer34ahas a top surface341aand a bottom surface342aopposite to the top surface341a. In some embodiments, the first lower circuit layer34ais formed or disposed on the bottom surface372of the core portion37, and covered by the first lower dielectric layer30a. The top surface341aof the first lower circuit layer34acontacts the bottom surface372of the core portion37. In some embodiments, the first lower circuit layer34amay include a first metallic layer343a, a second metallic layer344aand a third metallic layer345a. The first metallic layer343ais disposed on the bottom surface372of the core portion37, and may be formed from a copper foil. The second metallic layer344ais disposed on the first metallic layer343a, and may be a plated copper layer. The third metallic layer345ais disposed on the second metallic layer344a, and may be another plated copper layer. In some embodiments, the third metallic layer345amay be omitted.

An L/S of the second lower circuit layer38amay be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the second lower circuit layer38amay be substantially equal to the L/S of the first upper circuit layer34, and may be greater than or equal to about five times the L/S of the first circuit layers24of the upper conductive structure2. The second lower circuit layer38ahas a top surface381aand a bottom surface382aopposite to the top surface381a. In some embodiments, the second lower circuit layer38ais formed or disposed on the bottom surface302aof the first lower dielectric layer30a, and covered by the second lower dielectric layer36a. The top surface381aof the second lower circuit layer38acontacts the bottom surface302aof the first lower dielectric layer30a. In some embodiments, the second lower circuit layer38ais electrically connected to the first lower circuit layer34athrough the lower interconnection vias35a. The lower interconnection vias35atapers upwardly along a direction from the bottom surface32towards the top surface31of the lower conductive structure3.

In addition, in some embodiments, the second lower circuit layer38a′ is disposed on and protrudes from the bottom surface362aof the second lower dielectric layer36a. In some embodiments, the second lower circuit layer38a′ is electrically connected to the second lower circuit layer38athrough the lower interconnection vias35a.

In some embodiments, each interconnection via39electrically connects the first upper circuit layer34and the first lower circuit layer34a. The base metallic layer391of the interconnection via39, the second metallic layer344of the first upper circuit layer34and the second metallic layer344athe first lower circuit layer34amay be formed integrally and concurrently as a monolithic or one-piece structure.

The metallic structures8are disposed between the upper conductive structure2and the lower conductive structure3, and electrically connect the upper conductive structure2and the lower conductive structure3. An upper end of each of the metallic structures8contacts a pad (e.g., the pads245) of a circuit layer (e.g., the bottommost circuit layer24a) of the upper conductive structure2, and a lower end of each of the metallic structures8contacts a pad (e.g., the pads385) of a circuit layer (e.g., the second upper circuit layer38′) of the lower conductive structure3. In some embodiments, each of the metallic structures8is an electroless plating structures. That is, each of the metallic structures8is formed by electroless plating. As shown inFIG. 2, the metallic structure8includes an upper metallic portion82and a lower metallic portion84, and has an interface83between the upper metallic portion82and the lower metallic portion84. The upper metallic portion82is in contact with a circuit layer (such as the pad245of the bottommost circuit layer24a) of the upper conductive structure2. The lower metallic portion84is in contact with a circuit layer (such as the pads385of the second upper circuit layer38′) of the lower conductive structure3. The metallic structure8is substantially symmetrical with respect to the interface83. That is, the upper metallic portion82of the metallic structure8is substantially mirrored with or symmetrical with the lower metallic portion84of the metallic structure8. Further, the upper metallic portion82of the metallic structure8is in contact with the lower metallic portion84of the metallic structure8at the interface83. In some embodiments, the upper metallic portion82of the metallic structure8may include a first upper layer821and a second upper layer822. The first upper layer821is disposed on a circuit layer (such as the pad245of the bottommost circuit layer24a) of the upper conductive structure2, and the second upper layer822is disposed on the first upper layer821. The lower metallic portion84of the metallic structure8may include a first lower layer841and a second lower layer842. The first lower layer841is disposed on a circuit layer (such as the pads385of the second upper circuit layer38′) of the lower conductive structure3. A material of the first upper layer821is same as a material of the first lower layer841, and a thickness of the first upper layer821is substantially equal to a thickness of the first lower layer841. In some embodiments, the material of the first upper layer821and the first lower layer841both includes nickel. In addition, a material of the second upper layer822is same as a material of the second lower layer842, and a thickness of the second upper layer822is substantially equal to a thickness of the second lower layer842. In some embodiments, the material of the second upper layer822and the second lower layer842both includes palladium or gold. In addition, the first upper layer821, the second upper layer822, the first lower layer841and the second lower layer842are formed by electroless plating, thus, they are build-up metal layers.

As shown inFIG. 2, the second upper layer822is in contact with the second lower layer842at the interface83. However, the second upper layer822and the second lower layer842may be formed integrally as a monolithic or one-piece structure, and the interface83may be omitted. Thus, the metallic structure8may include three layers. However, the three-layered metallic structure8may still be substantially symmetrical with respect to an imaginary center plane. In some embodiments, the metallic structure8may include six layers, that is, the upper metallic portion82may include three layers (e.g., a nickel layer, a palladium layer and a gold layer), and the lower metallic portion84may include three layers (e.g., a nickel layer, a palladium layer and a gold layer). However, the two gold layers may be formed integrally as a monolithic or one-piece structure, thus, the metallic structure8may include five layers.

In some embodiments, a thickness of the metallic structure8may be substantially equal to a thickness of a circuit layer (such as the first circuit layer24or the bottommost circuit layer24a) of the upper conductive structure2. For example, the thickness of the metallic structure8may be about 2 μm to about 3 and the thickness of the first circuit layer24or the bottommost circuit layer24aof the upper conductive structure2may be about 2 μm to about 3 μm. In addition, a thickness of the circuit layer (such as the first circuit layer24or the bottommost circuit layer24a) of the upper conductive structure2is less than or equal to about 40%, less than or equal to about 35%, less than or equal to about 30% of a thickness of the circuit layer (such as the first upper circuit layer34, the second upper circuit layers38,38′, the first lower circuit layer34aand the second lower circuit layers38a,38a′) of the lower conductive structure3. For example, a thickness of the circuit layer (such as the first upper circuit layer34, the second upper circuit layers38,38′, the first lower circuit layer34aand the second lower circuit layers38a,38a′) of the lower conductive structure3may be about 12 μm to about 15 μm.

The intermediate layer12is interposed or disposed between the upper conductive structure2and the lower conductive structure3, and covers the metallic structures8. The intermediate layer12may bond the upper conductive structure2and the lower conductive structure3together. That is, the intermediate layer12adheres to the bottom surface22of the upper conductive structure2and the top surface31of the lower conductive structure3. In some embodiments, the intermediate layer12may be an adhesion layer that is cured from an adhesive material (e.g., includes a cured adhesive material such as an adhesive polymeric material) or an underfill. The intermediate layer12has a top surface121and a bottom surface122opposite to the top surface121. The top surface121of the intermediate layer12contacts the bottom surface22of the upper conductive structure2, and the bottom surface122of the intermediate layer12contacts the top surface31of the lower conductive structure3. Thus, the bottommost circuit layer24aof the upper conductive structure2and the topmost circuit layer38′ (e.g., the second upper circuit layer38′) of the lower conductive structure3are embedded in the intermediate layer12.

In some embodiments, a bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers20) of the upper conductive structure2is greater than a bonding force between a dielectric layer (e.g., the bottommost first dielectric layers20) of the upper conductive structure2and the intermediate layer12. In some embodiments, a material of the intermediate layer12is transparent, and can be seen through by human eyes or machine. That is, a mark disposed adjacent to the top surface31of the lower conductive structure3can be recognized or detected from the top surface21of the upper conductive structure2by human eyes or machine. In some embodiments, the intermediate layer12is substantially free of reinforcement element such as glass fiber. That is, the intermediate layer12may include no reinforcement element such as glass fiber, and may solely include a homogeneous resin. Alternatively, the intermediate layer12may include very few reinforcement element such as glass fiber. In addition, a material of the intermediate layer12may include Ajinomoto build-up film (ABF).

As shown in the embodiment illustrated inFIG. 1andFIG. 1A, the wiring structure1is a combination of the upper conductive structure2and the lower conductive structure3, in which the first circuit layers24and the bottommost circuit layer24aof the upper conductive structure2have fine pitch, high yield and low thickness; and the circuit layers (e.g., the first upper circuit layer34, the second upper circuit layers38,38′, the first lower circuit layer34aand the second lower circuit layers38a,38a′) of the lower conductive structure3have low manufacturing cost. Thus, the wiring structure1has an advantageous compromise of yield and manufacturing cost, and the wiring structure1has a relatively low thickness. In some embodiments, if a package has 10000 I/O counts, the wiring structure1includes two layers of the first circuit layers24and a layer of the bottommost circuit layer24aof the upper conductive structure2and six layers of the circuit layers (e.g., the first upper circuit layer34, the second upper circuit layers38,38′, the first lower circuit layer34aand the second lower circuit layers38a,38a′) of the lower conductive structure3. The manufacturing yield for one layer of the first circuit layers24and the bottommost circuit layer24aof the upper conductive structure2may be 99%, and the manufacturing yield for one layer of the circuit layers (e.g., the first upper circuit layer34, the second upper circuit layers38,38′, the first lower circuit layer34aand the second lower circuit layers38a,38a′) of the lower conductive structure3may be 90%. Thus, the yield of the wiring structure1may be improved. In addition, the warpage of the upper conductive structure2and the warpage of the lower conductive structure3are separated and will not influence each other. In some embodiments, a warpage shape of the upper conductive structure2may be different from a warpage shape of the lower conductive structure3. For example, the warpage shape of the upper conductive structure2may be a convex shape, and the warpage shape of the lower conductive structure3may be a concave shape. In some embodiments, the warpage shape of the upper conductive structure2may be the same as the warpage shape of the lower conductive structure3; however, the warpage of the lower conductive structure3will not be accumulated onto the warpage of the upper conductive structure2. Thus, the yield of the wiring structure1may be further improved.

In addition, during a manufacturing process, the lower conductive structure3and the upper conductive structure2may be tested individually before being bonded together. Therefore, known good lower conductive structure3and known good upper conductive structure2may be selectively bonded together. Bad (or unqualified) lower conductive structure3and bad (or unqualified) upper conductive structure2may be discarded. As a result, the yield of the wiring structure1may be further improved.

FIG. 2illustrates a cross-sectional view of a wiring structure1aaccording to some embodiments of the present disclosure. The wiring structure1ais similar to the wiring structure1shown inFIG. 1, except for structures of an upper conductive structure2aand a lower conductive structure3a. As shown inFIG. 2, the upper conductive structure2aand the lower conductive structure3aare both strip structures. Thus, the wiring structure1ais a strip structure. In some embodiments, the lower conductive structure3amay be a panel structure that carries a plurality of strip upper conductive structures2a. Thus, the wiring structure1ais a panel structure. In addition, a lateral peripheral surface27of the upper conductive structure2ais not coplanar with (e.g., is inwardly recessed from or otherwise displaced from) a lateral peripheral surface33of the lower conductive structure3a. In some embodiments, during a manufacturing process, the lower conductive structure3aand the upper conductive structure2amay be both known good strip structures. Alternatively, the upper conductive structure2amay be a known good strip structure, and the lower conductive structure3amay be a known good panel structure. As a result, the yield of the wiring structure1amay be further improved.

As shown inFIG. 2, the upper conductive structure2aincludes at least one fiducial mark43at a corner thereof, and the lower conductive structure3ahas at least one fiducial mark45at a corner thereof. The fiducial mark43of the upper conductive structure2ais aligned with a fiducial mark45of the lower conductive structure3aduring a manufacturing process, so that the relative position of the upper conductive structure2aand the lower conductive structure3ais secured. In some embodiments, the fiducial mark43of the upper conductive structure2ais disposed on and protrudes from the bottom surface22of the upper conductive structure2a(e.g., the bottom surface202of the bottommost first dielectric layer20). The fiducial mark43and the bottommost circuit layer24amay be at, or part of, the same layer, and may be formed concurrently. Further, the fiducial mark45of the lower conductive structure3ais disposed on and protrudes from the top surface31of the lower conductive structure3a(e.g., the top surface361of the second upper dielectric layer36). The fiducial mark45and the second upper circuit layer38′ may be at, or part of, the same layer, and may be formed concurrently.

FIG. 2Aillustrates a top view of an example of a fiducial mark43aof the upper conductive structure2aaccording to some embodiments of the present disclosure. The fiducial mark43aof the upper conductive structure2ahas a continuous cross shape.

FIG. 2Billustrates a top view of an example of a fiducial mark45aof the lower conductive structure3aaccording to some embodiments of the present disclosure. The fiducial mark45aof the lower conductive structure3aincludes four square-shaped segments spaced apart at four corners.

FIG. 2Cillustrates a top view of a combination image of the fiducial mark43aof the upper conductive structure2aofFIG. 2Aand the fiducial mark45aof the lower conductive structure3aofFIG. 2B. When the upper conductive structure2ais aligned with the lower conductive structure3aprecisely, the combination image shows the complete fiducial mark43aand the complete fiducial mark45a, as shown inFIG. 2C. That is, the fiducial mark43adoes not cover or overlap the fiducial mark45afrom the top view.

FIG. 2Dillustrates a top view of an example of a fiducial mark43bof the upper conductive structure2aaccording to some embodiments of the present disclosure. The fiducial mark43bof the upper conductive structure2ahas a continuous reversed “L” shape.

FIG. 2Eillustrates a top view of an example of a fiducial mark45bof the lower conductive structure3aaccording to some embodiments of the present disclosure. The fiducial mark45bof the lower conductive structure3ahas a continuous reversed “L” shape which is substantially the same as the fiducial mark43bof the upper conductive structure2a.

FIG. 2Fillustrates a top view of a combination image of the fiducial mark43bof the upper conductive structure2aofFIG. 2Dand the fiducial mark45bof the lower conductive structure3aofFIG. 2E. When the upper conductive structure2ais aligned with the lower conductive structure3aprecisely, the combination image shows solely the fiducial mark43bof the upper conductive structure2a, as shown inFIG. 2F. That is, the fiducial mark43bcompletely covers or overlaps the fiducial mark45bfrom the top view.

FIG. 2Gillustrates a top view of an example of a fiducial mark43cof the upper conductive structure2aaccording to some embodiments of the present disclosure. The fiducial mark43cof the upper conductive structure2ahas a continuous circular shape.

FIG. 2Hillustrates a top view of an example of a fiducial mark45cof the lower conductive structure3aaccording to some embodiments of the present disclosure. The fiducial mark45cof the lower conductive structure3ahas a continuous circular shape which is larger than the fiducial mark43cof the upper conductive structure2a.

FIG. 2Iillustrates a top view of a combination image of the fiducial mark43cof the upper conductive structure2aofFIG. 2Gand the fiducial mark45cof the lower conductive structure3aofFIG. 2H. When the upper conductive structure2ais aligned with the lower conductive structure3aprecisely, the combination image shows two concentric circles, as shown inFIG. 2I. That is, the fiducial mark43cis disposed at the center of the fiducial mark45b.

FIG. 3illustrates a cross-sectional view of a wiring structure1baccording to some embodiments of the present disclosure. The wiring structure1bis similar to the wiring structure1shown inFIG. 1, except for structures of the metallic structures8b. As shown inFIG. 3, the metallic structure8bmay include second layers, that is, the upper metallic portion may include one layer (e.g., a nickel layer, a palladium layer or a gold layer), and the lower metallic portion may include one layer (e.g., a nickel layer, a palladium layer or a gold layer). However, the two layers may be formed integrally as a monolithic or one-piece structure, thus, the metallic structure8may solely include one layer.

FIG. 4illustrates a cross-sectional view of a wiring structure1caccording to some embodiments of the present disclosure. The wiring structure1cis similar to the wiring structure1shown inFIG. 1, except that the metallic structure8is replaced by a solder material8c. The solder material8cis not formed by electroless plating, thus, it is not a build-up metal layer.

FIG. 5illustrates a cross-sectional view of a wiring structure1daccording to some embodiments of the present disclosure. The wiring structure1dis similar to the wiring structure1shown inFIG. 1, except that at least one conductive via14is further included. The conductive via14is formed of a metal, a metal alloy, or other conductive material, extends through the upper conductive structure2and the intermediate layer12, and is electrically connected to the second upper circuit layer38of the lower conductive structure3. A length (along a longitudinal axis) of the conductive via14is greater than a thickness of the high-density conductive structure (e.g., the upper conductive structure2). Further, the conductive via14tapers downwardly. Thus, a tapering direction of the inner via25of the upper conductive structure2is different from a tapering direction of the conductive via14. In some embodiments, the conductive via14is a monolithic structure or a one-piece structure having a homogeneous material composition, and a peripheral surface of the conductive via14is a substantially continuous surface without boundaries. The conductive via14and the second circuit layer28may be formed integrally as a monolithic or one-piece structure. In some embodiments, a maximum width of the conductive via14may be less than about 40 such as about 30 μm or about 20 In some embodiments, the conductive via14may extend through the lower conductive structure3or the wiring structure1dto electrically connect the upper conductive structure2and the lower conductive structure3.

As shown inFIG. 5, the upper conductive structure2includes a high-density region41and a low-density region47. In some embodiments, a density of a circuit line (including, for example, a trace or a pad) in the high-density region41is greater than a density of a circuit line in the low-density region47. That is, the count of the circuit line (including, for example, the trace or the pad) in a unit area within the high-density region41is greater than the count of the circuit line in an equal unit area within the low-density region47. Further, the conductive via14is disposed in the low-density region47of the high-density conductive structure (e.g., the upper conductive structure2). In some embodiments, the high-density region41may be a chip bonding area.

FIG. 6illustrates a cross-sectional view of a wiring structure1eaccording to some embodiments of the present disclosure. The wiring structure1eis similar to the wiring structure1shown inFIG. 1, except that at least one dent structure86is further included. The dent structure86is disposed between the upper conductive structure2and the lower conductive structure3. An upper end of the dent structure86contacts a dielectric layer (e.g., the first dielectric layer20) of the upper conductive structure2, and a lower end of the dent structure86contacts a dielectric layer (e.g., the second upper dielectric layer36) of the lower conductive structure3. A material of the dent structure86includes a polymer material (such as solder mask) rather than metal material. As shown inFIG. 6, the dent structure86includes an upper dent portion861and a lower dent portion862. The upper dent portion861is disposed on the (e.g., the first dielectric layer20) of the upper conductive structure2, and the lower dent portion862is disposed on the dielectric layer (e.g., the second upper dielectric layer36) of the lower conductive structure3. The upper dent portion861is in contact with the lower dent portion862. Thus, the upper dent portion861is adhered to the lower dent portion862, and there may be a boundary between the upper dent portion861and the lower dent portion862. In addition, the dent structure86is a standoff structure that provides the gap between a circuit layer (such as the pad245of the bottommost circuit layer24a) of the upper conductive structure2and a circuit layer (such as the pads385of the second upper circuit layer38′) of the lower conductive structure3before the metallic structures8are formed.

FIG. 7illustrates a cross-sectional view of a wiring structure if according to some embodiments of the present disclosure. The wiring structure if is similar to the wiring structure1ashown inFIG. 2, except for structures of an upper conductive structure2fand a lower conductive structure3f. The upper conductive structure2fand the lower conductive structure3fare both dice and may be singulated concurrently. Thus, the wiring structure if is a unit structure. That is, a lateral peripheral surface27fof the upper conductive structure2fand a lateral peripheral surface33fof the lower conductive structure3fare substantially coplanar with each other. In addition, at least one dent structure86is further included. The dent structure86is disposed between the upper conductive structure2fand the lower conductive structure3f. An upper end of the dent structure86contacts a dielectric layer (e.g., the first dielectric layer20) of the upper conductive structure2f, and a lower end of the dent structure86contacts a dielectric layer (e.g., the second upper dielectric layer36) of the lower conductive structure3fAs shown inFIG. 7, the dent structure86includes an upper dent portion861and a lower dent portion862. The upper dent portion861is disposed on the (e.g., the first dielectric layer20) of the upper conductive structure2f, and the lower dent portion862is disposed on the dielectric layer (e.g., the second upper dielectric layer36) of the lower conductive structure3f. In addition, the dent structure86is a standoff structure that provides the gap between a circuit layer (such as the pad245of the bottommost circuit layer24a) of the upper conductive structure2fand a circuit layer (such as the pads385of the second upper circuit layer38′) of the lower conductive structure3fbefore the metallic structures8are formed. It is noted that if the dent structure86and the fiducial marks43,45are disposed within a saw street, they may be disregarded after a singulation process.

FIG. 8illustrates a top view of the wiring structure if ofFIG. 7, wherein a second circuit layer28of the upper conductive structure2fis omitted for the purpose of the clear explanation. As shown inFIG. 8, the dent structures86are strip structures, and are disposed adjacent to two lateral peripheral surfaces respectively. As shown inFIG. 7, the lateral peripheral surface27fof the upper conductive structure2f, a lateral peripheral surface of the dent structures86aand the lateral peripheral surface33fof the lower conductive structure3fare substantially coplanar with each other.

FIG. 9illustrates a cross-sectional view of a bonding of a package structure4and a substrate46according to some embodiments. The package structure4includes a wiring structure1g, a semiconductor chip42, a plurality of first connecting elements44and a plurality of second connecting elements48. The wiring structure1gofFIG. 9is similar to the wiring structure1shown inFIG. 1, except for structures of an upper conductive structure2gand a lower conductive structure3g. The upper conductive structure2gand the lower conductive structure3gare both dice and may be singulated concurrently. Thus, the wiring structure1gis a unit structure. That is, a lateral peripheral surface27gof the upper conductive structure2g, a lateral peripheral surface33gof the lower conductive structure3gand a lateral peripheral surface of the intermediate layer12are substantially coplanar with each other. The semiconductor chip42is electrically connected and bonded to the second circuit layer28of the upper conductive structure2gthrough the first connecting elements44(e.g., solder bumps or other conductive bumps). The second lower circuit layer38a′ of the lower conductive structure3gis electrically connected and bonded to the substrate46(e.g., a mother board such as a printed circuit board (PCB)) through the second connecting elements48(e.g., solder bumps or other conductive bumps).

FIG. 10throughFIG. 35illustrate a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing the wiring structure1shown inFIG. 1, the wiring structure1eshown inFIG. 6and/or the package structure4shown inFIG. 9.

Referring toFIG. 10throughFIG. 21, a lower conductive structure3is provided. The lower conductive structure3is manufactured as follows. Referring toFIG. 10, a core portion37with a top copper foil50and a bottom copper foil52is provided. The core portion37may be in a wafer type, a panel type or a strip type. The core portion37has a top surface371and a bottom surface372opposite to the top surface371. The top copper foil50is disposed on the top surface371of the core portion37, and the bottom copper foil52is disposed on the bottom surface372of the core portion37.

Referring toFIG. 11, a plurality of through holes373are formed to extend through the core portion37, the top copper foil50and the bottom copper foil52by a drilling technique (such as laser drilling or mechanical drilling) or other suitable techniques.

Referring toFIG. 12, a second metallic layer54is formed or disposed on the top copper foil50, the bottom copper foil52and side walls of the first through holes373by a plating technique or other suitable techniques. A portion of the second metallic layer54on the side wall of each first through hole373defines a central through hole.

Referring toFIG. 13, an insulation material392is disposed to fill the central through hole defined by the second metallic layer54.

Referring toFIG. 14, a top third metallic layer56and a bottom third metallic layer56aare formed or disposed on the second metallic layer54by a plating technique or other suitable techniques. The third metallic layers56,56acover the insulation material392.

Referring toFIG. 15, a top photoresist layer57is formed or disposed on the top third metallic layer56, and a bottom photoresist layer57ais formed or disposed on the bottom third metallic layer56a. Then, the photoresist layers57,57aare patterned by exposure and development.

Referring toFIG. 16, portions of the top copper foil50, the second metallic layer54and the top third metallic layer56that are not covered by the top photoresist layer57are removed by an etching technique or other suitable techniques. Portions of the top copper foil50, the second metallic layer54and the top third metallic layer56that are covered by the top photoresist layer57remain to form a first upper circuit layer34. Meanwhile, portions of the bottom copper foil52, the second metallic layer54and the bottom third metallic layer56athat are not covered by the bottom photoresist layer57aare removed by an etching technique or other suitable techniques. Portions of the bottom copper foil52, the second metallic layer54and the bottom third metallic layer56athat are covered by the bottom photoresist layer57aremain to form a first lower circuit layer34a. Meanwhile, portions of the second metallic layer54and the insulation material392that are disposed in the through hole373form an interconnection via39. In some embodiments, the first upper circuit layer34may include a first metallic layer343, a second metallic layer344and a third metallic layer345. The first metallic layer343is disposed on the top surface371of the core portion37, and may be formed from a portion of the top copper foil50. The second metallic layer344is disposed on the first metal layer343, and may be a plated copper layer formed from the second metallic layer54. The third metallic layer345is disposed on the second metallic layer344, and may be another plated copper layer formed from the top third metallic layer56.

In some embodiments, the first lower circuit layer34amay include a first metallic layer343a, a second metallic layer344aand a third metallic layer345a. The first metallic layer343ais disposed on the bottom surface372of the core portion37, and may be formed from a portion of the bottom copper foil52. The second metallic layer344ais disposed on the first metallic layer343a, and may be a plated copper layer formed from the second metallic layer54. The third metallic layer345ais disposed on the second metallic layer344a, and may be another plated copper layer formed from the bottom third metallic layer56a. The interconnection via39includes a base metallic layer391formed from the second metallic layer54and the insulation material392. In some embodiments, the interconnection via39may include a bulk metallic material that fills the through hole373. The interconnection via39electrically connects the first upper circuit layer34and the first lower circuit layer34a.

Referring toFIG. 17, the top photoresist layer57and the bottom photoresist layer57aare removed by a stripping technique or other suitable techniques.

Referring toFIG. 18, a first upper dielectric layer30is formed or disposed on the top surface371of the core portion37to cover the top surface371of the core portion37and the first upper circuit layer34by a lamination technique or other suitable techniques. Meanwhile, a first lower dielectric layer30ais formed or disposed on the bottom surface372of the core portion37to cover the bottom surface372of the core portion37and the first lower circuit layer34aby a lamination technique or other suitable techniques. Then, at least one through hole303is formed to extend through the first upper dielectric layer30to expose a portion of the first upper circuit layer34by a drilling technique or other suitable techniques. Meanwhile, at least one through hole303ais formed to extend through the first lower dielectric layer30ato expose a portion of the first lower circuit layer34aby a drilling technique or other suitable techniques.

Referring toFIG. 19, a second upper circuit layer38is formed on the first upper dielectric layer30, and an upper interconnection via35is formed in the through hole303. Meanwhile, a second lower circuit layer38ais formed on the first lower dielectric layer30a, and a lower interconnection via35ais formed in the through hole303a.

Referring toFIG. 20, a second upper dielectric layer36is formed or disposed on the top surface301of the first upper dielectric layer30to cover the top surface301of the first upper dielectric layer30and the second upper circuit layer38by a lamination technique or other suitable techniques. Meanwhile, a second lower dielectric layer36ais formed or disposed on the bottom surface302aof the first lower dielectric layer30ato cover the bottom surface302aof the first lower dielectric layer30aand the second lower circuit layer38aby a lamination technique or other suitable techniques. Then, at least one through hole363is formed to extend through the second upper dielectric layer36to expose a portion of the second upper circuit layer38by a drilling technique or other suitable techniques. Meanwhile, at least one through hole363ais formed to extend through the second lower dielectric layer36ato expose a portion of the second lower circuit layer38aby a drilling technique or other suitable techniques.

Referring toFIG. 21, a second upper circuit layer38′ is formed on the second upper dielectric layer36, and an upper interconnection via35is formed in the through hole363. Meanwhile, a second lower circuit layer38a′ is formed on the second lower dielectric layer36a, and a lower interconnection via35ais formed in the through hole363a. It is noted that the second upper circuit layer38′ is the topmost circuit layer of the lower conductive structure3, and may include a plurality of traces and a plurality of pads385. However, in other embodiments, the second upper circuit layer38′ may solely include the pads385.

Meanwhile, the lower conductive structure3is formed, and the dielectric layers (including, the first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36a) are cured. At least one of the circuit layers (including, for example, one first upper circuit layer34, two second upper circuit layers38,38′, one first lower circuit layer34aand two second lower circuit layers38a,38a′) is in contact with at least one of the dielectric layers (e.g., the first upper dielectric layer30, the second upper dielectric layer36, the first lower dielectric layer30aand the second lower dielectric layer36a). The lower conductive structure3may be a wafer structure, a strip structure or a panel structure. Then, an electrical property (such as open circuit/short circuit) of the lower conductive structure3is tested.

Referring toFIG. 22, a lower dent portion862is formed or disposed on the second upper dielectric layer36of the lower conductive structure3. A thickness of the lower dent portion862may be greater than a thickness of the second upper circuit layer38′.

The upper conductive structure2is manufactured as follows. Referring toFIG. 23, a carrier65is provided. The carrier65may be a glass carrier, and may be in a wafer type, a panel type or a strip type. Then, a release layer66is coated on a bottom surface of the carrier65. Then, a conductive layer67(e.g., a seed layer) is formed or disposed on the release layer66by a physical vapor deposition (PVD) technique or other suitable techniques.

Referring toFIG. 24, a second dielectric layer26is formed on the conductive layer67by a coating technique or other suitable techniques. Then, at least one through hole264is formed to extend through the second dielectric layer26to expose a portion of the conductive layer67by an exposure and development technique or other suitable techniques.

Referring toFIG. 25, a seed layer68is formed on a bottom surface262of the second dielectric layer26and in the through hole264by a PVD technique or other suitable techniques. Then, a photoresist layer69is formed on the seed layer68. Then, the photoresist layer69is patterned to expose portions of the seed layer68by an exposure and development technique or other suitable techniques. The photoresist layer69defines a plurality of openings691. At least one opening691of the photoresist layer69corresponds to, and is aligned with, the through hole264of the second dielectric layer26.

Referring toFIG. 26, a conductive material70(e.g., a metallic material) is disposed in the openings691of the photoresist layer69and on the seed layer68by a plating technique or other suitable techniques.

Referring toFIG. 27, the photoresist layer69is removed by a stripping technique or other suitable techniques.

Referring toFIG. 28, portions of the seed layer68that are not covered by the conductive material70are removed by an etching technique or other suitable techniques. Meanwhile, a circuit layer24and at least one inner via25are formed.

Referring toFIG. 29, a plurality of first dielectric layers20and a plurality of circuit layers (including the first circuit layer24and the bottommost circuit layer24a) are formed by repeating the stages ofFIG. 24toFIG. 28. In some embodiments, the bottommost circuit layer24amay include a plurality of traces and a plurality of pads245. However, in other embodiments, the bottommost circuit layer24amay solely include the pads245. Meanwhile, the upper conductive structure2is formed, and the dielectric layers (including, the first dielectric layers20and the second dielectric layer26) are cured. At least one of the circuit layers (including, for example, the first circuit layers24and the bottommost circuit layer24a) is in contact with at least one of the dielectric layers (e.g., the first dielectric layers20and the second dielectric layer26). The upper conductive structure2may be a wafer structure, a strip structure or a panel structure. Then, an electrical property (such as open circuit/short circuit) of the upper conductive structure2is tested.

Referring toFIG. 30, an upper dent portion861is formed or disposed on the bottommost first dielectric layer20of the upper conductive structure2.

Referring toFIG. 31, the upper conductive structure2is attached to the lower conductive structure3through the upper dent portion861and the lower dent portion862. The upper dent portion861is in contact with or adhered to the lower dent portion862to form a dent structure86so as to provide a gap between the pads245of the bottommost circuit layer24aof the upper conductive structure2and the pads385of the second upper circuit layer38′ of the lower conductive structure3. Further, the dent structure86also form a gap between the upper conductive structure2and the lower conductive structure3. In some embodiments, a size and a spacing of the pads385of the second upper circuit layer38′ of the lower conductive structure3is substantially equal to a size and a spacing of the pads245of the bottommost circuit layer24aof the upper conductive structure2. In addition, a position of each of the pads385of the second upper circuit layer38′ of the lower conductive structure3corresponds to a position of each of the pads245of the bottommost circuit layer24aof the upper conductive structure2.

Referring toFIG. 32, a plurality of first upper layers821and a plurality of first lower layers841are formed concurrently by, for example, depositing such as electroplating, electroless plating, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first upper layer821is disposed on a circuit layer (such as the pad245of the bottommost circuit layer24a) of the upper conductive structure2, and the first lower layer841is disposed on a circuit layer (such as the pads385of the second upper circuit layer38′) of the lower conductive structure3. A material of the first upper layer821is same as a material of the first lower layer841, and a thickness of the first upper layer821is substantially equal to a thickness of the first lower layer841. In some embodiments, the material of the first upper layer821and the first lower layer841both includes nickel.

Referring toFIG. 33, a plurality of second upper layers822and a plurality of second lower layers842are formed concurrently by, for example, depositing such as electroplating, electroless plating, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The second upper layer822is disposed on the first upper layer821, and the second lower layer842is disposed on the first lower layer841. A material of the second upper layer822is same as a material of the second lower layer842, and a thickness of the second upper layer822is substantially equal to a thickness of the second lower layer842. In some embodiments, the material of the second upper layer822and the second lower layer842may include palladium or gold.

Meanwhile, the second upper layers822and the first upper layers821form a plurality of upper metallic portions82. The second lower layers842and the first lower layers841form a plurality of lower metallic portions84. The upper metallic portions82are in contact with the exposed portion of the circuit layer (such as the pads245of the bottommost circuit layer24a) of the upper conductive structure2, and the lower metallic portions84are in contact with the exposed portion of the circuit layer (such as the pads385of the second upper circuit layer38′) of the lower conductive structure3. The upper metallic portions82connect or adhere the lower metallic portions84to form a plurality of metallic structures8.

Referring toFIG. 34, an adhesive layer12is applied into the gap between the upper conductive structure2and the lower conductive structure3to bond the lower conductive structure3and the upper conductive structure2together, and to cover the metallic structures8. Then, the adhesive layer12is cured to form an intermediate layer12.

Referring toFIG. 35, the carrier65, the release layer66and the conductive layer67are removed. Then, a second circuit layer28is formed or disposed on the top surface21of the upper conductive structure2, so as to obtain the wiring structure1ofFIG. 1or the wiring structure1eof inFIG. 6. It is noted thatFIG. 1selectively shows a region of the wiring structure1without the dent structure86.

In some embodiments, a singulation process is conducted along the saw streets9to form a plurality of wiring structures1gofFIG. 9. The wiring structure1gofFIG. 9includes a singulated upper conductive structure2gand a singulated lower conductive structure3g. That is, a lateral peripheral surface27gof the upper conductive structure2g, a lateral peripheral surface33gof the lower conductive structure3gand a lateral peripheral surface of the intermediate layer12are substantially coplanar with each other. Then, a semiconductor chip42(FIG. 9) is electrically connected and bonded to the second circuit layer28of the upper conductive structure2through a plurality of first connecting elements44(e.g., solder bumps or other conductive bumps), so as to from a package structure4as shown inFIG. 9. Then, the second lower circuit layer38a′ of the lower conductive structure3gis electrically connected and bonded to a substrate46(e.g., a mother board such as a PCB) through a plurality of second connecting elements48(e.g., solder bumps or other conductive bumps).

FIG. 36throughFIG. 39illustrate a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing the wiring structure1dshown inFIG. 5. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIG. 10toFIG. 35.FIG. 36depicts a stage subsequent to that depicted inFIG. 35.

Referring toFIG. 36, at least one hole23is formed to extend through the upper conductive structure2, the intermediate layer12and a portion of the lower conductive structure3by drilling (such as laser drilling) to exposes a circuit layer (e.g., second upper circuit layers38) of the lower conductive structure3. In some embodiments, the hole23tapers downwardly.

Referring toFIG. 37, a metallic layer72is formed or disposed on the top surface21of the upper conductive structure2and in the hole23to form at least one conductive via14in the hole23by plating technique or other suitable technique(s).

Referring toFIG. 38, a top photoresist layer73is formed or disposed on the metallic layer72, and a bottom photoresist layer73ais formed or disposed on the bottom surface32of the lower conductive structure3. Then, the top photoresist layer73is patterned by exposure and development technique or other suitable technique(s).

Referring toFIG. 39, the portions of the metallic layer72that are not covered by the top photoresist layer73is removed by etching technique or other suitable technique(s). The portions of the metallic layer72that are covered by the top photoresist layer73remain to form a second circuit layer28. Then, the top photoresist layer73and the bottom photoresist layer73aare removed by stripping technique or other suitable technique(s), so as to obtain the wiring structure1dofFIG. 5. It is noted thatFIG. 1selectively shows a region of the wiring structure1dwithout the dent structure86.