Non-volatile semiconductor memory

A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

TECHNICAL FIELD

The present invention relates to non-volatile semiconductor memories and to methods for operating such memories.

BACKGROUND

Flash memories are high density non-volatile memories and may be divided into data flash and code flash memories.

Data flash memories are typically used for storing large data volumes in applications such as digital cameras, MP3 players and other electronic products. These applications require a large numbers of cells in each sector. The requirements regarding the reliability of data flash memories are less strict than for code flash memories. In order to minimize the area required for each memory cell, NAND architectures are used. However, NAND architectures lead to slower access times.

Code flash memories are typically used for storing program code in applications such as personal computers, mobile telephones, personal digital assistants and other electronic devices. This type of memory needs to meet higher reliability demands than data flash memories. NOR architectures are used to reduce access times. As smaller portions of memories need to be accessible for read, write or erase operations, sectors in code flash memories are smaller than in data flash memories.

The storage capacity of flash memories can be increased by increasing the number of bits stored per cell. Nitride programmable read only memory (NROM) cells can store two bits per cell and are based on charge trapping in a nitride layer of an ONO (oxide-nitride-oxide) gate dielectric. Charge is localized in two regions of the nitride layer of each cell and the charge stored in each region can be manipulated independently. For each region, the amount of electrical charge stored determines the threshold voltage values Vth of the cell. A high threshold value Vth corresponds to a high ‘1’ state and a low threshold value Vth ‘0’ to a low state. By applying a gate voltage that is between the high and low threshold voltage and sensing the current flowing through the transistor, the state stored in each region of the NROM cell can be determined. Apart from being able to store two bits per cell, NROM cell based memories further have the advantage of requiring minimal electrical power and a low production complexity.

In contrast to other flash memory technologies which depending on the type of flash memory use either a NOR or NAND architecture, NROM based memories can use the so-called “virtual ground array” architecture for both data flash and code flash memories.FIG. 1shows such a virtual ground array26. Individual memory cells23are arranged along rows and columns to form a matrix. The gates of memory cells23arranged along rows are connected by word lines3. The drain and source contacts of memory cells23arranged along columns are connected to bit lines4, with each bit line4being shared between two neighboring cells (23) along rows. Each memory cell23in the array26can be selected by the respective word line3and bit lines4corresponding to the row and the column in which the memory cell is located.

Memory cells are usually grouped together in sectors so that operations, such as erasing, may easily and simultaneously be preformed on a large number of memory cells. In general a word line will pass through more than one sector, connecting the gate electrodes of memory cells belonging to different sectors. Because of the shared word line common to memory cells of plural sectors, not only the memory cells in the sector that is to be erased are biased with a high negative or positive voltage at the gate necessary for this operation. In addition, also memory cells of other sectors not to be erased but connected to the same word line are biased. The states stored in memory cells of these sectors will usually not be changed because no voltage is applied to their bit lines. However, the voltage applied to the gates of the non-selected memory cells are high enough to affect the electric charge stored in the ONO layer of the memory cells over a large number of such program or erase cycles. As a result, the threshold voltages Vth in those cells change so that it is no longer possible to distinguish between the high and low state. This is known as “gate disturb” and can lead to wrong values being read out from the memory cells.

In most flash memory products gate disturb is not suppressed even though it leads to reduced reliability of the memory. Efforts to reduce the effects of gate disturb include optimizing the thickness of, for example, the ONO layer. In another approach word lines are divided into separate word lines for each sector. The gates of the cells to be erased are connected to a word line by using a sector specific select transistor. However, this approach leads to more complicated memory constructions.

SUMMARY OF THE INVENTION

Accordingly, in one aspect, the invention provides a non-volatile semiconductor memory in which gate disturb is minimized during the erase operation. Another aspect of the invention provides a method for operating non-volatile semiconductor memories in such a way that gate disturb is reduced during the erase operation. In a further aspect, the invention reduces the current needed for erasing cells in the non-volatile semiconductor memory.

The invention provides, in accordance with a first preferred embodiment, a non-volatile semiconductor memory comprising a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connects memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element, and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Since the first wells of the sectors are electrically insulated from each other and from the substrate by the insulating elements, they do not share electrical potentials. Therefore, erasing cells in a sector by applying the required electrical potentials will not affect the cells in other sectors. However, in order to erase cells a potential difference between the gate and the channel of a cell is required. This is achieved in the invention by electrically connecting the first wells, in which the channels of the cells are embedded in, to a predetermined potential by means of the switching elements.

Preferably, the predetermined potential to which each first well is biasable by means of the respective switching element is one of a substrate potential of the substrate region, a ground potential and a word line potential. Which potential is chosen as the predetermined potential depends on whether or not the first well contains memory cells that are to be erased or not. If the first well of a sector contains memory cells whose contents are to be erased the predetermined potential is chosen to be a substrate or a ground potential. In this case the first well is connected to substrate or ground and the potential difference between the channel and the gate of the cell necessary for erasing the cell can be applied. At the same time, if the sector contains memory cells whose contents are not to be erased, the predetermined potential is chosen to be a word line potential. In this case both the channel and the gate of the memory cell are at the word line potential and no potential difference exists between them. As a result, gate disturb is eliminated when erasing cells in another sector.

Preferably, the switching elements are transistors, each transistor comprising a first and second source/drain contact. The first source/drain contact is connected to the respective first well and the second source/drain contact is connected to the predetermined potential. Using transistors such as field effect transistors the first wells can be connected to the required predetermined potential. The transistors may be implemented in the same substrate as the memory.

Alternatively, each switching element comprises a first and a second transistor each having a first and a second source/drain contact. A first source/drain contact of the respective first transistor is connected to a word line potential and a second source/drain contact of the first transistor is connected to the respective first well. A first source/drain contact of the respective second transistor is connected to a substrate potential and a second source/drain contact of the second transistor is connected to the respective first well. The transistors are used to connect the respective first wells to either a word line or a substrate potential, depending on whether the first well contains memory cells that are to be protected against gate disturb or that are to be erased. The first and second transistor may be of opposite polarity, for example NMOS and PMOS transistors and may be controlled by the same electrical signal connected to the gates.

There is also provided, in accordance with a second embodiment, a non-volatile semiconductor memory comprising a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well, the at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element, and the semiconductor memory is constructed such that each first well is electrically disconnectable from the substrate region by means of the respective switching element. Again, as in the first embodiment, the first wells of the sectors are electrically insulated from each other and from the substrate by the insulating elements. In order to erase cells a potential difference between the gate and the channel of a memory cell is required. This is achieved by electrically connecting the first wells in which the channels of the memory cells are embedded into a substrate potential by means of the switching elements. To avoid gate disturb in the memory cells that are not to be erased, the first wells in which these memory cells are embedded are disconnected from the substrate potential by means of the respective switching element. The potential of these first wells floats and assumes a level close to the word line potential, so that again the potential difference between the channel and the gate is reduced and gate disturb minimized.

Preferably, the switching elements are transistors, each transistor comprising a first and second source/drain contact. The first source/drain contact is connected to the respective first well and the second source/drain contact is connected to the substrate region. Using transistors such as field effect transistors the first wells can be connected and disconnected from the substrate potential. The transistors may be implemented in the same substrate as the memory.

Regarding the insulating elements, according to the first and second preferred embodiments, the insulating elements each preferably comprise a well of a second doping type opposite to the first doping type; each first well being embedded in a respective well of the second doping type. The first wells and the wells in which they are embedded are of opposite doping type. As a result a depletion layer which electrically insulates the two wells is formed between the two wells. As the well of the second doping type embeds the first well, the first well is electrically insulated from the substrate as well as from adjacent first wells.

Alternatively, the insulating elements comprise an isolation well of a second doping type opposite of the first doping type, all first wells being embedded in the isolation well, and shallow trench isolation structures laterally separating the first wells other from one another. Electrical insulation of the first wells from the substrate is achieved by using a single large well of opposite doping type to the first wells in which all the first wells are embedded. Again, a depletion layer is formed where the wells meet. However, the first wells are not electrically insulated from each other by the single large well so that in addition shallow trench isolation structures are placed between the first wells.

Furthermore, alternatively, the insulating elements comprise a buried insulation layer arranged between the substrate region and the first wells, and shallow trench isolation structures laterally separating the first wells from one another. Instead of using a depletion layer for insulating the first wells from the substrate as described above, a buried insulation layer is used. This layer may be an oxide layer. The first wells are further electrically insulated from each other by shallow trench isolation structures placed between adjacent first wells.

Preferably, the substrate is a silicon-on-insulator substrate. In a silicon-on-insulator substrate the substrate region is insulated from the silicon layer in which the wells are formed by a insulation layer of, for example, silicon oxide and the first wells are formed in the silicon. The advantage of using a silicon-on-insulator substrate is that very little space is required for the insulation layer.

Regarding the memory cells, according to the first or second preferred embodiment, the memory cells are nitride programmable read only memory (NROM) cells. NROM cells are the preferred cell type as they can be used in a virtual ground array for code flash and data flash memories. However, the invention can also be used with other cell types, such as floating gate memory cells.

Preferably, the nitride programmable read only memory cells each comprise a nitride layer sandwiched between two oxide layers. Electric charges are storable in the nitride layer, which is located in a gate stack above the channel of the cell. The charges tunnel from the channel of the memory cell into the nitride layer if the required voltages are applied to the word lines and the bit lines. Because of the insulation provided by the two oxide layers the charges will remain in the nitride layer even if no further voltages are applied.

Specifically, the semiconductor memory comprises bit lines arranged in the substrate and the memory cells are constructed such that electrical charges are storable in the nitride layer on two respective sides of the bit lines. By storing charges in two separate positions in the nitride layer, it is possible to store two bits per cell. The two bits can be selectively read, programmed or erased by applying the required voltages to the respective bit lines and the gate of the memory cell.

Alternatively, regarding the memory cells, according to the first or second preferred embodiment, the semiconductor memory is an electrically erasable programmable read only memory.

Preferably, according to any one of the first and second embodiments, the memory cells are connected to the bit lines such as to form a virtual ground array. A virtual ground array has the advantage of being randomly accessible like a NOR architecture while at the same time being very compact like a NAND architecture. The memory cells may also be connected to form other architectures.

Preferably, the semiconductor memory comprises a plurality of word lines arranged in groups of word lines. The sectors are arranged along a first and a second direction across a substrate surface. Memory cells of sectors arranged adjacent to one another along the first direction are electrically connected to word lines of a same respective group of word lines, and memory cells of sectors adjacent to one another along the second direction are electrically connected to word lines of other groups of word lines. In this way it is possible to erase all the memory cells in one sector by applying the erase potential to all the word lines connecting memory cells in that sector. Memory cells in sectors along the second direction may share the same bit lines as memory cells in sectors along the first direction but are not erased as no word line potential is applied.

Preferably, in each sector the memory cells arranged along the first direction are connected to a same word line. In this way only one word line is required for reading, programming or erasing the cells connected to the word line.

Preferably, in each sector the memory cells arranged along the second direction are connected to different word lines. Together with the respective bit lines it is possible to select individual cells for read, program or erase operations by applying the necessary potentials to the respective bit lines of the cell.

According to embodiments of the invention, a first method for operating a non-volatile semiconductor memory is provided, the semiconductor memory comprising a substrate having a substrate region, comprising at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. The memory cells of a first group of sectors are connected to a first group of word lines. Erasing the memory cells of a first sector of the first group of sectors selectively to memory cells of all other sectors of the first group of sectors comprises the steps of: electrically connecting the first well of the first sector to a first predetermined potential, and electrically connecting the first wells of all other sectors of the first group of sectors to a second predetermined potential different from the first predetermined potential. By connecting the first well of the first sector to the first predetermined potential, the potential difference between the channel and the gate required to erase the cells in the first sector can be applied. By connecting the first wells of all the other sectors to the second predetermined potential, different from the first predetermined potential, the potential difference between the channel and the gate can be minimized, thus reducing gate disturb.

Preferably, according to the first method, the first well of each sector is connected to a respective switching element. By means of the respective switching elements, the first well of the first sector is connected to a first predetermined potential and the first wells of all other sectors of the first group of sectors are connected to the second predetermined potential when the first sector is erased. The switching element can connect the first wells to alternatively the first or the second predetermined potential, depending on whether the cells in the first well are to be erased or protected from gate disturb.

Preferably, according to the first method, each first well is connected to a respective switching element, the first well of the first sector is biased to the first predetermined potential and the first wells of all other sectors of the first group of sectors are biased to the second predetermined potential by means of the respective switching elements at a time when the memory cells of the first sector are erased. In this way the potential difference between the channel and the gate is large enough to erase the cells in the first sector while the potential difference between the channel and the gate of the cells in all other sectors is negligible, thus reducing gate disturb.

According to embodiments of the invention, a second method for operating a non-volatile semiconductor memory is provided, the semiconductor memory comprising a substrate having a substrate region, comprising at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. The memory cells of a first group of sectors being connected to a first group of word lines. Erasing the memory cells of a first sector of the first group of sectors selectively to memory cells of all other sectors of the first group of sectors comprises the steps of: electrically connecting the first well of the first sector to a first predetermined potential, and electrically disconnecting the first wells of all other sectors of the first group of sectors from the first predetermined potential. By connecting the first well of the first sector to the first predetermined potential, the potential difference between the channel and the gate required to erase the cells in the first sector can be applied. By disconnecting the first wells of all the other sectors from the first predetermined potential, the potential difference between the channel and the gate of the memory cells in those sectors can be minimized, thus reducing gate disturb.

Preferably, according to the second method, each first well is connected to a respective switching element. The first well of the first sector is biased with a first predetermined potential and the first wells of all other sectors of the first group of sectors are disconnected from the first predetermined potential by means of the respective switching elements at a time when the memory cells of the first sector are erased.

Preferably, according to the second method, the first predetermined potential is one of a ground potential and a substrate potential. In this way the potential difference between the channel and the gate is large enough to erase the cells in the first sector. The potential of the first wells of all the other sectors in the first group of sectors float and assumes a value close to the word line potential. As a result, the potential difference between the channel and the gate of those cells is reduced and gate disturb minimized.

Preferably, according to the first and second method, a word line potential is applied to the first group of word lines to which the memory cells of the first group of sectors are also connected. Applying a word line potential erases the memory cells being selected by the respective bit lines. In this way it is possible to erase whole sectors. For NROM cells the erasing potential is a negative potential of about 9 Volts.

The following list of reference symbols can be used in conjunction with the figures:1substrate region2first well3word line4bit line5gate electrode6first sector7other sectors of first group of sectors8group of sectors9switching element10oxide-nitride-oxide stack11shallow trench isolation structure12buried insulation layer13well of second doping type14first transistor15second transistor16,18first source/drain contact17,19second source/drain contact20isolation well of second doping type21nitride layer22silicon layer23memory cell25electrically insulating element26virtual ground array27first group of sectors28other groups of sectors29substrate32,33oxide layer34,35charge storing position36first group of word lines37other groups of word lines38word line decoder39bit line decodern second doping typep first doping typex first directiony second directionCgw equivalent capacitance between gate and first wellCws equivalent capacitance between first well and substrateGND ground potentialI currentVE switching signalVG gate potentialVGS potential difference between gate and substrateVGW potential difference between gate and first wellVP predetermined potentialVP1first predetermined potentialVP2second predetermined potentialVS substrate potentialVW potential of first wellWL word line potential

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Reference is now made toFIG. 2, which shows part of a cross-sectional view through a semiconductor memory according to the invention along a word line3. In contrast to prior art, the first wells2are not embedded in a substrate1. Rather, the first wells2are embedded in the additional wells13, which are then embedded in the substrate1. The substrate1and the first wells2are made of p-type semiconductor material. In each first well2several memory cells23are embedded. The cells23in each first well2are grouped together to form the respective sectors6,7.

Each cell23is connected to two bit lines4and a word line3which are used to select the cell23for reading, writing and erasing operations. The word line3is connected to the gates of all the cells23shown. In case of NROM cells, the detailed construction of the memory cells23is shown inFIG. 6and will be described later.

Referring again toFIG. 2, if cells23of the middle sector6are erased by applying a high negative voltage to the word line3, the same voltage will also bias the gates of the cells23in the sectors7at the left and right side of sector6. In prior art this will lead to gate disturb in the cells23of sectors7.

A preferred embodiment of the invention is shown inFIG. 2. The first wells2of each sector6,7are embedded in additional wells13of a doping type opposite to the doping type of the first wells2and of the substrate1. The first wells2and the substrate1may for example be made of p-type material and the wells13of n-type material or vice versa. As a consequence, depending on the voltages applied to the word line3and the substrate1, a depletion layer is created between the first wells2and the wells13of opposite doping or between the wells13of opposite doping type and the substrate1. As no charges are present in the depletion layer, it electrically insulates first wells2from the substrate1. The wells13surround the first wells2on the bottom and on the sides, so that the cells wells2are not only insulated from the substrate1but also from each other. The wells13of the opposite doping type can be merged together to form a single well individually embedding all first wells.

The wells13may further be connected to the ground potential GND as shown inFIG. 2. In this case the first wells2will only be insulated from each other and the substrate1if a word line potential WL negative with regard to the ground potential GND is applied to the word line3. This is for example the case when NROM cells are erased.

As a result of the electrical isolation of the first wells2of sectors6,7from each other and from the substrate1there is no electrical potential difference between the gate and the first wells2and no gate disturb occurs. However, it is also no longer possible to execute read, program and erase operations. For this reason the first wells2need to be connected to the required predetermined potentials VP for read, program and erase operations.

For this purpose each of the first wells2is connected to a switching element9. By means of the respective switching element9each of the first wells2can be electrically connected to the ground potential GND or to the word line potential WL. The switching elements9may be transistors.

For reading and programming cells23, the switching elements9of all first wells2are switched such as to connect the first wells2to the ground potential GND. For erasing memory cells23in a first sector6, the first well2of the first sector6is connected to the ground potential GND by means of the switching element9. The switching elements9of the sectors7in which the cells23are not to be erased, are used to connect the respective first wells2to the word line potential WL, as is shown inFIG. 2. As a result there is no potential difference between the channel and the gate of the cells23in the sectors7and no gate disturb occurs when cells23in the first sector6are erased.

FIG. 3shows another preferred embodiment for electrically insulating the first wells2from each other and from the substrate1. In contrast toFIG. 2, instead of wells13, a single, large isolation well20is provided in which all the first wells2are embedded. The isolation well20is of a doping type opposite the doping type of the first wells2and the substrate1. Electrical insulation is again achieved by a depletion layer, which is used to insulate the first wells2from the substrate1. However, the isolation well20does not insulate neighboring first wells2from each other, so that additional isolation structures11are used. In this embodiment these isolation structures11are shallow trench isolation (STI) structures, which must be deep enough to reach into the isolation well20. Using individual wells13for each sector6,7, as shown inFIG. 2requires the least process steps to achieve electrical insulation of the first wells2. However, using one big isolation well20and STI structures11reduces the space required for the insulation.

FIG. 4shows still another preferred embodiment for electrically insulating the first wells2from each other and from the substrate1. Instead of the isolation well20shown inFIG. 3, a buried insulation layer12is used to insulate the first wells2from the substrate1. A so-called silicon-on-insulator (SOI) substrate29may be used, which basically consists of a silicon wafer1with an oxide layer12on top and then another silicon layer22for the memory cell structures. Like in the preferred embodiment with the large isolation well20shown inFIG. 3, the neighboring first wells2also need to be electrically insulated from each other. This may again be achieved by shallow trench isolation (STI) structures11or other insulating elements. Using a silicon-on-insulator substrate with STI structures is the preferred implementation for the electrical insulating elements as the area required for insulation is drastically reduced.

In a variation of the invention the first wells2are no longer alternatively connectable to the ground potential GND or the word line potential WL by means of the respective switching elements, as shown inFIGS. 2 to 4. Instead of connecting the first wells2of the sectors7which are not to be erased to the word line potential WL, the potentials of the first wells2of the sectors7are left floating. The resultant potential VW of the first wells2is determined by a voltage divider and described later usingFIG. 6.

FIG. 5illustrates an embodiment similar to the one showing inFIG. 2. Corresponding numbers refer to the same structures. The difference between the two embodiments is that the first wells2are no longer connected to the word line potential WL by means of the switching elements9.

For reading and programming cells23in one of the sectors6,7, the switching elements9are closed so that all of the first wells2are connected to ground GND. To erase cells in a first sector6, the first well2of the first sector6is connected to the ground potential GND by means of the respective switching element9. The first wells2of the sectors7which are not to be erased are disconnected from the ground potential GND by means of the respective switching elements9and the potential VW of the first wells are left floating. Because the first wells2are insulated from each other and from the substrate1, the potentials VW of the first wells2of the sectors7, are no longer the same as the potential VW of the first well2in the first sector6. As a result, the potential difference between the word lines3and the first wells2in the sectors7will be less and gate disturb can be reduced.

In order to calculate the potential VW of the floating first wells2, reference is now made toFIG. 6. Shown inFIG. 6is a section through a single NROM cell as may be used in the invention. The gate electrode5of the cell23is connected to the word line3, which carries a word line potential WL. Below the gate electrode5is the so-called ONO layer10. The ONO layer includes a nitride layer21sandwiched in between two oxide layers32and33. Charge is stored in the nitride layer21at the locations34and35close to the left and right bit lines4, respectively. Both bit lines4are embedded in a first well2made from p-type semiconductor material. The channel of the NROM cell is formed between the two bit lines4and lies below the ONO layer10. To electrically insulate the first well2from other first wells2and from the substrate1, the first well2is embedded in a well13of a second, opposite doping type n.

Also shown inFIG. 6, there are two equivalent capacitors Cgw and Cws, which are connected in series. The capacitor Cgw represents the capacitance between the gate electrode5and the first well2, which is primarily caused by the insulating layers in the ONO layer10. It is connected to the potentials VG of the gate electrode5and potential VW of the first well2. The capacitor Cws is connected to the potential VW of the first well2and the potential VS of the well13of the second doping type n. It represents the capacitance of the depletion region of the PN-junction between the first well2and the well13of the second doping type n. In case a buried insulation layer12, such as provided when using a silicon-on-insulator structure29and shown inFIG. 5, is used to electrically insulate the first well2from the substrate1, the capacitance Cws represents the capacitance of the isolating oxide12. The well13of the second doping type n is electrically connected to the substrate1which is connected to the ground potential GND, so that there is no depletion region between the well13of the second doping type n and the substrate1.

Since the capacitors Cgw and Cws are connected in series, they carry the same charge Q and form a voltage divider. The potential difference VGW between the gate electrode5and the first well2is thus proportional to the potential difference VGS between the gate electrode5and the substrate1. VGW is a function of the capacitors Cgw and Cws and can be shown to be: VGW=VGS*Cws/(Cgw+Cws).

The potential difference VGW between the gate electrode5and the first well2is what causes gate disturb in the cells23of the sectors7and should therefore be minimized. According to the above formula, VGW will be small if the capacitance Cgw between the gate electrode5and the first well2is much larger than the capacitance Cws between the first well2and the well13of the second doping type n. In this case, as the voltage of a capacitor is inversely proportional to its capacitance, most of the voltage drop across the voltage divider will occur across the smaller capacitor Cws. The voltage VGW between the gate electrode5and the first well2will be small and gate disturb will be minimized.

For a given cell size the capacitance Cgw between the gate electrode5and the first well2is much larger than the capacitance Cws between the first well2and the substrate1. This is because the depletion region of the PN-junction between the triple well13and the first well2, or in case a buried isolator structure is used, the thickness of the isolation oxide12, is much thicker than the ONO layer10. As a result, gate disturb is usually suppressed well by just letting the potential of the first wells2float, without connecting the first wells2to a word line potential WL.

FIG. 6shows a cross-section through only one cell23. However, in a memory array many cells23may be connected to the same word line3and the resultant gate-well capacitance is the sum of all the gate-well capacitances Cgw of the cells23connected to the word line3. Similarly, the well-substrate capacity Cws depends on the size of the whole insulated area of a sector. For code flash memories Cgw is always much greater then Cws as all word lines3belong to one sector. For data flash memories this is not always the case, as the word lines3can belong to different sectors, so that depending on the size of the sector the capacitance ratio of Cgw to Cws is somewhat reduced and the invention is less effective in preventing gate disturb. However, in a so-called super-E sector, which is a huge erase sector, all the word lines3are used for erasing cells23at the same time and the invention is especially effective in minimizing gate disturb.

The embodiment shown inFIG. 5in which the potentials of the first wells2of the sectors7float, is advantageous compared to the embodiments shown inFIGS. 2 to 4in which the first wells2of the sectors7are connected to a word line potential WL in order to prevent gate disturb: letting the potential VW of the first wells2float leads to smaller capacitances which need to be charged or discharged during an erase operation.

Referring again toFIG. 6, a charging current I driven by the word line potential WL charges the capacitances Cgw and Cws. The equivalent capacitance of the series connection of the capacitances Cgw and Cws is C=Cgw*Cws/(Cgw+Cws) and is smaller than both Cgw and Cws. In case that the first wells2are connected to a word line potential WL, the capacitance Cgw is not charged and the equivalent capacitance is greater, being Cws. This means that the capacitance which has to be charged and discharged during an erase operation is smaller for the embodiment with the floating potential of the first wells2. As a consequence less power is needed to charge the word lines3to a given potential. This is especially advantageous in battery powered applications where the current required for operating the memory should be as low as possible. Again, the larger the ratio of Cgw to Cws the more current will be saved.

With regard to the electrical insulating elements25, the preferred embodiment of the invention shown inFIG. 5can also be constructed in various ways, similar to the embodiments shown inFIGS. 2,3and4. The electrical insulation of the first wells2from each other can be achieved using shallow trench isolation structures and a single isolation well20instead of a plurality of individual wells13or can be constructed using a buried insulation layer, such as provided by a silicon-on-insulator structure, together with shallow trench isolation structures.

FIG. 7shows a top view of a semiconductor memory having a substrate1and sectors6,7,8arranged along the x and y direction in rows and columns. Each sector6,7,8has memory cells23arranged along the x and y direction along rows and columns.

A word line decoder38and a bit line decoder39are used to select memory cells23for read, program or erase operations by means of the bit lines4and the word lines3connected to the cells23. Word lines3connecting cells23of a first group27of plural sectors6,7adjacent to one another along the first direction x are forming a group36of word lines. Word lines3connecting cells23in other groups28of sectors8adjacent to one another along the second direction y are grouped together in another word line group37. Bit lines4are only shown for cells23in the left column of sectors7,8. Of course, all cells23need to be connected to respective bit lines4.

InFIG. 7, every cell23is represented by its gate electrode5. Bit lines4pass the gates on the left and right sides, as is also shown in the cross-sectional view inFIG. 6. The cells23are connected to form a virtual ground array and may be nitride programmable read only memory (NROM) cells or floating gate cells, such as electrically erasable programmable read only memories (EEPROM).

InFIG. 7, different kinds of insulating elements25insulating the first wells2are illustrated for each group27,28of sectors6,7,8connected to a same respective group36,37of word lines. However, it is to be understood that those embodiments regarding the kind of insulating elements25are alternative to each other. Of course, in an actual semiconductor device all sectors6,7,8are insulated by the same kind of insulating element25.

In the bottom row of sectors the first wells2of each sector8are of a first doping type p and are embedded in wells13of a second doping type n. Each first well2is embedded in an individual well13. A cross-section along a word line3is shown inFIG. 2.

In the middle row of sectors8a buried insulation layer12is provided for insulating the first wells2from the substrate1. In practice the buried insulation layer12extends underneath all the first wells2of all the sectors6,7,8of the memory and can be part of a silicon-on-insulator substrate. Electrically insulating elements25are used to laterally insulate the first wells2from each other and are placed between adjacent first wells2and above the buried insulation layer12. The electrically insulating elements25can be shallow trench isolation structures11which may differ in size from the size shown. There may be only one shallow trench isolation structure11between two sectors8instead of two as shown. A cross-sectional view along one of the word lines3is shown inFIG. 4.

In the top row of sectors6,7all the first wells2of a first doping type p of sectors6,7are embedded in an isolation well20of a second doping type n. In practice, the isolation well20would embed all the first wells2of all the sectors6,7,8of the memory. Shallow trench isolation structures11are used to laterally insulate adjacent first wells2from each other. If sectors along the y-direction are also embedded in the isolation well20, the first wells2must also be electrically insulated from each other in that direction by further insulating elements11as shown in the middle row of sectors8. A cross-sectional view along one of the word lines3of the top row of sectors6,7is shown inFIG. 3.

According to a preferred embodiment of the invention switching elements9are connected to all first wells2of the memory. However, for clarity sake, the switching elements9of sectors7,8of the bottom row and the left column are not shown inFIG. 7. InFIG. 7, different kinds of switching elements9are illustrated. However, it is to be understood that those embodiments regarding the kind of switching element9are alternative to each other. Of course, in an actual semiconductor device all switching elements9will be of the same kind. The switching elements9are always connected to the respective first wells2. Electrical connections to a semiconductor material are marked with diamonds inFIG. 7.

The switching element9of the middle sector6in the top row of sectors6,7connects the first well2to a predetermined potential VP or a first predetermined potential VP1.

The switching element9of the right sector7in the top row of sectors6,7is a transistor14. The first source/drain contact16of the transistor14is connected to the first well2and the second source/drain contact17of the transistor14is connected to either a predetermined potential VP, a first predetermined potential VP1or a second predetermined potential VP2. The gate of the transistor14is connected to a control signal VE.

The switching element9of the middle sector6in the middle row of sectors8is made up of a first transistor14and a second transistor15. The first source/drain contact16of the transistor14is connected to the word line potential WL and the second source/drain contact17is connected to first well2. The first source/drain contact18of the transistor15is connected to the ground potential GND and the second source/drain contact19is connected to first well2. If the transistors14,15are chosen to be of opposite polarity, such as PMOS and NMOS, both transistors14,15can be controlled by the same signal VE.

The switching element9of the right sector8in the middle row of sectors8is used to connect or disconnect the first well2to the substrate potential VS. It is implemented as a transistor14. The first source/drain contact16of the transistor14is connected to the first well2and the second source/drain contact17of the transistor14is connected to the substrate potential VS. The substrate potential VS may be the same as the ground potential GND, if the substrate1is connected to the ground potential GND, as shown. The gate of the transistor14is connected to a control signal VE.

The switching elements9are controlled by a signal VE. The signal VE may be obtained from the bit lines4used for selecting the cells23. VE is chosen so that the first well2is connected to a ground potential GND or a substrate potential VS if one of the cells23in the first well2is selected by one of the bit lines4. The signal VE may be obtained from the output of a logic OR gate which has as inputs all the bit lines4leading to cells23located in one sector6,7,8or one first well2.

The principals of this invention to reduce gate disturb can also be applied to various read and program operations, they are not limited to the erase operation nor are they limited to NROM cells.

It will apparent to those skilled in the art that various modifications and variations can be made of the memory presented and the method of operating such a memory of the present invention without departing from the scope or the spirit of the invention. In view of the forgoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.