On-chip semiconductor device having enhanced variability

A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.

BACKGROUND

The present invention relates to semiconductor devices, and more specifically, to a semiconductor device including a physical unclonable function (PUF).

Device variability is typically caused by process variation(s), and it is much more substantial in smaller devices. Such variability is significant in proper circuit operation, and process improvements are made in order to tighten the device variability. Recently, device variability is being sought and applied to enforce security in information technology. As the security of internet-related networks, circuits, and applications becomes ever more stringent, it has become desirable to protect the information shared among semiconductor device communication.

One approach for preventing the unauthorized cloning of semiconductor devices is the use of Physical Unclonable Function (PUF) to encode a physical semiconductor device with a random set of numerical bits. A PUF generates a set of numerical bits, for example, 128 bits to form a matrix “A” A calculation of Y=A*X is performed during operation of the PUF, where “A” is a matrix having elements generated from the PUF, “X” is an input vector called a “challenge,” and “Y” is the output vector called the “response.” The matrix “A” and the input vector should only be known to the chip owner such that only the owner may know if the response is correct.

The PUF is typically embodied in the physical semiconductor device, and introduced a random variation in the threshold voltage (Vt) between a pair of transistor structures which is easy to evaluate but hard to predict. Each pair of transistor structures outputs either a “0” bit or a “1” bit. The bits generated from the PUF in one chip must be fixed and constant over time. In addition, the correlation among the bits generated from different PUF chips must be random. A semiconductor device including a PUF must be easy to fabricate but practically impossible to duplicate (i.e., is unclonable), even given the manufacturing process that fabricates the device. Conventional methods of fabricating a semiconductor device including a PUF typically add one or more PUF fabrication processes into the standard semiconductor device process flow. The added PUF fabrication processes, however, can increase the overall cost to fabricate the semiconductor device.

SUMMARY

According to at least one non-limiting embodiment of the present invention, a physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first dielectric area that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric area different from the first area that defines a second threshold voltage different from the first threshold voltage.

According to another non-limiting embodiment, a method of fabricating a physical unclonable function (PUF) semiconductor device comprises forming a first gate dielectric layer having a first dielectric area on a first active region of a semiconductor substrate, and forming a second gate dielectric layer having a second dielectric area different from the first dielectric area on a second active region of the semiconductor substrate. The method further includes forming a first semiconductor structure on the first gate dielectric layer to define a first threshold voltage of the first semiconductor structure, and forming a second semiconductor structure on the second gate dielectric layer to define a second threshold voltage of the second semiconductor structure that is different from the first threshold voltage.

According to yet another non-limiting embodiment, a method of fabricating a physical unclonable function (PUF) semiconductor device comprises forming a plurality of gate dielectric layers on a semiconductor substrate. Each gate dielectric layer has a gate dielectric area sized differently with respect to one another. The method further includes forming a semiconductor structure on each gate dielectric layer such that each semiconductor structure has a different threshold voltage with respect to one another.

According to another non-limiting embodiment, a physical unclonable function (PUF) semiconductor device comprises a plurality of gate dielectric layers on a semiconductor substrate. Each gate dielectric layer has a gate dielectric area that is different with respect to one another. A semiconductor structure is formed on each gate dielectric layer. Each semiconductor structure has a different threshold voltage with respect to one another.

According to still another non-limiting embodiment, a physical unclonable function (PUF) semiconductor array system comprises at least one pair of semiconductor structures on a semiconductor substrate. Each semiconductor structure includes a gate dielectric layer that defines a threshold voltage of a respective semiconductor structure. Each gate dielectric layer has a different gate dielectric area with respect to one another such that each threshold voltage is different from one another. A microcontroller is configured to apply an input voltage to each semiconductor structure and to determine the threshold voltage of each semiconductor device in response to the input voltage. The microcontroller determines a voltage differential based on the threshold voltage of each semiconductor device, and assigns a binary bit to the at least one pair of semiconductor structures based on a comparison between the voltage differential and a threshold value.

Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the features, refer to the description and to the drawings.

DETAILED DESCRIPTION

Various embodiments of the invention provide a PUF semiconductor device including a pair of large metal oxide field effect transistor (MOSFET) structures that introduce a random variation in the threshold voltage (Vt) of the device without requiring additional PUF fabrication processes. The large MOSFET structures includes a channel length ranging, for example, from approximately 60 nanometers (nm) to approximately 120 nm, which improves stability while still providing acceptable variations in Vt.

Unlike conventional semiconductor devices that implement additional PUF fabrication processes into the standard semiconductor device fabrication process flow, at least one embodiment of the invention induces variation of the Vt through variation in the gate dielectric thickness of a pair of transistor structure. For instance, as the thickness of the gate dielectric is reduced, the amount of voltage necessary to switch on the respective transistor structure is also reduced. That is, the offset of threshold voltage from each pair of transistors above is self-enhanced, i.e., with one transistor having lower Vt, the other transistor (necessarily) having higher Vt. Therefore, at least one embodiment of the invention randomly varies the gate dielectric layer of each transistor structures to introduce a variation in the Vt between the first transistor structure and the Vt of the second transistor structure.

The variation in the gate dielectric thickness can be adjusted when forming the gate structure of the semiconductor device, thereby excluding the need to incorporate additional PUF processes into the semiconductor fabrication process. For example, at least one non-limiting embodiment provides PUF device including an array of transistor pairs, where each pair of transistors has gate dielectric not only non-uniform but also asymmetric in an opposite way (i.e., thickness and length). Accordingly, costs for fabricating a PUF semiconductor device are reduced.

According to another embodiment, a method of fabricating a PUF device (e.g., a transistor pair, or further the gate oxide of the transistor pair) utilizes a single blocking litho/resist that partially covers both transistors. However, a first portion of a first transistor is exposed more to the litho etch than a similar portion of a second transistor. Accordingly, the gate dielectric of the first transistor and the second gate dielectric of the second transistor are fabricated in a non-uniform manner, which necessarily forms opposite, shapes/areas of the gate dielectrics. Thus, the transistor pair, i.e., the non-uniform gate dielectrics, is asymmetric in an opposite way in length and thickness for each pair with respect to each other, but can be simultaneously fabricated along an identical process flow using a blocking mask which exists in process flow (i.e., fabricated in reverse with respect to one another). Therefore, no extra process, mask or costs are required.

With reference now toFIG. 1, a PUF semiconductor device100is illustrated according to a non-limiting embodiment. The PUF semiconductor device100includes one or more device structures102a-102bon a single wafer (not shown). It should be appreciated that although a first device structure102aand a second device structure102bare shown, the invention is not limited thereto.

The first device structure102aincludes first and second semiconductor gate structures104a-104bformed on a first semiconductor substrate106a. The first semiconductor substrate106aincludes, for example, a semiconductor-on-insulator (SOI) substrate106a. According to an embodiment, the first SOI substrate106aincludes a bulk substrate layer108a, a buried insulator layer110aformed on an upper surface of the bulk substrate layer108a, and one or more active semiconductor layers112aformed on an upper surface of the buried insulator layer110a. The bulk semiconductor layer108acomprises, for example, silicon (Si). The buried insulator layer110acomprises, for example, silicon oxide (SiO2). The active semiconductor layers112acomprise, for example, Si. The SOI substrate106afurther includes one or more shallow trench isolation (STI) regions114athat electrically isolate the active semiconductor layers112afrom each other. The STI regions114acomprise, for example, SiO2.

The first and second gate structures104a-104are formed on an upper surface of a respective active semiconductor region112a. The first gate structure104aincludes a first gate electrode116a, and spacers118aformed on sidewalls of the gate electrode116aas understood by one of ordinary skill in the art. The first gate structure104afurther includes a first gate dielectric layer120acomprising, for example, SiO2. The first gate dielectric layer120ais interposed between the first gate structure104aand the active semiconductor layer112a.

Still referring toFIG. 1, the first gate dielectric layer120aincludes a first gate portion122aand a second gate portion124a. The first gate portion122ahas a first gate thickness (Q1_Tox_1) and a first gate dielectric length (Q1_Lox_1). The first gate thickness (Q1_Tox_1) and the first gate dielectric length (Q1_Lox_1) create a first shape that defines a first gate dielectric area of the first gate portion122a. According to a non-limiting embodiment, the first gate dielectric area is about 20% to about 80% of total gate dielectric length of120a, and may have the same width as the first gate dielectric layer120a. For example, the total gate dielectric area has dimensions of about 20 nm to about 80 nm in length, about 40 nm to about 200 nm in width, and is about 0.5 nm to about 4 nm thick.

The second gate portion124ahas a second gate dielectric thickness (Q1_Tox_2) and a second gate dielectric length (Q1_Lox_2). The second gate thickness (Q1_Tox_2) and the second gate dielectric length (Q1_Lox_2) create a second shape that defines a second gate dielectric area of the second gate portion124a. The second shape of the second gate dielectric layer120bi.e. is reversely arranged with respect to the first gate dielectric layer120. According to a non-limiting embodiment, the second gate dielectric layer ranges, for example, from about 20 nm to about 50 nm in length, and is about 2 nm to about 10 nm thick.

According to a non-limiting embodiment, the second gate dielectric length (Q1_Lox_2) is sized differently than the first gate dielectric length (Q1_Lox1). For example, the second gate dielectric length (Q1_Lox_2) is less than the first gate dielectric length (Q1_Lox1). In addition, the second gate dielectric thickness (Q1_Tox_2) is sized differently than the first gate dielectric thickness (Q1_Tox_1). For example, the first gate dielectric thickness (Q1_Tox_1) is less than (i.e., thinner) the second gate dielectric thickness (Q1_Tox_2).

Turning to the second gate structure104bshown inFIG. 1, a second gate electrode116bincludes spacers118bformed on the gate electrode sidewalls as understood by one of ordinary skill in the art. The second gate structure104bfurther includes a second gate dielectric layer120bcomprising, for example, SiO2. The second gate dielectric layer120bis interposed between the second gate structure104band the respective active semiconductor layer112a.

The second gate dielectric layer120bincludes a first gate portion122band a second gate portion124b. The first gate portion122bhas a first gate dielectric thickness (Q2_Tox_1) and a first gate dielectric length (Q2_Lox_1). The first gate thickness (Q2_Tox_1) and the first gate dielectric length (Q2_Lox_1) define a first gate dielectric area of the first gate portion122b. The second gate portion124bhas a second gate dielectric thickness (Q2_Tox_2) and a second gate dielectric length (Q2_Lox_2). The second gate thickness (Q2_Tox_2) and the second gate dielectric length (Q2_Lox_2) define a second gate dielectric area of the second gate portion124b.

Similar to the first gate dielectric layer120a, the second gate dielectric layer120bhas a second gate dielectric length (Q2_Lox_2) that is sized differently than a first gate dielectric length (Q2_Lox_1), and has a second gate dielectric thickness (Q2_Tox_2) that is sized differently than the first gate dielectric thickness (Q2_Tox_1). For example, the second gate dielectric length (Q2_Lox_2) is less than the first gate dielectric length (Q2_Lox_1). Unlike the first gate dielectric layer120a, however, the second gate dielectric layer120bhas a first gate dielectric thickness (Q2_Tox_1) that is greater than (i.e., thicker) than the second gate dielectric thickness (Q2_Tox_2).

Accordingly, at least one non-limiting embodiment provides a first device structure102awhere an overall gate dielectric area of the first gate dielectric layer120ais different than the overall gate dielectric area of the second gate dielectric layer120b. For example, the overall gate dielectric area of the first gate dielectric layer120ais less than the overall gate dielectric area of the second gate dielectric layer120b. In this manner, the threshold voltage (Q1_Vt) of the first gate structure104ais less than the threshold voltage (Q2_Vt) of the second gate structure104b.

Turning now to the second device structure102bshown inFIG. 1, third and fourth semiconductor gate structures104c-104dare formed on a second semiconductor substrate106b. Similar to the first semiconductor substrate106a, the second semiconductor substrate106bincludes, for example, a semiconductor-on-insulator (SOI) substrate106b. According to an embodiment, the second SOI substrate106bincludes a bulk substrate layer108b, a buried insulator layer110bformed on an upper surface of the bulk substrate layer108b, and one or more active semiconductor layers112bformed on an upper surface of the buried insulator layer110b. The bulk semiconductor layer108bcomprises, for example, silicon (Si). The buried insulator layer110bcomprises, for example, silicon oxide (SiO2). The active semiconductor layers112bcomprise, for example, Si. The SOI substrate106bfurther includes one or more shallow trench isolation (STI) regions114bthat electrically isolate the active semiconductor layers112bfrom each other. The STI regions114bcomprise, for example, SiO2.

The third and fourth gate structures104c-104care formed on an upper surface of a respective active semiconductor region112b. The third gate structure104cincludes a gate electrode116c, and spacers118cformed on sidewalls of the gate electrode116cas understood by one of ordinary skill in the art. The third gate structure104cfurther includes a first gate dielectric layer120ccomprising, for example, SiO2. The first gate dielectric layer120cis interposed between the third gate structure104cand the respective active semiconductor layer112b.

Still referring toFIG. 1, the first gate dielectric layer120cincludes a first gate portion122cand a second gate portion124c. The first gate portion122chas a first gate dielectric thickness (Q3_Tox_1) and a first gate dielectric length (Q3_Lox_1). The first gate thickness (Q3_Tox_1) and the first gate dielectric length (Q3_Lox_1) define a first gate dielectric area of the first gate portion122c. According to a non-limiting embodiment, the first gate dielectric area ranges, for example, from about 20 nm to about 80 nm in length, about 40 nm to about 200 nm in width, and is about 0.5 nm to about 4 nm thick.

The second gate portion124chas a second gate dielectric thickness (Q3_Tox_2) and a second gate dielectric length (Q3_Lox_2). The second gate thickness (Q3_Tox_2) and the second gate dielectric length (Q3_Lox_2) define a second gate dielectric area of the second gate portion124c. According to a non-limiting embodiment, the second dielectric area ranges, for example, from about 60 nm to about 120 nm in length, about 40 nm to about 200 nm in width, is about 1 nm to about 4 nm thick.

According to a non-limiting embodiment, the second gate dielectric length (Q3_Lox_2) is sized differently than the first gate dielectric length (Q3_Lox_1). For example, the second gate dielectric length (Q3_Lox_2) is greater than the first gate dielectric length (Q3_Lox_1). In addition, the second gate dielectric thickness (Q3_Tox_2) is sized differently than the first gate dielectric thickness (Q3_Tox_1). For example, the first gate dielectric thickness (Q3_Tox_1) is less than (i.e., thinner) than the second gate dielectric thickness (Q3_Tox_2).

Turning to the fourth gate structure104dshown inFIG. 1, a fourth gate electrode116dincludes spacers118dformed on the gate electrode sidewalls as understood by one of ordinary skill in the art. The second gate structure104dfurther includes a second gate dielectric layer120dcomprising, for example, SiO2. The second gate dielectric layer120dis interposed between the second gate structure104dand the respective active semiconductor layer112b.

The second gate dielectric layer120dincludes a first gate portion122dand a second gate portion124d. The first gate portion122dhas a first gate dielectric thickness (Q4_Tox_1) and a first gate dielectric length (Q4_Lox_1). The first gate thickness (Q4_Tox_1) and the first gate dielectric length (Q4_Lox_1) define a first gate dielectric area of the first gate portion122d. The second gate portion124dhas a second gate dielectric thickness (Q4_Tox_2) and a second gate dielectric length (Q4_Lox_2). The second gate thickness (Q4_Tox_2) and the second gate dielectric length (Q4_Lox_2) define a second gate dielectric area of the second gate portion124d.

Similar to the third gate dielectric layer120c, the second gate dielectric layer120dhas a second gate dielectric length (Q4_Lox_2) that is sized differently than a first gate dielectric length (Q4_Lox_1), and has a second gate dielectric thickness (Q4_Tox_2) that is sized differently than the first gate dielectric thickness (Q4_Tox_1). For example, the second gate dielectric length (Q4_Lox_2) is greater than the first gate dielectric length (Q4_Lox_1). Unlike the third gate dielectric layer120c, however, the fourth gate dielectric layer120dhas a first gate dielectric thickness (Q4_Tox_1) that is greater than (i.e., thicker) than the second gate dielectric thickness (Q4_Tox_2).

Accordingly, at least one non-limiting embodiment provides a second device structure102bwhere an overall gate dielectric area of the third gate dielectric layer120cis different than the overall gate dielectric area of the fourth gate dielectric layer120c. For example, the overall gate dielectric area of the third gate dielectric layer120cis greater than the overall gate dielectric area of the fourth gate dielectric layer120d. In this manner, the threshold voltage (Q3_Vt) of the third gate structure104cis greater than the threshold voltage (Q4_Vt) of the fourth gate structure104d.

As discussed in greater detail below, the difference in sizing between the first gate dielectric lengths (Q1_Lox_1-Q4_Lox_1) and the second gate dielectric length (Q1_Lox_2-Q4_Lox_2) occurs randomly during the fabrication of the gate dielectric layers120a-120d. As a result, a first random threshold voltage differential is produced between the pair of structures104a-104bof the first device102aand a second random threshold voltage differential is provided between the second pair of structures104c-104dof the second device102b. Each threshold voltage differential can be compared to a respective threshold value to generate either a “0” bit output or a “1” bit output. Accordingly, at least one embodiment of the invention provides a PUF semiconductor device100that generates a random succession of “0” bits or “1” bits, which can be easily evaluated but hard to predict and/or practically impossible to duplicate.

Turning now toFIGS. 2-10, a series of diagrams illustrate a process flow of fabricating a PUF semiconductor device200according to a non-limiting embodiment. Referring toFIG. 2, a semiconductor-on-insulator (SOI) starting substrate202is illustrated. Although a SOI starting substrate202is illustrated, it should be appreciated that a conventional bulk semiconductor substrate may be used without departing from the scope of the invention. The SOI substrate202includes a bulk substrate layer204, a buried insulator layer206formed on an upper surface of the bulk substrate layer204, and one or more active semiconductor layers208a-208bformed on an upper surface of the buried insulator layer206. The bulk semiconductor layer204comprises, for example, silicon (Si). The buried insulator layer206comprises, for example, silicon oxide (SiO2). The active semiconductor layers208a-208bcomprise, for example, Si. The SOI substrate202further includes one or more shallow trench isolation (STI) regions210that electrically isolate the active semiconductor layers208a-208bfrom each other. The STI regions210comprise, for example, SiO2.

Referring now toFIG. 3, the SOI substrate202is illustrated undergoing an oxidation process as understood by one of ordinary skill in the art. The oxidation process includes, for example, a thermal oxidation process. In addition, the oxidation process can include a dry oxidation process which exposes the SOI substrate202, and in particular the active semiconductor layers208a-208b(i.e., active Si) to molecular oxygen ions (O2) at high temperatures ranging, for example, from approximately 800 degrees Celsius (° C.) to approximately 1200° C. Although O2ions are descried, it should be appreciated that other ions may be used to form a second dielectric layer portion comprising a different material than the initial gate dielectric layers212a-212bformed according to the first oxidation process. It should also be appreciated that the dry thermal oxidation process can be replaced with a wet thermal oxidation process, which exposes the active semiconductor layers208a-208bto water vapor such as, for example, ultra-high purity (UHP) steam.

Turning toFIG. 4, the SOI substrate202is illustrated including dielectric gate layers212a-212bembedded in an upper portion of each active semiconductor layer208a-208bas a result of the preceding thermal oxidation process. In this manner, each active semiconductor layer208a-208bis interposed between a respective gate dielectric layer212a-212band the buried insulator layer206. The gate dielectric layers212a-212bcomprise SiO2, and can be utilized as gate dielectric layers, as discussed in greater detail below. The depth of the gate dielectric layers212a-212bcan be controlled based on the time at which the SOI substrate202is exposed to the preceding thermal oxidation process. According to a non-limiting embodiment the gate dielectric layers212a-212bcan have an initial depth ranging, for example, from approximately 2 nm to approximately 10 nm.

Referring now toFIG. 5, a block photoresist layer214is deposited directly on an upper surface of the SOI substrate202, which completely covers the STI layers210and the gate dielectric layers212a-212b. The block photoresist layer214comprises, for example, an organic light-sensitive material as understood by one of ordinary skill in the art which can be deposited on the upper surface of the SOI substrate using various deposition methods including, for example, spin coating.

Referring toFIG. 6, the photoresist layer214is patterned to form one or more openings216a-216btherein which exposes dielectric portions218a-218bof the underlying gate dielectric layer212a-212b, respectively. The patterning process includes interposing a photomask (not shown) between the photoresist layer214and a light source such as, for example, an ultra violet (UV) light source. The photomask includes openings formed therethrough. In this manner, solid portions of the photomask block a first portion of the UV light, while a second portion of the UV light passes through the mask openings and reaches the photoresist layer214. The UV light reacts with a portion of the photoresist layer214such that the openings216a-216bare formed therein. The size of the openings216a-216bis randomly varied with respect to each other due to the UV light exposure. According to a non-limiting embodiment, a first opening216ahas a first size (D1) and the a second opening216bhas a second size (D2) that is less than D1, as further shown inFIG. 6. In this manner, a dielectric layer portion218aexposed via the first opening216ahas a larger area than the opposing dielectric layer portion218bexposed via the second opening216b. That is, a single blocking litho/resist covers a first dielectric layer portion218bmore than a second dielectric layer portion218a.

Turning toFIG. 7, the exposed dielectric layer portion218aand the opposing exposed dielectric layer portion218bare recessed below respective remaining portions220a-220bof the gate dielectric layer212a-212bthat are covered by the remaining photoresist layer214. Various etching techniques may be implemented to etch the exposed dielectric layer portion218aand the exposed dielectric layer portion218bincluding, for example, a hydrofluoric (HF) etchant. According to a non-limiting embodiment, the exposed dielectric layer portion218aand the opposing exposed dielectric layer portion218bcan be recessed to have a thickness ranging from, for example, approximately 0.5 nm to approximately 3 nm.

With reference now toFIG. 8, the remaining photoresist layer214is removed from the upper surface of the PUF semiconductor device200. At this stage, the upper surface of the PUF semiconductor device200includes a first gate dielectric layer212aand a second gate dielectric layer212bwhich are asymmetrical with respect one another as discussed in greater detail below. The first gate dielectric layer212ahas a respective first dielectric layer portion218aand second dielectric layer portion220a(i.e., remaining portion220a). The first dielectric layer portion218aand the second dielectric layer220adefine a left dielectric layer portion218aand a right dielectric layer portion220bhaving different dimensions with respect to one another.

Similarly, the second gate dielectric layer212bhas a respective first dielectric layer portion218band second dielectric layer portion220b(i.e., remaining portion220b). The first dielectric layer portion218band the second dielectric layer portion220bof the second define a left dielectric layer portion218band a right dielectric layer portion220bhaving different dimensions with respect to one another.

The first dielectric layer portion218aof the first gate dielectric layer212ahas a first dielectric thickness (Q1_Tox_1) and a first dielectric length (Q1_Lox_1). The first dielectric thickness (Q1_Tox_1) and the first dielectric length (Q1_Lox_1) define a first dielectric area of the first dielectric layer portion218a. The second dielectric layer portion220aof the first gate dielectric layer212ahas a second dielectric thickness (Q1_Tox_2) and a second dielectric length (Q1_Lox_2). The second dielectric thickness (Q1_Tox_2) and the second dielectric length (Q1_Lox_2) define a second dielectric area of the second dielectric layer portion220a.

The dimensions of the first dielectric layer portion218aare different from the dimensions of the second dielectric layer portion220a. According to a non-limiting embodiment, the dielectric thickness (Q1_Tox_1) of the first dielectric layer portion218ais less than (i.e., thinner) than the dielectric thickness (Q1_Tox_2) of the second dielectric layer portion220a. In addition, the dielectric length (Q1_Lox_1) of the first dielectric layer portion218ais greater than the dielectric length (Q1_Lox_2) of the second dielectric layer portion220a.

Still referring to the non-limiting embodiment illustrated inFIG. 8, the first dielectric layer portion218bof the second gate dielectric layer212bhas a first dielectric thickness (Q2_Tox_1) and a first dielectric length (Q2_Lox_1). The first dielectric thickness (Q2_Tox_1) and the first dielectric length (Q2_Lox_1) define a first dielectric area of the first dielectric layer portion218b. The second dielectric layer portion220bof the second gate dielectric layer212bhas a second dielectric thickness (Q2_Tox_2) and a second dielectric length (Q2_Lox_2). The second dielectric thickness (Q2_Tox_2) and the second dielectric length (Q2_Lox_2) define a second dielectric area of the second dielectric layer portion220b.

Similar to the first gate dielectric layer212a, the second gate dielectric layer212bincludes a first dielectric layer portion218bthat has different dimensions than the second dielectric layer portion220b. According to a non-limiting embodiment, the dielectric thickness (Q2_Tox_1) of the first dielectric layer portion218bis less than (i.e., thinner) than the dielectric thickness (Q2_Tox_2) of the second dielectric layer portion220b. However, the dielectric length (Q2_Lox_1) of the first dielectric layer portion218bis less than the dielectric length (Q2_Lox_2) of the second dielectric layer portion220b. Accordingly, the overall second dielectric area of the second gate dielectric layer212bis greater than the overall first dielectric area of the first gate dielectric layer212a.

As further illustrated inFIG. 8, the first gate dielectric layer212aand the second gate dielectric layer212bare fabricated in reverse with respect to one another. For example, The first gate dielectric layer212ahas a first dielectric layer portion218a, i.e., a left dielectric layer portion218a, with a length (D1) and second dielectric layer portion220a, i.e., a right dielectric layer portion220a, with a length (D2). The second gate dielectric layer212b, however, has a first dielectric layer portion218b, i.e., a right dielectric layer portion218b, with a length (D2) and a second dielectric layer portion220b, i.e., a left dielectric portion220b, with a length (D1). That is, the length (D1) of the left dielectric layer portion218acorresponding to the first gate dielectric layer212amatches the length (D1) of the left dielectric layer portion220bcorresponding to the second gate dielectric layer212b. However, the thickness the left dielectric layer portion218acorresponding to the first gate dielectric layer212ais less than, for example, the thickness of the left dielectric layer portion220bcorresponding to the second gate dielectric layer212b.

Similarly, the length (D2) of the right dielectric layer portion220acorresponding to the first gate dielectric layer212amatches the length (D2) of the right dielectric layer portion218bcorresponding to the second gate dielectric layer212b. However, the thickness the right dielectric layer portion220acorresponding to the first gate dielectric layer212ais greater than, for example, the thickness of the right dielectric layer portion218bcorresponding to the second gate dielectric layer212b. Accordingly, the second dielectric gate layer212bis fabricated in reverse with respect to the first gate dielectric layer212a. It should be appreciated that the dimensions of the first and second gate dielectric layers212a-212bare not limiting. For example, the thickness of the left dielectric layer portion218acorresponding to the first gate dielectric layer212acan be greater than the thickness of the left dielectric layer portion220bcorresponding to the second gate dielectric layer212b, and the thickness of the right dielectric layer portion220acorresponding to the first gate dielectric layer212acan be less than the thickness of the right dielectric layer portion218bcorresponding to the second gate dielectric layer212b.

Turning now toFIG. 9, a first gate structure222ais formed on the first gate dielectric layer212aand a second gate structure222bis formed on the second gate dielectric layer212b. Each of the first and second gate structures222a-222binclude an electrode region224a-224bcomprising a dummy gate or metal gate as understood by one of ordinary skill in the art. The gate structures222a-222balso include spacers226a-226bformed on the sidewalls of a respective electrode region224a-224b. The spacers226a-226bcan comprise various materials including, but not limited to, silicon nitride (SiN).

The first gate structure222ais formed on the first gate dielectric layer212asuch that the first electrode region224ais disposed on a portion of the first dielectric layer portion218aand a portion of the second dielectric layer portion220a. In a similar manner, the second gate structure222bis formed on the second gate dielectric layer212bsuch that the second electrode region224bis disposed on a portion of the first dielectric layer portion218band a portion of the second dielectric layer portion220b. In a similar fashion, the second gate structure222bis formed on the second gate dielectric layer212bsuch that the second gate region224bis disposed partially on the first dielectric layer portion218band partially on the second dielectric layer portion220b. Since, however, the overall second dielectric area (e.g., the overall dielectric thickness) of the second gate dielectric layer212bis greater (i.e., portion220bis thicker than portion218b) than the overall first dielectric area (e.g., the overall oxide thickness) of the first gate dielectric layer212a(i.e., portion218ais thinner than portion220b), the second gate structure222bhas a threshold voltage (Q2_Vt) that is greater than the threshold voltage (Q1_Vt) of the first gate structure222a. In other words, the voltage required to switch on the first gate structure222ais less than the voltage required to switch on the second gate structure222bbecause the overall first dielectric area (e.g., the overall oxide thickness) formed beneath the first gate electrode region224ais less than the overall second dielectric area (e.g., the overall oxide thickness) formed beneath the second gate electrode region224b.

Referring now toFIG. 10, portions of the first gate dielectric layer212aand the second gate dielectric layer212bare removed from locations corresponding to source/drain regions of the active semiconductor layers208a-208b, respectively. Source/drain elements228a-228bare then formed on the source/drain regions (i.e., the exposed active semiconductor layers208a-208b) using various techniques including, for example, epitaxy crystalline growth, as understood by one of ordinary skill in the art. Accordingly, a PUF semiconductor device200including a pair of semiconductor structures (e.g., transistors). Each semiconductor structure includes a gate structures222a-222b, respectively, having a randomly created threshold voltage (Q1_Vt, Q2_Vt) due to the random size variation of the first and second gate dielectric layers212a-212bformed according to the process flow described in detail above.

For example, dielectric layer portion218aof the first gate dielectric layer212ais located at a first region (e.g., a left region) of the first semiconductor structure and dielectric layer portion220bof the first gate dielectric layer212ais located at a second region (e.g., right region) of the first semiconductor structure. Similarity, dielectric layer portion220bof the second gate dielectric layer212bis located at a first region (e.g., left region) of the second semiconductor structure matching the first region (e.g., left region) of the first semiconductor structure, and dielectric layer portion218bof the second gate dielectric layer212bis located at a second region (e.g., right region) of the second semiconductor structure matching the second region (e.g., right region) of the first semiconductor structure. In this manner, the thickness of the dielectric layer portions located at matching regions of the first and second semiconductor structures can be formed differently. For instance, a thickness of the dielectric layer portion218alocated at the first region of the first semiconductor structure is different than the thickness of dielectric layer portion220blocated at the first region of the second semiconductor structure.

A voltage differential between the first threshold voltage (Q1_Vt) and the second voltage threshold (Q2_Vt) can be determined using, for example, a microcontroller (not shown inFIG. 10) as discussed in greater detail below. The microcontroller can further compare the voltage differential to a threshold value to determine either a “0” bit or “1” bit corresponding to the particular PUF semiconductor device200. For example, if the voltage differential is below the threshold value, the microcontroller assigns a “0” bit output to the PUF semiconductor device200. If, however, the voltage differential is greater than or equal to the threshold value, the microcontroller assigns a “1” bit output to the PUF semiconductor device200. Since the voltage differential is based on the random sizing of the first gate dielectric layer212aand second gate dielectric layer212b, the bit output assigned to the PUF semiconductor device200(i.e., the pair of gate structure222a-222b) is also random.

Accordingly, at least one embodiment provides a PUF semiconductor device200that introduces a random variation in the threshold voltage (Vt) between a pair of semiconductor structures which is easy to evaluate but difficult to predict, and practically impossible to recreate. According to a non-limiting embodiment, an offset of threshold voltage from each pair of semiconductor structures (e.g., transistors) above is self-enhanced, i.e., with one semiconductor structure having a lower Vt, while the other semiconductor structure necessarily has a higher Vt. Moreover, since the random variation in Vt is based on the random sizing of the gate dielectric layers, the random variation can be achieved using a standard semiconductor fabrication process flow without introducing additional PUF fabrication processes. As a result, the overall costs to fabricate the PUF semiconductor device200are reduced.

Turning now toFIGS. 11-17, a series of diagrams illustrating a process flow of fabricating a PUF semiconductor device200having a random variation in gate lengths according to another non-limiting embodiment. With reference toFIG. 11, an SOI substrate202is illustrated following a photolithography process that patterns openings216a-216bin a photoresist layer214to exposes portions218a-218bof an initial gate dielectric layer212a-212b, respectively, which are formed according to a first oxidation process. As described in detail above, the patterning process includes interposing a photomask (not shown) between the photoresist layer214and a light source such as, for example, an ultra violet (UV) light source. The photomask includes pattern openings formed therethrough such that solid portions of the photomask block a first portion of the UV light, while the pattern openings allow a second portion of the UV light to reach the photoresist layer214. The UV light reacts with a portion of the photoresist layer214such that the openings216a-216bare formed therein. The size of the openings216a-216bis randomly varied with respect to each other due to the UV light exposure. According to a non-limiting embodiment, a first opening216ahas a first size (D1) and the a second opening216bhas a second size (D2) that is greater than D1, as further shown inFIG. 11. In this manner, the area of the exposed dielectric layer portion218ais smaller than the area of the opposing exposed dielectric layer portion218b.

FIG. 12illustrates the SOI substrate202ofFIG. 11after completely recessing the previously exposed dielectric layer portions218a-218bto partially expose each of the underlying first active semiconductor layer208aand the underlying second semiconductor layer208b. Various etching techniques may be implemented to etch the exposed dielectric layer portions218a-218bincluding, for example, an HF etchant. Since the size of the first opening216ais smaller than the size of the second opening216b, the area of the first exposed active semiconductor layer208ais smaller than the area of the second exposed active semiconductor layer208b.

Referring now toFIG. 13, the SOI substrate202is illustrated undergoing a second oxidation process. The second oxidation process is essentially applied to the entire SOI substrate202. However, only the exposed portions of the first active semiconductor layer208aand the second active semiconductor layer208breact to the second oxidation process. The second oxidation process can be similar to the first oxidation process used to form the initial gate dielectric layers212a-212b. For example, the second oxidation process can be a dry thermal oxidation process which exposes the SOI substrate202, and in particular the exposed active semiconductor layers208a-208b(i.e., active Si), to molecular oxygen ions (O2) at high temperature. The high temperature can range, for example, from approximately 800 degrees Celsius (° C.) to approximately 1200° C. Although O2ions are descried, it should be appreciated that other ions may be used to form a second dielectric layer portion comprising a different material than the initial gate dielectric layers212a-212bformed according to the first oxidation process. It should also be appreciated that the dry thermal oxidation process can be replaced with a wet thermal oxidation process, which exposes the active semiconductor layers208a-208bto water vapor such as, for example, ultra-high purity (UHP) steam.

Referring toFIG. 14, the SOI substrate202is illustrated following the aforementioned second oxidation process. As a result of the second oxidation process, second dielectric layer portions219a-219bare formed from the exposed active semiconductor layers208a-208b, respectively. The second dielectric219alayer portion, e.g., the left dielectric layer219alayer portion, of the first gate dielectric layer212ahas a different length and a different thickness than the first dielectric layer portion220a, e.g., the right dielectric layer portion220bof the first gate dielectric layer212a. Similarly, the second dielectric layer portion219b, e.g., the right dielectric layer portion layer219b, of the second gate dielectric layer212bhas a different length and a different thickness than the first dielectric layer portion220b, e.g., the left dielectric layer portion220bof the second gate dielectric layer212b. Accordingly, the resulting first gate dielectric layer212aand resulting second gate dielectric layer212bare fabricated in reverse and are asymmetrical with respect to one another. Although the second dielectric layer portions219a-219bare shown as having first thickness that is less than the thickness of the remaining dielectric portions220a-220b, it is possible that the second oxidation process could be used to form second dielectric layer portions219a-219bhaving a thickness that is greater than the thickness of the remaining dielectric portions220a-220b.

FIG. 15illustrates the substrate ofFIG. 14after removing the remaining photoresist layer to expose an upper surface of including a first gate dielectric layer212ahaving a second dielectric layer portion219athat is thinner than the remaining dielectric layer portion220a, and a second gate dielectric layer212bhaving a second dielectric layer portion219bthat is thinner than the remaining dielectric layer portion220b. For example, the first dielectric layer portion219aof the first gate dielectric layer212ahas a first dielectric thickness (Q1_Tox_1) and a first dielectric length (Q1_Lox_1). The first dielectric thickness (Q1_Tox_1) and the first dielectric length (Q1_Lox_1) define a first dielectric area of the first dielectric layer portion219a. The second dielectric layer portion220aof the first gate dielectric layer212ahas a second dielectric thickness (Q1_Tox_2) and a second dielectric length (Q1_Lox_2). The second dielectric thickness (Q1_Tox_2) and the second dielectric length (Q1_Lox_2) define a second dielectric area of the second dielectric layer portion220a.

As further illustrated inFIG. 15, the dimensions of the first dielectric layer portion219aare different from the dimensions of the second dielectric layer portion220a. For example, the dielectric thickness (Q1_Tox_1) of the dielectric layer portion219ais less than (i.e., thinner) than the dielectric thickness (Q1_Tox_2) of the remaining dielectric layer portion220a. In addition, the dielectric length (Q1_Lox_1) of the dielectric layer portion219ais less than the dielectric length (Q1_Lox_2) of the remaining dielectric layer portion220a.

Still referring to the non-limiting embodiment illustrated inFIG. 15, the dielectric layer portion219bof the second gate dielectric layer212bhas a first dielectric thickness (Q2_Tox_1) and a first dielectric length (Q2_Lox_1). The first dielectric thickness (Q2_Tox_1) and the first dielectric length (Q2_Lox_1) define a first dielectric area of the dielectric portion layer219b. The remaining dielectric layer portion220bof the second gate dielectric layer212bhas a second dielectric thickness (Q2_Tox_2) and a second dielectric length (Q2_Lox_2). The second dielectric thickness (Q2_Tox_2) and the second dielectric length (Q2_Lox_2) define a second dielectric area of the remaining dielectric portion layer portion220b.

Similar to the first gate dielectric layer212a, the second gate dielectric layer212bincludes a dielectric layer portion219bthat has different dimensions than the remaining dielectric layer portion220b. According to a non-limiting embodiment, the dielectric thickness (Q2_Tox_1) of the dielectric layer portion219bis less than (i.e., thinner) than the dielectric thickness (Q2_Tox_2) of the remaining dielectric layer portion220b. However, the dielectric length (Q2_Lox_1) of the dielectric layer portion219bis greater than the dielectric length (Q2_Lox_2) of the remaining dielectric layer portion220b. Accordingly, the overall dielectric area of the second gate dielectric layer212bis less than the overall dielectric area of the first gate dielectric layer212a.

As further illustrated inFIG. 15, the first gate dielectric layer212aand the second gate dielectric layer212bare fabricated in reverse with respect to one another. For example, the first gate dielectric layer212ahas a left dielectric layer portion219awith a length (D1) and right dielectric layer portion220awith a length (D2) greater than D1. The second gate dielectric layer212bhas a left dielectric layer portion220bwith a length (1) and a right dielectric layer portion219bwith a length (D2) that is greater than D1. That is, the length (D1) of the left dielectric layer portion219acorresponding to the first gate dielectric layer212amatches the length (D1) of the left dielectric layer portion220bcorresponding to the second gate dielectric layer212b. However, the thickness of the left dielectric layer portion219acorresponding to the first gate dielectric layer212ais less than, for example, the thickness of the left dielectric layer portion220bof the second gate dielectric layer212b.

Similarly, the length (D2) of the right dielectric layer portion220acorresponding to the first gate dielectric layer212amatches the length (D2) of the right dielectric layer portion219bcorresponding to the second gate dielectric layer212b. However, the thickness of the right dielectric layer portion220acorresponding to the first gate dielectric layer212ais greater than, for example, the thickness of the right dielectric layer portion219bof the second gate dielectric layer212b. It should be appreciated that the dimensions of the first and second gate dielectric layers212a-212bare not limiting. For example, the thickness of the left dielectric layer portion219acorresponding to the first gate dielectric layer212acan be greater than the thickness of the left dielectric layer portion220bcorresponding to the second gate dielectric layer212b, and the thickness of the right dielectric layer portion220acorresponding to the first gate dielectric layer212acan be less than the thickness of the right dielectric layer portion219bcorresponding to the second gate dielectric layer212b.

Turning toFIG. 16, a first gate structure222ais formed on the first gate dielectric layer212aand a second gate structure222bis formed on the second gate dielectric layer212b. Each of the first and second gate structures222a-222binclude an electrode region224a-224bcomprising a dummy gate or metal gate as understood by one of ordinary skill in the art. The gate structures222a-222balso include spacers226a-226bformed on the sidewalls of a respective electrode region224a-224b. The spacers226a-226bcan comprise various materials including, but not limited to, silicon nitride (SiN).

The first gate structure222ais formed on the first gate dielectric layer212asuch that the first electrode region224ais disposed partially on the dielectric layer portion219aand partially on the remaining dielectric layer portion220a. In a similar manner, the second gate structure222bis formed on the second gate dielectric layer212bsuch that the second electrode region224bis disposed partially on the dielectric layer portion219band partially on the remaining dielectric layer portion220b. Since, however, the overall second dielectric area (e.g., the overall oxide thickness) of the second gate dielectric layer212bis less than the overall first dielectric area (e.g., the overall dielectric thickness) of the first gate dielectric layer212a, the second gate structure222bhas a threshold voltage (Q2_Vt) that is less than the threshold voltage (Q1_Vt) of the first gate structure222a. In other words, the voltage required to switch on the first gate structure222ais greater than the voltage required to switch on the second gate structure222bbecause the overall dielectric area (e.g., the overall oxide thickness) formed beneath the first gate electrode region224ais greater than the overall dielectric area (e.g., the overall oxide thickness) formed beneath the second gate electrode region224b.

Referring now toFIG. 17, portions of the first gate dielectric layer212aand the second gate dielectric layer212bare removed from locations corresponding to source/drain regions of the active semiconductor layers208a-208b, respectively. Source/drain elements228a-228bare then formed on the source/drain regions (i.e., the exposed active semiconductor layers208a-208b) using various techniques including, for example, epitaxy crystalline growth, as understood by one of ordinary skill in the art. Accordingly, a PUF semiconductor device200is formed including a pair of gate structures222a-222beach having a randomly created threshold voltage (Q1_Vt, Q2_Vt) due to the random size variation of the first and second gate dielectric layers212a-212bformed according to the process flow described in detail above.

A voltage differential between the first threshold voltage (Q1_Vt) and the second voltage threshold (Q2_Vt) can be determined using, for example, a microcontroller (not shown inFIG. 17) as discussed in greater detail below. The microcontroller can further compare the voltage differential to a threshold value to determine either a “0” bit or “1” bit corresponding to the particular PUF semiconductor device200. For example, if the voltage differential is below the threshold value, the microcontroller assigns a “0” bit output to the PUF semiconductor device200. If, however, the voltage differential is greater than or equal to the threshold value, the microcontroller assigns a “1” bit output to the PUF semiconductor device200. Since the voltage differential is based on the random sizing variation between the first gate dielectric layer212aand second gate dielectric layer212b, the bit output assigned to the PUF semiconductor device200(i.e., the pair of gate structure222a-222b) is also random.

Accordingly, at least one embodiment provides a PUF semiconductor device200that introduces a random variation in the threshold voltage (Vt) between a pair of semiconductor structures which is easy to evaluate but difficult to predict, and practically impossible to recreate. Moreover, since the random variation in Vt is based on the random sizing of the gate dielectric layers of the gate structures, the random variation can be achieved using a standard semiconductor fabrication process flow without introducing additional PUF fabrication processes. As a result, the overall costs to fabricate the PUF semiconductor device200are reduced.

Referring now toFIG. 18, a block diagram of a PUF array system300is illustrated according to a non-limiting embodiment. The PUF array system300can include any number of PUF semiconductor devices100a-100nthat are connected to a controller and reader (i.e., microcontroller)302. Each PUF semiconductor device100a-100nincludes a first gate structure104aand a second gate structure104b. The first gate structure104ahas a first threshold voltage (Vt1) and the second gate structure104bhas a second threshold voltage (Vt2).

The microcontroller302is configured to provide an input voltage (Vin) and ground potential (Vg) to each PUF semiconductor device100a-100nof the PUF array300. In response to the Vin and Vg, the microcontroller302determines the first and second voltage thresholds (Vt1,Vt2) and calculates a voltage differential (ΔVt=Vt2−Vt1). The microcontroller302further compares the voltage differential to a threshold value to determine a binary output, i.e., a “0” bit or a “1” bit, corresponding to a respective PUF semiconductor device100a-100n. For example, if the voltage differential (ΔVt) is below the threshold value (Th), the microcontroller302assigns a “0” bit output to the PUF semiconductor device100a-100n. If, however, the voltage differential (ΔVt) is greater than or equal to the threshold value, the microcontroller302assigns a “1” bit output. The total number of bits output by the PUF array system300corresponds to the number of PUF semiconductor device100a-100nin the PUF array system300. Since the voltage differential is based on the threshold voltages of the gate structures104a-104b, which in turn are based on the random sizing of the first dielectric layer and second dielectric layer, the total bit output of the PUF array system300is also random. Accordingly, a PUF array system300includes a plurality of semiconductor devices100a-100nhaving random variations in the gate dielectric layers that introduce a variation in threshold voltages (Vt) which can be easily analyzed but practically impossible to duplicate.

A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

As used herein, the term module refers to a hardware module including an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the operations described therein without departing from the spirit of the invention. For instance, the operations may be performed in a differing order or operations may be added, deleted or modified. All of these variations are considered a part of the claimed invention.