Series voltage regulator with low dropout voltage and limited gain transconductance amplifier

A voltage regulation circuit intended to generate a regulated voltage for an electronic device, comprising: a transconductance amplifier based on a pair of MOS type differential amplifiers, said amplifier having a first input onto which a reference potential is applied and a second input onto which a counter reaction of said regulated voltage is input; a follower stage connected to the output from said transconductance amplifier; a MOS type transistor that will be used to make the output stage of the regulation circuit with a source connected to a first power supply potential. The transconductance amplifier comprises a resistive load 360 with a profile in K/gm, where gm is the transconductance coefficient of said input differential pair, said resistive load being connected to said first power supply potential.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic regulation circuits and particularly to a series voltage regulator with low dropout voltage.

2. Description of the Related Art

“Series” low DropOut (LDO) voltage regulators are frequently used for making battery powered circuits. Apart from their regulation function, they also switch unused electronic sub-circuits when necessary so as to reduce electrical consumption of the equipment. They are used jointly with switching power supplies to increase rejection of disturbances emitted by these same power supplies.

These circuits are used to make many mobile telephones on the market. Large efforts are made to increase the performances of these regulators, particularly in terms of load rejection and response to load variations. It is desirable to be able to create an output voltage with a precision of better than one percent, even for particularly low power supply voltages (less than 2 Volts).

LDO type regulation circuits are already known:

FIG. 1shows an example of a first known system like that described in the publication “Optimized Frequency-Shaping Circuit Topologies for LDOs” by Gabriel A. Rincàon-Mora and Philip E. Allen, IEEE TRANSACTIONS ON CIRCUIT AND SYSTEMS-II: ANALOG AND DIGITAL PROCESSING No. 6, June 1998. This first circuit is based on a cascade with a differential amplifier110acting as error amplifier, a follower stage120(or inverter) and a PMOS transistor (in the example illustrated)130used for voltage regulation supplying a load141-143. A counter-reaction chain materialized by resistive elements170and180is used for regulating the power supply voltage at the terminals of the drain of transistor130. The differential amplifier110is loaded by a capacitor150making an order zero (0) pole, which gives a high gain in open loop.

FIG. 2illustrates a second known circuit described particularly in document “A Capacitor-Free CMOS Low-dropout Regulator with Dampling-Factor-Control Frequency Compensation”, Ka Nang Leung and Philip K., T. Mok. IEEE JOURNAL OF SOLID STATE CIRCUIT, VOL. 38, No. 10, October 2003. For reasons of clarity, elements functionally identical to the first circuit have the same references. A regulator based on a chain comprising a differential error amplifier110, a follower or inverter stage120, and the PMOS transistor130are once again present. As above, the error amplifier110is loaded by a capacitive load formed by the capacitors Cm1, CM2and the DFC amplifier making a capacitor amplifier. The result is once again an order zero pole giving a high gain in open loop.

These two circuits, and in general circuits known according to the state of the art, introduce stability problems that are solved using appropriate pole splitting techniques. These techniques induce large transient responses during sudden current variations due to the large number of poles (in the Nyquist sense) in the slaving chain.

The result is loss of precision achieved in the regulator output voltage.

It is desirable to improve known regulation circuits, particularly for response transients to sudden variations in the current demand by the load.

BRIEF SUMMARY OF THE INVENTION

In one embodiment, a regulation circuit that is easy to manufacture and that considerably facilitates stabilization of the output voltage slaving chain.

Another embodiment includes a particularly stable low dropout series voltage regulator.

In one embodiment, a voltage regulation circuit comprises: a transconductance amplifier comprising a pair of MOS type transistors, said amplifier having a first input onto which a reference potential is applied and a second input onto which a counter reaction of said regulated voltage is input, and an output electrode; a follower stage connected to the output from said transconductance amplifier used to create an input to the MOS output transistor with a source connected to the power supply potential (Vdc)a resistive load with a profile in K/gm, where gm is the transconductance coefficient of said input differential pair, said resistive load being connected to the power supply potential to which the source of said output transistor is connected.

In this way, it is assured that the transconductance amplifier has a limited gain regardless of variations of the coefficient gm of the pair of MOS type transistors. This pushes the intrinsic pole of this transconductance amplifier well beyond the pole induced by the MOS output transistor compensation capacitor, and finally considerably facilitates compensation of the circuit and reduces transients generated by sudden variations of the load current.

Preferably, the output transistor is a PMOS type transistor with a source connected to the positive power supply potential and the resistive load in K/gm comprises at least one MOS type transistor connected in resistive load.

In one particular embodiment, the resistive load in K/gm comprises a fixed resistance, which acts as a stop and which is in parallel with at least one MOS type transistor.

In another embodiment, a transconductance amplifier comprises:

a first MOS type transistor with a gate, source and drain, a first reference potential (Vref) being input to the gate, and the source being connected to a first current source,

a second MOS type transistor with a gate, source and drain, a fraction of the output voltage from the regulator being input to the gate through a counter reaction circuit, the source being connected to said first current source;

a second current source connected between said first power supply potential (Vdc) and the drain of said first MOS transistor;

a third current source connected between said first power supply potential (Vdc) and the drain of said second MOS transistor;

a third MOS transistor comprising a source connected to the drain of said first MOS transistor and to said second current source; said third transistor being provided with a gate into which a second reference potential (Vref2) is input;

a fourth MOS transistor comprising a source connected to the drain of said second transistor and to said third current source; said fourth transistor being provided with a gate into which the second reference potential (Vref2) is input;

a fifth MOS transistor with a source, a gate and a drain, said source of said fifth MOS transistor being connected to a second power supply potential (GND), said drain of said fifth MOS transistor being connected to the drain of said third transistor, and forming the output electrode of said transconductance amplifier;

a sixth MOS transistor with a source, a gate and a drain, said source of said sixth MOS transistor being connected to said second power supply potential (GND), said drain of said sixth MOS transistor being connected to the drain of said fourth transistor, and to the gates of said fifth and sixth transistors.

Preferably, a follower stage comprises:

a seventh MOS type transistor comprising a gate, a source and a drain, said gate of said seventh transistor being connected to said output electrode of said transconductance amplifier and said drain of said seventh transistor being connected to a fourth current source;

a bipole transistor comprising a base, an emitter and a collector, the base of the bipole transistor being connected to the drain of said seventh MOS transistor, the emitter being connected to said second power supply potential (GND), and the collector being connected to the source of said seventh MOS transistor and to a first electrode of a resistance with a second electrode connected to said first power supply potential (Vdc).

Embodiments of the invention can also be used to make a battery powered portable switching apparatus, particularly such as a mobile telephone including a voltage regulation circuit comprising:

a transconductance amplifier based on a pair of MOS type differential transistors, said amplifier comprising a first input into which a reference potential is input and a second input into which a counter-reaction of said regulated voltage is input;

a follower stage connected to the output from said transconductance amplifier;

a MOS type transistor that will be used to make the output stage of the regulation circuit with a source connected to a first power supply potential (Vdc); wherein said transconductance amplifier comprises a resistive load with a profile in K/gm, where gm corresponds to the transconductance coefficient of said differential input pair, said resistive load being connected to said first power supply potential (Vdc).

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3illustrates the principle used to make a low dropout voltage regulator according to an embodiment. The circuit is particularly suitable for making battery powered electronic circuits, and particularly low voltage circuits like those used for mobile telephones.

The circuit according to the illustrated embodiment is used to convert from the compensation capacitance in the input stage present in known regulation circuits, and that induces problems of unwanted transient responses if there is a sudden variation in the load current.

FIG. 3shows a regulation circuit300that comprises a differential transconductance amplifier310, a follower stage320, and a transistor330. The follower stage320is connected to the output of the transconductance amplifier310and to the gate of the transistor330. The transconductance amplifier310is used as an error amplifier that receives a reference potential at its input (represented by element311) used to fix the output potential to be regulated and a fraction of this output potential through a counter-reaction network390, which comprises a compensation capacitor350in parallel with a set of two resistive passive elements370and380.

gm is the transconductance coefficient of the circuit310.

The transconductance amplifier can be made using any MOS type or other type of integrated or discrete amplifier circuit that can be used to obtain an output current proportional to the difference (error) between its two inputs.

In one preferred embodiment, the transconductance amplifier is made using a differential amplifier comprising MOS type transistors.

Unlike known circuits, the amplifier circuit310is loaded by a resistive type load360so as to limit the output gain of the error amplifier stage. This prevents an order 0 pole like that used in known circuits from being set-up, as described inFIGS. 1 and 2mentioned above.

In practice, the gain of the stage is limited to 30 or 40 dB, unlike in known circuits in which the gain can easily be as high as 100 dB.

Preferably, a resistive component will be chosen for the resistive element360with a resistance equal to K/gm, in which K is a constant and gm is the transconductance coefficient of the error amplifier.

On the output side of the follower stage, the circuit comprises a MOS transistor for which the gate is controlled by the output voltage from the follower stage. The source of the MOS transistor is connected to the power supply potential—usually fixed by the battery or the output from a DC/DC converter such as a switching power supply391. The drain of the MOS transistor outputs the regulator output potential, accessible at a load represented by two resistive elements341and343and a capacitive element342. As can be seen in the figure, a counter-reaction network390comprises a compensation capacitor350connected between the drain of the MOS transistor and the second input of the error amplifier circuit310, in parallel with two resistive elements370and380in series. The load341-342—343is connected to the midpoint of elements370and380.

As can be seen, due to the presence of the load360equal to K/gm, the regulation circuit300only comprises a main pole which is fixed by the output from the MOS transistor330, the counter reaction network390, and particularly the compensation capacitor350.

In one particular embodiment, an element of the same nature as the amplifier elements located in the error amplifier310and integrated in the same semiconducting substrate is used to make the resistive load360, so that it can be subjected to the same temperature variations. Thus, if the error amplifier310uses a pair of MOS transistors to make the differential stage, then the load360is made using MOS transistors as well, installed as a resistive load varying with the temperature and the inrush current.

In this way, even with large temperature variations and variations in the load341-342-343, it is assured that the gain of the amplifier stage310and360remains limited to K.

For a fixed gain-band product of the error amplifier stage310, it is found that the resistive load360with a profile in K/gm can assure a relatively high switching frequency for the input stage310and consequently prevents phase rotation due to the order 0 pole. Consequently, this phase rotation occurs after the phase rotation introduced by the compensation capacitor350, which makes it easy to stabilize the regulation circuit.

Consequently, the main pole of the regulation circuit is fixed essentially by the capacitor350and no longer by capacitors intrinsic to the input amplifier stage310and that are difficult to control.

Furthermore, it is found that the transients related to sudden load variations, which can reduce the precision of the regulation circuit, are avoided.

FIG. 4illustrates a particular regulation circuit400according to an illustrated embodiment. The circuit400will be described with reference to the use of a PMOS transistor for the output stage, it being understood that those skilled in the art could easily adapt the circuit to make a dual structure based on an NMOS transistor for the output stage.

The regulation circuit400comprises a transconductance amplifier310based on a differential pair, a first NMOS transistor410and a second NMOS transistor420, each comprising a gate, a source and a drain. The sources of the two transistors410and420are connected to a current source401in which there is a current i0circuit equal to:
i0=i1+i2
where i1and i2are equal to the currents circulating between the source and the drain electrodes respectively of transistors410and420.

The drain of transistor410is connected to a source of a third PMOS type transistor430, and to a current source431generating a current i3.

The drain of transistor420is connected to a source of a fourth transistor440(also of a PMOS type) and to a current source432generating a current i4.

In practice, the values of currents i3and i4can be fixed equal to 4 μA.

The PMOS transistor430is provided with a gate into which a reference potential Vref2 is input and a drain connected to the drain of a fifth MOS transistor405(NMOS type) for which the source is connected to a reference potential such as the ground.

The PMOS transistor440is provided with a gate into which the reference potential Vref2 is also input and it comprises a drain connected to the drain of a sixth MOS transistor405(NMOS type) for which the source is connected to the ground. The drain of the NMOS transistor406is also connected to the gate of this same transistor406and to the gate of the transistor405. The transistor406thus forms a current mirror with the transistor405, so that the following equation between the currents is satisfied:

i4−i2=i3−i1−is, where is is the output current from the electrode445.

If i3=i4is fixed, we have is=i2−i1.

Therefore the drain electrode of transistors430and405outputs the output current i2−i1from the transconductance amplifier and forms the output electrode445of the error amplifier stage.

The output electrode445is connected to the power supply potential (Vdc) to be regulated through the resistive load360with a profile in K/gm. The electrode445is also connected to an electrode of a current source471generating a current i7, and to the input of a follower stage320.

The follower stage320consists of a seventh PMOS transistor460for which the gate is connected to the output electrode445from the transconductance amplifier310. The drain of transistor460is connected to a sixth current source461generating a current i6and to the base of a bipole transistor470, the emitter of which is connected to the ground potential. The source of transistor460and the collector of the bipole transistor470are connected firstly to a first electrode of a resistance481and secondly to the gate of an eighth MOS transistor (PMOS type) forming the output transistor from the regulation circuit. The resistance481has a second electrode connected to the Vdc potential, to which the source of the transistor480is also connected. Finally, the transistor480comprises a drain generating the regulated output potential which is transmitted to the gate of the transistor420through the counter reaction network490, and also to the load340composed of a capacitive load492and to resistive loads491and493, as shown inFIG. 4.

The resistive load360connected between the potential Vdc and the output electrode445from the transconductance amplifier consists of a set of two PMOS transistors451and452connected in series, each having a gate and a drain connected together. In this way, a resistive load is made around a potential equal to 2× Vgs which corresponds perfectly to the offset introduced by the seventh transistor460and the eighth transistor480.

The result is a resistive set with a profile in K/gm and that gives a temperature and load variation profile corresponding to that of the regulator, particularly the differential pair410-420, but also the PMOS output transistor480.

Optionally, a connection is made in parallel on the two MOS transistors mounted in series on a fixed resistance453, which forms a stop to further limit the gain of the error amplifier stage310.

The polarization current of the PMOS transistors451and452is output by a seventh current source471generating a current i7so as not to disturb operation of the differential pair410and420.

In one variant embodiment, it would be possible to invert the type of all transistors and to make a regulation with an NMOS type output transistor.