Monolithic output stage with vertical high-side PMOS and vertical low-side NMOS interconnected using buried metal, structure and method

A voltage converter can include an output circuit having a vertical high-side device and a vertical low-side device which can be formed on a single die (i.e. a “PowerDie”). The high side device can be a PMOS transistor, while the low side device can be an NMOS transistor. The source of the PMOS transistor and the source of the NMOS transistor can be formed from the same metal structure, with the source of the high side device electrically connected to VIN and the source of the low side device electrically connected to ground. A drain of the high side PMOS transistor can be electrically shorted to the drain of the low side NMOS transistor during device operation using a metal layer which is interposed between the transistors and a semiconductor substrate.

DESCRIPTION OF THE INVENTION

This invention relates to the field of semiconductor devices and, more particularly, to power conversion and control structures and their methods of formation.

Semiconductor devices that provide power converter functionality, for example for altering DC power using a DC to DC (DC-DC) converter, are used in various capacities. For example, input DC power from one or more batteries can be converted to provide one or more power outputs at voltages that can be higher or lower than the input DC voltage. Performing a power conversion function using integrated circuits (IC's) typically requires a DC high-side transistor electrically coupled with voltage in (VIN), a DC low-side transistor electrically coupled with ground, and a control circuit. In a synchronous step-down device (i.e. a synchronous buck, or “synch buck” converter), for example, power conversion is performed to decrease voltage by alternately enabling the high-side device and the low-side device, with a switching and control function being performed by the controller circuit with high efficiency and low power loss through the device.

Power converter circuits which can operate at a high power density (for example, high voltage and high current, in a small space) are needed, particularly devices which can efficiently convert power at a reasonable cost while minimizing space required for the device on a printed circuit board or other receiving substrate. One challenge with high power density is that the size of the output circuitry increases as the voltage and current rating of the converter increases because power transistors require larger spacing in order to operate at high-voltages. Different implementations of the controller circuit, the high-side device, and the low-side device have been used, each with its own advantages and disadvantages.

As depicted inFIG. 1, co-packaged devices10can include control circuitry on one semiconductor die12to provide a controller IC, the high-side device on a second die14, and the low-side device on a third die16. A representative circuit schematic of theFIG. 1device is depicted inFIG. 2, which also depicts controller circuitry12, high-side MOSFET14connected to a VINpinout and adapted to be electrically coupled with VINduring device operation, and low-side MOSFET16connected to a power ground (PGND) pinout and adapted to be electrically coupled with PGNDduring device operation. The devices can have standard package pinouts and pin assignments such as those depicted. Forming controller, low-side, and high-side devices on separate dies can have problems with interconnection parasitics on the controller IC which can negatively influence device performance. This may result from parasitic inductance inherent in bond wires, electromagnetic interference (EMI), ringing, efficiency loss, etc. Higher-quality connections such as copper plate (or clip) bonding, or ribbon bonding, can be used to reduce parasitics, but this increases assembly costs. Further, co-packaging standard vertical MOSFETs can result in a circuit with parasitic inductance in series with the output node. Problems caused by parasitic inductances are well established in the art. While a capacitor can be connected to the output terminals such as the input (VIN) and ground to compensate for the negative impact of inductances connected to these nodes, internal parasitic inductances cannot be compensated by this technique since the internal nodes are not available at external package locations.

Additionally, packages containing three separate dies have higher production costs, for example because of the large number of die attach steps (three dies in this example), and additional space is required for spacing between adjacent dies to allow for die attach fillets, die placement tolerance, and die rotation tolerance, which reduces the power-density which can be achieved. To reduce electrical interference between adjacent dies and to realize the desired device interconnection, each die is placed on a separate die pad.

Examples of co-packaged devices include non-synch buck with co-packaged high-side MOSFET and external Schottky diode, non-synch buck with co-packaged high-side and low-side MOSFETs, synchronous buck with co-packaged high-side and low-side MOSFETs, boost converter with co-packaged MOSFETs (synchronous boost), and boost converter with co-packaged MOSFET and Schottky diodes.

Discrete devices can also be mounted separately to a printed circuit board. In this solution, a first packaged die containing controller circuitry is used in conjunction with a second packaged die containing a high-side MOSFET and a third package containing a low-side MOSFET. The three packages are mounted on a printed circuit board. However, this can increase packaging costs as the number of dies and separate packages which must be manufactured and handled is at least tripled, and the area used on the printed circuit board is also increased, leading to increased circuit board size.

Power converters exist which use N-channel MOSFETs for both high side and low side applications. This requires the use of complex designs for the controller and/or gate driver integrated circuits.

There is a need for power converters in which device processing costs and device footprint are reduced while providing a power converter device which has sufficient device electrical characteristics with low parasitic inductance and capacitance.

It should be noted that some details of the FIGS. have been simplified and are drawn to facilitate understanding of the inventive embodiments rather than to maintain strict structural accuracy, detail, and scale.

DC to DC power converters based on a high side lateral PMOS and low side lateral NMOS can be used in low-voltage monolithic (single die, using lateral devices interconnected on the top surface of the monolithic die) implementations as well as discrete implementations. The use of a lateral PMOS high side device simplifies the controller design. One drawback, however, is a relatively high specific resistance (RDSON*Area) of lateral PMOS devices, which is typically two to three times higher than that of a lateral NMOS device with equivalent geometry. This can result because of a much lower mobility of holes (carrier in PMOS) compared to electrons (carrier in NMOS). Discrete implementations, for example using efficient trench double-diffused metal oxide semiconductor (DMOS) PMOS devices, can suffer from parasitic inductance, large size, and a higher cost resulting from the need for multiple packages. Further, monolithic implementations are expensive, as the current rating and voltage rate increases, particularly because of the large size of high voltage, low resistance lateral PMOS devices. Co-packaging of a controller IC with a PMOS high side die and an NMOS low side die has been attempted, but this can be expensive due to the requirement to assemble multiple components and additional space (i.e. alignment and placement between the different dies). Thus, more efficient power stage configurations based on PMOS high side and NMOS low side devices would be desirable

Various embodiments of the present teachings can include one or more features. For example: 1) monolithic (single die) integration of a high side vertical PMOS device with a low side vertical NMOS device; 2) a substrate used as the output (i.e. phase node) for both devices; 3) a top metal overlying the high side PMOS device is voltage in (i.e. VIN, the PMOS source); 4) a top metal over the low side NMOS device, which can be formed as a single layer with the PMOS source metal, is the device ground (i.e. the NMOS source); 5) a power converter structure which can be formed using efficient devices such as enhancement mode devices, vertical DMOS devices, trench DMOS devices, or a combination of devices; 6) a power converter device which is compatible with high performance LDMOS devices; 7) a device wherein interconnection of the drain of the high side PMOS device (which is P-type) to the drain of the low side NMOS device (which is N-type) can achieved through a buried metal connection at the substrate-to-epitaxial layer interface; 8) one or more vertical DMOS and/or enhancement mode devices used for both NMOS and PMOS with planar gates; 9) a vertical trench gate structure used for both the NMOS and PMOS devices; 10) a buried metal short between the PMOS drain, the NMOS drain, and the conductive substrate; 11) transition or buffer layers doped with slow diffusing dopants such as antimony and arsenic can be used between a highly doped substrate and a buried conductor so as to minimize counter doping, and; 12) patterned or partial buried layer and a buried conductor.

A first method to form a structure according to an embodiment of the present teachings is depicted inFIGS. 3-16. As will be understood from the description below, this method can use as few as 9 layers, including: 1) a buried layer (BL) mask; 2) a PMOS drain mask; 3) a trench mask; 4) an N-body mask (i.e. a mask for implantation of the body of the PMOS device); 5) a P-body mask (i.e. a mask for implantation of the body of the NMOS device); 6) an N+ implant mask; 7) a P+ implant mask; 8) a contact opening etch mask, and; 9) a metal etch mask. The method can optionally include a bond pad etch mask.

As depicted inFIG. 3, a substrate wafer30(i.e. handle wafer) which highly doped to an N-type conductivity (i.e. “N+++”) can receive a conductor layer32such as a deposition of tungsten (W) or tungsten silicide (WSix) to a thickness of between about 0.1 microns (μm) to about 1.0 μm. Subsequently, polysilicon34is deposited on the conductor layer to a thickness of between about 0.1 μm to about 4.0 μm then planarized, for example using chemical mechanical polishing (CMP) to achieve a flat smooth surface. A separate device wafer36is bonded to the polished polysilicon surface of the substrate wafer, for example using commercially available wafer bonders such as those from EVG of Tempe, Ariz. and Karl Suss of Waterbury Center, Vt. After the device wafer is bonded to the handle wafer with the buried metal, the device wafer can be ground, polished, or planarized to a thickness of between about 0.2 μm to about 3.0 μm to result in a structure similar to that depicted inFIG. 4.

Next, a pad oxide50in the range of between about 100 Å to about 300 Å and a nitride52in the range of about 500 Å to about 1,500 Å are deposited on the device wafer. A patterned mask (not depicted) is formed over the nitride52, the nitride is etched, and an N+ buried layer54is implanted either before or after removal of the patterned mask. The N+ buried regions54can be implanted using antimony or arsenic, with doses in the range of between about 1E13 atoms/cm2to about 5E15 atoms/cm2and energies in the range of about 20 KeV to about 140 KeV. Once the mask is removed, a structure similar to that ofFIG. 5remains, including an N+ doped layer54implanted into the right side (as depicted) of the device wafer36.

With the nitride52and pad oxide50in place, an oxidation is performed which consumes a portion of device wafer and thickens the oxide on the exposed right side of the wafer to result in a thick oxide60on the right side (as depicted) of the device wafer36. This results in a slight step as depicted between the NMOS region62and the PMOS region64, equivalent to approximately half of the thickness of the oxide grown, which can be used as alignment for subsequent processing. The oxidation step can also be performed at a temperature sufficient to diffuse the N+ buried layer54into the device wafer as depicted. The nitride is stripped and a P+ buried layer implant66, for example using boron or BF2, a dose in the range of between about 1E13 atoms/cm2to about 5E15 atoms/cm2, and an energy in the range of between about 10 KeV and about 80 KeV can be is performed in a self-aligned fashion, since the oxide60grown over the N+ regions62will block this P implant. The P+ implant can be followed by an optional P+ buried layer anneal, which may be a rapid thermal processing (RTP) step and/or a diffusion to result in a structure similar to that depicted inFIG. 6.

Subsequently, the oxide is etched and the wafers are cleaned and an N-type epitaxial layer (N-epi)70is deposited on the top surface of the device wafer. The thickness and doping concentration of this epitaxial silicon region depend on the requirements of a subsequently-formed N-channel Vertical DMOS transistor. For a device rated at about 30V, the N-epi may have a thickness in the 3 to 6 micron range, and a doping concentration in the range of between about 2.0E16 atoms/cm3to about 2.6E16 atoms/cm3. It should be noted that the small step disparity between the N and P regions is neglected in the following description and FIGS., since it is a fraction of the thickness of the silicon grown and since it is outside of the active area of devices.

A pad oxide (not depicted) is formed on the epitaxial layer70and a patterned mask (preferably thick resist, in the 2 to 5 micron range for example, not depicted) is applied to enable the doping of the PMOS drain region, resulting in P-type portion72of epitaxial layer70, and an N-type portion74of epitaxial layer70. During the P-type implant, the mask protects N-type epitaxial layer portion74from implantation of P-type dopants using a thick resist. The PMOS drain implant can be performed using multiple high-energy boron implants, for example using a boron implant with energies in the ranges of about 100-200 KeV, about 300-450 KeV and about 800-1500 KeV, and doses in the range of between about 1 E11 atoms/cm2to about 1 E13 atoms/cm2, for a PMOS drain formation based on three separate implants. The resist is removed, and a PMOS drain region anneal can performed to result in theFIG. 7structure. The drain region anneal may be performed in a furnace, with temperature in the range of between about 900° C. to about 1200° C., depending on the desired PMOS drain doping profile. It should be noted that the NMOS drain74can also be formed by implant and diffusion, similar to that of the formation of the drain of the PMOS device, with any required process modifications.

It is known that the diffusion coefficients of silicon dopants including boron, arsenic and antimony are many orders of magnitude higher in tungsten silicide than they are in silicon. Layer32below the buried layers, if tungsten is used, may be at least partially converted to tungsten silicide during bonding and other high temperature steps.

As a result, the buried layer dopants may almost instantly diffuse laterally from one device region (e.g.64) to the other (e.g.62) once they come in contact with the silicide. In the case of the fast (in silicon) diffusing boron, the laterally diffused dopant may then up diffuse into the opposite conductivity type island. If this occurs, this may result in dopant compensation that increases buried layer resistivity. Further, if diffusion time is high enough and buried layer thickness is small enough, it will out diffuse the slower moving N buried layer to form a net P layer that separates the N buried layer from the N drain region. Options to mitigate these problems include using lower doping level for the P buried layer than for the N buried layer and using P for the N buried layer. The P diffusion coefficient is about equal to that of boron so the boron cannot easily out diffuse it. Using N and P type buried layer dopants with about the same diffusion coefficient may also result in similar up diffusion distance into the overlying epitaxial layer for both. That results in similar buried layer to body distance for both type devices as required for minimum on resistance at the same breakdown voltage for the two devices.

The diffusion of dopants within and out of the buried metal can be controlled by altering the types of dopants used, the dopant concentration, and the processing time and temperature. In addition, the diffusion of dopants may be altered by changing the composition of the buried metal. Compositions can include, for example, silicon-rich tungsten silicide (WSix, where x>2). Additionally, diffusion is dependent on the crystalline structure of the buried metal, for example, whether nanocrystalline, microcrystalline, or polycrystalline. Another diffusion control method includes the use of thin “barrier layers” such as TaN, TiN, TiW, TiWN, inserted within the buried metal. The use of a thin layer will minimize series resistance.

After forming a structure similar toFIG. 7, various processing can be performed, for example to form an optional masked active area oxidation, for example using a local oxidation of silicon (LOCOS) process at other wafer locations. A pad oxide is then formed, followed by a hard mask oxide, a trench mask80, an oxide etch, and a silicon etch of the epitaxial layer70to form MOSFET gate trenches82which results in a structure similar toFIG. 8.

TheFIG. 8structure is cleaned to remove the mask80and expose the epitaxial layer70as depicted inFIG. 9, then an optional isotropic (round hole) etch can be performed, followed by removal of the hardmask to expose the silicon surface in the active regions. The wafer is cleaned, and a sacrificial oxide (sac ox) growth is performed in the active region using standard thermal oxidation. This sac ox is stripped off just prior to growing a high-quality gate oxide100over all exposed silicon surfaces in the active area (which includes the horizontal top surface, trench sidewall and trench bottom).

After growing gate oxide100, a blanket polysilicon deposition is performed. This polysilicon can be undoped or can be selectively doped using ion implantation, for example using doped P+ polysilicon over the PMOS region and doped N+ polysilicon over the NMOS regions, using masks. A selective polysilicon etch back is performed to leave polysilicon102in the trenches, to remove the polysilicon from the upper surface of the epitaxial layer, and to leave the gate oxide100on the upper surface of the epitaxial layer72as depicted inFIG. 10. The etch back can be done using plasma etch techniques or CMP.

Subsequently, a patterned N-body mask (not depicted) is formed to expose a region of the PMOS device, an N-body implant of N-type dopants is performed, and an N-body anneal is performed to result in theFIG. 11structure which forms an N-body110on the PMOS side64of the wafer as depicted.

Next, a patterned P-body mask (not depicted) is formed to expose a portion of the NMOS region62, a P-body implant of P-type dopants is performed, and a P-body anneal is performed to result in theFIG. 12structure which forms a P-body120on the NMOS side62of the wafer as depicted.

After forming a structure similar toFIG. 12, a mask130is formed over the structure as depicted inFIG. 13which will be used to pattern various N+ regions. In this embodiment, this mask pattern defines PMOS body contacts132(i.e. contacts to the N-type body110of the PMOS device), defines the NMOS source134, and provides NMOS doping into the polysilicon regions102on the NMOS side62of the structure, while the polysilicon on the PMOS side64of the structure is protected from the N-type implant by the mask130. After forming the mask, an N+ implant is performed, for example to a dose in the range of between about 1E15 atoms/cm2to about 1E16 using an implant energy of about 70 KeV at 0° tilt. An N+ anneal is subsequently performed to result in theFIG. 13structure.

It will be noted that the polysilicon102will form device gate electrodes. For low threshold (turn-on) voltage, it is preferred that the PMOS gates in PMOS region64are doped to a net P+ conductivity while the NMOS gates in NMOS region62are doped to a net N+ conductivity. In the process depicted, N+ dopants are therefore implanted into the NMOS gates, while the P+ material is implanted the PMOS gates. However, in an alternate process, both the NMOS and PMOS polysilicon gates can receive N-type dopants, with mask140blocking the P-type implant from both the NMOS and PMOS polysilicon gates such that the gates are all doped to an N-type conductivity.

The N+ mask is removed and a P+ mask140is formed similar to that depicted inFIG. 14. The P+ mask will be used to define NMOS body contacts142(i.e. contacts to the P-type body120of the NMOS device), a PMOS source144, and PMOS doping into the polysilicon regions102on the PMOS side of the structure, while the polysilicon on the NMOS side of the structure is protected from the P-type implant by the mask140. The P+ implant can be performed using boron or BF2to a dose of between about 1E15 to about 1E16 ions/cm2, for example a dose of about 2E15, and an implant energy of between about 5 KeV to about 80 KeV with 0° tilt to result in theFIG. 14structure. Other implant schemes are also contemplated.

The P+ mask140is removed and a blanket oxide deposition is performed, for example using undoped oxide or borophosphosilicate glass (BPSG). An oxide reflow such as a BPSG reflow can be performed to generally planarize the surface of the assembly. A contact mask is formed over the oxide, then an etch is performed to remove the exposed oxide and the exposed gate oxide, with the etch stopping on the epitaxial layer70to form dielectric structures150. An oxide reflow such as a rapid thermal anneal (RTA) is performed and the mask is removed to result in a structure similar to that ofFIG. 15.

A blanket metal is formed, masked, and etched to form the NMOS and PMOS sources, as well as the gate connections to the respective device. This can result in a structure similar toFIG. 16, depicting PMOS source metal160which electrically contacts the PMOS source110(i.e. N-body) through N+ contacts132, and NMOS source metal162which electrically contacts the NMOS source120(i.e. P-body) through contacts142. Note that the gate metallization is not depicted inFIG. 16. The gates can be connected at the periphery of the active region, for example in accordance with known techniques.FIG. 16depicts a high side vertical trench gate PMOS device164and a low side vertical trench gate NMOS device166for the low side.

The die ofFIG. 16provides a first portion160and a second portion162of a single metal layer, with the first portion160supplying a connection to the source110of the PMOS transistor164and the second portion162supplying a connection to the source120of the NMOS transistor166. The die further includes a conductive structure32, for example a buried metal layer such as tungsten and/or tungsten silicide which connects the drains of the PMOS transistor and the NMOS transistor such that the two devices have a common drain. That is, the drains of the two devices are formed within the epitaxial layer, which is connected by the conductive layer32to electrically short the two drains together. Because the two drains are shorted together, they form a common drain which is electrically the same node. The drains of both devices can therefore be accessed from a single contact elsewhere on the die, such as the backside of the wafer, which can provide packaging advantages.

The source of the PMOS high side device receives voltage in (VIN), for example through metal160. The source of the NMOS low side device is the ground, and can be connected through metal162. The back of the die supplies the voltage out to the inductor (i.e. the output of the output stage). That is, as referenced in the FIGS., the back side of the die is the switched node of the output stage. Polysilicon102provides trench gates for the transistors, and can be connected at the periphery of the active region. The metal sources of the PMOS and NMOS transistors can provide a shielding for the trench gates and, therefore, provide shielded-gate transistors for both the high side PMOS transistor and the low side NMOS transistor.

Another device is depicted inFIGS. 17 and 18. As depicted inFIG. 17, the substrate180is heavily doped to an N+++ conductivity with red phosphorus or arsenic, for example to a concentration of between about 1 E19 atoms/cm3and about 9E19 atoms/cm3. An epitaxial layer182doped with a slower diffuser than the substrate, for example arsenic or antimony having a concentration in the range of between about 1E17 atoms/cm3to about 5E18 atoms/cm3and a thickness of between about 1 μm and about 6 μm, for example, is grown over the top surface of the substrate180to act as a “buffer” region to absorb any up-diffusion from the highly doped substrate. This provides a device buffer layer below a subsequently formed conductive layer184. The conductive layer184, which can include W or WSix, can be formed on or over substrate to a thickness of between about 0.1 μm to about 1.0 μm as depicted inFIG. 17. A material such as polysilicon186is deposited on or over the conductive layer184to a thickness of between about 0.1 μm and about 4.0 μm. The polysilicon is planarized, for example using CMP. A device wafer188is attached to the polysilicon186, then the process can continue according to the process ofFIGS. 3-16to result in a structure similar to that depicted inFIG. 18. A device in accordance withFIG. 18may have a lower substrate resistance resulting from a higher dopant concentration, for example from the use of high concentration red phosphorous rather than other dopants.

Another device is depicted inFIGS. 19 and 20. As depicted inFIG. 19, the substrate190is heavily doped to an N+++ conductivity with red phosphorus or arsenic, for example to a concentration of between about 1E19 atoms/cm3and about 9E19 atoms/cm3. A patterned conductive layer which can include W or WSixcan be formed on or over substrate to a thickness of between about 0.1 μm to about 1.0 μm, then masked and etched so that it remains only in the PMOS regions, to result in the conductive layer192as depicted inFIG. 19. A material such as polysilicon194is deposited on or over the conductive layer to a thickness of between about 0.1 μm and about 4.0 μm. The thickness can be much larger than the W or WSixthickness to allow for global planarization in addition to local planarization over the wafer surface. The polysilicon194is planarized, for example using chemical mechanical polishing (CMP), a device wafer196is attached to the polysilicon194, then the process can continue according to the process ofFIGS. 3-16to result in theFIG. 20structure.

In this embodiment, the drains of the PMOS and NMOS devices are connected together through the N+++ substrate. The drain of the PMOS device is connected to the substrate through P-type doping which electrically contacts metal192, with metal192contacting the substrate190.

A design trade off in the implementation of this method may arise from the fast diffusion of dopants through a tungsten silicide layer. For example, if the concentration of the P buried layer66is higher than that of the N substrate190at their respective sides of the silicide192, the P buried layer will tend to diffuse through the silicide to form a net P region adjacent the bottom of the silicide thus PN junction isolating the PMOS drain from the substrate. If the P buried layer doping is lower than the N substrate doping, the N+ dopant that up diffuses through the silicide will tend to form a net N region adjacent the top of the silicide that PN junction isolates the PMOS drain from the silicide and thus from the N substrate. Each of these instances may defeat the intended common drain connection of the two devices. A similar situation may also occur in one or more earlier implementations. If so, the only drain to drain connection will be laterally through the silicide layer.

Buried metal192, in effect, electrically shorts the P+ drain72over the buried metal to the underlying N+ substrate190, while the drain of the NMOS device is connected to the substrate190through common N-type doping. In this embodiment, the NMOS device does not include buried metal in the drain region which results in a thicker epitaxial silicon layer. This, in turn, can result in an NMOS device having a higher breakdown voltage, resulting from the thicker epitaxial layer in the drain region.

Technology computer aided design (TCAD) simulations using 2D process and device simulation software can confirm the performance of a PMOS transistor fabricated using a process flow compatible with an NMOS transistor fabricated at the same time on the same wafer. A TCAD simulation is depicted inFIG. 21. An RDSONat VGS=12V of 20 milli-Ohm (mΩ)*mm2, obtained with a BVDSSof 26V, which is an excellent figure of merit for a P-channel device.

Thus the various structures and methods of the present teachings can provide a low cost solution with a minimized number of masks. The structure provided reduces costs, for example because it can be formed in an area which is smaller than two discrete dies. The device provided has is high efficiency and can operate at high frequency through elimination of parasitic inductance between the drain of the high side PMOS transistor and the drain of the low side NMOS transistor. This approach enables the use of vertical MOSFET structures for both the high side and low side devices, which can minimize the specific resistance (RDSON*area), while providing independent threshold control. Without being bound by theory, it is believed that an embodiment of the present teachings can provide a PMOS with lower specific resistance because the devices are vertical and the cell pitch can be smaller than is possible using lateral PMOS (compared to monolithically integrated NMOS and PMOS using prior approaches such as standard Integrated Circuit technologies). Cell pitch is decreased, for example, from the use of only two electrodes on the top surface (source and gate) while lateral devices require the use of three electrodes (source, gate, and drain) on the top surface. The resulting output stage device (or PowerDie) as described can be co-packaged with a controller IC, or may be used as a separate power stage. The use of PMOS simplifies the design of the controller integrated circuit since the VGSof a P-channel device is with respect to the VIN, which is one of the supply rails.

It will be understood that another embodiment of the present teachings includes switching N junctions with P junctions, and P junctions with N junctions.

Terms of relative position as used in this application are defined based on a plane parallel to the conventional plane or working surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “horizontal” or “lateral” as used in this application is defined as a plane parallel to the conventional plane or working surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal. Terms such as “on,” “side” (as in “sidewall”), “higher,” “lower,” “over,” “top,” and “under” are defined with respect to the conventional plane or working surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.