Flash memory cell with dual erase modes for increased cell endurance

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

TECHNICAL FIELD

The present disclosure relates to integrated circuit memory devices, and more particularly, to a flash memory cell with dual erase modes for increased endurance (lifespan) of the cell.

BACKGROUND

Integrated circuit memory cells typically have a limited useful lifespan, e.g., due to degradation of cell performance over time. For example, certain flash memory cells may wear out after repeated program/erase cycling, e.g., in the range of 100,000 to 10 million cycles. In a typical flash memory cell, the erase performance degrades faster than the program performance, as a function of program/erase cycles.

FIG. 1shows the effects of program/erase cycling on an example flash memory cell having a pair of floating gates. In particular,FIG. 1shows example measured erase current data (Ir1) as a function of program/erase cycles and measured program current data (Ir0) as a function of program/erase cycles. As shown, the erase current (Ir1) degrades faster than the program current (Ir0), as a function of program/erase cycles. Thus, the effective lifespan of such memory cell may be limited by the erase cycling of the cell.

SUMMARY

Embodiments of the present invention provide an integrated circuit device including at least one memory cell configured for dual erase modes. For example, each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the effective lifespan of the cell. Some embodiments provide an integrated circuit device including flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

Some embodiments provide a method including providing a memory cell, e.g., a flash memory cell, including a floating gate and a pair of program/erase nodes over the floating gate, and using control electronics to selectively switch between the pair of program/erase nodes to perform a series of erase functions in the memory cell. In some embodiments, the pair of program/erase nodes comprise an erase gate and a word line, or a coupling gate and a word line, for example.

In one embodiment, the control electronics may switch or alternate between the pair of program/erase nodes to perform erase functions in the memory cell. For example, the control electronics may switch back and forth between the pair of program/erase nodes after each erase function. As another example, the control electronics may switch between the pair of program/erase nodes after every N erase functions, wherein N is greater than 1, e.g., where N is at least 10, at least 100, at least 1,000, at least 10,000, or at least 1,000,000.

In one embodiment, the method may include maintaining a count of erase functions performed using each of the pair of program/erase nodes, and switching between the program/erase nodes for performing erase functions based at least on the count of erase functions performed using each of the pair of program/erase nodes.

In one embodiment, the method may include measuring an erase current of the memory cell, and switching between the program/erase nodes for performing erase functions based at least on the measured erase current.

Some embodiments provide an electronic device, including a memory cell, e.g., flash memory cell, including a floating gate and a pair of program/erase nodes over the floating gate, and erase control electronics configured to selectively alternate or switch between the pair of program/erase nodes to perform a series of erase functions in the memory cell, e.g., after each erase function, or after N erase functions, wherein N is at least 10, at least 100, at least 1,000, at least 10,000, or at least 1,000,000.

DESCRIPTION OF THE INVENTION

Embodiments of the present invention provide an integrated circuit device including at least one memory cell configured for dual erase modes. For example, each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. Some embodiments provide an integrated circuit device including flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over a floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

As used herein, a “program/erase” node may include any memory cell node or element coupled to a floating gate for program and/or erase functions. Example program/erase nodes include an erase gate, a program gate, a word line, and a “coupling gates” (e.g., a program or erase gate coupled to multiple floating gates, such as the erase gate/coupling gate EG/CG formed between and coupled to a pair of floating gates FG in the example flash memory cell shown inFIG. 2).

Some embodiments provide an integrated circuit device including an array of flash memory cells, where each memory cell includes a pair of floating gates, with an erase gate or coupling gate shared by the floating gates, and a separate word line formed over each floating gate. The integrated circuit device may utilize the erase gate/coupling gate and the word line over each floating gate selectively (e.g., in any switched or alternating manner) for the erase function. This may increase the lifespan of such memory cells, e.g., by 100%, as compared with conventional devices. In one example embodiment, the memory cells may comprise “SuperFlash” cells, e.g., “ESF1+” or “ESF1 EG” cells or variants thereof, from Microchip Technology Inc. having a headquarters at 2355 West Chandler Blvd.

FIG. 2shows an example flash memory cell10that includes a pair of floating gates (FG), a word line (WL) formed over each floating gate, and an erase gate, also referred to as a “coupling gate” (EG/CG) extending over both floating gates (FGs).FIG. 2also shows a pair of bit lines (BL) at opposing sides of the cell.

The inventors surprisingly discovered that performing erase functions through either the word line WL or the erase gate/coupling gate EG/CG over each floating gate FG results in a similar degradation of the cell erase performance over time, as illustrated by the example test results shown inFIGS. 3A-3Dfor an example flash memory cell of the type shown inFIG. 2.FIG. 3Ashows example erase current (Ir1) data for erase functions performed via the word line, whileFIG. 3Bshows example erase current (Ir1) data for erase functions performed via the erase/coupling gate. The two data sets (two lines) in each figure correspond with the two floating gates in the cell.FIG. 3Cshows example program current (Ir0) data for program functions performed via the word line, whileFIG. 3Dshows example program current (Ir0) data for program functions performed via the erase/coupling gate. Again, the two data sets (two lines) in each plot correspond with the two floating gates in the cell.

As shown in the erase data (FIGS. 3A-3B), the degradation of the erase current over time (as a function of program/erase cycles) is similar for erase functions performed via the word line (FIG. 3A) and erase functions performed via the erase/coupling gate (FIG. 3A). The inventors conceived the idea to selectively use both the word line and the erase/coupling gate for erase functions, in an alternating or switched manner, to thereby increase (e.g., double or substantially double) the useful life of the cell (as measured in cycles). Accordingly, with respect to the example flash memory cell shown inFIG. 2, an embodiment of the present invention involves selectively switching or alternating between the word line and the erase/coupling gate for performing erase functions at each floating gate.

Thus, some embodiments provide an electronic device (e.g., integrated circuit device) including one or more flash memory cells, and erase control electronics (e.g., circuitry) configured to alternate or switch between (a) performing erase functions through the erase/coupling gate and (b) performing erase functions through the word line for each floating gate of each flash cell. The erase control electronics may switch the erase node after each program/erase cycle, or after N cycles (where N is any number greater than 1), or based on a cumulative count of erase cycles performed via the EG/CG (“EG erase”) versus the WL (“WL erase”), or based on a measured erase current after an EG erase or after a WL erase, or in any other manner or based on any other input data.

FIG. 4illustrates an example integrated circuit device10including (a) a memory cell structure12including (at least) a pair of program/erase nodes14,16formed over a floating gate18, and (b) erase control circuitry or electronics20, according to example embodiments of the present invention. Each program/erase node14and16may comprise any type of node coupled to a floating gate18in a manner than allows erase functionality via the respective node14,16. Each program/erase node14and16may or may not also provide program functionality via the floating gate18, depending on the particular embodiment. In some embodiments, memory cell structure12represents only a portion of a larger memory cell. For example, memory cell structure12may represent only the left half of the flash memory cell shown inFIG. 2, where node14represents the left-side word line WL and node16represents the coupling gate EG/CG extending over both floating gates18.

Erase control electronics (e.g., circuitry)20may be configured to selectively switch between the program/erase nodes14and16for performing erase functions in the memory cell. For example, control electronics may switch or alternate between the pair of program/erase nodes to perform erase functions in the memory cell. For example, erase control electronics20may switch back and forth between program/erase nodes14,16after each successive erase function.

As another example, erase control electronics20may switch between program/erase nodes14,16after every N erase functions, wherein N is greater than 1, e.g., where N is at least 10 (e.g., between 10 and 100), at least 100 (e.g., between 100 and 1,000), at least 1,000 (e.g., between 1,000 and 10,000), at least 10,000 (e.g., between 10,000 and 100,000), at least 100,000 (e.g., between 100,000 and 1,000,000), or at least 1,000,000 (e.g., between 1,000,000 and 2,000,000). In such embodiments, erase control electronics20may be configured to maintain a count of erase functions performed using each program/erase node14,16, and switch between the program/erase nodes14,16for performing erase functions based at least on the current count of erase functions, e.g., when the count of consecutive erase functions via a particular node14,16exceeds N.

As another example, erase control electronics20may be configured to switch between program/erase nodes14,16as a function of an actual erase current of the memory cell. Thus, in one embodiments, erase control electronics20may include circuitry for measuring an erase current of the respective memory cell, and switching between the program/erase nodes14,16based at least on the measured erase current, e.g., when the measured erase current meets or crosses a defined threshold value. In another embodiment, erase control electronics20may include circuitry for comparing the erase current of the respective memory cell with a reference current value (e.g., a pre-set current value stored in a reserved memory bit), without performing an active measurement of the erase current, and triggering a switch between the program/erase nodes14,16based at least on the comparison.

Erase control electronics20may include any suitable circuitry, hardware, and/or logic instructions for providing any of the functionality disclosed herein. For example, erase control electronics20may include charge pumps and high voltage decoders for pulse generation, and latches, flip flops, or shift registers for storing the cycle count/position. In some embodiments, erase control electronics20may include comparators to compare the stored cycle count with an on-chip reference value, and determine when to switch the erase node. For example, the circuitry may trigger an erase node switch when the stored cycle count is greater than an on-chip reference value N, and reset the store cycle count back to 1. Alternatively, erase control electronics20may use binary memory to alternate after each successive erase, where a value of 0 may represent erasing via node14, and a value of 1 may represent erasing via node16, where the memory switches from 0 to 1, or from 1 to 0 after each cycle. In an example embodiment in which the erase node is switched based on the actual (measured or otherwise) erase current of the cell, erase control electronics20may set a reserved reference bit to a specific current value, e.g., 15 uA, and compare the cell erase current to this reference current value to determine whether to trigger an erase node switch, e.g., when the cell erase current drops below the reference current value.

FIG. 5illustrates an example integrated circuit device100including a flash memory cell102having the structure shown inFIG. 2, and erase control circuitry or electronics104, according to one embodiment of the invention. Flash memory cell102may include a pair of floating gates FG, a word line WL over each floating gate FG, and a shared erase gate/coupling gate EG/CG formed between and extending over the pair of floating gates.

Erase control circuitry electronics104may be configured to selectively switch between the WL and EG/CG over each floating gate for performing erase functions via the respective floating gate, e.g., using any of the switching techniques disclosed herein (e.g., in an alternating manner, after each N erase cycles, based on a measured erase current, etc.). Erase control circuitry electronics104may include any suitable circuitry, hardware, and/or logic instructions for providing such switching functionality, e.g., including any of the elements discussed above regarding erase control electronics20shown inFIG. 4.

In one example embodiment, device100may be configured to apply the following cell voltages for performing a WL erase for “+” cell operation and for performing an EG erase for “EG” cell operation:WL erase (“+” cell operation); WL=10V, CG=−5VEG erase (“EG” cell operation); EG=10V, WL=−5V

The initial erased cell currents (Ir1) may be identical. In some embodiments, device100may selectively favor “+” or “EG” cell operation, e.g., due to reduced voltage requirements resulting from cell scaling.

FIG. 6illustrates an example algorithm200for selectively using two program/erase nodes (e.g., a word line and a erase/coupling gate) for cell erase functions, by alternating between the two program/erase nodes after each program/erase cycle, according to an example embodiment. Algorithm200may be executed or implemented by device10or device100, for example, and more particularly, by erase control electronics20or104.

At202, erase control electronics20or104may set a cycle number counter to 1. At204, a cell erase function is requested by the device. At206, erase control electronics20or104may determine whether the cycle counter value is odd. Depending on the result, erase control electronics20or104may effect a Node A erase (e.g., WL erase) at208or a Node B erase (e.g., EG erase) at210. Erase control electronics20or104may then increase the cycle counter value by one, and await the next erase request.

FIG. 7illustrates an example method for selectively using two program/erase nodes (e.g., a word line and a erase/coupling gate) for cell erase functions, by switching between the two program/erase nodes after every N program/erase cycles, where N>1, according to an example embodiment. Algorithm300may be executed or implemented by device10or device100, for example, and more particularly, by erase control electronics20or104.

At302, erase control electronics20or104may set an erase state to “Node A erase.” At304, erase control electronics20or104may set a cycle number counter to 1. At306, a cell erase function is requested by the device. At308, erase control electronics20or104may determine whether the erase state is currently set to “Node A erase” (as opposed to “Node B erase). Depending on the result, erase control electronics20or104may effect a Node A erase (e.g., WL erase) at310or a Node B erase (e.g., EG erase) at312. Erase control electronics20or104may then increase the cycle counter value by one at314.

Erase control electronics20or104may then compare the cycle counter value to a define threshold value N. N may be any suitable value greater than 1, e.g., as discussed above with respect toFIG. 4. If the cycle counter value does not exceed N, the device maintains the current erase state (“Node A erase” or “Node B erase”) and awaits the nest erase request at306. Alternatively, if the cycle counter value does exceed N, erase control electronics20or104switches the erase state at318-322. At318, erase control electronics20or104determines the current erase state, and based on the result, switches to the other erase state at320or322. Erase control electronics20or104may then reset the erase cycle counter to one at304, and await the next erase request.

FIG. 8illustrates an example voltage truth table400that may be implemented by device100shown inFIG. 5for operating the example memory cell102, including example voltages for selectively performing WL erase and EG erase, according to one example embodiment.