Method of and system for manufacturing semiconductor device

A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.

BACKGROUND

Electronic equipment involving semiconductor devices is essential for many modern applications. Technological advances in materials and design have produced generations of semiconductor devices, in which each generation includes smaller and more complex circuits than the previous generation. In the course of advancement and innovation, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased. Such advances have increased complexity of processing and manufacturing semiconductor devices. Therefore, there is a continuous need to modify the structure and manufacturing method of the devices in order to improve device robustness as well as reducing manufacturing cost and processing time. Among the various studies of the semiconductor devices, advanced types of field-effect transistors (FET), such as nanosheet FET, have attracted a great deal of attentions for their superior performance, e.g., better gate control and improved short channel effect.

DETAILED DESCRIPTION

The term “standard cell” or “cell” used throughout the present disclosure refers to a group of circuit patterns in a design layout to implement specific functionalities of a circuit. A standard cell is comprised of various patterns in one or more layers and may be expressed as unions of polygons. A design layout may be initially constructed through placement of a combination of identical or different standard cells during the layout design stage. The geometries of the patterns in the cells may be adjusted at different stages of layout design in order to compensate for design and process effects. A standard cell may cover circuits corresponding to a portion or an entirety of a die to be manufactured. The standard cells may be accessible from cell libraries provided by semiconductor circuit manufacturers or designers.

Some embodiments of the present disclosure discuss methods of generating standard cells associated with nanosheet field-effect transistor (FET) devices. Due to the fact that the widths and spacings of the nanosheets are irregular discrete numbers, it may involve a great deal of work in a layout revision stage to modify the design layout for fulfilling design rules while maintaining circuit efficiency in area and power. Through the design methodology of the proposed scheme, a set of standard cells associated with nanosheets is generated. In this set, the standard cells are provided with individual nanosheet widths and spacings selected from a finite set of widths and spacings for nanosheets to achieve the goal of equal cell heights among the standard cells, thereby simplifying efforts and cost of modifying the layout of the standard cells in a layout revision stage.

Some embodiments of the present disclosure also discuss layout methods and associated structures of semiconductor devices based on one or more nanosheet field-effect transistor (FET) devices. Through the proposed layout scheme, a semiconductor device is configured to accommodate different types of nanosheet FETs with different device size and capabilities. For example, different standard cells associated with nanosheet FETs can be designed having equal cell heights with different nanosheet sizes and spacings to fulfill design rules of nanosheet dimensions. In this way, the design cycle can be improved in searching for compliant nanosheet sizes and spacings while a better balance between area, power and performance is achieved.

FIG.1Ais a perspective view of a semiconductor device100, in accordance with some embodiments of the present disclosure. Referring toFIG.1A, the semiconductor device100is a nanosheet FET device. However, other types of semiconductor device are also possible for the semiconductor device100, such as nanowire FET, fin-type FET, or the like. Referring toFIG.1A, the semiconductor device100includes substrates102and112, an isolation region104, gate electrodes106and108and nanosheet stacks114and124.

The substrates102and112are formed from a same substrate wafer (not shown) and can be seen as two protrusive portions of the substrate wafer. In some embodiments, the substrates102and112are in a strip shape extending in the x-axis. The substrates102and112may be formed from a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrates102and112may include silicon; germanium; a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; combinations thereof, or the like.

The isolation region104is formed in trenches between the substrates102and112. In some embodiments, the isolation region104has an upper surface level with the upper surfaces of the substrates102and112. The isolation regions114may include insulating materials, such as a dielectric material, e.g., silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like. The isolation region114may be formed by chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a combination thereof, or the like. Other insulation materials formed by any suitable process may be also used. In some embodiments, an annealing process may be performed after the insulation material of the isolation region114is deposited.

The gate electrodes106and108are formed over the substrates102and112and the isolation region104. The gate electrodes106and108may extend in a direction, e.g., the y-axis, perpendicular to the direction in which the substrates102and112extend. In some embodiments, each of the gate electrodes106and108is made of one or more layers of conductive materials, such as doped polysilicon or metallic materials, e.g., Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, or the like, and may further include other work function adjusting metals, diffusion barrier materials or glue layers.

The nanosheet stacks114and124each includes a plurality of separated nanosheets in a stacked form and is arranged over the substrates102and112and the isolation region104. A nanosheet in the nanosheet stack114or124generally refers to a two-dimensional semiconductor slab with a length or width greater than about 100 nm and a thickness less than about 20 nm. The nanosheet stacks114and124may extend in a direction, e.g., the x-axis, in which the substrates102and112extend. In some embodiments, the nanosheet stacks114and124extend in a direction perpendicular to the direction in which the gate electrodes106and108extend. The nanosheet stacks114and124may overlap the gate electrodes106and108. In some embodiments, a portion of each nanosheet of the nanosheet stacks114and124is surrounded by the gate electrodes106and108.

In some embodiments, the nanosheet stacks114and124and the substrates102and112are formed from the same substrate wafer using photolithography and etching operations on this substrate wafer. The nanosheet stack114or124may be doped with an n-type impurity, e.g., arsenic, phosphorus, or the like, to form an n-type nanosheet FET, or may be doped with a p-type impurity, e.g., boron or the like, to form a p-type nanosheet FET. The stacked nanosheets of a same nanosheet stack114or124are configured to form a combined channel region or a combined source/drain region of a nanosheet FET. For example, the portion of each nanosheet of the nanosheet stack114which overlaps the gate electrode106serves as a combined channel region of a first nanosheet FET, while the other portions of each nanosheet of the nanosheet stack114on two sides of the channel region serves as the source/drain regions of the first nanosheet FET. Similarly, the portion of each nanosheet of the nanosheet stack124which overlaps the gate electrode106serves as a combined channel region of a second nanosheet FET, while the other portions of each nanosheet of the nanosheet stack124on two sides of the channel region of the second nanosheet FET serves as the source/drain regions of the second nanosheet FET.

In the depicted example, the number of nanosheet stacks114,124is set as two. However, the present disclosure is not limited thereto, and the number of the nanosheet stacks of the semiconductor device100can be less than or more than two. In the depicted example, each of the nanosheet stacks114and124has four nanosheet stacked over another. However, the present disclosure is not limited thereto, and the nanosheet stacks114and124can have an arbitrary number of nanosheets. In the depicted example, the number of gate electrodes is two. However, the present disclosure is not limited thereto, and the number of the gate electrodes of the semiconductor device100can be less than or more than two.

In some embodiments, the nanosheets in a same stack114or124are formed to have substantially equal dimensions, such as the nanosheet length measured in the x-axis, the nanosheet width measured in the y-axis and the nanosheet thickness measured in the z-axis. In some embodiments, the nanosheet dimensions of one nanosheet stack, e.g., the nanosheet stack114, may be different to those of another nanosheet stack, e.g., the nanosheet stack124. In some embodiments, the nanosheet stacks114and124have substantially equal nanosheet thicknesses and different nanosheet widths or nanosheet lengths.

In some embodiments, the nanosheet FET100further includes a work function adjusting layer118,128between the gate electrode108and each of the gate insulating layer116,126. In embodiments of an n-type nanosheet FET100, the work function adjusting layer118,128is formed of Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, a combination thereof, or the like, and may be formed to wrap around the gate insulating layer116,126by a deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), combinations thereof, or the like. In embodiments of a p-type nanosheet FET100, the work function adjusting layer118,128is formed of TiN, WN, TaN, Ru, Co, a combination thereof, or the like, and may be formed to wrap around the gate insulating layer116,126by ALD, CVD, PVD, combinations thereof, or the like.

FIG.2is a schematic diagram200of a design layout, in accordance with some embodiments of the present disclosure. The design layout200may include at least one semiconductor device, e.g., a complementary metal-oxide-semiconductor (CMOS) device, and can be implemented using a FET device, e.g., the nanosheet FET100as shown inFIG.1A. In some other embodiments, the design layout200includes a gate-all-around (GAA) device, a nanowire device, or the like.

The design layout200includes two exemplary rows R1and R2extending in a row direction along the x-axis. In the depicted example, only two rows are arranged in a column direction along the y-axis (perpendicular to the row direction) in the design layout200. However, the disclosure is not limited thereto and more than two rows are possible. The design layout200further includes first power rails V1and second power rails V2are alternatingly arranged and extend in the row direction (only one second power rail V2is illustrated inFIG.2for brevity). Each of the first power rails V1and the second power rail V2is arranged on an upper side or lower side of one of the rows R1, R2. In some embodiments, the center line of each of the first power rails V1and the second power rails V2is aligned with the upper side or lower side of the row R1or R2. In some embodiments, the first power rails V1are configured to supply first voltage while the second power rails V2are configured to supply second voltage different from the first voltage. In some embodiments, the first voltage is VDD and the second voltage is ground, or vice versa.

Referring toFIG.2, the design layout200includes a plurality of standard cells, for example, standard cells SC1, SC2, SC3, SC4and SC5. The standard cells SC1, SC2and SC3may be predetermined and stored in a cell library and accessible by a circuit designer. During a placement operation, the standard cells SC1, SC2and SC3are arranged in the row R1and the standard cells SC4and SC5are arranged in the row R2. AlthoughFIG.2shows only two or three standard cells in one row, the number of standard cells arranged in one row may be greater than three. Further, in some embodiments some of the standard cells contact each other, e.g., the standard cells SC1and SC2; in some other embodiments, the standard cells are separate from each other, e.g., the standard cells SC4and SC5.

The dimensions of the standard cells SC1through SC5are defined by their respective cell boundaries, in which each cell boundary includes an upper cell side and a lower cell side (both extending in the row direction) and a left cell side and a right cell side (both extending in the column direction). The standard cells SC1through SC5may be separated from one another or share at least one cell side. In some embodiments, the standard cells SC1through SC5have respective upper cell sides and lower cell sides aligned with the center lines of either the first power rails V1or the second power rails V2. Each standard cell SC1through SC5may have the same or different cell lengths in the row direction.

In some embodiments, a row height RH1of the first row R1is defined as a distance in the column direction between a center line CL1, extending in the row direction, of the lower first power rail V1and the center line CL2, extending in the row direction, of the second power rail V2. In some embodiments, a cell height CH1is determined based on a pitch between the lower first power rail V1and the second power rail V2. Similarly, a row height RH2of the second row R2is defined as a distance in the column direction between a center line CL2and a center line CL3of the upper first power rail V1. In some embodiments, the row height RH2is determined based on a pitch between the second power rail V2and the upper first power rail V1. In some embodiments, the row height RH1is the same as or different from the row height RH2.

In some embodiments, the cell height CH1of the standard cell SC1, SC2or SC3is determined based on the row height RH1. In some embodiments, the cell height CH1is determined based on a pitch between the lower first power rail V1and the second power rail V2. In some embodiments, the cell height CH1is equal to the row height RH1. Similarly, the cell height CH4of the standard cell SC4or SC5is equal to the row height RH2.

Each of the rows R1and R2defines one or more (row) active regions NOD and POD (indicated by dashed line boxes) along the row direction, in which the active regions POD and NOD have opposite conductivities. For example, the active region NOD denotes an active region doped with n-type dopants while the active region POD denotes an active region doped with p-type dopants. Each of the standard cells SC1through SC5includes one or more (cell) active regions (indicated by solid line boxes) with the dimensions defined by the cell boundaries of the respective standard cells and the boundaries of the respective (row) active region NOD or POD. For example, the standard cell SC1includes an n-type active region NOD1and a p-type cell active region POD1, where the n-type active region NOD1is defined by the cell boundary of the standard cell SC1and the boundary of the row active region NOD in the row R1, while the p-type active region POD1is defined by the cell boundary of the standard cell SC1and the boundary of the row active region POD in the row R1. The (cell) active region NODxy or PODxy (x denotes the index of the standard cell, and y is optionally used to denote the ordinal number to distinguish more than one similar active regions) within each standard cell SC1through SC5, e.g., the active regions NOD1and POD1, illustrated in the design layout200correspond to a top view of a nanosheet stack, e.g., nanosheet stack114or124, of the semiconductor device in the respective standard cell SC1through SC5. As a result, the configurations of the aforesaid (cell) active regions will determine the planar dimensions of the nanosheets in the nanosheet FET of the respective standard cell SC1through SC5.

Referring toFIG.2, the standard cells SC1, SC2, SC3include respective n-type active regions NOD1, NOD2, NOD3that are overlapped with each other in the row direction within the row active region NOD. In some embodiments, the active regions NOD1, NOD2and NOD3have different active region widths, referred to as OD (oxide definition) widths herein, measured in the column direction. In some embodiments, although the widths of the active regions NOD1, NOD2and NOD3are different, each of these active regions has at least one side, e.g., an upper side, aligned with one side of other active regions.

Similarly, the standard cells SC1, SC2, SC3include respective n-type active regions POD1, POD2, POD3overlapped with each other in the row direction within the row active region POD. In some embodiments, the active regions POD1, POD2and POD3have different OD widths. In some embodiments, although the widths of the active regions POD1, POD2and POD3are different, each of these active regions has at least one side, e.g., a lower side, aligned with a side of other active regions.

With respect to the standard cells SC1through SC5illustrated inFIG.2, only the (cell) active regions are shown for clarity. Other cell features, such as gate electrodes, are described in greater detail below.

FIG.3Ais a schematic diagram of design layouts for standard cells300A and300B, in accordance with various embodiments of the present disclosure. In some embodiments, the standard cells300A and300B correspond to the standard cells arranged in a same row, e.g., row R1or R2. The standard cells300A and300B are defined by their respective cell boundaries CB, and have cell heights CH1equal to a row height, e.g., RH1or RH2inFIG.2.

The standard cells300A and300B include respective gate electrodes GT1and GT2extending over a substrate (not shown) in the column direction. The materials of the gate electrodes GT1, GT2are similar to the gate electrodes106,108shown inFIG.1A. The standard cell300A further includes two active regions (OD) OD11and OD12extending in the row direction, in which channel regions of the active regions OD11and OD12are surrounded by the gate electrodes GT1. Similarly, the standard cell300B further includes two active regions (OD) OD21and OD22extending in the row direction, in which channel regions of the active regions OD21and OD22are and wrapped around by the gate electrodes GT2.

The standard cells300A and300B also include respectively conductive lines MD1and MD2extending in the column direction between adjacent gate electrodes GT1, GT2. The conductive lines MD1, MD2are arranged in a layer overlapping the gate electrodes GT1, GT2, and electrically coupled to the active regions OD11, OD12, OD21and OD22. The conductive lines MD1, MD2are configured to electrically couple source/drain regions of the active regions OD11, OD12, OD21, OD22in the standard cells300A,300B, to overlying or underlying layers of the standard cells300A,300B. The conductive lines MD1, MD2may be formed of doped polysilicon or metallic materials, such as copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or the like.

The standard cell300A or300B further includes a line separation pattern CMD, referred to herein as a “cut-MD pattern” extending in the row direction on an upper cell side and a lower cell side of the standard cell300A or300B. The cut-MD pattern CMD is used to signify an MD separation step during the semiconductor fabrication process, by which the contiguous conductive lines MD1or MD2extending in the column direction are segmented into aligned conductive line segments MD1or MD2with predetermined line lengths, as shown in the standard cell300A or300B. The positions of the cut-MD patterns CMD are shown inFIG.3Afor illustrational purposes. The cut-MD patterns CMD can also be arranged in other locations of the standard cell300A or300B for segmenting the conduction lines MD1or MD2extending through the standard cell300A or300B.

The standard cells300A and300B each includes a nanosheet FET formed of two active regions OD11and OD12or OD21and OD22. In some embodiments, the two active regions OD11and OD12(or OD21and OD22) are grouped and formed of one n-type active region and one p-type active region, or vice versa, as a basic unit to construct a semiconductor logic gate device, such as a NAND gate, an inverter gate, an XOR gate, an AND gate, a NOR gate, an AOI gate, or another suitable logic gate devices.

The grouped active regions OD11and OD12have equal nanosheet lengths L1measured in the row direction, and the grouped active regions OD21and OD22have equal nanosheet lengths L2measured in the row direction. In some embodiments, the nanosheet lengths L1and L2may be equal or different depending on various design requirements.

The grouped active regions OD11and OD12have nanosheet widths W11and W12, respectively, measured in the column direction, and the grouped active regions OD21and OD22have nanosheet widths W21and W22, respectively, measured in the column direction. The boundaries of these grouped active regions in each standard cell300A or300B are defined by lines K1and K2. The lines K1and K2are defined as lines extending in the row direction parallel to the upper or lower cell side of the standard cells300A,300B, in which the line K1is distant from the upper cell side by a marginal distance M1while the line K2is distant from the lower cell side by a marginal distance M2. The lines K1and K2define a flexibility width T1measured in the column direction. The upper sides of the active region OD11and OD21are aligned with each other at the line K1, while the lower sides of the active regions OD12and OD22are aligned with each other at the line K2. In some embodiments, the marginal distances M1and M2and the flexibility width T1are predetermined cell parameters that obey the constraint of the cell height CH1of the standard cell300A or300B as follows:
CH1=M1+T1+M2.

A spacing in the standard cell300A between the grouped active regions OD11and OD12has a spacing width S11, and a spacing in the standard cell300B between the grouped active region OD21and OD22has a spacing width S21, in which the following formula holds:
T1=S11+W11+W12=S21+W21+W22.

In some embodiments, the widths and spacings of active regions, e.g., the widths W11, W12, W21and W22and spacings S11and S21, are not only specifically determined according to the designer, but also are subject to the manufacturing capability. In some embodiments, although the values of the widths W11, W12, W21and W22and spacings S11and S21can be arbitrary in certain ranges for a designer, these value ranges may not pass the design rule check due to manufacturing limitations. In some embodiments, the active regions of the standard cells300A and300B adopt nanosheets, and the widths and spacings of the associated nanosheets as provided include only a predetermined set of numbers compliant with manufacturers' requirements. In some embodiments, these numbers are neither related to each other nor unpredictable in terms of an equation or formula.

In view of the unpredictable nature of the selected widths and spacings of the nanosheets, it may be a time-consuming work in tuning the dimensions of the nanosheets in a layout revision stage. This is because a small increment of an originally selected nanosheet width (spacing) picked from the set may not be included in the same set, and a greater incremental increase may be necessary, which usually exceeds the cell height of the standard cell at issue. As a result, an attempt to tune the width of a single nanosheet may inevitably involve alteration of cell heights across a large area of the design layout. The design cycle, area and power of the revised design layout may not be optimized due to the revised design layout in the context of nanosheet FETs.

In view of the above, some embodiments of the present disclosure propose a procedure to provide a standard cell library by generating a plurality of standard cells for nanosheet FETs with different selected nanosheet widths and spacings selected from a predetermined set of widths and spacings while ensuring that these standard cells have equal cell heights for the convenience of design layout.

FIG.3Cincludes tables for determining widths and spacings of active regions in various standard cells, in accordance with some embodiments. For the description ofFIG.3C, widths and spacings of active regions are correspondingly referred to as nanosheet widths and nanosheet spacings. Tables (a) and (b) include example formulas for determining combinations of nanosheet widths and nanosheet spacings that will result in cells having different nanosheet widths but the same cell height. Tables (c) and (d) include specific examples of applying a predetermined set of nanosheet widths and nanosheet spacings in Tables (a) and (b).

In Table (a), the first row and the first column list nanosheet widths W1, W2, W3, W4in a predetermined set of nanosheet widths. Each of the nanosheet widths W11, W12, W21and W22inFIG.3Ais configured to have one of the predetermined nanosheet widths W1, W2, W3, W4. In this example, W11=W12and W21=W22, and W11and W21are listed in Table (a). A formula for ΔW=2*(|W11−W21|) is listed in various cells of Table (a). For example, the cell at the column corresponding to W3and the row corresponding to W1has a formula 2*(|W1−W3|).

In Table (b), the first row and the first column list nanosheet spacings S1, S2, S3, S4, S5in a predetermined set of nanosheet spacings. Each of the nanosheet spacings S11, S21inFIG.3Ais configured to have one of the predetermined nanosheet spacings S1, S2, S3, S4, S5. A formula for ΔS=|S11−S21| is listed in various cells of Table (b). For example, the cell at the column corresponding to S3and the row corresponding to S1has a formula |S1−S3|.

As discussed herein, in the example configuration inFIG.3A, to achieve the same cell height CH1in various cells, the flexibility width T1is configured to be the same in such cells, i.e., T1=S11+W11+W12=S21+W21+W22. When ΔS=ΔW, this relationship for T1is satisfied. In some embodiments, Tables (a) and (b) are used to calculate various values for ΔS and ΔW. A cell in Table (a) having the same value (other than zero) as a cell in Table (b) indicates ΔS=ΔW and corresponding combinations of nanosheet widths and nanosheet spacings that will result in cells having the same T1and the same cell height.

Tables (c) and (d) show specific numeric examples for Tables (a) and (b). The first row and the first column of Table (c) list exemplary nanosheet widths selected from a predetermined set of nanosheet widths in the unit of nanometer, while the first row and the first column of Table (d) list exemplary nanosheet spacings selected from a predetermined set of nanosheet spacings in the unit of nanometer. Any nanosheet width or nanosheet spacing values not included in the predetermined set of nanosheet widths or nanosheet spacings may not pass the design rule check in an initial layout design stage or a layout revision stage. A value in a cell (x, y) of Table (c) represents a width difference ΔW calculated as described with respect to Table (a) for the nanosheet widths in the x-th row and the y-th column. Similarly, a value in a cell (x, y) of Table (d) represents a spacing difference ΔS calculated as described with respect to Table (b) for the nanosheet spacings in the x-th row and the y-th column. A cell in Table (c) and a cell in Table (d) that have the same value are indicated by the same label, e.g., one of L_a1, L_a2, L_a3, L_b1, L_b2 and L_c1.

The nanosheet widths W11, W12, W21and W22, and corresponding nanosheet spacings S11, S21selected for generating the standard cells300A and300B can be obtained from Tables (c) and (d). For example, in Table (c), the set of selected values of the widths W11=W12and W21=W22are provided as 15, 22, 35 and 41 (nm), while, in Table (d), the set of selected values of the spacings S11and S21are provided as 28, 34, 36, 40, 66 and 80 (nm, the unit is omitted for brevity hereinafter). Given the finite numbers of the selected widths and spacings, there is a finite number of combinations of nanosheet widths and nanosheet spacings that satisfy the same flexibility width T1across the standard cells300A and300B.

An exemplary fulfilling condition is given with reference to the entries in Tables (c) and (d) with labels L_a1 which indicate that the flexibility width T1is kept as110with W11=W12=15 and S11=80 in standard cell300A, and W21=W22=22 and S21=66 in standard cell300B. Similarly, another fulfilling condition is given with reference to the entries in Tables (c) and (d) with labels L_a2, which indicate that the flexibility width T1is kept as110with W11=W12=15 and S11=80 in standard cell300A, and W21=W22=35 and S21=40 in standard cell300B. A further fulfilling condition is given with reference to the entries in Tables (c) and (d) with labels L_a3, which indicate that the flexibility width T1is kept as110with W11=W12=15 and S11=80 in standard cell300A, and W21=W22=41, and S21=28 in standard cell300B.

Given the above, the standard cell300A or300B can be generated sharing an equal flexibility width T1=110 with four different combinations of selected nanosheet widths and nanosheet spacings. The cell heights CH1of different standard cells can be kept unchanged given that the marginal distances M1and M2are set equal in the standard cells300A and300B, while the nanosheet dimensions, e.g., nanosheet width and/or nanosheet spacing, can be made various, i.e., selected from a predetermined set of nanosheet widths and nanosheet spacings, in the standard cells300A and300B.

As shown inFIG.3C, six entries of Tables (c) and (d) inFIG.3Care marked with labels (e.g., L_a1, L_a2, L_a3, L_b1, L_b2 and L_c1) to indicate the compliant combinations of nanosheet widths and nanosheet spacings to achieve equal flexibility widths T1, thereby attaining the purpose of equal cell heights of the standard cells300A and300B. In some embodiments, some entries of Tables (c) and (d) are left without any label, which indicates no compliant combinations exist with respect to these nanosheet widths and nanosheet spacings to achieve equal flexibility widths T1, and thus these combinations are discarded from consideration during the generation of standard cells for a standard cell library.

The marginal distance M1or M2is selected in a manner similar to that for selecting compliant nanosheet widths and nanosheet spacings with reference toFIG.3C. Referring toFIG.2andFIG.3A, the marginal distance M1or M2may be set as one half of a spacing between two adjacent active regions of two abutting standard cells, e.g., a spacing Sx between the active regions NOD3and NOD42, i.e., M1=Sx/2. For example, the marginal distance M1or M2is selected from the set formed of numbers {14, 17, 18, 20, 33, 40} being half of the corresponding values {28, 34, 36, 40, 66, 80} in Table (d) ofFIG.3C. In this way, when two standard cells abut in the column direction, the adjacent marginal distance M1or M2of each standard cell contributes one half of the spacing between the cell boundary and a closest nanosheet, and thus the total spacing between two adjacent nanosheets of the abutting standard cells fulfill the requirement as provide in the set of the spacings shown in Table (d).

In some embodiments, the grouped active regions OD11and OD12(or the grouped active regions OD21and OD22) have equal nanosheet widths to maintain comparable electrical performance for the grouped active regions OD11and OD12(or the grouped active regions OD21and OD22). Under this assumption, the above formula can be further simplified as follows.
T1=S11+2*W11=S21+2*W21.

According to the above formulas, the nanosheet width W11can be different from the nanosheet width W21by an amount of D=|S11−S21|/2 to provide design flexibility between the standard cells300A and300B under the constraint of equal cell heights CH1for the standard cells300A and300B. In some embodiments, the difference between the widths W11and W21is greater than a tolerance level due to process variations during manufacturing of the nanosheets OD11and OD21. In some embodiments, the nanosheet width W11is different from the nanosheet width W21by at least 2.5% of the nanosheet width W11, by at least 5% of the nanosheet width W11or by at least 10% of the nanosheet width W11. Accordingly, the width S11is different from the width S21by an amount greater than a tolerance level due to process variations during manufacturing of the nanosheets OD11and OD21. In some embodiments, the spacing width S11is different from the spacing width S21by at least 5%, 10% or 20%, of the nanosheet width W11.

In some embodiments, the nanosheet width W11or W12in the standard cell300A is a multiple of the nanosheet width W21or W22, respectively, in the standard cell300B.

In some embodiments, the flexibility widths T1in the standard cells300A and300B are kept equal but may not be flush with each other along the lines K1and K2. In other words, the marginal distances M1and M2in the standard cell300A may not be equal to the corresponding marginal distances M1and M2in the standard cell300B. In some embodiments, to ensure equal cell height CH1across the standard cells300A and300B, the sum of marginal distances M1+M2in the standard cell300A is set to be equal to the sum of marginal distances M1+M2in the standard cell300B, in which the individual marginal distances M1and M2for the standard cells300A and300B are selected to be one half of any of the spacings in Table (d). In this way, the requirement of equal cell height CH1can still be maintained and greater design flexibility of the standard cells can be obtained.

As discussed previously, the planar areas of the nanosheet, determined by the nanosheet length and width, are closely related to the electrical performance of the nanosheet FET. The nanosheet widths and nanosheet spacings may be selected from a predetermined set of specific numbers of nanosheet widths and nanosheet spacings due to some manufacturing constraints. Therefore, the proposed framework of standard cell generation provides as many compliant combinations of nanosheet widths and nanosheet spacings as possible for a same type of standard cell, e.g., standard cells having the same functionality, with equal cell heights. For example, a standard cell library is provided or generated to include a plurality of inverter cells having the same cell height but with different nanosheet widths and/or nanosheet spacings. These inverter cells can replace each other in the circuit design stage. This will provide benefits when revisions to the placed cell layouts are required to meet the design requirements in the circuit design stage. For example, a placed cell that fails the circuit simulation may not need to be redesigned from scratch. Rather, the failed cell, e.g., an inverter cell, can be efficiently replaced with a similar standard cell, e.g., another inverter cell, which has the same cell height but with different nanosheet widths without revising other portions of the already placed layout or alteration of the cell height. As a result, a better tradeoff between performance, area and power is achieved while the design cycles can be improved.

FIG.3Bis a schematic diagram of design layouts for standard cells300C and300D, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells300C and300D are similar to those of the standard cells300A and300B, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIG.3AandFIG.3B, new lines K3and K4are used to define a flexibility width T2, in which the line K3is aligned with the upper cell sides of the standard cells300C and300D, and the lower sides of the active regions OD11and OD21are aligned with each other at the line K4. Lines K4and K2are used to define a flexibility width T4. As a result, the nanosheet widths W11, W12, W21and W22are tunable according to the following formulas:
T2=S21+W11=S22+W21.
T3=S31+W12=S32+W22.

The determination of the flexibility width T2and the selection of compliant nanosheet widths W11, W21and nanosheet spacings S21, S22are performed with help of Tables (a) and (b), or Tables (c) and (d), shown inFIG.3C, in a manner similar to that discussed for determining the flexibility width T1shown inFIG.3A. Similarly, the determination of the flexibility width T3and the selection of compliant nanosheet widths W12, W22and nanosheet spacings S31, S32are performed with help of Tables (a) and (b), or Tables (c) and (d), shown inFIG.3C, in a manner similar to that discussed for determining the flexibility width T1shown inFIG.3A. With the above arrangement, the active region OD12can be designed to have the nanosheet width W12independent of the nanosheet width W11of the active region OD11under the constraint of the flexibility width T2. Similarly, the active region OD22can be designed to have the nanosheet width W22independent of the nanosheet width W21of the active region OD21under the constraint of the flexibility width T3.

According to the above formula, the nanosheet width W12can be different from the nanosheet width W22by an amount of D=|S31-S32| to provide design flexibility between the standard cells300A and300B under the constraint of the flexibility width T3for the standard cells300A and300B. In some embodiments, the difference between the widths W12and W22is greater than a tolerance level due to process variations during manufacturing of the nanosheets OD12and OD22. In some embodiments, the nanosheet width W12is different from the nanosheet width W22by at least 2.5%, 5% or 10% of the nanosheet width W12. Accordingly, the spacing width S31is different from the spacing width S32by an amount greater than a tolerance level due to process variations during the manufacturing of the nanosheets OD21and OD22. In some embodiments, the spacing width S21is different from the spacing width S22by at least 2.5%, 5% or 10% of the nanosheet width W21.

FIG.4Ashows schematic diagrams of design layouts for standard cells400A and400B, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells400A and400B are similar to those of the standard cells300A and300B, and description of similar aspects are not repeated herein for brevity. Referring toFIG.3AandFIG.4A, the active regions OD11, OD12, OD21, OD22and lines K1, K2in the standard cells400A and400B are similar to those in the standard cells300A and300B. The standard cells400A and400B each further includes a third active region OD13and OD23with respective nanosheet widths W13and W23measured in the column direction. In some embodiments, the active region OD13or OD23is configured to be paired with another active region of another standard cell for forming a nanosheet FET, in which the standard cells of these paired active regions will be arranged in adjacent rows in a cell placement operation.

The nanosheet widths W11, W12, W21, W22of the grouped active regions OD11, OD12, OD21, OD22are defined by lines K1and K2and the flexibility width T1. A third line K3is defined as a line extending in the row direction parallel to the upper or lower cell side of the standard cells300A,300B, in which the line K3is distant from the lower cell side of the standard cells300A,300B by a marginal distance M2while the line K2is distant from the line K3by a flexibility width T2. In some embodiments, the marginal distances M1and M2and the flexibility widths T1and T2are predetermined cell parameters and obey the constraint of the cell height CH1as follows:
CH1=M1+T1+T2+M2.

The upper sides of the active regions OD11and OD21are aligned with each other at the line K1, while the lower sides of the active regions OD12and OD22are aligned with each other at the line K2, in which the following formula holds:
T1=S11+W11+W12=S21+W21+W22.

Similarly, the lower side of the active regions OD13and OD23are aligned with each other at the line K3, and a spacing width S12or S22exists between the active regions OD12and OD13or between the active region OD22and OD23, in which the following formula holds:
T2=S12+W13=S22+W23.

In some embodiments, the nanosheet width W11, W12or W13in the standard cell400A is a multiple of the nanosheet width W21, W22or W23associated with the same flexibility width T1or T2of the standard cell400B.

The different flexibility widths T1and T2can be different from each other and the spacing widths S11, S12, S21and S22can be different from each other. As a result, the active region OD13can be designed to have the tunable nanosheet width W13independent of the tunable nanosheet width W11or W12under the constraint of the flexibility width T1. Similarly, the active region OD23can be designed to have the tunable nanosheet width W23independent of the tunable nanosheet width W21or W22under the constraint of the flexibility width T2.

FIG.4Bshows schematic diagrams of design layouts for standard cells400C and400D, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells400C and400D are similar to those of the standard cells400A and400B, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIG.4AandFIG.4B, the standard cells400C and400D further include new lines K4and K5defining a flexibility width T3, for the active regions OD13and OD23, instead of the flexibility width T2inFIG.4A. The upper sides of the active regions OD13and OD23are aligned with each other at the line K4while the line K5is aligned with the lower cell sides of the standard cells400C and400D. The line K2is distant from the line K4by a marginal distance M3instead of the marginal distance M2inFIG.4A. As a result, the following formulas hold:
T3=S13+W13=S23+W23.
CH1=M1+T1+M3+T3.

FIG.4Cshows schematic diagrams of design layouts for standard cells400E and400F, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells400E and400F are similar to those of the standard cells400A and400B, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIG.4AandFIG.4C, the standard cells400E and400F further include new lines K6and K7defining a flexibility width T4, for the active regions OD11and OD21, instead of the flexibility width T1inFIG.4A. The line K7further defines a flexibility width T5with the line K2, for the active regions OD12and OD22, instead of the flexibility width T1inFIG.4A. The line K6is aligned with the upper cell sides of the standard cells400E and400F while the lower sides of the active regions OD11and OD21are aligned with each other at the line K7. A spacing width S14or S24is defined as a distance between the line K6and the upper side of the active region OD11or OD21. A spacing width S15or S25is defined as a distance between the line K7and the upper side of the active region OD12or OD22. As a result, the following formulas hold:
T4=S14+W11=S24+W21.
T5=S15+W12=S25+W22.
CH1=T4+T5+T2+M2.

FIG.4Dshows schematic diagrams of design layouts for standard cells400G and400H, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells400G and400H are similar to those of the standard cells400C,400D,400E and400F, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIGS.4B,4C and4D, the standard cells400G and400H can be seen as a combination ofFIG.4BwithFIG.4Cby adopting the lines K6, K7, K2, K4and K5for defining the flexibility widths T4, T5and T3, as discussed above. As a result, the following formula holds:
CH1=T4+T5+M3+T3.

FIG.5Ais a schematic diagram of design layouts for standard cells500A and500B, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells500A and500B are similar to those of the standard cells400A and400B, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIG.4AandFIG.5A, the active regions OD11, OD12, OD21, OD22and lines K1, K2in the standard cells500A and500B are similar to those in the standard cells400A and400B, in which the grouped active regions OD11and OD12(or OD21and OD22) are configured to form a first nanosheet FET of the standard cell500A (or500B). The standard cells500A and500B each further includes a fourth active region OD14and OD24with respective nanosheet widths W14and W24measured in the column direction. In some embodiments, the active region OD13or OD23is grouped with the active region OD14or OD24and the grouped active regions OD13/OD23and OD14/OD24are configured to form a second nanosheet FET.

The nanosheet widths of the aforesaid active regions OD11through OD14and OD21through OD24and their related parameters are defined in a way similar to those discussed in previous embodiments. For example, nanosheet widths W11, W12, W21, W22of the grouped active regions OD11, OD12, OD21, OD22are defined by lines K1and K2and a flexibility width T1along with spacing widths S11and S21. Nanosheet widths W13, W14, W23, W24of the grouped active regions OD13, OD14, OD23, OD24are defined by lines K3and K4and a flexibility width T2along with spacing widths S21and S22. The lines K1through K4are defined as lines extending in the row direction parallel to the upper or lower cell side of the standard cells500A,500B. The lines K1and K4are distant from the upper and lower cell sides, respectively, of the standard cells500A and500B by marginal distances M1and M2, respectively. The line K2is distant from the line K3by a marginal distance M3. In some embodiments, the marginal distances M1, M2and M3and the flexibility widths T1and T2are predetermined cell parameters and obey the constraint of the cell height CH1as follows:
CH1=M1+T1+M3+T2+M2.

The upper sides of the active regions OD11and OD21are aligned with each other at the line K1, while the lower sides of the active regions OD12and OD22are aligned with each other at the line K2, in which the following formula holds:
T1=S11+W11+W12=S21+W21+W22.

The upper sides of the active regions OD13and OD23are aligned with each other at the line K3, while the lower sides of the active regions OD14and OD24are aligned with each other at the line K4, in which the following formula holds:
T2=S12+W13+W14=S22+W23+W24.

In some embodiments, the grouped active regions, such as the active regions OD11and OD12, OD21and OD22, OD13and OD23, and OD14and OD24, have equal nanosheet widths to maintain comparable electrical performance between the grouped active regions. Under this assumption, the above formula can be further simplified as follows:
T1=S11+2*W11=S21+2*W21.
T2=S12+2*W13=S22+2*W23.

In some embodiments, the nanosheet width W11, W12, W13or W14in the standard cell500A is a multiple of the nanosheet width W21, W22, W23or W24associated with the same flexibility width T1, T2in the standard cell500B.

FIG.5Bshows schematic diagrams of design layouts for standard cells500C and500D, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells500C and500D are similar to those of the standard cells500A and500B, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIG.5AandFIG.5B, the standard cells500C and500D further include new lines K5, K6, K7, K8, K9and K10defining flexibility widths T3, T4and T5, along with respective spacing widths S13, S23, S14, S24, S15and S25, instead of the flexibility widths T1and T2inFIG.4A. The lines K5and K10are aligned with the upper and lower cell sides, respectively, of the standard cells500A,500B. The lower sides of the active regions OD11and OD21are aligned with each other at the line K6. The upper sides of the active regions OD12and OD22are aligned with each other at the line K7while the lower sides of the active regions OD13and OD23are aligned with each other at the line K8. The upper sides of the active regions OD14and OD24are aligned with each other at the line K9.

The line K6is distant from the line K7by a marginal distance M4and the line K8is distant from the line K9by a marginal distance M5. As a result, the following formulas hold:
T3=S13+W11=S23+W21.
T4=S14+W12+W13=S24+W22+W23.
T5=S15+W14=S25+W24.
CH1=T3+M4+T4+M5+T5.

FIG.5Cshows schematic diagrams of design layouts for standard cells500E and500F, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells500E and500F are similar to those of the standard cells500A,500B,500C and500D, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIGS.5A,5B and5C, the standard cells500E and500F can be seen as a combination ofFIG.5AwithFIG.5B, in which new flexibility widths T6and T7are defined by the lines K7, K3and K9along with respective spacing widths S16, S26, S17and S27for replacing the flexibility width T4. As a result, the following formulas hold:
CH1=T3+M4+T6+T7+T5.

In this way, the active region OD12or OD22can be designed to have the nanosheet width W12or W22independent of the nanosheet width W13or W23of the active region OD13or OD23under the constraint of the flexibility width T6. Similarly, the active region OD13or OD23can be designed to have the nanosheet width W13or W23independent of the nanosheet width W12or W22of the active region OD12or OD22under the constraint of the flexibility width T7.

FIG.5Dshows schematic diagrams of design layouts for standard cells500G and500H, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells500G and500H are similar to those of the standard cells500A,500B,500C and500D, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIGS.5A,5B and5D, the standard cells500G and500H can be seen as a combination ofFIG.5AwithFIG.5B, in which new flexibility widths T8and T9are defined by the lines K6, K2and K8along with respective spacing widths S18, S28, S19and S29for replacing the flexibility width T4. As a result, the following formulas hold:
CH1=T3+T8+T9+M5+T5.

FIG.5Eshows schematic diagrams of design layouts for standard cells500I and500J, in accordance with various embodiments of the present disclosure. The arrangements of the standard cells500I and500J are similar to those of the standard cells500A,500B,500C and500D, and descriptions of similar aspects are not repeated herein for brevity. Referring toFIGS.5A,5B and5E, the standard cells500I and500J can be seen as a combination ofFIG.5AwithFIG.5B, in which the flexibility widths T7and T8are defined instead of the flexibility width T4. As a result, the following formula holds:
CH1=T3+T8+M3+T7+T5.

FIG.6Ais a flowchart of a layout method600A, in accordance with some embodiments. It should be understood that additional steps can be provided before, during, and after the steps shown in these figures, and some of the steps described below can be replaced or eliminated in other embodiments of the method600A. The order of the steps may be interchangeable.

At step602, design data of a semiconductor device are generated or received. The design data may be represented as a netlist, a schematic diagram, a circuit diagram or the like. In some embodiments, the semiconductor device includes at least one electronic circuit, which can be a logic gate device in various types, such as a NAND gate, an inverter gate, an XOR gate, an AND gate, a NOR gate, an AOI gate, or another suitable logic gate device. In some embodiments, the design data in step602are generated during a synthesis stage of a design flow for manufacturing the semiconductor device.

At step604, a design rule deck is received. In some embodiments, the design rule deck includes design rules, such as a predetermined set of specified values of widths and spacings associated with active regions. In some embodiments, the active regions are implemented by nanosheets, and the predetermined set includes specified values of nanosheet widths and nanosheet spacings. In some embodiments, the specified widths and spacings are provided by a semiconductor manufacturer or circuit designer. In some embodiments, the specified values of the widths and spacings are unrelated to each other and are unpredictable through an equation or formula. In some embodiments, the specified values of the widths and spacings are elements of an irregular data sequence.

At step606, a standard cell library is provided according to the design data, and includes a first cell and a second cell, e.g., standard cells300A and300B. The first cell comprises a first active region having a first width, and the second cell comprises a second active region having a second width different from the first width. In some embodiments, each of the first cell and the second cell includes a nanosheet FET having a respective nanosheet stack, in which a first nanosheet stack of the first cell overlaps a second nanosheet stack of the second cell in the row direction. The first cell and the second cell have equal cell heights. In some embodiments, the first nanosheet stack and the second nanosheet stack have different nanosheet widths and nanosheet spacings, which are selected from the predetermined set of widths and spacings of the design rule deck. The first cell and the second cell are discussed above and are not repeated for brevity.

At step608, a design layout is generated by placing the first cell and the second cell, e.g., in a same row, according to the design data. The step608may be performed during a placement and routing stage of a design flow for manufacturing a semiconductor device.

At step610, a lithography mask is manufactured according to the design layout. At step611, a semiconductor device is fabricated in which a layer of the semiconductor device is formed according to the lithography mask. In some embodiments, the semiconductor device is fabricated according to the design layout.

FIG.6Bis a flowchart of a layout method600B, in accordance with some embodiments. It should be understood that additional steps can be provided before, during, and after the steps shown in these figures, and some of the steps described below can be replaced or eliminated in other embodiments of the method600B. The order of the steps may be interchangeable.

The steps602,604,606,610and611of the method600B are similar to those of method600A, and thus descriptions of these steps are simplified. At step602, design data of a semiconductor device are generated or received. At step604, a design rule deck is received including a predetermined set of specified values for widths and spacings for active regions, e.g., nanosheet widths and nanosheet spacings. At step606, a standard cell library is provided which includes a first cell and a second cell according to the design data. In some embodiments, the first cell and the second cell have equal cell heights, and corresponding first and second active regions with different first and second widths. In some embodiments, the first and second active regions comprise first and second nanosheet stacks with different nanosheet widths and nanosheet spacings. In some embodiments, the different nanosheet widths and nanosheet spacings are selected from the predetermined set of nanosheet widths and nanosheet spacings of the design rule deck.

At step612, a design layout is generated by placing the first cell in a row. The step612may be performed during a placement and routing stage of a design flow for manufacturing a semiconductor device.

At step614, a circuit simulation is performed to examine the physical characteristics and the electrical performance of the design layout. In some embodiments, the circuit simulation includes a post-layout simulation. In some embodiments, additional steps, such as parasitic parameter extraction and timing analysis, may be performed to provide layout-related information to support the circuit simulation. At step616, it is determined whether the design layout meets the design requirement according to the circuit simulation result.

If affirmative, at step610, a lithography mask is manufactured according to the design layout. At step611, a semiconductor device fabricated in which a layer of the semiconductor device is formed according to the lithography mask. In some embodiments, the semiconductor device is fabricated according to the design layout.

If it is determined that the first cell fails the circuit simulation, that means a circuit revision is required. At step618, the first cell is replaced with the second cell of the same cell height, and the method600B loops back to step616for performing another circuit simulation. In some embodiments, the second cell has a nanosheet width greater than that of the first cell and thus is capable of providing greater circuit performance than the first cell given the same cell height. In some embodiments, since the second cell resembles the first cell in most portions of the cell layout except for the nanosheet width, the difference between the original design layout incorporating the first cell and the revised design layout incorporating the second cell is minimized. In this way, the likelihood of revising the remaining portions of the revised design layout is reduced or minimized accordingly, and the cycle time of revising the design layout can be greatly shortened.

FIG.7Ais a schematic diagram700showing an integrated circuit (IC) manufacturing system, in accordance with some embodiments. The IC manufacturing system700is configured to manufacture an IC device780through a plurality of entities, such as a design subsystem710, a mask subsystem720, and a fabrication subsystem730. The entities in the IC manufacturing system700may be linked by a communication channel, e.g., a wired or wireless channel, and interact with one another through a network, e.g., an intranet or the internet. In an embodiment, the design subsystem710, the mask subsystem720and the fabrication subsystem730belong to a single entity, or are operated by independent parties.

The design subsystem710, which may be provided by a design house or a layout design provider, generates a design layout750, e.g., the design layout200, in a design phase for the IC devices780to be fabricated. The design subsystem710may perform the layout methods discussed in the present disclosure to generate the design layout750, e.g., the design layouts shown with reference to the figures of the present disclosure. In an embodiment, the design subsystem710operates a circuit design procedure to generate the design layout750. The design subsystem710may include further one or more steps, such as logic design, physical design, pre-layout simulation, placement and routing, timing analysis, parameter extraction, design rule check and post-layout simulation, to generate the design layout750. The design layout750may be converted from description texts into their visual equivalents to show a physical layout of the depicted patterns, such as the dimensions, shapes and locations thereof. In an embodiment, the design layout750can be expressed in a suitable file format such as GDSII, DFII, OASIS, or the like.

The mask subsystem720receives the design layout750from the design subsystem710and manufactures one or more masks (photomask, lithography masks or reticles) according to the design layout750. In an embodiment, the mask subsystem720includes a mask data preparation block722, a mask fabrication block724and a mask inspection block726. The mask data preparation block722modifies the design layout750so that a revised design layout760can allow a mask writer to transfer the design layout750to a writer-readable format.

The mask fabrication block724is configured to fabricate the one or more masks by preparing a substrate based on the design layout760provided by the mask data preparation block722. A mask substrate is exposed to a radiation beam based on the pattern of the design layout760in a writing operation, which may be followed by an etching operation to leave behind the patterns corresponding to the design layout760. In an embodiment, the mask fabrication block724includes a checking procedure to ensure that the layout data760complies with requirements of a mask writer and/or a mask manufacturer to generate the mask as desired. An electron-beam (e-beam), multiple e-beams, an ion beam, a laser beam or other suitable writer source may be used to transfer the patterns.

After the one or more masks are fabricated, the mask inspection block726inspects the fabricated masks to determine if any defects, such as full-height and non-full-height defects, exist in the fabricated mask. If any defects are detected, the mask may be cleaned or the design layout in the mask may be modified.

The fabrication subsystem730is an IC manufacturing entity that includes multiple manufacturing facilities or tools for the fabrication of a variety of the IC devices780. The fabrication subsystem730uses the mask fabricated by the mask subsystem720to fabricate a wafer770having a plurality of IC devices780thereon. The wafer770includes a semiconductor substrate and optionally various layers formed thereon. The operations provided by the manufacturing facilities or tools may include, but are not limited to, photolithography, deposition, sputtering, etching, diffusion, ion implantation and annealing. In some embodiments, test structures may be formed on the wafer770to generate test data indicative of the quality of the fabricated wafer770. In an embodiment, the fabrication subsystem730includes a wafer testing block732configured to ensure that the wafer770conforms to physical manufacturing specifications and mechanical and/or electrical performance specifications. After the wafer770passes the testing procedure performed by the wafer testing block732, the wafer770may be diced (or sliced) along the scribe line regions to form separate IC devices780. The dicing process can be accomplished by scribing and breaking, by mechanical sawing (e.g., with a dicing saw) or by laser cutting.

FIG.7Bis a schematic diagram of a system700for implementing or storing the design layouts discussed above, in accordance with some embodiments. The system700includes a processor701, a network interface703, an input and output (I/O) device705, a storage device707, a memory709, and a bus708. The bus708couples the network interface703, the I/O device705, the storage device707, the memory709and the processor701to each other.

The processor701is configured to execute program instructions that include a tool configured to generate the design layouts as described and illustrated with reference to figures of the present disclosure.

The network interface703is configured to access program instructions and data accessed by the program instructions stored remotely through a network (not shown).

The I/O device705includes an input device and an output device configured for enabling user interaction with the system700. In some embodiments, the input device includes, for example, a keyboard, a mouse, and other devices. Moreover, the output device includes, for example, a display, a printer, and other devices.

The storage device707is configured for storing the design layouts, one or more cell libraries including the configurations and settings of the standard cells as discussed previously, program instructions and data accessed by the program instructions. In some embodiments, the storage device707includes a non-transitory computer-readable storage medium, for example, a magnetic disk and an optical disk.

The memory709is configured to store program instructions to be executed by the processor701and data accessed by the program instructions. In some embodiments, the memory709includes any combination of a random access memory (RAM), some other volatile storage device, a read-only memory (ROM), and some other non-volatile storage device.

According to an embodiment, a method includes: receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and the first cell comprises a first active region having a first width in the first direction. The second cell has the cell height, and the second cell comprises a second active region having a second width in the first direction. The second width is different from the first width. The method further comprises manufacturing a semiconductor device according to the design layout.

According to an embodiment, a method comprises placing a first cell and a second cell in a first row of a design layout. The first cell comprises a first active region and a second active region. The first active region is separated from the second active region by a first distance in a first direction. The second cell comprises a third active region and a fourth active region. The third active region is separated from the fourth active region by a second distance in the first direction. The second distance is different from the first distance. The method further comprises manufacturing a semiconductor device according to the design layout.

According to an embodiment, a non-transitory computer readable storage medium comprises instructions which, when executed by a processor, cause the processor to perform a circuit simulation of an operation of a design layout comprising a first cell. The first cell has a cell height in a first direction, and the first cell comprises a plurality of first nanosheets having a first width in the first direction. In response to the circuit simulation failing to meet a design requirement, the processor is caused to replace the first cell in the design layout with a second cell to obtain a revised design layout. The second cell has the cell height, and the second cell comprises a plurality of second nanosheets having a second width in the first direction. The second width is greater than the first width. The processor is further caused to control manufacturing of a semiconductor device according to the revised design layout.