Phase locked loop with adaptive biasing

A phase locked loop including first and second charge pumps, a voltage buffer and a bias generator for adaptive biasing for improved performance. A voltage controlled oscillator, feedback circuit and phase detector portions may be provided to operate similar to conventional configurations. The first charge pump receives an adjust signal, such as from the phase detector, and selectively charges an intermediate node. The second charge pump receives the adjust signal and selectively charges a control node developing the control voltage for the VCO. A loop filter capacitor is referenced to the intermediate node. The voltage buffer, replacing the loop filter resistor, buffers the intermediate node and drives the control node. The bias generator converts the control voltage to a converter bias current based on the control voltage and adjusts the charge pump currents and a bias current of the voltage buffer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to phase locked loops, and more particularly to a phase locked loop with adaptive biasing for improved performance.

2. Description of the Related Art

A conventional phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The loop filter normally includes a resistor in series with a capacitor. The loop gain and damping ratio typically characterize PLL performance. For a conventional PLL, the charge pump current, the VCO gain and the loop filter resistance are fixed so that it has a fixed damping ratio and a fixed loop gain.

DETAILED DESCRIPTION

The loop gain of the phase locked loop (PLL) should be set as close as possible to its operating frequency in order to minimize jitter of the PLL. The loop gain, however, is affected by many factors, such as, for example, process technology factors, voltage and temperature variations, and noisy environments. A PLL should first be able to meet stability constraints under worst case conditions, so that the loop gain is normally set at the lowest operating frequency applicable for the worst case conditions, rather than being set for optimized performance. Conventional PLLs, therefore, have relatively narrow operating frequency range and poor jitter performance.

Existing solutions have proposed methods to make the damping ratio and the tracking bandwidth constant, where the tracking bandwidth is the ratio of loop bandwidth to PLL operating frequency. In one method, the loop filter resistor is implemented by an amplifier and set to be inversely proportional to the square root of charge pump current. Thus, the VCO frequency and the PLL loop bandwidth are also set to be proportional to the square root of charge pump current so that the ratio of loop bandwidth and PLL operating frequency is constant.

In the existing solutions, however, the bias current is proportional to the square of the loop control voltage, so that it consumes an appreciable amount of power particularly at higher frequencies. Moreover, the bias generator is provided within the PLL loop and provides current to the charge pump, the amplifier and the VCO. These existing solutions, therefore, cause the damping ratio and the tracking bandwidth to be dependent upon the VCO gain and effective output capacitance of each VCO stage. Since the effective capacitance is affected by parasitic capacitance, and since both the VCO gain and effective capacitance vary with many factors, such as process, voltage and temperature, it is difficult to control or otherwise predict these values accurately. Thus, the tracking bandwidth property is often deteriorated by these and other variations.

A PLL as described herein is configured with adaptive biasing to achieve a constant damping ratio and a constant tracking bandwidth. The PLL topology with adaptive biasing has a wider operating frequency range and improved jitter performance as compared to conventional configurations. Compared to other existing solutions, the PLL with adaptive biasing as described herein also exhibits lower power operation, broader operating frequency range and a tracking bandwidth which is process independent. In one embodiment, the PLL includes a bias generator (voltage to current converter), a second charge pump and a voltage buffer, where the voltage buffer effectively replaces the loop filter resistor. The bias generator senses the control voltage provided to the voltage controlled oscillator and provides bias values for the charge pumps and the voltage buffer. The disclosed PLL achieves tracking bandwidth in a manner which is not dependent on the gain or effective capacitance of the VCO so that tracking bandwidth is easier to predict and control, which in turn makes the PLL more accurate and robust. Since the bias generator does not provide current to the VCO, the VCO may be separately designed.

FIG. 1is a simplified block diagram of an electronic system100including a PLL103implemented according to one embodiment. The electronic system100includes a timing block102, a processor block104, and a memory block106coupled together by a system interface107. Although not shown, additional devices and systems and/or sub-systems may be included, such as a power system and an input/output (I/O) system and the like. The processor block104may include one or more processing devices or microprocessors or the like. The memory block106may be implemented according to any suitable memory type with one or more memory devices, such as random access memory (RAM) devices and/or read-only memory (ROM) devices or the like. The system interface107may be implemented in any suitable manner to enable communications between the timing block102, the processor block104and the memory block106, such as any type of bus structure, switch structure, switch fabric, network structure, etc. The timing block102incorporates the PLL103and may be used to generate one or more oscillating signals or clock signals or the like for use by other components or devices in the system.

The electronic system100may be implemented as a system-on-chip (SOC) or as an embedded processing system or the like. Alternatively, the electronic system100may be implemented in a discrete manner in which the timing block102, the processor block104and the memory block106may each be implemented on a separate integrated circuit (IC) or otherwise include any combination of one or more ICs or semiconductor chips or the like. The timing block102, for example, may be integrated on a separate IC incorporating the PLL103. The electronic system100may be configured for any type of application, such as communication systems, computer systems, sensing devices, etc., and for any one or more of consumer, industrial, commercial, computing, and/or automotive fields.

FIG. 2is a simplified block and schematic diagram of a conventional PLL200. The conventional PLL200includes a phase frequency detector (PFD)202, a charge pump (CP)204, a loop filter206, a voltage controlled oscillator (VCO)208, and a feedback circuit shown as a frequency divider210. The PFD202receives a reference frequency signal ωREFand a feedback frequency signal ωFBand outputs an up (UP) signal and a down (DN) signal. The UP and DN signals are provided to respective inputs of a charge pump204, which generated a control voltage VCTL filtered by the loop filter206. In the illustrated embodiment, the loop filter206includes a capacitor C and a resistor R coupled in series between VCTL and a reference node VREF, which may be any positive, negative or ground voltage level. VCTL is also provided to an input of the VCO204, having an output providing an output frequency signal ωVCOat an output of the PLL200. The output frequency signal ωVCOhas a frequency which is proportional to the voltage level of VCTL. The output frequency signal ωVCOis fed back to an input of the frequency divider210, in which the frequency divider210generates the feedback frequency signal ωFBfed back to an input of the PFD202. The frequency divider210divides the frequency of the output frequency signal ωVCOby a suitable frequency divider ratio N (e.g., ÷N) to control the frequency of the feedback frequency signal ωFB. N may be an integer, but is not limited an integer value.

The PFD202compares the phase and frequency of signals ωREFand ωFBand outputs the UP and DN signals to adjust phase and frequency of ωFBin an attempt to match that of ωREF.

The UP and DN signals are adjust signals in which a single adjust signal may be used in an alternative embodiment. The CP204generally operates to charge and discharge the capacitor C of the loop filter206based on the UP and DN signals to adjust VCTL accordingly. The VCO208correspondingly adjusts the output frequency ωVCObased on VCTL, which is divided down by the voltage divider210to develop the feedback frequency signal ωFB. In this manner, the PLL200generally operates to generate ωVCOsuch that ωVCO=N·ωREF.

The conventional PLL200has several deficiencies, including relatively narrow operating frequency range and poor jitter performance. If the PLL200is used as the PLL103of the electronic system100, then the overall performance of the electronic system100may be compromised. Jitter is an undesired deviation of the desired frequency of ωVCOwhich leads to a distorted output. The jitter is typically random an unpredictable which affects the overall accuracy of the signals using or otherwise based on the output frequency signal ωVCO. As an example, if the output of the PLL200is used as or otherwise used to generate a sampling clock signal for an analog to digital converter (ADC) (not shown), then the overall accuracy and performance of the ADC is compromised by the undesired jitter.

FIG. 3is a simplified block and schematic diagram of a PLL300implemented according to one embodiment. Similar components as those used in the conventional PLL200assume similar reference numerals. As shown, the PLL300includes the PFD202, the VCO208and the frequency divider210, which are coupled to operate in substantially the same manner as described for the PLL200. The CP204and the loop filter206, however, are replaced by a pair of charge pumps302and304(CP1and CP2), a loop filter306, and a bias generator308. The loop filter306is implemented by a capacitor C1and a voltage buffer305, in which the voltage buffer305generally replaces the loop filter resistor R. A capacitor C2is provided to reduce ripple voltage on VCTL.

The PFD202of the PLL300operates in substantially the same manner by comparing the phase and frequency of signals ωREFand ωFBand generating the UP and DN signals to adjust phase and frequency of ωFBin an attempt to match that of ωREF. The UP and DN signals are both provided to respective inputs of each of the charge pumps302and304. The output of the charge pump CP1develops an intermediate voltage VINT which is provided to one end of the capacitor C1and to the non-inverting or positive (+) input of the voltage buffer305. The other end of the capacitor C1is coupled to VREF. The inverting or negative (−) input of the voltage buffer305is coupled to its output which develops the control voltage VCTL. The output of the charge pump CP2is coupled to VCTL and thus to the negative input and output of the voltage buffer305. VCTL is provided to the input of the bias generator308and to the input of the VCO208. The VCO208operates in substantially the same manner and correspondingly adjusts the output frequency signal ωVCObased on VCTL, which is divided down by the voltage divider210to develop the feedback frequency signal ωFB. In this manner, the PLL300also generally operates to generate ωVCOsuch that ωVCO=N·ωREF.

The charge pumps302and304and the voltage buffer305of the PLL300each have at least one current control and/or bias input coupled to a corresponding bias output provided by the bias generator308. As shown, the bias generator308provides a P-type bias voltage VBP and an N-type bias voltage VBN. VBP and VBN are both provided to corresponding bias inputs of each of the charge pumps302and304. At least one of the bias voltages, such as VBN, is provided to a bias input of the voltage buffer305.

FIG. 4is a schematic diagram of one embodiment of each of the charge pumps CP1302and CP2304, which are each configured in substantially the same manner. Each of the charge pumps302and304includes a P-type device MP, an N-type device MN, and a pair of switches S1and S1coupled in series between source voltages VSRC and VREF (e.g., VSRC of VDD or VCC relative to VREF at ground or VSS or other suitable reference voltage level). The devices MP and MN may each be implemented as a metal-oxide semiconductor (MOS) transistor, such as using PMOS and NMOS transistors. The switches S1and S2are each figuratively shown as single-pole, single throw (SPST) switches each having switched terminals and a control terminal receiving either the UP signal or the DN signal. The switches S1and S2may be implemented using MOS transistors or the like. As shown, the source of MP is coupled to VSRC and its drain is coupled to one switched terminal of S1. The other switched terminal of S1is coupled to one switched terminal of S2at the node developing VINT. The other switched terminal of S2is coupled to the drain of MN, having its source coupled to VREF. The gate of MP receives the bias voltage VBP and the gate of MN receives the bias voltage VBN. Switch S1is controlled by the UP signal and switch S2is controlled by the DN signal.

MP and MN are shown developing a current ICP, which represents the charge/discharge current for both charge pumps CP1302and CP2304. In operation, when UP is asserted high and DN is asserted low, switch S1is closed while S2is opened so that current ICPflows to its output (e.g., CP1charges the capacitor C1). When DN is asserted high and UP is asserted low, switch S2is closed while S1is opened so that current ICPis drawn from its output (e.g., CP1discharges the capacitor C1).

FIG. 5is a schematic diagram of a bias generator500according to one embodiment which may be used as the bias generator308. The bias generator500includes 3 PMOS transistors MP1, MP2and MP3and 4 NMOS transistors MN1, MN2, MN3and MN4. The sources of MP1-MP3are coupled to the source voltage VSRC and their gates are coupled together at a common node developing the bias voltage VBP. MP1(diode-coupled) has its gate coupled to its drain which is further coupled to the drain of MN1. VCTL is provided to the gate of MN1, and the source of MN1is coupled to the drain of MN2. The drain of MP2is coupled to the drain and gate of MN3(diode-coupled) and also to the gate of MN2, and the drain of MP3is coupled to the drain and gate of MN4(diode-coupled) at a node which develops the bias voltage VBN. The sources of MN2-MN4are coupled to VREF.

FIG. 6is a schematic diagram of a bias generator600according to another, slightly simpler embodiment which may also be used as the bias generator308. The bias generator600includes 2 PMOS transistors MP1and MP2and3NMOS transistors MN1, MN2and MN3. The sources of MP1and MP2are coupled to VSRC and their gates are coupled together at a common node developing the bias voltage VBP. MP1(diode-coupled) has its gate coupled to its drain which is further coupled to the drain of MN1. VCTL is provided to the gates of MN1and MN2, and the source of MN1is coupled to the drain of MN2. The drain of MP2is coupled to the drain and gate of MN3(diode-coupled) at a node developing the bias voltage VBN. The sources of MN2and MN3are coupled to VREF.

For both bias generators500and600, MN2is configured to operate in its triode (or ohmic) region so that it functions as a resistance. The resistance value of MN2is controlled by a converter bias current ICONVshown as the drain current of MP2flowing to the drain/gate of MN3, where ICONVis controlled by the control voltage VCTL. The gate voltage of MP1and MP2(and MP3for bias generator500) develops the bias voltage VBP based on VCTL, and the drain/gate voltage of MN4(for bias generator500) or of MN3(for bias generator600) develops the bias voltage VBN. The bias voltages VBP and VBN are provided to the charge pumps CP1302and CP2304and at least one of the bias voltages (e.g., VBN) is provided to control the bias current of the voltage buffer305.

FIG. 7is a simplified schematic and block diagram of a voltage buffer700which may be used as the voltage buffer305according to one embodiment. The voltage buffer700is a simplified version in which it is understood that alternative (and more sophisticated) embodiments are contemplated. The voltage buffer700includes an output stage702and an input stage including NMOS transistors N1, N2and N3. The output stage702is coupled to VSRC and has an output coupled to the node developing the control voltage VCTL, where the output stage702may be implemented in any suitable manner. The output stage702is further coupled to the drains of N1and N2, which collectively form a differential input of the voltage buffer700. The sources of N1and N2are coupled together and to the drain of N2, having its source coupled to VREF. N1and N2form an input differential pair in which VINT is provided to the gate of N1and VCTL is provided to the gate of N2. The gate of N3receives VBN and develops a bias current IBUFfor the voltage buffer700.

The charge pump current ICPand the bias current IBUFof the voltage buffer305are each proportional to the converter bias current ICONV(e.g., ICP∝ICONVand IBUF∝ICONV, in which the symbol “∝” denotes a proportional relationship). The relative proportionality may be achieved by the relative size of the MOS devices implementing the respective functional blocks. ICONVis determined by VCTL and transconductance (voltage-current conversion) gain GMCONVof the bias generator308(such as implemented using 500 or 600 or similar configuration) according to the following equation 1:
ICONV=VCTL·GmCONV(1)
Using linear approximation, the loop gain KPLLof the PLL300is according to the following equation 2:

KPLL=ICP·RF·KVCO2⁢π·N(2)
where “RF” is the loop filter resistance, KVCOis the gain of the VCO208, and “N” is the frequency divider ratio. The voltage buffer305effectively replaces the loop resistor R (with resistance R) with RF, in which the voltage buffer305has a buffer transconductance referred to as GmBUF, and in which RFis inversely proportional to GmBUF. The bias voltage provided by the bias generator308generates the bias current IBUFof the voltage buffer305, where IBUFis related to RFand GmBUFaccording to the following equation 3:

RF∝1GmBUF∝1IBUF(3)
The frequency of the operating frequency signal ωREFof the PLL300may be determined according to the following equation 4:

ωREF=ωVCON=VCTL·KVCON(4)
Thus, the ratio of the loop gain KPLLand frequency of the operating frequency signal ωREF(tracking bandwidth) may be determined according to the following equation 5:

KPLLωREF=ICP2⁢π⁢RF·KVCO·1NVCTL·KVCON=RF2⁢π·ICPVCTL∝RF⁢ICONVVCTL∝RF·GmCONV∝ICONVIBUF->CONSTANT(5)
in which “CONSTANT” means that the ratio of the loop gain to operating frequency is constant. In this manner, tracking bandwidth is achieved by the PLL300.

In one embodiment, the charge pumps CP1302and CP2304, the voltage buffer305, the bias generator308and the VCO208are implemented using MOS devices. A value “k” is defined as a MOS device transconductance and VTHis defined as the threshold voltage of the MOS device. The bias current IVCOfor the VCO208is determined according to the following equation 6:

IVCO=12·k·(VCTL-VTH)2(6)
The output frequency signal ωVCOof the VCO208may be stated according to the following equation 7:

ωVCO=2·k·IVCOCB(7)
where CBis the total output capacitance of the VCO208. Using these relationships, the VCO gain KVCOof the VCO208may be derived as shown by the following equation 8:

KVCO=kCB(8)
Thus, the damping ratio ζ for the PLL300may be determined according to the following equation 9:

ζ=12·RF·ICP·KVCO·C⁢⁢12⁢π·N∝ICPIBUF->CONSTANT(9)
where C1is the capacitance of the loop capacitor C1of PLL300, and “CONSTANT” again means that the damping ratio is a relatively constant value. Since the damping ratio ζ is a constant value, the PLL300exhibits a stable and relatively fast response.

Since tracking bandwidth is achieved by the PLL300and the damping ratio is constant, the PLL300exhibits relatively low power, low jitter, and a broad operating frequency range. The tracking bandwidth is independent of the MOS process used to fabricate the PLL.

In summary, a bias generator is provided outside the PLL loop which receives the control voltage (VCTL) and which develops a converter current ICONV=VCTL·GmCONV, in which the voltage to current gain GmCONVis proportional to the square root of the bias current ICONV. The ratio of PLL loop gain and operating frequency is proportional to R·GmCONV. R is replaced with a voltage buffer having a gain GmBUF, in which the filter resistance RF=1/GmBUF. ICONVis used to develop IBUFin the voltage buffer (ICONV∝IBUF), in which GmBUFis proportional to the square root of IBUF. Thus, RFis inversely proportional to the bias current IBUFin the voltage buffer. Since GMCONVis proportional to the square root of bias current ICONV, since RFis inversely proportional to IBUF, and since IBUFis proportional to ICONV, then it follows that the ratio of PLL loop gain and operating frequency is constant and tracking bandwidth is obtained. Furthermore, the damping ratio of the PLL is constant.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, circuit implementations using NMOS transistors may be implemented using PMOS transistors and vice-versa, in which “N” and “P” generally denote different conductivity types. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.