Frequency calibration of radio frequency oscillators

A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored.

TECHNICAL FIELD

The present disclosure relates generally to integrated circuits, and more specifically to frequency calibration of radio frequency (RF) oscillators in the event of operating temperature or voltage drift.

BACKGROUND

Wireless communication devices with radio frequency (RF) integrated circuits (RFICs) may incorporate radio frequency voltage-controlled oscillators (RF VCOs) which are used as local oscillators to convert baseband communication channels to and from one of many RF channels.

RF channel tuning is accomplished by phase-frequency locking a RF VCO output frequency signal with a reference frequency, typically derived from a reference oscillator, in conjunction with a RF phase-locked loop (RF PLL). In wireless communication devices, the RF PLL is usually part of the same RFIC as the RF VCO. The RF PLL compares the RF VCO output frequency (utilizing a frequency divider) with the reference frequency. The RF PLL output provides a correction signal derived from the phase-frequency difference between the reference frequency and the frequency divided RF VCO output frequency.

The correction signal is, in turn, filtered (using a loop filter) to produce an analog control voltage for input to the RF VCO, and serves as a fine frequency tuning signal. When the RF VCO is not in phase or frequency lock with the reference frequency, the fine frequency tuning signal (the filtered correction signal) converges to a value (either increases or decreases in voltage) until the RF VCO output frequency is phase and frequency locked to the reference frequency. If the RF VCO cannot maintain phase and frequency lock, the wireless communication link performance, as measured at the RF channel, will not function properly or not at all.

Wireless communication devices operating across multiple radio frequency bands benefit from a RF VCO having wide frequency tuning range. Wide frequency tuning range is achieved with multiple tuning elements (comprised of fine and coarse tuning elements) in the RF VCO. Fine frequency tuning is provided by the fine tuning elements, while coarse frequency tuning is provided by the coarse tuning elements. During fine frequency tuning, the RF PLL and loop filter provide a fine frequency tuning signal to the fine tuning element within the RF VCO. Coarse frequency tuning is accomplished by switching in or out various discrete coarse tuning elements (setting a coarse frequency tuning code) to shift the RF VCO output frequency in large steps.

Unfortunately, the fine and coarse tuning element component values vary significantly with changes in operating temperature and operating voltage, leading to frequency drift in the RF VCO for a given fine frequency tuning signal voltage and coarse frequency tuning code. This frequency drift must be compensated for to ensure that the RFIC, along with RF VCO and RF PLL, properly tunes to the desired RF channel. In extreme cases, the frequency drift may exceed the fine frequency tuning signal voltage capability of the RF PLL and the RF VCO if the coarse frequency tuning code is held constant for a specific RF channel.

Coarse frequency tuning, in combination with fine frequency tuning, also allows the RFIC to better compensate for IC process variations. Coarse frequency tuning may be utilized as a method for reducing IC process variations affecting the RF VCO output frequency vs. coarse frequency tuning code (coarse frequency calibration).

Coarse frequency calibration may be done by frequency locking the RF PLL (with the fine frequency tuning signal) and RF VCO (with both fine frequency tuning signal and coarse frequency tuning code inputs) across multiple operating frequencies at circuit startup to compensate for process variations at a starting operating temperature. The final step of coarse frequency calibration is to store coarse frequency tuning codes across a range of desired RF VCO output frequencies.

Alternatively, coarse frequency calibration may be done only once, usually when the RFIC, including the RF VCO, is installed in a wireless communication device and is ready to be programmed and tested in a factory. In this case, the coarse frequency calibration is completed when the coarse frequency tuning codes are stored during factory testing over a range of desired RF VCO output frequencies at a nominal factory operating temperature. A third method may perform coarse frequency calibration at both circuit startup and in a factory environment.

As mentioned above, coarse frequency calibration may be done on multiple RF channels and/or operating RF bands (cellular, PCS, GPS, UMTS, GSM, etc) and multiple RF VCOs (transmit, receive, GPS, Bluetooth, etc). Coarse frequency tuning codes are generated during calibration and stored in the wireless communication device memory for later use as coarse frequency tuning during operation of the device with particular frequency bands or operating channels.

Conventional fine and coarse frequency tuning calibration techniques suffer in certain circumstances. In one instance, the RF VCO coarse frequency calibration is only performed at the beginning of the wireless communication device operation (on power-up), and at an initial temperature which changes after the coarse frequency calibration is complete.

One of the worst case conditions is to perform fine and coarse frequency tuning calibration at the coldest operating temperature (often below 0 C., freezing) and observe the RF VCO circuit behavior as the wireless communication device temperature rises from self-heating during normal operation. In the event that the coarse frequency tuning code is not changed for a given RF IC operating frequency, the fine frequency tuning signal (or voltage) is observed falling outside operating (voltage) limits. In this situation, the RF PLL will not be able to maintain frequency lock. Alternatively, the phase noise of the RF VCO may be significantly compromised as might occur when the fine frequency tuning signal approaches its operating (voltage) limit for a given coarse frequency tuning code. As explained above, coarse frequency tuning codes are matched to a particular RF operating channel during calibration and kept constant post-calibration. In either scenario, the wireless communication device may fail critical performance tests as it lacks proper calibration.

Given the limitations of RFICs utilizing wide-band RF VCOs with the requirement for coarse frequency tuning codes and fine frequency tuning signals, a more optimal design to deal with RF VCO frequency tuning variations for operating temperature changes is desirable.

SUMMARY

Techniques for correcting frequency tuning variations over operating temperature changes in a device including a RF VCO are provided.

A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored.

In one aspect, a RF VCO frequency is altered by adjusting the capacitance of a RF VCO LC resonator for frequency drift and changing output frequencies. In a further aspect, the capacitor within the LC resonator may be composed of multiple tuning elements in parallel to provide both coarse and fine frequency tuning of the RF VCO. Coarse frequency tuning is necessary to reduce the continuous fine frequency tuning range of the RF VCO and reduce the RF VCO phase noise verses frequency offset from the desired radio frequency. Fine frequency tuning is necessary to tune the RF VCO to the desired radio frequency. The fine frequency tuning signal is an analog voltage for continuous frequency tuning of the RF VCO and has limited voltage tuning range.

In another aspect, the coarse frequency tuning code is digital. There is a control register with multiple bits to select which capacitive (or inductive) elements in the RF VCO LC resonator are enabled or disabled. The switched capacitors (or inductors) may be connected in parallel with the fine frequency tuning element.

In a further aspect, a hardware circuit is added to the RFIC where the fine frequency tuning signal voltage for the RF VCO may be monitored continuously to determine if the fine frequency tuning signal voltage, provided to the RF VCO, is within specified voltage limits. If the fine frequency tuning signal voltage is too low or too high for the RF VCO to meet wireless communication device requirements or lock on the desired radio frequency, an interrupt signal may be asserted to the wireless communication device baseband modem (processor) that programs the radio frequency integrated circuit (RFIC), RF PLL, and coarse tuning control for the RF VCO. The processor or a hardware state machine on the RFIC initiates a coarse frequency calibration of the RF VCO, within the RFIC, to maintain frequency lock and optimal RF VCO phase noise performance.

Various other aspects and embodiments of the disclosure are described in further detail below.

The summary is neither intended nor should it be construed as being representative of the full extent and scope of the present disclosure, which these and additional aspects will become more readily apparent from the detailed description, particularly when taken together with the appended drawings.

DETAILED DESCRIPTION

A wireless communication device described therein may be used for various wireless communication cellular/PCS/IMT band systems such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA. In addition to cellular, PCS or IMT network standards, this wireless communication device may be used for local-area or personal-area network standards, WLAN, Bluetooth, & UWB. The wireless communication device may also be used for various mobile broadcast systems such as DVB-H, MediaFLO, etc.

FIG. 1is a block diagram of a wireless communication device10in accordance with the present embodiment as shown. Wireless communication device10includes radio frequency (RF) antenna12connected to RF Front-End14. RF Front-End14separates transmit and receive RF signal paths, and provides amplification and signal distribution. RF signals for transmit, TX_RF, and receive, RX_RF, are passed between transceiver20and RF Front-End14.

Transceiver20is configured to down-convert a RX_RF signal from RF to a signal for baseband I/Q demodulation by processor70, which may be a baseband modem or the like. Transceiver20is similarly configured to up-convert a signal from processor70, using baseband I/Q modulation, to a TX_RF signal. Signals to be up-converted and down-converted from/to baseband I/Q modulation are shown connected between transceiver20and processor70. Transceiver20utilizes a reference clock oscillator80. Reference clock oscillator80generates a reference clock frequency signal, REF_CLK, as will be shown in subsequentFIGS. 2 and 3.

Memory75stores processor programs and data and may be implemented as a single integrated circuit (IC), as shown.

Processor70is configured to demodulate incoming baseband receive I/Q signals, encode and modulates baseband transmit I/Q signals, and run applications from storage, such as memory75, to process data or send data and commands to enable various circuit blocks, all in a known manner.

In addition, processor70generates control signals to transceiver20through a data bus, serial bus, or a dedicated set of signals. Such control signals may include, for example, turning transceiver20on and off, changing RF channels, and performing or initiating within transceiver20RF VCO coarse frequency calibration.

Processor70is also configured to read the state of transceiver20, and at the same time also receive one or more interrupt signals (not shown) from transceiver20. Interrupt signals are used to initiate commands and algorithms between transceiver20and processor70.

It should be appreciated that the general operation of processor70, transceiver20, reference oscillator80, and memory75are well known and understood by those skilled in the art, and that various ways of implementing the associated functions are also well known, including providing or combining functions across fewer integrated circuits (ICs), or even within a single IC.

FIG. 2is a block diagram of a radio frequency integrated circuit (RFIC) transceiver (transceiver20) ofFIG. 1in accordance with the present embodiment as shown. Transceiver20includes transmit signal processing block22, receive signal processing block24, RF local oscillator (RF LO) generation block28, and control and status block26. Control and status block26provides digital control logic to/from processor70including an interrupt signal for RF VCO coarse frequency calibration. REF_CLK, from reference clock oscillator80, feeds into RF LO generation block28.

Transceiver20, while shown with just one transmit and receive signal processing block, may also exist with any combination of multiple receive blocks, multiple transmit blocks, or any number of possible transmit and receive signal processing block configurations. For example, transmit signal processor block22and receive signal processing block24are shown as separate functional blocks but may be combined to some extent in a half duplex radio device mode. Similarly, RF LO generation block28, while logically shown as a separate common block disposed between transmit signal processing block22and receive signal processing block24, other configurations are contemplated. Control and status block26can be similarly reconfigured without departing from the scope of the preferred embodiments described herein.

FIG. 3is a diagram of a radio frequency (RF) local oscillator (LO) generation block28ofFIG. 2in accordance with the present embodiment as shown. RF LO generation block28includes a RX LO generation block29and a TX LO generation block49. RX LO generation block29includes a RF VCO fine tuning block (RF PLL)31comprising a RF PLL and loop filter. RF PLL31compares REF_CLK, from reference clock oscillator80, to an output signal from RF VCO34, RX_VCO35, to lock RF VCO34to a desired frequency. RF PLL31output, Vt_PLL, is configured as an analog control signal for tuning the frequency of RF VCO34with an input signal, Vt_RX33a.

The output signal from RF VCO34, RX_VCO35, is further processed by LO generation block36. LO generation block36converts the RX_VCO33signal frequency to a desired receive RF channel frequency, RX_LO. LO generation block36may be implemented using frequency dividers, frequency mixers, switches, or a combination of all three types of elements to create a variety of frequency multiplication or division ratios between signals RX_VCO35and RX_LO. The RX_LO signal frequency is equal to the desired RX RF channel frequency in a particular operating frequency band (US cellular, US-PCS, IMT, GPS, etc). RX_LO signal is connected to the receive signal processing block24ofFIG. 2.

A RF VCO coarse tuning circuit32is utilized to coarse frequency tune RF VCO34at circuit startup and/or during RF channel changes, under processor70control, or a hardware state machine (within RF VCO coarse turning circuit32) control. If there are no starting values for coarse frequency tuning CT[0:N]33bfor a particular RX RF channel frequency, then RF VCO coarse tuning circuit32may perform a process called RF VCO calibration for one or more RX RF channel frequencies as will be shown in subsequentFIGS. 10-13.

Two digital to analog converters (DACs38aand39b) set Vmax39band Vmin39atune voltages based on digital inputs Vmax_RX_DIG37band Vmin_RX_DIG37afrom processor70via block26ofFIG. 2. Alternative designs may set the analog voltages Vmax39band Vmin39awith other circuit topologies. A Vt_RX comparator circuit41compares the Vt_RX33ainput of RF VCO34with Vmin39aand Vmax39b. If Vt_RX33ais above Vmax39bor below Vmin39a, then an interrupt logic signal Vt_H_OR_L_RX47is asserted (either Vt_H_RX OR Vt_L_RX is asserted at the input of OR gate46). Vt_H_OR_L_RX47(active high) initiates RF VCO coarse tuning circuit32operation (RF VCO calibration in this instance). Alternatively, the Vt_H_OR_L_RX47signal is sent to processor70via block26ofFIG. 9where processor70may control the RF VCO coarse tuning circuit32operation (coarse frequency tuning or RF VCO calibration).

An equivalent block for TX LO generation49is not shown for brevity. It should be readily understood that a similar block as shown for RX LO generation block29may be utilized for TX LO generation block48and as many LO generation blocks as required for multiple signal processing blocks of both RX and TX or RX only.

FIG. 4is a circuit diagram of a RF voltage-controlled oscillator (RF VCO34) ofFIG. 3in accordance with the present embodiment as shown. RF VCO34includes fine and coarse capacitive circuit elements to shift RF VCO34output frequency. Fine frequency tuning is implemented in LC circuit61with an inductor L and two varactors VCAP1and VCAP2. Frequency (and capacitance) fine tuning of RF VCO34is adjusted by analog control voltage, Vt_RX33a, across VCAP1and VCAP2. Coarse frequency turning block63includes fixed capacitor values Cmin as well as C[0] through C[N]. Other than Cmin, each fixed capacitor (C[0] . . . C[N]) is switched in or out individually or in combination by switches S[0] through S[N] with control signals CT[0] through CT[N]33b(from block32ofFIG. 3) to shift RF VCO34output frequency in coarse frequency steps (RX_VCO35).

The RF VCO34circuit is created when the frequency resonant structure composed of circuits61and63is placed in feedback around RF oscillating amplifier65(across the input and output of RF oscillator amplifier65). The output frequency (in radians/sec) of RF VCO34is equal to √(1/(L*Cvco)), where Cvco is a combination of fine and active coarse frequency tuning elements such that Cvco=Cmin+the active coarse capacitive circuit elements (C[0] . . . C[N])+Cvcap, where Cvcap is the total capacitance of VCAP1and VCAP2within LC circuit61. The output, RX_VCO35, of RF VCO34, is then fed back as an input to RF PLL31and to LO generation block36, as shown inFIG. 3.

The same circuit could apply across as many RF VCOs as required for multiple paths of both RX and TX or RX only (GPS or receiving broadcast signals). Alternatively one RF VCO may cover multiple modes and operating bands as long as simultaneous operation is not required. Other circuit topologies of distributed switchable frequency resonant elements (capacitors, inductors, transistors or combinations thereof) can discretely shift RF VCO output frequency, but are functionally equivalent.

FIG. 5is a circuit diagram of an alternate RF VCO34aofFIG. 3in accordance with the present embodiment as shown. RF VCO34aincludes fine capacitive and coarse inductive circuit elements to shift RF VCO34aoutput frequency (RX_VCO35). Fine frequency tuning is implemented in capacitive circuit61awith a capacitor C and two varactors VCAP1and VCAP2. Frequency (and capacitance) fine tuning of RF VCO34ais adjusted by analog control voltage, Vt_RX33a, across VCAP1and VCAP2. Coarse frequency turning block63aincludes fixed inductor values Lmax as well as switched fixed inductor values L[0] through L[N]. Other than Lmax, each fixed inductor (L[0] . . . L[N]) is switched in or out individually or in combination by switches S[0] through S[N] with control signals CT[0] through CT[N]33b(from block32ofFIG. 3) to shift RF VCO34aoutput frequency in coarse frequency steps (RX_VCO35).

The RF VCO34ais created when the frequency resonant structure composed of circuits61aand63ais placed in feedback around RF oscillating amplifier65(across the input and output of RF oscillator amplifier65). The output frequency (in radians/sec) of RF VCO34is equal to √(1/(Lvco*Cvco)), where Cvco is a combination of fine frequency tuning elements such that Cvco=C+Cvcap, where Cvcap is the total capacitance of VCAP1and VCAP2within capacitive circuit61aand where Lvco is the parallel combination of Lmax and active coarse frequency tuning elements (L[0] . . . L[N]). The output, RX_VCO35, of RF VCO34a, is then fed back as an input to RF PLL31and into LO generation block36, as shown inFIG. 3.

The same circuit could apply across as many RF VCOs as required for multiple paths of both RX and TX or RX only (GPS or receiving broadcast signals). Alternatively one RF VCO may cover multiple modes and operating bands as long as simultaneous operation is not required. Other circuit topologies of distributed switchable frequency resonant elements (capacitors, inductors, transistors or combinations thereof) can discretely shift RF VCO output frequency, but are functionally equivalent.

FIG. 6is a graph of RF VCO34fine frequency output vs. tuning voltage (Vt_RX33a) ofFIG. 3in accordance with the present embodiment as shown. The graph includes RF VCO34output frequency verses a fine frequency tuning voltage, Vt_RX33a, for a fixed coarse tuning code33b, CT=0, and at 25 degrees C. operating temperature. CT=0 corresponds to all the switch elements in the coarse tuning circuit63open. In this instance, the tuning range of RF VCO34is controlled by fine frequency tuning voltage, Vt_RX33a, between 0 and 0.7 volts DC. The equivalent circuit may be applied to different RX or TX frequency ranges by shifting the inductor or capacitor element values within RF VCO34.

FIG. 7is a graph of RF VCO34coarse and fine frequency output vs. tuning voltage (Vt_RX33a) and coarse tuning code33b(CT) ofFIG. 3in accordance with the present embodiment as shown. The graph includes RF VCO34output frequency output frequency verses the fine frequency tuning voltage, Vt_RX33a, for multiple coarse tuning codes33b, CT=0, 1, 2, 3, 4, and at 25 degrees C. operating temperature. The coarse frequency tuning codes33bcorrespond to incrementing the least-significant bits (LSBs) of CT[0:N] from 0 to 4 and opening and closing the corresponding switch elements in the coarse frequency tuning circuit63. The fine frequency tuning range of RF VCO34is controlled by fine frequency tuning in each instance of CT (0 to 4), Vt_RX33a, between 0 and 0.7 volts DC. With both coarse and fine frequency tuning, the total frequency tuning range of RF VCO34is greater than previously shown inFIG. 6where only fine frequency tuning was utilized. The equivalent circuit may be applied to different RX or TX frequency ranges by shifting the center frequency of the LC circuit composed of elements61and63of RF VCO34using the switched elements or a design change in the total capacitance or inductance or both.

FIG. 8is a graph of RF VCO34coarse and fine frequency output vs. tuning voltage (Vt_RX33a), coarse tuning code33b(CT), and temperature drift ofFIG. 3in accordance with the present embodiment as shown. The graph includes RF VCO34output frequency verses the fine frequency tuning voltage, Vt_RX33a, for two coarse tuning codes33b, CT=0 and 1, and over the RF VCO34full operating temperature range. In this instance, the operating temperature range shifts the output frequency of RF VCO34by ±5% relative to 25 degrees C. The tuning range of RF VCO34is controlled by fine tuning in each instance of CT (CT=0 and 1), Vt_RX33a, between 0 and 0.7 volts DC. If the desired output frequency is 2.6 GHz, the CT value must change from 0 to 1 for Vmin (0.1V)<Vt_RX<Vmax (0.6V) to remain valid over the operating temperature range. If the starting value of CT is 0 with a tuning voltage of V1(0.22V) and the temperature shift is from −5 to +5%, the RF VCO34will not maintain frequency lock until CT is changed from 0 to 1. At the point that CT is changed to 1, the new tuning voltage is V2(0.46V, within specified limits of Vmin and Vmax). The equivalent circuit may be applied to different RX or TX frequency ranges by starting with a different tuning frequency range for Vt_RX33aand coarse tuning codes33b. Performing the RF VCO calibration process with RF VCO coarse tuning circuit32will change the coarse tuning code (CT) from 0 to 1 in this instance.

FIG. 9is a block diagram of a transceiver control & status circuit26ofFIG. 2in accordance with the present embodiment as shown. Transceiver control and status circuit26includes an interface49to processor70(ofFIG. 1) for addressing and data encoding/decoding, a write register bank51, a read register bank53, and a OR gate55for combining multiple transceiver interrupt signals into one interrupt signal59. Transceiver control and status circuit26also includes a set-reset (SR) latch57which is set if triggered by OR gate55. The SR latch57is cleared (reset) by processor70prior to initiating RF VCO34calibration or in response to any interrupt generated by transceiver20by other circuits (not shown).

FIG. 10is an operational flow diagram of the process for performing fine frequency tuning of a RF VCO34, monitoring the fine frequency tuning signal voltage (Vt_RX33a), and coarse frequency tuning code33b(CT) during calibration under hardware control ofFIGS. 1,2,3,8and9in accordance with a preferred embodiment.

Operation flow diagram100starts when processor70sends commands and data to transceiver20for RF PLL31, RF VCO coarse tuning block32, and Vmin_DIG37aand Vmax_DIG37bto DACs38aand38b(block101). Transceiver20starts RF VCO coarse tuning block32to select a coarse tuning code33bfrom among multiple coarse tuning codes of RF VCO34for one or more desired RF channels (block103). Processor70reads transceiver20coarse tuning codes for one or more desired RF channels and stores the results in memory75(RF VCO34calibration completed and coarse tuning codes stored) (block105). Processor70, memory75, and transceiver20sets coarse tuning code33bfor desired RF channel and starts RF PLL31fine frequency tuning to determine the tuning voltage, Vt_RX33a, for the desired RF channel (block107). After the RF PLL31has locked on the desired RF channel (block109), RX LO generation block29monitors RF VCO34fine frequency tuning voltage, Vt_RX33a, with voltage comparators (42,44) (block111). If the voltage comparators (42and44) detect the condition where Vt_RX33ais outside of either Vmin39aor Vmax39b(block113), Vt_H_OR_L_RX signal is asserted (OR gate46and signal47) (block115restarts process100at block103). At any time, the operation flow diagram100may restart if the current RF channel is changed (back to block101).

FIG. 11is an operational flow diagram of the process for performing fine frequency tuning of a RF VCO34, monitoring the fine frequency tuning signal voltage (Vt_RX33a), and coarse frequency tuning code33b(CT) during calibration under processor control ofFIGS. 1,2,3,8and9in accordance with a preferred embodiment.

Operation flow diagram200starts when processor70sends commands and data to transceiver20for RF PLL31, RF VCO coarse tuning block32, and Vmin_DIG37aand Vmax_DIG37bto DACs38aand38b(block201). Transceiver20starts RF VCO coarse tuning block32to select a coarse tuning code33bfrom among multiple coarse tuning codes of RF VCO34for one or more desired RF channels (block203). Processor70reads transceiver20coarse tuning codes for one or more desired RF channels and stores the results in memory75(RF VCO34calibration completed and coarse tuning codes stored) (block205). Processor70, memory75, and transceiver20sets coarse tuning code33bfor desired RF channel and starts RF PLL31fine frequency tuning to determine the tuning voltage, Vt_RX33a, for the desired RF channel (block207). After the RF PLL31has locked on the desired RF channel (block209), RX LO generation block29monitors RF VCO34fine frequency tuning voltage, Vt_RX33a, with voltage comparators (42,44) (block211). If the voltage comparators (42and44) detect the condition where Vt_RX33ais outside of either Vmin39aor Vmax39b(block213), interrupt asserted (46,47,55,57) to processor70(block215). Processor70sends command to start RF VCO coarse tuning block32(block217restarts process200at block203). At any time, the operation flow diagram200may restart if the current RF channel is changed (back to block201).

FIG. 12is a plot of RF VCO34fine frequency tuning signal voltage (Vt_RX33a) during an initial RF PLL31locking procedure ofFIG. 3in accordance with the present embodiment as shown. The plot is an example timeline of startup behavior for several relevant signals for the RX LO generation block29and includes RF VCO34fine tuning input, Vt_RX33a, RF PLL31lock signal (RX_PLL_LOCK), and the corresponding generated interrupt signal (Vt_H_OR_L_RX47) from OR gate46during initial coarse frequency tuning, fine frequency tuning, RF PLL31settling (Vt_PLL), and RF PLL31locked conditions. Assuming all the circuit block supply voltages and RF PLL31settings have been preset to the desired RF channel (Time=0), RF VCO coarse tuning circuit32starts. During RF VCO34coarse frequency calibration (between Time=0 and Time<T1), the tuning voltage from RF PLL31, Vt_PLL, is disconnected (utilizing Vref_CT control signal from RF VCO coarse tuning block32) from RF VCO34fine frequency tuning input (Vt_RX33a). During calibration, reference voltage (Vref) is connected (Vt_RX33a=Vref during coarse frequency calibration) to RF VCO34fine frequency tuning input. Vref is equal to (Vmax+Vmin)/2 in this example, but other voltage settings may be used. RF VCO34calibration process with RF PLL31and RF VCO coarse tuning circuit32is described in further detail below in accordance with the present embodiment as shown.

Within RF VCO coarse tuning circuit32, all CT[0:N] bits (coarse tuning code33bbits most significant bit, MSB, to least significant bit, LSB) are toggled successively until RF VCO34converges to the frequency setting closest to the desired RF channel frequency. After RF VCO coarse frequency calibration is completed (coarse tuning code33bMSB through LSB set optimally by Time=T1) by RF VCO coarse tuning circuit32, fine frequency tuning voltage from RF PLL31, Vt_PLL, is reconnected to RF VCO34input tune line (Vt_RX33a=Vt_PLL) and fine frequency tuning correction is completed (by Time=T2). From this point in time, RF PLL31output voltage Vt_PLL, and RF VCO34converge (RX_PLL_LOCK indicates lock condition) to the desired frequency within a short time interval (by Time=T3). Subsequent to RF PLL31indicating lock condition (Time>T3), the fine frequency tuning voltage, Vt_RX33a, is monitored for voltage compliance between Vmin39aand Vmax39bvalues.

FIG. 13is a plot of RF VCO34fine frequency tuning signal voltage (Vt_RX33a), and RF PLL lock signal, while monitoring the corresponding interrupt signal47before, during and after coarse frequency calibration ofFIG. 3in accordance with the present embodiment as shown. The plot is an example timeline of RF VCO34, Vt_RX33a, RF PLL31lock (RX_PLL_LOCK signal), and RF VCO34, Vt_RX33a, generated interrupt signal47(at the output of OR gate46) when Vt_RX33afalls below Vmin39a. In this example, the interrupt signal is asserted (Time=T4) and RF VCO coarse tuning circuit32is restarted (Time=T5). The prior figure shows what happens after RF VCO coarse tuning circuit32has completed calibration (Time=T1inFIG. 12).

Those of skill in the art would understand that signals may be represented using any of a variety of different techniques. For example, data, instructions, signals that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative radio frequency or analog circuit blocks described in connection with the disclosure herein may be implemented in a variety of different circuit topologies, on one or more integrated circuits, separate from or in combination with logic circuits and systems while performing the same functions described in the present disclosure.