Semiconductor package including dummy board and method of fabricating the same

Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip, and a plurality of conductive balls, e.g., solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip. The adhesive material is applied on an adhesion surface of the dummy board adhered to a joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings. Cheap underfill materials can be selectively used, and a process time for reflow and curing of the adhesive material can be greatly reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2006-55060, filed on Jun. 19, 2006, the entire contents of which are herein incorporated by reference.

BACKGROUND

1. Technical Field

The present invention relates to a package of a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor package and a method of fabricating the same.

2. Background of the Related Art

As semiconductor devices have been miniaturized, packages with a size close to a chip size have been developed, such as a flip chip package and a chip size package. The chip size package generally has a lower reliability when compared with a conventional leadframe style package. In particular, since a stress is applied to a coupling section of the chip size package due to the thermal expansion coefficient difference between the package and a circuit board, the chip size package may be separated from the circuit board during manufacturing, testing, or operation.

Recently, a technique for applying an underfill material on a joint surface of a semiconductor chip including solder balls has been introduced in order to improve the reliability of the chip size package. The underfill material relieves a stress applied to the solder balls to prevent the solder balls from coming off the semiconductor chip when the chip size package is coupled to the circuit board or during a thermal cycling test.

FIG. 1is a cross-sectional view illustrating a conventional chip size package and a method of coupling the chip size package to a circuit board.

Referring toFIG. 1, a chip size package10includes a plurality of solder balls14formed on a joint surface of a semiconductor chip12. The solder balls14are used as I/O terminals of the semiconductor chip12, and the solder balls14can be formed by various methods as is known in the art.

A part of the solder ball14is bonded to the semiconductor chip12, and a curved portion adjacent to the bonding portion has a weak resistance to stress. In order to relieve stress applied to the solder balls14and fix the solder balls14to the semiconductor chip12, an underfill material16is applied on the bonding surface of the semiconductor chip12. The underfill material16is applied between the solder balls14, and then contacts curved surfaces of the solder balls14by curing and reflow processes.

Generally, the chip size package10is directly coupled to a circuit board50such as a printed circuit board (PCB). As illustrated, a solder mask54is formed on a coupling surface of the circuit board50to provide a region for coupling of the solder balls14. The solder mask54includes a plurality of openings58corresponding to the solder balls14to prevent the solder balls14from melting and contacting other portions of the circuit board50in addition to the pads56. The solder balls14are coupled to the pads56formed inside the openings in the circuit board50.

FIG. 2is a cross-sectional view illustrating a conventional chip size package coupled to a circuit board.

Referring toFIG. 2, as the soldering process is performed at a predetermined temperature, the solder balls14are coupled to the corresponding pads56, respectively. When the chip size package10is heated to a reflow temperature of the solder balls14or higher, it is electrically and mechanically coupled to the circuit board50. Here, the underfill material16is reflowed and pushed into the openings58.

As illustrated inFIG. 2, in the conventional chip size package, the underfill material16is coupled to the solder mask54to form a stress relief layer, and is cured through an additional heating cycle to improve bonding strength. The underfill material16relieves stress applied to the solder balls14to prevent the solder balls14from coming off the circuit board50due to the thermal expansion coefficient difference during the heating cycle.

However, the underfill material of the conventional chip size package has fluidity, and may be reflowed or deformed during the repeated heating cycles. Therefore, the thermal expansion coefficient difference may lead to decreases in the stress relieving effect on the solder balls.

Also, since the semiconductor chip is small and thin, stress and cracks due to an external impact are quickly transmitted. Therefore, the chip size package may be separated from the circuit board in an edge portion that is the weakest portion of the semiconductor chip.

The present invention addresses these and other disadvantages of the conventional art.

SUMMARY

The present invention provides a semiconductor package such as a chip size package in which a stress applied to solder balls can be greatly relieved and a method of fabricating the chip size package. The present invention also provides a semiconductor package where damage of a semiconductor chip can be reduced during a treatment for the chip size package and a method of fabricating the same.

Embodiments of the present invention provide semiconductor packages such as chip size packages including a dummy board for relieving a stress. The chip size package includes a semiconductor chip, and a plurality of solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip.

DETAILED DESCRIPTION

Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. It will also be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a portion is referred to as being adjacent to another portion, it can directly contact the other portion, or intervening portions may also be present. Like reference numerals refer to like elements throughout.

FIG. 3Ais a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention.

Referring toFIG. 3A, a semiconductor package, e.g., a chip size package according to a first embodiment of the present invention includes a semiconductor chip100and a plurality of conductive balls, e.g., solder balls102formed on the semiconductor chip100. The solder balls102may be formed using one or more metals such as lead and tin. For example, a metal layer may be formed on a joint surface of the semiconductor chip100and patterned to form a metal pattern, and then the metal pattern may be melted to form the solder balls102, or solder paste may be printed on a pad of the semiconductor chip100and heated to form the solder balls102. Alternatively, the solder balls102may be disposed on a joint surface of the semiconductor chip100and then heated to be joined to the semiconductor chip100.

The solder balls102may be formed on the joint surface of the semiconductor chip100as illustrated inFIG. 4, but the arrangement of the solder balls102should not be limited thereto, and may be variously designed depending on the semiconductor chip being manufactured.

A dummy board110is bonded to the semiconductor chip100. The dummy board110may be formed of an insulating material such as glass fiber and ceramic. The dummy board110may be preferably formed of a material with a small difference in the thermal expansion coefficient from the semiconductor chip100to relieve a stress applied to the solder balls102during thermal deformation.

As illustrated inFIG. 5, the dummy board110includes a plurality of openings112corresponding to the solder balls102. The solder balls102are aligned with the openings112and protrude from the dummy board110. The dummy board110supports side portions of the solder balls102to relieve a stress applied to the solder balls102when heat-treating the chip size package and coupling the chip size package to a circuit board.

An adhesive material114is interposed between the dummy board110and the semiconductor chip100to adhere the dummy board110to the semiconductor chip100. The adhesive material114is pushed into gaps adjacent to curved portions of the solder balls102to support bottom portions of the solder balls102contacting the semiconductor chip100and fill gaps120between the dummy board110and the solder balls102.

The adhesive material114may have fluidity and may be cured through a heat treatment process. The adhesive material114may be an inorganic material or an organic material that has fluidity. The adhesive material114may adhere the dummy board110to the semiconductor chip100through curing, and may have weak fluidity at a predetermined temperature to relieve a stress due to the thermal expansion coefficient difference between the semiconductor chip100and a circuit board.

The adhesive material114may be selected from conventional underfill materials. However, since the dummy board110supports the solder balls102, a smaller amount of underfill material is required when compared with conventional packages. Therefore, the process time may be reduced when compared with the conventional underfill material.

The chip size package according to the present invention may be coupled to various types of circuit boards, not limited to the circuit board including a solder mask154. The chip size package may be also coupled to a lead frame of a flip chip package as well as the circuit board.

FIG. 3Bis a cross-sectional view illustrating a semiconductor package, e.g., chip size package according to a second embodiment of the present invention.

Referring toFIG. 3B, the chip size package according to the second embodiment has a structure similar to that of the chip size package according to the first embodiment. That is, a plurality of solder balls102are formed on a semiconductor chip100and a dummy board110is adhered to the semiconductor chip100using an adhesive material114.

In the second embodiment, the dummy board110is wider than the semiconductor chip100in both width and length directions. Therefore, each edge of the dummy board110has an overhang portion OA with respect to the semiconductor chip100.

Side and upper surfaces of the semiconductor chip100are covered with a molding material130such that the semiconductor chip100is encapsulated. The molding material130sequentially covers the upper and side surfaces of the semiconductor chip100and the overhang portion OA of the dummy board110.

The molding material130protects the chip size package from an external impact and crack generation during heat treatment, and also isolates the semiconductor chip100from moisture and pollutants from the external environment. In addition, the molding material130may affix a heat radiating structure when the heat radiating structure is disposed on a rear surface of the semiconductor chip100.

FIGS. 6 and 7are cross-sectional views for illustrating a method of fabricating a semiconductor package, e.g., a chip size package according to an embodiment of the present invention.

Referring toFIG. 6, a semiconductor chip100is fabricated, and then a plurality of solder balls102is formed on the semiconductor chip100. The solder balls102may be formed of a single metal or a metal alloy, and the solder balls102may be formed by various methods as is known in the art. The solder balls102are arranged on a joint surface of the semiconductor chip100.

A dummy board110is formed independently of the fabrication of the semiconductor chin100. The dummy board110includes openings112corresponding to positions of the solder balls102of the semiconductor chip100. The openings112may be formed by mechanically or optically punching the dummy board110.

The dummy board110may be formed of an insulating material such as resin, glass fiber, and ceramic, and may be preferably formed of a material with a small difference in the thermal expansion coefficient from the semiconductor chip100to relieve a stress applied to the solder balls102during thermal deformation.

An adhesive material114is applied to an adhesion surface of the dummy board110. The adhesive material114may be an inorganic material or an organic material having fluidity. The adhesive material114may be reflowed and cured through the heat treatment to adhere the dummy board110to the semiconductor chip100.

The adhesive material114is formed in a liquid, paste, gel, or slurry type having viscosity, and thus may be applied on the dummy board110. The adhesive material114may be dried or cured to a predetermined degree after it is applied on the dummy board110. Alternatively, the adhesive material114may be a thermoplastic sheet, and may be reflowed and cured by the heat treatment.

Referring toFIG. 7, the dummy board110is adhered to a joint surface of the semiconductor chip100after the adhesive material114is applied on the dummy board110. Here, the solder balls102respectively correspond to the openings112of the dummy board110, and the dummy board110is adhered to a surface of the semiconductor chip100where the solder balls102are not formed.

The dummy board110is adhered to the semiconductor chip100while supporting side portions of the solder balls102. The adhesive material114is pushed by the dummy board110and is forced into gaps between the semiconductor chip100and curved portions of the solder balls102.

When the adhesive material114has fluidity, it may be forced into the gaps between the semiconductor chip100and curved portions of the solder balls102and gaps between the solder balls102and the dummy board110by a pressing force. Alternatively, when the adhesive material114is formed of a sheet having no fluidity, it may be reflowed by the heat treatment and forced into the gaps between the semiconductor chip100and the curved portions of the solder balls102and the gaps between the solder balls102and the dummy board110(120, refer toFIG. 3A). In the present invention, the adhesive material114may be heat-treated during a relatively small heating time, when compared with the conventional underfill material.

FIGS. 8A and 8Bare cross-sectional views of a semiconductor package, e.g., a chip size package coupled to a circuit board according to first and second embodiments of the present invention, respectively.

Referring toFIG. 8A, the chip size package according to a first embodiment is coupled to the circuit board. The circuit board may be chosen from a printed circuit board (PCB), a flame-retardant glass fiber board, an organic circuit board, a mother board, a ceramic substrate, a hybrid circuit board, an integrated circuit package, a flexible circuit board, and a frame board of a flip chip package.

Generally, the solder mask154is formed on a coupling surface of the circuit board to provide a region for coupling of the circuit board and the solder balls102. The solder mask154prevents the solder balls102from contacting other portions of the circuit board when the chip size package is heated. The solder mask154includes openings corresponding to the solder balls102. Pads152are formed in the respective openings and the solder balls102are bonded to the pads152.

The solder balls102melt at a reflow temperature and are thereby bonded to the pads152. Here, the adhesive material114may be partially reflowed and then cured, or may be cured without reflowing.

Referring toFIG. 8B, in the chip size package according to the second embodiment, the molding material130may encapsulate the semiconductor chip100, and prevent damage of the semiconductor chip100while coupling the chip size package to the circuit board or preparing the coupling thereof. Also, the molding material130may absorb an impact applied to the semiconductor chip100even after the coupling to prevent the crack generation and additionally relieve a stress applied to the solder balls102.

Referring toFIGS. 8A and 8B, an underfill material116may be disposed around the portions of the solder balls102that are connected to the pads152. The underfill material116may relieve a stress applied to bonding portions between the solder balls102and the pads152to prevent the solder balls102from coming off the pads152.

FIGS. 9A and 9Bare cross-sectional views illustrating modified examples of chip size packages according to first and second embodiments of the present invention, respectively.

Referring toFIGS. 9A and 9B, an underfill material116is applied on the dummy board114of the chip size packages according to the first and second embodiments. The underfill material116may be formed in a liquid, paste, gel, or slurry type having viscosity like the adhesive material114, and may be applied or suspended using a screen. Also, the underfill material116may be partially cured after applying. The underfill material116may be used in a relatively small quantity when compared with the conventional underfill material.

When the chip size package is coupled to the circuit board, as illustrated inFIGS. 10A and 10B, the underfill material116may be forced into gaps between the solder mask154and the solder balls102to fill the openings of the solder mask154. The underfill material116filled in the openings of the solder mask154may relieve a stress applied to bonding portions between the solder balls102and the pads152to prevent the solder balls102from coming off the pads152.

The chip size package according to the current embodiment may prevent the solder balls102from coming off the semiconductor chip100due to stress and also prevent the solder balls102from coming off the pads152of the circuit board. Therefore, a high reliability may be maintained during repetitive heating cycles.

The present invention should not be limited to the chip size package, and may be applied to various applications for relieving a stress applied to a solder ball or a solder bump formed on a semiconductor chip. Also, the present invention may be variously applied to fields for relieving a stress applied to a solder ball because of physical factors such as an external impact and thermal expansion coefficient difference.

As described above, the present invention can relieve a stress applied to conductive balls, e.g., solder balls by using a dummy board, and can support a coupling portion between the solder balls and a semiconductor chip using a smaller amount of material when compared with a conventional underfill material. Therefore, a material cheaper than the conventional underfill material can be selectively used, and a process time of reflowing and curing an adhesive material can be greatly reduced. In particular, in the case of mounting both surfaces where a plurality of chip size packages are coupled to a circuit board with time intervals in between each, the number of times of reflow and curing increases, and thus the total process time can be reduced even more by using the present invention.

Also, according to some embodiments of the present invention, since the semiconductor chip can be encapsulated by using the dummy board, the semiconductor chip can be protected from an external impact and crack generation during treatment of the chip size package.

Furthermore, a stress applied to a bonding portion between the solder balls and the circuit board can be relieved by additionally applying an underfill material on the dummy board.

Embodiments of the present invention provide semiconductor packages including a dummy board for relieving a stress. The semiconductor package includes a semiconductor chip, and a plurality of solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip.

In some embodiments, the dummy board is larger than the semiconductor chip in width and length directions, and each edge of the dummy board adhered to the semiconductor chip has an overhang portion extending outwardly from the semiconductor chip in each direction. A molding material may cover side and upper surfaces of the semiconductor chip to encapsulate the semiconductor chip. The molding material covers the overhang portion and the side and upper surfaces of the semiconductor chip.

Embodiments of the present invention also provide methods of fabricating semiconductor packages including a dummy board. The method includes forming a semiconductor chip and forming a plurality of solder balls on a joint surface of the semiconductor chip. A dummy board is formed which includes a plurality of openings corresponding to the solder balls. An adhesive material is applied on an adhesion surface of the dummy board adhered to the joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings.

In other embodiments, the dummy board is larger than the semiconductor chip in width and length directions, and thus each edge of the dummy board adhered to the semiconductor chip has an overhang portion extending outwardly from the semiconductor chip in each direction. A molding material may encapsulate the semiconductor chip. The molding material may be applied so as to sequentially cover upper and side surfaces of the semiconductor chip and the overhang portion of the dummy board and may be cured.