ENHANCED PPM FREQUENCY OFFSET DETECTOR

Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

BACKGROUND

The present invention relates to digital processing systems, and more specifically, to methods and circuitry for implementing an enhanced PPM (parts per million) frequency offset detector to detect a frequency offset between two clock signals.

PPM frequency offset detectors, also called PPM Watchdogs, are used to detect clock errors or clock signal drift in clock sources of computer processing units, integrated circuits, or the like. New techniques, systems, and circuitry for implementing an enhanced PPM frequency offset detector are needed to detect a frequency offset between two clock signals, for example, to eliminate the requirement of a third reference clock signal, reduce power requirements, and circuitry requirements to effectively and efficiently detect an PPM frequency offset between two clock signals.

SUMMARY

Embodiments of the present disclosure provide methods, systems, and circuitry for implementing an enhanced PPM frequency offset detector to detect a frequency offset between two clock signals.

According to one embodiment of the present disclosure, a frequency offset detector comprises: a first source counter receiving and counting a first clock signal; a second source counter receiving and counting a second clock signal; an offset counter clock controller coupled to the first source counter, the second source counter, and the offset counter clock controller configured to receive the first clock signal, the second clock signal, a count output of the first source counter, and a count output of second source counter; a PPM (parts per million) frequency offset counter coupled to the offset counter clock controller to detect a frequency offset between the first clock signal and the second clock signal, where the offset counter clock controller is configured to: detect a fastest clock signal of the first clock signal and the second clock signal; apply the fastest clock signal to the PPM frequency offset counter; enable counting the fastest clock signal, by the PPM frequency offset counter, based on the count output of the fastest clock signal; and disable counting the fastest clock signal, by the PPM frequency offset counter, based on the count output of the slowest clock signal.

According to one embodiment of the present disclosure, a method comprises receiving, by a first source counter, a first clock signal from a first clock signal source; receiving, by a second source counter, a second clock signal from a second clock signal source; an offset counter clock controller; transmitting by the first source counter, a first count output of the first source counter, to an offset counter clock controller; transmitting by the second source counter, a second count output of the second source counter, to the offset counter clock controller; receiving, by the offset counter clock controller, the first clock signal and the second clock signal; and detecting by the offset counter clock controller, a fastest clock signal of the first clock signal and the second clock signal, to apply to a PPM (parts per million) frequency offset counter, and where the offset counter clock controller enables counting the fastest clock signal, by the PPM frequency offset counter, based on a count value of the fastest clock signal, and disables the counting the fastest clock signal based on the count output of the slowest clock signal, to detect a frequency offset between the first clock signal and the second clock signal, and where the PPM frequency offset counter generates an error signal output based on counting the fastest clock signal.

DETAILED DESCRIPTION

Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

In one embodiment, two asynchronous clock signals CLK_A, CLK_B (e.g., from a first clock source A, and a second clock source B) are applied to respective M bit counters A, B (e.g., 21-bit counter or any M bit counter A, B). Each M bit counter A, B is initialized to an zero (0) state before being enabled to start counting the respective asynchronous clock signals CLK_A, CLK_B. With a frequency offset between the two asynchronous clock signals CLK_A, CLK_B, one of the respective bits BIT_N_A or BIT_N_B (digital count signals) goes high prior to the other BIT_N_B or BIT_N_A, if CLK_A or CLK_B is faster than CLK_B or CLK_A. The digital count signals BIT_N_A and BIT_N_B feed a downstream offset counter clock controller, which also receives the asynchronous clock signals CLK_A, CLK_B. The offset counter clock controller detects a fastest clock signal of the first clock signal CLK_A and the second clock signal CLK_B and applies the fastest clock signal to an input of a PPM frequency offset counter. The offset counter clock controller enables counting by the PPM frequency offset counter synchronously with the highest frequency clock or fastest clock of the first clock source A and the second clock source B. The offset counter clock controller disables counting by the PPM frequency offset counter synchronously with the lowest frequency clock of the first clock source A and the second clock source B. The PPM frequency offset counter generates an error signal output based on counting the fastest clock signal.

Some non-limiting advantages of the present disclosure are that the enhanced PPM frequency offset detector does not require a phase locked loop (PLL), loop filters, or creating PPM ranges to calculate a frequency offset or difference, as used in some known envelope detecting units. The disclosed PPM frequency offset detector uses two latches to detect a fastest clock signal between two clock signals that is used to detect frequency offset between the two clock signals, which is effective to implement. In one embodiment, the disclosed PPM frequency offset detector uses cascaded asynchronous latches providing a retimed offset clock enable with the fastest clock to avoid susceptibility to clock slivering, (i.e., a sliver clock pulse is a short duration clock pulse) which can prevent inaccurate counts for low PPM frequency offsets. The disclosed PPM frequency offset detector enables self-resetting when counts of the fast clock signal and the slow clock signal are reached.

FIG. 2 illustrates an example PPM frequency offset detector 200 to detect a frequency offset between two clock signals of one or more disclosed embodiments. PPM frequency offset detector 200 can be used in conjunction with the computer 101 and cloud environment of the computing environment 100 of FIG. 1 with the PPM Detector Control Component 182 for implementing methods according to one or more embodiments.

In accordance with the present disclosure, PPM frequency offset detector 200 detects a frequency offset between two clock signals, CLK_A and CLK_B from an independent first clock source and a second clock source, without using an additional independent reference clock, or third reference clock of some conventional arrangements. PPM frequency offset detector 200 effectively and efficiently detects a frequency offset between the asynchronous clock signals CLK_A and CLK_B, eliminating the need for a phase locked loop (PLL), loop filters, or creating PPM ranges to calculate a frequency offset or difference, often used in conventional envelope detecting arrangements.

PPM frequency offset detector 200 includes a pair of M bit counters A 202, and B 204 respectively receiving the independent, asynchronous first and second clock signals CLK_A and CLK_B. For example, the M bit counters A 202, and B 204 can be implemented with 21-bit counters or various other M bit counters. PPM frequency offset detector 200 includes an offset counter clock controller 206 and a frequency offset counter 208. The offset counter clock controller 206 receives at its inputs, count outputs BIT_N_A and BIT_N_B of the M bit counters A 202, and B 204, and the asynchronous first and second clock signals CLK_A and CLK_B. The outputs BIT_N_A and BIT_N_B of the M bit counters A 202, and B 204 comprise a programmable N bit count of the M bit counters. The offset counter clock controller 206 detects the fastest clock signal of the first and second clock signals CLK_A and CLK_B and applies the fastest clock signal CLK_PPM to the frequency offset counter 208.

In one embodiment, two asynchronous first and second clock signals CLK_A and CLK_B are applied to the M bit counters A 202, and B 204. Each M bit counter A 202, and B 204 is initialized to a zero (0) state before being enabled to start counting the respective asynchronous clock signals CLK_A and CLK_B. In operation, with a frequency offset between the two asynchronous clock signals CLK_A and CLK_B, one of the respective bits BIT_N_A or BIT_N_B (digital data signals) goes high earlier than BIT_N_B or BIT_N_A, depending on a fastest clock signal of the first source clock signal CLK_A or the second source clock signal CLK_B. The digital data signals outputs BIT_N_A and BIT_N_ B of M bit counters A 202, and B 204 feed the downstream offset counter clock controller 206. The offset counter clock controller 206 applies, the fastest clock signal, indicated at line CLK_PPM, to the PPM frequency offset counter 208 for counting the highest frequency clock of the first clock source signal CLK_A or the second clock source signal CLK_B. The offset counter clock controller 206 enables the PPM frequency offset counter 208 to start counting synchronously with the fastest clock signal (e.g., based on a bit count of the M bit counter A 202, or the M bit counter B 204) of the first clock signal CLK_A and the second clock signal CLK_B, such as based on BIT_N_A going high (e.g., with fast clock source signal CLK_A). The offset counter clock controller 206 disables the PPM frequency offset counter 208 to stop counting synchronously with the lowest frequency clock, of the first clock source signal CLK_A and the second clock source CLK_B, such as based on BIT_N_B going high (e.g., with slow clock source signal CLK_B), such as illustrated in FIG. 5.

FIG. 5 illustrates example illustrative PPM detector waveforms 500 of the PPM frequency offset detector 200 of one or more disclosed embodiments. In FIG. 5, an illustrated first clock signal CLK_A is faster than an illustrated second clock signal CLK_B. As shown, waveform BIT_N_A of the fast first clock signal CLK_A goes high, followed by a time delay interval until waveform BIT_N_B of the slow second clock signal CLK_B goes high, as indicated by an Arrow DELAY, which represents a time delay interval associated with a frequency offset between the first clock source signal CLK_A and the second clock source CLK_B.

FIG. 3 illustrates an example offset counter clock controller 206 of the PPM frequency offset detector 200, according to one disclosed embodiment. As shown, the offset counter clock controller 206 includes a Latch A, 302, a Latch B, 304, and a start logic circuit 306 (e.g., an example implementation of the start logic circuit 306 is shown in FIG. 4).

Latch A, 302, and Latch B, 304 are configured to detect a fastest clock signal of the first clock signal CLK_A and the second clock signal CLK_B, and the start logic circuit 306 controls counting (i.e., enables and disables counting) by the PPM frequency offset counter 208 of the fastest clock signal. Each of Latch A, 302, and Latch B, 304 can be implemented with a D (data) latch, which outputs the data D input at the Q output when the timing control (clock) C input is asserted or high; otherwise, the Q output holds the same D input when the C input was last asserted. As shown, BIT_N_A provides an input C to the Latch A, 302, and BIT_N_B provides an input C to the Latch B, 304. BIT_N_A provides an inverted input D to the Latch B, 304, and BIT_N_B provides an inverted input D to the Latch A, 302. When the first clock signal CLK_A is faster than the second clock signal CLK_B, the Q output of Latch A, 302 goes high for FASTA. Otherwise, when the second clock signal CLK_B is faster than the first clock signal CLK_A, then the Q output of Latch B, 304 goes high for FASTB.

Returning to FIG. 5 as shown, the first clock signal CLK_A is faster than the second clock signal CLK_B, and waveform FASTA of the fast first clock signal CLK_A goes high synchronously with the waveform BIT_N_A of the fast first clock signal CLK_A going high. As shown, the waveform FASTB of the slow second clock signal CLK_B remains low because the first clock signal CLK_A is faster than the second clock signal CLK_B.

Alternatively (e.g., not shown in FIG. 5), when the second clock signal CLK_B is faster than the first clock signal CLK_A, FASTB goes high synchronously with the waveform BIT_N_B of the fast second clock signal CLK_B, and the waveform FASTA of the slow first clock signal CLK_A remains low because the second clock signal CLK_B is faster than the first clock signal CLK_A.

For example, in an embodiment, with an example 21-bit counters 202, 204, and the first and second clock signals CLK_A, CLK_B are 100 MHz clocks, the respective waveform BIT_N_A and waveform BIT_N_B or the 21st bit go high at count 1048576. For example, another programmable bit number, such as the 15th bit (e.g., count=32768) can be used to detect which of the first clock signal CLK_A and the second clock signal CLK_B is faster. In an embodiment, the programmable bit number is a user-programmable value based on a given application of the PPM frequency offset detector 200. In an embodiment, with 100 MHz clocks A, B, and 21-bit counters 202, 204, the programmable bit number N can be provided, for example in a range between 10th bit and 21th bit of the 21-bit counters 202, 204.

In FIG. 3, the latch outputs FASTA, FASTB are applied to the start logic circuit 306 together with the BIT_N_A, of the first clock signal CLK_A and BIT_N_B, of the second clock signal CLK_B. The start logic circuit 306 uses BIT_N_A, and BIT_N_B, and the latch outputs FASTA, FASTB to control which clock (e.g., CLK_A or CLK_B) is applied to the PPM frequency offset counter 208 and when the fastest clock applied to the PPM frequency offset counter 208 is counted. The start logic circuit 306 applies the fastest clock CLK_PPM to the PPM frequency offset counter 208 based on the latch outputs FASTA, FASTB of Latch A, 302, and Latch B, 304. The PPM frequency offset counter 208 receives the PPM Select signal at startup or power on of the PPM frequency offset detector 200 and the start logic circuit 306 of the offset counter clock controller 206 applies the CLK_PPM of the fastest clock and enables counting by the PPM frequency offset counter 208 during an operational mode of the PPM frequency offset detector 200.

FIG. 4 illustrates details of an example implementation of the start logic circuit 306 of the offset counter clock controller 206 of the PPM frequency offset detector 200 of one disclosed embodiment. The start logic circuit 306 includes a pair of set-reset (SR) Latches 402, 404, which are asynchronous devices and rely on state of the S and R inputs independently of control signals. When a high input is applied to the S input of the SR Latches 402, 404, the Q output goes high, and is reset when a high input is applied to the R input of the SR Latches 402, 404. As shown, BIT_N-A is applied to the input S and BIT_N-B is applied to the input R of the SR Latch 402 to provide a high Q output of CLOCK_PPM_EN_A when BIT_N-A goes high, and is reset to provide a low Q output when the BIT_N-B goes high. As shown, BIT_N-B is applied to the input S and BIT_N-A is applied to the input R of the SR Latch 404 to provide high Q output of CLOCK_PPM_EN_B when BIT_N-B goes high, and reset to provide a low Q output when the BIT_N-A goes high when the first clock signal CLK_A is slower, i.e., the second first clock signal CLK_B is faster.

A first multiplexer (MUX) 406 (e.g., 2:1 multiplexer with 2 data lines and 1 select line) receives the Q output CLOCK_PPM_EN_A of the SR Latch 402 at input 0, the Q output CLOCK_PPM_EN_B of the SR Latch 404 at input 1, and FASTB at input S (select). An output CLOCK_PPM_EN_A is provided by the MUX 406 when the first clock signal CLK_A is the fastest clock. An output CLOCK_PPM_EN_B is provided by MUX 406 when the second clock signal CLK_B is the fastest clock. The MUX 406 provides an output CLOCK_PPM_EN (enable for the fastest clock A, or the fastest clock B) to an input D of a pair of cascaded DFFs (D Flip-Flops) 408 and 410. In an embodiment, the cascaded DFFs 408 and 410 are edge triggered flip-flops that trigger on a positive or rising clock edge when the clock pulse is changing from zero (0) to one (1). The cascaded DFFs 408 and 410 are configured to provide delay of up to 2 clock pulses to enable a retimed enable output Q of the cascaded latch 410 with the fastest clock to avoid susceptibility to clock slivering (i.e., to avoid missing a clock count with a short duration clock pulse or sliver clock pulse), preventing inaccurate counts for low PPM frequency offsets.

A second MUX 412 (e.g., 2:1 multiplexer) receives the first clock signal CLK_A at input 0, the second clock signal CLK_B at input 1, and FASTB at input S, providing a fastest clock output applied to an input 1 of a third MUX 414 (e.g., 2:1 multiplexer) and an input C to the cascaded DFFs 408 and 410. The cascaded DFFs 408 and 410 provides a Q retimed enable output of the cascaded latch 410 of CLOCK_PPM_EN_RETIMED, to input S of the third MUX 414. The third MUX 414 receives the retimed enable output Q of cascaded latch 410 of CLOCK_PPM_EN_RETIMED at its input S, with its input 0 connected to ground, and its input 1 of the fastest clock signal output of the second MUX 412. The third MUX 414 provides the output CLK_PPM of the fastest clock, which is received by the PPM frequency offset counter 208 of PPM frequency offset detector 200, as shown in FIGS. 2 and 3, such as illustrated by waveform CLK_PPM in FIG. 5 with the fastest clock CLK_A.

As shown, the offset counter clock controller 206 of the PPM frequency offset detector 200 provides the fastest clock signal at output CLK_PPM of the MUX 414 of the start logic circuit 306, enabled by the retimed enable signal CLOCK_PPM_EN_RETIMED applied to the select input of the MUX 414, to enable counting by the PPM frequency offset counter 208, using only the first clock signal CLK_A and the second clock signal CLK_B, eliminating the need for an additional reference clock signal for measuring the frequency offset between the first clock signal and the second clock signal.

Returning to FIG. 5, waveform CLK_PPM_EN goes high synchronously with the waveform BIT_N_A of the fast first clock signal CLK_A going high and the waveform FASTA, and remains high until waveform BIT_N_B of the slow second clock signal CLK_B goes high, as indicated by the Arrow DELAY. A waveform CLK_PPM_EN_RETIMED output of the cascaded DFF 410 includes a time delay, as indicated by arrow R (e.g., 1 cycle) following the waveform CLK_PPM_EN going high. As shown, waveform CLK_PPM of the fastest clock is applied to the PPM frequency offset counter 208, which begins one clock pulse or ½ cycle after the start of waveform CLK_PPM_EN_RETIMED. In an embodiment, the time delay R of waveform CLK_PPM_EN_RETIMED from the waveform CLK_PPM_EN, avoids susceptible to clock slivering, where clock slivering can otherwise result with inaccurate counts for low PPM offsets. An output of the PPM frequency offset counter 208 waveform ERROR is asserted or goes high synchronously with waveform BIT_N_B of the slow second clock signal CLK_B going high.

FIG. 6 is a flow chart illustrating example operational functions of PPM frequency offset detector 200, according to one disclosed embodiment. At block 602, a first source counter receives a first clock signal from a first clock signal source. At block 604, a second source counter receives a second clock signal from a second clock signal source. In an embodiment, the first source counter and the second source counter are M bit counters (e.g., the counters 202 and 204 in FIG. 2), such as 21-bit counters of various suitable implementations. At block 606, the first source counter transmits a count output of the first source counter, to an offset counter clock controller (e.g., the offset counter clock controller 206 in FIG. 2). At block 608, the second source counter transmits the count output of the second source counter, to the offset counter clock controller. In an embodiment, the count output represents a programmable bit count, such as the 15th bit (e.g., count=32768) or 21st bit (e.g., count=1048576) of the first and second source 21-bit counters. At block 610, the offset counter clock controller receives the first clock signal and the second clock signal.

At block 612, the offset counter clock controller detects a fastest clock of the first clock signal and the second clock signal; and applies the fastest clock signal to a PPM (parts per million) frequency offset counter (e.g., frequency offset counter 208 in FIG. 2), where the offset counter clock controller enables counting the fastest clock signal, by the PPM frequency offset counter, based on the count value of the fastest clock signal, and disables the counting the fastest clock signal based on the count output of the slowest clock signal, to detect a frequency offset between the first clock signal and the second clock signal.