DISPLAY DEVICE

A display device includes a substrate, a first driving transistor disposed over the substrate and included in a first subpixel, an overcoat layer over the first driving transistor, a first anode disposed over the first driving transistor and included in the first subpixel, a first emitting layer on the first anode, and a cathode on the first emitting layer. The first anode includes a first electrode part in a first area of the first subpixel, a second electrode part in a second area of the first subpixel different from the first area, and a first wire part connecting the first and second electrode parts. The overcoat layer includes a first trench in an area overlapping the first wire part. The first wire part includes a first bend disposed over the overcoat layer and bent along first and second inner side surfaces and a bottom surface of the first trench.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2021-0166127, filed on Nov. 26, 2021, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Technical Field

Embodiments of the present disclosure relate to a display device.

Description of Related Art

In fabrication of display panels, defects may occur due to a variety of reasons, for example, when an impurity is present in a variety of positions of a subpixel so that the subpixel forms a brightened point or a darkened point. For example, an impurity may be present between an anode and a cathode of an emitting device of each subpixel. In this case, the emitting device may not generate light, and thus the corresponding subpixel may become a darkened point.

BRIEF SUMMARY

In the field of display technology of the related art, when an anode-cathode short circuit is formed between an anode and a cathode of an emitting device by a process-induced impurity, a repair method of normalizing a corresponding subpixel by cutting a portion of the anode by irradiating the anode with a laser beam has been used. However, in such a repair method, separate laser irradiation equipment is required, and a laser beam must reach the anode electrode. Thus, there has been a problem in that the repair cannot be carried out in a situation in which a panel fabrication has been completed. In addition, there has been another problem in that, after shipment of a product and when a user has acquired a display device, the repair cannot be carried out. Therefore, the inventors of the present application have invented a repair method by which an anode can be self-cut without the irradiation of a laser beam, thereby normalizing a corresponding subpixel.

In embodiments of the present disclosure, provided is a display device having a structure by which a portion of an anode can be self-cut.

Also provided is a display device in which, during fabrication of a panel or after shipment of a product, a repair process of enabling a portion of an anode to be self-cut by reverse bias processing, thereby normalizing a corresponding subpixel, can be carried out.

According to embodiments, provided is a display device including: a substrate; a first driving transistor disposed over the substrate and included in a first subpixel; an overcoat layer over the first driving transistor; a first anode disposed over the first driving transistor and included in the first subpixel; a first emitting layer on the first anode; and a cathode on the first emitting layer.

The first anode may include a first electrode part disposed in a first area of the first subpixel, a second electrode part disposed in a second area of the first subpixel different from the first area, and a first wire part connecting the first electrode part and the second electrode part.

The overcoat layer may include a first trench in an area overlapping the first wire part. The first wire part may include a first bend disposed over the overcoat layer and bent along a first inner side surface, a bottom surface, and a second inner side surface of the first trench.

Also provided is a display device including: a first subpixel including a first driving transistor, a first anode, and a first emitting layer; a second subpixel including a second driving transistor, a second anode, and a second emitting layer; and an overcoat layer positioned between the first and second driving transistors and the first and second anodes, and including a first trench positioned in an area of the first anode and a second trench positioned in an area of the second anode.

The first anode may include a first electrode part disposed in a first area of the first subpixel, a second electrode part disposed in a second area of the first subpixel different from the first area, and a first wire part connecting the first electrode part and the second electrode part.

The second anode may include a third electrode part disposed in a third area of the second subpixel, a fourth electrode part disposed in a fourth area of the second subpixel different from the third area, and a second wire part connecting the third electrode part and the fourth electrode part.

When the first subpixel is a subpixel to which self-partial anode repair (SPARP) processing has been carried out and the second subpixel is a subpixel to which the SPARP processing has not been carried out, the first wire part may be disconnected inside the first trench of the overcoat layer, and the second wire part is not disconnected inside the second trench of the overcoat layer.

According to embodiments, the display device may have a structure by which a portion of an anode can be self-cut.

According to embodiments, in the display device, during fabrication of a panel or after shipment of a product, a repair process of enabling a portion of an anode to be self-cut by reverse bias processing, thereby normalizing a corresponding subpixel, can be carried out.

DETAILED DESCRIPTION

When it is mentioned that a first element “is connected or coupled to,” “contacts or overlaps,” etc., a second element, it should be interpreted that, not only can the first element “be directly connected or coupled to” or “directly contact or overlap” the second element, but a third element can also be “interposed” between the first and second elements, or the first and second elements can “be connected or coupled to,” “contact or overlap,” etc., each other via a fourth element. Here, the second element may be included in at least one of two or more elements that “are connected or coupled to,” “contact or overlap,” etc., each other. The term “over” is used herein in its broadest sense to include above, on, directly on, directly above, over and various combinations thereof, therefore the term “over” as used here of one structure relative to another structure is to be interpreted to include any one of those meanings or combinations thereof. Hereinafter, a variety of embodiments will be described in detail with reference to the accompanying drawings.

FIG.1is a diagram illustrating a system configuration of a display device100according to embodiments. Referring toFIG.1, a display driving system of the display device100according to embodiments may include a display panel110and a display driver circuit driving the display panel110.

The display panel110may include a display area DA on which images are displayed and a non-display area NDA on which images are not displayed. The display panel110may include a plurality of subpixels SP disposed over a substrate SUB in order to display images. The display panel110may include a plurality of signal lines disposed over the substrate SUB to drive the plurality of subpixels SP. For example, the plurality of signal lines may include data lines DL, gate lines GL, drive voltage lines, and the like.

Each of the plurality of data lines DL may be arranged to extend in a first direction (e.g., a column direction or a row direction). Each of the plurality of gate lines GL may be arranged to extend in a direction transverse (e.g., perpendicular to) the first direction.

The display driver circuit may include a data driver circuit120and a gate driver circuit130, and also include a controller140to control the data driver circuit120and the gate driver circuit130.

The data driver circuit120may output data signals (also referred to as data voltages) corresponding to image signals to the plurality of data lines DL. The gate driver circuit130may generate gate signals and output the gate signals to the plurality of gate lines GL. The controller140may convert image data input from an external host150into image data having a data signal format readable by the data driver circuit120, and supply the image data to the data driver circuit120.

The data driver circuit120may include one or more source driver integrated circuits (SDICs). For example, each of the SDICs may be connected to the display panel110by a tape-automated bonding (TAB) method, connected to a bonding pad of the display panel110by a chip-on-glass (COG) method or a chip-on-panel (COP) method, or implemented as a chip-on-film (COF) structure connected to the display panel110.

The gate driver circuit130may be connected to the display panel110by a TAB method, connected to a bonding pad of the display panel110by a COG method or a COP method, connected to the display panel110by a COF method, or formed in the non-display area NDA of the display panel110by a gate-in-panel (GIP) method.

Referring toFIG.1, in the display device100according to embodiments, each of the subpixels SP includes an emitting device ED and a pixel driver circuit SPC to drive the emitting device ED. The pixel driver circuit SPC may include a driving transistor DRT, a scan transistor SCT, and a storage capacitor Cst.

The driving transistor DRT may drive the emitting device ED by controlling a current flowing through the emitting device ED. The scan transistor SCT may transfer a data voltage Vdata to a second node N2, i.e., a gate node, of the driving transistor DRT. The storage capacitor Cst may be configured to maintain a voltage for a predetermined or selected time.

The emitting device ED may include an anode electrode AE, a cathode CE, and an emissive layer EL positioned between the anode electrode AE and the cathode CE. The anode AE may be a pixel electrode involved in the formation of the emitting device ED of each of the subpixels SP, and may be electrically connected to a first node N1of the driving transistor DRT. The cathode CE may be a common electrode involved in the formation of the emitting device ED of each of the subpixels SP, and a base voltage EVSS may be applied to the cathode CE.

For example, the emitting device ED may be an organic light-emitting diode (OLED), a light-emitting diode (LED) based on an inorganic material, a quantum dot emitting device that is a self-emissive semiconductor crystal, or the like.

The driving transistor DRT may be a transistor to drive the emitting device ED, and may include the first node N1, the second node N2, and a third node N3. The first node N1may be a source node or a drain node, and may be electrically connected to the anode AE of the emitting device ED. The second node N2may be a gate node, and may be electrically connected to a source node or a drain node of the scan transistor SCT. The third node N3may be a drain node or a source node, and may be electrically connected to a driving voltage line DVL through which a driving voltage EVDD is supplied. Hereinafter, for the sake of brevity, the first node N2will be described as being a source node, whereas the third node N3will be described as being a drain node.

The scan transistor SCT may switch the connection between a data line DL and the second node N2of the driving transistor DRT. The scan transistor SCT may control the connection between the second node N2of the driving transistor DRT and a corresponding data line DL among the plurality of data lines DL in response to a scan signal SCAN supplied through a scan line SCL, i.e., a type of gate line GL.

The storage capacitor Cst may be provided between the first node N1and the second node N2of the driving transistor DRT.

The structure of the subpixel SP illustrated inFIG.1is only an example given for explanation. Rather, the subpixel structure may further include one or more transistors or one or more capacitors. In addition, all of the plurality of subpixels may have the same structure, or some of the plurality of subpixels may have a different structure. Each of the driving transistor DRT and the scan transistor SCT may be an N-type transistor or a P-type transistor.

In addition, the display device100according to embodiments may have a top emission structure or a bottom emission structure. Hereinafter, as an example, the display device100will be described as having a top emission structure. For example, in the case of the top emission structure, the anode AE may be formed of a reflective metal, whereas the cathode CE may be formed of a transparent conductive film.

FIG.2illustrates a cathode-anode short circuit in a subpixel SP in which an impurity is present in the display device100according to embodiments. Referring toFIG.2, during a panel fabrication process or after the panel fabrication process (e.g., after shipment of a product), an impurity may present in an area of a subpixel SP among the plurality of subpixels SP disposed in the display panel110. When the impurity present in the area of the subpixel SP is positioned on the anode AE of the emitting device ED, the anode AE and the cathode CE may be electrically short-circuited by the impurity. This phenomenon will be referred to as a cathode-anode short circuit AC Short.

When a cathode-anode short circuit is formed, driving current supplied by the driving transistor DRT may flow directly from the anode AE electrically connected to the first node N1of the driving transistor DRT to the cathode CE. Consequently, the emitting device ED in the subpixel SP in which the cathode-anode short circuit is formed may not generate light, and thus the corresponding subpixel SP may be darkened. The subpixel SP darkened by the cathode-anode short circuit having the impurity may also be referred to as a bad subpixel Bad SP.

FIG.3illustrates an aging process for removing a cathode-anode short circuit in the display device100according to embodiments.

Referring toFIG.3, during a panel fabrication process or during a product repair process after shipment of the product, an aging process for removing a cathode-anode short circuit may be performed. The aging process is a type of repair method for the subpixels SP. The aging process may include reverse bias processing to apply a reverse bias voltage RBL between the cathode CE and the third node N3of the driving transistor DRT.

The reverse bias processing may be performed by the display driver circuit including the data driver circuit120, the gate driver circuit130, the controller140, a power management circuit, and the like. In the reverse bias processing, a turn-on level voltage may be supplied to the second node N2of the driving transistor DRT in order to turn on the driving transistor DRT. Here, the turn-on level voltage may be a turn-on level data voltage Vdata supplied to the second node N2of the driving transistor DRT through the scan transistor SCT. In the reverse bias processing, a driving voltage EVDD may be converted into a low level voltage, and the base voltage EVSS may be converted into a high level voltage.

In the reverse bias processing of the aging process, the cathode CE may have a higher voltage than the anode AE. When the reverse bias processing is performed, an aging current may flow from the cathode CE to the third node N3of the driving transistor DRT. Here, the aging current may flow through the driving transistor DRT.

When the aging process is performed, heat may be generated in a portion in which the cathode-anode short circuit is formed. The generation of heat in the portion having the cathode-anode short circuit through the aging process may be referred to as Joule heating. Heat generated in the portion having the cathode-anode short circuit may melt the cathode CE and the impurity, thereby removing the cathode-anode short circuit.

FIG.4illustrates emission states of a normal subpixel SP, a bad subpixel SP in which a cathode-anode short circuit AC Short is formed, a normalized subpixel SP from which a cathode-anode short circuit AC Short has been removed, and a bad subpixel SP from which a cathode-anode short circuit AC Short has not been removed.

When a cathode-anode short circuit is formed by an impurity in the area of a subpixel SP having a normal emission state (S1), the entire emission area of the subpixel SP may be darkened (S2). The darkened state (S2) of the subpixel SP may be recognized, and an aging process for the darkened subpixel SP may be performed.

When the cathode-anode short circuit is removed in the aging process, only a portion from which the cathode-anode short circuit is removed is in a non-emission state, and the overall emission state of the subpixel SP may be recognized as being generally normal (S3-1). When the cathode-anode short circuit is not removed in the aging process, the entire emission area of the subpixel SP may remain in the darkened state (S3-2).

As described above, in the case of the aging process, a situation in which the cathode-anode short circuit is not removed and the subpixel SP is not normalized may frequently occur. Therefore, embodiments of the present disclosure propose “self-partial anode repair (SPARP)” as a repair method having a higher probability to normalize a bad subpixel having an impurity.

The SPARP according to embodiments of the present disclosure is a repair process of cutting a portion of the anode AE of the subpixel SP having an impurity so that a portion of a subpixel SP is enabled to emit light using the remaining portion of the anode AE, thereby normalizing the subpixel SP.

In the SPARP processing according to embodiments, the partial cutting of the anode AE is a method of causing the anode AE to be self-cut in response to the application of a reverse bias voltage as in the aging process, rather than a method of cutting the anode AE by irradiating the anode AE with a laser beam or applying physical force to the anode AE.

In the SPARP processing according to embodiments, the anode AE may have a self-cutting enabled structure (also referred to as a trench structure) for the SPARP. In addition, an insulating layer below the anode AE may have a trench so that the self-cutting enabled structure (also referred to as the trench structure) can be formed. Here, the insulating layer having a trench may also be referred to as an overcoat layer.

When the SPARP according to embodiments is a repair method of normalizing a subpixel SP having an impurity by partially cutting the anode AE of the subpixel SP and lighting a half of the subpixel SP using a half of the anode AE, the SPARP may be referred to as self-half anode repair (SHARP). Hereinafter, for the sake of brevity, a structure for the SPARP and SPARP processing will be described in detail on the assumption that the SPARP is the SHARP.

The SPARP processing according to embodiments may be carried out during the panel fabrication process or during product repair processing after shipment of a product, or may be carried out while a repair menu function in user environment settings is being executed after the shipment of the product.

FIGS.5and6are equivalent circuits of first subpixels SP1for conceptually describing the SPARP of the display device100according to embodiments. The equivalent circuit of the first subpixel SP illustrated inFIG.5is an equivalent circuit of a normal subpixel without a cathode-anode short circuit due to no impurities being present therein. The equivalent circuit of the first subpixel SP illustrated inFIG.6is an equivalent circuit of a subpixel from which a cathode-anode short circuit is removed by the SPARP processing according to embodiments.

Referring toFIG.5, each of the subpixels SP in the display device100according to embodiments may include a first emitting device ED1, a first driving transistor DRT1, a first scan transistor SCT1, and a first storage capacitor Cst1. Each of the subpixels SP may further include a first sensing transistor SENT1switching the connection between a first node N1of the driving transistor DRT and a reference voltage line RVL. The first sensing transistor SENT1may be controlled by a sensing signal SENSE so as to be turned on or off.

As illustrated inFIG.5, a scan line SCL connected to a gate node of the first scan transistor SCT1and a sensing line SENL of the first sensing transistor SENT1may be different gate lines GL. Alternatively, the scan line SCL connected to the gate node of the first scan transistor SCT1and the sensing line SENL of the first sensing transistor SENT1may be may be the same gate line GL.

Referring toFIG.5, for the SPARP according to embodiments, the first emitting device ED1may include a first emitting device part PED1and a second emitting device part PED2. The first emitting device part PED1and the second emitting device part PED2may be connected in parallel to the first node N1of the first driving transistor DRT1and the cathode CE.

Referring toFIG.5, the first emitting device ED1may include a first anode AE1, a first emitting layer EL1, and a cathode CE. For the SPARP according to embodiments, the first anode AE1may include a first electrode part PAE1, a second electrode part PAE2, and a first wire (or conductive line) part CL1.

The first wire part CL1may connect the first electrode part PAE1and the second electrode part PAE2, and be electrically connected to the first node N1of the first driving transistor DRT1through a contact hole CNT.

The first emitting device part PED1may include the first electrode part PAE1, the first emitting layer EL1, and the cathode CE, whereas the second emitting device part PED2may include the second electrode part PAE2, the first emitting layer EL1, and the cathode CE.

Referring toFIG.5, in response to current driving of the first driving transistor DRT1, a first partial driving current Iped1may flow through the first emitting device part PED1, whereas a second partial driving current Iped2may flow through the second emitting device part PED2. Thus, the light can be emitted from the entire emission-possible area corresponding to the first emitting device ED1.

When a cathode-anode short circuit is formed by an impurity in the area of the first subpixel SP1, the SPARP processing according to embodiments may be carried out. For example, it will be assumed that a short circuit is formed between the first electrode part PAE1and the cathode CE as an impurity is present between the first electrode part PAE1, among the first electrode part PAE1and the second electrode part PAE2, and the cathode CE.

For the SPARP processing according to embodiments, the first wire part CL1may have predetermined or selected cutting points CP1and CP2.

The predetermined or selected cutting points CP1and CP2in the first wire part CL1may include one or more among the first cutting point CP1between the contact hole CNT and the first electrode part PAE1and the second cutting point CP2between the contact hole CNT and the second electrode part PAE2. Hereinafter, for the sake of brevity, it will be assumed that both the first cutting point CP1(i.e., a point at which a first trench TRC1to be described later is formed) and the second cutting point CP2(i.e., a point at which a second trench TRC2to be described later is formed) are present. In the predetermined or selected cutting points CP1and CP2, the first wire part CL1may have a structure (i.e., a self-cutting enabled structure) that can be easily cut by the reverse bias processing.

Referring toFIG.6, in the SPARP processing according to embodiments, the first wire part CL1may be self-cut by the reverse bias processing at the first cutting point CP1more adjacent to an impurity site PAE1to CE (i.e., the position of a cathode-anode short circuit), among the first cutting point CP1and the second cutting point CP2, due to characteristics of the self-cutting enabled structure.

Referring toFIG.6, in the SPARP processing according to embodiments, in response to current driving of the first driving transistor DRT1, no current is supplied to the first emitting device part PED1, whereas the second partial driving current Iped2may flow through the second emitting device part PED2. Thus, light can be emitted from an emission-possible area corresponding to the second emitting device part PED2, among the entire emission-possible area corresponding to the first emitting device ED1. That is, light can only be emitted from the half of the entire emission-possible area corresponding to the first emitting device ED1. However, since light can be emitted from a portion of the first subpixel SP, the first subpixel SP can be recognized as a normal subpixel.

Hereinafter, the self-cutting enabled structure of the first anode AE1which can be easily cut by the reverse bias processing in the above-described SPARP processing according to embodiments will be described in more detail.

FIGS.7to9illustrate an example of the self-cutting enabled structure of the first anode AE1for the SPARP of the display device100according to embodiments, andFIG.10illustrates an example of the first trench TRC1of the overcoat layer OC for the SPARP of the display device100according to embodiments.

Referring toFIGS.7to10, for the SPARP according to embodiments, the first anode AE1may have a self-cutting enabled structure (also referred to as a trench structure or an SPARP structure). Here, the first anode AE1taken as an example may be included in the first subpixel SP, and be a pixel electrode of the first emitting device ED1in a first subpixel SP.

The first subpixel SP may include the first driving transistor DRT1disposed over a substrate SUB. The overcoat layer OC, a type of insulating layer, may be disposed over the first driving transistor DRT1.

The first anode AE1may be disposed over the first driving transistor DRT1, and be electrically connected to the first node N1of the first driving transistor DRT1through the contact hole CNT in the overcoat layer OC. The first emitting layer EL1may be disposed on the first anode AE1. The cathode CE may be disposed on the first emitting layer EL1.

Referring toFIGS.7to10, the first anode AE1may include the first electrode part PAE1, the second electrode part PAE2, and the first wire part CL1. The first electrode part PAE1may be disposed in a first area A1of the first subpixel SP. The second electrode part PAE2may be disposed in a second area A2of the first subpixel SP different from the first area A1. The first wire part CL1may connect the first electrode part PAE1and the second electrode part PAE2.

The first emitting layer EL1may be disposed on all of the first electrode part PAE1, the second electrode part PAE2, and the first wire part CL1, or only be disposed on the first electrode part PAE1and the second electrode part PAE2.

In the first emitting layer EL1, a portion positioned on the first electrode part PAE1and a portion positioned on the second electrode part PAE2may be integrated. Alternatively, the first emitting layer EL1may be divided into a portion positioned on the first electrode part PAE1and a portion positioned on the second electrode part PAE2.

Referring toFIGS.7and8, the overcoat layer OC may include the first trench TRC1in an area in which the overcoat layer OC overlaps the first wire part CL1. Here, the position of the first trench TRC1may match the position of the first cutting point CP1among the predetermined or selected cutting points CP1and CP2in the first wire part CL1.

The first wire part CL1may include a first bend BL1disposed over the overcoat layer OC, and bent along a first inner side surface SIDE1a, a bottom surface BOT1, and a second inner side surface SIDE1bof the first trench TRC1.

The first wire part CL1may be electrically connected to the first node N1of the first driving transistor DRT1through the contact hole CNT (seeFIG.24) in the overcoat layer OC.

Referring toFIGS.7and9, the overcoat layer OC may further include the second trench TRC2in an area in which the overcoat layer OC overlaps the first wire part CL1. Here, the position of the second trench TRC2may match the position of the second cutting point CP2among the predetermined or selected cutting points CP1and CP2in the first wire part CL1.

The first wire part CL1may further include a second bend BL2disposed over the overcoat layer OC, and bent along a first inner side surface SIDE2a, a bottom surface BOT2, and a second inner side surface SIDE2bof the second trench TRC2.

The first trench TRC1may be positioned between the contact hole CNT and the first electrode part PAE1, whereas the second trench TRC2may be positioned between the contact hole CNT and the second electrode part PAE2.

The first trench TRC1may have a structure by which the first bend BL1of the first wire part CL1can be self-cut when a cathode-anode short circuit is formed by an impurity present between the first electrode part PAE1and the cathode CE. The second trench TRC2may have a structure by which the second bend BL2of the first wire part CL1can be self-cut when a cathode-anode short circuit is formed by an impurity present between the second electrode part PAE2and the cathode CE.

Referring toFIGS.7and10, the first trench TRC1of the overcoat layer OC may be formed in a direction transverse (e.g., perpendicular to) the longitudinal direction of the first wire part CL1. Likewise, the second trench TRC2of the overcoat layer OC may extend in a direction transverse (e.g., perpendicular to) the longitudinal direction of the first wire part CL1.

Referring toFIGS.7and8, a first organic material OM1may be disposed inside the first trench TRC1and around the first trench TRC1. The first wire part CL1may be disposed on the first organic material OM1.

The first organic material OM1may include a first side organic material OM1spositioned on the first inner side surface SIDE1aand second inner side surface SIDE1bof the first trench TRC1. The first side organic material OM1smay extend to outer portions TOP1aand TOP1bof the first trench TRC1. That is, the first side organic material OM1smay extend to the outer portions TOP1aand TOP1bof the first trench TRC1to be disposed on the outer portions TOP1aand TOP1bof the first trench TRC1. The first organic material OM1may further include a first bottom organic material OM1bpositioned on the bottom surface BOT1of the first trench TRC1.

Referring toFIGS.7and8, the first cutting point CP1may be a point between the first side organic material OM1sand the first bottom organic material OM1b. In the SPARP processing according to embodiments, when the reverse bias processing is carried out, the first wire part CL1of first anode AE1may be easily disconnected (e.g., broken) at the first cutting point CP1between the first side organic material OM1sand the first bottom organic material OM1b.

As described above, since the first side organic material OM1sand the first bottom organic material OM1bare disposed on the inner side surfaces SIDE1aand SIDE1band the bottom surface BOT1of the first trench TRC1formed in the overcoat layer OC and the first side organic material OM1sand the first bottom organic material OM1bare bent, the first wire part CL1of first anode AE1may be disposed so as to be easily disconnectable at the first cutting point CP1between the first side organic material OM1sand the first bottom organic material OM1bwhen the reverse bias processing is carried out in the SPARP processing according to embodiments.

Referring toFIGS.7and9, a second organic material OM2may be disposed inside the second trench TRC2and around the second trench TRC2. The first wire part CL1may be disposed on the second organic material OM2. The second organic material OM2may include a second side organic material OM2spositioned on the first inner side surface SIDE2aand the second inner side surface SIDE2bof the second trench TRC2. The second side organic material OM2smay be disposed to extend to outer portions TOP2aand TOP2bof the second trench TRC2. That is, the second side organic material OM2smay extend to the outer portions TOP2aand TOP2bof the second trench TRC2and be disposed on the outer portions TOP2aand TOP2bof the second trench TRC2. The second organic material OM2may further include a second bottom organic material OM2bpositioned on the bottom surface BOT2of the second trench TRC2.

Referring toFIGS.7and9, the second cutting point CP2may be a point between the second side organic material OM2sand the second bottom organic material OM2b. In the SPARP processing according to embodiments, when the reverse bias processing is carried out, the first wire part CL1of first anode AE1may be easily disconnected at the second cutting point CP2between the second side organic material OM2sand the second bottom organic material OM2b. As described above, since the second side organic material OM2sand second bottom organic material OM2bare disposed on the inner side surfaces SIDE2aand SIDE2band the bottom surface BOT2of the second trench TRC2formed in the overcoat layer OC and the second side organic material OM2sand the second bottom organic material OM2bare bent, the first wire part CL1of first anode AE1may be disposed so as to be easily disconnectable at the second cutting point CP2between the second side organic material OM2sand the second bottom organic material OM2bwhen the reverse bias processing is carried out in the SPARP processing according to embodiments.

The state of the first anode AE1may vary depending on the presence or absence of the SPARP processing according to embodiments or the type of the first subpixel SP (e.g., a normal subpixel without an impurity or a subpixel normalized by the SPARP processing).

When the first subpixel SP is a normal subpixel, that is, when the first subpixel SP is a subpixel to which the SPARP processing has not been carried out, all of the first electrode part PAE1, the second electrode part PAE2, and the first wire part CL1may be supposed to be electrically connected.

When the first subpixel SP is a subpixel normalized from a bad subpixel having a cathode-anode short circuit caused by an impurity, that is, the first subpixel SP is a subpixel normalized from the bad subpixel through the SPARP processing, only one of the first electrode part PAE1and the second electrode part PAE2may be supposed to be electrically connected to the first wire part CL1.

In the SPARP processing according to embodiments, how easily the first wire part CL1of first anode AE1having a cathode-anode short circuit will be disconnected may vary depending on the trench structure (e.g., a width Wt, a depth Dt, or an inner side surface inclination θt) of the overcoat layer OC or the width WL of the first wire part CL1.

Referring toFIGS.8and10, the first trench TRC1of the overcoat layer OC is a type of groove, and is a path through which the first wire part CL1of first anode AE1extends. The first wire part CL1of first anode AE1may extend through the first trench TRC1of the overcoat layer OC. The first wire part CL1of first anode AE1may be disposed along the first inner side surface SIDE1a, the bottom surface BOT1, and the second inner side surface SIDE1bof the first trench TRC1.

Referring toFIGS.8and10, the depth Dt of the first trench TRC1may be the height from the outer portions TOP1aand TOP1bof the first trench TRC1to the bottom surface BOT1of the first trench TRC1. The width Wt of the first trench TRC1may be the distance between the first inner side surface SIDE1aand the second inner side surface SIDE1b. The width Wt of the first trench TRC1may be determined on the basis of the bottom surface BOT1. The inner side surface inclination θt of the first trench TRC1may be an angle between the first inner side surface SIDE1aor the second inner side surface SIDE1band the bottom surface BOT1.

Referring toFIGS.7to10, the first trench TRC1and the second trench TRC2through which the first wire part CL1extents may have the same structure (e.g., the same width Wt, depth Dt, or inner side surface inclination θt).

Referring toFIGS.7to10, the first wire part CL1of first anode AE1may have a predetermined or selected width WL. The width WL of the first wire part CL1may correspond to the length Lt of the first trench TRC1. The length Lt of the first trench TRC1may be equal to the width WL of the first wire part CL1, greater than the width WL of the first wire part CL1, or smaller than the width WL of the first wire part CL1.

FIG.11illustrates examples of inner side surface inclination structures of the first trench TRC1of the overcoat layer OC for the SPARP of the display device100according to embodiments.

The inner side surface inclination θt of the first trench TRC1is an angle between the inner side surface SIDE1of the first trench TRC1and the bottom surface BOT1of the first trench TRC1. Here, the inner side surface SIDE1of the first trench TRC1may be the first inner side surface SIDE1aor the second inner side surface SIDE1b.

As in CASE1, the inner side surface inclination θt of the first trench TRC1may be in the range greater than 90° and smaller than 180°. As in CASE2, the inner side surface inclination θt of the first trench TRC1may be 90° (vertical). As in CASE3, the inner side surface inclination θt of the first trench TRC1may be in the range greater than 0° and smaller than 90°. The inner side surface inclination structure of CASE1may be referred to as a tapered structure, whereas the inner side surface inclination structure of CASE3may be referred to as an inverted tapered structure.

The self-cutting enabled structure of the first anode AE1refers to a structure refers to a structure by which the first wire part CL1of first anode AE1can be easily disconnected inside the first trench TRC1.

As the self-cutting enabled structure of the first anode AE1, the inverted tapered structure of CASE3may be most suitable, and the vertical structure of CASE2may be the next suitable. Thus, for the self-cutting enabled structure of the first anode AE1, the angle between the first inner side surface SIDE1aor the second inner side surface SIDE1bof the first trench TRC1and the bottom surface BOT1of the first trench TRC1may be equal to or smaller than 90° (CASE2and CASE3).

FIG.12illustrates examples of organic material deposition structures in the first trench TRC1of the overcoat layer OC for the SPARP of the display device100according to embodiments.

For the self-cutting enabled structure of the first anode AE1, the first organic material OM1may be deposited inside and around the first trench TRC1.

The first organic material OM1may include the first side organic material OM1spositioned on the first inner side surface SIDE1aand the second inner side surface SIDE1bof the first trench TRC1and the first bottom organic material OM1bpositioned on the bottom surface BOT1of the first trench TRC1. The first side organic material OM1smay extend to the outer portions TOP1aand TOP1bof the first trench TRC1to be disposed on the outer portions TOP1aand TOP1bof the first trench TRC1.

As in CASE4, the first side organic material OM1sand the first bottom organic material OM1bmay be separated from each other. Alternatively, the first side organic material OM1sand the first bottom organic material OM1bmay be connected to each other.

FIG.13illustrates an example of the first anode AE1self-cut by the SPARP processing for the first subpixel SP in the display device100according to embodiments.

In the area of the first subpixel SP, in a situation in which a cathode-anode short circuit is formed by an impurity present between the first electrode part PAE1of the first anode AE1and the cathode CE, when the SPARP processing according to embodiments is carried out for the first subpixel SP, the reverse bias processing (seeFIG.3) may be carried out.

When the reverse bias processing is carried out, the first wire part CL1may be self-cut inside the first trench TRC1due to characteristics of the self-cutting enabled structure (i.e., the trench structure). Particularly, the first wire part CL1may be self-cut inside the first trench TRC1more adjacent to a position at which the cathode-anode short circuit is formed, among the first trench TRC1and the second trench TRC2.

Here, the two predetermined or selected cutting points CP1and CP2in the first wire part CL1may include the first cutting point CP1between the contact hole CNT and the first electrode part PAE1and the second cutting point CP2between the contact hole CNT and the second electrode part PAE2. The first cutting point CP1may be at the position at which the first trench TRC1is formed, and the second cutting point CP2may be at the position at which the second trench TRC2is formed.

FIG.14illustrates changes in the emission state of the first subpixel SP before and after the SPARP processing for the first subpixel SP.

The state of the first anode AE1may vary depending on the presence or absence of the SPARP processing according to embodiments or the type of the first subpixel SP (e.g., a normal subpixel without an impurity or a subpixel normalized by the SPARP processing).

When the first subpixel SP is a normal subpixel, that is, when the first subpixel SP is a subpixel to which the SPARP processing has not been carried out, all of the first electrode part PAE1, the second electrode part PAE2, and the first wire part CL1may be supposed to be electrically connected.

Thus, driving current supplied by the first driving transistor DRT1may be supplied to the first electrode part PAE1and the second electrode part PAE2through the first wire part CL1. Consequently, both the first area A1in which the first electrode part PAE1is disposed and the second area A2in which the second electrode part PAE2is disposed may generate light, and the first subpixel SP may be recognized as normally generating light.

When a cathode-anode short circuit is formed by an impurity present between the first electrode part PAE1of the first anode AE1and the cathode CE, neither the first area A1in which the first electrode part PAE1is disposed nor the second area A2in which the second electrode part PAE2is disposed can generate light. Consequently, the first subpixel SP may be recognized as a darkened point.

When the SPARP processing according to embodiments is carried out, the first bend BL1of the first wire part CL1may be in a disconnected state. That is, the first bend BL1of the first wire part CL1may be self-cut inside the first trench TRC1.

Thus, the first electrode part PAE1among the first electrode part PAE1and the second electrode part PAE2is not electrically connected to the first driving transistor DRT1through the first wire part CL1.

Consequently, driving current supplied by the first driving transistor DRT1may only be supplied to the second electrode part PAE2through the first wire part CL1. As a result, in the first area A1in which the first electrode part PAE1is disposed and the second area A2in which the second electrode part PAE2is disposed, the first area A1does not generate light, and only the second area A2can generate light. As described above, when the second area A2, a portion of the entire emission area of the first subpixel SP, generates light, the first subpixel SP may be recognized as normally emitting light.

FIG.15illustrates an example of a first driving transistor DRT1in a first subpixel SP1and an example of a second driving transistor DRT2in a second subpixel SP2in the display device100according to embodiments, andFIG.16illustrates an example of first anode AE1in the first subpixel SP1and an example of second anode AE2in the second subpixel SP2in the display device100according to embodiments.

Referring toFIG.15, the plurality of subpixels SP disposed in the display panel110may include the first subpixel SP and the second subpixel SP2. Each of the first subpixel SP and the second subpixel SP2may have the subpixel structure illustrated inFIG.1or the subpixel structure illustrated inFIG.5. Briefly described, the first subpixel SP may include the first driving transistor DRT1and the first emitting device ED1disposed over the substrate SUB. The second subpixel SP2may include the second driving transistor DRT2and a second emitting device ED2disposed over the substrate SUB.

The first emitting device ED1may include the first anode AE1, the first emitting layer EL1, and the cathode CE. The second emitting device ED2may include the second anode AE2, a second emitting layer EL2, and the cathode CE.

The first anode AE1may be disposed over the first driving transistor DRT1, and be included in the first subpixel SP. The first emitting layer EL1may be disposed on the first anode AE1.

The second anode AE2may be disposed over the second driving transistor DRT2, and be included in the second subpixel SP2. The second emitting layer EL2may be disposed on the second anode AE2. The cathode CE may be disposed on the first emitting layer EL1and the second emitting layer EL2.

A buffer layer BUF may be disposed over the substrate SUB, and the first driving transistor DRT1and the second driving transistor DRT2may be disposed over the buffer layer BUF. A first light shield layer LS1may be disposed below the first driving transistor DRT1, and a second light shield layer LS2may be disposed below the second driving transistor DRT2.

The first driving transistor DRT1may include a first active layer ACT1, a first source electrode S1, a first drain electrode D1, and a first gate electrode G1. The first active layer ACT1may be disposed over the buffer layer BUF, and include a first channel area CH1, a first source conductorized area SC1, and a first drain conductorized area DC1. A gate insulating film G1may be disposed on the first active layer ACT1, and the first gate electrode G1may be disposed on the gate insulating film G1. An interlayer insulating film ILD may be disposed on the first active layer ACT1and the first gate electrode G1. The first source electrode S1and the first drain electrode D1may be disposed on the interlayer insulating film ILD, and be electrically connected to the first source conductorized area SC1and the first drain conductorized area DC1through holes in the interlayer insulating film ILD, respectively.

The second driving transistor DRT2may include a second active layer ACT2, a second source electrode S2, a second drain electrode D2, and a second gate electrode G2. The second active layer ACT2may be disposed over the buffer layer BUF, and may include the second channel area CH2, the second source conductorized area SC2, and the second drain conductorized area DC2. The gate insulating film G1may be disposed on the second active layer ACT2, and the second gate electrode G2may be disposed on the gate insulating film G1. The interlayer insulating film ILD may be disposed on the second active layer ACT2and the second gate electrode G2. The second source electrode S2and the second drain electrode D2may be disposed on the interlayer insulating film ILD, and be electrically connected to the second source conductorized area SC2and the second drain conductorized area DC2through contact holes in the interlayer insulating film ILD.

The channel size of the first driving transistor DRT1may be a value W1/L1obtained by dividing the width W1of the first channel area CH1with the length L1of the first channel area CH1. The channel size of the second driving transistor DRT2may be a value W2/L2obtained by dividing the width W2of the second channel area CH2with the length L2of the second channel area CH2.

For example, the channel size W1/L1of the first driving transistor DRT1may be the same as the channel size W2/L2of the second driving transistor DRT2. For another example, the channel size W1/L1of the first driving transistor DRT1may be different from the channel size W2/L2of the second driving transistor DRT2.

Referring toFIG.16, the first anode AE1may include the first electrode part PAE1disposed in the first area A1of the first subpixel SP1, the second electrode part PAE2disposed in the second area A2different from the first area A1of the first subpixel SP1, and the first wire part CL1connecting the first electrode part PAE1and the second electrode part PAE2.

The first wire part CL1may be electrically connected to the first node N1of the first driving transistor DRT1through the contact hole CNT.

The overcoat layer OC may include the first trench TRC1in an area overlapping the first wire part CL1. The overcoat layer OC may further include the second trench TRC2in an area overlapping the first wire part CL1. The first organic material OM1may be disposed inside and around the first trench TRC1. The second organic material OM2may be disposed inside and around the second trench TRC2.

The second anode AE2may include a third electrode part PAE3disposed in a third area A3of the second subpixel SP2, a fourth electrode part PAE4disposed in a fourth area A4different from the third area A3of the second subpixel SP2, and a second wire part CL2connecting the third electrode part PAE3and the fourth electrode part PAE4.

The second wire part CL2may be electrically connected to the first node N1of the second driving transistor DRT2through a contact hole CNT.

The overcoat layer OC may include a third trench TRC3in an area overlapping the second wire part CL2. The overcoat layer OC may further include a fourth trench TRC4in an area overlapping the second wire part CL2. The third organic material OM3may be disposed inside and around the third trench TRC3. The fourth organic material OM4may be disposed inside and around the fourth trench TRC4.

In the area of the first subpixel SP1, the overcoat layer OC may include the first trench TRC1and the second trench TRC2. In the area of the second subpixel SP2, the overcoat layer OC may include the third trench TRC3and the fourth trench TRC4.

When the channel size W1/L1of the first driving transistor DRT1of the first subpixel SP1is the same as or similar to the channel size W2/L2of the second driving transistor DRT2of the second subpixel SP2, current driving ability of the first driving transistor DRT1may be the same as or similar to current driving ability of the second driving transistor DRT2. In this case, the trench structure and the anode structure in the area of the first subpixel SP1may be the same as or similar to the trench structure and the anode structure in the area of the second subpixel SP2.

When the channel size W1/L1of the first driving transistor DRT1of the first subpixel SP1is different from the channel size W2/L2of the second driving transistor DRT2of the second subpixel SP2, current driving ability of the first driving transistor DRT1may be different from current driving ability of the second driving transistor DRT2. In this case, the trench structure and the anode structure in the area of the first subpixel SP1may be different from the trench structure and the anode structure in the area of the second subpixel SP2.

Hereinafter, for example, in a situation in which the channel size W1/L1of the first driving transistor DRT1of the first subpixel SP1is smaller than the channel size W2/L2of the second driving transistor DRT2of the second subpixel SP2, the trench structure and the anode structure in the area of the first subpixel SP1and the trench structure and the anode structure in the area of the second subpixel SP2will be described.

The first trench TRC1and the second trench TRC2may have the same structure, and the third trench TRC3and the fourth trench TRC4may have the same structure. Thus, the trench structure and the anode structure of the overcoat layer OC in the area of the first subpixel SP1will be described using the first trench TRC1, and the trench structure and the anode structure of the overcoat layer OC in the area of the second subpixel SP2will be described using the third trench TRC3.

Referring toFIGS.15and16, in a situation in which the first subpixel SP1is a subpixel to which the SPARP processing has been carried out and the second subpixel SP2is a subpixel to which the SPARP processing has not been carried out, the first wire part CL1may be disconnected inside the first trench TRC1of the overcoat layer OC, and the second wire part CL2may not be disconnected inside the third trench TRC3of the overcoat layer OC.

FIGS.17to19illustrate an example of a trench structure in the first subpixel SP1and an example of a trench structure in the second subpixel SP2in the display device100according to embodiments.

Referring toFIGS.17and18, the first wire part CL1of first anode AE1may be disposed over the overcoat layer OC, and may include the first bend BL1bent along the first inner side surface SIDE1a, the bottom surface BOT1, and the second inner side surface SIDE1bof the first trench TRC1. The second wire part CL2of the second anode AE2may include a third bend BL3disposed over the overcoat layer OC, and bent along the first inner side surface SIDE1a, the bottom surface BOT1, and the second inner side surface SIDE1bof the third trench TRC3.

Referring toFIGS.17to19, the channel size W1/L1of the first driving transistor DRT1in the first subpixel SP1may be smaller than the channel size W2/L2of the second driving transistor DRT2in the second subpixel SP2. Thus, the second driving transistor DRT2may have greater current driving ability than the first driving transistor DRT1, and drive greater current to flow through the second anode AE2. In contrast, the first driving transistor DRT1may have smaller current driving ability than the second driving transistor DRT2, and drive smaller current to flow through the first anode AE1.

Referring toFIG.17, since the channel size W1/L1of the first driving transistor DRT1is smaller than the channel size W2/L2of the second driving transistor DRT2, the width Wt1of the first trench TRC1may be narrower than the width Wt2of the third trench TRC3.

Since the channel size W1/L1of the first driving transistor DRT1is relatively small, the amount of normal driving current that the first driving transistor DRT1drives to flow may be relatively small. Thus, the width Wt1of the first trench TRC1may be designed to be relatively narrow so that the first trench TRC1can be easily disconnected by small aging current caused by the reverse bias processing in the SHARP processing.

Referring toFIG.18, since the channel size W1/L1of the first driving transistor DRT1is smaller than the channel size W2/L2of the second driving transistor DRT2, the depth Dt1of the first trench TRC1may be deeper than the depth Dt2of the third trench TRC3.

Since the channel size W1/L1of the first driving transistor DRT1is relatively small, the amount of normal driving current that the first driving transistor DRT1drives to flow may be relatively small. Thus, the depth Dt1of the first trench TRC1may be designed to be relatively deep so that the first trench TRC1can be easily disconnected by small aging current caused by the reverse bias processing in the SHARP processing.

Referring toFIG.19, since the channel size W1/L1of the first driving transistor DRT1is smaller than the channel size W2/L2of the second driving transistor DRT2, the width WL1of the first wire part CL1may be narrower than the width WL2of the second wire part CL2.

Since the channel size W1/L1of the first driving transistor DRT1is relatively small, the amount of normal driving current that the first driving transistor DRT1drives to flow may be relatively small. Thus, the width Wt1of the first wire part CL1may be designed to be relatively narrow so that the first wire part CL1can be easily disconnected by small aging current caused by the reverse bias processing in the SHARP processing.

FIGS.20to22illustrates examples of the relationship between the connecting wire structure of the first subpixel SP1and the connecting wire structure of the second subpixel SP2and the relationship between the trench structure of the first subpixel SP1and the trench structure of the second subpixel SP2.

Referring toFIG.20, when the width WO of the first trench TRC1is narrower than the width Wt2of the third trench TRC3or the depth DO of the first trench TRC1is deeper than the depth Dt2of the third trench TRC3, the width WL1of the first wire part CL1of first anode AE1may be wider than the width WL2of the second wire part CL2of the second anode AE2.

Referring toFIG.20, when the width Wt2of the third trench TRC3is wider than the width Wt1of the first trench TRC1or the depth Dt2of the third trench TRC3is shallower than the depth Dt1of the first trench TRC1, the width WL2of the second wire part CL2of the second anode AE2may be narrower than the width WL1of the first wire part CL1of first anode AE1.

Regarding the structure ofFIG.20, the width WO of the first trench TRC1may be narrower than the width Wt2of the third trench TRC3or the depth DO of the first trench TRC1is deeper than the depth Dt2of the third trench TRC3. Thus, the amount of driving current flowing through the first wire part CL1of first anode AE1may be reduced. However, since the width WL1of the first wire part CL1of first anode AE1is designed to the wider than the width WL2of the second wire part CL2of the second anode AE2, the amount of driving current flowing through the first wire part CL1of first anode AE1can be increased, thereby compensating for a decrease in the driving current.

Referring toFIG.21, the channel size W1/L1of the first driving transistor DRT1may be different from the channel size W2/L2of the second driving transistor DRT2. Even in this situation, the width WL1of the first wire part CL1may be the same as the width WL2of the second wire part CL2.

However, the width Wt1of the first trench TRC1may be different from the width Wt2of the third trench TRC3, or the depth DO of the first trench TRC1may be different from the depth Dt2of the third trench TRC3. For example, the width Wt1of the first trench TRC1may be narrow than the width Wt2of the third trench TRC3, or the depth Dt1of the first trench TRC1may be deeper than the depth Dt2of the third trench TRC3.

According to the structure ofFIG.21, even in the case that the width WL1of the first wire part CL1and the width WL2of the second wire part CL2are the same, the first wire part CL1can be caused to be easily disconnected inside the first trench TRC1by a small amount of aging current by setting the width Wt1of the first trench TRC1to be narrower than the width Wt2of the third trench TRC3or the depth Dt1of the first trench TRC1to be deeper than the depth Dt2of the third trench TRC3.

Referring toFIG.22, the channel size W1/L1of the first driving transistor DRT1may be different from the channel size W2/L2of the second driving transistor DRT2. In this case, the width WL1of the first wire part CL1may be different from the width WL2of the second wire part CL2. For example, the width WL1of the first wire part CL1may be narrower than the width WL2of the second wire part CL2.

However, the width WO of the first trench TRC1may be the same as the width Wt2of the third trench TRC3, or the depth DO of the first trench TRC1may be the same as the depth Dt2of the third trench TRC3.

According to the structure ofFIG.22, even in the case that the width WO of the first trench TRC1is the same as the width Wt2of the third trench TRC3or the depth DO of the first trench TRC1is the same as the depth Dt2of the third trench TRC3, the first wire part CL1can be caused to be easily disconnected inside the first trench TRC1by a small amount of aging current by designing the width WL1of the first wire part CL1to be narrower than the width WL2of the second wire part CL2.

FIG.23is a plan diagram illustrating an area in which four subpixels SP1, SP2, SP3, and SP4are disposed when the display device100according to embodiments is a transparent display, andFIG.24is a cross-sectional diagram illustrating the A-A′ area ofFIG.23in which a self-cutting enabled structure (i.e., a trench structure) of a first anode AE1inFIG.23is positioned.

Referring toFIG.23, the display device100according to embodiments may be a transparent display. The display device100according to embodiments may include transmission areas TA and non-transmission areas. The non-transmission areas may be areas in which the subpixels SP1, SP2, SP3, and SP4are disposed, emission areas of the subpixels SP1, SP2, SP3, and SP4, or areas in which pixel driver circuits SPC of the subpixels SP1, SP2, SP3, and SP4are disposed. The transmittance of the transmission areas may be equal to or higher than a predetermined or selected threshold transmittance.

Referring toFIG.23, for example, the four subpixels SP1, SP2, SP3, and SP4may be disposed in two columns, and the transmission areas TA may be disposed on both sides of the four subpixels SP1, SP2, SP3, and SP4.

Referring toFIG.23, the anode electrode AE of each of the four subpixels SP1, SP2, SP3, and SP4may have the same self-cutting enabled structure as described above.

The first anode AE1of the first subpixel SP1may include the first electrode part PAE1, the second electrode part PAE2, and the first wire part CL1. The second anode AE2of the second subpixel SP2may include the third electrode part PAE3, the fourth electrode part PAE4, and the second wire part CL2. A third anode AE3of the third subpixel SP3may include a fifth electrode part PAE5, a sixth electrode part PAE6, and a third wire part CL3. A fourth anode AE4of the fourth subpixel SP4may include a seventh electrode part PAE7, an eighth electrode part PAE8, and a fourth wire part CL4.

A transmission area TA may be positioned on one side of the first subpixel SP1, and the first wire part CL1may be disposed to intrude into a portion of the transmission area TA. The first wire part CL1may extend across at least one trench TRC of the overcoat layer OC. An organic material OM may be disposed inside or around the at least one trench TRC, and the first wire part CL1may be disposed on the organic material OM. The first wire part CL1may be connected to the driving transistor DRT of the first subpixel SP1through a contact hole CNT.

A transmission area TA may be positioned on one side of the second subpixel SP2, and the second wire part CL2may be disposed to intrude into a portion of the transmission area TA. The second wire part CL2may extend across at least one trench TRC of the overcoat layer OC. An organic material OM may be disposed inside or around the at least one trench TRC, and the second wire part CL2may be disposed on the organic material OM. The second wire part CL2may be connected to the driving transistor DRT of the second subpixel SP2through a contact hole CNT.

A transmission area TA may be positioned on one side of the third subpixel SP3, and the third wire part CL3may be disposed to intrude into a portion of the transmission area TA. The third wire part CL3may extend across at least one trench TRC of the overcoat layer OC. An organic material OM may be disposed inside or around the at least one trench TRC, and the third wire part CL3may be disposed on the organic material OM. The third wire part CL3may be connected to the driving transistor DRT of the third subpixel SP3through a contact hole CNT.

A transmission area TA may be positioned on one side of the fourth subpixel SP4, and the fourth wire part CL4may be disposed to intrude into a portion of the transmission area TA. The fourth wire part CL4may extend across at least one trench TRC of the overcoat layer OC. An organic material OM may be disposed inside or around the at least one trench TRC, and the fourth wire part CL4may be disposed on the organic material OM. The fourth wire part CL4may be connected to the driving transistor DRT of the fourth subpixel SP4through a contact hole CNT.

Referring toFIG.24, the A-A′ area nay be a portion of the area in which the first wire part CL1of first anode AE1, included in the first subpixel SP1, is disposed. The A-A′ area may be an area in which the self-cutting enabled structure (i.e., the trench structure) of the first anode AE1is positioned.

Referring toFIG.24, a passivation film PAS may be disposed to cover the first drain electrode D1and the first source electrode S1of the first driving transistor DRT1in the first subpixel SP1. The cross-sectional structure including from the substrate SUB to the first driving transistor DRT1is the same as that described above with reference toFIG.15.

Referring toFIGS.23to24, the overcoat layer OC may be disposed over the passivation film PAS. The overcoat layer OC may include a first trench TRC1formed at a position corresponding to the first cutting point CP1and a second trench TRC2formed at a position corresponding to the second cutting point CP2. The second organic material OM2may be disposed inside and outside the second trench TRC2.

The first anode AE1may include the first electrode part PAE1, the second electrode part PAE2, and the first wire part CL1. The first wire part CL1of first anode AE1may include a first connecting portion connected to the first electrode part PAE1, a second connecting portion connected to the second electrode part PAE2, and a link portion between the first connecting portion and the second connecting portion. The link portion of the first wire part CL1may pass across the first trench TRC1and the second trench TRC2.

The portion of the link portion of the first wire part CL1passing across the second trench TRC2may be disposed along the inner side surfaces and the bottom surface of the second trench TRC2. In addition, the portion of the link portion of the first wire part CL1passing across the second trench TRC2may be disposed on the second organic material OM2disposed inside and outside the trench TRC2.

The link portion of the first wire part CL1may be electrically connected to the first node N1corresponding to the first source electrode S1of the first driving transistor DRT1through the contact hole CNT in the overcoat layer OC.

A bank BK may be disposed on the first anode AE1The bank BK may have open areas corresponding to the emission areas of the first subpixel SP1. Here, the emission areas of the first subpixel SP1may match the position of the first electrode part PAE1and the position of the second electrode part PAE2. The positions of the open areas in the bank BK may match the positions of the first electrode part PAE1and the second electrode part PAE2of the first anode AE1.

The first emitting layer EL1may be disposed on the bank BK. In each of the open areas of the bank BK, the first emitting layer EL1may be disposed on the first electrode part PAE1and the second electrode part PAE2. The cathode CE may be disposed on the first emitting layer EL1, an encapsulation layer ENCAP may be disposed over the cathode CE, a black matrix BM and a color filter CF may be disposed on portions of the encapsulation layer ENCAP, and a top substrate TOP_SUB may be disposed over the black matrix BM, the color filter CF, and the remaining portion of the encapsulation layer ENCAP not covered with the black matrix BM or the color filter CF.

The insulating layers BUF, ILD, and PAS may be disposed in the transmission area TA, and no metal layers may be disposed in the transmission area TA. Here, since the cathode CE is a transparent cathode formed of a transparent conductive film, the cathode CE may be disposed in the transmission area TA. An emitting layer EL may be disposed in the transmission area TA.