Relay mechanism to facilitate processor communication with inaccessible input/output (I/O) device

A method includes transmitting, by a first processing device, a signal to a second relay processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The method also includes receiving, by the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

TECHNICAL FIELD

This disclosure is generally directed to computing devices. More specifically, this disclosure is directed to a relay mechanism to facilitate processor communication with an inaccessible input/output (I/O) device.

BACKGROUND

Computing devices routinely need to communicate with input/output (I/O) devices in an industrial process control and automation system. However, some computing devices in an industrial process control and automation system may not be able to communicate with various I/O devices, such as when older I/O devices are not electrically or logically accessible by newer computing devices. As a particular example, there may be a need in some circumstances for a particular computing device to interact with a specific I/O device, but the computing device may not be able to access the I/O device because of board design issues or other problems.

SUMMARY

This disclosure relates to a relay mechanism to facilitate processor communication with an inaccessible input/output (I/O) device.

In a first embodiment, a method includes transmitting, by a first processing device, a signal to a second relay processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The method also includes receiving, by the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

In a second embodiment, an apparatus includes a first processing device configured to transmit a signal to a second relay processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The first processing device is also configured to receive an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

In a third embodiment, a method includes receiving a signal from a first processing device at a second relay processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The method also includes transmitting, from the second relay processing device, the read command and/or the write command to the I/O device. The method further includes transmitting, to the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

In a fourth embodiment, an apparatus for use with a first processing device includes a second relay processing device configured to receive a signal from the first processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The second relay processing device is also configured to transmit the read command and/or the write command to the I/O device. The second relay processing device is further configured to transmit, to the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

DETAILED DESCRIPTION

FIG. 1illustrates an example industrial process control and automation system100according to this disclosure. As shown inFIG. 1, the system100includes various components that facilitate production or processing of at least one product or other material. For instance, the system100is used here to facilitate control over components in one or multiple plants102a-102n. Each plant102a-102nrepresents one or more processing facilities (or one or more portions thereof), such as one or more manufacturing facilities for producing at least one product or other material. In general, each plant102a-102nmay implement one or more processes and can individually or collectively be referred to as a process system. A process system generally represents any system or portion thereof configured to process one or more products or other materials in some manner.

InFIG. 1, the system100is implemented using the Purdue model of process control. In the Purdue model, “Level 0” may include one or more input/output (I/O) devices104a-104b. The I/O devices104a-104brepresent components in a process system that may perform any of a wide variety of functions. The I/O devices104a-104bcan include sensors, actuators, or the like. Sensors can measure a wide variety of characteristics in the process system, such as temperature, pressure, or flow rate. Actuators can alter a wide variety of characteristics in the process system. Sensors include any suitable structure for measuring one or more characteristics in a process system. Actuators include any suitable structure for operating on or affecting one or more conditions in a process system. The I/O devices104a-104bcould represent any other or additional components in any suitable process system.

In the Purdue model, “Level 1” may include at least two controllers106a-106b. Among other things, each controller106a-106bmay use the measurements from one or more I/O devices (such as one or more sensors) to control the operation of one or more other I/O devices (such as one or more actuators). Each controller106a-106bincludes any suitable structure for interacting with one or more I/O devices104a-104b. Each controller106a-106bcould, for example, represent a proportional-integral-derivative (PID) controller or a multivariable controller, such as a Robust Multivariable Predictive Control Technology (RMPCT) controller or other type of controller implementing model predictive control (MPC) or other advanced predictive control (APC). As a particular example, each controller106a-106bcould represent a computing device running a real-time operating system.

Two networks108are coupled to the controllers106a-106b. The networks108facilitate interaction with the controllers106a-106b, such as by transporting data to and from the controllers106aand106a. The networks108could represent any suitable networks or combination of networks. As a particular example, the networks108could represent a redundant pair of Ethernet networks, such as a FAULT TOLERANT ETHERNET (FTE) network from HONEYWELL INTERNATIONAL INC.

At least one switch/firewall110couples the networks108to two networks112. The switch/firewall110may transport traffic from one network to another. The switch/firewall110may also block traffic on one network from reaching another network. The switch/firewall110includes any suitable structure for providing communication between networks, such as a HONEYWELL CONTROL FIREWALL (CF9) device. The networks112could represent any suitable networks, such as an FTE network.

In the Purdue model, “Level 2” may include one or more machine-level controllers114coupled to the networks112. The machine-level controllers114perform various functions to support the operation and control of the controllers106a-106band I/O devices104a-104b, which could be associated with a particular piece of industrial equipment (such as a boiler or other machine). For example, the machine-level controllers114could log information collected or generated by the controllers106a-106b, such as measurement data from the sensors or control signals for the actuators. The machine-level controllers114could also execute applications that control the operation of the controllers106a-106b, thereby controlling the operation of the I/O devices104a-104b. In addition, the machine-level controllers114could provide edge access to the controllers106a-106b. Each of the machine-level controllers114includes any suitable structure for providing access to, control of, or operations related to a machine or other individual piece of equipment. Each of the machine-level controllers114could, for example, represent a server computing device running a MICROSOFT WINDOWS operating system. Although not shown, different machine-level controllers114could be used to control different pieces of equipment in a process system (where each piece of equipment is associated with one or more controllers106a-106bas well as I/O devices104a-104b).

One or more operator stations116are coupled to the networks112. The operator stations116represent computing or communication devices providing user access to the machine-level controllers114, which could then provide user access to the controllers106a-106b(and possibly the I/O devices104a-104b). As particular examples, the operator stations116could allow users to review the operational history of the I/O devices104a-104busing information collected by the controllers106a-106band/or the machine-level controllers114. The operator stations116could also allow the users to adjust the operation of the I/O devices104a-104b, controllers106a-106b, or machine-level controllers114. In addition, the operator stations116could receive and display warnings, alerts, or other messages or displays generated by the controllers106a-106bor the machine-level controllers114. Each of the operator stations116includes any suitable structure for supporting user access and control of one or more components in the system100. Each of the operator stations116could, for example, represent a computing device running a MICROSOFT WINDOWS operating system.

At least one router/firewall118couples the networks112to two networks120. The router/firewall118includes any suitable structure for providing communication between networks, such as a secure router or combination router/firewall. The networks120could represent any suitable networks, such as an FTE network.

In the Purdue model, “Level 3” may include one or more unit-level controllers122coupled to the networks120. Each unit-level controller122is typically associated with a unit in a process system, which represents a collection of different machines operating together to implement at least part of a process. The unit-level controllers122perform various functions to support the operation and control of components in the lower levels. For example, the unit-level controllers122could log information collected or generated by the components in the lower levels, execute applications that control the components in the lower levels, and provide secure access to the components in the lower levels. Each of the unit-level controllers122includes any suitable structure for providing access to, control of, or operations related to one or more machines or other pieces of equipment in a process unit. Each of the unit-level controllers122could, for example, represent a server computing device running a MICROSOFT WINDOWS operating system. Although not shown, different unit-level controllers122could be used to control different units in a process system (where each unit is associated with one or more machine-level controllers114, controllers106a-106b, and I/O devices104a-104b).

Access to the unit-level controllers122may be provided by one or more operator stations124. Each of the operator stations124includes any suitable structure for supporting user access and control of one or more components in the system100. Each of the operator stations124could, for example, represent a computing device running a MICROSOFT WINDOWS operating system.

At least one router/firewall126couples the networks120to two networks128. The router/firewall126includes any suitable structure for providing communication between networks, such as a secure router or combination router/firewall. The networks128could represent any suitable networks, such as an FTE network.

In the Purdue model, “Level 4” may include one or more plant-level controllers130coupled to the networks128. Each plant-level controller130is typically associated with one of the plants102a-102n, which may include one or more process units that implement the same, similar, or different processes. The plant-level controllers130perform various functions to support the operation and control of components in the lower levels. As particular examples, the plant-level controller130could execute one or more manufacturing execution system (MES) applications, scheduling applications, or other or additional plant or process control applications. Each of the plant-level controllers130includes any suitable structure for providing access to, control of, or operations related to one or more process units in a process plant. Each of the plant-level controllers130could, for example, represent a server computing device running a MICROSOFT WINDOWS operating system.

Access to the plant-level controllers130may be provided by one or more operator stations132. Each of the operator stations132includes any suitable structure for supporting user access and control of one or more components in the system100. Each of the operator stations132could, for example, represent a computing device running a MICROSOFT WINDOWS operating system.

At least one router/firewall134couples the networks128to one or more networks136. The router/firewall134includes any suitable structure for providing communication between networks, such as a secure router or combination router/firewall. The network136could represent any suitable network, such as an enterprise-wide Ethernet or other network or all or a portion of a larger network (such as the Internet).

In the Purdue model, “Level 5” may include one or more enterprise-level controllers138coupled to the network136. Each enterprise-level controller138is typically able to perform planning operations for multiple plants102a-102nand to control various aspects of the plants102a-102n. The enterprise-level controllers138can also perform various functions to support the operation and control of components in the plants102a-102n. As particular examples, the enterprise-level controller138could execute one or more order processing applications, enterprise resource planning (ERP) applications, advanced planning and scheduling (APS) applications, or any other or additional enterprise control applications. Each of the enterprise-level controllers138includes any suitable structure for providing access to, control of, or operations related to the control of one or more plants. Each of the enterprise-level controllers138could, for example, represent a server computing device running a MICROSOFT WINDOWS operating system. In this document, the term “enterprise” refers to an organization having one or more plants or other processing facilities to be managed. Note that if a single plant102ais to be managed, the functionality of the enterprise-level controller138could be incorporated into the plant-level controller130.

Access to the enterprise-level controllers138may be provided by one or more operator stations140. Each of the operator stations140includes any suitable structure for supporting user access and control of one or more components in the system100. Each of the operator stations140could, for example, represent a computing device running a MICROSOFT WINDOWS operating system.

Various levels of the Purdue model can include other components, such as one or more databases. The database(s) associated with each level could store any suitable information associated with that level or one or more other levels of the system100. For example, a historian141can be coupled to the network136. The historian141could represent a component that stores various information about the system100. The historian141could, for instance, store information used during production scheduling and optimization. The historian141represents any suitable structure for storing and facilitating retrieval of information. Although shown as a single centralized component coupled to the network136, the historian141could be located elsewhere in the system100, or multiple historians could be distributed in different locations in the system100.

In particular embodiments, the various controllers and operator stations inFIG. 1may represent computing devices. For example, each of the controllers106a,106b,114,122,130, and138could include one or more processing devices142and one or more memories144for storing instructions and data used, generated, or collected by the processing device(s)142. Each of the controllers106a,106b,114,122,130, and138could also include at least one network interface146, such as one or more Ethernet interfaces or wireless transceivers. Also, each of the operator stations116,124,132, and140could include one or more processing devices148and one or more memories150for storing instructions and data used, generated, or collected by the processing device(s)148. Each of the operator stations116,124,132, and140could also include at least one network interface152, such as one or more Ethernet interfaces or wireless transceivers.

As noted above, there may be some instances where a specific computing device in the industrial process control and automation system100cannot interact directly with a particular I/O device. As examples, the controller106amay not be able to communicate directly with the I/O device104a, or the controller106bmay not be able to communicate directly with the I/O device104b. This can arise for any number of reasons, such as the design of the controller(s) or I/O device(s).

In accordance with this disclosure, a controller or other computing device can be supplied with at least one relay processor, which can be placed in communication with at least one primary processor of the computing device. The relay processor can also be placed in communication with an I/O device that is otherwise electrically or logically inaccessible to the primary processor. As particular examples, the controller106acould include a relay processor facilitating communication with the I/O device104a, or the controller106bcould include a relay processor facilitating communication with the I/O device104b. As a result, the controller106ais able to interact with the I/O device104a, or the controller106bis able to interact with the I/O device104b.

In some embodiments, the primary and relay processors support a communication protocol that is used to share data between the processors. For example, the relay processor can be configured to write data to and read data from an I/O device. When the primary processor needs access to the I/O device, the primary processor can transmit a signal to the relay processor directing the relay processor to transmit a command (such as a read or write command) to the I/O device. This enables the primary processor to utilize the relay processor as a proxy to write data to or receive data from the I/O device, even though the primary processor is not able to electrically or logically access the I/O device.

The specific interactions between the primary and relay processors can vary depending on the functions being supported in the system100. For example, when an I/O device represents a sensor, the primary processor could use the relay processor as a proxy to obtain measurement data from the sensor. When an I/O device represents an actuator, the primary processor could use the relay processor as a proxy to provide control data to the actuator. Any other suitable interacts and data transfers could be supported between processors to support a relay with an I/O device.

There are various approaches to supporting communication between the primary and relay processors. For example, a shared memory that is accessible by both processors could be provided, and the shared memory could reside within or be external to the computing device. Any suitable mechanism could also be used to help reduce or prevent simultaneous access to the same memory location by both processors.

The communication protocol used by the processors can define whether a read or write operation is to be performed. In the case of a write operation, the communication protocol can define the data to be written. In the case of a read operation, the communication protocol can provide newly-read data in an agreed-upon memory location. Such a communication protocol can also provide a “return status,” which indicates whether a request is still in progress or if the request has completed. The return status may also indicate the success or failure of the operation. The relay processor, in its role as proxy, can periodically or continuously examine a shared memory area for any new requests. The primary processor can monitor the shared memory area in order to determine when new requests can be made or to determine when an existing request has completed.

A particular example of this functionality involves the addition of a circuit card to a controller106aor106b. The circuit card can contain both an unused processor and a gate array. The gate array can contain logic to drive an I/O path onto a communications network. For instance, the circuit card could denote an LCNP4E circuit card from HONEYWELL INTERNATIONAL INC., which is ordinarily used to provide a network path to a Local Control Network (LCN) in an industrial process control and automation system. This circuit card could include a processor (such as a MOTOROLA 68040 processor) that is not needed for normal communications over the LCN. The card is placed into the controller in order to give the card access to the communication medium used by the controller. However, the primary processor of the controller may be unable to access the gate array, such as due to the absence of any direct path to the gate array's memory. The unused processor on the circuit card of the controller could therefore be used as a relay processor. Here, the primary processor of the controller requests that the otherwise unused processor act as a relay, performing its desired I/O operations in the gate array as a proxy for the primary processor. After the desired operations are completed, the proxy informs the primary processor of the results, including any data that was newly read.

AlthoughFIG. 1illustrates one example of an industrial process control and automation system100, various changes may be made toFIG. 1. For example, the system100could include any number of sensors, actuators, controllers, servers, operator stations, networks, and other components. Also, the makeup and arrangement of the system100inFIG. 1is for illustration only. Components could be added, omitted, combined, or placed in any other suitable configuration according to particular needs. Further, particular functions have been described as being performed by particular components of the system100. This is for illustration only. In general, control and automation systems are highly configurable and can be configured in any suitable manner according to particular needs. In addition,FIG. 1illustrates one example operational environment in which a relay mechanism to facilitate processor communication with an inaccessible I/O device can be used. This functionality can be used in any other suitable system.

FIG. 2illustrates an example computing device200facilitating processor communication with an inaccessible I/O device according to this disclosure. The computing device200shown inFIG. 2could, for example, denote either of the controllers106a-106bshown inFIG. 1and described above. Note, however, that the controllers106a-106bcould be implemented in any other suitable manner.

As shown inFIG. 2, the computing device200includes a bus system202, which supports communication between at least one processing device204, at least one storage device206, at least one communications unit208, and at least one I/O unit210.

The processing device204executes instructions that may be loaded into a memory212. The processing device204may include any suitable number(s) and type(s) of processors or other devices in any suitable arrangement. Example types of processing devices204include microprocessors, microcontrollers, digital signal processors, field programmable gate arrays, application specific integrated circuits, and discreet circuitry. Using the terminology above, the processing device204could be said to represent the “primary” processor of the device200.

The memory212and a persistent storage214are examples of storage devices206, which represent any structure(s) capable of storing and facilitating retrieval of information (such as data, program code, and/or other suitable information on a temporary or permanent basis). The memory212may represent a random access memory or any other suitable volatile or non-volatile storage device(s). The persistent storage214may contain one or more components or devices supporting longer-term storage of data, such as a read only memory, hard drive, Flash memory, or optical disc.

The communications unit208supports communications with other systems or devices. For example, the communications unit208could include a network interface card or a wireless transceiver facilitating communications over a network. The communications unit208may support communications through any suitable physical or wireless communication link(s).

The I/O unit210allows for input and output of data. For example, the I/O unit210may provide a connection for user input through a keyboard, mouse, keypad, touchscreen, or other suitable input device. The I/O unit210may also send output to a display, printer, or other suitable output device. In addition, the I/O unit210can support communications and interactions with I/O devices, such as one or more I/O devices104aor104b.

As noted above, at least one relay processing device216can be used to support communications between the processing device204and at least one I/O device that is otherwise inaccessible to the processing device204. In particular, the relay processing device216can access the I/O device and function as a relay to provide information to or receive information from the processing device204. For example, at least one relay processing device216and at least one I/O unit210could reside on a circuit card that can be coupled to the device200. The processing devices204and216can be configured to support a communication protocol that is used to share data between the processing devices. For instance, the communication protocol may allow the processing device204to request that the relay processing device216perform a read or write operation involving an I/O device, where the processing device204lacks access to the I/O device. The communication protocol may also allow the relay processing device216to return information about the requested operation, such as an acknowledgement of a successful write operation or newly-read data for a successful read operation. Depending on whether a shared memory is used, the processing devices204and216may also support access to and use of the shared memory, such as within the memory212or persistent storage214.

AlthoughFIG. 2illustrates one example of a computing device200facilitating processor communication with an inaccessible I/O device, various changes may be made toFIG. 2. For example, computing devices can come in a wide variety of configurations. The computing device shown inFIG. 2is meant to illustrate one example implementation and does not limit this disclosure to a particular type of computing device.

FIG. 3illustrates a specific example of a computing device300facilitating processor communication with an inaccessible I/O device according to this disclosure. As shown inFIG. 3, this specific example of the computing device300includes an emulation architecture302running in conjunction with computing hardware304. The computing device300also includes an interface card306, which facilitates access to an LCN308via a media access unit (MAU)310. The computing hardware304here includes various device interfaces312, such as a small computer system interface (SCSI), a HONEYWELL PDG video interface, an LCN interface (LCNI), and a work station interface (WSI). The computing hardware304also includes at least one register314used to store information associated with interrupts generated by the computing hardware304. Note, however, that the computing hardware304could include any other or additional interfaces or memories.

The emulation architecture302includes an emulation framework that is used to emulate a specific type of processor (a 68040 processor in this example) on another type of processor (such as an INTEL x86 processor). The framework includes a kernel emulator316, an instruction emulator318, and an I/O emulator320. As the names imply, the kernel emulator316is used to emulate so-called kernel functions (compute functions not typically performed by a main processor, examples of which are named below). Also, the instruction emulator318is used to emulate the execution of instructions on a processor, and the I/O emulator320is used to emulate input and output operations on a processor. The kernel emulator316could include various types of emulations depending on the specific kernel being emulated. For example, the kernel emulator316could include a universal asynchronous receiver/transmitter (UART) emulator and a clock emulator for the 68040 processor. The instruction emulator318is used to implement various instructions that are not executed within the kernel emulator316. For instance, the instruction emulator318can be used to execute various instructions in legacy source code in order to emulate the execution of the legacy source code on the 68040 processor. In some embodiments, the instruction emulator318could denote an instruction emulator from MICROAPL LTD.

The interface card306in this example includes a gate array322and a memory324. The gate array322functions to provide physical connection to an external network, in this case an LCN. The memory324is used to store data flowing through the interface card306. The gate array322includes any suitable circuitry providing connection to an external network. The memory324includes any suitable structure for storing and facilitating retrieval of information, such as a dynamic random access memory (DRAM). The interface card306also includes a relay processor326, which as described above functions as a relay between a primary processor (which is executing the emulation architecture302) and the interfaces312. In this particular example, the relay processor326provides access to I/O devices via the four interfaces312described above (LCNI, SCSI, PDG, and WSI), although the relay processor326could provide access to any suitable I/O devices via any suitable interfaces.

In this example, the I/O emulator320includes multiple relays328that function to direct communications to and from the interfaces312via the relay processor326. Each type of interface312can have its own relay328so that programs executing as part of the emulation architecture302can access the interfaces312via the relays328without any knowledge that the interfaces312may actually be inaccessible through normal communications.

The emulators316-320communicate and exchange access notifications and interrupt notifications. An access notification is used to indicate that one emulator needs to access data or other information associated with another emulator. An interrupt notification is used by one emulator to inform another emulator that an interrupt has occurred so that the other emulator can take suitable action in response to the interrupt. An interrupt monitoring thread330is used here to scan for interrupts from the computing hardware304and to provide additional interrupt notifications to the emulator318.

One or more shared memories332a-332bcan be used to support the transport of data between various components of the computing device300inFIG. 3. Each shared memory332a-332bdenotes any suitable structure capable of storing data. While shown as separate memories here, the shared memories332a-332bcould denote different portions of a single memory device.

AlthoughFIG. 3illustrates one specific example of a computing device300facilitating processor communication with an inaccessible I/O device, various changes may be made toFIG. 3. For example, various components inFIG. 3could be combined, further subdivided, or omitted and additional components could be added according to particular needs. Also, whileFIG. 3illustrates one specific emulation involving an 68040 processor, any other suitable emulations involving different processors could also be supported.

FIGS. 4 and 5illustrate example methods for facilitating processor communication with an inaccessible I/O device according to this disclosure. In particular,FIG. 4illustrates an example method400used by a first processor (a primary processor) attempting to access an I/O device that is directly inaccessible by the first processor, andFIG. 5illustrates an example method500used by a second processor (a relay processor) acting as a proxy for the first processor. For ease of explanation, the methods400and500are described with respect to one of the controllers106a-106boperating in the system100ofFIG. 1, although the methods could be used with any other suitable devices and in any other suitable systems.

As shown inFIG. 4, a determination is made at a first processor that access to an I/O device is needed or desired at step402. This could include, for example, the processing device204of the controller106aor106bdetermining that read or write access to the I/O device104aor104bis needed, such as to execute control logic of the controller106aor106b.

The identified I/O device may not be electrically or logically accessible by the first processor. In that case, the first processor transmits a signal to a second processor that is able to access the I/O device at step404. This could include, for example, the processing device204in the controller106aor106btransmitting a signal to the relay processing device216that has access to the I/O device104aor104b. The first processor could identify the second processor as the proxy for the I/O device in any suitable manner, such as by using a table or other information stored at the first processor. The signal sent to the second processor could have any suitable contents depending on, for instance, whether the desired command is a read or write command.

An indication is received at the first processor that the second processor has transmitted a command to the I/O device at step406. This could include, for example, the processing device204receiving a return status indicating that a read or write command has been transmitted from the relay processing device216to the I/O device104aor104b. An indication is received at the first processor whether the command was successfully completed at step408. This could include, for example, the processing device204receiving a return status indicating whether the read or write command was successfully performed using the I/O device104aor104b. If needed, a shared memory is accessed to obtain results of the command at step410. This could include, for example, the processing device204accessing a shared memory location to obtain data read from the I/O device104aor104b. Note that the return status indicators could also be received via the shared memory.

At this point, the first processor can perform any desired function. For example, the first processor could use the obtained data to execute control logic. The first processor could also use the data to identify another I/O device to be accessed, either directly or indirectly via the same proxy processor or a different proxy processor.

As shown inFIG. 5, a second processor receives a signal from a first processor at step502. This could include, for example, the relay processing device216receiving a signal from the processing device204, where the relay processing device216has access to an I/O device104aor104bthat the processing device204wishes to access. In response, the second processor transmits a command to the I/O device on behalf of the first processor at step504. This could include, for example, the relay processing device216constructing a read or write command for the I/O device104aor104bbased on the signal received from the processing device204.

An indication is transmitted to the first processor that the second processor has transmitted a command to the I/O device at step506. This could include, for example, the relay processing device216providing a return status indicating that a read or write command has been transmitted from the relay processing device216to the I/O device104aor104b. An indication is transmitted to the first processor whether the command was successfully completed at step508. This could include, for example, the relay processing device216providing a return status indicating whether the read or write command was successfully performed using the I/O device104aor104b. If needed, a shared memory is accessed to store results of the command at step510. This could include, for example, the relay processing device216accessing a shared memory location to store data read from the I/O device104aor104b. Note that the return status indicators could also be provided via the shared memory.

AlthoughFIGS. 4 and 5illustrate examples of methods400and500for facilitating processor communication with an inaccessible I/O device, various changes may be made toFIGS. 4 and 5. For example, while shown as a series of steps, various steps shown in each figure could overlap, occur in parallel, occur in a different order, or occur multiple times. Moreover, some steps could be combined or removed and additional steps could be added according to particular needs.

Note that in the above description, the use of a relay processor is often described as providing access to an I/O device for a primary processor, where the primary and relay processors are associated with the same computing device (such as the same controller106aor106b). However, this need not be the case, and in other instances the primary and relay processors could form parts of different devices. For example, the primary processor in one controller106acould communicate with the relay processor in another controller106bto interact with the I/O device104b, or the primary processor in one controller106bcould communicate with the relay processor in another controller106ato interact with the I/O device104a. Suitable inter-device communications could be supported to allow processors in different devices to interact in this manner.