System and method for programming non-volatile memory

Circuitry for programming a non-volatile memory of an integrated circuit is disclosed. The circuitry requires only three pins: a power pin, a ground pin, and a data pin. Programming mode is initiated by coincidentally applying high voltages at the power pin and the data pin. The memory cells may be programmed individually in sequence, or all at once. A clock signal for selecting the memory cells is obtained through serial high voltage pulses applied to the power pin. The clock signal increments a state machine, which in turn causes one or more of the memory cells to be selected. Binary data is provided to the data pin, is stored, and is then provided to the memory cells. A high voltage pulse subsequently received at the data pin is passed to the memory cells, and causes the stored data to be programmed into the selected memory cell(s).

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to non-volatile memory integrated circuits, and in particular to a method and structure for programming a non-volatile memory integrated circuit.

2. Description of the Related Art

Some integrated circuits include a non-volatile memory composed of a plurality of non-volatile memory cells. Non-volatile memory retains data even after power to the memory is turned off. One common type of non-volatile memory is an EEPROM (Electrically Erasable Programmable Read-Only Memory).

In some applications, data may be written to, that is, programmed in, a non-volatile memory of an integrated circuit through externally-accessible pins of the integrated circuit. Typically, more than three pins are required to program a non-volatile memory. However, each such pin increases the size and cost of the integrated circuit. Accordingly, a need exists for a means by which a non-volatile memory can be programmed using as few pins as possible.

SUMMARY

The present invention includes circuits and methods for programming a non-volatile memory (e.g., an EEPROM) within an integrated circuit, using only three pins of the integrated circuit: (1) a power pin; (2) a data pin; and (3) a ground pin.

In one embodiment, an integrated circuit is provided that includes a non-volatile memory, and a programming circuit coupled to the non-volatile memory. The programming circuit comprises a power pin, a data pin, and a ground pin. A fixed-level nominal voltage is continuously applied to the power pin to power the integrated circuit. A programming mode is then initiated by applying a high voltage pulse to the power pin, and a high voltage pulse to the data pin while the aforementioned high voltage pulse is present on the power pin. After the programming mode is initiated, a series of high voltage pulses are provided on the power pin. The high voltage pulses are used to select sequential ones of the memory cells for programming. Binary data received at the data pin is temporarily stored in a latch or the like, and then is provided to the memory cells. A high voltage pulse subsequently received at the data pin is then provided to the non-volatile memory cells, and programs the stored binary data into the selected non-volatile memory cell, without programming the non-selected memory cells. The process repeats until all of the memory cells have been individually and sequentially selected and programmed. The programming mode may be exited by powering down the circuit.

In one embodiment, a method for programming the non-volatile memory cells includes simultaneously selecting all of the memory cells in response to a high voltage pulse received at the power pin, and then simultaneously programming all of the memory cells with binary data simultaneously provided to the memory cells.

These and other aspects of the present invention will become apparent in view of the detailed description, and the accompanying drawings, of the exemplary embodiments.

DETAILED DESCRIPTION

FIG. 1illustrates portions of an integrated circuit1, which includes: a plurality of non-volatile memory cells160(e.g., an EEPROM); a circuit100for programming the non-volatile memory cells160; and a circuit function block140. The circuit100includes at least three externally-accessible pins of integrated circuit1: a power pin102; a data pin104; and a ground pin106. Circuit function block140uses the data programmed into memory cells160. In one embodiment, circuit function block140allows integrated circuit1to function as a reset controller, as discussed below. However, the particular circuitry and function of circuit function block140may vary.

In one embodiment, integrated circuit1operates in two mutually-exclusive modes: (1) a programming mode, where memory cells160are programmed; and (2) a user mode, where circuit function block140operates.

The power pin102is coupled to an input of a power on reset device110and to an input of a high voltage detector112. As used herein, the terms “connected,” “coupled,” or variants thereof, mean any electrical connection or electrical coupling, either direct or indirect, between electrical elements.

During programming, power pin102is coupled to a first external power supply PS1that is capable of supplying a voltage signal V1having at least two voltage levels to power pin102. A first, lower voltage level of voltage signal V1, called the nominal voltage or “VNOM” herein, is the baseline voltage that powers circuit100, and is always provided to power pin102from power supply V1when circuit100is operating. A second, higher voltage level of voltage signal V1, called “VDDH” herein, is provided to power pin102from power supply PS1in the form of periodic, serial pulses. The high voltage VDDHpulses are used to create a clocking signal and to latch data within circuit100, as is discussed below. InFIG. 3, an example of voltage signal V1is shown on the top line of the timing chart.

During programming, data pin104is coupled to a second external power supply PS2that provides a voltage signal V2having a plurality of voltage levels to data pin104. Voltage signal V2includes low voltage levels corresponding to binary data, either logical zero or logical one, and high voltage pulses. The high voltage pulses are at a voltage level, called “VHH” herein, that is greater than the binary data voltage level and is sufficient to program the memory cells160. The high voltage VHHpulses received through the data pin104are ultimately used within circuit100to program binary data previously received through the data pin104into one or more selected non-volatile memory cells160. In the present embodiment, the high voltage VHHpulses received at the data pin104via voltage signal V2are at a voltage level that is greater than the high voltage VDDHpulses received at power pin102via voltage signal V1. For example, VNOMmay be 5 V, VDDHmay be 7.5-8 V, and VHHmay be 15-18 V. The specific values will vary with the application. InFIG. 3, an example of voltage signal V2is shown on the second line from the top of the timing chart.

Ground pin106is coupled to a ground voltage source (0 V) during programming.

An external programming device (not shown) that is coupled to power supplies PS1and PS2and to circuit100of integrated circuit1is used to program the non-volatile memory cells160. Such a programming device typically includes an electrical socket into which the integrated circuit1may be inserted, and a controller, such as a processor or personal computer running appropriate software. The controller controls: (1) the provision of voltage signal V1, including the nominal voltage VNOMand the serial high voltage VDDHpulses, from power supply PS1to power pin102; (2) the provision of voltage signal V2, including the binary data and high voltage VHHpulses, to the data pin104; and (3) the provision of the ground voltage (0 V) to the ground pin106. The programming device may be part of a larger external device that tests other aspects of the operation of the integrated circuit1.

The power on reset device110generates a power on reset signal POR at node114in response to detecting power being applied at the power pin102. In particular, the power on reset device110provides the power on reset signal POR at the node114upon detecting an initial voltage from the power supply PS1at the power pin102. The power on reset signal POR is provided until the voltage at the power pin102reaches a predetermined level and a specified time expires, after which the power on reset signal POR is removed from the node114. As discussed in more detail below, the programming control circuitry120receives the power on reset signal POR from the power on reset device110and uses the power on reset signal POR to reset internal components.

An input of the high voltage detector112is also connected to the power pin102. The high voltage detector112outputs a power pin high voltage signal VDH at node116upon detecting a high voltage (i.e., something greater than VNOM) at the power pin102via voltage signal V1. In one embodiment, the high voltage detector112outputs a power pin high voltage signal VDH having logic “high” or “1” when the voltage at the power pin102is above a predetermined voltage level. The high voltage detector112outputs a power pin high voltage signal VDH signal having logic “low” or “0” when the voltage at the power pin102is below the predetermined voltage level. For instance, if VDDHis 7.5-8 V, and VNOMis 5 V, then the high voltage detector112may be formed so that it outputs a logic level one whenever at least an intermediate threshold voltage (e.g., 6.5 V) between VNOMand VDDHis detected at power pin102.

As shown inFIG. 1, the programming control circuitry120and NOR gate122receive the power pin high voltage signal VDH at respective inputs thereof.

The NOR gate122receives the power pin high voltage signal VDH at an input connected to node116and receives a program select signal PRGSEL at another input. The program select signal PRGSEL is generated within the programming control circuitry120, and indicates whether programming mode has been initiated, as discussed below. Based on the power pin high voltage signal VDH and the program select signal PRGSEL, the NOR gate122outputs an output disable signal OUTDIS bar at node123. (The term “bar” is used where the signal is active low.) Thus, the output disable signal OUTDIS bar is logic low when either or both of the power pin high voltage signal VDH and the program select signal PRGSEL signal are logic high.

A gate of a depletion transistor124is connected to the node123and is controlled by the output disable signal OUTDIS bar. The depletion transistor124, in one embodiment, comprises a negative-threshold NMOS transistor. Thus, when the output disable signal OUTDIS bar is at logic low, and the source voltage of depletion transistor124is at a value higher than the absolute value of the depletion transistor threshold voltage, then the depletion transistor124is off (i.e., highly resistive). Thus, the depletion transistor124functions as a high voltage isolation device.

An input of an inverter126is also connected to the node123and receives the output disable signal OUTDIS bar and outputs the inverse thereof to an input of OR gate128. The OR gate128also receives data high signal DATAH bar at another input thereof. The data high signal DATAH bar is generated in the circuit function block140, as discussed below.

A gate of PMOS transistor130is connected to and controlled by the output of the OR gate128. Thus, when the output of the OR gate128is logic high, the PMOS transistor130is off (i.e., highly resistive). The output of the OR gate128is logic high when either the power pin high voltage signal VDH is high or the data high signal DATAH bar is high. Accordingly, when the power pin high voltage signal VDH is high, the transistors124,130are turned off.

An input of AND gate138is also connected (not shown) to the node123and receives the output disable signal OUTDIS bar. Another input of the AND gate138is connected to and receives a data low signal DATALO from the circuit function block140, as discussed below. The output of the AND gate138is connected to and controls a gate of NMOS transistor142. Thus, when either the output disable signal OUTDIS bar or the data low signal DATALO is logic low, or “0”, the NMOS transistor142is off (i.e., highly resistive). Accordingly, when the high voltage detector112output goes to logic high, the transistors130,124, and142are off, thereby creating a high impedance condition at the data pin104.

An input of high voltage detector132is connected to the data pin104such that the high voltage detector132outputs a data pin high voltage signal DIH at node136upon detecting a high voltage at the data pin104via voltage signal V2, similar to high voltage detector112discussed above. The high voltage detector132outputs a DIH signal having logic “high” or “1” when the voltage at the data pin104is above a predetermined voltage level and outputs a signal having logic “low” or “0” when the voltage at the data pin104is below the predetermined voltage level. In particular, the high voltage detector132detects when a high voltage pulse used to initiate the programming mode or to program the non-volatile memory cells is provided at data pin104via voltage signal V2. As discussed below, the data pin high voltage signal DIH is used by the programming control circuitry120.

A data input buffer146has an input connected to the data pin104via an optional negative-threshold NMOS transistor148. A gate of the NMOS transistor148is connected to power supply PS1, which permits NMOS transistor148to prevent voltages higher than the sum of the voltage signal V1and the absolute value of the transistor148threshold voltage from passing through transistor148to the data input buffer146.

The data input buffer146outputs a data in signal DIN at node149in response to a logic level voltage at the data pin104. In one embodiment, the data input buffer146is configured as a Schmidt trigger, although other input buffers may be alternatively employed. The data in signal DIN is received by the programming control circuitry120and the circuit function block140, as described below.

A switch150is connected between a ground terminal152, line151from the data pin104, and programming voltage (VPP) line154. Switch150is controlled by the program select signal PRGSEL generated in the programming control circuitry120. In one embodiment, the switch150may be implemented as a high voltage level shifter. In response to the program select signal PRGSEL signal, the switch150electrically connects the high voltage line154to the data pin104via line151so that the high voltage VHHpulse received at the data pin104via voltage signal V2may be provided to the programming voltage input P of the non-volatile memory cells160(FIG. 2) via line154, as the programming voltage VPP(i.e., VPP=VHH). The programming voltage signal VPPpulse carried to the memory cells160on line154is used to program the binary data provided by data line signal DINL into one or more selected non-volatile memory cells160.

A PMOS transistor153is optionally provided in line151between data pad104and switch150. The gate of transistor153is coupled to power supply PS1. Transistor153is a high voltage device that passes high voltages, but impedes voltages below the sum of the voltage signal V1voltage and the absolute value of the transistor153threshold voltage from reaching high voltage switch150and the circuitry downstream of switch150.

The circuit function block140ofFIG. 1represents portions of the integrated circuit1associated with the user's function for integrated circuit1when circuit100is not in the programming mode. The structure and purpose of circuit function block140can vary.

For example, circuit function block140may include circuitry that allows integrated circuit1to function as a reset controller, among other possible functions. Reset controllers may be used to monitor a power supply voltage provided to an associated system microcontroller, ASIC, and/or some other integrated circuit or device. If the power supply voltage is out of tolerance, e.g., too low, a reset signal output by the reset controller integrated circuit becomes active, and may be used to prevent the associated system microcontroller, ASIC, or other devices from operating. Reset signals typically become inactive 200 ms or so after the power supply voltage exceeds the reset threshold level.

In user mode, circuit function block140receives the data stored in the memory cells160through their respective outputs Q (FIG. 2) at all times, or during read operations initiated by circuit function block140, and may use the data for purposes associated with the user's application. Conventional circuitry associated with memory read operations may be used.

Circuit function block140also optionally receives the program select signal PRGSEL from program control circuitry120. The program select signal PRGSEL may be used to disable elements of circuit function block140(e.g., an oscillator or a state machine) that may interfere with programming mode.

Circuit function block140outputs the data low signal DATALO and data high signal DATAH bar (which are not necessarily complimentary). The respective value of these signals may be a combination of a memory cell160output and some operation of circuit function block140.

For instance, in a case where circuit function block140includes a reset controller function, the value of the data low signal DATALO and the data high signal DATAH bar in the user mode will determine whether transistors130and142, respectively, are on or off, which in turn will determine the output at data pin104, and hence the external characteristics of the reset controller. Outputs at any other data pins (not shown) also may be controlled by such signals. The particular values programmed into the memory cells160, therefore, may be used to vary the external characteristics of the reset controller of integrated circuit1, allowing the maker of integrated circuit1to use a single integrated circuit as the basis of a plurality of reset controller products having different external characteristics. For instance, one may configure the reset controller output in user mode as either a push pull (active high or active low) output or as an “open drain-like” output (p-type or n-type). In such a configuration, two memory cells160would be required to cover the four possible output configurations. Other memory cells160could be used to store values associated with other parameters of the reset controller function, such as a reference voltage parameter, a reset threshold parameter, and timing parameters, among other possibilities.

Depending on the application, circuit function block140may use data pin104as an input, and may use the data in signal DIN via buffer146for the user application performed by circuit function block140. For instance, in a reset controller application with a push pull configuration, NMOS transistor142and PMOS transistor130during user mode are on or off in a complimentary fashion. In such a case, the data in signal DIN would not be a useful input to circuit function block140. On the other hand, for an “open drain-like” configuration, which allows for only one of transistors142and130to be on or off, and for the other of transistors142and130to be off all of the time, data pin104may be used for providing a data input to circuit function block140in user mode. Such a configuration would include external pull up or pull down resistors.

A high value resistor156is coupled between node155on line151and ground. Node155is between transistor153and switch150. Resistor156provides a leakage path in programming mode when transistor153is off.

Power is provided to circuit function block140from power supply PS1through power pin102during both programming mode and user mode.

FIG. 2illustrates portions of an exemplary programming control circuit120and the non-volatile memory cells160. At the left side ofFIG. 2, a NAND gate202has an input connected to node116(FIG. 1) that receives the power pin high voltage signal VDH, and another input connected to node136(FIG. 1) that receives the data pin high voltage signal DIH.

A set-reset latch204includes a set input206, a reset input208and an output210. The set input206is connected to and receives the output of the NAND gate202. An inverter212includes an input that is connected to the node114(FIG. 1) and receives the power on reset signal POR. The output of the inverter212is connected to the reset input208of the latch204. Latch204is reset by receiving the inverted POR signal via the inverter212, which occurs shortly after the initial powering of circuit100. The latch204is set based on the power pin high voltage signal VDH and the data pin high voltage signal DIH. When both the VDH and DIH signals are logic “high”, a “1” is latched by the latch204and output by the latch204at the output210as program select signal PRGSEL. A program select signal PRGSEL indicates whether the programming control circuitry120is operating in programming mode. When the program select signal PRGSEL is at logic level one, programming mode has been initiated.

An AND gate216includes an input connected to node116and receives the power pin high voltage signal VDH. As mentioned above, high voltage VDDHpulses are provided via voltage signal V1to power pin102, and the power pin high voltage signal VDH will follow these pulses. Another input of the AND gate216is connected to the output210of the latch204and receives the program select signal PRGSEL. Since the power pin high voltage signal VDH pulses with the high voltage pulses of voltage signal V1that are applied to power pin102, the pulses will pass through AND gate216when programming mode is initiated. The pulsed output of the AND gate216, which is shown as clock signal SCLK; goes to clocking inputs of state machine222and data latch219.

The state machine222includes a reset input224, a clock input226, and an output225. Reset input224is coupled to the output of inverter212. Inverter212receives the power on reset signal POR, and outputs it in an inverted form as state machine reset signal SRES bar. Hence, state machine222resets when circuit100is initially powered, because that is when the power on reset signal POR is generated. In our example, state machine222is a counter, but may alternatively comprise any state machine that can accomplish the functions described herein.

Input226of state machine222is connected to the output of AND gate216. As mentioned above, the output of AND gate216, which is denoted as clock signal SCLK, follows the power pin high voltage signal VDH once programming mode is initiated. The power pin high voltage signal VDH pulses as a function of the serial high voltage pulses provided through power pin102. Hence, clock signal SCLK consists of a series of pulses. State machine222changes state (increments) in response to clock signal SCLK.

The latch219includes a clock input220, a data input221, a reset input223, and an inverting output228. Clock input220is connected to and receives the serially-pulsed output of AND gate216. Data input221is connected to node149(FIG.1), and thus receives the data in signal DIN, which reflects the binary data received through data pin104. Reset input223receives the state machine reset signal SRES bar, and hence resets when at the initial stage of the programming operation when the power on reset signal POR is generated. Latch219latches (i.e., stores) the data in signal DIN on the negative edge of pulses output by the AND gate216in response to the serially-pulsed power pin high voltage signal VDH. The latch219outputs the latched data at its inverted output228. This will be elaborated in the discussion of FIG.3.

A NAND gate232has an input connected to the output228of latch219. NAND gate232receives the data latched and output by latch219. Another input of the NAND gate232is connected to the output210of the latch204, and thus receives the program select signal PRGSEL. Based on the data output by the latch219and the program select signal PRGSEL, the NAND gate232outputs a data line signal DINL at node236. The data line signal DINL output by NAND gate232finally carries the binary data that was received through data pin104and stored in latch219to the data input D of all of the memory cells160. In other words, all of the memory cells160simultaneously receive the same binary data via data line signal DINL.

A decoder240has one or more inputs241connected to the output225of state machine222, and thus receives the binary counter signal CNT from the state machine222. The counter signal CNT may identify one of 2(M+1)number of different states of the counter. The decoder240receives and decodes the counter signal CNT output by state machine222during the respective counter cycle, and in turn outputs a cell select signal SEL at each of a plurality of outputs242. Each output242of decoder240is coupled via a respective one of a plurality of cell select lines244to a respective one of the memory cells160. The state of the cell select signal SEL on the respective cell select line244, either a logical one or a logical zero, selects or deselects, respectively, the particular memory cell160coupled to the particular cell select line244. A selected memory cell is programmed during the particular counter cycle, and a deselected memory cell is not programmed. Based on the state of the binary counter222, the decoder240will provide an appropriate cell select signal SEL for each of the respective memory cells160during any particular counter cycle. For one particular state, as discussed later, the decoder240will provide a logical one cell select signal SEL for all the memory cells160during one particular counter cycle. In addition, for the particular state after the power-on reset, the decoder240will provide no cell select signal SEL to the memory cells160. There may be additional states, up to the maximum number of states of the binary counter222that will result in no cell select signals SEL for the memory cells160.

For the exemplary embodiment ofFIGS. 1 and 2, which has memory cells160(0) to160(N) (total N+1), operated in accordance with the example ofFIG. 3, as discussed below, a minimum number of states of binary counter222is (N+1)+2. N+1 states are needed to select each SEL line individually. The additional two states are an initial state (FIG. 3) where no cells are selected (all cell select signals SEL being logical zero), and another state when all cells are selected (all cell select signals SEL being logical one).

Decoder240also receives the program select signal PRGSEL at enable input E of decoder240. The program select signal PRGSEL enables decoder240during programming mode. Accordingly, in user mode, decoder240is not enabled, and does not provide the cell select signals SEL to memory cells160.

As mentioned, in one programming sequence, the memory cells160may be selected and programmed in sequence, one by one, first to last, until each of the memory cells160is programmed appropriately. In such a case, the counter signal CNT output by state machine222will cause decoder240to select a sequential one of the memory cells160, and deselect the other memory cells160, until all of the memory cells160have been selected in sequence, one at a time. In another programming sequence, the counter signal CNT output by state machine222will cause decoder240to simultaneously select all of the memory cells160, so that all of the memory cells160may be programmed simultaneously.

The non-volatile memory of integrated circuit1includes a plurality of non-volatile memory cells160, e.g., EEPROMs, denoted as cells160(0)-160(N). The number of memory cells160can vary. Each individual cell (e.g.,160(0)), includes: (1) a select input terminal S that is coupled to an output242of decoder240via one of the cell select lines244, and receives the cell select signal SEL provided on the cell select line244; (2) a data input terminal D for receiving the data line signal DINL (i.e., binary data received through data pin104) via node236; (3) an output terminal Q for outputting the content of the memory cell160to circuit function block140(FIG.1); and (4) a programming voltage terminal P for receiving the high voltage programming signal VPPpulse via line154, switch150, and line151from data pin104. As discussed below, in order for an individual one of the memory cells160(0)-160(N) to be programmed with data corresponding with the data line signal DINL, the individual cell must be currently selected by a select signal SEL on a corresponding select signal line144, and the programming voltage signal VPPpulse received at the memory cell160must be above a threshold voltage capable of programming the memory cell160.

Note that the data signal DINL and programming voltage signal VPPare provided to all of the memory cells160concurrently. Hence, whether or not one or all of the memory cells160are programmed in any given counter cycle upon receipt of a high programming voltage signal VPPpulse depends on whether the particular memory cell160is selected or deselected at that time, which in turn depends on the state of state machine222.

In one embodiment, as an initial programming operation after the programming mode is entered, state machine222causes decoder240to simultaneously select all of the memory cells160(0)-160(N) by providing each memory cell160with a logical one cell select signal SEL. Accordingly, all of the memory cells160(0)-160(N) may be simultaneously and identically programmed with the binary data (either a logical one or zero) that is simultaneously provided to all of the memory cells160by the data line signal DINL upon receipt of the programming voltage through data pin104.

Operation of the exemplary circuits ofFIGS. 1 and 2will be further described in conjunction with the timing diagram shown in FIG.3. For the sake of example,FIG. 3shows various signals in the course of programming five non-volatile memory cells160, denoted cells160(0) to160(4), but the example applies to any plurality of non-volatile memory cells160.

As mentioned with respect toFIG. 1, only three pins are required for programming memory cells160: (1) a power pin102; (2) a data pin104; and (3) ground pin106. The voltage signal V1received on power pin102from power supply PS1is shown on the top line of FIG.3. Voltage signal V1includes the fixed-level nominal voltage VNOMthat is provided at all times during the programming operation, and serial pulses of the high voltage VDDH. That is, the voltage at power pin102is periodically increased from the nominal voltage VNOM(e.g., 5 V) to the high voltage VDDH(e.g., 8 V) and then decreased back to the nominal voltage VNOM. The serial high voltage VDDHpulses received on the power pin104are used within circuit100for clocking state machine222. The leading edge of each high voltage VDDHpulse of voltage signal V1initiates a new counter cycle.

The voltage signal V2received on data pin104is shown on the second line from the top of FIG.3. Voltage signal V2includes low voltage binary data, which is either a logical one or a logical zero, and pulses of the high voltage VHH. The high voltage VHHpulses are used to program previously-received binary data into the memory cells160.

The status of ground pin106is not shown inFIG. 3, but is 0 V.

Other signals shown inFIG. 3are internally generated within the circuits ofFIGS. 1 and 2during programming mode. For convenience, the state of the respective signals is shown as either a logical zero or a logical one. Practitioners will appreciate that the actual logical one voltages in the circuit nodes typically will have the same voltage variations as voltage signal V1from power supply PS1. The data in signal DIN is shown twice in FIG.3.

At time zero, the voltage signal V1is applied at power pin102from power supply PS1. The voltage signal V1ramps from 0 V to the nominal voltage VNOM(e.g., 5 V). In response, the power on reset signal POR goes from logic level zero to logic level one, and stays at logic level one until the voltage at power pin102reaches a predetermined level and a specified time passes, at which point the power on reset signal POR returns to logic level zero until the next power-on cycle. When the power on reset signal POR goes to logic level zero, the state machine reset signal SRES bar goes to logic level one. The output disable signal OUTDIS bar also goes to logic level one upon power on.

The programming mode is initiated upon: (1) receipt of a first high voltage VDDHpulse of voltage signal V1at power pin102from power supply PS1; and (2) during that first high voltage VDDHpulse, receipt of a high voltage VHHpulse of voltage signal V2at data pin104from power supply PS2. The programming mode is initiated within circuit100when the power pin high voltage signal VDH and the data pin high voltage signal DIH are coincidentally high. Initiation of the programming mode connotes a disabling of the user mode.

Referring toFIG. 3, at time A, the voltage signal V1received at power pin102initially pulses from the nominal voltage VNOMto the high voltage VDDH. This causes the power high voltage signal VDH to go to a logic level one, and the output disable signal OUTDIS bar to go to logic level zero.

Subsequently, the voltage signal V2received at data pin104pulses to the high voltage VHH. This causes high voltage detector112to output the data pin high voltage signal DIH at logic level one. When both the power high voltage signal VDH and the data pin high voltage signal DIH are in an initial logic level one state, programming control circuitry120causes the program select signal PRGSEL to go to logic level one, which indicates that the programming mode is initiated. The clock signal SCLK goes to logic level one when the power high voltage signal VDH and the program select signal PRGSEL are at logic level one. The initial high voltage VHHpulse of voltage signal V2is applied to the data pin104for a selected period of time during the first counter cycle, and then is removed. The high voltage VDDHpulses of voltage signal V1received on power pin102are of a greater duration than the high voltage VHHpulses of voltage signal V2received on data pin104.

The programming voltage signal VPPinFIG. 3mimics the high voltage VHHpulses of voltage signal V2on data pin104because switch150(FIG. 1) couples data pin104to line154, which carries the high voltage pulse to the programming voltage input P of the memory cells160. None of the memory cells160are selected (i.e., cell select signals SEL(0)-SEL(4) are logical zero) at the time of the initial high voltage VHHpulse on data pin104.

Note that, because the initial high voltage pulse VHHof voltage signal V2is not used to program memory cells160, it need not be the same level as (e.g., may be the same or less than) the high voltage VHHpulses of voltage signal V2subsequently provided on the data pin104to program the memory cells160, provided the first pulse is high enough to trigger high voltage detector136.

At time B, after programming mode is initiated, but still during the initial high voltage VDDHpulse of voltage signal V1on power pin102, a process of initially programming all of the five cells160(0)-160(4) with a common binary data value is begun. In this example, a logical one will be simultaneously programmed in all of the memory cells160(0)-160(4). To accomplish this, binary data corresponding to logic level one is provided via voltage signal V2on data pin104. The data in signal DIN goes to logic level one. Next, the voltage of voltage signal V1is dropped from the high voltage VDDHto the nominal voltage VNOM. On the negative edge of the voltage signal V1pulse, the power pin high voltage signal VDH goes to logic level zero. Clock signal SCLK follows to logic level zero. In addition, the data in signal DIN is stored in latch219. Latch219provides the stored binary data to NAND gate232.

Subsequently, the data line signal DINL provided to all of the memory cells160goes to logic level one, and decoder240selects all of the memory cells160(0)-160(4) for programming by outputting all of the cell select signals SEL(0)-SEL(4) at logic level one. Hence, each memory cell160(0)-160(4) receives an enabling cell select signal SEL, and the latched binary data via data line signal DINL.

Subsequently, at time B1, the voltage signal V2received at data pin104pulses to the high voltage VHH. The programming voltage signal VPPrises to the same high voltage level (i.e., equal to VHH). When memory cells160receive the high programming voltage signal VPPvia line154, the logical one provided to the data input terminal D of memory cells160(0)-160(4) via data line signal DINL is programmed into all of the memory cells160(0)-160(4) in a single counter cycle, since all of the memory cells160are selected.

Our example will now show the sequential programming of memory cells160(0)-160(4). Our example will store a logical zero in memory cell160(0). At time C, the voltage signal V1that is provided to power pin102pulses for a second time from the nominal voltage VNOMto the high voltage VDDH. Binary data corresponding to a logical zero is provided to data pin104via voltage signal V2. As a result, the data in signal DIN goes to logic level zero. Next, the voltage signal V1on the power pin102is dropped from the high voltage VDDHto the nominal voltage VNOM. On the negative edge of the voltage signal V1pulse, the power pin high voltage signal VDH and then the clock signal SCLK go to logic level zero. In addition, the logical zero data in signal DIN is stored in latch219. Decoder240then selects only memory cell160(0) by maintaining cell select signal SEL(0) at logic level one, and by changing cell select signals SEL(1)-SEL(4) to logic level zero. A logical zero data line signal DINL, which is output by NAND gate323based on the binary data stored in latch219, also is provided to the memory cells160. Subsequently, at time C1, the voltage signal V2received on data pin104pulses to the high voltage VHH, which raises the programming voltage signal VPPto the high voltage level. Since memory cell160(0) is selected, the logical zero binary data provided to memory cell160(0) via data line signal DINL is stored in memory cell160(0). Since memory cells160(1)-160(4) are not selected, they are not programmed, and continue to store a logical one.

At time D, when the voltage signal V1provided on power pin102pulses for a third time to the high voltage VDDH, a process for programming a logic level zero in cell160(1) is begun. Binary data corresponding to a logical zero is provided to data pin104via voltage signal V2. The data in signal DIN goes to logic level zero. Next, the voltage signal V1on the power pin102is dropped from the high voltage VDDHto the nominal voltage VNOM. On the negative edge of the voltage signal V1pulse, the power pin high voltage signal VDH and then the clock signal SCLK go to logic level zero. In addition, the logical zero data in signal DIN is latched in latch219. Decoder240selects only memory cell160(1) by changing cell select signal SEL(1) to logic level one, changing cell select signal SEL(0) to logic level zero, and maintaining cell select signals SEL(2)-SEL(4) at logic level zero. A logical zero data line signal DINL, which is output by NAND gate323based on the binary data stored in latch219, also is provided to the memory cells160. Subsequently, at time D1, the voltage signal V2received on data pin104pulses to the high voltage VHH, which raises the programming voltage signal VPPto the high voltage level. Since cell160(1) is selected, the logical zero provided to memory cell160(1) via data line signal DINL is programmed into memory cell160(1). Since memory cells160(0) and160(2)-160(4) are not selected, they are not programmed, even though they also (simultaneously) received the data line signal DINL and the programming voltage signal VPP.

Our example ofFIG. 3continues to the next memory cell, i.e., memory cell160(2). It is desired that memory cell160(2) store a logical one. However, during the initial programming cycle described above, a logical one already was programmed in memory cell160(2) (and in all of the other memory cells160). One way to maintain the logical one originally programmed in memory cell160(2) is to not pulse the voltage signal V2to the high voltage VHHwhen memory cell160(2) is selected. In particular, at time E, the voltage signal V1provided on power pin102pulses for a fourth time to the high voltage VDDH. Binary data corresponding to a logic level zero (or logic level one, it does not matter here) is provided on data pin104via voltage signal V2. The data in signal DIN goes to logic level zero. Next, the voltage signal V1on the power pin102is dropped from the high voltage VDDHto the nominal voltage VNOM. On the negative edge of the voltage signal V1pulse, the power pin high voltage signal VDH and then the clock signal SCLK go to logic level zero. In addition, the data in signal DIN is latched in latch219. Decoder240then selects only memory cell160(2) by changing cell select signal SEL(1) to logic level zero, changing cell select signal SEL(2) to logic level one, and by maintaining cell select signals SEL(0), SEL(3) and SEL(4) at logic level zero. The logical zero data line signal DINL is provided to the memory cells160from NAND gate232. However, because voltage signal V2is not pulsed to the high voltage VHHat time E1, a high voltage programming voltage signal VPPis not provided to memory cell160(2) when it is selected. According, memory cell160(2) is not programmed with the logical zero provided via data line signal DINL, and the logical one originally programmed into memory cell160(2) remains therein.

At time F, when the voltage signal V1provided on power pin102pulses for a fifth time to the high voltage VDDH, a process for storing a logic level zero in memory cell160(3) is begun. The process is the same as that described for memory cell160(1) above, except for the selection of memory cell160(3) and the deselection of cell160(1) and the other memory cells160by decoder240. Accordingly, further discussion is not necessary.

At time G, when the voltage signal V1provided on power pin102pulses for a sixth time to the high voltage VDDH, a process to program memory cell160(4) with a logical one is begun, notwithstanding that a logical one already was stored in memory cell160(4) during the initial programming. In particular, binary data corresponding to a logic level one is provided to data pin104via voltage signal V2. The data in signal DIN goes to logic level one. Next, the voltage signal V1on the power pin102is dropped from the high voltage VDDHto the nominal voltage VNOM. On the negative edge of the voltage signal V1pulse, the power pin high voltage signal VDH and then the clock signal SCLK go to logic level zero. In addition, the logical one data in signal DIN is stored in latch219. Decoder240then selects only memory cell160(4) by changing cell select signal SEL(4) to logic level one, changing cell select signal SEL(3) to logic level zero, and by maintaining cell select signals SEL(1) and SEL(2) at logic level zero. The logical one stored in latch219is passed to NAND gate232, which outputs a logical one data line signal DINL to all of the memory cells160. Subsequently, at time G1, the voltage signal V2received on data pin104pulses to the high voltage VHH, which raises the programming voltage signal VPPto the high voltage level. Since only memory cell160(4) is selected, the logical one provided to the memory cell160(4) from NAND gate232via data line signal DINL is programmed in memory cell160(4). Since memory cells160(0)-160(3) are not selected, they are not programmed and retain their previous data.

Practitioners will appreciate that the discussion and drawings herein describe exemplary embodiments of the invention, and that various additions, deletions, substitutions, and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims.