High efficiency single-inductor dual-control loop power converter

A high efficiency single-inductor dual-control loop power converter (SIDL) is proposed for converting unregulated DC input into regulated DC output to a power load. The SIDL includes:    A PWM switching power regulating loop for converting the unregulated DC input into the regulated DC output.    The power-efficiency maximizing loop includes: a power shunt transistor in parallel connection with the power diode and a real-time control loop adjusting, in response to a freewheeling current through the power diode, conductance of the power shunt transistor in a manner that a higher freewheeling current results in a higher conductance of the power shunt transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

Field of Invention

This invention relates generally to the field of electrical power supply. More specifically, the present invention is directed to the design of a switching power supply.

BACKGROUND OF THE INVENTION

Owing to its compact size, low weight and generally high efficiency, switching power supplies have enjoyed ever increasing market adoption in the consumer electronics industry. This is specially so in portable applications where compact size, low weight and battery life are all on top of the list of considerations.

As a first illustration of prior art switching power supply,FIG. 1illustrates a non-synchronous, single-loop regulated switching converter1. The single-loop regulated switching converter1operates to convert an unregulated DC input3into a regulated DC output voltage5supplying a power load4with power ground2. A controlled power output transistor9drives the power load4through a series, parallel network of power inductor6, power capacitor7and passive power diode8with the input side6aof the power inductor6connected to the power output transistor9and the output side6bconnected to the power load4. In this single-loop system, the control signal, being the gate voltage of the power output transistor9, is derived from a feedback control branch having an error amplifier10and a pulse width modulation (PWM) controller11that turns on or off the power output transistor9depending upon the regulated DC output voltage5being lower or higher than a “reference” voltage. As the power inductor6stores electrical energy with its coil current, the passive power diode8free-wheels the inductor current whenever the power output transistor9is turned off.

FIG. 2Atogether withFIG. 2Billustrate a second prior art single-loop synchronous regulated switching converter20and some of its related operating signal waveforms. Except for the replacement of the power diode8in the single-loop regulated switching converter1with a power shunt transistor21and its driving inverter22, the single-loop synchronous regulated switching converter20is essentially the same as the single-loop regulated switching converter1. As the inverter22is driven by the output of the PWM controller11, the single-loop synchronous regulated switching converter20operates on synchronously driving the power output transistor9and the power shunt transistor21, in a complementary off/on manner, with the feedback control branch having the error amplifier10and the pulse width modulation (PWM) controller11. This can be seen by comparing the two gate signal waveforms Vgs_Q120aand Vgs_Q220bof power output transistor9and power shunt transistor21respectively. To prevent a dangerous condition of shoot-through wherein both transistors9and21are conducting, a dead time t1is provided wherein both transistors9and21are OFF (Ids_Q120c=Ids_Q220d=0) and a load current Io returns through a built-in parasitic diode (part of power shunt transistor21, not shown) with forward voltage Vf. The corresponding energy loss is Vf*Io*t1. Additionally, there are energy losses during time intervals t2and t3wherein the power output transistor9is being switched OFF and the power shunt transistor21being switched ON respectively. Thus, the following total energy loss is incurred per switching cycle of the transistors9and21:
ELC=Energy loss per switching cycle=0.5*Vf*Io*(t2+t3)+Vf*Io*t1  (1)
A highly important measure of performance of a power converter is its overall power efficiency defined as:
overall power efficiency=output power/input power  (2)
Clearly, the above ELC acts to undesirably lower the overall power efficiency of the single-loop synchronous regulated switching converter20. As will be shown later, the loss of overall power efficiency becomes rapidly pronounced at lighter load current Io. Hence, a primary object of the present invention is to improve the overall power efficiency.

SUMMARY OF THE INVENTION

A high efficiency single-inductor dual-control loop power converter (SIDL) is proposed for converting unregulated DC input into regulated DC output to a power load. The SIDL includes:

an energy storage loop that itself includes: a power inductor having an input side and an output side with the output side in series connection to the power load; a power capacitor coupling the output side to a power ground; and a power diode bridging the input side to the power ground.
a first switching power regulating loop interposed between the unregulated DC input and the input side, for controllably converting the unregulated DC input into the regulated DC output while sensing a power regulation at the power load.
a second power-efficiency maximizing loop in parallel connection with the power diode for shunting a portion of its electrical current thus associated power loss so as to maximize the overall power efficiency of the SIDL regardless of the power level delivered to the power load.

In an embodiment, the switching power regulating loop employs a PWM control loop adjusting, in response to a sensed output at the power load, the turn-on time pulse width of a power output transistor that is in series connection with the power inductor.

In one embodiment, the regulated DC output is implemented as a regulated load voltage with the sensed output at the power load being the load voltage.

In an alternative embodiment, the regulated DC output is implemented as a regulated load current with the sensed output at the power load being the load current.

In an embodiment, the power-efficiency maximizing loop includes: a power shunt transistor in parallel connection with the power diode; and a real-time control loop adjusting, in response to a sensed freewheeling current through the power diode, conductance of the power shunt transistor in a manner that a higher sensed freewheeling current results in a higher conductance of the power shunt transistor. Furthermore, in response to a sensed freewheeling current of zero, the real-time control loop turns off the power shunt transistor for a corresponding transistor conductance of essentially zero.

In an embodiment, in response to any given level of sensed freewheeling current, the real-time control loop adjusts for just an adequate level of conductance of the power shunt transistor such that, beyond this adequate conductance level, a corresponding power loss attributable to driving the power shunt transistor itself would otherwise lower the overall power efficiency of the SIDL.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention.

FIG. 3is a top level circuit architecture illustrating an embodiment of the single-inductor dual-control loop converter (SIDL)30of the present invention. As referenced to a power ground2, the SIDL30converts an unregulated DC input3into a regulated DC output voltage5to a power load4with a load current Io15. The output end of the SIDL30is an energy storage loop further including the following components:a power inductor6having an input side6aand an output side6bwith the output side6bin series connection to the power load4.a power capacitor7coupling the output side6bto the power ground2.a power diode8bridging the input side6ato the power ground2.
For controllably converting the unregulated DC input3into the regulated DC output voltage5while sensing a power regulation at the power load4, a first switching power regulating loop32is interposed between the unregulated DC input3and the input side6a. As shown, the switching power regulating loop32has a PWM control loop that is a series connection of an error amplifier10, a first PWM feedback controller31and a power output transistor9. A power shunt transistor21is provided in parallel connection with the energy storage loop to control power dissipation due to a freewheeling current through the power diode8that is caused by the load current Io15while the power output transistor9is shut off. As a component, the first PWM feedback controller31itself is known in the art and it drives the power output transistor9with a switching power control signal14. The input of the first PWM feedback controller31is supplied by an output from the error amplifier10that produces an amplified signal representing the difference between a sensed output5band a desired reference voltage12. Hence, the first PWM feedback controller31adjusts, in response to the sensed output5bat the power load4, the turn-on time pulse width of the power output transistor9in series connection with the power inductor6to maintain the regulated DC output voltage5within a desired range of regulation regardless of changes in the power load4. In this embodiment, the regulated DC output is the regulated DC output voltage5thus; correspondingly, the sensed output5bat the power load4is its load voltage. By now it should become clear to those skilled in the art that, with small modifications, the regulated DC output can alternatively be implemented as a regulated load current thus, correspondingly, the sensed output at the power load4will be its load current with the SIDL30delivering a regulated output current instead. This will be presently illustrated.

To control and minimize the aforementioned energy loss per switching cycle, ELC as given by expression (1), hence maximizing the overall power efficiency of the SIDL30, a second power-efficiency maximizing loop34is introduced in parallel connection with the power diode8. As shown, the power-efficiency maximizing loop34has a serial connection of a current sensor40, a gain stage100and the power shunt transistor21. The current sensor40provides a signal that is proportional to a current flowing through the power diode8. Following the gain stage100, a properly scaled signal, in proportion to the power diode current, is applied to the gate of the power shunt transistor21causing it to shunt a portion of the power diode freewheeling current thus power loss through it. Thus, in response to a higher sensed freewheeling current, the power-efficiency maximizing loop34adjusts for a higher conductance of the power shunt transistor21. As the conductance of the power shunt transistor21can be controlled to become much higher than that of the power diode8and power dissipation is equal to I2R (from Ohm's Law), the corresponding ELC is reduced. On the other hand, the action of driving the gate of the power shunt transistor21has its own associated energy loss that is proportional to the square of the gate voltage. An excessive gate voltage applied to the power shunt transistor21would offset its power benefit derived from shunting a portion of the power diode freewheeling current. Therefore, the gain stage100needs to be properly set such that, in response to any given level of sensed freewheeling current through the power diode8, the power-efficiency maximizing loop34adjusts for just an adequate level of conductance of the power shunt transistor21beyond which a corresponding power loss attributable to driving the power shunt transistor21itself would otherwise lower the overall power efficiency of the SIDL30. As a corollary, in response to a sensed freewheeling current of zero through the power diode8, the power-efficiency maximizing loop34turns off the power shunt transistor21for a corresponding transistor conductance of essentially zero. In this way, the overall power efficiency of the SIDL30can be maximized regardless of the power level delivered to the power load4.

It is important to point out that the two switching power regulating loop32and power-efficiency maximizing loop34are, while operating simultaneously, totally different control loops because they sense different signals for making decision. As a result, the bandwidth (the responding time) of the two control loops are very different, as illustrated in the table below:

Switching powerPower-efficiencyregulating loopmaximizing loopSensed signalPower load related signalCurrent through powerdiodeResponse timeSlow (PWM time)Very Fast (real-timecomparison)
Also, as a pre-requisite for the power shunt transistor21to turn ON is current flowing through the power diode8, the root-cause of shoot-through wherein both transistors9and21are conducting has been eliminated hence no more need to provide the dead time t1as in the prior art.

FIG. 4is a circuit schematic illustrating an alternative of the first switching power regulating loop32of the SIDL30. A series connection of a comparator31aand an S-R latch31bfollows the output of the error amplifier10. The output of S-R latch31b, clocked by a PWM clock31c, then feeds the switching power control signal14. Notice that signal I-inductor13(with an illustrated I-inductor waveform13a), the other input of the comparator31a, is a sensed signal representing current through the power inductor6. Hence, this alternative of the first switching power regulating loop32implements a corresponding SIDL30delivering a regulated output current using a fixed frequency current mode PWM control.

FIG. 5is a circuit schematic illustrating another alternative embodiment of the first switching power regulating loop32of the SIDL30. A series connection of an inverter31dand a fixed delay time31efollows the output of the comparator31athat also feeds the R-terminal of the S-R latch31b. As the inputs of the comparator31aare the sensed output5b(of regulated DC output voltage5) and the reference voltage12, this alternative of the first switching power regulating loop32implements a corresponding SIDL30delivering a regulated output voltage using a constant-off voltage mode PWM control.

FIG. 6is a high level circuit architecture illustrating an embodiment of the second power-efficiency maximizing loop34. As shown, the power-efficiency maximizing loop34has two key important components serially connected: an I-diode signal100a, coming from the free-wheeling power diode current sensor40, and the gain stage100that amplifies the I-diode signal100ato an adequate level (power-efficiency control signal100b) to drive the power shunt transistor21.

FIG. 7AtoFIG. 7Cillustrate various ways to measure the free-wheeling diode current for the second power-efficiency maximizing loop34ofFIG. 6. InFIG. 7Aa diode negative terminal voltage VLX100cof the power diode8is measured. The measured diode negative terminal voltage VLX100ccan then be used in conjunction with a pre-determined diode current-voltage characteristics to estimate the free-wheeling diode current. InFIG. 7Ban I-sensing resistor100dof known value is placed in series connection with the power diode8. A measured voltage drop across the I-sensing resistor100dis then used to calculate the free-wheeling diode current. InFIG. 7Can I-sensor100ecan be placed in close proximity to the current path of the power diode8to directly sense the free-wheeling diode current. As a more specific embodiment, a Hall Effect device can be used as the I-sensor100e. In any case, depending upon whether the sensed free-wheeling diode current is a current signal or a voltage signal, the corresponding gain stage100can be either a trans-conductance amplifier or a voltage amplifier.

FIG. 8is a detailed SIDL circuit embodiment110implementing the top level circuit architecture ofFIG. 3. The SIDL circuit embodiment110converts an unregulated 12V DC input V13ainto a regulated 3.3V DC output voltage5adriving a load current Io15into the power load4. The switching power regulating loop32includes a cascade of a trans-conductance error amplifier G1112, a voltage comparator CMP113and an RS latch U2114driving a switching power control signal14into the power output transistor9. Thus, the RS latch U2114has a corresponding driving capability. The reference input of the trans-conductance error amplifier G1112is a precise voltage reference V2115, in this case 1.2 Volt, that ultimately determines the final regulated 3.3V DC output voltage5a. The trans-conductance error amplifier G1112produces an error current that is proportional to the voltage difference between the regulated 3.3V DC output voltage5aand the precise voltage reference V2115. A compensation network118, having a resistor element R in parallel with the trans-conductance error amplifier G1112, then converts the error current into an error signal Verr117feeding into a first input pf the voltage comparator CMP113. A second input of the voltage comparator CMP113is a ramp signal116whose peak is higher than the error signal Verr117. The ramp signal116can be an externally supplied voltage ramp or it can be generated by a current flowing through the power inductor L6or some combination of both. The output of the voltage comparator CMP113feeds the R-input of the RS latch U2114. Finally, a PWM clock31csupplies the S-input of the RS latch U2114. The power-efficiency maximizing loop34includes an operational amplifier X1111amplifying, with limited gain and driving capability, a voltage drop across the power diode8into a power-efficiency control signal100bdriving the power shunt transistor21.

FIG. 9compares the overall power efficiency (%) between a single-inductor dual-control loop power converter, power efficiency160, and a corresponding prior art single-loop synchronous regulated switching converter, power efficiency150. Some relevant specific parameters are:
unregulated DC input 3a=12V, regulated DC output voltage 5a=3.3V,
power inductor 6=3.7 μH (microHenry, 10−6Henry)
While the overall power efficiency are close to each other under heavy load (Load current Io from 0.7 Amp to 10 Amp), the advantage of the single-inductor dual-control loop power converter over prior art becomes rapidly obvious toward light load, starting from about 0.7 Amp and below.

FIG. 10Aillustrates various signal waveforms within the SIDL circuit embodiment110ofFIG. 8under a range of heavy load power level condition, Load current from about 1.6 Amp to about 2.4 Amp. The waveform power shunt transistor Vgs16looks to be approximately synchronous with respect to load current Io15and regulated 3.3V DC output voltage5a.FIG. 10Billustrates various signal waveforms within the SIDL circuit embodiment110ofFIG. 8under a range of light load power level condition, Load current Io from 0 mA to about 550 mA. Due to the nature of dual-control loop of the present invention, the waveform power shunt transistor Vgs16has now become highly non-synchronous with respect to load current Io15and regulated 3.3V DC output voltage5aresulting in the observed higher overall power efficiency compared to the prior art.

While the description above contains many specificities, these specificities should not be constructed as accordingly limiting the scope of the present invention but as merely providing illustrations of numerous presently preferred embodiments of this invention. For example, to those skilled in the art, while the present invention is illustrated using Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) to implement both power output transistor9and power shunt transistor21, the present invention can be readily implemented using bipolar transistors or other equivalent 3-terminal active switching devices as well.

Throughout the description and drawings, numerous exemplary embodiments were given with reference to specific configurations. It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in numerous other specific forms and those of ordinary skill in the art would be able to practice such other embodiments without undue experimentation. The scope of the present invention, for the purpose of the present patent document, is hence not limited merely to the specific exemplary embodiments of the foregoing description, but rather is indicated by the following claims. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.