Method of manufacturing memory structure

A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application no. 109112336, filed on Apr. 13, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a method of manufacturing a semiconductor structure, and in particular to a method of manufacturing a memory structure.

Description of Related Art

At present, in the manufacturing process of some memory devices, a charge-storage layer is formed in an opening between two adjacent isolation structures. However, when the width of the top of the opening between two adjacent isolation structures is too small, the gap-fill capability of the charge-storage layer is worsened. In addition, when the width of the top of the opening between two adjacent isolation structures is too small, the isolation structures produce a shadowing effect on the ion implantation process during the ion implantation process performed on a substrate below the opening. Therefore, the quality of the doped regions formed by the ion implantation process is poor.

SUMMARY OF THE INVENTION

The invention provides a method of manufacturing a memory structure that may improve the gap-fill capability of a charge-storage layer and may reduce the shielding effect on an ion implantation process.

The invention provides a manufacturing method of a memory structure including the following steps. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification process includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a method of forming the isolation structures may include the following steps. A patterning process is performed on the first pad layer and the substrate to form a plurality of trenches in the first pad layer and the substrate. An isolation structure material layer filled in the trenches is formed. The isolation structure material layer outside the trenches is removed.

According to an embodiment of the invention, in the method of manufacturing the memory structure, after the patterning process is performed on the first pad layer, an angle between a bottom surface of the first pad layer and sidewalls of the first pad layer may be less than 86 degrees.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a method of forming the isolation structure material layer is, for example, a high aspect ratio process (HARP) or high-density plasma chemical vapor deposition (HDPCVD).

According to an embodiment of the invention, in the method of manufacturing the memory structure, the first etching process is, for example, a wet etching process. A method of removing the first pad layer is, for example, a wet etching method.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a material of the first pad layer is, for example, silicon nitride. An etchant used in the first etching process may include a phosphoric acid. An etchant used to remove the first pad layer may include a phosphoric acid. A temperature of the phosphoric acid used to remove the first pad layer may be higher than a temperature of the phosphoric acid used in the first etching process.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a top width of the first openings may be enlarged by the second etching process.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the second etching process is, for example, a wet etching process.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a material of the isolation structures is, for example, silicon oxide. An etchant used in the second etching process may include diluted hydrofluoric acid (DHF).

According to an embodiment of the invention, in the method of manufacturing the memory structure, a total height of the first pad layer reduced by the shape modification treatment may be less than half of an initial height of the first pad layer.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the following steps may be further included. A cleaning process is performed on the first pad layer before the shape modification treatment is performed.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a cleaning solution used in the cleaning process may include diluted hydrofluoric acid.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the following steps may be further included. A second pad layer is formed on the substrate before the first pad layer is formed. A material of the second pad layer is, for example, silicon oxide.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the following steps may be further included. A doped region is formed in the substrate after the first pad layer is removed. The second pad layer is removed after the doped region is formed.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a charge-storage layer may be further formed in the second openings.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the charge-storage layer is, for example, a floating gate.

According to an embodiment of the invention, in the method of manufacturing the memory structure, a method of forming the charge-storage layer may include the following steps. A charge-storage material layer filled in the second openings is formed. The charge-storage material layer outside the second openings is removed.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the following steps may be further included. A first dielectric layer is formed on the substrate exposed by the second openings before the charge-storage layer is formed.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the following steps may be further included. A portion of the isolation structures is removed to form a plurality of third openings above the isolation structures. A second dielectric layer is formed on surfaces of the third openings and the charge-storage layer. A conductive layer is formed on the second dielectric layer. The conductive layer is filled in the third openings.

According to an embodiment of the invention, in the method of manufacturing the memory structure, the substrate may include a memory device region and a logic device region. The memory structure is located in the memory device region. The isolation structures in the memory device region and the isolation structures in the logic device region may be formed at the same time.

Based on the above, in the method of manufacturing the memory structure provided in the invention, a shape modification treatment is performed on the isolation structures to modify the sidewall shape of the isolation structures. As a result, the second openings have a larger top width. Since the second openings have a larger top width, the gap-fill capability of the charge-storage layer formed in the second openings may be improved. In addition, in the subsequent ion implantation process performed on the substrate below the second openings, the shielding effect of the isolation structures on the ion implantation process may be reduced.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1AtoFIG. 1Lare cross sections of a manufacturing process of a memory structure of an embodiment of the invention.

Referring toFIG. 1A, a pad layer102may be formed on a substrate100. The substrate100may be a semiconductor substrate such as a silicon substrate. The material of the pad layer102is, for example, silicon oxide. The method of forming the pad layer102is, for example, a thermal oxidation method.

Next, a pad layer104may be formed on the pad layer102. The material of the pad layer104is, for example, silicon nitride. The method of forming the pad layer104is, for example, a chemical vapor deposition method.

Referring toFIG. 1B, a patterning process is performed on the pad layer104, the pad layer102, and the substrate100, and a plurality of trenches106are formed in the pad layer104, the pad layer102, and the substrate100. For example, the pad layer104, the pad layer102, and the substrate100may be patterned via a lithography process and an etching process (e.g., dry etching process). In addition, after the patterning process is performed on the pad layer104, an angle θ between a bottom surface S1of the pad layer104and sidewalls S2of the pad layer104may be less than 86 degrees, thereby improving the gap-fill capacity of the isolation structures subsequently formed in the trenches106.

Referring toFIG. 1C, an isolation structure material layer108filled in the trenches106is formed. The material of the isolation structure material layer108is, for example, silicon oxide. The method of forming the isolation structure material layer108is, for example, a high aspect ratio process (HARP) or high-density plasma chemical vapor deposition (HDPCVD).

Referring toFIG. 1D, the isolation structure material layer108outside the trenches106is removed, and a plurality of isolation structures108aare formed in the pad layer104, the pad layer102, and the substrate100. The method of removing the isolation structure material layer108outside the trenches106is, for example, a chemical mechanical polishing method. In the present embodiment, the method of forming the isolation structures108ais exemplified by the above method, but the invention is not limited thereto.

Referring toFIG. 1EandFIG. 1F, at least one shape modification treatment is performed on the isolation structures108a. Each shape modification treatment includes performing the steps inFIG. 1EandFIG. 1F. In addition, before the shape modification treatment is performed, a cleaning process may be performed on the pad layer104to remove the native oxide (not shown) on the pad layer104. The cleaning solution used in the cleaning process may include diluted hydrofluoric acid.

Referring toFIG. 1E, a first etching process is performed on the pad layer104to reduce the height of the pad layer104and form openings110exposing sidewalls S3of the isolation structures108a. The openings110may have a top width W1. The first etching process is, for example, a wet etching process. When the material of the pad layer104is silicon nitride and the first etching process is a wet etching process, the etchant used in the first etching process may include phosphoric acid.

Referring toFIG. 1F, after the first etching process is performed, a second etching process is performed on the isolation structures108ato modify the shapes of the sidewalls S3of the isolation structures108aexposed by the openings110. In this way, the top width of the openings110may be enlarged by the second etching process. For example, the top width of the openings110may be enlarged from the top width W1(FIG. 1E) to a width W2(FIG. 1F). The second etching process is, for example, a wet etching process. When the material of the isolation structures108ais silicon oxide and the second etching process is a wet etching process, the etchant used in the second etching process may include diluted hydrofluoric acid. In the second etching process, in addition to removing a portion of the side of the isolation structures108ato modify the shape of the sidewalls S3of the isolation structures108aexposed by the openings110, a portion of the top of the isolation structures108amay also be removed to reduce the height of the isolation structures108a. In addition, since the pad layer104covers the pad layer102, the second etching process does not cause loss to the pad layer102.

InFIG. 1EandFIG. 1F, although the shape modification treatment is performed once on the isolation structures108aas an example, the invention is not limited thereto. In other embodiments, a plurality of shape modification treatments may also be performed on the isolation structures108ato obtain the desired sidewall shape of the isolation structures108a. That is, as long as at least one shape modification treatment is performed on the isolation structures108a, it falls within the scope of the invention. In addition, a total height H2of the pad layer104reduced by at least one shape modification treatment may be less than half of an initial height H1of the pad layer104. In some embodiments, the total height H2of the pad layer104reduced by the shape modification treatment may be one quarter to half of the initial height H1of the pad layer104. In some embodiments, the total height H2of the pad layer104reduced by the shape modification treatment may be one third to half of the initial height H1of the pad layer104.

In addition, when a plurality of shape modification treatments are performed on the isolation structures108a, a plurality of first etching processes and a plurality of second etching processes are performed. The amount of the pad layer104removed by each first etching process may be the same or different. The amount of the isolation structures108aremoved by each second etching process may be the same or different.

Referring toFIG. 1G, the pad layer104is removed, and an opening112is formed between two adjacent isolation structures108a. The method of removing the pad layer104is, for example, a wet etching method. When the material of the pad layer104is silicon nitride, the etchant used in the wet etching method may include phosphoric acid. In addition, the etchant used to remove the first pad layer may include phosphoric acid. The temperature of the phosphoric acid used to remove the pad layer104may be higher than the temperature of the phosphoric acid used in the first etching process. For example, the temperature of the phosphoric acid used in the first etching process to reduce the height of the pad layer104may be 120° C. to 140° C., and the temperature of the phosphoric acid used to remove the pad layer104may be 150° C. to 170° C. In the first etching process for reducing the height of the pad layer104, the use of phosphoric acid having a lower temperature may effectively control the amount of the pad layer104removed. In the step of removing the pad layer104, the use of phosphoric acid having a higher temperature may quickly remove the pad layer104.

Next, after the pad layer104is removed, a doped region114may be formed in the substrate100. The doped region114is, for example, a well region. The method of forming the doped region114is, for example, an ion implantation method. After the above shape modification treatment is performed on the isolation structures108a, the openings112may have a larger top width, so that the shielding effect of the isolation structures108aon the ion implantation process may be reduced.

Referring toFIG. 1H, after the doped region114is formed, the pad layer102may be removed. Thereby, the openings112may expose the substrate100. The method of removing the pad layer102is, for example, a wet etching method. When the material of the pad layer102is silicon oxide, the etchant used in the wet etching method may include hydrofluoric acid. In addition, in the process of removing the pad layer102, a portion of the top and a portion of the side of the isolation structures108amay be removed at the same time.

Referring toFIG. 1I, a dielectric layer116may be formed on the substrate100exposed by the openings112. The dielectric layer116may be used as a tunneling dielectric layer. The material of the dielectric layer116is, for example, silicon oxide. The method of forming the dielectric layer116is, for example, a thermal oxidation method.

Then, a charge-storage material layer118filled in the openings112may be formed. The charge-storage material layer118may be located on the dielectric layer116. The material of the charge-storage material layer118is, for example, doped polysilicon. The method of forming the charge-storage material layer118is, for example, a chemical vapor deposition method. After the shape modification treatment is performed on the isolation structures108a, the openings112may have a larger top width, so that the gap-fill capability of the charge-storage material layer118formed in the openings112may be improved.

Referring toFIG. 1J, the charge-storage material layer118outside the openings112may be removed, and a charge-storage layer118ais formed in the openings112. The charge-storage layer118ais, for example, a floating gate. The method of removing the charge-storage material layer118outside the openings112is, for example, a chemical mechanical polishing method. In the present embodiment, the method of forming the charge-storage layer118ais exemplified by the above method, but the invention is not limited thereto.

Referring toFIG. 1K, a portion of the isolation structures108amay be removed, and a plurality of openings120are formed above the isolation structures108a. The method of removing a portion of the isolation structures108aincludes a wet etching method, a dry etching method, or a combination thereof.

Referring toFIG. 1L, a dielectric layer122may be formed on the surface of the openings120and the charge-storage layer118a. For example, the dielectric layer122may be a composite layer of silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO). The method of forming the dielectric layer122is, for example, a chemical vapor deposition method or in-situ steam generation (ISSG).

Next, a conductive layer124may be formed on the dielectric layer122. The conductive layer124is filled in the openings120. The conductive layer124may be used as a control gate. The material of the conductive layer124is, for example, doped polysilicon. The method of forming the conductive layer124is, for example, a chemical vapor deposition method. As shown inFIG. 1B, since the angle θ between the bottom surface S1of the pad layer104and the sidewalls S2of the pad layer104may be less than 86 degrees, the isolation structures108amay have a larger initial top width. In this way, even if the shape modification treatment causes the top width of the isolation structures108ato be smaller, the isolation structures108amay still have a sufficient top width. That is, the openings120formed subsequently may have a sufficient top width, such that the conductive layer124formed in the openings120has sufficient gap-fill capability.

Via the above method, a memory structure10may be formed. The memory structure10may be a non-volatile memory, such as an embedded flash (eFlash) memory. In some embodiments, the substrate100may include a memory device region and a logic device region. The memory structure10may be located in the memory device region. The isolation structures108ain the memory device region and the isolation structures (not shown) in the logic device region may be formed at the same time.

Based on the above embodiments, it may be seen that in the method of manufacturing the memory structure10, a shape modification treatment is performed on the isolation structures108ato modify the sidewall shape of the isolation structures108a, thereby allowing the openings112to have a larger top width. Since the openings112have a larger top width, the gap-fill capability of the charge-storage layer118aformed in the openings112may be improved. In addition, in the subsequent ion implantation process performed on the substrate100below the openings112, the shielding effect of the isolation structures108aon the ion implantation process may be reduced.

Based on the above, in the method of manufacturing the memory structure of the above embodiments, a shape modification treatment is performed on the isolation structures, so that the gap-fill capability of the charge-storage layer may be improved, and the shielding effect on the ion implantation process may be reduced.