MEMS device with a bonding layer embedded in the cap

Embodiments of a semiconductor device structure are provided. The semiconductor device structure includes a cap structure. The cap structure includes: a first bonding layer and a cap substrate, and the first bonding layer is embedded in the cap substrate. The semiconductor device structure also includes a substrate structure. The substrate structure includes a substrate and a second bonding layer formed on the substrate. The substrate includes a micro-electro-mechanical system (MEMS) substrate or a semiconductor substrate. The cap structure is bonded to the substrate structure by bonding the first bonding layer and the second bonding layer.

BACKGROUND

Micro-electro mechanical system (MEMS) devices have recently been developed. MEMS devices include devices fabricated using semiconductor technology to form mechanical and electrical features. Examples of the MEMS devices include gears, levers, valves, and hinges. The MEMS devices are implemented in accelerometers, pressure sensors, microphones, actuators, mirrors, heaters, and/or printer nozzles.

Although existing devices and methods for forming the MEMS devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

The making and using of various embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the various embodiments can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

FIGS. 1A-1Ishow cross-sectional representations of various stages of forming a cap structure100, in accordance with some embodiments of the disclosure.

Referring toFIG. 1A, a cap substrate102is provided. In some embodiments, cap substrate102is made of silicon or other elementary semiconductor. In some embodiments, cap substrate102is made of silicon carbide, gallium arsenic, indium arsenide, indium phosphide, or other applicable materials.

Afterwards, a first photoresist (PR) layer120is formed on cap substrate102. In some embodiments, first PR layer120is a positive resist (positive tone resist). The positive resist is characterized by the exposed regions becoming more soluble in a developer solution.

After first photoresist layer120is formed, first photoresist layer120is patterned by a patterning process to form a patterned first photoresist layer120as shown inFIG. 1Bin accordance with some embodiments of the disclosure. The patterning process includes a photolithography process and an etching process. The photolithography processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

After patterned first photoresist layer120is formed, a portion of cap substrate102is removed by using patterned first photoresist layer120as a mask as shown inFIG. 1Cin accordance with some embodiments of the disclosure. As a result, trenches104are formed in cap substrate102. In some embodiments, cap substrate102is removed by a dry etching process or a wet etching process.

After a portion of cap substrate102is removed, patterned first photoresist layer120is removed as shown inFIG. 1Din accordance with some embodiments of the disclosure. In some embodiments, patterned first photoresist layer120is removed by a dry etching process or a wet etching process.

After patterned first photoresist layer120is removed, bonding material106is filled into trenches104and on cap substrate102as shown inFIG. 1Ein accordance with some embodiments of the disclosure. In some embodiments, bonding material106is made of eutectic material, such as germanium (Ge), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), indium (In), tin (Sn) or silicon (Si).

After bonding material106is formed, a planarization process is performed to remove the excess of bonding material106as shown inFIG. 1Fin accordance with some embodiments of the disclosure. As a result, first bonding layer108is formed. In some embodiments, a top surface of first bonding layer108is substantially level with a top surface of cap substrate102. In some embodiments, planarization process is a chemical polishing (CMP) process.

After the planarization process is performed, a second photoresist layer130is formed on first bonding layer108and cap substrate102as shown inFIG. 1Gin accordance with some embodiments of the disclosure.

After second photoresist layer130is formed, second photoresist layer130is patterned by a patterning process to form a patterned second photoresist layer130as shown inFIG. 1Hin accordance with some embodiments of the disclosure. Patterned second photoresist layer130is used to protect underlying first bonding layer108from being etched. In some embodiments, patterned second photoresist layer130covers first bonding layer108and a portion of cap substrate102.

After patterned second photoresist layer130is formed, an etching process is performed to remove unmasked regions as shown inFIG. 1Iin accordance with some embodiments of the disclosure. As a result, first bonding layer108is formed in an extending portion102aof cap substrate102. Afterwards, patterned second photoresist layer130is removed and cap structure100is formed.

It should be noted that first bonding layer108is embedded in cap substrate102. In some embodiments, first bonding layer108is made of germanium (Ge), and cap substrate102is made of silicon (Si). Therefore, germanium (Ge) is surrounded by silicon (Si).

It should be noted that a length L2of patterned second photoresist layer130is larger than a length L1of first bonding layer108. Therefore, a portion of cap substrate102underlying patterned photoresist layer130is not removed. As a result, an embedded first boning layer108is formed. In some embodiments, patterned second photoresist layer130has the length L2in a range from about 2 μm to about 2000 μm. In some embodiments, first bonding layer108has the length L1in a range from about 1 μm to about 1000 μm. In some embodiments, a ratio (L2/L1) of the length L2to the length L1is in a range from about 1 to about 5.

First bonding layer108is surrounded by extending portion102aof cap substrate102. In some embodiments, a height of extending portion102ais substantially equal to a height of first bonding layer108. In some embodiments, a distance W1between an edge of first bonding layer108and an edge of extending portion102ais in a range from about 0.1 μm to about 1000 μm. In some embodiments, first bonding layer108has a height H1in a range from about 0.1 μm to about 400 μm. In some embodiments, the extending portion102ahas a height (H2). In some embodiments, the height (H2) of extending portion102ais greater than the height (H1) of first bonding layer108.

In some embodiments, a ratio (L1/H1) of the length L1to the height H1is in a range from about 0.0025 to about 10000. In some embodiments, a ratio (W1/L1) of the distance W1to the length L1is in a range from about 0.0001 to about 200.

FIG. 2shows a top-view of a cap structure100, in accordance with some embodiments of the disclosure.FIG. 1Iis a top-view taken along AA′ line ofFIG. 2. As shown inFIG. 2, first bonding layer108and extending portion102arespectively have a ring structure to form a cavity150. First bonding layer108is sandwiched by extending portion102aof cap substrate102. In a top view, first bonding layer108and extending portion102aform three concentric rings. The concentric rings may have a shape that is a circle, rectangle, ellipse, square, or polygon when seen from a top view.

FIG. 3Ashows a cross-sectional representation of a semiconductor device structure10, in accordance with some embodiments of the disclosure. Semiconductor device structure10includes cap structure100obtained fromFIG. 1Iand a substrate structure400. Substrate structure400is bonded to cap structure100. Substrate structure400includes a semiconductor substrate302and a micro-electro-mechanical system (MEMS) substrate202.

Cap structure100is configured to provide a protection purpose for MEMS substrate202. In some embodiments, cap substrate102includes extending portion102a(or called stand-off features) to enclose and provide cavity150for the MEMS devices. In some embodiments, cap structure100does not include an integrated circuit.

MEMS substrate202may be a silicon wafer including MEMS devices, features and/or functionalities. In some embodiments, MEMS substrate202includes a number of MEMS devices. MEMS substrate202may alternatively or additionally include other elementary semiconductor, such as germanium (Ge). MEMS substrate202may also include a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, indium phosphide, or the like.

As shown inFIG. 3A, MEMS substrate202includes a movable element202mand fixed element202f. Movable element202mis also called as a proof mass. Movable element202mis supported by middle third bonding layer306c. In some embodiments, movable element202mis made of silicon-containing material, such as polysilicon, amorphous silicon, or crystalline silicon.

MEMS substrate202has a first surface facing cap structure100and a second surface facing semiconductor substrate302. In some embodiments, a second bonding layer204is formed on the first surface of MEMS substrate202. In some embodiments, a third bonding layer306is formed on semiconductor substrate302, and a metal layer304is formed in third bonding layer306. A through-silicon-via (TSV)206is formed in MEMS substrate202to electrically connect second bonding layer204to metal layer304. Third bonding layer306is used as an insulating layer.

Second bonding layer204includes germanium (Ge), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), indium (In), tin (Sn), silicon (Si) or combinations thereof. Second bonding layer204is formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, plating or other applicable processes. The patterns of second bonding layer204are defined by a photolithography process and an etching process. In some embodiments, second bonding layer204is a part of an interconnect structure. The interconnect structure includes conductive features, such as conductive lines, vias, or conductive pads, formed in an insulating material.

Semiconductor substrate302includes a semiconductor device such as an integrated circuit (IC). The IC includes complementary MOSFET (CMOS), a CMOS imaging sensor (CIS), a MEMS, and/or other applicable active and/or passive devices. In some embodiment, semiconductor substrate302includes an IC (or portion thereof) designed and formed by a CMOS-based processes. Semiconductor substrate302including a device formed using other semiconductor fabrication technologies is also within the scope of the described method and present disclosure. In some embodiments, semiconductor substrate302is a silicon wafer. Semiconductor substrate302may alternatively or additionally include other elementary semiconductor, such as germanium (Ge). Semiconductor substrate302may also include a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, indium phosphide, or the like.

Metal layer304includes aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), indium (In), tin (Sn), or combinations thereof. Meatl layer304is formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, plating or other applicable processes. In some embodiments, metal layer304is a part of an interconnect structure. The interconnect structure includes conductive features, such as conductive lines, vias, or conductive pads, formed in an insulating material.

In some embodiments, third bonding layer306is made of dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, spin-on glass (SOG), low-k material, fluoride-doped silicate glass (FSG), carbon doped silicon oxide or other applicable materials. In some embodiments, third bonding layer306includes multiple dielectric layers of dielectric materials.

As shown inFIG. 3A, substrate structure400is bonded to cap structure100by bonding first bonding layer108and second bonding layer204. More specifically, cap substrate102is bonded to MEMS substrate202by bonding first bonding layer108and second bonding layer204. In some embodiments, the bonding is performed through an eutectic bonding process. The eutectic bonding process is performed with a bonding force at a certain temperature. As a result, an eutectic alloy is formed from first bonding layer108and second bonding layer204.

During the eutectic bonding process, melted alloy has a liquid phase which is easily spilled out. Therefore, a portion of first bonding layer108and/or second bonding layer204may be squeezed by the bonding force. In addition, first bonding layer (such as Ge)108is easily oxidized and hydrolyzed when it is exposed. The squeezing, oxidation and hydrolysis problems may affect the quality and reliability of semiconductor device structure10.

In order to solve the above problems, first bonding layer108is surrounded by cap substrate102. In other words, there is a distance W1between the edge of first bonding layer108and the edge of extending portion102a. More specifically, the edge of first bonding layer108is not aligned with the edge of extending portion102a. When the eutectic bonding process is performed, the melted alloy with the liquid phase between first bonding layer108and second bonding layer204is blocked by cap substrate102. Therefore, squeezing problem is avoided. In other words, cap substrate102prevents the melted alloy from spilling out. In addition, due to the protection of cap substrate102and extending portion102a, first bonding layer108is prevented from being oxidized and hydrolyzed.

In some embodiment, the eutectic bonding process is performed at a temperature depending on an eutectic temperature of first bonding layer108and second bonding layer204. In some embodiments, the bonding temperature is higher than the eutectic temperature in a range from about 1 fold to about 1.1 folds. In some embodiments, when first bonding layer108is made of germanium (Ge), second bonding layer204is made of aluminum (Al), the eutectic bonding process is performed at a temperature in a range from about 420° C. to about 460° C. In some embodiment, the eutectic bonding process is performed at a pressure in a range from about 30 kN to about 300 kN. The eutectic bonding process may be performed in a controlled atmosphere (e.g., in the presence of a forming gas). Example forming gases include Ar, N2, H2, He, N2/H2, or combinations thereof. An alignment process is performed prior to the eutectic bonding process.

In some embodiments, a surface cleaning process is performed prior to the eutectic bonding process. The surface clean process may include a wet etching process, a dry etching process, or combinations thereof. For example, the wet etching process includes exposure to hydrofluoric acid (HF). The dry etching process includes argon sputtering and plasma etching process. In some embodiments, a post-bonding thermal process is performed.

FIGS. 3B-3Eshow cross-sectional representations of a semiconductor device structure10, in accordance with some embodiments of the disclosure.

As shown inFIG. 3B, movable element202mis supported by a middle third bonding layer306c. Two metal layers304are formed adjacent to middle third bonding layer306cand on semiconductor substrate302. Two metal layers304below middle third bonding layer306care used as stoppers. The stoppers are configured to prevent movable element202mfrom moving too far in the Z-direction and contacting other components or parts during a shock event.

As shown inFIG. 3C, an oxide layer310is formed on metal layer304. Oxide layer310is used as the stopper. A capacitor structure is constructed by metal layer304, oxide layer310and movable element202m. On the left side of middle third bonding layer306c, a first capacitor structure is formed. On the right side of middle third bonding layer306c, a second capacitor structure is formed. An acceleration difference between the left side and right side of movable element202mis obtained by determining the capacitance differences between the first capacitor structure and the second capacitor structure.

As shown inFIG. 3D, one oxide layer310is disposed between two metal layers304. Therefore, capacitor structure is constructed by two metal layers304and one oxide layer310. Similar toFIG. 3C, on the left side of middle third bonding layer306c, a first capacitor structure is formed. On the right side of middle third bonding layer306c, a second capacitor structure is formed. Therefore, an acceleration difference between the left side and right side of movable element202mis obtained by determining the capacitance differences between the first capacitor structure and the second capacitor structure. InFIG. 3C, oxide layer310is formed on metal layer304, but inFIG. 3D, oxide layer310is formed between two metal layers304.

As shown inFIG. 3E, on the left side of middle third bonding layer306c, oxide layer310is formed adjacent to metal layer304. On the right side of middle third bonding layer306c, another oxide layer310is formed adjacent to another metal layer304. A capacitor structure is constructed by two metal layers304and movable element202m. Oxide layer310inFIG. 3Eis also used as the stopper.

FIGS. 4A-4Dshow cross-sectional representations of various stages of forming a cap structure100′, in accordance with some embodiments of the disclosure. The structure inFIG. 4Ais the same as the structure inFIG. 1I. First bonding layer108is embedded in cap substrate102.

Afterwards, a third photoresist layer140is formed on first bonding layer108and cap substrate102as shown inFIG. 4Bin accordance with some embodiments of the disclosure.

After third photoresist layer140is formed, third photoresist layer140is patterned by a patterning process to form a patterned first photoresist layer140as shown inFIG. 4Cin accordance with some embodiments of the disclosure. Patterned third photoresist layer140is used to protect underlying first bonding layer108and a portion of cap substrate102from being etched. In some embodiments, patterned third photoresist layer140covers a top surface of extending portion102awithout coving the sidewalls of extending portion102a.

After patterned third photoresist layer140is formed, an etching process is performed to remove unmasked regions as shown inFIG. 4Din accordance with some embodiments of the disclosure. As a result, the height of extending portion102ais elongated from H1to H2. In some embodiments, the height (H2) of extending portion102ais greater than the height (H1) of first bonding layer108.

A portion of cap substrate102is removed to form a number of cap stopper112surrounded by extending portion102a. Cap stopper112is configured to prevent movable element202mfrom moving too far in the Z-direction and contacting other components or parts during a shock event. Afterwards, patterned third photoresist layer140is removed and cap structure100′ is formed.

FIG. 5shows a cross-sectional representation of a semiconductor device structure, in accordance with some embodiments of the disclosure. Substrate structure400is bonded to cap structure100′ obtained fromFIG. 4Dby bonding first bonding layer108and second bonding layer204. More specifically, cap substrate102is bonded to MEMS substrate202by bonding first bonding layer108and second bonding layer204. In some embodiments, the bonding is performed through an eutectic bonding process. As a result, an eutectic alloy is formed between first bonding layer108and second bonding layer204.

FIGS. 6A-6Dshow cross-sectional representations of various stages of forming a cap structure100″, in accordance with some embodiments of the disclosure. The structure inFIG. 6Ais the same as the structure inFIG. 1I. First bonding layer108is embedded in cap substrate102.

Afterwards, a third photoresist layer140is formed on first bonding layer108and cap substrate102as shown inFIG. 6Bin accordance with some embodiments of the disclosure.

After third photoresist layer140is formed, third photoresist layer140is patterned by a patterning process to form a patterned third photoresist layer140as shown inFIG. 6Cin accordance with some embodiments of the disclosure. Patterned third photoresist layer140is used to protect underlying first bonding layer108and a portion of cap substrate102from being etched. In some embodiments, the top surface and the sidewalls of extending portion102aare covered by patterned third photoresist layer140.

After patterned third photoresist layer140is formed, an etching process is performed to remove unmasked regions as shown inFIG. 6Din accordance with some embodiments of the disclosure. As a result, extending portion102ahas a stair-like shape. In addition, a number of cap stopper112is formed and surrounded by extending portion102a.

As shown inFIG. 6D, stair-like shaped extending portion102ahas a first stair having a height H3and a second stair having a height H1. In some embodiments, a ratio (H3/H1) of the height H3to the height H1is in a range from about 0.002 to about 100.

FIG. 7shows a cross-sectional representation of a semiconductor device structure, in accordance with some embodiments of the disclosure. Substrate structure400is bonded to cap structure100″ obtained fromFIG. 6Dby bonding first bonding layer108and second bonding layer204. More specifically, cap substrate102is bonded to MEMS substrate202by bonding first bonding layer108and second bonding layer204. In some embodiments, the bonding is performed through an eutectic bonding process.

FIGS. 8A-8Bshow cross-sectional representations of a semiconductor device structure20, in accordance with some embodiments of the disclosure.

As shown inFIG. 8A, semiconductor substrate302has a top surface302aand a bottom surface302b. MEMS substrate202is formed on top surface302aof semiconductor substrate302. A cap structure100ais bonded to substrate structure400by bonding second bonding layer204to semiconductor substrate302. Movable element202mis surrounded by extending portion102aof cap substrate102of cap structure100a.

It should be noted that first bonding layer108is embedded in cap substrate102. Therefore, during the eutectic bonding process, the melted alloy with the liquid phase is not squeezed by the bonding force. In addition, extending portion102aof cap substrate102provides a protection to first bonding layer108, and therefore first bonding layer108is prevented from being oxidized and hydrolyzed.

Embodiments of a semiconductor device structure are provided. A cap structure includes a cap substrate and a first bonding layer embedded in cap substrate. A substrate structure includes a MEMS substrate and a semiconductor substrate, and a second bonding layer is formed on the MEMS substrate. The cap structure is bonded to the semiconductor substrate or the MEMS substrate by bonding first bonding layer and the second bonding layer by an eutectic bonding process to form the semiconductor device structure. Because the first bonding layer is embedded in the cap substrate, a portion of first bonding layer and/or second bonding layer is not squeezed by the eutectic bonding process. Therefore, the squeezing problem is avoided. In addition, first bonding layer is not easily oxidized and hydrolyzed when it is protected by the surrounding cap substrate. As a result, an oxidation and hydrolysis problems are also resolved. Furthermore, the quality and reliability of semiconductor device structure are improved.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a cap structure. The cap structure includes: a first bonding layer and a cap substrate, and the first bonding layer is embedded in the cap substrate. The semiconductor device structure also includes a substrate structure. The substrate structure includes a substrate and a second bonding layer formed on the substrate. The substrate includes a micro-electro-mechanical system (MEMS) substrate or a semiconductor substrate. The cap structure is bonded to the substrate structure by bonding the first bonding layer and the second bonding layer.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface and a bottom surface. The semiconductor device structure also includes a micro-electro-mechanical system (MEMS) substrate formed on the top surface of the semiconductor substrate. The MEMS substrate has a first surface and a second surface and the second surface is in contact with the top surface of the semiconductor substrate. The semiconductor device structure further includes a cap substrate formed on the top surface of the semiconductor substrate or the first surface of the MEMS substrate. The cap substrate has an embedded bonding layer, and the cap substrate is bonded to the semiconductor substrate or the MEMS structure by the embedded bonding layer.

In some embodiments, a method for forming a semiconductor device structure is provided. The method includes providing a cap substrate and forming a bonding layer in the cap substrate. The method also includes forming a first photoresist layer on the cap substrate to cover the bonding layer and a portion of the cap substrate. The method further includes etching the cap substrate by using the first photoresist layer as a mask to form an extending portion. The bonding layer is embedded in the extending portion.