SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A semiconductor device includes a metal line and a metal pad formed at different integration levels of a semiconductor substrate, and an isolation layer by which the metal line and the metal pad are spaced apart from each other. The semiconductor device prevents short-circuiting between the metal pad and the metal line although the isolation layer is dislocated.

DESCRIPTION OF EMBODIMENTS

FIG. 2is a cross-sectional view illustrating a semiconductor device according to an embodiment.FIG. 3is a cross-sectional view illustrating a package ball bonded to the semiconductor device according to an embodiment.

Referring toFIG. 2, the semiconductor device according to the embodiment includes (i) a first metal pad116aand a second metal pad116bthat are spaced apart from each other and provided over an interlayer insulation film108, (ii) a trench T disposed between the first metal pad116aand the second metal pad116band formed in the interlayer insulation film108, and (iii) a metal line114formed in the trench T.

The semiconductor device may further include an isolation layer120formed over the metal line114and formed between the first metal pad116aand the second metal pad116b. In addition, the semiconductor device may further include protective layers118that are formed between the isolation layer120and a top surface of each of the first metal pad116aand the second metal pad116b.In this case, the semiconductor device may further include a first metal contact110aformed to pass through the interlayer insulation film108and coupled to a lower part of the first metal pad116a;and a second metal contact110aformed to pass through the interlayer insulation film108and coupled to a lower part of the second metal pad116b.

The semiconductor device may further include a first lower line102aconnected to a lower part of the first metal contact110a;and a second lower line102bconnected to a lower part of the second metal contact110b.In addition, the semiconductor device may further include a planarized interlayer insulation film104provided between the first lower line102aand the second lower line102b;and a protective layer106formed over the interlayer insulation film104.

The semiconductor device may further include a third metal contact111disposed between the metal line114and an surface of the trench T. The isolation layer120may include an insulation film such as a High Density Plasma (HDP) film. A passivation layer122may be formed over the isolation layer120. The passivation layer122may include a Polymide Isoindro Quirazorindione (PIQ).

The semiconductor device may further include a bonding region124configured to at least partially expose the first metal pad116aand the second metal pad116band formed at both sides of the isolation layer120.

As described above, the metal line114, the first and second metal pads116a,116bof the semiconductor device are spaced apart from each other by the isolation layer120, and are formed at different levels, such that the semiconductor device can reduce short-circuiting between the metal line114, the first and second metal pads116a,116beven when the isolation layer120, the first and second metal pads116a,116bare pushed toward the metal line114by a pressure generated when a package ball is bonded to the bonding region124.

FIG. 3is a cross-sectional view illustrating the package ball bonded to the semiconductor device according to an embodiment.

Referring toFIG. 3, if the package ball is bonded to the bonding region124, a pressure is imposed in arrow directions, such that the isolation120is shifted. However, the metal line114is prevented from being short-circuited to the first metal pad116because the metal line114and the first metal pad116aare formed at different levels. In addition, the isolation layer120is formed between the first metal pad116aand the second metal pad116band over the metal line114without interruption by the metal line114.

Accordingly, the semiconductor device according to the embodiment can prevent the isolation layers120from being interrupted by the metal line114and, at the same time, can also prevent the metal line114from coming into short circuit with the first metal pad116a.

FIGS. 4ato4fare cross-sectional views illustrating a method for forming the semiconductor device according to embodiments.

Referring toFIG. 4a, a first lower line102aand a second lower line102bare formed over a semiconductor substrate100. Subsequently, a planarization process such as Chemical Mechanical Polishing (CMP) is performed in a manner that a specific portion between the first lower line102aand the second lower line102bis filled and upper portions of the first lower line102aand the second lower line102bare exposed, resulting in formation of the interlayer insulation film104.

Thereafter, a protective layer106is formed over the interlayer insulation film104, and an interlayer insulation film108is formed over the protective layer106. Subsequently, the interlayer insulation film108is etched to expose the lower line102in a manner that a first contact hole107aand a second contact hole107bare formed, The interlayer insulation film108and the protective layer106interposed between the first contact hole107aand the second contact hole107bare selectively etched, so that a trench T is formed between the first and the second contact holes107a-b.

Referring toFIG. 4b, a metal layer109is formed over the interlayer insulation film108. The first and second contact hole107a,107bis filled with the conductive layer109, and the conductive layer109is formed in the trench T, e.g., in a liner type.

Referring toFIG. 4c, the planarization process such as CMP is performed against the conductive layer109to expose the interlayer insulation film108, such that not only the first metal contact110a and the second metal contact110bare configured to fill the contact hole, but also a third metal contact111is formed in the trench T.

Referring toFIG. 4d, a metal layer112is formed over the interlayer insulation film108. In this case, the trench T is filled with the metal layer112.

Referring toFIG. 4e, after a mask pattern (not shown) is formed to open a trench formed in the metal layer112, the metal layer112is etched using the mask pattern (not shown) as an etch mask. As a result, first metal pad and second metal pad are formed at a specific portion which was covered with the mask pattern (not shown). In addition, the metal layer112which was covering the trench T is exposed by the mask pattern (not shown) to form a metal line114.

In more detail, the first metal pad116aconnected to the first metal contact110a and the second metal pad116bconnected to the second metal contact110bare formed over the interlayer insulation film108. The metal layer112filled in the trench T is partially etched to form the metal line114at least partially filling in the trench T.

Referring toFIG. 4f, a protective layer118is formed over the first metal pad116aand the second metal pad116b.An isolation layer120is formed not only over the protective layer118but also over the metal line114and is also formed between the first metal pad116aand the second metal pad116b.The isolation layer120may include an insulation film formed using a High Density Plasma (HDP) process. Subsequently, a passivation layer122protecting the chip is formed over the isolation layer120, and one end of each the first metal pad116aand the second metal pad116bare opened so that a bonding region124is formed. In this case, a package ball is bonded to the bonding region124.

As described above, the semiconductor device according to the embodiment forms the isolation pattern120in such a manner of continuously extending between neighboring metal pads116a-band thus prevents the isolation pattern120from being interrupted by the metal line114. In addition, even if a bonding pressure is generated when the package ball is bonded to the bonding region, short-circuiting between the metal pads116and the metal line114can be prevented.

FIG. 5is a circuit diagram illustrating a semiconductor module according to one embodiment.

Referring toFIG. 5, a semiconductor module includes a plurality of semiconductor devices mounted to a module substrate, a command link for enabling each semiconductor device to receive control signals (for example, an address signal (ADDR), a command signal (CMD), a clock signal (CLK)) from an external controller (not shown), and a data link coupled to a semiconductor device so as to transmit data. In this case, the semiconductor elements may be exemplarily implemented as the semiconductor devices shown inFIG. 2. The command link and the data link may be formed to be identical or similar to those of general semiconductor modules. Although eight semiconductor chips are mounted to the front surface of the module substrate shown inFIG. 5, the semiconductor chips can also be mounted to the back surface of the module substrate. That is, the semiconductor chips can be mounted to one side or both sides of the module substrate, and the number of mounted semiconductor chips is not limited to that shown inFIG. 2. In addition, a material or structure of the module substrate is not limited to those ofFIG. 2, and the module substrate may also be formed of other materials or structures.

FIG. 6is a block diagram illustrating a semiconductor system according to an embodiment. Referring toFIG. 6, the semiconductor system includes at least one semiconductor module including a plurality of semiconductor chips, and a controller for providing a bidirectional interface between each semiconductor module and an external system (not shown) so as to control the operations of the semiconductor module. In addition, the semiconductor system may further include a command link and a data link that are configured to electrically interconnect the semiconductor module and the controller. The processor may be identical or similar in function to a controller for controlling a plurality of semiconductor modules for use in a general data processing system, and as such a detailed description thereof will herein be omitted for convenience of description. In one embodiment, the semiconductor device may be, for example, a semiconductor device shown inFIG. 2, and the semiconductor module may be, for example, a semiconductor module shown inFIG. 5.

FIG. 7is a block diagram illustrating an electronic unit according to an embodiment. Referring toFIG. 7, the electronic unit includes a semiconductor system and a processor electrically coupled to the semiconductor system. The semiconductor system may be the same as that ofFIG. 6. In an embodiment, the processor may include a Central Processing Unit (CPU), a Micro Processor Unit (MPU), a Micro Controller Unit (MCU), a Graphics Processing Unit (GPU), and a Digital Signal Processor (DSP).

In an embodiment, the CPU or MPU is configured in the form of a combination of an Arithmetic Logic Unit (ALU) serving as an arithmetic and logical operation unit and a Control Unit (CU) for controlling each unit by reading and interpreting a command. If the processor is a CPU or MPU, the electronic unit may include a computer or a mobile device. In addition, the GPU is used to calculate numbers having decimal points, and corresponds to a process for generating graphical data in real-time. If the processor is a GPU, the electronic unit may include a graphic device. In addition, DSP involves converting an analog signal (e.g., voice signal) into a digital signal at a high speed, using the calculated result, re-converting the digital signal into an analog signal, and using the re-converted result. The DSP mainly calculates a digital value. If the processor is a DSP, the electronic unit may include a sound and imaging device.

In an embodiment, the processor may include an Accelerate Calculation Unit (ACU), and may be configured in the form of a CPU integrated into the GPU, such that it serves as a graphics card.

FIG. 8is a block diagram illustrating an electronic system according to an embodiment. Referring toFIG. 8, an electronic system may include one or more interfaces electrically coupled to the electronic unit. The interface may include a monitor, a keyboard, a pointing device (mouse), a USB, a display or a speaker. However, the scope of the interface is not limited thereto and includes other examples or modifications.

As is apparent from the above description, the semiconductor device and the method for forming the same according to the embodiments form a metal pad and a metal line at different integration levels in such a manner that the metal pad and the metal line are doubly separated from each other by the level difference and by the isolation layer. Thus, short-circuiting between the metal pad and the metal line is prevented although the isolation layer is dislocated by a bonding pressure.

Those skilled in the art will appreciate that embodiments may be carried out in other specific ways than those set forth herein without departing from the spirit and essential characteristics of the embodiment. The above exemplary embodiments are therefore to be construed in all aspects as illustrative and not restrictive.

The above embodiments are illustrative and not limitative. Various alternatives and equivalents are possible. The embodiments are not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor are the embodiments limited to any specific type of semiconductor device. For example, the embodiments may be implemented in a dynamic random access memory (DRAM) device or non-volatile memory device.