Source/drain metal contact and formation thereof

The present disclosure provides a method for semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.

For example, fabrication of various device-level metal contacts becomes more challenging as feature sizes continue to decrease. At smaller length scales, metal contacts need to fit into small spaces while minimizing contact resistances. Although current methods of forming device-level contacts are generally adequate, they have not been entirely satisfactory in all aspects.

DETAILED DESCRIPTION

Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The present disclosure is directed to, but not otherwise limited to, a method to perform semiconductor fabrication, for example an aspect of semiconductor fabrication pertaining to source/drain metal contact formation. To illustrate the various aspects of the present disclosure, a FinFET fabrication process is discussed below as a non-limiting example. In that regard, a FinFET device is a fin-like field-effect transistor device, which has been gaining popularity in the semiconductor industry. The FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with one or more FinFET examples to illustrate various embodiments of the present disclosure, but it is understood that the application is not limited to the FinFET device, except as specifically claimed. In other words, the various aspects of the present disclosure may be applied in the fabrication of two-dimensional planar transistors too.

Referring toFIG. 1, a perspective view of an example semiconductor structure10is illustrated. The semiconductor structure10includes an N-type FinFET device structure (NMOS)15and a P-type FinFET device structure (PMOS)25, both disposed on a substrate52. The substrate52may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate52may include other elementary semiconductor materials such as germanium. In some embodiments, the substrate52is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate52is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate52includes an epitaxial layer. For example, the substrate52may include an epitaxial layer overlying a bulk semiconductor.

The semiconductor structure10also includes one or more fin structures54(e.g., Si fins) that extend from the substrate52in the Z-direction and surrounded by spacers55in the Y-direction. The fin structures54are elongated in the X-direction and may optionally include germanium (Ge). The fin structure54may be formed by using suitable processes such as photolithography or etching processes. In some embodiments, the fin structure54is etched from the substrate52using dry etch or plasma processes. In some other embodiments, the fin structure54can be formed by a double-patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density. The fin structure54also includes an epitaxially-grown feature12, which may (along with portions of the fin structure54) serve as the source/drain of the semiconductor structure10.

An isolation structure58, such as a shallow trench isolation (STI) structure, is formed to surround the fin structure54. In some embodiments, a lower portion of the fin structure54is surrounded by the isolation structure58, and an upper portion of the fin structure54protrudes from the isolation structure58, as shown inFIG. 1. In other words, a portion of the fin structure54is embedded in the isolation structure58. The isolation structure58prevents electrical interference or crosstalk.

The semiconductor structure10further includes a gate stack including a gate electrode60and a gate dielectric layer below the gate electrode60(not shown). The gate electrode60may include polysilicon or metal. Metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other applicable materials. Gate electrode60may be formed in a gate last process (or gate replacement process). Hard mask layers62and64may be used to define the gate electrode60. A dielectric layer65may also be formed on the sidewalls of the gate electrode60and over the hard mask layers62and64. The gate dielectric layer (not shown) may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, dielectric material(s) with high dielectric constant (high-k), or combinations thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or combinations thereof.

In some embodiments, the gate stack includes additional layers, such as interfacial layers, capping layers, diffusion/barrier layers, or other applicable layers. In some embodiments, the gate stack is formed over a central portion of the fin structure54. In some other embodiments, multiple gate stacks are formed over the fin structure54. In some other embodiments, the gate stack includes a dummy gate stack and is replaced later by a metal gate (MG) after high thermal budget processes are performed.

The gate stack may be formed by a deposition process, a photolithography process, and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods, and/or combinations thereof. The photolithography processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Alternatively, the photolithography process is implemented or replaced by other proper methods such as maskless photolithography, electron-beam writing, and ion-beam writing.

FinFET devices offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (also referred to as planar transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip. However, FinFET fabrication may still have challenges. For example, when forming metal contacts to connect an epitaxial source/drain feature, the metal contacts need to fit into small openings above the epitaxial source/drain feature while minimizing contact resistances. Some processes use a glue layer made of titanium nitride (TiN) or tantalum nitride (TaN) between metal contacts and the epitaxial source/drain feature to enhance adhesion therebetween, but the glue layer has higher resistivity than metal contacts, which in turn increases contact resistance. Further, some methods of depositing metal contacts suffer from bottle neck and voids problems in the opening above the epitaxial source/drain feature.

To reduce contact resistance and to avoid bottle neck and voids problems, the present disclosure utilizes unique fabrication process flows to allow metal contacts to be formed over an epitaxial source/drain feature without needing any glue layer. In some embodiments, a silicide layer is formed over an epitaxial source/drain feature, and a seed metal layer is formed over the silicide layer. The silicide layer and the seed metal layer are formed before a gate replacement process in some embodiments, and formed after a gate replacement process in other embodiments. A contact metal layer is then selectively formed such that it grows on a conductive surface (e.g., the seed metal layer) but not on dielectric surfaces. A fill metal layer may be formed over the contact metal layer to facilitate a subsequent CMP process. In some embodiments, the contact metal layer is formed directly on the silicide layer (without the intervening seed metal layer). The metal contacts formed herein improve device performances by lowering contact resistance and avoiding or minimizing bottle neck and voids problems.

The various aspects of the present disclosure will now be discussed below in more detail with reference toFIGS. 2, 3A-3G, 4A-4G, 5A-5G, and 6A-6Gbelow. In that regard,FIG. 2is a flowchart illustrating a method for fabricating a FinFET device,FIGS. 3A-3Eillustrate fragmentary cross-sectional side views of a portion of a FinFET device100at various stages of fabrication,FIGS. 4A-4Eillustrate fragmentary cross-sectional side views of a portion of a FinFET device200at various stages of fabrication,FIGS. 5A-5Eillustrate fragmentary cross-sectional side views of a portion of a FinFET device300at various stages of fabrication, andFIGS. 6A-6Eillustrate fragmentary cross-sectional side views of a portion of a FinFET device400at various stages of fabrication. It is understood that the cross-sectional views ofFIGS. 3A-3E, 4A-4E, 5A-5E, and 6A-6Ecorrespond to the cross-sectional views taken in the x-direction shown inFIG. 1, and as such they may be referred to as X-cuts.FIGS. 4F, 5F, and 6Fillustrate fragmentary top views of a portion of the FinFET devices200,300, and400, respectively.FIGS. 4G, 5G, and6G illustrate fragmentary cross-sectional Y-cut views of a portion of the FinFET devices200,300, and400, respectively.

Now referring toFIG. 2, which illustrates a method70for fabricating a FinFET device100according to embodiments of the present disclosure. The method70is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in the method70. Additional steps can be provided before, during, and after the method70, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. The method70is described below in conjunction withFIGS. 3A-3F, which are diagrammatic fragmentary cross-sectional views of the FinFET device100at different stages of fabrication according to embodiments of the present disclosure.

At the beginning of the method70(FIG. 2), a starting FinFET device (or FinFET structure)100is provided. Referring now toFIG. 3A, the FinFET device100includes fin structure110, which may be similar to the fin structure54discussed above with reference toFIG. 1. The fin structure110is disposed on a substrate (e.g., the substrate52, not shown inFIG. 3A) and may include a semiconductor material such as silicon or silicon germanium. In some embodiments, portions of the fin structure110serve as channel regions of transistors.

The FinFET device100also includes one or more dummy gate stacks130. Each dummy gate stack130may include one or more material layers, such as an oxide layer (i.e., a dummy gate dielectric layer), a poly-silicon layer (i.e., a dummy gate electrode), a hard mask layer, a capping layer, and/or other suitable layers. During fabrication, a gate replacement process will be performed to replace the dummy gate stacks130with metal gate stacks150, as described further below. In other words, the dummy gate stacks130are formed as a placeholder before forming other components, e.g., source/drain features. Once the other components have been formed, the dummy gate stacks130are removed and metal gate stacks are formed in their places. Each dummy gate stack130may be surrounded on its sidewalls by gate spacers132. The gate spacers132may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a low-k material (e.g., a dielectric material having a smaller dielectric constant than silicon dioxide), and/or other suitable dielectric materials. The gate spacers132may be a single layered structure or a multi-layered structure. As shown inFIG. 3A, each gate spacer132includes an inner layer (e.g., a low-k material right next to the gate spacer132) and an outer layer (further from gate spacer132). An opening136separates the two gate stacks130inFIG. 3A. In some embodiments, a width of the opening136is about 8 to about 15 nm.

In step72of the method70(FIG. 2), a source/drain feature120is formed in the opening136and on the fin structure110. The source/drain feature120may be formed by any suitable techniques, such as etching processes followed by one or more epitaxy processes. In one example, one or more etching processes are performed to remove portions of the fin structure110to form a recess therein. A cleaning process may be performed to clean the recess with a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow an epitaxial feature in the recess. Therefore, the source/drain feature120is sometimes called an epitaxial source/drain feature or simply an epitaxial feature, similar to the epitaxially-grown feature12shown inFIG. 1. The source/drain feature120may be suitable for a p-type FinFET device (e.g., a p-type epitaxial material) or alternatively, an n-type FinFET device (e.g., an n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epi SiGe), where the silicon germanium is doped with a p-type dopant such as boron, germanium, indium, and/or other p-type dopants. The n-type epitaxial material may include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC), where the silicon or silicon carbon is doped with an n-type dopant such as arsenic, phosphorus, and/or other n-type dopant.

Still referring toFIG. 3A, in step74of the method70(FIG. 2), a silicide layer140is formed over the source/drain feature120. In some embodiments, the silicide layer140is formed to wrap around the source/drain feature120(e.g., as shown in the Y-cut view ofFIG. 3G). In many embodiments, the silicide layer140includes titanium silicide (TiSi), cobalt silicide (CoSi), ruthenium silicide (RuSi), nickel silicide (NiSi), TiSiGe, CoSiGe, RuSiGe, NiSiGe, other suitable silicides, or combinations thereof. Different materials may be used depending on the application. In an example, titanium silicide is used in an n-type transistor, and cobalt silicide is used in a p-type transistor. The silicide layer140may be formed by any suitable method. For example, a metal layer (e.g., nickel) may be deposited over the device100by a deposition process such as CVD, ALD, PVD, other suitable processes, or combinations thereof. Then, the device100is annealed to allow the metal layer and the semiconductor materials of the source/drain feature120to react and form the silicide layer140. Thereafter, the un-reacted metal layer is removed, leaving the silicide layer140over the source/drain feature120. In some examples, the silicide layer140may be formed to a thickness of about 5 nm to about 7 nm, which may range from about 33% to about 90% of the width of the opening136.

In some embodiments, after formation, the silicide layer140is exposed to atmosphere or other air that contains oxygen. Thus, there is risk of the silicide layer140(e.g., TiSi) getting oxidized, which would increase its resistance. To prevent the silicide layer140from oxidation by surrounding air, its upper portion may be converted into a capping layer (not specifically shown inFIG. 3A), which may protect underlying TiSi. The capping layer can be formed using a suitable method, such as by exposing the silicide layer140to an inert gas or ammonia (NH3). The exposure leads to reactions that form chemicals such as titanium nitride in the upper portion of the silicide layer140, and the chemicals may block oxygen from reacting underlying TiSi. In some embodiments, the capping layer is about 2 to about 5 nm thick. Although the capping layer has a resistivity higher than that of a bottom-up metal layer160(described further below), the capping layer may still be used to avoid or minimize oxidation of the silicide layer140.

Still referring toFIG. 3A, in step76of the method70(FIG. 2), a seed metal layer142is formed on the silicide layer140in the opening136. In various embodiments, the seed metal layer142includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), or combinations thereof. The seed metal layer142may be a metal compound or alloy including Co, W, Ru, and/or Ni as well as other element(s) such as Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, Mo, Zn, K, Cd, Ru, In, Os, Si, or Ge, or combinations thereof. The seed metal layer142may be formed by a suitable method such as CVD, ALD or PECVD. In some embodiments, the seed metal layer142is about 1 to about 5 nm thick. If too thin, the seed metal layer142may not provide adequate adhesion between the silicide layer140and the bottom-up metal layer160. If too thick, the seed metal layer142may increase contact resistance because its resistivity is higher than that of the bottom-up metal layer160.

In some embodiments, the seed metal layer142is selectively formed such that it grows only on a conductive surface (e.g., the silicide layer140) but not on dielectric surfaces (e.g., the dummy gate stacks130and the gate spacers132). This helps with the trench filling performance, as well as avoiding any potential bottle necks in the opening136. The selective formation of the seed metal layer142may be realized by controlling process conditions including the pressure and/or the flow rate of a precursor used to form the seed metal layer142. For example, if W is used for the metal material of the seed metal layer142, it may be selectively deposited using process gases including tungsten fluoride, tungsten chloride, hydrogen, nitrogen, and silane, such as tungsten hexafluoride (WF6)/H2, WF6/H2/SiH4, tungsten chloride (WCl5)/H2, where the hydrogen gas facilitates the formation and deposition of W. The temperature may be in a range between about 250 degrees Celsius and about 500 degrees Celsius, the pressure may be in a range between about 5 mTorr and about 5 Torr, and the flow rate may be in a range between about 1 standard cubic centimeter per minute (sccm) to about 1000 sccm. As another example, if Co is used for the metal material of the seed metal layer142, Co(tBuDAD)2may be used for the deposition.

In other embodiments, however, the seed metal layer142may not be selective, and thus surfaces of the dummy gate stacks130and the gate spacers132may have metal materials deposited thereon, which may be removed by a chemical-mechanical planarization (CMP) process performed later. Regardless of whether the seed metal layer142is selective, it can be seen that the seed metal layer142is formed in the opening136over the silicide layer140.

In the present disclosure, the contact feature is laterally in direct contact with the dielectric layer, for example, the interfacial layer or the inter-metal layer. That is, the contact feature is free of a barrier layer and a glue layer (also called an adhesion layer in some instances). No barrier layer or glue layer (e.g., made of titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN)) is formed in the opening136over the silicide layer140(e.g., between the seed metal layer142and the silicide layer140). Compared to other devices that have a glue layer (in addition to or instead of the seed metal layer142), the seed metal layer142has a lower contact resistance with the silicide layer140because the seed metal layer142has a lower resistivity than a nitride-based glue layer.

Now referring toFIG. 3B, in step78of the method70(FIG. 2), a gate replacement process is performed to replace the dummy gate stacks130with metal gate stacks150. For example, during a “gate-last” process, the dummy gate stacks130are removed and metal gate stacks150are formed in their places. Forming the metal gate stacks150involves multiple processes such as etching and depositions. In an embodiment, an etching process is performed to form gate trenches by removing the dummy gate stacks130using a dry etching process, a wet etching process, an RIE, other suitable methods, or combinations thereof. A dry etching process may use chlorine-containing gases, fluorine-containing gases, and/or other etching gases. The wet etching solutions may include ammonium hydroxide (NH4OH), hydrofluoric acid (HF) or diluted HF, deionized water, tetramethylammonium hydroxide (TMAH), and/or other suitable wet etching solutions. In the gate replacement process, after the removal of the dummy gate stacks130, various metal layers such as work function metal layers and fill metal layers may be formed within the gate trenches, thereby forming the metal gate stacks150. The choice of material for a work function metal layer may be determined by an overall threshold voltage desired for the FET device100(e.g., n-type or p-type). Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, and/or other suitable p-type work function materials. Suitable n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, and/or other suitable n-type work function materials. Further, a fill metal layer formed over the work function metal layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), and/or other suitable materials. The fill metal layer may be formed by ALD, CVD, PVD, plating, and/or other suitable processes. After the gate replacement process, a CMP process may be performed to reduce a height of the metal gate stacks150to a desired level.

Still referring toFIG. 3B, in step80of the method70(FIG. 2), various middle end of the line (MEOL) processes are performed, including the formations of a sacrificial layer152, an interlayer dielectric (ILD) layer154, a trench156, and spacers158. Any suitable method(s) may be used to form these structures. In some embodiments, the sacrificial layer152is formed over the metal gate stacks150and the gate spacers132(e.g., using patterned deposition, or deposition plus photolithography or patterned etching). The sacrificial layer152may include a dielectric material such as silicon oxide, metal oxide, a high-k material, any other suitable material, or combinations thereof. The sacrificial layer152brings about various benefits. For example, the sacrificial layer152helps separate the metal gate stacks150from the to-be-formed over-burden metal170. In case there is any misalignment of the over-burden metal170with respect to the bottom-up metal layer160, the sacrificial layer152may prevent the over-burden metal170from electrically contacting the metal gate stacks150. The sacrificial layer152may also prevent the over-burden metal170from damaging the later formed spacers158. As a result, the sacrificial layer152increases the allowable processing window for forming the over-burden metal170.

The ILD layer154is formed over the device100using a suitable method. The ILD layer154may be a bottommost ILD layer and may be referred to as an ILD0layer. The ILD layer154includes a dielectric material, for example a low-k dielectric material in some embodiments, or silicon oxide in some other embodiments. After formation the ILD layer154is disposed adjacent the gate spacers132.

Still in step80, the trench156is formed over the opening136using any suitable etching method. Then, as shown inFIG. 3C, a thin layer of spacers158are formed in the trench156on the sidewalls of features including the gate spacers132, the sacrificial layer152, and the ILD layer154. The spacers158may include a dielectric material, for example, a low-k dielectric material in some embodiments, or silicon nitride (SiNx), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbide nitride (SIOCN), or combinations thereof in other embodiments. The spacers158may be formed by a deposition process followed by one or more etching and polishing processes. If not sufficiently protected, the spacer132may become inadvertently damaged during source/drain contact processes performed later. According to the various aspects of the present disclosure, the sacrificial layer152acts as a T-shaped helmet to protect the spacers158from potential etching damages.

Now referring toFIG. 3C, in step82of the method70(FIG. 2), a contact metal layer160is formed over the seed metal layer142via a contact formation process162. In various embodiments, the contact metal layer160includes cobalt (Co), tungsten (W), ruthenium (Ru), or combinations thereof. The contact metal layer160may be a metal compound or alloy including Co, W, and/or Ru as well as other element(s) such as Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, Mo, Zn, Ni, K, Cd, Ru, In, Os, Si, or Ge, or combinations thereof.

In some embodiments, the contact formation process162is a bottom-up growth approach; therefore, the contact metal layer160is also called a bottom-up metal layer. In other words, the contact formation process162is selective such that contact metal layer160is deposited on a conductive surface (e.g., the seed metal layer142) but not on dielectric surfaces (e.g., the sacrificial layer152, the ILD layer154, and the spacers158). The selective formation helps the contact metal layer160fill the opening136from bottom to top, improving filling performance. The selective formation also avoids any potential bottle necks to be formed near the top of the opening136, which if formed may lead to void(s) in the opening136. Due to the lack of bottle neck and voids issues, the contact metal layer160may fill up deep openings with high aspect ratios of height to width. In some examples, a total thickness of the silicide layer140and the contact metal layer160in the opening136is at least three times of a width of the contact metal layer160in the X-cut direction (shown inFIG. 3C). For example, the contact metal layer160may be formed to a thickness of about 15 nm to about 60 nm, which may range from about 100% to about 400% of the width of the opening136.

The selective formation of the contact metal layer160may be realized by controlling process conditions such as CVD conditions. For example, if W is used for the metal material of the contact metal layer160, it may be selectively deposited using CVD process gases such as WF6/H2, WF6/H2/SiH4, WCl5/H2, where the hydrogen gas facilities the formation and deposition of W. In some embodiments, a CVD process for forming the contact metal layer160is performed using conditions including: a process temperature between about 100 degrees Celsius and about 500 degrees Celsius, a gas pressure between about 1 Torr and about 50 Torr, a precursor gas flow rate between about 10 sccm and about 100 sccm, and a carrier gas (e.g., hydrogen) flow rate between about 5000 sccm and about 10000 sccm. The precursor having relatively low pressure, flow rate, and/or temperature allows the selective formation of the contact metal layer160, even though its growth speed would be slower than other conditions (e.g., higher pressure, flow rate, and/or temperature used in forming the over-burden metal170). Because the contact metal layer160is formed only in the small opening136, its growth speed is less of a concern than the over-burden metal170, which is to be formed in the larger trench156. Further, when the seed metal layer142has the same material as the contact metal layer160, the formation of the contact metal layer160may be configured to go faster than other situations where the seed metal layer142has a different material or is not present in the device100.

In other embodiments, the contact metal layer160may be selectively formed on a conductive surface using electroplating (ECP) or electron-less deposition (ELD). In ECP, a metal containing solution (e.g., copper mixed with an oxidizer) may be used under an applied voltage to extract the metal from the solution. The extracted metal (e.g., copper) is deposited on a conductive surface (e.g., the seed metal layer142), which acts as an electrode during the ECP process. In ELD, no voltage is needed, as the metal-containing solution also contains a reducing agent. The reducing agent reacts with a metal-containing material to produce metal (e.g., copper), which is then deposited on a conductive surface (e.g., the seed metal layer142). In some embodiments, the seed metal layer142and the contact metal layer160include different metals for optimized performance, such as the seed metal layer142being chosen for better adhesion with the silicide layer140while the contact metal layer160being chosen for lower resistivity and better integration with dielectric material without inter-diffusion concern. For example, the seed metal layer142includes tungsten while the contact metal layer160include copper. In another example, the seed metal layer142includes cobalt while the contact metal layer160include tungsten.

Regardless of whether the contact formation process162uses CVD, ECP, or ELD, it can be seen that the contact metal layer160is formed to fill in the opening136over the seed metal layer142. Compared to other devices that have a glue layer in the opening136, in the present disclosure, there is no glue layer in the opening136, so the contact metal layer160may directly contact the spacers158located on the sidewalls of the opening136. The contact metal layer160may directly contact the gate spacers132if the spacers158are not present on the sidewalls of the opening136. The direct contact between the contact metal layer160and spacers helps reduce resistivity because the contact metal layer160has lower resistivity than glue layers.

Now referring toFIG. 3D, in step84of the method70(FIG. 2), a fill metal layer170is formed over the device100. In various embodiments, the fill metal layer170includes cobalt (Co), tungsten (W), ruthenium (Ru), or combinations thereof. The fill metal layer170may be a metal compound or alloy including Co, W, and/or Ru as well as other element(s) such as Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, Mo, Zn, Ni, K, Cd, Ru, In, Os, Si, or Ge, or combinations thereof. In some embodiments, the fill metal layer170has the same material as the contact metal layer160to minimize contact resistance therebetween. As the fill metal layer170hangs over (“over-burdens”) the contact metal layer160, the fill metal layer170is sometimes called an over-burden metal layer. The fill metal layer170may be formed by ALD, CVD, PVD, plating, and/or other suitable processes. Because the fill metal layer170is formed in the larger trench156, its formation is in some embodiments faster than the formation of the seed metal layer142. Also, in cases there are multiple openings136with different sizes, the seed metal layer142formed in the openings136may vary in thickness depending on the sizes of respective openings136(e.g., a smaller opening136leads to a thicker seed metal layer142). In such cases, the fill metal layer170helps make up the thickness differences of the seed metal layer142by creating a roughly even top surface. In some embodiments, the fill metal layer170has a thickness greater than that of the trench156, therefore allowing the fill metal layer170to spread over the whole top surface of the device100. A filled-up top surface with no trenches or openings improves the performance of a CMP process, described next.

Now referring toFIG. 3E, in step86of the method70(FIG. 2), a CMP process is performed to remove an upper thickness of the device100, thereby planarizing a top surface of the device100. The CMP process may be performed under suitable conditions. In some embodiments, an upper thickness of about 5 to about 10 nm is removed from the device100. As shown inFIG. 3E, the fill metal layer170may be removed entirely in some embodiments such that the contact metal layer160may be connected to other conductive features such as upper vias without any risk of the fill metal layer170creating potential shorted circuits. An upper thickness of the contact metal layer160may be removed by the CMP process. If the filled-up top surface of the device100has surface roughness, the CMP process helps remove such roughness. Since any openings and/or trenches have been filled up by the fill metal layer170, the CMP encounters less or no structural buckling issues.

After the CMP process, a complete source/drain contact structure is formed including, from bottom to top, the silicide layer140, the seed metal layer, and the planarized contact metal layer160.FIGS. 3F and 3Gillustrate top views and Y-cut views, respectively, of the device100after step86, although distances and sizes are not to scale. The contact metal layer160may be surrounded by the spacers158in the X-cut view (FIG. 3E) and Y-cut view (FIG. 3F). As shown inFIG. 3G, when two fins structures110are disposed adjacent each other, their respective source/drain features120may merge into each other during the epitaxial growth process. The silicide layer140may wrap around the merged source/drain features120, and the seed metal layer142may wrap around the silicide layer140. The two fins structures110share one contact metal layer160, which may electrically connect the merged source/drain features120to other features such as upper vias. In the present embodiment, the contact metal layer160is landing on a concave surface of the merged source/drain feature120with increased contact area and reduced contact resistance.

Subsequently, at step88, the method100performs additional processing steps to complete fabrication of the device100. For example, additional vertical interconnect features such as contacts and/or vias, and/or horizontal interconnect features such as lines, and multilayer interconnect features such as metal layers and interlayer dielectrics can be formed over the device100.

The fabrication process disclosed herein may vary in terms of steps and sequences, but they all fall within the principles disclosed herein. For example,FIGS. 4A-4Fare diagrammatic fragmentary cross-sectional views of a FinFET device200at different stages of fabrication according to embodiments of the present disclosure. The FinFET device200is fabricated using a first variation of the method100. The FinFET device200is similar to the FinFET device100except differences specifically noted, thus for reasons of simplicity not all aspects are repeated herein. As shown inFIG. 4A, in this embodiment, the silicide layer140is formed just likeFIG. 3A, but the seed metal layer142is not formed. Instead of forming the seed metal layer142(step76), the method100may move directly from step74(for forming the silicide layer140) to steps78and80, where the method100performs gate replacement and middle end of the line processes, as shown inFIG. 4B.

As shown inFIG. 4C, in step82, the contact metal layer160is formed over and in direct contact with the silicide layer140(that is, without any intervening seed metal layer142). Since the silicide layer140is a conductive surface, the contact metal layer160may still be selectively formed such that it grows on the silicide layer140but not on dielectric surfaces (e.g., the sacrificial layer152, the ILD layer154, and the spacers158). However, in embodiments that do not use the seed metal layer142, the selective formation of the contact metal layer160may have different process conditions or parameters to achieve selective deposition since the silicide layer140, as a growing surface, has a different composition and material characteristics. For example, in some embodiments, a CVD process for forming the contact metal layer160is performed using a precursor gas flow rate between about 300 sccm and about 500 sccm (e.g., about 300 sccm and about 350 sccm). Having a higher precursor flow rate helps the growth of the contact metal layer160on the surface of the silicide layer140because the silicide layer140has lower conductivity than the seed metal layer142. In other words, the higher precursor flow rate allows the contact metal layer160to grow with reasonable rates even without the presence of the seed metal layer142. Since the range of about 300-350 sccm is still relatively low, the formation of seed metal layer142maintains its selectivity. As described above, such a selective formation approach helps avoid bottle neck and voids problems. Note that, due to the absence of the seed metal layer142that may have the same material as the contact metal layer160, the growth rate of the contact metal layer160on a different material (i.e., the silicide layer140) may be slowed down, even with higher precursor flow rates.

As described above, to prevent the silicide layer140from oxidation by surrounding air, its upper portion may contain a capping layer. In some embodiments, a precursor for forming the contact metal layer160is selected such that the precursor would not damage the capping layer in the silicide layer140. For example, if W is used for the metal material of the contact metal layer160, it may be formed using gases such as WF6/H2, WF6/H2/SiH4, where the hydrogen gas facilities the formation and deposition of W. Certain damages in the capping layer may increase contact resistance, e.g., due to increased surface roughness on the silicide layer140. However, even if damages to the capping layer is inevitable (e.g., when material choices for the contact metal layer160are limited), remedial actions may be taken to mitigate such damages. In some embodiments, the silicide layer140goes through surface treatment before and/or during formation of the contact metal layer160(e.g., by using chemicals to smoothen the surface of the silicide layer140) in order to mitigate the effect of potential surface damages.

Further, in embodiments that do not use the seed metal layer142, the contact metal layer160may have weaker adhesion with the underlying silicide layer140. As shown inFIG. 4C, to enhance the positional security of the contact metal layer160(and therefore prevent potential structural damages), an atom implantation process410may be optionally performed to implant big atoms into the spacers158after the formation of the contact metal layer160. In some embodiments, atoms bigger than silicon (e.g., germanium) are injected into the spacers158such that the spacers158next to the contact metal layer160would be pushed laterally, thereby tightening the adhesion between the spacers158and the contact metal layer160. In some embodiments, the atom implantation process410needs no mask for implantation because the big atoms can penetrate into dielectric layers that contain small atoms (e.g., the spacers158), but cannot substantially penetrate into the contact metal layer160or the sacrificial layer152; the reason being that the atoms contained therein are relatively big. At most, a shallow layer of implant atoms may be injected into the contact metal layer160or the sacrificial layer152, which would not substantially affect the performance of the device200.

Now referring toFIG. 4D, in step84of the method70(FIG. 2), a fill metal layer170is formed over the device200. Next, as shown inFIG. 4E, in step86of the method70(FIG. 2), a CMP process is performed to remove an upper thickness of the device200, thereby planarizing a top surface of the device200. After the CMP process, a complete source/drain contact structure is formed including, from bottom to top, the silicide layer140and the planarized contact metal layer160.FIGS. 4F and 4Gillustrate top views and Y-cut views, respectively, of the device200after step86, although distances and sizes are not to scale. The contact metal layer160may be surrounded by the spacers158in the X-cut view (FIG. 4E) and Y-cut view (FIG. 4G). As shown inFIG. 4G, the silicide layer140may wrap around the merged source/drain features120, but there is no seed metal layer142wrapping around the silicide layer140. The two fins structures110share one contact metal layer160, which may electrically connect the merged source/drain features120to other features such as upper vias.

As discussed above, the method100may be modified within the principles disclosed herein. For example,FIGS. 5A-5Fare diagrammatic fragmentary cross-sectional views of a FinFET device300at different stages of fabrication according to embodiments of the present disclosure. The FinFET device300is fabricated using a second variation of the method100. The FinFET device300is similar to the FinFET devices100and200except differences specifically noted, thus for reasons of simplicity not all aspects are repeated herein. As shown inFIG. 5A, in this embodiment, a starting device300with a source/drain feature120directly goes through gate replacement and middle end of the line processes (steps78and80of the method100) without first forming either a silicide layer or a seed metal layer. As shown inFIG. 5B, after the gate replacement and middle end of the line processes, a silicide layer140is formed in the opening136over the source/drain feature120(step74), and a seed metal layer142is formed over the silicide layer140(step76). Since the silicide layer140and the seed metal layer142are formed after the gate replacement and middle end of the line processes, as a benefit, the silicide layer140and the seed metal layer142do not have to go through certain thermal processes. As a result, the silicide layer140and the seed metal layer142may suffer from less damages and end up with more consistent properties. For example, the silicide layer140when formed post-gate-replacement may have a lower resistivity.

As shown inFIG. 5C, a contact metal layer160is formed over the seed metal layer142(step82). As shown inFIG. 5D, a fill metal layer170is formed over the device300(step84). As shown inFIG. 5E, a CMP process is performed to remove an upper thickness of the device300, thereby planarizing a top surface of the device300(step86).FIGS. 5F and 5Gillustrate top views and Y-cut views, respectively, of the device300after step86, although distances and sizes are not to scale. As shown inFIG. 5G, both the silicide layer140and the seed metal layer142are formed on the merged source/drain features120, but neither the silicide layer140nor the seed metal layer142fully wraps around the merged source/drain features120. The different Y-cut profile shown inFIG. 5G(compared toFIG. 3G) stems from the fact that the middle end of the line processes are performed (FIG. 5A) before forming the silicide layer140(FIG. 5B). That is, most surfaces (including sidewall surfaces) of the source/drain feature120have been covered by the ILD layer154by the time the silicide layer140is formed. The reduced contact area between the silicide layer140and the source/drain feature120may lead to increased contact resistance. However, as described above, the silicide layer140when formed post-gate-replacement may have a lower resistivity, which may offset the impact of having less contact area with the source/drain feature120.

FIGS. 6A-6Fare diagrammatic fragmentary cross-sectional views of a FinFET device400at different stages of fabrication according to embodiments of the present disclosure. The FinFET device400is fabricated using a third variation of the method100. The FinFET device400is similar to the FinFET devices100,200, and300except differences specifically noted, thus for reasons of simplicity not all aspects are repeated herein. As shown inFIG. 6A, in this embodiment, a starting device400with a source/drain feature120directly goes through gate replacement and middle end of the line processes (steps78and80of the method100) without first forming a silicide layer. As shown inFIG. 6B, after the gate replacement and middle end of the line processes, gate replacement and middle end of the line processes, a silicide layer140is formed in the opening136over the source/drain feature120(step74). As shown inFIG. 6C, a contact metal layer160is formed over the silicide layer140(step82). Note that, similar to the approach inFIGS. 4A-4G, no seed metal layer is formed between the silicide layer140and the contact metal layer160. Therefore, process conditions may be similarly adjusted to facilitate the selective formation of the contact metal layer160directly on the silicide layer140. As shown inFIG. 6D, a fill metal layer170is formed over the device400(step84). As shown inFIG. 6E, a CMP process is performed to remove an upper thickness of the device400, thereby planarizing a top surface of the device400(step86).FIGS. 6F and 6Gillustrate top views and Y-cut views, respectively, of the device400after step86, although distances and sizes are not to scale. As shown inFIG. 6G, the silicide layer140is formed on the merged source/drain features120, but the silicide layer140does not fully wrap around the merged source/drain features120.

In summary, the present disclosure utilizes various embodiments each having unique fabrication process flows to form source/drain contact features. Based on the above discussions, it can be seen that the present disclosure offers advantages over conventional semiconductor devices and the fabrication thereof. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the present disclosure reduces contact resistance between metal layers and a source/drain feature. For example, by eliminating a glue layer made of nitride materials, higher conductive metals are used instead to reduce contact resistance. Another advantage is that the fabrication methods presented herein avoids or minimizes bottle neck and voids problems. Other advantages include compatibility with existing fabrication process flows, etc.

One aspect of the present disclosure involves a method of semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.

One aspect of the present disclosure involves a semiconductor device. The semiconductor device includes a fin disposed on a substrate; first and second metal gate stacks disposed on the fin; first and second spacers disposed on respective sidewalls of the first and second metal gate stacks; a source/drain feature disposed on the fin and between the first and second metal gate stacks; a silicide layer disposed over the source/drain feature; a seed metal layer disposed on the silicide layer; and a bottom-up metal layer disposed over the seed layer and between the first and second spacers, wherein the bottom-up metal layer is in direct contact with the first and second spacers.

Another aspect of the present disclosure involves a semiconductor device. The semiconductor device includes a fin disposed on a substrate; first and second metal gate stacks disposed on the fin; first and second spacers disposed on respective sidewalls of the first and second metal gate stacks; a source/drain feature disposed on the fin and between the first and second metal gate stacks; and a contact feature landing on the source/drain feature. The contact feature further includes a silicide layer disposed over the source/drain feature; a seed metal layer of a first metal disposed on the silicide layer; and a bottom-up metal layer of a second metal disposed over the seed layer and between the first and second spacers, wherein the bottom-up metal layer is in direct contact with the first and second spacers, wherein the second metal is different from the first metal in composition.