Method for fabricating capacitor structures using the first contact metal

A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.

FIELD OF THE INVENTION

The present invention relates to improved methods for fabricating a metal capacitor/gate electrode structure.

RELATED ART

Metal gate electrodes have been used in conventional CMOS transistor applications. For example, U.S. Pat. No. 6,998,686 to Chau describes a multi-layer material stack for CMOS application. However, Chau undesirably adds significant complexity to a conventional CMOS (single-polysilicon) process because three (non-standard) metal layers must be deposited prior to depositing the polysilicon layer.

Metal electrodes have also been used to implement the control gate of an EEPROM structure, as set forth by H. C. Sung et al., “Novel Single Poly EEPROM with Damascene Control Gate Structure”, IEEE Electron Device Letter 2005, pp. 770. However, Sung et al. undesirably requires the addition of the following steps to a conventional CMOS process: a control gate mask formation, control gate etch, oxidation treatment, Al2O3deposition, barrier metal (TiN) deposition, tungsten (W) fill, chemical-mechanical polishing (CMP) and post ALD anneal.

Accordingly, it would be desirable to have improved methods for fabricating metal capacitor/gate electrode structures, which are compatible with a conventional CMOS process.

SUMMARY

Accordingly the present invention provides improved methods for fabricating metal electrodes over dielectric materials, wherein such methods can be robustly integrated into a conventional CMOS process flow without changing the properties of the other devices fabricated on the same wafer. The metal electrodes fabricated in accordance with the present invention may be used as upper capacitor electrodes, wherein the lower capacitor electrodes are formed by (salicided or non-salicided) polysilicon layers or (salicided or non-salicided) silicon active areas. Capacitors fabricated in this manner exhibit a small layout area and a high capacitance. The metal electrodes fabricated in accordance with the present invention may alternately be used for other applications, such as forming gate electrodes of high-voltage silicon-on-insulator (SOI) transistors, or control gates of electrically erasable programmable read only memory (EEPROM) cells.

In a particular embodiment, a metal electrode structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed using a conventional CMOS process steps, a non-conventional mask is formed over the pre-metal dielectric layer. This mask includes openings that define the locations where the metal electrode structures will subsequently be formed. A set of grooves are etched through the openings of the mask, wherein the grooves extend through the pre-metal dielectric layer to expose underlying polysilicon structures (which may be salicided or non-salicided). A dielectric layer is formed over the exposed polysilicon structures. The dielectric layer isolates these polysilicon structures from the subsequently formed metal electrode structures, thereby enabling the metal electrode structures to form transistor control gates or capacitor plates. The non-conventional mask is then stripped.

A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. These contact openings typically expose active (source/drain) regions and polysilicon regions. The contact mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact metal stack. A planarization step removes the upper portion of the deposited metal stack, thereby leaving metal contact plugs in the contact openings, and metal electrodes in the grooves. Advantageously, the process of the present invention adds only one non-conventional mask (and one non-conventional dielectric layer) to a conventional CMOS process.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a semiconductor structure100in accordance with one embodiment of the present invention. Semiconductor structure100includes three semiconductor devices101,102and103, which may fabricated on the same semiconductor substrate105. Semiconductor devices101,102and103will now be briefly described.

The polysilicon body region111of high-voltage transistor101is isolated from substrate105by shallow trench isolation (STI) region110. Source/drain contact plugs171and173provide electrical connections to metal salicide source/drain regions116and117, respectively (and thereby to the source/drain regions112and113of high-voltage transistor101). Source/drain regions112-113are separated by a channel region within polysilicon body region111. Stacked metal gate electrode172overlies this channel region (and is separated from this channel region by gate dielectric layer141). Given the above-described structure of high-voltage SOI transistor101, one of ordinary skill in the art would understand the general manner in which this device operates (e.g., the voltage applied to gate electrode172controls current flow between source/drain regions112-113). As described in more detail below, stacked metal gate electrode172is formed at the same time as source/drain contact plugs171and173, thereby enabling high-voltage transistor101to be fabricated with a process that is highly compatible with conventional CMOS processes.

Semiconductor device102is a single-poly electrically erasable and programmable read only memory (EEPROM) cell, which includes gate dielectric layer120, polysilicon floating gate electrode121, source/drain regions122-123, dielectric sidewall spacers124-125, metal salicide source/drain contact regions126-127, contact barrier layer106, pre-metal dielectric structure109, inter-gate dielectric layer142, source/drain contact plug174(which includes composite metal barrier region154and metal contact structure164), source/drain contact plug176(which includes composite metal barrier region156and metal contact structure166), and stacked metal control gate electrode175(which includes composite metal barrier region155and metal contact structure165). Given the above-described structure of single-poly EEPROM cell102, one of ordinary skill in the art would understand the general manner in which this device operates (e.g., the charge stored by the polysilicon floating gate121in response to program/erase operations determines the data stored by the EEPROM cell). As described in more detail below, stacked metal control gate electrode175is formed at the same time as source/drain contact plugs174and176, thereby enabling EEPROM cell102to be fabricated with a process that is highly compatible with conventional CMOS processes.

Semiconductor device103is a high-voltage capacitor, which includes shallow trench isolation region130, lower capacitor electrode133(which includes polysilicon region131and metal salicide region132), dielectric sidewall spacers134-135, contact barrier layer106, pre-metal dielectric structure109, capacitor dielectric layer143and stacked metal upper capacitor electrode177(which includes composite metal barrier region157and metal contact structure167). Given the above-described structure of high-voltage capacitor103, one of ordinary skill in the art would understand the general manner in which this device operates. As described in more detail below, stacked metal upper capacitor electrode177is formed at the same time as other contact plugs, thereby enabling high voltage capacitor103to be fabricated with a process that is highly compatible with conventional CMOS processes.

FIGS. 2A-2Hare cross-sectional views illustrating semiconductor structure100during various stages of fabrication, in accordance with one embodiment of the present invention.

FIG. 2Ais a cross-sectional diagram illustrating semiconductor devices101-103after conventional front-end CMOS processing has been completed. Note that salicidation (e.g., the formation of salicide regions116-117,126-127and132), deposition of the contact barrier dielectric106, deposition and planarization of the pre-metal dielectric layer107and formation of the pre-metal dielectric cap108, are all completed during conventional CMOS front-end processing. In the described embodiments, salicide regions116-117,126-127and132are cobalt salicide (CoSi2), however, different types of metal salicide can be used in other embodiments. Contact barrier dielectric layer106is typically silicon nitride (SiN), although other dielectric materials can be used in other embodiments. Pre-metal dielectric layer107can be, for example, boron phosphorus silica glass (BPSG) or phosphorus silica glass (PSG). Pre-metal dielectric cap layer108can be, for example, silicon dioxide deposited from tetra-ethoxy silane (TEOS). Pre-metal dielectric layer107can also include TEOS silicon dioxide. The pre-metal dielectric layer107is typically planarized using a chemical-mechanical polishing (CMP) process (prior to forming pre-metal dielectric cap108).

In a conventional CMOS process, after the front-end processing is complete (FIG. 2A), a contact process module is typically used to form metal contacts (plugs), which extend through the pre-metal dielectric structure109and contact polysilicon/salicide regions and active regions formed during the front-end processing. The metal contact plugs also provide connections to the upper metal lines that are formed during conventional back-end processing.

However, in accordance with the present invention, the contact process module is not implemented immediately after completing the front-end processing. Instead, processing proceeds as follows.

As illustrated inFIG. 2B, a photoresist mask200is formed over the upper surface of pre-metal dielectric structure109. Photoresist mask200includes openings201,202, and203, which define the locations where stacked metal gates/electrodes are to be subsequently formed using the contact process module in accordance with the present invention. More specifically, openings201,202and203define the locations of subsequently formed stacked metal gate electrode172, stacked metal control gate electrode175and stacked metal upper capacitor electrode177, respectively. Note that photoresist mask200represents an additional (non-conventional) mask with respect to a conventional CMOS process.

As illustrated inFIG. 2C, an etch is performed through the openings201-203of photo resist mask200, thereby forming grooves204-206, respectively. This etch is performed such that grooves204-206extend through pre-metal dielectric cap108, pre-metal dielectric layer107, and contact barrier dielectric layer106. The etch process can be dry, wet, or a combination of dry and wet etches. It is important to note that the underlying regions exposed by this etch process can be either non-salicided polysilicon or salicided polysilicon. For example, non-salicided polysilicon body region111is exposed through groove204, non-salicided polysilicon floating gate electrode121is exposed through groove205, and metal salicide region132is exposed through groove206. In an alternate embodiment, the upper surface of polysilicon floating gate electrode121may be salicided during the front-end process. Note that the etch ofFIG. 2Crepresents an additional etch with respect to a conventional CMOS process.

In accordance with one embodiment, a one-step dry etch process is implemented to form grooves204-206, wherein this one-step dry etch exhibits stop points on either cobalt salicide or polysilicon. For example, a fixed-time plasma etch may be performed at a power of about 1.1 kW and a low pressure of about 150 mTorr, with fluorinated carbon gases. This etch process has an oxide-to-cobalt salicide selectivity greater than 5. Using this one-step dry etch, grooves with a stop point on cobalt salicide are characterized by excellent etch uniformity over the entire surface of a wafer, accompanied with minimum consumption of cobalt salicide. This one-step dry etch provides a sharp front of the groove, which is critical for production of scaled-down devices. Moreover, this one-step dry etch does not result in significant differences in the shape and features of grooves having bottoms on cobalt salicide, polysilicon/STI regions or active areas.

As illustrated inFIG. 2D, photo resist mask200is then stripped, and a dielectric layer140is deposited over the resulting structure. In accordance with one embodiment, dielectric layer140may be silicon oxide, silicon nitride, or a high-dielectric material, such as alumina. Alternately, dielectric layer140may be a dielectric stack that includes any combination of these dielectric materials. The properties of dielectric layer140are selected to correspond with the desired properties of the gate/inter-gate dielectric layer formed by this layer140. That is, the properties of dielectric layer140are selected to correspond with the desired properties of transistor gate dielectric layer141, inter-gate dielectric layer142, and/or capacitor dielectric layer143. The formation of dielectric layer140represents an additional step with respect to a conventional CMOS process.

As illustrated inFIG. 2E, photoresist mask210is formed over dielectric layer140. This photo resist mask210is identical to the photo resist mask used to form the standard metal contact openings in a conventional CMOS process. Photo resist mask210includes openings211,212,213and214, which define the locations where the respective source/drain contact plugs171,173,174and176will be formed. Note that photo resist mask210may also include another opening (not shown), which defines the location where a contact to lower capacitor electrode133will be formed.

As illustrated inFIG. 2F, an etch is performed through the openings211-214of photo resist mask210thereby forming openings215-218, respectively. This etch is performed such that openings215-218extend through dielectric layer140, pre-metal dielectric cap108, pre-metal dielectric layer107, and contact barrier dielectric layer106. The etch process can be dry, wet, or a combination of dry and wet etches. It is important to note that the layers exposed by this etch process can be either salicided polysilicon (as illustrated) or non-salicided polysilicon. The initial portion of the etch ofFIG. 2F, wherein dielectric layer140is etched through openings211-214, represents an additional etch step with respect to a conventional CMOS process. However, the remaining portions of the etch ofFIG. 2Fare present in a conventional CMOS process.

As illustrated inFIG. 2G, photoresist mask210is stripped, and composite metal barrier layer150is formed over the resulting structure. Composite metal barrier layer150is a conventional layer that prevents subsequently deposited metal from spiking into underlying silicon regions. In the described embodiment, composite metal barrier layer150includes titanium and titanium nitride (Ti/TiN). The composition of metal barrier layer150is selected in view of the identity of the subsequently deposited metal contact material. For example, composite metal barrier layer150is selected to be titanium/titanium nitride when the subsequently deposited metal contact material is tungsten (W).

However, composite metal barrier layer150may have a different composition (e.g., tantalum/tantalum nitride (Ta/TaN)), when other metal contact materials are used (e.g., aluminum or copper). The selection of appropriate metal barrier materials is well known to those of ordinary skill in the art. The formation of composite metal barrier layer150is present in a conventional CMOS process.

As illustrated inFIG. 2Ha layer of metal contact material160is formed over the composite metal barrier layer150. In the described embodiment, the metal contact layer160is tungsten, which is fabricated by chemical vapor deposition (CVD). The metal contact layer160is deposited such that the previously formed openings204-206and215-218are filled. The deposition of metal contact layer160is present in a conventional CMOS process.

Following the chemical vapor deposition of metal contact layer160, a chemical mechanical polishing (CMP) process is performed. This CMP process is stopped after exposing the upper surface of pre-metal dielectric layer109. As a result, the portions of composite metal barrier layer150and metal contact layer160located directly over the upper surfaces of pre-metal dielectric structure109are removed. At the end of this CMP process, the remaining portions of composite metal barrier layer150form composite metal barrier regions151-157, and the remaining portions of metal contact layer160form metal contact structures161-167, as illustrated inFIG. 1. Note that the stacked metal electrode structures172,175and177formed in accordance with the present invention are wider than the metal contact plugs171,173,174and176. As a result, the wider metal electrode structures172,175and177may exhibit ‘dishing’, wherein the upper surfaces of these metal electrode regions172,175and177are slightly lower than the upper surfaces of the metal contact plugs171,173,174and176. However with appropriate layout design rules, this ‘dishing’ phenomenon will not interfere with the subsequent back-end processing steps. From the structure illustrated inFIG. 1, standard back-end processing steps are performed to complete fabrication of the semiconductor structure100.

Different dielectric materials can be used to implement dielectric layer140(FIG. 2D), in accordance with various embodiments of the present invention. For example, dielectric layer140may be silicon oxide, silicon nitride and their combinations (e.g., NO, ON, ONO). Various combinations were tested to demonstrate the feasibility of producing capacitors having a bottom electrode formed of either polysilicon (salicided or non-salicided) or an active area, and an upper electrode formed of a tungsten plug having a titanium/titanium nitride composite. In general, a capacitor having a bottom electrode formed of an active area can be formed in a manner similar to that described above for high-voltage capacitor structure103. However, the lower capacitor electrode131is replaced by a (salicided or non-salicided) conductively doped silicon region formed in the substrate105. (Note that lower capacitor electrode131, dielectric sidewall spacers134-135, and shallow trench isolation region130are eliminated in this capacitor structure).

FIG. 3is a table300that summarizes the characteristics of capacitor structures fabricated on seven different wafers. Within table300, EOT is the effective oxide thickness of the dielectric layer140in Angstroms, VBDis an averaged breakdown voltage of the resulting capacitor structures (over 10 units), and QBDis an averaged charge to breakdown (in Coulombs/cm2) measured at a 0.01 Amps/cm2current density through the capacitor structure (and averaged over 10 units). As illustrated by table300, all of the proposed capacitor structures show high performance and the ability to work at high voltages. No built-in charge was found in the tested capacitor structures.

In a particular embodiment of the present invention, the structure of semiconductor device102can be used to implement a complementary non-volatile memory cell whose basic structure is described in U.S. Pat. No. 6,788,576 to Roizin.FIG. 4is a circuit diagram of such a complementary non-volatile memory cell400, which includes a shared polysilicon floating gate having the structure of polysilicon floating gate121(FIG. 1), an inter-gate dielectric layer having the structure of inter-gate dielectric region142, and a shared control gate having the structure of stacked metal control gate175.

FIG. 5is a High Resolution TEM image500illustrating a dielectric region142in accordance with one embodiment of the present invention. In this embodiment, dielectric region142is an alumina-silicon dioxide (A-O) stack. Stacked metal control gate175(Ti/TiN under W, wherein W is not shown) provides a higher barrier for electron injection than a polysilicon control gate (pinning effect), and is therefore preferable in device operation (i.e., parasitic injection from the metal control gate175is suppressed during erase operations).

Post deposition annealing (PDA) reduces the EOT of the alumina-silicon dioxide stack142, and also improves the electrical performance of the alumina-silicon dioxide stack142. The electrical performance of the alumina-silicon dioxide stack142ofFIG. 5advantageously exceeds the analogous parameters of silicon dioxide with the same physical thickness.

FIG. 6is a graph600that illustrates the current-voltage (I-V) characteristics of a capacitor structure (500×500 mm2) fabricated with the alumina-silicon dioxide stack ofFIG. 5and a stacked metal upper electrode of titanium/titanium nitride (Ti/TiN) and tungsten (W).

FIGS. 7A-7Gare cross sectional views illustrating semiconductor devices701-703during various stages of fabrication, in accordance with an alternate embodiment of the present invention. Semiconductor devices701-703are similar to semiconductor devices101-103, with differences noted below. Processing in this alternate embodiment begins with the structure ofFIG. 2D, which has been described above. At this stage of the process, the gate dielectric layer140has been formed in the grooves204-206formed in the pre-metal dielectric layer109. A composite metal barrier layer750, which has the same characteristics as composite metal barrier layer150, is deposited over the gate dielectric layer140. A metal contact layer760, which has the same characteristics as metal contact layer160, is deposited over the composite metal barrier layer750.FIG. 7Ais a cross-sectional diagram illustrating semiconductor devices701-703after composite metal barrier layer750and metal contact layer760have been deposited over the semiconductor structure ofFIG. 2D. Note that the contact openings have not been formed at this time.

As illustrated inFIG. 7B, a chemical-mechanical polishing (CMP) process is performed, stopping on gate dielectric layer140. It is acceptable if a portion of the upper surface of gate dielectric layer140is removed during this CMP process. At the end of this CMP process, composite metal barrier region751and metal electrode structure761remain to form the stacked metal gate electrode771of high-voltage transistor701; composite metal barrier region752and metal electrode structure762remain to form stacked metal control gate electrode772of single-poly EEPROM cell702; and composite metal barrier region753and metal electrode structure763remain to form the stacked metal upper electrode773of high-voltage capacitor structure703.

As illustrated inFIG. 7C, photoresist mask210is formed over the resulting structure. This photo resist mask210, which has been described above in connection withFIG. 2E, includes openings211,212,213and214, which define the locations where the source/drain contact plugs will be formed.

As illustrated inFIG. 7D, an etch is performed through the openings211-214of photo resist mask210thereby forming openings215-218, respectively. The details of this etch are described above in connection withFIG. 2F.

As illustrated inFIG. 7E, photoresist mask210is stripped, and second composite metal barrier layer780is formed over the resulting structure. In the described embodiment, composite metal barrier layer780has the same characteristics as composite metal barrier layer750, although this is not necessary if the subsequently deposited metal contact material790differs from the metal of electrode (gate) structure760.

As illustrated inFIG. 7Fa second layer of metal contact material790is formed over the second composite metal barrier layer780. In the described embodiment, the second metal contact layer790has the same characteristics as the metal of electrode structure (first metal contact layer)760, although this is not necessary. Following the deposition of the second metal contact layer790, a chemical mechanical polishing (CMP) process is performed. This CMP process is stopped after exposing the upper surface of pre-metal dielectric layer109. As a result, the portions of the second composite metal barrier layer780and the second metal contact layer790located directly over the upper surfaces of pre-metal dielectric structure109are removed. At the end of this CMP process, the remaining portions of the second composite metal barrier layer780form composite metal barrier regions781-784, and the remaining portions of the second metal contact layer790form metal contact regions791-794, as illustrated inFIG. 7G. From the structure illustrated inFIG. 7G, standard back-end processing steps are performed to complete fabrication of the semiconductor structure.

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Thus, the invention is limited only by the following claims.