IMAGING ELEMENT AND IMAGING DEVICE

To downsize an imaging element formed by stacking a plurality of semiconductor substrates. The imaging element includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photoelectric conversion section that performs photoelectric conversion of incident light. The second semiconductor substrate includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.

FIELD

The present disclosure relates to an imaging element and an imaging device.

BACKGROUND

An imaging element that images a subject is implemented by using an imaging element having a configuration in which a plurality of substrates is stacked. The plurality of substrates corresponds to, for example, a substrate on which a pixel that converts incident light from the subject into an image signal using photoelectric conversion is formed and a substrate on which a circuit that generates a control signal of the pixel or a circuit that processes image signals is formed. A circuit that handles an analog image signal is disposed on the pixel. On the other hand, the circuit that processes image signals mainly uses a digital circuit that operates at a high speed. In this manner, with a configuration in which circuits having different characteristics are disposed on different substrates, it is possible to manufacture a substrate by applying an optimum process to these circuits. Further, the configuration of stacking these substrates making it also possible to reduce the area of the imaging element.

For example, there is proposed an imaging element in which a first substrate on which a photoelectric conversion element that performs photoelectric conversion of incident light is mainly disposed and a second substrate on which an amplification transistor that amplifies a signal generated by the photoelectric conversion element to generate an image signal is disposed are stacked to form a pixel (refer to Patent Literature 1, for example).

In this imaging element, a third substrate on which a circuit that generates a control signal of a pixel and a circuit that processes an image signal are formed is further stacked to form the imaging element. In addition, since the circuit constituting the pixel is divided into two substrates and stacked, a connecting location (contact) for using the reference potential of these substrates in common is disposed between the substrates. Here, the reference potential is a potential serving as a reference of a signal of a circuit of a pixel or a power supply voltage, and corresponds to a ground potential, for example.

CITATION LIST

Patent Literature

Patent Literature 1: WO 2020/105713 A

SUMMARY

Technical Problem

The above-described conventional technique has a problem of difficulty in downsizing the substrate. This is because there is a need to have a region where a contact is disposed on the first substrate, the second substrate, and the third substrate. In particular, in the second substrate stacked in the middle, a contact with the first substrate and a contact with the third substrate are disposed. There is a need to a region where these contacts are to be disposed, increasing the area of the substrate.

In view of this, regarding an imaging element and an imaging device having a configuration in which a plurality of semiconductor substrates is stacked, the present disclosure proposes an imaging element and an imaging device that can be downsized.

Solution to Problem

An imaging element according to the present disclosure includes: a first semiconductor substrate including a photoelectric conversion section that performs photoelectric conversion of incident light; and a second semiconductor substrate that includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present disclosure will be described below in detail with reference to the drawings. The description will be given in the following order. Note that, in each of the following embodiments, the same parts are denoted by the same reference symbols, and a repetitive description thereof will be omitted.1. First Embodiment2. Second Embodiment3. Third Embodiment4. Fourth Embodiment5. Application Example6. Example of application to mobile body7. Example of application to endoscopic surgery system

1. First Embodiment

[Functional Configuration of Imaging Device1]

FIG.1is a block diagram depicting an example of a functional configuration of an imaging device (imaging device1) according to an embodiment of the present disclosure.

The imaging device1ofFIG.1includes, for example, an input section510A, a row drive section520, a timing controlling section530, a pixel array section540, a column signal processing section550, an image signal processing section560, and an output section510B.

In the pixel array section540, pixels541are repeatedly disposed in an array. More specifically, a pixel sharing unit539including a plurality of pixels is a repeating unit, and is repeatedly disposed in an array including a row direction and a column direction. In the present specification, for convenience, the row direction may be referred to as an H direction, and the column direction orthogonal to the row direction may be referred to as a V direction. In the example ofFIG.1, one pixel sharing unit539includes four pixels (pixels541A,541B,541C, and541D). Each of the pixels541A,541B,541C, and541D includes a photoelectric conversion section101(depicted inFIG.6and the like described below). The pixel sharing unit539is a unit of sharing one pixel circuit (a pixel circuit210inFIG.3described below). In other words, one pixel circuit (the pixel circuit210to be described below) is provided for every four pixels (pixels541A,541B,541C, and541D). By allowing the pixel circuit to operate in time division, a pixel signal of each of the pixels541A,541B,541C, and541D is sequentially read out. The pixels541A,541B,541C, and541D are each disposed in 2 rows×2 columns, for example. The pixel array section540includes a plurality of row drive signal lines542and a plurality of vertical signal lines (column readout lines)543together with the pixels541A,541B,541C, and541D. The row drive signal line542drives the pixels541included in each of the plurality of pixel sharing units539disposed side by side in the row direction in the pixel array section540. In the pixel sharing unit539, individual pixels disposed side by side in the row direction are driven. As will be described in detail below with reference toFIG.4, the pixel sharing unit539is provided with a plurality of transistors. In order to drive each of the plurality of transistors, the plurality of row drive signal lines542is connected to one pixel sharing unit539. The pixel sharing unit539is connected to the vertical signal line (column readout line)543. A pixel signal is read out from each of the pixels541A,541B,541C, and541D included in the pixel sharing unit539via the vertical signal line (column readout line)543.

The row drive section520includes, for example, a row address controlling section that determines a position of a row for pixel drive, in other words, a row decoder section, and a row drive circuit section that generates a signal for driving the pixels541A,541B,541C, and541D.

The column signal processing section550includes, for example, a load circuit section connected to the vertical signal line543and configured to form a source follower circuit with the pixels541A,541B,541C, and541D (pixel sharing unit539). The column signal processing section550may include an amplifier circuit section that amplifies a signal read out from the pixel sharing unit539via the vertical signal line543. The column signal processing section550may include a noise processing section. The noise processing section removes system noise levels from the signal read out from the pixel sharing unit539as a result of photoelectric conversion, for example.

The column signal processing section550includes an analog-to-digital converter (ADC), for example. The analog-to-digital converter converts the signal read out from the pixel sharing unit539or the noise-processed analog signal into a digital signal. The ADC includes, for example, a comparator section and a counter section. The comparator section compares an analog signal to be converted with a reference signal for comparison. The counter section is supposed to count the time until the comparison result in the comparator section is inverted. The column signal processing section550may include a horizontal scanning circuit section that performs control to scan the readout column.

The timing controlling section530supplies a signal controlling timing to the row drive section520and the column signal processing section550on the basis of the reference clock signal and the timing control signal input to the device.

The image signal processing section560is a circuit that applies various types of signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of an imaging operation in the imaging device1. The image signal processing section560includes, for example, an image signal processing circuit section and a data holding section. The image signal processing section560may include a processor section.

An example of signal processing executed in the image signal processing section560is a tone curve correction process of increasing levels of gradations in a case where the AD converted imaging data is data obtained by imaging a dark subject and reducing the levels of gradations in a case where the AD converted imaging data is data obtained by imaging a bright subject. In this case, it is desirable to preliminarily store, in the data holding section of the image signal processing section560, the characteristic data of the tone curve, that is, which tone curve is to be used as a bases of the correction of gradation of the imaging data.

The input section510A is, for example, a section provided for inputting the above-described reference clock signal, the timing control signal, the characteristic data, and the like from the outside of the device to the imaging device1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, or the like. The characteristic data is data to be stored in the data holding section of the image signal processing section560, for example. The input section510A includes an input terminal511, an input circuit section512, an input amplitude changing section513, an input data conversion circuit section514, and a power supply section (not depicted), for example.

The input terminal511is an external terminal for inputting data. The input circuit section512is a unit provided for capturing a signal input to the input terminal511into the imaging device1. The input amplitude changing section513changes the amplitude of the signal captured by the input circuit section512to an amplitude highly usable inside the imaging device1. The input data conversion circuit section514changes the arrangement of data strings of the input data. The input data conversion circuit section514is constituted with a serial-to-parallel conversion circuit, for example. The serial-to-parallel conversion circuit converts a serial signal received as input data into a parallel signal. The input section510A can omit the input amplitude changing section513and the input data conversion circuit section514. The power supply section supplies power set to various voltages required inside the imaging device1on the basis of power supplied from the outside to the imaging device1.

When the imaging device1is connected to an external memory device, the input section510A may be provided with a memory interface circuit that receives data from the external memory device. Examples of the external memory device include a flash drive, SRAM, and DRAM.

The output section510B outputs image data to the outside of the device. Examples of the image data include image data captured by the imaging device1, image data that has undergone signal processing performed by the image signal processing section560, and the like. The output section510B includes, for example, an output data conversion circuit section515, an output amplitude changing section516, an output circuit section517, and an output terminal518.

The output data conversion circuit section515is, for example, constituted with a parallel-to-serial conversion circuit, and thus, the output data conversion circuit section515converts a parallel signal used inside the imaging device1into a serial signal. The output amplitude changing section516changes the amplitude of a signal used inside the imaging device1. The signal having amplitude changed will have high usability in an external device connected to the outside of the imaging device1. The output circuit section517is a circuit that outputs data from the inside of the imaging device1to the outside of the device. The output circuit section517also drives wiring outside the imaging device1connected to the output terminal518. Data is output from the imaging device1to the outside of the device via the output terminal518. The output section510B can omit the output data conversion circuit section515and the output amplitude changing section516.

When the imaging device1is connected to an external memory device, the output section510B may be provided with a memory interface circuit that outputs data to the external memory device. Examples of the external memory device include a flash drive, SRAM, and DRAM. [Schematic configuration of imaging device1]

FIGS.2and3depict an example of a schematic configuration of the imaging device1. The imaging device1includes three substrates (a first substrate100, a second substrate200, and a third substrate300).FIG.2schematically depicts a planar configuration of each of the first substrate100, the second substrate200, and the third substrate300.FIG.3schematically depicts a cross-sectional configuration of the first substrate100, the second substrate200, and the third substrate300stacked on each other.FIG.3corresponds to the cross-sectional configuration taken along line III-III′ depicted inFIG.2. The imaging device1is an imaging device having a three-dimensional structure formed by bonding three substrates (the first substrate100, the second substrate200, and the third substrate300). The first substrate100includes a semiconductor layer100S and a wiring layer100T. The second substrate200includes a semiconductor layer200S and a wiring layer200T. The third substrate300includes a semiconductor layer300S and a wiring layer300T. Here, a combination of the wiring included in each substrate of the first substrate100, the second substrate200, and the third substrate300together with an interlayer insulating film around the wiring is referred to as wiring layers (100T,200T, and300T) provided on each of the substrates (the first substrate100, the second substrate200, and the third substrate300) for convenience. The first substrate100, the second substrate200, and the third substrate300are stacked in this order, and specifically, the layers are stacked in order of the semiconductor layer100S, the wiring layer100T, the semiconductor layer200S, the wiring layer200T, the wiring layer300T, and the semiconductor layer300S in a stacking direction. Specific configurations of the first substrate100, the second substrate200, and the third substrate300will be described below. The arrow depicted inFIG.3indicates the incident direction of light L on the imaging device1. In the following cross-sectional views in the present specification, the light incident side in the imaging device1may be referred to as “lower”, “lower side”, or “below”, and the side opposite to the light incident side may be referred to as “upper”, “upper side”, or “above” for convenience. In addition, in the present specification, for convenience, in a substrate including a semiconductor layer and a wiring layer, a side of the wiring layer may be referred to as a front surface, and a side of the semiconductor layer may be referred to as a back surface. The description of the specification is not limited to the above terms. The imaging device1is, for example, a back-illuminated imaging device in which light enters from the back surface side of the first substrate100having a photodiode.

Both the pixel array section540and the pixel sharing unit539included in the pixel array section540are constituted by using both the first substrate100and the second substrate200. The first substrate100is provided with the plurality of pixels541A,541B,541C, and541D included in the pixel sharing unit539. Each of these pixels541includes a photodiode (photoelectric conversion section101described below) and a transfer transistor (charge transfer section102described below). The second substrate200is provided with a pixel circuit (the pixel circuit210to be described below) included in the pixel sharing unit539. The pixel circuit reads out the pixel signal transferred from the photodiode of each of the pixels541A,541B,541C, and541D via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate200includes a plurality of row drive signal lines542extending in the row direction and a plurality of vertical signal lines543extending in the column direction. The second substrate200further includes a power supply line544extending in the row direction. The third substrate300includes, for example, an input section510A, a row drive section520, a timing controlling section530, a column signal processing section550, an image signal processing section560, and an output section510B. The region in which the row drive section520is located partially overlaps the pixel array section540in the stacking direction of the first substrate100, the second substrate200, and the third substrate300(hereinafter, simply referred to as the stacking direction), for example. More specifically, the row drive section520is provided in a region overlapping the vicinity of an end of the pixel array section540in the H direction in the stacking direction (FIG.2). The column signal processing section550is provided, for example, in a region partially overlapping the pixel array section540in the stacking direction. More specifically, the column signal processing section550is provided in a region overlapping the vicinity of the end of the pixel array section540in the V direction, in the stacking direction (FIG.2). Although not depicted, the input section510A and the output section510B may be disposed in a portion other than the third substrate300, and may be disposed on the second substrate200, for example. Alternatively, the input section510A and the output section510B may be provided on the back surface (light incident surface) side of the first substrate100. The pixel circuit provided on the second substrate200may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit as an alternative term. In the present specification, the term “pixel circuit” is used.

The first substrate100and the second substrate200are electrically connected by a through-substrate electrode (through-substrate electrodes252,253A and253B ofFIG.6to be described below), for example. The second substrate200and the third substrate300are electrically connected via contact sections201,202,301, and302, for example. The contact sections201and202are provided on the second substrate200, while the contact sections301and302are provided on the third substrate300. The contact section201of the second substrate200is in contact with the contact section301of the third substrate300, while the contact section202of the second substrate200is in contact with the contact section302of the third substrate300. The second substrate200has a contact region201R including a plurality of the contact sections201and a contact region202R including a plurality of the contact sections202. The third substrate300has a contact region301R including a plurality of the contact sections301and a contact region302R including a plurality of the contact sections302. The contact regions201R and301R are provided between the pixel array section540and the row drive section520in the stacking direction (FIG.3). In other words, the contact regions201R and301R are provided, for example, in a region where the row drive section520(on the third substrate300) and the pixel array section540(on the second substrate200) overlap each other in the stacking direction or in a region in their vicinity. The contact regions201R and301R are disposed at ends in the H direction in such regions, for example (FIG.2). In the third substrate300, for example, the contact region301R is provided at a position overlapping a part of the row drive section520, specifically the end of the row drive section520in the H direction (FIGS.2and3). The contact sections201and301connect, for example, the row drive section520provided on the third substrate300and the row drive signal line542provided on the second substrate200to each other. For example, the contact sections201and301may connect the input section510A provided on the third substrate300, the power supply line544, and a reference potential line (a ground line described below) to each other. The contact regions202R and302R are provided between the pixel array section540and the column signal processing section550in the stacking direction (FIG.3). In other words, the contact regions202R and302R are provided, for example, in a region where the column signal processing section550(on the third substrate300) and the pixel array section540(on the second substrate200) overlap each other in the stacking direction or in a region in their vicinity. The contact regions202R and302R are disposed at ends in the V direction in such regions, for example (FIG.2). In the third substrate300, for example, the contact region301R is provided at a position overlapping a part of the column signal processing section550, specifically, the end of the column signal processing section550in the V direction (FIGS.2and3). The contact sections202and302are provided for connecting a pixel signal (a signal corresponding to the amount of charge generated as a result of photoelectric conversion in a photodiode) output from each of the plurality of pixel sharing units539included in the pixel array section540to the column signal processing section550provided on the third substrate300. The pixel signal is to be transmitted from the second substrate200to the third substrate300.

FIG.3is an example of a cross-sectional view of the imaging device1as described above. The first substrate100, the second substrate200, and the third substrate300are electrically connected to each other via the wiring layers100T,200T, and300T. For example, the imaging device1includes an electrical connecting location that electrically connects the second substrate200and the third substrate300to each other. Specifically, the contact sections201,202,301, and302are formed with electrodes formed of a conductive material. The conductive material is formed of, for example, a metal material such as copper (Cu), aluminum (Al), or gold (Au). By directly bonding wiring lines formed as electrodes, for example, the contact regions201R,202R,301R, and302R electrically connect the second substrate and the third substrate to each other, enabling signal input and/or output between the second substrate200and the third substrate300.

An electrical connecting location that electrically connects the second substrate200and the third substrate300can be provided at a desired location. For example, as described as the contact regions201R,202R,301R, and302R inFIG.3, the contact regions may be provided in a region overlapping the pixel array section540in the stacking direction. The electrical connecting location may be provided in a region not overlapping the pixel array section540in the stacking direction. Specifically, it may be provided in a region overlapping a peripheral portion disposed outside the pixel array section540in the stacking direction.

The first substrate100and the second substrate200are provided with connection holes H1and H2, for example. The connection holes H1and H2penetrate the first substrate100and the second substrate200(FIG.3). The connection holes H1and H2are provided outside the pixel array section540(or a portion overlapping the pixel array section540) (FIG.2). For example, the connection hole H1is disposed outside the pixel array section540in the H direction, while the connection hole H2is disposed outside the pixel array section540in the V direction. For example, the connection hole H1reaches the input section510A provided in the third substrate300, while the connection hole H2reaches the output section510B provided in the third substrate300. The connection holes H1and H2may be hollow, and may at least a partially contain a conductive material. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input section510A and/or the output section510B. Alternatively, there is a configuration in which the electrode formed as the input section510A and/or the output section510B is connected to the conductive material provided in the connection holes H1and H2. The conductive material provided in the connection holes H1and H2may be embedded in a part or all of the connection holes H1and H2, and the conductive material may be formed on side walls of the connection holes H1and H2.

FIG.3is a case of a structure in which the input section510A and the output section510B are provided on the third substrate300, but the present disclosure is not limited thereto. For example, by sending a signal of the third substrate300to the second substrate200via the wiring layers200T and300T, the input section510A and/or the output section510B can be provided on the second substrate200. Similarly, by sending a signal of the second substrate200to the first substrate1000via the wiring layers100T and200T, the input section510A and/or the output section510B can be provided on the first substrate100.

Note that the imaging device1and the pixel array section540are examples of an imaging element described in the claims.

FIG.4is an equivalent circuit diagram depicting an example of a configuration of the pixel sharing unit. The pixel sharing unit539includes the plurality of pixels541(FIG.4depicts four pixels541, namely, the pixels541A,541B,541C, and541D), one pixel circuit210connected to the plurality of pixels541, and a vertical signal line543connected to the pixel circuit210. The pixel circuit210includes, for example, four transistors, specifically, an amplification transistor213, a selection transistor214, a reset transistor211, and a capacitance switching transistor212. As described above, by operating one pixel circuit210in time division, the pixel sharing unit539is configured to sequentially output the pixel signals of the four pixels541(pixels541A,541B,541C, and541D) included in the pixel sharing unit539to the vertical signal line543. The mode in which one pixel circuit210is connected to the plurality of pixels541and pixel signals of the plurality of pixels541are output by the one pixel circuit210in time division is referred to as a mode in which “the plurality of pixels541shares one pixel circuit210”.

The pixels541A,541B,541C, and541D have components common to each other.

The pixels541A,541B,541C, and541D include, for example, a photoelectric conversion section101, a charge transfer section102electrically connected to the photoelectric conversion section101, and a charge holding section103electrically connected to the charge transfer section102. The photoelectric conversion section101(photoelectric conversion sections101A,101B,101C, and101D) has a cathode electrically connected to a source of the charge transfer section102and has an anode electrically connected to a reference potential line (for example, a ground line). The photoelectric conversion section101performs photoelectric conversion of incident light and generates a charge corresponding to the amount of received light. The charge transfer section102(charge transfer sections102A,102B,102C, and102D) is an n-channel MOS transistor, for example. The charge transfer section102has a drain electrically connected to the charge holding section103and has a gate electrically connected to a drive signal line (signal lines TG1, TG2, TG3, and TG4). This drive signal line is a part of the plurality of row drive signal lines542(refer toFIG.1) connected to one pixel sharing unit539. The charge transfer section102transfers the charge generated in the photoelectric conversion section101to the charge holding section103. The charge holding section103(charge holding sections103A,103B,103C, and103D) is an n-type diffusion layer region formed in the p-type semiconductor layer. Such charge holding section103is referred to as floating diffusion (FD). The charge holding section103is a charge holding means that temporarily holds the charge transferred from the photoelectric conversion section101, and is a charge-voltage conversion means that generates a voltage corresponding to the charge amount.

The four charge holding sections103(charge holding sections103A,103B,103C, and103D) included in one pixel sharing unit539are electrically connected to each other and electrically connected to the gate of the amplification transistor213and the source of the capacitance switching transistor212. The drain of the capacitance switching transistor212is connected to the source of the reset transistor211, while the gate of the capacitance switching transistor212is connected to a drive signal line FDG. This drive signal line FDG is a part of the plurality of row drive signal lines542connected to one pixel sharing unit539. The drain of the reset transistor211is connected to a power supply line Vdd, while the gate of the reset transistor211is connected to the drive signal line RST. This drive signal line RST is a part of the plurality of row drive signal lines542connected to one pixel sharing unit539. The gate of the amplification transistor213is connected to the charge holding section103, the drain of the amplification transistor213is connected to the power supply line Vdd, and the source of the amplification transistor213is connected to the drain of the selection transistor214. The source of the selection transistor214is connected to the vertical signal line543, while the gate of the selection transistor214is connected to the drive signal line SEL. This drive signal line SEL is a part of the plurality of row drive signal lines542connected to one pixel sharing unit539.

When the charge transfer section102is turned on, the charge transfer section102transfers the charge of the photoelectric conversion section101to the charge holding section103. A gate (transfer gate) of the charge transfer section102includes, for example, an electrode referred to as a vertical electrode, and is provided to extend from a front surface of a semiconductor layer (a semiconductor layer100S inFIG.6to be described below) to a depth reaching the photoelectric conversion section101as depicted inFIG.6to be described below. The reset transistor211resets the potential of the charge holding section103to a predetermined potential. When the reset transistor211is turned on, the potential of the charge holding section103is reset to the potential of the power supply line Vdd. The selection transistor214controls an output timing of the pixel signal from the pixel circuit210. The amplification transistor213generates a signal of a voltage corresponding to the level of the charge held in the charge holding section103as a pixel signal. The amplification transistor213is connected to the vertical signal line543via the selection transistor214. The amplification transistor213constitutes a source follower together with a load circuit section (refer toFIG.1) connected to the vertical signal line543in the column signal processing section550. When the selection transistor214is turned on, the amplification transistor213outputs the voltage of the charge holding section103to the column signal processing section550via the vertical signal line543. The reset transistor211, the amplification transistor213, and the selection transistor214are n-channel MOS transistors, for example.

The capacitance switching transistor212is used to change a gain of charge-voltage conversion in the charge holding section103. In general, a pixel signal is weak at the time of photographing in a dark place. Based on Q=CV, when the capacitance (FD capacitance C) of the charge holding section103is large at the time of performing charge-voltage conversion, this results in a small V at the time of conversion into a voltage by the amplification transistor213. On the other hand, in a bright place, the pixel signal becomes large, and thus, the charge holding section103cannot receive the charge of the photoelectric conversion section101unless the FD capacitance C is large. Further, the FD capacitance C needs to be large so that V when converted into a voltage by the amplification transistor213does not become too high (in other words, so as to be low). In view of these, when the capacitance switching transistor212is turned on, the gate capacitance for the capacitance switching transistor212increases, leading to a large entire FD capacitance C. In contrast, turning off the capacitance switching transistor212decreases the entire FD capacitance C. In this manner, switching on/off of the capacitance switching transistor212can achieve variable FD capacitance C, making it possible to switch the conversion efficiency. The capacitance switching transistor212is an re-channel MOS transistor, for example.

Incidentally, it is also possible to have a configuration not including the capacitance switching transistor212. At this time, for example, the pixel circuit210includes three transistors, for example, an amplification transistor213, a selection transistor214, and a reset transistor211. The pixel circuit210includes, for example, at least one of pixel transistors such as an amplification transistor213, a selection transistor214, a reset transistor211, and a capacitance switching transistor212.

The selection transistor214may be provided between the power supply line Vdd and the amplification transistor213. In this case, the drain of the reset transistor211is electrically connected to the power supply line Vdd and the drain of the selection transistor214. The source of the selection transistor214is electrically connected to the drain of the amplification transistor213, while the gate of the selection transistor214is electrically connected to the row drive signal line542(refer toFIG.1). The source of the amplification transistor213(an output end of the pixel circuit210) is electrically connected to the vertical signal line543, while the gate of the amplification transistor213is electrically connected to the source of the reset transistor211. Note that, although not depicted, the number of pixels541sharing one pixel circuit210may be other than four. For example, two or eight pixels541may share one pixel circuit210. [Configuration of pixel sharing unit]

FIG.5is a diagram depicting a configuration example of a pixel sharing unit according to the embodiment of the present disclosure. The drawing is a plan view depicting a configuration example of the pixel sharing unit539. In addition,FIG.5is a diagram depicting configurations of the first substrate100and the second substrate200viewed from the side of the second substrate200.

In the drawing, regions with diagonal hatching represent regions of the semiconductor substrates (a first semiconductor substrate120and a second semiconductor substrate220). A dotted polygon represents a semiconductor region formed on the first semiconductor substrate120. A region with net hatching represents an isolating section (isolating section171) formed on the first semiconductor substrate120. A region with dot hatching represents a semiconductor region formed on the second semiconductor substrate220. A two-dot chain line rectangle represents a gate electrode. A dotted circle represents a connecting location (connecting location151) that connects the well region of the first semiconductor substrate120and the well region of the second semiconductor substrate220to each other. A dashed circle represents a contact plug (contact plug244) formed on the second semiconductor substrate220. A solid circle represents through-substrate electrodes (through-substrate electrodes252and253).

As described above, the pixels541A,541B,541C, and541D are disposed on the first substrate100. As depicted in the figure, the pixels541A,541B,541C, and541D are disposed in a 2 row×2 column pattern, and the charge holding sections103A,103B,103C, and103D are disposed in the vicinity of the central portions thereof. The charge transfer sections102A,102B,102C, and102D and the photoelectric conversion sections101A,101B,101C, and101D are disposed adjacent to the charge holding sections103A,103B,103C, and103D, respectively.

The pixel circuit210is disposed on the second substrate200. The reset transistor211and the capacitance switching transistor212are disposed adjacent to each other, and the amplification transistor213and the selection transistor214are disposed adjacent to each other. The figure depicts an example in which the reset transistor211and the capacitance switching transistor212are disposed in a region overlapping the pixels541D and541B, respectively, while the amplification transistor213and the selection transistor214are disposed at positions overlapping the pixels541A and541C, respectively. Note that the amplification transistor213and the selection transistor214are formed in a semiconductor region226disposed in the same layer as the second semiconductor substrate220.

The reset transistor211and the capacitance switching transistor212are disposed in a well region of the second semiconductor substrate220included in the semiconductor layer200S described above. The reset transistor211in the drawing is provided with a drain region formed on the left side of the gate electrode and provided with a source region formed on the right side of the gate electrode. The source region of the reset transistor211also corresponds to the drain region of the capacitance switching transistor212. The gate electrode and the source region are sequentially disposed adjacent to the drain region of the capacitance switching transistor212.

An element isolating region261(element isolating region261B) is disposed around the reset transistor211and the capacitance switching transistor212. The element isolating region261, which is a groove-shaped region formed on the front surface side of the second semiconductor substrate220, isolates the diffusion layer of the element disposed on the second semiconductor substrate220. The element isolating regions261allow adjacent elements to be isolated from each other while sharing the reference potential. In the element isolating region261, the connecting location151is disposed. The drawing depicts the element isolating regions261A and261B.

The amplification transistor213and the selection transistor214are disposed separately from the reset transistor211and the capacitance switching transistor212. The amplification transistor213is provided with a drain region formed on the right side of the gate electrode and provided with a source region formed on the left side of the gate electrode. The source region of the amplification transistor213also corresponds to the drain region of the selection transistor214. The gate electrode and the source region are sequentially disposed adjacent to the drain region of the selection transistor214.

By removing the second semiconductor substrate220, a substrate isolating region262is formed to be disposed around the amplification transistor213and the selection transistor214. By disposing the substrate isolating region262, the amplification transistor213and the selection transistor214can be insulated from the reset transistor211and the like.

[Configuration of Cross-Section of Imaging Device]

FIG.6is a cross-sectional view depicting a configuration example of the imaging device according to the embodiment of the present disclosure. The figure is a cross-sectional view depicting a configuration example of the imaging device1, and is a cross-sectional view taken along line a-a′ inFIG.5. The imaging device1in the drawing includes a first substrate100, a second substrate200, and a third substrate300. As described above, the first substrate100includes the semiconductor layer100S and the wiring layer100T, the second substrate200includes the semiconductor layer200S and the wiring layer200T, and the third substrate300includes the semiconductor layer300S and the wiring layer300T. Further, the imaging device1further includes a color filter181and an on-chip lens401.

The semiconductor layer100S includes a first semiconductor substrate120, insulating films128and129, and an isolating section171.

The first semiconductor substrate120is a semiconductor substrate on which the photoelectric conversion section101is disposed. The charge transfer section102and the charge holding section103are further disposed on the first semiconductor substrate120in the drawing. The drawing depicts the photoelectric conversion sections101A and101B, the charge transfer sections102A and102B, and the charge holding sections103A and103B. The first semiconductor substrate120can be formed of silicon (Si), for example. The photoelectric conversion section101and the like are disposed in a well region formed in the first semiconductor substrate120. For convenience, it is assumed that the first semiconductor substrate120in the drawing constitutes a p-type well region. By disposing an n-type semiconductor region in the p-type well region, an element (a diffusion layer of element) can be formed.

A rectangle described in the first semiconductor substrate120in the drawing represents an n-type semiconductor region. The photoelectric conversion section101A is constituted with an n-type semiconductor region121A. Specifically, a photodiode, constituted by a p-n junction formed at an interface between the n-type semiconductor region121A and the surrounding p-type well region, corresponds to the photoelectric conversion section101A. As depicted in the drawing, the photoelectric conversion section101A is formed closer to the back surface side of the first semiconductor substrate120. The photoelectric conversion section101B is constituted similarly to the photoelectric conversion section101A.

The charge transfer section102A is constituted with the semiconductor regions121A and122A and a gate electrode131A. The n-type semiconductor regions121A and122A correspond to the source region and the drain region of the charge transfer section102A. As depicted in the drawing, the n-type semiconductor region121A is formed closer to the back surface side of the first semiconductor substrate120, while the n-type semiconductor region122A is formed on front-side surface of the first semiconductor substrate120. The gate electrode131A includes a columnar portion disposed on the front surface side of the first semiconductor substrate120and having a depth reaching the n-type semiconductor region121A. When a drive voltage is applied to the gate electrode131A, a channel is formed in a well region adjacent to the gate electrode131A, allowing the n-type semiconductor regions121A and122A to be conductive. That is, conduction is established between the photoelectric conversion section101A and the charge holding section103A, allowing the charge of the photoelectric conversion section101A to be transferred to the charge holding section103A. In this manner, the charge transfer section102A is constituted with a vertical transistor that transfers a charge in the thickness direction of the semiconductor substrate.

Similarly to the charge transfer section102A, the charge transfer section102B includes semiconductor regions121B and122B and a gate electrode131B. The gate electrodes131A and131B can be formed with polycrystalline silicon implanted with impurities.

Note that semiconductor regions123A and123B are disposed on the first semiconductor substrate120. The semiconductor regions123A and123B, being semiconductor regions disposed in the well region of the first semiconductor substrate120, are semiconductor regions having the same conductivity type as the well region and formed to have a relatively high impurity concentration.

The insulating film129is a film that insulates the front surface side of the first semiconductor substrate120. Further, the insulating film128is a film that insulates the back surface side of the first semiconductor substrate120. These films can be formed with silicon oxide (SiO2) or silicon nitride (SiN). The insulating film129is also disposed between the gate electrodes131A and131B and the first semiconductor substrate120. The insulating film129corresponds to a gate oxide film.

The isolating section171is disposed at a boundary of the pixels541to isolate the pixels541from each other. The drawing depicted an example in which the pixels541A and541B are isolated from each other by the isolating section171. The isolating section171can be constituted by embedding an insulator such as SiO2in a groove portion penetrating from the back surface side to the front surface side of the first semiconductor substrate120.

The wiring layer100T includes an insulating layer141, a pad132, and connecting locations151A and151B. The insulating layer141insulates the gate electrode131, the pad132, and the like disposed on the front surface side of the first semiconductor substrate120. The insulating layer141can be formed of SiO2, for example. The pad132is an electrode connected to the charge holding sections103A and103B and the charge holding sections103C and103D (not depicted). The pad132is further connected to a through-substrate electrode252described below. The pad132can be formed with polycrystalline silicon implanted with impurities.

The connecting locations151A and151B connect the first semiconductor substrate120and the second semiconductor substrate220in order to allow the reference potential (well potential) of the first semiconductor substrate120and the second semiconductor substrate220to be used in common. The connecting location151A is disposed between the semiconductor region123A and a high impurity concentration region225A to be described below, while the connecting location151B is disposed between the semiconductor region123B and a high impurity concentration region225B to be described below. The connecting locations151A and151B can be formed with polycrystalline silicon implanted with impurities. Note that the connecting locations151A and151B are also referred to as well contacts.

The semiconductor layer200S includes a second semiconductor substrate220, a semiconductor region226, an element isolating region261, a high impurity concentration region225, and an insulating film229.

The second semiconductor substrate220is a semiconductor substrate on which the pixel circuit210is disposed. In the drawing, the capacitance switching transistor212and the amplification transistor213of the pixel circuit210are depicted as being disposed on the second semiconductor substrate220. Similarly to the first semiconductor substrate120, the second semiconductor substrate220can be formed of Si. In addition, similarly to the first semiconductor substrate120, a p-type well region is formed in the second semiconductor substrate220. For convenience, it is assumed that the second semiconductor substrate220in the drawing constitutes a p-type well region.

The capacitance switching transistor212includes n-type semiconductor regions221and222and a gate electrode231. As described above, the capacitance switching transistor212is isolated by the element isolating region261(element isolating region261B). As depicted in the drawing, the element isolating region261B is formed in a groove shape having a depth that isolates a region where a diffusion layer (n-type semiconductor region221or the like) formed on the front surface side of the second semiconductor substrate220is formed. Note that the element isolating region261is a region in which an insulating layer241to be described below is disposed.

The amplification transistor213, being formed in the semiconductor region226, is constituted with: a semiconductor region (not depicted) constituting a drain region and a source region; and a gate electrode232. As described above, the semiconductor region226where the amplification transistor213is formed is isolated from the second semiconductor substrate220by the substrate isolating region262. The substrate isolating region262is an isolating region formed by removing the second semiconductor substrate220. The insulating layer241to be described below is also disposed in the substrate isolating region262.

The high impurity concentration region225is a semiconductor region disposed at the bottom of the element isolating region261and configured to have a relatively high impurity concentration of the same conductivity type as the well region of the second semiconductor substrate220. The drawing depicts the high impurity concentration regions225A and225B.

The wiring layer200T includes an insulating layer241, a wiring line242, a via plug243, a contact plug244, through-substrate electrodes252,253A, and253B, second connecting locations251A and251B, and contact sections201and202. The wiring line242is a conductor that transmits an electric signal or the like to an element or the like disposed on the second semiconductor substrate220. The wiring line242can be formed of metal such as copper (Cu). The insulating layer241insulates the wiring line242and the like. Similarly to the insulating layer141, the insulating layer241can be formed of SiO2or the like. The wiring line242and the insulating layer241can be configured in multiple layers. The drawing depicts the wiring line242and the insulating layer241configured in three layers as an example. The wiring lines242disposed in different layers can be connected to each other by the via plug243. The via plug243can be formed of columnar metal such as columnar Cu, for example. In addition, the wiring line242and the semiconductor region222, the gate electrode231, and the like of the second semiconductor substrate220can be connected by the contact plug244. The contact plug244can be formed of a columnar metal such as a columnar W, for example.

The through-substrate electrode252and the like are columnar electrodes that connect the wiring line242and a member disposed on the front surface side of the first semiconductor substrate120. The through-substrate electrode252is connected to the pad132. The through-substrate electrodes253A and253B are connected to the gate electrodes131A and131B, respectively. These through-substrate electrodes252and the like can be formed of metal such as W, and can be disposed in the substrate isolating region262.

The second connecting locations251A and251B connect the second semiconductor substrate220and a third semiconductor substrate320in order to allow the reference potential to be used in common with another circuit, for example, a circuit disposed on the third substrate300. The second connecting locations251A and251B can be formed of a columnar W, for example. Note that the second connecting locations251A and251B in the drawing are connected to the third substrate300via the wiring line242, the via plug243, and the contact section201.

As described above, the contact sections201and202are connected to the contact sections301and303of the third substrate300, respectively. The contact section201is connected to the second connecting location251and transmits the reference potential. The contact section202is used to transmit signals and the like.

The semiconductor layer300S includes the third semiconductor substrate320. The above-described image signal processing section560(not depicted) and the like are disposed on the third semiconductor substrate320. In addition, a well region is formed in the third semiconductor substrate320. A semiconductor region321is disposed in this well region. Similarly to the semiconductor region123, the semiconductor region321is formed to have a relatively high impurity concentration, and is connected to a contact plug344.

The wiring layer300T includes an insulating layer341, a wiring342, a via plug343, a contact plug344, and contact sections301and302. Since these configurations are similar to the insulating layer241, the wiring line242, the via plug243, the contact plug244, and the contact sections301and302, the description thereof will be omitted.

As depicted in the drawing, the second connecting location251is connected to the semiconductor region321of the third semiconductor substrate320via the wiring line242, the via plug243, the contact section201, the contact section301, the via plug343, the wiring342, and the contact plug344. With this configuration, the well region of the second semiconductor substrate220is electrically connected with the well region of the third semiconductor substrate320, allowing the reference potential to be used in common. The reference potential can be obtained by applying a ground potential of a power supply circuit connected to the third semiconductor substrate320, for example. In addition, a fixed potential other than the ground potential is also applicable to the reference potential. In this manner, the reference potential is supplied to the second semiconductor substrate220via the second connecting location251.

The color filter181is an optical filter that is disposed for each pixel541and transmits light having a predetermined wavelength among the incident light. The on-chip lens401is a lens that is disposed for each pixel541and condenses incident light onto the photoelectric conversion section101. [Configuration of pixel sharing unit]

FIG.7is a diagram depicting a configuration example of a pixel sharing unit according to the first embodiment of the present disclosure. The drawing is a schematic cross-sectional view depicting a configuration example of the first semiconductor substrate120and the second semiconductor substrate220including the connecting location151in the pixel sharing unit539. The drawing depicts some of the component in the cross-sectional view ofFIG.6, specifically, elements of the photoelectric conversion section101, the charge transfer section102, the charge holding section103, and the pixel circuit210, together with the semiconductor region123, the high impurity concentration region225, the connecting location151, and the second connecting location251. Note that the capacitance switching transistor212and the amplification transistor213are depicted as the pixel circuit210, without depicting the reset transistor211or the selection transistor214.

The photoelectric conversion section101is connected to the charge holding section103via the charge transfer section102which is a vertical transistor. The charge holding section103is connected to the wiring line242by the through-substrate electrode253. A source region of the capacitance switching transistor212and a gate electrode of the amplification transistor213are connected to the wiring line242via the contact plug244.

The capacitance switching transistor212and the reset transistor211(not depicted), which are constituted as planar type MOS transistors, are formed in a well region of the second semiconductor substrate220. The capacitance switching transistor212and the reset transistor211are isolated from the capacitance switching transistor212and the reset transistor211of the adjacent pixel sharing unit539by the element isolating region261. The capacitance switching transistor212and the reset transistor211disposed in different pixel sharing units539are connected via a well region, and operate on the basis of a common reference potential (well potential).

On the other hand, the amplification transistor213and the selection transistor214(not depicted) are constituted in a shape in which the gate electrode232is disposed on three sides of the semiconductor region226having a cuboid shape, via the insulating film229. The amplification transistor213having such a shape is referred to as a fin FET (Fin FET). Further, the amplification transistor213and the like are MOS transistors that operate in a depletion mode. In order to achieve complete depletion of the amplification transistor213, the semiconductor region226is constituted to have a relatively low impurity concentration. In addition, the amplification transistor213and the selection transistor214are isolated and insulated from the second semiconductor substrate220on which the capacitance switching transistor212and the like are disposed by the substrate isolating region262. This allows the amplification transistor213and the selection transistor214to have floating potentials different from the reference potential of the second semiconductor substrate220.

As described below, the semiconductor region226is formed by isolating a part of the second semiconductor substrate220by the substrate isolating region262. Note that the semiconductor region226is an example of a semiconductor region described in the claims.

The semiconductor region123is disposed in the well region of the first semiconductor substrate120. As described above, the semiconductor region123is configured to have a relatively high impurity concentration of the same conductivity type as the well region. The well region of the first semiconductor substrate120is connected to the connecting location151for allowing the reference potential (well potential) to be used in common. These semiconductor regions123are semiconductor regions disposed to make ohmic connection between the connecting location151and the well region of the first semiconductor substrate120.

The high impurity concentration region225is disposed in the well region of the element isolating region261of the second semiconductor substrate220. The high impurity concentration region225is connected, on its back surface side, to the connecting location151and connected, on its front surface side, to the second connecting location251. As described above, the high impurity concentration region225is configured to have the same conductivity type as the well region, with a relatively high impurity concentration, for example, an impurity concentration of 5×1017cm−3or more. By disposing the high impurity concentration region225, the connection between the connecting location151and the second connecting location251and the well region of the second semiconductor substrate220can be achieved as ohmic connection. In addition, the resistance of the high impurity concentration region225can be reduced, making it possible to reduce the voltage drop in the high impurity concentration region225.

As depicted in the drawing, the second connecting location251is connected to the well region of the first semiconductor substrate120via the high impurity concentration region225and the connecting location151. The second connecting location251can be formed by embedding a metal such as W in an opening291formed in the insulating layer241.

As described above, the second connecting location251is connected to the circuit of the third semiconductor substrate320via the wiring line242or the like, and supplies the reference potential. A common reference potential is supplied to the well region of the second semiconductor substrate220and the well region of the first semiconductor substrate120connected to each other by the second connecting location251and the connecting location151. In this case, the well region of the first semiconductor substrate120and the well region of the second semiconductor substrate220are configured to have the same conductivity type. In an example of the drawing, the well region of the first semiconductor substrate120and the well region of the second semiconductor substrate220are configured to be p-type. Such a well region is referred to as a p-well. A reference potential corresponding to the lowest voltage of the signal voltage and the power supply voltage is applied to such a p-well. For example, the ground potential is supplied to the second connecting location251. This ground potential can be supplied via a ground line of a power supply circuit that supplies power to the imaging device1, for example. This ground line normally has a potential of 0 V.

In addition, by disposing the high impurity concentration region225at the bottom of the element isolating region261and connecting the connecting location151and the second connecting location251to the second semiconductor substrate220in the element isolating region261, it is possible to reduce the area of the second semiconductor substrate220. In addition, by disposing the high impurity concentration region225only on the bottom of the element isolating region261, it is possible, in the manufacturing steps, to isolate a region where impurities diffuse from the element isolating region261, from elements such as the capacitance switching transistor212.

As described above, the amplification transistor213and the selection transistor214operate in the depletion mode. In contrast, the capacitance switching transistor212operates in an enhancement mode. Therefore, the amplification transistor213and the selection transistor214can be configured to have an impurity concentration different from the concentration of the well region in which the capacitance switching transistor212and the like are disposed.

The high impurity concentration region225in the drawing is formed in a region ranging from the bottom of the element isolating region261to the back surface side of the second semiconductor substrate220. The configuration of the high impurity concentration region225is not limited to this example. For example, a high impurity concentration region can be disposed on each of the bottom portion of the element isolating region261and the back surface side of the second semiconductor substrate220. In this case, the well region is disposed between the respective high impurity concentration regions.

[Method of Manufacturing Pixel Array Section]

FIGS.8A to8Lare diagrams each depicting an example of a method of manufacturing the pixel array section according to the first embodiment of the present disclosure.FIGS.8A to8Lare diagrams depicting a step of forming the connecting location151, the second connecting location251, and elements of the second semiconductor substrate220in the manufacturing step of the pixel array section540.

First, a well region is formed in the first semiconductor substrate120to form the semiconductor region123and the like. Next, the insulating film129is disposed on the front-side surface of the first semiconductor substrate120. Next, the insulating layer141is disposed on the front surface side of the first semiconductor substrate120. This process can be performed by forming a film of SiO2or the like by a method such as chemical vapor deposition (CVD). Next, an opening is formed in the insulating layer141adjacent to the semiconductor region123. The connecting location151is disposed in the opening. This process can be performed by forming a film of polycrystalline silicon or the like using a method such as CVD and removing an excessive film (FIG.8A).

Next, the second semiconductor substrate220is stacked on the front surface side of the first semiconductor substrate120. This process can be performed by heating and pressing the first semiconductor substrate120and the second semiconductor substrate. Next, the second semiconductor substrate220is ground to a desired thickness (FIG.8B).

Next, a hard mask601is disposed on the front surface side of the second semiconductor substrate220. On the hard mask601, an opening602is disposed in a region where the element isolating region261is to be formed (FIG.8C).

Next, the second semiconductor substrate220in the opening602of the hard mask601is etched to form the element isolating region261. This process can be performed by dry etching, for example (FIG.8D).

Next, ion implantation of impurities such as boron (B), for example, is performed using the hard mask601as a mask to form the high impurity concentration region225(FIG.8E).

Next, after removing the hard mask601, a hard mask603is disposed. On the hard mask603, an opening604is disposed in a region where the substrate isolating region262is to be formed (FIG.8F).

Next, the second semiconductor substrate220in the opening604of the hard mask603is etched to form the substrate isolating region262(FIG.8G).

Next, the hard mask603is removed. Next, the insulating layer241is disposed on the front surface side of the second semiconductor substrate220including the element isolating region261and the substrate isolating region262. Next, the front surface side of the second semiconductor substrate220is ground, and the insulating layer241disposed in a region other than the element isolating region261and the substrate isolating region262is removed (FIG.8H). This process can be performed by chemical mechanical polishing (CMP).

Next, the semiconductor region221and the like are formed on the second semiconductor substrate220. This can be formed by disposing a resist having an opening in a region such as the semiconductor region221on the front surface side of the second semiconductor substrate220and performing ion implantation. Next, a hard mask605is disposed on the front surface side of the second semiconductor substrate220. In the hard mask605, an opening606is disposed in a region where the gate electrode232is to be formed (FIG.8I).

Next, the second semiconductor substrate220in the opening606of the hard mask605is etched to form an opening607(FIG.8J).

Next, the hard mask605is removed. Next, the insulating film229is disposed on the front-side surface of the second semiconductor substrate220(FIG.8K).

Next, the gate electrodes231and232are disposed. This process can be performed by forming a material film such as the gate electrode231on the front surface side of the second semiconductor substrate220including the opening607and removing a film of an unnecessary region (FIG.8L).

Next, the insulating layer241is stacked on the front surface side of the second semiconductor substrate220(FIG.8M). Next, the opening291is formed in the insulating layer241adjacent to the element isolating region261(N ofFIG.8N). This can be formed by disposing a resist having an opening in a region where the opening291is to be formed and performing dry etching, for example.

Next, the second connecting location251is disposed in the opening291(FIG.8O). This process can be performed by disposing a material film of the second connecting location251on the front surface side of the second semiconductor substrate220including the opening291and grinding an unnecessary film by CMP or the like.

Thereafter, the formation of the wiring line242and the formation of the insulating layer241is repeated for a desired number of layers to form the wiring layer200T. Thereafter, the third semiconductor substrate320is stacked.

Through the above steps, the connecting location151, the second connecting location251, and elements of the second semiconductor substrate220can be formed.

In this manner, in the imaging device1according to the first embodiment of the present disclosure, the high impurity concentration region225is disposed in the element isolating region261formed in the second semiconductor substrate220, and the connecting location151is connected for allowing the reference potential to be used in common with the first semiconductor substrate120. With this configuration, the region where the connecting location151is disposed can be disposed to overlap the region of the element isolating region261, making it possible to reduce the area of the second semiconductor substrate220. In addition, by disposing the second connecting location251in the high impurity concentration region225, it is possible to further reduce the area of the second semiconductor substrate220.

2. Second Embodiment

The imaging device1of the first embodiment described above includes the second connecting location251formed of metal. In contrast, an imaging device1according to a second embodiment of the present disclosure is different from the above-described first embodiment in that the imaging device1includes a second connecting location251formed of Si.

[Configuration of Pixel Sharing Unit]

FIG.9is a diagram depicting a configuration example of a pixel sharing unit according to the second embodiment of the present disclosure. The figure, similarly toFIG.7, is a schematic cross-sectional view depicting a configuration example of the first semiconductor substrate120including the connecting location151and the second semiconductor substrate220in the pixel sharing unit539. The imaging device in the drawing is different from the pixel sharing unit539inFIG.7in including a second connecting location254instead of the second connecting location251.

Similarly to the connecting location151, the second connecting location254is a connecting location formed of polycrystalline silicon. Note that the resistance of the polycrystalline silicon constituting the second connecting location254can be reduced by implanting impurities such as B, for example.

[Method for Manufacturing Connecting Location]

FIGS.10A to10Care diagrams depicting an example of a method of manufacturing the second connecting location according to the second embodiment of the present disclosure.FIGS.10A to10Care diagrams depicting an example of manufacturing steps of the second connecting location254.

First, the steps ofFIGS.8A to8Lare executed. Next, an opening291is formed in the insulating layer241disposed in the element isolating region261(FIG.10A).

Next, the second connecting location254is disposed in the opening291(FIG.10B). This process can be performed by forming a polycrystalline silicon film on the front surface side of the second semiconductor substrate220including the opening291and removing an unnecessary film.

Next, a resist609is disposed on the front surface side of the second semiconductor substrate220. The resist609has an opening610in the vicinity of the second connecting location254(FIG.100). Next, ion implantation of B is performed using the resist609as a mask. This process can reduce the resistance of the second connecting location254.

[Another Method for Manufacturing Connecting Location]

FIGS.11A to11Dare diagrams depicting another example of the method of manufacturing the second connecting location according to the second embodiment of the present disclosure. First, the steps ofFIGS.8A to8Dare executed. Next, impurities such as B included in the connecting location151are diffused into the second semiconductor substrate220adjacent to the connecting location151to form the high impurity concentration region225(FIG.11A). This process can be performed by thermal diffusion. Next, the steps ofFIGS.8E to8Lare executed to dispose the insulating layer241in the element isolating region261. Next, an opening291is formed in the insulating layer241and the second semiconductor substrate220(FIG.11B).

Next, similarly to the steps ofFIG.10B, the second connecting location254is disposed in the opening291(FIG.11C).

Next, the resist609described inFIG.100is disposed on the front surface side of the second semiconductor substrate220, and ion implantation of impurities is performed (FIG.11D). This process can reduce the resistance of the second connecting location254. At this time, ion implantation of B is also performed into the second semiconductor substrate220in the vicinity of the bottom of the second connecting location254, and the high impurity concentration region225is also formed on the front surface side of the second semiconductor substrate220.

The configuration of the imaging device1other than this is similar to the configuration of the imaging device1in the first embodiment of the present disclosure, and thus the description thereof will be omitted.

In this manner, in the imaging device1according to the second embodiment of the present disclosure, the reference potential is supplied to the second semiconductor substrate220and the first semiconductor substrate120by the second connecting location254formed of polycrystalline silicon into which impurities have been implanted.

The imaging device1of the first embodiment described above includes the fin FET isolated from the well region of the second semiconductor substrate220. In contrast, an imaging device1according to a third embodiment of the present disclosure is different from the above-described first embodiment in that the imaging device1includes a MOS transistor formed in a well region to which a potential different from that of the well region of the second semiconductor substrate220is supplied.

[Configuration of Pixel Sharing Unit]

FIG.12is a diagram depicting a configuration example of a pixel sharing unit according to the third embodiment of the present disclosure. The figure, similarly toFIG.7, is a schematic cross-sectional view depicting a configuration example of the first semiconductor substrate120including the connecting location151and the second semiconductor substrate220in the pixel sharing unit539. The imaging device in the drawing is different from the pixel sharing unit539inFIG.7in that the amplification transistor213is constituted with a p-channel MOS transistor.

The amplification transistor213in the drawing is formed with a p-channel MOS transistor. The amplification transistor213is formed in a semiconductor region226constituted in an n-type well region. Specifically, p-type semiconductor regions228and227corresponding to the source region and the drain region, respectively, are disposed in the well region of the semiconductor region226. A reference potential (well potential) different from the p-type well region in which the capacitance switching transistor212is disposed is supplied to the n-type well region. Specifically, the highest potential in a circuit such as a power supply line that supplies power is supplied as a reference potential to the n-type well region.

In this manner, since the reference potential is different from that of the second semiconductor substrate220constituted in the p-type well region, the semiconductor region226constituted in the n-type well region is isolated and insulated from the second semiconductor substrate220. The semiconductor region226in the drawing is isolated from the second semiconductor substrate220in the drawing by a substrate isolating region262. Such an n-type well region is also referred to as an n-well. The well region of the semiconductor region226can be formed by isolating the second semiconductor substrate220by the substrate isolating region262and adding an impurity such as phosphorus (P) by ion implantation.

In the well region of the semiconductor region226, a semiconductor region224configured to have a high n-type impurity concentration is disposed. The semiconductor region224is connected with a contact plug259. Through the contact plug259, a reference potential is supplied from the third semiconductor substrate320.

The imaging device1of the third embodiment is not limited to this example. For example, the semiconductor region226may be constituted as a p-type well region, and a reference potential having a potential different from that of the well region of the second semiconductor substrate220may be supplied. Specifically, when the ground potential is supplied as the reference potential of the well region of the second semiconductor substrate220, a negative reference potential can also be supplied to the well region of the semiconductor region226.

The configuration of the imaging device1other than this is similar to the configuration of the imaging device1in the first embodiment of the present disclosure, and thus the description thereof will be omitted.

In this manner, in the imaging device1according to the third embodiment of the present disclosure, a semiconductor element having the reference potential different from those of the first semiconductor substrate120and the second semiconductor substrate220can be disposed close to the second semiconductor substrate220. This makes it possible to increase variations of elements applicable to the pixel sharing unit539and the like.

In the imaging device1of the first embodiment described above, the second connecting location251is disposed in the element isolating region261. In contrast, an imaging device1according to a fourth embodiment of the present disclosure is different from the above-described first embodiment in that a second connecting location251is disposed in a region different from the element isolating region261.

[Configuration of Pixel Sharing Unit]

FIG.13Ais a diagram depicting a configuration example of a pixel sharing unit according to the fourth embodiment of the present disclosure. The figure, similarly toFIG.7, is a schematic cross-sectional view depicting a configuration example of the first semiconductor substrate120including the connecting location151and the second semiconductor substrate220in the pixel sharing unit539. The pixel sharing unit539in the drawing is different from the pixel sharing unit539inFIG.7in that the second connecting location251is disposed in a region different from the element isolating region261.

In the second semiconductor substrate220in the drawing, a semiconductor region223is disposed in a region different from the element isolating region261. The semiconductor region223is a semiconductor region constituted to have a high p-type impurity concentration. The second connecting location251is connected to the semiconductor region223. The reference potential is supplied via the second connecting location251. By disposing the second connecting location251at a position different from the element isolating region261, it is possible to easily form the second connecting location251. Even with a narrowed width of the element isolating region261, it is possible to reduce the occurrence of failures due to positional deviation of the second connecting location251or the like. Further, the figure depicts an example in which an element such as the capacitance switching transistor212is disposed between the second connecting location251and the connecting location151.

On the other hand, since the second connecting location251and the connecting location151are disposed apart from each other. Therefore, in the pixel sharing unit539in the drawing, the electrical resistance between the second connecting location251and the connecting location151is relatively large. This increases the voltage drop between the second connecting location251and the connecting location151, producing a potential difference in the well potential of the second semiconductor substrate220. This leads to a possibility of affecting the operation of the capacitance switching transistor212and the like disposed between the second connecting location251and the connecting location151.

In order to reduce the electrical resistance between the second connecting location251and the connecting location151, it is necessary to increase the impurity concentration of the well region to reduce the resistance as depicted in the drawing. However, increasing the impurity concentration of the well region of the second semiconductor substrate220would increase impurities to be diffused from the region to the periphery. Arrival of this diffusing impurity at the semiconductor region226of the amplification transistor213would increase the impurity concentration of the semiconductor region226, causing inhibition of depletion of the amplification transistor213. This causes deterioration of the performance of the amplification transistor213. In addition, in order to increase the impurity concentration in the well region of the second semiconductor substrate220, it is necessary to perform ion implantation with a high dose and high energy. When such ion implantation is performed, impurity ions would be also implanted into the semiconductor region226close to the second semiconductor substrate220, increasing and the impurity concentration of the semiconductor region226.

This type of problem, such as diffusion of impurities from the second semiconductor substrate220, is a problem that is likely to occur in the semiconductor region226described inFIG.12.

FIG.13Bis a diagram depicting another configuration example of the pixel sharing unit according to the fourth embodiment of the present disclosure. The pixel sharing unit539inFIG.13Bis different from the pixel sharing unit539inFIG.13Ain that the second connecting location251and the semiconductor region223are disposed adjacent to the element isolating region261.

The second connecting location251inFIG.13Bis disposed adjacent to the element isolating region261. Since the second connecting location251is disposed in the vicinity of the connecting location151, it is possible to reduce the electric resistance between the second connecting location251and the connecting location151, leading to reduction of the voltage drop in the portion. In addition, since elements such as the capacitance switching transistor212are disposed at positions away from the second connecting location251and the connecting location151, it is possible to reduce the influence of the voltage drop due to the semiconductor substrate between the second connecting location251and the connecting location151. With this configuration, reference potentials (well potentials) of substantially the same potential are applied to the plurality of elements disposed in the well region of the second semiconductor substrate220. This makes it possible, in the second semiconductor substrate220in the drawing, to set the impurity concentration in the well region be made relatively low. It is not necessary to reduce the resistance of the well region described inFIG.13A, making it possible to suppress the problems such as diffusion of impurities from the second semiconductor substrate220due to the reduction in the resistance of the well region.

Further, similarly to the pixel sharing unit539inFIG.13A, the pixel sharing unit539in the drawing has a configuration in which the second connecting location251is disposed at a position different from the element isolating region261. Therefore, the pixel sharing unit539in the drawing can easily form the second connecting location251while maintaining the impurity concentration in the well region of the second semiconductor substrate220at a low concentration.

The configuration of the imaging device1other than this is similar to the configuration of the imaging device1in the first embodiment of the present disclosure, and thus the description thereof will be omitted.

In this manner, in the imaging device1according to the fourth embodiment of the present disclosure, the second connecting location251is disposed at a position different from the element isolating region261. This makes it possible to facilitate formation of the second connecting location251.

5. Application Examples

FIG.14depicts an example of a schematic configuration of an imaging system7including the imaging device1according to the embodiments and their modifications.

The imaging system7is, for example, an electronic device exemplified by an imaging device such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system7includes, for example, the imaging device1according to the above-described embodiments and their modifications, a DSP circuit743, frame buffer memory744, a display section745, a storage section746, an operation section747, and a power supply section748. In the imaging system7, the imaging device1according to the above-described embodiments and their modifications, the DSP circuit743, the frame buffer memory744, the display section745, the storage section746, the operation section747, and the power supply section748are connected to each other via a bus line749.

The imaging device1according to the above-described embodiments and their modifications outputs image data according to incident light. The DSP circuit743is a signal processing circuit that processes a signal (image data) output from the imaging device1according to the above-described embodiments and their modifications. The frame buffer memory744temporarily holds the image data processed by the DSP circuit743in units of frames. The display section745includes, for example, a panel-type display device such as a liquid crystal panel or an organic electro luminescence (EL) panel, and displays a moving image or a still image captured by the imaging device1according to the above-described embodiments and their modifications. The storage section746records image data of a moving image or a still image captured by the imaging device1according to the above-described embodiments and their modifications in a recording medium such as semiconductor memory or a hard disk. The operation section747issues operation commands for various functions of the imaging system7in accordance with an operation by the user. The power supply section748appropriately supplies various types of power as operation power of the imaging device1according to the above-described embodiments and their modifications, the DSP circuit743, the frame buffer memory744, the display section745, the storage section746, and the operation section747to these supply targets.

Next, an imaging procedure in the imaging system7will be described.

FIG.15depicts an example of a flowchart of an imaging operation in the imaging system7. A user instructs start of imaging by operating the operation section747(step S101). Subsequently, the operation section747transmits an imaging command to the imaging device1(step S102). Having received the imaging command, the imaging device1(specifically, a system control circuit36) executes imaging by a predetermined imaging method (step S103).

The imaging device1outputs image data obtained by imaging to the DSP circuit743. Here, the image data represents data for all the pixels of the pixel signal generated on the basis of the charge temporarily held in the floating diffusion FD. The DSP circuit743performs predetermined signal processing (for example, noise reduction processing) on the basis of the image data input from the imaging device1(step S104). The DSP circuit743causes the frame buffer memory744to hold the image data subjected to predetermined signal processing, and then, the frame buffer memory744causes the storage section746to store the image data (step S105). In this manner, imaging in the imaging system7is performed.

In the present application example, the imaging device1according to the above-described embodiments and their modifications is applied to the imaging system7. With this application, the imaging device1can be downsized or have high definition, making it possible to provide the small or high definition imaging system7.

6. Example of Application to Mobile Body

The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure may be applied to devices mounted on any of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots.

Hereinabove, an example of the vehicle control system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure can be suitably applied to the imaging section12031among the configurations described above. Specifically, the imaging device1inFIG.1can be applied to the imaging section12031. By applying the technology according to the present disclosure to the imaging section12031, it is possible to downsize the imaging section12031.

7. Example of Application to Endoscopic Surgery System

The technology according to the present disclosure (the present technology) is applicable to various products. For example, the techniques according to the present disclosure may be applied to endoscopic surgery systems.

The endoscope11100includes a lens barrel11101having a region of a predetermined length from a distal end thereof to be inserted into a body lumen of the patient11132, and a camera head11102connected to a proximal end of the lens barrel11101. In the example depicted, the endoscope11100is depicted which includes as a hard mirror having the lens barrel11101of the hard type. However, the endoscope11100may otherwise be included as a soft mirror having the lens barrel11101of the soft type.

The lens barrel11101has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus11203is connected to the endoscope11100such that light generated by the light source apparatus11203is introduced to a distal end of the lens barrel11101by a light guide extending in the inside of the lens barrel11101and is irradiated toward an observation target in a body lumen of the patient11132through the objective lens. It is to be noted that the endoscope11100may be a direct view mirror or may be a perspective view mirror or a side view mirror.

FIG.19is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG.18.

Further, the image pickup unit11402may not necessarily be provided on the camera head11102. For example, the image pickup unit11402may be provided immediately behind the objective lens in the inside of the lens barrel11101. The driving unit11403includes an actuator and moves the zoom lens and the focusing lens of the lens unit11401by a predetermined distance along an optical axis under the control of the camera head controlling unit11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit11402can be adjusted suitably.

An example of the endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. The technique according to the present disclosure can be applied to, for example, the endoscope11100and the image pickup unit11402of the camera head11102among the configurations described above. Specifically, the imaging device1inFIG.1can be applied to the image pickup unit11402. By applying the technology according to the present disclosure to the image pickup unit11402, it is possible to downsize the image pickup unit11402.

Although the endoscopic surgery system has been described here as an example, the technique according to the present disclosure may be applied to, for example, a microscopic surgery system or the like.

Note that the amplification transistor213, the selection transistor214, and the charge transfer section102of the pixel sharing unit539can also be constituted with a planar type MOS transistor such as the capacitance switching transistor212inFIG.7. Further, the reset transistor211and the capacitance switching transistor212can be formed in the shape of a fin FET. In this manner, the amplification transistor213and the like can be constituted with transistors of various shapes.

Note that the configuration of the second embodiment of the present disclosure can be applied to other embodiments. Specifically, the second connecting location254inFIG.9can be applied to the third and fourth embodiments of the present disclosure.

Effects

The imaging element (pixel array section540) includes the first semiconductor substrate120and the second semiconductor substrate220. The first semiconductor substrate120includes the photoelectric conversion section101that performs photoelectric conversion of incident light. The second semiconductor substrate220includes: the pixel circuit210that generates an image signal according to a charge generated by the photoelectric conversion; the element isolating region261that isolates elements of the pixel circuit210; and the high impurity concentration region225which is disposed below the element isolating region261and having a high impurity concentration and is connected to the first semiconductor substrate120in order to use the reference potential in common. In addition, the first semiconductor substrate120is stacked on the back surface side of the second semiconductor substrate220. This has an effect that the high impurity concentration region225connected to the first semiconductor substrate120is disposed in the element isolating region261in order to allow the reference potential to be used in common. This makes it possible to reduce the area of the second semiconductor substrate220.

In addition, the semiconductor device may further include the connecting location151that connects the high impurity concentration region225and the first semiconductor substrate120to each other. With this configuration, the reference potentials of the first semiconductor substrate120and the second semiconductor substrate220can be used in common.

In addition, the high impurity concentration region225may be disposed in the well region of the second semiconductor substrate220, and the connecting location151may connect the high impurity concentration region225and the well region of the first semiconductor substrate120to each other. This makes it possible to allow the well potential of the first semiconductor substrate120and the second semiconductor substrate220to be used in common.

In addition, the connecting location151may be formed of silicon. This makes it possible to adopt a high-temperature process in the subsequent manufacturing steps.

It is allowable to further provide the second connecting location251that is disposed on the front surface side of the second semiconductor substrate220and supplies the reference potential. This makes it possible to supply the reference potential to the first semiconductor substrate120and the second semiconductor substrate220.

The second connecting location251may be disposed in the element isolating region261and connected to the high impurity concentration region225. This has an effect of having a configuration in which the second connecting location251and the connecting location151are stacked via the high impurity concentration region225. This makes it possible to reduce the resistance between the second connecting location251and the connecting location151.

The second connecting location251may be disposed adjacent to the element isolating region261. This makes it possible to reduce the resistance between the second connecting location251and the connecting location151.

It is also allowable to further include the third semiconductor substrate320stacked on the front surface side of the second semiconductor substrate220and connected to the second connecting location251. This makes it possible to supply the reference potential from the third semiconductor substrate320.

The second connecting location251may be formed of metal.

The second connecting location251may be formed of silicon.

The high impurity concentration region225may have an impurity concentration of 5×1017cm−3or more. This makes it possible to reduce the resistance between the second connecting location251and the connecting location151.

Further, the first semiconductor substrate120may include: the charge holding section103that holds the charge generated by the photoelectric conversion; and the charge transfer section102that transfers the charge from the photoelectric conversion section101to the charge holding section103. The pixel circuit210may generate an image signal according to the held charge.

In addition, it is also allowable to further include a semiconductor region disposed in the same layer as the second semiconductor substrate220.

In addition, a reference potential different from the reference potential may be supplied to the semiconductor region.

In addition, the high impurity concentration region225may be disposed in a well region of the second semiconductor substrate220, and the semiconductor region may be configured in a well region of a conductivity type different from the well region of the second semiconductor substrate220. This makes it possible to use complementary elements.

Further, it is also allowable to dispose, in the semiconductor region, the amplification transistor213that amplifies a signal based on a charge generated by the photoelectric conversion in the pixel circuit210. With this configuration, the amplification transistor213can be isolated from the well region of the second semiconductor substrate220.

Further, it is also allowable to dispose, in the semiconductor region, a selection transistor214that controls the output of the image signal in the pixel circuit210. With this configuration, the selection transistor214can be isolated from the well region of the second semiconductor substrate220.

The imaging device1includes: the first semiconductor substrate120; the second semiconductor substrate220; and the column signal processing section550. The first semiconductor substrate120includes the photoelectric conversion section101that performs photoelectric conversion of incident light. The second semiconductor substrate220includes: the pixel circuit210that generates an image signal according to a charge generated by the photoelectric conversion; the element isolating region261that isolates elements of the pixel circuit210; and the high impurity concentration region225which is disposed below the element isolating region261and having a high impurity concentration and is connected to the first semiconductor substrate120in order to use the reference potential in common. In addition, the first semiconductor substrate120is stacked on the back surface side of the second semiconductor substrate220. The column signal processing section550processes the generated image signal. This has an effect that the high impurity concentration region225connected to the first semiconductor substrate120is disposed in the element isolating region261in order to allow the reference potential to be used in common. This makes it possible to reduce the area of the second semiconductor substrate220.

The effects described in the present specification are merely examples, and thus, there may be other effects, not limited to the exemplified effects.

Note that the present technique can also have the following configurations.

(1) An imaging element comprising:a first semiconductor substrate including a photoelectric conversion section that performs photoelectric conversion of incident light; anda second semiconductor substrate that includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.
(2) The imaging element according to the above (1), further comprising a connecting location that connects the high impurity concentration region and the first semiconductor substrate to each other.
(3) The imaging element according to the above (2), wherein the high impurity concentration region is disposed in a well region of the second semiconductor substrate, and the connecting location connects the high impurity concentration region and the well region of the first semiconductor substrate to each other.
(4) The imaging element according to the above (2) or (2), wherein the connecting location is formed of silicon.
(5) The imaging element according to any one of the above (2) to (4), further comprising a second connecting location that is disposed on a front surface side of the second semiconductor substrate and supplies the reference potential.
(6) The imaging element according to the above (5), wherein the second connecting location is disposed in the element isolating region and connected to the high impurity concentration region.
(7) The imaging element according to the above (5), wherein the second connecting location is disposed adjacent to the element isolating region.
(8) The imaging element according to any one of the above (5) to (7), further comprising a third semiconductor substrate stacked on a front surface side of the second semiconductor substrate and connected to the second connecting location.
(9) The imaging element according to any one of the above (5) to (8), wherein the second connecting location is formed of metal.
(10) The imaging element according to any one of the above (5) to (8), wherein the second connecting location is formed of silicon.
(11) The imaging element according to any one of the above (1) to (10), wherein the high impurity concentration region has an impurity concentration of 5×1017cm−3or more.
(12) The imaging element according to any one of the above (1) to (11),wherein the first semiconductor substrate includes: a charge holding section that holds a charge generated by the photoelectric conversion; and a charge transfer section that transfers the charge from the photoelectric conversion section to the charge holding section, andthe pixel circuit generates an image signal according to the held charge.
(13) The imaging element according to any one of the above (1) to (12), further comprising a semiconductor region disposed in a layer same as a layer of the second semiconductor substrate.
(14) The imaging element according to the above (13), wherein a reference potential different from the reference potential is supplied to the semiconductor region.
(15) The imaging element according to the above (14),wherein the high impurity concentration region is disposed in a well region of the second semiconductor substrate, andthe semiconductor region is configured in a well region having a conductivity type different from a conductivity type of a well region of the second semiconductor substrate.
(16) The imaging element according to any one of the above (13) to (15), wherein a transistor that amplifies a signal based on a charge generated by the photoelectric conversion in the pixel circuit is disposed in the semiconductor region.
(17) The imaging element according to any one of the above (13) to (16), wherein a transistor that controls output of the image signal in the pixel circuit is disposed in the semiconductor region.
(18) An imaging device comprising:a first semiconductor substrate including a photoelectric conversion section that performs photoelectric conversion of incident light;a second semiconductor substrate that includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate; anda processing circuit that processes the generated image signal.

REFERENCE SIGNS LIST