Write latency and energy using asymmetric cell design

Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including improving write latency and energy using asymmetric cell design.

BACKGROUND

DETAILED DESCRIPTION

A memory device may include multiple memory arrays of memory cells (e.g., a partition including multiple memory tiles) and may perform programming operations (e.g., access operations, including write operations). That is, the memory device may apply a voltage (e.g., a write voltage) to the memory arrays via one or more access lines (e.g., a word line or a bit/digit line) to write a logic state, such as a first logic state or a second logic state, to one or more memory cells. The memory device may write a logic state to each memory cell based on characteristics of the applied voltage. For example, the memory device may write a first logic state to a memory cell by applying a positive voltage across the memory cell and may write a second logic state to a memory cell by applying a negative voltage across the memory cell.

Applying a voltage across the memory cell may set a threshold voltage state of the memory cell, such that the logic state may be determined based on whether an applied voltage exceeds a threshold voltage of the memory cell causing current to run through the memory cell. In some cases, this phenomenon may be described as a snap-back event or thresholding the memory cell. If the applied voltage induces a current through the memory cell, the memory device may determine that the memory cell is storing the second logic state. Additionally, if the applied voltage does not induce a current through the memory cell, the memory device may determine that the memory cell is storing a first logic state.

In some examples, the threshold voltage of one or more memory cells in the memory arrays may drift (e.g., increase or decrease) over time. For example, electrical characteristics of a memory cell (e.g., resistivity of the memory cell) may change after repeated programming operations are performed on the memory cell resulting in the drift in threshold voltage. In some cases, a memory device may be configured to “cancel” or “offset” drift that has occurred in any one memory cell. That is, the memory device may be configured to lower the threshold voltage of the memory cell having experienced drift. If a cell was previously programmed to a first logic state, it may have drifted over time. Accordingly, it may be difficult to program the memory cell to the second logic state. However, performing a drift cancellation operation may cancel the drift that occurred so that programming a second logic state to the memory cell will be successful. Additionally or alternatively, performing a drift cancellation operation may identify the logic states stored to certain memory cells. For example, if a cell does not snap when performing a drift cancellation operation then it may already be programmed to the desired state.

To cancel the drift of a memory cell (e.g., to lower its threshold voltage), the memory device may apply a voltage to the cell that corresponds to a logic state that was written to the cell during a prior programming operation. For example, if a first logic state was written during a prior programming operation (e.g., using a positive programming voltage), then a positive voltage may be applied to the cell to cancel or mitigate any drift that may have occurred.

In some instances, a logic state may be written to a memory cell after a drift cancellation operation. For example, a positive voltage may be applied to a memory cell to cancel drift that may have occurred and a negative voltage may then be applied to the memory cell during a write operation. The voltages applied to access lines may toggle one or more times between positive and negative for drift cancellation purposes and to perform programming operations. But the toggling of the word line may consume time and power, which may be undesirable.

In accordance with examples as disclosed herein, a memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget (RWB). For example, an asymmetric memory cell may be polarity biased, and may support programming operations for logic states based on the polarity bias. Implementing the asymmetric memory cells supporting the asymmetric RWB enables the memory device to use fewer programming pulses, which increases programming speed and decreases system latency. Additionally, the asymmetric cell design enables the memory device to use lower programming pulses, which reduces resource consumption during programming operations.

Features of the disclosure are initially described in the context of memory devices and arrays with reference toFIGS.1,2,3A, and3B. Features of the disclosure are described in the context improving write latency and energy using asymmetric cell design with reference toFIGS.4A,4B, and5A-5E. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to improving write latency and energy using asymmetric cell design as described with reference toFIGS.6-9.

FIG.1illustrates an example of a memory device100that supports improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. In some examples, the memory device100may be referred to as or include a memory die, a memory chip, or an electronic memory apparatus. The memory device100may be operable to provide locations to store information (e.g., physical memory addresses) that may be used by a system (e.g., a host device coupled with the memory device100, for writing information, for reading information).

The memory device100may include one or more memory cells105that each may be programmable to store different logic states (e.g., a programmed one of a set of two or more possible states). For example, a memory cell105may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell105(e.g., a multi-level memory cell105) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells105may be arranged in an array.

A memory cell105may store a logic state using a configurable material, which may be referred to as a memory element, a storage element, a memory storage element, a material element, a material memory element, a material portion, or a polarity-written material portion, among others. A configurable material of a memory cell105may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase change memory cell, a thresholding memory cell, or a self-selecting memory cell, among other architectures.

In some examples, the material of a memory cell105may include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (IN), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG-alloy. In some examples, a SAG-alloy may also include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some examples, SAG-alloy may include silicon (Si) or indium (In) or a combination thereof and such chalcogenide materials may be referred to as SiSAG-alloy or InSAG-alloy, respectively, or a combination thereof. In some examples, the chalcogenide material may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms.

In some examples, a memory cell105may be an example of a phase change memory cell. In such examples, the material used in the memory cell105may be based on an alloy (such as the alloys listed above) and may be operated so as to change to different physical state (e.g., undergo a phase change) during normal operation of the memory cell105. For example, a phase change memory cell105may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). A relatively disordered atomic configuration may correspond to a first logic state (e.g., a RESET state, a logic 0) and a relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different than the first logic state, a SET state, a logic 1).

In some examples (e.g., for thresholding memory cells105, for self-selecting memory cells105), some or all of the set of logic states supported by the memory cells105may be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., the material in an amorphous state may be operable to store different logic states). In some examples, the storage element of a memory cell105may be an example of a self-selecting storage element. In such examples, the material used in the memory cell105may be based on an alloy (e.g., such as the alloys listed above) and may be operated so as to undergo a change to a different physical state during normal operation of the memory cell105. For example, a self-selecting or thresholding memory cell105may have a high threshold voltage state and a low threshold voltage state. A high threshold voltage state may correspond to a first logic state (e.g., a RESET state, a logic 0) and a low threshold voltage state may correspond to a second logic state (e.g., a logic state different than the first logic state, a SET state, a logic 1).

During a write operation (e.g., a programming operation) of a self-selecting or thresholding memory cell105, a polarity used for a write operation may influence (e.g., determine, set, program) a behavior or characteristic of the material of the memory cell105, such as a thresholding characteristic (e.g., a threshold voltage) of the material. A difference between thresholding characteristics of the material of the memory cell105for different logic states stored by the material of the memory cell105(e.g., a difference between threshold voltages when the material is storing a logic state ‘0’ versus a logic state ‘1’) may correspond to the read window of the memory cell105.

The memory device100may include access lines (e.g., row lines115each extending along an illustrative x-direction, column lines125each extending along an illustrative y-direction) arranged in a pattern, such as a grid-like pattern. Access lines may be formed with one or more conductive materials. In some examples, row lines115, or some portion thereof, may be referred to as word lines. In some examples, column lines125, or some portion thereof, may be referred to as digit lines or bit lines. References to access lines, or their analogues, are interchangeable without loss of understanding. Memory cells105may be positioned at intersections of access lines, such as row lines115and the column lines125. In some examples, memory cells105may also be arranged (e.g., addressed) along an illustrative z-direction, such as in an implementation of sets of memory cells105being located at different levels (e.g., layers, decks, planes, tiers) along the illustrative z-direction. In some examples, a memory device100that includes memory cells105at different levels may be supported by a different configuration of access lines, decoders, and other supporting circuitry than shown.

Operations such as read operations and write operations may be performed on the memory cells105by activating access lines such as one or more of a row line115or a column line125, among other access lines associated with alternative configurations. For example, by activating a row line115and a column line125(e.g., applying a voltage to the row line115or the column line125), a memory cell105may be accessed in accordance with their intersection. An intersection of a row line115and a column line125, among other access lines, in various two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell105. In some examples, an access line may be a conductive line coupled with a memory cell105and may be used to perform access operations on the memory cell105. In some examples, the memory device100may perform operations responsive to commands, which may be issued by a host device coupled with the memory device100or may be generated by the memory device100(e.g., by a local memory controller150).

Accessing the memory cells105may be controlled through one or more decoders, such as a row decoder110or a column decoder120, among other examples. For example, a row decoder110may receive a row address from the local memory controller150and activate a row line115based on the received row address. A column decoder120may receive a column address from the local memory controller150and may activate a column line125based on the received column address.

The sense component130may be operable to detect a state (e.g., a material state, a resistance state, a threshold state) of a memory cell105and determine a logic state of the memory cell105based on the detected state. The sense component130may include one or more sense amplifiers to convert (e.g., amplify) a signal resulting from accessing the memory cell105(e.g., a signal of a column line125or other access line). The sense component130may compare a signal detected from the memory cell105to a reference135(e.g., a reference voltage, a reference charge, a reference current). The detected logic state of the memory cell105may be provided as an output of the sense component130(e.g., to an input/output component140), and may indicate the detected logic state to another component of the memory device100or to a host device coupled with the memory device100.

The local memory controller150may control the accessing of memory cells105through the various components (e.g., a row decoder110, a column decoder120, a sense component130, among other components). In some examples, one or more of a row decoder110, a column decoder120, and a sense component130may be co-located with the local memory controller150. The local memory controller150may be operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with the memory device100), translate the information into a signaling that can be used by the memory device100, perform one or more operations on the memory cells105and communicate data from the memory device100to a host device based on performing the one or more operations. The local memory controller150may generate row address signals and column address signals to activate access lines such as a target row line115and a target column line125. The local memory controller150also may generate and control various signals (e.g., voltages, currents) used during the operation of the memory device100. In general, the amplitude, the shape, or the duration of an applied signal discussed herein may be varied and may be different for the various operations discussed in operating the memory device100.

The local memory controller150may be operable to perform one or more access operations on one or more memory cells105of the memory device100. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller150in response to access commands (e.g., from a host device). The local memory controller150may be operable to perform other access operations not listed here or other operations related to the operating of the memory device100that are not directly related to accessing the memory cells105.

In accordance with examples as disclosed herein, the memory device100may implement a programming scheme that uses low programming pulses (e.g., pulses applied via the row lines115or the column lines125to program the memory cells105) based on an asymmetric design for the memory cells105. For example, the asymmetric memory cells105may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric RWB. For example, an asymmetric memory cell105may be polarity biased, supporting programming operations for logic states based on the polarity bias. Implementing the asymmetric memory cells105supporting the asymmetric RWB enables the memory device100to use fewer programming pulses, increasing programming speed and decreasing system latency. Additionally, the asymmetric cell design enable the memory device100to use lower programming pulses, reducing resource consumption during programming operations.

The memory device100may include any quantity of non-transitory computer readable media that support improving write latency and energy using asymmetric cell design. For example, a local memory controller150, a row decoder110, a column decoder120, a sense component130, or an input/output component140, or any combination thereof may include or may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the memory device100. For example, such instructions, if executed by the memory device100, may cause the memory device100to perform one or more associated functions as described herein.

FIGS.2,3A, and3Billustrate an example of a memory array200that supports improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The memory array200may be included in a memory device100, and illustrates an example of a three-dimensional arrangement of memory cells105that may be accessed by various conductive structures (e.g., access lines).FIG.2illustrates a top section view (e.g., SECTION A-A) of the memory array200relative to a cut plane A-A as shown inFIGS.3A and3B.FIG.3Aillustrates a side section view (e.g., SECTION B-B) of the memory array200relative to a cut plane B-B as shown inFIG.2.FIG.3Billustrates a side section view (e.g., SECTION C-C) of the memory array200relative to a cut plane C-C as shown inFIG.2. The section views may be examples of cross-sectional views of the memory array200with some aspects (e.g., dielectric structures) removed for clarity. Elements of the memory array200may be described relative to an x-direction, a y-direction, and a z-direction, as illustrated in each ofFIGS.2,3A, and3B. Although some elements included inFIGS.2,3A, and3Bare labeled with a numeric indicator, other corresponding elements are not labeled, although they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features. Further, although some quantities of repeated elements are shown in the illustrative example of memory array200, techniques in accordance with examples as described herein may be applicable to any quantity of such elements, or ratios of quantities between one repeated element and another.

In the example of memory array200, memory cells105and word lines205may be distributed along the z-direction according to levels230(e.g., decks, layers, planes, tiers, as illustrated inFIGS.3A and3B). In some examples, the z-direction may be orthogonal to a substrate (not shown) of the memory array200, which may be below the illustrated structures along the z-direction. Although the illustrative example of memory array200includes four levels230, a memory array200in accordance with examples as disclosed herein may include any quantity of one or more levels230(e.g., 64 levels, 128 levels) along the z-direction.

Each word line205may be an example of a portion of an access line that is formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, a word line205may be formed in a comb structure, including portions (e.g., projections, tines) extending along the y-direction through gaps (e.g., alternating gaps) between pillars220. For example, as illustrated, the memory array200, may include two word lines205per level230(e.g., according to odd word lines205-a-n1and even word lines205-a-n2for a given level, n), where such word lines205of the same level230may be described as being interleaved (e.g., with portions of an odd word line205-a-n1projecting along the y-direction between portions of an even word line205-a-n2, and vice versa). In some examples, an odd word line205(e.g., of a level230) may be associated with a first memory cell105on a first side (e.g., along the x-direction) of a given pillar220and an even word line (e.g., of the same level230) may be associated with a second memory cell105on a second side (e.g., along the x-direction, opposite the first memory cell105) of the given pillar220. Thus, in some examples, memory cells105of a given level230may be addressed (e.g., selected, activated) in accordance with an even word line205or an odd word line205.

Each pillar220may be an example of a portion of an access line (e.g., a conductive pillar portion) that is formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, the pillars220may be arranged in a two-dimensional array (e.g., in an xy-plane) having a first quantity of pillars220along a first direction (e.g., eight pillars along the x-direction, eight rows of pillars), and having a second quantity of pillars220along a second direction (e.g., five pillars along the y-direction, five columns of pillars). Although the illustrative example of memory array200includes a two-dimensional arrangement of eight pillars220along the x-direction and five pillars220along the y-direction, a memory array200in accordance with examples as disclosed herein may include any quantity of pillars220along the x-direction and any quantity of pillars220along the y-direction. Further, as illustrated, each pillar220may be coupled with a respective set of memory cells105(e.g., along the z-direction, one or more memory cells105for each level230). A pillar220may have a cross-sectional area in an xy-plane that extends along the z-direction. Although illustrated with a circular cross-sectional area in the xy-plane, a pillar220may be formed with a different shape, such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in an xy-plane.

The memory cells105each may include a chalcogenide material. In some examples, the memory cells105may be examples of thresholding memory cells. Each memory cell105may be accessed (e.g., addressed, selected) according to an intersection between a word line205(e.g., a level selection, which may include an even or odd selection within a level230) and a pillar220. For example, as illustrated, a selected memory cell105-aof the level230-a-3may be accessed according to an intersection between the pillar220-a-43and the word line205-a-32.

A memory cell105may be accessed (e.g., written to, read from) by applying an access bias (e.g., an access voltage, Vaccess, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, an access bias may be applied by biasing a selected word line205with a first voltage (e.g., Vaccess/2) and by biasing a selected pillar220with a second voltage (e.g., −Vaccess/2), which may have an opposite sign relative to the first voltage. Regarding the selected memory cell105-a, a corresponding access bias (e.g., the first voltage) may be applied to the word line205-a-32, while other unselected word lines205may be grounded (e.g., biased to 0V). In some examples, a word line bias may be provided by a word line driver (not shown) coupled with one or more of the word lines205.

To apply a corresponding access bias (e.g., the second voltage) to a pillar220, the pillars220may be configured to be selectively coupled with a sense line215(e.g., a digit line, a column line, an access line extending along the y-direction) via a respective transistor225coupled between (e.g., physically, electrically) the pillar220and the sense line215. In some examples, the transistors225may be vertical transistors (e.g., transistors having a channel along the z-direction, transistors having a semiconductor junction along the z-direction), which may be formed above the substrate of the memory array200using various techniques (e.g., thin film techniques). In some examples, a selected pillar220, a selected sense line215, or a combination thereof may be an example of a selected column line125described with reference toFIG.1(e.g., a bit line).

The transistors225(e.g., a channel portion of the transistors225) may be activated by gate lines210(e.g., activation lines, selection lines, a row line, an access line extending along the x-direction) coupled with respective gates of a set of the transistors225(e.g., a set along the x-direction). In other words, each of the pillars220may have a first end (e.g., towards the negative z-direction, a bottom end) configured for coupling with an access line (e.g., a sense line215). In some examples, the gate lines210, the transistors225, or both may be considered to be components of a row decoder110(e.g., as pillar decoder components). In some examples, the selection of (e.g., biasing of) pillars220, or sense lines215, or various combinations thereof, may be supported by a column decoder120, or a sense component130, or both.

To apply the corresponding access bias (e.g., −Vaccess/2) to the pillar220-a-43, the sense line215-a-4may be biased with the access bias, and the gate line210-a-3may be grounded (e.g., biased to 0V) or otherwise biased with an activation voltage. In an example where the transistors225are n-type transistors, the gate line210-a-3being biased with a voltage that is relatively higher than the sense line215-a-4may activate the transistor225-a(e.g., cause the transistor225-ato operate in a conducting state), thereby coupling the pillar220-a-43with the sense line215-a-4and biasing the pillar220-a-43with the associated access bias. However, the transistors225may include different channel types, or may be operated in accordance with different biasing schemes, to support various access operations.

In some examples, unselected pillars220of the memory array200may be electrically floating when the transistor225-ais activated, or may be coupled with another voltage source (e.g., grounded, via a high-resistance path, via a leakage path) to avoid a voltage drift of the pillars220. For example, a ground voltage being applied to the gate line210-a-3may not activate other transistors coupled with the gate line210-a-3, because the ground voltage of the gate line210-a-3may not be greater than the voltage of the other sense lines215(e.g., which may be biased with a ground voltage or may be floating). Further, other unselected gate lines210, including gate line210-a-5as shown inFIG.3A, may be biased with a voltage equal to or similar to an access bias (e.g., −Vaccess/2, or some other negative bias or bias relatively near the access bias voltage), such that transistors225along an unselected gate line210are not activated. Thus, the transistor225-bcoupled with the gate line210-a-5may be deactivated (e.g., operating in a non-conductive state), thereby isolating the voltage of the sense line215-a-4from the pillar220-a-45, among other pillars220.

In a write operation, a memory cell105may be written to by applying a write bias (e.g., where Vaccess=Vwrite, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, a polarity of a write bias may influence (e.g., determine, set, program) a behavior or characteristic of the material of the memory cell105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity may set the material of the memory cell105with a first threshold voltage, which may be associated with storing a logic 0. Further, applying a write bias with a second polarity (e.g., opposite the first polarity) may set the material of the memory cell with a second threshold voltage, which may be associated with storing a logic 1. A difference between threshold voltages of the material of the memory cell105for different logic states stored by the material of the memory cell105(e.g., a difference between threshold voltages when the material is storing a logic state ‘0’ versus a logic state ‘1’) may correspond to the read window of the memory cell105.

In a read operation, a memory cell105may be read from by applying a read bias (e.g., where Vaccess=Vread, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, a logic state of the memory cell105may be evaluated based on whether the memory cell105thresholds in the presence of the applied read bias. For example, such a read bias may cause a memory cell105storing a first logic state (e.g., a logic 1) to threshold (e.g., permit a current flow, permit a current above a threshold current), and may not cause a memory cell105storing a second logic state (e.g., a logic 0) to threshold (e.g., may not permit a current flow, may permit a current below a threshold current).

In some cases, the memory device100may include the array of memory cells105to store data for a host device. In some cases, the memory device100may perform a programming operation (e.g., a write operation) on the memory cells105based on a command from a host device. In such cases, the memory device may drive a voltage through an access line (e.g., such as word line205) coupled with a set of memory cells105to perform the programming operation on the set of memory cells105. In some examples, the voltage may be compared to a threshold voltage of a memory cell105to determine a logic state of the memory cell105. However, in such examples, the threshold voltage may “drift” (e.g., shift) after repeated programming voltages are applied to the memory cell105or a duration elapses at the memory cell105. Drift may negatively affect the memory device's ability to accurately perform programming operations on the memory cell105. Therefore, drift cancellation procedures may be implemented on a memory array to prevent the effects of drift.

In accordance with examples as disclosed herein, the memory array200may implement a programming scheme that uses low programming pulses (e.g., pulses applied via access lines to program the memory cells105) based on an asymmetric design for the memory cells105. For example, the asymmetric memory cells105may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric RWB. For example, an asymmetric memory cell105may be polarity biased, supporting programming operations for logic states based on the polarity bias. Implementing the asymmetric memory cells105supporting the asymmetric RWB enables the memory array200to use fewer programming pulses, increasing programming speed and decreasing system latency. Additionally, the asymmetric cell design enable the memory array200to use lower programming pulses, reducing resource consumption during programming operations.

FIGS.4A and4Billustrate examples of programming diagrams400that support improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The programming diagram400-amay illustrate voltages associated with a programming operation performed on asymmetric memory cells as described with reference toFIGS.2,3A, and3B. Additionally, the programming diagram400-amay implement aspects of the memory device100as described with reference toFIG.1.

The programming diagram400-amay be an example diagram of threshold voltages used to determine logic states stored in the memory cells. A horizontal axis of the programming diagram400-amay indicate a voltage applied to the memory cells during a programming operation, and a vertical axis may represent a quantile of distribution (e.g., a percentage) based on the applied voltage. Further, a voltage405may symbolize a zero voltage (e.g., no voltage applied to the memory cells). In some implementations, a selection voltage410-a(e.g., a positive selection voltage, which may be referred to as +Vsel_dc) may be an example of a first voltage (e.g., a first programming pulse) applied to the asymmetric memory cells, and a selection voltage410-b(e.g., a negative selection voltage, which may be referred to as −Vsel_dc) may be an example of a second voltage (e.g., a second programming pulse) applied to the asymmetric memory cells to cancel drift and to write logic states to the asymmetric memory cells during a programming operation.

The programming diagram400-ais an example programming operation scheme for one or more asymmetric memory cells that have an improved RWB for voltages with a negative polarity (e.g., a read bias may be negative). However, the programming diagram400-amay be different in the case of a programming operation performed on one or more asymmetric memory cells that have an improved RWB for voltages with a positive polarity (e.g., a read bias may be positive). The one or more asymmetric memory cells may be negatively or positively biased based at least in part on the asymmetry in the design of the asymmetric memory cells. For example, the asymmetric memory cells may be designed with a preferred polarity for the RWB based on the manufacturing process used to form the asymmetric memory cells.

In some examples, threshold voltages415and420-bmay be used to determine a first logic state (e.g., “0”) stored in the asymmetric memory cells. Similarly, threshold voltages425and430-amay be used to determine a second logic state (e.g., “1”) stored in the asymmetric memory cells. Further, the threshold voltages420-aand430-amay be used after accounting for voltage drift at the asymmetric memory cells. In some implementations, threshold voltages420-band430-bmay be used to determine the logic states associated with the threshold voltages420-aand430-aprior to drift cancellation.

The programming operation may drive one or more asymmetric memory cells at least to a threshold voltage to program the logic state at the asymmetric memory cells. For example, to program the first logic state at the one or more asymmetric memory cells, the memory device may apply a voltage greater in magnitude than the threshold voltage415to the asymmetric memory cells, such as the selection voltage410-a. Similarly, to program the second logic state at the one or more asymmetric memory cells, the memory device may apply a voltage greater in magnitude than the threshold voltage425to the asymmetric memory cells, such as the selection voltage410-b.

The programming diagram400-amay differ from other different programming operations due to the asymmetric design of the memory cells. For example, in the programming diagram400-a, the threshold voltages430-aand430-beach have a magnitude less than the magnitude of the threshold voltage415. That is, the memory device may perform program operations without canceling the drift from the threshold voltage430-bto the threshold voltage430-a. Accordingly, the programming diagram400-amay have advantages over other different programming operations by having a shorter write completion time, lower resource requirements, and fewer pulses and polarity flips.

As illustrated inFIG.4Bthe programming diagram400-bmay implement aspects of the programming diagram400-a, such as the zero voltage405and the selection voltages410-aand410-bdescribed with reference toFIG.4A. The programming diagram400-bmay represent a timing associated with applying the voltages to one or more asymmetric memory cells of a set of asymmetric memory cells as demonstrated in the programming diagram400-a. The horizontal axis of the programming diagram400-bmay represent time and the vertical axis may represent the voltage applied to the one or more asymmetric memory cells. A logic state may be programmed to the asymmetric memory cells and remain until another voltage is applied (e.g., a programming pulse).

Prior to a time t1, the memory device may receive a command to write the first logic state (e.g., “0”) to a first subset of the set of memory cells and the second logic state (e.g., “1”) to a second subset of the set of memory cells. Prior to the time t1, the memory device may not apply a voltage to the set of asymmetric memory cells, and the logic state stored in each of the set of asymmetric memory cells may be based on a prior logic state programmed to each asymmetric memory cell.

At the time t1, the memory device may apply the positive selection voltage410-ato the set of asymmetric memory cells. Applying the selection voltage410-afor a duration435-abetween the time t1and a time t2may program the logic state of the asymmetric memory cells to the first logic state. That is, applying the selection voltage410-amay write the first logic state to memory cells of the first subset of the set of asymmetric memory cells. Applying the selection voltage410-amay additionally cancel a drift in one or more asymmetric memory cells of the second subset. For example, the one or more asymmetric memory cells of the second subset may store the first logic state, and applying the selection voltage410-amay refresh the first logic state stored in the one or more asymmetric memory cells.

At the time t2, the memory device may apply the negative selection voltage410-bto the second subset of the set of asymmetric memory cells. That is, at the time t2, a polarity of the applied voltage may flip. Applying the selection voltage410-bfor a duration435-bbetween the time t2and a time t3may write the second logic state to memory cells of the second subset of the set of asymmetric memory cells. The duration435-bmay be equal to or different than the duration435-a. In some examples, a sum of the durations435-aand435-bmay be less than a sum of three durations used to cancel a drift and program a set of memory cells that do not include the asymmetric design.

At the time t3, the memory device may cease applying a voltage to the set of asymmetric memory cells. That is, after the time t3, the zero voltage405may be applied to the asymmetric memory cells, for example, until another command is received to initiate a subsequent programming operation.

FIG.5A through5Eillustrate examples of processing steps500that support improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The processing steps illustrate various cross-sectional views of materials on a substrate505. The processing steps500may implement aspects of the memory device100as described with reference toFIG.1.

InFIG.5A, processing step500-ais depicted and includes a cross-sectional view of the memory architecture of a memory device before memory cell deposition. In the processing step500-a, a stack510of materials may be formed on the substrate505. The stack510may include a first dielectric material515and a first conductive material520in alternating layers. The first conductive material520may include carbon, tungsten, or a combination thereof. In some examples, the layers of the first conductive material520may be directly deposited in alternating layers with the first dielectric material515. Additionally, or alternatively, alternating layers of the first dielectric material515and an insulating material (e.g., nitride) may be deposited, and the insulating material may be removed (e.g., etched, exhumed) to form voids in which the first conductive material520may be deposited to form the stack510.

Any quantity of dielectric and conductive layers may be layered based on a desired height of the vertical stack of memory cells. The stack510of materials (e.g., first dielectric material515and first conductive material520) may be etched to form a cavity525and, in some examples, expose a surface506of the substrate505in the cavity525. In some cases, the substrate505may be etched to form the cavity525and a selector device507(e.g., a thin film transistor) may be deposited into the cavity525. Portions of the first conductive material520may be etched to form recesses530between the alternating layers of the first dielectric material515. In some cases, the etched portions of the first conductive material520may form a set of first electrodes in the recesses530. In some cases, the first electrodes may have a first contact area521and may be coupled with a first access line decoder.

InFIG.5B, processing step500-bis depicted and includes a cross-sectional view of the memory architecture of the memory device. In the processing step500-b, a storage material535may be deposited into the recesses530to form storage elements. In some cases, the storage material535may be a chalcogenide material. In some cases, the storage material535may be deposited into the recesses530such that a portion of the recesses530remains unfilled. For example, an outer surface of the storage material535may not be coplanar with an outer surface of the first dielectric material515. Additionally or alternatively, the storage material535may be deposited into the recesses530and additional storage material535may be deposited on the surrounding dielectric material515above and below the recesses530, as shown in the cross sectional view ofFIG.5B. In some cases, the storage elements may be coupled with the first electrodes. In some examples, the storage material535may be conformally deposited such that a thickness of the storage material535on each sidewall surrounding the recesses530(including the sidewall coupled with the first electrode) is substantially the same.

InFIG.5C, processing step500-cis depicted and includes a cross-sectional view of the memory architecture of the memory device. In the processing step500-c, a second conductive material540may be deposited into the recesses530to form a set of second electrodes. The second conductive material540may include carbon, tungsten, or a combination thereof. In some cases, each second electrode may have a second contact area541with different dimensions (e.g., a different width in a first direction, a different height in a second direction, or both) than the first contact area521of the first electrode. In some cases, the second conductive material540may be deposited to fill the recesses530. In some examples, additional second conductive material540may be deposited on the surrounding dielectric material515, such that a surface of the conductive material540may be coplanar with the outer surface of the dielectric material515. In some examples, the additional second conductive material540may be deposited on the additional storage material535deposited on the surrounding dielectric material515, as shown in the cross sectional view ofFIG.5C.

InFIG.5D, processing step500-dis depicted and includes a cross-sectional view of the memory architecture of the memory device. In the processing step500-d, the second conductive material540and the storage material535may be etched to reform the cavity525. In some examples, etching the second conductive material540and the storage material535may expose portions of the dielectric material515, the second conductive material540, or the storage material535. In some cases, the outer surfaces of the dielectric material515, the second conductive material540, and the storage material535may be coplanar, as shown in the cross-sectional view ofFIG.5D.

InFIG.5E, processing step500-eis depicted and includes a cross-sectional view of the memory architecture of the memory device. In the processing step500-e, the second conductive material540may be deposited in the reformed cavity525. In some cases, depositing the second conductive material540in the reformed cavity525may include depositing the second conductive material540on the outer surfaces of the dielectric material515, the second conductive material540, and the storage material535. Additionally, in the processing step500-e, a third conductive material545(e.g., carbon, tungsten, or both) may be deposited on the second conductive material540deposited in the processing step500-e, as shown in the cross-sectional view ofFIG.5E. In some cases, the third conductive material545may be coupled with a second access line decoder.

FIG.6shows a block diagram600of a memory device620that supports improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The memory device620may be an example of aspects of a memory device as described with reference toFIGS.1through5. The memory device620, or various components thereof, may be an example of means for performing various aspects of improving write latency and energy using asymmetric cell design as described herein. For example, the memory device620may include a reception component625, a programming component630, a thresholding component635, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The reception component625may be configured as or otherwise support a means for receiving, at a memory device, a command to write a first logic state to a first subset of a set of memory cells and a second logic state to a second subset of the set of memory cells, where each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. The programming component630may be configured as or otherwise support a means for applying, during a first duration and in response to the command, a first voltage to the first access line, where, during the first duration, at least one memory cell of the second subset thresholds and at least one memory cell of the first subset is written to the first logic state based at least in part on applying the first voltage to the first access line, the thresholding based at least in part on the second contact area being different than the first contact area. In some examples, the programming component630may be configured as or otherwise support a means for applying, during a second duration after the first duration and in response to the command, a second voltage to the first access line, where, during the second duration, the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the second voltage to the first access line.

In some examples, the programming component630may be configured as or otherwise support a means for applying, during the first duration, a third voltage to a second access line coupled with the at least one memory cell of the first subset, where the at least one memory cell of the first subset is written to the first logic state based at least in part on applying the third voltage to the second access line.

In some examples, the programming component630may be configured as or otherwise support a means for applying, during the first duration, the third voltage to a second access line coupled with the at least one memory cell of the second subset, where the at least one memory cell of the second subset thresholds based at least in part on applying the third voltage to the second access line coupled with the at least one memory cell of the second subset.

In some examples, the programming component630may be configured as or otherwise support a means for applying, during the second duration after the first duration, a fourth voltage to a second access line coupled with the at least one memory cell of the second subset, where the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the fourth voltage to the second access line.

In some examples, the third voltage has a first polarity and the fourth voltage has a second polarity different than the first polarity.

In some examples, during the first duration, the at least one memory cell of the second subset thresholds based at least in part on a prior logic state written to the at least one memory cell of the second subset.

In some examples, the first voltage has a first polarity and the second voltage has a second polarity different than the first polarity.

In some examples, a magnitude of the first voltage and a magnitude of the second voltage have a same magnitude.

In some examples, a first magnitude of a first threshold voltage associated with the first logic state is different than a second magnitude of a second threshold voltage associated with the second logic state based at least in part on the second contact area being different than the first contact area.

In some examples, the second magnitude is less than the first magnitude.

In some examples, a magnitude of the first voltage is greater than the second magnitude. In some examples, a magnitude of the second voltage is less than the first magnitude.

In some examples, each memory cell of the set of memory cells includes a chalcogenide material.

In some examples, the programming component630may be configured as or otherwise support a means for writing, during a first portion of an access operation, a first logic state to memory cells of a first subset of a set of memory cells, where each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. The thresholding component635may be configured as or otherwise support a means for thresholding, during the first portion of an access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area. In some examples, the programming component630may be configured as or otherwise support a means for writing, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding.

In some examples, the writing the first logic state to the memory cells of the first subset and, to support thresholding the memory cells of the second subset, the programming component630may be configured as or otherwise support a means for applying a first programming pulse to the set of memory cells during the first portion of the access operation, where the first programming pulse has a first polarity.

In some examples, the first programming pulse is applied to the first access line.

In some examples, to support writing the second logic state to the memory cells of the second subset, the programming component630may be configured as or otherwise support a means for applying a second programming pulse to the set of memory cells during the second portion of the access operation, where the second programming pulse has a second polarity that is different than the first polarity.

In some examples, the second programming pulse is applied to the first access line.

In some examples, the thresholding is further based at least in part on a logic state written to the memory cells of the second subset during a prior access operation.

In some examples, each memory cell of the set of memory cells includes a chalcogenide material.

FIG.7shows a flowchart illustrating a method700that supports improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The operations of method700may be implemented by a memory device or its components as described herein. For example, the operations of method700may be performed by a memory device as described with reference toFIGS.1through6. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware.

At705, the method may include receiving, at a memory device, a command to write a first logic state to a first subset of a set of memory cells and a second logic state to a second subset of the set of memory cells, where each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. The operations of705may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of705may be performed by a reception component625as described with reference toFIG.6.

At710, the method may include applying, during a first duration and in response to the command, a first voltage to the first access line, where, during the first duration, at least one memory cell of the second subset thresholds and at least one memory cell of the first subset is written to the first logic state based at least in part on applying the first voltage to the first access line, the thresholding based at least in part on the second contact area being different than the first contact area. The operations of710may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of710may be performed by a programming component630as described with reference toFIG.6.

At715, the method may include applying, during a second duration after the first duration and in response to the command, a second voltage to the first access line, where, during the second duration, the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the second voltage to the first access line. The operations of715may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of715may be performed by a programming component630as described with reference toFIG.6.

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving, at a memory device, a command to write a first logic state to a first subset of a set of memory cells and a second logic state to a second subset of the set of memory cells, where each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area; applying, during a first duration and in response to the command, a first voltage to the first access line, where, during the first duration, at least one memory cell of the second subset thresholds and at least one memory cell of the first subset is written to the first logic state based at least in part on applying the first voltage to the first access line, the thresholding based at least in part on the second contact area being different than the first contact area; and applying, during a second duration after the first duration and in response to the command, a second voltage to the first access line, where, during the second duration, the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the second voltage to the first access line.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying, during the first duration, a third voltage to a second access line coupled with the at least one memory cell of the first subset, where the at least one memory cell of the first subset is written to the first logic state based at least in part on applying the third voltage to the second access line.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying, during the first duration, the third voltage to a second access line coupled with the at least one memory cell of the second subset, wherein the at least one memory cell of the second subset thresholds based at least in part on applying the third voltage to the second access line coupled with the at least one memory cell of the second subset.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying, during the second duration after the first duration, a fourth voltage to a second access line coupled with the at least one memory cell of the second subset, where the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the fourth voltage to the second access line.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 4 where the third voltage has a first polarity and the fourth voltage has a second polarity different than the first polarity.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5 where during the first duration, the at least one memory cell of the second subset thresholds based at least in part on a prior logic state written to the at least one memory cell of the second subset.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6 where the first voltage has a first polarity and the second voltage has a second polarity different than the first polarity.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7 where a magnitude of the first voltage and a magnitude of the second voltage have a same magnitude.

Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 8 where a first magnitude of a first threshold voltage associated with the first logic state is different than a second magnitude of a second threshold voltage associated with the second logic state based at least in part on the second contact area being different than the first contact area.

Aspect 10: The method, apparatus, or non-transitory computer-readable medium of aspect 9 where the second magnitude is less than the first magnitude.

Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 9 through 10 where a magnitude of the first voltage is greater than the second magnitude and a magnitude of the second voltage is less than the first magnitude.

Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 11 where each memory cell of the set of memory cells includes a chalcogenide material.

FIG.8shows a flowchart illustrating a method800that supports improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The operations of method800may be implemented by a memory device or its components as described herein. For example, the operations of method800may be performed by a memory device as described with reference toFIGS.1through6. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware.

At805, the method may include writing, during a first portion of an access operation, a first logic state to memory cells of a first subset of a set of memory cells, where each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. The operations of805may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of805may be performed by a programming component630as described with reference toFIG.6.

At810, the method may include thresholding, during the first portion of an access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area. The operations of810may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of810may be performed by a thresholding component635as described with reference toFIG.6.

At815, the method may include writing, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding. The operations of815may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of815may be performed by a programming component630as described with reference toFIG.6.

Aspect 13: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for writing, during a first portion of an access operation, a first logic state to memory cells of a first subset of a set of memory cells, where each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area; thresholding, during the first portion of an access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area; and writing, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding.

Aspect 14: The method, apparatus, or non-transitory computer-readable medium of aspect 13 where the writing the first logic state to the memory cells of the first subset, and the thresholding the memory cells of the second subset includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying a first programming pulse to the set of memory cells during the first portion of the access operation, where the first programming pulse has a first polarity.

Aspect 15: The method, apparatus, or non-transitory computer-readable medium of aspect 14 where the first programming pulse is applied to the first access line.

Aspect 16: The method, apparatus, or non-transitory computer-readable medium of any of aspects 14 through 15 where the writing the second logic state to the memory cells of the second subset includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for applying a second programming pulse to the set of memory cells during the second portion of the access operation, where the second programming pulse has a second polarity that is different than the first polarity.

Aspect 17: The method, apparatus, or non-transitory computer-readable medium of aspect 16 where the second programming pulse is applied to the first access line.

Aspect 18: The method, apparatus, or non-transitory computer-readable medium of any of aspects 13 through 17 where the thresholding is further based at least in part on a logic state written to the memory cells of the second subset during a prior access operation.

Aspect 19: The method, apparatus, or non-transitory computer-readable medium of any of aspects 13 through 18 where each memory cell of the set of memory cells includes a chalcogenide material.

FIG.9shows a flowchart illustrating a method900that supports improving write latency and energy using asymmetric cell design in accordance with examples as disclosed herein. The operations of method900may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At905, the method may include forming a substrate. The operations of905may be performed in accordance with examples as disclosed herein.

At910, the method may include forming a stack of materials over the substrate, the stack of materials including a dielectric material and a first conductive material in alternating layers. The operations of910may be performed in accordance with examples as described herein.

At915, the method may include etching the stack of materials to form a set of cavities. The operations of915may be performed in accordance with examples as described herein.

At920, the method may include etching portions of the first conductive material to form a plurality of first electrodes in recesses between the alternating layers of the dielectric material, each first electrode of the plurality of first electrodes having a first contact area and including the first conductive material, where the plurality of first electrodes are coupled with a first access line decoder. The operations of920may be performed in accordance with examples as described herein.

At925, the method may include depositing a storage material in the set of cavities and the recesses to form a plurality of storage elements, each storage element of the plurality of storage elements coupled with a first electrode of the plurality of first electrodes. The operations of925may be performed in accordance with examples as described herein.

At930, the method may include depositing a second conductive material in the set of cavities and the recesses to form a plurality of second electrodes, each second electrode of the plurality of second electrodes having a second contact area different than the first contact area. The operations of930may be performed in accordance with examples as described herein.

In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:

Aspect 20: A method or apparatus including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a substrate; forming a stack of materials over the substrate, the stack of materials including a dielectric material and a first conductive material in alternating layers; etching the stack of materials to form a set of cavities; etching portions of the first conductive material to form a plurality of first electrodes in recesses between the alternating layers of the dielectric material, each first electrode of the plurality of first electrodes having a first contact area and including the first conductive material, where the plurality of first electrodes are coupled with a first access line decoder; depositing a storage material in the set of cavities and the recesses to form a plurality of storage elements, each storage element of the plurality of storage elements coupled with a first electrode of the plurality of first electrodes; and depositing a second conductive material in the set of cavities and the recesses to form a plurality of second electrodes, each second electrode of the plurality of second electrodes having a second contact area different than the first contact area.

Aspect 21: The method or apparatus of aspect 20, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching the second conductive material and the chalcogenide material to reform the set of cavities and depositing the second conductive material and a third conductive material in the set of cavities, the third conductive material coupled with a second access line decoder.

Aspect 22: The method or apparatus of any of aspects 20 through 21 where the first conductive material includes carbon, tungsten, or both and the second conductive material includes carbon, tungsten, or both.

Aspect 23: The method or apparatus of any of aspects 20 through 22 where the storage material includes a chalcogenide material.

Aspect 24: An apparatus, including: a set of memory cells; a first access line, where each memory cell of the set of memory cells is coupled with the first access line via a first electrode having a first contact area; a set of second access lines, where each memory cell of the set of memory cells is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area; and a controller coupled with the first access line and the set of second access lines, the controller configured to cause the apparatus to: receive a command to write a first logic state to a first subset of the set of memory cells and a second logic state to a second subset of the set of memory cells; apply, during a first duration and in response to the command, a first voltage to the first access line, where, during the first duration, at least one memory cell of the second subset thresholds and at least one memory cell of the first subset is written to the first logic state based at least in part on applying the first voltage to the first access line, the thresholding based at least in part on the second contact area being different than the first contact area; and apply, during a second duration after the first duration and in response to the command, a second voltage to the first access line, where, during the second duration, the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the second voltage to the first access line.

Aspect 25: The apparatus of aspect 24, where the controller is further configured to cause the apparatus to: apply, during the first duration, a third voltage to a second access line coupled with the at least one memory cell of the first subset, where the at least one memory cell of the first subset is written to the first logic state based at least in part on applying the third voltage to the second access line.

Aspect 26: The apparatus of aspect 25, where the controller is further configured to cause the apparatus to: apply, during the first duration, the third voltage to a second access line coupled with the at least one memory cell of the second subset, wherein the at least one memory cell of the second subset thresholds based at least in part on applying the third voltage to the second access line coupled with the at least one memory cell of the second subset.

Aspect 27: The apparatus of aspect 25, where the controller is further configured to cause the apparatus to: apply, during the second duration after the first duration, a fourth voltage to a second access line coupled with the at least one memory cell of the second subset, where the at least one memory cell of the second subset is written to the second logic state based at least in part on applying the fourth voltage to the second access line.

Aspect 28: The apparatus of aspect 27, where the third voltage has a first polarity and the fourth voltage has a second polarity different than the first polarity.

Aspect 29: The apparatus of any of aspects 24 through 28, where during the first duration, the at least one memory cell of the second subset thresholds based at least in part on a prior logic state written to the at least one memory cell of the second subset.

Aspect 30: The apparatus of any of aspects 24 through 29, where the first voltage has a first polarity and the second voltage has a second polarity different than the first polarity.

Aspect 31: The apparatus of any of aspects 24 through 30, where a magnitude of the first voltage and a magnitude of the second voltage include a same magnitude.

Aspect 32: The apparatus of any of aspects 24 through 31, where first magnitude of a first threshold voltage associated with the first logic state is different than a second magnitude of a second threshold voltage associated with the second logic state based at least in part on the second contact area being different than the first contact area.

Aspect 33: The apparatus of aspect 32, where the second magnitude is less than the first magnitude.

Aspect 34: The apparatus of any of aspects 32 through 33, where: a magnitude of the first voltage is greater than the second magnitude; and a magnitude of the second voltage is less than the first magnitude.

Aspect 35: The apparatus of any of aspects 24 through 34, where each memory cell of the set of memory cells includes a chalcogenide material.

Aspect 36: An apparatus, including: a set of memory cells; a first access line, where each memory cell of the set of memory cells is coupled with the first access line via a first electrode having a first contact area; a set of second access lines, where each memory cell of the set of memory cells is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area; and a controller coupled with the first access line and the set of second access lines, the controller configured to cause the apparatus to: write, during a first portion of an access operation, a first logic state to memory cells of a first subset of the set of memory cells; threshold, during the first portion of an access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area; and write, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding.

Aspect 37: The apparatus of aspect 36, where, to write the first logic state to the memory cells of the first subset and to threshold the memory cells of the second subset, the controller is further configured to cause the apparatus to: apply a first programming pulse to the set of memory cells during the first portion of the access operation, where the first programming pulse has a first polarity.

Aspect 38: The apparatus of aspect 37, where the first programming pulse is applied to the first access line.

Aspect 39: The apparatus of any of aspects 37 through 38, where, to write the second logic state to the memory cells of the second subset, the controller is further configured to cause the apparatus to: apply a second programming pulse to the set of memory cells during the second portion of the access operation, where the second programming pulse has a second polarity that is different than the first polarity.

Aspect 40: The apparatus of aspect 39, where the second programming pulse is applied to the first access line.

Aspect 41: The apparatus of any of aspects 36 through 40, where the thresholding is further based at least in part on a logic state written to the memory cells of the second subset during a prior access operation.

Aspect 42: The apparatus of any of aspects 36 through 41, where each memory cell of the set of memory cells includes a chalcogenide material.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels.