Adaptively controlled duty cycle clock generation circuit

A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

FIELD OF THE DISCLOSURE

This document pertains generally, but not by way of limitation, to the field of analog-to-digital converters and, in particular, to clock generation in ADCs.

BACKGROUND

Analog-to-digital converters (ADCs) are used to convert an unknown input voltage into a digital representation. Most ADCs work discretely. Among the discrete time ADCs, the pipeline ADCs and Delta-Sigma ADCs operate in a time division configuration including a sampling phase and an integration phase.

During the sampling phase, the integrator in the ADC will sample the input voltage. During the integrating phase, the ADC integrates or amplifies and then compares the result with a reference voltage. The unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period. Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero. The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period.

The sampling time and integrating time for the integrator circuit are controlled by two non-overlapping clocks. The clock source is typically from a local oscillator having a fixed 50% duty cycle. While the pulse widths of the two clocks are the same, the time constants of the sampling phase clock and the integrating phase clock are not the same. The integrating phase typically has a larger time constant since it is determined by the input transconductance of an amplifier of the integrator and the integrating capacitance. The input transconductance is limited and the time constant of the sampling phase is determined by a sampling switch resistance and sampling capacitance. The resistance is usually relatively small.

In designing the amplifier for the integrator, the time constant should be 1/N of the pulse width of the integrating phase. Such a time constant enables the settling accuracy to be N*τ where τ is the time constant and the settling accuracy of N*τ means an accuracy of e−N. If N=7, the settling accuracy is 0.09%. However, since the amplifier has process limitations in slow skew, the transconductance of the amplifier is smaller than a typical value. Thus, the time constant turns out to be larger than 1/N of the pulse width and the settling accuracy is reduced. The amplifier current may be increased to compensate for the inaccuracy but then the ADC power usage also increases.

SUMMARY OF THE DISCLOSURE

The present inventors have recognized, among other things, a need for improved total harmonic distortion performance over ADC fabrication process variations. For example, a clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

One embodiment is for a clock generation circuit that generates an adaptively controlled duty cycle output clock for an analog-to-digital converter having integrator amplifiers. The clock generation circuit includes an adaptive duty cycle control circuit to generate the adaptively controlled duty cycle output clock signal from an input clock having a duty cycle. A non-overlapping clock generation circuit is coupled to the adaptive duty cycle control circuit, the non-overlapping clock generation circuit is configured to generate a plurality of non-overlapping clocks where the duty cycle of the plurality of output clocks is controlled by the adaptively controlled duty cycle output clock signal. The adaptive duty cycle control circuit includes a current generator circuit including an amplifier, a transistor, and a resistance coupled in series, wherein the resistance is determined based on an input transconductance of the integrator amplifier. Another circuit including a transistor and capacitance coupled in series. The circuit is coupled in parallel with the current generator circuit, where the transistor is configured to act as a current mirror and the duty cycle of the input clock is adaptively controlled based on a product of the resistance and the capacitance and the product is proportional to a settling time of the integrator.

Another embodiment for an analog-to-digital converter. The converter includes a plurality of integrator circuits, each circuit comprising an input amplifier configured to have an input current. A clock generation circuit is coupled to the plurality of integrator circuits and configured to generate an adaptively controlled duty cycle output clock signal based on an input clock. The clock generation circuit comprises a current generator circuit including an amplifier, a transistor, and a resistance coupled in series, wherein the resistance is adjusted based on an input transconductance of the integrator amplifier. Another circuit includes a transistor and capacitance coupled in series and an amplifier having a reference voltage coupled to a first input and a second input coupled to a common node between the transistor and capacitance. The circuit is coupled in parallel with the current generator circuit, wherein the transistor is configured to act as a current mirror and the duty cycle of the input clock is adaptively controlled based on a product of the resistance and the capacitance and the product is proportional to a settling time of the integrator wherein the amplifier outputs the adaptively controlled duty cycle output clock signal to the integrator circuit. A transconductance bias circuit is coupled to the clock generation circuit. The transconductance bias circuit is configured to adjust the resistance based on the input current.

Another embodiment includes a method for generating an adaptively controlled duty cycle output clock for an analog-to-digital converter with an integrator amplifier. The method generates an input current in the integrator amplifier. The input current is compared to a current mirror current comprising a resistance. The resistance is adjusted until the input current is equal to the current mirror current. The adaptively controlled duty cycle output clock is generated based on a time constant of the adjusted resistance and a capacitance, wherein the time constant is proportional to a settling time of the integrator amplifier.

DETAILED DESCRIPTION

Integrator circuits in discrete time ADCs typically use non-overlapping clocks as sampling and integrating clock to perform the analog-to-digital conversion. The clock source is typically from a local oscillator which has a fixed 50% duty cycle and the clock is input to a non-overlapping clock generator to generate both the sampling clock and the integrating clock. A time constant of the amplifier circuit of the integrator ideally is 1/N of the pulse width of the integrating phase. Due to amplifier process limitations, the transconductance of the amplifier is smaller than a typical value. Thus, the time constant turns out to be larger than 1/N of the pulse width and the settling accuracy is reduced. These problems may be illustrated by reference toFIGS. 1-3as described subsequently.

FIG. 1is a schematic diagram of a differential integrator circuit100, such as in accordance with various embodiments. The circuit100comprises a differential amplifier101, a plurality of switches102-111, two sampling capacitors130,131, and two feedback capacitors140,141.

Three of the input switches104-106are coupled to a positive voltage sampling capacitor130. An input positive reference voltage Vrefpnode is coupled to a first input switch104. An input negative reference voltage Vrefnnode is coupled to a second input switch105. A positive input voltage Vipnode, coupled to be the input voltage to be sampled, is coupled to a third input switch106.

Another three of the input switches107-109are coupled to a negative voltage sampling capacitor131. The input positive reference voltage Vrefpnode is coupled to a fourth input switch109. The input negative reference voltage Vrefnnode is coupled to a fifth input switch108. A negative input voltage Vinnode, coupled to be the input voltage to be sampled, is coupled to a sixth input switch107.

The positive voltage sampling capacitor130is coupled to one side of a sampling phase switch103and an integration phase switch102. The other side of the integration phase switch102is coupled to an input (e.g., negative input) of the amplifier101and feedback capacitor140. The other side of the sampling phase switch103is coupled to a common mode voltage VCM(e.g., circuit virtual ground).

Similarly, the negative voltage sampling capacitor131is coupled to one side of a sampling phase switch111and an integration phase switch110. The other side of the integration phase switch110is coupled to an input (e.g., positive input) of the amplifier101and feedback capacitor141. The other side of the sampling phase switch111is coupled to a common mode voltage VCM(e.g., circuit virtual ground).

FIGS. 2 and 3illustrate the operation of the circuit ofFIG. 1in a single ended mode. When the sampling phase switches103,111are closed, the voltages from the input nodes Vip, Vinare coupled to their respective sampling capacitors130,131to charge the capacitors130,131. This circuit is illustrated inFIG. 2.

FIG. 2is a schematic diagram of the integrator circuit in a sampling phase, such as in accordance with the embodiment ofFIG. 1. For purposes of brevity and clarity, this circuit illustrates only the positive sampling portion ofFIG. 1. However, the negative sampling portion ofFIG. 1operates in a substantially similar manner.

This circuit shows that the positive input voltage Vipnode switch106is closed to connect the Vipvoltage to its respective sampling capacitor130. The input reference voltage node switches104,105are open so that those nodes are not connected to anything. The input voltage Vipmay then be able to charge the sampling capacitor130. The sampling phase switch103is closed to connect the other side of the sampling capacitor130to the common mode voltage (e.g., virtual ground). The integrator phase switch102is open to disconnect the amplifier101from the sampling capacitor130and, thus, produce an input capacitance200to the amplifier101.

FIG. 3is a schematic diagram of the integrator circuit in an integration phase, such as in accordance with the embodiment ofFIG. 1. For purposes of brevity and clarity, this circuit illustrates only the positive integrating portion ofFIG. 1. However, the negative integrating portion ofFIG. 1operates in a substantially similar manner.

This circuit shows that the positive input voltage Vipnode switch106is open to disconnect the Vipfrom its respective sampling capacitor130. One or both of the input reference voltage node switches104,105is closed so that one of these nodes is now connected to one side of the sampling capacitor130. The integrator phase switch102is closed to connect the other side of the sampling capacitor130to the input of the amplifier101. The sampling phase switch103is open to remove the common mode voltage from the circuit. Thus, the sampled voltage stored in the sampling capacitor130is free to be applied to the amplifier101.

The amplifier101in the above circuits ofFIGS. 1-3has finite gain and finite gain bandwidth. This will affect the settling accuracy, and then deteriorate the total harmonic distortion (THD) of the signal. However, the time constant during the sampling phase is much smaller because the switch resistance is usually relatively very small. In designing the amplifier101for the integrator, it is desirable to have a time constant of 1/N of the pulse width (i.e., N represents a number of time constants) of the integration phase clock so that the settling accuracy can be N*τ where τ is the time constant of the integrator circuit's amplifier. However, since the transistors in the amplifier have fabrication process variations across the silicon wafer, the transconductance of the input of the amplifier may be smaller than a typical value, making the time constant larger and the settling accuracy reduced from a desired value.

For example, transistors formed in slower portions of an integrated circuit wafer may have smaller transconductance values and, thus, worse THD as compared to faster portions of the wafer. Increasing the current in the amplifier may increase the transconductance and improve the THD in the slower portions of the wafer. This would result in an undesirable increase in the circuit power requirements.

The adaptive controlled duty cycle circuit of the present embodiments keeps the integration phase clock pulse width at N times of the time constant of the amplifier. Using the adaptive controlled duty cycle circuit, the settling time accuracy for the integration amplifier may be increased to compensate for fabrication process variations. In an ideal amplifier, N is approximately in a range of 8-10 to approximately provide a desirable −80 dB THD.

FIG. 4is a block diagram of an adaptively controlled duty cycle clock generation circuit, such as in accordance with various embodiments. The block diagram includes a local oscillator circuit401, an adaptively controlled duty cycle clock generation circuit405, and a non-overlapping clock generation circuit407. The adaptively controlled duty cycle clock generation circuit405is discussed subsequently in greater detail with reference toFIG. 9.

The local oscillator circuit401is configured to generate a clock CLK. The local oscillator circuit401may be a clock circuit or a voltage controlled oscillator that generates the clock CLK which is usually having a 50% duty cycle.

The clock CLK from the oscillator circuit401is input to the adaptive control duty cycle clock generation circuit405. This circuit generates adaptively generates the adaptive duty cycle clock CLK2that enables the integration phase clock pulse to have a pulse width of N*τ.

FIG. 5is a timing diagram of non-overlapping clocks with an adaptively controlled duty cycle clock, such as in accordance with various embodiments. The CLK signal represents the 50% duty cycle clock generated by the oscillator circuit401ofFIG. 4. The CLK2signal represents the adaptive duty cycle clock generated from the CLK signal by the adaptive control duty cycle clock generation circuit405ofFIG. 4. Pulses of the CLK2signal are separated by N*τ.

The CLK2signal is input to the non-overlapping clock generation407to generate the sampling phase clock P1and the integrating phase clock P2from the CLK2clock. It can be seen that the P1and P2clocks are non-overlapping clocks and the pulses of P2are now adaptively controlled to be N*τ wide.

FIG. 6is a schematic diagram of an amplifier circuit, such as in accordance with various embodiments. This circuit illustrates the determination of the transconductance gmand the time constant τ of the integrator circuit. This circuit is only one example of an amplifier circuit. Other embodiments may implement an amplifier using different components.

The transconductance gmmay be determined by:

gm=2⁢μ⁢⁢Cox⁡(WL)1⁢I
where W is a fabrication width of each of the input transistors601,602, L is a fabrication length of each of the input transistors601,602(the size of the two input transistors is assumed to be the same), I is the current through each input branch that includes the input transistors601,602, and Coxis a fixed capacitance parameter determined by the fabrication process. Transistor M7603generates a bias voltage for transistor M6604from a current source (e.g., current Ib).

The time constant τ of the circuit ofFIG. 6may be determined by:

τ=CLgm
where CLis the integrator load capacitance.

FIG. 7is a schematic diagram of a constant transconductance bias circuit with a feedback circuit, such as in accordance with various embodiments. This circuit is used to adjust the conductance of R to the transconductance of the input transistors601,602of the integrator amplifier, as illustrated inFIG. 6. The feedback circuit adjusts a resistance R710as described subsequently.

The circuit includes a current adapter circuit700, a transconductance bias circuit701, and a plurality of transistors720-723. The transconductance bias circuit701, includes a plurality of transistors703,704,706,707, and a variable resistance710.

The transconductance bias circuit701includes a first path730and a second path731configured as a current mirror. In the first path, a first transistor703is coupled in series with a second transistor704that is coupled in series with the variable resistance710. In the second path731, a first transistor706is coupled in series with a second transistor707. The two paths are coupled in parallel at a top common node and a bottom common node.

Transistors703and707are each coupled in a diode configuration where their respective control gates are coupled to their drain nodes. The control gates of the first transistors703,706of each path730,731are coupled together and the control gates of the second transistors704,707of each path730,731are coupled together.

The output of the current adapter circuit700is coupled to the variable resistance710such that the current adapter circuit700varies the resistance of the variable resistance710. The structure and operation of the current adapter circuit700and variable resistance710are discussed subsequently in greater detail with reference toFIG. 8.

Path732includes transistors720,721coupled in series and the input node of the current adapter circuit700is coupled to a common node between these transistors720,721. The source node of transistor720is coupled to the top common node of the two paths730,731. The control gate of the transistor720is coupled to the control gates of the first transistors703,706. The drain of the transistor720is coupled to the input of the current adapter700.

The control gates of transistors721-723are all coupled together and the sources of transistors721-723are coupled together. The gate of transistor723is coupled to its drain in a diode configuration. The drain of transistor721is coupled to the input of the current adapter circuit700and in series with transistor720as part of path732. Transistor M7603is the same transistor M7603inFIG. 6that generates the bias voltage from the current source and current Ib. Transistor M6704is the same transistor M6604inFIG. 6that provides the current of 2I for the amplifier.

Paths730-732are each current mirror circuits. Transistor722and path732mirror the current from transistor723, thus the current of path732and transistor722are proportional. The current IM8through the first path is equal to IM9through the second path731and IM10through the third path732(i.e., IM8=IM9=IM10).

In the constant transconductance bias circuit701, the value of the resistance R710is adjusted so that the current IM8and IM9is equal to I/M where I is the current of amplifier input transistors M1601,602ofFIG. 6and M is an integer set by a factor of size difference between transistor M9707and transistors M1601,602.

The physical size of transistor M9is fabricated so that it is proportional to the size of each of input transistors M1601,602. The size of M9707may be represented by

(WL)M⁢⁢9
where W is the fabricated width of the transistor M9707and L is the fabricated length. Thus,

(WL)M⁢⁢9=(WL)M⁢⁢1/M
and the transconductance of transistor M9707is 1/M of the transconductance of the input transistors M1601,602. This gmmay be expressed by:

gm=2⁢μ⁢⁢Cox⁡(WL)M⁢⁢9⁢IM=2⁢μ⁢⁢Cox⁡(WL)M⁢⁢1⁢IM2=gm⁢⁢1M.
K is an integer constant determined at fabrication to express a size difference between transistor M8704and transistor M9707. The fabricated sizes of transistors M8704and M9707is given as:

(WL)M⁢⁢8=K⁡(WL)M⁢⁢9
so that the transconductance of transistor M9707may be expressed as:

For the purposes of simplicity, K=4 and M=1 so that gm9=1/R and the gmof the input transistors M1601,602can be expressed as 1/R and the time constant τ of the amplifier circuit is expressed by:

τ=CLgm⁢⁢1=CL⁢R
where CLis the integrator load capacitance.

In operation, since the series circuits of each of paths730-732are current mirror circuits, their current magnitudes are equal. Thus, adjusting the resistance value R710to change the current IM8in path730will change the currents IM9and IM10in paths731and732, respectively. The current 2I through transistor722is equal to the sum of the currents through each of the amplifier input transistors M1601,602. The current I is compared with the current IM9through path731. If the current IM10is larger than I, then the current IM9is also larger. In this example, M=1, so the current of path731is I, not 2I, thus the current in731is the same as the current of each input transistor601or602individually and not the sum.

When current IM10is greater than I, the input to the current adapter circuit700will be pulled high since this current is larger than current I/M (M=1, in this example) through transistor M11721. When the input to the current adapter circuit700is pulled high, the circuit700increases the resistance value R710. This decreases current IM8which decreases current IM9and thus, decreases current IM10.

Conversely, when current IM10is less than I, the input to the current adapter circuit700will be pulled low by the larger current I/M through transistor M11721. When the input to the current adapter circuit700is pulled low, the circuit700decreases the resistance value R710. This increases current IM8which increases current IM9and thus, increases current IM10.

After the calibration, the resistance of R is 1/gm1, where gm1 is the input transconductance of input transistors601,602. The circuit ofFIG. 7calibrates the resistance of R such that it is equal to the reciprocal of the transconductance of the input transistors601,602. A resistance identical to resistance R is then used in the non-overlapping clock generation circuit as discussed subsequently with reference toFIG. 9.

FIG. 8is a schematic diagram of the current adapter circuit700, such as in accordance with the embodiment ofFIG. 7. This schematic illustrates only one example of a circuit for adjusting the resistance R710ofFIG. 7. Other embodiments may calibrate this resistance in other ways.

The current adapter circuit700comprises a comparator840and a counter circuit841. The resistance circuit710comprises a plurality of resistances (e.g., resistors)810-813and a plurality of addressable switches801-804.

An output of the comparator840is coupled to an enable input of the counter circuit841. A clock signal CLOCK is coupled to the clock input of the counter circuit841. The resistors810-813are coupled in series from an input node851of the resistance circuit710. Each switch801-804is coupled between a respective common node between two adjacent series connected resistors810-813and an output node850of the circuit710. The switches801-804are controlled by the count output bN-b0from the counter circuit841. The resistance circuit710structure is shown for purposes of illustration. As each switch801-804is activated, its associated resistor810-813is added to the previous resistors810-813for a total resistance R between the nodes850,851. Other resistance circuits may be used in which the resistance may be varied in other ways.

In operation, the input of the current adapter circuit700is a variable voltage depending on the current IM10ofFIG. 7. The comparator840is set with a reference voltage such that when the input voltage is greater than or equal to a predetermined threshold voltage, the output of the comparator is a logic high. When the input voltage is less than the reference voltage, the output of the comparator is a logic low. This enable input is input to the comparator840. The counter circuit841is enabled to count the rising edges of the clock signal CLK when the enable input is an enable state (e.g., logic high). The counter circuit841is disabled from counting when the enable input is a disable state (e.g., logic low).

The counter circuit841generates the count output bN-b0that is input to the resistance circuit710. The count output bN-b0represents a control word that is input to the resistance circuit710to control activating or deactivating the addressable switches801-804. Since the total resistance R of the resistance circuit710is increased or decreased by activation or deactivation of particular switches801-804, the control word controls the total resistance R of the circuit ofFIG. 7so that current IM10is equal to current I/M.

In an embodiment, the counter circuit841is reset to a value of I at power up of the circuit so that the total resistance R starts out relatively low. Thus, the resistance R can be slowly and incrementally increased until IM10is equal to current I/M.

FIG. 9is a schematic diagram of the adaptive control duty cycle clock generation circuit405, such as in accordance with various embodiments. This circuit includes a replica resistance900of resistance R710ofFIG. 7as well as a replica capacitance920of the load capacitance CLof the amplifier circuit. The replica resistance900is the same size and connected to the circuit ofFIG. 7so that the resistance R900in the circuit of FIGL9is adjusted simultaneously with the resistance R710ofFIG. 7.

The adaptive pulse width control circuit further includes a first amplifier901, a first comparator902, a first transistor910, a second transistor911, a switch921and an AND function930. The first amplifier901is coupled to a reference voltage VREFat its negative input node. The control gates of first and second transistors910,911are coupled to the output of the amplifier901. The first transistor910and resistance900(i.e., replica of the resistance R) are coupled in series between two voltage nodes (e.g., VDDand GND). A common node between the resistance900and the first transistor910is coupled to the positive input of the amplifier901.

The second transistor911and the capacitance920(i.e., replica of integrator load capacitance) are coupled in series between the two voltage nodes. A positive input to the comparator902is coupled to a common node between the second transistor911and the capacitance920. A negative input to the comparator902is coupled to the reference voltage VREF. The switch921is coupled between the positive amplifier input and one of the voltage nodes (e.g., GND). The switch921is controlled by a clock signal CLKBP.

An output of the second amplifier902is coupled to an input of the AND function930. A second input to the AND function930is coupled to the clock signal CLK. An output of the AND function930outputs the clock signal CLK2.

In operation, the circuit including the first transistor910, resistance900and amplifier901acts as a current generation. The voltage VREFis a constant voltage generated by a bandgap circuit. The current IM12of the series circuit of the first transistor910and resistance R900is given by VREF/R. The fabrication size of the second transistor911is 1/N of the size of the first transistor910. Thus, the current IM13through the series circuit of the second transistor911and the capacitance920is given by

VREF/RN.
The current IM13charges the capacitance920. Thus, the time for the current to charge the capacitance920to VREFon the positive input of the second amplifier902is set, as NCLR, so the settling time is N*τ. When the capacitance voltage reaches VREF, the output of the comparator902goes high.

The CLKBP is generated by the negative edge of the CLK using the NOR function940with CLK andCLK, output from an inverter941, as inputs. The NOR function940and inverter941circuit catches the negative edge of the CLK and outputs a pulse. The pulse width is determined by the delay of the inverter941.

The CLKBP clock signal activates the switch921when it goes high. Activating this switch pulls the capacitance920discharges the capacitance920to ground causing the positive input to the amplifier902to be 0V and, thus, the output clock CLK2to go to 0V. The pulse width of the CLKBP clock is relatively very short, just enough to discharge the capacitance920and let the current IM13to recharge the capacitance. The AND function930ensures that the CLK2signal is only high while the CLK signal is high and the output of comparator902is high.

FIG. 10is a timing diagram showing the non-overlapping clock and adaptively controlled duty cycle clock, such as in accordance with the embodiment ofFIG. 9. This figure shows the CLK signal on top and the non-overlapping CLK2signal generated by the adaptive control duty cycle clock generation circuit ofFIG. 9.

FIG. 11is a flowchart of a method of operation of the adaptively controlled duty cycle clock generation circuit for an analog-to-digital converter with an integrator amplifier, such as in accordance with various embodiments.

In block1101, an input current is generated in the integrator amplifier. In block1103, the input current is compared to a current mirror current where the current mirror comprises a resistance. In block1105, the resistance is adjusted until the current mirror current is equal to the input current. In block1107, the adaptively controlled duty cycle output clock is generated based on a time constant of the adjusted resistance and a load capacitance of the integrator amplifier circuit, wherein the time constant is proportional to a settling time of the integrator amplifier. Generating the adaptively controlled duty cycle output clock comprises charging the capacitance to a first voltage, comparing the first voltage to a reference voltage, generating a first output voltage when the first voltage is equal to or greater than the reference voltage, and generating a second output voltage when the first voltage is less than the reference voltage, where the second output voltage is less than the first output voltage.

FIG. 12is a block diagram of an analog-to-digital converter circuit1200, such as in accordance with various embodiments. This circuit1200is a simplified block diagram to highlight the various embodiments disclosed herein.

The circuit1200includes at least one integrator circuit100that includes an input amplifier. One example of such a circuit is illustrated inFIG. 1. The adaptive duty cycle control circuit405, as shown inFIG. 4, is coupled to the integrator circuit100to generate the adaptive duty cycle clocks for the integration operations. The transconductance bias circuit701is coupled to the adaptive duty cycle control circuit405to provide the adaptively control of the duty cycle of the input clock based on the product of the resistance in the transconductance bias circuit701and a capacitance, where the product is proportional to a settling time of the integrator. The resistance is determined based on the transconductance of the integrator amplifier.