High efficiency amplifier with reduced parasitic capacitance

A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

FIELD OF THE INVENTION

The present invention generally relates to semiconductor (SC) devices and integrated circuits (ICs) and, more particularly, to semiconductor amplifiers having reduced parasitic capacitance and higher power conversion efficiency.

BACKGROUND OF THE INVENTION

Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) often employ amplifiers whose overall performance and efficiency depend critically on the parasitic capacitance and efficiency of the amplifying transistors and on other circuit elements. If the parasitic capacitance is too high, amplifier efficiency and frequency response can suffer. Accordingly, there is an ongoing need to provide semiconductor amplifiers in which such parasitic capacitance is reduced so as to achieve improved power conversion efficiency.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.

The various embodiments of the invention described herein are illustrated by semiconductor devices and structures of particular conductivity type, as for example an NPN bipolar transistor having various P and N doped regions appropriate for that conductivity type device or structure. But this is merely for convenience of explanation and not intended to be limiting. Persons of skill in the art will understand that devices or structures of opposite conductivity type may be provided by interchanging conductivity types so that a P-type region becomes an N-type region and vice versa. For example, reference to an N-type buried layer (NBL) in an NPN transistor is intended to also represent a P-type buried layer of a PNP transistor, etc. Alternatively, the particular regions illustrated in what follows may be more generally referred to as of a “first conductivity type” and a “second opposite conductivity type”, where the first conductivity type may be either N or P type and the second opposite conductivity type is then either P or N type, and so forth. Silicon is an example of a suitable semiconductor material for the devices described herein, but persons of skill in the art will understand that the present invention applies to any type of semiconductor employing dielectric trench isolation walls, for example and not intended to be limiting, other type IV materials such as Ge and SiGe combinations, III-V materials, II-VI materials, combinations thereof and so forth. It will also be understood by those of skill in the art, that the present invention is not limited merely to bipolar transistors as shown herein by way of example, but applies to any semiconductor device wherein the principal output region has lateral parasitic capacitance arising from an adjacent isolation wall. While the examples presented herein show two or three unit amplifying cells, those of skill in the art will understand that any number from 1 to N unit amplifying cells may be included depending upon the desired power output. The larger the number of unit cells (or the larger the area of the unit cells) the greater the power output that can be realized.

FIG. 1is a simplified schematic cross-sectional view of two unit cells24,24′ of prior art bipolar amplifier20formed from two bipolar transistors25,25′.FIG. 2shows simplified plan view38of three unit cells24,24′,24″ of prior art bipolar amplifier20′ analogous to that depicted in cross-section inFIG. 1.FIG. 1further has capacitor symbols37added to indicate how lateral parasitic capacitance can arise in such prior art structures. Referring toFIGS. 1 and 2together, amplifier20,20′ comprises substrate22(e.g., P-type of resistivity of about 10-20 Ohm-cm), although high resistivity substrates typically of resistivity of about 500 Ohm-cm or greater, may also be used. Amplifier20,20′ has further semiconductor (SC) layer39typically formed by epitaxial growth on substrate22in which the various device regions above buried layer (BL)27,27′,27″ are formed. At the interface between further SC layer39and substrate22there are provided buried layer regions27,27′,27″ identified for convenience of description as N-type buried layer regions (abbreviated as “NBL”) and having sheet resistance of about 10 Ohms/sq., but higher or lower values may also be used. Above NBL27,27′,27″ lie N-type collector regions28,28′,28″ typically of doping density between about 1E16 and 1E18 atoms/cc and with N+collector contact regions34,34′,34″ and collector terminals35,35′. P-type base regions29,29′,29″ typically of doping density of about 1E18 to 1E19 atoms/cc are formed in N-type collector region28,28′,28″ by any convenient means. In order to avoid unduly cluttering the drawings, base contact regions are not shown inFIGS. 1 and 2, but persons of skill in the art will understand that they are customarily provided. N+emitter regions30,30′,30″ with emitter terminals31,31′ are formed in base regions29,29′,29″. Dielectric filled trench (abbreviated as “DFT”) lateral isolation walls26,26′,26″ laterally surround each unit cell24,24′,24″ with transistor25,25′,25″. Between  and laterally outside DFT isolation walls26,26′,26″ are P-type semiconductor regions36in further SC layer39. These are identified by the abbreviation “SP” to indicate that they are P-type regions ohmically coupled to P-type substrate (S)22.

Capacitance symbols37represent the lateral parasitic capacitance that exists between N type collector regions28,28′,28″ and SP regions36across DFT isolation walls26,26′,26″. As indicated inFIGS. 1-2, buried layer regions27,27′,27″ extend between surrounding isolation walls26,26′,26″ beneath transistors25,25′,25″, and may, as shown inFIG. 1, protrude slightly beyond DFT isolation walls26,26′,26″, but do not extend across SP regions36. In the prior art, the contribution of the lateral parasitic capacitance represented by capacitor symbols37, has been neglected as being inconsequential compared to the inhered junction capacitance between, for example, NBL regions27,27′,27″ and P-type substrate22. However, it has been found that this simplifying assumption is incorrect and that such lateral parasitic capacitance does have in many cases a significant adverse effect on amplifier properties, and that it can be avoided, for example, by the improved designs presented in the various embodiments described herein.

FIG. 3is a simplified schematic cross-sectional view of two unit cells42,42′ of bipolar amplifier40formed in portions43,43′ of device40and having reduced parasitic collector capacitance according to an embodiment of the present invention.FIG. 4shows simplified plan view48of three unit cells42,42′,42″ of bipolar amplifier40′ formed in portions43,43′,43″ and analogous to that depicted in cross-section inFIG. 3. As noted earlier, any number of unit cells may be included depending upon the desired power output. In general, the doping densities and resistivities of the various regions ofFIGS. 3-4are substantially similar to those described for analogous regions ofFIGS. 1-2. ConsideringFIGS. 3-4together, amplifier40,40′ differs from amplifier20,20′ ofFIGS. 1-2by: (i) inclusion of additional peripheral DFT isolation wall46surrounding unit cells42,42′,42″ and extending from surface391at least to substrate22, and (ii) arranging for portions361formed in parts431of SP regions36lying laterally outside DFT isolation walls26,26′,26″ and within further DFT isolation wall46to be electrically floating rather than ohmically coupled to substrate22. Accordingly, such electrically floating portions or regions361are identified by the abbreviation “FP” indicating that they are electrically floating P-type regions. This is accomplished by providing buried layer regions271between DFT isolation walls26,26′,26″ and between DFT isolation walls26,26′,26″ and peripheral DFT isolation wall46. Newly provided N-type NBL regions271between and around DFT  isolation walls26,26′,26″ are electrically floating since they are cut-off from buried layer regions27,27′,27″ of transistors25,25′,25″ by DFT isolation walls26,26′,26″ and are isolated from substrate22by virtue of the PN junctions formed therebetween. Floating NBL regions271electrically isolate FP portions361from substrate22, thereby also rendering FP portions361electrically floating. Since FP portions361are electrically floating they do not respond to changes in alternating current (AC) potential of N-type collector regions28,28′,28″ or buried layer regions27,27′,27″ across DFT isolation walls26,26′,26″ and therefore the lateral parasitic capacitance represented by capacitor symbols371inFIG. 3of amplifier structure40,40′ ofFIGS. 3-4is significantly reduced compared to that exhibited by amplifier structure20,20′ ofFIGS. 1-2. This improvement is quantitatively illustrated inFIGS. 5-6.

It has been assumed in the foregoing description and in the description that follows, that isolation walls26,46are comprised of dielectric filled trenches (DFTs). However, isolation walls26,46may have non-dielectric cores, provided that such cores are left floating. For example, according to further embodiments, isolation walls having poly-semiconductor cores may be used. These poly-cores may be doped or undoped. As long as they are floating, they have no significant effect on the phenomena and solutions described herein. Accordingly, the words “dielectric filled trench isolation walls” and the abbreviation “DFT” and “DFT isolation walls” are intended to also include those isolation walls that may have floating conductive cores of poly or other conductive materials with a surrounding dielectric material located between the cores and the semiconductor regions on either side of the trench.

FIG. 5shows plot50of the power added efficiency in percent as a function of the output power in dBm, comparing the amplifiers ofFIGS. 1-2andFIGS. 3-4operating at 1.9 GHz. Referring now toFIG. 5, power added efficiency (PAE) is a measure of how efficiently the amplifier converts direct current (DC) power to alternating current (AC) power and is defined as the ratio of the difference between the output AC power and the input AC power, divided by the input DC power, expressed as a percent. Assuming radio frequency (RF) operation, this is conveniently expressed by the formula:
PAE=100×(RFPout−RFPin)/DCPin,  [Eq. 1]
where RFPout is the output RF power, RFPin is the input RF power and DCPin is the direct current (DC) power input to the amplifier. InFIG. 5, trace52shows PAE in percent versus RFPout for amplifier20,20′ ofFIGS. 1-2and trace53shows PAE in percent versus RFPout for amplifier40,40′ ofFIG. 3-4. In these tests yielding traces, both amplifiers embodied18unit cells and, other than the modifications identified in (i) and (ii) above, were substantially similar and for traces52,53had substrate resistivity of about 19 Ohm-cm. Further trace54shows PAE in percent versus RFPout for amplifier40,40′ ofFIG. 3-4similar to that used in obtaining trace53but with a high resistivity substrate having a resistivity equal or greater than 500 Ohm-cm. It will be noted that a significant increase in PAE is obtained as a consequence of the invented embodiments. For future reference in connection withFIGS. 7-11, it is pointed out that trace54comprises two superimposed traces, a first trace showing the results for amplifier40,40′ ofFIGS. 3-4with a high resistivity substrate as noted above, and a second co-incident trace showing the results for an amplifier of the same geometry as amplifier40,40′ but with a further doped region underlying NBL27between NBL27and high resistivity substrate22. This further doped layer had doping intermediate between NBL27and high resistivity substrate22. The two traces54are substantially coincident. The reasons why such a further doped region is often desirable is explained in connection withFIGS. 7-11.

FIG. 6shows plot55of the collector capacitance in pico-farads as a function of collector voltage in volts, comparing the amplifiers ofFIGS. 1-2andFIGS. 3-4, without and with the combined use of a high resistivity substrate, as discussed above. Trace56ofFIG. 6shows the collector capacitance versus collector-substrate voltage for device20,20′ ofFIGS. 1-2with a standard substrate resistivity of about 19 Ohm-cm. Trace57ofFIG. 6shows the collector capacitance versus collector-substrate voltage for device40,40′ ofFIG. 3-4with a standard substrate. Trace58ofFIG. 6shows the collector capacitance versus collector-substrate voltage for device40,40′ ofFIGS. 3-4with a high resistivity substrate having a resistivity equal or greater than 500 Ohm-cm. It will be noted that a significant reduction in parasitic capacitance is obtained as a consequence of the invented embodiments.

While use of high resistivity substrates can reduce the parasitic capacitance of the amplifier and improve its power added efficiency, it can have deleterious effects in other parts of the same die.FIG. 7shows a simplified schematic cross-sectional view of unit cell61of bipolar amplifier60analogous to amplifier20,20′ ofFIGS. 1-2, together with buried  layer (BL) contact region63elsewhere on the same die, illustrating how undesirable parasitic buried layer (BL) leakage can arise. For convenience of illustration, BL contact region63and amplifying unit cell61are shown as being adjacent, but this is not essential and BL contact region63may be remote from amplifying unit cell61. Amplifier unit cell61is substantially the same as unit cell24or24′ ofFIGS. 1-2and the description thereof is included herein by reference, with the proviso that substrate62ofFIG. 7is of high resistivity (e.g., resistivity of about 500 Ohm-cm or greater). Electrically and physically separated NBL regions64and68having separation81of, for example and not intended to be limiting, about 2.5 micrometers are illustrated in BL contact region63. Larger or smaller separation may also be used. NBL region64having a doping density comparable to that of NBL27(e.g., sheet resistance of about 10 Ohms/sq.) is coupled to contact67by means of N sinker65and N+ contact region66having doping density similar to that of contact34. NBL region68also having a doping density comparable to that of NBL27is coupled to contact71by means of N sinker69analogous to sinker65and N+ contact region70analogous to contact region66. NBLs64,68, sinkers65,69, and N+ contact regions66,70are electrically and physically separated by SP regions76analogous to SP regions36ofFIGS. 1-2.

In multi-element devices, it is often the case that NBLs64,68will be at different electrical potentials. It has been found that when substrate62is formed from high resistivity material, that significant electrical leakage can exist between NBLs64,68via substrate62, as represented by resistor74. This parasitic leakage is undesirable since it wastes power, and adds to the joule heating of substrate62, which is often a critical parameter in high power device structures and may cause other undesirable side-effects. Thus, if the use of a high resistivity substrate is attempted in order to lower the parasitic collector-substrate capacitance of the amplifier portions of the die or IC (e.g., in unit cell61or analogous unit cells24,24′,24″), this attempt may be rendered impractical by the increase in parasitic leakage described above between buried layer regions such as NBLs64,68elsewhere on the die or IC.

FIG. 8shows a simplified schematic cross-sectional view of unit cell61′ of bipolar amplifier76analogous to amplifier20,20′ ofFIGS. 1-2, together with buried layer (BL) contact region63′ elsewhere on the same die, according to a further embodiment of the invention, showing how the undesirable parasitic buried layer (BL) leakage illustrated in connection withFIG. 7can be avoided without adverse effect on the parasitic capacitance in  amplifier unit cell61′. As noted above, BL contact region63′ is shown as being adjacent to amplifying unit cell61′, but this is merely for economy of illustration and BL contact region63′ may be located anywhere in the same die as unit amplifying cell61′. To facilitate comparison, spacing81between NBLs64,68inFIG. 8is substantially the same as inFIG. 7. Amplifier76ofFIG. 8differs from amplifier60ofFIG. 7by inclusion in amplifier76of additional P-type layer78having a maximum doping density of about 1E16 atoms/cm3, intermediate between the doping density of NBLs64,68(e.g., typically about 1E19 atoms/cm3or greater) and the doping density of high resistivity P-type substrate62(e.g., typically about 1E13 atoms/cm3or less). An implant dose of about 5E11 atoms/cm2with an energy of about 800 kilo-electron volts is suitable for layer78, but lower or higher doses and energies may be used depending upon the depth of buried layer regions64,68,27and the doping thereof and of substrate62. The effect of layer78is to reduce the leakage current (as shown inFIG. 9) that would otherwise occur between NBLs64,68by reducing the width of depletion regions of the reverse biased p-n junctions associated with NBLs64,68, and thereby preventing punch through between such adjacent depletion regions.

Layer78is shown inFIG. 8as having three portions; portion781beneath BL contact region63′, portion782beneath amplifier unit cell61′ and portion783beneath SP region76at the right side ofFIG. 8. Only portion781is needed to reduce the leakage between NBLs64,68. By performing a masked implant with unit cell61′ (and SP region76at the right side ofFIG. 8) covered, portion782(and783) may be omitted so that only portion781is provided. Portion781is sufficient to reduce the parasitic leakage illustrated inFIG. 7as shown inFIG. 9. However, for convenience of manufacturing, it is sometimes desirable to provide layer78by means of an unmasked blanket implant, which provides layer78in contact with and extending below NBLs64,68,27. Having portion782between NBL27and substrate62does not adversely affect the performance of amplifier unit cell61′ if the doping in portion782is chosen so that portion782is completely depleted under operating conditions. This is illustrated by trace54ofFIG. 5, wherein the PAE behavior of an amplifier of the type illustrated inFIGS. 3-4with and without layer78were found to be substantially the same, so that their PAE versus Pout traces are substantially coincident traces54.

FIG. 9shows plot72of buried layer leakage current in Amperes as a function of NBL64to NBL68contact-to-contact bias voltage in volts for the arrangement ofFIGS. 7 and 8under various conditions. Trace73shows the leakage current between NBLs64,68of BL contact region63ofFIG. 7wherein substrate62is of high resistivity material with a resistivity of about 500 Ohm-cm or greater and no implant layer equivalent to layer78ofFIG. 8. Trace77shows the leakage current between NBLs64,68of BL contact region63ofFIG. 7wherein substrate62has the standard resistivity of about 19 Ohm-cm and NBLs64,68are laterally spaced about 2.5 micrometers apart. A comparison of traces73and77illustrates the very large adverse leakage effect than can arise merely from using a high resistivity substrate in an attempt to reduce the parasitic capacitance of an amplifier elsewhere on the same die. Trace75shows the leakage current between NBLs64,68of BL contact region63′ ofFIG. 8wherein substrate62is of high resistivity material with a resistivity of about 500 Ohm-cm or greater and with layer78provided by an implant of about 5E11 ions/cm2at 800 keV, as has been previously described in connection withFIG. 8. It will be noted that providing region781of layer78underneath NBLs64,68of BL contact region63′ as described in connection withFIG. 8, reduces the leakage that would otherwise accompany use of a high resistivity substrate by about six to seven orders of magnitude, and as shown by co-incident trace54ofFIG. 5(as noted above), without any adverse effect on the PAE of amplifier unit cell61′ on the same die. The arrangement ofFIG. 8makes it possible to avoid the excess BL contact leakage when using a high resistivity substrate, which might otherwise preclude its use to help in lowering the parasitic capacitance of an associated amplifier on the same die.

FIG. 10shows a simplified schematic cross-sectional view of unit amplifier cell61″ and associated buried layer (BL) contact region63″ of bipolar amplifier80, according to a still further embodiment of the present invention. Amplifier80ofFIG. 10has N-type substrate82having a resistivity of about 500 Ohm-cm or greater. Substrate82is desirably floating, that is, not coupled to the reference potential of amplifier80. Amplifier80has P-type layer84of thickness89similar to P-type layer78ofFIG. 8, but it may have a higher doping density than P-type layer78ofFIG. 8. Like layer78, layer84has portion841beneath BL contact region63″, portion842beneath unit amplifying cell61″ and portion843beneath P region361at the right side ofFIG. 10. Since substrate82′ is N-type, it forms a PN junction with layer84, and P regions76″ and361are no longer ohmically coupled to substrate82. By replacing P-type substrate62with N-type substrate82, the parasitic capacitance associated with amplifying unit cell61″ is reduced. Because layer84is not a high resistivity layer but of intermediate resistivity or dopant concentration analogous to layer78ofFIG. 8(or higher), the  leakage between NBLs64,68is reduced compared to that ofFIG. 7.

FIG. 11shows a simplified schematic cross-sectional view of unit amplifier cell61′″ and buried layer (BL) contact region63′″ of a bipolar amplifier90, according to a yet still further embodiment of the present invention.FIG. 11differs fromFIGS. 7-8and10in that unit amplifying cell61′″ incorporates the structure illustrated in unit amplifying cells42,42′,42″ ofFIG. 3-4, which substantially reduces the lateral parasitic capacitance and further improves the PAE. Layer94has at least portion941and in other embodiments also one or more of portions942-944. Layer94is P-type. Substrate92may be P-type, as described in connection withFIG. 8or N-type as described in connection withFIG. 10, depending upon the desires of the designer and capability of the manufacturing process. As a consequence of incorporating the structure of unit amplifying cells42,42′,42″, etc., P-regions361located in parts431between DFT isolation walls26,26′,26″ and between DFT isolation walls26,26′,26″ and DFT isolation wall46are no longer ohmically coupled to substrate92and are identified as floating P-regions, abbreviated as “FP”, as a consequence of additional buried layer regions271′,271″. When substrate92is high resistivity P-type, the maximum reduction in collector-substrate capacitance is obtained in unit amplifying cells61′″ and where region941is P-type and of intermediate doping density as described in connection withFIG. 8, the problem of significant leakage between NBL contacts64,68of spacing81is avoided without adverse affect on the PAE behavior of unit amplifying cell61′″. The configuration ofFIG. 11is preferred since both low capacitance, high PAE and low BL contact leakage can be obtained. This is highly desirable.

According to a first embodiment, there is provided a semiconductor amplifier comprising, a semiconductor substrate, a semiconductor (SC) layer overlying the substrate and having an outer surface, one or more semiconductor unit amplifying cells formed in a first part of the SC layer; one or more first dielectric filled trenches (DFTs), wherein each of the one or more semiconductor unit amplifying cells is laterally surrounded by one of the one or more first DFTs, which first DTFs extend through the SC layer from the outer surface to at least the substrate, a second DFT laterally surrounding the one or more first DTFs and extending through the SC layer from the outer surface at least to the substrate, and further semiconductor regions located in a second part of the SC layer between the first and second DFTs, and wherein the further semiconductor regions are electrically floating with respect to the substrate. According to a further embodiment, the semiconductor substrate is of a first  conductivity type and the one or more unit amplifying cells comprise, a collector region of a second, opposite conductivity type, a base region of the first conductivity type located in the collector region, an emitter region of the second opposite conductivity type located within the base region, and a first buried layer (BL) region of the second, opposite conductivity type separating the collector region from the substrate and extending laterally across the first DFT surrounding each unit amplifying cell, and wherein the further semiconductor regions are separated from the substrate by a second BL region of the second, opposite conductivity type. According to a still further embodiment, the amplifier further comprises two or more third BL regions of the second, opposite, conductivity type located in one or more further parts of the SC layer laterally outside the second DFT, wherein the third BL regions are coupled to the outer surface of the SC layer by additional regions of the second opposite conductivity type and the third BL regions and additional regions are separated by still further semiconductor regions of the first conductivity type. According to a yet further embodiment, a portion of the substrate underlying the third BL regions has two or more parts of different doping density, a first part of a first doping density underlying and separated from the third BL regions and a second part lying between the third BL regions and the first part of the substrate, wherein the second part of the substrate has a second doping density intermediate between a doping density of the third BL regions and the doping density of the first part of the substrate. According to a still yet further embodiment, the first part of the substrate is of high resistivity. According to a yet still further embodiment, the amplifier further comprises a first buried layer (BL) extending laterally across and underlying at least one of the one or more unit amplifying cells, wherein the first BL is laterally bounded by the first DFT surrounding the at least one unit amplifying cell, and wherein the first BL is of a first doping type and first doping level, and the substrate is of a second, opposite conductivity type and has a first part separated from and lying beneath the first BL and of a second doping level less than the first doping level and a second part lying between the first part and the BL and of a third doping level intermediate between the first and second doping levels. According to an additional embodiment, the first part of the substrate has a resistivity equal or greater than about 500 Ohm-cm. According to a still additional embodiment, the BL has a sheet resistance of about 10 Ohms/sq. According to a yet additional embodiment, at least the first DFT has a polycrystalline semiconductor core.

According to a second embodiment, there is provided a semiconductor device, comprising, a substrate of a first conductivity type and having a first portion in which are  located one or more amplifier unit cells, two or more dielectric filled trench (DFT) isolation walls, comprising, first isolation walls laterally surrounding each of the one or more unit amplifying cells, and a second isolation wall separated from the one or more first isolation walls and collectively laterally surrounding the first isolation walls, and semiconductor regions overlying the substrate and of the first conductivity type lying between the first and second isolation walls, and wherein the semiconductor regions are electrically floating with respect to the substrate. According to a further embodiment, the semiconductor device further comprises buried layer (BL) regions of a second, opposite conductivity type having first portions underlying the one or more amplifying unit cells and second portions electrically separated from the first portions and underlying further semiconductor regions located outside the first DFT isolation walls. According to a still further embodiment, the first portion of the substrate in which are located the one or more amplifier unit cells further comprises buried layer (BL) regions of a second, opposite conductivity type and BL doping concentration underlying the one or more amplifying unit cells and extending laterally within the first isolation walls laterally surrounding each of the one or more unit amplifying cells, wherein the first portion of the substrate has parts of different doping concentrations beneath the BL regions, a first part in contact with the BL region of a first doping concentration less than the BL doping concentration and a second part underlying the first part and of a second doping concentration less than the first doping concentration. According to a yet further embodiment, the second doping concentration corresponds to a resistivity greater than or equal to about 500 Ohm-cm. According to a still yet further embodiment, the substrate further comprises, a second portion separated from the first portion, the second portion comprising spaced-apart buried layer (BL) regions of a second, opposite conductivity type and BL doping concentration, having contact sinkers extending from these spaced-apart BL regions to an external surface adapted to receive electrical connections thereto; and wherein a part of the second portion underlying the spaced-apart BL regions comprises a first region of the first conductivity type and a first doping concentration less than the BL doping concentration and a second region of the first conductivity type and a second doping concentration less than the first doping concentration. According to a yet still further embodiment, the second doping concentration corresponds to a resistivity of about 500 Ohm-cm or more.

According to a third embodiment, there is provided an electronic device, comprising, a semiconductor substrate of a first conductivity type and having a first surface,  spaced-apart first buried layer (BL) regions of a second, opposite, conductivity type and BL doping concentration, located within the substrate and spaced apart from the first surface, contact sinker regions of the second, opposite, conductivity type, extending substantially from the first surface to the spaced-apart first BL regions and adapted to facilitate individual electrical contact to the spaced-apart first BL regions, wherein a first portion of the semiconductor substrate underlying the spaced-apart first BL regions has a first doping concentration less than the BL doping concentration, and a second portion of the semiconductor substrate underlying the first portion has a second doping concentration less than the first doping concentration. According to a further embodiment, the second doping concentration corresponds to a resistivity equal or greater than about 500 Ohm-cm.