Semiconductor device and method of forming the same

A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor device and a method of forming the same.

Priorities are claimed on Japanese Patent Applications Nos. 2010-266916, filed Nov. 30, 2010 and 2011-105376, filed May 10, 2011, the contents of which are incorporated herein by reference.

2. Description of the Related Art

In recent years, semiconductor devices such as DRAMs (Dynamic Random Access Memories) have been miniaturized. Accordingly, if a gate length of a transistor is shortened, a short channel effect of the transistor is noticeable. As a result, sub-threshold current increases and a threshold voltage (Vt) of the transistor decreases.

Further, when impurity concentration of a semiconductor substrate increases in order to suppress the decrease of the threshold voltage (Vt) of the transistor, junction leak current increases.

Thereby, when a memory cell of a semiconductor device such as a DRAM is miniaturized, degradation of a refresh characteristic is a severe problem.

As a structure for resolving such problems, a trench gate transistor in which a gate electrode is buried in a trench formed in a main surface of a semiconductor substrate (also called “recess channel transistor”) is disclosed in Japanese Patent Laid-open Publication No. 2006-339476 and Japanese Patent Laid-open Publication No. 2007-081095.

As the transistor is a trench gate transistor, an effective channel length (gate length) can be secured physically sufficiently and a DRAM including a fine cell having a minimum processing dimension equal to or less than 60 nm can be realized.

Further, a DRAM including two trenches formed to be adjacent to each other in a semiconductor substrate, gate electrodes formed in the respective trenches through a gate insulating film, a first impurity diffusion region formed in a main surface of the semiconductor substrate located between the two gate electrodes and common to the two gate electrodes, and a second impurity diffusion region formed in the main surface of the semiconductor substrate located at a side of an element isolation region of the two gate electrodes is disclosed in Japanese Patent Laid-open Publication No. 2007-081095.

SUMMARY

In one embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove having first and second side walls facing to each other; a first gate insulating film covering the first and second side walls of the first gate groove; a first gate electrode on the first gate insulating film, the first gate electrode being in a lower portion of the first gate groove; a first burying insulating film that buries the first gate groove, the first burying insulating film covering the first gate electrode; a first diffusion region adjacent to a first upper portion of the first gate insulating film, the first upper portion being on an upper portion of the first side wall of the first gate groove; and a second diffusion region in contact with an entire portion of the second side wall of the first gate groove.

In another embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate having at least an active region that extends in a first direction, the semiconductor substrate having first and second gate electrode grooves; first and second isolation regions in the semiconductor substrate, the first and second isolation regions extending in a second direction, the first and second isolation regions extending across the at least active region to divide the at least active region into a plurality of device formation regions; first and second transistors disposed between the first and second isolation regions, the first and second transistors being aligned and adjacent to each other in the first direction, the first and second transistors having first and second diffusion regions, respectively, the first and second transistors having a third diffusion region as a common diffusion region, the third diffusion region being disposed between the first and second gate electrode grooves; a bit line electrically coupled to the third diffusion region; first and second gate insulating films in the first and second gate electrode grooves; and first and second gate electrodes on the first and second gate insulating films, respectively, the first and second gate electrodes burying lower portions of the first and second gate electrode grooves. The first diffusion region is in the semiconductor substrate, the first diffusion region is disposed between the first isolation region and the first gate electrode groove, the first diffusion region has a first bottom which is higher in level than a top portion of the first gate electrode. The second diffusion region is in the semiconductor substrate, the second diffusion region is disposed between the second isolation region and the second gate electrode groove, the second diffusion region has a second bottom which is higher in level than a top portion of the second gate electrode. The first gate electrode groove has first and second side surfaces and a first bottom, the first side surface facing against the first isolation region, the second side surface being adjacent to the third diffusion region. The second gate electrode groove has third and fourth side surfaces and a second bottom, the third side surface facing against the second isolation region, the fourth side surface being adjacent to the third diffusion region. The third diffusion region fills entirely in an interposed region of the semiconductor substrate between the first and second gate grooves, the third diffusion region extending from an upper surface of the semiconductor substrate to the bottoms of the first and second gate electrode grooves. The first transistor has a first channel region between the first diffusion region and the bottom of the third diffusion region. The second transistor has a second channel region between the second diffusion region and the bottom of the third diffusion region.

In still another embodiment, a method of forming a semiconductor device may include, but is not limited to, forming a gate electrode groove in a semiconductor substrate, the gate electrode groove having first and second side surfaces facing to each other, the gate electrode groove extending in a first direction; forming a gate insulating film on the first and second side surfaces of the gate electrode groove; forming a gate electrode which buries the gate electrode groove, the gate electrode covering the gate electrode; forming a first impurity diffusion region in the semiconductor substrate, the first impurity diffusion region covering the top of the gate insulating film disposed on the first side surface; and forming a second impurity diffusion region in the semiconductor substrate, the second impurity diffusion region covering the top of the gate insulating film disposed on the second side surface.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing the present invention, the related art will be explained, in order to facilitate the understanding of the present invention.

In the DRAM having the trench gate transistor disclosed in Japanese Patent Laid-open Publication No. 2006-339476 and Japanese Patent Laid-open Publication No. 2007-081095, a channel region of the transistor is formed in three surfaces, i.e., both side surfaces and a bottom of the trench.

The inventor has found that if the transistor having this configuration is further miniaturized, on current of the transistor is not sufficiently secured and normal operation of the DRAM is obstructed. This is caused by high channel resistance due to a channel region of the transistor being formed in the three surfaces constituting the trench, as described above.

Further, if an arrangement pitch of a trench gate becomes small, when a transistor is operated, an operation state of the transistor interferes with another adjacent transistor. Accordingly, the transistor cannot be independently operated.

This can be caused by a channel region formed between adjacent trench gates.

Further, in a trench gate transistor, since a gate electrode is formed to protrude upward from a surface of the semiconductor substrate, the protruding gate electrode itself makes it greatly difficult to form a bit line or a capacitor to be formed in a subsequent process. Thus, it is difficult to fabricate a DRAM.

Accordingly, even in a DRAM including a transistor using a trench, there is a need for a semiconductor device and a fabrication method thereof in which on current of the transistor is sufficiently secured and operation interference of an adjacent transistor is avoided to thereby resolve the difficulty of fabrication.

The inventor has newly found that if a memory cell of a DRAM (Dynamic Random Access Memory) is miniaturized, an interval between two adjacent cells provided in one active region becomes small, and, as a result, a disturbance defect between adjacent cells (hereinafter referred to simply as “disturbance defect”), in which, when one cell accumulates data “0,” the other cell accumulates data “1,” and the cell accumulating data “0” is continuously accessed, accumulated data in the cell accumulating the data “1” is destructed, is generated. This disturbance defect causes degradation of the reliability of a semiconductor device.

FIG. 42is a plan view showing an example of a layout of a conventional DRAM, andFIG. 43is a cross-sectional view taken along a line Z-Z of the DRAM shown inFIG. 42.

Next, the above-described disturbance defect found by the inventor will be described with reference toFIGS. 42 and 43.

Referring toFIG. 42, a plurality of regularly arranged active regions302are provided in a surface of a semiconductor substrate301. Each active region302is surrounded by an element isolation region303in which a trench formed in the surface of the semiconductor substrate301is buried with an insulating film. In a Y direction intersecting the active region302, a plurality of word lines WL extending in the Y direction are arranged.

Referring toFIG. 43, word lines WL1and WL2are formed by burying trenches provided across the plurality of active regions302and the element isolation region303in the surface of the semiconductor substrate301through a gate insulating film305.

On upper surfaces of the word lines WL1and WL2, a cap insulating film306is formed to bury the trenches. In one active region302, two word lines consisting of the word line WL1and the word line WL2are provided to intersect each other.

The two word lines WL1and WL2constitute gate electrodes of two corresponding transistors Tr1and Tr2, respectively. The transistor Tr1includes a drain diffusion layer307and a source diffusion layer308, in addition to the gate electrode consisting of the word line WL1.

Further, the transistor Tr2includes a drain diffusion layer312and the source diffusion layer308, in addition to the gate electrode consisting of the word line WL2. The source diffusion layer308is common to the transistors Tr1and Tr2, and is connected to a bit line BL at a bit line contact311.

Meanwhile, the drain diffusion layers307and312are connected to lower electrodes313and314(storage nodes) via capacitive contact plugs310formed in an interlayer insulating film309, respectively.

The lower electrodes313and314constitute capacitive elements316and317together with a capacitive insulating film and an upper electrode, which are not shown, respectively. The surface of the semiconductor substrate301corresponding to a bottom and two opposing side surfaces of the trenches buried with the word lines are channels of the transistors Tr1and Tr2.

For example, if the word line WL1is in an on state to form the channel of the transistor Tr1and a potential at a low (L) level is applied to the bit line319, the lower electrode313enters an “L” state. Then, the word line WL1is transferred to an off state to thereby accumulate L (data “0”) information in the lower electrode313.

Furthermore, for example, if the word line WL2is in an on state to form the channel of the transistor Tr2and a potential at a high (H) level is applied to the bit line319, the lower electrode314enters an H state. Then, the word line WL2is transferred to an off state to thereby accumulate H (data “1”) information in the lower electrode314.

Furthermore, for example, if the word line WL2is in an on state to form the channel of the transistor Tr2and a potential at a high (H) level is applied to the bit line319, the lower electrode314enters an H state. Then, the word line WL2is transferred to an off state to thereby accumulate H (data “1”) information in the lower electrode314.

As a result, electrons e− induced in the channel of the transistor Tr1reach the adjacent drain diffusion layer312, such that H information accumulated in the lower electrode314is destructed and the state is changed to the L state.

That is, a mode defect, which indicates that the data “1” is changed into the data “0,” is generated. This defect depends on the number of on/off times of the word line WL1. For example, if the number of on/off times is 10000, one of a plurality of cells is destroyed, and if the number of on/off times is 100000, ten cells are destroyed.

Originally, adjacent cells must independently hold information. However, if a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, is generated, a normal operation of the semiconductor device (DRAM) is obstructed and reliability is degraded.

This disturbance defect is not problematic when a cell is large, that is, when an interval L between the word line WL1and the word line WL2, which is defined as a minimum processing dimension F as shown inFIG. 42, is 70 nm.

However, if the memory cell is reduced and the interval between the word line WL1and the word line WL2becomes smaller than 50 nm, the disturbance defect is noticeable. Further, such a small interval causes a severer problem.

In one embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove having first and second side walls facing to each other; a first gate insulating film covering the first and second side walls of the first gate groove; a first gate electrode on the first gate insulating film, the first gate electrode being in a lower portion of the first gate groove; a first burying insulating film that buries the first gate groove, the first burying insulating film covering the first gate electrode; a first diffusion region adjacent to a first upper portion of the first gate insulating film, the first upper portion being on an upper portion of the first side wall of the first gate groove; and a second diffusion region in contact with an entire portion of the second side wall of the first gate groove.

In some cases, the semiconductor substrate further includes a second gate groove having third and fourth side walls facing to each other, and the second diffusion region is disposed between the first and second gate grooves, the second diffusion region being adjacent to the first and second gate grooves.

In some cases, the second diffusion region fills entirely in an interposed region of the semiconductor substrate between the first and second gate grooves.

In some cases, the semiconductor device may further include, but is not limited to, a second gate insulating film covering the third and fourth side walls of the second gate groove; a second gate electrode on the second gate insulating film, the second gate electrode being in an upper portion of the second gate groove; and a second burying insulating film that buries the second gate groove, the second burying insulating film covering the second gate electrode.

In some cases, the second diffusion region has a bottom portion which is lower than bottoms of the first and second gate grooves.

In some cases, the second diffusion region includes first and second regions which are united with each other, the first region being adjacent to the bottoms of the first and second gate grooves, and the second region filling entirely in an interposed region of the semiconductor substrate between the first and second gate grooves.

In some cases, the first and second gate grooves extend in a first direction in the semiconductor substrate.

In some cases, the semiconductor device may further include, but is not limited to, first isolation regions in the semiconductor substrate, the first isolation regions extending in a second direction crossing the first direction, the first isolation regions defining at least an active region of the semiconductor substrate; and second isolation regions in the semiconductor substrate, the second isolation regions extending in the first direction, the second isolation regions dividing the at least an active region into a plurality of device formation regions.

In some cases, the first region of the second diffusion region is a layered region, the first and second isolation regions have bottoms which are deeper than bottom of the first region of the second diffusion region, the first and second isolation regions divide the first region of the second diffusion region into a plurality of regions.

In some cases, the second isolation regions have bottoms which are substantially the same level as the bottoms of the first and second gate electrode grooves.

In some cases, the semiconductor device may further include, but is not limited to, third diffusion regions around the bottoms of the fourth regions, the third diffusion regions being the same in conductivity type as the semiconductor substrate, the third diffusion regions being higher in impurity concentration than the semiconductor substrate, the third diffusion regions contacting the first region of the second diffusion region.

In some cases, the first isolation region includes a first insulating film which buries in a first isolation groove extending in the second direction and in the semiconductor substrate.

In some cases, the second isolation region includes a second insulating film which buries in a second isolation groove extending in the first direction and in the semiconductor substrate.

In some cases, the semiconductor device may further include, but is not limited to, a bit line electrically coupled to the second diffusion region, the bit line extending in a direction crossing an extension direction of the gate electrode.

In some cases, the semiconductor device may further include, but is not limited to, an inter-layer insulating film over the first burying insulating film; a contact plug contacting the first diffusion region, the contact plug being in the first burying insulating film and the interlayer insulating film; a contact pad over the interlayer insulating film, the contact pad contacting an upper surface of the contact plug; and a capacitor electrically coupled to the contact pad.

In another embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate having at least an active region that extends in a first direction, the semiconductor substrate having first and second gate electrode grooves; first and second isolation regions in the semiconductor substrate, the first and second isolation regions extending in a second direction, the first and second isolation regions extending across the at least active region to divide the at least active region into a plurality of device formation regions; first and second transistors disposed between the first and second isolation regions, the first and second transistors being aligned and adjacent to each other in the first direction, the first and second transistors having first and second diffusion regions, respectively, the first and second transistors having a third diffusion region as a common diffusion region, the third diffusion region being disposed between the first and second gate electrode grooves; a bit line electrically coupled to the third diffusion region; first and second gate insulating films in the first and second gate electrode grooves; and first and second gate electrodes on the first and second gate insulating films, respectively, the first and second gate electrodes burying lower portions of the first and second gate electrode grooves. The first diffusion region is in the semiconductor substrate, the first diffusion region is disposed between the first isolation region and the first gate electrode groove, the first diffusion region has a first bottom which is higher in level than a top portion of the first gate electrode. The second diffusion region is in the semiconductor substrate, the second diffusion region is disposed between the second isolation region and the second gate electrode groove, the second diffusion region has a second bottom which is higher in level than a top portion of the second gate electrode. The first gate electrode groove has first and second side surfaces and a first bottom, the first side surface facing against the first isolation region, the second side surface being adjacent to the third diffusion region. The second gate electrode groove has third and fourth side surfaces and a second bottom, the third side surface facing against the second isolation region, the fourth side surface being adjacent to the third diffusion region. The third diffusion region fills entirely in an interposed region of the semiconductor substrate between the first and second gate grooves, the third diffusion region extending from an upper surface of the semiconductor substrate to the bottoms of the first and second gate electrode grooves. The first transistor has a first channel region between the first diffusion region and the bottom of the third diffusion region. The second transistor has a second channel region between the second diffusion region and the bottom of the third diffusion region.

In some cases, the first channel region extends from the bottom of the first diffusion region along the first side surface of the first gate electrode groove, and the second channel region extends from the bottom of the second diffusion region along the third side surface of the second gate electrode groove.

In some cases, the third diffusion region include first and second regions united with each other, the first region extends entirely in an interposed region between the first and second gate electrode grooves and from the upper surface of the semiconductor substrate to a deep portion between the bottoms of the first and second gate electrode grooves, the second region extending between the bottoms of the first and second gate electrode grooves, the second region contacting the bottoms of the first and second gate electrode grooves, the second region is a lowered region, the first channel region extends between the bottom of the first diffusion region to the second region of the third diffusion region, and the second channel region extends between the bottom of the second diffusion region to the second region of the third diffusion region.

In some cases, the first and second isolation regions have bottoms which are deeper than the bottom of the third diffusion region, and the third diffusion region is divided by the first and second isolation regions into a plurality of diffusion regions.

In some cases, the semiconductor device may further include, but is not limited to, fourth diffusion regions around the bottoms of the first and second isolation regions, the fourth diffusion regions being the same in conductivity type as the semiconductor substrate, the fourth diffusion regions being higher in impurity concentration than the semiconductor substrate, the fourth diffusion regions contacting the second region of the third diffusion region.

In still another embodiment, a method of forming a semiconductor device may include, but is not limited to, forming a gate electrode groove in a semiconductor substrate, the gate electrode groove having first and second side surfaces facing to each other, the gate electrode groove extending in a first direction; forming a gate insulating film on the first and second side surfaces of the gate electrode groove; forming a gate electrode which buries the gate electrode groove, the gate electrode covering the gate electrode; forming a first impurity diffusion region in the semiconductor substrate, the first impurity diffusion region covering the top of the gate insulating film disposed on the first side surface; and forming a second impurity diffusion region in the semiconductor substrate, the second impurity diffusion region covering the top of the gate insulating film disposed on the second side surface.

In some cases, the method may further include, but is not limited to, forming, before forming the gate electrode groove, first isolation grooves in the semiconductor substrate, the first isolation grooves extending in a second direction crossing the first direction; forming first isolation insulating films which buries the first isolation grooves to form first isolation regions defining active regions; forming second isolation grooves in the semiconductor substrate, the second isolation grooves extending in the first direction; and forming second isolation insulating films which buries the second isolation grooves to form second isolation regions dividing the active regions into a plurality of device formation regions. Forming the gate electrode grooves includes forming the gate electrode grooves each of which being disposed between the second isolation regions. The second diffusion region is formed by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into portions of the semiconductor substrates between the gate electrode grooves to form the second diffusion region.

In some cases, the second diffusion region is formed to have a bottom portion which is lower than the bottoms of the gate electrode grooves.

In some cases, the method may further include, but is not limited to, forming, before forming the gate electrode grooves, grooves in the semiconductor substrate, the grooves extending in a second direction crossing the first direction, the grooves having the same depth as the gate electrode grooves; making the grooves deeper to form the first isolation grooves; forming first isolation insulating films which bury the first isolation grooves to form first isolation regions defining active regions; forming second isolation grooves in the semiconductor substrate, the second isolation grooves extending in the first direction; forming second isolation insulating films which bury the second isolation grooves to divide the active regions into a plurality of device isolation regions; forming, before forming the first isolation insulating film, a first region in the form of a layer in the semiconductor substrate by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into the bottoms of the grooves; and forming a second region between the gate electrode grooves and contacting the first region by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into a portion in the semiconductor substrate between the gate electrode grooves, to form the second diffusion region. The gate electrode grooves are formed so that the bottoms of the gate electrode grooves are covered by the first region.

In some cases, the method may further include, but is not limited to, forming, before forming the gate electrode grooves, first isolation grooves in the semiconductor substrate, the first isolation grooves extending in a second direction crossing the first direction; forming first isolation insulating films which bury the first isolation grooves to form first isolation regions defining active regions; forming second isolation grooves in the semiconductor substrate, the second isolation grooves extending in the first direction; forming second isolation insulating films which bury the second isolation grooves to divide the active regions into a plurality of device isolation regions; forming, before forming the first isolation insulating film, a first region in the form of a layer in the semiconductor substrate by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into entirely a main surface of the grooves; and forming a second region between the gate electrode grooves and contacting the first region by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into a portion in the semiconductor substrate between the gate electrode grooves, to form the second diffusion region. The gate electrode grooves are formed so that the bottoms of the gate electrode grooves are covered by the first region.

In some cases, the method may further include, but is not limited to, forming, before forming the gate electrode grooves, first isolation grooves in the semiconductor substrate, the first isolation grooves extending in a second direction crossing the first direction; forming first isolation insulating films which bury the first isolation grooves to form first isolation regions defining active regions; forming second isolation grooves in the semiconductor substrate, the second isolation grooves extending in the first direction, the second isolation grooves having the same depth as the gate electrode grooves; forming second isolation insulating films which bury the second isolation grooves to divide the active regions into a plurality of device isolation regions; forming, before forming the second isolation insulating film, third diffusion regions around the bottoms of the second isolation grooves by carrying out an ion implantation of an impurity of the same conductivity type as the semiconductor substrate at a higher impurity concentration than the semiconductor substrate; forming, before forming the gate electrode, a first region in the form of a layer in the semiconductor substrate by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into the bottoms of the gate electrode grooves; and forming a second region between the gate electrode grooves and contacting the first region by carrying out a selective ion implantation of an impurity of a different conductivity type from the semiconductor substrate into a portion in the semiconductor substrate between the gate electrode grooves, to form the second diffusion region.

In some cases, the method may further include, but is not limited to, forming a bit line electrically coupled to the second diffusion region, the bit line extending in a direction crossing an extension direction of the gate electrode, the bit line extending over the second diffusion region between the gate electrode grooves.

In some cases, the method may further include, but is not limited to, forming an inter-layer insulating film over the buried insulating film; forming a contact plug contacting the first diffusion region, the contact plug being in the first burying insulating film and the interlayer insulating film; forming a contact pad over the interlayer insulating film, the contact pad contacting an upper surface of the contact plug; and forming a capacitor electrically coupled to the contact pad.

Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the accompanying drawings. Further, drawings used in the following description are for explaining configurations of the embodiments of the present invention, and a size, a thickness, or a dimension of each shown portion may differ from that of a real semiconductor device.

First Embodiment

FIG. 1is a schematic plan view of a memory cell array provided in a semiconductor device according to a first embodiment of the present invention, and FIG.2is a cross-sectional view taken along a line A-A of the memory cell array shown inFIG. 1.

InFIGS. 1 and 2, a DRAM (Dynamic Random Access Memory) is described as an example of the semiconductor device10of the first embodiment. Further, inFIG. 1, an example of a layout of a memory cell array of the DRAM is shown.

InFIG. 1, an X direction indicates a direction in which a bit line34extends, and a Y direction indicates a direction (a second direction) in which a gate electrode22and a second element isolation region17, which intersects the X direction, extend.

InFIG. 1, for convenience of explanation, among components of the memory cell array11, only a semiconductor substrate13, a first element isolation region14, an active region16, a second element isolation region17, a gate electrode trench18, a gate electrode22, the bit line34, a capacitive contact plug42, a capacitive contact pad44, and a plurality of element forming regions R are shown, and other components of the memory cell array11are not shown.

InFIG. 2, in fact, the bit line34extending in the X direction shown inFIG. 1is schematically shown. InFIG. 2, the same components as those of the semiconductor device10shown inFIG. 1are assigned the same reference numerals.

The semiconductor device10of the first embodiment includes a memory cell region in which the memory cell array11shown inFIGS. 1 and 2is formed, and a peripheral circuit region (a region in which a peripheral circuit is formed; not shown) arranged around the memory cell region.

Referring toFIGS. 1 and 2, the memory cell array11provided in the semiconductor device10of the first embodiment includes a semiconductor substrate13, a first element isolation region14, an active region16having a plurality of element forming regions R, a second element isolation region17, a gate electrode trench18, first and second transistors19-1and19-2, a gate insulating film21, a buried gate electrode22, a buried insulating film24, a mask insulating film26, a first impurity diffusion region28, a second impurity diffusion region29, an aperture32, a bit line contact plug33, a bit line34, a cap insulating film36, a sidewall film37, an interlayer insulating film38, a contact hole41, a capacitive contact plug42, a capacitive contact pad44, a silicon nitride film46, and a capacitor48.

Referring toFIGS. 1 and 2, the semiconductor substrate13is a plate-shaped substrate. For example, a p-type single-crystal silicon substrate may be used as the semiconductor substrate12. In this case, a p-type impurity concentration of the semiconductor substrate13may be, for example, 1E16 atoms/cm2.

Referring toFIG. 1, the first element isolation region14includes a first element isolation trench51and a first element isolation insulating film52.

The first element isolation trench51is formed in the semiconductor substrate13to extend in a direction (a second direction) tilted at a given angle with respect to the X direction shown inFIG. 1. A plurality of first element isolation trenches51are formed at given intervals with respect to the Y direction shown inFIG. 1. A depth of the first element isolation trench51may be, for example, 250 nm.

The first element isolation insulating film52is arranged to bury the first element isolation trench51. Although not shown, an upper surface of the first element isolation insulating film52is flush with the main surface13aof the semiconductor substrate13. For example, a silicon oxide film (SiO2film) may be used as the first element isolation insulating film52.

The first formed element isolation region14extends in a band shape in the second direction and partitions the active region16.

Referring toFIGS. 1 and 2, the second element isolation region17includes a second element isolation trench54, and a second element isolation insulating film55. The second element isolation trench54is formed in the semiconductor substrate13to extend in the Y direction (the first direction) shown inFIG. 1. Accordingly, the second element isolation trench54partitions part of the first element isolation region14. The second element isolation trench54is formed to be sandwiched between two gate electrodes22arranged to be adjacent to each other.

Each gate electrode22constitutes the word line of the memory cell. That is, in the memory cell of the present embodiment, one second element isolation region17and two gate electrodes22(word line) extending in the Y direction are paired and repeatedly arranged in the X direction.

The depth of the second element isolation trench54may be, for example, 250 nm.

The second element isolation insulating film55is arranged to bury the second element isolation trench54and the aperture26A formed in the mask insulating film26. The upper surface55aof the second element isolation insulating film55is flush with the upper surface26aof the mask insulating film26. For example, a silicon oxide film (SiO2film) may be used as the second element isolation insulating film55.

The second formed element isolation region17partitions a plurality of element forming regions R in the second direction.

Thus, the first element isolation region14formed by burying the first element isolation trench51formed in the semiconductor substrate13with the first element isolation insulating film52, and the second element isolation region17formed by burying the second element isolation trench54formed in the semiconductor substrate13with the second element isolation insulating film55are provided to thereby partition the active region16into a plurality of element forming regions R. Accordingly, the first and second transistors19-1and19-2can be easily turned on and a data retention characteristic of the memory cell array11can be improved so that a potential of the dummy gate electrode does not adversely affect the first and second transistors19-1and19-2, in comparison with a case in which a dummy gate electrode (not shown) to which a negative potential is applied through the gate insulating film21is provided in the second element isolation trench54to partition a plurality of element forming regions R.

Referring toFIGS. 1 and 2, the two gate electrode trenches18are provided to extend in the Y direction in the semiconductor substrate13located between the two second element isolation regions17. The gate electrode trench18is partitioned by inner surfaces consisting of a bottom18cand first and second opposing side surfaces18aand18b. The two gate electrode trenches18are arranged so that the second side surfaces18bface each other.

A depth of the gate electrode trench18is smaller than that of the first and second element isolation trenches51and54(a depth of the first and second element isolation regions14and17). If the depth of the first and second element isolation trenches51and54is 250 nm, the depth of the gate electrode trench18may be, for example, 150 nm.

Referring toFIG. 2, the first and second transistors19-1and19-2are trench gate transistors, each including a gate insulating film21, a gate electrode22, a buried insulating film24, a first impurity diffusion region28, and a second impurity diffusion region29.

As shown inFIG. 2, the first and second transistors19-1and19-2are arranged to be adjacent to each other. The second impurity diffusion region29functions as a common impurity diffusion region (a drain region in the structure shown inFIG. 2) of the first and second transistors19-1and19-2.

That is, the second side surface18bof the gate electrode trench18constituting the first transistor19-1, and the second side surface18bof the gate electrode trench18constituting the second transistor19-2face each other via the second impurity diffusion region29.

Referring toFIG. 2, the gate insulating film21is provided to cover the first and second side surfaces18aand18bof the gate electrode trench18and the bottom18cof the gate electrode trench18. For example, a silicon oxide film (SiO2film) of a single layer, a film (SiON film) formed by nitration of a silicon oxide film, a stacked silicon oxide film (SiO2film), a stacked film formed by stacking a silicon nitride film (SiN film) on a silicon oxide film (SiO2film), or the like may be used as the gate insulating film21.

If the silicon oxide film (SiO2film) of the single layer is used as the gate insulating film21, a thickness of the gate insulating film21may be, for example, 5 nm.

Referring toFIG. 2, the gate electrode22is arranged to bury a lower portion of the gate electrode trench18through the gate insulating film21. Accordingly, an upper surface22aof the gate electrode22is arranged in a position lower than a main surface13aof the semiconductor substrate13. The gate electrode22may have, for example, a stacked structure formed by sequentially stacking a titanium nitride film and a tungsten film.

Referring toFIG. 2, the buried insulating film24is arranged to bury the gate electrode trench18in which the gate insulating film21is formed, in order to cover the upper surface22aof the gate electrode22.

Further, an upper portion of the buried insulating film24protrudes from the main surface13aof the semiconductor substrate13, and an upper surface24aof the protruding portion is flush with the upper surface26aof the mask insulating film26. A silicon oxide film (SiO2film) may be used as the buried insulating film24.

Referring toFIG. 2, the mask insulating film26is provided on the upper surface28aof the first impurity diffusion region28. The mask insulating film26has a trench-shaped aperture26A formed on the second element isolation trench54. The mask insulating film26functions as an etching mask when the second element isolation trench54is formed in the semiconductor substrate13by anisotropic etching. A silicon nitride film is used as the mask insulating film26. In this case, a thickness of the mask insulating film26may be, for example, 50 nm.

Referring toFIG. 2, the first impurity diffusion region28is provided in the semiconductor substrate13located at a side of the first side surface18ato cover the upper portion21A of the gate insulating film21formed in the first side surface18aof the gate electrode trench18.

That is, the first side surface18aof the gate electrode trench18constituting the first transistor19-1and the first side surface18aof the gate electrode trench18constituting the second transistor19-2face the side surface of the second element isolation trench54via the semiconductor substrate13.

Accordingly, the first impurity diffusion region28includes the upper surface13aof the semiconductor substrate13sandwiched between the first side surface18aand the second element isolation trench54, and is provided to cover the upper portion21A of the gate insulating film21formed on the first side surface18a.

The bottom28bof the first impurity diffusion region28is arranged in a higher position than the upper surface22aof the gate electrode22buried in the gate electrode trench18(a position at a side of the upper surface13aof the semiconductor substrate13). A distance between a horizontal line including the bottom28bof the first impurity diffusion region28and a horizontal line including the upper surface22aof the buried gate electrode22is preferably less than 10 nm.

The first impurity diffusion region28is provided for the respective gate electrodes22constituting the first and second transistors19-1and19-2.

The first impurity diffusion region28is an impurity diffusion region functioning as the source/drain region (a source region in the structure shown inFIG. 2) of the first and second transistors19-1and19-2. If the semiconductor substrate13is a p-type silicon substrate, the first impurity diffusion region28is formed by ion-implanting n-type impurities into the semiconductor substrate13.

Referring toFIG. 2, the second impurity diffusion region29is provided in an entire portion of the semiconductor substrate13arranged between the two gate electrode trenches18. Accordingly, the second impurity diffusion region29is arranged to cover the entire gate insulating film21provided on the second side surfaces18bof the two gate electrode trenches18.

Further, a bottom of the second impurity diffusion region29protrudes downward from the bottoms18cof the two gate electrode trenches18.

Thus, the second impurity diffusion region29provided in an entire portion of the semiconductor substrate13arranged between the two gate electrode trenches18and having a bottom protruding downward from the bottoms18cof the two gate electrode trenches18is provided such that a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the bottom of the second impurity diffusion region29containing the n-type impurities, and thus the electrons e− induced in the channel of the first transistor19-1can be suppressed from reaching the second impurity diffusion region29(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect when an accumulation state of one cell is changed due to an operation state of the other adjacent cell can be suppressed so that H information resulting from the electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, generation of the disturbance defect can be suppressed.

The second impurity diffusion region29functions as the first and second common source/drain region (a drain region in the structure shown inFIG. 2) to the transistors19-1and19-2. If the semiconductor substrate13is a p-type silicon substrate, the second impurity diffusion region29is formed by ion-implanting n-type impurities into the semiconductor substrate13.

Thus, the first impurity diffusion region28including the upper surface13aof the semiconductor substrate13sandwiched between the first side surface18aand the second element isolation trench54and covering the upper portion21A of the gate insulating film21arranged on the first side surface18a, and the second impurity diffusion region29arranged in an entire portion of the semiconductor substrate13located between the two gate electrode trenches18and covering the entire gate insulating film21arranged on the second side surfaces18bof the two gate electrode trenches18are provided. Accordingly, when the first and second transistors19-1and19-2are operated, the channel region is formed only in the semiconductor substrate13contacting a lower portion of the gate insulating film21arranged on the first side surface18aand the semiconductor substrate13constituting the bottom18cof the gate electrode trench18. Thus, the channel region is not provided in the semiconductor substrate13contiguous to the second side surface18b, that is, between the first and second transistors19-1and19-2.

That is, only two surfaces of the one side surface (the first side surface18a) and a bottom (bottom18c) among three surfaces constituting the gate electrode trench18may be a channel region, and the other side surface (the second side surface18b) may not be the channel region.

Accordingly, when the first and second transistors19-1and19-2are in an on state, a channel region in which on current flows can be reduced in comparison with a conventional transistor. Accordingly, even in a miniaturized memory cell, channel resistance can be reduced to increase on current.

Further, when one of the first and second transistors19-1and19-2operates, the other transistor can be suppressed from malfunctioning.

Accordingly, even when the semiconductor device10is miniaturized and the gate electrode22is arranged with a small pitch, the first and second transistors19-1and19-2can be operated independently and stably.

Referring toFIG. 2, the aperture32is formed between the buried insulating films24protruding from the two gate electrode trenches18. The aperture32is formed to expose an upper surface29aof the second impurity diffusion region29.

Referring toFIG. 2, the bit line contact plug33is provided to bury the aperture32and is integrally formed with the bit line34. The lower end of the bit line contact plug33contacts the upper surface29aof the second impurity diffusion region29. If the bit line34is formed of a stacked film by sequentially stacking a polysilicon film, a titanium nitride (TiN) film, and a tungsten (W) film, the bit line contact plug33can be formed of a polysilicon film.

Referring toFIG. 2, the bit line34is provided in the upper surface24aof the buried insulating film24and integrally formed with the bit line contact plug33. Accordingly, the bit line34is electrically connected with the second impurity diffusion region29via the bit line contact plug33.

A stacked film formed by sequentially stacking a polysilicon film, a titanium nitride film and a tungsten film, a polysilicon film, a titanium nitride film, or the like may be used as a material of the bit line34.

Referring toFIG. 2, the cap insulating film36is provided to cover an upper surface of the bit line34. The cap insulating film36protects the upper surface of the bit line34and functions as an etching mask when a base material that becomes the bit line34is patterned by anisotropic etching (specifically, dry etching). A stacked film formed by sequentially stacking a silicon nitride film (SiN film) and a silicon oxide film (SiO2film) may be used as the cap insulating film36.

Referring toFIG. 2, the sidewall film37is provided to cover a side surface of the bit line34. The sidewall film37has a function of protecting a sidewall of the bit line34. A stacked film formed by sequentially stacking a silicon nitride film (SiN film) and a silicon oxide film (SiO2film) may be used as the sidewall film37.

Referring toFIG. 2, the interlayer insulating film38is provided on the upper surface26aof the mask insulating film26and the upper surface55aof the second element isolation insulating film55. An upper surface38aof the interlayer insulating film38is flush with the upper surface36aof the cap insulating film36. For example, a silicon oxide film (SiO2film) formed using CVD (Chemical Vapor Deposition) or a coated insulating film (silicon oxide film (SiO2film)) formed using SOG (Spin on Glass) may be used as the interlayer insulating film38.

Referring toFIG. 2, the contact hole41is formed in the pad insulating film13, the buried insulating film24, and the interlayer insulating film38to expose part of the upper surface28aof the first impurity diffusion region28.

Referring toFIG. 2, the capacitive contact plug42is provided to bury the contact hole41. A lower end of the capacitive contact plug42contacts part of the upper surface28aof the first impurity diffusion region28. Accordingly, the capacitive contact plug42is electrically connected with the first impurity diffusion region28. An upper surface42aof the capacitive contact plug42is flush with the upper surface38aof the interlayer insulating film38. The capacitive contact plug42may be, for example, a stacked structure formed by sequentially stacking a titanium nitride film and a tungsten film.

Referring toFIG. 2, the capacitive contact pad44is provided on the upper surface38aof the interlayer insulating film38so that part of the capacitive contact pad44connects to the upper surface42aof the contact plug42. A lower electrode57forming a capacitor48is connected to the capacitive contact pad44.

Accordingly, the capacitive contact pad44electrically connects the contact plug42with the lower electrode57.

Referring toFIG. 1, the capacitive contact pad44is circular and arranged in a position different from the capacitive contact plug42in the Y direction. The capacitive contact pads44are arranged between the adjacent bit lines34in the X direction.

That is, the capacitive contact pads44are repeatedly arranged in a staggered arrangement, in which a center portion of the capacitive contact pad44is arranged on the gate electrode22or upward from the side surface of the gate electrode22at one interval in the Y direction. In other words, the capacitive contact pads44are arranged in a flock formation in the Y direction.

Referring toFIG. 2, the silicon nitride film46is provided on the upper surface38aof the interlayer insulating film38to surround an outer peripheral portion of the capacitive contact pad44.

One capacitor48is provided for each capacitive contact pad44.

Each capacitor48includes a lower electrode57, a capacitive insulating film62that is common to a plurality of lower electrodes57, and an upper electrode59that is common to the plurality of lower electrodes57.

The lower electrode57is provided on the capacitive contact pad44and connected with the capacitive contact pad44. The lower electrode57is crown-shaped. The capacitive insulating film58is provided to cover surfaces of the plurality of lower electrodes57exposed from the silicon nitride film46and the upper surface of the silicon nitride film46.

The upper electrode59is provided to cover a surface of the capacitive insulating film58. The upper electrode59is arranged to bury the inside of the lower electrode57in which the capacitive insulating film58is formed and spaces between the plurality of lower electrodes57. An upper surface59aof the upper electrode59is arranged upward from upper ends of the plurality of lower electrodes57.

The formed capacitor48is electrically connected with the first impurity diffusion region28via the capacitive contact pad44.

Further, an interlayer insulating film (not shown) covering the upper surface59aof the upper electrode59, a contact plug (not shown) provided in the interlayer insulating film, a wiring (not shown) connected with the contact plug, and the like may be provided.

The semiconductor device10according to an aspect of the first embodiment has the following configuration: The semiconductor device10includes the active region16consisting of the semiconductor substrate13and extending in the second direction, the plurality of second element isolation trenches54extending in the first direction across the active region16, the first and second transistors19-1and19-2provided between two of the second adjacent element isolation trenches54and arranged to be adjacent in the second direction, one second impurity diffusion region29shared between the first and second transistors19-1and19-2and connected to the bit line34, two gate electrode trenches18sandwiching the second impurity diffusion region29therebetween and provided at both sides of the second impurity diffusion region29, the gate insulating film21covering the inner surface of the two gate electrode trenches18, the gate electrode22burying the lower portion of each gate electrode trench18, and the two first impurity diffusion regions28connected to the capacitor48provided in the upper surface13aof the semiconductor substrate13between the second element isolation trenches54facing the gate electrode trenches18. The gate electrode trench18has the first side surface18afacing the second element isolation trench54, the second side surface18bfacing the first side surface18avia the second impurity diffusion region29, and the bottom18c. The first impurity diffusion region28includes the upper surface13aof the semiconductor substrate13sandwiched between the first side surface18aand the second element isolation trench54and has the bottom28bin a higher position than the upper surface22aof the gate electrode22. The second impurity diffusion region29has a configuration provided in an entire portion from the upper surface13aof the semiconductor substrate13sandwiched at the second side surface18bto the bottom18cof the gate electrode trench18. The semiconductor substrate13in a portion contiguous to the second side surface18bis not the channel regions of the first and second transistors19-1and19-2.

Further, a portion of the semiconductor substrate13located downward from the bottom28bof the first impurity diffusion region28and contiguous to the first side surface18aand a portion of the semiconductor substrate13contiguous to the bottom18cof the gate electrode trench18become channel regions of the first and second transistors19-1and19-2.

According to the semiconductor device of the first embodiment, the first impurity diffusion region28including the upper surface13aof the semiconductor substrate13sandwiched between the first side surface18aand the second element isolation trench54and having a bottom28bin a higher position than the upper surface22aof the gate electrode22, and the second impurity diffusion region29provided in an entire portion from the upper surface13aof the semiconductor substrate13sandwiched at the second side surface18bto the bottom18cof the gate electrode trench18are provided to thereby form the channel region in only two surfaces of the bottom18cof the gate electrode trench18and the first side surface18a. Accordingly, channel resistance can be reduced in comparison with a conventional semiconductor device in which a channel region is formed in three surfaces (two opposing side surfaces and a bottom) of a gate electrode trench. Thus, it is possible to sufficiently secure on current of the first and second transistors19-1and19-2.

Further, the two gate electrode trenches18are provided at both sides of the second impurity diffusion region29to sandwich the second impurity diffusion region29and the second impurity diffusion region29is provided in an entire portion from the upper surface13aof the semiconductor substrate13sandwiched at the second side surface18bto the bottom18cof the gate electrode trench18, such that the channel region is not formed between the two gate electrode trenches18.

Accordingly, in a case in which an arrangement pitch of the gate electrode trench18is small, the first and second transistors19-1and19-2can be independently operated so that, when one of the first and second transistors19-1and19-2is operated, an operation state of the transistor does not interfere with the other adjacent transistor.

Further, the gate electrode22arranged to bury the lower portion of the gate electrode trench18via the gate insulating film, and the buried insulating film24arranged to bury the gate electrode trench18and covering the upper surface22aof the gate electrode22are provided, so that the gate electrode22does not protrude upward from the surface13aof the semiconductor substrate13.

Accordingly, as in the present embodiment, when a DRAM is used as the semiconductor device10, the bit line34or the capacitor48, which is formed after the gate electrode22is formed, can be easily formed. Thus, it is possible to easily fabricate the semiconductor device10.

Further, the second impurity diffusion region29provided in an entire portion of the semiconductor substrate13arranged between the two gate electrode trenches18and having a bottom protruding downward from the bottoms18cof the two gate electrode trenches18is provided such that a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the bottom of the second impurity diffusion region29containing the n-type impurities. Thus, the electrons e− induced in the channel of the first transistor19-1can be suppressed from reaching the second impurity diffusion region29(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, which means that an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be suppressed so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be suppressed.

FIGS. 3A through 3C,FIGS. 4A through 4C,FIGS. 5A through 5C,FIGS. 6A through 6C,FIGS. 7A through 7C,FIGS. 8A through 8C,FIGS. 9A through 9C,FIGS. 10A through 10C,FIGS. 11A through 11C,FIGS. 12A through 12C,FIG. 13,FIG. 14, andFIG. 15are views showing a process of fabricating the memory cell array provided in the semiconductor device according to the first embodiment of the present invention.

FIG. 3Ais a plan view of a region in which the memory cell array is formed,FIG. 3Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 3A, andFIG. 3Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 3A.

FIG. 4Ais a plan view of a region in which the memory cell array is formed,FIG. 4Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 4A, andFIG. 4Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 4A.

FIG. 5Ais a plan view of a region in which the memory cell array is formed,FIG. 5Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 5A, andFIG. 5Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 5A.

FIG. 6Ais a plan view of a region in which the memory cell array is formed,FIG. 6Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 6A, andFIG. 6Cis a cross-sectional view taken along a line B-B of the structure shown in FIG.6A.

FIG. 7Ais a plan view of a region in which the memory cell array is formed,FIG. 7Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 7A, andFIG. 7Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 7A.

FIG. 8Ais a plan view of a region in which the memory cell array is formed,FIG. 8Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 8A, andFIG. 8Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 8A.

FIG. 9Ais a plan view of a region in which the memory cell array is formed,FIG. 9Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 9A, andFIG. 9Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 9A.

FIG. 10Ais a plan view of a region in which the memory cell array is formed,FIG. 10Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 10A, andFIG. 10Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 10A.

FIG. 11Ais a plan view of a region in which the memory cell array is formed,FIG. 11Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 11A, andFIG. 11Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 11A.

FIG. 12Ais a plan view of a region in which the memory cell array is formed,FIG. 12Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 12A, andFIG. 12Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 12A.

First, in a process shown inFIGS. 3A through 3C, a pad oxide film65is formed on the main surface13aof the semiconductor substrate13. Next, a trench-shaped silicon nitride film66having apertures66ais formed on the pad oxide film65. As shown inFIG. 3A, the apertures66aextend in a band shape in a direction (a second direction) tilted at a given angle in an X direction and are formed at given intervals in a Y direction.

In this case, the apertures66aare formed to expose an upper surface of the pad oxide film13corresponding to a forming region of a first element isolation trench51. The apertures66aare formed by forming photoresist (not shown) patterned on the silicon nitride film66and etching the silicon nitride film66through anisotropic etching using the photoresist as a mask. The photoresist is removed after the apertures66aare formed.

Next, the semiconductor substrate13is etched by anisotropic etching (specifically, dry etching) using the silicon nitride film66having the apertures66aas a mask to thereby form the first element isolation trench51extending in the second direction.

A width W1of the first element isolation trench51may be, for example, 43 nm. A depth D1of the first element isolation trench51(a depth from the main surface13aof the semiconductor substrate13) may be, for example, 250 nm.

Next, in a process shown inFIGS. 4A through 4C, the first element isolation insulating film52burying the first element isolation trench51is formed.

Specifically, the first element isolation trench51is buried with a silicon oxide film (SiO2film) formed using an HDP (High Density Plasma) method or a coated silicon oxide film (SiO2film) formed using an SOG method

Then, a silicon oxide film (SiO2) formed upward from the upper surface of the silicon nitride film66silicon oxide film (SiO2film) is removed by a CMP (Chemical Mechanical Polishing) method to thereby form a first element isolation insulating film52consisting of a silicon oxide film (SiO2film) in the first element isolation trench51.

Accordingly, the first element isolation region14consisting of the first element isolation trench51and the first element isolation insulating film52and partitioning a band-shaped active region16extending in the second direction is formed.

Next, in a process shown inFIGS. 5A through 5C, the silicon nitride film66shown inFIGS. 4A through 4Cis removed, and then the pad oxide film65is removed. Specifically, the silicon nitride film66is removed by thermal phosphoric acid and then the pad oxide film65is removed by HF (hydrogen fluoride) etchant. Accordingly, the band-shaped active region16is exposed.

Next, part of the first element isolation insulating film52protruding from the main surface13aof the semiconductor substrate13is removed to thereby make the upper surface52aof the first element isolation insulating film52flush with the main surface13aof the in the semiconductor substrate13. Removal of the first element isolation insulating film52protruding from the main surface13aof the semiconductor substrate13is performed, for example, by wet etching.

Next, in a process shown inFIGS. 6A through 6C, the mask insulating film26having the trench-shaped aperture26A is formed in the main surface13aof the semiconductor substrate13and the upper surface52aof the first element isolation insulating film52shown inFIGS. 5A through 5C.

Specifically, the mask insulating film26is formed by forming a silicon nitride film (a base material of the mask insulating film26) covering the main surface13aof the semiconductor substrate13and the upper surface52aof the first element isolation insulating film52, forming photoresist (not shown) patterned on the silicon nitride film, and processing the aperture26A through anisotropic etching using the photoresist as a mask.

In this case, a plurality of apertures26A extend in a Y direction (a first direction) and are formed at given intervals in the X direction (seeFIG. 6A). Further, the apertures26A are formed to expose the main surface13aof the semiconductor substrate13corresponding to the forming region of the second element isolation trench54. The photoresist (not shown) is removed after the apertures26A are formed.

Next, the semiconductor substrate13is etched by anisotropic etching (specifically, dry etching) using the mask insulating film26having the aperture26A as a mask to thereby form the second element isolation trench54extending in the first direction.

The depth D2of the second element isolation trench54(a depth from the main surface13aof the semiconductor substrate13) may be, for example, 250 nm.

Next, the second element isolation insulating film55burying the second element isolation trench54is formed.

Specifically, the second element isolation trench54is buried with a silicon oxide film (SiO2film) formed by an HDP method or a coated silicon oxide film (SiO2film) formed by an SOG method.

Next, the insulating film formed upward from the upper surface26aof the mask insulating film26is removed using a CMP method to thereby form a second element isolation insulating film55having an upper surface55aformed of a silicon oxide film (SiO2film) and flush with the upper surface26aof the mask insulating film26in the second element isolation trench54.

Thereby, the second element isolation region17consisting of the second element isolation trench54and the second element isolation insulating film55and partitioning the band-shaped active region16shown inFIGS. 5A through 5Cinto a plurality of element forming regions R is formed.

Thus, after the first element isolation region14consisting of the first element isolation trench51formed in the semiconductor substrate13and the first element isolation insulating film52burying the first element isolation trench51and partitioning the band-shaped active region16is formed, the second element isolation region17consisting of the second element isolation trench54formed in the semiconductor substrate13and the second element isolation insulating film55burying the second element isolation trench54and partitioning the plurality of element forming regions R is formed. Accordingly, the first and second transistors19-1and19-2can be easily turned on and a data holding characteristic of the memory cell array11can be improved so that a potential of the dummy gate electrode does not adversely affect the first and second transistors19-1and19-2(seeFIG. 2), in comparison with a case in which a dummy gate electrode (not shown) to which a negative potential is applied through the gate insulating film21is provided in the second element isolation trench54to partition a plurality of element forming regions R.

Next, in a process shown inFIGS. 7A through 7C, two trench-shaped apertures26B extending in the Y direction are formed in the mask insulating film26located between the two second element isolation regions17.

In this case, the apertures26B are formed to expose the main surface13aof the semiconductor substrate13corresponding to the forming region of the gate electrode trench18. The apertures26B are formed by forming photoresist (not shown) patterned on the mask insulating film26and etching the mask insulating film26through anisotropic etching (specifically, dry etching) using the photoresist as a mask. The photoresist is removed after the apertures26B are formed.

Next, the semiconductor substrate13is etched by anisotropic etching (specifically, dry etching) using the mask insulating film26having the apertures26B as a mask to thereby form two gate electrode trenches18each having a bottom18cand first and second opposing side surfaces18aand18b.

In this case, the two gate electrode trenches18are formed so that second side surfaces18bface each other via the semiconductor substrate13(specifically, the semiconductor substrate13in a portion in which the second impurity diffusion region29is formed). Further, the depth D3of the gate electrode trench18(a depth from the main surface13aof the semiconductor substrate13) is smaller than the depths D1and D2of the first and second element isolation trenches51and54.

If the depths D1and D2of the first and second element isolation trenches51and54are 250 nm, the depth D3of the gate electrode trench18may be, for example, 150 nm.

Next, in a process shown inFIGS. 8A through 8C, a gate insulating film21covering the first and second side surfaces18aand18bof the gate electrode trench18and the bottom18cof the gate electrode trench18is formed. For example, a silicon oxide film (SiO2film) of a single layer, a film (SiON film) formed by nitriding a silicon oxide film, a stacked silicon oxide film (SiO2film), a stacked film formed by stacking a silicon nitride film (SiN film) on a silicon oxide film (SiO2film), or the like may be used as the gate insulating film21.

If a silicon oxide film (SiO2film) of a single layer is used as the gate insulating film21, the gate insulating film21may be formed by a thermal oxidation method. In this case, a thickness of the gate insulating film21may be, for example, 6 nm.

Next, the gate electrode22burying a lower portion of each gate electrode trench18through the gate insulating film21so that the upper surface22ais lower than the main surface13aof the semiconductor substrate13is formed.

Specifically, a titanium nitride film and a tungsten film are sequentially stacked, for example, by a CVD method to bury the gate electrode trench18, and then the titanium nitride film and the tungsten film are both etched back by dry etching so that the titanium nitride film and the tungsten film are left in a lower portion of the gate electrode trench18, to thereby form the gate electrode22consisting of the titanium nitride film and the tungsten film. Each gate electrode22constitutes the word line of the memory cell.

Next, a buried insulating film24covering the upper surface22aof the gate electrode22and burying the gate electrode trench18and the trench-shaped aperture26B is formed.

Specifically, an upper portion of the gate electrode trench18and the apertures26B are buried with an insulating film (e.g., silicon oxide film (SiO2film)) formed by an HDP method or a coated insulating film (e.g., silicon oxide film (SiO2film)) formed by an SOG method.

Next, the insulating film formed upward from the upper surface26aof the mask insulating film26is removed by a CMP method. Accordingly, a buried insulating film24consisting of the insulating film (e.g., silicon oxide film (SiO2film)) burying the gate electrode trench18and the apertures26B and having an upper surface24aflush with the upper surface26aof the mask insulating film26is formed.

Next, in a process shown inFIGS. 9A through 9C, phosphorus (P), which is impurities having a different conductivity type from the n-type impurities (a p-type silicon substrate that is a semiconductor substrate13e), is ion-implanted into in an entire upper surface of the structure shown inFIGS. 8A through 8Cunder conditions in which energy is 100 KeV and a dose amount is 1E14 atoms/cm2, to thereby form the first impurity diffusion region28in the semiconductor substrate13located between the gate electrode trench18and the first element isolation region17and form the impurity diffusion region71that is part of the second impurity diffusion region29in the semiconductor substrate13located between the two gate electrode trenches18.

Accordingly, the first impurity diffusion region28is formed in the semiconductor substrate13located at a side of the first side surface18aof the gate electrode trench18to cover the upper portion21A of the gate insulating film21formed on the first side surface18a.

In this case, the first impurity diffusion region28is formed to include the upper surface13aof the semiconductor substrate13sandwiched between the first side surface18aand the second element isolation trench54and to have a bottom28bburied in a higher position than the upper surface22aof the gate electrode22.

Further, a thickness of the mask insulating film26in this step may be, for example, 50 nm.

Next, in a process shown inFIGS. 10A through 10C, photoresist73having a trench-shaped aperture73aexposing the upper surface26aof the mask insulating film26located between the buried insulating films24is formed on the upper surface24aof the buried oxide film24, the upper surface26aof the mask insulating film26, and the upper surface55aof the second element isolation insulating film55.

Next, the mask insulating film26exposed from the aperture73ais removed by etching (wet etching or dry etching) using the photoresist73as a mask.

Accordingly, the upper surface71aof the impurity diffusion region71is exposed and part of the upper surface52aof the first element isolation insulating film52flush with the upper surface71aof the impurity diffusion region71is exposed.

Next, in a process shown inFIGS. 11A through 11C, phosphorus (P), which is impurities having a different conductivity type from the n-type impurities (a p-type silicon substrate that is a semiconductor substrate13e), is selectively ion-implanted into the impurity diffusion region71exposed from the photoresist73(in other words, the semiconductor substrate13in which the impurity diffusion region71has been formed) under conditions in which energy is 100 KeV and a dose amount is 1E14 atoms/cm2, to thereby form the second impurity diffusion region29in the entire semiconductor substrate13located between the two gate electrode trenches18.

Accordingly, the second impurity diffusion region29covering the entire gate insulating film21formed in the second side surfaces18bof the two gate electrode trenches18is formed in an entire portion of the semiconductor substrate13arranged between the two gate electrode trenches18, and the first and second transistors19-1and19-2each including the gate insulating film21, the gate electrode22, the buried insulating film24, the first impurity diffusion region28, and the second impurity diffusion region29are formed.

Thus, the first impurity diffusion region28covering the upper portion21A of the gate insulating film21arranged on the first side surface18ais formed and the second impurity diffusion region29covering the entire gate insulating film21arranged in the second side surfaces18bof the two gate electrode trenches18is formed in an entire portion of the semiconductor substrate13located between the two gate electrode trenches18. Accordingly, when the first and second transistors19-1and19-2shown inFIG. 2are operated, a channel region is formed only in the semiconductor substrate13contacting the lower portion of the gate insulating film21arranged on the first side surface18aand the semiconductor substrate13constituting the bottom18cof the gate electrode trench18, such that a channel region cannot be formed between the first and second transistors19-1and19-2.

That is, when the first and second transistors19-1and19-2are in an on state, a channel region in which on current flows can be reduced in comparison with a conventional transistor. Accordingly, even in the miniaturized memory cell, the channel resistance can be reduced to increase on current.

Further, when one of the first and second transistors19-1and19-2operates, the other transistor can be suppressed from malfunctioning. Accordingly, even when the semiconductor device10is miniaturized and the gate electrode22is arranged with a small pitch, the first and second transistors19-1and19-2can be operated independently and stably.

Further, in a process shown inFIGS. 11A through 11C, a bottom of the second impurity diffusion region29is formed to protrude downward from the bottoms18cof the two gate electrode trenches18.

Thus, since the bottom of the second impurity diffusion region29protrudes downward from the bottoms18cof the two gate electrode trenches18, a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− (not shown) induced in the channel of the first transistor19-1are trapped by the bottom of the second impurity diffusion region29containing the n-type impurities. Accordingly, the electrons e− induced in the channel of the first transistor19-1can be suppressed from reaching the second impurity diffusion region29(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be suppressed so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be suppressed.

Next, in a process shown inFIG. 13, the bit line contact plug33burying the aperture32and the bit line34arranged on the bit line contact plug33and extending in the X direction (seeFIG. 1) are formed en bloc.

Specifically, a polysilicon film, a titanium nitride film, and a tungsten film, which are not shown, are sequentially formed on the upper surface24aof the buried insulating film24to bury the aperture32(in this case, so that the polysilicon film buries the aperture32).

Next, a silicon nitride film (SiN film), which is not shown and is a base material of the cap insulating film36, is formed on the tungsten film that is not shown.

Then, photoresist (not shown) covering the forming region of the bit line34is formed on the silicon nitride film (SiN film) using photolithography technology.

Next, the silicon nitride film (SiN film), the tungsten film, the titanium nitride film, and the polysilicon film are patterned by anisotropic etching (specifically, dry etching) using the photoresist as a mask to thereby form, en bloc, the cap insulating film36constituting of the silicon nitride film (SiN film), the bit line contact plug33constituting of a polysilicon film and contacting the upper surface29aof the second impurity diffusion region29, and the bit line34arranged on the bit line contact plug33and consisting of a polysilicon film, a titanium nitride film, and a tungsten film.

Next, a silicon nitride film (SiN film) and a silicon oxide film (SiO2film) that are not shown are sequentially formed to cover the side surface of the bit line34, and the cap insulating film36, and then the silicon oxide film (SiO2film) and silicon nitride film (SiN film) are etched back over their entire surface to thereby form a sidewall film37that covers a side surface of the cap insulating film36and a side surface of the bit line34.

Thus, since the silicon nitride film (SiN film) and the silicon oxide film (SiO2film) are sequentially stacked to thereby form the sidewall film37, wettability of the silicon oxide film (coated insulating film) is enhanced when a coated insulating film (specifically, silicon oxide film (SiO2film)) is formed as the interlayer insulating film38using an SOG method. Thus, generation of voids in the silicon oxide film (coated insulating film) can be suppressed.

Next, the upper surface24aof the buried insulating film24, the upper surface26aof the mask insulating film26, and the upper surface55aof the second element isolation insulating film55are covered with the sidewall film37and an interlayer insulating film38having an upper surface38aflush with the upper surface36aof the cap insulating film36is formed. Accordingly, the upper surface36aof the cap insulating film36is exposed from the interlayer insulating film38.

Specifically, the upper surface24aof the buried insulating film24, the upper surface26aof the mask insulating film26, and the upper surface55aof the second element isolation insulating film55are coated with a coated insulating film (silicon oxide film (SiO2film)) using an SOG method so that the sidewall film37is covered, and then, heat treatment is performed to thereby make film quality of the silicon oxide film (coated insulating film) dense.

Further, when the silicon oxide film (coated insulating film) is formed using the SOG method, a coating liquid containing polysilazane is used. Further, the heat treatment may be performed in a steam atmosphere.

Next, polishing of the heat-treated silicon oxide film (coated insulating film) is performed using a CMP method until the upper surface36aof the cap insulating film36is exposed. Accordingly, the interlayer insulating film38having the upper surface38asubstantially flush with the upper surface36aof the cap insulating film36is formed.

Further, in a structure shown inFIG. 13, although not shown, a silicon oxide film (SiO2film) covering the upper surface36aof the cap insulating film36and the upper surface38aof the interlayer insulating film38may be formed using the CVD method after the silicon oxide film (coated insulating film) is polished.

Next, in a process shown inFIG. 14, the interlayer insulating film38, the mask insulating film26, the buried insulating film24, and the gate insulating film21are anisotropically etched (specifically, dry etched) using an SAC (Self Aligned Contact) method to thereby form a contact hole41, which exposes part of the upper surface28aof the first impurity diffusion region28.

In this case, dry etching is performed by a step of selectively etching the silicon oxide film (SiO2film) and a step of selectively etching the silicon nitride film (SiN film).

Next, a contact plug42having an upper surface42asubstantially flush with the upper surface38aof the interlayer insulating film38and a lower end contacting the upper surface28aof the first impurity diffusion region28is formed in the contact hole41.

Specifically, a titanium nitride film (not shown) and a tungsten film (not shown) are sequentially stacked using a CVD method to bury the contact hole41, and then unnecessary titanium nitride film and tungsten film formed on the upper surface38aof the interlayer insulating film38are removed through polishing using a CMP method to thereby form the contact plug42consisting of the titanium nitride film and the tungsten film in the contact hole41.

Next, a capacitive contact pad44contacting part of the upper surface42aof the capacitive contact plug42is formed on the upper surface38aof the interlayer insulating film38.

Specifically, a metal film (not shown) that is a base material of the capacitive contact pad44is formed to cover the upper surface36aof the cap insulating film36, the upper surface42aof the contact plug42, and the upper surface38aof the interlayer insulating film38.

Next, photoresist (not shown) covering a surface corresponding to the forming region of the capacitive contact pad44of an upper surface of the metal film is formed using photolithography technology. An unnecessary metal film exposed from the photoresist is then removed by dry etching using the photoresist as a mask to thereby form the capacitive contact pad44consisting of the metal film. After the capacitive contact pad44is formed, the photoresist (not shown) is removed.

Next, a silicon nitride film46covering the capacitive contact pad44is formed on the upper surface36aof the cap insulating film36, the upper surface42aof the contact plug42, and the upper surface38aof the interlayer insulating film38.

Next, in a process shown inFIG. 15, a silicon oxide film (SiO2film) that is not shown and has a great thickness is formed on the silicon nitride film46. The thickness of the silicon oxide film (SiO2film) may be, for example, 1500 nm.

Next, photoresist (not shown) patterned on the silicon oxide film (SiO2film) is formed using photolithography technology. A silicon oxide film (not shown) and the silicon nitride film46formed on the capacitive contact pad44are then etched by dry etching using the photoresist as a mask to thereby form a cylindrical hole (not shown) exposing the capacitive contact pad44. The photoresist (not shown) is then removed.

Next, a conductive film (e.g., titanium nitride film) is formed on an inner surface of the cylindrical hole (not shown) and an upper surface of the capacitive contact pad44to thereby form a crown-shaped lower electrode57that consists of the conductive film.

Next, the silicon oxide film (not shown) is removed using wet etching to thereby expose the upper surface of the silicon nitride film46. A capacitive insulating film58covering the upper surface of the silicon nitride film46and the lower electrode57is then formed.

Next, an upper electrode59is formed to cover the surface of the capacitive insulating film58. In this case, the upper electrode59is formed so that an upper surface59aof the upper electrode59is arranged upward from the capacitive insulating film58. Accordingly, a capacitor48consisting of the lower electrode57, the capacitive insulating film58, and the upper electrode59is formed on each capacitive contact pad44.

Thus, the semiconductor device10of the first embodiment is fabricated.

Further, in fact, an interlayer insulating film, a via, and a wiring that are not shown are formed on the upper surface59aof the upper electrode59.

According to the method of fabricating the semiconductor device of the first embodiment, the first impurity diffusion region28covering the upper portion21A of the gate insulating film21arranged on the first side surface18ais formed and the second impurity diffusion region29covering the entire gate insulating film21arranged on the second side surfaces18bof the two gate electrode trenches18is formed in an entire portion of the semiconductor substrate13located between the two gate electrode trenches18. Accordingly, when the first and second transistors19-1and19-2shown inFIG. 2are operated, the channel region is formed only in the semiconductor substrate13contacting the lower portion of the gate insulating film21arranged on the first side surface18a, and the semiconductor substrate13constituting the bottom18cof the gate electrode trench18, such that the channel region cannot be formed between the first and second transistors19-1and19-2.

That is, when the first and second transistors19-1and19-2are in an on state, a channel region in which on current flows can be reduced in comparison with a conventional transistor. Accordingly, even in the miniaturized memory cell, the channel resistance can be reduced to increase on current.

Further, when one of the first and second transistors19-1and19-2operates, the other transistor can be suppressed from malfunctioning. Accordingly, even when the semiconductor device10is miniaturized and the gate electrode22is arranged with a small pitch, the first and second transistors19-1and19-2can be operated independently and stably.

Further, the gate electrode22is formed to bury the lower portion of respective gate electrode trench18via the gate insulating film, and then the buried insulating film24covering the upper surface22aof the gate electrode22is formed to bury the gate electrode trench18. Accordingly, the gate electrode22does not protrude upward from the surface13aof the semiconductor substrate13.

Accordingly, as in the present embodiment, when a DRAM is fabricated as the semiconductor device10, the bit line34or the capacitor48formed after the gate electrode22is formed can be easily formed. Thus, it is possible to easily fabricate the semiconductor device10.

Further, in the first embodiment, although the case in which the silicon oxide film (SiO2film) is used as the buried insulating film24and the silicon nitride film (SiN film) is used as the mask insulating film26has been described by way of example, the silicon nitride film (SiN film) may be used as the buried insulating film24and the silicon oxide film (SiO2film) may be used as the mask insulating film26.

Accordingly, in a process shown inFIG. 14, when the contact hole41is formed, the silicon nitride film (SiN film), which is the buried insulating film24, functions as an etching stopper. Thereby, since the contact hole41does not expose the upper surface22aof the gate electrode22, the capacitive contact pad44and the gate electrode22can be prevented from being conducted via the contact plug42formed in the contact hole41.

Further, the bottom of the second impurity diffusion region29protrudes downward from the bottoms18cof the two gate electrode trenches18, such that a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the bottom of the second impurity diffusion region29containing the n-type impurities. Thus, electrons e− induced in the channel of the first transistor19-1can be suppressed from arriving at the second impurity diffusion region29(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be suppressed so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be suppressed.

Second Embodiment

FIG. 16is a cross-sectional view of a memory cell array provided in a semiconductor device according to a second embodiment of the present invention, and corresponds to a cross-section taken along a line A-A shown inFIG. 1.

InFIG. 16, a DRAM is described as an example of a semiconductor device80of the second embodiment. InFIG. 16, in fact, a bit line34extending in an X direction shown inFIG. 1is schematically shown. Further, inFIG. 16, the same components as the semiconductor device10of the first embodiment shown inFIG. 2are assigned the same reference numerals, and a description thereof will be omitted.

Referring toFIG. 16, the semiconductor device80of the second embodiment has the same configuration as the semiconductor device10except that the semiconductor device80includes a memory cell array81as an alternative to the memory cell array11provided in the semiconductor device10of the first embodiment.

The memory cell array81has the same configuration as the memory cell array11except that a second impurity diffusion region83is provided as an alternative to the second impurity diffusion region29provided in the memory cell array11, which has been described in the first embodiment.

That is, the first and second transistors19-1and19-2provided in the semiconductor device80of the second embodiment include the second impurity diffusion region83as an alternative to the second impurity diffusion region29, which has been described in the first embodiment.

The second impurity diffusion region83is a region formed by ion-implanting n-type impurities having a different conductivity type from the p-type silicon substrate, which is a semiconductor substrate13, into the semiconductor substrate13, and functions as a source/drain region (a drain region in the structure shown inFIG. 16).

The second impurity diffusion region83is an n-type impurity diffusion region that is common to the first and second transistors19-1and19-2, and includes a first region85and a second region86.

The first region85covers the gate insulating film21arranged on the bottom18cof the gate electrode trench18and is formed in a layer shape inside the semiconductor substrate13along a horizontal plane including the bottom18c. The first region85is divided into a plurality of regions by the first and second element isolation regions14and17formed to a deeper position than the first region85.

The second region86is formed in an entire portion of the semiconductor substrate13sandwiched between the two gate electrode trenches18and has the same configuration as the second impurity diffusion region29, which has been described in the first embodiment. The second region86reaches the first region85arranged downward from the second region86and is integrally formed with the first region85. The upper surface86aof the second region86coincides with the upper surface13aof the semiconductor substrate13and contacts the lower end of the bit line contact plug33. Accordingly, the second region86is electrically connected with the bit line34via the bit line contact plug33.

That is, the second impurity diffusion region83is provided to cover the gate insulating film21formed on the second side surfaces18band the bottoms18cof the two gate electrode trenches18.

Accordingly, the semiconductor substrate13in a portion contiguous to the second side surface18bof the gate electrode trench18, as well as the semiconductor substrate13in a portion contiguous to the bottom18cof the gate electrode trench18, is not the channel regions of the first and second transistors19-1and19-2.

Further, in the second embodiment, the case in which the n-type impurity diffusion region is used as the second impurity diffusion region83will be described by way of example.

According to the semiconductor device of the second embodiment, the second impurity diffusion region83is provided in the semiconductor substrate13to cover the gate insulating film21formed on the second side surfaces18band the bottoms18cof the two gate electrode trenches18, such that, when the first and second transistors19-1and19-2are operated, the channel region can be formed only in the semiconductor substrate13contacting the lower portion of the gate insulating film21arranged on the first side surface18. That is, only one surface (the first side surface18a) among the three surfaces of the gate electrode trench18(specifically, the first and second opposing side surfaces18aand18band the bottom18c) is the channel region, and the two other surfaces (the second side surfaces18band the bottom18c) are not the channel region.

Accordingly, when the first and second transistors19-1and19-2are in an on state, the channel region in which on current flows can be reduced in comparison with a conventional transistor. Thus, even in the miniaturized memory cell, the channel resistance can be reduced to increase the on current.

Further, when one of the first and second transistors19-1and19-2operates, the other transistor can be suppressed from malfunctioning.

Accordingly, even when the semiconductor device80is miniaturized and the gate electrode22is arranged with a small pitch, the first and second transistors19-1and19-2can be operated independently and stably.

Further, the second impurity diffusion region83consists of the first region85covering the gate insulating film21arranged on the bottom18cof the gate electrode trench18, provided in a layer shape inside the semiconductor substrate13along a horizontal plane including the bottom18cand divided into a plurality of regions by the first and second element isolation regions14and17, and the second region86provided in an entire portion of the semiconductor substrate13sandwiched between the two gate electrode trenches18, reaching the first region85arranged downward from the second region86, and integrally formed with the first region85. Accordingly, a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the first region85containing the n-type impurities. Thus, the electrons e− induced in the channel of the first transistor19-1can be prevented from reaching the second impurity diffusion region83(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be prevented so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be prevented.

FIGS. 17A through 17C,FIGS. 18A through 18C,FIGS. 19A through 19C,FIGS. 20A through 20C,FIGS. 21A through 21C,FIGS. 22A through 22C,FIGS. 23A through 23C,FIGS. 24A through 24C,FIGS. 25A through 25C,FIGS. 26A through 26C,FIGS. 27A through 27C,FIGS. 28A through 28C, andFIG. 29are views showing a process of fabricating a memory cell provided in a semiconductor device according to the second embodiment of the present invention.

FIG. 17Ais a plan view of a region in which the memory cell array is formed,FIG. 17Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 17A, andFIG. 17Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 17A.

FIG. 18Ais a plan view of a region in which the memory cell array is formed,FIG. 18Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 18A, andFIG. 18Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 18A.

FIG. 19Ais a plan view of a region in which the memory cell array is formed,FIG. 19Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 19A, andFIG. 19Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 19A.

FIG. 20Ais a plan view of a region in which the memory cell array is formed,FIG. 20Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 20A, andFIG. 20Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 20A.

FIG. 21Ais a plan view of a region in which the memory cell array is formed,FIG. 21Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 21A, andFIG. 21Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 21A.

FIG. 22Ais a plan view of a region in which the memory cell array is formed,FIG. 22Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 22A, andFIG. 22Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 22A.

FIG. 23Ais a plan view of a region in which the memory cell array is formed,FIG. 23Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 23A, andFIG. 23Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 23A.

FIG. 24Ais a plan view of a region in which the memory cell array is formed,FIG. 24Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 24A, andFIG. 24Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 24A.

FIG. 25Ais a plan view of a region in which the memory cell array is formed,FIG. 25Bis a cross-sectional view taken along a line A-A of a structure shown in FIG.25A, andFIG. 25Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 25A.

FIG. 26Ais a plan view of a region in which the memory cell array is formed,FIG. 26Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 26A, andFIG. 26Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 26A.

FIG. 27Ais a plan view of a region in which the memory cell array is formed,FIG. 27Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 27A, andFIG. 27Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 27A.

FIG. 28Ais a plan view of a region in which the memory cell array is formed,FIG. 28Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 28A, andFIG. 28Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 28A.

Further, the semiconductor device80of the second embodiment shown inFIG. 29corresponds to a cross-section of the semiconductor device80of the second embodiment shown inFIG. 16. Further, the line A-A shown inFIG. 17A,FIG. 18A,FIG. 19A,FIG. 20A,FIG. 21A,FIG. 22A,FIG. 23A,FIG. 24A,FIG. 25A,FIG. 26A,FIG. 27A, andFIG. 28Acorresponds to a cross-section of the semiconductor device80of the second embodiment shown inFIG. 16, which has been previously described.

First, in a process shown inFIGS. 17A through 17C, using the same technique as the process shown inFIGS. 3A through 3C, which has been described in the first embodiment, the pad oxide film65, the trench-shaped silicon nitride film66having the apertures66a, and the trench91are sequentially formed (seeFIGS. 3A through 3C).

In this case, the apertures66aare formed to expose the pad oxide film65corresponding to the forming region of the trench91.

Further, the trench91is part of the first element isolation trench51(seeFIG. 1). The trench91has substantially the same depth as the gate electrode trench18shown inFIG. 16.

If the depth of the gate electrode trench18is 150 nm, a depth D4of the trench91(a depth from the main surface13aof the semiconductor substrate13) may be, for example, 150 nm. Further, a width W2of the trench91may be, for example, 43 nm.

Next, in a process shown inFIGS. 18A through 18C, impurities having a different conductivity type from the semiconductor substrate13are selectively ion-implanted into the bottom91aof the trench91to thereby form the first region85, which is a layered impurity diffusion region, inside the semiconductor substrate13.

Specifically, phosphorus (P), which is impurities having a different conductivity type from the n-type impurities (a p-type silicon substrate that is a semiconductor substrate13e), is selectively ion-implanted into the bottom91aof the trench91using the silicon nitride film66having the aperture66aas a mask under conditions in which energy is 10 KeV and a dose amount is 1E14 atoms/cm2, to thereby form the first region85having a thickness M1of 60 nm in a position at which a depth D5(a depth of a center position of the first region85from the main surface13aof the semiconductor substrate13) is 150 nm.

Next, in a process shown inFIGS. 19A through 19C, the semiconductor substrate13located downward from the trench91shown inFIGS. 18A through 18Cis etched by anisotropic etching (specifically, dry etching) using the silicon nitride film66having the apertures66aas a mask to thereby form a plurality of first element isolation trenches51.

Accordingly, the plurality of first element isolation trenches51pass through the first layer region85, with the bottoms51cof first element isolation trenches51arranged downward from the first region85.

The depth D1of the first element isolation trench51(a depth from the main surface13aof the semiconductor substrate13) may be, for example, 250 nm.

Next, in a process shown inFIGS. 20A through 20C, the first element isolation insulating film52burying the first element isolation trench51is formed using the same technique as the process shown inFIGS. 4A through 4C, which has been described in the first embodiment (seeFIGS. 4A through 4C).

Accordingly, a plurality of first element isolation regions14consisting of the first element isolation trench51and the first element isolation insulating film52and that are deeper than the first region85are formed and the band-shaped active region16extending in the second direction is partitioned by the first element isolation region14.

Next, in a process shown inFIGS. 21A through 21C, the silicon nitride film66and the pad oxide film65are sequentially removed using the same technique as the process shown inFIGS. 5A through 5C, which has been described in the first embodiment, and then the first element isolation insulating film52protruding from the main surface13aof the semiconductor substrate13is removed to thereby make an upper surface52aof the first element isolation insulating film52flush with the main surface13aof the semiconductor substrate13(seeFIGS. 5A through 5C).

Next, in a process shown inFIGS. 22A through 22C, the mask insulating film26having the trench-shaped aperture26A, the second element isolation trench54deeper than the first region85, and the second element isolation insulating film55having an upper surface55aflush with the upper surface26aof the silicon nitride film26and burying the second element isolation trench54are sequentially formed using the same technique as the process shown inFIGS. 6A through 6C, which has been described in the first embodiment (seeFIGS. 6A through 6C).

Accordingly, the second element isolation region17consisting of the second element isolation trench54and the second element isolation insulating film55, partitioning the band-shaped active region16shown inFIGS. 21A through 21Cinto a plurality of element forming regions R, and passing through the first region85is formed.

The depth D2of the second element isolation trench54(a depth from the main surface13aof the semiconductor substrate13) may be, for example, 250 nm.

Thus, after the first element isolation region14consisting of the first element isolation trench51formed in the semiconductor substrate13and the first element isolation insulating film52burying the first element isolation trench51and partitioning the band-shaped active region16is formed, the second element isolation region17consisting of the second element isolation trench54formed in the semiconductor substrate13and the second element isolation insulating film55burying the second element isolation trench54and partitioning the plurality of element forming regions R is formed. Accordingly, the first and second transistors19-1and19-2can be easily turned on and a data retention characteristic of the memory cell array81can be improved so that a potential of the dummy gate electrode does not adversely affect the first and second transistors19-1and19-2(seeFIG. 16), in comparison with a case in which a dummy gate electrode (not shown) to which a negative potential is applied through the gate insulating film21is provided in the second element isolation trench54to partition a plurality of element forming regions R.

Next, in a process shown inFIGS. 23A through 23C, using the same technique as the process shown inFIGS. 7A through 7C, which has been described in the first embodiment, the trench-shaped aperture26B is formed in the mask insulating film26and then two gate electrode trenches18are formed so that second side surfaces18bface each other (seeFIGS. 7A through 7C).

In this case, the two gate electrode trenches18are formed so that bottoms18cof the gate electrode trenches18reach the first region85(expose the first region85). Accordingly, the bottoms18cof the two gate electrode trenches18are covered with the first region85.

A depth D3of the two gate electrode trenches18(a depth from the main surface13aof the semiconductor substrate13) is smaller than the depths D1and D2of the first and second element isolation trenches51and54. When the depths D1and D2of the first and second element isolation trenches51and54are 250 nm, the depth D3of the gate electrode trench18may be, for example, 150 nm.

Next, in a process shown inFIGS. 24A through 24C, the gate insulating film21, the gate electrode22, and a buried insulating film24having an upper surface24aflush with the upper surface26aof the mask insulating film26are sequentially formed using the same technique as the process shown inFIGS. 8A through 8C, which has been described in the first embodiment (seeFIGS. 8A through 8C).

Accordingly, since the gate insulating film21formed on the bottom18cof the gate electrode trench18is covered with the first region85, the semiconductor substrate13constituting the bottom18cof the gate electrode trench18does not function as a channel when the first and second transistors19-1and19-2shown inFIG. 16operate.

Next, in a process shown inFIGS. 25A through 25C, phosphorus (P), which is impurities having a different conductivity type from the n-type impurities (a p-type silicon substrate that is a semiconductor substrate13), is ion-implanted into an entire upper surface of the structure shown inFIGS. 24A through 24Cusing the same technique as the process shown inFIGS. 9A through 9C, which has been described in the first embodiment under conditions in which energy is 100 KeV and a dose amount is 1E14 atoms/cm2.

Accordingly, the first impurity diffusion region28is formed at a side of the main surface13aof the semiconductor substrate13located between the gate electrode trench18and the first element isolation region17, and the second impurity diffusion region83that is part of the impurity diffusion region71is formed in the semiconductor substrate13located between the two gate electrode trenches18(seeFIGS. 9A through 9C).

In this case, the first impurity diffusion region28and the impurity diffusion region71are formed not to contact the first region85. Further, a thickness of the mask insulating film26in this step may be, for example, 50 nm.

Next, in a process shown inFIGS. 26A through 26C, photoresist73having a trench-shaped aperture73aand an aperture32exposing the upper surface71aof the impurity diffusion region71are sequentially formed using the same technique as the process shown inFIGS. 10A through 10C, which has been described in the first embodiment (FIGS. 10A through 10Csee).

Next, in a process shown inFIGS. 27A through 27C, phosphorus (P), which is impurities having a different conductivity type from the n-type impurities (a p-type silicon substrate that is a semiconductor substrate13), is selectively ion-implanted into the semiconductor substrate13that is exposed from the photoresist73and in which the impurity diffusion region71has been formed (in other words, the semiconductor substrate13located between the two gate electrode trenches18) under conditions in which energy is 100 KeV and a dose amount is 1E14 atoms/cm2.

Accordingly, the second region86(the region that is part of the second impurity diffusion region83) contacting the first region85and covering the gate insulating film21arranged in the second side surfaces18bof the two gate electrode trenches18is formed in the entire semiconductor substrate13located between the two gate electrode trenches18.

Accordingly, the second impurity diffusion region83consisting of the first and second regions85and86and covering the gate insulating film21arranged in the second side surfaces18band bottoms18cof the two gate electrode trenches18is formed, and the first and second transistors19-1and19-2each including the gate insulating film21, the gate electrode22, the buried insulating film24, the first impurity diffusion region28, and the second impurity diffusion region83are formed.

Thus, the second impurity diffusion region83is formed in the semiconductor substrate13to cover the gate insulating film21arranged on the second side surfaces18band bottoms18cof the two gate electrode trenches18, thereby enabling only one surface (the first side surface18a) among three surfaces of the gate electrode trench18(specifically, the first and second opposing side surfaces18aand18b, and the bottom18c) to be used as a channel region.

Accordingly, when the first and second transistors19-1and19-2(seeFIG. 16) enter an on state, a channel region in which on current flows can be reduced in comparison with a conventional transistor. Thus, even in the miniaturized memory cell, the channel resistance can be reduced to increase on current.

Further, when one of the first and second transistors19-1and19-2operates, the other transistor can be suppressed from malfunctioning. Accordingly, even when the semiconductor device80is miniaturized and the gate electrode22is arranged with a small pitch, the first and second transistors19-1and19-2can be operated independently and stably.

Next, in a process shown inFIG. 29, using the same technique as the process shown inFIG. 13, which has been described in the first embodiment, the contact plug33burying the aperture32and contacting the upper surface86aof the second region86, the bit line34, and the cap insulating film36are formed en bloc, and then the sidewall film37and the interlayer insulating film38are sequentially formed (seeFIG. 13).

Further, the sidewall film37may be formed by sequentially stacking a silicon nitride film (SiN film) and a silicon oxide film (SiO2film).

Accordingly, when a coated insulating film (specifically, silicon oxide film (SiO2film)) formed as an interlayer insulating film38by an SOG method is formed, wettability of the silicon oxide film (coated insulating film) is enhanced. Thus, generation of voids in the silicon oxide film (coated insulating film) can be suppressed.

Next, using the same technique as the process shown inFIG. 14, which has been described in the first embodiment, the contact hole41, the capacitive contact plug42contacting the upper surface28aof the first impurity diffusion region28, the capacitive contact pad44, the silicon nitride film46, and the capacitor48consisting of the lower electrode57, the capacitive insulating film58, and the upper electrode59are sequentially formed.

Then, an interlayer insulating film, a via, and a wiring, which are not shown, are formed on the upper surface59aof the upper electrode59to thereby fabricate the semiconductor device80of the second embodiment.

According to the method of fabricating a semiconductor device of the second embodiment, n-type impurities having a different conductivity type from the semiconductor substrate13(p-type silicon substrate) are selectively ion-implanted to form the first layered region85, and then n-type impurities are selectively ion-implanted into an entire portion of the semiconductor substrate13arranged between the two gate electrode trenches18to form the second region86contacting the first layered region85, resulting in the second impurity diffusion region83consisting of the first and second regions85and86and covering the gate insulating film21formed on the second side surfaces18band the bottoms18cof the two gate electrode trenches18. Accordingly, when the first and second transistors19-1and19-2are operated, a channel region can be formed only in the semiconductor substrate13contacting a lower portion of the gate insulating film21arranged on the first side surface18.

Accordingly, when the first and second transistors19-1and19-2(seeFIG. 16) enter an on state, a channel region in which on current flows can be reduced in comparison with a conventional transistor. Thus, even in the miniaturized memory cell, the channel resistance can be reduced to increase on current.

Further, when one of the first and second transistors19-1and19-2operates, the other transistor can be suppressed from malfunctioning. Thus, even when the semiconductor device80is miniaturized and the gate electrode22is arranged with a small pitch, the first and second transistors19-1and19-2can be operated independently and stably.

Further, the first region85covering the gate insulating film21arranged on the bottom18cof the gate electrode trench18, provided in a layer shape inside the semiconductor substrate13along a horizontal plane including the bottom18cand divided into a plurality of regions by the first and second element isolation regions14and17is formed, and then the second region86reaching the first region85arranged downward from the second region86is formed in an entire portion of the semiconductor substrate13sandwiched between the two gate electrode trenches18to thereby form the second impurity diffusion region83consisting of the first and second regions85and86. Accordingly, a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, the electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the first region85containing n-type impurities. Thus, the electrons e− induced in the channel of the first transistor19-1can be prevented from reaching the second impurity diffusion region83(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be prevented so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be prevented.

FIGS. 30A through 30Care views showing a variant of a process of fabricating the memory cell array provided in the semiconductor device according to the second embodiment of the present invention.

FIG. 30Ais a plan view of a region in which the memory cell array is formed,FIG. 30Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 30A, andFIG. 30Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 30A. Further, the line A-A shown inFIG. 30Acorresponds to a cross-section of the semiconductor device80of the second embodiment shown inFIG. 16, which has been previously described.

Next, a method of fabricating a variant of the memory cell array81provided in the semiconductor device80according to the second embodiment will be described with main reference toFIGS. 30A through 30C.

First, in a process shown inFIGS. 30A through 30C, impurities having a different conductivity type from the semiconductor substrate13are selectively ion-implanted into the entire main surface13aof the semiconductor substrate13to thereby form the first region85, which is a layered impurity diffusion region, inside the semiconductor substrate13.

Specifically, phosphorus (P), which is impurities having a different conductivity type from the n-type impurities (a p-type silicon substrate that is a semiconductor substrate13), is ion-implanted into the entire main surface13aof the semiconductor substrate13under conditions in which energy is 120 KeV and a dose amount is 1E14 atoms/cm2, to thereby form the first region101having a thickness M1of 60 nm in a position of depth D5(a depth of a center position of the first region101from the main surface13aof the semiconductor substrate13) of 150 nm.

Next, the same process as the process shown inFIGS. 3A through 3C, which has been described in the first embodiment, is performed to thereby form a structure shown inFIGS. 19A through 19C, which has been described in the second embodiment.

Then, the processes from the process shown inFIGS. 20A through 20Cto the process shown inFIG. 29, which have described in the second embodiment, are sequentially performed to thereby fabricate the semiconductor device80of the second embodiment shown inFIG. 16.

Thus, the first region85that is part of the second impurity diffusion region96may be first formed, and with the method of fabricating a variant of the semiconductor device80, the same effects as those of the method of fabricating the semiconductor device80of the second embodiment can be obtained.

Third Embodiment

FIG. 31is a cross-sectional view of the memory cell array provided in the semiconductor device according to the third embodiment of the present invention, and corresponds to a cross-section taken along a line A-A shown inFIG. 1.

InFIG. 31, a DRAM is described as an example of a semiconductor device90of the third embodiment. Further, inFIG. 31, in fact, a bit line34extending in an X direction shown inFIG. 1is schematically shown. Further, inFIG. 31, the same components as those of the semiconductor device80of the second embodiment shown inFIG. 16are assigned the same reference numerals.

Referring toFIG. 31, the semiconductor device90of the third embodiment has the same configuration as the semiconductor device80except that the semiconductor device90includes a memory cell array91as an alternative to the memory cell array81provided in the semiconductor device80of the second embodiment.

The memory cell91has the same configuration as the memory cell array81except that a second element isolation region93and a second impurity diffusion region96are provided as an alternative to the second element isolation region17and the second impurity diffusion region83provided in the memory cell array81described in the second embodiment, and a third impurity diffusion region95is provided.

The second element isolation region93is formed by burying the second element isolation trench98having substantially the same depth as the gate electrode trench18with the second element isolation insulating film55. The upper surface55aof the second element isolation insulating film55constituting the second element isolation region93is flush with the upper surface26aof the mask insulating film26.

If the depth of the gate electrode trench18is 150 nm, the depth of the second element isolation trench98may be, for example, 150 nm.

The third impurity diffusion region95is a region that is formed by ion-implanting p-type impurities having the same conductivity type as the semiconductor substrate13(p-type silicon substrate) into the semiconductor substrate13at a high concentration. That is, a p-type impurity concentration of the third impurity diffusion region95is higher than that of the semiconductor substrate13. When the p-type impurity concentration of the semiconductor substrate13is 1E16 atoms/cm2, the p-type impurity concentration of the third impurity diffusion region95may be, for example, 1E19 atoms/cm2.

The third impurity diffusion region95is arranged to surround the bottom93A of the second element isolation region93and contacts the second adjacent impurity diffusion region96(specifically, the first region101). The third impurity diffusion region95is an impurity diffusion region for preventing the first region101, which will be described later, constituting the second impurity diffusion region96from contacting the second element isolation region93.

The second impurity diffusion region96has the same configuration as the second impurity diffusion region83except that a first layered region101is provided as an alternative to the first layered region85provided in the second impurity diffusion region83described in the second embodiment.

The first region101is formed with the same depth as the third impurity diffusion region95and is integrally formed with the second region86. An n-type impurity diffusion region may be used as the second impurity diffusion region96including the first region101.

The first region101covers the gate insulating film21formed in the bottoms18cof the two gate electrode trenches18. The first region101is formed by partitioning the second layered region86described in the second embodiment into element forming regions by the third impurity diffusion region95.

The first region101contacts the third impurity diffusion region95without contact with the second element isolation region93. Accordingly, the third impurity diffusion region95is formed between the first region101and the second element isolation region93.

According to the semiconductor device of the third embodiment, the second element isolation region93has substantially the same depth as the two gate electrode trenches18, and the third impurity diffusion region95containing p-type impurities having the same conductivity type as the semiconductor substrate (p-type silicon substrate) at a higher concentration than the semiconductor substrate, provided in the semiconductor substrate13to surround the bottom93A of the second element isolation region93, and contacting the first region101is provided. Accordingly, a path for releasing extra charges accumulated in the semiconductor substrate13located between the gate electrode22and the second element isolation region93(a path for releasing charges in the semiconductor substrate13located downward from the third impurity diffusion region95) can be formed between the bottom93A of the second element isolation region93and the first region101. Thus, the first and second transistors19-1and19-2can be operated independently and stably.

Further, the second impurity diffusion region96consisting of the first region101covering the gate insulating film21formed on the bottoms18cof the two gate electrode trenches18and divided into element forming regions by the third impurity diffusion region95, and the second region86provided in an entire portion of the semiconductor substrate13sandwiched between the two gate electrode trenches18, reaching the first region101arranged downward from the second region86and integrally formed with the first region101is provided. Accordingly, a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the first region101containing n-type impurities. Thus, the electrons e− induced in the channel of the first transistor19-1can be suppressed from reaching the second impurity diffusion region96(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be suppressed so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be suppressed.

Further, with the semiconductor device90of the third embodiment, the same effects as those of the semiconductor device80of the second embodiment can be obtained.

FIG. 32A through 32C,FIGS. 33A through 33C,FIG. 34A through 34C,FIGS. 35A through 35C,FIGS. 36A through 36C,FIGS. 37A through 37C,FIG. 38A through 38C,FIG. 39A through 39C, andFIG. 40are views showing a process of fabricating a memory cell provided in a semiconductor device according to the third embodiment of the present invention.

FIG. 32Ais a plan view of a region in which the memory cell array is formed,FIG. 32Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 32A, andFIG. 32Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 32A.

FIG. 33Ais a plan view of a region in which the memory cell array is formed,FIG. 33Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 33A, andFIG. 33Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 33A.

FIG. 34Ais a plan view of a region in which the memory cell array is formed,FIG. 34Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 34A, andFIG. 34Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 34A.

FIG. 35Ais a plan view of a region in which the memory cell array is formed,FIG. 35Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 35A, andFIG. 35Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 35A.

FIG. 36Ais a plan view of a region in which the memory cell array is formed,FIG. 36Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 36A, andFIG. 36Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 36A.

FIG. 37Ais a plan view of a region in which the memory cell array is formed,FIG. 37Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 37A, andFIG. 37Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 37A.

FIG. 38Ais a plan view of a region in which the memory cell array is formed,FIG. 38Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 38A, andFIG. 38Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 38A.

FIG. 39Ais a plan view of a region in which the memory cell array is formed,FIG. 39Bis a cross-sectional view taken along a line A-A of a structure shown inFIG. 39A, andFIG. 39Cis a cross-sectional view taken along a line B-B of the structure shown inFIG. 39A.

FIG. 40corresponds to a cross-section of the semiconductor device90of the third embodiment shown inFIG. 31. Further, a cross-section taken along the line A-A shown inFIG. 32A,FIG. 33A,FIG. 34A,FIG. 35A,FIG. 36A,FIG. 37A,FIG. 38A, andFIG. 39Acorresponds to the cross-section of the semiconductor device90of the third embodiment shown inFIG. 31, which has been previously described.

A method of fabricating the semiconductor device90(specifically, memory cell91) according to the third embodiment of the present invention will be described with reference toFIGS. 32A through 32C,FIGS. 33A through 33C,FIGS. 34A through 34C,FIGS. 35A through 35C,FIGS. 36A through 36C,FIGS. 37A through 37C,FIG. 38A through 38C,FIG. 39A through 39C, andFIG. 40.

In a process shown inFIGS. 32A through 32C, the processes from the process shown inFIGS. 3A through 3Cto the process shown inFIGS. 5A through 5C, which has been described in the first embodiment, is performed to thereby form the structure shown inFIGS. 5A through 5C.

Next, a mask insulating film26having an aperture26A and a second element isolation trench98(formed by etching the semiconductor substrate13) are sequentially formed on the main surface13aof the semiconductor substrate13using the same technique as the process shown inFIGS. 6A through 6Cof the first embodiment. A depth D6of the second element isolation trench98(a depth from the main surface13aof the semiconductor substrate13) may be, for example, 150 nm.

Next, in a process shown inFIGS. 33A through 33C, impurities having the same conductivity type as the semiconductor substrate13are ion-implanted at a higher concentration than the semiconductor substrate13into the bottom98aof the second element isolation trench98, and a third impurity diffusion region95surrounding the bottom98A of the second element isolation trench98is formed.

Specifically, boron (B), which is p-type impurities (impurities having the same conductivity type as the semiconductor substrate13), is ion-implanted into the bottom98aof the second element isolation trench98to thereby form the third impurity diffusion region95that is a p-type impurity diffusion region having a higher concentration than the p-type impurities of the semiconductor substrate13to surround the bottom98A of the second element isolation trench98.

If the p-type impurity concentration of the semiconductor substrate13is 1E16 atoms/cm2, the p-type impurity concentration of the third impurity diffusion region95may be, for example, 1E19 atoms/cm2.

Next, in a process shown inFIGS. 34A through 34C, the second element isolation insulating film55burying the second element isolation trench98and having an upper surface55aflush with the upper surface26aof the mask insulating film26is formed using the same technique as the method described with reference toFIGS. 6A through 6Cof the first embodiment (seeFIGS. 6A through 6C).

Accordingly, the second element isolation region93consisting of the second element isolation trench98and the second element isolation insulating film55and partitioning the band-shaped active region16shown inFIG. 33Ainto a plurality of element forming regions R is formed.

Next, in a process shown inFIGS. 35A through 35C, a trench-shaped aperture26B and two gate electrode trenches18having first opposing side surfaces18aare sequentially formed in the mask insulating film26using the same technique as the method described with reference toFIGS. 7A through 7Cof the first embodiment.

In this case, a depth D3of the gate electrode trench18(a depth from the main surface13aof the semiconductor substrate13) is substantially the same as that of the second element isolation trench98. If the depth of the second element isolation trench98is 150 nm, the depth D3of the gate electrode trench18may be, for example, 150 nm.

Next, in a process shown inFIGS. 36A through 36C, n-type impurities having a different conductivity type from the semiconductor substrate13(p-type silicon substrate) are ion-implanted into the bottom18cof the gate electrode trench18to thereby form the first region101, which is part of the second impurity diffusion region96, with the same depth as the third impurity diffusion region95.

Specifically, phosphorus (P), which is n-type impurities (impurities having a different conductivity type from the p-type silicon substrate that is a semiconductor substrate13), is selectively ion-implanted into the bottom18cof the gate electrode trench18under conditions in which energy is 100 KeV and a dose amount is 1E14 atoms/cm2, to thereby form the first region101to the same depth as the third impurity diffusion region95.

In this case, the first region101tries to spread in a direction (lateral direction) toward the second element isolation region93. However, since the third impurity diffusion region95, which is a high-concentration p-type impurity diffusion region, is formed in the bottom93A of the second element isolation region93, the first region101does not reach the second element isolation region93.

Thereby, as shown inFIG. 36B, the third impurity diffusion region95is present between the bottom93A of the second element isolation region93and the first region101, and the third impurity diffusion region95functions as passage through which charges can move.

Next, in a process shown inFIGS. 37A through 37C, the gate insulating film21, the gate electrode22, and the buried insulating film24are sequentially formed using the same technique as the method described with reference toFIGS. 8A through 8Cof the first embodiment (seeFIGS. 8A through 8C).

In this case, since the gate insulating film21formed on the bottom18cof the gate electrode trench18is covered with the first region101, the semiconductor substrate13constituting the bottom18cof the gate electrode trench18does not function as a channel.

Next, in a process shown inFIGS. 38A through 38C, phosphorus (P), which is n-type impurities, is ion-implanted into an entire upper surface of the structure shown inFIGS. 37A through 37Cusing the same technique as the method described with reference toFIGS. 9A through 9Cof the first embodiment under conditions in which energy is 100 KeV and a dose amount is 1E14 atoms/cm2to thereby simultaneously form the first impurity diffusion region28, and the second region86that is part of impurity diffusion region71(seeFIGS. 9A through 9C).

Next, in a process shown inFIGS. 39A through 39C, using the same technique as the process shown inFIGS. 10A through 10C,FIGS. 11A through 11C, andFIGS. 12A through 12Cof the first embodiment, an entire portion of the semiconductor substrate13located between the two gate electrode trenches18, formed in the second side surfaces18bof the two gate electrode trenches18is covered with the gate insulating film21and the first region85contacting the first region101is formed.

Accordingly, the second impurity diffusion region96consisting of the first region85and the first region101is formed.

Next, in a process shown inFIG. 40, the same process as the process shown inFIGS. 13 through 15, which has been described in the first embodiment, is performed to thereby fabricate the semiconductor device90of the third embodiment.

According to the method of fabricating a semiconductor device of the third embodiment, before the second element isolation insulating film55is formed, p-type impurities having the same conductivity type as the semiconductor substrate13are ion-implanted into the bottom98aof the second element isolation trench98at a higher concentration than the semiconductor substrate13to thereby form the third impurity diffusion region95surrounding the bottom93A of the second element isolation trench93, and then n-type impurities having a different conductivity type from the semiconductor substrate13are selectively ion-implanted into the bottom18cof the gate electrode trench18to thereby form the first layered region101(part of the second impurity diffusion region96). Accordingly, a path for releasing extra charges accumulated in the semiconductor substrate13located between the gate electrode22and the second element isolation region93(a path for releasing charges in the semiconductor substrate13located downward from the third impurity diffusion region95) can be formed between the bottom93A of the second element isolation region93and the first region101. Thus, the first and second transistors19-1and19-2can be operated independently and stably.

Further, the first region101covering the gate insulating film21formed on the bottoms18cof the two gate electrode trenches18and divided into element forming regions by the third impurity diffusion region95is formed, and then the second region86reaching the first region101arranged downward from the second region86is formed in an entire portion of the semiconductor substrate13sandwiched between the two gate electrode trenches18to thereby form the second impurity diffusion region96consisting of the first region101and the second region86. Accordingly, a state in which “L” is accumulated in the lower electrode57electrically connected with the first transistor19-1and “H” is accumulated in the lower electrode57electrically connected with the first transistor19-1is obtained. In this state, when on/off of the gate electrode22(word line) corresponding to the first transistor19-1is repeated, electrons e− induced in the channel of the first transistor19-1(not shown) are trapped by the first region101containing n-type impurities. Thus, the electrons e− induced in the channel of the first transistor19-1can be suppressed from reaching the second impurity diffusion region96(drain region) constituting the second transistor19-2.

Accordingly, generation of a disturbance defect, in which an accumulation state of one cell is changed due to an operation state of the other adjacent cell, can be suppressed so that H information resulting from electrons e− induced in the channel of the first transistor19-1being accumulated in the lower electrode57electrically connected with the second transistor19-2is not destructed and the state is not changed into an L state.

Further, even in a DRAM in which an interval between the two gate electrodes22arranged to be adjacent to each other is equal to or less than 50 nm, the generation of the disturbance defect can be suppressed.

Further, with the method of fabricating the semiconductor device90of the third embodiment, the same effects as those of the semiconductor device80of the second embodiment can be obtained.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such specific embodiments and various modifications and variations may be made without departing from the scope and spirit of the present invention defined in claims.

FIG. 41is a plan view showing another example of a layout of a memory cell array that can be applied to the semiconductor device according to the first to third embodiments of the present invention. InFIG. 41, the same components as those of the structure shown inFIG. 1are assigned the same reference numerals.

The semiconductor devices10,80and90of the first to third embodiments, which have been described above, may be applied to a layout in which the active region16and the bit line34as shown inFIG. 41are in zigzag shape.

As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.

The term “configured” is used to describe a component, section or part of a device includes hardware and/or software that is constructed and/or programmed to carry out the desired function.

Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.