Semiconductor device manufacturing method

Provided is a semiconductor device manufacturing method including the steps of: forming an n-type impurity diffusion region by ion-implanting arsenic into a capacitor formation region of a silicon substrate under a condition that a beam current is not less than 1 μA but less than 3 mA; forming a capacitor dielectric film on the capacitor formation region of the silicon substrate; and forming a capacitor upper electrode on the capacitor dielectric film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority of Japanese Patent Application No.2005-249435 filed on Aug. 30, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device manufacturing method.

2. Description of the Related Art

In a semiconductor device such as an LSI, in addition to an MOS transistor, a capacitor is formed on a semiconductor substrate for the purpose of computation processing, storage of information, or the like. Such capacitors may take various types of structures. Among those, a structure in which a lower electrode is formed of the impurity diffusion region of a semiconductor substrate is advantageous in that both the manufacturing process for the capacitor and that for an MOS transistor can be readily carried out in a compatible manner, because a capacitor dielectric film can be formed of the same thermal oxidation film as that forming a gate insulating film of the MOS transistor and an upper electrode can be formed of the same conductive film as that forming a gate electrode.

As described in the following Patent Literature 1, the problem with this type of capacitor is that when the impurity concentration in the impurity diffusion region serving as the lower electrode is low, the surface of a silicon substrate becomes depleted when the voltage applied to the capacitor is low, and hence the capacitance of the capacitor fluctuates. In order to reduce such dependency of the capacitance of the capacitor on the applied voltage, in this type of capacitor, it is preferable to set the impurity concentration in the above-mentioned impurity diffusion region to be as high as possible.

An impurity concentration is determined by the product (dose amount) of a beam current and implantation time of an ion implantation device. Accordingly, conventionally, a high-current ion implantation device capable of generating a high beam current on the order of 10 mA to 20 mA has been used to form the above-mentioned impurity diffusion region, whereby the impurity concentration in the impurity diffusion region has been increased.

However, when the amount of ion implantation to the impurity diffusion region is increased in this way in order to increase the impurity concentration, an amorphous layer is formed on the surface layer of the semiconductor substrate due to the ion implantation, which causes a decrease in the breakdown voltage of the thermal oxidation film that serves as the capacitor dielectric film. This causes another problem that the breakdown voltage between electrodes of the capacitor decreases, and that the decrease results in reduced reliability.

It should be noted that the technique relating to the present invention is also disclosed in the Patent Literature 2.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a semiconductor device manufacturing method is provided, the method including the steps of: forming an impurity diffusion region in a semiconductor substrate by ion-implanting an impurity into a capacitor formation region of the semiconductor substrate under a condition that a beam current is equal to or more than 1 μA but less than 3 mA; forming a capacitor dielectric film on the impurity diffusion region of the semiconductor substrate; and forming a capacitor upper electrode on the capacitor dielectric film.

According to the present invention, when forming the impurity diffusion region, which functions as the lower electrode of the capacitor, through ion implantation, the applied beam current is set to be equal to or more than 1 μA but less than 3 mA. By employing the beam current within this range, the thickness of an amorphous layer, which is formed on the surface layer of the semiconductor substrate due to the damage inflicted during the ion implantation, can be reduced. As a result, the breakdown voltage of the capacitor dielectric film formed on the impurity diffusion region can be inhibit from being lowered due to the influence of the amorphous layer, and it becomes possible to improve the breakdown voltage between electrodes of the capacitor.

As the capacitor dielectric film, there may be used, for example, a thermal oxidation film obtained through thermal oxidation of a surface of the semiconductor substrate in the impurity diffusion region. In this case, the amorphous layer undergoes crystallization to some degree due to the heat applied during the thermal oxidation.

Further, in the step of forming the capacitor dielectric film, a gate insulating film formed of the same insulating film as that forming the capacitor dielectric film may be formed on the transistor formation region of the semiconductor substrate, and in the step of forming the capacitor upper electrode, a gate electrode formed of the same conductive film as that forming the capacitor upper electrode may be formed on the gate insulating film.

In this way, the manufacturing process for the MOS transistor including the gate insulating film and the gate electrode, and the manufacturing process for the capacitor can be readily carried out in a compatible manner.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 1A to 1ZandFIGS. 2A to 2Fare sectional views of a semiconductor device according to an embodiment of the present invention during the manufacture thereof.

It should be noted that while there is no particular limitation as to the kind of the semiconductor device used, in the following, the description is directed to the example of an analog device to be used together with a logic IC.

First of all, the processes to be performed before obtaining the sectional structure shown inFIG. 1Awill be described.

First, in an atmosphere containing HCI and oxygen, the surface of a p-type silicon (semiconductor) substrate1is subjected to thermal oxidation with the substrate temperature being 900° C. to thereby form a thermal oxidation film2having a thickness of about 10 nm, and then a silicon nitride film3having a thickness of about 150 nm is further formed thereon by a low pressure CVD method.

The silicon substrate1has a low voltage MOS transistor formation region I, a high voltage MOS transistor formation region II, a capacitor formation region III, and a resistance formation region IV. Among these regions, the low voltage MOS transistor formation region I is divided into an n-type low voltage MOS transistor formation region Inand a p-type low voltage MOS transistor formation region Ip. Further, the high voltage MOS transistor formation region II is divided into an n-type high voltage MOS transistor formation region IIn, a p-type high voltage MOS transistor formation region IIp, and an input/output n-type high voltage MOS transistor formation region IIn(I/O).

Next, a photoresist is applied onto the silicon nitride film3, followed by exposure and development thereof to thereby form an island-like first resist pattern4on each of the regions I to III as shown in the drawing.

Next, as shown inFIG. 1B, with the first resist pattern4serving as the mask, etching is performed on the silicon nitride film3and the thermal oxidation film2through Reactive Ion Etching (RIE) using a fluorine-based gas as the etching gas, whereby an opening3ais formed in each of these films.

Subsequently, as shown inFIG. 1D, RIE using chlorine-based gas as the etching gas is employed to perform etching on the silicon substrate1through the opening3a, thereby forming a isolation groove1awith a depth of about 40 nm.

Next, the processes to be performed before obtaining the sectional structure shown inFIG. 1Ewill be described.

First, in order to recover the damage inflicted on the inner surface of the isolation groove1adue to RIE, a thermal oxidation film (not shown) having a thickness of about 10 nm is formed within the isolation groove1a. Thereafter, a silicon oxide film is formed on the silicon nitride film3through a High Concentration Plasma CVC (HDPCVD) method using silane as the reaction gas, and the isolation groove1ais completely filled with the silicon oxide film thus formed. Next, any excess silicon oxide film on the silicon nitride film3is polished away by a Chemical Mechanical Polishing (CMP) method, so the silicon oxide film remains as a device isolation insulating film6within the isolation groove1a. The isolation structure thus obtained is also referred to as Shallow Trench Isolation (STI).

It should be noted that while the silicon nitride film3functions as a polishing stopper during the CMP process described above, the thickness thereof becomes slightly smaller because of the polishing.

Next, as shown inFIG. 1F, the silicon nitride film3is removed away by wet etching using phosphoric acid to expose the thermal oxidation film2.

Subsequently, as shown inFIG. 1G, a photoresist is applied onto the entire upper surface of the silicon substrate1followed by exposure and development thereof, whereby a second resist pattern8having a window in n-type high voltage MOS transistor formation region IInis formed. Then, an n-type impurity such as phosphorous is ion-implanted through a window of the second resist pattern8, whereby a first n-well9is formed in the n-type high voltage MOS transistor formation region IInof the silicon substrate. It should be noted that the thermal oxidation film2on the first n-well9functions as a through-film during the ion implantation.

Next, as shown inFIG. 1H, a photoresist is applied onto the entire upper surface of the silicon substrate1followed by exposure and development thereof, whereby a third resist pattern10covering the p-type low voltage MOS transistor formation region Ipand the p-type high voltage MOS transistor formation region IIpis formed. Then, with the third resist pattern10serving as the mask and the thermal oxidation film2serving as the through-film, a p-type impurity such as boron is ion-implanted into the silicon substrate1in order to form p-well11in each of the regions In, IIn, IIn(I/O), III, and IV of the silicon substrate1.

Subsequently, as shown inFIG. 1I, a fourth resist pattern12, which has windows provided at positions above the p-type low voltage MOS transistor formation region Ipand the p-type high voltage MOS transistor formation region IIp, is formed on the silicon substrate1. Then, while the thermal oxidation film2is used as the through-film, an n-type impurity such as phosphorous is ion-implanted into the silicon substrate1through the windows of the fourth resist pattern14in order to form a second n-well13in each of the regions Ipand IIpof the silicon substrate1.

After this ion implantation, the fourth resist pattern12is removed.

Next, as shown inFIG. 1J, a fifth resist pattern15, which has a window provided at a position above the n-type low voltage MOS transistor formation region In, is formed on the silicon substrate1. Then, a p-type impurity such as boron is ion-implanted into the silicon substrate1through the window of the fifth resist pattern15in order to form a first threshold-voltage-adjusting n-type impurity diffusion region16for adjusting the threshold voltage of the n-type low voltage MOS transistor.

Next, as shown inFIG. 1K, a photoresist is applied onto the entire upper surface of the silicon substrate1followed by exposure and development thereof, whereby a sixth resist pattern17having a window provided at a position above the p-type low voltage MOS transistor formation region Ipis formed. Subsequently, an n-type impurity such as arsenic is ion-implanted into the silicon substrate1through the window of the sixth resist pattern17in order to form a first threshold-voltage-adjusting p-type impurity diffusion region18for adjusting the threshold voltage of the p-type low voltage MOS transistor. After this ion implantation, the sixth resist pattern17is removed.

Then, as shown inFIG. 1L, a seventh resist pattern19is formed on the silicon substrate1, the seventh resist pattern19having windows provided at positions above the n-type high voltage MOS transistor formation region IIn, the input/output n-type high voltage MOS transistor formation region IIn(I/O), and the capacitor formation region III.

Then, an n-type impurity is ion-implanted into the silicon substrate1through the windows of the seventh resist pattern19in order to form a second threshold-voltage-adjusting n-type impurity diffusion region20for adjusting the threshold voltage of the n-type low voltage MOS transistor.

Subsequently, as shown inFIG. 1M, an eighth resist pattern21is formed on the silicon substrate1, and a p-type impurity such as boron is ion-implanted into the silicon substrate1through a window of the eighth resist patter21. Accordingly, there is formed, in the p-type high voltage MOS transistor formation region IIpof the silicon substrate1, a second threshold-voltage-adjusting p-type impurity diffusion region22for adjusting the threshold voltage of the p-type low voltage MOS transistor.

Next, the processes to be performed before obtaining the sectional structure shown inFIG. 1Nwill be described.

First, a photoresist is applied onto the entire upper surface of the silicon substrate1followed by exposure and development thereof, whereby a ninth resist pattern23having a window provided at a position above the capacitor formation region III is formed. Then, under the conditions that the implantation energy is equal to or higher than 50 keV but not higher than 70 keV, more preferably 60 keV, and that the dose amount is set to 1×1015cm−2, and while using the thermal oxidation film2as the through-film, an n-type impurity such as arsenic is ion-implanted through the window of the ninth resist pattern23. Accordingly, an n-type impurity diffusion region24, which also serves as the lower electrode of the capacitor, is formed in the capacitor formation region III of the silicon substrate1. By performing the ion implantation with the thermal oxidation film2serving as the through-film, it is possible to prevent the surface of the silicon substrate1from becoming rough in the capacitor formation region III.

Incidentally, at the time of the ion implantation, the capacitor formation region III of the silicon substrate1suffers damage due to arsenic. For this reason, as indicated by the dashed circle in the figure, the surface layer portion of the silicon substrate1becomes amorphous, so an amorphous layer1bis formed in this portion.

After completing this ion implantation, the ninth resist pattern23is removed.

After removing the ninth resist pattern23, the silicon substrate1may be subjected to Rapid Thermal Anneal (RTA) in nitrogen atmosphere for the purpose of recrystallizing the amorphous layer1b. The conditions for RTA to be adopted at this time may be such that, for example, the substrate temperature is 1000° C. and the processing time is for 10 seconds.

Further, in this example, while arsenic not susceptible to thermal diffusion is used as the n-type impurity to be implanted into the n-type impurity diffusion region24, phosphorous may be used instead of arsenic. Although phosphorous is more susceptible to thermal diffusion than arsenic, by performing RTA with a short processing time as heat treatment such as activation annealing that will be described later, it is possible to suppress the breakage of the impurity concentration profile of the n-type impurity diffusion region24to the minimum level, the breakage caused by thermal diffusion.

Next, as shown inFIG. 1O, the thermal oxidation film2that has been damaged due to the above-mentioned ion implantations mentioned above is removed by wet etching in a hydrofluoric acid solution in order to expose the cleaning surface of the silicon substrate1.

Then, as shown inFIG. 1P, through thermal oxidation in steam atmosphere with the substrate temperature being about 800° C., a thermal oxidation film of about 5 nm in thickness is formed in the portion of the surface of the silicon substrate1corresponding to the transistor formation regions I and II in order to form a first gate insulating film26. Along with this, the amorphous layer1b(seeFIG. 1N) produced while the n-type impurity diffusion region24is formed is crystallized to some degree with the heat applied during the thermal oxidation.

In the above thermal oxidation method, a thermal oxidation film is also formed in the capacitor formation region III of the surface of the silicon substrate1. It should be noted, however, that the n-type impurity diffusion region24also serving as the lower electrode of the capacitor is formed in the capacitor formation region III, and the silicon substrate1undergoes accelerated oxidation due to the arsenic in the n-type impurity diffusion region24. Accordingly, the thickness of the thermal oxidation film formed in the capacitor formation region III is larger than that in the transistor formation regions I and II, the thickness being about, for example, 8 nm. Such a thick thermal oxidation film is used as a capacitor dielectric film25in this embodiment. The n-type impurity diffusion region24also serves to increase the thickness of the capacitor dielectric film25due to the accelerated oxidation mentioned above to thereby enhance the breakdown voltage thereof.

Thereafter, a tenth resist pattern27is formed on the silicon substrate1, leaving the n-type low voltage MOS transistor formation region Inand the p-type low voltage MOS transistor formation region Ipexposed.

Next, as shown inFIG. 1Q, the portions of the first gate insulating film26which are not covered with the tenth resist pattern27are removed by wet etching using a hydrofluoric acid solution as the etching solution, thereby exposing the cleaning surface of the silicon substrate1in each of the regions Inand Ip.

Next, as shown inFIG. 1S, the silicon substrate1is heated to about 750° C. in steam atmosphere, whereby the n-type low voltage MOS transistor formation region Inand the p-type low voltage MOS transistor formation region Ipof the silicon substrate1undergoes thermal oxidation again to thereby form a thermal oxidation film at a thickness of about 1.8 nm. The thermal oxidation film thus formed serves as a second gate insulating film28.

In the above thermal oxidation, the portions of the silicon substrate1under the first gate insulating film26and the capacitor dielectric film25also undergo oxidation, so the first gate insulating film26and the capacitor dielectric film25each having an original thickness on the order of 5 nm are increased in thickness to about 9 nm. As a result, two kinds of gate insulating films26and28that differ in thickness are formed on the silicon substrate1.

Subsequently, as shown inFIG. 1T, by use of a low pressure CVD method with silane serving as the reaction gas, a polysilicon film is formed on each of the first and second gate insulating films26and28and on the capacitor dielectric film25at a thickness of about 180 nm. The films thus formed serves as a conductive film30.

Next, as shown inFIG. 1U, an eleventh resist pattern31is formed on the conductive film30. Then, the conductive film30is subjected to dry etching using the eleventh resist pattern31as the mask. The portions of the conductive film30that remain under the eleventh resist pattern31without being etched away serve as a gate electrode30a, a capacitor upper electrode30b, and a resistance pattern30c. Among those, the capacitor upper electrode30bis formed in the portion of the capacitor formation region III excluding a contact region CR.

Next, as shown inFIG. 1V, a twelfth resist pattern32is formed on the silicon substrate1. Then, an n-type impurity such as phosphorous is ion-implanted into the silicon substrate1through windows of the twelfth resist pattern32, whereby a first n-type source/drain extension33are formed in each of the n-type high voltage MOS transistor formation region IInand the input/output n-type high voltage MOS transistor formation region IIn(I/O).

Further, during the above ion implantation, the above-mentioned n-type impurity are also implanted into the silicon substrate1in the contact region CR not covered with the capacitor upper electrode30b, whereby a low-concentration n-type impurity diffusion region for contact34is formed in the contact region CR.

Thereafter, the twelfth resist pattern32that has been used as the mask is removed.

Then, in order to prevent the first n-type source/drain extension33and the low-concentration n-type impurity diffusion region for contact34from undergoing diffusion in the subsequent thermal processes to cause the concentration distributions thereof to spread, annealing may be performed on the silicon substrate1at this point so that the first n-type source/drain extension33and the low-concentration n-type impurity diffusion region for contact34may previously be subjected to diffusion to some extent. The annealing at this time is carried out in nitrogen atmosphere at a substrate temperature of about 700° C. to 800° C. for about 120 minutes.

Subsequently, as shown inFIG. 1W, using a thirteenth resist pattern36formed on the silicon substrate1as the mask, a p-type impurity such as boron fluoride is ion-implanted into the p-type high voltage MOS transistor formation region IIpof the silicon substrate1to thereby form a first p-type source/drain extension37.

Next, as shown inFIG. 1X, a fourteenth resist pattern38, which is provided with a window through which the resist pattern30cis exposed, is formed on the silicon substrate1. Then, an impurity such as boron is ion-implanted through the window of the fourteenth resist pattern38in order to reduce the resistance of the resistance pattern30c.

After completing the above ion implantation, the fourteenth resist pattern38is removed.

Subsequently, as shown inFIG. 1Y, a fifteenth resist patter40is formed on the silicon substrate1, the fifteenth resist pattern40having windows through which the n-type low voltage MOS transistor formation region Inand parts of the input/output n-type high voltage MOS transistor formation region IIn(I/O) are exposed. It should be noted that the portion of the gate electrode30aand its vicinity in the region IIn(I/O) is covered with the fifteenth resist pattern40formed in an island-like shape.

Then, with the fifteenth resist pattern40as the mask, an n-type impurity such as arsenic is ion-implanted into the silicon substrate1, whereby a second n-type source-drain extension41is formed in the n-type low voltage MOS transistor formation region Inand two high-concentration n-type impurity diffusion regions42are formed in the region IIn(I/O). The distance between the two high-concentration n-type impurity diffusion regions42increases due to the use of the island-like fifteenth resist pattern40as the mask in the region IIn(I/O), whereby the breakdown voltage therebetween is enhanced.

Next, as shown inFIG. 1Z, with a sixteenth resist pattern44formed on the silicon substrate1as the mask, a p-type impurity such as boron is ion-implanted into the silicon substrate1in order to form a second p-type source/drain extension45in the p-type low voltage MOS transistor formation region Ip.

Next, as shown inFIG. 2A, a silicon oxide film is formed on the entire upper surface of the silicon substrate1through a CVD method. The silicon oxide film thus formed serves as a sidewall insulating film46.

Then, a photoresist is applied onto the sidewall insulating film46followed by exposure and development thereof, whereby a seventeenth resist pattern47is formed in each of the input/output n-type high voltage MOS transistor formation region IIn(I/O) and the resistance formation region IV.

Subsequently, as shown inFIG. 2B, with the seventeenth resist pattern as the mask, the sidewall insulating film46is etched back so that the sidewall insulating film46remains as an insulative sidewall46aby the side of each of the gate electrode30a, the capacitor upper electrode30b, and the resistance patter30c. During the etching back, the first and second gate electrodes26and28, and the capacitor dielectric film25, which are situated by the side of the insulative sidewall46a, are also etched away. As a result, in the capacitor formation region III, the silicon substrate1is exposed in the contact region CR situated by the side of the capacitor upper electrode30b.

Further, the sidewall insulating film46under the seventeenth resist pattern47is allowed to remain as silicide blocks46band46cin the regions IIn(I/O) and IV, respectively.

Next, as shown inFIG. 2C, with an eighteenth resist pattern50formed on the silicon substrate1as the mask, a p-type impurity such as boron is ion-implanted into the silicon substrate1in order to form a p-type source/drain region51by the side of the gate electrode30ain each of the regions Ipand IIpof the silicon substrate1. Further, during this ion implantation, a p-type impurity is also ion-implanted into the portion of the resistance pattern30cwhich is not covered with the silicide block46c, so the portion of the resistance pattern30cundergoes a reduction in resistance.

After completing the ion implantation, the eighteenth resist pattern50is removed.

Next, as shown inFIG. 2D, a photoresist is applied onto the entire upper surface of the silicon substrate1followed by exposure and development thereof, whereby a nineteenth resist pattern52is formed. Then, an n-type impurity such as phosphorous is ion-implanted into the silicon substrate through windows of the nineteenth resist pattern52. Accordingly, an n-type source/drain region53is formed by the side of the gate electrode30ain each of the regions In, IIn, and IIn(I/O) of the silicon substrate1. Further, in the capacitor formation region III, a high-concentration n-type impurity diffusion region for contact54is formed in the contact region CR situated by the side of the capacitor upper electrode30b.

Next, the processes to be performed before obtaining the sectional structure shown inFIG. 2Ewill be described.

First, as the activation annealing for activating the impurity contained in each of the source/drain regions51and53, RTA is carried out in nitrogen atmosphere with the substrate temperature being 1000° C. and the processing time for 10 seconds. The activation annealing causes the amorphous layer1b(seeFIG. 1N) formed on the silicon substrate1to crystallize again.

Next, a high-melting metal layer such as a cobalt layer is formed on the entire upper surface of the silicon substrate1by a sputtering method. Then, the silicon substrate1is heated to cause the high-melting metal layer and silicon to react with each other, whereby a high-melting metal silicide layer55is formed on each of the silicon substrate1and the gate electrode30a. Thereafter, the high-melting metal layer that remains on the device isolation insulating film6or the like without undergoing reaction is removed by wet etching.

Through the foregoing processes, n-type MOS transistors TR(low)n, TR(high)n, and TR(I/O)n, p-type MOS transistors TR(low)pand TR(high)p, a capacitor Q, and a resistance R, which constitute an analog circuit, are formed in the silicon substrate1as shown in the drawing.

Among those, the transistors TR(high)n, TR(high)p, and TR(I/O)ncan be driven at a high voltage of, for example, about 3.3 V due to the first gate insulating film26whose thickness has been increased to be 9 nm by the thermal oxidation performed twice. On the other hand, each of the transistors TR(low)nand TR(low)phas the second gate insulating film28with a small thickness of about 5 nm, and the drive voltage thereof is low at 1.2 V.

Further, the capacitor Q is constituted of the n-type impurity diffusion region24functioning as the lower electrode, the capacitor dielectric film25, and the capacitor upper electrode30b, and has the function of converting an applied voltage into an electric charge amount to thereby execute the addition/subtraction of the applied voltage (information) by replacing it with the sum/difference of the electric charge amount.

Subsequently, as shown inFIG. 2F, a silicon oxide film having a thickness of about 20 nm and a silicon nitride film having a thickness of about 70 nm are formed in the stated order on the entire surface by a plasma CVD method. Those films serve as a cover insulating film57. Further, a silicon oxide film is formed at a thickness of about 1000 nm on the cover insulating film57by an HDPCVD method as an interlayer dielectric58. Thereafter, the upper surface of the interlayer dielectric58is polished for flattening by a CMP method in order to make the thickness of the interlayer dielectric58on the flat surface of the silicon substrate1be about 70 nm.

Next, the interlayer dielectric58and the cover insulating film57are subjected to patterning by photolithography, whereby a hole58ais formed at a position above each of the p-type source-drain region51and the n-type source/drain region53. Further, through this patterning, the hole58ais also formed at a position above each of the contact region CR and capacitor upper electrode30bof the capacitor formation region III, and of the resistance pattern30c.

Then, a titanium film of about 20 nm to 50 nm in thickness and a titanium nitride film of about 50 nm in thickness are formed in the stated order on the inner surface of the hole58aand on the interlayer dielectric58by a sputtering method. Further, a tungsten film is formed on the titanium nitride film by a CVD method using tungsten hexafluoride as the reaction gas. The tungsten film thus formed completely fills the hole58a. Thereafter, any excess titanium film, titanium nitride film, and tungsten film on the interlayer dielectric58are removed through polishing by a CMP method, with those films being allowed to remain inside the hole58aas conductive plugs60.

The two conductive plugs60formed in the capacitor formation region III are electrically connected to the high-concentration impurity diffusion region for contact54in the contact region CR and to the capacitor upper electrode30b, respectively, and serve to apply a voltage to the capacitor Q.

Through the foregoing processes, the basic structure of the semiconductor device according to the embodiment is completed.

According to the semiconductor device manufacturing method described above, the capacitor Q with the n-type impurity diffusion region24serving as the lower electrode can be formed by simply adding the process of ion-implanting an impurity into the n-type impurity diffusion region24, the process described with reference toFIG. 1N, in addition to the manufacturing process for the respective MOS transistors to be formed in the transistor formation regions I and II. Accordingly, it makes it possible to readily manufacture a semiconductor device loaded with both the capacitor Q and the MOS transistors.

Incidentally, when the impurity concentration in the n-type impurity diffusion region24is increased, the depletion of the surface of the silicon substrate1in the region24can be suppressed, whereby it makes possible to suppress variations in the capacitance of the capacitor Q due to the depletion.

However, when the beam current to be applied during the ion-implantation of arsenic is increased in order to increase the impurity concentration in the n-type impurity diffusion region24, the damage inflicted on the silicon substrate1upon the ion-implantation becomes large. As a result, there is a fear that the amorphous layer1b(seeFIG. 1N) formed due to the damage inflicted at this time does not undergo sufficient crystallization due to the heat applied when the capacitor dielectric film25is formed by thermal oxidation, and that the quality of the capacitor dielectric film25degrades due to the influence of the uncrystallized amorphous film1b, and accordingly, that a decrease in the breakdown voltage of the dielectric film25is caused.

In order to avoid such an inconvenience, it is necessary to determine the upper limit for the amount of current to be applied when performing ion-implantation on the n-type impurity diffusion region24, and to ion-implant arsenic into the silicon substrate1in an amount of current not exceeding the upper limit. In view of this, the inventor of the present invention conducted the following examination in order to determine such an upper limit for the beam current.

FIG. 3is a graph obtained through examination of the relationship between a beam current and a thickness of an amorphous layer1bin the case where arsenic is ion-implanted into a silicon substrate1through a thermal oxidation film2having a thickness of 10 nm in the process ofFIG. 1N. Note that the thickness of the amorphous layer1bwas measured by an ellipsometry method.

Further, this examination was carried out with respect to three cases where the arsenic implantation energies are 50 keV, 60 keV, and 70 keV, respectively.

As shown inFIG. 3, with each the implantation energies, the thickness of the amorphous layer1bgradually decreases as the magnitude of the beam current decreases from 12 mA to 3 mA. However, when the beam current becomes less than 3 mA, the rate of the decrease in the thickness of the amorphous layer1bbecomes rapid.

Further,FIG. 4is a graph obtained through examination of the relationship between the beam current and the thickness of the amorphous layer1bin the case where arsenic is directly ion-implanted into the silicon substrate1without forming the thermal oxidation layer2.

As shown inFIG. 4, even in the case where the thermal oxidation film2is not formed, the amorphous layer1bundergoes a large decrease in thickness by making the beam current be less than 3 mA in the same manner as inFIG. 3.

From the results of theFIGS. 3 and 4, it is presumed that the breakdown voltage of the capacitor dielectric film25due to the amorphous layer1bcan be increased by making the beam current be less than 3 mA. To confirm this, the inventor of the present invention conducted the following experiment.

In this experiment, three silicon substrates1were prepared, and arsenic was ion-implanted into the respective silicon substrates1at different current amounts (1 mA, 3 mA, and 12 mA) to thereby form the n-type impurity diffusion region24. Then, after a plurality of capacitors Q were formed in each of the three silicon substrates, by gradually charging the respective capacitors Q, the number of capacitors Q that became defective as the capacitor dielectric film25broke down was determined with respect to each wafer.

FIG. 5shows the results. It should be noted that inFIG. 5, the horizontal axis represents the logarithm of the charge amount (QBD(C/cm2)) per unit area accumulated in the capacitors Q, and the vertical axis represents the cumulative frequency of the capacitors Q that became defective.

As shown inFIG. 5, in the case where the beam current is 12 mA, defective capacitors Q exist even in the region where the logarithm of the charge amount QBD is 10−5or less. From this, it is confirmed that the breakdown voltage of the capacitor dielectric film25actually decreases due to a large beam current.

On the other hand, in the case where the beam current is 3 mA, there exists no defective capacitor Q when the logarithm of the charge amount is less than 10−3.

Further, in the case where the beam current is the lowest at 1 mA, all the capacitors Q became defective at substantially the same time in the region where the logarithm of the charge amount is between 10−2and 10−1. This indicates that the breakdown voltage of the capacitor dielectric film25is increased in this case.

The above results make it clear that, in order to increase the breakdown voltage of the capacitor dielectric film25to enhance the breakdown voltage between electrodes of the capacitor Q, the beam current to be applied when forming the n-type impurity diffusion region24through ion implantation may be set to be lower than 3 mA.

Since such a low beam current cannot be realized with high-current ion implantation devices conventionally used in order to generate a high beam current on the order of 10 mA to 20 mA, the n-type impurity diffusion region24is preferably formed by using an ion implantation device adapted to generate a low beam current below 10 mA.

On the other hand, the lower limit for the beam current is set to 1 μA which is the smallest value of the beam current that can be generated by this ion implantation device.

It should be noted, however, that the product of the beam current and the implantation time becomes the dose amount in the ion implantation process, so a longer implantation time is required to attain a desired dose amount when the beam current is small. For this reason, in the actual production lines, the beam current to be applied is preferably determined within the range of 1 μA to 3 mA in balance with the throughput of the ion implantation process.

While in the foregoing embodiment of the present invention has been described in detail so far, the present invention is not limited to the one described above. For example, while in the above description the n-type impurity region24is formed on the p-well11, the p-type impurity diffusion region may be formed on the n-well to make this region serve as the lower electrode of the capacitor Q. In this case, BF2(boron fluoride) is employed as the kind of ion to be used when the p-type impurity diffusion region is formed through ion implantation.

According to the present invention, the beam current to be applied when the impurity diffusion region is formed in the semiconductor substrate through ion implantation is set to be equal to or more than 1 μA but less than 3 mA, whereby the breakdown voltage of the capacitor dielectric film on the impurity diffusion region can be enhanced and it makes it possible to form a high quality capacitor.