Method for forming deep trench isolation and related structure

According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure further comprises a trench situated in the substrate, where the trench has a first sidewall and a second sidewall in the substrate, and where the trench is situated directly underneath the field oxide region. According to this embodiment, the trench is used as a deep trench isolation region in the substrate and is typically filled with polysilicon. A thermally grown oxide liner is situated on the first and the second sidewalls of the trench, where the oxide liner is formed after removal of a hard mask. The hard mask may be densified TEOS oxide or HDP oxide and may be removed in an anisotropic dry etch process.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to forming isolation regions in semiconductor substrates.

2. Background Art

In a Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) process, deep trench isolation regions are typically formed to provide isolation between adjacent active regions of a semiconductor substrate. A deep trench isolation region may electrically isolate, for example, a bipolar transistor, such as a silicon-germanium heterojunction bipolar transistor, from an adjacent CMOS transistor, such as a PFET, fabricated on the same semiconductor substrate. Deep trench isolation regions may be formed on a substrate after formation of, for example, field oxide isolation regions, a buried layer, and an epitaxial layer of silicon.

In a typical conventional deep trench isolation process flow, a layer of silicon nitride (“nitride”) is deposited on a silicon substrate at a thickness of approximately 1500 Angstroms, for example. A hard mask having an approximate thickness of 4500 Angstroms and comprising densified tetraethylorthosilicate (“TEOS”) oxide or high-density plasma (“HDP”) oxide is then formed over the nitride layer. A photoresist mask is formed and patterned over the hard mask, and a trench is etched to a depth just below a field oxide region. After removal of the photoresist mask, the trench is further etched into the silicon substrate to a depth of between approximately 7.0 and 10.0 microns. During trench etching, the hard mask is also etched, which results in a reduction in hard mask thickness by approximately one half. After performance of cleaning and other preparatory steps as known in the art, a densified TEOS oxide liner is formed on the sidewalls of the trench and on the surface of the silicon substrate. The TEOS oxide liner may have a thickness of approximately 1000.0 Angstroms or greater.

Next, in the conventional deep trench isolation process discussed above, a conformal layer of polycrystalline silicon (also referred to as polysilicon) is deposited over the silicon substrate and trench. The layer of polysilicon is then recess etched in the trench to a depth of approximately 1500.0 Angstroms below the interface of the field oxide region and the nitride layer. The densified TEOS oxide liner situated on the sidewalls of the deep trench and on the silicon substrate surface is then removed in a wet etch process utilizing a buffered oxide etchant (“BOE”). However, since the polysilicon is recess etched to a depth of approximately 1500.0 Angstroms below the nitride layer, the BOE wet etch causes severe lateral etching of portions of the field oxide region situated on the sidewalls of the trench.

In an attempt to reduce the severe field oxide undercutting discussed above, semiconductor manufacturers have utilized a dry etch in place of the BOE wet etch. However, the dry etch approach causes formation of a non-uniform “mini-trench” or cavity on either side of the polysilicon-filled trench. As a result, removal of the densified TEOS oxide liner utilizing either the BOE wet etch or the dry etch approach causes undesirable deep mini-trenches or cavities to be formed in the field oxide.

Thus, there is a need in the art for effective deep trench isolation in a semiconductor substrate.

SUMMARY OF THE INVENTION

The present invention is directed to method for forming deep trench isolation and related structure. The present invention addresses and resolves the need in the art for effective deep trench isolation in a semiconductor substrate.

According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a field oxide region situated in the substrate, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The field oxide region may have a thickness of, for example, approximately 3000.0 Angstroms. The structure further comprises a trench situated in the substrate, where the trench has a first sidewall and a second sidewall in the substrate, and where the trench is situated directly underneath the field oxide region. According to this exemplary embodiment, the trench is used as a deep trench isolation region in the substrate and is typically filled with polysilicon. The trench may have a depth of, for example, between approximately 3.0 microns and approximately 7.0 microns and may have a width of, for example, approximately 1.0 micron.

According to this exemplary embodiment, the structure further comprises a thermally grown oxide liner situated on the first and the second sidewalls of the trench, where the oxide liner is formed after removal of a hard mask. The oxide line may have a thickness of, for example, approximately 1000.0 Angstroms. The hard mask may be densified TEOS oxide or HDP oxide and may be removed in an anisotropic dry etch process, for example. According to one embodiment, the invention is a method for achieving the above-described structure. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to method for forming deep trench isolation and related structure. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order to not obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.

The present invention involves a method of forming deep trench isolation that causes substantially no lateral etching of field oxide. As will be discussed in detail below, by causing substantially no lateral etching of field oxide, the present invention advantageously achieves a final topography that is substantially flat over a deep trench isolation region. The innovative method of the present invention can be applied in, for example, BiCMOS applications to achieve effective formation of deep trench isolation regions.

FIG. 1shows a flowchart illustrating an exemplary method according to an embodiment of the present invention. Certain details and features have been left out of flowchart100that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. Steps150through164indicated in flowchart100are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart100. It is noted that the processing steps shown in flowchart100are performed on a wafer, which, prior to step150, includes field oxide regions, a buried layer, and an epitaxial layer situated over the buried layer.

Moreover, structures250through264inFIGS. 2A through 2Hillustrate the result of performing, on the semiconductor structure discussed above, steps150through164of flowchart100, respectively. For example, structure250shows the semiconductor structure discussed above after processing step150, structure252shows structure250after the processing of step152, structure254shows structure252after the processing of step154, and so forth. It is noted that although formation of only one deep trench isolation region is specifically discussed herein to preserve brevity, multiple deep trench isolation regions can be formed in a substrate utilizing the innovative process of the present invention.

Referring now toFIG. 2A, structure250ofFIG. 2Ashows an exemplary structure including a silicon substrate that includes field oxide regions, a buried layer, and an epitaxial layer, after completion of step150of flowchart100inFIG. 1. In structure250, buried layer204, epitaxial layer206, and field oxide regions208,210, and212are formed in silicon substrate202. Buried layer204is formed in silicon substrate202in a manner known in the art and can comprise, for example, heavily doped N-type material. Epitaxial layer206can comprise single-crystal silicon, which can be epitaxially grown on silicon substrate202in a manner known in the art. Field oxide regions208,210, and212comprise silicon oxide and may be formed in silicon substrate202in a manner known in the art.

Continuing with step150inFIG. 1and structure250inFIG. 2A, at step150of flowchart100, silicon nitride (“nitride”) layer214is deposited on top surface218of silicon substrate202and hard mask216is formed on nitride layer214. Nitride layer214can be formed, for example, by depositing a layer of nitride on top surface218of silicon substrate202in a low pressure chemical vapor deposition (“LPCVD”) process and can have a thickness of approximately 1500.0 Angstroms, for example. Hard mask216can comprise densified oxide, which can be formed by depositing TEOS oxide on nitride layer214in an LPCVD process and densifying the TEOS oxide in a manner known in the art. In one embodiment, hard mask216can comprise high-density plasma (“HDP”) oxide. The thickness of hard mask216can be, for example, approximately 4500.0 Angstroms. The result of step150of flowchart100is illustrated by structure250inFIG. 2A.

Referring to step152inFIG. 1and structure252inFIG. 2B, at step152of flowchart100, a photoresist mask is deposited and patterned on hard mask216, the patterned photoresist mask is utilized to form trench220having an initial depth, and the photoresist mask is then removed. The photoresist mask can be deposited and patterned on hard mask216in a manner known in the art to achieve a trench opening in the photoresist mask having a width substantially equal to a critical dimension (“CD”). In a first etch step, trench220can be formed by utilizing an etchant such as CF4/CHF3/Ar or other appropriate etchant and adjusting the etchant chemistry to sequentially etch through hard mask216, nitride layer214, field oxide region208, and etch a short distance into epitaxial layer206. The resulting trench220formed by the etch step discussed above defines sidewalls222and224and bottom surface226. Bottom surface226of trench220can extend into epitaxial layer206to an initial depth a short distance below field oxide region208. Field oxide portions209and211, which are situated adjacent to sidewalls222and224, respectively, are formed as a result of the etch step discussed above.

In a second etch step, the photoresist mask can be removed from hard mask216and polymer residue formed as a result of the first etch step discussed above can be removed from sidewalls222and224of trench220in a wet strip utilizing an appropriate etchant as known in the art. The width of trench220is determined by the CD of the trench opening patterned in the photoresist mask discussed above, and can be, for example, approximately 1.0 micron. The result of step152of flowchart100is illustrated by structure252inFIG. 2B. It is noted that inFIG. 2Band in subsequent figures, only trench220is specifically discussed to preserve brevity.

Referring to step154inFIG. 1and structure254inFIG. 2C, at step154of flowchart100, hard mask216is utilized to perform a trench etch to define a final depth of trench220. The trench etch can be performed by utilizing an appropriate etchant to etch silicon in epitaxial layer206to increase the depth of trench220to a final depth of, for example, approximately 7.0 microns. In one embodiment, the trench etch discussed above can be utilized to increase the depth of trench220to a final depth of between approximately 3.0 and approximately 7.0 microns. During the trench etch, a portion of hard mask216is also removed, which reduces the thickness of hard mask216by approximately one half. By way of example, hard mask216can be reduced from an initial thickness of approximately 4500.0 Angstroms to a thickness of approximately 2250.0 Angstroms as a result of the trench etch. After performance of the trench etch discussed above, a post trench clean can be performed by utilizing a diluted HF dip or other appropriate etchant to remove approximately 200.0 Angstroms of oxide from sidewalls222and224of trench220. The result of step154of flowchart100is illustrated by structure254inFIG. 2C.

Referring to step156inFIG. 1and structure256inFIG. 2D, at step156of flowchart100, hard mask216is removed. In the present embodiment, hard mask216can be removed in an anisotropic dry etch process that is selective to silicon and nitride and utilizes an etchant such as C4F8/CO/Ar or other appropriate etchant. As a result of the high selectivity of the anisotropic dry etch process, the etchant does not significantly damage nitride layer214or silicon situated at bottom surface226of trench220. By way of example, the anisotropic dry etch process causes a loss of less than 100.0 Angstroms of nitride in nitride layer214. By utilizing an anisotropic dry etch to remove hard mask216, the present invention can maintain a uniform trench width of approximately 1.0 micron, for example. In contrast, in a process utilizing a wet etch to remove hard mask216, portions of field oxide208can be etched, which can undesirably alter the shape of trench220. After removal of hard mask216, sidewalls222and224of trench220can be cleaned by utilizing, for example, a plasma etch and an HF strip to remove polymer by-products formed on sidewalls222and224during etching of hard mask216. After removal of hard mask216, sidewalls222and224of trench220can be cleaned by utilizing, for example, a plasma etch and an HF strip to remove polymer by-products formed on sidewalls222and224during etching of hard mask216. The result of step156of flowchart100is illustrated by structure256inFIG. 2D.

Referring to step158inFIG. 1and structure258inFIG. 2E, at step158of flowchart100, a channel stop implant is performed and oxide liner228is thermally grown on sidewalls222and224and bottom surface226of trench220and over nitride layer214situated on substrate202.

In the channel stop implant performed in step158, a dopant such as boron, for example, can be implanted in bottom surface226of trench220to prevent current leakage. A wet strip can be performed to eliminate carbon and metal contamination resulting from the channel stop implant. Also, prior to thermally growing oxide liner228, a thirty-second HF preclean can be performed to appropriately clean sidewalls222and224and bottom surface226of trench220.

Next, oxide liner228is formed by thermally growing oxide on sidewalls222and224and bottom surface226of trench220. The layer of thermal oxide can be densified by utilizing, for example, a temperature of approximately 750° C. and an inert gas such as nitrogen to complete formation of oxide liner228. By way of example, oxide liner228can have a thickness of approximately 1000.0 Angstroms.

Since oxide liner228comprises thermally grown oxide, oxide liner228is not formed on nitride layer214situated on top surface218of silicon substrate202. By not forming oxide liner228on nitride layer214, a buffered oxide echant (“BOE”) wet strip does not need to be performed in a subsequent step to remove oxide liner228. As a result, the present invention advantageously eliminates field oxide lateral etching or undercutting caused by a BOE wet strip. By eliminating field oxide lateral etching, the present invention advantageously achieves a substantially flat final topography over a subsequently formed deep trench isolation region. The result of step158of flowchart100is illustrated by structure258inFIG. 2E.

Referring to step160inFIG. 1and structure260inFIG. 2F, at step160of flowchart100, a layer of polysilicon is conformally deposited over substrate202and etched in an etch back process. The layer of polysilicon can be conformally deposited over substrate202at a thickness of, for example, approximately 1.5 microns. As a result of conformal polysilicon deposition process discussed above, deposited polysilicon fills trench220. In the etch back process, a break-through etch is first performed utilizing, for example, a CF4 etch chemistry to break through an oxide skin that is usually formed on the layer of polysilicon. Next, a main etch is performed utilizing, for example, an SF6/O2 etch chemistry, followed by an over etch utilizing, for example, a C12/HBr etch chemistry. As a result of the etch back process discussed above, the layer of polysilicon is etched back to depth230inside trench220to form polysilicon portion232. Depth230can be, for example, approximately 1500.0 Angstroms below interface234, which is situated at a boundary of field oxide portion209(or field oxide portion211) and nitride layer214. Since the respective etch chemistries utilized to perform the main etch and the over etch discussed above are highly selective to oxide, minimal etching of oxide liner228occurs during the polysilicon etch back process. The result of step160of flowchart100is illustrated by structure260inFIG. 2F.

Referring to step162inFIG. 1and structure262inFIG. 2G, at step162of flowchart100, oxide is grown inside trench220to form continuous field oxide region240. As a result, grown oxide in trench220merges with field oxide portions209and211to form continuous field oxide region240. By way of example, field oxide region240can have a thickness of approximately 3000.0 Angstroms. Since substantially no lateral etching occurs in field oxide portions209and211, substantially no cavities are formed on top surface236of field oxide region240, which is formed when field oxide portions209and211are joined by oxide grown in trench220.

As discussed above, hard mask216is removed at step156. By removing hard mask216at step156, the present invention's deep trench isolation process advantageously avoids lateral etching in field oxide portions209and211that can occur as a result of removing hard mask216. As a result, the present invention advantageously achieves a field oxide region, i.e. field oxide region240, having substantially no cavities on its top surface, i.e. top surface236.

In contrast, in a conventional deep trench isolation process, the hard mask is generally removed after the polysilicon recess etch, which occurs at step160. In addition, in the conventional process, the oxide liner is removed with the hard mask, which further increases the thickness of the material that must be removed in an etching process. Furthermore, since, in the conventional process, the hard mask has a non-uniform thickness as a result of hard mask etching that occurs during trench etching, the material to be removed has a non-uniform thickness as well as an overall increased thickness. As a result, in the conventional process, a wet strip, such as a BOE wet strip, cannot be used to remove the hard mask and oxide liner without causing severe field oxide undercutting. Thus, in the conventional process, a dry etch process is used to remove the hard mask and oxide liner. However, the dry etch process results in formation of undesirable deep cavities in the top surface of field oxide situated above the deep trench isolation region. The result of step162of flowchart100is illustrated by structure262inFIG. 2G.

Referring to step164inFIG. 1and structure264inFIG. 2G, at step164of flowchart100, nitride layer214is removed. Nitride layer214can be removed by utilizing a phosphoric etch process or other appropriate etch process as known in the art. As a result of the present invention, deep trench isolation region242is effectively formed underneath field oxide region240. Thus, by effectively removing the hard mask prior to a polysilicon recess etch and preserving an oxide liner comprising thermally grown oxide, the present invention advantageously achieves a field oxide region, i.e. field oxide region240, having substantially no cavities formed on its top surface. As a result, the present invention advantageously achieves a substantially flat topography over the deep trench isolation region.

Thus, method for forming deep trench isolation and related structure have been described.