Failure detection circuit for a vehicle anti-skid braking system

An anti-skid braking system including a plurality of independent solenoid energizing circuits which are controlled in accordance with the outputs of sensors on separate wheels of a vehicle, has a failure detection circuit comprising a timer triggered into operation each time any one of the solenoids is energized, and reset when a back e.m.f. generated by the deactivation of any solenoid is detected. If the timer is not reset within a fixed period the system is disabled and a warning lamp is energized. The system also includes a circuit utilizing the back e.m.f. signals for testing the system each time it is switched on.

It is known to control the brakes of individual wheels or pairs of wheels 
of a vehicle by means of a multi-channel anti-skid system which releases 
the brake for a particular wheel or pair of wheels when that wheel or pair 
of wheels decelerates too rapidly, or which releases the brake for a 
particular wheel or pair of wheels when that wheel or pair of wheels is 
rotating at a speed significantly less than the average wheel speed. 
With such a system there is a danger that a failure in any channel of the 
system could cause the associated brake to be permanently disabled and 
this is obviously a dangerous condition. It is an object of the invention 
to provide a failure detection circuit for detecting such a condition. 
A vehicle anti-skid braking system in accordance with the invention 
includes a plurality of wheel speed sensors, a plurality of wheel slip 
detection circuits associated with the respective wheel speed sensors, a 
plurality of brake release solenoids connected to the respective slip 
detection circuits so as to energise a solenoid if the corresponding slip 
detection circuit detects slippage of the associated wheel, and a failure 
detection circuit comprising solenoid energisation detection means 
connected to said solenoids and producing an output signal when any one of 
the solenoids is energised, a timing circuit connected to the solenoid 
energisation detection means so as to be triggered into operation thereby, 
warning means operable by said timing circuit if the latter remains in 
operation for more than a predetermined time, means for detecting the back 
e.m.f. produced when each solenoid is switched off, and timer circuit 
reset means controlled by said back e.m.f. detecting means for resetting 
the timer circuit when any solenoid is switched off. 
The solenoids may be connected as the emitter loads of emitter follower 
power transistors forming the output stages of the detection circuits. In 
this case the solenoid energisation detector means may comprise an OR gate 
having its input terminals connected to the solenoid-emitter junctions. 
These junctions are preferably connected by biasing resistors to a signal 
source so that the junctions are normally held at a low voltage by current 
leakage through the resistor/solenoid circuits but the potential at a 
junction will change to provide an input signal to the OR gate if any 
solenoid becomes open circuit. 
The back e.m.f. detecting means may also be used to supply a signal when 
all the solenoids are switched off simultaneously during a system 
switch-on check sequence. By means of a simple timer circuit the solenoids 
can be energised during initial switch-on for a short period and then 
inhibited simultaneously. An AND gate (which may consist quite simply of 
an array of diodes and a single resistor) detects the simultaneous 
appearance of the back e.m.f. signals and causes a warning lamp to be lit 
briefly to assure the driver of the vehicle that the warning lamp and the 
fault detection system is operative.

Referring firstly to FIG. 1 the system, which is intended for a road 
vehicle has four wheel speed sensors 10, 11, 12, 13 which produce a.c. 
output signals of frequency proportional to the respective wheel speeds. 
Each sensor is connected to a amplifier/converter circuit 14, 15, 16 or 17 
which amplifies the a.c. signal to clipping and converts it to a d.c. 
signal proportional to the frequency of the a.c. signal. The output of 
each amplifier/converter circuit is connected to a corresponding control 
channel 18, 19, 20 or 21 which includes a differentiating circuit and a 
threshold circuit such that when the d.c. output of the corresponding 
amplifier/converter falls at more than a predetermined rate the control 
channel produces an output signal. 
There are three independently operable solenoids 22, 23, 24 driven by three 
drive circuits 25, 26, 27. The drive circuits 25 and 26 are connected 
respectively to the control channels 18 and 19 which are associated with 
the two front wheels of the vehicle and the corresponding solenoids 22, 23 
when energised release the brakes associated with the respective front 
brakes. The drive circuit 27 is connected to both control channels 20 and 
21 so that the solenoid 24 is energised to release both rear brakes when 
either rear wheel decelerates sufficiently rapidly to indicate incipient 
wheel slip. 
Turning now to FIG. 2, the solenoid drive circuit 25 is shown in detail and 
the circuits 26, 27 are identical. The circuit 25 includes an n-p-n power 
transistor 28 connected as an emitter follower with the solenoid 22 as its 
emitter load. Thus the emitter of the transistor 28 is connected by the 
solenoid 22 to an earth rail and its collector connected to a positive 
supply rail 29. The base of the transistor 28 is connected to the 
collector of a p-n-p driver transistor 30, the emitter of which is 
connected to the rail 29. The base of the transistor 30 is connected to 
the common point of two resistors R.sub.1, R.sub.2 connected in series 
between an input terminal 31 (connected to the associated control channel) 
and the rail 29. 
The base of the transistor 28 is also connected to the anode of a zener 
diode 32 the cathode of which is connected to the base of a p-n-p 
transistor 33 which has its emitter connected to the rail 29 and its 
collector connected to the earth rail via a resistor R.sub.4 and also to a 
terminal 35. 
A resistor R.sub.3 is connected between the rail 29 and the emitter of the 
transistor 28 but is of sufficiently high ohmic value to prevent actuation 
of the solenoid 22. 
An OR gate 36 has three input terminals connected to the emitter of the 
transistor 28 and to corresponding terminals of the circuits 26, 27 
respectively, so that the gate 36 produces an output whenever any of the 
solenoids 22, 23, 24 is energised. In addition the gate 36 will produce an 
output if any of the solenoids 22, 23, 24 is open circuit, by virtue of 
the resistor R.sub.3 and corresponding resistors R.sub.3 ' and R.sub.3 " 
of the circuits 26, 27. The output of the gate 36 is connected to the 
input terminal 37a of an electronic timer circuit 37 of known form which 
produces an output at its output terminal 37b if a signal is maintained at 
its input terminal 37a for a predetermined time unless a signal is applied 
in the meantime to a reset terminal 37c. 
The terminal 35 of the circuit 25 and corresponding terminals 35' and 35" 
of the circuits 26 and 27 are connected to the anodes of three diodes 
D.sub.1, D.sub.2 and D.sub.3 which have their cathodes interconnected and 
connected by a resistor chain R.sub.5, R.sub.6 to the earth rail. The 
common point of the resistors R.sub.5, R.sub.6 is connected to the base of 
a n-p-n transistor 38 which has its emitter connected to the earth rail 
and its collector connected by a resistor R.sub.7 to the reset terminal 
37c. The terminal 37c is also connected by a resistor R.sub.8 to the 
emitter of a p-n-p transistor 39 with its base connected to the collector 
of the transistor 38 and its collector connected to the base of the 
transistor 38. A pulse from any of the terminals 35, 35' and 35" will 
cause the transistor 38 to switch on and transistor 39 will latch 
transistor 38 on as long as current can flow from the reset terminal 37c. 
In use, each time a solenoid 22, 23 or 24 is energised an input is 
delivered to the terminal 37a so that operation of the timer circuit 
commences. When the solenoid is deenergised current will continue to flow 
therein owing to its inductance and in these circumstances the potential 
at the emitter of the transistor 28 will go negative until the zener diode 
32 breaks down and causes the transistor 33 to conduct. The transistor 28 
now receives base current via the base-emitter junction of the transistor 
33 and the zener diode and thus permits current to continue flowing 
through the solenoid until the energy stored thereby is dissipated. Thus 
the back e.m.f. generated by the solenoid 22 on de-energisation thereof is 
detected and for the duration of the dissipation of the energy therein a 
positive going signal appears at the terminal 35. This signal triggers the 
transistor 38 and resets the timer circuit 37. It will be appreciated that 
any solenoid being de-energised will reset the timer even though two or 
more of the solenoids were energised prior to resetting. 
As shown in FIG. 1 an output at the terminal 37b operates a failure circuit 
40 which both disables the whole anti-skid system via a power trip 41 and 
illuminates a warning lamp circuit 42. This will occur whenever the timer 
circuit 37 runs its predetermined time without being reset either as a 
result of a malfunction of the control channel/driver circuit or as a 
result of a solenoid going open circuit. 
The system also includes various other check circuits for example a rear 
wheel lock detector circuit 43 which is connected to the failure circuit 
40 both to disable the antiskid system and illuminates the lamp and two 
converter output comparators 44, 45 which compare the analogue signals 
from the converters 14, 15, 16, 17 and illuminate the lamp if these differ 
greatly. 
Furthermore an arrangement is provided for testing the system each time it 
is switched on. This arrangement includes a test pulse generator 46 which 
applies a ramp waveform to the control channels 18, 19, 20 and 21 at 
switch-on and also sets a memory device 47 via a timer 48. A timing 
circuit 49 commences operation at the same time, a capacitor 50 being 
charged from the supply via a resistor 51 and a diode 52 bridged by a 
resistor 53. A short time after switch-on (e.g. 30mS) the voltage on 
capacitor 50 becomes sufficient to fire a trigger circuit 54 which lights 
the lamp circuit 42 and also applies a pulse simultaneously to all the 
drive circuits 25, 26, 27 to turn these off. Thus the terminals 35, 35', 
and 35" produce positive going output signals simultaneously and these 
reset the memory 47 via diodes D.sub.4, D.sub.5, D.sub.6 having their 
cathodes connected to the terminals 35, 35' and 35" respectively and their 
anodes connected via a resistor R.sub.9 to the rail and also to the memory 
47. Resetting of the memory 47 causes the capacitor 50 to start 
discharging slowly via the resistor 53 until, after about one second the 
trigger circuit 54 resets, the lamp is extinguished and the solenoid 
inhibit signal is removed. During this period the lamp is noticeably 
checked and the solenoid drive disabled to prevent operation for longer 
than 30MS, even though the initial pulse may last for several hundred 
milliseconds and would otherwise remove all service braking for a 
dangerous duration at each switch on. Should the solenoid fail to switch 
off simultaneously the memory 47 is not reset and the trigger 54 does not 
reset, thereby leaving the solenoids inhibited and the anti-skid system 
disabled.