Semiconductor manufacturing apparatus and method for transferring wafer

A semiconductor manufacturing apparatus includes one or more process modules, a scheduler, and a transfer controller. A product wafer of a lot that is transferred from a load port to one of the one or more process modules is replenished such that a total number of wafers that are simultaneously processed in the one or more process modules becomes N. When an advance lot being processed and a post lot to be processed subsequent to the advance lot have a same processing condition, the scheduler creates the transfer plan to replenish with the product wafer of the post lot instead of a dummy wafer such that the transfer controller transfers the product wafer and the dummy wafer to the one or more process modules according to the created transfer plan.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority from Japanese Patent Application No. 2020-045740 filed on Mar. 16, 2020 with the Japan Patent Office, the disclosure of which is incorporated herein in its entirety by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor manufacturing apparatus and a method for transferring a wafer.

BACKGROUND

In a semiconductor manufacturing apparatus in the related art, for example, in a wafer transporting method in which wafers loaded in a plurality of cassettes are transported from the cassettes to a boat holding the wafers in a multiple tiers, the shortage of wafers on the boat is replenished with dummy wafers in order to perform the processing of the wafer under the same conditions (e.g., the number of the wafers on the boat or arrangement) (e.g., see Japanese Laid-Open Patent Publication No. 08-340040).

SUMMARY

An aspect of the present disclosure is a semiconductor manufacturing apparatus including at least one process modules configured to simultaneously process a group of N (N≥2) wafers; a scheduler configured to create a transfer plan of the wafers; and a transfer controller configured to control a wafer transfer of the group of N (N≥2) wafers. A product wafer of a lot that is transferred from a load port to one of the one or more process modules is replenished such that a total number of wafers that are simultaneously processed in the one or more process modules becomes N. When an advance lot being processed and a post lot to be processed subsequent to the advance lot have a same processing condition, the scheduler creates the transfer plan to replenish with the product wafer of the post lot instead of a dummy wafer such that the transfer controller transfers the product wafer and the dummy wafer to the one or more process modules according to the created transfer plan.

DETAILED DESCRIPTION

FIG.1is a configuration view of an example of an information processing system according to the present embodiment. In an information processing system1illustrated inFIG.1, a host computer10and one or more semiconductor manufacturing apparatuses12are connected via a communicable network18such as a local area network (LAN).

The host computer10is an example of a man-machine interface (MMI) that provides information on the semiconductor manufacturing apparatus12to an operator. The host computer10receives a parameter setting such as a system parameter setting from the operator. Further, the host computer10receives an instruction with respect to product management (lot management) or production management (batch management) from the operator.

According to a job execution request from the host computer10, the semiconductor manufacturing apparatus12transfers a wafer, which is a process target, to a process module (to be described later), and performs the process having characteristics according to the process module. In the present embodiment, the wafer transferred to the process module includes a product wafer that is lot-controlled, and a dummy wafer that fills a vacant slot of the process module. The name of the dummy wafer is an example, and may have another name such as a monitor wafer or a test wafer.

Further, the information processing system1inFIG.1is an example, and it goes without saying that there are various examples of a system configuration depending on the application or purpose. The distinction of devices such as the host computer10and the semiconductor manufacturing apparatus12inFIG.1is an example.

For example, the information processing system1may have various configurations such as a configuration in which the host computer10and the semiconductor manufacturing apparatus12are integrated or a further divided configuration. Further, the host computer10may treat a plurality of semiconductor manufacturing apparatuses12integrally as in the information processing system1inFIG.1, or may be provided one-to-one with the semiconductor manufacturing apparatus12.

The host computer10of the information processing system1illustrated inFIG.1is implemented by, for example, a computer having a hardware configuration illustrated inFIG.2.FIG.2is a hardware configuration view of an example of a compute.

A computer500inFIG.2includes, for example, an input device501, an output device502, an external interface (I/F)503, a random access memory (RAM)504, a read only memory (ROM)505, a central processing unit (CPU)506, a communication I/F507, and a hard disk drive (HDD)508, which are connected to each other via bus B. The input device501and the output device502may connected to use when necessary.

The input device501is, for example, a keyboard or a mouse, or a touch panel, and is used by, for example, an operator to input each operation signal. The output device502is, for example, a display, and displays a processing result by the computer500. The communication I/F507is an interface that connects the computer500to a network18. The HDD508is an example of a non-volatile storage device that stores a program or data.

The external I/F503is an interface with an external device. The computer500may read and/or write to a recording medium503asuch as a secure digital (SD) memory card via the external I/F503. The ROM505is an example of a non-volatile semiconductor memory (a storage device) that stores a program or data. The RAM504is an example of a volatile semiconductor memory (a storage device) that temporarily retains a program or data.

The CPU506is an arithmetic device that reads out a program or data from the storage device such as the ROM505or the HDD508onto the RAM504and executes a process so as to implement control or functions of the entire computer500.

The host computer10inFIG.1may implement various functions by, for example, the hardware configuration of the computer500inFIG.2

Further, the semiconductor manufacturing apparatus12of the information processing system1illustrated inFIG.1is implemented by, for example, a hardware configuration illustrated inFIG.3.FIG.3is a hardware configuration view of an example of the semiconductor manufacturing apparatus.

The semiconductor manufacturing apparatus12inFIG.3is configured to include a host communication unit601, a device control controller unit602, an acting force controller603, a front-end module604, a wafer transfer unit605, and a process module606.

The host communication unit601is an interface with the host computer10. The device control controller unit602communicates with the host computer10via the host communication unit601. The device control controller unit602controls the acting force controller603, the front-end module604, the wafer transfer unit605, and the process module606in accordance with, for example, various requests received from the host computer10.

The acting force controller603is configured to control the acting force (e.g., electric power, water, and gas required for manufacturing a product). The front-end module604is configured to include a load port that is an interface portion that supplies a wafer to the semiconductor manufacturing apparatus12. The load port is a portion that introduces the wafer into the semiconductor manufacturing apparatus12from the outside or takes out the wafer from the inside of the semiconductor manufacturing apparatus12to the outside. The load port introduces a carrier of wafer such as a front opening unified pod (FOUP) transmitted from the previous process to the semiconductor manufacturing apparatus12.

The wafer transfer unit605is configured by, for example, a transfer robot or a transporter that transfers the wafer between the load port and the process module606. The process module606is configured to include a reaction container such as a chamber or processing chamber capable of processing a plurality of wafers at the same time. The semiconductor manufacturing apparatus12inFIG.1may implement various functions (to be described later) by, for example, the hardware configuration inFIG.3.

The host computer10and the semiconductor manufacturing apparatus12of the information processing system1according to the present embodiment is implemented by, for example, a functional block inFIG.4.FIG.4is a functional block diagram of an example of the information processing system according to the present embodiment. In the functional block diagram inFIG.4, illustrations of configurations unnecessary for the description of the present embodiment are omitted.

The host computer10executes a program for the host computer10to implement a host computer side communication function unit20, a UI function unit22, a system parameter setting function unit24, and a job execution request function unit26.

The host computer side communication function unit20communicates with the semiconductor manufacturing apparatus12. The UI function unit22provides a user interface (UI) to an operator. The system parameter setting function unit24receives a system parameter setting (to be described later) from the operator. Further, the job execution request function unit26requests the semiconductor manufacturing apparatus12to execute a job in accordance with instructions with respect to the product management (lot management) or the production management (batch management) from the operator.

The semiconductor manufacturing apparatus12executes a program for the semiconductor manufacturing apparatus12to implement a semiconductor manufacturing apparatus side communication function unit40, a lot management function unit42, a recipe management function unit44, a schedule function unit46, an acting force control function unit48, a front-end module control function unit50, a transfer control function unit52, and a process module control function unit54.

The semiconductor manufacturing apparatus side communication function unit40communicates with the host computer10. The lot management function unit42performs the lot management and the batch management in accordance with the request for the job execution from the host computer. The recipe management function unit44manages the processing conditions of the process for the wafers, such as a command, a setting, and a parameter for the semiconductor manufacturing apparatus12as a recipe.

The schedule function unit46creates a transfer plan for the wafers (product wafers and dummy wafers). The transfer plan for the wafer indicates the transfer order or the transfer path when the wafer is transferred between the load port and the process module606.

The acting force control function unit48controls the acting force controller603in accordance with, for example, the recipe. The front-end module control function unit50controls the front-end module604in accordance with, for example, the transfer plan. The transfer control function unit52controls the wafer transfer unit605such that the wafer is transferred between the load port and the process module606in accordance with, for example, the transfer plan. The process module control function unit54controls the process module606in accordance with, for example, the recipe to process the wafer loaded in the slot of the process module606.

FIG.5is a view of an example for explaining an outline of wafer transfer in the semiconductor manufacturing apparatus according to the present embodiment. The semiconductor manufacturing apparatus12inFIG.5includes two process modules100aand100b. The process modules100aand100binclude a plurality of slots (e.g., six or the like), respectively. The process modules100aand100bsimultaneously process the wafer transferred according to the transfer plan and loaded in the slot. Hereinafter, descriptions will be made on an example in which the process modules100aand100bhave six slots, respectively.

The semiconductor manufacturing apparatus12inFIG.5includes four load ports132ato132d. A FOUP, which is an example of a wafer carrier, may be placed in each of the load ports132ato132d.FIG.5illustrates an example in which a FOUP134ais placed in the load port132aand a FOUP134dis placed in the load port132d. In the description in the following, the FOUP placed in the load ports132ato132dwill be separately referred to as the FOUPs134ato134d.

In the FOUP, the product wafer corresponding to the lot managed by the lot management function unit42is stored so as to be able to taken out by a loader arm138. “00/00” illustrated in the FOUPs134aand134dinFIG.5refers to “the number of the wafers returned to FOUP/the number of wafers carried out from FOUP.”

A loader module130of the semiconductor manufacturing apparatus12inFIG.5includes the load ports132ato132d, dummy wafer stockers136, a loader arm138, and an oriental unit140. In the dummy wafer stocker136, a dummy wafer is stored so as to be taken out by the loader arm138. The oriental unit140is used to perform positional alignment by rotating the wafer.

The product wafer is taken out from the FOUP in the load ports132ato132dby the loader arm138, and, after performing the positional alignment by the oriental unit140, is loaded in the slot of the process module100aor100bvia any one of load lock modules120ato120c, and a transfer module arm112of a transfer module110.

For example, as illustrated inFIGS.6A and6B, the product wafer and the dummy wafer are loaded in the process modules100aand100b.FIGS.6A and6Bare views of examples for explaining the product wafers and the dummy wafers loaded in the process module. InFIGS.6A and6B, an example in which a same recipe is used in the consecutive lot, the number of the produce wafers of the advance lot is 25, and the number of the wafers of the post lot is five.

It is assumed that the product wafer of the advance lot is stored, for example, in the FOUP134ain the load port132a. Further, it is assumed that the product wafer of the post lot is stored, for example, in the FOUP134din the load port132b. A three-digit number is given to the product wafers and dummy wafers inFIGS.6A and6B, and the load ports132ato132dfrom which the product wafers are taken out, or the dummy wafer stocker136from which the dummy wafers are taken out may be identified by the hundreds digit. Further, the tens place and the units place of the three-digit number given to the product wafer inFIGS.6A and6Bare serial numbers of the product wafer given to each lot. Further, the tens digit and the ones digit given to the dummy wafers inFIGS.6A and6Bare serial numbers of the dummy wafers.

FIGS.6A and6Billustrate the examples in which “1” is given to the hundreds digit of the product wafer taken out from the load port132a, and “2” is given to the hundreds digit of the product wafer taken out from the load port132b. Further, the examples in which “5” is given to the hundreds digit of the dummy wafer taken out from the dummy wafer stocker136are illustrated. For example, the wafer to which a three-digit number “125” is given refers to a product wafer having the serial number “25” taken out from the load port132a. The wafer to which a three-digit number “205” is given refers to a product wafer having the serial number “5” taken out from the load port132b. The wafer to which a three-digit number “506” is given refers to a dummy wafer having the serial number “6” taken out from the dummy wafer stocker136.

For example, in a case of a lot having 25 product wafers, the semiconductor manufacturing apparatus12divides the 25 product wafers into wafer groups having six wafers respectively, and processed in the order in the process module100aor100b. Therefore, the last wafer group is constituted by one product wafer having the serial number “25,” and thus, as illustrated in the process module100ainFIG.6A, the empty slots are filled with dummy wafers having the serial numbers “6” to “10.”

Further, for example, in a case of a lot having five product wafers, the number of the product wafers is less than six, which is required for the wafer group, and thus, as illustrated in the process module100binFIG.6A, the empty slots are filled with a dummy wafer having a serial number “12.” In the example inFIG.6A, when the number of the product wafers corresponding to the lot is not a multiple of six, dummy wafers are always used.

Therefore, in the semiconductor manufacturing apparatus12according to the present embodiment, as illustrated inFIG.6B, when the post lot subsequent to the advance lot has the same recipe, the product wafer of the post lot is used instead of the dummy wafer under predetermined valid conditions. For example, inFIG.6B, five empty slots of the last wafer group of the advance lot is replenished with five product wafers of the post lot instead of the dummy wafers.

Therefore, in the semiconductor manufacturing apparatus12according to the present embodiment, the number of the dummy wafers used may be reduced, and a turn around time (TAT) may be improved by the increase of the number of the process wafers that are process processed.

The function of using the product wafer of the post lot instead of the dummy wafer (hereinafter, the same product wafer replenishing function) may be switched between invalid and valid.

For example, as illustrated inFIGS.7A to7F, when the product wafers of the last wafer group of the advance lot are insufficient, the semiconductor manufacturing apparatus12in which the “same product wafer replenishing function” is valid uses the product wafers of the post lot for replenishment instead of the dummy wafers.

FIGS.7A to7Fare views of an example for explaining an operation example of the “same product wafer replenishing function.”FIG.7Aillustrates an example in which a FOUP in which nine product wafers are stored is placed in the load port132b, and a FOUP in which three product wafers are stored is placed in the load port132c. The operator manipulates the host computer10to start a job execution by designating the same recipe for the lot (advance lot) corresponding to the nine product wafers in the load port132band the lot (post lot) corresponding to the three product wafers in the load port132c.

FIG.7Billustrates a state in which the “201” product wafer is taken out from the FOUP in the load port132b. The product wafer taken out from the FOUP in the load port132bis transferred toward the process module100avia the loader arm, the oriental unit, the load lock module, and the transfer module arm112of the transfer module110.

FIG.7Cillustrates a state in which, subsequent to the “201” wafer product, the “202” to “205” product wafers are sequentially taken out from the FOUP in the load port132b, and are transferred toward the process module100avia the loader arm, the oriental unit, the load lock module, and the transfer module arm112of the transfer module110.

FIG.7Dillustrates a state in which, subsequent to the “206” product wafer, the “207” product wafer is taken out from the FOUP in the load port132b. The “207” product wafer taken out from the FOUP in the load port132bis transferred toward the process module100bsince there in no empty slot in the process module100a.

FIG.7Eillustrates a state in which, after the “207” to “209” product wafers are taken out from the FOUP in the load port132b, the “301” product wafer is taken out from the FOUP in the load port132c, instead of the dummy wafer. Further,FIG.7Eillustrates a state in which the transfer of the six of the “201” to “206” product wafers to the process module100ais completed.

The process module100aperforms a process according to the recipe on the six of the “201” to “206” product wafers loaded in the slot.

FIG.7Fillustrates a state in which the transfer of the “207” to “209” product wafers taken out from the FOUP in the load port132band the “301” to “303” product wafers taken out from the FOUP in the load port132cto the process module100bis completed.

The process module100bperforms a process according to the recipe on the “207” to “209” product wafers and the “301” to “303” product wafers loaded in the slot.

The transfer of the product wafer from the load port as illustrated inFIGS.7A to7Fto the process module100aor100bmay be implemented, for example, by creating a transfer plan as illustrated in a flowchart inFIG.8. InFIG.8, it is assumed that one control job (CJ) and one process job (PJ) are set for each lot.

The control job is an instruction of a processing unit in the semiconductor manufacturing apparatus12. The process job is a minimum processing unit in the semiconductor manufacturing apparatus12, and is a component of the control job.

FIG.8is a flowchart of an example of a process of creating a transfer plan. In step S10, the schedule function unit46determines whether the product wafer of the wafer group of the advance lot (control job) being executed is insufficient (the number of the product wafers in the FOUP is not a multiple of the number of the slots of the process modules100aand100b).

When the product wafer is not insufficient in the control job being executed, the schedule function unit46proceeds to step S12to determine that it is not necessary to replenish the advance lot with the wafer, and create a transfer plan for performing a process using only the product wafers of the advance lot.

When the product wafer of the wafer group in the control job being executed is insufficient, the schedule function unit46proceeds to step S14to determine whether or not there is a post lot (subsequent control job) at the time of planning the wafer group that is the last in the control job being executed.

When there is not a subsequent control job at the time of planning the wafer group that is the last in the control job being executed, the schedule function unit46proceeds to step S22to create a transfer plan for performing a process by replenishing dummy wafers to the place where the product wafers in the control job being executed are insufficient.

When there is a subsequent control job at the time of planning the wafer group that is the last in the control job being executed, the schedule function unit46proceeds to step S16to determine whether or not the control job being executed and the subsequent control job have the same recipe.

When the control job being executed and the subsequent control job do not have the same recipe, the schedule function unit46proceeds to step S22to create a transfer plan for performing a process by replenishing dummy wafers to the place where the product wafers in the control job being executed are insufficient.

When the control job being executed and the subsequent control job have the same recipe, the schedule function unit46proceeds to step S18to determine whether or not the subsequent control job executes conditioning before the wafer is carried in. When the subsequent control job executes the conditioning before the wafer is carried in, the schedule function unit46proceeds to step S22to create a transfer plan for performing a process by replenishing dummy wafers to the place where the product wafer in the control job being executed is insufficient. Further, when the subsequent control job does not execute the conditioning before the wafer is carried in, the schedule function unit46proceeds to step S20.

In step S20, the schedule function unit46creates a transfer plan for performing a process by replenishing the product wafer in the subsequent control job to the place where the product wafer in the control job being executed is insufficient.

The process of creating the transfer plan inFIG.8may be implemented, for example, as illustrated inFIG.9.FIG.9is a flowchart of another example of a process of creating a transfer plan. Since the processing procedure inFIG.9is the same as the flowchart inFIG.8except for a part, the description thereof will be omitted as appropriate.

Since steps S30to S32are the same as steps S10to S12inFIG.8, the description thereof will be omitted. When the product wafer of the wafer group in the control job being executed is insufficient, the schedule function unit46proceeds to step S34to determine whether or not the control job being executed performs conditioning after the wafer is carried out. When the control job being executed executes the conditioning after the wafer is carried out, the schedule function unit46proceeds to step S46to create the transfer plan for performing a process by replenishing dummy wafers to the place where the product wafers in the control job being executed are insufficient.

Further, when the control job being executed does not execute the conditioning after the wafer is carried out, the schedule function unit46proceeds to step S36. Since step S36is the same as step S14inFIG.8, the description thereof will be omitted.

When there is a subsequent control job at the time of planning the wafer group that is the last in the control job being executed, the schedule function unit46proceeds to step S38to determine whether or not the number of the product wafers in the subsequent control job is larger than or equal to the number of the insufficient product wafers in the control job being executed.

When the number of the product wafers in the subsequent control job is not larger than or equal to the number of the insufficient product wafers in the control job being executed, the schedule function unit46proceeds to step S46to create a transfer plan for performing a process by replenishing dummy wafers to the place where the product wafers in the control job n being executed are insufficient.

Further, when the number of the product wafers in the subsequent control job is larger than or equal to the number of the insufficient product wafers in the control job being executed, the schedule function unit46proceeds to step S40. Since steps S40to S44are the same as steps S16to S20inFIG.8, the description thereof will be omitted.

Except for the flowcharts illustrated inFIG.8andFIG.9, for example, the transfer plan may be created corresponding to the functional valid conditions illustrated inFIG.10.FIG.10is a view for explaining an example of functional valid conditions of the “same product wafer replenishing function.” The functional valid conditions illustrated inFIG.10are examples, and not all the conditions are necessary, and it is possible to add necessary conditions and delete unnecessary conditions. For example, “CJ of the post lot has been generated at the time of planning the last group of the advance lot,” which is the condition of the post lot inFIG.10may be deleted. Further, the functional valid conditions illustrated inFIG.10include both the conditions of the advance lot and the conditions of the post lot, but may be one of them.

The functional valid conditions inFIG.10are examples including the condition of the advance lot and the condition of the post lot. “1CJ1PJ,” which is the condition of the advance lot inFIG.10, is a condition that the lot is constituted by one control job and one process job.

“Not a lot started from the dummy port,” which is the condition of the advance lot inFIG.10, is a condition that the lot is not a control job started from the transfer of the dummy wafer. “Epilogue is not planned to be executed,” which is the condition of the advance lot inFIG.10, is a condition that the conditioning after the wafer is carried out, described in step S34inFIG.9, is not planned to be executed. “PM slot is not designated,” which is the condition of the advance lot inFIG.10, is a condition that the process module100aor100bthat is the transfer destination of the product wafer is not designated.

“The number of wafers to be processed is larger than or equal to the number of the insufficient wafers,” which is the condition of the post lot inFIG.10, is a condition that the number of the product wafers in the subsequent control job is larger than or equal to the number of the insufficient wafers in the control job being executed.

“The system recipe is the same as that of the advance lot,” which is the condition of the post lot inFIG.10, is a condition that the recipes of the control job being executed and the subsequent control job in step S16illustrated inFIG.8or in step S40illustrated inFIG.9are the same as each other.

“Prologue is not planned to be executed,” which is the condition of the post lot inFIG.10, is a condition that the conditioning before the wafer is carried in, described in step S18inFIG.8or in step S42inFIG.9, is not planned to be executed.

Further, “CJ of the post lot has been generated at the time of planning the last group of the advance lot,” which is the condition of the post lot inFIG.10, is a condition that there is the control job of the post lot at the time of planning the wafer group that is the last in the control job being executed, described in step S14inFIG.8or in step S36inFIG.9.

For example, in the semiconductor manufacturing apparatus12according to the present embodiment, when the lot having 13 product wafers is executed, the last wafer group has one product wafer, and thus, the number of the insufficient wafers is five. The transfer plan for the last wafer group is created at the time when all the wafers of the wafer group before the number of the product wafer is one are carried out from the load port.

As a result, when there is no post lot at the time when all the wafers of the wafer group before the number of the product wafer is one are carried out from the load port, the condition of the post lot is not satisfied, and thus, the same product wafer replenishing function is not operated, and a transfer plan is created to perform a process by replenishing dummy wafers to the place where the product wafers of the control job being executed are insufficient.

FIGS.11and12are views for explaining examples in which the same product wafer replenishing function is not operated because the condition of the post lot is not satisfied. For example, inFIG.11, the job execution of the advance lot having seven product wafers is started, and after the sixth product wafer is carried out from the load port132a, the job of the post lot having five product wafers is executed.

The transfer plan for the last wafer group of the advance lot is created at the timing when the last product wafer (sixth product wafer) of the previous wafer group is carried out. As a result, “CJ of the post lot has been generated at the time of planning the last group of the advance lot,” which is the condition of the post lot inFIG.10, is not satisfied.

Therefore, in the example inFIG.11, the product wafer of the advance lot and the product wafer of the post lot may not be process processed together, which cause the transfer plan that replenishes with five dummy wafers.

Further, in the example inFIG.12, after the job execution of the advance lot having three product wafers is started, the job of the post lot having three product wafers is executed.

Since the wafer group of the advance lot has one product wafer, and the transfer plan has been created, “CJ of the post lot has been generated at the time of planning the last group of the advance lot,” which is the condition of the post lot inFIG.10, is not satisfied.

Therefore, in the example inFIG.12, the product wafer of the advance lot and the product wafer of the post lot may not be process processed together, which cause the transfer plan that replenishes with three dummy wafers.

According to the embodiment, it is possible to reduce the number of the dummy wafers used in the semiconductor manufacturing apparatus12and to promote improvement of the turn around time by the increase of the number of the process wafers that are process processed.

According to the present disclosure, it is possible to reduce the number of the dummy wafers used in the semiconductor manufacturing apparatus.