Method for fabricating a strained structure

A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

CROSS-REFERENCE TO RELATED APPLICATIONS

TECHNICAL FIELD

This disclosure relates to integrated circuit fabrication, and more particularly to a field effect transistor with a strained structure.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin vertical “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. Having a gate on both sides of the channel allows gate control of the channel from both sides. Further advantages of FinFET comprises reducing the short channel effect and enabling higher current flow.

FIG. 1Ashows an isometric view of a conventional FinFET100, andFIG. 1Billustrates a cross-sectional view of the FinFET100taken along the line a-a ofFIG. 1A. The fin104/108comprises a raised active region104above a semiconductor substrate102. Fin104/108is surrounded by a shallow trench isolation (STI) structure106. A gate structure110comprising a gate dielectric112, a gate electrode114, and an optional hardmask layer116is formed above the fin104/108. Sidewall spacers118are formed on both sides of the gate structure110. Further, a portion of the fin104/108contains strained structures108in source and drain (S/D) recess cavities of the FinFET100. The strained structures108are formed after a fin recessing process and an epitaxial growth step. The strained structures108utilizing epitaxial silicon germanium (SiGe) may be used to enhance carrier mobility.

However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, an ordered atomic arrangement does not exist due to lattice mismatch between the portion104of the fin104/108and strained portions108. Thus, strain-induced crystal defects108amay become embedded in the strained structure108. The crystal defects108amay provide carrier transportation paths during device operation, thereby increasing the likelihood of device instability and/or device failure.

Accordingly, what is needed is methods for fabricating a reduced-defect strained structure.

DESCRIPTION

Referring toFIG. 2, illustrated is a flowchart of a method200for fabricating a semiconductor device according to various aspects of the present disclosure. The method200begins with block202in which a substrate is provided. The method200continues with block204in which a recess cavity comprising an upper portion and a lower portion may be formed in the substrate, wherein one sidewall of the recess cavity is dielectric and other sidewall of the recess cavity is the substrate. The method200continues with block206in which a dielectric film may be formed on the substrate sidewall portion and a bottom portion of the recess cavity. The method200continues with block208in which removing the dielectric film may include removing the dielectric film on the bottom portion of the recess cavity. The method200continues with block210in which epi-growing a first strained layer may be epi-grown in the lower portion of the recess cavity adjacent to a portion of the dielectric film. The method200continues with block212in which a portion of the dielectric film not adjacent to the first strained layer may be removed. The method200continues with block214in which a second strained layer may be epi-grown in the upper portion of the recess cavity. The discussion that follows illustrates various embodiments of semiconductor devices that can be fabricated according to the method200ofFIG. 2.

Referring toFIGS. 3A-3Fand4A-4E, illustrated are schematic cross-sectional views of strained structures308,408(inFIGS. 3F and 4E) of semiconductor devices300,400at various stages of fabrication according to various aspects of the present disclosure. As employed in the present disclosure, the term semiconductor devices300,400refer to a FinFET. The FinFET refers to any fin-based, multi-gate transistor. The semiconductor devices300,400may be included in a microprocessor, memory cell, and/or other integrated circuit (IC). It is noted that the method ofFIG. 2does not produce completed semiconductor devices300,400. Completed semiconductor devices300,400may be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, it is understood that additional processes may be provided before, during, and after the method200ofFIG. 2, and that some other processes may only be briefly described herein. Also,FIGS. 2 through 4Eare simplified for a better understanding of the present disclosure. For example, although the figures illustrate the semiconductor devices300,400, it is understood the IC may comprise a number of other devices comprising resistors, capacitors, inductors, fuses, etc.

Referring toFIG. 3A, a substrate102is provided having a fin structure104. In one embodiment, the substrate102comprises a crystalline silicon substrate (e.g., wafer). The substrate102may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET.

The substrate102may alternatively be made of some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate102may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

The fin structure104, formed over the substrate102, comprises one or more fins. In the present embodiment, for simplicity, the fin structure104comprises a single fin. The fin comprises any suitable material, for example, the fin structure104comprises silicon. The fin structure104may further comprise a capping layer disposed on the fin, which may be a silicon-capping layer.

The fin structure104is formed using any suitable process comprising various deposition, photolithography, and/or etching processes. An exemplary photolithography process may include forming a photoresist layer (resist) overlying the substrate102(e.g., on a silicon layer), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element including the resist. The masking element may then be used to etch the fin structure104into the silicon layer. The fin structure104may be etched using reactive ion etching (RIE) processes and/or other suitable processes. In an example, the silicon fin104is formed by using patterning and etching of a portion of the silicon substrate102. In another example, silicon fins of the fin structure104may be formed by using patterning and etching of a silicon layer deposited overlying an insulator layer (for example, an upper silicon layer of a silicon-insulator-silicon stack of an SOI substrate).

Isolation structure106may be formed on the substrate102to isolate the various doped regions. The isolation structure106may utilize isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various doped regions. In the present embodiment, the isolation structure106includes a STI. The isolation structure106may comprise silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, and/or combinations thereof. The isolation structure106, and in the present embodiment, the STI, may be formed by any suitable process. As one example, the formation of the STI may include patterning the semiconductor substrate102by a conventional photolithography process, etching a trench in the substrate102(for example, by using a dry etching, wet etching, and/or plasma etching process), and filling the trench (for example, by using a chemical vapor deposition process) with a dielectric material. In some embodiments, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

Still referring toFIG. 3A, a gate stack110is formed over the substrate102and over a portion of the fin structure104. The gate stack110typically comprises a gate dielectric layer112and a gate electrode layer114. The gate stack110may be formed using any suitable process, including the processes described herein.

In one example, the gate dielectric layer112and gate electrode layer114are sequentially deposited on the substrate102and over a portion of the fin structure104. In some embodiments, the gate dielectric layer112may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. In the present embodiment, the gate dielectric layer112is a high-k dielectric layer with a thickness in the range of about 10 to 30 angstroms. The gate dielectric layer112may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The gate dielectric layer112may further comprise an interfacial layer (not shown) to reduce damage between the gate dielectric layer112and the fin structure104. The interfacial layer may comprise silicon oxide.

In some embodiments, the gate electrode layer114may comprise a single layer or multilayer structure. In the present embodiment, the gate electrode layer114may comprise poly-silicon. Further, the gate electrode layer114may be doped poly-silicon with uniform or non-uniform doping. Alternatively, the gate electrode layer114may include a metal such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductive materials with a work function compatible with the substrate material, or combinations thereof. In the present embodiment, the gate electrode layer114comprises a thickness in the range of about 30 nm to about 60 nm. The gate electrode layer114may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof.

Then, a layer of photoresist is formed over the gate stack110by a suitable process, such as spin-on coating, and patterned to form a patterned photoresist feature by a proper lithography patterning method. In one embodiment, a width of the patterned photoresist feature is in the range of about 15 to 45 nm. The patterned photoresist feature can then be transferred using a dry etching process to the underlying layers (i.e., the gate electrode layer114and the gate dielectric layer112) to form the gate stack110. The photoresist layer may be stripped thereafter.

In another example, a hard mask layer116is formed over the gate stack110; a patterned photoresist layer is formed on the hard mask layer116; the pattern of the photoresist layer is transferred to the hard mask layer116and then transferred to the gate electrode layer114and the gate dielectric layer112to form the gate stack110. The hard mask layer116comprises silicon oxide. Alternatively, the hard mask layer116may optionally comprise silicon nitride, silicon oxynitride, and/or other suitable dielectric materials, and may be formed using a method such as CVD or PVD. The hard mask layer116has a thickness in the range from about 100 to 800 angstroms.

Still referring toFIG. 3A, the semiconductor device300further comprises a dielectric layer118formed over the substrate102and the gate stack110. The dielectric layer118may include silicon oxide, silicon nitride, silicon oxy-nitride, or other suitable material. The dielectric layer118may comprise a single layer or multilayer structure. The dielectric layer118may be formed by CVD, PVD, ALD, or other suitable technique. The dielectric layer118comprises a thickness ranging from about 5 to 15 nm. Then, an anisotropic etching is performed on the dielectric layer118to form a pair of spacers118on two sides of the gate stack110.

Still referring toFIG. 3A, other portions of the fin structure104(i.e., portions other than where the gate stack110and spacers118are formed thereover) are recessed to form source and drain (S/D) recess cavities130below a top surface of the substrate102disposed between the gate stack110and the isolation structure106. In one embodiment, using the pair of spacers118as hard masks, a biased etching process is performed to recess a top surface of the fin structure104that are unprotected or exposed to form the S/D recess cavities130. In an embodiment, the etching process may be performed under a pressure of about 1 mTorr to 1000 mTorr, a power of about 50 W to 1000 W, a bias voltage of about 20 V to 500 V, at a temperature of about 40° C. to 60° C., using a HBr and/or C12 as etch gases. Also, in the embodiments provided, the bias voltage used in the etching process may be tuned to allow better control of an etching direction to achieve desired profiles for the S/D recess cavities130. The recess cavity130may comprise an upper portion130uand a lower portion1301separated by the dotted line inFIG. 3A. One sidewall130iof the recess cavity130is dielectric and other sidewall130fof the recess cavity130is the substrate102. In one embodiment, a ratio of a height of the upper portion130uto a height of the lower portion1301may be from 0.8 to 1.2. In some embodiments, a height130abetween the top surface of the substrate102and a bottom of the S/D recess cavity130is in the range of about 300 to 2000 nm.

Referring toFIG. 3B, following formation of the recess cavity130, a dielectric film132may be formed along the substrate surface of the recess cavity130. The dielectric film132comprises a sidewall portion132wand a bottom portion132b.The dielectric film132may be formed of silicon oxide or silicon oxynitride grown using a thermal oxidation process. For example, the dielectric film132can be grown by a rapid thermal oxidation (RTO) process or in a conventional annealing process, which includes oxygen or NO2. A thickness t1of the dielectric film132may be in the range of about 20 to 100 angstroms.

Referring toFIG. 3C, subsequent to the formation of the dielectric film132, a dry etching process is performed to remove the bottom portion132bof the dielectric film132, whereby the sidewall portion132wof the dielectric film132is not removed. For example, the dry etching process may be a plasma etch process performed under a source power of about 120 to 160W, and a pressure of about 450 to 550 mTorr, using BF3, H2, and Ar as etching gases.

Referring toFIG. 3D, after the bottom portion132bof the dielectric film132is removed, a first strained layer136is epi-grown in the lower portion1301of the recess cavities130adjacent to a portion of the dielectric film132. In one embodiment, a first strained layer136comprising silicon germanium (SiGe) is epi-grown by a low-pressure chemical vapor deposition (LPCVD) process. The first strained layer136may serve as a relaxation layer and trap defects136ato eliminate crystal defects in a second strained layer138(shown inFIG. 3F) in the source and drain regions of the n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and GeH4as reaction gases. In another embodiment, a first strained layer136comprising silicon carbon (SiC) is epi-grown by a LPCVD process. The first strained layer136may serve as a relaxation layer and trap defects136ato eliminate crystal defects in a second strained layer138(shown inFIG. 3F) in the source and drain regions of the p-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and CH4as reaction gases. A thickness t2of the first strained layer136may be in the range of about 15 to 45 nm. The thickness t1of the dielectric film132is less than the thickness t2of the first strained layer136.

Referring toFIG. 3E, subsequent to the formation of the first strained layer136, a top portion of the sidewall portion132wof the dielectric film132not adjacent to the first strained layer136has been removed using a wet etching process, for example, by dipping the substrate102in hydrofluoric acid (HF), exposing a top surface132aof the remaining sidewall portion132wof the dielectric film132. Because the wet etching process has higher etch selectivity for oxide than to silicon, SiGe, and SiC, the etch process removes the dielectric film132faster than the fin structure104and the first strained layer136.

In the present embodiment, the first strained layer136is disposed between the isolation structure106and the remaining sidewall portion132wof the dielectric film132. In an embodiment, a top surface136bof the first strained layer136and the top surface132aof the remaining sidewall portion132wof the dielectric film132are substantially aligned. In another embodiment, the top surface136bof the first strained layer136and the top surface132aof the remaining sidewall portion132wof the dielectric film132are below a top surface106aof the isolation structure106.

Referring toFIG. 3F, after the top portion of the sidewall portion132wof the dielectric film132is removed, a second strained layer138overlying the first strained layer136and remaining sidewall portion132wof the dielectric film132is epi-grown in the upper portion130uof the recess cavities130in the fin structure104. Further, the first strained layer136, remaining sidewall portion132wof the dielectric film132, and second strained layer138are collectively hereinafter referred to as a strained structure308. It should be noted that the first strained layer136serves as a relaxation layer and may trap defects136ato eliminate crystal defects in the second strained layer138. Crystal defects in the second strained layer138may provide carrier transportation paths during device operation, thereby increasing the likelihood of device instability and/or device failure. Accordingly, The above method of fabricating a semiconductor device300may form a reduced-defect strained structure308to enhance carrier mobility and upgrade the device performance.

In one embodiment, the second strained layer138, such as silicon carbide (SiC), is epi-grown by a LPCVD process to form the source and drain regions of the n-type FinFET. An example the LPCVD process for the growth of SiC is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and CH4as reaction gases. In another embodiment, the second strained layer138, such as silicon germanium (SiGe), is epi-grown by a LPCVD process to form the source and drain regions of the p-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and GeH4as reaction gases. In still another embodiment, the second strained layer138, such as silicon, is epi-grown by a LPCVD process to form the source and drain regions of both the p-type FinFET and n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4as a reaction gas.

Alternatively,FIG. 4Ashows the substrate102ofFIG. 3Aafter deposition of a dielectric film142by a CVD process. The dielectric film142formed by CVD will deposit over all exposed surfaces, and thus may be formed on the isolation structure106, hard mask layer116, spacers118, and recess cavities130. The dielectric film142may comprise a first sidewall portion142w,a second sidewall portion142s,and a bottom portion142b.The dielectric film142may be formed of silicon oxide or silicon oxynitride deposited using a CVD process. For example, the dielectric film142can be deposited under a pressure less than 10 mTorr and a temperature of about 350° C. to 500° C., using SiH4and N2O as reacting precursors. A thickness t3of the dielectric film142may be in the range of about 20 to 100 angstroms.

Referring toFIG. 4B, subsequent to the formation of the dielectric film142, a dry etching process is performed to remove the bottom portion142bof the dielectric film142, whereby the first sidewall portion142wand second sidewall portion142sof the dielectric film142are not removed. For example, the dry etching process may be performed under a source power of about 120 to 160W, and a pressure of about 450 to 550 mTorr, using BF3, H2, and Ar as etching gases.

Referring toFIG. 4C, after the bottom portion142bof the dielectric film142removing process, a first strained layer146is epi-grown in the lower portion1301of the recess cavities130adjacent to a portion of the dielectric film142. In one embodiment, a first strained layer146comprising silicon germanium (SiGe) is epi-grown by a LPCVD process. The first strained layer146may serve as a relaxation layer and trap defects146ato eliminate crystal defects in a second strained layer148(shown inFIG. 4E) in the source and drain regions of the n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and GeH4as reaction gases. In another embodiment, a first strained layer146comprising silicon carbide (SiC) is epi-grown by a LPCVD process. The first strained layer146may serve as a relaxation layer and trap defects146ato eliminate crystal defects in the second strained layer148(shown inFIG. 4E) in the source and drain regions of the p-type FinFET. In one embodiment, LPCVD process for SiC deposition is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and CH4as reaction gases. A thickness t4of the first strained layer146may be in the range of about 12 to 40 nm. The thickness t3of the dielectric film142is less than the thickness t4of the first strained layer146.

Referring toFIG. 4D, subsequent to the formation of the first strained layer146, top portions of the first and second sidewall portions142w,142sof the dielectric film142not adjacent to the first strained layer146are removed using a wet etching process, for example, by dipping the substrate102in hydrofluoric acid (HF), exposing top surfaces142a,142bof the remaining first and second sidewall portions142w,142sof the dielectric film142. Because the wet etching process preferentially etches oxide over silicon, SiGe, and SiC, the etch process removes the dielectric film142faster than the fin structure104and the first strained layer146.

In the present embodiment, the first strained layer146is disposed between the isolation structure106and the remaining first sidewall portion142wof the dielectric film142. Further, the remaining second sidewall portion142sof dielectric film142is between the first strained layer146and the isolation structure106. In an embodiment, a top surface146bof the first strained layer146and the top surfaces142a,142bof the remaining first and second sidewall portions142w,142sof the dielectric film142are substantially aligned. In another embodiment, the top surface146bof the first strained layer136and the top surfaces142a,142bof the remaining first and second sidewall portions142w,142sof the dielectric film142are below the top surface106aof the isolation structure106.

Referring toFIG. 4E, after the top portions of the first and second sidewall portions142w,142sof the dielectric film142are removed, a second strained layer148overlying the first strained layer146and remaining first and second sidewall portions142w,142sof the dielectric film142is epi-grown in the upper portion130uof the recess cavities130. Further, the first strained layer146, remaining first sidewall portion142wand second sidewall portion142wof the dielectric film142, and second strained layer148are collectively hereinafter referred to as a strained structure408. It should be noted that the first strained layer146serves as a relaxation layer and may trap defects146ato eliminate crystal defects in the second strained layer148. Crystal defects in the second strained layer148may provide carrier transportation paths during device operation, thereby increasing the likelihood of device instability and/or device failure. Accordingly, the above method of fabricating a semiconductor device400may form a reduced-defect strained structure408to enhance carrier mobility and upgrade the device performance.

In one embodiment a second strained layer148comprising silicon carbide (SiC) is epi-grown by a LPCVD process to form the source and drain regions of the n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and CH4as reaction gases. In another embodiment a second strained layer148comprising silicon germanium (SiGe) is epi-grown by a LPCVD process to form the source and drain regions of the p-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4and GeH4as reaction gases. In still another embodiment a second strained layer148comprising silicon is epi-grown by a LPCVD process to form the source and drain regions of both the p-type FinFET and n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH4as a reaction gas.

After the steps shown inFIGS. 2,3and4have been performed, subsequent processes, comprising silicidation and interconnect processing, are typically performed to complete the semiconductor device300and400fabrication.

While the preferred embodiments have been described by way of example, it is to be understood that the disclosure is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the disclosure should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. The disclosure can be used to form or fabricate a strained structure for a semiconductor device. In this way, a strained structure having no defect in a semiconductor device is fabricated.