Silicon germanium fin immune to epitaxy defect

A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

BACKGROUND OF THE INVENTION

The present disclosure generally relates to the field of semiconductors, and more particularly relates to non-planar semiconductor devices comprising fins immune to epitaxy defects.

Silicon-germanium (SiGe) fin technology is being developed to enhance p-type field-effect transistor performance. Conventional SiGe fins generally rely on epitaxially growing SiGe on a silicon (Si) substrate. However, due to the fundamental constraint of critical thickness of epitaxial SiGe on Si, it has been found that SiGe fins formed by conventional epitaxy processes are usually susceptible to epitaxy defects.

SUMMARY OF THE INVENTION

In one embodiment, a method for forming a semiconductor structure is disclosed. The method comprises forming at least one fin on a semiconductor substrate. The least one fin comprises a semiconducting material. A dummy gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

In another embodiment, a semiconductor structure is disclosed. The semiconductor structure comprises a substrate and at least one fin formed on the substrate. The at least one fin comprises a semiconducting material and germanium diffused into the semiconducting material. A gate stack formed in contact with the at least one fin. A source region and a drain region are formed on the at least one fin.

In yet another embodiment, an integrated circuit is disclosed. The integrated circuit comprises a semiconductor structure. The semiconductor structure comprises a substrate and at least one fin formed on the substrate. The at least one fin comprises a semiconducting material and germanium diffused into the semiconducting material. A gate stack formed in contact with the at least one fin. A source region and a drain region are formed on the at least one fin.

DETAILED DESCRIPTION

It is to be understood that the present disclosure will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present disclosure.

Referring now to the drawings in which like numerals represent the same of similar elements,FIGS. 1-7illustrate various processes for fabricating a semiconductor fin structures that are immune to epitaxy defects. In general, the figures comprise a plain view and various cross-sectional views that are taken where indicated in the plain view. More specifically, the view “A” is taken along a line that passes through a fin, while views “B” and “C” are cross-section views that are taken transverse to the long axis of the fins. It should be noted that one or more embodiments are not limited to the processes discussed below for forming the initial fin structures, gate structures, and completing the device(s) the device. This discussion is provided for illustration purposes, and any process for fabricating the initial fin structures, gate structures, and for completing the finFET device(s) is applicable to embodiments of the present disclosure.

FIG. 1shows a semiconductor structure100that may be a part of a large semiconductor chip, for example, and is illustrated to include, among others, one or more three dimensional (3D) or fin-type field-effect-transistors (FETs) that are commonly known to include, for example, finFETs and tri-gate FETs. For the purpose of discussion hereinafter without losing generality, it is assumed and demonstratively illustrated that semiconductor structure100includes one or more finFETs (or finFET transistors), although the following discussion may be equally applied to tri-gate FETs with little or no modification.

In one embodiment, the semiconductor structure100comprises substrate102such as a silicon-on-insulator (SOI) substrate; a dielectric layer104(e.g., a BOX layer or oxide layer) overlying the substrate102; and one or more fin structures106,108,110overlying the dielectric layer104. The substrate layer102comprises at least one of Si, Ge alloys, SiGe, GaAs, InAs, InP, SiCGe, SiC, and other III/V or II/VI compound semiconductors. The fin structures106,108,110comprise a semiconductor material such as Si. The substrate layer102and the fin structures106,108,110can be made of the same or different materials. The dielectric layer104, in one embodiment, is a crystalline or non-crystalline oxide, nitride, oxynitride, or any other insulating material.

In one embodiment, prior to forming the fin structures106,108,110the semiconductor material/layer can be formed utilizing a layer transfer process including a bonding step, or an implantation process such as SIMOX (Separation by IMplantation of OXygen). This semiconductor layer can be undoped or doped with either p-type or n-type dopants through ion implantation, plasma doping, or gas phase doping. P-type transistors are produced by doping the semiconductor layer106with elements from group III of the periodic table (e.g., boron, aluminum, gallium, or indium). As an example, the dopant can be boron in a concentration ranging from 1×10E18 atoms/cm3 to 2×10E21 atoms/cm3. N-type transistors are produced by doping the semiconductor layer with elements from group V of the periodic table (e.g., phosphorus, antimony, or arsenic). The following embodiments refer to p-type transistors.

The fins106,108,110are formed, in one embodiment, by forming an etch-stop capping layer onto the semiconductor layer through, for example, deposition. The etch-stop capping layer, in one embodiment, may be made of silicon-nitride although other material suitable in providing etch-stop function may be used as well. One or more fin structures106,108,110are subsequently formed or etched out of the semiconductor layer to be on top of oxide layer104through a process involving masking, using industry-standard lithographic techniques, and directionally etching the etch-stop capping layer and underneath semiconductor layer. The directional etching process, for example a reactive-ion-etching (RIE) process, stops on the dielectric layer104. After the RIE etching process, the photo-resist mask used in the lithographic etching process may be removed, leaving the fin structures106,108,110.

FIG. 2shows that a replacement (dummy) gate202,204,206is formed on the fin structure106,108,110. The dummy gate202,204,206is formed, in one embodiment, using oxide, polysilicon, amorphous silicon, nitride, or a combination thereof. In this example, the dummy is amorphous silicon. Depending on the material of the dummy gate202,204,206, spacers (not shown) can then formed on the sidewalls of the dummy gates202,204,206by one or more spacer formation techniques. For example, if the material of the dummy gates202,204,206comprises amorphous silicon, sidewall spacers are required if the layer302is formed by epitaxial growth of high concentration of germanium containing material. The spacers can be formed by, for example, isotropically depositing a conformal layer of insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectric material and the like) followed by an anisotropic etch (e.g., reactive ion etch (RIE)) of that material to form spacers. In another embodiment, the dummy gates202,204,206can be amorphous silicon without sidewall spacers if the layer302is formed by any technique among the following: chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, and gas cluster beam deposition. In another embodiment, the dummy gates202,204,206can be any type of dielectric materials (such as amorphous silicon, silicon oxide, silicon nitride, etc.) and no sidewall spacers are required if the layer302is formed by any technique among the following: chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, and gas cluster beam deposition. It should be noted that the dummy gates discussed here can also be real gates formed using the “gate first” integration scheme.

An optional hard mask (not shown) can be formed on top of the dummy gate202,204,206. The hard mask can comprise a dielectric material such as a nitride, oxide, oxynitride material, and/or any other suitable dielectric layer. The dielectric hard mask can be a single layer of dielectric material or multiple layers of dielectric materials, and can be formed by a deposition process such as chemical vapor deposition (CVD) and/or atomic layer deposition (ALD). Alternatively, the hard mask can be grown, such as through thermal oxidation or thermal nitridation.

A layer302of material comprising germanium (Ge) is then deposited on and in contact with the fin structures106,108,110in the source and drain areas301,303of the device100, as shown inFIG. 3. The layer302, in one embodiment, comprises SiGe with a high percentage of Ge such as 20% to 100% (e.g., pure germanium). These materials can be deposited/formed on the fin structures106,108,110by low temperature chemical vapor deposition (CVD), atomic layer deposition, plasma enhanced chemical vapor deposition (PECVD), gas cluster beam deposition, molecular beam epitaxy growth techniques.

One or more processes are then utilized to diffuse Ge from layer302into the Si fins106,108,110to form SiGe fins406,408,410, as shown inFIG. 4. For example, a thermal annealing treatment can be utilized to cause diffusion of germanium atoms from layer302into the Si fins106,108,110, and particularly into the channel region form a SiGe channel. This process allows the Si fins106,108,110to become SiGe fins without experiencing defects caused by conventional epitaxy processes. The thermal treatment may be conducted by any method known in the art, for example, rapid thermal annealing (RTA) of the p-FET device100. At this point of the manufacturing process, there may be no thermal budget constraint and a high temperature furnace anneal may be used to ensure a homogeneous distribution of germanium atoms in the silicon fin120. Stated differently, both the silicon fin SiGe fins106,108,110and the germanium comprising/containing layer302may have a homogenous distribution of germanium atoms after the device100undergoes the thermal annealing treatment.

The thermal diffusion process may be performed at a temperature high enough to cause diffusion of germanium atoms out of layer302and into the Si fins106,108,110. In one embodiment, the annealing temperature may range from about 800° C. to about 1250° C. and the process is performed in an inert environment (e.g., nitrogen or argon). The inter-diffusion of silicon and germanium atoms between the layer302and the Si fins106,108,110forms SiGe fins406,408,410and in turn a SiGe channel. Inter-diffusion may occur when germanium atoms, activated by the high annealing temperature, migrate from a region containing a high germanium concentration (such as layer302) to a region of low (or zero) concentration of germanium atoms (such as the Si fins106,108,110).

In general, the initial concentration of germanium atoms in layer302, the annealing temperature and time determines the amount of germanium atoms diffusing into the Si fins106,108,110and particularly into the channel region during the thermal treatment. In one embodiment, the atomic concentration of germanium in the SiGe fins406,408,410and channel after thermal diffusion may range from about 15% to about 45%. The epitaxial thickness of the SiGe in the fins406,408,410ranges from, for example, 2 nm to 10 nm. As previously discussed, the final concentration of germanium atoms in the SiGe fins406,408,410and channel is proportional to the initial germanium concentration of the layer302.

After the SiGe fins406,408,410have been formed, epitaxial source/drains502,504are formed, as shown inFIG. 5. In one embodiment, the source and drain regions502,504of a PFET device(s) are formed from in-situ boron doped (ISBD) silicon germanium (SiGe). Namely, boron is introduced during growth of a SiGe epitaxial material in the source and drain regions of the PFET device. Prior to the epitaxial growth of silicon germanium, a pre-cleaning wet process may be performed to remove the excess layer302of material consisting germanium on the surface of dummy gate and the sidewall spacers. After the epitaxial source drain formation, an inter-layer dielectric (ILD) layer is deposited and followed by chemical mechanical planarization (CMP) process. The CMP process stops at the nitride cap (not shown) of the dummy gates202,204,206.

After the source/drain regions502,504have been formed, a dielectric layer602is formed over the entire structure100, as shown inFIG. 6. The dummy gates202,204,206are then selectively removed with respect to SiGe fins406,408,410(e.g., via selective etching). This creates trenches604,606,608within the dielectric layer602that exposes the channel regions610,612,614situated under the dummy gates202,204,206.FIG. 7shows that one or more gate stacks702,704,706are then formed on the SiGe fins406,408,410. For example, a thin conformal layer of gate dielectric708and thick layers of gate conductor material710and optional nitride (not shown) are deposited. The gate dielectric708contacts sidewalls of the SiGe fins406,408,410, a top surface of the SiGe fins406,408,410, and a top surface of the underlying dielectric layer104. The gate conductor710contacts sidewalls of the gate dielectric708, a top surface of the gate dielectric708formed on the top surface of the SiGe fins406,408,410, and a top surface of the gate dielectric708contacting the top surface of the underlying dielectric layer104. It should be noted that if sidewall spacers were not formed for the dummy gates, sidewall spacers712are formed prior to forming the replacement gates702,704,708. For example, the sidewall spacers712can be formed by inner spacer formation process after the dummy gates are removed but prior to high k dielectric and metal gate depositions. Fabrication of the devices, such as forming contacts and forming a dielectric layer(s) over the device, can then be completed utilizing one or more processes known the industry.

FIG. 8is an operational flow diagram illustrating a process for fabricating a semiconductor fin structures that are immune to epitaxy defects. InFIG. 8, the operational flow diagram begins at step802and flows directly to step804. It should be noted that each of the steps shown inFIG. 8has been discussed in greater detail above with respect toFIGS. 1-7. At least one fin, at step804, is formed on a semiconductor substrate. A dummy gate, at step806, is formed over and in contact with the at least one fin. A germanium comprising layer, at step808, is deposited over and in contact with the at least one fin.

Germanium, at step810, is diffused from the germanium comprising layer into the semiconducting. After the diffusing, a source region and a drain region with in contact with the at least one fin at step812. Then, an inter-layer dielectric material is deposited followed by the CMP process, stopping on gate cap layer, at step814. Gate cap and dummy gates, at step816, are then removed. After the gates have been removed, inner sidewall spacers are formed if no sidewall spacers on removed dummy gates, at step818. If the sidewall spacers have already been formed during the dummy gate formation process, the pre-formed sidewall spacers will stay intact after the dummy gates are removed. A gate stack is formed over and in contact with the at least one fin, at step820. The control flow then exit at step822.

Although specific embodiments of the disclosure have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the disclosure. The scope of the disclosure is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present disclosure.

It should be noted that some features of the present disclosure may be used in one embodiment thereof without use of other features of the present disclosure. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present disclosure, and not a limitation thereof.

Also that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed disclosures. Moreover, some statements may apply to some inventive features but not to others.