High performance power MOS structure

A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.

BACKGROUND

As semiconductor circuits such as metal-oxide-semiconductor field effect transistors (MOSFETs) are adapted for high power applications, problems arise with respect to high on-resistance issue. In a MOSFET device, such as high power lateral diffused metal-oxide semiconductor (LDMOS) structures, when a high power is applied to the gate, an electrical channel under the gate stack has higher on-resistance and low saturation current. As a result, the LDOMS power transistor's performance is degraded.

DETAILED DESCRIPTION

FIG. 1is a flowchart of one embodiment of a method for making an integrated circuit100.FIGS. 2-9are various cross-sectional views of an integrated circuit200in one embodiment, in portion or entirety, during various fabrication stages, fabricated by the method ofFIG. 1. The method100or the integrated circuit200each is one example of a method or an integrated circuit, respectively, that can benefit from various embodiments or aspects of the present invention. For the sake of further example, the integrated circuit100has a polysilicon feature embedded in a gate spacer between a source region and a gate electrode, as discussed in greater detail below. With reference toFIGS. 1 through 9, the method100and the integrated circuit200are collectively described below. It is understood that additional steps can be provided before, during, and after the method100, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. It is further understood that additional features can be added in the integrated circuit200, and some of the features described below can be replaced or eliminated, for additional embodiments of the integrated circuit.

Referring toFIGS. 1 and 2, the method begins at step102by forming various well regions in a substrate210. The substrate210may be or comprise a semiconductor wafer such as a silicon wafer. Alternatively, the substrate210may include other elementary semiconductors such as germanium. The substrate210may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate210may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate210includes an epitaxial layer overlying a bulk semiconductor. Various doped features, such as a well region, a source region and a drain region described below, may be formed in the epitaxy layer. Furthermore, the substrate210may include a semiconductor-on-insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX). In various embodiments, the substrate210may include a buried layer such as an N-type buried layer (NBL), a P-type buried layer (PBL), and/or a buried dielectric layer including a buried oxide (BOX) layer. For example, a P-type substrate may include an NBL at least under a P-type metal oxide semiconductor field effect transistor (PMOSFET).

Located in the substrate210are a N-well region212(also referred to as a power N-well) and P-well regions214and216(each also referred to as a power P-well) disposed adjacent the N-well region212. The P-well regions214and216are configured to laterally surround the N-well region212in one embodiment. The N-well region212and the P-well regions214and216are portions of substrate210, and are formed by various ion implantation processes. Alternatively, the N-well region212and the P-well regions214/216may be portions of an epitaxy layer such as a silicon epitaxy layer formed by epitaxy processing. The N-well region212has a N-type dopant such as phosphorus, and the P-well regions214and216have an P-type dopant such as boron. In one embodiment, the well regions212,214and216are formed by a plurality of processing steps, whether now known or to be developed, such as growing a sacrificial oxide on substrate210, opening a pattern for the location(s) of the P-well regions or N-well region, and implanting the impurities.

Referring toFIGS. 1 and 3, the method100proceeds to step104by forming various isolation features220on the substrate210. An isolation feature structure such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS) including the isolation feature220may be formed on the substrate to define and electrically isolate various active regions. As one example, the formation of an STI feature may include dry etching a trench in a substrate and filling the trench with insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In furtherance of the embodiment, the STI structure may be created using a processing sequence such as: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, using chemical mechanical polishing (CMP) processing to etch back and planarize, and using a nitride stripping process to remove the silicon nitride.

Still referring toFIGS. 1 and 3, the method100proceeds to step106by forming a gate stack222including a gate electrode224and a gate dielectric226and forming various light doped regions including light doped source region228and light doped drain region230(also referred to as LDD regions) in the substrate210.

The gate stack222is disposed on the substrate, including the gate dielectric226on the substrate210and the gate electrode224on the gate dielectric226. The gate stack further includes other features such as spacers described below. The gate dielectric226includes a silicon dioxide layer disposed on the substrate210. Alternatively, the gate dielectric226may include silicon oxide, high dielectric-constant (high k) materials, silicon oxynitride, other suitable materials, or combinations thereof. The high k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, HfO2, or combinations thereof. The gate dielectric may have a multilayer structure such as one layer of silicon oxide and another layer of high k material. The gate dielectric layer226may have a thickness ranging between about 20 Angstroms and about 200 Angstroms. The gate dielectric226may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, other suitable processes, or combinations thereof.

The gate electrode224is designed to be coupled to metal interconnects and is disposed overlying the gate dielectric226. The gate electrode226includes doped polycrystalline silicon (or polysilicon). Alternatively, the gate electrode layer may include doped poly-silicon, metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The gate electrode layer may be formed by CVD, PVD, plating, and other proper processes. The gate electrode layer may have a multilayer structure and may be formed in a multiple-step process.

The gate dielectric layer and the gate electrode layer formed on the substrate are then patterned to form a plurality of gate stacks using a process including photolithography patterning and etching. One exemplary method for patterning the gate dielectric and electrode layers is described below. A layer of photoresist is formed on the polysislicon layer by a suitable process, such as spin-on coating, and then patterned to form a patterned photoresist feature by a proper lithography patterning method. The pattern of the photoresist can then be transferred by a dry etching process to the underlying polysilicon layer and the gate dielectric layer to form gate electrodes224and gate dielectric226, as shown inFIG. 3, in a plurality of processing steps and various proper sequences. For example, the polysilicon layer is etched using a dry etching process with chemical SF6and HBR, with pressure ranging between about 20 and about 30 mtorr, and/or with radio frequency power ranging between about 240 W and about 280 W. The photoresist layer may be stripped thereafter. In another embodiment, only the gate electrode layer is pattered. In another embodiment, a hard mask layer may be used and formed on the polysilicon layer. The patterned photoresist layer is formed on the hard mask layer. The pattern of the photoresist layer is transferred to the hard mask layer and then transferred to the polysilicon layer to form the gate electrode. The hard mask layer may include silicon nitride, silicon oxynitride, silicon carbide, and/or other suitable dielectric materials, and may be formed using a method such as CVD or PVD.

A p-type base (also referred to as p-body) region228is formed in the N-well region212. The p-type base region218is laterally interposed between the isolation feature220and the gate electrode224. The p-type base region228is further extended to a portion of the substrate210underneath the gate electrode224such that the p-type base region228is partially underlying the gate electrode224to define a channel with a channel length “L” illustrated inFIG. 3. The p-type base region228includes p-type dopant such as boron and is formed by a method including ion implantation. In one embodiment, the p-type base region228is formed by an ion-implantation process with a tilt angle such that the p-type base region228is extended partially underlying the gate electrode224. In furtherance of the embodiment, the ion implantation process may utilize a tilt angle about 45 degree. In other embodiments, the tilt angle of the ion implantation is tuned for optimized channel length.

Light doped source region230and light doped drain region231(both also referred to as LDD regions) are formed in the substrate210after the formation of the gate dielectric226and gate electrode224. The LDD regions230and231are laterally positioned on sidewalls of the gate electrode and interposed by the gate electrode. Each of the LDD regions230and231has an edge substantially self-aligned to an edge of the gate electrode224, as illustrated inFIG. 3. The light doped source region is formed in the p-type base region228. The LDD regions include n-type dopant such as phosphorus or arsenic. The LDD regions are formed by a method including ion implantation or diffusion.

Referring toFIGS. 1 and 4, the method100proceeds to step108by forming a gate spacer and a conductive feature embedded in the gate spacer. Gate spacers232and234are formed on both sidewalls of the gate stack222. Particularly, a conductive feature (or second electrode)236is embedded in the gate spacer232overlying the light doped source region230. Optionally, another conductive feature is formed embedded in the gate spacer234overlying the light doped drain region231. The gate spacers includes a dielectric material such as silicon oxide. Alternatively, the gate spacers include a dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof. In one embodiment, the gate spacers have a multilayer structure. The embedded conductive feature236includes doped polycrystalline silicon. Alternatively, the embedded conductive feature236may include other suitable materials, such as metal, metal alloy, silicide, metal nitride, doped polysilicon, or combinations thereof. The embedded conductive feature236is separated from the substrate210by the dielectric material of the gate spacer232with a vertical distance to the substrate more than about 200 angstrom. The gate spacers and embedded conductive feature can be formed in a proper processing sequence. An exemplary method of forming the gate spacers and the embedded conductive feature is provided below.

Steps110,112,114and116of the method100provide a processing sequence for forming the gate spacers and the embedded conductive feature.FIGS. 5-8illustrate sectional views of the gate stack222as a portion of the integrated circuit200in one embodiment during various fabrication stages. With reference to FIGS.1and5-8, the exemplary method is described. At step110, with reference toFIG. 5, a first dielectric layer238is formed on the gate electrode224and the substrate210. A conductive layer240is formed on the dielectric layer238. In one embodiment, the dielectric layer238having silicon oxide is formed by a CVD, such as high temperature silicon oxide chemical vapor deposition (HTOCVD), using chemical N2O and SiH2Cl2. The deposition temperature may range between about 800 and about 830° C. In another embodiment, the conductive layer240having polysilicon is formed by CVD using silane (SiH4). The deposition temperature may range between about 600 and about 630° C. The polysilicon layer240is further doped with phosphorus using chemicals N2O and POCL3. The doping temperature ranges between about 800 and about 830° C.

At step112, with reference toFIG. 6, an etching process such as a dry etching technique is applied to the polysilicon layer240to substantially remove the polysilicon layer with only the conductive features (second electrode)236remaining on the dielectric layer238and proximate to the sidewalls of the gate electrode224as illustrated inFIG. 6. In one embodiment, the polysilicon layer240is etched using a dry etching process with chemical Cl2and HBR, with a pressure ranging between about 300 and about 600 mtorr, and/or with radio frequency power ranging between about 380 W and about 420 W. In another embodiment, the conductive feature236on the drain side and overlying the light doped drain region may be optionally removed by a processing sequence including photolithography patterning and wet etching.

At step114, with reference toFIG. 7, a second dielectric layer242is formed on the first dielectric layer238and the conductive feature236using a method such as CVD. The second dielectric layer242includes silicon oxide. Alternatively, the second dielectric layer242uses a material such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In one embodiment, a CVD process is implemented using chemical tetraethoxysilane (TEOS) and a deposition temperature ranging between about 680 and about 720° C.

At step116, with reference toFIG. 8, an etching process such as a dry etching technique is applied to the second dielectric layer242for the substantial removal thereof, leaving the gate spacers232and234proximate the sidewalls of the gate electrode224and having the conductive feature embedded therein. An anisotropic etching process such as a dry etching process may be used to etch the second dielectric layer242. In one embodiment, a dry etching process is implemented using chemical Ar, CF4and CHF3, with a pressure ranging between about 700 and about 850 mtorr, and/or with radio frequency power ranging between about 380 and about 420 W. The gate spacers232/234and embedded conductive feature236are formed as further illustrated inFIG. 4.

Referring toFIGS. 1 and 9, the method100proceeds to step118by forming a source region246and a drain region248in the substrate210. The source and drain regions246and248are positioned on both sides of the gate electrode224and interposed thereby. In one embodiment, each of the source region246and drain region248has an edge substantially self-aligned to an edge of the gate spacer234or gate spacer236as illustrated inFIG. 9. The source region246is positioned in the p-type base region228and adjacent the light doped source region230. The source and drain regions include n-type dopant such as phosphorus or arsenic. The source and drain regions are formed by a method such as ion implantation or diffusion. A rapid thermal annealing (RTA) process may be used to activate the implanted dopant. In various embodiments, the source and drain regions may have different doping profiles formed by multi-step implantation.

A contact region250may be formed in the substrate210and positioned in the p-type base region228. The contact region250includes p-type dopant such as boron with a doping concentration higher than that of the p-type base region228to provide a contact for connecting the p-type base region. The contact region is formed by a method including ion implantation and diffusion known in the art.

The thus formed integrated circuit provides the conductive feature232embedded in the spacer234overlying the light doped source region230and laterally interposed between the source region246and the gate electrode224. Due to the embedded conductive feature232, sidewall capacity defined between the gate electrode224and the light doped source region230is increased. Further explanation is provided below with reference toFIGS. 10 and 11.FIG. 10is a cross-sectional view of a portion of a conventional integrated circuit.FIG. 11is cross-sectional view of a portion of the integrated circuit200in one embodiment constructed according to aspects of the present disclosure.FIGS. 10 and 11are used only for illustration and explanation of one embodiment of the spacer structure with embedded conductive feature instead of limiting the scope of the present disclosure. Parameters d0, d1and d2inFIGS. 10 and 11are various effective lengths for relevant sidewall capacitance as illustrated inFIGS. 10 and 11. The sidewall capacitance is defined between the gate electrode224and the light doped source drain region230with gate spacer232as capacitor dielectric. In the traditional integrated circuit ofFIG. 10, the relevant sidewall capacitance C0is proportional to 1/d0. In the disclosed structure having the conductive feature236embedded in the gate spacer232, the sidewall capacitance Ct is associated with C1(proportional to 1/d1) and C2(proportional to 1/d2). The total sidewall capacitance Ct of the disclosed integrated circuit may be further quantitatively related with C1and C1as 1/Ct=1/C1+C2. It is clear based on the above that Ct is proportional to 1/(d1+d2) and therefore is higher than the sidewall capacitance C0of the traditional spacer structure. Thus, the induced carrier under the gate spacer232with the embedded conductive feature236is greater than that of the traditional spacer structure. The embedded conductive feature232can be used as an extended gate electrode, which results in more carriers induced by a gate voltage and leads to higher saturation current and lower on-resistance.

Other devices and features can be formed on the substrate210. Other devices may includes various transistors, various active and passive features configured and coupled to provide proper functions and applications such as various pulse width modulation (PWM) controller, class-D amplifier, photo flash charger, and/or DC-DC converter.

The method100and the integrated circuit200may further include forming various contacts and metal features on the substrate210. For example, silicide may be formed by silicidation such as self-aligned silicide (salicide) in which a metal material is formed next to Si structure, then the temperature is raised to anneal and cause reaction between underlying silicon and the metal to form silicide, and un-reacted metal is etched away. The salicide material may be self-aligned to be formed on various features such as the source region, drain region and/or gate electrode to reduce contact resistance.

A plurality of patterned dielectric layers and conductive layers are formed on the substrate210to form multilayer interconnects configured to couple the various p-type and n-type doped regions, such as the source region246, drain region248, contact region250, and gate electrode224.

In one embodiment, an interlayer dielectric (ILD) and a multilayer interconnect (MLI) structure are formed in a configuration such that the ILD separates and isolates each from other of the MLI structure. In furtherance of the example, the MIL structure includes contacts, vias and metal lines formed on the substrate210. In one example, the MIL structure may include conductive materials such as aluminum, aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof, being referred to as aluminum interconnects. Aluminum interconnects may be formed by a process including physical vapor deposition (or sputtering), chemical vapor deposition (CVD), or combinations thereof. Other manufacturing techniques to form the aluminum interconnect may include photolithography processing and etching to pattern the conductive materials for vertical connection (via and contact) and horizontal connection (conductive line). Alternatively, a copper multilayer interconnect may be used to form the metal patterns. The copper interconnect structure may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The copper interconnect may be formed by a technique including CVD, sputtering, plating, or other suitable processes.

The ILD material includes silicon oxide. Alternatively or additionally, the ILD includes a material having a low dielectric constant such as a dielectric constant less than about 3.5. In one embodiment, the dielectric layer includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials. The dielectric layer may be formed by a technique including spin-on, CVD, or other suitable processes.

MLI and ILD structure may be formed in an integrated process such as a damascene process. In a damascene process, a metal such as copper is used as conductive material for interconnection. Another metal or metal alloy may be additionally or alternatively used for various conductive features. Accordingly, silicon oxide, fluorinated silica glass, or low dielectric constant (k) materials can be used for ILD. During the damascene process, a trench is formed in a dielectric layer, and copper is filled in the trench. Chemical mechanical polishing (CMP) technique is implemented afterward to etch back and planarize the substrate surface.

Among various embodiments, the present method and structure provide enhanced performance of high saturation current and reduced on-resistance. The disclosed structure and method may have various embodiments, modifications and variations. In one example, the high power semiconductor devices may further include a stress layer overlying the substrate and gate features. The stress layer may comprise silicon nitride, silicon oxynitride, silicon oxide, and silicon carbide. In another embodiment, the source and drain regions may have different structures, such as raised, recessed, or strained. It is understood that the power integrated circuit200is illustrated herein only as an example. The high power semiconductor device may not be limited to an NMOS device and can be extended to a PMOS having an embedded poly feature in the gate spacer between the source region and gate electrode with a similar structure and configuration except that all doping types may be reversed and dimensions are modified according to PMOS design. In other embodiments, the high power integrated circuit may be a lateral diffused MOS (LDMOS) formed in a dual-well structure (a p-type well and a n-type well) within the substrate210. Further embodiments may also include, but are not limited to, vertical diffused metal-oxide-semiconductor (VDMOS), other types of high power MOS transistors, Fin structure field effect transistors (FinFET), and strained MOS structures.

Thus, the present disclosure provides a semiconductor device. The device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and adjacent a side of the gate electrode and laterally between the source region and the gate electrode; and a conductive feature embedded in the gate spacer.

In various embodiments, the semiconductor device may further include a base region in the substrate, having a second type of dopant different from the first type of dopant, disposed partially underlying the gate electrode, surrounding the source region. The semiconductor device may further include a contact region disposed in the base region, having the second type of dopant, and proximate the source region. The semiconductor device may further include a well region having the first type of dopant, disposed in the substrate, and surrounding the drain region and the base region. The semiconductor device may further include a light doped source region of the first type of dopant disposed in the base region, underlying the conductive feature embedded in the gate spacer. Each of the gate electrode and the conductive feature may include doped polycrystalline silicon. The conductive feature may be vertically separated from the substrate by a dielectric layer having a thickness more than about 200 angstrom. The gate spacer may include a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The semiconductor device may further include a gate dielectric layer vertical interposed between the gate electrode and the substrate.

The present disclosure also provides a method for forming a integrated circuit. The method includes forming a gate electrode on a semiconductor substrate; forming a gate spacer adjacent a sidewall of the gate electrode and a conductive feature embedded in the gate spacer; forming a light doped source region in the substrate laterally edging the gate electrode and underlying the conductive feature; and forming a source region and drain region in the substrate and laterally interposed by the gate electrode, wherein the source region, drain region and light doped source region each include a first type of dopant.

The present disclosure also provides various embodiments of the method. The method may further include forming a base region of a second type of dopant different from the first type of dopant in the substrate, surrounding the source region and the light doped source region, and partially underlying the gate electrode. The method may further include forming a well region of the first type of dopant in the substrate, having the base region and the drain region disposed therein. The forming of the gate spacer and the conductive feature may include forming a first dielectric layer on the gate electrode and the substrate; forming a conductive layer on the first dielectric layer; etching the conductive layer to form the conductive feature laterally between the source and the gate electrode; forming a second dielectric layer on the gate electrode, the conductive feature and the first dielectric layer; and etch the second dielectric layer to form the gate spacer with the conductive featured embedded therein. The forming of the first conductive layer may include forming a polycrystalline silicon layer. The forming of the polycrystalline silicon may include performing a chemical vapor deposition (CVD) process utilizing a chemical silane. The forming of the polycrystalline silicon may include performing a CVD process with a temperature ranging between about 600° C. and about 630° C. The method may further include performing an ion implantation to the polycrystalline silicon layer. The forming of the first dielectric layer and/or the forming of the second dielectric layer may include forming a silicon oxide layer. The etching of the conductive layer and the etching of the second dielectric layer each may include forming performing an anisotropically etching process. The method may further include forming a gate dielectric vertically interposed between the gate electrode and the substrate. The method may further include forming a light doped source region on the substrate after the forming of the gate electrode and edging the gate electrode; forming a source region and a drain region laterally interposed by the gate electrode after the forming the gate spacer; and forming a p-type base region in the substrate before the forming the gate electrode, surrounding the source region and the light doped source region, and partially underlying the gate electrode. The forming of the p-type base region may include implementing ion implantation with a tilt angle of about 45 degree.

The present disclosure also provides a semiconductor device. The method includes a source region and a drain region disposed in a substrate wherein the source and drain regions; a gate electrode formed on the substrate interposed laterally between the source and drain regions; and a gate spacer with a conductive feature embedded therein, laterally adjacent a sidewall of the gate electrode and laterally interposed between the source region and the gate electrode.

In various embodiments of the semiconductor device, the conductive feature may include doped polycrystalline silicon. The semiconductor device may further include a light doped source region underlying the conductive feature embedded in the gate spacer. The semiconductor device may further include a p-type base region formed in the substrate, surrounding the source region and the light doped source region, and partially underlying the gate electrode. The semiconductor device may further include an n-type well region formed in the substrate surrounding the p-type base region and drain region. The semiconductor device may further include an isolation feature disposed on the substrate defining active defining an active area, using a technique selected from the group consisting of local oxidation of silicon (LOCOS) and shallow trench isolation (STI).