Contact etching utilizing partially recessed hard mask

A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

BACKGROUND

The present invention relates to a semiconductor process and in particular to fabrication of a semiconductor device using a partially recessed hard mask.

The increasing demand for highly integrated and high-performance semiconductor devices has fueled the need for advances in integrated circuit manufacturing technology. To produce an integrated circuit with high integration density, semiconductor device and interconnect sizes must be reduced. Lithography and etching form trenches and contact holes in the dielectric layer prior to formation of the interconnects. Thereafter, the trenches and contact holes are filled with a metal layer, followed by polishing to complete the fabrication. This is a typical damascene process in semiconductor manufacturing technology. In a common etching technique used to form openings, such as trenches or contact holes, in a target layer on a substrate, a photoresist pattern is formed on the target layer serving as an etch mask. Since the thickness of the photoresist pattern can dictate the etching rate, the photoresist pattern must be thick if the contact holes are to be very small.

A photoresist layer having a thickness of 3000 Å or more, however, is not sensitive to the light used for lithography. That is, it is difficult to form a contact hole with a small critical dimension using a photoresist layer as an etch mask. Accordingly, the fabrication of a contact hole with small critical dimension using a polysilicon layer as an etch mask has been widely employed.

FIG. 1is a cross-section of a conventional semiconductor device fabricated using a single polysilicon hard mask. The semiconductor device comprises a substrate100, an interlayer dielectric (ILD) layer112, a polysilicon hard mask114, a barrier layer116, and a metal layer118. The substrate100comprises a device region10and an alignment region20, in which the device region10has a plurality of gate structures107formed thereon and the alignment region20has an opening101formed in the substrate100serving as an alignment mark (AM). The gate structure107comprises a gate dielectric layer102, a gate electrode104, and a gate spacer106. The ILD layer112overlies the substrate100, with the portion thereof over the device region10comprising a bit line contact hole (CB)113a, a gate contact hole (CG)113b, and a substrate contact hole (CS)113ctherein. The portion of ILD layer112on the alignment region20has an opening therein to expose the opening101. The polysilicon hard mask114is disposed on the ILD layer112and the portion thereof over the device region10has a plurality of holes to expose the bit line contact hole113a, the gate contact hole113b, and the substrate contact hole113cand the portion over the alignment region20has an opening therein to expose the opening (alignment mark)101. The barrier layer116comprising titanium nitride is conformably disposed on the polysilicon hard mask114and the inner surfaces of the contact holes113a,113b, and113cand the opening101. The metal layer118, such as a tungsten layer, is conformably formed on the barrier layer116and the opening101and fills the contact holes113a,113b, and113c.

During the fabrication of the semiconductor device, the alignment mark101on the alignment region20may fail due to light strongly reflected from the thicker polysilicon hard mask114. That is, it is difficult to define the contact holes113a,113b, and113cduring lithography. In order to solve this problem, the polysilicon hard mask114over the alignment mark101must be removed prior to definition of the contact holes113a,113b, and113c. As a result, a deeper and wider opening is formed by removing the ILD layer112over the alignment mark101during definition of the contact holes113a,113b, and113c. As the subsequent metal layer118is filled for the fabrication of contact plugs, the deeper and wider opening cannot be completely filled with the metal layer118. The metal layer118, however, is conformably formed on the inner surface of the opening. A dishing effect thus occurs during planarization by chemical mechanical polishing (CMP). As a result, the metal layer118adjacent to the alignment mark118is disconnected, as depicted by the arrows119shown inFIG. 1, thus reducing device reliability.

SUMMARY

An embodiment of the invention provides a method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region comprising an opening therein serving as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon pattern layer is formed overlying the dielectric layer serving as the hard mask, in which the polysilicon pattern layer comprises a-recessed region over the opening and a plurality of holes therein on the device region to expose the underlying dielectric layer. The exposed dielectric layer is etched using the polysilicon pattern layer as an etch mask, to form the plurality of contact holes in the dielectric layer on the device region.

The polysilicon pattern layer has a thickness of about 700 to 1000 Å and the recessed region a depth of about 300 to 500 Å. Moreover, the contact hole may comprise a bit line contact hole, a gate contact hole, or a substrate contact hole.

An embodiment of the invention also provides a semiconductor device fabricated using a partially recessed hard mask. The device comprises a substrate, a dielectric layer, a polysilicon pattern layer, a barrier layer, and a metal layer. The substrate has a device region and an alignment region comprising an opening therein serving as an alignment mark. The dielectric layer overlies the substrate and fills the opening, with the dielectric layer on the device region comprising a plurality of contact holes therein. The polysilicon pattern layer is disposed on the dielectric layer serving as the hard mask, with that over the opening on the alignment region having a recessed region and that on the device region having a plurality of holes therein to expose the contact holes formed in the underlying dielectric layer. The barrier layer is conformably disposed on the polysilicon pattern layer and the inner surfaces of the contact holes and the recessed region. The metal layer is disposed on the barrier layer and fills the contact holes and the recessed region.

The polysilicon pattern layer has a thickness of about 700 to 1000 Å and the recessed region a depth of about 300 to 500 Å. Moreover, the contact hole may comprise a bit line contact hole, a gate contact hole, or a substrate contact hole.

DETAILED DESCRIPTION

First, as shown inFIG. 2A, a substrate200for the fabrication of a semiconductor memory device is provided. The substrate200may be, for example, a silicon substrate. In this embodiment, the substrate200has a device region30, such as an array region or peripheral circuit region, and an alignment region40. The device region30has a plurality of gate structures207thereon and the alignment region40an opening201therein serving as an alignment mark (AM). Moreover, the gate structure207comprises a gate dielectric layer202, a gate electrode204, and a gate spacer206.

As shown inFIG. 2B, a dielectric layer212is deposited overlying the substrate200serving as an interlayer dielectric (ILD) layer, covering the gate structures207on the device region30and filling the opening201on the alignment region40. The ILD layer212may be a single layer or multiple layers, and can comprise, for example, a borophosphosilicate glass (BPSG) layer and a tetraethyl orthosilicate (TOES) oxide layer, and can be formed by the following steps. First, a BPSG layer208blanketly covers the gate structures207on the device region30and fills the opening201on the alignment region40. Excess BPSG layer208over the gate structures207is removed by chemical mechanical polishing (CMP). Thereafter, a TEOS oxide layer210is formed on the polished BPSG layer208by conventional deposition, such as chemical vapor deposition (CVD).

Next, a polysilicon layer214is deposited overlying the ILD layer212serving as a hard mask for subsequent etching. The polysilicon layer214may be formed by conventional deposition, such as CVD. Moreover, the polysilicon layer214has a thickness of about 700 to 1000 Å. Next, a photoresist pattern layer216is formed on the polysilicon layer214, which has an opening217therein to expose the polysilicon layer214over the opening201on the alignment region40.

Next, inFIG. 2C, the polysilicon layer214overlying the ILD layer212is patterned to form a polysilicon pattern layer214awhich has a recessed region219over the opening201on the alignment region40and a plurality of holes221a,221b, and221con the device region30to expose the underlying ILD layer212. The polysilicon pattern layer214amay be formed by following steps. First, the polysilicon layer214under the opening217is partially etched using the photoresist pattern layer216shown inFIG. 2Bas an etch mask, to form the recessed region219over the opening (alignment mark)201which has a depth of about 300 to 500 Å. The photoresist pattern layer216, no longer needed, is subsequently removed. Next, another photoresist pattern layer218is formed on the polysilicon pattern layer214a, in which the photoresist pattern layer218has a plurality of holes221a,221b, and221ctherein on the device region30. Thereafter, the polysilicon pattern layer214ais etched using the photoresist pattern layer218as an etch mask, to transfer the plurality of holes221a,221b, and221ctherein and expose the underlying ILD layer212for the subsequent definition of contact holes. The hole221acan be used for definition of a bit line contact hole (CB), hole221bfor definition of a gate contact hole (CG), and hole221cfor definition of a substrate contact hole (CS).

As mentioned above, if the polysilicon hard mask is too thick, the alignment mark for subsequent lithography may fail due to light strongly reflected from the hard mask. Conversely, if the polysilicon hard mask is not thick enough, the subsequent etching may suffer. However, in this embodiment, the thickness of the polysilicon hard mask214aover the alignment mark201is reduced due to the formation of the recessed region219. Accordingly, the strongly reflected light is prevented during subsequent lithography for the definition of contact holes.

Next, inFIG. 2D, after removal of the photoresist pattern layer218, the exposed ILD layer212on the device region30is etched using the polysilicon pattern layer214aas an etch mask to form a bit line contact hole223a, a gate contact hole223b, and a substrate contact hole223c. The ILD layer212over and in the alignment mark201is not etched due to the protection of the polysilicon pattern layer214athereon. As a result, the step height on the alignment region40can be reduced when the subsequent metal layer is deposited thereon.

Finally, inFIG. 2E, a barrier layer222comprising, for example, titanium and titanium nitride, is conformably formed on the polysilicon pattern layer214aand the inner surfaces of the contact holes223a,223b,223cand the opening219. Thereafter, a metal layer224, such as a tungsten layer, is formed on the barrier layer222, filling the contact holes223a,223b,223cand the opening219to complete fabrication of the contact plugs. The metal layer224is subsequently planarized by CMP.

FIG. 2Ealso illustrates a semiconductor device fabricated using a partially recessed hard mask of an embodiment of the invention. The semiconductor device comprises a substrate200, an ILD layer212, a polysilicon pattern layer214a, a barrier layer222, and a metal layer224. The substrate comprises a device region30and an alignment region40, the device region30comprising a plurality of gate structures207thereon and the alignment region40an opening201therein serving as an alignment mark (AM). Moreover, the gate structure207comprises a gate dielectric layer202, a gate electrode204, and a gate spacer206. The ILD layer212overlies the substrate200and fills the opening201, the ILD layer212on the device region30comprising a bit line contact hole223a, a gate contact hole223b, and a substrate contact hole223ctherein. Moreover, the ILD layer212may comprise a borophosphosilicate glass (BPSG) layer and a tetraethyl orthosilicate (TOES) oxide layer. The polysilicon pattern layer214ais disposed on the ILD layer212serving as the partially recessed hard mask, with over the opening (alignment mark)201on the alignment region40comprising a recessed region219. Moreover, the polysilicon pattern layer214aon the device region30comprises a plurality of holes therein to expose the bit line contact hole223a, the gate contact hole223b, and the substrate contact hole223cin the ILD layer212. The polysilicon pattern layer214ahas a thickness of about 700 to 1000 Å and the recessed region219a depth of about 300 to 500 Å. The barrier layer222comprising, for example, titanium and titanium nitride, is conformably disposed on the polysilicon pattern layer214aand the inner surfaces of the contact holes223a,223b, and223cand the recessed region219. The metal layer224, such as a tungsten layer, is disposed on the barrier layer222and fills the contact holes223a,223b, and223cand the recessed region219.

According to an embodiment of the invention, the thickness of the polysilicon pattern layer214aover the alignment mark201may be reduced, eliminating strongly reflected light from the hard mask. Moreover, since the step height of the metal layer224on the alignment region40is reduced by the partially recessed hard mask214a, disconnection of the metal layer224adjacent to the alignment mark201may be prevented after planarization.