Power device having super junction and schottky diode

A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

BACKGROUND

The present disclosure relates to a power semiconductor device, in particular a power device having a super junction structure and a Schottky diode.

Power semiconductor devices are used in many different industries. Some of these industries, such as telecommunications, computing and charging systems, are rapidly developing. Those industries would benefit from improved semiconductor device characteristics, including reliability, switching speed, and miniaturization.

Recent efforts to improve power semiconductor device characteristics include creating a Schottky barrier region that is separate from a transistor region. A separate Schottky barrier region reduces leakage current and improves reverse recovery characteristics. However, there is still room for improvements to the structure of power semiconductor devices to meet the demands for higher system efficiency through lower forward voltage (VF), faster reverse recovery performance and better reliability of emerging technologies.

SUMMARY

Embodiments of the present application relate to a power semiconductor device having a super junction and a Schottky diode, where the Schottky diode is integrated into the unit cell of the power device. The device has lower forward voltage (VF) and reduced reverse recovery time compared to conventional power devices.

A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

A power semiconductor device includes a substrate having an upper side and a lower side. A first electrode is disposed over the upper side of the substrate. A second electrode is disposed below the lower side of the substrate. An epi layer is formed over the substrate and between the first and second electrodes, the epi layer having a pillar and a well, the pillar and the well defining a gap. A trench is disposed over the pillar having a sidewall and a base, the base of the trench being recessed into the pillar. A metal contact layer is disposed over the base and the sidewall of the trench, the metal contact layer contacting the epi layer at the gap defined by the well and the pillar, thereby defining a Schottky interface at the gap.

A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

DETAILED DESCRIPTION

Embodiments of the present application relate to a power semiconductor device having a super junction and a Schottky diode. The Schottky diode is integrated into the unit cell of the power device, so that the Schottky diode does not consume any more area than the unit cell of the power device. The Schottky diode also provides a good current path between the super junction pillar and the source/emitter of the power device to minimize the dynamic switching problems and catastrophic failure under high-current avalanche. The Schottky diode may also be provided with adequate shielding, e.g., a highly doped region adjacent to the Schottky contact region (or Schottky interface) to reduce current leakage under reverse bias. In an embodiment, the power device is configured to have low epi resistivity and handle high breakdown voltage, e.g., greater than 300 voltage, or greater than 500 voltage, or greater than 700 voltages.

A detailed description of embodiments is provided below along with accompanying figures. The scope of this disclosure is limited only by the claims and encompasses numerous alternatives, modifications and equivalents. Although steps of various processes are presented in a given order, embodiments are not necessarily limited to being performed in the listed order. In some embodiments, certain operations may be performed simultaneously, in an order other than the described order, or not performed at all.

Numerous specific details are set forth in the following description. These details are provided to promote a thorough understanding of the scope of this disclosure by way of specific examples, and embodiments may be practiced according to the claims without some of these specific details. Accordingly, the specific embodiments of this disclosure are illustrative, and are not intended to be exclusive or limiting. For the purpose of clarity, technical material that is known in the technical fields related to this disclosure has not been described in detail so that the disclosure is not unnecessarily obscured.

FIG. 1illustrates a power semiconductor device100according to an embodiment of the present disclosure. In the present embodiment, the power device100is a power metal oxide semiconductor field effect transistor (MOSFET) device with a super junction structure (or pillars). In other embodiment, the power device100may be other power devices such as an insulated gate bipolar transistor (IGBT) device. If the power device100is an IGBT, it would have an additional P+ substrate or layer, as would be understood by one skilled in the art.

The power device100includes a semiconductor substrate102, for example silicon substrate. An epitaxial layer104(or epi layer) is provided on a first side of the substrate102, and a first electrode106is provided on or over a second side of the substrate102. In an embodiment, the epi layer104has N type conductivity. A second electrode108is provided over the epi layer104. A plurality of gate structures110are provided over the epi layer104and proximate to the second electrode108. The epi layer104provides a current path for the first and second electrodes106and108when the gate structure110is turned on. In the present embodiment, the power device100is a power MOSFET and the first and second electrodes106and108are drain and source electrodes, respectively. In another embodiment, the power device may be an IGBT and the first and second electrodes106and108may be collector and emitter electrodes, respectively.

Each of the gate structures110includes a gate electrode112, a gate oxide114and a gate spacer116. A plurality of wells118are provided in the epi layer, between the gate structures110. The depth of the well118may depend on the characteristics of the power device100. In an embodiment, the depth of the well ranges between about 1 micron to about 2 microns, or may be up to 5 microns. In an embodiment, the wells118have P conductivity and form a body diode with the epi layer104. The dopant concentration of the P wells118is around between 1.2×1016atoms/cm3and 8.0×1017atoms/cm3. A plurality of N+ regions120are provided within the P wells118and proximate the gate electrode112. In an embodiment, the N+ region120is a source region.

A plurality of pillars122(or super junction structures) are disposed in the epi layer104. Each pillar is spaced apart from the P well118, defining a gap123of 1-5 microns, or from 2-3 microns depending on implementation. This vertical gap123defines a Schottky diode region, and its size may vary depending on implementation. In an embodiment, the pillars122have P type conductivity, and have a dopant concentration of about 1016atoms/cm3. In an embodiment, the pillar122has a vertical dimension of at least 20 microns or at least 25 microns. In another embodiment, the pillar122may have a vertical dimension of about 30 microns to about 60 microns depending on implementation. For example, for a 600-650 V device, the pillars have a vertical dimension of about 45-50 microns in an implementation.

In an embodiment, a plurality of N+ enhancement regions124are provided in the gap123defined by the P wells and the pillars. The N+ enhancement regions124are provided to decrease the forward voltage drop of body diode and reduce the current leakage under reverse bias. In an embodiment, the N+ enhancement regions124are provided in an alternating pattern as shown inFIG. 1B, which show a top view of the N+ enhancement regions124and the P wells118. In another embodiment, gaps123may be present only where there is a corresponding N+ enhancement region124and absent elsewhere, as shown inFIG. 1C. In this embodiment, P wells118and P pillars122overlap in regions where N+ enhancement regions124are absent. In still another embodiment, the N+ enhancement regions124are not provided.

A plurality of trenches126extends from an upper surface of the epi layer104and into an upper portion of the P pillars122. The trenches126extend through the N+ source regions120and partly into the P wells118, so that the bases or bottoms of the trenches reside in the P pillars122. In an embodiment, the trench126extends about 1 micron to about 8 microns into the P pillars.

A plurality of Ohmic contact regions128are provided below the base of the trenches126. In an embodiment, the Ohmic contact regions128are formed by providing additional P type impurities, e.g., boron, to the upper portion of the P pillars122. In an embodiment, Ohmic contact regions128have a significantly higher dopant concentration than that of the P pillars122. For example, the P pillars have a dopant concentration of about 1016atoms/cm3, and the Ohmic contact regions128have a dopant concentration of about 1019atoms/cm3, which is 3 orders of magnitude as great as the dopant concentration of the P pillars122.

A Schottky contact layer130is disposed over surfaces of the trenches126. The Schottky contact layer130includes upper portions130a, side portions130b, and a bottom portion (or base)130c. The upper portions130aof the Schottky contact layer130extend beyond the trench and abut sides of the gate structures110. The side portions130bof the Schottky contact layer130contacts the gap123defined by the P well118and the P pillar122, thereby defining the Schottky contacts (Schottky interfaces). These Schottky contact define a Schottky diode where the anode is connected to (or corresponds to) the source electrode108and a cathode is connected to (or corresponds to) the drain electrode106. The Schottky diode reduces the forward voltage (VF) and reverse recovery time for the power device100. Since the Schottky contact is formed between the P well118and the P pillar122, the Schottky diode is integrated into the unit cell of the power device100. As a result, the Schottky diode does not consume any more area than the unit cell of the power device100.

In addition, the bottom portion130cof the Schottky contact layer130makes an Ohmic contact with the Ohmic contact regions128. The Ohmic contact results in a good current path between the pillar122and the second electrode108(e.g., source electrode), which reduces the likelihood of dynamic switching problems and catastrophic failure under high-current avalanche conditions.

The Schottky contact layer130, which forms a Schottky diode, may include a metal material such as Molybdenum (Mo), Platinum (Pt), Vanadium (V), Titanium (Ti), Palladium (Pd), etc. In another embodiment, the Schottky contact layer130is a silicide material, such as platinum or palladium silicide.

As explained above, the power device100having a Schottky diode has certain advantages.FIG. 2illustrates waveforms of currents flowing through two power devices as a function of a source-drain voltage VSD: “SJ MOS” represents a conventional super junction MOSFET device and “SJ with Schottky Diode” represents the power device100. In experiment, it has been found that the source-drain voltage VSDof SJ with Schottky diode (or the power device100) is lower than that of the conventional super junction MOSFET, especially at current levels below 15 A. For example, while the conventional super junction MOSFET has a source-drain voltage VSDof 0.68V at 1 A, the source-drain voltage VSDof the power device100is 0.46V at 1 A, which is about 30% lower than that of the conventional super junction MOSFET. It is believed that the Schottky diode lowers the source-drain voltage VSDof the power device100since Schottky diode has a lower forward voltage than a PN diode.

Similarly, while a conventional super junction MOSFET has a source-drain voltage VSDof 0.74V at 5 A, a super junction MOSFET with a vertical Schottky diode (or the power device100) is 0.66V at 5 A, which is about 11% lower than that of the conventional super junction MOSFET device. The power device100has a lower a source-drain voltage VSDthan the conventional MOSFET since the Schottky diode in the power device100has a lower forward voltage drop than a PN junction diode found in a conventional super junction MOSFET (for example, 0.2V˜0.5V compared to 0.7 V). Accordingly, the power device100having a Schottky diode has less body diode conduction loss than that of the conventional super junction MOSFET, thereby increasing power efficiency in applications including an inverter and DC-DC power conversion.

FIG. 3illustrates waveforms of body diode reverse recovery currents of a PN junction diode in a conventional super junction MOSFET device and of a vertical Schottky diode in a super junction MOSFET device (e.g., the power device100). A reverse recovery current of the vertical Schottky diode is significantly smaller than the reverse recovery current of the PN junction diode in the conventional super junction MOSFET device. For example, the reverse recovery current of the vertical Schottky diode of the power device100may be as low as zero at drain current values of less than 6 A when only vertical Schottky diode turns on. Because a reverse recovery current induces extra losses in a MOSFET switch in a bridge circuit with inductive load, when the power device100with a vertical Schottky diode is used in such a bridge circuit, a turn-on loss of the power device100would be less than that of a conventional super junction MOSFET switch. Additionally, a gate-source voltage oscillation in the bridge circuit can be reduced and prevent MOSFET malfunction.

FIGS. 4A-4Sillustrate aspects of a method of forming a semiconductor power device200in accordance with an embodiment of this disclosure.

InFIG. 4A, a semiconductor layer204is formed over a semiconductor substrate202. The layer204may be formed by an epitaxial growth process. In an embodiment, the substrate202is silicon and each epitaxial growth step forms an epi layer having about 2.5 to 3.2 microns. In other embodiment, the substrate202may be other semiconductor materials, such as a group IV semiconductor substrate, a group III-V compound semiconductor substrate, or a group II-VI oxide semiconductor substrate. For example, the group IV semiconductor substrate may include a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

The substrate202may include an epi layer. In an embodiment, the substrate202may be an N+ doped layer where the power device is a MOSFET. In another embodiment, the substrate202may be a P+ layer where the power device is an IGBT. The layer204is implanted with N type impurities (FIG. 4B) to convert the layer204to N type conductivity. Annealing may be performed to facilitate the diffusion of the impurities. In an embodiment, the layer204may be formed with the N type impurities so that the implantation step may be skipped.

A semiconductor layer206is formed over the layer204(FIG. 4C). The layer206is implanted with N type impurities, resulting in a structure with two N layers. Next, a patterned photoresist207is formed over the layer206(FIG. 4D), exposing selected portions of the layer206. P type impurities (or ions) are selectively implanted into the exposed portions of the layer206. These exposed portions of the layer206will be used to form the pillars (see numeral122inFIG. 1A). The P type impurities are provided with sufficient concentration to convert the exposed portions into a plurality of P regions208. The photoresist207is removed (FIG. 4E). The above steps are repeated (e.g., 13-20 times) to obtain a layer206′ having a plurality of pillars208′ (FIG. 4F). The layer206′ include multiple epi layers. In an embodiment, the total depth (or vertical dimension) of the pillar208′ from top to base is greater than 20 microns, e.g., in the range of about 30 to 60 microns. Annealing process may be performed after ions are implanted on each epi layer to facilitate the dopant diffusion.

Next, a semiconductor layer210is formed over the entire structure and doped with N impurities (FIG. 4G). The layer210may a single epi layer or a multiple epi layers according to implementation. The layer210is formed to have a depth of 2-4. The layer210is provided with sufficient depth to form a gap whereon the Schottky contact is to be formed subsequently. The layer210is doped with N type impurities. A patterned photoresist212is formed to exposes portions of the layer210.

In an embodiment, additional N doping is performed to provide higher N type concentration at selected portions of the layer210, thereby forming a plurality of N+ enhancement regions214(FIG. 4H). The N+ enhancement regions214corresponds to the N+ enhancement regions124inFIG. 1. Doping concentration in the N+ enhancement regions214may be, for example, from about 1.2×1016to 5×1017. The N+ enhancement regions214is formed to reduce the current leakage under reverse bias among other reasons. In the case where gaps between the P pillars208′ and subsequently formed P wells are not present where N+ enhancement regions214are absent (FIG. 1C), the overlap of the P pillars208′ and the subsequently formed P wells may be accomplished by means of an additional photomask and implant step in which the bridging implant region is formed only in areas outside the N+ enhancement regions214. Alternately, the bridging implant region may be formed where N+ enhancement regions214are present and allow the N+ enhancement regions214to counter-dope the P pillars208′ to form the desired gap for the Schottky diode. The N+ enhancement regions214may or may not be formed according to implementation.

FIG. 4Ishows a top view showing the N+ enhancement regions214and the pillars208′ according to an embodiment. The pattern of N+ enhancement regions214may be described as a checkerboard pattern over the pillars208′. In other words, each contiguous pillar208′ of the device may have an alternating pattern of N+ enhancement regions214and N body doping regions along its length, while the pattern of N+ enhancement regions214is offset for each neighboring pillar208′. The widths of the N+ enhancement regions214and the N body doping regions may be the same or similar, so that N+ enhancement regions214and N body doping regions are disposed in an alternating matrix, or checkerboard pattern, over the pillars208′. Although the shape of the N+ enhancement region214inFIG. 4Iis rectangular, embodiments are not limited to that specific shape. For example, the shape of the N+ enhancement regions214may be circular, hexagonal, or other shapes.

In an embodiment, the N+ enhancement regions214that are disposed over adjacent pillars208′ do not overlap one another with respect to a gate axis direction, or top-to-bottom direction of the drawing (seeFIG. 4I). In other embodiments, the N+ enhancement regions214of adjacent pillars208′ overlap one another with respect to the gate axis direction. In yet another embodiment, one or more of N+ enhancement regions214may extend over the entire P pillar210.

Referring toFIG. 4J, another layer216is formed over the N+ enhancement regions214by performing one or more epitaxial growth steps using the steps described above. The layer216has a depth of about 1-3 microns depending on implementation, or sufficient thickness to form a P well therein subsequently. A gate oxide layer218is formed over the layer216. A gate electrode layer220is formed over the gate oxide layer218. In an embodiment, the gate electrode layer is an N doped polysilicon, but may be other conductive material according to implementation.

The gate electrode layer220is etched to form a plurality of gate electrodes220′ using photolithography method which is well known in the art (FIG. 4K). AlthoughFIG. 4Kshows an intact gate oxide layer218in spaces between adjacent gate electrodes220′, some embodiments may include removing the gate oxide material provided between the gate electrodes220′. P type dopants are implanted into the layer216using the gate electrodes220′ as a mask to form a plurality of P wells222. Annealing may be performed to facilitate the diffusion of the dopants. The P wells222are formed to be spaced apart from the pillars208′, thereby providing a gap223. That is, the bottom of the P wells222and the top of the pillars208′ define the gap223to have a vertical dimension of at least 1 micron in an embodiment. In another embodiment, the gap223is 2-4 microns, or 2-3 microns. The size of the gap defines the Schottky contact (or Schottky interface) for the Schottky diode so its size may vary according to implementation.

N type impurities are selectively implanted into the top of the P wells222using the gate electrodes220′ as a mask (FIG. 4L). Alternately, a photoresist mask can be used to pattern the implant. The N doping is controlled to create a plurality of N+ regions224. In an embodiment, the N+ regions are source regions.

Referring toFIG. 4M, a gate dielectric layer (not shown) is formed over the gate electrode220′ and the N+ source regions224. The gate dielectric layer may be formed by depositing one or more dielectric layers over the upper surface of device. The dielectric layers may include a nitride layer, an oxide layer, or other dielectric materials. In an embodiment, the dielectric layer is a nitride layer. The dielectric layer is selectively etched to remove portions of dielectric material disposed between the gate electrodes220′, resulting in a plurality of gate spacers226. The gate spacers226define a plurality of gate structures228. The gate structure228includes a gate oxide218′, a gate electrode220′, and a gate spacer226.

A plurality of trenches230are formed over the pillars208′ and extend through the P wells222(FIG. 4N). The trenches are formed using known photolithography and anisotropic etch processes. In an embodiment, the trenches230extend into the pillars208′ by 1 micron to 8 microns.

An oxide layer232is formed over the trenches230(FIG. 4O). The oxide layer232may be formed using a deposition process or a thermal oxidation process and can have a thickness from 50-600 Angstroms. In an embodiment, the oxide layer232is formed globally on the entire structure including over the gate structures228. A nitride layer234is formed over the oxide layer232. In an embodiment, the nitride layer234has a thickness from 1000-2500 Angstroms.

An anisotropic etch is performed to expose the pillars208′ (FIG. 4P). The etch removes horizontally exposed portions of the nitride layer234and the oxide layer232, including the bottom portions of the nitride layer234and the oxide layer232that are disposed over the bottom surface of the trenches230. However, the nitride layer234and the oxide layer232remain on the sidewalls of the trenches230and the gate structures228. In some embodiments, a thin portion of oxide layer232may remain at the bottom surface of the trenches230. The remaining nitride and oxide layers serve as sidewall spacers236that protect the sidewalls of the trenches from a subsequent implantation step, which will be explained below. In an embodiment, a photoresist mask is formed over the gate structures228prior the anisotropic etch to protect the gates structures.

An ion implantation step is performed to form Ohmic contact regions238at the bottom of trenches230(FIG. 4Q), where portions of pillars208′ were exposed by the anisotropic etch above. In an embodiment, the Ohmic contact regions are doped with P type dopants to a concentration of at least 1019atoms/cm3. The Ohmic contact region238has a much higher conductivity than the body of pillars208′, which has a concentration of about 1016atoms/cm3.

The sidewall spacers236protect the sidewalls of the trenches230from the ions (or dopants) that may scatter during the implantation step. In an embodiment, a relatively low implantation energy, such as 3 to 25 keV may be used for the implantation step so that scattering ions would not have sufficient energy to penetrate the spacers236and be implanted into the sidewalls of the trench230. Furthermore, a heavier implant species such as BF2may be used instead of boron to reduce the projected range of the implant if so desired. Alternatively, the thickness of the spacers236may be increased to prevent the scattering ions from penetrating the sidewalls of the trench230. Or both the implantation energy and the thickness of the spacers236may be adjusted to prevent the scattering ions from penetrating into the sidewalls of the trench230. If the P type dopants are implanted into the sidewalls of the trench, these dopants can dilute the N type conductivity of the sidewalls where Schottky contact will be made subsequently, which would degrade the performance of the Schottky diode.

After the ion implantation step, the nitride and oxide layers234and232that are remaining on the gate structures228and the trenches230are removed (FIG. 4R). In an embodiment, the nitride and oxide layers234and232are removed using a wet etch step. The wet etch is selected to dissolve the oxide layer232underlying the nitride layer. As a result, the nitride layer is lifted off from the structure. In such an embodiment, the gate spacer226is formed using a nitride layer to protect the gate structures.

A Schottky contact layer240is formed over the exposed surfaces of the trenches230(FIG. 4R). The Schottky contact layer240may formed by masking and selectively forming a Schottky metal material such as Molybdenum (Mo), Platinum (Pt), Vanadium (V), Titanium (Ti), Palladium (Pd), etc. In an embodiment, the Schottky contact layer is formed by forming a silicide material, such as platinum or palladium silicide. The Schottky contact layer240may also be a combination of a metal material and a silicide material. In an embodiment, Schottky contact layer240is formed conformally on the surfaces of the trenches230. In an embodiment, although not shown, a barrier metal material such as titanium nitride may be formed over the surface of the Schottky material layer. The Schottky contact layer240makes a Schottky contact at the gap223defined by the P well222and the P pillar208′ to form a Schottky diode. A bottom portion of the Schottky contact layer240makes an Ohmic contact with the Ohmic contact region238. This Ohmic contact facilitates the current flow therethrough.

A first electrode242is formed by depositing a conductive material such as aluminum over the substrate202. In an embodiment, the first electrode242is a drain electrode (FIG. 4S). A second electrode244is formed by depositing a conductive material such as aluminum over the gate structures228and into the trenches230. In an embodiment, the second electrode is a source electrode. A resulting device is a power semiconductor device200which corresponds to the power device100inFIG. 1. The power device200may be a power MOSFET, IGBT, or the like according to implementation.

Aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples. Numerous alternatives, modifications, and variations to the embodiments as set forth herein may be made without departing from the scope of the claims set forth below. For example, in another embodiment, the P pillars may be formed by a process that includes forming alternating epitaxial semiconductor and blocking layers, implanting impurities into the blocking layers, and diffusing the impurities from the blocking layers into the epitaxial semiconductor layers as described in U.S. application Ser. No. 15/454,861, which is incorporated by reference. Alternately, the P pillars may be formed by an entirely different method, such as etching a deep trench, incorporating a P type dopant in the trench, and filling the trench with some material such as monocrystalline silicon. Furthermore, methods of incorporating the P type dopant may include growth of doped epitaxial silicon inside the deep trench, angled ion implantation, plasma ion doping, diffusion from a solid source, atomic layer deposition, or some other doping technique. Similarly, although a planar gate structure was used in the previous embodiments, other types of gate structures are possible. In particular, a trench gate structure can be used instead of a planar gate structure. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting.