Leadframes with folded conductor portion and devices therefrom

A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.

FIELD

This Disclosure relates to leadframes and devices including leadframes that operate under high current flows, such as field-effect transistors (FETs) and current sensors.

BACKGROUND

There are a variety of packaged devices that operate under high current flow in the leadframe, such as power FETs, gate drivers, and some sensor devices. Sensor devices include current sensors such as shunt-type current sensors, and thermal (temperature) sensors. The shunt for a current shunt sensor bridges between first and second pads, while the thermal sensor can be on a die attach pad, or on another leadframe feature.

For a current sensor example, a Hall-effect sensor is one commonly used type of current sensor that generally operates at high current including through their reduced width curved head portion (also called a loop portion) that is between an I+ fused lead and I− fused lead. The Hall-effect is known to be the generation of a potential difference (voltage) across an electrical conductor typically being a doped semiconductor material, known as a Hall voltage, when a magnetic field is applied in a direction perpendicular to the flow of current in the electrical conductor. A Hall-effect sensor is a transducer that varies its output voltage in response to a magnetic field created by a current to be measured by the sensor, where the current to be measured can be an alternating current (AC) or a direct-current (DC).

SUMMARY

This Disclosure recognizes for leadframes one can fold or bend additional material to form folded features in addition to a conventional planar metal conductor portion of a leadframe for a high current flow device to reduce the resistance of generally any leadframe feature, and/or to increase the mechanical strength to resist unintentional bending during assembly. High current flow devices include current sensor devices, or generally any other device that operates with high current flow in the leadframe, such as power FETs and drivers.

This Disclosure also recognizes for devices having a power pad, such as the power pad for high current applications including conventional Hall-effect sensor packages, have several limitations. For example, during assembly the power pad in a 50 A shunt current sensor device may not provide sufficient mechanical support for handling, leading to bending of the power pad. High joule heating (JH) in such current sensing devices during their normal operation can also limit the operating temperature of the device/package, where this operating temperature limit can be based on either the internal package temperature or on the ambient temperature. The root cause of these problems is recognized herein to be an insufficient leadframe thickness resulting in a current carrying cross-sectional area being too small. As a result, conventional leadframes for such current sensing devices do not provide a sufficiently high current handling capability, or heat transfer path, nor do conventionally leadframes provide sufficient mechanical support in assembly to avoid bending during the handling.

These limitations result in the devices only supporting lower current operation, such as in the case of a current sensor a current limit of about 15 A to 20 A of maximum field generating current (FGC). This can limit the maximum possible magnetic field strength and potentially causing excessive JH due to a leadframe thermal dissipation issue, as well as lowering the sensitivity of the sensor device which depends on the magnetic field strength (μV resolution) that is set by the operating current level. Other shortcomings include a relatively high DC resistance, and a high voltage induced dielectric breakdown problem that can be due to the dielectric breakdown of the mold compound or of the passivation dielectric layer(s) on the top surface of the Hall-effect IC die.

Disclosed aspects solve the above-described leadframe problems by providing leadframe designs having additional leadframe material that is then bent relative to the planar portion to form folded conductor portions referred to herein as folded features. The folded features result in an effective increase in metal thickness (such as by a factor of two) for one or more selected portions of the leadframe.

Disclosed aspects include a leadframe comprising leads or lead terminals generally on at least opposing sides, and a plurality of folded features. The folded features include i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the support features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded edge structure is configured to provide an effective increase in metal thickness, which provides benefits including reducing the deformation observed in assembly.

DETAILED DESCRIPTION

Disclosed folded conductor features provides at least one of mechanical function feature and an electrical function. When the folded conductor feature is an electrical function feature, the folded conductor provides a current density reduction as compared to the otherwise same conductor without the folded conductor, which is particularly useful for high current device applications. When the folded conductor feature is a mechanical function feature, the folded conductor feature assists during assembly handling by resisting stress-induced deformation of the leadframe. Disclosed folded features for conductors can provide both a mechanical function and an electrical function. For example, disclosed folded conductor shunt pads can be used for a current shunt type of current sensor to provide both a mechanical function and an electrical function.

FIG.1Ashows a top view of a side of a leadframe100for a Hall-effect current sensor having the loop portion (or head portion)130including additional material (before bending) beyond that of a conventional leadframe showing the additional material130aas a shaded area along the loop portion130, and also additional material120dbetween the inside of the leads120aand120bboth shown as fused leads, with additional material also along the inner edge of the leads120aand120badjacent to the loop portion130shown as120a1and120b1.

The additional material130a,120d,120a1and120bcan be bent to provide folded features including a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. In one arrangement, the angle is 180° relative to the planar portion to be in physical contact with the planar portion, thus being folded back upon itself. In another arrangement, the additional material is bent to provide a folded edge structure that together with the adjacent planar portion provides a double (2×) leadframe thickness, such as being effectively 16 mils thick for a nominal leadframe thickness of 8 mils.

FIG.1Bshows the result of optionally making first and second cuts in the locations shown of the additional material120d,120a1and120b, and130athat facilitates later bending and folding of the additional material to form a folded edge structure. The cuts are generally optional, and are only shown to represent the required deformation of the additional material120d,120a1and120b,130ato enable making the bends.

For example, the cuts shown inFIG.1Bmay not be necessary before bending if there is sufficient ductility of the metal material (e.g., copper) of the leadframe. Alternatively, the additional material120d,120a1,120band130acan be deformed by processes including hydrostatic compression or stamping.FIG.1Cshows a result of the leadframe100after a portion of the folding and bending of the additional material120d,120a1,120band130a.

FIG.1Dshows a side of a finished leadframe now shown as190after completion of the bending and folding of the additional material120d,120a1,120band130ashown inFIG.1Cto form folded edge structures now shown as folded edge structures170d,170a1,170b1and180a. The folded edge structures provide additional cross-sectional area providing effectively roughly twice the metal thickness around the loop portion130and along the portion between the leads120aand120badjacent to loop portion130.

FIG.2shows a top see-through view of an example package Hall-effect sensor device200comprising a leadframe having disclosed folding and bending of additional material along the loop130to provide a folded edge structure180aand also additional material to provide the folded edge structures170a1,170b1along an a surface of the leads120a,120badjacent to the loop130. Also shown is an IC die180with bond pads181, and a Hall-effect element170, both flipchip mounted onto lead terminals160-163of the leadframe. The lead terminals160-163are again shown as being fused lead terminals. The curved portion of the loop130is below the IC die180, and the IC die180is on the lead terminals160-163, thus being in a FCOL configuration.

“Fused leads” as used herein means only a single I+ pin generally being a fused lead120aand a single I− pin shown as fused lead120b, as shown inFIG.2for a first FGC path. These pins each have a cross-sectional area dimension of more than 2 times that of conventional single leads which are generally located on the opposite side (output side) of the leadframe that includes lead terminals160-163. Although not visible in the view shown, between the fused leads120aand120bis a first reduced width curved loop (or head).

The lead terminals160-163can respectively comprise VCC, Vout (providing the sensed Hall voltage), Vref (the reference voltage) and a ground. The respective loops both do not electrically contact the IC die180. The loop that is not shown is for providing a magnetic (B) field to the Hall-effect element170, and the loop130is also generally configured to provide the same function.

The conventional single lead terminals160,161,162and163make an electrical contact to the bond pads181on the IC die180. In one arrangement, as noted above, the lead terminal160can comprise VCC, lead terminal161can comprise Vout, lead terminal162can comprise Vref, and lead terminal163can comprise a ground. In operation, a DC power supply applied between lead terminal160and lead terminal163generates a constant current flow that flows in the semiconductor Hall-effect element170, such as in a p-type Hall effect element. The IC die180is then mounted onto the leadframe200, followed by applying a mold compound. Lastly, the package is trim-and-formed to remove the frame portion of the leadframe, and the leads are then generally then bent, such as in the gull-wing shape.

The Hall element on the IC die180includes a “Hall plate” which may comprise an epitaxial layer on a substrate, such as a semiconductor substrate including silicon in one particular example. The epitaxial region may have low to medium level of doping, such as a relatively lightly-doped pwell region. The Hall-effect element170may include vias. The Hall-effect IC die180may include one or more dielectric passivation layers comprising a nitride, an oxide, a polymer, a polyimide, or benzocyclobutene (BCB).

Although a flipchip arrangement for the IC die180is shown inFIG.2that generally utilizes pillars on the bond pads181, other flipchip bonding arrangements may be used such as utilizing solder balls on the bond pads181. Moreover, the IC die180may be assembled top side up with wirebonds or another connection technology to make the connections between the bond pads181and the leads or lead terminals of the leadframe.

There is signal processing circuitry171shown inFIG.2coupled to an output of the Hall-effect element170, where the signal processing circuitry171generally includes at least one amplifier. Mold compound is shown inFIG.2as241.

FIG.3shows an example leadframe300for a shunt-type current sensor that includes a first pad311and a second pad312upon which a current shunt320is shown placed thereon for creating a current path, and also a die pad301for mounting a sensor IC die330. There are downset support features for the first pad311and the second pad312that include folded features including a planar portion316aand a folded edge structure316bthat curves upwards at an angle of at least 45° relative to the planar portion316a. The folded edge structure316bincreases the thickness of the downset support features316as compared to the planar portion316aalone that is conventionally provided. The leadframes generally arrive with the first pad311and the second pad312, and the die pad301, all being downset relative to the leads314,324, and the downset support features316including additional material for bending to provide the folded edge structure316bfrom the leadframe supplier. The leadframe supplier can generally perform the bending of the additional material to provide the folded edge structures316b.

FIGS.4A-4Cshow a packaged FET400comprising a high-power FET die430on the die pad420of an example leadframe410with a die pad shown optionally configured as an exposed die pad420that has additional material bent to form the folded edge structures421that inFIGS.4B and4Cis bent and folded to increase the thickness of a portion of the die pad420. Disclosed aspects also include non-exposed die pads that have the die pad electrically isolated by the mold compound.

FIG.4Ais a top view of one side of a package FET400including an example leadframe including disclosed folded features shown as a half of a leadframe410that is illustrating a die pad420with additional material421in die pad sections, shown as being shaded regions, and located on the edge of the die pad420.FIG.4Aalso shows a side of the FET die430before the bending and folding of the additional material421that is used to form the folded edge structures471shown inFIGS.4B and4Cdescribed below, with arrows provided showing the direction to be folded. The leads on the side of the leadframe are shown as411-414. Although not shown, there are generally bondwires between the leads411-414and the bond pads431on the top surface of the FET die430.

FIG.4Bshows a 3D depiction of the package FET400shown inFIG.4Anow shown as package FET440after folding of the additional material421to form folded edge structures471.FIG.4Cis a front view depiction of the packaged FET440shown inFIG.4Bfrom the perspective of the eye when it is being viewed from the far left ofFIG.4C.

Examples

Disclosed aspects are further illustrated by the following specific Examples, which should not be construed as limiting the scope or content of this Disclosure in any way.

A linear numerical model was created using a unit shear force [1 N/m2] at the LDF die attach pad (DAP) or pads for the current shunt to simulate the deformation observed during assembly. For conventional pads for the current shunt and downset support features for the pads of the current shunt, such as downset support features316(without the folded edge structure316b) and first and second pads311and312shown inFIG.3above, the displacement was found to be 54.6 nm. For the leadframe portion500shown inFIG.5Athat included only the endmost downset support features316having the folded edge structure now shown as511and512having disclosed bending to provide an extra effective thickness to provide additional mechanical robustness, the displacement during assembly of the pad shown as312for the current shunt was reduced to 36.7 N/m2, or 67.2% as compared to the original leadframe design. Leads are shown as314.

The leadframe portion530shown inFIG.5Bincludes additional material now shown as folded edge structure539for the downset support features316to provide extra thickness to provide additional mechanical robustness. The term folded edge structure as used here means that the downset portion of the downset support features316include a folded edge structure511,512similar to that shown inFIG.5A. However, inFIG.5Ball the downset support features316had additional material configured as the folded edge structure511and512, where inFIG.5Aonly the outer downset support features316had the folded edge structure511and512. The displacement during assembly for pads312for the current shunt for this leadframe having the folded edge structures511and512was found to be reduced to 25.4 N/m2, or a 46.5% reduction compared to the original LDF design lacking the folded edge structures511and512.

The leadframe portion560shown inFIG.5Cincludes downset support features316having disclosed folded edge structures569for providing an extra thickness configured as interlocking pad ears. The folding of the folded edge structures569creates a constrained region such that that the pad312for the current shunt cannot move further because the pads including pad312hits the pad ears569when moved. The displacement during assembly for the pad312for the current shunt was found to be reduced to 23.3 N/m2, or a 43.7% reduction as compared to the original LDF design.

Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different leadframe-based packaged devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

Those having ordinary skill in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the above-described aspects.