Semiconductor devices with dielectric passivation layer and methods of manufacturing thereof

A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

BACKGROUND

Embodiments of the present disclosure are discussed in the context of forming a gate-all-around (GAA) field-effect-transistor (FET) device, and in particular, in the context of forming a replacement gate of a GAA FET device.

DETAILED DESCRIPTION

In general, to make an integrated circuit on a substrate, a number of fins can be formed over the substrate. The fins may have multiple groups, each of which may provide a respective function in the integrated circuit. In certain cases, the fins in each group are spaced from each other with a first distance and two adjacent groups are spaced from each other with a second distance, wherein the second distance is greater than the first distance. As such, the fins (and corresponding device features) on respective edges of the adjacent groups may experience imbalanced processing conditions (e.g., different etching conditions when compared to the fins away from the edge), which is sometimes referred to as “iso-dense loading effect.” This can cause various issues such as, for example, a poorly formed profile of the metal gate structure over the fins on the edges.

The present disclosure provides various embodiments of a semiconductor device and a method for forming the same, which can significantly limit the above-identified issues. For example, the semiconductor device, as disclosed herein, includes one or more inactive fins disposed on the edges of two adjacent fin groups, each of which includes a number of active fins. Such adjacent fin groups may be spaced apart with each other by a distance (hereinafter “inter-fin-group distance”) greater than a distance separating the fins in each group (hereinafter “intra-fin-group distance”). In some embodiments, the active fin may be adopted as an active (e.g., electrically functional) fin or channel in a completed GAA FET device; and the inactive fin may not be adopted as an active (e.g., electrically functional) fin or channel in a completed GAA FET device. Further, in some embodiments, each of the fins (including the active and inactive fins) may include a number of semiconductor layers (e.g., nanosheets, nanowires, or otherwise nanostructures) vertically spaced apart from each other, in which each active fin is coupled with source/drain structures (e.g., epitaxially grown semiconductor structures) and each inactive fin is coupled with dielectric trenches.

By inserting the inactive fins on the edges of adjacent fin groups, the active fins in each of the fin groups can suffer significantly less iso-dense loading effect. This is because the inactive fins, which will not be functional, may protect the active fins from experiencing the effect. Further, by coupling the dielectric trench to “inactivate” the fins on the edges, various advantages can be provided especially in advanced processing nodes. For example, the dielectric trench may not be formed until a dummy gate structure, which will be replaced with a metal gate structure, is defined and formed. Even forming an inactive fin, the existing technologies typically forms such an inactive fin in a relatively early processing stage (e.g., prior to STI recessing, prior to forming a dummy gate structure). By “delaying” a timing to inactive the fins, a profile of the dummy gate structure, which is accordingly inherited by the metal gate structure, can be well defined and reserved. Thus, overall performance of the disclosed semiconductor device can be significantly enhanced.

FIG.1illustrates a perspective view of an example GAA FET device100, in accordance with various embodiments. The GAA FET device100includes a substrate102and a number of nanostructures (e.g., nanosheets, nanowires, etc.)104above the substrate102. The nanostructures104are vertically separated from one another. Isolation regions106are formed on opposing sides of a protruded portion of the substrate102, with the nanostructures104disposed above the protruded portion. A gate structure108wraps around each of the nanostructures104(e.g., a full perimeter of each of the nanostructures104). Source/drain structures are disposed on opposing sides of the gate structure108, e.g., source/drain structure110shown inFIG.1. An interlayer dielectric (ILD)112is disposed over the source/drain structure110.

FIG.1depicts a simplified GAA FET device, and thus, it should be understood that one or more features of a completed GAA FET device may not be shown inFIG.1. For example, the other source/drain structure opposite the gate structure108from the source/drain structure110and the ILD disposed over such a source/drain structure are not shown inFIG.1. Further,FIG.1is provided as a reference to illustrate a number of cross-sections in subsequent figures. As indicated, cross-section A-A extends along a longitudinal axis of the nanostructures104and in a direction of a current flow between the source/drain structures (e.g., in the Y direction). Cross-section B-B extends along an axis parallel with a longitudinal axis of the gate structure108, which cut across the source/drain structure110(e.g., in the X direction). Subsequent figures refer to these reference cross-sections for clarity.

FIG.2illustrates a flowchart of a method200to form a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method200can be used to form a FinFET device, a GAA FET device (e.g., GAA FET device100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a gate-all-around (GAA) transistor device, or the like. It is noted that the method200is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method200ofFIG.2, and that some other operations may only be briefly described herein. In some embodiments, operations of the method200may be associated with cross-sectional or top views of an example GAA FET device at various fabrication stages as shown inFIGS.3,4,5,6A,6B,6C,6D,6E,6F,6G,7A,7B,7C,7D,8A,8B,8C,8D,9A,9B,9C,9D,10A,10B,10C,10D,11A,11B,11C,11D,12A,12B, and12C, respectively, which will be discussed in further detail below.

In brief overview, the method200starts with operation202of providing a substrate. The method200continues to operation204of forming a number of fin structures over the substrate. Each fin structure includes a number of first semiconductor layers and a number of second semiconductor layers. The method200continues to operation206of forming an isolation structure. The method200continues to operation208of forming one or more dummy gate structures. The method200continues to operation210of removing respective portions of the each of the fin structures. The method200continues to operation212of forming a dielectric passivation layer. The method200continues to operation214of patterning the dielectric passivation layer. The method200continues to operation216of forming source/drain structures. The method200continues to operation218of forming an interlayer dielectric. The method200continues to operation220of forming one or more active gate structures by removing the one or more dummy gate structures and the first semiconductor layers.

As mentioned above,FIGS.3-12Ceach illustrate, in a cross-sectional or top view, a portion of a GAA FET device300at various fabrication stages of the method200ofFIG.2. The GAA FET device300is similar to the GAA FET device100shown inFIG.1, but with multiple gate structures and multiple sets of nanostructures104(where each set is sometimes referred to as a fin structure in a completed GAA FET device). AlthoughFIGS.3-12Cillustrate the GAA FET device300, it is understood the GAA FET device300may include a number of other devices such as inductors, fuses, capacitors, coils, etc., which are not shown inFIGS.3-12C, for purposes of clarity of illustration.

Corresponding to operation202ofFIG.2,FIG.3is a cross-sectional view of the GAA FET device300including a semiconductor substrate302at one of the various stages of fabrication. The cross-sectional view ofFIG.3is cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1).

Corresponding to operation204ofFIG.2,FIG.4is a cross-sectional view of the GAA FET device300including a number of fin structures400A,400B,400C,410A,410B, and410C, at one of the various stages of fabrication. The cross-sectional views ofFIG.4is cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1).

As shown, the fin structures400A-C may be formed as a first fin group400in a first area of the substrate302; and the fin structures410A-C may be formed as a second fin group410in a second area of the substrate302. Although three fin structures are included in each fin group, it should be understood that each fin group can include any number of fin structures, while remaining within the scope of the present disclosure. Each of the fin structures400A-C (in the first fin group400) may be laterally spaced from one another (e.g., in the X direction) by a first (intra-fin-group) distance, D1; and each of the fin structures410A-C (in the second fin group410) may be laterally spaced from one another (e.g., in the X direction) by a second (intra-fin-group) distance, D2. Further, the first and second fin groups400and410are laterally spaced by a third (inter-fin-group) distance, D3, different from D1and D2.

For example, the fin structures400B and400C in the same first fin group400are spaced from each other by D1(similarly, the fin structures410B and410C in the same second fin group410are spaced from each other by D2), and the fin structure400C on an “edge” of the first fin group and the fin structure410C on an “edge” of the second fin group are spaced from each other by D3. In some embodiments, the fin structures400C and410C may sometimes be referred to as edge fin structures. The term “edge fin structure,” as used herein, may refer to a fin structure that is disposed as a last one in a first fin group, and next to a second fin group. Accordingly, a fin structure that is not disposed on the edge of a fin group (e.g., with one or more edge fin structures disposed next to it) may sometimes be referred to as a “non-edge fin structure.” In various embodiments, D3is greater than any of D1or D2. As a non-limiting example, D3can range from about 10 nanometers (nm) to about 3000 nm, and D1and D2can each range from about 5 nm to about 300 nm.

Each of the fin structures400A-C and410A-C includes a number of first semiconductor layers and a number of second semiconductor layers alternately disposed on top of one another. Using the fin structure400A (shown inFIG.4) as a representative example, the fin structure400A includes first semiconductor layers402and second semiconductor layers404. The first semiconductor layers402and the second semiconductor layers404are alternatingly disposed on top of one another (e.g., along the Z direction). For example, one of the second semiconductor layers404is disposed over one of the first semiconductor layers402then another one of the first semiconductor layers402is disposed over the second semiconductor layer404, so on and so forth.

Each of the fin structures400A-C and410A-C may include any number of alternately disposed first and second semiconductor layers402and404. For example inFIG.4, the fin structure400A includes 3 first semiconductor layers402, with 3 second semiconductor layers404alternatingly disposed therebetween and with one of the second semiconductor layers404being the topmost semiconductor layer. It should be understood that the fin structure of the GAA FET device300can include any number of first semiconductor layers and any number of second semiconductor layers, with either one of the first or second semiconductor layers being the topmost semiconductor layer, while remaining within the scope of the present disclosure.

The semiconductor layers402and404may have respective different thicknesses. Further, the first semiconductor layers402may have different thicknesses from one layer to another layer. The second semiconductor layers404may have different thicknesses from one layer to another layer. The thickness of each of the semiconductor layers402and404may range from few nanometers to few tens of nanometers. The bottommost layer of the fin structure may be thicker than other semiconductor layers402and404. In an embodiment, each of the first semiconductor layers410has a thickness ranging from about 5 nanometers (nm) to about 20 nm.

The two semiconductor layers402and404have different compositions. In various embodiments, the two semiconductor layers402and404have compositions that provide for different oxidation rates and/or different etch selectivity between the layers. In an embodiment, the first semiconductor layers402include silicon germanium (Si1-xGex), and the second semiconductor layers404include silicon (Si). In an embodiment, each of the second semiconductor layers404is silicon that may be undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed when forming the layers404(e.g., of silicon).

In various embodiments, the semiconductor layers404may be intentionally doped. For example, when the GAA FET device300is configured in n-type (and operates in an enhancement mode), each of the semiconductor layers404may be silicon that is doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the GAA FET device300is configured in p-type (and operates in an enhancement mode), each of the semiconductor layers404may be silicon that is doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb). In another example, when the GAA FET device300is configured in n-type (and operates in a depletion mode), each of the semiconductor layers404may be silicon that is doped with an n-type dopant instead; and when the GAA FET device300is configured in p-type (and operates in a depletion mode), each of the semiconductor layers404may be silicon that is doped with a p-type dopant instead. In some embodiments, each of the semiconductor layers402is Si1-xGexthat includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the semiconductor layers402of Si1-xGexin molar ratio. Furthermore, the first semiconductor layers402may include different compositions among them, and the second semiconductor layers404may include different compositions among them.

Either of the semiconductor layers402and404may include other materials, for example, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. The materials of the semiconductor layers402and404may be chosen based on providing differing oxidation rates and/or etch selectivity.

The semiconductor layers402and404can be epitaxially grown from the semiconductor substrate302as blanket layers, respectively. For example, a number of blanket semiconductor layers402and a number of blanket semiconductor layers404may be grown on the substrate302by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and/or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate302extends upwardly, resulting in the blanket semiconductor layers402and404having the same crystal orientation with the semiconductor substrate302. Upon growing the blanket semiconductor layers402and404on the semiconductor substrate302(as a stack), the stack may be patterned to form the fin structures (e.g.,400A-C,410A-C).

The fin structures are formed by patterning the blanket semiconductor layers402-404and the semiconductor substrate302using, for example, photolithography and etching techniques. For example, a mask layer (which can include multiple layers such as, for example, a pad oxide layer and an overlying pad nitride layer) is formed over the topmost semiconductor layer. The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer may act as an adhesion layer between the topmost semiconductor layer and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example.

The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer and pad nitride layer to form a patterned mask.

The patterned mask can be subsequently used to pattern exposed portions of the blanket semiconductor layers402-404and the substrate302to form trenches (or openings)420,425, and430, thereby defining the fin structures400A-C and410A-C between adjacent trenches. For example, the trench420may be formed to define adjacent fin structures400A and400B, and/or400B and400C; the trench425may be formed to define adjacent fin structures400C and410C; and the trench430may be formed to define adjacent fin structures410A and410B, and/or410B and410C. Accordingly, respective widths (along the X direction) of the trenches420,425, and430can be characterized with the distances, D1, D3, and D2, respectively, Each of the fin structures400A-C and410A-C can have a width extending along the X direction that is of about 3 nm to about 100 nm. In some embodiments, the fin structures400A-C and410A-C are formed by etching the blanket semiconductor layers402-404and substrate302using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or combinations thereof. The etch may be anisotropic. In some embodiments, the trenches420-430may be strips (when viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches420-430may be continuous and surround corresponding fin structure(s).

Corresponding to operation206ofFIG.2,FIG.5is a cross-sectional view of the GAA FET device300including an isolation structure502, at one of the various stages of fabrication. The cross-sectional views ofFIG.5is cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1).

The isolation structure502, which is formed of an insulation material, includes one or more portions to electrically isolate neighboring fin structures from each other. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other insulation materials and/or other formation processes may be used. In an example, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP), may remove any excess insulation material and form a top surface of the isolation structure502and a top surface of the fin structures400A-C and410A-C that are coplanar (not shown). The patterned mask used to define the fin structures400A-C and410A-C may also be removed by the planarization process.

In some embodiments, the isolation structure502includes a liner, e.g., a liner oxide (not shown), at the interface between each portion of the isolation structure502and the substrate302. In some embodiments, the liner oxide is formed to reduce crystalline defects at the interface between the substrate302and the isolation structure502. Similarly, the liner oxide may also be used to reduce crystalline defects at the interface between the fin structures400A-C and410A-C and the isolation structure502. The liner oxide (e.g., silicon oxide) may be a thermal oxide formed through a thermal oxidation of a surface layer of the substrate302, although other suitable method may also be used to form the liner oxide.

Next, the isolation structure502is recessed to form a shallow trench isolation (STI) structure502, as shown inFIG.5. The isolation structure502is recessed such that respective upper portions of the fin structures400A-C an410A-C protrude from between neighboring portions of the STI structure502. A top surface of the STI structure502may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or combinations thereof. The top surface of the STI structure502may be formed flat, convex, and/or concave by an appropriate etch. The isolation structure502may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation structure502. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation structure502.

Corresponding to operation208ofFIG.2,FIG.6Ais a top view of the GAA FET device300including one or more dummy gate structures600and610, at one of the various stages of fabrication; andFIG.6Bis a corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.6Bis cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1).

As shown inFIG.6A, the dummy gate structures600and610are formed over the fin structures400A-C and410A-C, respectively, where the fin structures400A-C are separated from each other by D1, the fin structures410A-C are separated from each other by D2, and the fin groups400A-C and410A-C (the edge fin structures400C and410C) are separated from each other by D3. The dummy gate structures600and610can each extend along a lateral direction (e.g., the X direction) perpendicular to the lateral direction along which the fin structures extend. The dummy gate structures600and610may be placed where respective active (e.g., metal) gate structures are later formed, in various embodiments. For example inFIG.6A, the dummy gate structure600is placed over a respective portion of each of the fin structures400A-C; and the dummy gate structure610is placed over a respective portion of each of the fin structures410A-C. Such an overlaid portion of the fin structure is later formed as a conduction channel, which includes portions of the second semiconductor layers404, and the dummy gate structures600-610are each replaced with an active gate structure to warp around each of the portions of the second semiconductor layers404.

The dummy gate structures600-610each include a dummy gate dielectric and a dummy gate, in some embodiments. For purposes of clarity of illustration, the dummy gate dielectric and dummy gate are shown as a single piece in the figures of the present disclosure. To form the dummy gate structures600-610, a dielectric layer is formed on the fin structures400A-C and410A-C. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like, and may be deposited or thermally grown. A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like. After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using suitable lithography and etching techniques to form a mask. The pattern of the mask then may be transferred to the gate layer and the dielectric layer by a suitable etching technique to form the dummy gate structures600-610.

Referring toFIG.6B, the dummy gate structures600-610(which are shown in dotted lines) are formed over the fin structures400A-C and410A-C, respectively, and in direct contact with the STI structure502. It should be appreciated that the GAA FET device300can include the dummy gate structures formed in other configurations, while remaining within the scope of the present disclosure. For example, between the adjacent fin structures (along the X direction), a cladding layer (similar as the first semiconductor layer402) and a dummy fin structure (overlaid or protected by a high-k dielectric layer) can be formed to produce a substantially planar top surface shared by the fin structures, the cladding layer, and the dummy fin structure. As used herein, the term “substantially planar” refers to a structure when the deviation of the structure from a plane is within the statistical atomic level variations inherent within semiconductor processing methods known in the art. In such embodiments, the dummy gate structures600-610may be formed over such a substantially planar top surface, with an etch stop layer disposed therebetween. The etch stop layer may include silicon oxide. The etch stop layer may be formed by a deposition process, such as chemical vapor deposition (CVD) (e.g., plasma enhanced chemical vapor deposition (PECVD), high aspect ratio process (HARP), or combinations thereof) process, atomic layer deposition (ALD) process, another applicable process, or combinations thereof.

The dummy gate structures600and610can be formed in various configurations, which will be discussed below with respect toFIGS.6A, and6B-6G. Referring again toFIG.6A, the dummy gate structures600and610are aligned along the X direction, and have respective widths along the Y direction. For example, the dummy gate structure600has a width, W1, and the dummy gate structure610has a width, W2. W1and W2can each range from about 1 nm to about 500 nm. In the illustrated example ofFIG.6A, W1is about equal to W2. The aligned dummy gate structures600and610can have different widths. For example, W1can be different from W2, as illustrated inFIG.6C. The dummy gate structures600and610can be offset from each other along the Y direction with a distance SG, as illustrated inFIG.6D. The distance may range from about 1 nm to about 500 nm. In some embodiments, the dummy gate structures600and610may be integrally formed as a single piece, as illustrated inFIG.6E. In some embodiments, the dummy gate structures600and610may be first integrally formed as a single piece, and then be disconnected or cut separately with a gate isolation structure620, as illustrated inFIG.6F. The gate isolation structure620may be formed of a dielectric material, thereby causing the dummy gate structures600and610to be electrically isolated from each other. The gate isolation structure620may extend along the X direction with a distance less than or equal to D3. Such gate isolation structure620can be formed over an STI (e.g.,502) or a dielectric dummy fin structure (not shown) disposed between the edge fin structures400C and410C. In some embodiments, the edge fin structures400C and410C may be formed as a single edge fin structure between two fin groups, as illustrated inFIG.6G. As such, D3may not be present.

Corresponding to operation210ofFIG.2,FIG.7Ais a top view of the GAA FET device300in which respective portions of each of the fin structures400A-C and410A-C that are not overlaid by the dummy gate structure600or610are removed, at one of the various stages of fabrication.FIGS.7B,7C, and7Dare corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.7Bis cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); the cross-sectional view ofFIG.7Cis cut in a direction along the lengthwise direction of a non-edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); and the cross-sectional view ofFIG.7Dis cut in a direction along the lengthwise direction of an edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1). As representative examples,FIG.7Cis cut along a lengthwise direction of the fin structure400B; andFIG.7Dis cut along a lengthwise direction of the fin structure400C.

The dummy gate structures600-610can serve as a mask to etch the non-overlaid portions of the fin structures400A-C and410A-C, which results in the fin structures400A-C and410A-C each including remaining portions of the semiconductor layers402and404alternatingly stacked on top of one another. The etched (removed) portions of the fin structures400A-C and410A-C are shown in dotted lines inFIG.7B. Such an etching step may be stopped when an intermediate surface of the fin structures400A-C and410A-C is about leveled with the top surface of the isolation structure502. In the illustrated example ofFIG.7B, the etched intermediate surface of the fin structures and the top surface of the isolation structure502share a flat surface. It should be understood that the etched intermediate surface of each of the fin structures may be recessed with respect the top surface of the isolation structure502(e.g., curve inwardly toward the substrate302), in some embodiments. In some other embodiments, while removing the non-overlaid portions of the edge fin structures400C and410C, the non-overlaid portions of the non-edge fin structures400A-B and410A-B may remain through the step of growing the respective source/drain structures. For example, the source/drain structures, which will be discussed in further detail below, can wrap around such “protruding” portions of the (e.g., Si) semiconductor layers404in the non-edge fin structures400A-B and410A-B.

FIGS.7C and7Dillustrate the cross-sectional view of the GAA FET device300cut across the fin structures400B and400C, respectively. Along the Z direction, the fin structures400B may have newly formed sidewalls that are aligned with sidewalls of the dummy gate structure600, which can further include gate spacers602disposed on its both sides; and the fin structures400C may have newly formed sidewalls that are also aligned with the sidewalls of the dummy gate structure600. Although not shown in the top view ofFIG.7A, it should be understood that one or more dummy gate structures (in parallel with the dummy gate structures600/610) can be formed to overlay the fin structures400A-C and/or410A-C. For example, each of the fin structures can be overlaid by multiple dummy gate structures that are in parallel with one another. Each of the dummy gate structures can serve as a mask to etch non-overlaid portions of the fin structures. As such, trenches, which are sandwiched between respective different remaining portions of each of the fin structures, can be formed.

For example inFIG.7C, trenches701are formed on the sides of the dummy gate structure600(and on the sides of the remaining portion of the fin structure400B that is overlaid by the dummy gate structure600). Each of the trenches701is sandwiched between the remaining portion of the fin structure400B overlaid by the dummy gate structure600and a remaining portion of the fin structure400B overlaid by another dummy gate structure (shown in dotted lines). Hereinafter, the remaining portion of the fin structure400B overlaid by the dummy gate structure600is referred to as “first remaining portion of fin structure400B.” For example inFIG.7D, trenches711are formed on the sides of the dummy gate structure600(and on the sides of the remaining portion of the fin structure400C that is overlaid by the dummy gate structure600). Each of the trenches711is sandwiched between the remaining portion of the fin structure400C overlaid by the dummy gate structure600and a remaining portion of the fin structure400C overlaid by another dummy gate structure (shown in dotted lines). Hereinafter, the remaining portion of the fin structure400C overlaid by the dummy gate structure600is referred to as “first remaining portion of fin structure400C.”

Upon forming the trenches (e.g.,701,711), inner spacers are formed along respective etched ends of the semiconductor layers402. As shown inFIG.7C, inner spacers700extend along respective etched ends of each of the semiconductor layers402in the first remaining portion of fin structure400B; and as shown inFIG.7D, inner spacers710extend along respective etched ends of each of the semiconductor layers402in the first remaining portion of fin structure400C. The inner spacers700and710may be concurrently or respectively formed.

To form the inner spacers700and710, respective end portions of each of the semiconductor layers402may first be removed. The end portions of the semiconductor layers402can be removed (e.g., etched) using a “pull-back” process to pull the semiconductor layers402back by an initial pull-back distance. In an example where the semiconductor layers404include Si, and the semiconductor layers402include Si1-xGex, the pull-back process may include a hydrogen chloride (HCl) gas isotropic etch process, which etches SiGe without attacking Si. As such, the Si layers404may remain intact during this process.

Next, the inner spacers700and710can be formed along the etched ends of each of the semiconductor layers402. Thus, the inner spacers700and710(e.g., their respective inner sidewalls) may follow the profile of the etched ends of the semiconductor layers402. In some embodiments, the inner spacers700and710can be formed conformally by chemical vapor deposition (CVD), or by monolayer doping (MLD) of nitride followed by spacer RIE. The inner spacers700and710can be deposited using, e.g., a conformal deposition process and subsequent isotropic or anisotropic etch back to remove excess spacer material on the sidewalls of the remaining portions of the fin structures (e.g.,400B,400C) and on a surface of the semiconductor substrate302. For example, the inner spacers700and710can be formed of silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5) appropriate to the role of forming an insulating gate sidewall spacers of transistors.

Corresponding to operation212ofFIG.2,FIG.8Ais a top view of the GAA FET device300including a passivation layer802, at one of the various stages of fabrication.FIGS.8B,8C, and8Dare corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.8Bis cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); the cross-sectional view ofFIG.8Cis cut in a direction along the lengthwise direction of a non-edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); and the cross-sectional view ofFIG.8Dis cut in a direction along the lengthwise direction of an edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1). As representative examples,FIG.8Cis cut along a lengthwise direction of the fin structure400B; andFIG.8Dis cut along a lengthwise direction of the fin structure400C.

As shown inFIGS.8A-B, the passivation layer802can be (e.g., conformally) formed over the area where the etched portions of the fin structures400A-C and410A-C were located. For example, the passivation layer802overlays the intermediate surfaces of the fin structures400A-C and410A-C and the top surface of the isolation structure502. Further, the passivation layer802can extend into (e.g., line) the trenches formed on the sides of each remaining portion of the fin structure400B. As shown inFIG.8C, the passivation layer802lines the trenches701formed on the sides of the first remaining portion of fin structure400B.

The passivation layer802can line respective bottom surface and inner sidewalls of each of the trenches701. In some embodiments, one inner sidewall of the trench701can be constituted by the sidewall of the first remaining portion of fin structure400B. Specifically, such an inner sidewall includes respective exposed sidewalls of the inner spacers700, respective exposed sidewalls of the semiconductor layers404, and the exposed sidewall of the dummy gate structure600. The other inner sidewall of the trench701can be constituted by the sidewall of another remaining portion of the fin structure400B (shown in dotted lines) next to the shown first remaining portion of fin structure400B, which can include the respective exposed sidewalls of inner spacers, the respective exposed sidewalls of semiconductor layers404, and the exposed sidewall of a dummy gate structure. As shown inFIG.8D, the passivation layer802lines the trenches711formed on the sides of the first remaining portion of fin structure400C. The passivation layer802can line respective bottom surface and inner sidewalls of each of the trenches711. In some embodiments, one inner sidewall of the trench711can be constituted by the sidewall of the first remaining portion of fin structure400C. Specifically, such an inner sidewall includes respective exposed sidewalls of the inner spacers710, respective exposed sidewalls of the semiconductor layers404, and the exposed sidewall of the dummy gate structure600. The other inner sidewall of the trench711can be constituted by the sidewall of another remaining portion of the fin structure400C (shown in dotted lines) next to the shown first remaining portion of fin structure400C, which can include the respective exposed sidewalls of inner spacers, the respective exposed sidewalls of semiconductor layers404, and the exposed sidewall of a dummy gate structure.

In some other embodiments, the inner spacers700and710may be formed after forming (and patterning, which will be discussed below) the passivation layer802. As such, one inner sidewall of the trench701may include respective exposed sidewalls of the semiconductor layers402, respective exposed sidewalls of the semiconductor layers404, and the exposed sidewall of the dummy gate structure600; and the other inner sidewall of the trench701may include respective exposed sidewalls of the semiconductor layers402in an adjacent remaining portion of the fin structure400B, respective exposed sidewalls of the semiconductor layers404in the adjacent remaining portion of the fin structure400B, and the exposed sidewall of a dummy gate structure next to the dummy gate structure600. Similarly, one inner sidewall of the trench711may include respective exposed sidewalls of the semiconductor layers402, respective exposed sidewalls of the semiconductor layers404, and the exposed sidewall of the dummy gate structure600; and the other inner sidewall of the trench711may include respective exposed sidewalls of the semiconductor layers402in an adjacent remaining portion of the fin structure400C, respective exposed sidewalls of the semiconductor layers404in the adjacent remaining portion of the fin structure400C, and the exposed sidewall of a dummy gate structure next to the dummy gate structure600.

The passivation layer802includes a material unfavorable for epitaxial growth, in some embodiments. As such, in a later stage of process where epitaxial growth is performed (e.g., when forming source/drain structures), the epitaxial growth can be significantly limited in the trenches where the passivation layer802still remains, e.g., trenches711, which will be discussed below. In some embodiments, the passivation layer802can include one or more silicon-based dielectric materials such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or combinations thereof, and may be deposited. In some embodiments, the passivation layer802can include one or more metal-based materials such as, for example, cobalt, tungsten, hafnium oxide, aluminum oxide, or combinations thereof, and may be deposited.

Corresponding to operation214ofFIG.2,FIG.9Ais a top view of the GAA FET device300in which the passivation layer802is patterned to selectively remain over the trenches in the edge fin structures, at one of the various stages of fabrication.FIGS.9B,9C, and9Dare corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.9Bis cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); the cross-sectional view ofFIG.9Cis cut in a direction along the lengthwise direction of a non-edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); and the cross-sectional view ofFIG.9Dis cut in a direction along the lengthwise direction of an edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1). As representative examples,FIG.9Cis cut along a lengthwise direction of the fin structure400B; andFIG.9Dis cut along a lengthwise direction of the fin structure400C.

As shown inFIGS.9A-B, the passivation layer802can be patterned (e.g., using photolithography and etching techniques) to remove from the area where the non-edge fin structures400A-B and410A-B are located. Alternatively, the passivation layer802may be formed over the area (as shown) by masking the non-edge fin structures400A-B and410A-B. Upon patterning the passivation layer802, the passivation layer802may partially overlay the intermediate surfaces of the fin structures400A-C and410A-C and the top surface of the isolation structure502. For example inFIG.9B, the passivation layer802may remain over the area where the etched portions of the edge fin structures400C and410C were located. As further illustrated inFIG.9C, the passivation layer802does not remain in the trenches701. The sidewalls of the first remaining portion of fin structure400B (and the sidewalls of the adjacent remaining portions of the fin structure400B) may be re-exposed. As further illustrated inFIG.9D, the passivation layer802remains lining the trench711. In various embodiments, the remaining passivation layer802may have a conformal thickness in the range of about 3˜300 angstroms (Å). The semiconductor layers404in each remaining portion of the edge fin structure400C (including the shown “first remaining portion of fin structure400C” and the adjacent remaining portions of the fin structure400C (shown in dotted lines)) remain non-exposed. As such, the (epitaxial) growth of source/drain structures in the edge fin structure400C can be significantly limited.

The main etch gas used to pattern the passivation layer802depends on the material of the passivation layer802. A Si-based passivation layer may use Cl2/HBr-based main etch gas, while a metal-based passivation layer may use BCl3/Cl2-based main etch gas. For etch of the passivation layer802, the dry etch conditions for the passivation layer may include a main etch gas of Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, and/or H2, for example. A passivation gas for tuning etch selectivity may include N2, O2, CO2, SO2, CO, and/or SiCl4. A dilution gas may include at least one of Ar, He, or Ne, for example. The plasma source power may be between 100 watts (W) and 3000 W. The plasma bias power may be between 0 W and 3000 W. The pressure may be between 1 mTorr and 800 mTorr. The flow rate may be between 1 standard cubic centimeters per minute (sccm) and 5000 sccm. For a wet clean etch, the main etch chemical may include at least one of HF, F2, or H3PO4, for example. An assisted etch chemical for selectivity tuning may include at least one of O3, H2SO4, HCl, HBr, or NH3. A solvent for the wet etch may include at least one of D1water, alcohol, or acetone.

Corresponding to operation216ofFIG.2,FIG.10Ais a top view of the GAA FET device300including source/drain structures1000A,1000B,1010A, and1010B formed in the non-edge fin structures400A,400B,410A, and410B, respectively, at one of the various stages of fabrication.FIGS.10B,10C, and10Dare corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.10Bis cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); the cross-sectional view ofFIG.10Cis cut in a direction along the lengthwise direction of a non-edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); and the cross-sectional view ofFIG.10Dis cut in a direction along the lengthwise direction of an edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1). As representative examples,FIG.10Cis cut along a lengthwise direction of the fin structure400B; andFIG.10Dis cut along a lengthwise direction of the fin structure400C.

The source/drain structures1000A-B and1010A-B may be formed using an epitaxial layer growth process on exposed ends (sidewalls) of each of the semiconductor layers404in the non-edge fin structures400A-B and410A-B. In some embodiments, a bottom surface of the source/drain structures1000A-B and1010A-B may be leveled with the top surface of the isolation structure502, as shown inFIG.10B. In some other embodiments, the bottom surface of the source/drain structures1000A-B and1010A-B may be lower than the top surface of the isolation structure502. The source/drain structures (e.g.,1000A and1000B,1010A and1010B) in the adjacent fin structures may merge with each other. On the other hand, in some embodiments, a top surface of the source/drain structures1000A-B and1010A-B may be higher than a top surface of the topmost semiconductor layers404in the non-edge fin structures400A-B and410A-B, as shown inFIG.10Cwhere the fin structure400B is shown. In some other embodiments, the top surface of the source/drain structures1000A-B and1010A-B may be leveled with or lower than the top surface of the topmost semiconductor layers404.

The source/drain structures1000A-B and1010A-B are electrically coupled to the respective semiconductor layers404of the non-edge fin structures400A-B and410A-B. As such, the semiconductor layers404of each of the non-edge fin structures400A-B and410A-B may collectively function as the “active” channel of a GAA transistor that conducts current flowing between its respective source/drain structures. However, it should be noted that at this stage of fabrication, those active GAA transistors are not finished yet. As the semiconductor layers404of the edge fin structures400C and410C remain overlaid by the passivation layer802, no source/drain structures can be formed in the edge fin structures400C and410C. As such, the semiconductor layers404of each of the edge fin structures400C and410C may collectively function as the “inactive” channel of a GAA transistor that does not conduct current.

In-situ doping (ISD) may be applied to form doped source/drain structures1000A-B and1010A-B, thereby creating the junctions for the GAA transistors. N-type and p-type FETs are formed by implanting different types of dopants to selected regions (e.g., the source/drain structures1000A-B and1010A-B) of the device to form the junction(s). N-type devices can be formed by implanting arsenic (As) or phosphorous (P), and p-type devices can be formed by implanting boron (B).

Corresponding to operation218ofFIG.2,FIG.11Ais a top view of the GAA FET device300including an interlayer dielectric (ILD)1102, at one of the various stages of fabrication.FIGS.11B,11C, and11Dare corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.11Bis cut in a direction parallel to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); the cross-sectional view ofFIG.11Cis cut in a direction along the lengthwise direction of a non-edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); and the cross-sectional view ofFIG.11Dis cut in a direction along the lengthwise direction of an edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1). As representative examples,FIG.11Cis cut along a lengthwise direction of the fin structure400B; andFIG.11Dis cut along a lengthwise direction of the fin structure400C.

Upon forming the source/drain structures1000A-B and1010A-B, the ILD1102can be formed by depositing a dielectric material in bulk over the workpiece, and polishing the bulk oxide back (e.g., using CMP) to the level of the dummy gate structures600and610, as illustrated inFIGS.11C-D. Specifically, the ILD1102may overlay the source/drain structures formed in the non-edge fin structures (see, e.g.,FIG.11C); and the ILD1102may fill the trenches formed in the edge fin structures, with the passivation layer802formed therebetween (see, e.g.,FIG.11D). As such, the semiconductor layers404of the edge fin structures are each coupled with one or more dielectric trenches, with the passivation layer sandwiched therebetween. The dielectric material of ILD1102includes silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or combinations thereof.

Corresponding to operation220ofFIG.2,FIG.12Ais a top view of the GAA FET device300including active gate structures1200and1210, at one of the various stages of fabrication.FIGS.12B and12Care corresponding cross-sectional view of the GAA FET device300. The cross-sectional view ofFIG.12Bis cut in a direction along the lengthwise direction of a non-edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1); and the cross-sectional view ofFIG.12Cis cut in a direction along the lengthwise direction of an edge fin structure of the GAA FET device300(e.g., cross-section B-B indicated inFIG.1). As representative examples,FIG.12Bis cut along a lengthwise direction of the fin structure400B; andFIG.12Cis cut along a lengthwise direction of the fin structure400C.

To form the active gate structures1200and1210, the dummy gate structures600-610and the semiconductor layers402of the edge and non-edge fin structures can be removed respectively or concurrently, while leaving the semiconductor layers404substantially intact. After the removal of the dummy gate structures600-610, a gate trench, exposing respective sidewalls of each of the semiconductor layers404that face the X direction, may be formed. After the removal of the semiconductor layers402to further extend the gate trench, respective bottom surface and/or top surface of each of the semiconductor layers404may be exposed. Consequently, a full circumference of each of the semiconductor layers404can be exposed. Next, the active gate structures1200and1210are formed to wrap around each of the semiconductor layers404.

The active gate structure1200and1210each include a gate dielectric and a gate metal, in some embodiments. The gate dielectric can wrap around each of the semiconductor layers404(e.g., the top and bottom surfaces and sidewalls facing the X direction). The gate dielectric may be formed of different high-k dielectric materials or a similar high-k dielectric material. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may include a stack of multiple high-k dielectric materials. The gate dielectric can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the gate dielectric may optionally include a substantially thin oxide (e.g., SiOx) layer, which may be a native oxide layer formed on the surface of each of the semiconductor layers404.

The gate metal can wrap around each of the semiconductor layers404with the gate dielectric disposed therebetween. Specifically, the gate metal can include a number of gate metal sections abutted to each other along the Z direction. Each of the gate metal sections can extend not only along a horizontal plane (e.g., the plane expanded by the X direction and the Y direction), but also along a vertical direction (e.g., the Z direction). As such, two adjacent ones of the gate metal sections can adjoin together to wrap around a corresponding one of the semiconductor layers404, with the gate dielectric disposed therebetween.

The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multi-layers thereof, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals that may include TiN, TaN, Ru, Mo, Al, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.

In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first stack structure including a first plurality of semiconductor layers vertically spaced from one another. The semiconductor device includes a second stack structure including a second plurality of semiconductor layers vertically spaced from one another. The semiconductor device includes a third stack structure including a third plurality of semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction perpendicular to the first lateral direction and wraps around each of the first plurality of semiconductor layers, each of the second plurality of semiconductor layers, and each of the third plurality of semiconductor layers. Ends of each of the first plurality of semiconductor layers are coupled with respective source/drain structures, ends of each of the second plurality of semiconductor layers are coupled with respective source/drain structures, and ends of each of the third plurality of semiconductor layers are coupled with a dielectric passivation layer.

In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a substrate. The semiconductor device includes a first stack structure, a second stack structure, a third stack structure, a fourth stack structure, a fifth stack structure, and a sixth stack structure formed over the substrate. The first through sixth stack structures all extend along a first lateral direction. The second stack structure is separated from each of the first and third stack structures with a first distance, the fifth stack structure is separated from each of the fourth and sixth stack structures with the first distance. The third stack structure is separated from the fourth stack structure with a second distance, and wherein the second distance is greater than the first distance. The semiconductor device includes first source/drain structures coupled to respective ends of an upper portion of the first stack structure. The semiconductor device includes second source/drain structures coupled to respective ends of an upper portion of the second stack structure. The semiconductor device includes first dielectric trenches coupled to respective ends of an upper portion of the third stack structure. The semiconductor device includes second dielectric trenches coupled to respective ends of an upper portion of the fourth stack structure. The semiconductor device includes third source/drain structures coupled to respective ends of an upper portion of the fifth stack structure. The semiconductor device includes fourth source/drain structures coupled to respective ends of an upper portion of the sixth stack structure.

In yet another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a first fin structure, a second fin structure, a third fin structure, a fourth fin structure, a fifth fin structure, and a sixth fin structure formed over a substrate. The first through sixth fin structures all extend along a first lateral direction. The second fin structure is separated from each of the first and third fin structures with a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures with the first distance, and the third fin structure is separated from the fourth fin structure with a second distance. The second distance is greater than the first distance. The method includes forming one or more gate structures overlaying a respective portion of each of the first through six fin structures. The method includes forming a first pair of trenches, a second pair of trenches, a third pair of trenches, a fourth pair of trenches, a fifth pair of trenches, and a sixth pair of trenches by removing respective portions of each of the first through six fin structures that are not overlaid by the one or more gate structures. The method includes forming a dielectric passivation layer over the third and fourth pairs of trenches. The method includes growing source/drain structures in the first, second, fifth, and sixth pairs of trenches, respectively.