Method of manufacturing a semiconductor integrated circuit device

Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased. Side wall spacers can be provided on the sides of the gate electrodes of the MISFETs and on the sides of the local wiring lines, and connection holes to semiconductor regions of these MISFETs are self-aligned to both the gate electrodes and the local wiring lines, whereby capacitor area can be increased and integration of the device can also be increased.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same and, more particularly, to a technique which is particularly effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).

A memory cell of an SRAM or a semiconductor memory device is composed of: a flip-flop circuit acting as an information storage unit for storing information of 1 bit; and a pair of transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors) for controlling the electrical connection between writing/reading data lines and the flip-flop circuit.

The flip-flop circuit of the memory cell is composed of a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters, for example. Each of these CMOS inverters is composed of one drive MISFET and one load MISFET. In this case, the memory cell is of a complete CMOS type of a combination of two drive MISFETs, two load MISFETs and two transfer MISFETs. Of these MISFETs, the transfer MISFETs and the drive MISFETs are of n-channel type whereas the load MISFETs are of p-channel type.

A pair of input/output terminals of the flip-flop circuit (the CMOS inverter) are cross-connected through a pair of wiring lines called “local wiring lines”, for example. Moreover, one of these input/output terminals is supplied with a power supply voltage (e.g., 3 V) of a circuit through a power supply voltage line whereas the other is supplied with a reference voltage (e.g., 0 V) of the circuit through a reference voltage line.

In U.S. Pat. No. 5,523,598, issued Jun. 4, 1996, there is disclosed an SRAM of the complete CMOS type, which is equipped with a pair of aforementioned local wiring lines. In this SRAM, the gate electrodes of the six MISFETs constituting the memory cells, the power supply voltage line connected with one input/output terminal of the flip-flop circuit, the reference voltage line connected with the other input/output terminal, the pair of local wiring lines, and the data lines connected with the drain regions of the transfer MISFETs are individually provided in different conductive layers. In this SRAM, moreover, the local wiring lines and other conductive layers (e.g., the reference voltage line) are arranged to intersect each other so that the reduction in the alpha particle soft error resistance, which might occur upon the miniaturization of the memory cell size and the lowering of the operating power supply voltage, is prevented by forming a capacitor element in the intersection region to increase the storage node capacitance of the memory cells.

SUMMARY OF THE INVENTION

Various problems arise in connection with the SRAM disclosed in U.S. Pat. No. 5,523,598. In the SRAM disclosed the reference voltage line), and the data lines are formed in different conductive layers. As a result, the mask registration allowance when forming the connection holes in the interlayer insulating film by using a photoresist as the mask is increased, resulting in increase of the memory cell size. When the gate electrodes are formed of a conductive film of a first layer, the local wiring lines are formed of a conductive film of a second layer, and the power supply lines are formed of a conductive film of a third layer, for example, it is necessary to ensure the registration allowance for both the gate electrodes and the local wiring lines.

In the SRAM disclosed in the aforementioned U.S. Pat. No. 5,523,598, the paired local wiring lines are formed of the same conductive film. This makes it necessary to arrange the two local wiring lines transversely in the memory cell, so that the memory cell size is increased.

An object of the present invention is to provide a semiconductor integrated circuit device (for example, a semiconductor memory such as a complete CMOS SRAM) having a reduced memory cell size, and a method of fabricating such semiconductor device.

Another object of the present invention is to provide a semiconductor integrated circuit device (e.g., semiconductor memory such as a complete CMOS SRAM) having improved alpha particle soft error resistance, and a method of fabricating such semiconductor device.

The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.

Illustrations of the invention to be disclosed herein will be briefly described in the following. These illustrations are representative of the present invention and do not define the scope thereof, the scope being defined by the appended claims.

According to the present invention, there is provided a semiconductor integrated circuit device comprising an SRAM including memory cells having a flip-flop circuit composed of a pair of drive MISFETs and a pair of load MISFETs, and having a pair of transfer MISFETs, which device-is constructed such that the individual gate electrodes of the drive MISFETs, the load MISFETs and the transfer MISFETs are composed of a first conductive film formed over a major face of a semiconductor substrate; one of the local wiring lines cross-connecting a pair of input/output terminals of the flip-flop circuit, is composed of a second conductive film formed over that first conductive film; and the other of the local wiring lines is composed of a third conductive film formed over the second conductive film, and a method of fabricating the device.

The semiconductor integrated circuit device of the present invention is constructed such that the one and the other of the local wiring lines are so arranged as to have at least partially and vertically overlapping portions, and the one and the other of the local wiring lines and an insulating film interposed therebetween constitute a capacitor element.

In regard to a method for manufacturing a semiconductor integrated circuit device, there is provided a method for manufacturing a semiconductor integrated circuit device (e.g., an SRAM) containing memory cells each having a flip-flop circuit including a pair of drive MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs, comprising the steps of:

(a) preparing (e.g., providing) a semiconductor substrate having a major face, over which the individual gate electrodes of the drive MISFETs, the load MISFETs and the transfer MISFETs are formed;

(b) forming a pair of local wiring lines cross-connecting a pair of input/output terminals of the flip-flop circuit, over the gate electrodes;

(c) forming side wall spacers on the individual side walls of the gate electrodes and the local wiring lines; and

(d) forming connection holes reaching the source regions of the drive MISFETs or the load MISFETs by depositing a second insulating film of an etching rate different from (e.g., greater than) that of the first insulating film over the local wiring lines, on which the side wall spacers are formed, and by etching the second insulating film. Also provided is the device fabricated by this method.

In regard to a method for manufacturing a semiconductor integrated circuit device, there is also provided a method for manufacturing a semiconductor integrated circuit device (e.g., an SRAM) containing memory cells each having a flip-flop circuit composed of a pair of drive MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs, comprising the steps of:

(a) preparing (e.g., providing) a semiconductor substrate having a major face, over which the individual gate electrodes of the drive MISFETs, the load MISFETs and the transfer MISFETs are formed;

(b) forming one of a pair of local wiring lines cross-connecting a pair of input/output terminals of the flip-flop circuit, over the gate electrodes;

(c) forming the other of the paired local wiring lines over the local wiring line formed in step (d);

(d) forming side wall spacers on the individual side walls of the gate electrodes and the one and the other of the local wiring lines, by etching a first insulating film which is deposited over the other of the local wiring lines; and

(e) forming connection holes reaching the source regions of the drive MISFETs or the load MISFETs by depositing a second insulating film of an etching rate different from that of the first insulating film over the other of the local wiring lines, on which the side wall spacers are formed, and by etching the second insulating film. Also provided is the device fabricating by this method.

According to the means thus far described, the paired local wiring lines cross-connecting the input/output terminals of the flip-flop circuit of the memory cell are formed in different conductive layers vertically with respect to the substrate. Therefore the space, required when the paired local wiring lines are composed of the same conductive film, for arranging the two local wiring lines transversely, can be eliminated, and the local wiring lines can be arranged partially in an overlapping manner, thereby reducing the area occupied by the memory cell.

According to the means thus far described, the one and the other of the local wiring lines are so arranged as to overlap vertically, and a capacitor element is formed of the one and the other of the local wiring lines and an insulating film interposed therebetween, so that the storage node capacitance of the memory cell can be increased, preventing the lowering of alpha particle soft error resistance entailed by the miniaturization of the memory cell size and the lowering of the operation power supply voltage. For example, the capacitor area can be about half the area of the memory cell, which realizes a thick capacitor dielectric. Soft error immunity can be achieved even at a 1.8 V supply voltage.

According to the means thus far described, the mask registration allowance when the connection holes are formed in the interlayer insulating film by using a photoresist as the mask can be eliminated, reducing the area occupied by the memory cells. The connection holes can be formed by a self-alignment technique (self-aligned to both the gates and the local wiring lines).

DETAILED DESCRIPTION OF THE INVENTION

While the present invention will be described in connection with specific and preferred embodiments, it will be understood that it is not intended to limit the invention to those embodiments. To the contrary, it is intended to cover all alterations, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Throughout the present disclosure, where devices are described as including or comprising specific components, and methods are described as comprising or including specific steps, it is contemplated that devices of the present invention also consist essentially of, or consist of, the recited components, and methods of the present invention also consist essentially of, or consist of, the recited steps. Accordingly, throughout the present disclosure any described device or process can consist essentially of, or consist of, the recited components or steps.

The present invention will be described in detail in connection with its embodiments with reference to the accompanying drawings. Throughout all the drawings for explaining the embodiments, the portions having the same functions are designated by the same reference numerals, and their repeated description will be omitted.

FIG. 5is an equivalent circuit diagram of a memory cell of an SRAM of a first embodiment of the present invention. This memory cell is arranged at the intersection between a pair of complementary data lines (a data line DL and a data line DL) and a word line WL and is composed of a pair of drive MISFETs Qd1and Qd2, a pair of load MISFETs Qp1and Qp2and a pair of transfer MISFETs Qt1and Qt2. Of these MISFETs, the drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2are of p-channel type, and the load MISFETs Qp1and Qp2are of p-channel type. In short, this memory cell is constructed of a complete CMOS type using four n-channel MISFETs and two p-channel MISFETs.

Of the six MISFETs constituting the aforementioned memory cell, the paired drive MISFETs Qd1and Qd2and the paired load MISFETs Qp1and Qp2constitute a flip-flop circuit acting as an information storing unit for storing information of 1 bit. One input/output terminal (a storage node) of this flip-flop circuit is electrically connected with one of the source and drain regions of the transfer MISFET Qt1, and the other input/output (i.e., a storage node) is electrically connected with one of the source and drain regions of the transfer MISFET Qt2.

The data line DL is electrically connected with the other of the source and drain regions of the transfer MISFET Qt1, and the data line DL is electrically connected with the other of the source and drain regions of the transfer MISFET Qt2. Moreover, one end (each source region of the load MISFETs Qp1and Qp2) of the flip-flop circuit is connected with the power supply voltage (Vcc), and the other (each source region of the drive MISFETs Qd1and Qd2) is connected with a reference voltage Vss. The power supply voltage (Vcc) is, e.g., 3 V whereas the reference voltage (Vss) is, e.g., 0 V (GND).

The input/output terminals of the flip-flop circuit are cross-connected through a pair of local wiring lines L1and L2. In the present embodiment, these paired local wiring lines L1and L2are arranged in different conductive layers, as will be described hereinafter.

A specific construction of the memory cell will be described with reference toFIG. 1(a top plan view of about one memory cell),FIG. 2(a section taken along line A–A′ ofFIG. 1),FIG. 3(a section taken along line B–B′ ofFIG. 1) andFIG. 4(a top plan view of about four memory cells). Incidentally,FIGS. 1 and 4show only connection holes for connecting the conductive layer constituting the memory cell and upper and lower conductive layers but omit the insulating films isolating the individual conductive layers.

The six MISFETs constituting the memory cell are formed in the active region which is surrounded by an element isolating groove2of a semiconductor substrate1made of single crystalline silicon. The drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2of n-channel type are formed in the active region of a p-type well3, and the load MISFETs Qp1and Qp2of p-channel type are formed in the active region of an n-type well4.

Each of the paired transfer MISFETs Qt1and Qt2include n-type semiconductor regions5and5(the source region and the drain region) formed in the active region of the p-type well3, a gate oxide film6formed on the surface of the active region, and a gate electrode7formed over the gate oxide film6. The individual gate electrodes7of the transfer MISFETs Qt1and Qt2are constructed so as to have a polycide structure, in which an n-type polycrystalline silicon film and a W (tungsten) silicide (WSi2) film are stacked, for example, and are integrated with the word line WL. This word line WL is extended in a first direction (in the lateral. direction ofFIGS. 1 and 4), and the paired transfer MISFETs Qt1and Qt2are arranged adjacent to each other in the first direction. The paired transfer MISFETs Qt1and Qt2are so arranged that their gate length direction is a second direction (the vertical direction ofFIGS. 1 and 4) perpendicular to the first direction.

Channel forming regions of the transfer MISFETs Qt1and Qt2are formed, in the active region of the p-type well3, under the gate electrodes7thereof and between n-type semiconductor regions5and5.

Each of the paired drive MISFETs Qd1and Qd2is composed of the n-type semiconductor regions5and5(the source region and the drain region) formed in the active region of the p-type well3, the gate oxide film6formed on the surface of the active region, and a gate electrode8formed over the gate oxide film6. The n-type semiconductor region5(the drain region) of the drive MISFET Qd1is formed in the active region shared with the n-type semiconductor region (one of the source region and the drain region) of the transfer MISFET Qd1, and the n-type semiconductor region5(the drain region) of the n-type semiconductor region5of the drive MISFET Qd2is formed in the active region shared with the n-type semiconductor region5(one of the source region and the drain region) of the transfer MISFET Qt2. The individual gate electrodes8of the drive MISFETs Qd1and Qd2are, illustratively, made to have a polycide structure in which an n-type polycrystalline silicon film and a silicide film are stacked, for example.

Channel forming regions of the driver MISFETs Qd1and Qd2are formed, in the active region of the p-type well3, under the gate electrodes8thereof and between the source region and the drain region thereof.

Each of the paired load MISFETs Qp1and Qp2is composed of p-type semiconductor regions9and9(the source region and the drain region) formed in the active region of the n-type well region4, the gate oxide film6formed on the surface of the active region, and the gate electrode8formed over the gate oxide film6. The gate electrode8of the load MISFET Qp1is integrated with the gate electrode8of the drive MISFET Qd1, and the gate electrode8of the load MISFET Qp2is integrated with the gate electrode8of the drive MISFET Qd2.

Channel forming regions of the load MISFETs Qp1and Qp2are formed, in the active region of the n-type well4, under the gate electrodes8thereof and between the source region and the drain region thereof.

The drive MISFET Qd1is arranged in the second direction between the load MISFET Qp1and the transfer MISFET Qt1, and the drive MISFET Qd2is arranged in the second direction between the load MISFET Qp1and the transfer MISFET Qt2. The paired drive MISFETs Qd1and Qd2and the paired load MISFETs Qp1and Qp2are so individually arranged that their gate length direction is the first direction.

On the surfaces of the individual n-type semiconductor regions5and5(the source regions and the drain regions) of the drive MISFETs Qd1and Qd2and the transfer MISFETs Qd1and Qt2, there are formed Ti (titanium) silicide (TiSi2) layers for reducing the sheet resistances of the n-type semiconductor regions5and5. Likewise, on the surfaces of the individual p-type semiconductor regions9and9(the source regions and the drain regions) of the load MISFETs Qp1and Qp2, there are formed the Ti-silicide layers for reducing the sheet resistances of the p-type semiconductor regions9and9.

Side wall spacers11of a silicon oxide film are formed on the individual side walls of the gate electrode7(the word line WL) of the transfer MISFETs Qd1and Qt2and the gate electrodes8of the drive MISFETs Qd1and Qd2(the load MISFETs Qp1and Qp2). A silicon oxide film (a cap insulating film)12is formed over the gate electrode7(the word line WL) and the gate electrode8.

Over the aforementioned six MISFETs, there is formed a silicon nitride film13, over which is formed one (i.e., the local wiring line L1) of the paired local wiring lines L1and L2. One end portion of this local wiring line L1is electrically connected through a connection hole14, which is opened in the silicon nitride film13and the silicon oxide film12, with the gate electrode8which is shared by the load MISFET Qp2and the drive MISFET Qd2. Another end portion of the local wiring line L1is electrically connected through a connection hole15, which is opened in the silicon nitride film13, with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1. Still another end portion of the local wiring line L1is electrically connected through a connection hole16, which is opened in the silicon nitride film13, with the p-type semiconductor region9(the drain region) of the load MISFET Qp1. In short, the local wiring line L1connects the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), the n-type semiconductor region5(the drain region) of the drive MISFET Qd1and the p-type semiconductor region9(the drain region) of the load MISFET Qp1with one another. The local wiring line L1is formed of a TiN (titanium nitride) film, for example. The local wiring line L1can be made of materials other than TiN, a refractory metal such as W or a refractory metal silicide such as a W-silicide.

The local wiring line L1is formed over the channel forming regions of the driver MISFETs Qd1and Qd2, of the load MISFETs Qp1and Qp2, and of the transfer MISFETs Qt1and Qt2.

Over the local wiring line L1, there is formed the other (the local wiring line L2) of the paired local wiring lines L1and L2through an interlayer insulating film17of a first layer which is formed of a silicon oxide insulating film of PSG (Phospho Silicate Glass). One end portion of the local wiring line L2is electrically connected through a connection hole18, which is opened in the silicon nitride film13and the silicon oxide film12, with the gate electrode8which is shared by the load MISFET Qp1and the drive MISFET Qd1. Another end portion of the local wiring line L2is electrically connected through a connection hole19, which is opened in the interlayer insulating film17and the silicon nitride film13, with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2. Still another end portion of the local wiring line L2is electrically connected through a connection hole20, which is opened in the interlayer insulating film17and the silicon nitride film13, with the p-type semiconductor region9(the drain region) of the load MISFET Qp2. In short, the local wiring line L2connects the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), the n-type semiconductor region5(the drain region) of the drive MISFET Qd2and the p-type semiconductor region9(the drain region) of the load MISFET Qp2electrically with one another. The local wiring line L2is composed of an Al (aluminum) film which is overlaid and underlaid with barrier metal layers of TiN, for example. In the connection holes18,19and20thus far described, moreover, there is buried plugs29which are composed of a W-film for ensuring the reliability of electrical connection between the local wiring line L2and the gate electrode8, and electrical connection between the n-type semiconductor region and the p-type semiconductor region9.

The local wiring line L2is formed over the channel forming regions of the driver MISFETs Qd1and Qd2, of the local MISFETs Qp1and Qp2, and of the transfer MISFETs Qt1and Qt2.

Over the local wiring line L2, there are formed, through an interlayer insulating film21of a second layer made of silicon oxide, a power supply voltage line22and a reference voltage line23. The power supply voltage line22is electrically connected through a connection hole24, which is opened in the interlayer insulating films21and17and the silicon nitride film13, with the individual p-type semiconductor regions9(the source-regions) of the load MISFETs Qp1and Qp2to supply these p-type semiconductor regions9with the power supply voltage (Vcc). The reference voltage line23is electrically connected through a connections hole25, which is opened in the interlayer insulating films21and17and the silicon nitride film13, with the individual n-type semiconductor regions (the source regions) of the drive MISFETs Qd1and Qd2to supply the n-type semiconductor regions with the reference voltage (Vss). The power supply voltage line22and the reference voltage line23are composed of an Al film which is overlaid and underlaid with barrier metal layers, for example. In the connection holes24and25, there are buried plugs37which are composed of a W-film, for example, for ensuring the reliability of electrical connection between the power supply voltage line22and the p-type semiconductor region9, and electrical connection between the reference voltage line23and the n-type semiconductor region5.

Over the power supply voltage line22and the reference voltage line23, there are formed, through an interlayer insulating film26of a third layer made of silicon oxide, the paired complementary data lines (the data line DL and the data line DL). One (the data line DL) of these complementary data lines is electrically connected through a connection hole27, which is opened in the interlayer insulating films26,21and17and the silicon nitride film13, with the n-type semiconductor region5(the other of the source region and the drain region) of the transfer MISFET Qt1. The other (the data line DL) of the complementary data lines is electrically connected through the connection hole27, which is opened in the interlayer insulating films26,21and17and the silicon nitride film13, with the n-type semiconductor region5(the other of the source region and the drain region) of the transfer MISFET Qt2. The data line DL and the data line DL are composed of Al films which are overlaid and underlaid with barrier metal layers of TiN. In the connection holes27and27, although not shown, there are buried plugs which are composed of W-films for ensuring the reliability of electrical connection between the data lines (DL and DL) and the n-type semiconductor region5.

Thus, in the SRAM of the present embodiment, the paired local wiring lines L1and L2cross-connecting the input/output terminals of the flip-flop circuit of the memory cell are formed in the different conductive layers. Thanks to this construction, the space, which is required for arranging the two local wiring lines transversely when the paired local wiring lines are formed in the same conductive layer, is not required, so that the local wiring lines L1and L2can be arranged partially in an overlapping manner, thereby reducing the area occupied by the memory cell.

A method for manufacturing the memory cell of the SRAM of the present embodiment will be described with reference toFIGS. 6 to 32. Of these showing the memory cell manufacturing method, sections (a) are taken along line A–A′ of the top plan views, and sections (b) are taken along line B–B′ of the top plan views. These individual top plan views show only the conductive layers and the connection holes but do not show the insulating films.

First of all, a groove30is formed in the periphery (element isolating region) of an active region AR of the major face of the semiconductor substrate1made of p-type single crystal silicon, as shown inFIGS. 6 and 7(a) and (b). This groove30is formed by depositing a silicon oxide film31and a silicon nitride film32consecutively over the semiconductor substrate1and then by dry-etching the silicon nitride32, the silicon oxide film31and the semiconductor substrate1consecutively by using a photoresist as the mask.

Next, a silicon oxide film36is buried in the groove30to form the element isolating groove2, as shown inFIGS. 8(a) and8(b). The element isolating groove2is formed by depositing the silicon oxide film36thickly over the semiconductor substrate1, including the inside of the groove30, by a CVD (Chemical Vapor Deposition) method and then by etching back (chemico-mechanical polishing (CMP)) the silicon oxide film36by using the silicon nitride film32as an etching stopper.

Next, the silicon nitride film32and the silicon oxide film31, left on the surface of the active region AR, are etched away. After this, as shown inFIGS. 9 and 10(a) and10(b), the semiconductor substrate1of the active region AR where the drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2are formed is doped with ions of p-type impurity (boron) to form the p-type well3, and the semiconductor substrate1of the active region AR where the load MISFETs Qp1and Qp2are formed is doped with ions of an n-type impurity (phosphorous or arsenic) to form the n-type well4. After this, the individual surfaces of the p-type well3and the n-type well4are thermally oxidized to form the gate oxide film6.

Next, an n-type polycrystalline silicon film33, a W-silicide film34and the silicon oxide film12are consecutively deposited over the semiconductor substrate1by a CVD method, as shown inFIG. 11(a) and (b). After this, the silicon oxide film12, the W-silicide film34and the n-type polycrystalline silicon film33are patterned by using a photoresist as the mask, as shown inFIGS. 12 and 13(a) and13(b), to form the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2and the gate electrodes8and8of the drive MISFETs Qd1and Qd2(the load-MISFITs Qp1and Qp2).

Next, as shown inFIGS. 14 and 15(a) and15(b), the p-type well3is doped with ions of n-type impurity (phosphorous or arsenic) to form the n-type semiconductor regions5and5(the source region and the drain region) of the transfer MISFETs Qt1and Qt2, and the drive MISFETs Qd1and Qd2, and the n-type well4is doped with the ions of p-type impurity (boron) to form the p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2. After this, the silicon oxide film, deposited over the semiconductor substrate1by a CVD method, is anisotropically etched to form the side wall spacers11on the individual side walls of the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2and the gate electrodes8and8of the drive MISFETs Qd1and Qd2.

Next, there are etched the gate oxide film covering the surfaces of the individual n-type semiconductor regions5and5(the source region and the drain region) of the drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2, and the gate oxide film6covering the surfaces of the p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2. After this, as shown inFIG. 16, a Ti-film35is deposited over the semiconductor substrate1by sputtering.

Next the semiconductor substrate1is annealed (thermally treated) to cause a reaction between the Ti-film35and the semiconductor substrate1(the n-type semiconductor region5and the p-type semiconductor region9). After this, the unreacted Ti-film35is etched to form the Ti-silicide layer10on the surfaces of the p-type semiconductor region5and the p-type semiconductor region9, as shown inFIGS. 17 and 18(a) and18(b). After this, the semiconductor substrate1is annealed, if necessary, to reduce the resistance of the Ti-silicide layer10. Instead of forming the Ti-silicide layer10, a Co (cobalt) film may be formed over the semiconductor substrate1by sputtering to cause a reaction between the semiconductor substrate1(the n-type semiconductor region5and the p-type semiconductor region9) and the Co film, thereby to form a Co-silicide layer.

Next, the silicon nitride film13, as thin as about 30 nm, is deposited over the semiconductor substrate1, as shown inFIGS. 19 and 20(a) and (b). After this, the connection hole14is opened in the silicon nitride film13and the silicon oxide film12over the gate electrodes8of the drive MISFET Qd2(or the load MISFET Qp2) by a dry-etching method using a photoresist as the mask. Simultaneously with this, the silicon nitride film13over the n-type semiconductor region5(the drain region) of the drive MISFET Qd1is etched off to form the connection hole15, and the silicon nitride film13over the p-type semiconductor region9(the drain region) of the load MISFET Qp1is etched to form the connection hole16. Next, the local wiring line L1is formed over the silicon nitride film13, as shown inFIGS. 21 and 22(a) and (b). The local wiring line L1is formed by patterning the TiN film, having a thickness of about 100 nm and deposited over the semiconductor substrate1by a sputtering method or a CVD method, by a dry-etching method using a photoresist as the mask. This local wiring line L1is connected through the connection hole14with the common gate electrode8of the load MISFET Qp2and the drive MISFET Qd2, through the connection hole15with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1, and through the connection hole16with the p-type semiconductor region9(the drain region) of the load MISFET Qp1.

Next, the interlayer insulating film17of PSG is deposited over the local wiring line L1by the CVD method, as shown inFIGS. 23 and 24(a) and (b). After this, the interlayer insulating film17, the silicon nitride film13and the silicon oxide film12lying over the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1) are opened to form the connection hole18by a dry-etching technique using a photoresist as the mask. Simultaneously with this, the interlayer insulating film17and the silicon nitride film13over the n-type semiconductor region5(the drain region) of the drive MISFET Qd2are etched to form the connection hole19, and the interlayer insulating film17and the silicon nitride film13over the p-type semiconductor region9(the drain region) of the load MISFET Qp2are etched to form the connection hole20.

Next, W-films are buried in the connection holes18,19and20to form the plugs29, as shown inFIGS. 25 and 26(a) and (b). After this, the local wiring line L2is formed over the interlayer insulating film17. The burying operation of the W-film is carried out by etching back the W-film which is deposited over the interlayer insulating film17by a sputtering method. The local wiring line L2is formed by depositing the TiN film, the Al film and the TiN film consecutively over the interlayer insulating film17by a sputtering method and then by patterning those films by a dry-etching method using a photoresist as the mask. The local wiring line L2is connected through the connection hole18with the common gate8of the load MISFET Qp1and the drive MISFET Qd1, through the connection hole19with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and through the connection hole20with the p-type semiconductor region9(the drain region) of the load MISFET Qp2.

Next, the interlayer insulating film21of silicon oxide is deposited over the local wiring line L1by a CVD method, as shown inFIGS. 27,28and29. After this, the interlayer insulating films21and17and the silicon nitride film13over the individual p-type semiconductor regions9and9(the source regions) of the load MISFETs Qp1and Qp2are opened to form the connection holes24and24by the dry-etching method, using a photoresist as the mask. Simultaneously with this, the interlayer insulating films21and17and the silicon nitride film13over the individual n-type semiconductor regions5and5(the source regions) of the drive MISFETs Qd1and Qd2are opened to form the connection holes25and25.

Next, W-films are buried in the connection holes24and25to form the plug37. After this, as shown inFIGS. 30,31and32, the power supply voltage line22and the reference voltage line23are formed over the interlayer insulating film21. These power supply and reference voltage lines22and23are formed by depositing a TiN film, an Al film and a TiN film consecutively over the interlayer insulating film21by a sputtering method, and then by patterning those films by a dry-etching method using a photoresist as the mask. The power supply voltage line22is connected through the connection holes24and24with the individual p-type semiconductor regions9and9(the source regions) of the load MISFETS Qp1and Qp2, and the reference voltage line23is connected through the connection holes25and25with the individual n-type semiconductor regions5and5(the source regions) of the drive MISFETS Qd1and Qd2.

After this, the interlayer insulating film26of silicon oxide is deposited over the power supply voltage line22and the reference voltage line23by a CVD method. After this, the interlayer insulating films26,21and17and the silicon nitride film13over the individual n-type semiconductor regions5and5(the drain regions) of the transfer MISFETs Qt1and Qt2are opened to form the connection holes27and27by a dry-etching method using a photoresist as the mask. Subsequently, W-films are buried in the connection holes27and27to form plugs, and the data lines DL and DL are then formed over the interlayer insulating film26. These data lines DL and DL-are formed by depositing a TiN film, an Al film and a TiN film consecutively over the interlayer insulating film26by a sputtering method, and then by patterning those films by a dry-etching method using a photoresist as the mask. The data line DL is connected through one of the connection holes27and27with the n-type semiconductor region5(the drain region) of the transfer MISFET Qt1, and the data line DL is connected through the other of the connection holes27and27with the n-type semiconductor region5(the drain region) of the transfer MISFET Qt2. The memory cell, as shown inFIGS. 1 to 4, is thus completed by the steps described.

FIG. 33is a top plan view showing a memory cell of an SRAM of the present embodiment;FIG. 34is a section taken along line A–A′ ofFIG. 33;FIG. 35is a section taken along line B–B′ ofFIG. 33; andFIG. 36is an equivalent circuit diagram showing the memory cell of the SRAM of the present embodiment.

In the SRAM of the present embodiment, as shown, the paired local wiring lines L1and L2cross-connecting the input/output terminals of the flip-flop circuit of the memory cell are formed in different conductive layers, as in the SRAM of the foregoing embodiment 1. In the SRAM of the present embodiment, moreover, the upper local wiring line L2overlaps with the lower local wiring line L1over a wide area, and a capacitor element C is composed of the local wiring lines L1and L2and a thin insulating film (a silicon nitride film42) interposed between the wiring lines. Specifically, the upper local wiring line L2is one electrode of the capacitor element C, the lower local wiring line L1is the other electrode, and the insulating film (the silicon nitride film42) is its dielectric film.

A method for manufacturing the memory cell of the SRAM of the present embodiment will be described with reference toFIGS. 37,38(a) and (b),39,40(a) and (b),41,42(a) and (b),43,44(a) and (b)45,46(a) and (b),47and48(a) and (b). Of the individual Figures showing the memory cell manufacturing method, sections (a) are taken along line A–A′ of the top plan views, and sections (b) are taken along line B–B′ of the top plan views. Moreover, the individual top plan views show only the conductive layers and the connection holes but do not show the insulating films.

First of all, in accordance with the manufacturing method of the foregoing embodiment 1, as shown inFIGS. 6et seq., up to and includingFIGS. 18(a) and (b), an element isolating groove2, a p-type well3, an n-type well4and a gate oxide film6are formed over a major face of the semiconductor substrate1. After this, drive MISFETs Qd1and Qd2and transfer MISFETs Qt1and Qt2are formed in a p-type well3, and load MISFETs Qp1and Qp2are formed in an n-type well4. Moreover, a Ti-silicide layer10is formed so as to reduce the sheet resistance over the surfaces of n-type semiconductor regions5and5(the source region and the drain region) of the transfer MISFETs Qd1and Qt2and the drive MISFETs Qd1and Qd2and over the surfaces of p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2.

Next, as shown inFIGS. 37 and 38(a) and (b), a silicon nitride film13, as thick as about 50 nm, is deposited over the semiconductor substrate1. After this, the silicon nitride film13and a silicon oxide film12over a gate electrode8of the drive MISFET Qd2(or the load MISFET Qp2) are opened to form a connection hole14by a dry-etching method using a photoresist as the mask. Simultaneously with this, the silicon nitride film13over the n-type semiconductor region5(the drain region) of the drive MISFET Qd1is etched to form a connection hole40, and the silicon nitride film13over the p-type semiconductor region9(the drain region) of the load MISFET Qp1is etched to form a connection hole41.

Next, as shown inFIGS. 39 and 40(a) and (b), a local wiring line L1is formed over the silicon nitride film13. This local wiring line L1is formed by patterning a TiN film, having a thickness of about 100 nm and deposited over the silicon nitride film13by a sputtering method or a CVD method, by a dry-etching method using a photoresist as the mask. The local wiring line L1is given an area wide enough to cover the six MISFETs constituting the memory cell. Specifically, the local wiring line L1is so arranged as to cover the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), the gate electrode7(the word line W1) of the transfer MISFETs Qt1and Qt2, the common n-type semiconductor region (one of the source region and the drain region) of the transfer MISFETs Qt1and Qt2and the drive MISFETs Qd1and Qd2, and the p-type semiconductor region9(the drain region) of the load MISFETs Qp1and Qp2.

The local wiring line L1is connected through the connection hole14with the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), through the connection hole40with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1, and through the connection hole41with the p-type semiconductor region9(the drain region) of the load MISFET Qp1.

Next, as shown inFIGS. 41 and 42(a) and (b), a silicon nitride film42having a thickness of about 30 nm is deposited over the local wiring line L1. After this, the silicon nitride films17and13and the silicon oxide film12over the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1) are opened to form a connection hole18by a dry-etching method using a photoresist as the mask. Simultaneously with this, the silicon nitride films17and13over the n-type semiconductor region5(the drain region) of the drive MISFET Qd2are etched to form the connection hole19, and the silicon nitride films17and13over the p-type semiconductor region9(the drain region) of the load MISFET Qp2are etched to form a connection hole20.

Next, as shown inFIGS. 43 and 44(a) and (b), a local wiring line L2is formed over the silicon nitride film42. This local wiring line L2is formed by patterning the TiN film, which is so deposited as to have a thickness of about 100 nm by a sputtering method or a CVD method, by a dry-etching method using a photoresist as the mask. The local wiring line L2can be made of not only TiN but also a refractory metal such as W or a refractory metal silicide such as W-silicide. The local wiring line L2is connected through the connection hole18with the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), through the connection hole19with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and through the connection hole20with the p-type semiconductor region9(the drain region) of the load MISFET Qp1.

The local wiring line L2is so formed over the lower local wiring line L1as to have an area wide enough to cover the six MISFETs constituting the memory cell and is substantially completely superposed on the local wiring line L1in the region excepting the open regions of the connection holes18,19and20and their registration allowance region. As a result, the capacitor element C can be composed of both the local wiring lines L1and L2and the silicon nitride film42(the dielectric film) interposed therebetween and made thinner than the local wiring lines L1and L2, and can be given a large capacitance, so that the amount of stored charge of the storage node can be increased to improve the alpha particle soft error resistance of the memory cell. If, moreover, the thin insulating film, interposed between the local wiring lines L1and L2, is made of a highly dielectric material such as tantalum pentoxide (Ta2O5), the amount of stored charge of the storage node can be further increased.

Next, as shown inFIGS. 45 and 46(a) and (b), an interlayer insulating film21made of silicon oxide is deposited over the local wiring line L2by a CVD method. After this, the interlayer insulating film21and the silicon nitride films17and13over the individual p-type semiconductor regions9and9(the source regions) of the load MISFETs Qp1and Qp2are opened to form connection holes24and24by a dry-etching method using a photoresist as the mask. Simultaneously with this, the interlayer insulating film21and the silicon nitride films17and13over the individual n-type semiconductor regions5and5(the source regions) of the drive MISFETs Qd1and Qd2are opened to form connection holes25and25.

Next, as shown inFIGS. 47 and 48(a) and (b), W-films are buried in the connection holes24and25to form plugs29, and power supply voltage line22and reference voltage line23are then formed over the interlayer insulating film21. These power supply and reference voltage lines22and23are formed by depositing a TiN film, an Al film and a TiN film consecutively over the interlayer insulating film21by a sputtering method, and then by patterning those films.

After this, an interlayer insulating film26of silicon oxide is deposited over the power supply voltage line22and the reference voltage line23by a CVD method. After this, the interlayer insulating films26and21and the silicon nitride films17and13over the individual n-type semiconductor regions5and5(the drain regions) of the transfer MISFETs Qt2and Qt2are opened to form connection holes27and27by a dry-etching method using a photoresist as the mask. Subsequently, W-films are buried in the connection holes27and27to form plugs, and the data lines DL and DL are then formed over the interlayer insulating film26. These data lines DL and DL are formed by depositing a TiN film, an Al film and a TiN film consecutively over the interlayer insulating film26by a sputtering method and then by patterning those films. The memory cell, as shown inFIGS. 33 to 35, is thus completed by the steps described.

In the SRAM of the present embodiment, the paired local wiring lines L1and L2cross-connecting the input/output terminals of the flip-flop circuit of the memory cell are formed in the same conductive layer. The method for manufacturing the memory cell of this SRAM will be described with reference toFIGS. 49 to 64. Of the individual Figures showing the memory cell manufacturing method, sections are taken along line C–C′ of the top plan views. Moreover, the individual top plan views show only the conductive layers and the connection holes but do not show the insulating films.

First of all, as shown inFIGS. 49 and 50, a p-type well3and a n-type well4are formed over the principal face of a semiconductor substrate1, and an element isolating field oxide film28and a gate oxide film6of a MISFET are then formed over those surfaces. After this, drive MISFETs Qd1and Qd2and transfer MISFETs Qt1and Qt2are formed in the p-type well3, and load MISFETs Qp1and Qp2are formed in the n-type well4. A gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2and gate electrodes8and8of the drive MISFETs Qd1and Qd2(the load MISFETs Qp1and Qp2) are formed of a polycrystalline silicon film having a thickness of about 300 nm. Side wall spacers on the individual side walls of the gate electrode7(the word line WL) and the gate electrode8are formed by etching a silicon oxide film.

Next, as shown inFIGS. 51 and 52, in order to reduce the sheet resistance, a Ti-silicide layer10is formed on the individual surfaces of the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2, the gate electrodes8and8of the drive MISFETs Qd1and Qd2(the load MISFETs Qp1and Qp2), individual n-type semiconductor regions5and5(the source region and the drain region) of the transfer MISFETs Qt1and Qt2and the drive MISFETs Qd1and Qt2, and individual p-type semiconductor regions9and9of the load MISFETS Qp1and Qp2.

In order to form the Ti-silicide layer10, a silicon oxide film12covering the individual surfaces of the gate electrode7(the word line WL) and the gate electrode8, a gate oxide film6covering the surfaces of the individual n-type semiconductor regions5and5(the source region and the drain region) of the drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2, and a gate oxide film6covering the surfaces of the individual p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2are etched. After this, a Ti-film is deposited over the semiconductor substrate1by sputtering. Next, the semiconductor substrate1is annealed to cause reactions individually between the Ti-film and the semiconductor substrate1(the n-type semiconductor region5and the p-type semiconductor region9) and between the Ti-film and the polycrystalline silicon film (the gate electrodes7and8), and the unreacted Ti-film is then etched away.

Next, as shown inFIGS. 53 and 54, a silicon nitride film13, as thin as about 30 nm, is deposited over the semiconductor substrate1by a CVD method. After this, the silicon nitride film13is dry-etched by using a photoresist as the mask to form a connection hole43, which reaches the n-type semiconductor region5(the drain region) of the drive MISFET Qd1and the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), and a connection hole44which reaches the p-type semiconductor region9(the drain region) of the load MISFET Q2and the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1). Simultaneously with this, a connection hole45is formed over the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and a connection hole46is formed over the p-type semiconductor region9(the drain region) of the load MISFET Qp1. At this time, the surface of a field oxide film28is covered with the silicon nitride film13, so that it is not removed by the dry-etching treatment.

Next, as shown inFIGS. 55 and 56, the paired local wiring lines L1and L2, composed of a TiN film, are formed over the silicon nitride film13. For forming these local wiring lines L1and L2, a TiN film having a thickness of about 50 to 100 nm is deposited over the silicon nitride film13by a sputtering method or a CVD method. Next, a silicon nitride film47having a thickness of about 100 nm is deposited over the TiN film by a CVD method. After this, the silicon nitride film47and the TiN film are patterned by a dry-etching method using a photoresist as the mask. The local wiring lines L1and L2can be made of not only TiN but also a refractory metal such as W or a refractory metal silicide such as a W-silicide.

The local wiring line L1is so arranged as to overlap with the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1) and the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2, and the local wiring line L2is so arranged as to overlap with the gate electrode8of the drive MISFIT Qd2(the load MISFET Qp2) and the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2. Thanks to this construction, a capacitor element C′ is composed of the local wiring line L1, the gate electrode8and the thin silicon nitride film13interposed therebetween, and a capacitor element C′ is formed of the local wiring line L2, the gate electrode8and the silicon nitride film13interposed therebetween, so that the charge storage capacity of the storage node can be increased to improve the alpha particle soft error resistance of the memory cell. These capacitor elements C′ act effectively similarly to those of the capacitor element C of the foregoing embodiment 2 (ofFIG. 36).

The local wiring line L1is connected through the connection hole43with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1and the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), and through the connection hole46with the p-type semiconductor region9(the drain region) of the load MISFET Qp1. In other words, the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), the n-type semiconductor region5(the drain region) of the drive MISFET Qd1, and the p-type semiconductor region9(the drain region) of the load MISFET Qp1are connected with one another through the local wiring line L1.

The local wiring line L2is connected through the connection hole44with the p-type semiconductor region9(the drain region) of the load MISFET Qp2and the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), and through the connection hole45with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2. In other words, the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and the p-type semiconductor region9(the drain region) of the load MISFET Qp2are connected with one another through the local wiring line L2.

Next, as shown inFIG. 57, a silicon nitride film53having a thickness of about 200 nm is deposited over the silicon nitride film47by a CVD method. After this, as shown inFIG. 58, this silicon nitride film53is anisottopically etched by a RIE (Reactive Ion Etching) method to form side wall spacers48on the individual side walls of the gate electrode7(the word line WL), the gate electrode8and the local wiring lines L1and L2.

Next, as shown inFIGS. 59 and 60, an interlayer insulating film49of a silicon oxide, such as PSG, of an etching rate different from that of the silicon nitride films47and53(the side wall spacer48) is deposited by a CVD method over the silicon nitride film47and the side wall spacers48. The etching rate of the material of insulating film49is greater than that of the silicon nitride of films47and53(side wall spacer48), for example. After this, the interlayer insulating film49over the individual p-type semiconductor regions9and9(the source regions) of the load MISFETs Qp1and Qp2are opened to form connection holes50and50by a dry-etching method using a photoresist as the mask. Simultaneously with this, the interlayer insulating film49over the individual n-type semiconductor regions and (the source regions) of the drive MISFETs Qd1and Qd2is opened to form connection holes51and51, and the interlayer insulating film49over the individual n-type semiconductor regions5and5(the other of the source region and the drain region) of the transfer MISFETs Qt1and Qt2is opened to form connection holes52and52.

At the aforementioned step of forming the connection holes50,51and52by etching the interlayer insulating film49of PSG, due to the silicon nitride film47formed over the local wiring lines L1and L2, and the side wall spacers of silicon nitride formed on the individual side walls of the gate electrode7(the word line WL), the gate electrode8and the local wiring lines L1and L2are hardly etched because their etching rates are different from (e.g., much less than) that of the material of the interlayer insulating film49.

The connection holes50,51and52and the local wiring lines L1and L2can be positionally displaced due to the misregistration of the photoresist mask used for forming the connection holes50,51and52by etching the interlayer insulating film49and the photoresist mask used for forming the local wiring lines L1and L2by etching the TiN film. However, in the present embodiment, even with a partial overlap between any of the connection holes50,51and52and the local wiring line L1or the local wiring line L2, neither the local wiring line L1nor the local wiring line L2is exposed from the side wall of any of the connection holes50,51and52when the interlayer insulating film49is etched, thereby preventing short circuit between the conductive film to be deposited at a later step in the connection holes50,51and52and the local wiring line L1or the local wiring line L2.

The connection holes50,51and52, the gate electrode7(the word line WL) and the gate electrode8can be relatively displaced due to misregistration between the photoresist mask to be used for forming the connection holes50,51and52by etching the interlayer insulating film49and the photoresist mask to be used for forming the gate electrode (the word line WL) and the gate electrode8by etching the polycrystalline silicon film. However, in the present embodiment, even with a partial overlap between any of the connection holes50,51and52and the gate electrode7(the word line WL) or the gate electrode8, the gate electrode8is not exposed from the side wall of the connection hole50or51, and the gate electrode7(the word line WL) is not exposed from the side wall of the connection hole52when the interlayer insulating film49is etched, thereby preventing short circuit between the conductive film to be deposited at a later step in the connection holes50,51and52and the gate electrode7(the word line WL) or the gate electrode8.

In short, according to the manufacturing method of the present embodiment, when the connection holes50,51and52are laid out, it is unnecessary to take into consideration the registration allowance between the connection holes50,51and52and the local wiring lines L1and L2and the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8. As a result, the connection holes5,51and52can be laid out so as to be closer to the local wiring lines L1and L2, the gate electrode7(the word line WL) and the gate electrode8by a distance corresponding to those registration allowances. Therefore, the area occupied by the memory cell can be reduced in both the first direction and the second direction perpendicular to the first direction.

In order that the side wall spacer48may function as the etching stopper when the interlayer insulating film49is etched, the thickness of the silicon nitride film53constituting the side wall spacer48has to be larger than the registration allowance of the photoresist mask. The thickness of the silicon nitride film53is set to at least about 200 nm when the sum of (1) the registration allowance between the connection holes50,51and52and the local wiring lines L1and L2, and (2) the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8, is about 200 nm, for example.

Next, the thin silicon nitride film13at the bottoms of the connection holes50,51and52is etched. After this, as shown inFIG. 61 and 62, power supply voltage line22, reference voltage line23and an intermediate wiring line54are formed over the interlayer insulating film49. The power supply voltage line, reference voltage line and intermediate wiring line22,23and54are formed by depositing a W-film, an Al film and a W-film consecutively over the interlayer insulating film49by a sputtering method, and then by patterning those films. Plugs of W-film may be formed, if necessary, in the connection holes50,51and52.

Next, as shown inFIGS. 63 and 64, an interlayer insulating film26of silicon oxide is deposited by a CVD method over the power supply voltage line22, the reference voltage line23and the intermediate wiring line54, and the interlayer insulating film26over the intermediate wiring line54is opened to form a connection hole55by a dry-etching method using a photoresist as the mask. After this, the data lines DL and DL are formed over the interlayer insulating film26. These data lines DL and DL are formed by depositing a TiN film, an Al film and a TiN film consecutively over the interlayer insulating film26by sputtering and then by patterning those films.

In the SRAM of the present embodiment, the paired local wiring lines L1and L2are formed in the same conductive layer as in the SRAM of the foregoing embodiment 3. A method for manufacturing the memory cell of this SRAM will be described with reference toFIGS. 65 to 82.

First of all, as shown inFIGS. 65 and 66, a p-type well3and an n-type well4are formed in the major face of a semiconductor substrate1, and a field oxide film28for isolating the elements and a gate oxide film6of an MISFET are then formed on those surfaces. After this, drive MISFETs Qd1and Qd2and transfer MISFETs Qd1and Qt2are formed in the p-type well3, and load MISFETs Qp1and Qp2are formed in the n-type well4. A gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2and gate electrodes8and8of the drive MISFETs Qd1and Qd2(the load MISFETs Qp1and Qp2) are composed of a polycrystalline silicon film. The insulating films (the cap insulating films) covering the gate electrode7(the word line WL) and the gate electrode8individually are composed of a silicon nitride film56. This silicon nitride film56is deposited thicker (the thickness is more than about 300 nm) than a later described silicon nitride film13. Side wall spacers11on the individual side walls of the gate electrode7(the word line WL) and gate electrode8are formed by etching a silicon oxide film anisottopically.

Next, as shown inFIGS. 67 and 68, the silicon nitride film56over the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1) is etched to form a connection hole57, and the silicon nitride film56over the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2) is etched to form a connection hole58. The connection hole57is formed in the region to be connected with the local wiring line L2at a later step, and the connection hole58is formed in the region to be connected with the local wiring line L1at a later step.

Next, as shown inFIGS. 69 and 70, a Ti-silicide layer is formed on the individual surfaces of the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), exposed at the bottom of the connection hole57, the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), exposed at the bottom of the connection hole58, n-type semiconductor regions5and5(the source region and the drain region) of the transfer MISFETs Qt1and Qt2, the n-type semiconductor regions5and5(the source region and the drain region) of the drive MISFETs Qd1and Qd2, and p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2.

In order to form the Ti-silicide layer10, the gate oxide film6, covering the surfaces of the individual n-type semiconductor regions5and5(the source region and the drain region) of the drive MISFETs Qd1and Qd2and transfer MISFETs Qt1and Qt2, and the gate oxide film6, covering the surface of the individual p-type semiconductor regions5and5(the source region and the drain region) of the load MISFETs Qp1and Qp2, are etched. After this, a Ti-film is deposited over the semiconductor substrate1by sputtering. Next, the semiconductor substrate1is annealed to cause reactions between the Ti-film and the semiconductor substrate1(the n-type semiconductor region5and the p-type semiconductor region9) and between the Ti-film and the polycrystalline silicon film (the gate electrode8exposed at the bottoms of the connection holes57and58), and the unreacted Ti-film is etched off.

Next, as shown inFIGS. 71 and 72, the silicon nitride film13, as thin as about 30 nm, is deposited over the semiconductor substrate1by a CVD method. After this, the silicon nitride film13is dry-etched by using a photoresist as the mask to form a connection hole43, which reaches the n-type semiconductor region5(the drain region) of the drive MISFET Qd1and the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), and a connection hole44which reaches the p-type semiconductor region9(the drain region) of the load MISFET Qp2and the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1). Simultaneously with this, a connection hole45is formed over the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and a connection hole46is formed over the p-type semiconductor region9(the drain region) of the load MISFET Qp1.

Since a connection hole58is formed in advance over the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), the connection hole43partially overlaps the connection hole58over the gate electrode8. Likewise, since a connection hole57is formed in advance over the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), the connection hole44partially overlaps the connection hole57over the gate electrode8.

In short, by the manufacturing method of the present embodiment, when the connection holes43,44,45and46are laid out, it is unnecessary to consider the registration allowance between those connection holes43to46and the gate electrode8and the registration allowance between the connection holes43to46and the connection holes57and58. As a result, the connection holes43to46can be laid out so as to be closer to the gate electrode8by a distance corresponding to those registration allowances. Therefore the area occupied by the memory cell in the first direction can be reduced.

Specifically, even if the connection holes43,44,45and46overlap the gate electrode8when they are formed by etching the silicon nitride film13, they do not reach the gate electrode8because the silicon nitride film56, thicker than the silicon nitride film13, is formed over the gate electrode8. Since, moreover, there is a large difference in the etching rate between the silicon nitride film and the silicon oxide film, the side wall spacers11, which are composed of the silicon oxide film on the individual side walls of the gate electrode7(or the word line WL) and the gate electrode8, are hardly etched when the silicon nitride film13is etched to form the connection holes43,44,45and46.

As a result, even if those connection holes43to46overlap the gate electrode8when they are formed, the conductive film deposited in the connection holes43to46and the gate electrode8do not short circuit at a later step.

Next, as shown inFIGS. 73 and 74, a TiN film having a thickness of about 100 nm is deposited over the silicon nitride film13by a sputtering method or a CVD method, and a silicon nitride film47having a thickness of about 100 nm is then deposited over that TiN film by a CVD method. After this, the silicon nitride film47and the TiN film are patterned by a dry-etching method using a photoresist as the mask to form paired local wiring lines L1and L2composed of the TiN film.

The local wiring line L1is connected through the connection hole43and the connection hole58with the gate electrode8of the drive MISFET. Qd2(the load MISFET Qp2), through the connection hole43with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1, and through the connection hole46with the p-type semiconductor region9(the drain region) of the load MISFET Qp1. The local wiring line L2is connected through the connection hole44and the connection hole57with the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), through the connection hole44with the p-type semiconductor region9(the drain region) of the load MISFET Qp2, and through the connection hole45with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2.

The local wiring line L1is so arranged as to overlap with the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1) and the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2, and the local wiring line L2is so arranged as to overlap with the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2) and the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2. Thanks to this construction, a capacitor element C′ is formed of the local wiring line L1, the gate electrode8and the silicon nitride film13interposed therebetween, and a capacitor element C′ is formed of the local wiring line L2, the gate electrode8and the silicon nitride film13interposed therebetween, so that the amount of charge of the storage node can be increased to improve the alpha particle soft error resistance of the memory cell.

Next, as shown inFIG. 75, a silicon nitride film59is deposited by a CVD method over the silicon nitride film47covering the local wiring lines L1and L2, and an interlayer insulating film49of PSG is deposited over the silicon nitride film59by the CVD method.

Next, as shown inFIG. 76 and 77, the interlayer insulating film49over the individual p-type semiconductor regions9and9(the source regions) of the load MISFETs Qp1and Qp2are opened by a dry etching method using a photoresist as the mask to form connection holes50and50. Simultaneously with this, the interlayer insulating film49over the individual n-type semiconductor regions5and5(the source regions) of the drive MISFETs Qd1and Qd2are opened to form connection holes51and51, and the interlayer insulating film49over the individual n-type semiconductor regions5and5(the drain regions) of the transfer MISFETs Qd1and Qt2are opened to form connection holes52and52. This etching treatment is interrupted at the instant when the silicon nitride film59is exposed at the bottoms of the connection holes50,51and52.

Next, the etching gas for the silicon oxide is changed to that for the silicon nitride, to etch the silicon nitride film59in the connection holes50,51and52and the thin silicon nitride film13below the former, as shown inFIG. 78. This etching treatment is carried out in the connection holes50,51and52under the condition that the side wall spacers are formed on the individual side walls of the gate electrode7(the word line WL), the gate electrode8and the local wiring lines L1and L2.

Thus, in the foregoing embodiment 3, the connection holes50,51and52are formed in the interlayer insulating film49after the side wall spacers48have been formed in advance on the individual side walls of the gate electrode7(the word line WL), the gate electrode8and the local wiring lines L1and L2. In the present embodiment, on the contrary, the side wall spacers of silicon nitride are formed when the connection holes50,51and52are formed by opening the interlayer insulating film49.

In this embodiment, like embodiment 3, the gate electrode7(the word line WL), the gate electrode8and the local wiring lines L1and L2are not exposed on the side walls of the connection holes50,51and52even if the connection holes50,51and52, the gate electrode7(the word line WL), and the gate electrode8overlap with each other and the connection holes50,51, and52and the local wiring lines overlap each other due to the misregistration of the photoresist mask. In short, in the case the manufacturing method of the present embodiment is used, when the connection holes50,51and52are laid out, it is unnecessary to take into consideration the registration allowance between the connection holes50,51and52and the local wiring lines L1and L2and the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8. As a result, the connection holes50,51and52can be laid out so as to be closer to the local wiring lines L1and L2, the gate electrode7(the word line WL) and the gate electrode8by a distance corresponding to those registration allowances so that the area to be occupied by the memory cell can be reduced.

In order that the side wall spacers formed by the silicon nitride film59may function as the etching stopper, the thickness of the silicon nitride film59is made larger than the registration allowance of the aforementioned photoresist mask.

Next, as shown inFIGS. 79 and 80, the power supply voltage line22, the reference voltage line23and the intermediate wiring line54are formed over the interlayer insulating film49in accordance with the manufacturing method of the aforementioned embodiment 3. Next, as shown inFIGS. 81 and 82, the interlayer insulating film26is deposited over the power supply voltage line22, the reference voltage line23and the intermediate wiring line54, and the interlayer insulating film26over the intermediate wiring line54is opened to form the connection hole55by a dry-etching method using a photoresist as the mask. After this, the data lines DL and DL are5formed over the interlayer insulating film26.

According to the manufacturing method of the present embodiment, there are required neither the registration allowance between the connection holes50,51and52and the local wiring lines L1and L2nor the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8, and further neither the registration allowance between the connection holes43and44and the gate electrode8nor the registration allowance between the connection hole43and the n-type semiconductor region5(between the connection hole44and the p-type semiconductor region9). As a result, the memory cell can be made smaller than that of the foregoing embodiment 3.

In the SRAM of the present embodiment, the paired local wiring lines L1and L2are formed in different conductive layers, so that a capacitor element C is formed of the upper local wiring line L2, the lower local wiring line L1and a thin insulating film interposed therebetween. The method for manufacturing the memory cell of this SRAM will be described with reference toFIGS. 83,84(a) and (b),85,86(a) and (b),87,88(a) and (b),89,90(a) and (b),91(a) and (b),92,93(a) and (b),94,95(a) and (b),96and97(a) and (b).

First of all, as shown inFIGS. 83 and 84(a) and (b), in accordance with the manufacturing method of the foregoing embodiment 1, the element isolating groove2and then the p-type well3and the n-type well4are formed in a major face of the semiconductor substrate1, and the gate oxide film6of the MISFET is formed over the p-type well3and the n-type well4. After this, the drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2are formed in the p-type well3, and the load MISFETs Qp1and Qp2are formed in the n-type well4. The gate electrode7(the word line WL) and the gate electrode8are composed of a polycrystalline silicon film, and the cap insulating film is composed of the silicon oxide film12. The side wall spacers11on the individual side walls of the gate electrode7(the word line WL) and the gate electrode8are formed by etching a silicon oxide film.

Next, as shown inFIGS. 85 and 86(a) and (b), in accordance with the manufacturing method of the foregoing embodiment 3, the Ti-silicide layer10is formed to reduce the sheet resistance over the individual surfaces of the gate electrode7(the word line WL) of the transfer MISFETs Qt1and Qt2, the gate electrode8and8of the drive MISFETs Qd1and Qd2(the load MISFETs Qp1and Qp2), the individual n-type semiconductor regions5and5(the source region and the drain region) of the transfer MISFETs Qd1and Qt2and the drive MISFETs Qd1and Qd2, the individual p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2.

Next, as shown inFIGS. 87 and 88(a) and (b), the silicon nitride film13, deposited over the semiconductor substrate by a CVD method and having a small thickness of about 50 nm, is etched to form the connection hole14over the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), the connection hole40over the n-type semiconductor region5(the drain region) of the drive MISFET Qd1and the connection hole41over the p-type semiconductor region9(the drain region) of the load MISFET Qp1. After this, the TiN film, deposited over the silicon nitride film13by a sputtering method or a CVD method and having a thickness of about 100 nm, is patterned to form the local wiring line L1. This local wiring line L1is given an area wide enough to cover the six MISFETs constituting the memory cell. The local wiring line L1is connected through the connection hole14with the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), through the connection hole40with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1, and through the connection hole41with the p-type semiconductor region9(the drain region) of the load MISFET Qp1.

Next, as shown inFIGS. 89 and 90(a) and (b), the silicon nitride film42, deposited over the semiconductor substrate1by a CVD method and having a small thickness of about 30 nm, is etched to form the connection hole18over the gate electrode8of the drive MISFET Qd1(or the load MISFET Qp1), the connection hole19over the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and the connection hole20over the p-type semiconductor region9(the drain region) of the load MISFET Qp2. After this the local wiring line L2of a TiN film is formed over the silicon nitride film42. The local wiring line L2is connected through the connection hole18with the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), through the connection hole19with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and through the connection hole20with the p-type semiconductor region9(the drain region) of the load MISFET Qp2.

The local wiring line L2is formed by depositing a TiN film having a thickness of about 100 nm over the silicon nitride film42by a sputtering method or a CVD method, by then depositing the silicon nitride film47having a thickness of about 100 nm over the TiN film by a CVD method, and thereafter by patterning the silicon nitride film47and the TiN film by a dry etching method using a photoresist as the mask. The local wiring line L2is given an area wide enough to cover the six MISFETs constituting the memory cell and to overlap the lower local wiring line L1substantially completely in the region excepting the open regions of the connection holes18,19and20and the registration allowance region. As a result, the capacitor element C is formed of the local wiring lines L1and L2(the paired electrodes) and the silicon nitride film42(the dielectric film) made thinner than the local wiring lines L1and L2. Moreover, the charge of the capacitor element C can be increased so that the amount of stored charge of the storage node can be increased to improve the alpha particle soft error resistance of the memory cell.

Next, as shown inFIG. 91(a) and (b), the side wall spacers48are formed on the individual side walls of the gate electrode8, the lower local wiring line L1and the upper local wiring line L2. The side wall spacer48is also formed on the side wall of the gate electrode7(the word line WL), although not shown. The side wall spacers48are formed by etching a silicon nitride film which is deposited over the silicon nitride film47by a CVD method and has a thickness of about 200 nm.

Next, as shown inFIGS. 92 and 93(a) and (b), the interlayer insulating film49of PSG having a thickness of about 400 nm is deposited over the silicon nitride film47by a CVD method. After this, the interlayer insulating film49is opened by a dry-etching method using a photoresist as the mask to form the connection holes50and50over the p-type semiconductor regions9and9(the source regions) of the load MISFETs Qp1and Qp2, the connection holes51and51over the n-type semiconductor region5and5(the source regions) of the drive MISFETs Qd1and Qd2, and the connection holes52and52over the n-type semiconductor regions5and5(the drain regions) of the transfer MISFETs Qt1and Qt2. Since, at this time, the side wall spacers48on the silicon nitride film act as the etching stoppers, neither the gate electrode8is exposed at the side walls of the connection holes50and51, nor is exposed the gate electrode7(the word line WL) at the side wall of the connection hole52. Likewise, neither the lower local wiring line L1nor the upper local wiring line L2is exposed at the side walls of the connection holes50,51and52.

In short, when the manufacturing method of the present embodiment is applied to the SRAM in which the paired local wiring lines L1and L2are arranged in the different conductive layers, it is unnecessary to take into consideration the registration allowance between the connection holes50,51and52and the upper local wiring line L2, and the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8. As a result, the connection holes50,51and52can be so arranged as to be closer to the upper local wiring line L2, the lower local wiring line L1, the gate electrode7(word line WL) and the gate electrode8by a distance corresponding to those registration allowances so that the area occupied by the memory cell can be reduced. In order that the side wall spacers48may function as the etching stoppers when the interlayer insulating film49is etched, the thickness of the silicon nitride film constituting the side wall spacers48is made larger than the registration allowance of the aforementioned photoresist mask.

In the present embodiment, the side wall spacers48of the silicon nitride are formed in advance on the individual side walls of the gate electrode7(the word line WL), the gate electrode8, the lower local wiring line L1and the upper local wiring line L2, and the connection holes50,51and52are then formed in the interlayer insulating film49. As in the foregoing embodiment 4, the silicon nitride film and the interlayer insulating film49are deposited over the silicon nitride film47covering the upper local wiring line L2so that the side wall spacers may be formed when the interlayer insulating film49is opened to form the connection holes50,51and52.

Next, as shown inFIGS. 94 and 95(a) and (b), in accordance with the manufacturing method of the foregoing embodiment 3, the power supply voltage line22, the reference voltage line23and the intermediate wiring line54are formed over the interlayer insulating film49. After this, as shown inFIGS. 96 and 97(a) and (b), the interlayer insulating film26is deposited over the power supply voltage line22, the reference voltage line23and the intermediate wiring line54, and the interlayer insulating film26ever the intermediate wiring line54is opened to form the connection hole55. After this, the data lines DL and DL are formed over the interlayer insulating film26.

According to the present embodiment, the paired local wiring lines L1and L2are formed in different conductive layers and are so arranged as to be superposed on each other so that the area occupied by the memory cell can be reduced. At the same time, there are made unnecessary the registration allowance between the connection holes50,51and52and the upper local wiring line L2, the registration allowance between the connection holes50,51and52and the lower local wiring line L1, and the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8, so that the area occupied by the memory cell can be further reduced.

According to the present embodiment, the upper local wiring line L2and the lower local wiring line L1are so arranged as to overlap with each other over a wide area, and the capacitor element C is composed of the local wiring lines L1and L2and the thin insulating film interposed therebetween, so that the alpha particle soft error resistance of the memory cell can be improved.

In the SRAM of the present embodiment, the paired local wiring lines L1and L2are formed in different conductive layers, so that a capacitor element C is formed of the upper local wiring line L2, the lower local wiring line L1and a thin insulating film interposed therebetween. The method for manufacturing the memory cell of this SRAM will be described with reference toFIGS. 98,99(a) and (b),100,101(a) and (b),102,103(a) and (b),104,105(a) and (b),106(a) and (b),107(a) and (b),108and109.

First of all, as shown inFIGS. 98 and 99(a) and (b), in accordance with the manufacturing method of the foregoing embodiment 1, the element isolating groove2and then the p-type well3and the n-type well4are formed in a major face of the semiconductor substrate1, and the gate oxide film6of the MISFET is formed over the p-type well3and the n-type well4. After this, the drive MISFETs Qd1and Qd2and the transfer MISFETs Qt1and Qt2are formed in the p-type well3, and the load MISFETs Qp1and Qp2are formed in the n-type well4. The gate electrode7(the word line WL) and the gate electrode8are composed of a polycrystalline silicon8aand Ti-silicide film8bfilm, and the cap insulating film is composed of the silicon nitride film12a. The side wall spacers11on the individual side walls of the gate electrode7(the word line WL) and the gate electrode8are formed by anisottopically etching a silicon nitride film which is deposited over the gate electrodes7,8and the cap insulating film12a.

Next, as shown inFIGS. 100 and 101(a) and (b), in accordance with the manufacturing method of the foregoing embodiment 1, the Ti-silicide layer10is formed to reduce the sheet resistance over the individual n-type semiconductor regions5and5(the source region add the drain region) of the load MISFETs Qp1and Qp2, and the individual p-type semiconductor regions9and9(the source region and the drain region) of the load MISFETs Qp1and Qp2.

Next, as shown inFIGS. 102 and 103(a) and (b), the silicon oxide film13a, deposited over the semiconductor substrate by a CVD method and having a small thickness of about 50 nm, is etched to form the connection hole14over the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), the connection hole40over the n-type semiconductor region5(the drain region) of the drive MISFET Qd1and the connection hole41over the p-type semiconductor region9(the drain region) of the load MISFET Qp1. After this, a TiN film, deposited over the silicon nitride film13aby a sputtering method or a CVD method and having a thickness of about 100 nm, is patterned to form the local wiring line L1. This local wiring line L1is given an area wide enough to cover the six MISFETs constituting the memory cell. The local wiring line L1is connected through the connection hole14with the gate electrode8of the drive MISFET Qd2(the load MISFET Qp2), through the connection hole40with the n-type semiconductor region5(the drain region) of the drive MISFET Qd1, and through the connection hole41with the p-type semiconductor region9(the drain region) of the load MISFET Qp1.

Next, as shown inFIGS. 104 and 105(a) and (b), the silicon nitride film42, deposited over the semiconductor substrate1by a CVD method and having a small thickness of about 30 nm, is etched to form the connection hole18over the gate electrode8of the drive MISFET. Qd1(or the load MISFET Qp1), the connection hole19over the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and the connection hole20over the p-type semiconductor region9(the drain region) of the load MISFET Qp2. After this the local wiring line L2of a TiN film is formed over the silicon nitride film42. The local wiring line L2is connected through the connection hole18with the gate electrode8of the drive MISFET Qd1(the load MISFET Qp1), through the connection hole19with the n-type semiconductor region5(the drain region) of the drive MISFET Qd2, and through the connection hole20with the p-type semiconductor region9(the drain region) of the load MISFET Qp2.

The local wiring line L2is formed by depositing a TiN film having a thickness of about 100 nm over the silicon nitride film42by a sputtering method or a CVD method, by then depositing the silicon nitride film47having a thickness of about 100 nm over the TiN film by a CVD method, and thereafter by patterning the silicon nitride film47and the TiN film by a dry etching method using a photoresist as the mask. The local wiring line L2is given an area wide enough to cover the six MISFETs constituting the memory cell and to overlap the lower local wiring line L1substantially completely in the region excepting the open regions of the connection holes18,19and20and the registration allowance region. As a result, the capacitor element C is formed of the local wiring lines L1and L2(the paired electrodes) and the silicon nitride film42(the dielectric film) made thinner than the local wiring lines L1and L2. Moreover, the charge of the capacitor element C can be increased so that the amount of stored charge of the storage node can be increased to improve the alpha particle soft error resistance of the memory cell.

Next, as shown inFIG. 106(a) and (b), the side wall spacers48aare formed on the individual side walls of the lower local wiring line L1and the upper local wiring line L2. The side wall spacer11ais also formed on the side wall of the gate electrode7,8(the word line WL). The side wall spacers48aare formed by anisottopically etching a silicon nitride film which is deposited over the silicon nitride film47by a CVD method and has a thickness of about 200 nm.

Next, as shown inFIGS. 107(a) and (b) and108, the interlayer insulating film49of PSG having a thickness of about 400 nm is deposited over the silicon nitride film47by a CVD method. After this, the interlayer insulating film49is opened by a dry-etching method using a photoresist as the mask to form the connection holes50and50over the p-type semiconductor regions9and9(the source regions) of the load MISFETs Qp1and Qp2, the connection holes51and51over the n-type semiconductor region5and5(the source regions) of the drive MISFETs Qd1and Qd2, and the connection holes52and52over the n-type semiconductor regions5and5(the drain regions) of the transfer MISFETs Qd1and Qt2. Since, at this time, the side wall spacers48a,11aof the silicon nitride film and the silicon nitride film47act as etching stoppers, neither the gate electrode8is exposed at the side walls of the connection holes50and51, nor is exposed the gate electrode7(the word line WL) at the side wall of the connection hole52. Likewise, neither the lower local wiring line L1nor the upper local wiring line L2is exposed at the side walls of the connection holes50,51and52.

In short, when the manufacturing method of the present embodiment is applied to the SRAM in which the paired local wiring lines L1and L2are arranged in different conductive layers, it is unnecessary to take into consideration the registration allowance between the connection holes50,51and52and the upper local wiring line L2, and the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8. As a result, the connection holes50,51and52can be so arranged as to be closer to the upper local wiring line L2, the lower local wiring line L1, the gate electrode7(word line WL) and the gate electrode8by a distance corresponding to those registration allowances so that the area occupied by the memory cell can be reduced. In order that the side wall spacers48a,11a, and the silicon nitride film47may function as the etching stoppers when the interlayer insulating film49is etched, the thickness of the silicon nitride film constituting the side wall spacers48ais made larger than the registration allowance of the aforementioned photoresist mask.

In the present embodiment, the side wall spacers48a,11aof the silicon nitride are formed in advance on the individual side walls of the gate electrode7(the word line WL), the gate electrode8, the lower local wiring line L1and the upper local wiring line L2, and the connection holes50,51and52are then formed in the interlayer insulating film49. As in the foregoing embodiment 4, the silicon nitride film and the interlayer insulating film49can be deposited over the silicon nitride film47covering the upper local wiring line L2so that the side wall spacers may be formed when the interlayer insulating film49is opened to form the connection holes50,51and52.

Next, as shown inFIGS. 107(a) and (b) and109, in accordance with the manufacturing method of the foregoing embodiment 3, the power supply voltage line22, the reference voltage line23and the intermediate wiring line54are formed over the interlayer insulating film49. After this, as shown inFIGS. 96 and 97(a) and (b), the interlayer insulating film26is deposited over the power supply voltage line22, the reference voltage line23and the intermediate wiring line54, and the interlayer insulating film26over the intermediate wiring line54is opened to form the connection hole55. After this, the data lines DL and DL are formed over the interlayer insulating film26.

According to the present embodiment, the paired local wiring lines L1and L2are formed in different conductive layers and are so arranged as to be superposed on each other so that the area occupied by the memory cell can be reduced. At the same time, there are made unnecessary the registration allowance between the connection holes50,51and52and the upper local wiring line L2, the registration allowance between the connection holes50,51and52and the lower local wiring line L1, and the registration allowance between the connection holes50,51and52and the gate electrode7(the word line WL) and the gate electrode8, so that the area occupied by the memory cell can be further reduced.

According to the present embodiment, the upper local wiring line L2and the lower local wiring line L1are so arranged as to overlap with each other over a wide area, and the capacitor element C is composed of the local wiring lines L1and L2and the thin insulating film interposed therebetween, so that the alpha particle soft error resistance of the memory cell can be improved.

Although our invention has been specifically described in connection with its embodiments, it should not be limited thereto but can naturally be modified in various manners without departing from the gist thereof.

The metal material of the local wiring lines can be selected from a variety of materials in addition to those of the foregoing embodiments. For example, the lower local wiring line may be made of a first-layer aluminum metal (TiN/Al/TiN) whereas the upper local wiring line may be made of a second-layer aluminum metal. In this case, the power supply voltage line and the reference voltage line are made of a third layer aluminum metal whereas the complementary data lines are made of a fourth-layer aluminum metal.

The effects obtained by the present invention disclosed herein will be briefly described in the following.

According to the SRAM of the present invention, the paired local wiring lines cross-connecting the input/output terminals of the flip-flop circuit of the memory cell are formed in different conductive layers. As a result, the space, required to arrange the paired local wiring lines transversely when the two local wiring lines are composed of a common conductive film, can be eliminated, so that the local wiring lines can be so arranged as to overlap partially to reduce the area occupied by the memory cell.

According to the SRAM of the present invention, the lower local wiring line and the upper local wiring line are so arranged as to overlap with each other, and a capacitor element is composed of those local wiring lines and the insulating film interposed therebetween. As a result, the storage node capacitance of the memory cell can be increased to prevent a drop in the alpha particle soft error resistance which may be caused by the miniaturization of the memory cell size and the drop in the operation power supply voltage.

According to the SRAM of the present invention, refractory metal silicide layers of a low resistance material are formed on the surfaces of the source and drain regions of the drive MISFETs, the load MISFETs and the transfer MISFETs constituting the memory cell, so that the high-speed operation of the memory cell can be realized.

According to the SRAM of the present invention, the active region of the semiconductor substrate (the p-type well) where the drive MISFETs and the transfer MISFETs are formed, and the active region of the semiconductor substrate (the n-type well) where the load MISFETs are formed, are isolated by the grooves which are opened in the semiconductor substrate. As a result, the area occupied by the element isolating region can be made lower than that of the case that the isolation is achieved by the field insulating film formed by a LOCOS method, so that the area occupied by the memory cell can be reduced.

According to the method for manufacturing the SRAM of the present invention, the mask registration allowance, when the connection holes are made in the interlayer insulating film by using a photoresist as the mask, can be eliminated to reduce the area occupied by the memory cell.

While we have shown and described several embodiments in accordance with the present invention, it is understood that the same is not limited thereto, but is susceptible of numerous changes and modifications as known to those skilled in the art. Therefore, we do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are encompassed by the scope of the appended claims.