Delay-based spread spectrum clock generator circuit

A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

TECHNICAL FIELD

The present invention relates to the field of spread spectrum clock generation and, in particular, to a delay-based spread spectrum clock generator circuit.

BACKGROUND

System on Chip (SoC) type integrated circuits typically include a digital circuit that operates in response to a clock signal. The evolution of SoC digital circuit designs requires increasing the frequency of the clock signal. However, as the operating frequency of the clock signal increases, the electromagnetic interference (EMI) also increases. This EMI can be a significant concern, especially in consumer electronics, with microprocessor-based systems and data transmission circuits. Reduction of EMI is therefore a critical design feature.

There are a number of known EMI reduction schemes including: the use of a shielding box, skew-rate control circuits and spread spectrum clock generation. Of these options, spread spectrum clock generation is an attractive solution because of its lower hardware cost. As a result, a spread spectrum clock generation circuit is a common component of many SoC designs.

SUMMARY

In an embodiment, a circuit comprises: a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals; a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output; and a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes: a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated.

In an embodiment, a method comprises: selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal; generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile; and processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal.

DETAILED DESCRIPTION

Reference is now made toFIG. 1which shows a block diagram for an embodiment of a spread spectrum clock generator circuit10. The circuit10includes a phase lock loop (PLL) circuit12configured to generate a clock signal14oscillating at a frequency fclk. The clock signal14is input to a delay chain circuit16that includes a plurality of delay elements18(for example, signal buffer circuits) of identical construction and designed to provide identical delays. The delay elements18are coupled in series with each other, with the delay chain circuit16including a plurality of taps20, wherein each tap20outputs a phase shifted clock signal22oscillating at the frequency fclk but having a different phase shift. The plurality of phase shifted clock signals22are applied to the inputs of a multiplexer circuit26. The selection input of the multiplexer circuit26receives a digital multiplexer control signal28and the multiplexer circuit26operates in response to the values of the digital multiplexer control signal28to select one of the phase shifted clock signals22for output as a spread spectrum clock signal (SSclk)30.

The multiplexer control signal28is generated by a control circuit40. The control circuit40includes a digital waveform generator circuit42that outputs a digital signal44whose values define a periodic signal having a triangular wave profile defined by a modulation depth parameter (mod_depth) and a modulation frequency parameter (mod_freq) and which is generated in response to a reference clock signal46output by a reference clock generator circuit48. The frequency fref of the reference clock signal46is substantially less than the frequency fclk of the clock signal14. A phase generator50receives the triangular wave profile digital signal44and generates the digital multiplexer control signal28. The phase generator50may, for example, comprise a digital integrator circuit (such as an accumulator with a transfer function

Reference is now made toFIG. 2which shows a block diagram for an embodiment of a spread spectrum clock generator circuit110. The circuit110includes a reference clock generator148that generates a reference clock signal146oscillating at a frequency fref. The reference clock signal146is input to a delay chain circuit116that includes a plurality of delay elements118(for example, signal buffer circuits) of identical construction and designed to provide identical delays. The delay elements118are coupled in series with each other, with the delay chain circuit116including a plurality of taps120, wherein each tap120outputs a phase shifted clock signal122oscillating at the frequency fref but having a different phase shift. The plurality of phase shifted clock signals122are applied to the inputs of a multiplexer circuit126. The selection input of the multiplexer circuit126receives a digital multiplexer control signal128and the multiplexer circuit126operates in response to the values of the digital multiplexer control signal128to select one of the phase shifted clock signals122for output as an input spread spectrum clock signal130. The input spread spectrum clock signal130is applied as the reference clock signal to a phase lock loop (PLL) circuit112that generates an output spread spectrum clock signal132oscillating at a frequency fclk (where the frequency fclk is substantially greater than the frequency fref).

The digital multiplexer control signal128is generated by a control circuit140. The control circuit140includes a digital waveform generator circuit142that outputs a digital signal44whose values define a periodic signal having a triangular wave profile defined by a modulation depth parameter (mod_depth) and a modulation frequency parameter (mod_freq) and which is generated in response to the reference clock signal146output by the reference clock generator circuit148. A phase generator150receives the values of the triangular wave profile digital signal144and generates the digital multiplexer control signal128. The phase generator150may, for example, comprise a digital integrator circuit (such as an accumulator with a transfer function of

The circuit110possesses a number of advantages over the circuit10in terms of a lower buffer delay and reduced power consumption. However, both circuit10and circuit110suffer from a common drawback in terms of a requirement for an excessively high number of delay elements18,118within the delay chain circuit16,116. Consider, for example, a reference frequency fref of 10e{umlaut over ( )}6, a modulation frequency of 50e{circumflex over ( )}3 and a modulation depth of 1% peak; so there is a period of 100 ns with a modulation depth of 1 ns Peak. The reference frequency divided by the modulation frequency is 200. The phase movement in the spread spectrum clock generator is given by: (0.5)*(1 ns)*100=50. The delay value (in each buffer) for a 5% error tolerance in profile is equal to 5/100*1 ns=50 ps. With this, the number of delay elements18,118required in the delay chain circuit16,116for the phase movement is 50 ns/50 ps=1000.

Reference is now made toFIG. 3which shows a block diagram for an embodiment of a spread spectrum clock generator circuit210. The circuit210includes a reference clock generator248that generates a reference clock signal246oscillating at a frequency fref. The reference clock signal246is input to a delay chain circuit216that includes a plurality of delay elements218(for example, signal buffer circuits) of identical construction and designed to provide identical delays. The delay elements218are coupled in series with each other, with the delay chain circuit216including a plurality of taps220, wherein each tap220outputs a phase shifted clock signal222oscillating at the frequency fref but having a different phase shift. The plurality of phase shifted clock signals222are applied to the inputs of a multiplexer circuit226. The selection input of the multiplexer circuit226receives a digital multiplexer control signal228and the multiplexer circuit226operates in response to values of the digital multiplexer control signal228to select one of the phase shifted clock signals222for output as an input spread spectrum clock signal230. The input spread spectrum clock signal230is applied as the reference clock signal to a phase lock loop (PLL) circuit212that generates an output spread spectrum clock signal232oscillating at a frequency fclk (where the frequency fclk is substantially greater than the frequency fref).

The multiplexer control signal228is generated by a control circuit240. The control circuit240includes a digital waveform generator circuit242that outputs a digital signal244whose values define a periodic signal having a triangular wave profile defined by a modulation depth parameter (mod_depth) and a modulation frequency parameter (mod_freq) and which is generated in response to the reference clock signal246output by the reference clock generator circuit248. A digital sigma-delta modulator260receives the digital signal144and generates a modulated digital signal262. In an embodiment, the sigma-delta modulator260is a third-order single, MASH 1-1-1 type circuit, but it will be understood that the sigma-delta modulator260may be of any desired order and configuration. A phase generator250receives the modulated digital signal262and generates the digital multiplexer control signal228. The phase generator250may, for example, comprise a digital integrator circuit (such as an accumulator with a transfer function

The circuit210ofFIG. 3takes advantage of the fact that the PLL212has a low-pass transfer function. The sigma-delta modulator260performs noise shaping by pushing the quantization noise introduced by the modulation operation into the higher frequency domain. This noise is then filtered out by the low-pass response of the PLL. This is beneficial because an error tolerance similar to theFIG. 2circuit can be achieved in circuit210with fewer delay elements. Consider, for example, a reference frequency fref of 10e{circumflex over ( )}6, a modulation frequency of 50e{circumflex over ( )}3, a modulation depth of 1% peak and sigma-delta modulation step of 5% (5 ns); so there is a period of 100 ns with a modulation depth of 1 ns Peak for the triangle waveform. The reference frequency divided by the modulation frequency is 200. The phase movement in the spread spectrum clock generator is given by: (0.5)*(1 ns)*100=50. So, the delay elements for phase movement with sigma-delta modulation are 50 ns/5 ns=10. The delay value (in each buffer) for a 5% error tolerance in profile is equal to 5/100*1 ns=50 ps. With this, the number of delay elements18,118required in the delay chain circuit16,116for the phase movement in theFIG. 3implementation 5 ns/50 ps=100. For a similar error tolerance, this is an order of magnitude reduction in the number of delay elements used by theFIG. 3circuit210in comparison to theFIG. 2circuit110.

Reference is now made toFIG. 4which shows a block diagram of a clocking control circuit300. The multiplexer control signal228output from the control circuit240is applied to the input of a multi-bit register302(formed, for example, by D-type flip-flops). The multi-bit register302is clocked by a clock signal304and responds to the leading edge of the clock signal304by latching the data values of the multiplexer control signal228output from the control circuit240for output as signal228′ to the selection input of the multiplexer circuit226. The multi-bit register302controls the timing for making changes to the value of the applied multiplexer control signal228′ so that such changes occur only when the logical value of the current phase and the next phase which is going to be selected are static. This is shown by the operating waveforms inFIG. 8where it will be noted that: at each positive edge of clock signal230the control circuit240gives the next value for the multiplexer control signal228; but if the changed value is immediately applied to the multiplexer there is a risk that a glitch will be produced on the output clock230; so, to avoid this concern, a delay is introduced, which is greater than the maximum phase change that can happen, and the glitch is avoided. This control operation is best achieved for the clock at time instants defined by Tref/4 and 3*Tref/4, where Tref is the clock period of the reference clock signal246. The input spread spectrum clock signal230is used to clock the logic circuitry of the control circuit240and is further applied to the input of a delay circuit306which delays the input spread spectrum clock signal230by Tref/4 and outputs the clock signal304.

Reference is now made toFIG. 5which shows a block diagram of a clocking control circuit400. The multiplexer control signal228output from the control circuit240is applied to the input of a multi-bit register402(formed, for example, by D-type flip-flops). The multi-bit register402is clocked by a clock signal404and responds to the leading edge of the clock signal404by latching the data values of the multiplexer control signal228output from the control circuit240for output as signal228′ to the selection input of the multiplexer circuit226. The multi-bit register402controls the timing for change in the applied multiplexer control signal228to occur only when the logical value of the current phase and the next phase which is going to be selected are static (see,FIG. 8). This is best achieved for the clock at time instants defined by Tref/4 and 3*Tref/4, where Tref is the clock period of the reference clock signal246. The input spread spectrum clock signal230is used to clock the logic circuitry of the control circuit240. The plurality of phase shifted clock signals222are applied to the inputs of a multiplexer circuit408. The selection input of the multiplexer circuit408receives a delayed version (signal228″) of the multiplexer control signal228generated by a delay circuit406(which delays the multiplexer control signal228by Tref/4 (for example)), and the multiplexer circuit408operates in response to that signal228″ to select one of the phase shifted clock signals222for output as the clock signal404.

With reference once again toFIG. 3, it will be noted that the length of the delay provided by each delay element218(for example, signal buffer circuit) in the delay chain circuit216is process, voltage and temperature (PVT) dependent. Because of this, the modulation depth of circuit210will also vary with change in process, voltage and temperature. An initial calibration can be performed to address the process and voltage variation of the buffer circuits. This calibration utilizes the circuit500shown inFIG. 6. Circuit500includes a delay element502configured to apply a small delay Δd to the reference clock signal246and generate a delayed clock signal504which is applied to the string of delay elements218in the delay chain circuit216. A D-type flip-flop506is provided for each delay element218, with the output of the delay element218provided to the D input of the corresponding flip-flop506. The clock input of each flip-flop506receives the reference clock signal246. The Q output of each flip-flop506is connected to a corresponding input of a binary encoder circuit510. The circuit500operates as a timed counter circuit with the binary encoder circuit510functioning to count the number of delay elements218which change logic state within one cycle of the reference clock signal246and output an encoded digital count value (Count)512indicative of the counted number.

The encoded digital count value512is then applied as a further input to the signal generator circuit242that generates the periodic signal244having the triangular wave profile (and optionally or alternatively to the sigma-delta modulator260that generates the digital output signal262). The value of the Count512is used in the signal generator circuit242to adjust the modulation depth (mod_depth) value by way of a simple multiplication (scaling) operation. In the alternative implementation, the value of the Count512is instead used in the sigma-delta modulator260to adjust the quantization levels. It is somewhat easier to perform the adjustment of modulation depth, and so this solution is preferable. The adjustment that is made will account for sensed differences in the Count512value due to process and voltage variation of the buffer circuits. For example, for Fref having a 100 ns period and where the delay provided by each delay element is 5 ns, then Count512=20 (ideal). The quantizer level for the SDM260is considered to be 5 ns (always). Now, due to process variation, the delay element becomes 10 ns, Count=10 (actual). In that case the scaling factor will become actual/deal=10/20=0.5. A multiplication block (not explicitly shown) positioned between generator242and SDM260can be used.

The foregoing calibration operation does not address temperature variation. However, temperature variation is minute in circuit210and may in many implementations be ignored without negative impact. If temperature compensation is needed, a delay locked loop (DLL) circuit may be provided in order to keep the buffer delays locked with each other.

Reference is now made toFIGS. 7A-7Dwhich show plots illustrating operation of theFIG. 3circuit210.FIG. 7Ashows the unfiltered output clock frequency signal230scaled by N (which is the divisor value in the PLL212) where the y-axis shows frequency in Hz and the x-axis shows the sample number in terms of clock cycle.FIG. 7Bshows the output clock frequency of the PLL with signal232where the y-axis shows frequency in Hz and the x-axis shows the sample number in terms of clock cycle.FIG. 7Cshows the multiplexer control for the delay chain signal228where the y-axis shows the value of the multiplexer selection and the x-axis shows the sample number in time (every REF cycle).FIG. 7Dshows a plot of the phase noise power spectral density where the y-axis shows dBc/Hz and the x-axis shows frequency in Hz. The density plot for “No mod clock” shows the density for the case where no spread spectrum clock generation (SSCG) is performed. The density plot for “Ideal SSCG” shows the density for the case where a pure triangle waveform is used for the spread spectrum clock generation. The density plot for “Modulated SSCG” shows the density for the case where sigma-delta modulation (SDM) of the triangle waveform is used for the spread spectrum clock generation.

Although the preceding description has been described herein with reference to particular circuits and embodiments, it is not intended to be limited to the particulars disclosed herein; rather, it extends to all functionally equivalent structures, methods, and uses, such as are within the scope of the appended claims.