Dual independent output LLC converter control

A method and apparatus for controlling a power converter are provided. In the method and apparatus, switching from a first phase to a second phase is delayed until it is determined that both a tank current signal of the converter goes below a tank current threshold and the converter has been in the first phase for more than a first minimum time period. Then the converter determines if a resonant capacitor voltage has fallen below a first resonant capacitance voltage threshold and if a tank current signal goes above a tank current threshold. The converter switches from the first phase to the second phase in response to determining at least one of: the resonant capacitor voltage has fallen below the first resonant capacitance voltage threshold and the tank current signal goes above the tank current threshold. The converter is additionally operated in third and fourth states.

BACKGROUND

Technical Field

This application is directed to controlling a power converter, and in particular controlling an LLC converter having two independent outputs.

Description of the Related Art

Dual independent output LLC converters are a class of converters characterized in that they output two voltages that are independent of each other. The output voltages may be used to supply power to one or more devices. Because this class of converters provides two independent output voltages and the two output voltages are taken into account in performing the control, conventional control of the converters is computationally intensive. Some conventional solutions (such as that described in R. Elferich and T. Duerbaum, “A New Load Resonant Dual-Output Converter,”Proceedings of the33rd Annual IEEE Power Electronics Specialists Conference,2002) utilize multidimensional control which increases the computational complexity required from control devices to operate the converter.

Other solutions, such as Bang-Bang charge control (BBCC) described in Z, Hu, Y. Liu, and P. C. Sen, “Bang-Bang Charge Control for LLC Resonant Converters,”IEEE Transactions on Power Electronics,Vol. 30, No. 2, February 2015, simplify the control of dual-output LLC converters. However, such solutions simplify control at the expense of introducing critical conditions that can disrupt operation of the converter.

Accordingly, a method and a controller for controlling a dual independent output LLC converter are desired. In addition, it is also desirable for the method and controller to simplify control of the LLC converter while at the same time maintaining stability in the operation of the LLC converter.

BRIEF SUMMARY

In an embodiment, a controller for controlling a power converter having a power stage with first and second output terminals includes first and second switches configured to control the power stage; and a control stage configured to control the first and second switches using a method that includes: determining a first resonant capacitance voltage threshold based on at least a first output voltage at the first output terminal; determining a second resonant capacitance voltage threshold based on at least a second output voltage at the second output terminal; switching from a first phase, in which the first switch is on and the second switch is off, to a second phase, in which the first and second switches are off, in response to determining that a resonant capacitor voltage of the power stage has fallen below the first resonant capacitance voltage threshold; switching from the second phase to a third phase in which the second switch is on and the first switch is off; and switching from third phase to a fourth phase, in which the first and second switches are off, in response to determining that a resonant capacitor voltage of the power stage has gone above the second resonant capacitance voltage threshold.

In an embodiment, the control stage is configured to switch from the first phase to the second phase in response to determining that a tank current signal, representative of a tank current of the power stage, goes below a tank current threshold and then goes above the tank current threshold. In an embodiment, the control stage is configured to delay switching from the first phase to the second phase in response to determining that the switches have been in the first phase for less than a first minimum time period.

In an embodiment, the control stage is configured to switch from the first phase to the second phase in response to determining that the resonant capacitor voltage of the power stage has fallen below the first resonant capacitance voltage threshold after determining that a tank current signal, representative of a tank current of the power stage, goes below a tank current threshold. In an embodiment, the control stage is configured to delay switching from the second phase to the third phase in response to determining that the switches have been in the second phase for less than a second minimum time period.

In an embodiment, the control stage is configured to switch from the third phase to the fourth phase in response to determining that a tank current signal, representative of a tank current of the power stage, goes above a tank current threshold and then goes below the tank current threshold. In an embodiment, the control stage is configured to delay switching from the third phase to the fourth phase in response to determining that the switches have been in the third phase for less than a first minimum time period.

In an embodiment, the control stage is configured to switch from the third phase to the fourth phase in response to determining that the resonant capacitor voltage of the power stage has risen above the second resonant capacitance voltage threshold after determining that a tank current signal, representative of a tank current of the power stage, goes above a tank current threshold. In an embodiment, the control stage is configured to delay switching from the fourth phase to another phase in response to determining that the switches have been in the fourth phase for less than a second minimum time period.

In an embodiment, a power converter includes a power stage with first and second output terminals; a switching stage with first and second switches configured to control the power stage; and a control stage configured to control the first and second switches using a method that includes: delaying switching from a first phase, in which the first switch is on and the second switch is off, to a second phase, in which the first and second switches are off, until determining that both: a tank current signal, representative of a tank current of the power stage, goes below a tank current threshold and the switches have been in the first phase for more than a first minimum time period; determining if a resonant capacitor voltage of the power stage has fallen below a first resonant capacitance voltage threshold; determining if the tank current signal goes above a tank current threshold; switching from the first phase to the second phase in response to determining at least one of: the resonant capacitor voltage of the power stage has fallen below the first resonant capacitance voltage threshold and the tank current signal goes above the tank current threshold; switching from the second phase to a third phase in which the second switch is on and the first switch is off; and switching from third phase to a fourth phase, in which the first and second switches are off.

In an embodiment, the control stage configured to: determine the first resonant capacitance voltage threshold based on at least a first output voltage at the first output terminal; and determine a second resonant capacitance voltage threshold based on at least a second output voltage at the second output terminal.

In an embodiment, the control stage is configured to: begin determining if the resonant capacitor voltage of the power stage has fallen below the first resonant capacitance voltage threshold and begin determining if the tank current signal goes above the tank current threshold after determining that both: the switches have been in the first phase for the first minimum time period, and the tank current signal goes below the tank current threshold.

In an embodiment, the control stage is configured switch from the second phase to the third phase in response to determining that the switches have been in the second phase for a second minimum time period or longer. In an embodiment, the control stage is configured to delay switching from the third phase to the fourth phase in response until the control stage determines that the tank current signal is above the tank current threshold and the switches have been in the third phase for at least a first minimum time period. In an embodiment, the control stage is configured to, after delaying the switching, switch from third phase to the fourth phase in response to determining that the resonant capacitor voltage has gone above the second resonant capacitance voltage threshold. In an embodiment, the control stage is configured to, after delaying the switching, switch from third phase to the fourth phase in response to determining that the tank current signal goes below the tank current threshold.

In an embodiment, a method includes delaying switching from a first phase, in which a first switch of a converter is on and a second switch of the converter is off, to a second phase, in which the first and second switches are off, until determining that both: a tank current signal, representative of a tank current of the converter, goes below a tank current threshold and the switches have been in the first phase for more than a first minimum time period; determining if a resonant capacitor voltage of the converter has fallen below a first resonant capacitance voltage threshold; determining if the tank current signal, representative of a tank current of the converter, goes above the tank current threshold; switching from the first phase to the second phase in response to determining at least one of: the resonant capacitor voltage has fallen below the first resonant capacitance voltage threshold and the tank current signal goes above the tank current threshold; switching from the second phase to a third phase in which the second switch is on and the first switch is off; and switching from third phase to a fourth phase, in which the first and second switches are off.

In an embodiment, the method includes determining the first resonant capacitance voltage threshold based on an input voltage and a first output voltage of the converter; and determining a second resonant capacitance voltage threshold based on the input voltage and a second output voltage of the converter. In an embodiment, the method includes beginning to determine if the resonant capacitor voltage has fallen below the first resonant capacitance voltage threshold and beginning to determine if the tank current signal goes above the tank current threshold after determining that both: the switches have been in the first phase for the first minimum time period, and the tank current signal goes below the tank current threshold. In an embodiment, the method includes switching from the second phase to the third phase in response to determining that the switches have been in the second phase for a second minimum time period or longer.

In an embodiment, the method includes delaying switching from the third phase to the fourth phase until determining that the tank current signal is above the tank current threshold and the switches have been in the third phase for at least a first minimum time period. In an embodiment, the method includes after delaying the switching, switching from the third phase to the fourth phase in response to determining that the resonant capacitor voltage has gone above a second resonant capacitance voltage threshold. In an embodiment, the method includes after delaying the switching, switching from the third phase to the fourth phase in response to determining that the tank current signal goes below the tank current threshold. In an embodiment, the method includes delaying switching from the fourth phase to another phase in response to determining that the switches have been in the fourth phase for less than a second minimum time period.

DETAILED DESCRIPTION

FIG. 1shows a block diagram of a dual independent output LLC converter100in accordance with an embodiment. The converter100includes a control stage102, a switching stage104, a power stage106, a first compensation stage108, a second compensation stage110, a first isolation stage112, a second isolation stage114, a tank current sensing stage116and a voltage sensing stage117.

As a dual independent output converter, the converter100outputs two independent output voltages: a first output voltage (VOUT1) and a second output voltage (VOUT2). As shown inFIG. 1, the first output voltage (VOUT1) is provided at a first output voltage node118and the second output voltage (VOUT2) is provided at a second output voltage node120.

The control stage102operates the converter100in one of a plurality of states. The control stage102determines first and second resonant voltage thresholds based on the input voltage and the first and second output voltages, respectively. The control stage102then determines the state in which to operate the converter100and whether to switch the converter between states based on comparing a resonant capacitance voltage of the converter with one of the resonant voltage thresholds. Further, the control stage102determines the state in which to operate the converter100and whether to switch states based on whether a tank current of the converter exceeds or is below a tank current threshold. Further, the control stage102may retain the converter100in one of the states for a minimum period of time before transitioning the converter100out of a state as described herein.

The power stage106of the converter100generates the output voltages based on a voltage received from the switching stage104. The switching stage104is coupled, at an input, to an input voltage node122and a ground node124. An input voltage (VIN) is provided at the input voltage node122and a ground voltage is provided at the ground node124. The input voltage (VIN) is used to drive the power stage106. The switching stage104also has an input for receiving one or more gate drive signals from the control stage102. The one or more gate drive signals dictate operation of the switching stage104. The switching stage104outputs the input voltage (VIN) or the ground voltage to the power stage106depending on a state of the one or more gate drive signals. As described herein, at times, neither voltage may be provided and the switching stage104is not connected to a voltage supply node.

The power stage106uses the voltage received from the switching stage104to generate the two independent output voltages (VOUT1and VOUT2). The power stage106may output the two independent output voltages to different loads or to the same load. The power stage106is coupled to a ground node125, which may be a physical ground, whereas the ground node124may be a virtual ground. The ground nodes124,125may provide ground for the primary and secondary sides of the converter100, respectively, and may be decoupled from each other. The converter100has a feedback loop for controlling and regulating the output voltages (VOUT1and VOUT2). The first compensation stage108has an input that is coupled to the first output voltage node118. The first compensation stage108receives, at the input, the first output voltage (VOUT1). The first compensation stage108compensates the first output voltage. The first compensation stage108has an output that provides a compensated first output voltage. The first compensation stage108may control its output using a filter implementing a control function, such as a Proportional Integral Derivative (PID).

The first isolation stage112, which may include an optocoupler, among other couplers, may be configured to channel or tunnel signals between voltage or power domains without breaching a boundary (for example, a power domain isolation boundary). It is desirable for the isolation stage112to timely translate a signal of one power domain into another signal of another power domain. For example, it is desirable for a lag between the signals to be at a minimum.

The first isolation stage112has an input coupled to the output of the first compensation stage108. The first isolation stage112receives, at the input, the compensated first output voltage. The first isolation stage112provides, at an output, an isolated first output voltage.

The second compensation stage110has an input coupled to the second output voltage node120. The second compensation stage110receives, at the input, the second output voltage (VOUT2). The second compensation stage110compensates the second output voltage. The second compensation stage110has an output that provides a compensated second output voltage. The second compensation stage110may control its output using a filter implementing a control function, such as a PID.

The second isolation stage114, which may be similar to the first isolation stage112and may be an optocoupler, has an input coupled to the output of the second compensation stage110. The second isolation stage114receives, at the input, the compensated second output voltage. The second isolation stage114provides, at an output, an isolated second output voltage.

The tank current sensing stage116of the converter100has an input coupled to the power stage106. As described herein, the tank current sensing stage116detects a tank current of the power stage106. The tank current sensing stage116has an output coupled to an input of the control stage102. The tank current sensing stage116provides, at the output, a first sensing signal representative of the tank current of the power stage106.

The voltage sensing stage117has an input coupled to the power stage106. The voltage sensing stage117senses a voltage across a resonant capacitance of the power stage106of the converter100as described herein. The voltage sensing stage117has an output coupled to an input of the control stage102. The voltage sensing stage117provides, at the output, a second sensing signal representative of the voltage across the resonant capacitance of the power stage106. In an embodiment, the voltage sensing stage117may be a resistance or a capacitance, among others.

The control stage102may be any type of controller, such as a microcontroller, a processor or a microprocessor, among others. The control stage102may include control logic (not shown), which may be analog or digital circuitry. The control stage102(or control logic thereof) is configured to operate and control the converter100(or its switching stage104or power stage106) in accordance with the embodiments described herein. Although not shown, the control stage102may include a non-transitory computer-readable storage medium or memory configured to store executable instructions that, when executed by the control stage102(or control logic thereof), cause the control stage102to operate and/or control the converter100(or its switching stage104or power stage106) as described herein.

The control stage102has a plurality of inputs. The control stage102has a first input coupled to the output of the first isolation stage112, a second input coupled to the output of the second isolation stage114, a third input coupled to the output of the tank current sensing stage116and a fourth input coupled to the output of the voltage sensing stage117. The control stage102receives the compensated first and second output voltages and the first and second sensing signals. The control stage102determines the timing of operating the switching stage104based on the compensated first and second output voltages and the sensing signals. The control stage102outputs the one or more gate drive signals for controlling the switching stage104.

FIG. 2shows a circuit block diagram of the dual independent output LLC converter100in accordance with an embodiment. Similar elements of the converter100to those described with reference toFIG. 1have the same reference numerals.

The switching stage104includes a first transistor126and a second transistor128. The power stage106includes a resonant inductance130, a shunt inductance132, a transformer134, a resonant capacitance148, a first diode136, a second diode138, a first output capacitance140and a second output capacitance142. The tank current sensing stage116includes a sense capacitance146and a sense resistance150.

In the switching stage104, the first and second transistors126,128are shown as n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), however, any other type of transistor or switch may alternatively be used. The first transistor126has a drain coupled to an intermediary node152, a source coupled to the ground node124and a gate for receiving a first gate drive signal. The second transistor128has a drain coupled to the input voltage node122, a source coupled to the intermediary node152and a gate for receiving a second gate drive signal.

The resonant inductance130is coupled between the intermediary node152and a first primary side node154. The shunt inductance132is coupled between the first primary side node154and a second primary side node156. The transformer134has a primary winding158coupled between the first and second primary side nodes154,156. The primary winding158, which is in the primary domain, is galvanically isolated from a first secondary winding160and a second secondary winding162, that is in the secondary domain. The transformer's secondary side is center-tapped, whereby the first secondary winding160is coupled between a first secondary side node164and a ground node125and the second secondary winding162is coupled between the ground node125and a second secondary side node166. The resonant capacitance148is coupled between the second secondary side node166and the ground node125.

The first diode136has an anode coupled to the first secondary side node164and a cathode coupled with the first output voltage node118. The first output capacitance140is coupled between the first output voltage node118and the ground node125. The second diode138has an anode coupled to the second secondary side node166and a cathode coupled to second output voltage node120. The second output capacitance142is coupled between the second output voltage node120and the ground node125.

In the tank current sensing stage116, the sense capacitance146is coupled between the second primary side node156and an output node168. The sense resistance150is coupled between the output node168and the ground node124. The tank current sensing stage116senses the tank current (iT) flowing into the resonant capacitance148(Cr) of the power stage106. The tank current sensing stage116outputs a first sensing signal (ics) representative of the tank current (iT) of the power stage106.

The control stage102outputs first and second gate drive signals to the switching stage104. The first and second gate drive signals may have opposite states when either is asserted. For example, when the first gate drive signal is asserted (activated, active or has a logical state of one), the second gate drive signal will be deasserted (deactivated, inactive or has a logical state of zero). The first gate drive signal, when asserted, causes the first transistor126to transition to the electrically conductive state (closed state). In the meantime, the second gate drive signal is deasserted, and the second transistor128is in the electrically non-conductive state (open state). When the first transistor126is in the electrically conductive state, the ground voltage is supplied to the power stage106.

The control stage102deasserts the first gate drive signal and asserts the second gate drive signal to supply the input voltage (VIN) to the power stage106. When the first gate drive signal is deasserted and the second gate drive signal is asserted, the first transistor126is open and the second transistor128is closed. Thus, the input voltage (VIN) is applied to the power stage106. The first and second gate drive signals may both be deasserted, in which case neither the input voltage nor the ground voltage is provided to the power stage106.

The duration of time that the first gate to drive signal is asserted and the duration of time that the second a gate drive signal is asserted control the first and second output voltages (VOUT1and VOUT2) of the converter100. It is noted that the loads (not shown) that are connected to the first and second output voltage nodes118,120and that draw the first and second output voltages (VOUT1and VOUT2) also affects the voltages.

The control stage102controls the output voltages (VOUT1and VOUT2) of the converter100based on feedback voltages (the isolated first and second output voltages) received from the first and second isolation stages112,114. In addition to the feedback voltages, the control stage102uses the sensing signals to drive the power stage106and control the output voltages. As described herein, the sensing signals are indicative of the voltage across the resonant capacitance148of the power stage106and the tank current passing through the second primary side node156.

FIG. 3shows a state diagram for controlling the converter100in accordance with an embodiment. The converter100is initially powered302or turned on. When the converter100is powered, the control stage102puts the converter100in a first state304, denoted as ‘LSON’ or low side on, in reference to turning on or switching to the electrically-conductive state the first transistor126of the switching stage104, or the low transistor in a stack in relation to the high second transistor128. In the first state304, the first gate drive signal is activated and the second gate drive signal is deactivated resulting in turning on the first transistor126and turning off the second transistor128and supplying a ground voltage to the power stage106.

While the converter100is in the first state304, the control stage102determines whether the voltage of the resonant capacitance148(VCr) represented by the second sending signal is below a first threshold for the resonant capacitance voltage. If the control stage102determines that the resonant capacitance voltage (VCr) is higher than the first threshold, the control stage102retains the converter100and the first state304. Conversely, if the control stage102determines that the resonant capacitance voltage (VCr) is lower than the first threshold, the control stage102transitions the converter100to a second state306. The control stage102evaluates whether the resonant capacitance voltage is lower than the first threshold periodically or according to a time schedule.

The second state306is denoted as dead time low or ‘DTL’ herein. In the second state306, the first and second gate drive signals are deactivated and both transistors126,128are in the electrically non-conductive state. The control stage102keeps the converter100in the second state306for a duration of time (denoted herein as ‘Tdead’). The duration of time may be predetermined. The control stage102may be configured with the duration of time (Tdead), whereby the duration of time may be stored in a memory of the control stage102.

After the duration of time expires, the control stage102transitions the converter100to a third state308, denoted herein as ‘HSON’ or high side on, in reference to turning on or switching to the electrically-conductive state the second transistor128that is the higher transistor in a stack of the switching stage104. In the third state308, the first gate drive signal is deactivated and the second gate drive signal is activated resulting in turning off the first transistor126and turning on the second transistor128. Consequently, the input voltage (VIN) is supplied to the power stage106.

While the converter is in the third state308, the control stage102determines whether the resonant capacitance voltage (VCr) is greater than a second threshold. As described herein, the second threshold for the voltage of the resonant capacitance is greater than the first threshold. If the control stage102determines that the resonant capacitance voltage is not greater than the second threshold, the control stage102retains the converter100in the third state308. Conversely, if the control stage102determines that the resonant capacitance voltage is greater than the second threshold, the control stage102transitions the converter100to a fourth state310.

The fourth state310is denoted herein as ‘DTH’ or dead time high, because it follows the state in which the high side of the switching stage104was in the on-state. Similar to the second state306, in the fourth state310, both the first and second gate drive signals are deactivated and both the first and second transistors126,128are non-conductive. The control stage102retains the converter100in the fourth state310for the duration of time (Tdead). After that the duration of time elapses the control stage102transitions the converter100back to the first state304. It is noted that the duration of time (Tdead) for the second and fourth states306,310may be the same or different.

Accordingly, per the method ofFIG. 3, when the resonant capacitance voltage exceeds the second threshold, the input voltage (VIN) is no longer provided to the power stage106. After the expiration of a minimum of time, the ground voltage is provided to the power stage106. The ground voltage continues to be provided until the resonant capacitance voltage drops below the first threshold. Then, the ground voltage is ceased to be provided to the power stage106. After the minimum period of time expires again, the input voltage is provided to the power stage106.

The first and second thresholds may be determined as a function of the first and second output voltages (or feedback voltages representative of the first and second output voltages). The first threshold may be represented as:

VthL=VIN2-(I2+(π-1)⁢I1)⁢LrCr,Equation⁢⁢(1)
where I1is the current flowing in the first primary side node154during conduction of diode136, I2is the current flowing in the first primary side node154during conduction of diode138, Lris the resonant inductance and Cris the resonant capacitance.

The second threshold may be represented as:

The terms for the first and second output currents and the resonant inductance and capacitance may be replaced with the terms for the first and second feedback voltages (Vfb1and Vfb2). The first and second thresholds may be represented as:

Equations (3) and (4) may be simplified as:

Thus, the first threshold may be estimated to be solely dependent on the input voltage, the first feedback voltage and the first gain term. Similarly, the second threshold may be estimated to be solely dependent on the input voltage, the second feedback voltage and the second gain term.

The control stage102receives the first and second feedback voltages from the first and second isolation stages112,114, respectively. The control stage102determines the first threshold based on the input voltage, the first feedback voltage and the first gain term. The control stage102also determines the second threshold voltage based on the input voltage, the second feedback voltage and the second gain term. The control stage102may be configured with the first and second gain terms, which may be stored by the control stage102.

FIG. 4shows a signal diagram for operating the converter100in accordance with an embodiment. InFIG. 4, the first threshold402, the second threshold404, the resonant capacitance voltage406, the first gate drive signal408and the second gate drive signal410are shown.

Initially, the converter100is in the third state308, whereby the second gate drive signal is asserted and the second transistor128of the switching stage104is closed. At a first time instance312, the control stage102determines that the resonant capacitance voltage exceeds the second threshold. In response to the determination, the control stage102transitions the converter100to the fourth state310. The converter100remains in the fourth state310for the duration of time (Tdead). At a second time instance314, the duration of time expires. In response, the control stage102transitions the converter100to the first state304. The converter100remains in the first state304until the resonant capacitance voltage drops below the first threshold at a third time instance316. The control stage102identifies that the resonant capacitance voltage has dropped below the first threshold. In response, the control stage102transitions the converter100to the second state306.

The control stage102retains the converter100in the second state306for the duration of time. It is noted that the durations of time that the converter100remains in the second and fourth states306,310may be the same or different. At a fourth time instance318, the duration of time expires. The control stage102detects that the duration of time expired. The control stage102transitions the converter to the third state308. The converter100remains in the third state308until the resonant capacitance voltage becomes greater than the second threshold at a fifth time instance320. In response to which, the control stage102transitions the converter100to the fourth state310.

It is noted that controlling the converter in accordance with the state diagram ofFIG. 3may result in critical operating conditions. If the resonant capacitance voltage does not drop below the first threshold, the converter100may not exit the first state304and transition to the second state306. Similarly, if the resonant capacitance voltage does not exceed the second threshold, the converter100may not exit the third state308and transition to the fourth state310.

Another critical condition may occur when the first and second thresholds are inverted. For example, under normal operating conditions the second threshold is greater than the first threshold. However, if the thresholds (determined based on Equations (5) and (6) above) are inverted such that the first threshold is greater than the second threshold, the converter100switching frequency may become infinite in a theoretical sense.

To mitigate threshold inversion and the scenario where the resonant capacitance voltage does not cross over one of the thresholds, alternative state switching for operating the converter100may be used.

FIG. 5shows a state diagram for controlling the converter100in accordance with an embodiment. The state diagram includes a first state502, a second state504, a third state506and a fourth state508. The first state502includes a first substate502aand the second substate502b, and the third state includes a first substate506aand a second substate506b. In the first state502, the first transistor126is closed and the second transistor128is open. In the second state504, both transistors126,128are open. In the third state506, the first transistor126is open and the second transistor128is closed. In the fourth state508, both transistors126,128are open.

When the converter100is powered, the control stage102puts the converter100in the first substate502aof the first state502(denoted herein as ‘LSON1’). Alternatively, the control stage102may put the converter100in another state upon starting or powering the converter100.

In the first state502(and its substates502a,502b), the first gate drive signal is asserted and the first transistor126is closed so that a ground voltage is supplied to the power stage106. The control stage102retains the converter100in the first substate502aof the first state502at least until two conditions are satisfied. The first condition is satisfied when a first period of time (denoted herein as ‘Tmin’) has elapsed. The second condition is satisfied when the tank current (iT) is lower than a tank current threshold, which may be 0 A. For example, the second condition may be satisfied when the tank current is negative or inverted. When the tank current is negative, zero current detection (ZCD) is set to have been made.

Accordingly, the control stage102retains the converter100in the first substate502aof the first state502for at least the duration of the first period of time. The first period of time may commence when the converter100is placed in the first substate502a. The control stage102may retain the converter100in the first substate502afor longer than the duration of the first period of time (Tmin) and until the tank current becomes lower than the threshold. The control stage102may retain the converter100in the first substate502afor a duration that is the greater of: the first period of time (Tmin) and a period of time required for the tank current to become lower than the tank current threshold, which may be 0 A.

While in the first substate502a, the control stage102monitors the tank current. When both the duration of the first period of time elapses and the tank current becomes negative or is inverted, the control stage102transitions the converter100to the second substate502bof the first state502.

At any point in the second substate502b, the control stage102may transition the converter100to the second state504provided that one or more of two conditions is met. In the second substate502bof the first state502, the control stage102monitors the resonant capacitance voltage and the tank current. Further, the control stage102identifies whether either one of two conditions are met based at least in part on monitoring the resonant capacitance voltage and the tank current. The first condition is met when the resonant capacitance voltage is below the first threshold. The second condition is met when the tank current is at or above 0 A.

The control stage102transitions the converter100to the second state504on a condition that at least one of the two conditions is met (i.e., the resonant capacitance voltage is below the first threshold and/or the tank current is at or above 0 A). The control stage102may retain the converter100in the first state502for any duration of time before transitioning the converter100out of the first state502and to the second state504when at least one of the two conditions is met. As described herein, in the second state504, both gate drive signals are deasserted and the transistors126,128are in the electrically non-conductive state.

The control stage102retains the converter100in the second state504for a second period of time (Tdead). The control stage102may include a timer and may initialize the timer upon transitioning the converter100to the second state504. The control stage102may measure, using the timer, the duration of time elapsing from initialization of the timer. When the duration of time reaches the second period of time, the control stage102transitions the converter100to the first substate506aof the third state506.

While the converter100is in the first substate506aof the first state502, the second gate drive signal is asserted and the second transistor128is closed. Further, the control stage102monitors the tank current. The control stage102determines whether two conditions are met. For a first condition, the control stage102monitors the tank current and determines whether the tank current is equal to or is greater than the tank current threshold. For example, the first condition is met if the tank current is equal to or is greater than 0 A. The second condition is a temporal condition. The control stage102monitors a time period elapsing from entry into the first substate506aof the third state506. The second condition is satisfied when the elapsed time is equal to or greater than the first period of time (Tmin).

When both conditions are met, the control stage102transitions the converter100to the second substate506bof the third state506. The controller converter100remains in the first substate506afor at least the first period of time. Use of the first substate506aensures that the converter100is in the third state506for at least the first period of time (Tmin) and that the converter100stays in, and does not transition out, of the third state506, until at least the first period of time (Tmin) has elapsed.

When the converter100is in the second substate506bof the third state506, the converter100may transition out of the third state506without a requirement that a minimum period of time has elapsed. In the second substate506bof the third state506, the control stage102monitors (or determines) the resonant capacitance voltage and the tank current. The control stage102causes the converter100to transition to the fourth state508on a condition that at least one of two conditions is met. The first condition is met when the resonant capacitance voltage exceeds the second threshold, and the second condition is met when the tank current is lower than the tank current threshold.

When the control stage102determines that at least one of the two conditions is met, the control stage102causes the converter100to transition to the fourth state508. In the fourth state both gate drive signals are deasserted and both transistors are in the open state. The control stage102retains the converter100in the fourth state for the second period of time (Tdead). The control stage102determines whether the second period of time (Tdead) has elapsed since the converter100transitioned to the fourth state. Once the control stage102determines that the second period of time has elapsed, the control stage102causes the converter100to transition to the first substate502aof the first state502.

Operating the converter100in accordance with the state diagram ofFIG. 5ensures that the converter100is retained in the first state502for at least the first period of time (Tmin). Further, the converter100transitions to the second state if a current condition of the converter100is met, even though the resonant capacitance voltage is not below the first threshold. In addition, the converter100is retained in the third state506for at least the first period of time (Tmin), and the converter100exits the third state506and transitions to the fourth state508if a current condition of the converter100is met, even though the resonant capacitance voltage has is not exceeded the second threshold. Accordingly, the two critical operating conditions for controlling the converter100are compensated for.

FIG. 6shows a signal diagram for operating the converter100in accordance with the state diagram ofFIG. 5. The first gate drive signal602, the second gate drive signal604, the first threshold606, the resonant capacitance voltage608, the tank current threshold610and the tank current612are shown inFIG. 5.

Initially, converter100is in the third state506, whereby the second gate drive signal604is asserted. At a first time instance614, the tank current612drops below the zero tank current threshold610. In response, the control stage102transitions the converter100to the fourth state508, where both the first and second gate drive signals602,604are deasserted. The converter100operates in the fourth state508for the second period of time. After the expiration of the second period of time, the control stage102transitions the converter to the first state502, where the first gate drive signal602is asserted.

The converter100remains in the first state502for at least the first period of time. After the first period of time expires and at a second time instance616, the resonant capacitance voltage608drops below the first threshold606. In response, the control stage102transitions the converter100to the second state504. The converter100remains in the second state504for the second period of time (Tdead). At a third time instance618, when the second period of time expires, the control stage102transitions the converter100to the third state506.