Facilitating communication between memory devices and CPUs

According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices.

TECHNICAL FIELD

The present disclosure relates generally to memory devices.

BACKGROUND

A memory board includes memory devices that can store data. In certain situations, a central processing unit (CPU) board may store and retrieve information (such as data or instructions) from the memory devices of the memory board. In these situations, the CPU board and the memory board should be compatible to store and retrieve data.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Overview

According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices.

DESCRIPTION

FIG. 1illustrates a system5that includes an example of an apparatus10with memory devices that may be used to store data. In the illustrated example, apparatus10is coupled to a central processing unit (CPU) board12and a clock source14of system5. In certain embodiments, CPU board12may be configured to communicate according to a first memory technology (a “CPU memory technology”). In certain embodiments, apparatus10comprises a circuit board20and one or more processors (such as one or more field programmable gate arrays (FPGAs))40and one or more memory devices42coupled to circuit board20. Memory devices42may be configured according to a second memory technology (a “memory device memory technology”). FPGA40may be configured to receive one or more messages conforming to the first memory technology, translate the messages from the first memory technology to the second memory technology, and provide the translated messages to the memory devices.

A memory technology may refer to features of a particular type of memory, such as dynamic random access memory (DRAM) or a static memory, for example, a synchronous static random access memory (SSRAM). Different memory technologies of different types of memory may have certain features that differ, while other features may be the same. Examples of features include data transfer rates, bandwidth, and clock frequency. Different memory technologies may be governed by different standards. For example, JEDEC Solid State Technology Association (formerly known as the Joint Electron Devices Engineering Council (JEDEC)) may have one standard for one memory technology and another standard for another memory technology.

In certain embodiments, the CPU memory technology may be an older (or newer) memory technology, and the memory device memory technology may be a newer (or older) memory technology. For example, the CPU memory technology may be single data rate synchronous dynamic random access memory (SDR SDRAM) memory technology, and the memory device memory technology may be double data rate synchronous dynamic random access memory (DDR SDRAM) memory technology.

System5may be implemented in any suitable environment. For example, system5may be implemented in a device such as communication switch. CPU board12may operate as a supervisor board of system5, and apparatus10may store information, such as data or instructions, for CPU board12. Any suitable signals may be communicated between CPU board12and apparatus10. As an example, CPU board12may provide power to apparatus10. As another example, CPU board12may store information at apparatus10and/or retrieve information from apparatus10. As yet another example, CPU board12and apparatus10may communicate messages to each other. In some cases, CPU board12fetches instructions from apparatus10. In some cases, CPU board12may send memory control messages to FPGA40. In some cases, CPU board12and FPGA40may also communicate serial presence detect (SPD) messages (which may conform to the JEDEC standard) to each other. For example, the SPD value for the number of ranks may indicate whether apparatus10is working on a 512 MB or a 1 G mode. A number rank may be 2 in the 1 G mode and may be 1 in the 512 MB mode. As another example, the SPD value may indicate the memory technology used.

Clock source14may provide a common clock signal to CPU board and apparatus10. The clock may have any suitable frequency, such as a frequency having a value in the range of less than 100, 100 to 500, or greater than 500 megahertz (MHz). The clock from the source to CPU12and the clock from source to apparatus10may be length matched to data bits and other control signals.

In the illustrated example, apparatus10includes a circuit board20, an interface (IF)24, one or more voltage regulators26, a light emitting diode (LED)28, a serial programmable read only memory (SPROM)30, a Joint Test Action Group (JTAG) interface34, a field programmable gate array (FPGA)40, and one or more memory devices42coupled as shown. Memory devices42may be organized in any suitable manner. For example, at least a subset of memory devices42may be organized into one or more banks, where each bank comprises one or more memory devices42. In the illustrated example, memory devices42are grouped into devices42a,42b, and42c, where devices42aform bank A and devices42bform bank B and42cperforms error correcting code (ECC) operations for banks A and B.

In certain embodiments, circuit board20comprises any suitable substrate that is operable to support and couple components of apparatus10. Circuit board20may comprise one or more pieces. In certain embodiments, interface24may communicate with another interface conforming to a memory technology that differs from that of apparatus10. For example, interface24may communicate with an SDRAM interface of CPU board12.

In certain embodiments, voltage regulator26may be used to power FPGA40and memory devices42and may convert input voltage into output voltages that may be used by components of apparatus10. A regulator26may be used to translate the electrical interface voltage from the CPU memory technology to an electrical interface voltage supported by the memory device memory technology. For example, regulator26may provide voltages to convert an electrical interface of 3.3 volt (V) low-voltage transistor-to-transistor logic (LVTTL) to an electrical interface of 1.8 V low-voltage complementary metal oxide semiconductor (LVCMOS). In the illustrated example, voltage regulator26converts 3.3 volts to 1.8 volts, 1.2 volts, and 2.5 volts. In the example, memory devices42may use 1.8 volts, FPGA40may use 3.3 volts, 2.5 volts, 1.8 volts, and/or 1.2 volts, and SPROM30may use 3.3 volts.

In certain embodiments, LED28may be used to provide a debug indicator. In certain embodiments, LED28may blink to indicate the power supply is satisfactory, the module is out of reset mode, and/or the clock is running. In certain embodiments, SPROM30may be used to configure FPGA40. In certain embodiments, SPROM30may store the image of FPGA40.

A memory device42may comprise any suitable device configured to store data, such as a DDR SDRAM, for example a Mobile DDR SDRAM (MDDR SDRAM) or a small outline dual in-line memory module (SO-DIMM). Memory devices42may have any suitable speed grade (for example, a speed grade with a value in the range of less than 100, 100 to 200, or greater than 200 MHz) and have any suitable burst length (for example, a burst length of 2). Memory devices42may have any suitable memory capacity, for example, a capacity with a value in the range of less than 512 MB, 512 MB to 1 G, or greater than 1 G.

A memory device42may have any suitable specifications. In certain examples, a memory device42may have a bidirectional data strobe signal (DQS), differential clock inputs, an LVCMOS 1.8 volt compatible input, a DDR data bus, a burst length of 2, and/or programmable drive strengths. Data may be stored at memory devices42in any suitable manner. An example of a technique for storing data is described in more detail with reference toFIG. 3.

In certain embodiments, FPGA40may be configured to receive one or more messages conforming to the CPU memory technology, translate the messages from the CPU board technology to the memory device memory technology, and provide the translated messages to memory devices42. FPGA40may translate any suitable messages, for example, memory commands, such as memory read, write, and/or refresh commands. In certain embodiments, CPU memory technology messages may be blocked and equivalent memory device memory technology messages may be issued. For example, in certain situations the initiation procedure and mode register command rights are different for the memory technologies. At start up of the board, FPGA40may block the CPU memory technology commands and then issue equivalent memory device memory technology commands.

FPGA40may translate between features that differ between CPU board12and apparatus10. Examples of features that may differ include memory interface protocols, the number of address bits for columns, mode register fields, support for adjustment of drive strengths, minimum burst length, electrical interface voltage, or other feature. In certain embodiments, FPGA40may be configured to translate timing of the CPU memory technology to timing of the memory device memory technology. The cycles may be translated such that the read and/or write latency is the same as for the first memory technology. In certain embodiments, apparatus10may perform the translations with software transparency, that is, no software changes are required to perform the translations.

In certain embodiments, FPGA40may be configured to stripe data onto the one or more memory devices. Data striping involves segmenting logically sequential data, such as a single file. The segments may be assigned to different physical devices in a round-robin fashion. In certain embodiments, FPGA40may be configured to select a first memory device of the one or more memory devices to store first data and select a second memory device of the one or more memory devices to store second data. In certain other embodiments, FPGA40may embed redundancy into striping, which may yield higher reliability for data stored on apparatus10.

In certain embodiments, FPGA40may be configured to implement a serial presence detect (SPD) feature. In certain embodiments, the SPD feature may identify the technology of memory devices42to CPU board12, and inform CPU board12of timing to use to access memory devices42.

FIG. 2illustrates an example of a layout that may be used for apparatus10. In the example, apparatus10includes end terminations50(50a-b), memory devices42a,42b, and42c, data busses56(56a-d), an addresses bus54, FPGA40, signal fan-out58, and PCB edge connector60coupled as shown. A termination50may be an external bus termination. In certain embodiments, apparatus10may have external die terminations and no on-die terminations, which may reduce power. Address bus54specifies an address of a memory location for reading or writing. A data bus56transfers data. Fan-out58and edge connector60may have a pin-out that matches the pin-out of CPU12. For example, the pin-out may given by the JEDEC Standard (JESD) 21-C specification for the SDRAM144pin SO-DIMM module. In certain embodiments, edge connector60may be located on CPU board12.

FIG. 3illustrates an example data flow that may be used for apparatus10. Memory devices42may have any suitable memory data width, for example, a width with a value in a range of 8 to 32 or greater than 32 bits. In the illustrated example, memory devices42may have a memory data width of 16 bits. The burst may be configured for any suitable cycle. In the illustrated example, the burst is configured at 2 (a two beat cycle) to push/pull 32 bit data at each access. Bits may be striped in any suitable manner. In the illustrated example, 32 bits of the most significant bits are striped to bank A42a, and 32 bits of the least significant bits are striped to bank B42b. Eight bits of error-correcting code (ECC) are striped to memory device42c.

FIG. 4illustrates an example of data striping that may be used with apparatus10. Bits may be striped in any suitable manner. The illustrated example shows one of two sets of busses. CS0and CS1are SDRAM side chip selects. In the illustrated example, SDRAM side D0-D31stripes to memory devices U4, U14, U5, U13. SDRAM side D32-D63stripes to MDDR memory devices U1, U16, U2, U15. SDRAM side D64-D71stripes to MDDR memory device U3.

Modifications, additions, or omissions may be made to the systems and apparatuses disclosed herein without departing from the scope of the invention. The components of the systems and apparatuses may be integrated or separated. For example, the components of apparatus10may be located on one or more boards20. Moreover, the operations of the systems and apparatuses may be performed by more, fewer, or other components. For example, the operations of a memory device40and SPROM30may be performed by one component, or the operations of FPGA40may be performed by more than one component. Additionally, operations of the systems and apparatuses may be performed using any suitable logic comprising software, hardware, and/or other logic. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

A component of the systems and apparatuses disclosed herein may include an interface, logic, memory, and/or other suitable element. An interface receives input, sends output, processes the input and/or output, and/or performs other suitable operation. An interface may comprise hardware and/or software.

Logic performs the operations of the component, for example, executes instructions to generate output from input. Logic may include hardware, software, and/or other logic. Logic may be encoded in one or more tangible media and may perform operations when executed by a computer. Certain logic, such as a processor, may manage the operation of a component. Examples of a processor include one or more computers, one or more microprocessors, one or more applications, and/or other logic.

In particular embodiments, the operations of the embodiments may be performed by one or more computer readable media encoded with a computer program, software, computer executable instructions, and/or instructions capable of being executed by a computer. In particular embodiments, the operations of the embodiments may be performed by one or more computer readable media storing, embodied with, and/or encoded with a computer program and/or having a stored and/or an encoded computer program.

A memory stores information. A memory may comprise one or more non-transitory, tangible, computer-readable, and/or computer-executable storage media. Examples of memory include computer memory (for example, Random Access Memory (RAM) or Read Only Memory (ROM)), mass storage media (for example, a hard disk), removable storage media (for example, a Compact Disk (CD) or a Digital Video Disk (DVD)), database and/or network storage (for example, a server), and/or other computer-readable medium.

Components of the systems and apparatuses disclosed herein may be coupled by any suitable communication network. A communication network may comprise all or a portion of one or more of the following: a public switched telephone network (PSTN), a public or private data network, a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), a local, regional, or global communication or computer network such as the Internet, a wireline or wireless network, an enterprise intranet, other suitable communication link, or any combination of any of the preceding.