Holdup time measurement for solid state drives

In one embodiment, a solid state drive (SSD) with power loss protection (PLP) includes a SSD controller, a secondary controller and a power circuit configured to supply power to the SSD from a power source during normal operation and backup power from a backup power source in response to a loss of power supplied by the power source. In the event of a loss of power, the secondary controller is configured to track the holdup time, or duration of time for which the primary controller can operate on backup power. In one embodiment, the holdup time tracked by the secondary controller is stored in a non-volatile memory in communication with the secondary controller.

FIELD OF THE INVENTION

This invention generally relates to measurement of holdup time during power loss protection (PLP) for solid state drives (SSDs).

BACKGROUND OF THE INVENTION

SSDs achieve much of their performance by maintaining critical data structures in volatile memory, which allows quick access during runtime. Use of volatile memory during runtime presents a problem if power is suddenly lost as volatile memory depends upon being powered to store and maintain the data in memory. Upon the loss of power to a volatile memory, the data stored in volatile memory will be lost. Accordingly, it is necessary to save critical data structures stored in volatile memory to non-volatile memory before power to the SSD falls below a threshold required for SSD operation. To address this issue, many SSDs include capacitors with high capacitance (e.g., supercapacitors, tantalum capacitors, etc.) to provide backup power for a short period of time after the loss of power. The use of a backup power source in an SSD helps prevent data loss due to a power outage or power loss. This feature is generally referred to as power loss protection (PLP).

When a power outage or power loss occurs for a host device (e.g., a computer) with an SSD, the energy stored by the supercapacitor provides backup power for a short time for the SSD to complete pending commands, save critical data and shut down properly. Without this, the SSD may not initialize properly for a subsequent boot. For example, if the volatile memory loses critical data such as the logical to physical mapping table of data (i.e., a table storing the mapping between the logical address used by the host to refer to data and the address at which data is physically located within non-volatile memory), the SSD may be unusable or may require a long data structure rebuild that requires the SSD to scan the entire drive and determine where data is located.

When an SSD with PLP is unable to save critical data to non-volatile memory, there are two possible failures that could have occurred. Either the SSD firmware failed to complete the power loss procedure while operating on backup power (e.g., procedure failed to start) or the backup power source was unable to provide power long enough for the SSD firmware to complete the power loss procedure. To identify the cause of the failure that resulted in the loss of critical data from volatile memory, it is necessary to identify how long the SSD was able to properly operate after loss of power.

One technique for measuring the duration of SSD operation on backup power measures the time from detecting a loss of power to when the SSD firmware power loss procedure completes. This technique is not achievable. If the SSD firmware logs completion of the power loss procedure, the procedure will have completed successfully and the drive will restart normally. If the SSD firmware fails to complete the power loss procedure, the duration of SSD operation on backup power will not be logged.

Another problem with using the SSD to measure the duration of SSD operation is that the SSD itself is not capable of identifying the moment at which it can longer operate as the SSD will have stopped operating at that point in time. As such, it is not possible to log an unsuccessful power loss procedure.

Accordingly, there is an unmet demand for SSDs with PLP that can efficiently and reliably measure the duration of SSD operation on backup power to identify the cause of an improper SSD shut down.

BRIEF DESCRIPTION OF THE INVENTION

In one embodiment, an SSD with PLP includes a primary controller operable at a first voltage, a secondary controller operable at a second voltage that is less than the first voltage, and a power circuit. The power circuit is configured to supply power to the primary controller and the secondary controller from a power source during normal operation of the SSD and from a backup power source in response to a loss of power supplied by the power source. The secondary controller is further configured to track a time from the loss of power supplied by the power source to a reset of the primary controller.

In one embodiment a host device comprises the power source that supplies power to the primary controller and the secondary controller during normal operation of the SSD. In another embodiment a capacitor or a battery comprises the backup power sources that supplies power to the SSD in response to a loss of power supplied by the power source during normal operation.

In one embodiment, the loss of power is detected when the power supplied by the power source during normal operation has fallen below a first predefined threshold. Further, the reset of the primary controller occurs in response to the backup power source falling below a second predefined threshold. In one embodiment, the secondary controller is configured to detect the power source falling below the first predefined threshold and the backup power source falling below the second predefined threshold.

In one embodiment, the secondary controller includes a timer to track the time from the loss of power supplied by the power source to a reset of the primary controller. In one embodiment, the secondary controller is configured to track the time by causing a bit to be stored at predefined time intervals in a non-volatile memory in communication with the secondary controller. In one embodiment, the secondary controller is configured to cause the time to be stored in the non-volatile memory at predefined time intervals.

In one embodiment, the primary controller is configured to transfer critical information from a volatile memory in communication with the primary controller to a non-volatile memory in communication with the primary controller. In on embodiment, the critical information transferred from the volatile memory to the non-volatile memory is a logical to physical address update log.

In one embodiment, a non-volatile memory is a component of the secondary controller.

In one embodiment, a method of PLP for an SSD includes supplying power from a power source during normal operation of the SSD and from a backup power source in response to a loss of power supplied by the power source. The method further includes supplying power to a primary controller operable at a first voltage, a secondary controller operable at second voltage that is less than the first voltage, and a non-volatile memory in communication with the secondary controller. The method further includes tracking a time from the loss of power to a reset of the primary controller.

In one embodiment, the method includes supplying backup power from a capacitor or a battery. In one embodiment, the method includes detecting the power source falling below a first predefined threshold. In one embodiment, the method includes detecting the backup power source falling below a second predefined threshold.

In one embodiment, the method includes storing an indication of the tracked time at predefined time intervals. In one embodiment, the method includes storing critical information in response to the loss of power in a second non-volatile memory in communication with the primary controller. In one embodiment, the method includes storing an L2P update log in response to the loss of power.

In one embodiment, the method includes storing the tracked time after regaining power from the power source.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1. is a block diagram illustrating one embodiment of an SSD with PLP100. SSD controller101communicates with non-volatile memory103through connection137and volatile memory105through connection135. Non-volatile memory103can be, but is not limited to, an EEPROM, NAND, NOR, MRAM, PCM, PCME, PRAM, PCRAM, PMC, RRAM, NRAM, Ovonic Unified Memory, Chalcogenide Ram and/or C-RAM, or any other type of non-volatile memory known in the art, and volatile memory105can be, but is not limited to, DRAM, SRAM, T-RAM, Z-RAM and/or any other type of volatile memory known in the art. SSD controller101stores and retrieves data from the volatile memory105during normal operation to allow quick access of data during run time. SSD controller101may periodically store data in the non-volatile memory103as well.

During normal operation, a host interface109supplies power to the other devices of SSD with PLP100. Host interface109transfers power over a connection123to a power fail switch111. Power fail switch111may be an electromechanical switch, a switching circuit composed of transistors or MOSFETs or any other type of switch known in the art. Power fail switch111transfers power from the host interface109to a power monitor113over a connection141. Power monitor113includes a number of voltage regulators (not shown) that regulate the power received from host interface109to emit regulated voltages for each of the devices of the SSD with PLP100, including a regulated voltage127for volatile memory105, a regulated voltage125for non-volatile memory103, a regulated voltage129for SSD controller101and a regulated voltage131for a secondary controller131. Power monitor113and power fail switch111can be implemented as part of a power circuit.

Power monitor113monitors the power supplied by connection141to determine if a loss of power occurs that may cause a loss of regulated voltages125,127,129and131. A loss of power from the host interface109may occur for a number of reasons, including, for example, removal of the SSD from the system during operation, a hardware failure, loss of electrical power to the host device due to a power outage, or a large load on the host device that causes a temporary drop out in the power supplied from host interface109. A loss of power may be detected by determining that the power supplied by connection141falls below a predefined threshold (e.g., 5 volts) for a predefined period of time (e.g., 5 milliseconds). Alternatively, it may be desirable to use only a predefined voltage threshold for detecting a loss of power as some applications may require detecting an instantaneous loss of power. When power monitor113detects a loss of power, power monitor113immediately emits a Supercap Enable signal to enable backup power to be supplied from a supercapacitor115and emits a PFAIL signal117identifying the loss of power to the SSD controller101and the secondary controller107. Supercapacitor115supplies backup power to power monitor113through connection141.

Upon receiving the PFAIL signal117, the SSD controller101ceases normal operation and begins performing a power loss procedure to process pending commands and save critical data structures to non-volatile memory103before power is lost to SSD controller101and/or volatile memory105. The power loss procedure may comprise various steps. SSD controller101may be programmed to acknowledge the completion of each step of the power loss procedure by sending a signal via a communication channel139to the secondary controller107. Upon receiving PFAIL signal117, the secondary controller immediately starts a timer

The SSD with PLP100is capable of switching to the backup power source, supercapacitor115, within a short period of time after detecting a loss of power from host interface109. Depending on the components used, switching may be accomplished as quickly as a few microseconds or even nanoseconds, resulting in no perceptible change to regulated voltages125,127,129and131. With the supply of backup power, the charge accumulated within supercapacitor115will decline in relation to a load presented by the components of SSD with PLP100. Typically, the size or value selected for supercapacitor115powers the SSD with PLP100for a sufficient duration of time that allows SSD controller101to complete its power loss procedure. If the size or value selected for supercapacitor115is too small, the voltage of supercapacitor115may drop below the threshold for maintaining regulated voltages125,127or129. If regulated voltages125,127or129lose regulation SSD controller101, non-volatile memory103and/or volatile memory105may stop functioning before the SSD controller101can complete its power loss procedure. However, even if the size or value selected for supercapacitor115is correct, it is also possible that a hardware issue may cause supercapacitor115to malfunction.

Power monitor113monitors the connection141to determine when the voltage supplied by supercapacitor115drops below a predefined threshold that represents the minimum regulated voltage at which SSD controller101can continue to operate. When power monitor113detects the voltage of supercapacitor115falls below the threshold voltage, power monitor113emits RESET signal121to SSD controller101, which is also monitored by secondary controller107. RESET signal121causes the SSD controller101to cease all operations and shut down prior to regulated voltage129dropping below the minimum operable voltage of SSD controller101.

When secondary controller107receives PFAIL signal117, the secondary controller107starts a timer to track holdup time or the duration of time for which the SSD controller101can operate on backup power supplied by the backup power source, supercapacitor115.

In one embodiment, the timer of secondary controller107can be a 200 Hz clock signal having a period of 5 ms from one rising edge to another (i.e., predefined interval or period of the clock signal). Each time 5 ms elapses (i.e., on each rising or falling edge) the secondary controller107tracks the holdup time by transmitting a HOLDUP TIME signal119to a second non-volatile memory143causing the second non-volatile memory143to store a holdup time bit (i.e., “0” or “1”). Second non-volatile memory143can be, but is not limited to, an EEPROM, NAND, NOR MRAM, PCM, PCME, PRAM, PCRAM, PMC, RRAM, NRAM, Ovonic Unified Memory, Chalcogenide Ram and/or C-RAM, or any other type of non-volatile memory known in the art. If the SSD controller101sent an acknowledgement to the secondary controller107indicating the completion of a particular step of the power loss procedure, the secondary controller107can also cause the acknowledgement to be stored in the second non-volatile memory143When the secondary controller107receives RESET signal121, the timer stops and the total number of holdup time bits stored in the second non-volatile memory143represents the holdup time of SSD controller101during backup power. For example, if the timer of secondary controller107is a 200 Hz clock signal and 20 holdup time bits are stored in non-volatile memory, the holdup time bits indicate that the SSD controller101operated for a holdup time of 100 milliseconds.

In another embodiment, when the secondary controller107receives PFAIL signal117, the secondary controller107erases a portion of the second non-volatile memory143by setting all bits in the portion of memory to a single value (e.g., “1” or “0”). The secondary controller107also starts a timer to track holdup time or the duration of time for which the SSD controller101can operate on backup power supplied by the backup power source, supercapacitor115.

For example, in one embodiment, the secondary controller107can erase a 32-byte page in secondary non-volatile memory143(e.g., an EEPROM) by setting all bits to a value of “1.” Accordingly, each byte of the 32-byte page will have 8 bit set to a value of “1.” The timer of secondary controller107can be a 200 Hz clock signal having a period of 5 ms from one rising edge to another (i.e., predefined interval or period of the clock signal). Each time 5 ms elapses (i.e., on each rising or falling edge) the secondary controller107transmits a HOLDUP TIME signal119to the second non-volatile memory143causing the second non-volatile memory143to transition a bit in the 32-byte page from a “1” to a “0.” After 40 ms, the secondary controller107will have transitioned all 8 bits in the first byte of the 32-byte page from a “1” to a “0,” causing the secondary controller107to start transitioning bits in the next byte of the 32-bye page in second non-volatile memory143during subsequent cycles of the 5 ms timer. If the SSD controller101sent an acknowledgement to the secondary controller107indicating the completion of a particular step of the power loss procedure, the secondary controller107can also cause the acknowledgement to be stored in the second non-volatile memory143. When the secondary controller107receives RESET signal121, the timer stops and the total number of “0” bits stored in the 32-byte page of the second non-volatile memory143represents the holdup time of SSD controller101during backup power. For example, if the timer of secondary controller107is a 200 Hz clock signal and 83 “0” bits are stored in the 32-byte page (i.e., 10-bytes storing 8 “0” bits and an 11th-byte storing 3 “0” bits) of the second non-volatile memory143, the holdup time bits indicate that the SSD controller101operated for a holdup time of 415 milliseconds. Second non-volatile memory143can be, but is not limited to, EEPROM, NAND, NOR, MRAM, PCM, PCME, PRAM, PCRAM, PMC, RRAM, NRAM, Ovonic Unified Memory, Chalcogenide Ram and/or C-RAM, or any other type of non-volatile memory known in the art.

In another embodiment, when secondary controller107receives PFAIL signal117, a timer starts to track the duration of time for which the SSD controller101can operate on backup power. Secondary controller107periodically transmits HOLDUP TIME signal119to store the current holdup time in the second non-volatile memory143. A separate signal operates within the secondary controller107and initiates the transmission and storage of the holdup time each time a predefined interval elapses. For example, if a 200 Hz clock signal is used, every 5 ms (i.e., predefined interval or period of the clock signal) the secondary controller107transmits HOLDUP TIME signal119to store the measured holdup time in second non-volatile memory143. After 5 ms, the value stored in non-volatile memory is 5 ms, after 10 ms, the value stored in non-volatile memory is 10 ms, etc. The benefit to this approach is that the latest measurement of holdup time is always stored in the second non-volatile memory143and does not need to be calculated as in the case of tracking the holdup time by storing bits (described above). However, this approach requires more free memory than storing bits as the measured holdup time is stored at predefined intervals.

If the SSD controller101is unable to complete the power loss procedure during backup power, the holdup time stored in non-volatile memory103indicates the duration of time for which SSD controller101operated on backup power and the acknowledgement stored in the second non-volatile memory143identifies the last step of the power loss procedure completed by SSD controller101. When the SSD with PLP100regains power, the SSD controller101sends a signal over communication channel145to the secondary controller107requesting that the secondary controller107return the holdup time and/or acknowledgements. If the holdup time was tracked by storing holdup time bits in the second non-volatile memory143, the secondary controller107calculates the holdup time and transmits the calculated holdup time to the SSD controller101over communication channel145along with any acknowledgements. If the holdup time was tracked by storing the holdup time at predefined intervals, the secondary controller107retrieves the last holdup time and returns the holdup time to the SSD controller101over communication channel145along with any acknowledgements. When the SSD controller101receives the holdup time and/or acknowledgments from the secondary controller107, the SSD controller101stores the information in an operational log.

Preferably, secondary controller107and second non-volatile memory143operate at voltages that are lower than the minimum operable voltage of the SSD controller101. Accordingly, secondary controller107and second non-volatile memory143will continue to operate on the backup power provided by supercapacitor115for a period of time after SSD controller101received the RESET signal121.

The embodiment ofFIG. 1does not require that the power monitor113detects the loss of power and emits PFAIL signal117and RESET signal121. This functionality can be incorporated in the secondary controller107. Secondary controller107can monitor power from the host interface109and when the secondary controller107detects a loss of power, the secondary controller107can emit the PFAIL signal117to the SSD controller101and the Supercap Enable signal to the power fail switch111. When the backup power voltage drops below a predefined threshold, the secondary controller107can emit the RESET signal121to shut down the SSD controller101before the regulated voltage129drops below a threshold representing the minimum operable voltage of the SSD controller101. Alternatively, the SSD controller101could monitor power from the host interface109and when a loss of power is detected, the SSD controller101could immediately begin performing its power loss procedure. The SSD controller101could further notify the secondary controller107of the detected power loss by emitting PFAIL signal117and could cause the power fail switch111to switch to supercapacitor115by emitting the Supercap Enable signal.

Although the embodiment ofFIG. 1describes the backup power source as a supercapacitor, any type of power source can be used, including tantalum capacitors or a battery.

In another embodiment, second non-volatile memory143can be an internal component of secondary controller107. In this embodiment, HOLDUP TIME signal119would be an internal signal of secondary controller107to communicate with the second non-volatile memory143. In another embodiment, non-volatile memory103can be used by the secondary controller107to store the tracked holdup time and/or acknowledgements, eliminating the need for second non-volatile memory143. If only a single non-volatile memory is used, secondary controller107writes the tracked holdup time and/or acknowledgements directly to non-volatile memory103via HOLDUP TIME signal119. In this embodiment, it may be preferable to have a dedicated partition in non-volatile memory103for secondary controller107to write the tracked holdup time and/or acknowledgements. Further, in this embodiment, non-volatile memory103preferably operates at voltage that is lower than the minimum operable voltage of the SSD controller101so that the non-volatile memory103continues to operate on backup power for a period of time after SSD controller101received RESET signal121. If non-volatile memory103is a NAND flash memory, it may be desirable to have a second non-volatile memory143that is an EEPROM, NOR flash memory or equivalent to write the tracked holdup time and/or acknowledgements. Repeatedly performing erase and write operations to a page of NAND flash memory is inefficient and can result in damaging the page in memory.

FIG. 2. is a timing diagram of one embodiment of an SSD with PLP, as described above, having a backup power source115, a power circuit (comprised of a power fail switch111and a power monitor113), a primary controller101and a secondary controller107. During normal operation a host interface109provides power to the SSD with PLP. A HOST PWR signal201monitors the power provided by the host interface109and a BACKUP PWR signal209monitors the charge accumulated within the backup power source115. During normal operation the host interface109(or any other power source available during normal operation) supplies power to the supercapacitor115. During normal operation there is no load on the backup power source115, which allows the accumulated charge on the backup power source115to remain substantially constant (represented by the constant portion of BACKUP PWR signal209). During normal operation, the primary controller101performs read and write operations to a volatile memory105(represented by rising and falling edges of SSD READ/WRITE signal215).

The power circuit causes a BACKUP ENABLE signal207to transition from high to low if the power circuit detects that the power provided by the host interface109falls below a predefined threshold203(represented by falling edge of signal201crossing threshold203). When BACKUP ENABLE signal207transitions from high to low, the backup power source115(e.g., supercapacitor, battery, or other backup powers source) is enabled. When power from the host interface109falls below a predefined threshold203, SSD with PLP also causes a PFAIL signal205to transition from high to low. In response to signal207transitioning from high to low, the backup power source115begins to power the SSD with PLP and the charge accumulated in the backup power source115begins to decline in proportion to the load presented by the SSD with PLP (represented by the declining portion of signal209).

Further, in response to PFAIL signal205transitioning from high to low, the primary controller101begins a power loss procedure to complete pending commands and save critical data structures from volatile memory105to non-volatile memory103. When PFAIL signal205transitions from high to low, SSD with PLP does not accept further read or write commands from the host interface109. Additionally, in response to PFAIL signal205transitioning from high to low, the secondary controller107starts a timer, represented by a HOLDUP CLK signal219, to measure the duration of time for which the primary controller101can operate on backup power supplied by the backup power source115.

When HOLDUP CLK signal219begins oscillating, the primary controller101may send an acknowledgement bit to the secondary controller107through a signal145, which the secondary controller107then writes to a second non-volatile memory143confirming that the secondary controller107started tracking the holdup time (represented by the first high to low to high transition of PLP ACK signal217). Each time the primary controller101completes a step of the power loss procedure another acknowledgement may be sent to the secondary controller107and stored in second non-volatile memory143. For example, the secondary controller107may store an acknowledgement bit in the second non-volatile memory143(represented by the second high to low to high transition of PLP ACK signal217) when the SSD controller101stores critical data structures from volatile memory105to non-volatile memory103. The primary controller101sends another acknowledgement bit to the secondary controller107to be stored in second non-volatile memory143(represented by the third high to low to high transition of PLP ACK signal217) when the SSD controller101completes pending read/write commands (represented by the constant portion of SSD READ/WRITE signal215).

Each time HOLDUP CLK signal219transitions from high to low, the secondary controller107tracks the holdup time by storing a holdup time bit223in second non-volatile memory143(i.e., a “0” bit is stored).

When the backup power voltage falls below a predefined threshold211(represented by BACKUP PWR signal209crossing threshold211) the SSD with PLP causes a RESET signal213to transition from high to low. Predefined threshold211represents the minimum regulated voltage at which the primary controller101can operate. Upon the transition of the RESET signal213from high to low the primary controller101ceases all functions and powers down and the HOLDUP CLK signal219of the secondary controller107stops oscillating. Once HOLDUP CLK signal219stops oscillating, further holdup time bits223will not be stored by the secondary controller107to second non-volatile memory143. Thus, HOLDUP CLK signal219starts oscillating when HOST PWR signal201crosses threshold203and stops oscillating when BACKUP PWR signal209crosses threshold211, effectively tracking the duration of time that the primary controller101operated on backup power. If the HOLDUP CLK signal219transitions from high to low twenty times, twenty holdup time bits223(represented by “0”s) are stored by the secondary controller107in second non-volatile memory143. If HOLDUP CLK signal219is a 200 Hz signal having a period of 5 ms (i.e., predefined interval or period of the clock signal), the holdup time measured by HOLDUP TIME signal221is 100 ms.

If the primary controller101is unable to complete the power loss procedure during backup power, HOLDUP TIME signal221tracks the duration of time for which the primary controller101operated on backup power and PLP ACK signal217identifies the last step of the power loss procedure completed by the primary controller101.

Although the timing diagram ofFIG. 2describes various steps occurring as a result of the signals transitioning from high to low (i.e., as a result of a falling edge of a signal), in an alternative implementation the various steps may occur as a result of the signals transitioning from low to high (i.e., as a result of a rising edge of a signal), or a combination of signals transitioning from low to high and high to low.

In another embodiment, second non-volatile memory143can be an internal component of secondary controller107. In another embodiment, non-volatile memory103can be used by the secondary controller107to store the tracked holdup time and/or acknowledgements, eliminating the need for second non-volatile memory143.

FIG. 3is a block diagram of one embodiment of an SSD with PLP300during normal operation. A volatile memory303is used for the temporary storage of commands and data that is being processed by an SSD Controller301. The SSD controller301stores in volatile memory303a command queue303acontaining incoming commands from a host interface309, a logical to physical address translation table, or L2P table303b, and a log of updates to be applied to the L2P table, or L2P update log303c. The volatile memory303can comprise DRAM, SRAM, T-RAM, Z-RAM and/or any other type of volatile memory known in the art.

SSD controller301also communicates with a non-volatile memory305, which is typically an array organized in banks of non-volatile memory devices311a-d,313a-d,315a-d, and317a-d, which provide permanent or long-term storage for the data. The non-volatile memory devices311a-d,313a-d,315a-b, and317a-bcan comprise, NAND flash memory, NOR flash memory, an EEPROM or any other non-volatile memory known in the art in any combination.

The SSD controller301temporarily buffers commands347received from the host interface309in a command queue303ain the volatile memory303. When the SSD controller301executes a command347received from the host interface309, the SSD controller301returns an acknowledgement, ACK signal345, to the host interface309. If the command347is a read command, the SSD controller301does not issue an acknowledgement, ACK signal345, until the read command is performed and the data is returned to the host interface309. If the command347is a write command, the SSD controller301may issue the ACK345signal as soon as the command is stored in the command queue303a, on the assumption that the command will be processed and the data will be stored in non-volatile memory305. When the SSD controller301sends an acknowledgement to the host interface309for a write command that has not yet been executed, the SSD controller301updates the command queue303ain the volatile memory303to indicate that an acknowledgement was sent (represented by assigning an ACK value of “1” in command queue303a). If a write command is acknowledged before it is written to the non-volatile memory305, the data for the write command is critical information if there is a loss of power, as the host interface309thinks the write command was executed by the SSD controller301. If the write command is not executed by the SSD controller301before a loss of power, when the host interface309requests that data upon a subsequent power-up, out of date or incorrect data may be returned by the SSD controller301.

The SSD controller301processes the commands in the command queue303aand the data is read from and written to the non-volatile memory305using multiple memory data channels321,323,325and327. In other embodiments, the non-volatile memory305may comprise any number of channels (i.e., 1 or more). Each channel is controlled independently by a channel controller301a,301b,301cand301dwithin the SSD controller301, and each channel controller communicates with a corresponding subset of the non-volatile memory devices311a-d,313a-d,315a-d, and317a-d. Within each channel controller301a-d, there is a channel command queue331,333,335and337. Within each channel command queue331,333,335and337, there may be a different mixture of memory commands directed to the corresponding non-volatile memory devices, including read (represented by “R”), write/program (represented by “P”) and erase (represented by “E”).

Similarly, secondary controller307includes a channel controller307athat allows the secondary controller307to write to non-volatile memory devices355a-dof second non-volatile memory353through a communication channel351. The non-volatile memory devices355a-dcan comprise, NAND flash memory, NOR flash memory, an EEPROM or any other non-volatile memory known in the art in any combination.

The L2P table303bis a table that identifies the logical location of a data block that is understood by the host interface309(i.e., the logic block address provided by commands347from the host interface309) and the location where the data is physically stored in the non-volatile memory305(i.e., expressed by non-volatile memory device, block number, page number and offset within the page). The SSD controller301periodically stores copies of the L2P table303bin the non-volatile memory305to ensure the data is available if the SSD controller301and/or volatile memory303unexpectedly lose power and power down. However, the SSD controller301primarily uses and updates the L2P table303bstored in volatile memory303for fast and convenient access. Upon power-up, the SSD controller301copies the L2P table303afrom non-volatile memory305to volatile memory303.

The L2P Table303bmust be continuously updated as new or updated data is written to the non-volatile memory305. In order to maintain good write performance, the SSD controller301does not update the copy of the L2P table303astored in non-volatile memory305every time new data is written to non-volatile memory305as this requires additional processing that causes the SSD with PLP300to operate slowly and inefficiently. Instead, the SSD controller301maintains the newly written data in an L2P update log303cthat identifies newly written data since the last update of the L2P table303astored in non-volatile memory305. In normal operation when the L2P update log303creaches a threshold requirement, which may be based on the amount of memory available to store the L2P update log303c(e.g., the number of entries in the L2P update log303cand/or duration of time since the last L2P update log303cwas saved), the SSD controller301may update any copies of L2P table303bin non-volatile memory305(not shown). In an alternative embodiment, L2P update log303cis used to update any copies of the L2P table303bin non-volatile memory305(not shown) at predefined intervals. Performing these updates at predefined intervals ensures that a large sequence of L2P write activity does not cause the L2P update log303cto exceed the amount of memory available to store the L2P update log303cin volatile memory303. The periodic updating of the L2P tables (in volatile and non-volatile memory) means that at the instant when a power failure occurs, the L2P tables in non-volatile memory305may be missing the latest updates from the L2P update log303c. Accordingly, the L2P update log303cis also considered critical information that should be written to the non-volatile memory305if there is a loss of power.

FIG. 4is a block diagram of another embodiment of an SSD with PLP400during a loss of power. A power monitor449is configured to detect a loss of power provided to the SSD with PLP400from a host interface409. A loss of power from host interface409may occur for a number of reasons, including, for example, removal of the SSD from the system during operation, a hardware failure, loss of electrical power to the host device due to a power outage, or a large load on the host device that causes a temporary drop out in the power supplied by the host device. Power monitor449may detect a loss of power by detecting that the power supplied by host interface409falls below a predefined threshold (e.g., 5 volts) for a predefined period of time (e.g., 5 milliseconds). Alternatively, it may be desirable to use only a predefined voltage threshold for detecting a loss of power as some applications may require detecting an instantaneous loss of power. When power monitor449detects a loss of power, it immediately emits a PFAIL signal439identifying the loss of power to the SSD controller401and the secondary controller407. Power monitor449also enables a backup power source (not shown), which provides backup power to SSD with PLP400. Alternatively, either SSD controller401or secondary controller407may enable the backup power source (not shown) in response to receiving PFAIL signal407.

Power monitor449also monitors the backup power source. When power monitor449detects the voltage of the backup power source fall below a threshold voltage (i.e., the minimum voltage at which SSD controller401can continue to operate) power monitor449emits a RESET signal441to SSD controller401, which is also monitored by secondary controller407. RESET signal441causes the SSD controller401to cease all operations and shut down prior to SSD controller101losing power. Preferably, secondary controller407and second non-volatile memory453operate at voltages that are lower than the minimum operable voltage of the SSD controller401. Accordingly, secondary controller407and second non-volatile memory453will continue to operate on backup power for a period of time after SSD controller401received the RESET signal421.

Upon receiving the PFAIL signal439, the SSD controller401ceases normal operation and begins performing a power loss procedure to process pending commands and save critical data structures to non-volatile memory405before backup power is lost to SSD controller401and/or volatile memory403. Pending commands in channel command queues431,433,435and437(e.g., read, write/program, and erase commands, not shown) are not changed or stopped by the SSD controller401. Since the backup power source continues to power non-volatile memory405, the pending commands in channel command queues431,433,435and437are executed. In another embodiment, all read commands in channel command queues431,433,435and437are disregarded because the data is simply not read and no data or acknowledgement, ACK signal445, is returned to the host interface409. In this case, the host interface409may later (after having regained power) process the error and take remedial action (e.g., by retrying the command or returning a read error to the application that caused the command to be issued). In another embodiment, all pending commands in channel command queues431,433,435and437may be stopped by the SSD controller401to reduce the consumption of backup power and ensure that critical data structure can be saved to non-volatile memory405before backup power is lost to SSD controller401or volatile memory403. After processing and/or stopping pending commands in channel command queues431,433,435and437, the SSD controller401begins saving critical data from volatile memory403to non-volatile memory405. There may be write commands in command queue403athat were acknowledged by SSD controller401but were not actually written to non-volatile memory405. If the write commands are lost due to a power failure, when the host later tries to retrieve the associated data, either the data returned will be old data or the data will be absent and an error will be returned. Accordingly, SSD controller401saves a copy of the command queue403ato non-volatile memory405containing at least the acknowledged write commands that have not been processed in command queue405a.

In one embodiment, the read commands and unacknowledged write commands in command queue403aare omitted from the command queue405astored to non-volatile memory405. The host can determine that it needs to reissue unexecuted read commands if the host interface409did not receive data in response to the read command from the SSD controller101prior to the loss of power. Similarly, the host can determine that it needs to reissue write commands if the host interface409did not receive an acknowledgement from the SSD controller401that the SSD controller401would write the data to non-volatile memory405prior to the loss of power. However, it may be desirable to save all commands from command queue403ato the command queue405a, including unacknowledged write commands (and the associated data to be written) and read commands. The SSD controller additionally must save the L2P update log403cto non-volatile memory405as L2P update log405c. It is important to save the L2P update log403cto non-volatile memory405because the L2P table403bstored in volatile memory403and the L2P table405bstored in non-volatile memory may not be up-to-date. The SSD controller401may send an acknowledgment to secondary controller407, via ACK signal443, each time the SSD controller401completes a step of the power loss procedure.

Upon receiving PFAIL signal439, the secondary controller407starts a timer to track the duration of time for which the SSD controller401can operate on backup power supplied by the backup power source. The timer of secondary controller407can be a clock signal having a predefined frequency. Upon each rising or falling edge of the clock signal (i.e., predefined interval or period of the clock signal), a channel controller407aof secondary controller407transmits a write command over memory data channel451causing the second non-volatile memory453to store a holdup time bit453a(represented by a “0” bit). If the SSD controller401sends an acknowledgement to the secondary controller407indicating that a particular step of the power loss procedure is complete, via ACK signal443, the secondary controller407can transmit a write command over memory data channel451causing the second non-volatile memory453to store an SSD ACK bit453b(represented by a “0” bit). When the secondary controller407monitor identifies RESET signal441, the secondary controller407stops the timer and the total number of holdup time bits453astored in second non-volatile memory453represent the holdup time of SSD controller401during backup power. For example, if the timer of secondary controller407is a 1 kHz clock signal and 10 holdup time bits453a(represented by ten “0s”) are stored in second non-volatile memory453, the holdup time bits453aindicate that the SSD controller401operated for a holdup time of 10 milliseconds. It may be desirable to use a higher frequency clock signal to measure the holdup time, as a higher frequency clock signal will result in better resolution for tracking holdup time. Further, the total number of SSD ACK bits453bstored in second non-volatile memory453represents the number of steps from the power loss procedure completed by SSD controller401.

In another embodiment, the secondary controller407periodically transmits the current holdup time upon each rising or filing edge of a clock signal. For example, if a 1 kHz clock signal is used, every 1 ms (i.e., predefined interval or period of the clock signal) the secondary controller407transmits the measured holdup time to second non-volatile memory453. After 5 ms, the value stored in second non-volatile memory453is 5 ms, after 7 ms, the value stored in second non-volatile memory453is 7 ms, etc.

After the SSD controller401completes the power loss procedure in response to the loss of power, the data previously stored in volatile memory403is lost (e.g., command queue403a, L2P table403band L2P update log403c) and the non-volatile memory405contains all of the necessary critical information to restart the SSD with PLP400.

If the SSD controller401is unable to complete the power loss procedure during backup power, holdup time453adindicates the duration of time for which the SSD controller401operated on backup power and SSD ACK453bidentifies the last step of the power loss procedure completed by the SSD controller401.

When the SSD with PLP400regains power, the SSD controller401sends requests over communication channel457to the secondary controller407requesting that the secondary controller407return the holdup time and/or acknowledgements. The channel controller407aof secondary controller407retrieves the holdup time453aand acknowledgements, SSD ACK453b, by sending read signals over memory data channel451to non-volatile memory devices455a-d. If the holdup time was tracked by storing holdup time bits453ain the second non-volatile memory453, the secondary controller407calculates the holdup time and transmits the calculated holdup time to the SSD controller401over communication channel457. If the holdup time was tracked by storing the measured holdup time at predefined intervals, the secondary controller407retrieves the last measurement of holdup time and returns the holdup time to the SSD controller401over communication channel457. Similarly, the secondary controller407returns the acknowledgements, SSD ACK453b, to the SSD controller401over communication channel457. When the SSD controller401receives the holdup time and/or acknowledgments from the secondary controller407, the SSD controller401stores the data in an operational log.

In another embodiment, second non-volatile memory453can be an internal component of secondary controller407. In another embodiment, non-volatile memory405can be used by the secondary controller407to store the tracked holdup time453aand/or acknowledgements453b, eliminating the need for second non-volatile memory453.

FIG. 5is a flowchart of steps500for one embodiment of performing PLP for an SSD, as described above. The SSD with PLP, comprising an SSD controller101, a secondary controller107, a volatile memory105, a non-volatile memory103, a second non-volatile memory143and a power circuit (comprised of power fail switch111and power monitor113) connected to a host device, such as a computer, via a host interface109, as described above. At step501, the power circuit detects a drop in the power supplied from the host interface109, indicating that the host device has experienced a loss of power. In one embodiment, the power circuit sends an alert signal to the SSD controller101and the secondary controller107indicating the loss of power. At step503, the power circuit switches to a backup power supply115to provide power to the SSD controller101, the secondary controller107, the volatile memory105, and the non-volatile memory103. The backup power supply115may comprise a supercapacitor, a battery, or any other suitable device for providing backup power to the components of the SSD, or any combination thereof. Additionally, at step503, the secondary controller107starts a timer to track the duration of time for which the SSD controller101can operate on backup power.

At step505, the SSD controller101processes all of the acknowledged write commands in the channel command queues. As previously discussed, acknowledged write commands are critical information in the event of a power failure because, upon reboot, the hose device will expect that certain data has been written to the non-volatile memory103. Optionally, in one embodiment, at step505, the SSD controller101may also processes all unacknowledged write commands and read commands in the channel command queues as would be done in normal operation. Processing all unacknowledged write commands and read commands in the channel command queues is not necessary because the host device can simply reissue any failed read and/or write commands when power is restored to the SSD, as the host will not expect that an unacknowledged read or write command was processed.

At step507, the L2P update log is copied from the volatile memory105to non-volatile memory103. At step509, all acknowledged write commands in the host command queue are copied to non-volatile memory103. Optionally, in one embodiment, at step511all read and unacknowledged write commands in the host command queue are also copied to non-volatile memory103. However, as previously discussed, read and unacknowledged write commands are not critical information that must be saved to non-volatile memory103and can be addressed by the host device after regaining power with no detrimental effect. Accordingly, in one embodiment, step511is skipped to reduce the amount of information copied to the non-volatile memory103and the method steps500proceeds directly from step509to step511.

After the SSD controller101completes each of steps505,507,509and511, the SSD controller101may be programmed to send an acknowledgement signal to the secondary controller107indicating that a particular step of the power loss procedure completed. If the secondary controller107receives an acknowledgement from the SSD controller101, the secondary controller107may store the acknowledgement in second non-volatile memory143after the completion of the respective step.

At step513, the power circuit detects that the power supplied by the backup power source115has fallen below a predefined threshold that represents the minimum voltage at which the SSD controller101can continue to operate. At step515, the power circuit applies a RESET signal to the SSD controller101. The secondary controller107and second non-volatile memory143preferably operate at a lower voltage than the SSD controller101, and thus, continue to operate on backup power for a longer period of time than the SSD controller101. In response to applying RESET to the SSD controller101(step515), at step517the secondary controller107stops the timer for tracking holdup time. During the time that SSD controller101is operating on backup power (i.e., steps503through515), the secondary controller107periodically stores an indication of the tracked holdup time in second non-volatile memory143. At step519, the SSD powers down. At step521, after the host device regains power the SSD device powers back up. At step523, the SSD controller101sends a request to secondary controller107to return the holdup time and acknowledgements. In response to the request from SSD controller101, secondary controller107retrieves the holdup time and acknowledgements stored in second non-volatile memory143and returns the data to SSD controller101. If the holdup time is tracked by storing holdup time bits in second non-volatile memory143, secondary controller107calculates the holdup time and returns the calculated holdup time to SSD controller101. SSD controller101stores the holdup time and acknowledgements received from secondary controller107in an operational log. In an alternative embodiment, only a single non-volatile memory may be used (e.g., non-volatile memory103). In this embodiment, at step523, the secondary controller107retrieves the holdup time and acknowledgements stored in volatile memory103and returns the data to SSD controller101. At step525, the SSD controller101repopulates the L2P table and L2P update log from non-volatile memory103to the volatile memory105. At step527, the SSD controller101reconstructs the host command queue from non-volatile memory103to the volatile memory105. At step529, the SSD controller101can resume normal read, write, and erase operations.

If the SSD controller101is unable to complete any of steps505,507,509or511(represented by dashed lines), steps513through523(represented by solid lines) would still execute as these steps occur when the power circuit detects the backup power source115is below a predefined threshold. The holdup time in step517indicates the duration of time for which the SSD controller101operated on backup power and the acknowledgements identify the last step of the power loss procedure completed by the SSD controller101. If the SSD controller101is unable to store all critical information (i.e. the acknowledged write commands in the channel command queue, acknowledged write commands in command queue, or L2P update log), when the SSD controller101powers up at step521, the SSD controller101will be in a failed state. Thus, the SSD controller101may not be able to perform some or all of steps525,527and529(represented by dashed lines).

Although method steps500describe a power circuit as detecting a loss of power from a host device and switching to a backup power source115, either the SSD controller101or the secondary controller107could be configured to perform this step. Additionally, the secondary controller107can be further configured to detect the backup power source115below a predefined threshold and apply RESET to the SSD controller101.

Implementing method steps500for an SSD with PLP allows for an accurate measurement of the time for which the primary controller101operates on backup power along with an indication of the steps of the power loss procedure that the primary controller101was able to perform.

Other objects, advantages and embodiments of the various aspects of the present invention will be apparent to those who are skilled in the field of the invention and are within the scope of the description and the accompanying Figures. For example, but without limitation, structural or functional elements might be rearranged, or method steps reordered, consistent with the present invention. Similarly, principles according to the present invention could be applied to other examples, which, even if not specifically described here in detail, would nevertheless be within the scope of the present invention.