One-time programmable bitcell for frontside and backside power interconnect

A bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline.

TECHNICAL FIELD

The present disclosure generally relates to an integrated circuit (IC). In particular, the present disclosure relates to a one-time programmable bitcell suitable for use with frontside and backside power interconnect.

BACKGROUND

In semiconductor manufacturing processes, a back end of line (BEOL) stage of an IC fabrication process adds metal interconnects on top of individual devices, such as transistors, capacitors, and resistors, where the individual devices were previously formed in a front end of line (FEOL) stage of the IC fabrication process. The metal interconnects are used to provide wiring between the individual devices, including supplying high frequency signals between the devices and supplying power to the devices. This results in high congestion of both signals and power lines in the lower metal levels. This also causes the metal stack to be a compromise between high power (e.g., high current, as implemented by a low resistance metal connection) and high speed (e.g., high frequency, as implemented by a low capacitance metal connection).

One-time programmable (OTP) memory is a type of non-volatile memory that can be written to only once. OTP memory is used in applications such as microprocessors, sensors, and display (e.g., for storing configuration or calibration parameters, identifiers, and other permanent information). A one-time programmable memory may include multiple OTP bitcells arranged, for example, in a linear array or in the rows and columns of a two-dimensional matrix or two-dimensional array.

SUMMARY

According to one embodiment of the present disclosure, a bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending substantially parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending substantially parallel to the bitline.

The write-once programmable circuit element may be a positive metal oxide semiconductor (PMOS) anti-fuse.

The select write device may include a cascode negative metal oxide semiconductor (NMOS) device. The cascode NMOS device may include: a first NMOS transistor having the gate electrode connected to the second signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a third signal line extending substantially perpendicular to the second signal line.

The select read device may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the first signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a third signal line extending substantially parallel to the first signal line.

The bitline may have a lower capacitance than the word line, and the word line may have lower resistance than the bitline.

The one-time programmable memory may further include a second one-time programmable bitcell including: a second write-once programmable circuit element and a second node connected in series between the word line and the power rail; a second select read device connected between the second node and a second bitline extending parallel to the bitline, the second select read device having a gate electrode connected to the first signal line; and a second select write device connected between the word line and the second node and in series with the second write-once programmable circuit element and the second node, the second select write device having a gate electrode connected to a third signal line extending substantially parallel to the bitline.

The select write device may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the second signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a fourth signal line extending substantially perpendicular to the second signal line, and the second select write device may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the third signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to the fourth signal line.

According to one embodiment of the present disclosure, a bitcell of a one-time programmable memory includes: a select read device connected between a node and a first bitline, the select read device having a gate electrode connected to a first signal line extending substantially perpendicular to the first bitline; a first select write device connected between a supply power rail and a power rail and in series with the node, the first select write device having a gate electrode connected to a second signal line extending substantially parallel to the first bitline, wherein the supply power rail has higher voltage than the power rail; a second select write device connected between the node and the power rail and in series with the first select write device and the node, the second select write device having a gate electrode connected to a third signal line extending substantially perpendicular to the first bitline; and a write-once programmable circuit element connected between the node and the power rail and in series with the first select write device, the second select write device, and the node.

The node and the write-once programmable circuit element may be between the first select write device and the second select write device.

The node and first select write device may be between the write-once programmable circuit element and the second select write device.

The select read device may include a PMOS read select device.

The one-time programmable memory may further include a second one-time programmable bitcell including: a second select read device connected between a second node and a second bitline extending substantially parallel to the first bitline, the second select read device having a gate electrode connected to the first signal line; a third select write device connected between the supply power rail and the second node, the third select write device having a gate electrode connected to a third signal line extending substantially parallel to the first bitline; a fourth select write device connected between the second node and the power rail, the fourth select write device having a gate electrode connected to the third signal line; and a second write-once programmable circuit element connected to the node, in series with the third select write device and the fourth select write device, between the supply power rail and the power rail.

According to one embodiment of the present disclosure, a method for writing to a bitcell of a one-time programmable memory including: a write-once programmable circuit element and a middle node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line, the bitline having lower capacitance than the word line, the word line having lower resistance than the bitline; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline, where the method includes: charging the node to an intermediate voltage between a rupture voltage and a ground voltage; applying a first signal to the first signal line to turn off the select read device; applying a second signal to the second signal line to turn on the select write device; and pulsing the power rail to the rupture voltage.

The write-once programmable circuit element of the bitcell may be a PMOS anti-fuse.

The select write device of the bitcell may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the second signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a third signal line extending perpendicular to the second signal line, and the method may further include: applying a third signal to the third signal line to turn on the second NMOS transistor.

The select read device of the bitcell may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the first signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a third signal line extending parallel to the first signal line, and the method may further include: applying a third signal to the third signal line to turn on the second NMOS transistor.

The bitcell may be a bitcell of an array of bitcells further including a second one-time programmable bitcell including: a second write-once programmable circuit element and a second node connected in series between the word line and the power rail; a second select read device connected between the second node and a second bitline extending parallel to the bitline, the second select read device having a gate electrode connected to the first signal line; and a second select write device connected between the word line and the second node and in series with the write-once programmable circuit element and the second node, the second select write device having a gate electrode connected to a third signal line extending parallel to the bitline, and the method may further include charging the second node to the intermediate voltage.

The select write device may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the second signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a fourth signal line extending perpendicular to the second signal line, the second select write device may include a cascode NMOS device including: a first NMOS transistor having the gate electrode connected to the third signal line; and a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to the fourth signal line, and the method may further include supplying a fourth signal to the fourth signal control line to turn on: the second NMOS transistor of the select write device; and the second NMOS transistor of the second select write device.

The array of bitcells may further include a third one-time programmable bitcell including: a third write-once programmable circuit element and a third node connected in series between the word line and a second power rail extending parallel to the word line; a third select read device connected between the third node and the bitline, the third select read device having a gate electrode connected to a fourth signal line; and a third select write device connected between the word line and the third node and in series with the write-once programmable circuit element and the third node, the third select write device having a gate electrode connected to the second signal line, and the method may further include maintaining the second power rail at a ground voltage during the writing to the bitcell.

DETAILED DESCRIPTION

Aspects of the present disclosure relate to a one-time programmable bitcell for frontside and backside power interconnect.

In a semiconductor manufacturing process, integrated circuits such as computer chips are fabricated on a flat semiconductor substrate by sequentially depositing layers of material onto the substrate. The substrate is typically a piece of silicon but may sometimes be another material such as gallium arsenide, which can provide different tradeoffs in terms of cost and performance. To add a patterned layer of material onto the substrate, a light-sensitive material is first applied to the substrate, and then a mask is used to selectively expose some parts of that light-sensitive material to light. This light exposure causes some parts of the light-sensitive material to cure and to attach to the surface so that the other parts of the material can be washed away. The desired material can then be applied over the entire surface and then the light-sensitive material, together with the desired material deposited on top, is removed such that desired material is placed only in the specified locations on the substrate. This process is repeated many times to deposit many layers of different materials onto the substrate, such as electrically insulating layers, electrically conductive layers, dopants, and the like. The controlled deposition of materials onto the substrate in specified patterns forms electrical circuit elements, such as transistors, resistors, capacitors, and wires (or metal interconnect) on the substrate, where the transistors are typically formed near the bottom of the stack of layers.

The size and shape of a metal interconnect or metal wire has a significant impact on its electrical properties. Generally, thicker wires (with a larger vertical height) have lower resistance and higher capacitance than thinner wires (with a smaller vertical height). This means that thicker wires are better suited for transmitting high current long distances, such as the case for power supply rails that supply power to different parts of the circuit. On the other hand, the high capacitance of these thicker wires makes them less suitable for transmitting rapidly-changing signals such as data signals across shorter distances (power supply voltages generally do not change much and therefore are tolerant of high capacitance). Conversely, thinner wires, which have higher resistance than thicker wires, are generally less suitable for transmitting power across longer distances, because the high resistance can cause a noticeable drop in voltage along the length of the wire. On the other hand, the lower capacitance of thinner wires makes them better suited to transmitting data signals across shorter distances.

Generally, thinner wires tend to be placed at lower layers of the stack of layers forming the semiconductor device and thicker wires tend to be placed at higher layers (deposited later than the lower layers). Nevertheless, the thicker wires deposited at higher layers also need to connect to the transistors near the bottom of the stack, that means the power supply needs be routed down through the lower levels of metal to connect to devices formed at the wafer surface. This creates congestion at the lower levels and forces the power lines to be partially routed through thin metal lines in the lower layers.

In some semiconductor chip manufacturing processes, all circuit elements of an integrated circuit, including transistors and metal interconnects, are formed on only one side of a flat substrate, where the other side of the substrate is unmodified (e.g., where semiconductor devices are not formed on the opposite side of the silicon substrate).

As semiconductor processes continue to scale, in some designs, metal interconnects are placed both on top of the device, such as transistors (topside interconnect), as well as below the transistors (backside or buried interconnect). Typically, the wafer is made in a similar way as previously, but with metal vias added that extend from the wafer surface down below the transistors. The wafer is flipped upside down, the wafer is thinned to expose the buried vias, and additional metal interconnect is added working from the backside of the wafer. This allows for interconnect to the transistors from both top (or frontside) and bottom (or backside). This also allows for two different metal stacks to be optimized independently for different functionality.

In these semiconductor processes, metal interconnects are placed both on one side (e.g., top) of the device, such as transistors (topside or frontside interconnect), as well as an opposite side (e.g., below) the transistors (backside or buried interconnect). During wafer processing, transistors and other devices are formed on one side of the wafer as discussed above. The wafer is held in place for many manufacturing steps by using a ring around the edge of the top or front of the wafer to press the wafer against a surface of a tool (e.g., a photolithography tool, a chemical vapor deposition tool, an ion implantation tool, an etching tool, etc.). When the wafers are being transferred from one tool to another tool during manufacturing, many tools use suction to “grab” the back of the wafer. (The front of the wafer cannot be touched without risk of damaging the layers formed there.) Layers are built up on one side of the wafer over many steps. The surface where the devices are formed is considered the front or frontside or top of the wafer.

In these semiconductor processes, after one side of the wafer is fully formed, it is covered in a protective layer and then flipped over such that the other side or back side can be processed (e.g., by forming metal interconnects and other devices on the other side of the wafer). The side of the wafer that is processed first and that has the transistors is typically referred to as the front or frontside or top of the wafer. The side of the wafer that is processed second is called the back or backside or bottom or buried side of the wafer. Forming transistors frequently involves higher temperatures than most metal interconnect can tolerate. Therefore, the transistors need to be formed before most metal interconnect is formed. Since metal interconnect is formed on the topside after the transistors are formed, the maximum temperature during the backside processing is limited to what the front side metal interconnect can tolerate. In practice, this often means that only metal interconnect can be added to the backside or buried side because applying high temperatures to form transistors on the backside would damage the previously deposited metal interconnect on the front side.

Because there are two different metal stacks—a topside or frontside stack located on or above of the same side of the substrate as the transistors and a backside stack located on the other side of the substrate (where part of the substrate was removed to provide access to the transistors on the front side)—the metal stacks on the two sides can be optimized for different functions: top side metal layers with thinner metal lines having low capacitance for high speed short distance interconnect; and backside metal layers with thicker metal interconnect having low resistance for high current power supplies, thereby enabling two different metal stacks that can be optimized for different functions providing improved overall performance.

In more detail, the buried (or backside) metal interconnect may be optimized for power supply needs (e.g., low resistance, high immunity to electro migration), noting that power supplies can tolerate higher capacitance than lines carrying high frequency signals. To reduce or minimize the pitch or spacing between the metal lines, the buried power rails may be optimized to run parallel to each other in a particular orientation. This works well for power supplies, which are typically direct current (DC), and which have coupling capacitors added between them to reduce or smooth ripples in the voltage. This approach is suitable for synthesized digital logic and static memory (SRAM) cells that are optimized for a specific pitch in a specific orientation. Changes to use the buried metal lines for short distance signals other can result in a very large area increase, resulting in inefficient use of space in the chip design. Typically, the minimum size of a thick metal line is much larger than a thin metal line, which means that a very large metal island may be needed to act as a jumper between two different backside metal layers (e.g., from backside metal1 to backside metal2). Specifically, if two signals run perpendicular to each other and need to have high density, such as when connecting to a bitcell, then typically one signal needs to be routed from one metal layer to a different metal layer. The small piece of metal needed to connect or pass a signal from one contact (or via) through a metal layer to a via on another level can be very costly in size. This small piece of metal used only to pass through (or jumper or bridge) two backside metal at different levels (or a contact to vias at different levels) can be called a dot or an island.

The topside metal interconnect may be optimized for high frequency signals traveling short distances. For example, the topside metal may be thin to reduce or minimize capacitance, although this will result in higher resistance than the buried metal of the backside interconnect. This increased resistance makes such thinner metal interconnects generally unsuitable for carrying high currents for long distances, such as the case for supplying power to the devices (transistors) in the design. On the other hand, these thinner metal interconnects are suitable for transmitting local signals. For example, if the output of one transistor is going into the gate of another transistor, very little current is needed (only needs to charge or discharge the metal interconnect capacitance and the gate of a transistor). In addition, the small thin metal line is small in size and therefore allows increased density of interconnect.

Therefore, in such an arrangement, the buried/backside metal interconnect is more appropriately used for any signal that needs high current (e.g., a low resistance interconnect to reduce a voltage drop or current-resistance (IR) drop along the interconnect) and that can tolerate high capacitance (e.g., low speed or low frequency signals, such as direct current (DC) signals). In contrast, the front or topside metal interconnect is more appropriately used for high speed or high frequency signals that need low capacitance and can tolerate limited current. In more detail, a metal interconnect may be designed for high current and low resistance by having a larger cross-sectional area (e.g., thicker and/or wider metal interconnects) but this larger cross-sectional area results in higher capacitance than metal interconnects with smaller cross-sectional areas. On the other hand, a metal interconnect may be designed for high speed and low capacitance by having a smaller cross-sectional area (e.g., thinner and/or narrower metal interconnects), but such a metal interconnect has higher resistance than metal interconnects with larger cross-sectional areas.

Accordingly, in these example arrangements, a buried/backside metal interconnect has a larger cross-sectional area than a frontside or topside metal interconnect and therefore the buried/backside metal interconnect has a lower resistance and higher capacitance than the front or topside metal interconnect. Likewise, the frontside or topside metal interconnect has a smaller cross-sectional area than the buried/backside metal interconnect and therefore has a higher resistance and lower capacitance than the buried/backside metal interconnect.

In some semiconductor manufacturing processes, most features are defined using the diffraction of light. Diffraction allows for features to be formed that are smaller than the wavelength of the light used to make them. This allows the buried metal lines to be pitch matched to the transistors, but with many limitations. Diffraction is very effective at making long straight lines, but it can be difficult to control diffraction effects to define dots or islands.

Generally, a one-time programmable (OTP) bitcell is programmed by applying a high voltage to rupture an anti-fuse, followed by a high current to form a conductive filament in the anti-fuse or a high current to break a connection in a fuse. The term write-once programmable circuit element will be used herein to refer to fuses and anti-fuses. The value stored in an OTP bitcell therefore depends on whether that write-once programmable circuit element (a fuse or anti-fuse) has been permanently altered—the OTP bitcell stores a default value (e.g., 0) if unaltered and stores a different value (e.g., 1) once the fuse or anti-fuse has been modified. In a comparative OTP array, OTP bitcells may be arranged in a row/column architecture (e.g., a two-dimensional matrix), where an individual bitcell is programmed (e.g., modified from the default value) by supplying high current flowing both vertically along a column line and horizontally along a row line to the particular bitcell being ruptured at a crossing region of the column line and row line. However, applying high current along both a column direction and a row direction may be challenging in arrangement where the low resistance (high current) metal interconnects (e.g., buried power rails) run parallel to one another (e.g., all along a column direction or all along a row direction) and there is a large area increase if an island is added to jump the signal from a first thick metal line to a second thick metal line running perpendicular to the first think metal line.

FIG.1Ashows an example 2T (two transistor) one time programmable (OTP) bitcell100. The bitcell100uses two NMOS devices: one as a select device110; and another as an anti-fuse device120(e.g., such that the anti-fuse, by default, provides a high resistance connection or effective open circuit, but ruptures when high voltage is applied to the anti-fuse, thereby breaking down the insulation and with high current forming a permanent connection through the anti-fuse). The bitcell100is programmed by rupturing that gate of the anti-fuse device120. This rupturing is done by bringing the word line (WL)130up to a voltage capable of rupturing that gate of the anti-fuse device120(e.g., a rupture voltage) for a specified write time and bringing that gate of the select device110high (by applying a turn-on voltage to select line140) to turn the select device on and holding the bitline (BL)150at 0V. When the gate of the anti-fuse ruptures the bitcell must provide a low resistance (high current) path from the word line WL130to the bitline BL150allowing sufficient current to flow to allow a low resistance filament to form. The bitcell may be one bitcell in an array of bitcells, where all of the bitcells in a same row are connected to the same word line WL and all of the bitcells in a same column are connected to the same bitline BL. As such, an individual bitcell can be selected for rupturing by applying the rupture voltage to the word line WL130connected to that bitcell, applying an appropriate voltage to the select line140, and holding the bitline BL150connected to that same bitcell at 0V.

FIG.1Bshows a layout view having of four bits (the schematic inFIG.1Ashows one bit), whereFIG.1Bshows the Metal1, Via1 and Metal2 for a linear array of four bitcells101,102,103, and104. As shown inFIG.1B, the write line WL131and the select line141are formed in the gate layer (e.g., polysilicon (Poly) or metal) (not shown, running under metal1 lines131and141) that is connected to Metal1 layer (shown with diagonal line pattern), and the write line WL131runs perpendicular to the bitlines BL151,152,153, and154, with the bitlines formed in the Metal2 layer and connecting to the Metal1 layer through contacts having the shape of dots or islands171,172,173, and174. Because both write line WL131and the bitlines BL151,152,153, and154need to carry high current during programing, ideally, they should both be in the backside metal when the backside metal is designed for low resistance (e.g., with a larger cross-sectional area).

However, as noted above, it is difficult to form small dots171,172,173, and174in backside metal using patterning techniques such as diffraction. The bitlines BL151,152,153, and154are also used in the high-speed, low current read operation, and therefore they should be in the topside metal, which has thinner wires with lower capacitance. Therefore, such a bitcell design100shown inFIG.1Ais not well suited for processes with low capacitance metal interconnect (e.g., transmitting high frequency signals) separated from low resistance metal interconnect (e.g., delivering power) in top and bottom metallization (e.g., high speed, low capacitance metal interconnect in the top metallization and high current, low resistance metal interconnect in the bottom metallization, or vice versa).

In another bitcell design (not shown), the metal used to route the bitlines and wordlines can be flipped. However, this change merely moves the locations of the metal islands to different locations and does not solve the underlying problem where these metal islands consume a large amount of area (space in the integrated circuit design).

Generally, the read time for OTP bitcells is much faster than the write time. The read operation is also typically performed at a much lower current. Other OTP non-volatile memory (NVM) designs may use the same metal interconnect to read from and write to the bitcell. However, in semiconductor technologies that have two types of metal interconnect optimized for different purposes (e.g., different current and speed), there is an opportunity for improvement.

As such, aspects embodiments of the present disclosure relate to one-time programmable (OTP) bitcells that use different metal interconnects for programming versus reading an OTP bitcell. For example, the signals to write the bitcell may be applied through the high current, low resistance backside metal interconnect and the signals to read the bitcell should be applied and received through the high speed, low capacitance topside metal interconnect.

Technical advantages of the present disclosure include but are not limited to the separation of high speed, low capacitance read metal interconnects from high current, low resistance metal interconnects (e.g., front side or topside signal metal lines separated from buried or backside power metal lines). This separation changes the design constraints for a bitcell layout for devices such as fuses and anti-fuses, as it is desirable for these bitcells to have: small size (area), a first operation that requires high current (e.g., in order to rupture a gate oxide in the anti-fuse to form a permanent low-resistance link), and a second operation that requires high speed (e.g., high frequency to perform high speed reads of the stored data). Aspects of embodiments of the present disclosure include a one-time programmable (OTP) bitcell designed to use the present interconnect schemes with separate topside metal interconnect and backside metal interconnect.

Some aspects of embodiments relate to OTP bitcells that include an additional device, or devices, so the high current, low resistance lines can run parallel and be switched by a device with a control signal running perpendicular to the high current, low resistance lines. This provides a technical advantage in that it avoids the need to have two high current signals running perpendicular to each other, as in the case of other OTP bitcells.

FIG.2is a circuit diagram of a three transistor (3T) one-time programmable (OTP) bitcell200with an anti-fuse device210, a select read device220, and a select write device230according to one embodiment of the present disclosure. In the example ofFIG.2, the write-once programmable circuit element is an anti-fuse device210that is shown as an NMOS device, but embodiments are not limited thereto. Having an additional transistor (in comparison to the 2T bitcell shown inFIG.1A) allows for separate read and write (programming) paths. The bitcell shown inFIG.2has two high power metal lines, a first power rail240(or fuse power rail or supply power rail or word line WL) and a second power rail250(or VSS or ground power rail), running in parallel in backside or buried metal lines metal (as indicated by the thicker lines inFIG.2). As used herein, the term parallel includes lines that are exactly parallel as well as lines that are substantially parallel (e.g., non-crossing or non-intersecting in a plan view of the integrated circuit layout). As used herein, the term perpendicular refers to lines that cross or intersect within the layout of the bitcell or array of bitcells (while this will generally be at 90 degrees, the present disclosure is not limited thereto, and these perpendicular or otherwise crossing lines may cross at angles near 90 degrees or other angles such as 45 degrees or 60 degrees). The select read device220is in series with the anti-fuse device210between the two high power metal lines240and250. The select write device230is controlled by a write signal supplied to its gate through a write select line260in top metal (as indicated by the thinner lines) that runs perpendicular to the buried or backside metal lines240and250. During programming, the write select line260can turn on the select write device230inside the OTP bitcell200, allowing for high current to flow a very short distance through topside metal from the first power rail240(or fuse power rail or supply power rail) through the anti-fuse device210to the VSS rail250(or ground power rail). The select write device230can be made large enough to handle the current needed. A read select line270in the topside metal (in another embodiment, not shown, line270is run in a gate layer (e.g., polysilicon or metal)) is used to control a gate of the select read device220to read the OTP bitcell200using a high speed, low current path through the bitline (BL)280, where the select read device220is connected between the bitline280and a middle node290between the anti-fuse device210and the select write device230.

FIG.3Ashows an example embodiment of a 3×2 array300of 3T OTP bitcells with separate read and program paths according to the embodiment ofFIG.2. In the example shown inFIG.3A, a first row of three bitcells301,302, and303are all connected to a first fuse power rail341(or first supply power rail), a first VSS power rail351(or first ground power rail, and first read select line371extending horizontally in parallel (e.g., in the row direction). Likewise, a second row of three bitcells304,305, and306are all connected to a second fuse power rail342(or second supply power rail), a second VSS power rail352(or second ground power rail), and a second read select line372extending horizontally in parallel (e.g., in the row direction). A first column of the 3×2 array300of 3T bitcells includes a first bitcell301from the first row and fourth bitcell304from the second row, which are both connected to a first write select line361and a first bitline381. Likewise, a second column includes a second bitcell302from the first row and a fifth bitcell305from the second row, both of which are connected to a second write select line362and a second bitline382. A third column includes a third bitcell303from the first row and a sixth bitcell306from the second row, both being connected to a third write select line363and a third bitline383.

To store a value in a 3T OTP bitcell of the array, voltage signals are applied to the power rails and the write line to select an individual bitcell whose write-once programmable circuit element (e.g., an anti-fuse or fuse) is to be ruptured in order to change the value that is output from the bitcell when its value is read. Accordingly, some aspects of the present disclosure relate to applying voltage signals in a manner that results in the programming of an individual OTP bitcell without affecting the values stored in other bitcells in the array.

In the example shown inFIG.3A, the fifth bitcell305(the middle cell in the lower row) is to be programmed by rupturing its anti-fuse device315.FIG.3Bshows a flowchart of a method390for performing a write operation to an array of 3T OTP bitcells with separate read and program paths according to the embodiment ofFIG.3A. The method may be performed by an OTP memory programming circuit or other controller circuit connected to control the signals (e.g., voltages) supplied to the power rails and write lines of the array300. In some embodiments, an OTP memory programming circuit configured to implement the method described herein is integrated into a specialized OTP memory controller for the OTP memory and may be specified in a macro to be integrated into an integrated circuit or specified in register transfer level code to be integrated into other synthesized logic on an integrated circuit.

To program a 3T bitcell such as that shown inFIG.2andFIG.3A, at392, the programming circuit pre-charges the middle nodes of all the bitcells that share the power line that will later be raised to the rupture voltage, in this example the middle nodes of the fourth bitcell304, the fifth bitcell305(middle node395), and the sixth bitcell306connected to the second fuse power rail342, where the middle nodes are between the anti-fuse device and the select write device230. These middle nodes are pre-charged to an intermediate voltage (Vinhibit greater than 0V and less than the rupture voltage) in order to protect anti-fuse devices of other bitcells in the row from rupturing due to leakage. In more detail and referring to the example ofFIG.3Awhere the fifth bitcell305in the second row is being ruptured, at392, the programming circuit applies a voltage signal to second read select line372to turn on its connected read select devices324,325, and326, and applies the Vinhibit voltage to at least all of the bitlines other than the bitline connected to the bitcell that will be ruptured—in this example, at least the first bitline381and the third bitline383. This sets the voltages of the middle nodes of the fourth bitcell304and the sixth bitcell306to Vinhibit.

At394, the programming circuit turns off the select read devices324,325, and326connected to the second read select line372, such as by disabling the signal applied to the second read select line372(e.g., corresponding to read select device220as shown inFIG.2), such as by applying a voltage below the threshold voltage that would turn on the select read devices324,325, and326.

At396, the programming circuit turns on the select write device335connected to the fifth bitcell305(the bitcell whose anti-fuse is to be ruptured) by applying a voltage signal to the corresponding second write select line362. All other select write devices are kept off (e.g., by applying voltages to the gates of the select write devices through the first write select line361and the third write select line363inFIG.3Ato turn off the corresponding select write devices).

At398, the programming circuit pulses the second fuse power rail342to a voltage sufficient to rupture the anti-fuse (Vrupt). The particular voltage depends on the semiconductor process technology and electrical characteristics of the anti-fuse. In some examples, this voltage level is 4V and is typically higher than VDD (e.g., in some semiconductor process technologies, VDD may be 1V).

In some embodiments of the present disclosure, instead of holding the write select line362high and pulsing the second fuse power rail342, the second fuse power rail342is held at a rupture voltage Vrupt and a pulse is supplied to the write select line362corresponding to the bitcell to be programmed (e.g., the fifth bitcell305ofFIG.3A).

In addition, in some embodiments of the present disclosure, instead of programming bitcells one at a time, multiple bitcells in a same row may be programmed simultaneously. In some examples, the write lines corresponding to the multiple cells to be programmed are all set to turn on the select write device of each bitcell, and the second fuse power rail342is then pulsed to permanently change the anti-fuses (or fuses) in each of the corresponding bitcells. Alternatively, the second fuse power rail342may be held at the rupture voltage Vrupt and the write lines corresponding to the bitcells to be programmed may be pulsed to permanently change the anti-fuse or fuse therein to program those bitcells. In some example embodiments, the number of bitcells that can be programmed simultaneously depends on the current required to rupture an anti-fuse or fuse and the maximum amount of current that can be supplied from the programming circuit through the power rails.

FIG.3Cshows an example embodiment of a 3×2 array of 3T OTP bitcells with separate read and program paths according to the embodiment ofFIG.2and where adjacent rows of 3T OTP bitcells share a power rail. In more detail, by having adjacent rows of bitcells share power rails, there is an area savings in the layout of the OTP memory. For example, as seen inFIG.3A, the area between the first VSS power rail351and the second fuse power rail342may go unused and design rules may require minimum spacing between these power rails, and also requiring two power rails to be placed for each row of the array. In contrast, in the example ofFIG.3C, the first row of OTP bitcells301F,302F, and303F are flipped along the row axis relative to the first row of OTP bitcells301,302, and303shown inFIG.4A, such that the first row and the second row of OTP bitcells share a fuse power rail342S. By continuing the flipping pattern, such a layout requires an average of one power rail per row of bitcells, plus one more power rail at the top or bottom of the array (e.g., N+1 power rails for an array of N rows), thereby resulting in savings in both area and number of power rails required.

In the arrangement shown inFIG.2and inFIG.3A, the select write device230ofFIG.2or the select write device335ofFIG.3Ashould be large enough to pass the current needed to rupture the anti-fuse device210ofFIG.2or the anti-fuse device315ofFIG.3A. For example, to rupture the gate oxide of the anti-fuse to form a permanent, low resistance connection, this current may be about 150-250 μA, depending on the sizes of the features of the anti-fuse and based on the semiconductor process technology.

Table 1 shows the operation of the bitcell shown inFIG.2, according to one embodiment.

While the OTP bitcell200shown inFIG.2and the bitcells shown in the array300ofFIG.3Ainclude write-once programmable circuit elements implemented using anti-fuses, embodiments are not limited thereto. For example, in some embodiments, the bitcell is implemented with a fuse device as the write-once programmable circuit element instead of an anti-fuse (e.g., such that the fuse, by default, provides a low resistance connection but ruptures when high current is applied to the fuse, thereby breaking the low resistance connection).

In the embodiment shown inFIG.2, the gate electrode of the NMOS anti-fuse device210is connected to the fuse power rail240. However, embodiments are not limited thereto.FIG.4Ashows an OTP bitcell400according to an embodiment of the present disclosure, where the OTP bitcell400is similar to the OTP bitcell200ofFIG.2, but where the anti-fuse is implemented using a PMOS anti-fuse410(instead of an NMOS anti-fuse device210, as shown inFIG.2). Similarly, in the example bitcells of the embodiments shown inFIGS.4B and4C, discussed below, the anti-fuse has been changed from NMOS to PMOS.

The source or drain of the anti-fuse410of the OTP bitcell400is connected to a fuse power rail440. A gate electrode of the PMOS anti-fuse410is connected to a select write device430(e.g., an NMOS write select device430) through a middle node490, where the anti-fuse410and the select write device430are connected in series between the fuse power rail440and a ground power rail450. The select write device430is controlled by signals applied to the gate electrode of the select write device430, as supplied through a write select line460extending in the column direction. A select read device420is connected between the middle node490and a bitline480and is controlled by a read select line470connected to the gate electrode of the select read device420.

Selecting an NMOS versus a PMOS anti-fuse may have different design tradeoffs. For example, for device reasons and depending on various design factors outside of the bitcell, it may be easier to rupture or to read an NMOS anti-fuse versus a PMOS anti-fuse (or vice versa), or selecting one type of anti-fuse versus the other may reduce the size of the bitcell. For example, in some processes the N-type and P-type transistors are stacked on different levels. In some embodiments, stacking devices one on top of each other using a mix of NMOS and PMOS reduces the size of the bitcell (e.g., where the PMOS anti-fuse410may be stacked on an NMOS write select device430).

When rupturing the anti-fuse of a bitcell during programming, high voltages may be applied to the transistors of other bitcells connected to the same fuse power rail or word line WL (e.g., in the same row as the bitcell being programmed). For example, as shown inFIG.3A, the anti-fuse of the fifth bitcell305is ruptured by applying 0 V or Vinhibit during a pre-charge phase, then applying the rupture voltage Vrupt to the second fuse power rail342(or word line WL). Similarly, as shown inFIG.4A, the anti-fuse410of the OTP bitcell400is ruptured by applying 0 V or Vinhibit during a pre-charge phase, then applying the rupture voltage Vrupt to the fuse power rail440(or word line WL).

FIGS.4B and4Cshows additional embodiments of the bitcell with additional devices added to reduce stress on the transistors during programming. For example, an NMOS cascode device may be added to reduce gate induced drain leakage (GIDL) during write or rupture of a write-once programmable circuit element (e.g., an anti-fuse device)411. The additional NMOS device may be shorted to VDD or switched, and the gate connection may be routed vertically or horizontally. In the OTP bitcell401shown inFIG.4B, the NMOS cascode transistor431B is added to the select write device431, such that the select write device431includes two NMOS transistors431A and431B in series, where the first NMOS transistor431A of the select write device has a gate electrode connected to a first write select line461A extending in a direction parallel to a bitline481and the second NMOS transistor431B of the select write device431has a gate electrode connected to a second write select line461B extending in a direction crossing the first write select line461A (e.g., parallel to a read select line471, a fuse power rail441, and a ground power rail451). In the arrangement shown inFIG.4B, the select read device421is unmodified from the example shown inFIG.4Aand is connected between middle node491and the bitline481.

Similarly, in the OTP bitcell402shown inFIG.4C, NMOS cascode devices are added to both the select read device422and the select write device432, such that the select read device422includes a first NMOS transistor422A and a second NMOS transistor422B in series between a middle node492and a bitline482and the select write device432includes a first NMOS transistor432A and a second NMOS transistor432B in series between the middle node492and a ground power rail452. An anti-fuse device412and the select write device432are connected in series between a fuse power rail442and the ground power rail452, with the middle node492located between the anti-fuse device412and the select write device432. The first NMOS transistor422A and the second NMOS transistor422B of the select read device422have gate electrodes that are respectively connected to a first read select line472A and a second read select line472B, both extending in a direction parallel to the fuse power rail442and the ground power rail452.

FIG.4Cis further labeled with voltages applied to the signal lines of an OTP bitcell402in a row of OTP bitcells during programming. By setting the gate electrodes of the cascode devices closer to the middle node492(the second NMOS transistor422B of the select read device422and the second NMOS transistor432B of the select write device432) to turn on the NMOS transistors, during programming, the stress on the other, turned off members of the cascode devices (respectively, the first NMOS transistor422A of the select read device422and the first NMOS transistor432A of the select write device432) is reduced. Accordingly, in the embodiment shown inFIG.4C, the first write select line462A is set to VDD or higher for the column corresponding to the bitcell that is to be programmed and set to 0V for the other columns. The second write line462B is set to VDD or higher, which turns on the cascode second NMOS transistor432B of the select write device432, thereby allowing current to flow through the select write device432of the OTP bitcell that is to be programmed, while also providing voltage protection to the second NMOS transistor432B of the other OTP bitcells in the same row. Likewise, the cascode second NMOS transistor422B of the select read device422is turned on by applying VDD or higher through the second read select line472B, which provides voltage protection to the first NMOS transistor422A of the select read device422. (In the example shown here, the bitline482may be set to 0V or may be unset (floating).) Accordingly, when the rupture voltage Vrupt is applied (e.g., pulsed) on the fuse power rail442, the cascode NMOS transistors of the select read device422and the select write device432provide voltage protection.

As discussed above, while an OTP bitcell according to some embodiments include an anti-fuse as the write-once programmable circuit element, embodiments are not limited thereto. For example, some embodiments of the present disclosure are directed to OTP bitcells that include a fuse as the write-once programmable circuit element instead of an anti-fuse.FIG.5Ais a circuit diagram of a bitcell500with a fuse510according to one embodiment of the present disclosure. As shown inFIG.5A, a PMOS write device531(e.g., PMOS transistor or first select write device), the fuse510, and an NMOS write device532(e.g., NMOS transistor) are connected in series between a pair of power rails (e.g., a fuse power rail540supplying a high voltage VDD and a ground power rail550supplying a low voltage VSS). The gate of the PMOS transistor or PMOS write device531is connected to a first control line561that is perpendicular to a second control line562connected to the gate of the NMOS transistor or NMOS write device532or second select write device.

In the embodiment shown inFIG.5A, the first control line561is parallel to a bitline580and the second control line562is parallel to the power rails540and550. A select read device520(e.g., an NMOS transistor) is connected between the bitline580and a middle node590, where the middle node is between the fuse510and the PMOS write device531, where a gate electrode of the select read device520is connected to a word line or read select line570. In the bitcell500ofFIG.5A, the power rails540and550can be held at a fixed voltage (directly connected to VDD and VSS). A single bitcell500is programmed by selectively turning on the gates of both select write devices (the PMOS select write device531and the NMOS select write device532) that are controlled with gate signals that run perpendicular to each other (e.g., one gate signal parallel to the bitline BL and perpendicular to the power rails, and another gate signal perpendicular to the bitline and parallel to the power rails).

When using a fuse, a very large current is used to permanently change the device characteristics. However, there is a possibility that the device characteristics of the fuse510will be shifted if high current flows through the fuse510during read operations. Therefore, in some embodiments, the select read device520much smaller (e.g., the transistor is narrower) than the select write devices (the PMOS select write device531and the NMOS select write device532), which thereby limits or restricts the current during read operations. In some embodiments, the current is restricted by using lower voltages on the gate of the select read device520. In some embodiments, a controller accessing the data stored in the OTP bitcells ensures that the read operation is performed very quickly so that the current flowing through the fuse510during the read operation is a very short pulse. Some embodiments of the present disclosure implement combinations of the above techniques, in some cases with other techniques, to limit or restrict the current flowing through the fuse510during read operations.

Table 2 shows the operation of the bitcell inFIG.5Aaccording to one example of the present disclosure.

FIG.5Bis a circuit diagram of a bitcell500B with an anti-fuse implemented using a capacitor according to one embodiment of the present disclosure. As shown inFIG.5B, a PMOS write device531B (e.g., PMOS transistor or first select write device), a write-once programmable circuit element510is an anti-fuse shown as a capacitor, and an NMOS write device532B (e.g., NMOS transistor) are connected in series between a pair of power rails (e.g., a fuse power rail540B supplying a high voltage VDD and a ground power rail550B supplying a low voltage VSS). The gate of the PMOS transistor or PMOS write device531B is connected to a first control line561B that is perpendicular to a second control line562B connected to the gate of the NMOS transistor or NMOS write device532B or second select write device. The bitcell500B shown inFIG.5Bis substantially similar to the bitcell500shown inFIG.5Awith the fuse510replaced with an anti-fuse510B which may be implemented as a capacitor. The capacitance of the capacitor510B may be designed such that, under read voltages the capacitor510B acts as an open circuit. However, when a rupture voltage is applied across the capacitor510B, the capacitor ruptures such that a conductive path is formed through the capacitor510B. Accordingly, the capacitor510B shown inFIG.5Bmay serve as an anti-fuse implementation of a write-once programmable circuit element.

FIGS.6A and6Bare circuit diagrams of different bitcell designs with a fuse according to one embodiment of the present disclosure. The bitcell600in the embodiment shown inFIG.6Ais similar to the bitcell500shown inFIG.5, except that the select read device620is connected to a middle node690between a PMOS select write device630A and the fuse610(instead of a node between the fuse510and the NMOS select write device532, as shown inFIG.5). Otherwise, the supply power rail640, the ground power rail650, bitline680, first write select line660A, second write select line660B, and second select write device630B operate much the same as corresponding components in the example ofFIG.5. In addition, the embodiment shown inFIG.6Auses a PMOS read select device620(controlled by a read select line670) instead of an NMOS read select device, as shown inFIG.5. In any of the embodiments described above (e.g., as shown inFIGS.2,3A,4A,4B,4C, and5), the read select device may similarly be implemented with a PMOS read select device (e.g., a PMOS transistor) in place of the NMOS transistors illustrated therein, which appropriate corresponding changes in the voltages supplied to the control lines or read select lines connected to the gate electrodes of the read select devices. Likewise, the read select device620shown inFIG.6Amay be implemented using a PMOS transistor (as shown inFIG.6A) or using an NMOS transistor.

The embodiment of the present disclosure shown inFIG.6B, depicts an OTP bitcell601where the two select write devices631A and631B are NMOS select write devices, in a manner similar to the cascaded devices shown inFIG.4B, but with a fuse instead of an anti-fuse. In the embodiment shown inFIG.6A, a fuse611, a first NMOS select write device631A, and a second NMOS select write device631B are connected in series between two power rails (a high voltage power rail641supplying a first voltage such as VDD and a low voltage power rail651suppling a second voltage lower than the first voltage, such as VSS), where the first NMOS select write device631A is controlled by a first write select line661A and the second NMOS select write device631B is controlled by a second write select line661B, and a select read device621(e.g., a PMOS select device), controlled by a read select line671, is connected between a bitline681and a node691, where the node is between the fuse611and the first NMOS select write device631A. In a manner similar to that described above with respect toFIG.4C, embodiments of the present disclosure that include a fuse instead of an anti-fuse may include multiple transistors in the select read device621(e.g., with two NMOS transistors connected in a cascode arrangement).

Accordingly, various aspects of embodiments of the present disclosure relate to one-time programmable (OTP) bitcells. In more detail, some aspects of embodiments relate to OTP bitcells that include additional devices so that high current, low resistance lines can run in parallel and be switched by the additional device using a control signal supplied on a control line running perpendicular to the high current, low resistance lines. Additional transistors may be further included in the bitcells to provide protection from high voltages that are applied during programming of the OTP bitcell, such as rupturing an anti-fuse (to form a permanent conductive path) or rupturing a fuse (to break a conductive path).

A computer-readable design of a one-time programmable bitcell circuit according to the present disclosure may be included within a library of available pre-designed cells or circuit blocks or circuit portions stored on a computer-readable medium (e.g., in a digital representation of a one-time programmable bitcell circuit circuit). This allows the design of a one-time programmable bitcell circuit according to the present disclosure to be placed as a standard circuit cell within a design of an integrated circuit (e.g., a digital representation of the integrated circuit). For example, a one-time programmable bitcell circuit specified by the computer-readable design may be incorporated into the design of a digital or mixed-signal integrated circuit, such that the one-time programmable bitcell circuit can store data associated with a particular instance of the integrated circuit (e.g., in the form of a programmed serial number, identifier, encryption key, or the like).

Specifications for a circuit or electronic structure (which may also be referred to as “instructions, which when executed by a processor, cause the processor to generate a digital representation of the circuit or electronic structure”) may range from low-level transistor material layouts to netlists to high-level description languages such as Verilog or VHDL.