STACKED MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING THE SAME

A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. Delay circuits or other logic may be included to ensure that the refresh operations do not overlap.

DETAILED DESCRIPTION

FIG. 1illustrates a cross-sectional view of an embodiment of a package of a stacked-memory device. Referring toFIG. 1, the stacked memory device10may be embodied within a system-in-package (SiP). That is, the stacked memory device10may be embodied into one package. The stacked memory device10includes a plurality of memory chips20,30,100, and40, and a memory controller60. The memory chips20,30,100, and40may be non-volatile memories, such as, but not limited to, a dynamic random access memories (DRAMs).

The memory controller60is mounted on a package substrate70, when the stacked memory device10is embodied into a SiP. One or more first microbumps61are included to attache the memory controller60to the package substrate70. The package substrate70may be a printed circuit board (PCB). A plurality of solder balls71attaches the package substrate70to a system board or an external or host device.

The memory controller60controls the plurality of memory chips20,30,100, and40. The stacked memory device10may include an application processor instead of the memory controller60in some embodiments. The memory controller60may be included in the application processor, when the stacked memory device10includes the application processor. Also, in alternative embodiments, the application processor may be embodied into a system on chip (SoC), a multimedia processor, or an integrated circuit.

The plurality of memory chips20,30,100, and40are stacked on the memory controller60. The number of the memory chips20,30,100, and40may be vary, for example, based on the intended application. The plurality of memory chips20,30,100, and40may be collectively referred to as a stack50, and each of the memory chips20,30,100, and40may be referred to as a slice. Hereinafter, the term “slice” may be used instead of a memory chip, with the understanding that both terms may be synonymous. One or more second microbumps11may be used for attaching the plurality of memory chips20,30,100, and40with each other.

The memory chips20,30, and100include vertical electrical connection (e.g., conductive) structures13to establish connection with the memory controller60electrically. The electrical connection structures may form at least two paths P1 and P2. The first path P1 transmits a command signal (for example, a write enable signal) to at least one of the plurality of memory chips20,30,100, and40. The second path P2 transmits a refresh control signal for controlling the refresh operation of at least one of the plurality of memory chips20,30,100, and40. The vertical electrical connection structures13may be, for example, through silicon vias (TSVs). In one embodiment, the memory chip40may not include the vertical electrical connection structure.

FIG. 2illustrates an embodiment of one of the plurality of memory chips inFIG. 1. Referring toFIGS. 1 and 2, in this embodiment, each of the plurality of memory chips20,30,100, and40includes a plurality of ranks and a refresh control circuit. The refresh control circuit controls a refresh operation for each of the plurality of ranks. The third memory chip100among the plurality of memory chips20,30,100, and40is explained for convenience of explanation, but the structure of the third memory chip100may be applied to another memory chips20,30, or40in common.

The third memory chip (or third slice100) includes a plurality of ranks110,120,130, and140. Each of the plurality of ranks110,120,130, and140includes a plurality of pads111,121,131, and141corresponding to respective ones of the second microbumps11.

Each of the plurality of memory chips20,30,100, and40performs various operations (for example, refresh operation) independently from one another. Also, each of the plurality of ranks110,120,130, and140performs various operations (for example, refresh operation) independently from one another.

The refresh operation of each of the plurality of ranks110,120,130, and140is controlled by a refresh control circuit150. The refresh control circuit150includes a pad151. A refresh control signal, generated by the memory controller60or another memory chip20,30, or40, may be received by the refresh control circuit150through the pad151. That is, a refresh control signal is transmitted along the second path P2 shown inFIG. 1, and the third slice100receives the refresh control signal through the pad151. The refresh control signal may be, for example, a power oscillator (POSC) signal.

One or more of the ranks in each of the plurality of memory chips20,30,100, and40are electrically connected to each other through the vertical electrical structure13. For example, Rank 3 in the chips are connected and/or Rank 4 in the chips may be connected. Channels are formed among the plurality of memory chips20,30,100, and40. For example, channel CH3 may be formed from a connection of Ranks 3 in the chips and channel CH4 may be formed from a connection of Ranks 4 in the chips.

FIG. 3is a diagram explaining one embodiment of the second path shown inFIG. 1. For convenience of explanation, the path is shown to pass from the memory controller60through the memory chips and pads. Also, the refresh control circuit of each chip is shown. InFIG. 3, the pad for the refresh control circuit is shown to be separate from the refresh control circuit. However, in other embodiments, the pad may be included in the refresh control circuit.

Referring toFIGS. 1 through 3, the memory controller60includes a refresh control signal generator65to generate a refresh control signal, for example, POSC. The refresh control signal POSC is transmitted from the memory controller60to the refresh control circuit25in the first memory chip20. The refresh control circuit25controls the refresh operation of one rank, for example, Rank 4, in response to the refresh control signal POSC. In some embodiments, the refresh control circuit25may generate a refresh control signal POSC, instead of the memory controller60.

The refresh control signal POSC is transmitted to the refresh control signal35of the second memory chip30through pads21and31. The refresh control signal35controls the refresh operation of one rank in response to the refresh control signal POSC.

The refresh control circuit150in memory chip100and the fourth refresh control circuit45in memory chip40receive the refresh control signal POSC through pads151or41similarly to the refresh control circuit25. Thus, the refresh control signal may be sent to the rank in each memory chip that corresponds to a same channel.

FIG. 4is a diagram explaining another embodiment of the second path shown inFIG. 1. Referring toFIGS. 1,2, and4, the memory controller60includes the refresh control signal generator65. The refresh control signal generator65generates a refresh control signal, for example, POSC. In some embodiments, the memory chip20,30,100or40may generate a refresh control signal POSC.

The refresh control signal POSC is transmitted to the first refresh control circuit25through the pad21of the first slice20. The first refresh control circuit25controls the refresh operation of one rank (for example, Rank4) included in the first slice20in response to the refresh control signal POSC.

A first refresh control signal POSC1output from the first refresh control circuit25is transmitted to the second refresh control circuit35through the pad31. The second refresh control circuit35delays the first refresh control signal POSC1and generates a second refresh control signal POSC2. The second refresh control circuit35controls the refresh operation of one rank included in the second slice30in response to the second refresh control signal POSC2and outputs the second refresh control signal POSC2.

The second refresh control signal POSC2output from the second refresh control circuit35is transmitted to the third refresh control circuit150through the pad151. The third refresh control circuit150delays the second refresh control signal POSC2and generates a third refresh control signal POSC3. The third refresh control signal150controls the refresh operation of one rank included in the third slice100in response to the third refresh control signal POSC3and outputs the third refresh control signal POSC3.

The third refresh control signal POSC3output from the third refresh control circuit150is transmitted to the fourth refresh control circuit45through the pad41.

FIG. 5illustrates an embodiment of a refresh control circuit inFIG. 2. Referring toFIGS. 1,2,3, and5, a refresh control circuit150-1includes a refresh control signal generator153, a selector155, and a refresh control block157.

The refresh control signal generator153generates a refresh control signal, for example, POSC signal. In some embodiments, the refresh control signal generator153may be set so as not to be operated.

The selector155outputs one of a first refresh control signal transmitted from the pad151or a second refresh control signal output from the refresh control signal generator153as a refresh control signal. A selecting signal SEL is set such that the selector155selects the first refresh control signal, when the first refresh control signal is generated by the memory controller60or another other slice20,30, or40. On the contrary, a selecting signal SEL is set such that the selector155selects the second refresh control signal, when the first refresh control signal may not be generated by the memory controller60or another slice20,30, or40, that is, when the third slice100generates the second refresh control signal. The selector155may be embodied into a multiplexer or another type of selector circuit.

The refresh control block157counts time in response to the refresh control signal output from the selector155and outputs the refresh control signal into one of the plurality of ranks110,120,130, and140according to the counting result. The operation of the refresh control block157will be described in greater detail below.

FIG. 6illustrates another embodiment of the refresh control circuit shown inFIG. 2. Referring toFIGS. 1,2,3, and6, a refresh control circuit150-2includes a refresh control signal generator161, a first selector163, a delay circuit165, and a second selector167.

The refresh control signal generator161generates a refresh control signal, for example, POSC. In some embodiments, the refresh control signal generator161may be set so as not to be operated.

The first selector163outputs one of a first refresh control signal transmitted from the pad151and a second refresh control signal output from the refresh control signal generator161as a refresh control signal. A first selecting signal SEL1is set such that the first selector163selects the first refresh control signal, when the first refresh control signal is generated by the memory controller60or another slice20,30, or40. On the contrary, a first selecting signal SEL1is set such that the first selector163selects the second refresh control signal, when the first refresh control signal may not be generated by the memory controller60or another slice20,30, or40.

The delay circuit165delays the refresh control signal output from the first selector163and outputs the delayed refresh control signal. The delay circuit165includes a plurality of buffers connected in series.

The second selector167outputs one of the delayed refresh control signals output from the delay circuit165to one of the plurality of ranks110,120,130, and140. The second selecting signal SEL2may be set to have different delay for each memory chip in advance.

FIG. 7illustrates another embodiment of the refresh control circuit shown inFIG. 2. Referring toFIGS. 1,2,4and7, a refresh control circuit150-3includes a refresh control signal generator171, a first selector173, a delay circuit175, and a second selector177.

The refresh control signal generator171generates a refresh control signal, for example, POSC signal. In some embodiments, the refresh control signal generator171may be set so as not to be operated.

The first selector173outputs one of a first refresh control signal POSC2transmitted through the pad151and a second refresh control signal output from the refresh control signal generator171as a refresh control signal in response to a first selecting signal SEL1. The first selecting signal SEL1is set such that the first selector173selects the first refresh control signal POSC2, when the first refresh control signal POSC2is generated by the second slice30. On the contrary, the first selecting signal SEL1is set such that the first selector173selects the second refresh control signal, when the first refresh control signal POSC2is not generated by the memory controller60or the second slice30.

The delay circuit175delays the refresh control signal output from the first selector173and outputs the delayed refresh control signals. The delay circuit175includes a plurality of buffers connected in series.

The second selector177outputs one of the delayed refresh control signals output from the delay circuit175to one of the plurality of ranks110,120,130, and140as a refresh control signal POSC3. Also, the second selector177outputs the selected refresh control signal POSC3to the fourth slice40. A second signal SEL2is set to have different delay for each memory chip in advance.

FIG. 8illustrates an embodiment of one of the plurality of ranks shown inFIG. 2. Referring toFIGS. 1,2, and8, the rank140includes a control logic250, an address register255, a row decoder257, a column decoder259, a plurality of memory cell arrays261, a sense amplifier263, an input/output gate265, a driver267, and a receiver (or an input buffer)269.

The control logic250outputs signals controlling the row decoder257and a column decoder259in response to a plurality of control signals POSC3, CKE, CK #, CS #, WE #, CAS #, and RAS #.

A clock signal CK, a clock enable signal CKE, and a clock bar signal CK # may be output from a clock driver.

A chip enable bar signal CS #, a write enable bar signal WE #, a column address strobe bar signal CAS #, and a row address strobe bar signal RAS # may be output from the memory controller60.

The control logic250may include one or more mode registers251and a command decoder253. Each mode register251stores data for controlling various operation modes of the rank140.

The command decoder253decodes the plurality of control signals CS #, WE #, CAS #, and RAS # and generates control signals for controlling the row decoder257and the column decoder259according to the decoding result. For example, the command decoder53may generate a refresh command when the control signals CS #, RAS #, and CAS # are low and the control signal WE # is high. The refresh command may generate an auto refresh command when the control signal CKE is high and may generate a self refresh command when the control signal CKE is low. The auto refresh operation or the self refresh operation may be performed in response to the refresh control signal POSC.

That is, the command decoder253generates control signals for controlling the row decoder257and the column decoder259according to the endecoded command.

The address register255receives an address ADD including a row address and a column address, transmits the row address into the row decoder257, and transmits the column address into the column decoder259.

The row decoder257decodes a row address received from the address register255in response to a control signal output from the control logic250and selects one of a plurality of word lines according to the decoding result.

Each of the plurality of memory cell arrays labeled as bank 0 through bank 3 includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells for storing data.

The sense amplifier263senses and amplifiers voltage changes of the plurality of bit lines.

The column decoder259decodes a column address output from the address register255and generates a plurality of column selecting signals according to the decoding result.

The input/output gate265transmits data or signals to the sense amplifier263, the driver267, or the receiver269output from the column decoder259.

The input/output gate265transmits data DQi received from the receiver269to the plurality of memory cell arrays261through the driver according to the plurality of column selecting signals output from the column decoder259during the write operation. Also, the input/output gate265transmits a plurality of signals sense amplified by the sense amplifier263to the driver267as a data DQi according to the plurality of column selecting signals output from the column decoder259during the read operation. The driver267outputs the data DQi to the memory controller60.

FIG. 9illustrates an embodiment of a timing diagram for explaining the operation of the stacked memory device inFIG. 1. Referring toFIGS. 1,2, and9, the memory controller60issues auto refresh commands AREF for performing the auto refresh operation with respect to one rank (e.g., Rank 4) in each of the plurality of memory chips20,30,100, and40.

Peak current may be generated when the one rank (e.g., Rank 4) in each of the plurality of memory chips20,30,100, and40performs the auto refresh operation at the same time. This may affect reliability of the memory chips20,30,100, and40.

In accordance with one embodiment, the memory controller60issues auto refresh commands AREF to the one rank in each chip to ensure that the auto refresh operation is not performed by the one rank in each chip at the same time, to thereby reduce the peak current. The auto refresh commands AREF includes a first through a fourth auto refresh commands AREF1˜4.

The first auto refresh command AREF1 is a command for performing the auto refresh operation for one rank (e.g., Rank 4) in the first memory chip20. The second auto refresh command AREF2 is a command for performing the auto refresh operation for one rank (e.g., Rank 4) in the second memory chip30. The third auto refresh command AREF3 is a command for performing the auto refresh operation for one rank (e.g., Rank 4) in the third memory chip100. The fourth auto refresh command AREF4 is a command for performing the auto refresh operation for one rank (e.g., Rank 4) in the fourth memory chip40.

Also, inFIG. 9, ‘tREFI’ is the average periodic refresh interval and ‘tRFC’ is the refresh command period time. As shown, the auto refresh command period time of auto refresh commands AFER1, AREF2, AREF3, and AREF4 do not overlap. Accordingly, peak current may not be generated.

FIG. 10illustrates another embodiment of a timing diagram for explaining the operation of the stacked memory device inFIG. 1. Referring toFIGS. 1 through 3,5, and10, the memory controller60issues self-refresh commands for performing a self-refresh operation for one rank (e.g., Rank 4) in each of the plurality of memory chips20,30,100, and40. Also, the memory controller60generates a refresh control signal, for example, POSC.

The first memory chip20receives the refresh control signal POSC output from the memory controller60through the second path P2. Specifically, the refresh control circuit25of the first memory chip20counts time in response to the refresh control signal POSC and transmits a first refresh control signal POSC1for one rank (e.g., Rank 4) of the first memory chip20according to the counting result. For example, the refresh control circuit25of the first memory chip20transmits the first refresh control signal POSC1to one rank of the first memory chip20when the counted value is 1. The self-refresh operation is performed in the one rank (e.g., Rank 4) of the first memory chip20in response to the first refresh control signal POSC1.

The second memory chip30receives the refresh control signal POSC output from the memory controller60through the second path P2. Specifically, the refresh control circuit35of the second memory chip30counts time in response to the refresh control signal POSC and transmits the second refresh control signal POSC2to one rank (e.g., Rank 4) of the second memory chip30. For example, the refresh control block of the second memory chip30transmits the second refresh control signal POSC2to a rank of the second memory chip30when the counted value is 2. The self-refresh operation is performed in one rank of the second memory chip30in response to the second refresh control signal POSC2.

The third memory chip100receives the refresh control signal POSC output from the memory controller60through the second path P2. Specifically, the refresh control block157of the third memory chip100counts time in response to the refresh control signal POSC and transmits the third refresh control signal POSC3to one rank (e.g., Rank 4) of the third memory chip100. The refresh control block157of the third memory chip100transmits the third refresh control signal POSC3to one rank of the third memory chip100when the counted value is 3. The self-refresh operation is performed in the one rank of the third memory chip100in response to the third refresh control signal POSC3. The memory controller60generates the refresh control signal POSC. Thus, the selector155outputs the refresh control signal output from the pad151in response to a selecting signal SEL.

The fourth memory chip40receives the refresh control signal output from the memory controller through the second path P2. Specifically, a refresh control block of the fourth memory chip40counts time in response to the refresh control signal POSC and transmits a fourth refresh control signal POSC4to one rank (e.g., Rank 4) of the fourth memory chip40. For example, the refresh control block of the fourth memory chip40transmits the fourth refresh control signal POSC4into the one rank of the fourth memory chip40when the counted value is 4. The self-refresh operation is performed in the one rank of the fourth memory chip40in response to the fourth refresh control signal POSC4.

Accordingly, the self refresh operation may not be performed with respect to one rank in each of the plurality of memory chips20,30,100, and40at the same time by using the refresh control signal POSC. That is, peak current may be reduced.

FIG. 11illustrates another embodiment of a timing diagram for explaining the operation of the stacked memory device inFIG. 1. Referring toFIGS. 1 through 3,6, and11, the memory controller60issues self-refresh commands for performing the self-refresh operation with respect to one rank in each of the plurality of memory chips20,30,100, and40. Also, the memory controller60generates a refresh control signal, for example, POSC.

The first memory chip20receives the refresh control signal output from the memory controller60through the second path P2. The refresh control circuit25of the first memory chip20delays the refresh control signal POSC and outputs a first refresh control signal POSC1. The refresh control circuit25of the first memory chip20transmits the first refresh control signal POSC1into one rank of the first memory chip20. The self-refresh operation is performed in the one rank of the first memory chip20in response to the first refresh control signal POSC1.

The second memory chip30receives the refresh control signal POSC1output from the memory controller60through the second path P2. The refresh control circuit35of the second memory chip30delays the refresh control signal POSC and outputs a second refresh control signal POSC2. The refresh control circuit35of the second memory chip30transmits the second refresh control signal POSC2into one rank of the second memory chip30. The self-refresh operation is performed in the one rank of the second memory chip30in response to the second refresh control signal POSC2.

The third memory chip100receives the refresh control signal POSC output from the memory controller60through the second path P2. The refresh control circuit150-2of the third memory chip100delays the refresh control signal POSC and outputs a third refresh control signal POSC3. That is, the second selector167selects one of the plurality of delayed refresh control signals output from the delay circuit165and outputs the same as a third refresh control signal POSC3. The refresh control circuit150-2of the third memory chip100transmits the third refresh control signal POSC3into one rank of the third memory chip100. The self-refresh operation is performed in the one rank of the third memory chip100in response to the third refresh control signal POSC3. The memory controller60generates the refresh control signal POSC. Thus, the first selector163outputs the refresh control signal POSC output from the pad151in response to a first selecting signal SEL1.

The fourth memory chip40receives the refresh control signal output from the memory controller60through the second path P2. The refresh control circuit45of the fourth memory chip40delays the refresh control signal POSC and outputs a fourth refresh control signal POSC4. The refresh control circuit45of the fourth memory chip40transmits the fourth refresh control signal POSC4into one rank of the fourth memory chip40. The self-refresh operation is performed in the one rank of the fourth memory chip40in response to the fourth refresh control signal POSC4.

FIG. 12illustrates another embodiment of a timing diagram for explaining the operation of the stacked memory device inFIG. 1. Referring toFIGS. 1,2,4,7, and12, the memory controller60issues self-refresh commands for performing the self-refresh operation with respect to one rank in each of the plurality of memory chips20,30,100, and40. Also, the memory controller60generates a refresh control signal, for example, POSC.

The first memory chip20receives the refresh control signal POSC output from the memory controller60through the second path P2. The refresh control circuit25of the first memory chip20outputs a first refresh control signal POSC1. The first refresh control signal POSC1and the refresh control signal POSC have the same phase.

The refresh control circuit25of the first memory chip20transmits the first refresh control signal POSC1to one rank of the first memory chip20. The self refresh operation is performed in the one rank of the first memory chip20in response to the first refresh control signal POSC1.

The second memory chip30receives the first refresh control signal output from the first memory chip20through the second path P2. The refresh control circuit35of the second memory chip30delays the refresh control signal POSC1and outputs a second refresh control signal POSC2. The refresh control circuit35of the second memory chip30transmits the second refresh control signal POSC2into one rank of the second memory chip30. The self-refresh operation is performed in the one rank of the second memory chip30in response to the second refresh control signal POSC2.

The third memory chip100receives the second refresh control signal POSC2output from the second memory chip30through the second path P2. The refresh control circuit150-3of the third memory chip100delays the second refresh control signal POSC2and outputs a third refresh control signal POSC3. That is, the second selector177outputs the third refresh control signal POSC3by selecting one of the plurality of delayed refresh control signals output from the delay circuit175. The refresh control circuit153-3of the third memory chip100transmits the third refresh control signal POSC3to one rank of the third memory chip100. The self refresh operation is performed in the one rank of the third memory chip100in response to the third refresh control signal POSC3.

The fourth memory chip40receives the third refresh control signal POSC3output from the third memory chip100through the second path P2. Specifically, the refresh control circuit45of the fourth memory chip40delays the third refresh control signal POSC3and output a fourth refresh control signal POSC4. The refresh control circuit45of the fourth memory chip40transmits the fourth refresh control signal POSC4to one rank of the fourth memory chip40. The self-refresh operation is performed in the one rank of the fourth memory chip40in response to the fourth refresh control signal POSC4.

FIG. 13illustrates an embodiment of a method for operating the stacked memory device shown inFIG. 1. Referring toFIGS. 1 through 3,5,10, and13, the refresh control circuit150of the third slice100receives a refresh control signal, in operation S10.

The refresh control block157counts time in response to the refresh control signal, in operation S20. The refresh control block157transmits a third refresh control signal POSC3to one rank (e.g., Rank 4) of the third slice100according to the counting result. The self refresh operation is performed in one rank of the third slice100in response to the third refresh control signal POSC3, in operation S30, when the counted value is 3.

FIG. 14illustrates another embodiment of a method for operating the stacked memory device inFIG. 1. Referring toFIGS. 1 through 3,6,11, and14, the refresh control circuit150of the third slice100receives a refresh control signal POSC, in operation S100. The refresh control signal POSC is received from the memory controller60.

The delay circuit165delays the refresh control signal POSC and outputs a plurality of delayed refresh control signals. The second selector167outputs one of the plurality of delayed refresh control signals as a third refresh control signal POSC3, in operation S200.

Any one of the plurality of ranks (e.g., Rank 4 in the third slice100performs the self-refresh operation in response to the third refresh control signal POSC3, in operation S300. The refresh control signal150of the third slice100receives a second refresh control signal POSC2in some embodiments. The second refresh control signal POSC2is received from the second slice30.

Referring toFIG. 7, the delay circuit175delays the second refresh control signal POSC2and outputs a plurality of delayed refresh control signals. The second selector177outputs one of the plurality of delayed refresh control signals as a third refresh control signal POSC3in response to a second select signal SEL2.

FIG. 15illustrates an embodiment of a memory system including the stacked memory device inFIG. 1. Referring toFIGS. 1 and 15, the memory system1500may be embodied into a portable device using or supporting an MIPI interface, personal digital assistant (PDA), portable multi-media player (PMP), tablet PC, or smart phone.

The memory system1500includes an application processor1510, a stack50, a camera module1540, and a 3D display1550.

The stack includes the plurality of memory chips20,30,100, and40inFIG. 1.

The application processor1510includes the memory controller60inFIG. 1.

A CSI host1512embodied in the application processor1510performs serial communication with a CSI device1541of the camera module1540through a camera serial interface (CSI). At this time, for example, the CSI host1512includes a deserializer DES, and the CSI device1541includes a serializer SER.

A DSI host1511embodied in the application processor1510performs serial communication with a DSI device1551of the 3D display1550through a display serial interface (DSI). At this time, for example, the DSI host1511includes a serializer SER, and the DSI device1551includes a deserializer DES.

The memory system1500further includes an RF chip1560communicating with the application processor1510. A PHY1513of the memory system1500and a PHY1561of the RF chip1560exchange data according to MIPI DigRF.

The memory system1500further includes a GPS receiver1520, a storage1570, a mike1580, and a speaker1590, and the memory system1500communicates by using a Wimax1530, a WLAN1500, and a UWB1610.

In the aforementioned embodiments, the same number rank of each memory chip is described as corresponding to a same channel. However, in other embodiments, different number ranks may correspond to a channel. Also, in the aforementioned embodiments, only one rank in each chip is subject to a refresh operation. However, in other embodiments, more than one rank in each chip may be refreshed at the same or different times, for example, in response to a POSC or other refresh control signal transmitted along path P2 or another path. Also, a refresh operation may be performed for multiple ranks in one chip independently and at different times from refresh operations performed for rank(s) in other chips.

The stacked memory device, the system including the same, and the method for operating the system according to one or more of the aforementioned embodiments have an effect of reducing peak current during the refresh operation in the stacked memory device by preventing the refresh operation from being performed in ranks included in the memory system at the same time.