Two stage voltage boost circuit, IC and design structure

A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Ser. No. 12/031,729, filed Feb. 15, 2008, currently pending and is related to US Patent Application having U.S. Ser. No. 12/031,731, filed Feb. 15, 2008, and currently pending. All related US Applications referenced above have common inventors and are assigned to the same assignee.

BACKGROUND OF THE INVENTION

The disclosure relates generally to voltage boost circuits.

A voltage boost circuit or charge pump is an electronic circuit that uses capacitors for energy storage to create a higher voltage power source. One challenge with charge pumps is that when creating a higher voltage power source, such as in a three times a supply voltage (3× Vdd) charge pump, voltages may be generated in excess of the oxide-stress limit of a field effect transistor (FET), i.e., a stress limit of the gate oxide thickness. Previous approaches have used FET devices with an oxide stress limit greater than the output voltage of the pumping system. This situation forces inclusion of a thicker, and typically lower performance FET in a technology menu which adds cost and complexity such as additional mask steps and extra characterization requirements. For example, a “medium” gate oxide thickness FET may have a gate oxide of approximately 22 Angstroms (Å), while a thicker gate oxide, lower performance FET may require a gate oxide of approximately 52 Å. Gate voltage controllers for generating a safe gate drive level below an excessive stress level of the oxide have been implemented, but they are limited in terms of the amount of boost permissible and require a precision current source for calibration.

BRIEF SUMMARY OF THE INVENTION

A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.

A first aspect of the disclosure provides a voltage boost circuit for boosting a supply voltage, the voltage boost circuit comprising: a first stage for boosting the supply voltage to a first boosted voltage, the first stage including a first voltage boost capacitor with a low node and a high node, the high node having an output of the first boosted voltage; a first passgate coupled to the high node of the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage, the second stage including a second voltage boost capacitor with a low node coupled to the high node of the first stage and a high node; a second pass-gate coupled to the high node of the second stage for transferring the second boosted voltage to an output node; and a gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second pass-gate.

A second aspect of the disclosure provides an integrated circuit (IC) designed to substantially operate at a supply voltage, the IC comprising: circuitry requiring a boosted voltage relative to the supply voltage; a voltage boost circuit including: a first stage for boosting the supply voltage to a first boosted voltage, the first stage including a first voltage boost capacitor with a low node and a high node, the high node having an output of the first boosted voltage, a first passgate coupled to the high node of the first stage, a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate, a second stage for boosting the first boosted voltage to a second boosted voltage, the second stage including a second voltage boost capacitor with a low node coupled to the high node of the first stage and a high node, wherein the second boosted voltage is the boosted voltage required by the circuitry; a second passgate coupled to the high node of the second stage for transferring the second boosted voltage to an output node, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.

A third aspect of the disclosure provides a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: an integrated circuit (IC) designed to substantially operate at a supply voltage, the IC including: circuitry requiring a boosted voltage relative to the supply voltage; a voltage boost circuit including: a first stage for boosting the supply voltage to a first boosted voltage, the first stage including a first voltage boost capacitor with a low node and a high node, the high node having an output of the first boosted voltage, a first passgate coupled to the high node of the first stage, a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate, a second stage for boosting the first boosted voltage to a second boosted voltage, the second stage including a second voltage boost capacitor with a low node coupled to the high node of the first stage and a high node, wherein the second boosted voltage is the boosted voltage required by the circuitry, a second passgate coupled to the high node of the second stage for transferring the second boosted voltage to an output node, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows one embodiment of a voltage boost circuit100according to the disclosure. Voltage boost circuit100may be used in an integrated circuit (IC)102designed to substantially operate at a supply voltage Vdd. IC102, however, includes circuitry104requiring a boosted voltage relative to supply voltage Vdd. Voltage boost circuit100presents a two stage voltage pump circuit that generates an output, boosted voltage (on output node NW_VPP) approximately 3 times a supply voltage Vdd. For example, output boosted voltage of approximately 2.8 Volts (V) for a supply voltage Vdd of approximately 1V may be obtained using voltage boost circuit100. However, as will be described herein, in contrast to conventional voltage boost circuits capable of attaining a 3Vdd boosted voltage, voltage boost circuit100may use lower voltage limit field effect transistors (FET) without lower performance, thicker gate oxide FETs. For example, voltage boost circuit100may use approximately 22 Angstrom (Å) gate oxide thickness FETs that can only withstand a gate oxide stress voltage of approximately 1.7V. As described herein, adjustment of the FET overdrive levels has been made so boosted voltages can be generated with FETs having lower voltage limits.

In one embodiment, voltage boost circuit100includes a first stage110and a second stage112. Each stage110,112, respectively, includes a voltage boost capacitor C3, C4having a low node L1, L2and a high node V1, V2. Respectively, each stage110,112also includes a restore circuit120,122connecting ground-level to its low node L1, L2, and a precharge circuit130,132connected to each high node V1, V2. Output passgates T32, T31are also connected to each high node V1, V2, respectively, with a gate control circuit140,142connected to each passgate T32, T31providing an on-state gate voltage level adjusted to reduce oxide stress. Voltage boost circuit100may also include a timing signal circuit150, which may include any now known or later developed circuitry for generating timing signals AA, BB, G1and G2, described in greater detail herein.

FIG. 2shows a 2-phase clock diagram of non-overlapping inputs AA and BB, non-overlapping inputs G1and G2, capacitor nodes L1, V1, L2, V2and output, boosted voltage NW_VPP. In one embodiment, non-overlapping inputs AA and BB may be approximately at supply voltage level inputs, e.g., approximately 1.1V, and non-overlapping inputs G1and G2may be approximately at a stress limit voltage VPP. Stress limit voltage VPP is set at a voltage stress limit of devices used for a respective maximum supply voltage. For example, stress limit voltage VPP may be approximately 1.7V for an oxide thickness of approximately 22 Angstroms.

Referring toFIGS. 1 and 2collectively, in a precharge phase, input BB drives a restore device120(i.e., transistor T40) of first stage110to restore low node L1of first stage110to ground (˜0V). Contemporaneously, input G1charges high node V1of first stage110to a supply voltage Vdd by precharge circuit130(i.e., FET T42), and the gate of first stage passgate T32is held in an off state at stress limit voltage VPP level by gate control circuit140(i.e., FET T36) controlled by input G2. Here, stress limit voltage VPP may be approximately twice supply voltage Vdd, e.g., approximately 1.7V. Second stage112is also held in precharge with low node L2connected to ground (˜0V) by restore circuit122(i.e., FETs T33and T34) controlled by input G1, and second stage high node V2is pre-charged to supply voltage Vdd by precharge circuit132(i.e., FET T45) controlled by input G1. Passgate T31is held in an off state by gate control circuit142by input G2.

In a boost or transfer phase, input AA is driven high by timing circuit150which drives first stage low node L1to supply voltage Vdd through FET T41. High node V1increases to almost twice the supply voltage to 2Vdd. Conventionally, the twice supply voltage 2Vdd present on first stage high node V1would exceed an oxide stress voltage limit of first stage passgate T32, e.g., of approximately 1.7V. This situation may occur, for example, when passgate T32includes a 22 Å thick gate oxide. To address this situation, however, gate control circuit140includes a resistive voltage divider144formed by resistor R1and resistor R2activated by FETs T37and T35, which produces an intermediate gate voltage (G2BUF) of approximately 300 millivolts (mV). (Resistive voltage divider144is disconnected from supply voltage Vdd by FET T35in the precharge phase by signal AABUF, which is an inversion of input AA). Accordingly, with a gate voltage level of first stage passgate T32held no lower than 300 mV, a first boosted voltage level on first stage high node V1of approximately 2Vdd (e.g., ˜1.7V) can be passed without exceeding the oxide stress voltage limit of first stage passgate T32. Hence, first stage passgate T32may include lower voltage limit FETs, e.g., 22 Å gate oxide thickness FET, which reduces the additional cost and complexity of adding in a thicker gate oxide, lower performance FET for first stage passgate T32.

With passgate T32in its on stage, first boosted voltage on first stage high node V1is transferred to second stage low node L2. Second stage high node V2then increases to a second boosted voltage of approximately 3Vdd (e.g., ˜2.8V). Conventionally, a 3Vdd gate voltage present on second stage high node V2would pose another gate oxide stress voltage level issue for passgate T31. However, gate control circuit142provides a low level voltage (e.g., ˜1.1V) by action of a resistive divider146formed by resistor R3and resistor R4from output node NW_VPP and pulldown FETs T37and T38, which are controlled by input G2. Hence, an on-state gate to source voltage level of second passgate T31is approximately at a stress limit voltage VPP for a maximum supply voltage thereof. (The stress an FET experiences is proportional to the source/drain voltage minus its gate voltage. To operate in a safe region this gate-source voltage Vgs, gate-drain voltage Vgd must be held below the oxide stress limit which, for example, may be 1.7V for a 22 Å device. In an embodiment with an output voltage at the drain of output passgate T31of 2.8V, the gate voltage may be 1. V or above to stay below the oxide stress limit. In a second embodiment, when the passgate T31voltage may be 2.95V at a higher supply voltage Vdd level, the gate may be at 1.25V or higher. The resistor stack is designed such that the oxide stress limit is not exceeded at the maximum power supply voltage.) Second boosted voltage of approximately thrice the supply voltage 3Vdd on high node V2is transferred to output node NW_VPP by second stage passgate T31.

In one embodiment, this output boosted voltage may be approximately 2.95V with a supply voltage Vdd of 1.1V. Second stage passgate T31, however, receives an on-state gate voltage level (e.g., ˜1.25V) which does not exceed a gate oxide voltage stress limit of a low voltage FET, which reduces the additional cost and complexity of adding in a thicker gate oxide, lower performance FET for second stage passgate T31.

Second stage passgate T31is turned off without the use of high-voltage level translated phases by resistive coupling of the gate node thereof to the drain node thereof by resistor R4of gate control circuit140. In one embodiment, a clock frequency of voltage boost circuit100may be, for example, 74 megaHertz (MHz), which is slow enough to allow resistors R3and R4of resistive divider146to be sized large enough to consume a relatively small amount of the total voltage boost circuit100capacity. In one embodiment, resistor R3is 8K-ohms and resistor R4is 10K-ohms, drawing a root mean square (RMS) current of about 80 micro amps.

During the boost phase, precharge circuit132(i.e., FET T45) needs to be off to prevent output charge from bleeding back through to supply voltage Vdd. Conventional practice is to use stress limit voltage VPP, but this voltage is regulated to a voltage level less than high node V2of second stage122, while stress limit voltage VPP may be regulated to approximately 1.7V. Consequently, high node V2of second stage122can rise to approximately 2.9V, causing part of the charge to pass through FET T45of precharge circuit132and into a supply voltage Vdd node. Since stress limit voltage VPP is regulated to a lower voltage than high node V2of second stage112, it is insufficient to use stress limit voltage VPP to turn off precharge circuit132. In order to address this situation, precharge circuit132resistively couples, through register R5, output node NW_VPP (indicated as G1BUF2) to a gate of FET T45. In contrast, in the precharge phase, precharge circuit132connects G1BUF2to ground (˜0V), through FETs T44and T43when timing signal G1goes high. In the boost phase of operation, when timing signal G1is at ground, FET T43is isolated from output node NW_VPP (e.g., ˜2.95V) on node G1BUF2by FET T44, which has supply voltage Vdd level on its gate. Similarly, the gates of FET T34of restore circuit122and FET T38of gate control circuit142are shielded from boosted voltages by shielding FETs T33and T37, respectively. As a result, precharge circuit132can swing between ground (˜0V) and output node NW_VPP (3Vdd) without reliability concerns. Hence, precharge circuit132can be completely turned off in the boost phase, preventing leakage through precharge circuit132transistor T45.

A two stage voltage boost circuit100as described herein uses voltage levels other than ground, supply voltage Vdd and output, boosted voltage (3Vdd) to control the on and off levels of passgates T31, T32. Hence, the use of the disclosed resistor structures obviates the need for boosted phases and associated level translators.

It is understood that while particular illustrative electronic parameter levels (e.g., voltages, frequency, resistance, etc.) have been presented herein, the values presented are not limiting of the claimed disclosure since those with ordinary skill in the art will recognize that variations in the particular dimensions and structure of voltage boost circuit100may readily provide different electronic parameter levels.

Voltage boost circuit100(FIG. 1) as described above may be part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and coded as a set of instructions on machine readable removable or hard media (e.g., residing on a graphical design system (GDS) storage medium).FIG. 3shows a block diagram of an exemplary design flow900used for example, in semiconductor design, manufacturing, and/or test. Design flow900may vary depending on the type of IC being designed. For example, a design flow900for building an application specific IC (ASIC) may differ from a design flow900for designing a standard component. Design structure920is preferably an input to a design process910and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure920comprises an embodiment of the disclosure as shown inFIG. 1in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure920may be contained on one or more machine readable medium. For example, design structure920may be a text file or a graphical representation of an embodiment of the disclosure as shown inFIG. 1. Design process910preferably synthesizes (or translates) an embodiment of the disclosure as shown inFIG. 1into a netlist980, where netlist980is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist980is re-synthesized one or more times depending on design specifications and parameters for the circuit.

Design process910may include using a variety of inputs; for example, inputs from library elements930which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a supply manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications940, characterization data950, verification data960, design rules970, and test data files985(which may include test patterns and other testing information). Design process910may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process910without deviating from the scope and spirit of the disclosure. The design structure of the disclosure is not limited to any specific design flow.

Design process910preferably translates an embodiment of the disclosure as shown inFIG. 1, along with any additional integrated circuit design or data (if applicable), into a second design structure990. Design structure990resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure990may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the disclosure as shown inFIG. 1. Design structure990may then proceed to a stage995where, for example, design structure990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.