External connection pad for semiconductor device package

At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, and an external connection pad tapered from a top surface to a bottom surface. The second patterned conductive layer includes a pad and a trace adjacent to the pad. The external connection pad is disposed on the pad of the second patterned conductive layer. A bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer.

BACKGROUND

1. Technical Field

The present disclosure relates to a substrate for a semiconductor device package, and to a substrate having an external connection pad that narrows, or tapers, from a top surface to a bottom surface and disposed on a pad of a patterned conductive layer.

2. Description of the Related Art

As miniaturization of semiconductor device packages progress, quantity and width/pitch of patterned conductive layers (e.g. pads or traces) in a substrate can be made small. This may present some challenges, such as a misalignment issue, a bridging/short-circuit issue, a thickness issue or other issues.

SUMMARY

In some embodiments, according to one aspect, a substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, and an external connection pad tapered from a top surface to a bottom surface. The second patterned conductive layer includes a pad and a trace adjacent to the pad. The external connection pad is disposed on the pad of the second patterned conductive layer. A bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer.

In some embodiments, according to another aspect, a semiconductor device package includes a substrate, a semiconductor device, and a connection element. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, and an external connection pad tapered from a top surface to a bottom surface. The second patterned conductive layer includes a pad and a trace adjacent to the pad. The external connection pad is disposed on the pad of the second patterned conductive layer. A bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer. The semiconductor device is disposed on the substrate and electrically connected to the external connection pad of the substrate. The connection element is disposed adjacent to the first surface of the first dielectric layer and electrically connected to the first patterned conductive layer.

In some embodiments, according to another aspect, a method for manufacturing a semiconductor device package includes: providing a first dielectric layer having a first surface and a second surface opposite to the first surface; forming a first patterned conductive layer adjacent to the first surface of the first dielectric layer; forming a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, the second patterned conductive layer including a pad and a trace adjacent to the pad; forming an external connection pad on the pad of the second patterned conductive layer, wherein the external connection pad is tapered from a top surface to a bottom surface, and a bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer; disposing a semiconductor device on the external connection pad through an interconnect element; and disposing a connection element on the first patterned conductive layer.

DETAILED DESCRIPTION

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

FIG. 1Ais a cross-sectional view of a substrate1in accordance with some embodiments of the present disclosure. The substrate1includes a first dielectric layer10, a first patterned conductive layer11, a second dielectric layer12, a second patterned conductive layer13, a passivation layer14and an external connection pad17.

The first dielectric layer10has a surface101and a surface102opposite to the surface101. The first dielectric layer10has a thickness ranged from approximately 5 micrometers (μm) to approximately 10 μm. In some embodiments, the first dielectric layer10may include an organic layer, such as a solder mask, a polyimide (PI), an epoxy, an Ajinomoto build-up film (ABF), a polypropylene (PP), a molding compound, or a dry film. The first dielectric layer10may include an inorganic layer, such as silicon (Si), a glass, or a ceramic.

The first patterned conductive layer11is disposed adjacent to the surface101of the first dielectric layer10. The first patterned conductive layer11is embedded in the surface101of the first dielectric layer10. A bottom surface of the first patterned conductive layer11is partially exposed by the passivation layer14. The bottom surface of the first patterned conductive layer11includes a recessed or sunken portion (e.g. which is exposed by the passivation layer14).

The passivation layer14is disposed on the surface101of the first dielectric layer10. The passivation layer14defines an opening to expose the sunken portion of the first patterned conductive layer11. A width of the opening may be approximately equal to a width of the sunken portion of the first patterned conductive layer11. The passivation layer14has a thickness ranged from approximately 7 μm to approximately 13 μm. In some embodiments, the passivation layer14may be a solder mask.

The second patterned conductive layer13is disposed adjacent to the surface102of the first dielectric layer11. The second patterned conductive layer13is electrically connected to the first patterned conductive layer11via an interconnection via. The second patterned conductive layer13comprises a pad131and a trace132adjacent to the pad131. In some embodiments, the pad131and the trace132may include a seed layer13a. The seed layer13amay include titanium (Ti), a titanium-copper alloy (TiCu), another metal, an alloy, or other suitable materials. The second patterned conductive layer13has a thickness t (e.g. as shown inFIG. 1B). The pad131has a width L (e.g. as shown inFIG. 1B).

The external connection pad17is disposed on the pad131of the second patterned conductive layer13.

In one or more embodiments, at least one portion of the trace132of the second patterned conductive layer13adjacent to the pad131is covered in a projective area of the external connection pad17(e.g. a projection of the external connection pad17in a direction towards the first dielectric layer10can overlap the at least one portion of the trace132). In one or more embodiments, at least one portion of another pad131adjacent to the pad131under the external connection pad17is covered in a projective area of the external connection pad17(e.g. a projection of the external connection pad17in a direction towards the first dielectric layer10can overlap the at least one portion of the another pad131). Under this arrangement, a surface density of conductive components including the pad131and the trace132of the second patterned conductive layer13can be increased. The surface area of the first dielectric layer10can thus be efficiently used. In some embodiments, an edge of the trace132is adjacent to or in contact with an edge of the projective area of the external connection pad17(e.g. the protrusion edge175is substantially coplanar with the edge of the trace132).

FIG. 1Bis a cross-sectional view of the external connection pad17according to some embodiments of the present disclosure. The second dielectric layer12is disposed on the surface102of the first dielectric layer10. The second dielectric layer12covers the second patterned conductive layer13and at least part of a side wall173of the external connection pad17. A protrusion edge175of the external connection pad17(an edge of a protruding portion of the external connection pad17, e.g. a portion that protrudes along the second dielectric layer12) is on a top surface of the second dielectric layer12. A bottom of the protrusion edge175of the external connection pad17is directly on the top surface of the second dielectric layer12. The second dielectric layer12has a thickness p. In some embodiments, the second dielectric layer12may include an organic layer, such as a solder mask, a PI, an epoxy, an ABF, a PP, a molding compound, or a dry film. The second dielectric layer12may include an inorganic layer, such as Si, a glass, or a ceramic.

The external connection pad17has a top surface171, a bottom surface172, and the side wall173(e.g. extending between the top surface171and the bottom surface172). The side wall173and the top surface of the second dielectric layer12define a joint A. In some embodiments, the top surface171of the external connection pad17may have a convex shape or a concave shape, or a substantially planar shape. The external connection pad17narrows, or tapers from the top surface171to the bottom surface172. In some embodiments, the external connection pad17includes a conductive body170and a seed layer174. The conductive body170may include copper (Cu), silver (Ag), gold (Au), another metal, an alloy, or other suitable materials. The seed layer174may include Ti, TiCu, another metal, an alloy, or other suitable materials. The external connection pad17has a protrusion edge175. The protrusion edge175includes a protrusion edge of the conductive body170and a protrusion edge of the seed layer174.

At least one of the pads131of the second patterned conductive layer13(e.g. the pad on which the external connection pad17is disposed) has a thickness t. The pad131of the second patterned conductive layer13has a width L. In some embodiments, the thickness t of the second patterned conductive layer13is ranged from approximately 2 μm to approximately 3 μm. The width L of the pad131is ranged from approximately 2 μm to approximately 5 μm. The external connection pad17has a bottom width B. The external connection pad17has a top width D (e.g. a width defined by a top of a recess in the second dielectric layer in which the external connection pad17is disposed). The external connection pad17has a top edge width D′ (e.g. as measured from edge to edge, such as from a first protrusion edge175to a second protrusion edge175disposed opposite to the first protrusion edge175). The protrusion edge175has a width d. The top edge width D′ of the external connection pad17is approximately equal to the top width D of the external connection pad17plus two widths d (that is, is approximately equal to 2 times d). The second dielectric layer12has a thickness p. In some embodiments, the thickness p of the second dielectric layer12is ranged from approximately 3 μm to approximately 12 μm.

In some embodiments, an angle θ between an imaginary line extended from the side wall173of the external connection pad17and an imaginary line extended from the bottom surface172of the external connection pad17is selected in accordance with the following equation:

where p is a thickness of the second dielectric layer12, t is a thickness of the second patterned conductive layer13, and x is a distance between an edge of the bottom surface172of the external connection pad17(e.g. an edge closest to the joint A) and a vertical imaginary line extended from the joint A. The parameter x is a horizontal distance between the edge of the bottom surface172of the external connection pad17and the vertical imaginary line extended from the joint A. The parameter x is a minimum distance between the edge of the bottom surface172of the external connection pad17and the vertical imaginary line extended from the joint A.

In some embodiments, the bottom width B of the external connection pad17is ranged from approximately 4 μm to approximately 15 μm. The top width D of the external connection pad17is ranged from approximately 6 μm to approximately 17.5 μm. The top width D′ of the external connection pad17is ranged from approximately 8 μm to approximately 19.5 μm. The width d of the protrusion edge175is ranged from approximately 0.8 μm to approximately 1.2 μm. The horizontal distance x is ranged from approximately 1.1 μm to approximately 4.7 μm. The thickness t of the second patterned conductive layer13is ranged from approximately 2 μm to approximately 3 μm. The thickness p of the second dielectric layer12is ranged from approximately 3 μm to approximately 12 μm. In some embodiments, the parameters of the thickness p, the thickness t and the horizontal distance x may be specifically selected such that the angle θ and the parameters satisfy design specifications of a semiconductor device package.

FIG. 1Cis a cross-sectional view of the external connection pad17according to some embodiments of the present disclosure. The structure ofFIG. 1Cis similar to the structure ofFIG. 1B, except that a portion of the trace132adjacent to the pad131is disposed under the external connection pad17. The structure ofFIG. 1Cis similar to the structure ofFIG. 1B, except that a portion of the trace132adjacent to the pad131disposed within a projective area of the external connection pad17. At least one portion of another pad131adjacent to the pad131under the external connection pad17is within a projective area of the external connection pad17.

FIG. 2Ais a cross-sectional view of a substrate2in accordance with some embodiments of the present disclosure. The substrate2includes a first dielectric layer10, a first patterned conductive layer11, a second dielectric layer12, a second patterned conductive layer23, a passivation layer14and an external connection pad27.

The first dielectric layer10has a surface101and a surface102opposite to the surface101.

The first patterned conductive layer11is disposed adjacent to the surface101of the first dielectric layer10. The first patterned conductive layer11is embedded in the surface101of the first dielectric layer10. A bottom surface of the first patterned conductive layer11is partially exposed by the passivation layer14. The bottom surface of the first patterned conductive layer11includes a recessed or sunken portion.

The passivation layer14is disposed on the surface101of the first dielectric layer10. The passivation layer14defines an opening to expose the sunken portion of the first patterned conductive layer11. A width of the opening may be approximately equal to a width of the sunken portion of the first patterned conductive layer11.

The second patterned conductive layer23is disposed adjacent to the surface102of the first dielectric layer11. The second patterned conductive layer23is electrically connected to the first patterned conductive layer11via an interconnection via. The second patterned conductive layer23comprises a first pad231, a trace232and a second pad233. A width of the first pad231is greater than a width of the second pad233. In some embodiments, the trace232is adjacent to the first pad231. The second pad233is adjacent to the first pad231. In some embodiments, the first pad231, the trace232and the second pad233may include a seed layer23a(e.g. as shown inFIG. 2B). The seed layer23amay include Ti, TiCu, another metal, an alloy, or other suitable materials. The second patterned conductive layer23has a thickness t. The first pad231has a width L.

The external connection pad27is disposed on the first pad231of the second patterned conductive layer23.

In one or more embodiments, at least one portion of the trace232of the second patterned conductive layer23adjacent to the first pad231is covered in a projective area of the external connection pad27(e.g. a projection of the external connection pad27in a direction towards the first dielectric layer10can overlap the at least one portion of the trace232). In one or more embodiments, at least one portion of the second pad233adjacent to the first pad231is covered in the projective area of the external connection pad27(e.g. a projection of the external connection pad27in a direction towards the first dielectric layer10can overlap the at least one portion of the second pad233). Under this arrangement, a surface density of conductive components including the first pad231, the trace232and the second pad233of the second patterned conductive layer23can be increased. The surface area of the first dielectric layer10can be efficiently used. In some embodiments, an edge of the trace232is adjacent to or in contact with an edge of the projective area of the external connection pad27(e.g. the protrusion edge275is substantially coplanar with the edge of the trace232).

The second dielectric layer12is disposed on the surface102of the first dielectric layer10. The second dielectric layer12covers the second patterned conductive layer23and at least part of a side wall273of the external connection pad27. A protrusion edge275of the external connection pad27is on a top surface of the second dielectric layer12. A bottom of the protrusion edge275of the external connection pad27is directly on the top surface of the second dielectric layer12. The second dielectric layer12has a thickness p.

FIG. 2Bis a cross-sectional view of the arrangement of the external connection pad27according to some embodiments of the present disclosure.

The external connection pad27has a top surface271, a bottom surface272, and the side wall273(e.g. extending between the top surface271and the bottom surface272). The side wall273and the top surface of the second dielectric layer12define a joint A. In some embodiments, the top surface271of the external connection pad27may have a convex shape or a concave shape. The external connection pad27narrows, or tapers, from the top surface271to the bottom surface272. In some embodiments, the external connection pad27includes a conductive body270and a seed layer274. The conductive body270may include Cu, Ag, Au, another metal, an alloy, or other suitable materials. The seed layer274may include Ti, TiCu, another metal, an alloy, or other suitable materials. The external connection pad27is located directly on a top surface of the first pad231of the second patterned conductive layer23. The external connection pad27has a protrusion edge275. The protrusion edge275includes a protrusion edge of the conductive body270and a protrusion edge of the seed layer274.

The pad231of the second patterned conductive layer23has a thickness t. The first pad231of the second patterned conductive layer23has a width L. In some embodiments, the thickness t of the second patterned conductive layer23is ranged from approximately 2 μm to approximately 3 μm. The width L of the first pad231is ranged from approximately 4 μm to approximately 15 μm. A width of the second pad233is ranged from approximately 2 μm to approximately 5 μm. The protrusion edge275has a width d. The external connection pad27has a bottom width B. The external connection pad27has a top width D. The external connection pad27has a top edge width D′. The top edge width D′ of the external connection pad27is approximately equal to the top width D of the external connection pad27plus two widths d. The bottom width B of the external connection pad27is greater than or approximately equal to the width L of the first pad231. In some embodiments, the thickness p of the second dielectric layer12is ranged from approximately 3 μm to approximately 15 μm. The pad231is separated from the trace232by a distance s.

In some embodiments, an angle θ between the side wall273of the external connection pad27and an imaginary line extended from the bottom surface272of the external connection pad27is defined in accordance with the following equation:

θ=tan-1⁡(p-tx)
where p is a thickness of the second dielectric layer12, t is a thickness of the second patterned conductive layer23, and x is a distance between an edge of the bottom surface272of the external connection pad27and a vertical imaginary line extended from the joint A. The parameter x is a horizontal distance between the edge of the bottom surface272of the external connection pad27and the vertical imaginary line extended from the joint A. The parameter x is a minimum distance between the edge of the bottom surface272of the external connection pad27and the vertical imaginary line extended from the joint A. In some embodiments, the value of the parameter x may be approximately equal to the value of the parameter s. In some embodiments, the parameters of the thickness p, the thickness t and the distance x may be specifically selected such that the angle θ and the parameters satisfy design specifications for a semiconductor device package.

In some embodiments, the value of parameter x plus the value of parameter d may be approximately equal to or greater than the value of the parameter s. The angle θ is selected in accordance with the following equation:

FIG. 2Cis an angle table of the angle θ for the substrate2corresponding to some embodiments of the present disclosure. In some embodiments, the angle θ is less than or approximately equal to 80.6 degrees, where about 3 μm≤p≤about 8 μm, about 2 μm≤t≤about 3 μm, and about 1 μm≤x≤about 2 μm. In some embodiments, the angle θ is less than or approximately equal to 71.6 degrees, where about 3 μm≤p≤about 5 μm, about 2 μm≤t≤about 3 μm, and about 1 μm≤x≤about 2 μm. In some embodiments, the angle θ is less than or approximately equal to 45 degrees, where about 3 μm≤p≤about 5 μm, about 2 μm≤t≤about 3 μm, and about 1 μm≤x≤about 2 μm. In some embodiments, the angle θ is less than or approximately equal to 26.6 degrees, where p=about 3 μm, t=about 2 μm, and x=about 2 μm.

FIG. 3Ais a cross-sectional view of a substrate3in accordance with some embodiments of the present disclosure. The substrate3includes a first dielectric layer10, a first patterned conductive layer11, a second dielectric layer12, a second patterned conductive layer33, a passivation layer14and an external connection pad37.

The first dielectric layer10has a surface101and a surface102opposite to the surface101.

The first patterned conductive layer11is disposed adjacent to the surface101of the first dielectric layer10. The first patterned conductive layer11is embedded in the surface101of the first dielectric layer10. A bottom surface of the first patterned conductive layer11is partially exposed by the passivation layer14. The bottom surface of the first patterned conductive layer11includes a recessed or sunken portion.

The passivation layer14is disposed on the surface101of the first dielectric layer10. The passivation layer14defines an opening to expose the sunken portion of the first patterned conductive layer11. A width of the opening may be approximately equal to a width of the sunken portion of the first patterned conductive layer11.

The second patterned conductive layer33is disposed adjacent to the surface102of the first dielectric layer11. The second patterned conductive layer33is electrically connected to the first patterned conductive layer11via an interconnection via. The second patterned conductive layer33comprises a first pad331, a trace332and a second pad333. A width of the first pad331is greater than a width of the second pad333. In some embodiments, the trace332is adjacent to the first pad331. The second pad333is adjacent to the first pad331. In some embodiments, the first pad331, the trace332and the second pad333may include a seed layer33a(e.g. as shown inFIG. 3B). The seed layer33amay include Ti, TiCu, another metal, an alloy, or other suitable materials. The second patterned conductive layer33has a thickness t. The first pad331has a width L.

The external connection pad37covers a top surface and a side wall of the first pad331of the second patterned conductive layer33. The external connection pad37covers (e.g. completely covers) the first pad331of the second patterned conductive layer33.

In one or more embodiments, at least one portion of the trace332of the second patterned conductive layer33adjacent to the first pad331is covered in the projective area of the external connection pad37(e.g. a projection of the external connection pad37in a direction towards the first dielectric layer10can overlap the at least one portion of the first pad331). In one or more embodiment, at least one portion of the second pad333adjacent to the first pad331is covered in the projective area of the external connection pad37(e.g. a projection of the external connection pad17in a direction towards the first dielectric layer10can overlap the at least one portion of the second pad333). Under this arrangement, a surface density of conductive components including the first pad331, the trace332and the second pad333of the second patterned conductive layer33can be increased. The surface area of the first dielectric layer10can be efficiently used. In some embodiments, an edge of the trace332is adjacent to or contacts an edge of the projective area of the external connection pad37(e.g. the protrusion edge375is substantially coplanar with the edge of the trace332).

The second dielectric layer12is disposed on the surface102of the first dielectric layer10. The second dielectric layer12covers the second patterned conductive layer33and at least part of a side wall373of the external connection pad37. The protrusion edge375of the external connection pad37is on the top surface of the second dielectric layer12. The bottom of the protrusion edge375of the external connection pad37is directly on the top surface of the second dielectric layer12. The second dielectric layer12has a thickness p.

FIG. 3Bis a cross-sectional view of the arrangement of the external connection pad37according to some embodiments of the present disclosure.

The external connection pad37has a top surface371, a bottom surface372, and the side wall373(e.g. extending between the top surface371and the surface102). The side wall373and the top surface of the second dielectric layer12define a joint A. In some embodiments, the top surface371of the external connection pad37may have a convex shape or a concave shape. The external connection pad37narrows, or tapers from the top surface371to the bottom surface372. In some embodiments, the external connection pad37includes a conductive body370and a seed layer374. The conductive body370may include Cu, Ag, Au, another metal, an alloy, or other suitable materials. The seed layer374covers the pad331. The seed layer374may include Ti, TiCu, another metal, an alloy, or other suitable materials. The external connection pad37has a protrusion edge375. The protrusion edge375includes a protrusion edge of the conductive body370and a protrusion edge of the seed layer374.

The pad331of the second patterned conductive layer33has a thickness t. The first pad331of the second patterned conductive layer33has a width L. In some embodiments, the thickness t of the second patterned conductive layer33is ranged from approximately 2 μm to approximately 3 μm. The width L of the first pad331is ranged from approximately 4 μm to approximately 15 μm. A width of the second pad333is ranged from approximately 2 μm to approximately 5 μm. The protrusion edge375has a width d. The external connection pad37has a bottom width B. The external connection pad37has a top width D. The external connection pad37has a top edge width D′. The top edge width D′ of the external connection pad37is approximately equal to the top width D of the external connection pad37plus two widths d. The bottom width B of the external connection pad37is approximately equal to the width L of the first pad331. In some embodiments, the thickness p of the second dielectric layer12is ranged from approximately 3 μm to approximately 15 μm. The pad331is spaced from the trace332by a distance s.

In some embodiments, an angle θ between the side wall373of the external connection pad37and an imaginary line extended from the bottom surface372of the external connection pad37is defined in accordance with the following equation:

θ=tan-1⁡(px)
where p is a thickness of the second dielectric layer12, t is a thickness of the second patterned conductive layer33, and x is a distance between an edge of the bottom surface372of the external connection pad37and a vertical imaginary line extended from the joint A. The parameter x is a horizontal distance between the edge of the bottom surface372of the external connection pad37and the vertical imaginary line extended from the joint A. The parameter x is a minimum distance between the edge of the bottom surface372of the external connection pad37and the vertical imaginary line extended from the joint A. In some embodiments, the distance x is the distance between the first pad331and the trace332. In some embodiments, the value of the parameter x may be approximately equal to the value of the parameter s. In some embodiments, the parameters of the thickness p, the thickness t and the distance x may be selected such that the angle θ and the parameters satisfy specifications for a semiconductor device package.

In some embodiments, the value of the parameter x plus the value of the parameter d may be approximately equal to or greater than the value of the parameter s. The side wall373of the external connection pad37does not contact the adjacent trace332or the adjacent pad333. The angle θ is determined by the following equation:

FIG. 3Cis an angle table of the angle θ for the substrate3corresponding to some embodiments of the present disclosure. The angle table shows the conditions under which the side wall373of the external connection pad73would not contact the trace332or the second pad333of the second patterned conductive layer33. In some embodiments, the range of the angle θ is about 45 degrees<θ≤about 71.6 degrees, about 2 μm≤t≤about 3 μm, and about 1 μm≤x≤about 2 μm.

FIG. 3Dis an angle table of the angle θ for the substrate3corresponding to some embodiments of the present disclosure. The angle table shows conditions under which at least one portion of the trace332of the second patterned conductive layer33is covered in the projective area of the external connection pad73or at least one portion of the second pad333of the second patterned conductive layer33is covered in the projective area of the external connection pad73. In some embodiments, the range of the angle θ is about 45 degrees<θ≤about 71.6 degrees, p=about 3 μm, about 2 μm≤t≤about 3 μm, and about 1 μm≤x≤about 2 μm. In some embodiments, the range of the angle θ is 45 degrees<θ≤about 56.3 degrees, p=about 3 μm, 2 μm≤t≤about 3 μm, and x=about 2 μm. In some embodiments, the range of the angle θ is about 63.5 degrees<θ≤about 71.6 degrees, p=about 3 μm, about 2 μm≤t≤about 3 μm, and x=about 1 μm.

FIG. 4Ais a cross-sectional view of a substrate4in accordance with some embodiments of the present disclosure. The substrate1includes a first dielectric layer10, a first patterned conductive layer11, a second dielectric layer12, a second patterned conductive layer13, a passivation layer14and an external connection pad47. The external connection pad47has a top surface471, a bottom surface472, and a side wall473. The external connection pad47includes a conductive body470and a seed layer474.

The depicted structure ofFIG. 4is similar to the structure depicted inFIG. 1, except that the side wall473of the external connection pad47defines one or more curved corners with the bottom surface472.

FIG. 4Bis a cross-sectional view of the arrangement of the external connection pad47according to some embodiments of the present disclosure. The definitions of the parameters are similar to those ofFIG. 1B. The parameter values implemented in the embodiments shown inFIG. 4Bmay be any suitable parameter values described herein, or may be adjusted to account for the curved corners.

FIG. 5is a cross-sectional view of a semiconductor device package5according to some embodiments of the present disclosure. The semiconductor device package5includes at least some components similar to those described above with respect toFIG. 1A, and a substrate1, a solder53, a conductive pillar55, a semiconductor device50, an underfill52, and a connection element51.

The connection element51is disposed adjacent to the surface101of the first dielectric layer10. The connection element51is disposed at the sunken portion of the first patterned conductive layer11. The connection element51is electrically connected to the first patterned conductive layer11. The connection element51has a first portion disposed in the passivation layer14and a second portion exposed from the passivation layer14.

The semiconductor device50is disposed on the substrate1. The underfill52is disposed between the substrate1and the semiconductor device50. The semiconductor device50is electrically connected to the external connection pad17of the substrate1through an interconnect element (e.g. through one of, or both of, the solder53and the conductive pillar55). The top surface171of the external connection pad17has a concave shape. The area of the top surface171of the external connection pad17is large enough to readily attach the semiconductor device50to the substrate1, and the resistance of the external connection pad17may be set to be within design specifications.

Since the top surface171of the external connection pad17has a concave shape, the top area of the top surface171of the external connection pad17is increased and the contact area of the top surface171of the external connection pad17configured to receive the solder53is increased.

FIG. 6is a cross-sectional view of a semiconductor device package6according to some embodiments of the present disclosure. The depicted structure ofFIG. 6is similar to the structure depicted inFIG. 5, except that the top surface171of the external connection pad17has a convex shape. Such a top surface can provide advantages similar to those described above with respect to the concave surface.

FIG. 7Ashows a type of a carrier for semiconductor package devices in accordance with some embodiments of the present disclosure.

As shown inFIG. 7A, a plurality of semiconductor devices50or dies are placed on a substantially square-shaped carrier54(e.g. in accordance with one or more embodiments described herein). In some embodiments, the carrier54may include organic materials (e.g., a molding compound, bismaleimide triazine (BT), a PI, a polybenzoxazole (PBO), a solder resist, an ABF, a PP or an epoxy-based material) and/or inorganic materials (e.g., silicon, a glass, a ceramic or quartz).

FIG. 7Bshows an another type of a carrier for semiconductor package devices in accordance with some embodiments of the present disclosure.

As shown inFIG. 7B, a plurality of semiconductor devices50or dies are placed on a substantially circle-shaped carrier56(e.g. in accordance with one or more embodiments described herein). In some embodiments, the carrier56may include organic materials (e.g., a molding compound, BT, a PI, a PBO, a solder resist, an ABF, a PP or an epoxy-based material) and/or inorganic materials (e.g., silicon, a glass, a ceramic or quartz).

FIG. 8AthroughFIG. 8Lillustrate some embodiments of a method of manufacturing the semiconductor device package1according to some embodiments of the present disclosure.

Referring toFIG. 8A, a method for manufacturing the semiconductor device package1includes providing a passivation layer14on a conductive layer11′, or forming the conductive layer11′ on the passivation layer14.

Referring toFIG. 8B, the conductive layer11′ is thinned by an etching operation. Then, the passivation layer14is patterned to form an opening to expose a portion of the conductive layer11′. The exposed portion of the conductive layer11′ is etched to form a recessed or sunken portion. The depth of the gap at the sunken portion may be set by controlling the etching operation.

Referring toFIG. 8C, a carrier61is bonded on the passivation layer14through an adhesion layer60, or is laminated to the passivation layer14. Then, a photoresist62is formed on the conductive layer11′ and then the conductive layer11′ is backside etched to form the first patterned conductive layer11. The photoresist62may be subsequently removed.

Referring toFIG. 8D, a first dielectric layer10having a bottom surface101and a top surface102opposite to the first surface is provided on the first patterned conductive layer11. In some alternative embodiments, the first dielectric layer10is provided, and the first dielectric layer10if formed on the first dielectric layer10. An opening is formed in the first dielectric layer10. A seed layer13ais formed on the surface102of the first dielectric layer10.

Referring toFIG. 8E, another photoresist62with openings is formed on the seed layer13a. A conductive layer is formed in the openings of the photoresist62by a plating operation to form a second patterned conductive layer13. In some embodiments, the second patterned conductive layer13may include the seed layer13a. The second patterned conductive layer13is formed adjacent to the top surface102of the first dielectric layer10and electrically connected to the first patterned conductive layer11. The second patterned conductive layer13comprises a pad131and a trace132adjacent to the pad131.

Referring toFIG. 8F, the photoresist62is removed and a portion of the seed layer13ais removed by an etching operation. Then, the second dielectric layer12is disposed on the top surface102of the first dielectric layer10. The second dielectric layer12is a development dielectric layer. The second dielectric layer12comprises a polymer, a sensitizer, and a solvent. In some embodiments, the sensitizer may comprise 1,2-Octanedione, 1-[4-(phenylthio)phenyl]-,2-(O-benzoyloxime), a photoacid generator, or triarylsulfonium hexafluoroantimonate. A weight percentage of the sensitizer (e.g. a percentage of the second dielectric layer12, by weight, that is constituted by the sensitizer) may be ranged from approximately 2.5% to approximately 0.1%. A weight percentage of the sensitizer may be about 0.2% or more, such as about 0.25% or more, 0.3% or more, 0.35% or more, or greater.

Referring toFIG. 8G, an opening is formed in the second dielectric layer12. A seed layer174is formed on the second dielectric layer12. A degree of inclination of a side wall of the opening of the second dielectric layer12can be controlled by selecting the weight percentage and/or concentration of the sensitizer in the second dielectric layer12. The degree of inclination of the side wall of the opening may directly define an angle θ of an external connection pad17(e.g. as shown inFIG. 1B). When the degree of inclination of the side wall of the opening increases, the angle θ of the external connection pad17decreases. Accordingly, when the weight percentage or concentration of the sensitizer increases, the angle θ of the external connection pad17decreases. An increase of the weight percentage of the sensitizer in the second dielectric layer12(development dielectric layer) would decrease a width of a bottom surface of the external connection pad17.

Referring toFIG. 8H, a conductive layer170is formed in the opening of the second dielectric layer12by a plating operation.

Referring toFIG. 8I, another photoresist62with openings is formed on the conductive layer170(e.g. to cover the conductive layer170).

Referring toFIG. 8J, etching operations are performed to remove a portion of the conductive layer170and a portion of the seed layer174so as to form the external connection pad17, thus forming a substrate1. According to the design of the substrate1, even if the opening of the second dielectric layer12shifts or is not properly aligned during an alignment operation, the external connection pad17would not contact an adjacent trace or pad (e.g. because a bottom of the external connection pad17is at a higher elevation than the adjacent trace or pad).

Referring toFIG. 8K, a semiconductor device50is attached to the external connection pad17through a solder53and a conductive pillar55. An underfill52is filled between the semiconductor device50and the second dielectric layer12.

According to the structure of the substrate1, the solder53is electrically connected to the external connection pad17. The risk of an undesirable solder bridge of the solder53that may occur during a reflow operation can be avoided. Additionally, since the surface density of the pad131and trace132of the second patterned conductive layer13is large, the whole thickness of the substrate1can be kept small.

Referring toFIG. 8L, the carrier61and the adhesion layer60are removed. The connection element51is disposed in the opening of the passivation layer14. Then, a singulation operation is performed.

The connection element51is disposed adjacent to the surface101of the first dielectric layer10. The connection element51is disposed on the first patterned conductive layer11. The connection element51has a first portion disposed in the opening of the passivation layer14and a second portion exposed from the passivation layer14. A width of the first portion of the connection element51is substantially equal to a width of the opening of the passivation layer14.

FIG. 9illustrates a cross-sectional view of a comparative substrate7. The substrate7includes a first dielectric layer10, a first patterned conductive layer11, a second dielectric layer12, a patterned conductive layer73, a solder53and a conductive pillar55. The patterned conductive layer73includes a first pad731and a second pad732. A width of the first pad131is greater than a width of the second pad732. The first pad has a large width for contacting the conductive pillar55. However, since the first pad may occupy a large area of the first dielectric layer10, a total number of I/O able to be implemented with the substrate7may be small.

The second dielectric layer12defines an opening. The opening may shift during an alignment operation. According to some design specifications, the second pad732should be completely covered by the second dielectric layer12, but may be exposed from the second dielectric layer12due to the shift. The solder53bleeds during a reflow operation and contacts the second pad732. Therefore, an undesirable solder bridge of the solder53occurs during the reflow operation.

FIG. 10illustrates a cross-sectional view of a comparative substrate8. The structure depicted inFIG. 10is similar to the structure depicted inFIG. 9, except that the second pad732is not exposed from the second dielectric layer12.

The opening of the second dielectric layer12may shift during an alignment operation. The degree of shift of the opening of the second dielectric layer12inFIG. 10is less than that shown inFIG. 9. However, the solder53still bleeds to the first dielectric layer10during a reflow operation. A structure of the solder53and conductive pillar55is not stable. The conductive pillar55may collapse when the substrate8encounters a press or a force during some operations for manufacturing a semiconductor device package, such as a bonding operation.

FIG. 11illustrates a cross-sectional view of a comparative semiconductor device package9. The semiconductor device package9includes a first dielectric layer10, a first patterned conductive layer11, a second dielectric layer12, a patterned conductive layer73, an underfill52, an interconnection element95and a semiconductor device50. The interconnection element95includes a conductive pillar951, a conductive pillar953, and a solder952. The underfill52is disposed between the second dielectric layer12and the semiconductor device50.

In order to increase a contact area between the conductive pillars951and953, the solder952can be disposed between the conductive pillars951and953. This kind of structure for the interconnection element95can help to avoid the solder bridge issue of the solder53depicted inFIG. 9and the collapse issue of the solder53and conductive pillar55depicted inFIG. 10. However, the structure of the interconnection element95increases the thickness of the semiconductor device package9.