Converter and method which remains biased for operation in the pulse frequency modulation mode and pulse width modulation mode

In accordance with an embodiment, a DC-DC converter is provided comprising a single regulation loop that drives a control circuit, wherein the control circuit selects between operation in a pulse width modulation operating mode and a pulse frequency modulation operating mode, the single regulation loop including a compensation loop, and wherein biasing of the compensation loop is maintained in response to selecting between the pulse width modulation and the pulse frequency modulation operating modes.

BACKGROUND

The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure.

Power converters are used in a variety of electronic products including automotive, aviation, telecommunications, and consumer electronics. Power converters such as Direct Current to Direct Current (“DC-DC”) switching converters have become widely used in portable electronic products such as laptop computers, personal digital assistants, pagers, cellular phones, etc. which are typically powered by batteries. DC-DC converters may include several regulation modes to maximize their efficiency over a load range. For example, it may be desirable to operate the DC-DC converter in a Pulse Frequency Modulation (PFM) operating mode for light load conditions and in a Pulse Width Modulation (PWM) operating mode for higher load conditions. Typically, these operating modes are optimized to provide the best efficiency in accordance with the best load line transient performance and load line regulation performance. A drawback with these systems is that regulation of the output voltage is degraded when the converter switches between the PFM and PWM operating modes.

Accordingly, it would be advantageous to have a circuit and a method for providing voltage regulation when switching between operating modes. It is desirable for the circuit and method to be cost and time efficient to implement.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or an anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.

It should be noted that a logic zero voltage level (VL) is also referred to as a logic low voltage or logic low voltage level and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Transistor-Transistor Logic (TTL) system a logic zero voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VH) is also referred to as a logic high voltage level, a logic high voltage, or a logic one voltage and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.

DETAILED DESCRIPTION

Generally the present invention provides a converter and a method for operating the converter in a plurality of operating modes wherein the converter remains biased to operate in the plurality of operating modes. In accordance with an embodiment, the converter includes an analog loop control circuit connected to an output stage through a control circuit that configures the converter circuit to operate in a pulse width modulation (PWM) operating mode or a pulse frequency modulation (PFM) operating mode.

In accordance with another embodiment, the converter comprises a single regulation loop that drives a control circuit that selects between operation in a pulse width modulation operating mode and pulse frequency modulation operating mode, wherein the control circuit maintains biasing conditions in response to operating in the pulse width modulation and the pulse frequency modulation operating modes.

In accordance with another embodiment, a method for operating the converter is provided. An error signal is compared with a reference signal to generate a comparison signal. In response to the comparison signal, the converter may be shifted between a pulse width modulation operating mode and a pulse frequency modulation operating mode, wherein the converter remains biased for operating in the pulse width modulation operating mode and the pulse frequency modulation operating mode because regulation of both operating modes is accomplished using a single compensation loop, i.e., single-loop regulation. Since the converter remains biased while in these operating modes, the converter is able to switch or shift between operating modes without degrading the performance of the converter in response to operating mode changes, e.g., when changing from a PWM operating mode to a PFM operating mode or from a PFM operating mode to a PWM operating mode.

FIG. 1is a circuit schematic of a DC-DC converter10in accordance with an embodiment of the present invention. What is shown inFIG. 1is DC-DC converter10comprising an analog loop control circuit12coupled to an output stage16through an operating mode control circuit14. Circuit12may be referred to as a regulation loop or an analog control loop circuit and operating mode control circuit14may be referred to as a PWM/PFM control circuit, a mode control circuit, or an operating mode control network. By way of example, analog loop control circuit12may include a reference generator20, comparators26,28,29,34, and36, an error amplifier38, a feedback network40, a PFM control network41, and may have inputs22and24and outputs31,33,35, and37. Error amplifier38and feedback network40serve as a compensation loop48. PFM control network41may be referred to as a tripping network, a PFM alarm network, or a fast PFM tripping network. More particularly, comparators34and36each have an inverting input and a noninverting input, wherein their inverting inputs are connected together and to an output of reference generator20. The inverting inputs of comparators34and36are coupled for receiving a reference signal VEASSfrom reference generator20. Error amplifier38has an inverting input, a noninverting input, and an output and is configured in a negative feedback configuration. In accordance with an embodiment, a feedback network40is connected between the inverting input and the output of error amplifier38, where error amplifier and feedback network40are referred to as compensation loop48. The noninverting input of error amplifier38may be connected to or, alternatively, serve as input24and may be coupled for receiving a reference voltage VREF1. By way of example, feedback network40is comprised of an impedance structure42having a terminal connected to the inverting input of error amplifier38and a terminal coupled for receiving a feedback voltage VFBat node22. Feedback network40further includes an impedance structure44having a terminal connected to the inverting input of error amplifier38and a terminal connected to the output of error amplifier38, which output is connected to the noninverting input of comparator34. It should be noted that impedance structures42and44in cooperation with error amplifier38form the single compensation loop of the DC/DC converter48.

PFM control network41may include a terminal connected to the noninverting input of comparator34and a terminal connected to the noninverting input of comparator36. Thus, PFM control network41may be connected between the noninverting inputs of comparators34and36. By way of example, PFM control network41is comprised of a resistor43and a current source45, wherein resistor43has a terminal connected to the noninverting input of comparator34and a terminal connected to the noninverting input of comparator36and current source45has a terminal commonly connected to the noninverting input of comparator36and to the terminal of resistor43that is connected to the noninverting input of comparator36to form a node47. PFM control network41generates a signal VEA1at node47that is a linear function of error amplifier output signal VEA. Output signal VEA1is transmitted to the noninverting input of comparator36. Signal VEAmay be referred to as an error signal and signal VEA1may be referred to as an adjusted error signal. The configuration of PFM control network41is not a limitation of the present invention. For example, PFM control network41may be comprised of a linear function generator that generates an output signal VFLEAthat is a linear function of an input signal VEA. Output signal VFLEAis transmitted to the noninverting input of comparator36.

The output of comparator34may be connected to or, alternatively, serves as output31and the output of comparator36may be connected to or, alternatively, serves as output33of analog loop control circuit12. Thus, error signal VEA, adjusted error signal VEA1, and comparison signals V31and V33are generated using a single compensation or regulation loop.

Comparator26has an inverting input connected to the output of error amplifier38, a noninverting input coupled for receiving a periodic signal VPERand an output that is coupled to or, alternatively, serves as output35of analog loop control circuit12. Comparator28has an inverting input coupled for receiving a reference signal VTON, a noninverting input connected to the noninverting input of comparator26and coupled for receiving periodic signal VPER, and an output that is coupled to or, alternatively, serves as output37of analog loop control circuit12.

PWM/PFM control circuit14has inputs51,53,55,57, and59and outputs54and56. In accordance with an embodiment, inputs51,53,55, and57are connected to outputs31,33,35, and37, respectively, of analog loop control circuit12. An embodiment of a PWM/PFM control circuit14is further described with reference toFIG. 2.

Output stage16includes transistors50and52, each having a control electrode, e.g., a gate and a pair of current carrying electrodes, e.g., a source and a drain. By way of example, transistor50is a p-channel field effect transistor and transistor52is an n-channel field effect transistor. The gate of transistor50is connected to output54through a driver60and the source of transistor50is coupled for receiving an input voltage VIN. The gate of transistor52is connected to output56through a driver62, the drain of transistor52is connected to the drain of transistor50, and the source of transistor52is coupled for receiving a source of operating potential VSS. By way of example, operating potential VSSis a ground potential. The commonly connected current carrying electrodes, i.e., drains, of transistors50and52form a node64. Drivers60and62may be referred to as drive circuits or driver circuits.

A zero crossing detector29is connected between node64and input59of PWM/PFM control circuit14. By way of example, zero crossing detector29comprises a comparator having an inverting input coupled for receiving, for example, source of operating potential VSS, a noninverting input connected to node64, and an output connected to input59.

An inductor68has a terminal connected to node64and a terminal connected to a load70at a node71and may conduct a current I68. By way of example, load70is a resistor74having a terminal connected to inductor68and a terminal coupled for receiving source of operating potential VSS. A capacitor72is coupled between node71and source of operating potential VSS. Inductor68and capacitor72form an external filter for DC/DC converter10.

Node71is connected to input22through resistors76and78. More particularly, resistor76has a terminal connected to node71and a terminal connected to input22and resistor78has a terminal connected to input22and a terminal coupled for receiving source of operating potential VSS. It should be noted that resistors76and78are optional circuit elements that may be used in external feedback configurations. However, other feedback networks may be employed or, alternatively, resistors76and78may be absent and node71can be connected directly to input22.

Output signal VOUTappears at node71.

FIG. 2is a circuit schematic of PWM/PFM control circuit14in accordance with an embodiment of the present invention. What is shown inFIG. 2is a counter102, a driver120, a clock138, flip-flops140and146, logic gates152,154, and156, and an inverter160. By way of example, counter102is comprised of flip-flops112,114, and116and has inputs104,106, and108and an output110. Flip-flop112has a data input commonly connected to the clocking inputs of flip-flops114and116, which commonly connected inputs are coupled to or, alternatively, serve as an input104of counter102. A data input of flip-flop114is connected to or, alternatively, serves as an input106of counter102. Input106is coupled for receiving a source of operating potential such as, for example, VDD. Flip-flop112has a clocking input that is coupled to or, alternatively, serves as input108of counter102and a data output connected to the active low reset inputs of flip-flops114and116. Flip-flop116has a data input connected to a data output of flip-flop114and a data output that is coupled to or, alternatively, serves as output110of counter102.

Logic gate152is an OR gate having an input connected to an output of clock138and an input connected to input104of counter102to form a commonly connected input which is connected to or serves as input51of PWM/PFM control circuit14.

Logic gate154is an OR gate having an input connected to output110of counter102and an input connected to input108of counter102to form a commonly connected input which is connected to input53of PWM/PFM control circuit14.

Flip-flop140has a clocking input connected to the output of OR gate152, a reset input, and a data output. Logic gate156is an OR gate having an input connected to or, alternatively, serving as input55of PWM/PFM control circuit14and an input connected to or, alternatively, serving as input57of PWM/PFM control circuit14. It should be noted that logic gates152,154, and156are not limited to being OR gates. They may be, for example, NAND gates or the like or other logic configurations.

Flip-flop146has a clocking input connected to the output of OR gate154, a reset input commonly connected to input108of counter102, the input of inverter160, and to input59of PWM/PFM control circuit14, and a data output connected to an enable input of clock138.

Driver120has an input122connected to the data output of flip-flop140and an input124connected to input59of PWM/PFM control circuit14through inverter160. By way of example, driver120includes inverters126,128,130,132,134, and136, and logic gates131and133, logic gate131is a two-input AND gate, and logic gate133is a three-input NAND gate. The number of inputs for logic gates131and133are not limitations of the present invention. AND gate131has an input connected to an input of inverter126and to an output of flip-flop140to form a commonly connected input that is connected to or, alternatively, serves as input122of driver120. AND gate131also has an input connected to the output of NAND gate133through inverters134and136and an output connected to the input of inverter128. NAND gate133has an input connected to the output of inverter126, an input connected to the output of inverter160, an input connected to the output of inverter128through inverters130and132, and an output connected to the input of inverter134. It should be noted that the output of inverter128is connected to the input of inverter130and is connected to or, alternatively, serves as output54of PWM/PFM control circuit14and the output of inverter134is connected to the input of inverter136and is connected to or, alternatively, serves as output56of PWM/PFM control circuit14. Output signal VOUTHappears at output54and output signal VOUTLappears at output56.

Converter10operates in a plurality of modes depending on the load condition. For example, in response to a light current load converter10operates in a PFM mode and in response to a higher current load it operates in a PWM mode. Converter10includes a single loop for PWM and PFM modes of operation, thus the regulation loop is biased to operate in the PWM operating mode in response to changing from the PFM to PWM operating mode. More particularly, reference generator20generates a reference signal VEASSwhich is transmitted to the inverting inputs of comparators34and36, which references comparators34and36to voltage VEASS. Reference signal VEASSmay be an image of a steady state value or a DC value of output voltage VEAfrom error amplifier38. Output voltage VEAis set by the regulation loop to adjust the switch duty cycle of transistors50and52to provide a desired DC output voltage VOUTat node71shown inFIG. 1. The absolute value of reference signal VEASSmay be a function of output voltage VOUT, input voltage VIN, and the ramp compensation voltage. It should be noted that output voltage VEAfrom error amplifier38is input into the inverting input of comparator34and is thus compared with reference signal VEASSto generate a comparison signal V31at output31of analog loop control circuit12.

FIG. 3is a schematic of a circuit suitable for use as impedance structure44ofFIGS. 1 and 2. Impedance structure44may be comprised of a capacitor162connected in parallel with a series connected resistor164and capacitor166.

FIG. 4is a schematic of a circuit suitable for use as impedance structure42ofFIG. 1. Impedance structure42may be comprised of a resistor168connected in parallel with a series connected resistor170and capacitor174and a resistor172having a terminal connected to the commonly connected terminals of capacitor174and resistor168. It should be noted that the configurations of impedance structures44and42shown inFIGS. 3 and 4, respectively, are not limitations of the present invention. For example, resistor172may be omitted or there may be fewer or a greater number of circuit elements.

FIG. 5is a timing diagram180illustrating current I68flowing through inductor68, output voltage VEAfrom error amplifier38, reference signal VEASS, and comparator output voltage V31. PWM/PFM control circuit14controls regulation in the PFM mode, where a PFM pulse is started in response to output voltage VEAbecoming greater than reference signal VEASS. At time t0, inductor current I68increases from a zero current level, PMOS transistor50is on and NMOS transistor52is off, and voltages V54and V56are at a logic low voltage level VL. Reference voltage VEASSis at a substantially constant voltage level and voltage VEAis increasing but substantially equal to voltage VEASS. In response to voltage VEAbecoming greater than reference voltage VEASSat a time t0+, comparator34generates a logic high voltage at output31, i.e., voltage V31transitions to a logic high voltage level which appears at input51of PWM/PFM control circuit14. It should be noted that the nomenclature t0is used to indicate a time close to but greater than time t0. Voltage VEAis still greater than reference voltage VEASSbetween times t1and t2, but decreases during this time interval. At time t2, error amplifier output voltage VEAis at substantially the same voltage level as reference voltage VEASSand continues decreasing and voltage V31at the output of comparator34transitions from a logic high voltage level to a logic low voltage level.

At time t3inductor current I68reaches a positive peak current level I68Pand begins to decrease in response to transistor50turning off and transistor52turning on. In response to transistor50being off and transistor52being on, voltages V54and V56transition to a logic high voltage level VH. At time t4, inductor current I68is clamped at a current level of zero in response to zero crossing detection circuitry and current clamping circuitry coupled to node64. Thus, zero crossing detector29turns off transistor52to prevent inductor current I68from going negative. In response to transistor52being off, voltage V56transitions to logic low voltage level VLand voltage V54remains at logic high voltage level VH.

At time t5, inductor current I68increases from a zero current level, reference voltage VEASSis at a substantially constant voltage level, and voltage VEAis increasing but substantially equal to voltage VEASS. In response to voltage VEAbecoming greater than reference voltage VEASSat a time t5+, comparator34generates a logic high voltage at output31, i.e., voltage V31transitions to a logic high voltage level which appears at input50of PWM/PFM control circuit14. In response to comparison signal V31, control signal V54generated by PWM/PFM control circuit14transitions from a logic high voltage level VHto logic low voltage level VL. Similar to the nomenclature t0+, the nomenclature t5+is used to indicate a time close to but greater than time t5. Voltage VEAis decreasing at time t6. At time t7inductor current I68reaches a positive peak current level I68Pand begins to decrease in response to transistor50turning off and transistor52turning on. In response to transistor50being off and transistor52being on, voltages V54and V56transition to logic high voltage level VH. It should be noted that a positive edge of voltage V31starts a PFM burst, and the negative edge can occur either during or after the TONperiod. Thus, the PFM burst is started in response to comparison signal V31which is generated by comparing error signal VEAwith reference signal VEASSwhere error signal VEAis greater than reference signal VEASS. The negative edge occurs in response to voltage VEAgoing lower than voltage VEASS.

At time t8, inductor current I68is clamped at a current level of zero in response to zero current detection circuitry and current clamping circuitry coupled to node64. Zero crossing detector29turns off transistor52to prevent inductor current I68from going negative. In response to transistor52turning off, voltage V56transitions to logic low voltage level VLwhile voltage V54remains at logic high voltage level VH.

At time t9, reference voltage VEASSis at a substantially constant voltage level, voltage VEAis increasing but substantially equal to voltage VEASS, and current I68increases from a zero current level. In response to voltage VEAbecoming greater than reference voltage VEASSat a time t9+, comparator34generates a logic high voltage at output31, i.e., voltage V31transitions to a logic high voltage level which appears at input51of PWM/PFM control circuit14. In response to comparison signal V31, control signal V54generated by PWM/PFM control circuit14transitions from logic high voltage level VHto logic low voltage level VL. Similar to the nomenclature t0+and t5+, the nomenclature t9+is used to indicate a time close to but greater than time t9.

At time t10, inductor current I68reaches a positive peak current level I68Pand begins to decrease in response to transistor50turning off and transistor52turning on. Accordingly, output signals V54and V56transition to logic high voltage level VH. It should be noted that at time t10, error amplifier output voltage VEAis still greater than reference voltage VEASS.

At time t11, inductor current I68reaches a zero current level, which serves as an inflection point, and begins increasing in response to transistor50turning on and transistor52turning off. Accordingly, output signals V54and V56transition to logic low voltage level VL. It should be noted that error amplifier output voltage VEAis still greater than reference voltage VEASS.

At times t12, t14, and t16, inductor current I68reaches a positive peak current level I68P, which serves as an inflection point, and begins to decrease in response to transistor50turning off and transistor52turning on. Accordingly, output signals V54and V56transition to logic high voltage level VH. It should be noted that at times t12, t14, and t16error amplifier output voltage VEAis still greater than reference voltage VEASS.

At times t13and t15, inductor current I68reaches a zero current level, which serves as an inflection point, and begins increasing in response to transistor50turning on and transistor52turning off. Accordingly, output signals V54and V56transition to logic low voltage level VL. Error amplifier output voltage VEAis still greater than reference voltage VEASS. It should be noted that the PFM bursts have become consecutive and that the PFM circuit generates its maximum output current. After counting several consecutive PFM bursts, PWM/PFM circuit14enters the PWM operating mode.

It should be noted that converter10includes two PFM comparators34and36that are referenced to a reference voltage VEASS, which is the steady state or DC output voltage of the error amplifier operating in a PWM operating mode. Voltages VEAand VEASSare input to comparator34which control PFM regulation. Converter10generates a PFM pulse each time voltage VEAgoes higher than voltage VEASS. Thus, comparator34ensures DC voltage regulation in the PFM operating mode by starting a PFM burst each time voltage VEAgoes higher than voltage VEASS. In the PWM operating mode, the regulation loop sets the value of voltage VEASSto set the switching frequency duty cycle that provides the desired output voltage VOUT. Thus, single regulation loop12of converter10includes a compensation loop and drives a control circuit14, wherein control circuit14selects between operation in a pulse width modulation operating mode and a pulse frequency modulation operating mode, and wherein biasing of the compensation loop is maintained in response to selecting between the pulse width modulation and the pulse frequency modulation operating modes.

In addition, regulation loop12controls switching from the PFM operating mode to the PWM operating mode in response to converter10being unable to deliver a desired current load. Comparator36monitors an adjusted error voltage that may be lower than or proportional to the error voltage output by error amplifier38and ensures that converter10changes from the PFM operating mode to the PWM operating mode in response to conditions in which the load change is too fast and the consecutive high output levels of comparator34are too long to be detected. Thus, comparator36causes converter10to switch into the PWM operating mode before output voltage VOUTdrops too much.

FIG. 6is a timing diagram182illustrating current I68flowing through inductor68, output voltage VEAfrom error amplifier38, and reference signal VEASSwith respect to time.FIG. 6illustrates converter10operating in the PFM operating mode before mode change time tcand operating in the PWM operating mode after mode change time tc. It should be noted that in both the PFM and PWM operating modes output voltage VEAoscillates about reference voltage VEASSand that inductor current I68flows for longer periods of time during the PWM operating mode compared to the PFM operating mode. It should be further noted that voltage VEASSis predetermined as the average VEAvalue during PWM regulation. Thus, the compensation loop made up of impedance structures42and44and error amplifier38is biased at a similar level in PFM and PWM operating modes. This improves the PFM to PWM mode transitions as the compensation loop is already biased around its PWM steady state value. The current ripple in the PWM operating mode is lower than the current ripple in the PFM operating mode.

FIG. 7is a timing diagram184illustrating output voltage VOUT, output voltage VEAfrom error amplifier38, reference signal VEASS, and control voltage V33output by comparator36with respect to time. From time t0to time t1, DC-DC converter10operates in a PFM mode. In this mode, output voltage VOUTand reference voltage VEASSare at substantially constant levels. Before time t1, the rate of the load change increases causing output voltage VOUTto decrease and voltages VEAand VEA1to increase. At time t1voltage VEAis substantially equal to voltage VEASSand increasing and at time t2voltage VEA1is substantially equal to voltage VEASSand increasing. Voltage VEA1increases to a level greater than reference voltage VEASSin response to load changes that are sufficiently fast that consecutive high comparison signal levels V31are too long to detect. In response to voltage VEA1being greater than reference voltage VEASS, comparator36outputs a logic high voltage comparison signal and PWM/PFM control circuit14configures DC/DC converter10to enter the PWM operating mode before the output voltage VOUTdecreases to a level that degrades the performance of DC-DC converter10.

FIG. 8is a circuit schematic of a DC-DC converter190in accordance with another embodiment of the present invention. DC-DC converter190includes an analog loop control circuit192coupled to an output stage16through an operating mode control circuit14. Operating mode control circuit14and output stage16have been described with reference toFIG. 1. Analog loop control circuit192is similar to analog loop control circuit12in that it includes error amplifier38, feedback network40, reference generator20, and comparators34,26, and28which have been described with reference toFIGS. 1-4. Error amplifier38and feedback network40form compensation loop48. Analog loop control circuit192differs from control circuit12in that comparator36and PFM control network41are absent from analog loop control circuit192.

FIG. 9is a circuit schematic of a DC-DC converter200in accordance with another embodiment of the present invention. What is shown inFIG. 9is DC-DC converter200comprising an analog loop control circuit202coupled to an output stage205through an operating mode control circuit204. Analog loop control circuit202may be referred to as a regulation loop and operating mode control circuit204may be referred to as a PWM/PFM control circuit, a mode control circuit, or an operating mode control network. By way of example, analog loop control circuit202may include a reference voltage generator216for generating a reference voltage VREF1, a reference voltage generator218for generating a reference voltage VEASS, comparator34, an error amplifier38, a feedback network40, and may have an input22and an output31at which output signal V31appears. Error amplifier38and feedback network40form compensation loop48. Comparator34has an inverting input and a noninverting input, wherein the inverting input is coupled for receiving a reference voltage signal VEASSfrom reference generator218. Error amplifier38has an inverting input, a noninverting input, and an output and is configured in a negative feedback configuration. In accordance with an embodiment, a feedback network40is connected between the inverting input and the output of error amplifier38. The noninverting input of error amplifier38may be coupled for receiving a reference voltage VREF1from reference generator216. Error amplifier38, feedback network40, resistors76and78have been described with reference toFIG. 1.

PWM/PFM control circuit204has an input206and an output208. In accordance with an embodiment, input206is connected to output31of analog control loop202.

Output stage205includes a transistor212connected to a diode214. Transistor212has a control electrode, e.g., a gate, and a pair of current carrying electrodes, e.g., a source and a drain. By way of example, transistor212is a p-channel field effect transistor. The source of transistor50is coupled for receiving an input voltage VIN, the gate is connected to output208, and the drain is connected to the cathode of diode214at node210. Transistor50is not limited to being a p-channel field effect transistor. The anode of diode214coupled for receiving a source of operating potential VSS. By way of example, operating potential VSSis a ground potential.

Inductor68has a terminal connected to node210and a terminal connected to node71, which is connected to feedback network40in a feedback configuration. Output stage70and capacitor72have been described with reference toFIG. 1.

By now it should be appreciated that a converter suitable for operating in PWM and PFM operating modes and a method for operating the converter have been provided. In accordance with embodiments, the converter is a multi-mode converter having a single regulation loop for operation in the PWM and PFM modes, wherein the single regulation loop maintains biasing of the converter for operation in the different modes without degrading its operation, i.e., the converter is biased so that it is suitable for PWM operation during the PWM and PFM operating modes. Converters such as, for example, converters10and190, are capable of operating in PWM and PFM operating modes and are referred to as multi-mode converters.

Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.