Multilayer chipset structure

A multilayer chipset structure is provided. The chips can be arranged in a stacking structure with multilayer circuit board. Each circuit board is formed with wiring opening and chipset opening. The chipset opening can be arranged with at least one chipset, such as a controller. The different openings cause connecting wires can pass therethrough so as to connect different chips or circuit elements on different layer. By this modularized structure, the multilayer package structure can be formed with a complicated structure in one package so as to reduce the packaging cost effectively. The connecting wires pass through the openings so as to reduce the whole path lengths needed. No complicated wiring is needed. All the conducting wires are at an upper side of the chips. In packaging, it only needs to package the upper side.

FIELD OF THE INVENTION

The present invention is related to chip packaging, and in particular to a multilayer chipset structure.

BACKGROUND OF THE INVENTION

In prior art semiconductor multilayer packaging structures, welding pads are welded on upper sides of circuit boards and chips. Conduction wires are used to connect the circuit boards and chips. Then packaging structures are added. In the prior art, to suit for the welding pads on different circuits, the conduction wires are wound and curved and are arranged on different positions of the circuit boards. As a result, it makes the works become difficult and times for assembling are increased dramatically. Furthermore, in packing, epoxy must be added to different surface and thus the thickness of the whole structure increases so that the assembly time and cost increase and heat dissipation effect reduces.

Therefore there is an eager demand for a novel structure which can decrease the complicated winding structure and thus reduce the assembly time and cost.

SUMMARY OF THE INVENTION

To improve above mentioned defects in the prior art, the present invention provides a multilayer chipset structure, wherein the chips can be arranged in a stacking structure with multilayer circuit board. Each circuit board is formed with wiring opening and chipset opening. The chipset opening can be arranged with at least one chipset, such as a controller. The different openings cause connecting wires can pass therethrough so as to connect different chips or circuit elements on different layer. By this modularized structure, the multilayer package structure can be formed with a complicated structure in one package so as to reduce the packaging cost effectively. Furthermore, in the present invention, the connecting wires pass through the openings so as to reduce the whole path lengths needed. In the present invention, all the conducting wires are at an upper side of the chips. In packaging, it only needs to package the upper side (such as sealing with epoxy). Packaging at other sides may be neglected.

To achieve above object, the present invention provides a multilayer chipset structure comprising: a chip circuit layer (100) containing: a first chip (10) having a plurality of welding pads (101) on a surface thereof for connecting external conducting wires; a first circuit board (20) being positioned above the first chip (10); the first circuit board (20) including at least one wiring opening (21) and at least one chipset opening (22); after the first circuit board (20) being combined with the first chip (10), the welding pads (101) on the first chip (10) exposing out from the wiring opening21; a first chipset (25) being placed in the chipset opening (22); the first chipset being arranged with a plurality of welding pads (251); after the first circuit board (20) being combined with the first chip (10), the first chipset (25) exposing out from the chipset opening (22); and wherein the first circuit board (20) is formed with a plurality of welding pads (211) near the wiring opening (21) of the first circuit board (20); first conducting wires (215) are connected between the welding pads (101) of the first chip (10) and the welding pads (211) of the first circuit board (20) so as to have the function of power and signal connections; and the first circuit board (20) is formed with a plurality of welding pads (221) near the chipset opening (22); second conducting wires (225) serve to connect the welding pads (221) of the first circuit board (20) and the welding pads (251) of the first chipset (25) so as to have the functions of power and signal connection.

The chip circuit layer (100) further comprises: at least one second circuit board (30) being installed above the first circuit board (20); the second circuit board (30) including at least one wiring opening (31) and at least one chipset opening (32); the wiring opening (31) of the second circuit board (30) serving to expose the welding pads (201) of the first circuit board (20) after the second circuit board (30) combines with the first circuit board (20); a second chipset (35) being arranged on the chipset opening (32) of the second circuit board (30); the second chipset (35) being arranged with a plurality of welding pads (351); the second chipset (35) exposing out from the chip set opening (32) of the second circuit board (30) after the second circuit board (30) is combined with the first circuit board (20); wherein a plurality of welding pads (311) are arranged on the second circuit board (30) near the wiring opening (31) of the second circuit board (30); third conducting wires (315) serving to connect the welding pads (311) on the second circuit board (30) with the welding pads (301) of the first circuit board (20) for signal and electrical connections; and a plurality of welding pads (321) are arranged on the second circuit board (30) near the chipset opening (32) of the second circuit board (30); fourth conducting wires (325) serving to connect the welding pads (321) on the second circuit board with the welding pads (351) of the second chipset (35) for signal and electrical connections.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIGS. 1 to 3, the first embodiment about the multiple chip packaging structure according to the present invention is illustrated. The structure comprises the following elements.

A chip circuit layer100contains the following elements.

A first chip10has a plurality of welding pads101on a surface thereof for connecting external conducting wires. For example, the first chip10may be a NAND flash chip.

A first circuit board20is positioned above the first chip10. The first circuit board20includes at least one wiring opening21and at least one chipset opening22. After the first circuit board20is combined with the first chip10, the welding pads101on the first chip10exposes out from the wiring opening21.

The first chipset25is placed in the chipset opening22. The first chipset25is, for example, a controller. The first chipset25is arranged with a plurality of welding pads251.

After the first circuit board20is combined with the first chip10, the first chipset25exposes out from the chipset opening22. As illustrated inFIG. 2, the chipset opening22is aside the wiring opening21. However, this arrangement is only one example for description of the invention. The arrangement of the chipset opening22and the wiring opening21may be another forms. All these are within the scope of the present invention.

The first circuit board20is formed with a plurality of welding pads211near the wiring opening21. Conducting wires215are connected between the welding pads101of the first chip10and the welding pads211of the first circuit board20so as to have the function of power and signal connections.

The first circuit board20is formed with a plurality of welding pads221near the chipset opening22. Conducting wires225serve to connect the welding pads221of the chipset opening22and the welding pads251of the first chipset25so as to have the functions of power and signal connection.

A set of outward conduction wires300have one ends connected to the welding pads211of the first circuit board20and another end connected to external devices. The connection of the outward conduction wires300is only one example and thus not used to confine the scope of the present invention. Preferably, the conduction wires300are gold wires with a preferred extension and wear enduring property.

A packaging layer200is above the chip circuit layer100. The packaging layer200encloses the chip circuit layer100for protection the chip circuit layer100.

With reference toFIGS. 4 to 7, another embodiment of the present invention is illustrated. The same elements as those shown in the first embodiment are not described herein.

The chip circuit layer100further comprises:

At least one second circuit board30is installed above the first circuit board20. The second circuit board30includes at least one wiring opening31and at least one chipset opening32. The wiring opening31of the second circuit board30serves to expose the welding pads201of the first circuit board20after the second circuit board30combines with the first circuit board20.

A second chipset35is arranged on the chipset opening32of the second circuit board30. The second chipset35is arranged with a plurality of welding pads351.

The second chipset35exposes out from the chip set opening32of the second circuit board30after the second circuit board30is combined with the first circuit board20. As illustrated inFIG. 2, the chip set opening32of the second circuit board30is at the same side as that locating the wiring opening31of the second circuit board30. However, this is used as an example for description of the invention. The wiring opening31and the chip set opening32of the second circuit board30may be arranged by another ways.

A plurality of welding pads311are arranged on the second circuit board30near the wiring opening31of the second circuit board30. Conducting wires315serve to connect the welding pads311with the welding pads301of the first circuit board20for signal and electrical connections.

A plurality of welding pads321are arranged on the second circuit board30near the chipset opening32of the second circuit board30. Conducting wires325serve to connect the welding pads321with the welding pads351of the second chipset35for signal and electrical connections.

At least one outwards extending conducting wire300having one end connected to welding pads321of the second circuit board30and another end extending out of the second circuit board30for connecting with external devices. In this example, the outwards extending conducting wires300is connected with the second circuit board300by using the welding pads311,321. However, the connection of the outwards extending conducting wire300and the second circuit board30are not confined to those shown in the drawings, other arrangements are still effective. Preferably, the outwards extending conducting wire300is a golden wire with preferred extension property and endurance for wearing.

Preferably, in the present invention, the conducting wires215,225,315and325are copper wires which has the advantage of low cost.

As illustrated inFIG. 7, the at least one second circuit board30includes a plurality of second circuit boards. Each of the second circuit board30is overlapped with one another so as to form with a multi-layer structure. Each second circuit board has an opening and respective welding pads on the upper surface thereof. Conductive wires are used to connect welding pads on the second circuit board30on an upper side and welding pads of the second circuit board30on a lower side through the opening of the second circuit board30on an upper side. Another chipset35is placed in the opening of the second circuit board30.

Advantages of the present invention are that the chips can be arranged in a stacking structure with multilayer circuit board. Each circuit board is formed with wiring opening and chipset opening. The chipset opening can be arranged with at least one chipset, such as a controller. The different openings cause connecting wires can pass therethrough so as to connect different chips or circuit elements on different layer. By this modularized structure, the multilayer package structure can be formed with a complicated structure in one package so as to reduce the packaging cost effectively.

Furthermore, in the present invention, the connecting wires pass through the openings so as to reduce the whole path lengths needed. No complicated wiring is needed. In the present invention, all the conducting wires are at an upper side of the chips. In packaging, it only needs to package the upper side (such as sealing with epoxy). Packaging at other sides may be neglected. Therefore the whole structure is simple and thin. The packing cost is low and work is easy. As a result, many circuit elements expose out so that heat dissipation is good.