Method of manufacturing printed circuit board

A method of manufacturing a printed circuit board includes forming an intermediate layer on a first conductive layer disposed on a first insulating layer, forming a second conductive layer and a second insulating layer on the intermediate layer, separating the first insulating layer from at least one portion of the first conductive layer, and etching the first conductive layer and the intermediate layer. After the etching, a surface of the second conductive layer protrudes further than a surface of the second insulating layer. The intermediate layer before the etching includes a portion overlapping the second conductive layer in a vertical direction and another portion not overlapping the second conductive layer in the vertical direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of priority to Korean Patent Application No. 10-2021-0185824 filed on Dec. 23, 2021 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by references in its entirety.

TECHNICAL FIELD

The present disclosure relates to a method of manufacturing a printed circuit board.

BACKGROUND

In accordance with high performance and/or hyper-integration density of electronic devices or electric devices in which a printed circuit board is used, the size of each component of a printed circuit board has also gradually decreased. As a printed circuit board or each component of a printed circuit board is highly integrated and/or miniaturized, it may be difficult to secure reliability of a printed circuit board.

SUMMARY

An aspect of the present disclosure is to provide a method of manufacturing a printed circuit board.

According to an aspect of the present disclosure, a method of manufacturing a printed circuit board includes forming an intermediate layer on a first conductive layer disposed on a first insulating layer; forming a second conductive layer and a second insulating layer on the intermediate layer; separating the first insulating layer from at least one portion of the first conductive layer; and etching the first conductive layer and the intermediate layer, wherein, after the etching, a surface of the second conductive layer protrudes further than a surface of the second insulating layer, and wherein the intermediate layer before the etching includes a portion overlapping the second conductive layer in a vertical direction and another portion not overlapping the second conductive layer in the vertical direction.

According to another aspect of the present disclosure, a method of manufacturing a printed circuit board includes forming an intermediate layer on a first conductive layer disposed on a first insulating layer; forming second conductive patterns, including a metal different from a metal included in the intermediate layer, on the intermediate layer, wherein the intermediate layer extends between adjacent patterns of the second conductive patterns; forming a second insulating layer on the intermediate layer to cover the second conductive patterns; and removing the first insulating layer, the first conductive layer, and the intermediate layer, so as to form the printed circuit board including the second conductive patterns at least partially embedded in the second insulating layer.

DETAILED DESCRIPTION

These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, structures, shapes, and sizes described as examples in embodiments in the present disclosure may be implemented in another example embodiment without departing from the spirit and scope of the present disclosure. Further, modifications of positions or arrangements of elements in example embodiments may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, accordingly, not to be taken in a limiting sense, and the scope of the present invention are defined only by appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled.

FIGS.1A to1Lare diagrams illustrating a process of manufacturing a printed circuit board in accordance with a method of manufacturing a printed circuit board according to an example embodiment.

Referring toFIGS.1A and1B, the method of manufacturing a printed circuit board in an example embodiment may include forming an intermediate layer131on a first conductive layer132on a first insulating layer111.

For example, the combination structure of the first insulating layer111and the first conductive layer132may be a copper clad laminate (CCL). For example, the adhesive layer113may allow the first insulating layer111and the first conductive layer132to adhere to each other, and the structure of the combination of the first insulating layer111, the adhesive layer113, and the first conductive layer132may be manufactured by a detachable copper foil (DCF) manufacturing method. For example, the adhesive layer113may be a foam tape, and the first conductive layer132may include copper (Cu).

Referring toFIGS.1C to1G, the method of manufacturing a printed circuit board in an example embodiment may include forming a second conductive layer125and a second insulating layer112on the intermediate layer131to cover the second conductive layer125. For example, the forming the intermediate layer131may be performed according to a nickel (Ni) plating process. For example, the second conductive layer125may include copper (Cu) and may be formed according to a copper (Cu) plating process.

Referring toFIG.1H, the method of manufacturing a printed circuit board in an example embodiment may include separating the first insulating layer111from at least one portion of the first conductive layer132. That is, a printed circuit board manufactured according to the method of manufacturing a printed circuit board in an example embodiment may have a coreless structure. For example, the size (e.g., a width and thickness) of the second conductive layer125may be relatively small, and the total number of stacks of the printed circuit board may be relatively small.

For example, the adhesive layer113adhered between the first insulating layer111and the first conductive layer132may be separated from at least one of the first insulating layer111and the first conductive layer132.

Referring toFIGS.1I to1K, the method of manufacturing a printed circuit board in an example embodiment may include etching the first conductive layer132and the intermediate layer131. For example, the etching may include etching one of a metal material and an insulating material using an etching liquid or an etching gas reacting to the one of the metal material and the insulating material and leaving the other.

Since the intermediate layer131is disposed between the first conductive layer132and the second conductive layer125, the intermediate layer131may prevent the second conductive layer125from being etched while the first conductive layer132is etched.

Referring toFIGS.1K and1L, after the etching, the surface (e.g., the upper surface) of the second conductive layer125facing the intermediate layer131may protrude further than the surface (e.g., the upper surface) of the second insulating layer112facing the intermediate layer

The second conductive layer125may be electrically connected to a component (e.g., an integrated circuit, or a passive component) disposed on the second conductive layer125. For example, the second conductive layer125may include a plurality of portions spaced apart from each other, and may be a pad or land of a printed circuit board.

Since the second conductive layer125protrudes upwardly, the second conductive layer125may be electrically connected to the component without solder including a material having a low melting point (e.g., a Pb-based material, an Sn-based material). Also, the size (e.g., a width and thickness) of the second conductive layer125may be reduced efficiently, and the number of a plurality of portions of the second conductive layer125per unit area may increase efficiently, such that the second conductive layer125may be advantageous for high integration and/or miniaturization of the component.

Referring toFIGS.1B to1I, the intermediate layer131before the etching may include a portion overlapping the second conductive layer125in a vertical direction and the other portion not overlapping the second conductive layer125in the vertical direction.

When the intermediate layer131does not include a portion not overlapping the second conductive layer125in the vertical direction, the difference between a design and an actual design of a portion of the intermediate layer131may cause a point at which the intermediate layer131may not prevent the second conductive layer125from being etched, and may act as a limitation in reliability of the intermediate layer131. For example, when a point of the second conductive layer125is etched while the first conductive layer132is etched, the electrical connection relationship of a point of the second conductive layer125with respect to the component may change. Alternatively, the physical structure of one point of the second conductive layer125may become unstable, and crevices or voids may be formed due to instability of the positional relationship between the second conductive layer125and the second insulating layer112. The importance of overcoming the limitation in reliability limit may be higher when the second conductive layer125has a structure protruding upwardly, and when the size (e.g., a width and thickness) of the second conductive layer125is relatively small or the number of divided portions in unit area increases.

When the intermediate layer131includes a portion overlapping the second conductive layer125in the vertical direction and another portion not overlapping the second conductive layer125in the vertical direction, the intermediate layer131may be implemented as a single panel, and a point at which the intermediate layer131may not prevent the second conductive layer125from being etched may be prevented in advance. Accordingly, reliability of the structure in which the second conductive layer125protrudes upwardly may increase, and high integration and/or miniaturization of the second conductive layer125may be implemented efficiently.

For example, referring toFIGS.1A and1B, the forming the intermediate layer131may include forming at least one portion of the intermediate layer131in a state in which a protective pattern is not formed on the first conductive layer132. Accordingly, the intermediate layer131may be manufactured as a single panel.

For example, referring toFIGS.1C and1D, the protective pattern115may be disposed on a portion of the intermediate layer131, and the second conductive layer125may be formed on another portion of the intermediate layer131where the protective pattern115is not formed. For example, the protective pattern115may be a photosensitive film, and may be removed after the second conductive layer125is formed.

For example, referring toFIGS.1E and1F, a portion of the second insulating layer112may be formed after the second conductive layer125is formed, and the interlayer via123penetrating a portion of the insulating layer112may be formed. For example, the conductive pattern121may be formed between a portion and another portion of the second insulating layer112, and may be connected to the interlayer via123. The interlayer via123may also be connected to the second conductive layer125. For example, the interlayer via123may be formed as a metal material is filled in a hole formed by a laser and/or a drill.

By repeating the processes described with reference toFIGS.1E and1F, a structure shown inFIG.1G(not including the surface layer141) may be formed.

For example, referring toFIG.1G, a surface layer141may be formed on the second insulating layer112, and a portion of the surface layer141may be penetrated. For example, the penetrated portion of the surface layer141may be an electrical connection path between the second conductive layer125and an additional substrate (or an additional component). For example, the surface layer141may be a solder resist.

For example, referring toFIG.1H, the first insulating layer111may be removed from at least one portion of the first conductive layer132.

For example, referring toFIG.1I, the first conductive layer132may be removed from the intermediate layer131.

For example, referring toFIG.1J, the intermediate layer131may be removed from the second insulating layer112by an etching process.

For example, referring toFIG.1K, the etching may further include etching a portion of the second insulating layer112. Accordingly, the second conductive layer125may further protrude upwardly from a level of the upper surface of the second insulating layer112. For example, the portion of the second insulating layer112including the surface (e.g., an upper surface) facing the intermediate layer131may include an Ajinomoto build-up film (ABF). Accordingly, the second insulating layer112may stably secure a positional relationship with respect to the second conductive layer125having a smaller size in accordance with high integration and/or miniaturization. For example, the upper surface of the second insulating layer112which is partially etched may go through a cleaning process.

For example, referring toFIG.1L, the method of manufacturing a printed circuit board in an example embodiment may further include performing a surface treatment on the surface (e.g., the upper surface) of the second conductive layer125facing the intermediate layer131after the etching. Accordingly, a surface treatment layer142may be formed, and the upper protruding structure of the second conductive layer125may be less affected from external elements (e.g., air) of the printed circuit board (e.g., corrosion due to chemical reaction, or the like).

For example, the surface treatment layer142may be at least one portion of an electroless nickel electroless palladium immersion gold (ENEPIG) structure. When reliability of the second conductive layer125is secured, the possibility that a variable in the process of forming the surface treatment layer142may act as a variable in the formation of the second conductive layer125may also be reduced. The surface treatment layer142is not limited to the ENEPIG structure, and may be implemented as an organic solder passivation (OSP) layer in example embodiments.

FIGS.2A to2Mare diagrams illustrating a process of manufacturing a printed circuit board in which a difference in thicknesses between one portion and the other portion of an intermediate layer is implemented in accordance with a method of manufacturing a printed circuit board according to an example embodiment.

The descriptions not described with respect toFIGS.2A to2Mmay be the same as the descriptions of the aforementioned example embodiment described with respect toFIGS.1A to11L.

Referring toFIGS.2A to2D, the method of manufacturing a printed circuit board in an example embodiment may include forming the intermediate layer131on the first conductive layer132on the first insulating layer

Referring toFIGS.2E to2I, the method of manufacturing a printed circuit board in an example embodiment may include forming a second conductive layer125and a second insulating layer112on the intermediate layer131.

Referring toFIG.2J, the method of manufacturing a printed circuit board in an example embodiment may include separating the first insulating layer111from at least one portion of the first conductive layer132.

Referring toFIGS.2K to2L, the method of manufacturing a printed circuit board in an example embodiment may include etching the first conductive layer132and the intermediate layer131.

Referring toFIGS.2L and2M, after the etching, the surface (e.g., the upper surface) of the second conductive layer125facing the intermediate layer131may protrude further than the surface (e.g., the upper surface) of the second insulating layer112facing the intermediate layer131.

Referring toFIGS.2B to2K, the intermediate layer131before the etching may include a portion overlapping the second conductive layer125in the vertical direction and the other portion not overlapping the second conductive layer125in the vertical direction.

Referring toFIGS.2C to2K, a thickness of a portion of the intermediate layer131overlapping the second conductive layer125in the vertical direction before the etching may be less than a thickness of the other portion of the intermediate layer131not overlapping the conductive layer125in the vertical direction.

Accordingly, without the etching a portion of the second insulating layer112inFIGS.1J and1K, the second conductive layer125may further protrude upwardly from the level of the upper surface of the second insulating layer112. Accordingly, the positional relationship between the second conductive layer125and the second insulating layer112may become stable, reliability of the second conductive layer125may increase, and efficiency of high integration and miniaturization of the second conductive layer125may increase.

For example, referring toFIGS.2A and2B, the intermediate layer131may be formed on the first conductive layer132on the first insulating layer111.

For example, referring toFIGS.2B to2D, the forming the intermediate layer may include forming a protective pattern115′ on at least one portion of the intermediate layer131in a state in which a portion of the intermediate layer131is formed on the first conductive layer132, and forming the other portion of the intermediate layer131on the region in which the protective pattern115′ is not formed. In this case, regions where the protective pattern115′ is formed may have a thinner layer of the intermediate layer131, as compared to regions where the protective pattern115′ is not formed, because the additional formation of the intermediate layer131after forming the protective pattern115′ shown inFIG.2Cis performed to the regions where the protective pattern115′ is not formed. Then, the protective pattern115′ may be removed. Accordingly, a difference in thicknesses between a portion of the intermediate layer131and another portion may be formed, as shown inFIG.2D.

For example, referring toFIGS.2D and2E, the forming the second conductive layer125and the second insulating layer112may include forming a protective pattern115on another portion of the intermediate layer131which is relative thicker and forming the second conductive layer125in a region in which the second protective pattern115is not formed. Thereafter, the protection pattern115may be removed.

The first and second insulating layers111and112are not limited to copper clad laminates (CCL) and ABF, and may be prepreg, FR-4, bismaleimide triazine (BT), photoimagable dielectric (PID) resin, and may be at least one of a material selected from a group consisting of thermosetting resin such as epoxy resin, thermoplastic resin such as polyimide, polytetrafluoroethylene (PTFE), glass-based resin and ceramic-based resin (e.g., low temperature co-fired ceramic (LTCC)). A material included in the first and second conductive layers132and125are not limited to copper (Cu), and may be at least one of silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), or titanium (Ti), gold (Au), and platinum (Pt). For example, the first and second conductive layers132and125may be implemented using a semi-additive process (SAP), a modified semi-additive process (MSAP), or a subtractive method.

FIGS.3A and3Bare diagrams illustrating a process of inspecting a second conductive layer while the printed circuit board inFIGS.1D and2Fis manufactured, viewed from the side.FIG.3Cis a plan diagram illustrating an intermediate process of manufacturing the printed circuit board inFIGS.1D and2F.

Referring toFIGS.3A to3C, the forming the second conductive layer125and the second insulating layer of the method of manufacturing a printed circuit board in an example embodiment may further include inspecting whether the second conductive layer125is formed in each of a plurality of positions on the intermediate layer131while the second conductive layer125is formed and the second insulating layer is not formed.

For example, the inspecting may be implemented by an automated optical inspection (AOI), and the type of light (e.g., visible light, infrared light, ultraviolet light, X-ray) used in the AOI may be appropriately determined to discriminate a difference between the metal material (e.g., nickel) of the intermediate layer131and the metal material (e.g., copper) of the second conductive layer125or to identify a difference in roughness depending on the difference of the metal materials.

When the intermediate layer131does not include a portion not overlapping the second conductive layer125in the vertical direction, the intermediate layer131may not be exposed upwardly, such that the AOI may not be able to be performed. As for the method of manufacturing a printed circuit board in an example embodiment, the intermediate layer131may include both a portion overlapping the second conductive layer125in the vertical direction and a portion not overlapping the second conductive layer125, such that an environment in which whether the second conductive layer125is defective may be detected relatively early may be provided, and process efficiency of the printed circuit board may improve.

FIG.4is an image indicating a stable dispositional relationship between a second conductive layer and a second insulating layer of a printed circuit board manufactured accordance with a method of manufacturing a printed circuit board according to an example embodiment.

Referring toFIG.4, the second conductive layer125having reliability according to the method of manufacturing a printed circuit board in an example embodiment may also have positional stability with respect to the second insulating layer112, and interactive force F1between the second conductive layer125and the second insulating layer112may also be balanced in the entire adjacent area of the second conductive layer125and the second insulating layer112. Accordingly, the possibility of crevices or voids between the second conductive layer125and the second insulating layer112may be reduced.

FIG.5Ais a diagram illustrating a structure of an electronic device in which a printed circuit board may be disposed according to an example embodiment.FIG.5Bis a diagram illustrating a system of an electronic device in which a printed circuit board may be disposed according to an example embodiment.

Referring toFIGS.5A and5B, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal wirings1090.

Depending on a type of the electronic device1000, the electronic device1000may include other components that may or may not be physically or electrically connected to the mainboard1010. These other components may include, for example, a camera module1050, an antenna1060, a display device1070, and a battery1080. However, an example embodiment thereof is not limited thereto, and these other components may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (for example, a hard disk drive), a compact disk (CD) drive), a digital versatile disk (DVD) drive, or the like. Also to the above examples, other components used for various purposes depending on a type of electronic device1000, or the like, may be included.

The electronic device may be implemented by a smartphone1100. A motherboard1110may be accommodated in a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. Also the other components which may or may not be electrically connected to the motherboard1110, such as the camera module1130and/or the speaker1140, may be accommodated therein. A portion of the components1120may be the chip related components, such as a component package1121, for example, but an example embodiment thereof is not limited thereto. The component package1121may be configured as a printed circuit board on which electronic components including active components and/or passive components are surface-mounted. Alternatively, the component package1121may be configured as a printed circuit board in which active and/or passive components are embedded. The electronic device is not necessarily limited to the smart phone1100, and may be another electronic device as described above. A printed circuit board having a smaller size, disposed on the motherboard1110, or the motherboard1110may be the printed circuit board according to an example embodiment of the present disclosure, but an example embodiment thereof is not limited thereto.

According to the aforementioned example embodiments, a printed circuit board manufactured according to the method of manufacturing a printed circuit board may increase reliability of a connection structure for components, or may be advantageous for high integration and/or miniaturization of the connection structure.