Reduced-length bond pads for broadband power amplifiers

In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.

FIELD OF INVENTION

The present invention relates generally to semiconductor amplifiers, and in particular to a reduced-length bond pad for connecting a drain finger manifold of a transistor to circuits on a substrate, the length of the bond pad selected to control a parasitic capacitance.

BACKGROUND

Modern wireless communication networks operate by transmitting voice and data content modulated onto Radio Frequency (RF) signals, generally between fixed access points (known as base stations, eNB, gNB, etc.) and a large number of mobile terminals (User Equipment or UE, tablets, laptops, etc.). Signal transmissions in both directions require RF power amplifiers. Efficiency (output power divided by DC power) is an important consideration in both cases. Efficient power amplifiers are desired at access points because inefficient amplifiers simply turn much of the power consumed into heat, raising operating costs and requiring physical designs to release the heat. The power amplifier in a mobile terminal is a major consumer of battery power, and high efficiency is desired to extend the useful device lifetime per charge.

Amplifiers operate most efficiently at or near compression—the point at which an amplifier is always ON, or strongly conducting. An amplifier operating below its compression point operates in a linear range—the output signal is an amplified version of the input signal. Amplifiers that operate partially or totally in compression can transmit frequency/phase modulated signals, or On-Off Keying modulated signals (e.g., Morse code), at high power with high efficiency. In these applications, linearity is not required—that is, the amplifier may distort the signal amplitude without affecting the information modulated onto the signal. However, communication signals that encode information, even in part, by modulating the amplitude of a carrier signal require power amplifiers to operate with high linearity, to preserve the AM information.

Many of the signal modulation schemes standardized for use in modern wireless communication networks, such as for example, the various levels of Quadrature Amplitude Modulation (16-QAM, 64-QAM, 256-QAM), require a linear amplifier to avoid loss of amplitude-modulated information that would occur if the amplifier ran in compression. A characteristic of many such signals is that the average signal power is relatively low, but intermittent peaks in the signal have high power, compared to the average. This characteristic is quantified as the Peak to Average Power Ratio (PAPR). A single power amplifier transmitting a high-PAPR signal exhibits low efficiency, as it must be sized for signal peaks, which occur infrequently, and on average it runs at very low power. That is, the power amplifier must be designed with a large “headroom” that, on average, is not used. Since the operating point of the amplifier is far below its compression point, efficiency is poor. This means much of the power it consumes (from a battery in the case of a mobile terminal) is wasted as heat.

William Doherty solved this problem in 1936, designing a power amplifier having improved efficiency while transmitting high-PAPR AM radio signals. An RF Doherty amplifier10, represented in block diagram form inFIG. 1, comprises a first transistor18aused for most signal amplification, often referred to as a “main” or “carrier” amplifier stage, and a second transistor18bused to amplify signal peaks, often referred to as an “auxiliary” or “peak” amplifier stage. The more general terms “first” and “second” transistor are used herein. A class-AB biased amplifier is often used for the first amplifier stage, which can be biased to amplify the average signal within a linear range, but close to compression (i.e., with low headroom). Signal peaks are amplified by, e.g., a class-C biased amplifier as the second amplifier stage, which is inactive most of the time, and only needs to be linear over a small portion of the input signal conduction angle.

A feature of the Doherty amplifier is the output connection of the first18aand second18btransistors, which is made through an impedance inverter22, often implemented using a quarter-wavelength transmission line, and often having a 90-degree phase shift. At low input signal power levels, the second transistor18bis inactive, and is effectively an open circuit. The system impedance (e.g., 50Ω) is reduced at the output of the second transistor18bdue to the output matching network24. This impedance is inverted to a much higher impedance by the impedance inverter22, presenting a high output impedance to the first transistor18a, improving its efficiency. As the second transistor18bbegins to amplify signal peaks, its increasing output current (summed with the output current of the first transistor18a) increases the voltage across the load impedance, which the impedance inverter22presents to the first transistor18aas a decreasing impedance. The lower impedance allows the first transistor18aoutput power to increase as the input signal power increases. This is known as load modulation, and it results in the Doherty amplifier10exhibiting high efficiency across the full range of input signal power.

Stated differently, load modulation occurs because the output voltage of the Doherty amplifier10is determined by the summation of the first18asecond18btransistor output currents, multiplied by the load impedance. Accordingly, the output impedance of the first transistor18ais varied by the load current delivered by the second transistor18b.

Note that, although the impedance inverter22often implements a 90-degree phase shift, this is not necessarily a requirement to obtain the load modulation of a Doherty amplifier. For example, a phase lag other than 90 degrees may be introduced in, e.g., the second transistor18bpath, and the impedance inverter22introduces a corresponding phase shift, such that the overall phase difference between the two transistor18a,18bpaths is at or near 90 degrees.

Referring toFIG. 1, a power divider circuit12divides an RF input signal between the first18aand second18btransistors in response to its instantaneous power level. A phase shifter14delays the phase of the second transistor18binput by matching the delay which the output impedance inverter22applies to the output of the first transistor18a, which is often 90 degrees. In some embodiments, the power divider12and phase shifter14may be combined in a quadrature power divider, which both splits the input signal and applies a 90 degree phase shift to the second transistor18binput. Input matching circuits16a,16bperform impedance matching, e.g., matching a standard 50Ω system impedance to the low input impedances of the first18aand second18btransistors. Similarly, output impedance matching circuits20a,20bmatch the low output impedance of transistors18a,18bto a standard system impedance, such as 50Ω.

As described above, the outputs of the first18aand second18btransistors in a Doherty configuration10are connected by an impedance inverter22having a 90 degree phase delay. The impedance inverter22is often implemented using a quarter-wavelength transmission line. The output of the Doherty amplifier10is taken at a so-called summing node, typically on the second transistor18bside of the impedance inverter22. An impedance transformer24transforms the load impedance Zloadseen by the Doherty amplifier circuit10to the standard 50Ω system impedance.

In many applications, the first and second transistors18a,18bmay be formed together on a semiconductor die26, as depicted inFIG. 2(a)—or each may be formed on a separate semiconductor die27,28, as depicted inFIG. 2(b)—which die or dice26,27,28are then bonded to a substrate30. The connection between the transistors18a,18boutputs, i.e., via an impedance inverter22, as well as any output matching circuits20a,20band impedance transformer24(not shown), is formed on the substrate30, which may for example comprise a Multi-Chip Module (MCM), or a Printed Circuit Board (PCB) including other RF circuitry.

To accommodate the relatively high current output by a power amplifier transistor18a,18b, the drain node typically comprises a plurality of drain “fingers,”32or parallel contacts to the transistor drain structure. These fingers32are connected via a manifold34, which is a metallization structure connecting all of the parallel drain fingers32for a given transistor18a,18b. Bond pads36are formed over the entire length of the manifolds34, providing a landing area for wire bonds38connecting the transistor18a,18bdrain terminals to the impedance inverter22on the substrate30. In the prior art, the bond pads36on the die26(FIG. 2(a)) or dice27,28(FIG. 2(b)) extend the entire length of the corresponding manifold34. This is to equalize the electrical length of signals output by each drain finger32. That is, if bond pad36covered only a part of the manifold34, an output signal from a distant drain finger32, not adjacent to the bond pad36, would have the additional electrical path length of part of the manifold34to travel down, before connecting to the bond pad36. This additional path length may alter the phase of that signal, as compared to one output by a drain finger32connecting to the manifold34where it is adjacent the bond pad36. Additionally, extending the bond pads36along the entire length of the manifolds34provides the greatest area for connection of wire bonds38to the substrate30.

However, conventional bond pads36have a large area which collects charge, and hence are a significant source of parasitic capacitance—for example, in the range of 0.4-2 pF for compact FET amplifiers—which limits the broadband performance of a Doherty amplifier10.

The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

SUMMARY

The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key/critical elements of embodiments of the invention or to delineate the scope of the invention. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

According to one or more embodiments described and claimed herein, the bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the, e.g., quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.

One embodiment relates to an amplifier. The amplifier includes a substrate and at least a first semiconductor die mounted on the substrate. At least a first transistor is formed on the first semiconductor die. The first transistor includes a first plurality of drain fingers; a first manifold electrically connecting the first plurality of drain fingers; and a first bond pad electrically connected to the first manifold. The first bond pad extends a length less than the length of the first manifold. The amplifier further included at least one bond wire electrically connecting the first bond pad to a circuit on the substrate.

Another embodiment relates to a method of manufacturing an amplifier. A substrate is provided. At least a first semiconductor die is mounted on the substrate. The first semiconductor die has at least a first transistor formed thereon. The first transistor includes a first plurality of drain fingers; a first manifold electrically connecting the first plurality of drain fingers; and a first bond pad electrically connected to the first manifold. The first bond pad extends a length less than the length of the first manifold. The first bond pad is electrically connected to a circuit on the substrate via at least one bond wire.

DETAILED DESCRIPTION

For simplicity and illustrative purposes, the present invention is described by referring mainly to an exemplary embodiment thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be readily apparent to one of ordinary skill in the art that the present invention may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention.

FIG. 3is an equivalent circuit schematic of key elements of the Doherty amplifier circuit ofFIG. 1. The first18aand second18bamplifiers are modeled as current sources, and the impedance inverter22, which may be implemented as a quarter-wave transmission line, is modeled as a pi-network, using lumped capacitances C1and C2, and lumped inductance L. As used herein, a “lumped” component represents spatially distributed electrical and physical circuit effects as one (or two, when associated with separate amplifiers18a,18b) electrical components, such as a resistor, capacitor, inductor, or the like. Such lumping of circuit effects greatly simplifies simulation, and is reasonably accurate over at least some range of operating conditions (power, frequency, etc.). At least some of the lumped inductance L and capacitances C1and C2represent parasitic effects. For example, the bond wires38contribute to the inductance L. The lumped capacitances C1and C2comprise primarily the source to drain capacitances CDSof the transistor devices18a,18b, but also include parasitic capacitance contributed by the large areas of the bonding pads36. This parasitic capacitance limits the broadband performance of the Doherty amplifier10.

According to embodiments of the present invention, the sizes of bond pads connecting to the drain finger manifolds of the first and second transistors are varied, at least in part to control the parasitic capacitance contributed by the bond pads. In this manner, designers can control the resulting capacitances, and utilize them in the design of the quarter-wavelength impedance inverter to optimize the Doherty amplifier's wideband performance.

FIGS. 4(a) and 4(b)depict reduced-length bond pads40, according to embodiments of the present invention.FIG. 4(a)depicts the case of two (or more) transistors18a,18bformed on a single semiconductor die26, which is mounted on a substrate30.FIG. 4(b)depicts the case of each transistor18a,18bbeing formed on a separate semiconductor die27,28, both of which are mounted on the substrate30. In both cases, the transistor18a,18boutputs are connected to an impedance inverter22formed on the substrate30, via a plurality of bond wires38. The bond wires38connect, on the die26, or dice27,28, to reduced-length bond pads40. That is, the bond pads40extend along their respective output manifolds34less than the full length of the manifolds34. The specific length of the bond pads40may be varied for each specific implementation, to control the parasitic capacitances they generate and contribute to the quarter-wave transmission line of the impedance inverter22. The lower limit of the bond pad40length is determined by the desired capacitance, as well as by ensuring enough area to bond a sufficient number of bond wires38to carry the output current.FIGS. 4(a) and 4(b)additionally show a bond wire38connecting the bond pad40of the transistor18ato a bonding pad42electrically connected to another circuit formed on the substrate30.

Prior art concerns about the phase misalignment of output signals from different drain fingers32are largely moot with state of the art circuit feature sizes, and at GHz frequencies. For example, a bond pad40according to embodiments of the present invention is on the order of 1 mm; at 2 GHz, the wavelength is 150 mm. Hence, changes in the electrical length due to the bond pad40do not have appreciable effect on the signal phases.

FIGS. 4(a) and 4(b)depict the bond pads40aligned with the outer edges of the corresponding manifolds34, as may be appropriate to accommodate a long impedance inverter circuit22. However, the size and position of the bond pads40inFIGS. 4(a) and 4(b)are not limiting. For example,FIGS. 5(a)-(d)depict other representative sizes and placements of bond pads40, at least one of which extends less than the full length of the corresponding manifold34.

FIG. 5(a)depicts a bond pad40on the first (upper) transistor that extends the full length of the corresponding manifold34—only the bond pad40on the second (lower) transistor is less than the length of the corresponding manifold34. Such an arrangement may be appropriate where only a slight reduction in parasitic capacitance is required, and/or a large bond pad40area is required to support a given number of wire bonds38to the first transistor.

InFIG. 5(b), both bond pads40are shorter than their respective manifolds34. In this embodiment, the bond pads40are both positioned toward the center, minimizing the length of the impedance inverter22. Additionally, the bond pad40on the second (lower) transistor is considerably shorter than the corresponding bond pad40depicted inFIG. 5(a)—reflecting, in this embodiment, a greater need to reduce the parasitic capacitance presented to the impedance inverter22.

InFIG. 5(c), both bond pads40are aligned with the tops of the respective manifolds34, and the bond pad40of the second transistor extends more nearly the full length of the corresponding manifold34.

InFIG. 5(d), both bond pads40are positioned at the center of the respective manifolds34. This minimizes the maximum electrical length (and hence any potential phase shift) of transistor output signals on the furthest drain fingers from the bond pad40.

In general, according to embodiments of the present invention, at least one bond pad40may assume any length that is less than the respective manifold34, and may be placed at any position along the length of the manifold. The length of the bond pad40is determined to achieve a required or desired capacitance, such as to optimize the broadband performance of the amplifier10.

FIG. 6depicts a graph of the simulated frequency responses for comparable Doherty amplifiers having conventional bond pads36extending the full length of respective manifolds34(dashed curve), and bond pads40according to embodiments of the present invention, wherein the length of each bond pad40is adjusted to be less than the length of the corresponding manifold, to optimize its parasitic capacitance contribution (solid curve). The curves exhibit a similar 3 dB point on the lower end, where m1=−3.005 dB at 1.750 GHz. At the higher frequencies, however, the conventional bond pad36lengths yield m3=−2.947 dB at 2.180 GHz, while the inventive shortened bond pads40, the lengths of which were optimized based on their capacitance, yield point m2=−2.971 dB at 2.240 GHz. Optimizing the bond pad40length thus improved the 3 dB bandwidth from 430 MHz to 490 MHz—an increase of ˜14%.

FIG. 7depicts the steps in a method100of manufacturing an amplifier. A substrate is provided (block102). At least a first semiconductor die is mounted on the substrate (block104). The first semiconductor die has at least a first transistor formed thereon. The first transistor comprises a first plurality of drain fingers; a first manifold electrically connecting the first plurality of drain fingers; and a first bond pad electrically connected to the first manifold. The first bond pad extends a length less than the length of the first manifold. The first bond pad is electrically connected to a circuit on the substrate via at least one bond wire (block106).

Embodiments of the present invention may be advantageously employed in any amplifier application where one or more transistor outputs are wirebonded to a substrate in a package, and where control of parasitic capacitance is advantageous. Embodiments are particularly well suited to Doherty amplifier configurations in such packaging, as the parasitic capacitance is incorporated into the, e.g., quarter-wave transmission line of an impedance inverter, and directly affects the amplifier operational characteristics, such as its bandwidth. As such, embodiments of the present invention are particularly well suited for wireless communication applications, such as massive MIMO (mMIMO) multi-chip module (MCM) power amplifiers and macro driver power amplifiers.

Embodiments of the present invention present significant advantages over the prior art. By engineering the length of a bond pad, at a length less than the full extent of a corresponding drain finger manifold, to achieve a required or desired capacitance, the operation of the impedance inverter is optimized, improving the wideband performance of a Doherty amplifier. At high frequency and small feature size, the phase mismatch in output signals from different drain fingers, having different electrical lengths from the drain finger to a bond wire, is negligible.

The term “directly electrically connected” or “electrically connected” or simply “connected” describes a permanent low-ohmic connection between electrically connected elements, for example a wire connection between the concerned elements. Although such a connection may have parasitic effects, such as the parasitic inductance of a bond wire, no component or element is interposed between the connected elements. By contrast, the term “electrically coupled” or simply “coupled” means that one or more intervening element(s) or components, configured to influence the electrical signal in some tangible way, may be (but is not necessarily) provided between the electrically coupled elements. These intervening elements may include active elements, such as transistors or switches, as well as passive elements, such as inductors, capacitors, diodes, resistors, etc.