Liquid crystal display with three-level scanning signal driving

An exemplary thin film transistor liquid crystal display (TFT-LCD) (100) includes an LCD panel having a number n (where n is a natural number) of gate lines G1-Gn that are parallel to each other, a data driving circuit (120), and a gate driving circuit (110). The gate driving circuit sequentially providing 3-level scanning signals to scan the gate lines G1-Gn. Each 3-level scanning signal sequentially includes a gate-on voltage, a feed-through compensation voltage, and a gate-off voltage wherein the gate-on voltage starts to be provided to a (Gi+1)th (1≦i≦n−1) of the gate lines G1-Gn at the time when the feed-through compensation voltage starts to be provided to a (Gi)th of the gate lines G1-Gn.

FIELD OF THE INVENTION

The present invention relates to a thin film transistor liquid crystal display (TFT-LCD), and a method for driving a TFT-LCD.

GENERAL BACKGROUND

A TFT-LCD has the advantages of portability, low power consumption, and low radiation, and has been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. Furthermore, the TFT-LCD is considered by many to have the potential to completely replace CRT (cathode ray tube) monitors and televisions.

FIG. 6is an abbreviated circuit diagram of a typical TFT-LCD. The TFT-LCD10includes an LCD panel (not shown), a data driving circuit2, and a gate driving circuit1. The LCD panel includes a thin film transistor (TFT) substrate (not shown), a color filter (CF) substrate (not shown) arranged in a position facing the TFT substrate, and a liquid crystal layer (not shown) sandwiched between the TFT substrate and the CF substrate.

The TFT substrate includes a number n (where n is a natural number) of gate lines (G1-Gn) that are parallel to each other and that each extend along a first direction, and a number m (where m is also a natural number) of data lines (D1-Dm) that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The TFT substrate also includes a plurality of thin film transistors (TFTs)3that function as switching elements. The TFT substrate further includes a plurality of pixel electrodes6formed on a surface thereof facing the CF substrate. Each TFT3is provided in the vicinity of a respective point of intersection of the gate lines (G1-Gn) and the data lines (D1-Dm).

The CF substrate includes a plurality of common electrodes7opposite to the pixel electrodes6. In particular, the common electrodes7are formed on a surface of the CF substrate facing the TFT substrate, and are made from a transparent material such as ITO (Indium-Tin Oxide) or the like.

Each TFT3includes a gate electrode31, a source electrode32, and a drain electrode33. An exemplary one of the TFTs3is labeled in detail inFIG. 6. In this TFT3, the gate electrode31, the source electrode32, and the drain electrode33are connected to a gate line Gn-1, a data line Dm-1, and one pixel electrode6respectively. The pixel electrode6, the common electrode7and the liquid crystal material sandwiched between the pixel electrode6and one common electrode7are represented as a liquid crystal capacitor (Clc)8. A storage capacitor (Cs)4is formed between a next gate line Gn and the drain electrode33of the TFT3.

FIG. 7shows abbreviated voltage waves of a plurality of scanning signals generated by the gate driving circuit1. V5represents a gate-on voltage that is a high voltage generated by the gate driving circuit1. V6represents a gate-off voltage that is a low voltage generated by the gate driving circuit1. The gate driving circuit1sequentially provides a gate-on voltage and a gate-off voltage as a scanning signal to one gate line Gn each time. In a frame time (shown as a double-headed arrow), the gate driving circuit1sequentially scans the gate lines from G1to Gn with the scanning signals.

When the gate-on voltage V5is provided to the gate electrode31of the TFT3via the gate line Gn-1, the TFT3connected to the gate line Gn-1is turned on. At the same time, a gradation voltage Vdgenerated by the data driving circuit2is provided to the pixel electrode6via the data line Dm-1and the activated TFT3in series. The potentials of all the common electrodes7are set at a uniform potential Vcom. Thus, an electric field is generated due to the voltage difference between the pixel electrode6and the common electrode7. The electric field is used to control the amount of light transmission of the corresponding pixel unit.

When the gate-off voltage V6is provided to the gate electrode31of the TFT3via the gate line Gn-1, the TFT3is turned off. The gradation voltage that is applied to the liquid crystal capacitor8when the TFT3is turned on is maintained after the TFT3is turned off. The gate driving circuit1providing gate-on and gate-off voltages to scan the gate lines (G1-Gn) is a so-called 2-level driving method.

However, due to the storage capacitor4between the drain electrode33of the TFT3connected to the gate line Gn-1and the next gate line Gn adjacent to the gate line Gn-1, the gradation voltage Vdapplied to the pixel electrode6is liable to be distorted when a voltage of the next gate line Gn changes from the gate-on voltage V5to the gate-off voltage V6. This kind of distorted voltage is known as a feed-through voltage. The feed-through voltage is liable to decrease the potential of the pixel electrode6. Thus the so-called flicker phenomena may appear on a display screen of the LCD panel of the TFT-LCD10.

What is needed, therefore, is a TFT-LCD and a method for driving the TFT-LCD which can overcome the above-described deficiencies.

SUMMARY

In one preferred embodiment, a TFT-LCD includes an LCD panel having a number n (where n is a natural number) of gate lines G1-Gn that are parallel to each other, a data driving circuit, and a gate driving circuit. The gate driving circuit sequentially providing 3-level scanning signals to scan the gate lines G1-Gn. Each 3-level scanning signal sequentially includes a first gate-on voltage, a first feed-through compensation voltage, and a first gate-off voltage wherein the gate-on voltage starts to be provided to a (Gi+1)th (1≦i≦n−1) of the gate lines G1-Gn at the time when the feed-through compensation voltage starts to be provided to a (Gi)th of the gate lines G1-Gn.

Other advantages and novel features will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, all the views are schematic.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1is an abbreviated circuit diagram of a TFT-LCD according to a preferred embodiment of the present invention. The TFT-LCD100includes an LCD panel (not shown), a gate driving circuit110, and a data driving circuit120. The LCD panel includes a TFT substrate (not shown), a CF substrate (not shown) arranged in a position facing the TFT substrate, and a liquid crystal layer (not shown) sandwiched between the TFT substrate and the CF substrate.

The TFT substrate includes a number n (where n is a natural number) of gate lines (G1-Gn) that are parallel to each other and that each extend along a first direction, and a number m (where m is also a natural number) of data lines (D1-Dm) that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The TFT substrate also includes a plurality of thin film transistors (TFTs)103that function as switching elements. The TFT substrate further includes a plurality of pixel electrodes106formed on a surface thereof facing the CF substrate. Each TFT103is provided in the vicinity of a respective point of intersection of the gate lines (G1-Gn) and the data lines (D1-Dm).

The CF substrate includes a plurality of common electrodes107opposite to the pixel electrodes106. In particular, the common electrodes107are formed on a surface of the CF substrate facing the TFT substrate, and are made from a transparent material such as ITO (Indium-Tin Oxide) or the like.

Each TFT103includes a gate electrode131, a source electrode132, and a drain electrode33. An exemplary one of the TFTs103is labeled in detail inFIG. 1. In this TFT103, the gate electrode131, the source electrode132, and the drain electrode133are connected to a gate line Gn-1, a data line Dm-1, and one pixel electrode106respectively. Liquid crystal material sandwiched between the pixel electrode106and one common electrode107on the CF substrate (not shown) is represented as a liquid crystal capacitor (Clc)108. A storage capacitor (Cs)104is formed between a next gate line Gn and the drain electrode133of the TFT103.

FIG. 2is an abbreviated block diagram of the gate driving circuit110. The gate driving circuit110includes a plurality of circuit units (C1-Cn). Each of the circuit units (C1-Cn) includes a first input terminal I1, a second input terminal I2, a first output terminal O1, and a second output terminal O2. A first power supply PH1, a second power supply PH2, and a third power supply V2are provided to each circuit unit Cn. The first power supply PH1is an alternating current power supply. The second power supply PH2is an alternating current power supply that has a reversed phase relative to the first power supply PH1. The third power supply V2is a low voltage direct current (DC) power supply.

The circuit units (C1-Cn) are connected in series through the corresponding first output terminals O1and first input terminals I1. The first input terminal of the circuit unit Cn is connected to the first output terminal O1of the circuit unit Cn-1. The first output terminal O1of the circuit unit Cn is connected to the second input terminal I1of the circuit unit Cn-1. The second output terminal O2of each of the circuit units (C1-Cn) is connected to a respective one of the gate lines (G1-Gn).

FIG. 3is a circuit diagram of an exemplary circuit unit C1. The circuit unit C1includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, and an eighth transistor P8. Each of the transistors (P1-P8) includes a gate electrode, a source electrode, and a drain electrode.

The first transistor P1and the second transistor P2are connected in series between the third power supply V2and ground through the drain electrode of the first transistor P1, the source electrode of the first transistor P1, the drain electrode of the second transistor P2, and the source electrode of the second transistor P2.

The third transistor P3and the fourth transistor P4are connected in series between the third power supply V2and ground through the drain electrode of the third transistor P3, the source electrode of the third transistor P3, the drain electrode of the fourth transistor P4, and the source electrode of the fourth transistor P4.

The fifth transistor P5and the sixth transistor P6are connected in series between the second power supply PH2and ground through the drain electrode of the fifth transistor P5, the source electrode of the fifth transistor P5, the drain electrode of the sixth transistor P6, and the source electrode of the sixth transistor P6.

The seventh transistor P7and the eighth transistor P8are connected in series between the second power supply PH2and a common voltage Vcom of the TFT-LCD100through the drain electrode of the seventh transistor P7, the source electrode of the seventh transistor P7, the drain electrode of the eighth transistor P8, and the source electrode of the eighth transistor P8.

The gate electrode of the first transistor P1and the gate electrode of the fourth transistor P4are connected to the first power supply PH1.

The gate electrode of the second transistor P2and the gate electrode of the third transistor P3are connected to be the first input terminal I1.

The gate electrode of the fifth transistor P5is connected to a connecting node between the source electrode of the third transistor P3and the drain electrode of the fourth transistor P4.

The gate electrode of the sixth transistor P6is connected to a connecting node between the source electrode of the first transistor P1and the drain electrode of the second transistor P2.

The gate electrode of the seventh transistor P7is connected to the gate electrode of the fifth transistor P5. The gate electrode of the eighth transistor P8is defined to be the second input terminal I2. A connecting node between the source electrode of the fifth transistor P5and the drain electrode of the sixth transistor P6is defined to be the first output terminal O1. A connecting node between the source electrode of the seven transistor P7and the drain electrode of the eight transistor P8is defined to be the second output terminal O2.

The first output terminal O1outputs the second power supply PH2when the fifth transistor P5is activated and the sixth transistor P6is turned off. The first output terminal O1outputs a zero volt voltage when the fifth transistor P5is turned off the sixth transistor P6is activated.

The second output terminal O2outputs the second power supply PH2when the seventh transistor P7is activated and the eighth transistor P8is turned off. The second output terminal O2outputs the common voltage Vcom when the seventh transistor P7is turned off and the eighth transistor P8is activated.

FIG. 4shows abbreviated voltage waves of a plurality of scanning signals generated by the gate driving circuit110. V0represents a gate-off voltage that is generated by the gate driving circuit110and is equal to zero volts. V1represents a gate-on voltage that is generated by the gate driving circuit110and is equal to 10 volts. V2represents a feed-through compensation voltage which is generated by the gate driving circuit110and is equal to −2 volts. The gate driving circuit1sequentially provides a gate-on voltage V1, a feed-through compensation voltage V2, and a gate-off voltage V0as a 3-level scanning signal to each of the gate lines (G1-Gn) each time. In a frame time (shown as a double-headed arrow), the gate driving circuit110sequentially scans the gate lines from G1to Gn with the 3-level scanning signals. A method whereby the gate driving circuit110provides 3-level scanning signals to scan the gate lines (G1-Gn) is defined to be a 3-level driving method.

For example, after the gate-on voltage V1is provided to one gate line Gi (1≦i≦n) of the gate lines (G1-Gn), the feed-through compensation voltage V2is provided to the gate line Gi. Then the gate-off voltage V0is provided to the gate line Gi. Thus the gate line Gi is scanned by the 3-level scanning signal. At the time the feed-through compensation voltage V2starts to be provided to the gate line Gi, the gate-on voltage V1simultaneously starts to be provided to the next gate line Gi+1 of the gates line (G1-Gn). After the gate-on voltage V1is provided to the gate line Gi+1, the feed-through compensation voltage V2and the gate-off voltage V0are sequentially provided to the gate line Gi+1.

The feed-through compensation voltage V2applied to the gate line Gi can depress or even eliminate the feed-through voltage generated by the storage capacitor104(which is located between the next gate line Gi+1 and the drain electrode133of the TFT103connected to the gate line Gi) when the gate-on voltage V1is applied to the gate line Gi+1.

FIG. 5is an exemplary voltage-transmittance graph which shows relationship between the transmittance of a pixel unit of the TFT-LCD100and the gradation voltage applied to the pixel unit. Curve “A” represents an ideal relationship between the transmittance of a pixel unit of an ideal TFT-LCD100and the gradation voltage applied to the pixel unit. Curve “B” represents the relationship between the transmittance of a pixel unit of an ideal TFT-LCD100which is driven by a 3-level driving method, and the gradation voltage applied to the pixel unit. Curve “C” represents the relationship between the transmittance of a pixel unit of the above-described conventional TFT-LCD10which is driven by a 2-level driving method, and the gradation voltage applied to the pixel unit. Comparing curve “B” and curve “C”, the position of curve “B” is closer to the ideal relationship curve “A” than is curve “C”. This demonstrates the TFT-LCD100which is driven by the 3-level driving method can depress (or even eliminate) the feed-through voltage generated by the storage capacitor104which is positioned between the drain electrode133of the TFT103connected to the gate line Gi and the next gate line Gi+1.