Data detector for detecting data in presence of control signals

Systems, methods, and other embodiments associated with a data detector that processes signals read from a storage device are described. According to one embodiment, a detector for detecting a data signal embedded in a read signal from a storage device includes a signal estimator configured to generate an estimate of the control signal from the read signal by sampling the read signal to determine characteristics of the control signal. The read signal includes the data signal and the control signal. The signal estimator uses the characteristics to calculate the estimate of the control signal. The detector also includes a cancellation unit configured to produce the data signal by cancelling the estimate of the control signal from the read signal.

BACKGROUND

Many data storage devices use detectors to reproduce data from a read signal when reading a storage medium. The detector reproduces the data by, for example, detecting the data in the read signal and converting the data from an analog signal into a binary format. However, detecting the data can be complicated by the presence of noise in the read signal. For example, the read signal can include the stored data and embedded control signals. Control signals are sometimes stored with the data to provide information about data locations in a storage medium. A data storage device uses the location information during read and write operations to ensure data is being read from a correct location in the storage medium.

However, when the control signal is present in the read signal, difficulties with decoding the data occur. Decoding difficulties occur because of interference from the control signal with detection of data and an increased signal-to-noise ratio (SNR) requirement of the detector. Thus, a higher bit error rate (BER) is present from the interference, which leads to the difficulties in decoding the read signal.

SUMMARY

In one embodiment, a detector for detecting a data signal embedded in a read signal from a storage device includes a signal estimator configured to generate an estimate of the control signal from the read signal by sampling the read signal to determine characteristics of the control signal. The read signal includes the data signal and the control signal. The signal estimator uses the characteristics to calculate the estimate of the control signal. The detector also includes a cancellation unit configured to produce the data signal by cancelling the estimate of the control signal from the read signal.

In another embodiment, the control signal is a continuous servo signal that is embedded with the data signal. The continuous servo signal guides the storage device when reading data from a storage medium of the storage device.

In another embodiment, the characteristics of the control signal include a phase and an amplitude. The cancellation unit is configured to cancel the estimate of the control signal from the read signal by combining an inverse of the estimate of the control signal with the read signal.

In another embodiment, the signal estimator is configured to remove the data signal from the read signal by using a filter and to use a remainder of the read signal to generate the estimate of the control signal.

In another embodiment, the read signal is a sinusoidal waveform. The signal estimator includes a filter that isolates a frequency band of the control signal to remove noise from the data signal of the read signal when generating the estimate of the control signal.

In one embodiment, a method for detecting a data signal embedded in a read signal of a storage device includes generating, in a hardware detector configured to perform the method, an estimate of a control signal from the read signal by sampling the read signal to determine characteristics of the control signal. The read signal includes the data signal and the control signal. Generating the estimate includes calculating the estimate using the characteristics. The method also includes producing the data signal by cancelling the estimate of the control signal from the read signal.

In another embodiment, the control signal is a continuous servo signal that is embedded with the data signal. The continuous servo signal guides the storage device when reading data from a storage medium of the storage device.

In another embodiment, the characteristics of the control signal include a phase and an amplitude. Cancelling the estimate of the control signal from the read signal includes subtracting the estimate of the control signal from the read signal.

In another embodiment, the method also includes filtering the read signal to isolate a frequency band of the control signal from the read signal. Filtering the read signal removes portions of the data signal from the read signal that have a different frequency than the control signal.

In another embodiment, generating the estimate of the control signal includes using a filter to remove portions of the data signal from the read signal and using a remainder of the read signal to generate the estimate of the control signal.

In one embodiment, a data detector for detecting a data signal embedded in a read signal that is produced by a storage device includes a signal estimator configured to determine characteristics of a servo signal from the read signal and to generate an estimate of the servo signal using the characteristics. The read signal includes the data signal and the servo signal. The data detector also includes a cancellation unit configured to output the data signal by applying the estimate of the servo signal to the read signal to cancel the servo signal from the read signal.

DETAILED DESCRIPTION

Described herein are examples of systems, methods, and other embodiments associated with a data detector that processes signals read from a storage device. In one embodiment, the signals include both data signals and embedded control signals, and the data detector is configured to reproduce or extract the data signals with a minimal amount of control signals remaining. In one embodiment, the data detector is configured to estimate the control signal from a read signal received from the storage device. The data detector uses the estimate of the control signal to cancel the actual control signal from the read signal leaving the data signal, which now has a reduced amount of interference from the control signal. With a lower amount of signals to process since some or all of the control signals are cancelled, the data signals can then be decoded at a lower error rate.

ConsiderFIG. 1, which illustrates an example of a read signal110and a comparison example of a data signal120. The read signal110is produced by a storage device (e.g., storage device230ofFIG. 2) when reading data from a storage medium (e.g., storage medium240ofFIG. 2) of the storage device. The storage medium in the storage device includes a section with data and a section with control information (e.g., control signals). The sections can be arranged in multiple layers with one layer on top of the other or the sections can be arranged side-by-side. In either case, when the storage device reads the storage medium the sections are read in tandem, which produces the read signal110that includes not only data like the data signal120but also embedded control signals (e.g., the read signal110is a superposition of a control signal and the data signal120). The embedded control signal, for example, is a low frequency (compared to the data signal120) sinusoidal signal. The control signal may also be a combination of two sinusoidal signals with different frequencies and phases.

If the data detector uses the read signal110as an input to a data decoder, the resulting data would include a high rate of errors. As seen inFIG. 1, the read signal110differs from the actual data signal120because of interference caused by the control signal in the read signal110. The high rate of errors in the data detector results from the control signal interfering with detection of data indicated in the read signal110. Accordingly, the data detector described herein is configured to extract the data signal120from the read signal110by applying an estimate of the control signal to the read signal110, to cancel the control signal and produce the data signal120. The data signal120is then provided to a data decoder to produce data with fewer errors because of a reduced amount of noise in the data signal120compared with the read signal110.

It is noted that cancelling the control signal is not intended to imply that the control signal is completely eliminated or removed from the read signal every time. The control signal may be partially removed during a cancellation process.

With reference toFIG. 2, one embodiment of a detector200is shown that is associated with producing a data signal that is embedded with a control signal. The detector200includes a signal estimator210and a cancellation unit220. The detector200is, for example, a hardware device (e.g., an integrated circuit) that is integrated within or is in communication with a storage device230. The storage device is, for example, a hard disk drive (HDD), a magnetic tape drive, or other storage device that produces a combined data and control signal when reading data from a storage medium240. The storage medium240may be a magnetic medium, an optical medium, electronic medium, and so on.

The signal estimator210receives a read signal (e.g., read signal110) that needs to be decoded from the storage device230. The signal estimator210is configured to generate an estimate signal that corresponds to the control signal embedded in the read signal. The control signal is, for example, a continuous servo signal that guides the storage device230by providing a location of data in the storage medium240. When the storage device230reads the storage medium240, the location in the storage medium240is read in tandem with the data. This results in the read signal including the control signal (e.g., location information) and the data signal.

To estimate the control signal, the signal estimator210samples the read signal to determine characteristics of the control signal. Sampling the read signal includes determining a current value (e.g., a voltage level) of the read signal. The signal estimator210samples the read signal at a predetermined frequency. In general, the predetermined frequency is twice a fundamental frequency of the control signal. However, depending on sampling requirements of the detector200, the predetermined frequency can be higher than twice the fundamental frequency of the control signal when, for example, a higher degree of accuracy is desired.

From sample values, the signal estimator210determines the characteristics of the control signal and then estimates the control signal. The characteristics include an amplitude (A) of the control signal and a phase (θ) of the control signal. Because the control signal is a sinusoidal waveform, the control signal can be represented by equation (1), as follows:
s(k)=Asin(2πfskT+θ)  (1)

A is the amplitude of the control signal.

θ is the phase of the control signal.

fsis a fundamental frequency of the control signal.

k is a sample value of the read signal.

T is a sampling frequency of the control signal. As previously described, the sampling frequency is twice the fundamental frequency (fs) or higher (e.g., four times the fundamental frequency), in one embodiment. Thus, T can be represented as ¼fswhen the sampling frequency is four times the fundamental frequency. Substituting ¼fsfor T in equation (1) results in equation (2), which follows.

When the sampling frequency of the read signal is four times the fundamental frequency, the signal estimator210produces an estimate of the control signal using equation (2) using estimated values of the amplitude and the phase determined from the read signal. An output of the signal estimator210is connected to the cancellation unit220to provide the estimate of the control signal to the cancellation unit220. The cancellation unit220also receives the read signal from the storage device. In one embodiment, the cancellation unit220is configured to produce the data signal by subtracting the estimate of the control signal from the read signal.

The cancellation unit220can also remove the control signal from the read signal by, for example, applying an inverse of the estimate of the control signal to the read signal in order to extract the data signal. An output of the cancellation unit220provides the data signal to, for example, a data decoder, which decodes the data signal to produce data in a binary format that can then be sent to a host computer.

Further aspects of estimating the control signal are discussed with respect toFIG. 3.FIG. 3illustrates one embodiment of a signal estimator300associated with estimating a control signal. InFIG. 3, the signal estimator300includes a filter310, an analog-to-digital converter (ADC)320, a gain controller330, a phase controller340, and a control signal generator350.

In one embodiment, the filter310is a band-pass filter or other filter that isolates a portion of the read signal. In the signal estimator300, the filter310is the first component to receive the read signal. The filter310receives the read signal first in order to remove portions of the read signal that have a different frequency than the control signal. In this way, the filter310isolates a portion of the read signal where the control signal is embedded and permits other components (e.g., the gain controller330and the phase controller340) to process the read signal without the presence of unwanted portions of the read signal. The filter310removes a majority of the data signal from the read signal which leaves a remainder of the read signal that includes the control signal and, possibly, some noise.

Accordingly, removing unwanted portions from the read signal permits the other components to more accurately and quickly determine values of the characteristics of the control signal. The components can more accurately and quickly determine the values since less noise is present after the filter310removes the unwanted portions of the read signal. The filter310can alternatively be implemented after the ADC320but before the gain controller330and the phase controller340.

The ADC320converts the read signal, received from the filter310, to a digital form. In one embodiment, the ADC320is configured to sample the read signal at a desired frequency (e.g., four samples per period). Once the ADC320samples and converts the read signal into a digital form, an output of the ADC320provides the read signal to the gain controller330and the phase controller340.

The gain controller330is configured to determine an estimate of an amplitude of the control signal. For example, the gain controller330uses adjacent sample values (s(k) and s(k+1)) of the read signal to calculate the estimate of the amplitude (A). The gain controller330is configured to square each sample value, sum the squared values, and then take a square root of the sum to calculate the amplitude. The calculated amplitude is provided as an output to the control signal generator350. Equation (3) illustrates the calculation performed by the gain controller330.
A=√{square root over (s(k)2+s(k+1)2)}{square root over (s(k)2+s(k+1)2)}  (3)

In one embodiment, the gain controller330averages the estimate of the amplitude with previous estimates and provides the average to the control signal generator350. For example, the gain controller330calculates a moving average of several estimated amplitudes and provides a value of the moving average to the control signal generator350. In this way, the gain controller330accounts for short-term fluctuations in the amplitude and can highlight longer-term trends to reduce a possibility of errors.

Alternatively, in one embodiment, the gain controller330is configured to estimate the amplitude using an envelope detector and automatic gain control. The envelope detector provides a coarse estimate of the amplitude by tracking bounds of an amplitude of the read signal. The coarse estimate of the amplitude from the envelope detector is then refined using automatic gain control (AGC) to produce the estimate of the amplitude that is provided to the control signal generator350.

The phase controller340is configured to determine an estimate of a phase of the control signal. For example, the phase controller340uses adjacent sample values (s(k) and s(k+1)) of the read signal to calculate the estimate of the phase (θ). The phase controller340is configured to calculate the arctangent of adjacent values to estimate the phase. The estimate of the phase is provided as an output to the control signal generator350. Equation (4) illustrates the calculation performed by the phase controller340.

In one embodiment, the phase controller340averages the estimate of the phase with previous phase estimates and provides the average to the control signal generator350. For example, the phase controller340calculates a moving average of several estimated phases and provides a value of the moving average to the control signal generator350. In this way, the phase controller340accounts for fluctuations in the phase of the control signal and can reduce a possibility of errors.

Alternatively, in one embodiment, the phase controller340is configured to estimate the phase using a timing recovery function. The timing recovery function estimates the phase by converging a phase of the control signal with a known phase. The phase controller340provides the estimated phase to the control signal generator350.

The control signal generator350receives the estimate of the amplitude from the gain controller330and the estimate of the phase from the phase controller340. The control signal generator350is configured to calculate an estimate of the control signal using the estimate of the phase estimate and the estimate of the amplitude. The estimate of the control signal is a reconstructed form of the control signal that is provided to a cancellation unit (e.g., cancellation unit220ofFIG. 2). The data signal can then be reproduced by cancelling the estimate of the control signal from the read signal.

Further aspects of estimating the control signal are discussed with respect toFIG. 4.FIG. 4illustrates one embodiment of a signal estimator400associated with estimating a control signal from a read signal. InFIG. 3, the signal estimator400includes a filter410, a signal multiplier420, an analog-to-digital converter (ADC)430, a gain controller440, a phase controller450, and a control signal generator460. The signal estimator400includes components similar to components of the signal estimator300ofFIG. 3. For example, the signal estimator400includes the same components as the signal estimator300except the signal estimator400includes the signal multiplier420, which is not included in the signal estimator300. Additionally, the signal estimator400includes a gain loop470and a timing recovery loop480.

The signal estimator400is configured to account for an offset (Δfs) from a nominal frequency (fs) in the control signal. The offset (Δfs) can occur in the control signal, for example, when a storage device uses different read and write frequencies. Accordingly, the gain loop470and the timing recovery loop480correct for the offset. Equation (5) illustrates an estimate of the control signal with the offset (Δfs).
s(k)=Asin(2π(fs+Δfs)kT+θ)  (5)

In the signal estimator400, the filter410is the first component to receive the read signal. The filter410is configured to remove portions of the read signal that have a different frequency than the control signal. The filter410provides remaining portions of the read signal to the signal multiplier420.

The signal multiplier420is part of the gain loop470. The gain loop470is configured to feedback an estimated amplitude from the gain controller440to the signal multiplier420. The signal multiplier420multiplies an inverse of the estimated amplitude with the output of the filter410. In this way, the signal multiplier420refines an estimate of the amplitude. An output of the signal multiplier420is provided to the ADC430. In one embodiment, the multiplier420can be implemented using a variable gain amplifier.

The ADC430converts the read signal from a sinusoidal analog waveform into a digital format. The ADC430is configured to sample the read signal at a desired sampling frequency. The desired sampling frequency is, for example, twice the nominal frequency (fs). Once sampled by the ADC430, sampled values of the read signal are provided to the gain controller440and the frequency and phase controller450. However, prior to providing the sampled values, the ADC430corrects the sampled values using an estimate of the phase (θ) and the frequency offset (Δfs) that are received as feedback from the frequency and phase controller450through the timing recovery loop480. The timing recovery loop480is illustrated with a single connection between the ADC430and the frequency and phase controller450. However, the timing recovery loop480can include individual connections for the estimate of the phase and for the offset.

The ADC430uses the estimate of the phase and the offset to correct the read signal for the offset. Once the read signal is corrected, sampled values of the read signal are provided by the ADC430to the gain controller440and the frequency and phase controller450.

In one embodiment, the gain controller440is similar to the gain controller330ofFIG. 3. For example, the gain controller440is configured to use adjacent sample values (s(k) and s(k+1)) of the read signal with equation (3) to calculate an estimate of the amplitude (A). Alternatively, in one embodiment, the gain controller440is configured to estimate the amplitude using an envelope detector. The envelope detector provides a coarse estimate of the amplitude by tracking bounds of an amplitude of the read signal. The coarse estimate of the amplitude is refined using automatic gain control (AGC). The AGC is implemented through the gain loop470to feedback the coarse estimate to refine the amplitude at the multiplier420. The gain controller440provides the estimate of the amplitude to the control signal generator460.

The control signal generator460also receives an input from the frequency and phase controller450. In one embodiment, the frequency and phase controller450is similar to the phase controller340ofFIG. 3. For example, the frequency and phase controller440is configured to use adjacent sample values (s(k) and s(k+1)) of the read signal with equation (4) to calculate the estimate of the phase (θ). The frequency and phase controller450is also configured to determine a value of the offset.

Alternatively, in one embodiment, the frequency and phase controller450is configured to estimate the phase and the frequency offset using a timing recovery loop480. A timing recovery function is implemented using feedback to the ADC430through the timing recovery loop480. The frequency and phase controller450provides the estimate of the phase and the offset to the control signal generator460and through the timing recovery loop480to the ADC430.

The control signal generator460is configured to reconstruct the control signal using the estimate of the amplitude, the estimate of the phase, and the offset. The signal estimator400produces the estimate of the control signal and provides the estimate of the control signal to a cancellation unit (e.g., cancellation unit220ofFIG. 2) to cancel the control signal from the read signal.

Further aspects of estimating the control signal are discussed with respect toFIG. 5.FIG. 5illustrates one embodiment of a method500associated with reproducing a data signal that is embedded with a control signal.FIG. 5will be discussed from the perspective of the detector200ofFIG. 2.

At510, the detector200filters the read signal. For example, a storage device that is reading a storage medium provides the read signal to the detector200as the read signal is generated. The detector200isolates a frequency band of the control signal from the read signal by filtering other frequencies from the read signal that are not consistent with the control signal. In this way, the detector200removes extraneous portions of the read signal that may interfere with later processing.

At520, the detector200samples the read signal. The detector200samples the read signal by, for example, determining a current value (e.g. a voltage level) of the read signal. The detector200samples the read signal at a sampling frequency to provide a sufficient number of data points to accurately reproduce the control signal. In one example, the detector200samples the read signal at twice a fundamental frequency of the control signal.

At530, the detector200determines characteristics of the control signal from the samples taken at520. The characteristics include, for example, a phase (θ) of the control signal and an amplitude (A) of the control signal. In one embodiment, at530, the detector200determines a phase of the control signal by calculating an arc tangent of adjacent samples of the read signal as illustrated in equation (4). Additionally, at530, the detector200determines an amplitude of the control signal by calculating a square of adjacent samples of the read signal. The detector200can determine the square of adjacent samples using equation (3).

In another embodiment, at530, the detector200determines the amplitude by tracking an amplitude of the read signal to produce a coarse estimate of the amplitude. The detector200refines the coarse estimate of the amplitude to produce an estimate of the amplitude of the control signal by using a feedback loop (gain loop) to perform automatic gain control on the coarse estimate. As a result, the detector produces an estimate of the amplitude of the control signal.

Additionally, at530, the detector200determines the phase by applying a timing recovery function to the read signal. In one embodiment, the timing recovery function is used to correct a frequency offset (Δfs) that is present in the control signal. The timing recovery function is implemented with a timing recovery loop that provides a feedback of the frequency offset and the phase. Accordingly, using the timing recovery loop the detector200can correct for the offset and provide a more accurate estimate of the phase.

At540, the detector200uses the characteristics determined at530to generate an estimate of the control signal. In one embodiment, the detector calculates the estimate of the control signal according to, for example, equation (2). In another embodiment, the detector200uses equation (5) to calculate an estimate of the control signal.

At550, the detector200cancels the estimate of the control signal from the read signal to produce a data signal. The data signal can then be decoded by a data decoder to reproduce encoded data with a lower bit error rate (BER) than is achieved if the read signal where used as a direct input to a data decoder. Accordingly, the method500achieves better data recovery by cancelling the control signal from the read signal using an estimate of the control signal.

FIG. 6illustrates another embodiment of the detector200fromFIG. 2that is configured with separate integrated circuits and/or chips. In this embodiment, the signal estimator210fromFIG. 2is embodied as a separate integrated circuit610. Additionally, the cancellation unit220is embodied on an individual integrated circuit620. The circuits are connected via connection paths to communicate signals. While integrated circuits610and620are illustrated as separate integrated circuits, they may be integrated into a common circuit board600. Additionally, integrated circuits610and620may be combined into fewer integrated circuits or divided into more integrated circuits than illustrated. In another embodiment, the signal estimator210and the cancellation unit220illustrated in integrated circuits610and620may be combined into a separate application specific integrated circuit. In other embodiments, the functionality associated with the signal estimator220may be embodied as firmware executable by a processor.

“Logic”, as used herein, includes but is not limited to hardware, firmware, instructions stored on a non-transitory medium or in execution on a machine, and/or combinations of each to perform a function(s) or an action(s), and/or to cause a function or action from another logic, method, and/or system. Logic may include a software controlled microprocessor, a discrete logic (e.g., ASIC), an analog circuit, a digital circuit, a programmed logic device, a memory device containing instructions, and so on. Logic may include one or more gates, combinations of gates, or other circuit components. Where multiple logics are described, it may be possible to incorporate the multiple logics into one physical logic. Similarly, where a single logic is described, it may be possible to distribute that single logic between multiple physical logics. One or more of the components and functions described herein may be implemented using one or more of the logic elements.

While for purposes of simplicity of explanation, illustrated methodologies are shown and described as a series of blocks. The methodologies are not limited by the order of the blocks as some blocks can occur in different orders and/or concurrently with other blocks from that shown and described. Moreover, less than all the illustrated blocks may be used to implement an example methodology. Blocks may be combined or separated into multiple components. Furthermore, additional and/or alternative methodologies can employ additional, not illustrated blocks.