Solid-state imaging device and driving method thereof, and electronic apparatus

A solid-state imaging device includes a photoelectric conversion unit, a light shielding unit and a transfer transistor. The photoelectric conversion unit generates charges by photoelectrically converting light. The light shielding unit is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit. The transfer transistor transfers charges generated in the photoelectric conversion unit. During a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor. During a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Japanese Priority Patent Application JP 2013-136216 filed Jun. 28, 2013, the entire contents of which are incorporated herein by reference.

BACKGROUND

The present disclosure relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus, and in particular, to a solid-state imaging device and a driving method thereof, and an electronic apparatus, capable of improving characteristics of pixels.

In the related art, in electronic apparatuses with imaging functions, such as digital still cameras and digital video cameras, solid-state imaging devices such as, a Charge Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS) image sensor are used. The solid-state imaging devices include a pixel in which a photodiode (PD) performing photoelectric conversion and a plurality of transistors are combined and an image is formed based on pixel signals which are output from a plurality of the pixels which are arranged in a plane manner.

For example, in the solid-state imaging device, charges accumulated in the PD are transferred to a Floating Diffusion (FD) unit having a predetermined capacity which is provided in a connection portion between the PD and a gate electrode of an amplifying transistor. Then, signals corresponding to a level of the charges stored in the FD unit are read from the pixel and AD-converted by an Analog Digital (AD) conversion circuit having a comparator so as to output the AD-converted signals.

In recent years, the solid-state imaging devices tend to have many pixels. Thus, when a pixel miniaturization is intended without changing the chip size, there is a problem that the light incident characteristics deteriorate and color mixing occurs between pixels.

For example, Japanese Unexamined Patent Application Publication No. 2010-169911 discloses a solid-state imaging device which performs an element separation optically and electrically by embedding an inter-pixel element separation film and a pixel light shielding film on a side on which light of a PD is incident, in order to reduce the color mixing between pixels. Further, Japanese Unexamined Patent Application Publication No. 2011-40531 discloses a solid-state imaging device that suppresses generation of a dark current by employing a fixed charge film.

Further, it has been known that the color mixing between pixels can be significantly reduced by employing an embedding technology in the solid-state imaging device.

Furthermore, Japanese Unexamined Patent Application Publication No. 2004-306144 discloses a solid-state imaging device that assists a charge transfer, for example, by applying a voltage to a poly-silicon embedded in a trench portion other than a drive signal of a normal pixel. Further, it is possible to intend to suppress the dark current, to improve a saturation charge amount, and to realize a low voltage drive, by applying a voltage to the trench portion.

In addition, Japanese Unexamined Patent Application Publication No. 2007-25807 discloses a solid-state imaging device capable of intending to suppress the dark current and of improving the saturation charge amount, by providing electrodes in an upper part and a lower part of the PD so as to apply a suitable voltage.

SUMMARY

However, in the solid-state imaging devices described above, it is not assumed that a potential is applied to a light shielding film and there is a problem that optical color mixing between pixels deteriorates when a pixel miniaturization is processed. Thus, the characteristics of the pixels deteriorate.

The present disclosure is made in view of such circumstances and intended to improve the characteristics of pixels.

According to an embodiment of the present disclosure, there is provided a solid-state imaging device including: a photoelectric conversion unit that generates charges by photoelectrically converting light; a light shielding unit that is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit; and a transfer transistor that transfers charges generated in the photoelectric conversion unit, wherein during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor, and wherein during a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

According to another embodiment of the present disclosure, there is provided a driving method of a solid-state imaging device including a photoelectric conversion unit that generates charges by photoelectrically converting light, a light shielding unit that is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit, and a transfer transistor that transfers charges generated in the photoelectric conversion unit, including: supplying a potential that repels the charges to the light shielding unit and a gate electrode of the transfer transistor, during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit; and supplying a potential that repels the charges to the light shielding unit and supplying a potential that attracts the charges to the gate electrode of the transfer transistor, during a charge transfer period in which charges are transferred from the photoelectric conversion unit.

According to still another embodiment of the present disclosure, there is provided an electronic apparatus including: a solid-state imaging device including a photoelectric conversion unit that generates charges by photoelectrically converting light; a light shielding unit that is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit; and a transfer transistor that transfers charges generated in the photoelectric conversion unit, wherein during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor, and wherein during a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

In the embodiments, during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor, and during a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

According to the embodiments of the present disclosure, it is possible to improve characteristics of pixels.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to drawings.

FIG. 1is a block diagram illustrating a configuration example of an embodiment of a solid-state imaging device according to an embodiment of the present technology.

As illustrated inFIG. 1, a solid-state imaging device11is a CMOS-type solid-state imaging device, and is configured to include a pixel array unit12, a vertical driving unit13, a column processing unit14, a horizontal driving unit15, an output unit16, and a driving control unit17.

The pixel array unit12includes a plurality of pixels21which are arranged in an array shape, is connected to the vertical driving unit13through a plurality of horizontal signal lines22corresponding to the number of rows of the pixel21, and is connected to the column processing unit14through a plurality of vertical signal lines23corresponding to the number of columns of the pixel21. In other words, the plurality of pixels21included in the pixel array unit12are respectively disposed at points in which the horizontal signal lines22and the vertical signal lines23intersect.

The vertical driving unit13sequentially supplies drive signals for driving (transferring, selecting, resetting, or the like) the respective pixels21to respective rows of the plurality of pixels21included in the pixel array unit12through the horizontal signal line22.

The column processing unit14extracts the signal levels of pixel signals by performing a Correlated Double Sampling (CDS) process on the pixel signals which are output from the respective pixels21and acquires pixel data corresponding to the amount of received light of the pixels21, through the vertical signal line23.

The horizontal driving unit15sequentially supplies the column processing unit14with drive signals for outputting the pixel data which is acquired from the respective pixels21from the column processing unit14, for each column of the plurality of pixels21included in the pixel array unit12.

The pixel data is supplied from the column processing unit14to the output unit16at a timing corresponding to the drive signal of the horizontal driving unit15, and the output unit16amplifies, for example, the pixel data and outputs the amplified pixel data to an image processing circuit in the subsequent stage.

The driving control unit17controls the driving of each block in the solid-state imaging device11. For example, the driving control unit17generates a block signal according to the driving period of each block and supplies the block signal to each block.

FIGS. 2A to 2Care diagrams illustrating a first configuration example of a pixel21included in a solid-state imaging device11.

FIG. 2Aillustrates a cross-sectional configuration example of the pixel21which is the first configuration example. In addition, light is incident on the pixel21from the top inFIG. 2A, and hereinafter, appropriately, a surface on a side on which light is incident is referred to as a light incident surface, and a surface facing the side opposite to the light incident surface is referred to as an opposite surface. Further,FIG. 2Billustrates a planar configuration example of the solid-state imaging device11as viewed from the opposite surface side, andFIG. 2Cillustrates a planar configuration example of the solid-state imaging device11as viewed from the light incident surface side.

As illustrated inFIGS. 2A to 2C, the pixel21is configured with a wiring layer31and a sensor layer32which are laminated, and a color filter layer and an on-chip lens layer, which are not shown, are laminated on the light incident surface side of the sensor layer32.

The wiring layer31includes a plurality of layers of wirings41formed between interlayer insulating films42, and three layers of wirings41-1to41-3are formed in a configuration example ofFIGS. 2A to 2C.

In the sensor layer32, a PD52and an FD unit53are formed on a semiconductor substrate51, a gate electrode54is laminated on the opposite surface side of the semiconductor substrate51, a fixed charge film55is laminated on the light incident surface side of the semiconductor substrate51, and an engraved light shielding electrode57is formed in a trench formed on the light incident surface of the semiconductor substrate51, through the fixed charge film55and a barrier metal56.

The semiconductor substrate51is a silicon substrate (P well) to which P-type impurities are injected. The PD52is formed by a PN junction formed by N-type impurities being injected to the semiconductor substrate51, and generates charges by photoelectrically converting the received light to accumulate the generated charges.

The FD unit53is a dense N-type region (floating diffusion region) formed by injecting N-type impurities in the vicinity of the opposite surface of the semiconductor substrate51, and temporarily stores the charges transferred from the PD52. Further, the FD unit53is a charge detection unit that converts the charges into a voltage, and the charges stored in the FD unit53are converted into a voltage in an amplifying transistor (an amplifying transistor62inFIG. 4which will be described later). The gate electrode54is an electrode constituting a gate of a transfer transistor (a transfer transistor61inFIG. 4which will be described later) which transfers charges accumulated in the PD52to the FD unit53.

The fixed charge film55is a film that holds, for example, negative fixed charges, and suppresses the generation of a dark current at a boundary surface of the semiconductor substrate51. In addition, an insulating film may be used instead of the fixed charge film55. The barrier metal56is a metal film which is formed for diffusion preventing or interaction preventing of a metal material forming the engraved light shielding electrode57.

For example, as illustrated inFIG. 2C, the engraved light shielding electrode57is formed so as to surround the outer periphery of the PD52. For example, an engraved light shielding film55is formed in such a manner that a trench is formed so as to surround the PD52on the light incident surface of the semiconductor substrate51, the fixed charge film55and the barrier metal56are formed on the inside of the trench, and then a metal having a light shielding property is embedded in the trench.

Accordingly, the engraved light shielding electrode57can prevent the occurance of an optical crosstalk and an electric crosstalk with other adjacent pixels21. In other words, the engraved light shielding electrode57can prevent the light incident on the pixel21from leaking to other pixels21, and prevent charges generated by photoelectric conversion in the pixel21from leaking to other pixels21.

Further, the vertical driving unit13is connected to the engraved light shielding electrode57through the horizontal signal line22ofFIG. 1, and a potential of a level corresponding to the signal supplied from the vertical driving unit13is applied to the engraved light shielding electrode57. For example, a negative potential is applied to the engraved light shielding electrode57, during a charge accumulation period in which charges are accumulated in the PD52, and during a charge transfer period in which charges are transferred from the PD52to the FD unit53. Further, a negative potential is applied to the gate electrode54during the charge accumulation period, and a positive potential is applied to the gate electrode54during the charge transfer period.

An operation of a potential applied during the charge accumulation period and during the charge transfer period will be described with reference toFIGS. 3A and 3B.

FIG. 3Aillustrates the pixel21during the charge accumulation period, andFIG. 3Billustrates the pixel21during the charge transfer period. In addition, the light incident on the pixel21is converted into electrons e in the PD52. Further, as illustrated inFIGS. 3A and 3B, the light incident on the pixel21in an oblique direction is prevented from leaking to other adjacent pixels21by being reflected on the engraved light shielding electrode57.

As illustrated inFIG. 3A, in the pixel21, a force pushing electrons e to the center of the PD52is generated as indicated by the hollow arrows by applying negative potentials (potentials that repel electrons e) to the gate electrode54and the engraved light shielding electrode57during the charge accumulation period. Accordingly, the pixel21can deepen the potential well of the PD52during the charge accumulation period and increase the saturation charge amount of the PD52. Further, in the pixel21, it is possible to suppress the generation of a dark current by applying a negative potential.

Further, during the charge transfer period, in the pixel21, a negative potential is applied to the engraved light shielding electrode57, whereas a positive potential (the potential of attracting electrons e) is applied to the gate electrode54. Thus, as indicated by the hollow arrows inFIG. 3B, a force pushing electrons e to the center of the PD52and the gate electrode54is generated. Accordingly, as indicated by the hollow arrow illustrated in dashed lines inFIG. 3B, in the pixel21, it is possible to assist the flow of the electrons e to the gate electrode54, and to improve the transfer performance of charges from the PD52to the FD unit53.

In this manner, it is possible to increase the saturation charge amount of the PD52and to suppress the generation of a dark current during the charge accumulation period, whereas it is possible to improve the transfer performance of charges during the charge transfer period, thereby improving the characteristics of the pixel21. Thus, for example, it is possible to improve an S/N ratio and to reduce noise at low light conditions in the pixel21.

Further, in the solid-state imaging device11, the materials used in the engraved light shielding electrode57on the light incident surface side can be used, for example, for light shielding in an optical black region. Thus, it is possible to reduce the number of steps in the production of the solid-state imaging device11. Further, it is possible to control the overflows of charges to other adjacent pixels21in the solid-state imaging device11.

Next, a driving method of the pixel21will be described with reference toFIGS. 4 and 5.

FIG. 4illustrates a circuit configuration of the pixel21.FIG. 5illustrates a drive signal supplied to the pixel21and potentials of respective units in the pixel21.

As illustrated inFIG. 4, the pixel21is configured to include a transfer transistor61, an amplifying transistor62, a selection transistor63, and a reset transistor64as well as the PD52, the FD unit53, the gate electrode54, and the engraved light shielding electrode57, which are described with reference toFIGS. 2A to 2C, and is connected to the vertical signal line23.

The transfer transistor61is driven according to a transfer signal TG supplied from the vertical driving unit13ofFIG. 1, and if the transfer signal TG supplied to the gate electrode54of the transfer transistor61is at a high level, the transfer transistor61is turned ON. Thus, the charges accumulated in the PD52are transferred to the FD unit53through the transfer transistor61.

The amplifying transistor62is an input portion of a source follower which is a reading circuit that reads signals obtained by the photoelectric conversion in the PD52, and outputs pixel signals of a level corresponding to the charges accumulated in the FD unit53to the vertical signal line23. In other words, the amplifying transistor62constitutes the source follower with a current source (not shown) connected to one end of the vertical signal line23by the drain electrode of the amplifying transistor62being connected to the power supply voltage through the selection transistor63and the source electrode thereof being connected to the vertical signal line23.

The selection transistor63is driven according to a selection signal SEL supplied from the vertical driving unit13ofFIG. 1, and if the selection signal SEL supplied to the gate electrode is at a high level, the selection transistor63is turned ON and the power supply voltage is connected to the amplifying transistor62.

The reset transistor64is driven according to a reset signal RES supplied from the vertical driving unit13ofFIG. 1. For example, if the reset signal RES supplied to the gate electrode is at a high level, the reset transistor64is turned ON, and resets the FD unit53by discharging the charges accumulated in the FD unit53to the power supply voltage.

Further, in the pixel21, as described above with reference toFIGS. 3A and 3B, a light shielding electrode applying voltage VRDis supplied from the vertical driving unit13to the engraved light shielding electrode57in order to apply the potential to the engraved light shielding electrode57.

FIG. 5illustrates, in order from the top, the selection signal SEL, the reset signal RES, the transfer signal TG, the light shielding electrode applying voltages VRD(1) and VRD(2), the potential level VFDof the FD unit53, and the potential level VSIGof the vertical signal line23. In addition, inFIG. 5, inverted signals (that is, −VRD(1) and −VRD(2)) are illustrated as the light shielding electrode applying voltages VRD(1) and VRD(2), and when the applying voltage is at a high level, a negative potential is applied to the engraved light shielding electrode57.

Here, it is possible to select either the light shielding electrode applying voltage VRD(1) or the light shielding electrode applying voltage VRD(2) for use in response to the operation of the pixel21. For example, the light shielding electrode applying voltage VRD(1) is selected for use in a case of performing a normal expected operation, and the light shielding electrode applying voltage VRD(2) is selected for use in a case of performing a pinning enhancement operation and a transfer assist enhancement operation.

Further, inFIG. 5, a timing t1is a timing at which selecting the pixel21as a pixel which outputs a pixel signal is started, and a timing t2is a timing at which charge transfer from the PD52to the FD unit53is started. Further, a timing t3is a timing at which selecting the pixel21as a pixel which outputs a pixel signal is terminated.

First, if the accumulation of charges of the PD52is started before the timing t1at which selecting the pixel21is started, the light shielding electrode applying voltage VRD(1) is switched from the low level to the high level. Similarly, the light shielding electrode applying voltage VRD(2) is switched from a low level to a first high level. Thus, a negative potential is applied to the engraved light shielding electrode57. In addition, the low level of the transfer signal TG is set to a negative potential and during a period other than the charge transfer period, a negative potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG.

Accordingly, during a period of accumulation of charges in the PD52, a negative potential is applied to the gate electrode54and the engraved light shielding electrode57, and as illustrated inFIG. 3A, a force pushing electrons e to the center of the PD52is generated.

Then, at the timing t1, the selection signal SEL is at a high level such that the pixel21is selected; and the reset signal RES is at a high level such that the potential level VFDof the FD unit53is reset. In other words, the FD unit53is in a state in which charges transferred to the FD unit53prior to the present process are left, and the charges are discharged to the power supply voltage. As a consequence of this, the potential level VSIGof the vertical signal line23varies depending on the potential level VFD(that is, a reset level) of the FD unit53. Thereafter, the reset signal RES is at a low level and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read as a potential of a reset level to the column processing unit14ofFIG. 1.

Next, at the timing t2, the transfer signal TG is at a high level such that the charges accumulated in the PD52are transferred to the FD unit53. In other words, at this time, a positive potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG. Accordingly, when charges are transferred from the PD52, a negative potential is applied to the engraved light shielding electrode57, whereas a positive potential is applied to the gate electrode54, such that, as illustrated inFIG. 3B, the flow of electrons e to the gate electrode54is assisted.

Further, at the timing t2, the light shielding electrode applying voltage VRD(2) is switched from the first high level to a second high level of a higher level.

Accordingly, if the light shielding electrode applying voltage VRD(2) is selected for use, when charges are transferred from the PD52, a negative potential corresponding to the second high level which is higher than the negative potential corresponding to the first high level is applied to the engraved light shielding electrode57.

Then, if charges are transferred from the PD52to the FD unit53, the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23vary depending on the amount of charges transferred to the FD unit53. Thereafter, the transfer signal TG is at a low level and the transfer of charges is terminated and thus the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read out to the column processing unit14ofFIG. 1as a potential of the pixel signal level.

Thereafter, at the timing t3, the selection signal SEL is at a low level and thus the selection of the pixel21is terminated. At this time, the light shielding electrode applying voltage VRD(1) is switched from a high level to a low level, and the light shielding electrode applying voltage VRD(2) is switched from the second high level to the low level.

Further, when the light shielding electrode applying voltage VRD(2) is selected as a voltage to be applied to the engraved light shielding electrode57, during the charge transfer period, a negative potential of the second high level which is at a higher level than the first high level during the charge accumulation period is applied to the engraved light shielding electrode57. Thus, the transfer assist of charge can be further enhanced.

Next,FIGS. 6A to 6Care diagrams illustrating a second configuration example of the pixel21included in the solid-state imaging device11.

FIG. 6Aillustrates a cross-sectional configuration example of the pixel21-1which is the second configuration example,FIG. 6Billustrates a planar configuration example of the pixel21-1as viewed from the opposite surface side, andFIG. 6Cillustrates a planar configuration example of the pixel21-1as viewed from the light incident surface side.

As illustrated inFIGS. 6A to 6C, the pixel21-1has a different configuration from the pixel21ofFIGS. 2A to 2Cin that a planar electrode72is laminated through an insulating film71on the opposite surface side of the semiconductor substrate51and a transparent conductive film74is laminated through a barrier metal73on a light incident surface side of the semiconductor substrate51.

In addition, otherwise, the pixel21-1has common components with the pixel21ofFIGS. 2A to 2C, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-1has a configuration common to the pixel21ofFIGS. 2A to 2Cin that the PD52and the FD unit53are formed on the semiconductor substrate51, the gate electrode54is laminated on the opposite surface side of the semiconductor substrate51, the fixed charge film55is laminated on the light incident surface side of the semiconductor substrate51, and the engraved light shielding electrode57is formed in the trench which is formed on the light incident surface of the semiconductor substrate51, through the fixed charge film55and the barrier metal56.

The insulating film71is a film having an insulating property and insulates a part between the semiconductor substrate51and the planar electrode72. The planar electrode72is an electrode disposed in a plane manner with respect to the opposite surface of the sensor layer32, and as illustrated inFIG. 6B, is configured so as to cover the entire surface of the pixel21-1other than a region in which the FD unit53and the gate electrode54are formed, on the opposite surface of the sensor layer32.

The barrier metal73is a metal film which is formed for diffusion prevention or interaction prevention of a metal material forming the transparent conductive film74. The transparent conductive film74is a film having optical transparency and electrical conductivity, and is formed so as to cover the entire surface of the pixel21-1in the light incident surface of the sensor layer32.

Then, in the pixel21-1, the vertical driving unit13is respectively connected to the planar electrode72and the transparent conductive film74through a horizontal signal line22ofFIG. 1, and a potential of a level corresponding to signals supplied from the vertical driving unit13is applied thereto. For example, a negative potential is applied to the planar electrode72during the charge accumulation period, and a positive potential is applied thereto during the charge transfer period. Further, a negative potential is applied to the transparent conductive film74, during the charge accumulation period and during the charge transfer period.

An operation of a potential applied during the charge accumulation period and during the charge transfer period will be described with reference toFIGS. 7A and 7B.

FIG. 7Aillustrates the pixel21-1during the charge accumulation period, andFIG. 7Billustrates the pixel21-1during the charge transfer period. In addition, the light incident on the pixel21-1is converted into electrons e in the PD52. Further, as illustrated inFIGS. 7A and 7B, the light incident on the pixel21-1in an oblique direction is prevented from leaking to other adjacent pixels21by being reflected on the engraved light shielding electrode57.

As illustrated inFIG. 7A, in the pixel21-1, a negative potential is applied to the gate electrode54, the engraved light shielding electrode57, the planar electrode72, and the transparent conductive film74during the charge accumulation period. Thus, as indicated by the hollow arrows inFIG. 7A, a force pushing electrons e to the center of the PD52is generated. Accordingly, the pixel21-1can deepen the potential well of the PD52during the charge accumulation period and increase the saturation charge amount of the PD52. Further, in the pixel21-1, it is possible to suppress the generation of a dark current by applying a negative potential.

Further, during the charge transfer period, in the pixel21-1, a negative potential is applied to the engraved light shielding electrode57and the transparent conductive film74, whereas a positive potential is applied to the gate electrode54and the planar electrode72. Thus, as indicated by the hollow arrows inFIG. 7B, a force pushing electrons e to the center of the PD52and to the opposite surface is generated. Accordingly, as indicated by the hollow arrows of a dashed line inFIG. 7B, in the pixel21-1, it is possible to assist the flow of the electrons e to the gate electrode54which is located on the opposite surface, and to improve the transfer performance of charges from the PD52to the FD unit53.

In this manner, it is possible to increase the saturation charge amount of the PD52and to suppress the generation of a dark current during the charge accumulation period, whereas it is possible to improve the transfer performance of charges during the charge transfer period, thereby improving the characteristics of the pixel21-1.

Next, a driving method of the pixel21-1will be described with reference toFIGS. 8 and 9.

FIG. 8illustrates a circuit configuration of the pixel21-1.FIG. 9illustrates a drive signal supplied to the pixel21-1and potentials of respective units in the pixel21-1.

As illustrated inFIG. 8, the pixel21-1has a different configuration from the pixel21ofFIG. 4in that a planar electrode72is disposed on the opposite surface side of the sensor layer32and a transparent conductive film74is disposed on the light incident surface side of the sensor layer32. In addition, the pixel21-1has common components with the pixel21ofFIG. 4in other parts, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-1is configured to include a transfer transistor61, an amplifying transistor62, a selection transistor63, and a reset transistor64, and is connected to a vertical signal line23.

Further, in the pixel21-1, a planar electrode applying voltage VTSFis supplied from the vertical driving unit13to the planar electrode72in order to apply the potentials, described with reference toFIGS. 7A and 7B, to the planar electrode72. Similarly, in the pixel21-1, a transparent conductive film applying voltage VTRis supplied from the vertical driving unit13to the transparent conductive film74in order to apply the potentials, described with reference toFIGS. 7A and 7B, to the transparent conductive film74.

FIG. 9illustrates, in order from the top, the selection signal SEL, the reset signal RES, the transfer signal TG, the light shielding electrode applying voltages VRD(1) and VRD(2), the transparent conductive film applying voltages VTR(1) and VTR(2), the planar electrode applying voltages VTSF(1) and VTSF(2), the potential level VFDof the FD unit53, and the potential level VSIGof the vertical signal line23.

Here, the light shielding electrode applying voltage VRD(1) and the transparent conductive film applying voltage VTR(1) are common, and the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) are common. Further, the light shielding electrode applying voltages VRD(1) and VRD(2) and the transparent conductive film applying voltages VTR(1) and VTR(2) are represented as inverted signals, and when the applying voltage is a high level, a negative potential is applied. In addition, the low level of the planar electrode applying voltages VTSF(1) and VTSF(2) is a negative potential, and the high level of the planar electrode applying voltages VTSF(1) and VTSF(2) is a positive potential.

Further, it is possible to select either a pair of the light shielding electrode applying voltage VRD(1) and transparent conductive film applying voltage VTR(1) or a pair of the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) for use in response to the operation of the pixel21-1. For example, the light shielding electrode applying voltage VRD(1) and the transparent conductive film applying voltage VTR(1) are selected for use in a case of performing a normal expected operation. In contrast, the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) are selected for use in a case of performing a pinning enhancement operation and a transfer assist enhancement operation.

In the same manner, it is possible to select either the planar electrode applying voltage VTSF(1) or the planar electrode applying voltage VTSF(2) for use in response to the operation of the pixel21-1. For example, the planar electrode applying voltage VTSF(1) is selected for use in a case of performing a normal expected operation, and the planar electrode applying voltage VTSF(2) is selected for use in a case of performing an operation of performing a transfer after causing charges to approach the vicinity of the opposite surface.

Further, inFIG. 9, a timing t1is a timing at which selecting the pixel21-1as a pixel which outputs a pixel signal is started, and a timing t2is a timing at which charge transfer from the PD52to the FD unit53is started. Further, a timing t3is a timing at which selecting the pixel21-1as a pixel which outputs a pixel signal is terminated.

First, if the accumulation of charges of the PD52is started before the timing t1at which selecting the pixel21-1is started, the light shielding electrode applying voltage VRD(1) and the transparent conductive film applying voltage VTR(1) are switched from the low level to the high level. Similarly, the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) are switched from the low level to a first high level. Thus, a negative potential is applied to the engraved light shielding electrode57and the transparent conductive film74. Further, at this time, the planar electrode applying voltages VTSF(1) and VTSF(2) are at a low level, a negative potential is applied to the planar electrode72. In addition, the low level of the transfer signal TG is set to a negative potential and during a period other than the charge transfer period, a negative potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG.

Accordingly, during a period of accumulation of charges in the PD52, a negative potential is applied to the gate electrode54, the engraved light shielding electrode57, the transparent conductive film74, and the planar electrode72, and as illustrated inFIG. 7A, a force pushing electrons e to the center of the PD52is generated.

Then, at the timing t1, the selection signal SEL is at a high level such that the pixel21-1is selected; and the reset signal RES is at a high level such that the potential level VFDof the FD unit53is reset. In other words, the FD unit53is in a state in which charges transferred to the FD unit53prior to the present process are left, and the charges are discharged to the power supply voltage. As a consequence of this, the potential level VSIGof the vertical signal line23varies depending on the potential level VFD(that is, a reset level) of the FD unit53. Thereafter, the reset signal RES is at a low level and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read as a potential of a reset level to the column processing unit14ofFIG. 1.

Next, at the timing t2, the transfer signal TG is at a high level such that the charges accumulated in the PD52are transferred to the FD unit53. In other words, at this time, a positive potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG. Further, simultaneously with the transfer signal TG, the planar electrode applying voltage VTSF(1) is at a high level such that a positive potential is applied to the planar electrode72according to the planar electrode applying voltage VTSF(1).

Accordingly, when charges are transferred from the PD52, a negative potential is applied to the engraved light shielding electrode57and the transparent conductive film74, whereas a positive potential is applied to the gate electrode54and the planar electrode72, such that as illustrated inFIG. 7B, the flow of electrons e to the gate electrode54is assisted.

Further, at the timing t2, the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) are switched from the first high level to a second high level of a higher level. Accordingly, if the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) are selected for use, when charges are transferred from the PD52, a negative potential corresponding to the second high level which is higher than the negative potential corresponding to the first high level is applied to the engraved light shielding electrode57and the transparent conductive film74.

Then, if charges are transferred from the PD52to the FD unit53, the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23vary depending on the amount of charges transferred to the FD unit53. Thereafter, the transfer signal TG and the planar electrode applying voltage VTSF(1) are at a low level such that the transfer of charges is terminated and thus the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read out to the column processing unit14ofFIG. 1as a potential of the pixel signal level.

Here, the planar electrode applying voltage VTSF(2) is at a high level at a predetermined timing later than the planar electrode applying voltage VTSF(1). In other words, when the planar electrode applying voltage VTSF(2) is selected for use, a positive potential is applied to the planar electrode72at a timing later than a timing at which a positive potential is applied to the gate electrode54. Thus, for example, when charges are transferred from the PD52to the FD unit53, electrons e are drawn to the opposite surface side of the semiconductor substrate51after the flow of electrons e to the gate electrode54is formed, such that the leakage of electrons e along the opposite surface of the semiconductor substrate51is prevented.

Thereafter, at the timing t3, the selection signal SEL is at a low level and thus the selection of the pixel21-1is terminated. At this time, the light shielding electrode applying voltage VRD(1) and the transparent conductive film applying voltage VTR(1) are switched from a high level to a low level. In the same manner, the light shielding electrode applying voltage VRD(2) and the transparent conductive film applying voltage VTR(2) are switched from the second high level to the low level.

Next,FIGS. 10A to 10Care diagrams illustrating a third configuration example of the pixel21included in the solid-state imaging device11.

FIG. 10Aillustrates a cross-sectional configuration example of the pixel21-2which is the third configuration example,FIG. 10Billustrates a planar configuration example of the pixel21-2as viewed from the opposite surface side, andFIG. 10Cillustrates a planar configuration example of the pixel21-2as viewed from the light incident surface side.

As illustrated inFIGS. 10A to 10C, the pixel21-2has a different configuration from the pixel21ofFIGS. 2A to 2Cin that the engraved light shielding electrode57is divided into the engraved light shielding electrodes57a-1and57a-2. In addition, otherwise, the pixel21-2has common components with the pixel21ofFIGS. 2A to 2C, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-2has a configuration common to the pixel21ofFIGS. 2A to 2Cin that the PD52and the FD unit53are formed on the semiconductor substrate51and the gate electrode54is laminated on the opposite surface side of the semiconductor substrate51.

As illustrated inFIG. 10C, the engraved light shielding electrode57a-1is formed to surround the three side surfaces of the PD52, that is, to surround the side surfaces of the PD52other than the side surface on the side on which the FD unit53and the gate electrode54are formed. Further, the engraved light shielding electrode57a-2is formed along the side surface of the PD52on the side in which the FD unit53and the gate electrode54are formed.

In other words, in the pixel21-2, a first trench is formed along three side surfaces other than the side surface of the PD52on the side in which the FD unit53and the gate electrode54are formed, from the light incident surface of the semiconductor substrate51, and a second trench is formed along the side surface of the PD52on the side in which the FD unit53and the gate electrode54are formed. Then, the engraved light shielding electrode57a-1is formed in the first trench through the fixed charge film55aand the barrier metal56a-1, and the engraved light shielding electrode57a-2is formed in the second trench through the fixed charge film55aand the barrier metal56a-2.

Then, in the pixel21-2, the vertical driving unit13is connected to the engraved light shielding electrodes57a-1and57a-2through the horizontal signal line22ofFIG. 1, and a potential of a level corresponding to signals supplied from the vertical driving unit13is applied thereto. For example, a negative potential is applied to the engraved light shielding electrode57a-1during the charge accumulation period and during the charge transfer period. Further, a negative potential is applied to the engraved light shielding electrode57a-2during the charge accumulation period, and a positive potential is applied to the engraved light shielding electrode57a-2during the charge transfer period.

An operation of a potential applied during the charge accumulation period and during the charge transfer period will be described with reference toFIGS. 11A and 11B.

FIG. 11Aillustrates the pixel21-2during the charge accumulation period, andFIG. 11Billustrates the pixel21-2during the charge transfer period. In addition, the light incident on the pixel21-2is converted into electrons e in the PD52. Further, as illustrated inFIGS. 11A and 11B, the light incident on the pixel21-2in an oblique direction is prevented from leaking to other adjacent pixels21by being reflected on the engraved light shielding electrode57.

As illustrated inFIG. 11A, in the pixel21-2, a negative potential is applied to the gate electrode54, the engraved light shielding electrode57a-1, and the engraved light shielding electrode57a-2during the charge accumulation period. Thus, as indicated by the hollow arrows inFIG. 11A, a force pushing electrons e to the center of the PD52is generated. Accordingly, the pixel21-2can deepen the potential well of the PD52during the charge accumulation period and increase the saturation charge amount of the PD52. Further, in the pixel21-2, it is possible to suppress the generation of a dark current by applying a negative potential.

Further, during the charge transfer period, in the pixel21-2, a negative potential is applied to the engraved light shielding electrode57a-1, whereas a positive potential is applied to the gate electrode54and the engraved light shielding electrode57a-2. Thus, as indicated by the hollow arrows inFIG. 11B, a force pushing electrons e to a side surface on the engraved light shielding electrode57a-2side and the gate electrode54is generated. Accordingly, as indicated by the hollow arrows of a dashed line inFIG. 11B, in the pixel21-2, it is possible to assist the flow of the electrons e to the gate electrode54which is located on the engraved light shielding electrode57a-2side, and to improve the transfer performance of charges from the PD52to the FD unit53.

In addition, during the charge transfer period, 0 V may be applied to the engraved light shielding electrode57a-2. Even in this case, the flow of electrons e to the engraved light shielding electrode57a-2side is assisted by the negative potential applied to the engraved light shielding electrode57a-1.

In this manner, it is possible to increase the saturation charge amount of the PD52and to suppress the generation of a dark current during the charge accumulation period, whereas it is possible to improve the transfer performance of charges during the charge transfer period, thereby improving the characteristics of the pixel21-2.

Next, a driving method of the pixel21-2will be described with reference toFIGS. 12 and 13.

FIG. 12illustrates a circuit configuration of the pixel21-2.FIG. 13illustrates a drive signal supplied to the pixel21-2and potentials of respective units in the pixel21-2.

As illustrated inFIG. 12, the pixel21-2has a different configuration from the pixel21ofFIG. 4in that an engraved light shielding electrode57a-2is disposed on the FD unit53side of the PD52, and an engraved light shielding electrode57a-1is disposed on the opposite side thereto. In addition, the pixel21-2has common components with the pixel21ofFIG. 4in other parts, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-2is configured to include a transfer transistor61, an amplifying transistor62, a selection transistor63, and a reset transistor64, and is connected to a vertical signal line23.

Further, in the pixel21-2, light shielding electrode applying voltages VRD1and VRD2are respectively supplied from the vertical driving unit13to the engraved light shielding electrodes57a-1and57a-2in order to apply the potentials described above with reference toFIGS. 11A and 11Bto the engraved light shielding electrodes57a-1and57a-2.

FIG. 13illustrates, in order from the top, the selection signal SEL, the reset signal RES, the transfer signal TG, the light shielding electrode applying voltages VRD1(1) and VRD1(2), the light shielding electrode applying voltages VRD2(1) and VRD2(2), the potential level VFDof the FD unit53, and the potential level VSIGof the vertical signal line23.

Here, it is possible to select either the light shielding electrode applying voltage VRD1(1) or the light shielding electrode applying voltage VRD1(2) for use in response to the operation of the pixel21-2. For example, the light shielding electrode applying voltage VRD1(1) is selected for use in a case of performing a normal expected operation. In contrast, the light shielding electrode applying voltage VRD1(2) is selected for use in a case of performing a pinning enhancement operation and a transfer assist enhancement operation. In the same manner, it is possible to select either the light shielding electrode applying voltage VRD2(1) or the light shielding electrode applying voltage VRD2(2) for use in response to the operation of the pixel21-2. For example, the light shielding electrode applying voltage VRD2(1) is selected for use in a case of performing a normal expected operation. In contrast, the light shielding electrode applying voltage VRD2(2) is selected for use in a case of performing a transfer assist operation of approaching the vicinity of the FD unit53once.

Further, inFIG. 13, a timing t1is a timing at which selecting the pixel21-2as a pixel which outputs a pixel signal is started, and a timing t2is a timing at which charge transfer from the PD52to the FD unit53is started. Further, a timing t3is a timing at which selecting the pixel21-2as a pixel which outputs a pixel signal is terminated.

First, if the accumulation of charges of the PD52is started before the timing t1at which selecting the pixel21-2is started, the light shielding electrode applying voltage VRD1(1) is switched from the low level to the high level, and the light shielding electrode applying voltage VRD1(2) is switched from the low level to the first high level. Further, similarly, the light shielding electrode applying voltages VRD2(1) and VRD2(2) are switched from the low level to the high level. Thus, a negative potential is applied to the engraved light shielding electrodes57a-1and57a-2. In addition, the low level of the transfer signal TG is set to a negative potential and during a period other than the charge transfer period, a negative potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG.

Accordingly, during a period of accumulation of charges in the PD52, a negative potential is applied to the gate electrode54and the engraved light shielding electrodes57a-1and57a-2, and as illustrated inFIG. 11A, a force pushing electrons e to the center of the PD52is generated.

Then, at the timing t1, the selection signal SEL is at a high level such that the pixel21-2is selected; and the reset signal RES is at a high level such that the potential level VFDof the FD unit53is reset. In other words, the FD unit53is in a state in which charges transferred to the FD unit53prior to the present process are left, and the charges are discharged to the power supply voltage. As a consequence of this, the potential level VSIGof the vertical signal line23varies depending on the potential level VFD(that is, a reset level) of the FD unit53. Thereafter, the reset signal RES is at a low level and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read as a potential of a reset level to the column processing unit14ofFIG. 1.

Next, at the timing t2, the transfer signal TG is at a high level such that the charges accumulated in the PD52are transferred to the FD unit53. In other words, at this time, a positive potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG. Further, simultaneously with the transfer signal TG, the light shielding electrode applying voltage VRD2(1) is at a low level such that a positive potential is applied to the engraved light shielding electrode57a-2according to the light shielding electrode applying voltage VRD2(1).

Accordingly, when charges are transferred from the PD52, a negative potential is applied to the engraved light shielding electrode57a-1, whereas a positive potential is applied to the gate electrode54and the engraved light shielding electrode57a-2, such that as illustrated inFIG. 11B, the flow of electrons e to the gate electrode54located on the engraved light shielding electrode57a-2side is assisted.

Further, at the timing t2, the light shielding electrode applying voltage VRD1(2) is switched from the first high level to a second high level of a higher level. Accordingly, if the light shielding electrode applying voltage VRD1(2) is selected for use, when charges are transferred from the PD52, a negative potential corresponding to the second high level which is higher than the negative potential corresponding to the first high level is applied to the engraved light shielding electrode57a-1.

In addition, the light shielding electrode applying voltage VRD2(2) is at a low level at a predetermined timing before the timing t2, and a positive potential is applied to the engraved light shielding electrode57a-2. Thus, prior to the charge transfer, an assist of causing electrons e to approach the vicinity of the FD unit53is performed first.

Then, if charges are transferred from the PD52to the FD unit53, the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23vary depending on the amount of charges transferred to the FD unit53. Thereafter, the transfer signal TG is at a low level and the transfer of charges is terminated and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read out to the column processing unit14ofFIG. 1as a potential of the pixel signal level.

Thereafter, at the timing t3, the selection signal SEL is at a low level and thus the selection of the pixel21-2is terminated. At this time, the light shielding electrode applying voltage VRD1(1) is switched from a high level to a low level, and the light shielding electrode applying voltage VRD1(2) is switched from the second high level to the low level.

Next,FIGS. 14A to 14Care diagrams illustrating a fourth configuration example of the pixel21included in the solid-state imaging device11.

FIG. 14Aillustrates a cross-sectional configuration example of the pixel21-3which is the fourth configuration example,FIG. 14Billustrates a planar configuration example of the pixel21-3as viewed from the opposite surface side, andFIG. 14Cillustrates a planar configuration example of the pixel21-3as viewed from the light incident surface side.

As illustrated inFIGS. 14A to 14C, the pixel21-3has a different configuration from the pixel21ofFIGS. 2A to 2Cin that the engraved light shielding electrode57is divided into the engraved light shielding electrodes57b-1and57b-2. In addition, otherwise, the pixel21-3has common components with the pixel21ofFIGS. 2A to 2C, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-3has a configuration common to the pixel21ofFIGS. 2A to 2Cin that a PD52and an FD unit53are formed on the semiconductor substrate51and a gate electrode54is laminated on an opposite surface side of the semiconductor substrate51.

As illustrated inFIG. 14A, in the pixel21-3, the engraved light shielding electrode57b-2is formed in a trench formed on the light incident surface side of the semiconductor substrate51, whereas the engraved light shielding electrode57b-1is formed in a trench formed on the opposite surface side of the semiconductor substrate51. Then, as illustrated inFIG. 14B, the engraved light shielding electrode57b-1is formed to surround the three side surfaces of the PD52, that is, to surround the side surfaces of the PD52other than the side surface on the side in which the FD unit53and the gate electrode54are formed. Further, the engraved light shielding electrode57b-2is formed along the side surface of the PD52on the side in which the FD unit53and the gate electrode54are formed, and as illustrated inFIG. 14C, is formed to surround the PD52while being laminated on the light incident surface of the semiconductor substrate51.

In other words, in the pixel21-3, a first trench is formed along three side surfaces other than the side surface of the PD52on the side in which the FD unit53and the gate electrode54are formed, from the opposite surface of the semiconductor substrate51. Then, the engraved light shielding electrode57b-1is formed in the first trench through the fixed charge film55b-1and the barrier metal56b-1.

In other words, in the pixel21-3, a second trench is formed along the side surface of the PD52on the side in which the FD unit53and the gate electrode54are formed, from the light incident surface of the semiconductor substrate51. Then, the engraved light shielding electrode57b-2is formed in the second trench through the fixed charge film55b-2and the barrier metal56b-2, and the engraved light shielding electrode57b-2is formed to surround the PD52on the light incident surface of the semiconductor substrate51through the fixed charge film55b-2.

Then, in the pixel21-3, the vertical driving unit13is connected to the engraved light shielding electrodes57b-1and57b-2through the horizontal signal line22ofFIG. 1, and a potential of a level corresponding to signals supplied from the vertical driving unit13is applied thereto. For example, a negative potential is applied to the engraved light shielding electrode57b-1during the charge accumulation period and during the charge transfer period. Further, a negative potential is applied to the engraved light shielding electrode57a-2during the charge accumulation period, and 0 V is applied to the engraved light shielding electrode57a-2during the charge transfer period.

An operation of a potential applied during the charge accumulation period and during the charge transfer period will be described with reference toFIGS. 15A and 15B.

FIG. 15Aillustrates the pixel21-3during the charge accumulation period, andFIG. 15Billustrates the pixel21-3during the charge transfer period. In addition, the light incident on the pixel21-3is converted into electrons e in the PD52. Further, as illustrated inFIGS. 15A and 15B, the light incident on the pixel21-3in an oblique direction is prevented from leaking to other adjacent pixels21by being reflected on the engraved light shielding electrode57.

As illustrated inFIG. 15A, in the pixel21-3, a negative potential is applied to the gate electrode54, the engraved light shielding electrode57b-1, and the engraved light shielding electrode57b-2during the charge accumulation period. Thus, as indicated by the hollow arrows inFIG. 15A, a force pushing electrons e to the center of the PD52is generated. Accordingly, the pixel21-3can deepen the potential well of the PD52during the charge accumulation period and increase the saturation charge amount of the PD52. Further, in the pixel21-3, it is possible to suppress the generation of a dark current by applying a negative potential.

Further, during the charge transfer period, in the pixel21-3, a negative potential is applied to the engraved light shielding electrode57b-1, whereas a positive potential is applied to the gate electrode54, and 0 V is applied to the engraved light shielding electrode57b-2. Thus, as indicated by the hollow arrows inFIG. 15B, a force pushing electrons e from the engraved light shielding electrode57b-1to the engraved light shielding electrode57b-2and the gate electrode54is generated. Accordingly, as indicated by the hollow arrows of a dashed line inFIG. 15B, in the pixel21-3, it is possible to assist the flow of the electrons e to the gate electrode54which is located on the engraved light shielding electrode57a-2side, and to improve the transfer performance of charges from the PD52to the FD unit53.

In addition, a positive potential may be applied to the engraved light shielding electrode57b-2during the charge transfer period. Even in this case, the flow of electrons e to the engraved light shielding electrode57a-2side is assisted by the positive potential applied to the engraved light shielding electrode57b-2. Further, when the engraved light shielding electrode57b-2is located in the vicinity of the gate electrode54, the flow of electrons e to the gate electrode54is assisted by applying the negative potential to the engraved light shielding electrode57b-2during the charge transfer period.

In this manner, it is possible to increase the saturation charge amount of the PD52and to suppress the generation of a dark current during the charge accumulation period, whereas it is possible to improve the transfer performance of charges during the charge transfer period, thereby improving the characteristics of the pixel21-3.

Next, a driving method of the pixel21-3will be described with reference toFIGS. 16 and 17.

FIG. 16illustrates a circuit configuration of the pixel21-3.FIG. 17illustrates a drive signal supplied to the pixel21-3and potentials of respective units in the pixel21-3.

As illustrated inFIG. 16, the pixel21-3has a different configuration from the pixel21ofFIG. 4in that an engraved light shielding electrode57b-2is disposed on the light incident surface side of the FD unit53side of the PD52, and an engraved light shielding electrode57b-1is disposed on the opposite surface side of the opposite side thereto. In addition, the pixel21-3has common components with the pixel21ofFIG. 4in other parts, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-3is configured to include a transfer transistor61, an amplifying transistor62, a selection transistor63, and a reset transistor64, and is connected to a vertical signal line23.

Further, in the pixel21-3, light shielding electrode applying voltages VFDand VRDare respectively supplied from the vertical driving unit13to the engraved light shielding electrodes57b-1and57b-2in order to apply the potentials described above with reference toFIG. 15to the engraved light shielding electrodes57b-1and57b-2.

FIG. 17illustrates, in order from the top, the selection signal SEL, the reset signal RES, the transfer signal TG, the light shielding electrode applying voltages VFD(1) and VFD(2), the light shielding electrode applying voltages VRD(1) and VRD(2), the potential level VFDof the FD unit53, and the potential level VSIGof the vertical signal line23.

Here, it is possible to select either the light shielding electrode applying voltage VFD(1) or the light shielding electrode applying voltage VFD(2) for use in response to the operation of the pixel21-3. For example, the light shielding electrode applying voltage VFD(1) is selected for use in a case of performing a normal expected operation. In contrast, the light shielding electrode applying voltage VFD(2) is selected for use in a case of performing a pinning enhancement operation and a transfer assist enhancement operation. In the same manner, it is possible to select either the light shielding electrode applying voltage VRD(1) or the light shielding electrode applying voltage VRD(2) for use in response to the operation of the pixel21-3. For example, the light shielding electrode applying voltage VRD(1) is selected for use in a case of performing a normal expected operation. In contrast, the light shielding electrode applying voltage VRD(2) is selected for use in a case of performing a transfer assist operation of approaching the vicinity of the FD unit53once.

Further, inFIG. 17, a timing t1is a timing at which selecting the pixel21-3as a pixel which outputs a pixel signal is started, and a timing t2is a timing at which charge transfer from the PD52to the FD unit53is started. Further, a timing t3is a timing at which selecting the pixel21-3as a pixel which outputs a pixel signal is terminated.

First, if the accumulation of charges of the PD52is started before the timing t1at which selecting the pixel21-3is started, the light shielding electrode applying voltage VFD(1) is switched from the low level to the high level, and the light shielding electrode applying voltage VFD(2) is switched from the low level to the high level. Further, similarly, the light shielding electrode applying voltages VRD(1) and VRD(2) are switched from the low level to the high level. Thus, a negative potential is applied to the engraved light shielding electrodes57b-1and57b-2. In addition, the low level of the transfer signal TG is set to a negative potential and during a period other than the charge transfer period, a negative potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG.

Accordingly, during a period of accumulation of charges in the PD52, a negative potential is applied to the gate electrode54and the engraved light shielding electrodes57b-1and57b-2, and as illustrated inFIG. 15A, a force pushing electrons e to the center of the PD52is generated.

Then, at the timing t1, the selection signal SEL is at a high level such that the pixel21-3is selected; and the reset signal RES is at a high level such that the potential level VFDof the FD unit53is reset. In other words, the FD unit53is in a state in which charges transferred to the FD unit53prior to the present process are left, and the charges are discharged to the power supply voltage. As a consequence of this, the potential level VSIGof the vertical signal line23varies depending on the potential level VFD(that is, a reset level) of the FD unit53. Thereafter, the reset signal RES is at a low level and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read as a potential of a reset level to the column processing unit14ofFIG. 1.

Next, at the timing t2, the transfer signal TG is at a high level such that the charges accumulated in the PD52are transferred to the FD unit53. In other words, at this time, a positive potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG. Further, at the timing t2, the light shielding electrode applying voltage VRD(1) is at a low level such that 0 V is applied to the engraved light shielding electrode57b-2.

Accordingly, when charges are transferred from the PD52, a negative potential is applied to the engraved light shielding electrode57b-1, whereas 0 V is applied to the engraved light shielding electrode57b-1, and thus a positive potential is applied to the gate electrode54. Thus, as illustrated inFIG. 15B, the flow of electrons e to the gate electrode54located on the engraved light shielding electrode57a-2side is assisted.

Further, at the timing t2, the light shielding electrode applying voltage VFD(2) is switched from the first high level to a second high level of a higher level. Accordingly, if the light shielding electrode applying voltage VFD(2) is selected for use, when charges are transferred from the PD52, a negative potential corresponding to the second high level which is higher than the negative potential corresponding to the first high level is applied to the engraved light shielding electrode57b-1.

In addition, the light shielding electrode applying voltage VRD(2) is at a low level at a predetermined timing before the timing t2, and thus 0 V is applied to the engraved light shielding electrode57b-2. Thus, prior to the charge transfer, an assist of causing electrons e to approach the vicinity of the FD unit53is performed first.

Then, if charges are transferred from the PD52to the FD unit53, the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23vary depending on the amount of charges transferred to the FD unit53. Thereafter, after the transfer signal TG is at a low level and the transfer of charges is terminated and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, the potential level VSIGof the vertical signal line23is read out to the column processing unit14ofFIG. 1as a potential of the pixel signal level.

Thereafter, at the timing t3, the selection signal SEL is at a low level and thus the selection of the pixel21-3is terminated. At this time, the light shielding electrode applying voltage VFD(1) is switched from a high level to a low level, and the light shielding electrode applying voltage VFD(2) is switched from the second high level to the low level.

Next,FIGS. 18A to 18Care diagrams illustrating a fifth configuration example of the pixel21included in the solid-state imaging device11.

FIG. 18Aillustrates a cross-sectional configuration example of the pixel21-4which is the fifth configuration example,FIG. 18Billustrates a planar configuration example of the pixel21-4as viewed from the opposite surface side, andFIG. 18Cillustrates a planar configuration example of the pixel21-4as viewed from the light incident surface side.

As illustrated inFIGS. 18A to 18C, the pixel21-4has a different configuration from the pixel21ofFIGS. 2A to 2Cin that the engraved light shielding electrode57is divided into the engraved light shielding electrodes57b-1and57b-2. In addition, otherwise, the pixel21-4has a different configuration from the pixel21ofFIGS. 2A to 2Cin that a planar electrode72is laminated on the opposite surface side of the semiconductor substrate51through the insulating film71, and a transparent conductive film74is laminated on the light incident surface side of the semiconductor substrate51through the barrier metal73. In addition, otherwise, the pixel21-4has common components with the pixel21ofFIGS. 2A to 2C, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-4has a configuration common to the pixel21ofFIGS. 2A to 2Cin that a PD52and an FD unit53are formed on the semiconductor substrate51and a gate electrode54is laminated on an opposite surface side of the semiconductor substrate51.

Here, in the pixel21-4, the engraved light shielding electrodes57b-1and57b-2are configured in the same manner as the engraved light shielding electrodes57b-1and57b-2of the pixel21-3illustrated inFIGS. 14A to 14C. Further, the insulating film71, the planar electrode72, the barrier metal73, and the transparent conductive film74in the pixel21-4are configured in the same manner as the insulating film71, the planar electrode72, the barrier metal73, and the transparent conductive film74of the pixel21-1illustrated inFIGS. 6A to 6C.

An operation of a potential applied during the charge accumulation period and during the charge transfer period will be described with reference toFIGS. 19A and 19B.

FIG. 19Aillustrates the pixel21-4during the charge accumulation period, andFIG. 19Billustrates the pixel21-4during the charge transfer period. In addition, the light incident on the pixel21-4is converted into electrons e in the PD52. Further, as illustrated inFIGS. 19A and 19B, the light incident on the pixel21-4in an oblique direction is prevented from leaking to other adjacent pixels21by being reflected on the engraved light shielding electrode57.

As illustrated inFIG. 19A, in the pixel21-4, a negative potential is applied to the gate electrode54, the engraved light shielding electrodes57b-1and57b-2, the planar electrode72, and the transparent conductive film74during the charge accumulation period. Thus, as indicated by the hollow arrows inFIG. 19A, a force pushing electrons e to the center of the PD52is generated. Accordingly, the pixel21-4can deepen the potential well of the PD52during the charge accumulation period and increase the saturation charge amount of the PD52. Further, in the pixel21-4, it is possible to suppress the generation of a dark current by applying a negative potential.

Further, during the charge transfer period, in the pixel21-4, a negative potential is applied to the engraved light shielding electrodes57b-1and57b-2and the transparent conductive film74, whereas a positive potential is applied to the gate electrode54and the planar electrode72. Thus, as indicated by the hollow arrows inFIG. 19B, a force pushing electrons e to the center of the PD52and the opposite surface is generated. Accordingly, as indicated by the hollow arrows of a dashed line inFIG. 19B, in the pixel21-4, it is possible to assist the flow of the electrons e to the gate electrode54which is located on the opposite surface, and to improve the transfer performance of charges from the PD52to the FD unit53.

In this manner, it is possible to increase the saturation charge amount of the PD52and to suppress the generation of a dark current during the charge accumulation period, whereas it is possible to improve the transfer performance of charges during the charge transfer period, thereby improving the characteristics of the pixel21-4.

Next, a driving method of the pixel21-4will be described with reference toFIGS. 20 and 21.

FIG. 20illustrates a circuit configuration of the pixel21-4.FIG. 21illustrates a drive signal supplied to the pixel21-4and potentials of respective units in the pixel21-4.

As illustrated inFIG. 20, the pixel21-4has a different configuration from the pixel21ofFIG. 4in that an engraved light shielding electrode57c-2is disposed on the light incident surface side of the FD unit53side of the PD52, and an engraved light shielding electrode57c-1is disposed on the opposite surface side of the opposite side thereto. Further, the pixel21-4has a different configuration from the pixel21ofFIG. 4in that a planar electrode72is disposed on the opposite surface side of the sensor layer32and a transparent conductive film74is disposed on the light incident surface side of the sensor layer32. In addition, the pixel21-4has common components with the pixel21ofFIG. 4in other parts, the common components are denoted by the same reference numerals and thus the detailed description thereof will be omitted. In other words, the pixel21-4is configured to include a transfer transistor61, an amplifying transistor62, a selection transistor63, and a reset transistor64, and is connected to a vertical signal line23.

Further, in the pixel21-4, light shielding electrode applying voltages VFDand VRDare respectively supplied from the vertical driving unit13to the engraved light shielding electrodes57c-1and57c-2in order to apply the potentials described above with reference toFIGS. 19A and 19Bto the engraved light shielding electrodes57c-1and57c-2. Similarly, in the pixel21-4, a planar electrode applying voltage VTSFis supplied from the vertical driving unit13to the planar electrode72in order to apply the potentials described above with reference toFIGS. 19A and 19Bto the planar electrode72. Further, a transparent conductive film applying voltage VTRis supplied from the vertical driving unit13to the transparent conductive film74in order to apply the potentials described above with reference toFIGS. 19A and 19Bto the transparent conductive film74.

FIG. 21illustrates, in order from the top, the selection signal SEL, the reset signal RES, the transfer signal TG, the transparent conductive film applying voltages VTR(1) and VTR(2), the light shielding electrode applying voltages VFD(1) and VFD(2), the light shielding electrode applying voltages VRD(1) and VRD(2), the planar electrode applying voltages VTSF(1) and VTSF(2), the potential level VFDof the FD unit53, and the potential level VSIGof the vertical signal line23.

Here, the light shielding electrode applying voltage VFD(1) and the transparent conductive film applying voltage VTR(1) are common, and the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) are common. Further, the transparent conductive film applying voltages VTR(1) and VTR(2), the light shielding electrode applying voltage VFD(1) and VFD(2), and the light shielding electrode applying voltages VRD(1) and VRD(2) are represented as inverted signals, and when the applying voltages are at high levels, a negative potential is applied. In addition, the low level of the planar electrode applying voltages VTSF(1) and VTSF(2) is a negative potential, and the high level of the planar electrode applying voltage VTSF(1) and VTSF(2) is a positive potential.

Further, it is possible to select either a pair of the light shielding electrode applying voltage VFD(1) and the transparent conductive film applying voltage VTR(1) or a pair of the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) for use in response to the operation of the pixel21-4. For example, the pair of the light shielding electrode applying voltage VFD(1) and the transparent conductive film applying voltage VTR(1) is selected for use in a case of performing a normal expected operation. In contrast, the pair of the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) is selected for use in a case of performing a pinning enhancement operation and a transfer assist enhancement operation.

In the same manner, it is possible to select either the light shielding electrode applying voltage VRD(1) or the light shielding electrode applying voltage VRD(2) for use in response to the operation of the pixel21-4. For example, the light shielding electrode applying voltage VRD(1) is selected for use in a case of performing a normal expected operation. In contrast, the light shielding electrode applying voltage VRD(2) is selected for use in a case of performing a transfer assist operation of approaching the vicinity of the FD unit53once.

In the same manner, it is possible to select either the planar electrode applying voltage VTSF(1) or the planar electrode applying voltage VTSF(2) for use in response to the operation of the pixel21-4. For example, the planar electrode applying voltage VTSF(1) is selected for use in a case of performing a normal expected operation. In contrast, the planar electrode applying voltage VTSF(2) is selected for use in a case of performing an operation of performing a transfer while causing charges to approach the vicinity of the opposite surface.

Further, inFIG. 21, a timing t1is a timing at which selecting the pixel21-4as a pixel which outputs a pixel signal is started, and a timing t2is a timing at which charge transfer from the PD52to the FD unit53is started. Further, a timing t3is a timing at which selecting the pixel21-4as a pixel which outputs a pixel signal is terminated.

First, if the accumulation of charges of the PD52is started before the timing t1at which selecting the pixel21-4is started, the light shielding electrode applying voltage VFD(1) and the transparent conductive film applying voltage VTR(1) are switched from the low level to the high level. Further, similarly, the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) are switched from the low level to a first high level. Furthermore, similarly, the light shielding electrode applying voltages VRD(1) and VRD(2) are switched from the low level to the high level. Thus, a negative potential is applied to the engraved light shielding electrodes57c-1and57c-2and the transparent conductive film74. Further, at this time, the planar electrode applying voltages VTSF(1) and VTSF(2) are at a low level, and a negative potential is applied to the planar electrode72. In addition, the low level of the transfer signal TG is set to a negative potential and during a period other than the charge transfer period, a negative potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG.

Accordingly, during a period of accumulation of charges in the PD52, a negative potential is applied to the gate electrode54, the engraved light shielding electrodes57b-1and57b-2, the planar electrode72, and the transparent conductive film74, and as illustrated inFIG. 19A, a force pushing electrons e to the center of the PD52is generated.

Then, at the timing t1, the selection signal SEL is at a high level such that the pixel21-4is selected; and the reset signal RES is at a high level such that the potential level VFDof the FD unit53is reset. In other words, the FD unit53is in a state in which charges transferred to the FD unit53prior to the present process are left, and the charges are discharged to the power supply voltage. As a consequence of this, the potential level VSIGof the vertical signal line23varies depending on the potential level VFD(that is, a reset level) of the FD unit53. Thereafter, the reset signal RES is at a low level and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, and then the potential level VSIGof the vertical signal line23is read as a potential of a reset level to the column processing unit14ofFIG. 1.

Next, at the timing t2, the transfer signal TG is at a high level such that the charges accumulated in the PD52are transferred to the FD unit53. In other words, at this time, a positive potential is applied to the gate electrode54of the transfer transistor61according to the transfer signal TG. Further, simultaneously with the transfer signal TG, the planar electrode applying voltage VTSF(1) is at a low level such that a positive potential is applied to the planar electrode72according to the planar electrode applying voltage VTSF(1).

Accordingly, when charges are transferred from the PD52, a negative potential is applied to the engraved light shielding electrode57and the transparent conductive film74, whereas a positive potential is applied to the gate electrode54and the planar electrode72, such that as illustrated inFIG. 19B, the flow of electrons e to the gate electrode54is assisted.

Further, at the timing t2, the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) are switched from the first high level to a second high level of a higher level. Accordingly, if the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) are selected for use, when charges are transferred from the PD52, a negative potential corresponding to the second high level which is higher than the negative potential corresponding to the first high level is applied to the engraved light shielding electrode57and the transparent conductive film74.

In addition, the light shielding electrode applying voltage VRD(2) is at a low level at a predetermined timing before the timing t2, and thus 0 V is applied to the engraved light shielding electrode57b-2. Thus, prior to the charge transfer, an assist of causing electrons e to approach the vicinity of the FD unit53is performed first.

Then, if charges are transferred from the PD52to the FD unit53, the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23vary depending on the amount of charges transferred to the FD unit53. Thereafter, after the transfer signal TG and the planar electrode applying voltage VTSF(1) are at a low level and the transfer of charges is terminated and the potential level VFDof the FD unit53and the potential level VSIGof the vertical signal line23are stable, the potential level VSIGof the vertical signal line23is read out to the column processing unit14ofFIG. 1as a potential of the pixel signal level.

Here, the planar electrode applying voltage VTSF(2) is at a high level at a predetermined timing later than the planar electrode applying voltage VTSF(1). In other words, when the planar electrode applying voltage VTSF(2) is selected for use, a positive potential is applied to the planar electrode72at a timing later than a timing at which a positive potential is applied to the gate electrode54. Thus, for example, when charges are transferred from the PD52to the FD unit53, electrons e are drawn to the opposite surface side of the semiconductor substrate51after the flow of electrons e to the gate electrode54is formed, such that the leakage of electrons e along the opposite surface of the semiconductor substrate51is prevented.

Thereafter, at the timing t3, the selection signal SEL is at a low level and thus the selection of the pixel21-4is terminated. At this time, the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) are switched from a high level to a low level. In the same manner, the light shielding electrode applying voltage VFD(2) and the transparent conductive film applying voltage VTR(2) are switched from the second high level to the low level.

Further, the solid-state imaging device11described above can be applied to various electronic apparatuses including imaging systems such as digital still cameras and digital video cameras, mobile phones with an imaging function, or other apparatuses with an imaging function.

FIG. 22is a block diagram illustrating a configuration example of an imaging apparatus mounted on an electronic apparatus.

As illustrated inFIG. 22, an imaging apparatus101is configured to include an optical system102, an imaging device103, a signal processing circuit104, a monitor105, and a memory106, and is capable of capturing still images and moving images.

The optical system102is configured to include one or a plurality of lenses, and guides image light (incident light) from an object to the imaging device103so as to focus the image light on a light receiving surface (sensor unit) of the imaging device103.

As the imaging device103, a solid-state imaging device11including phase difference pixels21aof various configuration examples described above is applied. Electrons are accumulated in the imaging device103for a fixed period, according to an image focused on the light receiving surface through the optical system102. Thus, signals according to the electrons accumulated in the imaging device103are supplied to the signal processing circuit104.

The signal processing circuit104performs various signal processes on the pixel signals which are output from the imaging device103. The image (image data) obtained by the signal processing circuit104performing the signal processes is supplied to and displayed on the monitor105, or is supplied to and stored (recorded) in the memory106.

In the imaging apparatus101configured in this manner, it is possible to obtain, for example, an image with less noise even at a low intensity of illumination by employing the solid-state imaging device11including the pixel21of various configuration examples described above.

In addition, the present technology may have the following configurations.

A solid-state imaging device including:

a photoelectric conversion unit that generates charges by photoelectrically converting light;

a light shielding unit that is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit; and

a transfer transistor that transfers charges generated in the photoelectric conversion unit,

wherein during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor, and

wherein during a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

The solid-state imaging device according to (1), further including:

a conductive film having optical transparency laminated on a light incident surface side on which light enters the photoelectric conversion unit, with respect to the semiconductor substrate on which the photoelectric conversion unit is formed,

wherein during the charge accumulation period and during the charge transfer period, the potential that repels the charges is supplied to the conductive film.

The solid-state imaging device according to (1) or (2), further including:

a planar electrode laminated in a plane manner on an opposite surface side which is opposite to the light incident surface side on which light enters the photoelectric conversion unit, with respect to the semiconductor substrate on which the photoelectric conversion unit is formed,

wherein during the charge accumulation period, the potential that repels the charges is supplied to the planar electrode, and

wherein during the charge transfer period, the potential that attracts the charges is supplied to the planar electrode.

wherein a part of the light shielding unit is formed on a light incident surface side on which light enters the photoelectric conversion unit, with respect to the semiconductor substrate on which the photoelectric conversion unit is formed, and another part of the light shielding unit is formed on an opposite surface side which is opposite to the light incident surface side, and respective potentials are independently supplied to the part and the other part of the light shielding unit.

a conductive film having optical transparency laminated on a light incident surface side on which light enters the photoelectric conversion unit, with respect to the semiconductor substrate on which the photoelectric conversion unit is formed, and

a planar electrode laminated in a plane manner on an opposite surface side which is opposite to the light incident surface side on which light enters the photoelectric conversion unit, with respect to the semiconductor substrate on which the photoelectric conversion unit is formed,

wherein a part of the light shielding unit is formed on the light incident surface side on which light enters the photoelectric conversion unit, with respect to the semiconductor substrate on which the photoelectric conversion unit is formed, and the other part of the light shielding unit is formed on an opposite surface side which is opposite to the light incident surface side, and respective potentials are independently supplied to the gate electrode of the transfer transistor, the conductive film, the planar electrode, the part and the other part of the light shielding unit.

A driving method of a solid-state imaging device including a photoelectric conversion unit that generates charges by photoelectrically converting light, a light shielding unit that is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit, and a transfer transistor that transfers charges generated in the photoelectric conversion unit, including:

supplying a potential that repels the charges to the light shielding unit and a gate electrode of the transfer transistor, during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit; and

supplying the potential that repels the charges to the light shielding unit and supplying a potential that attracts the charges to the gate electrode of the transfer transistor, during a charge transfer period in which charges are transferred from the photoelectric conversion unit.

An electronic apparatus including:

a solid-state imaging device including:

a photoelectric conversion unit that generates charges by photoelectrically converting light;

a light shielding unit that is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit; and

a transfer transistor that transfers charges generated in the photoelectric conversion unit,

wherein during a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor, and

wherein during a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

It should be understood that the disclosure is not limited to the above-described embodiments, but may be modified into various forms in a range without departing from a gist of the disclosure.