Converter circuit, corresponding electronic component, device and method

A converter circuit includes an input node for receiving an input signal and an output node for providing a converted output signal to a load, a switching power stage to receive the input signal and an on-off drive signal switching between an on-state and an off-state, and a reactive output network coupled to the switching power stage and configured to provide the converted output signal to the load. The converter circuit comprises a first feedback signal path configured to generate a PWM-modulated control signal for the switching power stage as a function of the converted output signal, and a second feedback signal path including an output variation sensing circuit to generate at least one output variation signal indicative of variations of the converted output signal over time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Italian Patent Application No. 102018000009323, filed on Oct. 10, 2018, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The description relates to switching converter circuits, e.g. DC/DC fixed-frequency switching converter circuits.

One or more embodiments may be applied, for instance, to circuits for improving the output dynamic performance of switching converters, e.g. improving output regulation during load transients.

One or more embodiments may be applied, for instance, to power management integrated circuits (PMIC) comprising plural switching converter circuits.

BACKGROUND

Switching converters operating according to various operating schemes are known in the art.

For instance, so-called constant on-time switching DC/DC converters are known. Such constant on-time switching DC/DC converters typically provide good dynamic output performance, e.g. good load transient regulation. On the other hand, constant on-time switching DC/DC converters can interact in an undesired manner due to their asynchronous operation, generating excessive noise and interferences.

Other switching converters are known under the designation of fixed-frequency (voltage mode) switching DC/DC converters. Such fixed-frequency converters are less affected by noise if compared to constant on-time converters, but typically provide worse dynamic output performance, e.g. worse load transient regulation.

Recent market developments are requesting development of power management integrated circuits (PMIC) comprising plural switching converters, e.g. plural switching converters fabricated on the same silicon die, with the aim of supplying different points of load (i.e., providing different voltage levels at different output terminals/pins of a same power management integrated circuit) with increased current requirements. For instance, the output current provided by one or more switching converters in a power management integrated circuit may be rather high, in order to provide satisfactory output power capability even at low voltages.

Such power management integrated circuits may comprise plural constant on-time converters and/or fixed-frequency converters.

Despite providing good dynamic output performance, power management integrated circuits comprising plural constant on-time converters may suffer from malfunctions.

For instance, different converters may tend to switch unexpectedly at unwanted instants due to noise internal to the integrated circuit. For instance, switching operation of a certain converter may generate noise that triggers (undesired) switching of other converters. One or more converters may thus tend to “couple” themselves, e.g. operating together and at the same frequency, resulting in simultaneous commutations and consequently in converters crosstalk, increased supply current, electromagnetic interferences and power supply bouncing.

Moreover, plural converters operating at the same time in a same integrated circuit should be phase-shifted in order to result in rather uniform current demand. Constant on-time converters may not be suitable for satisfying such operating condition, due to their possible undesired synchronized operation described above.

On the other hand, power management integrated circuits comprising plural fixed-frequency converters may not be suitable for applications which require good output dynamic performance, such as applications with fast and/or large load transient variations, despite facilitating integrating and/or interleaving plural fixed-frequency converters on the same integrated circuit due to better noise immunity.

In this context, document EP 1 826 893 A1 is indicative of the state of the art relating to fixed-frequency switching converters with improved output dynamic performance, e.g. improved load transient regulation.

SUMMARY

Despite the extensive activity in the area, further improved solutions are desirable.

For instance, solutions are desirable which may provide improved output dynamic performance, e.g. improved load transient regulation, in fixed-frequency switching converters.

Another desirable feature is providing circuits for modulating the entity of the output regulation of a switching converter as a function of the amplitude and/or slope of load transient steps.

Another desirable feature is providing circuits for managing the output regulation of a switching converter with reduced systematic inaccuracies.

Another desirable feature is providing circuits for managing the output regulation of a switching converter with reduced sensitivity to the shape of the ripple of the output signal.

Solutions are desirable which may not require any external circuit component, thus being fully integrated on silicon.

Moreover, solutions are desirable which may facilitate integrating plural fixed-frequency switching converters in single power management integrated circuits.

An object of one or more embodiments is to contribute in providing such improved solutions.

According to one or more embodiments, such an object can be achieved by means of a circuit having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding electronic component.

One or more embodiments may relate to a corresponding device.

One or more embodiments may relate to a corresponding method.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

One or more embodiments may provide a switching converter circuit configured for sensing variations of the converted output signal with a dedicated feedback loop working at a frequency which is higher than the switching frequency of the converter, thus facilitating adapting the switching activity of the converter circuit to fast and/or large output load variations, thereby increasing (temporarily) the operating bandwidth of the converter.

In one or more embodiments, such dedicated feedback loop may have a negligible impact on the overall power consumption of the converter circuit.

One or more embodiments may provide a solution for integrating, on a same die, plural switching converters having robust operation against noise and improved dynamic output performance.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

By way of introduction to a detailed description of exemplary embodiments, reference may be first had toFIG. 1.

FIG. 1is exemplary of a circuit architecture of a switching converter1, particularly a buck converter, having a voltage mode main control loop (or main feedback loop) from an output node102to a feedback input node114.

It will be appreciated that reference to a buck converter in the present description is by way of example only, and that one or more embodiments may be applied to other type of switching converters (e.g., boost converters, buck-boost converters, etc.).

It will be noted that the circuit architecture exemplified inFIG. 1may apply to both fixed-frequency and constant on-time switching converters.

As exemplified inFIG. 1, a switching converter1may have a switching stage14providing a switching signal VSWat a node110. A reactive output network of the converter1may comprise an inductor LOUTcoupled between the node110and the output node102, and one or more output capacitors COUTcoupled between the output node102and a (ground) reference terminal GND.

An output load16may be coupled between the output node102and the (ground) reference terminal GND. It will be appreciated that the output load16may be a distinct element from the embodiments.

In the converter1, a feedback circuit block10may receive at a first respective input node100a reference (voltage) signal VREFand at a second respective input node114the output (voltage) signal VOUTsensed at node102.

The feedback circuit block10may comprise a differential circuit18, e.g. an error amplifier, for comparing the output (voltage) signal VOUTto the reference (voltage) signal VREF, thereby generating an error signal VERR.

The feedback circuit block10may comprise a compensation network (see, for instance, the resistive components R1, R2, R3and the capacitive components C1, C2, C3inFIG. 1), e.g. a type-III compensation network known per se. Such compensation network may facilitate compensating the converter1, e.g. compensating the conjugate complex poles introduced in the transfer function of the converter1by the reactive output elements LOUTand COUT. The compensation network may also facilitate fixing the closed loop bandwidth of the converter1and providing a high gain at low frequencies as a result of the differential circuit18being in an integrator configuration, thus resulting in a negligible difference between the values of the signals VOUTand VREFat steady-state condition.

In the converter1, the error signal VERRprovided at the output of the differential circuit18at node104is received at an input of a modulator circuit block12which generates, at a node112, a PWM-modulated signal PWMcfor driving the switching stage14.

In case the converter1is a constant on-time converter, the modulator circuit block12may comprise, according to a conventional arrangement, a constant TONmodulator and a secondary frequency-locked loop (FLL) which aims at maintaining a constant switching frequency when the converter1operates in a steady-state condition. In one or more embodiments, the constant TONmodulator may comprise a STVCOT™ controller as available with companies of the ST group (group of companies of the Assignee).

Therefore, in converters based on a constant on-time architecture, the converter switching frequency may be driven by a frequency-locked loop (FLL) with the aim of operating the converter1in a “pseudo fixed-frequency” mode.

As previously noted, in case that plural constant on-time converters are included on a same die (or in the same integrated circuit), precise control of the switching phases of such plural converters may be hard to achieve, resulting in the converters possibly switching at undesired instants, e.g. together.

In case the converter1is a fixed-frequency converter, the modulator circuit block12may comprise, according to a conventional arrangement, a fixed-frequency ramp generator circuit and a TONcomparator which compares the error signal VERRprovided at the output of the differential circuit18with the ramp signal generated by the ramp generator circuit, thereby providing a PWM-modulated signal PWMcfor driving the switching stage14.

In such fixed-frequency architecture, if a load change (e.g., an increase or decrease of the current ILOADprovided at the output load16through the output node102) occurs during the converter OFF time, the modulator circuit block12may be unable to sense such load change until the successive converter ON time, which is driven by a clock signal CLK_REF received at the modulator circuit block12.

Generally, the clock signal CLK_REF may be assumed a low-frequency signal if compared to the time-scale of the variations expected on the output load16(e.g., the clock signal CLK_REF may have a period of about 1 μs, with 1 μs=10−6s, and load variations may take place in hundreds of ns, with 1 ns=10−9s).

In case the clock signal CLK_REF is a low frequency signal (as is the case, for instance, in many high-current applications) and/or the ratio VIN/VOUTbetween the input signal at node106and the output signal at node102of the converter1is large (as is the case in many low-voltage applications, e.g. when using the converter1for supplying the core of a microcontroller or memory modules in the range of 0.8 V to 3.3 V from a 12 V PCIe or SATA bus), the duty cycle of the PWM-modulated signal PWMcdriving the switching stage14of the converter1may be quite low.

As a result of a low duty cycle of the signal PWMcat node112, the converter OFF time may be large and the output voltage VOUTmay vary considerably as a result of a load change occurring during the converter OFF time (and not being sensed until the successive converter ON time).

In order to limit such variations of the output voltage VOUT, large capacitor arrays may be provided coupled at the output node102, which however may increase the cost and area occupation of the converter1.

Therefore, in one or more embodiments, solutions are provided for improving output load transient regulation in fixed-frequency switching converters, possibly reducing the need for large capacitor arrays at the output node102.

In one or more embodiments of a converter1as exemplified inFIG. 2, an additional feedback loop is provided between the output node102and the input node112bof the switching stage14.

Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

A converter circuit1according to one or more embodiments may be integrated (in a manner known to those skilled in the art) into a substrate S. In one or more embodiments, such a substrate S can be shared by various converter circuits as exemplified herein, integrated into such a common substrate S.

In one or more embodiments, an additional feedback loop may comprise a sensing circuit block24having an input coupled to the output node102of the converter1, and the converter circuit1may comprise a control circuit block22for coupling the output nodes of both the main and additional feedback loops to the input node112bof the switching stage14, thereby providing a drive signal PWMdto the switching stage14.

The sensing circuit block24may be configured to sense the output signal VOUTat node102and/or the output current provided to the load16. In particular, the sensing circuit block24may be configured to sense high frequency variations of the output signal VOUTand/or of the output current provided to the load16, thereby generating digital control signals LTE_TRIG and LTE_SKIP, according to the operation described in the following.

The control circuit block22may be configured to sense the digital control signals LTE_TRIG, LTE_SKIP from the sensing circuit block24, and control the switching operation of the switching stage14by means of a signal PWMdgenerated as a function of such digital control signals LTE_TRIG, LTE_SKIP and of the PWM-modulated signal PWMcfrom the modulator circuit block12.

In one or more embodiments, the additional feedback loop (also called LTE loop in the present description) may facilitate extending the bandwidth of the converter1with respect to previous solutions as exemplified inFIG. 1, thus resulting in the possibility of operating the converter1at higher frequencies.

For instance,FIG. 3is exemplary of a comparison between the frequency response of a conventional “type-III” converter according toFIG. 1and a “type-III+ LTE” converter according to one or more embodiments of the present description.

FIG. 3is exemplary of the amplitude of the transfer function VOUT/VREFfor both a “type-III” converter (dashed and dotted line) and a “type-III+ LTE” converter (thin solid line), and shows that the bandwidth of a converter1according to one or more embodiments may be extended up to a frequency Fp,LTEwhich is higher than the frequency Fp1,TYPE3that limits the bandwidth of a conventional “type-III” converter.

FIG. 4is exemplary of a possible implementation of a sensing circuit block24in one or more embodiments.

A sensing circuit block24may comprise a sensing portion40having a first input node102configured to receive the output signal VOUT, a second input node410configured to receive an (internal) reference signal VREF,int, and an output node400providing a digital signal VCOMP.

It will be noted that the reference signal VREF,intmay be generated internally to the sensing portion40, or alternatively may be generated externally. In one or more embodiments, generating the reference signal VREF,intinternally may result in reduced power consumption.

A sensing circuit block24may comprise a filter portion42having an input node coupled to the output node400of the sensing portion40, and providing the digital control signals LTE_SKIP and LTE_TRIG at respective output nodes418,420.

Operation of a sensing circuit block24in one or more embodiments, which will be better detailed in the following, may be described with reference to the exemplary signals illustrated inFIG. 5.

For instance, as exemplified inFIG. 5, in case a positive load current step (i.e., a steep increase of the output current ILOADdue to a load transient, generating a sharp decrease of the output voltage VOUT) happens during an OFF time of a converter1involving a fixed-frequency architecture (i.e., while the PWM-modulated signal PWMcis low, see instant t1to t2inFIG. 5), the sensing circuit block24may be configured to force an “extra” ON time of the converter1(see instant t2to t3inFIG. 5) by forcing the drive signal PWMdreceived at the switching stage14to a high value.

In one or more embodiments, forcing an “extra” ON time of the converter1may result in a smooth output signal VOUTas a result of a filtering operation performed by the filter portion42.

It is noted that, in one or more embodiments, the frequency of the clock signal CLK_LTE provided to the sensing circuit block24for its operation may be higher than the frequency of the clock signal CLK_REF controlling operation of the modulator circuit block12.

For instance, the frequency of the clock signal CLK_LTE may be an order of magnitude higher than the frequency of the clock signal CLK_REF, thus resulting in satisfactory improvement of the output dynamic performance of the converter1during load steps (see, for instance,FIG. 5).

A possible detailed embodiment of a sensing portion40of a sensing circuit block24in one or more embodiments are exemplified inFIG. 6.

In one or more embodiments, a sensing portion40may comprise an analog sensor circuit configured to operate as a delta modulator. Such sensing portion40may be configured to sense variations of the (voltage) signal VOUTat a feedback node102of the converter1, e.g. being sensitive to voltage variations in the order of few mV, and generate an output digital signal VCOMPat a node400indicative of said variations of the (voltage) signal VOUT.

In one or more embodiments, a sensing portion40may comprise:

an input node102configured for receiving an analog feedback (voltage) signal VOUTfrom the converter1;

an output node400configured for providing an output digital signal VCOMP;

a charge pump circuit block402, configured for receiving the output digital signal VCOMPas a control signal for operation of switches SW1, SW2, and for providing an output (voltage) signal VREF,iand an output (current) signal ICPat respective nodes422and414;

a filter circuit block600, having an input coupled to node422and providing the internal (filtered) reference signal VREF,intat node410;

a band-pass filter circuit block404, configured for receiving the feedback (voltage) signal VOUTat node102and the internal reference (voltage) signal VREF,intat node410, and providing at a node412an output (voltage) signal VPindicative of the feedback (voltage) signal VOUT;

a tunable impedance circuit block406, herein named ripple filter circuit block406, configured for transducing the (current) signal ICPprovided by the charge pump circuit block402into a (voltage) signal VMat node414; and

a (three-phase) comparator circuit block408, configured for receiving signals VPand VMat respective nodes412and414and providing the output digital signal VCOMPas a result of (clocked) comparison of signals VPand VM, the comparator circuit block408operating at the frequency of the clock signal CLK_LTE.

In one or more embodiments, the sensing portion40may be designed with the aim of reducing power consumption, e.g. down to 500 nA/MHz, and setting the input root mean square (rms) noise limit of the comparator circuit block408, e.g. down to Vripple/4, wherein Vrippleis the amplitude of the ripple superposed to the signal VMat the input of the comparator408.

In one or more embodiments as exemplified inFIG. 6, during operation at steady-state condition of the converter1, as a result of the signal VOUTnot varying, the signal VPat node412may have a (constant) DC value approximately equal to the value VREF,int.

As a result of the comparator408being a clocked comparator, considering—for the sake of simplicity only—an ideal operation of the feedback loop, the signal VMat node414may oscillate around the value of signal VP.

Such oscillating behavior of the signal VMaround the value of signal VPmay be explained as follows, also with reference to the exemplary signals ofFIG. 5.

As a result of the output digital signal VCOMPat node400being high, the charge pump circuit block402may inject a (small) current ICP, e.g. 1 μA, into the node414to charge the ripple filter circuit block406. The ripple filter circuit block406may be dimensioned (e.g., by choosing the values of the resistive and capacitive components RRF, CRF, CCOMPtherein) in such a way that the signal VMincreases and passes above the threshold value VPin a clock period due to the current ICPflowing from node414to ground. Therefore, at a successive rising edge of the clock signal CLK_LTE, the signal VMmay be higher than VPand the output digital signal VCOMPof the comparator408may change its status (i.e., may commute to low).

As a result of the output digital signal VCOMPof the comparator408being low, the charge pump circuit block402may sink a current ICPfrom node414to discharge the ripple filter circuit block406, thus resulting in the signal VMdecreasing and passing below the threshold value VPin a clock period. Thus, at a successive rising edge of the clock signal CLK_LTE, the signal VMmay be lower than VPand the output digital signal VCOMPof the comparator408may change its status again (i.e., may commute to high).

Therefore, in one or more embodiments, dimensioning of the ripple filter circuit block406may result in the clocked comparator408having its input differential signal (e.g., VP−VM) changing sign at each clock cycle of the clock signal CLK_LTE as a result of the comparator1operating in steady-state condition (i.e., without output load variations).

Therefore, a continuous oscillation with a hysteretic behavior may be generated in the control loop of the sensing portion40providing the control signal CPCMD, and the output digital signal VCOMPof the comparator408may oscillate with an average duty cycle of approximately 50% at a frequency which is half of the clock frequency CLK_LTE (see, e.g., signals VP, VM, VCOMP, CLK_LTE inFIG. 5).

As a result of the signal VOUTvarying, the steady-state condition of the converter1is not valid anymore. In one or more embodiments as exemplified inFIG. 6, as a result of the signal VOUTvarying, the average duty-cycle of the digital signal VCOMPat the output node400of the sensing portion40may change.

For instance, as exemplified inFIG. 6, the signal VOUTdecreasing may result in the signal VCOMPhaving a duty-cycle lower than 50%. Similarly, the signal VOUTincreasing may result in the signal VCOMPhaving a duty-cycle higher than 50%.

FIG. 7ais exemplary of possible time behavior of signals VP, VM, VCOMP, CLK_LTE and ICPin one or more embodiments as exemplified inFIG. 6, wherein the possibility of having a delay between the edges of the clock signal CLK_LTE and the commutations of the signal VCOMPat the output of the comparator408is shown. Such delay may be due, for instance, to the propagation delays in the circuit that implements the comparator408. Since the signal VCOMPmay be sampled by the filter portion42at edges of the clock signal CLK_LTE, the response of the system may not be dependent on the comparator delay.

FIG. 7bis exemplary of possible time behavior of signals PH1, PH2, PH3in a 3 phase clocked comparator408in one or more embodiments as exemplified inFIG. 6. The signal PH1enables the first stage of the comparator408(e.g., a differential couple). The signal PH2is enabled after a certain time needed (from analog simulations) to make it switch. At the regime of stage2, the output of the analog comparator is sampled by enabling the signal PH3. When all the phases are low, the comparator keeps the hold status.

Generally, driving schemes of phases PH1, PH2and PH3for a three-phase comparator are known in the art, thus a more detailed description will not be provided herein.

As noted, the charge pump circuit block402may inject or sink a fixed current ICPinto/from node414depending on the value of the command signal CPCMD, which is a replica of the digital signal VCOMP. At steady-state condition, the digital signal VCOMPhas a duty cycle which is approximately 50%; therefore, in a complete period of signal VCOMP, the total charge integrated by the ripple filter circuit block406at node414should ideally be zero, since a current ICP=IBIASis integrated for half period, and a current ICP=−IBIASis integrated for another half period. As a result, the average value of the signal VMshould be ideally constant over time.

As a result of a (small) difference (e.g., ±10%) between the positive and negative value of the current ICPprovided by the charge pump circuit block402, the output digital signal VCOMPof the comparator408may have spurious “double shots”, i.e. the output digital signal VCOMPmay have a duty cycle equal to 0% or 100% for certain periods, depending on the sign of the current error. If such current error in constant over time, the spurious “double shots” may occur periodically, with a certain frequency.

Such “double shots” may thus introduce a subharmonic component in the digital signal VCOMPat the node400, the frequency of the subharmonic component being dependent on the magnitude of the current error.

For instance,FIG. 8is exemplary of an operating condition wherein a current ICP=IBIAS−10% (equivalently, ICP= 9/10·IBIAS) is integrated in the ripple filter circuit block406for half period of the signal VCOMP, and a current ICP=−IBIAS−10% (equivalently, ICP=−11/10·IBIAS) is integrated for another half period of the signal VCOMP. In such condition, a “positive double shot” (i.e., the digital signal VCOMPskipping a 1→0 commutation) is generated in the signal VCOMPevery 10 periods, resulting in a subharmonic component of signal VCOMPhaving a frequency equal to 1/10 of the frequency of signal VCOMP.

Of course, “negative double shot” may occur in case the sign of the current error is the opposite.

Therefore, in order to limit the occurrence of malfunctions of the converter circuit, one or more embodiments may facilitate reducing the magnitude of the error of the current ICP, e.g. providing a maximum current error in the order of ±2% in the worst case scenario.

In one or more embodiments, the comparator408and the charge pump circuit block402may switch at a high frequency, e.g. in less than 1 ns (1 ns=10−9s), by using the current steering topology. In a current steering topology, the switches SW1and SW2may be configured to steer the current on another node (e.g., ground node or power supply node) when switched off. Therefore, the current generator coupled in series with the switches SW (implemented herein, for example, as current mirror) is never switched off and a current can be quickly restored in the switches SW when they are turned on.

Such current steering topology for switches is known in the art (e.g., it is employed in fast digital-to-analog converters), thus a more detailed description will not be provided herein.

In one or more embodiments, the band-pass filter circuit block404may be dimensioned in order to provide a stable signal VPat node412.

For instance, in one or more embodiments, the first pole of the band-pass filter circuit block404may decrease the sensitivity of the additional feedback loop between nodes102and112b, thereby facilitating controlling possible interactions between the main feedback loop of the converter1(comprising the blocks10and12) and the additional feedback loop (comprising block24).

For instance, the first pole of the type-III feedback network (see components R1, R2, R3, C1, C2, C3inFIG. 1) and the lower pole (i.e., the high-pass pole) of the band-pass filter circuit block404may be related and in track, e.g. by using the same resistor and capacitor modules and, possibly, the same trimming procedure (if trimming is performed on those components). The first pole of the type-III feedback network and the lower pole of the band-pass filter circuit block404being “in track” means that the frequency values of such singularities should be subject to the same variations, e.g. the same PVT variations.

In one or more embodiments, the second pole of the band-pass filter circuit block404(i.e., the low-pass pole) may filter the ripple of the signal VOUTreceived at node102and limit the frequency content of the signal VOUT.

Effects of the band-pass filter circuit block404are exemplified inFIG. 9a, which is exemplary of possible time behavior of signals at respective nodes in one or more embodiments, namely:

signal VPat node412, and

In particular, signals VCAP, VESRand VESLare indicative, respectively, of the voltage drops across the capacitive, resistive and inductive components CAP, ESR, ESL of the output capacitor COUT, as exemplified in the capacitor model ofFIG. 9b.

Frequency response of a sensing portion40of a sensing circuit block24in one or more embodiments may be analyzed with reference toFIGS. 10 and 11.

As a result of the sensing portion40operating as a delta modulator, e.g. a 1-bit delta modulator, the duty cycle of the respective output signal VCOMPmay be indicative of the derivative of the respective input signal VOUT. A transfer function from VOUTto VCOMPmay be computed for a simplified circuit (model), exemplified inFIG. 10, of the sensing portion40exemplified inFIG. 6. Such circuit ofFIG. 10may be derived from the complete circuit ofFIG. 6under some simplifying assumptions, namely:

neglecting both capacitors CCOMPcoupled at nodes412and414, respectively, whose main function is to balance the comparator kick-back injection and to reduce the sensitivity to the parasitic components ESL and ESR at the output node102; the singularities (e.g., poles in the transfer function) due to the parasitic components ESL and ESR are located at frequencies higher than the upper limit of the LTE loop bandwidth, which is a function of the comparator clock frequency CLK_LTE;

neglecting the filter circuit block600between nodes422and410, whose main function is to reduce the coupling between the signal VOUTand the bias current IBIASprovided by the charge pump circuit block402; and

considering node410coupled to the reference (ground) node GND, which is a DC bias condition but has no impact on the computation of the frequency transfer function.

Under the above mentioned assumptions, the simplified circuit (model) exemplified inFIG. 10may be obtained, and in the closed loop condition also the condition VP=VMmay be considered. Therefore, the following transfer function may be computed:

wherein the first factor is due to the band-pass filter circuit block404, and the second and third factors are due to the delta modulator behavior of the clocked comparator408cooperating with the charge pump circuit block402.

A diagram of the transfer function from VOUTto VCOMPunder the above mentioned simplifying assumptions is exemplified in Figure ii. The transfer function has two zeros approximately located at ƒ=0, and three poles whose values may be approximately computed according to the following equations:

Therefore, the frequencies of the poles in the transfer function may also comply with the following conditions:

wherein FSWis the switching frequency of the signal VSWat node110.

In one or more embodiments, the frequency of pole Fp2may be tuned by changing the value of the capacitor CRF, thus allowing for the frequency of pole Fp2for varying in a range ΔFp2.

In one or more embodiments, the maximum value GMAXof the transfer function from VOUTto VCOMPmay be obtained between the second and third poles, and may be computed according to the following equation:

In one or more embodiments, the additional feedback loop (e.g., the sensing circuit block24) may be almost insensitive to variations of the output signal VOUTat frequencies below the first pole Fp1, e.g. frequencies below the first pole of the type-III feedback network. In fact, such frequencies may be rather low and the main feedback loop comprising the feedback circuit block10may be able to react on such slow variations, e.g. due to slow load transients.

In one or more embodiments, the additional feedback loop (e.g., the sensing circuit block24) may have a derivative behavior at frequencies between the first pole Fp1and the second pole Fp2. The additional feedback loop may be sensitive to variations of the output signal VOUTand proportional to the derivative of such variations of the output signal VOUT.

In one or more embodiments, by tuning the frequency Fp1in order to be approximately equal to the first pole of the type-III feedback network, the bandwidth of the additional feedback loop may be extended up to the switching frequency FSW.

In one or more embodiments, the additional feedback loop (e.g., the sensing circuit block24) may saturate at a maximum value GMAX, which may be related to the noise performance of the sensing portion40.

In one or more embodiments, since the value of RHPmay be fixed, the ratio GMAX/Fp2may be constant and the sensitivity of the additional feedback loop (i.e., the frequency of the second pole Fp2) may be tuned by varying the value of the capacitor CRF.

In one or more embodiments, the frequency of the first pole Fp1may be fixed and possibly equal to the frequency of the first pole of the type-III feedback network in the feedback circuit block10.

It is noted that the analog sensing portion40of the sensing circuit block24in the additional feedback loop, comprising the filter blocks404,406and600, the latched (or clocked) comparator408and the charge pump circuit block402, may operate as a delta modulator. In one or more embodiments, the duty cycle of the signal VCOMPgenerated by the sensing portion40may thus carry information about variations, in the time order of 1/(10·Fp1) (due to the band-pass filter circuit block404), of the (filtered) output signal VOUTfrom the comparator1.

One or more embodiments aim at improving the response of the converter1to changes of the load16coupled thereto. For instance, as a result of the output current ILincreasing due to a load change, the output signal VOUTmay change and the sensing portion40may react on the derivative of the output signal VOUT. Such reaction may result in a local change of the duty cycle of the signal VCOMPprovided at the output of the sensing portion40to the filter portion42, with such change of the duty cycle of the signal VCOMPtriggering some actions in the converter1in order to react on the load change.

It is noted that, in one or more embodiments, the information carried by the duty cycle of the signal VCOMPmay be affected by non-idealities of the sensing portion40, for instance:

non-uniform charge transfer between the charging and discharging phases of the ripple filter circuit block406(e.g., due to different clock periods and/or different current values provided by the charge pump circuit block402, as previously noted), and/or

presence of an offset error in the comparator circuit block408.

In one or more embodiments, the information carried by the duty cycle of the signal VCOMPmay be used to reconstruct for a limited time window the shape of the output signal VOUT, thereby facilitating reacting on the variations of the output signal VOUTof the comparator1.

For instance, low-pass filtering may facilitate reducing the degree of the derivative applied to the output signal VOUT, thus providing locally the shape of the output signal VOUT.

Therefore, in one or more embodiments, filtering of the output signal VCOMPprovided at the output node400of the sensing portion40may be beneficial for:

reducing the effect of non-idealities of the analog sensing portion40;

reconstructing locally (i.e., for a limited time window) the shape of the output signal VOUTat node102for reacting to load transients; and

providing a programmable sensitivity of the additional feedback loop to load transients.

Such filtering of the output signal VCOMPmay be carried out by means of both analog and digital circuits. Otherwise, it is noted that digital filtering of the information digitally encoded via the delta modulator behavior of the sensing portion40may result in higher noise immunity, if compared to analog filtering. Digital filtering may also result in easier tuning of the filter characteristics (e.g., defining precise thresholds).

In one or more embodiments, since the filtering performed in the sensing portion40may be designed in order to react to high frequency components in the output signal VOUT(e.g., defining a derivative filter as previously noted), the “downstream” filtering performed in the filter portion42may have a low-pass behavior (e.g., defining an integrative filter) which may facilitate reconstructing the shape of the output (voltage) signal VOUT.

In one or more embodiments, the filter portion42may additionally be designed as a low-power circuit.

Therefore, in one or more embodiments, the filter portion42may comprise a moving average filter421, which is configured to receive the signal VCOMPprovided at node400by the sensing portion40, and provide an output filtered signal FOUTat node416. The moving average filter421may facilitate reconstructing the shape of the output (voltage) signal VOUT.

In one or more embodiments, the number of filter samples of the moving average filter may be constrained by a lower value and an upper value. For instance, the lower value may be defined in order to filter out possible spurious pulses of the comparator408due to non-idealities of the analog circuit blocks402,404,406,600. On the other hand, the upper value may be limited in order to have an additional feedback loop fast enough for reacting to fast load changes at the output node102of the converter1.

For instance, in one or more embodiments the delta-encoded information carried by the signal VCOMPmay be filtered by means of a moving average filter421on twelve samples. The transfer function TFDLPof the digital low-pass filter may thus be the following:

It is noted that different topologies may be used for implementing the digital filter421.

For instance,FIG. 12is exemplary of a possible implementation of the moving average filter421with a shift register SR with twelve 1-bit samples, one 2-bits adder, one 4-bits adder and one 4-bits sampler.

FIG. 13is exemplary of another possible implementation of the moving average filter421. The moving average filter421exemplified inFIG. 13comprises two shift registers SR1, SR2and one 4-bits adder. Each of the shift registers SR1, SR2may have half the length of the shift register SR exemplified inFIG. 12, and the two registers SR1, SR2may be configured to store alternatively a current value of the digital signal VCOMPat half the frequency of the delta-encoded signal VCOMP.

It is noted that the implementation of the moving average filter421exemplified inFIG. 13may be advantageous in reducing power consumption at steady state (charging the transfer function TFDLPof a further sampling period). In fact, since the delta-encoded signal VCOMPnormally has a duty cycle of 50% at steady state, one of the two shift registers SR1, SR2(e.g., SR1) would store 0s only, and the other of the two shift registers SR1, SR2(e.g., SR2) would store 1s only, thereby reducing the power consumption of both chains of registers since the outputs of the memory elements do not change, i.e. commutation of the memory elements is avoided in steady-state conditions.

In one or more embodiments, the output signal FOUTof the moving average filter421may be compared with two threshold values VTHand VTLat respective comparators417and419.

The output signal FOUTmay be compared to a first threshold VTHin a first comparator with hysteresis417, thereby generating a first output digital signal LTE_SKIP at a node418. The signal LTE_SKIP may be set to high as a result of the signal FOUTincreasing to the threshold VTHand set to low as a result of the signal FOUTreturning to its average value (i.e., when the converter operates at steady state and signal VCOMPhas duty cycle of 50%).

The output signal FOUTmay be compared to a second threshold VTLin a second comparator with hysteresis419, thereby generating a second output digital signal LTE_TRIG at a node420. The signal LTE_TRIG may be set to high as a result of the signal FOUTdecreasing to the threshold VTLand set to low as a result of the signal FOUTincreasing to the threshold VTH. Additionally, the signal LTE_TRIG may be set to high only if the output signal VOUTis lower than the reference voltage VREFat node100.

Therefore, the output digital signals LTE_TRIG and LTE_SKIP may be provided by the sensing circuit block24to the control circuit block22to trigger or skip, respectively, a pulse in the signal PWMdprovided at node112bfor driving the switching stage14.

In fact, in one or more embodiments, the digital signal LTE_TRIG may commute to high, e.g. in case of an increase of the output load, with such commutation to high resulting in the signal PWMdbeing forced to high in order to provide charge to the output capacitance COUT.

Similarly, in one or more embodiments, the digital signal LTE_SKIP may commute to high, e.g. in case of a release (decrease) of the output load, with such commutation to high resulting in the signal PWMdbeing forced to low in order to inhibit switching activity of the switching stage14.

Triggering additional pulses of the signal PWMdby means of the signal LTE_TRIG through the control block22may be a time-relevant issue. Thus, in one or more embodiments, the signal path from node420to node112b(i.e., the signal path allowing the propagation of signal LTE_TRIG which affects the signal PWMd) may comprise combinational logic circuits (only).

Skipping unwanted pulses of the signal PWMdby means of the signal LTE_SKIP through the control block22may involve accurate operation. For instance, skipping PWMdpulses should not be performed when the output signal VOUTis lower than the reference signal VREF. Thus, in order to avoid the masking of only unnecessary charging pulses, and thus stopping the switching functionality of the switching stage14when not needed, a clocked logic with FSM (Finite State Machine) may be used instead of involving combinatorial logic (only).

In one or more embodiments, digital filtering operated by the filter portion42may also facilitate masking the output of the additional feedback loop when the related effects on the output signal VOUTare not predictable.

For instance, operation of the additional feedback loop (e.g., operation of the sensing circuit block24and the control circuit block22) may be disabled by means of a timing mask, implemented through the digital filter portion42, during the start-up phase of the converter1, before the converter reaches a steady-state condition.

In one or more embodiments, signals LTE_TRIG and LTE_SKIP are provided by the sensing circuit block24to the control circuit block22. The control circuit block22may be configured to generate a drive signal PWMdfor driving the switching stage14, with the drive signal PWMdbeing generated as a function of a combination of information retrieved from the PWM-modulated control signal PWMcat the output112aof the main feedback loop10,12and signals LTE_TRIG and LTE_SKIP.

In particular, in one or more embodiments, the drive signal PWMdis generated by propagating the PWM-modulated control signal PWMcfrom node112ato node112b, and “overriding” high values, resp. low values, of such propagated signal with low values, resp. high values, as a result of the digital signal LTE_SKIP, resp. LTE_TRIG, being high (or, in general, being asserted).

In one or more embodiments, the signal LTE_SKIP may act inhibiting the transfer of charge from the inductor LOUTto the output node102possibly required by the main feedback loop. For instance, an AND logic gate may be placed along the generation path of the on-time trigger signal, the AND logic gate having one input configured to receive a complemented replica of the signal LTE_SKIP (see, for instance,FIG. 14).

In one or more embodiments, a rather sophisticated (combinational) elaboration of signal LTE_TRIG may be performed in the control circuit block22. For instance, such elaboration may aim at reducing the occurrence of spurious subharmonic components in the output signal VOUT, which may be due to a possible systematic intervention of the additional feedback loop (as previously described with reference toFIG. 8).

FIG. 14is exemplary of a possible implementation of a control circuit block22for use in one or more embodiments, according to the operation logic described previously.

InFIG. 14, in addition to logic gates known per se such as AND, OR, and NOT logic gates, the following blocks may be identified:

C: combinational blocks having two inputs A and B and one output Z, realizing the following logic function:

Examples of operation of one or more embodiments according to the architecture exemplified inFIG. 14are reported here below:

a) LTE_TRIG started and finished during a TOFFtime, approximately at the middle of a switching period→TONend pulse is generated and LTE_TRIG=PWM;

b) LTE_TRIG started during a TOFFtime and finished in correspondence to the beginning of a switching period→ the reset pulse is not generated and the PWM signal remains high;

c) LTE_TRIG started during a TONtime→ the reset pulse is not generated and the TONtime is determined by the output of the TONcomparator20;

d) LTE_TRIG started during a TOFFtime and finished in correspondence to the high-to-low transition of the signal CLK_REF→TONend pulse is generated and LTE_TRIG=PWM;

e) Positive Over Current (OCP_POS) event when LTE_TRIG=1→TONtime stopped and PWMdreset.

The signal OCP_POS may be indicative of a positive over-current event. As a result of such signal indicating an over-current, an over-current protection may be triggered by resetting the signal PWMdfor a certain time interval. Such operation has priority over the functionality of the LTE loop, since it provides a protection against possible damages to the circuit.

It is noted that other possible operating conditions may occur in the control circuit block22according to different possible values of signals LTE_TRIG, LTE_SKIP and others.

One or more embodiments may thus provide the advantages of both fixed-frequency and standard constant on-time (COT) converter architectures, e.g. high immunity to noise and good output dynamic performance.

One or more embodiments may provide improved performance in case of rapid load step with respect to conventional fixed-frequency converters while keeping under control the switching phase of the converter, e.g. allowing a disoverlapping and/or phase shift in presence of different points of load.

One or more embodiments may be advantageous in limiting power consumption.

One or more embodiments may allow using the same circuitry to improve the response of the system even in case of fast load current release.

One or more embodiments may facilitate modulating the entity of the correction to the PWM-modulated signal PWMcby means of the additional feedback loop as a function of the amplitude and slope of load transients steps, thereby reducing the risk of large undershoot and overshoot if any of the converter signals is changed (e.g., input voltage VINand output signal VOUT).

One or more embodiments may facilitate reducing intrinsic converter inaccuracies by operating a digital moving average filtering on the output of the comparator408, thus providing improved sensitivity with reduced risk of spurious interventions and anomalous behavior at constant output load (i.e., at steady state).

One or more embodiments may be almost insensitive to the shape of the output ripple thanks to a filtering operation provided by the analog sensing portion.

One or more embodiments may not need external components, with the whole circuit being possibly fully integrated on silicon.

One or more embodiments may thus relate to a converter circuit (e.g.,1), comprising:

an input node (e.g.,106) configured to receive an input signal (e.g., VIN) and an output node (e.g.,102) configured to provide a converted output signal (e.g., VOUT) to a load (e.g.,16);

a switching power stage (e.g.,14) configured to receive the input signal and an on-off drive signal (e.g., PWMd) switching between an on-state and an off-state, the switching power stage configured to provide at a respective output node (e.g.,110) a switching power signal (e.g., VSW);

a reactive output network (e.g., LOUT, COUT) between the respective output node of the switching power stage and the output node, the reactive output network configured to provide the converted output signal to the load,

wherein the circuit may comprise:

i) a first feedback signal path (e.g.,10,12) comprising:a comparator circuit (e.g.,10) configured to compare the converted output signal at the output node with a reference signal (e.g., VREF) and to generate an error signal (e.g., VERR) at a respective output node (e.g.,104), anda PWM generator circuit (e.g.,12) configured to receive at a respective input node (e.g.,120) a ramp signal (e.g., VRAMP) at a first frequency (e.g., CLK_REF), the PWM generator circuit coupled to the comparator circuit to receive the error signal therefrom and configured to generate a PWM-modulated control signal (e.g., PWMc) having the first frequency, the PWM-modulated control signal having respective on- and off-times which are a function of the error signal;

ii) a second feedback signal path comprising an output variation sensing circuit block (e.g.,24) configured to sense the converted output signal at the output node and to generate at least one output variation signal (e.g., LTE_TRIG, LTE_SKIP) indicative of variations of the converted output signal over time,

wherein the circuit may comprise a controller circuit block (e.g.,22) coupled to the PWM generator circuit in the first feedback signal path and to the output variation sensing circuit block in the second feedback signal path, wherein the controller circuit block is sensitive to the PWM-modulated control signal and the at least one output variation signal, the controller circuit block configured to generate the on-off drive signal for the switching power stage from the PWM-modulated control signal by increasing resp. decreasing the time the on-off drive signal is in the on-state as a result of the converted output signal decreasing resp. increasing.

As exemplified inFIG. 5, increasing the (overall or cumulative) time over which the on-off drive signal PWMdis in the on-state as a result of a decrease sensed in the output signal VOUTmay involve forcing the drive signal PWMdto the on-state by “inserting” a pulse between subsequent pulses in the sequence of pulses in the drive signal PWMd.

In one or more embodiments, increasing the (overall) time over which the on-off drive signal PWMdis in the on-state may be effected in other ways such as, for instance:

increasing the duration of the on-times of the pulses in the sequence of pulses in the drive signal PWMd, and/or

reducing the distance between adjacent pulses in the sequence.

Similarly, decreasing the (overall or cumulative) time over which the on-off drive signal PWMdis in the off-state may be effected in various ways such as, for instance:

“deleting” at least a portion of a pulse between subsequent pulses in the sequence of pulses in the drive signal PWMd; it will be appreciated that such deleting may involve a pulse as a whole or just “slicing” the pulse by forcing to the off-state an end or intermediate portion of the pulse, and/or

reducing the duration of the on-times of the pulses in the sequence of pulses in the drive signal PWMd, and/or

increasing the distance between adjacent pulses in the sequence.

In one or more embodiments, the at least one output variation signal may comprise:

a first output variation signal (e.g., LTE_TRIG) indicative of the converted output signal decreasing, and

a second output variation signal (e.g., LTE_SKIP) indicative of the converted output signal increasing.

In one or more embodiments, the controller circuit block is configured to generate the on-off drive signal for the switching power stage by:

propagating to the switching power stage the PWM-modulated control signal received from the PWM generator circuit, and

i) forcing the on-off drive signal for the switching power stage to the on-state as a result of the first output variation signal being indicative of the converted output signal decreasing;

ii) forcing the on-off drive signal for the switching power stage to the off-state as a result of the second output variation signal being indicative of the converted output signal increasing.

In one or more embodiments, the output variation sensing circuit block may comprise:

a sensing portion (e.g.,40) configured to sense the converted output signal at the output node by applying a delta modulation to the converted output signal at a second frequency (e.g., CLK_LTE), thereby generating a respective output digital signal (e.g., VCOMP) having a duty cycle which is a function of variations of the converted output signal over time; and

a filter portion (e.g.,42) configured to:

receive the output digital signal from the sensing portion and apply low-pass filtering to the output digital signal, thereby generating a respective output filtered signal (e.g., FOUT), and

compare the output filtered signal to at least one threshold value to generate the at least one output variation signal.

In one or more embodiments, the second frequency may be higher than the first frequency (CLK_REF), preferably at least one order of magnitude higher (i.e., at least 10 times higher) than the first frequency (CLK_REF).

In one or more embodiments, the filter portion may comprise a moving average digital filter (e.g.,421) configured to apply low-pass filtering to the output digital signal, thereby generating the respective output filtered signal.

In one or more embodiments, the moving average digital filter may comprise two shift registers (e.g., SR1, SR2) configured to alternatively store a current value of the output digital signal, with each of the two shift registers being operated at a frequency which is half of the second frequency.

In one or more embodiments, the sensing portion may comprise:

a band-pass filter circuit block (e.g.,404) configured to filter the converted output signal sensed at the output node and generate an intermediate filtered signal (e.g., VP) indicative of the value of the converted output signal;

a charge pump circuit block (e.g.,402) configured to inject or sink a certain current (e.g., ICP) into/from a respective filter circuit block (e.g.,406), thereby generating an oscillating signal (e.g., VM) at a respective output node (e.g.,414) of the respective filter circuit block; and

a clocked comparator (e.g.,408) configured to compare the intermediate filtered signal to the oscillating signal at the second frequency, thereby generating the respective output digital signal.

One or more embodiments may comprise a converter compensation network (e.g., R1, R2, R3, C1, C2, C3), preferably a type-III compensation network, the compensation network providing at least one compensating pole of the transfer function of the converter at a certain frequency, wherein the band-pass filter circuit block has a transfer function with a respective pole at said certain frequency of said at least one compensating pole.

In one or more embodiments, the controller circuit block may comprise a combinational logic circuit configured to force the on-off drive signal to the on-state as a result of the first output variation signal being indicative of the converted output signal decreasing.

In one or more embodiments, the controller circuit block may be configured to increase the time the on-off drive signal is in the on-state as a result of the converted output signal decreasing and the converted output signal being lower than the reference signal.

In one or more embodiments, an electronic component may comprise a plurality of circuits according to one or more embodiments, the circuits in the plurality of circuits being configured to receive an input signal at respective input nodes and provide respective output signals at respective output nodes.

In one or more embodiments, a device may comprise at least one circuit according to one or more embodiments and a load coupled to the output node in the at least one circuit to receive a converted output signal therefrom.

In one or more embodiments, the electronic component may comprise a plurality of circuits according to one or more embodiments, wherein the circuits in the plurality of circuits have respective output nodes coupled to different points of load to provide respective converted output signals to the different points of load.

In one or more embodiments, a method of operating a circuit according to one or more embodiments may comprise:

applying an input signal to the input node,

coupling a load or loads to the output node or nodes.

The extent of protection is defined by the annexed claims.