Devices including stacked nanosheet transistors

Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

FIELD

The present disclosure generally relates to the field of semiconductor devices and, more particularly, to nanosheet transistor devices.

BACKGROUND

The density of transistors in electronic devices has continued to increase. Though three-dimensional transistor structures can help to increase transistor density, they may experience electrical vulnerabilities, such as parasitic capacitance. For example, parasitic capacitance between a contact metal and a gate metal of a three-dimensional transistor structure can reduce device performance.

SUMMARY

A nanosheet transistor device, according to some embodiments herein, may include a transistor stack that includes a lower tri-gate nanosheet transistor having a first nanosheet width and an upper tri-gate nanosheet transistor on the lower tri-gate nanosheet transistor. The upper tri-gate nanosheet transistor may have a second nanosheet width that is different from the first nanosheet width.

A nanosheet transistor device, according to some embodiments, may include a transistor stack. The transistor stack may include a lower nanosheet transistor having a first nanosheet width and a lower gate width. Moreover, the transistor stack may include an upper nanosheet transistor on the lower nanosheet transistor. The upper nanosheet transistor may have a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively.

A method of forming a nanosheet transistor device, according to some embodiments, may include forming a preliminary transistor stack comprising a first plurality of nanosheets and a second plurality of nanosheets on the first plurality of nanosheets. The method may include forming a recess in the preliminary transistor stack by removing a first portion of the second plurality of nanosheets. The method may include forming a spacer in the recess. Moreover, the spacer may overlap the first plurality of nanosheets and contact a second portion of the second plurality of nanosheets that remains after removing the first portion.

DETAILED DESCRIPTION

Pursuant to embodiments of the present invention, nanosheet transistor devices comprising a transistor stack are provided. A transistor stack includes a lower transistor and an upper transistor that vertically overlaps the lower transistor and that may share a gate electrode with the lower transistor. Though stepped nanosheet (“sNS”) structures, which have different upper and lower nanosheet widths, have been proposed, a gate metal of an sNS structure may have parasitic capacitance with an adjacent contact metal. Specifically, the capacitance may increase with increased width of the gate on the stepped portion of the sNS structure. According to embodiments of the present invention, however, parasitic capacitance between an sNS gate and a source/drain contact can be reduced by removing a portion of the gate electrode material that is closest to the source/drain contact.

Example embodiments of the present invention will be described in greater detail with reference to the attached figures.

FIG.1Ais a plan view of a nanosheet transistor device100according to some embodiments of the present invention. The device100includes first and second transistor stacks110-1,110-2. For simplicity of illustration, only two transistor stacks110are shown inFIG.1A.

In some embodiments, however, the device100may include three, four, or more transistor stacks110. For example, the two transistor stacks110-1,110-2may be a pair of transistor stacks110that are closer to each other than to any other transistor stack110in the device100.

The first transistor stack110-1includes a first nanosheet stack120-1that is between a pair of source/drain regions150-1in a first horizontal direction X. The first nanosheet stack120-1includes nanosheets NS (FIG.1B) and a gate G (FIG.1B) that is on the nanosheets NS.

Though the nanosheets NS may contact the source/drain regions150-1, the gate G may be spaced apart from the source drain regions150-1in the direction X.

A source/drain contact140-1, which may comprise metal, is adjacent one of the source/drain regions150-1in a second horizontal direction Y, which may be perpendicular to the direction X. For example, the source/drain contact140-1may be a drain contact.

To reduce parasitic capacitance with the source/drain contact140-1, a region RG-1of the nanosheet stack120-1that is adjacent (e.g., aligned/overlapping in the direction X with) the source/drain contact140-1may be free of a gate electrode material (e.g., metal). The region RG-1may also reduce parasitic capacitance with both source/drain regions150-1. Likewise, a second nanosheet stack120-2of the second transistor stack110-2is between a pair of source/drain regions150-2and has a gate-free region RG-2that is adjacent a source/drain contact140-2.

FIG.1Bis a cross-sectional view, taken along the direction Y, of the first and second nanosheet stacks120-1,120-2ofFIG.1A. As shown inFIG.1B, each nanosheet stack120includes a plurality of lower nanosheets NS-L of a lower transistor TG-L and a plurality of upper nanosheets NS-U of an upper transistor TG-U. The upper nanosheets NS-U overlap the lower nanosheets NS-L in a vertical direction Z that is perpendicular to the horizontal directions X and Y.

The lower transistor TG-L further includes a lower gate G-L that is on the lower nanosheets NS-L. In the cross-sectional view ofFIG.1B, the lower gate G-L is shown on three sides of each of the lower nanosheets NS-L. The upper transistor TG-U likewise further includes an upper gate G-U that is on three sides of each of the upper nanosheets NS-U in the cross-sectional view ofFIG.1B. Accordingly, the transistors TG-L, TG-U shown inFIG.1Bare each tri-gate nanosheet transistors. In some embodiments, the gates G-L, G-U may be provided by a continuous gate electrode that is shared by the tri-gate transistors TG-L, TG-U. Moreover, each transistor stack110(FIG.1A) may, in some embodiments, be a complementary field-effect transistor (“CFET”) stack in which the lower tri-gate transistor TG-L and the upper tri-gate transistor TG-U are N-type and P-type transistors, respectively, or vice versa. Furthermore, though tri-gate transistors TG-L, TG-U are shown inFIG.1B, other types of transistors, such as gate-all-around (“GAA”) transistors (FIGS.1E,1F,2B), may include nanosheets NS.

The lower gate G-L has opposite sidewalls S1, S2, and the upper gate G-U has opposite sidewalls S3, S4. The gate-free region RG is adjacent the sidewall S4and vertically overlaps the lower gate G-L and the lower nanosheets NS-L. In some embodiments, the gate-free region RG may also be adjacent the sidewall S2. As shown inFIGS.1A and1B, the nanosheet stacks120-1,120-2are mirror symmetrical, in that the gate-free regions RG-1, RG-2face away from each other along the direction Y, as do the source/drain contacts140-1,140-2. The mirror symmetry thus increases a distance between the source/drain contacts140-1,140-2.

Moreover, the upper nanosheets NS-U may, in some embodiments, provide a fork sheet that extends in the direction Y toward the sidewall S3, where the sidewall S3of the upper gate G-U of the first transistor stack110-1is opposite (i.e., faces) the sidewall S3of the upper gate G-U of the second transistor stack110-2. As a result, the upper nanosheets NS-U of the upper tri-gate transistor TG-U of the first transistor stack110-1and the upper nanosheets NS-U of the upper tri-gate transistor TG-U of the second transistor stack110-2have opposite fork-sheet directions from each other. As shown inFIG.1B, upper nanosheets NS-U may have the same fork-sheet direction as lower nanosheets NS-L that are thereunder in a transistor stack110. In other embodiments, however, upper nanosheets NS-U of a transistor stack110may have an opposite fork-sheet direction from that of lower nanosheets NS-L that are in the transistor stack110, as described herein with respect toFIG.1D.

FIG.1Cis an enlarged view of the second nanosheet stack120-2ofFIG.1B. As shown inFIG.1C, the gate-free region RG may comprise an insulation region160that is on an upper surface US of the lower gate G-L and the sidewall S4of the upper gate G-U. Moreover, the insulation region160may contact respective sidewalls of the upper nanosheets NS-U and may vertically overlap the lower nanosheets NS-L. The insulation region160may comprise, for example, silicon nitride or silicon oxide. In some embodiments, the insulation region160may comprise a low-k spacer, which can provide better capacitance-reduction than a higher-k insulator. As used herein, the term “low-k” refers to a material that has a smaller dielectric constant than silicon dioxide.

FIG.1Calso illustrates that the upper nanosheets NS-U each have a width WN-U that is different from a width WN-L of each of the lower nanosheets NS-L. The nanosheet stack120-2is thus an sNS structure. Example sNS structures are discussed in U.S. Provisional Patent Application Ser. No. 63/086,781, filed on Oct. 2, 2020, the disclosure of which is hereby incorporated herein in its entirety by reference. Specifically, the width WN-U is narrower than the width WN-L. Moreover, due to the gate-free region RG, a width WG-U of the upper gate G-U is narrower than a width WG-L of the lower gate G-L. The narrower width WG-U can reduce parasitic capacitance between the upper gate G-U and a source/drain contact140(FIG.1A), as well as parasitic capacitance between the upper gate G-U and source/drain regions150(FIG.1A).

Due to its wider gate width WG-L and wider nanosheet width WN-L, the lower tri-gate transistor TG-L can have fewer (e.g., two versus three) nanosheets than the upper tri-gate transistor TG-U, while still having the same total nanosheet cross-sectional area (and/or the same total nanosheet surface area) as the upper tri-gate transistor TG-U. In some embodiments, as shown inFIG.1C, the sidewall S3of the upper gate G-U may be aligned with the sidewall S1of the lower gate G-L. The sidewall S4, however, of the upper gate G-U may vertically overlap the lower nanosheets NS-L, given the narrower width WG-U of the upper gate G-U.

Moreover, because the transistors TG-L, TG-U are tri-gate transistors, the lower nanosheets NS-L are spaced apart from the sidewall S1by a material (e.g., metal) of the lower gate G-L and the upper nanosheets NS-U are spaced apart from the sidewall S3by a material (e.g., metal) of the upper gate G-U. For example, a first distance in the direction Y between the sidewall S1and the lower nanosheets NS-L may be calculated by subtracting the width WN-L from the width WG-L. Likewise, a second distance in the direction Y between the sidewall S3and the upper nanosheets NS-U may be calculated by subtracting the width WN-U from the width WG-U. In some embodiments, the first distance may equal the second distance, such as when the nanosheet stack120is formed according to the operations that are shown inFIGS.3A-3N.

For simplicity of illustration, a gate insulation layer is omitted from view inFIG.1C. It will be understood, however, that a gate insulation layer may extend between each nanosheet NS and the gate G. Also, for simplicity of illustration, a substrate is omitted from view inFIG.1C. It will be understood, however, that the nanosheets NS may be vertically stacked on a substrate. Specifically, the lower tri-gate transistor TG-L may be between the upper tri-gate transistor TG-U and the substrate.

FIGS.1D-1Fare cross-sectional views of nanosheet stacks120′,120″, and120′″, respectively, according to other embodiments of the present invention. As shown inFIG.1D, the sidewall S3of the upper gate G-U may be offset from, rather than vertically aligned with, the sidewall S1of the lower gate G-L. For example, the lower nanosheets NS-L may be spaced apart from the sidewall S2, rather than the sidewall S1, by a material of the lower gate G-L such that the lower nanosheets NS-L have a fork-sheet direction that is opposite a fork-sheet direction of the upper nanosheets NS-U.

A transistor stack110(FIG.1A) is not limited to tri-gate transistors. Rather, the transistor stack110may include both a tri-gate transistor and a GAA transistor.

For example, referring toFIG.1E, the lower nanosheets NS-L may be surrounded by a gate G-L′ of a GAA transistor GA-L. A tri-gate transistor TG-U is stacked above the GAA transistor GA-L. As another example, referring toFIG.1F, the upper nanosheets NS-U may be part of a GAA transistor GA-U that is stacked above a tri-gate transistor TG-L.

Though the gate G-U′ of the GAA transistor GA-U is shown inFIG.1Fas having a similar width in the direction Y as a gate of the tri-gate transistor TG-L, the gate G-U′ may, in some embodiments, have a narrower width due to a gate-free region RG of the GAA transistor GA-U. For example, the GAA transistor GA-U may have a wider gate-free region RG than the tri-gate transistor TG-L, or the tri-gate transistor TG-L may not have a gate-free region RG that is vertically overlapped by the gate-free region RG of the GAA transistor GA-U. Moreover, for simplicity of illustration, the insulation region160(FIG.1C) is omitted from view inFIGS.1D-1F. A gate-free region RG in any ofFIGS.1D-1F, however, may comprise the insulation region160therein. Also, a gate-free region RG may be in any of (i) a lower transistor, (ii) an upper transistor, or (iii) both the upper transistor and the lower transistor of a transistor stack110(FIG.1A).

FIG.2Ais a plan view of a nanosheet transistor device200according to further embodiments of the present invention. The device200comprises a transistor stack that includes a nanosheet stack220that is between, in the direction X, source/drain regions150. To reduce parasitic capacitance with a source/drain contact140(and with the source/drain regions150), the nanosheet stack220includes an insulation region260. The insulation region260may comprise, for example, a low-k spacer. As an example, the insulation region260may be a lower-k region than another insulation region280(FIG.2B) that is on the gate G. For simplicity of illustration, only one nanosheet stack220is shown in the device200. In some embodiments, however, the device200may include two, three, four, or more nanosheet stacks220.

FIG.2Bis a cross-sectional view, taken along the direction Y, of the nanosheet stack220ofFIG.2A. As shown inFIG.2B, the nanosheet stack220includes a plurality of lower nanosheets NS-L that are vertically overlapped by a plurality of upper nanosheets NS-U, and further includes a gate G that is shared by the nanosheets NS-L, NS-U. Unlike the nanosheet stacks120(FIG.1B) of tri-gate transistors TG (FIG.1B), the nanosheets NS-L, NS-U of the nanosheet stack220are all surrounded by the gate G (e.g., by a metal gate electrode). The nanosheets NS-L, NS-U of the nanosheet stack220are thus nanosheets of a lower GAA transistor GA-L and an upper GAA transistor GA-U, respectively. Accordingly, each vertically-stacked transistor of the device200(FIG.2A) may be a GAA transistor GA. Moreover, each stack of two transistors in the device200may, in some embodiments, be a CFET stack in which the lower GAA transistor GA-L and the upper GAA transistor GA-U are N-type and P-type transistors, respectively, or vice versa.

The insulation region260may contact a sidewall of the gate G of the upper GAA transistor GA-U, and may be between the sidewall of the gate G and the insulation region280. The insulation region280may contact an opposite sidewall of the gate G of the upper GAA transistor GA-U, and may be on an upper surface of the gate G of the upper GAA transistor GA-U. Moreover, the insulation region260may be on an upper surface of the gate G of the lower GAA transistor GA-L, and may vertically overlap the lower nanosheets NS-L.

As is further shown inFIG.2B, the nanosheets NS are vertically stacked on an upper surface of a vertically-protruding portion of a substrate290, and device isolation regions295are on opposite sides of the vertically-protruding portion. The lower GAA transistor GA-L may be between the upper GAA transistor GA-U and the substrate290, which may be, for example, a semiconductor substrate.FIG.2Balso illustrates that an insulation region281may be between the lower nanosheets NS-L and the upper surface of the vertically-protruding portion of the substrate290, and that an insulation region282may be between the upper nanosheets NS-U and the lower nanosheets NS-L. In some embodiments, however, the insulation regions281,282may be omitted. Moreover,FIG.2Billustrates a gate insulation layer270, which may extend between each nanosheet NS and the gate G.

FIGS.3A-3Nare cross-sectional views illustrating operations of forming the nanosheet stack120ofFIG.1C. Referring toFIG.3A, a sacrificial material310may be between vertically-stacked preliminary nanosheets NS-P, which may have equal widths in the direction Y. The sacrificial material310may comprise, for example, a semiconductor material, such as silicon germanium, and the preliminary nanosheets NS-P may each be, for example, a silicon sheet. The sacrificial material310and the preliminary nanosheets NS-P may collectively be referred to herein as a “preliminary transistor stack.”

An insulating material320may be on the preliminary nanosheets NS-P and the sacrificial material310. As an example, the insulating material320may be an oxide or nitride, such as silicon oxide or silicon nitride. The insulating material320may serve as an etch mask (e.g., a hard mask) that protects the preliminary nanosheets NS-P and the sacrificial material310.

Referring toFIG.3B, an insulating material330having an etch selectivity with respect to the insulating material320is formed on the insulating material320. For example, the insulating material330may be silicon oxide if the insulating material320is silicon nitride, and the insulating material330may be silicon nitride if the insulating material320is silicon oxide. As shown inFIG.3B, the insulating material330exposes a portion of an upper surface of the insulating material320.

Referring toFIG.3C, the exposed portion of the insulating material320(FIG.3B) is removed, along with underlying portions of the preliminary nanosheets NS-P (FIG.3A) and the sacrificial material310(FIG.3A), to form a recess region301. For example, the insulating material330(FIG.3B) may be used as an etch mask (e.g., a hard mask) while etching the exposed portion of the insulating material320.

Referring toFIG.3D, a spacer340is formed in the recess region301(FIG.3C) and on sidewalls of the sacrificial material310, the preliminary nanosheets NS-P, and the insulating materials320,330(FIGS.3A and3B). The spacer340may comprise, for example, an oxide, such as silicon oxide.

Referring toFIG.3E, a portion of the spacer340that protrudes in the direction Y may be removed to form a recess region302that exposes an upper surface and a sidewall of the sacrificial material310.

Referring toFIG.3F, an insulating material350is formed in the recess region302(FIG.3E) and on a sidewall of the spacer340. The insulating material350has an etch selectivity with respect to the spacer340. For example, the insulating material350comprises an oxide if the spacer340comprises a nitride, and the insulating material350comprises a nitride if the spacer340comprises an oxide. As an example, the insulating material350may comprise silicon nitride.

Referring toFIG.3G, the insulating material330(FIG.3B) is removed to form a recess region303that exposes an upper surface of the remaining portion of the insulating material320and a portion of a sidewall of the spacer340.

Referring toFIG.3H, the insulating material320(FIG.3G) is removed (e.g., by using a selective etching process) to form a recess region304that exposes an upper surface of the sacrificial material310and a portion of a sidewall of the spacer340. Also, an insulating material360is formed (e.g., deposited) on the sidewall of the spacer340. The insulating material360and the spacer340may comprise the same material (e.g., silicon oxide or silicon nitride).

Referring toFIG.3I, a portion of an upper surface of the sacrificial material310that remains exposed after forming the insulating material360is removed, along with an underlying portion of the three uppermost nanosheets NS of the preliminary nanosheets NS-P (FIG.3A) to a point about midway between the upper nanosheet stack and the lower nanosheet stack. As a result, the three uppermost nanosheets NS are narrower, in the direction Y, than the two lowermost nanosheets NS. Moreover, this removal forms a recess region305that exposes sidewalls of the three uppermost nanosheets NS and exposes an upper surface of the sacrificial material310that vertically overlaps the two lowermost nanosheets NS.

Referring toFIG.3J, a spacer370is formed (e.g., by depositing another insulating material) on the insulating material360and on the exposed sidewalls of the three uppermost nanosheets NS. The spacer370overlaps the two lowermost nanosheets NS and contacts sidewalls of a portion of the three uppermost nanosheets NS that remains after forming the recess region305. The spacer370may comprise, for example, silicon nitride or silicon oxide, and may have an etch selectivity with respect to the spacer340and the insulating material360.

Referring toFIG.3K, a recess region306is formed by removing an exposed portion of the upper surface of the sacrificial material310, along with underlying portions of the two lowermost nanosheets NS, thus forming two lower nanosheets NS-L. The recess region306exposes sidewalls of the two lower nanosheets NS-L. The nanosheets NS-L are vertically overlapped by the spacer370and by upper nanosheets NS-U, which are the three uppermost nanosheets NS.

Referring toFIG.3L, a planarization process (e.g., chemical mechanical planarization) is performed to remove upper portions of the spacer340, the spacer370, the insulating material360, and the insulating material350. For example, the planarization process may remove tilted surfaces of the spacer370and the insulating material360, and result in upper surfaces of the spacer340, the spacer370, the insulating material360, and the insulating material350that are closer to the nanosheets NS.

Referring toFIG.3M, the portion of the spacer370that remains after the planarization process is removed and is replaced with a spacer380. The spacer380may comprise the same material as the insulating material350, and thus may have an etch selectivity with respect to the spacer340and the insulating material360. For example, the spacer380may comprise silicon nitride. In some embodiments, the spacer380may provide the insulation region160that is shown inFIG.1C.

Referring toFIG.3N, the sacrificial material310(FIG.3M), the spacer340(FIG.3M), and the insulating material360(FIG.3M) are replaced with a gate electrode material390, such as a metal. For example, the spacer340and the insulating material360may be removed and then the sacrificial material310may be removed, or vice versa, and resulting openings in the structure may be filled with the gate electrode material390. As a result, a lower gate G-L of a lower tri-gate transistor TG-L and an upper gate G-U of an upper tri-gate transistor TG-U are formed. The gates G-L, G-U shown inFIG.3Nmay thus each be referred to herein as a “tri-gate.”

FIG.4is a flowchart illustrating operations of forming the nanosheet stack120ofFIG.1C. These operations correspond to those that are shown in the cross-sectional views ofFIGS.3A-3N. The operations include forming (Block410) vertically-stacked preliminary nanosheets NS-P (FIG.3A) of a preliminary transistor stack. The preliminary nanosheets NS-P include lower nanosheets and upper nanosheets that are stacked on the lower nanosheets. Moreover, the preliminary transistor stack also includes a sacrificial material310(FIG.3A) that is on the lower nanosheets and the upper nanosheets.

An insulating material320(FIG.3A) is formed (Block415) on the preliminary transistor stack. Subsequently, an insulating material330(FIG.3B) having an etch selectivity with respect to the insulating material320is formed (Block420) on the insulating material320. A recess region301(FIG.3C) is then formed (Block425) by removing an exposed portion of the insulating material320, along with underlying portions of the preliminary nanosheets NS-P (FIG.3A) and the sacrificial material310(FIG.3A).

A spacer340(FIG.3D) is formed (Block430) in the recess region301. Another recess region302(FIG.3E) is formed (Block435) by removing an outer (e.g., horizontally-protruding lower) portion of the spacer340to expose an upper surface and a sidewall of the sacrificial material310(FIG.3E). Moreover, an insulating material350(FIG.3F) is formed (Block440) in the recess region302and on a sidewall of the spacer340.

Another recess region303(FIG.3G) is formed (Block445) by removing the insulating material330(FIG.3B) to expose an upper surface of the insulating material320and an upper portion of a sidewall of the spacer340. Next, the insulating material320is removed (Block450) to form a recess region304(FIG.3H) that exposes an upper surface of the sacrificial material310and a middle portion of the sidewall of the spacer340. An insulating material360(FIG.3H) is then formed (Block455), such as by deposition thereof, on the exposed sidewall of the spacer340and on a portion of the exposed upper surface of the sacrificial material310.

A further recess region305(FIG.3I) is formed by removing (Block460) a portion of the sacrificial material310, as well as portions of the three uppermost nanosheets NS that are thereunder, to narrow a width of three uppermost nanosheets NS. For example, a portion of the preliminary transistor stack that is exposed by the recess region304(FIG.3H) may be etched until reaching a portion of the sacrificial material310that is between the three uppermost nanosheets NS and the two lowermost nanosheets NS. A spacer370(FIG.3J) is formed (Block465) on the insulating material360and on exposed sidewalls of the three uppermost nanosheets NS after forming the recess region305. A recess region306(FIG.3K) is then formed (Block470) by removing an exposed portion of the upper surface of the sacrificial material310, along with underlying portions of the two lowermost nanosheets NS.

A planarization process (Block475) is performed to remove upper portions of the spacer340, the spacer370, the insulating material360, and the insulating material350. An example result of the planarization process is shown inFIG.3L. The portion of the spacer370that remains after the planarization process is then removed and replaced (Block480) with a spacer380(FIG.3M) that covers a respective sidewall of each nanosheet NS. Next, lower and upper gates G-L, G-U (FIG.3N) are formed (Block485) on the lower and upper nanosheets NS-L, NS-U, respectively, by replacing the sacrificial material310(FIG.3M), the spacer340(FIG.3M), and the insulating material360(FIG.3M) with a gate electrode material390(FIG.3N).

Nanosheet transistor devices100,200(FIGS.1A and2A) according to embodiments of the present invention may provide a number of advantages. These advantages include reducing parasitic capacitance between a gate G (FIGS.1C and2B) and a source/drain contact140(FIGS.1A and2A). Parasitic capacitance can be reduced by decreasing the amount of gate electrode material that is adjacent the source/drain contact140and/or by aligning (in the direction X;FIG.1A) an insulation region160,260(FIGS.1C and2A), which may comprise a low-k spacer rather than the gate electrode material, with the source/drain contact140. For example, the amount of gate electrode material may be reduced by using at least one tri-gate transistor TG (FIGS.1C-1F) in place of a GAA transistor in a transistor stack110(FIG.1A). As a result, a transistor stack (e.g., a CFET stack) with an sNS structure may have different gate widths WG-L, WG-U (FIG.1C).

Moreover, the reduced parasitic capacitance can improve alternating current (“AC”) speed/performance of the devices100,200. For example, by reducing a drain-side capacitance, AC speed/performance can be boosted, such as by boosting the frequency of a logic circuit in one of the devices100,200.

Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes illustrated herein but may include deviations in shapes that result, for example, from manufacturing.

It should also be noted that in some alternate implementations, the functions/acts noted in flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of the present invention.