Integrated circuits having photonic interconnect layers and methods for fabricating same

Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. In one embodiment of the present invention, an integrated circuit comprises an electronic device layer and one or more photonic interconnect layers. The electronic device layer includes one or more electronic devices, and the electronic device layer is attached to a surface of an intermediate layer. One of the photonic interconnect layers is attached to an opposing surface of the intermediate layer, and each of the photonic interconnect layers has at least one photonic device in communication with at least one of the electronic devices of the electronic device layer.

TECHNICAL FIELD

Embodiments of the present invention are related to integrated circuits, and, in particular, to integrated circuits having a number of photonic interconnect layers for transmitting signals to electronic devices.

BACKGROUND

In the mid 1960's, it was observed by semiconductor manufacturers that the number of transistors fabricated on integrated circuits (“chips”) was doubling about every 18 months. This trend has continued and is now termed “Moore's Law.” The number of transistors is viewed as a rough measure of computer processing power, which, in turn, corresponds to data processing speed. Another version of Moore's Law relates to memory capacity or the density of memory cells in memory chips. Although Moore's Law was originally made as an observation, over time Moore's Law has became widely accepted by the semiconductor industry as a goal for increasing computer processing power and memory capacity. As a result, semiconductor manufacturers have developed technologies for reducing the size of chip components to microscale and even nanoscale dimensions. These chips are typically embedded in packages, and the packages may be connected to other chips or electronic devices by way of signal wires patterned on a circuit board.

FIGS. 1A-1Cillustrate an example chip and package with circuit board interconnects for transmitting data to other chips and devices.FIG. 1Aillustrates a top view of an example chip102and package104. The package104is connected to four separate sets of nine parallel signal lines or wires106-109, each set of signal lines is called a “wire bus.” Each wire bus106-109transmits data in parallel between the chip102and other chips or electronic devices (not shown) that may be located on the same circuit board or different circuit boards. For example, the wire bus106may be connected directly to a random access memory (“RAM”) chip, which is located on the same circuit board (not shown), and the wire bus108may be connected to a sensor, which is located on a different circuit board (not shown).

FIG. 1Billustrates an enlargement of the chip102and the package104shown inFIG. 1A. The chip102includes a number of contact pads located near the perimeter of the chip102, such as contact pad110, and the package104includes a number of pins which are located around the perimeter of the package104, such as pin112. Each contact pad is connected to a single pin via a wire, and each pin is connected directly to a wire in a wire bus. For example, the contact pad110is connected to the pin112via a wire114, and the pin112is connected to a bus wire116. Each electrical signal transmitted or received by the chip102is carried by a contact pad, a wire, a pin, and a wire in a wire bus. Solder bonding.

FIG. 1Cillustrates a cross-sectional view of the chip102and the package104shown inFIG. 1B. As shown inFIG. 1C, the chip102and the package104are supported by a circuit board118. The chip102comprises a Si-based electronic device layer120, and an electronic interconnect layer composed of a local interconnect layer122and a global interconnect layer124. The electronic device layer120comprises transistors and/or capacitor components, electrical current sources, and drains (not shown). Interconnects in the local interconnect layer122, such as interconnect126, electronically interconnect devices in the electronic device layer120, and interconnects in the global interconnect layer124electronically interconnect components of the electronic device layer120to the contact pads. For example, interconnect128electronically interconnects components in the electronic device layer120to the contact pad110. The local interconnect layer122serves as a multiplexer by distributing signals between components of the electronic device layer120, and the global interconnect layer124serves a multiplexer by distributing signals generated within the electronic device layer120to other chips or devices. For example, interconnect128transmits signals to the contact pad110, which is coupled to the wire116by way of the pin112and the wire114.

In order for a first chip to transmit data to a second chip, the first chip multiplexes one or more signals encoding the data. The signals are multiplexed by the global interconnect around the perimeter of the first chip and transmitted to the second chip over a wire bus. Each wire in a wire bus carries one of the multiplexed signals. The global interconnect of the second chip demultiplexes the signals in order to obtain one or more signals that the second chip uses to process the data.FIG. 1Dillustrates a wire bus that electronically interconnects an example microprocessing (“CPU”) chip130and an example RAM chip132. A wire bus connecting the CPU chip130to the RAM chip132comprises 5 bus wires134-138. Suppose the CPU chip130generates data to be stored temporarily in the RAM chip132. The CPU chip130multiplexes the signal corresponding to the data by distributing the signal over contact pads140. The distributed signal can then be transmitted over the bus wires134-138to the contact pads142of the RAM chip132. The RAM chip demultiplexes the distributed signals received by contact pads142into fewer signals that can be used to store the data in one or more memory cells of the RAM chip132.

Although recent semiconductor fabrication methods have made it possible to increase the density of transistors and memory cells in chips, the number of wires needed to interconnect these chips has increased, which has increased the need for larger circuit board surface areas and longer bus wires. As a result, the time needed to transmit data between chips, measured in chip clock cycles, has increased. Although semiconductor manufacturers have responded by developing techniques for reducing the cross-sectional dimensions of the wires so that more wires can be fit into smaller surface areas, there exist limitations on these cross-sectional dimensions. For example, as wire sizes decrease and more wires are packed into a smaller surface area, the number of interference effects increase, such as interference between signals transmitted on adjacent wires, and the number of thermal effects increase, because wire resistance increases as the wire cross-sectional dimensions decrease. These physical limitations make it unlikely that semiconductor manufacturers can continue to take advantage of the component miniaturization offered by microscale and nanoscale semiconductor fabrication techniques. Furthermore, the intrinsic capacitance of the multiplexing and demultiplexing carried out at chip boundaries can greatly exceed the capacitance of the chip, which reduces signal speed transmission between chips. Manufacturers, designers, and users of computing devices have recognized a need for interconnects that provide high bandwidth and high-speed global interconnects between chips and other electronic devices.

SUMMARY

Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. In one embodiment of the present invention, an integrated circuit comprises an electronic device layer and one or more photonic interconnect layers. The electronic device layer includes one or more electronic devices, and the electronic device layer is attached to a surface of an intermediate layer. One of the photonic interconnect layers is attached to an opposing surface of the intermediate layer, and each of the photonic interconnect layers has at least one photonic device in communication with at least one of the electronic devices of the electronic device layer.

DETAILED DESCRIPTION

Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. The term “electronic devices” as used in the following description refers to general-purpose electronic devices, such as a CPU, RAM, read only memory, a sensor, or a logic cell and can also be used to refer to larger integrated electronic devices, such as a field programmable gate array (“FPGA”), which features a matrix of interconnected logic cells, or an application specific integrated circuit (“ASIC”), which features a number of different interconnected general purpose electronic devices. The term “photonic” refers to devices that can be used to transmit either classical electromagnetic signals or quantized electromagnetic signals with wavelengths that span the electromagnetic spectrum. In other words, the term “photonic” as used to describe embodiments of the present invention is not limited to devices for transmitting single quanta, also called “photons,” of electromagnetic signals. The term “channel,” also called “optical channel,” refers to electromagnetic radiation transmitted at one wavelength through a waveguide. In the various embodiments described below, a number of structurally similar components have been provided with the same reference numerals and, in the interest of brevity, an explanation of their structure and function is not repeated.

Photonic interconnect layer embodiments of the present invention can be used to replace certain global, wire-based interconnects used to interconnect physically separated integrated circuits, because transmitting information encoded in channels via waveguides has a number of advantages over transmitting encoded electrical signals via signal lines. First, degradation or loss is much less for channels transmitted via waveguides than for electrical signals transmitted via signal lines. Second, waveguides can be fabricated to support a much higher bandwidth than signal lines. For example, a single Cu or Al wire can only transmit a single electrical signal, while a single optical fiber can be configured to transmit about 100 or more channels. Finally, electromagnetic radiation provides, in general, a much higher transmission rate. For example, electrical signals can be transmitted through Cu and Al wires at about c/3, where c represents the speed of light in free space (about 300,000 k/s). By contrast, channels propagate through photonic devices, such as optical fibers and photonic crystal waveguides, at about c/1.5, which is about twice the speed allowed by wire-based interconnects.

FIG. 2illustrates an isometric view of an integrated circuit200that represents an embodiment of the present invention. The integrated circuit200includes an electronic device layer202located between a photonic interconnect layer204and an electronic interconnect layer206. The photonic interconnect layer202is supported by a substrate208and separated from the electronic device layer202by an intermediate layer210. The integrated circuit200also includes a passivation layer212that caps the electronic interconnect layer206. The electronic devices layer202includes a number of electronic devices (not shown) that can be in electrical communication with other integrated circuits and electronic devices via interconnects in the electronic interconnect layer206. The photonic interconnect layer204receives information encoded in channels to be processed by the electronic device layer202and transmits information encoded in channels generated by the electronic device layer202, as described in greater detail below with reference toFIGS. 4-10. The intermediate layer210and the substrate208are composed of materials having a lower refractive index than the photonic interconnect layer204so that the intermediate layer210and the substrate208can serve as cladding layers for the photonic interconnect layer204. For example, the intermediate layer210can be composed of a single layer of SiO2or a layer of Si sandwiched between two layers of SiO2, and the substrate208can be composed of SiO2.

FIG. 3illustrates a cross-sectional view of the integrated circuit200, shown inFIG. 2, that represents an embodiment of the present invention. As shown inFIG. 3, the electronic device layer202includes a first electronic device302and a second electronic device304, and the electronic interconnect layer206includes a first interconnect306in electrical communication with the first electronic device302and a second interconnect308in electrical communication with the second electronic device304. The electronic interconnect layer206may also include a number of interconnects (not shown) that provide electrical communication between the electronic device302and304. The photonic interconnect layer204includes a first photonic device310and a second photonic device312. The first and second photonic devices310and312can be waveguides, electro-optic modulators, and photodiodes, and certain embodiments are described in greater detail below with reference toFIGS. 5-10. The first photonic device310is in communication with the first electronic device302via a third interconnect314, and the second photonic device312is in communication with the second electronic device304via a fourth interconnect316. The interconnects306and308can be composed of Cu, Al, Pt, or other suitable conductor materials. In certain embodiments of the present invention, the interconnects314and316can also be composed of Cu, Al, Pt, or other suitable conductor materials. In other embodiments of the present invention, the interconnects314and316can be waveguides that transmit modes of electromagnetic radiation from the photonic devices310and312to modulators and photodiodes located within the electronic device layer202.

The photonic interconnect layer204can be used to transmit information that conventionally would have been transmitted over the global wire bus when the process of encoding information in channels and transmitting the encoded channels over waveguides is faster and provides a higher bandwidth than transmitting the same information in electrical signals over the global wire bus. General operation of the photonic interconnect layer204and the electronic device layer202is now described with reference toFIGS. 4-5.FIG. 4illustrates an exploded-isometric view of the integrated circuit200, shown inFIG. 2, that represents an embodiment of the present invention. As shown inFIG. 4, the photonic interconnect layer204receives an unencoded channel, called a “carrier wave,” λcw402.FIG. 5Ashows a plot of the electric field component of a carrier wave λcwversus time. InFIG. 5A, a vertical axis502corresponds to the electric field amplitude, and a horizontal axis504corresponds to time. A curve506represents the electric field component E(z,t) of the carrier wave λcwwith a regular vibrational frequency. The carrier wave λcwtypically carriers no information.

Returning toFIG. 4, an electrical signal s404encoding information is generated by the electronic device302and transmitted to the photonic interconnect layer. The electrical signal s404encodes information in form of a time-varying voltage pattern.FIG. 5Bshows a plot of an example time-varying voltage pattern508versus time. A vertical axis510represents voltage magnitude, and a horizontal axis512represents time. The time-varying voltage pattern508encodes a five-digit binary number “10101,” where low magnitude voltages514-516correspond to the binary number “1,” and relatively high magnitude voltages517and518correspond to the binary number “0.”

Returning again toFIG. 4, the photonic interconnect204includes an electro-optic modulator (not shown) that receives the electrical signal s404and encodes the information in the carrier wave λcw402to produce an encoded channelλ406. The encoded channelλ406can be produced by either amplitude or phase modulation of the carrier wave λcw402.FIG. 5Cillustrates an example of an amplitude modulated channel. InFIG. 5C, a single bit corresponds to four consecutive cycles of the signal, which is roughly equal to the time associated with a bit of the voltage pattern508. The cycles520-522have large amplitudes, which correspond to the binary number “1” and low voltage levels514-516, respectively, shown inFIG. 5B. The cycles523and524have relatively small amplitudes, which correspond to the binary number “0” and high voltage levels517and518, respectively.FIG. 5Dillustrates an example of a phase modulated channel. InFIG. 5D, a single bit also corresponds to four consecutive cycles of the signal. The cycles526-528are not phase shifted and correspond to the binary number “1” and low voltage levels514-516, respectively, shown inFIG. 5B. The cycles529and530are phase shifted by ½ the wavelength of the carrier wave λcw, which corresponds to the binary number “0” and high voltage levels517and518, respectively.

Returning again toFIG. 4, information encoded in a channelλ′406is transmitted into the photonic interconnect layer204and converted into an electronic signal s′408encoding the same information, which is transmitted to the electronic device302for processing.

In alternate embodiments of the present invention, a photonic interconnect layer may include a number of different photonic devices that can be configured in different ways in order to provide electrical and/or photonic communication with electronic devices in an electronic device layer.FIG. 6illustrates a first example configuration of photonic devices of a photonic interconnect layer600that represents an embodiment of the present invention. The photonic interconnect layer600includes a first photodiode602, a second photodiode604, a first electro-optic modulator606, and a second electro-optic modulator608. The electro-optic modulator606is composed of electrodes610and612located on opposite sides of a waveguide614, and the electro-optic modulator608is composed of electrodes616and618located on opposite sides of a waveguide620. The photonic devices are in electrical communication with the electronic devices of the electronic device layer202, shown inFIG. 4. For example, the first photodiode602and the first electro-optic modulator606can be in electrical communication with the electronic device302, shown inFIG. 4, and the second photodiode604and the second electro-optic modulator608can be in electrical communication with the electronic device304, shown inFIG. 4.

In order to transmit information generated by the electronic devices302and304to other electronic devices, a multi-channel laser and multiplexer626generates a first carrier wave λcw1and a second carrier wave λcw2, which are transmitted separately in the waveguides614and620, respectively. The electronic devices302and304generate information in the form of a time-varying voltage patterns, as described above with reference toFIG. 5A. The time-varying voltage pattern generated by the electronic device302is applied to the electrodes610and612of the electro-optic modulator606, and the time-varying voltage pattern generated by the electronic device304is applied to the electrodes616and618of the electro-optic modulator608. The time-varying voltage patterns create corresponding time-varying refractive index changes across waveguide regions628and630, which modulate the carrier waves λcw1and λcw2to produce corresponding channelsλ1andλ2encoding the same information encoded in the time-varying voltage patterns. Information generated by other electronic devices can be transmitted to the electronic devices302and304for processing in the form of a first information encoded channelλ1′ and a second information encoded channelλ2′. The photonic interconnect layer204includes a waveguide622that receives and transmits the first information encoded channelλ1′ to the first photodiode602, and includes a waveguide624that receives and transmits the second information encoded channelλ2′ to the second photodiode604. The photodiodes610and612convert the channelsλ1′ andλ2′ into electrical signals encoding the same information and transmit the electrical signals to the electronic devices302and304, respectively, for processing.

FIG. 7illustrates a second example configuration of photonic devices of a photonic interconnect layer700that represents an embodiment of the present invention. The photonic interconnect layer700represents a two-dimensional photonic crystal that includes 18 photonic nodes, denoted “PN,” and photonic crystal waveguides701-708. For a description of photonic crystals and photonic crystal waveguides seeFundamentals of Optical Waveguides, by Katsunari Okamoto, Elsevier Inc. 2005,Optical Waveguide Theory, by Snyder and Love, Chapman and Hall, London, 1983, andPhotonic Crystals, by Jean_Michel Lourtioz, Springer-Verlag, Berlin, 2005. Each photonic node is in electrical and/or photonic communication with an electronic device in the electronic device layer202and can be optically coupled to one or two of the waveguides. For example, the photonic node710can be optically coupled to the waveguides703and708. Each photonic node may be configured to extract one or more of the channels transmitted in a coupled waveguide and introduce into a coupled waveguide one or more encoded channels. One or more multi-channel lasers can be coupled to the waveguides in order to introduce unencoded carrier waves that can be used by the photonic nodes to encode information. For example, as shown inFIG. 7, a multi-channel laser712introduces carrier waves λcw1, λcw2, and λcw3into the waveguide701, carrier waves λcw4, λcw5, and λcw6into the waveguide702, carrier waves λcw7, λcw8, and λcw9into the waveguide703, and carrier waves λcw10, λcw11, and λcw12into the waveguide704. The photonic nodes can each be configured to extract and encode particular carrier waves. For example, the photonic nodes710,714, and716are configured to extract the carrier waves λcw7, λcw8, and λcw9, respectively, and encode information generated by electronically coupled electronic devices (not shown) in order to obtain corresponding encoded channelsλ7,λ9, andλ9. The photonic nodes710,714,716then evanescently couple the encoded channelsλ7,λ8, andλ9into the waveguide708, which can be output to an optical fiber coupled to the waveguide708.

Each photonic node may include a decoder that extracts a specific channel encoded with information from a waveguide and encodes the same information in electrical signals that are transmitted to electronically couple electronic devices for processing.FIG. 8Aillustrates a first decoder800that represents an embodiment of the present invention. The decoder800comprises a resonant cavity802located in close proximity to waveguide804. The resonant cavity802extracts an encoded channelλafrom the waveguide804via evanescent coupling. The resonant cavity802can be configured as a photodiode that converts the information encoded channelλainto an electrical signal encoding the same information that is transmitted to and processed by a coupled electronic device.

FIG. 8Billustrates a second decoder810comprising a first resonant cavity812and a second resonant cavity814. The first resonant cavity812is located in close proximity to a waveguide816and operates as a drop filter by extracting the encoded channelλafrom the waveguide816via evanescent coupling and transmitting the encoded channelλato the second resonant cavity814also via evanescent coupling. The second resonant cavity814can be configured as a photodiode that converts the information encoded channelλainto an electrical signal encoding the same information that is transmitted to an electronically coupled electronic device for processing.

Each photonic node may also include an encoder that extracts a specific carrier wave from a waveguide and encodes the information generated by an electronically coupled electronic device to produce an encoded channel that is coupled back into the waveguide.FIG. 9Aillustrates a first encoder900that represents an embodiment of the present invention. The encoder900comprises a resonant cavity902located in close proximity to a waveguide904. The resonant cavity902is configured as a drop filter to extract a particular carrier wave λcwbfrom the waveguide1702via evanescent coupling. The resonant cavity902can be configured as an electro-optic modulator that modulates the carrier wave λcwbto produce an encoded channelλb, which is then introduced to the waveguide902via evanescent coupling.

FIG. 9Billustrates a second encoder910that represents an embodiment of the present invention. The second encoder910includes a first resonant cavity912, a local waveguide914, a second resonant cavity916configured as an electro-optic modulator, and a third resonant cavity918that operates as an add filter. The first resonant cavity912is configured as a drop filter in order to extract a particular carrier wave λcwbvia evanescent coupling from a waveguide920. The carrier wave λcwbis then transmitted via evanescent coupling from the first resonant cavity912into the local waveguide914and then coupled again via evanescent coupling into the second resonant cavity916. The resonant cavity916receives electrical signals encoding information generated by an electronically coupled electronic device. The resonant cavity916operates as an electro-optic modulator by modulating the carrier wave λcwbto produce an encoded channelλb, which is then evanescently coupled into the third resonant cavity918. The third resonant cavity912is configured to operate as an add filter by placing the encoded channelλbinto the waveguide920via evanescent coupling.

In general, the resonant cavities configured to operate as drop filters and add filters are positioned within a range of the evanescent fields emanating from a waveguide. Both drop and add filter diameters and distances to the waveguide can be selected so that associated resonant cavities are resonators for specific channels carried by the waveguide. The dielectric constant of the photonic crystal slab, and the spacing and/or size of the lattice of cylindrical holes surrounding each resonant cavity can be selected so that the resonant cavities operated as drop filters can only extract certain channels. In order to provide strong couplings between a waveguide and a resonant cavity, the resonant cavities can be fabricated with high Q factors, such as a Q factor of about 1,000 or larger. For example, the first resonant cavity912, shown inFIG. 9, is configured and positioned near the waveguide920to extract and confine the channel λcwb, and the third resonant cavity918configured and positioned near the bus waveguide920to introduce the encoded channelλbinto the waveguide920. The local waveguide914is located near the second resonant cavity916so that a large fraction of the channel λbcan be transmitted via evanescent coupling into the second resonant cavity916from the local waveguide914. The third resonant cavity918is also configured and positioned to create a strong evanescent coupling with the second resonant cavity916.

Resonant cavities can be fabricated using a variety of different defects in a photonic crystal.FIG. 10Aillustrates a resonant cavity that can be used as a drop filter, an add filter, a electro-optic modulator, and a photodiode that represents one of many embodiments of the present invention. InFIG. 10A, a resonant cavity1002is created by omitting a cylindrical hole within a regular triangular grid of cylindrical holes in a photonic crystal slab1004. The diameter of the resonant cavity1002and the pattern and diameter of cylindrical holes surrounding the resonant cavity1002, such as cylindrical hole1006, can be selected to temporarily trap a particular channel within the resonant cavity1002. A resonant cavity may also be comprises of a cylindrical hole having a diameter that is different from the diameter of the surrounding cylindrical holes, and/or filling a particular cylindrical hole with a dielectric material that is different from the dielectric material of the photonic crystal. As shown inFIG. 10A, the photonic crystal slab1004is supported by a substrate1008and the photonic crystal1004is composed of an intrinsic semiconductor layer1010sandwiched between a positively doped semiconductor layer1012and a negatively doped semiconductor layer1014. The layers1010,1012, and1014comprise a single photonic-crystal layer called a “p-i-n” layer. In other embodiments of the present invention, the photonic crystal slab1004can be composed of a single semiconductor layer or two semiconductor layers, one positively doped and the other negatively doped.

Photonic devices, such as electro-optic modulators and photodiodes, can be fabricated at resonant cavities by fabricating electrodes near the resonant cavities.FIG. 10Billustrates a first configuration of a resonant cavity that can be operated as either an electro-optic modulator or photodiode that represents one of many embodiments of the present invention. A photonic device1016comprises the resonant cavity1002, sandwiched between two electrodes1020and1022. The electrode1020is in contact with the semiconductor layer1012, and the electrode1022is in contact with the semiconductor layer1014. In order for the photonic device1016to operate as a photodiode, the electrodes1020and1022collect a varying electrical current generated by variations in the intensity or amplitude of the electric field component of a channel resonating in the resonant cavity1002. The varying electrical current represents an information stream that can be transmitted from the electrodes1020and1022to an electronically coupled electronic device. The semiconductor layers1012and1014may have different dopant concentrations or dopant types so that the photonic device1016can be operated as an electro-optic modulator for encoding data in a carrier wave. The amplitude of the electric field component of a carrier wave resonating in the resonant cavity1002is changed by varying a voltage across the resonant cavity1002, as described above with reference toFIG. 5C.

FIG. 10Cillustrates a second configuration of a resonant cavity that can be operated as an electro-optic modulator that represents one of many embodiments of the present invention. As shown inFIG. 10C, a photonic device1026includes the resonant cavity1002and two electrodes1028and1030located under the resonant cavity1002. The layer1004can be comprised of the p-i-n layers, described above with reference toFIG. 10A, or a single semiconductor layer. The photonic device1026operates as an electro-optic modulator by varying a voltage across to the electrodes1028and1030which, in turn, changes the dielectric constant of the semiconductor layers in the resonant cavity1002causing a phase and/or amplitude change in the electric field component of a carrier wave resonating in the resonant cavity1002.

The intrinsic capacitance in demodulator electrode detectors is often low enough that fluctuations in current due to noise generated by thermal agitation of electrons in a conductor, called “Johnson noise,” may be insignificant. As a result, statistics associated with an electromagnetic signal source dominate the bit error rate (“BER”) arising in the serial digital signal corresponding to the output from the detector. For example, a Poisson distribution of an electromagnetic signal having30photons per bit is sufficient to achieve a BER of less than 10−13. Incorporating a doped region into a resonant cavity with a Q factor of 10 to 100 may compensate for the reduced absorption. With an appropriate choice of Q factor to impedance-match, the optical input losses of the cavity to the internal absorption loss of the detector may increase detection efficiency. For example, an increase in the detection efficiency of about 50% may be achieved.

Similar considerations can be applied to the design of a resonant cavity enhanced (“RCE”) modulator using electro-optic or current injection techniques. Modulation depths as high as 50% may be achieved for a resonant cavity with a Q factor greater than about 1,000. Although other physical effects can be employed, such as variations in the free carrier plasma index, electro-optic modulation can be used with a potential difference of about 30 mV applied across a gap of about 300 nm to produce an electric field of 1 kV/cm, which is sufficient to generate a refractive index change as large as 0.001 in a wide variety of linear dielectric materials.

In other embodiments of the present invention, an integrated circuit can employ two or more photonic interconnect layers.FIG. 11illustrates an isometric view of an integrated circuit1100having two photonic interconnect layers that represents an embodiment of the present invention. The integrated circuit1100includes a first photonic interconnect layer1102and a second photonic interconnect layer1104that receive information encoded in channels to be processed by the electronic device layer202and transmits information encoded in channels generated by the electronic device layer202, as described above with reference toFIGS. 4-10. The integrated circuit also includes a cladding separating the first photonic interconnect layer1102from the second photonic interconnect layer1104.

FIG. 12illustrates a cross-sectional view of the integrated circuit1100, shown inFIG. 11, that represents an embodiment of the present invention. As shown inFIG. 12, the first photonic interconnect layer1102includes a first photonic device1202and a second photonic device1204, and the second photonic interconnect layer1104includes a third photonic device1206. The first photonic device1202is in electrical communication with the first integrated circuit302via a first interconnect1208, the second photonic device1204is in electrical communication with the second integrated circuit304via a second interconnect1210, and the third photonic device1206is in electrical communication with first integrated circuit302via a third interconnect1212. In certain embodiments of the present invention, the interconnects1208,1210, and1212can be composed of Cu, Al, Pt, or other suitable conductor materials. In other embodiments of the present invention, the interconnects1208,1210, and1212can be waveguides that transmit modes of electromagnetic radiation from the photonic devices1202,1204, and1206to modulators and photodiodes located within the electronic device layer202.

In various embodiments of the present invention, the type of semiconductor materials and compounds used to form the photonic devices in the photonic interconnect layers is determined by the wavelengths selected for the carrier waves and encoded channels. For example, Si-based waveguides, Si-based electro-optic modulators, Ge-based electro-optic modulators, SiGe-based photodiodes, and Ge-based photodiodes are used with channels and laser sources providing carriers waves with wavelengths between about 1400 nm and about 1600 nm. In addition, for SiN-based waveguides, SiC-based waveguides, SiN/SiC-based electro-optic modulators, polymer-based electro-optic modulators, and Si-based photodiodes are used with channels and laser sources providing carrier waves with wavelengths between about 700 nm and about 900 nm.

FIG. 13illustrates a network1300comprising four chips1301-1304interconnected via photonic-based interconnects that represents an embodiment of the present invention. Electronic devices of the chips1301-1304are interconnected by waveguides, such as photonic crystal waveguides or optical fibers. For example, CPU1306is coupled to photonic nodes1308and1310. The photonic node1308is interconnected to the photonic node1312, which is coupled to RAM1314, and the photonic node1310is interconnected to the photonic node1316, which is coupled to sensor1318. Note that the number of waveguides needed to interconnect the photonic nodes is based on the bandwidth requirements for transmitting electromagnetic signals between the corresponding coupled subsystems. For example, three waveguides are used to interconnect the photonic nodes1308and1312, and two waveguides are used to interconnect the photonic node1310to the photonic node1316.

The following describes a number of method embodiments directed to fabricating the photonic integrated circuit200. Note that in certain method embodiments, the order of the steps described below may be changed according to the temperature at which certain features are formed. For example, a first set of method steps can be used to form a first set of electronic and photonic features within a high temperature range and a second set of method steps can be used to form electronic and photonic features within a relatively lower temperature range.

A first method for fabricating the integrated circuit200is described below with reference toFIGS. 14A-14G.FIGS. 14A-14Gillustrate processing steps for forming the integrated circuit200using cross-sectional views that represent embodiments of the present invention. First, as shown inFIG. 14A, a three-layer substrate1400is provided. The substrate1400comprises a first layer of silicon1402attached to a surface of a first oxide layer1404. The silicon layer1402and the oxide layer1404are often referred to as “silicon-on-insulator” (“SOI”). The substrate1400also includes a second semiconductor layer1406attached to an opposing surface of the oxide layer1404. The oxide layer1404can be composed of SiO2or another suitable insulating material; and the semiconductor layer1406can be composed of either silicon or a silicon/germanium compound.

Next, as shown inFIG. 14B, electronic devices1408and1410are formed in the first silicon layer1402. Photolithography and etching methods for forming components of the electronic devices1408and1410, such as transistors and capacitors, are well-known in the art. The first silicon layer1402with electronic devices1408and1410corresponds to the electronic device layer202described above.

Next, as shown inFIG. 14C, vias1412and1414are formed in the oxide layer1404and the semiconductor layer1406. The vias1412and1414extend through both the oxide layer1404and the semiconductor layer1406and can be formed using one or more well-known etching techniques, such as reactive-ion etching, focused ion-beam etching, and chemically assisted ion-beam etching. Interconnects1416and1418are then formed within the vias1412and1414, respectively. The interconnects1416and1418are composed of conductive material, such as Cu, Al, Pt, or other suitable conductive materials and can be deposited in the vias1412and1414using chemical-vapor deposition, plasma-enhanced chemical vapor deposition, or a physical vapor deposition technique, such as sputtering.

Next, as shown inFIG. 14D, a first carrier wafer1420may be attached to the first silicon layer1402. The first carrier wafer1420can be a layer of silicon or other suitable material which is attached to the silicon layer1402using an adhesive, such as epoxy, glue, or another suitable bonding substance for bonding the carrier wafer1420to the first silicon layer1402.

The carrier wafer1420can be used to support the three-layer substrate1400during the next step shown inFIG. 14E. As shown inFIG. 14E, photonic devices1420and1422are formed in the semiconductor layer1406. The photonic devices1420and1422can be electro-optic modulators, photodiodes, waveguides, and photonic nodes, and can be formed using various lithographic and etching techniques. For example, the photonic devices1420and1422can be formed using reactive-ion etching, focused ion-beam etching, chemically assisted ion-beam etching, electron beam lithography, photolithography, and nanoimprint lithography. The semiconductor layer1406with photonic devices1422and1424corresponds to the photonic interconnect layer204described above.

Next, as shown inFIG. 14F, the first carrier wafer1420is detached from the first silicon layer1402and a second carrier wafer1426is attached to the semiconductor layer1406using an adhesive. As shown inFIG. 14G, the second carrier wafer1426provides a support for forming an electronic interconnect layer1428, which corresponds to the electronic interconnect layer206described above and can be formed using any number of well-known techniques. In another embodiment of the present invention, the step described with reference toFIG. 14Gcan be performed after the step described with reference toFIG. 14B, which eliminates the need for the first carrier wafer1420.

A second method for fabricating the integrated circuit200is described below with reference toFIGS. 15A-15F.FIGS. 15A-15Fillustrate processing steps for forming the integrated circuit200using cross-sectional views that represent embodiments of the present invention. First, as shown inFIG. 15A, a three-layer substrate1500is provided. Like the substrate1400, the substrate1500comprises a first layer of silicon1502attached to a surface of a first oxide layer1504, which is referred to as “silicon-on-insulator” (“SOI”). The substrate1500also includes a second semiconductor layer1506attached to an opposing surface of the oxide layer1504. The first oxide layer1504can be composed of SiO2or another suitable insulating material, and the semiconductor layer1506can be composed of either silicon or a silicon/germanium compound.

Next, as shown inFIG. 15B, a second oxide layer1508is deposited on a surface of the semiconductor layer1506, and a second silicon layer1510is deposited on a surface of the second oxide layer1508. The second silicon layer1510can be deposited using chemical vapor deposition, plasma-enhanced chemical vapor deposition, low pressure chemical vapor deposition, or sputter deposition. The second silicon layer1510can be formed in a separate processing step and attached to the second oxide layer1508using smart cut or wafer bonding.

Next, as shown inFIG. 15C, electronic devices1512and1514are formed in the first silicon layer1502using well-know photolithography and etching. The first silicon layer1502with electronic devices1512and1514corresponds to the electronic device layer202described above. Next, an electronic interconnect layer1516is formed on the first silicon layer1502using well-known techniques. The electronic interconnect layer1516corresponds to the electronic interconnect layer206described above.

Next, as shown inFIG. 15D, a carrier wafer1518is bonded to the electronic interconnect layer1516using an adhesive, such as an epoxy, glue, or another suitable bonding substance. In addition, the second silicon layer1510and the oxide layer1508are removed using reactive-ion etching, focused ion-beam etching, and chemically assisted ion-beam etching.

The carrier wafer1518provides support for forming vias1520and1522are formed in the oxide layer1508and the semiconductor layer1506. The vias1520and1522extend through both the oxide layer1508and the semiconductor layer1506. Interconnects1524and1526are then formed within the vias1520and1522, respectively. The vias1520and1522and the interconnects1524and1526can be formed as described above with reference toFIG. 14C.

Next, as shown inFIG. 14F, photonic devices1528and1530are formed in the semiconductor layer1506. The photonic devices1528and1530can be electro-optic modulators, photodiodes, waveguides, and photonic nodes, and can be formed using various lithographic and etching techniques, as described above with reference toFIG. 14E.

A third method for fabricating the integrated circuit200is described below with reference toFIGS. 16A-16D.FIGS. 16A-16Dillustrate processing steps for forming the integrated circuit200using cross-sectional views that represents an embodiment of the present invention. First, as shown inFIG. 16A, a three-layer substrate1600is provided. The substrate1600includes a silicon-on-insulator substrate comprising a first layer of silicon1602attached to a surface of a first oxide layer1604. The substrate1600also includes a second silicon layer1606attached to an opposing surface of the oxide layer1604. The first oxide layer1604can be composed of SiO2or another suitable insulating material.

Next, as shown inFIG. 16B, a second oxide layer1608is deposited on a surface of the second silicon layer1606, and a semiconductor layer1610is deposited on a surface of the second oxide layer1608. The second oxide layer1608is composed of SiO2and can be deposited using chemical vapor deposition, plasma-enhanced chemical vapor deposition, low pressure chemical vapor deposition, spattering, and thermal oxidation. The semiconductor layer1610is composed of silicon or silicon/germanium and can be formed in a separate processing step and attached to the second oxide layer1608using wafer bonding.

Next, as shown inFIG. 16C, electronic devices1612and1614are formed in the first silicon layer1602using well-know photolithography and etching techniques. The first silicon layer1602with electronic devices1612and1614corresponds to the electronic device layer202described above. Next, an electronic interconnect layer1616can be formed on the first silicon layer1602using well-known techniques. The electronic interconnect layer1616corresponds to the electronic interconnect layer206described above. Next, vias1620and1622are formed in the first and second oxide layers1604and1608, the second silicon layer1606, and the semiconductor layer1610. The vias1620and1622extend through both the oxide layer1508and the semiconductor layer1506. Interconnects1624and1626are then formed within the vias1520and1522, respectively. The vias1620and1622and the interconnects1624and1626can be formed as described above with reference toFIG. 14C.

Next, as shown inFIG. 16D, photonic devices1628and1630are formed in the semiconductor layer1610. The photonic devices1628and1630can be electro-optic modulators, photodiodes, waveguides, and photonic nodes, and can be formed using various lithographic and etching techniques, as described above with reference toFIG. 14E.