Method and system for packet reassembly based on a reassembly header

In a control method of communication system in which primary packet output from an information processor in a transmitting end is sent to a network after fragmentation into a plurality of secondary packets in a communication controller at the transmitting end, and a plurality of secondary packets are sent to an information controller at the receiving end after reassembly for recovery of the primary packet by the communication controller at a receiving end, a reassembly header for processing the primary packet is sent to the information processor at the receiving end before the reassembly processing of the secondary packets is finished, and protocol processing in which the information processor analyzes the reassembly header is executed in parallel with reassembly processing of the packets in an information controller.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a control method of a communication system, a communication controller, a control method of a data processing system, a communication system and programs. More specifically, the present invention relates to a technology, which is effective and can be adopted as a computer network technology, which executes packet transfer communication using communication protocols such as TCP/IP (Transmission Control Protocol)/(Internet Protocol).

2. Description of the Related Art

In the field of computer networks, physical media for high-speed networks have developed and have become increasingly popular year after year. Today, it is not exceptional for personal computers to comprise ports for Gigabit Ethernet, and a network adapter (hardware connected to the information processor for transferring data to networks) for use with 10-Gigabit Ethernet (Trademark) is available.

Although the physical media have developed supporting increased data rates, the processing speed of TCP/IP, the predominant protocol of use in computer networks, has not caught up with the transmission rates of the physical media. Even in an ultrahigh-speed network such as 10 Gbit Ethernet, the actual transmission rate of the information processor even with an extremely high-speed CPU cannot equal the speed of the physical media, which gives rise to the issue that it is not possible to fully utilize the communication capacity of the network. Technologies for addressing the issue of protocol processing and for speeding up communications have been much examined.

The technology for high-speed protocol processing currently prevalent is a technology called TCP segmentation offload. According to this technology, packets are transferred with a size larger than the maximum size (MTU) that can be transferred to a network when transferred from an information controller to a network adapter. Over-sized packets are divided into packets of a size which can be transferred to the network by the network adapter. By so doing, a transmitting information controller can generate packet headers in units of large data size, reducing the frequency of protocol processing for packet header generation. Consequently, it is possible for a CPU with low capacity to transfer a large quantity of data at high-speed.

This idea can be applied to the receiving end. That is, the loading of the protocol processing can be reduced in the information controller by assembling a large-sized packet from small-sized packets and transferring it to the information controller (as in Patent Document 1, for example).

This reassembly processing allows improvement of communication throughput (transferred data volume per unit of time), however because the information controller cannot start protocol processing during reassembly processing by the network adapter, an issue remains that communication delay time increases.

TCP segmentation offload is a method, which divides segments at the TCP level. Besides this method, there is an approach to reduce the loading of the host by dividing packets at the IP level. For example, Patent Document 2 describes a method to reduce the loading of the source and the destination information controllers by reassembly and fragmentation between Ethernet IP packets and the data in the high-speed bus of a communication server lying between the external Ethernet and the high-speed bus interconnecting servers instead of a network.

As explained above, the loading of protocol processing in an information controller can be reduced by accumulating the packets received via a network, reassembling the packets into a large packet and transferring the packet to the information controller. However, the accumulation of the received packets causes a delay in the arrival of the packet to the receiving information controller by the amount of time required for accumulation, thus causing an increase in delay time. The issue to be addressed is to control the increase in packet transfer delay time whilst maintaining the loading reduction effect by packet reassembly processing of the receiving information controller at the receiving end.Patent Document 1: Japanese Published Unexamined Application No. 06-85822Patent Document 2: Japanese Published Unexamined Application No. 2000-101613

It is an object of the present invention to provide a technology, which enables the simultaneous pursuit of reduction of loading in the host computer by the fragmentation and reassembly of the transmitted and received packets and reduction of transmission delay time of the transmitted and the received packets.

It is another object of the present invention to provide a technology, which allows the simultaneous pursuit of efficient utilization of the transmission rate of the information network by fragmentation and reassembly of the transmitted and the received packets and reduction in transmission delay time of the transmitted and the received packets.

SUMMARY OF THE INVENTION

It is the first aspect of the present invention to provide a communication system control method, comprising steps of dividing a primary packet output from an information processor at the transmitting end into a plurality of secondary packets at a communication controller at the transmitting end and sending them to a network and reassembling the secondary packets to recover the primary packet at a communication controller at the receiving end and sending the packet to an information processor at the receiving end, wherein the communication controller at the receiving end sends a reassembly header, for processing the primary packet before reassembly processing of the secondary packets finishes, to the information controller at the receiving end, and the information processor executes protocol processing, during which the information processor analyzes the reassembly header and is executed in parallel with the reassembly processing of the secondary packets in the communication controller.

It is the second aspect of the present invention to provide a communication controller, which controls the transmission and reception of data lying between an information processor and a network, comprising a function of transferring, after the reception and reassembly, a plurality of the secondary packets generated by fragmentation of the primary packet at the transmitting end to the information processor at the receiving end; and a header analysis function for generating a reassembly header for processing the primary packet reassembled from the secondary packets and sending the packet to the information processor at the receiving end before the completion of the reassembly of the secondary packets.

It is the third aspect of the present invention to provide a communication controller, lying between an information processor and a network and comprising a function for generating the secondary packets by fragmentation of the primary packet received from the information processor and sending it to the network, wherein further comprised is a function for sending the secondary packets, comprising the data required to generate the reassembly header for processing the primary packet after reassembly, advance to the other secondary packets to the network.

It is the fourth aspect of the present invention to provide a communication controller, lying between an information processor and a network and comprising a function for generating the secondary packets by fragmentation of the primary packet received from the information processor and sending the secondary packets to the network, wherein further comprised is a function for sending the tertiary packet, comprising the data required to generate the reassembly header for processing the primary packet after reassembly, separately from the secondary packets to the network.

It is the fifth aspect of the present invention to provide a control method of an information processing system, comprising an information processor and a communication controller lying between the information processor and the network, wherein, when transferring a packet reassembled by the communication controller from a plurality of packets fragmented and sent to the network at the transmitting end, the method comprises steps of sending out a reassembly header, for processing the reassembled packet, to the information processor before completion of reassembly processing of the packets by the communication controller, and executing protocol processing in which the information processor analyzes the reassembly header in parallel with reassembly processing of the packets in an information controller.

Specifically, in the present invention, for the purpose of controlling the increase in delay time, before the reassembly of the packet at the receiving end, a header for the reassembled packet is generated by the communication controller at the time that the primary packet is received by a communication controller such as a network card and sent to the higher layer information controller to start protocol processing.

In order to generate the header for the reassembled packet and to determine whether to reassemble subsequent packets from the network or not, a simple header analysis system in the communication controller can be comprised.

By so doing, parallel operation of the protocol processing of the information processor and reception of subsequent packets to be reassembled by the communication controller can be executed. The protocol processing of the information processor can be started immediately upon reception of the header and completed at the time of transfer of all packet data to be reassembled by the communication controller. If data is not received within a designated time period, the processing is re-attempted with the received data or the data is dropped.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description, details of the preferred embodiment of the present invention are set forth with reference to the drawings.

FIG. 1is a schematic diagram describing a configuration of a communication system of one embodiment of the present invention.FIG. 2is a schematic diagram illustrating a configuration of a communication controller and a data processor, comprised in the communication system of the present embodiment.

The communication system of the present embodiment comprises a transmitting host10A with a transmission side communication controller20A, a receiving host10B with a reception side communication controller20B, and an information network30lying between the transmission side communication controller20A and the reception side communication controller20B.

Each of the transmitting host10A and the receiving host10B are comprised of an information processor10shown inFIG. 2, for example, and each of the transmission side communication controller20A and the reception side communication controller20B are comprised of a network card20also shown inFIG. 2.

The following description separates the functions of the network card20at the transmitting end from the functions of the network card20at the receiving end for convenience of explanation. However, transmission and reception are usually performed in one device in data communication, and therefore the transmission side communication controller20A and the reception side communication controller20B can be comprised of a single network card20.

The information processor10comprises a CPU11, which controls the entire device, main memory12, which stores data and programs run by the CPU11, and a memory bus13, which connects the CPU11and the main memory12.

In the main memory12, programs such as a Kernel12a, operating system software, and User processes12boperating at a higher level than the Kernel12aare implemented. Execution of these programs in the CPU11allows data communication over the information network30.

The network card20comprises a network controller21, buffer memory22, an encoder/decoder23, a transceiver24, and a bus controller25.

The network controller21controls transmission and reception of data, more specifically, sending packets to the information network30after fragmentation of the packets transmitted by the information processor10and passing out the fragmented packet arriving via the information network30to the information processor10after reassembling the fragmented packets. The network controller21is comprised of, for example, microcomputers and logic circuits. The operation of the network controller21by a program stored in a built-in ROM (not shown in drawings) realizes various functions as hereinafter explained.

The buffer memory22is used to temporarily hold packets for the purpose of fragmentation and reassembly processing of the packets, and is also used to store management information.

The encoder/decoder23performs operations such as encoding the data of the transmitted packet to the data for communication and decoding the encoded data from the transmitting end.

The transceiver24transmits and receives the transmitted and received data, encoded by the encoder/decoder23, after converting the data into signal form, which is compatible with the physical communication medium comprising the information network30.

The bus controller25controls data transfer via the memory bus13between the buffer memory22and the main memory12of the information processor10. It also mediates the access of the information processor10to the main memory12by the network controller21.

In this embodiment, an IP packet with a maximum size of 64 KB (kilobytes) at the transmitting host10A is divided into IP fragments (packets) by the transmission side communication controller20A. The reception side communication controller20B receives the IP fragments (packets). The payload in the IP packet before fragmentation includes a TCP packet.

FIG. 3is a diagram describing fragmentation of a packet in the present embodiment. The IP packet50(primary packet) before fragmentation contains an IP header51, a TCP header52, and data53. This IP packet50is generated by the transmitting host10A, and is passed to the transmission side communication controller20A.

In the transmission side communication controller20A, a plurality of IP fragment packets60(secondary packets) are formed by the fragmentation of an IP packet50. An IP fragment header61is added to each individual IP fragment packet60. The size of each IP fragment packet60is set to the maximum size which can be transferred by the information network30. By so doing, the transmitting host10A reduces the frequency, that is the loading, of transmission protocol processing, which comprises generating and adding an IP header and a TCP header to the head of the data53, by setting the length of the IP packet50to a size over the maximum size of the information network30.

As described inFIG. 4, in the case of the present invention, the network controller21of the network card20, which is the reception side communication controller20B, comprises a header analysis system21a. When a plurality of IP fragment packets60are reassembled and are passed to the receiving host10B, an analysis of the IP fragment header61of an individual IP fragment packet60enables generation of the reassembly header51-1used after reassembly, passing of it to the receiving host10B before the data, and simultaneous execution of reassembly processing of the IP fragment packet60by the network card20and protocol processing at the receiving host10B.

The reassembly header51-1is, as described later, generated in the header analysis system21a, comprised in part of the network controller21, so as to comprise the data, among other data in the IP header51in the IP packet50after reassembly, required to start the receiving end protocol processing at the receiving host10B.

A method for regenerating the reassembly header51-1from the IP fragment packet60is explained below.

AsFIG. 5describes, the IP header51of the IP packet50before fragmentation comprises the data of version51a, of the IP header length51b, of the type of service Sic, of the packet length (total length)51d, of the identifier (identification)51e, of the flags51f, of the fragment offset51g, of the time to live (TTL)51h, of the protocol51i, of the header checksum51j, of the source IP address51kand of the destination IP address51m.

With the exception of the last fragment packet, the IP fragment header61of an IP fragment packet60after fragmentation, as shown inFIG. 6, comprises the data of version61a, of the IP header length61b, of the type of service61c, of the packet length (total length)61d, of the identifier61e, of the flags61f, of the fragment offset61g, of the time to live (TTL)61h, of the protocol61i, of the header checksum61j, of the source IP address61kand of the destination IP address61m. The flags61fcontain “xx1” (where x, represents either 0 or 1).

The IP fragment header61of the last IP fragment packet60, as described inFIG. 7, has the same structure as the other IP fragment headers61(FIG. 6), except that the last bit of the flags61f, “xx0”, is different.

Reassembly of the IP fragment packet60is possible referencing such an IP fragment header61using the identifier61e(identification), the flags61f, the fragment offset61g, and the packet length61d(total length).

One bit in the flags61findicates whether or not more fragments follow the IP fragment packet. The fragment offset61gspecifies the offset of the fragment from the original datagram in units of 8 bytes starting from 0. The packet length61d(total length) is the length in units of bytes of the IP fragment packet (including the header and the data). The IP fragment packets60to be reassembled have the same value in the identifier61e(identification).

In the case of IP fragment packet60, the IP header after the reassembly processing (the packet header after the fragment reassembly) is obtained from the last fragment of the IP fragment header61. Because the TCP header of the packet after reassembly processing is in the first fragment, both the first and the last fragments of the IP fragment packet60are required to generate the reassembly header51-1sent to the receiving host10B.

The network card20at the receiving end inputs the IP fragment packet60to the reassembly packet header generator41of the network controller21, shown inFIG. 10Aand described later. When the reassembly packet header generator41recognizes the last fragment, it generates the IP header after reassembly processing (i.e. reassembly header51-1) of the fragments.

More specifically, the packet length61d(total length) of the reassembled IP fragment header61, shown inFIG. 7, should be replaced with the packet length61d(total length) of the last IP fragment packet60+the fragment offset61gof the last IP fragment packet60×8 (61d+[61g×8]), and the header checksum61jrecalculated. The reassembly packet header generator41carries out this calculation, as shown inFIG. 8.

The combination of the header obtained by the above method and the TCP header52, comprised in the first IP fragment packet60, generates the reassembly header51-1.

In the case of IP fragmentation, the data to generate the reassembly header51-1of the present embodiment is carried by the last fragment (the IP fragment packet60). For the effective performance of the present invention, the last fragment is required to be transmitted first. For that reason, transmission side communication controller20A comprises a reassembly packet header advance transmitter42, explained inFIG. 13described later. Generally, in the context of an IP packet50stored in the buffer memory22of a transmission side communication controller20A, the last part of the IP packet50after fragmentation into IP fragment packets60is not transferred first. However, because the entire IP packet50, which is the transmitted data, is originally stored in the buffer memory22, it is possible to transfer the last part first.

The reception side communication controller20B generates the reassembly header51-1, sends it to the receiving host10B, and notifies the receiving host10B that the reassembly header51-1was sent. In the present invention, this notification means is realized by allocating a notification domain12cin a part of the main memory12of the receiving host10B, by accessing the notification domain12cthrough the bus controller25and writing the notification flag data.

Other means such as generating an interrupt at the receiving host10B, polling the reception side communication controller20B from the receiving host10B, or a combination of the above means are also feasible.

When the receiving host10B recognizes the arrival of the reassembly header51-1, the receiving host10B executes the protocol processing of the receiving end with reference to the reassembly header51-1. For protocols such as TCP, which update the connection status, only operations to determine the updated value are executed during this protocol processing. The result is not yet set (SeeFIG. 18described later).

During the processing operation, the IP fragment packets60generated at the transmitting end (by the transmission side communication controller20A) arrive in sequence from the information network30. The protocol processing using the reassembly header51-1of the receiving host10B and the arrival of the data (the IP fragment packets60) from the information network30proceed in parallel.

The data arriving at the reception side communication controller20B can be processed by any of the following methods: a method of storing the data in the buffer memory22of the reception side communication controller20B until the protocol processing of the receiving host10B is finished; a method of transferring the data to the receiving host10B upon finishing the reassembly processing; and a method of transferring the data in sequence to the receiving host10B without storing it in the reception side communication controller20B.

The present embodiment adopts the method of storing the data in the buffer memory22of the reception side communication controller20B until protocol processing at the receiving host10B is finished. Upon completion of the reassembly of a plurality of IP fragment packets60in the reception side communication controller20B, the receiving host10B is notified of the completion. When the receiving host10B recognizes the completion, it sets the updated status of the protocol processing, transferring the reassembled data at the same time.

The above series of processes between the transmitting host10A and the receiving host10B during data communication is summarized in a flowchart inFIG. 9.

The communication data generated in the User process12bof the transmitting host10A is provided to the Kernel12a(Step101), and is comprised of the IP packet50, after TCP/IP protocol processing (Step102), it is passed on to the transmission side communication controller20A (Step103).

In the process of fragmentation of the IP packet50in the buffer memory22, the transmission side communication controller20A first generates the last IP fragment packet60(Step104), and sends it to the reception side communication controller20B (Step105). Then fragmentation processing of the unprocessed portion of the IP packet50into a plurality of IP fragment packets60(Step106) is executed, and the first IP fragment packet60is sent to the reception side communication controller20B (Step107).

The reception side communication controller20B generates the reassembly header51-1from the last IP fragment packet60received in Step105and the first IP fragment packet60comprising the TCP header52(Step108). The reassembly header51-1is sent to the receiving host10B (Step109).

The receiving host10B, having received the reassembly header51-1, starts TCP/IP the protocol processing of the receiver host (Step113).

At this time, the reception side communication controller20B receives the IP fragment packet60sequentially from the transmission side communication controller20A via the information network30(Step110), and executes reassembly processing to reassemble the original IP packet50simultaneously with the protocol processing of the receiving host10B (Step111). If errors are detected in the IP fragment packets60during the reassembly, the reception side communication controller20B sends an error notification to the receiving host10B, if required, using the method described inFIG. 16andFIG. 17, and passes the reassembled IP packet50to the receiving host10B (Step112).

Based on the protocol processing result (Step114) the data received in Step112by the receiving host10B, is transferred to the User process12bcomprised in the receiving host10B.

When error notification is generated by the reception side communication controller20B during protocol processing, the protocol processing result is cancelled if needed.

FIG. 10AandFIG. 10Bshow a comparison of the processing flow in time of the present embodiment with that of the conventional method.

To be more specific, in the conventional method described inFIG. 10B, the reassembly processing of the IP fragment packet60, the data transfer processing of the reassembled IP packet50from the reception side communication controller20B to the receiving host10B, and protocol processing at the receiving host10B are executed sequentially in time. Therefore, fragmentation of the IP packet50into the IP fragment packet60and recovery of the IP packet50in the reception side communication controller20B involves a large transmission delay time.

Compared with the conventional method, the present embodiment inFIG. 10A, however, enables the parallel operation of the protocol processing in the receiving host10B and the reassembly processing in the reception side communication controller20B. Consequently, the delay time caused by the reassembly processing of the IP fragment packet60into the IP packet50can be reduced. The advantage of this parallel operation in the present invention is especially notable when the protocol processing overhead at the receiving host10B is high (i.e. it is complicated and time-consuming).

The effects of the present embodiment are presented inFIG. 11Afor definite values.FIG. 11AandFIG. 11Bshow a detailed example in which a 10 Gbps (1.25 GB/s) network is used, and the transmission side communication controller20A divides the 4 KB IP packet into IP fragments of the MTU (Maximum Transfer Unit), generally used in Ethernet (Trademark), and transmits the IP fragments which are then received by the reception side communication controller20B. In such a case, the packet is divided into two 1.5 KB packets and a 1 KB packet, and then transferred.

The case of the conventional method as inFIG. 11Bis examined first. It takes 4 KB/1.25 GB/s=3.2 μs for the network cards at the receiving end to receive all the packets. The reassembly processing is also executed while the data is transferred from the network to the network cards, and it takes 3.2 μs to complete the reassembly processing.

The data transfer from the network cards to the host computer requires another 3.2 μs under the assumption that the bit-rate of the connection between the network cards and the host computer is 10 Gbps. TCP/IP protocol processing requires 5 μs˜10 μs per packet using a 2.4 GHz CPU. The protocol processing additionally requires the step of copying data from the Kernel to User space within the host computer, which takes 3.2 μs to copy 4 KB data at the rate of 10 Gbps. Accordingly, with the conventional method inFIG. 11B, the total time from the arrival of the primary packet to the network cards to complete the protocol processing in the host computer is 14.6 μs where the protocol processing (which can only be executed with the header) takes 5 μs.

The case of the present embodiment as inFIG. 11A, which transfers the reassembly header first, is examined next. In such a case, the receiving host10B can start the protocol processing on receiving the reassembly header51-1. The reassembly header generation time+the status updating time can be made significantly smaller than the protocol processing time. Consequently, the reassembly header generation time+the status updating time+the protocol processing time are less than 6.4 μs. The total processing time, which is the sum of the reassembly processing at the reception side communication controller20B+the data transfer time to the receiving host10B+the time of duration of the copy between Kernel-User space, is 9.6 μs. As a result, the present embodiment inFIG. 11Areduces the delay time by 35% compared with the conventional method. Such an effect of delay time reduction is useful in application programs (User processes12b), such as scientific computation, where the delay time of the information network30influences its functioning.

As indicated in the above example, the effect of the present embodiment depends on the capacity of the CPU11in the receiving host10B and the packet size of the IP packet50before fragmentation. In order to maximize the effect of this method in various systems, the packet size of the IP packet50before fragmentation can be selected according to the capacity of the receiving host10B.

The reassembly header advance transfer method of the present embodiment requires processing based only on the header information of the TCP/IP protocol processing in the receiving host10B. Basically all processing except the data checksum of TCP is possible with the header information alone. The types of processing are, for example, (Process 1) checking the header size of TCP and IP packets, (Process 2) verification of the header checksum, (Process 3) identification of connection by determination of the source-destination port pair of a TCP session, (Process 4) determination of whether the received data is within the volume of the Receive Window from the sequence number and data size of the received packet, (Process 5) reading the ACK field of the received packet, recognizing the status of reverse stream transfer, and preparation for reuse of the data releasing the buffer of the transferred data. In addition, interrupt handling, which is not generally a process mediated by packets, can be executed in advance at the time that the reassembly header51-1arrives at the receiving host10B.

Some conventional methods have been developed to generate the TCP data checksum in network cards which is used as the checksum offload. In the example above, the checksum is assumed to be calculated at the time when the network card receives the packet from the network. Therefore in the above example the protocol processing at the receiving host10B does not include the processing of the checksum. In the case of the conventional method, the checksum result is passed to the host on the transfer of the packet via the network.

The reassembly header advance transfer method of the present embodiment makes the assumption that on transferring packet data to the receiving host10B the checksum result notification is received by the receiving host10B. Alternatively a method in which errors are detected without data transfer by checksum error detection is also acceptable.

FIG. 12shows an example implementation of the reassembly packet header generator41of the network card20. The reassembly packet header generator41comprises, a header checksum determination system41a, a fragment offset determination system41b, a flag determination system41c, a total-length computation system41d, a checksum computation system41e, a higher layer header extraction system41f, a reassembly header constituent memory domain41g, AND circuit41i, and AND circuit41j.

When the last fragment of the IP fragment packet60is provided to the reassembly packet header generator41, the header checksum is determined. The fragment offset determination system41bconfirms that the fragment offset61gis not 0, and the flag determination system41cconfirms that the IP packet is not followed by any fragments.

More specifically, the fragment offset determination system41boutputs 0 when the fragment offset is 0, and 1 when the fragment offset is not 0 as the determination result41b-1.

The flag determination system41coutputs 1 when an IP packet is followed by more fragments, and 0 when an IP packet is not followed by any fragments as the determination result41c-1.

The logically inverted determination result41b-1and the determination result41c-1are provided to the AND circuit41j, which determines whether the packet is the first fragment packet. If the BOOLEAN AND operation results in 1, the packet is determined to be the first fragment packet, and the result is sent to the higher layer header extraction system41f.

The determination result41b-1and logically inverted determination result41c-1are provided to the AND circuit41i, which determines whether the packet is the last fragment packet. If the BOOLEAN AND operation results in 1, the packet is determined to be the last fragment packet, and the result is sent to the total length computation system41d.

When the determination of the last packet fragment is completed by the AND circuit41i, the total length computation system41dis started and a new total length is calculated from the fragment offset61gand packet length61d(total length). The result is reflected in the header of the packet. The checksum computation system41ecalculates and updates the checksum of the header of the packet. The resulting reassembled IP header51is loaded into the reassembly header constituent memory domain41gin the buffer memory22.

When the first fragment packet is provided to the device, after determination of the checksum, the higher layer header extraction system41fis controlled by the flag determination system41c, fragment offset determination system41band the AND circuit41j. Data including the higher layer header (TCP header52in this case) is extracted from the first fragment packet, and loaded into the reassembly header constituent memory domain41g. This part does not have to be exactly the higher layer header, however, it has to include the higher layer header. The two headers in the reassembly header constituent memory domain41gare combined and output as reassembly header51-1.

The explanation of the configuration of the reassembly packet header advance transmitter42in the network cards20is provided below with reference toFIG. 13. This reassembly packet header advance transmitter42is comprised of, for example, a network controller21in the network card20of the transmission side communication controller20A.

The device comprises a memory device42a, which stores the IP packet50received from the transmitting host10A, a fragmented header generator42b, which generates the IP fragment header61after fragmentation, a packet transmitter42c, which forms the IP fragment packet60by combining the generated header and data, and transmits packets via the information network30. An area of the buffer memory22can be used as the memory device42a.

In order to ensure that transmission of the last fragment packet (i.e. the packet, used to generate the reassembly header51-1at the reception side communication controller20B) precedes transmission of the other fragmented packets, the fragmented header generator42bgenerates the last fragment header from the packet header, upon receiving the packet. The fragmented header generator42bsends the header and the address of the data corresponding to the header to the packet transmitter42c. The packet transmitter42crequests the data from the memory device42ausing the acquired address, forms a packet by combining the data with the header and transmits the packet.

An explanation of the implementation of the reassembly packet header duplication transmitter43in the network cards20of the transmission side communication controller20A is provided with reference toFIG. 14. The reassembly packet header duplication transmitter43comprises a memory device43a, which temporarily holds the IP packet50arriving from the transmitting host10A, a fragmented header generator43b, and a packet transmitter43c. The reassembly packet header duplication transmitter43is implemented as a part of the network controller21, for example.

It is not until reception of the entire IP packet50by the transmission side communication controller20A from the transmitting host10A that the above-mentioned reassembly packet header advance transmitter42can start the transmission of a fragment packet (the IP fragment packet60). On the contrary, in the reassembly packet header duplication transmitter43, the fragmented header generator43bgenerates a redundant packet70(a tertiary packet) equivalent to the last IP fragment packet60, which can be used to generate the reassembly header51-1at the reception side communication controller20B at the point that the buffer memory22(the memory device43a) in the transmission side communication controller20A receives the header of the IP packet50before fragmentation. The redundant packet70is sent to the information network30via the packet transmitter43c.

After transmission of the redundant packet70, the fragment packet including the original data is transmitted. The reception side communication controller20B generates the reassembly header51-1on the arrival of the redundant packet70. The packet header71of the redundant packet70transmitted in advance of secondary packets and is implemented in a similar way to that of the IP fragment header61of the last IP fragment packet60of the fragmented packets. To be more specific, the packet header71is generated so as to be the same as the last fragmented packet of the original packet. All of the data72in the redundant packet70is null, set to 0.FIG. 14describes the operation at the point of transmission of the redundant packet70.

The reception side communication controller20B cannot distinguish the advance transmission redundant packet70from the original last fragment packet (the last IP fragment packet60). As a result, the reception side communication controller20B uses the BOOLEAN OR value of the data of both packets (the data53of the IP fragment packet60and the data72of the redundant packet70) as the data of the received packets. In order to reduce the loading of the BOOLEAN OR computation, fragmentation can be adjusted at the transmission side communication controller20A so that the size of the last fragmented packet is made as small as possible. Specifically, the size of the second to last fragmented packet is adjusted so that the last fragmented packet is of a minimum size.

FIG. 15gives an explanation of a reassembly completion notifier44comprised in the network card20, which is the reception side communication controller20B. The reassembly completion notifier44can be implemented as a part of the network controller21.

The reassembly completion notifier44provides a system to provide notification of the completion of packet reassembly by the reception side communication controller20B to the receiving host10B and to help the receiving host10B to check and recognize the reassembly completion of the reception side communication controller20B after the receiving host10B finishes the protocol processing. The receiving host10B, after finishing the protocol processing of the reassembly header51-1, checks the completion of the reassembly processing in the reception side communication controller20B, and on recognizing the completion, transfers the data to the application (User process12b).

The reassembly completion notifier44comprises a reassembly completion system44a, which determines the completion of the reassembly processing in the reception side communication controller20B and a flag writing system44b, which writes the result to a designated notification domain12cin the main memory12of the receiving host10B. The notification domain12cin the main memory12has an entry, which corresponds to a reassembly buffer address (comprised in every reassembly packet) of the buffer memory22in the network card20. The receiving host10B determines whether the reassembly of the IP packet50of the reassembly header51-1is completed or not by calculating the entry of the corresponding notification domain12cfrom the reassembly buffer address transferred with the reassembly header51-1to the receiving host10B.

FIG. 16provides an explanation of the data error detector/notifier45comprised in the network card20as the reception side communication controller20B. The data error detector/notifier45can be implemented as a part of the network controller21. The data error detector/notifier45comprises a packet error determination system45a, flag writing system45band reassembly buffer45c.

In the data error detector/notifier45, the packet error determination system45adetermines the checksum (the IP header checksum and the TCP header checksum) of the packet arriving from the information network30to the reception side communication controller20B. When the packet is a fragment packet (the IP fragment packet60) and has an error, the flag writing system45brecords the error in the notification domain12cof the main memory12in the receiving host10B, corresponding to the reassembly buffer45cstoring the fragment packet. By so doing, the receiving host10B is notified of the reassembly failure.

The data error detector/notifier45can be implemented in combination with the reassembly completion notifier44described above. For example, it can be realized by the bit corresponding to the individual IP packet after reassembly in the notification domain12cbeing changed from 1 bit to 2 bits.

The packet error determination system45acalculates the checksum of the packet data, determining the IP header checksum of the input packet at the same time, and accumulates (sums up) the checksum in a checksum accumulation domain provided for every set of packets to be reassembled. At completion of reassembly, a pseudo-header checksum, for calculation of the TCP checksum from the above checksum, is added. By so doing, the presence or the absence of errors in the data is determined after reassembly. The error notification is set in the notification domain12cwhen the presence of both of the IP header checksum error and the TCP header checksum error.

The explanation of a data timeout detector/notifier46comprised in the network card20as the reception side communication controller20B is given inFIG. 17. The data timeout detector/notifier46can be implemented as a part of the network controller21.

The data timeout detector/notifier46starts a timer on the commencement of reassembly. If a reassembly timeout occurs, the reassembly failure is recorded in the notification domain12cof the receiving host10B.FIG. 17is an example of an implementation, and the example comprises a timeout detection system46a, a flag writing system46band timer counter46c.

The data timeout detector/notifier46can be implemented in combination with the data error detector/notifier45described above, and can share a notification domain12cwith the data error detector/notifier45.

The detection of timeout should be applied to each of a plurality of reassembly processes proceeding in parallel. For that reason, the timeout detection system46acomprises timer counter46cfor each reassembly process. A plurality of timer counter46cfor each reassembly processes are summed up by the output of a timer. On the start of reassembly, 0 bit of the timer counter46cof each reassembly process is cleared. When it reaches a certain value, a timeout trigger is generated. For example, the timer counters46cfor each reassembly process are set as 2-bit counters and they count up when the base one counter (10 bits, for example) are all 1. This setup reduces the number of bits of the timer counter46cfor every reassembly.

An explanation of the data nullification system47comprised in the information processor10as the receiving host10B is provided with reference toFIG. 18. The data nullification system47can be implemented as a part of the Kernel12ain the information processor10.

The data nullification system47comprises a protocol processing program47a, a protocol processing result temporary storage domain47band a protocol processing status setting domain47c.

The data nullification system47is a system to nullify the protocol processing executed in advance in the receiving host10B, when an error is detected by the above data error detector/notifier45or a timeout is detected by the data timeout detector/notifier46.

The protocol processing program47aof the receiving host10B stores the result of the protocol processing in the protocol processing result temporary storage domain47buntil the completion of reassembly in the reception side communication controller20B in carrying out the protocol processing of the reassembly header51-1, and does not reflects the result in the status of protocol processing (the protocol processing status setting domain47c), of the receiving host10B.

On finishing the protocol processing, the protocol processing program47achecks the error and timeout data stored in the notification domain12c. When an error or a timeout is present, it drops the protocol processing result of the reassembly header51-1without reflecting the result in the status. When no error is found, the result is reflected in the protocol processing status setting domain47c.

As explained above, according to the embodiment of the present invention, the transmission delay time caused by the reassembly in the receiving host10B and the reception side communication controller20B is prevented from increasing without negating the load reduction effect of the protocol processing in the transmitting host10A and the receiving host10B by dividing the IP packet50into the IP fragment packet60in the transmission side communication controller20A and by the receiving reassembly processing, which recovers the IP packet50by reassembly of the IP fragment packet60in the reception side communication controller20B.

In addition, both improvement of the throughput and reduction of the transmission delay time allow the effective utilization of the high-speed transfer capabilities of the information network30.

In other words, a high-speed computer network is achieved by the transmitting host10A and the receiving host10B effectively utilizing the information transmission rate of the information network30.

The present invention is not limited to the above-described preferred embodiment. Various changes can be, of course, made without departing from the scope of the invention.

According to the present invention, it is possible to reduce both of the loading of the host computer by the fragmentation and reassembly of the transmitted and received packets, and the transmission delay time of the transmitted and the received packets.

It is also possible to realize both effective utilization of transmission speed of the information network by the fragmentation and reassembly of the transmitted and received packets, and reduction of the transmission delay time of the transmitted and the received packets.