Substrate with strained and relaxed silicon regions

A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer. The silicon device layer has a tensily-strained region overlying the silicon-germanium feature. Regions of the silicon device layer not overlying the silicon-germanium feature are less strained than the tensily-strained region. The tensily-strained region of the silicon device layer may be further processed into channel features in n-type field effect transistors with improved charge carrier mobilities and device drive currents.

BACKGROUND OF THE INVENTION

The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to methods for forming substrates with both strained and relaxed silicon regions, and substrates formed thereby.

The inclusion of strained channels in modern metal-oxide-semiconductor field effect transistor (MOSFET) devices holds the promise of increased charge carrier mobilities and transistor device currents. The performance of an n-type field effect transistor (NFET) is typically improved if its channel includes biaxially strained silicon with tensile strain.

Because of lattice mismatches, tensily strained silicon may be formed by epitaxially growing silicon on relaxed silicon-germanium. Such a technique is, for example, utilized when forming wafers by Strained-Si-Directly-on-Insulator (SSDOI) fabrication methodologies. During SSDOI fabrication, a strained silicon layer is typically grown on a silicon-germanium buffer layer of about 1-2 micrometers thickness. Subsequent processing, which includes wafer bonding to a thermally oxidized handle wafer, provides a wafer entirely covered in a strained silicon layer that overlies a thermal oxide layer.

BRIEF SUMMARY

Embodiments of the invention provide methods for forming semiconductor-on-insulator (SOI) substrates with regions of tensily strained silicon and relaxed silicon. Advantageously, the tensily strained regions may be used to form channel features in NFET devices, allowing those NFETs to benefit from increased charge carrier mobilities and transistor device currents.

Aspects of the invention are directed to a method for forming an integrated circuit. A first trench is formed in a first substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the first substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer with a tensily-strained region overlying the silicon-germanium feature.

Other aspects of the invention, moreover, are directed to an integrated circuit formed using a method comprising the steps set forth in the previous paragraph.

Finally, even additional aspects of the invention are directed to a film stack comprising a substrate, a dielectric layer, and an intact silicon device layer. The dielectric layer overlies the substrate. The intact silicon device layer overlies the dielectric layer and is characterized by a first region that is more tensily strained than a second region.

Techniques according to embodiments of the present invention can provide substantial beneficial technical effects. By way of example only, one or more embodiments may provide advantages including, but not limited to: forming substrates with both strained and relaxed silicon regions, and substrates formed thereby; and improving the performance of an NFET device by including a channel formed having biaxially strained silicon with tensile strain.

DETAILED DESCRIPTION

The present invention will be described with reference to illustrative embodiments. For this reason, numerous modifications can be made to these embodiments and the results will still come within the scope of the invention. No limitations with respect to the specific embodiments described herein are intended or should be inferred.

As the term is used herein and in the appended claims, “about” means within plus or minus ten percent.

FIGS. 1A and 1Bshow a flow diagram of a method100in accordance with an illustrative embodiment of the invention for forming a base structure for use in fabricating a complementary metal-oxide-semiconductor (CMOS) integrated circuit.FIGS. 2-10, in turn, show sectional views of intermediate film stacks formed during the illustrative integrated circuit processing. Although the method100and the structures formed thereby are entirely novel, one or more individual processing steps required to implement the method100may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. Moreover, details of the individual processing steps used to fabricate semiconductor devices described herein may be found in a number of publications, for example, S. Wolf and R. N. Tauber,Silicon Processing for the VLSI Era, Volume1, Lattice Press, 1986; S. Wolf,Silicon Processing for the VLSI Era, Vol.4:Deep-Submicron Process Technology, Lattice Press, 2003; and S. M. Sze,VLSI Technology, Second Edition, McGraw-Hill, 1988, all of which are incorporated by reference herein.

It is also emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to successfully form a functional device. Rather, certain processing steps that are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning steps and annealing steps, are purposefully not described herein for economy of description. However, one skilled in the art will readily recognize those processing steps omitted from this more generalized description.

The exemplary method100starts in step105with the formation of a trench200in a first substrate205. The first substrate205may, for example, be in the form of a silicon wafer. Initially a hard mask layer210is deposited on the first substrate205and patterned using conventional lithography and reactive ion etching (RIE). In one or more embodiments, the hard mask layer210may comprise, for example, silicon nitride. After stripping the photoresist, the hard mask layer210is then used as a mask for etching the trench200via RIE. The resultant film stack is shown inFIG. 2.

Subsequently, in step110, spacer features215are formed on opposed sidewalls of the trench200. The spacer features215may also comprise, for example, silicon nitride. As is common when forming such spacer features, the spacer features215may be formed by depositing the spacer material via chemical vapor deposition (CVD), and then etching the horizontally-oriented regions of spacer material on top of the hard mask layer210and at the bottom of the trench200via an anisotropic etching process such as RIE. The resultant film stack with the spacer features215in place is shown inFIG. 3.

In step115, a silicon-germanium feature220is formed in the trench200. Initially, in a first sub-step, a silicon-germanium layer is formed on the film stack inFIG. 3. Deposition may be by, for example, vapor-phase epitaxial growth in either a multi-wafer or a single-wafer reactor. When using a multi-wafer reactor, any native oxide on the surface of the first substrate205(at the bottom of the trench200) may be initially removed by dipping the wafer in diluted hydrofluoric acid. In addition to removing the native oxide, this wet etch also acts to terminate the surface of the first substrate205in hydrogen. The wafer may then be introduced into the multi-wafer reactor, where it is exposed to silane, germanium, and hydrogen in the milli-torr total pressure range and at about 500-700° C. Single-wafer processing may be performed in a single-wafer reactor with similar processing parameters, but the wet etch to remove the native oxide may be replaced by an in-situ high temperature anneal by rapid thermal processing (RTP) to sublimate that oxide. Single-wafer reactors capable of depositing silicon-germanium are available from, for example, Applied Materials (Santa Clara, Calif., USA).

The just-deposited silicon-germanium layer is preferably overgrown somewhat during its deposition to allow the silicon-germanium layer and ultimately the silicon-germanium feature220to be fully relaxed (i.e., have minimum internal strain). During deposition of the silicon-germanium, the concentration of germanium may be held substantially constant, or, in alternative embodiments, may be graded. The silicon-germanium deposition may, for example, be characterized by a straight or graded germanium concentration profile with a germanium concentration maintained in the 10-40 atomic percent range, although this range is meant to be purely illustrative and is not intended to limit the scope of the invention.

Once deposited, the silicon-germanium may be planarized down to the hard mask layer210by chemical-mechanical polishing (CMP) to yield the film stack shown inFIG. 4, now with the defined silicon-germanium feature220. In combination with this CMP step or in a separate CMP step, moreover, the silicon-germanium feature220, the hard mask layer210, and the tops of the spacer features215may be further polished so that the hard mask layer210is completely removed and the tops of the silicon-germanium feature220and the spacer features215are level with the top of the first substrate205. The resultant film stack is shown inFIG. 5.

Next, in step120, an etch stop layer225is formed on the film stack inFIG. 5. The etch stop layer may comprise, for example, more silicon-germanium. Deposition may again be by vapor-phase epitaxial growth. A silicon device layer230is then deposited on the etch stop layer225, as indicated in step125. Here, processing may occur by depositing by silicon epitaxy at elevated temperature (e.g., above about 600° C.) utilizing a gaseous source of silicon (e.g., silane, silicon tetrachloride, dichlorosilane), and hydrogen as reactants. Doping may also be incorporated by the addition of, for example, a source of phosphorous (e.g., phosphine).

Depositing the silicon device layer230in this manner produces the film stack shown inFIG. 6. Notably, the silicon device layer230includes a tensily-strained region235overlying the silicon-germanium feature220. Because germanium is larger than silicon, a lattice mismatch is present between the newly deposited silicon and the highly-ordered, largely defect-free silicon-germanium immediately underlying it. In contrast, in those regions of the silicon device layer230not overlying the silicon-germanium feature, the silicon device layer230is substantially less strained. The relaxed state of the regions of the silicon device layer230that do not overlie the silicon-germanium feature220occurs because the etch stop layer225is too thin to be highly ordered in these regions, and thus the silicon device layer230does not feel the effect of any underlying silicon-germanium to the extent it does immediately over the silicon-germanium feature220.

The silicon device layer230is thus a mixture of more and less strained regions with the underlying silicon-germanium feature220determining the region of tensile strain. Empirically, it has been determined that trench depths of greater than about 100 nanometers (nm) allow silicon-germanium features220to be grown with sufficient order and lack of defects to produce an overlying tensily-strained region of silicon suitable for processing into strain-enhanced channel features in NFETs. This trench depth is an order of magnitude less than the 1-2 micrometer thicknesses of silicon-germanium buffer layers used in convectional SSDOI processing. In one or more embodiments, when producing 10 nm NFET devices, the widths of the trenches200may be about 480 nm so as to accommodate ten tracks with 48 nm pitch, although this width value is solely by way of illustration and would be very design specific.

The remainder of the processing steps in the method100involve placing the silicon device layer230over a layer of silicon dioxide to, in effect, produce a silicon-on-insulator (SOI) substrate suitable for further CMOS processing into a desired integrated circuit. In step130, hydrogen is implanted into the first substrate205to a depth below the above-identified features to create a narrow layer of hydrogen240, as shown inFIG. 7. Subsequently, in step135, a second substrate245(e.g., silicon) covered in a dielectric layer250(e.g., silicon dioxide) (collectively, a “handle” wafer) is wafer bonded to the top of the film stack inFIG. 7with the dielectric layer250contacting the top of the silicon device layer230. In step140, the first substrate205is broken along the implanted hydrogen layer240by annealing the film stack. The resultant film stack is shown inFIG. 8.

Both the wafer bonding process involved in step135and the breaking of the first substrate via the hydrogen implant/anneal processing involved in steps130and140are common processing steps when forming SOI wafers, and, as a result, will already be familiar to one skilled in the relevant semiconductor processing arts. A process for wafer bonding, moreover, is described in U.S. Pat. No. 4,771,016 to Bajor et al. and entitled “Using rapid thermal process for manufacturing of wafer bonded SOI semiconductor,” which is hereby incorporated by reference herein. Breaking silicon via hydrogen implant/anneal (sometimes called a SMART CUT® process (registered trademark of S.O.I. TEC Silicon on Insulator Technologies Corp. (Bernin, France))) is described in U.S. Pat. No. 5,374,564 to Bruel and entitled “Process for the production of thin semiconductor material films,” which is also hereby incorporated by reference herein.

The above-described breaking of the first substrate in step140acts to reduce the thickness of the first substrate205and, in so doing, helps to facilitate complete removal of the first substrate205in step145. In step145, the remaining portion of the first substrate205is removed by, for example, wet etching selective to the silicon-germanium feature220, the etch stop layer225, and the spacer features215. During this etching, the etch stop layer225stops the silicon device layer230from being impacted, resulting in the film stack shown inFIG. 9. Wet etching may involve, for example, a solution comprising hot (e.g., near 80° C.) tetramethylammonium hydroxide, which can be very selective to silicon-germanium. It is noted that, inFIG. 9, the film stack is flipped vertically with respect to the previous figures to place the dielectric layer250(i.e., buried oxide) under the silicon device layer230, as is conventional when showing SOI substrates.

Finally, in step150, the spacer features215, silicon-germanium feature220, and the etch stop layer225are removed. Again, wet etching may be utilized, with the etching of the silicon-germanium feature220and the etch stop layer225being selective to the silicon device layer230. Silicon-germanium wet etching selective to silicon has been demonstrated with solutions comprising, for example, hydrogen peroxide, hydrofluoric acid, and acetic acid. Alternatively, the silicon-germanium may be removed by rapid thermal processing in an ambient comprising gaseous hydrofluoric acid. The resultant film stack is shown inFIG. 10.

Thus, to summarize, the method100comprises forming the silicon-germanium feature220in the trench200and then forming a silicon device layer230over the silicon-germanium feature220. Because of lattice mismatches, the region of the silicon device layer230overlying the silicon-germanium feature220is tensily strained while other regions that do not overlie the silicon-germanium feature220are substantially less strained (i.e., relaxed). The patterning applied to the trench200thereby ultimately determines the placement and size of the island of strained silicon in the silicon device layer230after additional processing. The tensily-strained region235may subsequently be converted into channel features in NFETs via additional CMOS processing, allowing those NFETs to benefit from increased charge carrier mobilities and transistor device currents.

While an exemplary method of forming a base structure film stack is set forth above, film stacks so formed would also fall within the scope of the invention. An embodiment of the invention may, for example, comprise a silicon substrate topped by a dielectric layer (e.g., silicon dioxide). An intact, as-deposited silicon device layer overlying the dielectric layer may comprise a first region that is more tensily strained than a second region. That is, the intact silicon device layer will have both strained and relaxed regions. Such a film stack is shown in, for example,FIG. 10.

At the same time, it should again be emphasized that the above-described embodiments of the invention are intended to be illustrative only. Other embodiments may, for example, utilize different processing steps from those expressly set forth above to achieve embodiments falling within the scope of the invention.

In one or more embodiments, for example, the method100may be applied without the use of the spacer features215. In so doing, step110may be eliminated, and step150may be modified to only remove the silicon-germanium feature220and the etch stop layer225.

Any element in a claim that does not explicitly state “means for” performing a specified function or “step for” performing a specified function is not to be interpreted as a “means for” or “step for” clause as specified in AIA 35 U.S.C. §112(f). In particular, the use of “steps of” in the claims herein is not intended to invoke the provisions of AIA 35 U.S.C. §112(f).