Semiconductor device with field electrode structures in a cell area and termination structures in an edge area

A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

BACKGROUND

The present application claims priority under 35 USC §119 to German (DE) Patent Application Serial No. DE 10 2014 112 371.9 filed on Aug. 28, 2014. The disclosure in this priority application is hereby incorporated fully by reference into the present application.

BACKGROUND ART

Power semiconductor devices based on IGFET (insulated gate field effect transistor) cells are typically vertical devices with a load current flow between a first surface at a front side of a semiconductor die and a second surface at a rear side. In a blocking mode, stripe-shaped compensation structures extending from the front side into the semiconductor die deplete semiconductor mesas formed between the stripe-shaped compensation structures. The compensation structures allow higher dopant concentrations in the semiconductor mesas without adverse impact on the blocking capability. Higher dopant concentrations in turn reduce the on state resistance of the device. During fabrication, deep compensation structures filled with thick field dielectrics may cause wafer bowing. For tolerable wafer bowing compensation structures may be too shallow for IGFETs specified for high breakdown voltage.

It is desirable to provide semiconductor devices with low ohmic losses and high breakdown voltage.

SUMMARY

According to an embodiment a semiconductor device includes field electrode structures regularly arranged in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

According to another embodiment a semiconductor device includes field electrode structures regularly arranged in a cell area and forming a first regular pattern. Termination structures including termination electrodes are formed in an inner edge area surrounding the cell area and form a second regular pattern congruent with a portion of the first regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. Doped regions directly adjoin the termination structures and form pn junctions with the drift zone in the inner edge area.

According to a further embodiment an electronic assembly includes a semiconductor device including field electrode structures regularly arranged in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

DETAILED DESCRIPTION

The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may be provided between the electrically coupled elements, for example elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.

FIGS. 1A to 1Brefer to a semiconductor device500including a plurality of identical IGFET (insulated gate field effect transistor) cells TC. The semiconductor device500may be or may include an IGFET, for example an MOSFET (metal oxide semiconductor FET) in the usual meaning including FETs with metal gates as well as FETs with non-metal gates. According to another embodiment, the semiconductor device500may be an IGBT.

The semiconductor device500is based on a semiconductor body100from a single crystalline semiconductor material such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs) or any other AIIIBVsemiconductor.

At a front side the semiconductor body100has a first surface101which may be approximately planar or which may be defined by a plane spanned by coplanar surface sections. A planar second surface102extends parallel to the first surface101at an opposite rear side. A distance between the first and second surfaces101,102is a function of the voltage blocking capability and may be at least 20 μm. According to other embodiments, the distance may be in the range of up to, e.g., 250 μm. A lateral surface103, which is tilted to the first and second surfaces101,102connects the first and second surfaces101,102.

In a plane parallel to the first surface101the semiconductor body100may have a rectangular shape with an edge length of several millimeters. A normal to the first surface101defines a vertical direction and directions orthogonal to the vertical direction are horizontal directions.

The transistor cells TC are formed in a cell area610, wherein each transistor cell TC includes a field electrode structure160extending from the first surface101into the semiconductor body100down to a bottom plane BPL. Each field electrode structure160includes a conductive spicular or needle-shaped field electrode165and a field dielectric161surrounding the field electrode165.

The field electrode165includes or consists of a doped polycrystalline silicon layer and/or a metal-containing layer. The field dielectric161separates the field electrode165from the surrounding semiconductor material of the semiconductor body100and may include or consist of a thermally grown silicon oxide layer. According to an embodiment, the field dielectric161may include or consist of a deposited silicon oxide layer, e.g., a silicon oxide layer based on TEOS (tetraethyl orthosilicate).

A vertical extension of the field electrode structures160is smaller than a distance between the first surface101and the second surface102such that a contiguous section CS of the semiconductor body100is formed between the field electrode structures160and the second surface102. The contiguous section CS includes a second portion121bof a drift zone121of a first conductivity type. The vertical extension of the field electrode structures160may be in a range from 0.2 μm to 45 μm, for example in a range from 2 μm to 20 μm.

A first horizontal extension of the field electrode165may be at most three times or at most twice as large as a second horizontal extension orthogonal to the first horizontal extension. The horizontal extensions may be in a range from 0.1 μm to 2 μm, for example in a range from 0.15 μm to 1 μm.

The horizontal cross-sections of the field electrodes165and the field electrode structures160may be ellipses, ovals, rectangles, or regular or distorted polygons, with or without rounded and/or chamfered corners, respectively. According to an embodiment, the first and second horizontal extensions are approximately equal and the horizontal cross-sectionals of the field electrodes165and the field electrode structures160are circles or regular polygons such as octagons, hexagons or squares, with or without rounded or chamfered corners, respectively.

The field electrode structures160, which are centered on a horizontal center point CP of the respective transistor cell TC, are regularly arranged, for example equally spaced. According to an embodiment, equally spaced field electrode structures160are arranged matrix-like in lines and rows in the cell area610. According to other embodiments, the field electrode structures160may be arranged in shifted lines, wherein odd lines are shifted with respect to even lines by half the distance between two neighboring field electrode structures160in the same line. Semiconducting portions of the transistor cells TC are formed in cell mesas170of the semiconductor body100, wherein the cell mesas170protrude from a contiguous section CS of the semiconductor body100, surround the field electrode structures160and form a grid with the field electrode structures160arranged in the meshes.

The cell mesas170include first portions121aof a drift zone121of the first conductivity type, wherein the first portions121adirectly adjoin the second portion121bformed in the contiguous section CS of the semiconductor body100. A dopant concentration in the second portion121bof the drift zone121may be equal to a dopant concentration in the first portion121aof the drift zone121. A mean dopant concentration in a drift zone121including the first and second portions121a,121bmay be between 1E15 cm−3and 1E17 cm−3, for example in a range from 5E15 cm−3to 5E16 cm−3.

Each cell mesa170further includes a body zone115of a second conductivity type opposite to the first conductivity type and one or more source zones110of the first conductivity type. The body zone115separates the source zone(s)110from the first portion121aof the drift zone121in the respective cell mesa170. A gate structure150extends from the first surface101into the cell mesas170. The gate structure150includes a gate electrode155capacitively coupled to the body zones115through a gate dielectric151.

Outer edges of the outermost field electrode structures160define the contour of the cell area610. An edge area690surrounds the cell area610. The edge area690may directly adjoin the lateral surface103. According to other embodiments, the edge area690may directly adjoin a logic portion including logic circuits based, e.g. on lateral transistors. An inner edge area691of the edge area690directly adjoins to and surrounds the cell area610and includes termination structures180.

The termination structures180may consist of at least one of insulating and intrinsic semiconducting materials. According to the illustrated embodiment, at least some of or all termination structures180include a termination electrode185and a termination dielectric181surrounding the termination electrode185, respectively.

The termination electrode185includes or consists of a doped polycrystalline silicon layer and/or a metal-containing layer. The termination dielectric181separates the termination electrode185from the surrounding semiconductor material of the semiconductor body100and may include or consist of a thermally grown silicon oxide layer. According to an embodiment, the termination dielectric181may include or consist of a deposited silicon oxide layer, e.g. a silicon oxide based on TEOS.

The termination and field dielectrics181,161may have the same thickness and the same configuration, e.g., the same layer structure. For example, if both termination and field dielectrics181,161consist of thermally grown semiconductor oxide, e.g. silicon oxide, the thickness of the field dielectrics161may be equal to the thickness of the termination dielectrics181. If the termination and field dielectrics181,161include a deposited oxide layer, the thickness of the deposited oxide layer may be the same in the field and the termination dielectrics161,181.

The vertical extension of the termination structures180is equal to or greater than the vertical extension of the field electrode structures160. A width of the termination structures180may be equal to or greater than a horizontal dimension of the field electrode structures160. Termination structures180and field electrode structures160may have the same horizontal cross-sectional shape and cross-sectional area and may be formed contemporaneously in the same photolithography process.

Center points CP of the termination structures180and the field electrodes structures160may be equally spaced such that the termination structures180and the field electrode structures160complement each other in a regular pattern, wherein center-to-center distances between neighboring termination structures180, between neighboring termination and field electrode structures180,160and between neighboring field electrode structures160are equal. The arrangement of the center points of the termination electrode structures180is congruent to the arrangement of the center points of a portion of the field electrode structures. In other words, the field electrode structures160form a first portion of a regular pattern and the termination structures180form a second portion of the same regular pattern.

An outer edge area699of the edge area690is devoid of termination structures180. The inner edge area691may include, in the same edge mesa190at most two of gate structures150, body zones115and source zones110such that the edge area690does not include functional transistor cells TC. Termination mesas190including first portions121aof the drift zone121separate neighboring termination structures180. The termination mesas190may have the same width as the cell mesas170. The termination mesas190protrude from the contiguous section CS of the semiconductor body100, surround the termination structures180and form a grid complementing the grid formed by the cell mesas170.

One or more doped regions186forming homojunctions with the drift zone121are formed in the inner edge area691of the edge area690between the cell area610and the outermost termination structure180.

Some or all of the doped regions186may be formed in the vertical projection of the termination structures180between the termination structures180and the second surface102. According to other embodiments some or all of the doped regions186may be formed between neighboring termination structures180or between neighboring termination and field electrode structures180,160in the inner edge area691, wherein the buried doped regions186may form unipolar homojunctions or pn junctions with the drift zone121. According to a further embodiment, some or all of the doped regions186may be near-surface doped regions close to or directly adjoining the first surface101in the termination mesas190. The doped regions186may be depletable at operation conditions within the absolute maximum ratings the semiconductor device500is specified for and increase the blocking capability of the semiconductor device500.

The termination structures180increase the blocking capability of the edge area690. By extending the geometry of the cell area610uniform dopant concentrations in corresponding mesas can be achieved even if, e.g., segregation of dopants occurs during thermal oxide growth for forming portions of the field or termination dielectrics161,181thereby simplifying the manufacturing of the semiconductor device500.

The termination structures180may exclusively include spicular or needle-shaped termination structures arranged in two or more rings around the cell area610, one, two or more circumferential termination structures180or a combination of spicular and circumferential termination structures.

FIGS. 2A to 2Crefer to semiconductor devices500with first termination structures180xincluding first portions180athat complement with field electrode structures160and, if applicable, second, spicular termination structures180yin a regular pattern as well as second portions180bconnecting neighboring first portions180a.

InFIG. 2Athe field electrode structures160are arranged in shifted lines, wherein odd lines are shifted with respect to even lines by half the center-to-center distance of the field electrodes160along the line direction. The edge area690includes needle-shaped first termination structures180ccomplementing the pattern of the field electrode structures160. At least one first termination structure180xincludes first portions180acomplementing with the field electrode structures160and spicular second termination structures180yin a regular pattern. Second portions180bof the first termination structure180xare formed between neighboring first portions180a, wherein a distance of the second portions180bto neighboring needle-shaped first termination structures180ais equal to a minimum distance between the first portions180aand the concerned first termination structures180.

The termination electrodes185assigned to the first and second portions180a,180bof the same first termination structure180xare connected to each other, wherein a width of the combined termination electrode185of the second termination structure180xmay vary. The circumferential first termination structure180xsurrounds the cell area610. Between the circumferential first trench structure180xand the cell area610the needle-shaped second termination structures180form one or more staggered rings. The thickness of the field dielectric181of the first termination structure180xis uniform and the same as that of the field dielectrics181of the second termination structures180y.

InFIG. 2Bthe combined termination electrode185in the circumferential first termination structure180xhas the same width in both the first and second portions180a,180b.

In both embodiments ofFIGS. 2A and 2Ban outermost termination mesa190between the first circumferential termination structure180xand the outermost ring of needle-shaped second termination structures180yhas approximately uniform width. In combination with a higher blocking capability in the edge area690than in the cell area610, the uniform width of the outermost termination mesa190may contribute to improved avalanche ruggedness.

FIG. 2Crefers to a circumferential first trench structure180xwith first portions180acomplementing with needle-shaped second termination structures180and field electrode structures160in a regular pattern and second portions180bdirectly connecting neighboring first portions180a. The circumferential first termination structure180xincludes straight sections at least twice as long as a center-to-center distance between neighboring field electrode structures160and surrounds the cell area610and two or more rings of the needle-shaped termination structures180y.

InFIG. 2Ethe horizontal cross-sections of the field electrode structures160and termination structures180are circles. Two rings of needle-shaped termination structures180surround the cell area610.

FIG. 2Frefers to an embodiment with the field and termination structures160,180arranged in lines and stripe-shaped gate structures150between neighboring lines of field electrodes160. Layouts with stripe-shaped gate structures150ofFIG. 2Fmay also be combined with circumferential termination structures180xas illustrated inFIGS. 2A to 2D, by way of example.

FIGS. 3A to 3Brefer to a semiconductor device500with near-surface doped regions186electrically connected to termination electrodes185.

A semiconductor body100as described in detail with reference toFIGS. 1Aand1B includes a drift and rear side structure120of the first conductivity type as well as a contact portion130, which may have the first or the second conductivity type, between the drift and rear side structure120and the second surface102. The drift and rear side structure120includes a drift zone121, in which a dopant concentration may gradually or in steps increase or decrease with increasing distance to the first surface101at least in portions of its vertical extension. According to other embodiments, the dopant concentration in the drift zone121may be approximately uniform. A mean dopant concentration in the drift zone121may be between 1E15 cm−3and 1E17 cm−3, for example in a range from 5E15 cm−3to 5E16 cm−3. The drift and rear side structure120may include further doped zones, for example a field stop layer128that separates the drift zone121from the contact portion130. A mean dopant concentration in the field stop layer128may be at least five times as high as a mean dopant concentration in the drift zone121and at most one-fifth of a maximum dopant concentration in the contact portion130.

The contact portion130may be a heavily doped base substrate or a heavily doped layer. Along the second surface102a dopant concentration in the contact portion130is sufficiently high to form an ohmic contact with a metal directly adjoining the second surface102. In case the semiconductor body100is based on silicon, in an n-conductive contact portion130the dopant concentration along the second surface102may be at least 1E18 cm−3, for example at least 5E19 cm−3, whereas in a p-conductive contact portion130the dopant concentration may be at least 1E18 cm−3, for example at least 5E18 cm−3.

In a cell area610, field electrode structures160extending from a front side down to a bottom plane BPL are regularly arranged at equal distances in lines and columns. According to the illustrated embodiment, the field electrode structures160are arranged matrix-like in lines and columns intersecting the lines at an angle α of 60°. Along the lines and rows, the field electrode structures160are spaced at a distance df. As regards further details of the field electrode structures160reference is made to the detailed description inFIGS. 1A and 1B.

Transistor cells TC are centered on horizontal center points CP of the field electrode structures160. Semiconducting portions of the transistor cells TC are formed in cell mesas170between the field electrode structures160. The cell mesas170include first portions121aof the drift zone121directly adjoining a second portion121bof the drift zone121in a contiguous portion CS of the semiconductor body100between the bottom plane BPL and the second surface102.

Each cell mesa170includes one or more source zones110and a body zone115forming first pn junctions pn1with the source zones110and a second pn junction pn2with the drift zone121.

The source zones110may be wells extending from the first surface101into the semiconductor body100, for example into the body zones115. According to an embodiment, one source zone110surrounds the field electrode structure160of the respective transistor cell TC in a horizontal plane. The source zone(s)110may directly adjoin the respective field electrode structure160or may be spaced from the field electrode structure160. According to other embodiments, the field electrode structure160of the concerned transistor cell TC is not completely surrounded by one source zone110or includes several spatially separated source zones110, which may be arranged rotational symmetric with respect to the center point CP.

The cell area610further includes a gate structure150with a conductive gate electrode155surrounding transistor sections of the transistor cells TC in a horizontal plane, wherein the transistor sections are portions of the cell mesas170including the source and body zones110,115. According to the illustrated embodiment, the gate structure150is spaced from the field electrode structures160. The gate electrode155includes or consists of a heavily doped polycrystalline silicon layer and/or a metal-containing layer.

The gate electrode155is completely insulated against the semiconductor body100, wherein a gate dielectric151separates the gate electrode155at least from the body zone115. The gate dielectric151capacitively couples the gate electrode155to channel portions of the body zones115. The gate dielectric151may include or consist of a semiconductor oxide, for example thermally grown or deposited silicon oxide, semiconductor nitride, for example deposited or thermally grown silicon nitride, a semiconductor oxynitride, for example silicon oxynitride, or a combination thereof.

The gate structure150may be a lateral gate formed outside the semiconductor body100along the first surface101. According to the illustrated embodiment the gate structure150is a trench gate extending from the first surface101into the semiconductor body100, wherein a vertical extension of the gate structure150is smaller than the vertical extension of the field electrode structures160. According to an embodiment, the vertical extension of the gate structure150may be in a range from 200 nm to 2000 nm, for example in a range from 600 nm to 1000 nm.

In the illustrated embodiments and for the following description, the first conductivity type is n-type and the second conductivity type is p-type. Similar considerations as outlined below apply also to embodiments with the first conductivity type being p-type and the second conductivity type being n-type.

When a voltage applied to the gate electrode150exceeds a preset threshold voltage, electrons accumulate in channel portions directly adjoining the gate dielectric151and form inversion channels short-circuiting the second pn junction pn2for electrons.

According to the illustrated embodiment the gate structure150forms a grid which meshes surround the field electrode structures160and portions of the cell mesas170including the source and body zones110,115. According to other embodiments, the gate structure150may directly adjoin to the field electrode structures160.

Portion of the gate structure150may extend into the edge area690, where the gate structure150may include expansions for electrically connecting the gate electrode155with a metal gate electrode at the front side and outside the vertical projection of the cell area610.

An interlayer dielectric210adjoining the first surface101may electrically insulate the gate electrode155from a first load electrode310arranged at the front side. In addition, the interlayer dielectric210may be formed in the vertical projection of the field electrode structures160.

The interlayer dielectric210may include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass), by way of example.

The first load electrode310may form or may be electrically coupled or connected to a first load terminal, for example the source terminal S in case the semiconductor device500is an IGFET. A second load electrode320, which directly adjoins the second surface102and the contact portion130, may form or may be electrically connected to a second load terminal, which may be the drain terminal D in case the semiconductor device500is an IGFET.

Each of the first and second load electrodes310,320may consist of or contain, as main constituent(s), aluminum (Al), copper (Cu), or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to other embodiments, at least one of the first and second load electrodes310,320may contain, as main constituent(s), nickel (Ni), tin (Sn), titanium (Ti), tungsten (W), tantalum (Ta), vanadium (V), silver (Ag), gold (Au), platinum (Pt), and/or palladium (Pd). For example, at least one of the first and second load electrodes310,320may include two or more sub-layers, wherein each sub-layer contains one or more of Ni, Sn, Ti, V, Ag, Au, Pt, W, and Pd as main constituent(s), e.g., a silicide, a nitride and/or an alloy.

Contact structures315extend through openings in the interlayer dielectric210and electrically connect the first load electrode310with the source and body zones110,115as well as with the field electrodes165of the transistor cells TC. The contact structures315bmay include one or more conductive metal containing layers based on, e.g., titanium (Ti) or tantalum (Ta) and a metal fill portion, e.g., based on tungsten (W). According to other embodiments the contact structures315,315binclude heavily doped semiconductor structures, e.g., heavily n-doped polycrystalline structures or heavily p-doped columnar single crystalline structures.

According to other embodiments the field electrodes165may be electrically connected with the gate electrodes155, to a control terminal of the semiconductor device500, to an output of an internal driver circuit, or may electrically float. An edge area690surrounding the cell area610includes termination structures180and termination mesas190as described in detail with regard to the previous Figures.

The termination mesas190include one or more near-surface doped region(s)186electrically connected to the termination electrodes185of neighboring termination structures180averted from the cell area610with respect to the concerned near-surface doped region186. Termination electrodes185electrically connected to the same near-surface doped region186share the same potential.

According to an embodiment, a plurality of near-surface doped regions186are electrically connected to different termination electrodes185, respectively. For example, the near-surface doped regions186may be closer to the cell area610than the termination electrodes185they are connected to. Connecting the termination electrodes185to potentials between the source and the drain potential locally reduces the effective electric field at the respective termination structure180.

The embodiment ofFIG. 3A to 3Bcan be combined with buried doped regions186formed in the vertical projection of at least some of the termination structures180between the bottom plane BPL and the second surface102.

The field electrode structures160allow higher dopant concentrations in the drift zone121without adversely affecting the blocking capability of the semiconductor device500. Compared to stripe-shaped field electrodes the needle-shaped field electrodes165increase the available cross-sectional area for the drift zone121and therefore reduce the on-state resistance RDSon. The near-surface doped regions186as well as the buried doped regions186between the termination structures180and the second surface102increase the voltage blocking capability.

Alternatively or in addition to dot-shaped near-surface doped regions186as illustrated inFIGS. 3A to 3Bthe semiconductor device500ofFIGS. 4A to 4Bincludes stripe-shaped near-surface doped regions186meandering between neighboring rings of termination structures180. Auxiliary contact structures316, which may be formed from heavily doped polycrystalline silicon may extend from the first surface into the termination structures180and the semiconductor body100and electrically connect the near-surface doped regions186to neighboring termination electrodes185.

FIGS. 5A to 5Eare related to further embodiments of the doped regions186that may be combined with any of the layouts depicted inFIGS. 2A to 2F, by way of example.

FIG. 5Aillustrates termination structures180completely formed from insulating material and/or intrinsic semiconducting material. Buried doped regions186are formed in the vertical projection of the termination structures180between the termination structures180and the second surface102. The buried doped regions186may directly adjoin the termination structures180or may be spaced from the termination structures180, form pn junctions with the drift zone121, and may be fully depleted in an operational mode of the semiconductor device500within the maximum ratings of the semiconductor device500. In the illustrated embodiment, a vertical extension of all termination structures180perpendicular to the first surface101is greater than a vertical extension of the field electrode structures160. According to other embodiments, the vertical extension of at least one circumferential termination structure180is greater than the vertical extension of the field electrode structures160.

For further details, reference is made to the description ofFIGS. 1A to 1BandFIGS. 3A to 3B.

InFIG. 5B, the termination structures180include conductive termination electrodes185and field dielectrics181insulating the termination electrodes185against the semiconductor body100. In the illustrated embodiment contact structures315electrically connect the first load electrode310with all termination electrodes185. According to other embodiments, only some of the termination electrodes185are electrically connected to the first load electrode310. Other embodiments may electrically connect some or all of the termination electrodes185to a gate potential applied to the gate electrodes155, to an additional control terminal or to an output of an internal driver circuit. According to further embodiments, some or all of the termination electrodes185may float. The termination electrodes185may be electrically connected to different potentials.

InFIG. 5Cthe termination electrodes185electrically float and are electrically connected to buried doped regions186formed in the vertical projection of the termination structures180between the bottom plane BPL and the second surface102. The buried doped regions186form pn junctions with the drift zone121, extend into the contiguous portions CS, and are spaced from the field stop layer128. The doped regions186may be formed by outdiffusion of dopants from termination electrodes185based on heavily doped polycrystalline silicon.

The semiconductor device500ofFIG. 5Dcombines electrically floating and depletable buried doped regions186formed in the vertical projection of the termination structures180with near-surface doped regions186electrically connected to neighboring termination electrodes185as illustrated inFIGS. 3A-3B and 4A-4B.

FIGS. 5E and 5Fconcern semiconductor devices500with doped regions186formed between neighboring termination structures180, respectively. One, two or more doped regions186may be formed in the respective termination mesa190, wherein the doped regions186may directly adjoin the neighboring termination structures180or may be spaced from the neighboring termination structures180.

InFIG. 5E, the doped regions186have the same conductivity type as the drift zone121and form unipolar homojunctions with the drift zone121. A minimum net dopant concentration in the doped regions186may be at most a half of the mean dopant concentration in the first portions121aof the drift zone121. Boron may be introduced into the doped regions to counterdope the drift zone121.

InFIG. 5Fthe conductivity type of the doped regions186is opposite to that of the drift zone121and the doped regions186form pn junctions with the drift zone121. The maximum net dopant concentration in the counter-doped region186is in a range between 1E15 cm−3and 1E18 cm−3

In the semiconductor device500illustrated inFIG. 5Gfield electrode structures160are regularly arranged in lines in a cell area610. Center points CP of the field electrode structures160form a first regular pattern. Termination structures180are formed in an inner edge area691surrounding the cell area610. Center points CP of the termination structures180form a second regular pattern congruent with a portion of the first regular pattern, wherein center-to-center distances between the termination structures180are equal to center-to-center distances between the field electrode structures160.

Cell mesas170separate neighboring ones of the field electrode structures160from each other in the cell area610and include first portions121aof a drift zone121. Gate structures150including a gate electrode155may extend from the first surface101into the semiconductor body100. A voltage applied to the gate electrode155controls a current flow through the cell mesas170. In the inner edge area691between the cell area610and an outermost termination structure180, doped regions186forming pn junctions with the drift zone121directly adjoin the termination structures180in a vertical projection of the respective termination structure180.

An auxiliary mesa175between the outermost field electrode structures160of the first pattern and the innermost termination structures180of the second pattern is narrower than the cell mesas170to improve the voltage blocking capability.

FIGS. 6A and 6Brefer to layouts with the transistor cells TC and field electrode structures160arranged in shifted lines, wherein the odd lines are shifted to the even lines by one half of the distance between two neighboring transistor cells TC or two neighboring field electrode structures160.

According to the embodiment ofFIG. 6Athe inner contour of a first termination structure180xfollows the contour line of a cell area610including needle-shaped field electrode structures160with octagonal horizontal cross-sections. A width of the termination structure180may vary or may be approximately uniform. As a result, the termination mesa190has long straight sections extending parallel to the lines of field electrode structures160and zigzag sections oriented orthogonal to the long straight sections180y. The edge area690further includes three rings of needle-shaped second termination structures180y.

FIG. 6Brefers to an embodiment with approximately square field electrode structures160and a circumferential first termination structure180xwith rectangular bulges along the inner contour in the projection of the indented lines. The inner contour of the frame-like termination structure180follows a contour of the cell area610approximated by orthogonal lines. According to further embodiments, transitions between orthogonal portions of the termination structure180or transitions to slanted, non-orthogonal sections may be rounded.

FIG. 7refers to an electronic assembly510that may be a motor drive, a switched mode power supply, a primary stage of a switched mode power supply, a synchronous rectifier, a primary stage of a DC-to-AC converter, a secondary stage of a DC-to-AC converter, a primary stage of a DC-to-DC converter, or a portion of a solar power converter, by way of example.

The electronic assembly510may include two identical or different semiconductor devices500as described above. The semiconductor devices500may be IGFETs and the load paths of the two semiconductor devices500are electrically arranged in series between a first supply terminal A and a second supply terminal B. The supply terminals A, B may supply a DC (direct-current) voltage or an AC (alternating-current) voltage. A network node NN between the two semiconductor devices500may be electrically connected to an inductive load, which may be a winding of a transformer or a motor winding, or to a reference potential of an electronic circuit, by way of example. The electronic assembly510may further include a control circuit504that supplies a control signal for alternately switching on and off the semiconductor devices500and a gate driver502controlled by the control circuit504and electrically connected to gate terminals of the semiconductor devices500.

The electronic assembly510may be a motor drive with the semiconductor devices500electrically arranged in a half-bridge configuration, the network node NN electrically connected to a motor winding and the supply terminals A, B supplying a DC voltage.