Selective current pumping to enhance low-voltage ESD clamping using high voltage devices

Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit from an ESD event. The ESD protection device includes first and second trigger elements. Upon detecting an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element, upon detecting the ESD pulse, provides a second trigger signal having a second pulse length. The second pulse length is different from the first pulse length. A primary shunt shunts power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. A current control element selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.

BACKGROUND

An electrostatic discharge (ESD) pulse is a sudden and unexpected voltage and/or current discharge that transfers energy to an electronic device from an outside body, such as from a human body for example. ESD pulses can damage electronic devices, for example by “blowing out” a gate oxide of a transistor in cases of high voltage or by “melting” an active region area of a device in cases of high current, causing junction failure.

As will be appreciated in greater detail below, the present disclosure relates to improved ESD protection techniques.

DETAILED DESCRIPTION

The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.

FIG. 1shows a circuit100that uses ESD protection techniques that are less than ideal. Circuit100includes ESD susceptible circuit102and ESD protection circuit104, both of which are electrically coupled to first and second circuit nodes106A,106B (e.g., DC supply voltage pin and ground pin, respectively, of an integrated circuit.) ESD protection circuit104includes first and second electrical paths108,110which extend in parallel between first and second circuit nodes106A,106B. First electrical path108includes trigger element111arranged thereon, and second electrical path110includes shunt112. Substrate pump114is arranged to pump the substrate of shunt112to enhance its gain during ESD events.

During operation, trigger element116detects a voltage and/or current spike indicative of ESD pulse124, and accordingly increases a voltage of a trigger signal at its output118. This increased voltage puts shunt112and substrate pump114into conductive states. Substrate pump114thus diverts some current of ESD pulse124into the substrate of shunt112via path120, which helps to increase the gain of shunt112. Because of the high-voltage trigger signal, shunt112now represents a low-impedance (relative to ESD susceptible circuit102) and power of ESD pulse124flows over shunt112and away from ESD susceptible circuit102, as shown by arrow122.

Although this technique is sufficient in some respects, ESD protection circuit104suffers from a shortcoming in that shunt112may be unable to adequately shunt large ESD pulses, particularly when low voltage devices are used for circuits102and104. Thus, if a large ESD pulse is impingent, the rapid influx of ESD current may “swamp” shunt112, such that some power from the ESD pulse may reach ESD susceptible circuit102and cause damage. Also, if too much current is channeled through shunt112per unit area, shunt112itself can also be damaged.

Therefore, aspects of the present disclosure relate to ESD protection techniques that still provide substrate pumping to increase gain of a shunt while also allowing increased current shunting relative to conventional approaches. Thus, these techniques provide a reliable protection against ESD pulses, thereby helping to achieve good manufacturing yields and reliable customer performance.

FIG. 2shows an exemplary ESD protection circuit200. ESD protection circuit200includes first, second, third, and fourth electrical paths202,204,206,208, respectively, which extend in parallel between first and second circuit nodes106A,106B. First electrical path202includes first trigger element210, second electrical path204includes second trigger element212, and third electrical path206includes primary shunt214. Fourth electrical path208includes current control element216. During operation, a low-impedance state for primary shunt214is triggered by a first trigger signal from first trigger element210. The current control element216is arranged to selectively act as a substrate pump for primary shunt214based on a second trigger signal from the second trigger element212and to selectively act as a secondary shunt in parallel with the primary shunt214based on the second trigger signal. The first and second trigger signals typically have different pulse lengths and/or have edges that are offset.

In some embodiments, such as the exemplary embodiment shown inFIG. 3, the current control element (e.g.,216inFIG. 2) can be implemented as a current divider302with an control terminal304. When no ESD pulse is present, the first and second trigger elements210,212are off, such that primary shunt214and current divider302both represent high impedance states between first and second circuit nodes106A,106B. Thus, normal operating power flows to the circuit102via first and second circuit nodes106A,106B in the absence of an ESD pulse. When an ESD pulse124is impingent, however, the first and second trigger elements210,212activate first and second trigger signals, which in turn concurrently activate the primary shunt214and the current divider302, respectively. In this state, the current divider302diverts ESD current flowing into terminal302A out of302B to pump substrate of primary shunt214(thereby increasing gain of primary shunt214), and concurrently diverts ESD current flowing into terminal302A out of302C to act as a secondary shunt.

In other embodiments, such as the exemplary embodiment shown inFIG. 4, a current control element (e.g.,216inFIG. 2) can be implemented as a current switch402that either acts as a substrate pump for the primary shunt214or acts as a secondary shunt at any given time, but does not act as both concurrently. When no ESD pulse is present, the first and second trigger elements210,212are again off, such that primary shunt214represents a high impedance state and the current switch402is set to position402B. Due to the high impedance when no ESD pulse is present, normal operating power flows to the circuit102via first and second circuit nodes106A,106B. When an ESD pulse124is impingent, however, the first trigger element210activates the primary shunt214. For part of this impingent ESD pulse124, the second trigger element212remains off such that the current switch402remains set to position402B and thus pumps current due to the ESD pulse124into the substrate of primary shunt214. At some later time in the ESD pulse, the second trigger element212is activated, and the current switch402changes its state to divert current to402C, thereby acting as a secondary shunt that works in parallel with primary shunt214and ceasing substrate pumping of primary shunt214.

FIGS. 5A-5Cillustrate an example where an ESD device500having a current switch502protects against an ESD pulse having a duration of about 150 ns. As shown inFIG. 5A, in the absence of an ESD pulse124, the first and second trigger elements210,212remain off and correspondingly provide low voltages at their respective outputs220,222. These low voltages, which are less than threshold voltages VTHof drain-extended MOS (DeMOS) transistors504,506,508, leave DeMOS transistors504,506,508in non-conducting, high impedance states. Thus, as long as no ESD pulse is present, first through fourth paths202-208represent high-impedance states and normal operating voltages on first and second circuit nodes106A,106B flow substantially un-impeded to the ESD susceptible circuit102. For example, if the first circuit node106A carries a 5-volt DC supply voltage and the second circuit node106B carries a 0-volt DC supply voltage, the ESD susceptible circuit102will see a 5V bias voltage in the absence of an ESD pulse124.

FIG. 5Brepresents ESD protection circuit500shortly after ESD pulse124has been detected by first and second trigger elements210,212. In response to detection of ESD pulse124, the first trigger element210asserts first trigger signal on first output220. The first trigger signal, when asserted, has a voltage level that is higher than the respective threshold voltages of primary pump504(e.g., DeNMOS) and primary shunt508(e.g. DeNMOS). Thus, the first trigger signal puts primary pump504and primary shunt508into conductive states, which tends to shunt ESD current as shown by current path512. For a first time interval when the first trigger signal is asserted, the second trigger signal remains de-asserted. Because of this, secondary pump510is conductive, and current due to ESD pulse is pumped into substrate of primary shunt508to increase its gain.

InFIG. 5C, at some later time in during the ESD pulse124, the second trigger element212is activated, causing the second trigger signal on222to have a voltage level that is higher than the threshold voltage of secondary shunt506. Thus, the second trigger signal puts secondary shunt506into a conductive state, and at the same turns off the secondary pump510. Because secondary shunt506is now conductive, some ESD impingent current is also shunted through secondary shunt506as shown by current path514. In this way, during a first portion of the ESD pulse when the second trigger signal is asserted (e.g., the first approximately 20 ns in this example), substrate pumping occurs (FIG. 5B), and during a second portion of the ESD pulse additional current shunting takes place (FIG. 5C).

FIGS. 6A-6Cshow an ESD protection circuit600where current divider602(e.g., current divider216inFIG. 2) includes secondary shunt604(e.g., DeNMOS) and secondary pump606(e.g., DePMOS), which are operably coupled as shown. InFIG. 6A-6C, inverter608is also included in the current divider602. However, it will be appreciated that in other embodiments, a DePMOS transistor (or other switching elements, such as MOSFETs, BJTs, etc.) could be substituted in secondary shunt604in place of the illustrated DeNMOS transistor, a DeNMOS transistor (or other switching elements, such as MOSFETs, BJTs, etc.) could be substituted in secondary pump606in place of DePMOS transistor, and inverter608need not be present in all embodiments. The same is true of the previous embodiment illustrated inFIGS. 5A-5C. An example where an ESD pulse124is impingent is now described below with regards toFIGS. 6A-6C.

FIG. 6Arepresents ESD protection circuit600prior to the onset of an ESD pulse. Because no ESD pulse is present, first and second trigger elements210,212remain off and correspondingly provide low voltages at their respective outputs220,222. These low voltages, which are less than threshold voltages VTHof primary shunt610and primary pump612, respectively, leave primary shunt610and primary pump612in non-conducting, high impedance states. Thus, as long as no ESD pulse is present, primary shunt610remains in a high-impedance (“off”) state and normal operating voltages on first and second circuit nodes106A,106B flow substantially unimpeded to ESD susceptible circuit102. For example, if first circuit node106A carries a 5-volt DC supply voltage and second circuit node106B carries a 0-volt DC supply voltage, ESD susceptible circuit102will see a 5V bias voltage in the absence of an ESD pulse.

FIG. 6Brepresents ESD protection circuit600shortly after ESD pulse124has been detected by first and second trigger elements210,212. In response to detection of ESD pulse124, first and second trigger elements210,212assert first and second trigger signals, respectively, on first and second outputs220,222, respectively. The first trigger signal at output220, when asserted, has a voltage level that is higher than the respective threshold voltages of primary pump612(e.g., DeNMOS) and primary shunt610(e.g. DeNMOS). Thus, the first trigger signal puts primary pump612and primary shunt610into conductive states, which tends to shunt ESD current as shown by current path614.

Similarly, the second trigger signal at output222, when asserted by second trigger element212, has a voltage level that is higher than the threshold voltages of secondary shunt604, inverter608, and the secondary pump606. Thus, the second trigger signal puts secondary shunt604and secondary pump606into conductive states. InFIG. 6B, some impingent ESD current flows through primary pump612and secondary pump606into substrate of primary shunt610, thereby increasing the gain of primary shunt610and aiding ESD current dissipation along current path614. In addition, when secondary shunt604is also conductive, some ESD impingent current is also shunted through secondary shunt604as shown by current path616. In this way, during a first portion of the ESD pulse when the second trigger signal is asserted (e.g., the first approximately 20 ns in this example), increased current dissipation is enabled relative to conventional approaches. For example, assuming equal size transistors, this embodiment can provide approximately 50% more current handling compared to conventional substrate pump proposals in some implementations.

The second trigger signal at output222often has a different pulse length than the first trigger signal at output220. For example, the pulse length of the second trigger signal is often shorter than the first pulse signal length. In FIG.6C's example (which represents 20-100 ns as measured from the onset of the ESD pulse), the second trigger signal at output222has been de-asserted in that its voltage level has now fallen below the threshold voltages of secondary shunt604and secondary pump606. Therefore, for this second time period in the ESD pulse, secondary shunt604and secondary pump606are now “off”. Therefore, current is no longer injected into the substrate of primary shunt610through secondary pump606, and current is no longer shunted over secondary shunt604as previously illustrated inFIG. 6B. Nevertheless, the ESD current is conducted over the primary shunt element610during this time period.

FIG. 7shows an exemplary illustration of an ESD protection circuit700where capacitor702has been added to help pump the substrate of primary shunt214. The capacitor702can be a discrete, off-chip capacitor or an on-chip capacitor formed in adjacent metal or poly layers of the IC, for example. The capacitor702gets charged during the first 20 ns and will provide the pumping current even after the secondary trigger element has timed-out after 20 ns. In other words, it helps to store charge for pumping over a period of time and supplies charge to the primary pump.

FIG. 8shows an exemplary embodiment of an ESD protection circuit800that makes use of a voltage adder802. In some embodiments, the voltage adder802can be implemented as an op amp that adds two voltages on voltage adder inputs808,810, and which is coupled to the first and second circuit nodes106A,106B. The voltage adder802limits a voltage potential increase on both the substrate of primary shunt214and source of primary pump806due to resistance of the substrate. If left unresolved, this undesired potential build-up can cause biasing issues (e.g., too little biasing) for the primary pump transistor806. To limit this voltage potential increase, during operation trigger element210asserts a trigger signal on804upon detecting a voltage or current spike indicative of an ESD pulse124. To retain an approximately constant gate to source voltage, VGS, for primary pump806, the voltage adder802adds the voltages on voltage adder inputs808,810to increase the adder output voltage provided to gate of primary pump806. In this way, the output voltage of the voltage adder802acts as a stepped-up trigger signal which has a dynamic voltage level that maintains a substantially constant gate-to-source voltage for the pump transistor806throughout an impingent ESD pulse. In other words, the voltage adder802compensates any loss in current in the primary pump806as would be the case for increased source potential.

FIG. 9shows an exemplary method900for ESD protection in accordance with one aspect of the present disclosure.

At step902, method900begins with first trigger element selectively activates a first trigger signal based on detection of the ESD pulse. For example, if an ESD pulse is detected, a voltage of the first trigger signal can be increased for approximately 100 ns to correspond to activation of the first trigger signal. The time for which the first trigger signal is asserted can depend on the size of the ESD pulse, and can vary widely depending on design constraints. Thus, the first trigger signal is in no way limited to a pulse length of 100 ns, but can be significantly longer or shorter depending on the implementation.

At step904, method900continues for the second trigger element to selectively activate a second trigger signal based on detection of the ESD pulse. For example, if an ESD pulse is detected, a voltage of the second trigger signal can be increased for approximately 20 ns to correspond to activation of the second trigger signal. The time for which the second trigger signal is asserted can depend on the size of the ESD pulse, and can vary widely depending on design constraints. Thus, the second trigger pulse is in no way limited to a pulse length of 20 ns, but can be significantly longer or shorter depending on the implementation. The pulse length of the second trigger signal often differs from the first pulse length.

At step906, the primary shunt shunts away the power of the ESD pulse from an ESD susceptible circuit based on the first trigger signal.

At step908, the primary pump selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.

At step910, the secondary shunt shunts away power due to the ESD pulse from the ESD susceptible circuit based on the second trigger signal.

Although several embodiments have been described above with regards to the figures, it will be appreciated that nothing in this description or in these figures limit the scope of the present disclosure in any way. Other embodiments are also contemplated as falling within the scope of the present disclosure. For example, although the illustrated circuits can be implemented as an integrated circuit in some embodiments, they can also be implemented as a combination of discrete components in other embodiments. Further, although some embodiments may describe elements being coupled between first and second circuit nodes (e.g.,106A,106B inFIG. 1-5), the second circuit node106B can in some instances include a plurality of physically distinct nodes that are legally equivalent to a single second circuit node. For example, in FIG.2's embodiment, the second circuit node can correspond to a single IC ground pin that is commonly coupled to first trigger element, second trigger element, shunt element, and current control element. However, in other embodiments, the first trigger element can be coupled to a first IC ground pin, the second trigger element can be coupled to a second IC ground pin that is physically distinct from the first IC ground pin, shunt element can be coupled to a third IC ground pin, and current divider can be coupled to a fourth IC ground pin.

Also, not all illustrated elements are required for all implementations.FIG. 10shows an exemplary embodiment where only one trigger element is employed rather than first and second trigger elements. In this example, the substrate pump includes a DeNMOS1002, and a DePMOS device1004that are operably coupled as shown. Selective current pumping is based on the first trigger signal only.

Thus it will be appreciated that some embodiments relate to an electrostatic discharge (ESD) protection device to protect an ESD susceptible circuit from an ESD pulse. The ESD protection device includes a first trigger element to, upon detecting an ESD pulse, provide a first trigger signal having a first pulse length. The ESD protection device also includes a second trigger element to, upon detecting the ESD pulse, provide a second trigger signal having a second pulse length different from the first pulse length. A shunt is adapted to, based on the first trigger signal, shunt power of the ESD pulse away from the ESD susceptible circuit. A current divider is adapted to, based on the second trigger signal, selectively pump current due to the ESD pulse into a substrate of the shunt.

Other embodiments relate to an ESD protection device to protect an ESD susceptible circuit, which is electrically connected to first and second circuit nodes, from an ESD event. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including a first trigger element arranged thereon. A second electrical path, which includes a second trigger element, extends between the first and second circuit nodes and is in parallel with the first electrical path. A third electrical path also extends between the first and second circuit nodes and is in parallel with the first and second electrical paths. The third electrical path includes a shunt to selectively shunt energy of the ESD event from the first circuit node to the second circuit node based on a first trigger signal from the first trigger element. A fourth electrical path extends between the first and second circuit nodes in parallel with the first and second electrical paths. The fourth electrical path includes a current divider to selectively shunt current from the first circuit node to the second circuit node based on a second trigger signal from the second trigger element.

Still other embodiments relate to an ESD protection circuit including a trigger element configured to assert a trigger signal when an ESD pulse is detected. A shunt element is arranged to shunt power of an impingent ESD pulse based on the trigger signal. A voltage adder provides a stepped-up trigger signal based on the trigger signal. A pump transistor provides a current to a substrate of the shunt based on the stepped-up trigger signal, wherein the stepped-up trigger signal has a dynamic voltage level to keep a gate-to-source voltage applied to the pump transistor substantially constant throughout the ESD pulse.

Another embodiment relates to a method for ESD protection. In the method, a first trigger signal is selectively asserted for first pulse length based on whether an ESD pulse is detected. A second trigger signal is selectively asserted for a second pulse length based on whether the ESD pulse is detected. The second pulse length differs from the first pulse length. Power of the ESD pulse is shunted away from an ESD susceptible circuit via a primary shunt based on the first trigger signal. Current due to the ESD pulse is selectively pumped into a substrate of the primary shunt based on the second trigger signal.