AMPLIFIER WITH PARASITIC CAPACITANCE NEUTRALIZATION

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

BACKGROUND

The present disclosure relates generally to wireless communication, and more specifically to amplifying signals for transmission or reception.

In a wireless communication device, a transmitter and a receiver may each be coupled to at least one antenna to enable the device to transmit and receive wireless (e.g., radio frequency (RF)) signals. For example, a power amplifier (PA) in a transmitter may convert a low-power RF signal to a higher power RF signal to drive the at least one antenna. As another example, a low-noise amplifier (LNA) in a receiver may convert a low-power RF signal to a higher power RF signal without adding excessive noise in order to facilitate retrieval of data in the signal.

However, and particularly for millimeter wave (mmWave) frequency range (e.g., 24.25-300 gigahertz (GHz)) applications, transistors used in the amplifiers may have low gain.

SUMMARY

In one embodiment, an electronic device includes one or more antennas and a transceiver communicatively coupled to the one or more antennas. The transceiver includes amplifiers, each amplifier having a first transistor and a second transistor. Each amplifier also has a third transistor having a gate coupled to a gate of the first transistor, and a drain coupled to a drain of the second transistor. Each amplifier further has a fourth transistor having a gate coupled to a gate of the second transistor, a drain coupled to a drain the first transistor, and a source coupled to a source of the third transistor. The source of the third transistor and the source of the fourth transistor are coupled to a resistive component.

In another embodiment, a transceiver includes multiple amplifiers, each amplifier having a first transistor and a second transistor. Each amplifier also has a first neutralizing transistor having a gate coupled to a gate of the first transistor, and a drain coupled to a drain of the second transistor. Each amplifier further has a second neutralizing transistor having a gate coupled to a gate of the second transistor, a drain coupled to a drain the first transistor, and a source coupled to a source of the first neutralizing transistor. The source of the first neutralizing transistor and the source of the second neutralizing transistor are coupled to a resistor. The transceiver also includes multiple matching networks communicatively coupled to the multiple amplifiers.

In yet another embodiment, amplification circuitry includes a first transistor and a second transistor. The amplification circuitry also includes a first neutralizing transistor having a gate coupled to a gate of the first transistor, and a drain coupled to a drain of the second transistor. The amplification circuitry further includes a second neutralizing transistor having a gate coupled to a gate of the second transistor, a drain coupled to a drain the first transistor, and a source coupled to a source of the first neutralizing transistor. The source of the first neutralizing transistor and the source of the second neutralizing transistor are coupled to a resistor.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Use of the terms “approximately,” “near,” “about,” “close to,” and/or “substantially” should be understood to mean including close to a target (e.g., design, value, amount), such as within a margin of any suitable or contemplatable error (e.g., within 0.1% of a target, within 1% of a target, within 5% of a target, within 10% of a target, within 25% of a target, and so on). Moreover, it should be understood that any exact values, numbers, measurements, and so on, provided herein, are contemplated to include approximations (e.g., within a margin of suitable or contemplatable error) of the exact values, numbers, measurements, and so on.

This disclosure is directed to amplifying signals for transmission or reception by neutralizing parasitic capacitance in transistors. In a wireless communication device, a transmitter and a receiver may each be coupled to at least one antenna to enable the device to transmit and receive wireless (e.g., radio frequency (RF)) signals. For example, a power amplifier (PA) in a transmitter may convert a low-power RF signal to a higher power RF signal to drive the at least one antenna. As another example, a low-noise amplifier (LNA) in a receiver may convert a low-power RF signal to a higher power RF signal without adding excessive noise in order to facilitate retrieval of data in the signal.

However, and particularly for millimeter wave (mmWave) frequency range (e.g., 24 gigahertz (GHz) or higher, 30 GHz or higher, between 24.25 GHz and 300 GHz, and so on) applications, the transistors used in the amplifiers to amplify input signals (“amplification transistors”) may have low gain, unacceptable reverse isolation, and/or instability. In particular, the amplification transistors may exhibit a parasitic capacitance, such as a gate-to-drain capacitance (Cgd), when in use. When employed in amplifiers (e.g., power amplifiers in transmitters, low-noise amplifiers in receivers), this parasitic capacitance may lead to gain loss and/or instability. In some amplifiers, a first capacitor may be used to couple a gate of a first amplification transistor to a drain of a second amplification transistor, and a second capacitor (e.g., of similar size) may be used to couple a gate of the second amplification transistor to a drain of the first amplification transistor, neutralizing parasitic capacitance of the first amplification transistor with capacitance of the first capacitor, and neutralizing parasitic capacitance of the second amplification transistor with capacitance of the second capacitor. However, process variation between manufacturing the first and second capacitors, between the first and second capacitors themselves, and/or of the gate-to-drain capacitance of the amplifiers/wireless communication device (e.g., due to real-world manufacturing imperfections) may decrease the neutralization effect of the capacitors, resulting in at least some parasitic capacitance that may cause a loss in the gain provided by the amplifiers, which may result in worse reverse isolation and instability issues.

As such, disclosed embodiments may include using transistors (e.g., “neutralization transistors”) instead of capacitors to neutralize parasitic capacitance of the transistors of the amplifier. That is, gates of a first amplification transistor and a first neutralization transistor may be coupled together, and gates of a second amplification transistor and a second neutralization transistor may be coupled together. Additionally, drains of the first amplification transistor and the second neutralization transistor may be coupled together, and drains of the second amplification transistor and the first neutralization transistor may be coupled together.

In some amplifiers, a source of the first neutralization transistor may be coupled (or shorted) to a gate of the first amplification transistor, a source of the second neutralization transistor may be coupled (or shorted) to a gate of the second amplification transistor, or the sources of the neutralization transistors may be left open or uncoupled from other components. However, these amplifiers may suffer from charge buildup (e.g., in the neutralization transistors). To avoid the charge buildup, in yet other amplifiers, the sources of the amplification transistors may be coupled to a node (e.g., without any intervening components), which may also be coupled to ground. Moreover, the source of the first neutralization transistor may be coupled in series with a first resistor, the source of the second neutralization transistor may be coupled in series with a second resistor, and both resistors may also be coupled to the node that is coupled to ground. However, these amplifiers may suffer from voltage swings of signals passing through the neutralization transistors at their source, which may result in imperfect neutralization, which may impact gain, reverse isolation and even stability.

The disclosed embodiments include amplifiers that couple the sources of the neutralization transistors together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors. In this manner, gate-to-drain capacitance (Cgd) of the first amplification transistor may be neutralized by Cgdof the first neutralization transistor, and Cgdof the second amplification transistor may be neutralized by Cgdof the second neutralization transistor, while canceling voltage swing at a source of the first neutralization transistor with voltage swing at a source of the second neutralization transistor.

FIG.1is a block diagram of an electronic device10, according to embodiments of the present disclosure. The electronic device10may include, among other things, one or more processors12(collectively referred to herein as a single processor for convenience, which may be implemented in any suitable form of processing circuitry), memory14, nonvolatile storage16, a display18, input structures22, an input/output (I/O) interface24, a network interface26, and a power source29. The various functional blocks shown inFIG.1may include hardware elements (including circuitry), software elements (including machine-executable instructions) or a combination of both hardware and software elements (which may be referred to as logic). The processor12, memory14, the nonvolatile storage16, the display18, the input structures22, the input/output (I/O) interface24, the network interface26, and/or the power source29may each be communicatively coupled directly or indirectly (e.g., through or via another component, a communication bus, a network) to one another to transmit and/or receive data between one another. It should be noted thatFIG.1is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in the electronic device10.

By way of example, the electronic device10may include any suitable computing device, including a desktop or notebook computer (e.g., in the form of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, or Mac Pro® available from Apple Inc. of Cupertino, California), a portable electronic or handheld electronic device such as a wireless electronic device or smartphone (e.g., in the form of a model of an iPhone® available from Apple Inc. of Cupertino, California), a tablet (e.g., in the form of a model of an iPad® available from Apple Inc. of Cupertino, California), a wearable electronic device (e.g., in the form of an Apple Watch® by Apple Inc. of Cupertino, California), and other similar devices. It should be noted that the processor12and other related items inFIG.1may be embodied wholly or in part as software, hardware, or both. Furthermore, the processor12and other related items inFIG.1may be a single contained processing module or may be incorporated wholly or partially within any of the other elements within the electronic device10. The processor12may be implemented with any combination of general-purpose microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate array (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, dedicated hardware finite state machines, or any other suitable entities that may perform calculations or other manipulations of information. The processors12may include one or more application processors, one or more baseband processors, or both, and perform the various functions described herein.

In the electronic device10ofFIG.1, the processor12may be operably coupled with a memory14and a nonvolatile storage16to perform various algorithms. Such programs or instructions executed by the processor12may be stored in any suitable article of manufacture that includes one or more tangible, computer-readable media. The tangible, computer-readable media may include the memory14and/or the nonvolatile storage16, individually or collectively, to store the instructions or routines. The memory14and the nonvolatile storage16may include any suitable articles of manufacture for storing data and executable instructions, such as random-access memory, read-only memory, rewritable flash memory, hard drives, and optical discs. In addition, programs (e.g., an operating system) encoded on such a computer program product may also include instructions that may be executed by the processor12to enable the electronic device10to provide various functionalities.

In certain embodiments, the display18may facilitate users to view images generated on the electronic device10. In some embodiments, the display18may include a touch screen, which may facilitate user interaction with a user interface of the electronic device10. Furthermore, it should be appreciated that, in some embodiments, the display18may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and/or other display technologies.

The input structures22of the electronic device10may enable a user to interact with the electronic device10(e.g., pressing a button to increase or decrease a volume level). The I/O interface24may enable electronic device10to interface with various other electronic devices, as may the network interface26. In some embodiments, the I/O interface24may include an I/O port for a hardwired connection for charging and/or content manipulation using a standard connector and protocol, such as the Lightning connector provided by Apple Inc. of Cupertino, California, a universal serial bus (USB), or other similar connector and protocol. The network interface26may include, for example, one or more interfaces for a personal area network (PAN), such as an ultra-wideband (UWB) or a BLUETOOTH® network, a local area network (LAN) or wireless local area network (WLAN), such as a network employing one of the IEEE 802.11x family of protocols (e.g., WI-FI®), and/or a wide area network (WAN), such as any standards related to the Third Generation Partnership Project (3GPP), including, for example, a 3rdgeneration (3G) cellular network, universal mobile telecommunication system (UMTS), 4thgeneration (4G) cellular network, long term evolution (LTE®) cellular network, long term evolution license assisted access (LTE-LAA) cellular network, 5thgeneration (5G) cellular network, and/or New Radio (NR) cellular network, a satellite network, a non-terrestrial network, and so on. In particular, the network interface26may include, for example, one or more interfaces for using a Release-15 cellular communication standard of the 5G specifications that include the millimeter wave (mmWave) frequency range (e.g., 24.25-300 gigahertz (GHz)) and/or any other cellular communication standard release (e.g., Release-16, Release-17, any future releases) that define and/or enable frequency ranges used for wireless communication. The network interface26of the electronic device10may allow communication over the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, and so forth).

The network interface26may also include one or more interfaces for, for example, broadband fixed wireless access networks (e.g., WIMAX®), mobile broadband Wireless networks (mobile WIMAX®), asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video broadcasting-terrestrial (DVB-T®) network and its extension DVB Handheld (DVB-H®) network, ultra-wideband (UWB) network, alternating current (AC) power lines, and so forth.

As illustrated, the network interface26may include a transceiver30. In some embodiments, all or portions of the transceiver30may be disposed within the processor12. The transceiver30may support transmission and receipt of various wireless signals via one or more antennas, and thus may include a transmitter and a receiver. The power source29of the electronic device10may include any suitable source of power, such as a rechargeable lithium polymer (Lipoly) battery and/or an alternating current (AC) power converter.

FIG.2is a functional diagram of the electronic device10ofFIG.1, according to embodiments of the present disclosure. As illustrated, the processor12, the memory14, the transceiver30, a transmitter52, a receiver54, and/or antennas55(illustrated as55A-55N, collectively referred to as an antenna55) may be communicatively coupled directly or indirectly (e.g., through or via another component, a communication bus, a network) to one another to transmit and/or receive data between one another.

The electronic device10may include the transmitter52and/or the receiver54that respectively enable transmission and reception of data between the electronic device10and an external device via, for example, a network (e.g., including base stations) or a direct connection. As illustrated, the transmitter52and the receiver54may be combined into the transceiver30. The electronic device10may also have one or more antennas55A-55N electrically coupled to the transceiver30. The antennas55A-55N may be configured in an omnidirectional or directional configuration, in a single-beam, dual-beam, or multi-beam arrangement, and so on. Each antenna55may be associated with a one or more beams and various configurations. In some embodiments, multiple antennas of the antennas55A-55N of an antenna group or module may be communicatively coupled a respective transceiver30and each emit radio frequency signals that may constructively and/or destructively combine to form a beam. The electronic device10may include multiple transmitters, multiple receivers, multiple transceivers, and/or multiple antennas as suitable for various communication standards. In some embodiments, the transmitter52and the receiver54may transmit and receive information via other wired or wireline systems or means.

As illustrated, the various components of the electronic device10may be coupled together by a bus system56. The bus system56may include a data bus, for example, as well as a power bus, a control signal bus, and a status signal bus, in addition to the data bus. The components of the electronic device10may be coupled together or accept or provide inputs to each other using some other mechanism.

FIG.3is a schematic diagram of the transmitter52(e.g., transmit circuitry), according to embodiments of the present disclosure. As illustrated, the transmitter52may receive outgoing data60in the form of a digital signal to be transmitted via the one or more antennas55. A digital-to-analog converter (DAC)62of the transmitter52may convert the digital signal to an analog signal, and a modulator64may combine the converted analog signal with a carrier signal to generate a radio wave. A power amplifier (PA)66receives the modulated signal from the modulator64. The power amplifier66may amplify the modulated signal to a suitable level to drive transmission of the signal via the one or more antennas55, and may include amplification circuitry or neutralization topology as described in further detail below. A filter68(e.g., filter circuitry and/or software) of the transmitter52may then remove undesirable noise from the amplified signal to generate transmitted data70to be transmitted via the one or more antennas55. The filter68may include any suitable filter or filters to remove the undesirable noise from the amplified signal, such as a bandpass filter, a bandstop filter, a low pass filter, a high pass filter, and/or a decimation filter. Additionally, the transmitter52may include any suitable additional components not shown, or may not include certain of the illustrated components, such that the transmitter52may transmit the outgoing data60via the one or more antennas55. For example, the transmitter52may include a mixer and/or a digital up converter. As another example, the transmitter52may not include the filter68if the power amplifier66outputs the amplified signal in or approximately in a desired frequency range (such that filtering of the amplified signal may be unnecessary).

FIG.4is a schematic diagram of the receiver54(e.g., receive circuitry), according to embodiments of the present disclosure. As illustrated, the receiver54may receive received data80from the one or more antennas55in the form of an analog signal. A low noise amplifier (LNA)82may amplify the received analog signal to a suitable level for the receiver54to process, and may include amplification circuitry or neutralization topology as described in further detail below. A filter84(e.g., filter circuitry and/or software) may remove undesired noise from the received signal, such as cross-channel interference. The filter84may also remove additional signals received by the one or more antennas55that are at frequencies other than the desired signal. The filter84may include any suitable filter or filters to remove the undesired noise or signals from the received signal, such as a bandpass filter, a bandstop filter, a low pass filter, a high pass filter, and/or a decimation filter. A demodulator86may remove a radio frequency envelope and/or extract a demodulated signal from the filtered signal for processing. An analog-to-digital converter (ADC)88may receive the demodulated analog signal and convert the signal to a digital signal of incoming data90to be further processed by the electronic device10. Additionally, the receiver54may include any suitable additional components not shown, or may not include certain of the illustrated components, such that the receiver54may receive the received data80via the one or more antennas55. For example, the receiver54may include a mixer and/or a digital down converter.

FIG.5is a schematic diagram of a radio frequency (RF) front end98of the transmitter52of the electronic device10, according to embodiments of the present disclosure. As illustrated, the RF front end98may amplify an input signal99by increasing power or a gain of the input signal99through use of amplifiers100. The input signal99may be received from any suitable source, such as the processor12(e.g., as part of an intermediate frequency (IF) processor, a baseband processor, an application processor, and so on). The amplifiers100may include PAs66of the transmitter52, and be coupled to a variety of suitable components or circuitry that facilitate amplification of an input signal, such as filters (which may include filters68of the transmitter52), mixers108, splitters114, phase shifters116, attenuators, matching networks, and so on. In particular, the RF front end98may include a mixer108may mix an input signal with another signal, such as a local oscillation signal110, to output a signal having a desired frequency (e.g., a radio frequency). The RF front end98may also or alternatively include a splitter114that splits an input signal into multiple signals. In some embodiments, such as when implemented in phased array transmitters, the RF front end98may include a phase shifter116to shift a phase of an input signal to a desired phase. An output signal117of the RF front end98may then be sent to one or more antennas55for transmission. It should be understood that the RF front end98is merely an illustrative example of the number of amplifiers100and how the amplifiers100may be distributed in the transmitter52of the electronic device10, and more or fewer components than the ones illustrated are contemplated, and, indeed, the components may be provided in different configurations.

FIG.6is a schematic diagram of RF front end118of the receiver54of the electronic device10, according to embodiments of the present disclosure. As illustrated, the RF front end118may amplify an input signal119received from one or more antennas55by increasing power or a gain of the input signal119through use of amplifiers100. The amplifiers100may include LNAs82of the receiver54, and be coupled to a variety of suitable components or circuitry that facilitate amplification of an input signal, such as filters (which may include filters84of the receiver54), mixers108, combiners120, phase shifters116, attenuators, matching networks, and so on. In particular, the RF front end118may include a phase shifter116to shift a phase of an input signal to a desired phase. The RF front end118may also or alternatively include a combiner120that combines multiple input signals into a single output signal. In some embodiments, the RF front end118may include a mixer108may mix an input signal with another signal, such as a local oscillation signal110, to output a signal having a desired frequency (e.g., a baseband or intermediate frequency). An output signal122of the RF front end118may then be sent to any suitable destination, such as the processor12(e.g., as part of an intermediate frequency (IF) processor, a baseband processor, an application processor, and so on). It should be understood that the RF front end118is merely an illustrative example of the number of amplifiers100and how the amplifiers100may be distributed in the receiver54of the electronic device10, and more or fewer components than the ones illustrated are contemplated, and, indeed, the components may be provided in different configurations.

Each amplifier100shown in the amplifier topologies98,118ofFIGS.5and6may include multiple instances of amplification circuitry, and each instance of amplification circuitry may include multiple transistors (e.g., two transistors), each which may exhibit parasitic capacitance that may lead to gain loss in the amplifier100. With multiple (e.g., two) transistors being in each instance of amplification circuitry, and multiple instances (e.g., four) of amplification circuitry in each amplifier100, it can be seen how even a small gain loss (e.g., on the order of 1 decibel (dB)) may magnify into a significant gain loss overall.

FIG.7is a schematic diagram of a multi-stage amplifier130that may be used in the transmitter52and/or receiver54of the electronic device10, according to embodiments of the present disclosure. As the name suggests, the multi-stage amplifier130may amplify power of an input signal132received at an input terminal133in multiple stages, where each stage corresponds to an amplifier100. As illustrated, a first amplification stage may correspond to a first amplifier100A, and a second amplification stage may correspond to a second amplifier100B. The multi-stage amplifier130may also include matching networks136A,136B,136C (collectively136) that match impedances between unequal input impedances and output impedances. In particular, the matching networks may include an input matching network136A that matches an impedance between the input terminal133and an input of the first amplifier100A, an interstage matching network136B that matches an impedance between an output of the first amplifier100A and an input of the second amplifier100B, and an output matching network136C that matches an impedance between an output of the second amplifier100B and an output terminal137. In some embodiments, the multi-stage amplifier130may also include attenuators that attenuate or reduce an amplitude of the input signal132.

The amplifiers100may each include multiple instances of amplification circuitry138. For example, each amplifier100may have two or more, three or more, four or more, eight or more, and so on, instances of amplification circuitry138. Each amplification circuitry138may be coupled in parallel to one another within each amplifier100, and have a respective switch140to activate (or couple to an operating circuit of the multi-stage amplifier130) each amplification circuitry138. Opening or closing each respective switch140to activate or deactivate each amplification circuitry138may vary the gain for an amplifier100. Enabling each amplification circuitry138to couple to or uncouple from an operating circuit of the multi-stage amplifier130provides tunability, with each independent amplification circuitry138being neutralized internally and separately from other amplification circuitries138.

While specific numbers of amplifiers100, matching networks136, and instances of amplification circuitry138are shown, it should be understood that more or less of these components, as well as additional other components, is contemplated. No matter the exact number of components, as with the amplifier topologies98,118ofFIGS.5and6, because each amplifier100may have multiple amplification circuitries138, and each multi-stage amplifier130may have multiple amplifiers100, the effect of providing better gain and reverse isolation by neutralizing parasitic capacitance of the amplification circuitries138is magnified and impactful to any electronic device10using the multi-stage amplifier130. For example, the gain for each amplification circuitry138may improve by 1.1 dB compared to not using the disclosed amplification circuitry138, which may result in up to almost 9 dB improvement for the multi-stage amplifier130.

FIG.8is a circuit diagram of the amplification circuitry138that may be used in amplifiers100of the electronic device10, including in the transmitter52and/or the receiver54of the electronic device10, according to embodiments of the present disclosure. As illustrated, the amplification circuitry138includes transistors150A,150B (collectively150) that amplify an input signal to the amplification circuitry138. For reference, the transistors150may be referred to as amplification, device, or main transistors150, and may be implemented by any suitable semiconductor device that amplifies electrical signals and power, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or MOS transistors), bipolar transistors, and so on. Each amplification transistor150A,150B may include a gate152A,152B, a source154A,154B, and a drain156A,156B. The amplification circuitry138also includes neutralization transistors158A,158B (collectively158) that respectively neutralize parasitic capacitance (e.g., a gate-to-drain capacitance (Cgd)) of the amplification transistors150A,150B. Like the amplification transistors150, the neutralization transistors158may be implemented by any suitable semiconductor device that amplifies electrical signals and power, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or MOS transistors), bipolar transistors, and so on. The amplification transistors150and the neutralization transistors158may be of similar type. Each neutralization transistor158A,158B may also include a gate160A,160B (collectively160), a source162A,162B (collectively162), and a drain164A,164B (collectively164).

As illustrated, the gate152A of the amplification transistor150A is coupled to the gate160A of the neutralization transistor158A, and the gate152B of the amplification transistor150B is coupled to the gate160B of the neutralization transistor158B. Additionally, the drain156A of the amplification transistor150A is coupled to the drain164B of the neutralization transistor158B, and the drain156B of the amplification transistor150B is coupled to the drain164A of the neutralization transistor158A. The sources162A,162B of the neutralization transistors158A,158B are coupled together (e.g., directly coupled, without any intervening components, such as resistors, between the sources162A,162B) at node166. The node166is also coupled to a resistor168, which is coupled to a node170. The sources154A,154B of the amplification transistors150A,150B are also coupled to the node170, as is a ground172. As explained in more detail below, the amplification circuitry138effectively neutralizes parasitic capacitance (Cgd) of the amplification transistors150, enabling improved gain in the amplification circuitry138.

FIG.9is a schematic diagram of the amplification circuitry138ofFIG.8that illustrates certain operating characteristics, according to embodiments of the present disclosure. When the amplification circuitry138is in operation, the first amplification transistor150A of the amplification circuitry138may operate in a first phase (e.g., a positive phase), and the second amplification transistor150A may operate at a second phase (e.g., a negative phase), or vice versa, such that the amplification circuitry138operates as a differential structure. That is, a first input signal180A to the first amplification transistor150A may be out-of-phase with a second input signal180B to the second amplification transistor150B by 180°. The input signals180A,180B may include complementary portions of a differential mode input signal, and the amplification circuitry138may amplify (e.g., increase power and/or gains of) the input signals180A,180B.

The first input signal180A may cause the first amplification transistor150A to exhibit a first parasitic capacitance182A (e.g., a capacitance from the gate152A of the first amplification transistor150A to the drain156A of the first amplification transistor150A), and the second amplification transistor150B may exhibit a second parasitic capacitance182B (e.g., a capacitance from the gate152B of the second amplification transistor150B to the drain156B of the second amplification transistor150B). It should be understood that the parasitic capacitances182A,182B (collectively182) are not explicit capacitors of the amplification circuitry138, but, instead, capacitances that exists between terminals of circuitry (e.g., of the amplification transistors150) and electronic components of the amplification circuitry138because of their proximity to each other. The parasitic capacitances182may be denoted as Cgd(e.g., a capacitance between a gate and drain of a transistor), and may have a detrimental impact to the amplification transistors150in terms of gain and isolation of output from input. That is, the parasitic capacitances182may cause the amplification transistors150to apply less gain the input signals180A,180B (collectively180), compared to if there were no parasitic capacitance. Moreover, while it may be intended for the amplification transistors150to receive input signals180at their respective gates152A,152B (collectively152) and output signals184A,184B (collectively184) at their respective drains156A,156B (collectively156), the parasitic capacitances182may instead create pathways for the output signals to return from the drains156to the gates152. This feedback or “reverse isolation” may make the amplification circuitry138unstable and worsen performance of the amplification circuitry138.

In some amplifiers, capacitors, which may be implemented using metal layers, are coupled to amplification transistors to neutralize their parasitic capacitances. For example, a first capacitor may be used to couple a gate of a first amplification transistor to a drain of a second amplification transistor, and a second capacitor may be used to couple a gate of the second amplification transistor to a drain of the first amplification transistor, neutralizing gate-to-drain parasitic capacitance (Cgd) of the first amplification transistor with capacitance of the first capacitor, and neutralizing parasitic capacitance of the second amplification transistor with capacitance of the second capacitor. However, operating characteristics of the capacitors may vary excessively (e.g., ±20% capacitance variation) due to real-world manufacturing imperfections. Similarly, the parasitic capacitance of the amplification transistors150may also vary because of manufacturing imperfections. The variation of capacitances of the metal capacitors and variation of the parasitic capacitance of the amplification transistors150may not track each other, meaning that there may be a possibility that a capacitance of a metal capacitor increases while the Cgdof amplification transistor150decreases due to fabrication imperfections. This process variation between manufacturing the first and second capacitors and parasitic capacitance (e.g., Cgd) of the amplification transistors150may result in ineffective neutralization of the parasitic capacitances in the amplifiers, resulting in gain loss provided by the amplifiers and/or rendering the amplifiers unstable.

As such, the capacitors may be replaced with transistors (e.g., the neutralization transistors158), which, because they may be fabricated near the amplification transistors150by following similar or the same fabrication steps with similar or the same processes, may not only better correlate to or match each other in capacitance, but may also track their variations. That is, if Cgdof the amplification transistors150increases, the Cgdof the neutralization transistors158may also increase, and vice versa, reducing or minimizing variation between the amplification transistors150and neutralization transistors158. Thus, the amplification circuitry138enables virtually implementing a capacitor via the neutralizing transistor158(e.g., the neutralizing transistor158acts as a capacitor) that follows the amplification transistor150in terms of process variation, and hence may ensure robust neutralization as Cgdof the amplification transistor150is being neutralized by the Cgdof the neutralization transistor158.

In some amplifiers, a source of the first neutralization transistor may be coupled (or shorted) to a gate of the first amplification transistor, a source of the second neutralization transistor may be coupled (or shorted) to a gate of the second amplification transistor, or the sources of the neutralization transistors may be left open or uncoupled from other components. However, these amplifiers may suffer from charge buildup (e.g., in the neutralization transistors). To avoid the charge buildup, in yet other amplifiers, the sources of the amplification transistors may be coupled to a node (e.g., without any intervening components), which may also be coupled to ground. Moreover, the source of the first neutralization transistor may be coupled in series with a first resistor, the source of the second neutralization transistor may be coupled in series with a second resistor, and both resistors may also be coupled to the node that is coupled to ground. However, these amplifiers may suffer from voltage swings of signals passing through the neutralization transistors at their sources, which may result in imperfect neutralization, which may impact gain, reverse isolation and even stability.

As illustrated inFIG.9, the disclosed amplification circuitry138couples the sources162of the neutralization transistors158together at the node166, such that a voltage swing of the first input signal180A in the first neutralization transistor158A, exiting its source162A, may be canceled by a voltage swing of a second input signal180B in the second neutralization transistor158B, exiting its source162B. That is, because the first and second input signals180may be opposite in polarity in differential mode (e.g., the second input signal180B may be 180° out-of-phase with the first input signal180A), they may be canceled at the node166. Such may not be the case for amplifiers that have intervening components (e.g., resistors) between each source of a respective neutralization transistor and a node coupling the resistors. The node166also couples to a resistive or impedance component, such as resistor168, which prevents charge building in the neutralization transistors158.

It should be understood that, although a resistor is shown, the resistor168may be replaced by any suitable component (e.g., resistive or impedance component) that provides a resistance or impedance, such that it may be considered an open circuit from the viewpoint of the neutralization transistors158, and block all or at least some current flow from the sources162of the neutralization transistors158to the ground172. For example, the resistor168may provide a resistance of 1 ohm (Ω) or greater, 10 Ω or greater, 100 Ω or greater, 1 kiloohm (kΩ) or greater, 10 kΩ or greater, 100 kΩ or greater, 1 megaohm (MΩ) or greater, and so on. This is to prevent a voltage swing at the drain164A of the first neutralization transistor158A from cancelling signals at the coupled drain156B of the (opposite) second amplification transistor150B, since the voltage swing and the signals are 180° out-of-phase with one another. Similarly, the resistor168may also prevent a voltage swing at the drain164B of the second neutralization transistor158B from cancelling signals at the coupled drain156A of the (opposite) first amplification transistor150A. Without the resistor168preventing the voltage swings at the drains164of the neutralization transistors158from cancelling the signals at the coupled drains156of the opposite amplification transistors150, the voltage swings may at least partially cancel gain provided by the amplification circuitry138.

It should be noted that, while an open circuit may also block current flow from the sources162of the neutralization transistors158to the ground172(e.g., in place of the resistor168), it may create charge formulation or buildup in the neutralization transistors158, which may hamper effectiveness of the amplification circuitry138. Additionally, as mentioned above with respect to the multi-stage amplifier130ofFIG.7, the switches140enable adjusting amplification applied by the multi-stage amplifier130by coupling to and engaging amplification circuitries138or uncoupling from and disengaging the amplification circuitries138. In some embodiments, the resistor168may include a variable resistor, which may enable a controller (e.g., including the processor12) to adjust resistance of the resistor168, thus further enabling adjustment of (e.g., enabling finer or more granular adjustment of) amplification applied by the amplification circuitry138.

Moreover, as described in further detail below with respect toFIGS.10-13, because the drains164of the neutralization transistors158are coupled to the drains156of respective opposite amplification transistors150(e.g., the drain164A of the first neutralization transistor158A is coupled drain156B of the second amplification transistor150B, and the drain164B of the second neutralization transistor158B is coupled to the drain156A of the first amplification transistor150A), and the signals at the drains164of the neutralization transistors158are opposite in polarity (e.g., out-of-phase by 180°) compared to the signals at the drains156of the respective opposite amplification transistors150, the signals at the drains164of the neutralization transistors158neutralize or cancel the parasitic capacitances at the opposite amplification transistors150.

FIG.10is a schematic diagram of a representation of the amplification circuitry138ofFIG.8when operating using alternative current (AC), mmWave frequencies, and in differential mode, according to embodiments of the present disclosure. That is, the input signals180A,180B may include AC signals, having frequencies in the mmWave range (e.g., 24.25-300 GHz), and/or include complementary portions of a differential signal. In such cases, from the viewpoint of the amplification transistors150and/or the neutralization transistors158, the node166may act as an AC ground190for the input differential signals180. As a result, any current loading at the node166may be ignored when the amplification circuitry138is in operation.

FIG.11is a schematic diagram of a representation of the amplification circuitry138ofFIG.10showing parasitic capacitances of the neutralization transistors158when operating in differential mode, according to embodiments of the present disclosure. As illustrated, the first neutralization transistor158A may exhibit and be represented by three parasitic capacitances, a first parasitic capacitance200A from the gate160A of the first neutralization transistor158A to the drain164A (which may be referred to as Cgd), a second parasitic capacitance202A from the gate160A to the source162A (which may be referred to as Cgs), and third parasitic capacitance204A from the drain164A to the source162A (which may be referred to as Cds), and a resistance206A. Similarly, the second neutralization transistor158B may exhibit and be represented by three parasitic capacitances, a first parasitic capacitance200B from the gate160B of the second neutralization transistor158B to the drain164B (which may be referred to as Cgd), a second parasitic capacitance202B from the gate160B to the source162B (which may be referred to as Cgs), and third parasitic capacitance204B from the drain164B to the source162B (which may be referred to as Cds), and a resistance206B.

FIG.12is a schematic diagram of a representation of the amplification circuitry138ofFIG.11illustrating how certain parasitic capacitances and resistances of the neutralization transistors158are absorbed or ignored when operating in differential mode, according to embodiments of the present disclosure. As mentioned above with respect to the amplifier topologies98,118ofFIGS.5and6and the multi-stage amplifier130ofFIG.7, each amplifier100may be coupled to one or more impedance matching devices, such as the matching networks ofFIG.7. These matching networks may absorb certain parasitic capacitances of the neutralization transistors158when matching impedances of the neutralization transistors158(e.g., with the drains of the neutralization transistors158).

In particular, the parasitic capacitances202A,202B (collectively202) from the gates160to the sources162(Cgs) of the neutralization transistors158may be absorbed by matching networks coupled to inputs218A,218B (collectively218) of the amplification circuitry138. Similarly, the parasitic capacitances204A,204B (collectively204) from the drains164to the sources162(Cds) of the neutralization transistors158may be absorbed by matching networks coupled to outputs220A,220B (collectively220) of the amplification circuitry138. Furthermore, resistances at the outputs220of the amplification circuitry138(e.g., outputs of the amplification transistors150and/or of the neutralization transistors158) may be much smaller than the resistances206of the neutralization transistors158when the amplification circuitry138operates in differential mode. As such, the resistances206of the neutralization transistors158may be ignored. As illustrated, because the parasitic capacitances202A,202B,204A,204B may be absorbed, and the resistances206may be ignored, only the parasitic capacitances200A,200B (collectively 220030) exhibited by the neutralization transistors158are from the gates160to the drains164(Cgd) of the neutralization transistors158may remain.

FIG.13is a schematic diagram of a representation of the amplification circuitry138ofFIG.11illustrating remaining capacitances after the certain parasitic capacitances and resistances of the neutralization transistors158are absorbed or ignored when operating in differential mode, according to embodiments of the present disclosure. With the parasitic capacitances202from the gates160to the sources162(Cgs) of the neutralization transistors158being absorbed by matching networks coupled to the inputs218of the amplification circuitry138, the parasitic capacitances204from the drains164to the sources162(Cds) of the neutralization transistors158being absorbed by matching networks coupled to the outputs220of the amplification circuitry138, and the resistances206of the neutralization transistors158being ignored due to being much larger (e.g., effectively acting as open circuits) than outputs220of the amplification circuitry138, the remaining parasitic capacitances200A,200B (collectively200) exhibited by the neutralization transistors158are from the gates160to the drains164(Cgd) of the neutralization transistors158.

These parasitic capacitances200may be used to accurately match and neutralize the parasitic capacitances182of the amplification circuitry138, as shown inFIG.9. In particular, the parasitic capacitance200A (Cgd) of the first neutralization transistor158A may neutralize the parasitic capacitance182(Cgd) of the first amplification transistor140A, and the parasitic capacitance200B (Cgd) of the second neutralization transistor158B may neutralize the parasitic capacitance182(Cgd) of the second amplification transistor150B. Advantageously, because the neutralization transistors158may be manufactured using the same process (e.g., same methods, same techniques, same silicon, same wafers, same batches, and so on) as the amplification transistors150, the neutralization transistors158may operate in the same manner or “track” the amplification transistors150. That is, as operating characteristics change (e.g., variations in input signals180, in ambient or environmental conditions), changes in operation of the amplification transistors150may be matched or tracked by the neutralization transistors158. As such, using the neutralization transistors158, as disclosed herein, may provide more effective neutralization than, for example, capacitors that may have significantly more process variation, as the capacitors are made using different processes and/or different materials than the amplification transistors150.

Moreover, when compared to amplifiers having a source of a first neutralization transistor coupled in series with a first resistor, a source of a second neutralization transistor coupled in series with a second resistor, and both resistors being coupled to the node that is coupled to ground, there may be parasitic capacitances associated with these resistors. That is, in addition to the parasitic capacitances from gates to drains (Cgd) of the neutralization transistors, such neutralization transistors also exhibit these parasitic capacitances associated with the resistors. As such, when attempting to neutralize parasitic capacitances of the amplification transistors, not only is the parasitic capacitances from gates to drains (Cgd), gates to sources (Cgs), and drains to sources (Cds) of the neutralization transistors applied, but so are these parasitic capacitances associated with the resistors. While the parasitic capacitances from gates to drains (Cgd) of the neutralization transistors track the operating characteristics of the parasitic capacitances of gates to drains (Cgd) of the amplification transistors, the parasitic capacitances associated with the resistors do not. As such, the parasitic capacitances associated with the resistors may negatively impact neutralization of the parasitic capacitances of the amplification transistors.

This may be avoided in the disclosed embodiments, as they avoid having the source162A of the first neutralization transistor158A coupled in series with a first resistor, the source162B of the second neutralization transistor158B coupled in series with a second resistor, and both resistors being coupled to a node that is coupled to ground. Instead, the sources162of the neutralization transistor158are coupled together (e.g., directly coupled, without any intervening components, such as resistors, between the sources162A,162B) at the node166. The node166is coupled to the resistor168, which is coupled to the node170. The sources154A,154B of the amplification transistors150A,150B are also coupled to the node170, as is a ground172. Coupling the sources162together in this manner (e.g., directly coupling, without any intervening components), and sharing the resistor168, avoids exhibiting such extraneous parasitic capacitances, and enables direct tracking of the parasitic capacitances of gates to drains (Cgd) of the amplification transistors with the parasitic capacitances from gates to drains (Cgd) of the neutralization transistors (e.g., without applying additional parasitic capacitances that may not track the parasitic capacitances of gates to drains (Cgd) of the amplification transistors).

Moreover, the first resistor coupled in series with the source of the first neutralization and second resistor coupled in series with the source of the second neutralization may be excessively lossy (e.g., cause loss in power gain), which may work directly against the purpose of amplifying power in signals. As shown inFIG.11, the disclosed amplification circuitry138does not include such lossy resistors (e.g., which would be coupled between drains164of the neutralization transistors158and the ground172).

FIG.14is a plot illustrating performance of the amplification circuitry138, according to embodiments of the present disclosure. In particular, the plot illustrates maximum gain (Gmax)240and reverse isolation242, both of which may be expressed in decibels, provided by the amplification circuitry138. When neutralization capacitance (Cneut) (e.g., as provided by the neutralization transistors158), which may be expressed in farads, is zero, the Gmax240provided by the amplification circuitry138is low. Cneutshown at244may be an ideal point of operation. This is because, at the Cneutof244, there is high Gmax240, and low reverse isolation242. As discussed above with respect toFIG.9, the reverse isolation242may be caused by the parasitic capacitances182creating feedback paths for the output signals184from the amplification transistors150to return from the drains156to the gates152, thus making the amplification circuitry138unstable and worsening performance of the amplification circuitry138. The Cneutshown at244is the point where the Gmax240is very high (e.g., relative to the range of Gmax240over the range of Cneut), and the reverse isolation242is very low (e.g., minimized relative to the range of reverse isolation242over the range of Cneut, such that the parasitic capacitances182of the amplification transistors150are effectively neutralized).

The plot also illustrates Kf248, which is a stability factor that quantifies stability of the amplification circuitry138, and may be unitless. As shown, at the Cneutshown at244, the Kf248is very high (e.g., maximized relative to the range of Kf248over the range of Cneut). In particular, the Kf248exhibited by the amplification circuitry138may be 1 or greater (e.g., 1.2 or greater, 1.4 or greater, 1.6 or greater, 1.8 or greater, and so on, such as 1.9). Moreover, the Gmax240may be on the order of 15 dB or higher, 17 dB or higher, 20 dB or higher, and so on (e.g., 17.6 dB) at mmWave frequencies (e.g., 24.25-300 GHz, 30-100 GHz, 40-60 GHz, such as 43.5 GHz), while providing reverse isolation242on the order of -40 dB or less, -50 dB or less, -60 dB or less, and so on (e.g., -50.6 dB).

In particular, when compared to amplifiers having a source of a first neutralization transistor coupled in series with a first resistor, a source of a second neutralization transistor coupled in series with a second resistor, and both resistors being coupled to the node that is coupled to ground, amplifiers having the disclosed amplification circuitry138may provide 0.5 dB or greater, 0.75 dB or greater, 1 dB or greater, and so on (e.g., 1.1 dB), greater Gmax240. The amplifiers having the disclosed amplification circuitry138may also provide better reverse isolation than such amplifiers, on the scale of 5 dB better (e.g. less), 10 dB better, 15 dB better, and so on, such as 12.7 dB better (or less).

Keeping in mind that applications using the amplification circuitry138, such as the amplifier topologies98,118ofFIGS.5and6and the multi-stage amplifier130ofFIG.7, may each have multiple instances of amplifiers100, which each may have multiple instances of the amplification circuitry138, any increase in gain and/or reverse isolation, such as an improvement of 1.1 dB in Gmax240and/or an improvement of 12.7 dB in reverse isolation242, is magnified. Indeed, an electronic device10may itself have multiple instances the amplifier topologies98,118ofFIGS.5and6and/or the multi-stage amplifier130ofFIG.7, and the improvement in gain and/or reverse isolation for each amplification circuitry138may be returned on an exponential scale when viewed at the level of the electronic device10.