Display device gate voltage generator outputting a compensation voltage

A display device is provided. A display device comprising, a gate voltage generator outputting a gate-on voltage and a gate-off voltage, a clock generator receiving the gate-on voltage and the gate-off voltage and outputting a clock signal, a gate driver receiving the clock signal and outputting a gate signal, the gate driver including a plurality of stages which are connected to a plurality of gate lines respectively, and a pixel unit comprising a plurality of pixels which are turned on or turned off by the gate signal to display an image, wherein the gate voltage generator comprises, a direct current (DC) converter connected to a sub-gate node and receiving a sub-gate signal which is one of outputs of the plurality of stages gate driver and outputting a compensation voltage using the received sub-gate signal.

This application claims priority from Korean Patent Application No. 10-2014-0137766 filed on Oct. 13, 2014 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present inventive concept relates to a display device and a method of driving the same.

2. Description of the Related Art

Flat panel displays such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs) are being actively developed to replace heavy and large cathode ray tubes (CRTs).

An LCD applies an electric field to a liquid crystal layer interposed between two electrodes which are disposed on display substrates and adjusts the transmittance of light passing through the liquid crystal layer by controlling the intensity of the electric field. Thus, the LCD display displays a desired image. An OLED displays characters or an image using the electroluminescence of particular organic material or polymer.

Of the flat panel displays, an LCD and an OLED each include a pixel unit which includes a plurality of pixels, each having a switch element, and a driving unit which includes various circuits and integrated circuits (ICs) for generating signals needed to drive the pixel unit.

An output voltage of the driving unit varies according to a change in temperature. Thus, the output voltage has to be compensated according to the temperature. In addition, since a low temperature leads to a low driving voltage, the display device may not be driven as intended at the low temperature (seeFIG. 11).

A module for adjusting the output voltage of the driving unit to compensate for the temperature change of the driving unit according to the conventional method has a temperature compensation circuit on a printed circuit board (PCB)800. The temperature compensation circuit in the PCB800cannot reflect the temperature change on the LCD panel which is influence by the temperature change. Therefore, the module may be unable to reflect temperature changes in the LCD panel. As a result, the output voltage of the driving unit may be adjusted inaccurately (seeFIGS. 12 and 13).

SUMMARY

Aspects of the present inventive concept provide a display device including a driving unit which can output a signal at a constant voltage level despite a temperature change of the display device.

Aspects of the present inventive concept also provide a method of driving a display device including a driving unit which can output a signal at a constant voltage level despite a temperature change of the display device.

However, aspects of the present inventive concept are not restricted to the one set forth herein. The above and other aspects of the present inventive concept will become more apparent to one of ordinary skill in the art to which the present inventive concept pertains by referencing the detailed description of the present inventive concept given below.

According to an aspect of the present inventive concept, there is provided a display device including a gate voltage generator outputting a gate-on voltage and a gate-off voltage, a clock generator receiving the gate-on voltage and the gate-off voltage and outputting a clock signal, a gate driver receiving the clock signal and outputting a gate signal, the gate driver including a plurality of stages which are connected to a plurality of gate lines respectively, and a pixel unit comprising a plurality of pixels which are turned on or turned off by the gate signal to display an image. The gate voltage generator includes a direct current (DC) converter connected to a sub-gate node and receiving a sub-gate signal which is one of outputs of the plurality of stages and outputting a compensation voltage using the received sub-gate signal.

The gate voltage generator may further include a charge pump connected to the DC converter and generating a gate on voltage and a gate off voltage using the compensation voltage.

The DC converter may include a detection unit connected to the sub-gate node and measuring a difference between an on-level voltage and an off-level voltage of the received sub-gate signal, a comparison unit connected to the detection unit and comparing a preset reference voltage with the difference between the on-level voltage and the off-level voltage of the sub-gate signal, a switch unit connected between the comparison unit and an output node, the switch unit including a switch and a switch controller which controls the switch using a comparison result of the comparison unit, and an inductor connected between an input node and the output node.

If the difference between the on-level voltage and the off-level voltage of the sub-gate signal is smaller than the preset reference voltage, the DC converter may output the compensation voltage that causes an on-level voltage of the sub-gate signal having a greater value than the on-level voltage of a previous sub-gate signal.

If the difference between the on-level voltage and the off-level voltage of the sub-gate signal is smaller than the preset reference voltage, the DC converter may output the compensation voltage that causes an off level voltage of the sub-gate signal having a smaller value than the off-level voltage of a previous sub-gate signal.

If the difference between the on-level voltage and the off-level voltage of the sub-gate signal is greater than the preset reference voltage, the DC converter may output the compensation voltage that causes an on-level voltage of the sub-gate signal having a smaller value than the on-level voltage of a previous sub-gate signal.

If the difference between the on-level voltage and the off-level voltage of the sub-gate signal is greater than the preset reference voltage, the DC converter may output the compensation voltage that causes an off-level voltage of the sub-gate signal having a greater value than the off level voltage of a previous sub-gate signal.

The a plurality of stages may sequentially output the gate signal, each of the stages including at least one amorphous silicon thin-film transistor, and the gate driver further comprises a dummy stage which outputs the sub-gate signal that is provided to the gate voltage generator.

The sub-gate signal may be provided from the last stage.

The switch unit may accumulate a plurality of comparison results received from the comparison unit and controls the operation of the switch using the accumulated comparison results.

The DC converter may further include a slope compensation unit.

The DC converter may output a plurality of compensation voltages.

According to another aspect of the present inventive concept, there is provided a method of driving a display device, the method includes providing a sub-gate signal, which is one of outputs of a gate driver, to a DC converter, generating a compensation voltage using the sub-gate signal, generating a gate-on voltage and a gate-off voltage using the compensation voltage, generating a clock signal using the gate-on voltage and the gate-off voltage, and generating a modified gate signal using the clock signal.

The generating the compensation voltage may include measuring a difference between an on-level voltage and an off-level voltage of the sub-gate signal, comparing a preset reference voltage with the difference between the on-level voltage and the off-level voltage of the sub-gate signal, and controlling a switch to reduce a difference between the gate-on/off voltage difference and the reference voltage.

DETAILED DESCRIPTION

A display device according to an embodiment of the present inventive concept will now be described in detail with reference toFIGS. 1 and 2. While a liquid crystal display (LCD) will be described as an example, the display device according to the embodiment of the present inventive concept is not limited to the LCD. The present inventive concept can also be applied to other types of display devices such as an organic light-emitting diode display (OLED).

FIG. 1is a block diagram of an LCD according to an embodiment of the present inventive concept.

Referring toFIG. 1, the LCD according to the current embodiment includes a gate voltage generator100, a clock generator200, a gate driver300, a timing controller400, a data driver500, and a liquid crystal panel600.

The liquid crystal panel600may include a display area DA where images are displayed and a non-display area PA where no images are displayed.

The display area DA includes a plurality of gate lines G1through Gn, a plurality of data lines D1through Dm, and a plurality of pixels601. The gate lines G1through Gnmay extend in a substantially row direction to be parallel to each other, and the data lines D1through Dmmay extend in a substantially column direction to be parallel to each other. The pixels601will be described later with reference toFIG. 2.

The non-display area PA is where no images are displayed. A first substrate720may be formed wider than a second substrate730, and the non-display area PA may be provided in a portion of the first substrate720which does not overlap the second substrate730. The gate driver300may be directly formed on the first substrate in the non-display area PA or mounted on the first substrate in the non-display area PA as an IC chip.

The gate voltage generator100may generate a gate-on voltage Vonand a gate-off voltage Voffand provide the gate-on voltage Vonand the gate-off voltage Voffto the clock generator200. In addition, the gate voltage generator100may receive a sub-gate signal Gsubfrom the gate driver300. The gate voltage generator100will be described in detail later with reference toFIGS. 3 through 5.

The timing controller400may receive input image signals R, G and B from an external graphics controller (not shown) and input control signals for controlling the display of the input image signals R, G and B. Examples of the input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal Mclk, and a data enable signal DE.

The timing controller400generates a data control signal CONT based on the input image signals R, G and B and the input control signals, and sends the data control signal CONT and an image data signal DAT to the data driver500.

The timing controller400provides a first clock generation control signal OE, a second clock generation control signal CPV, and an original scan start signal STV to the clock generator200. Here, the first clock generation control signal OE may enable gate signals Gout(1)through Gout(n), and the second clock generation control signal CPV may determine a duty ratio of each of the gate signals Gout(1)through Gout(n). The original scan start signal STV may indicate the start of a frame.

In response to the first clock generation control signal OE, the second clock generation control signal CPV, and the original scan start signal STV, the clock generator200outputs a clock signal CKV, a clock bar signal CKVB, the gate-off voltage Voffand scan start signal STVP to the gate driver300. Here, the clock signal CKV and the clock bar signal CKVB may swing between the gate-on voltage Vonand the gate-off voltage Voffand may have different phases.

The clock generator200converts the original scan start signal STV into a scan start signal STVP and provides the scan start signal STVP to the gate driver300. The scan start signal STVP is obtained by increasing the amplitude of the original scan start signal STV.

The gate driver300is enabled by the scan start signal STVP to generate a plurality of gate signals Gout(1)through Gout(n)using the clock signal CKV, the clock bar signal CKVB and the gate-off voltage Voff, and sequentially transmit the gate signals Gout(1)through Gout(n)to the gate lines G1through Gn, respectively.

The data driver500receives the image data signal DAT and the data control signal CONT from the timing controller400and provides an image data voltage corresponding to the image data signal DAT to each of the data lines D1through Dm. The data control signal CONT is used to control the operation of the data driver500and includes a horizontal start signal (not shown) for starting the operation of the data driver500and a load signal (not shown) for instructing the output of two data voltages.

The data driver500may be mounted, as an integrated circuit (IC), on the liquid crystal panel600in the form of a tape carrier package (TCP). However, the present inventive concept is not limited thereto, and the data driver500may also be directly formed on the non-display region PA of the liquid crystal panel600.

A further detailed description of the gate driver300will be given later with reference toFIGS. 9 and 10.

FIG. 2is an equivalent circuit diagram of one pixel601of the LCD ofFIG. 1.

Referring toFIG. 2, one pixel601ofFIG. 1includes the first substrate720having a switch element Qpxand a pixel electrode PE, the second substrate730having a color filter CF and a common electrode CE, and liquid crystal molecules710interposed between the first substrate720and the second substrate730. The color filter CF may be formed in a portion of the common electrode CE of the second substrate730to face the pixel electrode PE of the first substrate720.

In addition, a pixel601connected to an ith(i=one of 1 to n) gate line Giand a jth(j=one of 1 to m) data line Djmay include the switch element Qpx, which is connected to the ithgate line Giand the jthdata line Dj, and a liquid crystal capacitor Clcand a storage capacitor Cstwhich are connected to the switch element Qpx. The storage capacitor Cstcan be omitted if necessary. The switch element Qpxmay be a thin-film transistor made of amorphous silicon as an active layer.

FIG. 3is a block diagram of a gate voltage generator100according to an embodiment of the present inventive concept.

Referring toFIG. 3, the gate voltage generator100may include a direct current (DC) converter110and a charge pump120.

The DC converter110receives an input voltage Vinand a sub-gate signal Gsuband provides a compensation voltage Vcpto the charge pump120. In addition, the DC converter110may adjust the compensation voltage Vcpaccording to a change in temperature inside or outside the display device. An example of the DC converter110may be a DC-DC converter, and other types of converters can also be employed.

The charge pump120receives the compensation voltage Vcpfrom the DC converter110and outputs a gate-on voltage Vonand a gate-off voltage Voffusing the compensation voltage Vcp. Some circuits used in the display device may require a higher voltage than a power supply voltage due to their operation characteristics. Therefore, the charge pump120may be used to stably step up the power supply voltage to a higher voltage.

FIG. 4is a block diagram of a gate voltage generator100according to another embodiment of the present inventive concept.

Referring toFIG. 4, a DC converter110of the gate voltage generator100according to the current embodiment may output a first compensation voltage Vcp1and a second compensation voltage Vcp2. However, the present inventive concept is not limited thereto, and the DC converter110may also output a greater number of compensation voltages. Since other components of the gate voltage generator100have already been described above with reference toFIG. 3, a description thereof will be omitted.

FIG. 5is a block diagram of a gate voltage generator100according to another embodiment of the present inventive concept.

Referring toFIG. 5, the gate voltage generator100according to the current embodiment may include a first DC converter110-1, a second DC converter110-2, a first charge pump121, and a second charge pump122. The first DC converter110-1may receive an input voltage Vinand a sub-gate signal Gsuband output a first compensation voltage Vcp1. The first compensation voltage Vcp1may be provided to the first charge pump121. The first charge pump121may receive the first compensation voltage Vcp1and output a gate-on voltage Von. The second DC converter110-2may receive an input voltage Vinand a sub-gate signal Gsuband output a second compensation voltage Vcp2. The second compensation voltage Vcp2may be provided to the second charge pump122. The second charge pump122may receive the second compensation voltage Vcp2and output a gate-off voltage Voff.

However, the present inventive concept is not limited thereto, and more DC converters and more charge pumps can be included. In the current embodiment, the first and second charge pumps121and122are included in the gate voltage generator100, together with the first and second DC converters110-1and110-2. However, the present inventive concept is not limited thereto, and the first and second charge pumps121and122may also form a separate module, and the module may be formed or mounted within the display device. Since other components have been described above with reference toFIG. 3, a description thereof will be omitted.

FIG. 6is a circuit diagram of a DC converter110according to an embodiment of the present inventive concept.

Referring toFIG. 6, the DC converter110receives an input voltage Vinand a sub-gate signal Gsuband outputs a compensation voltage Vcpusing the input voltage Vinand the sub-gate signal Gsub. Here, the input voltage Vinis a voltage applied to drive the voltage generator. The input voltage Vinmay be received from an external power source (not shown). The sub-gate signal Gsubmay be one of the gate signals Gout(1)through Gout(n)output from the gate driver300. This will be described in greater detail later with reference toFIGS. 9 and 10.

The DC converter110may include a detection unit111, a comparison unit112, and a switch unit113.

The detection unit111may detect a difference between an on-level voltage and an off-level voltage (hereinafter, referred to as a ‘gate-on/off voltage difference’) of the sub-gate signal Gsuband provide the detected gate-on/off voltage difference to the comparison unit112.

The comparison unit112may compare the gate-on/off voltage difference with a reference voltage Vrefand output a difference between the gate-on/off voltage difference and the reference voltage Vref. The comparison unit112may include a non-inverting input terminal (+) and an inverting input terminal (−). The gate-on/off voltage difference may be input to the non-inverting input terminal (+), and the reference voltage Vrefmay be input to the inverting input terminal (−). The difference output from the comparison unit112may be provided to the switch unit113.

The switch unit113may receive the difference from the comparison unit112and switch the circuit such that the compensation voltage Vcpcan be generated. The switch unit113may include a switch controller114and a switch115. The switch controller114may receive the difference from the comparison unit112and control the operation of the switch115based on the difference. Controlling the operation of the switch115will be described later with reference toFIG. 7.

The switch controller114is connected to a control terminal of the switch115, thereby controlling the operation of the switch115. Another terminal of the switch115is connected to a node connecting an inductor L and a diode D1, and the other terminal of the switch115is connected to a ground. A reverse diode is connected between the node connecting the inductor L and the diode D1, and the ground. The ground may also be a node to which a predetermined voltage is applied.

In the current embodiment, the switch115is a metal oxide semiconductor field effect transistor (MOSFET) and the control terminal is a gate of the MOSFET. However, the present inventive concept is not limited thereto, and other electronic elements capable of functioning as the switch115can also be used.

The DC converter110may generate the compensation voltage Vcpas follows. When the MOSFET of the switch unit113is on, an electric current may flow from a node to which the input voltage Vinis applied to the ground node via the inductor L. During the electric current flow through the inductor L, energy is stored temporarily in a magnetic field in the inductor L. Here, if the switch115of the switch unit113is turned off, the current flows through the inductor L is changed, thus, a time-varying magnetic field induces a high voltage in the inductor L, thereby output voltage of the DC converter is changed to the compensation voltage Vcp. By repeating the above process, the desired compensation voltage Vcpcan be obtained. A value of the output compensation voltage Vcpmay be adjusted according to the on/off cycle of the switch115.

FIG. 7is a flowchart illustrating a method by which the DC converter110of outputs the compensation voltage Vcpaccording to an embodiment of the present inventive concept. Referring toFIG. 7, the DC converter110may receive a sub-gate signal Gsuband measure a gate-on/off voltage difference of the received sub-gate signal Gsub. The measured gate-on/off voltage difference of the sub-gate signal Gsubmay be compared with a reference voltage Vref. Here, the reference voltage Vrefmay be equal to a value of a gate signal that can be output from the gate driver300in an ideal condition unaffected by a change in temperature inside or outside the display device.

If a comparison result of the comparison unit112indicates that a difference between the gate-on/off voltage difference and the reference voltage Vrefis zero, a value of the compensation voltage Vcpmay be output as it is without additional manipulation of the switch controller114. If the comparison result of the comparison unit112indicates that the difference between the gate-on/off voltage difference and the reference voltage Vrefis not zero, the on/off cycle of the switch115may be changed by manipulating the switch controller114in order to reduce a difference between the gate-on/off voltage difference and the reference voltage by change the value of the compensation voltage Vcp.

Specifically, if the comparison result of the comparison unit112indicates that the gate-on/off voltage difference of the sub-gate signal Gsubis smaller than the reference voltage Vref, the switch unit113may operate in such a way to cause an on-level voltage of the sub-gate signal Gsubhaving a greater value than an on-level voltage of pre-outputted the sub-gate signal Gsubto be generated. In other words, the switch controller114may increase the value of the compensation voltage Vcpused to generate a gate-on voltage Vonby changing the on/off cycle of the switch115.

If the comparison result of the comparison unit112indicates that the gate-on/off voltage difference of the sub-gate signal Gsubis smaller than the reference voltage Vref, the switch unit113may operate in such a way to cause an off-level voltage of the sub-gate signal Gsubhaving a smaller value than an off-level voltage of pre-outputted the sub-gate signal Gsubto be generated. In other words, the switch controller114may decrease the value of the compensation voltage Vcpused to generate a gate-off voltage Voffby changing the on/off cycle of the switch115.

In addition, if the comparison result of the comparison unit112indicates that the gate-on/off voltage difference of the sub-gate signal Gsubis greater than the reference voltage Vref, the switch unit113may operate in such a way to cause an on-level voltage of the sub-gate signal Gsubhaving a smaller value than the on-level voltage of pre-outputted the sub-gate signal Gsubto be generated. In other words, the switch controller114may decrease the value of the compensation voltage Vcpused to generate the gate-on voltage Vonby changing the on/off cycle of the switch115.

If the comparison result of the comparison unit112indicates that the gate-on/off voltage difference of the sub-gate signal Gsubis greater than the reference voltage Vref, the switch unit113may operate in such a way to cause an off-level voltage of the sub-gate signal Gsubhaving a greater value than the off-level voltage of pre-outputted the sub-gate signal Gsubto be generated. In other words, the switch controller114may increase the value of the compensation voltage Vcpused to generate the gate-off voltage Voffby changing the on/off cycle of the switch115.

In addition, the switch unit113may change the compensation voltage Vcpby a preset amount or gradually. For example, the preset amount by which the compensation voltage Vcpis changed may be 0.1 V. In this case, if the comparison result of the comparison unit112indicates that the difference between the on-level voltage and the off-level voltage of the sub-gate signal Gsubis greater than the reference voltage Vrefand if the gate-on voltage Vonshould be adjusted, the value of the compensation voltage Vcpused to generate the gate-on voltage Vonmay be decreased by 0.1 V by adjusting the on/off cycle of the switch115. Accordingly, the value of the gate-on voltage Vonmay also be decreased. Finally, a sub-gate signal Gsubgenerated according to the decreased value of the gate-on voltage Vonmay be fed back to the DC converter110. The above process may be repeated until an ideal sub-gate signal Gsubis output.

In the above example, the preset amount by which the compensation voltage Vcpis changed is 0.1 V. However, the present inventive concept is not limited thereto, and the preset amount can have a different value. The compensation voltage Vcpcan also be changed by a different amount in each process of outputting the compensation voltage Vcp. For example, if the comparison result of the comparison unit112indicates that the gate-on/off voltage difference of the sub-gate signal Gsubis relatively large, the compensation voltage Vcpmay also be changed by a relatively large amount. If the comparison result of the comparison unit112indicates that the gate-on/off voltage difference of the sub-gate signal Gsubis relatively small, the compensation voltage Vcpmay also be changed by a relatively small amount.

In addition, the switch unit113may accumulate a plurality of comparison results received from the comparison unit112and change the compensation voltage Vcpusing the accumulated comparison results. In this way, the speed at which the compensation voltage Vcpand the sub-gate signal Gsubare changed can be adjusted.

FIG. 8is a circuit diagram of a DC converter110according to another embodiment of the present inventive concept.

Referring toFIG. 8, the DC converter110receives an input voltage Vinand a sub-gate signal Gsuband outputs a compensation voltage Vcpusing the input voltage Vinand the sub-gate signal Gsub. Unlike in the embodiment ofFIG. 6, in the current embodiment, a detection result of a detection unit111may be input to a comparison unit112via a slope compensation unit117. The slope compensation unit117may keep the circuit stable by preventing the circuit from becoming unstable depending on the waveform of a signal output from the detection unit111. Since each component of the DC converter110excluding the slope compensation unit117has been described above with reference toFIG. 6, a description thereof will be omitted.

FIG. 9is a block diagram of a gate driver300according to an embodiment of the present inventive concept.

Referring toFIG. 9, the gate driver300is enabled by a scan start signal STVP to generate a plurality of gate signals Gout(1)through Gout(n)using a clock signal CKV, a clock bar signal CKVB and a gate-off voltage Voff, and sequentially provide the gate signals Gout(1)through Gout(n)to a plurality of gate lines G1through Gn, respectively.

More specifically, the gate driver300includes a plurality of stages ST1through STn. The stages ST1through STnare connected in a cascade manner. The stages ST1through STnare connected to the respective gate lines G1through Gnand output the gate signals Gout(1)through Gout(n)to the gate lines G1through Gn, respectively. The gate-off voltage Voff, the clock signal CKV, the clock bar signal CKVB, and an initialization signal INT are input to each of the stages ST1through STn. The initialization signal INT may be provided by the clock generator200.

Each of the stages ST1through STnmay have a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a power source terminal GV, a frame reset terminal FR, a gate output terminal OUT1, and a carry output terminal OUT2.

For example, a carry signal Cout(j−1)of a previous stage STj−1may be input to the set terminal S of a jthstage STjconnected to a jthgate line Gj(j≠1), a gate signal Gout(j+1)of a next stage STj+1may be input to the reset terminal R of the jthstage STj, and the clock signal CKV and the clock bar signal CKVB may respectively be input to the first clock terminal CK1and the second clock terminal CK2of the jthstage STj. In addition, the gate-off voltage Voffmay be input to the power source terminal GV, the initialization signal INT or a carry signal Cout(n)of a last stage STnmay be input to the frame reset terminal FR. The gate output terminal OUT1may output a gate signal Gout(j), and the carry output terminal OUT2may output a carry signal Cout(j).

The scan start signal STVP, instead of a carry signal of a previous stage, may be input to the set terminal S of a first stage ST1because there is no carry signal of a previous stage. Also, the scan start signal STVP, instead of a carry signal of a next stage, may be input to the reset terminal R of the last stage STnbecause there is no carry signal of a next stage.

In addition, a gate line in any of the stages ST1through STnmay be connected to the gate voltage generator100such that one of the gate signals Gout(1)through Gout(n)can be fed back as a sub-gate signal Gsub.

In this embodiment, the gate signal Gout(n)of the last stage STnlocated at the bottom of the drawing is connected to the gate voltage generator100as a sub-gate signal Gsub. If the gate signal Gout(n)of the last stage STnis provided to the gate voltage generator100, the sub-gate signal Gsubreflecting all the stages ST1through STncan be provided to the gate voltage generator100as the sub-gate signal Gsubbecause the stages ST1through STnare electrically connected to each other to exchange signals.

The gate driver300may be manufactured as a separate semiconductor chip and attached to the liquid crystal panel600, or directly formed on the liquid crystal panel600as an amorphous silicon thin-film transistor. When each of the stages ST1through STnis manufactured as an amorphous silicon thin-film transistor, cost and space can be saved than when each of the stages ST1through STnis manufactured as a separate semiconductor chip. However, each of the stages ST1through STnis not necessarily manufactured using the above material or method and can be manufactured using various other methods of manufacturing an electronic element.

FIG. 10is a block diagram of a gate driver300according to another embodiment of the present inventive concept.

Referring toFIG. 10, unlike the gate driver300ofFIG. 9, the gate driver300according to the current embodiment may further include a dummy stage STsubwhich outputs a sub-gate signal Gsubonly. The number of dummy stages may be more than one. Since each component of the gate driver300excluding the dummy stage has been described above with reference toFIG. 9, a description thereof will be omitted. The dummy stage provides the sub-gate signal Gsub to the reset terminal of the previous stage STn and receives the scan start signal STVP as a reset signal. Embodiments of the present inventive concept provide at least one of the following advantages.

It is possible to output a gate signal having a constant voltage value despite a temperature change of a display device.

However, the effects of the present inventive concept are not restricted to the one set forth herein. The above and other effects of the present inventive concept will become more apparent to one of ordinary skill in the art to which the present inventive concept pertains by referencing the claims.