Asynchronous-logic circuit for full dynamic voltage control

Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a filing under 35 U.S.C. 371 as the National Stage of International Application No. PCT/SG2011/000253, filed Jul. 14, 2011, entitled “ASYNCHRONOUS-LOGIC CIRCUIT FOR FULL DYNAMIC VOLTAGE CONTROL,” which claims the benefit of and priority to U.S. Provisional Patent Application No. 61/364,478, filed Jul. 15, 2010 and entitled “ASYNCHRONOUS-LOGIC CIRCUIT FOR FULL DYNAMIC VOLTAGE CONTROL”, both of which are incorporated herein by reference in their entirety for all purposes.

FIELD

The present invention relates to a logic circuit, and in particular to asynchronous-logic for full Dynamic Voltage Scaling including operation in the sub-threshold voltage regime for ultra-low power operation.

BACKGROUND

Dynamic Voltage Scaling refers to the scaling of the magnitude of supply voltage to provide a means of power/speed trade-off. Specifically, for higher speed demands, supply voltage is ‘dialled-up’ and conversely ‘dialled-down’ when the demand for speed is modest.FIG. 1depicts the power dissipation (see bold solid line101) and speed (see bold dotted line102) characteristics of a digital circuit for a full range of Dynamic Voltage Scaling, where the supply voltage VDD103is adjusted from the nominal voltage regime104to the near-threshold voltage regime105to the sub-threshold voltage regime106. InFIG. 1, the readings of the power dissipation101and the speed102of the digital circuit are normalized to those at the nominal voltage107. At the sub-threshold voltage regime106, VDD103is even below the threshold voltage108of transistors, and the digital circuit still works, although significantly slower by merely using a weak-inversion current for charging and discharging, until at the minimum voltage109where the transistors therein fail to switch. Interestingly, in some applications, the maximum energy efficiency point/lowest power dissipation point of a digital circuit can be shown at the sub-threshold voltage regime106in a book entitled ‘Sub-threshold Designs for Ultra Low-power Systems’, Springer, 2006, authored by A. Wang, B. H. Calhoun, and A. P. Chandrakasan (herein Wang et al). Thus, operating digital circuits at the sub-threshold voltage regime106is highly attractive for ultra-low power dissipation, and when necessary, is suitable for full Dynamic Voltage Scaling for power/speed trade-off.

Sub-threshold operation offers the potential of ultra-low power, including operation at or near the maximum efficiency point or region, albeit very low speed. An important consideration for the practical realization of sub-threshold circuits may be operational robustness, that is their tolerance to process, voltage, and temperature (PVT) variations, whereby the process variations include threshold voltage variations. This difficulty of practical realization may be compounded when smaller geometry nano-scaled fabrication processes are used as these variations become increasingly variable. For example, the process parameter and threshold voltage variations (at nominal VDD) detailed in the International Technology Roadmap for Semiconductors (ITRS-2009) stipulate that these variations will increase from 11% and 42% for the current 45 nm process to 32% and 112% for the impending 9 nm process expected in 2024. These variations may strongly influence the circuit performance. As the effects of PVT variations (and permutations thereof) may be severe and largely unpredictable (or intractable), they may lead to unpredictable sub-threshold circuit performance. This appears to be a seemingly insurmountable obstacle to their acceptance within the electronics community and/or to their practical application, save relatively simple applications, for example wrist watches.

Attempts to accommodate the PVT variations in practical realization of complex digital sub-threshold systems include enforcing strict operating environments (e.g. expensive highly controlled fabrication processes and electrical conditions), transistor upsizing (to reduce the effects of random dopent fluctuations), analog-like current-mode approaches, adaptive body biasing, double-gate MOSFET, self-calibration techniques, redundancy circuitry, and adopting ‘pessimistic’ designs in the sense that large delay safety margins are allowed, etc; the large delay safety margins allowed for would typically include the worst-case delay, including clock skew, setup-time, hold-time for registers, etc. Consequently, designing a system with operation robustness, based on the contemporary and prevalent synchronous-logic design philosophy at the lower range of sub-threshold voltage operation is challenging, largely unsuccessful and/or its operation unnecessarily slower than warranted. This is because in synchronous-logic, a global clock or variants thereof is used for synchronization and every operation must be completed within a clock period. In fact, because a complete profile of the PVT variations is virtually intractable in the sub-threshold voltage regime106, the circuit operation cannot be guaranteed to be robust (substantially error-free) if the contemporary synchronous-logic design philosophy is adopted. A good description of synchronous-logic design philosophy can be found in a book authored by J. Rabaey, A. Chandrakasan, and B. Nikolic and entitled ‘Digital Integrated Circuits, A Design Perspective’,2ndEd. Upper Saddle River, N.J.: Prentice Hall, 2001. The associated design difficulties of synchronous-logic designs for sub-threshold operation can be found in the book by Wang et al.

An alternative digital logic design philosophy for sub-threshold voltage operation is to adopt the somewhat esoteric asynchronous-logic design philosophy, which is clockless or self-timed. There are four general async approaches: Delay-Insensitive, Self-Timed (including bundled-data), Speed-Independent and Quasi-Delay-Insensitive (QDI). Of these, only the QDI async approach offers the most practical approach for sub-threshold operation, significant advantages of design simplicity (in terms of accommodating PVT variations) and operation robustness. It innately detects the computation delays according to different workloads and operating conditions. A good description of asynchronous-logic design philosophy can be found in a book authored by J. Sparso and S. Fuber and entitledPrinciple of Asynchronous Circuit Design: A Systems Perspective, Norwell M A: Kluwer Academic, 2001 (herein Sparso et al). Further, a good description of the specific QDI approach can be found in a paper authored by A. Martin and M. Nsytrom and entitled ‘Asynchronous Techniques for System-on-chip Designs’, IEEE Proceedings, 2006, and in a book authored by S. C. Smith and J. Di and entitled ‘Designing Asynchronous Circuits using NULL Convention Logic(NCL)’, Morgan & Claypool, 2009 (herein Smith et al).

QDI circuits are typically implemented in either one of three logic families: Dynamic-Logic, Pass-Logic or Static-Logic. Static-Logic circuits may comprise complementary networks of n- and p-transistors. Typically the n-network ties the output to the ground and the p-network ties the output to the supply voltage. The configuration is such that the two networks are mutually exclusive for operation, and the output is connected at every point in time to either the ground or the supply voltage via a low resistance path. The logic output is thus statically stable and no additional circuitry is therefore needed to hold the output at its intended value. This can be contrasted with Dynamic-Logic, which requires temporary storage of signal values which generally rely on the capacitance of high impedance nodes. As a result of this operation, Dynamic-Logic suffers from current leakage and charge sharing, and thus requires the use of weak keepers to counteract charge leakage/sharing and thus to hold the dynamic signal value.

Known QDI circuits based on the Dynamic-Logic and Pass-Logic families and different variations thereof include differential cascode voltage swing logic (DCVSL), pre-charged half buffer, and mixed Dynamic-Logic/Pass-Logic/pseudo-Static-Logic. These QDI circuits can be found in literature, and are largely summarized in the abovementioned book authored by Sparso et al, and in a book authored by P. A. Beerel, R. O. Ozdag, and M. Ferretti and entitled ‘A Designer's Guide to Asynchronous VLSI’, Cambridge University Press, 2010 (herein Beerel et al). For sub-threshold operation, designs based on the Dynamic-Logic family are generally inapplicable or impractical due to their unreliability (poor robustness) and the associated critical sizing of transistors (especially for weak keepers) due to charge leakage/sharing. Similarly, QDI designs based on Pass-Logic family are impractical and not robust for sub-threshold operation due to either a weak logic ‘1’ transfer (for n-MOS pass-logic) or a weak logic ‘0’ transfer (for p-MOS pass-logic), resulting in poor noise margin. In other words, they suffer from weak current strength (especially when transistor stack is high). Furthermore, they often require weak keepers (which in turn require critical transistor sizing) for signal restoring/holding. On the other hand, designs based on the Static-Logic family are more reliable, in part because the associated sizing of transistors is not as critical and their level of noise margin is higher as compared to other logic families.

Reported QDI asynchronous-logic realization approaches based on Static-Logic family include NULL-convention-logic (NCL), Delay-Insensitive-Minterm-Synthesis (DIMS) and Direct Static-Logic Implementation (DSLI). However, these realizations based on these reported QDI realization approaches have relatively high overheads in terms of large IC area, long delays and high power/energy, in part because of their relatively complex realizations. These shortcomings are considerable in large digital systems because of the associated cost (large IC area), slow computation (long delay) and short battery lifespan (high power; or the need to accommodate higher heat).

In summary, the appropriate design methodology to operate digital circuits for full Dynamic Voltage Scaling (including for sub-threshold operation) is to adopt asynchronous-logic design philosophy, specifically the QDI approach with Static-Logic realization approach. At the juncture of technology, there is no operationally robust and yet ultra low power sub-threshold digital circuit, including those digital circuits based on the reported QDI realization approaches. Hence, it is highly desirable to have a design technique that is virtually insensitive to the PVT variations, and the associated attribute is operation robustness and yet ultra low power dissipation for sub-threshold digital circuits. This will be apparent later in this specification.

SUMMARY

As it will be apparent from the following description, one or more embodiments may provide a novel asynchronous-logic realization approach using Static-Logic that allows robust circuit operation in the sub-threshold region. The embodiments yield designs with simultaneous smaller IC area, higher speed and yet lower power than prior-art approaches that offer robust operation in the sub-threshold region. This presents a significant advancement in green technologies as power/energy budgets of such circuits are limited. Embodiments may also be applied to meet the ever increasing demand for portable devices with extended battery lifespan. Other applications include power-critical/energy-critical applications with modest speed requirements, such as physiological and biological sensors, hearing aids, including energy harvesting/scavenging applications, etc.

One implementation of the QDI asynchronous Static-Logic involves the integration of a REQ sub-circuit, a Request input, and two buffers into a Static-Logic cell redesigned for a basic dual-rail QDI circuit. This integration may simultaneously yield smaller IC size, higher speed and lower power dissipation.

According to aspects of the present invention there is provided a logic circuit according to claim1,13or15, or an asynchronous-logic pipeline according to claim17,18or19. Embodiments may be implemented according to any one of claim2to12,14or16.

DETAILED DESCRIPTION

In general terms, an embodiment of the present invention provides a new QDI Static-Logic realization approach appropriate for the full range of Dynamic Voltage Scaling. This new approach is termed “Pre-Charged Static-Logic” (PCSL) approach in this specification.

FIG. 2depicts a block diagram of asynchronous-logic QDI pipelines201. Inputs202is the input operands for a plurality of sets of data. Each set of data is encoded in a 1-of-N-rail manner where N is 2M, and M is a non-zero integer. For example,FIG. 3depicts the truth table of a dual-rail (N=2) encoding how a valid and a NULL (standby) data are represented. If the data Q.T301and Q.F302are of the opposite logic states, the data is considered valid. If the data Q.T301and Q.F302are of the same logic states, the data is considered NULL. Particularly, a low logic NULL303is when the data Q.T301and Q.F302are both ‘0’'s, and conversely, a high logic NULL304is when the data Q.T301and Q.F302are both Ts.

With reference toFIG. 2, consider now a standard 4-phase operation. During an active operation, one of the rails (in each set of data) will be asserted to indicate a valid data, and the QDI pipelines201will decode (i.e. compute) these data and assert the Acknowledge (ACK) signals203when the computation is completed. During a NULL i.e. empty (standby) operation, all the rails (in each set of data) will be de-asserted to all ‘0’'s (for low logic NULL) or all (for high logic NULL), and the QDI pipeline201will de-assert the ACK signals203.

The QDI pipelines201are self-timed, and detect the computation delays according to different workloads and operating conditions. The QDI pipelines201are able to synchronize their operation correctly (at any speed rates), and accommodate any PVT variations for substantially error-free operation.

FIG. 4depicts a possible pipeline implementation, embodying a QDI Controller Circuit,403and QDI Circuitsi409. Primary Inputsi401is first transferred through Latchesi405to be Inputsi407. Once Inputsi407are all valid, the Input Completion Detection (ICDi) circuit406will assert ACKi402, indicating that the data is valid and transferred successfully. Inputsi407will further assert QDI Circuitsi409for computation to produce an output, Outputsi(or equivalent to Inputsi+1)411. Depending on the circuit implementation for QDI Circuitsi409, REQi408may be necessary for asserting the QDI Circuitsi409. Once Inputsi+1411is transferred and acknowledged by the successive pipeline stage, ACKi+1412will assert the Latch Controlleri404to hold Inputsi407. Inputsi407will only be reset when Primary Inputsi401become NULL. Thereafter, the ICDi406will de-assert ACKi402, informing the preceding pipeline stage that new Primary Inputsi401can now be transferred.

The pipeline structure ofFIG. 4may be modified by rearranging QDI Controller Circuits and QDI Circuits, or by re-grouping them, or by integrating them together. Some of these pipeline modifications can be found in the book by Sparso et al.

The power/speed efficiency and robustness of QDI circuitsi409may depend on their circuit realizations. In the sub-threshold region regime, Static-Logic circuits are able to offer robust and substantially error-free operation (over other logic families, including Dynamic-Logic and Pass-Logic; see QDI circuits based on these logic families in the books by Sparso et al and Beerel et al).

FIG. 5(a) depicts a generic block diagram of a prior-art Static-Logic dual-rail QDI circuit based on the threshold logic transistor-level realization. The output Q.T510is constructed by the Pull-Up and State Holding Circuit502, Pull-Down and State-Holding Circuit504, feedback transistors506,508, and the buffer512. The output Q.F511is constructed by the Pull-Up and State Holding Circuit503, Pull-Down and State-Holding Circuit505, feedback transistors507,509, and the buffer513. Inputs501will reset both the outputs Q.T510and Q.F511(via the Pull-up and State-Holding Circuits502,503) to NULL, and when necessary, holds a logic state ‘0’ for the output Q.T510and the output Q.F511when a valid operation has not been asserted. Conversely, Inputs501will also be able to set one of the outputs (either Q.T510via the Pull-down and State-Holding Circuits504or Q.F511via the Pull-down and State-Holding Circuits505) to ‘1’ for a valid operation, and when necessary, holds a logic state ‘1’ for the outputs Q.T510and Q.F511when a NULL has not been asserted. Interestingly, the outputs Q.T510and Q.F511serve not only as the outputs, but also as the inputs connected to the feedback transistors506,507,508,509within the QDI circuit. Without a critical sizing of the transistors, although such prior-art designs are appropriate for full Dynamic Voltage Scaling, the drawback is large circuit overhead. Furthermore, the constructions of the Q.T and Q.F output blocks are separate circuit entities, hence area-inefficient. Examples of such designs include threshold-logic NCL circuits and circuits (with and without an additional Reset (RST) signal), and circuits by simply converting dual-rail Dynamic-Logic to dual-rail Static-Logic.

For clarity,FIGS. 5(b) and (c) depict a dual-rail AND/NAND circuit based on the prior-art threshold-logic NCL circuit with and without an RST signal respectively. The feedback transistors514,515,516,517inFIG. 5(b) and the feedback transistors522,523,524,525inFIG. 5(c) in part provide the state-holding function. Note that because the Q.F block of the AND/NAND gate (FIGS. 5(b) and (c)) is essentially serves as ‘OR’ function, hence the transistors515,517,518,519,520,521inFIG. 5(b) can be removed for optimization, so do the transistors523,525,526,527,528,529inFIG. 5(c). Nonetheless, even such optimization, the prior-art dual-rail AND/NAND gate is still not area-/speed-/power-efficient.

FIG. 6(a) further depicts another generic block diagram of prior-art dual-rail QDI circuits by using standard library cells601realized in Static-Logic (including the design structure depicted inFIG. 5(a)). The assertion of True Circuit603and False Circuit604is mutually exclusive (i.e. either the output Q.T605of True Circuit603or the output Q.F606of False Circuit604is asserted), and the de-assertion of True Circuits603and False Circuit604can be simultaneous. Particularly, Inputs602will assert True Circuit603for generating an output to ‘1’ if the data is valid (only for True Circuit603), and de-assert the output to ‘0’ when data is NULL. Similarly, Inputs602will assert False Circuit604for generating an output to ‘1’ if the data is valid (only for False Circuit604), and de-assert the output to ‘0’ when data is NULL. Because of a Static-Logic implementation, such prior-art designs are appropriate for full Dynamic Voltage Scaling, but the drawback is area-/speed-/power-inefficient due to a large number of library cells required. Examples of such designs include library-cell based NCL, Delay-Insensitive Minterm Synthesis (DIMS), and Direct Static Logic Implementation (DSLI) circuits. For clarity,FIGS. 6(b) to (d) depict a dual-rail AND/NAND circuit based on the prior-art library cells based on the NCL, DIMS and DSLI approaches respectively where it can be seen that the associated hardware is complex (more complex than the embodiments of the present invention; it will be later shown that these prior-art designs are also simultaneously slower and dissipate higher power than the embodiments of the present invention, see Tables II and III).

FIG. 7depicts a block diagram of the architecture of a logic circuit, an embodiment of the present invention, the PCSL approach. As delineated earlier, the objective of the present invention is to realize asynchronous-logic QDI circuits appropriate for full Dynamic Voltage Scaling, including robust sub-threshold voltage operation, and whose realization is simultaneously more hardware efficient (small IC area and/or low circuit overheads), higher speed and yet lower power than all prior-art techniques. The PCSL circuit inFIG. 7achieves low circuit overheads by means of an integration of a REQ sub-circuit (comprising first, second and third switches respectively in the form of transistors703,704,705, a Request input in the form of the REQ signal702, and two buffers709,710(one to each circuit outputs711)) into a Static-Logic cell in the form of a complementary Static-Logic library cell706(comprising two data inputs in the form of Inputs701) redesigned for a basic dual-rail QDI circuit.

This unique integration simultaneously yields the higher speed and yet lower power dissipation. This is as opposed to a design where the Static-Logic cell and a REQ sub-circuit comprising the REQ signal702are separate independent circuit entities. To be specific, a possible such prior-art circuit realization could be a DSLI circuit according toFIG. 6(a) where the Static-Logic cell and REQ subcircuit are constructed independently with a plurality of Static-Logic library gates (e.g. AND gates, OR gates, C-Muller gates, etc,), hence they are separate independent circuit entities.

InFIG. 7, the transistors703,704are p-MOS transistors but any other p-type transistor may be used. Similarly, inFIG. 7, the transistor705is an n-MOS transistor but any other n-type transistor may be used. The sources of the p-MOS transistors703,704are connected to a high supply rail in the form of the high voltage supply713. The drains of the p-MOS transistors703,704are connected to first and second Static-Logic cell outputs707,708from the complementary Static-Logic cell706, and respectively drive the buffers709,710to produce first and second circuit outputs711(or dual-rail outputs). The drain of the n-MOS transistor705is connected to a low voltage rail in the form of a negative supply rail712of the complementary Static-Logic cell706, and the source of the n-MOS transistor705is directly connected to a low supply rail in the form of the low voltage supply714. The complementary Static-Logic cell706further has a high voltage rail in the form of a positive supply rail715connected to the high voltage supply713. The gates of the p-MOS transistors703,704and the gate of the n-MOS transistor705are connected to the REQ signal702.

As shown inFIG. 7, the first and second Static-Logic cell outputs707,708are in communication with the first and second circuit Outputs711via the buffers709,710respectively. These buffers709,710have an inverting logic (i.e. are configured for inversion). In particular, the input of each buffer709,710is connected to respective Static-Logic cell outputs707,708of the complementary Static-Logic cell706whereas the outputs of the buffers709,710are the circuit outputs—Outputs711.

The operation of the logic circuit ofFIG. 7comprises an initial phase and an evaluate phase as follows.

During the initial phase, REQ signal702is at a negate-valued logic (in this case, ‘0’) to pre-charge the Static-Logic cell outputs707,708from the complementary Static-Logic cell706to resulting in a NULL Outputs711. In particular, when the REQ signal702receives the negate-valued logic, the transistors703,704are asserted and the transistor705is negated. The negation of the transistor705disconnects the complementary Static-Logic cell706from the low voltage supply714, thus the Static-Logic cell706is unable to compute (dis-charge) one of the Static-Logic cell outputs707,708even if the Inputs701are valid. Furthermore, the assertion of the transistors703,704effectively pre-charges the Static-Logic cell outputs707,708. As the pre-charged Static-Logic cell outputs707,708are connected to the circuit outputs711via buffers709,710with an inverting logic, the circuit outputs711are hence reset to a reset logic value (in this case, ‘0’ or in other words, NULL), rendering the Static-Logic Cell706inoperative. The REQ signal702also serves as a fast reset signal that significantly shortens the back-forward delay of the circuit, improving the overall speed of the QDI circuit.

During the evaluate phase, when the REQ signal702receives an assertive-valued logic (i.e. REQ702=‘1’), the transistors703,704are negated whereas the transistor705is asserted. This assertion of the transistor705connects the complementary Static-Logic cell706to the low voltage supply714, thereby enabling the Static-Logic cell706to compute (dis-charge) one of the Static-Logic cell outputs707,708if the Inputs701are valid, and the buffers709,710will assert valid outputs711(opposite states of the dual-rail signals). When the REQ signal702is ‘1’ and Inputs701is yet valid (i.e. pending for an active operation), the complementary Static-Logic cell706will hold its outputs711.

In the logic circuit ofFIG. 7, the Static-Logic cell outputs707,708are either charged through the high voltage supply713or discharged through the negative supply rail712to the low voltage supply714. These charging and discharging operations are performed in a mutually exclusive manner.

To delineate the design of basic digital cells embodying the PCSL architecture that simultaneously features lower hardware overheads, higher speed and yet lower power dissipation than prior-art designs,FIGS. 8(a) to (f) depict a 2-input AND/NAND gate, a 2-input OR/NOR gate, a 3-input AND_OR/AND_OR_INV (AO/AOI) gate, a 3-input OR_AND/OR_AND_INV (OA/OAI) gate, a 2-input XOR/XNOR gate, and a 2-input MUX gate respectively based on the present invention. A person skilled in the art can simply design other QDI cells based on the present invention. The design of basic digital cells embodying the prior-art approaches (e.g. NCL, DSIM and DSLI) can be found inFIGS. 5 and 6, and the books authored by Sparso et al and Smith et al. On a basis of 7 cells, a 2-input AND/NAND gate, a 2-input OR/NOR gate, a 3-input AO/AOI gate, a 3-input OA/OAI, a 2-input XOR, a 2-input MUX and a 3-input full adder, using a 130 nm CMOS process at sub-threshold voltage 0.15V, the designs based on the present invention are on average simultaneously 3× smaller IC area, 2.5× faster speed, and 2.3× lower energy/operation over the prior-art Static-Logic QDI designs—note that these worthy advantages are obtained simultaneously.

It is also possible to use inverted input operands.FIG. 9depicts a block diagram of an alternative structure, a complementary design, employing the PCSL approach. This alternative structure also achieves low circuit overheads by means of an integration of a REQ sub-circuit (comprising first, second and third switches respectively in the form of transistors903,904, and905, a Request input in the form of theREQsignal902, and two buffers909,910(to circuit Outputs911)) into a Static-Logic cell in the form of a complementary Static-Logic library cell906(comprising two data inputs in the form ofInputs901) redesigned for a basic dual-rail QDI circuit. Particularly, inFIG. 9, the transistors903,904are n-MOS transistors but any other n-type transistor may be used. Similarly, inFIG. 9, the transistor905is a p-MOS transistor but any other p-type transistor may be used. The sources of the n-MOS transistors903,904are connected to a low supply rail in the form of the low voltage supply914. The drains of the n-MOS transistors903,904are connected to first and second Static-Logic cell outputs907,908from the complementary Static-Logic cell906, and respectively drive the buffers909,910to produce first and second circuit outputs (or dual-rail outputs)911. The drain of the p-MOS transistor905is connected to a high voltage rail in the form of a positive supply rail912of the complementary Static-Logic cell906, and the source of the p-MOS transistor905is directly connected to a high supply rail in the form of the high voltage supply913. The complementary Static-Logic cell906further has a low voltage rail in the form of a negative supply rail915connected to the low voltage supply914. The gates of the n-MOS transistors903,904and the gate of the p-MOS transistor905are connected to theREQsignal902.

Similar to the logic circuit shown inFIG. 7, the first and second Static-Logic cell outputs907,908of the logic circuit ofFIG. 9are in communication with the first and second circuit outputs911via the buffers909,910having an inverting logic (i.e. configured for inversion). In particular, the input of each buffer909,910is connected to respective Static-Logic cell outputs907,908of the complementary Static-Logic cell906whereas the outputs of the buffers909,910are the circuit outputs—Outputs911.

The logic circuit operation of the alternative structure ofFIG. 9also comprises an initial phase and an evaluate phase as follows.

During the initial phase, theREQsignal902is at a negate-valued logic (in this case ‘1’) to dis-charge the Static-Logic cell outputs907,908from the complementary Static-Logic cell906to ‘0’'s, resulting in a NULL output (both ‘1’'s for Outputs911). In particular, when theREQsignal902receives the negate-valued logic, the transistors903,904are asserted and the transistor905is negated. The negation of the transistor905disconnects the Static-Logic cell906from the high voltage supply913, thus the Static-Logic cell906is unable to compute (charge) one of the Static-Logic cell outputs907,908even ifInputs901are valid. Furthermore, the assertion of the transistors903,904effectively dis-charges the Static-Logic cell outputs907,908. As the dis-charged Static-Logic cell outputs907,908are connected to the circuit outputs911via buffers909,910with an inverting logic, the circuit outputs911are hence reset to a reset logic value (in this case, ‘1’), rendering the Static-Logic Cell906inoperative. TheREQsignal902also serves as a fast reset signal that significantly shortens the back-forward delay of the circuit, improving the overall speed of the QDI circuit.

During the evaluate phase, when theREQsignal902receives an assertive-valued logic (i.e.REQsignal902=‘0’), the transistors903,904are negated whereas the transistor905is asserted. This assertion of the transistor905connects the complementary Static-Logic cell906to the high voltage supply913, thereby enabling the Static-Logic cell906to compute (charge) one of the Static-Logic cell outputs907,908ifInputs901are valid, and the buffers909,910will assert valid outputs911(opposite states of the dual-rail signals). When REQ902is ‘0’ andInputs901is yet valid (i.e. pending for an active operation), the complementary Static-Logic cell906will hold its Outputs911.

FIG. 10depicts a 2-input AND/NAND gate based on the alternative structure ofFIG. 9. Other QDI cells can be designed based on this alternative structure, and these QDI cells embodying the present invention feature the same advantages as the structure depicted in FIG.7—simultaneous hardware simplicity, faster and lower power dissipation over other prior-art QDI cells.

The REQ sub-circuit (e.g. transistors703,704, and705associated with REQ702inFIG. 7or transistors903,904,905associated withREQ902inFIG. 9) can be redesigned in a number of ways wherein the REQ sub-circuit is still an integral part of either the complementary Static-Logic cell706or the complementary Static-Logic cell906. For instance, more transistors can be connected either in series or parallel to serve the same function of the REQ sub-circuit. Furthermore, other signals (in addition to REQ702orREQ902) can be inserted into the REQ sub-circuit to improve controllability, either to reset or to evaluate the QDI circuit. There may also be more than one Request input and more than one transistor may be controlled by either the same Request input or different Request inputs.

The buffers709,710,909,910can be redesigned in a number of ways wherein the buffers709,710,909,910are to initialize a proper NULL operation (either all ‘0’'s or all ‘1’'s) appropriate for a pre-defined handshake signaling, or to provide higher load drivability, or both. For instance, an inverter chain can be used for each buffer709,710,909,910. Furthermore, the buffers709,710,909,910can also be eliminated where the NULL operation received by input operands and by output operands is at different logic states. The buffers also need not have an inverting-logic. Instead, they may have a non-inverting logic (i.e. they may be configured for non-inversion).

A dual-rail circuit can be modified to any 1-of-N-rail circuits by using these design principles. For example, for a 1-of-4-rail circuit, the complementary Static-Logic cells706,906can be redesigned into a quad Static-Logic cell for 4 outputs, and wherein only one of the 4 outputs can be asserted during an active operation.

The present invention thus far has been described for the design of basic digital cells. This invention can be applied to virtually all aspects of a digital QDI system, including systems that employ basic digital cells. For example, consider the design of a QDI pipeline.

The pipeline operation embodying the circuits using the design principle mentioned in the present invention is similar to that inFIG. 4, and its specific pipeline implementation can be modified according to the specific control signals. For example,FIG. 11shows a pipeline structure where the library cells1114designed based on the present invention are embodied in QDI Circuit,1109. The Data Completion Detection (DCDi)1115, comprising OR gates and C-Muller gates, generates an All Valid/Empty (AVEi) signal1116which is used to detect the validity/nullity signals generated in part from the library cells1114. AVEi1116will thereafter feedback the C-Muller gate1113which in turn control Latchesi1105for either passing Primary Inputsi1101to Inputsi1107or holding Inputsi1107. The pipeline structure inFIG. 11fully abides by the QDI protocol (termed ‘Fully-QDI’), hence its pipeline operation is extremely robust (in terms of accommodating PVT variations).

To delineate the advantages of the present invention, on the basis of the established ISCAS C880, C6288, S344, and S1238 benchmarks, Table II respectively show the area (proportional to the hardware overheads), delay, and energy/operation figures-of-merit of the ISCAS benchmarks redesigned as the Fully-QDI pipelines employing the PCSL and the prior-art NCL, DISM and DSLI approaches. For ease of interpreting the results, the figures-of-merit are normalized with respect to the results obtained for the pipeline employing the invented PCSL approach. From Table II, it can be seen that the Fully-QDI pipelines employing the invented PCSL approach simultaneously achieve the smallest area, least delay, and the lowest energy/operation. These simultaneous advantages are considerable and highly valued in practical IC designs.

TABLE IIBenchmarking of Area, Delay and Energy/Operation of Fully-QDIPipelines based on the Present Invention and the Prior-Art DesignsAreaDelayEnergy/OperationPresent Invention1.0×1.0×1.0×Prior-Art1.9×2.1×2.5×

FIG. 12depicts an alternative pipeline structure where library cells1214designed based on the present invention are similarly embodied in QDI Circuiti1209. Note that this pipeline structure does not include DCDi(seeFIG. 11) to fully acknowledge the output signals in part generated by the library cells1214. As a result, the pipeline structure inFIG. 12does not fully abide by the QDI protocol (termed ‘Pseudo-QDI’) because it requires an implicit timing during the reset phase to guarantee error-free operation. Nonetheless, such implicit timing is easily satisfied in practice; this implicit timing has been verified to yield designs with robust operation by means of well-established ISCAS benchmark circuits with very large variations, specifically for ±3σ process variations in 130 nm CMOS.

On the basis of the same ISCAS benchmarks, Table III respectively shows the area, delay and energy/operation figures-of-merit of the ISCAS benchmarks redesigned as the Pseudo-QDI pipelines employing the PCSL and the prior-art NCL, with a fast RST signal (seeFIG. 5(c)). As before, for ease of interpretation, the figures-of-merit are normalized with respect to the results obtained for the pipeline employing the inventor PCSL approach. From Table III, it can be seen that the Pseudo-QDI pipelines employing the invented PCSL approach simultaneously achieve smaller area, faster delay and lower energy/operation.

TABLE IIIBenchmarking of Area, Delay and Energy/Operation of Pseudo-QDIPipelines based on the Present Invention and the Prior-Art DesignsAreaDelayEnergy/OperationPresent Invention1.0×1.0×1.0×Prior-Art2.1×1.5×1.6×

Of the two Fully-QDI and Pseudo-QDI pipelines, the latter pipeline is, as expected, more IC area-efficient and energy-efficient than the former (due to a simpler pipeline structure in the latter). In terms of speed, both pipelines are comparable. In both pipeline designs, pipelines embodying the present invention feature the simultaneously least IC-area, fastest speed and lowest power dissipation compared to the same pipelines embodying prior-art QDI designs.

To delineate the robustness of the Fully-QDI and Pseudo-QDI pipelines depicted inFIGS. 11 and 12respectively, consider the design of an 8-tap 8-bit Finite Impulse Response (FIR) filter based on each of these pipeline structures. Both the Fully-QDI and pseudo-QDI FIR filters were designed and fabricated in a 130 nm CMOS process and based on the library cells designed based on the present invention. As expected, both Fully-QDI and Pseudo-QDI FIR filters were functional for full-range dynamic voltage scaling, ranging from the nominal voltage of 1.2V down to the lower range of sub-threshold voltage region of 130 mV (where the transistors therein fail to operate). The microphotograph of the fabricated prototype Fully-QDI and Pseudo-QDI FIR filters is shown inFIG. 13. Also as expected, both Fully-QDI FIR and Pseudo-QDI FIR filters were found to be operationally robust, even with large operating supply voltage variations and with large temperature changes from 25° C. to −55° C. Further as expected, both the Fully-QDI and Pseudo-QDI FIR filters were energy-efficient, and at the sub-threshold voltage range of 0.25V to 0.3V, they featured the most energy-efficiency voltage point. Of the two designs, the Pseudo-QDI FIR filter was, as expected, found to be more energy-efficient and IC area-efficient than the Fully-QDI filter (due to a simpler pipeline structure in the former). In terms of speed, both designs are comparable.

In summary, the invented PCSL technique offers a unique approach that offers simultaneous lower hardware overheads (IC area), faster operation (less delay) and yet lower power dissipation than prior-art approaches appropriate for full Dynamic Voltage Scaling including sub-threshold operation.

It should be clear that a skilled person in the art can further modify the pipeline structure in a number ways by modifying either (or both) QDI Circuiti409,1109,1209or QDI Controller Circuiti403,1103,1203wherein the library cells based on the present invention are part thereof. Such modifications may include moving QDI Controller Circuiti403,1103,1203after QDI Circuiti409,1109,1209, adding/deleting any intermediate signals suitable for various specific communication channels, adding/removing completion detection circuits for acknowledging the signal validity/nullity, and combining/splitting different pipelines.

It should be also clear that a skilled person in the art can re-arrange in a number of ways the library cells based on the present invention in a pipeline structure. Such re-arrangement includes placing the library cells based on the present invention at different columns and at different rows in QDI Circuit,409,1109,1209and interleaving the library cells based on the present invention with other prior-art library cells.

It should be even clear that a skilled person in the art can incorporate in a number of ways the library cells based on the present invention into the various blocks in a pipeline structure. Such in-corporation may include applying the library cells based on the present invention to QDI Controller Circuiti403,1103,1203(including Latchesi405,1105,1205, Latch Controlleri404,1104,1204and ICDi406,1106,1206) and QDI Circuiti409,1109,1209, and grouping the library cells based on the present invention with other prior-art library cells.

The foregoing describes preferred embodiments, which, as will be understood by those skilled in the art, may be subject to variations or modifications in design, construction or operation without departing from the scope of the claims. For example, the logic level ‘1’ may be interchangeably referred to as ‘logic high’ and logic level ‘0’ may also be interchangeably referred to as ‘logic low’. These variations, for instance, are intended to be covered by the scope of the claims.