Semiconductor devices and methods for manufacturing the same

Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

BACKGROUND

Example embodiments relate to semiconductor devices and methods for manufacturing the same.

2. Description of the Related Art

A semiconductor device may include an integrated circuit provided with a plurality of metal oxide semiconductor field effect transistors (MOSFETs). As semiconductor devices are highly integrated, a line width of a gate electrode included in a MOS transistor is reduced. The reduction in the line width of the gate electrode may cause a short channel effect and increase an electrical resistance of the gate electrode to cause a resistance-capacitance (RC) delay.

To solve an increase problem in the sheet resistance and contact resistance of the gate, source and drain of a MOSFET, a process of forming a silicide layer having a low resistivity has been developed. Techniques to form a gate electrode with a metallic material having a low resistivity have been proposed.

SUMMARY

Example embodiments may provide semiconductor devices including a metal gate electrode having a fine line width. Example embodiments may also provide methods for manufacturing semiconductor devices including a metal gate electrode having a fine line width.

Some example embodiments of the inventive concepts provide semiconductor devices including a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of a sidewall of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

Other example embodiments of the inventive concepts provide methods for manufacturing semiconductor devices including forming a gate stack including a gate insulation pattern, a gate sacrificial pattern and a capping pattern which are sequentially stacked on a semiconductor substrate, forming a spacer structures at both sidewalls of the gate stack, forming source/drain regions in the semiconductor substrate at both sides of the gate stack, forming an etch stop pattern covering the source/drain regions under an upper surface of the gate sacrificial pattern, forming a gap fill insulation layer covering the etch stop pattern but exposing the capping pattern of the gate stack, removing the capping pattern and the gate sacrificial pattern to form a trench between the spacer structures, and forming a metal gate electrode in the trench.

According to further example embodiments, a semiconductor device includes a substrate, a gate insulation layer on the substrate, a metal gate electrode on the gate insulation layer, a plurality of spacer structures on the substrate at sides of the metal gate electrode, source/drain regions in the semiconductor substrate at the sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extending from the bottom portion to cover at least a part of sidewalls of the spacer structures, an upper surface of the sidewall portion being between the substrate and an upper surface of the metal gate electrode.

According to still other example embodiments, a method of manufacturing a semiconductor device includes forming a gate stack including a gate insulation pattern, a gate sacrificial pattern and a capping pattern on a semiconductor substrate, forming spacer structures at sidewalls of the gate stack, forming source/drain regions in the semiconductor substrate at both sides of the gate stack, forming an etch stop pattern between an upper surface of the gate sacrificial pattern and the substrate such that the source/drain regions are covered, forming a gap fill insulation layer covering the etch stop pattern such that the capping pattern of the gate stack remains exposed, removing the capping pattern and the gate sacrificial pattern to form a trench between the spacer structures, and forming a metal gate electrode in the trench.

According to yet further example embodiments, a semiconductor device includes a first semiconductor layer, a metal gate on the first semiconductor layer, a plurality of spacer structures on sides of the metal gate, and an etch stop layer on the first semiconductor layer and sidewalls of the spacer structures, a surface of the metal gate a greater distance from the first semiconductor layer than the etch stop layer.

DETAILED DESCRIPTION

Semiconductor devices according to example embodiments may include a highly integrated semiconductor devices, for example, a DRAM, SRAM, flash memory, micro electro mechanical systems (MEMS) device, optoelectronic device, and/or processor (e.g., CPU and/or DSP). A semiconductor device may be comprised of only the same type of semiconductor devices or may be a single chip data processing device comprised of different types of semiconductor devices necessary for providing a complete function.

FIGS. 1-10are cross-sectional diagrams illustrating methods of manufacturing semiconductor devices according to example embodiments of the inventive concepts. Referring toFIG. 1, a semiconductor substrate100with an active region defined by a device isolation layer102may be prepared. The semiconductor substrate100may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, and/or an epitaxial thin film substrate obtained by performing a selective epitaxial growth.

The device isolation layer102defining the active region may be formed by forming a trench in the semiconductor substrate100and then filling the trench with an insulation material. For example, the device isolation layer102may include Boron-Phosphor Silicate Glass (BPSG), High Density Plasma (HDP) oxide, Undoped Silicate Glass (USG), and/or Tonen SilaZene. The semiconductor substrate100may include wells101doped with n-type and/or p-type impurities to form NMOS and PMOS transistors. For example, the active region may include a p-type well101for forming an NMOS transistor and/or an n-type well101for forming a PMOS transistor.

Gate stacks110may be formed on the active region of the semiconductor substrate100. A gate stack110may be formed by sequentially stacking a gate dielectric layer, a gate conductive layer and a capping layer on the semiconductor substrate100and then patterning the gate dielectric layer, the gate conductive layer and the capping layer. A line width of a gate electrode of a semiconductor device may be determined by the patterning of the gate stack110. For example, the line width of the gate stack110may be about 10 nm to about 100 nm. The plurality of gate stacks110may be formed spaced apart by a distance from each other on the semiconductor substrate100.

The gate stack100may include a gate dielectric pattern111, a gate pattern113and/or a capping pattern115. The gate dielectric pattern111may include, for example, a silicon oxide layer, a silicon oxynitride layer, and/or a high-k dielectric layer. The gate dielectric pattern111may include one or more layers. A high-k dielectric layer may denote insulation materials with a dielectric constant higher than silicon oxide (e.g., tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, niobium oxide, cesium oxide, indium oxide, iridium oxide, barium strontium titanate (BST), and/or lead zirconate titanate (PZT)).

The gate pattern113may include a material with an etch selectivity with respect to silicon oxide, silicon oxynitride and/or silicon nitride. For example, the gate pattern113may include polysilicon doped with n-type or p-type impurities. The gate patterns113may include, for example, undoped polysilicon. The capping pattern115may be used as an etch mask while the gate pattern113is formed, and may include, for example, silicon nitride and/or silicon oxynitride. According to at least one example embodiment, the capping pattern115may be a silicon nitride layer deposited at a temperature of about 400° C. to about 600° C.

A first spacer SP1may be on both sidewalls of each of the gate stacks110. According to at least one example embodiment, the first spacer SP1may be formed by conformally depositing a silicon nitride layer on the entire surface of the semiconductor substrate100including the gate stacks110and performing a blanket anisotropic etch process (e.g., an etch back process). The silicon nitride layer may be deposited by using, for example, a thermal CVD, a plasma enhanced CVD, a remote plasma CVD, a microwave plasma CVD and/or an atomic layer deposition (ALD). According to at least one example embodiment, the first spacer SP1may be a silicon nitride layer formed by performing a thermal CVD process at a high temperature of about 700° C. to about 800° C. The first spacer SP1formed thus may have etch selectivity with respect to the capping pattern115of the gate stack110.

A silicon oxide layer may be conformally deposited on the entire surface of the semiconductor substrate100including the gate stacks110(e.g., prior to the forming of the silicon nitride layer). The silicon oxide layer may be formed by using, for example, a CVD and/or ALD process, and/or by thermally oxidizing the gate patterns113and the semiconductor substrate100. The silicon oxide layer formed thus may cure etch damage occurring in the sidewall of the gate pattern113while the gate pattern113is patterned, and may function as a buffer layer between the semiconductor substrate100and the silicon nitride layer. By, for example, anisotropically etching the silicon oxide layer and the silicon nitride layer, the first spacer SP1including an L-shaped oxide spacer121and the silicon nitride layer may be formed on both sidewalls of each of the gate stacks110.

According to at least one example embodiment, the first spacer SP1including silicon nitride may directly contact the sidewalls of the gate stack110and a surface of the semiconductor substrate100. The first spacer SP1formed thus may solve a short channel effect due to a distance between source and drain electrodes (i.e., a channel length decreases as the line width of the gate electrode in a MOSFET decreases). The first spacer SP1may increase a distance between lightly doped impurity regions131. Lightly doped impurity regions131doped with n-type or p-type impurities may be formed at both sides of the gate stacks110.

The light doped impurity regions131may be formed by implanting n-type or p-type impurity ions into the semiconductor substrate100by using the gate stacks110and the first spacers SP1as ion implantation masks. In this ion implantation, the p-type impurity may be boron (B) and the n-type impurity may be arsenic (As), for example. The lightly doped impurity region131may be self-aligned with the first spacer SP1. The lightly doped impurity region131may extend under the first spacer SP1due to impurity diffusion. According to at least one example embodiment, the lightly doped impurity region131may be formed by using the gate stack110as an ion implantation mask prior to the forming of the first spacer SP1.

A channel impurity region (not illustrated) may be formed by performing a halo ion implantation process (e.g., after the lightly doped impurity region131is formed). The channel impurity region may be formed by implanting impurity ions of an opposite conductive type to the lightly doped impurity region131. The channel impurity region may prevent a punch-through phenomenon by increasing the concentration of the active region under the gate stack110.

Referring toFIG. 2, a second spacer SP2covering sidewalls of the first spacer SP1at both sides of the gate stacks110may be formed. According to at least one example embodiment, the second spacer SP2may be formed by forming the lightly doped impurity region131, conformally depositing a silicon nitride layer on an entire surface of the semiconductor substrate100and then performing a blanket anisotropic etch process (e.g., an etch back process). The silicon nitride layer may be deposited by, for example, a thermal CVD, a plasma enhanced CVD, a remote plasma CVD, a microwave plasma CVD and/or an atomic layer deposition (ALD). According to at least one example embodiment, the silicon nitride layer of the second spacer SP2may be formed by using an atomic layer deposition at a temperature of about 400° C. to about 600° C. The second spacer SP2may have etch selectivity with respect to the first spacer SP1.

A silicon oxide layer may be conformally formed on the semiconductor substrate100(e.g., before the forming of the silicon nitride layer for forming the second spacer SP2). The silicon oxide layer may be formed by using, for example, CVD and/or ALD. The silicon oxide layer may cover the lightly doped impurity region131exposed to the atmosphere and may function as a buffer layer between the semiconductor substrate100and the silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be etched back to form the second spacer SP2constituting an L-shaped oxide spacer123covering the first spacer SP1and the silicon nitride layer.

A silicon oxide layer may be formed on the silicon nitride layer for forming the second spacer SP2(e.g., before performing the anisotropic etch process). The second spacer SP2may be formed by sequentially forming a silicon oxide layer, a silicon nitride layer and a silicon oxide layer and anisotropically etching the silicon oxide layer, silicon nitride layer and silicon oxide layer. The second spacer SP2including the silicon nitride layer may be L-shaped, and an upper oxide spacer125may be formed on the L-shaped second spacer SP2. The forming of the second spacer SP2may increase the distance between highly doped impurity regions133. According to other example embodiments, the second spacer SP2including the silicon nitride layer may directly contact the sidewall of the first spacer SP1and the surface of the semiconductor substrate100.

Heavily doped impurity regions133doped with an N-type or P-type impurity may be formed at both sides of the gate stacks110. For example, boron (B) may be used as a P-type impurity and arsenic (As) may be used as an N-type impurity. When the heavily doped impurity regions133are formed, a concentration of the impurity and the ion implantation energy may be greater than the concentration of the impurity and the ion implantation energy for forming the lightly doped impurity region131. A heat treatment process, for example, a rapid thermal process (RTP) and/or laser annealing (LSA) may be performed (e.g., after the ion implantation process).

After the heavily doped impurity regions133are formed, a source/drain including the lightly doped impurity region131and the heavily doped impurity region133may be formed in the active region between the gate stacks110. A plurality of gate structures may be formed on the semiconductor substrate100. The gate structure may include the gate stack110and the first and second spacers SP1and SP2at both sides of the gate stack110. MOSFETs may be on the semiconductor substrate.

When MOSFETs are formed, the line width of the gate electrode may decrease (e.g., may be reduced to increase integration density), whereby the distance between the gate stacks110may decrease. Because the first and second spacers SP1and SP2for securing the distance between the source and drain electrodes may be formed on the sidewalls of each of the gate stacks110, the forming of the first and second spacers SP1and SP2may decrease a region of the semiconductor substrate100exposed between the gate stacks110. The forming of the first and second spacers SP1and SP2may decrease the spacing between the gate structures. In a subsequent process of filling the gate structures with an insulating material, it may be difficult to completely fill a gap region between the gate structures with an insulating material. According to at least one example embodiment, before filling the gap region between the gate structures with an insulating material, forming of a silicide layer and forming of an etch stop pattern may be performed, as illustrated inFIGS. 2 and 3.

Referring toFIG. 2, a silicide layer135may be formed on the heavily doped impurity regions133. The forming of the silicide layer135may include forming a metal layer on the heavily doped impurity regions133, performing a heat treatment to react the metal layer with silicon, and removing metal which is not reacted with the silicon. For example, a metal layer may be conformally deposited on the semiconductor substrate100including the gate structures, and a heat treatment may be performed. The metal layer may include, for example, a refractory metal, for example, cobalt (Co), titanium (Ti), nickel (Ni) and/or tungsten (W). The metal layer may include, for example, a metal alloy with at least two of hafnium (Hf), tungsten (W), cobalt (Co), platinum (Pt), molybdenum (Mo), palladium (Pd), vanadium (V) and/or niobium (Nb).

A metal layer may be formed and a heat treatment may be performed. Some of the silicon of the heavily doped impurity region133may be consumed and the silicide layer135may be formed at the portion where silicon is consumed. The heat treatment may be performed at a temperature of about 250° C. to about 800° C. An RTP apparatus and/or a furnace may be used. The silicide layer135formed on the heavily doped impurity region133may be, for example, a cobalt silicide layer, a titanium silicide layer, a nickel silicide layer and/or a tungsten silicide layer. After the heat treatment for forming the silicide layer135, a wet etch process may be performed to remove metal which is not reacted with the silicon.

Referring toFIG. 3, an etch stop layer140may be, for example, conformally deposited on the semiconductor substrate100formed with the gate structures. According to at least one example embodiment, the etch stop layer140may cover a capping pattern115of the gate stack110, the spacer structure SP and the silicide layer135. As the etch stop layer is conformally formed on the semiconductor substrate100, the etch stop layer140may define a gap region between the gate structures. The etch stop layer140may be formed of a material with etch selectivity to insulation layers. According to at least one example embodiment, the etch stop layer140may include a material with etch selectivity to the first spacer SP1. The etch stop layer140may have etch selectivity with respect to the first and second spacers SP1and SP2. For example, the etch stop layer140may be formed of a silicon nitride layer and/or silicon oxynitride layer.

The etch stop layer140may include a silicon nitride layer. The etch stop layer140may be deposited using, for example, thermal CVD, plasma enhanced CVD, remote plasma CVD, microwave plasma CVD and/or atomic layer deposition. According to at least one embodiment, the silicon nitride layer of the etch stop layer140may be formed by using a plasma enhanced CVD at a temperature of about 250° C. to about 500° C. The etch stop layer140may have etch selectivity with respect to the first and second spacers SP1and SP2. The etch stop layer140may be used as an etch stop layer and may be used as a stress layer for applying stress to the channel region of a transistor.

The capping pattern115of the gate stack110, the first and second spacers SP1and SP2, and the etch stop layer140may be formed of or include a silicon nitride layer. The capping pattern115of the gate stack110, the first and second spacers SP1and SP2, and the etch stop layer140may have etch selectivity according to a hydrogen content of the silicon nitride layers. The hydrogen content of a silicon nitride layer may vary depending on, for example, a process temperature for depositing the silicon nitride layer. When a deposition process is used for forming a silicon nitride layer, the silicon nitride layer may be deposited by using a silicon source gas and a nitrogen source gas. The silicon source gas may be, for example, SIH4, Si2H6, SiH3Cl and/or SiH2Cl2. The nitrogen source gas may be, for example, NH3and/or N2. When a silicon nitride layer is formed by reacting these source gases, the silicon nitride layer may include hydrogen. The hydrogen content contained in the silicon nitride layer may decrease as the process temperature for forming the silicon nitride layer is elevated.

According to at least one example embodiment, the first spacer SP1may include about 2 atomic % to about 10 atomic % hydrogen based on a formation temperature of about 700° C. to about 800° C. using thermal CVD. The second spacer SP2may include a greater amount of hydrogen than the first spacer SP1when the second spacer SP2is formed at a temperature of about 400° C. to about 600° C., which may be lower than the deposition temperature of the first spacer SP1, by using an ALD. For example, the hydrogen content contained in the silicon nitride layer of the second spacer SP2may be about 10 atomic % to about 15 atomic %. The etch stop layer140may include a greater amount of hydrogen than the second spacer SP2when the etch stop layer140is formed at a temperature of about 250° C. to about 500° C., which is lower than the deposition temperature of the second spacer SP2, by using a PE-CVD. For example, the hydrogen content contained in the etch stop layer140may be about 10 atomic % to about 20 atomic %.

The first and second spacers SP1and SP2, and the etch stop layer140, which may be formed of silicon nitride layers, may have different etch rates from one another in a process of removing the silicon nitride layer when the first and second spacers SP1and SP2, and the etch stop layer140are formed at different process temperatures. According to other example embodiments, the etch stop layer140may be a silicon nitride layer formed by using an ALD at a temperature of about 400° C. to about 600° C., which may be similar to the deposition temperature of the second spacer SP2. According to still other example embodiments, the second spacer SP2may be formed at a temperature of about 700° C. to about 800° C. by using a thermal CVD, similarly to the first spacer SP1.

Referring toFIGS. 4 and 5, an etch stop pattern141may be selectively formed on the heavily doped impurity region133. The etch stop pattern141may be formed by locally removing the etch stop layer140from the upper surface of the gate structure. The forming of the etch stop pattern141may include forming a sacrificial insulation layer150on the etch stop layer140, locally forming a sacrificial insulation pattern151between the gate structures, and selectively removing the etch stop layer140formed on the gate structure. Referring toFIG. 4, the sacrificial insulation layer150on the etch stop layer140may include, for example, a high density plasma oxide (HDP), tetraethylorthosilicate (TEOS), plasma enhanced tetraethylorthosilicate (PE-TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), polymer and/or polysilicon.

According to at least one example embodiment, the sacrificial insulation layer150may be a layer formed by using a high density plasma-chemical vapor deposition (HDP-CVD). HDP-CVD is a technique which combines CVD and sputtering etch processes. HDP-CVD may deposit a silicon oxide layer by supplying a deposition gas for depositing a silicon oxide layer and an etch gas for etching an insulation layer together. The deposition gas and the etch gas for forming the silicon oxide layer may be ionized by plasma, and the deposition gas and etch gas which may be ionized may be accelerated toward the surface of the semiconductor substrate100. The accelerated deposition gas ions may form a silicon oxide layer and the accelerated etch gas ions may etch the deposited silicon oxide layer. While the sacrificial insulation layer150is formed, the deposition process and the etch process may be performed at the same time. Because the deposition rate may be faster than the etch rate, the sacrificial insulation layer150may be formed on the etch stop layer140.

When the sacrificial insulation layer150is formed by HDP-CVD, because the etch rate in an upper portion of the gap region between the gate structures is faster than the deposition rate, the sacrificial insulation layer150may be thinner in the upper portion of the gap region than in a lower portion of the gap region. The sacrificial insulation layer150formed by an HDP-CVD may have a conical profile, pointed at the top, on the gate structures, as illustrated inFIG. 4. The sacrificial insulation layer150with a difference in deposition thickness may be formed on the etch stop layer140by using HDP-CVD.

The sacrificial insulation layer150may be anisotropically etched to form a sacrificial insulation pattern151on the etch stop layer140between the gate structures. The sacrificial insulation pattern151may be formed by, for example, blanket-etching the sacrificial insulation layer150using an etch-back process. Because the sacrificial insulation layer150is thinly deposited at the upper portion of the gap region between the gate structures by using HDP-CVD, some of the etch stop layer140formed on the gate structure by the etch-back process may be exposed. The thickness of the sacrificial insulation layer150on the semiconductor substrate100and the gate structures may decrease to form the sacrificial insulation pattern151. The sacrificial insulation patterns151may be locally formed between the gate structures, as illustrated inFIG. 5.

An upper surface of the sacrificial insulation pattern151may be leveled lower than an upper surface of the gate pattern113. The sacrificial insulation pattern151may be left on the gate structure. The sacrificial insulation patterns formed thus may prevent the etch stop layer140on the heavily doped impurity region133from being removed while the etch stop layer140is etched. The etch stop layer140may be anisotropically and/or isotropically etched to form an etch stop pattern141by using the sacrificial insulation pattern151as a mask. As the etch stop pattern141is formed, an extended gap region may be formed between the gate structures.

According to at least one example embodiment, because a hydrogen content of the etch stop layer140may be different from the hydrogen content of the first and second spacers SP1and SP2, the etch stop layer140may have an etch selectivity with respect to the first and second spacers SP1and SP2, and the etch stop layer140may be selectively etched. The etch stop layer140exposed by the sacrificial insulation pattern151may be selectively etched so that upper portions of the first and second spacers SP1and SP2are exposed by the etch stop pattern141. Because the sacrificial insulation pattern151may be used as an etch mask, the etch stop pattern141may be left on the heavily doped impurity region133(e.g., silicide layer135). In a case where the sacrificial insulation pattern151is left on the gate structure, some of the etch stop layer140may be left on the gate structure when the etch stop pattern141is formed (e.g., on the top of the gate structure).

The etch stop pattern141may include a bottom portion covering an upper surface of the heavily doped impurity region133, and a sidewall portion extending from the bottom portion to partially cover the sidewall of the second spacer SP2. An upper surface of the sidewall portion may be positioned lower than an upper surface of the gate pattern113. For example, the distance from the upper surface of the bottom portion of the etch stop pattern141to the upper surface of the sidewall portion may be in a range of about 0% to about 80% of a distance from the upper surface of the semiconductor substrate100to the upper surface of the metal gate. The sidewall portion may have an angle less than or equal to 90 degrees with respect to the semiconductor substrate100according to shapes of the first and second spacers SP1and SP2. As the etch stop pattern141is formed as above, an upper width between the gate structures may increase. A gap fill margin of a gap fill insulation layer153may be secured.

Referring toFIG. 6, a gap fill insulation layer153filling the extended gap region between the gate structures may be formed. The gap fill insulation layer153may be formed of an insulation material with superior gap fill characteristic. For example, the gap fill insulation layer153may be formed of HDP oxide, TEOS, PE-TEOS, O3-tetra ethyl ortho silicate (O3-TEOS), undoped silicate glass (USG), PSG, BSG, BPSG, fluoride silicate glass (FSG), spin on glass (SOG), tonen silazene (TOSZ), or combinations thereof. The gap fill insulation layer153may be formed by using a deposition technique capable of providing superior step coverage. For example, the gap fill insulation layer153may be formed by using a CVD, spin coating and/or the like. The gap fill insulation layer153may be deposited to a sufficient thickness on the extended gap region and the gate structures.

According to at least one example embodiment, the gap fill insulation layer153may be formed of the same material as the sacrificial insulation pattern151. In this case, for example, the gap fill insulation layer153may cover upper surfaces of the sacrificial insulation pattern151and the etch stop pattern151. The gap fill insulation layer153may cover the upper surface of the sidewall portion of the etch stop pattern141. According to other example embodiments, the gap fill insulation layer153may be formed on the etch stop pattern141after the sacrificial insulation pattern151is removed.

A metal gate replacing process of replacing the gate pattern113with a metallic material may be performed. For example, in the case the gate pattern113includes an impurity doped polysilicon, when the line width of the gate pattern113is less than or equal to 100 nm, resistance may increase. In a process of forming impurity regions and the silicide layer135, the gate pattern113may be damaged due to a high temperature heat treatment process. In the case the gate pattern113is formed of a metallic material, it may be difficult to pattern the metallic material in a fine line width less than or equal to 100 nm, and the gate pattern113may be damaged due to a high temperature heat treatment process.

According to example embodiments of the inventive concepts, after the processes for forming the impurity regions31,133and the silicide layer135, which may be followed by a high temperature heat treatment process, are performed, the gate pattern113formed of polysilicon may be replaced by a metallic material. A metal gate electrode with a fine line width less than or equal to 100 nm, and superior and/or improved characteristic may be formed. A metal gate replacing process may include exposing an upper surface of the gate pattern113as illustrated inFIG. 7, selectively removing the gate pattern113to form a trench156between the first spacers SP1as illustrated inFIG. 8, and forming a metal gate electrode in the trench156as illustrated inFIG. 9.

Referring toFIG. 7, a process of planarizing the gap fill insulation layer153that forms a gap fill insulation pattern155may be performed until the gate pattern113is exposed. For the planarizing of the gap fill insulation layer153, an etch back process and/or chemical mechanical polishing (CMP) process may be used, for example. According to at least one example embodiment, the gap fill insulation layer153may be planarized by performing a CMP process until the upper surface of the capping pattern115is exposed. An etch back process may be performed to remove the capping pattern115, so that the upper surface of the gate pattern113may be exposed. The gap fill insulation layer153may be planarized to the upper surface of the gate pattern113by using a CMP process. Some portions of the first and second spacers SP1and SP2may be removed together.

As illustrated inFIG. 3, in a case where the etch stop layer140covers the first and second spacers SP1and SP2and the capping pattern115, when the gap fill insulation layer153is planarized for the metal gate replacing process, the etch stop layer140may be exposed together with the upper surface of the capping pattern115. In this case, while the capping pattern115including silicon nitride is removed, some portion of the etch stop layer140may be removed together with the capping pattern115. A dent may be generated at an upper surface of the planarized gap fill insulation layer153. The dent may cause a process failure when the gate pattern113is replaced by a metal pattern in a subsequent process. According to example embodiments of the inventive concepts, when the gap fill insulation layer153is planarized and the capping pattern115is removed, the etch stop pattern141formed of silicon nitride may not be exposed by the gap fill insulation layer153. A dent may not be generated at the upper surface of the gap fill insulation pattern155when the capping pattern115is removed.

Referring toFIG. 8, the gate pattern113may be removed to form a trench156between one pair of gate structures. The removing of the gate pattern113may be performed by a combination of a dry etch and a wet etch. Some of the gate pattern113exposed by the gap fill insulation layer153may be dry-etched. While some of the gate pattern113is dry-etched, an upper portion of the first spacer SP1may be also dry-etched. An inclination surface inclined inwardly may be formed at an upper portion of the first spacer SP1. An upper width of the trench156may be greater than a lower width of the trench156.

The gate patterns113may be wet-etched by using an etchant with etch selectivity to an interlayer dielectric and the first spacers SP1to form a trench156between one pair of first spacers SP1. For example, in the case the gate pattern113is formed of polysilicon, the gate pattern113may be wet-etched by using an etchant in which nitric acid, acetic acid and hydrofluoric acid are mixed. Before the wet etch process for etching the gate pattern113is performed, a process of removing a native oxide layer formed on a surface of the gate pattern113may be performed.

The trench156may expose inner walls of the first spacers SP1and an upper surface of the gate insulation pattern111. According to example embodiments, some portion of the gate pattern113may be left on the gate insulation pattern111as illustrated inFIG. 19. In this case, the etch process for removing the gate pattern113may prevent the gate insulation pattern111from being damaged. As illustrated inFIG. 9, a metal gate electrode163may be formed in the trench156.

The forming of the metal gate electrode163may include depositing a metal layer filling the trench156on the gap fill insulation pattern155, and planarizing the metal layer until the gap fill insulation pattern155is exposed. The metal layer may be formed by using, for example, CVD, physical vapor deposition (PVD) and/or ALD. For example, the metal layer may include tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel and/or conductive metal nitrides, or combinations thereof. The metal layer may be planarized by using an etch process and/or a CMP process until the gap fill insulation pattern155is exposed. The metal gate electrode163may be formed in the trench156. Because the gate electrode of the MOSFET is formed of a metallic material with low resistivity, operational characteristics of the semiconductor device may be enhanced.

According to example embodiments, a barrier metal layer161may be conformally formed in the trench156(e.g., before the metal layer is deposited). For example, the barrier metal layer161may include titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, zirconium nitride, or combinations thereof. The barrier metal layer161may prevent and/or reduce a metallic material from being diffused into the gate insulation pattern111and the semiconductor substrate100.

Referring toFIG. 10, contact plugs175connected to the silicide layer135may be formed. An interlayer dielectric170may be formed on the gap fill insulation pattern155(e.g., after the metal gate electrodes163are formed). For example, the interlayer dielectric may include an HDP oxide, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or combinations thereof.

The interlayer dielectric170, the gap fill insulation pattern155, the sacrificial insulation pattern151and the etch stop pattern141may be patterned to form contact holes exposing the silicide layer135. The forming of the contact holes may include, for example, forming a mask pattern on the interlayer dielectric170, and anisotropically etching the interlayer dielectric170, the gap fill insulation layer153and the sacrificial insulation pattern151by using the mask pattern. When the contact holes are formed in the interlayer dielectric170, the gap fill insulation pattern155and the sacrificial insulation pattern151may be etched by using an anisotropic etch process, and an upper surface of the etch stop layer141may be exposed. The contact hole exposing the silicide layer135may be formed by over-etching some of the etch stop pattern141exposed by the contact hole.

A conductive material may be filled into the contact holes to form contact plugs175. The contact plugs175may be formed of a metallic material with low resistivity. For example, the contact plug175may be formed of cobalt, titanium, nickel, tungsten, molybdenum, and/or a metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride and/or titanium aluminum nitride). A barrier metal layer (not shown) for preventing a metal element from being diffused may be formed (e.g., before the contact plug175is formed). The barrier metal layer may conformally cover an inner wall of the trench. The barrier metal layer may be formed conformally on inner walls of the gate insulation pattern111and the first spacer SP1. For example, the barrier metal layer may include a conductive metal nitride (e.g., tungsten nitride, titanium nitride and/or tantalum nitride).

The contact plug175may penetrate a portion of the etch stop pattern141and may be connected to the silicide layer135. While according to at least one example embodiment the contact plugs175may be connected to the silicide layers135, respectively, the connection of the contact plugs175may be changed selectively.

FIGS. 11-14are cross-sectional diagrams illustrating methods of manufacturing semiconductor devices according to other example embodiments of the inventive concepts. According to the example embodiments ofFIGS. 11-14and the example embodiments ofFIGS. 1-10, like reference numerals may denote like elements, and thus their description may be omitted. Gate stacks110, spacer structures SP and an etch stop layer140may be formed on a semiconductor substrate100, as described with reference toFIGS. 1-3. Referring toFIG. 3andFIG. 11, a sacrificial insulation pattern151exposing an upper portion of an etch stop layer140may be formed.

The forming of the sacrificial insulation pattern151may include, for example, forming a sacrificial insulation layer150covering the gate structures and then recessing an upper surface of the sacrificial insulation layer150to locally leave the sacrificial insulation pattern151between the gate structures. The sacrificial insulation layer150may be formed on the etch stop layer140to a sufficient thickness such that a gap region between the gate structures may be filled. The sacrificial insulation layer150may cover an entire surface of the etch stop layer140. The sacrificial insulation layer150may include, for example, a HDP oxide, TEOS, PE-TEOS, O3-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or combinations thereof.

An upper surface of the sacrificial insulation layer150may be recessed to form a sacrificial insulation pattern151on the etch stop layer140covering the semiconductor substrate100. The sacrificial insulation pattern151may be formed by, for example, wet-etching the sacrificial insulation layer150such that the etch stop layer140covering an upper portion of the gate stack110is exposed. By the wet etching process, the upper surface of the sacrificial insulation layer150may be recessed to a point lower than an upper surface of the gate pattern113. The etch stop layer140covering upper portions of the gate stack110and the spacer structure SP may be exposed. The sacrificial insulation pattern151may be locally formed between the gate stacks110.

As described with reference toFIG. 5, the etch stop layer140exposed by the sacrificial insulation pattern151may be selectively removed to form an etch stop pattern141. The etch stop pattern141may be selectively formed on heavily doped impurity regions133(e.g., silicide layer135). An extended gap region may be formed between the gate structures.

Referring toFIG. 12, a gap fill insulation layer153covering the gate structures and the etch stop patterns141may be formed. As described with reference toFIG. 6, the gap fill insulation layer153may be formed of the same material as the sacrificial insulation pattern151. The gap fill insulation layer153may be formed to a sufficient thickness on the extended gap region between the gate structures and on the gate structures. The gap fill insulation layer153may cover the upper surfaces of the sacrificial insulation pattern151and the etch stop pattern141. The etch stop pattern141may be covered by the gap fill insulation layer153.

Referring toFIGS. 12-14, a metal gate replacing process may be performed. The metal gate replacing process may include exposing an upper surface of the gate pattern113as illustrated inFIG. 12, selectively removing the gate pattern113to form a trench between the first spacers SP1as illustrated inFIG. 13, and forming a metal gate electrode in the trench as illustrated inFIG. 14.

Referring toFIG. 12, the gap fill insulation layer153may be planarized by performing an etch back process or a CMP process until an upper surface of the capping pattern115is exposed. Gap fill insulation patterns154may be formed. An upper surface of the gate pattern113may be exposed by wet-etching the capping pattern115using, for example, an etchant containing phosphoric acid. The upper surface of the gate pattern113may be lower than the upper surface of the gap fill insulation pattern154, and the etch stop pattern141may not be exposed by the gap fill insulation layer154. Portions of the first and second spacers SP1and SP2adjacent to the capping pattern115may be removed together while removing the capping pattern115(e.g., capping pattern115of silicon nitride).

Referring toFIG. 13, an upper portion of the gate pattern113may be removed by performing a dry etch process. An upper width of a trench156may be greater than a lower width of the trench156by etching upper portions of the first and second spacers SP1and SP2. The trench156may be formed between the pair of first spacers SP1by wet-etching the gate patterns113using an etchant with etch selectivity to the interlayer dielectric and the first spacer SP1. Referring toFIG. 14, a metal gate electrode163may be formed in the trench156. The forming of the metal gate electrode163, as described with reference toFIG. 9, may include depositing a metal layer filling the trench156on the gap fill insulation pattern154, and etching the metal layer to locally form the metal gate electrode163in the trench156.

FIGS. 15-17are cross-sectional diagrams illustrating methods of manufacturing semiconductor devices according to still other example embodiments of the inventive concepts. With respect to the example embodiments ofFIGS. 15-17and the example embodiments ofFIGS. 1-10, like reference numerals may denote like elements, and the description of like elements may be omitted.

According to at least one example embodiment, as illustrated inFIG. 11, a sacrificial insulation pattern151may be formed on the etch stop layer140. At least portions of the etch stop layer140, the first and second spacers SP1and SP2, and the capping patterns115, which may include silicon nitride, may be removed at the same time by an anisotropic and/or isotropic etch process. As illustrated inFIG. 15, an upper surface of the gate pattern113may be exposed, and an upper surface of the sidewall of the etch stop pattern141may be positioned lower than the upper surface of the gate pattern113. An extended gap region may be formed between the gate stacks110. Because the sacrificial insulation pattern151is used as an etch mask, when the upper surface of the gate pattern113is exposed, the etch stop pattern141covering the heavily doped impurity region133(e.g., a silicide layer135) may be formed between the gate structures.

Referring toFIG. 16, a gap fill insulation pattern155filling the extended gap region between the gate stacks110may be formed. The gap fill insulation pattern155may include, for example, the same insulation material as the sacrificial insulation pattern151. The upper surface of the gate pattern113may be exposed by planarizing the gap fill insulation layer153to form the gap fill insulation pattern155. The gap fill insulation pattern155may cover the etch stop pattern141and the first and second spacers SP1and SP2. As described with reference toFIG. 8, a trench156may be formed by removing the gate pattern113. Referring toFIG. 17, a metal gate electrode163may be formed in the trench156.

FIG. 18is a perspective view illustrating semiconductor devices according to further example embodiments of the inventive conceptsFIGS. 19-25are cross-sectional diagrams illustrating semiconductor devices according to various example embodiments of the inventive concepts. Referring toFIG. 18, a semiconductor device according to at least one example embodiment may include a metal gate electrode MG on a semiconductor substrate100, impurity regions131and133in the semiconductor substrate100at both sides of the metal gate electrode MG, an etch stop pattern141covering spacer structures (SP) at both sides of the metal gate electrode MG, the impurity regions131and133, and a portion of sides of the spacer structures SP.

The semiconductor substrate100may include an active region defined by a device isolation layer (not shown). The semiconductor substrate100may include wells (not shown) doped with an n-type or p-type impurity in order to form NMOS and PMOS transistors. The plurality of metal gate electrodes MG may be disposed on the active region, and a gate insulation pattern111may be between the semiconductor substrate100and the metal gate electrodes MG. The n-type and p-type impurity regions131and133may be in the semiconductor substrate100at the both sides of the metal gate electrodes MG. Spacer structures SP may be on the semiconductor substrate100at the both sides of the metal gate electrodes MG.

The impurity regions131and133may include a lightly doped impurity region131and a heavily doped impurity region133. A silicide layer135may be on the surface of the heavily doped impurity region133. According to at least one example embodiment, the lightly doped impurity region131may be aligned with a sidewall of the metal gate electrode MG, and/or a sidewall of a first spacer SP1. The heavily doped impurity region133may be aligned with a sidewall of a second spacer SP2. The spacer structure SP may include a first spacer SP1covering the sidewall of the metal gate electrode MG, and the second spacer SP2covering the sidewall of the first spacer SP1. The first and second spacers SP1and SP2may cover a portion of the semiconductor substrate100. For example, the first and second spacers SP1and SP2may be “L” shaped. Spacer structures SP spaced apart to face each other may be disposed between the adjacent metal gate electrodes MG.

An etch stop pattern141may be on the semiconductor substrate100between the metal gate electrodes MG. The etch stop pattern141may include a bottom portion covering the heavily doped impurity region133and a sidewall portion extending from the bottom portion to cover a portion of the sidewall of the second spacer SP2. The bottom portion of the etch stop pattern141may cover the silicide layer135on the heavily doped impurity region133. An upper surface of the sidewall portion of the etch stop pattern141may be positioned lower than the upper surface of the metal gate electrode MG. A height of the sidewall portion of the etch stop pattern141(e.g., a distance from an upper surface of the bottom portion of the etch stop pattern141to the upper surface of the sidewall portion) may vary. For example, the distance from an upper surface of the bottom portion of the etch stop pattern141to the upper surface of the sidewall portion may be about 0% to about 80% of a distance from the upper surface of the substrate100to the upper surface of the metal gate.

The upper surface of the sidewall portion of the etch stop pattern141may be positioned lower than the upper surfaces of the spacers SP1and SP2. The bottom portion of the etch stop pattern141may cover the entire surface of the heavily doped impurity region133(e.g., the silicide layer135). Between the adjacent metal gate electrodes MG, an area of the region overlapping between the etch stop pattern141and the semiconductor substrate100may be larger than an area of the region overlapping between the spacer structure SP and the semiconductor substrate100. The etch stop pattern141between a metal gate electrode MG and the device isolation layer may extend to the device isolation layer.

The first and second spacers SP1and SP2and the etch stop pattern141may include a silicon nitride layer with hydrogen. A hydrogen content of the first and second spacers SP1and SP2, and the etch stop pattern141may be different from each other. For example, the hydrogen content in the etch stop pattern141may be greater than the hydrogen content in the first and second spacers SP1and SP2. The etch stop pattern141may be thicker than the first and second spacers SP1and SP2.

A contact hole171through which a contact plug175penetrates may be in the etch stop pattern141. An area of the contact hole171may be substantially the same as a cross-sectional area of the contact plug175. Because the contact plug175penetrates the etch stop pattern141, the contact plug175may directly contact the etch stop pattern141. The contact plug175may penetrate a sacrificial insulation pattern (not shown) and a gap fill insulation pattern155on the etch stop pattern141, and may be connected to the silicide layer135under the etch stop pattern141.

The sacrificial insulation pattern and gap fill insulation pattern155may be on the etch stop layer141. The sacrificial insulation pattern and gap fill insulation pattern155may include the same material (e.g., may be silicon oxide). An interface may not be formed between the sacrificial insulation pattern and gap fill insulation pattern155. An upper surface of the gap fill insulation pattern155may be at the same plane as the upper surface of the metal gate electrode MG. The gap fill insulation pattern155may cover the upper surface of the sidewall portion of the etch stop pattern141. Between the adjacent metal gate electrodes MG, a width of the gap fill insulation pattern155may be greater than that of the sacrificial insulation pattern. The gap fill insulation pattern155may bury the etch stop pattern141between the adjacent metal gate electrodes MG.

The metal gate electrode MG may be on the gate insulation pattern111between the first spacers SP1. According to at least one example embodiment, the metal gate electrode MG may include a barrier metal layer161and a metal pattern163. The metal pattern163may include a metallic material, for example, tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, and/or nickel. The barrier metal layer161may extend from between the metal pattern163and the gate insulation pattern111to between the metal pattern163and the first spacer SP1. The barrier metal layer161may include a conductive metal nitride, for example, a titanium nitride, a tantalum nitride, a tungsten nitride, a hafnium nitride, and/or a zirconium nitride. According to at least one other example embodiment, as illustrated inFIG. 19, the metal gate electrode MG may also include a polysilicon pattern114between the gate insulation pattern111and the metal pattern163.

Referring toFIG. 20, according to at least one example embodiment, a spacer structure SP may include first and second spacers SP1and SP2, in which the second spacer SP2may cover a portion of the sidewall of the first spacer SP1. The upper surface of the second spacer SP2may be lower than the upper surface of the metal gate electrode MG. The second spacer SP2and the etch stop pattern141may include a material with etch selectivity to the first spacer SP1. For example, the second spacer SP2and the etch stop pattern141may be, for example, a silicon nitride layer including hydrogen, in which a hydrogen content of the second spacer SP2and a hydrogen content of the etch stop pattern141may be greater than a hydrogen content of the first spacer SP1. When the upper surface of the second spacer SP2is positioned lower than the upper surface of the metal gate electrode MG, the gap fill insulation pattern155may cover the upper surface of the sidewall portion of the etch stop pattern141and the upper surface of the second spacer SP2.

Referring toFIG. 21, according to at least one example embodiment, an etch stop pattern143covering the upper surface of the silicide layer135may include a bottom portion parallel to the semiconductor substrate100without a sidewall portion having a slope with respect to the semiconductor substrate100. Referring toFIG. 22, according to at least one example embodiment, a spacer structure SP at the both sides of the metal gate electrode MG may include a first spacer SP1. The sidewall portion of the etch stop pattern141may cover a portion of a sidewall of the first spacer SP1.

Referring toFIG. 23, according to at least one example embodiment, a spacer structure SP may include first and second spacers SP1and SP2, in which heights of the first and second spacers SP1and SP2, and a height of a sidewall portion of an etch stop pattern141may be different from each other. For example, the height of the sidewall portion of the etch stop pattern141may be less than the height of the second spacer SP2, and the height of the first spacer SP1may be greater than the height of the second spacer SP2. The first spacer SP1may cover the entire sidewall of the metal gate electrode MG. According to example embodiments illustrated inFIG. 22, the gap fill insulation pattern155may cover upper surfaces of the first and second spacers SP1and SP2and the etch stop pattern141.

Referring toFIG. 24, according to at least one example embodiment, heights of first and second spacers SP1and SP2, and a height of a sidewall portion of an etch stop pattern141may be different from each other, and upper surfaces of the first and second spacers SP1and SP2and the etch stop pattern141may be lower than the upper surface of the metal gate electrode MG. A gap fill insulation layer155may cover the upper surfaces of the first and second spacers SP1and SP2and the etch stop pattern141, and may directly contact one sidewall of the metal gate electrode MG.

Referring toFIG. 25, according to at least one example embodiment, a semiconductor device may include a source/drain region protruding at both sides of the metal gate electrode MG. A semiconductor layer180, which may protrude from inside the semiconductor substrate100to over the surface of the substrate100, may be at both the sides of the metal gate electrode MG. For example, an upper surface of the semiconductor layer180may be higher than the upper surface of the gate insulation pattern111. The semiconductor layer180may be the same conductive type as the impurity regions131and133, and may be formed of a semiconductor material with a lattice constant different from a semiconductor material constituting the semiconductor substrate100. For example, the semiconductor layer180may be formed of silicon germanium and/or silicon carbide.

According to an example embodiment illustrated inFIG. 25, a silicide layer185may be disposed between an upper portion of the semiconductor layer180and an etch stop pattern141. The bottom portion of the etch stop pattern141may cover the semiconductor layer180. The sidewall portion of the etch stop pattern141may extend from the bottom portion to cover a portion of a sidewall of a spacer structure SP. An upper surface of the sidewall portion of the etch stop pattern141and a lower surface of the etch stop pattern141may be positioned lower than the upper surface of the metal gate electrode MG. The lower surface of the etch stop pattern141may be positioned between the upper surface of the gate insulation pattern111and the upper surface of the metal gate electrode MG.

FIGS. 26 and 27are drawings for schematically explaining electronic devices including semiconductor devices in accordance with some embodiments of the inventive concept.

Referring toFIG. 26, an electronic device1300including a vertical channel transistor in accordance with the some embodiments of the inventive concept may be may be a PDA, a laptop computer, a portable computer, a web tablet, a wireless phone, a cell phone, a digital music player, a wire/wireless electronic device or one of composite electronic devices including at least two those devices. The electronic device1300may include a controller1310, an input/output device1320such as a keypad, a keyboard, a display, etc., a memory1330and a wireless interface1340that are combined with one another through a bus1350. The controller1310may include, for example, one or more microprocessors, digital signal processors, micro controllers, or something like that. The memory1330may be used to store commands executed by the controller1310. The memory1330may be used to store user data. The memory1330may include a vertical channel transistor in accordance with the some embodiments of the inventive concept. The electronic device1300may use the wireless interface1340to transmit data to a wireless communication network communicating using a RF signal and/or receive data from the network. For example, the wireless interface1340may include an antenna, a wireless transceiver, etc. The electronic device1300may be used in a communication interface protocol of a third generation such as CDMA, GSM, NADC, E-TDMA, CDMA2000.

Referring toFIG. 27, the semiconductor devices in accordance with embodiments of the inventive concept may be used to embody a memory system. The memory system1400may include a memory device1410to store huge amounts of data and a memory controller142. The memory controller142controls the memory device1410to read data from the memory device1410or write data in the memory device1410in response to a read/write request of a host1430. The memory controller1420may constitute an address mapping table to map an address provided from a mobile device or a computer system into a physical address of the memory device1410. The memory device1410may include the semiconductor devices in accordance with embodiments of the inventive concept.

According to example embodiments of the inventive concepts, semiconductor devices may include an etch stop pattern covering source/drain regions at a level lower than an upper surface of a metal gate electrode. Therefore, when source/drain electrodes are formed on a semiconductor substrate and a metal gate electrode is formed, partial etch of the etch stop layer that generates a process failure may be prevented.