Semiconductor device and method of fabricating the same

A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.

BACKGROUND

The background description presented herein is for the purpose of generally providing context for the disclosure. Work of the presently named inventor(s), to the extent such work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Modern electronic devices such as computers, portable communication devices, and the like include semiconductor memories to store data for performing various tasks. Some semiconductor memories store data using a variable resistance element, which has different resistance states in response to a voltage or current applied thereto. These semiconductor memories include a resistive random access memory (RRAM), a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), a magneto-resistive random access memory (MRAM), an E-fuse, and the like.

As electronic devices become smaller and more versatile, the semiconductor memories included in the electronic devices continue to decrease in size and increase in degree of integration. Such continued scaling of the semiconductor memories leads to manufacturing issues such as increasing complexity of fabrication processes and manufacturing costs.

SUMMARY

Various embodiments are directed to a semiconductor device and a method of fabricating the same, which reduce a number of manufacturing processes and manufacturing costs.

An embodiment is directed to a semiconductor device including a memory cell that has an electrode formed using a sidewall spacer fabrication process.

In an embodiment, a semiconductor device comprises a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.

In an embodiment, a semiconductor device comprises a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; an insulation layer disposed between two neighboring second conductive layers including said second conductive layer; and a variable resistance layer extending in the second direction and disposed between the first and second conductive layers. The second conductive layer is formed by performing a process of forming sidewall spacers on sidewalls of the insulation layer.

In an embodiment, a method of fabricating a semiconductor device comprises forming a first conductive layer over a substrate, the first conductive layer extending in a first direction; forming a variable resistance layer over the first conductive layer, the variable resistance layer extending in a second direction, the first and second directions being substantially perpendicular to each other; and forming two neighboring second conductive layers extending in the second direction over the first conductive layer so that an upper portion of the variable resistance layer is disposed between lower portions of the two neighboring second conductive layers. The forming of the two neighboring second conductive layers includes forming sidewall spacers on both sidewalls of the upper portion of the variable resistance layer so that upper portions of the sidewall spacers are disposed at a higher level than a top surface of the variable resistance layer; and forming the two neighboring second conductive layers by removing a top portion of the sidewall spacers by a predetermined depth.

In an embodiment, a method of fabricating a semiconductor device comprises forming a first conductive layer over a substrate, the first conductive layer extending in a first direction; forming a variable resistance layer over the first conductive layer, the variable resistance layer extending in a second direction, the first and second directions being substantially perpendicular to each other; and forming a second conductive layer over the variable resistance layer extending in the second direction. The forming of the second conductive layer includes forming a sidewall spacer over the variable resistance layer and removing a top portion of the sidewall spacer by a predetermined depth.

DETAILED DESCRIPTION OF EMBODIMENTS

Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments.

FIG. 1Ais a perspective view illustrating a semiconductor device in accordance with an embodiment of the disclosure. The semiconductor device includes a first conductive layer110that extends in a first direction (e.g., the direction of a line A-A′) and a second conductive layer130that extends in a second direction (e.g., the direction of a line B-B′), which crosses the first direction. In an embodiment, the first direction is substantially perpendicular to the second direction.

The semiconductor device also includes a variable resistance layer120that extends in the second direction and is disposed between the first conductive layer110and the second conductive layer130. The variable resistance layer120is formed over the first conductive layer110and disposed between lower portions of two neighboring second conductive layers130.

In an embodiment, the first and second conductive layers110and130are configured to function as electrodes. Although not shown in the perspective view ofFIG. 1A, a cross-section of the first and second conductive layers110and130is similar to a cross-section of a sidewall spacer whose top portion has been removed, as shown in View C. In a memory cell array of the semiconductor device, the first conductive layer110may correspond to a bit line, and the second conductive layer130may correspond to a word line, and vice versa. The variable resistance layer120corresponds to a variable resistance element.

In an embodiment, each variable resistance layer120is shared by two upper electrodes, i.e., two second conductive layers130so that two memory cells are formed between the two upper electrodes and one lower electrode, i.e., one first conductive layer110. As shown inFIG. 1A, an upper portion of the variable resistance layer120is disposed between lower portions of two second conductive layers130. Since one variable resistance layer120is shared by two second conductive layers130, the two memory cells are formed within a width w, which includes widths of two second conductive layers130and a width of one variable resistance layer120.

In a conventional semiconductor device, a memory cell includes one variable resistance layer coupled to a single upper electrode. In a memory cell in accordance with an embodiment, however, a variable resistance layer is coupled to two upper electrodes. In this manner, a number of variable resistance layers120may be reduced and a degree of integration of memory cells in the semiconductor device remains high, compared to a memory cell having one variable resistance layer over which one upper electrode is disposed.

The first and second conductive layers110and130may include any material that is electrically conductive to transmit electrical signals therethrough. In an embodiment, the material includes metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), or metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN).

The variable resistance layer120acting as the variable resistance element has a resistance state that changes in response to an input signal (e.g., voltage or current) applied to the first and second conductive layers110and130. In an embodiment, in order to store a two-bit data (e.g., logic high and low data), the variable resistance layer120has two different resistance states (e.g., high and low resistance states) determined depending on the input signal. For example, the high and low resistance states correspond to logic high and low data, respectively.

The variable resistance layer120may include a single layer or a plurality of layers. In an embodiment, the variable resistance layer120has a stacked layer structure of at least two different layers, which show the variable resistance characteristics in combination.

Referring toFIGS. 1B and 1C, the variable resistance layer120has a stacked layer structure that may includes a reservoir layer120A or120A′ and a tunnel barrier layer120B or a selector layer120B′ over the first conductive layer110and a substrate140. In an embodiment, the selector layer120B′ has a multi-layer structure including a tunnel barrier layer.

The reservoir layer120A or120A′ is provided to supply oxygen vacancies to the tunnel barrier layer120B or the selector layer120B′, so that a plurality of current paths (or filaments) is formed in the tunnel barrier layer120B or the selector layer120B′. Specifically, when a voltage is applied to the first and second conductive layers110and130to create an electric field across the reservoir layer120A or120A′ and the tunnel barrier layer120B or the selector layer120B′, oxygen vacancies migrate from the reservoir layer120A or120A′ into the tunnel barrier layer120B or the selector layer120B′.

When the applied voltage is higher than a predetermined value so that a sufficient number of the oxygen vacancies are injected into the tunnel barrier layer120B or the selector layer120B′, a plurality of filaments is formed in the tunnel barrier layer120B or the selector layer120B′. As a result, a resistance value of the tunnel barrier layer120B or the selector layer120B′ decreases, and thus a total resistance value of the variable resistance layer120is “set” to a low resistance state corresponding to, e.g., the logic low data.

On the other hand, the variable resistance layer120may be “reset” to a high resistance state corresponding to, e.g., the logic high data. For example, in a unipolar switching mode, a portion of the filaments formed in the tunnel barrier layer120B or the selector layer120B′ disappears by diffusion of the vacancies at an elevated temperature after a given voltage is applied to an electrode for a predetermined time. Alternatively, in a bipolar switching mode, when a negative voltage is applied to an electrode, the negative voltage drives electrons into the tunnel barrier layer120B or the selector layer120B′ to fill the vacancies in a portion of the filaments formed near the electrode. As a result, the portion of the filaments formed near the electrode disappears and the variable resistance layer120is reset to the high resistance state.

In order to form filaments in the tunnel barrier layer120B or the selector layer120B′, the tunnel barrier layer120B or the selector layer120B′ includes a filament formation region having a predetermined thickness, e.g., t1inFIG. 1Bor t2inFIG. 1C. The predetermined thickness of the filament formation region is small enough to allow an electric field to penetrate through the tunnel barrier layer120B or the selector layer120B′, and thus the filaments to be formed in the tunnel barrier layer120B or the selector layer120B′. On the other hand, the predetermined thickness is large enough to prevent an electrical short from occurring through the tunnel barrier layer120B or the selector layer120B′. For example, the thickness t1or t2is in a range of 1 nm to 5 nm.

The selector layer120B′ is typically configured to prevent a sneak current from flowing through unselected memory cells. In another embodiment, the selector layer120B′ includes a tunnel barrier layer. A height h3of the selector layer120B′ may range from 5 nm to 30 nm.

A height h1of the reservoir layer120A is greater than the thickness t1of the filament formation region in the tunnel barrier layer120B. A height h2of the reservoir layer120A′ is greater than the thickness of t2of the filament formation region in the selector layer120B′. For example, the height h1or h2ranges from 10 nm to 50 nm.

In an embodiment, the tunnel barrier layer120B or the selector layer120B′ includes a substance (e.g., TiO2, Ta2O5, etc.) that satisfies a stoichiometric ratio. In an embodiment, the reservoir layer120A or120A′ includes an oxygen-deficient metal oxide material. The oxygen-deficient oxide material includes a substance that is deficient in oxygen compared to a substance that satisfies the stoichiometric ratio. For example, the reservoir layer120A or120A′ includes TiOx(x<2) or TaOy(y<2.5).

A semiconductor device may have a multi-layer structure including a plurality of vertically arranged variable resistance layers. In an embodiment, the semiconductor device includes a second variable resistance layer (not shown) that extends in the first direction (the line A-A′) and formed over the second conductive layer130. In this embodiment, similar to the variable resistance layer120, the second variable resistance layer (not shown) is disposed between lower portions of two neighboring third conductive layers (not shown) that extend in the first direction. The third conductive layers are formed over the second variable resistance layer in the same manner as the second conductive layer130. Additional conductive layers (not shown) and additional variable resistance layers (not shown) may be stacked in the same manner as described above.

In an embodiment, when a vertically stacked memory cell including the first variable resistance layer120is selected, the second conductive layer130may function as a bit line and the first conductive layer110may function as a word line. On the other hand, when another memory cell including the second variable resistance layer is selected, the second conductive layer130may function as a word line and the third conductive layer may function as a bit line. As such, each of the conductive layers may function as a bit line or a word line depending on which of adjacent memory cells is selected.

FIGS. 2A to 2Fare cross-sectional views illustrating a method for fabricating the first conductive layer110ofFIG. 1Ain accordance with an embodiment.FIGS. 2A to 2Fillustrate cross-sectional views taken along the line B-B′ ofFIG. 1A.

Referring toFIG. 2A, a substrate2-140is provided. In an embodiment, the substrate2-140includes a semiconductor substrate or an insulator substrate.

A first insulation layer240is formed over the substrate2-140. The first insulation layer240includes a material that is the same as a material used to electrically insulate the first conductive layer110from the second conductive layer130inFIG. 1A. In an embodiment, the first insulation layer240includes an oxide layer. In an embodiment, the oxide layer is deposited using a chemical vapor deposition (CVD) method such as a low-pressure (LP) CVD or a plasma-enhanced (PE) CVD, or a bias sputtering method. In another embodiment, the oxide layer is deposited by combining a high-density plasma (HDP) CVD with the bias sputtering method.

Referring toFIG. 2B, a photoresist material (not shown) is formed over the first insulation layer240and then patterned using a photolithography method, thereby forming photoresist layers250separated by an opening that has width w1. In an embodiment, an excimer laser source (e.g. KrF, ArF, etc.) is used to implement a photolithography resolution enhancement technique, for instance, immersion lithography. In an embodiment, the width w1is approximately 40 nm.

Referring toFIG. 2C, in order to reduce the width w1of the opening (e.g., approximately 40 nm), which is defined by two adjacent photoresist layers250inFIG. 2B, additional resolution enhancement techniques, such as reflow of the photoresist layers250and resolution enhancement of lithography by assist of chemical shrink (RELACS), are performed on the photoresist layers250. As a result, photoresist patterns260having an opening width w2are formed. In an embodiment, the opening width w2is approximately 20 nm. The opening width w2(e.g., approximately 20 nm) defined by two neighboring photoresist patterns260is smaller than the corresponding opening width w2(e.g., approximately 40 nm) defined by the two neighboring photoresist layers250inFIG. 2B.

Subsequently, a hard mask layer265is deposited over portions of the first insulation layer240that are exposed by the photoresist patterns260.

Referring toFIG. 2D, the photoresist patterns260are removed, and then the first insulation layer240is etched using the hard mask layer265as an etch mask. An etching rate of the hard mask layer265is lower than that of the first insulation layer240. As a result, an insulation pattern270is formed. In an embodiment, an anisotropic etching process, such as plasma etching (PE), reactive ion etching (RIE), high-density plasma etching (HDPE), or the like, is performed in a substantially vertical direction to form the insulation pattern270. Subsequently, the remaining portions of the hard mask layer265are removed.

Referring toFIG. 2E, after forming the insulation pattern270, a conductive film (not shown) is conformally deposited along a surface of the resultant structure including the substrate2-140and the insulation pattern270. After that, the conductive film is etched back in a substantially vertical direction using a highly anisotropic etching method (e.g., PE, RIE, HDPE, or the like) until the deposited conductive film remains only on sidewalls of the insulation pattern270. As a result, a conductive pattern280is formed to have a cross-section that is similar to a sidewall spacer, as illustrated inFIG. 2E.

Specifically, the conductive pattern280has a first side in contact with the insulation pattern270. In an embodiment, the first side is substantially vertical with respect to the substrate2-140along the surface contacting the insulation pattern270. If a top surface of the insulation pattern270is slightly smaller than a bottom surface of the insulation pattern270, a first side of the conductive pattern280contacting the insulation pattern270may be provided at a slight angle with respect to the substrate2-140.

The conductive pattern280has a curved portion at a second side. The curved portion includes a plurality of subsections, each of which corresponds to a circular arc approximating the curved portion at a point of the curved portion. A curvature is defined as an inverse of a radius of each subsection, (i.e., the circular arc at a point of the curved portion). Thus, the curved portion has the plurality of curvatures. These curvatures of the second side of the conductive pattern280results from the anisotropic etching of the conformally deposited conductive film. In an embodiment, the second side includes a curved upper portion corresponding to one finite curvature and a vertical lower portion corresponding to zero curvature (i.e., infinite radius). In other embodiments, due to non-uniformity of the conductive film and imperfect anisotropic etching, the second side may have a curved portion including a plurality of subsections with different curvatures. The plurality of curvatures of the second side may change from a top portion of the second side to a bottom portion of the second side. In an embodiment, the second side has subsections with curvatures decreasing from the top portion to the bottom portion of the second side.

This configuration of the conductive pattern280, where the sidewall of one side has a curved portion and the sidewall of the other side is vertical in a cross-sectional view, is similar to a shape that a sidewall spacer often has in a semiconductor device. Thus, as described in more detail below, a method for forming a conductive pattern according to an embodiment may be similar to that of forming a sidewall spacer having such a shape. Accordingly, for convenience of description, a conductive pattern and a method for forming the same in accordance with an embodiment may be described herein as that of a sidewall spacer. In addition, as used in this disclosure, the term “sidewall spacer shape” and similar terms refer to a configuration where, in a cross-sectional view, a structure has one sidewall with at least one curved portion and an opposing sidewall that is substantially vertical with respect to a substrate. However, one of skilled in the art will understand that such references are merely for convenience of description and are not intended to limiting.

Referring toFIG. 2F, a second insulation material fills spaces between the conductive patterns280and then the resultant structure is planarized to form a planarized insulation layer290. During the planarization process, e.g. chemical mechanical planarization, upper portions of the conductive pattern280and the insulation pattern270are also removed by a predetermined depth. As a result, a conductive layer2-110, which corresponds to the remaining portion of the conductive pattern280, is formed. For example, a height h4of the conductive layer2-110ranges from 40 nm to 100 nm. The conductive layer2-110includes a first side in contact with the remaining portion of the insulation pattern270, and a second side in contact with the planarized insulation layer290. A curvature of a top portion of the second side is determined by the planarization process. An area of the top surface of the conductive layer2-110over which the variable resistance layer120(seeFIG. 1A) will be formed is also determined by the planarization process. For example, a width w3of the top portion of the conductive layer2-110ranges from 10 nm to 20 nm. The conductive layer2-110functions as an electrode of a memory cell as described above with reference toFIG. 1A.

FIGS. 3A-3Eare cross-sectional views illustrating a method for fabricating the semiconductor device ofFIG. 1Bin accordance with an embodiment. The cross-sectional views are taken along the line A-A′ ofFIG. 1A.

Referring toFIG. 3A, a first conductive layer3-110is formed over a substrate3-140.

Referring toFIG. 3B, a reservoir layer3-120A is formed by performing substantially the same processes as used for fabricating the insulation pattern270inFIG. 2Ddescribed above with reference toFIGS. 2A-2D. The reservoir layer3-120A is formed using resolution enhancement techniques such as immersion lithography, PR reflow/RELACS, and highly anisotropic etching. The reservoir layer3-120A may have a width that is smaller than a minimum feature size obtained by performing a conventional photolithography method.

Subsequently, a tunnel barrier layer3-120B is conformally deposited along a surface of the resultant structure including the reservoir layer3-120A and an exposed portion of the first conductive layer3-110. Various deposition methods capable of forming a film with good step coverage may be used to form the tunnel barrier layer3-120B. In an embodiment, an atomic layer deposition (ALD) method is used to form the tunnel barrier layer3-120B.

Referring toFIG. 3C, a first insulation material layer330is formed over the tunnel barrier layer3-120B. In an embodiment, the first insulation material layer330includes an oxide layer. A material for forming the first insulation material layer330is deposited in a vertical direction with a small range of arrival angles by using an anisotropic deposition method such as a physical vapor deposition (PVD) method. For example, the material for forming the first insulation material layer330is deposited using collimated sputter deposition, ionized sputter deposition, or the like. As a result, the first insulation material layer330is not formed over a predetermined upper portion of sidewalls of the reservoir layer3-120A.

Referring toFIG. 3D, a second conductive pattern340is formed by performing substantially the same processes as used to form the conductive pattern280inFIG. 2E. As a result, the second conductive pattern340is formed to have a cross-section similar to a sidewall spacer.

Referring toFIG. 3E, a second insulation material layer is deposited to fill spaces between the second conductive patterns340and then is planarized to form a second insulation layer350. During the planarization process, the second conductive pattern340is also planarized to form a second conductive layer3-130. The second conductive layer3-130has similar geometric features to the first conductive layer2-110that is formed as described above with reference toFIG. 2F.

In an embodiment, the first and second insulation layers330and350are formed using the same material. Thus, in an embodiment, the first insulation layer330and the second insulation layer350include an oxide layer.

FIGS. 4A-4Eare cross-sectional views illustrating a method for fabricating the semiconductor device ofFIG. 1Cin accordance with an embodiment. The cross-sectional views are taken along the line A-A′ ofFIG. 1A.

Referring toFIG. 4A, a first conductive layer4-110is formed over a substrate4-140.

Referring toFIG. 4B, a reservoir material layer410is formed over the first conductive layer4-110. Subsequently, a selector material layer420is formed over the reservoir material layer410. In an embodiment, the selector material layer420is deposited using PVD, CVD, or ALD.

Referring toFIG. 4C, the reservoir material layer410and the selector material layer420are patterned by performing substantially the same processes as used for fabricating the insulation pattern270inFIG. 2D. As a result, a reservoir layer4-120A′ and a selector layer4-120B′ are formed to have a width that is smaller than a minimum feature size obtained by performing a conventional photolithography method.

Referring toFIG. 4D, a first insulation material layer430is formed over the selector layer4-120B′ and the first conductive layer4-110so that the layers form a vertical stack. In an embodiment, the first insulation material layer430is formed so that it is not provided on a predetermined upper portion of sidewalls of the selector layer4-120B′. In an embodiment, the first insulation material layer430includes an oxide layer. The first insulation material layer430may be formed by performing a deposition process such as collimated sputter deposition, ionized sputter deposition, or the like, that is used to form the first insulation material layer330shown inFIG. 3C. A thickness of the first insulation material layer430is greater than a thickness of the reservoir layer4-120A′and smaller than a total thickness of the reservoir layer4-120A′ and the selector layer4-120B′.

Subsequently, a second conductive pattern440is formed by performing substantially the same processes as used to form the conductive pattern280shown inFIG. 2E. As a result, the second conductive pattern440also has a cross-section similar to a sidewall spacer.

Referring toFIG. 4E, a second insulation material fills spaces between the second conductive patterns440and then is planarized to form a second insulation material layer450. During the planarization process, the second conductive pattern440is also planarized to form a second conductive layer4-130. The second conductive layer4-130has similar geometric features to the second conductive layer3-130shown inFIG. 3E. In an embodiment, the first and second insulation material layers430and450are formed using the same material.

FIG. 5Ais a perspective view illustrating a semiconductor device in accordance with another embodiment. The semiconductor device includes a first conductive layer510that extends in a first direction (e.g., a line A-A′), and a variable resistance layer520that extends in a second direction (e.g., a line B-B′) and is formed over the first conductive layer510. The semiconductor device also includes a second conductive layer530that extends in the second direction and is formed over the variable resistance layer520. In an embodiment, the first direction is approximately perpendicular to the second direction.

In an embodiment, the first and second conductive layers510and530are configured to function as electrodes. In a memory cell array of the semiconductor device, the first conductive layer510may correspond to a bit line, and the second conductive layer530may correspond to a word line, and vice versa.

The variable resistance layer520acts as a variable resistance element that has a resistance state changing in response to an input signal (e.g., voltage or current) applied to the first and second conductive layers510and530.

The variable resistance layer520may include a single layer or a plurality of layers. In an embodiment, the variable resistance layer520is a stacked structure of at least two different layers that show the variable resistance characteristics in combination.

Referring toFIG. 5B, the stacked structure includes a reservoir layer520A and a selector layer520B. In an embodiment, the selector layer520B includes a tunnel barrier layer.

In order to form filaments in the selector layer520B, a filament formation region in the selector layer520B may have a thickness t3that is sufficiently small to allow an electric field to penetrate therethrough and sufficiently large to prevent an electrical short from occurring through the selector layer520B. In an embodiment, the thickness t3ranges from 1 nm to 5 nm.

In an embodiment, the selector layer520B is configured to function as a selector to prevent sneak currents from flowing through unselected memory cells. In another embodiment, a selector (not shown) is formed over the selector layer520B.

A height h3of the reservoir layer520A may be greater than the thickness t3of the filament formation region in the selector layer520B. In an embodiment, the height h3ranges from 10 nm to 50 nm.

As shown in View C ofFIG. 5A, a cross-section of the second conductive layer530is similar to a sidewall spacer with a planarized top portion. The cross-section of the second conductive layer530has similar geometric features to the second conductive layer130shown inFIGS. 1B and 1C.

FIGS. 6A to 6Eare cross-sectional views illustrating a method for fabricating the semiconductor device ofFIG. 5B.

Referring toFIG. 6A, a first conductive layer6-510is formed over a substrate6-540by performing substantially the same processes as used for forming the conductive layer2-110inFIG. 2F. Subsequently, an insulation layer6-550is formed over the first conductive layer6-510by performing a lithography resolution enhancement technique such as immersion lithography, PR reflow/RELACS, or high anisotropic etching. The insulation layer6-550is formed to perpendicularly cross the first conductive layer6-510.

Referring toFIG. 6B, a reservoir material layer640is deposited over the insulation layer6-550and an exposed portion of the first conductive layer6-510in a substantially vertical direction with a small range of arrival angles by performing an anisotropic deposition method such as PVD method. For example, the reservoir material layer640is deposited using collimated sputter deposition, ionized sputter deposition, or the like, which is used to form the first insulation layer330inFIG. 3C.

After that, a selector material layer650is formed over the reservoir material layer640. The selector material layer650is deposited in a substantially vertical direction with a small range of arrival angles by performing an anisotropic deposition method such as PVD.

In another embodiment, the selector material layer650is conformally formed over the reservoir material layer640and the insulation layer6-550. Various deposition methods capable of forming a film with good step coverage (e.g., CVD and ALD) may be used to form the selector material layer650.

Referring toFIG. 6C, a conductive pattern660is formed on exposed sidewalls of the insulation layer6-550and sidewalls of the reservoir material layer640and the selector material layer650by performing substantially the same processes as used for forming the conductive pattern280inFIG. 2E. The conductive pattern660has a cross-section similar to a sidewall spacer.

Referring toFIG. 6D, the selector material layer650and the reservoir material layer640are etched back in a substantially vertical direction using the conductive pattern660as an etch mask, so that the selector material layer650and the reservoir material layer640remain under the conductive pattern660. During the etch-back process, an etching technique that is highly anisotropic (e.g., PE, RIE, or HDPE) may be used. As a result, a selector layer6-520B and a reservoir layer6-520A are formed under the conductive pattern660.

Referring toFIG. 6E, an insulation material is deposited to cover the resultant structure including the selector layer6-520B and the reservoir layer6-520A so as to fill spaces between the conductive patterns660, and then the deposited insulation material is planarized by a predetermined depth to form a planarized insulation layer6-560. During the planarization process, the conductive pattern660is also planarized to form a second conductive layer6-530. The second conductive layer6-530has geometric features similar to the second conductive layer3-130inFIG. 3E.

FIG. 7Aillustrates a semiconductor device in accordance with an embodiment, which has a multi-layer structure of a plurality of variable resistance layers. In an embodiment, the semiconductor device includes a second variable resistance layer740that extends in a first direction (e.g., a line A-A′) and is formed over a second conductive layer7-530. The second conductive layer7-530, a first variable resistance layer7-520, and a first conductive layer7-510correspond to the second conductive layer530, the variable resistance layer520, and the first conductive layer510inFIG. 5A, respectively. The semiconductor device further includes a third conductive layer750that extends in the first direction and is formed over the second variable resistance layer740. Additional conductive layers (not shown) and variable resistance layers (not shown) may be repeatedly stacked in the manner described above.

In a stacked structure ofFIG. 7A, the first to third conductive layers7-510,7-530, and750and the first and second variable resistance layers7-520and740form two vertically stacked memory cells, e.g., first and second memory cells. The first memory cell is implemented by the first conductive layer7-510, the first variable resistance layer7-520, and the second conductive layer7-530. The second memory cell is implemented by the second conductive layer7-530, the second variable resistance layer740, and the third conductive layer750. A detailed structure of the memory cells will be described with reference to embodiments shown inFIGS. 7B and 7C.

FIGS. 7B and 7Care cross-sectional views each illustrating a semiconductor device having a multi-layer structure in accordance with an embodiment. In these embodiments, each of first and second variable resistance layers includes a reservoir layer and a selector layer.

Referring toFIG. 7B, the semiconductor device includes a first stack structure ST1and a second stack structure ST2. The first stack structure ST1includes a first reservoir layer7-520A, a first selector layer7-520B, and a second conductive layer7-530. The second stack structure ST2includes a second reservoir layer740A, a second selector layer740B, and a third conductive layer750. In this embodiment, the first stack structure ST1includes layers stacked in the same order as those stacked in the second stack structure ST2. In the first and second stack structures ST1and ST2, the selector layers, e.g.,7-520B and740B, are formed over the reservoir layers, e.g.,7-520A and740A, respectively.

The first, second, and third conductive layers7-510,7-530, and750are configured to function as electrodes of memory cells. For example, when a vertically stacked memory cell including the first variable resistance layer7-520is selected, the second conductive layer7-530may function as a bit line and the first conductive layer7-510may function as a word line. On the other hand, when another memory cell including the second variable resistance layer740is selected, the second conductive layer7-530may function as a word line and the third conductive layer750may function as a bit line. As such, each of the conductive layers may function as a bit line or a word line depending on which one of adjacent memory cells is selected.

Referring toFIG. 7C, in an embodiment, the semiconductor device includes a first stack structure ST1and a second stack structure ST2. In this embodiment, the layers of the first stack structure ST1are stacked in a different order from those of the second stack structure ST2. Specifically, while the first selector layer7-520B is formed over the first reservoir layer7-520A in the first stack structure ST1, the second reservoir layer740A is formed over the second selector layer740B in the second stack structure ST2. Thus, the first variable resistance layer7-520and the second variable resistance layer740have a symmetrical structure with respect to the second conductive layer7-530. As a result, in an embodiment, the second conductive layer7-530is used as a shared bit line, and the first and third conductive layers7-510and750are used as word lines. In this embodiment, since the number of layers of the multi-layer structure in a cell array region is reduced using the shared bit line, fabrication processes of the semiconductor device may be simplified. Moreover, since control of activation and/or deactivation of bit lines and word lines becomes simpler, the number of decoders in a core region may be reduced. Manufacturing costs may be reduced at least for these reasons.

FIGS. 8A to 8Care cross-sectional views illustrating a method for fabricating a semiconductor device having the symmetrical structure ofFIG. 7Cin accordance with an embodiment. The cross-sections are taken along a line B-B′ ofFIG. 7A. One of skill in the art will understand that a method for fabricating a semiconductor device having the structure shown inFIG. 7Buses similar processes as those for fabricating a semiconductor device having the structure shown inFIG. 7C. Thus, a detailed description of a method for forming the structure shown inFIG. 7Bwill be omitted.

Referring toFIG. 8A, an insulation layer830is formed over a first stack structure ST1that is formed as described above with reference toFIGS. 6A to 6E. The insulation layer830is formed using lithography resolution enhancement techniques such as immersion lithography, PR reflow/RELACS, and high anisotropic etching.

After that, a selector material layer870is formed over the insulation layer830and an exposed portion of the first stack structure ST1. In this embodiment, the selector material layer870is deposited in a substantially vertical direction with a small range of arrival angles by using an anisotropic deposition method, e.g., PVD.

In another embodiment, the selector material layer870is conformally formed over the insulation layer830and the exposed portion of the first stack structure ST1. Various deposition methods such as CVD and ALD, which are capable of forming a film with good step coverage, may be used to form the selector material layer870.

Referring toFIG. 8B, a reservoir material layer880is deposited over the selector material870in a substantially vertical direction with a small range of arrival angles by using an anisotropic deposition method such as PVD. For example, the reservoir material layer880is deposited using collimated sputter deposition, ionized sputter deposition, or the like, which is used to form the reservoir material layer640shown inFIG. 6B.

Referring toFIG. 8C, the manufacturing processes described with reference toFIGS. 6C to 6Eare performed on the resultant structure including the reservoir material layer880and the selector material layer870. As a result, a second stack structure ST2including a second selector layer8-740B, a second reservoir layer8-740A, and a third conductive layer8-750is formed. In this embodiment, a first variable resistance layer8-520in the first stack structure ST1includes a first selector layer8-520B that is formed over a first reservoir layer8-520A, and a second variable resistance layer8-740in the second stack structure ST2includes the second reservoir layer8-740A that is formed over the second selector layer8-740B. Thus, the first variable resistance layer8-520and the second variable resistance layer8-740are formed to have a symmetrical structure with respect to a second conductive layer8-530in the first stack structure ST1.

FIG. 9is a configuration diagram of a microprocessor including a semiconductor device in accordance with an embodiment.

Referring toFIG. 9, the microprocessor900may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor900may include a memory unit910, an operation unit920, and a control unit930. The microprocessor900may be various types of processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit910is a part which stores data in the microprocessor900, as a processor register or a register. The memory unit910may include a data register, an address register and a floating point register. In addition, the memory unit910may include various registers. The memory unit910may perform the function of temporarily storing data for which operations are to be performed by the operation unit920, result data from performing the operations, and an address where data for performing of the operations are stored.

The memory unit910may include one of the above-described semiconductor devices. The memory unit910including a semiconductor device as described herein may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the memory unit910may become easy, scaling of the memory unit910may be possible and reliability of the memory unit910may be improved. As a consequence, a fabrication process of the microprocessor900is simplified, scaling of the microprocessor900may be possible, and the reliability of the microprocessor900may be improved.

The operation unit920is a part which performs operations in the microprocessor900. The operation unit920performs arithmetical operations or logical operations according to signals transmitted from the control unit930. The operation unit920may include at least one arithmetic logic unit (ALU).

The control unit930receives signals from the memory unit910, the operation unit920and an external device of the microprocessor900, performs extraction, decoding and controlling upon input and output of commands, and executes processing represented by programs.

The microprocessor900according to the present embodiment may additionally include a cache memory unit940which can temporarily store data to be inputted from an external device or to be outputted to an external device. In this case, the cache memory unit940may exchange data with the memory unit910, the operation unit920and the control unit930through a bus interface950.

FIG. 10is a configuration diagram of a processor including a semiconductor device in accordance with an embodiment.

Referring toFIG. 10, a processor1000may improve performance and realize multi-functionality by including various functions in addition to controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor1000may include a core unit1010, a cache memory unit1020, and a bus interface1030. The core unit1010is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit1011, an operation unit1012and a control unit1013. The processor1000may be various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The memory unit1011is a component which stores data in the processor1000, as a processor register or a register. The memory unit1011may include a data register, an address register and a floating point register. In addition, the memory unit1011may include various registers. The memory unit1011may perform the function of temporarily storing (i) data for which operations are to be performed by the operation unit1012, (ii) result data obtained by performing the operations and (iii) an address where data for performing of the operations are stored. The operation unit1012is a component which performs operations in the processor1000. The operation unit1012performs arithmetical operations or logical operations in response to signals from the control unit1013. The operation unit1012may also include at least one arithmetic logic unit (ALU). The control unit1013receives signals from the memory unit1011, the operation unit1012, and an external device of the processor1000, performs extraction, decoding, controlling upon input and output of commands, and executes processing represented by programs.

The cache memory unit1020is a part which temporarily stores data to compensate for a difference in data processing speed between the core unit1010operating at a high speed and an external device operating at a low speed. The cache memory unit1020may include a primary storage section1021, a secondary storage section1022, and a tertiary storage section1023. In general, the cache memory unit1020includes the primary and secondary storage sections1021and1022, and may include the tertiary storage section1023when high storage capacity is desired. When appropriate, the cache memory unit1020may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit1020may be changed according to a chip design. The speeds at which the primary, secondary, and tertiary storage sections1021,1022and1023store and discriminate data may be substantially the same or different. In the case where the speeds of the respective storage sections1021,1022and1023are different, the speed of the primary storage section1021may be set to be the fastest. At least one storage section of the primary storage section1021, the secondary storage section1022, and the tertiary storage section1023of the cache memory unit1020may include one of the above-described semiconductor devices. The cache memory unit1020including the semiconductor device in accordance with an embodiment may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the cache memory unit1020may become easy, scaling of the cache memory unit1020may be possible and the reliability of the cache memory unit1020may be improved. As a consequence also, a fabrication process of the processor1000may become easy, scaling of the processor1000may be possible and the reliability of the processor1000may be improved.

Although it was shown inFIG. 10that all the primary, secondary, and tertiary storage sections1021,1022and1023are configured inside the cache memory unit1020, the embodiments are not limited thereto. For example, it is to be noted that all the primary, secondary, and tertiary storage sections1021,1022and1023of the cache memory unit1020may be configured outside the core unit1010and may compensate for a difference in data processing speed between the core unit1010and the external device. For another example, the primary storage section1021of the cache memory unit1020may be disposed inside the core unit1010and the secondary storage section1022and the tertiary storage section1023may be configured outside the core unit1010to strengthen the function of compensating for a difference in data processing speed.

The bus interface1030is a part which connects the core unit1010and the cache memory unit1020for effective transmission of data.

As shown inFIG. 10, the processor1000according to an embodiment may include a plurality of core units1010, and the plurality of core units1010may share the same cache memory unit1020. The plurality of core units1010and the cache memory unit1020may be connected through the bus interface1030. The plurality of core units1010may be configured in substantially the same way as the above-described configuration of the core unit1010. In the case where the processor1000includes the plurality of core units1010, the primary storage section1021of the cache memory unit1020may be configured in each core unit1010, and the secondary storage section1022and the tertiary storage section1023may be configured outside the plurality of core units1010in such a way as to be shared through the bus interface1030.

In an embodiment, the processing speed of the primary storage section1021may be faster than the processing speeds of the secondary and tertiary storage section1022and1023.

The processor1000may further include an embedded memory unit1040which stores data, a communication module unit1050which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit1060which drives an external memory device, and a media processing unit1070which processes the data processed in the processor1000or the data inputted from an external input device and outputs the processed data to an external interface device. In addition, the processor1000may include a plurality of modules. In this case, the plurality of modules which are added may exchange data with the core units1010, the cache memory unit1020, and other units, through the bus interface1030.

The embedded memory unit1040may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), and the like. The nonvolatile memory may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magneto-resistive random access memory (MRAM), and the like.

The communication module unit1050may include both a module capable of being connected with a wired network and a module capable of being connected with a wireless network. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), and the like. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), and the like.

The memory control unit1060is to administrate data transmitted between the processor1000and an external storage device operating according to a different communication standard. The memory control unit1060may include various memory controllers, for example, controllers for controlling IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like.

The media processing unit1070processes the data processed in the processor1000or the data inputted from the external input device and output the processed data to the external interface device to be transmitted in the forms of image, voice and others, and may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio (HD audio), a high definition multimedia interface (HDMI) controller, and the like.

FIG. 11is a configuration diagram of a system in accordance with an embodiment.

Referring toFIG. 11, a system1100as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations on data. The system1100may include a processor1110, a main memory device1120, an auxiliary memory device1130, and an interface device1140. The system1100of the present embodiment may comprise one of various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and the like.

The processor1110controls decoding of inputted commands and processing such as operation, comparison, etc. for the data stored in the system1100, and may comprise a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like.

The main memory device1120is a memory which can call and execute programs or data from the auxiliary memory device1130when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device1120may include one of the above-described semiconductor devices. The main memory device1120including a semiconductor device as described herein may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the main memory device1120may become easy, scaling of the main memory device1120may be possible and the reliability of the main memory device1120may be improved. As a consequence also, a fabrication process of the system1100may become easy, scaling of the system1120may be possible and the reliability of the system1100may be improved. Also, the main memory device1120may further include a volatile memory such as a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like in which all contents are erased when power supply is cut off. Unlike this, the main memory device1120may not include the semiconductor devices according to the embodiments, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device1130is a memory device for storing program codes or data. While the speed of the auxiliary memory device1130is slower than the main memory device1120, the auxiliary memory device1130can store a larger amount of data. The auxiliary memory device1130may include one of the above-described semiconductor devices in accordance with the embodiments. The auxiliary memory device1130including the semiconductor device in accordance with the aforementioned embodiment may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the auxiliary memory device1130may become easy, scaling of the auxiliary memory device1130may be possible and the reliability of the auxiliary memory device1130may be improved. As a consequence, a fabrication process of the system1100may become easy, scaling of the system1100may be possible and the reliability of the system1100may be improved.

Also, the auxiliary memory device1130may further include a data storage system (see the reference numeral1200ofFIG. 12) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like. Unlike this, the auxiliary memory device1130may not include the semiconductor devices according to the embodiments, but may include data storage systems (see the reference numeral1200ofFIG. 12) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like.

The interface device1140may be to perform exchange of commands and data between the system1100of the present embodiment and an external device. The interface device1140may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), and a communication device. The communication device may include both a module capable of being connected with a wired network and a module capable of being connected with a wireless network. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), and the like. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), and the like.

FIG. 12is a configuration diagram of a data storage system in accordance with an embodiment.

Referring toFIG. 12, a data storage system1200may include a storage device1210which has a nonvolatile characteristic as a component for storing data, a controller1220which controls the storage device1210, and an interface1230for connection with an external device. The data storage system1200may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and the like, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like.

The controller1220may control exchange of data between the storage device1310and the interface1230. To this end, the controller1220may include a processor1221for performing an operation for and processing commands inputted through the interface1230from an outside of the data storage system1200.

The interface1230is to perform exchange of commands and data between the data storage system1200and the external device. In the case where the data storage system1200is a card type, the interface1230may be an interface which is compatible with a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like. In the case where the data storage system1200is a disk type, the interface1230may be an interface which is compatible with IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and the like.

The data storage system1200according to the present embodiment may further include a temporary storage device1240for efficiently transferring data between the interface1230and the storage device1210according to diversification and high performance of an interface with an external device, a controller and a system. The storage device1210and the temporary storage device1240for temporarily storing data may include one of the above-described semiconductor devices in accordance with the embodiments. The storage device1210or the temporary storage device1240including the semiconductor device in accordance with the aforementioned embodiment may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the storage device1210or the temporary storage device1240may become easy, scaling the storage device1210of the temporary storage device1240may be possible and the reliability of the storage device1210or the temporary storage device1240may be improved. As a consequence, a fabrication process of the data storage system1200may become easy, scaling of the data storage system1200may be possible and the reliability of the data storage system1200may be improved.

FIG. 13is a configuration diagram of a memory system in accordance with an embodiment.

Referring toFIG. 13, a memory system1300may include a memory1310which has a nonvolatile characteristic as a component for storing data, a memory controller1320which controls the memory1310, and an interface1330for connection with an external device. The memory system1300may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like.

The memory1310for storing data may include one of the above-described semiconductor devices in accordance with the embodiments. The memory1310including the semiconductor device in accordance with the aforementioned embodiment may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the memory1310may become easy, scaling of the memory1310may be possible and the reliability of the memory1310may be improved. As a consequence, a fabrication process of the memory system1300may become easy, scaling of the memory system1300may be possible and the reliability of the memory system1300may be improved. Also, the memory1310according to the present embodiment may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and the like, which have a nonvolatile characteristic.

The memory controller1320may control exchange of data between the memory1310and the interface1330. To this end, the memory controller1320may include a processor1321for performing an operation for and processing commands inputted through the interface1330from an outside of the memory system1300.

The interface1330is to perform exchange of commands and data between the memory system1300and the external device. The interface1330may be compatible with a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and the like.

The memory system1300according to the present embodiment may further include a buffer memory1340for efficiently transferring data between the interface1330and the memory1310according to diversification and high performance of an interface with an external device, a memory controller and a memory system. The buffer memory1340for temporarily storing data may include one of the above-described semiconductor devices in accordance with the embodiments.

The buffer memory1340including the semiconductor device in accordance with the aforementioned embodiment may include a first conductive layer extending in a first direction; a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other; and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction, wherein an upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including said second conductive layer. Through this, a fabrication process of the buffer memory1340may become easy, scaling of the buffer memory1340may be possible and the reliability of the buffer memory1340may be improved. As a consequence, a fabrication process of the memory system1300may become easy, scaling of the memory system1300may be possible and the reliability of the memory system1300may be improved.

Moreover, the buffer memory1340according to the present embodiment may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and the like, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and the like, which have a nonvolatile characteristic.

In another embodiment, the buffer memory1340may not include the semiconductor devices according to the embodiments, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and the like, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and the like, which have a nonvolatile characteristic.