Electro-optical device and electronic apparatus

A liquid crystal apparatus includes a scan line extending in a ±X direction, a data line extending in a ±Y direction that intersects with the ±X direction, a TFT having a semiconductor layer in which, at a position overlapping with the scan line in plan view, one source drain region and a channel region extend along the ±X direction, and at a position overlapping with the data line in plan view, another source drain region extends along the ±Y direction, and a first upper capacitance element and a second upper capacitance element provided at a position overlapping with the data line, so as to overlap with the other source drain region in plan view.

The present application is based on, and claims priority from JP Application Serial Number 2019-191773, filed Oct. 21, 2019, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to an electro-optical device and an electronic apparatus.

2. Related Art

In the past, as one of electro-optical devices, an active drive type liquid crystal apparatus including a transistor as a switching element for each pixel has been known. When such a liquid crystal device is used in a light modulating means such as a projector, incident light on the liquid crystal apparatus increases compared to a direct view type liquid crystal apparatus. The increased incident light makes it easier to generate light leakage current in a transistor region. The light leakage current may inhibit potential retention of pixels, and cause deterioration in display quality such as flickering, or display unevenness for each of the pixels. Thus, various attempts have been made to suppress the deterioration in display quality.

For example, JP-A-6-67207 discloses a liquid crystal display apparatus in which a pixel additional capacity is formed in a groove formed in a vertical direction with respect to a substrate, in order to increase a retention capacitor and improve potential retention characteristics of pixels. In addition, JP-A-2012-78624 proposes a retention capacitor that is a capacitance element provided so as to cover a Thin Film Transistor (TFT), in order to reduce light incident on a transistor region and increase the retention capacitor.

However, for the liquid crystal display apparatus described in JP-A-6-67207, there has been a problem in that it is difficult to increase the retention capacitor. In particular, it is desirable that a film thickness of a dielectric film is thin, in order to increase the retention capacitor. Compared to this, since a gate insulating film and the dielectric film are in an identical layer, it was difficult to reduce the film thickness of the dielectric film.

In addition, in the liquid crystal apparatus described in JP-A-2012-78624, there has been a problem in that structure becomes complex, the number of manufacturing steps are likely to increase, and manufacturing costs are difficult to reduce. In other words, there has been a demand for an electro-optical device that increases a retention capacitor and reduces manufacturing costs.

SUMMARY

An electro-optical device includes a scan line extending in a first direction, a data line extending in a second direction that intersects with the first direction, a transistor having a semiconductor layer in which, at a position overlapping with the scan line, one source drain region and a channel region extend along the first direction, and at a position overlapping with the data line, another source drain region extends along the second direction, and a capacitance element having a capacitance electrode provided, at a position overlapping with the data line, so as to overlap with the other source drain region.

The above electro-optical device may include a substrate, the substrate may include a recessed portion at a position overlapping with the data line, and the other source drain region may extend along a side surface and a bottom surface of the recessed portion.

The above electro-optical device may include an insulating layer in the recessed portion, and the other source drain region may extend on the insulating layer.

The above electro-optical device may include a pixel electrode provided corresponding to the transistor, and a first relay layer electrically coupled to the pixel electrode via a first contact hole, and the first contact hole may overlap with a second contact hole for electrically coupling a gate electrode of the transistor to the scan line.

In the above electro-optical device, a gate insulation layer of the transistor includes a silicon oxide film and a silicon nitride film, and a capacitance insulation layer of the capacitance element may be constituted only by a silicon nitride film.

In the above electro-optical device, a silicon nitride film may not be provided in a region of the semiconductor layer that does not overlap with the gate electrode and the capacitance electrode.

The above electro-optical device may include the pixel electrode provided corresponding to the transistor, the first relay layer electrically coupled to the pixel electrode, and a second relay layer electrically coupled to the first relay layer, the first relay layer and the second relay layer may each include a main body portion extending in the first direction, and overlapping with the semiconductor layer, and a protruding portion protruding in the second direction from the main body portion.

The above electro-optical device may include a capacitance wiring line electrically coupled to the capacitance electrode, and the capacitance wiring line and the capacitance electrode may each include a main body portion extending in the second direction, and overlapping with the data line, and a protruding portion protruding in the first direction from the main body portion, and overlapping with the semiconductor layer extending in the first direction.

In the above electro-optical device, the capacitance wiring line may include another protruding portion protruding toward an opposite side to the protruding portion, and overlapping with another semiconductor layer adjacent to the semiconductor layer.

The above electro-optical device may include a light shielding wall provided along a part of the semiconductor layer, and the light shielding wall may include an identical material to a material of the data line.

In the above electro-optical device, the gate electrode of the transistor may be electrically coupled to the scan line via the light shielding wall.

An electronic apparatus includes the above electro-optical device.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Here, in each of the following drawings, as necessary, X, Y, Z axes are assigned as mutually orthogonal coordinate axes, a direction indicated by each arrow is denoted as + direction, and a direction opposed to the + direction is denoted as a − direction. Note that, the a +Z direction may be referred to as an upper side and a −Z direction may be referred to as a lower side, and viewing in the +Z direction is referred to as viewing in plan view, or in a planar manner. Furthermore, in the following description, for example, a description for a substrate of “on the substrate” indicates any one of a case in which a component is disposed on the substrate in contact therewith, a case in which a component is disposed on the substrate via another structure, or a case in which a part of a component is disposed on the substrate in contact therewith, and another part is disposed on the substrate via another structure.

1. First Exemplary Embodiment

In the present exemplary embodiment, an active drive type liquid crystal apparatus including a thin film transistor as a transistor for each pixel will be described as an example of an electro-optical device. Note that, hereinafter, the thin film transistor is abbreviated as TFT. The liquid crystal apparatus can be used favorably as a light modulation device in a projection-type display apparatus as an electronic apparatus described below, for example.

1.1. Configuration of Liquid Crystal Apparatus

A configuration of the liquid crystal apparatus as an electro-optical device according to the present exemplary embodiment will be described with reference toFIG.1toFIG.3.FIG.1is a schematic plan view illustrating a configuration of a liquid crystal apparatus as an electro-optical device according to a first exemplary embodiment.FIG.2is a schematic cross-sectional view illustrating structure of the liquid crystal apparatus.FIG.3is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal apparatus. Here,FIG.2illustrates a cross section along a YZ plane including a line segment H-H′ inFIG.1.

As illustrated inFIG.1andFIG.2, a liquid crystal apparatus100of the present exemplary embodiment includes an element substrate10, a counter substrate20disposed and facing the element substrate10, and a liquid crystal layer50including liquid crystal sandwiched between the element substrate10and the counter substrate20.

For a substrate10sof the element substrate10, for example, a substrate such as a glass substrate or a quartz substrate is used. For a substrate20sof the counter substrate20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used.

A shape of the element substrate10in plan view is larger than that of the counter substrate20. The element substrate10is bonded to the counter substrate20, via a seal material40disposed along an outer edge of the counter substrate20. Liquid crystal having positive or negative dielectric anisotropy is encapsulated in a gap between the element substrate10and the counter substrate20to provide the liquid crystal layer50.

A display region E including a plurality of pixels P arrayed in a matrix is provided inside the seal material40. A partition portion24is provided surrounding the display region E, between the seal material40and the display region E. A dummy pixel region (not illustrated) that does not contribute to display is provided around the display region E.

The element substrate10is provided with a terminal portion in which a plurality of external coupling terminals104are arrayed. A data line driving circuit101is provided between a first side portion along the terminal portion, and the seal material40. In addition, an inspection circuit103is provided between the seal material40along a second side portion facing the first side portion and the display region E.

A pair of scan line driving circuits102are provided between the seal material40along a third side portion and a fourth side portion orthogonal to the first side portion and facing each other, and the display region E. Further, between the seal material40of the second side portion and the inspection circuit103, a plurality of wiring lines107coupling the two scan line driving circuits102are provided.

Wiring lines linked to the data line driving circuit101and the scan line driving circuit102are coupled to the plurality of external coupling terminals104arrayed along the first side portion. Note that, the arrangement of the inspection circuit103is not limited to the above.

Here, in the present specification, a direction along the first side portion is a ±X direction as a first direction. Further, a second direction that intersects with the first direction is a ±Y direction, that is a direction orthogonal to the first side and along the third side portion and the fourth side portion facing each other. In addition, a direction orthogonal to the ±X direction and the ±Y direction that is a normal line direction of the element substrate10and the counter substrate20is a ±Z direction.

As illustrated inFIG.2, on a surface of the element substrate10son a side of the liquid crystal layer50, a light-transmitting pixel electrode15and a TFT30as a transistor being a switching element, that are provided for each of the pixels P, and signal wiring line, and an alignment film18covering these components are provided. The TFT30and the pixel electrode15are constituent elements of the pixel P. The element substrate10includes the substrate10s, the pixel electrode15, the TFT30, the signal wiring line, and the alignment film18that are provided on the substrate10s. The pixel electrode15is provided corresponding to the TFT30.

The partition portion24, an insulating layer25formed covering the partition portion24, a counter electrode21as a common electrode provided covering the insulating layer25, and an alignment film22covering the counter electrode21are provided on the surface of the substrate20son a side of the liquid crystal layer50. The counter substrate20in the present exemplary embodiment includes at least the partition portion24, the counter electrode21, and the alignment film22. Note that, in the present exemplary embodiment, the example in which the common electrode is disposed on a side of the counter substrate20as the counter electrode21is illustrated, but the present disclosure is not limited thereto.

As illustrated inFIG.1, the partition portion24surrounds the display region E, and is provided at a position overlapping with the scan line driving circuit102and the inspection circuit103in a planar manner. Accordingly, light incident on these circuits from a side of the counter substrate20is shielded, and erroneous operation of the circuits due to the incident light is prevented. Further, unnecessary stray light is shielded so as not to be incident on the display region E, ensuring high contrast in display of the display region E.

The insulating layer25is formed of an inorganic material such as, for example, light-transmissive silicon oxide. The insulating layer25is provided so as to cover the partition portion24and such that a surface on a side of the liquid crystal layer50is flat.

The counter electrode21includes a transparent conductive layer such as an Indium Tin Oxide (ITO) film and an Indium Zinc Oxide (IZO) film, covers the insulating layer25, and is electrically coupled to vertical conducting portions106provided at four corners of the counter substrate20respectively. The vertical conducting portion106is electrically coupled to a wiring line on a side of the element substrate10.

The alignment film18covering the pixel electrode15, and the alignment film22covering the counter electrode21are selected based on an optical design of the liquid crystal apparatus100. Examples of a formation material of the alignment films18and22include an inorganic alignment film of silicon oxide or the like, and an organic alignment film of polyimide or the like.

The liquid crystal apparatus100thus configured is, for example, of a transmissive-type, and an optical design is adopted such as a normally white mode in which transmittance of the pixel P when voltage is not applied is larger than transmittance when voltage is applied, or a normally black mode in which the transmittance of the pixel P when voltage is not applied is smaller than the transmittance when voltage is applied. In the liquid crystal panel including the element substrate10and the counter substrate20, a polarizing element is disposed on each of a light incident side and light exit side in accordance with the optical design.

In the present exemplary embodiment, an example is described, in which the optical design of the normally black mode is applied, using the inorganic alignment films described as the alignment films18and22, and a liquid crystal material having negative dielectric anisotropy.

Next, an electrical configuration of the liquid crystal apparatus100will be described below with reference toFIG.3. As illustrated inFIG.3, the liquid crystal apparatus100includes a plurality of scan lines3, a plurality of data lines6, and a plurality of capacitance lines8disposed in parallel with the data lines6, as signal wiring lines insulated from one another and orthogonal to one another at least in the display region E. The scan line3extends in the ±X direction as the first direction. The data line6extends in the ±Y direction as the second direction intersecting with the first direction. Note that, inFIG.3, a direction in which the capacitance line8extends is the ±Y direction, but the present disclosure is not limited thereto.

The scan line3, the data line6, and the capacitance line8, and the pixel electrode15, the TFT30, and a capacitance element16in a region partitioned by these signal wiring lines, are provided, and these wiring lines and components constitute a pixel circuit of the pixel P. The pixel electrode15, the TFT30, and the capacitance element16are disposed for each the pixel P.

The scan line3is electrically coupled to a gate of the TFT30. Specifically, the data line6is electrically coupled to a data line side source drain region, that is one source drain region in the TFT30. The scan line3has a function to simultaneously control on and off of the TFTs30provided in an identical line. The pixel electrode15is electrically coupled to a pixel electrode side source drain region, that is another source drain region in the TFT30. A semiconductor layer including the source drain region of the TFT30will be described later.

The data lines6are electrically coupled to the above-described data line driving circuit101, and supply image signals D1, D2, . . . , and Dn supplied from the data line driving circuit101to the pixels P. The scan lines3are electrically coupled to the above-described scan line driving circuit102, and supply scan signals SC1, SC2, . . . , and SCm supplied from the scan line driving circuit102to the pixels P.

The image signal D1to the image signal Dn supplied from the data line driving circuit101to the data lines6may be line-sequentially supplied in this order, or may be supplied to the plurality of respective data lines6adjacent to each other in groups. The scan line driving circuit102line-sequentially supplies the scan signal SC1to the scan signal SCm to the scan lines3in a pulsed manner at predetermined timings.

In the liquid crystal apparatus100, the TFT30as the switching element is turned on only for a certain period of time by being inputted with the scan signal SC1to the scan signal SCm. Accordingly, the image signal D1to the image signal Dn supplied from the data lines6are written to the pixel electrodes15at predetermined timing. Then, the image signal D1to the image signal Dn having a predetermined level written into the liquid crystal layer50via the pixel electrodes15are held for a certain period of time between the pixel electrodes15and the counter electrodes21that are disposed facing the pixel electrodes15with the liquid crystal layer50interposed therebetween.

To prevent the image signal D1to the image signal Dn held from leaking, the capacitance elements16are electrically coupled in parallel with liquid crystal capacitance provided between the pixel electrodes15and the counter electrodes21. The capacitance element16is provided in a layer between the semiconductor layer described below of the TFT30and the capacitance line8. Details of the semiconductor layer and the capacitance element16will be described later.

Here, although not illustrated inFIG.3, the inspection circuit103described above is coupled to the data line6. Thus, in a manufacturing process of the liquid crystal apparatus100, the above image signals can be detected via the inspection circuit103, and it is possible to check malfunction and the like of the liquid crystal apparatus100.

Next, a configuration of the pixel P in the liquid crystal apparatus100will be described with reference toFIG.4.FIG.4is a schematic plan view illustrating arrangement of the pixels.

As illustrated inFIG.4, the pixels P in the liquid crystal apparatus100are arranged in a matrix in the ±X direction and the ±Y direction in the display region E. The pixel P has, for example, an opening area OP that is substantially rectangular in plan view. The opening area OP is surrounded by non-opening areas CL each having a light shielding property, extending in the ±X direction and in the ±Y direction, that are provided in a lattice pattern.

In the non-opening area CL extending in the ±X direction, the scan line3is provided. A conductive member having a light shielding property is used for the scan line3, and a part of the non-opening area CL is constituted by the scan line3.

In the non-opening area CL extending in the ±Y direction, the data line6is provided. A conductive member having a light shielding property is also used for the data line6, and a part of the non-opening area CL is constituted by the data line6.

The non-opening area CL is constituted by the scan line3, the data line6, the TFT30, the capacitance line8, and the like provided on the element substrate10. Furthermore, the non-opening area CL may include a light shielding portion provided in an identical layer to the partition portion24illustrated inFIG.2and that is a black matrix patterned in a lattice shape, in the counter substrate20.

In the non-opening area CL extending in the ±X direction, a contact hole is provided in a middle of the ±X direction corresponding to each of the pixels P, so as to sandwich the above-described TFT30in the ±Y direction. Thus, a width in the ±Y direction of the non-opening area CL is larger in the area where the contact hole is provided, compared to the other areas. In addition, in the non-opening area CL extending in the ±Y direction, the capacitance element16is provided between the pixels P adjacent to each other. Detailed structure of the pixel P including the contact hole and the capacitance element16described above will be described later.

The pixel electrode15that is substantially square in plan view is provided for each of the pixels P. The pixel electrode15is provided in the opening area OP such that an outer edge overlaps with the non-opening area CL. A plurality of the pixel electrodes15are arranged in a matrix corresponding to the pixels P.

The liquid crystal apparatus100of the present exemplary embodiment is of the transmissive-type as described above, and is configured assuming that light is incident from the side of the counter substrate20. As such, the element substrate10is provided with structure that reduces not only light directly incident on the TFT30, but also diffraction light, reflected light, and the like originating from the incident light. The liquid crystal apparatus100includes the capacitance element16with a retention capacitor increased.

Note that, an incident direction of light on the liquid crystal apparatus100is not limited from the side of the counter substrate20, but light may be incident from a side of the element substrate10. In addition, the liquid crystal apparatus100may have a configuration in which a focusing means such as a microlens that focuses incident light for each the pixel P is provided on a substrate on a side on which light is incident.

1.2. Configuration of Element Substrate

Next, structure of the element substrate10included in the liquid crystal apparatus100will be described with reference toFIG.5.FIG.5is a schematic cross-sectional view illustrating the structure of the element substrate. Note that, inFIG.5, each of a line A1-A2, a line C1-C2, and a line B1-B2inFIG.4is included, and three cross sections along the ±Z direction are illustrated side-by-side. Further,FIG.5does not illustrate the alignment film18.

As illustrated inFIG.5, the element substrate10of the liquid crystal apparatus100includes the substrate10s, the scan line3, the TFT30including a semiconductor layer30S and a gate electrode30G, the capacitance element16, the data line6, and a plurality of interlayer insulating layers described below. The substrate10sof the element substrate10has a trench TR as a recessed portion. First layer to sixth layer are stacked as a plurality of layers on the substrate10s.

The plurality of layers in the element substrate10include, in order from a lower side, the first layer including the scan line3, the second layer including the semiconductor layer30S, the third layer including the gate electrode30G, the fourth layer including the data line6, the fifth layer including the capacitance line8as a capacitance wiring line, and the sixth layer including the pixel electrode15.

A first interlayer insulating layer11ais provided between the first layer and the second layers, a gate insulation layer11band a capacitance insulation layer16bare provided between the second layer and the third layer, a second interlayer insulation layer11cis provided between the third layer and the fourth layer, and a third interlayer insulation layer12is provided between the fourth layer and the fifth layer, and a fourth interlayer insulation layer13is provided between the fifth layer and the sixth layer. This prevents occurrence of a short circuit between the layers. Here, the first interlayer insulating layer11ais an example of an insulating layer on an inside of the trench TR in the present disclosure.

The scan line3is provided in the first layer on the substrate10s. The scan line3is provided in the non-opening area CL illustrated inFIG.4in plan view. The scan line3includes a site extending in the ±X direction, and a site protruding in the ±Y direction from the extending site.

A known formation material having a light shielding property and electrical conductivity can be adopted for the scan line3. Thus, the scan line3has a function to shield light incident on the semiconductor layer30S primarily from the lower side. In the present exemplary embodiment, tungsten silicide is used as the formation material of the scan line3. A thickness of the scan line3is not particularly limited, but is approximately 150 nm, for example. Note that, in the present specification, a thickness of each layer in the ±Z direction is also simply referred to as a “thickness”.

The first interlayer insulating layer11ais provided between the scan line3and the second layer. The first interlayer insulating layer11ainsulates the scan lines3and the TFT30from each other. Further, the first interlayer insulating layer11ais provided extending to the inside of the trench TR described below.

A silicon-based oxide film or the like is adopted as a formation material of the first interlayer insulating layer11a. Examples of the formation material include, for example, silicon oxide (None-doped Silicate Glass (NSG), silicon nitride, and the like. In the present exemplary embodiment, silicon oxide is used as the formation material of the first interlayer insulating layer11a. A thickness of the first interlayer insulating layer11ais not particularly limited, but is approximately 200 nm, for example.

The second layer and the third layer on the first layer are provided with the TFT30. The TFT30includes the semiconductor layer30S provided in the second layer, and the gate electrode30G provided in the third layer. A Lightly Doped Drain (LDD) structure is formed in the semiconductor layer30S of the TFT30.

The semiconductor layer30S is provided in the non-opening area CL illustrated inFIG.4in plan view. Specifically, the semiconductor layer30S is bent in the ±Y direction from the ±X direction, corresponding to a site where the ±X direction and the ±Y direction intersect in the non-opening area CL. One source drain region s1, one LDD region s2, a channel region s3, another LDD region s4, and a part of another source drain region s5of the semiconductor layer30S are provided at a position overlapping with the scan line3in plan view, and extending along the ±X direction.

Of the semiconductor layer30S, the other source drain region s5is bent in the ±Y direction from the ±X direction in plan view, and extends along the ±Y direction. In the other source drain region s5, a part of a site extending in the ±Y direction is at a position overlapping with the data line6in plan view, and is also provided on the inside of the trench TR described later. A part of the other source drain region s5extending in the ±Y direction also functions as a lower capacitance electrode of the capacitance element16.

The semiconductor layer30S has the LDD regions s2and s4that have high electrical resistance with the channel region s3interposed therebetween. Thus, leakage current when turned off is suppressed. In terms of the leakage current suppression when turned off, it is sufficient to adopt a configuration in which the LDD region s4is included in a joint portion between the other source drain region s5to which the capacitance element16and the pixel electrode15are electrically coupled, and the channel region s3. The semiconductor layer30S is, for example, formed of a polysilicon film obtained by crystallization process is applied to an amorphous silicon film. A thickness of the semiconductor layer30S is not particularly limited, but is approximately 50 nm, for example.

The gate insulation layer11bis provided covering the semiconductor layer30S. The gate insulation layer11bis disposed between the semiconductor layer30S and the gate electrode30G along with the capacitance insulation layer16bdescribed below, and insulates the semiconductor layer30S and the gate electrode30G from each other. In other words, the gate insulation layer11band the capacitance insulation layer16bare examples of the gate insulation layer of the present disclosure. The gate insulation layer11bhas, for example, double structure formed of two types of silicon oxide. A thickness of the gate insulation layer11bis not particularly limited, but is approximately 75 nm, for example.

The capacitance insulation layer16bis provided covering a part of the gate insulation layer11b, and a part of the other source drain region s5. Of the capacitance insulation layer16b, a site overlapping with the channel region s3in plan view, insulates the semiconductor layer30S from the gate electrode30G along with the gate insulation layer11b. A site of the capacitance insulation layer16bthat overlaps with the other source drain region s5functions as a dielectric layer of the capacitance element16.

A dielectric material is used for the capacitance insulation layer16b. Examples of the dielectric material include, for example, hafnium oxide, aluminum oxide, silicon oxide, silicon nitride, tantalum oxide, and the like, and a single layer film of the material, or a combination of these films is used. In the present exemplary embodiment, silicon nitride is used as the dielectric material of the capacitance insulation layer16b. A thickness of the capacitance insulation layer16bmay be smaller than the thickness of the gate insulation layer11b, and is approximately 20 nm, for example.

The gate electrode30G is provided in the third layer so as to face the channel region s3of the semiconductor layer30S in the ±Z direction. The gate electrode30G includes a first gate electrode g1and a second gate electrode g2. The first gate electrode g1is disposed above the channel region s3via the gate insulation layer11band the capacitance insulation layer16b. The second gate electrode g2is disposed above the first gate electrode g1.

Conductive polysilicon that is a degenerate semiconductor, metal silicide, metal, a metal compound, or the like, is used as a formation material of the first gate electrode g1. In the present exemplary embodiment, the first gate electrode g1includes double structure of a conductive polysilicon film and a tungsten silicide film. A thickness of the first gate electrode g1is not particularly limited, but is approximately 150 nm, for example.

Here, in the present exemplary embodiment, hereinafter, the conductive polysilicon film refers to a polysilicon film that is injected with phosphorus atoms and imparted with electrical conductivity. Note that, atoms to be injected are not limited to the phosphorus atoms.

A metal compound having a light shielding property such as tungsten silicide is used as a formation material of the second gate electrode g2. A thickness of the second gate electrode g2is not particularly limited, but is approximately 60 nm, for example.

The second gate electrode g2is electrically coupled to the scan line3via a pair of second contact holes CNT1. The pair of second contact holes CNT1penetrate the first interlayer insulating layer11a, the gate insulation layer11b, the capacitance insulation layer16b, and the first gate electrode g1. The pair of second contact holes CNT1are disposed and facing each other in the ±Y direction with a part of the semiconductor layer30S interposed therebetween.

The trench TR is provided along a side of the +X direction of the pixel P in plan view, in the non-opening area CL described above. The trench TR is a substantially rectangular recessed portion in plan view. The trench TR includes a bottom surface along an XY plane and a side surface along the ±Z direction, and an upper side thereof is open.

On the inside of the trench TR, in addition to the first interlayer insulating layer11a, the other source drain region s5, and the capacitance insulation layer16bdescribed above, a first upper capacitance electrode16cis disposed. The capacitance element16is formed by each of these layers and a second upper capacitance electrode4above the trench TR. The capacitance element16has a function to increase the retention capacitor and improve potential retention characteristics in the pixel electrode15.

The first interlayer insulating layer11ais provided covering the side surface and the bottom surface of the trench TR. On the first interlayer insulating layer11a, the part of the other source drain region s5serving as the lower capacitance electrode of the capacitance element16is provided. The other source drain region s5extends along the side surface and the bottom surface of the trench TR.

The capacitance insulation layer16bserving as the dielectric layer of the capacitance element16is provided covering the other source drain region s5on the inside of the trench TR. In other words, the role of the dielectric layer of the capacitance element16is not played by the gate insulation layer11b, but is played by the capacitance insulation layer16b. As described above, the gate insulation layer of the TFT30includes the gate insulation layer11bof the silicon oxide film and the capacitance insulation layer16bof the silicon nitride film. Compared to this, the capacitance insulation layer16bof the capacitance element16only includes the silicon nitride film. In other words, two layers, that is, the gate insulation layer11band the capacitance insulation layer16interpose between the gate electrode30G and the semiconductor layer30S. Compared to this, only the capacitance insulation layer16bbeing unilamellar interposes between the other source drain region s5serving as the lower capacitance electrode and the first upper capacitance electrode16c. As described above, in the present exemplary embodiment, the thickness of the capacitance insulation layer16bis made smaller with respect to the thickness of the gate insulation layer11b.

The first upper capacitance electrode16cis provided covering the capacitance insulation layer16b, and fills the inside of the trench TR, and the second upper capacitance electrode4is further provided on the first upper capacitance electrode16c. The first upper capacitance electrode16cis provided by patterning from an identical layer to the first gate electrode g1. The second upper capacitance electrode4is provided by patterning from an identical layer to the second gate electrode g2. The first upper capacitance electrode16cand the second upper capacitance electrode4are examples of the capacitance electrode of the present disclosure. Note that, a part of the capacitance element16is provided on, in addition to the inside of the trench TR, an upper rim of the trench TR.

The second interlayer insulating layer11cis provided above the gate electrode30G, the second upper capacitance electrode4, and the like, so as to cover the gate electrode30G, the second upper capacitance electrode4, and the like. The second interlayer insulating layer11cis also provided at a position overlapping with the TFT30in a planar manner. The second interlayer insulating layer11cis provided by using one or more types of silicon-based oxide films such as a Tetraethyl Orthosilicate (TEOS) film, an NSG film, a Phosphosilicate Glass (PSG) film containing phosphorus (P), a Borosilicate Glass (BSG) film containing boron, and a Borophosphosilicate Glass (BPSG) film containing boron and phosphorus. In the present exemplary embodiment, silicon oxide is used as a formation material of the second interlayer insulating layer11c. A thickness of the second interlayer insulating layer11cis not particularly limited, but is approximately 400 nm, for example.

Contact holes CNT2and CNT3are provided in the second interlayer insulating layer11c. The contact holes CNT2and CNT3penetrate the second interlayer insulating layer11cand the gate insulation layer11bto reach the semiconductor layer30S. Specifically, the contact hole CNT2electrically couples the one source drain region s1of the semiconductor layer30S to the data line6in an upper layer. The contact hole CNT3electrically couples the other source drain region s5of the semiconductor layer30S to a second relay layer7described later.

The data line6and the second relay layer7are provided in the fourth layer on the third layer so as to cover the second interlayer insulating layer11cand the like. As described above, the data line6extends in the ±Y direction in the non-opening area CL of the pixel P. The data line6is electrically coupled to the one source drain region s1of the semiconductor layer30S via the contact hole CNT2.

The second relay layer7is provided in a state of an independent island in plan view. The second relay layer7is electrically coupled to the other source drain region s5of the semiconductor layer30S via the contact hole CNT3.

A formation material of the data line6and the second relay layer7is not particularly limited as long as the material is a low-resistance wiring line material having electrical conductivity, but examples include metal such as aluminum (Al) and titanium (Ti), and metal compounds thereof. In the present exemplary embodiment, the data line6and the second relay layer7each have four-layer structure of titanium (Ti) layer/titanium nitride (TiN) layer/aluminum (Al) layer/titanium nitride (TiN) layer. A thickness of each of the data line6and the second relay layer7is not particularly limited, but is approximately 350 nm, for example.

The third interlayer insulating layer12is provided covering the data line6, the second relay layer7, and the like. A formation material similar to that of the first interlayer insulating layer11a, for example, is adopted for the third interlayer insulating layer12. In the present exemplary embodiment, silicon oxide is used for the third interlayer insulating layer12. A thickness of the third interlayer insulating layer12is not particularly limited, but is approximately 400 nm, for example.

Contact holes CNT4and CNT5are provided in the third interlayer insulating layer12. The contact hole CNT4penetrates the second interlayer insulating layer11cand the third interlayer insulating layer12, and electrically couples the second upper capacitance electrode4of the capacitance element16to the capacitance line8above the third interlayer insulating layer12.

The contact hole CNT5penetrates the third interlayer insulating layer12, and electrically couples the second relay layer7to the first relay layer9that is an upper layer of the third interlayer insulating layer12.

The capacitance line8and the first relay layer9are provided in the fifth layer on the fourth layer. The capacitance line8overlaps with the data line6extending in the ±Y direction in plan view. Although not illustrated, the capacitance line8is electrically coupled to the vertical conducting portion106of the counter substrate20described above. Accordingly, the capacitance line8is electrically coupled to the counter electrode21, and is provided with a common potential. Accordingly, potential of the data line6and the scan line3is suppressed so as not to affect the pixel electrode15, by the capacitance line8. The capacitance line8is also electrically coupled to the first upper capacitance electrode16cof the capacitance element16and the second upper capacitance electrode4, via the contact hole CNT4.

The first relay layer9is provided in a state of an independent island in plan view. The first relay layer9is electrically coupled to the second relay layer7, via the contact hole CNT5.

A formation material of the capacitance line8and the first relay layer9is, similar to the data line6, not particularly limited as long as the material is a low-resistance wiring line material having electrical conductivity, but examples include metal such as aluminum (Al) and titanium (Ti), and metal compounds thereof. In the present exemplary embodiment, the capacitance line8and the first relay layer9each have four-layer structure of titanium (Ti) layer/titanium nitride (TiN) layer/aluminum (Al) layer/titanium nitride (TiN) layer. A thickness of each of the capacitance line8and the first relay layer9is not particularly limited, but is approximately 250 nm, for example.

The fourth interlayer insulating layer13is provided covering the capacitance line8and the first relay layer9. Examples of a formation material of the fourth interlayer insulating layer13include a silicon-based oxide film similar to that of the first interlayer insulating layer11a. In the present exemplary embodiment, silicon oxide is used for the fourth interlayer insulating layer13. A thickness of the fourth interlayer insulating layer13is not particularly limited, but is approximately 300 nm, for example.

A first contact hole CNT6is provided in the fourth interlayer insulating layer13. The first contact hole CNT6electrically couples the first relay layer9to the pixel electrode15that is an upper layer of the fourth interlayer insulating layer13. The first contact hole CNT6overlaps with one in the +Y direction of the pair of second contact holes CNT1in plan view.

The pixel electrode15is provided in the sixth layer on the fifth layer. The pixel electrode15is electrically coupled to the other source drain region s5also serving as the lower capacitance electrode of the capacitance element16, via the first contact hole CNT6, the first relay layer9, the contact hole CNT5, the second relay layer7, and the contact hole CNT3. The pixel electrode15is provided, for example, after forming a transparent conductive film of ITO, IZO, or the like, by performing patterning. In the present exemplary embodiment, ITO is used for the pixel electrode15. A thickness of the pixel electrode15is not particularly limited, but is approximately 145 nm, for example.

Although not illustrated, the alignment film18is provided covering the pixel electrode15. The alignment film18of the element substrate10, and the alignment film22of the counter substrate20described above are each formed of an aggregate of columns each grown to be columnar by vapor-depositing an inorganic material such as silicon oxide from a predetermined direction such as an oblique direction. In addition, liquid crystal molecules included in the liquid crystal layer50illustrated inFIG.2have negative dielectric anisotropy with respect to the alignment films18and22.

1.3. Method for Manufacturing Liquid Crystal Apparatus

A method for manufacturing the liquid crystal apparatus100according to the present exemplary embodiment will be described with reference toFIG.6toFIG.33.FIG.6is a process flow diagram illustrating a method for manufacturing an element substrate in the method for manufacturing the liquid crystal apparatus.FIG.7,FIG.9,FIG.11,FIG.13,FIG.15A,FIG.15B,FIG.17,FIG.19A,FIG.19B,FIG.21,FIG.23,FIG.25,FIG.27,FIG.29, andFIG.31are schematic cross-sectional views illustrating the method for manufacturing the element substrate.FIG.8,FIG.10,FIG.12,FIG.14,FIG.16,FIG.18,FIG.20,FIG.22,FIG.24,FIG.26,FIG.28,FIG.30,FIG.32, andFIG.33are schematic plan views illustrating the method for manufacturing the element substrate. In the following description,FIG.5will also be referred to.

Here, in the schematic cross-sectional view described above, as inFIG.5, respective three cross sections corresponding to the line segment A1-A2, the line segment Cl-C2, and the line segment B1-B2illustrated inFIG.4are illustrated side-by-side. Furthermore, in the schematic plan view described above, a periphery of one number of the opening area OP illustrated inFIG.4is enlarged and illustrated. Note that, hereinafter, unless otherwise noted, a state in plan view will be described in description of the schematic plan view.

The method for manufacturing the liquid crystal apparatus100of the present exemplary embodiment includes a method for manufacturing the element substrate10described below, and known techniques can be adopted except for steps included in the method for manufacturing the element substrate10. Thus, in the following description, only the method for manufacturing the element substrate10will be described. Additionally, in the method for manufacturing the element substrate10as well, known techniques can be adopted unless otherwise noted.

As illustrated inFIG.6, the method for manufacturing the element substrate10of the present exemplary embodiment includes steps S1to S12. Hereinafter, the steps from step S1to step S12will be described. Note that, the process flow illustrated inFIG.6is an example, and the present disclosure is not limited thereto.

In step S1, as illustrated inFIG.7, the scan line3and the trench TR are formed at the substrate10s. First, the scan line3is provided on the substrate10s. The scan line3has a site extending in the ±X direction, and a site protruding from the above site in the ±Y direction. The pair of second contact holes CNT1are provided in the site protruding in the ±Y direction. Patterning formation using, for example, a photolithography method is used for forming the scan line3.

Next, the trench TR is provided. Specifically, as illustrated inFIG.8, the trench TR is between pixels P adjacent to each other in the ±X direction, and is substantially rectangular that fits in the non-opening area CL. In the trench TR, although not particularly limited, for example, a depth in the ±Z direction is approximately 3 μm, and a width in the ±X direction is approximately 1 μm. Wet etching using, for example, a hard mask is used to form the trench TR. Then the processing proceeds to step S2.

In step S2, as illustrated inFIG.9andFIG.10, the first interlayer insulating layer11ais provided in a solid form, on the substrate10sincluding the scan line3and the inside of the trench TR. Examples of a method for forming the first interlayer insulating layer11ainclude an atmospheric pressure Chemical Vapor Deposition (CVD) method, a reduced pressure CVD method, or a plasma CVD method using a processing gas such as monosilane (SiH4), dichlorosilane (SiH2Cl2), orthosilicic acid tetraethyl (TEOS), and ammonia (NH3).

At this time, the inside of the trench TR is also covered by the first interlayer insulating layer11a, to adjust formation conditions so that a width in the ±X direction of the trench TR narrows. The width in the ±X direction of the trench TR covered with the first interlayer insulating layer11ais, for example, approximately 0.3 μm, compared to an initial width of approximately 1 μm. In this way, the trench TR is filled with the capacitance element16and the like provided on the inside of the trench TR. Thus, the data line6and the like provided on an upper layer do not fall into an indentation originating from the trench TR, and disconnection of the data line6and the like can be prevented. Then the processing proceeds to step S3.

In step S3, a polysilicon layer is provided on the first interlayer insulating layer11aincluding the inside of the trench TR. The polysilicon layer is an amorphous polysilicon film, and a reduced pressure CVD method or the like is used for formation. Next, as illustrated inFIG.11, the polysilicon layer is patterned to provide the semiconductor layer30S.

As illustrated inFIG.12, the semiconductor layer30S is provided by being bent in the ±Y direction from the ±X direction. Although not illustrated, the semiconductor layer30S is overlapped and disposed on the non-opening area CL. Then the processing proceeds to step S4.

In step S4, as illustrated inFIG.13andFIG.14, the gate insulation layer11bis provided in a solid form, on the semiconductor layer30S and the first interlayer insulating layer11a. When, for example, double structure including two types of silicon oxide is adopted for the gate insulation layer11b, a first silicon oxide film obtained by thermal oxidation of the polysilicon film is provided, and then a second silicon oxide film is provided under high temperature conditions at 700° C. to 900° C. using the reduced pressure CVD method. At this time, the inside of the trench TR is also covered with the gate insulation layer11b. Then the processing proceeds to step S5.

In step S5, the other source drain region s5that is the lower capacitance electrode of the capacitance element16is formed. First, as illustrated inFIG.16, a resist RE is formed in a region excluding the inside of the trench TR and the rim of the trench TR. The region in which the resist RE is not disposed corresponds to a site of the other source drain region s5of the semiconductor layer30S that functions as the lower capacitance electrode of the capacitance element16.

Next, ion implantation is performed for the semiconductor layer30S. First, electrical conductivity is imparted to the semiconductor layer30S on the inside of the trench TR and the rim of the trench TR, that is the region in which the resist RE is not disposed. At this time, ions are implanted into the semiconductor layer30S via the gate insulation layer11b. Accordingly, as illustrated inFIG.15A, the semiconductor layer30S on the inside of the trench TR and the rim of the trench TR turns to the other source drain region s5. The ions implanted are, for example, phosphorus (P).

Next, the gate insulation layer11bon the inside of the trench TR and the rim of the trench TR in which the resist RE is not disposed is removed by wet etching. This state is illustrated inFIG.15B. Thereafter, all of the resist RE is removed. Then the processing proceeds to step S6.

In step S6, an insulating layer16xis formed. The insulating layer16xis a layer turning to the capacitance insulation layer16bin a step that follows. As illustrated inFIG.17andFIG.18, the insulating layer16xis provided in a solid form, on the other source drain region s5on the inside of the trench TR and the rim of the trench TR, and on the gate insulation layer11b. Specifically, the insulating layer16xis provided by the reduced pressure CVD method, the plasma CVD method, or the like using silicon nitride. Then the processing proceeds to step S7.

In step S7, a second conductive layer16yand a third conductive layer4xare formed. The second conductive layer16yis a layer turning to the first gate electrode g1and the first upper capacitance electrode16cin a step that follows. The third conductive layer4xis a layer turning to the second gate electrode g2and the second upper capacitance electrode4in a step that follows.

First, the second conductive layer16yis provided in a solid form on the insulating layer16x. Specifically, after a polycrystalline silicon film is provided by the reduced pressure CVD method, phosphorus is implanted into the polycrystalline silicon film, and then diffused to form a conductive polysilicon film. Concentration of phosphorus atoms in the second conductive layer16yis to be 1×1019particles/cm3or larger. At this time, the inside of the trench TR is filled with the second conductive layer16y.

Next, as illustrated inFIG.19A, the pair of second contact holes CNT1facing each other in the ±Y direction with the semiconductor layer30S interposed therebetween are provided. The pair of second contact holes CNT1penetrate the second conductive layer16y, the insulating layer16x, the gate insulation layer11b, and the first interlayer insulating layer11ato reach as far as the scan line3. For example, dry etching is used to form the pair of second contact holes CNT1.

Next, as illustrated inFIG.19BandFIG.20, the third conductive layer4xis provided in a solid form on the second conductive layer16y. At this time, the third conductive layer4xis provided so as to fill the pair of second contact holes CNT1, to electrically couple the scan line3to the third conductive layer4x. Then the processing proceeds to step S8.

In step S8, as illustrated inFIG.21, the gate electrode30G, the capacitance element16, and the like are formed. Specifically, the insulating layer16x, the second conductive layer16y, and the third conductive layer4xare patterned using the dry etching.

Accordingly, the gate electrode30G constituted by the first gate electrode g1and the second gate electrode g2is provided on the gate insulation layer11bvia the capacitance insulation layer16b. At this time, in plan view, the insulating layer16xof silicon nitride is removed in a region other than the gate electrode30G and the second upper capacitance electrode4. This facilitates hydrogenation in the semiconductor layer30S. In other words, in a region on the semiconductor layer30S that does not overlap with the gate electrode30G of the semiconductor layer30S and the capacitance insulation layer16bbelow the gate electrode30G, silicon nitride is not provided.

By the patterning described above, the capacitance element16is also provided that is constituted by a part of the other source drain region s5, the capacitance insulation layer16b, the first upper capacitance electrode16c, and the second upper capacitance electrode4.

As illustrated inFIG.22, the gate electrode30G is disposed in a state of an island in plan view, and includes a site overlapping with the pair of second contact holes CNT1, and a site overlapping with the semiconductor layer30S (not illustrated).

The second upper capacitance electrode4is provided extending in the ±Y direction so as to overlap with the non-opening area CL extending in the ±Y direction. The second upper capacitance electrode4includes a main body portion4aoverlapping with the data line6provided above, and extending in the ±Y direction, and a protruding portion4bprotruding in the −X direction from the main body portion4a. The protruding portion4boverlaps with a site of the semiconductor layer30S that extends in the ±X direction. The capacitance insulation layer16band the first upper capacitance electrode16care disposed so as to overlap with the second upper capacitance electrode4. Then the processing proceeds to step S9.

In step S9, as illustrated inFIG.23, the one source drain region s1, the LDD regions s2and s4, the channel region s3, and a part of the other source drain region s5are formed in the semiconductor layer30S by the ion implantation. Specifically, implantation of medium concentration ion and subsequent implantation of high concentration ion are performed for the semiconductor layer30S.

First, the LDD regions s2and s4sandwiching the channel region s3in the ±X direction is provided by the implantation of medium concentration ion. Next, by patterning the resist RE illustrated inFIG.24, the LDD regions s2, s4of the semiconductor layer30S, and the channel region s3are masked, and the implantation of high concentration ion is performed for the rest of the semiconductor layer30S. This provides the source drain regions s1and s5. Then the processing proceeds to step S10.

In step S10, the second interlayer insulating layer11cand the like are formed. First, the second interlayer insulating layer11cis provided on the second gate electrode g2, the second upper capacitance electrode4, and the gate insulation layer11bexposed upward. Examples of a method for forming silicon oxide being the second interlayer insulating layer11cinclude, for example, an atmospheric pressure CVD method, the reduced pressure CVD, the plasma CVD method, or the like using, monosilane, dichlorosilane, TEOS, Triethyl Borate (TEB), and the like.

Next, impurity activation annealing is performed by heating at about 1000° C. Subsequently, hydrogen plasma processing is performed. Accordingly, defects in the semiconductor layer30S are terminated with hydrogen, and characteristics of the switching element are improved.

Next, as illustrated inFIG.25andFIG.26, the contact holes CNT2and CNT3are formed by the dry etching. The contact holes CNT2and CNT3penetrate the gate insulation layer11band the second interlayer insulating layer11cto reach as far as the semiconductor layer30S. In plan view, the contact hole CNT2overlaps with the one source drain regions s1, and the contact hole CNT3overlaps with a site of the other source drain region s5that is adjacent to the LDD region s4. Then the processing proceeds to step S11.

In step S11, the data line6and the second relay layer7are formed. At this time, as illustrated inFIG.27, the data line6and the second relay layer7are provided so as to fill the contact holes CNT2and CNT3.

As illustrated inFIG.28, the data line6is provided extending in the ±Y direction, and overlaps with a site of the other source drain region s5that extends in the ±Y direction (not illustrated). In other words, the data line6is provided extending in the ±Y direction, and overlaps with the trench TR and the capacitance element16in plan view. The data line6has a site protruding in the +X direction that overlaps with the non-opening area CL extending in the ±X direction. The contact hole CNT2is provided in the site.

The second relay layer7is provided in a state of an island independent of the data line6. The second relay layer7includes a main body portion7aextending in the ±X direction and overlapping with a part of the semiconductor layer30S below, and a protruding portion7bprotruding in the ±Y direction from the main body portion7a.

The data line6is electrically coupled to the one source drain region s1of the semiconductor layer30S via the contact hole CNT2. The second relay layer7is electrically coupled to the other source drain region s5of the semiconductor layer30S via the contact hole CNT3. Then the processing proceeds to step S12.

In step S12, an upper layer of the data lines6is formed. First, the third interlayer insulating layer12is provided in a solid form, on the data line6, the second relay layer7, and the second interlayer insulating layer11cexposed upward. The third interlayer insulating layer12is provided by the plasma CVD method using, for example, a silicon oxide film.

Next, as illustrated inFIG.29andFIG.30, the contact holes CNT4and CNT5are provided by the dry etching. The contact hole CNT4penetrates the third interlayer insulating layer12and the second interlayer insulating layer11c, and reaches as far as the second upper capacitance electrode4of the capacitance element16. The contact hole CNT5penetrates the third interlayer insulating layer12and reaches as far as the second relay layer7.

Next, the capacitance line8and the first relay layer9are formed. At this time, as illustrated inFIG.31, the capacitance line8and the first relay layer9are provided so as to fill the contact holes CNT4and CNT5.

The capacitance line8is electrically coupled to the second upper capacitance electrode4via the contact hole CNT4. The first relay layer9is electrically coupled to the other source drain region s5of the semiconductor layer30S, via the contact hole CNT5, the second relay layer7, and the contact hole CNT3.

As illustrated inFIG.32, the capacitance line8is provided to extend in the ±Y direction, so as to overlap with the non-opening area CL extending in the ±Y direction. The capacitance line8includes a main body8aoverlapping with the data line6provided below and extending in the ±Y direction, a protruding portion8bprotruding in the −X direction from the main body portion8a, and another protruding portion8cprotruding from the body8ain the +X direction opposed to the protruding portion8b. The protruding portion8boverlaps with a site of the semiconductor layer30S that extends in the ±X direction. The contact hole CNT4is provided in the protruding portion8b. The other protruding portion8coverlaps with another semiconductor layer30S (not illustrated) adjacent to the semiconductor layer30S in the +X direction.

The first relay layer9is provided in a state of an island independent of the capacitance line8, and overlaps with the contact hole CNT5. The first relay layer9includes a main body portion9aextending in the ±X direction and overlapping with a part of the semiconductor layer30S below, and a protruding portion9bprotruding in the ±Y direction from the main body portion9a.

Next, the fourth interlayer insulating layer13is provided in a solid form, on the capacitance line8, the first relay layer9, and the third interlayer insulating layer12exposed upward. The fourth interlayer insulating layer13is provided by the plasma CVD method using, for example, a silicon oxide film. After the third interlayer insulating layer12is provided, a planarization process such as a Chemical & Mechanical Polishing (CMP) process is performed to flatten unevenness caused by the structure of the lower layer.

Next, the first contact hole CNT6penetrating the fourth interlayer insulating layer13to expose the first relay layer9is provided by the dry etching. Thereafter, as illustrated inFIG.33, the pixel electrode15corresponding to the opening area OP is provided on the fourth interlayer insulating layer13. At this time, the pixel electrode15is provided to fill the first contact hole CNT6. Accordingly, the pixel electrode15is electrically coupled to the other source drain region s5of the semiconductor layer30S, via the first contact hole CNT6, the first relay layer9, the contact hole CNT5, the second relay layer7, and the contact hole CNT3.

Of the method for manufacturing the element substrate10, known techniques can be used for subsequent steps, and descriptions thereof will be omitted. According to the method for manufacturing described above, the element substrate10and the liquid crystal apparatus100are manufactured.

According to the present exemplary embodiment, the following advantages can be obtained.

The retention capacitor can be increased, and manufacturing costs can be reduced. Specifically, the one source drain regions s1and the channel region s3of the semiconductor layer30S are overlapped and disposed on the scan line3, and the other source drain region s5and the capacitance element16are overlapped and disposed on the data line6. Accordingly, an area of the capacitance element16is easily ensured, and a retention capacitor of the capacitance element16can be increased.

In addition, in the capacitance element16, the other source drain region s5that extends of the semiconductor layer30S, is the lower capacitance electrode, and the first upper capacitance electrode16cand the second upper capacitance electrode4that are the capacitance electrodes, are overlapped and disposed on the lower capacitance electrodes. In other words, since the part of the semiconductor layer30S is used as the lower capacitance electrode, the manufacturing process can be simplified. As described above, the liquid crystal apparatus100that increases the retention capacitor, and reduces the manufacturing costs can be provided.

The capacitance element16is disposed on the inside of the trench TR, that is the side surface and the bottom surface of the trench TR, and the area of the capacitance element16is enlarged. Accordingly, the retention capacitor of the capacitance element16can be further increased.

Since the first interlayer insulating layer11ais disposed in the trench TR, the trench TR is not made too wide, compared to a case where the first interlayer insulating layer11ais not present. Thus, the data line6and the like disposed on the trench TR are made less likely to fall into the trench TR, and it is possible to suppress occurrence of disconnection or the like in the data line6.

Since the first relay layer9overlaps with one of the pair of second contact holes CNT1, an opening ratio in the liquid crystal apparatus100can be improved, compared to a case where the first relay layer9do not overlap with the second contact hole CNT1.

The gate insulation layer11band the capacitance insulation layer16bare disposed between the gate electrode30G and the channel region s3of the semiconductor layer30S, and only the capacitance insulation layer16bis disposed as the dielectric layer of the capacitance element16. Accordingly, insulating properties between the gate electrode30G and the semiconductor layer30S can be ensured, and the dielectric layer of the capacitance element16can be thinned. In other words, the retention capacitor of the capacitance element16can be further increased.

The capacitance insulation layer16bformed of the silicon nitride film is not provided, in plan view, on the semiconductor layer30S in a region not overlapping with the gate electrode30G, the first upper capacitance electrode16c, and the second upper capacitance electrode4, thus the defects in the semiconductor layer30S are terminated with hydrogen in the hydrogen plasma processing step, and the characteristics of the switching element are improved.

Since the main body portion9aof the first relay layer9and the main body portion7aof the second relay layer7overlap with the semiconductor layer30S, light shielding properties are improved, and occurrence of optical leakage current in the TFT30can be suppressed. In addition, the first contact hole CNT6can be provided in the protruding portion9bof the first relay layer9to ensure electrical coupling to the pixel electrode15.

The protruding portions4b,8b, and8cthat overlap in plan view with the semiconductor layer30S can reduce light incident on the TFT30, and enhance the light shielding properties for the TFT30. Additionally, the capacitance line8, that is a constant potential line, makes it possible to shield effects of potential fluctuations of the data line6and the scan line3, and it is possible to suppress deterioration in display quality of the liquid crystal apparatus100.

Since the capacitance element16is provided in a region overlapping with the non-opening area CL in plan view, the opening ratio in the liquid crystal apparatus100can be improved.

2. Second Exemplary Embodiment

In the present exemplary embodiment, as in the first exemplary embodiment, an active drive type liquid crystal apparatus including a TFT as a transistor for each pixel will be exemplified as an electro-optical device. The liquid crystal apparatus according to the present exemplary embodiment differs from the liquid crystal apparatus100of the first exemplary embodiment in a configuration of an element substrate. Thus, the same components as in the first exemplary embodiment are given the same reference signs, and redundant descriptions of these components will be omitted.

2.1. Configuration of Element Substrate

Structure of an element substrate210included in the liquid crystal apparatus of the present exemplary embodiment will be described with reference toFIG.34.FIG.34is a schematic cross-sectional view illustrating the structure of the element substrate in the liquid crystal apparatus according to the second exemplary embodiment. Note that, the liquid crystal apparatus according to the second exemplary embodiment has similar arrangement of pixels to that of the liquid crystal apparatus100in the first exemplary embodiment. Thus, inFIG.34, three cross sections corresponding toFIG.5in the element substrate10of the liquid crystal apparatus100are illustrated.

As illustrated inFIG.34, the element substrate210in the liquid crystal apparatus of the present exemplary embodiment includes a pair of light shielding walls77facing each other in the ±Y direction with the semiconductor layer30S interposed therebetween. The light shielding wall77is provided in a contact hole CNT7. The element substrate210of the present exemplary embodiment differs from the element substrate10of the first exemplary embodiment in this regard.

The light shielding wall77provided in the contact hole CNT7penetrates the first interlayer insulating layer11a, the gate insulation layer11b, and the second interlayer insulating layer11c, and is electrically coupled to the scan line3. A relay layer207in the fourth layer penetrates the second interlayer insulating layer11c, and is electrically coupled to the second gate electrode g2, via the contact hole CNT7. The Relay layer207includes an identical material to that of the data line6. In other words, the metal or metal compound thereof described above is used for the relay layer207, similar to the data line6.

Accordingly, the second gate electrode g2is electrically coupled to the scan line3via the contact hole CNT7. In other words, the gate electrode30G of the TFT30is electrically coupled to the scan line3via the contact hole CNT7.

The other source drain region s5of the semiconductor layer30S is electrically coupled to a second relay layer217via the contact hole CNT3. A formation material similar to that of the data line6and the relay layer207is used for the second relay layer217. The second relay layer217is electrically coupled to a first relay layer209via a contact hole CNT9penetrating the third interlayer insulating layer12.

A similar formation material to that of the capacitance line8of the fifth layer is also used for the first relay layer209. The first relay layer209is electrically coupled to the pixel electrode15via the first contact hole CNT6penetrating the fourth interlayer insulating layer13above.

The configuration of the element substrate210other than the above-described configuration is similar to the configuration of the element substrate10of the first exemplary embodiment.

2.2. Method for Manufacturing Liquid Crystal Apparatus

A method for manufacturing the liquid crystal apparatus in the present exemplary embodiment will now be described. The method for manufacturing the liquid crystal apparatus of the present exemplary embodiment includes a method for manufacturing the element substrate210, and known techniques can be adopted except for steps included in the method for manufacturing the element substrate210. Additionally, the method for manufacturing the element substrate210includes the method of manufacturing the element substrate10of the first exemplary embodiment. Thus, in the following description, only steps specific in the method for manufacturing the element substrate210will be described. Note that, in the following method for manufacturing, known techniques can be adopted unless otherwise noted.

The method for manufacturing the element substrate210of the present exemplary embodiment will be described, with reference toFIG.35AtoFIG.47.FIG.35A,FIG.35B,FIG.36,FIG.38,FIG.39,FIG.41,FIG.43, andFIG.45are schematic cross-sectional views illustrating the method for manufacturing the element substrate.FIG.37,FIG.40,FIG.42,FIG.44,FIG.46, andFIG.47are schematic plan views illustrating the method for manufacturing the element substrate. Note that, the method for manufacturing the element substrate210has similar steps to those of the element substrate10of the first exemplary embodiment, and thusFIG.6will also be referred to in the following description.

First, of the process flow of the first exemplary embodiment illustrated inFIG.6, step S1to step S6are performed similarly to the first exemplary embodiment. Then, as illustrated inFIG.35A, the second conductive layer16yis provided in a solid form on the insulating layer16x.

Next, as illustrated inFIG.35B, the third conductive layer4xis provided in a solid form on the second conductive layer16y. In the element substrate210, the third conductive layer4xturning to the second gate electrode g2is not electrically coupled to the scan line3via a contact hole.

Next, as illustrated inFIG.36, the gate electrode30G, the capacitance element16, and the like, are provided. This step corresponds to step S8of the first exemplary embodiment. Specifically, the insulating layer16x, the second conductive layer16y, and the third conductive layer4xare patterned using the dry etching.

As illustrated inFIG.37, the gate electrode30G is provided in a state of an island independently of the second upper capacitance electrode4and the like. The second upper capacitance electrode4is provided extending in the ±Y direction. Note that, although not illustrated, the first gate electrode g1and the capacitance insulation layer16b, below the second gate electrode g2are overlapped and disposed on the gate electrode30G. Further, the first upper capacitance electrode16cis overlapped and disposed on the second upper capacitance electrode4.

At this time, as in the first exemplary embodiment, the insulating layer16xof silicon nitride is removed in a region other than the gate electrode30G and the second upper capacitance electrode4. In other words, in a region on the semiconductor layer30S that does not overlap with the gate electrode30G of the semiconductor layer30S and the capacitance insulation layer16bbelow the gate electrode30G, silicon nitride is not provided.

Next, as illustrated inFIG.38, as in the first exemplary embodiment, the one source drain region s1, the LDD regions s2, s4, the channel region s3, and a part of the other source drain region s5are provided on the semiconductor layer30S. This step corresponds to step S9of the first exemplary embodiment.

Next, the second interlayer insulating layer11cis provided on the second gate electrode g2, the second upper capacitance electrode4, and the gate insulation layer11bexposed upward. Next, the impurity activation annealing at about 1000° C. is performed, and followed by the hydrogen plasma processing. This step corresponds to step S10of the first exemplary embodiment.

Next, as illustrated inFIG.39, the contact hole CNT7including a pair of contact holes CNT70is provided by the dry etching. The pair of contact holes CNT70are through holes for providing the light shielding wall77. The pair of contact holes CNT70penetrate the first interlayer insulating layer11a, the gate insulation layer11b, and the second interlayer insulating layer11cto reach as far as the scan line3. The pair of contact holes CNT70are disposed facing each other in the ±Y direction with a part of the semiconductor layer30S interposed therebetween. A site of the contact hole CNT7other than the pair of contact holes CNT70penetrates the second interlayer insulating layer11cand reaches as far as the second gate electrode g2.

As illustrated inFIG.40, the contact hole CNT7includes the pair of contact holes CNT70facing each other in the ±Y direction with the semiconductor layer30S interposed therebetween. The site of the contact hole CNT7other than the pair of contact holes CNT70is disposed along the ±Y direction intersecting with the semiconductor layer30S.

Next, the data line6, the relay layer207, and the second relay layer217are provided. This step corresponds to step S11of the first exemplary embodiment. Specifically, as illustrated inFIG.41, when the data line6, the relay layer207, and the second relay layer217are provided, the contact holes CNT2, CNT3, and the contact hole CNT7including the pair of contact holes CNT70are filled. The light shielding wall77is provided in the contact hole CNT70of the contact hole CNT7.

As illustrated inFIG.42, the data line6is provided extending in the ±Y direction, and overlaps with a site of the other source drain region s5(not illustrated) that extends in the ±Y direction. In other words, the data line6is provided extending in the ±Y direction, and overlaps with the trench TR and the capacitance element16. The data line6has a site protruding in the +X direction that overlaps with the non-opening area CL extending in the ±X direction. The contact hole CNT2is provided in the site.

The relay layer207is provided in a state of an island independent of the data line6, and is electrically coupled to the scan line3and the second gate electrode g2via the contact hole CNT7. The relay layer207includes a main body portion extending in the ±X direction and overlapping with a part of the semiconductor layer30S below (not illustrated), and a protruding portion protruding in the ±Y direction from the main body portion.

The second relay layer217is provided in a state of an island independent of the data line6and the relay layer207. The second relay layer217is electrically coupled to the other source drain region s5of the semiconductor layer30S, via the contact hole CNT3.

Next, an upper layer of the data line6as in the first exemplary embodiment is formed. This step corresponds to step S12of the first exemplary embodiment. First, the third interlayer insulating layer12is provided in a solid form, on the data line6, the second relay layer217, the relay layer207, and the second interlayer insulating layer11cexposed upward.

Next, as illustrated inFIG.43andFIG.44, the contact holes CNT4and CNT9are provided by the dry etching. The contact hole CNT4penetrates the third interlayer insulating layer12and the second interlayer insulating layer11c, and reaches as far as the second upper capacitance electrode4of the capacitance element16. The contact hole CNT9penetrates the third interlayer insulating layer12and reaches as far as the second relay layer217.

Next, the capacitance line8and the first relay layer209are provided. Specifically, as illustrated inFIG.45andFIG.46, when the capacitance line8and the first relay layer209are provided, the contact holes CNT4and CNT9are filled.

The first relay layer209is provided in a state of an island independent of the capacitance line8, and is electrically coupled to the second relay layer217via contact holes CNT9. The first relay layer209includes a main body portion209aextending in the ±X direction and overlapping with a part of the semiconductor layer30S below, and a protruding portion209bprotruding in the ±Y direction from the main body portion9a.

The first relay layer209is electrically coupled to the other source drain region s5of the semiconductor layer30S, via the contact hole CNT9, the second relay layer217, and the contact hole CNT3.

Next, the fourth interlayer insulating layer13is provided in a solid form, on the capacitance line8, the first relay layer209, and the third interlayer insulating layer12exposed upward. Thereafter, the fourth interlayer insulating layer13is subjected to the planarization process such as the CMP process.

Next, a through hole penetrating the fourth interlayer insulating layer13to expose the first relay layer209is provided by the dry etching. Thereafter, as illustrated inFIG.47, the pixel electrode15corresponding to the opening area OP is provided on the fourth interlayer insulating layer13. At this time, the first contact hole CNT6is also provided so as to fill the above through hole. The pixel electrode15is electrically coupled to the other source drain region s5of the semiconductor layer30S, via the first contact hole CNT6, the first relay layer209, the contact hole CNT9, the second relay layer217, and the contact hole CNT3.

Of the method for manufacturing the element substrate210, known techniques can be used for subsequent steps, and descriptions thereof will be omitted. According to the method for manufacturing described above, the element substrate210and the liquid crystal apparatus including the element substrate210are manufactured.

According to the present exemplary embodiments, the following advantages can be obtained, in addition to the effects of the first exemplary embodiment.

The light shielding wall77can reduce light incident on the TFT30, and further enhance light shielding properties for the TFT30. In addition, common potential identical to that of the scan line3can be applied to the gate electrode30G via the light shielding wall77.

In the element substrate10of the first exemplary embodiment, the pair of contact holes CNT1, the contact holes CNT2, and CNT3are provided in the separate steps, but the pair of contact holes CNT70corresponding to the pair of contact holes CNT1, contact holes CNT2, CNT3, and the like, are provided in one step. Thus, it is possible to reduce the etching process for providing the through hole, and the manufacturing process can be further simplified.

3. Third Exemplary Embodiment

3.1. Electronic Apparatus

With reference toFIG.48, an electronic apparatus of the present exemplary embodiment will be described by using a projection-type display apparatus as an example.FIG.48is a schematic view illustrating a configuration of the projection-type display apparatus as the electronic apparatus according to a third exemplary embodiment.

As illustrated inFIG.48, a projection-type display apparatus1000as the electronic apparatus according to the present exemplary embodiment includes a lamp unit1001as a light source, dichroic mirrors1011,1012as a color separation optical system, and three liquid crystal apparatuses1B,1G,1R that are electro-optical panels, three reflection mirrors1111,1112,1113, three relay lenses1121,1122,1123, a dichroic prism1130as a color synthesis optical system, and a projection lens1140as a projection optical system.

In the lamp unit1001, for example, a discharge type light source is adopted. The method of the light source is not limited thereto, and a solid light source such as a light emitting diode, laser, or the like may be adopted.

Light exited from the lamp unit1001is separated by the two dichroic mirrors1011and1012into color light of three colors having different wavelength ranges from each other. The color light of three colors includes substantially red light, substantially green light, and substantially blue light. In the following description, the substantially red light is also referred to as red light R, the substantially green light is also referred to as green light G, and the substantially blue light is also referred to as blue light B.

The dichroic mirror1011transmits red light R and reflects green light G and blue light B each having a wavelength shorter than that of the red light R. The red light R transmitted through the dichroic mirror1011is reflected by the reflection mirror1111and is incident on the liquid crystal apparatus1R. The green light G reflected by the dichroic mirror1011is reflected by the dichroic mirror1012, and is then incident on the liquid crystal apparatus1G. The blue light B reflected by the dichroic mirror1011transmits the dichroic mirror1012and is exited toward a relay lens system1120.

The relay lens system1120includes the relay lenses1121,1122,1123and the reflection mirrors1112, and1113. Since a light path of the blue light B is longer compared to the green light G and the red light R, luminous flux tends to be larger. Thus, expansion of the luminous flux is suppressed using the relay lens1122. The blue light B incident on the relay lens system1120is reflected by the reflection mirror1112and is converged in a vicinity of the relay lens1122by the relay lens1121. Then, the blue light B is incident on the liquid crystal apparatus1B via the reflection mirror1113and the relay lens1123.

The liquid crystal apparatus100as the electro-optical device of the first exemplary embodiment is applied to the liquid crystal apparatuses1R,1G, and1B that are light modulating devices, in the projection-type display apparatus1000. Additionally, a liquid crystal apparatus other than the first exemplary embodiment may be applied as the liquid crystal apparatuses1R,1G, and1B.

Each of the liquid crystal apparatuses1R,1G, and1B is electrically coupled to an upper circuit of the projection-type display apparatus1000. Accordingly, image signals specifying gray scale levels of the red light R, the green light G, and the blue light B are supplied from external circuits respectively, and processed by the upper circuit. Thus, the liquid crystal apparatuses1R,1G, and1B are driven and the color light of each the apparatus is modulated.

The red light R, the green light G, and the blue light B modulated by the liquid crystal apparatuses1R,1G, and1B, respectively are incident on the dichroic prism1130from three directions. The dichroic prism1130synthesizes the red light R, the green light G, and the blue light B entered. In the dichroic prism1130, red light R and the blue light B are reflected by 90 degrees, and the green light G transmits. Thus, the red light R, the green light G, and the blue light B are synthesized as display light for displaying a color image and exited toward the projection lens1140.

The projection lens1140is disposed so as to face outside the projection-type display apparatus1000. The display light is expanded via the projection lens1140and exited, and projected onto a screen1200that is a target of projection.

In the present exemplary embodiment, the projection-type display apparatus1000is illustrated as the electronic apparatus, but electronic apparatuses to which the electro-optical device according to the present disclosure is applied is not limited thereto. For example, the electro-optical device according to the present disclosure may be applied to an electronic apparatus such as a projection type Head-Up Display (HUD), a direct view type Head Mounted Display (HMD), a personal computer, a digital camera, a liquid crystal television, or the like.

As described above, according to the projection-type display apparatus1000according to the present exemplary embodiment, the following advantages can be achieved.

In the liquid crystal apparatuses1R,1G, and1B, potential retention capability of the pixel P is improved, occurrence of optical leakage current is suppressed, and display quality is improved. In addition, the projection-type display apparatus1000with reduced manufacturing costs can be provided.

Contents derived from the exemplary embodiments will be described below.

An electro-optical device includes a scan line extending in a first direction, a data line extending in a second direction that intersects with the first direction, a transistor having a semiconductor layer in which, at a position overlapping with the scan line, one source drain region and a channel region extend along the first direction, and at a position overlapping with the data line, another source drain region extends along the second direction, and a capacitance element having a capacitance electrode provided, at a position overlapping with the data line, so as to overlap with the other source drain region.

According to this configuration, a high opening ratio of a pixel can be achieved. Specifically, the one source drain region and the channel region of the semiconductor layer are overlapped and disposed on the scan line, and the other source drain region and the capacitance element are overlapped and disposed on the data line. Thus, by thinning the scan line and the data line, the opening ratio can be easily ensured, and light utilization efficiency can be increased. Further, a retention capacitor can be increased and manufacturing costs can be reduced.

Further, in the capacitance element, the other source drain region that extends of the semiconductor layer is a lower capacitance electrode, and an upper capacitance electrode that is, for example, the capacitance electrode is disposed in the same layer as a gate electrode of the transistor, so as to overlap with the lower capacitance electrode. In other words, since a part of the layer constituting the transistor is used as the lower capacitance electrode or the upper capacitance electrode, a manufacturing process can be simplified. As described above, it is possible to provide the electro-optical device that can increase the light utilization efficiency while suppressing deterioration in display quality and reduce the manufacturing costs.

The above electro-optical device may include a substrate, the substrate may include a recessed portion at a position overlapping with the data line, and the other source drain region may extend along a side surface and a bottom surface of the recessed portion.

According to this configuration, the capacitance element is disposed on an inside of the recessed portion that is the side surface and the bottom surface of the recessed portion, and an area of the capacitance element is enlarged. Further, by deepening the recessed portion of the capacitance element, it is possible to increase the retention capacitor. Accordingly, the retention capacitor of the capacitance element can be further increased.

The above electro-optical device may include an insulating layer in the recessed portion, and the other source drain region may extend on the insulating layer.

According to this configuration, since the insulating layer is disposed in the recessed portion, the recessed portion is not made too wide, compared to a case where there is no insulating layer. Thus, the data line and the like disposed on the recessed portion are made less likely to fall in the recessed portion, and it is possible to suppress occurrence of disconnection or the like in the data line.

The above electro-optical device may include a pixel electrode provided corresponding to the transistor, and a first relay layer electrically connected to the pixel electrode via a first contact hole, and the first contact hole may overlap with a second contact hole for electrically coupling a gate electrode of the transistor to the scan line.

According to this configuration, since the first relay layer overlaps with the second contact hole, the opening ratio in the electro-optical device can be improved, compared to a case where the first relay layer does not overlap with the second contact hole.

In the above electro-optical device, a gate insulation layer of the transistor includes a silicon oxide film and a silicon nitride film, and a capacitance insulation layer of the capacitance element may be constituted only by a silicon nitride film.

According to this configuration, insulating properties of the gate insulation layer can be ensured, and the capacitance insulation layer can be made thinner than the gate insulation layer. In other words, the retention capacitor of the capacitance element can be further increased.

In the above electro-optical device, a silicon nitride film may not be provided in a region of the semiconductor layer that does not overlap with the gate electrode and the capacitance electrode.

According to this configuration, in a hydrogen plasma processing step, defects in the semiconductor layer are terminated with hydrogen, and characteristics of a switching element are improved.

The above electro-optical device may include the pixel electrode provided corresponding to the transistor, the first relay layer electrically connected to the pixel electrode, and a second relay layer electrically connected to the first relay layer, the first relay layer and the second relay layer may each include a main body portion extending in the first direction, and overlapping with the semiconductor layer, and a protruding portion protruding in the second direction from the main body portion.

According to this configuration, since the respective main body portions of the first relay layer and the second relay layer overlap with the semiconductor layer, a light shielding property is improved, and occurrence of light leakage current in the transistor can be suppressed. In addition, the respective protruding portions of the first relay layer and the second relay layer can improve the light shielding property, and by providing contact holes, electrical coupling to an upper layer or a lower layer can be ensured.

The above electro-optical device may include a capacitance wiring line electrically connected to the capacitance electrode, and the capacitance wiring line and the capacitance electrode may each include a main body portion extending in the second direction, and overlapping with the data line, and a protruding portion protruding in the first direction from the main body portion, and overlapping with the semiconductor layer extending in the first direction.

According to this configuration, light incident on the transistor is reduced by the protruding portion overlapping with the semiconductor layer, and the light shielding property for the transistor can be improved.

In the above electro-optical device, the capacitance wiring line may include another protruding portion protruding toward an opposite side to the protruding portion, and overlapping with another semiconductor layer adjacent to the semiconductor layer.

According to this configuration, light incident on the transistor of the other semiconductor layer is reduced by the other protruding portion, and the light shielding property for the transistor can be further improved. Additionally, effects of potential fluctuations of the data line and the scan line can be electrically shielded by the capacitance wiring line to which constant potential is applied and a protruding portion of the capacitance wiring line, and deterioration in display quality can be prevented.

The above electro-optical device may include a light shielding wall provided along a part of the semiconductor layer, and the light shielding wall may include an identical material to that of the data line.

According to this configuration, light incident on the transistor is reduced by the light shielding wall, and the light shielding property for the transistor can be further improved.

In the above electro-optical device, the gate electrode of the transistor may be electrically connected to the scan line via the light shielding wall.

According to this configuration, the gate electrode can be provided with identical potential to potential applied to the scan line.

An electronic apparatus includes the above electro-optical device.

According to this configuration, the electronic apparatus can be provided, in which display quality of the mounted electro-optical device is improved, with manufacturing costs reduced.