Systems and methods for mitigating data interference in a contact signal

The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for determining contact between a head assembly and a storage medium.

FIELD OF THE INVENTION

The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for determining contact between a head assembly and a storage medium.

BACKGROUND

Typical implementations of hard disk based storage devices utilize a thermal element to control the fly height of the read/write head. Heating the thermal element causes a distance between the read/write head and a storage medium to decrease. Where the heat generated by the thermal element is sufficient, the read/write head may be brought into contact with the storage medium. In some cases, this contact can damage one or more components of the storage device.

Hence, for at least the aforementioned reason, there exists a need in the art for advanced systems and methods for determining contact between the read/write head and the storage medium.

BRIEF SUMMARY

The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for determining contact between a head assembly and a storage medium.

Various embodiments of the present invention provide storage devices that include: a read/write head assembly and an interference mitigated touch down circuit. The read/write head assembly is disposed in relation to a storage medium, and includes a sensor operable to provide a sensor output indicating contact between the read/write head assembly and the storage medium and a write head. The interference mitigated touch down circuit is operable to: estimate an interference in the sensor output from the write head; and remove the interference from the sensor output to yield a filtered output.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for performing determining contact between a head assembly and a storage medium.

A hard disk interface (“HDI”) sensor is included in the read/write head assembly near a write data signal generator. As the read/write head assembly flies close to the storage medium occasional contact between the read/write head assembly and the storage medium may occur. The occurrence of such contact is indicated by an output from the HDI sensor. As an example, the HDI sensor may be a thermally sensitive sensor that provides a current indicative of a contact or non-contact condition. In particular, where contact occurs, the temperature of the HDI sensor increases causing a change in the current. The current is processed to determine the occurrence of contact, but at times is inaccurate. As contact can lead to damage to one of both of the read/write head assembly, inaccuracy in the HDI sensor is undesirable.

Various embodiments of the present invention provide storage devices that include: a read/write head assembly and an interference mitigated touch down circuit. The read/write head assembly is disposed in relation to a storage medium, and includes a sensor operable to provide a sensor output indicating contact between the read/write head assembly and the storage medium and a write head. The interference mitigated touch down circuit is operable to: estimate an interference in the sensor output from the write head; and remove the interference from the sensor output to yield a filtered output. In some instances of the aforementioned embodiments, the storage device further includes the storage medium. In various instances of the aforementioned embodiments, the interference mitigated touch down circuit is implemented as part of a semiconductor device, and/or the storage device is a hard disk drive.

In one or more instances of the aforementioned embodiments, the interference mitigated touch down circuit is further operable to determine a contact between the storage medium and the read/write head assembly based on the filtered output, and to provide a contact output. In particular embodiments of the present invention, estimating the interference in the sensor output includes calculating a coherent output based upon two or more instance of the sensor output, and calculating a least mean squared value based at least in part on the coherent output. In some such instances, the coherent output is a running average of the two or more instances of the sensor output. In various such instances, estimating the interference in the sensor output further includes transforming the dimension of the coherent output from a first space to a second space. Calculating a least mean squared value is based at least in part on the coherent output transformed to the second space. In some cases, the first dimension is a power of P, and in one particular case, the value of P is nine. In one or more instances of the aforementioned embodiments, removing the interference from the sensor output includes subtracting the interference from the sensor output to yield the filtered output.

Turning toFIG. 1, a storage system100including a read channel circuit110having write interference mitigated touch down circuitry in accordance with various embodiments of the present invention. Storage system100may be, for example, a hard disk drive. Storage system100also includes a preamplifier170, an interface controller120, a hard disk controller166, a motor controller168, a spindle motor172, a disk platter178, and a read/write head176. Interface controller120controls addressing and timing of data to/from disk platter178. The data on disk platter178consists of groups of magnetic signals that may be detected by read/write head assembly176when the assembly is properly positioned over disk platter178. In one embodiment, disk platter178includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly176is accurately positioned by motor controller168over a desired data track on disk platter178. Motor controller168both positions read/write head assembly176in relation to disk platter178and drives spindle motor172by moving read/write head assembly to the proper data track on disk platter178under the direction of hard disk controller166. Spindle motor172spins disk platter178at a determined spin rate (RPMs). Once read/write head assembly176is positioned adjacent the proper data track, magnetic signals representing data on disk platter178are sensed by read/write head assembly176as disk platter178is rotated by spindle motor172. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter178. This minute analog signal is transferred from read/write head assembly176to read channel circuit110via preamplifier170. Preamplifier170is operable to amplify the minute analog signals accessed from disk platter178. In turn, read channel circuit110decodes and digitizes the received analog signal to recreate the information originally written to disk platter178. This data is provided as read data103to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data101being provided to read channel circuit110. This data is then encoded and written to disk platter178.

In addition to sensing data stored on disk platter178, read/write head assembly176provides for sensing contact between read/write head assembly176and disk platter178. Such sensing may be done by a write interference mitigated touch down circuit that receives a signal from a touch sensor, and filters any write data interference from the signal to yield a filtered signal. This filtered signal is then compared with a threshold value to yield a contact indication. In some cases, read channel circuit110is implemented similar to that disclosed in relation toFIG. 3abelow and the write interference mitigated touch down circuit may be implemented similar to that disclosed below in relation toFIG. 3b. Further, the systems may operate consistent with that discussed below in relation toFIGS. 5a-5b.

It should be noted that storage system100may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system100, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

A data decoder circuit used in relation to read channel circuit110may be, but is not limited to, a low density parity check (LDPC) decoder circuit as are known in the art. Such low density parity check technology is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as DRAM, NAND flash, NOR flash, other non-volatile memories and solid state drives.

In addition, it should be noted that storage system100may be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter178. This solid state memory may be used in parallel to disk platter178to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit110. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered by disk platted178. In such a case, the solid state memory may be disposed between interface controller120and read channel circuit110where it operates as a pass through to disk platter178when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter178and a solid state memory.

Turning toFIG. 2, a graphical depiction of an example read/write head assembly220disposed above a surface210of a storage medium278that may be used in relation to different embodiments of the present invention. As shown, read write head assembly220includes a heater element222that is operable to control a distance between read write head assembly220and surface210, a read/write head226operable to generate magnetic fields to store information on surface210and to sense magnetic information previously stored on surface210, and a head disk interface sensor228operable to sense contact between read/write head assembly220and surface210.

Turning toFIG. 3a, a data processing circuit300is shown that includes a write interference mitigated touch down circuit360in accordance with some embodiments of the present invention. Data processing circuit300includes an analog front end circuit310that receives an analog signal305. Analog front end circuit310processes analog signal305and provides a processed analog signal312to an analog to digital converter circuit314. Analog front end circuit310may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit310. In some cases, analog signal305is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal305is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input305may be derived.

Analog to digital converter circuit314converts processed analog signal312into a corresponding series of digital samples316. Analog to digital converter circuit314may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples316are provided to an equalizer circuit320. Equalizer circuit320applies an equalization algorithm to digital samples316to yield an equalized output325. In some embodiments of the present invention, equalizer circuit320is a digital finite impulse response filter circuit as are known in the art. It may be possible that equalized output325may be received directly from a storage device in, for example, a solid state storage system. In such cases, analog front end circuit310, analog to digital converter circuit314and equalizer circuit320may be eliminated where the data is received as a digital data input. Equalized output325is stored to an input buffer353that includes sufficient memory to maintain a number of codewords until processing of that codeword is completed through a data detector circuit330and decoder circuit370including, where warranted, multiple global iterations (passes through both data detector circuit330and decoder circuit370) and/or local iterations (passes through decoder circuit370during a given global iteration). An output357is provided to data detector circuit330.

Data detector circuit330may be a single data detector circuit or may be two or more data detector circuits operating in parallel on different codewords. Whether it is a single data detector circuit or a number of data detector circuits operating in parallel, data detector circuit330is operable to apply a data detection algorithm to a received codeword or data set. In some embodiments of the present invention, data detector circuit330is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector circuit330is a maximum a posteriori data detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. In some cases, one data detector circuit included in data detector circuit330is used to apply the data detection algorithm to the received codeword for a first global iteration applied to the received codeword, and another data detector circuit included in data detector circuit330is operable apply the data detection algorithm to the received codeword guided by a decoded output accessed from a central memory circuit350on subsequent global iterations.

Upon completion of application of the data detection algorithm to the received codeword on the first global iteration, data detector circuit330provides a detector output333. Detector output333includes soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. Detector output333is provided to a local interleaver circuit342. Local interleaver circuit342is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output and provides an interleaved codeword346that is stored to central memory circuit350. Interleaver circuit342may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set. Interleaved codeword346is stored to central memory circuit350.

Once decoder circuit370is available, a previously stored interleaved codeword346is accessed from central memory circuit350as a stored codeword386and globally interleaved by a global interleaver/de-interleaver circuit384. Global interleaver/de-interleaver circuit384may be any circuit known in the art that is capable of globally rearranging codewords. Global interleaver/De-interleaver circuit384provides a decoder input352into decoder circuit370. In some embodiments of the present invention, the data decode algorithm is a layered low density parity check algorithm as are known in the art. In other embodiments of the present invention, the data decode algorithm is a non-layered low density parity check algorithm as are known in the art.

Where decoded output371fails to converge (i.e., fails to yield the originally written data set) and a number of local iterations through decoder circuit370exceeds a threshold, the resulting decoded output is provided as a decoded output354back to central memory circuit350where it is stored awaiting another global iteration through a data detector circuit included in data detector circuit330. Prior to storage of decoded output354to central memory circuit350, decoded output354is globally de-interleaved to yield a globally de-interleaved output388that is stored to central memory circuit350. The global de-interleaving reverses the global interleaving earlier applied to stored codeword386to yield decoder input352. When a data detector circuit included in data detector circuit330becomes available, a previously stored de-interleaved output388is accessed from central memory circuit350and locally de-interleaved by a de-interleaver circuit344. De-interleaver circuit344re-arranges decoder output348to reverse the shuffling originally performed by interleaver circuit342. A resulting de-interleaved output397is provided to data detector circuit330where it is used to guide subsequent detection of a corresponding data set previously received as equalized output325.

Alternatively, where the decoded output converges (i.e., yields the originally written data set), the resulting decoded output is provided as an output codeword372to a de-interleaver circuit380that rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output382. De-interleaved output382is provided to a hard decision buffer circuit390that arranges the received codeword along with other previously received codewords in an order expected by a requesting host processor. The resulting output is provided as a hard decision output392.

Decoder circuit370is designed to accept codewords that are not constrained by a ‘1’ symbol in the final circulant in the codeword. This is facilitated by using a standard non-binary, low density parity check decoder circuit that is augmented to include an inverse mapping circuit to adjust a soft data output to compensate for the non-constrained circulant. Such an approach utilizes only a relatively small amount of additional circuitry, but results in an increased distance between possible accepted decoded outputs thereby reducing the likelihood of a mis-correction. One example implementation of decoder circuit370is described below in relation toFIG. 4below.

In addition, data processing circuit300includes write interference mitigated touch down circuit360that is operable to assert a touch down signal365when contact between a read/write head assembly and a storage medium is sensed. Write interference mitigated touch down circuit360receives a head/disk interface (“HDI”) input363that represents a temperature of a read/write head assembly. When a read/write head assembly contacts a storage medium, there is a dramatic increase in temperature of the read/write head assembly that causes a corresponding dramatic change in HDI input363. The assertion of a write gate369indicates a write to a storage medium is underway. Based upon this, write interference mitigated touch down circuit360mitigates interference in HDI input363from write data (magnetic fields) that is generated during a write process.

Turning toFIGS. 4a-4c, the processing of an HDI input is graphically depicted showing three scenarios. First, inFIG. 4a, a non-contact scenario410is shown including a servo region416and a data region413. As shown, non-contact scenario includes an HDI signal from a head disk interface sensor with an amplitude sufficient to indicate contact. The amplitude is increased above what the HDI signal is expected to be due to interference due to magnetic write signals generated by a read/write head near the head disk interface sensor. Second, inFIG. 4b, a filtered version420of non-contact scenario410is shown where the HDI signal corresponding to servo region416is filtered out using servo gate input367. In addition, a write interference portion425,427of data region413is separated from the overall signal. Third, inFIG. 4c, a write interference mitigated HDI output430shows write interference portions425,427subtracted from the data regions413of the non-contact scenario410. As shown, the amplitude of write interference mitigated HDI output430is substantially less than that shown inFIG. 4aand more in line with what the HDI signal would be in a non-contact scenario.

Returning toFIG. 3a, in some cases, write interference mitigated touch down circuit360includes an energy based head touch down sensor (not shown) as is more fully described in U.S. patent application Ser. No. 13/894,680 entitled “Systems and Methods for Energy Based Head Contact Detection”, and filed by Song et al. on a date even herewith. In such cases, the data region is indicated when servo gate input367is asserted low. The energy based head touch down sensor calculates an energy threshold to which the energy of HDI input363is compared. Where the energy of HDI input363is greater than the calculated energy threshold, touch down signal365is asserted indicating contact between the read/write head assembly and the storage medium. Otherwise, where HDI input363is less than the calculated energy threshold, touch down signal365is not asserted.

Turning toFIG. 3b, one implementation of write interference mitigated touch down circuit360ofFIG. 3ais shown in accordance with various embodiments of the present invention. A write interference mitigated touch down circuit900is shown that includes a coherent combination circuit901, a dimension shrinking circuit920, a least mean squared calculation circuit902, an interference elimination circuit903, a test data selection circuit950, and a touch down detector circuit970. As previously mentioned, touch down detector circuit970may be implemented similar to that disclosed in the previously incorporated patent application entitled “Systems and Methods for Energy Based Head Contact Detection” that asserts a touch down indicator972based upon a filtered HDI signal969. In other cases, touch down detector circuit970may be a simple comparator circuit that compares a filtered HDI signal969with a threshold value, and where filtered HDI signal969exceeds the threshold value a touch down indicator972is asserted.

Test data selection circuit950is operable to feed an X-data input905that is derived when the read/write head assembly is guaranteed not to be in contact with the storage medium. The resulting data from the HDI sensor during this period is referred to as training data and is provided as a data input952to coherent combination circuit901. At other times when training is not underway, test data selection circuit950feeds X-data input905that is derived when the read/write head assembly is not guaranteed to not be in contact with the storage medium. The resulting data from the HDI sensor during this period is referred to as test data and is provided as a data input952to coherent combination circuit901. Of note, when touch down indicator972is asserted, test data selection circuit950does not provide data input952to avoid introducing contact information included in X-data input905to an estimated write interference value962.

Coherent combination circuit901coherently combines the HDI signal (received as X-data input905) across a number of wedges (i.e., user data regions separated by servo regions) to yield a coherent output912. In particular, coherent combination circuit901includes a coherent calculation circuit910and a reset circuit915. Coherent calculation circuit910calculates coherent output912(z[n]) in accordance with the following equation:

Coherent⁢⁢Output⁢⁢912⁢⁢(z⁡[n])=1M⁢∑i=1M⁢Data⁢⁢Input⁢⁢952i.
Such a running average may be implemented using a hardware efficient approach consistent with the following equation:

z⁡[n]=1M+1⁢(z⁡[n]*M+Data⁢⁢Input⁢⁢952),
where M is incremented as each instance of data input952is incorporated into the running average. Again, data input952is only included in the aforementioned calculation when a non-contact situation (indicated by de-assertion of touch down indicator972). Reset circuit915receives a clear signal907, and upon receiving clear signal907, reset circuit915resets both M and data input952. This allows coherent combination circuit901to track slow varying interference caused by writing via the read/write head disposed near the head disk interface sensor.

Coherent output912includes a substantial amount of data that directly correlates to a sampling frequency of received data. Application of a least mean squares algorithm to such a substantial amount of data results in a complex and costly computational load. To avoid having to operate on an unwieldy amount of data, dimension shrinking circuit920transforms coherent output912from a z[n] space into a u[n] space. The dimension of the data in the z[n] space a power of P as shown in the following equations:
z[1]=a0+a1(Δt)+a2(Δt)2+ . . . +aP(Δt)P+v[1];
z[2]=a0+a1(2Δt)+a2(2Δt)2+ . . . +aP(2Δt)P+v[2];
z[2]=a0+a1(nΔt)+a2(nΔt)2+ . . . +aP(nΔt)P+v[n].
The preceding equations may be recast as follows:
z=Ha+v.
Dimension shrinking circuit920recasts coherent output912in accordance with the following equation:
u=Ga+{tilde over (v)},
based upon a transform defined by the following equation:
HTz=HTHa+HTv.
Such an approach reduces the power of P dimension of the z[n] space to a P+1 dimension exhibited by the u[n] space.

In particular, dimension shrinking circuit920calculates u and g components in accordance with the following equations:

gp,k=∑i=1N⁢(i⁢⁢Δ⁢⁢t)P+k-2;andup=∑i=1N⁢(i⁢⁢Δ⁢⁢t)P-1⁢z⁡[i].
In one particular embodiment of the present invention, P is selected as nine (9). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of P that may be used in relation to different embodiments of the present invention. upis provided as a space converted output922, and gp,kis provided as space converted output924.

Space converted output922and space converted output924are provided to least mean squared calculation circuit902. Least mean squared calculation circuit902is an efficient reformulation of the following least mean squared algorithm:

To implement the aforementioned equations, least mean squared calculation circuit902includes a component calculation circuit930, a least mean squared circuit935, and a comparator circuit940. Component calculation circuit930sums a product of space converted output922and space converted output924over the dimension of the u[n] space in accordance with the following equation:

ck=∑p=1P+1⁢(gp,k)⁢(up);and⁢dl=∑p=1P+1⁢(gp,k)⁢(gp,l).
Ckand dlare provided as a component output932to least mean squared circuit935where they are used to calculate a current least mean squared value937in accordance with the following equation:

Least⁢⁢Mean⁢⁢Squared⁢⁢Value⁢⁢937=Least⁢⁢Mean⁢⁢Squared⁢⁢Value⁢⁢937-λ⁡[ck-∑l=1P+1⁢al⁢dl].
Least mean squared value937is provided to comparator circuit940where it is compared with an error threshold value909. Error threshold value909may be either user programmable or fixed depending upon the particular implementation. Recalculation of least mean squared value937continues until it is below error threshold909.

In addition, least mean squared value937is provided to touch down detection circuit903. Touch down detection circuit903includes an interference estimation circuit960and an estimated interference elimination circuit960. Interference estimation circuit960calculates an estimated interference962in accordance with the following equation:

Turning toFIGS. 5a-5b, a flow diagram500shows a method for contact detection in accordance with some embodiments of the present invention. Turning specifically toFIG. 5aand following flow diagram500, a distance between the read/write head assembly and the storage medium is increased to guarantee an HDI signal represents no contact for use as training data (block505). By increasing the distance, it can be assure that the data received as the HDI signal does not include any signal indicative of a contact as in the absence of interference, the HDI signal should be approximately zero. Thus, any signal greater than zero that provided as the HDI signal during this period is likely due to interference. This interference may be from magnetization of the write head.

A coherent output is calculated based upon the received HDI signal in accordance with the following equation (block510):

Coherent⁢⁢Output⁢⁢(z⁡[n])=1M⁢∑i=1M⁢HDI⁢⁢Signali.
Such a running average may be implemented using a hardware efficient approach consistent with the following equation:

z⁡[n]=1M+1⁢(z⁡[n]*M+HDI⁢⁢Signal),
where M is incremented as each instance of the HDI signal is incorporated into the running average.

The coherent output is transformed to a different space to minimize the dimension (block515). This conversion may be from the preceding z[n] space to a u[n] space in accordance with the following process:
z[1]=a0+a1(Δt)+a2(Δt)2+ . . . +aP(Δt)P+v[1];
z[2]=a0+a1(2Δt)+a2(2Δt)2+ . . . +aP(2Δt)P+v[2];
z[2]=a0+a1(nΔt)+a2(nΔt)2+ . . . +aP(nΔt)P+v[n].
As noted in the preceding equation, the dimension of the z[n] space is P. The preceding equations may be recast as follows:
z=Ha+v.
Based upon this, the following equation may be used to perform the dimension transform:
u=Ga+{tilde over (v)},
based upon a transform defined by the following equation:
HTz=HTHa+HTv.
Such an approach reduces the power of P dimension of the z[n] space to a P+1 dimension exhibited by the u[n] space. In particular, the dimension transform may be implemented by calculating u and g components in accordance with the following equations:

gp,k=∑i=1N⁢(i⁢⁢Δ⁢⁢t)P+k-2;andup=∑i=1N⁢(i⁢⁢Δ⁢⁢t)P-1⁢z⁡[i].
In one particular embodiment of the present invention, P is selected as nine (9). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of P that may be used in relation to different embodiments of the present invention.

Using the aforementioned u and g components a least mean squared value is calculated (block520). This calculation may be done in accordance with the following equations:

ck=∑p=1P+1⁢(gp,k)⁢(up);⁢dl=∑p=1P+1⁢(gp,k)⁢(gp,l).
Using the aforementioned Ckand dlelements the least mean squared value is calculated in accordance with the following iterative equation:

Least⁢⁢Mean⁢⁢Squared⁢⁢Value=Least⁢⁢Mean⁢⁢Squared⁢⁢Value-λ⁡[ck-∑l=1P+1⁢al⁢dl].
The least mean squared value is compared with an error threshold value (block525). Where the least mean squared value is greater than the error threshold value (block525), the processes of blocks510-525are repeated. Alternatively, where the least mean squared value is greater than the error threshold value (block525), an estimated interference in the HDI signal is calculated based upon the least mean squared value (block530). The estimated interference is calculated in accordance with one or more embodiments of the present invention:

Estimated⁢⁢Interference=∑p=0P⁢least⁢⁢mean⁢⁢squared⁢⁢valuep⁡(n⁢⁢Δ⁢⁢t)P.
It is then determined whether more training data (i.e., data generated when the read/write head assembly is a substantial difference from the storage device) is to be processed (block535). Where additional training information is to be processed (block535), the processes beginning at block510are performed for the next instance of data received.

Alternatively, where no additional training data remains to be processed (block535), the processes beginning onFIG. 5bbegins. Turning toFIG. 5b, the distance between the read/write head assembly and the storage medium is allowed to move such that a no contact condition can no longer be guaranteed (block540). As such, the received HDI signal may include contact information in addition to any interference. The previously calculated estimated interference is subtracted from the original HDI signal to yield a filtered output (block545). The filtered output is substantially limited to only data indicative of a contact scenario. This filtered output is compared with a contact threshold value to determine whether the read/write head assembly came into contact with the storage medium (block550). Where the filtered output is greater than the threshold value, therefore indicating contact (block550), the recently received data is excluded from inclusion in updating the estimated interference (block555) and the processes of blocks540-550are repeated. In addition, while not shown in a specific block, a contact indicator is provided as an output.

Alternatively, where the filtered output is less than or equal to the threshold value, therefore indicating no contact (block550), the recently received data is used to update the estimated interference. In particular, a coherent output is calculated based upon the received HDI signal in accordance with the following equation (block560). This coherent output is calculated the same way it was calculated in block510above. The coherent output is then transformed to a different space to minimize the dimension (block565). This transform may be done similar to that discussed above in relation to block515. A least mean squared value is then calculated using the space converted outputs (block570). This calculation may be done similar to that discussed above in relation to block520. It is then determined whether the least mean squared value is less than the error threshold (block575). Where the least mean squared value is greater than or equal to the error threshold (block575), the processes beginning at block545are repeated. Alternatively, where the least mean squared value is less than the error threshold (block575), the estimated interference is updated based on the least mean squared value (block580). The estimated interference may be updated consistent with that discussed above in relation to block530.