Direct logical block addressing flash memory mass storage architecture

A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid erase cycles each time information stored in the mass storage is changed. Erase cycle are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address

FIELD OF THE INVENTION 
This invention relates to the field of mass storage for computers. More 
particularly, this invention relates to an architecture for replacing a 
hard disk with a semiconductor nonvolatile memory and in particular flash 
memory. 
BACKGROUND OF THE INVENTION 
Computers conventionally use rotating magnetic media for mass storage of 
documents, data, programs and information. Though widely used and commonly 
accepted, such hard disk drives suffer from a variety of deficiencies. 
Because of the rotation of the disk, there is an inherent latency in 
extracting information from a hard disk drive. 
Other problems are especially dramatic in portable computers. In 
particular, hard disks are unable to withstand many of the kinds of 
physical shock that a portable computer will likely sustain. Further, the 
motor for rotating the disk consumes significant amounts of power 
decreasing the battery life for portable computers. 
Solid state memory is an ideal choice for replacing a hard disk drive for 
mass storage because it can resolve the problems cited above. Potential 
solutions have been proposed for replacing a hard disk drive with a 
semiconductor memory. For such a system to be truly useful, the memory 
must be nonvolatile and alterable. The inventors have determined that 
FLASH memory is preferred for such a replacement. 
FLASH memory is a transistor memory cell which is programmable through hot 
electron, source injection, or tunneling, and erasable through 
Fowler-Nordheim tunneling. The programming and erasing of such a memory 
cell requires current to pass through the dielectric surrounding floating 
gate electrode. Because of this, such types of memory have a finite number 
of erase-write cycles. Eventually, the dielectric deteriorates. 
Manufacturers of FLASH cell devices specify the limit for the number of 
erase-write cycles between 100,000 and 1,000,000. 
One requirement for a semiconductor mass storage device to be successful is 
that its use in lieu of a rotating media hard disk mass storage device be 
transparent to the designer and the user of a system using such a device. 
In other words, the designer or user of a computer incorporating such a 
semiconductor mass storage device could simply remove the hard disk and 
replace it with a semiconductor mass storage device. All presently 
available commercial software should operate on a system employing such a 
semiconductor mass storage device without the necessity of any 
modification. 
SunDisk proposed an architecture for a semiconductor mass storage using 
FLASH memory at the Silicon Valley PC Design Conference on Jul. 9, 1991. 
That mass storage system included read-write block sizes of 512 Bytes to 
conform with commercial hard disk sector sizes. 
Earlier designs incorporated erase-before-write architectures. In this 
process, in order to update a file on the media, if the physical location 
on the media was previously programmed, it has to be erased before the new 
data can be reprogrammed. 
This process would have a major deterioration on overall system throughput. 
When a host writes a new data file to the storage media, it provides a 
logical block address to the peripheral storage device associated with 
this data file. The storage device then translates this given logical 
block address to an actual physical block address on the media and 
performs the write operation. In magnetic hard disk drives, the new data 
can be written over the previous old data with no modification to the 
media. Therefore, once the physical block address is calculated from the 
given logical block address by the controller, it will simply write the 
data file into that location. In solid state storage, if the location 
associated with the calculated physical block address was previously 
programmed, before this block can be reprogrammed with the new data, it 
has to be erased. In one previous art, in erase-before-write architecture 
where the correlation between logical block address given by the host is 
one to one mapping with physical block address on the media. This method 
has many deficiencies. First, it introduces a delay in performance due to 
the erase operation before reprogramming the altered information. In solid 
state flash, erase is a very slow process. 
Secondly, hard disk users typically store two types of information, one is 
rarely modified and another which is frequently changed. For example, a 
commercial spread sheet or word processing software program stored on a 
user's system are rarely, if ever, changed. However, the spread sheet data 
files or word processing documents are frequently changed. Thus, different 
sectors of a hard disk typically have dramatically different usage in 
terms of the number of times the information stored thereon is changed. 
While this disparity has no impact on a hard disk because of its 
insensitivity to data changes, in a FLASH memory device, this variance can 
cause sections of the mass storage to wear out and be unusable 
significantly sooner than other sections of the mass storage. 
In another architecture, the inventors previously proposed a solution to 
store a table correlating the logical block address to the physical block 
address. The inventions relating to that solution are disclosed in U.S. 
Pat. No. 5,388,083, issued on Feb. 7, 1995 and U.S. Pat. No. 5,479,638, 
issued on Dec. 26, 1995. Those applications are incorporated herein by 
reference. 
The inventors' previous solution discloses two primary algorithms and an 
associated hardware architecture for a semiconductor mass storage device. 
It will be understood that "data file" in this patent document refers to 
any computer file including commercial software, a user program, word 
processing software document, spread sheet file and the like. The first 
algorithm in the previous solution provides means for avoiding an erase 
operation when writing a modified data file back onto the mass storage 
device. Instead, no erase is performed and the modified data file is 
written onto an empty portion of the mass storage. 
The semiconductor mass storage architecture has blocks sized to conform 
with commercial hard disk sector sizes. The blocks are individually 
erasable. In one embodiment, the semiconductor mass storage can be 
substituted for a rotating hard disk with no impact to the user, so that 
such a substitution will be transparent. Means are provided for avoiding 
the erase-before-write cycle each time information stored in the mass 
storage is changed. 
According to the first algorithm, erase cycles are avoided by programming 
an altered data file into an empty block. This would ordinarily not be 
possible when using conventional mass storage because the central 
processor and commercial software available in conventional computer 
systems are not configured to track continually changing physical 
locations of data files. The previous solution includes a programmable map 
to maintain a correlation between the logical address and the physical 
address of the updated information files. 
All the flags, and the table correlating the logical block address to the 
physical block address are maintained within an array of CAM cells. The 
use of the CAM cells provides very rapid determination of the physical 
address desired within the mass storage, generally within one or two clock 
cycles. Unfortunately, as is well known, CAM cells require multiple 
transistors, typically six. Accordingly, an integrated circuit built for a 
particular size memory using CAM storage for the tables and flags will 
need to be significantly larger than a circuit using other means for just 
storing the memory. 
The inventors proposed another solution to this problem which is disclosed 
in U.S. Pat. No. 5,485,595, issued on Jan. 16, 1996. That application is 
incorporated herein by reference. 
This additional previous solution invented by these same inventors is also 
for a nonvolatile memory storage device. The device is also configured to 
avoid having to perform an erase-before-write each time a data file is 
changed by keeping a correlation between logical block address and 
physical block address in a volatile space management RAM. Further, this 
invention avoids the overhead associated with CAM cell approaches which 
require additional circuitry. 
Like the solutions disclosed above by these same inventors, the device 
includes circuitry for performing the two primary algorithms and an 
associated hardware architecture for a semiconductor mass storage device. 
In addition, the CAM cell is avoided in this previous solution by using 
RAM cells. 
Reading is performed in this previous solutions by providing the logical 
block address to the memory storage. The system sequentially compares the 
stored logical block addresses until it finds a match. That data file is 
then coupled to the digital system. Accordingly, the performance offered 
by this solution suffers because potentially all of the memory locations 
must be searched and compared to the desired logical block address before 
the physical location of the desired information can be determined. 
What is needed is a semiconductor hard disk architecture which provides 
rapid access to stored data without the excessive overhead of CAM cell 
storage. 
SUMMARY OF THE INVENTION 
The present invention is for a nonvolatile memory storage device. The 
device is configured to avoid having to perform an erase-before-write each 
time a data file is changed. Further, to avoid the overhead associated 
with CAM cells, this approach utilizes a RAM array. The host system 
maintains organization of the mass storage data by using a logical block 
address. The RAM array is arranged to be addressable by the same address 
as the logical block addresses of the host. Each such addressable location 
in the RAM includes a field which holds the physical address of the data 
in the nonvolatile mass storage expected by the host. This physical block 
address information must be shadowed in the nonvolatile memory to ensure 
that the device will still function after resuming operation after a power 
down because Rams are volatile memory devices. In addition, status flags 
are also stored for each physical location. The status flags can be stored 
in either the nonvolatile media or in both the RAM and in the nonvolatile 
media. 
The device includes circuitry for performing two primary algorithms and an 
associated hardware architecture for a semiconductor mass storage device. 
The first algorithm provides a means for mapping of host logical block 
address to physical block address with much improved performance and 
minimal hardware assists. In addition, the second algorithm provides means 
for avoiding an erase-before-write cycle when writing a modified data file 
back onto the mass storage device. Instead, no erase is performed and the 
modified data file is written onto an empty portion of the mass storage. 
Reading is performed in the present invention by providing the logical 
block address to the memory storage. The RAM array is arranged so that the 
logical block address selects one RAM location. That location contains the 
physical block address of the data requested by the host or other external 
system. That data file is then read out to the host. 
According to the second algorithm, erase cycles are avoided by programming 
an altered data file into an empty mass storage block rather than itself 
after an erase cycle of the block as done on previous arts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 shows an architecture for implementation of a solid state storage 
media according to the present invention. The storage media is for use 
with a host or other external digital system. The mass storage is 
partitioned into two portions, a volatile RAM array 100 and a nonvolatile 
array 104. According to the preferred embodiment, all of the nonvolatile 
memory storage is FLASH. The FLASH may be replaced by EEPROM. The RAM can 
be of any convenient type. 
The memory storage 104 is arranged into N blocks of data from zero through 
N-1. Each of the blocks of data is M Bytes long. In the preferred 
embodiment, each data block is 512 Bytes long to correspond with a sector 
length in a commercially available hard disk drive plus the extra numbers 
of bytes to store the flags and logical block address information and the 
associated ECC. The memory 104 can contain as much memory storage as a 
user desires. An example of a mass storage device might include 100M Byte 
of addressable storage. 
There are a plurality of RAM locations 102. Each RAM location 102 is 
uniquely addressable by controller using an appropriate one of the logical 
block addresses provided by the host system or the actual physical address 
of the nonvolatile media. The RAM location 102 contains the physical block 
address of the data associated with the logical block address and the 
flags associated with a physical block address on the nonvolatile media. 
It is possible that the physical block address can be split into two fields 
as shown in FIG. 2. These fields can be used for cluster addresses of a 
group of data blocks. The first such field 290 is used to select a cluster 
address and the second such field 292 can be used to select the start 
address of the logical block address associated with this cluster. 
A collection of information flags is also stored for each nonvolatile 
memory location 106. These flags include an old/new flag 110, a used/free 
flag 112, a defect flag 114, and a single/sector flag 116. Additionally, 
there is also a data store 122. 
When writing data to the mass storage device of the present invention, a 
controller determines the first available physical block for storing the 
data. The RAM location 102 corresponding to the logical block address 
selected by the host is written with the physical block address where the 
data is actually stored within the nonvolatile memory array in 104 (FIG. 
1). 
Assume for example that a user is preparing a word processing document and 
instructs the computer to save the document. The document will be stored 
in the mass storage system. The host system will assign it a logical block 
address. The mass storage system of the present invention will select a 
physical address of an unused block or blocks in the mass storage for 
storing the document. The address of the physical block address will be 
stored into the RAM location 102 corresponding to the logical block 
address. As the data is programmed, the system of the present invention 
also sets the used/free flag 112 in 104 and 293 to indicate that this 
block location is used. One used/free flag 112 is provided for each entry 
of the nonvolatile array 104. 
Later, assume the user retrieves the document, makes a change and again 
instructs the computer to store the document. To avoid an 
erase-before-write cycle, the system of the present invention provides 
means for locating a block having its used/free flag 112 in 100 unset (not 
programmed) which indicates that the associated block is erased. The 
system then sets the used/free flag for the new block 112 of 106 and 293 
of 100 and then stores the modified document in that new physical block 
location 106 in the nonvolatile array 104. The address of the new physical 
block location is also stored into the RAM location 102 corresponding the 
logical block address, thereby writing over the previous physical block 
location in 102. Next, the system sets the old/new flag 110 of the 
previous version of the document indicating that this is an old unneeded 
version of the document in 110 of 104 and 293 of 100. In this way, the 
system of the present invention avoids the overhead of an erase cycle 
which is required in the erase-before-write of conventional systems to 
store a modified version of a previous document. 
Because of RAM array 100 will lose its memory upon a power down condition, 
the logical block address with the active physical block address in the 
media is also stored as a shadow memory 108 in the nonvolatile array 104. 
It will be understood the shadow information will be stored into the 
appropriate RAM locations 102 by the controller. During power up sequence, 
the RAM locations in 100 are appropriately updated from every physical 
locations in 104, by reading the information 106 of 104. The logical 
address 108 of 106 is used to address the RAM location of 100 to update 
the actual physical block address associated with the given logical block 
address. Also since 106 is the actual physical block address associated 
with the new data 122, the flags 110, 112, 114, and 116 are updated in 293 
of 102 with the physical block address of 106 in 100. It will be apparent 
to one of ordinary skill in the art that the flags can be stored in either 
the appropriate nonvolatile memory location 106 or in both the nonvolatile 
memory location and also in the RAM location 102 associated with the 
physical block address. 
During power up, in order to assign the most recent physical block address 
assigned to a logical block address in the volatile memory 100, the 
controller will first reads the Flags 110, 112, 114, and 116 portion of 
the nonvolatile memory 104 and updates the flags portion 293 in the 
volatile memory 100. Then it reads the logical block address 108 of every 
physical block address of the nonvolatile media 104 and by tracking the 
flags of the given physical block address in the volatile memory 100, and 
the read logical block address of the physical block address in the 
nonvolatile memory 104, it can update the most recent physical block 
address assigned to the read logical block address in the volatile memory 
100. 
FIG. 3 shows a block diagram of a system incorporating the mass storage 
device of the present invention. An external digital system 300 such as a 
host computer, personal computer and the like is coupled to the mass 
storage device 302 of the present invention. A logical block address is 
coupled via an address bus 306 to the volatile RAM array 100 and to a 
controller circuit 304. Control signals are also coupled to the controller 
304 via a control bus 308. The volatile RAM array 100 is coupled via data 
paths 140 for providing the physical block address to the nonvolatile RAM 
array 104. The controller 304 is coupled to control both the volatile RAM 
100, the nonvolatile array 104, and for the generation of all flags. 
A simplified example, showing the operation of the write operation 
according to the present invention is shown in FIGS. 4 through 8. Not all 
the information flags are shown to avoid obscuring these features of the 
invention in excessive detail. The data entries are shown using decimal 
numbers to further simplify the understanding of the invention. It will be 
apparent to one of ordinary skill in the art that in a preferred 
embodiment binary counting will be used. 
FIG. 4 shows an eleven entry mass storage device according to the present 
invention. There is no valid nor usable data stored in the mass storage 
device of FIG. 4. Accordingly, all the physical block addresses are empty. 
The data stored in the nonvolatile mass storage location `6` is filled and 
old. Additionally, location `9` is defective and cannot be used. 
The host directs the mass storage device of the example to write data 
pursuant to the logical block address `3` and then to `4`. The mass 
storage device will first write the data associated with the logical block 
address `3`. The device determines which is the first unused location in 
the nonvolatile memory. In this example, the first empty location is 
location `0`. Accordingly, FIG. 5 shows that for the logical block address 
`3`, the corresponding physical block address `0` is stored and the used 
flag is set in physical block address `0`. The next empty location is 
location `1`. FIG. 6 shows that for the logical block address `4`, the 
corresponding physical block address `1` is stored and the used flag is 
set in physical block address `1`. 
The host instructs that something is to be written to logical block address 
`3` again. The next empty location is determined to be location `2`. FIG. 
7 shows that the old flag in location `0` is set to indicate that this 
data is no longer usable, the used flag is set in location `2` and the 
physical block address in location `3` is changed to `2`. 
Next, the host instructs that something is to be written to logical block 
address `4` again. The next empty location is determined to be location 
`3`. FIG. 8 shows that the old flag in location `1` is set to indicate 
that this data is no longer usable, the used flag is set in location `3` 
and the physical block address in location `4` is changed to `3`. (Recall 
that there is generally no relation between the physical block address and 
the data stored in the same location.) 
FIG. 9 shows algorithm 1 according to the present invention. When the 
system of the present invention receives an instruction to program data 
into the mass storage (step 200), then the system attempts to locate a 
free block (step 202), i.e., a block having an unset (not programmed) 
used/free flag. If successful, the system sets the used/free flag for that 
block and programs the data into that block (step 206). 
If on the other hand, the system is unable to locate a block having an 
unset used/free flag, the system erases the flags (used/free and old/new) 
and data for all blocks having a set old/new flag and unset defect flag 
(step 204) and then searches for a block having an unset used/free flag 
(step 202). Such a block has just been formed by step 204. The system then 
sets the used/flag for that block and programs the data file into that 
block (step 206). 
If the data is a modified version of a previously existing file, the system 
must prevent the superseded version from being accessed. The system 
determines whether the data file supersedes a previous data file (step 
208). If so, the system sets the old/new flag associated with the 
superseded block (step 210). If on the other hand, the data file to be 
stored is a newly created data file, the step of setting the old/new flag 
(step 210) is skipped because there is no superseded block. Lastly, the 
map for correlating the logical address 108 to the physical address 130 is 
updated (step 212). 
By following the procedure outlined above, the overhead associated with an 
erase cycle is avoided for each write to the memory 104 except for 
periodically. This vastly improves the performance of the overall computer 
system employing the architecture of the present invention. 
In the preferred embodiment of the present invention, the programming of 
the flash memory follows the procedure commonly understood by those of 
ordinary skill in the art. In other words, the program impulses are 
appropriately applied to the bits to be programmed and then compared to 
the data being programmed to ensure that proper programming has occurred. 
In the event that a bit fails to be erased or programmed properly, a 
defect flag 114 (in FIG. 1) is set which prevent that block from being 
used again. 
The present invention is described relative to a preferred embodiment. 
Modifications or improvements which apparent to one of ordinary skill in 
the art after reading this disclosure are deemed within the spirit and 
scope of this invention.