Neuromorphic device including gating lines with different widths

A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.

TECHNICAL FIELD

Exemplary embodiments relate to a neuromorphic device, and more particularly, to a neuromorphic device including a plurality of gating lines that surround an outer surface of a synapse and that have different widths.

DISCUSSION OF THE RELATED ART

Recently, much attention has been paid to neuromorphic technology, which uses chips that mimic the human brain. A neuromorphic device based on the neuromorphic technology includes a plurality of pre-synaptic neurons, a plurality of post-synaptic neurons, and a plurality of synapses. The neuromorphic device outputs pulses or spikes having various levels, magnitudes, or times, according to learning states of the neuromorphic device. A synapse system of the neuromorphic device has an improved performance when the synapse system has multiple resistance levels.

SUMMARY

Various embodiments are directed to a synapse system which has multiple resistance levels by using gating lines with various widths.

Various embodiments are directed to a neuromorphic device including a synapse system which has multiple resistance levels by using gating lines with various widths.

Various objects to be achieved by the disclosure are not limited to the aforementioned objects, and those skilled in the art to which the disclosure pertains may clearly understand other objects from the following descriptions.

In an embodiment, a neuromorphic device may include: a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.

The plurality of gating lines may be disposed to be parallel.

At least one of the plurality of gating lines may be parallel to one of the row line and the column line.

The plurality of gating lines may have different thicknesses.

The plurality of gating lines may respectively surround portions of an outer surface of the synapse.

The neuromorphic device may further include a plurality of absorption layers respectively disposed between the plurality of gating lines and the synapse.

Each of the plurality of absorption layers may include an oxidizable metal.

The plurality of absorption layers may have hollow cylinder shapes that respectively surround portions of an outer surface of the synapse.

The neuromorphic device may further include a plurality of barrier layers respectively disposed between the plurality of gating lines and the plurality of absorption layers.

Each of the plurality of barrier layers may include one or more of gold (Au), platinum (Pt), silver (Ag), nickel (Ni), tin (Sn), chrome (Cr), titanium nitride (TiN), tungsten nitride (WN), another metal nitride, and an oxidization-resistant conductive material.

The plurality of barrier layers may have hollow cylinder shapes that respectively surround outer surfaces of the plurality of absorption layers.

The synapse may include a core and a tunnel layer. The core may have a pillar shape. The tunnel layer may surround an outer surface of the core.

The core may include a perovskite-based material.

The tunnel layer may include one of a silicon oxide, a silicon nitride, or a combination thereof.

The plurality of gating lines may include at least three gating lines having different thicknesses.

The core may include oxygen, and the at least three gating lines may include an oxidizable metal.

The neuromorphic device may further include at least three absorption layers respectively disposed between the at least three gating lines and the synapse to surround portions of an outer surface of the synapse, Each of the at least three absorption layers may include an oxidizable metal.

The neuromorphic device may further include at least three barrier layers respectively disposed between the at least three gating lines and the at least three absorption layers. Each of the at least three barrier layers may include an oxidization-resistant metal.

In an embodiment, a neuromorphic device may include: a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a synapse disposed between the row line and the column line, the synapse having a pillar shape; and a plurality of gating lines disposed between the row line and the column line, the plurality of gating line respectively surrounding portions of an outer surface of the synapse. The synapse may have a core and a tunnel layer. The core may include oxygen. The tunnel layer may surround an outer surface of the core and pass oxygen ions. The plurality of gating lines may extend to be parallel to at least one of the row line and the column line. The plurality of gating lines may have different thicknesses. Portions of the plurality of gating lines may be oxidizated by being coupled with the oxygen ions that passed through the tunnel layer from the core.

The plurality of gating lines comprises at least three gating lines.

DETAILED DESCRIPTION

In the present disclosure, advantages, features, and methods for achieving them will become more apparent after a reading of the following exemplary embodiments taken in conjunction with the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Terms used in this specification are used for describing various embodiments, and do not limit the invention. As used herein, a singular form is intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms ‘includes’ and/or ‘including,’ when used in this specification, specify the presence of at least one stated feature, step, operation, and/or element, but do not preclude the presence or addition of one or more other features, steps, operations, and/or elements thereof.

When one element is referred to as being ‘connected to’ or ‘coupled to’ another element, it may indicate that the former element is directly connected or coupled to the latter element or another element is interposed therebetween. On the other hand, when one element is referred to as being ‘directly connected to’ or ‘directly coupled to’ another element, it may indicate that no element is interposed therebetween. Furthermore, ‘and/or’ includes each of described items and one or more combinations.

The terms such as ‘below,’ ‘beneath,’ ‘lower,’ ‘above,’ and ‘upper,’ which are spatially relative terms, may be used to describe the correlation between one element or components and another element or other components, as illustrated in the drawings. The spatially relative terms should be understood as terms including different directions of elements during the use or operation, in addition to the directions illustrated in the drawings. For example, when an element illustrated in a drawing is turned over, the element which is referred to as being ‘below’ or ‘beneath’ another element may be positioned above another element.

Moreover, various embodiments of this specification will be described with reference to cross-sectional views and/or plan views which are ideal exemplary diagrams of the invention. In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the disclosure should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing processes. For example, an angled region may have a round shape or a certain curvature. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

Throughout the specification, like reference numerals refer to like elements. Therefore, although the same or similar reference numerals are not mentioned or described in a corresponding drawing, the reference numerals may be described with reference to other drawings. Furthermore, although elements are not represented by reference numerals, the elements may be described with reference to other drawings.

In this specification, ‘potentiation,’ ‘set,’ ‘learning,’ and ‘training’ may be used as the same or similar terms, and ‘depressing,’ ‘reset,’ and ‘initiation’ may be used as the same or similar terms. For example, an operation of lowering resistance values of synapses may be exemplified as potentiation, setting, learning, or training; and an operation of raising resistance values of synapses may be exemplified as depressing, resetting, or initiation. Furthermore, when a synapse is potentiated, set, or trained, a gradually increasing voltage/current may be outputted from the synapse because the conductivity of the synapse is increasing. When a synapse is depressed, reset, or initiated, a gradually decreasing voltage/current may be outputted from the synapse because the conductivity of the synapse is decreasing. For convenience of description, a data pattern, an electrical signal, a pulse, a spike, and a firing may be interpreted as having the same, similar, or a compatible meaning. Furthermore, a voltage and a current may also be interpreted as having the same or a compatible meaning.

FIGS. 1A to 1Care block diagrams conceptually illustrating neuromorphic devices in accordance with various embodiments of the present disclosure.

Referring toFIG. 1A, a neuromorphic device may include pre-synaptic neurons10, row lines15, post-synaptic neurons20, column lines25, synapses30, row gating controllers40R, and row gating lines50R. The row lines15and the row gating lines50R may be arranged in parallel with each other.

The pre-synaptic neurons10may transmit electrical signals to the synapses30through the row lines15in a learning mode, a reset mode, or a reading mode.

The post-synaptic neurons20may transmit electrical signals to the synapses30through the column lines25in the learning mode or the reset mode, and may receive electrical signals from the synapses30through the column lines25in the reading mode.

The respective row lines15may extend from the respective pre-synaptic neurons10in a row direction, and may be electrically coupled to the synapses30.

The respective column lines25may extend from the respective post-synaptic neurons20in a column direction, and may be electrically coupled to the synapses30.

The row gating controllers40R may provide gating signals to the synapses30through the row gating lines50R.

The respective row gating lines50R may extend from the respective row gating controllers40R in the row direction, and may be electrically coupled to the synapses30.

The synapses30may be disposed at intersections of the row lines15and the column lines25. Synapses30which share the same row line15may share the same row gating line50R.

Referring toFIG. 1B, a neuromorphic device may include pre-synaptic neurons10, row lines15, post-synaptic neurons20, column lines25, synapses30, column gating controllers40C, and column gating lines50C. The column gating controllers40C may provide gating signals to the synapses30through the column gating lines50C. The respective column gating lines50C may extend from the respective column gating controllers40C in a column direction, and may be electrically coupled to the synapses30. Synapses30that share the same column line25may also share the same column gating line50C.

Referring toFIG. 1C, a neuromorphic device may include pre-synaptic neurons10, row lines15, post-synaptic neurons20, column lines25, synapses30, row gating controllers40R, column gating controllers40C, row gating lines50R, and column gating lines50C. The row gating controllers40R may provide gating signals to the synapses30through the row gating lines50R, and the column gating controllers40C may provide gating signals to the synapses30through the column gating lines50C. The synapses30that share the same row line15may also share the same row gating line50R. Synapses30that share the same column line25may also share the same column gating line50C. That is to say, each of the synapses30may be electrically coupled to a corresponding one of the row lines15, a corresponding one of the column lines25, a corresponding one of the row gating lines50R, and a corresponding one of the column gating lines50C.

FIGS. 2A to 2Dare perspective views conceptually illustrating synapse systems of neuromorphic devices in accordance with various embodiments of the present disclosure.

Referring toFIG. 2A, a synapse system of a neuromorphic device may include a row line15, a column line25, a synapse30, and a row gating line50R. The row line15may have a line shape and extend in a row direction. The row gating line50R may have a line shape, may extend in the row direction, and may be disposed above the row line15to be in parallel with the row line15. The column line25may have a line shape, may extend in a column direction perpendicular to the row direction, and may be disposed above the row line15and the row gating line50R. The synapse30may be disposed between the row line15and the column line25. InFIG. 2A, the row direction may correspond to an X-axis direction, and the column direction may correspond to a Y-axis direction.

In a top view, the synapse30may be disposed at an intersection of the row line15and the column line25. That is, the synapse30may be disposed in an intersection region between the row line15and the column line25. A bottom end of the synapse30may directly contact the row line15, and a top end of the synapse30may directly contact the column line25. The synapse30may pass through the row gating line50R in a Z-axis direction. Thus, the row gating line50R may surround a side surface, i.e., a sidewall, of the synapse30. In another embodiment of the present disclosure, positions of the row line15and the column line25may be changed with each other. That is, the row line15may be disposed over the row gating line50R and the column line25.

Referring toFIG. 2B, a synapse system of a neuromorphic device may include a row line15that extends in a row direction, a column line25that extends in a column direction, a synapse30, and a column gating line50C that extends in the column direction. The column gating line50C may have a line shape, may extends in the column direction, and may be disposed above the row line15and below the column line25to be in parallel with the column line25. The synapse30may pass through the column gating line50C, and thus the column gating line50C may surround a side surface, i.e., a sidewall, of the synapse30.

Referring toFIG. 2C, a synapse system of a neuromorphic device may include a row line15extending in a row direction, a column line25extending in a column direction, a synapse30, a row gating line50R extending in the row direction, and a column gating line50C extending in the column direction. The row gating line50R and the column gating line50C are disposed between the row line15and the column line25. The row gating line50R may be disposed above the column gating line50C. In other words, the row line15extending in the row direction, the column gating line50C extending in the column direction, the row gating line50R extending in the row direction, and the column line25extending in the column direction may be sequentially stacked. The synapse30may pass through the row gating line50R and the column gating line50C between the row line15and the column line25, and thus the row gating line50R and the column gating line50C may surround a side surface, i.e., a sidewall, of the synapse30.

Referring toFIG. 2D, a synapse system of a neuromorphic device may include a row line15extending in a row direction, a column line25extending in a column direction, a synapse30, a row gating line50R extending in the row direction, and a column gating line50C extending in the column direction. The row gating line50R and the column gating line50C may be electrically coupled to each other and disposed at the same level. In an embodiment, the row gating line50R and the column gating line50C may be formed using the same layer.

FIG. 3Ais a perspective view illustrating a synapse system of a neuromorphic device in accordance with an embodiment, andFIG. 3Bis a cross-sectional view taken along line I-I′ ofFIG. 3A.

Referring toFIGS. 3A and 3B, the synapse system includes a row line15, first and second gating lines51aand51bthat are disposed above the row line15, a column line25disposed above the first and second gating lines51aand51b, and a synapse30that is disposed between the row line15and the column line25and that passes through the first and second gating lines51aand51b. The first and second gating lines51aand51bmay surround a side surface, i.e., a sidewall, of the synapse30.

Referring toFIG. 3B, the synapse30may include a core31and a tunnel layer32surrounding the core31; the core31may have a pillar shape, the tunnel layer32may have a cylinder shape. That is, the tunnel layer32may surround an outer surface of the core31. The first and second gating lines51aand51bmay be arranged to be parallel to the row line15, or the column line25, or both. InFIGS. 3A and 3B, the first and second gating lines51aand51bextend in the same direction, but embodiments are not limited thereto. In another embodiment, the first gating line51amay cross the second gating line51b. Therefore, the first and second gating lines51aand51bmay include any one of, or may be both of, the row gating line50R and the column gating line50C ofFIGS. 2A to 2D. Positions of the first gating line51aand the second gating line51bmay be changed with each other. The first and second gating lines51aand51bmay have a first thickness T1and a second thickness T2, respectively, that are different from each other. For example, the second thickness T2may be equal to an integer times the first thickness T1. In an embodiment, the second thickness T2is two times the first thickness T1.

Each of the row line15and the column line25may include one or more of tungsten (W), tungsten nitride (WN), copper (Cu), titanium nitride (TiN), an inoxidizable metal, and an inoxidizable metal compound.

The first and second gating lines51aand51bmay include a metal capable of being partially oxidized by being coupled with oxygen ions. The metal may include any of aluminum (Al), titanium (Ti), hafnium (Hf), zirconium (Zr), lanthanum (La), niobium (Nb), yttrium (Y), strontium (Sr), and another oxidizable metal.

The core31of the synapse30may include a metal oxide layer, which includes movable oxygen ions. For example, the core31may include a perovskite-based material (such as PrxCayMnO3or PCMO) (x and y are positive numbers and, for example, x+y=1). The tunnel layer32may include at least one of a silicon oxide, a silicon nitride, or another dielectric material.

FIGS. 3C to 3Eare views illustrating an operation of the synapse system of the neuromorphic device shown inFIG. 3B. For example, in the synapse system of the neuromorphic device shown inFIG. 3B, a 0 (zero) or positive (+) voltage may be applied selectively to the first and second gating lines51aand51b. As mentioned above, the first and second gating lines51aand51bmay collectively be any one or both of the row gating line50R and the column gating line50C shown inFIGS. 2A to 2D. Namely, both the first and second gating lines51aand51bmay collectively be either the row gating line50R or the column gating line50C, or the first and second gating lines51aand51bmay respectively be the row gating line50R and the column gating line50C, or may respectively be the column gating line50C and the row gating line50R.

Referring toFIG. 3C, when a positive (+) voltage is applied to the first gating line51aand no voltage, e.g., a zero voltage, is applied to the second gating line51b, a portion of the first gating line51amay be converted into a first oxidized layer55a, and a first channel56amay be formed in the core31of the synapse30. For example, when the positive (+) voltage is applied to the first gating line51a, oxygen ions (O−) included in the core31of the synapse30may move to the first gating line51athrough the tunnel layer32. Accordingly, the first oxidized layer55amay be formed in the portion of the first gating line51athat is adjacent to the tunnel layer32. The first oxidized layer55amay have a hollow cylinder shape that serves as a rim surrounding the outer surface of the synapse30. The first channel56amay be formed at a central portion of the core31. The first channel56amay be formed due to an oxygen ion deficiency phenomenon occurring when the oxygen ions (O−) in the core31pass through the tunnel layer32and move to the first gating line51aby an electric field induced by the first gating line51athat surrounds the core31. That is to say, the electrical conductivity of the first channel56amay be changed when the first oxidized layer55ais formed since the first channel56ais deficient in oxygen ions (O−). For example, when the core31includes an N-type material and the positive (+) voltage is applied to the first gating line51a, an electrical resistance value of the first channel56amay decrease, and thus the electrical conductivity of the first channel56amay increase. Conversely, when the core31includes a P-type material and the positive (+) voltage is applied to the first gating line51a, the electrical resistance value of the first channel56amay increase, and thus the electrical conductivity of the first channel56amay decrease.

In the following descriptions, it is assumed that the core31includes the N-type material. The first channel56amay have a vertical length L1corresponding to the vertical thickness T1of the first gating line51a. A horizontal width of the first channel56amay be changed depending on the magnitude of the voltage applied to the first gating line51a. Due to the first channel56aformed in the core31, the electrical resistance value of the core31of the synapse30may decrease.

Referring toFIG. 3D, when a positive (+) voltage is applied to the second gating line51band no substantial voltage, e.g., a zero voltage, is applied to the first gating line51a, a portion of the second gating line51bmay be converted into a second oxidized layer55b, and a second channel56bmay be formed in the core31of the synapse30. The second channel56bmay have a vertical length L2corresponding to the vertical thickness T2of the second gating line51b. When referring back toFIGS. 3A and 3B, since the vertical thickness T2of the second gating line51bis two times the vertical thickness T1of the first gating line51a, the vertical length L2of the second channel56bmay be two times the vertical length L1of the first channel56a. Accordingly, as the second channel56bis formed in the core31, the electrical resistance value of the core31of the synapse30may further decrease compared to when the first channel56ais disposed in the core31.

Referring toFIG. 3E, when a positive (+) voltage is applied to both the first and second gating lines51aand51b, portions of the first and second gating lines51aand51bmay be respectively converted into first and second oxidized layers55aand55b, and first and second channels56aand56bmay be formed in the core31of the synapse30. Accordingly, the electrical resistance value of the core31of the synapse30may additionally decrease compared to when one of the first and second channels56aand56bis disposed in the core31.

Referring toFIGS. 3B to 3E, the core31may have four resistance states. In other words, the lengths of the first and second channels56aand56bformed in the core31may form four combinations of 0 (zero), L1, L2, and L3(wherein L3=L+L2). Therefore, the synapse30in accordance with the embodiment of the present disclosure may have multi-bit storage capability according to the four resistance states. As summarized in the following Table 1, when a positive (+) voltage is applied selectively to the first and second gating lines51aand51b, the first and second channels56aand56bare selectively formed in the core, and thus the core31may have four resistance levels Level 0 to Level 3.

In the synapse system described above with reference toFIGS. 3C to 3E, the first and second oxidized layers55aand55bmay be reduced or may disappear by applying a negative (−) voltage to the first and second gating lines51aand51b. For example, when the negative (−) voltage is applied to the first and second gating lines51aand51b, oxygen ions in the oxidized layers55aand55bmay move to the core31of the synapse30. Thus, the synapse30may be reset.

FIGS. 3F and 3Gare views illustrating a structure and an operation of a synapse system of a neuromorphic device in accordance with an embodiment of the present disclosure.

In addition to the structures of the synapse system shown inFIG. 3B, the synapse system shown inFIG. 3Fmay further include first and second absorption layers52aand52b. The first absorption layer52amay be formed between the first gating line51aand the synapse30, and the second absorption layer52bmay be formed between the second gating line51band the synapse30. That is, each of the first and second absorption layers52aand52bmay have a hollow cylinder shape, and may serve as a rim that surrounds the outer surface of the synapse30. The first and second absorption layers52aand52bmay absorb oxygen ions that move from the core31of the synapse30. In other words, the first and second absorption layers52aand52bmay be easily oxidized. For example, each of the first and second absorption layers52aand52bmay include one or more of aluminum (Al), titanium (Ti), hafnium (Hf), zirconium (Zr), lanthanum (La), niobium (Nb), yttrium (Y), strontium (Sr), and another oxidizable metal. Each of the first and second gating lines51aand51bmay include one or more of gold (Au), platinum (Pt), silver (Ag), nickel (Ni), tin (Sn), chrome (Cr), titanium nitride (TiN), tungsten nitride (WN), a conductive metal nitride, and an oxidization-resistant conductive material, which are not easily oxidized.

Referring toFIG. 3G, when a positive (+) voltage is applied to the first and second gating lines51aand51b, oxygen ions in the core31of the synapse30may move to the first and second absorption layers52aand52bthrough the tunnel layer32. Accordingly, the first and second absorption layers52aand52bmay be converted into first and second oxidized layers55aand55b, respectively. First and second channels56aand56bmay be formed in the core31of the synapse30. When referring additionally toFIGS. 3C and 3Dand Table 1, the core31of the synapse30in accordance with this embodiment may also have four resistance states, similar to those of the embodiment shown inFIG. 3B, according to selective voltage applications to the first and second gating lines51aand51b.

FIGS. 3H and 3Iare views illustrating a structure and an operation of a synapse system of a neuromorphic device in accordance with an embodiment of the present disclosure. In addition to the structure of the synapse system shown inFIG. 3F, the synapse system of the neuromorphic device shown inFIG. 3Hmay further include a first barrier layer53aformed between the first gating line51aand the first absorption layer52a, and a second barrier layer53bformed between the second gating line51band the second absorption layer52b. The first and second barrier layers53aand53bmay have hollow cylinder shapes that surround outer surfaces of the first and second absorption layers52aand52b, respectively. The first and second barrier layers53aand53bmay block oxygen ions, which have moved from the core31of the synapse30, from diffusing or moving to the first and second gating lines51aand51b, respectively. Therefore, the oxygen ions moved from the core31of the synapse30may only oxidize the first and second absorption layers52aand52bwithout oxidizing the first and second gating lines51aand51b. Each of the first and second barrier layers53aand53bmay include one or more of gold (Au), platinum (Pt), silver (Ag), nickel (Ni), tin (Sn), chrome (Cr), titanium nitride (TiN), tungsten nitride (WN), a metal nitride, and an oxidization-resistant conductive material.

Referring toFIG. 3I, when a positive (+) voltage is applied to the first and second gating lines51aand51b, oxygen ions in the core31of the synapse30may move to the first and second absorption layers52aand52bthrough the tunnel layer32. Accordingly, the first and second absorption layers52aand52bmay be converted into first and second oxidized layers55aand55b, respectively. First and second channels56aand56bmay be formed in the core31of the synapse30. Because the oxygen ions are prevented from diffusing or moving to the first and second gating lines51aand51bby the first and second barrier layers53aand53b, the first and second gating lines51aand51bmay not be oxidized. When referring additionally toFIGS. 3C and 3Dand Table 1, the core31of the synapse30in accordance with this embodiment may also have four resistance states, similar to those of the embodiment shown inFIG. 3B, according to selective voltage applications to the first and second gating lines51aand51b.

FIG. 4Ais a perspective view illustrating a synapse system of a neuromorphic device in accordance with an embodiment of the present disclosure, andFIG. 4Bis a cross-sectional view taken along line II-II′ ofFIG. 4A.

Referring toFIGS. 4A and 4B, the synapse system of the neuromorphic device may include a row line15, a column line25, first to third gating lines51ato51cdisposed between the row line15and the column line25, and a synapse30that passes through the first to third gating lines51ato51c.

The first to third gating lines51ato51cmay have different thicknesses T1, T2, and T3, respectively. For example, the second and third thicknesses T2and T3may be equal to an integer times the first thickness T1. In an embodiment, the second thickness T2is equal to two times the first thickness T1, and the third thickness T3is equal to three times the first thickness T1. Positions of the first to third gating lines51ato51cmay be changed with one another in accordance with various embodiments.

FIG. 4Cis a view illustrating an operation of the synapse system of the neuromorphic device shown inFIGS. 4A and 4B. Referring toFIG. 4C, when a positive (+) voltage is applied to the first to third gating lines51ato51c, first to third oxidized layers55ato55cmay be respectively formed in portions of the first to third gating lines51ato51cthat are adjacent to a tunnel layer32, and thus first to third channels56ato56cmay be formed in a core31. Vertical lengths L1to L3of the first to third channels56ato56cmay correspond to the vertical thicknesses T1to T3of the first to third gating lines51ato51c, respectively. For example, the first channel56amay have the first vertical length L1, the second channel56bmay have the second vertical length L2that is two times the first vertical length L1, and the third channel56cmay have the third vertical length L3that is three times the first vertical length L1.

In another embodiment of the present disclosure, a positive (+) voltage may be applied selectively to the first to third gating lines51ato51c. Thus, the first to third oxidized layers55ato55cand the first to third channels56ato56cmay be formed selectively. The first to third channels56ato56cmay be selectively formed to have a total vertical length corresponding to one of eight combinations of 0 (zero), L1, L2, L3, L1+L2, L1+L3, L2+L3, and L1+L2+L3. In this embodiment, since L3=L1+L2, the core31may have seven resistance levels. As summarized in the following Table 2, when the positive (+) voltage is applied selectively to the first to third gating lines51ato51c, the first to third channels56ato56care formed selectively, and thus the core31may have seven resistance levels Level 0 to Level 6.

FIGS. 4D and 4Eare views illustrating a structure and an operation of a synapse system of a neuromorphic device in accordance with an embodiment of the present disclosure. In addition to the structure of the synapse system shown inFIG. 4B, the synapse system of the neuromorphic device shown inFIG. 4Dmay further include first to third absorption layers52ato52c, which are respectively formed between the first to third gating lines51ato51cand the synapse30. The descriptions for this embodiment may be understood with reference toFIG. 3F.

Referring toFIG. 4E, when a positive (+) voltage is applied to the first to third gating lines51ato51c, oxygen ions in the core31of the synapse30may move to the first to third absorption layers52ato52cthrough the tunnel layer32. Accordingly, the first to third absorption layers52ato52cmay be converted into first to third oxidized layers55ato55c, respectively. Thus, first to third channels56ato56cmay be formed in the core31of the synapse30. Vertical lengths L1, L2, and L3of the first to third channels56ato56cmay correspond to the vertical thicknesses T1to T3of the first to third gating lines51ato51c, respectively. By referring additionally toFIGS. 3C and 3D, the positive (+) voltage may be applied selectively to the first to third gating lines51ato51c.

FIGS. 4F and 4Gare views illustrating a structure and an operation of a synapse system of a neuromorphic device in accordance with an embodiment of the present disclosure. In addition to the structure of the synapse system shown inFIG. 4D, the synapse system of the neuromorphic device shown inFIG. 4Fmay further include first to third barrier layers53ato53cthat are formed between the first to third gating lines51ato51cand the first to third absorption layers52ato52c. The first to third barrier layers53ato53cmay have hollow cylinder shapes that surround outer surfaces of the first to third absorption layers52ato52c, respectively. The first to third barrier layers53ato53cmay block oxygen ions, which have moved from the core31of the synapse30, from diffusing or moving to the first to third gating lines51ato51c. Each of the first to third barrier layers53ato53cmay include one or more of gold (Au), platinum (Pt), silver (Ag), nickel (Ni), tin (Sn), chrome (Cr), titanium nitride (TiN), tungsten nitride (WN), another metal nitride, and an oxidization-resistant conductive material.

Referring toFIG. 4G, when a positive (+) voltage is applied to the first to third gating lines51ato51c, oxygen ions in the core31of the synapse30may move to the first to third absorption layers52ato52cthrough the tunnel layer32. Accordingly, the first to third absorption layers52ato52cmay be converted into first to third oxidized layers55ato55c, respectively. First to third channels56ato56cmay be formed in the core31of the synapse30. Because the oxygen ions are prevented from diffusing or moving to the first to third gating lines51ato51cby the first to third barrier layers53ato53c, the first to third gating lines51ato51cmay not be oxidized. The positive (+) voltage may be applied selectively to the first to third gating lines51ato51c.

In another embodiment of the present disclosure, the second thickness T2may be equal to two times the first thickness T1, and the third thickness T3may be equal to four times the first thickness T1. Therefore, the third vertical length L3of the third channel56cmay be equal to four times the first vertical length L1of the first channel56a. As summarized in the following Table 3, when the positive (+) voltage is applied selectively to the first to third gating lines51ato51c, the first to third channels56ato56care formed selectively, and thus the core31may have eight resistance levels Level 0 to Level 7.

FIG. 5Ais a perspective view illustrating a synapse system of a neuromorphic device in accordance with an embodiment of the present disclosure, andFIGS. 5B to 5Dare cross-sectional views taken along line III-III′ ofFIG. 5A.

Referring toFIGS. 5A and 5B, a synapse system of a neuromorphic device may include a row line15, a column line25, first to fourth gating lines51ato51ddisposed between the row line15and the column line25, and a synapse30that passes through the first to fourth gating lines51ato51d. The first to fourth gating lines51ato51dmay have different thicknesses T1, T2, T3, and T4, respectively. In an embodiment, the second thickness T2is equal to two times the first thickness T1, the third thickness T3is equal to three times the first thickness T1, and the fourth thickness T4is equal to four times the first thickness T1. Positions of the first to fourth gating lines51ato51dmay be changed with one another in accordance with various embodiments.

In addition to the structure of the synapse system of the neuromorphic device described above with reference toFIG. 5B, a synapse system of a neuromorphic device ofFIG. 5Cmay further include first to fourth absorption layers52ato52d, which are respectively formed between the first to fourth gating lines51ato51dand the synapse30.

In addition to the structure of the synapse system shown inFIG. 5C, a synapse system of a neuromorphic device shown inFIG. 5Dmay further include first to fourth barrier layers53ato53dwhich are formed between the first to fourth gating lines51ato51dand the first to fourth absorption layers52ato52d, respectively.

When a positive (+) voltage is applied selectively to the first to fourth gating lines51ato51d, the first to fourth absorption layers52ato52dmay be converted selectively to first to fourth oxidized layers (not shown), and first to fourth channels (not shown), which have vertical lengths corresponding to the thicknesses T1, T2, T3, and T4of the first to fourth gating lines51ato51d, may be formed selectively. The oxidized layers and the channels are not illustrated inFIGS. 5C and 5D, but they may be understood from the above other embodiments.

It is summarized in the following Table 4 that, when the positive (+) voltage is applied selectively to the first to fourth gating lines51ato51d, the first to fourth channels are formed selectively, and thus the core31may have11resistance levels Level 0 to Level 10.

According to the present disclosure, the number of gating lines (51x) may be further increased, and/or vertical thicknesses (Tx) of the gating lines (51x) may be further diversified. Thus, vertical lengths (Lx) of channels (56x) may be further diversified as well. As a result, the resistance levels of the core31may also be diversified.

FIG. 6Ais a diagram conceptually illustrating a variable resistance system in accordance with an embodiment of the present disclosure. Referring toFIG. 6A, the variable resistance system may include a buffer layer105on a substrate100, a variable resistance layer131, a tunnel layer132, a first bit line structure115, a second bit line structure125, gating lines151ato151d, and an interlayer dielectric layer106. The first bit line structure115may include a first bit line wire115aand a first bit line plug115b, and the second bit line structure125may include a second bit line wire125aand a second bit line plug125b.

The substrate100may include a silicon wafer, or a metal, glass, ceramic, or plastic substrate. The buffer layer105may isolate the substrate100and the variable resistance layer131physically and electrically. For example, the buffer layer105may block ion movement between the substrate100and the variable resistance layer131. The buffer layer105may include a dielectric material such as a silicon nitride. The variable resistance layer131may include a perovskite-based material (such as PrxCayMnO3or PCMO, wherein x and y are positive numbers and, for example, x+y=1). The tunnel layer132may include a silicon oxide, a silicon nitride, or another dielectric material. Each of the first bit line structure115and the second bit line structure125may include one or more of tungsten (W), tungsten nitride (WN), copper (Cu), titanium nitride (TiN), an inoxidizable metal, and an inoxidizable metal compound. Each of the gating lines151ato151dmay include one of metals capable of being partially oxidized by being coupled with oxygen ions. For example, the metals include aluminum (Al), titanium (Ti), hafnium (Hf), zirconium (Zr), lanthanum (La), niobium (Nb), yttrium (Y), strontium (Sr), and another oxidizable metal. The interlayer dielectric layer106may include any one of a silicon oxide, a silicon nitride, a dielectric organic, and a combination thereof.

The gating lines151ato151dmay have different horizontal widths with respect to the orientation ofFIG. 6A. For example, the first gating line151amay have a first horizontal width W1, the second gating line151bmay have a second horizontal width W2, the third gating line151cmay have a third horizontal width W3, and the fourth gating line151dmay have a fourth horizontal width W4.

FIG. 6Bis a diagram illustrating an operation of the variable resistance system shown inFIG. 6A. Referring toFIG. 6B, when a positive (+) voltage is applied to the first to fourth gating lines151ato151d, portions of the first to fourth gating lines151ato151dthat are adjacent to the tunnel layer132may be converted into first to fourth oxidized layers155ato155d, respectively, and first to fourth channels156ato156dmay be formed in the variable resistance layer131. The first to fourth oxidized layers155ato155dmay be formed when oxygen ions in the variable resistance layer131move to the first to fourth gating lines151ato151dthrough the tunnel layer132. Accordingly, as the variable resistance layer131becomes deficient in oxygen ions, the first to fourth channels156ato156dmay be formed. The first to fourth oxidized layers155ato155dmay be adjacent to the tunnel layer132, and the first to fourth channels156ato156dmay be adjacent to the buffer layer105.

FIG. 6Cis a diagram conceptually illustrating a variable resistance system in accordance with an embodiment of the present disclosure. In addition to the structure of the variable resistance system shown inFIG. 6A, the variable resistance system shown inFIG. 6Cmay further include first to fourth absorption layers152ato152d, which are formed between the first to fourth gating lines151ato151dand the tunnel layer132. The first to fourth absorption layers152ato152dmay absorb oxygen ions which moved from the variable resistance layer131through the tunnel layer132. That is to say, the first to fourth absorption layers152ato152dmay be easily oxidized. For example, each of the first to fourth absorption layers152ato152dmay include one or more of aluminum (Al), titanium (Ti), hafnium (Hf), zirconium (Zr), lanthanum (La), niobium (Nb), yttrium (Y), strontium (Sr), and another oxidizable metal. The first to fourth gating lines151ato151dmay include one or more of gold (Au), platinum (Pt), silver (Ag), nickel (Ni), tin (Sn), chrome (Cr), titanium nitride (TiN), tungsten nitride (WN), a conductive metal nitride, and an oxidization-resistant conductive material, which are not easily oxidized.

FIG. 6Dis a diagram conceptually illustrating a variable resistance system in accordance with an embodiment of the present disclosure. In addition to the structure of the variable resistance system shown inFIG. 6C, the variable resistance system shown inFIG. 6Dmay further include first to fourth barrier layers153ato153d, which are respectively formed between the first to fourth gating lines151ato151dand the first to fourth absorption layers152ato152d. Each of the first to fourth barrier layers153ato153dmay include one or more of gold (Au), platinum (Pt), silver (Ag), nickel (Ni), tin (Sn), chrome (Cr), titanium nitride (TiN), tungsten nitride (WN), another metal nitride, and an oxidation-resistant conductive material.

FIG. 6Eis a diagram illustrating an operation of the variable resistance system shown inFIG. 6D. Referring toFIG. 6E, when a positive (+) voltage is applied to the first to fourth gating lines151ato151d, the first to fourth absorption layers152ato152dmay be converted into first to fourth oxidized layers155ato155d, respectively, and first to fourth channels156ato156dmay be formed in the variable resistance layer131. The first to fourth barrier layers153ato153dmay block oxygen ions in the variable resistance layer131from moving to the first to fourth gating lines151ato151d, respectively.

FIG. 7is a block diagram conceptually illustrating a pattern recognition system900in accordance with an embodiment. For example, the pattern recognition system900may include one of a speech recognition system, an image recognition system, a code recognition system, a signal recognition system, and a system for recognizing various patterns.

Referring toFIG. 7, the pattern recognition system900in accordance with the embodiment may include a central processing unit (CPU)910, a memory unit920, a communication control unit930, a network940, an output unit950, an input unit960, an analog-digital converter (ADC)970, a neuromorphic unit980, and a bus990. The CPU910may generate and transmit various signals for a learning process to be performed by the neuromorphic unit980, and perform a variety of processes and functions for recognizing patterns such as voice and images according to an output of the neuromorphic unit980.

The CPU910may be connected to the memory unit920, the communication control unit930, the output unit950, the ADC970, and the neuromorphic unit980through the bus990.

The memory unit920may store information in accordance with operations of the pattern recognition system900. The memory unit920may include one or more of a volatile memory device such as DRAM or SRAM, a nonvolatile memory device such as PRAM, MRAM, ReRAM, or NAND flash memory, and a memory unit such as a HDD (Hard Disk Drive) or a SSD (Solid State Drive).

The communication control unit930may transmit and/or receive data such as a recognized voice and image to and/or from a communication control unit of another system through the network940.

The output unit950may output the data such as the recognized voice and image using various methods. For example, the output unit950may include one or more of a speaker, a printer, a monitor, a display panel, a beam projector, a hologrammer, and so on.

The input unit960may include one or more of a microphone, a camera, a scanner, a touch pad, a keyboard, a mouse, a mouse pen, a sensor, and so on.

The ADC970may convert analog data transmitted from the input unit960into digital data.

The neuromorphic unit980may perform learning and recognition using the data transmitted from the ADC970, and output data corresponding to a recognized pattern. The neuromorphic unit980may include one or more of the neuromorphic devices in accordance with the various embodiments.

According to the embodiments of the present disclosure, a synapse system may have multiple resistance levels. Accordingly, a learning level of a synapse of a neuromorphic device may be subdivided.