SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE

A semiconductor element includes an element body including an obverse surface facing one side in a thickness direction, a wiring layer on the obverse surface electrically connected to the element body, and an obverse-surface electrode formed on and electrically connected to the wiring layer. An outer edge of the obverse-surface electrode includes a corner portion as viewed in the thickness direction. The wiring layer includes a first edge extending along the outer edge of the obverse-surface electrode as viewed in the thickness direction, and a second edge connected to the first edge and facing the corner portion as viewed in the thickness direction. The second edge includes a portion defining, as viewed in the thickness direction, a distance from the second edge to the outer edge of the obverse-surface electrode, wherein the distance is greater than a distance from the first edge to the outer edge of the obverse-surface electrode.

TECHNICAL FIELD

The present disclosure relates to a semiconductor element and a semiconductor device.

BACKGROUND ART

Conventionally, semiconductor elements having switching functions have been used for current control in various industrial apparatuses and vehicles. Such a semiconductor element is configured with a switching circuit such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). For example, JP-A-2020-5323 discloses an example of a semiconductor device including a semiconductor element (MOSFET).

DETAILED DESCRIPTION OF EMBODIMENTS

The following describes a preferred embodiment of a semiconductor element and a semiconductor device according to the present disclosure with reference to the drawings. In the following, the same or similar constituent elements are denoted by the same reference numerals, and the descriptions thereof are omitted. The terms such as “first”, “second” and “third” in the present disclosure are used merely as labels and are not necessarily intended to impose orders on the items to which these terms refer.

In the present disclosure, the phrases “an object A is formed in an object B” and “an object A is formed on an object B” include, unless otherwise specified, “an object A is formed directly in/on an object B” and “an object A is formed in/on an object B with another object interposed between the object A and the object B”. Similarly, the phrases “an object A is disposed in an object B” and “an object A is disposed on an object B” include, unless otherwise specified, “an object A is disposed directly in/on an object B” and “an object A is disposed in/on an object B with another object interposed between the object A and the object B”. Similarly, the phrase “an object A is located on an object B” includes, unless otherwise specified, “an object A is located on an object B in contact with the object B” and “an object A is located on an object B with another object interposed between the object A and the object B”. Furthermore, the phrase “an object A overlaps with an object B as viewed in a certain direction” includes, unless otherwise specified, “an object A overlaps with the entirety of an object B” and “an object A overlaps with a portion of an object B”. Furthermore, the phrase “an object A (or the constituent material thereof) contains a material C” includes “an object A (or the constituent material thereof) is made of a material C” and “an object A (or the constituent material thereof) is mainly composed of a material C”.

FIGS.1to14show a semiconductor element A1according to an embodiment, and a semiconductor device B1including the semiconductor element A1. As shown in these figures, the semiconductor device B1includes, in addition to the semiconductor element A1, a first lead51, a plurality of second leads52, a plurality of first connecting members61, a plurality of second connecting members62, a plurality of third connecting members63, and a sealing resin7.

The semiconductor device B1is an intelligent power device (IPD), for example. As can be understood from the configuration described in detail below, the semiconductor device B1is configured by modularizing the semiconductor element A1, and the semiconductor element A1is configured by integrating a power chip, such as a MOSFET or an IGBT, and a control circuit that controls the power chip onto one chip. The shape and size of the semiconductor device B1is not particularly limited. For example, the semiconductor device B1has a dimension of 4 mm to 7 mm in a first direction x, a dimension of 4 mm to 8 mm in a second direction y, and a dimension of 0.7 mm to 2.0 mm in a thickness direction z.

For convenience of description, the thickness direction of the semiconductor device B1is referred to as the “thickness direction z”. In the following description, one side in the thickness direction z may be referred to as “upward”, and the other side as “downward”. The terms such as “top”, “bottom”, “upward”, “downward”, “upper surface”, and “lower surface” are used to indicate the relative positions of elements and the like in the thickness direction z, and do not necessarily define the relationship with respect to the direction of gravity. Furthermore, “plan view” refers to the view seen in the thickness direction z. A direction perpendicular to the thickness direction z is referred to as the “first direction x”. For example, the first direction x is the horizontal direction in a plan view (seeFIG.2) of the semiconductor device B1. The direction perpendicular to the thickness direction z and the first direction x is referred to as the “second direction y”. The second direction y is the vertical direction in a plan view (seeFIG.2) of the semiconductor device B1.

The semiconductor element A1exerts the electrical function of the semiconductor device B1. As shown inFIGS.2,6, and7, the semiconductor element A1is mounted on the first lead51. The semiconductor element A1includes an element body10, an interlayer insulating layer13, a wiring layer14, an insulating film17, an obverse-surface electrode21, a reverse-surface electrode24, a plurality of pad portions25, and a surface protection film26.

The element body10is a main component of the IPD, for example. As shown inFIGS.2,8,10, and12, the element body10includes a switching circuit30and a control circuit40, for example. The switching circuit30is a MOSFET or an IGBT, for example. The present embodiment is described with an example where the switching circuit30is an n-channel MOSFET having a vertical structure. However, the switching circuit30may be a p-channel MOSFET or may have a horizontal structure instead of a vertical structure. Furthermore, the switching circuit30may be an IGBT instead of a MOSFET, or may be another transistor. The control circuit40controls the switching circuit30. For example, the control circuit40includes functional elements such as a gate drive circuit, a protection circuit, and an active clamp circuit. The gate drive circuit generates a gate signal that controls the drive of the switching circuit30, based on a control signal inputted from the outside. The protection circuit protects the switching circuit30from overcurrent and overheating by detecting, for example, the current flowing through the switching circuit30and the temperature of the switching circuit30. The active clamp circuit absorbs the energy of an inductive load. The functional elements of the control circuit40are not limited to the examples given above. The element body10may omit the control circuit40and may be configured with only the switching circuit30. The occupancy of each of the switching circuit30and the control circuit40relative to the element body10in plan view is not particularly limited. In the example shown inFIGS.2and8, the occupancy of the switching circuit30is larger than that of the control circuit40.

As shown inFIGS.2and8, the element body10has a rectangular shape in plan view. As shown inFIG.12, the element body10has an obverse surface10aand a reverse surface10b. The obverse surface10afaces one side in the thickness direction z. The reverse surface10bfaces the opposite side from the obverse surface10a. As shown inFIGS.12and13, the element body10includes a semiconductor substrate11and a semiconductor layer12.

The semiconductor substrate11supports the semiconductor layer12. The semiconductor substrate11is an n+ semiconductor layer. The semiconductor substrate11contains silicon (Si) or silicon carbide (SiC). The semiconductor substrate11has a surface (e.g., the lower surface inFIG.12) facing away from the semiconductor layer12in the thickness direction z, and this surface corresponds to the reverse surface10bof the element body10.

The semiconductor layer12is formed on the semiconductor substrate11. As shown inFIG.12, the switching circuit30and the control circuit40are configured in the semiconductor layer12. The semiconductor layer12is electrically connected to the semiconductor substrate11. The boundary surface between the semiconductor layer12and each of the interlayer insulating layer13and the wiring layer14is the obverse surface10aof the element body10. The semiconductor layer12includes an epitaxial layer121. The epitaxial layer121occupies a large portion of the semiconductor layer12. The epitaxial layer121is an n− semiconductor. The epitaxial layer121is formed on the semiconductor substrate11.

As shown inFIGS.13and14, the switching circuit30configured in the semiconductor layer12includes a plurality of trench gate structures31, a gate insulating film32, a plurality of body regions33, a plurality of source regions34, a plurality of body contact regions35, and a DTI structure36. Out of these elements, the body regions33, the source regions34, and the body contact regions35are semiconductors different from the epitaxial layer121, and are configured by replacing the surface portion of the epitaxial layer121. The semiconductor layer12includes the trench gate structures31, the gate insulating film32, the body regions33, the source regions34, the body contact regions35, and the DTI structure36, in addition to the epitaxial layer121. The epitaxial layer121and the semiconductor substrate11constitute the drain region of the switching circuit30.

As shown inFIGS.13and14, the trench gate structures31extend from the boundary surface between each of the body regions33and each of the source regions34and the body contact regions35in the thickness direction z toward the semiconductor substrate11. The trench gate structures31are arranged at equal intervals in the first direction x and extend in the second direction y. As shown inFIGS.13and14, each of the trench gate structures31has a first trench311, a gate electrode312, and an embedded electrode313.

The first trench311forms a groove dug from the boundary surface between each of the body regions33and each of the source regions34and the body contact regions35in the thickness direction z toward the semiconductor substrate11. The gate electrode312and the embedded electrode313are spaced apart from each other in the thickness direction z and housed in the first trench311. The embedded electrode313is located closer to the semiconductor substrate11than is the gate electrode312in the thickness direction z. The gate electrode312and the embedded electrode313are polycrystalline polysilicon, for example. The gate electrode312and the embedded electrode313extend in the second direction y.

Each of the first trenches311has the gate insulating film32embedded therein. The gate electrode312and the embedded electrode313are covered with the gate insulating film32. The gate insulating film32is silicon oxide (SiO2), for example. The gate insulating film32electrically insulates the gate electrode312and the embedded electrode313from each other. The gate insulating film32also electrically insulates the gate electrode312and the embedded electrode313from the outside of the trench gate structure31.

The body regions33are formed on the epitaxial layer121. The body regions33are p− semiconductors. The body regions33extend in the second direction y. Each of the body regions33, except for those located at both ends in the first direction x, is sandwiched by two of the trench gate structures31that are adjacent to each other in the first direction x. The body regions33each sandwiched by two adjacent trench gate structures31in the first direction x include a body region33that is in contact with the gate insulating film32embedded in each of the two trench gate structures31.

As shown inFIGS.13and14, the source regions34and the body contact regions35are formed on the body regions33. The source regions34are n+ semiconductors. The body contact regions35are p+ semiconductors. In each of the trench gate structures31in a cross section perpendicular to the second direction y, one of the source regions34adjoins one side of the trench gate structure31in the first direction x, and one of the body contact regions35adjoins the other side of the trench gate structure31in the first direction x. As shown inFIG.11, in the region sandwiched by two adjacent trench gate structures31of the plurality of trench gate structures31in plan view, the source regions34and the body contact regions35are in contact with each other in the first direction x and arranged alternately in the second direction y. Accordingly, the source regions34and the body contact regions35form a checkered pattern in the region (seeFIG.11). The source regions34and the body contact regions35are covered with the gate insulating film32. The body contact regions35can be replaced with the body regions33that are p-type semiconductors.

As shown inFIG.13, the DTI structure36(DTI: Deep Trench Isolation) extends from the boundary surface between the epitaxial layer121and the interlayer insulating layer13in the thickness direction z toward the semiconductor substrate11. The bottom of the DTI structure36is positioned closer to the semiconductor substrate11than the bottom of each trench gate structure31. The DTI structure36has a frame shape surrounding the trench gate structures31in plan view. Thus, as shown inFIG.10, the switching circuit30is partitioned from the control circuit40by the DTI structure36. In the illustrated example, the switching circuit30is partitioned into two regions by two DTI structures36. However, the switching circuit30may be partitioned into three or more regions by three or more DTI structures36, or may be grouped as a single region and partitioned from the control circuit40by a single DTI structure36. The semiconductor element A1is described with an example where the DTI structure36is used as a means to partition the switching circuit30. However, it is possible to use a p-type diffusion region, which is formed by replacing a portion of the epitaxial layer121, as another such means. As shown inFIG.13, the DTI structure36has a second trench361and an insulator362.

The second trench361forms a groove dug from the boundary surface between the epitaxial layer121and the interlayer insulating layer13in the thickness direction z toward the semiconductor substrate11. The insulator362is accommodated in the second trench361. The insulator362may be polycrystalline polysilicon or silicon oxide. The second trench361has the gate insulating film32embedded therein. The insulator362is covered with the gate insulating film32.

The interlayer insulating layer13is stacked on the semiconductor layer12and formed on the obverse surface10a. The interlayer insulating layer13contains at least one of silicon oxide and silicon nitride (Si3N4). The interlayer insulating layer13is formed by plasma chemical vapor deposition (CVD), for example.

As shown inFIG.13, the interlayer insulating layer13has a first film131, a second film132, a third film133, and a fourth film134. The first film131is stacked on the gate insulating film32. As shown inFIGS.13and14, the trench gate structures31are formed with a plurality of dents each resulting from a step between a gate electrode312and a group of source regions34and body contact regions35in the thickness direction z. The first film131enters each of the dents. The second film132is stacked on the first film131. The third film133is stacked on the second film132. The fourth film134is stacked on the third film133. As shown inFIG.13, the fourth film134is formed with a plurality of openings135passing through in the thickness direction z. A portion of the wiring layer14is exposed from each of the openings135. The openings135are connected to a plurality of openings171(described below) in the insulating film17. The position and size of each opening135corresponds to the position and size of each opening171in the insulating film17.

The wiring layer14is stacked on the semiconductor layer12and formed on the obverse surface10a. The wiring layer14contains aluminum (Al), for example. The wiring layer14may be made of an aluminum-copper (Cu) alloy (AlCu).

As shown inFIG.13, the wiring layer14includes a first layer141, a second layer142, a plurality of first vias143, and a plurality of second vias144. The first layer141and the second layer142are stacked and spaced apart from each other in the thickness direction z with the interlayer insulating layer13interposed therebetween. The first layer141is formed on the first film131and covered with the second film132. The second layer142is formed on the third film133. The periphery of the second layer142is covered with the fourth film134in plan view. The portions of the second layer142not covered with the fourth film134are exposed from the openings135in the fourth film134and openings171(described below) of the insulating film17, and the exposed portions are covered with an underlying layer23. The first vias143are embedded in the first film131, and pass through the first film131in the thickness direction z. The first vias143are connected to the first layer141, the source regions34, and the body contact regions35. The second vias144are embedded in the second film132and the third film133, and pass through the third film133and the second film132arranged on the first layer141in the thickness direction z. Each of the second vias144is connected to the first layer141and the second layer142. In the illustrated example, the wiring layer14is made up of two layers, namely the first layer141and the second layer142. However, the wiring layer14may be made up of a single layer or three or more layers. Each of the first layer141and the second layer142may have a thickness (i.e., the dimension in the thickness direction z) of 0.1 μm to 4.0 μm.

As shown inFIGS.8and9, an outer edge15of the wiring layer14in plan view has a plurality of first edges151and152and a plurality of second edges153and154. The outer edge15(the first edges151and152and the second edges153and154) is the periphery of each of the first layer141and the second layer142in the wiring layer14in plan view.

Each of the first edges151and152extends along an outer edge22(described below) of the obverse-surface electrode21in plan view. A pair of first edges151extend in the first direction x and are spaced apart from each other in the second direction y. A pair of first edges152extend in the second direction y and are spaced apart from each other in the first direction x.

Each of the second edges153and154is connected to one of the first edges151and152. Each of the second edges154extends in the first direction x, and each of the second edges153extends in the second direction y. In the example shown inFIGS.8and9, the second edges153and the second edges154are perpendicular to each other. Furthermore, the second edges153are perpendicular to the first edges151, and the second edges154are perpendicular to the first edges152. Unlike this example, the second edges153may be inclined to the first edges151, and the second edges154may be inclined to the first edges152.

As shown inFIGS.8and9, the wiring layer14has a plurality of cutouts161, a plurality of slits162, and an edge portion163.

The cutouts161are provided at four corners of the rectangular wiring layer14defined by the first edges151and152. Each of the cutouts161has an L shape in plan view, and has a pair of second edges153and154among the above-described second edges153and154. Each pair of second edges153and154is formed by a cutout161.

The edge portion163is a portion of the wiring layer14located between a portion of the obverse-surface electrode21(a plurality of penetrating portions212described below) and each of the first edges151and152in plan view. The edge portion163is arranged along the outer edge15.

The slits162are where the wiring layer14(at least the second layer142) is not formed. The slits162are arranged appropriately at the edge portion163. In the example shown inFIG.9, the slits162include those arranged along the first edges151, those arranged along the first edges152, and those arranged along the second edges153. In the example shown inFIG.9, the slits162are arranged in two rows along each of the first edges151and152. The number of rows of the slits162is changed appropriately according to a distance d163(seeFIG.9) between the outer edge22and openings171(penetrating portions212described below). Although the slits162are arranged to form a neatly aligned matrix pattern in the example shown inFIG.9, they may be arranged otherwise to form an irregularly deformed pattern. Each slit162has a strip shape in plan view in the illustrated example, but the plan-view shape of each slit162is not particularly limited. For example, the plan-view shape of each slit162may be a circle, a polygon, or an ellipse, instead of a strip. The plan-view dimensions of each slit162are not particularly limited. In the case where each slit162has a strip shape, the dimension thereof in the longitudinal direction is 0.5 μm to 10 μm (e.g., 4.8 μm), and the dimension thereof in the transverse direction is 0.5 μm to 10 μm (e.g., 1.2 μm). A distance d11(seeFIG.9) between any two of the slits162is 0.5 μm to 3.0 μm, for example. A distance d12(seeFIG.9) between any two of the rows of the slits162is 0.5 μm to 3.0 μm, for example. A distance d162(seeFIG.9) from the slits162arranged along each of the pairs of first edges151and152to each of the pairs of first edges151and152is 0.1 μm to 2.0 μm, for example.

The insulating film17is stacked on the interlayer insulating layer13. The insulating film17is electrically insulative, and may be a passivation film. The insulating film17may contain silicon nitride. Unlike this configuration, the insulating film17may be made up of a silicon oxide film formed on the interlayer insulating layer13and a silicon nitride film formed on the silicon oxide film. As shown inFIG.13, the insulating film17is formed with a plurality of openings171passing through in the thickness direction z. The openings171are spaced apart from each other in plan view. The openings171are connected to the respective openings135, and a portion of the wiring layer14is exposed from each of the openings171and the openings135. As shown inFIG.9, openings171near each of the four corners of the wiring layer14are arranged in an L shape in plan view.

The obverse-surface electrode21is formed on the wiring layer14. The obverse-surface electrode21is made of a metal material and may contain copper. The obverse-surface electrode21includes a first portion21A and a second portion21B. The first portion21A and the second portion21B are spaced apart from each other. The first portion21A overlaps with the switching circuit30in plan view, and is electrically connected to the switching circuit30via the underlying layer23and the wiring layer14. The second portion21B overlaps with the control circuit40, and is electrically connected to the control circuit40via the underlying layer23and the wiring layer14.

As shown inFIGS.12and13, the obverse-surface electrode21(each of the first portion21A and the second portion21B) includes a main portion211and a plurality of penetrating portions212.

The main portion211is formed on the insulating film17. The thickness (the dimension in the thickness direction z) of the main portion211may be, but not limited to, 100% to 2000% with respect to the thickness of each of the first layer141and the second layer142. In the example where the thickness of each of the first layer141and the second layer142is 0.1 μm to 4.0 μm, the thickness (the dimension in the thickness direction z) of the main portion211may be 4.0 μm to 20.0 μm.

The penetrating portions212are each connected to the main portion211. The penetrating portions212are integrally formed with the main portion211. The penetrating portions212fill the respective openings171. The penetrating portions212are embedded in the insulating film17and pass through the insulating film17in the thickness direction z. Each of the penetrating portions212is connected to a portion of the wiring layer14exposed from one of the openings171, via the underlying layer23. Each of the penetrating portions212electrically connects the main portion211and the wiring layer14.

As shown inFIG.8, the outer edge22of the obverse-surface electrode21(the first portion21A in the illustrated example) has an octagonal shape in plan view, for example. The plan-view shape of the outer edge22is not limited to an octagon. As shown inFIG.8, the outer edge22surrounds the outer edge15of the wiring layer14in plan view. The outer edge22corresponds to the periphery of the main portion211in plan view. As shown inFIGS.8and9, the outer edge22has a plurality of side ends221and222, and a plurality of corner portions223.

The side ends221and222are connected to each other via the corner portions223. A pair of side ends221extend in the first direction x and are spaced apart from each other in the second direction y. A pair of side ends222extend in the second direction y and are spaced apart from each other in the first direction x.

The corner portions223are arranged at four corners of the obverse-surface electrode21when the obverse-surface electrode21defined by the side ends221and222is seen as a rectangle in plan view. Each of the corner portions223is connected to one of the pair of side ends221and one of the pair of side ends222. Each corner portion223is linear in plan view and inclined to the two side ends221and222connected to the corner portion223.

As shown inFIGS.8and9, the semiconductor element A1is configured such that the outer edge15of the wiring layer14and the outer edge22of the obverse-surface electrode21have the following relationships.

First, the first edges151and the side ends221are substantially parallel to each other. For example, in plan view, a distance d151(seeFIG.9) between a first edge151to the outer edge22(a side end221), i.e., the interval between the first edge151and the side end221, in the vertical direction (the second direction y inFIG.9) of the first edge151, is 5.0 μm to 20 μm. Similarly, the first edges152and the side ends222are parallel (or substantially parallel) to each other. For example, in plan view, a distance d152(seeFIG.9) between a first edge152to the outer edge22(a side end222), i.e., the interval between the first edge152and the side end222, in the vertical direction (the first direction x inFIG.9) of the first edge152, is 5.0 μm to 20 μm. Although the distance d151and the distance d152are the same (or substantially the same) in the present embodiment, they may be different from each other.

Second, each of the second edges153includes a portion where a distance d153(seeFIG.9) from the second edge153to the outer edge22(a corner portion223) in the vertical direction (the first direction x in the example shown inFIG.9) of the second edge153is greater than the distance d151. In the example shown inFIG.9, the distance d153is greater than the distance d151at any position on the second edge153. Similarly, each of the second edges154includes a portion where a distance d154(seeFIG.9) from the second edge154to the outer edge22(a corner portion223) in the vertical direction (the second direction y in the example shown inFIG.9) of the second edge154is greater than the distance d152. In the example shown inFIG.9, the distance d154is greater than the distance d152at any position on the second edge154. In the following description, these relationships may be referred to as “second relationships”.

As shown inFIGS.12and13, the underlying layer23is arranged under the obverse-surface electrode21, and is in contact with the obverse-surface electrode21. The underlying layer23contains titanium (Ti), for example.

As shown inFIGS.6,7,12, and13, the reverse-surface electrode24is provided at the reverse surface10bof the element body10. The reverse-surface electrode24is provided over the entirety of the reverse surface10b. The reverse-surface electrode24is electrically connected to the semiconductor layer12(epitaxial layer121) via the semiconductor substrate11. The material and configuration of the reverse-surface electrode24are not particularly limited. For example, the reverse-surface electrode24may include a layer that is in contact with the semiconductor substrate11and contains silver (Ag), and a layer that is formed on the Ag layer and contains gold (Au). As shown inFIGS.6and7, the reverse-surface electrode24is bonded to the first lead51via a conductive bonding member29. The material of the conductive bonding member29may be, but not limited to, solder, silver paste, or sintered silver.

The pad portions25are formed on the main portion211of the obverse-surface electrode21. The pad portions25include those formed on the first portion21A and those formed on the second portion21B. The pad portions25are formed to facilitate bonding of the first connecting members61and the second connecting members62with respect to the obverse-surface electrode21. Unlike the illustrated example, the semiconductor element A1may not include any of the pad portions25, and the first connecting members61and the second connecting members62may be directly bonded to the obverse-surface electrode21. The configuration and material of the pad portions25are not particularly limited. For example, each of the pad portions25may include a nickel (Ni) layer, a palladium (Pd) layer, and a Au layer stacked in this order from the side that is in contact with the obverse-surface electrode21.

As shown inFIGS.12and13, the surface protection film26covers a surface of the insulating film17. The surface protection film26covers a side surface of the main portion211of the obverse-surface electrode21. The surface protection film26is electrically insulative. The surface protection film26contains polyimide, for example.

The first lead51and the second leads52are each made of a metal selected from a group including Cu, Ni, and iron (Fe) or an alloy thereof, for example. Appropriate portions of the first lead51and the second leads52may be plated with a metal selected from a group including Ag, Ni, Pd, and Au. The thickness of each of the first lead51and the second leads52is not particularly limited, and may be 0.12 mm to 0.2 mm.

The first lead51supports the semiconductor element A1. The first lead51is electrically connected to the reverse-surface electrode24of the semiconductor element A1via the conductive bonding member29. As shown inFIGS.2,6, and7, the first lead51has a die pad portion511and two extending portions512.

The die pad portion511supports the semiconductor element A1. The shape of the die pad portion511is not particularly limited. In the example shown inFIG.2, the die pad portion511has a rectangular shape in plan view. As shown inFIGS.6and7, the die pad portion511has a die-pad obverse surface511aand a die-pad reverse surface511b. The die-pad obverse surface511afaces a first side in the thickness direction z. The die-pad reverse surface511bfaces away from the die-pad obverse surface511ain the thickness direction z. In the illustrated example, the die-pad obverse surface511aand the die-pad reverse surface511bare flat surfaces. The semiconductor element A1is bonded to the die-pad obverse surface511a. As shown inFIGS.3,6, and7, the die-pad reverse surface511bis exposed from the sealing resin7(a resin reverse surface72described below).

As shown inFIGS.2and6, the two extending portions512extend from the die pad portion511to the respective sides in the first direction x. In the example shown inFIG.6, each of the extending portions512has a first section extending from the die pad portion511in the first direction x, a second section inclined relative to the first section and extending to the side in the thickness direction z that the die-pad obverse surface511afaces, and a third section extending from the second section in the first direction x, so that the extending portion512has a bent shape as a whole.

As shown inFIG.2, the second leads52are spaced apart from the first lead51. The second leads52include those electrically connected to the switching circuit30and those electrically connected to the control circuit40. The second leads52are arranged around the first lead51. In the illustrated example, the second leads52include those arranged on a first side in the second direction y with respect to the first lead51, and those arranged on a second side in the second direction y with respect to the first lead51. The second leads52on each of the first side and the second side in the second direction y are spaced apart from each other in the first direction x. As shown inFIGS.2and6, each of the second leads52has a pad portion521and a terminal portion522.

One of the first connecting members61, the second connecting members62, and the third connecting members63is connected to the pad portion521. In the example shown inFIG.7, the pad portion521is offset from the die pad portion511to the side in the thickness direction z that the die-pad obverse surface511afaces.

The terminal portion522extends outward from the pad portion521in the second direction y. The terminal portion522has a strip shape in plan view. As shown inFIG.7, the terminal portion522is bent into a gull-wing shape as viewed in the first direction x. As shown inFIG.7, a tip (an end distal to the die pad portion511in the second direction y) of the terminal portion522is located at the same (or substantially the same) position as the die pad portion511in the thickness direction z.

The terminal portions522of the second leads52are used as external terminals of the semiconductor device B1. The external terminals include an input terminal for a control signal, a ground terminal, an output terminal connected to a load, a power supply terminal, a non-connected terminal, a self-diagnostic output terminal.

Each of the first connecting members61, the second connecting members62, and the third connecting members63electrically connects two elements that are spaced apart from each other. The first connecting members61, the second connecting members62, and the third connecting members63are bonding wires, for example. The first connecting members61, the second connecting members62, and the third connecting members63may be plate-like metal members instead of bonding wires. Each of the first connecting members61, the second connecting members62, and the third connecting members63may contain a metal selected from a group including Au, Cu, and Al.

Each of the first connecting members61is bonded to one of the pad portions25formed on the first portion21A of the semiconductor element A1and one of the pad portions521of the second leads52. Each of the first connecting members61electrically connects the obverse-surface electrode21(first portion21A) and one of the second leads52.

Each of the second connecting members62is bonded to one of the pad portions25formed on the second portion21B of the semiconductor element A1and one of the pad portions521of the second leads52. Each of the second connecting members62electrically connects the obverse-surface electrode21(second portion21B) and one of the second leads52.

Each of the third connecting members63is bonded to the die pad portion511and one of the pad portions521of the second leads52. Each of the third connecting members63electrically connects the reverse-surface electrode24and one of the second leads52.

The sealing resin7covers a portion of each of the first lead51and the second leads52, the semiconductor element A1, the first connecting members61, the second connecting members62, and the third connecting members63. The sealing resin7is an insulating resin, and may contain an epoxy resin mixed with a filler. The sealing resin7has a resin obverse surface71, a resin reverse surface72, two resin side surfaces73, and two resin side surfaces74.

The resin obverse surface71faces the same side as the die-pad obverse surface511ain the thickness direction z. The resin obverse surface71is a flat surface, for example. The resin reverse surface72faces the opposite side from the resin obverse surface71(the same side as the die-pad reverse surface511b) in the thickness direction z. The resin reverse surface72is a flat surface, for example. The die-pad reverse surface511bis exposed from the resin reverse surface72.

The two resin side surfaces73are located between the resin obverse surface71and the resin reverse surface72in the thickness direction z, and are spaced apart from each other in the first direction x as shown inFIGS.2to4. Each of the extending portions512is exposed from one of the two resin side surfaces73. The two resin side surfaces74are located between the resin obverse surface71and the resin reverse surface72in the thickness direction z, and are spaced apart from each other in the second direction y as shown inFIGS.2,3and5. Each of the second leads52protrudes from one of the two resin side surfaces74.

The following describes the advantages of the semiconductor element A1and the semiconductor device B1.

The semiconductor element A1includes the wiring layer14formed on the obverse surface10aof the element body10, and the obverse-surface electrode21formed on the wiring layer14. In this configuration, when the temperature of the semiconductor element A1rises, the wiring layer14is subjected to a stress (thermal stress) via the insulating film17due to the thermal expansion of the obverse-surface electrode21. If the semiconductor element A1has a different configuration whereby, in plan view, a portion of the outer edge15of the wiring layer14connected to a pair of first edges151and152corresponds to a virtual edge150shown inFIG.9, then portions near the four corners of the wiring layer14may be crushed and deformed as a result of the thermal stress applied to the wiring layer14. Note that the distance from the virtual edge150to the outer edge22(corner portion223) in the direction vertical to the virtual edge150is the same (or substantially the same) as each of the distances d151and d152shown inFIG.9. The deformation of the wiring layer14as described above may cause breakage of the wiring layer14, and may also cause a void between the wiring layer14and the insulating film17when the temperature of the semiconductor element A1drops to a normal temperature. In other words, deformation of the wiring layer14lowers the reliability of the semiconductor element. In view of this, the semiconductor element A1is configured such that the outer edge15of the wiring layer14includes a pair of second edges153and154connected to a pair of first edges151and152. Further, each of the second edges153and154includes a portion that defines, in plan view, a distance d153or d154between the second edge153or154and the outer edge22(corner portion223) of the obverse-surface electrode21along the direction perpendicular to the second edge153or154, where the distance d153or d154is greater than the distance d151or d152between the first edge151or152and the outer edge22of the obverse-surface electrode21along the direction perpendicular to the first edge151or152. In other words, the semiconductor element A1is configured such that the wiring layer14and the obverse-surface electrode21satisfy the second relationships described above. As a result, the semiconductor element A1allows the portion of the wiring layer14arranged in a uniform manner to have a relatively small area at the four corners of the wiring layer14in plan view, as compared to the configuration where the portion of the outer edge15connected to a pair of first edges151and152corresponds to the virtual edge150inFIG.9. This makes it possible to reduce the occurrence of breakage of the wiring layer14and voids between the wiring layer14and the insulating film17by suppressing the thermal stress applied to the wiring layer14by the thermal expansion of the obverse-surface electrode21. In other words, the semiconductor element A1can improve reliability on a temperature change.

In the semiconductor element A1, the obverse-surface electrode21contains copper and the wiring layer14contains aluminum. In such a configuration, the difference in coefficients of thermal expansion between the obverse-surface electrode21and the wiring layer14causes the thermal stress due to the thermal expansion of the obverse-surface electrode21to be easily applied to the wiring layer14. Accordingly, as can be seen in the semiconductor element A1, configuring the wiring layer14and the obverse-surface electrode21to satisfy the second relationships described above is preferable in terms of improving the reliability of the semiconductor element A1on a temperature change.

In the semiconductor element A1, the thickness (the dimension in the thickness direction z) of the main portion211of the obverse-surface electrode21is 100% to 2000% with respect to the thickness (the dimension in the thickness direction z) of each of the first layer141and the second layer142of the wiring layer14. Although an increase in the size of the obverse-surface electrode21enables a decrease in the on-resistance of the switching circuit30, it also causes an increase in the thermal stress on the wiring layer14due to the thermal expansion of the obverse-surface electrode21. In view of this, the thickness of the main portion211is designed to be 100% to 2000% with respect to the thickness of each of the first layer141and the second layer142, and the wiring layer14and the obverse-surface electrode21are configured to satisfy the second relationships described above, whereby the semiconductor element A1can improve reliability on a temperature change while reducing the on-resistance of the switching circuit30.

In the semiconductor element A1, the wiring layer14includes the cutouts161each having a pair of second edges153and154. Each of the cutouts161has an L shape in plan view. Furthermore, in the semiconductor element A1, a plurality of openings171are arranged in an L shape at each of the four corners of the wiring layer14. According to the configuration, the cutouts161are formed along the arrangement direction of the openings171. In other words, each pair of second edges153and154is formed along a plurality of openings171arranged in an L shape. This makes it possible to reduce the area of the wiring layer14near the four corners of the obverse-surface electrode21in plan view, thus suppressing the thermal stress applied to the wiring layer14due to the thermal expansion of the obverse-surface electrode21. In other words, for the configuration where a plurality of openings171are formed in an L shape near each of the four corners of the obverse-surface electrode21, forming each of the cutouts161in an L shape in plan view is preferable in terms of improving the reliability of the semiconductor element A1on a temperature change.

In the semiconductor element A1, the edge portion163of the wiring layer14is formed with one or more slits162. The edge portion163can be formed in the wiring layer14due to the processing limit in the manufacturing of the semiconductor element A1. Since the wiring layer14is arranged in a uniform manner at the edge portion163, the edge portion163is also subjected to the thermal stress due to the thermal expansion of the obverse-surface electrode21, which may lead to the deformation of the wiring layer14at the portions other than the four corners in plan view. To address this issue, the semiconductor element A1is provided with one or more slits162, so that the slits162(the insulating film17filled in the slits162) restrain the wiring layer14to suppress the deformation of the wiring layer14. In other words, the semiconductor element A1can suppress the deformation of the wiring layer14not only at the four corners of the wiring layer14but also across the entire periphery of the wiring layer14, which makes it possible to further improve reliability on a temperature change.

The semiconductor device B1includes the semiconductor element A1. The semiconductor device B1undergoes frequent temperature changes depending on its use environment. For example, when the semiconductor device B1is mounted on a circuit board of an automobile or the like, the automobile may run under various climatic conditions from cold to hot and humid areas. Furthermore, when the semiconductor device B1is mounted within the engine room, it will be constantly exposed to temperature changes resulting from the environment and driving patterns. Since the semiconductor element A1can improve reliability on a temperature change as described above, the semiconductor device B1has improved reliability on a temperature change. This allows the use of the semiconductor device B1even in an environment with frequent temperature changes, and the semiconductor device B1is therefore applicable to a wide range of uses.

The above embodiment has provided an example where each of the cutouts161formed at the four corners of the wiring layer14has an L shape in plan view. However, the plan-view shape of the cutouts161is not particularly limited as long as the above-described second relationships are satisfied. For example, each of the cutouts161may have the shape shown inFIG.15, and a second edge155, which is connected to a pair of first edges151and152at the outer edge15of the wiring layer14, may be curved instead of being linear.

The semiconductor element and the semiconductor device according to the present disclosure are not limited to those in the above embodiment. Various design changes can be made to the specific configurations of the elements of the semiconductor element and the semiconductor device according to the present disclosure. For example, the present disclosure includes the embodiments according to the following clauses.

A semiconductor element comprising:an element body including an obverse surface facing one side in a thickness direction;a wiring layer formed on the obverse surface and electrically connected to the element body; andan obverse-surface electrode formed on and electrically connected to the wiring layer,wherein an outer edge of the obverse-surface electrode includes a corner portion as viewed in the thickness direction,the wiring layer includes a first edge extending along the outer edge of the obverse-surface electrode as viewed in the thickness direction, and a second edge connected to the first edge and facing the corner portion as viewed in the thickness direction, andthe second edge includes a portion that defines, as viewed in the thickness direction, a distance from the second edge to the outer edge of the obverse-surface electrode in a direction perpendicular to the second edge, the distance being greater than a distance from the first edge to the outer edge of the obverse-surface electrode in a direction perpendicular to the first edge.

The semiconductor element according to clause 1, wherein the outer edge of the obverse-surface electrode includes a side end that is connected to the corner portion and parallel to the first edge, andthe corner portion is linear as viewed in the thickness direction and inclined to the side end as viewed in the thickness direction.

The semiconductor element according to clause 2, wherein the obverse-surface electrode has an octagonal shape as viewed in the thickness direction.

The semiconductor element according to clause 2 or 3, wherein the obverse-surface electrode includes a main portion having the corner portion and the side end and overlapping with the wiring layer as viewed in the thickness direction.

The semiconductor element according to clause 4, further comprising an insulating film interposed between the main portion and the wiring layer in the thickness direction.

The semiconductor element according to clause 5, wherein the obverse-surface electrode includes a plurality of penetrating portions passing through the insulating film and electrically connecting the main portion and the wiring layer.

The semiconductor element according to clause 6, wherein the wiring layer includes an edge portion located between the plurality of penetrating portions and the first edge as viewed in the thickness direction, and the edge portion is formed with at least one slit.

The semiconductor element according to clause 7, wherein the edge portion is formed with a plurality of slits, and the plurality of slits are arranged along the first edge.

The semiconductor element according to any of clauses 1 to 8, wherein the wiring layer includes an L-shaped cutout having the second edge.

The semiconductor element according to any of clauses 1 to 9, wherein the wiring layer includes a first layer and a second layer stacked and spaced apart from each other in the thickness direction, and a plurality of vias electrically connecting the first layer and the second layer.

The semiconductor element according to clause 10, further comprising an interlayer insulating layer located between the first layer and the second layer, andthe plurality of vias pass through the interlayer insulating layer in the thickness direction.

The semiconductor element according to any of clauses 1 to 11, wherein the wiring layer contains aluminum, andthe obverse-surface electrode contains copper.

The semiconductor element according to any of clauses 1 to 12, wherein the element body includes a switching circuit and a control circuit.

The semiconductor element according to clause 13, wherein the obverse-surface electrode includes a first portion and a second portion spaced apart from each other,the first portion overlaps with the switching circuit as viewed in the thickness direction, andthe second portion overlaps with the control circuit as viewed in the thickness direction.

The semiconductor element according to clause 13 or 14, further comprising a reverse-surface electrode,wherein the element body includes a reverse surface facing an opposite side from the obverse surface, andthe reverse-surface electrode is provided on the reverse surface and electrically connected to the switching circuit.

The semiconductor element according to any of clauses 1 to 15, wherein the element body contains silicon.

A semiconductor device comprising:a semiconductor element according to any of clauses 1 to 16;a die pad portion on which the semiconductor element is mounted;a sealing resin covering at least a part of the die pad portion and the semiconductor element; anda terminal portion protruding from the sealing resin and electrically connected to the semiconductor element.

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