Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2018-229561 filed on Dec. 7, 2018 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and, for example, to a semiconductor device including a transistor to which a gate resistance is connected and a method of manufacturing a semiconductor device.

A semiconductor module handling large power is generally configured by multiple parallel connections in which a plurality of semiconductor chips are connected in parallel. This makes it possible to configure an inverter system or the like that handles a large current. In such a multi-parallel-connected semiconductor module, a gate resistance is incorporated in a semiconductor chip as a damping resistance or suppression of an unbalance operation between semiconductor chips.

SUMMARY

Japanese unexamined Patent Application publication No. 2003-197914 discloses that a gate resistance is formed in a gate pad region to suppress an increase in chip size. However, since the contact is formed under the gate pad, there is a fear that the influence on the wire bonding property is caused by the influence of the step in this portion. In addition, the size of the gate resistance needs to be equal to or smaller than the gate pad region, and the design of the gate resistance is limited. Further, since a capacitance due to the oxide film formed under the gate resistance is connected in parallel with the gate resistance, an influence of the capacitance on the resistance value of the gate resistance cannot be eliminated.

Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

According to one embodiment, a semiconductor device comprises a gate resistance provided on a main surface of a semiconductor substrate, a first and a second contact extending in a first direction extending along a plane parallel to the main surface and contacting with an upper surface of the gate resistance at an a distance along a second direction orthogonal to the first direction, and a carrier discharging portion formed in the semiconductor substrate below the gate resistance and configured to discharge a carrier. The gate resistance comprises a first contacting portion extending in the first direction, a second contacting portion extending in the first direction and contacting with the second contact, and a plurality of extending portions extending in the second direction and contacting with the first contacting portion at one end of the extending portions and contacting with the second contacting portion at another end of the extending portions. The gate resistance has an opening formed between adjacent extending portions, and connected to a gate electrode of a transistor via the first contact or the second contact, and the carrier discharging portion is formed in the opening.

According to the above embodiment, it is possible to provide a semiconductor device and a method of manufacturing the semiconductor device, which can suppress breakdown due to current concentration and an increase in chip size.

DETAILED DESCRIPTION

For clarity of explanation, the following description and drawings are appropriately omitted and simplified. In the drawings, the same elements are denoted by the same reference numerals, and a repetitive description thereof is omitted as necessary.

Comparative Example

Before describing a semiconductor device according to embodiments, the semiconductor device according to a comparative example will be described. Thereby, the semiconductor device according to the embodiments can be made clearer.

FIG. 1Ais a plan view exemplifying the semiconductor device according to a comparative example.FIG. 1Bis a cross-sectional view exemplifying the semiconductor device according to the comparative example, and shows a cross-section taken along a line I-I inFIG. 1A.FIG. 1Cis a graph exemplifying a correlation between a length of a gate resistance and a resistance value incorporated in the semiconductor device according to the comparative example, and horizontal axis shows the length of the gate resistance, and vertical axis shows the gate resistance value.

As shown inFIGS. 1A and 1B, a semiconductor device101according to the comparative example is formed in a semiconductor substrate10. The semiconductor device101includes a gate resistance120, an emitter wiring30, a gate pad40, a first contact61, and a second contact62. The gate resistance120, the emitter wiring30, the gate pad40, the first contact61, and the second contact62are provided on a main surface10aof the semiconductor substrate10. InFIG. 1A, a plurality of emitter wirings30are provided. A collector electrode (not shown) is provided on a back surface10b. The gate resistance120is, for example, disposed between the emitter wiring30and the gate pad40on the main surface10aof the semiconductor substrate10. The gate resistance120has a rectangular shape having a width W and a length L when viewed from the main surface10a.

Here, for convenience of description of the semiconductor device101, an XYZ orthogonal coordinate axis is introduced. A direction perpendicular to the main surface10aof the semiconductor substrate10is defined as a Z-axis direction, a direction from the back surface10bto the main surface10ais defined as a +Z-axis direction, and a direction from the main surface10ato the back surface10bis defined as a −Z-axis direction. The +Z-axis direction is also referred to as an upward direction, and the −Z-axis direction is also referred to as a downward direction. A plane parallel to the main surface10ais defined as an XY plane. For example, a direction along the length L of the gate resistance120is the X-axis direction, and a direction along the width W of the gate resistance120is the Y-axis direction.

The gate resistance120includes, for example, polysilicon doped with a predetermined impurity as a material. The gate resistance120is covered with an insulating film50. The insulating film50includes, for example, silicon oxide such as PSG and SOG.

The first contact61and the second contact62are connected to the main surface10aside of the gate resistance120. The first contact61is, for example, a so-called high-side contact connected to a gate wiring71on the gate pad40side. The second contact62is, for example, a so-called low-side contact connected to a gate wiring72on an active cell side. The first contact61and the second contact62are formed in a portion where the insulating film50is removed by etching or the like. On an upper surface of the gate resistance120, the first contact61is connected to a vicinity of an end of the gate resistance in the +X-axis direction. On the upper surface of the gate resistance120, the second contact62is connected to a vicinity of an end in the −X-axis direction.

The first contact61and the second contact62extend in the Y-axis direction in the XY plane parallel to the main surface10a. For example, on the upper surface of the gate resistance120, the first contact61and the second contact62extend from a vicinity of an end on the −Y-axis direction side to a vicinity of an end on the +Y-axis direction side. Further, the first contact61and the second contact62are connected to the upper surface of the gate resistance120at distance mutually in the X-axis direction. A plurality of first contacts61and a plurality of second contacts62may be formed. The first contact61and the second contact62may be formed of a plurality of contacts separated from each other in the X-axis direction. Each contact extends in the Y-axis direction.

The first contact61and the second contact62are connected to the gates wiring71and72formed so as to cover the insulating film50. The gates wiring71and72are made of, for example, aluminium. Since a current flows between the gate wiring71and the gate resistance72, the gate resistance120functions as a resistance.

FIG. 2Ais a plan view exemplifying the gate resistance of the semiconductor device according to the comparative example, andFIG. 2Bis a cross-sectional view exemplifying the gate resistance of the semiconductor device according to the comparative example, and shows a cross-section of a II-II line inFIG. 2A.

As shown inFIGS. 2A and 2B, the gate resistance120is rectangular and is formed on the semiconductor substrate10.FIG. 2Acollectively shows the first contact61and the second contact62formed of the plurality of the contacts. The semiconductor substrate10has an n-type drift layer11, a deep p-type diffusion layer12functioning as a well layer, and a shallow p-type diffusion layer13. In the semiconductor substrate10, the deep p-type diffusion layer12is formed on the n-type drift layer11, and the shallow p-type diffusion layer13is formed on the deep p-type diffusion layer12. The semiconductor substrate10may have other diffusion layer. For example, an n-type field stop layer and a p-type collector layer may be included below the n-type drift layer11.

An insulating film51is formed on the semiconductor substrate10, and the gate resistance120is formed on the insulating film51. The gate resistance120is covered with the insulating film50. The emitter wiring30, for example, is formed on the insulating film50. In the vicinity of the ends of the gate resistance20in the +X-axis direction and the −X-axis direction, gate wiring71and72are formed on the insulating film50and connected to the first and second contact61and62via contact holes formed in the insulating film50.

Next, two problems relating to the gate resistance120according to the comparative example will be described. First problem is that a chip size of the semiconductor device101increases. As shown inFIG. 1C, as the length L of the gate resistance120increases, the resistance value increases. When the gate resistance120is set to a predetermined resistance value, it is necessary to increase the gate resistance120to a predetermined length. Therefore, the area on the main surface10aoccupied by the gate resistance120becomes large. Thus, it is the first problem to increase the chip size in order to achieve the predetermined resistance value. As the chip size increases, a cost of manufacturing the semiconductor device1increases.

Second problem is that carriers15such as holes are concentrated in a peripheral region16of the gate resistance120to cause current concentration. As shown inFIG. 1B, carriers15such as holes accumulated under the gate pad40are discharged from the peripheral region16of the gate resistance120at the time of turn-off. Since the gate resistance120covers the main surface10aof the semiconductor substrate10, the carrier15accumulated at a time of conduction is not extracted from a region where the gate resistance120is disposed. Thus, the carriers15concentrate in the peripheral region16of the gate resistance120and cause breakdown.

The first and second problems also relate to configurations of the first contact61and the second contact62. From the viewpoint of EMD (Electromigration-Damage), the first contact61and the second contact62require that a length in the Y-axis direction corresponding to the width W of the gate resistance120is about 2000 [μm], and a length in the X-axis direction corresponding to the length L of the gate resistance120is about 5 [μm] (in the drawing, 2000 [μm]×1 [μm]×5). Thus, the length of each contact in the Y-axis direction (2000 [μm]) and the length in the X-axis direction also increase the chip size and increase the cost. In addition, the area of the gate resistance120for contact is also required, which causes a decrease in breakdown tolerance.

First Embodiment

Next, the semiconductor device of a first embodiment will be described.FIG. 3Ais a plan view exemplifying the gate resistance of the semiconductor device according to the first embodiment, andFIG. 3Bis a cross-sectional view exemplifying the gate resistance of the semiconductor device according to the first embodiment, and shows a cross-section of the III-III line ofFIG. 3A.FIG. 4Ais a plan view exemplifying the semiconductor device according to the first embodiment, andFIG. 4Bis a cross-sectional view exemplifying the semiconductor device according to the first embodiment, and shows a cross-section of the IV-IV line ofFIG. 4A.FIG. 5Ais a cross-sectional view illustrating a parasitic MOS of the semiconductor device according to the first embodiment, and is an enlarged view ofFIG. 4B.FIG. 5Bis a diagram illustrating a connection relationship of a configuration of the parasitic MOS.FIGS. 6A and 6Bare plan views illustrating the semiconductor device according to the first embodiment, andFIG. 6Bis an enlarged view of the VI region ofFIG. 6A.

As shown inFIGS. 3A and 3B, a gate resistance20of the present embodiment is provided on the main surface10aof the semiconductor substrate10. InFIG. 3A, the semiconductor substrate10is omitted. Note that reference numerals are omitted as appropriate so that the drawings are not complicated. The same applies to the following figures. The gate resistance20is in the appearance of a strip, and a plurality of openings25are formed. The gate resistance20has a shape in which a plurality of openings25are thinned out from a rectangular flat conductive film formed of a solid film. Specifically, the gate resistance20has a first contacting portion21with which the first contact61is connected, a second contacting portion22with which the second contact62is contacted, and a plurality of extending portions23. The first contacting portion21and the second contacting portion22extend, for example, in the Y-axis direction. The first contacting portion21and the second contacting portion22are arranged at a distance in the X-axis direction. The first contact61is connected to the upper surface of the first contacting portion21. The second contact62is connected to the upper surface of the second contacting portion22.

The plurality of the extending portions23extend in the X-axis direction. One end of the extending portions23is connected to the first contacting portion21, and the other end of the extending portions23is connected to the second contacting portion22. The extending portion23includes a solid film formed on the main surface10a. The length of each extending portion23in the Y-axis direction and the number of extending portions23are determined based on a predetermined resistance value of the gate resistance20. The plurality of extending portions23are arranged at a distance in the Y-axis direction between the first contacting portion21and the second contacting portion22. Therefore, in the gate resistance20, the openings25is formed between the adjacent extending portions23.

As shown inFIG. 3B, the semiconductor substrate10includes the n-type drift layer11, the deep p-type diffusion layer12functioning as the well layer, and the shallow p-type diffusion layer13. In the semiconductor substrate10, the deep p-type diffusion layer12is formed on the n-type drift layer11, and the shallow p-type diffusion layer13is formed on the deep p-type diffusion layer12. The semiconductor substrate10may have other diffused layer. An insulating film51is formed on the semiconductor substrate10, and the extending portions23, the first contacting portion21, and the second contacting portion22of the gate resistance20are formed on the insulating film51. The gate resistance20is covered with the insulating film50. The emitter wiring30, for example, is formed on the insulating film50. Also in the present embodiment, the gate wiring71and72are formed on the insulating film50in the vicinity of the end in the +X-axis direction and in the vicinity of the end in the −X-axis direction of the gate resistance20, and may be connected to the first contact61and the second contact62via the contact holes formed in the insulating film50. Thus, the gate resistance20is connected to the gate electrode of the transistor via the first contact61or the second contact62.

Next, a carrier discharging portion80of the semiconductor device1will be described. As shown inFIGS. 4A and 4B, andFIGS. 5A and 5B, the semiconductor device1includes a carrier discharging portion80in addition to the gate resistance20, the first contact61, and the second contact62. The carrier discharging portion80is a portion for discharging the carrier formed on the semiconductor substrate10below the gate resistance20. The carrier discharging portion80is formed in the opening25. In the present embodiment, the carrier discharging portion80is a parasitic MOS81.

The parasitic MOS81includes a trench electrode41, a trench insulating film43, the n-type drift layer11, the deep p-type diffusion layer12, the shallow p-type diffusion layer13, a p-type body contact layer14, and the emitter wiring30. The parasitic MOS81may include other diffusion layers.

The trench electrode41is provided in a trench42formed in the semiconductor substrate10. The trench42is circularly formed in the semiconductor substrate10when viewed from the main surface10aof the semiconductor substrate10. The trench electrodes41extend from the main surface10aof the substrate to the n-type drift layer11. For example, the trench electrodes41includes polysilicon doped with a predetermined impurity. In which conductive materials such as polysilicon are buried in the trench42is referred to as a trench conductive layer, and which functions as the parasitic MOS81and a MOS electrode is referred to the trench electrodes41. The trench electrode41of the parasitic MOS81is connected to the emitter wiring30and an emitter potential is applied.

The trench insulating film43is formed on an inner surface of the trench42, and is formed between the trench electrodes41and the semiconducting substrate10. The trench insulating film43includes, for example, silicon oxide.

In the semiconductor substrate10, the n-type drift layer11is formed in a portion surrounded by the trench electrode41. The shallow p-type diffusion layer13is formed on the n-type drift layer11in the semiconductor substrate10. The p-type body contact layer14is formed on the shallow p-type diffusion layer13in the semiconductor substrate10. The deep p-type diffusion layer12is formed outside portion of the circular trench electrode41in the semiconductor substrate10. The emitter wiring30is connected to the p-type body contact layer14. The emitter wiring30is connected to the p-type body contact layer14via a contact opening44formed in the semiconductor substrate10. The emitter wiring30is also connected to the trench electrode41.

As shown inFIG. 5B, the parasitic MOS81operates as a parasitic PMOS by combining the trench electrode41to which the emitter potential is applied and the deep p-type diffusion layer12to be floated. That is, the deep p-type diffusion layer12serving as floating becomes a p-type diffusion layer of a p-type channel FET, the n-type drift layer11becomes a n-type channel layer, and the p-type body contact layer14becomes a p-type diffusion layer of a p-type channel FET. Thus, a pnp MOSFET is formed. At turn-off, holes are generated in a side of the trench electrode41. Therefore, the deep p-type diffusion layer12serving as floating is electrically connected to the p-type body contact layer14. As a result, a hole discharge path is secured and the holes are discharged.

As shown inFIGS. 6A and 6B, in the semiconductor device1, the gate wiring71of the gate pad40side is formed so as to connect to the first contact61of the gate resistance20. As a result, the first contact61is connected to the gate pad. On the other hand, the gate wiring72of the active cell side is formed so as to be connected to the second contact62. As a result, the second contact62is connected to the active cell.

The emitter wiring30is disposed on the semiconductor substrate10between the gate wiring71and the gate wiring72. The emitter wiring30is formed so as to be connected to the p-body contact layer14of the parasitic MOS81formed in the openings25of the gate resistance20.

Next, a method of manufacturing the semiconductor device1will be described.FIGS. 7A, 7B and 7C,FIGS. 8A, 8B and 8C, andFIGS. 9A, 9B and 9Care process cross-sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment.

First, as shown inFIG. 7A, an active cell portion91and a gate-resistance portion92are set on the main surface10aof the semiconductor substrate10. For example, the semiconductor substrate10includes the active cell portion91and the gate resistance portion92when viewed from the main surface10a, and an IGBT is formed in the active cell portion91and a gate resistance20is formed in the gate resistance portion92.

In order to form an n-type hole barrier layer, for example, an n-type impurity is introduced into the active cell portion91by ion implantation or the like. At the same time, a p-type impurity is introduced into the active cell portion91and the gate resistance portion92by ion implantation or the like in order to form, for example, the deep p-type diffusion layer12. As a result, a region17aincluding the n-type impurity and a region12aincluding the p-type impurity are formed in the semiconductor substrate10.

Next, as shown inFIG. 7B, the trench42is formed so as to separate the region17aincluding the n-type impurity and the region12aincluding the p-type impurity of the active cell portion91. At the same time, the trench42is formed so as to separate the region12aincluding the p-type impurity in the gate resistance portion92.

Next, as shown inFIG. 7C, the semiconductor substrate10is heat-treated to diffuse impurities in each region. As a result, the deep p-type diffusion layer12and the n-type hole barrier layer17are formed in the active cell portion91, and the deep p-type diffusion layer12is formed in the gate resistance portion92. In present embodiment, each diffusion layer is separated by the trench42. Therefore, the diffusion of each impurity is limited to the region separated by the trench42.

Next, as shown inFIG. 8A, the insulating film51is formed on the main surface10aof the semiconductor substrate10and the inner surface of the trench42. For example, oxidation treatment is performed to form the insulating film50. As a result, in the active cell portion91, a gate dielectric film45is formed on the inner surface of the trench42. In the gate resistance portion92, the trench insulating film43is formed.

Next, as shown inFIG. 8B, a conductive material is deposited on the semiconductor substrate10and inside the trench42. Then, in the active cell portion91, portions other than the inside of the trench42are removed. Thus, the conductive material is embedded in the trench42to form the trench electrode41. The trench electrode41of the active cell portion91functions as the gate electrode. On the other hand, in the gate resistance portion92, portions other than the inside of the trench42and the gate resistance20are removed. As a result, the trench electrode41is formed, and the gate resistance20is formed from the conductive material on the main surface10aside. When forming the gate resistance20, as described above, the first contacting portion21, the second contacting portion22and the plurality of extending portions23are provided, and the openings25are formed between adjacent extending portions23.

Next, as shown inFIG. 8C, an impurity is introduced into the semiconductor substrate10by ion implantation or the like in order to adjust the impurity concentrations of a channel layer and to form the shallow p-type diffusion layer13. Then, the insulating film50(e.g. PSG, SOG, or the like) is formed on the semiconductor substrate10.

Next, as shown inFIG. 9A, a contact opening44is formed by etching or the like on the insulating films50and51and the semiconductor substrate10. Although not shown, an opening for forming the first contact61and the second contact62is formed in the insulating films50and51on the gate resistance20.

Next, as shown inFIG. 9B, an impurity is introduced by ion implantation or the like via the contact opening44. Thus, the p-type body contact layer14is formed.

Next, as shown inFIG. 9C, the emitter wiring30of aluminium or the like is formed on the semiconductor substrate10so as to connect to the p-type body contact layer14through the contact trench44. Although not shown, gate wirings71and72made of aluminium or the like are formed on the semiconductor substrate10so as to be connected to the gate resistance20via openings formed in the insulating films50and51on the gate resistance20. Thus, the first contact61and the second contact62connected to the upper surface of the gate resistance20are formed.

In this manner, a predetermined process is performed on the active cell portion91to form an IGBT. At the same time, the gate resistance20including the carrier discharging portion80is formed in the gate resistance portion92. In this manner, the semiconductor device1can be manufactured.

Next, effects of the present embodiment will be described. In the present embodiment, the opening25is provided in the gate resistance20, and the gate resistance20is formed into a strip shape. As a result, the resistance value of the gate resistance20can be increased. Therefore, the length L between the first contact61and the second contact62can be reduced, and the area occupied by the gate resistance20on the main surface10aof the semiconductor substrate10can be reduced. Therefore, an increase in the chip size can be suppressed.

A parasitic MOS81is formed in the opening25. As a result, carriers such as holes accumulated in the semiconductor substrate10below the gate resistance20can be effectively discharged through the parasitic MOS81. Therefore, current concentration in the peripheral region16of the gate resistance20at a time of turn-off can be suppressed.

Further, since the area occupied by the gate resistance20on the main surface10acan be reduced, the capacitance formed in the semiconductor substrate10can be reduced, and the speed-up and the amount of displacement current generated can be suppressed.

In forming the gate resistance20, it may be formed simultaneously with the manufacturing process of the active cell portion91. For example, the gate resistance20and the trench electrode41of the parasitic MOS81can be formed at the same time as the trench electrode41of the active cell portion91. In addition, the deep p-type diffusion layer12, the shallow p-type diffusion layer13, and the p-type body contact layer14in the parasitic MOS81can be formed simultaneously with the active cell portion91. Therefore, an increase in manufacturing cost can be suppressed.

In particular, when the deep p-type diffusion layer12is formed, the trench42is formed so as to separate the region12aincluding the impurity, and thereafter the impurity is diffused. Therefore, since the diffusion of the impurity is limited by the trench42, a fine diffusion layer can be formed.

Second Embodiment

Next, a semiconductor device according to second embodiment will be described. In the semiconductor device of the present embodiment, the emitter wiring30is connected to the outer portion of the trench electrode41so that floating layer is not formed below the gate resistances20.FIG. 10Ais a plan view exemplifying a semiconductor device according to second embodiment, andFIG. 10Bis a cross-sectional view exemplifying a semiconductor device according to second embodiment, and shows a cross-section taken along line X-X inFIG. 10A.

As shown inFIGS. 10A and 10B, also in the present embodiment, a plurality of openings25are formed in the gate resistance20. In the semiconductor device2of the present embodiment, the carrier discharging portion80formed in the opening25is different from that of the first embodiment. That is, the emitter wiring30is connected to the deep p-type diffusion layer12outside the region surrounded by the trench electrodes41. Therefore, the deep p-type diffusion layer12has a region in which a floating layer is not formed.

Specifically, the carrier discharging portion80includes trench electrodes41, the trench insulating film43, the n-type drift layer11, the deep p-type diffusion layer12, the shallow p-type diffusion layer13, the diffusion p-type body contact layer14, and the emitter wiring30. The trench electrode41, the trench insulating film43, the n-type drift layer11, the deep p-type diffusion layer12, and the shallow p-type diffusion layer13are the same as those in the first embodiment. In the present embodiment, the p-type body contact layer14is formed on the deep p-type diffusion layer12outside of the circular-shaped trench electrode41. The emitter wiring30is connected to the p-type body contact layer14formed on the outside of the circular trench electrode41. For example, the emitter wiring30is connected to the p-type body contact layer14through a circular-shaped contact trench44formed along the outside of the trench electrode41.

In the carrier discharging portion80of the present embodiment, the discharge path of the carrier15is not inside surrounded by the circular trench electrode41, but outside the circular trench electrode41. Therefore, the carrier15is directly discharged from the semiconductor substrate10below the gate resistance20. Therefore, the deep p-type diffusion layer12has a region in which a floating layer is not formed.

According to the semiconductor device2of the present embodiment, the deep p-type diffusion layer12under the gate resistance29is connected to the emitter wiring30. Therefore, the carriers15formed in the substrate10below the gate resistance20can be directly discharged from the deep p-type diffusion layer12to the emitter wiring30. Therefore, the discharge effect of the carrier15can be improved. The formation of the carrier discharging portion80of the second embodiment can also be formed simultaneously with the manufacture of the active cell portion91, such as the IGBT, as in the first embodiment. Other forms and effects are included in the description of the first embodiment.

Third Embodiment

Next, a semiconductor device according to a third embodiment will be described. In the semiconductor device of the present embodiment, only the p-body contact layer14is formed without forming a parasitic MOS81in the opening25.FIG. 11Ais a plan view exemplifying a semiconductor device according to the third embodiment, andFIG. 11Bis a cross-sectional view exemplifying a semiconductor device according to the third embodiment, and shows a cross-section of a XI-XI line inFIG. 11A.

As shown inFIGS. 11A and 11B, in a semiconductor device3of the present embodiment, a plurality of openings25are formed in the gate resistance20. In the semiconductor device3of the present embodiment, the carrier discharging portion80formed in the opening25is the p-type body contact layer14.

Specifically, the carrier discharging portion80includes the n-type drift layer11, the deep p-type diffusion layer12, the shallow p-type diffusion layer13, the p-type body contact layer14, and the emitter wiring30. The n-type drift layer11is formed on the semiconductor substrate10. The deep p-type diffusion layer12is formed on the n-type drift layer11. The p-type body contact layer14is formed on the deep p-type diffusion layer12. The emitter wiring30is connected to the p-type body contact layer14. For example, the emitter wiring30is connected to the p-type body contact layer14through a contact trench44formed in the semiconductor substrate10.

In the semiconductor device of the present embodiment, the trench electrode41is not formed in the opening25. Therefore, it is possible to cope with the planar type IGBT. That is, the gate resistance92can be manufactured together with the planar IGBT by using the manufacturing process of the planar IGBT. Other forms and effects are included in the description of the first and second embodiments.

Fourth Embodiment

Next, a semiconductor device according to fourth embodiment will be described. In the gate resistance in the semiconductor device of the present embodiment, the extending portion is formed inside the trench42.FIG. 12Ais a plan view illustrating the gate resistance of a semiconductor device according to the fourth embodiment, andFIG. 12Bis a cross-sectional view illustrating the gate resistance of a semiconductor device according to the fourth embodiment, and shows a cross-sectional view of a XII-XII line according toFIG. 12A.FIG. 13Ais a plan view exemplifying a semiconductor device according to the fourth embodiment, andFIG. 13Bis a cross-sectional view exemplifying a semiconductor device according to the fourth embodiment, and shows a cross-section of a XIII-XIII line inFIG. 13A.

As shown inFIGS. 12A and 12B, a gate resistance20aof present embodiment has an extending portion23aformed within the trench42. The extending portion23aincludes a trench conductive layer provided inside the trench42. The opening25is formed between the adjacent extending portions23a. As shown inFIGS. 13A and 13B, in the semiconductor device4of present embodiment, the carrier discharging portion80formed in the opening25is a p-type body contact layer14. Therefore, present embodiment is the same as the third embodiment.

In the above-described first, second and third embodiments, the extending portion23of the gate resistance20is a planar type and is formed as a beta film on the main surface10aof the semiconductor substrate10. On the other hand, in the present embodiment, the extending portion23aof the gate resistance20ais formed by embedding a conductive material such as polysilicon in the trench42. In this manner, by forming the gate resistance20ainside the trench42, the adjustment range of the resistance value of the gate resistance20acan be expanded. For example, the adjustment range can be extended from a small resistance value to a large resistance value. When the gate resistance20ais designed, the distance between the extending portions23aadjacent to each other in the Y-axis direction can be determined based on a predetermined resistance value of the gate resistance20a.

An opening25is formed between the extending portions23aformed inside the trench42. The discharge of the carrier15can be adjusted by adjusting the pitch of the contact opening44in the opening25.

The extension portion23aof the present embodiment can be formed at the same time when the trench electrode41is formed. Therefore, an increase in manufacturing cost can be suppressed. Other forms and effects are included in the description of the first, second and third embodiments.

Fifth Embodiment

Next, a semiconductor device according to fifth embodiment will be described. In the gate resistance20ain the semiconductor device of the present embodiment, the extending portion23ais formed inside the trench42. A parasitic MOS81is formed in the opening25.FIG. 14Ais a plan view illustrating a semiconductor device according to the fifth embodiment, andFIG. 14Bis a cross-sectional view illustrating a semiconductor device according to the fifth embodiment, and shows a cross-sectional view of a XIV-XIV line according toFIG. 14A.

As shown inFIGS. 14A and 14B, the gate resistance20aof the semiconductor device5of present embodiment has an extending portion23aformed within the trench. The parasitic MOS81is formed in the opening25. Therefore, the configuration of the gate resistance20ais the same as that of the fourth embodiment. The configuration of carrier discharging portion80is the same as that of the first embodiment.

FIG. 15Ais a plan view illustrating a semiconductor device according to another example of the fifth embodiment; andFIG. 15Bis a cross-sectional view illustrating a semiconductor device according to another example of the fifth embodiment, and shows a cross-section of a XV-XV line according toFIG. 15A. As shown inFIGS. 15A and 15B, in a semiconductor device5aof another embodiment of the fifth embodiment, the extending portion23ais thinned out as compared with the semiconductor device5described above. That is, the interval between the extending portions23ain the Y-axis direction is widened. In this manner, in the semiconductor device5a, the resistance of the gate resistance20acan be adjusted by adjusting the distance between the extending portions23a. By increasing the distance, the resistance value can be increased. Therefore, when the resistance value of the gate resistance20ais set to be large, an increase in size can be suppressed.

According to the semiconductor device5and the semiconductor device5aof the present embodiment, it is possible to improve the discharge effects of the carrier15and to adjust the resistance of the gate resistance20a. Other forms and effects are included in the description of the first, second, third and fourth embodiments.

Sixth Embodiment

Next, a semiconductor device according to sixth embodiment will be described. In the semiconductor device101of the comparative example shown inFIG. 1, the insulating film51is provided to insulate between the gate resistance120and the lower p-type diffusion layer. However, the insulating film51functions as a capacitor connected in parallel between the gate and the emitter, and changes the resistance value of the gate resistance20.

FIG. 16Ais a circuit diagram illustrating an equivalent circuit of a semiconductor device according to a comparative example.FIG. 16Bis a graph illustrating a gate waveform of a semiconductor device according to a comparative example, and the horizontal axis indicates time, and the vertical axis indicates a gate potential and a gate current. As shown inFIG. 16A, the gate of the semiconductor device101is connected to an internal resistance Rgintand a parasitic resistance Rgpara, and the capacitance of the insulating film51is connected in parallel between the gate and the emitter. Here, the inner resistance Rgintmeans a resistance by the gate resistance120, and the parasitic resistance Rgparameans a parasitic gate resistance.

For example, when a verification experiment is actually performed, it is measured that the capacity is reduced. Capacitance measurements are usually detected in AC (1 MHz). As shown inFIG. 16B, a gate control of the IGBT is PWM-controlled by triangular wave comparison and a pulse waveform, but since the gate is pulled negative, the pulse waveform is a waveform close to AC. If the capacitance is fluctuating, the resistance value changes depending on the switching frequency. The change in impedance Z is given by the following equation:
Z=1/(2π×f×c)

Where f represents the switching frequency and c represents the capacitance. Such parasitic capacitances are affected by process variations and cause a difference between semiconductor devices. This causes an imbalance in the operation of the parallel connection. Therefore, stable switching cannot be performed. The present embodiment is to solve such a problem.

Hereinafter, the semiconductor device of the present embodiment will be described with reference to the drawings.FIG. 17Ais a diagram illustrating a semiconductor device according to the sixth embodiment, andFIG. 17Bis a circuit diagram illustrating an equivalent circuit of the semiconductor device according to the sixth embodiment. As shown inFIG. 17A, in the semiconductor device6of the present embodiment, the p-type diffusion layer below the gate resistance20is separated by an isolation layer46and is floating. That is, it is separated from the surrounding emitter potential layer. Therefore, as shown inFIG. 17B, no capacitance is formed between the gate and the emitter. This makes it possible to suppress the variation of the resistance value of the gate resistance20, thereby enabling stable switching.

FIG. 18Ais a plan view exemplifying a semiconductor device according to the sixth embodiment.FIGS. 18B and 18Care cross-sectional views exemplifying a semiconductor device according to the sixth embodiment.FIG. 18Bshows a cross-section of a XVIIIb-XVIIIb line ofFIG. 18A, andFIG. 18Cshows a cross-section of a XVIIIc-XVIIIc line ofFIG. 18A.

As shown inFIGS. 18A, 18B, and 18C, the semiconductor device6of present embodiment has a gate resistance20, and the carrier discharging portion80of the opening25is a parasitic MOS81. In addition, the semiconductor device6includes isolation layer46that separates the semiconductor substrate10circularly along a periphery of the gate resistance20so as to surround the gate resistance20when viewed from the main surface10a. The isolation layer46is, for example, a trench conductive layer provided inside the trench42formed in the semiconductor substrate10. With such a configuration, the p-type diffusion layers12and13below the gate resistance20are made floating. Therefore, since it is not connected to the emitter potential, it does not function as a parallel capacitor. As a result, the variation of the resistance value of the gate resistance20is suppressed, and stable switching is enabled.

When the amount of carriers15to the floating layer fluctuates, a displacement current to the gate is generated and a potential fluctuates. However, in the present embodiment, a parasitic MOS81connected to the floating layer is formed to secure a carrier discharge path, so that the potential variation of the floating layer can be suppressed.

In addition, by increasing the thickness of the insulating film50such as PSG and SOG, the parasitic MOS81formed in the opening25of the gate resistance20and the capacitance of the emitter wiring30on the gate resistance20can be suppressed from increasing. Note that the p-type diffusion layer below the gate pad40can suppress the variation of the floating potential by connecting to the emitter potential.

Next, the results of confirming the capacitance reduction effects by floating isolation using simulations (TCAD) will be described. A conventional structure (referred to as a structure A) in which a capacitance is added below the gate resistance20without separating the p-type diffusion layer below the gate resistance20, and a structure (referred to as a structure B) in which the p-type diffusion layer below the gate resistance20is separated and the p-type diffusion layer is floated are compared. According to this, it was confirmed that the capacity drastically decreased in the case of the structure B.

The effect on the switching characteristics will be described with reference to the results of the verification performed by the circuit simulation. The verification method used is a general L load switching circuit and is a double pulse test. According to this, in the case of the conventional structure A, which has a Rgintparallel capacitance, the gate waveform greatly vibrates on the turn-on side of the structure A. Similarly, vibration of the gate waveform was also confirmed on the turn-off side. It is considered that the capacitance acts as a path at the time of the gate charge, and causes a speed change and a gate vibration.

From this, it is confirmed that there are two factors that cause imbalance, which is a problem of the conventional structure A. One is to vary the gate resistance, i.e. to reduce the gate resistance. The other is that the capacity acts as a path. In order to stabilize the switching, it is necessary to eliminate the above-mentioned factors. In the structure B in which the p-type diffusion layer of the present embodiment is made floating, it is possible to suppress the change of the switching speed and the gate vibration and to perform stable switching.

Although each embodiment has been described above, the present invention is not limited to the above-described form, and can be changed within a range not deviating from the technical idea. Also, a semiconductor device in which the configurations of the first to sixth embodiments are combined is within the scope of the technical idea.