Dynamic power supply switching for clocking signals

In an integrated circuit having input circuitry whose positive and/or negative input signals are gated by one or more clocked input switches, the switch clock signal CLK_SW used to clock the input switch(es) is automatically generated based on the higher of the IC's power supply voltage VDD and the positive input signal voltage Vplus. In one embodiment, a clock level shifter shifts an input clock signal CLK_VDD from the VDD voltage domain to generate a level-shifted clock signal CLK_VPLUS in the Vplus voltage domain. Based on a control signal VSEL, a clock selector selects either the input clock signal or the level-shifted clock signal to be the switch clock signal. An over-voltage detector generates both the logic state and the voltage domain of the control signal based on the higher of VDD and Vplus, such that the input switches are appropriately clocked even during over-voltage conditions in which Vplus>VDD.

BACKGROUND

The present disclosure relates to electronic circuitry and, more specifically but not exclusively, to operating circuitry during over-voltage conditions.

2. Description of the Related Art

FIG. 1is a simplified block diagram of a portion of a prior-art integrated circuit (IC)100. As shown inFIG. 1, integrated circuit100provides two exemplary circuit functions: (i) analog signal processing implemented by an analog amplifier104and a signal processing circuit106and (ii) analog signal measurement for out-of-range voltage detection that triggers an alarm implemented by comparator108and flip-flop110, all of which are powered by a local (i.e., on-chip) power supply consisting of a positive power supply voltage VDD and a negative power supply voltage (i.e., ground reference voltage) GND. The two exemplary circuit functions are driven by a differential analog input signal consisting of a positive input signal Vplus and a negative input signal Vminus that are applied to two IC input nodes, which can also be respectively referred to by the labels Vplus and Vminus. Application of the input signals Vplus and Vminus, as well as a reference signal Vtrip, to the two exemplary circuit functions is controlled by a set of clock-driven switches102driven by clock signal CLK. In other words, the two exemplary circuit functions are gated by the clocked switches102. The rest of the details of these two exemplary circuit functions are not important for the present disclosure.

In many applications, the voltage levels of the input signals Vplus and Vminus stay within the supply voltage range for the IC. That is, the positive input signal voltage Vplus is always less than or equal to the positive supply voltage VDD, and the negative input signal voltage Vminus is always greater than or equal to the negative supply voltage GND. There are, however, applications that require handling voltages in excess of the IC supply voltage range. Handling voltages which exceed the IC supply voltage range usually require some special circuit techniques unless the signals can simply be divided down using a resistor divider to within the IC supply voltage range. Where dividers are not appropriate, e.g., when the input voltages can vary significantly and dynamically, such as from GND up to twice or more of the IC supply voltage VDD, circuit functions such as precision analog measurement present a challenge.

DETAILED DESCRIPTION

Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Embodiments of the present invention may be embodied in many alternative forms and should not be construed as limited to only the embodiments set forth herein. Further, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention.

One approach to handling signal voltages above the IC power supply is to use switched-capacitor (S-C) circuits where an input capacitor structure sustains the average voltage in order to (i) maintain the actual voltages applied at IC MOSFET gates in critical analog circuits, such as amplifiers and comparators, to within the desired voltage range for performance or (ii) prevent these devices from being overstressed by the high external voltage, or both. S-C circuits operate on clock signals or phases that turn on and turn off various switches in the circuit to perform analog circuit functions using well-known circuit techniques, such as those represented inFIG. 1. This requires the S-C clock voltage level to be equal to the highest input signal level in order to shut off PMOS transistors, which is never a problem for input voltages between VDD and GND.

However, internally generated clocks in the IC have a voltage swing limited by the supplies, i.e., GND to VDD. Where the input signal voltages can vary significantly, the S-C switches include both PMOS and NMOS transistors. PMOS switches are most efficient at voltages near VDD or at least well above GND, and NMOS switches are most efficient at voltages near GND or at least well below VDD, so the combination provides low-impedance conduction over the full voltage range. The clocks driving these transistors must apply a voltage range at the switches which will (i) enable low-impedance conduction when turned on and (ii) also turn off the switches completely when they are not to conduct. Level shifters can be used to translate signals from VDD to higher voltage levels if a low-impedance voltage source is available to power the level shifter, but they do not always work well over a wide voltage range. In particular, when the input signal is at a low voltage level, near GND for example, the level-shifted clock signals fail to provide the voltage needed for adequate switch conduction.

Switching between clock signals, one powered by VDD and another by a higher voltage equal to or greater than Vplus (it can be Vplus if the signal is low impedance) can solve this problem, but the switchover can create timing anomalies if any clock edges occur during a switchover between clock sources. This can result in clock-transition delays which may degrade performance. The embodiments described below address all of these issues.

By minimizing the loading on the positive input signal Vplus, this signal can be used as an alternative supply voltage for clocking input MOSFET switches. Applying Vplus to only a minimal load allows the signal to be used as a voltage source without degradation of analog measurements where the input signal is of sufficiently low impedance. In alternative embodiments, if available, a second supply associated with the input signal can be used as the alternative supply voltage instead of Vplus itself. For example, the second supply could be an external power supply that powers the external circuitry that generates Vplus.

FIG. 2is a simplified block diagram of a portion of an integrated circuit200according to one embodiment of the present disclosure. Analogous to integrated circuit100ofFIG. 1, the application of input signals Vplus and Vminus (as well as reference signal Vtrip) to input circuitry210is gated by clocked input switches208, which are driven by switch clock signal CLK_SW. When implemented using FET devices, input switches208have threshold voltages much greater than the error band for sensing a supply voltage switching event, which makes the switches transparent to MOSFET operation, even in the unlikely occurrence of supply switching during a clock phase transition.

Note that, although not always explicitly represented as such, the clock signals described in this specification are differential clock signals comprising a true clock phase and a complement clock phase.

Depending on the particular implementation, input circuitry210can perform analog signal processing and/or analog signal measurement analogous to the corresponding circuit functions inFIG. 1and/or any other appropriate circuit functions.

Switch clock signal CLK_SW is provided to input switches208by clock selector206, which selects switch clock signal CLK_SW to be either (i) input clock signal CLK_VDD or (ii) level-shifted clock signal CLK_VPLUS generated by clock level shifter204, where the selection by clock selector206is based on a control signal VSEL generated by over-voltage detector202.

Input clock signal CLK_VDD, which may be generated on-chip, is within the voltage domain of power supply VDD. Clock level shifter204level shifts input clock signal CLK_VDD from the VDD voltage domain to the voltage domain of the positive input signal Vplus to generate level-shifted clock signal CLK_VPLUS. Both clock signals are applied to clock selector206. Clock level shifter204is designed to switch the clock phase supply voltage directly at the driver stages to drive FET switches208without glitching that can otherwise upset proper sampling operation. Since the supply source selection is integrated into the driving stage, PMOS switch turn on and NMOS switch turn off are completely independent of supply switching transients. In addition, since, at the point of supply switching, the two supplies are at or very near the same voltage, switching anomalies that may be present in other designs are eliminated.

In one implementation, clock level shifter204, designed to implement the switching directly at the output stage, works efficiently whenever the voltage difference is more than 10 mV. The importance of switching directly at the output stage is that (1) switching delays are eliminated, which could otherwise allow for signal glitches that behave as runt clock signals, and (2) neither dead time (when neither drive path is enabled) nor driver contention (when both paths are enabled) are possible.

Over-voltage detector202compares the positive power supply voltage VDD to the positive input signal voltage Vplus to generate control signal VSEL. In one implementation, when over-voltage detector202detects that Vplus is less than VDD, over-voltage detector202drives control signal VSEL low to indicate that a normal operating condition exists. When over-voltage detector202detects that Vplus is greater than VDD, over-voltage detector202drives control signal VSEL high to indicate that an over-voltage condition exists. Note that, in addition to generating the logic state of the control signal VSEL based on the higher of VDD and Vplus, over-voltage generator202also sets the voltage domain of the control signal VSEL based on the higher of VDD and Vplus.

In one implementation, over-voltage detector202responds to supply differences of less than 10 mV for a 6-sigma offset error window to assure that the higher supply is active at the clock buffers. This voltage is well below the voltage required for conduction in input switches208, so, during the switching of supplies, no MOS switches are allowed to conduct improperly.

Hysteresis in over-voltage detector202eliminates continual chatter at the sense output when the two supplies are equal or nearly equal with noise. This hysteresis results from a low-current design that results in a slow response for nearly identical supply source inputs, but a fast response for large voltage differences, so that continual chatter is eliminated.

When control signal VSEL is low (i.e., normal operating condition), clock selector206selects the input clock signal CLK_VDD to be the switch clock signal CLK_SW used to drive input switches208. When control signal VSEL is high (i.e., over-voltage condition), clock selector206selects the level-shifted clock signal CLK_VPLUS to be the switch clock signal CLK_SW used to drive input switches208.

FIG. 3is a simplified block diagram of one possible implementation of over-voltage detector202ofFIG. 2. A pair of matched voltage dividers302divide both the power supply voltage VDD and the positive input voltage Vplus by the same divisor to generate divided voltage signals VDD_in and VP_in, respectively.

Gain-stage circuitry304, which includes a Schmidt trigger, generates the logic states of VDD-voltage-domain intermediate signals vselb and voutb based on the divided signals VDD_in and VP_in. In particular, when VDD_in is greater than VP_in (i.e., normal operating condition), gain-stage circuitry304drives signal vselb high (i.e., VDD) and signal voutb low (i.e., ground). When VP_in is greater than VDD_in (i.e., over-voltage condition), gain-stage circuitry304drives signal vselb low (i.e., GND) and signal voutb high (i.e., VDD). Gain-stage circuitry304is designed with low offset error enhanced by some voltage gain due to FET body bias effects and with output hysteresis to eliminate continual chatter for essentially equal voltages. Note that the voltage domain of intermediate signals vselb and voutb is the VDD voltage domain.

Dual-supply level shifter306generates true and complementary (aka false) components vsel and vselb of the control signal VSEL bfrom the intermediate signals vselb and voutb received from gain-stage circuitry304, where the voltage domain for the control signals vsel and vselb is based on the greater of the power supply voltage VDD and the positive input voltage Vplus. Thus, if VDD is greater than Vplus, then dual-supply level shifter306generates the control signals vsel and vselb in the VDD voltage domain. If Vplus is greater than VDD, then dual-supply level shifter306generates the control signals vsel and vselb in the Vplus voltage domain.

At the output of gain-stage circuitry304, differential, dual-supply level shifter306provides both true and complementary control signals vsel and vselb for both clock buffer supply sources. The output design of the single differential level shifter306ensures that supply switching is completely and tightly synchronized for the supply being enabled and the supply being disabled, which guarantees that both cannot be enabled at the same time, even briefly, to eliminate supply switching current feedthrough between supplies.

FIG. 4is a simplified block diagram of one possible implementation of clock selector206ofFIG. 2. Clock selector206has four tri-state inverters402-408configured to operate as output buffers. Tri-state inverters402and404respectively receive the inverted phases of level-shifted clock signal CLK_VPLUS (i.e., CLK_VPLUS_b) and input clock signal CLK_VDD (i.e., CLK_VDD_b) and together generate the non-inverted phase of switch clock signal CLK_SW (i.e., CLK_SW_a). Similarly, tri-state inverters406and408respectively receive the non-inverted phases of level-shifted clock signal CLK_VPLUS (i.e., CLK_VPLUS_a) and input clock signal CLK_VDD (i.e., CLK_VDD_a) and together generate the inverted phase of switch clock signal CLK_SW (i.e., CLK_SW_b).

As indicated inFIG. 4, tri-state inverters402and406are powered by the positive input signal Vplus, while tri-state inverters404and408are powered by the power supply voltage VDD. The control signals vsel and vselb are applied to all four tri-state inverters.

When vsel is low and vselb is high (indicating a normal operating condition), tri-state inverters402and406are tri-stated (i.e., disabled), and tri-state inverters404and408operate to generate both phases of switch clock signal CLK_SW in the VDD voltage domain based on input clock signal CLK_VDD. When vsel is high and vselb is low (indicating an over-voltage condition), tri-state inverters404and408are tri-stated, and tri-state inverters402and406operate to generate both phases of switch clock signal CLK_SW in the Vplus voltage domain based on level-shifted clock signal CLK_VPLUS.

FIGS. 5,7, and8are schematic circuit diagrams corresponding to one possible implementation of the different components of integrated circuit200shown inFIG. 2. In particular,FIG. 5is a schematic circuit diagram of over-voltage detector202,FIG. 7is a schematic circuit diagram of clock level shifter204and clock selector206, andFIG. 8is a schematic circuit diagram of input switches208and input circuitry210.

Referring toFIG. 5, transistors P3, I25, I41, and I28form the voltage divider of matched voltage dividers302ofFIG. 3that generates the divided voltage signal VDD_in from the power supply voltage VDD, while transistors P4, I26, I42, and I27form the other voltage divider of matched voltage dividers302that generates the divided voltage signal VP_in from the positive input signal Vplus.

Block508ofFIG. 5is a common bulk (e.g., n-well) bias voltage generator that generates a bulk bias voltage flnw that (i) is equal to the higher of VDD and Vplus and (ii) is applied to the bulk of each of the eight transistors in the pair of matched voltage dividers302. Because all eight transistors share a common bulk bias voltage, they can all be implemented physically closer to each other in the integrated circuit layout, thereby improving the similarity of the divisors applied by the two matched voltage dividers.

This shared n-well structure provides a secondary advantage: Setting the bulk bias voltage flnw at the higher of the two supplies will back-bias or pinch the current flow in the divider string tied to the lower supply. This effect reduces the input to the gain-stage circuitry304at the lower supply sensed. The effect is to enhance the differential voltage sensed by differential pair N9/N10and provide some measure of noise immunity from internal coupling into sensitive device nodes to reduce the potential for erroneous switching in high-noise environments.

FIG. 6is a schematic circuit diagram of common bulk bias generator508ofFIG. 5, which includes a pair of low-threshold PMOS devices I0and I1, cross-connected to pass the higher of the two applied voltages VDD and Vplus. When power supply voltage VDD is greater than positive input signal voltage Vplus, transistor I0is on and transistor I1is off, which drives bulk bias voltage flnw to VDD. When positive input signal voltage Vplus is greater than power supply voltage VDD, transistor I0is off and transistor I1is on, which drives bulk bias voltage flnw to Vplus. Note that the bulk bias voltage flnw is also applied to the bulks of transistors I0and I1.

Transistors P9, P10, N9, N10, and I29form a voltage gain stage502of gain-stage circuitry304ofFIG. 3, while transistors P16, P17, P11, N14, N19, and N18and inverter transistors I39and I40form Schmidt trigger504of gain-stage circuitry304, which outputs VDD-voltage-domain intermediate signal voutb. Schmidt trigger504is a standard Schmidt trigger implementation, but with a large hysteresis. The large hysteresis enables dynamic switching as the monitored voltage varies, while eliminating “chatter” (output oscillations due to noise differential between the device supply voltage VDD and the monitored voltage Vplus).

When the power supply voltage VDD is greater than the input voltage Vplus, then the divided voltage VDD_in is greater than the divided voltage VP_in. In this case, the drain current of device N10is greater than the drain current of device N9. The N9drain current equals the P9drain current, which gets mirrored as the P10drain current, which is therefore less than the N10drain current. As a result, node “amp” is pulled toward GND. When the node “amp” voltage drops sufficiently, currents in devices N18and N14are reduced, and the node “vout” begins to move up from GND. As soon as the gate-source voltage across device N19is sufficient to conduct current, device N14loses current equal to that taken by device N19, which drives node “vout” even higher in a positive feedback mechanism which results in device N19taking all of the N18current to ensure that the “vout” node rises to VDD. PMOS transistors P16and P11conduct current to pull “vout” to VDD. This is the well-known Schmidt Trigger mechanism.

If the input voltage Vplus rises to greater than the supply voltage VDD, then the N9drain current becomes greater than the N10drain current. The N9drain current is mirrored so that the P10drain current exceeds the N10drain current, and node “amp” rises to VDD. When the node “amp” voltage rises sufficiently, the gate-source voltages across devices P11and P16are reduced, and device N14begins to conduct current. When the node “amp” voltage rises further, the N14drain current pulls node “vout” below VDD, and eventually device P17begins to conduct, thus starving device P11of current, and the Schmidt Trigger positive feedback works in the opposite direction as before. As device P17starves device P11and “vout” falls towards GND, the N19gate-source voltage drops so that eventually all of the N18current passes through device N14to pull node “vout” to GND.

Gain-stage circuitry304also includes transistors I37and I38, which form an inverter506that outputs VDD-voltage-domain intermediate signal vselb. Inverter506provides switching speed that insures that the control signals vsel and vselb switch simultaneously.

Transistors I35, I33, I32, I34, I30, and I31form dual-supply level shifter306ofFIG. 3, which converts the VDD-voltage-domain intermediate signals voutb and vselb into true and complementary control signals vsel and vselb. Dual-supply level shifter306is a single differential buffer, half biased on the supply voltage VDD and half biased on the monitored supply Vplus. The side of the differential buffer which is in a logical high state switches supply depending on which supply is greater. The high-state logic is explained in two cases.

In the first case of an over-voltage condition, the monitored supply voltage Vplus is greater than the IC supply voltage VDD. In that case, the control signal vsel is driven to the monitored supply voltage Vplus, which provides the correct logical high state for the active supply, while the complementary control signal vselb is driven to the negative supply voltage GND, which is common to both supplies.

In the second case of a normal operating condition, the IC supply VDD greater than the monitored supply Vplus. In that case, the control signal vsel is driven to GND, while complementary control signal vselb is driven to the IC supply voltage VDD, which provides the logical high state for the active supply.

Note that, when VDD is greater than Vplus, gain-stage circuitry304drives intermediate signal vselb to VDD, which is also the appropriate voltage level for the complementary control signal vselb. When Vplus is greater than VDD, gain-stage circuitry304drives intermediate signal vselb to GND, which is also the appropriate voltage level for the complementary control signal vselb, since GND is the negative voltage level for both the VDD voltage domain and the Vplus voltage domain. That is why the intermediate signal vselb can be passed through dual-supply level shifter306without ever going through any level shifting (during both normal operating conditions and over-voltage conditions) to be presented as the complementary control signal vselb.

Referring toFIG. 7, transistors P1, P2, N1, and N2form clock level shifter204ofFIG. 2, which generates Vplus-voltage-domain, level-shifted clock signal CLK_VPLUS from VDD-voltage-domain, input clock signal CLK_VDD. Input clock phases CLK_VDD_a and CLK_VDD_b (biased by positive supply VDD and negative supply GND) drive clock level shifter204with the sources of transistors P1and P2connected to the monitored supply voltage Vplus.

Input clock phases CLK_VDD_a and CLK_VDD_b form a differential signal pair. When CLK_VDD_a rises and CLK_VDD-b falls, device N2conducts current, and device N1is shut off. Device N2pulls the signal node CLK_VPLUS_b to GND, which pulls the gate of device P1low, so that device P1conducts to pull signal node CLK_VPLUS_a to the voltage at Vplus. Conversely, when the input clocks switch state, the signal node CLK_VPLUS_b is driven to the voltage at Vplus, and the signal node CLK_VPLUS_b is driven to GND.

When the input signal Vplus is a very small voltage, such as 200 mV, the gate-source voltages applied to the appropriate PMOS device, P1or P2, might not be sufficient to enable current conduction. It is important to recognize that this apparent failure is not an issue, because the input voltage Vplus will not be the selected voltage, because the select circuit of FIG. E will have node vsel driven to GND and vselb driven to VDD, so the selected clock signal is CLK_VDD, and the voltages at nodes CLK_VPLUS_a and CLK_VPLUS_b are deselected.

The rest ofFIG. 7corresponds to clock selector206ofFIG. 2, which comprises the four tri-state inverters402-408ofFIG. 4. Input clock CLK_VDD drives tri-state inverters404and408, biased from the IC supply voltage VDD, while level-shifted clock signal CLK_VPLUS generated by clock level shifter204drives tri-state inverters402and406, biased from the monitored supply voltage Vplus.

In particular, transistors P3, P4, N3, and N4form tri-state inverter402ofFIG. 4, which generates the non-inverted phase CLK_SW_a of switch clock CLK_SW from the inverted phase CLK_VPLUS_b of the level-shifted clock signal CLK_VPLUS during over-voltage conditions. Transistors P5, P6, N5, and N6form tri-state inverter404ofFIG. 4, which generates the non-inverted phase CLK_SW_a of switch clock CLK_SW from the inverted phase CLK_VDD_b of the input clock signal CLK_VDD during normal operating conditions.

Transistors P7, P8, N7, and N8form tri-state inverter406ofFIG. 4, which generates the inverted phase CLK_SW_b of switch clock CLK_SW from the non-inverted phase CLK_VPLUS_a of the level-shifted clock signal CLK_VPLUS during over-voltage conditions. Transistors P9, P10, N9, and N10form tri-state inverter408ofFIG. 4, which generates the inverted phase CLK_SW_b of switch clock CLK_SW from the non-inverted phase CLK_VDD_a of the input clock signal CLK_VDD during normal operating conditions.

Tri-state inverters402and404have a common output node CLK_SW_a, while tri-state inverters406and408have their own common output node CLK_SW_b. PMOS devices P4, P6, P8, and P10are placed in a common n-well controlled by bulk bias voltage generator I30with the common n-well node fnw, biased at the higher of the two voltages VDD and Vplus, which enables complete shutoff of the inactive buffer devices. Depending on the implementation, bulk bias voltage generator I30may be a second instance of the bulk bias voltage generator ofFIG. 6or the same instance may be used to generate both bulk bias voltage flnw ofFIG. 5and bulk bias voltage fnw ofFIG. 7. Note that flnw and fnw are both abbreviations for “floating n-well,” because the n-well voltages will float to the higher of the two voltage sources applied.

When the IC supply voltage VDD is greater than the monitored voltage Vplus, the voltage at node fnw is the IC supply voltage VDD, and the control signals vsel and vselb are GND and VDD, respectively. Therefore, devices P4and P8have their gate voltages equal to their bulk (n-well) voltage, with neither source nor drain capable of a higher voltage, so they are disabled. Devices P6and P10have their gate voltages tied to GND, or zero volts, so they are enabled. In a similar manner, devices N5and N9have their gate voltages at VDD and are enabled, so tri-state inverters404and408biased by supply VDD are active. Devices N3and N7have their gate voltages at GDN, so they are disabled.

When the input signal voltage Vplus is greater than the IC supply voltage VDD, the voltage at node fnw is at the input signal voltage Vplus, and the control signals vsel and vselb are Vplus and GND, respectively. Now, devices P4and P8have their gate voltages tied to GND, so they are enabled. Devices P6and P10have their gate voltages tied to Vplus, which is also their bulk (n-well) voltage, so they are disabled. In a similar manner, devices N5and N9have their gates tied to GND and are disabled, while devices N3and N7have gate voltages at Vplus, so they are active.

When supply VDD and supply Vplus are equal, the hysteresis in Schmidt trigger504ofFIG. 5ensures that the control signals vsel and vselb are at valid logic states and not intermediate voltages. Noise and other factors may result in occasional switching of states at nodes vsel and vselb, but, except for the sub-nanosecond switching time, the control signals vsel and vselb are always in valid logic states of either ‘0’ or ‘1’, where ‘0’ is GND, and ‘1’ is the selected higher voltage of supply voltage VDD and supply voltage Vplus.

When the supplies are equal, then it does not matter which tri-state inverters conduct and which tri-state inverters are disabled, because the output signal being driven high is being driven to the same voltage from either side. The output signals being driven low are not affected by any switchover so PMOS switch enable and NMOS switch disable are not impacted.

FIG. 8is an exemplary circuit implementation of clocked input switches208and input circuitry210ofFIG. 2for an amplifier analogous to analog amplifier104ofFIG. 1with corresponding input switches102. In particular, switch blocks802and804form clocked input switches208ofFIG. 2, which are analogous to input switches102ofFIG. 1. Details of these blocks, which are switched-capacitor input switches plus storage capacitors, are shown inFIG. 9. The rest of the elements shown inFIG. 8, including amplifier806, form an exemplary embodiment of input circuitry210ofFIG. 2that is analogous to analog amplifier104ofFIG. 1.

Switch block802receives input signals VPLUSand VMINUSand outputs switched input signal cinm, which gets applied to the negative input inn of amplifier806, while switch block804receives input signals VPLUSand VMINUSand outputs switched input signal cinp, which gets applied to the positive input inp of amplifier806. Note that cinm and cinp are complementary signals due to the fact that the input signals VPLUSand VMINUSare flipped for switch block804relative to switch block802. The timing of both switch blocks802and804is based on switch clock phases CLK_SW_a and CLK_SW_b. nwell is an n-well bias voltage for switch blocks802and804, while Vcm is the common-mode voltage midway between VPLUSand VMINUS.

Amplifier806and its feedback capacitor networks contain all the critical timing and charge transfer timing requirements for accuracy. An input sub-circuit, formed by devices I76and I91, samples the switched input signals cinm and cinp, but the timing is delayed such that the sub-circuit's transitions do not overlap the amplifier's critical timing, so that no charge errors occur.

Implementing an input switched-capacitor circuit running on clocks that switch supplies and using the input capacitors to isolate the remaining circuits from supply changes enables the monitoring functions to do all critical timing functions on the IC supply voltage, with only input signal sampling done with the input switching MOSFETs and input capacitance structure. The rest of the details of exemplary input circuitry210shown inFIG. 8are not important for the present disclosure.

FIG. 9is a schematic circuit diagram of switch circuitry900, which can be used to implement each of switch blocks802and804ofFIG. 8. Inputs CLK_SW_a and CLK_SW_b are the clock signals that control input switch pairs MP2/I0and I2/I3. When CLK_SW_a is high and CLK_SW_b is low, the input v2is selected to apply a voltage at node cmim of the storage capacitor CIA. When the clock signals reverse state, input v1is selected to apply a voltage at node cmim. When switch circuitry900is used to implement switch block802ofFIG. 8, inputs v1and v2are input signals VMINUSand VPLUS, respectively, and output v3is switched input signal cinm. On the other hand, when switch circuitry900is used to implement switch block804ofFIG. 8, inputs v1and v2are input signals VPLUSand VMINUS, respectively, and output v3is switched input signal cinp. Bias generator902generates the n-well bias voltage for devices MP2and I3in a manner analogous to bias generator508ofFIG. 6.

Although the disclosure has been described in the context of a specific switched-capacitor implementation, the invention is not so limited. In general, the invention can be used with any circuit architecture in which input switches are used, including, for example, chopper-stabilized amplifiers designed to handle inputs above the IC supply voltage or communications links between devices either at different power supplies or with common-mode noise which potentially results in input voltages exceeding the IC supply voltage.

The disclosure can be applied to switched-capacitor circuit designs that perform current-monitoring functions that are directly tied to the IC inputs. Switched-capacitor inputs are used to protect sensitive internal amplifiers from voltages exceeding the IC supply voltage. The input switches of these circuits operate at the monitored voltage in order to control the PMOS switches when the monitored voltage exceeds the IC supply voltage.

The present disclosure enables analog measurement and signal processing of a small signal with a dynamically changing common-mode voltage range from zero volts (GND) to voltages well in excess of the power supply (VDD) of the IC that performs these functions with one or more of the following capabilities:

(1) Accurate measurement of a low-level differential signal (in the 1-100 mV range) for an input common mode level anywhere from GND to greater than VDD, possibly even more than twice VDD.

(2) When the monitored input voltage is less than the IC power supply voltage, the input circuitry operates on the IC power supply to provide sufficient drive to operate the input switching MOSFETs or performance degrades to unacceptable levels.

(3) When the monitored input voltage is greater than the IC power supply voltage, the input circuitry operates on the monitored signal to control input switching MOSFETs, because the PMOS switch devices must have body connection to the highest voltage to avoid parasitic conduction from device source to well, which bypasses the device and may cause latchup.

(4) Monitored input is assumed to vary dynamically below and above the IC power supply, with no ability to control such common-mode behavior.

(5) Although clock supply switching can occur during normal operation at critical timing edges, the circuit functions properly and meets design specifications even if the supply switching occurs in the middle of clock transitions.

Embodiments of the invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi chip module, a single card, or a multi card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro controller, general purpose computer, or other processor.

Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources.

Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here.

Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors.

As used in this specification and claims, the term “channel node” refers generically to either the source or drain of a metal oxide semiconductor (MOS) transistor device (also referred to as a MOSFET), and the term “control node” refers generically to the gate of the MOSFET. Similarly, as used in the claims, the terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bi polar device when an embodiment of the invention is implemented using bi-polar transistor technology.

It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims.

The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non enabled embodiments and embodiments that correspond to non statutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.