Memory and memory system

A memory includes a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller.

BACKGROUND

Various embodiments of the present invention relate to a memory and a memory system.

2. Description of the Related Art

As the degree of integration of memories increases, the gap between a plurality of word lines included in a memory decreases. As the gap between the word lines decreases, the coupling effect between the neighboring word lines increases.

Whenever data is inputted to or outputted from a memory cell, a word line toggles between an inactive state and an active state. The increased coupling effect between the neighboring word lines may cause damage to data of the memory cells coupled to a word line which is adjacent to a frequently activated word line. This phenomenon is called row hammering or word line disturbance, which is a problem because data of a memory cell is damaged before the memory cell is refreshed.

FIG. 1is a schematic view illustrating the row hammering phenomenon.FIG. 1shows a part of a cell array included in a memory device.

InFIG. 1, ‘WLL’ may denote a word line with excessive activation times, which may be referred to as a frequently activated word line, and ‘WLL−1’ and ‘WLL+1’ may denote word lines disposed adjacent to the frequently activated word line WLL, which may be referred to as neighboring word lines. ‘CL’ may denote a memory cell coupled to the frequently activated word line WLL, and ‘CL−1’ may denote a memory cell coupled to the neighboring word line WLL−1, and ‘CL+1’ may denote a memory cell coupled to the neighboring word line WLL+1. The memory cells CL, CL−1, and CL+1 may include cell transistors TL, TL−1, and TL+1 and cell capacitors CAPL, CAPL−1, and CAPL+1, respectively.

InFIG. 1, when the frequently activated word line WLL is activated or deactivated, the voltages of neighboring word lines WLL−1 and WLL+1 may increase or decrease due to the coupling effect between the adjacent word lines WLL, WLL−1 and WLL+1, affecting the amount of charges of the cell capacitors CL−1 and CL+1.

Therefore, when the frequently activated word line WLL toggles between an inactive state and an active state, the amount of charges stored in the cell capacitors CAPL−1 and CAPL+1 included in the memory cells CL−1 and CL+1 may be changed and the data of the memory cells may be deteriorated.

Also, the electromagnetic wave generated as a word line toggles between the inactive state and the active state may damage data by charging or discharging electrons into or out of a cell capacitor of the memory cell coupled to a neighboring word line.

A method for improving the row hammering phenomenon may include detecting a row (i.e., a word line) that is activated excessive times and additionally refreshing the rows disposed adjacent to the row that is activated excessive times. Such an additional refresh operation may be generally performed hidden when a typical refresh operation is performed. For example, whenever a refresh command is applied to a memory N times, where N is an integer equal to or greater than 1, the memory may perform an additional refresh operation hidden without the memory controller knowing, in addition to a typical refresh operation.

Recently, a study on a cryogenic memory which operates at a cryogenic temperature has been conducted. At a cryogenic temperature, charges are scarcely discharged from the cell capacitor of a memory, so a refresh operation may be rarely performed or may not be performed at all. That is, since the data retention time of the memory cell is greatly increased at the cryogenic temperature, a refresh command may be rarely applied to the memory, compared to ordinary memories. However, even in a cryogenic memory, data loss due to the row hammering may occur. Therefore, the refresh command being rarely applied to the memory may inevitably decrease the number of the additional refresh operations performed in the memory, which is problematic.

SUMMARY

Embodiments of the present invention are directed to a technology for refreshing rows that need to be refreshed due to a row hammering phenomenon.

In accordance with an embodiment of the present invention, a memory includes: a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller.

In accordance with another embodiment of the present invention, a memory system includes: a memory controller; and a memory, wherein the memory includes: a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller, wherein the memory controller is suitable for transferring a command for refreshing the target rows to the memory when the information is received from the memory.

In accordance with yet another embodiment of the present invention, a memory system includes: a memory controller; and a memory, wherein the memory includes: a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller, wherein the memory controller is suitable for applying no command to the memory in a predetermined period after the information is received from the memory.

In accordance with still another embodiment of the present invention, a method for operating a memory system including a memory controller and a memory includes: determining, by the memory, a row that is likely to lose data among a plurality of rows as a target row; determining, by the memory, whether a number of target rows reaches a threshold value or not; and transferring, by the memory, information representing that the number of the target rows reaches the threshold value to the memory controller.

In accordance with still another embodiment of the present invention, a method for operating a memory system including a memory controller and a memory includes: determining, as a target row, a neighboring row disposed adjacent to a row with excessive activation times; checking whether a number of target rows reaches a threshold value or not; informing a memory controller when the number of the target rows reaches the threshold value; and performing a refresh operation on the target rows.

DETAILED DESCRIPTION

It is noted that reference to “an embodiment,” “another embodiment” or the like does not necessarily mean only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s).

As used herein, singular forms may include the plural forms as well and vice versa, unless the context clearly indicates otherwise.

The articles ‘a’ and ‘an’ as used in this application and the appended claims should generally be construed to mean ‘one or more’ unless specified otherwise or it is clear from the context to be directed to a singular form.

FIG. 2is a block diagram illustrating a memory system200in accordance with an embodiment of the present invention.

Referring toFIG. 2, the memory system200may include a memory controller210and a memory220.

The memory controller210may control the operation of the memory220based on a request of a host HOST. The host HOST may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), and the like. The memory controller210may include a host interface211, a scheduler212, a command generator213, and a memory interface215. The memory controller210may be included in a CPU, GPU, AP, or the like. In this case, the host HOST may refer to a structure other than the memory controller210in this configuration. For example, when the memory controller210is included in a CPU, the host HOST shown in the drawing may represent constituent elements except the memory controller210in the CPU.

The host interface211may be an interface for communication between the host HOST and the memory controller210.

The scheduler212may determine the order of the requests to be directed to the memory220among the requests from the host HOST. In order to improve the performance of the memory220, the scheduler212may change the order that the requests are received from the host HOST and the order of the operations to be directed to the memory220. For example, although the host HOST requests for a read operation of the memory220first and then requests for a write operation subsequently, the scheduler212may be able to change the order of the requested operations such that the write operation is performed before the read operation.

The scheduler212may schedule a refresh operation between the operations requested from the host HOST to prevent the data of the memory220from being lost. When the memory system200operates in a cryogenic environment, the data retention time of the memory220may increases drastically. Therefore, in the cryogenic environment, the scheduler212may be able to schedule the refresh operation very rarely. For example, the scheduler212may schedule the refresh operation in such a manner that the memory cells of the memory220may be refreshed only once a day. Meanwhile, when information representing the number of rows classified as target rows reaches a threshold value is transferred from the memory220, that is, when information representing that the number of rows that are likely to lose their data due to the row hammering phenomenon is equal to or greater than the threshold value is transferred from the memory220, the scheduler212may schedule an additional refresh operation to prevent the data from being lost.

The command generator213may generate a command to be applied to the memory220according to the order of the operations that are determined by the scheduler212.

The memory interface215may be an interface between the memory controller210and the memory device220. A command CMD and an address ADD may be transferred from the memory controller210to the memory220through the memory interface215, and data DATA may be transferred/received. The memory interface215may also be referred to as a PHY interface.

The memory220may perform an operation directed by the memory controller210. The memory220may include a command receiving circuit221, an address receiving circuit222, a data transferring/receiving circuit223, a command decoder224, a target row determining circuit225, an address counter226, and a memory array227.

The command receiving circuit221may receive a command CMD transferred from the memory interface215of the memory controller210, and the address receiving circuit222may receive an address ADD transferred from the memory interface215of the memory controller210. The data transferring/receiving circuit223may receive data DATA transferred from the memory interface215during a write operation and transfer data DATA to the memory interface215during a read operation. The memory220may be provided with a plurality of command pads (not shown), a plurality of address pads (not shown), and a plurality of data pads (not shown). The command receiving circuit221may receive a command CMD through the command pads, and the address receiving circuit222may receive an address ADD through the address pads, and the data transferring/receiving circuit may transfer/receive data DATA through the data pads.

The command decoder224may decode the command CMD received through the command receiving circuit221to generate internal command signals. The internal command signals may include an active signal ACT, a precharge signal PCG, a read signal RD, a write signal WT, a refresh signal REF, and an additional refresh signal ADD_REF.

The target row determining circuit225may determine a row (i.e., a word line) that is likely to lose data among a plurality of rows of the memory array227as a target row. The target row determining circuit225may select a row disposed adjacent to a row that is activated excessive times as a target row based on the active signal ACT and the address ADD which is received through the address receiving circuit222. For example, when a fourth row is activated (i.e., accessed) excessive times, third and fifth rows that are adjacent to the fourth row may be selected as target rows. An additional refresh address ADD_REF_ADD outputted from the target row determining circuit215may be an address representing a target row. When the number of target rows is equal to or greater than a threshold value (e.g., 2), the target row determining circuit215may transfer information ADD_REF_REQ representing that the number of target rows reaches the threshold value, which is simply referred to as additional refresh operation requesting information, to the memory controller210through the data transferring/receiving circuit223.

The address counter226may change the refresh address REF_ADD whenever the refresh signal REF is activated. The refresh address REF_ADD generated in the address counter226may be used not for an additional refresh operation but for a normal refresh operation.

The memory array227may perform the operations directed by the internal command signals ACT, PCG, RD, WT, REF, and ADD_REF. In an additional refresh operation in which the additional refresh signal ADD_REF is activated, the memory array227may perform a refresh operation on the row selected by the target address (i.e., an additional refresh address) ADD_REF_ADD outputted from the target row determining circuit215. Also, in a refresh operation in which the refresh signal REF is activated, the memory array227may perform a refresh operation on the row selected by the refresh address REF_ADD. Also, the address ADD transferred from the memory controller210may be used during the active, read, and write operations of the memory array227. The memory array227may include constituent elements for the operations such as an active operation, a precharge operation, a read operation, a write operation, a refresh operation, and an additional refresh operation, such as a cell array, a row circuit for activating/deactivating rows of the cell array, a column circuit for inputting/outputting data to/from the cell array.

FIG. 3is a flowchart describing a method for operating the memory system200shown inFIG. 2in accordance with an embodiment of the present invention.

Referring toFIG. 3, in step S301, the target row determining circuit225of the memory220may determine a row that is likely to lose data as a target row. For example, the target row determining circuit225may determine the rows disposed adjacent to an excessively accessed row as target rows.

When the number of the target rows is equal to or greater than a threshold value (‘Yes’ in step S303), information ADD_REF_REQ representing the number of the target rows that are equal to or greater than the threshold value is activated, and this information ADD_REF_REQ may be transferred to the memory controller210through the data transferring/receiving circuit223in step S305. Here, although the information ADD_REF_REQ is illustrated to be transferred to the memory controller210through the data transferring/receiving circuit223inFIG. 2, those skilled in the art will recognize that the information ADD_REF_REQ may be transferred to the memory controller210through another route, for example, the information ADD_REF_REQ may be transferred to the memory controller210through another type of a pad. For reference, when the number of the target rows is less than a threshold value (‘No’ in step S303), the process proceeds back to the step S301.

When the information ADD_REF_REQ is transferred to the memory controller210through the data transferring/receiving circuit223, the information ADD_REF_REQ may be transferred in a period in which data DATA are not transferred between the memory controller210and the memory220. For example, since data DATA are not transferred between the memory controller210and the memory220during an active operation, the memory220may transfer the information ADD_REF_REQ to the memory controller210in a predetermined period after the active command is applied to the memory220.

The memory controller210may transfer an additional refresh command to the memory220in response to the information ADD_REF_REQ in step S307. The additional refresh command may be transferred to the memory220through a command CMD.

The command decoder224of the memory210may decode the command CMD to activate an additional refresh signal ADD_REF, and in response to the activated additional refresh signal ADD_REF, a target row designated by the target address ADD_REF_ADD may be refreshed in step S309. Herein, one or more target rows may be refreshed, and the refreshed target rows may no longer be target rows.

Subsequently, the process proceeds back to the step S301.

According to the operation method ofFIG. 3, when the number of target rows requiring an additional refresh operation in the memory220is equal to or greater than the threshold value, the memory220may transfer the information ADD_REF_REQ representing the number of target rows requiring an additional refresh operation in the memory220that are equal to or greater than the threshold value to the memory controller210. The memory controller210may then apply an additional refresh command to the memory220in response to the information ADD_REF_REQ, and the target rows in the memory210may be refreshed. Accordingly, even in a memory system in which a refresh operation is rarely performed, such as a cryogenic memory system, target rows required to be refreshed due to a row hammering phenomenon may be refreshed instantly.

FIG. 4is a flowchart describing a method for operating the memory system200shown inFIG. 2in accordance with another embodiment of the present invention.

Referring toFIG. 4, the operations of the steps S301, S303, and S305illustrated inFIG. 3may be performed in the same manner inFIG. 4(refer to S401, S403, and S405).

The memory controller210may transfer a refresh command to the memory220in response to the information ADD_REF_REQ in step S407. The refresh command may be transferred to the memory220through the command CMD.

The command decoder224of the memory220may decode the command CMD to activate a refresh signal REF, and in response to the activated refresh signal REF, a row designated by the refresh address REF_ADD may be refreshed. Also, a target row designated by a target address ADD_REF_ADD may be additionally refreshed in a refresh operation period in step S409. That is, the memory controller210may apply a refresh command to the memory220in response to the information ADD_REF_REQ, and the memory220may perform a general refresh operation and an additional refresh operation in a refresh operation period. When a refresh command is applied to the memory220, an additional refresh operation may be performed after the refresh operation is performed as the command decoder224activates the refresh signal REF and then activates the additional refresh signal ADD_REF.

Subsequently, the process proceeds back to the step S401.

According to the operation method ofFIG. 4, when the number of target rows requiring an additional refresh operation in the memory220is equal to or greater than the threshold value, the memory220may transfer the information ADD_REF_REQ representing the number of target rows requiring an additional refresh operation in the memory220that are equal to or greater than the threshold value to the memory controller210. Also, the memory controller210may apply a refresh command to the memory220in response to the information ADD_REF_REQ, and a refresh operation and an additional refresh operation may be performed in the memory220. Accordingly, even in a memory system in which a refresh operation is rarely performed, such as a cryogenic memory system, target rows required to be refreshed due to the row hammering phenomenon may be refreshed instantly.

FIG. 5is a flowchart describing a method for operating the memory system200shown inFIG. 2in accordance with yet another embodiment of the present invention.

Referring toFIG. 5, the operations of the steps S301, S303, and S305illustrated inFIG. 3may be performed in the same manner inFIG. 5(refer to S501, S503, and S505).

When the memory controller210receives the information ADD_REF_REQ, in step S507, the memory controller210may not apply any command to the memory220in a predetermined period after the information ADD_REF_REQ is received. That is, when the information ADD_REF_REQ is received, the memory controller210may not direct any operation to the memory220during the predetermined period.

The memory220may perform an additional refresh operation in a predetermined period after transferring the information ADD_REF_REQ to the memory controller210in step S509. Since no operation is to be directed to the memory220during the predetermined period, the memory220may be able to perform an additional refresh operation in the predetermined period. The target row determining circuit225may be able to transfer the activated information ADD_REF_REQ to the memory controller210through the data transferring/receiving circuit223and at the same time transfer the information ADD_REF_REQ to the command decoder224. The command decoder224may activate the additional refresh signal ADD_REF in response to the reception of the activated information ADD_REF_REQ and as a result, an additional refresh operation may be performed. When the additional refresh operation is performed, the refreshed target row may no longer be a target row.

Subsequently, the process proceeds back to the step S401.

According to the operation method ofFIG. 5, when the number of target rows requiring an additional refresh operation in the memory220is equal to or greater than a threshold value, the memory220may transfer information ADD_REF_REQ representing the number of target rows requiring an additional refresh operation in the memory220that are equal to or greater than the threshold value to the memory controller210. Then, the memory controller210may not apply any command to the memory220during a predetermined time in response to the information ADD_REF_REQ, and the memory220may perform an additional refresh operation during the predetermined time. Therefore, even in a memory system in which a refresh operation is rarely performed, such as a cryogenic memory system, target rows required to be refreshed due to the row hammering phenomenon may be refreshed instantly.

According to the embodiments of the present invention, rows that need to be refreshed due to the row hammering phenomenon may be refreshed.