SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

BACKGROUND

DETAILED DESCRIPTION

FIG.1throughFIG.11are cross-sectional views schematically illustrating a process flow for fabricating an SoIC component in accordance with some embodiments of the present disclosure.

Referring toFIG.1, a first carrier C1 including a bonding layer B1 formed on a top surface thereof is provided. The first carrier C1 may be a semiconductor wafer, and the bonding layer B1 may be a bonding layer prepared for fusion bond. In some embodiments, the bonding layer B1 is a deposited layer formed over the top surface of the first carrier C1. In some alternative embodiments, the bonding layer B1 is a portion of the first carrier C1 for fusion bond. For example, the material of the first carrier C1 includes silicon or other suitable semiconductor materials, and the material of the bonding layer B1 includes silicon (Si), silicon dioxide (SiO2) or other suitable bonding materials.

One or more semiconductor dies100(e.g., logic dies) are provided and placed on the top surface of the bonding layer B1. InFIG.1, only one semiconductor die100is illustrated, however, the number of the semiconductor die100is not limited. The semiconductor die100may include an active surface (i.e. front surface) and a back surface opposite to the active surface. The semiconductor die100is placed on the top surface of the bonding layer B1 such that the active surface of the semiconductor die100faces the bonding layer B1 carried by the first carrier C1. The semiconductor die100may include a bonding layer B2 formed on the active surface thereof. After the semiconductor die100is placed on the top surface of the bonding layer B1, the bonding layer B2 is in contact with the bonding layer B1. In an embodiment where multiple semiconductor dies are picked-up and placed on the bonding layer B1, the semiconductor dies may be placed onto the bonding layer B1 in a side-by-side manner such that semiconductor dies are arranged in array and spaced apart from each other. In some embodiments, the material of the bonding layer B2 includes silicon (Si), silicon dioxide (SiO2) or other suitable bonding materials.

The semiconductor die100may include a semiconductor substrate102having semiconductor devices formed therein, an interconnect structure104disposed on the semiconductor substrate102and electrically connected to semiconductor devices formed in the semiconductor substrate102, and a dielectric layer106covering the interconnect structure104. The dielectric layer106of the semiconductor die100is covered by the bonding layer B2. The semiconductor die100may further include through semiconductor vias (TSVs)103formed in the semiconductor substrate102and electrically connected to interconnect wirings of the interconnect structure104. As illustrated inFIG.1, the TSVs103are embedded in the semiconductor substrate102and the interconnect structure104, and the TSVs103are not revealed from the back surface of the semiconductor substrate102.

After the semiconductor die100is picked up and placed on the bonding layer B1, a chip-to-wafer fusion bonding process may be performed such that a fusion bonding interface is formed between the bonding layer B1 and the bonding layer B2. For example, the fusion bonding process for bonding the bonding layer B1 and the bonding layer B2 is performed at temperature ranging from about 100 Celsius degree to about 290 Celsius degree. The bonding layer B1 may be directly bonded to the bonding layer B2. In other words, there is no intermediate layer formed between the bonding layer B1 and the bonding layer B2. The above-mentioned fusion bonding interface formed between the bonding layer B1 and the bonding layer B2 may be a Si—Si fusion bonding interface, a Si—SiO2fusion bonding interface, a SiO2—SiO2fusion bonding interface or other suitable fusion bonding interface.

Referring toFIG.1andFIG.2, after the semiconductor die100is bonded to the first carrier C1 through the bonding layer B1 and the bonding layer B2, an insulating material is formed to cover the bonding layer B1, the bonding layer B2, and the semiconductor die100. In some embodiments, the insulating material is formed by an over-molding process or a film deposition process such that a portion of the top surface of the bonding layer B1, side surfaces of the bonding layer B2, and a back surface and side surfaces of the semiconductor die100are encapsulated by the insulating material. After performing the over-molding process or film deposition process, a grinding process may be performed to reduce the thickness of the insulating material and the thickness of the semiconductor die100such that semiconductor die100′ with reduced thickness and a first insulating encapsulation110are formed over the bonding layer B1. In some embodiments, the grinding process for reducing the thickness of the insulating material and the thickness of the semiconductor die100includes a mechanical grinding process, a chemical mechanical polishing (CMP) process, or combinations thereof.

As illustrated inFIG.2, in some embodiments, the thickness of the semiconductor die100′ is equal to the thickness of the first insulating encapsulation110, and the semiconductor die100′ and the bonding layer B2 are laterally encapsulated by the first insulating encapsulation110. In other words, the first insulating encapsulation110is merely in contact with the side surfaces of the semiconductor die100′ and the bonding layer B2, and back surface of the semiconductor substrate102′ is accessibly revealed from the first insulating encapsulation110. In some alternative embodiments, not illustrated inFIG.2, the thickness of the semiconductor die is slightly less than or greater than the thickness of the first insulating encapsulation due to polishing selectivity of the grinding process. In other words, the top surface of the first insulating encapsulation may be slightly higher than or slightly lower than the back surface of the semiconductor die.

Referring toFIG.3, a bonding structure120is formed over the back surface of the semiconductor die100′ and the revealed surface of the first insulating encapsulation110. In other words, the bonding structure120may entirely cover the back surface of the semiconductor substrate102′ and the revealed surface of the first insulating encapsulation110. The bonding structure120may include a dielectric layer120aand conductors120beach penetrating through the dielectric layer120a. The material of the dielectric layer120amay be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitirde (SiOxNy, where x>0 and y>0) or other suitable dielectric material, and the conductors120bmay be conductive vias (e.g., copper vias), conductive pads (e.g., copper pads) or combinations thereof.

Referring toFIG.4, one or more semiconductor dies200(e.g., memory dies, logic dies or other suitable dies) are provided and placed on a portion of the bonding structure120. InFIG.4, only one semiconductor die200is illustrated, however, the number of the semiconductor die200is not limited. In some embodiments, the semiconductor die200is placed on bonding structure120and stacked above the semiconductor die100′. The semiconductor die200may include a semiconductor substrate202, an interconnect structure204disposed on the semiconductor substrate202, and a bonding structure220disposed on and electrically connected to the interconnect structure204. The bonding structures220of the semiconductor die200is in contact with a portion of the bonding structure120. The bonding structure220may include a dielectric layer220aand conductors220beach penetrating through the dielectric layer220a. The material of the dielectric layer220amay be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitirde (SiOxNy, where x>0 and y>0) or other suitable dielectric material, and the conductors220bmay be conductive vias (e.g., copper vias), conductive pads (e.g., copper pads) or combinations thereof.

The conductors220bof the bonding structure220are aligned with the conductors120bof the bonding structure120, and sub-micron alignment precision between the semiconductor die200and the semiconductor die100′ may be achieved. Once the bonding structures220are aligned precisely with the bonding structure120, a chip-to-wafer hybrid bonding is performed such that the bonding structure220of the semiconductor die200is hybrid bonded to the bonding structure120. In other words, the semiconductor die200and the semiconductor die100′ may be bonded through a face-to-back hybrid bonding process.

In some embodiments, to facilitate chip-to-wafer hybrid bonding between the bonding structure120and the bonding structure220, surface preparation for bonding surfaces of the bonding structure120and the bonding structure220is performed. The surface preparation may include surface cleaning and activation, for example. Surface cleaning may be performed on the bonding surfaces of the bonding structure120and the bonding structure220to remove particles on bonding surfaces of the conductors120b, the dielectric layer120a, the conductors220b, and the dielectric layer220a. The bonding surfaces of the bonding structures120and the bonding structure220are cleaned by wet cleaning, for example. Not only particles may be removed, but also native oxide formed on the bonding surfaces of the conductors120band the conductors220bmay be removed. The native oxide formed on the bonding surfaces of the conductors120band the conductors220bmay be removed by chemicals used in the wet cleaning.

After cleaning the bonding surfaces of the bonding structures120and the bonding structure220, activation of the top surfaces of the dielectric layer120aand the dielectric layer220amay be performed for development of high bonding strength. In some embodiments, plasma activation is performed to treat and activate the bonding surfaces of the dielectric layer120aand the dielectric layer220a. When the activated bonding surface of the dielectric layer120ais in contact with the activated bonding surface of the dielectric layer220a, the dielectric layer120aand the dielectric layer220aare pre-bonded. The bonding structure220and the bonding structure120are pre-bonded through a pre-bonding of the dielectric layer120aand the dielectric layer220a. After the pre-bonding of the dielectric layer120aand the dielectric layer220a, the conductors120bare in contact with the conductors220b.

After the pre-bonding of the dielectric layer120aand the dielectric layer220a, a hybrid bonding of the semiconductor die200and the bonding structure120is performed. The hybrid bonding of the semiconductor die200and the bonding structure120may include a treatment for dielectric bonding and a thermal annealing for conductor bonding. The treatment for dielectric bonding is performed to strengthen the bonding between the dielectric layer120aand the dielectric layer220a. The treatment for dielectric bonding may be performed at temperature ranging from about 100 Celsius degree to about 150 Celsius degree, for example. After performing the treatment for dielectric bonding, the thermal annealing for conductor bonding is performed to facilitate the bonding between the conductors120band the conductors220b. The thermal annealing for conductor bonding may be performed at temperature ranging from about 300 Celsius degree to about 400 Celsius degree, for example. The process temperature of the thermal annealing for conductor bonding is higher than that of the treatment for dielectric bonding. Since the thermal annealing for conductor bonding is performed at relative higher temperature, metal diffusion and grain growth may occur at bonding interfaces between the conductors120band the conductors220b. After performing the thermal annealing for conductor bonding, the dielectric layer120ais bonded to the dielectric layer220a, and the conductors120bare bonded to the conductors220b. The conductor bonding between the conductors120band the conductors220bmay be via-to-via bonding, pad-to-pad bonding or via-to-pad bonding.

Referring toFIG.4andFIG.5, after the semiconductor die200is bonded to the semiconductor die100′ through the bonding structure120and the bonding structure220, an insulating material is formed to cover the bonding structure120, the bonding structure220, and the semiconductor die200. In some embodiments, the insulating material is formed by an over-molding process or a film deposition process such that a portion of the top surface of the bonding structure120, side surfaces of the bonding structure220, and a back surface and side surfaces of the semiconductor die200are encapsulated by the insulating material. After performing the over-molding process or film deposition process, a grinding process may be performed to reduce the thickness of the insulating material and the thickness of the semiconductor die200such that a semiconductor die200′ with reduced thickness and a second insulating encapsulation210are formed over the bonding structure120. After performing the grinding process, a semiconductor substrate202′ having reduced thickness is accessibly revealed from the second insulating encapsulation210. In some embodiments, the grinding process for reducing the thickness of the insulating material and the thickness of the semiconductor die200includes a mechanical grinding process, a chemical mechanical polishing (CMP) process, or combinations thereof.

As illustrated inFIG.5, in some embodiments, the thickness of the semiconductor die200′ is equal to the thickness of the second insulating encapsulation210, and the semiconductor die200′ and the bonding structure220are laterally encapsulated by the second insulating encapsulation210. In other words, the second insulating encapsulation210is merely in contact with side surfaces of the semiconductor die200′ and the bonding structure220, and the back surface of the semiconductor die200′ is accessibly revealed from the second insulating encapsulation210. In some alternative embodiments, not illustrated inFIG.5, the thickness of the semiconductor die is slightly less than or greater than the thickness of the second insulating encapsulation due to polishing selectivity of the grinding process. In other words, the top surface of the second insulating encapsulation may be slightly higher than or slightly lower than the back surface of the semiconductor die. Furthermore, the first insulating encapsulation110is spaced apart from the second insulating encapsulation210by the bonding structure120.

A bonding layer B3 is formed to cover the back surface of the semiconductor substrate202′ and the revealed surface of the second insulating encapsulation210. The bonding layer B3 may be a bonding layer prepared for fusion bond. In some embodiments, the bonding layer B3 is a deposited layer formed over the back surface of the semiconductor substrate202′ and the revealed surface of the second insulating encapsulation210. For example, the material of the bonding layer B3 includes silicon (Si), silicon dioxide (SiO2) or other suitable bonding materials.

Referring toFIG.6, a second carrier C2 including a bonding layer B4 formed on a top surface thereof is provided. The second carrier C2 may be a semiconductor wafer, and the bonding layer B4 may be a bonding layer prepared for fusion bond. In some embodiments, the bonding layer B4 is a deposited layer formed over the top surface of the second carrier C2. In some alternative embodiments, the bonding layer B4 is a portion of the second carrier C2 for fusion bond. For example, the material of the second carrier C2 includes silicon or other suitable semiconductor materials, and the material of the bonding layer B4 includes silicon (Si), silicon dioxide (SiO2) or other suitable bonding materials.

The resulted structure formed on the first carrier C1 is flipped upside down and transfer-bonded to the bonding layer B4 carried by the second carrier C2 such that the bonding layer B3 is in contact with and bonded to the bonding layer B4. In some embodiments, a wafer-to-wafer fusion bonding process is performed such that a fusion bonding interface is formed between the bonding layer B3 and the bonding layer B4. For example, the fusion bonding process for bonding the bonding layer B3 and the bonding layer B4 is performed at temperature ranging from about 100 Celsius degree to about 290 Celsius degree. The bonding layer B3 may be directly bonded to the bonding layer B4. In other words, there is no intermediate layer formed between the bonding layer B3 and the bonding layer B4. Furthermore, the fusion bonding interface formed between the bonding layer B3 and the bonding layer B4 may be a Si—Si fusion bonding interface, a Si—SiO2fusion bonding interface, a SiO2—SiO2fusion bonding interface or other suitable fusion bonding interfaces.

Referring toFIG.6andFIG.7, after bonding the bonding layer B3 and the bonding layer B4, a de-bonding process may be performed such that the bonding layer B1is de-bonded from the bonding layer B2 and the first insulating encapsulation110. The de-bonding process may be a laser lift-off process or other suitable de-bonding processes. After removing the bonding layer B1 and the first carrier C1, a grinding process may be performed such that the bonding layer B2 is removed to expose a surface of the dielectric layer106. During the removal of the bonding layer B2, the first insulating encapsulation110may be thinned down. In addition, after the removal of the bonding layer B2, the first insulating encapsulation110and the and the dielectric layer106may be further thinned down. In some embodiments, the removal of the bonding layer B2 and the thinning of the first insulating encapsulation110and the dielectric layer106may be performed by a same grinding process (e.g., a CMP process). As illustrated inFIG.7, after performing the grinding process, the semiconductor die100′ is revealed, but pads P (e.g., copper pads) of the semiconductor die100′ are not revealed and covered by the dielectric layer106.

Referring toFIG.8, a passivation layer230is formed to cover the first insulating encapsulation110and the dielectric layer106of the semiconductor die100′. The passivation layer230may be formed through chemical vapor deposition (CVD) or other suitable depositions. In some embodiments, the passivation layer230includes silicon oxide layer, silicon nitride layer, silicon oxynitride layer or other suitable dielectric layer. An anti-arcing material layer or a charge spreading pattern240is formed on the passivation layer230. The anti-arcing material layer240may be formed through sputtering, chemical vapor deposition (CVD) or other suitable depositions. In some embodiments, the anti-arcing material layer240includes a conductive layer, such as a sputtered titanium (Ti) layer, a sputtered Ti—Cu alloy layer, a sputtered tantalum (Ta) layer or other suitable metallic materials. The thickness of the anti-arcing material layer240may range from about 10 angstroms to about 1000 angstroms. The thickness of the anti-arcing material layer240may be modified.

Referring toFIG.8andFIG.9, a patterning process of the dielectric layer106, the passivation layer230, and the anti-arcing material layer240is performed such that a patterned dielectric layer106′, a patterned passivation layer230′, and an anti-arcing pattern240′ are formed. Multiple first openings OP1 are formed in the patterned dielectric layer106′, the patterned passivation layer230′, and the anti-arcing pattern240′ such that top surfaces of the pads P (e.g., copper pads) of the semiconductor die100′ are partially exposed by the first openings OP1. In some embodiments, a photolithography process is performed to form a patterned photoresist layer PR1 on the anti-arcing material layer240, and an etching process (e.g. a dry etching process) is performed to remove portions of the dielectric layer106, the passivation layer230, and the anti-arcing material layer240that are not covered by the patterned photoresist layer PR1 until the top surfaces of the pads P (e.g., copper pads) of the semiconductor die100′ are partially exposed.

In an embodiment where the first openings OP1 are formed by a dry etching process (e.g., a plasma dry etching process), since charge accumulation occurred around the first openings OP1 is minimized by the anti-arcing material layer240or the anti-arcing pattern240′, arcing damage issue of the pads P (e.g., copper pads) of the semiconductor die100′ may be improved. In some embodiments, the anti-arcing pattern240′ includes a conductive pattern, such as a sputtered titanium (Ti) pattern, a sputtered Ti—Cu alloy pattern, a sputtered tantalum (Ta) pattern or other suitable metallic pattern. The thickness of the anti-arcing material layer pattern240′ may range from about 10 angstroms to about 1000 angstroms. The thickness of the anti-arcing pattern240′ may be modified to minimize charge accumulation and provide proper anti-arcing function.

Referring toFIG.9andFIG.10, after forming the first openings OP1, the patterned photoresist layer PR1 is removed from the anti-arcing pattern240′. After the removal of the patterned photoresist layer PR1, a post passivation layer250including second openings OP2 is formed to cover the patterned dielectric layer106′, the patterned passivation layer230′, and the anti-arcing pattern240′. The post passivation layer250may extend into the first openings OP1 (illustrated inFIG.9), and portions of the pads P of the semiconductor die100′ are revealed by the second openings OP2 defined in the post passivation layer250. A plating process may be performed such that multiple conductive terminals260are formed on the revealed portions of the pads P of the semiconductor die100′. As illustrated inFIG.10, the conductive terminals260may land on the pads P of the semiconductor die100′, fill the second openings OP2 defined in the post passivation layer250, and protrude from the top surface of the post passivation layer250. Furthermore, the conductive terminals260may be spaced apart from the anti-arcing pattern240′ by the post passivation layer250. The anti-arcing pattern240′ may be electrically insulated from the conductive terminals260. For example, the anti-arcing pattern240′ is electrically floating. In some embodiments, as illustrated inFIG.10, no seed layer is formed between the conductive terminals260and the post passivation layer250.

Referring toFIG.10andFIG.11, after forming the conductive terminals260, a de-bonding process is performed such that an SoIC de-bonded from the carrier C2 is obtained. In some other embodiments where multiple semiconductor dies100′ and multiple semiconductor dies200′ are used, a singulation process is further performed such that multiple singulated SoICs are obtained.

As illustrate inFIG.11, the SoIC may include a semiconductor die (i.e. first semiconductor die or bottom tier semiconductor die)200′, a semiconductor die (i.e. second semiconductor die or top tier semiconductor die)100′, a passivation layer230′, an anti-arcing pattern240′, a post passivation layer250, and conductive terminals260. The semiconductor die100′ is stacked over the semiconductor die200′. The semiconductor die100′ may be bonded to the semiconductor die200′ through a face-to-back hybrid bonding process. The semiconductor die100′ may be bonded to the semiconductor die200′ through the bonding structure120and the bonding structure220, and the semiconductor die100′ is electrically connected the semiconductor die200′ through the bonding structures120and220. The passivation layer230′ covers the semiconductor die100′ and includes first openings OP1 for revealing pads P (e.g., copper pads) of the semiconductor die100′. The anti-arcing pattern240′ is disposed over the passivation layer230′, and the anti-arcing pattern240′ is distributed outside the first openings OP1 of the passivation layer230′. For example, the anti-arcing pattern240′ is disposed on a top surface of the passivation layer230′. In other words, the anti-arcing pattern240′ may be disposed between the post passivation layer250and the passivation layer230′. The post passivation layer250may cover the passivation layer230′ and the anti-arcing pattern240′. The post passivation layer250may extend into the first openings OP1 and includes second openings OP2 for revealing portions of the pads P of the semiconductor die100′. For example, the post passivation layer250may extend along sidewall of the first openings OP1. The conductive terminals260are disposed over and electrically connected to the pads P of the semiconductor die100′. Furthermore, the conductive terminals260may be spaced apart from sidewalls of the anti-arcing pattern240′ by the post passivation layer250.

FIG.12andFIG.14are a cross-sectional view schematically illustrating another process flow for fabricating an SoIC component in accordance with some embodiments of the present disclosure.

Referring toFIG.9andFIG.12, after performing the process illustrated inFIG.9, the patterned photoresist layer PR1 (illustrated inFIG.9) is removed through a stripping process, for example. A seed layer270is conformally formed to cover the anti-arcing pattern240′ and the pads P of the semiconductor die100′ through sputtering, for example. The sputtered seed layer270not only cover top surface of the anti-arcing pattern240′, but also extends along and covers the side surfaces of the patterned dielectric layer106′, the patterned passivation layer230′, and the anti-arcing pattern240′. In some embodiments, the seed layer270includes a sputtered Ti/Cu seed layer. After forming the seed layer270, a patterned photoresist layer PR2 is formed on the seed layer270, and the patterned photoresist layer PR2 includes multiple openings for exposing portions of the seed layer270. A plating process may be performed to form conductive posts280in the openings defined in the patterned photoresist layer PR2.

Referring toFIG.12andFIG.13, the patterned photoresist layer PR2 are removed from the seed layer270through a stripping process, for example. After removing the patterned photoresist layer PR2, portions of the seed layer270that are not covered by the conductive posts280are exposed. A patterning process is performed to remove the exposed portions of the seed layer270and the anti-arcing pattern240′ located under the seed layer270until the patterned passivation layer230′ are revealed. After performing the above-mentioned patterning process, a reflow process may be performed to reshape the conductive posts280such that anti-arcing patterns240aand conductive bump280aare formed over the semiconductor die100′, wherein each of the conductive terminals260aincludes the seed pattern270aand the conductive bump280aon the seed pattern270a, the seed pattern270acovers the anti-arcing pattern240′ and extends into the first openings OP1, and the conductive bump280ais spaced apart from the anti-arcing pattern240′ by the seed pattern270a. The conductive terminals260amay electrically connected to and directly cover the anti-arcing patterns240a. In some embodiments, the anti-arcing pattern240ais disposed on the top surface of the passivation layer230′ and distributed outside the first openings OP1 of the passivation layer230′. Furthermore, the top surface of the anti-arcing pattern240amay be entirely covered by the seed pattern270aof the conductive terminals260a.

Referring toFIG.13andFIG.14, after forming the conductive terminals260a, a de-bonding process is performed such that an SoIC de-bonded from the carrier C2 is obtained. In some other embodiments where multiple semiconductor dies100′ and multiple semiconductor dies200′ are used, a singulation process is further performed such that multiple singulated SoICs may be obtained.

As illustrate inFIG.11andFIG.14, the SoIC illustrated inFIG.14is similar with that illustrated inFIG.11except for configuration of the conductive terminals260aformed on the semiconductor dies100′.

FIG.15throughFIG.19are cross-sectional views schematically illustrating still another process flow for fabricating an SoIC component in accordance with other embodiments of the present disclosure.

Referring toFIG.8andFIG.15, after performing the process illustrated inFIG.8, a patterning process of the dielectric layer106, the passivation layer230, and the anti-arcing material layer240is performed such that a patterned dielectric layer106′, a patterned passivation layer230′, and an anti-arcing pattern240′ are formed. Multiple first openings OP1 are formed in the patterned dielectric layer106′, the patterned passivation layer230′, and the anti-arcing pattern240′ such that top surfaces of the pads P1 (e.g., copper pads) of the semiconductor die100′ are partially exposed by the first openings OP1, and the pads P2 of the semiconductor die100′ are not exposed. The pads P2 of the semiconductor die100′ are covered by the patterned dielectric layer106′, the patterned passivation layer230′, and the anti-arcing pattern240′. In some embodiments, as illustrated inFIG.15, a photolithography process is performed to form a patterned photoresist layer PR3 on the anti-arcing material layer240, and an etching process (e.g. a dry etching process) is performed to remove portions of the dielectric layer106, the passivation layer230, and the anti-arcing material layer240that are not covered by the patterned photoresist layer PR3 until the top surfaces of the pads P1 (e.g., copper pads) of the semiconductor die100′ are partially exposed. The number of the pads P1 and the number of the pads P2 are not limited in the present application.

In an embodiment where the first openings OP1 are formed by a dry etching process (e.g., a plasma dry etching process), since charge accumulation occurred around the first openings OP1 is minimized by the anti-arcing material layer240or the anti-arcing pattern240′, arcing damage issue of the pads P1 (e.g., copper pads) of the semiconductor die100′ may be improved.

Referring toFIG.15andFIG.16, after forming the first openings OP1, the patterned photoresist layer PR3 is removed from the anti-arcing pattern240′ through a stripping process, for example. After the removal of the patterned photoresist layer PR3, a post passivation layer250including second openings OP2 is formed to cover the patterned dielectric layer106′, the patterned passivation layer230′, and the anti-arcing pattern240′. The first openings OP1 are wider than the second openings OP2. The post passivation layer250may extend into the first openings OP1, and portions of the pads P1 of the semiconductor die100′ are revealed by the second openings OP2 defined in the post passivation layer250. A plating process may be performed such that multiple conductive terminals260are formed on the revealed portions of the pads P1 of the semiconductor die100′. As illustrated inFIG.16, the conductive terminals260may land on the pads P1 of the semiconductor die100′, fill the second openings OP2 defined in the post passivation layer250, and protrude from the top surface of the post passivation layer250. Furthermore, the conductive terminals260may be spaced apart from the anti-arcing pattern240′ by the post passivation layer250. In some embodiments, as illustrated inFIG.16, no seed layer is formed between the conductive terminals260and the post passivation layer250.

Referring toFIG.17, the post passivation layer250and the anti-arcing pattern240′ are patterned to form a third opening OP3 for exposing a portion of the patterned passivation layer230′. The third opening OP3 is located above the pads P2 of the semiconductor die100′. Furthermore, the third opening OP3 may be wider than the first openings OP1 and the second openings OP2.

Referring toFIG.17andFIG.18, one or more fourth openings OP4 are formed in the patterned dielectric layer106′ and the patterned passivation layer230′. A photolithography process followed by an etching process (e.g. a dry etching process) is performed to remove portions of the patterned dielectric layer106′ and the patterned passivation layer230′ until the top surfaces of the pads P2 of the semiconductor die100′ are partially exposed by the fourth openings OP4. The number of the fourth openings OP4 and the number of the pads P2 are not limited in the present application. In an embodiment where the fourth openings OP4 are formed by a dry etching process (e.g., a plasma dry etching process), since charge accumulation occurred around the fourth openings OP4 can be minimized by the anti-arcing pattern240′ or240b, arcing damage issue of the pads P2 of the semiconductor die100′ may be improved.

Conductive terminals260aelectrically connected to the pads P2 of the semiconductor die100′ are formed to fill the fourth openings OP4. In some embodiments, the conductive terminals260aeach includes a seed pattern270aand a conductive bump280acovering the seed pattern270a. As illustrated inFIG.18, the height of the conductive terminals260amay be substantially equal to the height of the conductive terminals260, and the lateral dimension (e.g., maximum width) of the conductive terminals260amay be greater than the lateral dimension (e.g., maximum width) of the conductive terminals260. The fabrication processes of the conductive terminals260aillustrated inFIG.18are similar with those illustrated inFIGS.12and13. Detailed descriptions regarding to fabrication processes of the conductive terminals260aare thus omitted.

As illustrated inFIG.18, after the conductive terminals260aare formed, the anti-arcing pattern240′ may include a first portion240aand a second portion240b, the first portion240aof the anti-arcing pattern240′ is located between the patterned passivation layer230′ and the conductive terminals260a, and the second portion240bof the anti-arcing pattern240′ is located between the patterned passivation layer230′ and the post passivation layer250. The first portion240aof the anti-arcing pattern240′ is spaced apart from the second portion240bof the anti-arcing pattern240′. Furthermore, the first portion240aof the anti-arcing pattern240′ is distributed in the third openings OP3.

Referring toFIG.18andFIG.19, after forming the conductive terminals260a, a de-bonding process is performed such that an SoIC de-bonded from the carrier C2 is obtained. In some other embodiments where multiple semiconductor dies100′ and multiple semiconductor dies200′ are used, a singulation process is further performed such that multiple singulated SoICs are obtained.

As illustrate inFIG.11andFIG.19, the SoIC illustrated inFIG.19is similar with that illustrated inFIG.11except that the SoIC illustrated inFIG.19includes both the conductive terminals260and260a.

In the above-described embodiments, the anti-arcing pattern may minimize arcing damage issue of the pads of the semiconductor die. Accordingly, the fabrication yield may increase.

In accordance with some embodiments of the disclosure, a semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die. In some embodiments, a top surface of the anti-arcing pattern is entirely covered by the conductive terminals. In some embodiments, the anti-arcing pattern is distributed outside the first openings of the passivation layer. In some embodiments, the conductive terminals each includes a seed pattern and a bump on the seed pattern, the seed pattern covers the anti-arcing pattern and extends into the first openings, and the bump is spaced apart from the anti-arcing pattern by the seed pattern. In some embodiments, the semiconductor structure further includes a post passivation layer, wherein the anti-arcing pattern is disposed on a top surface of the passivation layer, the anti-arcing pattern includes a first portion and a second portion, the first portion of the anti-arcing pattern is located between the passivation layer and first conductive terminals among the conductive terminals, and the second portion of the anti-arcing pattern is located between the passivation layer and the post passivation layer. In some embodiments, the post passivation layer extends into the first openings and includes second openings for revealing portions of the pads of the second semiconductor die, and second conductive terminals among the conductive terminals are electrically connected to the portions of the pads of the second semiconductor die though the second openings of the post passivation layer. In some embodiments, the post passivation layer includes third openings wider than the first openings of the passivation layer, and the first portion of the anti-arcing pattern is distributed in the third openings. In some embodiments, the semiconductor further includes a post passivation layer covering the passivation layer and the anti-arcing pattern, wherein the post passivation layer extends into the first openings and includes second openings for revealing portions of the pads of the second semiconductor die, and the anti-arcing pattern is between the post passivation layer and the passivation layer. In some embodiments, the anti-arcing pattern is spaced apart from the conductive terminals by the post passivation layer.

In accordance with some other embodiments of the disclosure, a semiconductor structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation, a passivation layer, a charge spreading pattern, and conductive terminals is provided. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first bonding structure over the first interconnect structure. The second semiconductor die is stacked over the first semiconductor die. The second semiconductor die includes a second semiconductor substrate, a second interconnect structure, and a second bonding structure, wherein the second interconnect structure and the second bonding structure are disposed on opposite surfaces of the second semiconductor substrate, and the second semiconductor die is electrically connected the first semiconductor die through the first and second bonding structures. The insulating encapsulation laterally encapsulates the first and second semiconductor dies. The passivation layer is disposed over the second interconnect structure of the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die. The charge spreading pattern disposed between the conductive terminals and the passivation layer. In some embodiments, insulating encapsulation comprises a first encapsulation portion and a second encapsulation portion, the first semiconductor die is laterally encapsulated by the first encapsulation portion, and the second semiconductor die is laterally encapsulated by the second encapsulation portion.

In some embodiments, the charge spreading pattern is distributed outside the first openings of the passivation layer, a top surface of the charge spreading pattern is entirely covered by the conductive terminals, the conductive terminals each includes a seed pattern and a bump on the seed pattern, the seed pattern covers the charge spreading pattern and extends into the first openings, and the bump is spaced apart from the charge spreading pattern by the seed pattern. In some embodiments, the semiconductor structure further includes a post passivation layer, wherein the charge spreading pattern is disposed on a top surface of the passivation layer and includes a first portion and a second portion, the first portion of the charge spreading pattern is located between the passivation layer and parts of the conductive terminals, and the second portion of the charge spreading pattern is located between the passivation layer and the post passivation layer. In some embodiments, the semiconductor structure further includes a post passivation layer covering the passivation layer and the charge spreading pattern, wherein the post passivation layer extends into the first openings and includes second openings for revealing portions of the pads of the second semiconductor die, and the charge spreading pattern is between the post passivation layer and the passivation layer. In some embodiments, the charge spreading pattern is electrically floating.

In accordance with some other embodiments of the disclosure, a method including the followings is provided. An upper tier semiconductor die is bonded to a bottom tier semiconductor die, wherein the upper tier semiconductor die comprises pads. A passivation layer is formed over a top surface of the upper tier semiconductor die. An anti-arcing pattern is formed over the passivation layer, wherein the passivation layer comprises openings for revealing the pads of the upper tier semiconductor die. Conductive terminals are formed over the upper tier semiconductor die, wherein the conductive terminals are electrically connected to the pads of the upper tier semiconductor die. In some embodiments, the anti-arcing pattern is electrically connected to the conductive terminals after forming the conductive terminals over the upper tier semiconductor die. In some embodiments, the anti-arcing pattern is formed by depositing an anti-arcing material followed by a patterning process, and the patterning process is performed by using the conductive terminals as a mask. In some embodiments, the method further includes: forming a post passivation layer over the passivation layer to cover at least a portion of the anti-arcing pattern. In some embodiments, the anti-arcing pattern is electrically insulated from the conductive terminals after forming the conductive terminals over the upper tier semiconductor die.