Video board for serving both 1-bit plane operation and 2-bit plane operation

A video board in a personal computer supports a 2-gray level monitor as well as a 4-gray level monitor, by serving both the 1-bit plane video board operation and the 2-bit plane video board operation. A video output controller, having a shift register, a jumper and a divider, generates video output signals according to the selection made between the 1-bit and the 2-bit plane video boards. The shift register shifts the inputted data according to the order of the clock pulses. In the case of the 1-bit plane video board operation, eight clock pulses are supplied with a clock pulse input line connected to the clock generator output line by the jumper, while in the case of the 2-bit plane video board operation, four clock pulses are supplied with the clock pulse input line coupled to the divider by the jumper. The frequency of the clock pulses from the clock generator is divided by 2 through passing the divider. The decision of the operations of each bit plane video board is made by the jumper.

BACKGROUND OF THE INVENTION 
The present invention relates to video boards for use in, for example, 
personal computers, and more particularly to video boards supporting both 
a 1-bit plane video board mode for a black/white monitor and a 2-bit plane 
video board mode for a 4-gray level monitor. 
Heretofore, a known monochrome video board has supported a 2-gray level 
(black and white) monochrome monitor. Recently, however, an improved 
monochrome video board has been developed to support a 4-gray level(black, 
white, gray1 and gray2) monochrome monitor for graphics. 
The former 2-gray level monochrome monitor usually must use the 1-bit plane 
board for supplying two kinds of video intensity (black and white) and the 
latter 4-gray level monochrome monitor must use the 2-bit plane video 
board for supplying four kinds of video intensity (black, white, gray1 and 
gray2). Conventionally, the two video boards have different hardware. That 
is, since the 2-gray level monochrome monitor and the 4-gray level 
monochrome monitor each utilizes its own bit plane operation, they have 
not been compatible with each other. Therefore, the 1-bit plane video 
board can never support the 4-gray level monitor, and if the 2-bit plane 
video board is connected to the black/white monitor, it may have 
considerable disadvantages not only in memory allocation and race problems 
but also in cost. 
SUMMARY OF THE INVENTION 
Thus, an object of the present invention is to provide a video board 
capable of being applied to different types of monochrome monitors by 
operating selectively the 1-bit plane video board mode or 2-bit plane 
video board mode. 
According to one aspect of the present invention, a video board serving 
both the operation of the 1-bit plane video board and the operation of the 
2-bit plane board includes a graphic processor for controlling operation 
of the video board under the control of a computer, a memory for storing 
and sending out picture information under the control of the graphic 
processor, a switch for the picture information in the memory by 
separately buffering it into the most and the least significant bits, a 
video output controller for selectively generating both operation of the 
1-bit plane video board and the 2-bit plane video board by shifting the 
output of the switch and by a given shift order depending on the selection 
between the operation of the 1-bit and the 2-bit plane video board, and a 
connector for transmitting output of the video output controller to a 
monitor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
In FIG. 1, a block diagram according to the invention is shown. A graphic 
processor 20 controls the general operation of a video board according to 
the invention. A host interface 10 exchanges data and control signals 
between a personal computer and the graphic processor 20. A memory 
controller 30 is connected to the graphic processor 20 for generating and 
applying write control signals or read control signals to a memory 80, 
which stores the information from the personal computer. Using a decoded 
addressing technique, an address decoder 40, connected to the address 
lines of the graphic processor 20, selects specified addresses within the 
memory 80. A data buffer 50 transmits information from the graphic 
processor 20 to the memory location selected by the address decoder 40. A 
switch 90 buffers the 16-bit data from the memory 80 and outputs the 
16-bit data into a video output controller 100 only eight bits at a time, 
while the video output controller 100 shifts the 8-bit data from the 
switch 90 according to the selection made between 1-bit plane video board 
mode and 2-bit plane video board mode, or transmits in parallel the input 
data. The video output controller 100 and a monitor are interconnected by 
a connector 110. A timing controller 70, supplied by an oscillator 60, 
generates adequate clock pulses to the graphic processor 20 and the video 
output controller 100 by dividing the clock frequency. 
FIG. 2 shows in more detail an example of the memory controller 30 in FIG. 
1, in which the first memory controller 31 for generating write enable 
signals to the memory 80 and a second memory controller 32 for generating 
serial output enable signals to the memory 80 are both controlled by two 
address lines LAD8-LAD9 and a transmission or output enable line TR/OE. 
A more detailed block diagram of an example of the memory 80 is shown in 
FIG. 3. The memory 80, composed of sixteen 16K .times.4 DRAMs 82, is 
divided into quarters, and each part, composed of four RAMs, is called a 
bank. Each bank is selected by the control signals from the memory 
controller 30. 
Referring to FIG. 4, a more detailed block diagram of the video output 
controller 100 in FIG. 1 is shown. A shift register 101 shifts the data 
from the switch 90 by a required shift order, according to the condition 
of first and second selection lines S0, S1 or outputs in parallel the same 
data that is input. With a jumper 102, the user selects 1-bit plane video 
board or 2-bit plane video board. Operation of the 2-bit plane video board 
is performed by a divider 103 for dividing the period of the timing 
controller 70. 
The graphic processor 20 exchanges data, addresses and control signals with 
a computer via the host interface 10. The graphic processor 20 controls 
the video board and sends pictures to the monitor in accordance with the 
information from the personal computer, and tells the personal computer 
when the execution of a given instruction is accomplished. 
The graphic processor 20 is supplied with clock (CLK) by the clock 
generator 70, and from this a video synchronizing signal is generated. For 
example, VCLK input line of "TMS 34010" of the Texas Instrument Co. is 
supplied with 13.3 MHz-clock when the machine cycle of the graphic 
processor 20 is 40 MHz. 
The graphic processor 20 may generate a horizontal synchronous signal 
(H-SYNC) of 65 KHz and a vertical synchronous signal (V-SYNC) of 62 KHz by 
dividing the frequency of the input clock (V CLOCK) as necessary; 
otherwise the frequencies of these two synchronous signals (H/V-SYNC) can 
be adjusted by programming when using "TMS 34010". 
In addition to generating those synchronous signals, the graphic processor 
20 generates address signals, transmission or output enable (TR/OE) 
signal, row address strobe signal (RAS) and column address strobe (CAS) 
signal in order to refresh Dynamic Random Access Memory (DRAM) 80, which 
includes video RAM(VRAM) for the monitor and general purpose RAM (RAM) for 
the other than the monitor. 
The TR/OE signal and address signals for controlling writing or reading of 
the memory 80 content is applied to the memory controller 30, which 
generates four memory control signals to pins CTL 0 to CTL 3, as 
illustrated in FIG. 2. 
The first controller 31 generates write enable signals to pins WES0 to WES3 
for storing information in the memory 80 under the control of the address 
signals from lines LAD8 to LAD9 and the TR/OE signal. The second 
controller 32 generates serial output enable signals to pins SOE0 to SOE3 
for outputting the stored information under the control of the address 
signals from lines LAD8 to LAD9 and the TR/OE signal. 
In FIG. 3, control signals CTL0-CTL3 are equivalent to WES signals during 
writing phase and are equivalent to SOE signals during reading phase. 
An address of the DRAMs is not designated until the RAS signal and CAS 
signal are active. The content being addressed is then loaded on the data 
bus. 
The circuit of FIG. 3 uses sixteen DRAMs of 16K.times.4 bits, which, as 
mentioned above, are divided into quarters. And a batch of four DRAMs is 
called a bank, as illustrated in FIG. 3. Each bank is selected by one of 
the control signals on pins CTL0 to CTL3 which the memory controller 30 
generates by the help from the two address lines of the graphic processor 
20. When one of the banks is selected, 16-bit data of the selected VRAM is 
read out at a time. 
Memory logic states of each bank selection are illustrated in Table 1; 
(TABLE 1) 
______________________________________ 
A9 A8 
______________________________________ 
The first bank of RAM 0 0 
The second bank of RAM 0 1 
The third bank of RAM 1 0 
The fourth bank of RAM 1 1 
______________________________________ 
According to the logic state of the TR/OE signal of the graphic processor 
20, one of the control signals, generated by the memory controller 30 
applies to the corresponding bank, and the memory content of a given 
location can thereby be read out or written in on the basis of the address 
condition shown in Table 1. 
The first memory controller 31 generates the write enable signals to pins 
WES0 to WES3, and the second memory controller 32 generates the serial 
output enable signals to pins SOE0 to SOE3 according to the condition of 
the TR/OE signal. 
Thus, image data is written to a given location of the video RAM, while the 
TR/OE signal is in logic high state. The data in the memory location of 
the video RAM is transmitted to the shift register 101, while the TR/OE 
signal is in logic low state. The serial output enable signals enable the 
data to be serially loaded in the video output data bus. 
Here, most areas of the video RAMs are used as a frame buffer for the video 
output. The rest, if any, can be used for general memory. As the frame 
buffer has the information relating to the screen, the graphic processor 
20 always refreshes the frame buffer at regular intervals. When some data 
are changed, the last data can be updated within a short period owing to 
the characteristics by which the video RAM immediately sends the data to 
the shift register. 
The DRAM can also be used as a memory for programs and data or used as an 
off-screen memory. Here, the off-screen memory, like bit block transfer, 
may be necessary for particular graphic operations requiring bit 
manipulation. The DRAM may store data of temporary results from some 
mathematical operation, and final data may be sent to the frame buffer of 
the video RAM. The 16-bit data from the frame buffer is loaded on the 
8-bit data bus by the switch 90 only 8 bits at a time. 
The "74LS157" device may be used for the switch 90. The 8-bit data bus is 
connected to the 8-bit shift register 101 of video output controller 100, 
as illustrated in FIG. 4. 
Now the operation of video output signals is further explained. The first 
selection line SO and the second selection line S1 decide the operation 
mode of the shift register 101. 
When the second selection signal on line S1 is fixed in logic low state and 
the first selection signal on line S0 is in logic low state, the data into 
the eight input lines D0-D7 are transmitted via the eight output lines 
Q0-Q7 since the 8-bit shift register 101 is then set in parallel mode. 
On the other hand, when the first selection line S0 is in logic high state 
as well as the second selection line S1 is in logic low state, the input 
data are shifted left as many times as required, depending on the order of 
the clock pulse CP. 
______________________________________ 
After one clock 
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 
pulse is applied 
Q1 Q2 Q3 Q4 Q5 Q6 Q7 X 
______________________________________ 
In the first case of 1-bit plane video board mode, the user switches the 
jumper 102 to the first selection line S0 directly without passing through 
the divider 103, so the shift register carries out a shift operation eight 
times between set pulses, as illustrated in FIG. 5A. 
Therefore, after eight clock pulses, 8 bits of the data are transmitted in 
serial one bit per clock pulse to the connector 110 through the first 
output line Q0, and the fifth output terminal Q4 remains inactive. 
After the eight clock pulses, a set pulse is applied to the first selection 
line S0, to set the new data received at the input terminals D0-D7 onto 
the output terminals Q0-Q7 respectively. Thereafter, the new data is 
transmitted via terminal Q0 during the next eight clock pulses CP. 
In the second case of 2-bit plane video board mode, the jumper 102 is 
switched to the divider 103 so that the shift register 101 may carry out 
shift operation four times between set pulses, as illustrated in FIG. 5B, 
after 8-bit data is loaded in parallel on the eight input lines D0-D7 of 
the shift register 101. As a result, after four clock pulses, 8 bits of 
the data are transmitted in serial two bits per clock pulse to the 
connector 110 through the first and fifth output lines Q0, Q4. 
Thus, the divider 103 increases the frequency of the set pulses from the 
clock generator 70 by two, in case of 2-bit plane video board mode. The 
logic state of the first selection line S0 should be negligibly low as 
compared with its logic high state when switching is carried out by means 
of the jumper 102. 
The negligibly logic low condition referred to herein means that the value 
of logic low condition must be less than 1/10 of that of the logic high 
condition. It also means that load time should be less than 1/10 of shift 
time. This is because the shift register performs its operation after 
8-bit data is once loaded, and the load operation must be accomplished 
before the next period. It is also because a time error between the end of 
shift and the start of the next data load operation must be avoided. 
As described hereinabove, the illustrated circuit has advantages in that it 
is able to use two types of monitor by supporting the operation not only 
of 1-bit plane video board but also of 2-bit plane video board with the 
same video board, and in that it reduces the required memory capacity to a 
half of that of the 2-bit plane video plane in case of use as 1-bit plane 
video board, so that the rest of the memory may be used as an off-screen 
memory or for other purposes, thereby promoting memory efficiency and 
improved graphic speed. 
The invention is not restricted to the details of the foregoing embodiment. 
The invention extends to any novel one, or any novel combination, of the 
features disclosed in this specification (including any accompanying 
claims, abstract and drawings), or to any method or process so disclosed.