ELECTRONIC DEVICE AND METHOD OF OPERATING THE SAME

An electronic device includes a display panel, a display driver IC (DDI), a gate driver, a light-emission driver, and a processor. The display panel includes multiple data lines, multiple gate signal lines, and light-emission signal lines. The DDI drives the display panel. The gate driver applies gate scan signals to the multiple gate signal lines, based on control of the DDI. The light-emission driver applies light-emission signals to the multiple light-emission signal lines, based on control of the DDI. The processor controls the DDI. The processor controls a first scan speed of the gate scan signals to be different from a second scan speed of the light-emission signals.

BACKGROUND

Various embodiments of the disclosure relate to an electronic device and a method for operating the same.

2. Description of Related Art

Displays of electronic devices correspond to core technologies in the information communication era, and have been evolving to be thinner, lighter, portable, and high-performance. For example, OLED displays are drawing attention as flat display displays capable of reducing weight and volume, which are drawbacks of cathode ray tubes (CRTs). An OLED display may have multiple pixels disposed in a matrix type, thereby displaying images. Each of the pixels may include a light-emitting element, at least one thin film transistor (hereinafter, referred to as TFT) configured to independently drive the light-emitting element, and a storage capacitor.

SUMMARY

When an image displayed on a foldable display or rollable display moves vertically, there may be a difference in speed of image update, depending on the position of gate lines. There is a problem in that such a difference in speed of image update, depending on the position of gate lines, results in a jelly-scroll effect (the image appears slanted). The speed of image update may be increased in an attempt to prevent the jelly-scroll effect of the display, but this causes a problem of increased power consumption due to high-speed driving, and increased component prices.

It is a technical aspect of various embodiments of the disclosure to provide an electronic device and a method for operating the same, wherein the occurrence of a jelly-scroll effect can be prevented in a foldable or rollable display.

Technical aspects to be accomplished by the disclosure are not limited to the above-mentioned technical aspects, and other technical aspects not mentioned herein will be clearly understood from the following description by those skilled in the art to which the disclosure pertains.

An electronic device according to various embodiments of the disclosure may include a display panel, a display driver IC (DDI), a gate driver, a light-emission driver, and a processor. The display panel may include multiple data lines, multiple gate signal lines, and light-emission signal lines. The DDI may drive the display panel. The gate driver may apply gate scan signals to the multiple gate signal lines, based on control of the DDI. The light-emission driver may apply light-emission signals to the multiple light-emission signal lines, based on control of the DDI. The processor may control the DDI. The processor may control a first scan speed of the gate scan signals to be different from a second scan speed of the light-emission signals.

In a method for operating an electronic device according to various embodiments of the disclosure, a gate driver may apply gate scan signals to multiple data lines disposed in a display panel at a first scan speed. A light-emission driver may apply light-emission signals to multiple light-emission signal lines disposed in the display panel at a second scan speed. A processor may control the first scan speed of the gate scan signals to be different from the second scan speed of the light-emission signals.

An electronic device according to various embodiments of the disclosure may prevent the occurrence of a jelly-scroll effect when an image moves vertically in a foldable or rollable display.

An electronic device according to various embodiments of the disclosure may prevent a jelly-scroll effect without increasing the DDI driving speed, thereby preventing power consumption and component prices from increasing.

Various other advantageous effects identified explicitly or implicitly through the disclosure may be provided.

DETAILED DESCRIPTION

According to an embodiment, the display module160illustrated inFIG. 1may include a flexible display configured to be able to be folded or unfolded.

According to an embodiment, the display module160illustrated inFIG. 1may include a flexible display slidably disposed to provide a screen (e.g., a display screen).

For example, the display region of the electronic device101is a region visually exposed to allow an image to be output, and the electronic device101may adjust the display region on the basis of movement of a sliding plate (not shown) or movement of the display. There may be an example in which a rollable-type electronic device, which is configured to selectively enlarge a display region by at least partially operating at least a part (e.g., a housing) of the electronic device101in a slidable manner, includes the above-described display module160. For example, the display module160may be called a slide-out display or an expandable display. According to an embodiment, the display module160illustrated inFIG. 1includes a flexible display, but the disclosure is not limited thereto. The display module160may include a bar-type, or plate-type display.

FIG. 2is a block diagram of a display module according to various embodiments of the disclosure.

Referring toFIG. 2, a display module160may include a display200, and a display driver IC230(hereinafter, referred to as DDI230) for controlling the display200.

The DDI230may include an interface module231, a memory233(e.g., a buffer memory), an image processing module235, and/or a mapping module237.

According to an embodiment, the DDI230may receive image data, or image information including an image control signal corresponding to a command for controlling the image data from another element of the electronic device101through the interface module231.

According to an embodiment, the image information may be received from a processor (e.g., the processor120inFIG. 1) (e.g., the main processor121inFIG. 1) (e.g., the application processor) or an auxiliary processor (e.g., the auxiliary processor123inFIG. 1) (e.g., the graphics processing unit) operated independently of functions of the main processor121.

According to an embodiment, the DDI230may communicate with a touch circuit250or a sensor module176through the interface module231. Further, the DDI230may store at least a part of the received image information to the memory233. In an example, the DDI230may store at least a part of the received image information to the memory233in frame units.

According to an embodiment, the image processing module235may perform pre-processing or post-processing (e.g., perform resolution, brightness, or size adjustment) of at least a part of the image data, based at least on characteristics of the image data or characteristics of the display200.

According to an embodiment, the mapping module237may generate a voltage value or a current value corresponding to the image data pre-processed or post-processed through the image processing module235. In an embodiment, the generation of a voltage value or a current value may be performed based at least partially on, for example, attributes of pixels (e.g., arrangement of pixels (red-green-blue (RGB) stripe or Pentile structure) or the size of each of subpixels) of the display200.

In an embodiment, at least some pixels of the display200may be driven based at least partially on the voltage value or the current value, and thus visual information (e.g., text, images, or icons) corresponding to the image data may be displayed through the display200.

According to an embodiment, the display module160may further include a touch circuit250. The touch circuit250may include a touch sensor251and a touch sensor IC253for controlling the same.

In an embodiment, the touch sensor IC253may control the touch sensor251in order to sense a touch input or a hovering input to a specific position on the display200. For example, the touch sensor IC253may sense the touch input or the hovering input by measuring changes in a signal (e.g., a voltage, the amount of light, resistance, or the quantity of electric charge) regarding the specific position on the display200. The touch sensor IC253may provide information (e.g., position, area, pressure, or time) about the sensed touch input or hovering input to the processor (e.g., the processor120inFIG. 1).

According to an embodiment, at least a part (e.g., the touch sensor IC253) of the touch circuit250may be included as a part of the display driver IC230or a part of the display200.

According to an embodiment, at least a part (e.g., the touch sensor IC253) of the touch circuit250may be included as a part of another element (e.g., the auxiliary processor123) disposed outside the display module160.

According to an embodiment, the display module160may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor, or an illuminance sensor) of the sensor module176, or a control circuit therefor. The at least one sensor or the control circuit therefor may be embedded in a part (e.g., the display200or the DDI230) of the display module160or in a part of the touch circuit250. For example, when the sensor module176embedded in the display module160includes a biosensor (e.g., a fingerprint sensor), the biosensor may acquire, through a partial region of the display200, biometric information (e.g., a fingerprint image) associated with a touch input. In another example, when the sensor module176embedded in the display module160includes a pressure sensor, the pressure sensor may acquire pressure information associated with a touch input through a partial region or the entire region of the display200. According to an embodiment, the touch sensor251or the sensor module176may be disposed between pixels of a pixel layer of the display200, or on or beneath the pixel layer.

FIG. 3illustrates the flat (e.g., opened) state of an electronic device according to various embodiments of the disclosure.FIG. 4illustrates the folded (e.g., closed) state of an electronic device according to various embodiments of the disclosure.

Referring toFIGS. 3 and 4, an electronic device101may include a housing300, a hinge cover330configured to cover a foldable part of the housing300, and a display200disposed in a space formed by the housing300. In an embodiment, the display200may be a flexible display or a foldable display.

A surface on which the display200is disposed may be defined as a first surface, or the front surface of the electronic device101. Further, a surface opposite to the front surface may be defined as a second surface, or the rear surface of the electronic device101. Further, a surface surrounding a space between the front surface and the rear surface may be defined as a third surface, or the side surface of the electronic device101. For example, the electronic device101may be folded or unfolded in a first direction (e.g., the X-axis direction) with reference to a folding region203.

In an embodiment, the housing300may include a first housing structure310, a second housing structure320including a sensor region324, a first rear cover380, and a second rear cover390. The housing300of the electronic device101is not limited to the type or the coupling, illustrated inFIGS. 3 and 4, and may be implemented by another shape or another combination and/or coupling of components. For example, in another embodiment, the first housing structure310and the first rear cover380may be integrally formed, and the second housing structure320and the second rear cover390may be integrally formed.

In the illustrated embodiment, the first housing structure310and the second housing structure320may be disposed at opposite sides about a folding axis A, and may have shapes which are overall symmetric with respect to the folding axis A. The angle or distance formed between the first housing structure310and the second housing structure320may vary depending on whether the electronic device101is in a flat state, is in a folded state, or is in an intermediate state. In the illustrated embodiment, the second housing structure320, unlike the first housing structure310, may additionally include the sensor region324in which various sensors are disposed, but may have a shape symmetric with that of the second housing structure320in other regions.

In an embodiment, the first housing structure310and the second housing structure320may form a recess for receiving the display200together. In the illustrated embodiment, due to the sensor region324, the recess may have at least two different widths in a direction (e.g., the x-axis direction) perpendicular to the folding axis A.

For example, the recess may have a first width W1between a first part310aof the first housing structure310and a first part320aof the second housing structure320, formed at the edge of the sensor region324of the second housing structure320. The recess may have a second width W2formed between a second part310bof the first housing structure310, parallel to the folding axis A, in the first housing structure310and a second part320bof the second housing structure320, which is parallel to the folding axis A and does not correspond to the sensor region324, in the second housing structure320. The second width W2may be formed to be larger than the first width W1. In other words, the first part310aof the first housing structure310and the first part320aof the second housing structure320, which have asymmetrical shapes, may form the first width W1of the recess. The second part310bof the first housing structure310and the second part320bof the second housing structure320, which have symmetrical shapes, may form the second width W2of the recess.

In an embodiment, the first part320aand the second part320bof the second housing structure320may have different distances from the folding axis A. The width of the recess is not limited to the illustrated example. In various embodiments, the recess may have multiple widths on the basis of the shape of the sensor region324or parts of the first housing structure310and the second housing structure320, which have asymmetrical shapes.

In an embodiment, the first housing structure310and the second housing structure320may be at least partially formed of a metal or nonmetal material having rigidity, the magnitude of which is selected to support the display200.

In an embodiment, the sensor region324may be formed to have a predetermined region adjacent to one corner of the second housing structure320. However, the arrangement, shape, and size of the sensor region324are not limited to the illustrated example. For example, in another embodiment, the sensor region324may be provided at another corner of the second housing structure320or in a predetermined region between the top corner and the bottom corner. In an embodiment, components, embedded in the electronic device101so as to perform various functions, may be exposed on the front surface of the electronic device101through the sensor region324or through at least one opening provided in the sensor region324. In various embodiments, the components may include various types of sensors. The sensors may include one or more of a front camera, a receiver, or a proximity sensor.

The first rear cover380may be disposed at one side of the folding axis A on the rear surface of the electronic device, and, for example, may have a substantially rectangular periphery. The periphery may be surrounded by the first housing structure310. Similarly, the second rear cover390may be disposed at the other side of the folding axis A on the rear surface of the electronic device, and the periphery thereof may be surrounded by the second housing structure320.

In the illustrated embodiment, the first rear cover380and the second rear cover390may have substantially symmetrical shapes with reference to the folding axis A. However, the first rear cover380and the second rear cover390do not necessarily have symmetrical shapes, and in another embodiment, the electronic device101may include the first rear cover380and the second rear cover390, which have various shapes. In another embodiment, the first rear cover380may be formed integrally with the first housing structure310, and the second rear cover390may be formed integrally with the second housing structure320.

In an embodiment, the first rear cover380, the second rear cover390, the first housing structure310, and the second housing structure320may form a space in which various components (e.g., a printed circuit board or a battery) of the electronic device101can be disposed. In an embodiment, one or more components may be disposed or visually exposed on the rear surface of the electronic device101. For example, at least a part of a sub-display290may be visually exposed through a first rear region382of the first rear cover380. In another embodiment one or more components or sensors may be visually exposed through a second rear region392of the second rear cover390. In various embodiments, the sensors may include a proximity sensor and/or a rear camera.

The hinge cover330may be disposed between the first housing structure310and the second housing structure320and configured to cover internal components (for example, a hinge structure). In an embodiment, the hinge cover330may be covered or exposed outside by a part of each of the first housing structure310and the second housing structure320, depending on the state (flat state or folded state) of the electronic device101.

In an embodiment, as illustrated inFIG. 3, when the electronic device101is in a flat state, the hinge cover330may be covered by the first housing structure310and the second housing structure320, and thus may not be exposed. In an embodiment, as illustrated inFIG. 4, when the electronic device101is in a folded state (e.g., a fully folded state), the hinge cover330may be exposed outside between the first housing structure310and the second housing structure320. In an embodiment, in an intermediate state in which the first housing structure310and the second housing structure320are folded with a certain angle, the hinge cover330may be partially exposed outside between the first housing structure310and the second housing structure320. However, in this case, an exposed region may be smaller than that in the fully folded state. In an embodiment, the hinge cover330may include a curved surface.

The display200may be disposed in a space formed by the housing300. For example, the display200may be seated in a recess formed by the housing300, and may form most of the front surface of the electronic device101.

Therefore, the front surface of the electronic device101may include the display200, and a partial region of the first housing structure310and a partial region of the second housing structure320, which are adjacent to the display200. Further, the rear surface of the electronic device101may include the first rear cover380, a partial region of the first housing structure310adjacent to the first rear cover380, the second rear cover390, and a partial region of the second housing structure320adjacent to the second rear cover390.

The display200may imply a display having at least a partial region which can be deformed into a flat surface or a curved surface. In an embodiment, the display200may include the folding region203, and a first region201, disposed at one side (at the left of the folding region203illustrated inFIG. 3), and a second region202, disposed at the other side (the right side of the folding region203illustrated inFIG. 3), with reference to the folding region203. The display200may include a polarizing film (or a polarizing layer), a window glass (e.g., ultra-thin glass (UTG) or a polymer window), and an optical compensation film (OCF).

The division of the region of the display200is for the illustrative purposes, and the display200may be divided into multiple (for example, at least four or two) regions depending on the structure or functions thereof. In an embodiment, the region of the display200may be divided by the folding region203or the folding axis A, which extends parallel to the y-axis. However, in another embodiment, the region of the display200may be divided with reference to another folding region (e.g., a folding region parallel to the x-axis) or another folding axis (e.g., a folding axis parallel to the x-axis).

The first region201and the second region202may have overall symmetrical shapes about the folding region203. Unlike the first region201, the second region202may include a cut notch due to the presence of the sensor region324, but may have a shape symmetrical with that of the first region201in other regions. In other words, the first region201and the second region202may include parts having symmetrical shapes and parts having asymmetrical shapes.

Hereinafter, a description will be made of operations of the first housing structure310and the second housing structure320and each region of the display200according to the state (e.g., a flat state and a folded state) of the electronic device101.

In an embodiment, when the electronic device101is in a flat state (e.g.,FIG. 3), the first housing structure310and the second housing structure320may be placed to face an identical direction while forming an angle of 180 degrees therebetween. The surface of the first region201of the display200and the surface of the second region202may form 180 degrees therebetween, and may face an identical direction (e.g., toward the front surface of the electronic device). The folding region203may form an identical flat surface together with the first region201and the second region202.

In an embodiment, when the electronic device101is in a folded state) (e.g.,FIG. 4), the first housing structure310and the second housing structure320may be placed to face each other. The surface of the first region201of the display200and the surface of the second region202may face each other while forming a narrow angle (e.g., 0 to 10 degrees) therebetween. At least a part of the folding region203may be formed as a curved surface having a predetermined curvature.

In an embodiment, when the electronic device101is in an intermediate state (a half folded state), the first housing structure310and the second housing structure320may be placed to have a certain angle. The surface of the first region201of the display200and the surface of the second region202may form a larger angle than the folded state and a smaller angle than the flat state. The folding region203may be at least partially formed as a curved surface having a predetermined curvature. In this time, the curvature may be smaller than that in the folded state.

FIG. 5is a block diagram of a display module according to an embodiment of the disclosure.

The display module160illustrated inFIG. 5may be at least partially similar to the display module160illustrated inFIG. 1and/orFIG. 2, or may include another embodiment.

Referring toFIG. 5, the display module160according to an embodiment may include a display panel510, a data controller520, a gate controller530, a timing controller540, and/or a memory550(e.g., dynamic random access memory (DRAM)).

According to various embodiments, at least some of the data controller520, the gate controller530, the timing controller540, and/or the memory550(e.g., the dynamic random access memory (DRAM)) may be disposed in a DDI (e.g., the DDI230inFIG. 2).

According to an embodiment, the data controller520, the timing controller540, and/or the memory550(e.g., the dynamic random access memory (DRAM)) may be disposed on the DDI230(e.g., the DDI230inFIG. 2), and the gate controller530may be disposed in a non-display region (e.g., a non-display region616inFIG. 6) of the display panel510.

According to an embodiment, the display panel510may include multiple gate lines (GLs) and multiple data lines (DLs). According to an embodiment, the multiple gate lines (GLs) may be formed in a first direction (e.g., the transverse direction inFIG. 5), and may be disposed at a designated interval.

According to an embodiment, the multiple data lines (DLs) may be formed, for example, in a second direction (e.g., the longitudinal direction inFIG. 5) perpendicular to the first direction, and may be disposed at a designated interval.

In various embodiments of the disclosure, “the scan direction of the display panel510” may be defined as a vertical direction (e.g., the transverse direction inFIG. 5) in which the gate lines (GLs) are formed. For example, when multiple gate lines (GLs) are formed in a first direction (e.g., the transverse direction inFIG. 5), the scan direction of the display panel510may be defined as a second direction (e.g., the longitudinal direction inFIG. 5) perpendicular to the first direction.

According to an embodiment, pixels (P) may be disposed in each of some regions of the display panel510, in which the multiple gate lines (GLs) cross the multiple data lines (DLs). According to an embodiment, each pixel (P) may display a designated gradation by being electrically connected to a gate line (GL) and a data line (DL).

According to an embodiment, each pixel (P) may receive an input of a gate scan signal and a light-emission signal through a gate line (GL), and may receive an input of a data signal through a data line (DL). According to an embodiment, each pixel (P) may receive input of a high potential voltage (e.g., an ELVDD voltage) and a low potential voltage (e.g., an ELVSS voltage) as power for driving an organic light emitting diode (OLED).

According to an embodiment, each pixel (P) may include an OLED and a pixel driving circuit (not shown) for driving the OLED. According to various embodiments, the structure of each pixel (P) and the structure of the pixel driving circuit may be at least partially similar or identical to the structure of a pixel (P) and the pixel driving circuit, disclosed in Korean Registered Patent Publication No. 10-2189223.

According to an embodiment, the pixel driving circuit disposed in each pixel (P) may control, based on the gate scan signal and the light-emission signal, turning-on (an enabled state) or turning-off (e.g., a disabled state) of the OLED.

According to an embodiment, when being in a turned-on state (e.g., an enabled state), the OLED of each pixel (P) may display a gradation (e.g., luminance) corresponding to a data signal during a period of one frame.

According to an embodiment, the data controller520may drive multiple data lines (DLs). According to an embodiment, the data controller520may receive inputs of at least one synchronization signal and a data signal (e.g., digital image data) from the timing controller540or a processor120(e.g., the processor120inFIG. 1). According to an embodiment, the data controller520may determine a data voltage (e.g., analog image data) corresponding to the input data signal by using a reference gamma voltage and a designated gamma curve. According to an embodiment, the data controller520may apply the data voltage to the multiple data lines (DLs), thereby supplying the data voltage to each pixel (P).

According to an embodiment, the data controller520may receive inputs of multiple synchronization signals having an identical frequency or difference frequencies from the timing controller540or the processor120(e.g., the processor120inFIG. 1).

In an example, the data controller520may receive an input of a first synchronization signal having a first frequency (e.g., 30 Hz), a second synchronization signal having a second frequency (e.g., 60 Hz) higher than the first frequency, a third synchronization signal having a third frequency (e.g., 120 Hz) higher than the second frequency, or a fourth synchronization signal having a fourth frequency (e.g., 240 Hz) higher than the third frequency.

According to an embodiment, multiple synchronization signals may be frequency control signals generated by the processor120when the electronic device101drives a display (e.g., the display200inFIG. 2) through a split screen. For example, the processor120may execute a first application and a second application, and then may display an execution screen of the first application through a first part (e.g., the first region201inFIG. 3or a first region612inFIG. 6) of the display panel510and may display an execution screen of the second application through a second part (e.g., the second region202inFIG. 3or a second region614inFIG. 6) of the display panel510.

According to an embodiment, the processor120may independently control a driving frequency of the execution screen of the first application, displayed through the first part (e.g., the first region201inFIG. 3or the first region612inFIG. 6), and a driving frequency of the execution screen of the second application, displayed through the second part (e.g., the second region202inFIG. 3or the second region614inFIG. 6).

According to an embodiment, in order to control the first part (e.g., the first region201inFIG. 3or the first region612inFIG. 6) and the second part (e.g., the second region202inFIG. 3or the second region614inFIG. 6) in a first driving frequency (e.g., 120 Hz), the processor120may supply a first synchronization signal corresponding to the first driving frequency to the data controller520.

According to an embodiment, in order to control the first part (e.g., the first region201inFIG. 3or the first region612inFIG. 6) in the first driving frequency (e.g., 120 Hz), the processor120may supply the first synchronization signal corresponding to the first driving frequency to the data controller520, and, in order to control the second part (e.g., the second region202inFIG. 3or the second region614inFIG. 6) in a second driving frequency (e.g., 60 Hz), may supply a second synchronization signal corresponding to the second driving frequency to the data controller520.

According to an embodiment, the data controller520may apply a data voltage corresponding to the first driving frequency (e.g., 120 Hz) to some data lines (DLs) corresponding to the first part (e.g., the first region201inFIG. 3or the first region612inFIG. 6) among the multiple data lines (DLs). In addition, the data controller520may apply a data voltage corresponding to the second driving frequency (e.g., 60 Hz) to some data lines (DLs) corresponding to the second part (e.g., the second region202inFIG. 3or the second region614inFIG. 6) among the multiple data lines (DLs).

According to an embodiment, the gate controller530may drive the multiple gate lines (GLs). According to an embodiment, the gate controller530may receive an input of at least one synchronization signal from the timing controller540or the processor120(e.g., the processor120inFIG. 1).

According to an embodiment, the gate controller530may include a gate driver531(e.g., scan driver) for sequentially generating multiple gate scan signals on the basis of the synchronization signal and supplying the generated multiple gate scan signals to the gate lines (GLs).

According to an embodiment, the gate controller530may include a light-emission driver532for sequentially multiple light-emission signals on the basis of the synchronization signal and supplying the generated light-emission signals to the gate lines (GLs).

For example, each gate line (GL) may include a gate signal line (SCL), to which a gate scan signal is applied, and/or a light-emission signal line (EML), to which a light-emission signal is applied.

According to an embodiment, the gate controller530may receive synchronization signals that have an identical frequency and are input from the timing controller540or the processor120(e.g., the processor120inFIG. 1). In an embodiment, the gate controller530may apply a gate scan signal and/or a light-emission signal, corresponding to a first driving frequency (e.g., 120 Hz), to some gate lines (GLs) corresponding to the first part (e.g., the first region201inFIG. 3or the first region612inFIG. 6) among the multiple gate lines (GLs), and may apply a gate scan signal and/or a light-emission signal, corresponding to the first driving frequency (e.g., 120 Hz), to some gate lines (GLs) corresponding to the second part (e.g., the second region202inFIG. 3or the second region614inFIG. 6) among the multiple gate lines (GLs).

In another embodiment, the gate controller530may receive multiple synchronization signals which have different frequencies and are input from the timing controller540or the processor120(e.g., the processor120inFIG. 1). In an embodiment, the gate controller530may apply a gate scan signal and/or a light-emission signal, corresponding to a first driving frequency (e.g., 120 Hz), to some gate lines (GLs) corresponding to the first part (e.g., the first region201inFIG. 3or the first region612inFIG. 6) among the multiple gate lines (GLs), and may apply a gate scan signal and/or a light-emission signal, corresponding to a second driving frequency (e.g., 60 Hz), to some gate lines (GLs) corresponding to the second part (e.g., the second region202inFIG. 3or the second region614inFIG. 6) among the multiple gate lines (GLs).

According to an embodiment, the timing controller540may control driving timing of the gate controller530and the data controller520. According to an embodiment, the timing controller540may acquire a data signal (e.g., digital image data) for one frame. According to an embodiment, the timing controller540may receive the data signal for one frame from the processor120. According to an embodiment, the timing controller540may refer to the memory550(e.g., DRAM), which stores a data signal of a previous frame, so as to perform control such that at least a part of the display panel510displays an image of the previous frame, based on a designated event.

According to an embodiment, the timing controller540may convert the acquired data signal (e.g., the digital image data) so as to correspond to the resolution of the display panel510, and may supply the converted data signal to the data controller520.

FIG. 6illustrates a placement type of a display driver IC (DDI)630in a foldable display600.

Referring toFIG. 6, the foldable display600may include a display panel610and the DDI630.

According to an embodiment, the display panel610may include a first region612and a second region614. In an embodiment, the first region612and the second region614of the display panel610may be folded or unfolded in a first direction (e.g., the x-axis direction) with reference to a folding axis.

In an embodiment, the display panel610is folded with reference to the folding axis, and thus multiple gate lines620may be formed in a second direction (e.g., the y-axis direction).

According to an embodiment, the display panel610is folded with reference to the folding axis, and thus the DDI630may be disposed in a non-display region616of one side of the display panel610in the first direction (e.g., the x-axis direction). That is, the DDI630may be disposed in the non-display region616of a side parallel to the folding axis.

FIG. 7illustrates a jelly-scroll effect caused when an image700displayed on a foldable display moves in the vertical direction.

Referring toFIG. 7, a gate scan may start from a gate line of a first part (A) and the scan may end in a gate line of a second part (B). When the image700is moved (e.g. scrolled) in the vertical direction in the display panel610, a speed difference may be caused in updating of the image700. That is, a speed difference may be caused, depending on the position of a gate line, in updating of the image700in each pixel.

The electronic device of the disclosure may maintain a gate scan speed as the gate scan speed is, when driving the display panel610and increase a light-emission scan (EM scan) speed, thereby preventing a jelly-scroll effect from being caused. The electronic device according to various embodiments of the disclosure may not increase the driving speed of the DDI, and may prevent a jelly-scroll effect to prevent an increase in power consumption and a rise in a component price.

FIG. 8illustrates a display module800according to an embodiment of the disclosure.

Referring toFIG. 8, the display module800according to an embodiment of the disclosure may include a DDI810, a gate driver820(e.g., a scan driver), a light-emission driver830, and a display840.

The display840may include multiple gate lines (e.g., the multiple gate lines (GLs) inFIG. 5) and multiple data lines (e.g., the multiple data lines (DLs) inFIG. 5). According to an embodiment, the multiple gate lines (GLs) may be formed in a first direction (e.g., the x-axis direction), and may be disposed at a designated interval. According to an embodiment, the multiple data lines (DLs) may be formed, for example, in a second direction (e.g., the y-axis direction) perpendicular to the first direction, and may be disposed at a designated interval. According to an embodiment, each gate line (GL) may include gate signal lines (e.g., the gate signal lines (SCLs) inFIG. 5), to which a gate scan signal is applied, and/or light-emission signal lines (e.g., light-emission signal lines (EMLs) inFIG. 5), to which a light-emission signal is applied.

According to an embodiment, the DDI810may include a first signal generator812and a second signal generator814. The first signal generator812may be electrically connected to the gate driver820. The second signal generator814may be electrically connected to the light-emission driver830.

In an embodiment, the first signal generator812may generate, based on a synchronization signal and a control signal input from a timing controller (e.g., the timing controller540inFIG. 5), first clocks816for driving the gate driver820and first control signals818for controlling the gate driver820. The first clocks816and the first control signals818, generated by the first signal generator812, may be supplied to the gate driver820.

In an embodiment, the second signal generator814may generate, based on a synchronization signal and a control signal input from a timing controller (e.g., the timing controller540inFIG. 5), second clocks822for driving the light-emission driver830and second control signals824for controlling the light-emission driver830. The second clocks822and the second control signals824, generated by the second signal generator814, may be supplied to the light-emission driver830.

In an embodiment, the gate signal lines (SCLs) may be electrically connected to the gate driver820. The light-emission signal lines (EMLs) may be electrically connected to the light-emission driver830.

In an embodiment, the gate driver820may generate multiple gate scan signals on the basis of the first clocks816and the first control signals818, which are input from the first signal generator812. The multiple gate scan signals generated by the gate driver820may be sequentially applied to the gate signal lines (SCLs) disposed in the display840.

In an embodiment, the light-emission driver830may generate multiple light-emission signals on the basis of the second clocks822and the second control signals824, which are input from the second signal generator814. The multiple light-emission signals, generated by the light-emission driver830, may be applied to the light-emission signal lines (EMLs) disposed in the display840.

According to an embodiment, the multiple gate scan signals of the gate driver820and the multiple light-emission signals of the light-emission driver830may be generated to have an identical frequency.

According to an embodiment, a first scan speed of the multiple gate scan signals may be different from a second scan speed of the multiple light-emission signals.

In an embodiment, the multiple gate scan signals that are output from the gate driver820and applied to the display840may have a first scan speed.

In an embodiment, the multiple light-emission signals that are output from the light-emission driver830and applied to the display840may have a second scan speed higher than the first scan speed.

FIG. 9illustrates a display module900according to an embodiment of the disclosure. In describingFIG. 9, a detailed description of the same elements as those of the display module800illustrated inFIG. 8may be omitted.

Referring toFIG. 9, the display module900according to an embodiment of the disclosure may include a DDI910, a gate driver920, a light-emission driver930, and a display940.

The display940may include multiple gate lines (e.g., the multiple gate lines (GLs) inFIG. 5) and multiple data lines (e.g., the multiple data lines (DLs) inFIG. 5). According to an embodiment, each gate line (GL) may include gate signal lines (e.g., the gate signal lines (SCLs) inFIG. 5), to which a gate scan signal is applied, and/or light-emission signal lines (e.g., light-emission signal lines (EMLs) inFIG. 5), to which a light-emission signal is applied.

According to an embodiment, the DDI910may include a signal generator912and a signal modulator914. InFIG. 9, the signal modulator914is disposed in the DDI910. However, the signal modulator914may be disposed as a separate element outside the DDI910.

In an embodiment, the signal generator912may be electrically connected to the gate driver920. The signal modulator914may be electrically connected to the light-emission driver930.

In an embodiment, the signal generator912may generate, based on a synchronization signal and a control signal input from a timing controller (e.g., the timing controller540inFIG. 5), first clocks916for driving the gate driver920and first control signals918for controlling the gate driver920. The first clocks916and the first control signals918, generated by the signal generator912, may be supplied to the gate driver920.

In an embodiment, the signal modulator914may receive the first clocks916and the first control signals918, which are output from the signal generator912.

The signal modulator914may modulate the received first clocks916and the received first control signals918to generate second clocks922for driving the light-emission driver930and second control signals924for controlling the light-emission driver930. The second clocks922and the second control signals924, generated by the signal modulator914, may be supplied to the light-emission driver930.

In an embodiment, the gate signal lines (SCLs) may be electrically connected to the gate driver920. The light-emission signal lines (EMLs) may be electrically connected to the light-emission driver930.

In an embodiment, the gate driver920may generate multiple gate scan signals on the basis of the first clocks916and the first control signals918that are input from the signal generator912. The multiple gate scan signals that have been generated by the gate driver920may be sequentially applied to the gate signal lines (SCLs) disposed in the display940.

In an embodiment, the light-emission driver930may generate multiple light-emission signals on the basis of the second clocks922and the second control signals924that are input from the signal modulator914. The multiple light-emission signals that have been generated by the light-emission driver930may be applied to the light-emission signal lines (EMLs) disposed in the display940.

According to an embodiment, the multiple gate scan signals of the gate driver920and the multiple light-emission signals of the light-emission driver930may be generated to have an identical frequency.

According to an embodiment, a first scan speed of the multiple gate scan signals may be different from a second scan speed of the multiple light-emission signals.

In an embodiment, the multiple gate scan signals that are output from the gate driver920and applied to the display940may have a first scan speed.

In an embodiment, the multiple light-emission signals that are output from the light-emission driver930and applied to the display940may have a second scan speed higher than the first scan speed.

FIG. 10illustrates a method for operating an electronic device according to an embodiment of the disclosure.

FIG. 11illustrates multiple gate scan signals and multiple light-emission signals applied to a display panel according to an embodiment of the disclosure.

Referring toFIGS. 10 and 11, an electronic device (e.g., the electronic device101inFIG. 1or the electronic device101inFIG. 3) according to an embodiment of the disclosure may drive a display panel (e.g., the display panel610inFIG. 6) in a first frequency (e.g., 120 Hz). When the display panel (e.g., the display panel610inFIG. 6) is driven in 120 Hz, a period of one frame may be about 8.3 ms.

The electronic device according to an embodiment of the disclosure may operate multiple gate scan signals1010at a first scan speed, and may operate multiple light-emission signals1020at a second scan speed higher than the first scan speed. Here, the multiple gate scan signals1010and the multiple light-emission signals1020may be generated as active-high signals.

According to an embodiment, a processor (e.g., the processor120inFIG. 1) may separately designate the number of pixels for calculating one horizontal period (1H) in the display module, such that the multiple gate scan signals1010and the multiple light-emission signals1020have different speeds.

In an embodiment, the processor (e.g., the processor120inFIG. 1) may separately designate the number of pixels for calculating one horizontal period (1H) by a gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) and a light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9).

For example, the processor (e.g., the processor120inFIG. 1) may set the number of pixels for calculating one horizontal period (1H) by the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) to a first number. The processor (e.g., the processor120inFIG. 1) may set the number of pixels for calculating one horizontal period (1H) by the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) to a second number greater than the first number. When the number of pixels for calculating one horizontal period (1H) by the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) is set to the second number greater than the first number, the one horizontal period (1H) calculated by the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) may be shorter than the one horizontal period (1H) calculated by the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9).

In an embodiment, the processor (e.g., the processor120inFIG. 1) may configure a frequency of a first clock, applied to the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9), and a frequency of a second clock, applied to the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9), to be different from each other.

In an embodiment, the processor (e.g., the processor120inFIG. 1) may apply a first clock having a first frequency to the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9). The processor (e.g., the processor120inFIG. 1) may apply a second clock having a second frequency higher than the first frequency to the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9).

In an embodiment, the first clock applied to the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) and the second clock applied to the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) may have different frequencies, and thus the speed of the multiple gate scan signals1010may be different from the speed of the multiple light-emission signals1020.

In an embodiment, since the second frequency of the second clock is higher than the first frequency of the first clock, the speed of the multiple light-emission signals1020may be made to be higher than the speed of the multiple gate scan signals1010. The multiple gate scan signals1010may be sequentially applied to multiple gate signal lines (e.g., the multiple gate signal lines (SCLs) inFIG. 5) at a first speed during a period of one frame. The multiple light-emission signals1020may be applied to multiple light-emission signal lines (e.g., the light-emission lines (EMSs) inFIG. 5) at a second speed higher (e.g., greater) than the first speed during the period of one frame.

In an embodiment, a light-emission scan may be started (e.g., at timing1003) by supply of a first light-emission signal1020to a first light-emission signal line (EML) after a first time period (ΔT) elapses from a timing1001at which a gate scan is started by supply of a first gate scan signal1010to a first gate signal line (SCL). That is, a gate scan operation may be performed for the full time of one frame (e.g., a first time period). A light-emission scan operation may be performed for a time (e.g. a second time period) obtained by subtracting the first time period (ΔT) from the full time of one frame. Therefore, during the period of one frame, the time for the gate scan operation becomes longer than the time for the light-emission scan operation. That is, during the period of one frame, the time for the light-emission scan operation becomes shorter than the time for the gate scan operation. During the period of one frame, the longer the first time period (ΔT) is, the faster the speed of the light-emission scan may be.

In an embodiment, in the display panel (e.g., the display panel610inFIG. 6), the order of a light-emission signal off (EM scan off) operation, a gate scan operation, and a light-emission scan operation may be maintained without being changed.

In an embodiment, the light-emission signal off (EM scan off) operation and the light-emission scan operation may be performed by the same light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9), and thus a light-emission off signal1030and a light-emission signal1020may be scanned at the same speed.

In an example, a gate scan operation for all gate signal lines (SCLs) may be performed between a first timing1001, at which scanning of the light-emission off signal1030is started, and a second timing1002, at which scanning of the light-emission signals1020is ended, during a period of one frame.

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may separate trigger signals that are applied to the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) and the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) so that a first start timing of the gate scan operation is different from a second start timing of the light-emission scan operation. That is, the processor (e.g., the processor120inFIG. 1) may separate trigger signal applied to the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) and the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) to adjust the first time period (ΔT) in the period of one frame. For example, the processor (e.g., the processor120inFIG. 1) may control a first trigger signal to be applied to the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) at a first timing. The processor (e.g., the processor120inFIG. 1) may control a second trigger signal to be applied to the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9) after the first time period (ΔT) elapses from the first timing.

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may control operations of a horizontal period (H) counter or a clock counter such that a first start timing of a gate scan operation by the gate driver (e.g., the gate driver820inFIG. 8or the gate driver920inFIG. 9) is different from a second start timing of a light-emission scan operation by the light-emission driver (e.g., the light-emission driver830inFIG. 8or the light-emission driver930inFIG. 9). That is, the processor (e.g., the processor120inFIG. 1) may control the operations of the horizontal period (H) counter or the clock counter to adjust the first time period (ΔT) in the period of one frame.

According to an embodiment, a light-emission signal1020is applied from a timing at which a data voltage is applied to each pixel of the display panel (e.g., the display panel610inFIG. 6), and thus times at which light-emission of the respective pixels actually starts may be different from each other.

In an embodiment, a brightness difference may be caused between respective (e.g., the display panel610inFIG. 6). The processor (e.g., the processor120inFIG. 1) may measure the brightness of each pixel through optical image-capturing, and may compensate for the brightness difference for each line (DL and GL620), based on the measured brightness of each pixel.

In an embodiment, a brightness difference may be caused between respective lines of the display panel (e.g., the display panel610inFIG. 6). The processor (e.g., the processor120inFIG. 1) may generate compensation data according to the brightness difference between the respective lines, based on a light-emission time difference between the respective lines, and may supply the compensation data to the DDI to perform source voltage compensation. The processor may compensate for the brightness difference for each line (DL and GL620) through the source voltage compensation.

FIG. 12illustrates a single gate scan operation and a multi-duty (or cycle) operation of a light-emission signal during a period of one frame according to an embodiment of the disclosure.

Referring toFIG. 12, according to various embodiments, an electronic device (e.g., the electronic device101inFIG. 1or the electronic device101inFIG. 3) may configure multiple duties (or cycles) of a light-emission signal output in each frame.

According to an embodiment, the electronic device101may drive a display panel (e.g., the display panel610inFIG. 6) in 120 Hz 2 duty (or cycle). In this case, the period of one frame may be about 8.3 ms corresponding to 120 Hz, and the length of a duty which one light-emission signal has may be about 4.15 ms.

In an embodiment, during a first period1201of a period of a half of a frame (about 4.15 ms), a gate scan signal1010may be sequentially applied to all gate signal lines (SCLs), and a gate scan operation may be performed. In an embodiment, during the first period1201of the period of a half of a frame (about 4.15 ms), a first light-emission scan operation may be performed, and thus all pixels may perform first light emission. Subsequently, during a second period1202, a light-emission signal off (EM scan off) operation may be performed, and second light-emission scan operation may be performed, and thus all pixels may perform second light emission.

As illustrated inFIG. 9, the electronic device101according to various embodiments may configure the number of duties (cycles) of a light-emission signal output during each frame as not only two but also four (e.g., four duties), six (e.g., six duties), or eight (e.g., eight duties).

When driving a display panel, the electronic device of the disclosure may maintain a gate scan speed as the gate scan speed is and increase a light-emission scan (EM scan) speed, thereby preventing a jelly-scroll effect from being caused. In various embodiments of the disclosure, the electronic device may not increase the driving speed of a DDI, and may prevent a jelly-scroll effect to prevent an increase of power consumption and a rise in component prices.

An electronic device (e.g., the electronic device101inFIG. 1or the electronic device101inFIG. 3) according to various embodiments of the disclosure may include a display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6), a display driver IC (DDI) (e.g., the DDI230inFIG. 2), a gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9), a light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9), and a processor (e.g., the processor120inFIG. 1). The display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6) may include multiple data lines, multiple gate signal lines (e.g., the gate signal line (SCL) inFIG. 5), and multiple light-emission signal (e.g., the light-emission signal1020inFIG. 10) lines (e.g., the light-emission signal (e.g., the light-emission signal1020inFIG. 10) lines (EMLs) inFIG. 5). The DDI (e.g., the DDI230inFIG. 2) may drive the display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6). The gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) may apply, based on control of the DDI (e.g., the DDI230inFIG. 2), gate scan signals (e.g., the gate scan signals1010inFIG. 10) to the multiple gate signal lines (e.g., the gate signal lines (SCLs) inFIG. 5). The light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9) may apply, based on control of the DDI (e.g., the DDI230inFIG. 2), light-emission signals (e.g., the light-emission signals1020inFIG. 10) to the multiple light-emission signal (e.g., the light-emission signal1020inFIG. 10) lines (e.g., the light-emission signal (e.g., the light-emission signal1020inFIG. 10) lines (EMLs) inFIG. 5). The processor (e.g., the processor120inFIG. 1) may control the DDI (e.g., the DDI230inFIG. 2). The processor (e.g., the processor120inFIG. 1) may control a first scan speed of the gate scan signals (e.g., the gate scan signals1010inFIG. 10) to be different from a second scan speed of the light-emission signals (e.g., the light-emission signals1020inFIG. 10).

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may make the second scan speed of the light-emission signals (e.g., the light-emission signals1020inFIG. 10) higher than the first scan speed of the gate scan signals (e.g., the gate scan signals1010inFIG. 10) during a period of one frame.

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may supply a first light-emission signal (e.g., the light-emission signal1020inFIG. 10) to a first light-emission signal (e.g., the light-emission signal1020inFIG. 10) line (e.g., the light-emission signal (e.g., the light-emission signal1020inFIG. 10) line (EML) inFIG. 5) after a first time period elapses from a timing at which a first gate scan signal (e.g., the gate scan signal1010inFIG. 10) has been supplied to a first gate signal line (e.g., the gate signal line (SCL) inFIG. 5).

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may make a second time period of a light-emission scan operation, at which the light-emission signals (e.g., the light-emission signals1020inFIG. 10) are supplied, shorter than a first time period of a gate scan operation, at which the gate scan signals (e.g., the gate scan signals1010inFIG. 10) are supplied, during a period of one frame.

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may configure the number of pixels for calculating one horizontal period by the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) to be different from the number of pixels for calculating one horizontal period by the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9).

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may configure a frequency of a first clock applied to the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) to be different from a frequency of a second clock applied to the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9).

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may apply a first clock having a first frequency to the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9), and may apply a second clock having a second frequency higher than the first frequency to the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9).

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may perform a gate scan operation for all gate signal lines (e.g., the gate signal line (SCL) inFIG. 5) between a first timing, at which scanning of a light-emission off signal is started, and a second timing, at which scanning of the light-emission signals (e.g., the light-emission signals1020inFIG. 10) is ended, during a period of one frame.

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may apply a first trigger signal to the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) at a first timing. Further, the processor may apply a second trigger signal to the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9) after the first time period elapses from the first timing.

According to an embodiment, the processor (e.g., the processor120inFIG. 1) may compensate, based on a difference in light-emission time of each line (DL and GL620) of the display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6), for a difference in luminance of each of the lines of the display panel.

In a method for operating an electronic device (e.g., the electronic device101inFIG. 1or the electronic device101inFIG. 3) according to various embodiments of the disclosure, a gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) may apply, at a first scan speed, gate scan signals (e.g., the gate scan signals1010inFIG. 10) to multiple data lines disposed in a display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6). A light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9) may apply, at a second scan speed, light-emission signals (e.g., the light-emission signals1020inFIG. 10) to multiple light-emission signal (e.g., the light-emission signal1020inFIG. 10) lines (e.g., the light-emission signal (e.g., the light-emission signal1020inFIG. 10) lines (EMLs) inFIG. 5) disposed in the display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6). A processor (e.g., the processor120inFIG. 1) may perform control such that the first scan speed of the gate scan signals (e.g., the gate scan signals1010inFIG. 10) is different from the second scan speed of the light-emission signals (e.g., the light-emission signals1020inFIG. 10).

According to an embodiment, the second scan speed of the light-emission signals (e.g., the light-emission signals1020inFIG. 10) may be made to be higher than the first scan speed of the gate scan signals (e.g., the gate scan signals1010inFIG. 10) during a period of one frame.

According to an embodiment, a first light-emission signal (e.g., the light-emission signal1020inFIG. 10) may be supplied to a first light-emission signal (e.g., the light-emission signal1020inFIG. 10) line (e.g., the light-emission signal (e.g., the light-emission signal1020inFIG. 10) line (EML) inFIG. 5) after a first time period elapses from a timing at which a first gate scan signal (e.g., the gate scan signal1010inFIG. 10) has been supplied to a first gate signal line (e.g., the gate signal line (SCL) inFIG. 5).

According to an embodiment, a second time period of a light-emission scan operation, at which the light-emission signals (e.g., the light-emission signals1020inFIG. 10) are supplied, may be made to be shorter than a first time period of a gate scan operation, at which the gate scan signals (e.g., the gate scan signals1010inFIG. 10) are supplied, during a period of one frame.

According to an embodiment, the number of pixels for calculating one horizontal period by the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) may be configured to be different from the number of pixels for calculating one horizontal period by the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9).

According to an embodiment, a frequency of a first clock applied to the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) may be configured to be different from a frequency of a second clock applied to the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9).

According to an embodiment, a first clock having a first frequency may be applied to the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9), and a second clock having a second frequency higher than the first frequency may be applied to the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9).

According to an embodiment, a gate scan operation for all gate signal lines (e.g., the gate signal lines (SCLs) inFIG. 5) may be performed between a first timing, at which scanning of a light-emission off signal is started, and a second timing, at which scanning of the light-emission signals (e.g., the light-emission signals1020inFIG. 10) is ended, during a period of one frame.

According to an embodiment, a first trigger signal may be applied to the gate driver (e.g., the gate driver531inFIG. 5, the gate driver820inFIG. 8, or the gate driver920inFIG. 9) at a first timing. Further, a second trigger signal may be applied to the light-emission driver (e.g., the light-emission driver532inFIG. 5, the light-emission driver830inFIG. 8, or the light-emission driver930inFIG. 9) after the first time period elapses from the first timing.

According to an embodiment, based on a difference in light-emission time of each line (DL and GL620) of the display panel (e.g., the display panel510inFIG. 5or the display panel610inFIG. 6), compensation may be made for a difference in luminance of each of the lines of the display panel.