Display method of display device

A display method includes steps of: receiving, by the controller, a first frame and a second frame from an input data; up-converting, by the controller, a frame rate of the input data to produce a third frame based on the first frame and the second frame; identifying, by the controller, a static image content of the third frame according to a comparison of the first frame and the second frame; controlling, by the controller, the driver circuit not to update data of pixels within a static display area of the display panel corresponding to the static image content during the period of time that the third frame is displayed by the display panel.

TECHNICAL FIELD

The disclosure relates to a display method of a display device.

BACKGROUND

Recently, high-resolution, high-frame-rate display devices such as 4K2K (4096*2160 pixels) liquid-crystal displays (LCDs) are developed. Under the circumstances, it is intended to use high-speed driver circuits to drive the display panel.

However, as the operation speed of a driver circuit increased, the power consumption of the driver circuit will be higher, causing the operating temperature to rise and adversely affecting the performance of the display device.

Therefore, there is a need to provide a display method capable of reducing the power consumption of driver circuits of a display device.

SUMMARY

The disclosure is directed to a display method of a display device, which can reduce the power consumption of driver circuits without adversely affecting the display quality.

According to an embodiment of the present invention, a display method of a display device including a controller, a display panel and a driver circuit responsive to the controller to drive the display panel is provided. The display method includes steps of: receiving, by the controller, a first frame and a second frame from an input data; up-converting, by the controller, a frame rate of the input data to produce a third frame based on the first frame and the second frame; identifying, by the controller, a static image content of the third frame according to a comparison of the first frame and the second frame; controlling, by the controller, the driver circuit not to update data of pixels within a static display area of the display panel corresponding to the static image content during the period of time that the third frame is displayed by the display panel.

DETAILED DESCRIPTION

FIG. 1illustrates a schematic diagram of a display device10according to an embodiment of the present invention. The display device10includes a controller108, a display panel106and a driver circuit12responsive to the controller108to drive the display panel106. The driver circuit12, for example, includes a gate driver102and a source driver104.

The gate driver102and the source driver104couple to a plurality of gate lines GL(1)-GL(M) and data lines DL(1)-DL(N), respectively, where M and N are integers. The display panel106includes a plurality of pixels PX defined by intersections of the gate lines GL(1)-GL(M) and the data lines DL(1)-DL(N). As shown inFIG. 1, pixels PX in the display panel106form an active matrix.

The controller108includes a frame rate controller1082and a timing controller1084. The frame rate controller1082may receive input data Din from an external video source (not shown) at a first frame rate. The frame rate controller1082may process the input data Din by using data compensation technique such as motion estimation motion compensation (MEMO), and output the processed data with a second frame rate to the timing controller1084. For high display quality, the second frame rate is usually greater than the first frame rate. For example, in a 4K2K display system, the frame rate (first frame rate) of the input data Din is 30 Hz, and the frame rate (second frame rate) of the processed data is 60 Hz or 120 Hz.

Response to the processed data from the frame rate controller1082, the timing controller1084may utilize synchronization signals and/or other timing signals to control the gate driver102and the source driver104to drive the gate lines GL(1)-GL(M) and the data lines DL(1)-DL(N) with specific driving schemes. When a gate line (e.g., GL(1)) is driven by the gate driver102, the gate line is enabled, and pixels PX coupled to the enabled gate line can be charged by the corresponding data lines (e.g., DL(1)-DL(N)).

FIG. 2illustrates a schematic flowchart of a display method of the display device10according to an embodiment of the present invention. In step202, the controller108receives a first frame and a second frame from the input data Din. The first frame and the second frame may be two successive frames in the input data Din.

In step204, the controller108up-converts the frame rate of the input data Din to produce a third frame based on the first frame and the second frame. The third frame can be deemed as an interleaved frame between the first and second frames in a time sequence, for constituting the processed data with higher frame rate. Taking a 60 Hz 4K2K LCD for example, the controller108may process an input data Din with 30 Hz of frame rate to output processed data with doubled frame rate. In such situation, odd frames (including the first and second frames) in the processed data are directly from the input data Din, and even frames (including the third frame) in the processed data are interleaved frames produced by data compensation technique such as MEMC.

The up-conversion of the frame rate of the input data Din can be implemented in various ways. For example, the controller108may interpolate the first frame and the second frame to produce the third frame. In another example, the controller108may repeat the first frame or the second frame, and take one of the duplicates as the third frame.

In step206, the controller108identifies static image content of the third frame according to a comparison of the first frame and the second frame. For example, the controller108may compare the first frame with the second frame, and recognize image content (e.g., background) that remains unchanged (or slightly changed) between the first and second frames as the static image content. Conversely, for image content (e.g., foreground) that varies in different frames, the controller108may identify it as dynamic image content.

In step208, the controller108controls the driver circuit12not to update data of pixels within a static display area of the display panel106corresponding to the static image content during the period of time that the third frame is displayed by the display panel106. The static display area described herein is an area of the display panel106for displaying the static image content of a frame. In an embodiment, the controller108may deactivate at least one of the gate driver102and the source driver104to hold data of pixels within the static display area during the period of time that the third frame is displayed. The deactivation of a gate driver, for example, includes operation of stopping enabling gate lines. The deactivation of a source driver, for example, includes operation of entering in a high-impedance mode or outputting signals to maintain data voltages on the data lines.

In another embodiment, the controller108may jump to updating data of pixels within a dynamic display area of the display panel106corresponding to the dynamic image content of the third frame by skipping updating data of pixels within the static display area of the display panel106in a frame time (which is defined by the second frame rate in step204ofFIG. 2for example). The dynamic display area described herein is an area of the display panel106for displaying the dynamic image content of a frame. Details about the abovementioned driving schemes will be further elaborated in connection withFIGS. 4-10.

Although data of pixels in the static display area of the display panel106may not be updated by the driver circuit12during the period of time that an interleaved frame (e.g., the third frame) is displayed, the static image content of the interleaved frame can still be correctly displayed on the display panel106because the pixels in the static display area may hold data voltages charged in the previous frame time (e.g., the frame time for the first frame). In this manner, the driver circuit12can drive the static display area of the display panel106with less update (refresh) frequency, and thus can be provided with reduced power consumption and lowered operating temperature.

FIG. 3illustrates a schematic diagram of a static display area STA and a dynamic display area DDA on the display panel. In this example, the displayed frame includes static image content in its upper portion and dynamic image content in its lower portion, which are displayed on the static display area STA and the dynamic display area DDA of the display panel106, respectively. As shown inFIG. 3, the static display area STA includes gate lines GL(1)-GL(i) disposed in the upper portion of the display panel106, and the dynamic display area DDA includes gate lines GL(i+1)-GL(M) disposed in the lower portion of the display panel106, where i is an integer and 1<i<M.

FIG. 4illustrates a schematic driving scheme for the display panel106. In this example, the up-converted input data to be displayed includes a sequence of frames402,404and406that each has static image content in the upper portion and has dynamic image content in the lower portion. Frames402,404and406are sequentially displayed on the display panel106, wherein frames402and406are from the input data Din, and frame404is an interleaved frame produced based on frames402and406.

In frame time FT402, the display panel106is driven by normal scheme. For example, the gate driver102may sequentially generate scan signals to enable each gate line GL(1)-GL(M), and meanwhile, the source driver104may correspondingly output data signals to the pixels PX coupled to each gate line GL(1)-GL(M), so that the previous displayed content on the display panel106can be updated to frame402. Understandably, the present invention is not limited thereto, and the normal scheme described herein can be implemented by any other known frame-refreshing approaches.

In frame time FT404, the display panel106is driven by the proposed power saving scheme to display frame404. The controller108controls the driver circuit12not to update the displayed content of the static display area STA by deactivating the gate driver102and the source driver104(the update-disabled area is represented as a shadowed region in the figure), and further controls the driver circuit12updates date of pixels within the dynamic display area DDA only.

In frame time FT406, the display panel106is driven by the abovementioned normal scheme to update the displayed content to frame406. With the illustrated driving scheme, the equivalent frame rate for the static image content in different frames can be reduced by one-half, so the driver circuit12can be provided with reduced power consumption.

FIG. 5illustrates a schematic timing chart of operations of the display panel106during the frame time FT402and FT404shown inFIG. 4.

In frame time FT402, the gate driver102sequentially enables rows of pixels PX by applying scan signals GS to the gate lines GL(1)-GL(M), such that each pixel on the display panel106can be charged to new pixel data for frame402. By this way, the previous displayed content on the display panel106is updated to frame402.

Then, during a first half of frame time FT404, both the gate driver102and source driver104are deactivated by the controller108, such that data of pixels in the static display area STA are maintained but not updated by new frame data for frame404.

During a second half of frame time FT404, the gate driver102and the source driver104are reactivated. The gate driver102sequentially outputs scan signals GS to each gate line disposed in the dynamic display area DDA, and meanwhile, the source driver104correspondingly outputs new pixel data for frame404to the data lines, such that the displayed content of the dynamic display area DDA are updated to the dynamic image content of frame404.

FIG. 6illustrates another schematic driving scheme of the display panel106. In the example ofFIG. 6, frames602and608are successive frames from the input data Din, and frames604and606are interleaved frames produced based on frames602and608by MEMC technique for example.

The static/dynamic image content of the interleaved frames604and606can be identified by comparing image contents of frames602and608. For example, given that both frames602and608include static image content in their upper portion and include dynamic image content in their lower portion, the interleaved frames604and606, which are produced based on the frames602and608, can also be identified as including static image content in their upper portion and including dynamic image content in their lower portion.

In frame time FT602, the display panel106is driven by normal scheme. The driver circuit12is activated to update the whole displayed content to frame602.

Then, in frame time FT604and FT606, the display panel106is driven by the proposed power saving scheme. The controller108deactivates the driver circuit12to disable the update of the displayed content of the static display area STA, and reactivate the driver circuit12to update the displayed content of the dynamic display area DDA to the dynamic image content of frame604/606.

Next, in frame time FT608, the display panel106is driven by normal scheme again. The controller108activates the driver circuit12to update the whole displayed content on the display panel106to frame608.

Although the number of interleaved frames between frames602and608is exemplified by two inFIG. 6, the present invention is not limited thereto. The number of interleaved frames can be arbitrary, depending on different display applications.

Further, in some embodiments, the display panel106can be driven with normal scheme to display one or more interleaved frames containing static image content, to avoid data voltages hold by pixels in the static display area from decaying to a level which may adversely affect the display quality.

FIG. 7illustrates another schematic driving scheme of the display panel106. In the example ofFIG. 7, frames702and706are successive frames from the input data Din, and frame704is an interleaved frame produced based on frames702and706.

In this example, frames702and706are static images (i.e., only static image content is included), so the interleaved frame704is a static image, too.

In frame time FT702, the display panel106is driven by normal scheme. The controller108controls the driver circuit12to update the whole displayed content to frame702.

Then, in frame time FT704, the display panel106is driven by the proposed power saving scheme. To reduce power consumption, the controller108deactivates the driver circuit12to disable the update of pixel data for the static display area STA (the update-disabled area is represented as a shadowed region in the figure), such that pixels on the display panel106hold data voltages charged in the previous frame time, i.e., frame time FT702.

Next, in frame time FT706, the display panel106is driven by normal scheme. The controller108activates the driver circuit12to update the whole displayed content on the display panel106to frame706.

FIG. 8illustrates another schematic driving scheme of the display panel106. In the example ofFIG. 8, frames802and806are successive frames from the input data Din, and frame804is an interleaved frame produced based on frames802and806.

In this example, frames802and806include dynamic image content in their upper-right portion and static image content in their upper-left portion and lower portion. Thus, for the gate lines (e.g., GL(1)-GL(i)) disposed in the upper portion of the display panel106, they may pass through both the static display area STA and the dynamic display area DDA, while for the gate lines (e.g., GL(i+1)-GL(M)) disposed in the lower portion of the display panel106, they pass through the static display area STA only.

In frame time FT802, the display panel106is driven by normal scheme. The controller108controls the driver circuit12to update the previous displayed content on the display panel106to frame802.

In frame time FT804, to avoid losing any information of the dynamic image content, the update of displayed content for any display area that includes gate lines (e.g., GL(1)-GL(i)) passing through the dynamic display area DDA will not be disabled. As shown inFIG. 8, because the upper portion of the display panel106includes gate lines (e.g., GL(1)-GL(i)) passing through both the static display area STA and the dynamic display area DDA, the displayed content for the upper portion of the display panel106will be updated by the driver circuit12normally. On the other hand, because the gate lines (e.g., GL(i+1)-GL(M)) in the lower portion of the display panel106pass through the static display area STA only, the displayed content for the lower portion (which is represented as a shadowed region in the figure) of the display panel106will not be updated by the driver circuit12.

In frame time FT806, the display panel106is driven by normal scheme again. The driver circuit12responds to the controller108to update the whole displayed content to frame806.

FIG. 9illustrates another schematic driving scheme of the display panel106. In the example ofFIG. 9, frames902and908are successive frames in the input data Din, and frames904and906are interleaved frames produced based on frames902and908.

In this example, it is assumed that both frames902and908include static image content in their upper portion and include dynamic image content in their lower portion, so the interleaved frames904and906, which are produced based on the frames902and908, are identified as including static image content in their upper portion and having dynamic image content in their lower portion.

In frame time FT902, the display panel106is driven by normal scheme. The driver circuit12enables the gate lines and data lines to update the displayed content on the display panel106to frame902.

In frame time FT904, frames904and906are successively displayed on the display panel106. During the period of time that frame904is displayed, the controller108skips updating data of pixels within the static display area STA, and directly jumps to updating data of pixels within the dynamic display area DDA. After data of pixels within the dynamic display area DDA are updated to the dynamic image content of frame904, the controller108then uses the rest of frame time FT904to display the next frame906. That is, the controller108may use the rest of frame time FT904to update the displayed content in the dynamic display area DDA to the dynamic image content of frame906. In this manner, the frame rate for the frame's dynamic image content can be raised without increasing the operating frequency of the driver circuits. In frame time FT908, the display panel106is driven by normal scheme, to update the displayed content on the display panel106to frame908.

FIG. 10illustrates a schematic timing chart of operations of the display panel106during the frame time FT904shown inFIG. 9.

In the example ofFIG. 10, frame time FT904is divided into sub-frame times FT904A and FT904B, wherein sub-frame time FT904A is the period of time that frame904is displayed, and sub-frame time FT904B is the period of time that frame906is displayed.

Because the update for the displayed content of the static display area STA is skipped according to the driving scheme, the sub-frame time FT904A will begin with the update for the displayed content of the dynamic display area DDA. As shown inFIG. 10, from the beginning of sub-frame time FT904A, the scan signals GS are sequentially applied to the gate lines GL(i+1)-GL(M) passing through the dynamic display area DDA of the display panel106, such that data of pixels within the dynamic display area DDA are updated to the dynamic image content of frame904.

In sub-frame time FT904B, i.e., the rest of frame time FT904, scan signals GS are sequentially applied to the gate lines GL(i+1)-GL(M) within the dynamic display area DDA for the next frame906, such that data of pixels within the dynamic display area DDA can be updated to the dynamic image content of frame906.

Although the number of interleaved frames containing static image content displayed in one frame time is shown by two inFIG. 9, the invention is not limited thereto. The number of interleaved frames displayed in one frame may be arbitrary, depending on different applications. Further, in the present invention, the size, shape, quantity and location of the static display area STA and the dynamic display area DDA can be arbitrary, depending on actual frame content.

Based on the above, the proposed display method can reduce the power consumption of the driver circuit without adversely affecting the display quality. When an interleaved frame is displayed, the controller may control the driver circuit to disable/skip the update for the displayed content of the static display area to save power and reduce operating temperature.