Method of fabricating semiconductor device

A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Taiwan application serial no. 93106283, filed Mar. 10, 2004.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating an integrated circuit. More particularly, the present invention relates to a method of fabricating a semiconductor device capable of preventing the problem of having some photoresist residue retained after photoresist development due to non-complete exposure of a photoresist layer with a high aspect ratio.

2. Description of the Related Art

In the fabrication of an integrated circuit, the source/drain region or gate of a device is electrically connected to another device through a contact and a conductive line. The most common types of contacts include bit line contacts and gate contacts. At present, these two types of contacts are formed separately due to processing limitations. In other words, two independent photolithographic/etching processes are carried out in sequence to form the bit line contacts and the gate contacts respectively.

In a conventional fabrication process, an etching operation is carried out using a photoresist layer having bit line contact opening and gate contact opening patterns. The etching operation removes a portion of the dielectric layer so that a bit line contact opening that exposes a portion of the source/drain region in the substrate and a semi-finished gate contact opening that exposes a portion of the cap layer in a stack gate structure are formed. In general, the cap layer is normally a silicon nitride layer having a thickness of several hundred angstroms. Therefore, if the aforementioned patterned photoresist layer is used as a photomask for etching the cap layer, the exposed substrate within the bit line contact opening is likely to be over-etched and damaged because silicon and silicon nitride have not significantly different etching rates. To prevent over-etching, the aforementioned patterned photoresist layer is used as an etching mask to remove the dielectric layer over the source/drain region and form the bit line contact openings. Thereafter, a second patterned photoresist layer having openings that exposes the cap layers of the stack gate structures only is formed over the substrate. Finally, the cap layers are removed to form the gate contact openings by performing an etching operation using the second patterned photoresist layer as an etching mask.

However, in the first etching operation to form the bit line contact, considerable length of time is still required to expose the source/drain region in the substrate. Therefore, if there is some misalignment in the etching process, the cap layer and the spacers lining the sidewall of the stack gate structure may be damaged causing the gate conductive layer to expose. Eventually, the gate conductive layer will form a short circuit with a subsequently formed bit line contact plug.

On the other hand, because the a semi-finished gate contact opening has already formed on the substrate, some photoresist material will also fill the semi-finished gate contact opening when the second photoresist layer is formed over the substrate. Since the semi-finished gate contact opening has a high aspect ratio, the photoresist material near the bottom section of the semi-finished gate contact opening is difficult to get exposed. Hence, some residual photoresist may be retained on the cap layer to prevent a clean removal of the cap layer in a subsequent etching operation. In the presence of some residue, the contact resistance of the contacts will have significant variations.

SUMMARY OF INVENTION

Accordingly, at least one objective of the present invention is to provide a method of fabricating a semiconductor device capable of preventing the problem of having some photoresist residue retained after photoresist development due to non-complete exposure of a photoresist layer with a high aspect ratio.

At least a second objective of the present invention is to provide a method of fabricating a semiconductor device capable of preventing a gate conductive layer from shorting with a bit line contact plug inside the semiconductor device.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a semiconductor device. First, a substrate is provided. A stack gate structure having a cap layer thereon is formed on the substrate and then a spacer is formed on each side of the stack gate structure. A first dielectric layer having a top surface that exposes the cap layer is formed over the substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate so that the first dielectric layer and the cap layers in a second region of the substrate is exposed. A portion of the cap layers in the second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer and a mask layer are sequentially formed over the substrate. The mask layer has a first opening for defining a bit contact opening and a second opening for defining a gate contact opening. The second dielectric layer within the first opening and the underlying the buffer layer and the first dielectric layer are etched in sequence to form a bit line contact opening. In the meantime, the second dielectric layer within the second opening and the underlying cap layer are etched in sequence to form a gate contact opening.

According to one preferred embodiment of the present invention, the buffer layer and the cap layer are fabricated using an identical material. Furthermore, the buffer layer and the cap layer have an etching rate different from the second dielectric layer and the first dielectric layer. The buffer layer and the cap layer are silicon nitride layers, for example.

Because the buffer layer is fabricated using a material having an etching rate that differs from the second dielectric layer and the first dielectric layer, a three-stage etching process can be carried out to form the first contact opening through an adjustment of the gaseous reactants. The first stage etching operation is carried out using the buffer layer and the cap layer as an etching stop layer. The second stage etching operation is carried out using the first dielectric layer as an etching stop layer. Finally, the third stage etching operation is carried out for a short period of time so that the cap layer and the spacers will not be too seriously damage to expose the gate conductive layer even if there is some misalignment.

The process of forming a buffer layer over the first dielectric layer and the cap layer in the first region of the substrate so that the exposed cap layers in the second region can have a thickness smaller than or equal to the buffer layer includes the following steps. First, a buffer layer is formed over the substrate. Thereafter, a photoresist layer is formed over the buffer layer. The photoresist layer covers the first dielectric layer and surrounding cap layer for forming the first contact openings. Using the photoresist layer as an etching mask, a portion of the buffer layer is removed to expose the cap layers and then the cap layers are etched until the cap layers have a thickness smaller than or equal to the buffer layer.

In process of etching out the contact openings according to the present invention, the cap layer within the second opening in the mask layer has a thickness smaller than or equal to the buffer layer. Thus, the process of removing the buffer layer in an etching operation also removes the cap layers entirely. In other words, there is no need to form an extra photoresist layer just to remove the cap layer and prevents the problems of having residues after photoresist development due to unexposed photoresist at the bottom of a photoresist layer when the aspect ratio is high.

According to one embodiment of the present invention, the process of fabricating the cap layer and the buffer layer can also be so controlled that the buffer layer is thicker than the cap layer. This also ensures the cap layers within the second opening in the mask layer can be completely removed after the etching process.

DETAILED DESCRIPTION

FIGS. 1A through 1Eare schematic cross-sectional views showing the steps for fabricating a semiconductor device according to one preferred embodiment of the present invention. First, as shown inFIG. 1A, a substrate200having a first region202and a second region204is provided. The first region202is an area around a memory cell region for forming bit line contacts and the second region204is an area around a memory cell region for forming gate contacts and an area for forming peripheral circuits, for example. Thereafter, a plurality of stack gate structures206is formed within the first region202and the second region204. The stack gate structures206comprises a gate dielectric layer208next to the substrate, a pair of gate conductive layers210,212in the middle and a cap layer214at the top. The gate dielectric layer208is a silicon oxide layer, the gate conductive layers210,212are polysilicon or metal silicide layers and the cap layer214is a silicon nitride layer, for example. Next, a source/drain region248is formed in the substrate200, for example, by performing an ion implantation process. Afterwards, spacers250are formed on the sidewalls of the stack gate structures206. The spacers250are silicon nitride layers formed, for example, by depositing silicon nitride over the substrate and etching back the silicon nitride layer thereafter.

A dielectric layer216is formed over the substrate200. The top surface of the dielectric layer216exposes the cap layers214of the stack gate structures206. The dielectric layer216is formed, for example, by depositing dielectric material such as borophosphosilicate glass or silicon oxide over the substrate200and then performing a chemical-mechanical polishing using the cap layer214as a polishing stop layer.

A buffer layer218is formed over the substrate200to cover the dielectric layer216and the cap layers214. The buffer layer218is fabricated using a material having an etching rate that differs from the dielectric layer216and a subsequently formed dielectric layer222(shown inFIG. 1C) such as silicon nitride. Thereafter, a mask layer220is formed over the buffer layer218to cover the first region202but exposes the buffer layer218in the second region204. The mask layer220is a photoresist layer, for example. Furthermore, the mask layer220may integrate with the photoresist layer used for opening up alignment marks. In other words, the mask layer220may include an opening pattern within the second region204and an opening pattern (not shown) for opening up alignment marks.

As shown inFIG. 1B, an etching operation is carried out to remove a portion of the buffer layer218in the second region204and a portion of the exposed cap layer214within the second region204. After the etching operation, a buffer layer218aand cap layers214aare formed such that the cap layers214ain the second region204have a thickness smaller than or equal to a buffer layer218ain the first region202. If the cap layers214are specifically made to have a thickness smaller than or equal to the buffer layer218during the fabrication process, there is no need to etch the cap layer214after the buffer layer218in the second region204has been removed. Thereafter, the mask layer220is removed.

As shown inFIG. 1C, another dielectric layer222such as a silicon oxide layer is formed over the substrate200. Thereafter, a mask layer224is formed over the dielectric layer222. The mask layer224is a photoresist layer having openings226,228and230therein, for example. The opening226is formed within the first region202above the source/drain region248in the first region202. The opening228is formed in a memory cell area within the second region204above the cap layer214aof the stack gate structure206, for example. The opening230is formed within the second region204above a source/drain region248of a peripheral memory cell, for example.

Thereafter, an etching operation is carried out inside an etching station to remove the dielectric layer222within the openings226,228and230in the mask layer224. After the etching operation, the opening226exposes the buffer layer218ain the first region202, the opening228exposes the cap layers214ain the second region204and the opening230exposes the dielectric layer216. If the dielectric layer222is a silicon oxide layer, the gaseous reactants used in the etching operation include C4F6, O2and Ar.

As shown inFIG. 1D, using the same etching station, the buffer layer218awithin the opening226is removed to expose a portion of the dielectric layer216and the cap layer214awithin the opening228are removed to form a gate contact opening232. If both the buffer layer218aand the cap layers214aare silicon nitride layers, the gaseous reactants used in the etching operation include CF4, CHF3, O2and Ar. Because the cap layers214ahave a thickness smaller than or equal to the buffer layer218a, complete removal of the cap layers214ais ensured when the buffer layer218ais completely removed.

Thereafter, the etching operation is continued inside the same etching station to remove the dielectric layer216within the openings226,230and form contact openings234,236respectively. The contact opening234is a bit line contact opening that exposes one of the source/drain regions248and the contact opening236is a contact opening that exposes one of the source/drain regions248in a peripheral circuit region, for example. The gaseous reactants used in the etching operation include C4F6, O2and Ar.

As shown inFIG. 1E, the mask layer224is removed. Thereafter, conductive material is deposited into the contact openings232,234,236to form contact plugs238,240,242respectively.

Because the buffer layer is fabricated using a material having an etching rate that differs from its overlying and underlying dielectric layer, the contact openings are formed by performing the etching operation in three separate stages through an adjustment of the composition of gaseous reactants. In the first stage, the second dielectric layer is etched using the buffer layer and the cap layer as an etching stop layer. In the second stage, the buffer layer and the cap layer are etched using the first dielectric layer as an etching stop layer. Finally, in the third stage, the first dielectric layer is etched for a short period of time. Hence, the cap layer and the spacers will not be too seriously damage to expose the gate conductive layer even if there is some misalignment.

In process of etching out the contact openings according to the present invention, the cap layer within the second opening of the mask layer has a thickness smaller than or equal to the buffer layer. Thus, the process of removing the buffer layer in an etching operation also removes the cap layers completely. In other words, there is no need to form an extra photoresist layer just to remove the cap layer and prevents the problems of having residues after photoresist development due to unexposed photoresist at the bottom of a photoresist layer when the aspect ratio is high. Furthermore, the present invention also has a greater processing window than the conventional fabrication process.

According to one embodiment of the present invention, the process of fabricating the cap layer and the buffer layer can also be so controlled that the buffer layer is thicker than the cap layer. This also ensures the cap layers within the second opening in the mask layer can be completely removed after the etching process.