Coding for pulse amplitude modulation with an odd number of output levels

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

FIELD

This disclosure relates to driver circuits for Pulse Amplitude Modulation (PAM), and more particularly, to driver circuits for Pulse Amplitude Modulation (PAM) with an odd number of output levels.

BACKGROUND

Pulse Amplitude Modulation (PAM) is a modulation scheme where the information can be encoded as an amplitude of a series of signal pulses. PAM can be used in different communication schemes. For example, some Ethernet communication standards can use PAM as their modulation scheme. As one example, 100BASE-T4 Ethernet standard uses three-level PAM modulation (PAM-3). As another example, 1000BASE-T Gigabit Ethernet uses five-level PAM-5 modulation. PAM can also be used for communication schemes for local computer bus for attaching hardware devices in a computer. For example, PAM can be used in Peripheral Component Interconnect (PCI) Express (e.g., PCI Express 6.0), which is part of the PCI Local Bus standard.

In PAM signaling schemes, such as PAM-2 modulation (non-return to zero (NRZ)) or PAM-4 modulation with an even number of output levels, there are a symmetric number of output levels. For example, PAM-2 modulation can have output levels ‘−1’ and ‘+1’. PAM-4 modulation can have output levels ‘−1’, ‘−⅓’, ‘+⅓’ and ‘+1’. For PAM signaling schemes with an even number of output levels, the average resistor current in a complementary voltage mode driver circuit can be zero or about zero. Therefore, driver circuit reliability concerns due to electro-migration is relatively low.

However, for PAM signaling schemes with an odd number of output levels (such as PAM-3 modulation, PAM-5 modulation, or the like), there is an output level that is not balanced by a corresponding complementary level. For example, the PAM-3 modulation can have output levels ‘−1’, ‘0’, and ‘+1’. Since the output level ‘0’ does not have an equal and opposite complementary level, the overall average current in the driver circuit (and/or a driver circuit components) is non-zero. Therefore, driver circuit reliability concerns due to electro-migration increase.

SUMMARY

Various embodiments of this disclosure relate to apparatuses and methods for introducing an additional encoding for PAM signaling schemes with an odd number of output levels. For example, various embodiments of a driver circuit are disclosed to introduce an alternative encoding for the ‘0’ output level such that the output level is ‘0’ differentially but is created by swapping two halves of the driver circuit so the average current is about zero, thus improving reliability.

Various embodiments of a driver circuit are disclosed. In some embodiments, the driver circuit includes a first circuit and a second circuit. The first circuit includes a first inverter circuit having a first input terminal, a first output terminal, and a first impedance element electrically coupled to the first output terminal. The first circuit further includes a second inverter circuit having a second input terminal, a second output terminal, and a second impedance element electrically coupled to the second output terminal and electrically coupled to the first impedance element at a first connection point. The second circuit includes a third inverter circuit having a third input terminal, a third output terminal, and a third impedance element electrically coupled to the third output terminal. The second circuit further includes a fourth inverter circuit having a fourth input terminal, a fourth output terminal, and a fourth impedance element electrically coupled to the fourth output terminal and electrically coupled to the third impedance element at a second connection point. A first input signal to the first input terminal, a second input signal to the second input terminal, a third input signal to the third input terminal, and a fourth input signal to the fourth input terminal are selected such that the first connection point has substantially the same voltage as the second connection point for encoding a value using the driver circuit.

In some embodiments, a device includes a first inverter circuit electrically coupled to a first impedance element and a second inverter circuit electrically coupled to a second impedance element, where the second impedance element is electrically coupled to the first impedance element. The device further includes a processor configured to control, based on a first encoding, the first inverter circuit and the second inverter circuit such that a first current flows through the first and second impedance elements, where the first current has a first value and a first direction. The processor is further configured to control, based on a second encoding, the first inverter circuit and the second inverter circuit such that a second current flows through the first and second impedance elements, where the second current has a second value and a second direction. The first value is substantially the same as the second value, and the first direction is opposite to the second direction.

In some embodiments, a method includes determining that a first output level is to be generated by a driver circuit configured to generate an odd number of output levels. The method further includes determining whether a first encoding or a second encoding is to be used for generating the first output level. An average current in the driver circuit generated by the first encoding and the second encoding is substantially zero. The method further includes controlling a plurality of input signals to generate the first output level based at least on the first encoding or the second encoding.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are merely examples and are not intended to be limiting. In addition, the present disclosure repeats reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and, unless indicated otherwise, does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG.1illustrates a system100that includes a PAM driver circuit106, according to some embodiments. As shown inFIG.1, system100can include a transmitter device102and a receiver device110. Transmitter device102can communicate with receiver device110using communication infrastructure112. Although transmitter device102is discussed herein as a transmitter device, the embodiments of this disclosure can include a transceiver device as transmitter device102. Similarly, although receiver device110is discussed herein as a receiver device, the embodiments of this disclosure can include a transceiver device as receiver device102.

According to some embodiments, transmitter device102and receiver device110can belong to different systems that communicate with each other using communication infrastructure112. For example, transmitter device102can be located on a first computer system and receiver device110can be located on a second computer system, where the first and second computer systems communicate with each other using communication infrastructure112(e.g., an Ethernet cable). However, the embodiments of this disclosure are not limited to these examples and other systems can use transmitter device102and receiver device110.

Additionally, or alternatively, transmitter device102and receiver device110can belong to the same system. For example, transmitter device102and receiver device110can be devices and/or circuits on the same computer system and can communicate with each other using communication infrastructure112(e.g., a PCI bus.) In some embodiments, the computer system that includes transmitter device102and receiver device110can be a system-on-chip (SoC). In some embodiments, the computer system that includes transmitter device102and receiver device110can be configured for use in a desktop computer, a server, or a mobile computing system, such as a tablet, a laptop computer, and a wearable computing device.

Communication infrastructure112provides communication between, for example, transmitter device102and receiver device110. According to some embodiments, communication infrastructure112can use PAM as its modulation scheme. In some implementations, communication infrastructure112can use Ethernet communication standards that use PAM as their modulation scheme. As one example, 100BASE-T1 Ethernet standard, 100BASE-T4 Ethernet standard, and 1000BASE-T4 Ethernet standard use three-level PAM modulation (PAM-3). As another example, 10BASE-T Ethernet standard, 100BASE-T2 Ethernet standard, 1000BASE-T Ethernet standard use five-level PAM-5 modulation. PAM can also be used for communication schemes for a local computer bus attaching hardware devices in a computer system. In some implementations, communication infrastructure112can use PCI (e.g., PCI Express, such as PCI Express 6.0), a high speed standard part of the PCI Local Bus standard. In some implementations, communication infrastructure112can be display ports. In some implementations, communication infrastructure112can be a Universal Serial Bus (USB). In some implementations, communication infrastructure112can be used within microcontrollers for communicating control signals. In some implementations, communication infrastructure112can be used in photobiology. However, the embodiments of this disclosure are not limited to these examples, and communication infrastructure112can include other communication infrastructures that can use PAM signaling schemes as a modulation scheme. In some examples, communication infrastructure112can include a printed circuit board (PCB), a FR4 PCB, a wire cable, a coaxial cable, an AC-coupled communication infrastructure or DC-coupled communication infrastructure, an optical communication infrastructure, or the like.

Transmitter device102can include a processor104, a PAM driver circuit106(also referred to herein as “driver circuit106”), a data source108, and a communication infrastructure114. According to some embodiments, data source108can include the data (e.g., the output transmit pattern) that transmitter device102is to send to receiver device110. In some embodiments, data source108can belong to and/or be located at the higher levels (e.g., higher levels in the Open Systems Interconnect (OSI) model) of transmitter device102. Additionally, or alternatively, data source108can include a memory circuit for storing the data (e.g., the output transmit pattern) that transmitter device102is to send to receiver device110. The memory circuit can include any suitable type of memory, such as a dynamic random-access memory (DRAM), a static random-access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), or a non-volatile memory. It is noted that although a single data source108is illustrated inFIG.1, any suitable number of data sources may be employed.

In some embodiments, processor104can be representative of a general-purpose processor that performs computational operations. For example, processor104can be a central processing unit (CPU), such as a microprocessor, a graphics processing unit (GPU), a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). It is noted that although a single processor104is illustrated inFIG.1, any suitable number of processors may be employed.

Communication infrastructure114can provide the communication between processor104, PAM driver circuit106, and data source108. In some examples, communication infrastructure114can include a communication bus. In some examples, communication infrastructure114can include any communication infrastructure such as, but not limited to, a PCB, a FR4 PCB, a wire cable, a coaxial cable, an AC-coupled communication infrastructure or DC-coupled communication infrastructure, an optical communication infrastructure, or the like.

According to some embodiments, PAM driver circuit106is configured to receive the data (e.g., the output transmit pattern) that transmitter device102is to send to receiver device110and modulate the received data to send to receiver device110on communication infrastructure112. PAM driver circuit106can use different PAM signaling schemes such as, but not limited to, PAM-2 modulation, PAM-3 modulation, PAM-4 modulation, PAM-5 modulation, or the like. According to some embodiments, PAM driver circuit106can receive the data from data source108and/or processor104. In some examples, processor104can control the operations of PAM driver circuit106and/or control the data from data source108to PAM driver circuit106. According to some embodiments, PAM driver circuit106is configured to receive the data (e.g., the output transmit pattern) from, for example, data source108and generate output levels based on the received data and/or some control information from processor104. PAM driver circuit106is configured to transmit the generated output levels on communication infrastructure112to receiver device110. According to some embodiments, the output levels are the signal amplitudes of the output signals of PAM driver circuit106.

It is noted that although a single PAM driver circuit106is illustrated inFIG.1, any suitable number of driver circuits may be employed. Also, although processor104, PAM driver circuit106, and data source108are illustrated as separate devices/circuits inFIG.1, the embodiments of this disclosure can include any combination of processor104, PAM driver circuit106, and data source108.

Some examples are discussed herein with respect to PAM-3 modulation. However, the embodiments of this disclosure can be applied to any suitable PAM signaling schemes with, for example, an odd number of output levels. As discussed above, the PAM-3 modulation can have output levels ‘−1’, ‘0’, and ‘+1’. In a non-limiting example where PAM driver circuit106uses PAM-3 modulation, PAM driver circuit106and/or processor104can use two threshold levels for determining the output levels from the data received at PAM driver circuit106and/or at processor104. For example, PAM driver circuit106and/or processor104use a first threshold level and a second threshold level, where the second threshold level is smaller than the first threshold level.

PAM driver circuit106and/or processor104can compare the data (e.g., the output transmit pattern) from, for example, data source108with the threshold levels. If the data is greater than the first threshold level, PAM driver circuit106can generate ‘+1’ output level. If the data is smaller than that second threshold lever, PAM driver circuit106can generate ‘−1’ output level. If the data is between the first and second threshold levels, PAM driver circuit106can generate ‘0’ output level. In some examples, the threshold levels can be a ternary signal or a ternary symbol.

In a non-limiting example in 100Base-T1, two ternary symbols can be combined to form a code group. When code group represents data, it represents three bits of data:

As illustrated in Table 1, data can be the data input to PAM driver circuit106and T1 and T2 are the output levels (e.g., symbols) that are the output of PAM driver circuit106.

As noted above, the embodiments of this disclosure are not limited to these examples and can include any suitable PAM signaling schemes with, for example, an odd number of output levels.

As discussed in more detail below, various embodiments of this disclosure relate to circuits and methods for introducing an additional encoding for the PAM signaling schemes with an odd number of output levels. For example, various embodiments of PAM driver circuit106are disclosed to introduce an alternative encoding for, for example, the ‘0’ output level such that the output level is ‘0’ differential but is created by swapping the two halves of the driver circuit such that the current can be averaged to be zero (or about zero) and better reliability can be achieved.

According to some embodiments, PAM driver circuit106can be a voltage mode driver circuit. However, the embodiments of this disclosure can also be applied to other driver types such as current mode logic circuit and benefits can be achieved by spreading the average current across different components of the driver circuit.

According to some embodiments, processor104can be configured to enable or disable the ‘+0’ and ‘−0’ encodings. In some examples, transmitter device102can be configured to enable or disable the ‘+0’ and ‘−0’ encodings by sending a request to processor104. Additionally, or alternatively, processor104can be configured to enable or disable the ‘+0’ and ‘−0’ encodings based on one or more parameters such as, but not limited to, operating conditions of transmitter device102, processor104, and/or PAM driver circuit106.

FIG.2illustrates an implementation of PAM driver circuit106, according to some embodiments. As illustrated inFIG.2, PAM driver circuit106can include inverter circuits201a,201b,203a,203a, impedance elements205a,205b,207a,207b, and load209. PAM driver circuit106can include two halves. The first half of PAM driver circuit106can include inverter circuits201aand201band impedance elements205aand205b. The second half of PAM driver circuit106can include inverter circuits203aand203band impedance elements207aand207b.

Some embodiments of this disclosure are discussed with respect to resistors as examples of impedance elements205a,205b,207a,207b(e.g., resistors205a,205b,207a,207b.) However, the embodiments of this disclosure are not limited to resistors, and impedance elements205a,205b,207a,207bcan include other elements such as, but not limited to, inductors, coils, T-coils, or the like. In some implementations, PAM driver circuit106can include a differential resistance, in addition to impedance elements205a,205b,207a,207b.

As illustrated inFIG.2, inverter circuit201ais electrically coupled to resistor205aand can be controlled using input signal221a. Resistor205ais also electrically coupled to resistor205b. Resistor205bis further electrically coupled to inverter circuit201b. Inverter circuit201bcan be controlled using input signal221b.

Similarly, as illustrated inFIG.2, inverter circuit203ais electrically coupled to resistor207aand can be controlled using input signal223a. Resistor207ais also electrically coupled to resistor207b. Resistor207bis further electrically coupled to inverter circuit203b. Inverter circuit203bcan be controlled using input signal223b.

Load209is electrically coupled between output ports211and213. In some implementations, load209can be a resistor. However, the embodiments of this disclosure are not limited to this example, and load209can include other loads. In some examples, load209can be a differential load. In some examples, load209can be single-ended electrically coupled to a supply or reference voltage. Output port211is a connection point, where resistor205ais electrically coupled to resistor205b. Output port213is a connection point, where resistor207ais electrically coupled to resistor207b. According to some embodiments, the output levels generated by PAM driver circuit106are the signal amplitudes of the output signals of PAM driver circuit106, for example, the voltage levels at load209. In other words, the output levels generated by PAM driver circuit106are the voltage differences between the voltage levels at output port211and the voltage levels at output port213.

According to some embodiments, input signals221a,221b,223a,223bare used to control PAM driver circuit106to generate the output levels based on the data (e.g., the output transmit pattern) from, for example, data source108ofFIG.1. The data can be randomized data by coding, by scrambling, or any other suitable method. In some implementations, processor104can receive the data from data source108and use the data to generate input signals221a,221b,223a,223bbased on the data. Processor104can send input signals221a,221b,223a,223bto PAM driver circuit106to generate the output levels based on the data. Additionally, or alternatively, PAM driver circuit106can receive the data from data source108and generate input signals221a,221b,223a,223bbased on the data. PAM driver circuit106can use input signals221a,221b,223a,223bto generate the output levels.

According to some embodiments, PAM driver circuit106is configured to generate a ‘+1’ output level, a ‘−1’ output level, and two ‘0’ output levels. The two ‘0’ output levels are described herein as a ‘+0’ output level and a ‘−0’ output level. By generating alternative ‘0’ output levels, PAM driver circuit106is configured to generate the output level that is ‘0’ differential but is created by swapping the two halves of PAM driver circuit106such that current can be averaged to be zero or about zero. Therefore, better reliability can be achieved and electro-migration can be reduced.

As discussed in more detail with respect toFIG.4A, for a first encoding of PAM driver circuit106(e.g., ‘+0’ encoding) to generate the ‘+0’ output level, input signals221a,221b,223a,223bcan be controlled such that a first current can flow through resistors205aand205b. The first current has a first value and a first direction. According to some embodiments, input signals221a,221b,223a,223bcan be controlled/generated by processor104and/or PAM driver circuit106based on the data from data source108to generate the first current.

As discussed in more detail with respect toFIG.4B, for a second encoding of PAM driver circuit106(e.g., ‘−0’ encoding) to generate the ‘−0’ output level, input signals221a,221b,223a,223bcan be controlled such that a second current can flow through resistors205aand205b. The second current has a second value and a second direction. According to some embodiments, input signals221a,221b,223a,223bcan be controlled/generated by processor104and/or PAM driver circuit106based on the data from data source108to generate the second current. According to some embodiments, the first current and the second current have substantially the same value but different directions. In other words, the first value is substantially the same as the second value and the first direction is opposite to the second direction.

The above examples are discussed with respect to the first half of PAM driver circuit106, which includes inverter circuits201aand201band resistors205aand205b. The second half of PAM driver circuit106, which includes inverter circuits203aand203band resistors207aand207b, can be controlled similarly.

As discussed in more detail with respect toFIG.4A, for the first encoding of PAM driver circuit106(e.g., ‘+0’ encoding) to generate the ‘+0’ output level, input signals221a,221b,223a,223bcan be controlled such that a third current can flow through resistors207aand207b. The third current has a third value and a third direction. According to some embodiments, input signals221a,221b,223a,223bcan be controlled/generated by processor104and/or PAM driver circuit106based on the data from data source108to generate the third current.

As discussed in more detail with respect toFIG.4B, for the second encoding of PAM driver circuit106(e.g., ‘−0’ encoding) to generate the ‘−0’ output level, input signals221a,221b,223a,223bcan be controlled such that a fourth current can flow through resistors207aand207b. The fourth current has a fourth value and a fourth direction. According to some embodiments, input signals221a,221b,223a,223bcan be controlled/generated by processor104and/or PAM driver circuit106based on the data from data source108to generate the fourth current. According to some embodiments, the third current and the fourth current have substantially the same value but different directions. In other words, the third value is substantially the same as the fourth value and the third direction is opposite to the fourth direction.

For the first encoding of PAM driver circuit106(e.g., ‘+0’ encoding), the first current (the current through resistors205aand205b) generates a first voltage at output port211. Similarly, the third current (the current through resistors207aand207b) generates a third voltage at output port213. In this first encoding of PAM driver circuit106(e.g., ‘+0’ encoding), the first voltage at output port211is substantially the same as the third voltage at output port213. Therefore, the voltage difference between output ports211and213is about 0 volts and the output level generated by PAM driver circuit106is ‘+0’ output level.

For the second encoding of PAM driver circuit106(e.g., ‘−0’ encoding), the second current (the current through resistors205aand205b) generates a second voltage at output port211. Similarly, the fourth current (the current through resistors207aand207b) generates a fourth voltage at output port213. In this second encoding of PAM driver circuit106(e.g., ‘−0’ encoding), the second voltage at output port211is the substantially the same as the fourth voltage at output port213. Therefore, the voltage difference between output ports211and213is about 0 volts and the output level generated by PAM driver circuit106is ‘−0’ output level.

According to some embodiments, by changing the direction of the currents flowing through resistors205a,205b,207a,207bfor the ‘0’ output level, electro migration issues can be minimized at resistors205a,205b,207a,207b. Additionally, the electro migration issues can be minimized at the interconnection between resistor205aand inverter circuit201a, at the interconnection between resistor205band inverter circuit201b, at the interconnection between resistor207aand inverter circuit203a, and at the interconnection between resistor207band inverter circuit203b.

In non-limiting examples, resistors205a,205b,207a,207bcan have a resistance of about 50 ohms to about 150 ohms. In non-limiting examples, resistors205a,205b,207a,207bcan have a resistance of about 75 ohms to about 125 ohms. In non-limiting examples, resistors205a,205b,207a,207bcan have a resistance of about 90 ohms to about 110 ohms. In non-limiting examples, resistors205a,205b,207a,207bcan have a resistance of about 100 ohms. In non-limiting examples, resistors205a,205b,207a,207bcan have the same or substantially the same resistance. In non-limiting examples, resistors205a,205b,207a,207bcan have different resistances. However, the embodiments of this disclosure are not limited to these examples and resistors205a,205b,207a,207bcan have other values.

AlthoughFIG.2and PAM driver circuit106are discussed above with respect to PAM-3 modulation, similar circuits and controls can be used for other PAM signaling schemes. For example, similar circuits and controls can be used for PAM signaling schemes with an odd number of output levels, where the ‘0’ output level can be generated using two different encodings (e.g., ‘+0’ encoding and ‘−0’ encoding) as discussed above.

FIG.3illustrates a more detailed illustration of PAM driver circuit106, according to some embodiments. Similar or the same elements inFIG.3as the elements inFIGS.1and2are illustrated with the same numerals and are not discussed in more detail with respect toFIG.3for brevity.

FIG.3illustrates one exemplary implementation of inverter circuits201a,201b,203a,203bofFIG.2. For example, inverter circuit201aofFIG.2can include devices331aand333a. Inverter circuit201bofFIG.2can include devices331band333b. Inverter circuit203aofFIG.2can include devices351aand353a. Inverter circuit203bofFIG.2can include devices351band353b. Although some exemplary devices of inverter circuits201a,201b,203a,203bare provided, the embodiments of this disclosure are not limited to these devices, and inverter circuits201a,201b,203a,203bcan include other components. For example, inverter circuits201a,201b,203a,203bcan additionally include resistors, inductors, coils, T-coils, and the like.

In some embodiments, a MOS transistor can have three terminals denoted as “source,” “gate,” and “drain.” In response to an application of a voltage to the gate terminal, the MOS transistor alters the conductivity between the drain and source terminals, thereby changing the flow of current between the two terminals. The voltage applied to the gate terminal needs to exceed a particular value (referred to as a “threshold voltage”) to allow current to flow between the drain and source terminals. The current between the drain and source terminals generally increases in response to an increase in the voltage level applied to the gate. Depending on a type of majority carrier (e.g., n-type or p-type) that conducts current between the source and drain terminals, the polarity of voltage level applied to the gate terminal may be different relative to the threshold voltage.

In some embodiments, devices333a,333b,353a,353bcan be implemented as n-type MOS transistors, such as n-type MOSFETs, FinFETs, GAAFETs, and any other suitable devices. In some embodiments, devices331a,331b,351a,351bcan be implemented as p-type MOS transistors, such as p-type MOSFETs, FinFETs, GAAFETs, and any other suitable devices.

In some embodiments, device331acan have a first terminal that is electrically coupled to a voltage power supply also referred to as “VDD.” Device331acan have a second terminal that is electrically coupled to a first terminal of resistor205a. Device331acan have a third terminal configured to receive input221a. Similarly, device333acan have a first terminal electrically coupled to the second terminal of device331aand the first terminal of resistor205a. Device333acan have second terminal that is coupled to a ground level (e.g., 0 V), also referred to as “VSS.” Device333acan have a third terminal that is electrically coupled to the third terminal of device331aand can receive input221a.

In some examples, VDD can be about 0.5 V to about 1.5 V. For example, VDD can be about 0.75 V to about 1.25 V. For example, VDD can be about 0.95 V to about 1.05 V. For example, VDD can be about 1 V.

In some embodiments, device331bcan have a first terminal that is electrically coupled to the voltage power supply. Device331bcan have a second terminal that is electrically coupled to a first terminal of resistor205b. Device331bcan have a third terminal configured to receive input221b. Similarly, device333bcan have a first terminal electrically coupled to the second terminal of device331band the first terminal of resistor205b. Device333bcan have a second terminal that is coupled to the ground level (e.g., 0 V). Device333bcan have a third terminal that is electrically coupled to the third terminal of device331band can receive input221b. A second terminal of resistor205ais electrically coupled to a second terminal of resistor205b. Output port211is electrically coupled to second terminal of resistor205aand second terminal of resistor205b.

In some embodiments, device351acan have a first terminal that is electrically coupled to the voltage power supply. Device351acan have a second terminal that is electrically coupled to a first terminal of resistor207a. Device351acan have a third terminal configured to receive input224a. Similarly, device353acan have a first terminal electrically coupled to the second terminal of device351aand the first terminal of resistor207a. Device353acan have a second terminal that is coupled to the ground level. Device353acan have a third terminal that is electrically coupled to the third terminal of device351aand can receive input223a.

In some embodiments, device351bcan have a first terminal that is electrically coupled to the voltage power supply. Device351bcan have a second terminal that is electrically coupled to a first terminal of resistor207b. Device351bcan have a third terminal configured to receive input223b. Similarly, device353bcan have a first terminal electrically coupled to the second terminal of device351band the first terminal of resistor207b. Device353bcan have a second terminal that is coupled to the ground level (e.g., 0 V). Device353bcan have a third terminal that is electrically coupled to the third terminal of device351band can receive input223b. A second terminal of resistor207ais electrically coupled to a second terminal of resistor207b. Output port213is electrically coupled to the second terminal of resistor207aand second terminal of resistor207b.

AlthoughFIG.3and PAM driver circuit106are discussed above with respect to PAM-3 modulation, similar circuits and controls can be used for other PAM signaling schemes. For example, similar circuits and controls can be used for PAM signaling schemes with an odd number of output levels, where the ‘0’ output level can be generated using two different encodings (e.g., ‘+0’ encoding and ‘−0’ encoding) as discussed above.

FIG.4Aillustrates the PAM driver circuit operating for the ‘+0’ encoding, according to some embodiments.FIG.4Aillustrates a more detailed operation of PAM driver circuit106for the ‘+0’ encoding, according to some embodiments. Similar or the same elements inFIG.4Aas the elements inFIGS.1-3are illustrated with the same numerals and are not discussed in more detail with respect toFIG.4Afor brevity.

According to some embodiments, input signals221a,221b,223a,223bare generated to control PAM driver circuit106to generate ‘+0’ output level. As discussed above, input signals221a,221b,223a,223bare generated by processor104and/or PAM driver circuit106based on the data from data source108. For example, the data from data source108is to be modulated to ‘0’ output level. Based on the data, processor104and/or PAM driver circuit106generate input signals221a,221b,223a,223bto generate ‘+0’ output level.

In a non-limiting example, input signal221acan have a first value (e.g., ‘0’), input signal221bcan have a second value (e.g., ‘1’), input signal223acan have the first value (e.g., ‘0’), and input signal223bcan have the second value (e.g., ‘1’). According to some implementations, input control221aand221bcan be generated from the same input but one is inverted compared to the other. According to some implementations, input control223aand223bcan be generated from the same input but one is inverted compared to the other.

Given these values of input signals221a,221b,223a,223b, devices333a,331b,353a,351bofFIG.3are off. Given these values of input signals221a,221b,223a,223b, devices331a,333b,351a,353bofFIG.3andFIG.4Aare on.

According to some embodiments, the sum of the resistance of device331aand the resistance of resistor205ais equal to the sum of the resistance of device333band the resistance of resistor205b. Therefore, the voltage at output port211is about VDD/2. Similarly, the sum of the resistance of device351aand the resistance of resistor207ais equal to the sum of the resistance of device353band the resistance of resistor207b. Therefore, the voltage at output port213is about VDD/2. Therefore, the voltage difference at the output of PAM driver circuit is about 0 V and the ‘+0’ output level is generated.

In these embodiments, current401flows through resistors205aand205bfrom VDD to the ground level. The value of current401can be about

I1=V⁢D⁢DR⁢1⁢a+R⁢1⁢b,
where R1a is me resistance of resistor205aand R1b is the resistance of resistor205b. In this example, the resistances of devices331aand333bare ignored.

Similarly, current403flows through resistors207aand207bfrom VDD to the ground level. The value of current403can be about where

I2=V⁢D⁢DR⁢2⁢a+R⁢2⁢b,
where R2a is the resistance of resistor207band R2b is the resistance of resistor207a. In this example, the resistances of devices351aand353bare ignored.

FIG.4Billustrates the PAM driver circuit operating for the ‘−0’ encoding, according to some embodiments.FIG.4Billustrates a more detailed operation of PAM driver circuit106for the ‘−0’ encoding, according to some embodiments. Similar or the same elements inFIG.4Bas the elements inFIGS.1-3are illustrated with the same numerals and are not discussed in more detail with respect toFIG.4Bfor brevity.

According to some embodiments, input signals221a,221b,223a,223bare generated to control PAM driver circuit106to generate ‘−0’ output level. As discussed above, input signals221a,221b,223a,223bare generated by processor104and/or PAM driver circuit106based on the data from data source108. For example, the data from data source108is to be modulated to ‘0’ output level. Based on the data, processor104and/or PAM driver circuit106generate input signals221a,221b,223a,223bto generate ‘−0’ output level.

In a non-limiting example, input signal221acan have the second value (e.g., ‘1’), input signal221bcan have the first value (e.g., ‘0’), input signal223acan have the second value (e.g., ‘1’), and input signal223bcan have the first value (e.g., ‘0’). According to some implementations, input control221aand221bcan be generated from the same input but one is inverted compared to the other. According to some implementations, input control223aand223bcan be generated from the same input but one is inverted compared to the other. In these examples, input signals221a,221b,223a,223bhave the opposite values compared to their corresponding values for ‘+0’ encoding ofFIG.4A.

Given these values of input signals221a,221b,223a,223b, devices331a,333b,351a,353bofFIG.3are off. Given these values of input signals221a,221b,223a,223b, devices333a,331b,353a,351bofFIG.3andFIG.4Bare on.

According to some embodiments, the sum of the resistance of device333aand the resistance of resistor205ais equal to the sum of the resistance of device331band the resistance of resistor205b. Therefore, the voltage at output port211is about VDD/2. Similarly, the sum of the resistance of device353aand the resistance of resistor207ais equal to the sum of the resistance of device351band the resistance of resistor207b. Therefore, the voltage at output port213is about VDD/2. Therefore, the voltage difference at the output of PAM driver circuit is about 0 V and the ‘+0’ output level is generated.

In these embodiments, current411flows through resistors205band205afrom VDD to the ground level. The value of current411can be about

I3=V⁢D⁢DR⁢1⁢a+R⁢1⁢b,
where R1a is the resistance of resistor205aand R1b is the resistance of resistor205b. In this example, the resistances of devices331band333aare ignored.

Similarly, current413flows through resistors207band207afrom VDD to the ground level. The value of current413can be about

I4=V⁢D⁢DR⁢2⁢a+R⁢2⁢b,
where R2a is the resistance of resistor207band R2b is the resistance of resistor207a. In this example, the resistances of devices351band353aare ignored.

As illustrated inFIGS.4A and4B, the direction of current411ofFIG.4Bis the opposite of the direction of current401ofFIG.4A. But both currents401and411have the same or substantially the same value. Therefore, although both circuits ofFIGS.4A and4Bgenerate ‘0’ output levels (e.g.,FIG.4Agenerates ‘+0’ output level andFIG.4Bgenerates ‘−0’ output level), but the direction of the currents in resistors205aand205bis opposite to one another. Accordingly, by controlling input signals221a,221b,223a,223b, PAM driver circuit106can generate the same ‘0’ output level but reverse the currents in resistors205aand205band therefore reduce the effects of electro-migration at these resistors.

Similarly, as illustrated inFIGS.4A and4B, the direction of current413ofFIG.4Bis the opposite of the direction of current403ofFIG.4A. But both currents403and413have the same or substantially the same value. Therefore, although both circuits ofFIGS.4A and4Bgenerate ‘0’ output levels (e.g.,FIG.4Agenerates ‘+0’ output level andFIG.4Bgenerates ‘−0’ output level), but the direction of the currents in resistors207aand207bis opposite to one another. Accordingly, by controlling input signals221a,221b,223a,223b, PAM driver circuit106can generate the same ‘0’ output level but reverse the currents in resistors207aand207band therefore reduce the effects of electro-migration at these resistors.

FIG.4Cillustrates the PAM driver circuit operating for the ‘+1’ encoding, according to some embodiments.FIG.4Cillustrates a more detailed operation of PAM driver circuit106for the ‘+1’ encoding, according to some embodiments. Similar or the same elements inFIG.4Cas the elements inFIGS.1-3are illustrated with the same numerals and are not discussed in more detail with respect toFIG.4Cfor brevity.

According to some embodiments, input signals221a,221b,223a,223bare generated to control PAM driver circuit106to generate ‘+1’ output level. As discussed above, input signals221a,221b,223a,223bare generated by processor104and/or PAM driver circuit106based on the data from data source108. For example, the data from data source108is to be modulated to ‘+1’ output level. Based on the data, processor104and/or PAM driver circuit106generate input signals221a,221b,223a,223bto generate ‘+1’ output level.

In a non-limiting example, input signal221acan have the first value (e.g., ‘0’), input signal221bcan have the first value (e.g., ‘0’), input signal223acan have the second value (e.g., ‘1’), and input signal223bcan have the second value (e.g., ‘1’). According to some implementations, input control221aand221bcan be generated from the same input. According to some implementations, input control223aand223bcan be generated from the same input.

Given these values of input signals221a,221b,223a,223b, devices333a,333b,351a,351bofFIG.3are off. Given these values of input signals221a,221b,223a,223b, devices331a,331b,353a,353bofFIG.3andFIG.4Care on.

In these embodiments, current421flows through resistors205a,205b, through load209, and through resistors207a,207bfrom VDD to the ground level. The value of current421can be about

I5=V⁢D⁢D(11R⁢1⁢a+1R⁢1⁢b)+(11R⁢2⁢a+1R⁢2⁢b)+R⁢L,
where R1a is the resistance of resistor205a, R1b is the resistance of resistor205b, R2a is the resistance of resistor207b, and R2b is the resistance of resistor207a. In this example, the resistances of devices331a,331b,353a,353aare ignored. Current421at load209generates the ‘+1’ output level as, for example, the positive voltage difference between the voltage at output port211minus the voltage at output port213.

FIG.4Dillustrates the PAM driver circuit operating for the ‘−1’ encoding, according to some embodiments.FIG.4Dillustrates a more detailed operation of PAM driver circuit106for the ‘−1’ encoding, according to some embodiments. Similar or the same elements inFIG.4Das the elements inFIGS.1-3are illustrated with the same numerals and are not discussed in more detail with respect toFIG.4Dfor brevity.

According to some embodiments, input signals221a,221b,223a,223bare generated to control PAM driver circuit106to generate ‘−1’ output level. As discussed above, input signals221a,221b,223a,223bare generated by processor104and/or PAM driver circuit106based on the data from data source108. For example, the data from data source108is to be modulated to ‘−1’ output level. Based on the data, processor104and/or PAM driver circuit106generate input signals221a,221b,223a,223bto generate ‘−1’ output level.

In a non-limiting example, input signal221acan have the second value (e.g., ‘1’), input signal221bcan have the second value (e.g., ‘1’), input signal223acan have the first value (e.g., ‘0’), and input signal223bcan have the first value (e.g., ‘0’). According to some implementations, input control221aand221bcan be generated from the same input. According to some implementations, input control223aand223bcan be generated from the same input.

Given these values of input signals221a,221b,223a,223b, devices331a,331b,353a,353bofFIG.3are off. Given these values of input signals221a,221b,223a,223b, devices333a,333b,351a,351bofFIG.3andFIG.4Care on.

In these embodiments, current431flows through resistors207a,207b, through load209, and through resistors205a,205bfrom VDD to the ground level. The value of current431can be about

I6=V⁢D⁢D(11R⁢1⁢a+1R⁢1⁢b)+(11R⁢2⁢a+1R⁢2⁢b)+R⁢L,
where R1a is the resistance of resistor205a, R1b is the resistance of resistor205b, R2a is the resistance of resistor207b, and R2b is the resistance of resistor207a. In this example, the resistances of devices331a,331b,353a,353aare ignored. Current431at load209generates the ‘−1’ output level as, for example, the negative voltage difference between the voltage at output port211minus the voltage at output port213.

As illustrated inFIGS.4C and4D, the direction of current431ofFIG.4Dis the opposite of the direction of current421ofFIG.4C. But both currents421and431have the same or substantially the same value. Therefore, the ‘+1’ output level and the ‘−1’ output level generate currents with the same (or substantially the same value) but with opposite directions. By reversing the direction of the currents in resistors205a,205b,207a,207b, the effects of electro-migration at these resistors is reduced when ‘+1’ output level and ‘−1’ output level are used.

AlthoughFIGS.4A-4Dand PAM driver circuit106are discussed above with respect to PAM-3 modulation, similar circuits and controls can be used for other PAM signaling schemes. For example, similar circuits and controls can be used for PAM signaling schemes with an odd number of output levels, where the ‘0’ output level can be generated using two different encodings (e.g., ‘+0’ encoding and ‘−0’ encoding) as discussed above.

FIG.5illustrates a method500for operating a PAM driver circuit, according to some embodiments. For illustrative purposes, the operations illustrated in method500will be described with reference to the example PAM driver circuit106inFIGS.1-3and4A-4D. Additional operations may be performed between various operations of method500and may be omitted merely for clarity and ease of description. Additional operations can be provided before, during, and/or after method500; one or more of these additional operations are briefly described herein. Moreover, not all operations may be needed to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously or in a different order than shown inFIG.5. In some embodiments, one or more other operations may be performed in addition to or in place of the presently described operations.

At510, it is determined that a ‘0’ output level is to be generated by a driver circuit. For example, processor104and/or PAM driver circuit106determines that PAM driver circuit106is to generate a ‘0’ output level. According to some embodiments, processor104and/or PAM driver circuit106determines that PAM driver circuit106is to generate the ‘0’ output level based on data received from a data source (e.g., data source108ofFIG.1). Data source108can belong to and/or be located at the higher levels (e.g., higher levels in the OSI model) compared to the PAM driver circuit. According to some embodiments, processor104and/or PAM driver circuit106determines that PAM driver circuit106can use at least the received data to determine that the ‘0’ output level is to be generated.

At520, it is determined whether a first encoding or a second encoding is to be used for generating the ‘0’ output level. For example, processor104and/or PAM driver circuit106determines the first encoding (e.g., ‘+0’ encoding) or the second encoding (e.g., ‘−0’ encoding) is to be used for generating the ‘0’ output level.

According to some embodiments, processor104and/or PAM driver circuit106are configured to use different algorithms to determine when and how to change the encodings (e.g., the first encoding to the second encoding and vice versa) for the ‘0’ output level. In some implementations, processor104and/or PAM driver circuit106are configured to change the encodings for the ‘0’ output level such that an average number of ‘+0’ encodings is equal to (or is substantially equal to) ‘−0’ encodings. Additionally, or alternatively, processor104and/or PAM driver circuit106are configured to change the encodings for the ‘0’ output level to minimize encoding changes such that consecutive ‘0’ output levels can keep the same encoding. For example, a long string of ‘0’ output levels does not result in multiple ‘+0’ encoding and ‘−0’ encoding changes, which may waste power and create noise.

According to some embodiments, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include changing the encoding to ‘+0’ encoding every time a ‘+1’ output level is encountered and to ‘−0’ encoding when a ‘−1’ output level is encountered. For example, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include determining whether a previous output level included a ‘+1’ output level or a ‘−1’ output level. In these examples, in response to determining that the previous output level included the ‘+1’ output level, processor104and/or PAM driver circuit106can determine that the first encoding (e.g., the ‘+0’ encoding) is to be used for generating the ‘0’ output level. In response to determining that the previous output level included the ‘−1’ output level, processor104and/or PAM driver circuit106can determine that the second encoding (e.g., the ‘−0’ encoding) is to be used for generating the ‘0’ output level.

According to some embodiments, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include alternating between ‘+0’ encoding and ‘−0’ encoding every time there is a power state transition. According to some implementations, the power state transition can include transitions between different power states of, for example, processor104, PAM driver circuit106, data source108, and/or transmitter device102ofFIG.1. For example, the power state transition can include transition from active state to sleep state or vice versa. However, the embodiments of this disclosure can include other power state transitions. In some implementations, the determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include determining whether a previous ‘0’ output level was generated using the first encoding (e.g., ‘+0’ encoding), determining that a power state transition has occurred, and in response to determining that the power state transition has occurred, determining that the second encoding (e.g., ‘−0’ encoding) is to be used for generating the ‘0’ output level.

According to some embodiments, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include time or number of symbols/words alternating between the ‘+0’ encoding and the ‘−0’ encoding periodically. For example, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include periodically switching between the first encoding (e.g., ‘+0’ encoding) and the second encoding (e.g., ‘−0’ encoding). The periodicity of the switching can depend at least on one of a time period or a number of symbols/words. For example, for every T seconds (e.g., a predetermined period), the encoding for ‘0’ output level can change between the first and second encodings. According to some embodiments, the number of symbols/words include the number of symbols/words in the data provided by data source108that is used by PAM driver circuit106to generate the output signals sent to receiver device110. For example, for a first N symbols/words, the first encoding is used. For the second N symbols/words, the second encoding is used. For the third N symbols/words, the first encoding is used; and so on. In some non-limiting examples, N can be 10, 20, 40, 80, 160, or the like, or N can be a binary number like16,32,64,128,256, or the like. However, the embodiments of this disclosure are not limited to these examples.

According to some embodiments, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level can include examining a first symbol in a multi-symbol word. In these example, if that symbol generates the ‘+1’ output level (e.g., (1,1)), then processor104and/or PAM circuit driver106use the ‘+0’ encoding (e.g., (1,0) symbol encoding) for the entire word. However, if that symbol generates the ‘−1’ output level (e.g., (0,0)), then processor104and/or PAM circuit driver106use the ‘−0’ encoding (e.g., (0,1) symbol encoding). If that symbol generates the ‘0’ output level, then processor104and/or PAM circuit driver106keep the previous encoding. For example, determining whether the first encoding or the second encoding is to be used for generating the ‘0’ output level includes examining a first symbol in a multi-symbol word input to the driver circuit. The multi-symbol word can include the multi-symbol word in the data provided by data source108that is used by PAM driver circuit106to generate the output signals sent to receiver device110. In response to the first symbol generating the ‘+1’ output level, method500can include determining to use the first encoding (e.g., ‘+0’ encoding). In response to the first symbol generating the ‘−1’ output level, method500can include determining to use the second encoding (e.g., ‘−0’ encoding). In response to the first symbol generating the ‘0’ output level, method500can further include determining to use a previous encoding associated with a previous ‘0’ output level associated with a previous multi-symbol word.

At530, a plurality of input signals are controlled to generate the ‘0’ output level based at least on the first encoding or the second encoding. For example, processor104and/or PAM driver circuit106can generate and/or determine input signals to control PAM driver circuit106to generate the ‘0’ output level based on the encoding determined at520. As discussed above in detail with respect toFIGS.1-3and4A-4D, processor104and/or PAM driver circuit106can generate and/or determine the input signals to one or more inverter circuits to control PAM driver circuit106to generate the ‘0’ output level based on the encoding determined at520.

According to some embodiments, for PAM signaling with an odd number of output levels, swapping the encoding (e.g., between the ‘+0’ encoding and the ‘−0’ encoding) can be logically equivalent to transposing or swapping the most significant bit (MSB) and the least significant bit (LSB) bits in a symbol or can be logically equivalent to swapping the entire MSB and LSB words in a multi-symbol word. However, the swapping the encoding may be implemented with any form of combinational logic that produces the correct results.

FIG.6illustrates exemplary systems of devices that include embodiments of the PAM driver circuits as described herein. System or device600, which can incorporate or otherwise utilize one or more of the techniques described herein, can be utilized in a wide range of areas. For example, system or device600can be utilized as part of the hardware of systems such as a desktop computer610, a laptop computer620, a tablet computer630, a cellular or mobile phone640, or a television650(or a set-top box coupled to a television).

Similarly, the disclosed embodiments can be utilized in a wearable device660, such as a smartwatch or a health-monitoring device. Smartwatches can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed solely to perform health-monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to an emergency medical service, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or a helmet designed to provide computer-generated reality experiences such as those based on augmented and/or virtual reality, etc.

System or device600can also be used in various other contexts. For example, system or device600can be utilized in the context of a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service670. Still further, system or device600can be implemented in a wide range of specialized devices, such as home electronic devices680that includes refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Elements can also be implemented in various modes of transportation. For example, system or device600can be employed in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles690.

The applications illustrated inFIG.6are merely exemplary and are not intended to limit the potential future applications of disclosed systems or devices. Other example applications include, without limitation, portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.