Supporting pseudo open drain input/output standards in a programmable logic device

Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

TECHNICAL FIELD

This disclosure generally relates to integrated circuits. More specifically, the disclosure relates to systems and methods for supporting a pseudo open drain (POD) input/output (I/O) standard.

DESCRIPTION OF THE RELATED TECHNOLOGY

A programmable logic device (PLD) is a semiconductor integrated circuit which contains logic circuitry and routing that may be configured to perform a host of logic functions. In a typical scenario, a designer uses electronic design automation (EDA) tools to create a design. These tools use information regarding the hardware capabilities of a given programmable logic device to help the designer implement the custom logic circuit using multiple resources available on that given programmable logic device.

In some scenarios, a PLD may interface with another device, or different logic instantiated or designed in a PLD may interface with each other. For instance, a PLD may interface with another PLD or a fixed logic device such as an application specific integrated circuit (ASIC), structured ASIC, processor, memory, or other devices and/or peripherals. Often, interfacing with other devices requires following a particular protocol or standard. For example, interfacing with some SDRAM (synchronous dynamic random-access memory) memories may require following a DDR4 (fourth generation double data rate) protocol.

However, new interface protocols may be developed following the design of a PLD. That is, a PLD may be designed, taped-out, and fabricated before the release of a new interface protocol standard such as DDR4 for SDRAM.

Allowing a PLD to support a new interface standard without changing the design of the PLD itself provides a multitude of advantages. The PLD may not need to be redesigned, recharacterized, and fabricated again. Moreover, an older PLD may still be used for newer interface standards, providing cost savings and potentially extending the market life of older PLDs.

SUMMARY

The subject matter described herein provides a device, such as a programmable logic device, to support a pseudo-open drain (POD) standard used in interface protocols such as fourth generation double data rate (DDR4). In one example, an input/output (I/O) circuit may include an OR gate. Inputs to the OR gate may include an inverted output enable signal and a data signal. The output enable and data signals may, for example, be received from a user's design in soft logic (e.g., programmable or configurable logic) of the PLD. An output of the OR gate may be coupled to components within the I/O circuit. Additionally, a native output enable input of the I/O circuit may be terminated to a fixed voltage. Accordingly, the POD standard may be followed.

These and other features will be presented in more detail in the following specification and the accompanying figures, which illustrate by way of example.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

The techniques and mechanisms disclosed herein are primarily described with reference to Programmable Logic Devices (PLDs) such as Field Programmable Gate Arrays (FPGAs), but are not necessarily limited to PLDs.

FIG. 1Aillustrates an example of soft logic of a PLD providing signals to an Input/Output (I/O) buffer. In an implementation, an I/O may include an I/O buffer125and an I/O pad130. I/O buffer125may receive input signals output enable115and data120from soft logic105(e.g., configurable or programmable logic of a PLD). The output enable115and data120signals may be received from a user design110instantiated within soft logic105. That is, user design110may provide output enable115and data120. In some implementations, the interconnect for the signals may be routed, for example through the placement and routing methodology of the workflow of implementing a PLD, from configured logic associated with user design110in soft logic105to interconnect associated with the inputs of I/O buffer125.

As an example, user design110may include a soft processor (i.e., a processor instantiated within soft logic105). When the processor wants to provide data to another device, such as an external memory peripheral, the processor in user design110may assert an output enable signal115to configure I/O buffer125to provide the data120signal to output pad130. Accordingly, data120is provided to output pad130and available to another device with access to output pad130(e.g., by being connected to a pin associated with output pad130).

FIG. 1Billustrates a circuit schematic of I/O buffer125in accordance with some implementations. InFIG. 1B, I/O buffer125includes four transistors: M1150, M2155, M3160, and M4165. I/O buffer125also includes two inverters135and140. The input of inverter140is output enable115. The input for inverter135is data120. Additionally, high supply voltage VCC and low supply voltage GND are provided.

In an implementation, transistors M1150and M2155may be PMOS transistors. Transistors M3160and M4165may be n-type metal-oxide-semiconductor (NMOS) transistors. InFIG. 1B, Transistor M1150is coupled to a high supply voltage. Transistor M4is coupled to a low supply voltage. Transistor M1150is coupled to transistor M2155. Transistor M2155is coupled to transistor M3160to define an output node170coupled to output pad130. Transistor M3160is coupled to transistor M4165.

Additionally, the gate of transistor M1150is coupled to the output of inverter140. Therefore, the inverse of output enable115is provided to the gate of transistor M1150. That is, if output enable115is high (i.e., “1”), then the gate of transistor M1150is provided a low signal (i.e., “0”). The gates of transistors M2155and M3160are coupled together and further coupled to the output of inverter135. Therefore, the inverse of data120is provided to the gates of transistors M2155and M3160. The gate of transistor M4165is provided output enable115. Output enable115and data120may be provided by a user design, as discussed above. For example, output enable115and data120may be signals routed from user design110in soft logic105to hardwired, native interconnect associated with inputs for I/O buffer125. That is, native output enable170may be a fixed interconnect that receives an output enable115signal from user design110in soft logic105.

FIG. 2Aillustrates a truth table for the I/O buffer ofFIG. 1B. InFIG. 2A, if output enable115is low (indicated as “0”), output node170may be in a high impedance state (tri-stated or floating) indicated as “Z”, i.e., it is undriven. In truth table200, in the first two rows, output enable115is low, and therefore outputs205are both indicated as being in a high impedance state. If output enable115is high, then data120may be “passed” to output node175and provide the appropriate signal onto output pad130.

For example, using the first row of truth table200, if data120is low and output enable115is low, then the output of inverter140inFIG. 1Bis high and the output of inverter135is high. Transistor M1150turns off because it is a PMOS transistor and its gate terminal is coupled to the output of inverter140, which is providing a high signal. Transistor M4165receives output enable115via interconnect170. Accordingly, the gate of transistor M4165is provided output enable115without any inversion, and thus it receives a low signal and turns off.

Transistors M2155and M3160receive the inverse of data120from the output of inverter135. Since data120is low, the output of inverter135is high, and therefore, transistor M2155turns off and transistor M3160turns on. However, as previously discussed, transistor M4165is also turned off, and therefore, output node170is not being pulled high or low. That is, transistors M1150and M2155are turned off, and therefore, high supply voltage VCC is not provided to output node170. Likewise, transistor M4165is turned off, and therefore, low supply voltage GND is not provided to output node170. Accordingly, output node170is floating, or in a high impedance state as indicated by “Z” in truth table200.

In the second row of truth table200, data120is high and output enable115is low. Since output enable120is low, the output at output node175is floating, as indicated by the high impedance “Z” in truth table200. For example, in the circuit ofFIG. 1B, since data120is high, the output of inverter135is low. Transistor M2155turns on and transistor M3160turns off. However, as previously discussed, when output enable is low, transistors M1150and M4165turn off, and therefore, neither high supply voltage VCC nor low supply voltage GND are provided to output node170. Accordingly, output node170is floating.

In the third row of truth table200, data120is low and output enable is high. Therefore, output node170should follow data120. For example, in the circuit ofFIG. 1B, since output enable is high, transistor M4165turns on. Transistor M1150also turns on because the input to inverter140is output enable, which is high, and therefore its output is low. Since data120is low, the output of inverter135is high. Accordingly, transistor M2155turns off and transistor M3160turns on. Since both transistors M3160and M4165are turned on, and M4165is coupled to low supply voltage GND, output node170is pulled low rather than floating.

In the fourth row of truth table200, both data120and output enable115are high. The output at output node170is high since output enable115is high, and therefore, the output follows data120. For example, in the circuit ofFIG. 1B, since output enable115is high, transistor M4165turns on. Additionally, transistor M1150also turns on since the output of inverter140is the inverse of output enable115(i.e., low). Since data120is high, the output of inverter135is low. Thus, transistor M3160turns off and transistor M2155turns on. Therefore, since transistors M1150and M2155are both on, output node170is driven high.

However, tri-stating the outputs when output enable115is low may not be appropriate for every interface standard. For example, some SDRAM (synchronous dynamic random-access memory) memories may require following a DDR4 (fourth generation double data rate) protocol which uses a Pseudo Open Drain (POD) I/O standard. POD I/O does not tri-state the output when the I/O is not supposed to be enabled. Rather, the output may be driven, such as pulled high instead of floating.

In some implementations, floating outputs may be undesirable because tri-stated signals may be more susceptible to signal integrity issues. For example, a tri-stated output may pick up noise which may make the output appear to be toggling. In some applications, such as DDR4, an output toggling in a particular manner may indicate data is being provided at the output. However, if the output is actually tri-stated, there should be no data to be read at the output (i.e., the output is supposed to be disabled). Therefore, the circuit ofFIGS. 1A and 1Bmay not properly function with SDRAM DDR4 devices.

FIG. 2Billustrates a truth table for an I/O buffer compatible with the POD I/O standard. InFIG. 2B, truth table250differs from truth table200ofFIG. 2Ain that if output enable is low, the output is high rather than tri-stated. For example, outputs255are high inFIG. 2Brather than low as in outputs205inFIG. 2Awhen output enable is low. Accordingly, a circuit following truth table250inFIG. 2Bmay support the POD I/O standard used in SDRAM DDR4 devices.

FIG. 3Aillustrates an example of a PLD configured to support the POD I/O standard. In an implementation, an I/O may include I/O buffer125and output pad130. Output enable115and data120may be routed in soft logic105from user design110to OR gate305. OR gate305may include an inverted input for the output enable signal. For example, in an implementation, an inverter may be placed such that the input of the inverter is output enable115and the output of the inverter is coupled to an input of OR gate305. The output of OR gate305may be provided to the data input of I/O buffer125. Additionally, the native output enable input for I/O buffer125may be set or terminated to a fixed voltage, as indicated by “1”375, rather than receiving output enable115.

FIG. 3Billustrates a circuit schematic of an I/O buffer configured to support the POD I/O standard in accordance with some implementations. InFIG. 3B, I/O buffer125includes the same transistors and inverters as the I/O buffer ofFIG. 1B. That is, I/O buffer125inFIG. 3Balso includes four transistors (transistors M1150, M2155, M3160, and M4165) and two inverters (inverters135and140). However, because the native output enable interconnect170for I/O buffer125is terminated high (as indicated by “1”375), and data120and an inverted output enable115are inputs to OR gate305whose output is provided to inverter135, I/O buffer125may be configured to support the POD I/O standard by driving the output to high when the output is disabled.

For example, using the first row of truth table250ofFIG. 2B, if data120is low and output enable120is low, output node170should be high rather than floating as in truth table200. In the circuit ofFIG. 3B, since “1”375drives interconnect170high, the output of inverter140is low, and therefore, transistor M1150turns on. Additionally, transistor M4165also turns on because interconnect170is driven high. That is, because “1”375is terminated high, both transistors M1150and M4165turn on. Output enable115is inverted (i.e., now high) and then provided to an input of OR gate305. Data120is low and also provided as an input to OR gate305. Accordingly, the output of OR gate305is high. The output of OR gate305is provided as an input to inverter135, which provides a low output since the input is high. Accordingly, since the output of inverter135is low, transistor M2155turns on and transistor M3160turns off. Therefore, since transistor M1150and M2155are on, output node170is pulled high to VCC and provided to output pad130.

In the second row of truth table250, data120is high and output enable115is low. The output of OR gate305is high, and therefore, the output of inverter135is low. Accordingly, transistor M2155turns on and transistor M3160turns off. As previously discussed, transistors M1150and M4165are always on because “1”375is terminated high. Therefore, since both transistors M1150and M2155are on, output node170may also be pulled high to VCC and provided to output pad130.

In the third row of truth table250, data120is low and output enable115is high. Since output enable115is inverted before being provided as an input to OR gate305, the inputs to OR gate305are both low, and therefore, the output of OR gate305is low. As such, the output of inverter135is high, and therefore, transistor M3160turns on and transistor M2155turns off. Since transistor M4165is always turned on and transistor M3160is turned on, output node160is pulled low to GND.

In the fourth row of truth table250, both data120and output enable115are high. The output of OR gate305is high, and therefore, the output of inverter135is low. Transistor M2155turns on and transistor M3160turns off. Since transistor M1150is always turned on and transistor M2155is also turned on, output node170is pulled high to VCC.

FIG. 4is a flowchart illustrating a method for modifying a logic design to support the POD I/O standard for DDR4 SDRAM. InFIG. 4, at block410, a logic design may be received. For example, the design may be implemented in a hardware description language (HDL) such as Verilog or VHDL. In another implementation, the design may be synthesized logic or a netlist. In block420, an inverter may be inserted into the logic design. For example, an inverter to invert output enable115may be inserted, or instantiated, into the logic design. In block430, an OR gate may be inserted into the logic design. Additionally, the output of the inverter may be routed to an input of the OR gate. In some implementations, a single logical function incorporating both an inverter and an OR gate may be inserted. In block440, output enable115and data120may be routed from a user's design to the inserted logic (e.g., inverter or OR gate). At block450, the output of the OR gate may be routed to an input of an I/O buffer. In an implementation, the output of the OR gate may be routed to a native data input of the I/O buffer. At block460, a native output enable of the I/O may be routed to a power supply or terminated (e.g., high).

Though the circuits and techniques disclosed herein utilize NMOS and PMOS transistors, any other type of element with the functionality of a switch may be used. For example, bipolar junction transistors, memristors, and other components may be used. Depletion-type and/or enhancement-type NMOS and PMOS transistors may also be used.

FIG. 5illustrates a technique for implementing a programmable chip. An input stage501receives selection information typically from a user for logic such as a processor core as well as other components to be implemented on an electronic device. In one example, the input received is in the form of a high-level language program. A generator program505creates a logic description and provides the logic description along with other customized logic to any of a variety of synthesis tools, place and route programs, and logic configuration tools to allow a logic description to be implemented on an electronic device.

In one example, an input stage501often allows selection and parameterization of components to be used on an electronic device. The input stage501also allows configuration of hard coded logic. In some examples, components provided to an input stage include intellectual property functions, megafunctions, and intellectual property cores. The input stage501may be a graphical user interface using wizards for allowing efficient or convenient entry of information. The input stage may also be a text interface or a program reading a data file such as a spreadsheet, database table, or schematic to acquire selection information. The input stage501produces an output containing information about the various modules selected. At this stage, the user may enter security information about individual components that needs to be isolated. For example, different levels of component security and which components are allowed to communicate with each other may be entered.

In typical implementations, the generator program505can identify the selections and generate a logic description with information for implementing the various modules. The generator program505can be a Perl script creating HDL files such as Verilog, Abel, VHDL, and AHDL files from the module information entered by a user. In one example, the generator program identifies a portion of a high-level language program to accelerate. The other code is left for execution on a processor core. According to various embodiments, the generator program505identifies pointers and provides ports for each pointer. One tool with generator program capabilities is System on a Programmable Chip (SOPC) Builder available from Altera Corporation of San Jose, Calif. The generator program505also provides information to a synthesis tool507to allow HDL files to be automatically synthesized. In some examples, a logic description is provided directly by a designer. Hookups between various components selected by a user are also interconnected by a generator program. Some of the available synthesis tools are Leonardo Spectrum, available from Mentor Graphics Corporation of Wilsonville, Oreg. and Synplify available from Synplicity Corporation of Sunnyvale, Calif. The HDL files may contain technology specific code readable only by a synthesis tool. The HDL files at this point may also be passed to a simulation tool.

As will be appreciated by one of skill in the art, the input stage501, generator program505, and synthesis tool507can be separate programs. The interface between the separate programs can be a database file, a log, or simply messages transmitted between the programs. For example, instead of writing a file to storage, the input stage501can send messages directly to the generator program505to allow the generator program to create a logic description. Similarly, the generator program can provide information directly to the synthesis tool instead of writing HDL files. Similarly, input stage501, generator program505, and synthesis tool507can be integrated into a single program.

A user may select various modules and an integrated program can then take the user selections and output a logic description in the form of a synthesized netlist without intermediate files. Any mechanism for depicting the logic to be implemented on an electronic device is referred to herein as a logic description. According to various embodiments, a logic description is an HDL file such as a VHDL, Abel, AHDL, or Verilog file. A logic description may be in various stages of processing between the user selection of components and parameters to the final configuration of the device. According to other embodiments, a logic description is a synthesized netlist such as an Electronic Design Interchange Format Input File (EDF file). An EDF file is one example of a synthesized netlist file that can be output by the synthesis tool507.

A synthesis tool507can take HDL files and output EDF files. Tools for synthesis allow the implementation of the logic design on an electronic device. Some of the available synthesis tools are Leonardo Spectrum, available from Mentor Graphics Corporation of Wilsonville, Oreg. and Synplify available from Synplicity Corporation of Sunnyvale, Calif. Various synthesized netlist formats will be appreciated by one of skill in the art.

A verification stage513typically follows the synthesis stage507. The verification stage checks the accuracy of the design to ensure that an intermediate or final design realizes the expected requirements. A verification stage typically includes simulation tools and timing analysis tools. Tools for simulation allow the application of inputs and the observation of outputs without having to implement a physical device. Simulation tools provide designers with cost effective and efficient mechanisms for both functional and timing verification of a design. Functional verification involves the circuit's logical operation independent of timing considerations. Parameters such as gate delays are disregarded.

Timing verification involves the analysis of the design's operation with timing delays. Setup, hold, and other timing requirements for sequential devices such as flip-flops are confirmed. Some available simulation tools include Synopsys VCS, VSS, and Scirocco, available from Synopsys Corporation of Sunnyvale, Calif. and Cadence N.C.-Verilog and NC-VHDL available from Cadence Design Systems of San Jose, Calif. After the verification stage513, the synthesized netlist file can be provided to physical design tools519including place and route and configuration tools. A place and route tool locates logic cells on specific logic elements of a target hardware device and connects wires between the inputs and outputs of the various logic elements in accordance with logic and security provided to implement an electronic design. According to various embodiments of the present invention, the place and route tool may perform the techniques of the present invention to implement the various security requirements and rules as defined by the user. The iterative technique may be transparent to the user, but the resulting device can be physically tested at523.

For programmable logic devices, a programmable logic configuration stage can take the output of the place and route tool to program the logic device with the user selected and parameterized modules. According to various embodiments, the place and route tool and the logic configuration stage are provided in the Quartus Development Tool, available from Altera Corporation of San Jose, Calif. As will be appreciated by one of skill in the art, a variety of synthesis, place and route, and programmable logic configuration tools can be used using various techniques of the present invention.

As noted above, different stages and programs can be integrated in a variety of manners. According to one embodiment, the input stage501, the generator program505, the synthesis tool507, the verification tools513, and physical design tools519are integrated into a single program. The various stages are automatically run and transparent to a user. The program can receive the user-selected modules, generate a logic description depicting logic for implementing the various selected modules, and implement the electronic device. As will be appreciated by one of skill in the art, HDL files and EDF files are mere examples of a logic description. Other file formats as well as internal program representations are other examples of a logic description.

FIG. 6illustrates one example of a computer system. The computer system600includes any number of processors602(also referred to as central processing units, or CPUs) that are coupled to devices including memory606(typically a random access memory, or “RAM”), memory604(typically a read only memory, or “ROM”). The processors602can be configured to generate an electronic design. As is well known in the art, memory604acts to transfer data and instructions uni-directionally to the CPU and memory606are used typically to transfer data and instructions in a bi-directional manner.

Both of these memory devices may include any suitable type of the computer-readable media described above. A mass storage device608is also coupled bi-directionally to CPU602and provides additional data storage capacity and may include any of the computer-readable media described above. The mass storage device608may be used to store programs, data and the like and is typically a secondary storage medium such as a hard disk that is slower than memory. The mass storage device608can be used to hold a library or database of prepackaged logic or intellectual property functions, as well as information on generating particular configurations. It will be appreciated that the information retained within the mass storage device608, may, in appropriate cases, be incorporated in standard fashion as part of memory606as virtual memory. A specific mass storage device such as a CD-ROM614may also pass data uni-directionally to the CPU.

CPU602is also coupled to an interface610that includes one or more input/output devices such as such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers. The CPU602may be a design tool processor. Finally, CPU602optionally may be coupled to a computer or telecommunications network using a network connection as shown generally at612. With such a network connection, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described process steps. It should be noted that the system600might also be associated with devices for transferring completed designs onto a programmable chip. The above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.

While particular embodiments of the invention have been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, embodiments of the present invention may be employed with a variety of components and should not be restricted to the ones mentioned above. It is therefore intended that the invention be interpreted to include all variations and equivalents that fall within the true spirit and scope of the present invention.