Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

PRIORITY APPLICATION

This application claims the benefit of priority to Malaysian Application Serial Number PI 2018701247, filed Mar. 27, 2018, which is incorporated herein by reference in its entirety.

FIELD

This disclosure relates to through-silicon via techniques with face-to-face multiple die computing apparatus that use redistribution layers for packaging substrates.

BACKGROUND

DETAILED DESCRIPTION

Face-to-face (F2F), through-silicon via (TSV) multi-die apparatus are assembled into a chip-scale package (CSP) that approaches the footprint of a first semiconductive device. Several TSVs allow all inter-chip interconnections to be within the first die footprint. In an embodiment, such packages are achieved without necessarily conforming to industry-norm CSPs. Chip proximity by the F2F architecture, allows for higher-speed signal transmission. Heat management is carried out by a single heat sink that forms a heat-enabling solution for the F2F TSV chip package.

FIG. 1Ais a cross-section elevation of a semiconductive wafer101during processing according to an embodiment. A semiconductive wafer101includes several individual die sectors, including a first die sector101′, a subsequent die sector101nth, and a second die sector101″. It is understood that several individual dice may be processed from a single wafer according to the several disclosed embodiments, but three individual dice are illustrated as exemplars.

Processing is directed to the first die sector101′. The first die sector101′ is referred to as the first semiconductive device110. The first semiconductive device110includes an active surface114and a backside surface116. The active surface114includes active devices and metallization118(hereinafter metallization118). In an embodiment, a first through-silicon via (TSV)120and a second TSV122are part of several TSVs that communicate from the backside surface116to the metallization118. In an embodiment, a first electrical bump124is coupled to the metallization118, as well as a second electrical bump126is coupled to the metallization118. In an embodiment, the electrical bumps124and126are solder bumps. In an embodiment, the electrical bumps124and126are copper pillars.

FIG. 1Bis a cross-section elevation of the semiconductive wafer101depicted inFIG. 1Aafter further processing according to an embodiment. A semiconductive wafer composite package includes the semiconductor wafer101depicted inFIG. 1A, as well as a semiconductor wafer102that is identical to the semiconductor wafer101. The two wafers101and102are assembled face-to-face with respective adhesives128and130, which are bonded to a medium such as polymer media132that acts as a carrier.

FIG. 1Cis a cross-section elevation of the semiconductor wafer composite package depicted inFIG. 1Bafter further processing according to an embodiment. The two semiconductor waters101and102have each been assembled to respective redistribution layers134and136.

Attention is directed to the first die110. The redistribution layer (RDL)134, includes but is not limited to a two-layer fan-out distribution architecture. In an embodiment, the RDL134includes an inner via138that contacts the first die100, a first trace level140that contacts the inner via. Opposite the inner via138and first trace are an outer via142and an RDL bond pad144. It is understood that the RDL134may have a three-layer fan-out, or fan-in architecture. Similarly, the RDL134may have a four-layer architecture, but a two-layer, fan-out architecture is illustrated.

As illustrated, each die in each wafer101and102is processed and fitted with an RDL at wafer-level processing. The adhesives128and130and the carrier132hold the wafers101and102sufficiently rigidly to allow processing the respective RDLs134and136. In an embodiment, the respective RDLs134and136are separately processed and are picked-and-placed onto wafers101and102.

FIG. 1Dis a cross-section elevation of a portion of the semiconductor wafer composite package depicted inFIG. 1Bafter further processing according to an embodiment. The first wafer101has been released from the carrier132and the adhesive128. The first wafer101and the corresponding RDL134have been inverted and seated upon a carrier146. In an embodiment, the first die110(and all dice within the first water101) are tested by use of the RDL134, which allows for bin splitting for each die within the first wafer101as well as each accompanying to-be-singulated RDL of the RDL134. In an embodiment, testing is done before separating the first wafer101and the second wafer102from the adhesives128and130and the polymer media132.

In an embodiment after testing, a flux is applied to the first and subsequent electrical bumps124and126in preparation for bonding various types of daughter dice to the first die110.

FIG. 1Eis a cross-section elevation of the first wafer101and its corresponding wafer-level RDL134after further processing according to an embodiment. The first die110has been further processed by bonding a subsequent die148to the first electrical bump124, and the first die has also been further processed by bonding a second die150to the second electrical bump126.

FIG. 1Fis a cross-section elevation of the first wafer101, the corresponding RDL, and bonded daughter dice148and150after further processing according to an embodiment. After bonding of the subsequent die148and the second die150, a wafer-level molding compound152is formed over the first wafer101and the several daughter dice148and150.

In an embodiment, the wafer-level molding compound152underfills the respective subsequent and second dice148and150, such that the respective first and second electrical bumps124and126are also contacted with the wafer-level molding compound152.

Attention is directed to the subsequent die148, which includes an active surface154and a backside surface156. The active surface154includes active devices and metallization158(hereinafter metallization158). Similar to the subsequent die148, the second die150is similarly oriented and has active and backside surfaces and metallization.

The subsequent die148and the second die150are each mounted F2F with the first die110and the subsequent and second dice148and150each electrically contacts the first die110through the respective first and second electrical bumps124and126.

In an embodiment, processing of the wafer-level molding compound152is done by backgrinding to expose the subsequent die backside surface156(as well as the second die backside surface).

In an embodiment, the subsequent die148and the second die150do not have the same approximate thicknesses. In example embodiment as illustrated inFIG. 1E, the subsequent die148has a lower Z-height than the second die150. In this example embodiment, backgrinding is done to achieve substantially the same backside height from the first die110metallization118for the respective subsequent and second dice148and150. As illustrated, both the wafer-level molding compound152and the respective subsequent and second dice148and150have substantially the same Z-height, as used within conventional backgrinding parameters.

FIG. 1Gis a cross-section elevation of the semiconductor wafer composite package depicted inFIG. 1Fafter further processing according to an embodiment. The first die110has been inverted and a ball-grid array160(one landside electrical bump160enumerated) has been assembled to the several RDL bond pads144(one RDL bond pad144enumerated).

FIG. 1His a cross-section elevation of the semiconductor wafer composite package105depicted inFIG. 1Gafter package singulation according to an embodiment. The several die sectors101′,101″ and101nthare singulated and the exemplary first die110contains the first die sector101′. In an embodiment, singulation is done by a sawing technique to singulate the several die sectors101′,101″ and101nthwhile protecting the several structures of the RDL134′, the subsequent and second dice148and150, respectively.

FIG. 1is a cross-section elevation of one F2F, TSV, multi-die apparatus100that has been assembled into a chip-scale package (CSP) that approaches the footprint of the first semiconductive device110after further processing of structures depicted inFIG. 1Haccording to an embodiment. In an embodiment, the F2F, TSV, multi-de apparatus100has the relative dimensions as illustrated, but it is not necessarily within industry-norm relative dimensions of chip-scale packaging.

In an embodiment, a heat sink162is seated upon the backside surface156of the subsequent die148(as well as the backside surface of the second die150) by use of a thermal adhesive164.

As illustrated the first TSV120and the second TSV122are part of several TSVs that communicate from the backside surface116to the metallization118. In an embodiment as illustrated, the several TSVs are grouped into a region of higher TSV density (illustrated along the X-direction), where the subsequent die148and the second die150approximately abut. In an embodiment, the several TSVs are uniformly dispersed throughout the first die110.

In an embodiment, the first die110is a processor such as made by Intel Corporation of Santa Clara, Calif., the subsequent die148is a memory die, and the second die150is a memory-controller hub (MCH). In an embodiment, the first die150is a platform-controller hub (PCH), the subsequent die148is a processor and the second die150is a memory die. In an embodiment, the first die150is an MCH, the subsequent die148is a processor and the second die150is a baseband processor. In an embodiment, the first die150is both a PCH and an MCH, the subsequent die148is a processor and the second die150is a memory die.

As illustrated, the first semiconductive device110has an X-Y footprint (where the Y-direction is into and out of the plane of the drawing) and the X-Y footprint may be referred to as a die shadow. At singulation, the die shadow is the largest X-Y footprint that is derived from any singluated semiconductive device110, although the RDL134may have substantially the same X-Y dimensions as the die shadow, within conventional parameters of wafer-level RDL singulation techniques such as the effects of a die and RDL sawing procedure. Similarly, the subsequent and second semiconductive devices148and150are within the die shadow. Similarly, the several landside electrical bumps160are also confined within the die shadow.

Whereas the first semiconductive device110is central to the F2F, TSV, chip package, multi-die apparatus100, the “die shadow” is cast in both directions along the Z-direction.

In a system embodiment, the F2F, TSV, chip package, multi-die apparatus100, is assembled to a board166such as a motherboard in a computing system. In an embodiment, the board166includes a shell168that provides at least one of physical and electrical-insulation protection to the F2F, TSV, chip package, multi-die apparatus100. In an embodiment, the shell168is the outer shell of a hand-held computing system such as a wireless communicator.

FIG. 2is a top plan of a subsequent die248, a second die250and a third die251, all of which are F2F mounted on a first die210according to an embodiment. The first die210is illustrated in ghosted lines to represent being positioned directly below (Z-direction) the several dice248,250and251, similarly to the subsequent die148and second die150being positioned directly below the first die110depicted inFIG. 1. The first die210is represented slightly smaller than the composite footprint of the several dice248,250and251to illustrate perspective. In an embodiment, an RDL234is disposed below the first die210. The RDL234is also represented slightly smaller than the footprint of the first die210to illustrate perspective.

In an embodiment, a ball-grid array260(one landside electrical bump260enumerated) has been mated to the RDL234, similarly to the ball-grid array160mated to the RDL134illustrated inFIG. 1. The ball-grid array260is also depicted in ghosted lines to represent position below several other structures.

In an embodiment, TSV communication between the first die210and the respective subsequent, second and third dice248,250and251, is done with several TSVs. A first TSV220couples the first die210to the subsequent die248. A second TSV222couples the first die210to the second die250. A third TSV223couples the first die210to the third die251.

In an embodiment, the respective first, second and third TSV220,222and223are part of several TSVs that are clustered in the first die210below the intersection of the respective subsequent, second and third dice248,250and251. In an embodiment, the clustering as illustrated may be described as having a higher TSV density at an intersection between two dice that are F2F with the first die210, than at an edge of the first die210. In an embodiment, the clustering as illustrated may be described as having a higher TSV density at an intersection between three dice that are F2F with the first die210, than at an edge of the first die210. This asymmetrical clustering embodiment is depicted inFIG. 2.

Similarly to the die shadow embodiments disclosed with respect to the semiconductor apparatus100depicted inFIG. 1, a die shadow for the first semiconductive device210substantially covers all other structures depicted inFIG. 2.

FIG. 3is a top plan of a subsequent die348, a second die350and a third die351, all of which are F2F mounted on a first die310according to an embodiment. The first die310is illustrated in ghosted lines to represent being positioned directly below (Z-direction) the several dice348,350and351, similarly to the subsequent die248and second die250being positioned directly below the first die210depicted inFIG. 2. The first die310is represented slightly smaller than the composite footprint of the several dice348,350and351to illustrate perspective. In an embodiment, an RDL334is disposed below the first die310. The RDL334is also represented slightly smaller than the footprint of the first die310to illustrate perspective.

In an embodiment, a ball-grid array360(one landside electrical bump360enumerated) has been mated to the RDL334, similarly to the hall-grid array260mated to the RDL234illustrated inFIG. 2. The ball-grid array360is also depicted in ghosted lines to represent position below several other structures.

In an embodiment, TSV communication between the first die310and the respective subsequent, second and third dice348,350and351, is done with several TSVs. A first TSV320couples the first die310to the subsequent die348. A second TSV322couples the first die310to the second die350. A third TSV323couples the first die310to the third die351.

In an embodiment, the respective first, second and third TSV320,322and323are part of several TSVs that are substantially uniformly distributed across the first die310below the respective subsequent, second and third dice348,350and351. In an embodiment, the substantially uniform distribution as illustrated may be described as having the same TSV density at an intersection between two dice that are F2F with the first die310, compared to any grouping of four or more TSV at an edge of the first die310. This clustering embodiment is depicted inFIG. 3. In an embodiment, TSV density per unit area below any of the dice that are F2F with the first die, is the same as density per unit area below any other of the dice.

Similarly to the die shadow embodiments disclosed with respect to the semiconductor apparatus100depicted inFIG. 1, a die shadow for the first semiconductive device310substantially covers all other structures depicted inFIG. 3.

FIG. 4is a process flow diagram according to several embodiments.

At410, the process includes forming first and second electrical bumps on a metallization of a first semiconductive device at an active surface.

At420, the method includes forming a redistribution layer on the first semiconductive device at a backside surface to couple with a through-silicon via that communicates from the metallization to the backside surface.

At430, the process includes face-to-face assembling subsequent and second semiconductive devices with the first semiconductive device to the respective first and second electrical bumps.

At440, the process includes singulating the first semiconductive device from a wafer.

At450, the process includes seating a heat sink on the subsequent and second semiconductive device backside surfaces.

At460, the process includes assembling the semiconductor apparatus to a computing system.

FIG. 5is included to show an example of a higher-level device application for the disclosed embodiments. The F2F, TSV, chip package, multi-die apparatus embodiments may be found in several parts of a computing system. In an embodiment, the F2F, TSV, chip package, multi-die apparatus embodiments can be part of a communications apparatus such as is affixed to a cellular communications tower. In an embodiment, a computing system500includes, but is not limited to, a desktop computer. In an embodiment, a system500includes, but is not limited to a laptop computer. In an embodiment, a system500includes, but is not limited to a tablet. In an embodiment, a system500includes, but is not limited to a notebook computer. In an embodiment, a system500includes, but is not limited to a personal digital assistant (PDA). In an embodiment, a system500includes, but is not limited to a server. In an embodiment, a system500includes, but is not limited to a workstation. In an embodiment, a system500includes, but is not limited to a cellular telephone. In an embodiment, a system500includes, but is not limited to a mobile computing device. In an embodiment, a system500includes, but is not limited to a smart phone. In an embodiment, a system500includes, but is not limited to an internet appliance. Other types of computing devices may be configured with the microelectronic device that includes TSV pillar and electrical bump in backside recess embodiments.

In an embodiment, the processor510has one or more processing cores512and512N, where512N represents the Nth processor core inside processor510where N is a positive integer. In an embodiment, the electronic device system500using a F2F, TSV, chip package, multi-die apparatus embodiment that includes multiple processors including510and505, where the processor505has logic similar or identical to the logic of the processor510. In an embodiment, the processing core512includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In an embodiment, the processor510has a cache memory516to cache at least one of instructions and data for the multi-layer solder resist on a semiconductor device package substrate in the system500. The cache memory516may be organized into a hierarchal structure including one or more levels of cache memory.

In an embodiment, the processor510includes a memory controller514, which is operable to perform functions that enable the processor510to access and communicate with memory530that includes at least one of a volatile memory532and a non-volatile memory534. In an embodiment, the processor510is coupled with memory530and chipset520. In an embodiment, the chipset520is part of a F2F, TSV, chip package, multi-die apparatus embodiment depicted in any ofFIGS. 1-3. The processor510may also be coupled to a wireless antenna578to communicate with any device configured to at least one of transmit and receive wireless signals. In an embodiment, the wireless antenna interface578operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UVB), Bluetooth, WiMax, or any form of wireless communication protocol.

In an embodiment, the volatile memory532includes, but is not limited to, Synchronous Dynamic Random-Access Memory (SDRAM), Dynamic Random-Access Memory (DRAM), RAMBUS Dynamic Random-Access Memory (RDRAM), and/or any other type of random access memory device. The non-volatile memory534includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), cross-point memory or any other type of non-volatile memory device.

The memory530stores information and instructions to be executed by the processor510. In an embodiment, the memory530may also store temporary variables or other intermediate information while the processor510is executing instructions. In the illustrated embodiment, the chipset520connects with processor510via Point-to-Point (PtP or P-P) interfaces517and522. Either of these PtP embodiments may be achieved using a F2F, TSV, chip package, multi-die apparatus embodiment as set forth in this disclosure. The chipset520enables the processor510to connect to other elements in a F2F, TSV, chip package, multi-die apparatus recess embodiment in a system500. In an embodiment, interfaces517and522operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In an embodiment, the chipset520is operable to communicate with the processor510,505N, the display device540, and other devices572,576,574,560,562,564,566,577, etc. The chipset520may also be coupled to a wireless antenna578to communicate with any device configured to at least do one of transmit and receive wireless signals.

The chipset520connects to the display device540via the interface526. The display540may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, the processor510and the chipset520are merged into a F2F, TSV, chip package, multi-die apparatus embodiment in a system. Additionally, the chipset520connects to one or more buses550and555that interconnect various elements574,560,562,564, and566. Buses550and555may be interconnected together via a bus bridge572such as at least one F2F, TSV, chip package, multi-die apparatus embodiment. In an embodiment, the chipset520, via interface524, couples with a non-volatile memory560, a mass storage device(s)562, a keyboard/mouse564, a network interface566, smart TV576, and the consumer electronics577, etc.

While the modules shown inFIG. 5are depicted as separate blocks within the F2F, TSV, chip package, multi-die apparatus embodiments in a computing system500, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory516is depicted as a separate block within processor510, cache memory516(or selected aspects of516) can be incorporated into the processor core512.

To illustrate the F2F, TSV, chip package, multi-die apparatus embodiments and methods disclosed herein, a non-limiting list of examples is provided herein:

Example 1 is a semiconductor apparatus, comprising: a first semiconductive device including an active surface and a backside surface; a through-silicon via (TSV) that communicates from the active surface to the backside surface; first and second electrical bumps coupled to the active surface; subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the first and subsequent semiconductive devices are positioned face-to-face with the first semiconductive device and a redistribution layer (RDL) that contacts the first semiconductive device backside surface and the TSV.

In Example 2, the subject matter of Example 1 optionally includes wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device, further including: a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device.

In Example 3, the subject matter of any one or more of Examples 1-2 optionally include wherein the first semiconductive device exhibits a die shadow, and wherein the RDL is configured substantially within the die shadow.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow.

In Example 5, the subject matter of any one or more of Examples 1-4 optionally include wherein the first and second electrical bumps are copper pillars.

In Example 6, the subject matter of any one or more of Examples 1-5 optionally include wherein each of the subsequent and second semiconductive devices include active and backside surfaces, wherein the first and second electrical bumps are copper pillars that contact the first semiconductive device active surface to the respective subsequent and second semiconductive device active surfaces.

In Example 7, the subject matter of any one or more of Examples 1-6 optionally include wherein each of the subsequent and second semiconductive devices include active and backside surfaces, further including a heat sink seated on the respective subsequent and second semiconductive device backside surfaces.

In Example 8, the subject matter of any one or more of Examples 1-7 optionally include a molding compound that contacts the respective first and second electrical bumps.

In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the subsequent and second semiconductive devices are configured within a die shadow of the first semiconductive device, and wherein the RDL is configured within the die shadow.

In Example 10, the subject matter of any one or more of Examples 1-9 optionally include a molding compound that contacts the respective first and second electrical bumps, wherein the first and second electrical bumps are copper pillars; wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device; a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device; wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow; a heat sink seated on the respective subsequent and second semiconductive device backside surfaces.

In Example 11, the subject matter of any one or more of Examples 1-10 optionally include wherein the TSV is one of a plurality of TSVs, and wherein the plurality of TSVs are asymmetrically configured within the first semiconductive device.

In Example 12, the subject matter of any one or more of Examples 1-11 optionally include a third semiconductive device face-to-face coupled to the first semiconductive device.

In Example 13, the subject matter of any one or more of Examples 1-12 optionally include a third semiconductive device face-to-face coupled to the first semiconductive device; wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device; a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device; a third TSV that communicates from the active surface to the backside surface, wherein the third TSV is positioned below the third semiconductive device; and wherein the first semiconductive device exhibits a die shadow, and wherein the RDL is configured substantially within the die shadow.

In Example 14, the subject matter of any one or more of Examples 1-13 optionally include a third semiconductive device face-to-face coupled to the first semiconductive device; wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device; a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device; a third TSV that communicates from the active surface to the backside surface, wherein the third TSV is positioned below the third semiconductive device; wherein the first semiconductive device exhibits a die shadow, and wherein the RDL is configured substantially within the die shadow; and wherein the subsequent, second and third semiconductive devices are substantially within the die shadow.

Example 15 is a process of assembling a semiconductor apparatus, comprising: forming first second electrical bumps on a metallization of a first semiconductive device, wherein the first semiconductive device includes an active surface and a backside surface, and wherein the metallization is part of the active surface; forming a redistribution layer on the first semiconductive device backside surface, wherein the first semiconductive device includes a through-silicon via (TSV) that communicates from the backside surface to the metallization; assembling a subsequent semi conductive device and a second semiconductive device to the respective first and second electrical bumps, wherein the first and subsequent semiconductive devices are assembled face-to-face to the first semiconductive device; and wherein the first semiconductive device forms a footprint that shadows the subsequent semiconductive device, the second semiconductive device and the redistribution layer.

In Example 16, the subject matter of Example 15 optionally includes contacting first and second electrical bumps with a molding compound that also contacts the first, subsequent and second semiconductive devices; and planarizing the molding compound at the subsequent and second semiconductive device backside surfaces.

In Example 17, the subject matter of any one or more of Examples 15-16 optionally include contacting the first and second electrical bumps with a molding compound that also contacts the first, subsequent and second semiconductive devices; planarizing the molding compound at the subsequent and second semiconductive device backside surfaces; and seating a heat sink at the subsequent and second semiconductive device backside surfaces.

In Example 18, the subject matter of any one or more of Examples 15-17 optionally include wherein the first semiconductive device is part of a semiconductive wafer including a plurality of semiconductive devices, further including after assembling the second semiconductive device: contacting the first and second electrical bumps with a molding compound that also contacts the first, subsequent and second semiconductive devices; planarizing the molding compound at the subsequent and second semiconductive device backside surfaces; and singulating the first semiconductive device from the semiconductive wafer to achieve a chip-scale package with the subsequent and second semiconductive devices and the redistribution layer.

In Example 19, the subject matter of any one or more of Examples 15-18 optionally include wherein the first semiconductive device is part of a semiconductive wafer including a plurality of semiconductive devices, further including after assembling the second semiconductive device: contacting the first and second electrical bumps with a molding compound that also contacts the first, subsequent and second semiconductive devices; planarizing the molding compound at the subsequent and second semiconductive device backside surfaces; and singulating the first semiconductive device from the semiconductive wafer to achieve a chip-scale package with the subsequent and second semiconductive devices and the redistribution layer; and seating a heat sink at the subsequent and second semiconductive device backside surfaces.

Example 20 is a computing system, comprising: a first semiconductive device including an active surface and a backside surface; a through-silicon via (TSV) that communicates from the active surface to the backside surface; first and second electrical bumps coupled to the active surface; subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the first and subsequent semiconductive devices are positioned face-to-face with the first semiconductive device; a redistribution layer (RDL) that contacts the first semiconductive device backside surface and the TSV; a molding compound that contacts the respective first and second electrical bumps, wherein the first and second electrical bumps are copper pillars; wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device; a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device; wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow; and wherein the semiconductor apparatus is part of a chipset.

In Example 21, the subject matter of Example 20 optionally includes a heat sink seated on the respective subsequent and second semiconductive device backside surfaces; and a ball-grid array contacting the RDL, RDL is coupled to a board, and wherein the board includes a shell that provides electrical insulation for the first semiconductive device.

With semiconductive devices, an “active surface” includes active semiconductive devices and may include metallization that connects to the active semiconductive devices. A “backside surface” is the surface opposite the active surface.