Latency locked loop circuit for driving a buffer circuit

In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.

FIELD

The present disclosure is generally related to buffer circuits, and more particularly to a latency locked loop circuit for driving a buffer circuit.

BACKGROUND

Pulse width modulation (PWM) systems are used to generate analog signals from digital data. PWM signals can be used to drive an H-bridge or similar device (such as an amplifier or other buffer circuit) to achieve high power and high efficiency amplification. An ideal H-bridge is simply a buffer that reproduces the digital waveforms with higher output amplitude. Preferably, the buffer has a fixed delay, providing edge transitions (rising or falling) at its output at a fixed time offset from the input.

Unfortunately, the propagation delay of a practical H-bridge implementation may be variable and/or signal dependent. In Class D amplifiers, such as those used in audio applications, propagation delay variations through an H-bridge or buffer circuit represents a non-linearity. Such a non-linearity can result in degraded Total Harmonic Distortion of the audio signal. If spectral energy spreading techniques have been applied to the PWM signal, such a non-linearity can cause high frequency noise to fold into the lower frequencies of the audio band or the band of interest, resulting in harmonic distortion or degraded signal-to-noise ratio (SNR).

SUMMARY

In one embodiment, a circuit includes a buffer circuit having a buffer input and a buffer output and includes a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal of the buffer, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the buffer output to produce a substantially constant total delay from the signal input to the buffer output.

In another embodiment, a device includes a load circuit, a buffer circuit, and a latency locked loop (LLL) circuit. The buffer circuit includes a buffer input and a buffer output that is coupled to the load circuit. The LLL circuit includes an LLL input for receiving a first pulse width modulated (PWM) signal, a feedback input coupled to the buffer output, and an LLL output terminal coupled to the buffer input. The LLL circuit is configured to control pulse widths and pulse positions of pulses within an output signal on the output terminal by controlling a propagation delay of individual edge transitions of the first PWM signal.

In yet another embodiment, a circuit includes an H-bridge comprising first and second inputs and first and second outputs and includes a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs configurable to receive first and second pulse width modulated (PWM) signal, respectively. The LLL circuit further including a first LLL output coupled to the first input of the H-bridge and a second LLL output coupled to the second input of the H-bridge. The LLL circuit is configured to automatically control a first variable delay associated with the first LLL input and a second variable delay associated with the second LLL input to provide a substantially constant total propagation delay from the first and second LLL inputs to the first and second outputs of the H-bridge for individual edge transitions within the first and second PWM signals.

In still another embodiment, a circuit includes an H-bridge including an input and including an output configurable to provide a pulse width modulated (PWM) output signal to a load circuit. The circuit further includes a latency locked loop (LLL) circuit including an LLL input for receiving a PWM input signal and including an LLL output coupled to the input of the H-bridge. The LLL circuit is configured to measure pulse widths of the PWM output signal and to adjust edge timing of the PWM input signal at the input of the H-bridge to ensure that pulse widths of the PWM output signal are substantially equal to pulse widths of the PWM input signal.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A latency locked loop circuit is disclosed below that uses feedback to eliminate propagation delay variations of an H-bridge type driver, ensuring that the net propagation delay through the H-bridge is substantially constant. In particular, the feedback is used to adjust a variable delay to offset propagation delay variations through the H-bridge, keeping the delay substantially constant and thus the H-bridge is linearized. Further, the data rate of the signal is not changed. In a particular example, the latency locked loop circuit uses timing feedback around the H-bridge to provide timing edge placement at the output of the H-bridge that is signal independent, while retaining the content of the original signal.

Before discussing the latency locked loop circuit in detail, it is important to understand how an H-bridge introduces propagation delay variations into the output waveform. A representative example of such a circuit is described below with respect toFIG. 1.

In the following discussion, the term “connected” is used to refer to both direct connections and indirect connections between components. It should be understood that, within the illustrated embodiments, additional circuit elements and parasitic components (not shown) may exist within the circuitry, and that the illustrated connections may include such elements and/or parasitic components. Accordingly, the term “connected” as used herein includes direct connections as well as indirect couplings.

FIG. 1is a diagram of a circuit100including a conventional H-bridge driver circuit102with a load including a speaker122. H-bridge102includes two half H-bridges, including half H-bridge110and a half H-bridge112. Circuit100further includes inputs104and106and outputs connected to a speaker122through an inductive/capacitive load represented by inductors114and116and capacitors118and120.

In operation, first and second input signals (i.e., a positive input signal (INP)124and a negative input signal (INN)126) are applied to inputs104and106. The first and second input signals can be pulse-width modulated (PWM) signals. Alternatively, the first and second input signals can be other types of differentially encoded digital signals. H-bridge102amplifies (and delays) pulses within the signals to produce corresponding positive output signal (OUTP)134and negative output signal (OUTN)136. Propagation delays within output signals134and136may vary based, in part, on the size of transistors used within H-bridge102and on the load current provided to the load circuitry, represented by speaker122and the inductive-capacitive connection, represented by inductors114and116and by capacitors118and120.

In general, inductors114and116“store” an average current that follows the audio signal content contained within input signals124and126. Superimposed on this average current is a high frequency sawtooth ripple current due to the switching. For example, for a maximum single-ended output swing of 6.6V, the average inductor current could be as high as 1.0 ampere with a sawtooth ripple current of plus or minus 50 mA, depending on the switching frequency. As the audio signal level changes, the average currents stored in the inductors114and116also change, and these current levels can either help or impede signal propagation through the H-bridge102. Further, in complementary metal oxide semiconductor (CMOS) implementations, parasitic effects, such as the body effect, can impact threshold voltages and other parameters of the MOS devices, contributing to variations in the propagation delays.

Such propagation delays may vary according to the particular transition edge. In particular, rising edge transitions may have a different propagation delay than that of falling edge transitions. For differential signals where the content of interest is contained in the difference between the signals, such propagation delays can lead to distortion of the content.FIGS. 2 and 3below depict an example where the timing of the output waveforms of output signals134and136does not match that of the input waveforms of input signals124and126.

FIG. 2is a timing diagram200depicting differential input and output signals (OUTPand OUTN)134and136of the H-bridge102ofFIG. 1for positive output signals. In this example, the fixed portion of the propagation delay from H-bridge102has been removed. As shown, rising edge transitions of the positive input (INP)124are delayed within the positive output (OUTP)134by a first offset delay (d1) that is different from the second offset delay (d2) associated with the falling edge transition of the positive output (OUTP)134relative to the corresponding falling edge of the positive input (INP)124. Further, the rising edge transitions of the negative input (INN)126are delayed within the negative output (OUTN)136by a third offset delay (d3) that is different from the fourth offset delay (d4) associated with the falling edge transition of the negative output (OUTN)136.

It should be understood that the offset delays (d1, d2, d3, and d4) can be different from one another. Such delay variation between rising and falling edges contributes a nonlinearity that reduces the signal-to-noise-plus-distortion ratio (SNDR) of the output signal.

FIG. 3is a timing diagram300depicting differential input and output signals (OUTPand OUTN)134and136of the H-bridge102ofFIG. 1for negative output signals. In this instance, the edge transitions (d1, d2, d3, and d4) in the output signals134and136again vary from their corresponding input signals124and126; however, the variations are different from those associated with the positive output signals inFIG. 2.

Such variations represent four possible propagation delay modes: rise transition, fall transition, positive load current, and negative load current. An illustrative example of a representative propagation delay versus load current for a rising edge transition and for a falling edge transition is described below with respect toFIG. 4.

FIG. 4is a graph400of propagation delay as a function of the load current for rising and falling edges of a signal through H-bridge102ofFIG. 1. Within graph400, the horizontal axis represents load current in amperes and the vertical axis represents the delay in nanoseconds. Graph400shows a delay for a rising edge transition402and a delay for a falling edge transition404as a function of the load current. Unfortunately, the rising and falling edge transitions402and404do not have odd or even symmetry, so propagation delays through the H-bridge102do not cancel. Thus, the propagation error should be corrected and controlled, which correction may include managing up to four independent states.

To better understand the source of the variable propagation delays, it should be understood that buffer circuits, such as H-bridges, often use fairly large transistor devices, which may have large gate-to-source capacitances. Such gate-to-source capacitances introduce delays in switching in response to transitions within the input signal. One possible model of the conventional H-bridge that takes into account the delay in switching is described below with respect toFIG. 5.

FIG. 5is a diagram of a representative model of a conventional H-bridge500, such as the H-bridge102depicted inFIG. 1. H-bridge500includes supply terminals502and504, which may be positive and ground terminals. Additionally, H-bridge500includes a PMOS transistor506, an NMOS transistor508, an output terminal510, and diodes512and514. PMOS transistor506has a source connected to supply terminal502, a gate connected to supply terminal502through a gate current source (Igp) and a drain connected to output terminal510. NMOS transistor508includes a drain connected to output terminal510, a gate connected to supply terminal504through a gate current source (Ign), and a source connected to supply terminal504. Diode514includes an anode connected to supply terminal504and a cathode connected to the output terminal510. Diode512includes an anode connected to the output terminal510and a cathode connected to the supply terminal502. The output terminal510is connected to an output current source (ILoad).

The output current source (ILoad) is used to represent the current “stored” in the load inductor. The NMOS and PMOS transistors508and506, respectively, are turned on and off with pre-drivers that are represented as current sources (Ign and Igp). In most Class D amplifiers, the output transistors are very large, resulting in extremely large gate to source capacitances; therefore, the gate-to-source (Vgs) voltages cannot be changed quickly, so the pre-drivers can be modeled as current sources (Ign and Igp). Assuming that the load current (ILoad) is positive and assuming that the NMOS transistor508should be turned on to pull the output voltage on output terminal510to zero, the square law model of the transistor drain current can be calculated according to Equation 1 below:
I=K[Vgs−VT]2(1)

In Equation 1, the variable (K) is a constant, the variable (VT) is the threshold voltage, and the variable (Vgs) is the gate-to-source voltage. The gate capacitance of the NMOS transistor508is charged up to a level of Vgs that can sink the load current (ILoad). Larger load currents require the Vgs to be raised to a higher level, which requires more time to charge based on current supplied by the current pre-driver (assuming the current pre-driver supplies a substantially constant current). Thus, within the model, propagation time increases with larger load currents, which is consistent with real implementations. The propagation delay (τP) can be estimated according to Equation 2 below:

In Equation 2, the variable (Cgsn) is the gate-to-source capacitance of NMOS transistor508. It should be understood that Equation 2 is valid for positive load currents and does not take into account the turning off of the PMOS transistor506. However, Equation 2 nevertheless does confirm that larger load currents lead to increased propagation times (Tp).

If the load current (ILoad) is negative, the output voltage will decrease to ground as soon as the PMOS transistor506turns off, independent of the state of NMOS transistor508because the load current (ILoad) is pulled through the protection diode514, which is connected to supply terminal504(i.e., to ground).

In the context of PWM signals, all desired audio information is contained in the edges of the PWM signal. At the output of the H-bridge500, if the placement of edge transitions is signal dependent (i.e. load current dependent), then a non-linearity results. Such signal dependent propagation delay causes harmonic distortion of the low frequency signal content at the output of the H-bridge500. Since a PWM signal has high frequency components, it is possible that high frequency out-of-band energy (noise or distortion) can be folded into the lower frequency audio passband due to the nonlinearities.

Embodiments of a latency locked loop circuit described below with respect toFIGS. 6 and 7can be used to dynamically adjust the propagation delay to provide a substantially constant total propagation delay from the inputs to the outputs of the circuit by controlling timing for rising and falling edge transitions independent of the input waveform and independent of the load current. An example of a latency lock loop circuit is described below with respect toFIG. 6that uses a timing feedback from the output of the H-bridge to dynamically adjust timing edge placement at the input of the H-bridge, producing an output signal having a substantially constant propagation delay that is signal and load current independent.

FIG. 6is a block diagram of a circuit600including half H-bridge110and including a latency lock loop (LLL) circuit604. LLL circuit604includes a variable delay circuit606having an input for receiving an input signal (such positive input signal (INP)124) and an output connected to an input of half H-bridge110. Variable delay circuit606also includes a control input for receiving an adjustment signal from loop filter612. LLL circuit604further includes a reference delay circuit608including an input for receiving positive input signal (INP)124and an output connected to a first input of a phase/frequency detector (PFD)610. PFD610includes a second input connected to an output terminal of half H-bridge110for receiving edge transitions of positive output signal (OUTP)134and includes an output connected to loop filter612. While in the illustrated embodiment, PFD610is shown, it should be understood that other types of phase detectors may also be used.

In the illustrated embodiment ofFIG. 6, it is assumed, for simplicity, that the rising and falling edges of the half H-bridge110have the same delay variation with a given load current. The input signal (INP)124is applied both to variable delay circuit606and to reference delay circuit608simultaneously. Reference delay circuit608has a fixed delay that is independent of the input signal (INP)124.

In operation, the input signal propagates through the cascade of variable delay circuit606and half H-bridge110and, ideally, the total delay through the variable delay circuit606and the half H-bridge110is substantially equal to the reference delay through the reference delay circuit608. PFD610compares the edges of the output signal (OUTP)134at the output of half H-bridge110to the edges of the signal from the reference delay circuit608, and provides a phase error signal to loop filter612. Loop filter612generates an adjustment signal to adjust variable delay circuit606to control the delay of the transitions within the input signal, which are subsequently provided to half H-bridge110. PFD610and loop filter612cooperate to adjust the variable delay of variable delay circuit606until the total propagation delay matches the delay provided by reference delay circuit608, without substantially altering the data rate (or frame rate) of the signal.

In one particular embodiment, loop filter612can be a first order filter, such as an integrator, for basic operation. The first order filter may be a lossy integrator or a lossless filter. In other embodiments, loop filter612can be a higher order filter (i.e., second order or higher order) for enhanced in-band attenuation, particularly at low frequencies. Such a higher order filter may be any passive or active filter known in the art. Further, loop filter612may store a history of edge transitions. Loop filter612can be digital or analog. In an embodiment, loop filter612can be digital and can be adapted to provide an analog interpolation that is provided to variable delay circuit606to adjust the variable delay. Such analog interpolation may be used to apply particular variable delays in response to repeated patterns within the input signal, for example.

In the illustrated embodiment, LLL circuit604controls pulse widths by controlling the edge transition position within a PWM frame at the output of the half H-bridge110by controlling the propagation delay of individual edges of the PWM input signal124at the input of the half H-bridge110. In some instances, the propagation delay of rising edges may be significantly different from that of falling edges. Further, propagation delay of negative pulses may be different from that of positive pulses. In such instances, in may be desirable to independently control each of the transitions.

In a particular embodiment, one or more loop filters, such as loop filter612, may be used to store a history of phase errors/edge placement errors for each type of edge. In such an instance, the edge placement errors may be averaged, combined, interpolated, or otherwise processed to produce a variable delay adjustment signal. In one instance, the phase errors of the individual edges may be linearly combined to produce a corrective adjustment for variable delay circuit606. In an embodiment, the circuit may include eight independent loop filters including a first set of four loop filters and a second set of four loop filters. Each loop filter of the first set of four loop filters may be configured to control a delay associated with one of a rising edge transition and a falling edge transition of one of the first and second PWM signals. Each loop filter of the second set of four loop filters may be configured to control a delay associated with one of a rising edge transition and a falling edge transition of inverted and interchanged versions of the first and second PWM signals. Depending on the implementation, the control signal provided by loop filter612to variable delay circuit606may be based on a weighted summation of the phase errors, an average, or other factors.

In the illustrated embodiment, one or more of reference delay circuit606, reference delay608, PFD610, and loop filter612can be implemented as digital components. For example, reference delay608can be formed using a plurality of inverters. Reference delay circuit606can be formed using a series of gated inverters, which can be selectively bypassed to produce a desired delay.

It should be understood that the output signal134has substantially the same pulse widths as input signal124, with a fixed propagation delay (i.e., timing offset). However, output signal134and input signal124have substantially the same frequency, data rate, frame rate, and so on. While the amplitude of the output signal134may vary from that of the input signal124, the pulse widths and other characteristics of the signals are substantially the same.

In the illustrated embodiment, LLL circuit604is configured to provide edge adjustments for rising edges of an input signal, such as a positive PWM signal of a differential signal pair. However, the loop filter612, PFD610, variable delay circuit606, and reference delay circuit608may be duplicated with the addition of some inverters and a slicer to provide edge transition adjustments for falling edges of the input signal. Further, the circuit may be duplicated to provide edge adjustments for rising and falling edges of a second input signal, such as the negative PWM signal of the differential signal pair. An example of a circuit configured to independently control output edge transitions for rising and falling edges of two input signals is described below with respect toFIG. 7.

FIG. 7is a block diagram of a circuit700including LLL circuitry704and734for independently adjusting propagation delays for both rising and falling edges of input signals. LLL circuitry704and734includes four independent feedback loops701,703,731, and733configured to cancel the load current dependent propagation delay of the H-bridge102(represented by half H-bridges110and112). A first LLL circuit704includes first and second feedback loops701and703for adjusting propagation delays of rising and falling edge transitions of first input signal124. A second LLL circuit734includes third and fourth feedback loops731and733for adjusting propagation delays of rising and falling edge transitions of second input signal126. While the first and second LLL circuits704and734are depicted as separate circuits, it should be understood that, at least in some embodiments, the circuits704and734represent first and second signal processing portions of a single LLL circuit.

First feedback loop701includes a variable delay circuit706, a reference delay circuit708, a slicer710, a phase/frequency detector (PFD)712, a charge pump714, and a capacitor716. The charge pump714and capacitor716represent loop filter612inFIG. 6. Second feedback loop703includes a slicer710, a variable delay circuit718, a reference delay circuit720, a PFD722, a charge pump726, a capacitor730, and inverters724and728. Variable delay circuit706includes a delay input connected to input104for receiving input signal (INP)124, a delay control input connected to PFD712through charge pump714and to ground through capacitor716, and a delay output connected to half H-bridge110. Reference delay circuit708includes a reference input connected to pin104for receiving input signal (INP)124and a reference output connected to an input of PFD712. Slicer710includes an input connected to an output of half H-bridge110for receiving output signal (OUTP)134, a second input for receiving a voltage signal (which may be a reference voltage that is approximately half of a peak-to-peak voltage swing between a first logic level and a second logic level of the output signal (OUTP)134(i.e., VPP/2), and an output connected to a second input of PFD712. PFD712detects phase differences between transitions from the reference-delayed version of input signal124from reference delay circuit708and the total-propagation-delayed version of input signal124represented by output signal (OUTP)134received from slicer710. PFD712communicates phase error data to charge pump714, which produces an output signal that controls the variable delay of variable delay circuit706to adjust rising edge transition timing for a next rising edge within input signal (INP)124.

Second feedback loop703includes a slicer710, a variable delay circuit718, a reference delay circuit720, a PFD722, a charge pump726, a capacitor730, and inverters724and728. Second feedback loop703operates in the same manner as first feedback loop701, except that the input signal (INP)124is inverted by inverter728and the sliced version of the output signal from slicer710is inverted by inverter724. Thus, second feedback loop703operates on the falling edge transitions within input signal (INP)104and variably delays falling edge transitions from input signal (INP)124and provides them to half H-bridge110.

Third feedback loop731includes a variable delay circuit736, a reference delay circuit738, a slicer740, a PFD742, a charge pump744, and a capacitor746. Fourth feedback loop733includes a variable delay circuit748, a reference delay circuit750, a PFD circuit752, a charge pump756, slicer740, a capacitor760, and inverters754and758. Third and fourth feedback loops731and733operate in the same manner as first and second feedback loops701and703, except that the third and fourth feedback loops731and733operate on the second input signal (INN)126received from pin106and provide the variably delayed version of the second input signal (INN)126to half H-bridge112. Further, third and fourth feedback loops731and733adjust the variable delays of variable delay circuits736and748based on the output signal (OUTN)136.

In operation, feedback loops701and731are adapted to adjust timing of edge transitions for the rising edge transitions of the positive input (INP) signal and the negative input signal (INN), respectively. Feedback loops703and733are adapted to adjust timing of edge transitions for the falling edge transitions of the positive input (INP) and the negative input (INN) signal, respectively. Feedback loops701,703,731, and733are independent of one another and cooperate to cancel the load current dependent propagation delay of the H-bridge circuit (represented by half H-bridges110and112).

In the illustrated embodiment ofFIG. 7, it is assumed that variable delay circuits706,718,736, and748; reference delay circuits708,720,738, and750; and PFD circuits712,722,742, and752are configured to respond to rising edge transitions. Accordingly, inverters724,728,754, and758are included to capture the effect of the falling edge transitions.

In a particular example, differential input signals are received, such as differentially modulated PWM signals, including a first signal at positive input (INP)104and a second signal at negative input (INN)106. The first signal is provided to variable delay circuit706and to reference delay circuit708within first feedback loop701and to variable delay circuit718and reference delay circuit720via inverter728within second feedback loop703. The second signal is provided to variable delay circuit736and reference delay circuit738within third feedback loop731and to variable delay circuit748and reference delay circuit750via inverter758within fourth feedback loop733. Variable delay circuits706and736apply respective variable delays to the rising edge transitions of the first and second input signals and provide the variably delayed signals to the respective half H-bridges110and112, which introduce their own delays, which may be both signal and load current dependent. Variable delay circuits718and748apply respective variable delays to falling edge transitions of the first and second input signals and provide the variably delayed signals to the respective half H-bridges110and112, which introduce their own delays, which may be both signal and load current dependent.

Slicers710and740capture the edge transitions of positive output signal (OUTP)134on a first output terminal and of negative output signal (OUTN)136on a second output terminal, which edge transitions are provided to PFD circuits712and742and which are provided to PFDs722and752through inverters724and754, respectively. Reference delay circuits708and720apply fixed delays to input signal124, and reference delay circuits738and750apply fixed delays to input signal126. The delays applied by reference delay circuits708,720,738, and750may be programmed to be greater than the estimated delay introduced by the circuitry of the H-bridge circuit102.

PFDs712,722,742and752compare the reference delayed edge transitions with the sampled edge transitions from slicers710and740to determine a phase error for each of the transition edges. PFDs712,722,742and752generate phase error signals, which after filtering are provided to variable delay circuits706,718,736, and748, to adjust the variable delay such that the overall delay from inputs104and106to the outputs of half H-bridges110and112are substantially equal to the reference delays provided by reference delay circuits708,720,738, and750. In a particular embodiment, the resulting overall delay through the circuit is substantially constant for rising edges and falling edges, independent of the load current of any load circuitry connected to the H-bridge102.

In the illustrated embodiment, PFDs712,722,742, and752are depicted as phase/frequency detectors; however, other types of phase detectors may be used. Further, it should be understood that, in some embodiments, variable delay circuits706,718,736, and748, reference delay circuits708,720,738, and750, PFDs712,722,742, and752may be implemented as digital components.

While a conventional delay lock loop acquires and typically settles into a relatively static condition, the LLL circuitry704and734continuously tracks propagation delay variation of the H-bridge102and adjusts the variable delay of variable delay circuits706,718,736, and748to cancel out propagation delay variations. Since delay variations of the H-bridge102are signal dependent, the variable delay adjustment control signal from the PFDs712,722,742, and752, after filtering by charge pumps714,726,744, and756and capacitors716,730,746, and760, has distorted signal content, which pre-distorts and effectively cancels the distortion in the output signals (OUTPand OUTN)134and136.

In a particular example, LLL circuitry704and734was used to drive audio signals into a speaker (i.e, the load circuit). In this example, the LLL circuitry704and734reduced total harmonic distortion of the H-bridge102driving audio signals into the speaker from 45 dB to over 70 dB. Depending on the frequency band of interest and depending on the filters used, the LLL circuitry704and734can be used to cancel load current dependent and signal content dependent propagation delays to produce a substantially constant propagation delay from input to output, linearizing the circuit.

In the illustrated embodiment ofFIG. 7, LLL circuitry704and734adjusts timing of edge transitions at the input of the half H-bridges110and112, based on delays measured in the output signals134and136so that the output signals134and136are substantially the same as the inputs signals114and116in terms of data rate, pulse widths, frequency, and so on. Thus, the total propagation delay from inputs104and106to the outputs of half H-bridges110and112remains substantially constant, independent of the content of the input signal and independent of the load current.

In conjunction with the circuits600and700depicted inFIGS. 6 and 7and described above, a latency locked loop circuit is disclosed that uses feedback to substantially eliminate propagation delay variation of a buffer circuit, such as an H-bridge type of driver circuit. The LLL circuitry adjusts a variable delay at an input to the buffer circuit to control a total propagation delay, such that the total propagation delay remains substantially constant, independent of the input signal and the load current. Thus, LLL circuitry can be incorporated into a driver of a buffer circuit to linearize the buffer circuit performance and to reduce total harmonic distortion and prevents the folding of high frequency PWM components into the desired signal band, improviding the overall signal-to-noise-plus-distortion ratio (SNDR).

Although the inventive subject matter has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the invention.