Semiconductor memory device

A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-139001, filed on May 28, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and more particularly to a test function in a multi-bank 2-port memory device.

2. Description of the Related Art

In image processing, for example, a memory requires unbroken, continuous read/write operations and concurrent processing such as bank activation and precharge.

A general 1-port multi-bank memory has one port, which comprises control lines for feeding bank active, bank precharge, read, write, row address and column address signals, and data lines for feeding read data and write data. This configuration allows only one command to enter in an identical cycle. Accordingly, it is not possible to execute read and write operations at the same time.

On the other hand, a 2-port multi-bank memory has two ports each provided with respective bank active, bank precharge, read, write, row address and column address control lines. Therefore, it is possible to feed plural commands in an identical cycle and execute read and write operations at the same time.

As obvious from the above, because the 2-port multi-bank memory can support image processing and so forth by one piece, it is more advantageous in cost and so forth than the 1-port multi-bank memory (Patent Document 1: JP 5-109279A).

The existing test systems (hereinafter referred to as “general memory testers”) owned by the semiconductor memory manufacturers have been produced for the purpose of testing 1-port memories in many cases and are difficult to test 2-port multi-bank memories sufficiently based on the actual specs for the following reasons.

Firstly, the general memory tester can not generate plural different addresses at the same time even when it is required to feed different addresses to 2 ports individually in a test on concurrent read/write operations and so forth.

Secondly, it is only possible to generate identical write data and expected-value data (read data) at the same time.

SUMMARY OF THE INVENTION

In an aspect the present invention provides a semiconductor memory device, comprising: a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

In another aspect the present invention provides a semiconductor memory device, comprising: a memory unit having a first and a second port and including plural banks; and a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports.

In another aspect the present invention provides a semiconductor memory device, comprising: a memory unit having a first and a second port and including plural banks; a bank address register operative to store a bank address fed from external; a bank address conversion circuit operative to convert the bank address fed from external or the bank address stored in the bank address register into a bank address different from these bank addresses and operative to supply the bank address before conversion to one of the first and second ports and supply the bank address after conversion to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments associated with the semiconductor memory device according to the present invention will now be described in detail with reference to the drawings.

First Embodiment

FIG. 1is a block diagram of a semiconductor memory device according to a first embodiment of the present invention.

The semiconductor memory device according to the present embodiment comprises a memory unit1, which has a first and a second port, that is, a port0and a port1, and is divided into plural banks, bank #0, bank #1, bank #2, . . . , bank #n; a data buffer2operative to control data input/output between the memory unit1and the outside via DOUT (xZ); and a port-0control circuit3and a port-1control circuit4, which control the port0and the port1. It also comprises RBS, CBS bank address conversion circuits5,6with input AISEL<0:B> operative to receive a first bank address given from external and generate a second bank address different therefrom and operative to supply the second bank address to either the port-0control circuit3with P0_RBS<0:B>, P0_CBS<0:B>, P0_RA<0:X>, P0_CA<0:Y>, /P0_BACT, /P0_BPRC, /P0_WRITE, /P0_READ, or the port-1control circuit4with P1_RBS<0:B>, P1_CBS<0:B>, P0_RA<0:X>, P1_RA<0:X>, P0_CA<0:Y>, P1_CA<0:Y>, /P1_BACT, /P1_BPRC, /P1_WRITE, /P1_READ; and a decoder7for CBS Conversion Circuit Control for column bank address conversion circuit control operative to control the bank address conversion circuits5,6. It further comprises a write data conversion circuit14operative to convert input data fed from external DIN (xZ) and DISEL and supply the converted input data to the data buffer2via DWR.

Each of the banks in the memory unit1includes plural word lines, and plural bit lines crossing these word lines. There are memory cells connected at the intersections of the word lines and the bit lines.

The data buffer2receives write data DWR given from the write data conversion circuit14and supplies it to the memory unit1. It also receives data output from the memory unit1and provides it as output data DOUT to external. These operations are controlled by the port-0control circuit3or the port-1control circuit4.

The port-0control circuit3is supplied, in general, with a row address P0_RA used to select a word line; a column address P0_CA used to select a bit line; a first row bank address P0_RBS output in sync with the row address P0_RA to select P0_RA activate a bank; a first column bank address P0_CBS output in sync with the column address P0_CA to select a bank and execute a read operation or a write operation; a bank active signal /P0_BACT used to activate a bank (herein and hereinafter the mark “/” means an “L”-active negative logic signal); a bank precharge signal /P0_BPRC used to terminate the operation to the current bank and prepare an operation to another bank; and a write signal /P0_WRITE and a read signal /P0_READ. It controls the port0based on these signals. On the other hand, at the time of testing, the port-0control circuit is supplied with a row bank address P0_RBS′ and a column bank address P0_CBS′ given from the bank address conversion circuits5,6via selection switches8and9in place of the row bank address P0_RES and the column bank address P0_CBS. The selection switches8and9are controlled with a test mode signal TM given from external at the time of testing.

The port-1control circuit4is supplied, similar to the port-0control circuit3, in general, with a row address P1_RA, a column address P1_CA, a row bank address P1_RBS, a column bank address P1_CBS, a bank active signal /P1_BACT, a bank precharge signal /P1_EPRC, and a write signal /P1_WRITE and a read signal /P1_READ. It controls the port1based on these signals. On the other hand, the port-0control circuit is supplied with a row bank address P1_RBS′ and a column bank address P1_CBS′ given from the bank address conversion circuits5,6via selection switches10and11at the time of testing in place of the row bank address P1_RBS and the column bank address P1_CBS. It is also supplied with a row address P0_RA and a column address P0_CA given via selection switches12and13in place of the row address P1_RA and the column address P1_CBS. The selection switches10-13are controlled with the test mode signal TM given from external at the time of testing.

The bank address conversion circuits5,6include a row bank address conversion circuit5and a column address conversion circuit6.

The row bank address conversion circuit5receives the first row bank address P0_RBS given from external and generates a second row bank address P0_RBS2different from the first row bank address P0_RBS. The row bank address conversion circuit5supplies the first row bank address P0_RBS as the row bank address P0_RBS′ or P1_RBS′ via the selection switch8or10to one of the port-0control circuit3and the port-1control circuit4and supplies the second row bank address P0_RBS2to the other.

FIG. 2is a circuit diagram of the row bank address conversion circuit5. The circuit shown in the figure only shows a circuit for one bit in a row bank address and, in practice, such circuits are provided by the number corresponding to the bits in the row bank address.

The row bank address conversion circuit5includes a row bank address conversion unit5a, which receives the first row bank address P0_RBS<0:B> and an inversion bit selection signal AISEL<0:B> and provides the second row bank address P0_RBS2<0:B>, and a selection gate unit5b, which receives the first row bank address P0_RBS<0:B> and the second row bank address P0_RBS2<0:B> and selectively distributes these bank addresses P0_RBS<0:B>, P0_RBS2<0:B> to the selection switches8and10based on a port-0standard signal P0STD. The port-0standard signal P0STD is a signal that defines the port0as the standard when it is “H” and the port1as the standard when it is “L”.

The row bank address conversion unit5aincludes an OR gate G1, which receives the first row bank address P0_RBS<0:B> and the inversion bit selection signal AISEL<0:B>, and an OR gate G2, which receives the inverted signal of the first row bank address P0_RBS<0:B> output from an inverter IV1and the inverted signal of the inversion bit selection signal AISEL output from an inverter IV2. The outputs from these OR gates G1and G2are fed to a NAND gate G3, from which output is inverted through an inverter IV3and provided as the second row bank address P0_RBS2. The inversion bit selection signal AISEL has a value of (B+1) bits including “1” indicative of inversion-intended bits and “0” for others, of (B+1) bits given in the row bank address P0_RBS<0:B>.

The selection gate unit5bincludes four transfer gates TR1-TR4. The transfer gates TR1and TR2select one of the first row bank address P0_RBS<0:B> and the second row bank address P0_RBS2<0:B> fed to respective sources and supply the selected one to the selection switch8as the row bank address P0_RBS′<0:B>. The transfer gates TR3and TR4select one of the first row bank address P0_RBS<0:B> and the second row bank address P0_RBS2<0:B> fed to respective sources and supply the selected one to the selection switch10as the row bank address P1_RBS′<0:B>. The transfer gates TR1and TR4include NMOS transistors and PMOS transistors, of which gates are supplied with the port-0standard signal P0STD and the inverted signal thereof, respectively. The transfer gates TR2and TR3include PMOS transistors and NMOS transistors, of which gates are supplied with the port-0standard signal P0STD and the inverted signal thereof, respectively. When the port-0standard signal P0STD=“L”, this configuration turns the row bank address P0_RBS′<0:B> at the port0and the row bank address P1_RBS′ at the port1to the second rowbank address P0_RBS2<0:B> and the first row bank address P0_RBS<0:B>, respectively. In contrast, when the port-0standard signal P0STD=“H”, it turns the row bank address P0_RES′ at the port0and the row bank address P1_RBS′<0:B> at the port1to the first row bank address P0_RBS<0:B> and the second row bank address P0_RBS2<0:B>, respectively.

Operation of this circuit is described next.

It is assumed herein that the row bank address P0_RBS<0:B> has a value of 3 bits “010” and the inversion bit selection signal AISEL<0:E> has a value of 3 bits “001”.

In this case, as for the bit0, because of P0_RBS<0>=0 and AISEL<0>=1, the outputs from the OR gates G1, G2become “1”, “1”, respectively. Therefore, the NAND gate G3and the inverter IV3turn the output from the row bank address conversion unit5ato “1”. As for the bit1and the bit2, similarly, the outputs from the row bank address conversion unit5abecome “1”, “0”. Therefore, the output from the row bank address conversion unit5aexhibits “011”, which is equal to the row bank address P0_RBS<0:2> except that the 0-th bit is inverted. The output from the row bank address conversion unit5abecomes the second row bank address P0_RBS2<0:2>.

In the case of the port-0standard signal P0STD=“H”, the transfer gates TR1and TR4are turned on and the transfer gates TR2and TR3are turned off. Therefore, the row bank address P0_RBS′<0:B> becomes “010” that is equal to the first row bank address P0_RBS<0:B>, and the row bank address P1_RBS′<0:B> becomes “011” that is equal to the second row bank address P0_RBS2<0:B>. In contrast, in the case of the port-0standard signal P0STD=“L”, the transfer gates TR1and TR4are turned off and the transfer gates TR2and TR3are turned on. Therefore, the row bank address P0_RBS′ becomes “011” that is equal to the second row bank address P0_RBS2<0:B>, and the row bank address P1_RBS′<0:B> becomes “010” that is equal to the first row bank address P0_RBS<0:B>.

The column bank address conversion circuit6receives the first column bank address P0_CBS<0:B> given from external and generates a second column bank address P0_CBS2<0:B> different from the first column bank address P0_CBS<0:B>. Further, the column bank address conversion circuit6supplies the column bank address P0_CBS<0: B> as the column bank address P0_CBS′<0:B> or P1_CBS′<0:B> via the selection switch9or11to one of the port-0control circuit3and the port-1control circuit4and supplies the second column bank address P0_CBS2<0:B> to the other.

FIG. 3is a circuit diagram of the column bank address conversion circuit6. The circuit shown in the figure only shows a circuit for one bit in a column bank address and, in practice, such circuits are provided by the number corresponding to the bits in the column bank address.

The column bank address conversion circuit6includes a column bank address conversion unit6a, which receives the first column bank address P0_CBS<0:B> and an inversion bit selection signal AISEL<0:B> and provides the second column bank address P0_CBS2<0:B>, and a selection gate unit6b, which receives the first column bank address P0_CBS<0:B> and the second column bank address P0_CBS2<0:B> and selectively distributes these column bank addresses P0_CBS<0:B>, P0_CBS2<0:B> to the selection switches9and11based on a port-0column bank address selection signal CBSSEL0and a port-1column bank address selection signal CBSSEL1given from the decoder7for column bank address conversion circuit control.

The column bank address conversion unit6aincludes an OR gate G4, which receives the first column bank address P0_CBS<0:B> and the inversion bit selection signal AISEL<0:B>, and an OR gate G5, which receives the inverted signal of the column bank address P0_CBS<0:B> output from an inverter IV5and the inverted signal of the inversion bit selection signal AISEL output from an inverter IV6. The outputs from these OR gates G4and G5are fed to a NAND gate G6, from which output is inverted through an inverter IV7and provided as the second column bank address P0_CBS2<0:B>. The inversion bit selection signal AISEL has a value of (B+1) bits including “1” indicative of inversion-intended bits and “0” for others, of (B+1) bits given in the column bank address POCBS<0:B>.

The selection gate unit6bincludes four transfer gates TR5-TR8. The transfer gates TR5and TR6select one of the first column bank address P0_CBS<0:B> and the second column bank address P0_CBS2<0:B> fed to respective sources and supply the selected one to the selection switch9as the column bank address P0_CBS′<0:B>. The transfer gates TR3and TR4select one of the first column bank address P0_CBS<0:B> and the second column bank address P0_CBS2<0:B> fed to respective sources and supply the selected one to the selection switch11as the column bank address P1_CBS′<0:B>. The transfer gate TR5includes an NMOS transistor and a PMOS transistor, of which gates are supplied with the port-0 column bank address selection signal CBSSEL0and the inverted signal thereof, respectively. On the other hand, the transfer gate TR6includes a PMOS transistor and an NMOS transistor, of which gates are supplied with the port-0column bank address selection signal CBSSEL0and the inverted signal thereof, respectively. In addition, the transfer gate TR7includes an NMOS transistor and a PMOS transistor, of which gates are supplied with the port-1column bank address selection signal CBSSEL1and the inverted signal of IV9, respectively. On the other hand, the transfer gate TR8includes an NMOS transistor and a PMOS transistor, of which gates are supplied with the port-1column bank address selection signal CBSSEL1and the inverted signal of IV9, respectively. When the port-0column bank address selection signal CBSSEL0=“L” and the port-1column bank address selection signal CBSSEL1=“H”, this configuration turns the column bank addresses P0_CBS′<0:B> and P1_CBS′<0:B> to the second column bank address P0_CBS2<0:B> and the first column bank address P0_CBS<0:B>, respectively. In contrast, when the port-0column bank address selection signal CBSSEL0=“H” and the port-1column bank address selection signal CBSSEL1=“L”, it turns the column bank addresses P0_CBS′<0:B> and P1_CBS′<0:B> to the column bank address P0_CBS<0:B> and the second column bank address P0_CBS2<0:B>, respectively.

Operation of this circuit is described next.

It is assumed herein that the column bank address P0_CBS<0:B> has a value of 3 bits “010” and the inversion bit selection signal AISEL<0:B> has a value of 3 bits “001”.

In this case, as for the bit0, because of P0_CBS<0>=0 and AISEL<0>=0, the outputs from the OR gates G4, G5become “1”, “1”, respectively. Therefore, the NAND gate G6and the inverter IV7turn the output from the column bank address conversion unit6ato “1”. As for the bit1and the bit2, similarly, the outputs from the column bank address conversion unit6abecome “1”, “0”. Therefore, the output from the column bank address conversion unit6aexhibits “001”, which is equal to the column bank address P0_CBS<0:2> except that the 0-th bit is inverted. The output from the column bank address conversion unit6abecomes the second column bank address P0_CBS2<0:B>.

In the case of the port-0column bank address selection signal CBSSEL0=“H” and the port-1 column bank address selection signal CBSSEL1=“L”, the transfer gates TR5and TR6are turned on and the transfer gates TR6and TR7are turned off. Therefore, the column bank address P0_CBS′<0:B> becomes “010” that is equal to the first column bank address P0_CBS<0:B>, and the column bank address P1_CBS′<0:B> becomes “011” that is equal to the second column bank address P0_CBS2<0:B>. In contrast, in the case of the port-0 column bank address selection signal CBSSEL0=“L” and the port-1 column bank address selection signal CBSSEL1=“H”, the transfer gates TR5and TR8are turned off and the transfer gates TR6and TR7are turned on. Therefore, the column bank address P0_CBS′<0:B> becomes “011” that is equal to the second column bank address P0_CBS2<0:B>, and the column bank address P1_CBS′<0:B> becomes “010” that is equal to the first column bank address P0_RBS<0:B>.

The decoder7for column bank address conversion circuit control is a circuit for determining a port for read operation-use as the standard, that is, a port supplied with the first column bank address P0_CBS<0: B> given from external. It receives write signals /P0_WRITE, /P1_WRITE and read signals /P0_READ, /P1_READ and controls the column bank address conversion circuit6based on these signals.

FIG. 4is a circuit diagram of the decoder7for column bank address conversion circuit control.

The decoder7for column bank address conversion circuit control includes a NOR gate G7operative to receive the read signal /P1_READ via IV23and the write signal /P0_WRITE via IV20; a NAND gate G8operative to receive the output from the NOR gate G7and the read signal /P0_READ via IV21; and a NOR gate G9operative to receive the port-0standard signal P0STD and the output from the NAND gate G8. The output from the NOR gate G9is transferred as the port-1column bank address selection signal CBSSEL1to the column bank address conversion circuit6. It also includes a NOR gate G10operative to receive the read signal /P0_READ and the write signal /P1_WRITE via IV22; a NAND gate G11operative to receive the output from the NOR gate G10and the read signal /P1_READ; and a NOR gate G12operative to receive the output from the NAND gate G11and the inverted signal of the port-0standard signal P0STD output from an inverter IV10. The output from the NOR gate G12is transferred as the port-0column bank address selection signal CBSSEL0to the column bank address conversion circuit6.

Operation of this circuit is described next.

The following description is given to the case where the port0is determined as the standard and the port0is used in read operation and the port1in write operation.

In this case, the input signals are set as follows: the port-0standard signal P0STD=“H”, the write signal /P0_WRITE=“H” at the port0, the read signal /P0_READ=“L” at the port0, the write signal /P1_WRITE=“L” at the port1, and the read signal /P1_READ=“H” at the port1. Therefore, the output from the NOR gate G7is “L” and the output from the NAND gate G8is “H”. As a result, the output from the NOR gate G9, that is, the port-1column bank address selection signal CBSSEL1becomes “L”. On the other hand, the output from the NOR gate G10is “H” and the output from the NAND gate G11is “L”. As a result, the output from the NOR gate G12, that is, the port-0column bank address selection signal CBSSEL0becomes “H”. Finally, the column bank address P0_CBS′ at the port0becomes the first column bank address P0_CBS, and the column bank address P1_CBS′ at the port1becomes the second column bank address P0_CBS2.

The following description is given to the case where the port1is determined as the standard and the port0is used in write operation and the port1in read operation.

In this case, the input signals are set as follows: the port-0standard signal P0STD=“L”, the write signal /P0_WRITE=“L” at the port0, the read signal /P0_READ=“H” at the port0, the write signal /P1—WRITE=“H” at the port1, and the read signal /P1—READ=“L” at the port1. Therefore, the output from the NOR gate G7is “H” and the output from the NAND gate G8is “L”. As a result, the output from the NOR gate G9, that is, the port-1column bank address selection signal CBSSEL1becomes “H”. On the other hand, the output from the NOR gate G10is “L” and the output from the NAND gate G11is “H”. As a result, the output from the NOR gate G12, that is, the port-0column bank address selection signal CBSSEL0becomes “L”. Finally, the column bank address P0_CBS′ at the port0becomes the second column bank address P0_CBS2, and the column bank address P1_CBS′ at the port1becomes the first column bank address P0_CBS.

As can be found from the above, the column bank address conversion circuit6is controlled such that the first column bank address P0_CBS fed from external is supplied to the column bank address P0_CBS′ or P1_CBS′ of the port for read operation-use of two ports, and the second column bank address P0_CBS2is supplied to the port for write operation-use for the following reason. If the column bank address P0_CBS′ or P1_CBS′ for read operation-use is set at the second column bank address P0_CBS2, the comparison value given from the memory tester is compared with the data read with the second column bank address P0_CBS2, and thus the memory tester can not carry out a correct test.

FIG. 5shows an example of the correspondence table of bank addresses at the port0and the port1in accordance with the row bank address (RBS) conversion circuit5and the column bank address (CBS) conversion circuit6. Exemplary banks included are bank #0, bank #1, bank #2, bank #3, bank #4, bank #5, bank #6, and bank #7.

When the inversion bit selection signal AISEL<2:0> is “001” shown in the right hand three columns as AISEL<2>, AISEL<1>, and AISEL<0>, and “010” is given as the row bank address RA_RBS from external, the row bank address conversion circuit5and the column bank address conversion circuit6generate “011” as the second bank address with the first bit inverted, which is transferred to the port-1control circuit4. The states of RBS and CBS for port0and port1are shown for the respective bits RBS<2> RBS<1> RBS<0> CBS<2> CBS<1> and CBS<0>. The bit readings for each of the banks are shown to the left as 000, 001, 010, 011, 100, 101, 110, 111. The solid dots show the position on the table for the respective banks of the bit combination shown in row7of the table as read from the top. As a result, adjacent banks #2and #3are activated to permit concurrent read/write operations to these banks. Setting the inversion bit selection signal AISEL in this way makes it possible to carry out a test on malfunctions due to the interference between adjacent banks and so forth. Further, the inversion bit selection signal AISEL can be set arbitrarily and therefore operation tests with combinations of all banks can be made flexibly.

The write data conversion circuit14in the present embodiment is operative to invert bits in the input data DIN given from external and supply the inverted data to the data buffer2.

FIG. 6is a circuit diagram of the write data conversion circuit14.

The write data conversion circuit14comprises an inverter IV11operative to receive the input data DIN (xZ), and a data selection unit14aoperative to selectively provide the input data DIN (xZ) and the output from the inverter IV11as the write data DWR to the data buffer2.

The data selection unit14aincludes a transfer gate TR9operative to receive the input data DIN (xZ) at the source and provide the input data from the drain to the data buffer2, and a transfer gate TR10operative to receive the inverted data of the input data DIN (xZ) output from the inverter IV11at the source and provide the inverted input data from the drain to the data buffer2. An NMOS transistor in the transfer gate TR9and a PMOS transistor in the transfer gate TR10have respective gates, which are supplied with a data inversion selection signal DISEL. On the other hand, a PMOS transistor in the transfer gate TR9and an NMOS transistor in the transfer gate TR10have respective gates, which are supplied with the inverted signal of the data inversion selection signal DISEL output from an inverter IV12.

Operation of this circuit is described next.

When the data inversion selection signal DISEL=“L”, the transfer gates TR9and TR10are turned on and off, respectively. Therefore, the input data DIN (xZ) is provided to the data buffer2as it is. In contrast, when the data inversion selection signal DISEL=“H”, the transfer gates TR9and TR10are turned off and on, respectively. Therefore, the inverted data of the input data DIN (xZ) output from the inverter IV16is provided to the data buffer2.

The write data conversion circuit14makes it possible to generate output data DOUT different from the input data DIN (xZ). Namely, a general memory tester is restricted such that it can supply only one data at a time and accordingly can not make the input data DIN (xZ) different the output data DOUT (expected-value data). The inversion of the input data DIN (xZ), however, makes it possible.

In particular, the bit inversion of the input data DIN (xZ) can make the input data DIN (xZ) opposite in level polarity to the output data DOUT, thereby carrying out a test on the interference such as data leakage between both lines for transferring the input data DIN (xZ) and the output data DOUT.

Subsequently, a test on concurrent read/write operations according to the present embodiment is described.

FIG. 7is a timing chart showing times T0-T15on clock line CLK of concurrent read/write operations in the present embodiment when the read operation is executed from the port to the bank #1and the write operation is executed from the port1to the bank #2at the same time.

First, the row bank address P0_RBS and the row address P0_RA at the port0are specified with the row address RAa of the bank #1and then the bank active signal /POBACT is made “L” to activate the bank #1(T0).

Next, the column bank address P0_CBS and the column address P0_CA are specified with the column address CAa of the bank #1and then the read signal /P0_READ is made “L” to select the bank #1(T2-T10), and DM is made “L”, and, after a certain time elapsed, data Aa is read out of the bank #1as the output data DOUT (T6-T13).

On the other hand, as for the port1, similarly, the column bank address P1_RBS and the row address P0_RA are specified with the row address RAb of the bank #2and the row address RAa and then the bank active signal /P1_BACT is made “L” to activate the bank #2(T0).

Next, the column bank address P1_CBS and the column address P1_CA are specified with the column address CAb of the bank #2and then the write signal /P1_WRITE is made “L” to select the bank #2and write data Ab in the bank #2as the input data DIN (T2-T10).

Next, a test on concurrent read/write operations shown inFIG. 7in the present embodiment is described. A semiconductor memory device of which memory unit1is a 2-port 4-bank memory is herein described by way of example.

FIG. 8is a conceptual view of the test on concurrent read/write operations in the present embodiment.

Previously, 0 is written from the port0or the port1in all memory cells in 4 banks prior to the operation test on concurrent read/write operations (S1) as shown in (1).

Next, the inversion bit selection signal AISEL<0>=“H” is set to “H” and the input data inversion selection signal DISEL=“H” is set to “H”, and POSTD=H is set to “H” (S2).

Then, while 0 read is executed from the port0to a bank #0, data write is executed from the port1to a bank #1(S3) as shown at (2).

Finally, while data read is executed from the port1to a bank #2, data write is executed from the port0to a bank #3(S4) as shown at (3).

FIG. 9is a timing chart showing times T20-T31on clock line CLK at the time (S3) of an operation test on the read operation from the port0to the bank #0and the write operation from the port1to the bank #1.

First, the memory tester ADD (Port0) (Tester→Memory) designates the row bank address RA#0of the bank #0and gives a bank active instruction BACT#0to the port0shown on line CMD (Port0) and a bank active instruction BACT#1to the port1shown online CMD (Port1). At this time, the row bank address conversion circuit5generates a second row bank address RA#1based on the first row bank address RA#0given from the memory tester. Thereafter, it provides the first row bank address RA#0to the port0for standard-use and the second row bank address RA#1to the other port1. Thus, the bank #0and the bank #1are selected and activated (T20) at ADD (Port0) (Inside Memory) and ADD (Port1) (Inside Memory), respectively.

Subsequently, the memory tester designates the column bank address CA#0of the bank #0, and gives a read instruction READ#0to the port0and a write instruction WRITE#1to the port1. In addition, it sets write data WD#1and an Expected Value Setting CD#0having the same value as the write data WD#1from DIN (Tester-Memory) (T21−). At this time, the column bank address conversion circuit6generates a second column bank address CA#1based on the first column bank address CA#0given from the memory tester. Thereafter, it provides the first column bank address CA#0to the port0for read operation-use and the second column bank address CA#1to the other port1. The input data WD#1is bit-inverted at the write data conversion circuit14and then transferred to the data buffer2(/WD#1). Thus, the write data /WD#1is written in the bank #1at DWR (Inside Memory). On the other hand, when a certain time elapsed after the issue of the read instruction READ#0(a read latency RL=3 inFIG. 9), the output data RD#0read out of the bank #0is compared with the expected value CD#0(T23−).

After completion of the concurrent read/write operations as above, bank precharge instructions BPRC#0and BPRC#1are given to the port0and the port1to bring the bank #0and the bank #1into the idle state (T31).

FIG. 10is a timing chart at times T40-T51on clock line CLK at the time (S4) of an operation test on the write operation at the port0to the bank #3and the read operation from the port1to the bank #2. The left hand indications correspond with those inFIG. 9.

First, the memory tester designates the row bank address RA#3of the bank #3and gives a bank active instruction BACT#3to the port0and a bank active instruction BACT#2to the port1. At this time, the row bank address conversion circuit5generates a second row bank address RA#2based on the first row bank address RA#3given from the memory tester. Thereafter, it provides the first row bank address RA#3to the port0for standard-use and the second row bank address RA#2to the other port1. Thus, the bank #2and the bank #3are selected and activated (T40).

Subsequently, the memory tester designates the column bank address CA#3of the bank #3, and gives a write instruction WRITE#3to the port0and a read instruction READ#2to the port1. In addition, it sets write data WD#3and an expected value CD#2having the same value as the write data WD#3(T41−). At this time, the column bank address conversion circuit6generates a second column bank address #2based on the first column bank address CA#3given from the memory tester. Thereafter, it provides the first column bank address CA#3to the port1for read operation-use and the second column bank address CA#2to the other port0. The write data WD#3is bit-inverted at the write data conversion circuit14and then transferred to the data buf fer2(/WD#3). Thus, the write data /WD#3is written in the bank #3. On the other hand, when a certain time elapsed after the issue of the read instruction READ#2(a read latency RL=3 inFIG. 10), the output data RD#2read out of the bank #2is compared with the expected value CD#2(T43−).

After completion of the concurrent read/write operations as above, bank precharge instructions BPRC#3and BPRC#2are given to the port0and the port1to bring the bank #3and the bank #2into the idle state (T51).

A general memory tester is not possible to specify two ports with different addresses at the same time and generate different write data and expected-value data at the same time. Therefore, in the case of the semiconductor memory device according to the prior art, a sufficient functional test can not be made with the general memory tester as a problem.

With this regard, in accordance with the present embodiment, it is made possible to carry out a test on concurrent read/write operations to different banks even with the use of the general memory tester.

In accordance with the present embodiment, the row address and the column address fed to the port-1control circuit4at the time of testing are always the row address P0_RA and the column address P0_CA fed from external, which are same as the row address and the column address given to the port-1control circuit3. Even in such the case, however, it is possible to carry out a test on concurrent read/write operations to different banks using 2 ports.

Specifying the ports0and1with different row and column addresses can be supported by such circuits that are similar to the row bank address conversion circuit5and the column bank address conversion circuit6and separately provided to the row address and the column address.

Second Embodiment

FIG. 11is a block diagram of a semiconductor memory device according to a second embodiment of the present invention. The indications inFIG. 11similar to those shown inFIG. 1and not repeated here.

The present embodiment further comprises, in addition to the semiconductor memory device according to the first embodiment, a row address register115operative to hold the contents of the third row bank address P0_RBS<0:B> and the row address P0_RA<0:X>, and selection switches116and117operative to transfer the row address P0_RA<0:X> (hereinafter referred to as P0_RA1) held in the row address register115and the row addresses P0_RA<0:X> and P1_RA<0:X> alternatively to the port-0control circuit3and the port-1control circuit4.

The row address register115receives the row bank address P0_RBS<0:B> and the row address P0_RA<0:X>. In addition, it receives a load act signal LDRACT that gives an instruction for holding the first row bank address P0_RBS<0:B> and the row address P0_RA<0:X>, currently given, and a control signal WROW that gives an instruction for transferring the third row bank address P0_RBS1and the row address P0_RA1, currently held, to the row bank address conversion circuit105and the selection switches116,117. These input signals are processed in a control circuit contained in the row address register.

The selection switches116and117are controlled by the control circuit in the row address register115. These switches select the row addresses P0_RA<0:X> and P1_RA<0:X> and transfer them to the port-0control circuit3and the port-1control circuit4. When the row address register115receives the control signal WROW, the control circuit in the row address register115switches the selection switches116and117to supply the row address P0_RA1to the port-0control circuit3and the port-1control circuit4.

Operation of the present embodiment is described. The following description is given to the case where the third and fourth banks are further activated while two banks are subjected to concurrent read/write operations.

FIG. 12is a timing chart from times T100-T123on clock line CLK of concurrent read/write/bank active operations in the present embodiment. Indications similar to those inFIG. 7are not repeated here.

First, at the port0, the bank active signal /P0_BACT is turned “L” and the row address RAa is given, thereby activating the first bank, that is, the bank a (T100). Next, the read signal /P0_READ is turned “L” and the column address CAa is fed (T102-T108). When a certain period of time elapsed (a read latency=3CLK inFIG. 12), data Aa is provided as the output data DOUT from the first bank #0(T106-T121).

On the other hand, at the port1, the bank active signal /P1_BACT is turned “L” and the row address RAb is given, thereby activating the second bank, that is, the bank #1(T100). Next, the write signal /P1_WRITE is turned “L” and the column address CAb is given, thereby writing the input data DIN, that is, data Ab in the bank #1(1102-T118).

After completion of the concurrent read/write operations to the bank #0and the bank #1, a write operation to a third bank, that is, a bank #2and a read operation to a fourth bank, that is, a bank #3are started continuously (T119, T122). For that purpose, the bank #2and the bank #3are activated during the read operation to the bank #0and the write operation to the bank #1(T116).

In the series of the above operations, the most problematic matter is the bank active operation to the bank #2and the bank #3at the time of the read operation to the bank a and the write operation to the bank #1executed concurrently (T116), which corresponds to the worst case in a 2-port multi-bank memory when the supply voltage lowers.

FIG. 13is a timing chart from times T140-1161of the signals from the memory tester and the signals inside the memory in the present embodiment at the time of a test made on the concurrent read/write/bank active operations shown inFIG. 12. Similar indication fromFIGS. 7 and 12are not repeated here.

First, prior to the concurrent read/write operations to the first and second banks, that is, the bank #0and the bank #1, the memory tester previously designates the row bank address RBSc of the third bank, that is, the bank #2and the row address RAc0, and gives a load act instruction LDACT (T104), thereby holding the row bank address RBSc of the bank #2and the row address RAc0in the row address register115.

Next, the memory tester designates the row bank address RBSa and the row address RAa0, and gives a bank active instruction BACT to the port0and the port1. At this time, the row bank address RBSb of the second row bank, that is, the bank #1is generated based on the row bank address RBSa fed to the row bank address conversion circuit105inside the memory, thereby making the bank #0and the bank #1active (T141).

Next, a read instruction READ and a write instruction WRITE are given to the port0and the port1(T142), thereby starting a write operation to the bank #1(T142-1157). When a certain period of time elapsed, a read operation to the bank #0is started (T145, not shown inFIG. 13, through T160). In this example, pieces of input data /Db0-/Dbn to the bank #1are derived from the input data Db0-Dbn given from the memory tester and bit-inverted at the write data conversion circuit14inside the memory.

During the concurrent read/write operations to the bank #0and the bank #1, the memory tester issues the control instruction WROW. In this case, the third row bank address P0_RBSc and the row address P0_RAc0held in the row address register115, as well as a bank address RBSd of a fourth bank, that is, a bank #3, generated based on the given bank address RBSc, and a row address RAd0identical to the row address RAc0are given to the port0and the port1to make the bank #2and the bank #3active (T155). Thus, immediately after completion of the read operation to the bank #0and the write operation to the bank #1(T160, T157), a write operation to the bank #2and a read operation to the bank #3can be started (T158, T160).

In accordance with the second embodiment, it is possible to provide a semiconductor memory device such as a 2-port multi-bank memory sufficiently capable of an operation test with the use of a general memory tester even in the worst case when the supply voltage lowers.

Third Embodiment

A semiconductor memory device according to a third embodiment includes plural such row address registers115, one of which is contained in the semiconductor memory device according to the second embodiment.

This configuration makes it possible to support an operation test on concurrent read/write/bank active operations, which include the concurrent read/write operations to the first and second banks, that is, the bank #0and the bank #1(T203-T218), and additionally activating the third and fourth banks, that is, the bank #2and the bank #3(T216), and further activating a fifth and a sixth bank, that is, a bank #4and a bank #5(T217) as shown inFIG. 14.

In the case of carrying out a test on the operation as shown inFIG. 14from times T200-T223, the semiconductor memory device according to the second embodiment may be given one additional row address register115′ and thus provided with two row address registers in total. Similar indications from previous figures are not repeated here.

First, previously, the row address register115holds the row address RAc of the third bank, that is, the bank #2and the newly added row address register115′ holds the row address RAe of the fifth bank, that is, the bank #4.

Next, the bank #0and the bank #1are activated (T200) and the concurrent read/write operations to the bank #0and the bank #1are executed (T203-T218). During the concurrent read/write operations, when the control signal WROW is given to the row address register115, the row address RAc of the bank #2held in the row address register115is transferred to the row bank address conversion circuit105. On reception of this, the row bank address conversion circuit105generates the row bank address RAd of the fourth bank, that is, the bank #3, and transfers it to the port-0control circuit3and the port-1control circuit4. At this time, the bank active signals /P0_BACT and /P1_BACT are activated at “L”, thereby activating the bank #2and the bank #3(T216). Subsequently, when the control signal WROW is given to the row address register115′, the row address RAe of the bank #4held in the row address register115′ is transferred to the row bank address conversion circuit105. On reception of this, the row bank address conversion circuit105generates the row bank address RAf of the sixth bank, that is, the bank #5, and transfers it to the port-0control circuit3and the port-1control circuit4. At this time, the bank active signals /P0_BACT and /P1_BACT are activated at “L”, thereby activating the bank #4and the bank #5(T217).

In accordance with the present embodiment, it is possible to hold one different row bank address in one row address register and accordingly activate much more banks than the second embodiment even during concurrent read/write operations.

The row address register115in the semiconductor memory device according to the second embodiment may include an update means operative to count up the held row bank address every time of the input of the control signal WROW to exert the similar effect.