Amplifying solid-state image pickup device

There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.

This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2004-049482 filed in Japan on Feb. 25, 2004, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to an amplifying solid-state image pickup device.

Conventionally, there has been proposed an amplifying solid-state image pickup device which has a pixel section having an amplification function and a scanning circuit disposed around the pixel section, where pixel data is read from the pixel section by the scanning circuit. In particular, there has been known an APS (Active Pixel Sensor) type image sensor formed of CMOSs (Complementary Metal Oxide Semiconductor) which are advantageous for integration of the pixel part with peripheral drive circuit and signal processing circuit.

For the APS type image sensor, there is a need for forming a photoelectric conversion part, an amplification part, and a pixel select part and a reset part normally within one pixel. Therefore, in the APS type image sensor, normally, three to four MOS transistors (Tr) are used in addition to the photoelectric conversion part formed of photodiodes (PD).

FIG. 8shows a construction of an APS type image sensor which employs one photodiode (PD) and four MOS transistors (Tr) to make up a PD+4Tr system. This PD+4Tr system APS image sensor is disclosed in, for example, Reference “I. Inoue et al., IEDM Tech. Digest, pp. 883–886 (1999).”

The APS type image sensor of the PD+4Tr system shown inFIG. 8is made up of a photodiode201as a “PD” and, as the “4Tr,” a transfer transistor202for transferring signal charge stored in the photodiode201, a reset transistor231, an amplification transistor232and a pixel select transistor233. In this case, assuming that the photodiode201is given as buried type and signal charge transfer from the photodiode201is perfect, it is known that quite great noise reduction can be achieved and that high-quality images can be obtained.

A drive pulse for the transfer transistor202is represented by φT, a drive pulse for the reset transistor231is represented by φRR, and a drive pulse for the pixel select transistor233is represented by φS. Also, a vertical signal line235is grounded via a constant-current load transistor234to which a drive pulse φLis applied, where an output signal VSis obtained. In addition, VDDrepresents a power supply voltage (constant voltage).

For the amplifying solid-state image pickup device, it is useful to obtain a high resolution by reading out all the pixels independently of one another in the still picture mode and to enhance a read frame speed or sensitivity despite sacrificing the resolution by performing addition among pixels in the moving picture mode.

However, in the case of the amplifying solid-state image pickup device shown inFIG. 8, there would arise a problem as follows. That is, because signal charge is converted and amplified into a voltage signal and then read out from pixel to pixel, the addition operation among pixels is one to be performed among the read voltage signals. This require analog or digital memory elements in addition to the pixel section for the purpose of the addition operation, resulting in a more complex read circuit construction. Further, this method is poor in the S/N (Signal-to-Noise ratio) improvement effect. The reason of this is as follows.

Here is examined an addition between two pixels P1and P2. Signals at the pixels are assumed as s1and s2, respectively, and noise generated at the photoelectric conversion part is assumed as np1and np2, and noise generated at the in-pixel amplification part is assumed as na1and na2. Since noise np1and np2and noise na1and na2are not mutually correlated but independent of each other, total noise n12is as shown by the following equation (Eq. 1):
n12=√{square root over (()}np12+np22+na12+na22)  (Eq. 1)

A total signal s12is as shown by the following equation (Eq. 2):
s12=s1+s2(Eq. 2)

Assuming a case where noise generated at the photoelectric conversion part is suppressed so that (np1, np2)<<(na1, na2) and where signals P1and P2are of the same and generated noise is also equivalent,
s12=2·s1andn12=√{square root over (2)}·na1,
s12/n12=√{square root over (2)}·(s1/na1)  (Eq. 3)
so that the S/N is improved only to √{square root over (2)} times.

Here is examined a case where the addition operation between pixels is performed before the conversion to voltage and the amplification, and then a signal after the addition is read out.

In this case, the noise after the addition is represented by the following equation (Eq. 4), being smaller than that of (Eq. 1):
n12=√{square root over (()}np12+np22+na12)  (Eq. 4)

On the other hand, since the signal is represented by (Eq. 2) through charge addition, a case is examined in which (np1, np2)<<(na1) and the signals P1and P2are of the same.
Since s12=2·s1and n12=na1,
s12/n12=2·(s1/na1)  (Eq. 5)
so that the S/N is improved to two times. An example of this operation is shown below.

FIG. 9shows an amplifying solid-state image pickup device in which a signal charge storage part208, a reset transistor231, an amplification transistor232and a pixel select transistor233are provided in common to a plurality of photodiodes201and transfer transistors202(see, e.g., JP 09-46596 A).

InFIG. 9, the same symbols as those inFIG. 8represent the same contents as those inFIG. 8.FIG. 9differs fromFIG. 8in that one set of a charge detection part208, a reset transistor231, an amplification transistor232and a pixel select transistor are provided in common to upper-and-lower two pixels. As a result, turning ON simultaneously a drive pulse φT(m, 1) of a transfer transistor202of a pixel (m, 1) and a drive pulse φT(m, 2) of a transistor of a pixel (m, 2) makes it possible to read out added-up signal charge of photodiodes201of the upper-and-lower two pixels (m: natural number).

However, in the construction and operation of the amplifying solid-state image pickup devices shown inFIG. 9, there arise problems as shown below. That is, given that the capacity of the common signal charge storage part208is CFD, a charge-voltage conversion efficiency η at which signal charge Qsig derived from the photodiode201is converted to a voltage signal Vsig is
η=GSF·Vsig/Qsig=GSF/CFD(Eq. 6)
where GSFis the gain of a source follower circuit made up of the amplification transistor232and the constant-current load transistor234, being smaller than 1.

As apparent from Equation 6, the capacity CFDneeds to be reduced in order to enlarge the charge-voltage conversion efficiency η. The capacity CFDof the common signal charge storage part208is a sum of a drain-side junction capacitance of the transfer transistor202and a gate capacitance of the amplification transistor232, both transistors being connected to the signal charge storage part208. Therefore, the drain junction capacitance of the transfer transistors and wiring capacitance increase according as the number of photodiodes and transfer transistors connected to a common signal charge storage part increases, which leads to a problem that the charge-voltage conversion efficiency η decreases.

SUMMARY OF THE INVENTION

The present invention, intended to solve this problem, has an object of providing an amplifying solid-state image pickup device which performs an addition of signal charges in pixels, making it possible to achieve the addition operation without burdening the read circuit, and which is capable of not only enhancing the S/N improvement effect by addition but also keeping the charge-voltage conversion efficiency even with the addition structure.

In order to achieve the above object, according to the present invention, there is provided an amplifying solid-state image pickup device comprising:

a plurality of photoelectric conversion transfer parts which are provided for individual pixels, respectively, and each of which has a photoelectric conversion element and at least one transfer transistor for transferring signal charge of the photoelectric conversion element, wherein

the plurality of photoelectric conversion transfer parts are divided into a plurality of photoelectric conversion transfer part groups each composed of at least two of the photoelectric conversion transfer parts, respectively;

a plurality of switched capacitor amplification parts which are provided for the individual photoelectric conversion transfer part groups, respectively, of which input side of each is connected to an output side of each transfer transistor of the photoelectric conversion transfer parts and of which output side of each is connected to a signal line; and

a control part for selecting a plurality of photoelectric conversion transfer parts out of all the photoelectric conversion transfer parts within the photoelectric conversion transfer part group, and controlling the transfer transistors and the switched capacitor amplification parts so that signal charges of the photoelectric conversion elements of the selected plurality of photoelectric conversion transfer parts are transferred to the input side of the switched capacitor amplification part via the transfer transistors of the selected plurality of photoelectric conversion transfer parts, the plurality of signal charges are added up, and the added-up signal charge is read out by the switched capacitor amplification parts.

In this amplifying solid-state image pickup device of this invention, the signal charges of the plurality of photoelectric conversion elements are added up on the input side of the switched capacitor amplification part via the transfer transistors. This means an addition by electric charge, producing a large effect for S/N improvement. Also, the addition operation is performed at the pixel part, so that the read circuit never becomes complex. It becomes possible to effectively reduce the capacity of the signal charge storage part on the input side of the switched capacitor amplification parts by constituting amplifiers with the switched capacitor amplification parts, so that the charge-voltage conversion gain can be enhanced. Also, since a plurality of photoelectric conversion transfer parts are selected out of all the photoelectric conversion transfer parts in the photoelectric conversion transfer part group and then the signal charges of the photoelectric conversion elements of the selected photoelectric conversion transfer parts are added up, it becomes possible to select the combination of pixels (photoelectric conversion elements) in various ways, making the device applicable over a wide range.

In one embodiment, the control part is switchable between an addition operation mode for performing addition of the signal charges and an independent operation mode for independently reading signal charges of the photoelectric conversion elements, respectively, without performing the addition of signal charges.

In this embodiment, only changing the driving method of the control part makes it possible to select from between the independent operation mode that involves no addition operation so that a high resolution is ensured, and the addition operation mode that involves addition operation so that high frame read speed and sensitivity improvement are ensured whereas the resolution is sacrificed.

In one embodiment, the photoelectric conversion element is a buried photodiode.

In one embodiment, each of the photoelectric conversion elements has any one of a plurality of color characteristics, and

the signal charges of the photoelectric conversion elements are added up which have an identical color characteristic.

In this embodiment, the amplifying solid-state image pickup device serves as a color solid-state image pickup device, in which pixel addition is enabled even with color elements and, in particular, enhancing the signal quantity of identical colors in primary-color based color elements allows the sensitivity to be increased.

In one embodiment, each of the photoelectric conversion elements has any one of a plurality of color characteristics, and

the signal charges of the photoelectric conversion elements are added up which have different color characteristics composing a combination of a specified plurality of colors, respectively.

In this embodiment, the amplifying solid-state image pickup device serves as a color solid-state image pickup device, in which pixel addition is enabled even with color elements and, in particular, enhancing necessary color signals by addition of a particular combination of colors especially in complementary-color based color elements allows the sensitivity to be increased.

In one embodiment, the photoelectric conversion transfer part groups are arrayed in a matrix shape,

in each of the photoelectric conversion transfer parts, the transfer transistors are composed of an odd-numbered field transfer transistor and an even-numbered field transfer transistor which respectively transfer signal charge of the photoelectric conversion element,

the switched capacitor amplification part includes an odd-numbered field switched capacitor amplification part whose input side is connected to an output side of the odd-numbered field transfer transistor and an even-numbered field switched capacitor amplification part whose input side is connected to an output side of the even-numbered field transfer transistor,

the control part includes an odd-numbered field control part for controlling the odd-numbered field transfer transistor and the odd-numbered field switched capacitor amplification part as well as an even-numbered field control part for controlling the even-numbered field transfer transistor and the even-numbered field switched capacitor amplification part, and

the odd-numbered field control part and the even-numbered field control part perform interlace reading of a columnar-direction combination of photoelectric conversion elements to be added to the odd-numbered field switched capacitor amplification part side as well as a columnar-direction combination of photoelectric conversion elements to be added to the even-numbered field switched capacitor amplification part side each with a shift of one row in the columnar direction.

In this embodiment, the combination of pixels to be added up on the field basis is shifted by one horizontal row (i.e., shifted by one row in the columnar direction) so as to implement interlace reading. Therefore, it becomes possible to do interlace reading, which has been difficult to do particularly with color elements.

According to the amplifying solid-state image pickup device of the present invention, the signal charges of the plurality of photoelectric conversion elements are added up on the input side of the switched capacitor amplification parts via the transfer transistors, the S/N improvement effective becomes larger. Also, the addition operation is performed at the pixel part, so that the read circuit never becomes complex. Further, with the amplification circuit provided as the switched capacitor type, it becomes possible to effectively reduce the capacity of the signal charge storage part on the input side of the switched capacitor amplification parts, so that the charge-voltage conversion gain can be enhanced. Also, only changing the driving method makes it possible to select from between an operation mode that involves no addition operation so that a high resolution is ensured, and an operation mode that involves addition operation so that high frame read speed and sensitivity improvement are ensured whereas the resolution is sacrificed.

Thus, the present invention is greatly useful for the formation of image sensors that are capable of switching between still pictures of high resolution and motion pictures of high sensitivity and high speed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinbelow, the present invention is described in more detail by reference to an embodiment shown in the accompanying drawings.

First Embodiment

FIGS. 1A to 1Cshow a two-dimensional amplifying solid-state image pickup device as an example of an amplifying solid-state image pickup device, which is an embodiment of the present invention.FIG. 1Ais an explanatory view showing an example of pixel addition,FIG. 1Bis an explanatory view showing another example of pixel addition, andFIG. 1Cis a circuit diagram of the two-dimensional amplifying solid-state image pickup device.

FIG. 1Ashows an example of a method for performing an addition between upper-and-lower two pixels30,30of an identical color in a Bayer pattern color filter that is composed of the three primary colors, green (G), red (R) and blue (B), where the addition operation is performed every other pixel.

FIG. 1Bshows an example of a method for performing an addition between upper-and-lower two pixels30,30of a specific color combination in a color filter that is composed of complementary colors of yellow (Ye), cyan (Cy) and magenta (Ma), and green (G), where the following addition results can be obtained alternately in a cycle of 1H (one horizontal scanning period):
[Ye+G, Cy+Ma]−th row→brightness+color-difference signal (2B-G)
[Cy+G, Ye+Ma]−th row→brightness+color-difference signal (2R-G).
Thus, a necessary color signal can be obtained.

As shown inFIG. 1C, a circuit for fulfilling the pixel addition shown inFIGS. 1A and 1Bincludes a photoelectric conversion transfer part10provided in every pixel30, a switched capacitor amplification part20for converting signal charge derived from the photoelectric conversion transfer part10into voltage to amplify the voltage, and a vertical scanning circuit25as an example of a control part for controlling the photoelectric conversion transfer part10and the switched capacitor amplification part20.

FIG. 1Cshow only two columns, the j-th (j is a natural number) column and the (j+1)-th column, out of the photoelectric conversion transfer parts10of a plurality of rows and a plurality of columns, where switched capacitor amplification parts20are respectively connected to photoelectric conversion transfer part groups. The photoelectric conversion transfer part groups are respectively constituted by photoelectric conversion transfer parts10in each column. It is noted that k is an integer of not less than 2, and an example of k=4 is shown inFIG. 1C.

The photoelectric conversion transfer part10has a photodiode1as an example of a photoelectric conversion element whose anode is connected to the ground, and a transfer transistor2whose drain is connected to a cathode of the photodiode1.

Also, the switched capacitor amplification part20has an inverting amplifier3, a reset transistor5and a capacitor4(as an example of a capacitance element), both being inserted between input and output of the inverting amplifier3, and a select transistor6inserted between the output side of the inverting amplifier3and a vertical signal line7.

On the input side of the inverting amplifier3is a signal charge storage part8to which four photoelectric conversion transfer parts10are commonly connected at their output side (i.e., source of the transfer transistors2). That is, the signal charge storage part8extends from an input end of the switched capacitor amplification part20up to the output side of each transfer transistor2. It is noted that a capacitance of the signal charge storage part8is expressed by CFD, and a capacitance of the capacitor4is by Cin.

The vertical scanning circuit25has transfer transistor drive signal lines21, a select transistor drive signal line22, and a reset transistor drive signal line23.

The transfer transistor drive signal line21is connected to a gate of the transfer transistor2of each of the photoelectric conversion transfer parts10arrayed along the row direction. The select transistor drive signal line22is connected to a gate of the select transistor6of the switched capacitor amplifier part20. The reset transistor drive signal line23is connected to a gate of the reset transistor5of the switched capacitor amplifier part20.

Referring toFIG. 1C, a pixel of the first row connected to the n-th switched capacitor amplifier part20is expressed by (n, 1) where n is a natural number, and a pixel of the second row is by (n, 2), . . . , a pixel of the fourth row is by (n, 4). Drive pulses φT(n, 1), φT(n, 2), . . . , φT(n, 4) outputted from the vertical scanning circuit25are applied to the gate of the transfer transistor2of each of the pixel(n, 1), pixel(n, 2), . . . , pixel(n, 4) via each of transfer transistor drive signal lines21.

A drive pulse φR(n) is applied to the gate of the reset transistor5of the n-th switched capacitor amplifier part20via the reset transistor drive signal line23, and a drive pulse φs(n) is applied to the gate of the select transistor6via the select transistor drive signal line22.

Then, an output signal Vs,jis obtained from an output signal line7of the j-th column, and an output signal Vs,j+1is obtained from output signal line11of the (j+1)th column.

It is noted that the gain GAMof the inverting amplifier3is set as large a value as possible. With the gain GAMlarge enough, the inverting amplifier3, the reset transistor5and the capacitor4make up a switched capacitor amplifier inFIG. 1C. Accordingly, the signal charge of the signal charge storage part8is transferred to the capacitor4(capacitance Cin) and stored therein. That is, the capacitance for conversion of signal charge into voltage effectively changes from CFDto Cin, where a setting that CFD>>Cinmakes it possible to increase the charge-voltage conversion efficiency.

Further, inFIG. 1C, assuming that the photodiode1is of the buried type and that the charge transfer from the photodiode1to the signal charge storage part8via the transfer transistor2is perfect, noise generated at the photoelectric conversion transfer part10can be suppressed to a large extent.

FIGS. 2A–2Care timing charts for explaining operations of the two-dimensional amplifying solid-state image pickup device shown inFIGS. 1A–1C, whereFIG. 2Acorresponds toFIG. 1A,FIG. 2Bcorresponds toFIG. 1B, andFIG. 2Cshows timing in the case where pixel addition is not performed. It is in a period T3Athat the pixel addition operation is performed, andFIGS. 2A–2Cdiffer from one another only in the operation in each period T3A.

In a period T1, in common toFIGS. 2A–2C, a drive pulse φR(n) applied to the reset transistor5of the n-th switched capacitor amplification part20goes High level, causing the reset transistor5to turn to an On state. As a result, input and output of the inverting amplifier3are short-circuited, where the voltage of the signal charge storage part8is reset to a constant voltage.

In the next period T2, in common toFIGS. 2A–2C, the drive pulse φR(n) goes Low level, causing the reset transistor5to turn to an Off state. However, because the drive pulse φs(n) is at High level, the select transistor6turns to the On state. Also, the inverting amplifier3inverts and amplifies the voltage of the signal charge storage part8, and the reset level is read to the vertical signal line7via the select transistor6.

In the next period T3B, the drive pulse φs(n) goes Low level, causing the select transistor6to turn Off.

In the case shown inFIG. 2A, in the period T3Aof the first 1H (one horizontal scanning period), the drive pulse φT(n,1) applied to the pixel (n, 1) and the drive pulse φT(n, 3) applied to the pixel (n, 3) go High level, so that the potential levels of the gates of the transfer transistors2rise. Resultantly, the signal charges stored in the photodiodes1of the pixels (n, 1) and (n, 3) are transferred to the signal charge storage part8. That is, pixel signal charges of the pixels (n, 1) and (n, 3) are added up. In the next 1H, since the drive pulse φT(n, 2) applied to the pixel (n, 2) and the drive pulse φT(n, 4) applied to the pixel (n, 4) go High level, so that the potential levels of the gates of transfer transistors2rise. Resultantly, the signal charges stored in the photodiodes1of the pixels (n, 2) and (n, 4) are transferred to the signal charge storage part8. That is, pixel signal charges of the pixels (n, 2) and (n, 4) are added up. Thus, the operation shown inFIG. 2Acorresponds to that ofFIG. 1A.

In the case shown inFIG. 2B, in the period T3Aof the first 1H, the drive pulse φT(n, 1) applied to the pixel (n, 1) and the drive pulse φT(n, 2) applied to the pixel (n, 2) go High level, so that the potential levels of the gates of the transfer transistors2rise. Resultantly, the signal charges stored in the photodiodes1of the pixels (n, 1) and (n, 2) are transferred to the signal charge storage part8. That is, pixel signal charges of the pixels (n, 1) and (n, 2) are added up. In the next 1H, since the drive pulse φT(n, 3) applied to the pixel (n, 3) and the drive pulse φT(n, 4) applied to the pixel (n, 4) go High level, so that the potential levels of the gates of the transfer transistors2rise. Resultantly, the signal charges stored in the photodiodes1of the pixels (n, 3) and (n, 4) are transferred to the signal charge storage part8. That is, pixel signal charges of the pixels (n, 3) and (n, 4) are added up. Thus, the operation shown inFIG. 2Bcorresponds to that ofFIG. 1B.

In the case shown inFIG. 2C, in the operation in the period T3A, since the drive pulse φT(n, i) applied to the pixel (n, i) goes High level so that the potential level of the gate of the transfer transistor2rises, signal charge stored in the photodiodes1of the pixel (n, i) is transferred to the signal charge storage part8. That is, pixel signal charge of the pixel (n, i) is read out solely. In this case, because i is shifted from 1 to 4 successively by 1H, the pixels (n, 1) to (n, 4) are read out successively and independently.

In the next period T4, in common toFIGS. 2A–2C, the drive pulse φT(n, 1) goes Low level, causing the transfer transistor2to turn to an Off state. Therefore, the signal charge storage part8holds a voltage that is shifted from the voltage in the period T2by a variation due to the signal charge transfer, and the drive pulse φs(n) is at High level so that the select transistor6turns to an On state. Therefore, the signal level is amplified by the inverting amplifier3, and read to the vertical signal line7via the select transistor6.

In the above addition operation for pixel signals, since signal charges are added up on the input side of the switched capacitor amplification part20, noise resulting after the addition is represented by the mentioned equation (Eq. 4), being smaller as compared with that of the mentioned equation (Eq. 1).

In the addition operation of the present invention, a signal is represented by the above (Eq. 2) through charge addition. Therefore, assuming that (np1, np2)<<(na1) and that signals of P1and P2are of the same, the S/N is as shown by the above (Eq. 5) from the relations that s12=2·s1and n12=na1, where the improvement of S/N enlarges to a double.

Further, in the present invention, with the gain GAMof the inverting amplifier3large enough as described above, there is a great advantage that the input capacitance CFDof the switched capacitor amplification part20can be neglected, allowing the charge-voltage conversion efficiency to be increased despite the pixel charge addition structure.

InFIGS. 2A and 2B, a case has been shown in which the addition period T3Afor addition of two pixel signal charges is concurrent between two rows. However, the present invention not being limited to this, the periods T3Aand T3Amay not coincide each other between two rows if the periods T3Aand T3Aare within the period T3B. That is, even with a time difference in read operation, a correct addition is achieved.

Second Embodiment

FIG. 3shows an example of pixel addition in a two-dimensional amplifying solid-state image pickup device as an example of an amplifying solid-state image pickup device, which is another embodiment of the invention.FIG. 4shows a circuit diagram for fulfilling the pixel addition shown inFIG. 3, andFIGS. 5A and 5Bshows timing charts for explaining operations of the circuit shown inFIG. 4.

FIG. 3shows an example of a method for performing an addition among upper-and-lower two pixels30,30and left-and-right two pixels30,30of an identical color in a Bayer pattern color filter that is composed of the three primary colors, green (G), red (R) and blue (B), where the addition operation is performed every other pixel in both horizontal and vertical directions.

FIG. 4, in which symbols common toFIG. 1Crepresent like contents, differs fromFIG. 1Cin that a first signal charge storage part81of the j-th column and a third signal charge storage part83of the (j+2)th column are connected to each other while a second signal charge storage part82of the (j+1)th column and a fourth signal charge storage part84of the (j+3)th column are connected to each other, and that the transfer transistors2of the first and second columns in groups of four columns are connected to a horizontal transfer transistor drive signal line φT(n, Ai) while the transfer transistors2of the third and fourth columns in groups of four columns are connected to a horizontal transfer transistor drive signal line φT(n, Bi), where i and n are natural numbers.

InFIGS. 5A and 5B, the same symbols as inFIG. 2Arepresent the same contents.

FIG. 5Ashows an operational timing chart of operation shown inFIG. 3. Referring toFIG. 5A, in the period T3Aof the first 1H, drive pulses φT(n, A1) and φT(n, B1) as well as φT(n, A3) and φT(n, B3) on the transfer transistor drive signal lines from a vertical scanning circuit (not shown) turn ON simultaneously, and totally four pixels, i.e. pixel signals of the 1st column and the 3rd column of the 1st row as well as pixel signals of the 1st column and the 3rd column of the 3rd row, are added up and led to the signal line7of the j-th column, while totally four pixels, i.e. pixel signals of the 2nd column and the 4th column of the 1st row as well as pixel signals of the 2nd column and the 4th column of the 3rd row, are added up and led to the signal line11of the (j+1)th column.

In the period T3Aof the next 1H, drive pulses φT(n, A2) and φT(n, B2) as well as φT(n, A4) and φT(n, B4) turn ON simultaneously, and totally four pixels, i.e. pixel signals of the 1st column and the 3rd column of the 2nd row as well as pixel signals of the 1st column and the 3rd column of the 4th row, are added up and led to the signal line7of the j-th column, while totally four pixels, i.e. pixel signals of the 2nd column and the 4th column of the 2nd row as well as pixel signals of the 2nd column and the 4th column of the 4th row, are added up and led to the signal line11of the (j+1)th column.

Referring toFIG. 5B, in the operation in the period T3A, since drive pulses φT(n, Ai) and φT(n, Bi) applied to the pixels on the i-th row in groups of n rows go High level with a shift of a 1H (one horizontal scanning period) so that the potential levels of the gates of the transfer transistors2rise, signal charges stored in the photodiodes1of the pixels of the i-th row are transferred to the first and third signal charge storage parts81,83with a shift of a 1H period and are transferred to the second and fourth signal charge storage parts82,84with a shift of a 1H period. That is, pixel signals of the first column and third column in groups of four columns at the i-th row in groups of n rows are respectively led to the signal line7of the j-th column with a shift of a 1H period, and pixel signals of the second column and fourth column in groups of four columns at the i-th row in groups of n rows are respectively led to the signal line11of the (j+1)th column with a shift of a 1H period. In this case, because i is shifted from 1 through 4 successively on the 2H basis, all the pixels of the first through the fourth rows in groups of n rows are read out successively and independently on the 1H basis.

Third Embodiment

FIGS. 6A and 6Bshow an example of the pixel addition of a two-dimensional amplifying solid-state image pickup device as an example of an amplifying solid-state image pickup device, which is yet another embodiment of the present invention. Also,FIG. 7shows a circuit diagram for performing the pixel addition shown inFIGS. 6A and 6B.

FIGS. 6A and 6B, likeFIG. 1B, show an example of the method for performing an addition between upper-and-lower two pixels30,30of a specific color combination in a color filter that is composed of the complementary colors of yellow (Ye), cyan (Cy) and magenta (Ma), and green (G), where the following addition results can be obtained alternately in a cycle of 1H:
[Ye+G, Cy+Ma]-th row→brightness+color-difference signal (2B-G)
[Cy+G, Ye+Ma]-th row→brightness+color-difference signal (2R-G).

The difference fromFIG. 1Blies in that the combination of pixels30to be added up is shifted by one horizontal row on the field basis, thereby enabling the interlaced reading. That is, in the odd-numbered field shown inFIG. 6A, the above signal is obtained by the addition between an odd-numbered row and an even-numbered row. In the even-numbered field shown inFIG. 6B, the above signal is obtained by the addition between an even-numbered row and an odd-numbered row.

FIG. 7, in which symbols common toFIG. 1Crepresent like contents, differs fromFIG. 1Cin that transfer transistors for transferring charge from photodiodes1include an odd-numbered field transfer transistor2aand an even-numbered field transfer transistor2b, where the odd-numbered field transfer transistor2ais connected to an odd-numbered field signal charge storage part8awhile the even-numbered field transfer transistor2bis connected to an even-numbered field signal charge storage part8b, and where the odd-numbered field signal charge storage part8ais connected to an odd-numbered field switched capacitor amplification part20awhile the even-numbered field signal charge storage part8bis connected to an even-numbered field switched capacitor amplification part20b.

In the odd-numbered field, drive pulses are applied from an odd-numbered field drive system (odd-numbered field vertical scanning circuit)25ato the gates of the odd-numbered field transfer transistors2aand the odd-numbered field switched capacitor amplification parts20a. That is, a drive pulse φT(Ōn, i) is applied to a gate of the transfer transistor2aof the i-th row, a drive pulse φR(Ōn) is applied to a gate of a reset transistor5, and a drive pulse φS(Ōn) is applied to a gate of the select transistor6.

Similarly, in the even-numbered field, drive pulses are applied from an even-numbered field drive system (even-numbered field vertical scanning circuit)25bto the even-numbered field transfer transistors2band the even-numbered field switched capacitor amplification parts20b. That is, a drive pulse φT(En, i) is applied to a gate of the transfer transistor2aof the i-th row, a drive pulse φR(En) is applied to a gate of the reset transistor5, and a drive pulse φS(En) is applied to a gate of the select transistor6.

Consequently, in comparison between the odd-numbered field and the even-numbered field, the combination of the photodiodes1(in the column direction) to be connected to the switched capacitor amplification parts20a,20bare shifted from each other by 1 horizontal row (i.e., shifted by one in the column direction). Therefore, in comparison between one case where drive pulses are applied from the odd-numbered field drive system25aand another case where the drive pulses are applied from the even-numbered field drive system25b, the combination of pixels to be added up is shifted by 1 horizontal row. That is, the interlaced reading is enabled. Thus, it becomes implementable to perform interlaced reading, which has been difficult for color elements of the APS image sensor.