DUMMY DIES AND METHOD OF FORMING THE SAME

The present disclosure provides a dummy die with improved thermal conductivity and warpage control. The dummy die includes an adjustment layer formed over a semiconductor substrate. The adjustment layer has a thermal conductivity in a range between about 30 W/mK and about 100 W/mK. The adjustment layer may include silicon nitride or silicon carbide.

BACKGROUND

Three-dimensional integrated circuits (3DICs) are a relatively recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (POP) and system-in-package (SiP) packaging techniques. A 3DIC may provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as examples.

DETAILED DESCRIPTION

Embodiments will be described with respect to embodiments in a specific context, namely an integrated circuit package. Other embodiments may also be applied, however, to other electrically connected components, including, but not limited to, package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, die-to-wafer assemblies, in assembling packaging, in processing substrates, interposers, or the like, or mounting input components, boards, dies or other components, or for connection packaging or mounting combinations of any type of integrated circuit or electrical component. Various embodiments described herein allow for packaging functional components (such as, for example, integrated circuit dies) of varying functionalities and dimensions (such as, for example, heights) in a same integrated circuit package. Various embodiments described herein may be integrated into a chip-on-wafer-on-substrate (CoWoS) process and a chip-on-chip-on-substrate (CoCoS) process.

Embodiments of the present disclosure relates to a dummy die with an adjustment layer to increase thermal conductivity and warpage control. The adjustment layer may include one or more layer of materials having thermal conductivity in a range between about 30 W/mK and about 100 W/mK. In some embodiments, the adjustment layer may include silicon nitride or silicon carbide. In some embodiments, dummy dies may be bond with another die by a bonding film including dummy conductors formed therein to further improve thermal conductivity.

FIG.1is a flow diagram of a method100of forming of dummy dies according to embodiments of the present disclosure. Particularly, the method100forms dummy dies used in SoIC (system on integrated circuit) packaging with improved thermal conductivity. A dummy die may be regarded as a device-free die. A dummy die is substantially free of any electronic devices. For example, a dummy die is substantially free of any active components or functional components, such as transistors, capacitors, resistors, diodes, photodiodes, fuse devices and/or other similar devices. A dummy die may include a semiconductor substrate and a bonding structure. Embodiments of the present disclosure provide a dummy die with a bonding structure having improved thermal conductivity and/or improved warpage adjustment.

FIGS.2-8,9A-9E, and10schematically demonstrate various processing stages during fabrication of dummy substrate200according to embodiments of the present disclosure. Particularly,FIGS.2-8,9A-9E, and10demonstrate forming dummy devices using the method100.

In operation102, an adhesive layer204is deposited on a semiconductor substrate202, as shown inFIG.2.FIG.2is a schematic partial cross-sectional view of the semiconductor substrate202. A plurality of dummy substrate200are to be formed from the semiconductor substrate202.

The semiconductor substrate202is formed from one or more semiconductor materials. In some embodiments, the semiconductor substrate202is a bear substrate including an elementary semiconductor, such as silicon or germanium in a crystalline, a polycrystalline, or an amorphous structure; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as e.g., silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.; combinations thereof, or other suitable material. In some embodiments, the semiconductor substrate202may include one or more dopants. The semiconductor substrate202may also be in the form of silicon-on-insulator (SOI). The SOI substrate may comprise a layer of a semiconductor material, e.g., silicon, germanium and/or the like, formed over an insulator layer, e.g., buried oxide and/or the like, which is formed on a silicon substrate. In addition, other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like.

The adhesive layer204is deposited on a front side202fof the semiconductor substrate202. In some embodiments, the adhesive layer204may be formed by flowing an oxidizing precursor to the processing chamber. In some embodiments, one or more cleaning processes may be performed to remove native oxides and/or contaminations from the semiconductor substrate202prior to forming the adhesive layer204.

The adhesive layer204provides adhesion between subsequent layers to be formed on the semiconductor substrate202. In some embodiments, when the semiconductor substrate202comprises silicon, the adhesive layer204comprises silicon oxide. In some embodiments, the adhesive layer204is formed of USG (undoped silica glass). In some embodiments, the adhesive layer204have a thickness in a range between about 100 Å and about 1000 Å. If the thickness of the adhesive layer204is less than 100 Å, adhesion effect of the adhesive layer204may not provide sufficient adhesion for the subsequent layer to the semiconductor substrate202to sustain the subsequent process, such as grinding and planarization, for example, cracks may be formed in the adhesive layer204. If the thickness of the adhesive layer204is greater than 1000 Å, ductility of the adhesive layer204may reduce, and a buckling may be formed in the adhesive layer204.

In operation104, an adjustment layer206is deposited on the semiconductor substrate202over the adhesive layer204, as shown inFIG.2. In some embodiments, the adjustment layer206provides improved heat conductivity in the subsequently formed dummy substrate200. Additionally, the adjustment layer206also provides stress modulation or warpage adjustment to the semiconductor substrate202.

The adjustment layer206has a thickness T1. In some embodiments, the thickness T1is in a range between about 3000 Å and about 6000 Å. A thickness less than 3000 Å may not provide sufficient thermal conductivity or stress modulation/warpage adjustment. A thickness great than 6000 Å may create too much stress and causing the adjustment layer206to peel off from the semiconductor substrate202.

In some embodiments, the adjustment layer206may be a thermal conducting layer having a thermal conductivity in range between about 30 W/mK and about 100 W/mK. In some embodiments, the adjustment layer206may include a suitable dielectric film, such as a semiconductor nitride or a semiconductor carbide. In some embodiments, the adjustment layer206may include silicon nitride (Si3N4or SiN), Si-rich silicon nitride, a N-rich silicon nitride, silicon carbide, or the like.

In some embodiments, the adjustment layer206may be silicon nitride. The adjustment layer206may be formed by flowing precursors containing a nitrogen source and a semiconductor source. In some embodiments, the adjustment layer206is formed at a low temperature range to improve thermal conductivity and avoid forming hot spots in a SoIC.

In operation106, a bonding film208is deposited over the adjustment layer206, as shown inFIG.3.FIG.3is a partial cross-sectional view of the dummy substrate200after operation106. The bonding film208is configured to bond the dummy die to be formed with other dies during subsequent packaging. Particularly, the bonding film208may be selected from any material suitable to bond the adjustment layer206with another die or with another bonding filming. The bonding film208may be formed with any suitable material for bonding in packaging. In some embodiments, the bonding film208is formed of an oxide material. For example, the bonding film208is formed of USG. In some embodiments, the bonding film208has a thickness in a range between about 100 Å and about 1000 Å. The thickness of the bonding film208may be selected according to the queue time. Because the bonding film208may absorb moisture during wait time, it is desirable to have a thinner bonding film208to avoid trapping excess moisture in IC packages if there is long queue time for the dummy substrate200during packaging.

In operation108, a photoresist layer210is deposited over the bonding film208and a dicing pattern is formed in the photoresist layer210, as shown inFIG.4.FIG.4is a partial cross-sectional view of the dummy substrate200after operation108. The photoresist layer210may be deposited over the bonding film208. A photolithography process is followed to form a dicing pattern with trenches212in the photoresist layer210. The photoresist layer210is selectively removed to form the trenches212. The trenches212may form a grid defining a plurality of rectangular areas. As shown inFIG.4, the bonding film208is exposed at the bottom of the trenches212.

In operation110, one or more etch processes are performed to etch through the bonding film208, the adjustment layer206, the adhesive layer204, and into the semiconductor substrate202forming dicing trenches214, as shown inFIG.5.FIG.5is a partial cross-sectional view of the dummy substrate200after operation110. The patterned photoresist layer210is used as a mask to form the dicing trenches214. The dicing trenches214may form a grid in the bonding film208, the adjustment layer206, the adhesive layer204, and into the semiconductor substrate202forming a plurality of dummy areas216. The dicing trenches214are formed into the semiconductor substrate202but not through the semiconductor substrate202so that the dummy areas216remain connected by the semiconductor substrate202. The dicing trenches214are deep enough so that the dummy areas216may be separated from one another when the semiconductor substrate202is grinded down from the back side. In some embodiments, the dicing trenches214have a width W1in a range between about 6 microns and about 10 microns.

In operation112, a protective layer218is deposited to fill the dicing trenches214and cover the dummy areas216, as shown inFIG.6.FIG.6is a partial cross-sectional view of the dummy substrate200after operation112. The protective layer218is used to cover and protect the bonding film208and exposed portions of the semiconductor substrate202, the adhesive layer204and the adjustment layer206during subsequent processing. The protective layer218may be formed by any material that is capable of isolate the dummy areas216from the processing environment during the subsequent processing. The protective layer218may also be easily removed from the dummy areas216. In some embodiments, the protective layer218may be formed from a photoresist material. In some embodiments, the protective layer218may be deposited over the dummy areas216by a spin-on coating process followed by a curing process, e.g., a low temperature curing technique. However, any suitable coatings, any suitable deposition techniques, and any suitable curing techniques may also be used. Alternatively, the protective layer218may be a curable resin, polyimide coating, polybenzoxazole (PBO), epoxy films, or the like.

In operation114, a back grinding tape220and a carrier wafer222are attached to the protective layer218, as shown inFIG.7.FIG.7is a partial cross-sectional view of the dummy substrate200after operation114. The back grinding tape220is first attached to the protective layer218. The carrier wafer222is then attached to the back grinding tape220so that the semiconductor substrate202may be thinned down from a back side202b.

In operation116, the semiconductor substrate202is flipped over and a back grinding process is performed to thin down the semiconductor substrate202from the back side202b, as shown inFIG.8.FIG.8is a partial cross-sectional view of the dummy substrate200after operation118. The back grinding process reduces thickness of the semiconductor substrate202to a target thickness according to the design.

In some embodiments, the back grinding process is performed to reduce the thickness of the semiconductor substrate202and to “dice” the dummy substrate200into a plurality of dummy dies224. As shown inFIG.8, the back grinding process removes the portion of the semiconductor substrate202without the dicing trenches214and exposes the protective layer218. In some embodiments, the concentration of the protective layer218in the grinding waste may be used as an end point for the back grinding process. After the back grinding process, the thickness of the semiconductor substrate202is reduced to a thickness T2. In some embodiment, the thickness T2is in a range between about 50 microns and about 100 microns.

Even though, the dummy dies224are fabricated after the operation114, the plurality of dummy dies224remain connected by the protective layer218. The dummy dies224are separated by the dicing trenches214which are filled with the protective layer218. The bonding film208on each dummy die224is in contact with the protective layer218, which is attached to the back grinding tape220.

In operation118, one or more expanding processes are performed to increase the distance between the dummy dies224, as shown inFIGS.9A-9E.FIG.9Ais a partial cross-sectional view of the dummy dies224after operation118.FIGS.9B and9Care schematic top views of the plurality of dummy dies224before and after an expansion process.FIGS.9D and9Eare schematic top views of the plurality of dummy dies224before and after a second expansion process.

After the back grinding process, the plurality of dummy dies224are flipped over and attached to an expansion tape226on a frame228. As shown inFIG.9A, the plurality of dummy dies224are glued to the expansion tape226at the back side202b. The carrier wafer222and the back grinding tape220are then removed. The expansion tape226is then stretched so that the dicing trenches214between the dummy dies224widens.

In some embodiments, ultra-violet radiation230may be applied to the expansion tape226so that the expansion tape226may be relaxed and stretched to increase the distance between neighboring dummy dies224. As shown inFIG.9B, prior to the expansion process, the distance between neighboring dummy dies224is the width W1of the dicing trenches214. As discussed above, the width W1is in a range between about 6 microns and about 10 microns. As shown inFIG.9C, after the expansion tape226is stretched, the distance between neighboring dummy dies224is a width W1′. In some embodiments, the width W1′ may be in a range between about 60 microns and about 65 microns. The expanded distance W1′ allows the dummy dies224to be individually picked up from the expansion tape226for subsequent packaging.

In some embodiments, one or more additional expansion processes may be performed to further increase the distance between neighboring dummy dies224for ease of handling. As shown inFIG.9D, the dummy dies224may be transferred from the expansion tape226on the frame228to a second expansion tape226′ on a second frame228′. InFIG.9E, the second expansion tape226′ is stretched and the distance between neighboring dummy dies224increases to a distance W1″. In some embodiments, the width W1″ may be in a range between about 450 microns and about 550 microns. Even though two expansion processes are shown in the example, more or less expansions may be used to realize desirable distance between the dummy dies224so that the dummy dies224may be picked up by die handling tools.

In operation120, the dummy dies224are cleaned and ready for subsequent packaging, as shown inFIG.10.FIG.10is a partial cross-sectional view of the dummy dies224after operation120. The dummy dies224are cleaned to remove the protective layer218by a suitable process, for example, by an ashing process when the protective layer218includes photoresist material. After cleaning, the bonding film208on each dummy die224is exposed. The extended distance W1″ allows the dummy dies224to be picked up individually from the expansion tape226′ for packaging.

The dummy die224according to the present disclosure includes an adjustment layer, such as the adjustment layer206, deposited on a semiconductor substrate202in place of oxide based bonding films. The adjustment layer206is formed by a material with higher thermal conductivity therefore improving heat dissipation in IC packages. The adjustment layer206may also be a high stress layer to improve wafer warpage control, thus, improving bonding quality.

FIG.11includes thermal conductivity and temperature curves of silicon oxide and silicon nitride. Curve250is thermal conductivity and temperature curve of silicon oxide. Curve252is thermal conductivity and temperature curve of silicon nitride. Silicon oxide is used in dummy dies according to the current state of the art. Silicon oxide facilitates bonding between a dummy die to other dies in an IC package. According to embodiments of the present disclosure, the adjustment layer206is used to replace silicon oxide in dummy dies. The adjustment layer206may be formed by silicon nitride. As shown inFIG.11, the thermal conductivity of silicon nitride is much higher than the thermal conductivity of the silicon oxide, particularly at low temperatures. For example, at 25° C., the thermal conductivity of silicon nitride is about 55 W/mK while the thermal conductivity of silicon oxide is about 25 W/mK. Thus, by using the adjustment layer206with silicon nitride to replace silicon oxide layer, embodiments of the present disclosure improve heat dissipation in the bonding region between dummy dies and device dies.

In some embodiments, the adjustment layer206is designed to achieve desirable warpage. For example, a negative warpage may be desired in a dummy die to improve bonding quality. A negative warpage is defined when a substrate is warped towards its back side.FIG.12Ais schematic sectional view of a dummy die224to illustrate negative warpage. InFIG.12A, the dummy die224is positioned with the back side202bof the semiconductor substrate202facing up and the bonding film208facing down. When the dummy die224has no warpage, a profile260of the dummy die224is planar. When the dummy die224has a negative warpage, the profile of the dummy die224is represented by the curve262. With a negative warpage, the bonding film208first would contact the die to be bonded at the center region, and the contact area would expand from the center region to the edge region, thus, improving high bonding quality.

In state-of-the art technology, a negative warpage is achieved by depositing a certain thickness of silicon oxide. For example, a silicon oxide layer having a thickness in a range between about 15 k angstroms and 20 k angstroms is applied to a semiconductor substrate to achieve a negative warpage to improve bonding quality. The adjustment layer206according to the present disclosure may achieve the same or more negative warpage at lesser thickness.

FIG.12Bschematically demonstrates of warpages corresponding to thickness of the adjustment layer206. Line264marks the negative warpage in a wafer with a silicon oxide film having a thickness between 15 k angstroms and 20 k angstrom. Line266indicates shows the warpage values from the adjustment layer206according to the present disclosure. The adjustment layer206is formed from silicon nitride. When the adjustment layer206has a thickness of 3.5 k angstroms, the negative warpage in the dummy die224is slightly less than the negative warpage achieved by a silicon oxide film having a thickness between 15 k angstroms and 20 k angstrom. When the adjustment layer206has a thickness of 4.5 k angstroms, the negative warpage in the dummy die224is about 50% greater than the negative warpage achieved by a silicon oxide film having a thickness between 15 k angstroms and 20 k angstrom. When the adjustment layer206has a thickness of 5.5 k angstroms, the negative warpage in the dummy die224is about twice the negative warpage achieved by a silicon oxide film having a thickness between 15 k angstroms and 20 k angstrom.

As shown inFIG.12B, the adjustment layer206according to the present disclosure may achieve an equal amount or more negative warpage in with a much thinner film. The reduced thickness between the dummy die and the die to be bonded further improves heat dissipation.

FIG.13is a flow diagram illustrating a method300of forming of an integrated circuit package according to embodiments of the present disclosure. Dummy dies according to the present disclosure may be used in the method300.FIGS.14-24schematic demonstrates various processing stages during fabrication of an integrated circuit (IC) package400according to embodiments of the present disclosure. The IC package400may be fabricated using the method300.

The method300may be used to form a 3DIC (three-dimensional integrated circuit) package. In a typical formation process of forming a 3DIC, two layers of dies are vertically stacked, and electrical connections are formed between the two layers of dies. For example, a top die is stacked over a bottom die. The top die and the bottom die may have different dimensions. Dummy dies may be used to make up the dimension difference between the top die and the bottom dies. In the method300, a larger bottom die is bonded to a smaller top die and one or more dummy dies. It should be noted that the terms “top die” and “bottom die” are used for clarity in description, and not necessarily referred to the physical position of the dies.

In operation302, a first die406is attached to a carrier wafer402for bonding a second die, as shown inFIG.14.FIG.14is a schematic cross-sectional view of the IC package400after operation302. The first die406may be referred to as a bottom die is attached to the carrier wafer402via an adhesive layer404.

The first die406may be a logic die, a memory die, a 3DIC die, a CPU (computation process unit) die, a GPU (graphic process unit) die, a SoC (system-on-chip) die, a MEMS die, or the like. The first die406may be a single die or a composition die, such as a chiplet having two or more dies. In some embodiments, the first die406may be a chiplet that includes two or more cores, CPU processors, GPU (processors, and a bus network connecting the two or more cores. From a top view, the first die406may be in a quadrilateral, a rectangular or a square shape.

The carrier wafer402may comprise, for example, glass, silicon oxide, aluminum oxide, and the like. The adhesive layer404is applied to the carrier wafer402. Alternatively, the carrier wafer402may comprise a carrier tape. The adhesive layer404may be used to glue the carrier wafer402to other devices such as the first die406. In some embodiments, the adhesive layer404may be a thermal release film. In some embodiments, the adhesive layer404may be an ultraviolet (UV) glue, which loses its adhesive property when exposed to UV lights. Any suitable adhesive may be utilized, and all such adhesives are fully intended to be included within the scope of the present disclosure.

The first die406may include a substrate412, a device layer414formed in and on the substrate412, and an interconnect structure416formed on the device layer414. The interconnect structure416may include multiplayers of dielectric materials having conductive features418formed therein.

The substrate412may comprise bulk silicon, doped or undoped, or an active layer of a SOI substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. The substrate412has a front side408and a back side410. The device layer414is formed on the front side408of the substrate412. In operation302, the first die406is attached to the carrier wafer402such that the back side410of substrate412faces up for subsequent bonding.

The device layer414include a variety of devices, such as transistors, capacitors, resistors, inductors and the like, which may be used to generate the desired structural and functional requirements of the design for the first die406.

The interconnect structure416is formed over the front side408of the substrate412over the device layer414. The conductive features418embedded in the interconnect structure416are designed to connect the various devices in the device layer414to form functional circuitry. The interconnect structure416is formed of alternating layers of dielectric and conductive material and may be formed through any suitable processes, such as deposition, damascene, dual damascene, etc.

In operation304, a bonding film420is deposited over the first die406, as shown inFIG.15.FIG.15is a schematic cross-sectional view of the IC package400after operation304. In some embodiments, a grinding process may be performed to thin down the substrate412to a desired thickness prior to depositing the bonding film420.

Even though only a single first die406is shown inFIG.14in the first layer, during packaging process, a plurality of dies may be placed over the carrier wafer402to be processed simultaneously. A filling material419may be injected within cavities between the neighboring dies. In some embodiments, the filling material419may include epoxy, resin, molding compounds resin, or the like. After the filling material419is placed into cavities between the dies, the filling material419may be cured to harden the filling material419for optimum protection. While the exact curing process is dependent at least in part on the particular material chosen for the filling material419. In some embodiments, the filling material419may be cured by heating the filling material419to a temperature between about 100° C. and about 130° C. A chemical mechanical polishing (CMP) process may be performed to remove the filling material419deposited over the first die406and to thin down the substrate412in the first die406.

In some embodiments, the bonding film420may be formed of silicon oxide, silicon oxynitride, silicon nitride, or low-k dielectric materials having k values lower than about 3.0. The low-k dielectric materials may include a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In some embodiments, the bonding film420may be formed by suitable fabrication techniques such as chemical vapor deposition (CVD), High-Density Plasma Chemical Vapor Deposition (HDPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

In operation306, bond pad features422, also referred to as bond pad metals (BPMs) are formed in the bonding film420, as shown inFIGS.16A,16B, and16C.FIG.16Ais a schematic cross-sectional view of the IC package400after operation306.FIG.16Bis a plane view of the IC package along B-B line onFIG.16A.FIG.16Cis a plane view of the IC package along C-C line onFIG.16A.

The bond pad features422may be formed of copper or other suitable metal to facilitate subsequent bonding. In some embodiments, the bond pad features422may be formed by suitable fabrication techniques such as electroplating or deposition. In some embodiments, the bond pad features422may be formed by a damascene process, such as a single damascene process or a dual-damascene process. The bond pad features422are configured to bond with bond pad features on a second die. The bond pad features422are arranged within a region corresponding to the second die and in a pattern matching bond pad features in the second die.FIG.16Bschematically demonstrates the distribution of the bond pad features422in the bonding film420. The number of the bond pad features422may be less than or more than what is depicted inFIG.16B. The bond pad features422may be designated based on the demand and/or design layout. In some embodiments, a top surface of the bond pad features422and a top surface of the bonding film420are substantially coplanar so as to provide an appropriate surface for the subsequent bonding. The planarity may be achieved, for example, through a planarization step such as a chemical mechanical polishing (CMP) step or a mechanical grinding step. After planarization, the first die406has a substantially planar bonding surface406bincluding areas of the bonding film420and areas of the bond pad features422.

In some embodiments, a portion of the bond pad features422are connected to through semiconductor vias (TSVs)424. The TSVs424are embedded in the substrate. In some embodiments, the TSVs424may be formed of copper or other suitable metal that is easy for forming a D-D (dielectric-dielectric) and M-M (metal-metal) bonding. In some embodiments, the TSVs424may be formed in at the same time with the bond pad features422by a damascene process. In other embodiments, the TSVs424may be previously fabricated during the front end of the line processes with the device layer414. The TSVs424may be used to provide electrical connection between the first die406and a second die to be bonded to the first die406. First ends of the TSVs424are in contact with the bond pad features422and second ends of the TSVs424are in contact with the conductive features418in the interconnect structure416. The conductive features418may be connected with the active components and/or passive comments in the device layer414.

FIG.16Cschematically demonstrates the distribution of the TSVs424in the substrate412. The number of the TSVs424may be less than or more than what is depicted inFIG.16C. The number and lay out of the TSVs424are designated based on the demand and/or design layout.

In operation308, a second die426and one or more dummy dies224are bonded to the first die406, as show inFIGS.17A-17B.FIG.17Ais a schematic cross-sectional view of the IC package400after operation308.FIG.17Bis a plane view of the IC package along B-B line onFIG.17A.

The second die426may be a logic die, a memory die, a 3DIC die, a CPU die, a GPU (die, a SoC die, a MEMS die, or the like. The second die426may be a single die or a composition die, such as a chiplet having two or more dies. In some embodiments, the second die426may be a memory die.

The second die426may include a substrate428, a device layer430formed in and on the substrate428, and an interconnect structure432formed on the device layer430. The interconnect structure432may include multiplayers of dielectric materials having conductive features434formed therein. The second die426may include a dielectric layer436formed over the interconnect structure432. The dielectric layer436includes bond pads438and bond vias440embedded therein. A bonding film442is formed on the dielectric layer436. Bond pad features444are formed in the bonding film442.

The substrate428may comprise bulk silicon, doped or undoped, or an active layer of a SOI substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. The device layer430is formed on the front side of the substrate428. In operation308, the second die426is bonded to the first die406with a back side of substrate428facing up.

The device layer430include a variety of devices, such as transistors, capacitors, resistors, inductors and the like, which may be used to generate the desired structural and functional requirements of the design for the second die426.

The interconnect structure432is formed over the front side of the substrate428over the device layer430. The conductive features434embedded in the interconnect structure432are designed to connect the various devices in the device layer430to form functional circuitry. The interconnect structure432is formed of alternating layers of dielectric and conductive material and may be formed through any suitable processes, such as deposition, damascene, dual damascene, etc.

The dielectric layer436may include one or more dielectric layers. In some embodiments, the material of the dielectric layer436may be silicon oxide, silicon nitride, silicon oxynitride, or a dielectric layer formed by other suitable dielectric materials. In some embodiments, the dielectric layer436may be undoped silicon glass, lower-k material, extreme low-k material, silicon oxide, or the like. The bond pads438and bond vias440may be formed by aluminum, aluminum copper, or the other suitable conductive material.

In some embodiments, the bonding film442may be formed of silicon oxide, silicon oxynitride, silicon nitride, or low-k dielectric materials having k values lower than about 3.0. The low-k dielectric materials may include carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In some embodiments, the bonding film442may be formed by suitable fabrication techniques such as chemical vapor deposition (CVD), High-Density Plasma Chemical Vapor Deposition (HDPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

The bond pad features444may be formed of copper or other suitable metal to facilitate subsequent bonding. In some embodiments, the bond pad features444may be formed by suitable fabrication techniques such as electroplating or deposition. In some embodiments, the bond pad features444may be formed by a damascene process, such as a single damascene process or a dual-damascene process. The bond pad features444are configured to bond with the bond pad features422on the first die406. In some embodiments, the bond pad features444are arranged in the same layout mirroring the bond pad features422. A portion of the bond pad features444are in contact with the bond pads438by the bond vias440to provide electrical connection to components in the device layer430.

In some embodiments, a top surface of the bond pad features444and a top surface of the bonding film442are substantially coplanar so as to provide an appropriate surface for the subsequent bonding. The planarity may be achieved, for example, through a planarization step such as a chemical mechanical polishing (CMP) step or a mechanical grinding step. After planarization, the second die426has a substantially planar bonding surface426bincluding areas of the bonding film442and areas of the bond pad features444.

In some embodiments, the first die406and the second die426may be bonded face-to-face as shownFIG.17A. The bonding film442of the second die426is bonded to the bonding film420of the first die406through the dielectric-to-dielectric bonding, and the bond pad features444of the second die426are bonded to the bond pad features422of the first die406through the metal-to-metal bonding. The bonding process may be referred to as D-D and M-M bonding.

Before bonding the second die426to the first die406, the second die426may be picked-up and placed onto the bonding surface406bof the first die406such that the bonding surface406bof the first die406is in direct contact with the bonding surface426bof the second die426, and the bond pad features422and444are aligned and in direct contact. In some embodiments, to facilitate the D-D and M-M bonding between the first die406and the second die426, surface preparation for the bonding surfaces of the first die406and second die426may be performed. The surface preparation may include surface cleaning and activation, for example. In some embodiments, the bonding surface406bof the first die406and the bonding surface426bof the second die426may be cleaned by wet cleaning.

After bonding, a D-D and M-M bonding surface is formed between the first die406and the second die426. In some embodiments, the metal-to-metal bonding at the D-D and M-M bonding interface is copper-to-copper bonding. In some embodiments, the dielectric-to-dielectric bonding at the D-D and M-M bonding interface is achieved with Si—O—Si bonds generated. After bonding, the first die406is electrically connected to the second die426by the bonding between the bond pad features444and the bond pad features422. During the D-D and M-M bonding process, a low temperature heating process at a temperature range between about 100° C. and about 280° C. is performed to strengthen the dielectric-to-dielectric bonding at the D-D and M-M bonding interface. A high temperature heating process is performed at a temperature in a range between about 100° C. and about 400° C. to facilitate the metal-to-metal bonding at the D-D and M-M bonding interface.

As shown inFIG.17B, the second die426is smaller than the first die406. One or more dummy dies224are bonded to the first die406so that the bottom layer and the top layer are substantially the same size.FIG.17Bdepicts four dummy dies224. Less or more dummy dies224may be included depending on the design of the IC package400.

Shape and dimension of each dummy die224may be selected according to the shapes, dimensions, and relative position of the first die406and the second die426. The surface area of each dummy die224may be selected according to the surface area of the larger die or the first die406in the IC package400. In some embodiments, a ratio of the surface area of each dummy die224over the surface area of the first die406may be in a range between about 7.5% and about 10%. The shape of the dummy dies224may be rectangular, square, or other shapes conform with the layout.

Before bonding the dummy dies224to the first die406, the dummy dies224may be picked-up from the frame, such as the frame228′ inFIG.10and placed onto the bonding surface406bof the first die406such that the bonding surface406bof the first die406is in direct contact with the bonding film208of the dummy die224. In some embodiments, to facilitate the D-D and M-M bonding between the dummy dies224and the second die426, surface preparation for the bonding surfaces of the first die406and dummy dies224may be performed. The surface preparation may include surface cleaning and activation.

The dummy dies224are stacked on the first die406and bonded thereon. The dummy dies224are disposed side-by-side with each other and with the second die426. In some embodiments, the dummy dies224are fusion-bonded with the first die406. In other words, the dummy dies224are bonded with the first die406through dielectric-to-dielectric bonding. In some embodiments, the dummy dies224may be bonded by a low temperature heating process at a temperature range between about 100° C. and about 280° C. to strengthen the dielectric-to-dielectric bonding. In some embodiments, bonding the dummy dies224to the first die406and bonding the second die426to the first die406may be performed in the same D-D and M-M bonding process. Alternatively, bonding the dummy dies224to the first die406and bonding the second die426to the first die406may be performed in separate bonding processes.

In operation310, a dielectric film446is deposited over the IC package400to fill gaps between the dummy dies224and the second die426, as shown inFIG.18.FIG.18is a schematic cross-sectional view of the IC package400after operation310. In some embodiments, the dielectric film446may include an oxide material, such as silicon oxide (SiO), TEOS, BPTEOS, or the like. The dielectric film446may also be a nitride material. The dielectric film446may also be a low-k dielectric material, a polymer material, other dielectric material, the like, or combinations thereof. The dielectric film446may also be formed by plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), plasma vapor deposition (PVD), or the like.

In operation312, a planarization process is performed, as shown inFIG.19.FIG.19is a schematic cross-sectional view of the IC package400after operation312. The planarization process removes excess dielectric film446over the dummy dies224and the second die426. The planarization process may also be used to thin down the dummy dies224and the second die426and to generate a planar surface448for further process.

In operation314, a second carrier wafer450is attached to the IC package400on the surface448, as shown inFIG.20.FIG.20is a schematic cross-sectional view of the IC package400after operation314. In some embodiments, a bonding film452is formed over the second carrier wafer450. A bonding film454is formed over the planar surface448of the IC package400. In some embodiments, the bonding film208is formed of an oxide material. For example, the bonding films452,454may include a dielectric material, such as silicon oxide, silicon oxynitride, or the like.

The IC package400is attached to second carrier wafer450by bonding the bonding films452,454. After the second carrier wafer450is attached to the IC package400, the first carrier wafer402may be removed, and the IC package400flipped over to form contacts over the front side of the first die406. In some embodiments, a surface preparation, such as surface cleaning and activation, may be performed to expose a topmost layer of the conductive features418for subsequent processing.

In operation316, a RDL (redistribution layer) structure456and external connectors464are formed over the first die406, as shown inFIG.21.FIG.21is a schematic cross-sectional view of the IC package400after operation314.

The RDL structure456may comprise one or more conductive layers462formed in on or more passivation layers458. In some embodiments, the RDL structure456may include a protection layer460disposed over the passivation layers458. The passivation layer458may be formed from a nitride base material. The protection layer460may be formed from silicon oxide, silicon nitride, or a combination. The conductive layers462may include metals such as aluminum, copper, tungsten, titanium, and combinations thereof. The RDL structure456may be formed by depositing the conductive layers462through chemical vapor deposition and then etching the undesired portions, leaving the RDL structure456. Other materials and process, such as a well-known damascene process, could alternatively be used to form the RDL structure456.

The external connectors464may be contact bumps such as micro bumps or controlled collapse chip connection (C4) bumps. The external connectors464may comprise a material such as tin, or other suitable materials, such as silver or copper. In some embodiments, the external connectors464are tin solder bumps formed by any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shape. A protective layer466may be formed between the RDL structure456and the external connectors464. In some embodiments, the protective layer466may be formed from polyimide, or the like.

As shown inFIG.21, the substrate202in the dummy dies224and substrate412the first die406are bonded via the bonding film420, the bonding film208, the adjustment layer206, and the adhesive layer204. During operation, heat generated in the device layer414may dissipate from the substrate412to the substrate202via the bonding layers, i.e., the bonding film420, the bonding film208, the adjustment layer206, and the adhesive layer204. Because the adjustment layer206has improved thermal conductivity, the heat dissipation is improved. Additionally, the effective bonding length between the dummy dies224and the first die406also improves because the adjustment layer206is used to induce a warpage of the dummy dies224to improve bonding quality. Improved bonding quality further improves heat transfer between the dummy die224and the first die406.

FIG.22is a flow diagram illustrating a method500of forming of an integrated circuit package according to embodiments of the present disclosure.FIGS.23A-23D,24A-24C, and25schematically demonstrate various processing stages during fabrication of an IC package600using the method500.

The method500is similar to the method300except that the method500includes operations506and508in place of the operations306and308in the method300. In operation506, dummy conductors are formed in a first die. In operation508, dummy dies are bonded to the first die in areas of with the dummy conductors. The method500starts with the operations302and304. The corresponding phases may be depicted inFIGS.14and15.

In operation506, dummy conductors602are formed in the bonding film420in addition to the bond pad features422, as shown inFIGS.23A-23D.FIG.23Ais a schematic cross-sectional view of the IC package600after operation506.FIG.23Bis a plane view of the IC package600.FIGS.23C and23Dare partial sectional views showing a dummy conductor according to embodiments of the present disclosure.

The dummy conductors602are conductive features, such as vias or lines, formed in the bonding film420. The dummy conductors602are configured to further improve thermal conductivities between the first die406and the dummy die224.

Similar to the bond pad features422, the dummy conductors602are conductive features, lines and/or vias, formed in the bonding film420. As discussed above, at least a portion of the bond pad features422are connected to the TSVs424formed in the substrate412of the first die406. The bond pad features422are also intended to connect with conductors in the die to be bonded, such as the bond pad features444in the second die426. Unlike the bond pad features422, the dummy conductors602electrically float in the bonding film420. That is the dummy conductors602are not connected to any conductors in the first die406. The dummy conductors602are also not connected to any conductive features in the die to be bonded, such as the dummy die224.

The dummy conductors602may be formed of copper or other suitable metal. In some embodiments, the dummy conductors602may be formed by suitable fabrication techniques such as electroplating or deposition. The dummy conductors602may be formed by forming trenches and vias in the bonding film420and filling the trenches and vias in the bonding film420. In some embodiments, the dummy conductors602may be formed by a damascene process, such as a single damascene process or a dual-damascene process. In some embodiments, the dummy conductors602may be formed simultaneously with the bond pad features422.

After operation506, top surfaces of the of the dummy conductors602and the bond pad features422and a top surface of the bonding film420are substantially coplanar so as to provide an appropriate surface for the subsequent bonding. The planarity may be achieved, for example, through a planarization step such as a chemical mechanical polishing (CMP) step or a mechanical grinding step. After planarization, the first die406has a substantially planar bonding surface606bincluding areas of the bonding film420, areas of the bond pad features422, and areas of the dummy conductors602.

In some embodiments, the dummy conductors602may have a height H in the bonding film420. In some embodiments, the height H of the dummy conductors602may be in arrange between about 1 k angstroms to about 20 k angstroms. In some embodiments, the height H of the dummy conductors602may be substantially the same as the height of the bond pad features422.

In some embodiments, the height H of the dummy conductors602may be embedded in the bonding film420, as shown inFIG.23A. In other embodiments, the dummy conductors602may have the same thickness of the bonding film420so that the dummy conductors602is in contact with the back side410of the substrate412, as shown inFIG.23C. In other embodiments, the height H of the dummy conductors602may greater than the thickness of the bonding film420so that the dummy conductors602extends into the substrate412, as shown inFIG.23D.

FIG.23Bschematically demonstrates the distribution of the dummy conductors602in the bonding film420. As shown inFIG.23B, the dummy conductors602are arranged with areas of the bonding film420configured to receive dummy dies in the subsequent bonding.FIG.23Bis a schematic depiction of the dummy conductors602. The number, shape, and arrangement of the dummy conductors602may be arranged in any suitable manner. In some embodiments, a total surface area of dummy conductors602may be selected first. Shape and layout of the dummy conductors602may be determined to achieve to total surface area.

In some embodiments, the total areas of the dummy conductors602may be determined by a surface area of the dummy die to bond with. For example, a ratio of the total surface areas of the dummy conductors602to bond with a dummy die over a surface area of the dummy die may be in a range between about 0.03 and abut 0.3.

In other embodiments, the surface area of the first die406, i.e., the die on which the dummy conductors602are formed, may affect the total surface area of the dummy conductors602. For example, a ratio of the total surface areas of the dummy conductors602over the surface area of the first die406may be in a range between about 0.001 and abut 0.01.

In other embodiments, the surface area of the second die426, i.e., the non-dummy die to bond with the first die406, may also affect the total surface area of the dummy conductors602. For example, a ratio of the total surface areas of the dummy conductors602over the surface area of the second die426may be in a range between about 0.003 and abut 0.03.

The dummy conductors602may be any suitable shapes and in a suitable arrangement to achieve to total surface area. For example, the dummy conductors602may be conductive vias, having a diameter D in a range between about 0.01 mm and about 0.1 mm. In other embodiments, the dummy conductors602may be conductive lines having a width in a range between about 0.01 mm and about 0.1 mm and a length between about 1 mm and about 10 mm. In some embodiments, the dummy conductors602may have the same shape. In other embodiments, the dummy conductors602may be in a combination of shapes.

In some embodiments, the dummy conductors602may be distributed in one or more dummy areas604. Each dummy area604may have a shape similar to the dummy die224to be bonded thereon. The dummy area604may be slightly smaller than the surface area of the dummy die224so that a conductor-free band is formed around an edge of the dummy die224after bonding described in the operation508.

In operation508, the second die426and one or more dummy dies224are bonded to the first die406, as show inFIGS.24A-24C.FIG.24Ais a schematic cross-sectional view of the IC package600after operation508.FIG.24Bis a plane view of the IC package600.FIG.24Cis a partial plane view showing distribution of the dummy conductors602with relative to the dummy die224after bonding.

The first die406and the second die426may be bonded face-to-face by a D-D and M-M bonding process, as described above with the operation308. The dummy dies224are bonded to the first die406with the dummy conductors602in the bonding surface. The dummy dies224are positioned side-by-side with each other and with the second die426and over areas of the dummy conductors602. In some embodiments, the dummy dies224are fusion-bonded with the first die406. In some embodiments, the dummy dies224may be bonded by a low temperature heating process at a temperature range between about 100° C. and about 280° C. to strengthen the dielectric-to-dielectric bonding.

In some embodiments, the dummy dies224are aligned with and positioned over the corresponding dummy areas604so that a conductor-free band606is formed within an edge region of each dummy die224, as shown inFIG.24C. The conductor-free band606reduces non-bonding length near the edge region of the dummy die224, thus improving bonding quality. In some embodiments, the conductor-free band606may have a width BW in a range between about 1 mm and about 2 mm.

In some embodiments, bonding the dummy dies224to the first die406and bonding the second die426to the first die406may be performed in the same D-D and M-M bonding process. Alternatively, bonding the dummy dies224to the first die406and bonding the second die426to the first die406may be performed in separate bonding processes.

After the operation508, operations310,312,314, and316may be performed as described with the method300above.FIG.25is a schematic cross-sectional view of the IC package600after operation314.

As shown inFIG.25, the substrate202in the dummy dies224and substrate412the first die406are bonded via a film stack including the bonding film420with the dummy conductors602, the bonding film208, the adjustment layer206, and the adhesive layer204. During operation, heat generated in the device layer414may dissipate from the substrate412to the substrate202via the film stack. In addition to the material in the adjustment layer206, thermal conductivity of the film stack is further reduced by the presence of the dummy conductors602in the bonding film420.

Embodiments of the present disclosure provide a dummy die with an improved bonding structure. Particularly, the dummy die according to the present disclosure increases thermal conductivity through the dummy die, enhances warpage adjustment with a thinner film. Embodiments of the present disclosure further comprises dummy conductors to bond with the dummy die, which further increases thermal conductivity. Increased thermal conductivity leads to improved heat dissipation in IC packages according to the present disclosure.

Some embodiments of the present disclosure relate to a semiconductor package comprising: a first die having a first bonding film; a second die stacked over the first die and bonded to the first die via the first bonding film; and a dummy die stacked over the first die and bonded to the first die via the first bonding film, wherein dummy die comprises: a substrate; an adjustment layer formed over the substrate, wherein the adjustment layer has a thermal conductivity in a range between about 30 W/mK and about 100 W/mK; and a second bonding film formed over the adjustment layer, wherein the second bonding film is bonded to the first bonding film.

Some embodiments of the present disclosure relate to a method comprising: bonding a first die to a second die, wherein the first die comprises a first bonding film, and the second die is bonded to the first bonding film; and bonding a dummy die to the first die, wherein the dummy die comprises: a substrate; an adjustment layer formed over the substrate, wherein the adjustment layer has a thermal conductivity in a range between about 30 W/mK and about 100 W/mK; and a second bonding film formed over the adjustment layer, and the first bonding film is bonded to the second bonding film.

Some embodiments of the present disclosure relate to a method for forming dummy dies, comprises: depositing an adjustment layer on a front side of a semiconductor substrate; depositing a bonding film on the adjustment layer; forming a dicing pattern over the bonding film; etching through the bonding film, the adjustment layer, and into the semiconductor substrate using the dicing pattern to form dicing trenches; depositing a protection layer in the dicing trenches and on the bonding film; attaching a carrier wafer to the protection layer; and grinding the semiconductor substrate from a back side to expose the protection layer in the dicing trenches.