Wafer level burn-in using light as the stimulating signal

An apparatus comprises multiple light sources that are applied to specific locations on the surface of a wafer for the purpose of causing a component on a die to respond as if a digital signal had been applied to the component. The multiple light sources may comprise several thousand point light sources such as the individual fibers of a fiber optic bundle. The light is controlled in such a manner to stimulate operation of the electronic circuit for the purpose of burning in the circuit.

FIELD OF THE INVENTION

This invention relates to the burning in of integrated circuits, and specifically to the burning in of integrated circuits in wafer form using light as the stimulating signal to facilitate a current flow to particular components on the integrated circuit.

BACKGROUND OF THE INVENTION

Integrated circuits are subject to early failure, also referred to as infant mortality, which is caused by latent defects in the circuits. In particular, semiconductors that have a relatively large die size and use thin oxides are susceptible to infant mortality problems. For quality reasons, circuit manufactures desire to remove these early failure circuits, or die, from the product line prior to shipment to customers. In addition, circuit manufactures desire to remove these early failure die from the product line prior to placement of the die into multi-chip modules (CM) where a single failed die may result in failure and scrapping of the entire MCM.

The bulk of these early failures can be detected prior to shipment of the circuits by exercising the circuits at a high temperature and a working voltage to simulate actual use. Exercising the circuit includes applying power and sending data signals to the circuit to activate various portions of the circuit. For example, in the case of a memory circuit each of the memory cells are exercised by storing and retrieving data from each of the cells. When this exercise process is performed at a high temperature, the process is called burn-in.

To begin the conventional burn-in process, the individual die in wafer form are initially tested for minimal functionality for a short time and at ambient temperatures in a probe card station. This initial probe station test is run at a slow speed of approximately 5 MHz or less, due to possible interference problems. The test involves placing probes directly onto the pads of the die and then testing each of the die's components. The test may take approximately five seconds to three minutes per die, in addition to the relocation time of moving the probes from one die to another. Each of the die can be tested individually at the probe station because die in wafer form are not electrically connected to one another. Due to the short time period used to test each die, the die are tested sequentially until each die on the wafer has been classified as either good (pass) or bad (fail).

The good die are cut from the wafer and mounted in a package which is in turn mounted on a burn-in board. The die typically are permanently mounted in the package so that a die which fails final testing after the burn-in exercise will be discarded along with its package. A typical burn-in board includes space for multiple packages electrically connected to one another, for example, fifteen packages per board, so that the die on a single burn-in board can be exercised in parallel. Several burn-in boards are placed in a burn-in oven in an inert atmosphere for an extended period of time and exercised at a high temperature. In one example, 52 boards are exercised in a burn-in oven for 24 hours at a temperature of 125° C. The burn-in exercise is run at a speed of approximately 400 MHz to simulate actual working conditions. After the burn-in process, the die undergo a final test to eliminate those which have failed during burn-in. These failed die are removed from the product line.

Burn-in ovens may have a footprint of twelve square feet or more and may be over five feet tall. Accordingly, entire rooms or floors of fabrication facilities may be devoted to the burn-in process. Due to the long time frame and high temperature of the burn-in process, the energy usage is substantial. The process of placing the individual die in packages, placing the packages on the burn-in board, placing the burn-in boards in the burn-in ovens, and placing the packaged die in the final die tester is labor intensive.

The hardware used during the burn-in process is package specific. In other words, packages and burn-in boards for each specific type of die must be purchased. These costs can be enormous. In the case of multi-chip modules (CM), the package and burn-in board costs can be tenfold over the cost of single die packages and burn-in boards. These package and burn-in board costs continue to rise due to higher pin counts and specifications.

In one example, a wafer includes six hundred die. Each of the die are placed in a one-hundred-and-sixty pin package. Each package may cost $50 or more. The package is placed on a burn-in board that receives thirty-six packages per board and costs approximately $4,000. Seventeen boards are required to burn-in all the die from the single wafer. The cost of seventeen burn-in boards is approximately $68,000. The cost of six hundred packages is approximately $30,000. Moreover, the cost of the oven, energy usage, and labor must be added to these package and burn-in board costs.

Accordingly, manufactures are researching methods to simplify and minimize the cost of the burn-in process. Once method involves providing temporary packages for holding the die during the burn-in process. These temporary packages are expensive and have reliability questions surrounding their use. A substantial labor investment is still required in placing the die in these temporary packages. The energy usage of these temporary packages is generally similar to the requirements of the permanent packages.

A process that would allow wafer level burn-in exercising of individual die would eliminate the cost of packages and packaging labor for bad die, lower the cost of burn-in boards and allow more die to be placed in a single burn-in oven at one time. However, there are multiple obstacles to overcome in exercising die at the wafer level.

Each die has multiple signals that are required to control/exercise the die and multiple devices on each die that must be stimulated. Connection to a single die using electrical probes is common practice, as in the short duration, ambient temperature initial probe test mentioned above. However, the burn-in process takes a long period of time and is conducted at a high temperature and in an inert atmosphere. Accordingly, sequential wafer level burning in of the individual die on a wafer would not be time or cost efficient. If the electrical probe connection method were attempted for simultaneous wafer level burn-in for all die on the wafer, (using the same die example cited above) the probe card would require one-hundred-and-sixty pins times six-hundred die per wafer, or 96,000 probes. Each of these 96,000 probes must be aligned to connect to each of the corresponding die pads, without damaging the pads, to a tolerance of +/−0.001 inch, and must not drift out of this tolerance range during exercising of the circuit. Accordingly, the probes must not bend or bow due to temperature changes ranging from ambient to as much as 140° C. Each of these 96,000 connections must be made within the eight-inch diameter of the wafer. With so many electrical probes concentrated in such a small area, electrical noise and cross talk problems are inevitable. Wafer level burn-in using electrical probe connections does not appear to be feasible.

SUMMARY OF THE INVENTION

The method and apparatus of the invention facilitates burning in of integrated circuits in wafer form using light as the stimulating signal and using only a few electrical connections. The invention takes advantage of the circuit's normal sensitivity to light to facilitate flow of an electrical current to particular components on the die. The burn-in chamber of the present invention can be manufactured in a size of approximately one cubic foot, substantially reducing the floor space and energy requirements for the burn-in process.

The apparatus comprises multiple light sources that are applied to specific locations on the surface of the wafer for the purpose of causing a die to respond as if a digital signal had been applied to the circuit, or, in other words, for causing the circuit to respond as if it were an optical detector. In one example, the multiple light sources may comprise several million point light sources such as the individual fibers of a fiber optic bundle. The light is controlled in such a manner to communicate to intelligent devices on the die or to stimulate operation of the electronic circuitry of the die for the purpose of burn-in exercise signals. This apparatus and method of the present invention may also be used to test die for functionality.

The apparatus includes electrical power source and ground connections positioned on a probe card which are physically connected to the die using bump technology. In one embodiment a signal connection, also called a clock connection, is also physically connected to the die. The probe card includes multiple apertures for allowing light from a light source to impinge upon the die at predetermined locations. A fiber optical bundle is used to transmit light from the source to the probe card. The probe card may include optical markers for facilitating alignment of the probe card bump connections and the probe card light source apertures to corresponding predetermined locations on the die. Accordingly, the device allows for probe card alignment and exercising of the entire die by the use of only two or three mechanical connections and multiple, non-contact, optical connections.

Accordingly, it is an object of the present invention to provide a method and apparatus of burning in circuits in wafer form.

It is another object of the present invention to provide a method and apparatus of burning in circuits that is cost effective.

It is still another object of the present invention to provide a method and apparatus of burning in circuits that reduces the required number of physical connections to the die.

It is yet another object of the present invention to provide a method and apparatus of burning in circuits that reduces electrical noise and cross talk problems.

It is yet a further object of the present invention to provide a method and apparatus for optically aligning a probe card with a die.

It is another object of the present invention to provide a method and apparatus for powering on and off individual dies on a wafer.

These and other objects and advantages of the invention will become more fully apparent as the description that follows is read in conjunction with the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Turning now to the drawings, and initially toFIG. 1, a semiconductor wafer10has a diameter12of approximately eight inches and scribe lines14that delineate multiple individual integrated circuits16, also called die. The wafer shown includes forty-five identical die16but other numbers of die and other diameters of the wafer can also be used with the device and method of the present invention. In the wafer form shown, integrated circuits16are identical to but electrically isolated from one another.

FIG. 2shows a detailed view of an individual die16from the wafer of FIG.1. Die16includes a pattern of contact pads18and a pattern of optical regions20, also called optically sensitive devices, positioned around an edge region22of the die. The contact pads allow sending and retrieving of signals, via a physical probe attached to the pad (not shown), to and from individual components24positioned on an interior region26of the die. Optical regions20of the die comprise a set of diodes that are electrically connected to contact pads18and function to ensure that voltage applied at a contact pad, and transmitted to a component24, falls within a predetermined voltage range. Those skilled in the art will understand that, typically, each of contact pads18and optical regions20are connected to a corresponding component24but that only a few of the components are shown in the figure for ease of illustration. Contact pads18are used for testing of the die during the initial probe test described above. Contact pads18are also used for exercising the die during the conventional burn-in process described above wherein the electrical probes of a package are physically connected to the contact pads. Optical regions20, heretofore, have not been used as an input or an output region for stimulation signals during the burn-in process.

Still referring toFIG. 2, contact pads20include specific contact points for power, ground and signal connections. In particular, contact point28is connected to an outside power source in order to power the die. Contact point30is connected to an outside electrical ground. Die designed specifically for use with the present invention may also include a contact point32connected to an outside signal device, also called a clock, as will be described in more detail below. Contact point32generally will be positioned in edge region22but is shown in the center of die16for ease of illustration. These contact points are electrical/mechanical connections between the die and the outside world. The layout of the die demonstrates, generally, the proportional size of the contact points and optical regions to the total surface area of the die.

Optical regions34,36and38, respectively, are connected to enable, gate and write components. Optical regions40,42,44and46are connected to output components that may command their corresponding optical region to emit an optical signal on command, i.e., these optical regions will individually light up when instructed to do so by their corresponding component24. Optical regions34through46are used during the burn-in method of the present invention to verify that all of components24are being properly exercised. These optical regions are non-physical connections between the die and the outside world.

As an example, the component24connected to optical region40may be commanded to emit a “1” in which case optical region40will light up. This optical output of the region can be detected by a corresponding optical fiber strand(s) as will be described below. In this manner, testing as well as exercising of the components of the die can be verified in real-time during the burn-in process.

Die16may also include alignment pads48and50used to align a probe card on the die. In a preferred embodiment, pads48and50are optical regions that allow alignment of the probe card of the present invention using optical signals and a pattern recognition system that indicates to a controller when the optical signals are aligned with alignment pads48and50.

Those skilled in the art will understand that each of the optical regions shown on the die typically is electrically connected to a unique component positioned internally within the die wherein each component has a unique function. Using the device of the present invention, the component is exercised by sending a light signal to the corresponding optical region. The optical regions preferably are positioned in edge region22so that the interior components are not damaged during the exercising process and so that the optical regions can be easily located. However, the optical regions may be positioned at any location on the die, depending on the particular design of the die. Other numbers, sizes, and arrangements of optical regions, contact pads and alignment pads may also be used as is desired for a particular application.

FIG. 3illustrates schematically the relationship between several elements of die16and the fundamental principle of the present invention. In particular, optical region20is shown comprising two individual optical regions20aand20b, which are electrically connected to contact pad18. In the preferred embodiment, optical regions20aand20beach comprise an electrostatic discharge (ESD) protection diode. (Each of optical regions20shown inFIG. 2preferably will comprise two individual optical regions20aand20bas shown inFIG. 3.) If an input protection diode were found to be optically sensitive, or if the input protection diode were designed to be optically sensitive, these diodes would be an ideal optical region target of the present invention. Moreover, other nodes of die16could be designed with an optically sensitive component accessible for this technology.

Diode20ais connected to a power source through contact point28. Diode20bis connected to a ground through contact point30. Contact pad18and diodes20aand20bare each connected to component24which in turn typically is connected to other components24of die16. The orientation of diodes20aand20bensures, under typical operating conditions, that the voltage at component24is within the range of ground (zero volts) and the voltage of the power source, also called Vcc. If the voltage at contact pad18, or component24, is greater than the voltage of power source28, diode20abiases the current, i.e., allows the current to flow through diode20atoward source28, to lower the voltage at the contact pad to that of the voltage of power source28. If the voltage at contact pad18, or at component24, is less that ground, i.e., a negative voltage, diode20bbiases the current, i.e., allows the current to flow through diode20btoward contact pad18, to increase the voltage at the contact pad to that of a zero voltage.

For example, during the conventional burn-in process a probe is physically connected to contact pad18and a current is applied. If the current applied results in a voltage at the contact pad that is greater than Vcc, diode20awill bias the current to flow toward source28thereby drawing contact pad18toward the voltage of power source contact point28. If the current applied results in a voltage at the contact pad that is less than ground, diode20bwill bias the current to flow from ground30thereby drawing contact pad18toward the voltage of ground contact point30. If the current applied at contact pad18is within the range of zero volts to the voltage at Vcc, the diodes will not bias current and the current will flow into component24and cause component24to respond appropriately. In this manner, as known by those skilled in the art, direct physical/electrical contact with contact pad18allows exercising of component24during the burn-in process.

In contrast, the process and apparatus of the present invention allows exercising of component24during the burn-in process by the use of optical signals, and without the need for a direct physical/electrical connection to contact pad18. The device and method of the present invention utilizes the internal connections of optical regions20with power source Vcc, already built into the die. However, die16may be specifically designed to position optical regions20in easily accessible locations on the die or to incorporate other optical regions for additional testing or exercising of the die.

To exercise component24using the method and device of the present invention, an optical signal, i.e., a light beam, is applied to optically sensitive diode20awhich results in current leakage at diode20a. In other words, shining a light beam on diode20acauses the diode to allow current to flow from Vcc toward the component. A flow of current toward the component through diode20ais not typically permitted because diode20anormally only allows a current flow toward Vcc. The flow of current from Vcc through diode20acannot be stored in contact pad18(the contact pad typically has no capability to store a charge) and cannot flow toward ground30due to diode20b. (The optical illumination beam of the present invention, therefore, should stimulate only diode20aor20b, but not both diodes at the same time.) Accordingly, the current leakage of diode20awill result in a current flow from Vcc to component24, the same result as when current is applied via a physical connection at contact pad18.

In the alternative, if one desires to draw a current from component24, an optical signal, i.e., a light beam, is applied to optically sensitive diode20b(and not simultaneously to diode20a). This will result in current leakage at diode20bthereby biasing current from the component toward ground30. Accordingly, stimulating diode20bhas the same effect as physically drawing a current from contact pad18.

Drawing current through either of diodes20aor20bin the “leakage” direction, i.e., opposite to the normal biased orientation of the diode, will cause component24to respond appropriately, i.e., to respond in the same manner as during the conventional burn-in exercise mentioned above. A single electrical/mechanical connection on the die at Vcc contact pad28, therefore, allows each of components24of the die to be exercised, rather than requiring an electrical/mechanical connection at each contact point18. In this manner, the method and apparatus of the present invention allows exercising of components24during the burn-in process without requiring direct physical/electrical connection to contact pads18.

Eliminating the need for a direct physical/electrical connection to each of contact pads18on a die provides the following advantages: allows wafer level burn-in of multiple die because optical signal fibers can be placed in a tighter arrangement than electrical probes; reduces energy costs because wafer level burn-in ovens can be small in size; reduces labor costs because each of the die do not need to be placed in a package; reduces the possibility of damage to the die by reducing the number of physical/electrical connections to the die; reduces the chance of noise and cross-talk problems because fiber optic strands typically do not have “noise” problems; reduces the cost of the burn-in process because packaging is not required; allows for automated optical alignment of the mechanical connections of a probe card with a die using pattern recognition technology; and allows for the powering on and off of individual dies on a wafer using optically sensitive switches built into the probe card.

The current leakage phenomenon of the diodes of a die discussed above may be described as the die's “normal sensitivity to light”. For the apparatus and method of the present invention to function properly, diodes20aand20bshould be optically accessible on the die. Die16, therefore, preferably will be designed so that the diodes, or other possible optical regions20, will be optically accessible and positioned in known locations. The known location of optical regions20on die16may be programmed into a computer so that a computer controlled optical source may activate particular optical regions upon command during a burn-in exercise, as will be further described below. Placement of die16in a package will generally cover these optically sensitive features so that regions20cannot be accessed. Accordingly, the method and burn-in chamber of the present invention typically will be used with die in wafer form, i.e., die not mounted in individual packages.

FIG. 4shows a cross-section of a burn-in chamber60. The chamber may be manufactured having a diameter of approximately one foot and a height of approximately one foot so that the chamber is only one cubic foot in size. The size of the burn-in chamber generally will be determined by the diameter of the wafer processed in the chamber.

Burn-in chamber60includes a multi-source light chamber62, light control signals64, a multi-filter mask66, a light channel controller68, a fiber optic block70, electrical connections72, a membrane probe card74, a wafer (such as wafer10shown in FIG.1), a temperature control device76, a coolant connection78, and a heating device80. Of course, the particular arrangement and the particular elements are shown merely for illustrative purposes and other arrangements and elements may also be utilized in the device and method of the present invention.

In the preferred embodiment, multi-source light chamber62comprises a parabolic reflector82having a focal point84. A light source86emits a source light beam, or beams, at focal point84so that light is reflected by the parabolic walls of the chamber downwardly and perpendicularly to the uppermost surface of probe card74. Light source86may comprise one or multiple light bulbs that emit light at one or at multiple desired intensities. To achieve an increase in intensity, the wattage of the bulbs may be increased. The multiple light bulbs may also emit light at one of or at multiple wavelengths as desired. In another embodiment, light source86may comprise one or more lasers that emit, for example, red or green light, or light at other wavelengths, as desired. In another embodiment light source86may comprise a liquid crystal display panel thereby eliminating the need to light control signals64. Any light source may be used as is appropriate for the particular burn-in procedure being implemented. The use of multiple light emitters in light source86allows for control of the optical stimulation of a variety of particular optical regions on a die.

As an example, an optical switch may be connected to the power source of an individual die wherein the switch in the on position would allow power to the die during the entire burn-in process. It may be desirable to toggle on and off separate optical regions of the die during the burn-in process. Accordingly, green laser light may be used for stimulating the optical switch and appropriate filters activated and deactivated to allow red laser light to stimulate the separate optical regions only at desired times. The use of filters, therefore, together with the multiple light sources allows for precise control of multiple optical stimulation procedures on the individual components of die16.

Light control signals64may comprise a liquid crystal display (LCD) panel having an array of pixels measuring 1024 by 1024. Such a panel would comprise 1,048,576 individual pixels, each of which may be used to control individual fiber optic strands used to optically stimulate optical regions20on die16. (“Stimulation of optical regions20” refers to stimulation of either regions20aor20b.) An electrical connection is used to control signals64, such as communication signal patterns or control vectors. Of course, other sized LCD panels or other light control signal devices may be utilized.

Multi light filter mask66is a light source filter used to filter light submitted to controller68. The filter may comprise wavelength/color filters, such as red or green filters, that only allow the passage of a particular colored light when the filter is activated. Mask66may also comprise other standard optical filters such as polarizers, retarders, quarter-wave plates and the like used to control light received by the die. As discussed in the example above, filters66may be activated, i.e., turned on or off by the use of particular frequencies, and, in conjunction with multiple light sources86, allow light to continually stimulate an optical switch to continually provide power to the die, and to toggle on and off particular optical regions of the die during the burn-in process. In the case of a wavelength filter, as will be understood by those skilled in the art, the filter typically will allow the passage of a particular range of wavelengths or several particular ranges of wavelengths during specified time periods, as opposed to allowing only a single wavelength to pass.

Multi-filter mask66may also be used to facilitate fast exercise times to realistically simulate actual use of the component. For example, the LCD panel of light control signals64may only operate at a speed of 1 millisecond per cycle. Mask66may be activated for only a portion of this millisecond time frame. Accordingly, within the millisecond that a particular fiber optic strand92is illuminated by LCD panel64of chamber60, multi-filter mask66may be activated to allow light to pass to die16for only a portion of the millisecond time interval. In this manner, fast on/off cycle times may be achieved by using the relatively slow technology of an LCD panel in conjunction with a fast filter activated during the LCD illumination time period.

Light channel controller68typically comprises a computer88connected to light control signals64and is designed to control the light source pixels introduced to fiber optic block70. Controller68may be positioned external to chamber60and comprise a standard personal computer connected to light control signal device64by a standard eight pin connector interface. In this manner, as an example, computer88will control the activation of each of the 1,048,576 individual pixels of light control signals64, much the same way that a computer controls the individual pixels of a computer monitor. Those skilled in the art will understand that other light channel controllers may also be utilized.

Still referring toFIG. 4, and further referring toFIG. 5, fiber optic block70typically comprises a fiber optic bundle90including several million individual fiber optic strands92tightly sandwiched together and extending between light channel controller68and membrane probe card74. Preferably, no diffraction takes place within the strands of the fiber optic bundle. Each strand92typically has a diameter of {fraction (1/1000)}ths of an inch, whereas optical regions20(FIGS. 2 and 3) typically have a diameter of approximately 28 mils. Accordingly, several adjacent strands92typically are activated by controller68when a particular optical region20is to be optically stimulated by light transmitted through strands92.

Bundle90preferably is coherent meaning that a cross section94of a particular strand92will be positioned in the same location at an input end96and at an output end98of bundle90. In the embodiment shown, individual fiber optic strands92are densely packed so that bundle90extends across the entire diameter of chamber60and, therefore, across the entire diameter12of wafer10.

Individual strands of bundle90aligned with optical regions20of a die will be activated by controller68and LCD panel64during the burn-in process so as to stimulate optical regions20aligned with the particular strands. Individual strands unaligned with individual optical regions20will merely provide support and stability to the neighboring strands that are activated. Accordingly, fiber optic bundle90is scalable for burning in any sized wafer because the million or so stands of the bundle can be individually activated to apply a light beam to any location on the particular die. In other words, bundle90can be used for the stimulation of die having a variety of optical region locations, so long as the predetermined location of each of optical regions20is stored in the memory of controller68, or in another such storage device. Moreover, the individual strands of bundle90may be sized to any desired diameter, or provided in other shapes, so that the device is scalable for burning in die having any size optical regions20. The ability to control light emitted to individual strands in bundle90ensures that light is only presented to intended targets on the wafer.

Fiber optic block70typically is positioned approximately two inches above wafer10to prevent heat damage to the fiber optic strands from the wafer, which may reach temperatures during the burn-in process of approximately 125° C. or more. Moreover, fiber optic block70insulates the LCD panel from the high temperatures required for circuit burn-in.

In another embodiment, individual fiber optic strands92are flexible and not tightly packed so that each individual strand may be positioned in line with a particular optical region20on a die16. However, this embodiment would likely eliminate the scalability and universal use of the upper components of chamber60.

Electrical connections72include power, ground and signal connections to membrane probe card74. The signal connections may be connected to pattern generators for generating electrical contact signals. The connections typically include simple electrical wiring but other connections may also be used.

Still referring toFIG. 4, membrane probe card74comprises multiple layers as will be described below, wherein the uppermost layer typically is connected to electrical connections72. Probe card74is positioned directly above and is in contact with portions of wafer10across diameter12. The probe card includes several physical/electrical connections to each die16on wafer10. The probe card also includes optical switches associated with each die that are used to turn the individual die on or off. The description of the probe card with respect toFIGS. 6 through 13will illustrate how apertures can be used to access light sensitive locations on the semiconductor die and how electrical contact can be made for power connections to each individual die using bump technology.

Temperature control device76typically comprises a thermostat100connected to an anodized aluminum plate102via a computer, wherein the plate is in direct contact with wafer10. The plate serves as a support for the wafer and allows the application of heat to, or the dissipation of heat from, the wafer. During the burn-in process, the wafer is initially heated to an extreme temperature, such as 125° C., by the conduction of heat from heating device80, through plate76and to wafer10. Once the wafer is heated to this temperature, the individual components on each of the die of the wafer are exercised at a high speed. This produces excess heat on the wafer that should be dissipated to avoid damage to the die. At this point in the burn-in process, heating device80ceases to provide heat to plate76and coolant is run through the device at coolant connection78. Heat is then conducted from the wafer, through plate76and out of the system by coolant connection78. In this manner, wafer10is held within a desirable temperature range during the entire burn-in process.

Plate76preferably is anodized so that the electrical integrity of the wafer will not be compromised by contact with the aluminum plate. In the preferred embodiment, plate76can dissipate as much as 5000 watts of heat from the wafer during the burn-in process. Those skilled in the art will understand that other temperature controllers may also be used.

Coolant connection78is connected to temperature control device76and typically comprises piping that extends through plate102wherein a cooling gas or liquid is fed through the piping, as known in the art. Of course, other cooling devices may also be used to dissipate heat from wafer10during the burn-in process.

Heating device80may comprise a resistive heating coil, a ceramic heater, a moving gas or liquid heat exchanger system, or any other heating device sufficient for purposes of the present invention. Heating device80typically is in direct contact with aluminum plate102so as to allow direct heat conduction to the wafer through plate102from device80.

FIG. 6shows a side view of a section of probe card74and a die16. The section shown typically is in an edge region of probe card74and includes three mechanical connections to the top of the probe card. In the preferred embodiment, probe card74extends across the full diameter12of wafer10so that a single probe card is used for simultaneously powering on and off all the die on the wafer during simultaneous burn-in of each die on the wafer.

In a preferred embodiment, probe card74includes a power source layer110, an insulation layer112, a signal layer114, also called clock layer114, an insulation layer116, and a ground layer118. Insulation layers112and116electrically isolate the layers on either side of the particular insulation layer, as will be understood by those skilled in the art. In one embodiment the insulation layers are manufactured of velum but any insulating material suitable to electrically insulate the source, signal and ground layers may be used. In one embodiment the power, signal and ground layers are manufactured of a metallic substance such as gold. Any other electrically conductive material, or combination of materials, may also be used.

Power source layer110includes a switch120movable between the on (closed) and the off (open) positions so as to control power to the entire probe card. In the preferred embodiment, switch120is an optical switch that moves between the open and the closed positions when a light signal is applied to the switch. Switch120is directly connected to layer110and extends through the entire depth of layer110so that the remainder of layer110is only powered when switch120is in the on position. Accordingly, switch120is the main control switch for simultaneously providing power to all the die on wafer10.

A second switch121allows isolation or powering (when switch120provides power to layer110) of a single die. In other words, a switch121is associated with each individual die whereas only one switch120is positioned on the probe card. Utilizing switch121to isolate an individual die reduces the problem of one die shorting out the power to all other die on the wafer when all the die are electrically tested in parallel.

Switch121is aligned with an electrical lead122, also called a “via”, that extends through layers112,114,116, and118. Lead122contacts layer110through switch121and terminates in an electrically conductive bump124positioned on an underside of layer118. Bump124is mechanically connected to contact pad28of die16during the burn-in process so that a particular die is powered by the probe card through via122. Lead122is electrically isolated from signal layer114by an isolation barrier126and is electrically isolated from ground layer118by an isolation barrier128. Barrier128also electrically isolates bump124from ground layer118. Lead122is electrically connected to metallic power source layer110through switch121so that an individual die on wafer10is electrically connected in parallel to the power source only when its corresponding switch121is in the on position.

Signal layer114is electrically connected to an electrically conductive bump130by an electrical lead132that extends from a signal switch134. Lead132is electrically isolated from ground layer118by an isolation barrier136and switch134is electrically isolated from power source layer110by an isolation barrier138. Barrier136also electrically isolates bump130from ground layer118. Bumps124and130, and leads122and132are manufactured of an electrically conductive material, such as gold, though other materials may be used. Those skilled in the art will understand that the isolation barriers surround the electrical leads but generally do not extend through the entire cross section of the probe card layer. Lead132is electrically connected to metallic signal source layer114so that each of the die on wafer10is electrically connected in parallel to the signal layers providing for simultaneous electrical connection of all the die on the wafer to signal layer114.

Ground layer118is directly connected to the die by an electrically conductive bump140. A lead142connects bump140to an electrical ground connection144through isolation barriers146and148. The probe card of the present invention, therefore, mechanically contacts an individual die at three electrical connection points124,130and140. The probe card is also connected to the outside world, i.e., a power source, a ground, and a signal clock, at three points120,134and144.

For the wafer shown inFIG. 1, which has 45 individual die positioned thereon, probe card74will include 135 electrically conductive bumps. The remainder of the “connections” to the wafer will be optical connections, as will be described below in more detail. The probe card, however, will have only three outside contact points, i.e.,120,134and144, on an upper side of layer110. Other locations of the three outside contact points, such as a connection to the side of the probe card, may also be used.

FIG. 7shows a cross section of another embodiment158of a probe card having only three layers. Prove card158includes power source layer110, insulation layer112, and ground layer118. Switch121is connected to electrically conductive bump124by electrical lead122. Isolation barrier128insulates lead122from ground layer118. Electrical lead142is isolated from power source layer110by isolation barrier146. This three-layer system provides for burning in of a die with only two mechanical connections to each die, i.e., bumps124and140.

This three-layer embodiment is used in the device and method of the present invention when relatively slow electrical speeds, such as speeds slower than 2 MHz are required for exercising each component. For example, LCD panel64is capable of changing the activation of individual pixels at a speed of approximately only one millisecond per on/off cycle. However, stimulation of a particular component24on die16may be desired at much faster speeds. The speed of many currently available die is 400 MHz or faster. Accordingly, when faster electrical speeds are desired, such as faster than one millisecond, the probe card ofFIG. 5, having signal layer114with physical connection at bump130, is preferred because the contact pad18of a particular component can be contacted at bump130.

FIG. 8shows another cross-section of probe card74shown in FIG.6. In this cross sectional view, layers110,114and118are electrically connected to and in parallel with corresponding contact points124,130and140aligned with a particular die, through the continuous layers of the cross-section shown in FIG.6. Accordingly, leads122and132need only extend upwardly to the desired layer of the probe card. In particular, bump124, via lead122, is electrically connected to power source layer110through switch121and is isolated by barriers126and128. Bump130, via lead132, is electrically connected to signal layer114and is isolated by barrier136. Bump140is directly electrically connected to ground layer118. Contact points124,130and140are different from, and are aligned with a die that is different from, the die shown in FIG.6. In other words, probe card74includes multiple sets of three contact points124,130and140, wherein each set of contact bumps is aligned with a set of three corresponding contacts pads of a die.

FIG. 9shows another cross-section of probe card158shown in FIG.7. In this cross sectional view, layers110and118are electrically connected to and in parallel with corresponding contact points124and140, through the continuous layers of the cross-section shown in FIG.6. Accordingly, lead122need only extend upwardly to the desired layer of the probe card. In particular, bump124, via lead122, is electrically connected to power source layer110and is isolated by barrier128. Bump140is directly electrically connected to ground layer118.

FIG. 10shows a plan view of the entire probe card74. The probe card includes the three mechanical connections120,134and144, positioned in an edge region of the probe card, and switches121aligned with each individual die (switches121are shown on only a few selected dies in FIG.10).

FIG. 11shows a plan view of power source layer110of probe card74, in the portion of the probe card shown in FIG.6. Power source layer110includes multiple apertures160that extend through layer110so as to allow the passage of a beam of light from fiber optic bundle90through selected apertures of the probe card. Some of the apertures are filled with conductive material to produce the electrical leads that extend through the probe card. Apertures160preferably are arranged on layer110so as to correspond to the position of optical regions20of die16, shown inFIG. 2, so that light passing through apertures160will impinge upon a particular optical region20. In a preferred embodiment, apertures160are created by layer technology including multiple deposition and etching steps. In one embodiment, apertures160have a diameter of approximately {fraction (3/1000)}ths to {fraction (4/1000)}ths of an inch. Other diameters will be appropriate for other particular die configurations. The apertures may also be drilled by mechanical or laser technology and typically will have a circular cross section.

For use with a particular designed die, probe card74, including power source layer110, will have apertures positioned in alignment with the optical regions of the particular die being burned in. Accordingly, those skilled in the art will understand that other sizes, shapes, numbers and arrangements of apertures will be utilized depending on the particular size, shape, number and arrangement of optical regions on the die being burned in. The apertures preferably have a size corresponding to the size of optical regions20on die16to reduce interference problems and to facilitate precise alignment of a beam of light passing through the aperture with the corresponding die optical region. Accordingly, several of individual fiber optic strands92may be activated to emit a light beam through a single aperture160having a corresponding sized diameter.

In particular, an aperture161is positioned adjacent to a power source input lead188for the formation of switch120within layer110. An aperture162is aligned with power source contact point28of the die and is filled with conductive material to create lead122, used for connection of power source layer110to the die. An aperture164is aligned with ground contact point30on the die. The aperture is filled with conductive material to create lead142for connection of a ground to bump140of the probe card. The aperture is positioned adjacent a ground lead wire190and is connected thereto by ground connection144. An aperture166is aligned with signal contact point32on the die. The aperture is filled with conductive material to create lead132for connection of signal switch134to bump130.

Apertures168,170and172, respectively, allow a light beam to stimulate enable, gate and write optical regions34,36and38(see FIG.2), respectively. Apertures174,176,178and180each allow a light beam to stimulate or receive optical output from output regions40,42,44and46, respectively. Apertures182and184allow a light beam to track the position of alignment pads48and50to align the probe card on the die.

The portion of probe card74shown inFIG. 11includes optical switch120for simultaneously powering on and off all the die on the wafer, switch121for powering on and off a particular die, signal switch134for passing an electrical signal directly to a particular contact pad on each die of the wafer, and ground contact connection pad144for connecting each die to the ground. (Switches120,121, and134are shown schematically.)

In a preferred embodiment, optical switch120includes an optical region186and switch121comprises an optical region at the uppermost portion of lead122. The optical regions facilitate movement of the switches from the on (closed) to the off (open) position when the regions receive light at a particular intensity or wavelength.

For example, switch120may be activated by green light whereas switch121may be activated by red light. Mask66in the burn-in chamber may include a green filter that is continuously activated so as to allow the continuous passage of green light. The continuous green light may be used to continuously activate switch120to allow power to each die on the wafer. When the green filter is not activated, none of the die on the wafer will be powered. Mask66may include a red filter that is intermittently activated, or activated only in predetermined locations above the die, so as to allow red light to pass only when and where the red filter is activated. Activation of red light to particular switches121will allow power to each of die16that correspond to the activated switches (when switch120is also in the on position). Switches121allow control of individual die so that a shorted die may be electrically disconnected from the remainder of the good die being tested. Switches120and121may comprise any optical switch known in the art. Moreover, mask66may comprise other methods of control of the light impinging upon switches120and121.

Signal switch134is mechanically connected to a controller for exercising a particular component24on the die at a high speed. Switch134is electrically isolated from power source probe card layer110by isolation barrier138. As stated earlier, the on/off capability of an LCD panel is generally limited to a one millisecond per on/off illumination response time. Faster exercise times, i.e., shorter exercise time periods, such as 2 MHz or faster typically are desired. Accordingly, the mechanical connection of switch134to die16allows a single component to be exercised at a high speed by use of the mechanical connection.

Ground contact connection pad144electrically connects ground lead wire190to electrical lead142. Lead142is comprised of aperture164which has been filled with conductive material. Connection pad144is electrically isolated from power source probe card layer110by isolation barrier146.

FIG. 12shows a plan view of signal layer114of probe card74, in the portion of the probe card shown in FIG.6. Signal layer114includes electrical lead122, created by the filling of aperture162with conductive material, surrounded by isolation barrier126. Electrical lead132, created by the filling of aperture166with conductive material, is electrically connected to layer114. Electrical lead142, created by the filling of aperture164with conductive material, is surrounded by isolation barrier148.

FIG. 13shows a plan view of ground layer118of probe card74, in the portion of the probe card shown in FIG.6. Ground layer118includes electrical lead122, created by the filling of aperture162with conductive material, surrounded by isolation barrier128. Electrical lead132, created by the filling of aperture166with conductive material, is surrounded by isolation barrier136. Electrical lead142, created by the filling of aperture164with conductive material, is electrically connected to layer118.

FIG. 14schematically shows use of the invention to optically stimulate a die16so as to produce a current at a particular component on the die. Particular stands92of fiber optic bundle90are aligned with a particular aperture160of probe card74. Strands92are illuminated to produce a beam of light192that travels through aperture160and impinges upon optical region20. (The optical region is shown raised above the upper surface of die16for purposes of illustration.) Another set of optical strands92is aligned with and stimulates switch121with a beam of light194so that the switch will allow power to the individual die shown.

Stimulation of optical region20is understood to mean stimulation of either of optical sub-regions20aor20b. Optical stimulation of region20results in leakage of the diode positioned at optical region20. This leakage of the diode results in a flow of current196from power source Vcc through power source layer110and switch121, electrical lead122, bump124, contact pad28, and through internal die electrical connection198, to component24. After component24had been activated for a sufficient time period, mask66deactivates switch121, or deactivates illumination though aperture160, so that current no longer flows to component24. Multiple components24are connected to single power source contact pad28so that only one physical/electrical connection to the die is required to individually exercise each component on the die.

Accordingly, the present invention comprises burn-in chamber60wherein only the probe card need be changed for the burning in a particular die. In other words, probe card74is manufactured so that apertures160in the probe card will be aligned with optical regions20on a die. For each different die, a different probe card will be manufactured. However, the remainder of burn-in chamber60is not die specific because the illumination of each optical fiber strand92, and the duration of that illumination, can be controlled via computer programs and appropriate filters and light sources. Accordingly, the burn-in chamber of the present invention facilitates the burning-in of die at the wafer level, without requiring packages or burn-in boards.

Thus, a method and apparatus for wafer level burn-in of die has been disclosed. Although the preferred apparatus and method for performing burn-in has been disclosed, it should be appreciated that further variations and modifications may be made thereto without departing from the scope of the invention as defined in the appended claims.