FIFO interface for flag-initiated DMA frame synchro-burst operation

The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is control of data transfers in a digital signal processor.

BACKGROUND OF THE INVENTION

Digital signal processors (DSP) are often connected to external FIFO memory at an expansion bus interface or external memory interface. The expansion bus interface uses direct memory access (DMA) to link the digital signal processor core and its peripheral devices to the expansion bus. Synchronous first-in-first-out (FIFO) devices with deep pipelines enable burst transfer of large amounts of data in the form of frames in rapid succession over many clock cycles. The term synchronous FIFO implies that the FIFO read or write accesses are synchronous to the read or write clock, respectively. Clocks are both locked in time to the system clock. The term synchronization event refers to an event, generated by the FIFO which causes the DSP/DMA controller to read (or write) a given or known amount of data. For this discussion, the synchronization event is closely related to the activation of a FIFO status flags. These FIFO status flags may include Almost Empty (PAE), Almost Full (PAF), Half Full (HF). These operations can be carried out only with full synchronism between the DSP and the FIFO.

FIG. 1illustrates a pair of conventional synchronous FIFOs101and102connected to the expansion bus100of a conventional DSP. FIFO101permits the expansion bus to read in external data. FIFO102permits the expansion bus to write data out to external devices. The expansion bus100is normally only one of many peripheral interface devices connected to the direct memory access (DMA) within the DSP via a DMA control bus and a DNA data bus. The expansion bus clock XPCLK103is derived from DSP system clock and drives both the read clock of FIFO101and the write clock of FIFO102. Data flows to the expansion bus port XD(N:0)117from FIFO101Q(N:0) output105via I/O path104. Data flows to the D(N:0) input106of FIFO102from expansion bus port XD(N:0)117via I/O path104. FIFO flagsPAE111(almost empty flag) andPAF112(almost full flag) are two of the possible flags that may be used to signal the INTx109and INTy110expansion bus inputs is possible. Expansion bus enable signals107(XCEx,XOE,XOEandXOE) drive the enable logic108configured to control the FIFO enables as required. FIFO101inputs data on D(N:0) input115as timed by write clock113. FIFO102output data on Q(N:0) output116as timed by read clock114.

FIFOs101and102are typically used in one of three modes. In the first mode, the system reads from or writes to the FIFO at a fixed rate without regard for the FIFO flags. The inbound and outbound rates from a given FIFO are matched such that overflow or underflow does not normally occur. In the event that an overflow or underflow does occur there is generally a recovery mechanism provided by the system. In some cases there is no need for recovery mechanism because data loss is acceptable. In the second mode, the system is tightly coupled to the FIFO and is able to halt accesses to the FIFO based on the status of the empty flag for a read or the full flag for a write. In the third mode, a system is loosely coupled to the FIFO and performs a burst transfer based on the status of one of the intermediate flags. Among these flags are half full, almost full, or almost empty. The almost full and almost empty flags are typically user defined by the value stored in an offset register in programmable FIFOs. The length of the burst will typically match the offset defined by the given flag. This burst transfer mode of operation of mode3is of prime interest here.

Flag Triggered Burst Synchronization in DSPS Without Synchronization Control

Consider the case of a digital signal processor with read bursts triggered when the half full flag HF switches to an active high state. When the HF flag switches from low to high, the digital signal processor initiates a read burst from the FIFO of length HF, which is half the FIFO depth. In digital signal processors without frame synchronization control, having synchronization events triggered from programmable FIFO flags such as HF is likely to produce problematical conditions. There are two separate problem conditions for a read burst. A similar analysis shows that the counterpart of these two scenarios can occur for write bursts to the FIFO.

The first problem occurs as follows. Assume the FIFO is 1024 words deep and the HF Flag is set to become active at 512 words occupancy. Assume further that bursts are set to occur in 512 word increments. This means that a burst read by the digital signal processor from the FIFO is initiated when the FIFO HF Flag transitions to the active state and signals that the FIFO contains 512 or more words. In general, the read and write side for the FIFO do not have to both operate in the same use model as defined above. It will be typical for the digital signal processor side of the FIFO to operate in mode3, while the other side operates in mode1or2. A write burst into the FIFO from an external source is initiated when the HF Flag transitions to the inactive state signaling that the FIFO contains less than 512 words. If the write operation proceeds faster than the read operation, it is possible to have two sequential write bursts without having a full read burst between them. Without the full read burst in between these two write bursts, the FIFO then gets locked into a state where more than 512 words are stored and no read burst request initiated from the HF Flag can occur.

The second problem occurs as follows. Assume the FIFO is 1024 words deep and the HF Flag is inactive initially with the FIFO storing one less than 512 words occupancy. Assume again that bursts are set to occur in 512 word increments. In this scenario a burst read by the digital signal processor from the FIFO is initiated when the FIFO HF Flag transitions to the active state and signals that the FIFO contains 512 or more words. It also means that a write burst into the FIFO from an external source is initiated when the HF Flag transitions to the inactive state signaling that the FIFO contains less than 512 words. Combinations of alternating single word writes with single word reads can cause spurious events to be generated. This means that a succession of two burst reads by the DSP from the FIFO can be initiated without an intervening write burst and an underflow results.

These two scenarios indicate that triggering a synchronization event in the digital signal processor from a FIFO flag such as half full flag HF is subject to possible malfunction. In general the risk is incurred when bursts are interrupted before completion. Thus if the read burst is interleaved in time with a write burst in process, or conversely if the write burst is interleaved in time with a read burst in process, problems can arise. The normal practice to avoid this is to force the direct memory access unit to ignore events requesting service during a current frame transfer. For example, for a typical data transfer the beginning of which was synchronized by detecting an active. almost full flagPAF112during a DSP burst read from a FIFO, the FIFO resets thePAFflag112to the inactive high state after the first piece of data was read. If thePAFflag112were to stay inactive during the burst, this would indicate that the data source is permitted to write additional data to the FIFO before the direct memory access unit completes reading the burst frame.

In an example of a direct memory access unit controlled solution, after a frame is completed, the direct memory access unit waits an additional n-clock cycles before checking to determine if the flag is still active. This is merely to account for any synchronization delays within the FIFO between when an access occurs and when the flag is updated. If it is still active, the next frame will be synchronized based on the fact that the flag is still active. This delay is needed to give the external FIFO time to update its flags and give thePAFflag112time to propagate through the internal registers before being registered inside the direct memory access unit. For example, a FIFO typically takes approximately one to three FIFO clock cycles to update itsPAFflag112externally.

In addition, the direct memory access unit must mask spurious transitions on the flag input while the transfer is in progress, and wait n-additional cycles before reevaluating the flag. The difficulties relating to generation of spurious transitions on the flag output is one that relates equally to the use of any of the available flags in a conventional FIFO.

FIG. 2illustrates the timing relationships between a flag input to the digital signal processor, the generation of a direct memory access synchronization event, and the direct memory access frame. The EXT_INTl signal201is triggered, for example, by almost full signalPAF112or almost emptyPAEsignal111from a FIFO. (see111and112ofFIG. 1). Further recognition of interrupts generating a DMA_Synch_Event signal202are ignored until the DMA_Frame203completes at time205.

The transition of Flag_Input_to_EXT_INTl signal201from high to low while a burst is not in progress triggers direct memory access synchronizing event202.

The negative edge of Flag_Input_to_EXT_INTl signal201triggers a frame transfer on signal DMA_Frame203. This gates off DMA_Synch_Event signal at time202. During the synchronization event, the transition on Flag_Input_to_EXT_INTl signal201at time204is ignored.

After a read burst completes internally at time205, a delay of n-clock cycles211is inserted before another DAM_Synch_Event signal at time206checks whether Flag_Input_to_EXT_INTl signal201is active at time207.

Because Flag_Input_to_EXT_INTl signal201is still active at time207after the burst and delay, the new DMA_Synch_Event at time206is registered inside the direct memory access unit.

The new direct memory access synchronization event triggers another DMA_Frame burst at time208.

FIG. 3illustrates a conventional FIFO device used in pairs (as inFIG. 1) for data transfer to and from the digital signal processor via the expansion bus. The FIFO includes RAM array300configured to accept data from WData input301via input register302and pass data to output register303and read output port304. Synchronous read control logic306and write control logic307accept respective read clock309and write clock310from a common source at the expansion bus XFCLK clock output (103inFIG. 1). Read pointer313and write pointer314collectively track the respective placements of read and write data handled by the FIFO. The pointers provide information for generation of flags and status in the status flag logic316. A number of possible flags can be generated, such as: almost emptyPAEflag111; almost fullPAFflag112; and half full HF flag118/119.

SUMMARY OF THE INVENTION

The invention is a modification of conventional FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications described make the FIFO-DMA interface are immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to provide the digital signal processor a means for synchronized frame transfer functionality even if it is not implemented by the digital signal processor. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The FIFO device described in this invention has modified timing logic within the status flag logic block and modified burst control signal behavior. In this manner the FIFO-DSP interface is made immune to deadlock conditions and generation of spurious interrupt events in FIFO flag initiated bursts.FIG. 4illustrates the waveforms of the synchronized burst mode implemented in the FIFO of this invention. With the modifications described a synchronous FIFO can interface properly with the digital signal processor in flag-initiated frame transfer functionality even if the digital signal processor does not already have a synchronous interface.

WhileFIG. 4illustrates the concept of the invention for modification of the almost full flagPAF412to be supplanted by the advanced almost full flagADVPAF422, the principles are easily extended to modify the operation of almost empty flagPAE111(FIG. 1) to become the advanced almost empty flagADVPAE(not shown inFIG. 4) or the half full flagHF(118and119ofFIG. 1) to become the advanced half full flagADVHF(not shown inFIG. 4). Further extension to empty flags and full flags also is straightforward. Under normal non-burst FIFO operations, thePAFalmost full flag (pin112ofFIG. 1) functions as it would in the many conventional FIFO devices. That is, thePAFflag112is synchronized to WCLK or RCLK, (represented by CLK400inFIG. 4) if thePAFflag112is programmed as synchronous.

If theADVpin426(FIGS. 4 and 5) is a static signal asserted active low as noted inFIG. 4, the signalPAF412operation will be supplanted as seen in theADVPAFwaveform422illustrated inFIG. 4. The frame size value Frame_Size421may reside in a status register in the digital signal processor and ENDFRM416(bothFIGS. 4 and 5) is provided by the digital signal processor to end the burst. Alternatively, the Frame_Size421can be provided to the FIFO during a reset either serially or in parallel through WData port301(FIG. 3), much like the programmable flag offset values are programmed during a reset. If the Frame_Size421is programmed into the FIFO during reset, the FIFO will generate internally both a signal STARTFRM415and a signal ENDFRM416.ADVPAF422will be synchronized to one of the clocks, either WCLK or RCLK, depending on the programmable flag timing mode. The sequence of events for a burst mode cycle is illustrated inFIG. 4as follows.

For Advanced ModeADV=0

Once theADVpin426is set low (advanced mode), bothADVPAF422andPAF412go low at the same time401, asPAF412would have gone low in the non-advanced mode (whenADV=1). STARTFRM415is generated at402. WhenADVPAF422goes low at time404it triggers a DMA_Synch_Event403in the digital signal processor and the signal DMA_Frame424internal to the FIFO is asserted high at time409. After the DMA Frame is completed as indicated by pulse407in ENDFRM416, theADVPAFpin422returns high at time408on the positive edge of the clock co-incident with the trailing edge of ENDFRM416at time417. Note that during the DMA Frame interval421PAF412toggles once at times405,410, but there is no response in theADVPAFsignal422since the DMA_Frame424is still active during interval defined by421.

The end of DMA_Frame signal424occurs at the rising edge of ENDFRM416at time407. In one embodiment of the invention ENDFRM416is added as an additional FIFO pin that can receive a pulse from the digital signal processor signaling the end of the frame burst. In the alternate embodiment the generation of ENDFRM416is handled by the FIFO (no ENDFRM pin) and the pulse427in ENDFRM416will be internal to the FIFO. This causes the DMA_Frame signal424in the FIFO to be de-asserted at time419. After the completion of DMA_Frame signal424, n-clocks428are appended to the DMA_Frame cycle during which time no new cycles may begin.

On a later rising edge411of the clock400, STARTFRM415is once again generated at time420.ADVPAF422andPAF412are again asserted low since theADV426is low. This causes another DMA_Frame signal424to become active. WhenADVPAF422goes low at time414it triggers a DMA_Synch_Event423in the digital signal processor at time413and the DMA_Frame signal424internal to the FIFO is asserted high at time429. After DMA_Frame signal424completes, theADVPAFpin422returns high at time418on the positive edge of the clock co-incident with the trailing edge of ENDFRM416at time437.

The frame size and word counting can be handled one of two ways. First, the digital signal processor can handle frame size and word count using a status register. At the end of the direct memory access frame and the subsequent n-CPU clocks required by the digital signal processor, the digital signal processor could assert a pulse on the ENDFRM416of the FIFO signaling the end of a direct memory access frame in the FIFO. Second, the frame size plus the associated n-CPU clock equivalents could be passed either serially or parallel to the FIFO during reset. The default frame size value is preferably four words. The frame size is stored in a register in the FIFO and placed in a counter at the beginning of a direct memory access frame event. Once the counter decrements to 0 and becomes empty it would signal the end of the direct memory access frame and allow theADVPAFpin422to be asserted if the other conditions are correct.

FIG. 5is an illustration of the DSP-FIFO interface similar to block diagram ofFIG. 1as modified to incorporate the added signals ENDFRM416andADV426. These signals are needed to incorporate the functionality described to provide flexible control over the frame transfer operation. Statically setting the signalADV426to an active low state changes the timing on the signal511to conform to the timing ofADVPAF422.ADVPAFsignal511supplies INTx input509of external bus100. Similarly, for a digital signal processor performing write bursts to a FIFO102the identical signals ENDFRM416andADV426allow the digital signal processor write FIFO102to generate an analogous signalADVPAE512for write burst operation.ADVPAEsignal512supplies INTy input510of external bus100.

FIG. 6illustrates the status flag logic a portion of the FIFO block diagram (316ofFIG. 3), showing the additional signals ENDFRM416andADV426input to the status flag logic block616. Four blocks internal to the status flag logic are illustrated. The frame size register601holds the value of the frame size programmed into the FIFO during the reset operation. When the FIFO operates from the programmed frame size value the frame size counter602is used to count words transferred during a frame. The flag generation logic603keys off the completion cycle in the frame size counter602and the inputs from the flag input logic604to generate the flagsADVPAF425,ADVPAE512, andADVHF609. This option, the second embodiment of the invention allows for the digital signal processor to program the FIFO during the reset cycle passing the frame size and word count information to the FIFO via the offset registers320. This allows the FIFO to generate on command the modified flag signals signal on its own without the otherwise required ENDFRM416andADV426input signals.