System and method to utilize a composite block of data during compression of data blocks of fixed size

An information handling system includes a processor that detects a cache flush request of a memory device within the processor, and identifies multiple blocks of data within an address space associated with the cache flush request. The processor groups the multiple blocks of data into a single composite block of data, and compresses the composite block of data. The processor stores the compressed composite block of data, and stores metadata for the compressed composite block of data. The metadata includes information for both the composite block of data and information for each of the multiple blocks of data.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to improving compression ratios by utilizing a composite block of data during compression of data blocks of fixed size.

BACKGROUND

SUMMARY

An information handling system includes a storage device to store a compressed block of data, and a processor. The processor may identify multiple blocks of data within an address space of a memory device. The processor may group the multiple blocks of data into a single composite block of data, and compress the composite block of data. The processor may store the compressed composite block of data in the storage device. The processor may store metadata for the compressed composite block of data. The metadata includes information for both the composite block of data and information for each of block of the multiple blocks of data.

DETAILED DESCRIPTION OF DRAWINGS

FIG. 1illustrates an information handling system100that utilizes a data exchange architecture in accordance with the prior art. Information handling system100includes software110, a processor120, and a system memory160. Software110represents machine-executable code stored on information handling system100that is executable by processor120, and includes a first application112that is associated with a first context, a second application114that is associated with a second context, and a context isolation layer116. Application112is associated with one or more address ranges in the system physical address space (SPA) provided by system memory160. The address ranges associated with application112are collectively shown as a portion162of system memory160. Similarly, application114is associated with one or more address ranges in system memory160, collectively shown as a portion164of the system memory. Context isolation layer116represents one or more agent, application program interface (API), utility, or the like that operates to maintain the isolation between memory162and164. Examples of context isolation layer116may include a system Basic Input/Output System (BIOS) or Universal Extensible Firmware Interface (UEFI), hereinafter referred to collectively as “BIOS,” that operates to provide isolated memory ranges for system operations, a virtual desktop system that isolates various memory ranges for the use of multiple users of the virtual desktop system, a hypervisor or virtual machine manager (VMM) that sets up and maintains virtual machines and their associated memory ranges, or the like.

In operation, when applications112and114are instantiated on information handling system100, context isolation layer116allocates memory162and164to the use of their respective applications. In addition, when applications112and114need to interact, for example by moving data from one application to the other, context isolation layer116operates to manage the transfer of data between memory162and164.

Note here that the data exchange architecture of information handling system100requires the execution of code associated with context isolation layer116by processor120in order to perform data transfers between memory162and memory164. As such, the prior art data exchange architecture imposes a processing burden on processor120, thereby reducing the processor cycles available for performing other tasks associated with applications112and114. It will be understood that this processing overhead may be partially mitigated by the inclusion of Direct Memory Access (DMA) hardware in information handling system100. However, it will be further understood that such DMA hardware is typically a vendor specific add-on, and access to such DMA hardware by applications112and114directly is typically difficult. In particular, even with the inclusion of DMA hardware, processor120is still needed to set up DMA transfers, and context isolation layer116is still needed in its role as gatekeeper to system memory160.

FIG. 2illustrates an information handling system200that utilizes a Smart Data Accelerator Interface (SDXI) data exchange architecture in accordance with an embodiment of the current disclosure. Information handling system200includes software210, SDXI hardware220, and a system physical address space (SPA)260. SDXI hardware220includes a first family of processors222and an associated SDXI interface242, a second family of processors224and an associated SDXI interface244, one or more Graphics Processor Unit (GPU)226and an associated SDXI interface246, a Field-Programmable Gate Array (FPGA)248and an associated SDXI interface248, and a Smart I/O device230and an associated SDXI interface250. Software210is similar to software110, and represents machine-executable code stored on information handling system200that is executable by a processor such as one or more of processors222and224. Software210includes a first application212that is associated with a first context, a second application214that is associated with a second context, and a context isolation layer216. Software210may include functions and features similar to software110, as described above. In particular, software210may implement the data exchange architecture of information handling system100, as needed or desired. As such, application212is associated with one or more address ranges in SPA260, with the associated address ranges shown as a portion262of the SPA, and application214is associated with one or more address ranges in the SPA, with the associated address ranges shown as a portion264in the SPA. Here too, context isolation layer216is similar to context isolation layer116, representing one or more agent, API, utility, or the like that operates to maintain the isolation between memory262and264. As such, context isolation layer216operates to allocate memory262and memory264when respective application212and application214are instantiated on information handling system200, and the context isolation layer prevents the use of various memory ranges by unauthorized applications.

The SDXI data exchange architecture represents an industry effort to expand and standardize data movement protocols and hardware accelerator interfaces. As such, information handling system200broadens the scope of data exchanges on both the hardware side and the memory side. In particular, on the hardware side, SDXI hardware220incorporates various types of processing elements, co-processors, accelerators, and other data movers, as typified by processor families222and224, GPU226, FPGA228, and Smart I/O device230. On the memory side, SPA260is expanded to include not only the system physical memory, as typified by memory262and memory264, but also separately attached memory, such as Storage Class Memory (SCM) devices266, memory mapped I/O (MMIO) devices268, and memory architectures, such as Compute Express Link (CXL) and Gen-Z memory interfaces, fabric-attached memory, and the like, as shown collectively as memory device270. In particular, the SDXI data exchange architecture treats all of memory devices262,264,266,268, and270as a single SPA260. The SDXI data exchange architecture then provides standardized interfaces for data movement between software210, SDXI hardware220, and SPA260. Here, SDXI interfaces242,244,246,248, and250represent hardware and software associated with their respective hardware devices, such that a common set of SDXI commands, instructions, procedures, calls, and the like, referred to hereinafter as “SDXI commands,” can be made to the hardware devices. Here, the details of implementing the various SDXI commands can be left to the design requirements and desires of the various hardware manufacturers. In this way, the SDXI data exchange architecture remains extensible and forward-compatible with new hardware or memory developments, and is independent of actual data movement details, data acceleration implementations, and the underlying I/O interconnect technology. The SDXI commands support: data movement between different address spaces including user address spaces located within different virtual machines; data movement without mediation by privileged software once a connection has been established; an interface and architecture that can be abstracted or virtualized by privileged software to allow greater compatibility of workloads or virtual machines across different servers; a well-defined capability to quiesce, suspend, and resume the architectural state of a per-address-space data mover to allow “live” workload or virtual machine migration between servers; mechanisms to enable forwards and backwards compatibility across future specification revisions, allowing software and hardware designed to different specification revisions to interoperate; the ability to incorporate additional offloads in the future leveraging the architectural interface; and a concurrent DMA model. As used herein, SDXI will be understood to represent any present or future specifications, specification revisions, articles, working papers, or other publications of the Smart Data Accelerator Interface (SDXI) Technical Working Group (TWG) of the Storage Networking Industry Association (SNIA).

FIG. 3illustrates an embodiment of an information handling system300similar to information handling system200. Information handling system300includes a software layer310, a hardware layer320, and an attachment layer340. Software layer310is similar to software210, and includes a workload312, a data pipeline API314, a SDXI API316, and a SDXI hardware driver318. Hardware layer320includes a processor322, a memory (SPA)324, and a SDXI hardware device330. Attachment layer340includes a Network Interface Card (NIC)342and a Non-Volatile Memory—Express (NVMe) Solid State Drive (SSD)344. NIC342and SSD344are each extensions of the SPA space of information handling system300.

Workload312and data pipeline API314operate similarly to applications212and214, and context isolation layer216, and represent elements of a typical information handling system that perform the processing task of the information handling system. In particular, workload312operates to perform various operations on data and to move data between different storage and processing elements of information handling system300, and may make various service calls to data pipeline API to assist in such processing operations and data moves. SDXI API316represents an API configured to provide the core operability as specified by a particular revision of an SDXI specification. In addition, SDXI API316provides additional extensions to the core operability of the particular SDXI specification, as described below. When workload312or data pipeline API314invoke SDXI API316for the various data operations or data moves, the SDXI API operates to direct SDXI hardware driver318elicit SDXI hardware330to perform one or more of the invoked operations or data moves, as needed or desired. In this regard, SDXI hardware driver318and SDXI hardware330are closely associated with each other.

As such, SDXI hardware330represents a wide variety of different types of hardware that can be utilized to perform the SDXI core operations and extensions as described herein. An example of SDXI hardware330may include accelerator blocks within a general purpose processor or processor family, such as a CPU or the like, a purpose specific processor, such as a GPU or the like, a logic-based device or state-based device, such as a FPGA, a Complex Programmable Logic Device (CPLD) or the like, a smart I/O device that provides in-line data processing in the course of I/O operations, such as a smart NIC, a Host Bus Adapter (HBA), a storage controller such as a RAID controller, a Network Attached Storage (NAS) device, a Storage Area Network (SAN) controller, or the like, or another processing device, as needed or desired. Here, it will be understood that, SDXI hardware330may be configured to provide operations consistent with its type, but that are not specifically associated with its SDXI functionality. For example, where SDXI hardware330represents a FPGA type of device, it will be understood that the FPGA device may be invoked to provide functionality of a more general nature, in addition to the SDXI functionality as described herein.

SDXI hardware330includes a SDXI interface332, various accelerator blocks334, and a processor SoC336. Accelerator blocks334may represent hardware accelerators, logic-based or state-based accelerators, or other configurable or pre-configured accelerator functions, as needed or desired. As described further below, SDXI hardware330may operate in some embodiments to provide enhanced data pipelining operations. For example, SDXI hardware330may provide data movement: between different locations in memory324, to and from the memory and a network connected to NIC342, to and from the memory and NVMe SSD344, to and from the network and the NVMe SSD, and between different locations in the NVME SSD. SDXI hardware330may further operate in some embodiments to provide enhanced data transformation operations on data, either as atomic operations or in conjunction with the data movement utilizing various accelerator blocks334. In particular, various embodiments of SDXI hardware330may provide: data compression/decompression, data encryption/decryption, data checksums, hash functions such as SHA-256 hashes and the like, RAID functions, erasure coding, and the like. Other functions that may be performed by SDXI hardware330may include data deduplication, LZ-4 compression, compression ratio and block size optimization, data operation chaining, multi-point data movement, uncompressible block handling, and query analytics.

FIG. 4illustrates an embodiment of an information handling system400similar to information handling systems200and300. Information handling system400includes a processor complex (not illustrated) that provides a communication interface405to provide data communications with multiple SDXI hardware devices410. An example of interface405may include a Third Generation Peripheral Component Interconnect—Express (PCIe Gen3) ×16 (16-lane) communication link, a PCIe Gen3 communication link with greater or fewer lanes (e.g., ×4, ×8, ×32), or another communication interface, as needed or desired. Information handling system400further includes a multi-queue Direct Memory Access (DMA) engine430, and a data bridge435. Each of the SDXI hardware devices410are connected to receive data and instructions from DMA engine430, and to provide data and control information to data bridge435. DMA engine430provides dynamic allocation of parallel data flows to the multiple SDXI hardware devices410, as needed by the processing tasks operating on information handling system400. The data flows are provided to DMA engine430via interface405, and may be received from memory or storage devices within the SPA of information handling system400. Data bridge435receives the data flows from SDXI hardware devices410and communicates the data flows via interface405to the memory and storage devices within the SPA of information handling system400.

Each of the SDXI hardware devices410may be understood to be similar hardware devices, such as where the SDXI hardware devices are each provided by a common manufacturer and are a common device type. Here, DMA engine430may allocate data flows to the various SDXI hardware devices410based upon factors unrelated to the particular device type of the SDXI hardware devices. For example, DMA engine430may allocate data flows based upon the resource loading or availability of each of the SDXI hardware devices, the power level or power state of each of the SDXI hardware devices, or other factors not directly related to the type of the SDXI hardware devices, as needed or desired. Further, each of SDXI hardware devices410may be understood to be different hardware devices, such as where the SDXI hardware devices are provided by different manufacturers and are different device types. Here, DMA engine430may allocate data flows to the various SDXI hardware devices410based upon the type of each of the SDXI hardware devices. For example, where a particular SDXI hardware device410contains a network function, DMA engine430may allocate network based data flows to that particular SDXI function. On the other hand, where a different SDXI hardware device contains a storage controller function, DMA engine430may allocate storage based data flows to the other SDXI function.

SDXI hardware device410is illustrated as including a source data FIFO/deceleration module412, a destination data FIFO/acceleration module414, a copy engine420, a compression engine422, a decompression engine424, and one or more additional engines426. The configuration illustrated by SDXI hardware device410will be understood to be typical, and representative of a wide range of device configurations, as needed or desired. As such, the particular configuration illustrated by SDXI hardware device410should not be understood to be limiting on the type, nature, features, configuration, or functionality of SDXI hardware devices in general. Other functions that may be performed by SDXI hardware410may include data deduplication, LZ-4 compression, compression ratio and block size optimization, data operation chaining, multi-point data movement, uncompressible block handling, and query analytics.

FIG. 5illustrates a portion of an information handling system500similar to information handling systems200,300, and400according to an embodiment of the current disclosure. Information handling system500may be suitable device including, but not limited to, a distributed storage array. Information handling system500includes a processor502, a cache504, and a local storage device506. In different examples, cache504may be incorporated within the same physical chip as processor502or may be a separate component of information handling system500as shown inFIG. 5. As used and described herein cache504may be broadly interpreted as any suitable memory device to store data associated with processor502and anything component of information handling system500. Processor502includes a driver510, which in turn includes a cluster level object manager device512, a distributed object manager device514, and a log structured object manager device516. Cache504may store component blocks520and522, as well as metadata530and532. Although only data blocks520and522are shown inFIG. 5, cache504may store any suitable number of data blocks without varying from the scope of the disclosure. One of ordinary skill in the art would recognize that information handling system500may include addition components without varying from the scope of this disclosure.

During operation, one or more components, such as processor502, within information handling system500may provide one or more data transfers between memory spaces. In an example, the data transfers may be between any suitable memory spaces including, but not limited to, memory spaces in different contexts, such as in between different virtual machines. The data transfers may be complaint with any suitable protocol or hardware, such as an SDXI hardware device. Information handling system500may provide any suitable accelerator operation as a transform for the data being transferred. In an example, the accelerator operation may be any suitable operation including, but not limited to, data compression, encryption, cyclic redundancy check (CRC) calculation, erasure code offloads, and hash calculations for deduplication.

In previous information handling systems, compression operations were performed on a storage unit size block of data. For example, in a distributed storage array device, the storage unit size may be 4 Kbyte. In certain examples, small blocks of data may have compression ratios that are less than compression ratios for compression of an entire file containing the same data blocks due to less data history within the small blocks to search for matches. In certain information handling systems, such as a distributed storage array, a compression policy may be to discard compression results if a compression ratio for a block of data is not equal to or greater than a particular threshold including, but not limited to, 40%, 50%, and 60. For example, if a bock of data is X KBytes the compressed data may be discarded if the compressed data is not ½X KBytes or less. Processor502may improve information handling system500by grouping or combining multiple blocks of data within cache504and compress the composite block of data to achieve higher compression ratios as compared to possible compression ratios of a single block of data. Therefore, if information handling system500is a distributed storage array, the higher compression ratios may enable a higher percentage of blocks of data being stored in a compressed format within local storage device506.

In an example, processor502may receive a flush command for cache504. In certain examples, cache504may be any suitable cache of processor502including, but not limited to, a write cache of the processor. In an example, the flush command may include a command to write one or more blocks of data, such as component blocks520and522, from cache504to local storage device506.

In response to the flush command, processor502, via driver510, may perform one or more suitable operations to compile data blocks520and522into a single composite block of data. For example, driver510may retrieve multiple blocks of data from cache504. In an example, the multiple blocks may be any suitable number of data blocks including, but not limited to, component blocks of data520and522within cache504. In certain examples, each block of data520and522within cache504may be substantially the same size. In an example, data blocks520and522may be any suitable blocks of data within cache504including, but not limited to, contiguous blocks of data. In response to retrieving the multiple blocks of data, including blocks520and522, driver510may compile the blocks of data into a single composite block of data540. In an example, composite block540may be formed from any suitable number of blocks of data including, but not limited to, components blocks520and522.

Driver510may perform one or more suitable operations to compress composite block540. In an example, if data blocks520and522both include a first number of descriptors for data, then a concatenated or composite block540may include a chain of descriptors substantially equal to the sum of the descriptors of both of the data blocks. In an example, cluster level object manager device512concatenate blocks520and522and store the metadata for the concatenated data block or composite block540. Based on the chain of descriptors, distributed object manager device514may utilize compression history for data blocks520and522to match searches to better compress composite540. In this example, distributed object device514may perform the compression operations within processor502. In previous information handling systems, the compression of blocks of data would be performed by log structured object manager device516. Thus, information handling system500performs data compression in distributed object manager514which is a higher level object manager as compared to log structured object manager device516. In an example, information handling system500may be a distributed file system and treat composite block540as a compression entity.

In response to composite block540being compressed, the compressed composite data block may be stored in local storage device506. In an example, local storage device506may be utilized for any suitable data storage including, but not limited to, a permanent data storage device. In certain examples, metadata530for data block520and metadata532for data block522may also be stored in local storage device506. In an example, metadata530and532for may include dependencies of individual blocks520and522on composite block540. In certain examples, the metadata association between individual blocks or component blocks520and522of parent composite block540may be utilized by processor502for compression of the composite block.

In an example, distributed object manager device512may use destination addresses in local storage device506to write the compressed data. Processor502may determine a number of data buffers needed to write out the compressed data of composite block540based on the size of the compressed data block. In an example, the compressed data may be read from local storage device506in any substantial manner including, but not limited to, an application layer reading the compressed data in any similar manner as any other compressed data.

FIG. 6is a flow diagram of a method600for utilizing a composite block of data during compression of data blocks of fixed size according to another embodiment of the current disclosure, starting at block602. It will be readily appreciated that not every method step set forth in this flow diagram is always necessary, and that certain steps of the methods may be combined, performed simultaneously, in a different order, or perhaps omitted, without varying from the scope of the disclosure.FIG. 6may be employed in whole, or in part, by information handling system100depicted inFIG. 1, information handling system500depicted inFIG. 5, or any other type of system, controller, device, module, processor, or any combination thereof, operable to employ all, or portions of, the method ofFIG. 6.

At block604, a flush to persistence command for a cache is received. In an example, the cache may be any suitable cache of a processor including, but not limited to, a write cache of the processor. In certain examples, the flush command may include a command to write one or more blocks of data from the cache to a permanent storage device.

At block606, multiple blocks of data are retrieved from the cache. In an example, the multiple blocks may be any suitable number of data blocks within the cache. In certain examples, each block of data within the cache may be substantially the same size. For example, each of the blocks of data may be 4 Kbyte. In certain examples, the multiple blocks of data may be any suitable blocks of data including, but not limited to, contiguous blocks of data. In an example, a driver of a processor may retrieve the multiple blocks of data.

At block608, the multiple blocks of data are compiled into a single composite block of data. In an example, the composite block of data may be formed from any suitable number of blocks of data to create a composite block of data that may result in a higher level of compression as compared to each of the original blocks of data within the cache. For example, the composite block may include a chain descriptor including descriptors from each of the multiple blocks, and the chain descriptor may improve the compression ratios based on histories of each of the multiple blocks.

At block610, the composite block of data is compressed. In an example, any suitable component within a processor may perform the compression of the composite block. For example, an accelerator within the processor may compress the composite block. In certain examples, a distributed object device may perform the compression operations within the accelerator of the processor. At block612, the compressed composite data block is stored in a local storage device. In an example, the local storage device may be utilized for any suitable data storage including, but not limited to, permanent data storage. At block614, metadata for each of the multiple blocks of data is stored, and the method ends at block616. In an example, the metadata for the individual data blocks within the composite data block may include dependencies of the individual blocks on the composite block. In certain examples, the metadata association between the individual blocks or component blocks of a parent composite block may be utilized by the processor for compression of the composite block. Decompression of a composite block will require retrieval of all blocks that compose the composite block.

Information handling system700can include devices or modules that embody one or more of the devices or modules described below, and operates to perform one or more of the methods described below. Information handling system700includes a processors702and704, an input/output (I/O) interface710, memories720and725, a graphics interface730, a basic input and output system/universal extensible firmware interface (BIOS/UEFI) module740, a disk controller750, a hard disk drive (HDD)754, an optical disk drive (ODD)756, a disk emulator760connected to an external solid state drive (SSD)762, an I/O bridge770, one or more add-on resources774, a trusted platform module (TPM)776, a network interface780, a management device790, and a power supply795. Processors702and704, I/O interface710, memory720, graphics interface730, BIOS/UEFI module740, disk controller750, HDD754, ODD756, disk emulator760, SSD762, I/O bridge770, add-on resources774, TPM776, and network interface780operate together to provide a host environment of information handling system700that operates to provide the data processing functionality of the information handling system. The host environment operates to execute machine-executable code, including platform BIOS/UEFI code, device firmware, operating system code, applications, programs, and the like, to perform the data processing tasks associated with information handling system700.

In the host environment, processor702is connected to I/O interface710via processor interface706, and processor704is connected to the I/O interface via processor interface708. Memory720is connected to processor702via a memory interface722. Memory725is connected to processor704via a memory interface727. Graphics interface730is connected to I/O interface710via a graphics interface732, and provides a video display output736to a video display734. In a particular embodiment, information handling system700includes separate memories that are dedicated to each of processors702and704via separate memory interfaces. An example of memories720and730include random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/UEFI module740, disk controller750, and I/O bridge770are connected to I/O interface710via an I/O channel712. An example of I/O channel712includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. I/O interface710can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/UEFI module740includes BIOS/UEFI code operable to detect resources within information handling system700, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/UEFI module740includes code that operates to detect resources within information handling system700, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller750includes a disk interface752that connects the disk controller to HDD754, to ODD756, and to disk emulator760. An example of disk interface752includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator760permits SSD764to be connected to information handling system700via an external interface762. An example of external interface762includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive764can be disposed within information handling system700.

I/O bridge770includes a peripheral interface772that connects the I/O bridge to add-on resource774, to TPM776, and to network interface780. Peripheral interface772can be the same type of interface as I/O channel712, or can be a different type of interface. As such, I/O bridge770extends the capacity of I/O channel712when peripheral interface772and the I/O channel are of the same type, and the I/O bridge translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel772when they are of a different type. Add-on resource774can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource774can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system700, a device that is external to the information handling system, or a combination thereof.

Network interface780represents a NIC disposed within information handling system700, on a main circuit board of the information handling system, integrated onto another component such as I/O interface710, in another suitable location, or a combination thereof. Network interface device780includes network channels782and784that provide interfaces to devices that are external to information handling system700. In a particular embodiment, network channels782and784are of a different type than peripheral channel772and network interface780translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels782and784includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels782and784can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

Management device790represents one or more processing devices, such as a dedicated baseboard management controller (BMC) System-on-a-Chip (SoC) device, one or more associated memory devices, one or more network interface devices, a complex programmable logic device (CPLD), and the like, that operate together to provide the management environment for information handling system700. In particular, management device790is connected to various components of the host environment via various internal communication interfaces, such as a Low Pin Count (LPC) interface, an Inter-Integrated-Circuit (I2C) interface, a PCIe interface, or the like, to provide an out-of-band (OOB) mechanism to retrieve information related to the operation of the host environment, to provide BIOS/UEFI or system firmware updates, to manage non-processing components of information handling system700, such as system cooling fans and power supplies. Management device790can include a network connection to an external management system, and the management device can communicate with the management system to report status information for information handling system700, to receive BIOS/UEFI or system firmware updates, or to perform other task for managing and controlling the operation of information handling system700. Management device790can operate off of a separate power plane from the components of the host environment so that the management device receives power to manage information handling system700when the information handling system is otherwise shut down. An example of management device790include a commercially available BMC product or other device that operates in accordance with an Intelligent Platform Management Initiative (IPMI) specification, a Web Services Management (WSMan) interface, a Redfish Application Programming Interface (API), another Distributed Management Task Force (DMTF), or other management standard, and can include an Integrated Dell Remote Access Controller (iDRAC), an Embedded Controller (EC), or the like. Management device790may further include associated memory devices, logic devices, security devices, or the like, as needed or desired.