Routing for reducing impedance distortions

A substrate having a core with vias disposed therein. A reference layer is formed on the core, with voids in the reference layer that are formed around the vias in the core. Traces on a routing layer overlie the reference layer. Also included is a contact layer with contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of the sections are also aligned in rows substantially along the first direction and aligned with the vias. Further, the traces within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.

FIELD

This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to the design of substrates and circuit boards.

BACKGROUND

Integrated circuits, such as bump bonded flip chip integrated circuits, are typically electrically and mechanically housed in a package prior to use in a larger circuit. The package provides several important functions for the integrated circuit. First, the package provides mechanical and structural support to the integrated circuit, and thus protects it from physical damage. Additionally, the substrate, which is the interposer between the integrated circuit and the printed circuit board and forms the base of the package, physically spreads out, or routes, the electrical connections that are made to the integrated circuit on one side of the substrate, so that electrical connections to other parts of the overall circuit, such as to a printed circuit board, can be more easily made on the other side of the substrate.

One type of substrate is fabricated with a relatively rigid sheet of a non-electrically conductive material, called a core, upon which one or more build-up layers are formed, typically on both sides of the core. For example, the core may have electrically conductive layers formed on both of its sides, which are then covered with a non-electrically conductive layer, and then another electrically conductive layer, and so on until the desired number of electrically conductive layers have been formed.

The electrically conductive layers in the substrate are patterned, typically at the time that they are formed, so as to provide specific functions. For example, on an electrically conductive layer on which signals from the integrated circuit are conducted, the layer typically includes a plurality of electrically conductive lines or signal traces, which route the signal from one part of the substrate, such as an inner portion, to a different part of the substrate, such as a more peripheral portion. An electrically conductive layer that provides a ground plane is typically a large, contiguous, electrically conductive sheet. Finally, an electrically conductive layer that provides a power plane typically includes multiple electrically conductive sheets that do not electrically connect one with another, at least not on that same layer.

Electrical connections from one to another of the electrically conductive layers of the substrate are provided by forming holes in the non-electrically conductive layers between them, and either coating or filling the holes with an electrically conductive material. Such structures are called vias. Vias typically must also be formed through the substrate core. These core vias can be formed by mechanical or laser drilling. Because the core is typically much thicker than any of the build-up layers, core vias are often much larger than the vias that extend between the electrically conductive build-up layers.

Unfortunately, the large size of the core vias can present problems when designing a substrate. For example, a standard core for a substrate has electrically conductive layers formed on either side, and core vias drilled through it that connect to, and often align with, signal balls. When the electrically conductive layers formed on the core serve as reference layers, such as power or ground planes, for signals routed on the layers above or below the core, then some clearance has to be provided between the signal core vias and the electrically conductive portions of the reference layers, to ensure that the vias do not short to the reference layer. These clearances are called voids herein, and are formed around the vias on the reference layer. The voids tend to utilize a relatively large amount of space on that layer. However, it is desirable that the signal traces on the routing layer overlying or underlying the reference layer remain predominantly over the conductive portions of the reference layer, and not travel over the voids in the reference layer. When the signal traces travel over the voids, there tend to be problems with inconsistent impendence.

Various solutions have been proposed for this problem of preventing signal traces from routing over voids on their reference planes, including forming the signal traces with narrower widths, or more closely spaced together, so as to be able to fit the signal traces within the small spaces of the reference layer that are left between the voids formed around the core vias. Alternately, the substrate can be made larger so as to increase the amount of room available between the voids for the signal traces. However, these solutions introduce new problems. Signal traces with narrower widths do not conduct the signals as well and tend to have higher resistance. Signal traces that are more closely spaced together tend to have an increase in crosstalk between the signals conducted on the traces. Finally, larger substrates require more space within the circuit in which they are used, which is generally undesirable for most applications.

What is needed, therefore, is a substrate design that provides more usable space for signal trace routing without running signal traces over voids, and without increasing the size of the substrate.

SUMMARY

The above and other needs are met by an improvement to a substrate having an electrically nonconductive core with vias disposed therein. An electrically conductive reference layer is formed on the electrically nonconductive core, with voids in the electrically conductive reference layer that are formed around and aligned with the vias in the electrically nonconductive core. Electrically conductive traces on a routing layer overlie the electrically conductive reference layer. Also included is a contact layer with electrically conductive contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of each of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of each of the sections are also aligned in the same rows substantially along the first direction, since they are formed directly around the vias and aligned with the vias. Further, the traces on the overlying routing layer within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.

In this manner, the voids in the reference layer are substantially aligned within a given section of the substrate, and thus there are relatively large and unbroken corridors of space between the voids where the reference layer exists. Thus, there are also relatively large and unbroken corridors over which the signal traces can be routed, without having to overlie the voids. Thus, the signal traces do not need to be crowded too closely one to another, nor do they need to overlie the voids. Rather, they can remain well referenced to the underlying reference layer. By rearranging the core vias and the voids for these vias in this manner, space within each of the logical sections of the substrate is better utilized, and the electrical characteristics of the substrate are improved without increasing the size of the substrate.

In various preferred embodiments, the voids aligned within a given row are interconnected. The rows of vias within each of the sections of the core are all disposed in a same direction in one embodiment, and in another embodiment the rows of vias within each of the sections of the core are not all disposed in a same direction. In yet another embodiment the first direction of the rows of vias within the given one of each of the sections is substantially disposed along a logical radial line from the center of the substrate. In alternate embodiments, the reference layer is either a power layer or a ground layer. Also described is a packaged integrated circuit that includes the substrate described above. In addition, a printed circuit board is also described.

DETAILED DESCRIPTION

With reference now toFIG. 1there is depicted a cross sectional view of a portion of a substrate10. The embodiments of the invention as described herein are applicable to the cases where the substrate10is either a substrate or a printed circuit board. In either case, the substrate10is generally used to route signals from a generally central location on one side of the substrate10to generally more dispersed locations on the opposite of the substrate10. Thus, although the descriptions provided below are given in regard to the specific case of a substrate, it is appreciated that the invention is applicable as well to a printed circuit board. It is also appreciated that, while the substrate10depicted inFIG. 1is a ten-layer substrate, the invention is equally applicable to substrates having four layers, six layers, eight layers, or other numbers of layers, with signals routed either above or below the core22.

In the specific embodiment depicted inFIG. 1, the substrate10includes a core22with four build-up layers on either side of the core22. Specifically, the substrate10has a first electrically conductive layer20that is formed directly on a first side of the core22, and then four build-up layers12,14,16, and18on top of the first side of the core22, where layer12is the upper most layer on the first side of the substrate10. Similarly, the substrate10has a second electrically conductive layer24that is formed directly on a second opposing side of the core22, and then four build-up layers26,28,30, and32on top of the second side of the core22, where layer32is the upper most layer on the second side of the substrate10. It is appreciated that the number of layers as depicted inFIG. 1is representative only, and that in various embodiments of the invention, the substrate10may include either a greater or a lesser number of such build-up layers, within the constraints as dictated by the description contained herein.

The electrically conductive layers are disposed between non-electrically conductive layers, which electrically insulate the electrically conductive layers one from another. In the example as depicted inFIG. 1, an integrated circuit34is electrically connected to contacts on the upper most layer12of the substrate10. Also as depicted inFIG. 1, electrical contacts36are provided on the lower most layer32of the substrate10. The electrical contacts36are depicted as ball contacts, but may be of another type, and are used for making electrical connections between the packaged integrated circuit assembly and other portions of a larger circuit in which the packaged integrated circuit is used.

FIG. 1also provides a legend on the right hand side of the figure, in which there is given the layer designations for a very specific embodiment of the invention. In this specific embodiment, the upper most layer12includes a VDDIO structure36, which is the power plane for the input/output circuitry disposed in an outer portion of the integrated circuit. Layer16includes a VSSIO structure38, which is the ground plane for all the input/output circuitry in the integrated circuit. Layer20includes a VDDIO structure40, which is the power plane for the input/output circuitry disposed in an inner portion of the integrated circuit. Layers14and18contain the circuitry routing to the outer and inner portions of the integrated circuit, respectively.

In the embodiment depicted inFIG. 1, the signal traces38on layer18are preferably referenced to the power plane40on layer20. The best referencing is provided when the signal traces38do not overlie any voids within the power plane40, which is generally referred to herein as the reference layer40. It is appreciated that the reference layer40may be either a power (VDD) layer or a ground (VSS) layer.

With reference now toFIG. 2, there is depicted a top plan view of a logical section of the substrate10, depicting the relative alignment between core vias46in the core22, voids48in the reference layer40, and signal traces38, where the signal traces38overlie the voids48around the core vias46. By “logical section” it is meant that this is a portion somewhere within the whole of the substrate10, but there are no actual lines or other markings on the substrate10itself which would delineate one logical section from another.

As mentioned above, the embodiment depicted inFIG. 2is not a preferred embodiment, as there are irregularities in the impedance of the signal traces38between those areas that are properly referenced and those areas that are not, such as between those portions of the signal traces38which overlie the reference plane40and those portions of the signal traces38which overlie the voids48. It can also be seen that the arrangement of the vias46produces many gaps between two adjacent voids48in which signal traces38cannot easily be routed without running over the voids48.

With reference now toFIG. 3, there is depicted a top plan view of a logical section of the substrate10, depicting the relative alignment between core vias46, voids48in the reference layer40, and signal traces38, where the signal traces38have been placed closer together so as to not overlie the voids48around the core vias46. As mentioned above, this is also not a preferred embodiment, as the close proximity of the signal traces38to each other tends to increase the degree of crosstalk that is experienced between the signals. As before, the arrangement of the vias46produces many gaps between the adjacent voids48in which signal traces38cannot easily be routed without running over the voids48.

With reference now toFIG. 4, there is depicted a top plan view of a logical section of the substrate10, depicting the relative alignment between core vias46, voids48in the reference layer40, and signal traces38, where the core vias46and voids48have been realigned so that the signal traces38do not overlie the voids48around the core vias46. In this preferred embodiment, the signal traces38are neither narrowed, so there is no impact on their resistance, nor are they crowded together such that crosstalk between them increases. However, they also do not substantially overlie the voids48in the reference layer40, so the impedance of the signal traces38is not disrupted in that manner, and the signal traces38are well referenced to the reference layer40.

The benefits of the embodiment as depicted inFIG. 4are enabled by having the signal traces38, the vias46, and the voids48substantially aligned in rows that are directed along a given direction. In this manner, good use is made of the space available for the signal traces38, and the substrate10does not need to be made larger in order to accommodate all the desired signal traces38without resorting to the non-preferred embodiments described above. In other words, the space on the substrate10is compacted between rows of vias46and voids48, so that there are fewer unusable gaps between them. As depicted inFIG. 4, some or all of the voids48may be linked together to form a continuous void around a row of vias46.

One important difference between the embodiment depicted inFIG. 4and the embodiments depicted inFIGS. 2 and 3is the alignment of the vias46and voids48within the logical section depicted. Typically, the core vias46are aligned to some structure within the substrate10other than the signal traces38. For example, the core vias46can be aligned with reference to the contacts36which make electrical connections to the outside circuitry, such as the ball contacts. When the core vias46are aligned to some other structure in this manner, the voids48are automatically aligned in the same manner, and then the signal traces38must be routed as best as can be done around the orientation of the voids48.

However, in the embodiment as depicted inFIG. 4, the core vias46within the depicted logical section of the substrate10are aligned substantially in rows in generally the same direction as the desired routing of the signal traces38within that same logical section. Thus, the voids48are also substantially aligned in rows that travel in the same general direction as the signal traces38in that logical section of the substrate10. In this manner, the various structures are aligned with reference to the desired routing of the signal traces38, and not with reference to some other structure. Thus, there is more space that is usable for the routing of the signal traces38, and less space that is undesirably disposed in gaps between the voids48.

Thus, the vias46and voids48within each logical section are preferably aligned according to the desired routing of the signal traces38within that logical section. This alignment may be, in various embodiments, in the same general direction within all logical sections of the substrate10, or more preferably may be in different general directions within the various logical sections of the substrate10. For example, the general direction for each logical section may be generally along a radial line extending from the center of the substrate10and through the logical section to the peripheral edge of the substrate10. In most embodiments, the general direction of alignment within a given logical section will be different from section to section, but generally along radial lines of the substrate10as the signals are routed generally outwardly from a relatively small and centrally located integrated circuit34to contacts36that are located generally toward the peripheral edges of the substrate10.