Interface device with programmable voltage gain and/or input impedance having an analog switch comprising N and P field effect transistors connected in series

An interface device for connection between two electronic components of an electronic circuit, includes:

The present invention relates to an interface device, which can be connected between two electronic components of an electronic circuit and comprising:

an input terminal, an output terminal and a reference terminal, the device having an input voltage between the reference terminal and the input terminal, an output voltage between the reference terminal and the output terminal, an input impedance, and an output voltage gain,

at least one resistance connected to at least one terminal among the input terminal and the output terminal,

at least one analog switch positioned between the output terminal and the reference terminal, the switch having a closed state or an open state, and

control means for the or each switch, at least one parameter among the input impedance and the output voltage gain of the device having distinct values as a function of whether the analog switch is closed or open.

The invention also relates to an electronic system having an electronic component capable of delivering an output voltage, an analog-digital converter, and such an interface device connected between the electronic component and the analog-digital converter.

An interface device of the aforementioned type is known from the technical sheet for the PGA2310 electronic component by Texas Instruments. The electronic component includes an interface device with programmable voltage gain comprising an input terminal, an output terminal, and a reference terminal, a plurality of resistances connected between the input and output terminals, a multiplexer including a plurality of analog switches connected in parallel to the resistances, and means for controlling each switch.

Furthermore, known from document WO 97/24807 is a type of switch commonly used as analog switch, for example in multiplexers. This type of switch comprises two connection terminals, an N-type field effect controllable transistor and a P-type field effect controllable transistor connected in parallel to the N-type transistor.

However, such interface devices have a voltage operating range limited at the outside to their supply voltages and cannot be used with higher voltages. This drawback on the one hand prevents these interface devices from being connected with electronic components such as transducers, or buses, capable of producing high voltages, in the vicinity of several tens of volts, or several hundreds of volts, and on the other hand prohibits said interface devices from being used in an environment capable of causing high voltages at the terminals of the electronic components.

The aim of the invention is to propose a programmable interface device having an extended voltage operating range, so as to connect it with electronic components capable of producing high voltages.

To that end, the invention relates to an interface device of the aforementioned type, characterized in that the or each analog switch comprises at least one N-type field effect controllable transistor and one P-type field effect controllable transistor connected in series.

According to other embodiments, the interface device includes one or more of the following features, considered alone or according to all technically possible combinations:

the device comprises two resistances, the first resistance being connected between the input terminal and the output terminal, and the second resistance being connected to the analog switch on the one hand and the output terminal on the other hand,

the or each analog switch comprises at least three N- or P-type controllable field effect transistors, alternatingly connected in series,

the field effect transistors of the or each analog switch are MOSFET transistors of the N (NMOS) or P (PMOS) type,

the device comprises a polarization stage connected to the output terminal of the device and capable of being connected to a polarization potential, and the polarization stage comprises a polarization resistance, a field effect controllable transistor, and a protection diode of the transistor,

the device comprises a plurality of resistances connected in series between the input terminal and the output terminal, and the resistances are connected to one another at respective connection nodes,

the device comprises at least one polarization stage connected, on the one hand, to a point among the output terminal and the connection node and capable of being connected, on the other hand, to a polarization potential, and the or each polarization stage comprises a polarization resistance, a controllable field effect transistor, and a protection diode of the transistor,

the transistor of the or each polarization stage is a MOSFET transistor of the P (PMOS) or N (NMOS) types,

the substrates of each field effect transistor of the or each analog switch are connected to protection diodes,

the substrates of each field effect transistor of the or each analog switch are not electrically connected to any potential,

the device includes means for establishing a high inversion regime of the field effect transistors of the or each analog switch, when said switch(es) are in their closed state, and

the control means for the or each analog switch are capable of applying control voltages on the gate of each field effect transistor of the or each analog switch, the voltage applied on the gate of each N-type field effect transistor of a given switch having a value opposite that of the voltage applied on the gate of each P-type field effect transistor of that given switch.

The invention also relates to an electronic system, of the type having an electronic component, an analog-digital converter, and an interface device connected between the electronic component and the analog-digital converter, characterized in that the interface device is as defined above.

According to another embodiment, the electronic system includes the following features:

the maximum value of the voltage delivered by the electronic component is greater than the supply voltages of the interface device, or the control voltages of the or each analog switch of the interface device.

The electronic system10includes an electronic component12capable of delivering voltage, an analog-digital converter14, and an interface device16according to the invention connected in series between the electronic component12and the analog-digital converter14.

In the embodiment ofFIG. 1, the electronic system10is an electronic sensor capable of converting a physical data to be measured into a digital signal. The electronic component12is a transducer.

Alternatively, the electronic system10is a system capable of being connected to a voltage bus, and the electronic component12is a bus transmitter.

The transducer12is capable of converting the physical data to be measured into an analog voltage Uin.

The analog-digital converter14is capable of converting an analog voltage Uout into a digital signal.

As illustrated inFIG. 2, the interface device16comprises an input terminal17capable of receiving the analog voltage Uin from the transducer12, an output terminal18capable of delivering the output voltage Uout to the analog-digital converter14with a voltage gain from the input voltage Uin, and a reference terminal19having a reference potential Vref. The input voltage Uin corresponds to the voltage between the input terminal17and the reference terminal19. In other words, Uin=Vin−Vref, where Vin is the potential at the input terminal17. The output voltage Uout corresponds to the voltage between the output terminal18and the reference terminal19. In other words, Uout=Vout−Vref, where Vout is the potential at the output terminal18.

The output voltage Uout verifies the following equation:
Uout=G×Uin+U0,

where G is the voltage gain comprised between zero and one, inclusive, and U0is an offset voltage having a predetermined value.

The interface device16comprises a first power supply terminal19A that can be powered by a first power supply voltage Uss with a negative value and a second power supply terminal19B that can be powered by a second power supply voltage Udd, having a positive value and for example opposite that of the first power supply voltage Uss.

InFIG. 2, the interface device16according to a first embodiment comprises a polarization stage20, a first adaptation resistance22, a second adaptation resistance24and an analog switch26.

According to this embodiment, the polarization stage20can provide a positive polarization, and includes a P-type insulated gate field effect transistor28, also called PMOS transistor28(P-type Metal Oxide Semiconductor Field Effect Transistor), a polarization resistance30, and a protection diode32connected in series.

The polarization stage20is connected to the output terminal18and can be connected to a positive polarization potential Vpol+.

The first adaptation resistance22is connected by one of its terminals to the input terminal17and by its other terminal to the output terminal18.

The second adaptation resistance24is connected by one of its terminals to the analog switch26and by its other terminal to the output terminal18.

The analog switch26is connected between the second adaptation resistance24and the reference terminal19.

In the polarization stage20, the polarization resistance30is connected between the transistor28and the protection diode32. The anode of the diode32is connected to the polarization resistance30, and the cathode of the diode32is connected to the output terminal18.

InFIGS. 3 and 4, the analog switch26includes an input terminal34, an output terminal36, an N-type insulated gate field effect transistor38, also called NMOS transistor38(N-type Metal Oxide Semiconductor Field Effect Transistor), and a PMOS transistor40connected in series between the input34and output36terminals.

The NMOS38and PMOS40transistors are, for example, placed in insulating boxes capable of electrically insulating them from one another, as well as relative to the other electronic components of the electronic sensor10. The insulating boxes are, for example, according to those described in document U.S. Pat. No. 5,389,811A column 2 lines 63 to 66 and column 3 lines 3 to 6, in light of FIGS. 3 and 4 of that document.

In the embodiment ofFIG. 3, the analog switch26includes a protection diode42connected by the anode to the substrate46of the NMOS transistor38, and able to be connected by the cathode to the power supply voltage Uss, as well as a protection diode44connected by the cathode to the substrate48of the PMOS transistor40, and able to be connected by the anode to the power supply voltage Udd.

In the embodiment ofFIG. 4, the substrates46,48of the NMOS38and PMOS40transistors of the analog switch26are alternatively not connected to any electric potential. The substrates46,48of the NMOS38and PMOS40transistors of the analog switch26are then said to be floating.

InFIG. 5, the analog switch26alternatively comprises three N- or P-type field effect transistors, alternatingly connected in series. The analog switch26comprises the input terminal34, the output terminal36, and an NMOS transistor50, a PMOS transistor52, and an NMOS transistor54connected in series in that order between the input34and output36terminals.

In the example ofFIG. 5, the substrates56,58,60of the NMOS50, PMOS52and NMOS54transistors are not connected to any potential, the substrates being said to be floating.

Alternatively, the analog switch26includes a protection diode connected by the anode to the substrate56of the NMOS transistor50, and able to be connected by the cathode to the power supply voltage Uss. The analog switch26also includes a protection diode connected by the cathode to the substrate58of the PMOS transistor52, and able to be connected by the anode to the power supply voltage Udd. The analog switch26lastly includes a protection diode connected by the anode to the substrate60of the NMOS transistor54, and able to be connected by the cathode to the power supply voltage Uss.

The operation of the interface device16according to the invention will now be explained.

In the three embodiments of the analog switch26ofFIGS. 3 to 5, the switch26is controlled using control voltages62,64,66,67,68applied on the gates of the NMOS and PMOS transistors. Each control voltage can assume two different values, the value of the control voltages62,66,68applied on the NMOS transistors being opposite the value of the voltages64,67applied on the PMOS transistors. In these three embodiments, the possible values for each control voltage are preferably chosen to be equal to the values of the power supply voltages Uss and Udd of the interface device16.

When the NMOS38,50,54or PMOS40,52transistors are in their blocked state, the analog switch26is in the open state.

Conversely, when the NMOS38,5054and PMOS40,52transistors are in their on state, the analog switch26is in the closed state.

In the closed state, the analog switch26has an internal impedance Zon. The first resistance22has an impedance Rser, and the second resistance24has an impedance Rpar.

Depending on whether the analog switch26is open or closed, the impedance Z seen from the input terminal17and the voltage gain G of the interface device16assume different values summarized in the following table, assuming that the polarization stage20is deactivated, in other words that the polarization transistor28is blocked, and assuming the impedance of the analog switch26in the open state to be very high, typically in the vicinity of several tens of MΩ:

This time, it is assumed that the polarization stage20is activated, in other words that the polarization transistor28is on. In the on state, the polarization transistor28has an internal impedance Zpmos. The positive polarization potential Vpol+ is, for example, equal to +15 V, and it is assumed that the voltage Uin is lower than the positive polarization potential Vpol+, which makes it possible to ensure that the polarization diode32is always on. It is also assumed that the polarization resistance30has an impedance Rpol and that the impedance of the analog switch26in the open state is very high, typically in the vicinity of several tens of MΩ. This then yields the following table:

Input impedance Z of theVoltage gain GState of the switch 26device 16of the device 16OpenRser + Rpol + ZpmosRpol+ZpmosRser+Rpol+ZpmosClosedF1 (Uin)A
where:the input impedance Z is a function F1of the input voltage Uin when the switch26is in the closed state, and

The polarization stage20, shown inFIG. 2, provides a positive offset voltage U0to the output voltage Uout delivered by the output terminal18. It also makes it possible, when the device is empty, i.e. when no input voltage Uin is applied on the input terminal17, to have a non-zero voltage on the input17of the device. This is useful for certain types of sensors, in particular discrete avionics sensors.

In the three embodiments described above, adding a protection diode, or leaving the substrates of the NMOS38,50,54and PMOS40,52transistors floating, prevents conduction of parasitic diodes within those transistors.

This parasitic conduction within a transistor should be avoided, as it causes a significant drop in the impedance between the substrate of the transistor and one of the elements among the drain and the source of the transistor. This parasitic conduction also causes very significant heating due to the rise in the current flowing through the parasitic diodes, often creating breakdowns of the diodes, and therefore the destruction of the transistor.

The analog switch26as used in the three embodiments thus prevents the direct polarization of the drain-substrate or source-substrate junctions of the NMOS38,50,54and PMOS40,52transistors, and therefore the degradation or even destruction of those transistors. When voltages exceeding the control voltages62,64,66,67,68or any power supply voltages of the substrates Uss and Udd are applied on the terminals34and36of the switch, the switch26according to the invention remains in the open state, whereas the switch of the state of the art with the NMOS and PMOS transistors connected in parallel is destroyed when such voltages are applied on its terminals.

Electrically insulating the N- or P-type field effect transistors of the analog switch26makes it possible to avoid the degradation or destruction of the transistors after high voltages are applied on the input17of the interface device16, typically voltages in the vicinity of plus or minus 100 V, whereas with the analog switch of the state of the art having a parallel arrangement, a latch-up phenomenon may occur and cause the degradation or even destruction of the transistors.

Connecting the analog switch26to the reference potential Vref, as shown inFIG. 2, also makes it possible, for adaptation resistances22and24of at least several tens of kΩ, or even several hundred kΩ, to guarantee operation in a high inversion regime of the NMOS and PMOS transistors of the switch26, when the latter is closed. This makes it possible to have an internal impedance of the switch26that is substantially constant when said switch26is closed, as illustrated inFIG. 6, which shows the evolution of the impedance of two types of analog switches as a function of the voltage applied to those switches.

The first curve69illustrates the evolution of the impedance of an analog switch of the state of the art, in the closed state, comprising two N- or P-type field effect transistors connected in parallel, as a function of the voltage applied to that switch.

The second curve70illustrates the evolution of the impedance of an analog switch26according to the invention, in the closed state, comprising two N- or P-type field effect transistors connected in series, as a function of the voltage applied to that switch.

The two switches are, in this example, powered by voltages Udd equal to +15 V and Uss equal to −15 V and controlled by control voltages62,64, equal to Udd and Uss, respectively, or +15 V and −15 V, respectively.

For voltages applied to the terminals of the switches higher than the control voltages62,64, the switch of the state of the art with a parallel arrangement has a zero impedance and is destroyed, whereas the switch26according to the invention is not destroyed, but has a very strong impedance, for example greater than several tens of MΩ. Due to the placement of the transistors38,40of the switch26according to the invention in series, and despite control voltages62,64intended to keep the switch26in the closed state, the switch26goes into the open state when voltages higher than the control voltages62,64are applied to its terminals.

The voltage resistance range of such a serial switch26without being destroyed is thus extended relative to that of the parallel switch of the state of the art. The voltages that such a serial switch26can bear in this state are indeed only limited to the breakdown voltages of the electronic components making it up, which depend on the components used.

Furthermore, for voltages applied to the switch26between −5 V and +5 V, the switch26has an impedance in the vicinity of 1 kΩ, depending on the size of the transistors of said switch. The switch26is then in the closed state.

In the closed state, the impedance of a serial analog switch26is substantially constant for a narrow voltage range71. In the example ofFIG. 6, the voltage range71is between −2 V and +2 V.

Optimal operation in the closed state of the serial analog switch26is thus obtained for voltages applied to the switch26comprised in the voltage range71. When this condition is met, the transistors of the switch26operate in a high inversion regime, so as to have a substantially constant internal impedance of the switch26.

One can thus see that connecting such a serial switch26to a reference potential Vref makes it possible to extend the voltage operating range of said switch26relative to that of the parallel switch of the state of the art.

FIG. 7illustrates a second embodiment of the invention, for which the elements similar to those of the first embodiment, previously described, are identified using identical references, and are therefore not described again.

The interface device16comprises a polarization stage72able to provide a negative polarization. The polarization stage72includes an NMOS transistor73, the polarization resistance30, and the protection diode32, connected in series.

In the polarization stage72, the polarization resistance30is connected between the NMOS transistor73and the protection diode32. The anode of the diode32is connected to the output terminal18, and the cathode of the diode32is connected to the polarization resistance30.

The polarization stage72is on the one hand connected to the output terminal18, and on the other hand can be connected to a negative polarization potential Vpol−, so as to provide a negative offset voltage U0to the output voltage Uout delivered by the output terminal18.

According to this embodiment of the invention, the input impedance Z, seen from the input terminal17, and the voltage gain G of the interface device16, depending on whether the analog switch26is open or closed, have values identical to those of the first embodiment.

The advantages of this second embodiment of the interface device16are identical, relative to the analog switch26and the polarization stage72, to those of the first embodiment, and are therefore not described again.

FIG. 8illustrates a third embodiment of the invention for which the elements similar to those of the first embodiment, previously described, are identified using identical references, and are therefore not described again.

According to the third embodiment of the invention, the interface device16includes an input terminal74, an output terminal76, a reference terminal77having a reference potential Vref, the polarization stage20able to provide a positive polarization, as well as a first resistance78, a second resistance80, a third resistance82, a fourth resistance84and a fifth resistance86. The interface device16also includes a first analog switch26A and a second analog switch26B. The first analog switch26A is connected in parallel with the third resistance82. The second analog switch26B is connected in parallel with the fourth resistance84.

The output terminal76corresponds to the connection node between the two analog switches26A,26B or, in other words, the connection node between the third and fourth resistances82,84.

The first resistance78, the second resistance80and the third resistance82are connected in series in that order between the input terminal74and the output terminal76. The first and second resistances78,80are connected to one another at a connection node88, and the second and third resistances80,82are connected to one another at a connection node89.

The fourth resistance84and the fifth resistance86are connected in series, the fourth resistance84being connected to the output terminal76, and the fifth resistance86being connected to the reference terminal77.

The polarization stage20, comprising a PMOS transistor capable of providing a positive polarization, is on the one hand connected to the connection node88, and on the other hand can be connected to the positive polarization potential Vpol+.

Alternatively, the polarization stage comprises an NMOS transistor able to provide a negative polarization as described inFIG. 7. It is on the one hand connected to the connection node88, and on the other hand can be connected to the negative polarization potential Vpol−.

For reference voltages of the circuit, and polarization and control voltages of the given switches, the values of the first, second and fifth resistances78,80and86are chosen so that for any voltage Uin comprised in the desired operating interval, the voltage applied to the terminals of each switch26A,26B in the closed state remains in the voltage range71.

For a reference potential Vref equal to 0 V, a polarization potential Vpol+equal to +5 V, and control voltages equal to +15 V or −15 V, the first, second and fifth resistances78,80and86have, for example, the values of 50 kΩ, 30 kΩ and 1 kΩ, respectively.

The first analog switch26A is denoted S1, and the second analog switch26B is denoted S2. The switch S1is connected in parallel with the third resistance82, and the switch S2is connected in parallel with the fourth resistance84.

In the closed state, the two analog switches S1and S2have a same internal impedance Zon. The first, second, third, fourth and fifth resistances78,80,82,84,86respectively have impedances R1, R2, R3, R4, R5.

Depending on whether the analog switches S1and S2are open or closed, the input impedance Z seen from the input terminal74and the voltage gain G of the interface device16have different values summarized in the table below, assuming that the polarization stage20is deactivated, Zon is small compared to R3and R4, and the impedance of the analog switches S1and S2in the open state is very high, typically in the vicinity of several tens of MΩ:

The polarization stage20provides a positive offset voltage U0to the output voltage Uout delivered by the output terminal76.

The choice of the first, second and fifth resistances78,80and86makes it possible to guarantee the operation in a high inversion regime of the field effect transistors of the analog switches26A,26B when said switches are closed. This characteristic of the interface device16makes it possible to have a substantially constant internal impedance of the switches26A,26B when said switches are closed.

Furthermore, the interface device16according to this third embodiment makes it possible, compared with the fourth embodiment described hereafter in reference toFIG. 9, to decrease the surface occupied by the different resistances, and thus to substantially reduce the manufacturing costs.

The other advantages of this third embodiment, relative to the analog switches26A,26B and the polarization stage20, are identical to those of the first embodiment, and are therefore not described again.

FIG. 9illustrates a fourth embodiment of the invention for which the elements similar to those of the first embodiment, previously described, are identified using identical references, and are therefore not described again.

The interface device16according to the fourth embodiment of the invention includes an input terminal90, an output terminal92, a reference terminal93having a reference potential Vref, three polarization stages20each able to provide a specific positive polarization, as well as a first resistance94, a second resistance96, a third resistance98, a fourth resistance100, a fifth resistance102and a sixth resistance104. The interface device16also includes three analog switches26.

The interface16according to this fourth embodiment corresponds to the cascading association of three interface devices ofFIG. 2.

Alternatively, one skilled in the art will understand that it is also possible to associate a number N of devices ofFIG. 2in a cascading manner, N being an integer greater than or equal to two.

Each analog switch26is on the one hand connected to one resistance among the fourth, fifth and sixth resistances100,102,104, and on the other hand connected to the reference terminal93.

The first, second and third resistances94,96and98are connected in series between the input terminal90and the output terminal92. The first and second resistances94,96are connected to one another at a first connection node106, and the second and third resistances96,98are connected to one another at a second connection node108.

Each polarization stage20is connected on the one hand to a respective connection node106,108or to the output terminal92, and can be connected on the other hand to a positive polarization potential Vpol+1, Vpol+2, Vpol+3, respectively.

Alternatively, the three polarization stages can provide a negative polarization as shown inFIG. 7, each polarization stage being connected on the one hand to a respective connection node106,108or to the output node92, and being able to be connected on the other hand to a negative polarization potential Vpol−1, Vpol−2, Vpol−3, respectively.

Alternatively, one skilled in the art will understand that it is also possible to associate a number N of devices ofFIG. 7in a cascading manner, N being an integer greater than or equal to two.

The three analog switches26are differentiated from one another: a first switch26is designated switch S3, a second switch26is designated switch S4, and the third switch26is designated switch S5.

The three analog switches26are respectively denoted S3, S4and S5, the switch S3being connected to the first connection node106by means of the fourth resistance100, the switch S4being connected to the second connection node108by means of the fifth resistance102, and the switch S5being connected to the output terminal92by means of the sixth resistance104.

Depending on whether the analog switches S3, S4and S5are open or closed, the input impedance Z seen from the input terminal90and the voltage gain G of the interface device16have different values summarized in the following table, assuming that the three polarization stages20are deactivated and the impedance of the analog switches S3, S4and S5in the open state is very high, typically in the vicinity of several tens of MΩ:

The three polarization stages20provide a positive offset voltage U0to the output voltage Uout delivered by the output terminal92.

More generally, the number of possible values for the input impedance and the voltage gain of the interface device16depends on the number of analog switches26used.

One can thus see that, compared with the interface device16according to the first embodiment, the interface device according to this embodiment makes it possible to obtain a larger number of possible values for the input impedance and the voltage gain of the device.

Furthermore, the interface device16according to this fourth embodiment is easier to implement than the interface device according to the third embodiment because it does not impose any particular choices on the values of the resistances.

The other advantages of this fourth embodiment, relative to the analog switches26and the polarization stages20, are identical to those of the first embodiment, and are therefore not described again.