Analog-to-digital conversion apparatus for video signal

An analog-to-digital conversion circuit for converting an input analog video signal to a digital video signal includes a sync separator for deriving from the analog video signal a horizontal synchronizing signal, and a voltage controlled oscillator (VCO) for producing a clock signal. An A/D converter converts the input analog signal to digital video based on the timing of the clock signal. The VCO, which produces the clock signal, is controlled by a circuit which compares the phase of the horizontal synchronizing signal extracted from the digital video signal to the phase of the clock signal. The clock signal is therefore highly stable and free of any adverse effects generated by drifts of the synchronizing signal separator and adverse effects produced by a lowpass filter employed in the circuit.

BACKGROUND OF THE INVENTION 
This invention relates generally to a video analog-to-digital conversion 
(hereinafter referred to as the video "A/D converter" or alternately as 
the "A/D conversion circuit) circuit, and more particularly to a circuit 
for generating a clock signal which is synchronized to a digital video 
signal produced by the A/D converter. 
In conventional video A/D converters designed for handling a video signal, 
a synchronizing signal is extracted from an input analog video signal by a 
synchronizing signal separator circuit. A clock signal is generated by a 
phase locked loop on the basis of the separated synchronizing signal. In 
other words, the video A/D converter contains, in addition to a 
conventional A/D converter, a voltage control oscillator (VCO) for 
generating the clock signal, a counter for frequency-dividing the clock 
signal to generate a frequency divided output signal having a frequency 
equal to that of the synchronizing signal and a phase comparator for 
comparing the phase of the frequency division output signal from the 
counter to the output of the separated synchronizing signal to provide a 
control voltage for the VCO. The clock signal from the VCO is supplied to 
the A/D converter which provides a digital (PCM) video signal output. The 
video A/D converter also includes a lowpass filter for preventing folded 
noise, the filter being located as a pre-stage circuit of the A/D 
converter. 
The synchronizing signal in the synchronizing signal separator is obtained 
by a clipper (comparator) after frequency band limitation is made by a 
lowpass filter in order to remove any erroneous components, i.e., a 
chrominance component and a noise component contained in the video signal. 
Consequently and due to the lowpass filter, a drift is generated and since 
the lowpass filter is disposed before the A/D converter, a drift or fixed 
delay also occurs. Further, the A/D converter itself produces variations 
in conversion time. Therefore, synchronisation between the synchronizing 
signal in the digital video signal and the clock signal supplied to the 
A/D converter for effecting quantitization is inaccurate. The phase 
difference therebetween sometimes may reach as much as a full clock 
period. 
If the abovementioned clock signal is then used to produce a control signal 
for mixing, for example, plural digital video signals in a digital video 
system where all video signals are processed in digital form, the phase 
difference between the synchronizing signal contained in the digital video 
signal and the clock signal causes a delicate time lag in a mixed video 
signal. In the worst case, horizontal blanking appears in the active video 
portion when a plurality of digital video processing equipment are 
connected in series in the digital video system. 
SUMMARY OF THE INVENTION 
It is therefore a primary object of the present invention to provide a 
video A/D converter circuit which can generate a clock signal which is 
accurately synchronized to a synchronizing signal contained in the 
digitised video signal. 
In accordance with the present invention, there is provided an A/D 
conversion circuit which comprises an A/D converter for quantizing an 
input analog video signal to obtain a digital video signal, means for 
separating a horizontal synchronizing pulse from the input analog video 
signal and outputting it as a first horizontal synchronizing signal, a 
voltage control oscillator (VCO) for generating a clock signal, a 
frequency divider for counting down the clock signal to generate a second 
horizontal synchronizing signal, means for obtaining first data 
representing a substantially intermediate value of the amplitude of the 
tip of the horizontal synchronizing signal contained in the digital video 
signal by use of the first horizontal synchronizing signal, means for 
obtaining second data by sampling the digital video signal at the timing 
of the second horizontal synchronizing signal, means for obtaining third 
data corresponding to a difference between the first and second data, and 
means for feeding back the third data as a control voltage to the VCO. 
In the present invention, the phase-locked loop is formed by using the 
phase of the horizontal synchronizing signal contained in the digital 
video signal, and any adverse influences of the drifts of the 
synchronizing signal separator and the folded noise prevention lowpass 
filter can be removed.

DESCRIPTION OF THE PRIOR ART 
Referring to FIG. 1, a prior art A/D conversion circuit receives an input 
analog video signal at an input terminal 1. The video signal is passed 
through a buffer amplifier 2 having a low output impedance characteristic 
and then to a folded noise prevention lowpass filter 3 and to a 
synchronization signal separator 4. Synchronization signal separator 4 
delivers an input horizontal synchronizing signal to supply it to one of 
inputs of a phase comparator 5. Voltage control oscillator (VCO) 6 
generates a clock signal and a frequency-dividing counter 7 produces a 
horizontal synchronizing signal by dividing the clock signal received from 
VCO 6. The horizontal synchronizing signal is supplied to the other input 
of phase comparator 5. Phase comparator 5 outputs a feed body signal 
representing the phase difference between the input horizontal 
synchronizing signal and the produced horizontal synchronizing signal and 
supplied this feedback signal to the VCO 6 as a control signal. Therefore, 
the clock signal is synchronized with the input horizontal synchronizing 
signal. 
The clock signal thus obtained is supplied to A/D converter 8 which 
convertes the input analog video signal delivered from the lowpass filter 
3 into a digital (PCM) video signal. The digital video signal is supplied 
to an output terminal 9. 
The present invention results from the discovery that if the clock signal 
of the prior art of FIG. 1 is used in a digital video processing system, a 
problem arises in that the phase of the synchronizing signal contained in 
the output digital video signal at the terminal 9 and the phase of the 
clock signal are not accurately synchronized to each other. 
DESCRIPTION OF A PREFERRED EMBODIMENT 
FIG. 2 is a block diagram showing one embodiment of the present invention. 
As a note it is pointed out that the frequency of the clock signal in this 
embodiment is 13.5 MHz of the standard of the component system and is 858 
times the frequency of the horizontal synchronizing signal. Theefore, a 
voltage control oscillator (VCO) 6 generates a clock signal of 13.5 MHz. 
This embodiment employs buffer amplifier 2, lowpass filter 3, synchronizing 
signal separator 4, voltage controlled oscillator (VCO) 6, 
frequency-dividing counter 7, A/D converter 8, and output terminal 9 which 
identically correspond to the similarly numbered elements of FIG. 1. The 
embodiment further comprises a pulse generator 12 which generates a 
pedestal sample pulse S.sub.p and a sync tip sample pulse S.sub.s based on 
a horizontal synchronization pulse delivered from synchronizing signal 
separator 4. In the embodiment, this horizontal synchronizing pulse from 
separator 4 is referred to as a first horizontal synchronizing signal. 
FIG. 3 shows the timings of the pedestal sample pulse S.sub.p and the sync 
tip sample pulse S.sub.s with the horizontal synchronizing signal. Both 
pedestal sample pulse S.sub.p and the sync tip sample pulse S.sub.s are 
latched by latch circuits 13 and 14, respectively, in response to clock 
signal from the VCO 6 in order to accurately synchronize them to the clock 
signal. Therefore, latch circuits 13 and 14 generates a synchronized 
pedestal sample pulse S.sub.p ' and a synchronized sync tip sample pulse 
S.sub.s '. Other latch circuits 15 and 16 latch the digital PCM video 
signal delivered from the A/D converter 8 in response to the synchronized 
pedestal sample pulse S.sub.p ' and the synchronized sync tip sample pulse 
S.sub.s ', respectively. As result, latch circuits 15 and 16 hold pedestal 
data corresponding to the pedestal level and sync tip data corresponding 
to the sync tip level, respectively. A calculating circuit 17 produces the 
average of the pedestal data and the sync tip data. Therefore, this 
average corresponds to the intermediate level V.sub.a between the pedestal 
level and the sync tip level as shown in FIG. 3 and is referred to as 
first PCM data. 
Frequency dividing counter 7 generates a second horizontal synchronizing 
signal by frequency-dividing the clock signal from the VCO 6 by 858. 
Another latch circuit 18 latches the digital PCM video signal from A/D 
converter 8 in response to the timing of the edge of the second horizontal 
synchronizing signal to hold second PCM data. In the embodiment, the first 
PCM data is respective of an ideal value at the edge of a horizontal 
synchronizing signal or, in the other words, target data to which the 
second PCM data should be equal to when the clock signal is synchronized 
with the horizontal synchronizing signal contained in the PCM video 
signal. A calculating circuit 19 calculates the difference data between 
the first PCM data and the second PCM data. The difference data are 
supplied through a D/A converter 20 the VCO 6 as a control signal. Thus, 
the VCO 6 is controlled to generate the clock signal such that the 
difference data between the first PCM data and the second PCM data tends 
toward zero. Accordingly, the frequency of the clock signal generated by 
the VCO 6 is accurately 858 times horizontal synchronizing frequency and 
the second horizontal synchronizing signal produced by frequency-dividing 
counter 7 is completely coincident with the horizontal synchronizing 
signal contained in the PCM video signal. 
As described above, the present invention provides an A/D conversion 
circuit which can produce a highly accurate and stable clock signal, free 
of any adverse effects generated by the drifts of the synchronizing signal 
separator and the noise prevention lowpass filter. This is provided by 
directly comparing the phase of the horizontal synchronizing signal in the 
digital video signal with the phase of the clock signal. 
From another viewpoint, the circuit arrangement of the present invention 
can be regarded as a highly stable flywheel type synchronizing signal 
reproducing circuit in which the horizontal synchronizing signal is 
outputted from a terminal 11 (FIG. 2). Therefore, in an overall digital 
video system, the clock signal and the horizontal synchronizing signal can 
be commonly used for a plurality of video sources and hence the A/D 
conversion circuit can be produced more economically. Further, in addition 
to the horizontal synchronizing signal, other synchronizing signals such 
as a vertical synchronizing signal, a burst flag signal and a blanking 
signal which are fully synchronized to the digital video signal can be 
obtained based on the synchronized clock signal according to the present 
invention.