Devices for the self-adjusting setting of the operating point in amplifier circuits with neuron MOS transistors

A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.

BACKGROUND OF THE INVENTION 
In particular for amplifier circuits that are linear with respect to the 
large signal and that have neuron MOS transistors, there is a great 
potential for many analog circuit applications, such as for example video 
and audio applications, sensor technology, analog computers, fuzzy 
circuits and neural networks. 
From the IEEE Transactions on Electron Devices, vol. 39, no. 6, June 1992, 
the construction and manner of functioning of a neuron MOS transistor and 
its use as an amplifier are known. 
If, using a neuron MOS transistor, an amplifier, or, respectively, summing 
amplifier, is realized that is linear with respect to the large signal, as 
a rule it exhibits in its transmission characteristic curve an undefined 
zero point displacement or, respectively, a displacement of the operating 
point, which for example is due to a process-caused charging of the 
floating gate of the neuron MOS transistor. 
SUMMARY OF THE INVENTION 
It is an object of the invention to provide devices in which, in at least 
one such amplifier stage, a defined zero point voltage, dependent on a 
settable target value for the zero point voltage, is enabled with the 
smallest possible component outlay. 
In general terms, the present invention is a device for self-adjusting 
setting of the operating point in amplifier circuits with neuron MOS 
transistors. An adjustment stage and at least one amplifier stage, of 
essentially identical construction thereto, are provided. Each have a 
series circuit of an MOS field effect transistor and a neuron MOS 
transistor. All gates of the MOS transistors are connected with a common 
voltage source. The adjustment stage and the at least one amplifier stage 
are connected such that an equally large current flows through them. Input 
gates of the neuron MOS transistor belonging to the adjustment stage, 
which gates represent amplifier inputs in the at least one amplifier stage 
of essentially identical construction, are connected with reference 
potential. A feedback gate of the neuron MOS transistor belonging to the 
adjustment stage is connected with a voltage source that supplies a target 
value for the zero point voltage of the at least one amplifier stage. The 
transistor is fed back to an output of the respective amplifier stage in 
the at least one amplifier stage of essentially identical construction. 
Advantageous developments of the present invention are as follows. 
An equally large current in the adjustment stage and in the at least one 
amplifier stage is produced by providing a multiple current mirror with an 
input and at least one output. The input of the multiple current mirror is 
connected to the adjustment stage. One of the at least one outputs of the 
multiple current mirror is connected to a respective amplifier stage. 
An equally large current is produced in the adjustment stage and in the at 
least one amplifier stage by providing a multiple current mirror or a 
current source circuit with an input, a first output and at least one 
additional output. The input of the multiple current mirror or of the 
current source circuit is connected to the one current source that 
supplies the current. The adjustment stage is connected to the first 
output of the multiple current mirror or the current source circuit. One 
of the at least one further outputs of the multiple current mirror or of 
the current source circuit is connected to a respective amplifier stage. 
The neuron MOS transistors of the adjustment stage and of the at least one 
amplifier stage has an additional adjustment gate that is connected with 
the output of the adjustment stage. 
Using electronic switches one of the at least one amplifier stages is 
switched at regular time intervals as an adjustment stage, whereby the 
input gates of the neuron MOS transistor can be switched selectively 
either to inputs of the amplifier stage or to reference potential. An 
adjustment gate of the neuron MOS transistor can be switched to an 
internal output of the amplifier stage and a feedback gate can be switched 
to a voltage source with the target value of the zero point voltage. The 
internal output can be switched to the feedback gate and to an external 
output of the amplifier stage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 shows an amplifier circuit that is linear with respect to the large 
signal, with an neuron MOS transistor comprising n inputs. Given 
symmetrical supply voltages, its transmission function is 
##EQU1## 
V.sub.OUT thereby stands for the output voltage of the circuit and 
V.sub.IN,i stands for the input voltage at the I-th input of the circuit 
IN.sub.i. The parameters w.sub.IN,i stand for what is known as the 
weighting of the respective coupling gates, which are calculated via the 
ratio of the coupling capacity C.sub.IN,i between the input IN.sub.i and 
the floating gate and the sum C.sub.ges of all capacitances of which one 
electrode represents the floating gate: 
##EQU2## 
The parameter C.sub.FG in equation (3) thereby stands for the capacitance 
between the floating gate and the channel region, including the 
source-drain overlap capacitances. A definition analogous to that of the 
parameters w.sub.IN,i holds for the parameter w.sub.OUT which represents 
the weighting of the coupling gate connected with the amplifier output 
OUT. 
If a possible process-caused charging of the floating gate to a potential 
V.sub.QP and a potential contribution V.sub.CH, coupled in via the channel 
region, are also taken into account, there results a floating gate level 
##EQU3## 
from the solution of this equation for V.sub.OUT and the combination of 
the voltages V.sub.FG, V.sub.QP and V.sub.CH to the zero point voltage 
##EQU4## 
schematically shows the output voltage VOUT according to equation (1) as a 
function of the weighted sums of the input signals for various values 
V.sub.0. The zero point voltage V.sub.0 thereby indicates the axis segment 
in which the transmission function according to equation (1) intersects 
the ordinate, on which the weighted sum of the input signals is here 
plotted. In many applications, it is desirable or necessary to be able to 
assign a particular value to the zero point voltage V.sub.0. In many 
applications, this will be the value V.sub.0 =0 V. This corresponds to a 
setting of the operating point of the amplifier circuits or, respectively, 
to a compensation of the DC portion of the transmission function according 
to equation (1). 
FIG. 3 shows as an example a first construction of the inventive device in 
which identical blocks 0 . . . k, respectively of a series circuit of an 
n-channel MOS transistor T20,0 . . . T20,k and of a respective neuron MOS 
transistor T10,0 . . . T1O,k, as well as a multiple current mirror circuit 
SS, are provided. All gates of the transistors T20,0 . . . T20,k are 
connected with a voltage source V20, and a respective first terminal of 
the blocks, which at the same time forms a first terminal of the neuron 
MOS transistor, is connected with the negative supply voltage VSS. The 
second terminal of the block 0, which at the same time forms a second 
terminal of the n-channel MOS transistor T20,0, is connected with an input 
E of the multiple current mirror SS. The respective second terminals, 
which at the same time form the second terminals of the respective 
n-channel MOS transistors T20,1 . . . T20,k, are connected with the 
respective outputs A1 . . . Ak of the multiple current mirror. The block 0 
is connected in such a way that the gate of the neuron MOS transistor with 
the output weighting w.sub.out receives the target value V.sub.0,soll of 
the zero point voltage, and all gates with the input weightings w.sub.IN,1 
. . . w.sub.IN,n receive reference potential. The block 0 connected in 
this way forms a controlled current sink that draws a current I at the 
input E that is dependent on the predetermined target value V.sub.0,soll 
of the zero point voltage. 
To the extent that the blocks 0 . . . k all comprise the same layout, the 
topology of the immediate environment of the blocks 0 . . . k is 
identical, and the distance of these blocks from one another on the chip 
is not too large, it can be assumed that the voltage V.sub.QP caused by 
the process-caused charging of the floating gate is equal in the equations 
(4) and (5) for all stages or, respectively, neuron MOSFETs T10,0 . . . 
T10,k. Under the assumption that all amplifier stages are operated with 
the same cross-current I, this means that the same voltage V.sub.0 arises 
for all stages. 
Under the condition 
##EQU5## 
i.e., that at the inputs of an amplifier stage j=1 . . . k the 
contribution of the input signals V.sub.IN,i (T10,j) is identical to the 
contribution of the input signals V.sub.IN,i (T10,0) in block 0, namely 0, 
the voltage V.sub.OUT =V.sub.0 must necessarily arise at the output of an 
amplifier stage for which the equation (7) is fulfilled, since the 
respective neuron MOS transistor T10,j of an amplifier stage j-1 . . . k 
is then located in exactly the same operating point as the neuron MOS 
transistor T10,0 in the block 0. 
The preconditions additionally introduced above practically present no 
limitation, since for a given amplifier stage whose neuron MOS transistor 
is configured in a particular way it is always possible to construct a 
suitable current sink via layout measures, i.e. via a copy of a block and 
a corresponding alteration of the connection of the coupling gates. 
If several amplifier stages are used in one circuit, which however are all 
configured differently, or else which are very far apart from one another 
on the chip for certain reasons, a separate current sink must be built 
into each amplifier circuit. In this case as well, the advantages of 
neuron MOS amplifiers in comparison with known solutions are obtained, 
i.e. in particular their low space and power consumption. 
FIG. 4 shows a second construction of the invention, which differs from the 
one shown in FIG. 3 in that an additional gate with an adjustment 
weighting W.sub.ADJ is respectively provided for the neuron MOS 
transistors T10,0 . . . T10,k, and all these additional gates are 
connected with an additional output A0 of the current mirror SS, and in 
that in block 0 the terminal of the transistor T20,0 is not connected with 
the current mirror input E, but rather with the additional output A0, and 
that in place of the block 0 a constant current sink IC draws a current I. 
From a circuit-oriented perspective, the circuits in FIG. 3 and FIG. 4 
differ with respect to their principle of operation in that the stage 0 in 
FIG. 3 itself generates a reference current, which is then mirrored as 
precisely as possible via the current mirror SS and must be impressed onto 
the stages 1 . . . k. In contrast, in FIG. 4 a current that is equal for 
all stages and is also predetermined is impressed on all stages, i.e. on 
the stages 1 . . . k, and in particular also on the reference stage 0. 
Here the stage 0 accordingly cannot operate as a reference current 
generator, since a current is predetermined for it; rather, it functions 
as a reference voltage generator, whereby the reference voltage it 
produces is supplied to the further stages 1 . . . k, as described above. 
This difference has consequences with respect to the demands on the 
current mirror SS: While in FIG. 3 a circuit SS is necessary that has an 
exact current mirror characteristic, in the circuit according to FIG. 4 it 
is necessary only to fulfill the requirement that a current source circuit 
be present that provides the same current at all its outputs. This means 
in particular that in FIG. 4, in place of an exact current mirror SS, in 
principle all circuits can be used that produce the same output currents 
using an arbitrary reference quantity k+1, which output currents are 
supplied to the stages 0 . . . k. It is thereby sufficient if the 
functional connection between the reference quantity and the output 
currents is known only approximately and is not described by an exact 
mirror relationship. As will be discussed later in connection with FIGS. 
6-8, there are circuits that derive the reference for exactly equal output 
currents from a current impressed at the input side, but whose ratio 
between the input current and the output current does not exhibit the 
exact characteristic required by current mirror circuits. 
The incorporation of such a coupling gate, with the weighting W.sub.ADJ, 
into a neuron MOS amplifier according to FIG. 1 does have the effect that 
the absolute values of the weightings w.sub.IN,i with I=1 . . . n and 
w.sub.OUT decrease, but the ratios w.sub.IN,i /w.sub.IN,m (I, m=1 . . . n) 
or, respectively, w.sub.IN,i /w.sub.OUT (I=1 . . . n) remain preserved. 
This connection has the effect that, as desired, the voltage V.sub.0 in the 
transmission function of all amplifier stages 1 . . . k takes on the 
target value V.sub.0,soll, which is established by the following 
calculation: 
If the system of equations (1) . . . (5) in the present case modifies the 
amplifier stages in FIG. 4 expanded by a further coupling gate with the 
weighting w.sub.ADJ, the following output voltages result for the 
amplifier stages in the blocks 1 . . . k: 
##EQU6## 
Equations (9) and (10) likewise hold for T10,0; the relations analogous to 
equation (8), i.e. the transmission function of T10,0, is: 
##EQU7## 
Since the inputs IN.sub.i (T10,0) are all connected with the GND 
potential=0 V, the sum in equation (11) supplies no contribution, so that 
equation (11) can be simplified to 
##EQU8## 
Substitution of equation (12) in equation (8) yields 
##EQU9## 
i.e. the desired transmission function for the amplifier stages 1 . . . k. 
FIG. 5 shows a third construction of the inventive device in which the 
direct voltage portion of the transmission function or, respectively, the 
zero point voltage V.sub.0 ensues by means of feedback and subtraction of 
the output voltage, carried out periodically. In a way similar to FIG. 4, 
the neuron MOSFET T10 of the amplifier stage is expanded in relation to 
the amplifier stage in FIG. 1 by an additional coupling gate with the 
weighting w.sub.ADJ. The weighting w.sub.ADJ is thereby exactly as large 
as the weighting w.sub.OUT. 
A capacitor C.sub.HELP, which serves for the storage of a voltage value, 
can be connected parallel to the weighting gate with the weighting 
w.sub.ADJ, against GND or against another constant voltage level. However, 
this measure is not absolutely required for operation, since the coupling 
gate with the weighting w.sub.ADJ alone can also already serve as the 
storage capacitor. 
Switches S, which enable a separation of the inputs from the coupling 
gates, are inserted between the inputs IN.sub.1 . . . IN.sub.n and the 
associated coupling gates. These switches S are controlled by a signal 
.PHI..sub.1. For further explanations, with respect to the switch S it 
should be the case that it is closed by an H level and opened by an L 
level. Also, additional switches S', which are controlled by a signal 
.PHI..sub.2 and via which the potential of the coupling gate can be 
connected with GND, are located at each coupling gate that can be 
connected with an input. Via a switch S1 driven with the signal 
.PHI..sub.1, a drain node OUT,int of the transistor T20 can be connected 
with the output OUT of the circuit, and via a switch S2 that is likewise 
controlled with the signal .PHI..sub.1 the drain node OUT,int of the 
transistor T20 can be connected with the coupling gate with the weighting 
w.sub.OUT. The node OUT,int can in addition be connected with the coupling 
gate with the weighting w.sub.ADJ via a switch S3 controlled via the 
signal .PHI..sub.2, and an additional switch S4 controlled via the signal 
.PHI..sub.2 can connect the coupling gate with the weighting w.sub.OUT 
with a voltage source that supplies the target value V.sub.0,soll of the 
zero point voltage of the transmission function. 
If the circuit is operated with the pulse schema, likewise drawn into the 
circuit diagram, for the signals .PHI..sub.1 and .PHI..sub.2, the circuit 
has the desired transmission function during the phases in which 
.PHI..sub.1 has the H level. During the phases in which the signal 
.PHI..sub.2 takes on the H level, the transmission function is again 
compensated anew each time. 
The compensation takes place by storing a particular potential value at the 
coupling gate with the weighting w.sub.ADJ or, respectively, at the 
capacitor that results from the parallel connection of this coupling gate 
and the capacitor C.sub.HELP, which potential value causes the adjustment 
of the transmission function, as is explained in more detail below. It is 
necessary to carry out this compensation periodically, since, due to the 
non-ideality of real switches S, the charge located at the coupling gate 
with the weighting w.sub.ADJ, including the optionally present capacitor 
C.sub.HELP connected in parallel, can change during the operation of the 
circuit, due to leakage currents over the switch S that connects this 
coupling gate with the node OUT,int. The clock frequency of the adjustment 
periodically carried out thus depends on the quality of the switch with 
respect to its leakage characteristics in the switched-off state and on 
the requirements of precision of the entire circuit. 
For a time at which .PHI..sub.2 is at the H level and .PHI..sub.1 is at the 
L level, the transmission function is: 
##EQU10## 
Since the coupling gates with the weightings w.sub.IN,i, I=1 . . . n, are 
all connected with GND potential=0 V, the sum in equation (14) makes no 
contribution, so that equation (14) can be simplified to 
##EQU11## 
The node with which the coupling gate with the weighting w.sub.ADJ is 
connected is thus charged to the voltage V.sub.OUT,int (.PHI..sub.2 =H). 
If .PHI..sub.2 again takes on the L level, this potential is maintained at 
this node. If .PHI..sub.1 thereupon takes on the H level, the overall 
stage has the transmission function 
##EQU12## 
Given the dimensioning w.sub.ADJ =w.sub.OUT introduced above, substitution 
of equation (15) into equation (16) yields the desired transmission 
function: 
##EQU13## 
The advantage of the construction of the inventive device according to FIG. 
5 is that no additional reference neuron MOSFET T10,0 is required for 
which the precondition must be fulfilled that the process-caused charging 
of its floating gate is exactly as large as the charging of the floating 
gates of the neuron MOSFETs in the actual amplifier stages of blocks 1 . . 
. k. 
Alongside the precondition that the process-caused charging of the floating 
gate in the respective reference stages is exactly as large as the 
charging of the floating gates of the neuron MOSFETs in the actual 
amplifier stages, for the circuits according to FIG. 3 and FIG. 4 the 
precondition must be fulfilled that the geometries of the transistors 
agree with one another as far as possible. Due to statistical 
fluctuations, called matching errors, small differences in the dimensions 
characteristic for the transistors are however always present, despite 
identical layouts. In this connection, in the circuit according to FIG. 5 
it is advantageous that no reference neuron MOSFET is used, and matching 
problems thus cannot be a factor. 
A combination in which, as shown in FIG. 5, a stage operates, by means of 
switching over, both as an adjustment stage and also as an amplifier 
stage, and in which further amplifier stages, as shown in FIG. 3 or 4, are 
simultaneously adjusted, is likewise possible. 
FIGS. 6 and 7 show exemplary embodiments for the multiple current mirror SS 
of FIGS. 3 and 4, whereby FIG. 6 shows a detail circuit of a simple 
multiple current mirror and FIG. 7 respectively shows a detail circuit of 
a cascaded multiple current mirror. These two circuits differ in that the 
circuit according to FIG. 7 has an essentially higher output resistance, 
and thereby has an essentially lower dependence of the output current on 
the voltage present at the current source output than the circuit 
according to FIG. 6, which has an advantageous effect on the linearity of 
the amplifier stages. Nonetheless, in the circuit according to FIG. 6 the 
required least voltage drop between VDD and output is smaller than in the 
circuit according to FIG. 7, which in turn increases the controllability 
of the amplifier stages. 
FIG. 8 shows a current source circuit with an arbitrary number of identical 
outputs. It is hereby to be remarked that in the circuit of FIG. 8 a 
transistor is identified with "|" whose transistor width is only 0.1 to 
0.25 of the transistor width otherwise used. 
The principle of operation of this circuit has the effect that on the one 
hand it has a fairly large output resistance, whereby the required minimum 
voltage drop between VDD and output is however considerably smaller than 
in the case of the circuit according to FIG. 7. In addition, however, the 
principle of operation of this circuit has the effect that while all 
output currents are identical, they never fully achieve the magnitude of 
the input current. However, corresponding to the discussion of the 
function of the current mirror SS in the circuit according to FIG. 4, the 
last-named characteristic does not result in a limitation in this case, so 
that the circuit according to FIG. 8, due to its good characteristic for 
combining a high output resistance with a small required least voltage 
drop between VDD and output, is excellently suited for use in the circuit 
according to FIG. 4. 
Of course, it is possible to construct all the devices shown in the figures 
in complementary fashion as well, whereby the terminals VDD and VSS must 
be exchanged and the n-channel types used must be replaced with p-channel 
types. 
The invention is not limited to the particular details of the apparatus 
depicted and other modifications and applications are contemplated. 
Certain other changes may be made in the above described apparatus without 
departing from the true spirit and scope of the invention herein involved. 
It is intended, therefore, that the subject matter in the above depiction 
shall be interpreted as illustrative and not in a limiting sense.