Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof

A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.

TECHNICAL FIELD

The disclosure relates in general to a package structure and manufacturing method, and more particularly to a package substrate, a manufacturing method of the package substrate, a package structure for a semiconductor device and a manufacturing method thereof.

BACKGROUND

Along with the popularity of electronic products in people's daily life, the demand for semiconductor devices is increasing. As the design of semiconductor device is directed towards thinness, when the semiconductor device is downsized, the quantity of I/O pins increases, not decreases, making the pitch/width of the wire further decreased and directed towards the design of fine pitch such as 50 μm or even below 35 μm.

However, during the process of bonding the semiconductor device to a package substrate by way of flip-chip assembly, short-circuit may be occurred due to the bridging between two adjacent conductive bumps when the solder is reflowed at a high temperature. In addition, when the solder is not confined by a solder mask which restricts its flow on the wire layer, the solder reflowed at a high temperature may be easily overspread along the wire layer, hence reducing the height between the flipped semiconductor device and the package substrate. As the height is decreased, it will be harder for the underfill layer to be interposed into the gap between the semiconductor device and the package substrate, and the reliability of the package will therefore deteriorate.

SUMMARY

The disclosure is directed to a package substrate, a manufacturing method of the package substrate, a package structure for a semiconductor device and a manufacturing method thereof capable of increasing the reliability for packaging the semiconductor device and conforming to the design of fine pitches.

According to one embodiment, a package substrate comprising a dielectric layer, a first conductive layer and a second conductive layer is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface is exposed from the top surface and further has the same plane with the top surface or is concaved to the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface is exposed from the bottom surface and further has the same plane with the bottom surface or is concaved to bottom surface.

According to another embodiment, a manufacturing method of a package substrate comprising the following steps is provided. A conductive substrate is provided. A first photoresist layer is formed on the conductive substrate, wherein the first photoresist layer is patterned to form several first openings exposing a portion of the conductive substrate. A first conductive layer is formed in the first openings. A second photoresist layer is formed on the first photoresist layer and the first conductive layer, wherein the second photoresist layer is patterned to form several second openings exposing a portion of the first conductive layer. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and the second photoresist layer are removed. A dielectric layer is formed on the conductive substrate, wherein the dielectric layer covers the first conductive layer, the second conductive layer and a portion of the conductive substrate. A portion of the dielectric layer is removed, and a surface of the second conductive layer is exposed from the bottom surface of the dielectric layer and has the same plane with the bottom surface of the dielectric layer. A third photoresist layer is formed on the conductive substrate and the dielectric layer, wherein the third photoresist layer is patterned to form a third opening exposing a portion of the conductive substrate. A portion of the conductive substrate is removed to form a fourth opening, and a surface of the first conductive layer and the top surface of the dielectric layer are exposed in the fourth opening and the surface of the first conductive layer has the same plane with the top surface of the dielectric layer. The third photoresist layer is removed. A fourth photoresist layer is formed on the conductive substrate, the dielectric layer, the first conductive layer and the second conductive layer, wherein the fourth photoresist layer is patterned to form a fifth opening exposing a portion of the surface of the first conductive layer. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed. Besides, a welding layer covering the surface of the second conductive layer is further formed on the second conductive layer.

According to an alternate embodiment, a package structure for a semiconductor device is provided. The package structure comprises a package substrate, a semiconductor device, an underfill layer and a sealant layer. The package substrate comprises a dielectric layer, a first conductive layer and a second conductive layer. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface is exposed from the top surface and has the same plane with the top surface or is concaved to the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface is exposed from the bottom surface and has the same plane with the bottom surface or is concaved to the bottom surface. The semiconductor device having a conductive bump is disposed on the package substrate. The conductive bumps are supported between the semiconductor device and the package substrate.

According to another alternate embodiment, a package manufacturing method for a semiconductor device is provided. The method comprises the following steps. A conductive substrate is provided. A first photoresist layer is formed on the conductive substrate, wherein the conductive substrate is patterned to form several first openings exposing a portion of the conductive substrate. A first conductive layer is formed in the first openings. A second photoresist layer is formed on the first photoresist layer and the first conductive layer, wherein the second photoresist layer is patterned to form several second openings exposing a portion of the first conductive layer. A second conductive layer contacting the first conductive layer is formed on the second openings. The first and the second photoresist layer are removed. A dielectric layer is formed on the conductive substrate, wherein the dielectric layer covers the first conductive layer, the second conductive layer and a portion of the conductive substrate. A portion of the dielectric layer is removed, and a surface of the second conductive layer is exposed from the bottom surface of the dielectric layer and has the same plane with the bottom surface of the dielectric layer. A third photoresist layer is formed on the conductive substrate, the dielectric layer, the first conductive layer and the second conductive layer, wherein the third photoresist layer is patterned to form a third opening exposing a portion of the conductive substrate. A portion of the conductive substrate is removed to form a fourth opening, and a surface of the first conductive layer and the top surface of the dielectric layer are exposed in the fourth opening and the surface of the first conductive layer has the same plane with the top surface of the dielectric layer. The third photoresist layer is removed. A fourth photoresist layer is formed on the conductive substrate, the dielectric layer, the first conductive layer and the second conductive layer, wherein the fourth photoresist layer is patterned to form a fifth opening exposing a portion of the surface of the first conductive layer. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed. A welding layer covering the surface of the second conductive layer is formed on the second conductive layer to form a package substrate composed of the dielectric layer, the first conductive layer, the second conductive layer and the bonding pad. A semiconductor device is disposed on the package substrate, wherein the semiconductor device has a conductive bump connected to the bonding pad and supported between the semiconductor device and the package substrate.

The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiments. The following description is made with reference to the accompanying drawings.

DETAILED DESCRIPTION

The package substrate, the manufacturing method of the package substrate, the package structure for a semiconductor device and the manufacturing method thereof disclosed in the present embodiment can be used in a package structure having a larger quantity of I/O pins without using a solder mask to cover the surface of the package substrate to avoid short-circuit due to solder bridging, such that fine pitch precision between the wires still can be sustainable. Preferably, the solder can be confined to be within a predetermined cavity and cannot flow outside the cavity, the height of the interconnection wire structure in the package substrate can be reduced through the arrangement of top-down stacked conductor layers. Furthermore, by surrounding the package substrate with an annular reinforcing structure, the strength of the package is enhanced, warpage or deformation of the package is avoided, and the package reliability of the semiconductor device is thus improved.

A number of embodiments are disclosed below for elaborating the invention. However, the embodiments of the invention are for detailed descriptions only, not for limiting the scope of protection of the invention.

FIGS. 1A and 1Brespectively are a schematic diagram of a package substrate and a cross-sectional view along a cross-sectional line I-I according to an embodiment of the invention.FIGS. 2A and 2Brespectively are a schematic diagram of a package substrate and a cross-sectional view along a cross-sectional line I-I according to an embodiment of the invention.FIGS. 3A and 3Brespectively are a schematic diagram of a package substrate and a cross-sectional view along a cross-sectional line I-I according to an embodiment of the invention.

Referring toFIGS. 1A and 1B, the package substrate100comprises a dielectric layer110, a first conductive layer120, a second conductive layer130, a bonding pad140and a welding layer150. The dielectric layer110has a top surface112and a bottom surface114. The first conductive layer120is embedded into the dielectric layer110, and a first surface122is exposed from the top surface112. The second conductive layer130is embedded into the dielectric layer110, and a second surface132is exposed from the bottom surface114. The bonding pad140is disposed within a cavity123defined by a side wall121of the first conductive layer120and a side wall111of the dielectric layer110(referring toFIG. 1B). When the first surface122has the same plane with the top surface112, the bonding pad140is partially (or completely) embedded into the first conductive layer120and the dielectric layer110, so that the peripheral of the bonding pad140is confined within a cavity123by both the side wall121of the first conductive layer120and the side wall111of the dielectric layer110(FIG. 1B) and cannot move around to avoid short-circuit due to the bridging of the bonding pad140(such as the solder) when the solder is reflowed at a high temperature. The bonding pad140is formed by a material selected from tin (Sn), copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), gold (Au), or a combination thereof, and preferably is a reflowable solder material.

As indicated inFIG. 1A, the first surface122has the same plane with the top surface112of the dielectric layer110, and the second surface132further has the same plane with the bottom surface114of the dielectric layer110. As indicated inFIG. 2A, the first surface122is concaved to the top surface112of the dielectric layer110, and the second surface132is concaved to the bottom surface114of the dielectric layer110. When the first surface122is concaved to the top surface112of the dielectric layer110, the bonding pad140is partially (or completely) embedded into the cavity113of the dielectric layer110, so that two opposite sides of the bonding pad140are confined within a cavity113by the side wall111of the dielectric layer110alone and cannot move around (referring toFIG. 2B) to avoid short-circuit due to the bridging of the bonding pad140(such as the solder) when the solder is reflowed at a high temperature. Moreover, when the second surface132is concaved to the bottom surface114(referring toFIG. 2A), a solder ball190(referring toFIG. 4A) can be fixed on each welding layer150, so that the quality of ball implantation is further stabilized.

Next, referring toFIGS. 3A and 3B, given that the solder will not be short-circuited, the bonding pad140can be directly formed on the first surface122of the first conductive layer120. The first conductive layer120can be formed by an anti-erosion material such as nickel-copper alloy, nickel-chromium alloy and so on. The bonding pad140is formed by a material selected from tin (Sn), copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), gold (Au), or a combination thereof, and preferably is formed by a bump not requiring reflowing such as a stud bump.

Referring toFIGS. 4A˜4C, schematic diagrams of a package structure for a semiconductor device according to an embodiment of the invention are shown. As indicated inFIGS. 4A˜4C, the package substrate can be any of the package substrates100used inFIGS. 1A, 2A and 3A. Detailed descriptions of the package substrate are already disclosed above and the similarities are not repeated here. As indicated inFIGS. 4A˜4C, the semiconductor device160is disposed on the package substrate100. The semiconductor device160has several conductive bumps162, and only three conductive bumps162are illustrated in the diagram, wherein one conductive bump162is correspondingly connected to one bonding pad140, and the conductive bumps162are supported between the semiconductor device160and the package substrate100. In comparison to the bonding pad140, the conductive bumps162have a higher melting point, therefore when the bonding pad140is heated and melted, the non-melted conductive bumps162have a sufficient height to support the semiconductor device160and maintain a suitable pitch between the semiconductor device160and the package substrate100. The conductive bumps162, such as electroplated copper columns, have a predetermined height. The bonding pad140is such as a solder. When the conductive bumps162is connected to the bonding pad140as indicated inFIGS. 1A and 2A, the bonding pad140preferably is confined within a cavity123and cannot flow around to avoid short-circuit due to the bridging of the bonding pad140when the bonding pad140is reflowed at a high temperature. Besides, the conductive bump162may further comprise a solder pad disposed on the copper column, wherein a portion of the solder pad is adhered on the bonding pad140.

Besides, the underfill layer170encapsulates the peripheral of the conductive bumps162, and is preferably formed by a thermal setting epoxy resin. The underfill layer170, having the advantages of fast fluidity and quick curability, can be cured in the reflowing process, so that the bonding pad140is not affected by the fluidity of the underfill layer170and still maintains the conductivity between the conductive bumps162and the bonding pad140. In addition, the sealant layer180, which encapsulates the peripheral of the semiconductor device160and the underfill layer170and is preferably formed by a thermal setting epoxy resin, protects the semiconductor device160. Moreover, several solder balls190are formed on the welding layer150, and only three solder balls190are illustrated, wherein one solder ball190is correspondingly connected to one welding layer150, and the solder balls190can be formed by a leadless solder paste or a lead solder paste.

As indicated inFIG. 4B, the sealant layer180encapsulates the peripheral of the semiconductor device160and the underfill layer170, and the top surface112of the semiconductor device160is exposed. The sealant layer180preferably formed by transfer molding is cured by way of high temperature baking process.

As indicated inFIG. 4C, the conductive bumps162, such as stud bumps, are preferably formed by copper or gold. The tip of the conductive bump162may pass through the underfill layer170having lower fluidity to be electrically connected to the bonding pad140disposed under the underfill layer170. The underfill layer170, which can be formed by a thermal setting non-conductive adhesive, encapsulates the peripheral of the conductive bumps162.

In another embodiment, no bonding pad is disposed on the package substrate100. The conductive bump162comprises a copper column and a solder pad disposed on the copper column, wherein a portion of the solder pad is directly adhered on the first conductive layer120, so that the semiconductor device160is formed on the semiconductor substrate. When the conductive bumps162are connected to the first conductive layer120, the conductive bumps162preferably are confined within the side wall of the dielectric layer110and cannot flow around. With a surface of the first conductive layer120being concaved to a top surface of the dielectric layer110, the conductive bumps162are confined, and can thus be accurately positioned on the first conductive layer120.

In the embodiments disclosed above, the design of a surface of the first conductive layer120being concaved to a top surface of the dielectric layer110prolongs the path of two adjacent first conductive layers spreading along the outer surface of the package body, hence avoiding the risk of two adjacent first conductive layers being short-circuited when electro migration occurs.

Referring toFIGS. 5A˜5Y.FIGS. 5A˜5S are schematic diagrams of a manufacturing method of package substrate according to an embodiment of the invention.FIGS. 5T˜5Y are schematic diagrams of a manufacturing method for a semiconductor element according to an embodiment of the invention. Firstly, referring toFIGS. 5A˜5D, a conductive substrate50is provided, and a first photoresist layer52is formed on the conductive substrate50and is patterned to form several first openings54exposing a portion of the conductive substrate50. Then, a first conductive layer120is formed in the first openings54. As indicated inFIG. 5A, the conductive substrate50is a metal substrate preferably formed by a copper board or a steel board electroplated with a copper layer. As indicated inFIGS. 5B and 5C, the first photoresist layer52is formed on the conductive substrate50by way of spin coating, and is further patterned by processes such as baking, exposure, and development, so that the first photoresist layer52has several first openings54. As indicated inFIG. 5D, the first conductive layer120formed in the first openings54by way of electroplating is preferably formed by copper, nickel, gold or a combination thereof.

Next, referring toFIGS. 5E˜5H, a second photoresist layer56is formed on the first photoresist layer52and the first conductive layer120, and is patterned to form several second openings58exposing a portion of the first conductive layer120. A second conductive layer130is formed in the second openings58. Then, the first photoresist layer52and the second photoresist layer56are removed. As indicated inFIGS. 5E and 5F, the second photoresist layer56formed on the conductive substrate50by way of spin coating is patterned by processes such as baking, exposure, and development, so that the second photoresist layer56has several second openings58. As indicated inFIG. 5G, the second conductive layer130formed in the second openings58by way of electroplating is preferably formed by copper, nickel, gold or a combination thereof. The second conductive layer130directly contacts the first conductive layer120, and the second conductive layer130and the first conductive layer120are stacked together in a top down manner to form an interconnection wire structure. As indicated inFIG. 5H, the first photoresist layer52and the second photoresist layer56are removed by a de-photoresist agent (such as acetone) to expose the first conductive layer120and the second conductive layer130which are mutually stacked. Although the present embodiment only illustrates the first conductive layer120and the second conductive layer130, a conductive layer with more than two layers can also be formed, and it does not impose any further restrictions on the invention.

Next, referring toFIGS. 5I˜5L, a dielectric layer110is formed on the conductive substrate50, wherein the dielectric layer110covers the first conductive layer120, the second conductive layer130and a portion of the conductive substrate50. A portion of the dielectric layer110is removed and a surface of the second conductive layer130(that is, the second surface132) is exposed from the bottom surface114of the dielectric layer110and has the same plane with the bottom surface114of the dielectric layer110. Then, a third photoresist layer60is formed on the conductive substrate50and the dielectric layer110, and is patterned to form a third opening62exposing a portion of the conductive substrate50. As indicated inFIG. 5I, the dielectric layer110is formed on the conductive substrate50by way of transfer molding. That is, the liquid-state dielectric layer110is injected to the mold cavity, and then is baked and cured. The dielectric layer110can also be formed on the conductive substrate50by way of compression molding, and the semi-cured state dielectric layer110is then completely cured at a high temperature and shaped. As indicated inFIG. 5J, a portion of the dielectric layer110is removed by way of grinding and/or buffing, so that the second surface132of the second conductive layer130is exposed from the dielectric layer110, and has the same plane with the bottom surface114of the dielectric layer110. Besides, the second surface132of the second conductive layer130may be concaved to the bottom surface114of the dielectric layer110by way of etching as indicated inFIG. 2Afor the convenience of ball implantation. As indicated inFIGS. 5K and 5L, the third photoresist layer60is formed on the conductive substrate50by way of slit die coating or dip coating, and then is patterned by processes such as baking, exposure, and development, so that the third photoresist layer60has a third opening62.

Next, referring toFIGS. 5M˜5P, a portion of the conductive substrate50is removed to form a fourth opening51, and a surface of the first conductive layer120and the top surface112of the dielectric layer110are exposed in the fourth opening51. The surface of the first conductive layer120has the same plane with the top surface112of the dielectric layer110. The third photoresist layer60is removed. Then, a fourth photoresist layer64is formed on the conductive substrate50, the dielectric layer110, the first conductive layer120and the second conductive layer130, and is patterned to form a fifth opening66exposing a portion of the surface of the first conductive layer120. As indicated inFIG. 5M, the conductive substrate50is formed in the fourth opening51by way of wet etching, and only a fourth opening51is illustrated, and the non-etched portion of the conductive substrate50forms an annular reinforcing structure53connected to the peripheral of the dielectric layer110. The annular reinforcing structure53surrounds the top surface112of the dielectric layer110to enhance the strength of the entire package substrate to avoid the package substrate being warped or deformed. Besides, the surface of the first conductive layer120can be completely etched and become concaved to the top surface112of the dielectric layer110as indicated inFIG. 2A. As indicated inFIG. 5N, the third photoresist layer60is removed by a de-photoresist agent (such as acetone) to expose the first conductive layer120and the second conductive layer130which are mutually stacked. As indicated inFIGS. 5O and 5P, the fourth photoresist layer64is formed by way of slit die coating or dip coating, and is patterned by processes such as baking, exposure, and development, so that the fourth photoresist layer64has several fifth openings66. Moreover, a portion of the surface of the first conductive layer120exposed in the fifth opening66can be further etched to form a cavity123as indicated inFIG. 1A.

Next, referring toFIGS. 5Q˜5S, a bonding pad140is formed in the fifth opening66. The fourth photoresist layer64is removed. Then, a welding layer150covering a surface of the second conductive layer130is formed on the second conductive layer130. As indicated inFIG. 5Q, the bonding pad140is formed in the fifth opening66by way of electroplating, wherein the bonding pad140is formed by a material selected from tin (Sn), copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), gold (Au), or a combination thereof and is preferably formed by a reflowable soldering material. As indicated inFIG. 5R, the fourth photoresist layer64is removed by a de-photoresist agent (such as acetone) to expose the first conductive layer120and the second conductive layer130which are mutually stacked. As indicated inFIG. 5S, the welding layer150is formed on the second conductive layer130by way of electroless-plating or immersion, wherein the welding layer150is formed by a material selected from tin (Sn), copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), gold (Au), or a combination thereof, or an organic solderability preservatives (OSP). Detailed descriptions of the manufacturing method of the package substrate100are disclosed above, and detailed descriptions of the manufacturing method for the semiconductor device160are disclosed below.

Referring toFIGS. 5T˜5W, a semiconductor device160is disposed on the package substrate100. The semiconductor device160has a conductive bump162connected to the bonding pad140and supported between the semiconductor device160and the package substrate100. A underfill layer170is formed to encapsulate the peripheral of the conductive bumps162. A sealant layer180is formed to encapsulate the peripheral of both the semiconductor device160and the underfill layer170. As indicated inFIG. 5T, the semiconductor device160is realized by an integrated circuit element whose active surface has several conductive bumps162disposed thereon, and only three conductive bumps162are illustrated in the diagram, wherein one conductive bump162corresponds to one bonding pad140. In comparison to the bonding pad140, the conductive bumps162have a higher melting point, and are realized by such as copper columns, copper bumps, gold bumps or stud bumps having a predetermined height, and the bonding pad140is realized by such as a reflowable soldering material. As indicated inFIGS. 5U and 5V, the underfill layer170is firstly formed on the package substrate100, and then the conductive bumps162of the semiconductor device160passes the underfill layer170having lower fluidity to be electrically connected to the bonding pad140disposed under the underfill layer170, so that the underfill layer170encapsulates the peripheral of the conductive bumps162. Apart from the above method for forming the underfill layer170, the underfill layer170can also be formed according to another method. For example, the semiconductor device160is firstly disposed on the package substrate100, and then the underfill layer170having better fluidity is interposed into the gap between the semiconductor device160and the package substrate100to encapsulate the peripheral of the conductive bumps162. As indicated inFIG. 5V, when the conductive bumps162is connected to the bonding pad140, as indicated inFIGS. 1A and 2A, the bonding pad140is preferably confined within a cavity123and cannot move around to avoid the short-circuit due to bridging of the bonding pad140when the bonding pad is reflowed at a high temperature. As indicated inFIG. 5W, the sealant layer180is preferably formed by way of transfer molding, and is baked at a high temperature and cured. Besides, the sealant layer180can also expose the top surface112of the semiconductor device160as indicated inFIG. 4Bto increase the heat dissipation area of the semiconductor device160.

Next, referring toFIGS. 5X˜5Y, a solder ball190is formed on the welding layer150, and the package substrate100and the sealant layer180are divided to form several package structures for the semiconductor devices160. As indicated inFIG. 5X, several solder balls190are formed on the welding layer150, wherein each solder ball190is correspondingly connected to a welding layer150and can be formed by a leadless solder paste or a lead solder paste. As indicated inFIG. 5X, two package structures101for the semiconductor device, such as chip scale package structure, are divided by a cutting tool along a singulation line L, and the annular reinforcing structure53is dispensed with so that the volume of the package can be reduced.

FIGS. 6A and 6Brespectively are a top view of package substrate200and a cross-sectional view along a cross-sectional line A-A according to an embodiment of the invention.FIGS. 7A and 7Brespectively are a top view of package substrate200and a cross-sectional view along a cross-sectional line B-B according to another embodiment of the invention. As indicated inFIGS. 6A and 6B, the package substrate200comprises an annular reinforcing structure202and four package units204. The annular reinforcing structure202has four openings205separated by ribs203, and each opening205correspondingly exposes a package unit204. Each package unit204is divided into 12 device blocks206, for example, which are encapsulated by the dielectric layer210, and the peripheral of the package units204are connected to each other by ribs203to avoid the package units being warped or deformed. In addition, as indicated inFIGS. 7A and 7B, the annular reinforcing structure202has a larger opening207correspondingly exposing four package units204. Each package unit204is divided into 12 device blocks206, for example. The 48 device blocks206together are encapsulated by the dielectric layer210, and the outmost peripheral of the four package units204is connected to the annular reinforcing structure202to avoid the package units being warped or deformed.

Referring toFIGS. 8A and 8B, processes of forming a positioning hole on an annular reinforcing structure53are shown. When the third photoresist layer60is formed on the conductive substrate50, the third opening62exposes the middle part of the conductive substrate50as well as a portion of the outer side55of the conductive substrate50. The outer side55is removed by way of etching to form a positioning hole57in the annular reinforcing structure53. In the present embodiment, the positioning hole57can be used as a reference point for positioning the semiconductor device160(referring toFIG. 5T). The positioning hole57can also be formed on the outer side55of the conductive substrate50before the first photoresist layer52is formed (referring toFIG. 5A), and it does not impose further restrictions on the invention.