Clock signal generation circuit, optical scanning apparatus, and image forming apparatus

The present invention discloses a clock signal generation circuit for generating one or more clock signals for performing a scanning operation by scanning a light beam from a light source to a scan target. The clock signal generation circuit includes a determination circuit for determining authenticity of start information in accordance with at least one of the length of the start information and the timing at which the start information is input, and a generation circuit for generating the clock signals in synchronization with the start information when the determination circuit determines that the start information is authentic.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a clock signal generation circuit, an optical scanning apparatus, and an image forming apparatus, and more particularly to a signal generation circuit for generating clock signals used when scanning a scanning target with a light beam from a light source, an optical scanning apparatus including the signal generation circuit, and an image forming apparatus including the optical scanning apparatus.

2. Description of the Related Art

In an image forming apparatuses (e.g. laser printers, digital copiers), the light, which is modulated in accordance with image information, is condensed from a light source onto the photoconductor via a polygon mirror, scanning lens, etc., and is moved (scanned) in a predetermined direction (scanning direction), to thereby form latent images (electrostatic images) on the photoconductor. Then, the image information is made visible by attaching toner to the latent images.

In recent years and continuing, the demand for forming images with higher quality is growing. Therefore, under such circumstances, the problem where a beam spot deviates from a predetermined position on a photoconductor cannot be ignored. This problem is caused by, for example, inclination of the deflection/reflection face of the polygon mirror, inconsistency of the distance from the rotation axis of the deflection/reflection face, and changes in the wavelength of the light from the light source.

Various technologies (see, for example, Japanese Laid-Open Patent Application Nos.11-167081, 2001-228415, and 2002-36626) are proposed for correcting the deviation of the beam spot. The aforementioned technologies correct the deviation by correcting clock signals used during the scanning of a photoconductor (hereinafter referred to as “pixel clock signals”). However, with the apparatus disclosed in the aforementioned Japanese Laid-Open Patent Application Nos.11-167081, 2001-228415, and 2002-36626, the signals, which are output from a photo-detecting element serving to detect the timing for starting the scanning of a single line, may be adversely affected by noise. This results in the formation of irregular latent images and leads to the degradation of image quality.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a clock signal generation circuit, an optical scanning apparatus, and an image forming apparatus that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a clock signal generation circuit for generating one or more clock signals for performing a scanning operation by scanning a light beam from a light source to a scan target, the clock signal generation circuit including: a determination circuit for determining authenticity of start information in accordance with at least one of the length of the start information and the timing at which the start information is input; and a generation circuit for generating the clock signals in synchronization with the start information when the determination circuit determines that the start information is authentic.

Furthermore, the present invention provides an optical scanning apparatus for performing a scanning operation by scanning a light beam from a light source to a scan target scanning, the optical scanning apparatus including: a detection sensor for detecting the start of the scanning operation and outputting signals including start information indicative of the start of the scanning operation; a clock signal generation circuit for receiving the signals output from the detection sensor, the clock signal generation circuit including a determination circuit for determining authenticity of the start information in accordance with at least one of the length of the start information and the timing at which the start information is input, and a generation circuit for generating the clock signals in synchronization with the start information when the determination circuit determines that the start information is authentic; and an optical control circuit for controlling the light source in accordance with the clock signals generated by the clock signal generation circuit.

Furthermore, the present invention provides an image forming apparatus including the optical scanning apparatus according to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention are described with reference toFIGS. 1-27.FIG. 1shows an exemplary configuration of an image forming apparatus (in this embodiment, a laser printer)100according to an embodiment of the present invention.

The laser printer100shown inFIG. 1includes, for example, an optical scanning apparatus900, a photoconductor drum (scanning target)901on which scanning is performed, a charging brush902, a developing roller903, a toner cartridge904, a cleaning blade905, a sheet feeding tray906, a sheet feeding roller907, a pair of resist rollers (resist roller pair)908, a transferring roller911, a fixing roller909, a sheet discharging roller912, and a sheet discharge tray910.

The charging brush902, the developing roller903, the transferring roller911, and the cleaning blade905are each positioned in the vicinity of the surface of the photoconductor drum901. The charging brush902, the developing roller903, the transferring roller911, and the cleaning blade905are arranged in this order with respect to the rotating direction of the photoconductor drum901.

The photoconductor drum901has a photosensitive layer formed on its surface. The photoconductor drum901in this embodiment rotates in a clockwise direction (arrow direction) as shown inFIG. 1.

The charging brush902is for electrically charging the surface of the photoconductor drum901.

The optical scanning apparatus900irradiates a light beam, being modulated in accordance with the image information from an upper level apparatus (e.g. personal computer), to the surface of the photoconductor drum901that is charged by the charging brush902. Accordingly, the charge on the surface of the photoconductor drum901is removed at areas where the light beam is irradiated. Thereby, a latent image corresponding to the image information is formed on the surface of the photoconductor drum901. The latent image is delivered toward the developing roller903along with the rotation of the photoconductor drum901. The longitudinal direction (direction of the rotation axis) of the photoconductor drum901is referred to as a “scanning direction”, and the rotating direction of the photoconductor drum901is referred to as a “sub-scanning direction”. Further details of the configuration of the optical scanning apparatus900are described below.

The toner cartridge904has toner stored therein. The toner stored in the toner cartridge904is supplied to the developing roller903. The amount of toner inside the toner cartridge904is checked (inspected), for example, when the power is turned on or when a printing operation is completed. In a case where there is only a small amount of toner remaining in the toner cartridge904, a message requesting replacement of the toner cartridge904is displayed on a display part (not shown).

The toner from the toner cartridge904is charged and evenly thinly applied to the surface of the developing roller903along with the rotation of the developing roller903. Furthermore, the developing roller903has applied a predetermined voltage such that electric fields of opposite direction are generated between the charged area of the photoconductor drum901(area to which the light beam is irradiated) and the uncharged area of the photoconductor drum (area to which the light beam is not irradiated). This voltage enables the toner on the developing roller903to be attached only to the surface of the charged area of the photoconductor drum901to which the light beam is irradiated. In other words, the developing roller903makes visible the image information by having toner attached to the latent image formed on the surface of the photoconductor drum901. The latent image, having toner attached thereto, is delivered toward the direction of the transferring roller911along with the rotation of the photoconductor drum901.

The sheet feeding tray906has recording paper (transfer medium)913stored therein. The sheet feeding roller907is provided in the vicinity of the sheet feeding tray906. The sheet feeding roller907extracts the recording paper913sheet-by-sheet and conveys the recording paper913to the pair of resist rollers (resist roller pair)908. The resist roller pair908is situated in the vicinity of the transferring roller911. The resist roller pair908once first holds the recording paper913extracted by the sheet feeding roller907and then delivers the recording paper913to a space part between the photoconductor drum901and the transferring roller911in correspondence with the rotation of the photoconductor drum901.

A voltage having an opposite polarity with respect to the toner on the surface of the photoconductor drum901is applied to the transferring roller911for electrically attracting the toner to the recording paper913. This voltage allows the latent image on the surface of the photoconductor drum901to be transferred to the recording paper913. Then, the recording paper913having the latent image transferred thereto is delivered to the fixing roller909.

The fixing roller909applies heat and pressure to the recording paper913. Thereby, the toner is fixed onto the recording paper913. Then, the recording paper913is delivered to the sheet discharge tray910via the sheet discharging roller912and is sequentially stacked on the sheet discharge tray910.

The cleaning blade905removes the toner (residual toner) remaining on the surface of the photoconductor drum901. It is to be noted that the removed residual toner can be reused. The photoconductor drum901having residual toner removed from its surface returns to the original position of the charging brush902.

Next, an exemplary configuration of the above-described optical scanning apparatus900is described with reference toFIGS. 2 and 3.

The optical scanning apparatus900includes, for example, a light source unit801having a semiconductor laser LD as its light source, a collimator lens CL, a cylinder lens805, a polygon mirror808, a polygon motor (not shown) for rotating the polygon mirror808, an fθ lens806, a return mirror807, a toroidal lens812, two photosensitive elements813,814, two printed boards802,809, a processing circuit815, and an optical housing804. The optical system having the collimator lens CL, the cylinder lens805, the polygon mirror808, the fθ lens806, the return mirror807, and the toroidal lens812situated on the optical path between the light source unit801and the photoconductor drum901may hereinafter be also referred to as “scanning optical system”.

The light source unit801, which has the printed board802mounted on its rear side, is pressed against the wall of the optical housing804by a spring member (not shown). The position of the light source unit801pressed against the wall of the optical housing804can be adjusted by using an adjustment screw803. Accordingly, the orientation of the maximum output strength of the laser beam emitted from the semiconductor laser LD can be adjusted. The adjustment screw is fastened to a projecting part provided to the wall of the optical housing804. In the optical housing804, the collimator lens CL, the cylinder lens805, the polygon mirror808, the polygon motor (not shown), the fθ lens806, the return mirror807, the toroidal lens812, and the two photosensitive elements813,814are each fixed and supported at a predetermined position.

Furthermore, in the same manner as the light source unit801, the printed board809is mounted to the wall of the optical housing804from the outside. The upper part of the optical housing804is sealed by a cover811. Furthermore, the optical housing804has plural attachment parts810projecting from its walls. The attachment parts810are to be fastened to a frame member of the laser printer100by screws.

The collimator lens CL converts (collimates) the laser beam emitted from the semiconductor laser LD to a substantially parallel ray. The cylinder lens805couples the light from the collimator lens CL.

The polygon mirror808includes plural deflection faces for deflecting the light from the cylinder lens805at an equal speed and equal angle within a predetermined angle range. The fθ lens806converts the light deflected by the polygon mirror808at an equal speed. The return mirror807bends the optical path of the light from the fθ lens806. The toroidal lens812condenses the light from the return mirror807onto the surface of the photoconductor drum901, to thereby form a beam spot on the photoconductor drum901.

Next, the operation of the optical scanning system according to an embodiment of the present invention is described. The light beams irradiated from the semiconductor laser LD are first converged to the vicinity of the deflection face of the polygon mirror808via the collimator lens CL and the cylinder lens805. The polygon mirror808is rotated at a predetermined speed in direction B (seeFIG. 3) by the polygon motor (not shown). The light beam converged to the vicinity of the deflection face of the polygon mirror is deflected along with the rotation of the polygon mirror800. The deflected light beam transmits through the fθ lens806and is converted to a light beam for scanning the return mirror807in the longitudinal direction within a predetermined angle range at a constant speed. Then, the light beam reflected from the return mirror807is scanned across the surface of the photoconductor drum901via the toroidal lens812. That is, the beam spot formed on the surface of the photoconductor drum901moves in the scanning direction. In scanning the light beam in the scanning direction, a single scan from an initial scanning position to a terminal scanning position is also hereinafter referred to as a “single line scan”.

The return mirror807has two photosensitive elements813,814provided on respective ends in the scanning direction for detecting the initiation (start) and termination (end) of the single line scan. In this embodiment, the photosensitive elements813,814are positioned so that the photosensitive element813receives the light beam deflected from the polygon mirror808before the execution of the single line scan and the photosensitive element814receives the light beam after the execution of the single line scan. Each photosensitive element813,814outputs a signal(s) (photoelectric conversion signal) in accordance with the amount of received light.

As shown inFIG. 4, the printed board809includes, for example, two I/V amps60,61, two binarization circuits62,63, and two inverters64,65.

The I/V amp60converts the photoelectric conversion signals from the photosensitive element813to voltage signals and amplifies the voltage signals with a predetermined gain. The I/V amp61converts the photoelectric conversion signals from the photosensitive element814to voltage signals and amplifies the voltage signals with a predetermined gain.

The binarization circuit63binarizes the signals output from the I/V amp60. The binarization circuit62binarizes the signals output from the I/V amp61.

The inverter64inverts the signals output from the binarization circuit62and outputs the inverted signals as first horizontal synchronizing signals Hsync1. The inverter65inverts the signals output from the binarization circuit63and outputs the inverted signals as second horizontal synchronizing signals Hsync2. The first horizontal synchronizing signal Hsync1changes from “H (high level)” to “L (low level)” when a light beam is received by the photosensitive element813. The second horizontal synchronizing signal Hsync2changes from “H (high level)” to “L (low level)” when a light beam is received by the photosensitive element814. Accordingly, as shown inFIGS. 8-10, the part where the signal level of the first horizontal synchronizing signal Hsyncl is “L” serves as information indicating the start of the single line scan. Both the first horizontal synchronizing signal Hsync1and the second horizontal synchronizing signal Hsync2are output to a process circuit815.

As shown inFIG. 4, the printed circuit802includes, for example, a laser drive circuit50. The laser drive circuit50converts modulation data (described below) from the process circuit815into corresponding drive signals and outputs the drive signals to the light source unit801. The drive signals are supplied to the semiconductor laser LD in the light source unit801.

As shown inFIG. 4, the process circuit815includes, for example, a deviation information detection circuit10, a memory15, a pixel clock generation circuit (clock signal generation circuit)20, an image process circuit30, and a laser drive data generation circuit40.

Based on the first horizontal synchronizing signal Hsync1and the second horizontal synchronizing signal Hsync2, the deviation information detection circuit10detects position deviation information of each line. In this embodiment of the present invention, the deviation information detection circuit10calculates the time spent for scanning a single line by referring to the first horizontal synchronizing signal Hsync1and the second horizontal synchronizing signal Hsync2and compares the calculated time with a predetermined reference time (hereinafter also referred to as “single line scan reference time”). Based on the difference obtained from this comparison (hereinafter referred to as “scan time difference”), the position deviation information is obtained. Then, the deviation information detection circuit10generates phase data Sphase for correcting position deviation (if any) based on the position deviation information. In this embodiment of the present invention, “position deviation” refers to a case where the latent image (more specifically, the pixels of the latent image) formed on the surface of the photoconductor drum901deviates from its expected position with respect to the scanning direction. The position deviation may be caused by, for example, a scanning irregularity due to the characteristics of the fθ lens806, inclination of the deflection/reflection face of the polygon mirror808, inconsistency of the distance from the rotation axis of the deflection/reflection face, irregularity in the rotation of the polygon mirror808, and changes in the wavelength of the laser beam from the semiconductor laser LD.

In this embodiment of the present invention, based on plural scan time differences (obtained by experiments performed beforehand), position deviation of each pixel is calculated in correspondence with each of the scan time differences. Based on the results of the calculations, a map indicating the pixel(s) for changing the phase in correspondence with each of the obtained scan time differences and the amount of the change is generated. The map for each scan time difference is stored as a position deviation information table in the memory15.

Accordingly, the deviation information detection circuit10refers to the position deviation information table in the memory15, extracts a map in accordance with an obtained scan time difference, and generates a phase data item(s) Sphase based on the map. In addition to referring to the scan time difference obtained from a recent (immediate) single line scan, the map may also be extracted by referring to past history information of one or more scan time differences.

In one example, the phase data item Sphase includes three bits (bit0(b0) , bit1(b1) , bit2(b2)) as shown inFIG. 5. The phase data item Sphase corresponds to a phase shift amount of a pixel clock signal (described below). The generated phase data item Sphase is output to the pixel clock generation circuit20in synchronization with a pixel clock signal.

As shown inFIG. 5, a phase data item Sphase “000” corresponds to a shift amount of “0”, a phase data item Sphase “001” corresponds to a shift amount of “+ 1/16”, a phase data item Sphase “010” corresponds to a shift amount of “+ 2/16”, a phase data item Sphase “011” corresponds to a shift amount of “+ 3/16”, a phase data item Sphase “111” corresponds to a shift amount of “− 1/16”, a phase data item Sphase “110” corresponds to a shift amount of “− 2/16”, and a phase data item Sphase “101” corresponds to a shift amount of “− 3/16”. It is to be noted that the symbol “+” of the shift amount indicates that the clock width of a pixel clock signal is extended with respect to a reference cycle, and the symbol “−” of the shift amount indicates that the clock width of a pixel clock signal is shortened with respect to a reference cycle.

The pixel clock generation circuit20generates a pixel clock signal (clock signal used when scanning a light beam from a light source to a scan target) PCLK based on the first horizontal synchronizing signal Hsync1and the phase data item Sphase.

The pixel clock generation circuit20according to an embodiment of the present invention includes, for example, a high frequency clock generation circuit201(seeFIG. 6), a phase synchronization control circuit203, a status signal generation circuit205, a control data generation circuit207, first and second transition detection circuits211,221, first and second control signal generation circuits212,222, first and second clock generation circuits213,223, a selection signal generation circuit231, and a multiplexer233.

The high frequency clock generation circuit201generates a high frequency clock signal VCLK which serves as a reference signal. In this embodiment of the present invention, a reference cycle of a pixel clock signal PCLK (cycle of a pixel clock signal when the phase shift is not executed, indicated as “Tp”) corresponds to eight times of the cycle of the high frequency clock signal VCLK (indicated as “Tv”). In the reference cycle according to this embodiment of the present invention, the duty ratio is 50%.

The phase synchronization control circuit203generates a phase status signal Pstat and two phase synchronization signals Psyn1, Psyn2. The generated phase status signal Pstat is output to the status signal generation circuit205and the selection signal generation circuit231. The generated phase synchronization signal Psync1is output to the transition detection circuit211. The generated phase synchronization signal Psync2is output to the transition detection circuit221.

As shown inFIG. 7, the phase synchronization control circuit203according to an embodiment of the present invention includes, for example, two flip-flops203a,203b, two counters203c,203d, a register203e, two phase synchronization signal generation circuits203f,203g, and a phase status signal generation circuit203h.

The flip-flop203A latches the first horizontal synchronizing signal Hsync1at the rise of the high frequency clock signal VCLK and generates a first enable signal EN1. The enable signal EN1is output to the counter203c.

The flip-flop203B latches the second horizontal synchronizing signal Hsync2at the drop of the high frequency clock signal VCLK and generates a second enable signal EN2. The enable signal EN2is output to the counter203d.

The counter203cperforms a counting operation of counting (counting up) count values at the rise of the high frequency clock signal VCLK when the first enable signal EN1is “L (low level)”. The counter203cresets the count value to “0” at the rise of the high frequency clock signal VCLK when the first enable signal EN1changes from “L (low level)” to “H (high level)”. The count value is output as a first count signal (indicated as “count1”) to the phase synchronization signal generation circuit203f.

The counter203dperforms a counting operation of counting (counting up) count values at the drop of the high frequency clock signal VCLK when the second enable signal EN2is “L (low level)”. The counter203dresets the count value to “0” at the drop of the high frequency clock signal VCLK when the second enable signal EN2changes from “L (low level)” to “H (high level)”. The count value(s) is output as a second count signal (indicated as “count2”) to the phase synchronization signal generation circuit203g.

The phase synchronization signal generation circuit203fcompares the count value obtained from the first count signal count1with a reference count stored in the register203e. If the count value obtained from the first count signal countl matches the reference count, the phase synchronization signal generation circuit203foutputs a first phase synchronization signal Psync1which becomes a “H” (high level) signal in synchronization with the rise of the high frequency clock signal VCLK. The phase synchronization signal generation circuit203gcompares the count value obtained from the second count signal count2with a reference count stored in the register203e. If the count value obtained from the second count signal count2matches the reference count, the phase synchronization signal generation circuit203goutputs a second phase synchronization signal Psync2which becomes a “H” (high level) signal in synchronization with the drop of the high frequency clock signal VCLK.

The phase status signal generation circuit203hgenerates a phase status signal Pstat based on the first and second phase synchronization signals Psync1, Psync2. In this embodiment of the present invention, the phase status signal Pstat is output as a “L” (low level) when the timing of the rise of the first phase synchronization signal Psync1is earlier than the timing of the rise of the second phase synchronization signal Psync2, and is output as a “H” (high level) when the timing of the rise of the second phase synchronization signal Psync2is earlier than the timing of the rise of the first phase synchronization signal Psync1.

The operation of the above-described phase synchronization control circuit203is described with reference to the timing charts shown inFIGS. 8-10. In this embodiment of the present invention, the reference count stored in the register203eis “4”. That is, the reference count corresponds to a value which is half (½) of the reference cycle Tp of the pixel clock signal PCLK.

As shown inFIG. 8, in a case where the first horizontal synchronizing signal Hsync is changed from “H” to “L” (timing A inFIG. 8), the second enable signal EN2becomes “L” when the high frequency clock signal VCLK drops from “H” to “L” (timing B inFIG. 8) and then the first enable signal EN1becomes “L” when the high frequency clock signal VCLK rises from “L” to “H” (timing C inFIG. 8). Accordingly, the counter203dstarts the counting operation at the drop of the high frequency clock signal VCLK, and the counter203cstarts the counting operation at the rise of the high frequency clock signal VCLK. In this embodiment of the present invention, the counting operation by the counter203dis started before the counting operation by the counter203c. Furthermore, when the count value obtained from the second count signal count2becomes “4”, the phase synchronization signal generation circuit203ggenerates a second phase synchronization signal Psync2of a high level (H) at the drop of the high frequency clock signal (timing D inFIG. 8). Furthermore, when the count value obtained from the first count signal countl becomes “4” the phase synchronization signal generation circuit203fgenerates the first phase synchronization signal Psync1of a high level (H) at the rise of the high frequency clock signal (timing E inFIG. 8). In this embodiment of the present invention, the second phase synchronization signal Psync2becomes a high level (H) before the first phase synchronization signal Psync1becomes a high level (H). The phase status signal Pstat becomes a high level (H) at the same timing that the first phase synchronization signal Psync1becomes a high level (timing E inFIG. 8). As exemplarily shown inFIG. 8, in a case where the first horizontal synchronizing signal Hsync is changed from “L” to “H” (timing F inFIG. 8), the second enable signal EN2of a high level (H) is generated at the drop of a following high frequency clock signal(s) VCLK (timing G inFIG. 8) when the high frequency clock signal VCLK is a high level (H) and the first enable signal EN1of a high level (H) is generated at the rise of the high-frequency clock signal VCLK (timing H inFIG. 8) when the high frequency clock signal VCLK is a low level (L).

As shown inFIG. 9, in a case where the first horizontal synchronizing signal Hsync is changed from “H” to “L” (timing A inFIG. 9), the first enable signal EN1becomes “L” when the high frequency clock signal VCLK rises from “L” to “H” (timing B inFIG. 9) and then the second enable signal EN2becomes “L” when the high frequency clock signal VCLK drops from “H” to “L” (timing C inFIG. 9). Accordingly, the counter203cstarts the counting operation at the rise of the high frequency clock signal VCLK, and the counter203dstarts the counting operation at the drop of the high frequency clock signal VCLK. In this embodiment of the present invention, the counting operation by the counter203cis started before the counting operation by the counter203d. Furthermore, when the count value obtained from the first count signal count1becomes “4”, the phase synchronization signal generation circuit203fgenerates a first phase synchronization signal Psync1of a high level (H) at the rise of the high frequency clock signal (timing D inFIG. 9). Furthermore, when the count value obtained from the second count signal count2becomes “4” the phase synchronization signal generation circuit203ggenerates the second phase synchronization signal Psync2of a high level (H) at the drop of the high frequency clock signal (timing E inFIG. 9). In this embodiment of the present invention, the first phase synchronization signal Psync1becomes a high level (H) before the second phase synchronization signal Psync2becomes a high level (H). The phase status signal Pstat becomes a low level (L) at the timing when the second phase synchronization signal Psync2becomes a high level. As exemplarily shown inFIG. 9, in a case where the first horizontal synchronizing signal Hsync is changed from “L” to “H” (timing F inFIG. 9), the first enable signal EN1of a high level (H) is generated at the rise of a following high frequency clock signal(s) VCLK (timing G inFIG. 9) when the high frequency clock signal VCLK is a low level (H) and the second enable signal EN2of a high level (H) is generated at the drop of the high frequency clock signal VCLK (timing H inFIG. 9) when the high frequency clock signal VCLK is a high level (H).

As exemplarily shown inFIG. 10, in a case where the count values obtained from each of the counters203c,203dare less than “4” (“2” in the example shown inFIG. 10), neither the first phase synchronization signal Psync1nor the second phase synchronization signal Psync2change when the first horizontal synchronizing signal Hsync1changes from “L” to “H” (timing F inFIG. 10). Thus, in such a case, the phase status signal Pstat also does not change. In other words, in a case where the first horizontal synchronizing signal Hsync1is “L” (low level) for a short period, there is no change in any one of the phase status signal Pstat, the first phase synchronization signal Psync1, or the second phase synchronization signal Psync2. Therefore, even in a case where factors such as noise cause the first horizontal synchronizing signal Hsync1to temporarily change to “L” (low level), such change has no effect on the signals output from the phase synchronization control circuit203.

Returning toFIG. 6, the status signal generation circuit205generates a status signal (indicated as “status” inFIG. 6) based on the bit0of the phase data item Sphase, the phase status signal Pstat, and the pixel clock signal PCLK (output signal from multiplexer233). The generated status signal is output to the control data generation circuit207. More specifically, the status signal generation circuit205initializes the level of the status signal to “L” when the phase status signal Pstat changes from “L” to “H”. The status signal is set in accordance with the change of signal level of the phase status signal Pstat. For example, as shown inFIG. 11, the status signal changes in synchronization with the timing of the rise of the pixel clock signal PCLK (timing A, B inFIG. 11) in a case where the bit0of the phase data item Sphase is “1”. The level of the status signal is initialized to “H” when the phase status signal Pstat changes from “H” to “L”.

The control data generation circuit207generates first and second control data items Dcnt1, Dcnt2based on the phase data item Sphase and the status signal. The generated first control data item Dcnt1is output to the control signal generation circuit212, and the generated second control data item Dcnt2is output to the control signal generation circuit222. For example, as shown inFIG. 12, the first and second control data items Dcnt1and Dcnt2are both “010” regardless of the value of the status signal in a case where the phase data item Sphase is “000”. In a case where the phase data item Sphase is “001”, the first control data item Dcnt1is “010” and the second control data item Dcnt2is “001” when the status signal is “0”, but the first control data item Dcnt1is “001” and the second control data item Dcnt2is “010” when the status signal is “1”. In a case where the phase data item Sphase is “010”, the first and second control data items Dcnt1and Dcnt2are both “001” regardless of the status signal. In a case where the phase data item Sphase is “011”, the first control data item Dcnt1is “001” and the second control data item Dcnt2is “000” when the status signal is “0”, but the first control data item Dcnt1is “000” and the second control data item Dcnt2is “001” when the status signal is “1”. In a case where the phase data item Sphase is “111”, the first control data item Dcnt1is “011” and the second control data item Dcnt2is “010” when the status signal is “0”, but the first control data item Dcnt1is “010” and the second control data item Dcnt2is “011” when the status signal is “1”. In a case where the phase data item Sphase is “110”, the first and second control data items Dcnt1, Dcnt2are both “011” regardless of the status signal. In a case where the phase data item Sphase is “101”, the first control data item Dcnt1is “100” and the second control data item Dcnt2is “011” when the status signal is “0”, but the first control data item Dcnt1is “011” and the second control data item Dcnt2is “100” when the status signal is “1”.

Returning toFIG. 6, the first transition detection circuit211generates a first detection signal Strans1based on the high frequency clock signal VCLK, the first phase synchronization signal Psync1, and the first clock signal CLK1(signal output from first clock generation circuit213). The generated first detection signal Strans1is output to the first control signal generation circuit212. For example, as shown inFIG. 13, the first transition detection circuit211operates at the rise of the high frequency clock signal VCLK. When the first transition detection circuit211detects the rise of the first phase synchronization signal Psync1(timing A inFIG. 13), the first transition detection circuit211outputs a pulse signal having a length substantially equal to a single clock width of a high frequency clock signal VCLK at a timing after eight clock outputs of the high frequency clock signal VCLK (timing B inFIG. 13). Then, when the first transition detection circuit211detects the rise of the first clock signal CLK1(timings C and D inFIG. 13), the first transition detection211outputs a pulse signal having a length substantially equal to a single clock width (Tv) of a high frequency clock signal VCLK. The eight clock outputs are substantially equal to the signal delay time of the first transition detection circuit211.

The second transition detection circuit221generates a second detection signal Strans2based on the high frequency clock signal VCLK, the second phase synchronization signal Psync2, and the second clock signal CLK2(signal output from the second clock generation circuit223). The generated second detection signal Strans2is output to the second control signal generation circuit222. For example, as shown inFIG. 14, the second transition detection circuit221operates at the drop of the high frequency clock signal VCLK. When the second transition detection circuit221detects the rise of the second phase synchronization signal Psync2(timing A inFIG. 14), the second transition detection circuit221outputs a pulse signal having a length substantially equal to a single clock width of a high frequency clock signal VCLK at a timing after eight clock outputs of the high frequency clock signal VCLK (timing B inFIG. 14). Then, when the second transition detection circuit221detects the rise of the second clock signal CLK2(timings C and D inFIG. 14), the second transition detection221outputs a pulse signal having a length substantially equal to a single clock width (Tv) of a high frequency clock signal VCLK. The eight clock outputs substantially equal to the signal delay time of the second transition detection circuit221.

The first control signal generation circuit212generates two first control signals CTL1a, CTL1bbased on the high frequency clock signal VCLK, the first control date item Dcnt1, and the first detection signal Strans1. The generated first control signals CTL1a, CTL1bare both output to the first clock generation circuit213.

As shown inFIG. 15, the first control signal generation circuit212according to an embodiment of the present invention includes nine shift registers212a-212iand a multiplexer212m. As shown inFIG. 17, each of the shift registers212a-212ioperates at the rise of the high frequency clock signal VCLK and outputs a signal (S10-S17) at a delayed timing in response to an input signal. The delay of the output signals (S10-S17) is substantially equal to a single clock output of a high frequency clock signal VCLK.

For example, the first control signal generation circuit212shown inFIG. 15is set in a manner that: the first detection signal Strans1is input to the shift register212a; the output signal (S10) from the shift register212ais input to the shift register212b; the output signal (S11) from the shift register212cis input to the shift register212c; the output signal (S12) from the shift register212cis input to the shift register212d; the output signal (S13) from the shift register212dis input to the shift register212e; the output signal (S14) from the shift register212eis input to the shift register212f; the output signal (S15) from the shift register212fis input to the shift register212g; the output signal (S16) from the shift register212gis input to the shift register212h; the output signal (S17) from the shift register212his input to the shift register212i; the output signal (S18) from the shift register212iis input to a D0port of the multiplexer212m. Furthermore, the first control signal generation circuit212shown inFIG. 15is set in a manner that: the output signal (S17) from the shift register212his input to a D1port of the multiplexer212m; the output signal (S16) from the shift register212gis input to a D2port of the multiplexer212m; the output signal (S15) from the shift register212fis input to a D3port of the multiplexer212m; and the output signal (S14) from the shift register212eis input to a D4port of the multiplexer212m. The output signal (S12) from the shift register212cserves as the first control signal CTL1a.

The first control data item Dcnt1is input to a selection port of the multiplexer212m. For example, as shown in the table ofFIG. 16, the multiplexer212mis set so that: the D0port is selected when the first control data item Dcnt1is “000”; the D1port is selected when the first control data item Dcnt is “001”; the D2port is selected when the first control data item Dcnt1is “010”; the D3port is selected when the first control data item Dcnt1is “011”; and the D4port is selected when the first control data item Dcnt1is “100”. The output signal from the multiplexer212mserves as the first control signal CTL1b.FIG. 17shows an exemplary case where the first control data item Dcnt1is “010”.

The second control signal generation circuit222generates two second control signals CTL2a, CTL2bbased on the high frequency clock signal VCLK, the second control data item Dcnt2, and the second detection signal Strans2. The generated second control signals CTL2a, CTL2bare both output to the second clock generation circuit223.

As shown inFIG. 18, the second control signal generation circuit222according to an embodiment of the present invention includes nine shift registers222a-222iand a multiplexer222m. As shown inFIG. 20, each of the shift registers222a-222ioperates at the drop of the high frequency clock signal VCLK and outputs a signal (S20-S27) at a delayed timing in response to an input signal. The delay of the output signals (S20-S27) is substantially equal to a single clock output of a high frequency clock signal VCLK.

For example, the second control signal generation circuit222shown inFIG. 18is set in a manner that: the second detection signal Strans2is input to the shift register222a; the output signal (S20) from the shift register222ais input to the shift register222b; the output signal (S21) from the shift register222cis input to the shift register222c; the output signal (S22) from the shift register222cis input to the shift register222d; the output signal (S23) from the shift register222dis input to the shift register222e; the output signal (S24) from the shift register222eis input to the shift register222f; the output signal (S25) from the shift register222fis input to the shift register222g; the output signal (S26) from the shift register222gis input to the shift register222h; the output signal (S27) from the shift register222his input to the shift register222i; the output signal (S28) from the shift register222iis input to a D0port of the multiplexer222m. Furthermore, the second control signal generation circuit222shown inFIG. 17is set in a manner that: the output signal (S27) from the shift register222his input to a D1port of the multiplexer222m; the output signal (S26) from the shift register222gis input to a D2port of the multiplexer222m; the output signal (S25) from the shift register222fis input to a D3port of the multiplexer222m; and the output signal (S24) from the shift register222eis input to a D4port of the multiplexer222m. The output signal (S22) from the shift register222cserves as the second control signal CTL2a.

The second control data item Dcnt2is input to a selection port of the multiplexer222m. For example, as shown in the table ofFIG. 19, the multiplexer222mis set so that: the D0port is selected when the second control data item Dcnt2is “000”; the D1port is selected when the second control data item Dcnt2is “001”; the D2port is selected when the second control data item Dcnt2is “010”; the D3port is selected when the second control data item Dcnt2is “011”; and the D4port is selected when the second control data item Dcnt2is “100”. The output signal from the multiplexer222mserves as the second control signal CTL2b.FIG. 20shows an exemplary case where the second control data item Dcnt2is “010”.

Returning toFIG. 6, the first clock generation circuit213generates a first clock signal CLK1based on the high frequency clock signal VCLK and the first control signals CTL1a, CTL1b. The generated first clock signal CLK1is output to the first transition detection circuit211and the multiplexer233. For example, as shown inFIG. 21, the first clock generation circuit213operates at the rise of the high frequency clock signal VCLK and outputs a first clock signal CLK1in accordance with the first control signal CTL1a, CTL1b. The output first clock signal CLK1becomes “L” when the first control signal CTLais “H”, and becomes “H” when the first control signal CTLbis “H”.

The second clock generation circuit223generates a second clock signal CLK2based on the high frequency clock signal VCLK and the second control signals CTL2a, CTL2b. The generated second clock signal CLK2is output to the second transition detection circuit221and the multiplexer233. For example, as shown inFIG. 22, the second clock generation circuit223operates at the drop of the high frequency clock signal VCLK and outputs a second clock signal CLK1in accordance with the second control signal CTL2a, CTL2b. The output second clock signal CLK2becomes “L” when the second control signal CTL2ais “H”, and becomes “H” when the second control signal CTL2bis “H”.

Since the pairs of the first and second transition detection circuits211,221, the first and second control signal generation circuits212,222, and the first and second clock signal generation circuits213,223can each be manufactured by using components that are substantially the same, manufacture costs can be reduced.

The selection signal generation circuit231generates a selection signal Ssel based on bit0of the phase data item Sphase, the phase status signal Pstat, and the pixel clock signal PCLK (signal output from the multiplexer233). The generated selection signal Ssel is output to a selection port of the multiplexer233. More specifically, the selection signal generation circuit231initializes the level of the selection signal Ssel to “H” when the phase status signal Pstat changes from “L” to “H”. The selection signal Ssel is set in accordance with the change of signal level of the phase status signal Pstat. For example, as shown inFIG. 23, the selection signal Ssel changes in synchronization with the timing of the drop of the pixel clock signal PCLK (timing A, B inFIG. 23) in a case where the bit0of the phase data item Sphase is “1”. The level of the selection signal Ssel is initialized to “L” when the phase status signal Pstat changes from “H” to “L”.

Returning toFIG. 6, the multiplexer233selects either one of the first clock signal CLK1or the second clock signal CLK2based on the selection signal Ssel and outputs the selected clock signal (CLK1or CLK2) as the pixel clock signal PCLK. For example, as shown inFIG. 24, the first clock signal CLK1is selected when the selection signal Ssel is “L”, and the second clock signal CLK2is selected when the selection signal Ssel is “H” (period between timings A and B inFIG. 24). Accordingly, the cycle of the pixel clock signal PCLK becomes Tp (reference cycle=8 Tv) when the phase data item Sphase is “000”, the cycle of the pixel clock signal PCLK becomes (1+ 1/16) Tp when the phase data item Sphase is “001”, and the cycle of the pixel clock signal PCLK is becomes (1− 1/16) Tp when the phase data item Sphase is “111”. In other words, as shown inFIG. 24, the pixel clock signal PCLK is adjusted with resolution of a half (½) cycle of the high frequency clock signal VCLK. Thereby, a pixel clock signal PCLK synchronizing with the start indication information is generated. As described above, since none of the phase status signal Pstat, the first phase synchronization signal Psync1, and the second phase synchronization signal Psync2change when the length of the start indication information is less than ½ of the reference cycle Tp of the pixel clock signal, the pixel clock signal PCLK, which synchronizes with the start indication information, is not generated. Therefore, even in a case where factors such as noise causes the first horizontal synchronizing signal Hsync1to temporarily change to “L” (low level), such change has no effect on the pixel clock signal PCLK from the pixel clock generation circuit20.

Returning toFIG. 4, the image process circuit30generates image data based on image information from an upper level apparatus. The generated image data are output to the laser drive data generation circuit40in synchronization with the pixel clock signal PCLK from the pixel clock generation circuit20.

The laser drive data generation circuit40generates a modulation data item based on the pixel clock signal PCLK from the pixel clock generation circuit20and the image data from the image process circuit30. The modulation data item is for modulating the light beam from the semiconductor laser LD. The modulation data are generated such that a single pixel corresponds to a single clock output of a pixel clock signal PCLK. Therefore, as exemplarily shown inFIG. 24, the length of modulation data (i.e. pixel width) changes in correspondence with the clock width of the pixel clock signal PCLK. The generated modulation data are output to the laser drive circuit50.

Hence, the pixel clock generation circuit20serves as a clock signal generation circuit according to an embodiment of the present invention, in which the phase synchronization control circuit203is included in a determination circuit according to an embodiment of the present invention. Furthermore, the high frequency clock generation circuit201, the status signal generation circuit205, the control data generation circuit207, the first and second transition detection circuits211,221, the first and second control signal generation circuits212,222, the first and second clock generation circuits213,223, the selection signal generation circuit231, and the multiplexer233are included in a generation circuit according to an embodiment of the present invention.

In the optical scanning apparatus900, the polygon mirror808is included in a deflection part according to an embodiment of the present invention. Furthermore, the fθ lens806, the return mirror807, the toroidal lens812are included in an optical system according to an embodiment of the present invention. Furthermore, the photo-sensitive element813is included in a detection sensor according to an embodiment of the present invention. Furthermore, the laser drive data generation circuit40and the laser drive circuit50are included in a light source control circuit according to an embodiment of the present invention.

Furthermore, the laser printer100serves as an image forming apparatus according to an embodiment of the present invention, in which the charging brush902, the developing roller903, the toner cartridge904, and the transfer roller911are included in a transfer apparatus according to an embodiment of the present invention.

As described above, with the phase synchronization control circuit203in the pixel clock generation circuit (clock signal generation circuit)20according to an embodiment of the present invention, a counting operation is started by the two counters (203c,203d) when the first horizontal synchronizing signal Hsync1changes from “H” to “L”. Then, the two phase synchronization signals (Psync1, Psync2) and the phase status signal Pstat change when the count value of the respective counters (203c,203d) reaches “4”. Then, the generation of pixel clock signal PCLK is started in synchronization with the first horizontal synchronizing signal Hsync1. Meanwhile, the two phase synchronization signals (Psync1, Psyn2) and the phase status signal Pstat do not change in a case where the first horizontal synchronizing signal Hsync1changes from “L” to “H” before the count value of the respective counters (203c,203d) reaches “4”. In this case, the generation of pixel clock signals PCLK synchronizing with the first horizontal synchronizing signal Hsync1does not start. In other words, the phase synchronization control circuit203determines that start information (information which informs the start of generating clock signals) is authentic (true) when the length of the start information is equal to or greater than a predetermined value. For example, even if start information is input in a case where the first horizontal synchronizing signal Hsync1temporarily becomes “L” due to noise, the phase synchronization control circuit203is able to determine that the input start information is false (not authentic). Thereby the pixel clock signal PCLK will not be generated in synchronization with the false start information. Accordingly, the clock signal generation circuit of the present invention can precisely generate clock signals used for scanning a light beam from a light source to a scan target without being affected by noise.

Although the conventional clock generation circuit generates clock signals having the same cycle as resolution with a high frequency clock generation circuit, the pixel clock generation circuit20according to an embodiment of the present invention can control the phase of the pixel clock signals with a resolution which is ½ of the cycle of the high frequency clock signals. Thereby, manufacture costs and energy consumption of the high frequency clock generation circuit can be reduced.

Furthermore, since the optical scanning apparatus900according to an embodiment of the present invention includes the above-described pixel clock generation circuit20which is resistant to noise, the light beam can be stably irradiated from the semiconductor laser LD. Thereby, the photoconductor drum901can be stably scanned.

Since the laser printer (image forming apparatus)100according to an embodiment of the present invention includes the above-described optical scanning apparatus900, high quality image forming can be achieved.

Although the value of the reference count stored in the register203eis “4” (i.e. value corresponding to ½ of a reference cycle Tp of a pixel clock signal PCLK) according to the above-described embodiment of the present invention, the reference count may alternatively be set with other values in accordance with, for example, the type of noise superposing the first horizontal synchronizing signal Hsync1. Alternatively, a DIP switch, for example, may be included in the printed board802so that the value of the reference count can be set or changed through the DIP switch. Alternatively, a control panel (not shown) may be included in the laser printer100so that the value of the reference count can be set or changed in a maintenance mode of the control panel.

Although the phase synchronization control circuit203determines authenticity of the start information in accordance with the length of the start information according to the above-described embodiment of the present invention, the authenticity of the start information may alternatively be determined by other criteria. In a first modified example 1 of the present invention shown inFIG. 25, the phase synchronization control circuit203may determine authenticity, of the start information by comparing a start information item (start information item B inFIG. 25) with a previous start information item (start information item A inFIG. 25). For example, the phase synchronization control circuit203determines that the start information item B is authentic (true) if the time elapsed from the start information item A (elapse time Tint inFIG. 25) is equal to or greater than a predetermined time, and determines that the start information item B is not authentic (false) if the time elapsed from the start information item A (elapse time Tint inFIG. 25) is less than the predetermined time. One example of the predetermined time may be the reference time for scanning a single line. In this determination, reference may be made to the length of the start information for improving the precision of the determination.

In a second modified example 2 of the present invention shown inFIG. 26, during a period where the light beam from the semiconductor laser LD includes image information, the phase synchronization control circuit203may determine authenticity of the start information by referring to timing signal which include information indicating that the image information is being written (portion where the level of the timing signal is “H”). For example, the phase synchronization control circuit203determines that the start information is authentic (true) if the timing signal at the drop of the first horizontal synchronizing signal Hsync1is “L” (information A and information C inFIG. 26), and determines that the start information is not authentic (false) if the timing signal at the drop of the first horizontal synchronizing signal Hsync1is “H” (information B inFIG. 26). For example, the timing signal may be generated in the laser drive data generation circuit40. In this determination, reference may be made to the length of the start information for improving the precision of the determination.

In a third modified example 3 of the present invention shown inFIG. 27, during a period where the light beam from the semiconductor laser LD does not include image information, the phase synchronization control circuit203may determine authenticity of the start information by referring to a timing signal which includes information indicating an idling state (portion where the level of the timing signal is “H”). For example, the phase synchronization control circuit203determines that the start information is authentic (true) if the timing signal at the drop of the first horizontal synchronizing signal Hsync1is “H” (information A and information C inFIG. 27), and determines that the start information is not authentic (false) if the timing signal at the drop of the first horizontal synchronizing signal Hsync1is “L”. (information B inFIG. 26). For example, the timing signal may be generated in the laser drive data generation circuit40. In this determination, reference may be made to the length of the start information for improving the precision of the determination.

Furthermore, at least a portion of the circuit(s) included in the process circuit815may be mounted to the printed board802according to an embodiment of present invention.

Although the laser printer100is described as an example of the image forming apparatus of the present invention, other alternative apparatuses may be used. The image forming apparatus may be, for example, a digital copier, a scanner, a facsimile, or a multi-function machine, where each includes the optical scanning apparatus900according to an embodiment of the present invention. In other words, high quality image formation can be achieved by providing an image forming apparatus including the optical scanning apparatus900.

The present application is based on Japanese Priority Application No.2005-044075 filed on Feb. 21, 2005, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.