DEVICE UNDER TEST (DUT) STRUCTURES FOR VOLTAGE CONTRAST (VC) DETECTION OF CONTACT OPENS

A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuits and, in particular, to DUT structures for VC image detection of contact opens.

BACKGROUND

Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the sub-10 nm range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

DESCRIPTION OF THE EMBODIMENTS

Device under test (DUT) structures for voltage contrast (VC) detection of contact opens are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or more embodiments described herein are directed to structures and architectures for utilizing voltage contrast (VC) to determine if contact metal of integrated circuits is touching epitaxial (epi) source or drain structures, which in turn is grounded to the substrate. Embodiments may include or pertain to manufacturing process technologies for various types of integrated circuits.

To provide context,FIGS.1A,1B and1Care transmission electron microscope (TEM) images showing cross-sections of various types of contact opens/defects in an integrated circuit structure. The integrated circuit structures100a,100band100cinclude epitaxial source/drain structure102above a sub-fin104of a substrate. A contact silicide106and contact metallization108is formed over the epitaxial source/drain structure102, and ideally, the contact silicide106should be in contact with the epitaxial source/drain structure102.

FIG.1Aillustrates a defect in integrated circuit100acaused by a shallow contact, meaning that the contact silicide106is formed too shallow, which forms a gap between it and the epitaxial source/drain structures102.FIG.1Billustrates a defect in integrated circuit100bcaused by a missing portion of contact silicide106. In this case, there is a vertical gap in the contact silicide106, which causes the contact metallization108flow through the gap and touch the epitaxial source/drain structure102.FIG.1Cillustrates a defect in integrated circuit100ccaused by epi damage, which in this case is caused by a noncontiguous epitaxial source/drain structure102to the underlying fin104. The defects described above can be described as contact opens or shorts.

Successful inline detection of epitaxial silicon to contact metal opens is notoriously difficult. Inline detection of contact opens typically fails since contact opens are buried defects that occur post contact metallization. As these defects are not detectable top down, the defects are typically not discovered until fabrication is complete and tested. For example, processes have had to rely on end of line signals to detect such buried defects. To solve this problem, some destructive Quick turn monitors (QTMs) have been developed that try to etch the epi through the contact space prior to contact metallization to determine if there is an oxide layer that prevents the etch. The QTMs perform unreliably as they are hard to engineer and this approach can only detect contact underetch, not missing contact metal.

In accordance with one or more embodiments described herein, dummy device under test (DUT) structures are used to take advantage of voltage contrast (VC) mode for the detection of electrical opens/shorts between contacts and the epitaxial silicon, preferably shortly after contact metallization is performed. The disclosed embodiments provide inline detection to the difficult problem of epitaxial silicon to contact metal defects/opens and trims 5-6 weeks of yield learning time by not having to run potential skews for solutions to end of line. The VC test is also non-destructive so this can be run on production wafers that can go to end of line thereby minimizing cost and also establishing correlations to known yield signals at end of line. In one embodiment, a DUT structure is fabricated for detection of contact opens on p-type epi. In a second embodiment, a DUT structure is fabricated for detection of contact opens on n-type epi. A wafer of integrated circuits incorporating such dummy DUT structures may exhibit an increase in manufacturing yield.

VC mode is a technique used in semiconductor inspection and analysis to detect defects or irregularities in integrated circuits. VC mode involves applying a voltage to a specific layer of the semiconductor device and observing the resulting contrast in the image produced by an electron microscope. In VC mode, a small voltage is applied to a specific layer of the semiconductor device using a probe. The voltage causes a change in the electrical potential of the layer, which in turn causes changes in the electron beam as it passes through the layer. These changes in the electron beam can be detected by an electron microscope and used to create a VC image of the device. The VC image shows areas where the voltage contrast is high, indicating areas of the device where there may be defects or irregularities.

FIG.1D, as an example, illustrates a VC image110showing a contact open defect in a device array, where a dark contact112in the device array indicates the presence of a contact open.

The disclosed embodiments utilize specialized dummy device under test (DUT) structures created for VC analysis that can be used to detect electrical opens/shorts between the contact and the epitaxial silicon. The DUT structures are designed to take advantage of the fact that in VC mode, electron beam tools can distinguish between grounded and floating features. This technique is especially useful in detecting defects that are buried or hidden and are not otherwise accessible for detection through optical metrology. The DUT structures may be fabricated alongside active structures on a test wafer and the wafer is then examined in VC mode to identify defects between the contact and the epitaxial silicon. In the resulting VC images, grounded features appear bright whereas floated appear darker under the right polarity.

FIGS.2A and2Bare diagrams illustrating planar views of DUT structures for inline voltage contrast (VC) detection of contact opens on a p-type epi and an n-type epi, respectively, in accordance with the disclosed embodiments. The DUT structures200aand200binclude a fin202a/202bformed along a first direction over a substrate (not shown) and the fin202a/202bincludes a diffusion region210. The diffusion region210or epi layer is not visible in this view but is shown inFIG.2C, which illustrates a cross-section TEM image of a portion of DUT structure200that is representative of DUT structures200aand200b. Diffusion region210comprises a 1D diffusion, which includes a single fin for FinFET devices, and refers to the diffusion of dopant atoms in one dimension only, typically in the vertical direction of the device to form either a p-type fin and a p-type diffusion region or an n-type fin and an n-type diffusion region. The dopant atoms are diffused only in the vertical direction of the fin, resulting in a concentration profile that varies only along the vertical direction. This type of diffusion is used to create a heavily doped source and drain region in the fin.

Referring toFIGS.2A,2B, and2C, in embodiments an interlayer dielectric (ILD)212covers the substrate (not shown) from which the fin202is formed. Trench openings are etched in the ILD212and are filled with contact silicide and metallization to form a trench contact (TCN) segment206a/206b(collectively referred to as TCN segment206). The TCN segment206a/206bis formed along a second direction generally orthogonal to the first direction over the fin202a/202band in contact with the diffusion region210, as shown inFIG.2C. In embodiments, the TCN segment206a/206bis formed with a minimum allowed TCN length for a particular technology node, e.g., the smallest TCN feature in an integrated circuit structure product. The advantage of using the minimum allowed TCN length is that it enables localization to one unique epitaxial Si-contact metal interface. So one segment would equal to one defect which helps in yield learning as well as fault isolation and failure analysis.

Referring toFIGS.2A and2B, a floating gate204a/204bis formed generally parallel to the TCN segment206a/206b. Because the DUT structures200aand200bare dummy devices, the floating gate204a/204band the TCN segment206a/206bare not in contact with one another, and the floating gate204a/204bdoes not have a via formed thereon. However, a contact via208a/208bmay be optionally formed on the TCN segment206a/206b, which is useful when there is a desire to inspect the DUT structure200a/200bfrom a via layer formed over DUT structure200a/200b.

Referring toFIG.2A, the DUT structure200afor VC detection of contact opens on a p-type diffusion region or epi is shown. The TCN segment200ais minimum length and formed on a 1D p-type diffusion and is in contact with only one p-type epi. The DUT structure200acan be referred to as a p-type DUT structure. In one embodiment, the diffusion region210is a PTAP structure that comprises PMOS outside of an n-well in a p-type substrate, which results in improved VC signals.

Referring toFIG.2Bshowing the DUT structure200bfor VC detection of contact opens on an n-type diffusion region, the TCN segment200ais minimum length and formed on a 1D n-type diffusion. The DUT structure200bcan be referred to as an n-type DUT structure. In the case of n-type diffusion, the TCN segment200bis still in contact with only one n-type epi. However, n-type silicon does not naturally appear bright in VC images. Therefore, n-type DUT structure200bfurther includes a neighboring TCN segment214that is connected by one or more floating gates204bto a PTAP structure comprising a p-type fin202aladjacent to the TCN segment200b. Conduction through n-type DUT structure200bflows from the n-type TCN contact206bacross the n-type fin202bthrough the floating gate204bto the neighboring connected to PTAP structure, and then through the PTAP. The functionality of the p-type fin202alin the PTAP structure is to provide electrons to the n-type fin202bso that opens can be detected in the TCN segment206b. In VC mode, the PTAP structure generates bright regions in the resulting VC image. Although the PTAP structure is shown comprising only one p-type fin202al, in other embodiments, the PTAP structure may comprises multiple p-type fins.

In both DUT structures200a/200b, process corners are stretched by using a TCN segment that is of minimum length on only one epi. This allows for quicker fault isolation as the exact TCN-epi interface that is failing is known. The DUT structures200a/200bprovide inline detection of contact opens, which are difficult to detect and shaves 5-6 weeks of yield learning time by not having to run potential skews for solutions to end of line. The VC test is also non-destructive and thus can be run on production wafers that can go to end of line, thereby minimizing cost and also establishing correlations to known yield signals at end of line.

The DUT structures200a/200bare fabricated on a wafer using the same materials used to fabricate active integrated circuit (IC) structures on the wafer. However, the DUT structures200a/200bare not electrically connected to other components in the IC structure and serve only for detection of electrical opens/shorts between the TCN segments206a/206band the diffusion regions/epitaxial silicon. Subsequent to contact metallization, VC mode is performed. If the TCN segments206a/206bhave no open defects, the TCN segments206a/206bwill appear bright in the resulting VC image, as shown inFIG.3A.

FIG.3Ais a diagram showing an example VC image taken of a segment of different types of integrated circuit structures on a wafer. AndFIG.3Bshows a histogram of pixel intensity values that can be extracted from the VC image. The VC image300shows different types of features at different pixel intensity values. The different types of integrated circuit structures include PMOS type contacts or silicon structures, NMOS type contacts or silicon structures, PTAP structures, which are PMOS structures on a PMOS substrate, and NTAP structures, which are NMOS structures on an NMOS substrate. In the histogram ofFIG.3B, a zero pixel intensity is defined as a black and the lowest pixel intensity values generally correspond to a floating gate in the VC image. P-type silicone or substrate have high pixel intensity values. Typically, PTAP structures correspond to the highest (brightest) pixel values in the VC image, followed by PMOS structures. If a segment appears dark in the VC image300when it should appear bright, a defect may exists. Cross-section imaging can then be performed on that segment to reveal the defects, as shown inFIGS.1A-1C.

The DUT structures200a/200bdescribed above can be replicated to form a dummy integrated circuit structure comprising one or more arrays of DUT structures, as shown inFIGS.4A and4B.FIG.4Aillustrates a layout schematic400afor detection of TCN segment contact opens using arrays of p-type DUT structures200aon a wafer.FIG.4Billustrates a layout schematic400bfor detection of TCN segment contact opens using arrays of n-type DUT structures200bon a wafer.

FIG.5illustrates a view of a large array500of DUT structures200aand200bfromFIGS.2A and2Bto test the yield of a manufacturing process. The dummy DUT structures200aand200bare interspersed in white spaces between active devices on a wafer. The large arrays of DUT structures may span several 10s/100s of microns with a periodic arrangement of 1D diffusion regions and min length TCNs with floating/dummy gates that are not connected up to routing metal layers. A contact via may land on one or more of the minimum sized TCN segments to enable detection post via formation as well. The DUT structures can be detected by reverse engineering by polishing down to the via and FE stack and examining a planar TEM image.

A method of fabricating a device under test (DUT) structure for voltage contrast (VC) detection of manufacturing defects may include forming a fin along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is formed along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is formed generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon. A VC image is taken and a contact open is determined there when the TCN segment has low (dark) pixel intensity values in the VC image.

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus,FIGS.6A and6Bare top views of a wafer and dies that include one or more DUT structures for VC image detection of contact opens, in accordance with one or more of the embodiments disclosed herein.

Referring toFIGS.6A and6B, a wafer600may be composed of semiconductor material and may include one or more dies602having integrated circuit (IC) structures formed on a surface of the wafer600. Each of the dies602may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more DUT structures for VC image detection of contact opens), such as described above. After the fabrication of the semiconductor product is complete, the wafer600may undergo a singulation process in which each of the dies602is separated from one another to provide discrete “chips” of the semiconductor product. In particular, structures that include embedded non-volatile memory structures having an independently scaled selector as disclosed herein may take the form of the wafer600(e.g., not singulated) or the form of the die602(e.g., singulated). The die602may include one or more embedded non-volatile memory structures based independently scaled selectors and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer600or the die602may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die602. For example, a memory array formed by multiple memory devices may be formed on a same die602as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.7illustrates a block diagram of an electronic system700, in accordance with an embodiment of the present disclosure. The electronic system700can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system700may include a microprocessor702(having a processor704and control unit706), a memory device708, and an input/output device710(it is to be appreciated that the electronic system700may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system700has a set of instructions that define operations which are to be performed on data by the processor704, as well as, other transactions between the processor704, the memory device708, and the input/output device710. The control unit706coordinates the operations of the processor704, the memory device708and the input/output device710by cycling through a set of operations that cause instructions to be retrieved from the memory device708and executed. The memory device708can include a non-volatile memory cell as described in the present description. In an embodiment, the memory device708is embedded in the microprocessor702, as depicted inFIG.7. In an embodiment, the processor704, or another component of electronic system700, includes one or more DUT structures for VC image detection of contact opens, such as those described herein.

FIG.8is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more DUT structures for VC image detection of contact opens, in accordance with one or more of the embodiments disclosed herein.

Referring toFIG.8, an IC device assembly800includes components having one or more integrated circuit structures described herein. The IC device assembly800includes a number of components disposed on a circuit board802(which may be, e.g., a motherboard). The IC device assembly800includes components disposed on a first face840of the circuit board802and an opposing second face842of the circuit board802. Generally, components may be disposed on one or both faces840and842. In particular, any suitable ones of the components of the IC device assembly800may include a number of DUT structures for VC image detection of contact opens, such as disclosed herein.

In some embodiments, the circuit board802may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board802. In other embodiments, the circuit board802may be a non-PCB substrate.

The IC device assembly800illustrated inFIG.8includes a package-on-interposer structure836coupled to the first face840of the circuit board802by coupling components816. The coupling components816may electrically and mechanically couple the package-on-interposer structure836to the circuit board802, and may include solder balls (as shown inFIG.8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure836may include an IC package820coupled to an interposer804by coupling components818. The coupling components818may take any suitable form for the application, such as the forms discussed above with reference to the coupling components816. Although a single IC package820is shown inFIG.8, multiple IC packages may be coupled to the interposer804. It is to be appreciated that additional interposers may be coupled to the interposer804. The interposer804may provide an intervening substrate used to bridge the circuit board802and the IC package820. The IC package820may be or include, for example, a die (the die602ofFIG.6B), or any other suitable component. Generally, the interposer804may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer804may couple the IC package820(e.g., a die) to a ball grid array (BGA) of the coupling components816for coupling to the circuit board802. In the embodiment illustrated inFIG.8, the IC package820and the circuit board802are attached to opposing sides of the interposer804. In other embodiments, the IC package820and the circuit board802may be attached to a same side of the interposer804. In some embodiments, three or more components may be interconnected by way of the interposer804.

The interposer804may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer804may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer804may include metal interconnects810and vias808, including but not limited to through-silicon vias (TSVs)806. The interposer804may further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer804. The package-on-interposer structure836may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly800may include an IC package824coupled to the first face840of the circuit board802by coupling components822. The coupling components822may take the form of any of the embodiments discussed above with reference to the coupling components816, and the IC package824may take the form of any of the embodiments discussed above with reference to the IC package820.

The IC device assembly800illustrated inFIG.8includes a package-on-package structure834coupled to the second face842of the circuit board802by coupling components828. The package-on-package structure834may include an IC package826and an IC package832coupled together by coupling components830such that the IC package826is disposed between the circuit board802and the IC package832. The coupling components828and830may take the form of any of the embodiments of the coupling components816discussed above, and the IC packages826and832may take the form of any of the embodiments of the IC package820discussed above. The package-on-package structure834may be configured in accordance with any of the package-on-package structures known in the art.

FIG.9illustrates a computing device900in accordance with one implementation of the disclosure. The computing device900houses a board902. The board902may include a number of components, including but not limited to a processor904and at least one communication chip906. The processor904is physically and electrically coupled to the board902. In some implementations the at least one communication chip906is also physically and electrically coupled to the board902. In further implementations, the communication chip906is part of the processor904.

The processor904of the computing device900includes an integrated circuit die packaged within the processor904. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more DUT structures for VC image detection of contact opens, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip906also includes an integrated circuit die packaged within the communication chip906. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more DUT structures for VC image detection of contact opens, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device900may contain an integrated circuit die that includes one or more DUT structures for VC image detection of contact opens, in accordance with implementations of embodiments of the disclosure.

Thus, embodiments described herein include DUT structures for VC image detection of contact opens.

Example embodiment 1: A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

Example embodiment 2: The DUT structure of embodiment 1, wherein the TCN segment has a minimum allowed TCN length for a particular technology node.

Example embodiment 3: The DUT structure of embodiment 1 or 2, further comprising a contact via formed on the TCN segment.

Example embodiment 4: The DUT structure of embodiment 1, 2 or 3, wherein the DUT structure is used for VC contrast detection of contact open defects.

Example embodiment 5: The DUT structure of embodiment 1, 2, 3, or 4, wherein the fin is doped to form the p-type fin and the p-type diffusion region, the p-type diffusion region being a PTAP structure that comprises PMOS outside of an n-well in a p-type substrate.

Example embodiment 6: The DUT structure of embodiment 1, 2, 3, or 4 wherein the fin is doped to form the n-type fin and the n-type diffusion region, the DUT structure further comprising a neighboring TCN segment that is connected via the floating gate to a PTAP structure comprising a p-type fin adjacent to the neighboring TCN segment, the PTAP structure comprising PMOS outside of an n-well in a p-type substrate.

Example embodiment 7: The DUT structure of embodiment 1, 2, 3, 4, 5, or 6, wherein the DUT structure is replicated to form arrays of DUT structures.

Example embodiment 8: The DUT structure of embodiment 1, 2, 3, 4, 5, 6, or 7, wherein the DUT structure is fabricated on a wafer using materials used to fabricate active integrated circuit structures on the wafer.

Example embodiment 9: An integrated circuit (IC) structure for voltage contrast (VC) detection of manufacturing defects comprises a p-type device under test (DUT) structure. The p-type DUT structure comprises a p-type fin along a first direction over a substrate, the p-type fin having a p-type diffusion region. A first trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the p-type fin and in contact with the p-type diffusion region. A first floating gate is generally parallel to the first TCN segment over the p-type fin, wherein the first floating gate and the first TCN segment are not in contact, and the first floating gate does not have a via formed thereon. An n-type device under test (DUT) structure, comprises an n-type fin along a second direction over a substrate, the n-type fin having a n-type diffusion region. A second trench contact (TCN) segment is along a second direction generally orthogonal to the second direction over the n-type fin and in contact with the n-type diffusion region. A second floating gate is generally parallel to the second TCN segment over the n-type fin, wherein the second floating gate and the second TCN segment are not in contact, and the second floating gate does not have a via formed thereon. A neighboring TCN segment connected via the second floating gate to a PTAP structure comprising a p-type fin adjacent to the neighboring TCN segment, the PTAP structure.

Example embodiment 10: The integrated circuit (IC) structure of embodiment 9, wherein the p-type DUT structure and the p-type DUT structure are replicated to form one or more arrays of DUT structures.

Example embodiment 11: The integrated circuit (IC) structure of embodiment 10, wherein the one or more arrays of DUT structures are interspersed in white spaces between active devices on a wafer.

Example embodiment 12: The integrated circuit (IC) structure of embodiment 11, wherein the DUT structures are not electrically connected to other components in the IC structure and serve only for detection of electrical opens or shorts.

Example embodiment 13: A method of fabricating a device under test (DUT) structure for voltage contrast (VC) detection of manufacturing defects comprises forming a fin along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is formed along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is formed generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

Example embodiment 14: The method of embodiment 13, further comprising taking a VC image and determining there is a contact open in the DUT structure when the TCN segment has low pixel intensity values in the VC image.