Information processing apparatus and data transfer method

An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the register. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an information processing apparatus including multiple chips and a data transfer method.

Description of the Related Art

Increase in performance of central processing units (CPUs) and increase in size of electrical circuits have been advanced in recent years in order to support speeding up and complication of data processing. A method of increasing the number of circuits that are capable of being installed on one chip through high integration achieved by miniaturization of semiconductor processes and a method of dividing a circuit into multiple chips are known as the methods of increasing in size of the electrical circuits.

In order to increase the processing speed by dividing a circuit into multiple chips and performing the processes in parallel, it is necessary to transfer data between the chips at high speed. In order to achieve this, a method of connecting multiple image processing units using a Peripheral Component Interconnect (PCI) Express interface, which is a high-speed serial interface standard, to realize parallel image processing is proposed (refer to Japanese Patent Laid-Open No. 2005-323159).

However, since it is necessary to add PCI Express switches in order to connect the multiple image processing units to the PCI Express interface, which offers point-to-point connection, in the method disclosed in Japanese Patent Laid-Open No. 2005-323159, there is a problem in that the cost is increased.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, an information processing apparatus includes a first chip, a second chip, and a third chip, wherein the first chip, the second chip, and the third chip are connected in series to each other, wherein the second chip includes a receiving unit configured to receive data and address information attached to data from the first chip, a register configured to store address translation information, a determination unit configured to determine whether the address information attached to the data received from the first chip by the receiving unit corresponds to an address translation area based on the address translation information set to the register, an address translation unit configured to translate the address information attached to the data and output the translated address information to an internal bus with the received data, a controller unit configured to control to store data to which address information corresponding to an address area set for the second chip is attached among the data received via the internal bus in a memory for the second chip, and a transmission unit configured to transmit data to which address information corresponding to an address area set for transfer to the third chip is attached among the data received via the internal bus to the third chip, and wherein the address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will herein be described with reference to the attached drawings.

First Embodiment

In a first embodiment, an image processing apparatus is exemplified as an information processing apparatus for description. The information processing apparatus is not limited to the image processing apparatus and may be any apparatus as long as the apparatus includes multiple chips and data transfer is performed between the chips. The image processing apparatus is, for example, a printer or a scanner. In addition, the image processing apparatus is, for example, a multifunctional printer, a copier, or a plotter, which has a printing function and a scanning function. A method is exemplified in the first embodiment in which the data transfer is performed from a controller chip to multiple image processing chips while performing address translation in the image processing apparatus.

FIG. 1is a block diagram illustrating an exemplary configuration of the image processing apparatus according to the first embodiment. A microchip (integrated circuit) is an electronic circuit typically located on one plate (“chip”) of semiconductor material. As a circuit in which all or some of the circuit elements are inseparably associated and electrically interconnected so that it is considered to be indivisible for the purposes of construction and commerce, a chip can be made very compact and have up to several billion transistors and other electronic components in an area the size of a human fingernail.

Referring toFIG. 1, an image processing apparatus100includes a controller chip110, an image processing chip120, and an image processing chip130. The image processing apparatus100is capable of being connected to a host personal computer (PC)190via a host interface191. The image processing apparatus100may be connected to the host PC190via a network.

The host PC190is an external apparatus of the image processing apparatus and is capable of transmitting a variety of data including print data via the host interface191.

The image processing apparatus100is capable of receiving the print data from the host PC190and performing printing on a recording medium (a sheet of paper) based on the received print data.

The controller chip110is connected to the image processing chip120via an internal interface181. The image processing chip120is connected to the image processing chip130via an internal interface182. In the first embodiment, each of the internal interface181and the internal interface182is PCI Express offering the point-to-point connection. As illustrated inFIG. 1, in the image processing apparatus100, the controller chip110, the image processing chip120, and the image processing chip130are connected in series to each other.

The controller chip110includes a CPU111, a host communication unit112, an internal communication unit113, a random access memory (RAM) controller unit114, a read only memory (ROM) controller unit116, and a terminal control unit119. The CPU111, the host communication unit112, the internal communication unit113, the RAM controller unit114, the ROM controller unit116, and the terminal control unit119are connected to each other via a main bus118in the controller chip110.

The CPU111controls the controller chip110in accordance with programs stored in a ROM117.

The host communication unit112communicates with the host PC190via the host interface191. For example, the host communication unit112transmits and receives the print data to and from the host PC190and receives an instruction to control the image processing apparatus100from the host PC190. The internal communication unit113communicates with the image processing chip120via the internal interface181for transmission and reception of data and control.

The RAM controller unit114is connected to a RAM115provided outside the controller chip110via a system bus and controls reading from the RAM115and writing into the RAM115. The RAM115is a storage unit that stores temporary data, such as image data that is being processed. The RAM115is a dynamic random access memory (DRAM) in the first embodiment.

The ROM controller unit116is connected to the ROM117provided outside the controller chip110via the system bus and controls reading from the ROM117. The ROM117stores programs executed by the CPU111and programs executed by a CPU121in the image processing chip120and a CPU131in the image processing chip130described below.

The main bus118is an internal bus of the controller chip110. Data is capable of being transferred to each component in the controller chip110via the main bus118.

The terminal control unit119controls resetting of the CPU121in the image processing chip120and the CPU131in the image processing chip130described below.

An address is allocated in advance to each of the host communication unit112, the internal communication unit113, the RAM controller unit114, the ROM controller unit116, and the terminal control unit119. Each of the host communication unit112, the internal communication unit113, the RAM controller unit114, the ROM controller unit116, and the terminal control unit119includes an identification unit that determines whether the transferred data is for the own address based on the allocated address. For example, when the CPU111submits a request to write and transfer data to a certain address to the main bus118, either of the host communication unit112, the internal communication unit113, the RAM controller unit114, the ROM controller unit116, and the terminal control unit119determines that the writing and transfer request is for the own address and acquires the address in the writing and transfer request and data corresponding to the address.

The image processing chip120includes the CPU121, a first internal communication unit122, a second internal communication unit123, a RAM controller unit124, a printing control unit126, and a reset control unit129. The CPU121, the first internal communication unit122, the second internal communication unit123, the RAM controller unit124, the printing control unit126, and the reset control unit129are connected to each other via a main bus128.

The CPU121controls the image processing chip120in accordance with programs.

The first internal communication unit122communicates with the controller chip110via the internal interface181. The second internal communication unit123communicates with the image processing chip130via the internal interface182.

The RAM controller unit124is connected to a RAM125provided outside the image processing chip120via a system bus and controls reading from the RAM125and writing into the RAM125. The RAM125is a storage unit that stores temporary data, such as image data that is being processed.

The printing control unit126controls a printing unit127. The printing unit127causes ink or toner to adhere to a medium, such as a sheet of paper, based on the print data to generate a printed product.

The main bus128is an internal bus of the image processing chip120. Data is capable of transferred to each component in the image processing chip120via the main bus128. The reset control unit129includes a register (not shown inFIG. 1) to receive an address translated from a different address in the first internal communication unit122. The reset control unit129may release a resetting of the CPU121based on the received address.

The image processing chip130includes the CPU131, a first internal communication unit132, a second internal communication unit133, a RAM controller unit134, a printing control unit136, and a reset control unit139. The CPU131, the first internal communication unit132, the second internal communication unit133, the RAM controller unit134, the printing control unit136, and the reset control unit139are connected to each other via a main bus138.

The CPU131controls the image processing chip130in accordance with programs.

The first internal communication unit132communicates with the image processing chip120via the internal interface182.

The RAM controller unit134is connected to a RAM135provided outside the image processing chip130via a system bus and controls reading from the RAM135and writing into the RAM135. The RAM135is a storage unit that stores temporary data, such as image data that is being processed.

The printing control unit136controls a printing unit137. The printing unit137causes ink or toner to adhere to a medium, such as a sheet of paper, based on the print data to generate a printed product.

The image processing chip130differs from the image processing chip120in that, where the second internal communication unit123in the image processing chip120communicates with the image processing chip130, the second internal communication unit133in the image processing chip130has no chip to which the second internal communication unit133is connected.

The main bus138is an internal bus of the image processing chip130. Data is capable of transferred to each component in the image processing chip130via the main bus138.

Although the controller chip110differs from the image processing chips120and130in configuration in the first embodiment, the chips that are connected in series to each other may have the same configuration. In this case, for example, chips having the functions of the controller chip110and the image processing chips120and130may be used.

The image processing apparatus according to the first embodiment is a printer and each of the printing unit127and the printing unit137composes part of a print head. The printing unit127and the printing unit137perform different processes based on data. For example, the printing unit127and the printing unit137may perform processes for different colors or may perform processes for different areas in an image of the same color. However, the printing unit127and the printing unit137are not limited to the above ones. As described above, the image processing performed by the image processing chip120is different from the image processing performed by the image processing chip130in the first embodiment.FIGS. 2A and 2Bare block diagrams illustrating exemplary configurations of the internal communication units in the respective chips according to the first embodiment.

The configuration of the internal communication unit113in the controller chip110and the configuration of the first internal communication unit122in the image processing chip120will now be described with reference toFIG. 2A.

The internal communication unit113in the controller chip110includes a main bus communication portion211, a transmission portion212, a reception address translation portion213, and an internal communication register portion214. The internal communication register portion214includes a source starting address register215, a source ending address register216, and a destination starting address register217. In general, a register is a small amount of fast storage acting as a quickly accessible location available to a digital processor's CPU.

The configuration of the first internal communication unit122in the image processing chip120is the same as that of the internal communication unit113in the controller chip110. Specifically, the first internal communication unit122includes a main bus communication portion221, a transmission portion222, a reception address translation portion223, and an internal communication register portion224. The internal communication register portion224includes a source starting address register225, a source ending address register226, and a destination starting address register227.

The transmission portion212in the internal communication unit113is connected to the transmission portion222in the first internal communication unit122via the internal interface181.

The data transfer without a PCI Express switch from the controller chip110to the image processing chip120will now be described. The main bus communication portion211transfers data acquired from the main bus118in the controller chip110to the transmission portion212. Address information is included in (is attached to) the data acquired from the main bus118and the address information and the data are directly transferred to the transmission portion212. The data and the address information are transferred from the transmission portion212to the transmission portion222in the image processing chip120via the internal interface181, and the data and the address information are transferred from the transmission portion222to the reception address translation portion223.

The reception address translation portion223performs an operation to translate a specific area in the transferred address information into another address area. The reception address translation portion223determines whether the input address corresponds to the area to be translated using the address setting in the source starting address register225and the address setting in the source ending address register226in the internal communication register portion224. If the input address corresponds to the area to be translated, the reception address translation portion223translates the address information in the area to be translated into other address information in accordance with the setting value in the destination starting address register227. Each chip is capable of translating multiple address spaces because the chip includes the multiple registers, which will be described in detail below. Each register in the internal communication register portion224is accessible from both the internal interface181and the main bus128.

After the translation of the address information, the reception address translation portion223outputs the translated address information and the data and transfers the address information and the data to the main bus communication portion221. The main bus communication portion221transfers the translated address information and the data to the main bus128.

With the configuration described above, the data transmitted from the controller chip110is capable of being transferred to a desired address area in the image processing chip120. The reception address translation portion213and the internal communication register portion214in the internal communication unit113in the controller chip110are the same as the reception address translation portion223and the internal communication register portion224in the first internal communication unit122in the image processing chip120.

The configuration of the second internal communication unit123in the image processing chip120and the configuration of the first internal communication unit132in the image processing chip130will now be described with reference toFIG. 2B.

The second internal communication unit123in the image processing chip120includes a main bus communication portion231, a transmission portion232, a reception address translation portion233, and an internal communication register portion234. The internal communication register portion234includes a source starting address register235, a source ending address register236, and a destination starting address register237.

The configuration of the first internal communication unit132in the image processing chip130is the same as that of the first internal communication unit122in the image processing chip120. Specifically, the first internal communication unit132includes a main bus communication portion241, a transmission portion242, a reception address translation portion243, and an internal communication register portion244. The internal communication register portion244includes a source starting address register245, a source ending address register246, and a destination starting address register247.

The transmission portion232in the second internal communication unit123is connected to the transmission portion242in the first internal communication unit132via the internal interface182.

In addition, the second internal communication unit123in the image processing chip120has the same configuration as that of the internal communication unit113in the controller chip110described above. The first internal communication unit132in the image processing chip130has the same configuration as that of the first internal communication unit122in the image processing chip120.

How to map memory spaces and how to perform the address translation in the first embodiment will now be described with reference toFIG. 3,FIGS. 4A and 4B, andFIG. 5.

FIG. 3illustrates an example of how to map memory spaces in the first embodiment. The memory spaces of the controller chip110, the image processing chip120, and the image processing chip130illustrated inFIG. 3indicate address maps of the main bus118, the main bus128, and the main bus138in the controller chip110, the image processing chip120, and the image processing chip130, respectively.

In the memory space of the main bus118in the controller chip110, an area from 0x8000_0000 to 0x8C00_0000 is allocated in advance to the internal communication unit113. In addition, in the memory space of the main bus118in the controller chip110, an area from 0x9000_0000 to 0x90FF_FFFF is allocated in advance to a register for internal circuits in the controller chip110. The internal circuits include the host communication unit112, the internal communication unit113, the RAM controller unit114, the ROM controller unit116, and the terminal control unit119. An area from 0xF000_0000 to 0xFFFF_FFFF is allocated in advance to the ROM controller unit116. The memory space of the PCI Express of the controller chip110is allocated for the image processing chip120and the image processing chip130, which will be described in detail below.

In the memory space of the main bus128in the image processing chip120, an area from 0x8000_0000 to 0x8C00_0000 is allocated in advance to the second internal communication unit123. In addition, in the memory space of the main bus128in the image processing chip120, an area from 0x9000_0000 to 0x90FF_FFFF is allocated in advance to a register for internal circuits in the image processing chip120. An area from 0x0000_0000 to 0x3FFF_FFFF is allocated in advance to the RAM controller unit124.

In the memory space of the main bus138in the image processing chip130, an area from 0x8000_0000 to 0x8C00_0000 is allocated in advance to the second internal communication unit133. In addition, in the memory space of the main bus138in the image processing chip130, an area from 0x9000_0000 to 0x90FF_FFFF is allocated in advance to a register for internal circuits in the image processing chip130. An area from 0x0000_0000 to 0x3FFF_FFFF is allocated in advance to the RAM controller unit134.

Each chip having the above configuration accesses a certain memory space depending on the transfer destination and transfers certain data. Upon reception of data, each chip determines with the first internal communication unit122or132whether the data is transferred to a space of the own chip or to a space of a chip subsequent to the own chip based on the address information. Specifically, each chip translates (rewrites) the address information based on the address information and translation information set in the internal communication register portion in the chip in advance.

In the memory space of the main bus118in the controller chip110, the area from 0xF000_0000 to 0xFFFF_FFFF is identified as access to the ROM117. For example, when the CPU111submits a request to read and transfer data to 0xF000_0000 to the main bus118, the ROM controller unit116determines that the request is for the own chip, acquires the address in the reading and transfer request, and reads out data from the ROM117.

In the memory space of the main bus118in the controller chip110, the area from 0x8000_0000 to 0x8C00_0000 is identified as access to the internal communication unit113. For example, when the CPU111submits the request to write and transfer data to 0x8400_0000 to the main bus118, the internal communication unit113determines that the request is for the own chip and acquires the address in the writing and transfer request and data corresponding to the address.

The address and the data that are acquired are transferred from the main bus communication portion211to the transmission portion212in the internal communication unit113and are transmitted to the image processing chip120via the internal interface181. The address here is 0x8400_0000 and is the same as that on the main bus118. The address and the data are transferred from the transmission portion222to the reception address translation portion223in the first internal communication unit122in the image processing chip120.

The reception address translation portion223translates the transferred address based on the register settings stored in the internal communication register portion224. The reception address translation portion223transfers the transferred data to the main bus communication portion221with the translated address. After the writing and transfer request is submitted from the main bus communication portion221to the main bus128, the transfer from the controller chip110to the image processing chip120is completed.FIGS. 4A and 4Billustrate examples of how to perform the address translation in the reception address translation portions in the first embodiment. The register configuration of the internal communication register portion224in the first internal communication unit122in the image processing chip120and how to perform the address translation in the reception address translation portion223will be described here.

Referring toFIG. 4A, (a) illustrates exemplary settings in the address translation in a 16-MB space from 0x8000_0000 to 0x80FF_FFFF. A source starting address 0x8000_0000 is set in the source starting address register225and a source ending address 0x80FF_FFFF is set in the source ending address register226. A destination starting address 0x9000_0000 is set in the destination starting address register227. With the above settings, the 16-MB space from 0x8000_0000 to 0x80FF_FFFF is translated into 0x9000_0000 to 0x90FF_FFFF. The CPU111or the CPU121sets destination addresses for the registers in the image processing chip120in accordance with the content of processing to the transfer data.FIG. 5is a flowchart illustrating an exemplary process of translating an address, which is performed by the reception address translation portion223.

Referring toFIG. 5, in Step S501, the reception address translation portion223acquires an address that is input.

In Step S502, the reception address translation portion223determines whether the address acquired in Step S501corresponds to an address translation area set in the internal communication register portion224. If the following condition is met, the reception address translation portion223determines that the address acquired in Step S501corresponds to the translation area.
(Source starting address)≤(Acquired address)≤(Source ending address)

If the reception address translation portion223determines that the address acquired in Step S501corresponds to the translation area (YES in Step S502), in Step S503, the reception address translation portion223performs the address translation. The address is translated according to the following expression:
(Acquired address)−(Source starting address)+(Destination starting address)

If the reception address translation portion233determines that the address acquired in Step S501does not correspond to the translation area (NO in Step S502), in Step S504, the process illustrated inFIG. 5is terminated without translating the acquired address.

Referring toFIG. 4A, (b) illustrates exemplary settings in the address translation in a 16-MB space from 0x8100_0000 to 0x81FF_FFFF. A source starting address 0x8100_0000 is set in the source starting address register225and a source ending address 0x81FF_FFFF is set in the source ending address register226. A destination starting address 0x8100_0000 is set in the destination starting address register227. With the above settings, no translation is practically performed in the 16-MB space from 0x8100_0000 to 0x81FF_FFFF.

Referring toFIG. 4A, (c) illustrates exemplary settings in the address translation in a 64-MB space from 0x8400_0000 to 0x87FF_FFFF. A source starting address 0x8400_0000 is set in the source starting address register225and a source ending address 0x87FF_FFFF is set in the source ending address register226. A destination starting address 0x0000_0000 is set in the destination starting address register227. With the above settings, the 64-MB space from 0x8400_0000 to 0x87FF_FFFF is translated into 0x0000_0000 to 0x81FF_FFFF.

Referring toFIG. 4A, (d) illustrates exemplary settings in the address translation in a 64-MB space from 0x8800_0000 to 0x8BFF_FFFF. A source starting address 0x8800_0000 is set in the source starting address register225and a source ending address 0x8BFF_FFFF is set in the source ending address register226. A destination starting address 0x8800_0000 is set in the destination starting address register227. With the above settings, no translation is practically performed in the 64-MB space from 0x8800_0000 to 0x8BFF_FFFF.

Next, the register configuration of the internal communication register portion244in the first internal communication unit132in the image processing chip130and how to perform the address translation in the reception address translation portion243will be described.

Referring toFIG. 4B, (a′) illustrates exemplary settings in the address translation in a 16-MB space from 0x8100_0000 to 0x81FF_FFFF. A source starting address 0x8100_0000 is set in the source starting address register245and a source ending address 0x81FF_FFFF is set in the source ending address register246. A destination starting address 0x9000_0000 is set in the destination starting address register247. With the above settings, the 16-MB space from 0x8100_0000 to 0x81FF_FFFF is translated into 0x9000_0000 to 0x90FF_FFFF.

Referring toFIG. 4B, (b′) illustrates exemplary settings in the address translation in a 64-MB space from 0x8800_0000 to 0x8BFF_FFFF. A source starting address 0x8800_0000 is set in the source starting address register245and a source ending address 0x8BFF_FFFF is set in the source ending address register246. A destination starting address 0x0000_0000 is set in the destination starting address register247. With the above settings, the 64-MB space from 0x8800_0000 to 0x8BFF_FFFF is translated into 0x0000_0000 to 0x90FF_FFFF.

As described above, the pieces of address translation information including the address information in the source starting address register, the address information in the source ending address register, and the address information in the destination starting address register are stored in the internal communication register portion in each chip.

How to perform the address translation in accordance with the settings in the internal communication register portion will now be described with reference toFIG. 3andFIGS. 4A and 4B. As illustrated inFIG. 4A, pieces of information concerning the address translation for the four areas in the memory space of the main bus128are set in the internal communication register portion224in the image processing chip120. The settings in (a) inFIG. 4Acorrespond to a translation area (a) inFIG. 3, the settings in (b) inFIG. 4Acorrespond to a translation area (b) inFIG. 3, the settings in (c) inFIG. 4Acorrespond to a translation area (c) inFIG. 3, and the settings in (d) inFIG. 4Acorrespond to a translation area (d) inFIG. 3.

First, a path through which data is transferred from the controller chip110to the image processing chip120will be described. As described above, the settings in the address translation in (a) inFIG. 4Acorrespond to the translation area (a) inFIG. 3. Upon occurrence of the data transfer to an address 0x8000_0010 in the controller chip110, the transmission portion212transfers the address information and the data to the image processing chip120via the internal interface181as the transfer to 0x8000_0010. In the image processing chip120, the reception address translation portion223determines that the address 0x8000_0010 corresponds to the translation area and translates the address 0x8000_0010 into 0x9000_0010. The data is transferred from the controller chip110to the address 0x9000_0010 in the image processing chip120in the above manner.

As described above, the settings in the address translation in (c) inFIG. 4Acorrespond to the translation area (c) inFIG. 3. Upon occurrence of the data transfer to an address 0x8400_0010 in the controller chip110, the transmission portion212transfers the address information and the data to the image processing chip120via the internal interface181as the transfer to 0x8400_0010. In the image processing chip120, the reception address translation portion223determines that the address 0x8400_0010 corresponds to the translation area and translates the address 0x8400_0010 into 0x0000_0010. In other words, the address 0x8400_0010 corresponds to an address area set for own chip (the image processing chip120) in the internal communication register portion224and is translated into the address 0x0000_0010 in the own chip. The data is transferred to the RAM controller unit124via the main bus communication portion221and the main bus128. The RAM controller unit124stores the data in the RAM125. The data stored in the RAM125is read out via the RAM controller unit124, is subjected to certain processing in, for example, the printing control unit126in the image processing chip120, and is transmitted to the printing unit127. In other words, the RAM controller unit124determines that the address information that has been translated into 0x0000_0010 and has been transferred to the main bus128via the main bus communication portion221corresponds to the own chip.

Next, a path through which data is transferred from the controller chip110to the image processing chip130via the image processing chip120will be described.

As illustrated inFIG. 4B, pieces of information concerning the address translation for the two areas in the memory space of the main bus138are set in the internal communication register portion244in the image processing chip130. These settings are used to translate the addresses for the data transfer received from the image processing chip120in the reception address translation portion243in the image processing chip130. The settings in (a′) inFIG. 4Bcorrespond to a translation area (a′) inFIG. 3and the settings in (b′) inFIG. 4Bcorrespond to a translation area (b′) inFIG. 3. The data transfer path using the translation area (b) and the translation area (a′) will now be described. Upon occurrence of the data transfer to an address 0x8100_0020 in the controller chip110, the transmission portion212transfers the address information and the data to the image processing chip120via the internal interface181as the transfer to 0x8100_0020.

In the image processing chip120, the reception address translation portion223determines that the address 0x8100_0020 corresponds to the translation area and translates the address 0x8100_0020 into 0x8100_0020 (e.g., no translation is practically performed in the 16-MB space from 0x8100_0000 to 0x81FF_FFFF). The data transferred to 0x8100_0020 is transmitted to the image processing chip130via the main bus128, the second internal communication unit123, and the internal interface182.

In the image processing chip130, the reception address translation portion243determines that the address 0x8100_0020 corresponds to the translation area and translates the address 0x8100_0020 into 0x9000_0020. The data transferred to 0x9000_0020 is transferred to the address 0x9000_0020 in the image processing chip130via the main bus138. The data is capable of being transferred from the controller chip110to the address 0x9000_0020 in the image processing chip130through the above path.

Similarly, the transfer from the controller chip110to the address 0x0000_0000 in the image processing chip130, illustrated inFIG. 3, is also capable of being performed via the translation area (d) in the image processing chip120and the translation area (b′) in the image processing chip130. The data transferred to 0x0000_0000 is transferred to the RAM controller unit134via the main bus138. The RAM controller unit134stores the data in the RAM135. The data stored in the RAM135is read out via the RAM controller unit134, is subjected to certain processing in, for example, the printing control unit136in the image processing chip130, and is transmitted to the printing unit137.

In the first embodiment, combination of the multiple address translation operations in the multi-chip configuration in which the multiple chips area connected in series to each other allows the data transfer between chips via an intermediated chip and the data transfer between adjacent chips to be efficiently performed.

More specifically, even in the case in which the multiple chips are connected in series to each other, the address translation allows data to be transferred to a desired chip without using any switch or the like, such as a PCI Express switch, or without intervening firmware. The data to be transferred to the next image processing chip130is capable of being transferred to the image processing chip130without being stored in the RAM125corresponding to the image processing chip120.

A case will now be described with reference toFIGS. 6A and 6Bin which the destination address is dynamically changed in the image processing apparatus according to the first embodiment.

The destination address set in the internal communication register portion is changed after the transfer of data in this case.

First, the data transfer from the controller chip110to the image processing chip120will be described. In order to transfer the data allocated to the address space from 0x8400_0000 to 0x87FF_FFFF in the controller chip110to 0x0000_0000 in the image processing chip120, the destination address of the translation area (c) is set to a translation area (c′). Since this setting is similar to the translation area (c) in the image processing chip120illustrated inFIG. 4A, a description of this setting is omitted herein. With this setting, first data allocated to the address space from 0x8400_0000 to 0x87FF_FFFF in the controller chip110is capable of being transferred to the space from 0x0000_0000 to 0x03FF_FFFF in the image processing chip120.

The destination address of the translation area (c) is changed to the setting values in a translation area (c″) after the first data is transferred in the above manner. The destination address is changed from 0x0000_0000 to 0x0400_0000. Then, after the change of the destination address, second data allocated to the address space from 0x8400_0000 to 0x87FF_FFFF in the controller chip110is transferred. The second data allocated to the address space from 0x8400_0000 to 0x87FF_FFFF in the controller chip110is capable of being transferred to a 64-MB space from 0x0400_0000 in the image processing chip120.

Next, the data transfer from the controller chip110to the image processing chip130will be described.

Settings are made to transfer the data allocated to the address space from 0x8800_0000 to 0x8BFF_FFFF in the controller chip110to the image processing chip130via the image processing chip120. The settings in the translation area (d) in the image processing chip120are used without change and the destination address of the translation area (b) in the image processing chip130is set to the translation area (b′). Since this setting is similar to the translation area (d) in the image processing chip120illustrated inFIG. 4Aand the translation area (b′) in the image processing chip130illustrated inFIG. 4B, a description of this setting is omitted herein. With this setting, first data allocated to the address space from 0x8800_0000 to 0x8BFF_FFFF in the controller chip110is capable of being transferred to a 64-MB space from 0x0000_0000 in the image processing chip130.

The CPU111or the CPU121changes the settings in the translation area (b′) to setting values in a translation area (b″) based on the data after the first data is transferred in the above manner. Specifically, the destination address is changed from 0x0000_0000 to 0x4000_0000. Then, after the change of the destination address, second data allocated to the address space from 0x8800_0000 to 0x8BFF_FFFF in the controller chip110is transferred. The second data is capable of being transferred to a 64-MB space from 0x0400_0000 in the image processing chip130via the image processing chip120.

As described above, changing the destination address of the registers in the internal communication register portion after the data transfer allows the data transfer to an area (a total of 128 MB) larger than the address space of 64 MB in the transfer from the controller chip110to the image processing chip130. Similarly, also in the transfer from the controller chip110to the image processing chip120, use of the settings in the translation area (c′) and the setting values in the translation area (C″) allows the data transfer to an area larger than the address space of 64 MB.

In other words, dynamically changing the destination address allows the amount of data exceeding that in the address translation area to be transferred between the chips.

An exemplary sequence of the image processing apparatus100will now be described with reference toFIGS. 7A to 7C.

FIGS. 7A to 7Care flowcharts illustrating a startup sequence of the image processing apparatus100.

Upon turning on of the controller chip110, the image processing chip120, and the image processing chip130, the startup sequence is started. The chips are in a communication state in response to the turning on of the controller chip110, the image processing chip120, and the image processing chip130.

Referring toFIG. 7A, in Step S701, a reset signal connected to a reset terminal of the controller chip110is changed from a Low level to a High level when the power state of the controller chip110is stabilized after the turning on of the controller chip110. As a result, the resetting of the controller chip110is released.

In Step S702, the resetting of the CPU111in the controller chip110is released in response to the reset release of the controller chip110.

In Step S703, the CPU111the resetting of which has been released reads out a startup program from the ROM117to initialize the controller chip110.

In Step S704, the internal communication register portion214in the internal communication unit113is set. In Step S705, the source starting address register215to the destination starting address register217for the address translation in the internal communication unit113are set. These settings are used in a case in which data is transferred from the image processing chip120or the image processing chip130to the controller chip110. Data is capable of being transferred from the image processing chip120or the image processing chip130to the controller chip110in the same manner as in the transfer of data from the controller chip110to the image processing chip120and the image processing chip130.

In Step S706, the CPU111causes the terminal control unit119in the controller chip110to set ports of the controller chip, which are connected to reset terminals of the image processing chip120and the image processing chip130, from a Low level to a High level.

In Step S721, the resetting of the image processing chip120is released. In Step S731, the resetting of the image processing chip130is released. Upon release of the resetting of the image processing chip120and the image processing chip130, the first internal communication unit122in the image processing chip120is in a state in which training to link to the internal interface181is repeated and the first internal communication unit132in the image processing chip130is in a state in which training to link to the internal interface182is repeated.

In Step S707, the CPU111in the controller chip110sets the internal communication unit113so as to start a link-up process with the internal interface181. The internal communication unit113in the controller chip110and the first internal communication unit122in the image processing chip120start the PCI Express link-up process via the internal interface181.

In Step S708, it is determined whether the link-up process is completed. If the link-up process is completed (YES in Step S708) and the communication with the internal interface181is ready, the sequence goes to Step S710inFIG. 7B.

Referring toFIG. 7B, in Step710and Step S723, the CPU111in the controller chip110sets the source starting address register225to the destination starting address register227for the address translation in the first internal communication unit122in the image processing chip120via the internal interface181. For example, the settings in (a) inFIG. 4Aare used here.

In Step S750, the RAM125in the image processing chip120is initialized. The initialization is performed by submitting the transfer request from the CPU111to an address 0x8000_0100. The transfer is performed by translating the address 0x8000_0100 into an address 0x9000_0100 by the reception address translation portion223in the image processing chip120via the internal interface181and writing the address 0x9000_0100 into the register in the RAM controller unit124in the image processing chip120.

In Step S751, the RAM controller unit124and the RAM125are initialized in accordance with the setting value written in Step S750. This makes the RAM125available.

In Step S711, program data for the image processing chip120is transferred to an address 0x0000_0000 in the image processing chip120. Specifically, the data stored in the ROM117is transferred from the controller chip110to the image processing chip120using the address 0x8400_0000 as a staring address.

In Step S724, the program data is written into an address space from the address 0x0000_0000 in the image processing chip120through the address translation, as illustrated inFIGS. 6A and 6B. The address space from the address 0x0000_0000 is mapped to the RAM controller unit124connected to the main bus128and is finally written into the RAM125. The address 0x0000_0000 corresponds to a boot vector of the CPU121in the image processing chip120.

In Step S712, the CPU111in the controller chip110releases the resetting of the CPU121in the image processing chip120. Specifically, the transfer request is submitted from the CPU111to the address 0x8000_00000. The transfer is performed by translating the address 0x8000_00000 into the address 0x9000_0000 by the reception address translation portion223in the image processing chip120via the internal interface181and writing the address 0x9000_0000 into the register in the reset control unit129in the image processing chip120. In Step S725, the reset control unit129releases the resetting of the CPU121based on the written data.

In Step S726, the CPU121the resetting of which has been released reads out a startup program stored in the RAM125to initialize the image processing chip120.

The CPU111in the controller chip110and the CPU121in the image processing chip120are in a state in which the CPU111and the CPU121are capable of operating in accordance with the programs through the previous steps.

Next, the image processing chip130is started.

Since Steps from S714to S720for the image processing chip130, which are performed by the controller chip110and which are illustrated inFIG. 7BandFIG. 7C, are similar to Steps from S705to Step S712for the image processing chip120described above, which are performed by the controller chip110, a description of Steps from S714to S720is omitted herein. In Step S770, the CPU111changes the address translation settings in the image processing chip120. Specifically, the CPU111changes the address translation settings from the settings in the translation area (c′) to the settings in the translation area (c″) inFIG. 6B. Changing the address translation settings to the predetermined values in accordance with the content of the data processing allows the data to be transferred to an area that is not the program area.

In Step S771, the address translation settings in the image processing chip130are changed. Specifically, the settings in (b′) are changed to the settings in (b″) inFIG. 6B. Changing the address translation settings allows the data to be transferred to an area that is not the program area.

In the first embodiment, it is possible to start up the three chips with one ROM. In addition, changing the address translation settings for program transfer to the address translation settings for data transfer allows an image data transfer area between the chips to be ensured.

According to the first embodiment, it is possible to increase the processing speed while keeping the low cost by using the multiple chips.

OTHER EMBODIMENTS

The present invention is not limited to the above embodiment. For example, although the configuration in which the three chips are connected to each other is described in the above embodiment, the present invention is not limited to this configuration. The present invention is applicable to a configuration in which four or more chips are used.

Although the address translation portions are provided at the reception side in the above embodiment, the arrangement of the address translation portions is not limited to this. The address translation portions may be provided for transmission.

Although the transfer from the controller chip is described in the above embodiment, the transfer is not limited to this. For example, the present invention is applicable to transfer from an image processing chip1to a main chip. The present invention is also applicable to transfer from an image processing chip2to the image processing chip1and transfer from the image processing chip2to the controller chip.

Although the example in which the two image processing chips have the same configuration is described in the above embodiment, the present invention is not limited to this. The image processing chips that are connected in series to each other may have different configurations.

Although the controller chip has a configuration different from those of the image processing chips in the above embodiment, the present invention is not limited to this. The controller chip and the image processing chips may have the same configuration.

Although each of the internal interfaces181and182is the PCI Express interface in the above embodiment, the present invention is not limited to this. Any interface may be used as long as peer-to-peer connection is established.

This application claims the benefit of Japanese Patent Application No. 2015-110372, filed May 29, 2015, which is hereby incorporated by reference herein in its entirety.