Semiconductor device

Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches (3) are formed in a charge accumulation region (6) of a p-type silicon substrate (1) to reduce a contact area between the p-type silicon substrate (1) and a lightly doped n-type well region (2), thereby reducing a leak current from the lightly doped n-type well region (2) to the p-type silicon substrate (1).

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. JP2008-215125 filed on Aug. 25, 2008, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device in which a leak current from a metal-oxide-semiconductor (MOS) capacitor to a silicon substrate is suppressed.

2. Description of the Related Art

When a MOS capacitor is formed on a silicon substrate and used at the same voltage as that applied to the silicon substrate, an electrode for the silicon substrate side of the MOS capacitor must be formed on a well region of an opposite conductivity to the silicon substrate. When the MOS capacitor has a large area and is used under a high temperature, in particular, the leak current becomes considerably large between the silicon substrate and the well region in which the electrode for the silicon substrate side is formed, causing a problem in circuit construction.

Conventional ways of avoiding the above-mentioned leak current include a method involving forming a capacitor with a first polysilicon layer and a second polysilicon layer being opposing electrodes, and a method involving separating, as in silicon on insulator (SOI), the silicon substrate and the well region in which the electrode on the silicon substrate side is formed, by an oxide film.

Apart from the problem of the leak current, as a way of realizing high integration of capacitors in a dynamic random access memory (DRAM) cell, conventionally, a trench capacitor which is formed by utilizing a recess surface of a trench formed in a silicon substrate has been used as described in JP 02-165663 A.

As has been described above, as a way of suppressing the leak current parasitically flowing from the capacitor to another circuit, when the capacitor is formed of two polysilicon layers, there is a need to add a step of forming the second polysilicon layer, and because the leak current between the electrodes is large compared with a capacitor formed of a silicon substrate and polysilicon interposing a gate oxide film therebetween, quality of an insulating film between the first polysilicon layer and the second polysilicon layer needs to be optimized. Further, when the well and the silicon substrate are separated by the oxide film using a SOI substrate, a cost for the substrate increases, becoming a problem.

SUMMARY OF THE INVENTION

Instead of using the two polysilicon layers or the SOI substrate as described above, the present invention utilizes a trench capacitor to reduce a contact area between a silicon substrate and a well which serves as an electrode on a silicon substrate side of a capacitor, thereby suppressing a leak current between the silicon substrate and the well which serves as the electrode on the silicon substrate side.

Specifically, the present invention provides a semiconductor device including a metal oxide semiconductor (MOS) capacitor, comprising: a silicon substrate of a first conductivity type; a lightly doped well region of a second conductivity type, which is formed by diffusing impurities into the silicon substrate; a charge accumulation region formed in the lightly doped well region of the second conductivity type; trenches formed in the charge accumulation region; a heavily doped region of the second conductivity type, which is formed outside the charge accumulation region and has a higher impurity concentration than an impurity concentration of the lightly doped well region of the second conductivity type; an oxide film formed in the trenches formed in the charge accumulation region and on a surface of the silicon substrate of the first conductivity type; a polysilicon electrode formed on the oxide film; and a substrate-side electrode formed to make contact with the heavily doped region of the second conductivity type.

The present invention also provides a semiconductor device including a MOS capacitor, comprising: a silicon substrate of a first conductivity type; a lightly doped well region of a second conductivity type, which is formed by diffusing impurities into the silicon substrate; a charge accumulation region formed in the lightly doped well region of the second conductivity type; trenches formed in the charge accumulation region; a heavily doped region of the second conductivity type, which is formed outside the charge accumulation region and has a higher impurity concentration than an impurity concentration of the lightly doped well region of the second conductivity type; a heavily doped charge accumulation region of the second conductivity type formed in the trenches formed in the charge accumulation region and on a surface of the silicon substrate of the first conductivity type; an oxide film formed on the heavily doped charge accumulation region of the second conductivity type; a polysilicon electrode formed on the oxide film; and a substrate-side electrode formed to make contact with the heavily doped region of the second conductivity type.

With the above-mentioned means, the contact area between the silicon substrate of the first conductivity type and the well region of the second conductivity type may be reduced, and hence the leak current between the silicon substrate of the first conductivity type and the well region of the second conductivity type may be reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a cross-sectional view of a semiconductor device100according to a first embodiment of the present invention. The semiconductor device100has the following structure. For example, in a p-type silicon substrate1having a resistance of 20 to 30 Ωcm, a lightly doped n-type well region2is formed to a depth of 20 μm with an impurity such as phosphorus at a concentration of about 1×1016cm−3. Further, a heavily doped n-type region7to make contact with a substrate-side electrode8is formed on a part of a surface of the lightly doped n-type well region2. The heavily doped n-type region7has a concentration of 1×1024cm−3and uses phosphorus or arsenic as an impurity species.

Subsequently, a plurality of trenches3each having a depth of 5 to 10 μm and an opening width of 2 to 3 μm are formed on a surface of the silicon substrate1. After forming the trenches3, the silicon substrate1is thermally oxidized to form an oxide film4with a thickness of 500 Å on the surface of the silicon substrate1and inner walls of the trenches3. On the oxide film4, a polysilicon film is deposited to a thickness of 4,000 Å, impurities are introduced to the polysilicon film to impart electrical conductivity, and then the polysilicon film is patterned to form a polysilicon electrode5on the lightly doped n-type well region2including the plurality of trenches3. A region below the electrode5is called a charge accumulation region6and serves as a capacitor. Then, an aluminum alloy is formed to a thickness of approximately 5,000 Å as the substrate-side electrode8on the heavily doped n-type region7.

By forming the trenches3in the charge accumulation region6as described above, a contact area between the p-type silicon substrate1and the lightly doped n-type well region2may be reduced, and hence a leak current between the p-type silicon substrate1and the lightly doped n-type well region2may be reduced. Note that the substrate and the well region have been described to be p-type and n-type, respectively, but the conductivity type may be opposite so that the substrate is n-type and the well region is p-type.

FIG. 2is a cross-sectional view of a semiconductor device101according to a second embodiment of the present invention. The semiconductor device101has the following structure. For example, in a p-type silicon substrate1having a resistance of 20 to 30 Ωcm, a lightly doped n-type well region2is formed to a depth of 20 μm with an impurity such as phosphorus at a concentration of about 1×1016cm−3. Further, a heavily doped n-type region7to make contact with a substrate-side electrode8is formed on a part of a surface of the lightly doped n-type well region2. The heavily doped n-type region7has a concentration of 1×1020cm−3and uses phosphorus or arsenic as an impurity species.

Subsequently, a plurality of trenches3each having a depth of 5 to 10 μm and an opening width of 2 to 3 μm are formed in a surface of the silicon substrate1. On inner walls of the trenches3and the surface of the silicon substrate1, a heavily doped n-type charge accumulation region9is formed. Note that the heavily doped n-type charge accumulation region9has a concentration of 1×1018to 1×1020cm−3. Then, the silicon substrate1is thermally oxidized to form an oxide film4with a thickness of 500 Å on the surface of the silicon substrate1and the inner walls of the trenches3. On the oxide film4, a polysilicon film is deposited to a thickness of 4,000 Å, impurities are introduced to the polysilicon film to impart electrical conductivity, and then the polysilicon film is patterned to form a polysilicon electrode5on the lightly doped n-type well region2including the plurality of trenches3. The electrode5is formed to have the same size as a size of the heavily doped n-type charge accumulation region9. Then, an aluminum alloy is formed to a thickness of approximately 5,000 Å as the substrate-side electrode8on the heavily doped n-type region7.

By forming the trenches3in the charge accumulation region6as described above, a contact area between the p-type silicon substrate1and the lightly doped n-type well region2may be reduced, and hence a leak current between the p-type silicon substrate1and the lightly doped n-type well region2may be reduced. Further, depletion of the polysilicon electrode5during application of a voltage may be prevented by forming the heavily doped n-type charge accumulation region9.