A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to content addressable memories, and more specifically, to a content addressable memory having a multi-stage priority encoder for encoding multiple matches in a content addressable memory.

2. Brief Description of the Related Art

Priority encoders are electronic logic circuits that determine which of a number of inputs has the highest or lowest priority. Priority encoders are used in a variety of computer systems, as well as other applications. Priority encoders can be utilized in conjunction with content addressable memory (CAM), for example.

Modern communications systems transmit data over digital networks. System resources are finite, so allocation of those resources becomes necessary. For example, system capacity limitations may restrict the amount of data that can be transmitted by the network, or a user may wish to give priority to certain categories of data over others.

Practically all digital networks make use of some form of packet or block type data format to dynamically route data packets or blocks through the network. The data contained in the packets can be categorized in various ways, including type of packet, packet content, size, creation date, and urgency of delivery, for example. Depending on the purpose of the communications system and the preferences of the user, it may be necessary to limit or expand the amount of bandwidth to be allocated to a particular category of data.

Content addressable memories (CAMs) are used in communications systems as search engines for routing paths in data network routers and switches. The packets being routed can be viewed as belonging to a particular category. Typically, a CAM issues a single search result that is independent of a packet category. Consequently, it is necessary for the user to handle bandwidth allocation, for example, by discarding search results for certain categories. A significantly more efficient way of utilizing a CAM as a search engine is needed.

CAM can be used to perform fast address searches. For example, Internet routers often include a CAM for searching an address containing specified data. Thus, CAMs allow routers to perform high speed address searches to facilitate more efficient communication between computer systems over computer networks. Besides routers, CAMs are also utilized in such areas as databases, network adapters, image processing, voice recognition applications, and others.

In contrast to random access memory (RAM), which returns data in response to requests, CAM returns an address where the requested data is located. In a typical application, a CAM memory array generates a number of match signals on a match line in response to a request. The match signals are provided to a priority encoder to determine the address corresponding to the highest priority match. In a typical application, a priority encoder can determine the highest priority match from among 128K match inputs.

Referring toFIG. 1, a typical priority encoder2is illustrated. Priority encoder2includes a highest priority indicator (HPI)4and an address encoder6. The operation of HPI4can be likened to a “thermometer” for determining which of the match results has the highest priority. Conventionally, match inputs from respective match lines in a CAM are applied to terminals IN0-IN5of HPI2. An ENABLE signal is provided. When multiple matches are encountered, the match line located on the lowest segment of the HPI is given the highest priority, by convention, as described further below. The match line that indicates a match on inputs IN0-IN5and which has the highest priority will cause the lowest output terminal PO0-PO5to change states, indicating a match.

As shown inFIG. 1, HPI4utilizes an arrangement of logic gates to determine which of the inputs has the highest priority. Each stage of HPI4includes an inverter, a NAND gate, and a NOR gate. A highest priority segment10includes inverter12which inverts the ENABLE signal, and supplies it to NOR gate14. NOR gate14also receives a signal on match line input IN0. ENABLE is supplied to NAND gate16, along with match line input IN0. The result from NOR gate14is supplied on output terminal PO0. Output terminal PO0supplies the match signal from the highest priority stage to address encoder6.

HPI2includes six priority stages, each stage having a successively lower priority. Thus, the signal from NAND gate16is supplied to the next logically lowest priority stage (physically higher on the “thermometer,” as shown inFIG. 1) formed similarly of inverter22, NOR gate24, and NAND gate26. NOR gate24supplies a signal to output terminal PO1, and NAND gate26supplies its signal to the third lowest priority stage formed of inverter32, NOR gate34, and NAND gate36. A similar fourth-lowest priority stage is shown which includes inverter42, NOR gate44, and NAND gate46. A similar fifth-lowest priority stage is shown which includes inverters52, NOR gate54, and NAND gates56, providing an output signal on PO4to address encoder6. A final sixth stage includes NOR gate58, providing its output signal on PO5.

In operation, matches supplied from a CAM (not shown) are indicated on match lines IN0-IN6as logic 0, the ENABLE signal having a logic 1. Thus, in the first stage, if match line IN0is low, output PO0will be high, indicating a highest priority match. If match lines IN1, IN2, and IN3are active low, output PO1will produce a high signal, indicating a highest priority match. The remaining output signals PO0and PO2-PO5will be logic low.

In certain applications, it may be desirable to encode more than one highest priority input. For example, in CAMs, the comparand data bits are implemented such that a comparison can be made for a logic state of 1, a logic state of 0, or a “don't care” state wherein bits in the comparand register are masked as not to be involved in the matching search, and a match is declared regardless of what state is in the respective “don't care” bits in the CAM words. These “don't care” bits are used typically in a search known in the art as a search for the longest match. As a result of a search for the longest match, multiple words in the CAM may match the un-masked data bits in the comparand register. In such typical application, a special multi-match detection circuit indicates the presence of multiple matches. Using a typical prior art priority encoder, only one match, the one with the highest priority, is recorded. It is desirable, instead, to find the identity of all the matching words. In order to determine the next highest priority match, the user must discard the highest priority match, and re-encode the CAM match results to obtain the next highest priority match. Such manual manipulation of the CAM results is time consuming and inefficient.

A priority encoder is needed that can encode multiple matches in a CAM.

BRIEF SUMMARY OF THE INVENTION

The multi-priority encoder is formed of several “single” priority encoders interconnected to allow the first priority encoder to report the highest priority match, the second priority encoder to report the second priority match, etc.

DETAILED DESCRIPTION OF THE INVENTION

In the illustrative embodiments of the present invention, match inputs are active “LOW,” wherein inputs which arc not active are at a logic state of “1,” and active inputs go to the state of “0.” The multi-priority encoder is comprised of a succession of identical circuits known as “highest priority indicators” or “single priority encoders.” In the circuits shown here, the first highest priority indicator generates an output indicating the first highest priority. The second highest priority indicator generates an output indicating the second highest priority. A third highest priority indicator generates an output indicating the third highest priority, etc.

FIG. 2illustrates an exemplary embodiment of a multi-priority encoder100according to the present invention, in which three levels of priority are provided: first, second, and third. In the priority encoder of the present invention, priority has two dimensions: one dimension, vertical, within each of the single priority encoders, and another dimension, horizontal, between the three single-priority encoders.

Within a single highest priority indicator, the highest priority input is at the bottom, and the level of priority descends with the ascending inputs. Within the multi-priority encoder, the highest priority is given to the single priority encoder on the left, with a descending priority towards the right.

Any active output of a higher priority single-priority indicator leads to logic circuitry preventing an active output of the same vertical priority level in corresponding lesser priority single-priority indicators.

Referring toFIG. 2, priority encoder100includes three highest priority indicators (HPIs)101,102, and103. The operation of HPIs101-103is like that of HPI4described above in connection withFIG. 1, and similarly can be likened to a “thermometer” for determining which of the match results has the highest priority. Match inputs from respective match lines in a CAM are applied to terminals PIN0-PIN3of HPI101. An P_ENABLE signal is provided. When multiple matches are encountered, the match line located on the lowest segment of HPI101is given the highest priority. The match line that indicates a match on inputs PIN0-PIN3and which has the highest priority will cause the output on the corresponding terminal PRI10-PRI13to change states, indicating a match.

As shown inFIG. 2, HPI101utilizes an arrangement of logic gates to determine which of the inputs has the first highest priority. Each stage of HPI101includes an inverter, a NAND gate, a NOR gate, and an OR gate. A highest priority segment110includes inverter112which inverts the ENABLE signal, and supplies it to NOR gate114. NOR gate114also receives a signal on match line input PIN0. ENABLE is supplied to NAND gate116, along with match fine input PIN0. The result from NOR gate114is supplied on output terminal PRI10, and to OR gate118. Output terminal PRI10supplies the match signal from the highest priority stage to an address encoder (not shown). The output of OR gate118is supplied to the highest priority stage of the second highest priority indicator102.

HPI101includes four priority stages, each ascending stage in the vertical direction having a successively lower priority. Thus, the signal from NAND gate116is supplied to the next logically lower priority stage (physically higher on the “thermometer,” as shown inFIG. 2) formed similarly of inverter122, NOR gate124, NAND gate126, and OR gate128. NOR gate124supplies a signal to output terminal PRI11, OR gate128passes its signal to the second highest priority stage of second highest priority indicator102, and NAND gate126supplies its signal to the third lowest priority stage of first highest priority indicator101. The third lowest priority stage of first highest priority indicator101similarly is formed of inverter132, NOR gate134, NAND gate136, and OR gate138. A similar fourth-lowest priority stage is shown which includes inverter142, NOR gate144, NAND gate146, and OR gate148. Additional lower priority stage are not shown, but are within the scope of the present invention.

In operation, matches supplied from a CAM (not shown) are indicated on match lines PIN0-PIN3as logic 0, the ENABLE signal having a logic 1. Thus, in the first stage110, if match line PIN0is low, output PRI10will be high, indicating a highest priority match. A logic 1, indicating no match, will be forwarded to the highest priority stage of second highest priority indicator102, formed of NOR gate214, NAND gate216, and OR gate218. A logic 1 similarly will be supplied to the highest priority stage of third highest priority indicator103, formed of NOR gate314, NAND gate316, and OR gate318. Thus, no further priority encoding effectively will take place in the current clock cycle for the signal of match line PIN0, and the output signals PRI20and PRI30will not indicate a match.

If, on the other hand, PIN0indicates no match (logic 1) and match lines PIN1, PIN2, and PIN3are active low, indicating a match on each line, output PRI11will produce a high signal, indicating a highest priority match, and a logic 1 will be passed on to second highest priority stage of second highest priority indicator102, formed of inverter222, NOR gate224, NAND gate226, and OR gate228. A logic 1 similarly will be supplied to the second highest priority stage of third highest priority indicator103, formed of inverter322, NOR gate324, NAND gate326, and OR gate328. Thus, no further priority encoding effectively will take place in the current clock cycle for the signal of match line PIN1, and the output signals PRI21and PRI31will not indicate a match.

The remaining output signals PRI12and PRI13will be logic low, and logic low signals will be supplied to the third and fourth highest priority stages of second highest priority indicator102. The third highest priority stage of second highest priority indicator102, formed of inverter232, NOR gate234, NAND gate236, and OR gate238, generates a logic 1 on output PRI22, and supplies a logic 1 to the third highest priority stage of third highest priority indicator103, formed of inverter332, NOR gate334, NAND gate336, and OR gate338.

The fourth highest priority stage of second highest priority indicator102, formed of inverter242, NOR gate244, NAND gate246, and OR gate248, generates a logic 0 on output PRI23, and supplies a logic 0 to the third highest priority stage of third highest priority indicator103, formed of inverter342, NOR gate344, NAND gate346, and OR gate348. The third match, originally supplied on match line PIN3, is indicated on output PRI33as a logic 1. Additional fourth, fifth, etc. highest priority indicators, coupled similarly, are within the scope of the present invention.

FIG. 3shows an alternative embodiment for a multi-priority encoder400, in which two levels of priority are encoded. Encoder400includes a first highest priority indicator401and a second highest priority indicator402. Referring toFIG. 3, a priority encoder400according to an alternative embodiment of the invention is shown. Encoder400includes a serial arrangement of two highest priority indicators401and402, each of which utilizes transistors to create a dynamic thermometer segment which propagates a logic LOW signal to indicate a priority match.

As shown inFIG. 3, first highest priority indicator401includes match lines PI_N0-PI_N4, p-channel pass transistors M2, M9, M17, M25, M33, n-channel transistors M4, M12, M20, M28, and M36, p-channel pass transistors M5, M13, M21, and M29, and n-channel transistors M1, M8, M16, M24, and M32. The match input data from a CAM (not shown) is supplied on lines PI_N0-PI_N4, and priority results are provided by the outputs of NOR gates404-408to second highest priority indicator402. Priority results also are provided on priority outputs PO00-PO04. An ENABLE_N input and VDDalso are provided.

Second highest priority indicator402includes match lines PI_N0-PI_N4, p-channel pass transistors M6, M14, M22, and M30, coupled in series with p-channel pass transistors M7, M15, M23, and M31. N-channel transistor M3, and paired couplings of n-channel transistors M10and M11, M18and M19, M26and M27, and M34and M35couple the outputs of NOR gates404-408to three-input NOR gates410-414. Priority result signals from second highest priority indicator402are provided on output signal lines PO10-PO14.

Highest priority indicators401and402are arranged such that only the highest priority input line having a match will produce a HIGH signal on its associated NOR gate in each highest priority indicator. In first highest priority indicator401, for example, if an active LOW signal indicating a match is present on match lines PI_N1and PI_N2, a logic 1 will result only on PO01, and passage of the match signal to second highest priority indicator402will be blocked. In the example, only the signal on line PI_N2will be passed along to the second highest priority indicator402. This will result in a second highest priority output (logic 1) on output PO12.

Referring toFIG. 4, a processor system500is represented which uses a CAM510employing a multi-match priority encoder511according to the present invention. Processor system500generally comprises a central processing unit (CPU)502, such as a microprocessor, that communicates with one or more input/output (I/O) devices504over a bus506. The processor system500also includes random access memory (RAM)508. One or more CAM devices510also communicate with CPU502, CAM510utilizing a priority encoder511according to the present invention. The system may also include peripheral devices such as a floppy disk drive512and a compact disk (CD) ROM drive514which also communicate with CPU502over the bus506.

FIG. 5illustrates a router600including a CAM containing a multi-match priority encoder according to the present invention. Router600incorporates a CAM array memory chip604as may be used in a communications network, such as, e.g., part of the Internet backbone. Router600includes a plurality of input lines and a plurality of output lines. Data transmitted from one location to another is sent in packet form. Prior to the packet reaching its final destination, packet are received devices, such as router600, for decoding data identifying the packet's ultimate destination, and deciding which output line and what forwarding instructions are required for the packet.

The present invention provides an apparatus and method for encoding multiple simultaneous matches in a CAM. While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims.