Programmable capacitor and method of operating same

A programmable capacitor in an integrated circuit (IC) comprises a conductive line located parallel to an interconnect. When a bias voltage is applied to the conductive line, a parasitic capacitance is created between the interconnect and the conductive line. By properly sizing and locating the conductive line, a desired capacitance can be coupled to the interconnect. A bias control circuit can apply or remove the bias voltage from the conductive line, thereby enabling the capacitance to be coupled or decoupled, respectively, from the interconnect. Because of its simple construction, multiple capacitive structures can be formed around a single interconnect to provide capacitive adjustment capability. By changing the number of conductive lines to which the bias voltage is applied, the total capacitance provided by the multiple capacitive structures can be varied. A feedback loop can be incorporated to provide adjustment during IC operation.

FIELD OF THE INVENTION

The present invention relates to capacitive devices, and more particularly, to a programmable capacitor in an integrated circuit.

BACKGROUND OF THE INVENTION

In integrated circuits (IC's), capacitors are commonly used for data storage, signal filtering, and timing adjustments. However, conventional IC capacitors are difficult and/or costly to produce within an IC due to the nature of current wafer processing techniques.FIG. 1Ashows a conventional planar capacitor101, which comprises a polysilicon layer130and an oxide layer140formed on a p-type substrate110. Polysilicon layer130and a depletion region112in substrate110provide an upper plate and a lower plate, respectively, for planar capacitor101. The dielectric constant of oxide layer140, along with the area of polysilicon layer130and the area of depletion region112control the capacitance of capacitor101. The simple geometry of planar capacitor101is relatively straightforward to manufacture. However, the planar construction of planar capacitor101requires that polysilicon layer130occupy a large area on the surface of an IC die. This large area makes the construction of planar capacitor101increasingly problematic as IC die sizes decrease and device densities increase.

FIG. 1Bshows a conventional trench capacitor102, comprising a polysilicon layer132having a plate portion133, and an oxide layer142extending into a trench114formed in a substrate110. Oxide layer142provides a dielectric layer between plate portion133and a depletion region113formed in substrate110around trench114. By orienting the capacitor “plates” in the vertical direction, trench capacitor102occupies significantly less IC die surface area than planar capacitor101. However, the irregular geometry of trench capacitor102significantly increases manufacturing complexity, thereby leading to increased cost and decreased reliability.

FIG. 1Cshows a conventional stacked capacitor103, comprising an oxide layer144sandwiched by an upper polysilicon layer134and an intermediate polysilicon layer150. Stacked capacitor103is formed over an NMOS transistor160. NMOS transistor160is not an essential component of stacked capacitor103, and can be replaced with other IC structures, such as bipolar transistors or resistive elements. NMOS transistor160comprises a polysilicon gate162and a gate oxide164formed over two n-type regions120in substrate110. An oxide layer166provides a surface insulating layer for NMOS transistor160. Intermediate polysilicon layer150is deposited over one of the n-type regions120of NMOS transistor160and a portion of oxide layer166. Intermediate polysilicon layer150also extends over a field oxide124that isolates NMOS transistor160from adjacent IC devices. Oxide layer144is formed over intermediate polysilicon layer150, and upper polysilicon layer134is deposited over oxide layer144to complete stacked capacitor103. The non-planar contours of upper polysilicon layer134and intermediate polysilicon layer150increase their effective surface areas, thereby increasing the capacitance of stacked capacitor103. Because stacked capacitor103is “stacked” over an existing IC structure, efficient IC die surface area utilization is provided. At the same time, the deep etch and subsequent step coverage issues of trench capacitor102are avoided. However, while stacked capacitor103is easier to produce than trench capacitor102, the formation of intermediate polysilicon layer150requires an additional polysilicon deposition step, thereby increasing overall manufacturing cost and cycle time for an IC including stacked capacitor103.

Due to variations inherent in semiconductor manufacturing processes, specific capacitance values are difficult to produce using the aforementioned conventional capacitance structures. The dielectric constant of an oxide layer can vary between production runs, and precise control of oxide layer thickness is difficult to achieve. Also, the non-planar configurations of the trench and stacked capacitors makes the areas of the polysilicon “plates” difficult to accurately control. Finally, during normal IC operation, temperature effects can change the material properties of the capacitive structures, leading to further variations in actual capacitance values. Therefore, conventional capacitive structures are ill-suited for situations requiring precise capacitance settings, such as delay lines and bandpass filters.

Accordingly, it is desirable to provide a capacitive structure in an IC that is compact, easily manufacturable, controllable, and adaptable to process and operating variations.

SUMMARY OF THE INVENTION

The present invention is directed towards apparatus and methods for creating capacitance in an integrated circuit (IC), overcoming the cost and accuracy limitations of conventional capacitive structures by utilizing controlled parasitic capacitance effects.

Typically, IC manufacturers attempt to eliminate parasitic (unwanted) capacitances in IC's. An IC comprises a variety of functional devices configured to perform specified sets of tasks. Dielectric material separates and isolates the functional devices from one another. Interconnects provide conductive paths between functional devices, thereby allowing signals to be transmitted from one functional device to another. When interconnects run parallel to one another, parasitic capacitances can be generated which impose undesirable effects on the signals travelling along the interconnects. Maintaining a large spacing between interconnects alleviates the problem, but the industry trend towards shrinking IC die sizes and increasing device densities makes such a technique unfeasible. Alternative methods such as multilevel, orthogonal placement of interconnects can reduce the effects of parasitic capacitances, but also increase manufacturing cost and complexity.

In an embodiment of the present invention, a conductive line is coupled to a bias control circuit. The conductive line is positioned parallel to an interconnect that electrically connects two IC devices within an integrated circuit. The bias control circuit applies a bias voltage to the parallel conductive line to induce a parasitic capacitance between the interconnect and the parallel conductive line. By making the parasitic capacitance equal to a desired capacitance, signals transmitted between the two IC devices along the interconnect can be delayed or filtered. The magnitude of the parasitic capacitance is controlled by the length of the parallel conductive line, the distance between the interconnect and the parallel conductive line, and the dielectric constant of the material between the interconnect and the parallel conductive line. Unlike an interconnect, which provides a conductive path between two or more IC devices, the parallel conductive line has no specific routing requirements, and can therefore be sized as necessary to provide the desired capacitance.

In another embodiment of the present invention, the bias control circuit comprises logic circuits to selectively bias the parallel conductive line to a desired voltage potential. Removal of the bias voltage from the parallel conductive line minimizes the capacitive path between the interconnect and the conductive line, thereby allowing the parasitic capacitance to be decoupled from the interconnect as desired.

In another embodiment of the present invention, multiple parallel conductive lines are placed along side the interconnect. By changing the number of the multiple parallel conductive lines to which the bias voltage is applied, the total capacitance coupled to the interconnect can be adjusted.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 2Ashows a circuit comprising a capacitive structure200in accordance with an embodiment of the present invention. Capacitive structure200comprises a conductive line202coupled to a bias control circuit260. Conductive line202is positioned parallel to an interconnect216that electrically couples a first integrated circuit (IC) device212and a second IC device214in a single integrated circuit. Bias control circuit260comprises circuitry to apply a bias voltage to conductive line202. When conductive line202is properly biased by bias control circuit260, a capacitance is coupled between conductive line202and interconnect216. Interconnect216typically comprises a metal or polysilicon line, and first IC device212and second IC device214can comprise various structures formed in an IC, such as transistors, inverters, or even configurable logic blocks (CLB's) of a programmable logic device (PLD) such as a field programmable gate array (FPGA). Conductive line202can be formed along side interconnect216using the same process steps used to create interconnect216, thereby eliminating the need for the additional manufacturing process steps typically required by conventional capacitive structures. However, conductive line202can also be formed over or under interconnect216, while still providing the desired capacitive function.

FIG. 2Bshows a capacitive structure201in accordance with a particular embodiment of the present invention. Capacitive structure201comprises a bias control circuit261coupled to a conductive line202. Bias control circuit261provides a conductive path between conductive line202and the Vss voltage supply terminal. In the described embodiment, the Vss voltage supply terminal is maintained at a voltage of 0V (ground). Because conductive line202is electrically connected to ground, a capacitive path is provided between interconnect216and ground.

FIG. 2Cshows a circuit electrically equivalent to the circuit ofFIG. 2B. Aresistance R216represents the line resistance of interconnect216, and a capacitor240represents a capacitance C240provided by capacitive structure201. Resistance R216is coupled between first IC device212and second IC device214, while capacitor240is coupled between interconnect216and the Vss voltage supply terminal, thereby forming an RC circuit between first IC device212and second IC device214. As is well known in the art, the charging and discharging time constant of a capacitor in an RC circuit is directly related to the resistance of the resistor and the capacitance of the capacitor. For the circuit shown inFIG. 2C, if an output signal from IC device212is a step function between ground (0V) and a maximum voltage Vmax, an input signal received by IC device214is the same as a voltage Vc across capacitor240. When capacitor240is being charged (the output signal from IC device212switching from 0V to voltage Vmax), a voltage Vc across capacitor240varies according to the equation:
Vc=Vmax(1−e−t/(R216C*C240))  (1)

Similarly, when capacitor240is being discharged (the output signal from IC device212switching from voltage Vmax to 0V), voltage Vc varies according to the equation:
Vc=Vmax*e−t/(R216*C240)(2)

In either the charging or discharging case, the change in voltage Vc is proportional to the exponential term e−t/(R216*C240). Therefore, the coupling of capacitor240to interconnect216creates an effective delay element between first IC device212and second IC device214. As can be seen from equations (1) and (2), the rate of change of voltage Vc is dependent on the value of capacitance C240. Therefore, by properly configuring conductive line202(FIG.2B), a desired delay can be applied to signals travelling between first IC device212and second IC device214.

FIG. 2Dshows an isometric representation of interconnect216and conductive line202isolated from one another by a dielectric material290. Conductive line202has a length L and a height h. Interconnect216and conductive line202are parallel and separated by a distance d. Capacitance C240formed between interconnect216and conductive line202is then defined by the equation:
C240((8.85×10−12F/mm)*k*L*h)/d(3)

where k is the dielectric constant of dielectric material290and all lengths are in units of meters. Dielectric material290is typically silicon dioxide, which can have a dielectric constant from 5 to 25, depending on the oxide manufacturing process. Other materials such as silicon nitride and various polyimides can also be used as dielectrics.

FIG. 3Ashows a capacitive structure301including a bias control circuit361coupled to a conductive line202, in accordance with another embodiment of the present invention. Bias control circuit361comprises a memory cell310coupled to the gate terminal of a pass transistor320. A first signal terminal of pass transistor320is coupled to conductive line202, and a second signal terminal of pass transistor320is coupled to the Vss voltage supply terminal. When the output of memory cell310is in a logic HIGH state, pass transistor320is turned on, thereby coupling conductive line202to the Vss voltage supply terminal and enabling the capacitive function of capacitive structure301. However, when the output of memory cell310is in a logic LOW state, pass transistor320is turned off. As a result, conductive line202is not connected to any voltage potential, or is left “floating”. Because line202is left in a floating state, it is not connected into the equivalent circuit of FIG.2C. As a result, the capacitor has little to no effect on signals transmitted on interconnect216. In this manner, capacitive structure301provides an “on/off switchable” capacitance that can be activated or de-activated as desired.

FIG. 3Bshows another embodiment of the present invention, a capacitive structure302that comprises a bias control circuit362coupled to conductive line202. Bias control circuit362comprises a transmission gate330, and memory cells310and340. Transmission gate330is formed by an NMOS pass transistor332, a PMOS pass transistor334, and an inverter336. A first signal terminal of NMOS pass transistor332is coupled to a first signal terminal of PMOS pass transistor334to form an output terminal of transmission gate330. A second signal terminal of NMOS pass transistor332is coupled to a second signal terminal of PMOS pass transistor334to form an input terminal of transmission gate330. A gate terminal of NMOS pass transistor332is coupled to an input terminal of inverter336to form a control terminal of transmission gate330. Finally, an output terminal of inverter336is connected to a gate terminal of PMOS pass transistor334to complete transmission gate330. The output terminal of transmission gate330is coupled to conductive line202. An output signal from memory cell310is applied to the control terminal of transmission gate330, whereas an output signal from memory cell340is applied to the input terminal of transmission gate330. When the output signal of memory cell310is in a logic HIGH state, both NMOS pass transistor332and PMOS pass transistor334are turned on, allowing the output signal of memory cell340to bias conductive line202. Because memory cell340can provide either a logic HIGH or logic LOW output signal, line202can be biased to either state, depending on the desired effect of capacitive structure302. Memory cell340ca be replaced with an adjustable voltage generator to provide even greater bias resolution. In addition, when the output signal of memory cell310switches to a logic LOW state, transmission gate330is turned off. This switching in turn biases conductive line202to a floating state which decouples conductive line202from interconnect216, thereby effectively eliminating the capacitive effect of capacitive structure302. Alternatively, separate memory cells could be used to control NMOS pass transistor332and PMOS pass transistor334.

FIG. 3Cshows a capacitive structure304according to another embodiment of the present invention. Capacitive structure304comprises a bias control circuit364coupled to a conductive line202. Bias control circuit364comprises a memory cell370, a first inverter372, a second inverter374, and a multiplexer376. An output terminal of IC device212is connected to an input terminal of first inverter372and a first input terminal of multiplexer376. An output terminal of first inverter372is connected to an input terminal of second inverter374and a second input terminal of multiplexer376. An output terminal of second inverter374is connected to interconnect216. An output terminal of multiplexer376is coupled to conductive line202which is positioned parallel to interconnect216. Finally, memory cell370is coupled to a control terminal of multiplexer376. Memory cell370controls the output signal provided by the output terminal of multiplexer376.

When an output signal from the output terminal of IC device212is generated, the transmission delays associated with first inverter372and second inverter374allow the output of multiplexer376to adjust the voltage on conductive line202before an output signal from the output terminal of second inverter374can be applied to interconnect216. By defining the signal passed by multiplexer376, memory cell370controls the capacitive effect provided by conductive line202.

If the output of memory cell370is a logic “0” (LOW), multiplexer376couples conductive line202with the output of first inverter372. As a result, a capacitive delay is applied to signals on interconnect216due to the capacitive coupling of conductive line202. For example, if the output of IC device212is in a logic LOW state for an initial period of time, interconnect216will also be in a LOW state, while conductive line202will be HIGH. When the output of IC device212switches from LOW to HIGH, the output of first inverter372goes LOW, bringing conductive line202to a logic LOW state also. Due to the delay introduced by second inverter374, interconnect216does not begin to transition until after conductive line202has switched from HIGH to LOW. Consequently, the transition of interconnect216from LOW to HIGH is delayed by the capacitive coupling of conductive line202. Similarly, when the output of IC device212transitions from HIGH to LOW, conductive line switches HIGH before interconnect216begins to transition, again ensuring a capacitive delay.

However, if the output of memory cell370is a logic “1” (HIGH), multiplexer376biases conductive line202with the output signal from IC device212, thereby minimizing the capacitive effect from conductive line202. For example, if the output of IC device212is in a logic LOW state for an initial period of time, both conductive line202and interconnect216will be biased LOW also. Then, when the output of IC device212switches to a logic HIGH state, conductive line202goes HIGH before interconnect216due to the delays introduced by first inverter372and second inverter374. As a result, when interconnect216ultimately begins to switch from LOW to HIGH, conductive line202is already at a logic HIGH state. Therefore, conductive line202produces minimal capacitive delay in the transition of interconnect216from a logic LOW to a logic HIGH state. Similarly, when the output of IC device212is switching from a logic HIGH state to a logic LOW state, conductive line202goes LOW before interconnect216begins to change. Therefore, the capacitive delay applied to the transition from HIGH to LOW of interconnect216is again minimized.

FIG. 4Ashows a variable capacitance structure400in accordance with another embodiment of the present invention. Variable capacitance structure400comprises a bias control circuit410connected to conductive lines202(a),202(b),202(c), and202(d). While four conductive lines are shown inFIG. 4A, any number of conductive lines can be formed depending on design requirements and the desired performance of variable capacitive structure400. Conductive lines202(a)-202(d) are positioned in parallel with interconnect216. Bias control circuit410provides independent “on/off switchable” bias control to conductive lines202(a)-202(d). Alternatively, separate bias control circuits could be provided for each of conductive lines202(a)-202(d). In either case, independent “on/off switchable” bias control allows the total number of conductive lines202(a)-202(d) providing a capacitive function at any given time to be controlled. Therefore, the total capacitance provided by variable capacitive structure400can be adjusted.

Multiple capacitive elements are feasible due to the low manufacturing cost and simple construction of capacitive structure400. Conductive lines202(a)-202(d) can be formed during the same manufacturing process steps used to produce interconnect216. No deep etches or extra polysilicon deposition steps are required.

The quantity, configuration, and distribution of conductive lines in variable capacitive structure400define the character of the adjustment capability of variable capacitive structure400. The sum of the capacitances provided by all of the conductive lines biased “on” by bias control circuit410defines the total capacitance coupled to interconnect216by variable capacitive structure400. For example, if conductive lines202(a)-202(d) have lengths L(a)-L(d), respectively, and all are a constant height h and a equal distance d from interconnect216, then equation (3), which defines the capacitance provided by a given conductive line, reduces to:
C202(x)=C*L(x); x=a, b, c, or d  (4)where C is a constant equal to ((8.85×10−2)*k*h)/s, s is the separation between the interconnect and the conductive lines, and k is the dielectric constant of the dielectric material isolating the interconnect from the conductive lines. If lengths L(a)-L(d) are all equal to a length2L, then four different non-zero capacitance values are available from variable capacitive structure400, as shown in Table 1.

As can be seen from the “Total Capacitance” column of Table 1, the capacitance provided by variable capacitive structure400can be changed in increments of 2 CL. Therefore, by shortening conductive lines202(a)-202(d), the adjustment resolution of variable capacitive structure400is increased. On the other hand, increasing the lengths of conductive lines202(a)-202(d) increases the range of capacitance values available from variable capacitive structure400.

Numerous benefits are provided by this adjustment capability. For example, post-production definition of a precise capacitance value would be possible, thereby minimizing the effects of any manufacturing process variations. The adjustment capability also enables tuning of the capacitive value during normal operation of the IC, thereby providing a means for compensating temperature-induced changes in material properties. In addition, variable capacitance structure400allows specific capacitance values to be provided as required during IC operation. Such multiple capacitance values can be used, for example, to provide varying breakpoint frequencies in a signal filter.

FIG. 4Bshows a variable capacitance structure420in accordance with another embodiment of the present invention. Variable capacitance structure420comprises capacitive structures301(a),301(b),301(c), and301(d). Capacitive structures301(a)-301(d) comprise bias control circuits360(a)-360(d), respectively, coupled to conductive lines203(a)-203(d), respectively. The use of multiple bias control circuits360(a)-360(d), rather than the single bias control circuit410shown inFIG. 4A, allows different implementations of bias control circuits to be used to bias different conductive lines if desired. Conductive lines203(a)-203(d) are all parallel to interconnect216and are all the same distance from interconnect216.

Conductive lines203(a)-203(d) have lengths L1(a)-L′(d), respectively. These lengths L′(a)-L′(d) are all different. Because each of conductive lines203(a)-203(d) has a different length, the capacitive effect each can produce is different. This difference of length allows a greater variety of total capacitances to be produced by variable capacitive structure420, as compared to the capacitances that would be achievable with the same number of conductive lines of identical length. Table 1 indicates that the four equal-length conductive lines of variable capacitive structure400shown inFIG. 4Acan couple four different non-zero capacitance values to interconnect216. However, if lengths L′(a), L′(b), L′(c), and L′(d) are equal to lengths L,2L,4L, and8L, respectively, then fifteen different non-zero capacitance values can be provided by variable capacitive structure420, as shown in Table 2. This increase in available capacitance values is achieved without increasing the number of conductive lines requiring bias control.

Alternatively, instead of varying the lengths of conductive lines203(a)-203(d), different capacitive effects from each conductive line can be produced by varying the distance or angle between interconnect216and each conductive line.

Also inFIG. 4B, conductive line203(d) is shown on the side of interconnect216opposite to conductive lines203(a)-203(c). This placement allows a greater number of conductive lines to be placed along a given length of interconnect216. However, the capacitive effect of conductive line203(d) is the same as the effect it would produce if it were on the same side of interconnect216as conductive lines203(a)-203(c). Conductive lines can be positioned at any location around or over or below interconnect216, although the conductive lines would ideally be in the same plane to simplify the manufacturing process.

FIG. 4Cshows a feedback control circuit430coupled to variable capacitance structure420(1). The structure and operation of variable capacitance structure420(1) are similar to those of variable capacitance structure420shown inFIG. 4B(discussed above). Therefore, the following discussion is specifically directed towards the structure and operation of feedback control circuit430.

A first input terminal of feedback control circuit430is connected to interconnect216at a node A, located at the output terminal of IC device212. A second input terminal of feedback control circuit430is connected to interconnect216at a node B, located at the input terminal of IC device214. In addition, bias control circuits360(a)-360(d) each include a control terminal coupled to an output terminal of feedback control circuit430, enabling feedback control circuit430to control the activation (biasing) of conductive lines203(a)-203(d). By comparing the timing of signals received at nodes A and B, feedback control circuit430can determine an actual (measured) delay introduced by variable capacitance structure420(1) into signals travelling on interconnect216. Feedback control circuit430can then activate or deactivate combinations of bias control circuits360(a)-360(d) until the actual delay is equal to a desired delay.

Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. For example, materials with varying dielectric constants could be used to isolate different conductive lines from the interconnect in order to produce varying capacitive effects. Thus, the invention is limited only by the following claims.