Semiconductor component and method for producing a semiconductor component

One aspect of the invention relates to a semiconductor component with a semiconductor body with a top side and with a bottom side. A first coil that is monolithically integrated with the semiconductor body is arranged distant from the bottom side and comprises N first windings, wherein N≧1. The first coil has a first coil axis that extends in a direction different from a surface normal of the bottom side.

TECHNICAL FIELD

Embodiments of the invention relate to semiconductor components and the production thereof.

BACKGROUND

Semiconductor components are often operated together with coils. However, extra handling like mounting the coil on a carrier is required. If the coil is to be electrically connected to the semiconductor component, the respective connection lines may cause electromagnetic interference. Hence, there is a need for an improved solution.

SUMMARY

One aspect of the invention relates to a semiconductor component with a semiconductor body with a top side and with a bottom side. In all embodiments of the present invention, the top side and the bottom side may be selected to be the sides of the semiconductor body that have the largest areas. A first coil that is monolithically integrated with the semiconductor body is arranged distant from the bottom side and comprises N first windings, wherein N≧1. For instance, N may be at least 2, or at least 5. The first coil has a first coil axis that extends in a direction different from a surface normal of the bottom side. In the sense of the present invention, a coil is regarded as monolithically integrated with a semiconductor body if the coil is mechanically joined to the semiconductor body and at least partly arranged in a trench formed in the semiconductor body.

Two, more than two, or all windings of the first coil may have the same size and/or shape. Further, the first coil may have a first coil axis that does not run perpendicularly to the bottom side. Optionally, such a first coil axis may run parallel to the bottom side.

A further aspect of the invention relates to a method for producing a semiconductor component with a coil that is monolithically integrated with a semiconductor body. To this, a semiconductor body with a top side and with a bottom side is provided and a first trench that extends from the top side into the semiconductor body is produced. Then, an electrically conductive first partial winding arranged on a surface of the first trench and an electrically conductive second partial winding arranged on the surface of the first trench are produced simultaneously. Thereby, the first partial winding is electrically insulated from the second partial winding. Each of the first and second partial windings includes two top ends. Also produced is a connection section that is arranged on the top side and that electrically conductively connects one of the first ends of the first partial winding and one of the first ends of the second partial winding.

DETAILED DESCRIPTION

Referring now toFIG. 1there is illustrated a partly completed first coil monolithically integrated with a semiconductor body3. The semiconductor body3includes a top side31and a bottom side32, wherein the top side31and the bottom side are the sides of the semiconductor body3with the largest areas. The semiconductor body3may be made of any bulk semiconductor material as it is conventionally used for producing semiconductor chips. For instance, suitable semiconductor bulk materials are silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium (Ga), gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), indium phosphide (InP) or indium arsenide (InAs).

The partly completed coil has electrically conductive first U-shaped sections19each having two first vertical sections11,12, and a first connection section13. In the embodiment illustrated inFIG. 1, each of the above-mentioned first and second partial windings is represented by one of the U-shaped sections19. Each first vertical section11includes a top end111and a bottom end112. Accordingly, each first vertical section12includes a top end121, and a bottom end122facing the bottom side32. Accordingly, each of the U-shaped sections19, that is, each of the partial windings19, has two top ends111and121. The two first vertical sections11,12extend from the first connection section13toward the top side31. In the sense of the present invention, a section11,12is regarded as a “vertical section” if the distance between its top end111and the bottom side32is greater than the distance between its bottom end112and the bottom side32. According to the illustrated embodiment, each of the vertical sections11,12may optionally be straight and include an angle of less than or equal to the normal direction n of the bottom side32. In each first U-shaped electrically conductive section, the respective first connection section13electrically conductively connects the respective first vertical sections11,12at their bottom ends112and122.

Optionally, all first vertical sections11,12and all connection sections13may be produced simultaneously, for instance by depositing one or more electrically conductive materials like metal or polycrystalline semiconductor material or combinations thereof. For instance, suitable metals are titanium (Ti), tungsten (W), aluminum (Al), copper (Cu). An example for a suitable polycrystalline semiconductor material is polycrystalline silicon.

As illustrated inFIG. 2, a coil can be produced by electrically connecting two or more first U-shaped sections in series. Such a series connection may be realized using one or more first conductor paths14, each first conductor path14electrically conductively connecting a top end111of a first vertical section11of a first U-shaped section to a top end121of a first vertical section12of a further U-shaped section. Such a conductor path14may be formed by one or more electrically conductive materials like metal or polycrystalline semiconductor material, for instance polycrystalline silicon. By electrically connecting a desired number of first U-shaped sections with a respective number of first connection sections14, a first coil10can be created.

As also illustrated inFIG. 2, a coil axis15of the first coil10may run in a direction which is different from the direction of a surface normal n of the bottom side32. For instance, the coil axis15may run parallel to the bottom side32, i.e., perpendicular to the surface normal n of the bottom side32.

In the same manner, two or more coils10,20may be monolithically integrated with a common semiconductor body3. In the embodiment illustrated inFIGS. 3 and 4, a first coil10and a second coil20are monolithically integrated with the semiconductor body3.FIG. 3shows the partly completed first and second coils10′,20′,FIG. 4the completed first and second coils10,20. The first and second coils10,20ofFIG. 3may have the same construction as the first coil10described with reference toFIGS. 1 and 2. Accordingly, the first coil10and the second coil20each have a first U-shaped electrically conductive section, each respective U-shaped section having two first vertical sections21,22, and a first connection section23. Each first vertical section21includes a top end211and a bottom end212. Accordingly, each first vertical section12includes a top end121, and a bottom end122facing the bottom side32. The two first vertical sections21,22run non-parallel to the bottom side32and extend from the first connection section23toward the top side31. In each first U-shaped electrically conductive section21,22,23, the respective first connection section23electrically conductively connects the respective first vertical sections21and22at their bottom ends212and222.

The two coils10,20may share a common volume. That is, the first coil10surrounds a first interior zone and the second coil20surrounds a second interior zone that overlaps the first interior zone.

As illustrated, the coil axes15and25of the first and second coils10and20, respectively, may optionally coincide.

The second coil20is formed by electrically connecting two or more second U-shaped sections in series. Similar to the first U-shaped sections, each second U-shaped section includes two second vertical sections21,22, and a second connection section23. Each second vertical section21includes a top end211and a bottom end212. Accordingly, each second vertical section22includes a top end221, and a bottom end222facing the bottom side32. The two second vertical sections21,22run substantially perpendicular to the bottom side32and extend from the second connection section23toward the top side31. In each second U-shaped electrically conductive section, the respective second connection section23electrically conductively connects the respective second vertical sections21,22at their bottom ends212and222.

Optionally, any coil of the present invention may be coreless, or, alternatively, include a magnetic core that is surrounded by at least one or even all windings of the coil. In this connection, a “magnetic core” is intended to mean a core that includes or consists of magnetic material.

An example of a partly completed coil10that includes a magnetic core4is illustrated inFIG. 5.FIG. 6shows the completed coil10with all windings surrounding the core4. In order to produce a coil4as shown inFIG. 6, a partly completed coil10′ as described with reference toFIG. 1is provided. Then, a magnetic core4is formed in the first U-shaped sections so as to achieve the arrangement ofFIG. 5. Subsequently, the coil10is completed by electrically conductively connecting two, more than two or all first U-shaped sections in series in the same manner as described with reference toFIG. 2by providing the required number of first conductor paths14on that side of the magnetic core4facing away from the bottom side32.

The magnetic core4may be ferromagnetic or ferrimagnetic and therefore comprise or consist of ferromagnetic or ferrimagnetic material. For instance, the magnetic core may comprise magnetic material that has a relative magnetic permability μrof at least 10 or of at least 200, and may range to 140,000. Suitable magnetic or ferromagnetic materials are, for instance, nickel (Ni), iron (Fe) or cobalt (Co). Optionally, a magnetic core4used in the present invention may consist of a magnetic or ferromagnetic material which is homogeneously distributed over the magnetic core4. Alternatively, the magnetic core4may have a layered structure with a number of magnetic or ferromagnetic layers which are electrically insulated from one another in order to avoid or reduce eddy currents. Furthermore, a ferro/ferrimagnetic metal powder which is embedded in dielectric isolation components, may be used as ferromagnetic or ferrimagnetic material.

In a corresponding manner illustrated inFIG. 8, a first coil10and a second coil20may share a common magnetic core4. That is, the magnetic core4is surrounded by at least one winding of the first coil10and at least one winding of the second coil20. Of course, a common magnetic core4may also be surrounded by all windings of the first and second coils10,20.

The first and second coils10and20may have the same structure as the first and second coils10and20described above with reference toFIGS. 3 and 4. In order to form a series connection with two or more U-shaped sections21,22,23electrically connected in series, one or more first conductor paths24each electrically conductively connect a top end211of a first vertical section21of a first U-shaped section to a top end221of a first vertical section22of a further U-shaped section. Such a conductor path24may be formed by one or more electrically conductive materials like metal or polycrystalline semiconductor material, for instance polycrystalline silicon. By electrically connecting a desired number of first U-shaped sections with a respective number of first connection sections24, a second coil20can be created.FIG. 7shows the arrangement ofFIG. 8prior to forming the first conductor paths14and24. Optionally, the first conductor paths14and24may be deposited simultaneously in the same deposition step.

Referring now toFIGS. 9A to 9Pand10A to10P, a first method for producing a semiconductor component with a monolithically integrated coil will be explained.FIG. 10x(x=A . . . P) corresponds toFIG. 9xand is a cross-sectional view for a respective cross-sectional plane marked inFIG. 9x, and a top view otherwise.

FIGS. 9A and 10Ashow a section of a semiconductor body3. For instance, the semiconductor body3may be a semiconductor wafer or any other flat semiconductor die. In order to produce a trench that extends from a top side31of the semiconductor body3into the semiconductor body3, a continuous hard mask layer40is deposited on the top side31. For instance, the hard mask layer40may include or consist of one or a combination with at least two of the following materials: an oxide, a polycrystalline semiconductor material like polycrystalline silicon etc., USG (undoped silicate glass), a nitride, and any combination of the mentioned materials.

Subsequently, a photoresist layer50is deposited on the hard mask layer40and photolithographically structured. The result is illustrated inFIGS. 9B and 10B. Then, as illustrated inFIGS. 9C and 10C, the hard mask layer40is structured by etching using the structured photoresist layer50as a mask. The photoresist mask can be removed by chemical ashing processes.

In a further, anisotropic etching step using the structured hard mask layer40as a mask, a trench35is etched into the semiconductor body3, seeFIGS. 9D and 10D. The trench35extends from the top side31into the semiconductor body3. Generally, the trench35may have any shape. For instance, in a view from the top side the trench35may be straight, u-shaped or ring-shaped. Optionally, as illustrated inFIGS. 9E and 10E, the hard mask layer40may be removed after the completion of the trench35. The trench35is defined by a ring-shaped side wall35w, and, on its side facing toward the bottom side32, by a bottom wall35b, wherein the side wall35wand the bottom wall35bform a simply connected, continuous surface that only consists of doped or undoped semiconductor material. Generally, however, in other embodiments a side wall35wmay also have shapes different from that of a ring.

Then, as illustrated inFIGS. 9F and 10F, a dielectric layer41, an optional barrier layer60, and an electrically conductive layer70are, in the mentioned order one after the other, subsequently and conformally deposited on the side wall35wand the bottom wall35b. All those layers41,60,70may be formed as continuous layers. The dielectric layer41serves to electrically insulate the coil to be produced against the semiconductor body3. For instance, the dielectric layer41may consist of or include on of the following materials: an oxide of a constituent of the semiconductor material from which the semiconductor body3is formed, e.g. silicon dioxide (SiO2), SiN, Si3N4, nitride, ONO. According to one embodiment, the dielectric layer41may include a silicon nitride layer, and an oxide layer arranged between the silicon nitride layer and the semiconductor body3. The optional barrier layer60serves to avoid that material from the electrically conductive layer70diffuses into the semiconductor body3. This is of particular relevance if the electrically conductive layer70consists of or comprises metal as metal can adversely affect the electric properties of an active semiconductor region which can optionally be integrated with the semiconductor body3adjacent to the trench35. If the electrically conductive layer70consists of doped or undoped polycrystalline semiconductor material, a barrier layer60is dispensable but may also be used. For instance, a barrier layer60may consist of or include TiW (Titanium/Tungsten).

In a subsequent step illustrated inFIGS. 9G and 10G, the remaining trench35is completely filled or overfilled with a mask material42, for instance a varnish, carbon (C), or an imide or an oxide. A suitable oxide is, e.g., a silicon oxide. Then, the top side of the mask material42is planarized and, as illustrated inFIGS. 9H and 10H, a photoresist layer51is formed on the planarized mask material42and photolithographically structured. The structured photoresist layer51is then used as a mask for anisotropically etching the mask material42, seeFIGS. 9J and 10J. Anisotropically etching the mask material42is performed selectively with regard to the electrically conductive layer70. That is, no or substantially no material of the electrically conductive layer70is removed.

In a subsequent isotropical etching process, for instance a wet etching process, the structured mask material42is used as a mask for selectively etching the electrically conductive layer70with regard to the barrier layer60. In embodiments in which no barrier layer60is used, the isotropical etching is selective with regard to the dielectric layer41. In any case, the result of the isotropical etching process is a number of U-shaped electrically conductive sections, each including a two first vertical sections11,12, and a first connection section13as described above with reference toFIG. 1, seeFIGS. 9K and 10K. Alternatively, only one such U-shaped electrically conductive section may be produced by etching away that parts of the electrically conductive layer70deposited on opposite sides of the side wall35w. In case of two or more such U-shaped electrically conductive sections, the sections are electrically insulated from one another.

Then, as illustrated inFIGS. 9L and 10L, the structured mask material42is removed from the trench and the two first vertical sections11,12, and a first connection section13, that is, the U-shaped electrically conductive sections, are exposed. Following, the trench is again filled or overfilled with a dielectric material43, seeFIGS. 9M and 10M, which is subsequently planarized on its top side such that the top ends111and121of the first vertical sections11and12, respectively, are exposed, seeFIGS. 9N and 10N. Suitable dielectric materials43are, e.g., oxides like silicon oxides, or plastics. Oxides may be deposited, for instance, by chemical vapor deposition (CVD).

In a further step illustrated inFIGS. 9P and 10P, first conductor paths14are produced on the planarized top side of the planarized dielectric material43and the top ends111,121such that the conductor paths14electrically conductively connect the U-shaped sections in series as explained above with reference toFIG. 2. For instance, suitable dielectric materials43include or consist of one or a combination with at least two of the following materials: silicon dioxide (SiO2), a CVD-oxide, an imide, an epoxy.

The conductor paths14can be procuded by depositing a continous layer of conductive material, for instance a metal or a doped polycrystalline semiconductor material, on the planarized top side of the planarized dielectric material43onto the top ends111,121, and by structuring the conductive material so as to obtain the required number of conductor paths14.

As is also illustrated inFIGS. 9P and 10P, a continuous layer33of doped or undoped semiconductor material may be arranged between the first coil10and the bottom side32. Thereby, each straight line35,36that runs perpendicular to the bottom side32and that intersects one, more than one or all first windings of the coil10, also intersects the continuous layer33.

Referring now toFIGS. 11A to 11Eand12A to12E, a second method for producing a semiconductor component with a monolithically integrated coil will be explained. In that coil, the first U-shaped electrically conductive sections, i.e. the two first vertical sections11,12and the first connection section13, include or consist of a silicide.FIG. 12x(x=A . . . E) corresponds toFIG. 11xand is a cross-sectional view if there is a cross-sectional plane marked inFIG. 11x, and a top view otherwise.

In the second method, an arrangement as illustrated inFIGS. 9L and 10Lis produced in the same manner as described with reference toFIGS. 9A to 9Land10A to10L, wherein the electrically conductive layer70includes or consists of polycrystalline silicon. In the subsequent process, the polycrystalline silicon will be used for forming a silicide. In the embodiment illustrated inFIGS. 11A to 11Eand12A to12E, a barrier layer60as described inFIGS. 9A to 9Land10A to10L is dispensed with but may optionally be provided. Insofar, the arrangement illustrated inFIGS. 11A and 12Acorresponds to the arrangement illustrated inFIGS. 9L and 10L.

As illustrated inFIGS. 11B and 12B, a metal layer80is desposited on the dielectric layer41and the structured electrically conductive layer70of the arrangement illustrated inFIGS. 11A and 12A. The metal layer80includes or consists of a metal that is able to form a silicide with the silicon contained in the electrically conductive layer70. Suitable silicidable metals are, for instance, titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), platinum (Pt), nickel (Ni) or any combination with two or more of those metals.

In order to form a silicide from the metal comprised in the metal layer80and the silicon or polysilicon comprised in the electrically conductive layer70, the metal layer80and the electrically conductive layer70may be tempered at a temperature of at least 200° 0 or of at least 250° C. so as to accelerate a diffusion of the silicidable metal into the electrically conductive layer70and, associated therewith, the formation of a silicide from the silicidable metal and the silicon comprised in the electrically conductive layer70.FIGS. 11C and 12Cillustrate the arrangement after the silicidation process. Reference numeral81designates the formed silicide. As becomes clear fromFIGS. 11C and 12C, the silicide81may be self aligned, i.e. a salicide (“self aligned silicide”).

As can be seen fromFIGS. 11C and 12C, the silicidation process does not necessarily affect the whole electrically conductive layer70. That is, underneath the silicide81, sections of the original electrically conductive layer70may remain. However, it is also possible that the silicidation process includes the whole electrically conductive layer70. In this latter case, substantially all silicon comprised in the electrically conductive layer70would be used for siliciding the metal of the metal layer80.

It is to be noted that adjacent to the silicide81, unsilicided sections of the metal layer80remain. In a subsequent isotropic etching process, for instance a wet etching or plasma etching process, the unsilicided sections of the metal layer80are removed in order to achieve a number of independent first U-shaped sections as illustrated inFIGS. 11A and 12A. Hence, different first U-shaped sections are electrically insulated from one another. Each first U-shaped section is formed of two first vertical sections11,12and a first connection section13as described with reference toFIG. 1. and includes or consists of a section of the formed silicide81. In other embodiments it is also possible that there is only one first U-shaped section. In any case, the remaining parts of the metal layer80are removed from opposite side walls of the trench. Otherwise, the respective parts of the metal layer80would short-circuit the adjacent U-shaped section. The etching process for removing the remaining parts of the metal layer80may be selective relative to the underlying dielectric layer41, that is, the etching process does not affect or at least does not substantially affect the dielectric layer41.

Then, as illustrated inFIGS. 11D and 12D, the trench is again filled or overfilled with a dielectric material43which is subsequently planarized on its top side such that the top ends111and121of the first vertical sections11and12, respectively, are exposed.

In a further step illustrated inFIGS. 11E and 12E, first conductor paths14are produced on the planarized top side of the planarized dielectric material43and the top ends111,121such that the conductor paths14electrically conductively connect the U-shaped sections in series as explained above with reference toFIG. 2. For instance, suitable dielectric materials43include or consist of one or a combination with at least two of the following materials: silicon dioxide (SiO2), a thermal oxide, a CVD oxide, an imide, an epoxy.

The conductor paths14can be procuded by depositing a continous layer of conductive material, for instance a metal or a doped polycrystalline semiconductor material, on the planarized top side of the planarized dielectric material43and the top ends111,121, and by structuring the conductive material so as to obtain the required number of conductor paths14.

Referring now toFIGS. 13A to 13Kand14A to14K, a third method for producing a semiconductor component with a monolithically integrated coil will be explained. In that third method, the first U-shaped electrically conductive sections, i.e. the two first vertical sections11,12and the first connection section13, are formed by electroplating a seed layer.FIG. 14x(x=A . . . K) corresponds toFIG. 13xand is a cross-sectional view if there is a cross-sectional plane marked inFIG. 13x, and a top view otherwise.

In the third method, an arrangement as illustrated inFIGS. 9F and 10Fis produced in the same manner as described with reference toFIGS. 9A to 9Fand10A to10F but without depositing the electrically conductive layer70on the barrier layer60. The respective arrangement is illustrated inFIGS. 13A and 14A.

A contiuous diffusion barrier, for instance TiW (titanium tungsten) with a thickness from 20 nm to 500 nm, and a metallic seed layer85with a thickness of, for instance, 20 nm to 500 nm, is deposited on the dielectric layer41, seeFIGS. 13B and 14B. For instance, the seed layer85may include or consist of one or a combination with at least two of the following metals: chromium (Cr), copper (Cu), nickel (Ni), palladium (Pd).

In a subsequent step illustrated inFIGS. 13C and 14C, the remaining trench35is completely filled or overfilled with a mask material42. Then, the top side of the mask material42is planarized and, as illustrated inFIGS. 13D and 14D, a photoresist layer51is formed on the planarized mask material42and photolithographically structured. The structured photoresist layer51is then used as a mask for anisotropically etching the mask material42. Anisotropically etching the mask material42is performed selectively with regard to the seed layer85. That is, no or substantially no material of the seed layer85is removed. The result is a structured mask layer, seeFIGS. 13E and 14E, which is used as a mask in a subsquent electroplating process illustrated inFIGS. 13F and 14F. Optionally, the structured photoresist layer51may be removed.

For electroplating, the arrangement is immersed into a solution which includes ions of the metal with which the seed layer to be electroplated. Electroplating takes place using a DC power supply100with a negative pole101and a positive pole102. The negative pole101is electrically conductively connected to the continuous seed layer85, the positive pole to an anode105. Optionally, the anode105may include or consist of the metal to be electroplated on the seed layer85. The voltage provided by the DC power supply100causes the positive charged metal ions to move toward and to coat the seed layer85in regions where it is not covered with the mask material42, thereby forming a structured metalliziation70on the continuous seed layer85. After electroplating is completed, the mask material42is removed, seeFIGS. 13G and 14G. Then, the continous seed layer85including the underlying diffusion barrier layer60is structured by overetching of the seed layer85and the barrier layer60using the structured metalliziation70as a mask. That is, a small amount of the structured metalliziation70is also etched away.

Then, as illustrated inFIGS. 13H and 14H, the trench is again filled or overfilled with a dielectric material43which is subsequently planarized on its top side such that the top ends111and121of the first vertical sections11and12, respectively, are exposed, seeFIGS. 13J and 14J.

In a further step illustrated inFIGS. 13K and 14K, first conductor paths14are produced on the planarized top side of the planarized dielectric material43and the top ends111,121such that the conductor paths14electrically conductively connect the U-shaped sections in series as explained above with reference toFIG. 2. For instance, suitable dielectric materials43include or consist of one or a combination with at least two of the following materials: silicon dioxide (SiO2), a CVD oxide, an epoxy, an imide.

Referring now toFIGS. 15A to 15Jand16A to16J, a fourth method for producing a semiconductor component with a monolithically integrated coil will be explained. In that fourth method, the first U-shaped electrically conductive sections, i.e. the two first vertical sections11,12and the first connection section13, are formed by electroless (i.e. non-galvanic) plating of a seed layer.FIG. 16x(x=A . . . J) corresponds toFIG. 15xand is a cross-sectional view if there is a cross-sectional plane marked inFIG. 15x, and a top view otherwise.

In the fourth method, an arrangement as illustrated inFIGS. 13B and 14Bis produced in the same manner as described with reference toFIGS. 13A to 13Band14A to14F. The respective arrangement is also illustrated inFIGS. 15A and 16A, respectively.

In a subsequent step illustrated inFIGS. 15B and 16B, the remaining trench35is completely filled or overfilled with a mask material42, for instance an oxide, an imide, a photoresist, an isolator, or carbon. Then, the top side of the mask material42is planarized and a photoresist layer51is formed on the planarized mask material42and photolithographically structured. Then, the structured photoresist layer51is used as a mask for anisotropically etching the mask material42, seeFIGS. 15C and 16C. Anisotropically etching the mask material42is performed selectively with regard to the seed layer85. That is, no or substantially no material of the seed layer85is removed. As a result, a structured mask layer42overlays the continuous seed layer85.

The structured mask layer42is used as a mask in a subsquent etching process in which the seed layer85and the underlying barrier layer60is etched away in regions where it is not covered with the mask material42(FIG. 15D). The etching, which may be isotropic or anisotropic, is performed selectively with regard to the barrier layer60. That is, no or substantially no material of the barrier layer60is removed. Optionally, the structured photoresist layer51may be removed prior to or during the etching of the seed layer85.

After the etching of the seed layer85is completed, the mask material42is removed as illustrated inFIGS. 15E and 16Eand the structured seed layer85is exposed.

In order to accomplish electroless (i.e. non-galvanic) plating of the structured seed layer85with a plating metal, the arrangement is immersed into a conventional plating solution that contains the plating metal. During electroless plating, the surface of the structured seed layer85but not the surface of the dielectric layer41is plated with the plating metal70. After electroless plating is completed, seeFIGS. 15F and 16F, a partly completed coil as described with reference toFIG. 1is present. The partly completed coil has electrically conductive first U-shaped sections each including two first vertical sections11,12, and a first connection section13. Each first U-shaped section includes a U-shaped section of the structured seed layer85and an overlying U-shaped section of the plating metal70.

Then, as illustrated inFIGS. 15G and 16G, the trench is again filled or overfilled with a dielectric material43which is subsequently planarized on its top side such that the top ends111and121of the first vertical sections11and12, respectively, are exposed, seeFIGS. 15H and 16H.

In a further step illustrated inFIGS. 15J and 16J, first conductor paths14are produced on the planarized top side of the planarized dielectric material43and the top ends111,121such that the conductor paths14electrically conductively connect the U-shaped sections in series as explained above with reference toFIG. 2. For instance, suitable dielectric materials43include or consist of one or a combination with at least two of the following materials: silicon dioxide (SiO2), a CVD oxide, an epoxy, an imide.

Referring now toFIG. 17A, there is illustrated a perspective view of a first coil10sharing a common magnetic core4with a second coil20. A cross-sectional view is shown inFIG. 17B. Different from the arrangements ofFIGS. 4 and 8, the windings1of the first coil10and the windings2of the second coil20do not enclose a common volume. In other words, the first coil10and the second coil20are arranged adjacent to one another. This allows for the first and second coils10,20to be produced simultaneously, in particular with one of the methods described above.

As describe above, a magnetic core4used as a core of a first and/or second coil10,20may be made of a magnetic or ferromagnetic or ferrimagnetic material which is homogeneously distributed over the magnetic core4. Alternatively, as illustrated inFIG. 17B, a magnetic core4may have a layered structure with a number of magnetic or ferromagnetic layers45which are electrically insulated from one another by intermediate dielectric or low-ohmic layers46in order to avoid or reduce eddy currents. For instance, the ferromagnetic layers45may consist of or include nickel (Ni), iron (Fe), or a mixture of nickel (Ni) and iron (Fe), or of a ferro- or ferrimagnetic metal powder, which is embedded in dielectric isolation components.

According to the present invention, a magnetic core4having as described in the above embodiments, i.e. having either a layered or a homogeneous structure, may be used as a core of a single coil10, for instance, if the single coil10is used as an inductivity, or as a common core with at least two coils10,20. In the latter case, the at least two coils10,20and the magnetic core4may form a transformer if two of the coils10,20are electrically insulated from one another. Generally, any arrangement with only one coil10or with at least two coils10,20may be used with a magnetic core4inserted in the coil(s)10,20, or without a magnetic core4. In the sense of the present invention, a coil10,20is regarded to not include a magnetic core4if the interior of the coil10,20has a relative magnetic permeability μrof about 1 and/or of less than 1. If a magnetic core4is provided, such a core may include a cavity, which, for instance, may be surrounded by the dielectric43(seeFIGS. 9M,9N,9P,10M,10N,10P,13H,13J,13K,14H,14J,14K,15G,15H,15J,16G,16H,16J).

The semiconductor body3of any of the coils and arrangements described above may, in addition to the at least one coil10,20, include one or more electrically active components, for instance a field effect transistor like a MOSFET (metal oxid semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), a JFET (junction field effect transistor), a TEDFET (trench extended drain field effect transistor), a diode. An example for such an arrangement is illustrated inFIG. 18. The arrangement is not yet completed. A first coil10is monolithically integrated with the same semiconductor body3as a field effect transistor or an IGBT. The field effect transistor includes a gate electrode71arranged in a trench38and/or on a surface of the semiconductor body3, and an optional field electrode or trench capacitor72arranged in a trench39, the last of which may be electrically connected to a source electrode to be produced. Both the gate electrode71and the field or capacitor electrode72are arranged in an active region30of the semiconductor component and are formed from sections of the same electrically conductive layer70as the first (in this embodiment U-shaped) sections of the first coil10. That is, the gate electrode71, the field electrode72and the (in this example U-shaped) sections of the first coil10may be produced simultaneously. In addition, a second coil20or even more such coils may be monolithically integrated with the semiconductor body3.

As is also illustrated inFIG. 18, a first coil10may be arranged distant from the bottom side32. For instance, the distance d32between the first coil10and the bottom side32may be at least 10 μm. Irrespective therefrom, the difference d70=D3−d32between the thickness D3of the semiconductor body3and the distance d32may be, for instance, in the range from 1 μm to 10 μm, and/or at least 5 μm. The thickness D3of the semiconductor body3may be, for instance, at least 20 μm. The thickness D3−d32is identical to the depth d70to which the partial windings19extend from the top side31into the semiconductor body3. If the coils are positioned at the chip-border, they may extend as deep or deeper than the vertical drift zone of the power transistor or IGBT. Therefore, the difference D3−d32may be in a range from 5 μm to 20 μm, to 60 μm, to 150 μm or even to 300 μm.

According to a further example illustrated inFIG. 19A, a transformer that includes first and second coils10,20monolithically integrated with the same semiconductor body3as a controllable semiconductor switch7may be used to galvanically decouple a control signal for controlling the controllable semiconductor switch7. To this, first and second coils10,20form a transformer. The first coil10is dielectrically insulated from the second coil20. The output of a first driver circuit D1is electrically connected to the first coil10. Hence, an output signal S1provided by the first driver circuit D1causes a signal S2in the second coil20which is electrically connected to the input of a second driver circuit D2. The second driver circuit D2may also be monolithically integrated with the semiconductor body3. An output of the second driver circuit D2is electrically connected to the gate electrode71of the controllable semiconductor switch7. At its output, the second driver circuit D2provides a signal S2which depends on the signals S1and S2. For instance, the signals S1, S2and S2may be used to continuously toggle the controllable semiconductor switch between an electrically conductive ON-state and an electrically blocking OFF-state. Such a device may be used, for instance, in inverters, rectifiers or any other power converter.

Optionally, as also illustrated inFIG. 19A, the transformer may include a core4. Alternatively, the transformer may be coreless. Compared with a transformer that includes a magnetic core4, a higher toggle frequency of the semiconductor switch7can be achieved using coreless transformer.

According to still a further example illustrated inFIG. 19B, a transformer that includes first and second coils10,20monolithically integrated with the same semiconductor body3as a controllable semiconductor switch7may be used to galvanically decouple an output signal generated from the controllable semiconductor switch7. Again, first and second coils10,20form a transformer. The first coil10is dielectrically insulated from the second coil20. The first coil10is electrically connected to the controllable semiconductor switch7. An electric current I10through the first coil10can be modulated by the controllable semiconductor switch7. Optionally, a driver circuit D3may be used for modulating the controllable semiconductor switch7. The driver circuit D3may be monolithically integrated with the semiconductor body3or, alternatively, provided in a component separate from the semiconductor body3. At its output, the driver circuit D3provides a signal S3. For example, the signal S3may be used to continuously toggle the controllable semiconductor switch7between an electrically conductive ON-state and an electrically blocking OFF-state.

If a further electronic component is electrically connected to the second coil20, the further electronic component may be controlled by an electric current I20through the second coil20, which electric current I20is caused by the electric current I10through the first coil10. The further electronic component, which is galvanically decoupled from the controllable semiconductor switch7by the transformer, may be monolithically integrated with the semiconductor body3or be provided as a separate device.

Optionally, as also illustrated inFIG. 19B, the transformer may include a core4. Alternatively, the transformer may be coreless.

In principle, instead or in addition to the controllable semiconductor switch7, any other active semiconductor device may also be monolithically integrated in the semiconductor body3together with a coil10, or together with a transformer having coils10and20.

Referring now toFIG. 20, there is schematically illustrated a TEDFET. The structure and the functional principle of a TEDFET may be the same as of the TEDFET described in WO 2007/012490 A2. This document is incorporated by reference in the present application.

The TEDFET ofFIG. 20includes a semiconductor body3and has a drift zone75and drift control zones76. Between each of the drift control zones76and the drift zone75, a thin dielectric layer77is arranged. Further, a ring-shaped edge termination structure78surrounds an active region of the TEDFET. The edge termination structure78may have any conventional structure like field rings, field plates, a VLD-structure (VLD=variation in lateral doping), etc.

The TEDFET is a vertical semiconductor component, that is, the flow direction of the electric current through the drift zone75runs substantially perpendicular to the top and bottom sides31,32. Hence, a magnetic field caused by the electric current occurs in particular in the border area of the active region.

As the strength of the magnetic field is a measure for the strength of the electric current through the drift zone75, detecting of the electromagnetic induction in an integrated sensing coil the axis of which is parallel to the magnetic field vector allows for the determination of the temporally change rate of the electric current. To this, a first coil10as described in the examples above may be used as a sensing coil. InFIG. 20, two of many possible ways and positions for arranging a sensing coil10monolithically in the semiconductor body3are illustrated.

A first possible position for arranging a first (sensing) coil20is inside the edge termination78, for instance between an outermost drift control zone76and the edge termination78. The coil axis15may run parallel to the top and bottom sides31and32.

A second possible position is inside or outside the edge termination78, for instance within an arbitrary one of the drift control zones76. Here, the coil axis15may run parallel to the top and bottom sides31and32, too.

In the previous embodiments, the first coils10and the second coils20were described to have electrically conductive first U-shaped partial windings19. However, the invention may be realized with any other shape. Generally, a partial winding19is only required to have two top ends111,121. In each partial winding19, the distance between the partial winding19and the bottom side32is smaller than the distances between each of its top ends111,121and the bottom side32. Regardless of the shapes of the partial windings19of a coil10,20, the coils10,20may be produced with any of the methods described above and may be used either with or without a magnetic core and in the same applications as described above.

A further embodiment of a first coil10is illustrated inFIG. 21. That embodiment corresponds to the embodiment ofFIG. 1with the sole difference that there is substantially no connection section13. That is, the sections11and12are directly connected to one another at their bottom-most ends. The completed coil10is illustrated inFIG. 22which corresponds toFIG. 2. According to the cross-sectional view ofFIG. 23, the sections11and12may include an angle β. Optionally, each of the sections11and12may be inclined by an angle α to the normal direction n of the bottom side32. The trench35for producing such a coil10may have a triangular cross section. Such a trench35may advantageously be directly achieved by wet etching the semiconductor body3with a suitable etchant, for instance KOH (potassium hydroxide) if the semiconductor body3is based on silicon. In case of a coil10having a triangular cross-section, the angle β may be, for instance, in the range from −120° to +120°. In the case of KOH etching of the 100 planes in Si, the angle α is for example 54.7°.