High density multi-electrode array

A high density micro-electrode array includes a transistor layer including a plurality of access transistors and a substrate in operable communication with the transistor layer including, wherein at least a portion of the substrate includes a plurality of trenches. The system includes a plurality of electrodes at least partially located in the plurality of trenches, wherein each of the plurality of electrodes is connected to at least one of the plurality of access transistors and wherein each of the electrodes is separated by a distance less than approximately one microns.

BACKGROUND

The present invention relates to multi-electrode arrays, and more specifically, to high density multi-electrode arrays.

Multi-electrode arrays are used for various applications including, for example, electrical interfacing to neurons. Multi-electrode arrays have been fabricated by a variety of methods and can be used for both in vivo or in vitro applications. Multi-electrode arrays can be used to stimulate or probe brain activity, to stimulate neurons and study the resulting neuron plasticity or to train live neural networks and use them for computation.

In currently available micro-electrode arrays, the density of the electrodes range from approximately one hundred electrodes per square millimeter in microelectromechanical systems (MEMS) arrays to approximately ten thousand electrodes per square millimeter in micro-fabricated arrays. These electrode densities are achieved using standard CMOS metallization techniques. The density of typical micro-electrode arrays is much smaller than typical neuron density. For example, the neuron density for visual cortex is approximately two hundred million neurons per cubic millimeter.

BRIEF SUMMARY

According to one embodiment of the present disclosure, a high density micro-electrode array includes a transistor layer including a plurality of access transistors and a substrate in operable communication with the transistor layer including, wherein at least a portion of the substrate includes a plurality of trenches. The system includes a plurality of electrodes at least partially located in the plurality of trenches, wherein each of the plurality of electrodes is connected to at least one of the plurality of access transistors and wherein each of the electrodes is separated by a distance less than approximately one microns.

According to another embodiment of the present disclosure, a high density micro-electrode array includes a transistor layer including a plurality of access transistors, wherein one or more of the plurality of access transistors is in operable communication with a stimulation circuit and wherein one or more of the plurality of access transistors is in operable communication with a detection circuit. The high density micro-electrode array includes a buried oxide layer formed on a portion of the transistor layer and a plurality of electrodes formed beneath the transistor layer, wherein each of the plurality of electrodes is connected to at least one of the plurality of access transistors and wherein the electrodes are separated by approximately one micron.

DETAILED DESCRIPTION

It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (i.e., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

With reference now toFIG. 1, a cross section of a high density micro-electrode array100in accordance with an exemplary embodiment of the disclosure is shown. The high density micro-electrode array100includes a plurality of tightly packed electrodes102that are formed inside trenches104in the substrate106. In exemplary embodiments, each electrode102is connected to at least one access transistor in the transistor layer108to enable addressing of each of individual electrodes102.

In exemplary embodiments, the high density micro-electrode array100may be fabricated using a variety of techniques. In one exemplary embodiment, a high density micro-electrode array100is fabricated by starting with a substrate106that contains a heavily doped region110at the top of the substrate. In exemplary embodiments, the heavily doped region may only be few microns in thickness. The fabrication process includes forming trenches104in the heavily doped region110of the substrate106and filling the trenches104with a dielectric liner112and a conductive electrode102. In one exemplary embodiment, the conductive electrode102may be a heavily doped polysilicon, as done for example in trench dynamic random access (DRAM) technology. In another exemplary embodiment, the conductive electrode102may contain a bio-compatible metal such as titanium or platinum. After the trenches104are lined and filled, each electrode102is connected to at least one access transistor (not specifically shown) in the transistor layer108for addressing thereof. In one embodiment, after formation of the electrodes102in the trenches104, an access transistor and periphery circuits for sensing neuron activity and for stimulating are fabricated using standard CMOS processing. The periphery circuit may contain one or more of the following units: electrode addressing control, signal amplification and detection, neuron stimulation generation, timing, interface to outside chips/instrumentations, etc. After the electrodes102are connected to an access transistor in the transistor layer108, the opposite side of the substrate106is thinned, exposing at least a portion of the electrodes102. In exemplary embodiments, only a portion of the substrate106that contains the high density electrode array is thinned.

As then shown inFIG. 2, the substrate106has been thinned to a depth sufficient to expose at least a portion of the dielectric liner112. The process of thinning the substrate106can be done by wafer thinning, grinding, etching, or other commonly known techniques. In exemplary embodiments, the substrate thinning process may include using wet/dry etching with good selectivity between the substrate106and the dielectric liner112. For example, wet etching may be done using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) to remove a portion of the substrate106and leave the dielectric liner112intact. Alternatively, dry etching based on hydrogen bromide (HBr) chemistry can be used which has good selectivity to the dielectric liner112.

Continuing now with reference toFIG. 3, a portion of the dielectric liner112has been etched away from the tip of the electrodes102, exposing the electrodes102. As illustrated inFIG. 4, a dielectric layer120may optionally be used to insulate the remaining heavily doped region110of the substrate. In exemplary embodiments, the dielectric layer120may a polymer such as polymethylmethacrilate (PMMA), a spin-on-glass or another suitable alternative.

Turning now toFIG. 5, another exemplary embodiment of a high density multi-electrode array500is illustrated. The high density multi-electrode array500includes a silicon-on-insulator (SOI) wafer that is used in the transistor layer508above a buried oxide layer (BOX)514. In one exemplary embodiment, as illustrated inFIG. 6a, during the fabrication of the high density multi-electrode array500a portion of the heavily doped region510of the substrate can be etched to a desired depth. Alternatively, as shown inFIG. 6b, the substrate may be etched down to the BOX514.

Referring now toFIG. 7, a circuit diagram of an exemplary addressing scheme for addressing electrodes in a high density multi-electrode array is shown. As illustrated, the electrodes702in the high density multi-electrode array can be addressed using a single access transistor716per electrode in a word line/bit line addressing scheme. The access transistors716connect the electrodes702to circuitry718which may be used to send or receive signals to or from the electrodes702. In other exemplary embodiments, alternative configurations that use one or more transistors for addressing each electrode can be used. For example, in one embodiment two access transistors may be used to activate a single electrode with one access transistor being used for measuring neuron activity and another access transistor being used for stimulating neuron activity. In an alternative embodiment, some electrodes can be used exclusively for probing or measuring neuron activity while others are used exclusively for stimulating neuron activity.

In exemplary embodiments, the high density multi-electrode array may be fabricated such that the high density multi-electrode array encompasses the entire substrate806or such that only a portion of the substrate is used for the high density multi-electrode, as illustrated respectively byFIGS. 8aand8b. In the embodiment shown inFIG. 8b, only the portion of the substrate that contains the high density multi-electrode array is thinned during the fabrication process.

Referring now toFIG. 9, a flow diagram illustrating an exemplary process for fabricating a high density micro-electrode array is illustrated. The first step in the exemplary fabrication process, as shown at process step902, is providing a substrate that optionally contains a heavily doped region. After the substrate has been provided, the next step in the exemplary fabrication process is forming trenches in the substrate, as shown at process step904. Once the trenches have been formed, they are filled with a dielectric liner and then a conductive electrode, as shown is process steps906and908respectively. The next step in the exemplary fabrication process, as illustrated at process step910, is forming a transistor layer on top of the substrate and connecting each electrode to at least one access transistor. After the electrodes are connected to access transistors, the substrate is thinned to expose at least a portion of each of the electrodes, as shown at process step912.

In exemplary embodiments, the process for fabricating a high density micro-electrode array may include an additional step of adding a dielectric layer to insulate the remaining portion of the substrate that surrounds the electrodes. The flow diagram depicting the process for fabricating a high density micro-electrode array is provided as just one exemplary fabrication process that can be used. There may be many variations to the fabrication process or the process steps described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

Turning now toFIG. 10, a micro-needle1000suitable for in vivo applications that includes an exemplary embodiment of a high density micro-electrode array is illustrated. The micro needle1000includes layers of wafer each containing a high density micro-electrode array1100and periphery circuit1018. The layers of wafer that make up the micro-needle1000are cut so that the dimensions and shape are suitable for in vivo applications. Typical micro-needles have a width and thickness of 20-50 μm and length of 100-1000 μm and contain about 103micro-electrodes on its side. In certain applications the micro-needles can be arranged in a one-dimensional or two-dimensional array as known in the art.

In exemplary embodiments a high density micro-electrode array in accordance with the present disclosure may have an electrode density of greater than approximately one hundred thousand electrodes per square millimeter. In other exemplary embodiments a high density micro-electrode array in accordance with the present invention may have an electrode density of greater than approximately one million electrodes per square millimeter. In exemplary embodiments, the electrodes in the high density micro-electrode are formed such that the distance separating the electrodes can range from approximately two hundred nanometers (nm) to approximately two microns (μm).