Solid-state impedance matching systems including a hybrid tuning network with a switchable coarse tuning network and a varactor fine tuning network

An eVC including coarse and fine tuning networks. The coarse tuning network includes a circuit: receiving a RF input signal from a RF generator; outputting a RF output signal to a reference terminal or load; and receiving a DC bias voltage. The circuit is switched between first and second states. A capacitance of the circuit is based on the DC bias voltage while in the first state and is not based on the DC bias voltage while in the second state. The fine tuning network is connected in parallel with the coarse tuning network and includes a varactor. The varactor includes: a first diode receiving the RF input signal; and a second diode connected in a back-to-back configuration with the first diode and outputting a RF output signal to the reference terminal or load. A capacitance of the varactor is based on a second received DC bias voltage.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is related to U.S. Pat. No. 8,576,013 issued on Nov. 5, 2013 and titled “POWER DISTORTION-BASED SERVO CONTROL SYSTEMS FOR FREQUENCY TUNING RF POWER SOURCES” and U.S. Pat. No. 8,781,415 issued on Jul. 15, 2014 and titled “DISTORTION CORRECTION BASED FEEDFORWARD CONTROL SYSTEMS AND METHODS FOR RADIO FREQUENCY POWER SOURCES”. The entire disclosures of these U.S. patents are incorporated herein by reference.

FIELD

The present disclosure generally relates to impedance matching networks.

BACKGROUND

Plasma etching is frequently used in semiconductor fabrication. In plasma etching, ions are accelerated by an electric field to etch exposed surfaces on a substrate. The electric field is generated based on RF power signals generated by a radio frequency (RF) generator of a RF power system. The RF power signals generated by the RF generator must be precisely controlled to effectively execute plasma etching.

A RF power system may include a RF generator, a matching network and a load (e.g., a plasma chamber). The RF generator generates RF power signals, which are received at the matching network. The matching network matches an input impedance of the matching network to a characteristic impedance of a transmission line between the RF generator and the matching network. This impedance matching aids in maximizing an amount of power forwarded to the matching network (“forward power”) and minimizing an amount of power reflected back from the matching network to the RF generator (“reverse power”). Forward power may be maximized and reverse power may be minimized when the input impedance of the matching network matches the characteristic impedance of the transmission line.

An RF matching network may include a load capacitance and a tune capacitance. The load capacitance is connected in parallel with a load (e.g., plasma chamber) and the tune capacitance is connected in series between an RF input and the load. The load capacitance and/or the tune capacitance may include a switching network. The switching network typically includes field effect transistors (FETs) and/or p-type intrinsic n-type (PIN) diodes. A PIN diode has a binary state (i.e. either ON or OFF).

A switching network including FETs and/or PIN diodes is complex due to the number of diodes required. PIN diodes are susceptible to breakdown and are relatively expensive. Switching of the PIN diodes to vary the overall capacitance of a load capacitance or a tune capacitance is performed in a discontinuous fashion. Switching of PIN diodes can cause discontinuous jumps in a resonant frequency and impedance of a matching network, which can be seen by a RF source providing an RF signal to an input of the matching network. In addition, switching of the PIN diodes can cause off resonance operation of the RF source while the resonant frequency is re-established by a feedback control loop. Off-resonance operation can cause significant stress on the FETs. To reduce the stated problems requires, for example, the FETs have an associated capacitor and driving circuit.

Various challenges exist with switching PIN diodes. A capacitance associated with a PIN diode is switched into a circuit by applying a bias voltage across the PIN diode.FIG. 1shows an example schematic diagram of a traditional dual-pin diode circuit10of an impedance matching circuit. The dual-PIN diode circuit10includes PIN diodes14,16and corresponding capacitors Cn1, Cn2. The PIN diodes14,16are connected in series respectively with the capacitors Cn1, Cn2between an RF input terminal18and an RF output terminal20. The PIN diodes14,16receive respectively bias voltages VSWT1, VSWT2.

When one or more of the PIN diodes14,16are forward biased, the dual-PIN diode circuit10is in conduction mode and current is permitted to flow between the terminals18,20. As a result, the capacitors Cn1, Cn2are applied to the impedance matching circuit. Conversely, when the PIN diodes are reverse biased, current flow is prevented and in this open-circuit condition, the capacitors Cn1, Cn2are removed from the impedance matching circuit. As an alternative to using PIN diodes, FET switches can be used. In a FET switch implementation, each individual diode performs as a binary switch having an ON (or conduction) state and an OFF (or open) state. An impedance matching network may include a network of PIN diodes to switch a set of capacitors to cover a capacitance range necessary to cover an impedance space associated with a process range of a reactor (or plasma chamber).

Tuning Resolution

A significant disadvantage of using PIN diodes to switch in capacitors is tuning resolution. Several PIN diodes and associated capacitors are necessary to provide a suitable capacitance range to cover a predetermined impedance tune space. A design requirement may be to have enough diode and capacitor combinations for the capacitance range to achieve a suitable resolution when sequencing between each diode and capacitor pair. Referring again toFIG. 1, when VSWT1is forward biased and VSWT2is reverse biased, only the capacitance Cn1is connected. If VSWT2is changed from being reverse biased to being forward biased, the combination of Cn1, Cn2are connected. In this case, the difference between Cn1and Cn2is the effective resolution of the circuit. To achieve a lower resolution, more PIN diodes/FETs and corresponding capacitors must be integrated into the impedance matching circuit.

PIN diodes and FETs allow for fast switching between changes in capacitance. PIN diodes and FETs can be switched at a faster rate than a conventional impedance matching circuits having electromechanical variable capacitors. Capacitances of electromechanical variable capacitors are changed via stepper motors, which incrementally change the capacitances in a linear manner. Capacitance changes with PIN diodes and FETs allow for capacitance ranges (or multiple incremental capacitance steps) to be skipped, whereas electromechanical variable capacitors need to incrementally switch through a series of capacitances to arrive at a desired capacitance. For a conventional impedance matching circuit including electromechanical variable capacitors, an example resolution is less than 0.2 pico-farads (pF) per adjacent (or stepped) capacitance switching transitions.

FIGS. 2A and 2Bshow differences in impedance tuning spaces for two arrays of PIN diode switches, which convey a practical tuning limitation using PIN diode switches.FIG. 2Ashows a Smith chart of an impedance tuning space for a bias matching network having a first array of PIN diodes.FIG. 2Bshows a Smith chart of another impedance tuning space for a bias matching network having a second array of PIN diodes. ForFIG. 2A, a load capacitor C1and a tune capacitor C2of an impedance matching circuit include respective sets of diode and capacitor combinations, where each of the sets includes 24 diode and capacitor combinations to provide 24×24 arrays. Due to different predetermined capacitance ranges for C1and C2, the effective resolutions of C1and C2may be respectively 24 pF per adjacent capacitance switching transition and 56 pF per adjacent capacitance switching transition. In view of the Smith chart ofFIG. 2A, large sparse regions can be seen between changes in capacitances for the makeup of this 24×24 array. C2has a larger resolution than C1. To improve the resolution of C2, the array associated with C2may be scaled from 24 diode switches to 96 diodes switches. The revised impedance tuning space is shown in the Smith Chart ofFIG. 2B. With the increased number of diodes, the resolution is reduced to 14 pF per adjacent capacitance switching transition. Although a reduction in resolution is provided, this is not sufficient to satisfy certain reflected power requirements. A consequence of poor capacitor resolution is lower impedance tuning performance, and an industry standard to meet 0.25% of reflected power remains a challenge with the use of PIN diode/switches.

Voltage and current stress limitations are associated with a PIN diode circuit (e.g., the dual-PIN diode circuit ofFIG. 1) having PIN diodes in series with capacitors. The number of capacitors can be increased for current sharing, which results in more capacitors per PIN diode/switch. To manage the voltage stress, PIN diodes with higher voltage ratings can be used and have increased cost. Also, for the load capacitor C1, with 24 diode switch positions and properly shared current, 92 capacitors are required. For the tune capacitor C2, with 96 diode switch positions and properly shared current, 960 capacitors are required. Thus, there is substantial number of components and associated cost with using PIN diode circuits. In addition, PIN diode circuits are limited in ability to meet targeted tuning impedance performance.

SUMMARY

An electronic variable capacitance is provided including a coarse tuning network and a fine tuning network. The coarse tuning network includes a switchable circuit configured to (i) receive a RF input signal from a RF generator of a plasma processing system, (ii) output a first RF output signal to a reference terminal or to a load, and (iii) receive a first direct current (DC) bias voltage. The switchable circuit is configured to be switched between a first state and a second state. A capacitance of the switchable circuit is based on the first DC bias voltage while in the first state and is not based on the first DC bias voltage while in the second state. The fine tuning network is connected in parallel with the coarse tuning network, the fine tuning network comprises a back-to-back diode varactor. The back-to-back diode varactor is configured to receive a second DC bias voltage. The back-to-back diode varactor includes a first diode configured to receive the RF input signal, and a second diode connected in a back-to-back configuration with the first diode and configured to output a second RF output signal to the reference terminal or to the load. A capacitance of the back-to-back diode varactor is based on the second DC bias voltage.

In other features, a method of operating an electronic variable capacitance is provided, wherein the first electronic variable capacitance includes a hybrid tuning network including a coarse tuning network and a fine tuning network. The fine tuning network is connected in parallel with the coarse tuning network. The method includes: receiving a first RF input signal from a RF generator of a plasma processing system at a switchable circuit of the coarse tuning network. The switchable circuit is configured to be switched between a first state and a second state. The method further includes: outputting a first RF output signal from the switchable circuit to a reference terminal or to a load; receiving a first DC bias voltage at the switchable circuit, where a capacitance of the switchable circuit is based on the first DC bias voltage while in the first state and is not based on the first DC bias voltage while in the second state; and receiving a second DC bias voltage at a back-to-back diode varactor of the fine tuning network. The method further includes: receiving the first RF input signal at a first diode of the back-to-back diode varactor; and outputting a second RF output signal from a second diode to the reference terminal or to the load, where the second diode is connected in a back-to-back configuration with the first diode, and where a capacitance of the back-to-back diode varactor is based on the second DC bias voltage.

In other features, a method is provided and includes: determining a distortion quantity, wherein the distortion quantity is an indication of an amount of reflected power provided from a RF generator to a plasma processing chamber; and based on the distortion quantity, determining a gain value for an electronic variable capacitance, wherein the electronic variable capacitance is a shunt capacitance or a series capacitance of an impedance matching network connected between the RF generator and the plasma processing chamber. The electronic variable capacitance comprises a switchable circuit and a varactor. The varactor is connected in parallel with the switchable circuit. The method further includes, during a direct convergence mode: adjusting a first DC bias voltage from an initial DC bias voltage directly to a first target voltage; and supplying the first target voltage to the switchable circuit or the varactor.

In other features, a controller is provided that includes an adjustment module, a control circuit, and a bias circuit. The adjustment module is configured to determine a distortion quantity corresponding to a transfer of RF power from a RF generator to an impedance matching network of a plasma processing system. The control circuit is configured to (i) generate a control signal based on the distortion quantity, and (ii) output the control signal to a driver circuit to provide a first DC bias voltage to and set a capacitance of a switchable circuit of a hybrid tuning network in the impedance matching network. The bias circuit is configured to (i) generate a second DC bias voltage based on the distortion quantity, and (ii) output the second DC bias voltage to a varactor of the hybrid tuning network. The adjustment module is configured to: receive a first feedback signal based on a condition of the switchable circuit; receive a second feedback signal based on a condition of the varactor; adjust the control signal based on the first feedback signal; and adjust the second DC bias voltage based on the second feedback signal.

DESCRIPTION

In the following description, numerical designators may be used to refer to the same circuit element, component, module, etc. in different figures. For example, the numerical designator ‘150’ ofFIG. 6refers to the same impedance matching network ‘150’ ofFIG. 5. Also, in the following description, alpha-numeric designators may not be used to refer to the same circuit elements in different figures. For example, an alpha-numeric designator ‘C1’ inFIG. 8Arefers to a different capacitor than the alpha-numeric designator ‘C1’ inFIG. 12.

FIG. 3shows a FET switched capacitance circuit50that includes a first field effect transistor FET1, a second field effect transistor FET2, capacitors CA, CB, and inductors L1-L5. The FET switched capacitance circuit50may be included as part of a load capacitor or a tune capacitor of an impedance matching network. A drain terminal of FET1is connected to (i) an RF input terminal52via CA, and (ii) L3. Source terminals of FET1, FET2are connected to each other. A gate terminal of FET1is connected to L1, which receives a direct current (DC) control voltage VDCfrom a voltage source54. The source terminals of FET1, FET2are connected to L4, which is connected to a reference terminal (or ground)56. The voltage source54is connected to the reference terminal56. A gate terminal of FET2is connected to L2, which receives the DC control voltage VDCfrom the voltage source54. A drain terminal of FET2is connected to L5. L3and L5are connected to a bias terminal58, which receives a DC bias voltage VBIAS. The drain terminal of FET2is also connected to an RF output terminal60via CB.

The DC bias voltage VBIASis applied across each of FET1, FET2from the drains to the sources of FET1, FET2. Depending on the DC control voltage VDCand the ON/OFF states of FET1, FET2, the DC bias voltage VBIAScorresponds to one of two voltage levels. When the gates are driven OFF, the DC bias voltage VBIASis high. As an example, the DC bias voltage VBIASmay be within a predetermined range of 600 VDC. This provides the benefit of a lower capacitance value associated with an OFF FET. When the FET pair (or FET1and FET2) are conducting (referred to as ‘conducting mode’), the DC bias voltage VBIASis driven toward 0 VDC. The capacitors CA, CBare connected between terminals52,60independent of whether FET1, FET2are ON. The capacitance, when FET1, FET2are ON, is provided by the capacitances of CA, CB. The capacitance, when FET1, FET2are OFF, is provided by the capacitances CA, CBand capacitances of FET1, FET2, which are connected in series. The capacitances of FET1, FET2are collectively referred to as output source-to-substrate capacitance COSS, which is based on the DC bias voltage VBIAS. The DC bias voltage VBIASis greater than 0 VDC.

To provide a range of possible capacitances for the load capacitance or the tune capacitance of an impedance matching network, a switchable tuning network can be provided including multiple versions of the FET switched capacitance circuit50. The FET switched capacitance circuit50is constructed for a parallel combination of FET pairs. The RF input and RF output terminals of the versions may be connected, such that the FET pairs and corresponding capacitances CA, CBare connected in parallel. Each of the FET pairs receives a respective DC bias voltage. InFIG. 3, FET1, FET2are referred to as a FET pair. A switchable tuning network may include multiple versions of the FET switched capacitance circuit including FET pairs and corresponding capacitors CA, CB. Each of the FET switched capacitance circuits provides a predetermined and respective capacitance range. Below Table 1 provides examples of measured capacitances for each of five FET switched capacitance circuits.

TABLE 1Examples of Capacitance Values of FET Pairsof a FET switched capacitance circuit.Off State Capacitance (pF)ON state Capacitance (pF)FET PairAcross RF TerminalsAcross RF Terminals1102.9672.2281.5572.0370.4260.7468.4141.5542.767.6

FIG. 4shows a plot of total capacitance values and capacitance differences for the switchable tuning network associated with Table 1. The switchable tuning network was switched through a sequence of FET pair ON/OFF states. The sequence yielded the ascending range of total capacitance values ofFIG. 4. The second y-axis shows a difference in capacitance for each sequential change in capacitance. In sequential change in capacitance is associated with changing one or more states of one or more switches in the switchable tuning network. Although the plot shows four noticeable peaks in the capacitance difference, on average, the capacitance difference is less than 50 pF. By adjusting capacitors CA, CB, the peaks can be reduced. This is because each of the peaks is associated with one particular FET switch pair. The peaks may not be able to be fully reduced. This is because the capacitor differences may be more than can be accounted for by varying one or more bias voltages provided to the FET pairs. As a result, the FET switched capacitance circuits have an inherent resolution limitation. To further reduce the peaks and to provide fine tuning, one or more varactor circuits may be connected in parallel to the switchable tuning network. This is further shown and described below. An example of a hybrid tuning network including a switchable tuning network connected in parallel with one or more varactors is shown inFIG. 12.

Hybrid tuning networks are disclosed herein and may include solid-state variable capacitors, where each of the solid-state variable capacitors includes a network of FET switches connected in parallel with one or more varactors. Each of the varactors includes a network of diodes that are biased to vary a net capacitance of the hybrid tuning networks. The network of FET switches provides coarse tuning capability. The varactors provide fine tuning capability. The coarse and fine tuning capabilities provide improved tuning operation relative to prior art implementations. Additional features include improved switching rates at increased bias voltages to achieve a wide capacitance range and resolution. Also, to reduce voltage stress, the solid-state variable capacitors may be coupled to an air-core transformer. An example of this is shown inFIG. 18. The combination of the solid-state variable capacitors and the air-core transformer enables a complete electronic controlled match of an impedance matching network. In addition, the impedance matching network and/or portions thereof may be packaging in a sealed enclosure, which prevents an air exchange that can degrade the impedance matching network and/or environment. The environment may refer to an area within a facility where air cleanliness is of high-importance for high-volume manufacturing.

FIG. 5shows a RF power system100that includes a RF generator102, a matching network104(referred to also herein as an “impedance matching network”), and a load106of the matching network104. The RF generator102generates a RF power signal107, which is provided to the matching network104. The matching network104matches an input impedance of the matching network104to a characteristic impedance of a transmission line108between the RF generator102and the matching network104. Put another way, the matching network104matches an impedance of the load106to an impedance as seen by the output of the RF generator102. The matching network104and the load106may be considered as the load on the RF generator102. The load106may be, for example, a plasma chamber or other RF load. The impedance of the load106may be static (i.e. unchanging over time) or dynamic (i.e. changing over time).

The RF generator102includes a RF power source120(or a power amplifier) and a feedback loop122. The power amplifier120generates the RF power signal107, which is outputted to the matching network104. The power amplifier120may generate the RF power signal107based on a power signal received from a power source124external to the power amplifier120. Although the power source124is shown as part of the RF generator102, the power source124may be external to the RF generator102. The power source124may be, for example, a direct current (DC) power source.

The feedback loop122includes one or more sensors (first sensors)126, a scaling module128, a first summer130, and a power control module132. The sensors126may include voltage, current and/or directional coupler sensors. The sensors126may detect (i) voltage V and current I output of the power amplifier120, and/or (ii) forward (or source) power PFWDout of the power amplifier120and/or RF generator102and reverse (or reflected) power PREVreceived from the matching network104. The voltage V, current I, forward power PFWD, and reverse power PREVmay be scaled and/or filtered versions of the actual voltage, current, forward power and reverse power of the output of the power amplifier120. The sensors126may be analog and/or digital sensors. In a digital implementation, the sensors126may include analog-to-digital (A/D) converters and signal sampling components with corresponding sampling rates.

The sensors126generate sensor signals133, which are received by the scaling module128. The scaling module128scales the sensor signals133and generates a power feedback signal134. The power feedback signal134is generated based on the sensor signals133and a scaling matrix. The power feedback signal134may represent the forward power for forward power leveling deliver power. The power feedback signal134may represent the RF power transferred to the matching network104or load power Pdand can be represented by equation 1, where V is voltage output of the power amplifier120and/or RF generator102, I is current out of the power amplifier120and/or RF generator102, and Θ is a phase difference between the voltage and the current outputs V, I of the power amplifier120.
Pd=|V∥I|cos(Θ)=PFWD−PREV(1)

The first summer130sums the power feedback signal134with a predetermined power setpoint signal136, which may be generated by a power setpoint module138. The power feedback signal134may be subtracted from the predetermined power setpoint signal136to generate an error signal efb.

The power control module132receives the error signal efband generates a power control signal upfbto regulate power out of the power amplifier120. The power control signal upfbis provided to the power amplifier120. The power amplifier120adjusts the RF power signal107based on the power control signal upfb. The RF power signal107may be a continuous waveform or a pulsed waveform. The servo control described herein allows for the RF power signal107to be pulsed due to the update rate associated with the servo control. The power control module132may include a proportional integral derivative (PID) controller and/or a direct digital synthesis (DDS) component(s). In one implementation, the power control module132is a first PID controller with a function identified as Dpfb(z). The power control signal upfbmay be a drive signal and have a DC offset or rail voltage, a frequency and a phase. However, the power control signal upfbdoes not adjust frequency of the RF power signal107.

The RF generator102may further include a first feedforward loop140and a second feedforward loop142. The first feedforward loop140includes a first distortion module144and a first correction circuit146. The first distortion module44determines a distortion value dtrepresentative of the distortion as seen at the output of the power amplifier120and/or RF generator102. The distortion values described herein may be used during the hybrid tuning control method ofFIG. 21. The first distortion value dtis generated based on the sensor signals133and a distortion function. The distortion function is described in more detail below. The first correction circuit146generates a first power tuning value (or first impedance tuning value) utffbased on the first distortion value dt. The tuning value utffis provided to the matching network104for frequency response tuning and impedance adjusting purposes. The first distortion module144may determine the first distortion value dtbased on a sinusoidal function and/or a cross-correlation function.

Multiple techniques are disclosed herein that include maximizing optimal power transfer in an RF power system with a dynamic load (i.e. a load having varying impedance(s)). A first technique, which is described with respect toFIG. 5includes the RF power source124connected to the matching network104. The matching network104may include an impedance matching network150with one or more variable tuning elements152(e.g., variable capacitors). Each of the variable tuning elements may include a hybrid tuning network153. The variable tuning elements152may be in a ‘L’-configuration (one capacitance in parallel with the RF generator102and one capacitance in series with the load106) or in other configurations as shown below inFIGS. 14 and 17.

The variable tuning elements152are used for adjusting tune and load parameters of the matching network104, and may have respectively an associated tune input154and load input156. The tune and load parameters refer to impedance adjustments perforated in the matching network104via the variable tuning elements152. As an example, the tune parameter and the load parameter may be associated with respective capacitances of capacitors in the matching network104.

A second technique, which is described with respect toFIG. 6, introduces a variable frequency adjustment to the power amplifier120and may be used alternatively or in combination with the first technique. The tune and load parameters may each be fixed, discretely selectable, and/or adjustable when using the second technique.

In both the first and second techniques, the RF power transferred Pdfrom the power amplifier120to the matching network104is maximized. This may occur when the forward power PFWDto the matching network104is maximized and/or the reverse power PREVfrom the matching network is minimized. The first distortion value dtis determined via the first distortion module144using vector calculus without determining the phase Θ. The first distortion value dtmay be equal to and/or be represented by a sinusoidal function.

The techniques disclosed herein enable autonomous servo of an agile frequency RF power source (power amplifier120) for maximized power transfer. Although servo control includes feedback and feedforward control, the feedforward control provided herein aids in quickly maximizing the power transferred to the matching network104. These techniques include determining distortion of a RF power system (RF power system110) and providing feedforward correction using vector calculus. The distortion refers to the reflected power due to the reactive change in load impedance, which is directly related to the sinusoidal function of the phase Θ. As an alternative to and/or in addition to using a sinusoidal function, a cross-correlation function may be used to determine the first distortion value dt. The first distortion module144may determine the first distortion value dt.

Referring again toFIG. 5, in one implementation, the first correction circuit146includes a first input module160, a second summer162and a tune control module164(or Dtff(z)). The first input module160may generate a first predetermined value (e.g., 0 when determining the distortion value dtaccording to the sine function or 1 when determining the distortion value dtaccording to the cosine function). The second summer162may subtract the first distortion value dtfrom the first predetermined value to generate a tuning or first correction value ct. The time control module164may include a second PID controller and generate a power tuning value (or first impedance tuning value) utffbased on the first correction value ct. The tune control module64may adjust the power tuning value utffto match the first distortion value dtwith the first predetermined value. The tune control module164may generate and/or receive the first predetermined value.

The second feedforward loop142may include a second distortion module170and a second correction circuit172. The second distortion module170determines a ratio of magnitudes (or second distortion value) dlbased on the sensor signals133and a second distortion function. The first and second distortion values dt, dleach provide an indication of distortion and/or associated parameters, as measured by the sensors33.

The second correction circuit172may include a load setpoint module176, a third summer178and a load control module180, which may be represented as a function Dlff(z). The load setpoint module176may generate a predetermined load setpoint value (e.g., 50 Ohms (Ω)). The third summer178may subtract the second distortion value dlfrom the load setpoint value to generate a load correction value (second correction value) cl.

The load control module180may include a third PID controller and may generate a power load value (or second impedance tuning value) ulffbased on the second correction value cl. The load control module180may adjust the power load value ulffto match the second distortion value dlto the load setpoint value. The load control module180may generate and/or receive the load setpoint value.

The tune control module164and the load control module180are coupled, as represented by arrow182. The arrow182represents a mutual coupling between the tune and the load inputs154,156of the matching network104. The power load value ulffis affected (or indirectly adjusted) when the power tune value utffis directly adjusted by the tune control module164. Similarly, the power tune value utffis affected (or indirectly adjusted) when the power load value ulffis directly adjusted by the load control module180. The tune and load inputs154,156are adjusted respectively by the power tune value utffand the power load value ulff.

The matching network104may also include second sensors190. The second sensors190may include phase and magnitude sensors, which are used by the impedance matching network150to adjust the tune and load inputs154,156. The impedance matching network150may adjust the tune and load inputs154,156such that the load106and the matching network104have an impedance as seen by the power amplifier120and/or the RF generator102matching the impedance of the transmission line108. The tune and load inputs154,156may be adjusted until phase of the RF power signal107is 0 and impedance of the matching network104is at a predetermined impedance (e.g., 50Ω). This aids in minimizing the reverse power PREV, which maximizes power transferred to the matching network104. The second sensors190may be electrically coupled to the transmission line108and used to detect the distortion (or PREV) of the RF power system100. The tune and load adjustments performed by the impedance matching network150based on the outputs of the second sensors190do not need to fully maximize the power transferred, as the feedforward loops140,142further aid in maximizing the power transferred.

The second sensors190may be located at an input of the matching network104, not at an output of the matching network104to quantify the distortion of the RF power system10as a function of the reverse power PREV. The matching network104may apply a feedforward match correction umffto correct an impedance mismatch between the matching network104and the transmission line108. Collective power transfer contributions by the power control module132and the matching network104(and/or controller of the matching network104) to power delivery may be analytically represented as a sum of the correction values provided by these controllers. This sum is provided by equation 2, where u is the total distortion correction.
u=upfb+umff(2)

The tune and load control modules164,180provide the distortion corrections values utffand ulff, which are provided to the tune and load inputs154,156. The match correction value umffmay be expressed as a sum of these correction values, as represented by equation 3.
umff=utff+ulff(3)

Without the distortion correction of the matching network104, there can be a loss in the RF power system100if feedback control is used without feedforward control. The second sensors190may be coupled to the transmission line108to measure the reverse power PREV. The matching network104may not correct all of the distortion, as other feedforward control is provided via the feedforward loops140,142. The matching network104may adjust the tune and load inputs154,156based on the reverse power PREV. The distortion correction as performed by the matching network104may be limited and may not reduce the reverse power PREVto 0 due to model imperfections and/or a measurement error. The feedforward correction provided by the feedforward loops140,142may further correct the distortion and reduce the reverse power PREVto 0.

FIG. 6shows a RF power system200that includes a RF generator202, the matching network104with the impedance matching network150and the second sensors190, and the load106. The RF generator202generates a RF power signal204, which is provided to the impedance matching network150. The RF generator202includes a RF power source (or a power amplifier)206and the feedback loop122. The power amplifier206generates the RF power signal204, which is an output to the matching network104. The power amplifier206may generate the RF power signal204based on (i) a power signal received from the power source124external to the power amplifier206, and/or (ii) a frequency tuning value ufff. The power source124may be, for example, a direct current (DC) power source.

The feedback loop122includes the sensors126, the scaling module128, the first summer130, and the power control module132. The sensors126generate the sensor signals133, which are received by the scaling module128. The scaling module128scales the sensor signals133and generates the power feedback signal134. The power feedback signal134is generated based on the sensor signals133and the scaling matrix. The first summer130sums the power feedback signal134with the predetermined power setpoint signal136, which may be generated by the power setpoint module138. The power feedback signal134may be subtracted from the predetermined power setpoint signal136to generate the error signal efb.

The power control module132receives the error signal efband generates the power control signal upfbto regulate power out of the power amplifier206. The power amplifier206adjusts the RF power signal204based on the power control signal upfband the frequency tuning value ufff. The RF power signal204may be a pulsed waveform and have a frequency set based on the frequency tuning value ufff.

The RF generator102may further include the first feedforward loop140, the second feedforward loop142, and a third feedforward loop210. The RF power system100may include the third feedforward loop210and not the first and second feedforward loops140,142or may include the first, second and third feedforward loops140,142,210, as shown. The first feedforward loop140includes the first distortion module144and the first correction circuit146with the first input module160, the second summer162and the tune control module164. The second feedforward loop142may include the second distortion module170and the second correction circuit172with the load setpoint module176, the third summer178and the load control module180.

Although the third feedforward loop210is drawn as a feedback loop, the third feedforward loop210performs as a feedforward loop and performs a feedforward function and is thus referred to herein as a feedforward loop. The third feedforward loop210provides the frequency tuning value ufff, which is used to adjust frequency of the RF power signal204. By adjusting the frequency of the RF power signal204, frequency responses of the matching network104changes, which alters impedances in the matching network104. These impedance changes affect impedance matching between the matching network104and the transmission line108, which affects the amount of reverse power PREVand the amount of power transferred Pd.

The third feedforward loop210includes the first distortion module44and a third correction circuit212. The third correction circuit212includes a second input module214, a fourth summer216and a frequency control module218, which may be represented as a function Dfff(z). The second input module214generates a third predetermined value (e.g., 1). The fourth summer216may subtract the distortion tuning value dtfrom the third predetermined value to generate a third correction value cf. The frequency control module218may include a fourth PID controller and generate the frequency tuning value ufffbased on the third correction value cf. The frequency control module218may adjust the frequency tuning value ufffto match the first distortion value dtto the third predetermined value. The frequency control module218may generate and/or receive the third predetermined value.

FIG. 7shows a generalized model of a plasma system300. The plasma system300includes a RF power supply302, a matching network304, and a plasma chamber306. The RF power supply302generates a sinusoidal output signal to plasma chamber306via transmission line308having a resistance RT330and matching network304. Circuit components of the matching network304may be included in the matching network104ofFIGS. 5-6. The matching network304is modeled as a tunable load capacitor CLOAD312shorted to ground, a tunable series capacitor CTUNE314in series with transmission line308and output inductance LO316. The capacitors312,314may be replaced with other variable tuning elements, circuits and/or networks. Current flowing into matching network304is shown as il(t), voltage circulating through matching network304is indicated as vl(t), and the impedance of matching network304is shown as Zl. The plasma chamber306is modeled as a real resistive load RP320in series with a reactive element, parasitic capacitance CP322. The series combination of resistive load RP320and parasitic capacitance CP322is placed in parallel with reactive stray capacitance CSTRAY326. Current flowing into plasma chamber306is shown as iP(t), voltage circulating through plasma chamber306is indicated as vP(t), and the impedance of plasma chamber306is shown as Zp.

The capacitors312,314may each be replaced with, implemented as, and/or include any of the hybrid tuning networks disclosed herein. The capacitances are referred to as electronic variable capacitors (eVCs) because capacitances of the capacitors312,314are electronically controlled. Examples of the hybrid tuning networks are disclosed below. Each of the hybrid tuning networks may be used for both coarse tuning and fine tuning. The coarse and fine tuning may be controlled by the diagnostic control module350, the actuator control module/devices362, the tune control module164ofFIGS. 5-6and/or the load control module180ofFIGS. 5-6. The tuning may be performed based on one or more of the herein described distortion signals dt, dl, dtas further described below.

For remote impedance tuning operation, a communication link351between the RF power supply and impedance matching device is provided to communicate desired variability of configurable reactive elements. As an example, the communication link351may be connected between the circuits146,172and the matching network104and include distortion correction (or actuator command) signals utff, ulff. The communication link may be an analog or digital communication link.

Example circuits and modules controlling impedance tuning are the circuits146,172and the modules144,160,164,170,176,180, which may control impedance tuning based on the distortion quantities disclosed herein. Through a remote impedance controlling interface (e.g., the display197) device details and performance statistics may be reported.

The feedforward impedance tuning described herein may use the notion of a numerically complex quantity of distortion, d=dr+jdi. The corresponding actuators are varied until the min(d)=min(dr)=min(di). The update to the impedance tuning actuators are governed by conventional proportional-plus-integral-plus-derivative controllers (PID). The gains for the PID controllers are selected to suitably tune the load impedance of the impedance tuning device without significant overshoot (underdamped) or substantially overdamped performance. Therefore, the gain is chosen for

G≈∂x∂d
for a particular range corresponding to the change of the actuator command signal, x, to the change in the distortion.

FIG. 8Ais a schematic of a back-to-back diode varactor400that includes a pair of diodes D1, D2, inductors L1, L2and capacitor C1. The diodes D1, D2and inductors L1, L2are connected in series between a DC bias voltage terminal402and a reference terminal (or ground)404. Anodes of the diodes D1, D2are connected to each other. An RF input signal is received at a terminal406between the diode D2and the inductor L2. The capacitor C1is a bypass capacitor that permits passage of RF power and is connected (i) at a first end to the inductor L1and a cathode of the diode D1, and (ii) at a second end to an RF output terminal or ground terminal408. The inductors L1, L2may be referred to as RF chokes because the inductors L1, L2prevent passage of RF power.

The back-to-back diode varactor400ofFIG. 8Amay be connected in parallel with the FET switched capacitance circuit50ofFIG. 3. This combination provides an example of a hybrid tuning network that can be used for both coarse tuning and fine tuning. The FET switched capacitance circuit may be used for coarse tuning and the back-to-back diode varactor400may be used for fine tuning.

The back-to-back diode varactor400is supplied the DC bias voltage VBIASat the terminal402, which is used to set a capacitance of the back-to-back diode varactor400between the RF input terminal406and the RF output or ground terminal408. This is different than providing a DC bias voltage at a center tap (or anodes) of the diodes D1, D2, where an equal amount of voltage is applied to each of the diodes D1, D2. Upon applying a non-zero positive DC bias voltage VBIAS, anode-cathode voltages across each of the diodes D1, D2reach a charge equilibrium condition. As a result, diode D1is reverse-biased and diode D2is slightly forward biased. The forward bias is less than a built-in potential of the diode D2, since reverse-biased diode D1prevents DC current flow.

The capacitance of a p-type/n-type (PN) junction can be expressed as provided by equation 4, where ϕ is the built-in potential of the diode, VBIASis the applied DC bias voltage, n is a power law exponent of a diode capacitance, and K is the capacitance constant.

The power law exponent n is dependent upon the fabrication technique used to manufacture the corresponding diode. For example, a uniformly doped junction has a power law exponent n of 0.5. Example values of the built-in potential ϕ are 0.5-01.6V. The capacitance constant K is also known as a zero bias junction capacitance and depends upon diode construction and device area. The capacitance relationship of expression 4 results in a sharply nonlinear capacitance-voltage curve with highest capacitance at a smallest (magnitude) DC bias voltage (examples of this are shown inFIGS. 9A, 9B).

For the back-to-back diode varactor400, three examples are provided for corresponding DC bias voltages. For the first example, the DC bias voltage is 0V and diodes D1, D2have capacitance approximately equal to K. This results in a composite capacitance of the diodes D1, D2in series being K/2. For the second example, the DC bias voltage is 10V, the diode D2is forward biased slightly less than ϕ, capacitance of the diodes D2is equal to K, and the diode D1is reverse biased by 10-ϕ and has a lower capacitance than D2. As a result, the composite capacitance of the diodes D1, D2is a series combination of the capacitances of diodes D1, D2. For the third example, the DC bias voltage is 500V, the diode D2is forward biased slightly less than ϕ, capacitance of the diode D2is equal to K (or a relatively high capacitance), and the diode D1is provided with a high-reverse DC bias voltage and thus has a smaller capacitance than the diode D2. The small capacitance of diode D1dominates the composite capacitance of diodes D1, D2, since the diodes D1, D2are connected in series.

The condition in which one diode is slightly forward biased is different from traditional varactors with center-tapped bias circuits. An example traditional varactor having a center-tapped bias circuit is shown inFIG. 10in which both diodes are reverse-biased by a DC bias voltage. The varactor tuning circuits disclosed herein operate as a variable capacitor while a DC bias voltage plus a voltage of a RF input signal is less than an Avalanche breakdown voltage (e.g., ±1200V) of the corresponding back-to-back diodes. The traditional varactors with center-tapped bias circuits do not function as a variable capacitor unless the bias voltage of each diode is negative and has an absolute value greater than a peak RF voltage. This is unlike the disclosed varactor tuning circuits, which allow one of the diodes to be forward biased and allows the diodes to be biased with a voltage having an absolute value less than a peak voltage of a received RF input signal.

The disclosed varactor tuning circuits operate as a variable capacitance while one of the diodes is forward biased and the other one of the diodes is reversed biased. Since one of the diodes is reversed biased, a forward bias voltage across the other diode, while the DC bias voltage is greater than 0 and is adjusted in magnitude, remains at a voltage (e.g., 1.2V) less than the built-in potential (e.g., 1.6V) and is prevented from exceeding the built-in potential ϕ. This allows the disclosed varactor tuning circuits to continue to operate as a variable capacitor for a large range of DC bias voltages. See for exampleFIG. 11A. Zero-biasing the diodes of the traditional varactors with center-taped bias voltage results in the diodes turning ON due to an RF voltage received and the diodes no longer operating as a variable capacitor. When the diodes of the traditional varactors turn ON, the traditional varactors operate as a rectifier and no longer operate as a variable capacitor. This is unlike the disclosed varactor tuning circuits, which provide peak capacitance when the DC bias voltage across the diodes is 0, see for exampleFIG. 11C. The diodes of the disclosed varactor tuning circuits are OFF (not forward biased at a voltage greater than the built-in potential ϕ) when the DC bias voltage is 0. The capacitance of the disclosed varactor tuning circuits decreases as the DC bias voltage increases. As a result, the disclosed varactor tuning circuits operate fundamentally different than traditional varactor circuits with center-taped bias voltages.

If a small RF input voltage (much less than the DC bias voltage) is applied to the back-to-back diode varactor400, capacitance can be varied from K/2 to a smaller value (with a range of a ratio of a maximum capacitance Cmax of the back-to-back diode varactor400to a minimum capacitance Cmin of the back-to-back diode varactor400being 3-10x, where x is a predetermined value). When the RF input signal voltage increases (as in a high-power circuit), the diodes D1, D2may alternately become reverse biased as the RF input signal transitions from a positive peak to a negative peak. The net effect of this situation reduces a tuning range of the back-to-back diode varactor400. This effect can be reduced by adding diode pairs in series with the existing diodes D1, D2, but this reduces the capacitance of the back-to-back diode varactor400and increases cost/complexity. The hybrid tuning circuits described with respect to, for example,FIGS. 12, 14, 17 and 21-22overcome these problems.

For a small RF input signal (e.g., less than 10V peak-to-peak), the following equations 5-11 andFIGS. 11A-11Cmay be used or a variation thereof depending upon the components incorporated in the varactor being monitored and/or operated. Equations 5-11 and plots ofFIGS. 11A-11Bare for the back-to-back diode varactor ofFIG. 8Awithout RF chokes (e.g., the inductors L1, L2) and without one or more bypass capacitors (e.g., the capacitor C1).

If the power law exponent n of equation 4 is equal to 0.5, equation 4 can be converted to equation 5.

C=Kϕ-V(5)
The capacitance relationship of equation 5 has a corresponding sharply non-linear capacitance-voltage curve with a highest capacitance at a smallest magnitude of a DC bias voltage. Since the diodes D1, D2are arranged back-to-back in series, the anodes of diodes D1, D2have equal and opposite charge, such that charge Q1of diode D1is equal to charge Q2of diode D2, where V1is voltage across diode D1and represented by curve420inFIG. 11A. The charge Q1is represented by equation 6 and the charge Q2is represented by equation 7, where voltage V2is voltage across diode D2and represented by curve422inFIG. 11A. Setting Q1equal to Q2provides equation 8.

In addition, since voltages across the diodes D1, D2are defined from anode to cathode, a total voltage V across the diodes D1, D2is represented by equation 9.
V=V2−V1(9)
Equations 7-9 may be used to solve for V1and/or V2. For example, since V2is equal to V plus V1, equation 8 can be converted to provide equation 10.

KV1ϕ-V1=(K⁡(V+V1))ϕ-(V+V1)(10)
Solving for V1in terms of V provides equation 11. A similar equation can be provided for V2.

Capacitances C1, C2respectively of the diodes D1, D2and a total capacitance CTacross the diodes D1, D2can be determined using equations 12-14. These capacitances may be determined via the modules and/or devices350,164,180,362ofFIGS. 5-7and/or during the method ofFIG. 21.

Varactor Circuit Variants

The back-to-back diode configuration of the back-to-back diode varactor400reduces harmonics that can result from a nonlinear capacitance-RF input voltage relationship. Harmonics are reduced because capacitance of one diode increases while capacitance of the other diode decreases, due to charge conservation. If a DC bias voltage is applied, the center node (or node between the anodes of diodes D1, D2) is charged. A voltage across the diodes, D1, D2slowly decays when the DC bias voltage is removed depending upon a leakage current of diode D1. This can cause issues if very fast capacitance changes are required. A bleeder resistor R1(e.g., a 100 kilo-Ohm resistor) may be connected across the diode D1to allow faster changes in the DC bias voltage, as shown or may be connected between (i) the diodes D1, D2and (ii) ground. A first end of the bleeder resistor R1may be connected to the center tap between the diodes D1, D2and a second end of the bleeder resistor R1may be connected to ground. AlthoughFIG. 8Ashows the diodes D1, D2connected anode-to-anode, the diodes may be connected cathode-to-cathode, where the respective anodes of the diodes D1, D2are connected to (i) the inductor L1and the capacitor C1, and (ii) the RF input terminal and the inductor L2. This is shown inFIG. 8B.

The back-to-back diode varactor400responds to changes in the DC bias voltage. The changes are a function of the applied RF input voltage. This is shown inFIG. 9A. With varying RF power levels, the applied RF input voltage has a noticeable impact to a range of capacitance of the back-to-back diode varactor400. To understand a magnitude of this effect, differences in capacitance for different RF power levels and DC bias voltages for the back-to-back diode varactor400are shown inFIG. 9B. At high-power levels, the effect the RF power level has on the change in capacitance is reduced. For this reason, the back-to-back diode varactor400may be used for fine tuning purposes in combination with the FET switched capacitance circuit50. The DC bias voltage may be set high to minimize the effect of RF power level on the capacitance of the back-to-back diode varactor400, thereby allowing the capacitance to be fine-tuned from a set point or range set by the FET switched capacitance circuit50. The capacitance is fined tuned by adjusting the DC bias voltage.

FIG. 12shows a hybrid tuning network500with a coarse tuning network502and a fine tuning network504. The fine tuning network504is connected in parallel with the coarse tuning network502between an RF input terminal505and an RF output or reference terminal506. If the terminal506is a reference terminal, the reference terminal506may be connected to ground. Although the coarse tuning network502is shown as a switchable circuit including FETs, the coarse tuning network502may include PIN diodes, relays, and/or other elements having controllable state changes. The coarse tuning network502includes one or more FET switch capacitance circuits508(m FET switch capacitance circuits are shown). In one embodiment, the coarse tuning network502includes five FET switch capacitance circuits508. The fine tuning network504includes one or more varactors509(n varactors are shown). In one embodiment, each of the varactors509includes two pairs of back-to-back diodes. In an embodiment, the fine tuning network504includes two varactors. An inductor LRFis connected between the RF input terminal505and ground. The FET switch capacitance circuits508and the varactors509output respective RF output signals to the RF output or reference terminal506depending on whether the hybrid tuning network500is included in a shunt eVC (e.g., CLOAD) or a series eVC (e.g., CTUNE).

Each of the FET switch capacitance circuits508includes corresponding: transistors T1, T2; capacitors C1, C2, C3, C4; inductors L1, L2, L3, L4, L5; and resistors R1, R2, R3. The transistors T1, T2may be power metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-to-drain diodes, as shown or may be replaced with other switching devices, such as other types of transistors and/or RF switches (e.g., microelectromechanical (MEM) switches). The capacitances, inductances and resistances of the circuit elements of each of the FET switch capacitance circuits508may be different. In one embodiment, the capacitances of the transistors T1, T2and the capacitors C1, C2, C3, C4of each of the FET switch capacitance circuits508are different, such that each of the FET switch capacitance circuits508provides a different overall capacitance.

For each of the FET switch capacitance circuits508, sources of the transistors T1, T2are connected to the inductor L2, which is connected to ground. Gates of transistors T1, T2are connected to the inductor L1. The resistor R1and the inductor L1are connected in series between the gates and a control terminal510. A drain of the transistor T1is connected to capacitors C1, C2and to inductor L3. Capacitors C1, C2are connected in parallel between the drain of transistor T1and the RF input terminal505. Inductors L3, L4and resistor R2are connected in series between the drain of transistor T1and a bias input terminal512, which receives a corresponding DC bias voltage. The DC bias voltage may be received from one of the modules and/or devices350,164,180,362ofFIGS. 5-7. Inductor L5and resistor R3are connected between a drain of transistor T2and the bias input terminal512. Capacitors C3, C4are connected in parallel between the drain of the transistor T2and the RF output or reference terminal506.

The inductors L1, L2, L3, L4, L5block RF signals from passing to control circuits, DC bias circuits and/or ground. More RF power is received at the drain of the transistor T1than exists at the sources of transistors T1, T2and/or the drain of transistor T2. For this reason, two inductors L3, L4are provided between the drain of transistor T1and the DC bias terminal512to provide added protection to prevent RF power from passing from the capacitors C1, C2to the DC bias terminal512. Each of the FET switch capacitance circuits508has a respective DC bias terminal and receives a respective DC bias voltage.

Each of the varactors509includes a first pair of back-to-back diodes D1, D2, a second pair of back-to-back diodes D3, D4, resistors R1, R2, inductor L1and capacitors C1, C2, C3. Anodes of the diodes D1, D2may be connected to each other and anodes of diodes D3, D5may be connected to each other. In another embodiment, cathodes of the diodes D1, D2are connected to each other and cathodes of the diodes D3, D4are connected to each other. The diodes D1, D2and inductor L1are connected in series between the RF input terminal505and a DC bias terminal520. The diodes D1, D2, D3, D4are biased based on a received DC bias voltage. Each of the varactors509may have a respective DC bias terminal and receives a respective DC bias voltage. In the embodiment, shown, the varactors509have a common DC bias terminal520and receive a same DC bias voltage.

Resistors R1of the varactors509are connected between the anodes of D1, D2and ground. Resistors R2are connected between the anodes of D3, D4and ground. Cathodes of diodes D2, D4are connected to each other. Capacitors C1, C2, C3of the varactors509are connected in parallel and between the cathodes of the diodes D2, D4and the RF output or reference terminal506.

The DC bias voltages provided to the DC bias terminals (e.g.,512,520) of the FET switch capacitance circuits508and the varactors509may be between 0-800 VDC and provided by a digital-to-analog (D-to-A) converter (e.g., an example of a D-to-A converter is shown inFIG. 20). The D-to-A converter may include converters, transformers, and/or other circuit elements to convert 0-3.3 VDC to 0-800 VDC. DC bias voltages are provided to the FET switch capacitance circuits when the transistors T1, T2are OFF (or during a FET capacitance control mode). A DC bias voltage (or voltages) are provided to the varactors509during a varactor capacitance control mode. These modes are further described below with respect toFIG. 21.

AlthoughFIG. 12shows incorporation of both a switchable network (or multiple FET switch capacitance circuits) and a varactor network (or multiple varactors), in certain embodiments, only the switchable network or only the varactor network are included as part of a tuning network. For example, in one embodiment, the one or more of the varactors509are connected in parallel and are implemented without the FET switch capacitance circuits. This provides a varactor-based timing network, which may be implemented as CLOADand/or CTUNE.

FIG. 13shows a switch driver circuit550that provides fast switching between states of FETs of a coarse tuning network (e.g., the coarse tuning network502ofFIG. 12) of a hybrid tuning network. A version of the switch driver circuit550may be provided for each of the FET switch capacitance circuits of a coarse tuning network of a hybrid tuning network. The switch driver circuit550provides (i) control signals to gates of FETs T1, T2of a FET switch capacitance circuit551, and (ii) DC bias voltages to drains of the FETs T1, T2. The DC bias voltages are provided when the FETs T1, T2are OFF or the gates of the FETs T1, T2are low. The DC bias voltage is switched ON and OFF to swing voltage across the FETs T1, T2between a high-voltage (e.g., 600-800 VDC) and 0V. The DC voltage swings between the high-voltage and 0V at a switching rate of, for example, less than 10 micro-seconds (μs). The switch driver circuit550provides a cascade transistor configuration that provides the quick transition between the high-voltage and 0V.

The switch driver circuit550includes a bipolar combination circuit560, a bias control circuit562, and a switch control circuit564. The bipolar combination circuit560controls states of the circuits562,564and whether a predetermined voltage (e.g., 12V) is provided to the circuits562,564to enable operation of the circuits562,564. The bias control circuit562controls whether a predetermined bias voltage (e.g., 600-800 VDC) is provided to the FETs T1, T2. The switch control circuit564controls ON/OFF states of the FETs T1, T2.

The bipolar combination circuit560includes transistors Q1, Q2, diodes D1, D2. Bases of the transistors Q1, Q2receive a control signal CTRL, which may be generated by one of the modules and/or devices350,164,180,362ofFIGS. 5-7. The control signal CTRL turns ON and OFF the bipolar combination circuit560. A collector of Q1is connected to a cathode of D1and receives a supply voltage VB. Emitters of Q1, Q2are connected to each other and to an anode of D1and a cathode of D2. A collector of Q2is connected to an anode of D2and to a terminal at a supply voltage −VB.

The bias control circuit562includes transistors Q3-Q5, resistors, R1-R9, capacitors C1-C3, diode D3, and inductors L1-L4. The resistor R1and capacitor C1are connected in parallel and to (i) an output of the bipolar combination circuit560, (ii) resistor R2, and (iii) a base of Q4. The resistor R2is connected to ground. An emitter of Q4is connected to ground. A collector of Q4is connected to resistor R3, which is connected to resistor R4, base of Q3and a cathode of D3. Resistor R4is connected to resistor R5and collectors of transistors Q3, Q5. Transistors Q3, Q5are connected as a Darlington pair. Resistor R5receives a high DC bias voltage (e.g., 600-800 VDC) from a voltage supply. An emitter of Q3is connected to a base of Q5. An emitter of Q5is connected to an anode of D3, the capacitor C2and the inductor L1. The capacitor C2is connected to ground. The inductor L1is connected to R6and is in series with R6and R7. Although not shown, a capacitor may be connected (i) across the inductor L1, (ii) at a first end to the anode of D3, the emitter of Q5and C2, and (iii) at a second end to resistor R6. The resistor R6is connected to capacitor C3and resistor R7. The capacitor C3is connected to ground. The resistor R7is connected to resistors R8and R9. Resistor R8and inductors L2, L3are connected in series between the resistor R7and a drain of T1. The resistor R9and inductor L4are connected in series between the resistor R7and a drain of T2.

The switch control circuit564includes resistors R10, R11, capacitors C4, C5, C6and inductors L7, L8. Resistor R10, inductor L7, resistor R11and inductor L8are connected in series between (i) the output of the bipolar combination circuit560and (ii) gates of the transistors T1, T2. Capacitor C4is connected between (i) the resistor R10, the capacitor C5and the inductor L7, and (ii) ground. Capacitor C5is connected in parallel with inductor L7. Capacitor C6is connected between (i) capacitor C5, inductor L7, and resistor R11, and (ii) capacitor C6. The resistor R11is connected to the inductor L8, which is connected to gates of T1, T2.

The FET switch capacitance circuit551includes the FETs T1, T2, capacitors C7-C10and inductors L5, L6. Capacitors C7, C8are connected in parallel between an RF input terminal570and a drain of T1. Inductor L5is connected between the RF input terminal570and ground. Inductor L6is connected between sources of the T1, T2and ground. Capacitors C9, C10are connected in parallel between a drain of T2and an RF output terminal or ground572. Capacitors C9, C10are connected to an RF output terminal if the FET switch capacitance circuit551is part of a tuning capacitor (e.g., the tuning capacitor314ofFIG. 7). Capacitors C9, C10are connected to ground if the FET switch capacitance circuit551is part of a load capacitance (e.g., load capacitor312ofFIG. 7).

During operation, if the control signal CTRL is HIGH, then Q1, Q2are ON. Since Q1, Q2are ON, the FETs T1, T2are ON, Q4is ON, Q3and Q5are OFF and the bias voltage provided to the FETs is 0V. If the control signal CTRL is LOW, then Q1, Q2are OFF. Since Q1, Q2are OFF, the FETs T1, T2are OFF, Q4is OFF, Q3and Q5are ON and the bias voltage provided to the FETs is at a high-voltage (e.g., 600-800 VDC). The cascade transistor arrangement of Q3, Q5allows for a bias voltage switching rate of less than 10 μs.

Voltage Stress Reduction

Possibly the greatest challenge associated with a solid-state variable capacitor is handling voltage stress. To complement the hybrid tuning networks disclosed herein, impedance transformation techniques are disclosed to reduce voltage stress. This is especially applicable for a tuning capacitor (e.g., the timing capacitor314ofFIG. 7) of an impedance matching network. As an example, the voltage stress of a tuning capacitor can be greater than 2800 root mean squared voltage (Vrms) when 3 kilo-watts (KW) is applied at an RF input for a tuned condition and received by the tuning capacitor. Three approaches are described to limit the voltage stress associated with impedance matching networks and include impedance transformation, transformer coupling, and modified impedance matching.

Impedance Transformation

Traditionally, an input impedance to an impedance matching network is 50 Ohms (Ω) and matches a characteristic impedance of a line section coupling a RF power supply to a load. As disclosed herein, the input impedance is scaled at the RF input from 50Ω to an impedance less than 50Ω. Voltage drop is a square root of impedance drop. For instance, if the impedance changes by a factor of 2 from 50Ω to 25Ω, then voltage stress can decrease by a factor of √{square root over (2)}.

The impedance transformation may be provided via a transformer. A transformer may be connected between the RF input and the load and tuning capacitors of an impedance matching network. For example, a transformer may be connected between (i) resistor330and (ii) capacitors312,314ofFIG. 7. The primary and secondary windings of the transformer may be preconfigured to provide a predetermined impedance transformation (e.g., 50Ω to 25Ω). An example impedance transformation transformer602is shown inFIG. 14.

FIG. 14shows another impedance matching network600that includes an impedance transformation transformer602and includes a load capacitor CLOAD, an inductor L1, a tuning capacitor CTUNE, and an inductor L2. The impedance transformation transformer602includes a primary winding606and a secondary winding608. The primary winding606receives a RF input signal. The output of the secondary winding608is connected to the capacitors CLOAD, CTUNE. The capacitors CLOAD, CTUNEmay be implemented similarly to the capacitors312,314ofFIG. 7. The capacitor CLOADis connected in series with the inductor L1and between the output of the transformer602and ground. The capacitor CTUNEis connected in series with the inductor L2and between the output of the transformer602and an output terminal610of the impedance matching network600.

Transformer Coupling

FIG. 15Ashows another impedance matching network620that includes an input capacitor CIN, a load capacitor CLOAD, a transformer622, a timing capacitor CTUNE, and an output capacitor CC. The transformer622includes a primary winding624and a secondary winding626. The capacitors CIN, CLOADare connected between the primary winding624and ground and receive an RF input signal. The capacitors CLOAD, CTUNEmay be implemented similarly to the capacitors312,314ofFIG. 7. The primary winding624is connected between an RF input terminal and the capacitor CC. The capacitor CTUNEis connected between the second winding626and ground. The secondary winding626is connected between the capacitor CTUNEand ground.

The electronic variable elements that are susceptible to the highest voltage stress (i.e. the capacitors CLOAD, CTUNE) are transformer coupled via the transformer622. The transformer622may be implemented as an air-wound transformer having an air-wound coil, where the secondary winding626is wrapped around a tubular coil. The primary winding624is located within a channel of the tubular coil. The channel includes air. The air within the channel and the insulative (or dielectric) material of the tubular coil provide an insulative barrier between the primary winding624and the secondary winding626. An example of an air-wound transformer is shown inFIG. 18.

Example series and shunt reactance curves are respectively shown inFIG. 15Bfor the capacitor CTUNEand capacitor CLOADusing an air-wound transformer. A series reactance range650, a shunt reactance range652and a measured series reactance range654are shown.FIG. 16Ashows model driven requirements for the series reactance without the air-wound transformer for a capacitance range of 160 to 980 pF.FIG. 16Bshows actual measured series reactance with transformer coupling. The series reactance ofFIG. 16Boverlaps modelled reactance requirements for an impedance matching tune space. The change in the capacitance between the plots ofFIGS. 16A, 16Bis related to a number of turns of the air-wound transformer and a corresponding impedance transformation of the air-wound transformer, which is a second benefit with transformer coupling. The eVC range of the impedance matching network is increased as a function of a number of turns of the air-wound transformer.

Modified Impedance Matching

FIG. 17is a schematic diagram of another impedance matching network670that includes an input capacitor CIN, a load capacitor CLOAD, inductor672,674,676, a tuning capacitor CTUNE, and an output capacitor CC. Resistance of a RF power supply is represented by resistor R1. The capacitors CIN, CLOADare connected between the inductor672and ground and receive an RF input signal from the RF power supply. The capacitors CLOAD, CTUNEmay be implemented similarly to the capacitors312,314ofFIG. 7. The inductor672is connected between an RF input terminal and the capacitor CC. The inductors674,676are connected in series between (i) the inductor672and the capacitor CC, and (ii) the inductor676and the capacitor CTUNE. The capacitor CTUNEis connected between (i) an output of the inductor674and input of the inductor676, and (ii) ground. The inductor676is connected between the inductor674and ground. The capacitor CCis connected between (i) the inductors672,674and an output terminal of the impedance matching network670. By the capacitor CTUNEbeing connected to a node between the inductors674,676, the capacitor CTUNEis connected to a lower voltage stress node. The capacitor CTUNEmay be a solid-state variable capacitor. AlthoughFIG. 17is directed to reducing voltage stress for the capacitor CTUNE, a similar implementation may be provided to reduce voltage stress for CLOAD.

Dual Enclosure

FIG. 18is a view of a dual enclosure. The dual enclosure includes a first (outer) enclosure700and a second (inner) enclosure702. The inner enclosure702is within the outer enclosure700. The outer enclosure700is an air-tight enclosure, such that air is unable to enter or exit the outer enclosure700. One or more hybrid tuning networks (a single hybrid tuning network704is shown) are disposed within the inner enclosure702and are cooled via fans708,710and a heat exchanger712. Any of the hybrid tuning networks disclosed herein and/or corresponding impedance matching circuits may be disposed within the inner enclosure702.

In the example shown, the fan708directs air out of the inner enclosure702and into the outer enclosure700. The fan710directs air from the outer enclosure700into the inner enclosure702. The air is passed through the heat exchanger712. Although two fans are shown, one or more fans may be included. As an alternative embodiment, the fans708,710may both direct air (i) into the inner enclosure702, or (ii) out of the inner enclosure702. If the fans708,710are both directing air in the same direction, the inner enclosure702may have openings (e.g., holes) to allow air to pass through a wall of the inner enclosure702and between (i) an area in the inner enclosure and (ii) an area exterior to the inner enclosure702and in the outer enclosure700.

A cooling fluid (e.g., water) is circulated in and out of the heat exchanger712and in and out of the outer enclosure700to cool the air passing through the heat exchanger712. An alternative to using the heat exchanger712, fins may be mounted within the outer enclosure700along outer surfaces of the outer enclosure700. The fins increase surface area and remove heat from the outer enclosure700.

An air-wound transformer714is shown and is connected to the hybrid tuning network704. The air-wound transformer714may be implemented as described above with respect toFIG. 15A. The air-wound transformer714includes a primary coil715and a secondary coil717. The secondary coil717is wrapped around the primary coil715. The primary coil715may be an air-wound coil. A first end719of the primary coil715may be connected to capacitor CLOAD(an example of a first end of a primary coil being connected to a capacitor CLOADis shown inFIG. 15A). A second end721of the primary coil715may be connected to capacitor CC. A first end723of the secondary coil717may be connected to capacitor CTUNE(an example of which is shown inFIG. 15A). A second end725of the secondary coil717may be connected to ground.

The hybrid tuning network704may be implemented as capacitor CLOADor capacitor CTUNEand include a coarse tuning network716and a fine tuning network718. The coarse tuning network716and the fine tuning network718may be implemented as any of the coarse tuning networks and fine tuning networks disclosed herein. As an example, the coarse tuning network716may be implemented as a FET switch capacitance circuit and the fine tuning network718may be implemented as a varactor circuit. Although a single hybrid tuning network is shown inFIG. 18, more than one hybrid tuning network may be implemented within the inner enclosure702.

Conventional matching networks utilize fans for convection cooling electromechanical devices. Air is exchanged from within an enclosure with air in a local environment external to the enclosure by convection cooling. For solid-state devices used in an eVC, a high-volume of air exchange brings particles into an enclosure, and over time, may cause generation of undesirable conductive paths overlaying circuitry. The embodiment ofFIG. 18provides a dual enclosure that has a high volume of pressurized air to cool components of an impedance matching network without being open to exterior particles. The embodiment ofFIG. 18mitigates parasitic impedances from affecting circuit performance by having limited conduction cooling. The dual enclosure minimizes contaminates and prevents accumulation of particles overtime. The accumulation of particles can degrade operation of eVCs. The dual enclosure embodiment: (1) removes heat from the inner enclosure702via the fans708,710and heat exchanger712; (2) provides a larger surface area within the outer enclosure700for heat exchange without a coolant filled heat exchanger; and (3) may circulate compressed air in the inner enclosure702for thermal convection cooling. In the event a component of an eVC fails, the sealed outer enclosure700prevents a release into a clean room environment any particles from within the inner enclosure702. If a failure of a solid-state device occurs, emission of toxic gas and particles can occur, which are contained within the enclosures700,702. This embodiment is different than direct conduction cooling of RF semiconductor devices.

Additionally, many plasma reactors are heated for semiconductor manufacturing processes, which can impinge on thermal operation of devices used in an electronic matching network if conduction cooling is the primary thermal solution. The electronic devices of the networks716,718, which may be implemented on a PCB are not mounted directly to a heat sink. The electronic devices may be mounted upright and primarily cooled using convection cooling. Fans blow and circulate air within the volume of the inner enclosure702. Heat is removed from the inner enclosure702. This prevents dissipation, which can occur in various circuit elements of an impedance matching network without heat removal. The stated-embodiments prevent conductive particles from being brought into the inner enclosure702and being deposited on circuit components and adversely affecting operation of the impedance matching network.

Calibration

FIG. 19shows an example Smith chart of a tune and load space of an impedance matching network including a hybrid tuning network. The load space is the impedance region that the impedance matching network can translate to a source impedance. The tune space is the impedance to convert the load impedance to the source impedance. A metric widely used in industry is repeatability of a tune space between multiple manufactured impedance matching networks. Many suppliers of conventional impedance matching networks calibrate a tune impedance range to a specification to reduce variability from component to component.

The parallel combination of FET switch capacitance circuits and varactors provided by the disclosed hybrid tuning networks enable a tuning method of an impedance matching network, which includes solid-state eVCs. The plot of capacitance of a varactor as a function of bias voltage shown inFIG. 16Aindicates a varying range of capacitance. In one embodiment, calibration includes setting a particular bias voltage for each varactor of a hybrid tuning network. This yields a more reproducible product. More importantly, a wide range of capacitance and different combinations of FET switch configurations provide multiple solutions. For example, a particular tune impedance may be achieved by providing (i) a low bias voltage to set a varactor at a high capacitance, and (ii) a FET switch configuration with a low capacitance range. Similarly, the same reactance could be achieved for a high bias varactor voltage to obtain a low varactor capacitance with the FET switches configured to a high capacitance value. The parallel configuration provides reasonable tuning conditions with different network configurations. The disclosed calibration method alleviates the repeatability problem and enables a hybrid tuning control method described below with respect toFIG. 21.

FIG. 20shows a control circuit800including a control module802and a hybrid tuning network804. The control module800may be implemented as one or more of the modules and/or devices350,164,180,362ofFIGS. 5-7. The control module802includes (i) a FET control circuit806or other coarse tuning control circuit, (ii) a varactor bias circuit808or other fine tuning bias circuit, (iii) analog-to-digital (A/D) converters810,812, and (iv) an adjustment module813. The hybrid tuning network804includes (i) FET switch capacitance circuits820or other coarse tuning circuits, and (ii) varactors822or other fine tuning circuits. The FET switch capacitance circuits820may be implemented as the switch capacitance circuits508ofFIG. 12. The varactors822may be implemented as the varactors509ofFIG. 12.

The FET control circuit806may include and/or be connected to a binary control interface834. The binary control interface834forwards control signals (e.g., control signal CTRL) to driver circuits838. Each of the driver circuits838may be implemented as the switch driver circuit550ofFIG. 13. The driver circuits838drive FETs in the FET switch capacitance circuits820including providing DC bias voltages and gate control signals. DC bias voltages provided to the FETs may be measured and/or provided as feedback signals to the A/D converters810.

The varactor bias circuit808includes a digital-to-analog converter (DAC) interface840that converts digital bias control signals to analog bias control signals, which are provided to the varactors822to set DC bias voltages of the varactors822. As an example, the DAC interface may include a 212-bit DAC. For a 100 pF range, capacitance resolution of the hybrid tuning network804is 0.02 pF (100 pF/212). This is at least an order of magnitude better than prior art tuning networks. As an example, one of the analog bias control signals may be provided to the DC bias terminal520ofFIG. 12. Actual DC bias voltages at the varactors may be measured and/or provided to the A/D converters812.

The control module802and/or the adjustment module813controls operation of the circuits806,808based on the feedback signals generated by the A/D converters810,812. The control module802and/or the adjustment module813may control generation of and/or adjust the signals output from the interfaces834,840. The control circuit800may be operated according to, for example, the method ofFIG. 21.

For further defined structure of the modules ofFIGS. 5-7 and 20see below provided method ofFIG. 21and below provided definition for the term “module”. The systems, networks, and circuits disclosed herein may be operated using numerous methods, an example method is illustrated inFIG. 21. InFIG. 21, a hybrid tuning control method is shown. Although the following tasks are primarily described with respect to the implementations ofFIGS. 5-7, 12-13 and 20-21, the tasks may be easily modified to apply to other implementations of the present disclosure. The tasks may be iteratively performed. The tasks may be performed by control circuit800ofFIG. 20.

The method may begin at900. At902, a circuit (e.g., the control circuit800) operates in an initialization mode and an electronic match is initialized. This includes setting DC bias voltages of one or more coarse tuning networks and one or more fine tuning networks. The DC bias voltages may be initial predetermined voltages stored in memory (e.g., memory352). The DC bias voltages may be set by a system user and/or customer. A coarse tuning control circuit (e.g., the FET control circuit806) generates control signals (e.g., control signal CTRL) to set initial DC bias voltages of the coarse tuning network(s). The control signals are provided to driver circuits (e.g., driver circuits838), which in turn provide DC bias voltages to the coarse tuning networks (e.g., the FET switch capacitance circuits820). A fine tuning bias circuit (e.g., the varactor bias circuit808) sets initial DC bias voltage(s) for the fine tuning network(s).

At904, a control module (e.g., one of the control modules162,180,350,362,802, or a controller) determines whether RF power is ON. For example, the control module may determine whether a RF input signal is being generated and received by the coarse tuning network(s) and the fine tuning network(s). If the RF input signal is being received, task905may be performed.

At905, the control module may wait a predetermined period of time prior to transitioning between the initialization mode and a direct conversion mode (or first coarse tuning mode). The predetermined period of time may be greater than or equal to 0 seconds. This delay may be implemented based on a clock, a timer, a counter or other timing method implemented by the control module.

At906, the control module and/or an adjustment module (e.g., the adjustment module813) transitions to the direct conversion mode and determines whether a value K is equal to 0. Although not shown inFIG. 21, K may be set to a predetermined value prior to or at a beginning of operating in the direct conversion mode. K is an integer and may be initially greater than or equal to 0. If K is equal to 0, then task914is performed, otherwise task908is performed.

At908, the control module determines one or more distortion quantities (e.g., one of the distortion quantities dt, dl, or d described above). As an example, the distortion quantities may be generated by one of the modules144,170,350and provided to and/or accessible by the adjustment module. Although the following tasks are described with respect to a single distortion quantity, the tasks may be performed based on multiple distortion quantities.

At910, the coarse tuning control circuit, based on the distortion quantity, generates control signal(s) to adjust the DC bias voltage(s) initially provided to the coarse tuning network(s). Each iteration of task910includes a single adjustment in one or more of the DC bias voltage(s). The control signals are provided to the driver circuits, which in turn provide adjusted DC bias voltage(s) to the coarse tuning network(s). The control signal(s) may be generated based on a relationship or table having predetermined control signal values for distortion quantity ranges. In one embodiment, the fine tuning bias circuit adjusts DC bias voltage(s) for the fine tuning network(s) based on the distortion quantity. In this embodiment and for each iteration of task910, each of the DC bias voltage(s) of the fine tuning bias circuit is adjusted once. The DC bias voltage(s) for the fine tuning network(s) may be generated based on a relationship or table having predetermined DC bias voltages for distortion quantity ranges. In another embodiment, the fine tuning bias circuit does not adjust the DC bias voltage(s) provided to the fine tuning network(s).

The adjustments performed during task910may be associated with large steps or changes in DC bias voltages and/or capacitances of the coarse tuning network(s) and the fine tuning network(s). The DC bias voltages of the coarse tuning network(s) and the fine tuning network(s) are generated as estimates to set the capacitances within predetermined ranges of target capacitance values. Further tuning is performed in tasks914-922to more accurately set capacitances of the coarse tuning network(s) and the fine tuning network(s) to the target capacitance values.

The direct convergence performed during task910may be performed based on expressions 15-16, where GCLOADis gain of CLOADand GCTUNEis gain of CTUNE, dris a real distortion quantity of d, and diis an imaginary distortion quantity of d. Example plots are shown inFIGS. 22A, 22Bfor four different test cases T1-T4.
GCLOAD=205dr−1(15)
GCTUNE=277di−1(16)
The gain GCLOADis directly proportional to an amount of change in DC bias voltages and/or capacitances of CLOAD. The gain GCTUNEis directly proportional to an amount of change in DC bias voltages and/or capacitances of CTUNE.

If dris large, then the gain GCLOADis near 0 and there is minimal change to the DC bias voltages and corresponding capacitances for CLOAD. As drdecreases in magnitude, the gain GCLOADincreases in magnitude and the DC bias voltages and corresponding capacitances are adjusted. Similarly, if diis large, then the gain GCTUNEis near 0 and there is minimal change to the DC bias voltages and corresponding capacitances for CTUNE. As didecreases in magnitude, the gain GCTUNEincreases in magnitude and the DC bias voltages and corresponding capacitances are adjusted. At912, the control module sets the value K equal to K minus 1.

At914, the control module and/or the adjustment module transitions from the direct conversion mode to a second coarse tuning mode (or FET control mode). During the second coarse tuning mode, one or more DC bias voltage(s) of the coarse tuning network(s) may be adjusted. During the second coarse tuning mode, DC bias voltage(s) of the fine tuning network(s) are not adjusted. During task914, the control module and/or the adjustment module measures distortion to generate one or more distortion quantities (e.g., one of the distortion quantities dt, dl, or d described above). Although the following tasks are described with respect to a single distortion quantity, the tasks may be performed based on multiple distortion quantities.

At916, the control module performs proportional integral derivative (PID) control of the coarse tuning network(s) based on (i) the distortion quantity determined at914, (ii) target DC bias voltage(s), and (iii) measured DC bias voltage(s) feedback to the adjustment module via, for example, A/D converters (e.g., the A/D converters810). This includes changing the control signals and thus adjusting DC bias voltage(s) of the coarse tuning network(s).

At918, if a state of one or more devices (e.g., diode, switch, FET, relay, etc.) has changed due to the PID control at916, then task914is performed, otherwise task920is performed. In one embodiment, task920is performed after a state of the one or more devices has not been changed for a predetermined number of iterations of tasks914-918.

At920, the control module and/or the adjustment module transitions from the second coarse tuning mode to a fine tuning mode (or varactor control module) and determines one or more distortion quantities (e.g., one of the distortion quantities d1, dr, or d described above). Although the following tasks are described with respect to a single distortion quantity, the tasks may be performed based on multiple distortion quantities. During the fine tuning mode, the DC bias voltage(s) of the coarse tuning networks are not adjusted. During the fine tuning mode, the DC bias voltage(s) of the fine tuning networks may be adjusted.

At922, the control module performs proportional integral derivative (PID) control of the fine tuning network(s) based on (i) the distortion quantity determined at920, (ii) target DC bias voltage(s), and (iii) measured DC bias voltage(s) feedback to the adjustment module via, for example, A/D converters (e.g., the A/D converters812). This includes adjusting DC bias voltage(s) of the fine tuning network(s).

At924, if a DC bias voltage was changed due to the PID control at922, then task920is performed, otherwise the method may end at926. In one embodiment, task920is performed after no DC bias voltages have been changed for a predetermined number of iterations of tasks920-924. As an alternative to ending at926and if there has been a large (more than a predetermined amount of) change in the RF input voltage and/or a large (more than a predetermined amount of) change in distortion, the control module may return to task906,908,914or916.

To illustrate that the modes ofFIG. 21can be performed iteratively and in different orders than above-described, dashed-arrows are shown inFIG. 21. For example, at an end of the initialization mode, the direct conversion mode, the second coarse tuning mode, or the fine tuning mode may be performed. At an end of the direct conversion mode, the initialization mode, the second coarse tuning mode or the fine tuning mode may be performed. At an end of the second coarse tuning mode, the initialization mode, the direct conversion mode or the fine tuning mode may be performed. At an end of the fine tuning mode, the initialization mode, the direct conversion mode or the second coarse tuning mode may be performed.

The method ofFIG. 21may be performed for each hybrid tuning network and/or variable reactive element (e.g., CLOADand/or CTUNE) of a plasma processing system. The method ofFIG. 21may be performed for CLOADwhile the method ofFIG. 21is being performed for CTUNE. As an example, the control module may be operating in one of the initialization, direct conversion, second coarse tuning and fine tuning modes for a first hybrid tuning network and/or first variable reactive element while operating in a different one of the initialization, direct conversion, second coarse tuning and fine tuning modes for a second hybrid tuning network and/or second variable reactive element.

The above-described tasks are meant to be illustrative examples; the tasks may be performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application. Also, any of the tasks may not be performed or skipped depending on the implementation and/or sequence of events.

Control Summary

A traditional tuning network typically operates based on a function of frequency and includes two variable reactive elements. The hybrid tuning networks disclosed herein include two variable reactive elements CLOAD, CTUNE, where each of the variable reactive elements has two or more control actuators (or coarse and fine tune actuators). As above-described, a solid-state impedance network that includes varactors has a capacitance variation challenge due to changes in varactor impedance as a result of changes in applied RF voltage. This is readily seen inFIG. 9A, where capacitance varies for a varying applied RF power (voltage) with a constant DC bias voltage applied. The above-described implementations include controlling reactances of eVCs including varactors using fine and coarse tuning actuators (e.g., the control module802, the FET control circuit806, the varactor bias circuit808, the driver circuits838ofFIG. 20). FET switches may be referred to as coarse actuators and a varactor bias circuit may be referred to as a fine tuning actuator. A set of actuators per eVC enables a coordinated control methodology to quickly tune to variable load conditions and change applied RF voltages during plasma ignition and steady-state plasma operation with varying power conditions.

The sets of actuators allow for tuning of a hybrid tuning network and/or variable reactance element with different control sequences at a certain moment in time, for example: (1) simultaneous fine and course tuning; (2) course tuning only; and (3) fine tuning only. Prior to an ignition process, a preset configuration of the fine and course actuators are initially established, as described with respect to task902. Coarse tuning networks and/or FET switches provide course tuning during a transition from a vacuum state to a state of formulating plasma.

As RF input voltage varies, a control module (or impedance controller) maintains a tuned condition via coarse and/or fine adjustments. The fine adjustments are provided via fine tuning networks and/or varactors. Coarse and fine tune actuators may be controlled in different coarse/fine tune sequences. As an example, a coarse/fine tune sequence may include: coarse tuning only; coarse tuning followed by fine tuning; and/or fine tuning only. This sequence of actuation also enables different tuning rates for each actuator. For example, FET switching may occur at a higher rate than DC bias voltage adjustment of varactors. Rates of the actuators may be adjusted during a tuning session, thereby providing variable rate control of coarse and fine tuning actuators. These rates may be varied while RF input voltage is varied.

Actuation Examples

If a hybrid tuning network includes a coarse tuning network with 5 FET switch capacitance circuits, then 25or 32 possible combinations are available in providing an overall capacitance of the coarse tuning network. Four implementation examples are described below with respect toFIGS. 23A-23Dfor this type of hybrid tuning network. Tasks performed with respect to these examples may be performed for each eVC (e.g., CLOADand CTUNE) of an impedance matching network.

As a first example and referring toFIGS. 21 and 23A, the initialization mode may be performed. During the initialization mode combination3may be selected. Combination3may be changed to combination x during a subsequent iteration of the direct conversion mode, as identified by step1inFIG. 23A. Control may determine that the second coarse tuning mode can be skipped and the fine tuning mode may be performed. This may include decreasing a DC bias voltage to varactors of a fine tuning network to increase capacitance, as identified by step2inFIG. 23A.

As a second example and referring toFIGS. 21 and 23B, the initialization mode may be performed. During the initialization mode combination3may be selected. Combination3may be changed to combination x during a subsequent iteration of the direct conversion mode, as identified by step1inFIG. 23B. Combination x may be changed to combination y during an iteration of the direct convergence mode, as identified by step2inFIG. 23B. The fine tuning mode may be performed subsequent to performing the direct convergence mode. This may include decreasing a DC bias voltage to varactors of a fine tuning network to increase capacitance, as identified by step3inFIG. 23B.

As a third example and referring toFIGS. 21 and 23C, the initialization mode may be performed. During the initialization mode combination3may be selected. Combination3may be changed to combination x during a subsequent iteration of the direct conversion mode, as identified by step1inFIG. 23C. Combination x may be changed to combination y during an iteration of the direct convergence mode, as identified by step2inFIG. 23C. The fine tuning mode may be performed subsequent to performing the direct convergence mode. This may include decreasing a DC bias voltage to varactors of a fine tuning network to increase capacitance, as identified by step3inFIG. 23C. Due to plasma changes, step4may be performed including performing another iteration of the fine tuning mode including increasing the DC bias voltage to the varactors to decrease capacitance. During this adjustment, a maximum DC bias voltage may be reached, identified by number5inFIG. 23C. Another iteration of the direct convergence mode is then performed to change the combination from y to z, identified as step6inFIG. 23C. Another iteration of the fine tuning mode may then be performed to decrease the DC bias voltage to the varactors and increase capacitance, as identified by step7ofFIG. 23C.

As a fourth example and referring toFIGS. 21 and 23D, the initialization mode may be performed. During the initialization mode combination3may be selected. Combination3may be changed to combination x during a subsequent iteration of the direct conversion mode, as identified by step1inFIG. 23D. Combination x may be changed to combination y during an iteration of the direct convergence mode, as identified by step2inFIG. 23D. The fine tuning mode may be performed subsequent to performing the direct convergence mode. This may include decreasing a DC bias voltage to varactors of a fine tuning network to increase capacitance, as identified by step3inFIG. 23D. During step3, a minimum DC bias voltage may be reached (identified by number4inFIG. 23D) resulting in control to switch to the direct convergence mode to switch from combination y to combination z. This is shown by step5inFIG. 23D. Another iteration of the fine tuning mode may then be performed to decrease the DC bias voltage to the varactors and increase capacitance, as identified by step6inFIG. 23D.

FIG. 24is a Smith chart of bi-model impedance ranges (or tune spaces) of an impedance matching network including a hybrid tuning network. A challenge with RF power delivery systems is accounting for changes in load conditions during periods when plasma is not present, during transition periods when plasma is being generated, and during periods when plasma is present in a plasma chamber. The combination of the calibration and dual-actuation control techniques disclosed herein provide an additional enhancement. The impedance matching networks disclosed herein may operate in a single model mode or a multi-model mode (e.g., a bi-model mode). The parallel configurations disclosed herein that each include a coarse tuning network and a fine tuning network for a corresponding eVC enable operation in multi-modal tune spaces. This allows for operating in the same or different tune spaces (i) prior to plasma generation, (ii) during plasma generation, and (iii) while plasma exists in a plasma chamber.

During the process of plasma ignition, impedances of eVCs are controlled while transitioning from a vacuum state (no active plasma, or low energy particle state) to a high-density plasma glow state. The eVCs are configured to allow a portion of a tune space can be used to tune a first impedance and a second portion of the tune space can be used to tune a second impedance. Thus, multiple load impedance regions may exist. One instantiation that will benefit from a bi-modal tune space is to (1) perform tuning for a vacuum condition of a reactor (or generator) based on a first region, and (2) perform tuning for a plasma process based on a second region. Examples of different load and tune ranges (or regions) are shown inFIG. 24for CLOADand CTUNE. The benefit of this approach is that a RF power supply is able to deliver power into a near 50Ω load while the load is in a vacuum state. This was not achievable using a traditional impedance matching circuit. The multi-modal approach allows the RF power supply to deliver power into a smaller impedance region around a 50Ω load, which results in more reliable RF power delivery, less system complexity, and better processing conditions. As an example, the vacuum regions ofFIG. 24are provided with a capacitance range of CTUNEbeing 30-150 pF. The plasma processing regions ofFIG. 24are provided with a capacitance range for FET switches being 400-1500 pF for CLOADor CTUNE. Different multi-modal impedance ranges can be achieved with different impedance tuning circuits, which are controlled as described above.

As an alternative to providing impedance matching tuning control via a RF generator, autonomous tuning can be performed at an impedance matching network.FIG. 25shows a RF power system1000including a RF generator1002, an impedance matching network1004and the load106. The RF generator1002may operate similarly to the RF generator102ofFIGS. 5-6with regards to generating a RF signal. The RF generator1002may not include one or more of the modules144,160,164,170,176,180, the circuits146,172, and the summers162,178shown inFIGS. 5-6. The RF signal is provided to the impedance matching network1004via the cable108. The transmission line interlocks195may be included. The impedance matching network1004may include the impedance matching circuits150, second sensors190, interlocks191,193, first sensors1010and a control module1012. The first sensors may monitor RF signals, voltages, current, power, reverse power, forward power and/or or other parameters associated with the cable108.

The parameters detected by the sensors190,1010are provided to the control module1012. The control module1012controls operation of the impedance matching circuit150including the variable tuning elements152and the hybrid tuning networks153based on the parameters received from the sensors190,1010. The control module1012may operate similarly to the modules164,180,352,362ofFIGS. 5-7and control module802ofFIG. 20and may perform the method ofFIG. 21. This allows the hybrid tuning networks153to be controlled by the control module1012at the impedance matching network1004rather than remotely by the RF generator1002. This includes generate control signals and the DC bias voltages described herein to adjust capacitances of the hybrid tuning networks of CLOADand CTUNE.

Although the above-described implementations are primarily described with respect to eVCs, variable inductors that are electronically controlled may be used as solid-state tunable devices. Also, although FET switches are primarily disclosed for use in coarse tuning networks, PIN diodes may be used and switched, such that tolerable reflected power is achieved for a broad tune space and a corresponding RF power supply is configured for load power control. The load power control enables power regulation with non-zero reflected power.

The above-described embodiments provide solid-state impedance matching with variable reactance control. This is enhanced with techniques to reduce component stress. A sealed enclosure is also provided with a self-contained heat exchanger for improved cooling and degradation prevention.

Application Examples

The semiconductor manufacturing industry has appreciated the ability for tuning actuators to tune at time scales associated with plasma time constants and RF rise times. While frequency control has enhanced thin-films processes and allowed other techniques to evolve to support next generation device fabrication, these techniques have limited actuator tuning rates. The hybrid tuning networks disclosed herein have fast tuning actuators. Application examples are provided below that can benefit from the disclosed techniques.

RF power delivery during periodic RF power transitions can cause impedance fluctuations. For improved power delivery, the solid-state actuators disclosed herein enable a broader impedance tuning space relative to a limited frequency range. The more time the RF generator(s) is coupled to a 50Ω load during these periodic transitions, the more repeatable and reproducible is RF power delivery. The improved repeatability and reproducability corresponds to improved (i) plasma parameter control (e.g., electron temperature, density, and potential), (ii) tailored pulsed waveforms, and (iii) thin-film processing.

Continuous Plasma Processing:

Reactor temperature variation occurs during a transition from plasma ignition to steady-state cycling due to plasma and gas temperature heating. Additionally, process chemistry cycles vary through ionization and dissociations. This variance can be increased due to particle contamination. It is desirable to have plasma continuously ON for many plasma treatment steps in the manufacturing of semiconductor devices. This improves yields with steady-state plasma and reactor conditioning throughout the processing of multiple wafers and decreases manufacturing throughput time. The challenge imposed by continuous plasma processing is the variation of impedances during the multiple steps performed to process a wafer. High-speed impedance tuning actuators disclosed herein enable continuous plasma processing through a broader range of impedance space corresponding to a wider plasma process tune space.

A plasma-enhanced atomic layer deposition (PEALD) process is generally defined by a sequential set of mechanical and RF steps that are repeated for particular deposition objectives. Atomic layer etch (ALE), though not yet adopted in a high-volume manufacturing environment, is expected to be defined in a similar manner. During these sequential thin-film manufacturing steps, fast and repeatable ignition is desired. The electronic variable devices disclosed herein enable these types of processes to advance with more repeatable impedance matching.

50Ω impedance matching is common. The impedance matching networks disclosed herein provide a wide tune space for impedance matching with (i) reduced control system complexity, and (ii) a potential for less silicon to be used in a RF generator while providing increased reliability for a RF power delivery system.

Coupling power to a non-sinusoidal periodic impedance variation greatly benefits from the tuning actuators disclosed herein, which have time scales that are relative to a broadband response of a power supply. This creates a near steady-state impedance for constant voltage/current requirements of the RF power supply.

A First Specific Reactor—High Density Plasma (HDP):

Biased RF power supplies draw an ion flux toward a surface for material treatment. During transients, it is desired to have this ion flux be repeatable and reproducible for a controlled material removal rate. For high-density plasma sources, plasma generation is independent of ion energy levels. The high-speed electronic tuning devices disclosed herein couple and maintain load impedance closer to design objectives of a power supply, which prevents large power gradients that impose power drop outs and power swings. Faster tuning actuators also enable controllable RF power delivery during mode transitions between electric field coupling to magnetic field coupling, which increases the operational process space for the reactor to serve wider thin-film manufacturing processes.

A Second Specific Reactor—Capacitively-Coupled Plasma (CCP):

The electronic variable devices and actuators disclosed herein benefit CCP bias similarly to the benefits of a HDP source with one notable subtly. The source RF power supply responsible for plasma generation is not nearly as independent in the case for HDP. For this reason, control of the RF power responsible for plasma generation is needed to maintain a collisionless sheath. Applying fast tuning solid-state actuators to a CCP reactor benefits selectivity associated with ion energy levels, sheath performance as it relates to plasma density, and stabilization of the RF power delivery to ameliorate plasma parameters for highly reactive plasma sources.

A Third Specific Reactor—a Cold Atmospheric Plasma Source (CAPS):

Stability of RF power delivery in atmospheric plasma sources are a significant challenge. The challenges are associated with the requirements of the plasma application and the variability of the plasma source. The plasma source has near term and long term time constants associated with the ignition and gradual evolution toward a steady-state condition. Post ignition, many factors contribute to variability that must be countered to deliver a repeatable plasma source to the application. Coupling this type of plasma source with high-speed solid-state tuning actuators accelerates the adoption of many applications associated with CAPS.

Although the terms first, second, third, etc. may be used herein to describe various elements, components, loops, circuits, and/or modules, these elements, components, loops, circuits, and/or modules should not be limited by these terms. These terms may be only used to distinguish one element, component, loop, circuit or module from another element, component, loop, circuit or module. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, loop, circuit or module discussed below could be termed a second element, component, loop, circuit or module without departing from the teachings of the example implementations disclosed herein.

In this application, apparatus elements described as having particular attributes or performing particular operations are specifically configured to have those particular attributes and perform those particular operations. Specifically, a description of an element to perform an action means that the element is configured to perform the action. The configuration of an element may include programming of the element, such as by encoding instructions on a non-transitory, tangible computer-readable medium associated with the element.