SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME

A semiconductor device includes a first semiconductor structure that includes a first substrate, circuit devices on the first substrate, a lower interconnection structure, and a lower bonding structure; and a second semiconductor structure disposed on and connected to the first semiconductor structure The second semiconductor structure includes a stack structure; channel structures that including a first portion that penetrate through the stack structure in the vertical direction and a second portion that extends upward from the first portion; a first material layer disposed on the stack structure and the channel structure and having first conductivity; and a second material layer disposed between the first material layer and the stack structure and having second conductivity., The first material layer overlaps second portions of the channel structures in the vertical direction, and the second material layer does not overlap the second portions of the channel structures in the vertical direction.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 U.S.C. 119 (a) from Korean Patent Application No. 10-2023-0108420, filed on Aug. 18, 2023 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments of the present disclosure are directed to a semiconductor device and a data storage system that includes the same.

DISCUSSION OF THE RELATED ART

A semiconductor device should be able to store high-capacity data in a data storage system. Accordingly, a method for increasing data storage capacity of a semiconductor device has been researched. For example, as a method for increasing data storage capacity of a semiconductor device, a semiconductor device that includes memory cells disposed three-dimensionally, instead of memory cells disposed two-dimensionally, has been suggested.

SUMMARY

An embodiment of the present disclosure provides a semiconductor device that has increased electrical properties and reliability and that can be easily manufactured.

An embodiment of the present disclosure provides a data storage system that includes a semiconductor device that has increased electrical properties and reliability and that can be easily manufactured.

According to an embodiment of the present disclosure, a semiconductor device includes a first semiconductor structure that includes a first substrate, circuit devices disposed on the first substrate, a lower interconnection structure that is electrically connected to the circuit devices, and a lower bonding structure connected to the lower interconnection structure; and a second semiconductor structure disposed on and connected to the first semiconductor structure. The second semiconductor structure includes a stack structure that includes interlayer insulating layers and gate electrodes stacked in a vertical direction; channel structures that each include a first portion that penetrates through the stack structure in the vertical direction and a second portion that extending upward from the first portion; an upper interconnection structure disposed below the stack structures; an upper bonding structure connected to the upper interconnection structure and bonded to the lower bonding structure; a first material layer disposed on the stack structure and the channel structure and that has a first conductivity; and a second material layer disposed between the first material layer and the stack structure and that has a second conductivity that differs from the first conductivity. The first material layer overlaps the second portion of the channel structures in the vertical direction, and the second material layer does not overlap the second portion of the channel structures in the vertical direction.

According to an embodiment of the present disclosure, a semiconductor device includes a stack structure that includes interlayer insulating layers and gate electrodes stacked in a vertical direction; a first material layer disposed on the stack structure and that includes a first semiconductor material that has a first conductivity; a second material layer disposed between the first material layer and the stack structure and that includes a second semiconductor material that has a second conductivity that differs from the first conductivity; a channel structure that includes a first portion that penetrates through the stack structure in the vertical direction, and a second portion that extends upward from the first portion, penetrates through the second material layer, and is disposed below the first material layer; and a buffer layer disposed between the second portion of the channel structures and the second material layer, and between the second portion of the channel structures and the first material layer.

According to an embodiment of the present disclosure, a data storage system includes a semiconductor storage device that includes a first semiconductor structure that includes a substrate and circuit devices disposed on the substrate; a second semiconductor structure that includes a stack structure that includes interlayer insulating layers and gate electrodes stacked in a vertical direction and channel structures that penetrate through the stack structure; and input/output pad electrically connected to the circuit devices; and a controller that is electrically connected to the semiconductor storage device through the input/output pad and that controls the semiconductor storage device. The first semiconductor structure further includes a lower interconnection structure that is electrically connected to the circuit devices; and a lower bonding structure connected to the lower interconnection structure. The second semiconductor structure includes an upper interconnection structure disposed below the stack structure; an upper bonding structure connected to the upper interconnection structure and bonded to the lower bonding structure; a first material layer disposed on the stack structure and the channel structure and that has a first conductivity; and a second material layer disposed between the first material layer and the stack structure and that has a second conductivity that differs from the first conductivity. Each of the channel structures includes a first portion that penetrates through the stack structure in the vertical direction and a second portion that extends upward from the first portion, where the first material layer overlaps second portion of the channel structures in the vertical direction, and the second material layer does not overlap the second portion of the channel structures in the vertical direction.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

FIG.1is an exploded perspective view of a semiconductor device according to an embodiment.

Referring toFIG.1, a semiconductor device100according to embodiments includes a peripheral circuit region PERI and a memory cell region CELL stacked in the vertical direction Z. The peripheral circuit region PERI and memory cell region CELL are bonded and coupled to each other. The memory cell region CELL includes a memory region MA that includes a memory cell array region MCA and a connection region CA, and an external side region OA disposed on an side of the memory region MA. A conductive pad300, which is an input/output pad, is disposed on the external side region OA. A plurality of memory regions MA that include the memory cell array region MCA and the connection region CA are disposed.

The peripheral circuit region PERI includes a raw decoder DEC, a page buffer PB and a peripheral circuit PC. In the peripheral circuit region PERI, the raw decoder DEC generates driving signals for a wordline by decoding an input address and transmits the signals. The page buffer PB is connected to the memory cell array region MCA through bitlines, and reads data stored in memory cells. The peripheral circuit PC includes a control logic and a voltage generator, and may include, for example, a latch circuit, a cache circuit, and/or a sense amplifier. The peripheral circuit region PERI further includes a pad region, and the pad region includes an electrostatic discharge (ESD) device or a data input/output circuit. The ESD element or data input/output circuit of the pad region are electrically connected to the conductive pad300of the external side region PA. The various circuit regions DEC, PB, and PC in the peripheral circuit region PERI may be disposed in various forms.

Hereinafter, an example of the semiconductor device100will be described in greater detail with reference toFIGS.2A to3C.

FIGS.2A to2Care plan views that illustrate a semiconductor device according to an embodiment, andFIG.2Bis an enlarged view of region “A” inFIG.2A.

FIGS.3A to3Care cross-sectional views of a semiconductor device according to an embodiment,FIGS.3A and3Bare cross-sectional views taken along cutting lines I-I′ and II-II′ ofFIG.2A, respectively, andFIG.3Cis an enlarged view of region “B” inFIG.3A.

InFIG.2A, a first region R1correspond to the memory cell array region MCA illustrated inFIG.1, and a second region R2may correspond to the connection region CA illustrated inFIG.1.

Referring toFIGS.3A and3B, in an embodiment, the semiconductor device100includes a peripheral circuit region PERI and a memory cell region CELL. The memory cell region CELL is disposed on the peripheral circuit region PERI. The peripheral circuit region PERI and the memory cell region CELL are bonded to each other through bonding structures180and280. The peripheral circuit region PERI may be referred to as the first semiconductor structure S1, and the memory cell region CELL may be referred to as the second semiconductor structure S2.

The peripheral circuit region PERI includes a first substrate101, circuit devices120on the first substrate101, a lower interconnection structure130, a lower bonding structure180, and a lower capping layer190.

The first substrate101includes a semiconductor material, such as one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate101may be provided as a bulk wafer or an epitaxial layer. In the first substrate101, an active region is defined by device isolation layers. Source/drain regions128that include impurities are disposed in a portion of the active region.

The circuit devices120includes a transistor. Each of the circuit devices120includes a circuit gate dielectric layer122, a circuit gate electrode124, and a source/drain region128. The source/drain regions128include impurities and are disposed in the first substrate101on both sides of the circuit gate electrode124. Spacer layers126are disposed on both sides of the circuit gate electrode124. The circuit gate dielectric layer122includes at least one of silicon oxide, silicon nitride, or a high-k material. The circuit gate electrode124includes at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), or ruthenium (Ru). For example, the circuit gate electrode124includes a doped polycrystalline silicon layer. According to an embodiment, the circuit gate electrode124includes two or more multiple layers.

The lower interconnection structure130is electrically connected to the circuit gate electrodes124and the source/drain regions128of the circuit devices120. The lower interconnection structure130includes lower contact plugs135and lower interconnection lines137in which at least one region has a line shape. A portion of lower contact plugs135are connected to the source/drain regions128and the other portion of lower contact plugs135are connected to the gate electrodes124. The lower contact plugs135electrically connect the lower interconnection lines137disposed on different levels from the upper surface of the first substrate101to each other. The lower interconnection structure130includes a conductive material, such as at least one of tungsten (W), copper (Cu), or aluminum (Al), etc., and each component further includes a diffusion barrier that includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). In embodiments, the number of layers and the arrangement form of the lower contact plugs135and the lower interconnection lines137in the lower interconnection structure130can vary.

The lower bonding structure180is connected to the lower interconnection structure130. The lower bonding structure180includes a lower bonding via182, a lower bonding pad184, and a lower bonding insulating layer186. The lower bonding via182is connected to the lower interconnection structure130. The lower bonding pad184is connected to the lower bonding via182. The lower bonding via182and the lower bonding pad184include conductive materials, such as at least one of tungsten (W), copper (Cu), or aluminum (Al), etc., and each component further includes a diffusion barrier. The lower bonding insulating layer186also functions as a diffusion barrier of the lower bonding pad184and includes at least one of SiCN, SiO, SIN, SiOC, SiON or SiOCN. The lower bonding insulating layer186has a thickness that is less than a thickness of the lower bonding pad184, but an embodiment thereof is not necessarily limited thereto. The lower bonding structure180is in direct contact with and bonded or connected to the upper bonding structure280by hybrid bonding. For example, the lower bonding pad184is in direct contact with and coupled to the upper bonding pad284by copper-to-copper bonding (copper (Cu)-copper (Cu) bonding), and the lower bonding insulating layer186is in direct contact with and coupled to the upper bonding insulating layer286by dielectric-to-dielectric bonding. The lower bonding structure180, together with the upper bonding structure280, provide an electrical connection path between the peripheral circuit region PERI and the memory cell region CELL.

The lower capping layer190is disposed on the first substrate101and covers the circuit devices120and the lower interconnection structure130. The lower capping layer190may include a plurality of insulating layers. The lower capping layer190includes an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

The memory cell region CELL includes a first material layer203that includes a first region R1, a second material layer202on the lower surface of the first material layer203, a buffer layer201on the lower surface of the second material layer202, gate electrodes230stacked on the lower surface of the buffer layer201and that include the first region R1and the second region R2, interlayer insulating layers220alternately stacked with the gate electrodes230, channel structures CH that penetrate through the gate electrodes230, isolation regions MS that extend in one direction through the gate electrodes230, and first insulating regions GS that penetrate through a portion of the gate electrodes230. The memory cell region CELL includes a horizontal insulating layer219A parallel with and adjacent to the first and second material layers203and202in the second region R2, a passivation layer219B disposed on the first material layer203, second insulating regions SS that53apenetrate through a portion of the gate electrodes230, and an upper capping layer290that covers the gate electrodes230. The interlayer insulating layers220alternately stacked with the gate electrodes230form a stack structure ST.

The memory cell region CELL includes gate contact plugs252that are electrically connected with the peripheral circuit region PERI, an upper interconnection structure270below the stack structure ST, and an upper bonding structure280connected to the upper interconnection structure270.

The memory cell region CELL furthers include dummy vertical structures DVH, gate contact plugs252, and a substrate contact via267on the body interconnection254in the second region R2.

As illustrated inFIG.3A, in the first region R1, the gate electrodes230are stacked and spaced apart from each other in a vertical direction, for example, the Z-direction, and the channel structures CH are disposed. As illustrated inFIG.3A, in the second region R2, the gate electrodes230have different lengths in the X-direction such that contact pads that electrically connect the memory cells to the peripheral circuit region PERI are provided. Also, in the second region R2, a source interconnection253and a body interconnection254may be disposed. The second region R2further includes a region that extends from a side end of the gate electrodes230to an edge of the semiconductor device100. For example, the second region R2further includes a region in which the conductive pad300is disposed. The second region R2extends in at least in one direction, for example, from at least one end of the first region R1in the X-direction.

The first region R1and second region R2include regions both below and above the passivation layer219B, including the passivation layer219B.

Referring toFIG.3C, each of the channel structures CH includes a filling insulating layer247, a channel layer240on a side surface and an upper surface of the filling insulating layer247, and a data storage structure245between the outer side surface of the channel layer240and the stack structure ST. The data storage structure245includes a tunneling layer241, a data storage layer242, and a blocking layer243that are sequentially stacked from the channel layer240. The tunneling layer241tunnels electric charges into the charge storage layer242and includes, for example, at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The data storage layer242is a material layer that can store data. For example, the data storage layer242may be configured as an electric charge trap layer or a floating gate conductive layer. The blocking layer243includes at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-K material, or a combination thereof.

As illustrated in the enlarged view inFIG.3C, each of the channel structures CH includes a first portion in the stack structure ST and a second portion that upwardly protrudes above the stack structure ST. The channel layer240is disposed entirely in the first and second portions of the channel structure CH, and extends up to the upper end of the second portion. The channel layer240includes a protrusion240athat upwardly protrudes above the stack structure in the second portion and a non-protruding portion240bdisposed in the stack structure ST and the first portion of the channel structure CH.

The first material layer203has a first conductivity. For example, the first material layer203includes a first semiconductor material that has a P-type conductivity. For example, the first material layer203includes a doped semiconductor material, such as one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor includes one of silicon, germanium, or silicon-germanium. For example, the first material layer203includes a silicon layer, such as a silicon layer that has a P-type conductivity. For example, the first material layer203is a crystalline semiconductor layer such as one of a single crystalline silicon layer, a polycrystalline silicon layer, or an epitaxial layer. The first material layer203functions as a body selection line (BSL) that provides an erase voltage during an erase operation in first region R1. As illustrated in the enlarged view inFIG.3C, the first material layer203overlaps the channel structures CH in the Z-direction, and at least a portion of channel structures CH, such as an end and a portion of a side surface adjacent to the end of channel structures CH, is electrically connected through the buffer layer201.

The second material layer202is disposed between a lower surface of the first material layer203and the stack structure ST in the first region R1. The second material layer202has a second conductivity that differs from the first conductivity. For example, the second material layer202includes a second semiconductor material that has an N-type conductivity. For example, the second material layer202includes a doped semiconductor material, such as one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor includes one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The second material layer202functions as a common source line (CSL) of the semiconductor device100. For example, the second material layer202includes a silicon layer, such as a silicon layer that has N-type conductivity. For example, the second material layer202is provided as a crystalline semiconductor layer or an epitaxial layer, such as a single crystal silicon layer or a polycrystalline silicon layer doped with second conductivity-type impurities that differ from that of the first material layer203. As illustrated in the enlarged view inFIG.3C, the second material layer202includes openings2020through which the channel structures CH penetrate, and the openings2020surround the side surface of the second portions of the channel structures CH, that is, the side surface of the protrusion240A of the channel layer240. Accordingly, the second material layer202does not overlap the channel structure CH in the Z-direction. The second material layer202surrounds one region of the protrusion240A of the channel structure CH, such as a portion of the side surface, and is electrically connected to the channel layer240through the buffer layer201. The buffer layer201is disposed below the second material layer202.

The buffer layer201includes a semiconductor material, such as one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor includes one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). According to an embodiment, the buffer layer201conformally covers the channel structures CH, but an embodiment thereof is not necessarily limited thereto.

The buffer layer201includes a silicon layer. For example, the buffer layer201is one of an undoped single crystalline silicon layer, an undoped crystalline semiconductor layer such as an undoped polycrystalline silicon layer, or an undoped epitaxial layer.

The buffer layer201is interposed between the second material layer202and the stack structure ST, between the second material layer202and the second portions of the channel structures CH, and between the first material layer203and the second portions of the channel structures CH. The buffer layer201is in contact with the second material layer202, and is in contact with the first material layer203in a portion of regions and is selectively electrically connected with the channel layer240of the channel structure CH and the first material layer203or the second material layer202.

The first material layer203, the second material layer202and the buffer layer201are sequentially stacked in the first region RI and in the boundary regions between the first region R and the second region R2. For example, the first material layer203, the second material layer202and the buffer layer201do not extend through the entire second region R2, and extend only to the first region R1and a portion of the second region R2adjacent to the first region R1in the X-direction. For example, the first material layer203, the second material layer202and the buffer layer201extend to the first region R1and a boundary region of the second region R2, where a source interconnection253and the body interconnection254electrically connected to the common source line and the body selection line.

In the first region R1and the boundary region of the second region R2, the second material layer202extends further from the first material layer203toward the second region R2. In the extended region of the second material layer202, the second material layer202is connected to the upper source interconnection253, and the source interconnection253does not overlap the first material layer203in the Z-direction.

The memory cell region CELL further includes an upper conductive layer204in contact with the first material layer203and disposed on the first material layer203. The upper conductive layer204is a conductive layer in contact with the first material layer203. The upper conductive layer204includes at least one of a metal-semiconductor compound, a metal-nitride, or a metal, such as tungsten (W), copper (Cu), or aluminum (Al).

The upper conductive layer204is vertically aligned with the first material layer203. The memory cell region CELL further includes a body contact via268on the upper conductive layer204and the body interconnection254on the body contact via268.

The first material layer203and the second material layer202do not extend to the second region R2, but the buffer layer201does extend to the second region R2, but an embodiment thereof is not limited.

The first material layer203, the second material layer202and the buffer layer201include a semiconductor material and, for example, include crystalline silicon.

The first material layer203is doped with first conductivity-type impurities, the second material layer202is doped with second conductivity-type impurities that differs from the first conductivity, and a portion of the buffer layer201becomes conductive as first and second conductivity-type impurities diffuse downward, and the remaining portion of the buffer layer201is an undoped semiconductor layer.

For example, the first material layer203is a polycrystalline silicon layer doped with P-type impurities, the second material layer202is a polycrystalline silicon layer doped with N-type impurities, and the buffer layer201is an undoped polycrystalline silicon layer.

The horizontal insulating layer219ais disposed parallel to the first material layer203and the second material layer202in at least a portion of the second region R2. The horizontal insulating layer219ais a multilayer structure in the second region R2. For example, a portion of the multilayer structure is undoped crystalline silicon that is simultaneously formed with the buffer layer201, and includes at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. For example, the horizontal insulating layer219aincludes a lower horizontal insulating layer and an upper horizontal insulating layer that include different insulating materials.

The gate electrodes230are vertically stacked and spaced apart from each other on the lower surface of the horizontal insulating layer219aand the buffer layer201and form the stack structure ST along with the interlayer insulating layers220. The stack structure ST includes vertically stacked lower and upper stack structures. However, in embodiments, the stack structure includes a single stack structure.

The gate electrodes230include at least one lower gate electrode230L that forms the gate of the ground selection transistor, memory gate electrodes230M that form the plurality of memory cells, and upper gate electrodes230U that forms the gates of the string selection transistors. In the terms “the lower gate electrode230L and the upper gate electrodes230U”, “lower” and “upper” refer to a direction during a manufacturing process. The number of memory gate electrodes230M that form the memory cells is determined by a capacity of the semiconductor device100. In embodiments, the number of the upper gate electrodes230U and the number of the lower gate electrodes230L is one to two or more, and have a structure the same as or different from the memory gate electrodes230M. In an embodiment, erase gate electrodes are further disposed below the upper gate electrodes230U, but in an embodiment in which a bulk erase operation is performed, an erase operation is performed without the erase gate electrodes. In addition, a portion of the gate electrodes230, such as the memory gate electrodes230M adjacent to the upper or lower gate electrodes230U and230L, may be dummy gate electrodes, but an embodiment thereof is not necessarily limited thereto.

The gate electrodes230are vertically stacked and spaced apart from each other on the lower surface of the horizontal insulating layer219A and the buffer layer201, extend with different lengths in at least one direction and form a step structure with a staircase shape. The gate electrodes230form a step structure in the X-direction as illustrated inFIG.3A, and form a step structure in the Y-direction as well. Due to the step structure, the ends of the gate electrodes230are exposed. The gate electrodes230are connected to gate contact plugs252in the second region R2.

The gate electrodes230include a metal, such as tungsten (W). In embodiments, the gate electrodes230include polycrystalline silicon or a metal silicide. In embodiments, the gate electrodes230further include a diffusion barrier. For example, the diffusion barrier includes at least one of tungsten nitride (wN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

At least a portion of the gate electrodes230is isolated by isolation regions MS in the Y-direction. The isolation regions MS penetrate through the gate electrodes230and extend in the Z-direction in the memory cell array region MCA and connection region CA. The isolation regions MS extend in the X-direction and isolate the gate electrodes230from each other in the Y-direction. The isolation regions MS are spaced apart from each other in the Y-direction and are parallel to each other. The gate electrodes230between a pair of adjacent isolation regions MS form a memory block, but the range of the memory block is not necessarily limited thereto. A width of the isolation region MS decreases toward the horizontal insulating layer219A and the buffer layer201, but an embodiment thereof is not necessarily limited thereto. An isolation insulating layer264is disposed in the isolation regions MS. In embodiments, in the isolation regions MS, a conductive layer is further disposed in the isolation insulating layer264. The isolation insulating layer264includes an insulating material such as silicon oxide or silicon nitride, such as one of silicon oxide, silicon nitride, or silicon oxynitride. In embodiments, the arrangement order and the number of the isolation regions MS are not necessarily limited to the illustrated examples inFIG.2A.

The interlayer insulating layers220are disposed between the gate electrodes230. Similar to the gate electrodes230, the interlayer insulating layers220are spaced apart from each other in a direction perpendicular to the lower portion of the horizontal insulating layer219A and the buffer layer201, such as a Z-direction, and extend in the X-direction. The interlayer insulating layers220include an insulating material such as silicon oxide or silicon nitride.

The channel structures CH are spaced apart from each other in rows and columns below the lower surface of the first and second material layers203and202in the first region R1. The channel structures CH are disposed in a zigzag pattern in one direction on the X-Y plane, such as the X-direction. The channel structures CH penetrate through the gate electrodes230, extend in a vertical direction perpendicular to the lower surface of the first material layer203, such as the Z-direction, have a pillar shape, and have an inclined side surface and a width that decreases toward the first material layer203.

Each of the channel structures CH includes lower and upper channel structures that respectively penetrate through a lower gate stack group and an upper gate stack group of the gate electrodes230are connected to each other, and may have a bent portion due to a difference or change in width in the connection region.

In an embodiment, protruding lengths of the second portions of the channel structures CH and the protrusions240A of channel layer240might not be the same, but an embodiment thereof is not limited thereto. The channel layer240has an annular side surface that surrounds the internal filling insulating layer247, but in other embodiments, the channel layer240has a pillar shape, such as a cylindrical shape or a prism shape, without a filling insulating layer247. The protrusion240A of the channel layer240is in contact with the second material layer202and the first material layer203with the buffer layer201interposed therebetween. The protrusion240A of the channel layer240is connected to the buffer layer201. The channel layer240includes a semiconductor material such as one of a polycrystalline silicon or a single crystal silicon, and the semiconductor material may be an undoped material or a material including P-type or N-type impurities. According to an embodiment, at least a portion of the side surface of the protrusion240A of the channel layer240is spaced apart from the second material layer202with the buffer layer201therebetween, and an upper end portion and at least a portion of the side surface adjacent to the upper end portion are spaced apart from the first material layer203with the buffer layer201therebetween. Accordingly, the protrusion240A of the channel layer240overlaps the first material layer203in the Z-direction, but does not overlap the second material layer202in the Z-direction.

Accordingly, when an appropriate voltage level is applied to each material layer203and202, the first material layer203or the second material layer202electrically connects to the channel layer240through the buffer layer201.

Accordingly, the height of the second portion of the channel structure CH, that is, the height of protrusion240A, is greater than the sum of the thicknesses of the buffer layer201and the second material layer202, and the height of protrusion240A of the channel layer240is defined as the length from the upper surface of the data storage structure245to an upper end of the channel layer240. Accordingly, the upper surfaces of the second portions of the channel structures CH are located at a higher level than the upper surface of the second material layer202, and the protrusion240A protrudes above the upper surface of the second material layer202by a predetermined height h1. For example, the protrusion240A has a slope with the non-protruding portion240B to maintain the annular shape, as illustrated inFIG.3C.

For example, in the protrusion240A, as the channel layer240is in contact with the first material layer203and the second material layer202and the buffer layer201, depending on the voltage applied to the first material layer203or the second material layer202, the channel layer240is selectively electrically connected to one of the specific material layers203and202and a current can flow therethrough.

The second material layer202is a common source. To perform an erase operation in which electrons trapped in the data storage layer242in the data storage structure245escape into the channel layer240, an erase voltage is applied to the first material layer203, holes flow from the first material layer203into the channel layer240through the buffer layer201, and the erase operation in which electrons trapped in the data storage layer242may escape into the channel layer240is performed.

For example, the second material layer202doped with N-type impurities and the first material layer203doped with P-type impurities are simultaneously connected to the protrusion240A of the channel layer240, and can be selectively electrically connected depending on the applied voltage, such that the required operation can be performed.

For example, since a bulk erase operation can be performed, an erase operation can be performed at a faster speed than performing the erase operation of the channel layer240using a general erase transistor GIDL TR using gate-drain leakage current, and by operating without an erase transistor, a relatively fast operation speed may be secured.

In an embodiment, the channel structure CH further includes a head240C that has an expanded width on one end in the second region as illustrated inFIG.4A.

In an embodiment illustrated inFIG.4A, a head240C of the channel structure CH has a width w5that is greater than a width w6of the first portion of the channel structure CH. The head240C of the channel structure CH is a stopper that maintains the depth of the channel hole uniformly during the manufacturing process, but an embodiment thereof is not necessarily limited thereto.

The head240C may have different widths w5in Z-direction. For example, the head240C has a width w5that decreases upwardly, but an embodiment thereof is not necessarily limited thereto, and in some embodiments, the upper and lower widths of the head240C are the same. For example, the width w5on the smallest head240C is greater than the width w6of the first portion of the channel structure CH.

For example, the width w5of head240C is about ½ to ⅗ of the spacing distance between neighboring channel structures CH.

For example, when the spacing distance between neighboring channel structures CH is about 140 nm to 150 nm, the width w5of head240C is about 70 nm to 85 nm. The width w6of the first portion of the channel structure CH is about 59 nm to 61 nm, or about 60 nm.

Even when the head240C is formed, the stack structure of the second region of the channel structures CH is the same as inFIG.3C, and the height of the protrusion240A is greater than the sum of the thicknesses of the buffer layer201and the second material layer202. Accordingly, the head240C protrudes above the upper surface of the second material layer202by a predetermined height h1. The shape of the head240C is determined by the filling insulating layer247.

For example, when the head240C of the protrusion240A is formed, the contact area between the first material layer203and the channel layer240is expanded by the surface area of the head240C, thereby increasing the amount of inflow of holes during a bulk erase operation.

As illustrated inFIG.4B, in an embodiment, in a portion of the channel protrusion240A, such as a region close to the upper end thereof, the filling insulating layer247is not formed, and a pad pattern246that includes a polycrystalline semiconductor layer that is the same as the channel layer240is formed. Accordingly, each of the channel structures CH further includes a pad pattern246connected to the channel layer240. The pad pattern246includes an undoped semiconductor, such as undoped silicon.

The height of the protrusion240A is greater than the sum of the thicknesses of the buffer layer201and the second material layer202. Accordingly, the upper surface of the protrusion240A protrudes above the upper surface of the second material layer202by a predetermined height h1and has a higher level.

In another embodiment, as illustrated inFIG.4C, the channel structure CH further includes a head240C having an extended width w5on an end of the second portion. The head240C has the same shape as that shown inFIG.4A. The height of the protrusion240A is greater than the sum of the thicknesses of the buffer layer201and the second material layer202. Accordingly, the head240C of the protrusion240A protrudes above the upper surface of the second material layer202by a predetermined height h1.

The region of the protrusion240A that extends from the head240C of the protrusion240A has a pad pattern246as illustrated inFIG.4Bin which the filling insulating layer247is not formed. Accordingly, the head240C, which is a pad pattern, includes an undoped semiconductor, such as undoped silicon.

In the channel structures CH, channel pads249are disposed in a lower portion of the channel layer240. The channel pads249cover the lower surface of the filling insulating layer247and are electrically connected to the channel layer240. The channel pads249include, for example, doped polycrystalline silicon.

The data storage structure245is disposed between the gate electrodes230and the channel layer240. The data storage structure245includes the tunneling layer241, the charge storage layer242, and the blocking layer243that are sequentially stacked from the channel layer240. In embodiments, at least a portion of the data storage structure245forms a first channel dielectric layer that extends horizontally along the gate electrodes230.

The data storage structure245is removed from the upper portion of the stack structure such that the protrusion240A of the channel layer240in the second portion is exposed. Accordingly, the upper surface of the data storage structure245is in contact with the buffer layer201, and the side surface of the data storage structure245in the first portion surrounds the non-protruding portion240B of the channel layer240.

The channel layer240, the gate dielectric layer245, and the filling insulating layer247are connected to each other between the upper channel structure and the lower channel structure. An interlayer insulating layer220that has a relatively great thickness is further disposed between the upper channel structure and the lower channel structure. However, the form of the interlayer insulating layers220varies in other embodiments.

The dummy vertical structures DVH are disposed in the second region R2and have a structure that is the same as or similar to the channel structures CH, but do not perform a practical function in the semiconductor device100. The dummy vertical structures DVH are disposed regularly in columns and rows in the second region R2. The dummy vertical structures DVH has a diameter that is greater than a maximum diameter of the gate contact plugs252. The shape, the number and/or the spacing of dummy vertical structures DVH can vary. The channel structures CH and the dummy vertical structures DVH may have a substantially circular shape in a plan view, but an embodiment thereof is not necessarily limited thereto, and in some embodiments, the channel structures CH and the dummy vertical structures DVH have an oval shape. The dummy vertical structures DVH prevent deformation such as warpage of the stack structure ST.

Each of the gate contact plugs252has a cylindrical shape or a truncated cone shape, and a width thereof decreases upwardly. The gate contact plugs252penetrate through a portion of the cell region insulating layer290. A plurality of the gate contact plugs252are disposed and are spaced apart from each other.

The gate contact plugs252are disposed in the second region R2and extend in a vertical direction, such as the Z-direction. The gate contact plugs252are connected to ends or contact pads according to the staircase shape of the gate electrodes230. The gate contact plugs252are connected to the upper interconnection structure270in a lower portion.

The second semiconductor structure S2further includes conductive patterns253and254spaced apart from each other on the first material layer203and in the passivation layer219bin the boundary region between first region R1and second region R2, and a plurality of vias267,268in contact with the conductive patterns253and254. The conductive patterns253and254include source interconnections253that overlap the second material layer202and body interconnections254that overlap the first material layer203.

The plurality of vias include source contact vias267disposed between the source interconnections253and the second material layer202and body contact vias268disposed between the body interconnection254and upper conductive layer204.

The plurality of source contact vias267penetrate through the passivation layer219band the horizontal insulating layer219aand are in contact with the second material layer202and the source interconnection253.

The plurality of body contact vias268penetrate through the passivation layer219band are in contact with the upper conductive layer204and the body interconnection254.

As illustrated inFIG.2C, the body interconnection254and the source interconnection253are disposed on the dummy channel structure DVH. The components are formed on the dummy channel structure DVH of the second region R2, and the first material layer203, the second material layer202, and the buffer layer201extend into the second region R2. In the example inFIG.2C, the regions of the body interconnection254and the source interconnection253does not extend further into the second region R2in the X-direction.

The isolation regions MS penetrate through the gate electrodes230and extend in the X-direction. The isolation regions MS extend parallel to each other. The isolation regions MS penetrate through the entirety of the gate electrodes230stacked on the buffer layer201and the horizontal insulating layer219a,and may be connected to the buffer layer201and the horizontal insulating layer219a.Each of the isolation regions MS is an integrated layer that extends in the X-direction. A sub-isolation region that extends intermittently between the isolation regions may be formed, but an embodiment thereof is not necessarily limited thereto.

As illustrated inFIG.3B, in an embodiment, the isolation insulating layer264is disposed in the isolation regions MS. The isolation insulating layer264has a shape whose width decreases toward the buffer layer201and the horizontal insulating layer219A, but an embodiment thereof is not necessarily limited thereto. In some embodiments, a conductive layer is further disposed in the isolation insulating layer264. For example, the conductive layer functions as a contact plug connected to the common source line and the body selection line of the semiconductor device100.

The first insulating regions GS extend from the upper surface of the first material layer203, and penetrate through the first and second material layer202, the buffer layer201or the horizontal insulating layer219a,the lower gate electrodes230L, and a portion of the interlayer insulating layers220.

At least one first insulating region GS is disposed higher than a level of the intermediate memory gate electrodes230M and penetrates through the lower gate electrodes230L in the vertical direction. As illustrated inFIG.2A, the first insulating regions GS extends in the X-direction through the first region R1and the second region R2in a plan view. The first insulating regions GS have a wavy shape that extends in the X-direction, for example, a shape that oscillates in the X-Y plane and is continuously bent, such as a wave pattern shape.

Due to this shape, the lower gate electrodes230L are isolated or divided into disposed in a row in the X-direction.

The above embodiment will be described in greater detail with reference toFIG.5below.

As illustrated inFIG.2B, in an embodiment, the first insulating regions GS form a plurality of regions between two isolation regions MS spaced apart from each other in the Y-direction.

The first insulating regions GS form two to three regions between two adjacent isolation regions MS, and the ground selection gate electrode, which is the lower gate electrode230L, may be divided depending on the vertical extension of the first insulating regions GS.

Each first insulating region GS extends in the X-direction in a wavy shape, and an extension direction thereof has a same length in the X-direction as the isolation region MS.

The wavy shape of the first insulating region GS is disposed between the plurality of channel structures CH in the plan view.

As illustrated inFIG.2B, when the plurality of channel structures CH are disposed a zigzag pattern in the X-Y plane, the first insulating region GS has a wavy shape to continuously pass between the channel structures CH arranged in a zigzag pattern.

Each first insulating region GS has the same width w1in the X-Y plane, but an embodiment thereof is not necessarily limited thereto, and as the width w1decreases toward the channel structure CH, the first insulating region GS is spaced apart from the channel structure CH by a predetermined distance d1or more.

Accordingly, the first insulating region GS has a smaller structure in a mountain n1and a valley n2, but an embodiment thereof is not necessarily limited thereto.

In addition, a width w4of a two-row channel structure CH that extends in the X-direction is greater than a width w3of the path of the first insulating region GS. Accordingly, the path of the first insulating region GS is bent in the region between the two rows of channel structures CH, such that the first insulating region GS does not contact the channel structures CH.

In addition, a distance d3between two channel structures CH between which the first insulating region GS passes, that is, the distance d3between the central points O1and O3of the center of the channel structures CH and the distance d2between two channel structures CH between which the first insulating region GS does not pass is the same as the distance d3.

Accordingly, even when the first insulating region GS extends between the channel structures CH, the spacing distances d2and d3between the channel structures CH is not widened and the arrangement between the channel structures CH is not changed. In addition, since the first insulating region GS extends between the isolation regions MS, an additional isolation region MS is not disposed between the isolation regions MS. Accordingly, a density of the channel structure CH is increased, and no dummy channel structure DVH are formed in the first insulating regions GS. Accordingly, cell capacity in the same area is increased, such that memory capacity can be secured.

The first insulating layer206is disposed in the first insulating region GS. The first insulating layer206includes an insulating material, such as one of silicon oxide, silicon nitride, or silicon oxynitride.

As illustrated inFIG.3B, the first insulating region GS has inclined side surfaces such that a width thereof decreases toward the first substrate structure S1. The first insulating region GS has side surfaces inclined or tapered in an opposite direction from the channel structures CH, the isolation regions MS, the upper interconnection structure270, and the upper bonding structure280. The first insulating region GS is wider in an upper portion than in a lower portion.

The first insulating region GS completely penetrates through the lower gate electrodes230L from the first material layer203, and a lower end thereof is disposed in the interlayer insulating layer220below the lower gate electrodes230L. For example, with respect to the memory gate electrodes230M, when the upper gate electrodes230are referred to as lower gate electrodes230L and the lower gate electrodes230are referred to as upper gate electrodes230U, the first insulating region GS penetrates at least a portion of the lower gate electrodes230L.

The lower gate electrode230L penetrated by the first insulating region GS are exposed by the first insulating region GS and are in direct contact with the first insulating layer206. In addition, the side surfaces of gate dielectric layers on the upper and lower surfaces of the lower gate electrode230L are exposed through the first insulating region GS and are in direct contact with the first insulating layer206. That is, in the gate electrodes230, the side surface that opposes the channel structure CH is covered with gate dielectric layers as illustrated inFIG.3C, and the side surface that opposes the first insulating region GS is not covered with gate dielectric layers as illustrated inFIG.3B. This is because the first insulating region GS is formed after the gate dielectric layers and the gate electrodes230are formed. In addition, the gate electrodes230below the first insulating region GS including the memory gate electrodes230M and have flat upper and lower surfaces and extend to a region below the first insulating region GS.

In an embodiment, the first insulating region GS is formed from the upper surface of the first material layer203after the first and second substrate structures S1and S2are bonded to each other. Accordingly, since the shape of the gate electrodes230is not affected by the first insulating region GS, the gate electrodes230have flat upper and lower surfaces below the first insulating region GS. Accordingly, different from an example in which the first insulating region GS is formed before the gate electrodes230are formed, a seagull-shaped recess is prevented from forming in the gate electrodes230, such that defects of the gate electrodes230due to the recess, such as short circuit defects and leakage current defects, can be prevented.

The second insulating regions SS extend in the X-direction between two isolation regions MS spaced apart from each other in the Y-direction in the first region R1, as illustrated inFIG.2A. The second insulating regions SS have a wavy shape that extends in the X-direction, similar to the first insulating regions GS on the X-Y plane.

The second insulating regions SS penetrate through a portion of the gate electrodes230that includes the lowermost upper gate electrode230U. The second insulating regions SS isolate the upper gate electrodes230U from each other in the Y-direction, as illustrated inFIG.3B. However, the number of gate electrodes230isolated by the second insulating regions SS can vary in embodiments. The upper gate electrodes230U isolated by the second insulating regions SS form different string selection lines. In the second insulating regions SS, the second insulating layer213is disposed. The second insulating layer213includes an insulating material, such as one of silicon oxide, silicon nitride, or silicon oxynitride.

As illustrated inFIG.2B, when the lower gate electrode230L is divided into n number of portions by the first insulating regions GS, the upper gate electrode230U are divided into 2n number of portions by the second insulating regions SS.

The plurality of second insulating regions SS include at least one first-second insulating region SS that overlaps a first insulating region GS in the Z-direction, and a second-second insulating region SS that does not overlap a first insulating region GS in the Z-direction. When two first insulating regions GS are formed between two isolated isolation regions MS, the lower gate electrodes230L are divided into three portions, five second insulating regions SS are formed, and the230U upper gate electrodes are divided into six portions. The width of the second insulating region SS is less than the width of the first insulating region GS, but an embodiment thereof is not necessarily limited thereto.

A extension length in the X-direction of the second insulating region SS is shorter than that of the first insulating region GS in the X-direction.

The upper capping layer290covers the gate electrodes230disposed on the lower surface of the buffer layer201and the horizontal insulating layer219A. The upper capping layer290is formed of an insulating material and may include a plurality of insulating layers.

The passivation layer219bis disposed on the upper surface of the first material layer203. The passivation layer219bprotects the semiconductor device100. In an embodiment, the passivation layer219bhas openings in some regions that define a pad region connected to an external device. The passivation layer219bincludes at least one of silicon oxide, silicon nitride, or silicon carbide.

An etch stop layer221is further disposed above the uppermost interlayer insulating layer220. The etch stop layer221is formed such that only the base substrate is removed in an etching process due to etch selectivity with respect to a sacrificial base substrate. To this end, the etch stop layer221includes a semiconductor material, such as one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor includes one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). According to an embodiment, the etch stop layer221is as an undoped crystalline semiconductor layer, and, for example, is formed of undoped polycrystalline silicon, but an embodiment thereof is not necessarily limited thereto.

When the etch stop layer221is disposed on the uppermost interlayer insulating layer220, the etch stop layer221is disposed throughout the first region RI and the second region R1.

The upper interconnection structure270electrically connects the upper conductive layer204of the gate electrodes230, the channel structures CH, the second material layer202and the first material layer203to the circuit devices120. The upper interconnection structure270includes a channel contact plug271, a gate contact stud272, an upper contact plug275, and an upper interconnection line277. The channel contact plug271is connected to the channel pad249of the channel structure CH. The channel contact plug271is electrically connected to the channel layer240through the channel pad249of the channel structures CH in the memory cell array region MCA. The upper contact plugs275are connected to the channel contact plug271and the gate contact stud272. The gate contact stud272is connected to the gate contact plug252. The upper interconnection line277is connected to the upper contact plug275. The upper interconnection structure270includes a conductive material, such as one of tungsten (W), copper (Cu), or aluminum (Al), etc., and each component further includes a diffusion barrier that includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). In embodiments, the number of the upper contact plugs275and the upper interconnection lines277in the upper interconnection structure270and the arrangement form thereof can vary.

The upper bonding structure280is connected to the upper interconnection structure270. For example, the gate contact stud272and the channel contact plug271are electrically connected to the upper bonding structure280. The upper bonding structure280includes an upper bonding via282, an upper bonding pad284, and an upper bonding insulating layer286. The upper bonding via282is connected to the upper interconnection structure270. The upper bonding pad284is connected to the upper bonding via282. The upper bonding via282and the upper bonding pad284include a conductive material, such as one of tungsten (W), copper (Cu), or aluminum (Al), etc., and each component further includes a diffusion barrier. The upper bonding insulating layer286also functions as a diffusion barrier for the upper bonding pad284and includes at least one of SiCN, SiO, SIN, SiOC, SiON or SiOCN. The upper bonding insulating layer286has a thickness that is less than a thickness of the upper bonding pad284, but an embodiment thereof is not necessarily limited thereto.

FIG.5is an exploded perspective view of gate electrodes of a semiconductor device according to an embodiment.

In an embodiment,FIG.5illustrates a portion of gate electrodes230disposed between a pair of spaced apart isolation regions MS inFIG.2A. InFIG.5, the gate electrodes230are illustrated in a direction opposite to the stacking direction of the gate electrodes230illustrated inFIG.3A.

Of the gate electrodes230, upper gate electrode230U disposed on an uppermost end (the lowermost end inFIG.3A) are used as a string selection line. The upper gate electrode230U is isolated into six sub-upper gate electrodes230Ua,230Ub,230Uc,230SUd,230Ue, and230Uf in the Y-direction by the second insulating regions SS. The sub-upper gate electrodes230Ua,230Ub,230Uc,230Ud,230Ue, and230Uf are connected to different contact plugs, and independently receive electrical signals. For example, of the gate electrodes230, a gate electrode230on an uppermost end corresponds to the upper gate electrode230U, but the number of the upper gate electrodes230U can vary in some embodiments.

The central memory gate electrodes230Mn disposed at a lower portion of the upper gate electrode230U are disposed as a single flat layer without a groove. The lowermost memory gate electrode230M0is also disposed as a single layer without a groove. InFIG.5, only the uppermost memory gate electrode230Mn and the lowermost memory gate electrode230M0are illustrated for convenience of illustration, but similarly, each of the memory gate electrodes230M forms a layer and is disposed without a groove. The memory gate electrodes230Mn are configured as wordlines.

Of the gate electrodes230, the lower gate electrodes230L disposed at a lower portion of the memory gate electrodes230M are used as a body selection line, and are divided into three sub-lower gate electrodes230La,230Lb, and230Lc by the first insulating regions GS. The first insulating regions GS are disposed side by side in the X-direction, and the lower gate electrode230L is completely divided in the Y-direction. The sub-lower gate electrodes230La,230Lb, and230Lc are connected to different contact plugs and independently receive electrical signals. However, in some embodiments, the number of sub-lower gate electrodes230La,230Lb, and230Lc disposed between a pair of adjacent isolation regions MS can vary.

For example, when an off voltage is applied to the lower gate electrode230L, a bulk erase operation is performed by an erase voltage of the first material layer203.

For example, the first insulating region GS and the second insulating region SS have a wavy shape, such that the first insulating region GS and the second insulating region SS can bend and cross a region between the channel structures CH, which are disposed in a zigzag pattern. Accordingly, the dummy channel structure DVH are not present between the first insulating region GS and the second insulating region SS, and the channel structures CH are disposed such that the distance between channel structures CH between which the first insulating region GS and the second insulating region SS pass and the distance between channel structures CH between which the first insulating region GS and the second insulating region SS do not pass is constant.

FIGS.6and7are cross-sectional views of a semiconductor device according to an embodiment.FIG.6illustrates a region that corresponds toFIG.3B, andFIG.7illustrates a region that corresponds toFIG.3A.

Referring toFIG.6, in an embodiment, in the semiconductor device100, the first insulating region GS is selectively disposed only below the buffer layer201. For example, the first insulating region GS is recessed in the Z-direction below a lower portion of the buffer layer201, in the opposite direction from the protrusion240A of the channel layer240of the channel structure CH.

The first insulating region GS is disposed by selectively removing portions of the etch stop layer221to the lower gate electrode230L at the uppermost end of the gate electrode230. Accordingly, a lower end of the first insulating region GS is recessed into the interlayer insulating layer220, which is a lower portion of the lower gate electrode230L, as illustrated inFIG.3B, and has an upper surface at a same level of the upper surface of the etch stop layer221. Accordingly, the buffer layer201is disposed on the upper surface of the first insulating layer206, which is disposed in the first insulating region GS.

Referring toFIG.7, in an embodiment, in the semiconductor device100, the etch stop layer221is not formed. For example, the interlayer insulating layer220′ of the uppermost end above the lower gate electrode230L has a thickness equal to or greater than the sum of the thicknesses of the interlayer insulating layer220and the etch stop layer221inFIG.3B.

Accordingly, after forming the interlayer insulating layer220′ to a sufficient thickness, when the sacrificial substrate is etched, the interlayer insulating layer220′ is exposed and the channel protrusion240A can be disposed.

For example, the first insulating region GS is selectively disposed only below the buffer layer201as illustrated inFIG.6, and is removed from the upper conductive layer204above the second material layer202. In addition, when the configurations inFIGS.6to7are used, the shape of the protrusion240of the channel layer240is not limited to the example inFIGS.3C and4A to4Cand can vary.

FIGS.8A to8Kare cross-sectional views that illustrate a method of manufacturing a semiconductor device according to an embodiment, and illustrate a region that corresponds toFIG.3B.

Referring toFIG.8A, in an embodiment, a first semiconductor structure S1(PERI) that includes circuit devices120that form a peripheral circuit region PERI, a lower interconnection structure130, a lower bonding structure180, and a lower capping layer190, is formed on a first substrate101.

Device isolation layers are formed in the first substrate101, and a circuit gate dielectric layer122and a circuit gate electrode124are sequentially formed on the first substrate101. The device isolation layers by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer122is formed on the first substrate101, and the circuit gate electrode124is formed on the circuit gate dielectric layer122. The circuit gate dielectric layer122and the circuit gate electrode124can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer122are formed of silicon oxide, and the circuit gate electrode124are formed of at least one of polycrystalline silicon or a metal silicide layer, but an embodiment thereof is not necessarily limited thereto. Spacer layers126are formed on both sidewalls of the circuit gate dielectric layer122and the circuit gate electrode124, and source/drain regions128are formed by injecting impurities into the active region of the first substrate101on both sides of the circuit gate electrode124.

The lower contact plugs135of the lower interconnection structure130are formed by forming a portion of the lower capping layer190, removing a portion thereof by etching and filling a conductive material therein. Lower interconnection lines137are formed by, for example, depositing a conductive material and patterning the material.

Of the lower bonding structures180, the lower bonding via182is formed by forming a portion of the lower capping layer190, removing a portion by etching, and filling a conductive material therein. The lower bonding pad184is formed by, for example, depositing a conductive material and patterning the material. The lower bonding structure180is formed by, for example, a deposition process or a plating process. The lower bonding insulating layer186can be formed by covering a portion of an upper surface and a side surface of the lower bonding pad184and performing a planarization process until the upper surface of the lower bonding pad184is exposed.

The lower capping layer190includes a plurality of insulating layers. The lower capping layer190is a portion in each of the processes that form the lower interconnection structure130and the lower bonding structure180. Accordingly, the first semiconductor structure S1, which is the peripheral circuit region PERI, is formed.

Referring toFIG.8B, the process of manufacturing the second substrate structure S2(CELL) starts.

An etch stop layer221is formed on the base substrate200, and the sacrificial insulating layers118and the interlayer insulating layers220are alternately stacked on the etch stop layer221, thereby forming an upper stack structure.

Thereafter, channel structures CH that penetrate through the stack structure of the sacrificial insulating layers218and the interlayer insulating layers220are formed. In a region that corresponds to the isolation region MS (seeFIG.3B), an isolation opening TS that penetrates through the stack structure of the etch stop layer221, the sacrificial insulating layers218, and the interlayer insulating layers220is formed, and a first isolation opening TSI that penetrates through the upper sacrificial insulating layer218is formed in a region that corresponds to the second insulating region SS.

The base substrate200includes a semiconductor material, such as one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The etch stop layer221is a layer that terminates etching by etch selectivity when the base substrate200is removed, which will be described below. For example, when the base substrate200is a single crystal or an amorphous semiconductor, the etch stop layer221is formed as a polycrystalline semiconductor layer.

A portion of the sacrificial insulating layers218are replaced with gate electrodes230(seeFIG.3A) through a subsequent process. The sacrificial insulating layers218are formed of a material that differs from that of the interlayer insulating layers220, and are formed of a material with etch selectivity under specific etching conditions with respect to the interlayer insulating layers220. For example, the interlayer insulating layer220is formed of at least one of silicon oxide or silicon nitride, and the sacrificial insulating layers218is formed of a material different from that of the interlayer insulating layer220, that is one or more of silicon, silicon oxide, silicon carbide, or silicon nitride. In embodiments, the thickness of the interlayer insulating layers220are not the same. The thickness of the interlayer insulating layers220and the sacrificial insulating layers218and the number of films included therein can vary from the illustrated examples.

As illustrated inFIG.6, the interlayer insulating layer220′ (uppermost interlayer insulating layer) in contact with the base substrate200has a thickness greater than that of the other interlayer insulating layer220without the etch stop layer221, but an embodiment thereof is not necessarily limited thereto.

In the second region R2, a photolithography process and an etching process are repeatedly performed on the sacrificial insulating layers using a mask layer such that the sacrificial insulating layers218in an upper portion extend shorter than the sacrificial insulating layers218in a lower portion. Accordingly, the sacrificial insulating layers218form a step structure with a staircase shape that has a predetermined unit.

Vertical sacrificial structures are formed that penetrate through the lower stack structure. The vertical sacrificial structures are formed by anisotropically etching the lower stack structure of the sacrificial insulating layers218and the interlayer insulating layers220using a mask layer, forming hole-shaped channel holes and filling the holes. The vertical sacrificial structures are recessed into the base substrate200at a uniform depth, but an embodiment thereof is not necessarily limited thereto. The vertical sacrificial structure includes a semiconductor material such as polycrystalline silicon. According to an embodiment, the vertical sacrificial structure includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. After forming the vertical sacrificial structure, an upper stack structure of the sacrificial insulating layers218and the interlayer insulating layers220is formed on the lower stack structure and the vertical sacrificial structure.

When a channel hole that forms a vertical sacrificial structure is formed, a sacrificial blocking structure is preferentially formed that maintains a recess depth of the channel hole into the base substrate to be uniform.

A sacrificial blocking structure is formed in the position where a channel hole is formed in the base substrate200by using a material that is etch selectivity with respect to the base substrate200for the anisotropic etching. For example, the structure is a metal. When a channel hole is formed when the sacrificial blocking structure is formed in each channel hole, the channel hole is not formed in a region below the sacrificial blocking structure due to the sacrificial blocking structure. Thereafter, the sacrificial blocking structure is removed through the channel hole, and depending on the shape of the sacrificial blocking structure, a channel structure CH having a head240C is formed as illustrated inFIG.4AorFIG.4C.

An upper capping layer290that covers the stack structure of the sacrificial insulating layers218and the interlayer insulating layers220is partially formed.

The channel structures CH are formed by forming upper holes in a vertical sacrificial structure, forming hole-shaped channel holes by removing the vertical sacrificial structure, and filling the channel holes with a plurality of layers. The plurality of layers include the data storage structure245, the channel layer240, the filling insulating layer247, and the channel pad249. The upper channel holes of the channel holes are formed by anisotropically etching the upper stack structure of the sacrificial insulating layers218and the interlayer insulating layers220using a mask layer. The lower channel holes of the channel holes are formed by removing the vertical sacrificial structure exposed through the upper channel holes.

Due to the height of the stack structure, a sidewall of the channel structures CH is not perpendicular to an upper surface of the base substrate200. The channel structures CH are formed to be recessed into a portion of the base substrate200, depending on the depth of the channel hole.

The data storage structure245is formed to have a uniform thickness. In this process, the entirety or a portion of the data storage structure245is formed, and a portion that extends perpendicular to the base substrate200along the channel structures CH is also formed. The channel layer240is formed on a data storage structure245in the channel structures CH. The filling insulating layer247is formed to fill the channel structures CH and includes an insulating material. The channel pad249is formed of a conductive material, such as polycrystalline silicon.

As illustrated inFIGS.4B and4C, when the channel structure246is formed in the protrusion240of the channel structures CH, before forming the channel layer240and when the data storage structure245is formed, channel layer materials such as silicon are grown is the region in the base substrate200through selective epitaxial growth (SEG), and the channel structure246is formed at a channel end to have a pillar shape, rather than an annular shape.

Referring back toFIG.8C, in an embodiment, the sacrificial insulating layers (218inFIG.8B) are removed through an isolation opening (TS inFIG.8B) and gate electrodes230are formed by depositing a conductive material. An isolation region MS is formed in the isolation opening (TS inFIG.8B), and a second insulating region SS is formed in the first isolation opening TS1.

The conductive material includes one of a metal, polycrystalline silicon, or a metal silicide. After forming the gate electrodes230, the conductive material deposited in the isolation opening TS is removed through an additional process, the isolation region MS is formed by filling an insulating material and a conductive material, and the second insulating region SS is formed by filling the first isolation opening TSI with an insulating material.

Referring toFIG.8D, andFIG.3A, in an embodiment, an upper interconnection structure270that includes gate contact plugs252and channel contact plugs271are formed, and an upper bonding structure280is formed.

In the first region R1, the channel contact plugs271are connected to the channel structures CH. In the second region R2, the gate contact plugs252are connected to the gate electrodes230. The gate contact plugs252are formed at different depths, or are formed by simultaneously forming contact holes using an etch stop layer, and filling the contact holes with a conductive material.

The contact studs272are connected to the gate contact plugs252. The upper contact plugs275are formed on the contact studs272, and vertically connect the upper interconnection lines277to each other.

The upper bonding structure280is formed in a similar manner to the lower bonding structure180. Accordingly, a second semiconductor structure S2, which is a memory cell region CELL, is formed. However, during a process of manufacturing a semiconductor device, the memory cell region CELL further includes the base substrate200.

Referring toFIG.8E, in an embodiment, the first semiconductor structure S1, which is the peripheral circuit region PERI, and the second semiconductor structure S2, which is the memory cell region CELL, are bonded to each other.

The peripheral circuit region PERI and the memory cell region CELL are connected to each other by bonding the lower bonding pad184to the upper bonding pad284by applying pressure. The lower bonding insulating layer186and the upper bonding insulating layer286are connected to each other by bonding with pressure. The memory cell region CELL is turned upside down and bonded to the peripheral circuit region PERI such that the upper bonding pad284face downward. The peripheral circuit region PERI and the memory cell region CELL are directly bonded to each other without using an adhesive, such as an adhesive layer, therebetween.

Referring toFIG.8F, in an embodiment, the data storage structure245on the base substrate200and the channel structure CH is removed. First, the base substrate200is removed. A portion of the base substrate200is removed from an upper surface by a polishing process such as a grinding process, the other portion is removed by an etching process such as wet etching and/or dry etching, and is etched until the etch stop layer221is upwardly exposed. However, in some embodiments, the entire base substrate200is removed through an etching process. In the region from which the base substrate200was removed, the channel structures CH has a protruding second portion.

The data storage structure245on the second portion of the channel structure CH is removed. The data storage structure245is removed by a photolithography process and an etching process such as wet etching and/or dry etching. Accordingly, in the second portion of the channel structure CH protruding to the etch stop layer221, preferably to the stack structure, the channel layer240is exposed and the protrusion240A is disposed. Accordingly, when a subsequent process is performed, the channel layer240of the second portion is in direct contact with the buffer layer201.

Referring toFIG.8G, in an embodiment, a buffer layer201is formed on the protrusion240A and the etch stop layer221of the channel layer240of the channel structure CH.

The buffer layer201is formed as, for example, a crystalline silicon layer or an epitaxial layer. In this process, the etch stop layer221formed at a lower portion of the buffer layer201is replaced by forming the uppermost interlayer insulating layer220to have a relatively great thickness as illustrated inFIG.7. The buffer layer201is formed to conformally cover the protrusion240A of the channel layer240.

As illustrated inFIG.8H, in an embodiment, a second material layer202, a first material layer203and an upper conductive layer204are consecutively formed to have a first thickness above the buffer layer201.

The second material layer202is deposited in-situ and includes N-type impurities that have a second conductivity, and is formed as a crystalline silicon layer, such as a polycrystalline silicon layer. The first thickness of the second material layer202is less than the height of the protrusion240A of the channel layer240, such that both the end of the protrusion240A of the channel layer240and the side surface thereof are exposed above the second material layer202.

The second material layer202and the protrusion240A of the channel layer240are electrically connected through the side surface of the channel layer that corresponds to the first thickness of the second material layer202, and are electrically connected through the buffer layer201.

A first material layer203is formed on the second material layer202.

The first material layer203is formed to cover at least a portion of area of the second material layer202and has an area less than that of the second material layer202.

The first material layer203is a crystalline silicon layer deposited in-situ and includes P-type impurities that have a first conductivity, such as a polycrystalline silicon layer.

The first material layer203is formed to have a thickness sufficient to cover an end of the protrusion240A of the channel layer240and overlaps the protrusion240A in the Z-direction. Accordingly, the first material layer203and the channel layer240are electrically connected to each other through the buffer layer201.

The first material layer203extends to a boundary between the first region R1and the second region R2, and the second material layer202extends further toward the second region R2and has an area greater than that of the first material layer203.

An upper conductive layer204is further formed on the first material layer203.

The upper conductive layer204is formed by depositing a conductive material, such as a metal such as aluminum (Al) or tungsten (W), on the first material layer203, and is formed to have the same area as the first material layer203.

For example, a horizontal insulating layer219athat covers the second region R2is formed to correspond to the level of the second material layer203. The horizontal insulating layer219ahas a multilayered structure, but an embodiment thereof is not necessarily limited thereto.

The horizontal insulating layer219A is formed of the same material as the sacrificial insulating layers118, but an embodiment thereof is not necessarily limited thereto, and is formed while being in contact with the first and second material layers203and202in a region without the buffer layer201.

Referring toFIG.8I, a second insulating opening TS2that corresponds to the first insulating region GS inFIG.2Ais formed on the upper conductive layer204.

The second insulating opening TS2penetrates from the upper conductive layer204to the lower gate electrode230L. On the X-Y plane, the second insulating opening TS2has a wavy shape and extends in the X-axis direction and has a width that decreases in the Z-axis direction.

Due to the second insulating opening TS2, the lower gate electrode230L has a shape cut to a predetermined capacity as illustrated inFIG.5, and the gate electrode disposed thereon does not have an insulating region above the second insulating opening TS2.

The second insulating opening TS2is spaced apart from the channel structure CH formed in the first region RI by a predetermined distance d1or more.

In addition, the second insulating opening TS2, is formed by selectively removing the remaining layers in which the channel structure CH is not formed. A channel structure CH of sufficient capacity can be assured and the lower gate electrode230L is cut. As illustrated inFIG.8J, the first insulating layer206is formed to have an upper surface coplanar with an upper surface of the upper conductive layer204while filling the second insulating opening TS2.

The process of forming the first insulating region GS by filling the first insulating layer206in the second insulating opening TS2is performed simultaneously with the process of forming the horizontal insulating layer219b.For example, the horizontal insulating layer219band the first insulating layer206of the first insulating region GS are formed of the same material.

Thereafter, as illustrated inFIG.8K, in an embodiment, upper patterns253and254and a passivation layer219bmay be formed.

A passivation layer219bis formed on the first region R1and the second region R2. For example, the passivation layer is implemented in multiple layers. After forming a lower portion of the passivation layer219b,a via hole that opens the upper conductive layer204and the second material layer202is formed, and each of the source contact via267and the body contact via268is formed in the via hole. The source interconnection253is formed in contact with the source contact via267, each body interconnection254is formed in contact with the body contact via268, and an upper portion is formed. The passivation layer219bis flattened by a polishing process such as a grinding process or a chemical mechanical polishing process. A process of removing a portion of the passivation layer219band forming an input/output pad may be added as a subsequent process, but an embodiment thereof is not necessarily limited thereto.

The semiconductor device of embodiments illustrated inFIGS.2A to7can be manufactured by processes illustrated byFIGS.8A to8K.

FIG.9illustrates a data storage system that includes a semiconductor device according to an embodiment.

Referring toFIG.9, in an embodiment, a data storage system1000includes a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be a storage device that includes one or a plurality of semiconductor devices1100or an electronic device that includes a storage device. For example, the data storage system1000may be implemented as a solid state drive device (SSD) that includes one or more semiconductor devices1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

The semiconductor device1100may be implemented as a non-volatile memory device, such as a NAND flash memory device described in an aforementioned embodiment with reference toFIGS.1to3C. The semiconductor device1100includes a first structure1100F and a second structure1100S on the first structure1100F. In embodiments, the first structure1100F is disposed on the side of the second structure1100S. The first structure1100F is implemented as a peripheral circuit structure that includes a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S is implemented as a memory cell structure that includes a bitline BL, a common source line CSL, a body select lines BSL, wordlines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2and memory cell strings CSTR disposed between the bitline BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR includes lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bitline BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2can vary in embodiments.

In embodiments, the upper transistors UT1and UT2include a string select transistor, and the lower transistors LT1and LT2include a ground select transistor. The gate lower lines LL1and LL2are gate electrodes of the lower transistors LT1and LT2, respectively. The wordlines WL are gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1and UL2are gate electrodes of the upper transistors UT1and UT2, respectively.

In embodiments, the lower transistors LT1and LT2include a lower erase control transistor LT1and a ground select transistor LT2connected to each other in series. The upper transistors UT1and UT2include a string select transistor UT1and an upper erase control transistor UT2connected to each other in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT2is used in an erase operation that erases data stored in the memory cell transistors MCT using a GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the wordlines WL, and the first and second gate upper lines UL1and UL2are electrically connected to the decoder circuit1110through first connection interconnections1115that extend from the first structure1100F to the second structure1100S. The bitlines BL are electrically connected to the page buffer1120through second connection interconnections1125that extend from the first structure110F to the second structure1100S.

In the first structure1100F, the decoder circuit1110and the page buffer1120perform control operations on at least one selected memory cell transistor MCT. The decoder circuit1110and the page buffer1120are controlled by the logic circuit1130. The semiconductor device1100communicates with the controller1200through an input/output pad1101electrically connected to the logic circuit1130. The input/output pads1101are electrically connected to the logic circuit1130through an input/output connection line1135that extends from the first structure1100F to the second structure1100S.

The controller1200includes a processor1210, a NAND controller1220, and a host interface1230. In embodiments, the data storage system1000includes a plurality of semiconductor devices1100, and the controller1200controls the plurality of semiconductor devices1100.

The processor1210controls an overall operation of the data storage system1000that includes the controller1200. The processor1210operates according to a predetermined firmware, and accesses the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220includes a controller interface1221that processes communication with the semiconductor device1100. Through the controller interface1221, a control command for controlling the semiconductor device1100, data to be written to the memory cell transistors MCT of the semiconductor device1100, and data to be read from the memory cell transistors MCT of the semiconductor device1100can be transmitted. The host interface1230provides a communication function between the data storage system1000and an external host. When a control command from an external host is received through the host interface1230, the processor1210controls the semiconductor device1100in response to the control command.

FIG.10is a perspective view of a data storage system that includes a semiconductor device according to an embodiment.

Referring toFIG.10a data storage system2000in an embodiment includes a main board2001, a controller2002mounted on the main board2001, one or more semiconductor packages2003, and a DRAM2004. The semiconductor package2003and the DRAM2004are connected to the controller2002by interconnection patterns2005formed on the main board2001.

The main board2001includes a connector2006that includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector2006varies depending on a communication interface between the data storage system2000and the external host. In embodiments, the data storage system2000can communicate with an external host according to one of a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), or an M-Phy for universal flash storage (UFS). In embodiments, the data storage system2000operates by power supplied from an external host through the connector2006. The data storage system2000may further include a power management integrated circuit (PMIC) that distributes the power received from the external host to the controller2002and the semiconductor package2003.

The controller2002writes data to or reads data from the semiconductor package2003, and can increase an operating speed of the data storage system2000.

The DRAM2004is a buffer memory that compensates for differences in speed between the semiconductor package2003, which is a data storage space, and an external host. The DRAM2004in the data storage system2000may operate as a cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the data storage system2000includes the DRAM2004, the controller2002further includes a DRAM controller that controls the DRAM2004, in addition to a NAND controller that controls the semiconductor package2003.

The semiconductor package2003includes first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bis a semiconductor package that includes a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bincludes a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300disposed on lower surfaces of the semiconductor chips2200, a connection structure2400that electrically connects the semiconductor chips2200to the package substrate2100, and a molding layer2500that covers the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100is configured as a printed circuit board that includes package upper pads2130. Each semiconductor chip2200includes an input/output pad2210. The input/output pad2210corresponds to the input/output pad1101inFIG.9, and includes the conductive pad300inFIG.1. Each of the semiconductor chips2200includes gate stack structures3210and channel structures3220. Each of the semiconductor chips2200includes the semiconductor device described in an aforementioned embodiment with reference toFIGS.1to8.

In embodiments, the connection structure2400is a bonding wire that electrically connects the input/output pad2210to the upper package pads2130. Accordingly, in each of the first and second semiconductor packages2003aand2003b,the semiconductor chips2200are electrically connected to each other by a bonding wire method, and are electrically connected to the package upper pads2130of the package substrate2100. In other embodiments, in each of the first and second semiconductor packages2003aand2003b,the semiconductor chips2200are electrically connected to each other by a connection structure that includes a through-electrode (TSV) instead of the connection structure2400of a bonding wire method.

In embodiments, the controller2002and the semiconductor chips2200are included in a single package. In an embodiment, the controller2002and the semiconductor chips2200are mounted on an interposer substrate that differs from the main board2001, and the controller2002and the semiconductor chips2200are connected to each other by interconnection formed on the interposer substrate.

FIG.11is a cross-sectional view of a semiconductor package according to an embodiment.

FIG.11is a cross sectional view of the semiconductor package2003inFIG.10taken along line III-III′.

Referring toFIG.11, in an embodiment, in the semiconductor package2003A, the package substrate2100is implemented as a printed circuit substrate. The package substrate2100includes a package substrate body portion2120, package upper pads2130disposed on an upper surface of the package substrate body portion2120(seeFIG.10), lower pads2125disposed on the lower surface of the package substrate body2120or exposed through the lower surface, and internal interconnections2135that electrically connect the upper pads2130to the lower pads2125in the package substrate body2120. The lower pads2125are connected to the interconnection patterns2005of the main the substrate2001of the data storage system2000through conductive connection portions2800as illustrated inFIG.11.

In the semiconductor package2003A, each of the semiconductor chips2200A includes a semiconductor substrate4010, a first semiconductor structure4100disposed on the semiconductor substrate4010, and a second semiconductor structure4200bonded to the first semiconductor structure4100by wafer bonding on the first semiconductor structure4100.

The first semiconductor structure4100includes a peripheral circuit region that includes a peripheral interconnection4110and a lower bonding structure4150. The second semiconductor structure4200includes a common source line4205, a gate stack structure4210interposed between the common source line4205and the first semiconductor structure4100, a channel structure4220and an isolation structure4230that penetrate through the gate stack structure4210, and an upper bonding structure4250that is electrically connected to wordlines of the channel structures4220and the gate stack structure4210. For example, the upper bonding structure4250is electrically connected to the channel structures4220and wordlines through the gate contact plugs252, which are electrically connected to bitlines4240and wordlines. The lower portion bonding structure4150of the first semiconductor structure4100and the upper bonding structure4250of the second semiconductor structure4200are bonded to each other while being in contact with each other. The bonded portions of the lower bonding structure4150and the upper bonding structure4250are formed of copper (Cu), for example.

The second semiconductor structure4200further includes a first insulating region GS as illustrated in the enlarged view. Each of the semiconductor chips2200A includes at least one first insulating region GS that penetrates through and isolates the lower gate electrode230L.

Each of the semiconductor chips2200A further includes an input/output pad2210and an input/output interconnection4265below the input/output pad2210. The input/output connection interconnection4265is electrically connected to a portion of the second bonding structures4210. The input/output pad2210includes a conductive pad300.

The semiconductor chips2200A inFIG.11are electrically connected to each other by connection structures2400in the form of bonding wires. However, in some embodiments, semiconductor chips in a semiconductor package, such as the semiconductor chips2200A inFIG.11, are electrically connected to each other by a connection structure that includes a through electrode TSV.

According to aforementioned embodiments, in a structure in which two or more substrate structures are bonded to each other, a bulk erase operation can be performed by implementing a common source line and a body selection line to allow the common source line and the body selection line to be simultaneously in contact with the channel layer exposed on the backside surface of the upper substrate structure. In addition, by forming an insulating region that extends from the backside surface of the upper substrate structure and penetrates through at least one gate electrode has a wavy shape pass between the channel structures, the capacity of the channel structure can be assured. Accordingly, a semiconductor device that has increased reliability and integration density and a data storage system that includes the same can be provided.

While embodiments have been illustrated and described above, it will be configured as apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.