High performance MOS device with graded silicide

A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.

TECHNICAL FIELD

This invention generally relates to semiconductor devices and fabrication processes, and particularly to semiconductor device having a strained layer over source/drain regions.

BACKGROUND

The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device drive current improvement becomes more important. Among efforts being made to improve device drive current, forming a strained silicon channel, thus enhancing carrier mobility, is a known practice. Strain, sometimes referred to as stress, can enhance bulk electron and hole mobility. The performance of a MOS device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.

When silicon is placed under strain, the electron mobility is dramatically increased. One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of silicon, the silicon film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility.

Strain can also be induced by forming a strained contact etch stop (CES) layer on a MOS device. When a contact etch stop layer is deposited, due to the lattice spacing mismatch between the CES layer and the underlying layer, an in-plane strain develops to match the lattice spacing. In the channel region, strain also develops as a response to the strain applied, and the carrier mobility is enhanced. Strain applied to the channel region is determined by the intrinsic strain in the CES layer and its thickness, and the intrinsic strain generally increases when the thickness of the CES layer increases.

While CES layers are desirable for strain engineering, very thick CES layers cause difficulty in subsequent processes, such as inter-layer dielectric (ILD) gap filling, and therefore are undesired in high-density circuit design.FIG. 1illustrates a conventional method of improving strain without the necessity of increasing the thickness of the CES layer. After the formation of the spacers4, an extra recess step is performed on the substrate2along edges of the respective spacers4, forming recesses6in the source/drain regions12. A strained CES layer10is then formed. Due to the recesses6, strain applied on the channel region8by the CES layer10increases, and about a seven percent device drive current improvement has been observed due to the increased strain.

The drive current improvement is significant in large devices. In small devices, particularly devices manufactured using 65 nm technologies and beyond, the drive current improvement is less observable, even though the channel mobility is improved. A possible reason is that the recessing of the source/drain regions12causes current crowding effects in regions16, which are substantially narrower portions of the source/drain regions12, and the device drive current is degraded accordingly. The current crowding effects are especially severe in small devices. In devices manufactured using 90 nm technology, the device drive current degradation due to current crowding effects is less than about one percent. In devices manufactured using 65 nm technology, the device drive current is degraded about 12 percent. With the further scaling of the devices, the device drive currents are expected to degrade even more.

What is needed, therefore, is a method to increase the strain applied to the channel region while eliminating the detrimental current crowding effects, so that device drive currents are improved.

SUMMARY OF THE INVENTION

The preferred embodiments of the present invention provide a semiconductor device and a method of forming the same. The semiconductor device suffers fewer current crowding effects and has improved drive current.

In accordance with one aspect of the present invention, the semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a conductive layer on the diffusion region, and a cap layer over the conductive layer. Preferably, the conductive layer is a silicide layer. The cap layer provides a strain to the channel region of the semiconductor device. Preferably, the cap layer is a contact etch stop layer.

In accordance with another aspect of the present invention, the gate spacer includes a first portion and a second portion. The first and second portions preferably include materials having different etching characteristics.

In accordance with yet another aspect of the present invention, the method of forming the semiconductor device includes providing a substrate, forming a gate structure overlying the substrate, forming a sidewall spacer on a sidewall of the gate structure, removing an exposed portion of the substrate material to form a recess, thinning the sidewall spacer, forming a diffusion region in the semiconductor substrate, forming a silicide region on the diffusion region, and forming a cap layer having an inherent strain over the gate, the gate spacer and the source/drain region.

In accordance with yet another aspect of the present invention, the step of forming the sidewall spacer includes forming a first sidewall spacer on the sidewall of the gate and forming a second sidewall spacer along the first sidewall spacer, and the step of thinning the sidewall spacer includes removing a portion of the second sidewall spacer.

In accordance with yet another aspect of the present invention, the step of forming the sidewall spacer includes forming a first sidewall spacer on the sidewall of the gate and forming a second sidewall spacer along the first sidewall spacer, and the step of thinning the sidewall spacer includes removing substantially the entire second sidewall spacer.

The preferred embodiments of the present invention reduce current crowding effects, so that the device drive current is improved. Leakage current is also reduced due to increased distance between the (source/drain) silicide regions and respective junctions.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 2illustrates the formation of a gate stack comprising a gate dielectric20and a gate electrode21on a substrate18. The gate dielectric20preferably has high dielectric constant (k value). In the preferred embodiment, the substrate18comprises bulk silicon. In alternative embodiments, other commonly used materials and structures, such as germanium, SiGe, strained silicon on SiGe, silicon on insulator (SOI), silicon germanium on insulator (SGOI), germanium on insulator (GOI), and the like, can also be used. Shallow trench isolation regions (STI)24are formed in the substrate18to isolate subsequently formed devices. Typically, the formation of STIs24includes etching trenches in the substrate18and filling the trenches with dielectric materials.

Lightly doped drain/source (LDD) regions22are formed in the substrate18, preferably by implanting appropriate impurities using the gate electrode21as a mask. Optionally, halo regions23having an impurity type opposite the type of impurities in the LDD regions22are formed. Halo regions23are used for neutralizing the impurity of the LDD regions and the subsequently formed heavily doped source/drain regions, so that the LDD regions and heavily doped source/drain regions have greater abruptness on their borders. Halo regions23are preferably located close to the borders of the respective LDD regions22and subsequently formed source/drain regions. As is known in the art, by adjusting the implanting energy level and impurity elements, impurities can be implanted to desired depths, preferably with the center of the distribution region close to the desired border of the LDD regions22and subsequently formed source/drain regions.

FIG. 3illustrates the formation of a dummy layer25, which is used for forming spacers. In the preferred embodiment, the dummy layer25includes a liner oxide layer26, sometimes referred to as an adhesion layer, and a nitride layer28. Preferably, the liner oxide layer26has better adhesion to the gate electrode21than the nitride layer28adheres to the gate electrode21. In alternative embodiments, the dummy layer25may include single or composite layers comprising oxide, silicon nitride, silicon oxynitride (SiON) and/or other low-k materials, and may be formed using commonly used techniques, such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), etc.

FIG. 4illustrates the liner oxide layer26and nitride layer28being patterned and etched to form gate spacers30. Either wet etching or dry etching can be used. The resulting spacers30comprise liner oxide portions301and nitride portions302. Preferably, the thickness W1of the spacers30is between about 15 nm and about 75 nm.

Disposable spacers32are then formed along outer edges of the respective spacers30, as illustrated inFIG. 5. Disposable spacers32preferably comprise materials having different etching characteristics from the materials used to form gate spacers30, particularly the spacer portions302, so that disposable spacers32can be removed or thinned without damaging the gate spacers30. In the preferred embodiment, the disposable spacers32are formed of oxide. Preferably, the thickness W3of the disposable spacers32is between about 1 nm and 55 nm. Also, the combined width W2of the gate spacers30and disposable spacers32are preferably less than about 80 nm, and more preferably between about 30 nm and 80 nm.

FIG. 6illustrates the formation of recesses34. The substrate18is preferably etched anisotropocally along edges of the disposable spacers32to form the recesses34, which preferably extend from the respective edges of the disposable spacers32to the respective STI regions24. Recesses34preferably have a depth D of less than about 50 nm, and more preferably between about 1 nm and about 30 nm. Further discussion regarding the recessing depth D and width W2are provided in subsequent paragraphs.

The disposable spacers32are then removed, as shown inFIG. 7. In the preferred embodiment, wet etching is performed and a suitable etchant is chosen based on the material of the disposable spacers32. For example, an HF-containing etchant is used for stripping disposable spacers32that comprise oxides, while an H3PO4-containing etchant is preferably used for etching silicon nitride based spacers.

Source/drain regions36, sometimes referred to as diffusion regions, are then formed, as shown inFIG. 8, preferably by implanting appropriate impurities using the gate spacers30and gate electrode21as masks. Although in the preferred embodiment, the source/drain regions36are formed after the removal of the disposable spacers32, in other embodiments, the source/drain regions36can be formed before the disposable spacers32are removed.

A conductive region38is formed, as illustrated inFIG. 9. The conductive region38is preferably a silicide region, and also preferably comprises nickel. However, other commonly used metals such as titanium, cobalt, palladium, platinum, erbium, and the like, can also be used to form silicides. As is known in the art, the silicidation is preferably performed by blanket deposition of an appropriate metal layer, followed by an annealing step in which the metal reacts with the underlying exposed silicon. Un-reacted metal is then removed, preferably with a selective etch process, and the silicide regions38are left. The thickness of the silicide regions38is preferably between about 5 nm and about 50 nm. The silicide regions38are graded due to the step heights of the source/drain regions36.

Next, as shown inFIG. 10, a cap layer40, sometimes referred to as a “strain inducing layer”40is formed. Although this layer is preferably a contact etch stop (CES) layer and is interchangeably referred to as CES layer40throughout the description, it can be any strained layer or layers, even if the layer does not perform an etch stop function. The cap layer40may also be a composite layer comprising a CES layer and other layers. The type and strength of the strain are determined by the deposition process and materials used. Preferably, nitride, oxynitride, and the like, are used. The thickness T of the cap layer40is preferably greater than the depth D of the recesses34(please refer toFIG. 6). Also, the thickness T is preferably between about 100 nm and about 1200 nm.

It is observed that by forming gate spacers30and disposable spacers32, the preferred embodiments of the present invention have the effect of shifting the silicide portion42away from the channel region43by a distance of (W2- W1). The distance D1between the silicide regions42and the nearest border44, or the junction, of the source/drain regions36is therefore increased. As a result, the current crowding effects are reduced and the device drive current is improved. A further advantage of the preferred embodiments of the present invention is that the leakage current flowing from the silicide regions38to the substrate18is also reduced due to the increased distance between the silicide regions38and junctions, which are located at the borders44.

In order to increase the strain applied to the channel region43, the distance W2(as shown inFIG. 6) is preferably small. However, the crowding effects increase when the distance W2decreases, and the saturation current Idsat(not shown) is adversely affected. Therefore, the beneficial effects caused by the increased strain are offset somewhat. The determination of the distance W2has to take both factors into account. Preferably, in 65 nm technology, the distance W2is less than about 70 nm, and more preferably between about 30 and 70 nm.

The strain introduced to the channel region and the drain saturation current Idsatof the device are related to the recessing depth D (please refer toFIG. 6).Havinga greater recessing depth D increases the strain in the channel. However, the likelihood of current crowding also increases since the silicide regions are closer to the respective junctions when the recessing depth D increases. Considering that increased distance W2reduces the likelihood of the current crowding, balanced D and W2values will provide optimal effects. The optimal values of the D/W2ratio can be found through experiments. In the preferred embodiment, the ratio of D/W2is between about 1/7 and 3/7.

In another embodiment of the present invention, after the structure shown inFIG. 6is formed, an outer portion of the spacers32is stripped, preferably by dry etching, and the spacers32become thinner. Wet etching can also be used. The resulting structure is shown inFIG. 11. Adjusting etching time is a preferred way of controlling the thinning of the spacers.FIGS. 12 and 13illustrate structures after the formation of silicide regions38and cap layer40, respectively.

FIGS. 14 through 16illustrate yet another embodiment of the present invention. The initial steps of this embodiment are similar to those shown inFIG. 2 through 4, andFIG. 14illustrates a resulting structure. However, the thickness W2′ of the spacers30is preferably greater than the thickness w1as shown inFIG.4, and preferably has a similar value to W2as in the previously discussed embodiment.FIGS. 15 and 16illustrate the formation of the recesses34, which have depth D, and source/drain regions36, respectively. The gate spacers30are then thinned to the thickness W1. The resulting structure is the same as shown inFIG. 8. In the preferred embodiment, spacer portion301comprises oxide, while spacer portion302comprises nitride, and wet etching using an H3PO4-containing etchant can be performed to remove outer portions of the spacers30. The ratio of W1/W2′ can be controlled by adjusting can be illustrated inFIG. 9 and 10, respectively. The requirements of the materials, dimensions and forming methods have been discussed in the previously discussed embodiment, and thus are not repeated.