High-frequency device including high-frequency switching circuit

A high-frequency device having a switching circuit includes a compound semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on one main surface of the compound semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the compound semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed on the other main surface of the active region of the compound semiconductor substrate.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2005-210169 filed in the Japanese Patent Office on Jul. 20, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high-frequency devices including high-frequency switching circuits and being applicable to, for example, cellular phones.

2. Description of the Related Art

For example, cellular phones have communicated with each other using high-frequency signals having frequencies in the range of 800 MHz to 2.3 GHz. In such relatively high frequencies, compound semiconductors such as GaAs, which has high electron mobility, in place of known Group IV semiconductors, such as a Si semiconductor, have often been used for power amplifiers (PAs) for amplifying transmission powers, low-noise amplifiers (LNA) for amplifying received signals, and switching circuits for switching signals, in view of high-frequency characteristics.

Devices including high-frequency integrated circuits containing the compound semiconductors such as GaAs have satisfactory high-frequency characteristics when the devices are driven at low voltages. However, as trends toward lower voltage and higher performance grow, there have been further stringent demands for the improvement of frequency characteristics, in particular, a reduction in distortion of switching circuits that correspond to third-generation (3G) cellular phones and that enable simultaneous transmission and reception.

For example, as switching circuits for switching antennae in cellular phones, from the above-described reasons, switch monolithic microwave integrated circuits (switch MMICs) including field-effect transistors (FETs) each containing a GaAs compound semiconductor have often been used. Such antenna-switching circuits are required to meet stringent requirements: low loss, low distortion, and the like at a low operating voltage, e.g., at an operating voltage of 2.6 V.

Various switch ICs have been proposed (for example, see Uda. A Very High Isolation GaAs SPDT Switch IC Seald in an Ultra-compact Plastic Package. IEEE GaAs IC Symposium 1995, pp. 132-135H).

FIG. 12is a circuit diagram showing the most basic switching circuit including junction gate field-effect transistors (J-FETs) each containing, for example, a GaAs compound semiconductor. In this case, a first FET1and a second FET2are disposed on a common GaAs substrate, the first FET1and the second FET2each being a J-FET. The source of the first FET1is connected to the drain of the second FET2. One end of the current channel of the first FET1is connected to a first input/output terminal I/O1with a capacitor C1, the other end is connected to a second input/output terminal I/O2via a capacitor C2. One end of the current channel of the second FET2is connected to a ground terminal GND via a capacitor C3. Thereby, the circuit is DC-decoupled from the exterior.

The gate of the first FET1is connected to a control signal input terminal CTL1via a resistor R1. The gate of the second FET2is connected to a control signal input terminal CTL2via a resistor R2. The midpoint of the current channel between the source of the first FET1and the drain of the second FET2is connected to a DC bias terminal via a resistor R3.

In this switching circuit11, for example, a logic circuit applies a bias voltage of 2 V to the switching circuit via the resistor R3. For example, when a high voltage, e.g., 3 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1is 1 V. As a result, the FET1is ON. On the other hand, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2is −2 V. As a result, the FET2is OFF. Therefore, the channel between the terminals I/O1and I/O2is ON, that is, the switching circuit is ON.

In contrast, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1is −2 V. As a result, the FET1is OFF. On the other hand, for example, when a high voltage, e.g., 3 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2is 1 V. As a result, the FET2is ON. Therefore, the channel between the terminals I/O1and I/O2is OPEN. That is, the signal channel is high-frequency-short-circuited, thus ensuring further isolation.

FIG. 13is a schematic cross-sectional view of a mounted high-frequency device including a known switch MMIC having the above-described switching circuit.

In this case, a switch MMIC102is mounted on a conductive die pad101. Electrodes of the MMIC102are connected to first and second high-frequency input/output terminals I/O1and I/O2, at which a high frequency is inputted or outputted, with lead wires104or the like. The switch MMIC102, the conductive die pad101, and the first and second high-frequency input/output terminals I/O1and I/O2are covered with a resin mold105to form a packaged integrated circuit (IC). The packaged IC is disposed on a circuit board100. The conductive die pad101and the first and second high-frequency input/output terminals I/O1and I/O2are electrically connected to the circuit board100.

The die pad101is formed of a conductive metal layer and is grounded.

FIG. 14is a schematic fragmentary cross-sectional view of a junction gate field-effect transistor (J-FET) containing, for example, GaAs. In this case, a lightly doped semiconductor layer constituting a channel-forming region107is disposed on a GaAs substrate106composed of bulk GaAs and is disposed between, for example, two heavily doped N regions, i.e., a source region108S and a drain region108D. A drain electrode D, a source electrode S, and a gate electrode G are in ohmic contact with the drain region, the source region, and the gate region, respectively.

The presence of the semiinsulating GaAs substrate106disposed directly below the channel-forming region107, i.e., remote from a gate region109, minimizes leakage of a signal.

SUMMARY OF THE INVENTION

As described above, in consumer applications typified by cellular phones, high-frequency MMICs each containing a GaAs compound semiconductor have often been used. Achievement of high-frequency GaAs ICs having satisfactory high-frequency performance and productivity is required.

However, in the high-frequency switching circuits each containing the compound semiconductor, it is difficult to sufficiently achieve lower distortion, which is a stringent requirement, with high reliability.

According to an embodiment of the present invention, there is provided a high-frequency device including a high-frequency switching circuit that overcomes such disadvantages.

According to an embodiment of the present invention, there is provided a high-frequency device including a switching circuit that overcomes such disadvantages.

A high-frequency device having a switching circuit according to an embodiment of the present invention includes a compound semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on one main surface of the compound semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the compound semiconductor substrate, wherein the switching circuit having a field-effect transistor disposed on the other main surface of the active region of the compound semiconductor substrate.

In the above-described high-frequency device having the switching circuit according to an embodiment of the present invention, the positive voltage applied to the compound semiconductor substrate is a fixed positive voltage.

In the above-described device according to an embodiment of the present invention, the insulating portion is disposed on the back surface of the compound semiconductor substrate constituting the switching circuit. Thus, the positive voltage is applied to the compound semiconductor substrate while the substrate is electrically isolated from other components. Therefore, it is possible to stably suppress and control a depletion region under the field-effect transistor.

The above-described high-frequency device having the switching circuit according to an embodiment of the present invention further includes a resistor for applying the predetermined positive voltage to the compound semiconductor substrate, the resistor being disposed between the power terminal and the voltage-applying terminal.

The above-described high-frequency device having the switching circuit according to an embodiment of the present invention further includes a metal plate disposed between the compound semiconductor substrate and the insulating portion, the metal plate being attached to the compound semiconductor substrate, wherein the metal plate serves as the voltage-applying electrode.

The high-frequency device having the switching circuit according to an embodiment of the present invention further includes a silicon semiconductor substrate having a complementary metal-oxide semiconductor logic circuit; a control signal input terminal for feeding a control signal to the logic circuit; and a control signal output terminal for receiving a control signal from the logic circuit.

In the high-frequency device having the switching circuit according to an embodiment of the present invention, the compound semiconductor substrate is a GaAs substrate.

In the above-described structure according to an embodiment of the present invention, the insulating portion is disposed on the back surface of the compound semiconductor substrate, and a positive voltage is applied to the substrate. Thus, it is possible to compensate the nonuniformity of control in a production process and to significantly reduce distortion, as compared with a known unstable switching circuit to which a positive voltage is not applied.

This is believed to be due to the following.

With respect to a reduction in the distortion of a switching circuit composed of a compound semiconductor, in a current technique of producing a compound semiconductor, for example, a low-level impurity concentration and a material composition profile are not sufficiently controlled. Thus, the production of the field-effect transistor results in a minute lot-to-lot variation. In an unstable state in which a voltage is not applied to the compound semiconductor substrate, in fact, in the unstable state in which a bias voltage such as a ground voltage is not applied to the compound semiconductor substrate, an undesired trap is left directly below a channel, and a depletion region is difficult to be controlled. This is believed to be the cause for the generation of the distortion.

Furthermore, a large time constant of the capture or release of an electric charge by the trap impairs the high-speed control of a high-frequency circuit.

Moreover, the depletion region is an undesired capacitance component to degrade high-frequency characteristics.

According to an embodiment of the present invention, the substrate is electrically isolated by the insulating portion, and a voltage is applied to the substrate. As a result, the influence of the trap and the depletion region are suppressed, thus reducing the distortion and improving the high-frequency characteristics.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A high-frequency device including a switching circuit according to an embodiment of the present invention will be exemplified. It is understood that the present invention is not limited to the embodiment.

FIG. 1is a block diagram of a device according to the embodiment of the present invention.FIG. 2is a schematic fragmentary cross-sectional view of the device.

In the present invention, a switching circuit11including a FET1that is a high-electron-mobility transistor (HEMT), a junction field-effect transistor, or the like is disposed on a compound semiconductor substrate1composed of GaAs or the like. In this embodiment, the switching circuit11and a logic circuit12for controlling the switching circuit11.

An insulating portion2is disposed on the back surface of the GaAs compound semiconductor substrate1, i.e., the insulating portion2is disposed on a main surface opposite a main surface at which the field-effect transistor is disposed. In this embodiment, the insulating portion2is an insulating package substrate20composed of, for example, a glass epoxy resin of flame retardant type4(FRT4).

The package substrate20includes, for example, first and second input/output terminals I/O1and I/O2and a ground terminal GND, which are used for the switching circuit11; and control signal input terminals CTL1and CTL2and a power terminal Vdd, which are used for the logic circuit12.

The compound semiconductor substrate1includes, for example, a high-frequency device containing the switching circuit11having the same circuit structure as that shown inFIG. 12and the logic circuit12for driving the switching circuit11.

In the present invention, the compound semiconductor substrate1includes a voltage-applying electrode30for applying a predetermined positive voltage to the compound semiconductor substrate1. A predetermined positive voltage from the power terminal Vdd is applied to the voltage-applying electrode30. In this case, preferably, a resistor R is disposed between the power terminal Vdd and the voltage-applying electrode30to intercept an alternating current component when the voltage is applied to the voltage-applying electrode30.

For example, a power supply connection terminal33is disposed on an insulating surface layer34on the compound semiconductor substrate1. The power supply connection terminal33is connected to the power terminal Vdd with a lead wire or the like. The resistor R is formed as a circuit element in the compound semiconductor substrate1and is disposed between the power supply connection terminal33and the voltage-applying electrode30.

As described above, the switching circuit11includes first and second FET1and FET2on the common compound semiconductor substrate1, for example, a GaAs substrate, the FET1and FET2each being a HEMT or a J-FET. The source of the first FET1is connected to the drain of the second FET2. One end of the current channel of the first FET1is connected to a first input/output terminal I/O1with a capacitor C1, the other end is connected to a second input/output terminal I/O2via a capacitor C2. One end of the current channel of the second FET2is connected to a ground terminal GND via a capacitor C3. Thereby, the circuit is DC-decoupled from the exterior.

Gates of the first and second FET1and FET2are connected to control signal input terminals CTL1and CTL2via resistor R1and R2, respectively, the signal input terminals CTL1and CTL2receiving control signals from the logic circuit12. The midpoint of the current channel between the source of the first FET1and the drain of the second FET2is connected to a DC bias terminal via a resistor R3.

The logic circuit12is supplied with a voltage from the power terminal Vdd to which a power supply voltage is applied. Control signals from control signal terminals CTLa and CTLb are fed to the logic circuit12. The logic circuit12feeds predetermined control signals to the control signal input terminals CTL1and CTL2. The logic circuit12feeds a predetermined bias voltage to a bias terminal Bias.

The above-described circuit elements, i.e., the switching circuit11and the logic circuit12, are disposed on a main surface of the active region1aof the compound semiconductor substrate1. The active region1acan be formed by ion implantation.

The first field-effect transistor FET1is exemplified inFIG. 2. The field-effect transistor is formed by the following procedure: for example, a p-type gate region5or the like is formed on a channel-forming region4having low impurity concentration by ion implantation or the like. An n-type source or drain3is similarly formed by ion implantation or the like so as to be disposed at each side of the channel-forming region4.

A resin mold package40covers the compound semiconductor substrate1and the like disposed on the package substrate20.

The switching circuit11having the structure is controlled by a signal from the logic circuit12and operates in the same way as described inFIG. 12.

That is, for example, a bias voltage of 2 V from the logic circuit12is applied to the switching circuit11via the resistor R3. For example, when a high voltage, e.g., 3 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1is 1 V. As a result, the FET1is ON. On the other hand, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2is −2 V. As a result, the FET2is OFF. Therefore, the channel between the terminals I/O1and I/O2is ON, that is, the switching circuit11is ON.

In contrast, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1is −2 V. As a result, the FET1is OFF. On the other hand, for example, when a high voltage, e.g., 3 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2is 1 V. As a result, the FET2is ON. Therefore, the channel between the terminals I/O1and I/O2is OPEN. That is, the signal channel is high-frequency-short-circuited, thus ensuring further isolation.

In the present invention, as described above, the voltage-applying electrode30is disposed on the compound semiconductor substrate1in order to apply, for example, a predetermined positive bias voltage to the compound semiconductor substrate1. This results in a high-frequency device including a switching circuit having improved distortion.

This is believed to result from a decrease in capacitance due to the reduction of the depletion region of the field-effect transistor. For example, this is believed to result from the prevention of the capture and release of an unstable electric charge by a trap or the like.

In the embodiment shown inFIG. 2, the voltage-applying electrode30is disposed on a main surface having the circuit elements, such as a FET, of the compound semiconductor substrate1. Alternatively, as shown inFIG. 3that is a schematic fragmentary cross-sectional view of a high-frequency device including a switching circuit according to an embodiment of the present invention, the voltage-applying electrode30may be constituted of first and second electrodes31and32that are electrically connected to each other.

In this case, a resistor R may be disposed between the first and second electrodes31and32. Alternatively, the above-described resistor R may be disposed between the first electrode31and the power supply connection terminal33.

As shown inFIG. 3, the first electrode31is disposed on one main surface having circuit elements, such as a FET, of the compound semiconductor substrate1. The second electrode32is disposed on the other main surface. A positive voltage can be applied to the compound semiconductor substrate1using the second electrode32.

As shown inFIG. 3, the first electrode31may be electrically connected to the second electrodes32through a via hole50passing through the compound semiconductor substrate1.

Alternatively, the first electrode31may be electrically connected to the second electrodes32with lead wires.

In the structure shown inFIG. 3, the second electrode32is disposed under at least a region at which field-effect transistors, such as FET1and FET2, are disposed. However, a larger area of the second electrode32results in larger parasitic capacitance, thereby possibly affecting high-frequency characteristics. Thus, the area of the second electrode32is preferably 50% or less of that of the compound semiconductor substrate1.

FIG. 4is a schematic cross-sectional view of a device according to another embodiment of the present invention. In this embodiment, a metal plate is disposed between the compound semiconductor substrate and the insulating portion2.

In this embodiment, a metal plate60, which is a lead frame, is disposed. A die pad61of the lead frame is electrically connected to the back surface of the compound semiconductor substrate1shown inFIG. 2with a conductive material62, such as a silver paste. The resin mold package40functions as the insulating portion2. In this case, the voltage-applying electrode30may be connected to the power terminal Vdd via the die pad61and the above-described resistor R.

InFIGS. 3 and 4, the same or equivalent elements corresponding toFIGS. 1 and 2are designated using the same reference numerals, and redundant description is not repeated.

FIGS. 5,6, and7are each a schematic cross-sectional view showing an exemplary positional relationship between a field-effect transistor (FET) and the voltage-applying electrode30. Each exemplified FET is a junction-gate pseudomorphic high-electron-mobility transistor (PHEMT). That is, the compound semiconductor substrate1provided with epitaxially grown semiconductor layers constituting the PHEMT is disposed on a semi-insulating (SI) GaAs substrate1S or the like.

As shown in each ofFIGS. 5,6, and7, for example, an undoped buffer layer71composed of AlGaAs, a first n-type-impurity-doped layer72, a channel layer73, a second n-type-impurity-doped layer74, and a lightly doped layer75are formed in that order by epitaxial growth on the GaAs substrate1S. A p-type gate region76is formed by ion implantation of Zn ions or the like.

Contact layers78, which are each an n-type heavily doped source/drain composed of GaAs or the like, are disposed between the p-type gate region76. Electrodes79are disposed on the respective contact layers78. Thereby, the FET, which is HEMT, is formed.

In addition to the active region1aincluding the circuit elements such as the FET, a high-resistivity nonactive region1bformed by ion implantation of boron B is disposed so as to surround the active region1aor to separate a plurality of active regions.

As shown inFIG. 5or7, the voltage-applying electrode30may be disposed on the nonactive region1b. Alternatively, as shown inFIG. 6, which is a schematic cross-sectional view, the voltage-applying electrode30may be disposed on another active region1aseparated from the active region1aincluding the FET by the nonactive region1b.

The voltage-applying electrode30is in contact with an impurity-doped region77of the same conductivity type as that of the channel (channel-forming region) or the same conductivity type as that of the gate.

In this structure, it was confirmed that distortion characteristics and isolation were further stabilized and improved. This is believed to result from the successful application of a positive voltage to the back side of the FET.

The impurity-doped region77can be formed simultaneously with, for example, the formation of the p-type gate region76of the FET, such as the HEMT, or the contact layers78, which are each a source/drain.

In the above-described embodiment, the nonactive region1bis formed by ion implantation. Alternatively, the active region1amay be formed in a high-resistivity semiconductor layer by ion implantation depending on the structure of the FET.

In each of the above-described embodiments, the switching circuit11and the logic circuit12are disposed on the common compound semiconductor substrate1. Alternatively, as shown inFIG. 8, which is a schematic plan view, a high-frequency device having the following structure may be formed: for example, only the switching circuit11is disposed on the GaAs compound semiconductor substrate1. A logic circuit is disposed on, for example, a Si substrate, which is a Group IV element semiconductor substrate, different from the compound semiconductor substrate1. The switching circuit11is connected to the logic circuit with lead wires or the like. InFIG. 8, the same or equivalent elements are designated using the same reference numerals, and redundant description is not repeated.

FIG. 9is a graph showing the dependence of the OFF capacitance of the field-effect transistor FET1on bias voltage applied to the compound semiconductor substrate1. In this case, it is found that the OFF capacitance is reduced by 10% when a voltage of 3 V is applied to the substrate.

That is, with respect to switching properties, isolation is improved.

The device shown inFIG. 3is a high-frequency device having a dual pole dual throw (DPDT) switch. In this case, intermodulation distortions IMD2and IMD3are significantly improved.

As shown inFIG. 10, high-frequency input signals RF2and RF1are fed to a dual pole 3 throw (DP3T) switching circuit between input/output terminals I/O1and I/O2.FIG. 11shows second- and third-order intermodulation distortions in an inventive example, in which a voltage is applied to a substrate, and a related example, in which a voltage is not applied to a substrate. As is clear from the results, in the inventive example, the intermodulation distortions are improved.

As described above, a high-frequency device, corresponding to 3G, according to the embodiment of the present invention meets the stringent requirements, i.e., has improved high-frequency characteristics, in particular, reduced distortion.