MULTILAYER CERAMIC CAPACITOR AND MOUNTING STRUCTURE OF MULTILAYER CERAMIC CAPACITOR

A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers, first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction perpendicular or substantially perpendicular to the stacking direction, and first and second end surfaces facing each other in a length direction perpendicular or substantially perpendicular to the stacking and width directions, a first external electrode on the first end surface, a second external electrode on the second end surface, a third external electrode on the first side surface, and a fourth external electrode on the second side surface. A first internal electrode layer is exposed at the first and second end surfaces, and a second internal electrode layer is exposed at the first and second side surfaces and is within a range from the second main surface to ⅓ of the multilayer body in the stacking direction.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application No. 2022-072494 filed on Apr. 26, 2022. The entire contents of this application are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor.

2. Description of the Related Art

For example, there are known a decoupling capacitor used for stabilizing a power supply voltage supplied to an integrated circuit component (IC) that operates at a high speed, and a through-type multilayer ceramic capacitor used for taking measures against noise of a power supply line supplied to the integrated circuit component (IC). For example, a through-type multilayer ceramic capacitor generally includes a ceramic body (a multilayer body) having an outer surface including a first main surface and a second main surface that face each other, a first side surface and a second side surface that face each other, and a first end surface and a second end surface that face each other. Inside the ceramic body, a plurality of first internal electrodes and a plurality of second internal electrodes are alternately arranged in the direction in which these electrodes are stacked. Each of the first internal electrodes has both ends that respectively lead to the first and second end surfaces to be connected to the first and second external electrodes. Further, each of the second internal electrodes has both ends that respectively lead to the first and second side surfaces to be connected to the third and fourth external electrodes.

Such a through-type multilayer ceramic capacitor may be reduced in total number of internal electrodes in order to reduce the capacitance. In this case, when the total number of internal electrodes is reduced, the direct-current (DC) resistance (Rdc) increases, with the result that the amount of heat generated by the through-type multilayer ceramic capacitor may sometimes increase.

Thus, as a structure capable of suppressing an increase in DC resistance while suppressing an increase in capacitance, there is known a structure in which a plurality of signal internal electrodes are contiguously stacked as disclosed in Japanese Patent Laid-Open No. 2012-221993. According to the structure disclosed in Japanese Patent Laid-Open No. 2012-221993, the value of the DC resistance (Rdc) can also be reduced while reducing the capacitance.

SUMMARY OF THE INVENTION

However, when capacitance portions are disposed on the upper and lower sides in the structure as disclosed in Japanese Patent Laid-Open No. 2012-221993, the external electrodes on the side surfaces (the third and fourth external electrodes) are connected to the capacitance portions located far from the mounting surface, which increases the area where the external electrodes on the side surfaces cover the multilayer body near the signal electrode (the first internal electrode), thereby causing a problem that a sufficient heat dissipation effect cannot be achieved. Further, the current path to the mounting substrate is increased in length, thereby also causing a problem that the effect of low equivalent series inductance (ESL) cannot be sufficiently achieved.

Thus, preferred embodiments of the present invention provide multilayer ceramic capacitors and mounting structures of the multilayer ceramic capacitors that are each capable of fully achieving a sufficient heat dissipation effect and a low ESL effect while decreasing a capacitance and yet suppressing an increase in DC resistance.

A multilayer ceramic capacitor according to a preferred embodiment of the present invention includes a multilayer body including a plurality of dielectric layers stacked on one another and a plurality of internal electrode layers respectively stacked on the dielectric layers, the multilayer body including a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a width direction perpendicular or substantially perpendicular to the stacking direction, and a first end surface and a second end surface that face each other in a length direction perpendicular or substantially perpendicular to the stacking direction and the width direction, a first external electrode on the first end surface, a second external electrode on the second end surface, a third external electrode on the first side surface, and a fourth external electrode on the second side surface. The internal electrode layers include a first internal electrode layer exposed at the first end surface and the second end surface, and a second internal electrode layer exposed at the first side surface and the second side surface. The second internal electrode layer is located within a range from the second main surface to one third of the multilayer body in the stacking direction.

Further, a mounting structure of a multilayer ceramic capacitor according to a preferred embodiment of the present invention includes a mounting substrate, and a multilayer ceramic capacitor mounted on the mounting substrate. The multilayer ceramic capacitor is a multilayer ceramic capacitor according to a preferred embodiment of the present invention, and the mounting substrate includes a core of a substrate, a first connection conductor on the core and connected to the first external electrode, a second connection conductor on the core and connected to the second external electrode, a third connection conductor on the core and connected to the third external electrode, and a fourth connection conductor on the core and connected to the fourth external electrode. The multilayer ceramic capacitor is mounted such that the second main surface faces the mounting substrate.

According to a preferred embodiment of the present invention, it is possible to provide multilayer ceramic capacitors and mounting structures of the multilayer ceramic capacitors that are each capable of fully achieving a sufficient heat dissipation effect and a low ESL effect while decreasing a capacitance and yet suppressing an increase in DC resistance.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A. First Preferred Embodiment

A multilayer ceramic capacitor10according to the first preferred embodiment of the present invention will be hereinafter described. Multilayer ceramic capacitor10is a through-type multilayer ceramic capacitor (a multilayer ceramic capacitor of a three-terminal type).

FIG.1is an external perspective view showing an example of a multilayer ceramic capacitor according to the first preferred embodiment of the present invention.FIG.2is a top view showing an example of the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.FIG.3is a bottom view showing an example of the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.FIG.4is a side view showing an example of the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.FIG.5is a cross-sectional view taken along a line V-V inFIG.1.FIG.6is a cross-sectional view taken along a line VI-VI inFIG.1.FIG.7is a cross-sectional view taken along a line VII-VII inFIG.5.FIG.8is a cross-sectional view taken along a line VIII-VIII inFIG.5.FIG.9is a schematic diagram viewed from the side of a first side surface of the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.

As shown inFIGS.1to9, multilayer ceramic capacitor10includes, for example, a multilayer body12and an external electrode30.

Multilayer body12includes a plurality of dielectric layers14stacked on one another and a plurality of internal electrode layers16respectively stacked on dielectric layers14. Further, multilayer body12includes a first main surface12aand a second main surface12bthat face each other in a stacking direction x, a first side surface12cand a second side surface12dthat face each other in a width direction y perpendicular or substantially perpendicular to stacking direction x, and a first end surface12eand a second end surface12fthat face each other in a length direction z perpendicular or substantially perpendicular to stacking direction x and width direction y.

Multilayer body12has a rectangular or substantially rectangular parallelepiped shape having corners and ridges that are preferably rounded. Each of the corners is a portion where three surfaces of multilayer body12meet, and each of the ridges is a portion where two surfaces of multilayer body12meet. Further, protrusions and recesses or the like may be provided partially or entirely in first and second main surfaces12aand12b, first and second side surfaces12cand12d, and first and second end surfaces12eand12f.

In this case, the dimension of multilayer body12in length direction z is defined as a dimension1, the dimension of multilayer body12in width direction y is defined as a dimension w, and the dimension of multilayer body12in stacking direction x is defined as a dimension t. The dimensions of multilayer body12are not particularly limited but it is preferable that dimension1is about 0.9 mm or more and about 1.6 mm or less, dimension w is about 0.4 mm or more and about 0.8 mm or less, and dimension t is about 0.2 mm or more and about 0.6 mm or less.

Multilayer body12includes an effective layer portion18, a first outer layer portion20alocated on the first main surface12aside, and a second outer layer portion20blocated on the second main surface12bside. First outer layer portion20aand second outer layer portion20bare disposed to sandwich effective layer portion18in stacking direction x.

In other words, first outer layer portion20ais a collection of a plurality of dielectric layers14located on the first main surface12aside of multilayer body12and located between first main surface12aand one of internal electrode layers16that is closest to first main surface12a. Second outer layer portion20bis a collection of a plurality of dielectric layers14located on the second main surface12bside of multilayer body12and located between second main surface12band one of internal electrode layers16that is closest to second main surface12b. Further, effective layer portion18is a region sandwiched between first outer layer portion20aand second outer layer portion20b. Multilayer body12includes a first region28ain which dielectric layers14and first internal electrode layers16aare alternately stacked in stacking direction x connecting first main surface12aand second main surface12b, and a second region28bin which first internal electrode layer16aand second internal electrode layer16bare alternately stacked with dielectric layer14interposed therebetween. Second region28bis located closer to second main surface12bthan first region28a. When second region28bis located closer to second main surface12bthan first region28a, the current path extending from second region28bto mounting substrate50and generating a capacitance is shortened, so that a low ESL effect can be achieved.

Multilayer body12has side portions (W gaps)22aand22blocated between first side surface12cand one end in width direction y of each of a first facing portion25aof a first internal electrode layer16aand a second facing portion25bof a second internal electrode layer16b(described later), and also located between second side surface12dand one end in width direction y of each of first facing portion25aof first internal electrode layer16aand second facing portion25bof second internal electrode layer16b(described later). Side portion22aand side portions22bof multilayer body12include a first extending portion27aand a second extending portion27b, respectively, of second internal electrode layer16b.

Further, multilayer body12has end portions (L gaps)24aand24blocated between first end surface12eand one end in length direction z of each of first facing portion25aof first internal electrode layer16aand second facing portion25bof second internal electrode layer16b(described later), and also located between second end surface12fand one end in length direction z of each of first facing portion25aof first internal electrode layer16aand second facing portion25bof second internal electrode layer16b(described later). End portion24aand end portions24bof multilayer body12include a first leading portion26aand a second leading portion26b, respectively, of first internal electrode layer16a.

Dielectric layer14can be made, for example, of a dielectric ceramic including a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3as a ceramic material. Further, dielectric layer14may be made of the above-mentioned main component additionally including a subcomponent such as an Mn compound, an Fe compound, a Cr compound, a Co compound, or an Ni compound.

The thickness of dielectric layer14is preferably 1 μm or more and 15 μm or less. The number of stacked dielectric layers14is preferably 80 or more and 200 or less. This number of dielectric layers14is equal to the total number of dielectric layers14in effective layer portion18and dielectric layers14in first and second outer layer portions20aand20b.

Internal Electrode Layer

Internal electrode layer16includes first internal electrode layer16aand second internal electrode layer16b.

First internal electrode layer16ais disposed on a corresponding one of the plurality of dielectric layers14. First internal electrode layer16aextends to reach first end surface12eand second end surface12f.

More specifically, as shown inFIG.7, first internal electrode layer16aextending between first and second end surfaces12eand12fof multilayer body12includes first facing portion25alocated in a center portion of first internal electrode layer16a, a first leading portion26aextending from first facing portion25ato reach first end surface12eof multilayer body12, and a second leading portion26bextending from first facing portion25ato reach second end surface12fof multilayer body12. First facing portion25ais located in a center portion on dielectric layer14. First leading portion26ais exposed at first end surface12eof multilayer body12, and second leading portion26bis exposed at second end surface12fof multilayer body12. Thus, first internal electrode layer16ais not exposed at first side surface12cand second side surface12dof multilayer body12.

The shapes of first facing portion25a, first leading portion26a, and second leading portion26bof first internal electrode layer16aare not particularly limited but are preferably rectangular or substantially rectangular in a plan view. Note that the corners each may be rounded.

Second internal electrode layer16bis disposed on a corresponding one of the plurality of dielectric layers14. Further, second internal electrode layer16bextends to reach first side surface12cand second side surface12d. Second internal electrode layer16bis disposed on dielectric layer14different from dielectric layer14on which first internal electrode layer16ais disposed.

More specifically, as shown inFIG.8, second internal electrode layer16bextending between first and second side surfaces12cand12dof multilayer body12includes second facing portion25blocated in a center portion of second internal electrode layer16b, first extending portion27aextending from second facing portion25bto reach first side surface12c, and second extending portion27bextending from second facing portion25bto reach second side surface12d. Second facing portion25bis formed in a rectangular or substantially rectangular shape so as to extend in the direction toward first end surface12eand extend in the direction toward second end surface12f. Second facing portion25bis located in a center portion on dielectric layer14. First extending portion27ais exposed at first side surface12cof multilayer body12, and second extending portion27bis exposed at second side surface12dof multilayer body12. Thus, second internal electrode layer16bis not exposed at first end surface12eand second end surface12fof multilayer body12.

The shapes of second facing portion25b, first extending portion27a, and second extending portion27bof second internal electrode layer16bare not particularly limited but are preferably rectangular or substantially rectangular in a plan view. Note that the corners each may be rounded.

First facing portion25aof first internal electrode layer16afaces second facing portion25bof second internal electrode layer16b. In the present preferred embodiment, first facing portion25aof first internal electrode layer16afaces second facing portion25bof second internal electrode layer16bwith dielectric layer14interposed therebetween, to generate a capacitance, so that the characteristics of the capacitor are developed.

The number of first internal electrode layers16ais preferably larger than the number of second internal electrode layers16b. When first internal electrode layers16aare larger in number than second internal electrode layers16b, the DC resistance is reduced to achieve an effect of suppressing the temperature rise of multilayer body12.

The number of first internal electrode layers16ais not particularly limited but is preferably 49 or more and 100 or less, for example. The number of second internal electrode layers16bis not particularly limited but is preferably 1 or more and 50 or less, for example. Thus, the total number of first internal electrode layers16aand second internal electrode layers16bis preferably 50 or more and 150 or less.

The thickness of first internal electrode layer16ais not particularly limited but is preferably about 0.5 μm or more and about 1.1 μm or less, for example. The thickness of second internal electrode layer16bis not particularly limited but is preferably about 0.5 μm or more and about 1.1 μm or less, for example.

Second internal electrode layer16blocated closest to first main surface12ain second region28bof multilayer body12is located within a range from second main surface12bto one third of multilayer body12in stacking direction x. In other words, a length d1between second main surface12band second internal electrode layer16blocated closest to first main surface12ain second region28bof multilayer body12is equal to or less than about one third of dimension t that is the length dimension of multilayer body12in stacking direction x. When second internal electrode layer16blocated closest to first main surface12ain second region28bof multilayer body12is located within a range from second main surface12bto about one third of multilayer body12in stacking direction x, the current path to mounting substrate50is shortened, so that the ESL can be reduced.

More preferably, second region28bis disposed closer to second main surface12bthan first region28a. This allows second region28bto be located close to second main surface12b, so that the ESL can be more effectively reduced.

First internal electrode layer16aand second internal electrode layer16bmay be for example made of an appropriate conductive material like metals such as Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of these metals, such as an Ag—Pd alloy.

External Electrode

External electrode30is disposed on multilayer body12, specifically, on each of the first end surface12eside, the second end surface12fside, the first side surface12cside, and the second side surface12dside. External electrode30includes a first external electrode30a, a second external electrode30b, a third external electrode30c, and a fourth external electrode30d. First external electrode30ais disposed on first end surface12e. First external electrode30ais connected to first internal electrode layer16a. Further, first external electrode30amay be disposed also on a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d.

Second external electrode30bis disposed on second end surface12f. Second external electrode30bis connected to first internal electrode layer16a. Further, second external electrode30bmay be disposed also on a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d.

Third external electrode30cis disposed on first side surface12c. Third external electrode30cis connected to second internal electrode layer16b. Further, third external electrode30cmay have a first covering portion30c1covering second internal electrode layer16bexposed at first side surface12c, and a first bent portion30c2on second main surface12bto be in parallel or substantially in parallel with second internal electrode layer16b. By providing first bent portion30c2, the reliability of electrical connection to mounting substrate50can be further maintained.

Fourth external electrode30dis disposed on second side surface12d. Fourth external electrode30dis connected to second internal electrode layer16b. Further, fourth external electrode30dmay have a second covering portion30d1(not shown) covering second internal electrode layer16bexposed at second side surface12d, and a second bent portion30d2formed on second main surface12bto be in parallel or substantially in parallel with second internal electrode layer16b. By providing second bent portion30d2, the reliability of electrical connection to mounting substrate50can be further maintained.

Further, it is preferable that an end portion of each of third and fourth external electrodes30cand30din length direction z of multilayer body12is located at a distance of about 5 μm or more and about 100 μm or less from an end portion of second internal electrode layer16bin length direction z of multilayer body12that is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12. In this case, more specifically, a length d2is preferably about 5 μm or more and about 100 μm or less, in which length d2extends between an end portion of each of third and fourth external electrodes30cand30din length direction z of multilayer body12and an end portion of second internal electrode layer16bin length direction z of multilayer body12that is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12.

Further, an end portion of each of third and fourth external electrodes30cand30din stacking direction x of multilayer body12is preferably located at a distance of about 5 μm or more and about 100 μm or less from second internal electrode layer16bclosest to first main surface12athat is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12. In this case, more specifically, a length d3is preferably about 5 μm or more and about 100 μm or less, in which length d3extends between an end portion of each of third and fourth external electrodes30cand30din stacking direction x of multilayer body12and an end portion of second internal electrode layer16bin stacking direction x of multilayer body12that is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12.

By disposing third external electrode30cand fourth external electrode30das described above, the area where third external electrode30cand fourth external electrode30dcover multilayer body12can be reduced while maintaining the reliability of electrical connection between second internal electrode layer16band each of third and fourth external electrodes30cand30d, so that heat can be further dissipated.

External electrode30includes an underlying electrode layer32disposed on the surface of multilayer body12and a plating layer34disposed to cover underlying electrode layer32. Underlying electrode layer32includes a first underlying electrode layer32a, a second underlying electrode layer32b, a third underlying electrode layer32c, and a fourth underlying electrode layer32d.

Plating layer34includes a first plating layer34a, a second plating layer34b, a third plating layer34c, and a fourth plating layer34d.

In other words, first external electrode30aincludes first underlying electrode layer32aand first plating layer34a. Second external electrode30bincludes second underlying electrode layer32band second plating layer34b. Third external electrode30cincludes third underlying electrode layer32cand third plating layer34c. Fourth external electrode30dincludes fourth underlying electrode layer32dand fourth plating layer34d.

First underlying electrode layer32ais disposed on the surface of first end surface12eof multilayer body12and formed to extend from first end surface12eto cover a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d.

Second underlying electrode layer32bis disposed on the surface of second end surface12fof multilayer body12and formed to extend from second end surface12fto cover a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d.

Note that first underlying electrode layer32amay be disposed only on the surface of first end surface12eof multilayer body12, and second underlying electrode layer32bmay be disposed only on the surface of second end surface12fof multilayer body12.

Third underlying electrode layer32cis disposed on the surface of first side surface12cof multilayer body12and formed to extend from first side surface12cto cover second main surface12b.

Fourth underlying electrode layer32dis disposed on the surface of second side surface12dof multilayer body12and formed to extend from second side surface12dto cover second main surface12b.

Underlying electrode layer32includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

The following describes the configurations in which underlying electrode layer32is formed as a baked layer, a conductive resin layer, and a thin film layer as described above.

Baked Layer

The baked layer includes a glass component and a metal component. The glass component of the baked layer includes at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The metal component of the baked layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like. Also, a plurality of baked layers may be provided. The baked layer is formed by applying a conductive paste including a glass component and a metal component onto multilayer body12and firing it. The baked layer may be formed by firing the stacked chip including internal electrode layer16and dielectric layer14simultaneously with the conductive paste applied onto the stacked chip, or may be formed by firing the stacked chip including internal electrode layer16and dielectric layer14to obtain multilayer body12onto which a conductive paste is applied and then baked. When the baked layer is obtained by firing the stacked chip including internal electrode layer16and dielectric layer14simultaneously with the conductive paste applied onto the stacked chip, the baked layer is preferably formed by baking a material additionally including a dielectric material in place of a glass component.

The thickness of first underlying electrode layer32alocated on first end surface12e, in length direction z connecting first and second end surfaces12eand12f, and at the center of first underlying electrode layer32ain stacking direction x is preferably about 20 μm or more and about 50 μm or less.

Further, the thickness of second underlying electrode layer32blocated on second end surface12f, in length direction z connecting first and second end surfaces12eand12f, and at the center of second underlying electrode layer32bin stacking direction x is preferably about 20 μm or more and about 50 μm or less.

In the case where first underlying electrode layer32ais provided on a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d, the thickness of first underlying electrode layer32alocated on each of first and second main surfaces12aand12b, in stacking direction x connecting first and second main surfaces12aand12b, and at the center of first underlying electrode layer32ain length direction z connecting first and second end surfaces12eand12fis preferably about 5 μm or more and about 20 μm or less, for example. Further, the thickness of first underlying electrode layer32alocated on each of first and second side surfaces12cand12d, in width direction y connecting first and second side surfaces12cand12d, and at the center of first underlying electrode layer32ain length direction z connecting first and second end surfaces12eand12fis preferably about 5 μm or more and about 20 μm or less, for example.

In the case where second underlying electrode layer32bis provided on a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d, the thickness of second underlying electrode layer32blocated on each of first and second main surfaces12aand12b, in stacking direction x connecting first and second main surfaces12aand12b, and at the center of second underlying electrode layer32bin length direction z connecting first and second end surfaces12eand12fis preferably about 5 μm or more and about 20 μm or less, for example. Further, the thickness of second underlying electrode layer32blocated on each of first and second side surfaces12cand12d, in width direction y connecting first and second side surfaces12cand12d, and at the center of second underlying electrode layer32bin length direction z connecting first and second end surfaces12eand12fis preferably about 5 μm or more and about 20 μm or less, for example.

The thickness of third underlying electrode layer32clocated on first side surface12c, in width direction y connecting first and second side surfaces12cand12d, and at the center of third underlying electrode layer32cin length direction z connecting first and second end surfaces12eand12fis preferably about 20 μm or more and about 40 μm or less, for example.

Further, the thickness of fourth underlying electrode layer32dlocated on second side surface12d, in width direction y connecting first and second side surfaces12cand12d, and at the center of fourth underlying electrode layer32din length direction z connecting first and second end surfaces12eand12fis preferably about 20 μm or more and about 40 μm or less, for example.

The thickness of third underlying electrode layer32clocated on second main surface12b, in stacking direction x connecting first and second main surfaces12aand12b, and at the center of third underlying electrode layer32cin length direction z connecting first and second end surfaces12eand12fis preferably about 5 μm or more and about 20 μm or less, for example.

The thickness of fourth underlying electrode layer32dlocated on second main surface12b, in stacking direction x connecting first and second main surfaces12aand12b, and at the center of fourth underlying electrode layer32din length direction z connecting first and second end surfaces12eand12fis preferably about 5 μm or more and about 20 μm or less, for example.

Conductive Resin Layer

The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on multilayer body12without providing a baked layer. The conductive resin layer may completely cover the baked layer or may partially cover the baked layer. Further, a plurality of conductive resin layers may be provided.

The conductive resin layer includes a thermosetting resin and metal(s). The conductive resin layer includes a thermosetting resin and therefore is more flexible than a baked layer, for example, made of a fired product of a conductive paste or a plating film. Thus, even when multilayer ceramic capacitor10receives a physical impact or an impact caused by a thermal cycle, the conductive resin layer functions as a shock-absorbing layer and thereby can prevent cracking from occurring in multilayer ceramic capacitor10.

As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi, or an alloy including these metals can be used. Further, powdery metals each having a surface coated with Ag can also be used. When powdery metals each having a surface coated with Ag are used, Cu, Ni, Sn, Bi or an alloy powder thereof is preferably used as powdery metals. The reason why the conductive powdery metals of Ag are used as conductive metal is because Ag is lowest in specific resistance among metals and therefore is suitable for an electrode material, because Ag is a noble metal and therefore is not oxidized and exhibits a high weather resistance, and also because an inexpensive metal can be used for the base material while maintaining the above-described characteristics of Ag.

Further, as the metal contained in the conductive resin layer, a metal obtained by subjecting Cu or Ni to an antioxidant treatment can also be used. As the metal contained in the conductive resin layer, powdery metals each having a surface coated with Sn, Ni, or Cu can also be used. When powdery metals each having a surface coated with Sn, Ni, or Cu are used, Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof is preferably used as powdery metals.

The metal contained in the conductive resin layer is responsible mainly for electrical conductivity of the conductive resin layer. Specifically, electrically conductive fillers come into contact with each other to thereby form an electrical path inside the conductive resin layer.

The metal contained in the conductive resin layer may have a spherical shape, a flat shape or the like, but it is preferable to use a mixture of spherical-shaped powdery metals and flat-shaped powdery metals.

Examples of the resin for the conductive resin layer usable herein include various known thermosetting resins such as an epoxy resin, a phenol resin, an urethane resin, a silicone resin, or a polyimide resin. Among them, the epoxy resin excellent in heat resistance, moisture resistance, adhesiveness, and the like is one of the most appropriate resins.

Further, the conductive resin layer preferably includes a curing agent together with the thermosetting resin. When the epoxy resin is used as a base resin, examples of the curing agent for the epoxy resin usable herein include various known compounds such as a phenol-based compound, an amine-based compound, an acid anhydride-based compound, an imidazole-based compound, an active ester-based compound, or an amide-imide-based compound.

The thickest portion of the conductive resin layer preferably has a thickness of about 20 μm or more and about 70 μm or less, for example.

Thin Film Layer

When a thin film layer is provided as underlying electrode layer32, the thin film layer is formed by a thin film forming method such as a sputtering method or a vapor deposition method such that metal particles are deposited to form a layer of about 1 μm or less.

Plating layer34is disposed to cover underlying electrode layer32.

Plating layer34includes at least one selected, for example, from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like. Plating layer34may include a plurality of layers. In this case, plating layer34preferably has a two-layer structure of Ni plating and Sn plating. The Ni plating layer is used to prevent underlying electrode layer32from being eroded by solder used when multilayer ceramic capacitor10is mounted. The Sn plating layer is used to improve the solderability in mounting multilayer ceramic capacitor10, to thereby allow easy mounting. The thickness per layer of plating layer34is preferably about 1 μm or more and about 6 μm or less, for example.

Note that external electrode30may be formed only of a plating layer without providing underlying electrode layer32. Although not shown, the following describes the structure in which a plating layer is provided without providing underlying electrode layer32.

One or each of first external electrode30a, second external electrode30b, third external electrode30c, and fourth external electrode30dmay be formed such that a plating layer is formed directly on the surface of multilayer body12without providing underlying electrode layer32. In other words, multilayer ceramic capacitor10may have a structure including a plating layer electrically connected to first internal electrode layer16aand second internal electrode layer16b. In such a case, the plating layer may be formed after a catalyst is disposed on the surface of multilayer body12as pretreatment.

When the plating layer is formed directly on multilayer body12without providing underlying electrode layer32, reduction in thickness of underlying electrode layer32can be translated into a lower profile, i.e., a decrease in thickness, or into a thickness of multilayer body12, i.e., a thickness of effective layer portion18. Thus, the degree of freedom in designing a thin chip can be improved.

The plating layer preferably includes a lower plating electrode formed on the surface of multilayer body12and an upper plating electrode formed on the surface of the lower plating electrode. Each of the lower plating electrode and the upper plating electrode preferably includes, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, or the like, or an alloy including the metal(s). Further, the lower plating electrode is preferably formed of Ni having solder barrier performance, and the upper plating electrode is preferably formed of Sn or Au excellent in solderability.

Further, for example, when first internal electrode layer16aand second internal electrode layer16beach are formed of Ni, the lower plating electrode is preferably formed of Cu that is well joined to Ni. The upper plating electrode should only be formed as required, and each of first external electrode30a, second external electrode30b, third external electrode30c, and fourth external electrode30dmay be formed only from the lower plating electrode. In the plating layer, the upper plating electrode may be provided as an outermost layer, or another plating electrode may be further formed on the surface of the upper plating electrode.

In this case, when external electrode30is formed only of a plating layer without providing underlying electrode layer32, the thickness per layer of the plating layer disposed without providing underlying electrode layer32is preferably about 1 μm or more and about 15 μm or less.

Further, the plating layer preferably includes no glass. The proportion of metal per unit volume of the plating layer is preferably about 99 vol % or more.

The dimension in length direction z of multilayer ceramic capacitor10including multilayer body12and external electrode30is defined as a dimension L. Dimension L is preferably about 1.0 mm or more and about 1.7 mm or less, for example.

The dimension in stacking direction x of multilayer ceramic capacitor10including multilayer body12and external electrode30is defined as a dimension T. Dimension T is preferably about 0.3 mm or more and about 0.7 mm or less, for example.

The dimension in width direction y of multilayer ceramic capacitor10including multilayer body12and external electrode30is defined as a dimension W. Dimension W is preferably about 0.5 mm or more and about 0.9 mm or less, for example.

In multilayer ceramic capacitor10shown inFIG.1, second internal electrode layer16blocated closest to first main surface12ain second region28bof multilayer body12is located within a range from second main surface12bto one third of multilayer body12in stacking direction x. As a result, the current path to mounting substrate50is shortened, so that the ESL can be reduced.

Further, in multilayer ceramic capacitor10shown inFIG.1, the area where third external electrode30cand fourth external electrode30dcover multilayer body12can be reduced as compared with the conventional case, so that heat can be further dissipated.

2. Mounting Structure of Multilayer Ceramic Capacitor

The following describes the mounting structure of the multilayer ceramic capacitor according to the first preferred embodiment of the present invention with reference toFIGS.10and11.

As shown inFIGS.10and11, a mounting structure100of the multilayer ceramic capacitor according to the first preferred embodiment includes multilayer ceramic capacitor10and mounting substrate50according to the first preferred embodiment. Mounting substrate50includes a core member51and a conductor land52of the substrate. Core member51of the substrate is formed, for example, from a substrate made of a material obtained by impregnating a mixed base material of a glass fabric (cloth) and a glass nonwoven fabric with an epoxy resin or a polyimide resin, or formed from a ceramic body manufactured by baking a sheet obtained by mixing ceramics and glass. Note that core member51of the substrate may be a single-layer substrate or may be a substrate formed by stacking a plurality of layers.

The thickness of core member51of the substrate is not particularly limited but is preferably about 200 μm or more and about 800 μm or less, for example.

One of the main surfaces of core member51of the substrate is provided with conductor land52and defines a substrate-side mounting surface51aserving as a mounting surface of multilayer ceramic capacitor10.

Conductor land52includes a first conductor land52a, a second conductor land52b, a third conductor land52c, and a fourth conductor land52d.

First conductor land52ais electrically connected and mechanically bonded by a bonding material54to first external electrode30aof multilayer ceramic capacitor10. Second conductor land52bis electrically connected and mechanically bonded by bonding material54to second external electrode30bof multilayer ceramic capacitor10. Third conductor land52cis electrically connected and mechanically bonded by bonding material54to third external electrode30cof multilayer ceramic capacitor10. Fourth conductor land52dis electrically connected and mechanically bonded by bonding material54to fourth external electrode30dof multilayer ceramic capacitor10.

Note that conductor land52may be provided on the main surface of core member51of the substrate on the side opposite to substrate-side mounting surface51a.

The material of conductor land52is not particularly limited but may be formed, for example, of metal such as copper, gold, palladium, or platinum. Further, the thickness of conductor land52, i.e., the dimension in stacking direction x, is not particularly limited but is preferably about 20 μm or more and about 200 μm or less, for example. Bonding material54can be formed, for example, of an epoxy-based adhesive for high heat resistance.

In the above description, mounting substrate50corresponds to a mounting substrate according to a preferred embodiment of the present invention. Core member51of the substrate corresponds to a core of a substrate according to a preferred embodiment of the present invention. Substrate-side mounting surface51acorresponds to a mounting surface according to a preferred embodiment of the present invention. The plurality of conductor lands52correspond to a plurality of connection conductors according to a preferred embodiment of the present invention. However, the connection conductors according to preferred embodiments of the present invention is not limited by other purposes, functions, shapes, names, and the like as long as it is provided as, in addition to what is called a land, a conductor disposed between the multilayer ceramic capacitor and the mounting substrate to allow electrical connection therebetween.

Mounting structure100of the multilayer ceramic capacitor shown inFIGS.10and11is mounted on mounting substrate50such that second main surface12bof multilayer ceramic capacitor10faces substrate-side mounting surface51a. This implements electrical connection between multilayer ceramic capacitor10and mounting substrate50in the state in which the distance between substrate-side mounting surface51aof mounting substrate50and each of first and second extending portions27aand27brespectively extending from first and second side surfaces12cand12dis minimized.

Accordingly, in mounting structure100of multilayer ceramic capacitor10shown inFIGS.10and11, various functions of multilayer ceramic capacitor10according to the first preferred embodiment of the present invention described above are reflected as they are, and thus, the current path from second internal electrode layer16bof multilayer ceramic capacitor10to mounting substrate50can be shortened as compared with the conventional case. As a result, various effects of multilayer ceramic capacitor10according to the first preferred embodiment of the present invention are reflected to achieve the effect of improving the low ESL characteristics in the mounting structure of the multilayer ceramic capacitor.

3. Method of Manufacturing Multilayer Ceramic Capacitor

The following describes a non-limiting example of a method of manufacturing multilayer ceramic capacitor10according to the first preferred embodiment of the present invention.

First, a dielectric sheet for dielectric layer and a conductive paste for internal electrode are prepared. The dielectric sheet and the conductive paste for internal electrode layer include a binder and a solvent, which may be a known binder and a known solvent.

The conductive paste for internal electrode layer is printed on the dielectric sheet in a prescribed pattern, for example, by screen printing or gravure printing. Thus, a dielectric sheet having a pattern of the first internal electrode layer formed thereon and a dielectric sheet having a pattern of the second internal electrode layer formed thereon are prepared. More specifically, a screen mask for printing the first internal electrode layer and a screen mask for printing the second internal electrode layer are separately prepared, and the patterns of the respective internal electrode layers can be printed using a printing machine capable of separately printing these two types of screen masks.

In this case, sheets having the first internal electrode layers printed thereon are stacked to form a portion to be provided as first region28a. Further, sheets having the first internal electrode layers printed thereon and sheets having the second internal electrode layers printed thereon are alternately stacked to form a portion to be provided as second region28b. At this time, the number of stacked sheets having the first internal electrode layers printed thereon is larger than the number of stacked sheets having the second internal electrode layers printed thereon.

Then, a prescribed number of dielectric sheets on which the patterns of the internal electrode layers are not printed are stacked to form a portion to be provided as first outer layer portion20aon the first main surface12aside. Then, the portion to be provided as first region28aformed in the above-described process is stacked on the portion to be provided as first outer layer portion20a. Then, the portion to be provided as second region28bformed in the above-described process is stacked on the portion to be provided as first region28a. Then, a prescribed number of dielectric sheets on which the patterns of the internal electrode layers are not printed are stacked on a portion to be provided as second region28b, to form a portion to be provided as second outer layer portion20bon the second main surface12bside. This produces stacked sheets. In this case, by changing the order in which the portion to be provided as first region28aand the portion to be provided as second region28bare stacked, first region28aand second region28bcan be arranged at desired positions.

Then, the stacked sheets are pressed in the stacking direction by, for example, hydrostatic pressing to produce a stacked block.

Then, the stacked block is cut into a prescribed size to cut out stacked chips. At this time, the corners and the ridges of each stacked chip may be rounded by barrel polishing or the like.

Then, the cut-out stacked chip is fired to produce multilayer body12. The firing temperature, which depends on the materials of dielectric layer14and internal electrode layer16, is preferably about 900° C. or higher and about 1400° C. or lower.

Underlying Electrode Layer

Subsequently, third underlying electrode layer32cof third external electrode30cis formed on first side surface12cof multilayer body12obtained by firing, and fourth underlying electrode layer32dof fourth external electrode30dis formed on second side surface12dof multilayer body12.

When a baked layer is formed as underlying electrode layer32, a conductive paste including a glass component and a metal component is applied and then baked to thereby form a baked layer as underlying electrode layer32. The baking temperature at this time is preferably about 700° C. or higher and about 900° C. or lower, for example. In the present preferred embodiment, underlying electrode layer32is formed of a baked layer.

In this case, various methods can be used as a method of forming a baked layer. Example of the method used herein include a method of adjusting the direction of multilayer body12by a camera or a magnet such that second main surface12bis located below, and then holding multilayer body12with a holding jig and extruding the conductive paste through a slit or a hole so to be applied. In the case of the above-described method, by increasing the extrusion amount of the conductive paste, third underlying electrode layer32cand fourth underlying electrode layer32dcan be formed not only on second main surface12bbut also on a portion of first side surface12cand a portion of second side surface12dso as to cover second internal electrode layer16bexposed at first side surface12cand second side surface12d.

Then, first underlying electrode layer32aof first external electrode30ais formed on first end surface12eof multilayer body12obtained by firing, and second underlying electrode layer32bof second external electrode30bis formed on second end surface12fof multilayer body12. In the present preferred embodiment, first underlying electrode layer32aand second underlying electrode layer32bare formed by a DIP method so as to extend not only to reach first end surface12eand second end surface12fbut also to reach a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d.

In the baking treatment, first underlying electrode layer32aof first external electrode30a, second underlying electrode layer32bof second external electrode30b, third underlying electrode layer32cof third external electrode30c, and fourth underlying electrode layer32dof fourth external electrode30dmay be simultaneously baked, or first underlying electrode layer32aof first external electrode30a, second underlying electrode layer32bof second external electrode30b, third underlying electrode layer32cof third external electrode30c, and fourth underlying electrode layer32dof fourth external electrode30dmay be separately baked.

Conductive Resin Layer

When underlying electrode layer32is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. Note that the conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may alone be directly formed on multilayer body12without forming the baked layer.

As a method of forming a conductive resin layer, a conductive resin paste including a thermosetting resin and a metal component is applied on the baked layer or multilayer body12, and subjected to heat treatment at a temperature of about 250° C. or higher and about 550° C. or lower to thermally cure the resin to thereby form a conductive resin layer. At this time, the atmosphere during the heat treatment is preferably an N2 atmosphere. In order to prevent scattering of the resin and to prevent oxidation of various metal components, the oxygen concentration is preferably suppressed to be about 100 ppm or less, for example.

Examples of the method of applying a conductive resin paste may include a method of extruding the conductive resin paste through a slit so as to be applied, similarly to the method of forming underlying electrode layer32with a baked layer.

Thin Film Layer

When underlying electrode layer32is formed of a thin film layer, masking or the like is performed, and thereby, underlying electrode layer32can be formed by a thin film forming method such as a sputtering method or a vapor deposition method at a position where external electrode30is desired to be formed. Underlying electrode layer32formed of a thin film layer is provided such that metal particles are deposited to form a layer of 1 μm or less.

Plating Layer

Further, external electrode30may be formed only of a plating layer without providing underlying electrode layer32. In this case, external electrode30can be formed by the following method.

First end surface12eand second end surface12fof multilayer body12are plated to form a lower plating electrode in the portion where first internal electrode layer16ais exposed. Similarly, first side surface12cand second side surface12dof multilayer body12are plated to form a lower plating electrode in the portion where second internal electrode layer16bis exposed. In the plating treatment, either electrolytic plating or electroless plating may be adopted, but electroless plating requires a pretreatment with a catalyst or the like in order to improve the plating precipitation speed, which disadvantageously complicates the process. Thus, it is usually preferable to use electrolytic plating. As a plating method, barrel plating is preferably used. Further, an upper plating electrode formed on the surface of the lower plating electrode may be similarly formed as required.

Finally, plating layer34is formed. Plating layer34may be formed on the surface of underlying electrode layer32or may be formed directly on multilayer body12. In the present preferred embodiment, plating layer34is formed on the surface of underlying electrode layer32. More specifically, an Ni plating layer as a lower plating layer and an Sn plating layer as an upper plating layer are formed on underlying electrode layer32. In the plating treatment, either electrolytic plating or electroless plating may be adopted. However, electroless plating requires a pretreatment with a catalyst or the like in order to improve the plating precipitation speed, which disadvantageously complicates the process. Thus, it is usually preferable to use electrolytic plating.

Multilayer ceramic capacitor10according to the present preferred embodiment is manufactured as described above.

B. Second Preferred Embodiment

A multilayer ceramic capacitor110as an example of a multilayer ceramic capacitor according to the second preferred embodiment of the present invention will be hereinafter described.FIG.12is an external perspective view showing an example of the multilayer ceramic capacitor according to the second preferred embodiment of the present invention.FIG.13is a top view showing an example of the multilayer ceramic capacitor according to the second preferred embodiment of the present invention.FIG.14is a bottom view showing an example of the multilayer ceramic capacitor according to the second preferred embodiment of the present invention.FIG.15is a side view showing an example of the multilayer ceramic capacitor according to the second preferred embodiment of the present invention.FIG.16is a cross-sectional view taken along a line XVI-XVI inFIG.12.FIG.17is a cross-sectional view taken along a line XVII-XVII inFIG.12.FIG.18is a cross-sectional view taken along a line XVIII-XVIII inFIG.16.FIG.19is a cross-sectional view taken along a line XIX-XIX inFIG.16.FIG.20is a schematic diagram viewed from the side of a first side surface of the multilayer ceramic capacitor according to the second preferred embodiment of the present invention.

As shown inFIGS.12to20, multilayer ceramic capacitor110according to the second preferred embodiment includes a multilayer body12and an external electrode130. In multilayer ceramic capacitor110, third external electrode30cand fourth external electrode30dof multilayer ceramic capacitor10according to the first preferred embodiment are contiguously disposed on second main surface12b. Therefore, the components corresponding to those in the first preferred embodiment are denoted by the same reference characters, and the detailed description thereof will not be repeated.

The following describes external electrode130of multilayer ceramic capacitor110according to the second preferred embodiment. External electrode130includes a first external electrode130adisposed on the first end surface12eside, a second external electrode130bdisposed on the second end surface12fside, and a third external electrode130cdisposed on the first side surface12cside and the second side surface12dside and contiguously disposed on second main surface12b.

First external electrode130aand second external electrode130bof external electrode130according to the second preferred embodiment correspond to first external electrode30aand second external electrode30b, respectively, of external electrode30according to the first preferred embodiment. Thus, the detailed description thereof will not be repeated in the present preferred embodiment.

Third external electrode130cof external electrode130according to the second preferred embodiment is disposed on a portion of first side surface12c, a portion of second side surface12d, and a portion of second main surface12bof multilayer body12. Further, third external electrode130cis contiguously disposed on second main surface12b. Further, third external electrode130cis connected to second internal electrode layer16b.

Further, the end portion of third external electrode130cin length direction z on each of first and second side surfaces12cand12dis preferably located at a distance of, for example, about 5 μm or more and about 100 μm or less from the end portion of second internal electrode layer16bin length direction z of multilayer body12that is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12. In this case, more specifically, a length d2′ is preferably, for example, about 5 μm or more and about 100 μm or less, in which length d2′ extends between the end portion of third external electrode130con each of first and second side surfaces12cand12din length direction z of multilayer body12, and the end portion of second internal electrode layer16bin length direction z of multilayer body12that is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12.

Further, the end portion of third external electrode130con each of first and second side surfaces12cand12din stacking direction x of multilayer body12is preferably located at a distance of, for example, about 5 μm or more and about 100 μm or less from second internal electrode layer16bclosest to first main surface12athat is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12. In this case, more specifically, a length d3′ is preferably, for example, about 5 μm or more and about 100 μm or less, in which length d3′ extends between the end portion of each of third and fourth external electrodes30cand30din stacking direction x of multilayer body12and the end portion of second internal electrode layer16bin stacking direction x of multilayer body12that is exposed at a corresponding one of first and second side surfaces12cand12dof multilayer body12.

By disposing third external electrode130cas described above, the area where third external electrode130ccovers multilayer body12can be reduced while maintaining the reliability of electrical connection between second internal electrode layer16band third external electrode130c, so that heat can be further dissipated.

Further, disposing third external electrode130cas described above achieves an effect that the self-alignment effect is readily exerted even if mounting misalignment occurs when multilayer ceramic capacitor10is mounted on the substrate.

External electrode130includes an underlying electrode layer132disposed on the surface of multilayer body12and a plating layer134disposed to cover underlying electrode layer132. Underlying electrode layer132includes a first underlying electrode layer132a, a second underlying electrode layer132b, and a third underlying electrode layer132c. Plating layer134includes a first plating layer134a, a second plating layer134b, and a third plating layer134c. In other words, first external electrode130aincludes first underlying electrode layer132aand first plating layer134a. Second external electrode130bincludes second underlying electrode layer132band second plating layer134b. Third external electrode130cincludes third underlying electrode layer132cand third plating layer134c. Underlying electrode layer132and plating layer134of external electrode130according to the second preferred embodiment correspond to underlying electrode layer32and plating layer34, respectively, of external electrode30according to the first preferred embodiment. Thus, the detailed description thereof will not be repeated in the present preferred embodiment.

2. Mounting Structure of Multilayer Ceramic Capacitor

The following describes a mounting structure of the multilayer ceramic capacitor according to the second preferred embodiment of the present invention with reference toFIGS.21and22.

As shown inFIGS.21and22, a mounting structure200of the multilayer ceramic capacitor according to the second preferred embodiment includes multilayer ceramic capacitor110and mounting substrate50according to the second preferred embodiment. Mounting substrate50includes a core member51and a conductor land52of the substrate. Since core member51and conductor land52in the substrate of mounting substrate50are the same as those in mounting structure100of the multilayer ceramic capacitor according to the first preferred embodiment, the detailed description thereof will not be repeated in the present preferred embodiment.

Mounting structure200of the multilayer ceramic capacitor shown inFIGS.21and22is mounted on mounting substrate50such that second main surface12bof multilayer ceramic capacitor110faces substrate-side mounting surface51a. This implements electrical connection between multilayer ceramic capacitor110and mounting substrate50in the state in which the distance from substrate-side mounting surface51aof mounting substrate50to each of first and second extending portions27aand27brespectively extending from first and second side surfaces12cand12dis reduced or minimized.

Further, in mounting structure200of the multilayer ceramic capacitor shown inFIGS.21and22, third external electrode130cis contiguously disposed on the second main surface12bside of multilayer body12. Accordingly, multilayer ceramic capacitor110is mounted on mounting substrate50such that second main surface12bof multilayer ceramic capacitor110faces substrate-side mounting surface51a, to thereby achieve an effect that the self-alignment effect is readily exerted even if mounting misalignment occurs when multilayer ceramic capacitor110is mounted on the substrate.

Accordingly, in mounting structure200of multilayer ceramic capacitor110shown inFIGS.21and22, various functions of multilayer ceramic capacitor110according to the second preferred embodiment of the present invention described above are reflected as they are, and thereby, the current path from second internal electrode layer16bof multilayer ceramic capacitor110to mounting substrate50can be shortened as compared with the conventional case. As a result, various effects of multilayer ceramic capacitor110according to the second preferred embodiment of the present invention are reflected to achieve the effect of improving the low ESL characteristics in the mounting structure of the multilayer ceramic capacitor.

3. Method of Manufacturing Multilayer Ceramic Capacitor

The following describes a method of manufacturing multilayer ceramic capacitor110according to the second preferred embodiment of the present invention. Since the method of manufacturing multilayer body12is the same as the method of manufacturing multilayer ceramic capacitor10according to the first preferred embodiment, a method of forming external electrode130on multilayer body12will be hereinafter described.

Underlying Electrode Layer

Third underlying electrode layer132cof third external electrode130cis formed on each of first side surface12cand second side surface12dof multilayer body12obtained by firing. When a baked layer is formed as underlying electrode layer132, a conductive paste including a glass component and a metal component is applied and then baked to thereby form a baked layer as underlying electrode layer132. The baking temperature at this time is preferably about 700° C. or higher and about 900° C. or lower. In the present preferred embodiment, underlying electrode layer132is formed of a baked layer.

In this case, various methods can be used as a method of forming a baked layer. Example of the method used herein include a method of adjusting the direction of multilayer body12by a camera or a magnet such that second main surface12bis located below, and then holding multilayer body12with a holding jig and extruding the conductive paste through a slit or a hole so as to be applied. In the case of this method, by increasing the extrusion amount of the conductive paste, third underlying electrode layer132ccan be formed not only on second main surface12bbut also on a portion of first side surface12cand a portion of second side surface12dso as to cover second internal electrode layer16bexposed at first and second side surfaces12cand12d. Further, a roller transfer method can also be used. In the case of the roller transfer method, when third underlying electrode layer132cis formed not only on second main surface12bbut also on a portion of first side surface12cand a portion of second side surface12dso as to cover second internal electrode layer16bexposed at first and second side surfaces12cand12d, the pressing pressure during roller transfer is increased, so that third underlying electrode layer132ccan be formed on a portion of first side surface12cand a portion of second side surface12dso as to cover second internal electrode layer16bexposed at first and second side surfaces12cand12d.

Then, first underlying electrode layer132aof first external electrode130ais formed on first end surface12eof multilayer body12obtained by firing, and second underlying electrode layer132bof second external electrode130bis formed on second end surface12fof multilayer body12.

In the present preferred embodiment, first underlying electrode layer132aand second underlying electrode layer132bare formed by a DIP method so as to extend not only to reach first end surface12eand second end surface12fbut also to reach a portion of first main surface12a, a portion of second main surface12b, a portion of first side surface12c, and a portion of second side surface12d.

In the baking treatment, first underlying electrode layer132aof first external electrode130a, second underlying electrode layer132bof second external electrode130b, and third underlying electrode layer132cof third external electrode130cmay be baked simultaneously, or first underlying electrode layer132aof first external electrode130a, second underlying electrode layer132bof second external electrode130b, and third underlying electrode layer132cof third external electrode130cmay be baked separately.

Conductive Resin Layer

In the case where underlying electrode layer132is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. Note that the conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may alone be directly formed on multilayer body12without forming the baked layer.

As a method of forming a conductive resin layer, a conductive resin paste including a thermosetting resin and a metal component is applied on the baked layer or multilayer body12, and subjected to heat treatment at a temperature of about 250° C. or higher and about 550° C. or lower to thermally cure the resin to thereby form a conductive resin layer. At this time, the atmosphere during the heat treatment is preferably an N2 atmosphere. In order to prevent scattering of the resin and to prevent oxidation of various metal components, the oxygen concentration is preferably suppressed to be about 100 ppm or less, for example.

Examples of the method of applying a conductive resin paste may include a method of extruding the conductive resin paste through a slit so as to be applied or a roller transfer method, similarly to the method of forming underlying electrode layer132from a baked layer.

Thin Film Layer

When underlying electrode layer132is formed of a thin film layer, masking or the like is performed, and as a result, underlying electrode layer132can be formed by a thin film forming method such as a sputtering method or a vapor deposition method at a position where external electrode30is desired to be formed. Underlying electrode layer132formed of a thin film layer is provided such that metal particles are deposited to form a layer of about 1 μm or less, for example.

Plating Layer

Further, external electrode130may be formed only of a plating layer without providing underlying electrode layer132. In this case, external electrode130can be formed by the following method.

First end surface12eand second end surface12fof multilayer body12are plated to form a lower plating electrode in the portion where first internal electrode layer16ais exposed. Similarly, first side surface12cand second side surface12dof multilayer body12are plated to form a lower plating electrode in the portion where second internal electrode layer16bis exposed. In the plating treatment, either electrolytic plating or electroless plating may be adopted, but electroless plating requires a pretreatment with a catalyst or the like in order to improve the plating precipitation speed, which disadvantageously complicates the process. Thus, it is usually preferable to use electrolytic plating. As a plating method, barrel plating is preferably used. Further, an upper plating electrode formed on the surface of the lower plating electrode may be similarly formed as required.

Finally, plating layer134is formed. Plating layer134may be formed on the surface of underlying electrode layer132or may be formed directly on multilayer body12. In the present preferred embodiment, plating layer134is formed on the surface of underlying electrode layer132. More specifically, an Ni plating layer as a lower plating layer and an Sn plating layer as an upper plating layer are formed on underlying electrode layer132. In the plating treatment, either electrolytic plating or electroless plating may be adopted. However, electroless plating requires a pretreatment with a catalyst or the like in order to improve the plating precipitation speed, which disadvantageously complicates the process. Thus, it is usually preferable to use electrolytic plating.

As described above, multilayer ceramic capacitor110according to the present preferred embodiment is manufactured.

Although the preferred embodiments of the present invention have been disclosed as above in the aforementioned description, the present invention is not limited thereto.

In other words, various modifications can be made to the above-described preferred embodiments with regard to mechanisms, shapes, materials, number and quantities, positions, arrangements, or the like without departing from the scope of the present invention, and are included in the present invention.

Preferred embodiments of the present invention relates to multilayer ceramic capacitors and mounting structures of the multilayer ceramic capacitors, and particularly can be utilized as multilayer ceramic capacitors and mounting structures of the multilayer ceramic capacitors that are capable of fully achieving a sufficient heat dissipation effect and a low ESL effect while decreasing a capacitance and yet suppressing an increase in DC resistance.