Global network computers

An apparatus for a network of computers is presented. A plurality of inner firewalls operate within a personal computer. The personal computer operates in a network of computers and includes at least one microprocessor and at least two memory components. The plurality of inner firewalls deny access to a first memory component of the personal computer by another computer through a network connection with the personal computer during a shared operation. The plurality of inner firewalls also allow access to a second memory component of the personal computer by the other computer through the network connection with the personal computer during the shared operation.

BACKGROUND OF THE INVENTION

This invention relates generally to one or more computer networks that include computers, such as personal computers (PC's) or network computers such as servers, which have microprocessors linked by broadband transmission means and have hardware, software, firmware, and other means such that at least two parallel processing operations occur that involve at least two sets of computers in the network or in interconnected networks. This invention constitutes a form of metacomputing.

More particularly, this invention relates to one or more large networks, like the Internet, which comprise smaller networks and large numbers of interconnected computers, wherein multiple separate parallel or massively parallel processing operations involving multiple different sets of computers occur simultaneously. Even more particularly, this invention relates to one or more such networks wherein multiple parallel or massively parallel microprocessing processing operations occur separately or in an interrelated fashion, and wherein ongoing network processing linkages are established between virtually any microprocessors of separate computers connected to the network.

Still more particularly, this invention relates generally to a network structure or architecture that enables the shared use of network microprocessors for parallel processing, including massive parallel processing, and other shared processing such as multitasking, wherein personal computer owners provide microprocessor processing power to a network, such as for parallel or massively parallel processing or multitasking, in exchange for network linkage to other personal computers and other computers supplied by network providers such as Internet Service Providers (ISP's), including linkage to other microprocessors for parallel or other processing such as multitasking. The financial basis of the shared use between owners and providers may be whatever terms to which the parties agree, subject to governing laws, regulations, or rules, including payment from either party to the other based on periodic measurement of net use or provision of processing power like a deregulated electrical power grid or involving no payment. The network system may provide an essentially equivalent usage of computing resources by both users and providers since any network computer operated by either entity is potentially both a user and provider of computing resources alternately or simultaneously, assuming multitasking is operative. A user may have an override option exercised on the basis of, for example, a user profile, a user's credit line, or relatively instant payment.

This invention also relates to a network system architecture including hardware and software that provides use of the Internet or other network, without cost, to users of personal computers or other computers, while also providing users with computer processing performance that at least doubles every 18 months through metacomputing means. This metacomputing performance increase provided by the new Grid (or MetaInternet) is in addition to other performance increases, such as those already anticipated by Moore's Law.

The computer industry has been governed over the last 30 years by Moore's Law, which holds that the circuitry of computer chips shrinks substantially each year, yielding a new generation of chips every 18 months with twice as many transistors, such that microprocessor computing power effectively doubles every year-and-a-half.

The long-term trend in computer chip miniaturization is projected to continue unabated over the next few decades. For example, slightly more than a decade ago a 16 kilobit DRAM (dynamic random access memory) memory chip (storing 16,000 data bits) was typical; the standard in 1996 was the 16 megabit chip (16,000,000 data bits), which was introduced in 1993; and industry projections are for 16 gigabit memory chips (16,000,000,000 data bits) to be introduced in 2008 and 64 gigabit chips in 2011, with 16 terabit chips (16,000,000,000,000 data bits) conceivable by the mid-to-late 2020's. This is a thousand-fold increase regularly every fifteen years. Hard drive speed and capacity are also growing at a spectacular rate, even higher in recent years than that of semiconductor microchips.

Similarly, regular and enormous improvements may continue in microprocessor computing speeds, whether measured in simple clock speed or MIPS (millions of instructions per second) or numbers of transistors per chip. For example, performance has improved by four or five times every three years since Intel launched its X86 family of microprocessors used in the currently dominant “Wintel” standard personal computers. The initial Intel Pentium Pro microprocessor was introduced in 1995 and is a thousand times faster than the first IBM standard PC microprocessor, the Intel 8088, which was introduced in 1979. By 1996 the fastest of microprocessors, such as Digital Equipment Corporation's Alpha chip, and even the microprocessor of the Nintendo 64 video game system, were faster than the processor in the original Cray Y-MP supercomputer.

Microprocessors, software, firmware, and other components are also evolving from 8-bit and 16-bit systems into the 32-bit systems that are becoming the standard today, with some 64-bit systems like the DEC Alpha already introduced and more coming, such as Intel's Itanium microprocessor in 2001, with future increases to 128-bit systems likely.

A second major development trend in the past decade or so has been the rise of parallel processing, a computer architecture utilizing more than one CPU microprocessor linked together into a single computer with new operating systems having modifications that allow such an approach. Thousands of relatively simple microprocessors may be used together for massively parallel processing. The field of supercomputing has been overtaken by this approach, which includes designs utilizing many identical standard personal computer microprocessors.

Hardware, firmware, software, and other components specific to parallel processing are in a relatively early stage of development compared to that for single processor computing. Therefore, much further design and development are expected in the future to better maximize the computing capacity made possible by parallel processing. Continued improvement is anticipated in system hardware, software, and architectures for parallel processing so that reliance on the need for multiple microprocessors to share a common central memory is reduced, thereby allowing more independent operation of those microprocessors, each with their own discrete memory, like current personal computers, workstations, and most other computer systems architecture. For unconstrained operation, each individual microprocessor should have rapid access to sufficient memory.

Several models of personal computers having more than one microprocessor are now available. In the future, personal computers, broadly defined to include versions not currently in use, will likely also employ parallel computing utilizing multiple microprocessors or massively parallel computing with very large numbers of microprocessors. Future designs, such as Intel's Itanium chip, are expected to have a significant number of parallel processors on a single microprocessor chip.

A form of parallel processing called superscalar processing is also being employed within microprocessor design. The current generation of microprocessors, such as the Intel Pentium, have more than one data path within the microprocessor in which data is processed, with two to three paths being typical now and as many as eight in 1998 in IBM's new Power 3 microprocessor chip.

A third major development trend is the increasing size of bandwidth, which is a measure of communications power or transmission speed, in terms of units of data per second, between computers connected by a network. Previously, the local area networks and telephone lines typically linking computers including personal computers have operated at speeds much lower than the processing speeds of a personal computer. For example, a typical 1997 Intel Pentium operates at 100 MIPS, whereas the most common current Ethernet connecting PC's is roughly 10 times slower at 10 megabits per second (Mbps), although some Ethernet connections are now 100 Mbps and telephone lines are very much slower, the highest typical speed in 1998 being the approximately 56 kilobits reached during downloads.

The situation is expected to change dramatically. Bandwidth or transmission speed is anticipated to expand from 5 to 100 times as fast as the rise of microprocessor speeds, due to the use of coaxial cable, wireless, and especially fiber optic cable and optical wireless, instead of old telephone twisted pair lines, and due to the use of dense wave division multiplexing (DWDM). Telecommunication providers are now making available single fiber connections supporting a bandwidth of 40 gigabits per single fiber, and, alternatively, as many as 160 wavelength channels (lambdas) per single fiber.

Technical improvements are expected in the near term which will make it possible to carry over 2 gigahertz (billions of cycles per second) on each of 700 wavelength channels (lambdas), adding up to more than 1,400 gigahertz on a single fiber thread. Experts have estimated that the bandwidth of optical fiber has been utilized one million times less fully than the bandwidth of coaxial or twisted pair copper lines. Within a decade, 10,000 wavelength streams per fiber are expected; 20 to 80 wavelengths on a single fiber is already commercially available. The use of thin mirrored hollow wires or tubes called omniguides may also provide very substantial additional increases.

Other network connection developments, such as asynchronous transfer mode (ATM) and digital signal processors, whose price/performance ratio has improved tenfold every two years, are also supporting the rapid increase in bandwidth. The increase in bandwidth reduces the need for switching, and switching speed will be greatly enhanced when practical optical switches are introduced in the near future, potentially reducing costs substantially.

The result of this huge bandwidth increase is extraordinary: already it is technically possible to connect virtually any computer to a network with a bandwidth that equals or exceeds the computer's own internal system bus speed, even as that bus speed itself is increasing significantly. The principal constraint is the infrastructure, consisting mostly of connecting the “last mile” to personal computers with optical fiber or other broad bandwidth connections, which still need to be built. The system bus of a computer is its internal network connecting many or most of its internal components such as microprocessor, random access memory (RAM), hard drive, modem, floppy drive, and CD-ROM; for recent personal computers, the system bus has been only about 40 megabits per second, but is up to 133 megabits per second on Intel's Pentium PCI bus in 1995. IBM's 1998 Power3 microprocessor chip has a system bus of 1.6 gigabits per second and there is now up to a gigabit per second on Intel's Pentium PCI bus.

Despite these tremendous improvements anticipated in the future, a typical PC is already so fast that its microprocessor is essentially idle during most of the time the PC is in actual use, and the operating time itself is but a small fraction of those days the PC is even in use at all. Nearly all PC's are essentially idle during roughly all of their useful life. A microprocessor of a PC may be in an idle state 99.9% of the time, disregarding unnecessary microprocessor busywork such as executing screen saver programs, which have been made essentially obsolete by power-saving CRT monitor technology, which is now standard in the PC industry.

Because the reliability of PC's is so exceptionally high now, with the mean time to failure of all components typically several hundred thousand hours or more, the huge idle time of PC's represents a total loss; given the high capital and operating costs of PC's, the economic loss is very high. PC idle time does not in effect store a PC, saving it for future use, since the principle limiting factor to continued use of today's PC's is obsolescence, not equipment failure resulting from use.

Moreover, there is continuing concern that Moore's Law, which holds that the constant miniaturization of circuits results in a doubling of computing power every 18 months, cannot continue to hold true much longer. Indeed, Moore's Law may now be nearing its limits for silicon-based devices, perhaps by as early as 2010. No new technologies have yet emerged that seem to have the potential for development to a practical level by then, although many recent advances have the potential to maintain Moore's Law.

SUMMARY OF THE INVENTION

However, the confluence of all three of the established major trends summarized above-supercomputer-like personal computers, the spread of parallel processing using personal computer microprocessors (particularly massively parallel processing), and the enormous increase in network communications bandwidth—enables a solution to the excessive idleness problem of personal computers and the possible end of Moore's Law. The solution may achieve very high potential economic savings once the basic infrastructure connecting personal computers with optical fiber is in place in the relatively near future.

The solution is to use those mostly idle PC's (or their equivalents or successors) to build a parallel or massively parallel processing computer or computers utilizing a very large network, like the Internet or, more specifically, like the World Wide Web (WWW), or their equivalents or eventual successors like the Grid or MetaInternet (and including Internet II and the Next Generation Internet, which are under development now and which will utilize much broader bandwidth and will coexist with the Internet, the structure of which is in ever constant hardware and software upgrade and including the SuperInternet based on essentially all optical fiber transmission) with extremely broad bandwidth connections and virtually unlimited data transmission speed.

A prime characteristic of the Internet is the very large number of computers of all sorts already linked thereto, with the future potential for an effectively universal connection. The Internet is a network of networks of computers that provides nearly unrestricted access worldwide. The currently existing and soon-to-be widely available very broad bandwidth of network communications is used to link personal computers externally in a manner at least equivalent to, and probably much faster than, the faster internal system buses of the personal computers, so that no external processing constraint is imposed on linked personal computers by data input, output, or throughput; the speed of the microprocessor itself and the internal connections or buses of the PC are the only processing constraint of the system.

This makes possible efficient external parallel processing (and multitasking), including massively parallel processing, in a manner paralleling more conventional internal parallel processing, called superscalar processing.

In one embodiment, the World Wide Web is transformed into a huge virtual massively parallel processing computer or computers, with potential through its established hyperlinks connections to operate in a manner at least somewhat like a neural network or neural networks, since the speed of transmission in the broadband linkages is so great that any linkage between two microprocessors is virtually equivalent to direct, physically close connections between those microprocessors.

With further development, digital signal processor-type microprocessors and/or analogue microprocessors may be particularly advantageous for this approach, either alone or in conjunction with conventional microprocessors and/or the new microprocessors described below. Networks with WWW-type hyperlinks incorporating digital signal processor-type microprocessors could operate separately from networks of conventional microprocessors or with one or more connections between such differing networks or with relatively complete integration between such differing networks. Simultaneous operation across the same network connection structure should be possible, employing non-interfering transmission links.

Such extremely broad bandwidth networks of computers enable every PC within the network to be fully utilized or nearly so. Because of the extraordinary extent to which existing PC's are currently idle, at optimal performance this new system may result in a thousand-fold increase in computer power available to each and every PC user, and, on demand, almost any desired level of increased power, limited mostly by increased cost, which however are relatively far less than possible from other conceivable computer network configurations. This revolutionary increase is in addition to the extremely rapid, but evolutionary increases already occurring in the computer/network industry, as discussed above.

The metacomputing hardware and software means of the Grid (or MetaInternet) provides performance increases that are likely to at least double every eighteen months based on the doubling of personal computers shared in a typical parallel processing operation by a standard PC user, starting first with at least 2 PC's, then about 4, about 8, about 16, about 32, about 64, about 128, about 256, and about 512, for example. After about fifteen years, for example, it is anticipated that each standard PC user will likely be able to use a maximum of about 1,024 personal computers for parallel processing or any other shared computing use, while generally using for free the Internet or its successors, like the Grid (or MetaInternet). At the other end of the performance spectrum, supercomputers experience a similar performance increase generally, but ultimately the performance increase is limited primarily by the cost of adding network linkages to available PC's, so there is definite potential for a huge leap in supercomputer performance.

Network computer systems as described above offer almost limitless flexibility due to the abundant supply of heretofore idle connected microprocessors. This advantage allows “tightly coupled” computing problems, which normally are difficult to process in parallel, to be solved without knowing in advance how many processors are available (as is now necessary in relatively massively parallel processing), what they are, and their connection characteristics. A minimum number of equivalent processors (with equivalent other specifications) are easily found nearby in a massive network like the Internet and assigned within the network from those multitudes available nearby. Moreover, the number of microprocessors used are almost completely flexible, depending on the complexity of the problem, and limited only by cost. The existing problem of time delay is solved largely by the widespread introduction of broad bandwidth connections between computers processing in parallel.

The state of the known art relating to this application is summarized inThe Grid: Blueprint for a New Computing Infrastructure,edited by Ian Foster and Carl Kesselman, and published by Morgan Kaufman Publishers, Inc. in 1998. The state of the known art relating to this application is also summarized in:Scalable Parallel Computingby Kai Hwang and Zhiwei Xu, published by WCB McGraw-Hill in 1998;Parallel Programmingby Barry Wilkinson and Michael Allen, published by Prentice Hall in 1998;Computer Architecture: A Quantitative Approach(2nd Edition) by David Patterson and John Hennessy, published by Morgan Kaufmann in 1996;Parallel Computer Architectureby David Culler and Jaswinder Singh, published by Morgan Kaufman in 1998; andComputer Organization and Designby John Hennessy and David Patterson, published by Morgan Kaufman in 1998.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The new network computer utilizes PC's as providers of computing power to the network, not just users of network services. These connections between network and personal computer are enabled by a new form of computer/network financial structure that is rooted in the fact that economic resources being provided the network by PC owners (or leaser) are similar in value to those being provided by the network provider providing connectivity.

Unlike existing one-way functional relationships between PC users and network providers such as internet service providers, which often currently utilize telecommunications networks for connectivity, wherein the network provider provides access to a network like the Internet for a fee, much like cable TV services, this new relationship recognizes that the PC user is also providing the network access to the user's PC for parallel computing use, which has a similar value. The PC thus both provides and uses services on the network, alternatively or potentially even virtually simultaneously, in a multitasking mode.

This new network operates with a structural relationship that is roughly like that which presently exists between an electrical power utility and a small independent power generator connected to a deregulated utility's electrical power grid, wherein electrical power can flow in either direction between utility and independent generator depending on the operating decisions of both parties, and at any particular point in time each party is in either a debt or credit position relative to the other based on the net direction of that flow for a given period, and each party is billed accordingly. In the increasingly deregulated electrical power industry, electrical power, in terms of creation and transmission, is becoming a commodity bought and sold in a competitive marketplace that crosses traditional borders. With the structural relationship proposed herein for the new network, parallel free market structures can develop over time in a new computer power industry dominated by networks of personal computers in all their forms providing shared processing in a grid scaling almost seamlessly from local to national to international like an open market electrical power grid.

For this new network and its structural relationships, a network provider or Internet service provider (ISP) is defined in the broadest possible way as any entity (corporation or other business, government, not-for-profit, cooperative, consortium, committee, association, community, or other organization or individual) that provides personal computer users (very broadly defined below) with initial and continuing connection hardware and/or software and/or firmware and/or other components and/or services to any network, such as the Internet and WWW or Internet II or Next Generation Internet (NGI) or their present or future equivalents, coexistors, or successors, like the herein proposed Grid (or MetaInternet), including any of the current or future types of Internet access providers (ISP's) including telecommunication companies, television cable or broadcast companies, electrical power utilities or other related companies, satellite communications companies, or their present or future equivalents, coexistors or successors.

The connection means used in the networks of the network providers, including between personal computers or equivalents or successors, may be very broad bandwidth, including electromagnetic connections such as optical connections, including wired like fiber optic cable or wireless like optical wireless, for example, but not excluding any other electromagnetic or other means, including television coaxial cable and telephone twisted pair, as well as associated gateways, bridges, routers, and switches with all associated hardware and/or software and/or firmware and/or other components and their present or future equivalents or successors. The computers used by the Internet service providers include any current or future computers, including such current examples as mainframes, minicomputers, servers, and personal computers, and their associated hardware and/or software and/or firmware and/or other components, and their present or future equivalents or successors.

Other levels of network control beyond the Internet or other network service provider also exist to control any aspect of the parallel processing network structure and function, any one of which levels may or may not control and interact directly with the PC user. For example, at least one level of network control like the World Wide Web Consortium (W3C) or Internet Society (ISOC) or other ad hoc industry consortia establish and ensure compliance with any prescribed parallel processing network standards and/or protocols and/or industry standard agreements for any hardware and/or software and/or firmware and/or other component connected to the network. Under the consensus control of these consortia/societies, other levels of the parallel processing network control can deal with administration and operation of the network. These other levels of the parallel processing network control can potentially be constituted by any network entity, including those defined immediately above for network providers.

The principal defining characteristic of the parallel processing network herein described is communication connections (including hardware and/or software and/or firmware and/or other component) of any form, including electromagnetic (such as light and radio or microwaves) and electrochemical (and not excluding biochemical or biological), between PC users and their computers, with connection (either directly or indirectly) to the largest number possible of users and their computers and microprocessors being highly advantageous, such as networks like the Internet (and Internet II and the Next Generation Internet) and WWW and equivalents and successors, like the Grid (or MetaInternet). Multiple levels of such networks will likely coexist with different technical capabilities, like Internet and Internet II, but have interconnection and therefore communicate freely between levels, for such standard network functions as electronic mail, for example.

A personal computer (PC) user is defined in the broadest possible way as any individual or other entity routinely using a personal computer, which is defined as any computer, such as digital or analog or neural or quantum, particularly including personal use microprocessor-based personal computers having one or more microprocessors (each including one or more parallel processors) in their general current form, including hardware with fixed or reconfigurable circuitry (such as field-programmable gate array or FPGA) and/or electromechanical components (including micro or nano sized) and/or optical components, including all-optical, and/or software and/or firmware and/or any other component and their present and future equivalents or successors, such as application-specific (or several application) computers, network computers, handheld personal digital assistants, personal communicators such as telephones and pagers, wearable computers, digital signal processors, neural-based computers (including PC's), entertainment devices such as televisions and associated cable digital set-top control boxes, video tape recorders, video electronic games, videocams, compact or digital video disk (CD or DVD) player/recorders, radios and cameras, other household electronic devices, business electronic devices such as printers, copiers, fax machines, footwear, automobile or other transportation equipment devices, robots, toys, and other electronic devices, especially including those owned (or leased directly or indirectly) and used directly by individuals, utilizing one or more microprocessors, including those made of inorganic compounds such as silicon and/or other inorganic or organic (including biological, such as DNA) compounds, and other current or successor devices incorporating one or more microprocessors (or functional or structural equivalents), including routers, switches, and other network devices, as well as current and future forms of mainframe computers, minicomputers, workstations, and even supercomputers, as well as routers, switches, and other electrical or optical network devices (or microelectro-mechanical devices such as MEMS), that can be considered as PCs in the distributed processing network described herein, since they can be used functionally in the same general way in the network as a PC or a PC can be used to perform their functions, at least in a limited fashion alone or more effectively in numbers that are aggregated together or distributed. Such personal computers as defined above have owners or Teasers, which may or may not be the same as the computer users. Continuous connection of computers to the network, such as the Internet, WWW, or equivalents or successors, is not required, since connection can also be made at the initiation of a shared processing operation.

Parallel processing is defined as one form of shared processing involving two or more microprocessors used in solving the same computational problem or other task. Massively parallel microprocessor processing involves large numbers of microprocessors. In today's technology, massive parallel processing is probably to be considered to be about 64 microprocessors (referred to in this context as nodes) and over 7,000 nodes have been successfully tested in an Intel supercomputer design using PC microprocessors (Pentium Pros). It is anticipated that continued software improvements will make possible effective use of a much larger number of nodes, very possibly limited only by the number of microprocessors available for use on a given network, even an extraordinarily large one like the Internet or its equivalents and/or successors, like the Grid (or MetaInternet). Shared processing also includes multitasking, which is unrelated processing in parallel.

Broadband wavelength or broad bandwidth network transmission is defined here to mean a transmission speed (usually measured in bits per second) that is at least high enough (or roughly at least equivalent to the internal clock speed of the microprocessor or microprocessors times the number of microprocessor channels equaling instructions per second or operations per second or calculations per second) so that the processing input and output of the microprocessor is substantially unrestricted, particularly including at peak processing levels, by the bandwidth of the network connections between microprocessors that are performing some form of parallel processing, particularly including massive parallel processing. Since this definition is dependent on microprocessor speed, it increases as microprocessor speeds increase. For microchips with more than one processor, the network connection to the microchip may have bandwidth broad enough to ensure that all of the microprocessors are unrestricted by a bottleneck at the connection during the microprocessors' peak processing levels.

However, a connection means referenced above is a light wave or optical waveguide connection such as fiber optic cable, which in 1996 already provided multiple gigabit bandwidth on single fiber thread and is rapidly improving significantly on a continuing basis, so the general use of optical waveguide connections such as fiber between PCs may assure broad bandwidth for data transmission that is far greater than microprocessor and associated internal bus speed to provide data to be transmitted. In addition, new wired optical connections or waveguide in the form of thin, mirrored hollow wires or tubes called omniguides offer even much greater bandwidth than optical fiber and without need for amplification when transmitting over distances, unlike optical fiber. The connection means to provide broad bandwidth transmission is either wired or wireless, with wireless (especially optical) generally provided for mobile personal computers (or equivalents or successors) and as otherwise indicated below. Wireless connection bandwidth is also increasing rapidly and optical wireless bandwidth is considered to offer essentially the same benefit as fiber optic cable: data transmission speed that exceeds data processing speed.

The financial basis of the shared use between owners/leasers and providers is whatever terms to which the parties agree, subject to governing laws, regulations, or rules, including payment from either party to the other based on periodic measurement of net use or provision of processing power, in a manner like an deregulated or open market electrical power grid.

In one embodiment, as shown inFIG. 1, in order for this network structure to function effectively, there is a meter device5(comprising hardware and/or software and/or firmware and/or other component) to measure the flow of computing power between PC1user and network2provider, which may provide connection to the Internet and/or World Wide Web and/or Internet II and/or any present or future equivalent or successor3, like the Grid (or MetaInternet). In one embodiment, the PC user may be measured by some net rating of the processing power being made available to the network, such as net score on one or more standard tests measuring speed or other performance characteristics of the overall system speed, such as PC Magazine's benchmark test program, ZD Winstone (potentially including hardware and/or software and/or firmware and/or other component testing) or specific individual scores for particularly important components like the microprocessor (such as MIPS or millions of instructions per second) that may be of application-specific importance, and by the elapsed time such resources were used by the network. In the simplest case, for example, such a meter need measure only the time the PC was made available to the network for processing4, which can be used to compare with time the PC used the network (which is already normally measured by the provider, as discussed below) to arrive at a net cost; potential locations of such a meter include at a network computer such as a server, at the PC, and at some point on the connection between the two. Throughput of data in any standard terms is another potential measure.

In another embodiment, as shown inFIG. 2, there also is a meter device7(comprised of hardware and/or software and/or firmware and/or other component) that measures the amount of network resources6that are being used by each individual PC1user and their associated cost. This includes, for example, time spent doing conventional downloading of data from sites in the network or broadcast from the network6. Such metering devices currently exist to support billing by the hour of service or type of service, as is common in the public industry, by providers such as America Online, Compuserve, and Prodigy. The capability of such existing devices is enhanced to include a measure of parallel processing resources that are allocated by the Internet Service Provider or equivalent to an individual PC user from other PC users6, also measured simply in time. The net difference in time4between the results of meter5and meter7for a given period provides a reasonable billing basis.

Alternately, as shown inFIG. 3, a meter10also estimates to the individual PC user prospectively the amount of network resources needed to fulfill a processing request from the PC user to the network (provider or other level of network control) and associated projected cost, provides a means of approving the estimate by executing the request, and a realtime readout of the cost as it occurs (alternatively, this meter may be done only to alert9the PC user that a given processing request8falls outside normal, previously accepted parameters, such as level of cost). For an unusually deep search request, a priority or time limit and depth of search may be criteria or limiting parameters that the user can determine or set with the device, or that can be preset, for example, by the network operating system of the ISP or by the operating system of the PC or other components of the parallel processing system.

The network may involve no payment between users and providers, with the network system (software, hardware, etc.) providing an essentially equivalent usage of computing resources by both users and providers (since any network computer operated by either entity can potentially be both a user and provider of computing resources (even simultaneously, assuming multitasking), with potentially an override option by a user (exercised on the basis, for example, of user profile or user's credit line or through relatively instant payment).

As shown inFIGS. 4A-4C, the priority and extent of use of PC and other users may be controlled on a default-to-standard-of-class-usage basis by the network (provider or other) and overridden by the user decision on a basis prescribed by the specific network provider (or by another level of network control). One example of a default basis is to expend up to a PC's or other user's total credit balance with the provider described above and the network provider then to provide further prescribed service on a debt basis up to some set limit for the user; different users may have different limits based on resources and/or credit history.

A specific category of PC user based, for example, on specific microprocessor hardware owned or leased, may have access to a set maximum number of parallel PC's or microprocessors, with smaller or basic users generally having less access and vice versa. Specific categories of users may also have different priorities for the execution of their processing by the network other than the simplest case of first come, first served (until complete). A very wide range of specific structural forms between user and provider are possible, both conventional and new, based on unique features of the new network computer system of shared processing resources.

For example, in the simplest case, in an initial system embodiment, as shown inFIG. 4A, a standard PC1user request11for a use involving parallel processing may be defaulted by system software13, as shown inFIG. 4B, to the use of only one other essentially identical PC12microprocessor for parallel processing or multitasking, as shown inFIG. 4C; larger standard numbers of PC microprocessors, such as about three PC's at the next level, as shown in laterFIG. 10G(which could also illustrate a PC1user exercising an override option to use a level of services above the default standard of one PC microprocessor, presumably at extra cost), for a total of about four, then about 8, about 16, about 32, about 64, and so on, or virtually any number in between, is made available as the network system is upgraded in simple phases over time, as well as the addition of sophisticated override options. As the phase-in process continues, many more PC microprocessors can be made available to the standard PC user (virtually any number), starting at about 128, for example, then about 256, then about 512, then about 1024 and so on over time, as the network and all of its components are gradually upgraded to handle the increasing numbers. System scalability at even the standard user level is essentially unlimited over time.

For most standard PC users (including present and future equivalents and successors), connection to the Internet or present or future equivalents or successors like the Grid (or MetaInternet) may be at no cost to PC users, since in exchange for such Internet access the PC users can generally make their PC, when idle, available to the network for shared processing. Competition between Internet Service Providers (including present and future equivalents and successors) for PC user customers may be over such factors as the convenience and quality of the access service provided and of shared processing provided at no additional cost to standard PC users, or on such factors as the level of shared processing in terms, for example, of number of slave PC's assigned on a standard basis to a master PC. The ISP's can also compete for parallel processing operations, from inside or outside the ISP Networks, to conduct over their networks.

In addition, as shown inFIGS. 5A-5B, in another embodiment there is a (hardware and/or software and/or firmware and/or other) controlling device to control access to the user's PC by the network. In its simplest form, such as a manually activated electromechanical switch, the PC user could set this controller device to make the PC available to the network when not in use by the PC user. Alternatively, the PC user could set the controller device to make the PC available to the network whenever in an idle state, however momentary, by making use of multitasking hardware and/or software and/or firmware and/or other component (broadcast or “push” applications from the Internet or other network could still run in the desktop background).

Or, more simply, as shown inFIG. 5A, whenever the state that all user applications are closed and the PC1is available to the network14(perhaps after a time delay set by the user, like that conventionally used on screensaver software) is detected by a software controller device12installed in the PC, the device12signals15the network computer such as a server2that the PC available to the network, which could then control the PC1for parallel processing or multitasking by another PC. Such shared processing can continue until the device12detects an application being opened16in the first PC (or at first use of keyboard, for quicker response, in a multitasking environment), when the device12signals17the network computer such as a server2that the PC is no longer available to the network, as shown inFIG. 5B, so the network can then terminate its use of the first PC.

In the embodiment shown inFIG. 6, there is a (hardware and/or software and/or firmware and/or other component) signaling device18for the PC1to indicate or signal15to the network the user PC's availability14for network use (and whether full use or multitasking only) as well as its specific (hardware/software/firmware/other components) configuration20(from a status19provided by the PC) in sufficient detail for the network or network computer such as a server2to utilize its capability effectively. In one embodiment, the transponder device is resident in the user PC and broadcasts its idle state or other status (upon change or periodically, for example) or responds to a query signal from a network device.

Also, in another embodiment, as shown inFIG. 7, there is a (hardware/software and/or firmware and/or other component) transponder device21resident in a part of the network (such as network computer, switch, router, or another PC, for example) that receives22the PC device status broadcast and/or queries26the PC for its status, as shown inFIG. 7.

In one embodiment, as shown inFIG. 8, the network grid also has resident in a part of its hardware and/or software (and/or firmware and/or other components) a capacity such as to allow it to most effectively select and utilize the available user PC's to perform parallel processing initiated by PC users or the network providers or others. To do so, the network grid should have the (hardware and/or software and/or firmware and/or other component) capability of locating each PC accurately at the PC's position on the geographic grid lines/connection means23so that parallel processing occurs between PC's (PC1and PC12) as close together as possible, which should not be difficult for PC's at fixed sites with a geographic location, customarily grouped together into cells24, as shown inFIG. 8, but which requires an active system for any wireless microprocessor to measure its distance from its network relay site, as discussed below inFIG. 14.

One of the primary capabilities of the Internet (or Internet II or successor, like the Grid or MetaInternet) or WWW network computer is to facilitate searches by the PC user or other user. As shown inFIG. 9, searches are particularly suitable to multiple processing, since, for example, a typical search is to find a specific Internet or WWW site with specific information. Such site searches can be broken up geographically, with a different PC processor1′ allocated by the network communicating through a wired means99as shown (or wireless connections) to search each area, the overall area being divided into eight separate parts, as shown, which may be about equal, so that the total search would be about ⅛ as long as if one processor did it alone (assuming the PC1microprocessor provides control only and not parallel processing).

As a typical example, a single PC user might need 1,000 minutes of search time to find what is requested, whereas the network computer, using multiple PC processors, might be able to complete the search in 100 minutes using 10 processors, or 10 minutes using 100 processors or 1 minute using 1,000 processors (or even 1 second using 60,000 processors), assuming performance transparency, which should be achievable, at least over time, even for massive numbers of parallel processors. The parallel processing network's external parallel processing may be completely scalable, with virtually no theoretical limit.

The above examples also illustrates a tremendous potential benefit of network parallel processing. The same amount of network resources, 60,000 processor seconds, was expended in each of the equivalent examples. But by using relatively large multiples of processors, the network can provide the user with relatively immediate response with no difference in cost (or relatively little difference)—a major benefit. In effect, each PC user linked to the network providing external parallel processing becomes, in effect, a virtual supercomputer. As discussed below, supercomputers can experience a similar spectacular leap in performance by employing a thousand-fold (or more) increase in microprocessors above current levels.

Such power will likely be required for any effective searches in the World Wide Web (WWW). WWW is currently growing at a rate such that it is doubling every year, so that searching for information within the WWW will become geometrically more difficult in future years, particularly a decade hence, and it is already a very significant difficulty to find WWW sites of relevance to any given search and then to review and analyze the contents of the site.

In addition, many more large databases are being made Web accessible and the use of Extensible Markup Language (XML) will accelerate that trend. Moreover, existing search engine results list information from a prior general search and merely summarized on the web servers of search engine operators, whereas embodiments of the present invention allow a further contemporaneous specifically targeted search directed by the PC user utilizing search engine results only as a starting point for much greater depth and analysis allowed by the shared use of many other PC's in a parallel processing operation.

Therefore, the capability to search with massive parallel processing can dramatically enhance the capabilities of scientific, technological and medical researchers.

Such enhanced capabilities for searching (and analysis) can also fundamentally alter the relationship of buyers and sellers of any items and/or services. For the buyer, massive parallel network processing can make it possible to find the best price, worldwide, for any product or the most highly rated product or service (for performance, reliability, etc.) within a category or the best combination of price/performance or the highest rated product for a given price point and so on. The best price for the product can include best price for shipping within specific delivery time parameters acceptable to the buyer.

For the seller, such parallel processing can drastically enhance the search, worldwide, for customers potentially interested in a given product or service, providing very specific targets for advertisement. Sellers and producers can know their customers directly and interact with them directly for feedback on specific products and services to better assess customer satisfaction and survey for new product development.

Similarly, the vastly increased capability provided by the system's shared parallel processing can produce major improvements in complex simulations like modeling worldwide and local weather systems over time, as well as design and testing of any structure or product, from airliners and skyscrapers to new drugs and to the use of much more sophisticated artificial intelligence (AI) in medical treatment and in sorting through and organizing the PC users' voluminous input of electronic data from “push” technologies. Improvements in games also result, especially in terms of realistic simulation and realtime interactivity.

The Internet or WWW network computer system like the Grid (or MetaInternet) can put into the hands of the PC user an extraordinary new level of computer power vastly greater than the most powerful supercomputer existing today. The world's total of microchips was already about 350 billion in 1997, of which about 15 billion are microprocessors of some kind; most are fairly simple “appliance” type microchips running wrist watches, televisions, cameras, cars, telephones, etc. Assuming growth at its current rates, in a decade the Internet/Internet II/WWW may have a billion individual PC users, each providing an average total of at least 10 highly sophisticated microprocessors (assuming PC's with at least 4 microprocessors (or more, such as 16 microprocessors or 32, for example) and associated other handheld, home entertainment, and business devices with microprocessors or digital processing capability, like a digital signal processor or successor devices. That results in a global computer a decade from now made of at least 10 billion microprocessors, interconnected by broad bandwidth electromagnetic wave means at speeds approaching the speed of light.

In addition, the exceptionally numerous special purpose “appliance” microprocessors noted above, especially those that operate now intermittently like personal computers, may be designed to the same basic consensus industry standard used for parallel microprocessors for PC's (or equivalents or successors) or for PC “systems on a chip”, discussed later inFIGS. 10A-H, so that all PCs and microprocessors function homogeneously or are homogeneous in the parallel processing Internet. If such PCs and appliance microprocessors are also connected by any broad bandwidth means including fiber optic cable or optical wireless or other wireless, then the number of parallel processors potentially available can increase roughly about 10 times, for a net potential “standard” computing performance of up to 10,000 times current performance within fifteen years, exclusive of Moore's Law routine increases. Web-based ubiquitous computing would become a reality, in terms either of direct connection to the Web or use of common Web standards.

Moreover, in an environment where all current intermittently operating microprocessors follow the same basic design standards so that all are homogeneous parallel processors, then although the cost per microprocessor increases somewhat, especially initially, the net cost of computing for all users falls drastically due to the general performance increase due to the use of billions of otherwise idle “appliance” microprocessors. Therefore, the overall system cost reduction compels a transformation of virtually all such microprocessors, which are currently specialty devices known as application-specific integrated circuits (ASICs), into general microprocessors (like PC's), with software and firmware providing most of their distinguishing functionality. As noted above, homogeneity of parallel (and multi-tasking) processing design standards for microprocessors and network, including local and Internet, may be employed, but heterogeneity is also a well established parallel processing alternative providing significant benefits compared to non-parallel processing.

A typical supercomputer today utilizing the latest PC microprocessors has less than a hundred. Using network linkage to all external parallel processing, a peak maximum of perhaps 1 billion microprocessors can be made available for a network supercomputer user, providing it with the power 10,000,000 times greater than is available using current conventional internal parallel processing supercomputers (assuming the same microprocessor technology). Because of its virtually limitless scalability mentioned above, resources made available by the network to the supercomputer user or PC user can be capable of varying significantly during any computing function, so that peak computing loads can be met with effectively whatever level of resources are necessary.

In summary, regarding monitoring the net provision of power between PC and network,FIGS. 1-9show embodiments of a system for a network of computers, including personal computers, comprising: means for network services including browsing functions, as well as shared computer processing such as parallel processing, to be provided to the personal computers within the network; at least two personal computers; means for at least one of the personal computers, when idled by a personal user, to be made available temporarily to provide the shared computer processing services to the network; and means for monitoring on a net basis the provision of the services to each personal computer or to the personal computer user. In addition,FIGS. 1-9show embodiments including where the system is scalar in that the system imposes no limit to the number of the personal computers, including at least 1024 personal computers; the system is scalar in that the system imposes no limit to the number of personal computers participating in a single shared computer processing operation, including at least 256 personal computers; the network is connected to the Internet and its equivalents and successors, so that the personal computers include at least a million personal computers; the network is connected to the World Wide Web and its successors; the network includes at least one network server that participates in the shared computer processing; the monitoring means includes a meter device to measure the flow of computing power between the personal computers and the network; the monitoring means includes a means by which the personal user of the personal computer is provided with a prospective estimate of cost for the network to execute an operation requested by the personal user prior to execution of the operation by the network; the system has a control means by which to permit and to deny access to the personal computers by the network for shared computer processing; access to the personal computers by the network is limited to those times when the personal computers are idle; and the personal computers having at least one microprocessor and communicating with the network through a connection means having a speed of data transmission that is at least greater than a peak data processing speed of the microprocessor.

Also, relative to maintaining a standard cost,FIGS. 1-9show embodiments of a system for a network of computers, including personal computers, comprising: means for network services including browsing functions, as well as shared computer processing such as parallel processing, to be provided to the personal computers within the network; at least two personal computers; means for at least one of the personal computers, when idled by a personal user, to be made available temporarily to provide the shared computer processing services to the network; and means for maintaining a standard cost basis for the provision of the services to each personal computer or to the personal computer user. In addition,FIGS. 1-9show embodiments including where the system is scalar in that the system imposes no limit to the number of personal computers, including at least 1,024 personal computers; the system is scalar in that the system imposes no limit to the number of the personal computers participating in a single shared computer processing operation, including at least 256 personal computers; the network is connected to the Internet and its equivalents and successors, so that the personal computers include at least a million personal computers; the standard cost is fixed; the fixed standard cost is zero; the means for maintaining a standard cost basis includes the use of making available a standard number of personal computers for shared processing by personal computers; the network is connected to the World Wide Web and its successors; the personal user can override the means for maintaining a standard cost basis so that the personal user can obtain additional network services; the system has a control means by which to permit and to deny access to the personal computers by the network for shared computer processing; the personal computers having at least one microprocessor and communicating with the network through a connection means having a speed of data transmission that is at least greater than a peak data processing speed of the microprocessor.

Browsing functions generally include functions like those standard functions provided by current Internet browsers, such as Microsoft Explorer 3.0 or 4.0 and Netscape Navigator 3.0 or 4.0, including at least access to searching World Wide Web or Internet sites, exchanging E-Mail worldwide, and worldwide conferencing; an intranet network uses the same browser software, but may not include access to the Internet or WWW. Shared processing includes parallel processing and multitasking processing involving more than two personal computers, as defined above. The network system is entirely scalar, with any number of PC microprocessors potentially possible.

As shown inFIGS. 10A-10F, to deal with operational and security issues, it may be beneficial for individual users to have one microprocessor or equivalent device that is designated, permanently or temporarily, to be a master30controlling device (comprising hardware and/or software and/of firmware and/or other component) that remains inaccessible (using, for example, a hardware and/or software and/or firmware and/or other component firewall50) directly by the network but which controls the functions of the other slave microprocessors40when the network is not utilizing them.

For example, as shown inFIGS. 10A, a typical PC1may have four or five microprocessors (even on a single microprocessor chip), with one master30and three or four slaves40, depending on whether the master30is a controller exclusively (through different design of any component part), requiring four slave microprocessors40; or the master microprocessor30has the same or equivalent microprocessing capability as a slave40and multiprocesses in parallel with the slave microprocessors40, thereby requiring only three slave microprocessors40. The number of PC slave microprocessors40can be increased to virtually any other number, such as at least about eight, about 16, about 32, about 64, about 128, about 256, about 512, about 1024, and so on. These multiples are not required, and the number of PC master microprocessors30may be increased. Also included is an internal firewall50between master30and slave40microprocessors. As shown in precedingFIGS. 1-9, the PC1inFIG. 10Amay be connected to a network computer2and to the Internet or WWW or present or future equivalent or successor3, like the Grid (or MetaInternet).

Other typical PC hardware components such as hard drive61, floppy diskette drive62, compact disk-read only memory (CD-ROM)63, digital video disk (DVD)64, Flash memory65, random access memory (RAM)66, video or other display67, graphics card68, and sound card69, as well as digital signal processor or processors, together with the software and/or firmware stored on or for them, can be located on either side of internal firewall50, but such devices as the display67, graphics card68and sound card69and those devices that both read and write and have non-volatile memory (retain data without power and generally have to be written over to erase), such as hard drive61, Flash memory65, floppy diskette drive62, read/write CD-ROM63or DVD64may be located on the PC user side of the internal firewall50, where the master microprocessor is also located, as shown inFIG. 10A, for security reasons; their location can be flexible, with that capability controlled such as by password-authorized access.

Alternately, any of these devices that are duplicative (or for other exceptional needs) like a second hard drive61′, can be located on the network side of the internal firewall50. RAM66or equivalent or successor memory, which typically is volatile (data is lost when power is interrupted), should generally be located on the network side of the internal firewall50, but some can be located with the master microprocessor to facilitate its independent use.

However, read-only memory (ROM) devices including most current CD drives (CD-ROM's)63′ or DVD's (DVD-ROM) drives64′ can be safely located on the network side of the internal firewall50, since the data on those drives cannot be altered by network users; preemptive control of use may remain with the PC user.

However, at least a portion of RAM can be kept on the Master30microprocessor side of the internal firewall50, so that the PC user can retain the ability to use a core of user PC1processing capability entirely separate from any network processing. If this capability is not desired, then the master30microprocessor can be moved to the network side of the internal firewall50and replaced with a simpler controller on the PC1user side, like the master remote controller31discussed below and shown inFIG. 10I.

The master microprocessor30may also control the use of several or all other processors60owned or leased by the PC user, such as home entertainment digital signal processors70, especially if the design standards of such microprocessors in the future conform to the requirements of network parallel processing as described above. In this general approach, the PC master processor uses the slave microprocessors or, if idle (or working on low priority, deferable processing), makes them available to the network provider or others to use. Wireless connections100, including optical wireless, are expected to be extensively used in home or business network systems, including use of a master remote controller31without (or with) microprocessing capability, with broad bandwidth connections such as fiber optic cable connecting directly to at least one component such as a PC1, shown in a slave configuration, of the home or business personal network system; that connection links the home system to the network2such as the Internet 3, as shown inFIG. 10I. A business system may include broadband such as fiber optic or optical wireless links to most or all personal computers PC1and other devices with microprocessors, such as printers, copiers, scanners, fax machines, telephone and video conferencing equipment; other wired or wireless links also can be used.

A PC1user can remotely access his networked PC1by using another networked master microprocessor30on another PC1and using a password or other access control means for entry to his own PC1master microprocessor30and files, as is common now in Internet and other access. Alternately, a remote user can simply carry his own digitally stored files and his own master microprocessor or use another networked master microprocessor temporarily has his own.

In the simplest configuration, as shown inFIG. 10B, the PC1may have a single master microprocessor30and a single slave microprocessor40, separated by an internal firewall50, with both processors used in parallel or multitasking processing or with only the slave40so used, and connected with broad bandwidth such as optical fiber wire99to a network computer2and Internet 3 and successors like the Grid (or MetaInternet). Virtually any number of slave microprocessors40is possible. The other non-microprocessor components shown inFIG. 10Aabove may also be included in this simpleFIG. 10Bconfiguration.

As shown inFIG. 10C, microchips90are expected to integrate most or all of the other necessary computer components (or their present or future equivalents or successors), like a PC's volatile memory like RAM66(such as DRAM), graphics82, sound83, power management84, network communications85, and video processing86, possibly including modem87, non-volatile memory like flash (or magnetic like MRAM or ovonic unified memory)88, system BIOS88′, digital signal processor (DSP) or processors89, and other components or present or future equivalents or successors) and internal bus, on a single chip90(silicon, plastic, or other), known in the industry as “system on a chip”. Such a PC microchip90can have the same architecture as that of the PC1shown above inFIG. 10A: namely, a master control and/or processing unit93and one or more slave processing units94(for parallel or multitasking processing by either the PC1or the Network2), separated by an internal firewall50and connected by broad bandwidth wire99such as optical fiber cable to a network computer3and the Internet 3 and successors like the Grid (or MetaInternet). Alternatively, microchip90can be an “appliance” system on a chip.

Existing PC components with mechanical components like hard drive61, floppy or other removable diskette62, CD-ROM63, and DVD64, which are mass storage devices with mechanical features that will likely not become an integral part of a PC “system of a chip” may still be capable of connection to a single PC microchip90and control by a single PC master unit93.

In the simplest multi-processor case, as shown inFIG. 10D, the chip90has a single master unit93and at least one slave unit94(with the master having a controlling function only or a processing function also), separated by an internal firewall50and connected by broad bandwidth wire99such as fiber optic cable to a network computer3and the Internet 3 (and successors like the Grid or MetaInternet). The other non-microprocessor components shown inFIG. 10Aabove may also be included in this simpleFIG. 10Dconfiguration.

As noted above, any computer may be both a user and provider, alternatively—a dual mode operating capability. Consequently, any PC1within the network2, connected to the Internet 3 and successors like the Grid (or MetaInternet), can be temporarily a master PC30at one time initiating a parallel or multitasking processing request to the network2for execution by at least one slave PC40, as shown inFIG. 10E. At another time the same PC1can become a slave PC40that executes a parallel or multitasking processing request by another PC1′ that has temporarily assumed the function of master30, as shown inFIG. 10F. The simplest approach to achieving this alternation is for both master and slave versions of the parallel processing software to be loaded in each or every PC1that is to share in the parallel processing, so each PC1has the necessary software means, together with minor operational modifications, such as adding a switching means by which a signaled request for parallel processing initiated by one PC1user using master software is transmitted to at least a second PC1, triggering its slave software to respond by initiating parallel processing.

As shown inFIGS. 10G and 10H, which are parallel toFIGS. 10E and 10F, the number of PC slave processors40can be increased to any virtually other number, such as at least about 4; as shown, the processing system is completely scalar, so that further increases can occur to, for example, about eight, about 16, about 32, about 64, about 128, about 256, about 512, about 1024, and so on; the PC master microprocessors30can also be increased.

In summary, as noted above relative toFIG. 10I, a PC1can function as a slave PC40and be controlled by a master controller31, which can be remote and which can have limited or no microprocessing capability, but can as well have similar or greater capability. As shown inFIGS. 10J and 10K, such a master controller31is located on the PC user side of the internal firewall50, under the control of the PC user, while the microprocessors40reside on the network side of the internal firewall50. The master controller31may receive input from the PC user by local means such as keyboard, microphone, videocam or future hardware and/or software and/or firmware or other equivalent or successor interface means (as does a master processor40) that provides input to a PC1or microprocessor30originating from a user's hand, voice, eye, nerve or nerves, or other body part; in addition, remote access by telephone, cable, wireless or other connection may also be enabled by a hardware and/or software and/or firmware and/or other means with suitable security such as password controlled access. Similarly, as shown inFIGS. 10L and 10M, relative to a PC “system on a chip”, a master controller unit93′ (which could be capable of being accessed by the PC user through a remote controller31) with only a controlling capability can be located on the PC user side of the internal firewall50, under the control of the PC user, while the slave processor units94would reside on the network side of the internal firewall50.

FIGS. 10N and 10Oshow PC1with an internal firewall50that is configurable through either hardware and/or software and/or firmware and/or other means; software configuration is easiest and most typical, but active motherboard hardware configuration is possible and may present some security advantages, including a use of manual or electromechanical or other switches or locks.FIG. 10Nshows a CD-ROM63′ that has been placed by a PC user on the network side of an internal firewall50from a previous position on the PC user side of an internal firewall50, which was shown inFIG. 10A. The settings of an internal firewall50may default to those that safely protect the PC1from uncontrolled access by network users, but with capability for the relatively sophisticated PC user to override such default settings and yet with proper safeguards to protect the unsophisticated user from inadvertently doing so; configuration of an internal firewall50may also be actively controlled by a network administrator in a local network like that of a business, where a PC user may not be the owner or leaser of the PC being used, either by remote access on the network or with a remote controller31.

Similarly,FIGS. 10P and 10Qshow a PC “system on a chip”90with an internal firewall50that is configurable through either hardware and/or software and/or firmware and/or other means; software configuration is easiest and most typical. Active configuration of the integrated circuits of the PC microchip90is also possible and may present some speed and security advantages. Such direct configuration of the circuits of the microchip90to establish or change its internal firewall50could be provided by the use of field-programmable gate arrays (or FPGA's) or their future equivalents or successors; microcircuit electromechanical or other switches or locks can also be used potentially. InFIG. 10P, for example, slave processing unit94′ has been moved to the PC user side of an internal firewall50from a network side position shown inFIGS. 10C and 10L. Similarly,FIG. 10Qshows the same active configuration of chip circuit using FPGA's for the simplest form of multiprocessing microchip90with a single slave unit94′, transferring its position to the PC user's side of an internal firewall50from a network side shown inFIGS. 10M and 10D.

In summary, relative to the use of master/slave computers,FIGS. 10A-10Ishow embodiments of a system for a network of computers, including personal computers, comprising: at least two personal computers; means for at least one personal computer, when directed by its personal user, to function temporarily as a master personal computer to initiate and control the execution of a computer processing operation shared with at least one other personal computer in the network; means for at least one other personal computer, when idled by its personal user, to be made available to function temporarily as at least one slave personal computer to participate in the execution of a shared computer processing operation controlled by the master personal computer; and means for the personal computers to alternate as directed between functioning as a master and functioning as a slave in the shared computer processing operations. In addition,FIGS. 10A-10Hshow embodiments including those wherein the system is scalar in that the system imposes no limit to the number of personal computers; for example, the system can include at least 256 said personal computers; the system is scalar in that the system imposes no limit to the number of personal computers participating in a single shared computer processing operation, including at least 256 said personal computers, for example; the network is connected to the Internet and its equivalents and successors, so that personal computers include at least a million personal computers, for example; the shared computer processing is parallel processing; the network is connected to the World Wide Web and its successors; a means for network services, including browsing and broadcast functions, as well as shared computer processing such as parallel processing, are provided to said personal computers within said network; the network includes at least one network server that participates in the shared computer processing; the personal computers include a transponder or equivalent or successor means so that a master personal computer can determine the closest available slave personal computers; the closest available slave personal computer is compatible with the master personal computer to execute said shared computer processing operation; the personal computers having at least one microprocessor and communicating with the network through a connection means having a speed of data transmission that is at least greater than a peak data processing speed of the microprocessor; and a local network PC1being controlled remotely by a microprocessor controller31.

Use of the internal firewall50, as described above inFIGS. 10A-10I, provides a solution to a security problem by completely isolating host PC's1that are providing slave microprocessors to the network for parallel or other shared processing functions from any capability to access or retain information about any element about that shared processing. In addition, of course, the internal firewall50provides security for the host PC against intrusion by outside hackers; by reducing the need for encryption and authentication, the use of internal firewalls50can provide a relative increase in computing speed and efficiency. In addition to computers such as personal computers, the internal firewall50described above could be used in any computing device included in this application's above definition of personal computers, including those with “appliance”-type microprocessors, such as telephones, televisions or cars, as discussed above.

In summary, regarding the use of internal firewalls,FIGS. 10A-10Ishow embodiments of a system architecture for computers, including personal computers, to function within a network of computers, comprising: a computer with at least two microprocessors and having a connection means with a network of computers; the architecture for the computers including an internal firewall means for personal computers to limit access by the network to only a portion of the hardware, software, firmware, and other components of the personal computers; the internal firewall means will not permit access by the network to at least a one microprocessor having a means to function as a master microprocessor to initiate and control the execution of a computer processing operation shared with at least one other microprocessor having a means to function as a slave microprocessor; and the internal firewall means permitting access by the network to the slave microprocessor. In addition, the system architecture explicitly includes embodiments of, for example, the computer is a personal computer; the personal computer is a microchip; the computer has a control means by which to permit and to deny access to the computer by the network for shared computer processing; the system is scalar in that the system imposes no limit to the number of personal computers, including at least 256 said personal computers, for example; the network is connected to the Internet and its equivalents and successors, so that the personal computers include at least a million personal computers, for example; the system is scalar in that the system imposes no limit to the number of personal computers participating in a single shared computer processing operation, including at least 256 said personal computers, for example; the personal computers having at least one microprocessor and communicating with the network through a connection means having a speed of data transmission that is at least greater than a peak data processing speed of the microprocessor.

In summary, regarding the use of controllers with internal firewalls,FIGS. 10J-10Mshow embodiments of a system architecture for computers, including personal computers, to function within a network of computers, comprising for example: a computer with at least a controller and a microprocessor and having a connection means with a network of computers; the architecture for the computers including an internal firewall means for personal computers to limit access by the network to only a portion of the hardware, software, firmware, and other components of the personal computers; the internal firewall means will not permit access by the network to at least a one controller having a means to initiate and control the execution of a computer processing operation shared with at least one microprocessor having a means to function as a slave microprocessor; and the internal firewall means permitting access by the network to the slave microprocessor. In addition, the system architecture explicitly includes embodiments of, for example, the computer is a personal computer; the personal computer is a microchip; the computer has a control means by which to permit and to deny access to the computer by the network for shared computer processing; the system is scalar in that the system imposes no limit to the number of personal computers, including at least 256 said personal computers, for example; the network is connected to the Internet and its equivalents and successors, so that the personal computers include at least a million personal computers, for example; the system is scalar in that the system imposes no limit to the number of personal computers participating in a single shared computer processing operation, including at least 256 said personal computers, for example; the personal computers having at least one microprocessor and communicating with the network through a connection means having a speed of data transmission that is at least greater than a peak data processing speed of the microprocessor; and the controller being capable of remote use.

In summary, regarding the use of internal firewalls that can be actively configured,FIGS. 10N-10Qshow embodiments of a system architecture for computers, including personal computers, to function within a network of computers, comprising for example: a computer with at least two microprocessors and having a connection means with a network of computers; the architecture for the computers including an internal firewall means for personal computers to limit access by the network to only a portion of the hardware, software, firmware, and other components of the personal computers; the internal firewall means will not permit access by the network to at least a one microprocessor having a means to function as a master microprocessor to initiate and control the execution of a computer processing operation shared with at least one other microprocessor having a means to function as a slave microprocessor; the internal firewall means permitting access by the network to the slave microprocessor; the configuration of the internal firewall being capable of change by a user or authorized local network administrator; the change in firewall configuration of a microchip PC is made at least in part using field-programmable gate arrays or equivalents or successors. In addition, the system architecture explicitly includes embodiments of, for example, the computer is a personal computer; the personal computer is a microchip; the computer has a control means by which to permit and to deny access to the computer by the network for shared computer processing; the system is scalar in that the system imposes no limit to the number of personal computers, including at least 256 said personal computers; the network is connected to the Internet and its equivalents and successors, so that the personal computers include at least a million personal computers; the system is scalar in that the system imposes no limit to the number of personal computers participating in a single shared computer processing operation, including at least 256 said personal computers; the personal computers having at least one microprocessor and communicating with the network through a connection means having a speed of data transmission that may be at least greater than a peak data processing speed of the microprocessor.

PC1or PC microprocessors90may be designed homogeneously to the same basic consensus industry standard as parallel microprocessors for PC's (or equivalents or successors) as inFIGS. 10A-10Bor for PC “systems on a chip” discussed inFIGS. 10C-10D. Although the cost per microprocessor might rise somewhat initially, the net cost of computing for all users is expected to fall drastically almost instantly due to the significant general performance increase created by the new capability to use of heretofore idle “appliance” microprocessors. The high potential for very substantial benefit to all users may provide a powerful force to reach consensus on industry hardware, software, and other standards on a continuing basis for such basic parallel network processing designs utilizing the Internet 3 and WWW and successors. Such basic industry standards may be adopted at the outset of system design and for use of only the least number of shared microprocessors initially. Such basic industry homogeneous standards may be adopted at the outset and for the least number of shared microprocessors initially, and design improvements incorporating greater complexity and more shared microprocessors may be phased in gradually over time on a step-by-step basis, so that conversion to the Grid (or MetaInternet) or architecture at all component levels may be relatively easy and inexpensive. The scalability of the Grid (or MetaInternet) system architecture (both vertically and horizontally) as described herein makes this approach possible.

By 1998, manufacturing technology improvements allow 20 million transistors to fit on a single chip (with circuits as thin as 0.25 microns) and, in the next cycle, 50 million transistors using 0.18 micron circuits. That entire computer on a chip may be directly linked by fiber optic or wireless optic or other broad bandwidth connection means to the network so that the limiting factor on data throughput in the network system, or any part, may be only the speed of the linked microprocessors themselves, not the transmission speed of the network linkage. Such direct fiber or wireless optic linkage and integration of volatile memory (RAM like DRAM (dynamic random access memory) or equivalent), or non-volatile memory (like flash, magnetic, such as MRAM, or ovonic memory), on the “system on a chip” microchip obviates an increasingly unwieldy number of microchip connection prongs, which is currently in the three to four hundred range in the Intel Pentium and Pentium Pro series and will reach over a thousand prongs in the 1998 IBM Power3 microprocessor. One or more digital signal processors89and one or more all optical switches92located on a microprocessor90(or30or40), together with numerous channels and/or signal multiplexing (such as wave division) of the fiber optic signal can substitute for a vast multitude of microchip connection prongs.

For computers that are not reduced to a single chip, the internal system bus or buses of any such PC's may have a transmission speed that is at least high enough that all processing operations of the PC microprocessor or microprocessors are unrestricted (and other PC components like RAM such as DRAM) and that the microprocessor chip or chips are directly linked by fiber optic or other broad bandwidth connection, as with the system chip described above, so that the limiting factor on data throughput in the network system, or any part, is only the speed of the linked microprocessors themselves, not the transmission speed of the linkage.

The individual user PC's may be connected to the Internet (via an Intranet)/Internet II/WWW or successor, like the Grid (or MetaInternet) network by any electromagnetic means, such as with the very high transmission speed provided by the broad bandwidth of optical connections like fiber optic cable. Hybrid systems using fiber optic cable for trunk lines and coaxial cable to individual users may be used. Given the speed and bandwidth of transmission of fiber optic or equivalent or successor connections, conventional network architecture and structures should be acceptable for good system performance, making possible a virtual complete interconnection network between users.

However, the best speed for any parallel processing operation may be obtained, all other things being equal, by utilizing the available microprocessors that are physically the closest together. Consequently, as shown previously inFIG. 8, the network needs the means (through hardware and/or software and/or firmware and/or other component) to provide on a continually ongoing basis the capability for each PC to know the addresses of the nearest available PC's, perhaps sequentially, from closest to farthest, for the area or cell immediately proximate to that PC and then those cells of adjacent areas.

Network architecture that clusters PC's together is not mandatory and can be constructed by wired means. However, as shown inFIG. 11, it may be very beneficial to construct local network clusters101(or cells) of personal computers1′ by wireless100means, especially optical wireless and dense wave division multiplexing (DWDM), since physical proximity of any PC1to its closest other PC1′ may be easier to access directly that way, as discussed further below. Since optical wireless range is about 3 kilometers currently, large clusters communicating with broadband connections are possible. In addition, at least several network providers may serve any given geographic area to provide competitive service and prices.

Those wireless PC connections may be PC-resident and capable of communicating by wireless or wired (or mixed) means with all available PC's in the cluster or cell geographic area, both proximal and potentially out to the practical limits of the wireless transmission.

As shown inFIG. 12, wireless PC connections100can be made to existing non-PC network components, such as one or more satellites110, or present or future equivalent or successor components and the wireless transmissions can be conventional radio waves, such as infrared or microwave, or can utilize any other part of the electromagnetic wave spectrum, particularly optical, and can utilize dense wave division multiplexing (DWDM) to create numerous channels.

Moreover, as shown inFIG. 13, such a wireless or wired approach also makes it possible to develop network clusters101of available PC's1′ with complete interconnectivity; i.e., each available PC1in the cluster101may be connected wirelessly100(including optical wireless and DWDM) to every other available PC1in the cluster101, constantly adjusting to individual PC's becoming available or unavailable. Given the speed of some wired broad bandwidth connections, like fiber optic cable, such clusters101with virtual complete interconnectivity is certainly a possible embodiment even for PCs with wired connections.

As shown inFIG. 14A-14D, such wireless systems may include a wireless device120comprising hardware and/or software and/or firmware and/or other component, like the PC1availability device described above resident in the PC, but also with a network-like capability of measuring the relative distance from each PC1in its cluster101by that PC's signal transmission by transponder or its functional equivalent and/or other means to the nearest other PC's1′ in the cluster101. As shown inFIG. 14A, this distance measurement could be accomplished in a conventional manner between transponder devices120connected to each PC in the cluster101; for example, by measuring in effect the time delay from wireless transmission, optical or other and including DWDM, by the transponder device120of an interrogating signal105to request initiation of shared processing by a master PC1to the reception of a wireless transmission response106signaling availability to function as a slave PC from each of the idle PC's1′ in the cluster101that has received the interrogation signal105. The first response signal106′ received by the master PC1is from the closest available slave PC1″ (assuming the simplest shared processing case of one slave PC and one master PC), which is selected for the shared processing operation by the requesting master PC1, since the closer the shared microprocessor, the faster the speed of the wireless connections100is between sharing PC's (assuming equivalence of the connection means and other components among each of the PC's1′). The interrogation signal105may specify other selection criteria also, for example, for the closest compatible (initially perhaps defined by a functional requirement of the system to be an identical microprocessor) slave PC1″, with the first response signal106′ being selected as above.

This same transponder approach also can be used between PC's1″ connected by a wired99(or mixed wired/wireless) means, despite the fact that connection distances would generally be greater (since not line of sight, as is wireless), as shown inFIG. 14A, since the speed of transmission by broad bandwidth transmission means such as fiber optic cable is so high as to offset that greater distance. From a cost basis, this wired approach may be employed for such PC's already connected by broad bandwidth transmission means since additional wireless components like hardware and software are not necessary. In that case, a functionally equivalent transponder device120may be operated in wired clusters101in generally the same manner as described above for PC's connected in wireless clusters101. Networks incorporating PC's1connected by both wireless and wired (or mixed) means are anticipated, like the home or business network mentioned inFIG. 10I, with mobile PC's or other computing devices using wireless connections. Depending on distances between PC's and other factors, a local cluster101of a network2may connect wirelessly between PC's and with the network2through transponding means linked to wired broad bandwidth transmission means, as shown inFIG. 14C.

As shown inFIG. 14D, the same general transponder device means120can also be used in a wired100network system2employing network servers98operated, for example, by an ISP, or in any other network system architectures (including client/server or peer to peer) or any other topologies (including ring, bus, and star) either well known now in the art or their future equivalents or successors.

TheFIG. 14approach to establishing local PC clusters101for parallel or other shared processing avoids using network computers such as servers (and, if wireless, other network components including even connection means), so that the entire local system of PC's within a cluster101operates independently of network servers, routers, etc. Moreover, particularly if connected by wireless means, including optical wireless and DWDM, the size of the cluster101could be quite large, being limited generally by PC wireless transmission power, PC wireless reception sensitivity, and local and/or other conditions affecting transmission and reception. Additionally, one cluster101could communicate by wireless100means with adjacent, overlapping, or other clusters101, as shown inFIG. 14B, which could thereby include those beyond its own direct transmission range.

To improve response speed in shared processing involving a significant number of slave PC's1, a virtual potential parallel processing network for PC's1in a cluster101may be established before a processing request begins. This is accomplished by the transponder device120in each idle PC1, a potential slave, broadcasting by transponder120its available state when it becomes idle and/or periodically afterwards, so that each potential master PC1in the local cluster101is able to maintain relatively constantly its own directory121of the idle PC's1closest to it that are available to function as slaves. The directory121may contain, for example, a list of about the standard use number of slave PC's1for the master PC (which initially probably is just one other PC1″) or a higher number, listed sequentially from the closest available PC to the farthest. The directory of available slave PC's1may be updated on a relatively up-to-date basis, either when a change occurs in the idle state of a potential slave PC in the directory121or periodically.

Such ad hoc clusters101should be more effective by being less arbitrary geographically, since each individual PC is effectively in the center of its own ad hoc cluster. Scaling up or down the number of microprocessors required by each PC at any given time is also more seamless.

The complete interconnection provided by such ad hoc wireless clusters is also remarkable because such clusters mimic the neural network structure of the animal brain, wherein each nerve cell, called a neuron, interconnects in a very complicated way with the neurons around it. By way of comparison, the global network computer described above that is expected in a decade can have at least about 10 times as many PC's as a human brain has neurons and they can be connected by electromagnetic waves traveling at close to the speed of light, which is about 300,000 times faster than the transmission speed of human neurons (which, however, are much closer together).

As individual PC's continue to become much more sophisticated and more network oriented, compatibility issues may decrease in importance, since all major types of PC's will be able to emulate each other and most software, particularly relative to parallel processing, may no longer be hardware-specific. However, to achieve maximum speed and efficiency, it is beneficial to set compatible hardware, software, firmware, and other component standards to realize potential performance advantages attainable with homogeneous parallel processing components of the global network computer.

Until that compatibility or homogeneity is designed into the essential components of network systems, the existing incompatibility or heterogeneity of current components increases the difficulty involved in parallel processing across large networks. Even so, the use of message passing interfaces (MPI) and parallel virtual machines (PVM), for example, has made massively parallel processing between heterogeneous personal computers fairly easy for uncoupled operations, as shown for example in the Beowulf operating system, Globus, and the Legion system, from which has been derived Applied Meta. Programming languages like Java provide a partial means for dealing with the heterogeneity problem, whereas Linux provides greater speed and efficiency. In addition, using similar configurations of existing standards, like using PC's available on the Internet (with its vast resources) with a specific Intel Pentium chip with other identical or nearly identical PC components is probably the best way in the current technology to eliminate many of the serious existing problems that can easily be designed around using available technologies by adopting reasonable consensus standards for homogeneous specification of all parallel processing system components, both networks and computers. The potential gains to all parties with an interest far outweigh the potential costs.

The above described global network computer system has an added benefit of reducing the serious and growing problem of the nearly immediate obsolescence of PC and other computer hardware, software, firmware, and other components. Since the system above is the sum of its constituent parts used in parallel processing, each specific PC component becomes less critical. As long as access to the network utilizing sufficient bandwidth is possible, then all other technical inadequacies of the user's own PC can be completely compensated for by the network's access to a multitude of technically able PC's of which the user will have temporary use.

Although the global network computer will clearly cross the geographical boundaries of nations, its operation is not likely to be unduly bounded by inconsistent or arbitrary laws within those individual states. There will be considerable pressure on all nations to conform to reasonable system architecture and operational standards generally agreed upon, since the penalty of potential exclusion from a global network computer system like the Internet/WWW is potentially so high as to not be politically possible any in any country.

As shown inFIG. 15, because the largest number of user PC's are completely idle, or nearly so, during the night, it can be useful for the most complicated large scale parallel processing, involving the largest numbers of processors with uninterrupted availability as close together as possible, to be routed by the network to geographic areas of the globe undergoing night and to keep them there even as the Earth rotates by shifting computing resources as the world turns. As shown in the simplest case inFIG. 15, during the day, at least one parallel processing request by at least one PC1in a network2in the Earth's western hemisphere131is transmitted by very broad bandwidth connection wired99means such as fiber optic cable to the Earth's eastern hemisphere132for execution by at least one PC l′ of a network2′, which is idle during the night, and the results are transmitted back by the same means to network2and the requesting at least one PC1.

Any number of individual PC's within local networks like that operated by an ISP can be grouped into clusters or cells, as is typical in the practice of the network industry. As is common in operating electrical power grids and telecommunications and computer networks, many such processing requests from many PC's and many networks could be so routed for remote processing, with the complexity of the system growing substantially over time in a natural progression.

Alternatively, for greater security or simplicity, nighttime parallel processing can remain within a relatively local area and emphasize relatively massively parallel processing by larger entities such as business, government, or universities for relatively complicated applications that benefit from comparatively long nightly periods of largely uninterrupted use of significant numbers of slave personal computers PC1.

Any of the embodiments shown inFIGS. 1-15can be combined with one or more of any other ofFIGS. 1-15of this application to provide a useful improvement over the art.

While the conventional approach to configuring a network of personal computers PC1for parallel processing is simply to string them together in a simple bus-type architecture, as shown previously inFIG. 9,FIGS. 16A-16Zand16AA show a new hierarchical network topology.

Although theFIG. 9network structure is simple and produces reasonable results in loosely coupled problems like geographic searches described earlier, as a general approach it has at least three important problems.

First, as the number of personal computers PC1being used in the network grows, an increasingly greater deal of complex pre-operation planning and custom tailoring-type programming at the master PC1level is required to establish a means for allocating portions of the operation among the large number of available personal computers PC1′.

Second, operational results coming back to PC1from personal computers PC1′ are not synchronized, so that PC1frequently alternates between being idle and being overwhelmed. When the number of personal computers PC1′ is very large, both problems can be significant; when the number is massive, the problems can be overwhelming and seriously degrade the operation of the network.

Third, generally there are no means established for personal computers PC1′ to communicate or cooperate with each other during such network operations, so sharing operational results during processing between personal computers PC1′ is usually not feasible, especially when large numbers of PC1are involved. Consequently, closely coupled problems are generally not amenable to solution by conventional parallel processing by computers using a simple bus-type network likeFIG. 9.

The new hierarchical network topology shown inFIG. 16Ais a simple subdivision step whereby a personal computer PC1(or equivalent PC on a microprocessor chip90) or microprocessor30acting as a master M1divides a given operation into two parts (for example, two halves), then sends by an optical or electrical connection such as optical fiber or wire99the one half parts to each of two connected available slave personal computers PC1(or PC microprocessor90) or microprocessor30, as shown one processing level down as S21and S22. The topology ofFIG. 16A(and subsequentFIGS. 16) can be connected to the Internet 3 and World Wide Web, for example.

FIG. 16Bshows that slave personal computer PC1(or PC microprocessor90) or microprocessor40located at S21has temporarily adopted the same functional role as a master to repeat the same subdivision of the given operation. Therefore, having already been divided in half once inFIG. 16A, the given operation is again subdivided inFIG. 16B, this time in half into quarters of the original operation (for example) by S21, which then sends one quarter to each of two additional available slave personal computers PC1(or PC microprocessors90) or microprocessors40located at S31and S32.

FIG. 16Cshows personal computers PC1(or PC microprocessor90) or microprocessors40at S31and S32sending operational results back to S21after performing the processing required by the given operation, instead of repeating again the subdivision process. That processing action by S31and S32can be dictated by pre-established program criteria, for example by automatically defaulting to operational processing at the S3level after two subdivision processes as shown above, so that the operation can be processed in parallel by four available slave personal computers PC1(or PC microprocessors90) or microprocessors40. Alternately, as another example, the criteria can be a user preference command overriding an otherwise automatic default to level three processing in order to specify some other level of processing involving more or less slave PC1(or PC microprocessors90) or microprocessors40.

Similarly, inFIG. 16Aabove, the personal computer PC1(or PC microprocessor90) or microprocessor40acting as master M1also can initiate the parallel processing operation (or, alternatively, a multi-tasking operation) on the basis of preset program parameters through software, hardware, or firmware or other means; parameter examples again may be pre-set automatic default or user preference override.

LikeFIG. 16C,FIG. 16Dshows operational results being passed back to the next higher level, this time from slave personal computers PC1(or PC microprocessors90) or microprocessors40, S21and S22, to master personal computer PC1(or PC microprocessor90) or microprocessor30, M1, where the operation is completed after the S21and S22results are consolidated.

FIG. 16Gshows master personal computer PC1(or PC microprocessor90) or microprocessor30, M1, offloading by wireless connection100, such as optical wireless and DWDM for example, the entire parallel processing operation to an available slave personal computer PC1(or PC microprocessor90) or microprocessor40that temporarily functions as S1in the place of M1on the first processing level for the duration of the given parallel processing (or multi-tasking) operation, the first step of which the operation is shown inFIG. 16H, which is likeFIG. 16Aexcept as shown.

FIG. 16Ishows a personal computer PC1(or PC microprocessor90) or microprocessor40that is executing a command to function in the slave role of S21for a given operation but has become unavailable, or was unavailable initially (due, for example, to interruption for another higher priority command by its user or to malfunction), when results of the given operation from a lower parallel processing level are passed to S21. In that situation, S21(or S31or S32) can simply offload those results to another personal computer PC1(or PC microprocessor90) or microprocessor30(or40) that is then available and it can become S21and take over the role of S21in the given operation for the duration of that operation. Similarly, the role of any unavailable or malfunctioning master or slave PC1or microprocessor90,30, or40can be transferred to an available functioning one.

As shown inFIG. 16J, S21then completes the parallel processing operation and passes its portion of the operational results to M1.

The offloading capability of functional roles of master and slave personal computers PC1(and PC microprocessors90) and microprocessors30(and40) from unavailable to available PC1,30and40as shown inFIGS. 16G-16Jcan also be used in previous figures in this application. In the simplest case initially, all processing roles of personal computers PC1(and PC microprocessors90) and microprocessors (30or40), like S21, above can be determined at the beginning of an operation based on availability (based on non-use and lack of malfunctioning component) and remain unaltered until the end of the operation. But, with more sophisticated system software and hardware and firmware, during an operation any number of the processing roles can be offloaded from personal computers PC1(or PC microprocessors90) or microprocessors30(or40) to others as required, even multiple times and many simultaneously.

FIG. 16Eshows the multi-processing network topology ofFIGS. 16A-16Jin a larger scale embodiment, including all personal computers PC1(or PC microprocessors90) or microprocessors30(or40) that are participating in a typical operation, including in this example one personal computer PC1(or PC microprocessor90) or microprocessor30(or40) at level one; two at level two; four at level three; and eight at level four. The network topology is completely scalar in that any practical number of additional processing levels or personal computers PC1(or PC microprocessors90) or microprocessors30(or40) can be added to those shown. Topologies limited to just two (or three) levels are also possible, which is the simplest case of operation processing subdivision that distinguishes over the conventionalFIG. 9single level “string-together” architecture.

The number of processing personal computers PC1(or PC microprocessors90) or microprocessors40doubles at each additional processing level and therefore can be represented by 2N, where N is the last or final processing level, for the simplest case, as shown above, which is splitting one given operation into two parts such as halves between each level.

Instead of subdividing one operation as above, two separate parallel processing operations can be multi-tasked on separate branches, such as S21and S22as shown, using the same network architecture described above. As is clear from this example, any practical mix of multi-tasking and/or parallel processing is possible using the above network architecture.

FIG. 16Eshows the distribution of a given parallel processing (or multi-tasking) operation as routed through a four level virtual network, beginning at M1. “Virtual” as used here means temporary, since in the next parallel operation originating at M1it may be the case that many of the personal computers PC1(or microprocessors90) or microprocessors30(or40) that had been available for a previous operation would not still be available for the next operation.

FIG. 16Eshows a binary tree network architecture for the initial distribution of an operation from M1down through four slave processing levels, whileFIG. 16Fshows the subsequent processing and accumulation of results back from there to M1.FIG. 16Fshows an inverted view ofFIG. 16Eto show the sequence of the operation, from operation distribution inFIG. 16Eto result accumulation inFIG. 16F.

More specifically,FIG. 16Fshows the processing slave personal computers PC1(or PC microprocessors90) or microprocessors40at the fourth level, S41through S48, where they process the operation to produce results which are then routed back through two other levels of the virtual network to M1.

In the routing of operational results shown inFIG. 16F, each slave personal computer PC1(or PC microprocessor90) or microprocessor40has the capability to either simply pass through those results only as a direct communication link or connection; or, alternatively, for example, to consolidate those results sent from the personal computers PC1(or PC microprocessor90) or microprocessors40at a lower level; or, to provide additional other processing based on those lower processing level results.

Such consolidation or additional processing can reduce or eliminate duplicative data from a search or other operation producing duplicative results and can also serve to buffer the originating master M1from overloading caused by many sets of results arriving at M1in theFIG. 9single processing level architecture in an uncoordinated fashion from what may be a large number of slave personal computers PC1(or PC microprocessor90) or microprocessors40. Such a consolidation role for personal computers PC1(or PC microprocessor90) or microprocessors40substantially reduces or eliminates the excessive custom pre-planning and synchronization problems of the conventionalFIG. 9network topology discussed above.

FIG. 16Kshows a simple example indicative of the extremely complicated network structure that can result from subdividing a given operation in which the complexity of the operation involved is not uniform, due to, for example, variations in the data. In this example, pre-set program splitting criteria can be employed that balances the processing load of each slave personal computer PC1(or PC microprocessor90) or microprocessor40. With this approach, the complex portions of a given operation can automatically draw greater resources in the form of additional splitting of that more difficult portion of the problem, so that additional levels of parallel processing slave personal computers PC1(or PC microprocessors90) or microprocessors40can be brought into the virtual network to process the operation, as shown in the left branch ofFIG. 16K.

FIG. 16Kis a fairly simple example, but when the same kind of dynamic network structure is applied to a virtual network using many more personal computers PC1(or PC microprocessor90) or microprocessors30or40and many processing levels, involving both micro levels in PC microprocessor chips90and macro levels in personal computers PC1networks (such as shown later inFIG. 20B), then the potential complexity of the virtual network increases significantly. For example, each PC microprocessor chip90may have64slave microprocessors94on the final processing level; each personal computer PC1may have64slave PC microprocessor chips90at the final processing level, and the virtual network may include64personal computers PC1at the final processing level. With this large number of physical resources available (which can of course be very substantially greater) to the virtual network created by processing a given operation or operations, like that shown inFIG. 16K, it is clear that the operation itself can sculpt an incredibly complex virtual network that is custom tailored to the specific operation. All that is required is a operation subdivision process as described earlier that can be resident in each PC1(or PC microprocessor90) or microprocessor30or40, or that can be passed along with data (as can be operation application software) as the operation is executed.

Thus,FIG. 16Kshows an example of a highly flexible virtual network architecture that is capable of being dynamically configured in real time by the processing requirements imposed on the components of the network by a specific given operation and its associated data, as allowed by the network hardware/software/firmware architecture.

FIGS. 16L and 16Mshow examples of other possible subdivision parallel processing methods, such as subdivision routing to three slave personal computers PC1(or PC microprocessors90) or microprocessors40at the next level down, as shown inFIG. 16L, or subdivision routing to four slave personal computers PC1(or PC microprocessors90) or microprocessors40, as shown inFIG. 16M. Subdivision routing to any practical number of slave personal computers PC1(or PC microprocessors90) or microprocessors40between processing levels can be done.

Such routing subdivision can also vary between processing levels or even within the same processing level, as shown inFIG. 16N; these exemplary variations can result from pre-set program criteria such as those that balance operational loads, like those shown previously inFIG. 16K. The means for subdividing problems for parallel or multi-tasking processing can also vary, within at least a range of methods known in the computer and mathematical arts.

FIG. 16Oshows slave personal computer PC1(or PC microprocessor90) or microprocessor40, S41, sending operational results to a higher processing level, S31, which can then function as a router or as one or more high speed switch42(which can be located as92on a PC microprocessor90also, including as an all optical switch), passing through unaltered results back down to the original level to personal computer PC1(or PC microprocessor90) or microprocessor40, S42, as shown inFIG. 16P.FIG. 16Qdemonstrates the capability for any two pair of slave personal computers PC1(or PC microprocessors90) or microprocessors40like S41and S42to communicate directly between each other, including wired or wirelessly100as shown.FIGS. 16O-16Qshow the same subsection of the network topology shown inFIG. 16F(the left uppermost portion).

A personal computer PC1(or PC microprocessor90) or microprocessor30(or40) located on a higher processing level in the network architecture such as S31can process results as well as route them, as shown inFIG. 16V, in which S31receives results from S41and S42at a lower processing level and then processes that data before sending its processing results to a higher level to S21, as shown inFIG. 16W.

Together,FIGS. 16V-16Wand16O-16Q show the capability of any personal computer PC1(or PC microprocessor90) or microprocessor30(or40) of theFIG. 16F(and16E) network structural and functional invention to communicate with any other personal computer PC1(or PC microprocessor90) or microprocessor30(or40) participating in a given parallel processing (or multi-tasking) operation. That communication can take the form of simple pass-through of unmodified results or of modification of those results by processing at any level.

FIGS. 16X-16Zshow the applicant's new hierarchical network structure and function applied to the design of a personal computer PC1, as discussed previously inFIGS. 10A and 10B.FIG. 16Xshows the simplest general design, with a master M1microprocessor30and two slave S21and S22microprocessors40.FIG. 16Yshows the same network structure with an additional level of slave microprocessors40, S3through S34, whileFIG. 16Zshows the same network structure asFIG. 16Ywith an additional level of slave microprocessors40, S41through S48. As shown in these examples, this network structure is completely scalar, including any practical number of slave microprocessors40on any practical number of processing levels.

FIG.16AA shows a useful embodiment in which each microprocessor30and40has, in addition to internal cache memory, its own random access memory (RAM)66or equivalent memory (volatile like DRAM or non-volatile like Flash memory, magnetic such as MRAM memory, or ovonic unified memory), integrated on-microchip90or separate off-microchip. A significant amount of such microchip RAM (volatile like DRAM or non-volatile like Flash memory, magnetic such as MRAM memory, or ovonic unified memory), significantly greater than cache memory (SRAM) and other on-chip memory used on microprocessor chips today, can be beneficial in improving the efficient operation of the microprocessor; if located off microprocessor chip, the size of such memory can substantially exceed the size of the associated microprocessor, but an on-microprocessor chip location for DRAM or Flash (or MRAM or ovonic memory), like cache (SRAM) memory, offers the best potential for improving microprocessor speed and efficiency. The design can also incorporate (or substitute) conventional shared memory or RAM66′ (i.e. memory used by all, or some, of the microprocessors30or40(or90) of the personal computer PC1).

FIGS. 16R-16Tare parallel toFIGS. 16X-16Zabove, but show PC microprocessor90architecture rather than macro PC1architecture; a PC microprocessor90is as earlier described inFIG. 10C, a personal computer on a microchip.

FIG. 16Uis like FIG.16AA, also except for showing PC microprocessor90architecture instead of PC1architecture.FIG. 16Ushows a useful embodiment in which each PC microprocessor93or94has its own integrated on-microchip (or separate off microchip) random access memory (RAM)66or equivalent memory (volatile like DRAM or non-volatile, like Flash memory, magnetic such as MRAM memory, or ovonic unified memory). A significant amount of such RAM or other memory, significantly greater than cache (SRAM) memory or other on-microchip memory used on microprocessor chips today, can be beneficial in improving the efficient operation of the microprocessor; if located off-microprocessor chip, the size of such memory can substantially exceed the size of the associated microprocessor, but an on-microprocessor chip90location for DRAM or Flash (or MRAM or ovonic memory), like cache (SRAM) memory, offers the best potential for improving microprocessor speed and efficiency. The microchip design can also incorporate (or substitute) conventional shared memory or RAM66′ (i.e. memory used by all, or some, of the PC microprocessors93or94of the personal computer PC microprocessor90).

FIGS. 16R-16Ushow a different and improved basic microchip architecture which can exclude or reduce the currently used superscalar approach in microprocessors to execute multiple instructions during each clock cycle. TheFIGS. 16R-16Uarchitecture is much simpler and, by integrating memory with microprocessor, reduces memory bottlenecks. The simplicity of theFIGS. 16R-16Umicrochip design, which may have little or no superscalar components, compared to conventional superscalar designs (the inherent extreme complexity of which creates a very substantial memory overhead), can result in the use of a much greater proportion of independent, non-superscalar processors per microchip, exclusive of integrating memory or RAM66onto the microprocessor chip90, as discussed inFIG. 16U.

FIGS. 16X-16Zand16AA, by using the same architecture for PC1networks asFIGS. 16R-16U, import the same advantage of microchip parallel processing performance to parallel processing in PC1networks.

FIG.16AB shows a direct connection of optical fiber99from Internet 3 (or another network) to random access memory (RAM) microchip66′. The connection may be at a central portion140of RAM chip66′ to provide equal access to stored data on RAM chip66′. The direct connection can be anywhere on RAM chip66′. Digital signal processor (DSP)89is on RAM chip66′ for connection with optical fiber99. RAM chip66′ is for shared memory use among PC's1and for broadcast use. RAM chip66′ can include volatile or non-volatile (flash-type) memory. RAM chip66′ can have more than one DSP89, such as shown inFIG. 20B.

AllFIGS. 16A-16Zand16AA-16AB, like the preceding figures of this application, show sections of a network of personal computers PC1(or PC microprocessors90) or microprocessors30or40which can be parts of the WWW or Internet or Internet II or the Next Generation Internet (meaning connected to it) or Intranets or Extranets or other networks.

Also, except forFIGS. 16R-16Tand16X-16Z, all of theFIG. 16series show personal computers PC1and microprocessors30or40as occupying the same location. This dual representation was done for economy of presentation and to show the parallel functionality and interchangability in conceptual terms of personal computer PC1and microprocessors30or40in the structure of the new network. So, takingFIG. 16Aas an example, M1, S21and S22show three personal computers PC1or, alternatively, one microprocessor30and two microprocessors40.

As noted initially inFIG. 10C, a personal computer PC1can be reduced in size to a PC microprocessor chip90, so preceding Figures showing personal computer PC1also generally represent PC microprocessor chip90.

Finally,FIGS. 16A-16Zand16AA-16AB show a mix of electrical and optical connections, including wired99, especially connections such as optical glass fiber or omniguides, and wireless100, especially wireless optical (and mixtures of both in a single figure), and dense wave division multiplexing (DWDM). Generally, either99or100or a mix can be used relatively interchangeably in the network inventions shown (as well as in prior figures), though in some embodiments either highest transmission speed (i.e. broadest bandwidth) or mobility (or some other factor) may dictate a use of wired or wireless. Generally, fiber optic wire99and dense wave division multiplexing (DWDM) may provide the most advantageous transmission means because it has the greatest bandwidth or data transmission speed, so it may be used for connections between personal computers and microchips, including direct connections, although optical wireless100also offers very high bandwidth, especially with dense wave division multiplexing (DWDM). Other wireless100(but also including optical wireless), including with DWDM, can be used where mobility is a paramount design criteria.

TheFIG. 16embodiments can be combined with, or modified by incorporating, any other network system architectures (including client/server or peer to peer) or any other topologies (including ring, bus, and star) either well known now in the art or their future equivalents or successors.

Any of the embodiments shown inFIGS. 16A-16Zand16AA-16AB can be combined with any one or more of the preceding or subsequent figures of this application to provide a useful improvement over the art.

The parallel processing network architecture shown in the precedingFIGS. 16A-16Zand16AA-16AB and in earlier figures has several features unique to its basic design that provide for the security of personal computers PC1(or PC microprocessor90) or microprocessor40that share other computers for parallel and multi-tasking processing. First, the slave personal computers PC1(or microprocessors40) each have only part of the operation (for large operations, only a very small part) and therefore unauthorized surveillance of a single PC1can provide only very limited knowledge of the entire operation, especially in only a relatively local area in which switching or routing was employed. Second, the addresses of the slave personal computers PC1(or microprocessors40) are known or traceable, and therefore are not protected by anonymity (like hackers usually are) in case of unauthorized intervention. In addition, cryptography can be employed, with on microprocessor chip30,40, or90hardware55being used in some embodiments due to efficiency, although software and firmware can also be used, or a separate PC1hardware-based component56like an encryption microchip can be used; with either encryption component55or56, micro electromechanical locks can be used to prevent access other than by the direct physical user; other MicroElectroMechanical System (MEMS) devices located on microchips like PC90can be used for access prevention or other functions. Nonetheless, these inherent strengths can be substantially reinforced, as indicated inFIGS. 17B-17D.

FIG. 17Ashows at least one internal firewall50performing its conventional function of keeping out intruders such as hackers from the Internet 3 from unauthorized access for either surveillance of, or intervention in, a user's personal computer PC1(or PC microprocessor90) or master microprocessor30.

FIG. 17Bshows that, since Internet users can, as enabled by the applicant's network structure invention, use one or more of the slave microprocessors40of another's personal computer PC1(or PC microprocessor90) for parallel (or multi-tasking) processing, the at least one internal firewall50has a dual function in also protecting Internet3use (or other shared use on a network) from unauthorized surveillance or intervention by a PC1owner/user who is providing the shared resources. To maintain the privacy necessary to operate such a cooperatively shared network arrangement, unauthorized surveillance or intervention must be carefully prevented by hardware/software /firmware or other means.

FIG. 17Ctherefore shows master M personal computer PC1(or PC microprocessor90) using the slave S2microprocessor40of a different personal computer, PC1′, which is available for Internet 3 (or other net) shared use, while internal firewall50′ blocks unauthorized access into PC1′ by PC1(although PC1′ owner/user can always interrupt a shared operation and take back control and use of slave S′ microprocessor40, which then triggers off-loading action to compensate, as discussed above inFIGS. 16I-16J).

FIG. 17Dis similar toFIG. 17C, but shows a PC microprocessor90with a slave microprocessor94being used by Internet 3 users (or other net), so that at least one firewall50serves both to deny access such as surveillance by master M microprocessor93to an Internet 3 parallel processing (or multi-tasking) operation on slave S microprocessor94and to deny access to master M microprocessor93by Internet 3 (or other net) users of slave S microprocessor94. At least one internal firewall50may be implemented by non-configurable hardware at the microchip level to provide protection against tampering with the internal firewall50by a PC1user, who has easier access to software or macro hardware such as PC motherboards to alter. Also, non-configurable hardware denying access from the network is the most immune to hacking from any outside source, including the Internet, and can therefore be used either for general protection or to protect an innermost kernel of the most confidential of personal files (such as passwords or financial data) and the most critical of operating system components, such as the system bios or access to file alternation.

Any of the embodiments shown inFIGS. 17A and 17Bcan be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

The flexible network architectures shown earlier inFIG. 16Kand otherFIG. 16series (and other figures) have many applications and may be used to design improvements and alternatives to the network itself. In addition, the flexible network can be used to simulate and design personal computers PC1and particularly PC microprocessor chips90(and other microchips), which may be static or configurable (in response to the requirements of a given operation, like theFIG. 16Knetwork architecture) or a mix.

TheFIG. 16Knetwork architecture has capabilities that substantially exceed simulating the fairly simple binary circuit structure of a typical PC microprocessor90or other microchip, since any personal computer PC1or PC microprocessor chip90in theFIG. 16Knetwork can simulate much more than a simple binary circuit on/off state or other simple microchip circuit. Any PC1or PC microprocessor chip90in aFIG. 16Knetwork can represent virtually any number of states or conditions simulating any kind of circuit, however complex it might be, the only limit being the processing time required for what can be a very large number—thousands or millions—of personal computers PC1or PC microprocessors90to process the simulation; there are only practical constraints, not theoretical ones, although increasingly large numbers of processors are expected to be phased in, as discussed before.

One potential related application of prior described network inventions is to simulate the unique “qubit” component necessary to construct a quantum computer, as well as a virtual quantum computer itself.

FIGS. 18A-18Dshow designs for a virtual quantum computer or computers.FIG. 18Ashows personal computer PC1(or microprocessor90) with the addition of a software program151simulating a “qubit” for a quantum computer or computers and thereby becoming a virtual qubit (VQ)150, a key component of a quantum computer153.FIG. 18Bshows a personal computer PC1(or microprocessor90) with a digital signal processor (DSP)89connected to a hardware analog device152simulating a qubit, with the PC1monitoring the qubit through the DSP89, thereby simulating a virtual qubit (VQ)150for a quantum computer153; this arrangement allows the option of simultaneous use of the PC1through multi-tasking for both digital and quantum computing.

FIG. 18Cis likeFIG. 16A, but incorporates a virtual qubit in PC1, so that a virtual quantum computer153can have any network architecture like those shown inFIGS. 16A-16Zand16AA-16AB, as well as other figures of this application.

As shown inFIG. 18D, for example, a virtual qubits (VC)150network can provide complete interconnectivity, likeFIG. 13. Virtual qubits VC150like those described inFIGS. 18A & 18Bcan be added to or substituted for microprocessors30and40in priorFIGS. 16B-16Qand16V-16AA of this application, as well as earlier figures. As shown by those prior figures, the number of virtual qubits150is limited only to whatever is practical at any given time; in terms of development, that means as few as a single qubit150in one or more networked personal computers PC1to begin, but the number of qubits150may become extremely large, as indicated in previous figures.FIG. 18Dshows a mix of wired99and wireless100connections.

Any of the embodiments shown inFIGS. 18A-18Dcan be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

Like personal computers located in the home or office, personal computers PC1in automobiles170(including other transportation vehicles or other conveyances) are in actual use only a very small percentage of the time, with the average dormant period of non-use totaling as much as 90 percent or more. Personal computers PC1are now being added to some automobiles and will likely become standard equipment over the next decade or so. In addition, automobiles already have a very large number of microcomputers on board in the form of specialized microprocessors35which are likely to become general parallel processors in future designs, as discussed earlier in this application.

Automobiles therefore form a potentially large and otherwise unused resource for massive parallel processing through the Internet 3 and other networks, as described in earlier figures. However, when idle and thus generally available for network use, automobiles lack their usual power source, the engine, which of course is then off, since it is too large to efficiently provide electrical power to on board computers, except occasionally. As shown inFIG. 19, the car engine can have a controller (hardware, software or firmware or combination in the PC1or other microprocessor35), for example, connected to an automobile computer network178to automatically start the automobile engine in order to recharge the car battery171when the battery is low (and well before the battery is too low to start the engine), but the engine additionally needs to be controlled as above not to expend all available fuel automatically.

Alternately, the automobile170can be fitted with a very small auxiliary engine-power electrical power generator177to provide power to the automobile's computer network; the engine of the generator177can be fed by the main engine fuel tank and controlled as above.

Two solutions, not mutually exclusive, to alleviate (but not solve) the lack of power problem noted above are, first, adding an additional car battery171′ for network use (at least primarily) or, second, using a single battery but adding a controller in the PC1, for example, that prevents the existing battery171from being discharged to a level near or below that which is needed to start the automobile170.

In addition, as shown inFIG. 19, one or more solar power generating cells or cell arrays172can be incorporated in an automobile's outer surface, with generally the most effective placement being on a portion of the upper horizontal surface, such as a portion of the roof, hood, or trunk. For charging the automobile battery171when sunlight is not available, such as at night or in a garage, a focused or focusable light source173can provide external power to the solar panel.

Alternately, a connection device174such as a plug for an external electrical power source can be installed on or near the outer surface of the automobile. In addition, or independently, a connection device175for an optical fiber (or other wired) external connection to the Internet 3 or other net may be used; an intermediate high transmission speed can also exist between the automobile network and a fiber optic connection to the Internet 3. Alternately, a wireless receiver176, including optical wireless and/or DWDM, located near where the automobile is parked, such as in a garage, can provide connectivity from the automobile's personal computer or computers PC1directly to the Internet 3 or to a network in a home or business like that shown inFIG. 10I.

Any of the embodiments shown inFIG. 19can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

FIG. 20Ais likeFIG. 16Y(and can be combined with FIG.16AA), but in addition shows a slave microprocessor40functioning as S1, the function of master having been temporarily or permanently offloaded to it by M1microprocessor30. In addition,FIG. 20Ashows the processing level of slave microprocessors40, S31through S34, each with a separate output/input communication link to a digital signal processor (DSP)89or other transmission/reception component; the transmission linkages are shown as111,112,113, and114, respectively. The DSP89can be connected to a wired99means such as optical fiber to the Internet (or other net), although non-optical fiber wire can be used (and probably does not require a DSP89).

FIG. 20Bis likeFIG. 16S(and can be combined withFIG. 16U), but with the same new additions described above inFIG. 20A. LikeFIG. 16S,FIG. 20Bshows a detailed view of personal computer PC microprocessor901, which is a personal computer PC on a microchip90, including two more levels of parallel processing within the microprocessor90. In addition, the two new levels of PC microprocessor90shown inFIG. 20Bare a second processing level consisting of PC microprocessors9021through9024and a third processing level consisting of PC microprocessors9031through90316(a third level total of 16 microprocessors90). Each of the three processing levels shown in theFIG. 20Bexample is separated between levels by an intermediate direct connection to the Internet 3 (or other network) and by four output lines from the higher processing level. For example, microprocessors9021through9024are shown receiving respectively from the outputs111through114from four slave microprocessors94, S31through S34of PC microprocessor901.

PC microprocessor901is shown in detail including all slave microprocessors94, while other PC microprocessors90at the second and third processing levels are not, for simplicity and conciseness of presentation. An additional processing level can be present, but is not shown for the sake of simplicity, and personal computers PC1likeFIG. 20Acan be used interchangeably with PC microprocessors90.

FIG. 20Bshows that between each processing level the output links from every PC microprocessor90can be transmitted from slave microprocessors94directly to PC microprocessors90at the next processing level below, such as from PC microprocessor9021down to PC microprocessors9031through9034, via the Internet 3 or other net. Each of the transmission/reception links from those slave processing microprocessors94(S31through S34), shown as111,112,113, and114for PC microprocessor901, can be transmitted or received on a different channel (and can use multiplexing such as wave or dense wave division, abbreviated as DWDM) on an optical fiber line (because of its huge capacity, one optical fiber line is expected to be sufficient generally, but additional lines can be used) that may connect directly to PC microprocessor chip901, which can incorporate a digital signal processor89or other connection component (of which there can be one or more) for connecting to the wired connection like fiber optic line, as shown, or wireless connection.

Any of the embodiments shown inFIGS. 20A and 20Bcan be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

FIGS. 21A and 21Bare likeFIGS. 20A and 20B(and therefore also can be combined with FIGS.16AA and16U, respectively), but show additionally that all microprocessors30,40,93, and94of PC1or PC901can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/reception connection component. The additional communications linkages are shown as141,142,143, and144, which connect to M1, S1, S21, and S22, respectively, and connect to the network, including the Internet 3, the WWW, the Grid, and equivalents or successors. Like all preceding and subsequent figures,FIGS. 21A and 21Bare schematic architectural plans of the new and unique components of the parallel processing system invention disclosed in this application and can represent either physical connections or virtual relationships independent of hardware.FIG. 21Bshows an embodiment in which the additional linkages lead through the Internet 3 to microprocessors PC9025-9028.

The additional communications linkages141,142,143, and144, as well as the original linkages111,112,113, and114ofFIGS. 20A and 20B, may have a bandwidth sufficiently broad to at least avoid constraining the processing speed of microprocessors30,40,93, and94connected to the linkages. The ultra high bandwidth of optical connections like optical fiber or omniguides or optical wireless may provide external connections between PC1and PC901microprocessors that are far greater than the internal electrical connections or buses of those microprocessors, for example, by a factor of 10, or 100, or 1000, which are already possible with optical fiber, or 1,000,000, which is possible with optical omniguides, which are not limited to a relatively smaller band of wavelengths using DWDM like optical fiber; future increases will be substantial since the well established rate of increase for optical bandwidth is much greater than that for microprocessor speed and electrical connections. Wireless optical antennas that are positioned on the exterior of houses, buildings, or mobile reception sites, instead of inside of glass or other windows, should significantly increase the number of optical wavelengths that can be sent or received by each of the wireless optical antennas; the entire connection is freespace optical wireless, which allows for greater dense wave division multiplexing (DWDM) and thereby greater bandwidth.

A major benefit of the embodiments shown inFIGS. 21A-21Bis that PC1and PC901can function like theFIG. 9embodiment to efficiently perform operations that are uncoupled, so that each microprocessor M1, S1-S34can operate independently without microprocessors M1, S1, and S21-S22being idled, as they may be inFIGS. 20A and 20B. Another benefit is that for tightly coupled parallel operations, microprocessors M1, S1, and S21-S22can have broad bandwidth connections with microprocessors30,40,93, or94that are not located on PC1or PC901. Thus the embodiments shown inFIGS. 21A and 21Bprovide an architecture that allows PC1or PC901the flexibility to function in parallel operations either likeFIGS. 20A-20Bembodiments or like theFIG. 9embodiment, depending on the type of parallel operation being performed. Studies indicate that single chip multiprocessors like PC901can also perform uniprocessor operations with a speed like that of uniprocessor architectures like wide-issue superscalar or simultaneous multithreading.

LikeFIGS. 20A and 20B, the embodiment ofFIGS. 21A and 21Bincludes broad bandwidth connection to the Internet 3 by wired means such as optical connection by fiber optic cable or omniguide or optical wireless, although other wired or non-wired means can be used with benefit, and the use of DWDM is clearly advantageous.

Another advantage of the embodiments shown inFIGS. 22A and 22Bwhen functioning in theFIG. 9form of loosely coupled or uncoupled parallel processing or multitasking is that if PC1or PC901is functioning as a web server and typically uses only one microprocessor to do so, it can quickly add mirror web sites using one or more additional microprocessors to meet increasing volume of visits or other use of the web site. This replication of web sites on additional microprocessors in response to increasing load can also be done using theFIG. 16form of tightly coupled parallel processing. PC1and PC901or any of their microprocessors30,40,93, and94or other components can also serve as a switch or a router, including other associated hardware/software/firmware network components.

Any of the embodiments shown inFIGS. 21A and 21Bcan be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

Binary tree configurations of microprocessors shown inFIGS. 16,20,21A, and21B can be laid out in2D using an H-tree configuration, as shown inFIG. 21C, and can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

FIG. 22Ashows a microprocessor PC901like that ofFIG. 21B, except thatFIG. 22Ashows the microprocessors93and94each connecting to an optical wired interconnection99′ such as thin mirrored hollow wire or omniguide or optical fiber (and other very broad bandwidth connections can be used); the interconnect can include a digital signal processor89′ employed with a microlaser150, which can be tunable, and other components to transmit and receive digital data for microprocessors93and94into the optical wired interconnects99′ such as an omniguide using, for example, a specific wavelength of light for each separate channel of each separate microprocessor93and94utilizing dense wave division multiplexing (DWDM).

FIG. 22Bshows an enlargement of the digital signal processor89′ with microlaser150with other transmission and reception components.

FIG. 22Ashows a simple bus network connection architecture between the interconnect99′ and the microprocessors93and94. However, since the interconnection99′ is optical and the bandwidth available is very broad, the optical connection99′ allows connections between microprocessors93and94in PC901that are functionally equivalent to those shown inFIG. 21B, which includes a representation of physical connections. The interconnects between microprocessors93and94likeFIG. 21Bare shown within the omniguide99′ shown inFIG. 22A. In fact, the potential bandwidth of the optical interconnect99′ is so great that complete interconnection between all microprocessors93and94with PC901is possible, even for a much greater number of microprocessors either in a larger PC901likeFIG. 16Tfor example, or in other PC90s, such as PC9021-9024and9031-90316inFIGS. 20B and 21Bconnected to PC901through a network such as the Internet 3, the WWW, or the Grid; consequently, any conventional network structure can be implemented. Consequently, the embodiment shown inFIG. 22Ahas the flexibility of those ofFIGS. 21A and 21Bto function in parallel operations like either theFIGS. 20A-20Bembodiments or like theFIG. 9embodiment, depending on the type of parallel operation to be performed, or theFIG. 16embodiments.

It should be noted that the optical interconnect99′ shown inFIG. 22Acan beneficially have a shape other than a thin wire or tube, such as an omniguide with any form or shape located above and connection to microlasers150at a suitable location such as on or near the upper surface of the microchip PC901located at least at each microprocessor93and94or connected thereto, for example; the optical interconnect99′ and microlasers150and associated transmission and reception components can be located elsewhere on the microchip PC901with benefit. An omniguide can take a waveform shape or rely exclusively on a mirrored (or semi-mirrored) surface or surfaces (or combination of both shape and mirrored surface) to guide lightwave signals such as propagated by a microlaser150substantially directly and/or by reflection. A relatively large optical interconnect99′ can enable freespace or wireless-like connections between microlasers150; such an optical interconnect99′ can cover substantially the entire PC90microchip or can connect multiple PC90microchips and can connect one or more PC90microchips to other PC components.

As shown inFIG. 22A, random access memory (RAM)66can be located on microchip PC901like inFIG. 16Uand also can be connected directly or indirectly to the optical interconnect99′ (or use non-optical connections not shown), so that the microprocessors93and94and RAM66can communicate with a very broad bandwidth connection, including with RAM66and microprocessors93and94located off microchip PC901on the network including the Internet 3 and WWW. Any other component of the PC90microchip can be connected with the optical interconnect99′ and more than one such interconnect99′ can be used on the same PC90or other microchip. Microlasers150can include, for example, 5-to-20-micron-high (or other height) vertical cavity-surface-emitting lasers (VCSELs), which can beam down waveguides built into the PC90microchip; alternatively, freespace optics can be employed; and lenses can be employed. Radio-frequency (RF) signals can also be used for similar interconnects99′. Micro light emitting diodes (LEDs) can substitute for one or some or all of the microlasers150and either can be a transceiver (transmit and receive light signals).

FIG. 22Cis a side cross section of the microchip PC901shown inFIG. 22Ataken at hatched line22C (which is abbreviated).FIG. 22Cshows the location of the omniguide above the surface of the microprocessors93and94and RAM66and connecting them while also containing two or more microlasers150(associated DSP and other components not shown) proximate to each to contain the optical signal generated by the microlasers150so that the signal can be transmitted between microprocessors93and94and RAM66either directly or by being reflected off the mirrored (or semi-mirrored) surface of the omniguide99′, for example. Each of the microprocessors93and94(or30or40) and RAM66(or any other memory component such as L1 cache or L2 cache, for example, or other microchip component) can have one or more microlasers150and each such microlaser150can distinguish itself from other microlasers150on the microchip (or off it) that also generate wavelength signals by using, for example, a distinct wavelength of light for data transmission and/or utilizing wave or dense wave division multiplexing.FIG. 22Ais a top view of the microchip PC901which is a PC system on a microchip, any of which disclosed in this application can be also more generally any microchip with multiple processors. The microlasers150(and associated transmission and reception components such as DSP) that are associated with RAM (or parts of it) or other memory components can either provide data in response to direct inquiries or fetches made by a microprocessor93or94or can broadcast a continual stream of current data (continually updated and repeated in continuous cycle, for example) which is used by the microprocessor as needed.

Any of the embodiments shown inFIGS. 22A,22B and22C can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

FIG. 23Ashows multiple firewalls50, a concept indicated earlier by the at least one firewall50discussed inFIG. 17D.FIG. 23Ashows a PC1or microchip90with a primary firewall50and additional interior firewalls501,502, and503, that are within primary firewall50. As shown, interior firewall503is in the most protected position, since it is inside all the other firewalls, while the other interior firewalls502, and501are progressively less protected, since, for example, interior firewall501is protected from the outside network only by the primary firewall50. As shown, progressively more protected positions can be created within the PC1or microchip90. The interior firewalls can also be arranged in any other way within the primary firewall50. The interior firewalls can be used to separate user files from system files, for example, or to separate various hardware components from each other. In this manner, a number of compartments can be created within the PC1or microchip90to more safely protect the software, hardware, and firmware of the PC1or microchip90, just as ships have a number of separate watertight compartments to protect against flooding and avoid sinking. Any of the primary or interior (or other inner firewalls discussed below) can be hardware, software, or firmware, or a combination, and can coexist in layers, so that a firewall50, for example, may have a hardware firewall, a software firewall, and a firmware firewall, either as independent units or as integrated components. W3inFIG. 23Aand subsequent Figures denotes the World Wide Web.

FIG. 23Bshows another embodiment of compartments created by inner firewalls within a PC1or microchip90. Primary firewall50and interior firewall501are likeFIG. 23A, but interior firewalls502,503, and504are shown perpendicular to firewalls50and501(just to illustrate in a simplified schematic way, which may be different in an actual embodiment). In this way, an upper row of compartments U1and U2can be used, for example, to bring from the network files which are first authenticated and then enter into the U1compartment, are decrypted, and undergo a security evaluation, such as by virus scan, before transfer to the most secure compartment U2. Any operations could potentially occur in any compartment, depending on the level of security desired by the user (by over-ride) for example, but an advantageous default system would allow for files with the highest levels of authentication, encryption, and other security evaluations to be allowed into the most secure compartments.

Similarly, operating system files can also be authenticated and brought from the network side of the PC1or microchip90into compartment O1for decryption and security evaluation or other use, and then finally transferred into the most secure compartment O2. Again, similarly, a row of compartnents can be used for separating hardware, such as a master microprocessor30or93being located in compartment M1and a remote controller31, for example, located in compartment M2.

Also, additional inner firewalls5022,5033, and5044can be located outside the primary firewall50, but within the network portion of the PC1or microchip90, to separate user files in compartment U from operating system files in compartment O from hardware such a slave microprocessor in compartment S on the network side. In the example shown, an additional row is shown for hardware, including a hard drive in a compartment HD on the network side, a hard drive in compartment HD1on the PC1or microchip90user's side, and flash memory (such as system bios88) in compartment F2. Each microprocessor30,40,93, or94can have its own compartment in a manner like that shown inFIG. 23B, as can associated memory or any other hardware component.

FIG. 23Cshows an inner firewall50embodiment similar toFIG. 23B, butFIG. 23Cshows that any file or set of files, such as operating files O or user data files U or application files A, can have its own inner firewall50Oor50Uor50A. Similarly, any hardware component, such as hard drive HD, also can have its own inner firewall50HD. Additionally, more than one file or set of files or hardware components can be grouped together within an inner firewall, such as50Sshown inFIG. 23C.

FIGS. 23D and 23Eshow operating system files O or application files A like those shown inFIG. 23C, but organized differently in discrete layers, each separate grouping of the operating or application files having a separate firewall50(and optionally with as well as a PC1or PC90firewall shown in earlier Figures), so that the firewall structure is like that of an onion. The operating system files O or application files A can have a parallel structure, with an innermost kernel operating system or application file located in the center, with additional features in other files in subsequent layers, from the simplest to the most complex and from the most secure and trusted to the least secure and trusted.

Using this structure, as shown inFIG. 23D, an innermost operating system core O1may be firmware stored in a read-only memory (ROM), located in a microchip for quick access, so that a simplest version operating system with all core features can be protected absolutely from alteration and can be available almost immediately, without lengthy boot up procedures required by loading the operating system from a hard drive, for example. The core operating system O1can include a core of the system BIOS or of the operating system kernel, for example; it would be advantageous for this core to be capable of independent operation, not dependent on components in other levels to operate at the basic core level (similarly, other levels can advantageously be independent of higher levels).

A secondary operating system O2can be software located advantageously on flash or other microchip non-volatile memory such as magnetic (or less advantageously, a hard drive or other mechanical storage media) and can consist of additional features that are more optional, such as those not always used in every session, or features that require updating, changing, or improving, such features coming from trusted sources located on a network, such as the Internet or the Web; additional portions of or upgrades to the system BIOS and the operating system kernel can be located in O2, for example.

A third level operating system O3located, for example, on a hard drive, can consist of additional software features that are used only occasionally and are more optional, and can be loaded as needed by a user into DRAM or magnetic memory microchip for execution, for example. Operating systems O2and O3can include, for example, the most recent upgrades from a known and trusted source, such as a commercial software vendor or open source software developer, that are downloaded from a network, including the Internet and the Web, or loaded from conventional memory media like CD or floppy diskette. All three levels of such operating systems O1, O2, and O3together can constitute, for example, roughly the equivalent of a conventional PC operating system typical in the year 2000.

A fourth level operating system O4, for example, can consist of special use or single use operating system add-ons, especially software coming from untrusted or unauthenticated sources on a network, such as the Internet or the Web.

For example, the graphical interface of the operating system can be in 2D only at the O1level, in3D at the O2level, rendering at the O3level, and animation in the O4level; additionally, a standard format can be maintained in the O1and O2levels, with user or vender customization at the O3level.

As shown inFIG. 23E, application files such as A1, A2, A3, and A4can be structured the same way as operating system files O inFIG. 23Dand with the same layered approach to firewalls50as inFIG. 23D. Typical application software of the year 2000 can be restructured in this manner.

The kernel operating system files O1and O2, as well as kernel application files A1and A2can be located in any personal computer PC1or PC90, including at the level of an appliance including the simplest device, advantageously in ROM and in non-volatile read/write memory such as Flash (or magnetic such as MRAM, or ovonic memory) microchips, for example, as described inFIGS. 23D and 23Eabove. Inclusion of wireless connection capability is advantageous, as is the use of DWDM.

An advantage of the file and firewall structures shown inFIGS. 23D and 23Eis that a system crash or file corruption should never occur at the simple and unalterable level O1or A1and any level above O1or A1can be recovered at a lower level, specifically the highest level at which there is a stable system or uncorrupted data. For example, a word processing application program can have the most basic functions of a typewriter (i.e. storing alphanumeric, punctuation, spacing, and paragraph structure data) stored on a ROM microchip in A1and related user files (i.e. such as a word document) on U2. Insertion of a digital video file into a word document can be handled at the A3level and insertion of a downloaded special effect at the A4level. In this example, a crash caused by the insertion at the least secure and most complex A4level would not disturb the word document located at the U2or U3level. Rebooting and/or recovery can be automatic when detected by the operating system or at the option of the user.

Thus,FIGS. 23A-23Eillustrate embodiments wherein a PC1or microchip90includes a hierarchy of firewalls. In the context of the present invention, firewalls may be structured to allow varying degrees of access from the network side of PC1or microchip90. As discussed above, ROM may totally deny access from the network side, effectively creating an innermost firewall. Hardware, software, firmware, or combinations thereof may be structured to deny or allow a predetermined maximum level of access from the network side, effectively creating outer firewalls. Similarly, intermediate firewalls effectively may be created.

Any of the embodiments shown inFIGS. 23A-23Ecan be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

Additionally, an inner firewall can divide any hardware component into a separate network side compartment and a separate firewall protected side compartment. For example, a hard drive61can have a controller61′ that is divided into two compartments, HD and HD1, as above. As shown inFIG. 24, the user side HD1compartment of the controller61′ can have a read capability controller r and a write capability controller w, while the network side HD compartment can be limited to a read capability controller r only. The user side HD1compartment controller can be, for example, used to control only the upper surface of the hard drive61platters, while the network side HD compartment controller can be used to control only the lower surface of the hard drive61platters, so that a single hard drive can effectively serve a dual role as both a network-accessible hard drive and a user-accessible hard drive, while maintaining a firewall50between them. Additionally, the network side HD controller can optionally have a write capability also, which can be preemptively turned on or off by the PC1or microchip90user. Other relative allocations between network and user of the HD61platters can be made and can be configurable by the user or system administrator or not configurable.

Similarly, CD drives63or DVD drives64(read only or read/write) can have a controller63′ or64′ like that of the HD controller61′ above that is divided by a firewall50, so that some laser beams are under network control and other laser beams are under user control, like the above hard drives. Floppy disk drives, “Zip” drives, and other removable disk or diskette drives can similarly be divided by a firewall50so that there is a physical user portion of the disk or diskette and a physical network portion of the disk or diskette, both either fixed or configurable by a user or system administrator or other authorized source. Memory microchips such as RAM or Flash or other can also be divided into network and user sides in a similar manner.

Any of the embodiments shown inFIG. 24can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

The use of volatile memory on the network side of the PC1or microchip90is particularly useful in eliminating viruses and other security problems originating from the network side, such as malicious hackers on the Internet. When the network side of the firewall50of the PC1or microchip90is returned to its user (preemptively or otherwise), volatile memory like random access memory (RAM) such as DRAM on the network side can first be erased. For example, volatile memory can be purged by momentarily interrupting power to the network side of the PC1or microchip90, thereby erasing all network data so that no network data is retained when the user regains control of the network side of the PC1or microchip90for the user's use, except at the user's option; other conventional means may be employed. Of course, when the user is specifically using the network side, for example, for Web browsing, the operating system or the user can selectively save network side files or transfer them to the user side.

On the network side, non-volatile memory like Flash, MRAM, and ovonic memory with network data must be overwritten to obtain the same erasure-type protection, which can be a disadvantage if it takes much more time. Moreover, for relatively large storage media, such as CD-RW or DVD-RW with write-once capability, network data writing must be tracked to be effectively erased. Any new network file on non-volatile memory with only a write-once capability can be erased by overwriting all “0's” to “1's”, so that, for example, the network data written on a CD-RW or DVD-RW would be converted to all “1's” or “pits” (no unpitted writing surface within the network data sector, permanently overwriting the file); optionally, the operating system or the user can selectively save network side files or transfer them to the user side, or vice versa. There is a disadvantage to using Flash memory, since repeated overwriting will eventually degrade it.

FIGS. 25A-25Dshow the use for security of power interruption or data overwrite of volatile memory like DRAM and non-volatile memory like Flash or MRAM (or ovonics), respectively, of the network portion (N) of a personal computer PC1or system on a microchip PC90; the network (N) portion being created within a PC1or PC90by a firewall50(as described above in previous figures) and including resources that, when idled by a user, can be used by the network, including the Internet (I) or the World Wide Web. Such use is to prevent the unplanned or approved mixture of user and network files by either files being retained in the “swing space” (N) during the transition from use by a network user to use by the PC1/PC90user or vice versa.

As shown inFIG. 25AandFIG. 25C, when the network portion (N) of the PC1personal computer or PC90microchip is idled by a user, for example, power is interrupted to volatile memory like DRAM and/or data is overwritten to files in non-volatile memory like Flash or MRAM (or ovonics), so that no files exist in the network portion (N) after such interruption or overwriting.

After the step shown inFIGS. 25A and 25C, the network portion (N) can be used safely from a security viewpoint by a user from the network, including the Internet and the World Wide Web (and potentially including other network resources), as shown inFIG. 25B, or by the PC1/PC90user, as shown inFIG. 25D, potentially including other resources from the user portion (U) of the PC1or PC90. As noted earlier, theFIG. 25approach can advantageously be used as an additional feature to other conventional security measures.

Any of the embodiments shown inFIGS. 25A-25Dcan be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

It is currently contemplated that commercial embodiments of the networks, computers, and other components of the Internet, World Wide Web, and the Grid (or MetaInternet) described in this application in the precedingFIGS. 1-25, including hardware, software, firmware, and associated infrastructure will be developed in conjunction and with the assistance of the Internet Society (ISOC), the World Wide Web Consortium (W3C), the Next Generation Internet (NGI), professional organizations like the Institute of Electrical and Electronics Engineers (IEEE) and the American National Standards Institute (ANSI), as well as other national and international organizations, and industry consortia drawn from the telecommunication, T.V. cable, ISP, network, computer, and software industries, as well as university and other research organizations, both U.S. and international, to set agreed upon operating standards which, although often arbitrary, are critical to efficient, reliable functioning of the Grid (or MetaInternet).

It is also presently contemplated that the Linux programming language will take a central role in the Grid (or MetaInternet), since a homogeneous system has an advantage as being most efficient and effective, and Linux is among the most stable, efficient higher level software available, one that has already established a preemininent role in distributed parallel processing. A heterogeneous Grid (or MetaInternet) is certainly feasible too, but less advantageous, as is the Java programming language, which excels in heterogeneous environments. Although Linux may be employed instead of Java in keeping with the more effective homogeneous approach for parallel processing systems that can scale even to the massive numbers of PCs available on the Internet and WWW, either Java or principles employed in Java may be used with benefit, especially in certain cases like security, such as the use of “sandboxes” to provide secure execution environments for downloaded code (see page 39 ofThe Grid, Foster and Kesselman and associated bibliography references 238, 559, 555, and 370), although use of one or more internal firewalls as discussed earlier inFIGS. 10 and 17to protect personal user files and critical hardware and software systems, such as the operating system, may provide similar capability.

It is also contemplated currently that, like the Linux programming language, the Grid (or MetaInternet) described in this application can be developed into a commercial form using open source principles for Internet-like standards for software and hardware connections and other components. Such open source development is anticipated to be exceptionally successful, like Linux, because much of it can be freeware, although modified with one vital enhancement to provide equity for significant contributors: minimal licensing fees that are to be paid only by medium to large commercial and governmental entities at progressive rates based on financial size; the resulting funding can be used for significant financial and other awards for special research and development efforts relating to the Grid (or MetaInternet) and its open source development, particularly outstanding achievements by individuals and teams, especially independent developers and virtual teams, the awards also being progressive in terms of importance of contribution and most being peer-selected. Open source commercial development of the Grid (or MetaInternet) should therefore, like Linux, attract the most interested and best qualified technical expertise on the planet, all linked by the Internet and WWW to collaborate virtually in realtime 24 hours a day and 7 days a week, creating a virtual entity extraordinarily skilled in the existing art.

It is also anticipated that the exclusive rights to the Grid (or MetaInternet) granted by patents issued on this application, particularly for the homogeneous embodiment of the Grid (or MetaInternet)—which is by far the most effective and efficient form—will ensure that the Grid (or MetaInternet) is homogeneous on critical hardware and software standards and protocols. That is because any heterogeneous systems cannot compete commercially due to inherent inferiority in efficiency, while any competing homogeneous system would infringe the patents issuing from this and other applications and therefore be enjoined from operations. The open Grid (or MetaInternet) standards would thus be patent-protected.

As noted earlier, the Internet 3 and WWW (and successors or equivalents) are expected to ensure that any single design standard in widespread use, such as the Wintel standard (software/hardware) and the Apple MacIntosh standard (also both), are homogeneous as to Grid (or MetaInternet) parallel processing systems as outlined in this application, since the Internet and WWW and equivalents or successors make available such a large pool of homogeneous computers with the same standard, in ever increasingly close proximity as more and more PCs and other devices go online. The increasingly universal connection attribute of the Internet 3 and WWW and successors therefore create virtual homogeneity for most significant brands.

The term homogeneous as it is used here refers to functional design standards primarily, not physical structure, for example, when applied to hardware. In this sense, then, for example, the Intel Pentium II, the Advanced Micro Devices (AMD) K6-6, and the Cyrix MII microprocessor chips are functionally compatible and homogeneous with no need for special emulation software, although they are each structurally quite different and use different microcode at the microchip level. The new Transmeta microprocessors are expected to be functionally compatible and homogeneous through elaborate and highly efficient emulation, potentially an ideal microprocessor for the Grid (or MetaInternet). In contrast, for example, the Apple G3 processor is also structurally different but in addition requires a different operating system and is therefore not functionally compatible and not homogeneous with the Pentium II, K6-6, and MII microprocessors discussed above. Similarly, MS DOS and DR DOS are functionally compatible software PC operating systems and homogeneous, even though their codes are different, whereas Apple MacIntosh operating systems are not functionally compatible or homogeneous with the two DOS systems, except with the addition of special emulation software, which is not efficient. Substantially interchangeable use therefore is a defining element of homogeneity as used in this application. An example of a heterogeneous parallel processing system distributed among many computers, which can be of any sort, is the University of Virginia's Legion system, in contrast to the homogeneous systems discussed above.

This application encompasses all new apparatus and methods required to operate the above described network computer system or systems, including any associated computer or network hardware, software, or firmware (or other component), both apparatus and methods, specifically included, but not limited to (in their present or future forms, equivalents, or successors): all enabling PC and network software, hardware, and firmware operating systems, user interfaces and application programs; all enabling PC and network hardware design and system architecture, including all PC and other computers, network computers such as servers, microprocessors, nodes, gateways, bridges, routers, switches, and all other components; all enabling financial and legal transactions, arrangements and entities for network providers, PC users, and/or others, including purchase and sale of any items or services on the network or any other interactions or transactions between any such buyers and sellers; and all services by third parties, including to select, procure, set up, implement, integrate, operate and perform maintenance, for any or all parts of the foregoing for PC users, network providers, and/or others.

The combinations of the many elements of the applicant's invention introduced in the preceding figures are shown because those embodiments are considered to be at least among the most useful possible, but many other useful combination embodiments exist but are not shown simply because of the impossibility of showing them all while maintaining a reasonable brevity in an unavoidably long description caused by the inherently highly interconnected nature of the inventions shown herein, which generally can operate all as part of one system or independently.

Therefore, any combination that is not explicitly described above is definitely implicit in the overall invention of this application and, consequently, any part of any of the preceding Figures and/or associated textual description can be combined with any part of any one or more other of the Figures and/or associated textual description of this application to create new and useful improvements over the existing art.

In addition, any unique new part of any of the preceding Figures and/or associated textual description can be considered by itself alone as an individual improvement over the existing art.

The foregoing embodiments meet the overall objectives of this invention as summarized above. However, it will be clearly understood by those skilled in the art that the foregoing description has been made in terms only of the most preferred specific embodiments. Therefore, many other changes and modifications clearly and easily can be made that are also useful improvements and definitely outside the existing art without departing from the scope of the present invention, indeed which remain within its very broad overall scope, and which invention is to be defined over the existing art by the appended claims.