Body contacts for field-effect transistors

Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

BACKGROUND

Field

The present disclosure generally relates to field-effect transistor (FET) devices and more particularly to body contacts for such FET devices.

Description of Related Art

In electronics applications, field-effect transistors (FETs) can be utilized as switches and in amplifiers. Switches can allow, for example, routing of radio-frequency (RF) signals in wireless devices. Amplifiers can amplify signals for transmission or amplify received signals.

SUMMARY

According to a number of implementations, the present disclosure relates to a field-effect transistor (FET) that includes a first assembly of source, gate, and drain implemented on a first active region; a second assembly of source, gate, and drain implemented on a second active region; and a first body contact implemented between the first assembly and the second assembly.

In some embodiments, the FET includes a silicon-on-insulator (SOI) substrate. In some embodiments, the first assembly and the second assembly are dimensioned substantially the same and the first body contact is positioned at approximately the center of the FET.

In some embodiments, the FET also includes a third assembly of source, gate, and drain implemented on a third active region, and a second body contact implemented between the second assembly and the third assembly. In further embodiments, the first assembly and the third assembly are dimensioned substantially the same such that the first body contact and the second body contact are positioned substantially symmetrically about a center line of the FET.

In some embodiments, each of the first and second assemblies of respective source, gate, and drain is implemented in a finger configuration with gate fingers extending in a direction to provide a folded T-shaped body contact configuration for the first body contact and the gate fingers of the first and second assemblies. In further embodiments, the finger configuration of each of the first and second assemblies results in source and drain fingers being interleaved with the gate fingers. In yet further embodiments, the source fingers and the drain fingers are arranged in alternating rows. In yet further embodiments, a particular source finger of the first assembly is electrically connected to a source finger of the second assembly that is positioned on the same row as the particular source finger of the first assembly. In yet further embodiments, a particular drain finger of the first assembly is electrically connected to a drain finger of the second assembly that is positioned on the same row as the particular drain finger of the first assembly. In further embodiments, a particular source finger of the first assembly is electrically connected to a source finger of the second assembly that is offset by one row from the particular source finger of the first assembly. In yet further embodiments, a particular drain finger of the first assembly is electrically connected to a drain finger of the second assembly that is offset by one row from the particular drain finger of the first assembly.

In some embodiments, the first body contact further includes a first connecting metal extending along a width of the first body contact on a first side and a second connecting metal extending along a width of the first body contact on a second side opposite the first side. In further embodiments, a first plurality of gate fingers electrically coupled to the first connecting metal that extends away from the first connecting metal over the first active region and a second plurality of gate fingers electrically coupled to the second connecting metal that extends away from the second connecting metal over the second active region. In yet further embodiments, the FET also includes a third connecting metal that electrically couples the first connecting metal and the second connecting metal to electrically connect the first plurality of gate fingers and the second plurality of gate fingers.

According to a number of implementations, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of devices. The RF module also includes a die mounted on the packaging substrate, the die including a field-effect transistor (FET) having a first assembly of source, gate, and drain implemented on a first active region, the FET further including a second assembly of source, gate, and drain implemented on a second active region, the FET further including a body contact implemented between the first assembly and the second assembly.

In some embodiments, the RF module is a switch module. In some embodiments, the die is a silicon-on-insulator (SOI) die.

According to a number of implementations, the present disclosure relates to a wireless device that includes a transceiver configured to process radio-frequency (RF) signals. The wireless device also includes an RF module in communication with the transceiver, the RF module including a switching device having a field-effect transistor (FET), the FET including a first assembly of source, gate, and drain implemented on a first active region, the FET further including a second assembly of source, gate, and drain implemented on a second active region, the FET further including a body contact implemented between the first assembly and the second assembly. The wireless device also includes an antenna in communication with the RF module, the antenna configured to facilitate transmitting and/or receiving of the RF signals.

In some embodiments, the RF module is a switch module.

According to a number of implementations, the present disclosure relates to a field-effect transistor (FET) that includes an assembly of source, gate, and drain implemented on an active region; a first body contact implemented on a first side of the assembly; and a second body contact implemented on a second side of the assembly, the second side opposite the first side of the assembly.

In some embodiments, the FET also includes a plurality of gate fingers, a first connecting metal, and a second connecting metal that together form a gate contact for the FET device. In further embodiments, the plurality of gate fingers is coupled to the first connecting metal and to the second connecting metal. In yet further embodiments, the first connecting metal is implemented between the first body contact and the assembly and the second connecting metal is implemented between the second body contact and the assembly. In some embodiments, the first active region of the assembly includes a plurality of conductive features in rows between the plurality of gate fingers to form alternating strips of source and drain. In further embodiments, the conductive features include conductive vias.

In some embodiments, each of the first body contact and the second body contact includes a plurality of conductive features.

According to a number of implementations, the present disclosure relates to a method for fabricating a radio-frequency (RF) device, the method including forming a field-effect transistor (FET) over a substrate layer; electrically connecting the substrate layer to a substrate node; and coupling a non-grounding circuit to the substrate node to adjust RF performance of the FET.

According to a number of implementations, the present disclosure relates to a method for fabricating a field-effect transistor (FET), the method including forming or providing a substrate; implementing a first assembly of source, gate, and drain on a first active region of the substrate; implementing a second assembly of source, gate, and drain on a second active region of the substrate; and forming a first body contact between the first assembly and the second assembly.

In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate.

According to a number of implementations, the present disclosure relates to a method for fabricating a radio-frequency (RF) device, the method includes forming a field-effect transistor (FET) using the method of the above implementations; electrically connecting the substrate to a substrate node; and coupling a non-grounding circuit to the substrate node to adjust RF performance of the FET.

According to a number of implementations, the present disclosure relates to a field-effect transistor (FET) that includes a first assembly of source, gate, and drain implemented on a first active region, the first assembly having a first width and a first length; a second assembly of source, gate, and drain implemented on a second active region, the second assembly having a second width and a second length, such that the first width is greater than the second width and the first length is not equal to the second length; and a body contact implemented between the first assembly and the second assembly such that the body contact is away from a center of the FET.

In some embodiments, the FET includes a silicon-on-insulator (SOI) substrate. In some embodiments, the FET also includes a plurality of gate fingers, a first connecting metal, and a second connecting metal that together form a gate contact for the FET device. In further embodiments, the first active region of the assembly includes a plurality of conductive features in rows between the plurality of gate fingers to form alternating strips of source and drain.

In some embodiments, the body contact further includes a first connecting metal extending along a width of the body contact on a first side and a second connecting metal extending along a width of the body contact on a second side opposite the first side. In further embodiments, the FET also includes a first plurality of gate fingers electrically coupled to the first connecting metal that extends away from the first connecting metal over the first active region and a second plurality of gate fingers electrically coupled to the second connecting metal that extends away from the second connecting metal over the second active region, the number of gate fingers of the first plurality of gate fingers being different from the number of gate fingers of the second plurality of gate fingers.

In some embodiments, each of the first and second assemblies of respective source, gate, and drain is implemented in a finger configuration with gate fingers extending in a direction to provide a folded T-shaped body contact configuration for the first body contact and the gate fingers of the first and second assemblies.

According to a number of implementations, the present disclosure relates to a field-effect transistor (FET) that includes a first assembly of source, gate, and drain implemented on a first active region; a second assembly of source, gate, and drain implemented on a second active region, the second assembly aligned with the first assembly in a first row; a third assembly of source, gate, and drain implemented on a second active region, the third assembly aligned with the first assembly in a first column; a fourth assembly of source, gate, and drain implemented on a second active region, the fourth assembly aligned with the second assembly in a second column and with the third assembly in a second row; and a body contact assembly implemented between the first assembly, the second assembly, the third assembly, and the fourth assembly.

In some embodiments, the FET includes a silicon-on-insulator (SOI) substrate. In some embodiments, the body contact assembly is positioned between the first row and the second row and between the first column and the second column. In further embodiments, the body contact assembly forms a cross shape.

In some embodiments, the body contact assembly includes a first body contact implemented between the first and second assemblies and a second body contact implemented between the third and fourth assemblies. In some embodiments, the body contact assembly includes a first body contact implemented between the first and third assemblies and a second body contact implemented between the second and fourth assemblies. In some embodiments, the body contact assembly includes a first body contact implemented between the first and second assemblies, a second body contact implemented between the third and fourth assemblies, a third body contact implemented between the first and third assemblies, and a fourth body contact implemented between the second and fourth assemblies.

In some embodiments, each of the first, second, third, and fourth assemblies of respective source, gate, and drain is implemented in a finger configuration with gate fingers extending over the first, second, third, and fourth active regions to provide alternating rows of source and drain interleaved with the gate fingers. In some embodiments, the first assembly has a first width and a first length and the second assembly has a second width and a second length such that the first width is greater than the second width. In further embodiments, the first length is greater than the second length.

According to a number of implementations, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of devices. The RF module also includes a die mounted on the packaging substrate, the die including a field-effect transistor (FET) having a first assembly of source, gate, and drain implemented on a first active region, the first assembly having a first width and a first length, the die further including a second assembly of source, gate, and drain implemented on a second active region, the second assembly having a second width and a second length, such that the first width is greater than the second width and the first length is not equal to the second length, and the die further including a body contact implemented between the first assembly and the second assembly such that the body contact is away from a center of the FET.

In some embodiments, the RF module is a switch module. In some embodiments, the die is a silicon-on-insulator (SOI) die.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, one or more of the disclosed features may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Disclosed herein are various examples related to body contacts for field-effect transistors (FETs). FETs, such as those having silicon-on-insulator (SOI) process technology, are utilized in many radio-frequency (RF) circuits, including those involving high performance, low loss, high linearity switches. In such RF switching circuits, performance advantage typically results from building a transistor in silicon, which sits on an insulator such as an insulating buried oxide (BOX). The BOX typically sits on a handle wafer, typically silicon, but can be glass, borosilicon glass, fused quartz, sapphire, silicon carbide, or any other electrically-insulating material.

In various examples herein, FETs are sometimes described in the context of such SOI technology. However, it will be understood that one or more features of the present disclosure can also be implemented in other types of FETs.

FIG. 1illustrates a terminal representation of a FET100having nodes associated with a gate, a source, a drain and a body. Examples related to contacts for such a body are described herein in greater detail.

FIG. 2illustrates that, in some embodiments, a FET100having a body contact configuration as described herein can also include a substrate node. Among others, U.S. Pat. Pub. No. 2016/0322385 published Nov. 3, 2016 and entitled “Substrate bias for field-effect transistor devices,” which is expressly incorporated herein by reference in its entirety, discloses additional details about how such a substrate node can be biased and/or coupled to one or more other nodes of the transistor to, for example, improve both linearity and loss performance of the transistor.

U.S. Pat. Pub. No. 2016/0322385 also discloses examples of how FET devices having one or more features as described herein can be fabricated as wafers, as well as various applications that utilize such FET devices. U.S. Pat. Pub. No. 2016/0322385 also discloses examples of various products that can include such FET devices.

FIGS. 3A and 3Brespectively illustrate side sectional and plan views of an example SOI FET device10having an active FET implemented over a substrate such as a silicon substrate associated with a handle wafer16. Although described in the context of such a handle wafer, it will be understood that the substrate does not necessarily need to have functionality associated with a handle wafer.

An insulator layer such as a BOX layer14can be formed over the handle wafer16, and the active FET can be formed based on an active silicon device12over the BOX layer14. In various examples described herein, and as illustrated inFIGS. 3A and 3B, the active FET can be configured as an NPN or PNP device.

In the example ofFIGS. 3A and 3B, terminals for the gate24, source20, drain22and body26can be configured and provided to allow operation of the FET. It will be understood that in some embodiments, the source and the drain can be interchanged.

Referring toFIGS. 3A and 3B, a contact feature28provides an electrical contact with the body26. It is noted that in the example ofFIGS. 3A and 3B, such a body contact feature28is located at one end of the FET device10.

In general, a body contact is typically utilized to control a voltage potential associated with the FET body. If the body contact is implemented at an end of a given FET device, such as in the example ofFIGS. 3A and 3B, such voltage controlling influence provided by the body contact may weaken significantly at locations relatively far away from the body contact.

For example,FIG. 4illustrates an example of a FET device400having a T-shaped body contact configuration. More particularly, a plurality of conductive features436such as conductive vias can be implemented on a region of a body434to generally form a body contact450. In the example ofFIG. 4, such a body contact450generally forms a “T” shape along with the direction of a plurality of gate fingers424.

In the example ofFIG. 4, the gate fingers424and a connecting metal430can collectively form a gate contact for the FET device400. Portions of an active region412between the gate fingers424can be provided with a plurality of conductive features432such as conductive vias to form alternating strips of source and drain for the FET device400.

In the example ofFIG. 4, the foregoing configuration generally results in an assembly of source, gate and drain generally occupying a region indicated as440, and the body contact occupying a region indicated as450. To facilitate the description herein, the region440may be referred to as an assembly of source, gate and drain, or simply as S/G/D, an S/G/D region, or an S/G/D assembly. Similarly, the region450may be referred to herein as a body contact, a body, or the like.

FIG. 5illustrates a block diagram of the example FET device400ofFIG. 4. Such a FET device can have an overall dimension of D1×D2. The S/G/D region440has a width of W0, and a length of L0. The body contact450can be positioned on one end of the width (W0) dimension.

Depicted in the S/G/D region440are examples of influence contour lines542,544that can result from, for example, application of a voltage at the body contact450. Generally, such an influence from the body contact450decreases as distance increases. Accordingly, the body contact influence in a first example region between the body contact450and the first influence contour line542is generally stronger than the body contact influence in a second example region between the first influence contour line542and the second influence contour line544. Similarly, the body contact influence beyond the second influence contour line544is generally weaker than the body contact influence in the second region. Accordingly, a relatively weak control of the body can result in FET devices such as that ofFIGS. 4 and 5. For example, the region to the left of the second influence contour line544(when viewed as depicted inFIG. 5) can have a relatively weak body control when compared to the region to the right of the first influence contour line542.

FIGS. 6 and 7illustrate another example FET device600having a configuration similar to the example FET device400ofFIGS. 4 and 5, but with an additional body contact implemented on the opposite end of an S/G/D region640. More particularly, the S/G/D region640can include a plurality of gate fingers624, and strips of source and drain about such gate fingers. The gate fingers624can be connected by first and second connecting metals630a,630bto form a gate contact for the FET device600.

A first body contact650acan be implemented on the first end of the FET device600(e.g., the right side in the example FET device600). Similarly, a second body contact650bcan be implemented on the second end of the FET device600. Accordingly, the two body contacts650a,650band the direction of the gate fingers624generally form an “H” shape.

To merely facilitate the description of the FET device600, suppose that the S/G/D region640is dimensioned (L0×W0) similar to the example ofFIGS. 4 and 5. In such a configuration, the first body contact650acan exert its influence as depicted by first and second influence contour lines742a,744a. Similarly, the second body contact650bcan exert its influence as depicted by first and second influence contour lines742b,744b.

Accordingly, the weak body contact influence region (e.g., on the left side) in the example ofFIGS. 4 and 5is now strongly influenced by the second body contact650b. However, such a dual body contact configuration involves addition of the second body contact. Still assuming the same S/G/D region dimensions (L0×W0) among the examples ofFIGS. 4 and 5andFIGS. 6 and 7, such a second body contact may increase the overall dimensions of the FET device600. For example, the D2dimension of the example FET device ofFIGS. 4 and 5is increased to a dimension of D3.

In some embodiments, a FET device can include a body contact that can be implemented between a first S/G/D region and a second S/G/D region. Such a configuration can address at least some of the foregoing issues described with reference toFIGS. 4-7, as well as provide additional advantageous features described herein.

FIG. 8illustrates a block diagram of a FET device800having a body contact850implemented between a first S/G/D assembly840aimplemented on a first active region812aand a second S/G/D assembly840bimplemented on a second active region812b. The first assembly840aand the second assembly840bcan be dimensioned such that the body contact850is positioned so that it bridges the center of the FET device800. In some embodiments, the body contact850can be positioned at approximately the center of the FET device800. Such an arrangement of the first S/G/D assembly840a, the body contact850, and the second S/G/D assembly840bcan be along a direction of gate fingers824a,824b. An example of such an arrangement is illustrated inFIG. 9.

In the example ofFIG. 9, the body contact850includes a plurality of conductive features836implemented to provide an electrical contact with a body850. The first S/G/D assembly840aincludes a plurality of gate fingers824aimplemented over a first active region812ato define strips or rows of the first active region812a. A plurality of conductive features832aare implemented for such strips to form source and drains. When connected appropriately such strips with corresponding conductive features can function as alternating source and drain strips or rows. The gate fingers824aof the first S/G/D assembly840acan be interconnected by a connecting metal830a.

Similarly, the second S/G/D assembly840bincludes a plurality of gate fingers824bimplemented over a second active region812bto define strips or rows of the second active region812b. A plurality of conductive features832bare implemented for such strips to form source and drains. When connected appropriately such strips with corresponding conductive features can function as alternating source and drain strips. The gate fingers824bof the second S/G/D assembly840bcan be interconnected by a connecting metal830b.

The connecting metal830afor the first gate fingers824aand the connecting metal830bfor the second gate fingers824bmay or may not be interconnected. In the example ofFIG. 9, the conductive features836associated with the body contact850and the conductive features832a,832bassociated with the source and drain strips can include, for example, conductive vias, conductive trenches, or some combination thereof.

The following observations can be made comparing the example ofFIGS. 8 and 9with the example ofFIGS. 4 and 5. Merely for the purpose of such a comparison, suppose that the length dimension of each of the first and second S/G/D assemblies840a,840bofFIGS. 8 and 9is L0, approximately the same as that of the S/G/D assembly440ofFIGS. 4 and 5. Further, suppose that the overall width dimension of the first S/G/D assembly840a, the body contact850, and the second S/G/D assembly840b(W1+body contact width+W1) ofFIGS. 8 and 9is similar to the overall width dimension of the body contact450and the S/G/D assembly440(body contact width+W0) ofFIGS. 4 and 5. In such a comparison, the width W1can be approximately half of the width W0.

In such a configuration ofFIGS. 8 and 9, it is apparent that most of each of the first and second S/G/D assemblies840a,840bis strongly influenced by the common body contact850. More particularly, the first influence contour line842aon the right side of the body contact850covers much of the first S/G/D assembly840a. Similarly, the first influence contour line842bon the left of the body contact850covers much of the second S/G/D assembly840b.

In the foregoing comparison of the FET device400ofFIGS. 4 and 5and the FET device800ofFIGS. 8 and 9, one can see that improved body contact influence can be obtained with the configuration ofFIGS. 8 and 9while utilizing a single body contact and maintaining a similar area for S/G/D functionality.

The following observations can be made when the example ofFIGS. 8 and 9is compared to the example ofFIGS. 6 and 7. Merely for the purpose of such a comparison, suppose again that the length dimension of each of the first and second S/G/D assemblies840a,840bofFIGS. 8 and 9is L0, approximately same as that of the S/G/D assembly640ofFIGS. 6 and 7. Further, suppose that the overall width dimension of the first S/G/D assembly840a, the body contact850, and the second S/G/D assembly840bis W1+body contact width+W1inFIGS. 8 and 9, and that the overall width dimension of the first body contact650a, the S/G/D assembly640, and the second body contact650bis body contact width+W0+body contact width inFIGS. 6 and 7.

In such a comparison, if the width W1is assumed to be approximately half of the width W0, the foregoing overall width dimension in the example ofFIGS. 6 and 7is greater than the overall width dimension in the example ofFIGS. 8 and 9by approximately one body contact width. Accordingly, one can see that while the body contact influence is relatively strong in both examples (ofFIGS. 6 and 7and ofFIGS. 8 and 9), the configuration in the example ofFIGS. 8 and 9can achieve a relatively strong influence with one less body contact and less overall area.

To facilitate the discussion herein, the example configuration ofFIGS. 8 and 9can be referred to as a folded configuration, with the common body contact850generally defining a fold line. Such a common body contact forms a T-shaped configuration with the first gate fingers824a. The same common body contact850also forms a T-shaped configuration with the second gate fingers824b. Accordingly, the example configuration ofFIGS. 8 and 9can also be referred to as a folded T-shaped body contact configuration. For example, the first gate fingers824aand the second gate fingers824bextend in a direction substantially perpendicular to the respective connecting metals830a,830b, forming the T-shaped configuration. The configuration of the respective gate fingers824a,824balso results in source and drain fingers being interleaved with the gate fingers824a,824bon each of the first assembly840aand the second assembly840b. In some embodiments, the source and drain fingers of the respective assemblies840a,840bare arranged in alternating strips or rows.

FIGS. 10 and 11illustrate that, in some embodiments, two body contacts can be implemented within a FET device1000. A first body contact1050acan be implemented between a first S/G/D assembly1040aimplemented on a first active region1012aand a second S/G/D assembly1040bimplemented on a second active region1012b, and a second body contact1050bcan be implemented between the second S/G/D assembly1040band a third S/G/D assembly1040cimplemented on a third active region1012c. In some embodiments, the first assembly1040aand the third assembly1040care dimensioned substantially the same such that the first body contact1050aand the second body contact1050bare positioned substantially symmetrically about a center line of the FET device1000.

The first body contact1050aincludes a plurality of first conductive features1036aimplemented to provide an electrical contact with a first body1034a. Similarly, the second body contact1050bincludes a plurality of second conductive features1036bimplemented to provide an electrical contact with a second body1034b.

Referring toFIG. 11, the first S/G/D assembly1040aincludes a plurality of gate fingers1024aimplemented over a first active region1012ato define strips or rows of the first active region1012a. A plurality of conductive features1032acan be implemented for such strips to form source and drains. When connected appropriately, such strips with corresponding conductive features can function as alternating source and drain strips or rows. The gate fingers1024aof the first S/G/D assembly1040acan be interconnected by a connecting metal1030a.

The second S/G/D assembly1040bincludes a plurality of gate fingers1024bimplemented over a second active region1012bto define strips or rows of the second active region1012b. A plurality of conductive features1032bcan be implemented for such strips or rows to form source and drains. When connected appropriately such strips with corresponding conductive features can function as alternating source and drain strips or rows. The gate fingers1024bof the second S/G/D assembly1040bcan be interconnected by a connecting metal1030bon one end and a connecting metal1030con the other end.

The third S/G/D assembly1040cincludes a plurality of gate fingers1024cimplemented over a third active region1012cto define strips or rows of the third active region1012c. A plurality of conductive features1032ccan be implemented for such strips or rows to form source and drains. When connected appropriately such strips with corresponding conductive features can function as alternating source and drain strips or rows. The gate fingers1024cof the third S/G/D assembly1040ccan be interconnected by a connecting metal1030d.

In the example ofFIG. 11, the connecting metal1030afor the first gate fingers1024aand the connecting metal1030bfor the second gate fingers1024bmay or may not be interconnected. Similarly, the connecting metal1030cfor the second gate fingers1024band the connecting metal1030dfor the third gate fingers1024cmay or may not be interconnected.

In the example ofFIG. 11, the conductive features1036a,1036bassociated with the first and second body contacts1050a,1050b, and the conductive features1032a,1032b,1032cassociated with the source and drain strips can include, for example, conductive vias, conductive trenches, or some combination thereof.

The following observations can be made when comparing the example ofFIGS. 10 and 11with the example ofFIGS. 6 and 7. Merely for the purpose of such a comparison, suppose that the length dimension of each of the first, second and third S/G/D assemblies1040a,1040b,1040cofFIGS. 10 and 11is L0, approximately the same as that of the S/G/D assembly40ofFIGS. 6 and 7. Further, suppose that the overall width dimension of the first S/G/D assembly1040a, the first body contact1050a, the second S/G/D assembly1040b, the second body contact1050b, and the third S/G/D assembly1040c(W2+body contact width+2×W2+body contact width+W2) ofFIGS. 10 and 11is similar to the overall width dimension of the first body contact650a, the S/G/D assembly640, and the second body contact650b(body contact width+W0+body contact width) ofFIGS. 6 and 7. In such a comparison, the width W2can be approximately a quarter of the width W0.

In such a configuration ofFIGS. 10 and 11, the farthest distance from a body contact (e.g., body contacts1050a,1050b) to any location on the S/G/D assemblies (e.g., S/G/D assemblies1040a,1040b,1040c) is approximately W2(e.g., a quarter of W0). In the configuration ofFIGS. 6 and 7, however, the farthest distance from a body contact (e.g., body contacts650a,650b) to any location on the S/G/D assembly (e.g., S/G/D assembly640) is approximately half of W0. Accordingly, the two body contacts1050a,1050bofFIGS. 10 and 11being distributed differently than the two body contacts650a,650bofFIGS. 6 and 7results in stronger body contact influence for the S/G/D assemblies of the former. For example, the first influence contour line1042aassociated with the first body contact1050acan cover substantially all the first S/G/D assembly1040aas well as most of the second S/G/D assembly1040b. Similarly, the first influence contour line1042bassociated with the second body contact1050bcan cover substantially all the third S/G/D assembly1040cas well as most of the second S/G/D assembly1040b. It is apparent that the overlapping coverage of the first influence lines1042aand1042bresults in the second S/G/D assembly1040bbeing strongly influenced by the first and second body contacts1050a,1050b.

Merely for descriptive purposes, the example configuration ofFIGS. 10 and 11can be referred to as a double-folded configuration, with the two body contacts1050a,1050bgenerally defining two fold lines. The first body contact1050aforms a T configuration with the first gate fingers1024aand forms a T configuration with the second gate fingers1024b. Similarly, the second body contact1050bforms a T configuration with the third gate fingers1024cand forms a T configuration with the second gate fingers1024b. Accordingly, the example configuration ofFIGS. 10 and 11can also be referred to as a double-folded T-shaped body contact configuration.

In some embodiments, one or more additional body contacts can be introduced to provide further reduction in body contact-to-body contact spacing and thereby increase the body contact influence at various locations of a FET device. In some embodiments, such reduction in body contact-to-body contact spacing can be balanced with any introduction or increase in narrow-width effects.

FIGS. 12-15illustrate examples of how source and drain connections can be implemented for the example FET devices800,1000ofFIGS. 9 and 11. More particularly,FIG. 12illustrates a FET device1200that is similar to the FET device800ofFIG. 9. In the example ofFIG. 12, the connecting metal1230afor the first gate fingers1224aand the connecting metal1230bfor the second gate fingers1224bcan be interconnected by a connecting metal1221to electrically connect the gate fingers on both sides of the body contact1250.

Similarly,FIG. 13illustrates a FET device1300that is similar to the FET device1000ofFIG. 11. In the example ofFIG. 13, the four connecting metals1330a,1330b,1330c,1330dcan be interconnected by a connecting metal1321to electrically connect the gate fingers.

Referring to the example ofFIG. 12, the alternating strips or rows of conductive features (e.g., conductive features832aand832binFIG. 9) can be electrically coupled or connected by a first metal, and the other alternating rows of conductive features can be connected by a second metal. For example, conductive features of the first row at the top and the third row from the top can be connected by a first metal (e.g., using a first metal M1) to form a source connection1260. Similarly, conductive features of the second row from the top and the fourth row from the top can be connected by the second metal (e.g., using a second metal M2) to form a drain connection1262. In some embodiments, a particular source finger of a first assembly1240acan be electrically connected to a source finger of a second assembly1240bthat is positioned on the same row as the particular source finger of the first assembly. Similarly, a particular drain finger of the first assembly1240acan be electrically connected to a drain finger of the second assembly1240bthat is positioned on the same row as the particular drain finger of the first assembly.

Referring to the example ofFIG. 13, the alternating rows of conductive features (e.g., conductive features1032a,1032band1032cinFIG. 11) can be connected by a first metal, and the other alternating rows of conductive features can be connected by a second metal. For example, conductive features of the first row at the top and the third row from the top can be connected by the first metal (e.g., M1) to form a source connection1360. Similarly, conductive features of the second row from the top and the fourth row from the top can be connected by the second metal (e.g., M2) to form a drain connection1362.

FIG. 14illustrates a FET device1400having a gate configuration similar to the example ofFIG. 12. The FET device1400can include a connecting metal1421configured to connect a first connecting metal1430ato a second connecting metal1430bto electrically connect gate fingers1424a,1424bon both sides of the body contact1450. In the example ofFIG. 14, however, a source connection1460can be made by connecting conductive features of a given strip or row in the first S/G/D assembly1440awith conductive features of an offset strip or row in the second S/G/D assembly1440b. For example, conductive features of the first row at the top of the second S/G/D assembly1440bcan be connected with conductive features of the second row from the top of the first S/G/D assembly1440a. Similarly, conductive features of the third row from the top of the second S/G/D assembly1440bcan be connected with conductive features of the fourth row from the top of the first S/G/D assembly1440a. Such two connections can be joined to form a source connection1460(e.g., using a first metal M1).

Similarly, conductive features of the first row at the top of the first S/G/D assembly1440acan be connected with conductive features of the second row from the top of the second S/G/D assembly1440b. Similarly, conductive features of the third row from the top of the first S/G/D assembly1440acan be connected with conductive features of the fourth row from the top of the second S/G/D assembly1440b. Such two connections can be joined to form a drain connection1462(e.g., using a second metal M2).

In some embodiments, a particular source finger of the first assembly1440acan be electrically connected to a source finger of the second assembly1440bthat is positioned on a row that is offset by one row from the particular source finger of the first assembly1440a. Similarly, a particular drain finger of the first assembly1440acan be electrically connected to a drain finger of the second assembly1440bthat is positioned on a row that is offset by one row from the particular drain finger of the first assembly1440a.

FIG. 15illustrates a FET device1500having a gate configuration similar to the example ofFIG. 13. In the example ofFIG. 15, however, a source connection1560can be made by connecting conductive features of a given row in a S/G/D assembly with conductive features of an offset row in the neighboring S/G/D assembly. For example, conductive features of the first row at the top of the first S/G/D assembly1540acan be connected with conductive features of the second row from the top of the second S/G/D assembly1540band conductive features of the first row at the top of the third S/G/D assembly1540c. Similarly, conductive features of the third row from the top of the first S/G/D assembly1540acan be connected with conductive features of the fourth row from the top of the second S/G/D assembly1540band conductive features of the third row from the top of the third S/G/D assembly1540c. Such two connections can be joined to form a source connection1560(e.g., using a first metal M1).

Similarly, conductive features of the second row from the top of the first S/G/D assembly1540acan be connected with conductive features of the first row at the top of the second S/G/D assembly1540band conductive features of the second row from the top of the third S/G/D assembly1540c. Similarly, conductive features of the fourth row from the top of the first S/G/D assembly1540acan be connected with conductive features of the third row from the top of the second S/G/D assembly1540band conductive features of the fourth row from the top of the third S/G/D assembly1540c. Such two connections can be joined to form a drain connection1562(e.g., using a second metal M2).

In some embodiments, the offset arrangement of source and drain connections in neighboring S/G/D assemblies can provide a number of advantages. For example, impact from undesirable process variations such as source/drain mismatch and/or active region (RX)/polysilicon contact (PC) misalignment can be reduced or mitigated.

For example, suppose that in the example ofFIGS. 4 and 5, the active region (RX)412of the FET device400is shifted to the left by an amount ΔW relative to the S/G/D assembly440. In such a situation, the effective width of the S/G/D assembly440is then W0−ΔW.

As illustrated inFIG. 16, suppose that a FET device1600configured in the same manner as the FET device1400in the example ofFIG. 14(which is based on the example ofFIGS. 8 and 9), is shifted with the same amount of RX shift (ΔW), resulting in an original RX position1670and a shifted RX position1672. In the original RX position1670, and referring to the dimensions ofFIG. 8, the total width associated with the S/G/D assemblies1640a,1640bis approximately W1+W1=2×W1. In the shifted RX position1672, the width of the first S/G/D assembly1640ais decreased by an amount ΔW, and width of the second S/G/D assembly1640bis increased by an amount ΔW. Accordingly, the total width associated with the S/G/D assemblies1640a,1640bis approximately (W1−ΔW)+W1+ΔW)=2×W1. Thus, one can see that for embodiments of FET devices having an even number of S/G/D assemblies, an impact in device parameter (e.g., S/G/D width) resulting from a shift in RX can be substantially canceled or reduced.

In another example, and as illustrated inFIG. 17, suppose that a FET device1700(configured in a manner similar to the FET device1400described herein with reference toFIG. 14) includes a polysilicon contact (PC) that is shifted downward (as illustrated inFIG. 17) from an original PC position1774to a shifted PC position1776. For the second S/G/D assembly1740b, two rows of source contacts can be farther away from the shifted PC position1776, while for the first S/G/D assembly1740a, two rows of drain contacts can be farther away from the shifted PC position1776. Accordingly, when the source and drain are connected respectively as indicated inFIG. 17, source/drain asymmetry resulting from a PC shift can be reduced.

In the various examples described herein with reference toFIGS. 8-17, it is assumed that S/G/D assemblies, as well as one or more body contacts in a given FET device are configured to form a generally symmetric FET device. It will be understood that, in some embodiments, a FET device having one or more features as described herein can be configured in non-symmetric manners with respect to one or more design parameters.

For example,FIG. 18illustrates a FET device1800having a body contact1850implemented between a first S/G/D assembly1840aand a second S/G/D assembly1840b, similar to the example FET device800ofFIG. 8. In the example ofFIG. 18, however, one or more design parameters of the FET device1800can be different between the first and second S/G/D assemblies1840a,1840b.

For example, either or both of L and W dimensions can be different among the first and second S/G/D assemblies1840a,1840b. InFIG. 18, the first S/G/D assembly1840ahas dimensions L1×W1, and the second S/G/D assembly1840bhas dimensions L2×W2. The values of L1and L2may or may not be the same. Similarly, the values of W1and W2may or may not be the same.

It is noted that in a configuration where the values of W1and W2are different, the position of the body contact1850is generally away from the middle.

In another example, the first and second S/G/D assemblies1840a,1840bcan have different numbers of fingers. InFIG. 18, the first S/G/D assembly1840ahas N1fingers, and the second S/G/D assembly1840bhas N2fingers. The values of N1and N2may or may not be the same.

In the various examples described herein with reference toFIGS. 8-17, it is assumed that S/G/D assemblies, as well as one or more body contacts in a given FET device are arranged along a single direction. For example, various S/G/D assemblies and respective body contact(s) are arranged along a horizontal direction.

FIG. 19illustrates that, in some embodiments, one or more features of the present disclosure can be implemented to provide a plurality of S/G/D assemblies arranged in two dimensions and separated by one or more body contacts. For example, four S/G/D assemblies1940a,1940b,1940c,1940dcan be implemented for a FET device1900, and such S/G/D assemblies can be separated by a cross-shaped body contact assembly indicated as1950. It will be understood that such a body contact assembly can have one or more body contacts.

For example, the body contact assembly1950can include a first body contact implemented between the first and second assemblies1940a,1940band a second body contact implemented between the third and fourth assemblies1940c,1940d. As another example, the body contact assembly1950can include a first body contact implemented between the first and third assemblies1940a,1940cand a second body contact implemented between the second and fourth assemblies1940b,1940d. As a further example, the body contact assembly1950can include a first body contact implemented between the first and second assemblies1940a,1940b, a second body contact implemented between the third and fourth assemblies1940c,1940d, a third body contact implemented between the first and third assemblies1940a,1940c, and a fourth body contact implemented between the second and fourth assemblies1940b,1940d.

Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general-purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers.

Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices.

Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general-purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means.

Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s).