Data storage device and an electronic device including the same

A data storage device may include a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0142307, filed on Oct. 12, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present inventive concept relate to a data storage device, and more particularly to an electronic device including the same.

DISCUSSION OF RELATED ART

Semiconductor devices may have high performance, high functionality, and high density. Various semiconductor package structures (e.g., POP (package-on-package): and MCP (multi-chip-package) structures) have been developed. However, heat may be generated in semiconductor package structures, and thus a semiconductor chip may be damaged, or functional or performance characteristics of the semiconductor devices may be reduced.

SUMMARY

One or more exemplary embodiments of the present inventive concept may provide a data storage device configured to efficiently discharge heat and an electronic device including the same.

According to one or more exemplary embodiments of the inventive concept, a data storage device includes a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.

The upper semiconductor chip may include a first memory chip, and the lower semiconductor chip may include a control chip controlling the first memory chip.

The data storage device may include a second memory chip disposed on the bottom surface of the package substrate and spaced apart from the control chip.

The package substrate may include a first interconnection line connecting the control chip to the first memory chip and extending in a first direction, and a second interconnection line connecting the at least one lower bump to the control chip and extending a second direction crossing the first direction.

The data storage device may include a mold layer disposed on the bottom surface of the package substrate.

The at least one lower bump may include a through-mold via passing through the mold layer.

The data storage device may include a passive device disposed on the package substrate and spaced apart from the upper semiconductor chip.

The data storage device may include at least one upper bump disposed between the upper semiconductor chip and the package substrate.

The package substrate may include a third interconnection line connecting the at least one upper bump to the passive device.

The data storage device may include a radiation element disposed on a bottom surface of the control chip. A stack thickness of the control chip and the radiation element may be smaller than a thickness of the at least one lower bump.

According to one or more exemplary embodiments of the inventive concept, an electronic device includes a main substrate and a data storage device disposed on a top surface of the main substrate. The data storage device includes a package substrate smaller than the main substrate. An upper semiconductor chip is disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.

The electronic device may include a first radiation element disposed on a bottom surface of the lower semiconductor chip. A stack thickness of the lower semiconductor chip and the first radiation element may be smaller than a thickness of the at least one lower bump.

The data storage device may include a mold layer disposed between the package substrate and the main substrate. The at least one lower bump may include a through-mold via passing through the mold layer.

The mold layer may be disposed on a bottom surface of the lower semiconductor chip. A stack thickness of the lower semiconductor chip and the mold layer on the bottom surface of the lower semiconductor chip may be smaller than a thickness of the at least one lower bump.

The electronic device may include a second radiation element disposed between the main substrate and the mold layer. A stack thickness of the lower semiconductor chip, the mold layer, and the second radiation element may be substantially equal to a thickness of the at least one lower bump.

According to one or more exemplary embodiments of the inventive concept, a data storage device includes a package substrate, and a first memory chip disposed on a top surface of the package substrate. A control chip is disposed on a bottom surface of the package substrate. At least one bump is disposed on the bottom surface of the package substrate and spaced apart from the control chip. The at least one bump is thicker than the control chip.

The data storage device may include a second memory chip disposed on the bottom surface of the package substrate and spaced apart from the control chip. The second memory chip may be thinner than the at least one bump.

The data storage device may include a mold layer disposed on the bottom surface of the package substrate to cover the control chip. The at least one bump may include a through-mold via passing through the mold layer.

The data storage device may include a passive device disposed on the top surface of the package substrate and spaced apart from the first memory chip.

The data storage device may include a radiation element disposed on a bottom surface of the control chip. A stack thickness of the control chip and the radiation element may be smaller than a thickness of the at least one bump.

According to one or more exemplary embodiments of the inventive concept, an electronic device includes a first substrate, and at least one first bump disposed on the first substrate. A second substrate is disposed on the at least one first bump. The second substrate has an area smaller than the first substrate. At least one second bump is disposed on the second substrate. A memory chip is disposed on the at least one second bump. A control chip is disposed between the at least one first bump and between the first and second substrates. The control chip is thinner than the at least one first bump.

The electronic device may include a mold layer disposed between the first substrate and the second substrate, and a through-mold via passing through the mold layer and connecting the first and second substrates to each other.

The mold layer may cover the control chip. A stack thickness of the control chip and the mold layer on a bottom surface of the control chip may be smaller than a thickness of the at least one first bump.

The electronic device may include a first radiation element disposed between the first substrate and the mold layer. A stack thickness of the control chip, the mold layer, and the first radiation element may be substantially equal to a thickness of the at least one first bump.

The electronic device may include a second radiation element disposed on a bottom surface of the control chip. A stack thickness of the control chip and the second radiation element may be smaller than a thickness of the east least one first bump.

The at least one first bump may be thicker than the at least one second bump.

DETAILED DESCRIPTION

Exemplary embodiments of the present inventive concept will now be described in more detail with reference to the accompanying drawings in which exemplary embodiments are shown. Exemplary embodiments of the present inventive concept may, however, may be embodied in various different forms, and should not be construed as being limited to the exemplary embodiments described herein.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it may be directly on the other element or intervening elements may be present. Exemplary embodiments of the present inventive concept may be described with reference to cross-sectional views. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Thus, exemplary embodiments of the present inventive concept are not limited to the specific shape illustrated in the exemplary views, but may include other shapes that may be created according to, for example, manufacturing processes.

Exemplary embodiments of the present inventive concept described herein may include their complementary counterparts. The same reference numerals or the same reference designators may refer to the same elements throughout the specification and drawings.

FIG. 1is a plan view illustrating an electronic device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 1, an electronic device10according to an exemplary embodiment of the present inventive concept may include a main substrate20, a control device30, a first data storage device40, and a second data storage device50. The control device30, the first data storage device40, and the second data storage device50may be disposed on the main substrate20. According to an exemplary embodiment of the present inventive concept, at least one of an interface, an input/output device, a graphic card, a LAN card, and a sound card may be disposed on the main substrate20. The control device30may control the first data storage device40and the second data storage device50. According to an exemplary embodiment of the present inventive concept, the control device30may perform an operation of writing or reading data to or from one or both of the first and second data storage devices40and50. The control device30may include, for example, a central processing unit (CPU). The first data storage device40may be used to temporarily store control signals of the control device30. For example, the first data storage device40may include at least one DRAM chip. Alternatively, the first data storage device40may include at least one SRAM chip. The first data storage device40with the SRAM chip and the control device30may be included in a single device. The second data storage device50may be used to non-temporarily store data output from the control device30. According to an exemplary embodiment of the present inventive concept, the second data storage device50may include at least one nonvolatile memory device. For example, the second data storage device50may include a solid-state drive (SSD).

FIG. 2is a cross-sectional view illustrating a main substrate, a control device, and a second data storage device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 2, the control device30and the second data storage device50may be disposed on the main substrate20. The main substrate20may be larger than the control device30and the second data storage device50. The control device30may be spaced apart from the second data storage device50. Alternatively, the control device30and the second data storage device50may be disposed on top and bottom surfaces, respectively, of the main substrate20.

FIG. 3is a cross-sectional view illustrating a second data storage device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 3, the second data storage device50may include a package substrate60, a first memory chip70, passive devices74, a control chip80, and a second memory chip90.

The first memory chip70, the passive devices74, the control chip80, and the second memory chip90may be disposed on the package substrate60. According to an exemplary embodiment of the present inventive concept, the package substrate60may include a lower interconnection pad61, an upper interconnection pad63, a first interconnection line62, a second interconnection line64, a third interconnection line66, and a fourth interconnection line68. The lower interconnection pad61may be disposed on a bottom surface of the package substrate60. The upper interconnection pad63may be disposed on a top surface of the package substrate60. The first to fourth interconnection lines62,64,66, and68may be disposed in the package substrate60.

The package substrate60may be smaller than the main substrate20. The package substrate60may be disposed on the main substrate20. The package substrate60and the main substrate20may be substantially parallel to each other. According to an exemplary embodiment of the present inventive concept, lower bumps82may be disposed between the top surface of the main substrate20and the bottom surface of the package substrate60. The lower bumps82may electrically connect the main substrate20to the package substrate60. For example, the lower bumps82may be disposed between the lower interconnection pad61and the main substrate20. The lower bumps82may penetrate a lower mold layer100. For example, the lower bumps82may include through-mold vias (TMVs). The lower mold layer100may be disposed between the package substrate60and the main substrate20.

The first memory chip70and the passive devices74may be disposed on the top surface of the package substrate60. The first memory chip70may be connected to the package substrate60through upper bumps72. The upper bumps72may serve as data transmission lines between the first memory chip70and the package substrate60. According to an exemplary embodiment of the present inventive concept, the upper bumps72may be smaller than the lower bumps82. For example, the number of the upper bumps72may be from about 100 to about 300. Each of the upper bumps72may electrically connect the first memory chip70to the upper interconnection pad63of the package substrate60. The first memory chip70may be configured to non-temporarily store data. According to an exemplary embodiment of the present inventive concept, the first memory chip70may include a non-volatile memory device. For example, the first memory chip70may include a plurality of vertically-stacked NAND FLASH memory chips.

The passive devices74may be spaced apart from the first memory chip70. At least one of the passive devices74may be configured to lower a level of a voltage to be supplied to the first memory chip70. According to an exemplary embodiment of the present inventive concept, at least one of the passive devices74may be configured to store or delay a current to be supplied to the first memory chip70. For example, the passive devices74may include at least one of a capacitor, a resistor, and an inductor. The passive devices74and the first memory chip70may be connected to each other through the upper bumps72, the upper interconnection pad63, and the first interconnection line62. The first interconnection line62may extend in a direction substantially parallel to the top surface of the main substrate20. The first interconnection line62may connect the upper interconnection pad63to at least one of the passive devices74. The second interconnection line64may connect at least one of the passive devices74to the lower interconnection pad61. The second interconnection line64may extend in a direction substantially perpendicular to the top surface of the main substrate20.

The control chip80and the second memory chip90may be disposed on the bottom surface of the package substrate60. According to an exemplary embodiment of the present inventive concept, the lower bumps82may be arranged to enclose the control chip80and the second memory chip90. The lower mold layer100may cover the control chip80and the second memory chip90.

The control chip80and the lower bumps82may be connected to each other through the lower interconnection pad61and the third interconnection line66. The lower bumps82may serve as data I/O terminals between the control chip80and the control device30. For example, the number of the lower bumps82may be the same as that of the number of upper bumps72. For example, the number of the lower bumps82may be from about 100 to about 300. The third interconnection line66may extend substantially parallel to the first interconnection line62. The third interconnection line66may be disposed below the first interconnection line62. The third interconnection line66may connect the control chip80to the second memory chip90. The fourth interconnection line68may extend substantially parallel to the second interconnection line64. The fourth interconnection line68may connect the control chip80to the upper interconnection pad63. The control chip80may be connected to the first memory chip70through the upper bumps72, the upper interconnection pad63, and the fourth interconnection line68.

The control chip80may control the first memory chip70and the second memory chip90. According to an exemplary embodiment of the present inventive concept, the control chip80may be configured to perform an operation of writing or reading data to or from one or both of the first and second memory chips70and90. For example, the control chip80may include an application processor (AP) chip. The control chip80may be thinner than the lower bumps82. A stack thickness of the control chip80and the lower mold layer100under the control chip80may be smaller than a thickness of each of the lower bumps82. The lower bumps82may have a thickness that is substantially equal to a distance between the main substrate20and the package substrate60.

The POP structure may include a lower package and an upper package on the lower package. The lower package may include a lower substrate, lower bumps, and a memory control chip. The upper package may include an upper substrate, upper bumps, and a memory chip. The stack thickness of the POP structure may be the sum of thicknesses of the lower substrate, the lower bumps, the memory control chip, the upper substrate, the upper bumps, and the memory chip.

The data storage device50according to an exemplary embodiment of the present inventive concept may have a stack thickness that is the sum of thicknesses of the lower bumps82, the package substrate60, the upper bumps72, and the first memory chip70. For example, the presence of the control chip80may lead to an increase of the stack thickness of the data storage device50. Thus, the stack thickness of the data storage device50may be smaller than that of the POP structure. Thus, the data storage device50may have a signal transmission length shorter than that of the POP structure.

The second memory chip90may be used to temporarily store data. For example, the second memory chip90may include at least one DRAM chip. Alternatively, the second memory chip90may be used to non-temporarily store data. The second memory chip90may include at least one SRAM chip. The second memory chip90may have a thickness that is smaller than that of the lower bumps82and is substantially equal to that of the control chip80.

Heat may be generated from the control chip80when data is processed by the control chip80. According to an exemplary embodiment of the present inventive concept, the electronic device10may have a first air gap G1between the main substrate20and the control chip80. The control chip80may be cooled by an air120(see, e.g.,FIG. 4) flowing through the first air gap G1.

FIG. 4is a plan view illustrating a flow of air flowing through an air gap between the second data storage device and the main substrate ofFIG. 3.

Referring toFIG. 4, air120may be heated by the control chip80, and heated air122may be exhausted to an outer region of the package substrate60. The main substrate20may be larger than the package substrate60in a plan view. As a result of convection, cool air124may be supplied to a region below the package substrate60from a region outside the control chip80. The lower bumps82may be arranged at or along an edge region of the package substrate60, and thus, the heated air122and the cool air124may flow through spaces between the lower bumps82. Thus, the control chip80may be cooled (e.g., to about room temperature) by the air120.

Referring toFIG. 3, the first air gap G1may be defined as an empty space that is positioned below the control chip80and between the lower mold layer100and the main substrate20. According to an exemplary embodiment of the present inventive concept, the first air gap G1may serve as an air passage for ventilation of the air120. The lower mold layer100below the control chip80may be an air cooling, heat-dissipation layer. The control chip80may be cooled by the lower mold layer100and the air120in the first air gap G1.

FIG. 5is a cross-sectional view illustrating a second data storage device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 5, the second data storage device50may include a first radiation element112. The first radiation element112may be disposed between the control chip80and the first air gap G1. For example, the first radiation element112may include a conductive silver paste or a metal block. The first radiation element112may allow heat generated from the control chip80to be transferred to the air120in the first air gap G1. Thus, the control chip80may be cooled by the first radiation element112and the air120in the first air gap G1. Alternatively, the first radiation element112may fill a gap region between the control chip80and the main substrate20, without the first air gap G1.

Each of the package substrate60, the first memory chip70, the upper bumps72, the passive devices74, the control chip80, the lower bumps82, and the second memory chip90described with reference toFIG. 5may be substantially the same as the corresponding components described with reference toFIG. 3, and thus duplicative descriptions may be omitted.

FIG. 6is a cross-sectional view illustrating a second data storage device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 6, the second data storage device50may include a second radiation element114. The second radiation element114may be disposed below the control chip80and between the lower mold layer100and the main substrate20. According to an exemplary embodiment of the present inventive concept, the second radiation element114may be disposed between the main substrate20and the lower mold layer100. The second radiation element114may be in contact with the top surface of the main substrate20and the bottom surface of the lower mold layer100. The second radiation element114may be configured to allow heat generated from the control chip80to be transferred to the main substrate20. For example, the second radiation element114may include a conductive silver paste, a metal block, or an under fill structure. According to an exemplary embodiment of the present inventive concept, the second radiation element114may be exposed to the first air gap G1between the lower mold layer100and the main substrate20. The second radiation element114may be cooled by the air120(see, e.g.,FIG. 4) flowing through the empty space between the lower mold layer100and the main substrate20.

Each of the package substrate60, the first memory chip70, the upper bumps72, the passive devices74, the control chip80, the lower bumps82, and the second memory chip90described with reference toFIG. 6may be substantially the same as the corresponding component described with reference toFIG. 3, and thus duplicative descriptions may be omitted.

FIG. 7is a cross-sectional view illustrating a second data storage device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 7, the lower mold layer100may expose the control chip80. A second air gap G2may be defined as an empty space between the control chip80and the main substrate20. The control chip80may be cooled by the air120flowing through the second air gap G2. The second memory chip90may be exposed to the second air gap G2. According to an exemplary embodiment of the present inventive concept, the lower mold layer100may cover the second memory chip90. The second air gap G2may be formed by removing the lower mold layer100from the bottom surface of the control chip80. A height of the second air gap G2may be greater than that of the first air gap G1, when measured from the main substrate20.

Each of the package substrate60, the first memory chip70, the upper bumps72, the passive devices74, the control chip80, the lower bumps82, and the second memory chip90described with reference toFIG. 7may be substantially the same as the corresponding component described with reference toFIG. 3, and thus duplicative descriptions may be omitted.

According to exemplary embodiments of the inventive concept, a data storage device may be disposed on a main substrate. The data storage device may include a package substrate, a memory chip, and a control chip. The memory chip may be disposed on the package substrate. The control chip may be disposed between the package substrate and the main substrate. The control chip may be efficiently cooled by an air flowing through an air gap between the main substrate and the control chip.