Method of forming a semiconductor device using a sacrificial uniform vertical thickness spacer structure

Disclosed is a method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method forms such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate structure. The use of an epitaxial growth process, as opposed to a deposition and etch process, ensures that the resulting spacers will have a uniform vertical thickness. Then, any process steps (e.g., implant and/or etch process steps) requiring the use of the gate sidewall spacers (e.g., as a mask or shield) are performed. Precise implant and/or etch profiles can be achieved, during these process steps, as a function of the uniformity of the gate sidewall spacers. Once such process steps are completed, the sidewall spacers are selectively removed. Optionally, before removing the sidewall spacers, they can be oxidized in order to enhance the selective removal process.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to semiconductor device processing and, more specifically, to a method of forming planar and non-planar semiconductor devices using a sacrificial uniform vertical thickness spacer structure.

2. Description of the Related Art

Sidewall spacers provide many fundamental functions in semiconductor processing. For example, typically following gate structure formation, a source/drain extension implantation process is performed in order to form source/drain extension regions with relatively low doping levels immediately adjacent to a gate structure. Next, gate sidewall spacers are formed. These gate sidewall spacers subsequently function as masks (i.e., as shields) during a source/drain region implantation process. The source/drain region implant process forms source/drain regions with relatively high doping levels offset from the gate structure by the width of the gate sidewall spacers (i.e., aligned to the gate sidewall spacers). Such sidewall spacers may similarly be used as masks (i.e., as shields) during other process steps, including but not limited to, salicide formation and/or etch steps.

Sidewall spacers are conventionally formed by conformally depositing one or more layers of dielectric materials, such as an oxide (e.g., silicon dioxide) and/or a nitride (e.g., silicon nitride), to a desired thickness. However, the conformal deposition results in less material being deposited around the top corners of the gate structure, with rounding occurring. Then, an anisotropic etch process is performed to remove the dielectric material from the horizontal surfaces. As illustrated inFIG. 18, while the etch process is selected to be anisotropic, the resulting sidewall spacers60are inevitably tapered (i.e., not uniform) as a result of different deposition rates and etching rates near the upper and lower corners of the gate structure20. That is, the thickness of the resulting sidewall spacers60is greater adjacent to the bottom surface of the gate structure closest to the substrate10(see first thickness65) than it is adjacent to the top surface of the gate structure20(see second thickness66).

As device sizes are scaled, achieving precise implant and/or etch profiles can be critical to achieving reliable electrical performance. For example, precise implant profiles can be critical for avoiding short channel effects, when implanting highly doped source/drain regions offset from the gate structure. Precise etch profiles can similarly be critical for avoiding such short channel effects, when etching trenches to be used for epitaxially grown source/drain regions offset from the gate structure. However, as a result of the tapered gate sidewall spacers, precise implant and/or etch profiles are difficult to achieve. That is, due to the tapered sidewall spacer structure, implant and/or etch profiles are inevitably graded. Such graded profiles can negatively impact device performance. Therefore, there is a need in the art for an improved method of forming planar and non-planar semiconductor devices using a uniform vertical thickness spacer structure in order to achieve precise implant and/or etch profiles and, thereby to optimize device performance.

SUMMARY

Disclosed herein are embodiments of an improved method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method embodiments form such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate structure. The use of an epitaxial growth process, as opposed to a deposition and etch process, to form the spacers ensures that the resulting spacers will have a uniform vertical thickness. Then, any process steps (e.g., implant and/or etch process steps) requiring the use of the gate sidewall spacers (e.g., as a mask or shield) are performed. Precise implant and/or etch profiles can be achieved, during these process steps, as a function of the uniformity of the gate sidewall spacers. Once such process steps are completed, the sidewall spacers are selectively removed. Optionally, before removing the sidewall spacers, they can be oxidized in order to enhance the selective removal process.

More particularly, disclosed herein are embodiments of a method of forming a non-planar semiconductor device (i.e., a vertical device, such as a fin-type field effect transistor (finFET)). The method embodiments comprise forming a semiconductor body (i.e., a semiconductor fin) for the non-planar semiconductor device on an insulator layer. Next, a gate structure is formed on the insulator layer adjacent to the semiconductor body. Specifically, the gate structure (e.g., a gate dielectric layer-gate conductor layer stack) is formed adjacent to the center portion of the semiconductor body on the opposing sidewalls and across the top surface.

After the gate structure is formed, sacrificial gate sidewall spacers are formed on the vertical sidewalls of the gate structure. These sacrificial gate sidewall spacers are specifically formed by selectively growing an epitaxial film (e.g., a silicon germanium (SiGe), silicon carbide (SiC), or silicon germanium carbide (SiGeC) film) on the vertical sidewalls of the gate structure so that the sidewall spacers have an essentially uniform thickness. That is, the use of an epitaxial growth process, as opposed to a deposition and etch process, to form the spacers ensures that the resulting sidewall spacers will have essentially the same thickness adjacent to the bottom surface of the gate structure closest to the insulator layer as they do adjacent to the top surface of the gate structure.

Once the sidewall spacers are formed, they can be used as masks (i.e., as shields) during at least one subsequent process step. Then, the sidewall spacers are selectively removed. It should be noted that the composition of the epitaxial film should be pre-selected so that it can be selectively etched over the material used in the gate structure. Additionally, prior to removal, the sidewall spacers can be oxidized in order to enhance the selective removal process. After the sidewall spacers are removed, additional processing can be performed in order to complete the semiconductor device structure.

Also disclosed herein are embodiments of a method of forming a planar semiconductor device (i.e., a horizontal device, such as a planar FET). The method embodiments comprise forming isolation structures (e.g., shallow trench isolation (STI) structures) to define an area of a semiconductor layer within which the planar semiconductor device will be formed. Then, a gate structure (e.g., a gate dielectric layer-gate conductor layer stack) for the planar semiconductor device is formed on the semiconductor layer and, particularly, above a designated channel region within the defined area of the semiconductor layer.

After the gate structure is formed, sacrificial gate sidewall spacers with uniform vertical thickness are formed on the vertical sidewalls of the gate structure. To form such sacrificial gate sidewall spacers, an epitaxial film (e.g., a silicon germanium (SiGe), silicon carbide (SiC), or silicon germanium carbide (SiGeC) film) is selectively grown such that it has a vertical portion on the vertical sidewalls of the gate structure and a horizontal portion on the semiconductor layer. After the epitaxial film is selectively grown, an anisotropic etch process is performed to remove the horizontal portion from the semiconductor layer. This anisotropic etch process further leaves the vertical portion on the vertical sidewalls of the gate structure so as to create sacrificial gate sidewall spacers having an essentially uniform thickness. That is, the remaining gate sidewall spacers will have essentially the same thickness adjacent to the bottom surface of the gate structure closest to the semiconductor layer as they do adjacent to the top surface of the gate structure. It should be noted that, while this method embodiment does use an anisotropic etch process, because the sidewall material is formed by selective epitaxy, the sidewall material is uniformly thick on the sidewalls from top to bottom, and thus the tapering of the resultant sidewall spacer is minimized or avoided altogether.

Alternatively, to form such sacrificial gate sidewall spacers, thin nitride spacers can be formed on the sidewalls of the gate structure by conventional means. A thin film of oxide layer can then be thermally grown on the exposed semiconductor layer and the exposed top surface of the gate structure. Next, the thin nitride spacers are selectively removed in order to expose the original gate sidewalls, while keeping the horizontal surfaces of both the semiconductor layer and the gate structure covered by the oxide layer. Then, a uniform thickness epitaxial film is selectively grown to create the sacrificial gate sidewall spacers. The resulting sacrificial sidewall spacers will have a vertical portion on the vertical sidewalls of the gate structure and a horizontal portion on the semiconductor layer.

Once the sidewall spacers are formed, they can be used as masks (i.e., as shields) during at least one subsequent process step. Then, the sidewall spacers are selectively removed. It should be noted that the composition of the epitaxial film should be pre-selected so that it can be selectively etched over the material used in the gate structure. Additionally, prior to removal, the sidewall spacers can be oxidized in order to enhance the selective removal process. After the sidewall spacers are removed, additional processing can be performed in order to complete the semiconductor device structure.

DETAILED DESCRIPTION

The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description.

As mentioned above, sidewall spacers provide many fundamental functions in semiconductor processing. Such sidewall spacers are conventionally formed by conformally depositing one or more layers of dielectric materials, such as an oxide (e.g., silicon dioxide) and/or a nitride (e.g., silicon nitride), to a desired thickness. However, the conformal deposition results in less material being deposited around the top corners of the gate structure, with rounding occurring. Then, an anisotropic etch process is performed to remove the dielectric material from the horizontal surfaces. As illustrated inFIG. 18, while the etch process is selected to be anisotropic, the resulting sidewall spacers60are inevitably tapered (i.e., not uniform) as a result of the different deposition rates and etching rates near the upper and lower corners of the gate structure20. That is, the thickness of the resulting sidewall spacers60is greater adjacent to the bottom surface of the gate structure closest to the substrate10(see first thickness65) than it is adjacent to the top surface of the gate structure20(see second thickness66).

As device sizes are scaled, achieving precise implant and/or etch profiles can be critical to achieving reliable electric performance. For example, precise implant profiles can be critical for avoiding short channel effects, when implanting highly doped source/drain regions offset from the gate structure. Precise etch profiles can similarly be critical for avoiding such short channel effects, when etching trenches to be used for epitaxially grown source/drain regions offset from the gate structure. However, as a result of the tapered gate sidewall spacers, precise implant and/or etch profiles are difficult to achieve. That is, due to the tapered sidewall spacer structure, implant and/or etch profiles are inevitably graded. Such graded profiles can negatively impact device performance.

In view of the foregoing, disclosed herein are embodiments of an improved method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method embodiments form such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate structure. The use of an epitaxial growth process, as opposed to a deposition and etch process, to form the spacers ensures that the resulting spacers will have a uniform vertical thickness. Then, any process steps (e.g., implant and/or etch process steps) requiring the use of the gate sidewall spacers (e.g., as a mask or shield) are performed. Precise implant and/or etch profiles can be achieved, during these process steps, as a function of the uniformity of the gate sidewall spacers. Once such process steps are completed, the sidewall spacers are selectively removed. Optionally, before removing the sidewall spacers, they can be oxidized in order to enhance the selective removal process.

More particularly, referring to the flow diagram ofFIG. 1, disclosed herein are embodiments of a method of forming a non-planar semiconductor device (i.e., a vertical device, such as a fin-type field effect transistor (finFET)). The method embodiments comprise providing a wafer (e.g., a silicon-on-insulator (SOI) wafer) (101). This wafer can comprise a substrate200(e.g., a single crystalline silicon substrate), an insulator layer210(e.g., a buried oxide layer) on the substrate200, and a semiconductor layer215(e.g., a single crystalline silicon layer) on the insulator layer210(seeFIG. 2). Additionally, the wafer can comprise a thin dielectric cap layer216on the semiconductor layer215(seeFIG. 2). This cap layer251can comprise, for example, an oxide (e.g., silicon dioxide) or a nitride (e.g., silicon nitride).

Next, at least one semiconductor body250for the non-planar semiconductor device is formed on the insulator layer210(102). Specifically, the dielectric cap layer216and semiconductor layer215can be patterned using conventional techniques (e.g., lithographic patterning or sidewall image transfer patterning techniques) to form one or more semiconductor bodies250(i.e., semiconductor fins) on the insulator layer210, each having a dielectric cap251covering its top surface (see the top view diagram ofFIG. 3Aand the different cross-section view diagrams ofFIGS. 3B-3C).

Next, a gate structure220is formed on the insulator layer210adjacent to a single semiconductor body250(as illustrated, in the top view diagram ofFIG. 3A) or, in the case of a multi-fin device, adjacent to multiple semiconductor bodies (104). Specifically, the gate structure220is formed adjacent to the center portion (i.e., the designated channel region255) of one or more semiconductor bodies250on the opposing sidewalls and across the top surface (see different cross-section views ofFIGS. 3B and 3C).

Gate structure formation can be accomplished using conventional processing techniques for non-planar devices. That is, a thin gate dielectric layer (e.g., an oxide layer, a high-k gate dielectric layer or any other suitable gate dielectric layer) can be formed (e.g., deposited) in a conformal layer over the semiconductor body. Next, a blanket polysilicon gate conductor layer221can be formed (e.g., deposited) on the gate dielectric layer. A dielectric cap layer222comprising, for example, an oxide (e.g., silicon dioxide) or a nitride (e.g., silicon nitride) is formed on the polysilicon gate conductor layer221. Next, the resulting gate stack (i.e., the cap layer222, gate conductor layer221and gate dielectric layer) is patterned (e.g., lithographically) to form a gate structure220that is positioned, as discussed above, adjacent to the center portion (i.e., the designated channel region255) of one or more semiconductor bodies250on the opposing sidewalls and across the top surface.

After the gate structure220is formed, processing steps that do not require the use of gate sidewall spacers can be performed. For example, a source/drain extension implantation process can be performed in order to form source/drain extension regions with relatively low doping levels within the semiconductor body (or bodies) immediately adjacent to the gate structure.

Then, sacrificial gate sidewall spacers260are formed on the vertical sidewalls225of the gate structure220(106, see the top view diagram ofFIG. 4Aand the different cross-section views ofFIGS. 4B-4C). These sacrificial gate sidewall spacers260are specifically formed by a selective epitaxial growth (SEG) process. That is, the sacrificial gate sidewall spacers260are formed by selectively growing an epitaxial film (e.g., a silicon germanium (SiGe), silicon carbide (SiC), or silicon germanium carbide (SiGeC) epitaxial film) on the vertical sidewalls225of the gate structure220and, more particularly, on the polysilicon gate conductor221so that the sidewall spacers260have an essentially uniform thickness (107).

This SEG process can be accomplished using, for example, conventional chemical vapor epitaxy, vapor phase epitaxy, etc. SEG process parameters (e.g., germanium and/or carbon concentrations, temperature, pressure, etc.) should be preselected so as to ensure uniform growth, to minimize Ge and/or C diffusion and to further allow for subsequent selective removal of the gate sidewall spacers260(at process112discussed in detail below). For example, in one embodiment an epitaxy film of SiGe can be formed with ambient gases comprising SiH2Cl2, GeH4with HCl at moderate temperatures in the range of 400° C. to 700° C.

It should be noted that since the gate structure220is formed, as described above, with the dielectric cap222, then the epitaxial film will not grow on the top surface226(i.e., the horizontal surface) of the gate structure220. Similarly, since the semiconductor body250is formed on an insulator layer210, the epitaxial film will also not grow on the horizontal surfaces immediately adjacent to the semiconductor body250. Thus, in this embodiment, the sidewall spacers260can be formed without the use of an anisotropic etch process. The use of a selective epitaxial growth process alone, as opposed to a deposition and etch process, to form the spacers260ensures that the resulting sidewall spacers260will have essentially the same thickness265adjacent to the bottom surface of the gate structure220closest to the insulator layer210as they do adjacent to the top surface226of the gate structure220.

Once the sidewall spacers260are formed, they can be used as masks (i.e., as shields) during at least one subsequent process step (110). Such subsequent process steps can include, but are not limited to, an implant process step, an etch process step, a salicide formation process step, etc. (111). For example, referring to the top view and cross section diagrams ofFIGS. 5A and 5B, respectively, the gate sidewall spacers260can function as masks (i.e., as shields) during a source/drain region implantation process. The source/drain region implant process forms source/drain regions256with relatively high doping levels offset from the gate structure220(and, thus, the channel region255) by the width265of the gate sidewall spacers260.

Then, the sidewall spacers260are selectively removed (112). It should be noted that the composition of the epitaxial film (e.g., the concentration of Ge and/or C in the epitaxial film) should be pre-selected so that it can be selectively etched over the polysilicon material used in the gate structure220. Those skilled in the art will recognize that various techniques (e.g., high temperature etch process, a plasma dry etch process, a wet etch process) are known for selectively etching SiGe, SiC and SiGeC over polysilicon. Optionally, prior to removal (e.g., either before or after process step110), the sidewall spacers260can be oxidized in order to enhance the selective removal process.

After the sidewall spacers260are removed, additional processing can be performed in order to complete the semiconductor device structure (114). This additional processing can include, but is not limited to, removal of the dielectric cap222from the top surface226of the gate structure220, salicide formation, interlayer dielectric deposition, contact formation, etc.

Referring toFIG. 7, also disclosed herein are embodiments of a method of forming a planar semiconductor device (i.e., a horizontal device, such as a planar FET). The method embodiments comprise providing a wafer (e.g., a silicon-on-insulator (SOI) wafer or bulk silicon wafer) (701). Isolation structures315(e.g., shallow trench isolation (STI) structures) can be formed (e.g., using conventional STI formation techniques) on the wafer300to define an area of a semiconductor layer350within which the planar semiconductor device will be formed (702, seeFIG. 8).

Then, a gate structure320for the planar semiconductor device is formed on the semiconductor layer350and, particularly, above a designated channel region355within the defined area of the semiconductor layer350(704, see top view and cross section diagrams ofFIGS. 9A and 9B, respectively). Specifically, gate structure320formation can be accomplished using conventional processing techniques for planar devices. That is, a thin gate dielectric layer (e.g., an oxide layer, a high-k gate dielectric layer or any other suitable gate dielectric layer) can be formed (e.g., deposited). Next, a blanket polysilicon gate conductor layer can be formed (e.g., deposited) on the gate dielectric layer. Optionally, a dielectric cap layer (not shown) comprising, for example, an oxide (e.g., silicon dioxide) or a nitride (e.g., silicon nitride) can be formed on the polysilicon gate conductor layer. Next, the resulting gate stack (i.e., the optional cap layer, gate conductor layer and gate dielectric layer) is patterned (e.g., lithographically) to form a gate structure320that is positioned above a center portion (i.e., the designated channel region355) of the semiconductor layer350.

After the gate structure320is formed, processing steps that do not require the use of gate sidewall spacers can be performed. For example, a source/drain extension implantation process can be performed in order to form source/drain extension regions with relatively low doping levels within the semiconductor body (or bodies) immediately adjacent to the gate structure.

Next, sacrificial gate sidewall spacers, having a uniform vertical thickness, are formed on the vertical sidewalls325of the gate structure320(706). In one embodiment, an epitaxial film360(e.g., a silicon germanium (SiGe), silicon carbide (SiC), or silicon germanium carbide (SiGeC) epitaxial film) is selectively grown such that it has a vertical portion361on the vertical sidewalls325of the gate structure320and a horizontal portion362on the semiconductor layer350immediately adjacent the gate structure320(707-708). It should be noted that if the gate structure is formed at process704without the optional dielectric cap, then the process of growing the epitaxial film will result in the growth of an additional horizontal portion363on the top surface326of the gate structure of the gate structure320(see top view and cross section diagrams, respectively, ofFIGS. 10A and 10B). However, if the gate structure320is formed with the optional dielectric cap, this dielectric cap with ensure that the epitaxial film360does not grow on the top surface326of the gate structure320.

The epitaxial film360is specifically formed by a selective epitaxial growth (SEG) process. This SEG process can be accomplished using, for example, conventional chemical vapor epitaxy, vapor phase epitaxy, etc. SEG process parameters (e.g., germanium and/or carbon concentrations, temperature, pressure, etc.) should be preselected so as to ensure uniform growth (i.e., that the film360has an essentially uniform thickness365), to minimize Ge and/or C diffusion and to further allow for subsequent selective removal (at process714discussed in detail below). For example, in one embodiment an epitaxy film of SiGe can be formed with ambient gases comprising SiH2Cl2, GeH4with HCl at moderate temperatures in the range of 400° C. to 700° C.

After the epitaxial film360is selectively grown, an anisotropic etch process (e.g., a reactive ion etch (RIE) process) is performed to remove the horizontal portion362from the semiconductor layer350and, if present, the additional horizontal portion363from the top surface326of the gate structure320(709-710, see top view and cross-section diagrams, respectively, ofFIGS. 11A and 11B). This anisotropic etch process further leaves the vertical portion361on the vertical sidewalls325of the gate structure320so as to create sacrificial gate sidewall spacers having an essentially uniform thickness. That is, the remaining vertical portion361of the epitaxial film360will function as gate sidewall spacers and will have essentially the same thickness365adjacent to the bottom surface of the gate structure320closest to the semiconductor layer350as they do adjacent to the top surface326of the gate structure320. It should be noted that, while this method embodiment does use an anisotropic etch process, the tapering of the resultant sidewall spacer361is minimized or avoided altogether because the sidewall material is formed by selective epitaxy, the sidewall material is uniformly thick on the sidewalls from top to bottom, and thus the tapering of the resultant sidewall spacer is minimized or avoided altogether.

Alternatively, after the gate structure320is formed, thin nitride (e.g., Si3N4) gate sidewall spacers1201can be formed on the sidewalls325of the gate structure320by conventional means (i.e., by conformal deposition followed by anisotropic etch to completely remove the Si3N4from horizontal surfaces) (712, seeFIG. 12). A thin oxide film1202(e.g., SiO2) can then be thermally grown on the exposed horizontal surface of the semiconductor layer350and the exposed top surface326of the gate structure320(713, seeFIG. 13). Next, the Si3N4thin spacers1201on the sidewalls325are selectively removed using an isotropic etch and, thereby exposing the original gate sidewalls325but keeping the horizontal surfaces of both the semiconductor layer350and the top326of the gate structure320covered by SiO21202(714, seeFIG. 14). Then, a uniform thickness epitaxial film1260(e.g., a silicon germanium (SiGe), silicon carbide (SiC), or silicon germanium carbide (SiGeC) film) is selectively grown, in the same manner as discussed above, to create the sacrificial gate sidewall spacers (714, seeFIG. 15). The resulting sacrificial gate sidewall spacers1260will have a vertical portion1261on the vertical sidewalls325of the gate structure320and a horizontal portion1262on the semiconductor layer350.

Once the sidewall spacers (e.g.,361ofFIG. 11Bor1260ofFIG. 15) are formed, they can be used as masks (i.e., as shields) during at least one subsequent process step (718). Such subsequent process steps can include, but are not limited to, an implant process step, an etch process step, a salicide formation process step, etc. (719). For example, the gate sidewall spacers361(as shown inFIG. 16, or the gate sidewall spacers1260ofFIG. 15) can function as masks (i.e., as shields) during a source/drain region implantation process. The source/drain region implant process forms source/drain regions356with relatively high doping levels offset from the gate structure320(and, thus, the channel region355) by the width365of the gate sidewall spacers361.

Then, the sacrificial sidewall spacers are selectively removed (720, seeFIG. 17). It should be noted that the composition of the epitaxial film (e.g., the concentration of Ge and/or C in the epitaxial film) should be pre-selected so that it can be selectively etched over the polysilicon material used in the gate structure320. Those skilled in the art will recognize that various techniques (e.g., high temperature etch process, a plasma dry etch process, a wet etch process) are known for selectively etching SiGe, SiC and SiGeC over polysilicon. Optionally, prior to removal (e.g., either before or after process step718), the sidewall spacers can be oxidized in order to enhance the selective removal process.

After the sidewall spacers are removed, additional processing can be performed in order to complete the semiconductor device structure (722). This additional processing can include, but is not limited to, removal of the optional dielectric cap from the top surface326of the gate structure320, salicide formation, interlayer dielectric deposition, contact formation, etc.

It should be understood that the corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. Additionally, it should be understood that the above-description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Well-known components and processing techniques are omitted in the above-description so as to not unnecessarily obscure the embodiments of the invention.

Finally, it should also be understood that the terminology used in the above-description is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises”, “comprising,” and/or “incorporating” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Therefore, disclosed above are embodiments of an improved method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method embodiments form such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate structure. The use of an epitaxial growth process, as opposed to a deposition and etch process, to form the spacers ensures that the resulting spacers will have a uniform vertical thickness. Then, any process steps (e.g., implant and/or etch process steps) requiring the use of the gate sidewall spacers (e.g., as a mask or shield) are performed. Precise implant and/or etch profiles can be achieved, during these process steps, as a function of the uniformity of the gate sidewall spacers. Once such process steps are completed, the sidewall spacers are selectively removed. Optionally, before removing the sidewall spacers, they can be oxidized in order to enhance the selective removal process. Benefits which flow from this invention include, but are not limited to, the ability to fabricate high-speed transistors at lower manufacturing cost, and provide lower power circuits at increased circuit densities. Furthermore, other structures may benefit from less-tapered structures, such as MicroElectroMechanical Structures (MEMS), where less-tapered mechanical structures can provide for more-robust mechanical systems, such as accelerometers, micro-mechanical switches, and so on.