Apparatus and method for symbol time recovery using feedback loop

Methods and an apparatus are provided. A first method includes receiving an estimated first arrival path (FAP); processing the estimated FAP; providing a rounding operation on the processed estimated FAP to generate an adjustment value for adjusting a fast Fourier transform (FFT) window; determining a quantization error based on the processed estimated FAP; and summing the quantization error to the processed estimated FAR A second method includes receiving an estimated FAP; determining a weighted average of the estimated FAP; processing the weighted average of the estimated FAP; providing a rounding operation on the processed weighted average of the estimated FAP to generate an adjustment value for adjusting an FFT window; determining a delayed STR adjustment based on the processed weighted average of the estimated FAP in a previous time slot; and summing the delayed STR adjustment to the processed weighted average of the estimated FAP in a current time slot.

FIELD

The present disclosure relates generally to a wireless communication system and, more particularly, to an apparatus and method for symbol time recovery (STR) using a feedback loop.

BACKGROUND

In a wireless communication system (e.g., a 5thgeneration (5G) communication receiver), a receiver may determine a symbol timing to demodulate symbols transmitted from a transmitter. An STR processor may be used to adjust a fast Fourier transform (FFT) timing window according to a time offset. A method of estimating a time offset (e.g., an STR method) may be based on first arrival path (FAP) estimation. An FAP indicates a time instance of a first path, which is at time 0 if there is no time offset. If there is a time offset, an FAP may be shifted accordingly. Based on an estimated FAP, an FFT timing window may be adjusted to a desired range to compensate for a time offset.

In a method using an STR processor, an FAP, as well as other timing-related parameters such as last arrival path (LAP) and center of mass (CoM), may be obtained by performing a moving sum operation on a channel power delay profile (PDP) (e.g., sliding a window of length W across a PDP and cumulatively summing the values of the windows), which may be obtained from a channel estimation (CE) processor. Different types of reference signals, e.g., tracking reference signal (TRS), a channel state information reference signal (CSI-RS), a synchronization signal block (SSB), a physical broadcast channel demodulation reference signal/secondary synchronization signal (PBCH DMRS/SSS), and a physical downlink shared channel DMRS (PDSCH DMRS), may be used to generate a PDP depending on specific configurations. A predefined threshold for a moving sum is used to determine an FAP. As a result, a method using an STR processor may be sensitive to a quality of an instantaneously estimated PDP and a choice of a threshold. For a fading channel with a small number of reference signals, a variance of an estimated FAP may be very large, causing incorrect FFT window placement.

Moreover, since a PDP may be obtained from a CE processor, a sampling rate of a PDP may be dependent on a numerology and a pattern of a specific reference signal (RS), which may be different from a sampling rate of an orthogonal frequency division multiplexing (OFDM) system. When a sampling rate of a PDP is much less than a sampling rate of a system, an estimated PDP may not accurately reflect a true time offset due to insufficient resolution.

SUMMARY

According to one embodiment, a method is provided. The method includes receiving an estimated first arrival path (FAP); processing the estimated FAP; providing a rounding operation on the processed estimated FAP to generate an adjustment value for adjusting a fast Fourier transform (FFT) window; determining a quantization error based on the processed estimated FAP; and summing the quantization error to the processed estimated FAP.

According to one embodiment, a method is provided. The method includes receiving an estimated FAP; determining a weighted average of the estimated FAP; processing the weighted average of the estimated FAP; providing a rounding operation on the processed weighted average of the estimated FAP to generate an adjustment value for adjusting an FFT window; determining a delayed STR adjustment based on the processed weighted average of the estimated FAP in a previous time slot; and summing the delayed STR adjustment to the processed weighted average of the estimated FAP in a current time slot.

According to one embodiment, an apparatus is provided. The apparatus includes a moving sum processor configured to estimate an FAP; a processor configured to process the estimated FAP; a rounding processor configured to perform a rounding operation on the processed estimated FAP to generate an adjustment value for adjusting an FFT window; a quantization error compensation processor configured to determine a quantization error based on the processed estimated FAP; and an adder configured to sum the quantization error to the processed estimated FAP.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the same elements will be designated by the same reference numerals although they are shown in different drawings. In the following description, specific details such as detailed configurations and components are merely provided to assist with the overall understanding of the embodiments of the present disclosure. Therefore, it should be apparent to those skilled in the art that various changes and modifications of the embodiments described herein may be made without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. The terms described below are terms defined in consideration of the functions in the present disclosure, and may be different according to users, intentions of the users, or customs. Therefore, the definitions of the terms should be determined based on the contents throughout this specification.

The present disclosure may have various modifications and various embodiments, among which embodiments are described below in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

The terms used herein are merely used to describe various embodiments of the present disclosure but are not intended to limit the present disclosure. Singular forms are intended to include plural forms unless the context clearly indicates otherwise. In the present disclosure, it should be understood that the terms “include” or “have” indicate existence of a feature, a number, a step, an operation, a structural element, parts, or a combination thereof, and do not exclude the existence or probability of the addition of one or more other features, numerals, steps, operations, structural elements, parts, or combinations thereof.

FIG.1is a block diagram of an apparatus for determining an FFT timing window using an STR processor, according to an embodiment. An apparatus100includes a CE processor101, the STR processor103, an FFT window determiner processor105, and an FFT processor107. In an embodiment, the CE processor101, the STR processor103, the FFT window determiner processor105, and the FFT processor107may be included in one processor, or the functionality of each may be distributed amongst a plurality of processors.

The CE processor101includes an output109for providing a PDP. The STR processor103includes an input connected to the output109of the CE processor101and an output111. The output111of STR processor103is an STR adjustment. The STR processor103uses the PDP to determine the STR adjustment based on the FAP. The inputs to the STR processor103may include PDP information from the CE processor101, parameters of circular shift Δcirccircular shift to the right) and a sliding window length W, which may be used in a moving sum algorithm. To estimate different timing-related parameters such as FAP, LAP, and median, thresholds for estimating each of them may also be provided. Then a circular shift operation is performed which is useful in addressing negative time offset, followed by calculating a moving sum of the PDP with a window length W. Finally, FAP/LAP/median may be calculated using the provided thresholds in the same manner.

The FFT window determiner processor105includes an input connected to the output111of the STR processor103for receiving the STR adjustment and an output113for outputting a received signal in the determined FFT window. The FFT window determiner processor105places an FFT window on a received signal based on the STR adjustment to extract the portion of the received signal that is in the determined FFT window. The FFT processor107includes an input connected to the output113of the FFT window determiner processor105for receiving the portion of the received signal that is within the determined FFT window. The FFT processor107applies FFT processing on the signal received from the FFT window determiner processor105.

FIG.2is a block diagram of the STR processor103ofFIG.1, according to an embodiment.

Referring toFIG.2, the STR processor (or feedback loop processor)103includes a moving sum processor201, a subtractor203, a gain stage205(e.g., an amplifier), an adder207, a delay stage209, and a rounding processor211. In an embodiment, the functionality of the moving sum processor201and the rounding processor211may be included in one processor, or the functionality of each may be distributed amongst a plurality of processors.

The moving sum processor201includes an input connected to the output109of the CE processor101for receiving the PDP, and an output213for providing an estimate of an FAP z′. The subtractor203includes a first input connected to the output213of the moving sum processor201for receiving the estimated FAP z′, a second input215for receiving a nonzero FAP offset n (e.g., a target FAP offset), and an output217for subtracting the nonzero FAP offset γtfrom the estimated FAP z′ to provide the difference as an intermediate STR adjustment τc. The nonzero FAP offset γthelps to prevent STR adjustment from overshooting the correct timing point and facilitate the shift of the FFT window within a desired region.

The nonzero FAP offset γtis integrated into the SIR processor103. The goal of such nonzero FAP offset γtis to leave room for possible estimation error and prevent the FFT window from being placed behind the correct timing position. For example, Equation (8) below, shows that the effect of γtin the feedback loop is equivalent to subtracting γtfrom an infinite impulse response (IIR) filtered FAP estimation Sn, and the STR adjustment, τa,n(323), obtained from the feedback loop, is actually equal to Sn−γt. With a true time offset denoted as βT0and a received signal denoted as y(n), the received signal after applying the STR adjustment may be as in Equation (1) as follows:
y(n−βT0+[τa,n])=y(n−βT0+[Sn]−γt)  (1)

If there is an estimation error δ>0 such that [Sn]=βT0+δ, then the received signal in Equation (1) above may be as in Equation (2) as follows:
y(n−βT0+[τa,n])=y(n+δ−γt)  (2)

If there is no nonzero FAP offset such that γt=0, the received signal becomes γ(n+δ). Thus, the FFT window may be placed behind the correct timing due to estimation error, which may cause inter-symbol interference (ISI). However, if there is a proper nonzero FAP offset such that γt>8, then n+δ−γt<n. Thus, the FFT window is placed before the correct timing. Due to a cyclic prefix (CP) in an OFDM system, there will be no ISI in such a situation.

The gain stage205includes an input connected to the output of the subtractor203and an amplifier output219, where the gain stage205has loop gain α. The gain stage205applies the loop gain α to the intermediate STR adjustment to obtain an amplified intermediate STR adjustment. The adder207includes a first input connected to the output219of the gain stage205for receiving the amplified intermediate STR adjustment, a second input221for receiving a delayed accumulated STR adjustment, and an output223, where the output223of the adder207provides an accumulated STR adjustment τa. That is, τaresults from subtracting γtfrom estimated FAP z′, multiplying the difference by a, and adding the delayed accumulated STR adjustment to the product.

The delay stage209includes an input connected to the output223of the adder207for receiving the accumulated STR adjustment and an output connected to the second input221of the adder207for providing the delayed accumulated STR adjustment. The rounding processor211includes an input connected to the output223of the adder207for receiving the accumulated STR adjustment and an output connected to the output111of the STR processor103for providing a rounded STR adjustment. The rounding processor211applies a rounding operation to the accumulated STR adjustment to obtain a rounded accumulated STR adjustment. Since an FFT window shift must be an integer number of samples, a rounding operation is applied by the rounding processor211on the accumulated STR adjustment. The FFT timing window is adjusted according to the rounded accumulated STR adjustment.

FIG.3is a block diagram of the STR processor103ofFIG.1, according to an embodiment.

Referring toFIG.3, the STR processor103includes a moving sum processor301, a subtractor303, a gain stage305(e.g., an amplifier), an adder307, a quantization error compensation processor309, and a rounding processor311. In an embodiment, the moving sum processor301, the quantization error compensation processor309, and the rounding processor311may be included in one processor, or the functionality of each may be distributed amongst a plurality of processors.

The moving sum processor301includes an input connected to the output109of the CE processor101for receiving the PDP, and an output313for providing an estimate of an FAP z′. The subtractor303includes a first input connected to the output313of the moving sum processor301for receiving the instantaneous estimated FAP z′ without any STR adjustment, a second input315for receiving a nonzero FAP offset γtto be subtracted from the estimated of an FAP z′, and an output317to provide the difference as an intermediate STR adjustment τc.

The gain stage305includes an input connected to the output317of the subtractor303and an amplifier output319for providing an amplified intermediate STR adjustment, where the gain stage305has loop gain α. The adder307includes a first input connected to the amplifier output319of the gain stage305, a second input321for receiving a quantization error compensated accumulated STR adjustment, and an output323, where the output323of the adder307provides the accumulated STR adjustment τa.

The quantization error compensation processor309includes an input connected to the output323of the adder307and an output connected to the second input321of the adder307. The quantization error compensation processor309adds quantization error compensation to the amplified intermediate STR adjustment to obtain an accumulated STR adjustment. The rounding processor311includes an input connected to the output323of the adder307and an output connected to the output111of the STR processor103. The rounding processor311applies a rounding operation to the accumulated STR adjustment to obtain a rounded accumulated STR adjustment. In order to compensate for a quantization error from the rounding operation, an embodiment of the present disclosure includes the STR processor103having the quantization error compensation processor309. The STR processor103reduces the variance of the estimated FAP z′ and makes the estimated FAP z′ more stable around the true FAP z. The FFT timing window is adjusted according to the rounded accumulated STR adjustment.

Since an FFT window shift must be an integer number of samples, a rounding operation is applied by the rounding processor311on the accumulated STR adjustment τa, which may cause a quantization error. One embodiment of the present disclosure includes the quantization error compensation processor309that is integrated into the STR processor103to compensate for an error from the rounding operation.

FIG.4is a block diagram of the STR processor103ofFIG.1, according to an embodiment.

Referring toFIG.4, the STR processor103includes a moving sum processor401, a weighted average processor403, a subtractor405, a gain stage407(e.g., an amplifier), an adder409, a delay stage411, and a rounding processor413. In an embodiment, the moving average processor401, the weighted average processor403, and the rounding processor413may be included in one processor, or the functionality of each may be distributed amongst a plurality of processors.

The moving sum processor401includes an input connected to the output109of the CE processor101for receiving the PDP, and an output415for providing the estimate of the FAP z′. The weighted average processor403includes an input connected to the output415of the moving sum processor401for receiving the estimated FAP z′ and an output417for providing a weighted average of the estimated FAP z′. The subtractor405includes a first input connected to the output417of the weighted average processor403, a second input419for receiving the nonzero FAP offset γt(e.g., the target FAP offset), and an output421, where the output421of the subtractor405provides an intermediate STR adjustment τc(i.e., the modified FAP). The weighted average processor403may use an instantaneous PDP with a mask to refine the output417. A mask operation is applied on the change of the estimated FAP before and after the weighted average processor403to refine the output417of the weighted average and constrain the correction from weighted average within a reasonable range. The amount of change may be scaled by an output of a raised cosine filter applied on a power ratio of instantaneously estimated PDP.

When the resolution of the PDP is low (i.e., the sampling rate of the PDP is much less than the sampling rate of the OFDM system), the weighted average processor403is activated. The weighted average processor403may receive the estimated FAP z′ and the PDP as input, and output a refined FAP. With the input FAP denoted as r and the PDP denoted as P(t), the refined FAP from weighted average is as in Equation (3) as follows:

τ′=∑t=τ-wlτ+wrt·P⁡(t)∑t=τ-wlτ+wrP⁡(t)(3)
where wland wrdenote the left and right window size, respectively, where weighted average is performed within.

The effect of the weighted average processor403is to obtain an averaged FAP estimation based on the PDP around it. However, since the weighted average is calculated from the instantaneous PDP, the quality of the PDP estimation affects the results. Ideally, the power of the channel tap at FAP should be greater than the power of channel taps round the channel tap at FAP. However, for an instantaneously calculated PDP, it is possible that the power of channel taps around FAP is greater than the power of the channel tap at FAP, which may cause the refined FAP τ′ to be incorrectly shifted by a large amount. In order to constrain the amount of the shift, a masking operation based on the power ratio may be applied. After τ′ is calculated, the amount of shift may be as in Equation (4) as follows:
Δτ=τ′−τ  (4)
and depending on whether Δτis greater than or less than 0, the power ratio may be as in Equation (5) as follows:

If the power ratio r is too large, τ′ may have been greatly shifted as compared to τ, so τ′ may not be reliable. In order to constrain the shift, a mask H(r) may be applied on r, which may be a raised cosine filter as in Equation (6) as follows:

For example, a raised cosine filter may have T=½,β=1.

An amount of the shift Δτmay be scaled by H(r) and added back to obtain a refined FAP as in Equation (7) as follows:
τ′=τ+Δτ·H(r)  (7)
which is the final output of the weighted average processor503.

The gain stage407includes an input connected to the output421of the subtractor405to receive the intermediate STR adjustment τcand an amplifier output423for providing an amplified intermediate STR adjustment, where the gain stage407has loop gain α. The adder409includes a first input connected to the output423of the gain stage407, a second input425for receiving a delayed accumulated STR adjustment, and an output427, where the output427of the adder409provides the accumulated STR adjustment τa.

The delay stage411includes an input connected to the output427of the adder409and an output connected to the second input425of the adder409. The rounding processor413includes an input connected to the output427of the adder409and an output connected to the output111of the STRP processor103for providing the adjusted STR.

FIG.5is a block diagram of the STR processor103ofFIG.1, according to an embodiment.

Referring toFIG.5, the STR processor103includes a moving sum processor501, a weighted average processor503, a subtractor505, a gain stage507(e.g., an amplifier), an adder509, a quantization error compensation processor511, and a rounding processor513. In an embodiment, the moving average processor501, the weighted average processor503, the quantization error compensation processor511, and the rounding processor513may be included in one processor, or the functionality of each may be distributed amongst a plurality of processors.

The moving sum processor501includes an input connected to the output109of the CE processor101for receiving the PDP, and an output515for providing the estimate of the FAP z′. The weighted average processor503includes an input connected to the output515of the moving sum processor501for receiving the estimated FAP z′ and an output517for providing a weighted average of the estimated FAP z′. The subtractor505includes a first input connected to the output517of the weighted average processor503, a second input519for receiving the nonzero FAP offset γt(e.g., the target FAP offset), and an output521, where the output521of the subtractor505provides an intermediate STR adjustment τc(i.e., the modified FAP). The weighted average processor503may use an instantaneous PDP with a mask to refine the output517. A mask operation is applied on the change of the estimated FAP before and after the weighted average processor503to refine the output517of the weighted average and constrain the correction from weighted average within a reasonable range. The amount of change may be scaled by an output of a raised cosine filter applied on a power ratio of the instantaneously estimated PDP.

The gain stage507includes an input connected to the output521of the subtractor505to receive the intermediate STR adjustment τcand an amplifier output523for providing an amplified intermediate STR adjustment, where the gain stage507has loop gain α. The adder509includes a first input connected to the output523of the gain stage507, a second input525for receiving a quantization error compensated accumulated STR adjustment, and an output527, where the output527of the adder509provides the accumulated STR adjustment τa.

Since an FFT window shift must be an integer number of samples, a rounding operation is applied by the rounding processor513on the accumulated STR adjustment τa, which may cause a quantization error. One embodiment of the present disclosure includes the quantization error compensation processor511that is integrated into the STR processor103to compensate for an error from the rounding operation. One embodiment of the present disclosure further includes the weighted average processor503for determining an adaptive weighted average with a mask to control a level of refinement when the resolution of the PDP is low. Since the adaptive weighted average utilizes the instantaneous estimated PDP, the adaptive weighted average may be sensitive to the estimation quality of the PDP. One embodiment of the present disclosure further applies a mask operation on the output of the weighted average processor503, which provides a much more robust refinement. The weighted average leads to better STR adjustment when the resolution of PDP is low and the number of resource blocks (RBs) is small.

FIG.6is an illustration of a mathematical principle of a feedback loop, according to an embodiment.

Referring toFIG.6, the mathematical principle includes a first subtractor601, a second subtractor603, a gain stage605(e.g., an amplifier), an adder607, quantization error compensation609, and a rounding611.

The first subtractor601includes a first input613for receiving an estimated FAP z assuming no STR adjustment is applied, a second input627for rounded τa, and an output615for providing an estimated FAP z′ assuming the STR adjustment of rounded τais applied. The second subtractor603includes a first input connected to the output615of the first subtractor601for receiving the instantaneous estimated FAP z′, a second input617for receiving a nonzero FAP offset γtto be subtracted from the estimated FAP z′, and an output619to provide the difference as an intermediate STR adjustment τc.

The gain stage605includes an input connected to the output619of the second subtractor603and an amplifier output621for providing an amplified intermediate STR adjustment, where the gain stage605has loop gain α. The adder607includes a first input connected to the amplifier output621of the gain stage605, a second input623for receiving a quantization error compensated accumulated STR adjustment, and an output625, where the output625of the adder607provides the accumulated STR adjustment τa.

The quantization error compensation609includes an input connected to the output625of the adder607and an output connected to the second input623of the adder607. The quantization error compensation609adds quantization error compensation to the amplified intermediate STR adjustment to obtain an accumulated STR adjustment. The rounding611includes an input connected to the output625of the adder607and an output627connected to the second input of the first subtractor613. The rounding611applies a rounding operation to the accumulated STR adjustment to obtain a rounded accumulated STR adjustment. In order to reduce a variance of the estimated FAP z′, as well as to compensate for a quantization error of the FAP z′, an embodiment of the present disclosure includes the quantization error compensation609. The mathematical principle reduces the variance of the estimated FAP z′ and makes the estimated FAP z′ more stable around the true FAP

An error caused from the rounding may be compensated for by the quantization error compensation as expressed in Equation (8), which corresponds toFIG.6, as follows:
τa,n=Sn−γt=τa,n-1+α·τc,n+α·([τa,n-1]−τa,n-1)  (8)
where subscript n denotes the time instance, [⋅] denotes the rounding operation, and Snis the IIR filter on the estimated FAP znassuming no STR adjustment is applied, which may be as in Equation (9) as follows:
Sn=IIRα(zn)=α·zn+(1−α)·Sn-1(9)

Equation (8) above indicates that the accumulated STR adjustment τa,n, which may be obtained as τa,n-1+α·τc,n+α·([τa,n-1]−τa,n-1) is in fact equivalent to the IIR filtered version of the estimated FAP znsubtracted by nonzero FAP offset γt. Since γtis a constant, the variance of τa,nis equivalent to the variance of Sn. Thus, the variance of τa,nmay be as in Equation (10) as follows:

στ2=σS2=α2-α⁢σz2(10)
where στ2, σS2, σz2denote the variances of τa,n, Sn, zn, respectively. By choosing the loop gain α<1, the variance of the accumulated STR adjustment, στ2, is reduced as compared to the variance of the estimated FAP without STR adjustment, σz2.

FIG.7is a block diagram of the quantization error compensation processor309,511, and609ofFIGS.3,5, and6, respectively, according to an embodiment.

Referring toFIG.7, the quantization error compensation processor309,511, and609includes a delay stage701, a rounding processor703, a subtractor705, a gain stage707(e.g., an amplifier), and an adder709. In an embodiment, the functionality of the rounding processor703may be distributed amongst a plurality of processors.

The delay stage701includes an input connected to the output323,527, and625of the adder307,509, and607of the STR processor103for receiving the accumulated STR adjustment τa, respectively, and an output711. The rounding processor703includes an input connected to the output711of the delay stage701and an output713.

The subtractor705includes a first input connected to the output713of the rounding processor703, a second input connected to the output711of the delay stage701for receiving a value to be subtracted from the first input connected to the output713of the rounding processor703, and an output715. The gain stage707includes an input connected to the output715of the subtractor705and an output717, where the gain stage707has loop gain α. The adder709includes a first input connected to the output717of the gain stage707, a second input connected to the output711of the delay stage701, and an output connected to the output321,525, and623of the quantization error compensation processor309,511, and609, respectively.

FIG.8is a flowchart of a method of generating a rounded STR adjustment, according to an embodiment. A step performed by a processor may be distributed amongst a plurality of processors.

Referring toFIG.8, the method receives a PDP at801.

At803, an instantaneous FAP z′ is estimated. The instantaneous FAP z′ may be estimated by performing a moving sum across a channel PDP using a window of length W. The PDP may be determined by channel estimation using an RS.

At805, a nonzero FAP offset γtis applied to the estimated instantaneously estimated FAP z′ to generate an intermediate STR adjustment τc.

At807, the intermediate STR adjustment τcis amplified by a loop gain α.

At809, quantization error compensation is added to the amplified intermediate STR adjustment τcto generate an STR adjustment τa.

At811, the STR adjustment τais rounded, which is the output of the STR processor103.

FIG.9is a flowchart of a method of generating a rounded STR adjustment, according to an embodiment. A step performed by a processor may be distributed amongst a plurality of processors.

Referring toFIG.10, the method receives a PDP at901.

At903, an instantaneous FAP z is estimated. The instantaneous FAP z′ may be estimated by performing a moving sum across a channel PDP using a window of length W. The PDP may be determined by channel estimation using an RS.

At905, a weighted average of the estimated instantaneous FAP z′ is determined. The weighted average may obtain an averaged FAP estimation based on the PDP around it. The weighted average may further include a masking operation based on a power ratio to constrain an amount of shift of the weighted averaged FAP. In an embodiment, the weighted average may be omitted.

At907, a nonzero FAP offset γtis applied to the weighted average of the estimated instantaneously estimated FAP z′ to generate an intermediate STR adjustment τc.

At909, the intermediate STR adjustment τcis amplified by a loop gain α.

At911, a delayed STR adjustment τa(i.e., STR adjustment in the previous time slot) is added to the amplified intermediate STR adjustment τcto generate an STR adjustment τa.

At913, the STR adjustment τais rounded, which is the output of the STR processor103.

FIG.10is a flowchart of a method of generating a rounded STR adjustment, according to an embodiment. A step performed by a processor may be distributed amongst a plurality of processors.

Referring toFIG.10, the method receives a PDP at1001.

At1003, an instantaneous FAP z′ is estimated. The instantaneous FAP z′ may be estimated by performing a moving sum across a channel PDP using a window of length W. The PDP may be determined by channel estimation using an RS.

At1005, a weighted average of the estimated instantaneous FAP z′ is determined. The weighted average may obtain an averaged FAP estimation based on the PDP around it. The weighted average may further include a masking operation based on a power ratio to constrain an amount of shift of the weighted averaged FAP. In an embodiment, the weighted average may be omitted.

At1007, a nonzero FAP offset γtis applied to the weighted average of the estimated instantaneously estimated FAP z′ to generate an intermediate STR adjustment τc.

At1009, the intermediate STR adjustment τcis amplified by a loop gain α.

At1011, quantization error compensation is added to the amplified intermediate STR adjustment τcto generate an STR adjustment τa.

At1013, the STR adjustment τais rounded, which is the output of the STR processor103.

An electronic device according to various embodiments may be one of various types of electronic devices. The electronic devices may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According various embodiments, the electronic devices are not limited to those described above.

As used herein, the term “processor” may include a unit implemented in hardware, software, or firmware, and may interchangeably be used with other terms, for example, “logic,” “logic block,” “part,” or “circuitry”. A processor may be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, a processor may be implemented in a form of an application-specific integrated circuit (ASIC).

Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure may be modified in various forms without departing from the scope of the present disclosure. Thus, the scope of the present disclosure shall not be determined merely based on the described embodiments, but rather determined based on the accompanying claims and equivalents thereto.