Frequency synthesizer using two phase locked loops

The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

FIELD OF THE INVENTION

The application relates to a frequency synthesizer.

BACKGROUND OF THE INVENTION

FIG. 1is a diagram illustrating a prior art frequency synthesizer employing one phase locked loop. Referring toFIG. 1, the frequency synthesizer, i.e. a single phase locked loop has a reference frequency oscillator11, a phase detector12, a low pass filter13, a voltage controlled oscillator14and a frequency divider15.

A synthesized frequency Fout is N times the reference frequency Fref being outputted from the reference frequency oscillator11. Accordingly, the synthesizer having the output frequency Fout that is integer times the reference frequency Fref is called an integer-N frequency synthesizer.

However, the prior art frequency synthesizer has various disadvantages. For example, a phase noise performance is degraded when a channel spacing is reduced. The channel spacing refers to a spacing between frequencies that may be obtained by using the frequency synthesizer. In case of the integer-N phase locked loop ofFIG. 1, the output frequency Fout is integer times the reference frequency Fref. Thus, the output frequency Fout may be increased or decreased by a unit of the reference frequency Fref, and the channel spacing is same as the reference frequency Fref.

Therefore, the reference frequency Fref should be lowered in order to reduce the channel spacing, that is, to in order to obtain dense frequencies. However, for stability of the phase locked loop, it is preferable that a bandwidth of the phase locked loop is less than one tenth of the reference frequency Fref. Therefore, the reference frequency Fref should be reduced in order to reduce the channel spacing, but the bandwidth is also reduced when the reference frequency Fref is reduced. Moreover, the phase noise is increased as the bandwidth of the phase locked loop is decreased because of an effect of a phase noise of the voltage controlled oscillator14.

For example, when the output frequency Fout is required to be varied by having the channel spacing of 100 KHz within a range between 2.0 GHz and 2.1 GHz, the reference frequency Fref should be 100 KHz, and N should be capable of being varied within a range between 20000 and 21000. In addition, it is preferable that the bandwidth of the phase locked loop is no more than 10 KHz.

SUMMARY OF THE INVENTION

An object of embodiments of the application is to reduce or solve at least the above problems and/or disadvantages in the related art or to provide at least the advantages described herein in whole or in part.

Another object of the application is to provide a frequency synthesizer having a low phase noise characteristic while having narrow channel spacing.

Another object of the application is to provide a frequency synthesizer having a low phase noise characteristic while having a narrow channel spacing by overcoming a correlation between the channel spacing and the phase noise.

Another object of the application is to provide a frequency synthesizer having a low phase noise characteristic while having a narrow channel spacing by using two phase locked loops.

To achieve objects of the application in whole or in part, there is provided a frequency synthesizer that can include an integer-N phase locked loop to receive a signal having a reference frequency to output a signal having a first output frequency, a fractional-N phase locked loop to receive the signal having the reference frequency to output a signal having a second output frequency and a circuit to combine the signal having the first output frequency and the signal having the second output frequency to output a signal having an output frequency of the frequency synthesizer.

To achieve objects of the application in whole or in part, there is provided a frequency synthesizer that can include a reference frequency oscillator to output a reference frequency signal, an integer-N phase locked loop to receive the reference frequency signal to output a signal having a first output frequency, a fractional-N phase locked loop to receive the reference frequency signal to output a signal having a second output frequency, a first divider to receive the signal having the second output frequency to output an in-phase signal having a third output frequency corresponding to 1/L of the second output frequency, a second divider to receive the signal having the second frequency to output a quadrature signal having the third output frequency, a first frequency adder to receive the signal having the first output frequency and the in-phase signal having the third output frequency to output an in-phase signal having a frequency corresponding to a sum of the first output frequency and the third output frequency and a second frequency adder to receive the signal having the first output frequency and the quadrature signal having the third output frequency to output a quadrature signal having the frequency corresponding to the sum of the first output frequency and the third output frequency, wherein L is an integer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments according to the application will be described with reference to the accompanying drawings. Such embodiments are exemplary and not to be construed as limiting. Many alternatives, modifications, and variations will be apparent to those skilled in the art. Interpretations of terms and/or wordings used in description and claims should not be limited to common or literal meanings.

The bandwidth of the phase locked loop can be limited in a related art fractional-N phase locked loop of a sigma-delta type so as to reduce a spur or a quantization noise. More specifically, while the sigma-delta frequency synthesizer allows a fine frequency adjustment by a unit of few Hz even when the reference frequency Fref applied externally is higher than tens of Mhz, the bandwidth of the phase locked loop cannot be widened unconditionally because of the quantization noise that is a characteristic of the sigma-delta frequency synthesizer. Generally, the bandwidth of the phase locked loop is selected from one thousandth of the reference frequency. Therefore, the phase locked loop has the bandwidth of tens of KHz when the reference frequency is tens of MHz, thereby acting as a factor for increasing the phase noise of the phase locked loop.

In addition, the phase noise of the related art fractional-N phase locked loop of the sigma-delta type increases as an operating frequency is increased. Therefore, a large amount of noises is generated when the sigma-delta type phase locked loop is used to obtain the high frequency of hundreds of MHz or few Ghz.

FIG. 2is a diagram illustrating a first embodiment of a frequency synthesizer in accordance with the application. As shown inFIG. 2, a frequency synthesizer can include a reference frequency oscillator20, an integer-N phase locked loop30, a fractional-N phase locked loop40and a frequency adder50.

The reference frequency oscillator20provides a signal having a reference frequency Fref to the integer-N phase locked loop30and the fractional-N phase locked loop40. The reference frequency oscillator20, for instance, may be a crystal oscillator. However, embodiments are not intended to be so limited.

The integer-N phase locked loop30can receive the signal having the reference frequency Fref and output a signal having a first output frequency Fout1corresponding to integer times the reference frequency Fref Various types of the integer-N phase locked loop30such as a direct division type, a prescaler type, a pulse swallow type or the like may be used as the integer-N phase locked loop30.

The fractional-N phase locked loop40can receive the signal having the reference frequency Fref and output a signal having a second output frequency Fout2corresponding to a fractional multiple of the reference frequency Fref. Various types of the fractional-N phase locked loop40such as a current injection type, a sigma-delta modulation type or the like may be used as the fractional-N phase locked loop40.

The frequency adder50can receive an output signal of the integer-N phase locked loop30and an output signal of the fractional-N phase locked loop40to output a signal having a frequency corresponding to a sum of the first output frequency Fout1and the second output frequency Fout2, e.g., an output frequency Fout.

Since a phase noise of a final output signal, e.g., the signal having the output frequency Fout, can correspond to a sum of a phase noise of the signal having the first output frequency Fout1and a phase noise of the signal having the second output frequency Fout2. It is preferable that a design method be applied in order to reduce (e.g., or minimize) a channel spacing and/or the phase noise. One exemplary embodiment of a design method will now be described.

First, the integer-N phase locked loop (e.g., integer-N PLL30) can be designed to provide a highest frequency possible for a generation of a high frequency signal provided to a logic circuit (e.g., the frequency adder50). A degradation of the phase noise caused by the high frequency can be overcome by large bandwidth. The fractional-N phase locked loop (e.g., fractional-N PLL40) can have a relatively small bandwidth for a narrow channel spacing. The degradation of the phase noise generated can be reduced or overcome by reducing the second output frequency Fout2. Generally, when the frequency is reduced to one half, a RMS (root mean square) phase noise is reduced to one half.

FIG. 3is a diagram illustrating an embodiment of the integer-N phase locked loop30employed in the frequency synthesizer ofFIG. 2. InFIG. 3, the integer-N phase locked loop30is shown as a direct division type. However, embodiments of the application as not intended to be limited by such an exemplary disclosure.

Referring toFIG. 3, the integer-N phase locked loop30can include a phase detector31, a low pass filter32, a voltage controlled oscillator33and a frequency divider34. The phase detector31can output a voltage corresponding to a phase difference between the signal having the reference frequency Fref and a signal being outputted by the frequency divider34.

The low pass filter32can output a voltage where a high frequency component of the voltage being outputted from the phase detector31is reduced or removed therefrom. The voltage controlled oscillator33can output the signal having a frequency corresponding to the voltage being outputted from the low pass filter32, e.g., the first output frequency Fout1. The frequency divider34can output a signal having a frequency Fout1/N that corresponds to one Nth of the first output frequency Fout1.

The exemplary frequency synthesizer shown inFIG. 3therefore outputs the first output frequency Fout1that is N times the reference frequency Fref by having the above-described components.

FIG. 4is a diagram illustrating an embodiment of the fractional-N phase locked loop40employed in the frequency synthesizer ofFIG. 2. InFIG. 4, a fractional-N phase locked loop of sigma-delta modulation type is shown. However, embodiments of the application are not intended to be limited by such an exemplary disclosure.

As shown inFIG. 4, the fractional-N phase locked loop40can include a phase detector41, a low pass filter42, a voltage controlled oscillator43, a dual-modulus prescaler44and a sigma-delta modulator45. The phase detector41can output a voltage corresponding to a phase difference between the signal having the reference frequency Fref and a signal being outputted by the dual-modulus prescaler44.

The low pass filter42can output a voltage where a high frequency component of the voltage being outputted from the phase detector41is reduced or removed therefrom. The voltage controlled oscillator43can output the signal having a frequency corresponding to the voltage being outputted from the low pass filter42, e.g., the second output frequency Fout2.

The dual-modulus prescaler44can perform an operation where the second output frequency Fout2is divided by M for L1times, and an operation wherein the second output frequency Fout2is divided by (M+1) for L2times. Since the second output frequency Fout2has a value of Fref×M when the dual-modulus prescaler44successively divides the second output frequency Fout2by M and a value of Fref×(M+1) when the dual-modulus prescaler44successively divides the second output frequency Fout2by (M+1), the second output frequency Fout2has a value between Fref×M and Fref×(M+1) (e.g., the second output frequency Fout2is divided by M for L1times and divided by (M+1) for L2times). The second output frequency Fout2can be determined by a ratio L1:L2that is a ratio of the number of the divisions of the second output frequency Fout2by M and the number of the divisions of the second output frequency Fout2by (M+1) by the dual-modulus prescaler44.

For example, when the reference frequency Fref is 10 MHz and M is 10, and (L1, L2) is set to be (100, 0), the second output frequency Fout2is 100.0 MHz. When (L1, L2) is set to be (99, 1), the second output frequency Fout2is 100.1 MHz. When (L1, L2) is set to be (98, 2), the second output frequency Fout2is 100.2 MHz. When (L1, L2) is set to be (0, 100), the second output frequency Fout2is 110.0 MHz. However, the dual-modulus prescaler44can have a drawback of a fractional spurs whereby a periodic (L1+L2) phase error is generated in the output frequency.

The sigma-delta modulator45can generate a pseudorandom number b(t) to be transmitted to the dual-modulus prescaler44in order to reduce or remove the fractional spurs. The dual-modulus prescaler44can select one of M and (M+1) according to b(t), thereby reducing the fractional spurs.

FIGS. 5(a)-(b) are diagrams illustrating exemplary embodiments of a frequency adder that can be employed in the frequency synthesizer ofFIG. 2.FIG. 5(a) is a diagram illustrating an embodiment of the frequency adder50using a filter, andFIG. 5(b) is a diagram illustrating an embodiment of the frequency adder50using an image rejection.

As shown inFIG. 5(a), the frequency adder50can include a mixer51and a filter52. The mixer51can output a signal that is a combination (e.g., a product) of the signal having the first output frequency Fout1and the signal having the second output frequency Fout2. The output of the mixer51can include an unwanted frequency (e.g., Fout1−Fout2) as well as a desired frequency (e.g., Fout1+Fout2). The filter52can remove the unwanted frequency (e.g., Fout1−Fout2) from the frequencies being outputted from the mixer51and output the desired frequency (e.g., Fout1+Fout2), as the output frequency Fout.

As shown inFIG. 5(b), the frequency adder50can include a first mixer53, a second mixer54and an adder55. The first mixer53can output a signal that is combination (e.g., a product) of an in-phase signal Fout1(I) having the first output frequency Fout1and an in-phase signal Fout2(I) having the second output frequency Fout2. The second mixer54can output a signal that is a combination (e.g., a product) of a quadrature signal Fout1(Q) having the first output frequency Fout1and quadrature signal Fout2(Q) having the second output frequency Fout2.

The adder55can output a combination (e.g., a sum) of the outputs of the first mixer53and the second mixer54. An image component of the output of the first mixer53and an image component of the output of the second mixer54has a same magnitude and an inverted phase. Therefore, the image component can be reduced or removed from the adder55such that the adder55outputs the signal having a pure frequency (e.g., Fout1+Fout2), e.g., the output frequency Fout without the image component.

Embodiments of frequency synthesizer, in accordance with the application will be described using an example where an output frequency Fout is required to be varied by having the channel spacing of 100 KHz within a range between 2.0 GHz and 2.1 GHz.

The variable output frequency Fout having the channel spacing of 100 KHz may be obtained when the reference frequency Fref is set to be 10 MHz, N is set to range from 190 to 200, M is set to be 10, L1is set to range from 0 to 100 and L2is set to be (100−L1). Since the integer-N phase locked loop30can output the signal having the frequency corresponding to (Fref×N), the integer-N phase locked loop30outputs the signal having the first output frequency Fout1that varies by 10 MHz within a range between 1.90 GHz and 2.00 GHz. The fractional-N phase locked loop40can output the signal having the second output frequency Fout2that varies by Fref/(L1+L2) within a range between (Fref×M) and (Fref×(M+1)). In this example, the fractional-N phase locked loop40can output the signal having the second output frequency Fout2that varies by 100 KHz within a range between 100 MHz and 110 MHz. Therefore, the frequency adder50can output the output frequency Fout (e.g., Fout1+Fout2) that varies by 100 KHz within a range between 2.0 GHz and 2.1 GHz.

In this example, since the reference frequency Fref inputted to the integer-N phase locked loop30is 10 MHz, which is one hundred times larger than that of the related art, a bandwidth of the integer-N phase locked loop30may be set to be 1 MHz, which is one hundred times larger than that of the related art. Therefore, the phase noise of the integer-N phase locked loop according to embodiments may be reduced more than the related art. While the first output frequency Fout1that is outputted from the integer-N phase locked loop30can have the channel spacing of 10 MHz, the output frequency Fout of the frequency synthesizer since the second output frequency Fout2that is outputted from the fractional-N phase locked loop40can have the channel spacing of 100 KHz. Therefore, embodiments of a frequency synthesizer in accordance with the application can be advantageous over the related art in that the frequency synthesizer has a narrower channel spacing and/or a lower phase noise. Further, while the output of the fractional-N phase locked loop40may have the phase noise caused by the fractional spurs, the phase noise may be reduced by the fractional-N phase locked loop of the sigma-delta type shown inFIG. 4.

From above description, N, M, L1and L2should preferably be programmable in order to obtain sufficiently wide frequency range as well as the narrow channel spacing. Therefore, it is preferable that N, M, L1and L2are programmable. However, embodiments are not intended to be so limited.

In addition, since a fine frequency adjustment is possible for the fractional-N phase locked loop40, it is preferable that the channel spacing of the second output frequency Fout2being outputted from the fractional-N phase locked loop40is smaller than that of the first output frequency Fout1being outputted from the integer-N phase locked loop30. Moreover, since the integer-N phase locked loop30may simply generate the high frequency, it is preferable that the first output frequency Fout1being outputted from the integer-N phase locked loop30is higher than the second output frequency Fout2being outputted from the fractional-N phase locked loop40.

FIG. 6is a diagram illustrating a second embodiment of a frequency synthesizer in accordance with the application. As shown inFIG. 6, the frequency synthesizer can include a reference frequency oscillator20, an integer-N phase locked loop30, a fractional-N phase locked loop40′, a first L divider60I, a second L divider60Q, a first frequency adder50I and a second frequency adder50Q.

Since the reference frequency oscillator20and the integer-N phase locked loop30are similar to those ofFIG. 2, a detailed description thereof is omitted here.

The fractional-N phase locked loop40′ can receive a signal having a reference frequency Fref and output a signal having a second output frequency Fout2′ corresponding to a fractional multiple of the reference frequency Fref. Various types of the fractional-N phase locked loop40′ such as the current injection type, the sigma-delta modulation type or the like may be used as the fractional-N phase locked loop40′. The fractional-N phase locked loop40′ ofFIG. 6can output the signal having the second output frequency Fout2′ that is L times higher than that of the fractional-N phase locked loop40ofFIG. 2, and the second output frequency Fout2′ is lowered or divided L times by the L dividers60I and60Q for input to the frequency adders50I and50Q.

The first L divider60I and the second L divider60Q can output a signal having a third output frequency Fout3corresponding to one Lth of the second output frequency Fout2′. L can be a multiple of 2 such as 2, 4 and 6. _I or _Q after Fout3inFIG. 6represents that a phase difference can exist. For example, _I represents an in-phase signal, and _Q represents a quadrature signal. Therefore, a signal being outputted from the first L divider60I and a signal being outputted from the second L divider60Q preferably have a same frequency and have a phase difference of 90°. The phase difference may be obtained by differentiating a starting point of a period or the like. For example, the starting point of the period of the second L divider60Q can lag that of the first L divider60I by L/2.

The first frequency adder50I can receive an output signal of the integer-N phase locked loop30and an output signal of the first L divider60I to output a signal having a frequency corresponding to a sum of the first output frequency Fout1and the third output frequency Fout3, e.g., an output frequency Fout. The second frequency adder50Q can receive the output signal of the integer-N phase locked loop30and an output signal of the second L divider60Q to output the signal having a frequency corresponding to the sum of the first output frequency Fout1and the third output frequency Fout3, e.g., an output frequency Fout. Since the signal being outputted by the first frequency adder50I and the signal being outputted by the second frequency adder50Q preferably have the phase difference of 90°, _I and _Q are shown after reference numeral Fout. The frequency synthesizer in accordance with the second embodiment of the application can generate the I and Q signals simultaneously. For example, the first frequency adder50I or the second frequency adder50Q may be configured as shown inFIG. 5(a).

As described above, embodiments of methods and apparatus for frequency synthesis have various advantages. For example, embodiments of methods and frequency synthesizers according to the application can have a low phase noise characteristic while having the narrow channel spacing or overcome a correlation between the channel spacing and the phase noise.

To obtain a high frequency and narrow channel spacing using the related art integer-N phase locked loop, a deterioration due to the phase noise caused by the high frequency and a deterioration due to the phase noise because of the small bandwidth are generated. Similar disadvantages occur when obtaining the high frequency and the narrow channel spacing using the related art fractional-N phase locked loop. However, in accordance with embodiments of methods or apparatus for frequency synthesis according to the application, only the degradation of the phase noise caused by the high frequency is generated since the integer-N phase locked loop has the large bandwidth, and only the degradation of the phase noise caused by the small bandwidth is generated since the fractional-N phase locked loop has a low frequency. Therefore, phase noise of the frequency synthesizer of embodiments may have a smaller value than that of the related art integer-N phase locked loop and the related art fractional-N phase locked loop.

Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to affect such feature, structure, or characteristic in connection with other ones of the embodiments. Furthermore, for ease of understanding, certain method procedures may have been delineated as separate procedures; however, these separately delineated procedures should not be construed as necessarily order dependent in their performance. That is, some procedures may be able to be performed in an alternative ordering, simultaneously, etc.