Array substrate for liquid crystal display and fabrication method thereof

Disclosed is an array substrate for a liquid crystal display, including: a substrate; a gate line and a thin film transistor having a gate electrode, a source electrode, a drain electrode and an active layer formed over the substrate; an interlayer insulating layer formed on the thin film transistor; a first gate redundancy line formed on the interlayer insulating layer, and connected electrically with one of the gate electrode and the gate line through a first gate contact hole and formed of the same material as the source and drain electrodes; a passivation layer provided on the first gate redundancy line and the interlayer insulating layer; and a pixel electrode electrically connected with the drain electrode through the drain contact hole formed in the passivation layer.

This application claims the benefit of Korean Patent Application No. 2003-40394, filed on Jun. 20, 2003, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display, and more particularly, to an array substrate for a liquid crystal display and a fabrication method thereof.

2. Description of the Related Art

Recently, as modern society quickly changes in an information-oriented society, flat panel displays having many advantages such as slimness, light weight, and low power consumption are widely used. Particularly, among the flat panel displays, liquid crystal displays (LCD) having superior color reproduction have been developed.

As known in the art, a liquid crystal display is formed by the steps of: arranging two substrates each having electrode formed on one surface thereof to face with each other; and injecting liquid crystal material between two substrates. In the liquid crystal display, images are displayed by rearranging liquid crystal molecules by an electric field generated by a voltage applied to two electrodes to vary light transmittance.

In the above liquid crystal display, a lower substrate is an array substrate including a thin film transistor for applying a signal to a pixel electrode and is formed by repeating a metallic film and insulating film forming step and a lithography step. Further, an upper substrate is a substrate including a color filter layer of three colors of red, green and blue sequentially arranged and is manufactured using a pigment dispersion method, a dyeing method, an electro deposition method, etc.

Generally, an active layer of the thin film transistor is formed of amorphous silicon (a-Si:H). This is because the amorphous silicon is easily fabricated in a large-sized structure, thereby resulting in a higher productivity, and the amorphous silicon can be deposited on the substrate at a lower temperature below 350° C., thereby permitting use of a lower price insulating substrate.

However, because a hydrogenated amorphous silicon is in disordered atomic arrangement due to a weak Si—Si bond and a dangling bond, when light is radiated on or an electric field is applied to the hydrogenated amorphous silicon, it is changed to be in a meta-stable state, so that when the amorphous silicon is used in the thin film transistor, questionable stability results.

In particular, the amorphous silicon has a disadvantage in which deterioration is caused by light radiation. Further, because a driving unit for a display pixel has an electric characteristic (low field effect mobility:0.1˜1.0 cm2/V·s) that causes the reliability to deteriorate, the amorphous silicon is difficult to use in a driving circuit.

Further, if a liquid crystal panel for the liquid crystal display increases in resolution, the pad pitch external to the substrate is narrowed for connecting a gate line and a data line of a thin film transistor substrate with a tape carrier package (TCP), so that TCP bonding itself becomes difficult.

However, because polycrystalline silicon has a field effect mobility larger than the amorphous silicon, the driving circuit can be formed directly on the substrate, which decreases the manufacturing cost for a driving integrated circuit and simplifies the mounting structure of the driving IC.

Further, the above polycrystalline silicon has the advantages that the field effect mobility is one hundred to two hundreds times larger than that of the amorphous silicon, the response speed is fast, and the stability is excellent with respect to temperature and light. Furthermore, the polycrystalline silicon has the advantage that the driving circuit can be formed on the same substrate.

Various fabrication methods of polycrystalline silicon having the above advantages are known in the art. Typically, to form polycrystalline silicon, amorphous silicon is deposited through a plasma enhanced chemical vapor deposition or a low pressure chemical vapor deposition, and the deposited amorphous silicon is again crystallized.

As one method of forming polycrystalline silicon uses a laser annealing method in which the substrate is heated to a temperature of about 250° C. while an excimer laser radiates a thin amorphous silicon film to form the polycrystalline silicon. Another crystallizing method is a metal induced crystallization (MIC) method in which a metal deposited on the amorphous silicon is used as a seed to form the polycrystalline silicon. Another crystallizing method is a solid phase crystallization (SPC) method in which the amorphous silicon is heated for a long time at a high temperature to form the polycrystalline silicon, etc.

On the other hand, in order to provide a reliable thin film transistor, it is important to form a larger crystalline grain. One method for solving this is a single crystalline forming method (Robert S. Sposilli, M. A. Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956˜957, 1997) using a sequential lateral solidification (SLS) crystallization technique that uses the fact that the silicon crystalline grain grows up from a boundary surface between a liquid-phase silicon and a solid-phase silicon in a vertical direction.

In the SLS crystallization technique, the magnitude of the laser energy, and the range and the translation distance of the laser beam are properly controlled such that the silicon crystalline grain can be laterally grown-up by a predetermined length to allow the amorphous silicon to be crystallized as a single crystalline silicon.

Hereinafter, with reference to the attached drawings, a conventional array substrate and fabrication method thereof will be described including a polycrystalline silicon thin film transistor.

FIGS. 1A and 1Bare sectional views respectively illustrating conventional top-gate type thin film transistors of a pixel and a driving circuit, and the pixel and the driving circuit all employ a top-gate type thin film transistor in which a gate electrode is positioned over a semiconductor layer.

First, in a pixel thin film transistor (I) ofFIG. 1A, a buffer layer114is formed on a whole insulating substrate100, a semiconductor layer116is formed on the buffer layer114, and then a gate insulating layer118and a gate electrode120are sequentially formed on a central portion of the semiconductor layer116.

Further, an interlayer insulating layer124having first and second semiconductor layer contact holes122aand122bformed therein is formed on the whole resultant substrate having the gate electrode120. Additionally, source and drain electrodes126and128are formed to connect with the semiconductor layer116through the first and second semiconductor layer contact holes122aand122b.

Furthermore, a passivation layer132having a drain contact hole130formed therein is formed on the resultant substrate having the source and drain electrodes126and128, and a pixel electrode is formed on the passivation layer to connect with the drain electrode128through the drain contact hole130.

The semiconductor layer116includes an active layer116aformed in a region corresponding to the gate insulating layer118, and an N+doped N-type impurity layer116cformed in a contact region with the source and drain electrodes126and128. In a junction portion between the source and drain electrodes126,128between the active layer116aand the N-type impurity layer116cand the gate electrode120, a lightly doped drain (LDD) layer116bis located.

The LDD layer116bis doped with a lower concentration for the purpose of dispersing hot carriers so as to prevent a leakage current from increasing and to minimize a current loss in an ON state.

InFIG. 1B, a complimentary metal-oxide-silicon (CMOS) thin film transistor includes a thin film transistor (II) having an N doped channel and a thin film transistor (III) having a P doped channel, and for description convenience, the same elements are numbered in a sequence of II and III.

As shown inFIG. 1B, an N-type semiconductor layer140and a P-type semiconductor layer142are formed on the insulating substrate100having the buffer layer114formed. Herein, the gate insulating layers144aand144band the gate electrodes146aand146bare respectively formed on the N-type and P-type semiconductor layers140and142. Additionally, the interlayer insulating layer124having the semiconductor layer contact holes147a,147b,147cand147dformed therein is formed on the whole resultant substrate having the gate electrodes146aand146b.

Source and drain electrodes150a,152a,150band152bare respectively formed on the interlayer insulating layer124to connect with the N-type and P-type semiconductor layers140and142through the semiconductor layer contact holes147a,147b,147cand147d, and the passivation layer132is formed on the whole resultant substrate having the source and drain electrodes150a,152a,150band152b.

The N-type semiconductor layer140includes, as in the semiconductor layer116ofFIG. 1A, an active layer140aformed in a contact region with the gate insulating layer144a, an N-type impurity layer140cformed in a region including a contact region with the source and drain electrodes150aand152a, and an LDD layer140bbetween the active layer140aand N-type impurity layer140c.

Hereinafter, a conventional fabrication method will be described for a general thin film transistor of the pixel and a CMOS thin film transistor of the driving circuit.

FIG. 2is a process flow chart illustrating a conventional fabrication method of a top-gate type thin film transistor ofFIGS. 1A and 1B, and this fabrication method includes a photolithography step (hereinafter, “masking process”) using a photoresist (PR).

First, the insulating substrate is prepared, and the buffer layer is formed on the insulating substrate S100. For the material of the buffer layer, an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx) may be used.

Next, the active layer is formed on the buffer layer S11. In this step, the amorphous silicon (a-Si) layer is deposited to have a thickness of about 550 Å on the resultant substrate having the buffer layer formed, and then a dehydrogenation process is performed. Additionally, through a crystallization process, a crystalline silicon layer is formed such as a polycrystalline silicon layer or a single crystalline silicon layer, and then the crystalline silicon layer is used to form the active layer by a first masking process.

After that, the gate insulating layer and the gate electrode are formed S120. A silicon nitride film with a thickness of about 1000 Å and a molybdenum (Mo) film with a thickness of about 2000 Å are sequentially deposited on the resultant substrate having the active layer formed, and then through a second masking process, the gate insulating layer and the gate electrode are formed.

Next, a step is performed for completing the N-type semiconductor layer. That is, the N−doped LDD layer is formed on the resultant substrate having the gate electrode, the gate insulating layer is formed, and then through a third masking process, the N+doped N-type impurity layer is formed S130.

Next, the P+ doped P-type impurity layer is formed on the resultant substrate having the N-type impurity layer formed therein, through a fourth masking process S140.

Further, a step is performed for forming the interlayer insulating layer S150. The inorganic insulating film with a thickness of about 7000 Å may be silicon nitride or silicon oxide and is deposited on the resultant substrate having the P-type impurity layer formed, and then through a fifth masking process, the interlayer insulating layer having the semiconductor layer contact hole is formed.

Next, molybdenum (Mo) with a thickness of about 500 Å and aluminum neodymium (AlNd) with a thickness of about 3000 Å are sequentially deposited on the resultant substrate with the interlayer insulating layer, and then through a sixth masking process, a blanket etching is performed to form the source and drain electrode to connect with the impurity layer through the semiconductor layer contact hole S160.

Further, the silicon nitride film with a thickness of about 4000 Å is deposited to form the passivation layer on the resultant substrate with the source and drain electrodes, and then a hydrogenation heat-treatment process is performed. The hydrogenation heat-treatment process may be performed once using nitrogen (N2) gas at a temperature of change about 380° C.

Next, through a seventh masking process, the drain contact hole is formed in the passivation layer S170.

Finally, the pixel electrode is formed on the passivation layer S180. In this step, a layer of Indium Tin Oxide (ITO) about 500 Å thick is deposited on the resultant substrate having the passivation layer formed, and then through an eighth masking process, the pixel electrode is formed to connect with the drain electrode through the drain contact hole.

One problem as the liquid crystal display increases size and increases in resolution, the length of the lines lengthen and a width thereof are narrowed thereby resulting in increasing a probability of a signal delay.

Accordingly, there remains a need to decrease the resistance of the lines using a low resistance material.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a liquid crystal display and a fabrication method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide an array substrate for a liquid crystal display and a fabrication method thereof in which a gate redundancy line is formed on a gate electrode and/or a gate line in a thin film transistor such that the resistance of the gate electrode and/or the gate line is decreased, and the gate electrode and gate line are prevented from being disconnected thereby being applicable to a large area liquid crystal display panel resulting in a better quality low resistance line that prevents signal delay.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided an array substrate for a liquid crystal display, the array substrate including: a substrate; a gate line and a thin film transistor having a gate electrode, a source electrode, a drain electrode and an active layer formed over the substrate; an interlayer insulating layer formed on the thin film transistor; a first gate redundancy line formed on the interlayer insulating layer, and connected electrically with one of the gate electrode and the gate line through a first gate contact hole and formed of the same material as the source and drain electrodes; a passivation layer provided on the first gate redundancy line and the interlayer insulating layer; and a pixel electrode electrically connected with the drain electrode through the drain contact hole formed in the passivation layer.

In another aspect of the present invention, there is provided an array substrate for a liquid crystal display, including: a substrate; a gate line and a thin film transistor having a gate electrode, a source electrode, a drain electrode and an active layer formed on the substrate; an interlayer insulating layer formed on the thin film transistor; a passivation layer formed on the interlayer insulating layer; a pixel electrode electrically connected with the drain electrode through a drain contact hole formed in the passivation layer; and a gate redundancy line formed on the passivation layer, and connected electrically with one of the gate electrode and the gate line through a gate contact hole and formed of the same material as the pixel electrode.

In another aspect of the present invention, there is provided a method for fabricating an array substrate for a liquid crystal display, the method including the steps of: forming a gate line and a gate electrode on a substrate; forming an interlayer insulating layer on the gate line and the gate electrode; forming a first gate redundancy line on the interlayer insulating layer and electrically connected with one of the gate electrode and the gate line through a first gate contact hole; forming a passivation layer on the first gate redundancy line and the interlayer insulating layer; and forming a drain contact hole in the passivation layer, and forming a pixel electrode connected electrically with the drain electrode through the drain contact hole.

In another aspect of the present invention, there is provided a method for fabricating an array substrate for a liquid crystal display, the method including the steps of: forming a gate line and a gate electrode on a substrate; forming an interlayer insulating layer on the gate line and the gate electrode; forming a passivation layer on the interlayer insulating layer; and forming a gate contact hole in the passivation layer, and forming a gate redundancy line connected electrically with one of the gate electrode and the gate line through the gate contact hole.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to embodiments of the present invention, example of which are illustrated in the accompanying drawings.

FIG. 3is a sectional view respectively illustrating top-gate type thin film transistors of a pixel and a driving circuit according to a first embodiment of the present invention. InFIG. 3, the pixel and the driving circuit all have a top-gate type thin film transistor in which a gate electrode is positioned on a semiconductor layer.

First, as shown inFIG. 3, in a pixel thin film transistor (IV), a buffer layer214is formed on a whole insulating substrate200, a semiconductor layer216is formed on the buffer layer214, and then a gate insulating layer218and a gate electrode220are sequentially formed on a central portion of the semiconductor layer216.

Further, an interlayer insulating layer224having first and second semiconductor layer contact holes222aand222band a gate contact hole239formed therein is formed on the resultant substrate to cover the gate electrode220. Additionally, source and drain electrodes226and228are formed to connect with the semiconductor layer216through the first and second semiconductor layer contact holes222aand222b.

Furthermore, a gate redundancy line229is formed to connect with the gate electrode220through the gate contact hole239formed in the interlayer insulating layer224. The gate redundancy line229is formed at the same time that the source and drain electrodes226and228are formed and with the same material.

Additionally, a passivation layer232having a drain contact hole230is formed on the resultant substrate having the source and drain electrodes226and228and the gate redundancy line229, and a pixel electrode234is formed on the passivation layer232to connect with the drain electrode228through the drain contact hole230.

The semiconductor layer216includes an active layer216aformed in a region corresponding to the gate insulating layer218, and an N+doped N-type impurity layer216cformed in a contact region with the source and drain electrodes226and228. In a junction portion between the source and drain electrodes226and228between the active layer216aand the N-type impurity layer216cand the gate electrode220, a lightly doped drain (LDD) layer216bis formed.

The LDD layer216bis doped with a lower concentration for the purpose of dispersing hot carriers so as to prevent a leakage current from increasing and to minimize a current loss in an ON state.

Also, as shown inFIG. 3, in the array substrate for the liquid crystal display according to the present invention, the CMOS thin film transistor of the driving circuit includes a thin film transistor (V) having an N doped channel and a thin film transistor (VI) having a P doped channel.

As illustrated, an N-type semiconductor layer240and a P-type semiconductor layer242are formed on the insulating substrate200having the buffer layer214formed. The gate insulating layers244aand244band the gate electrodes246aand246bare formed on the N-type and P-type semiconductor layers240and242. Additionally, the interlayer insulating layer224having the semiconductor layer contact holes247a,247b,247c, and247dand the gate contact holes239aand239bis formed on the whole resultant substrate having the gate electrodes246aand246b.

Source and drain electrodes250a,252a,250band252bare respectively formed on the interlayer insulating layer224to connect with the N-type and P-type semiconductor layers240and242through the semiconductor layer contact holes247a,247b,247c, and247d. Additionally, gate redundancy lines249aand249bare formed to connect with the gate electrodes246aand246bthrough the gate contact holes239aand239b. Also, the passivation layer232is formed on the whole resultant substrate having the source and drain electrodes250a,252a,250band252band the gate redundancy lines249aand249b.

Herein, as in the semiconductor layer216of the pixel the N-type semiconductor layer240includes an active layer240aformed in a contact region with the gate insulating layer244a, an N-type impurity layer240cformed in a region including a contact region with the source and drain electrodes250aand252a, and an LDD layer240bbetween the active layer240aand N-type impurity layer240c.

Also, because the P-type semiconductor layer242uses a positively charged carrier, it has less carrier deterioration and a smaller leakage current than those of the N-type thin film transistor. Accordingly, the P-type semiconductor layer242is constructed to include a contact region with the gate insulating layer244bas the active layer242aand an external region of the active layer242aas the P-type impurity layer242bwithout an individual LDD layer.

In the above description, the thin film transistor having an LDD layer formed is described, but in the thin film transistor also may be formed in an offset structure not the LDD layer.

Also, in the above description, it is described that the gate redundancy line is formed on the gate electrode, but the gate redundancy line may be formed on the gate line as well as the gate electrode.

Hereinafter, for an array substrate for the liquid crystal display according to the present invention, a fabrication method of the pixel thin film transistor will be described in detail.

FIGS. 4A to 4Dare views illustrating a sequence of the fabrication method of the top-gate type thin film transistor according to a first embodiment of the present invention. This fabrication method includes a photolithography process using a photoresist (PR).

First, as shown inFIG. 4A, the buffer layer214is formed on the insulating substrate200. The buffer layer214material may be an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx).

Next, the semiconductor layer216is formed on the buffer layer214. In this step, the amorphous silicon (a-Si) is deposited with a thickness of about 550 Å on the resultant substrate having the buffer layer214formed, and then a dehydrogenation process is performed. Additionally, a crystallization process forms a crystalline silicon layer such as a polycrystalline silicon layer or a single crystalline silicon layer, and then the crystalline silicon layer is used to form the semiconductor layer216by a first masking process.

Further, the gate insulating layer218and the gate electrode220are sequentially formed.

A silicon nitride film or a silicon oxide film with a thickness of about 1000 Å is sequentially deposited to form the gate insulating layer218on the resultant substrate having the semiconductor layer216. Then, molybdenum (Mo) with a thickness of about 2000 Å is deposited and, the gate electrode220is formed by a second masking process.

Next, a step is performed for completing the N-type semiconductor layer. The N−doped LDD layer216bis formed on the resultant substrate having the gate electrode220and the gate insulating layer218, and then through a third masking process, the N+doped N-type impurity layer216cis formed.

Next, the P+ doped P-type impurity layer (not shown in the drawing, but used to form the driving circuit thin film transistor) is formed on the resultant substrate having the N-type impurity layer216cformed therein.

Further, a step is performed for forming the interlayer insulating layer224. The inorganic insulating film with a thickness of about 7000 Å may be silicon nitride or silicon oxide and is deposited on the resultant substrate.

Next, as shown inFIG. 4B, the semiconductor layer contact holes222aand222band the gate contact hole239are formed in the interlayer insulating layer224using a fifth masking process.

Further, aluminum neodymium (AlNd) with a thickness of about 3000 Å and molybdenum (Mo) with a thickness of about 500 Å are deposited to form a metallic layer on the resultant substrate having the interlayer insulating layer224including the semiconductor layer contact holes222aand222band the gate contact hole239. The metallic layer also may be formed to include Mo/Al/Mo, and also instead of aluminum, an aluminum alloy may be used.

Next, a blanket etching process is performed by a sixth masking process. Accordingly, as shown inFIG. 4C, the source and drain electrodes226and228are formed to connect with the impurity layer through the semiconductor layer contact holes222aand222b. Additionally, the gate redundancy line229is formed of the same material as the source and drain electrodes226and228, to connect with the gate electrode220through the gate contact hole239.

Additionally, as shown inFIG. 4D, a silicon nitride film or silicon oxide film about 4000 Å thick is deposited to form the passivation layer232on the resultant substrate having the source and drain electrodes226and228and the gate redundancy line229formed.

Next, the hydrogenation heat-treatment step is performed. The hydrogenation heat-treatment step may be performed once at a temperature of about 380° C. using nitrogen (N2) gas.

Next, through a seventh masking process, the drain contact hole230is formed in the passivation layer232, and the pixel electrode234is formed on the passivation layer232. In this step, ITO with a thickness of about 500 Å is deposited on the resultant substrate having the passivation layer232formed, by an eighth masking process, the pixel electrode234is formed to connect with the drain electrode228through the drain contact hole230.

Accordingly, the present invention may, by the gate redundancy line, lower the resistance of the gate electrode and the gate line and prevent the gate electrode and the gate line from being disconnected, thereby improving response speed and providing good image quality in the liquid crystal display.

FIG. 5is a sectional view respectively illustrating the pixel thin film transistor (VII) and a driving circuit CMOS thin film transistor (VIII) and (IX) according to a second embodiment of the present invention. InFIG. 5, a pixel and a driving circuit all have a top-gate type thin film transistor in which a gate electrode is positioned on a semiconductor layer.

First, as shown inFIG. 5, in a pixel thin film transistor (VII), a buffer layer314is formed on a whole insulating substrate300, a semiconductor layer316is formed on the buffer layer314, and then a gate insulating layer318and a gate electrode320are sequentially formed on a central portion of the semiconductor layer316.

Further, an interlayer insulating layer324having first and second semiconductor layer contact holes322aand322bformed therein is formed on the resultant substrate having the gate electrode320. Additionally, source and drain electrodes326and328are formed to connect with the semiconductor layer316through the first and second semiconductor layer contact holes322aand322b.

Additionally, a passivation layer332having the drain contact hole330and the gate contact hole339therein is formed on the resultant substrate having the source and drain electrodes326and328and the gate electrode320formed. Also, a pixel electrode334is formed on the passivation layer332to connect with the drain electrode328through the drain contact hole330.

The passivation layer332and the interlayer insulating layer324formed on the gate electrode320are etched to form the gate contact hole339.

At the same time that the pixel electrode334is formed on the passivation layer332, a gate redundancy line329is formed of the same material. Accordingly, the gate redundancy line329is in contact with the gate electrode320through the gate contact hole339.

The semiconductor layer316includes an active layer316ain a region corresponding to the gate insulating layer318, and an N+doped N-type impurity layer316cin a contact region with the source and drain electrodes326and328. In a junction portion between the source and drain electrodes326and328between the active layer316aand the N-type impurity layer316cand the gate electrode320, a lightly doped drain (LDD) layer316bis formed.

The LDD layer316bis doped with a lower concentration for the purpose of dispersing hot carriers so as to prevent a leakage current from increasing and to minimize a current loss in an ON state.

Also, as shown inFIG. 5, the CMOS thin film transistor of the driving circuit includes a thin film transistor (VIII) having an N doped channel and a thin film transistor (IX) having a P doped channel.

As illustrated, an N-type semiconductor layer340and a P-type semiconductor layer342are formed on the insulating substrate300having the buffer layer314formed. The gate insulating layers344aand344band the gate electrodes346aand346bare respectively formed on the N-type and P-type semiconductor layers340and342. Additionally, the interlayer insulating layer324having the semiconductor layer contact holes347a,347b,347cand347dformed therein is formed on the whole resultant substrate having the gate electrodes346aand346b.

Source and drain electrodes350a,352a,350b, and352bare respectively formed on the interlayer insulating layer324to respectively connect with the N-type and P-type semiconductor layers340and342through the semiconductor layer contact holes347a,347b,347c, and347d. Additionally, the passivation layer332is formed on the resultant substrate having the source and drain electrodes350a,352a,350b, and352b.

Herein, the gate contact holes339aand339bpassing through the passivation layer332and the interlayer insulating layer324are simultaneously formed when the drain contact hole330is formed in the pixel part thin film transistor. Also, when the pixel electrode334is formed in the pixel thin film transistor, the gate redundancy lines349aand349bare simultaneously formed of the same material.

As in the semiconductor layer316of the pixel part, the N-type semiconductor layer340includes an active layer340aformed in a contact region with the gate insulating layer344a, an N-type impurity layer340cformed in a region including a contact region with the source and drain electrodes350aand352a, and an LDD layer340bformed between the active layer340aand N-type impurity layer340c.

Also, because the P-type semiconductor layer342uses a positively charged carrier, it has less carrier deterioration and smaller leakage current than those of the N-type thin film transistor. Accordingly, the P-type semiconductor layer342is constructed to include a contact region with the gate insulating layer344bas the active layer342a, and an external region of the active layer342aas the P-type impurity layer342bwithout an individual LDD layer.

Hereinafter, for an array substrate for the liquid crystal display according to the present invention, the fabrication method of the pixel thin film transistor will be described in detail.

FIGS. 6A to 6Dare views illustrating a sequence of the fabrication method of the top-gate type pixel thin film transistor according to a second embodiment of the present invention. This fabrication method includes a photolithography process using a photoresist (PR).

First, as shown inFIG. 6A, the buffer layer314is formed on the insulating substrate300. The buffer layer material may be an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx).

Next, the semiconductor layer316is formed on the buffer layer314. In this step, the amorphous silicon (a-Si) layer is deposited with a thickness of about 550 Å on the resultant substrate having the buffer layer314formed, and then a dehydrogenation process is performed. Additionally, a crystallization process forms a crystalline silicon layer such as a polycrystalline silicon layer or a single crystalline silicon layer, and then the crystalline silicon layer is used to form the semiconductor layer316by a first masking process.

Further, the gate insulating layer318and the gate electrode320are sequentially formed.

A silicon nitride film or a silicon oxide film with a thickness of about 1000 Å is sequentially deposited to form the gate insulating layer318on the resultant substrate having the semiconductor layer316. Then molybdenum (Mo) with a thickness of about 2000 Å is deposited, and by a second masking process, the gate electrode320is formed.

Next, a step is performed for completing the N-type semiconductor layer316. The N−doped LDD layer316bis formed on the resultant substrate having the gate electrode320and the gate insulating layer318, and then through a third masking process, the N+doped N-type impurity layer316cis formed.

Next, the P+ doped P-type impurity layer (not shown) is formed on the resultant substrate having the N-type impurity layer316cformed therein.

Further, a step is performed for forming the interlayer insulating layer324. The inorganic insulating film with thickness of about 7000 Å may be silicon nitride or the silicon oxide and is deposited on the resultant substrate having the P-type impurity layer formed therein.

Next, as shown inFIG. 6B, the semiconductor layer contact holes322aand322bare formed in the interlayer insulating layer324using a fifth masking process.

Further, aluminum neodymium (AlNd) with a thickness of about 3000 Å and molybdenum (Mo) with a thickness of about 500 Å are deposited to form a metallic layer on the resultant substrate having the interlayer insulating layer324including the semiconductor layer contact holes322aand322b. The metallic layer also may be formed to include Mo/Al/Mo, and also instead of aluminum, an aluminum alloy may be used.

Next, a blanket etching process is performed by a sixth masking process. Accordingly, the source and drain electrodes326and328are formed to connect with the impurity layer316cthrough the semiconductor layer contact holes322aand322b.

Additionally, as shown inFIG. 6C, a silicon nitride film or silicon oxide film about 4000 Å thick is deposited to form the passivation layer332on the resultant substrate having the source and drain electrodes326and328formed.

Next, the hydrogenation heat-treatment step is performed. The hydrogenation heat-treatment step may be performed once at a temperature of about 380° C. using nitrogen (N2) gas.

Next, through a seventh masking process, the drain contact hole330and the gate contact hole339are formed in the passivation layer332. The drain contact hole330and the gate contact hole339are simultaneously formed using one mask. The gate contact hole339is formed by etching the passivation layer332and the interlayer insulating layer324to expose an upper surface of the gate electrode320.

Finally, as shown inFIG. 6D, the pixel electrode334is formed on the passivation layer332. In this step, ITO with a thickness of about 500 Å is deposited on the resultant substrate having the passivation layer332formed, and the pixel electrode334is formed to connect with the drain electrode328through the drain contact hole330by an eighth masking process.

When the pixel electrode334is formed in the pixel thin film transistor, the gate redundancy line329is simultaneously formed of the same material. Accordingly, the gate redundancy line329is in contact with the gate electrode320through the gate contact hole339.

As described above, the present invention can, by the gate redundancy line, prevent the gate electrode and the gate line from being disconnected to thereby provide a good quality of image in the liquid crystal display. Additionally, in the above description, it is illustrated that the gate redundancy line is formed on the gate electrode, however the gate redundancy line may be formed on the gate line as well as the gate electrode.

On the other hand, the present invention is also applicable to a liquid crystal display including a bottom-gate type thin film transistor as well as the liquid crystal display including the top-gate type thin film transistor. With reference to the attached drawing, an array substrate including the bottom-gate type thin film transistor using the poly crystalline silicon, and a fabrication method thereof according to the present invention will be described in another embodiment.

FIG. 7is a schematic plane view illustrating a portion of a pixel region in an array substrate including a bottom-gate type thin film transistor according to a third embodiment of the present invention.

As shown inFIG. 7, a matrix type of a pixel region is defined on a transparent substrate by a plurality of gate lines411arranged in parallel with one another and a plurality of data lines412arranged in parallel with one another substantially perpendicular to the gate lines411. Additionally, at a crossing point of two lines411and412, a thin film transistor including a semiconductor layer416, a gate electrode420, and source and drain electrodes426and428is provided. Also, a pixel electrode434is further provided to electrically connect to the thin film transistor.

The semiconductor layer416is electrically connected with the source and drain electrodes426and428by first and second semiconductor layer contact holes422aand422b. Further, the drain electrode428and the pixel electrode434are electrically connected with each other by the drain contact hole430.

Additionally, a gate redundancy line429is connected with the gate electrode420and the gate line411through the gate contact hole439. The gate redundancy line429is, at the time of forming the source and drain electrodes426and428, formed of the same material on the gate electrode420and the gate line411. The gate contact hole439formed on the gate electrode420is located in a region where the semiconductor layer416is not formed.

FIGS. 8A and 8Bare respective sectional views, taken along lines I-I′ and II-II′ ofFIG. 7, and schematically illustrate a portion of the pixel region in the array substrate including the bottom-gate type thin film transistor according to the present invention.

As shown inFIG. 8Ataken along line I-I′ ofFIG. 7, a buffer layer414is formed on a whole insulating substrate400, and a gate electrode420is formed on the buffer layer414. Further, a gate insulating layer418is formed covering the resultant substrate having the gate electrode420, and a semiconductor layer416is formed on the gate insulating layer418.

An interlayer insulating layer424is further formed having first and second semiconductor contact holes422aand422btherein and covering the resultant substrate having the semiconductor layer416. Also, source and drain electrodes426and428are formed to respectively connect with the semiconductor layer416through the first and second semiconductor layer contact holes422aand422b.

On the other hand, in the present invention, when the first and second semiconductor layer contact holes422aand422bare formed, the gate contact hole (not shown inFIG. 8A, but referring to a reference numeral439ofFIG. 8B) is simultaneously formed in the interlayer insulating layer424.

Additionally, a passivation layer432having the drain contact hole430therein is formed on the resultant substrate having the source and drain electrodes426and428. Also, the pixel electrode434is formed on the passivation layer432to connect with the drain electrode428through the drain contact hole430.

In the meanwhile, as shown inFIG. 8Btaken along line II-II′ ofFIG. 7, the buffer layer414is formed on the whole insulating substrate400, and the gate electrode420is formed on the buffer layer414.

Further, the gate insulating layer418is formed on the resultant substrate having the gate electrode420, and the interlayer insulating layer424is formed on the resultant substrate having the gate insulating layer418.

Additionally, the gate redundancy line429is formed to connect with the gate electrode420through the gate contact hole439formed in the interlayer insulating layer424and the gate insulating layer418. The gate redundancy line429is formed at the same time as the source and drain electrodes and of the same material.

Accordingly, the present invention can, by the gate redundancy line, lower the resistance of the gate electrode and the gate line and prevent the gate electrode and the gate line from being disconnected, thereby improving the response speed and image quality of the liquid crystal display. The fabrication method of the liquid crystal display including the bottom-gate type thin film transistor according to the present invention is similar with those of the first and second embodiments.

FIG. 9is a schematic plane view illustrating a portion of the pixel region in an array substrate including a bottom-gate type thin film transistor according to a fourth embodiment of the present invention.

As shown inFIG. 9, a matrix type of a pixel region is defined on a transparent substrate by a plurality of gate lines511arranged in parallel with one another and a plurality of data lines512arranged in parallel with one another substantially perpendicular to the gate line511. Additionally, at a crossing point of two lines511and512, a thin film transistor including a semiconductor layer516, a gate electrode520, and source and drain electrodes526and528is provided. Also, a pixel electrode534is further provided to electrically connect to the thin film transistor.

The source and drain electrodes526and528are electrically connected with the semiconductor layer516through first and second semiconductor layer contact holes522aand522b, and the drain electrode528and the pixel electrode534are electrically connected with each other by the drain contact hole530.

Additionally, a gate redundancy line529is connected with the gate electrode520and the gate line511through the gate contact hole539. The gate redundancy line529is, at the same time of forming the pixel electrode534, formed of the same material. The gate contact hole539formed on the gate electrode520is located in a region where the semiconductor layer516is not formed.

FIGS. 10A and 10Bare respective sectional views taken along lines III-III′ and IV-IV′ ofFIG. 9, and schematically illustrate a portion of a pixel region in an array substrate including the bottom-gate type thin film transistor according to the present invention.

As shown inFIG. 10Ataken along line III-III′ ofFIG. 9, a buffer layer514is formed on a whole insulating substrate500, and a gate electrode520is formed on the buffer layer514. Further, a gate insulating layer518is formed covering the resultant substrate having the gate electrode520, and a semiconductor layer516is formed on the gate insulating layer518.

An interlayer insulating layer524is further formed having first and second semiconductor contact holes522aand522band covering the resultant substrate having the semiconductor layer516. Also, source and drain electrodes526and528are formed to respectively connect with the semiconductor layer516through the first and second semiconductor layer contact holes522aand522b.

Additionally, a passivation layer532including the drain contact hole530is formed on the resultant substrate having the source and drain electrodes526and528. Also, the pixel electrode534is formed on the passivation layer532to connect with the drain electrode528through the drain contact hole530. The drain contact hole530and the gate contact hole (not shown inFIG. 10A, but referring to a reference numeral539ofFIG. 10B) are simultaneously formed using one mask.

Additionally, as shown inFIG. 10Btaken along line IV-IV′ ofFIG. 9, the buffer layer514is formed on the whole insulating substrate500, and the gate electrode520is formed on the buffer layer514.

Further, the gate insulating layer518is formed on the resultant substrate having the gate electrode520, and the interlayer insulating layer524is formed on the gate insulating layer518. Also, the passivation layer532is formed on the interlayer insulating layer524.

Additionally, the gate redundancy line529is formed to connect with the gate electrode520through the gate contact hole539formed passing through the passivation layer532, the interlayer insulating layer524and the gate insulating layer518. The gate redundancy line529is formed at the same time as the pixel electrode and formed of the same material.

Accordingly, the present invention can, by the gate redundancy line, prevent the gate electrode and the gate line from being disconnected thereby providing improved image quality in the liquid crystal display. The fabrication method of the liquid crystal display including the bottom-gate type thin film transistor according to the present invention is similar with those of the first and second embodiments.

Further, in the above-described embodiments according to the present invention, the method is described in which, when the source and drain electrodes are formed, the same material is used to form the gate redundancy line, or when the pixel electrode is formed, the same material is used to form the gate redundancy line. However, in the present invention, a dual gate redundancy line can be formed in which, when the source and drain electrodes are formed, a first gate redundancy line is formed, and when the pixel electrode is formed, a second gate redundancy line is overlapped to be formed on the first gate redundancy line.

Also, as shown inFIGS. 11A to 11D, in the array substrate for the liquid crystal display according to the present invention, various types of contact holes may be realized which are provided on the gate electrode and/or the gate line and on which the gate redundancy line is formed.

In other words, as shown inFIG. 11A, the contact hole639for connection of a gate redundancy line629may be formed only on a gate electrode620. Additionally, as shown inFIG. 11B, the contact hole639for connection of the gate redundancy line629may be formed only on the gate line611. Further, as shown inFIG. 11C, the contact hole639for connection of the gate redundancy line629may also be formed all on the gate electrode620and the gate line611.

Furthermore, as shown inFIG. 11D, the contact holes639for connection of the gate redundancy line629may be formed in not all gate redundancy line629forming regions, but only in partial regions.

The above various types of contact holes may be applied to all of the top-gate type liquid crystal displays and the bottom-gate type liquid crystal displays. Here, numerals612and626and628respectively designate the data line, the source electrode and the drain electrode.

As described above, in the present invention, when the source and drain electrode or the pixel electrode, the gate redundancy line is formed so as to further form a second metallic film on the gate metal. Accordingly, the present invention may lower the resistance of the gate electrode and the gate line and prevent the gate electrode and the gate line from being disconnected, thereby improving the response speed and the image quality of the liquid crystal display.

Further, the present invention has an advantage of, when the source and drain electrode or the pixel electrode are simultaneously formed, the gate redundancy line is formed thereby increasing a manufacturing efficiency by reducing the number of individual masking processes needed.