FABRICATION OF HIGH MOBILITY THIN FILM TRANSISTORS ON THIN AND FLEXIBLE CERAMIC SUBSTRATE

A method for making a thin film transistor device includes forming a semiconductor film on a flexible substrate comprising a thin ribbon of refractory material that does not degrade when heated to temperatures greater than about 750° C. The semiconductor film is crystallized by heating the semiconductor film and the flexible substrate to at least about 750° C. A dielectric material is deposited on the crystallized semiconductor film. Gate, source, and drain electrodes are formed on the dielectric material.

BACKGROUND

Various types of semiconductor devices have been developed. For example, thin film transistors may be utilized in display backplanes, sensor arrays, switching circuits for RF electronics, sensors, and various other technologies. Thin film transistors typically include conductive source drain pads connected with a semiconductor film or layer that is separated from a conductive gate by a dielectric film or layer. The semiconductor film may be characterized by its charge mobility.

Silicon is a known semiconductor film, and it may be deposited on insulator substrates using chemical vapor deposition, typically utilizing plasma-enhanced chemical vapor deposition (PECVD). The PECVD process produces amorphous silicon (a-Si), which has low electron mobility (e.g., less than 1 cm2·V−1·s−1), which is on the order of 1,000 times less than that of crystalline silicon. In order to increase mobility, a-Si may be crystallized into a polycrystalline film. Excimer laser annealing (ELA) is a known method for forming polycrystalline films on low strain point glasses. In ELA, a significant portion of the energy may be absorbed by the silicon rather than the substrate. The ELA process may alleviate thermal constraints associated with the substrate material, which permits the use of substrates with maximum allowable temperatures of less than 750° C. (e.g., display glass).

SUMMARY

An aspect of the present disclosure is a thin film transistor device that is fabricated utilizing a refractory substrate having an elevated temperature capability. A silicon film may be deposited on the substrate, and the whole substrate along with the silicon film may be heated to temperatures above about 750° C., thereby converting amorphous silicon into uniform, high-mobility polycrystalline silicon through the process of solid-phase crystallization. The substrate may comprise a ribbon ceramic substrate that does not degrade at higher temperatures (e.g., greater than about 750° C.), while providing desirable dielectric properties (e.g., a high dielectric constant), extremely low substrate thickness, and also providing the ability to process the substrate in a roll-to-roll process.

Another aspect of the present disclosure is a method of making a thin film transistor device. The method includes forming a semiconductor film (layer) on a thin flexible substrate. The flexible substrate preferably comprises a thin ribbon of refractory material (e.g., ceramic) that does not degrade when heated to temperatures greater than at least about 750° C. The semiconductor film is crystallized (annealed) by simultaneously heating the semiconductor film and the flexible substrate to at least about 750° C. in a kiln, oven, furnace, or other suitable apparatus. Annealing may be accomplished utilizing a convective heating process. A gate insulator dielectric is formed on the crystallized semiconductor film, and a gate electrode is formed on the gate insulator dielectric. Source and drain electrodes are formed such that the source and drain electrodes are in electrical contact with the crystallized semiconductor film. The electrical contact may comprise Ohmic contact or, alternatively, Schottky contact, as required for a particular device. The method may optionally include forming the source and/or drain electrodes on the crystallized semiconductor film whereby the source and drain electrodes are in electrically conductive contact with the crystallized semiconductor film.

The crystallized semiconductor film may have an electron mobility of at least about 10 cm2·V−1·s−1, and the semiconductor film may comprise silicon that is amorphous prior to crystallization. The semiconductor film is optionally deposited on the flexible substrate utilizing plasma-enhanced chemical vapor deposition.

A plurality of the thin film transistor devices may optionally be formed on an elongated continuous substrate that extends through at least one process station, wherein the at least one process station is selected from the group consisting of a plasma-enhanced chemical vapor deposition station; a heating (annealing) station comprising at least one of a kiln, an oven, or a furnace; a station for forming the gate insulator dielectric on the crystallized semiconductor film, and a station that forms at least one of the gate electrode, the source electrode, and the drain electrode.

The elongated continuous substrate may optionally include opposite end portions, and the method may optionally include forming rolls including the opposite end portions. The elongated continuous substrate may be moved through at least one station in a roll-to-roll process that includes forming spaced apart first and second rolls using the opposite end portions.

The refractory material of the flexible substrate is optionally selected from the group consisting of flexible alumina ceramic and flexible yttrium-stabilized zirconia.

The flexible substrate optionally has a thickness of about 5 μm to about 100 μm, and the flexible substrate may optionally have a thickness of about 20 μm.

The flexible substrate optionally has a width of about 200 mm to about 400 mm when the semiconductor film is formed on the flexible substrate.

The process optionally includes forming through substrate conductive vias that extend through the flexible substrate, or vias that extend through a passivating insulating layer that extends over at least one of the gate electrode, the source electrode, and the drain electrode.

Optionally, at least one of the source electrode and the gate electrode are in Schottky or Ohmic contact with the crystallized semiconductor film.

The method optionally includes doping the crystallized semiconductor material to form source, drain, and channel regions. The source, drain, and channel electrodes may be formed adjacent the source, drain, and channel regions, respectively. The method optionally includes forming a pair of gate electrodes adjacent to the channel region.

The semiconductor film optionally comprises a material selected from the group consisting of Ge, SiGe, CdTe, CIGS, Epitaxial GaAs, GaN, and silicon.

The method optionally includes patterning the semiconductor film to form a plurality of electrically isolated regions (islands) of semiconductor film disposed on the flexible substrate, whereby a plurality of thin film transistor devices can be formed on a single piece of the flexible substrate.

The method optionally includes depositing a first layer of material on the flexible substrate before forming the semiconductor film on the substrate, wherein the first layer comprises a material selected from the group consisting of smoothening materials having reduced surface roughness relative to a surface roughness of the flexible substrate, barrier materials that prevent migration of molecules from the flexible substrate into the semiconductor film, and materials that provide a barrier and reduced surface roughness.

Another aspect of the present disclosure is a method for making a display panel comprising a plurality of thin film transistor devices. The method includes forming a semiconductor film on a flexible substrate, wherein the flexible substrate comprises a thin ribbon of refractory material. The semiconductor film is patterned to form a plurality of discrete islands of the semiconductor film that are disposed on the flexible substrate. The islands are preferably electrically separated from one another by gaps that may be filled with a dielectric material. The method further includes crystallizing the semiconductor film by convectively heating the semiconductor film and the flexible substrate. The semiconductor film is doped after crystallization. The method further includes forming a gate insulator dielectric on the crystallized semiconductor film of each discrete island. A gate electrode is formed on the gate insulator dielectric of each discrete island. A source electrode is formed, wherein the source electrode is electrically connected to the crystallized semiconductor film of each discrete island. The method further includes forming a drain electrode that is electrically connected to the crystallized semiconductor film of each discrete island. The method further includes operably connecting the thin film transistor devices to form a plurality of sub-pixels. The crystallized semiconductor film may, optionally, have an electron mobility of at least about 10 cm2·V−1·s−1.

A plurality of the thin film transistor devices may, optionally, be formed on an elongated continuous substrate that extends through at least one station, wherein the at least one station is selected from the group consisting of a plasma-enhanced chemical vapor deposition station, a convective heating station, a station for forming the gate insulator dielectric on the crystallized semiconductor film, and a station that forms at least one of the gate electrode, the source electrode, and the drain electrode.

Another aspect of the present disclosure is a method for making a thin film transistor device. The method includes forming a semiconductor film on a flexible substrate, wherein the flexible substrate comprises a thin ribbon of refractory material. The method further includes depositing a smoothening film onto the flexible substrate to provide reduced surface roughness. The semiconductor film is crystallized by convectively heating the semiconductor film and the flexible substrate to at least about 750° C. in a kiln, oven, or furnace. The method further includes forming a gate insulator dielectric on the crystallized semiconductor film, forming a gate electrode on the gate insulator dielectric, and forming a source electrode that is electrically connected to the crystallized semiconductor film. The method further includes forming a drain electrode that is electrically connected to the crystallized semiconductor film. The crystallized semiconductor film optionally comprises silicon having a mobility of at least about 10 cm2·V−1·s−1.

A plurality of the thin film transistor devices are optionally formed on an elongated continuous substrate in a roll-to-roll process.

DETAILED DESCRIPTION

Reference will now be made in detail to the present preferred embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

With reference toFIG.1, a thin film transistor device1according to an aspect of the present disclosure includes a substrate2A which may comprise a ceramic substrate material2, an optional surface smoothing layer3, and/or an optional diffusion barrier layer4. As discussed in more detail below, the ceramic substrate material2may initially be in the form of an elongated thin flexible ribbon ceramic material. For example, substrate2may comprise a Corning® Alumina Ribbon Ceramic, or a Corning® Zirconia Ribbon Ceramic. Substrate2may have a thickness of about 5 μm-100 μm, with a typical thickness of about 20 μm. Substrate2may have an initial width of about 200-400 μm, and may initially form a roll. It will be understood, however, that the present disclosure is not limited to these materials or dimensions.

Device1further includes a polycrystalline silicon semiconductor material5, a source electrode6, a drain electrode7, and a gate electrode8. Source electrode6, drain electrode7, and gate electrode8may comprise metal (e.g., copper, silver, etc.) or other electrically conductive material. An insulating dielectric layer9may be formed from an oxide material to electrically separate (isolate) the gate8from the source and drain electrodes6and7, and the channel region10of silicon semiconductor material5. Additional dielectric material9A and9B may be disposed between electrodes6,7, and substrate2A. Dielectric material9,9A, and9B may comprise SiNx, SiO2(or both), or other suitable material. The silicon semiconductor material5may include highly doped regions11and12that are in electrical contact (Ohmic or Schottky contact) with source and drain electrodes6and7. Silicon semiconductor material5may further include lightly doped drains (LLDs)11A and12A disposed adjacent channel region10. Channel region10may also be lightly doped. The regions11,11A,12,12A of silicon material5outside of channel region10may be p-doped, and the channel region10may be n-doped. It will be understood that the arrangement just described comprises an NMOS metal oxide semiconductor field effect transistor (MOSFET). However, the n- and p-type doping may be reversed to form a PMOS MOSFET. It will be understood that the amount and type of doping of semiconductor material5in the regions10,11,11A,12, and12A may vary depending on the requirements of a particular device.

With further reference toFIG.2, a process24of making device1generally includes steps24-33. Steps24-33generally correspond toFIGS.3-8. InFIG.2, the steps24-33may generally correspond to stations utilized in the fabrication of device1. As noted above, the ceramic substrate material2is initially in the form of a ribbon ceramic. The substrate material2may initially be in the form of a roll21, and the ceramic substrate material2may be utilized in a roll-to-roll process, whereby a plurality of the completed devices1are interconnected by a carrier layer to form a roll22. As noted above, the ribbon ceramic substrate2may comprise, but is not limited to, tape-cast thin and flexible alumina (e.g., Corning® Alumina Ribbon Ceramic) and yttrium-stabilized zirconia (e.g., Corning® Zirconia Ribbon Ceramic). As noted above, substrate2may have a thickness of about 5 μm-100 μm, with a typical thickness of about 20 μm. Substrate2may have an initial width of about 200-400 μm, and may initially form a roll.

Referring again toFIG.2, in a first step24of process20, an optional surface smoothening material3is deposited onto ribbon ceramic substrate2(see alsoFIG.3) to provide a reduced surface roughness. Smoothening material3is optional and may not be required if the surface of substrate2is sufficiently smooth and/or if the materials deposited on substrate2do not require a high smoothness. In general, the smoothening material3may be deposited onto ceramic substrate2utilizing a spin-coating process utilizing commercially available Spin-On-Glass (SOG) products. It will be understood that SOG materials are generally known, and may consist of short-chain Si-based molecules dissolved in an organic solvent solution. The SOG materials may be deposited on the surface of ceramic substrate2, and the solvent may then be evaporated. If the SOG material comprises Si—(OH)4molecules, a dense amorphous SixOyfilm can be formed due to a condensation reaction. Alternative formulations may incorporate phosphorus and boron, which result in either phospho-silicate glass (PSG) or boro-phospho-silicate glass (BPSG). Alternatively, the smoothening layer3may comprise a silica-based material (e.g., pure silica, or lightly doped silica) that forms amorphous coating on ceramic substrate material2. The coating3may be deposited in a liquid state, such as through spin, spray, or slot die coating, and subsequently cured/annealed to form a dense glass network. Alternatively, the smoothening layer3may comprise a silica-based (either pure silica, or lightly doped) amorphous coating on ceramic substrate material2. The coating3may be deposited in a liquid state, such as through spin, spray, or slot die coating, and subsequently cured/annealed to form a dense glass network. In general, the surface smoothening layer3may have an average surface roughness (Ra) of about 20-50 nm down to about 5 nm or less. This may be significantly less rough than the surface of substrate2prior to depositing smoothening layer3. For example, substrate2may have a surface roughness of about 20-30 nm on one side, and a surface roughness of about 50-60 nm on the opposite side.

Referring again toFIG.2, at step25a diffusion barrier layer or film4is optionally deposited onto the ceramic substrate material2or onto the smoothing layer3(see alsoFIG.4). The diffusion barrier layer4may comprise a suitable material such as silicon nitride or silicon oxide (silicon dioxide, SiO2). It will be understood that other suitable materials may also be utilized. The diffusion barrier layer4is utilized (if necessary) to prevent diffusion of undesirable elements (molecules) from ceramic substrate material2and/or surface smoothing layer3into the silicon material5. In general, the diffusion barrier layer4may be formed utilizing a suitable process such as plasma-enhanced chemical vapor deposition (PECVD). If the diffusion barrier layer4comprises silicon dioxide, the layer4may be deposited utilizing a chemical vapor deposition process, or a thermal oxidation process utilizing a high temperature furnace with an oxygen source (e.g., gas or vapor).

It will be understood, however, that the optional diffusion barrier film4may not be required in all cases, and the diffusion barrier layer4is not necessarily limited to the examples and corresponding processes described above. Rather, the diffusion barrier layer4may comprise virtually any suitable material that is deposited utilizing virtually any suitable process. Also, if smoothening layer3has sufficient barrier properties, the smoothening layer3may provide both smoothening and barrier functions, whereby a separate barrier layer4is not required.

Referring again toFIG.2, at step26an amorphous silicon film5is formed on substrate2A (substrate2A may comprise one or more of ceramic substrate material2, surface smoothing layer3, and/or diffusion barrier layer4) (see alsoFIG.5). The amorphous silicon film or layer5may be deposited utilizing a suitable process such as plasma-enhanced chemical vapor deposition (PECVD). It will be understood that numerous suitable processes are known, and the present disclosure is not limited to a PECVD process. Also, although the semiconductor film or layer5is described as comprising silicon, the layer5may comprise other semiconductor materials such as Ge, SiGe, CdTe, CIGS, Epitaxial GaAs, GaN, etc., where the formation of semiconductor crystalline structures may benefit from high temperature (e.g., greater than about 750° C.) processing at extended times (e.g., greater than 1 μs) to form crystalline semiconductor materials.

Referring again toFIG.2, at step27the amorphous silicon film5and the smoothening film3and/or diffusion barrier film4is patterned into one or more discrete islands15whereby the upper surface16of ceramic substrate2may be exposed (see alsoFIG.6). Formation of individual islands15alleviates potential warpage and/or stress that might otherwise occur as a result of differences in the coefficients of thermal expansion between ceramic substrate material2and semiconductor material5. Formation of islands15also provides electrical isolation of the silicon conductor material5of adjacent islands15. A plurality of islands15may (optionally) be formed on an elongated ceramic ribbon substrate2, whereby the islands15form a patterned layer with gaps17(elongated grooves) between adjacent islands15. The gaps or grooves17may form a grid and islands15may be substantially rectangular in plan view. Although the layers3and4may be patterned (i.e., removed) between adjacent islands15, the layers3and/or4do not necessarily need to be removed in the region of gaps17, and the layers3and/or4may form upper surfaces13in the regions of gaps17between islands15. As discussed below, the gaps between islands15may (optionally) be filled with an electrically insulating material.

Referring again toFIG.2, at step28the silicon material (e.g., amorphous silicon5) is crystallized by annealing the semiconductor material5at an elevated temperature (e.g., at least about 750° C., and preferably greater than about 750° C.). Annealing may be accomplished utilizing a kiln, oven, furnace or other suitable apparatus or process to provide convective heating of substrate2and all materials that are deposited on substrate2at the time of the annealing process. In general, the annealing (step28) may be performed after the islands15are formed as shown inFIG.6.

Referring again toFIG.2, at step29the crystallized semiconductor material5is then doped to form doped regions10,11,11A,12, and12A as shown inFIG.6. As discussed above, the source and drain regions11and12, respectively, may be highly doped, and the adjacent regions11A and12A may be lightly doped. The channel region10may also be lightly doped, if required. Doping may be accomplished utilizing vapor-phase epitaxy or other suitable process. It will be understood that various doping amounts/regions may be utilized as required for a particular application.

Referring again toFIG.2, at step30dielectric material9and9A (FIG.7) is deposited onto the annealed silicon film5and surface13of layers3and/or4. Alternatively, if the layers3and4are removed during the formation of islands15, the dielectric material9A may be deposited directly onto surface16of ceramic substrate2.

Referring again toFIG.2, at step31electrically conductive vias18may be formed in (through) the gate insulator dielectric9, and through the source and drain dielectric9A (see alsoFIG.8). Vias18may comprise metal or other electronically conductive material and may extend through substrate2to form through substrate vias (TSV·s). Alternatively, as discussed below, an insulating layer48(FIG.10A) may be formed (after the electrodes6,7, and8are formed) at steps32,33, and vias18A (FIGS.10A and11) may be formed to provide electrical connections to the electrodes6,7, and8. Vias18(or18A) may have virtually any suitable configuration, and may be hollow with additional conductive material adjacent the opposite ends thereof (e.g., vias18A) to provide electrical contact with one or more additional conductive materials35. It will be understood that various types of suitable vias are known, and the electrically conductive vias18or18A may be positioned and configured as required for a particular application.

Referring again toFIG.2, at step32conductive metal film35is deposited on the exposed surface areas of silicon film5and dielectric materials9,9A (see alsoFIG.9). The conductive material35is checked (if necessary) to ensure Ohmic (or Schottky) contact between the conductive material35and the semiconductor film5at the interface36(FIG.9) between conductive material35and semiconductor material5. In general, the electrical contact may comprise Ohmic contact. Alternatively, Schottky contact may be formed if required for a particular device. The conductive material35may be formed using a physical vapor deposition process or other suitable technique. Conductive material35may comprise metal or other electrically conductive material.

Referring again toFIG.2, at step33the conductive material35is patterned to form source, drain, and gate electrodes6,7, and8, respectively. As shown inFIG.10, the conductive material35may be completely removed around the gate electrode8to expose the surface36of dielectric gate insulating material9to thereby electrically isolate the gate8from the source and drain electrodes6and7, respectively. One or more conductors38may optionally be disposed adjacent lower surface40of ceramic substrate2to electrically connect the electrodes6,7, and8as required in a particular device. The formation of electrodes6,7, and8may be accomplished utilizing an etching process or other suitable technique to pattern conductive material35.

With reference toFIG.10A, a passivation insulating layer or film48may be deposited over the electrodes6,7, and8and over surface36of gate insulator9, and vias18A may be formed to thereby electrically interconnect the electrodes6,7, and8to conductors35A positioned above layer48rather than conductor(s)35as shown inFIG.10. If vias18A are utilized, step31(FIG.2) is conducted after the electrodes are patterned (step33), and insulating film48is also formed after the electrodes are patterned. Conductors35or35A may be utilized to operably interconnect a large number of devices1as required for a flat screen device or other assembly. As shown inFIG.10A, the TSVs18ofFIG.10are not required if vias18A are utilized. However, it will be understood that an insulating layer48may still be formed on the device ofFIG.10to protect the upper surface of device1from moisture, mechanical damage, etc. Insulating layer48may comprise an oxide material (e.g., silicon oxide or silicon nitride) that is deposited in substantially the same manner as insulating material9,9A.

With further reference toFIG.11, a dual gate thin film transistor device1A may be fabricated in a manner that is substantially similar to the process described above in connection withFIGS.1-10(and10A) to form device1. The dual gate device1A includes a pair of gates8that may be located between the source and drain electrodes6and7, respectively. It will be understood that gates8do not necessarily need to be physically positioned between electrodes6and7, but rather may be functionally between electrodes6and7as discussed below in connection withFIG.12. Device1A may include vias18as shown inFIG.10A, and device1A may also include an insulating layer48.

With further reference toFIG.12, a plurality of dual gate transistors1A may be utilized in an LCD display panel42having a plurality of sub-pixels44. The display panel42may comprise an indium tin oxide (ITO) electrode45that is operably connected to the double gate devices1A. Devices1A may be configured as shown inFIG.12, and may include source and drain electrodes6and7, and a gate electrode8disposed adjacent a highly doped region46. In the configuration ofFIG.12, the electrodes6and7are physically positioned (located) to the side of a pair of gate electrodes8. Nevertheless, the devices1A ofFIG.12may have substantially the same functional configuration as shown inFIG.11, and the gates8ofFIG.12are therefore between electrodes6and7in terms of the function of the transistors1A. Conductors35A (or35) may form a grid to electrically connect source, drain, and gate electrodes6,7, and8, respectively, as required. The sub-pixel44may comprise a fringe field switching pixel wherein the sub-pixel44is generally in the shape of a rhombus as shown inFIG.12. Alternatively, sub-pixel44may comprise an OLED including a double gate device1A, in which case the OLED case is generally rectangular or square. It will be understood that various display panel configurations are known in the art, and the specific configurations of a thin film transistor1or1A according to the present disclosure may vary as required for a particular application.

As shown inFIGS.3-11, a thin film device1according to the present disclosure may be formed in a roll-to-roll process. In general, the steps24-33ofFIG.2may correspond to individual stations at which the materials are deposited, patterned, annealed, and doped as discussed in more detail above in connection withFIGS.2-10. Because some of the steps24-33may require more time (e.g., annealing step28), an individual ribbon of the ceramic substrate material may be split into a plurality of individual strips for the annealing step28. In this way, a plurality of strips may be annealed simultaneously (in parallel) to thereby compensate for the increased time required for the annealing step28relative to the other steps.

Although the number of rolls21and22(FIGS.2and3) utilized in the process20(FIG.2) may vary, additional rolls21and22may be positioned adjacent an oven or kiln to provide for parallel annealing at step28(FIG.2), whereas fewer rolls21and22may be positioned adjacent the stations corresponding to steps24-27and steps29-33. Also, at least some of the stations may be positioned directly adjacent one another in a line, whereby a ribbon of the substrate may extend through multiple stations, with a single roll upstream of the first station of the line, and a single roll downstream of the last station of the line.

The ribbon ceramic substrate material2preferably has suitable thermal capabilities to withstand high temperatures to permit annealing of semiconductor material5by heating both the substrate2and the semiconductor material5. Significantly, the ribbon ceramic substrate may withstand temperatures well above 750° C. and may also provide high heat transfer through the substrate due (at least in part) to the reduced thickness of the substrate relative to conventional rigid substrates. This permits annealing of the semiconductor material5in a relatively short period of time (e.g., 15, 30, 45, or 60 minutes) utilizing convection heating via gasses (e.g., air, nitrogen, etc.). The material of ribbon ceramic material2may also have a very high dielectric constant and it may be very thin and flexible. The high thermal conductivity of the ceramic substrate2may be suitable for various electronic applications in which the substrate2dissipates heat generated from the transistor. Thin film transistors fabricated on a ribbon ceramic substrate according to an aspect of the present disclosure may be well-suited for RF applications due to the high dielectric properties of the ribbon ceramic substrate at radio frequencies (RF).

Because the substrate2can withstand temperatures above 750° C., the annealing process (e.g., step25,FIG.2) to form crystalline silicon semiconductor material can be conducted at high substrate temperatures utilizing convection heating in a convection heating apparatus (e.g., an oven, kiln, or furnace), which may provide significant cost savings compared to known excimer laser annealing, flash lamp annealing, or other processes that may be necessary for substrates having lower maximum allowable temperatures.