Fabricating method of a liquid crystal display device

A horizontal electric field applying type thin film transistor substrate of a LCD device having an increased aperture ratio as well as a simplified manufacturing process. The device includes a gate line having a double layered structure including a transparent first conductive layer and an opaque second conductive layer, a data line crossing the gate line to define a pixel area; a thin film transistor connected to the gate line and the data line; a common line having first and second conductive layers and substantially parallel to the gate line; a common electrode extended from the first conductive layer of the common line in the pixel area; and a pixel electrode connected to the thin film transistor to form a horizontal electric field with the common electrode in the pixel area.

Korean Patent Application No. P2004-47574, filed on Jun. 24, 2004, is hereby incorporated by reference for all purposes as is fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device using a horizontal electric field. More particularly, the present invention relates to a horizontal electric field applying type thin film transistor substrate having a simplified process, and a fabricating method thereof.

2. Description of the Related Art

A liquid crystal display device controls the light transmittance of liquid crystal using an electric field, thereby displaying a picture. The liquid crystal display device is divided into two main types: a vertical electric field applying type and a horizontal electric field applying type based upon the direction of an electric field that drives the liquid crystal.

The vertical electric field applying type liquid crystal display device drives a liquid crystal of TN (twisted nematic) mode using a vertical electric field formed between a pixel electrode and a common electrode which are disposed opposite in upper and lower substrates. The vertical electric field applying type liquid crystal display device has an advantage in that its aperture ratio is high, but a disadvantage in that its viewing angle is as narrow as 90°.

The horizontal electric field applying type liquid crystal display device drives a liquid crystal of IPS (in-plane switching) mode using a horizontal electric field which is formed between a pixel electrode and a common electrode disposed in parallel in the lower substrate. The horizontal electric field applying type liquid crystal display device has an advantage in that its viewing angle is as wide as 160°. Hereinafter, the horizontal electric field applying type liquid crystal display device will be described in detail.

The horizontal electric field applying type liquid crystal display device includes a thin film transistor substrate (lower plate) and a color filter substrate (upper plate) which are opposite to each other and bonded together; a spacer maintaining a cell gap between the two substrates; and a liquid crystal filled in the cell gap.

The thin film transistor substrate includes thin film transistors; a plurality of signal wire lines forming a horizontal electric field by pixels; and an alignment film spread thereon for liquid crystal alignment. The color filter substrate includes a color filter for realizing color; a black matrix for preventing light leakage; and an alignment film formed thereon for liquid crystal alignment.

In the liquid crystal display device, the thin film transistor substrate includes a semiconductor process and requires a plurality of mask processes. Thus, its fabricating method is complicated so as to be a major cause of the manufacturing cost increase of the liquid crystal display panel. In order to solve this, the thin film transistor substrate has been developed in a direction of reducing the number of mask processes. This is because one mask process includes many processes like a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photo-resist peeling process, an inspection process and so on. Accordingly, four mask processes have recently been on the rise, wherein the four mask processes are reduced by one mask process from five mask processes which has been a standard mask process of the thin film transistor substrate.

FIG. 1is a plan view illustrating a horizontal electric field applying type thin film transistor substrate using four mask processes of the related art, andFIG. 2is a sectional diagram illustrating the thin film transistor substrate shown inFIG. 1, taken along the lines I-I′, II-II′.

The thin film transistor substrate shown inFIGS. 1 and 2includes a gate line2and a data line4which are formed on a lower substrate45to cross each other with a gate insulating film46therebetween; a thin film transistor6formed at each crossing part; a pixel electrode14and a common electrode18which are formed to form a horizontal electric field in a pixel area; and a common line16connected to the common electrode18. And, the thin film transistor includes a storage capacitor20formed at an overlapping part of the pixel electrode14and the common line16; a gate pad24connected to the gate line2; a data pad30connected to the data line4; and a common pad36connected to the common line16.

The gate line2supplying a gate signal and the data line4supplying a data signal are formed in a cross structure to define a pixel area.

The common line16supplying a reference voltage for driving liquid crystal is formed substantially parallel to the gate line2with a pixel area therebetween.

The thin film transistor6receives the pixel signal of the data line4to be charged and kept in the pixel electrode14in response to the gate signal of the gate line2. The thin film transistor6includes a gate electrode8connected to the gate line2; a source electrode10connected to the data line4; a drain electrode12connected to the pixel electrode14; an active layer48which overlaps the gate electrode8with a gate insulating film46therebetween to form a channel between the source electrode10and the drain electrode12; and ah ohmic contact layer50for being in ohmic contact with the source and drain electrodes10,12and the active layer48.

The active layer48and the ohmic contact layer50are formed to overlap the data line4, the data pad lower electrode32, and a storage upper electrode22.

The pixel electrode14is connected to the drain electrode12of the thin film transistor6through a first contact hole13penetrating a passivation film52. The pixel electrode14is connected to the drain electrode12, and includes a first horizontal part14A formed parallel to the adjacent gate line2; a second horizontal part14B formed to overlap the common line16; and a finger part14C formed in perpendicular between the first and second horizontal parts14A,14B.

The common electrode18is connected to the common line16and formed at a pixel area. The common electrode18is formed parallel to the finger part14C of the pixel electrode14in the pixel area5.

Accordingly, a horizontal electric field is formed between the pixel electrode14to which a pixel signal is supplied through the thin film transistor6and the common electrode18to which a reference voltage (hereinafter, referred to as “common voltage”) is supplied through the common line16. Specifically, the horizontal electric field is formed between the common electrode18and the finger part14C of the pixel electrode14. The liquid crystal molecules, which are arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate by such a horizontal electric field, rotate by dielectric anisotropy. And, the transmittance of the light transmitted through the pixel area is changed in accordance with the extent of rotation of the liquid crystal molecules, thereby realizing a gray level.

The storage capacitor20includes the common line16and the storage upper electrode22which overlap the common line16with the gate insulating film46, the active layer48and the ohmic contact layer50and is connected to the pixel electrode14through a second contact hole21that is formed in the passivation film50. The storage capacitor20is made to stably keep the pixel signal charged in the pixel electrode until the next pixel signal is charged.

The gate line2is connected to a gate driver (not shown) through the gate pad24. The gate pad24includes a gate pad lower electrode26extended from the gate line2; and a gate pad upper electrode28connected to the gate pad lower electrode26through a third contact hole27penetrating the gate insulating film46and the passivation film52.

The data line4is connected to a data driver (not shown) through the data pad30. The data pad30includes a data pad lower electrode32extended from the data line4; and a data pad upper electrode34connected to the data pad lower electrode32through a fourth contact hole penetrating the passivation film52.

The common line16receives a common voltage from an external common voltage source (not shown) through the common pad36. The common pad36includes a common pad lower electrode38extended from the common line16; and a common pad upper electrode40connected to the common pad lower electrode38through a fifth contact hole39penetrating the gate insulating film and the passivation film52.

A fabricating method of the thin film transistor substrate having such a configuration is described in detail by use of four mask processes as shown inFIGS. 3A to 3d.

Referring toFIG. 3A, a gate metal pattern inclusive of the gate line2, the gate electrode8, the gate pad lower electrode26, the common line16, the common electrode18and the common pad lower electrode38is formed on the lower substrate45by use of a first mask process.

To describe in detail, a gate metal layer is formed on the lower substrate45by a deposition method such as sputtering. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, thereby forming the gate metal pattern inclusive of the gate line2, the gate electrode8, the gate pad lower electrode26, the common line16, the common electrode18and the common pad lower electrode38. The gate metal layer is formed of metal of Al, Mo, Cr in a single or double layer structure.

Referring toFIG. 3B, the gate insulating film46is spread on the lower substrate45where the gate metal pattern is formed. And there are formed a semiconductor pattern inclusive of the active layer48and the ohmic contact layer50; and a source/drain metal pattern inclusive of the data line4, the source electrode10, the drain electrode12; the data pad lower electrode32and the storage upper electrode22.

To describe in detail, the gate insulating film46, an amorphous silicon layer, n+ amorphous silicon layer and the source/drain metal layer are sequentially formed by a deposition method such as PECVD, sputtering on the lower substrate45where the gate metal pattern is formed. Herein, the material of the gate insulating film46is mainly an inorganic insulating material such as SiOx, SiNx and so on. The source/drain metal layer is formed of metal of Al, Mo, Cr system in a single or double layer structure. And then, a photo-resist pattern having a stepped difference is formed on the source/drain metal layer by the photolithography process using a second mask. The source/drain metal layer is patterned by use of the photo-resist pattern having the stepped difference, thereby forming the source/drain metal pattern inclusive of the data line4, the source electrode10, the drain electrode integrated with the source electrode10, and the storage upper electrode22. And, the n+ amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photo-resist pattern, thereby forming the ohmic contact layer50and the active layer48. Subsequently, the source/drain metal pattern exposed by ashing the photo-resist pattern is etched along with the ohmic contact layer50, thereby separating the source electrode10and the drain electrode12.

And then, the photo-resist pattern remaining on the source/drain metal pattern is removed by a stripping process.

Referring toFIG. 3C, the passivation film52inclusive of the first to fifth contact holes13,21,27,33,39is formed by a third mask process on the gate insulating film46where the source/drain metal pattern is formed.

To describe in detail, the passivation film52is formed by the deposition method such as PECVD on the entire surface of the gate insulating film46where the source/drain metal pattern is formed. Subsequently, the passivation film52is patterned by the photolithography process and the etching process using a third mask, thereby forming the first to fifth contact holes13,21,27,33,39. The first contact hole13exposes the drain electrode12by penetrating the passivation film52, and the second contact hole21exposes the storage upper electrode22by penetrating the passivation film52. The third contact hole27exposes the gate pad lower electrode26by penetrating the passivation film52and the gate insulating film46, and the fourth contact hole33exposes the data pad lower electrode32by penetrating the passivation film52. The fifth contact hole39exposes the common pad lower electrode38by penetrating the passivation film52and the gate insulating film46.

Herein, the material of the passivation film52is an inorganic insulating material like the gate insulating film46, or an organic insulating material such as BCB, PFCB or acrylic organic compound with low dielectric constant.

Referring toFIG. 3D, a transparent conductive pattern inclusive of the pixel electrode14, the gate pad upper electrode28, the data pad upper electrode34and the common pad upper electrode40is formed on the passivation film54by use of a fourth mask process.

To describe in detail, a transparent conductive film is spread on the passivation film52. Subsequently, the transparent conductive film is patterned by the photolithography process and the etching process using a fourth mask, thereby forming a transparent conductive pattern inclusive of the pixel electrode14, the gate pad upper electrode28, the data pad upper electrode34and the common pad upper electrode40. The pixel electrode14is connected to the drain electrode12that is exposed through the first contact hole13, and is connected to the storage upper electrode22that is exposed through the second contact hole21. The gate pad upper electrode28is connected to the gate pad lower electrode26that is exposed through the third contact hole27. The data pad upper electrode34is connected to the data lower electrode32that is exposed through the fourth contact hole33. The common pad upper electrode40is connected to the common pad lower electrode38that is exposed through the fifth contact hole39.

Herein, the material of the transparent conductive film is ITO (indium tin oxide).

In this way, the related art horizontal electric field applying type thin film transistor substrate and the fabricating method thereof reduces the number of processes to four mask processes, thereby reducing the manufacturing cost proportionally thereto.

However, the common electrode18formed in the pixel area is formed of an opaque gate metal. Thus, there is a problem in that the aperture ratio is low.

Further, due to the aperture ratio problem, there is a limit in increasing the overlapping area of the storage upper electrode22and the common line16formed of the opaque metal. Thus, there is a problem in that the capacity of the storage capacitor20is low.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a liquid crystal display device and fabricating method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide a horizontal electric field applying type thin film transistor substrate for increasing an aperture ratio as well as simplifying its process, and a fabricating method thereof.

Another advantage of the present invention is to provide a horizontal electric field applying type thin film transistor substrate for increasing the capacity of a storage capacitor without reducing the aperture ratio, and a fabricating method thereof.

To achieve these and other advantages of the invention, a liquid crystal display device according to an aspect of the present invention includes a gate line having a double layered structure including a transparent first conductive layer and an opaque second conductive layer; a data line crossing the gate line to define a pixel area; a thin film transistor connected to the gate line and the data line; a common line having first and second conductive layers and substantially parallel to the gate line; a common electrode extended from the first conductive layer of the common line in the pixel area; and a pixel electrode connected to the thin film transistor to form a horizontal electric field with the common electrode in the pixel area.

In another embodiment, a fabricating method of a liquid crystal display device includes: forming a gate pattern having a double layered structure including a transparent first conductive layer and an opaque second conductive layer deposited on a substrate, and a common pattern having a common line of the double layered structure and a common electrode formed of the first conductive layer using a first mask; forming a gate insulating film on the gate pattern and the common pattern; forming a semiconductor pattern on the gate insulating film, and a source/drain pattern having a data line, a source electrode and a drain electrode on the semiconductor pattern using a second mask; forming a passivation film on the source/drain pattern, and a contact hole exposing the drain electrode using a third mask; and forming a pixel electrode connected to the drain electrode through the contact hole using a fourth mask, wherein a horizontal electric field is formed with the common electrode.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

With reference toFIGS. 4 to 12, embodiments of the present invention will be explained as follows.

FIG. 4is a plan view illustrating a horizontal electric field applying type thin film transistor substrate according to an embodiment of the present invention, andFIG. 5is a sectional diagram illustrating the thin film transistor substrate shown inFIG. 4, taken along the lines III-III′, IV-IV′, V-V′, and VI-VI′.

The thin film transistor substrate shown inFIGS. 4 and 5includes a gate line102and a data line104which cross each other with a gate insulating film152therebetween on a lower substrate to define a pixel area; a thin film transistor TFT connected to the gate line102, the data line104and a pixel electrode118; a common electrode122and a pixel electrode118arranged to form a horizontal electric field in a pixel area; and a common line120connected to the common electrode122. And, the thin film transistor substrate further includes first and second capacitors Cst1, Cst2respectively formed at an overlapping part of the common electrode122and the pixel electrode118and an overlapping part of the common line120and the pixel electrode118; a gate pad124connected to the gate line102; a data pad132connected to the data line104; and a common pad140connected to the common line120.

The gate line102supplies a scan signal from a gate driver (not shown) and the data line104supplies a video signal from a data driver (not shown). The gate line102and the data line104cross each other with the gate insulating film152therebetween to define each pixel area. Herein, the gate line102may be formed in a double structure in which a first conductive layer101of transparent conductive layer and a second conductive layer103of opaque metal are formed.

The thin film transistor TFT has a video signal on the data line104charged in the pixel electrode118and kept there in response to a scan signal of the gate line102. For this, the thin film transistor TFT includes a gate electrode which is included in the gate line102; a source electrode110connected to the data line104; a drain electrode112which is opposite to the source electrode110and is connected to the pixel electrode118; an active layer114which overlaps the gate line102with the gate insulating film152therebetween to form a channel between the source electrode110and the drain electrode112; and an ohmic contact layer116formed on the active layer114except for the channel part for being in ohmic contact with the source electrode110and the drain electrode112.

A semiconductor pattern115having the active layer114and the ohmic contact layer116is formed to overlap the data line104and a data pad lower electrode134.

The common line120and the common electrode122supply a reference voltage for driving liquid crystal, i.e., common voltage, to each pixel.

For this, the common line120includes an internal common line120A formed parallel to the gate line102in a display area; and an external common line120B commonly connected to the internal common line120A in a non-display area. The common line120may be formed in a double structure such that first and second conductive layers101,103are formed similar to the gate line102.

The common electrode122is connected to the internal common line120A in each pixel area. Specifically, the common electrode122includes a finger part122B extended from the first conductive layer101of the internal common line120A to the pixel area; and a horizontal part122A connected to the finger part122B. The common electrode122is formed of the transparent conductive layer like the first conductive layer101of the common line120.

The pixel electrode118is connected to the drain electrode112of the thin film transistor TFT, and is arranged to form the horizontal electric field with the common electrode118in each pixel area. Specifically, the pixel electrode118includes a first horizontal part118A which is formed parallel to the gate line102to be connected to the drain electrode112that is exposed through the first contact hole108; a second horizontal part118C formed to overlap the internal common line120A; and a finger part118B formed parallel to the finger part122B of the common electrode to be connected between the first and second horizontal parts118A,118C. If a video signal is supplied to the pixel electrode118through the thin film transistor TFT, a horizontal electric field is formed between the finger part118B of the pixel electrode118and the finger part122B of the common electrode122to which a common voltage is supplied through the common line120. The liquid crystal molecules, which are arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate by such a horizontal electric field, rotate by dielectric anisotropy. And, the transmittance of the light transmitted through the pixel area is changed in accordance with the extent of rotation of the liquid crystal molecules, thereby realizing the gray level.

The storage capacitor includes a first storage capacitor Cst1formed for the first horizontal part118A of the pixel electrode118to overlap the horizontal part122A of the common electrode122with the passivation film154and the gate insulating film152therebetween; and a second storage capacitor Cst2formed of the second horizontal part118C of the pixel electrode118to overlap the internal common line120A with the passivation film154and the gate insulating film152therebetween. Herein, the line width of the part which is to overlap the pixel electrode118is made to be relatively greater in the first conductive layer101of the common line120to increase the overlapping area with the pixel electrode118, thereby enabling an increase in the capacity of the second storage capacitor Cst2without reducing the aperture ratio. Further, the first and second storage capacitors Cst1, Cst2are connected to the pixel electrode118in parallel by sharing the common electrode122or the common line120, thus the capacity of the storage capacitor may be further increased. Herein, it is possible to have one of the first and second storage capacitors Cst1, Cst2as the storage capacitor.

The storage capacitor allows the pixel signal charged in the pixel electrode118to remain stable until the next pixel signal is charged.

The gate line102is connected to a gate driver (not shown) through the gate pad124. The gate pad124includes a gate pad lower electrode126extended from the gate line102; a gate pad upper electrode130connected to the gate pad lower electrode126which is exposed through a second contact hole128penetrating the gate insulating film152and the passivation film154. Herein, the gate pad lower electrode126has a double structure wherein the first and second conductive layers101,103are formed, similar to the gate line102.

The data line104is connected to a data driver (not shown) through the data pad132. The data pad132includes a data pad lower electrode134extended from the data line104together with the semiconductor pattern115thereunder; and a data pad upper electrode138connected to the data pad lower electrode134which is exposed through the third contact hole136penetrating the passivation film154.

The common line120receives reference voltage from a common voltage source (not shown) through the common pad140. The common pad140includes a common pad lower electrode142extended from the external common line120B; and a common pad upper electrode146connected to the common pad lower electrode142which is exposed through a fourth contact hole144penetrating the gate insulating film152and the passivation film154. Herein, the common pad lower electrode142has a double structure wherein the first and second conductive layers101,103are formed, similar to the common line120.

In the horizontal electric field applying type thin film transistor substrate according to the embodiment of the present invention, the common electrode122may be formed of the first conductive layer being the transparent conductive layer, thus it is possible to prevent the deterioration of aperture ratio caused thereby. Further, the common line120may be formed in the double structure such that the first and second conductive layers101,103are formed. Thus, line resistance can be reduced. And, the storage capacitor is configured by having the first and second storage capacitors Cst1, Cst2connected in parallel. Thus, the capacity can be increased without reducing the aperture ratio.

The thin film transistor substrate according to the present invention having such an advantage is formed by the following four mask processes.

FIGS. 6A and 6Bare a plan view and a sectional diagram for explaining a first mask process in a fabricating method of a transflective thin film transistor substrate according to an embodiment of the present invention, andFIGS. 7A to 7Eillustrate sectional diagrams specifically explaining the first mask process.

By the first mask process, there is formed on the lower substrate150a gate pattern having the gate line102and the gate pad lower electrode126; and a common pattern having the common line120, the common electrode122and the common pad lower electrode142. Herein, the gate pattern, the common line and pad120,142are formed in the double structure that the first and second conductive layers101,103are formed, and the common electrode122and part of the internal common line120A are formed in a single layer structure to be extended from the first conductive layer101of the common line120. The gate and common patterns having the double and single layer structure are formed by one mask process using a halftone mask or a diffractive exposure mask. Hereinafter, the case that the halftone mask is used as a first mask is taken as an example for explanation.

Specifically, as shown inFIG. 7A, the first and second conductive layers101,103are formed on the lower substrate150by a deposition method such as sputtering, and a photo-resist167is formed thereon. The first conductive layer101is formed of a transparent conductive material such as ITO, TO, IZO, and the second conductive layer is formed of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo W system. And then, the photo-resist167is exposed and developed by the photolithography process using the halftone mask160, thereby forming a photo-resist pattern168having a stepped difference, as shown inFIG. 7B.

The halftone mask160, as shown inFIG. 7A, includes a transparent quartz SiO2 substrate166, and a partial transmission layer164and a shielding layer162formed thereon. The shielding layer162overlapping the partial transmission layer164is located in an area where the gate pattern is to be formed, to shield ultraviolet ray UV, thereby having a first photo-resist pattern168A remain after development, as shown inFIG. 7B.

The partial transmission layer164which does not overlap the shielding layer162is located in an area where the common electrode122and part of the internal common line120A are to be formed, to partially transmit the ultraviolet ray UV, thereby having a second photo-resist pattern168B remain after development, as shown inFIG. 7B, wherein the second photo-resist pattern168B is thinner than the first photo-resist pattern168A. For this, the shielding layer162is formed of metal such as Cr, CrOx, and the partial transmission layer164is formed of MoSix.

Subsequently, the first and second conductive layers101,103are patterned by the etching process using the photo-resist pattern168with a stepped difference, thereby forming the common electrode122, and the gate pattern, the common line120and the common pad142which have the double layer structure, as shown inFIG. 7C.

And then, the photo-resist pattern168is ashed by an ashing process using oxygen plasma. Thus, the first photo-resist pattern168A becomes thin and the second photo-resist pattern168B is removed, as shown inFIG. 7D. And, the second conductive layer103on the common electrode122and the part of the internal common line120A is removed by the etching process using the ashed first photo-resist pattern168A. At this moment, both side parts of the second conductive layer103patterned along the ashed photo-resist pattern168A are etched once more, thus the first and second conductive layers101,103of the gate pattern, the common line120and the common pad142have a uniform stepped difference in a step shape. Accordingly, in a case in which the side surface part of the first and second conductive layers101,103have a steep slope, the short defect of the source/drain metal layer which can be generated thereon can be prevented.

And, the first photo-resist pattern168A remaining on the gate pattern is removed by the stripping process, as shown inFIG. 7E, thereby completing the gate and common pattern having the double and single layer structure.

FIGS. 8A and 8Billustrate a plan view and a sectional diagram explaining a second mask process in a fabricating method of the thin film transistor substrate according to the embodiment of the present invention, andFIGS. 9A to 9Eillustrate sectional diagrams specifically explaining the second mask process.

The gate insulating film152is formed on the lower substrate150where the gate pattern is formed. And, there is formed by the second mask process thereon the source/drain pattern inclusive of the data line104, the source electrode110, the drain electrode112, the data pad lower electrode134, and the semiconductor pattern115inclusive of the active layer114and the ohmic contact layer116. The semiconductor pattern115and the source/drain pattern are formed by one mask process using the diffractive exposure mask or the halftone mask. Hereinafter, the case of using the diffractive exposure mask as the second mask will be explained.

Specifically, as shown inFIG. 9A, there are sequentially formed the gate insulating film152, an amorphous silicon layer105, an amorphous silicon layer107doped with impurities (n+ or p+) and a source/drain metal layer109on the lower substrate150where the gate pattern is formed. For example, the gate insulating film152, the amorphous silicon layer105and the amorphous silicon layer107doped with impurities (n+ or p+) are formed by a PECVD method, and the source/drain metal layer109is formed by a sputtering method. The gate insulating film152is formed of an inorganic insulating material such as SiOx, SiNx. The source/drain metal layer109is formed of Cr, Mo, Mo W, Al/Cr, Cu, Al(Nd), Al/(Mo), Al(Nd)/Al, Al(Nd)/Cr, Mo/Al(Nd)/Mo, Cu/Mo or Ti/Al(Nd)/Ti. After the photo-resist180is formed over the source/drain metal layer109, the photo-resist180is exposed and developed by the photolithography process using the diffractive exposure mask170, thereby forming a photo-resist pattern182having the stepped difference, as shown inFIG. 9B.

The diffractive exposure mask170, as shown inFIG. 9A, includes a quartz substrate172, and a shielding layer174and a diffractive exposure slit176which are formed of a metal layer such as Cr thereon. The shielding layer174is located at an area, where the semiconductor pattern and the source/drain pattern are to be formed, to shield ultraviolet ray, thereby having a first photo-resist pattern182A remain after development, as shown inFIG. 9B. The diffractive exposure slit176is located at an area, where the channel of the thin film transistor is to be formed, to diffract the ultraviolet ray, thereby having a second photo-resist pattern182B remain after development, as shown inFIG. 9B, wherein the second photo-resist pattern182B is thinner than the first photo-resist pattern182A.

Subsequently, the source/drain metal layer109is patterned by the etching process using the photo-resist pattern182with the stepped difference, thereby forming the source/drain pattern and the semiconductor pattern115thereunder, as shown inFIG. 9C. In this case, the source electrode110and the drain electrode112in the source/drain pattern have an integrated structure.

And then, the photo-resist pattern182is ashed by the ashing process using oxygen O2plasma. Thus, the first photo-resist pattern182A becomes thin and the second photo-resist pattern182B is removed, as shown inFIG. 9D. And, the source/drain pattern exposed by removing of the second photo-resist pattern182B and the ohmic contact layer116thereunder are removed by the etching process using the ashed first photo-resist pattern182A, thereby separating the source electrode110and the drain electrode112and exposing the active layer114. Accordingly, there is formed a channel of the active layer114between the source electrode110and the drain electrode112. At this moment, both side parts of the source/drain pattern are etched once more along the ashed first photo-resist pattern182A, thus the source/drain pattern and the semiconductor pattern115have a uniform stepped difference in a step shape.

And, the first photo-resist pattern182A remaining on the source/drain pattern is removed by the stripping process, as shown inFIG. 9E, thereby completing the semiconductor pattern115and the source/drain pattern.

FIGS. 10A and 10Bare a plan view and a sectional diagram explaining a third mask process in the fabricating method of the thin film transistor substrate according to the embodiment of the present invention.

By the third mask process, there is formed the passivation film154having the first to fourth contact holes108,128,136,144by a method such as PECVD, spin coating, spinless coating on the gate insulating film152where the source/drain pattern is formed.

Specifically, the passivation film154is formed by a method such as PECVD, spin coating, spinless coating on the gate insulating film152where the source/drain pattern is formed. The passivation film154is formed of an organic insulating material or an inorganic insulating material like the gate insulating film152. And, the passivation film154and the gate insulating film152are patterned by the photolithography process and the etching process using the third mask on the passivation film154, thereby forming the first to fourth contact holes108,128,136,144. Herein, the first and third contact holes108,136respectively expose the drain electrode112and the data pad lower electrode134by penetrating the passivation film154. The second and fourth contact holes128,144respectively expose the gate pad lower electrode126and the common pad lower electrode142by penetrating the passivation film154and the gate insulating152.

FIGS. 11A and 11Bare a plan view and a sectional diagram for explaining a fourth mask process in the fabricating method of the thin film transistor substrate according to an embodiment of the present invention.

By the fourth mask process, there is formed the transparent conductive pattern inclusive of the pixel electrode118, the gate pad upper electrode130, the data pad upper electrode138and the common pad upper electrode146.

Specifically, the transparent conductive layer is formed on the passivation film154by a deposition method such as sputtering. The transparent conductive layer is formed of ITO, TO or IZO like the first conductive layer101of the gate and common pattern. Further, the transparent conductive layer can be replaced with an opaque metal, such as Ti, W, which has high corrosion resistance and high strength. And then, the transparent conductive layer is patterned by the photolithography process and the etching process using the fourth mask, thereby forming the transparent conductive pattern having the pixel electrode118, the gate pad upper electrode130, the data pad upper electrode138and the common pad upper electrode146. Accordingly, the pixel electrode118, the gate pad upper electrode130, the data pad upper electrode138and the common pad upper electrode146respectively connected to the drain electrode112, the gate pad lower electrode126, the data pad lower electrode134and the common pad lower electrode142through the first to fourth contact holes108,128,136,144. For example, each of the pixel electrode118, the gate pad upper electrode130, the data pad upper electrode138and the common pad upper electrode146is in contact with the surface of each of the drain electrode112, the gate pad lower electrode126, the data pad lower electrode134and the common pad lower electrode142.

On the other hand, in a case in which the second conductive layer103of the gate pattern and the common pattern and the source/drain pattern are formed of a metal like Mo, with which the dry etching is performed with ease, as shown inFIG. 12, each of the pixel electrode118, the gate pad upper electrode130, the data pad upper electrode138and the common pad upper electrode146is in contact with the side surface of each of the drain electrode112, the gate pad lower electrode126, the data pad lower electrode134and the common pad lower electrode142. This is because the second and fourth contact holes128,144penetrate the second conductive layer130of the gate pad lower electrode126and the common pad lower electrode142and the first and fourth contact holes108,136penetrate the drain electrode112and the data pad lower electrode134in case that the passivation film154and the gate insulating film152are patterned by the third mask process. Particularly, the first and third contact holes108,136penetrate to the semiconductor pattern115under the drain electrode112and the data pad lower electrode134, or are extended to the part of the gate insulating film152.

FIG. 13is a plan view illustrating a horizontal electric field applying type thin film transistor substrate according to another embodiment of the present invention, andFIG. 14is a sectional diagram illustrating the thin film transistor substrate shown inFIG. 13, taken along the lines III-III′, IV-IV′, V-V′, VI-VI′, and VII-VII′.

The thin film transistor substrate shown inFIGS. 13 and 14includes the same components as the thin film transistor substrate shown inFIGS. 4 and 5except that the common electrode222is formed in the double structure that the first and second conductive layers101,103are deposited, like the common line120. Accordingly, the description on the repeated components will be omitted.

The common electrode includes a finger part222B which is connected to the internal common line120A and has a double structure that a transparent first conductive layer101and an opaque second conductive layer are deposited; and a horizontal part222A which is connected to the finger part222B and has a single layer structure formed of only the first conductive layer101. Herein, the second conductive layer103of the finger part222B plays the role of a shielding layer of light leakage caused by the first conductive layer101. At this moment, the second conductive layer103of the finger part222B has a line width narrower than the first conductive layer101so as not to interfere both side parts of the first conductive layer101which contributes to the aperture ratio. For example, the corresponding both side parts of the first conductive layer101from the edge of the finger part222B to about 1 μm inward contributes to the aperture ratio. Thus, the second conductive layer103is formed to overlap the remaining part except the both side parts of the first conductive layer101. Accordingly, the finger part222B of the common electrode222improves the aperture ratio by the first conductive layer101and the light leakage is prevented by the second conductive layer103, thereby enabling to improve contrast.

The finger part222B of the common electrode having the double structure and the horizontal part222A having the single layer structure, as described inFIGS. 6A to 7E, are formed by one mask process using the halftone mask or diffractive exposure mask. In this case, in the finger part222B, the overlapping part of the first and second conductive layers101,103is formed to correspond to the shielding part of the halftone mask (or diffractive exposure mask) and both side parts of the first conductive layer101, which does not overlap the second conductive layer103, are formed in correspondence to the partial transmission part (or diffractive exposure part).

As described above, the horizontal electric field applying type thin film transistor substrate and the fabricating method thereof according to the present invention forms the common electrode of transparent first conductive layer by the same mask process as other common pattern and the gate pattern of the double structure having the first conductive layer. Accordingly, the overall process can be simplified to the four mask processes and the aperture ratio can also be improved. Further, the storage capacitor includes the first and second storage capacitors connected in parallel. Thus, the capacity can be increased without reducing the aperture ratio.

Further, in the horizontal electric field applying type thin film transistor substrate and the fabricating method thereof according to the present invention, the finger part of the common electrode further includes the opaque second conductive layer which overlaps the transparent first conductive layer with its line width narrower than the first conductive layer. Thus, the aperture ratio is improved on both side parts of the first conductive layer, which does not overlap the second conductive layer and the contrast can be improved by preventing the light leakage by the second conductive layer.