Voltage gain amplifier for automotive radar

Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.

TECHNICAL FIELD

This disclosure is related to the field of voltage gain amplifiers for use in the receiver chain of automotive radar devices and, in particular, to a voltage gain amplifier design that is capable of providing a desired level of attenuation in alias bands resulting from a given receiver chain configuration while avoiding issues of gain peaking.

BACKGROUND

Radar systems are now regularly used in driver assistance systems in automobiles, such as for determining the distance to other vehicles and objects near the vehicle that is utilizing the radar system. As one example, the cruise control systems of vehicles may utilize radar such that, in the absence of a nearby vehicle in front of the vehicle utilizing the radar system, a set speed is maintained by the vehicle utilizing the radar system, yet when a nearby vehicle is present in front of the vehicle utilizing the radar system, the vehicle utilizing the radar system slows down to maintain a set distance between itself and the nearby vehicle.

Such a radar system includes a transmit chain to transmit radio waves, and a receive chain to receive radio waves that have reflected off a nearby vehicle or object and returned to the vehicle employing the radar system. By analyzing the received radio waves, the distance to the nearby vehicle or object can be determined.

With reference toFIG. 1, a receive chain10for a vehicular radar system is now described. The receive chain10includes a mixer11, which receives an input radiofrequency signal RX_IN from a radar wave receiver. This input radiofrequency signal RX_IN represents radar waves that have reflected off a target and returned to the receive chain10.

A local oscillator output signal LO_IN is amplified by an amplifier12, and the mixer11mixes the amplified local oscillator output signal LO_IN with the input radiofrequency signal RX_IN to produce a baseband signal. A high-pass filter13filters the baseband signal to attenuate the DC spur and outputs the baseband signal in differential form. The outputs of the high-pass filter13are the differential signals Vinp and Vinm, and each output also carries the input common mode voltage Vicm.

A voltage gain amplifier (VGA)15disclosed herein receives the differential input signal Vicm+Vinp at its non-inverting input terminal, and receives the differential input signal Vicm-Vinm at its inverting input terminal. The VGA15generates the output differential signals Voutp and Voutm, which are received as input by a second voltage gain amplifier (VGA2)24that provides further amplification.

Note that the second VGA24may be of any design, and in some instances does not have the same structure and function as the VGA15. Output of the second VGA24is received and filtered by the low-pass filter16to produce the output differential signals Vlpfp and Vlpfm, which are then converted to the digital domain by the analog to digital converter (ADC)17. The digital signal output OUT from the ADC17can be used to determine the distance between the vehicle into which the receive chain10is integrated and nearby vehicles or objects.

In this example, the bandwidth of the intermediate frequency is approximately 25 MHz, and the ADC17driven by the VGA15is a 12 bit ADC, with a sampling frequency of 100 MHz. The result of the 25 MHz intermediate frequency bandwidth and the sampling frequency of 100 MHz is an alias band at 75 MHz-100 MHz. Therefore, attenuation of about 72 dB at 75 MHz-100 Mhz is desired in order to avoid inadvertently sampling a signal in the alias band.

The low-pass filter16is therefore designed to act as an anti-aliasing filter, and is placed after the second VGA24because, if the low-pass filter16were to be placed before the VGA15, then noise introduced by the low-pass filter16would be amplified, which is undesirable. Therefore, signals in the alias band of 75 MHz-100 MHz are present at the input of the VGA15, and these signals could saturate the VGA15, drowning out the desired signal inside the intermediate frequency band.

As such, it is desired for the design of the VGA15to attenuate signals in the alias band. Attempts at creating VGAs that attenuate signals in the alias band have been made, but they suffer drawbacks. For example, gain peaking in the bandwidth in which attenuation is desired may occur, making the desired level of attenuation unattainable.

Therefore, further development is needed.

SUMMARY

Disclosed herein is a circuit (e.g., a voltage gain amplifier) including: an amplifier having an input receiving an input signal and generating an output signal at an output, wherein the output signal includes desirable low frequency components and undesirable high frequency components; a high-pass filter receiving the output signal and configured to filter out the desirable low frequency components and pass the undesirable high frequency components; and a transistor circuit coupled between the input of the amplifier and ground, wherein the transistor circuit is driven by the undesirable high frequency components of the output signal passed by the high-pass filter such that the transistor circuit removes those undesirable high frequency components from the input signal.

Also disclosed herein is a circuit including: an amplifier having an input receiving an input signal and generate an output signal at an output, wherein the output signal includes undesirable high frequency components; a first chopper configured receive the output signal and process the output signal, wherein the first chopper outputs a chopper output signal in which the undesirable high frequency components are downconverted to a lower frequency as well as upconverted to a higher frequency; a low-pass filter configured to pass the undesirable high frequency components that were downconverted to the lower frequency while filtering out the undesirable high frequency components that were upconverted to the higher frequency; a second chopper configured to upconvert the undesirable high frequency components that were downconverted to the lower frequency by the first chopper back to their original high frequency; and a transistor circuit coupled between the second chopper and ground, wherein the transistor circuit is driven by the downconverted undesirable high frequency components of the output signal passed by the low-pass filter such that the transistor circuit, through the second chopper, removes those upconverted undesirable high frequency components from the input signal.

DETAILED DESCRIPTION

The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein. Note that any resistors illustrated as adjustable resistors may be, for example, banks of selectable resistors, or may be adjustable by any other suitable fashion.

The structure and operation of a voltage gain amplifier (VGA)15, such as may be used in the receive chain1ofFIG. 1, is now described with initial reference toFIG. 2. In particular, the structure is first described, and thereafter, the operation will be described.

The VGA15is comprised of a differential pair of NPN bipolar junction transistors NP1and NP2. A first amplifier23receives the differential input signal Vinp+Vicm at its non-inverting input, has its inverting input coupled to the emitter of the transistor NP1, and provides its output to the base of the transistor NP1. Similarly, a second amplifier26receives the differential input signal Vinm+Vicm at its non-inverting input, has its inverting input coupled to the emitter of the transistor NP2, and provides its output to the base of the transistor NP2. Two adjustable resistors Rs are coupled in series between the emitters of transistors NP1and NP2, with an input common mode voltage Vicm being formed at the center tap between the resistors Rs. The DC gain of the VGA15is Rd/Rs, therefore the gain of the VGA15can be varied by varying Rs.

A current source22is coupled to the emitter of the transistor NP1and sinks a current I1therefrom. An adjustable resistor Rz and NMOS transistor configured as a capacitor Cz are coupled in series between the base of the transistor NP1and ground, and a capacitor C1is coupled between the base of the transistor NP1and ground. A capacitor Cs (representing the input capacitance of the differential amplifier) is illustratively coupled between the inverting terminal of the amplifier23and ground. A current source21is coupled between the collector of the transistor NP1and a supply voltage Vdd, and sources a current I1+I2/2. The capacitor C1is utilized for stabilization of the amplifier23.

Similarly, a current source25is coupled to the emitter of the transistor NP2and also sinks the current I1therefrom. An adjustable resistor Rz and NMOS transistor configured as a capacitor Cz are coupled in series between the base of the transistor NP2and ground, and a capacitor C1is coupled between the base of the transistor NP1and ground. A capacitor Cs (representing the input capacitance of the differential amplifier) is illustratively coupled between the inverting terminal of the amplifier26and ground. A current source24is coupled between the collector of the transistor NP2and the supply voltage Vdd, and sources the current I1+I2/2. The capacitor C1is utilized for stabilization of the amplifier26.

The VGA15also includes a second differential pair of NPN bipolar junction transistors NP3and NP4. The emitters of transistors NP3and NP4are coupled to tail current source28, which sinks a current I2therefrom. The collector of the transistor NP3is coupled to the collector of the transistor NP1as well as to the non-inverting terminal of an amplifier27. The base of the transistor NP3is coupled through a capacitor C1to the non-inverting output of the amplifier27. The collector of the transistor NP4is coupled to the collector of the transistor NP2as well as to the inverting terminal of the amplifier27to receive the output voltage Voutp. The base of the transistor NP3is coupled through a capacitor C1to the inverting output of the amplifier27to receive the output voltage Voutn. Resistors R1are coupled in series between the bases of the transistors NP3and NP4, with an output common mode voltage Vocm forming at the center tap of the resistors R1. The resistors R1and capacitors C1form a high-pass filter. An adjustable resistor Rd is coupled between the inverting input and non-inverting output of the amplifier27, and another adjustable resistor Rd is coupled between the non-inverting input and inverting output of the amplifier27.

In operation, the amplifiers23and26boost the transconductance of the transistors NP1and NP2. The resistors Rz and capacitors Cz form a pole in the transfer function (a zero in the input network), while the capacitors Cs and Rs form a zero in the transfer function. The differential current generated by the transistors NP1and NP2as a result of the resistors Rs flows through the resistors Rd, yielding a gain of:

Note that in the above equation, Cd represents the load capacitance at the output of the VGA15. The resistance values of Rz and Rs track one another over PVT variation because they are formed in the same technology (integrated into the same substrate using the same techniques). Similarly, Cz will generally track the gate to source capacitances of the transistors NP1and NP2. This tracking eliminates concerns of gain peaking, because the pole

1(1+sCz*Rz)
term cancels the zero (1+sCs*Rs).

If it is desired to increase the gain by reducing Rs, Rz is reduced accordingly pursuant to a calibration function to maintain the pole-zero cancelation and the according gain peaking elimination. Similarly, if it is desired to increase the gain by increasing Rd, after setting the value of Rs, Rz is increased to move the zero in the input network closer to the intermediate frequency to remove a gain drooping effect due to Rd*Cd.

To provide for the desired 72 dB of attenuation, the capacitance value of capacitors C1and the resistance value of resistors R1are selected dependent upon where the alias band is expected to be (and may be trimmed for precision), and therefore in the example shown, C1and R1are selected so as to filter frequencies higher than 75 MHz from the input of the differential amplifier formed by transistors NP3and NP4. Therefore, if the differential signal represented by Voutp and Voutn has a component with a frequency of 75 MHz or greater, that component will be removed from the input of the amplifier27by the differential amplifier formed by transistors NP3and NP4, and ultimately from the differential signal represented by Voutp and Voutn. Stated another way, the resistors R1and capacitors C1form a high-pass filter for the purpose of driving the gates of the differential amplifier formed by transistors NP3and NP4with only the high frequency components of the output signal represented by Voutp and Voutn, causing the differential amplifier to effectively act as a low-pass filter, removing signal components greater than the set high-pass filter frequency (here, as an example, 75 MHz) from the output signal represented by Voutp and Voutn.

The reason for the use of this feedback loop to perform low-pass filtering, as opposed to placing capacitors in parallel with the resistors Rd, is that the resulting pole would vary as Rd is varied to change the gain of the VGA15if capacitors had been placed in parallel with the resistors Rd to perform the desired filtering.

Therefore, this design of VGA not only eliminates the gain peaking problem of the prior art, but also achieves the 72 dB attenuation in the alias band of 75 MHz-100 MHz.

It should be appreciated here that the bandwidth of the amplifier formed by transistors NP3and NP4here is 75 MHz-100 MHz (thus, equal to the bandwidth of the alias band).

Now described with reference toFIG. 3is a variant of the VGA15′ that not only eliminates high frequency gain peaking but also provides desired attenuation of the output signals Voutp and Voutn at 75 MHz. The VGA15′ has the same structure of the VGA15ofFIG. 2, except for the connections to the transistors NP3and NP4. Here, a 100 MHz chopper31(the frequency of the chopper32is 100 MHz to match the frequency of the ADC17) is coupled between the collector of transistor NP3and the collector of transistor NP1, and is coupled between the collector of transistor NP4and the collector of transistor NP3.

Also, here, the filter between the output of the amplifier27and the input to the differential amplifier formed by transistors NP3and NP4is different than in the VGA15, because it is a low-pass filter. Indeed, a capacitor C3is coupled between the bases of the transistors NP3and NP4. A resistor R3is coupled between the base of transistor NP4and a 100 MHz chopper32(the frequency of the chopper32is 100 MHz to match the frequency of the ADC17), and another resistor R3is coupled between the base of transistor NP3and the chopper32. The chopper32is coupled between the resistor R3and the inverting output of the amplifier27, and between the resistor R3and the non-inverting output of the amplifier27.

Note that the differential amplifier formed by the transistors NP3and NP4is to have a bandwidth greater than 75 MHz, since the signal driving its input will have a frequency of at least 75 MHz. The choppers31and32are used to reduce this bandwidth. The high frequency components of Voutp and Voutn that were at 75 MHz are therefore chopped by the chopper32to 25 MHz and 125 MHz. The low-pass filter formed by resistors R3and capacitor C3filters out the signal components at 125 MHz, so the bases of the transistors NP3and NP4receive only the 25 MHz signal components. The chopper31converts the frequencies of the signals sink by the transistors NP3and NP4back to 75 MHz to 100 MHz, which is the bandwidth of the alias band.

Thus, in the embodiment ofFIG. 3, the bandwidth of the differential amplifier formed by transistors NP3and NP4in the embodiment ofFIG. 3is 0 MHz-25 MHz, as opposed to the 75 MHz-100 MHz bandwidth of the differential amplifier formed by transistors NP3and NP4in the embodiment ofFIG. 3.

The robust performance of the VGA15′ and VGA15can be seen in the graph ofFIG. 4, where it can be seen that the prior art gain peaking is eliminated, and that the desired attenuation of 72 dB in alias band is achieved, and is in fact exceeded, as the attenuation in the alias band is 78 dB. From the graph ofFIG. 4, it can be noticed that the gain remains relatively flat, and varies by less than 0.5 dB.

In the above descriptions, an intermediate frequency bandwidth of 25 MHz was used as an example, as was the sampling frequency of 100 MHz. The alias band of 75 MHz-100 MHz and the desired attenuation of 72 dB result from the selection of the intermediate frequency bandwidth and sampling frequency. Similarly, the frequency of the choppers result from the frequency of the alias band. It should be understood that these values are for the sake of example, and that any intermediate frequency bandwidth and sampling frequency may be used, and that the level of desired attenuation and the frequency of the choppers may be adjusted accordingly depending upon the intermediate frequency bandwidth and sampling frequency.

It should be understood that, although the example voltage gain amplifiers illustrated and described above have utilized bipolar junction transistors, field effect transistors may instead be used. For example, compare the VGA15″ ofFIG. 5to the VGA15ofFIG. 2. Here, it can be seen that the transistors configured as capacitors Cz′ are n-channel transistors, in which the NPN transistors NP1and NP2are replaced by n-channel transistors MN1and MN2, and in which the NPN transistors NP3and NP4are replaced by n-channel transistors MN3and MN4. The principles of operation of the VGA15″ remain the same as that of the VGA15described above.

Similarly, it should be understood that, although the example voltage gain amplifiers illustrated and described have utilized NPN bipolar junction transistors, they may instead utilize PNP bipolar junction transistors. For example, compare the VGA15′″ ofFIG. 6to the VGA15′ ofFIG. 3. Here, it can be seen that the NPN transistors NP1and NP2are replaced by PNP transistors PN1and PN2, and that the NPN transistors NP3and NP3are replaced by PNP transistors PN3and PN4. In addition, note that the capacitor Cs is coupled between the inverting terminal of amplifier23and Vdd, that the capacitor C1is coupled between the output terminal of amplifier23and Vdd, and that the series connected adjustable resistor Rz and transistor configured as a capacitor Cz are coupled in series between the output terminal of the amplifier23and Vdd. In addition, note that the current I1from the current source22is sourced to the emitter of the PNP transistor PN1, and that the current I1+I2/2 from the current source21is sunk from the collector of the PNP transistor PN1to ground. Similarly, note that the capacitor Cs is coupled between the inverting terminal of amplifier26and Vdd, that the capacitor C1is coupled between the output terminal of amplifier26and Vdd, and that the series connected adjustable resistor Rz and transistor configured as a capacitor Cz are coupled in series between the output terminal of the amplifier26and Vdd. In addition, note that the current I1from the current source25is sourced to the emitter of the PNP transistor PN2, and that the current I1+I2/2 from the current source24is sunk from the collector of the PNP transistor PN2to ground. The principles of operation of the VGA15′″ remain the same as that of the VGA15′ described above.