EXPOSURE-CONTROLLING APPARATUS AND IMAGE-FORMING APPARATUS

There is provided an apparatus having an exposure head including K light-emitting chips arranged along a rotation axis of a photosensitive body. Light-emitting elements to form a latent image are arranged in each light-emitting chip. The apparatus includes: a dividing unit that divides image data into K pieces of partial image data for the K light-emitting chips that are temporarily stored in memory resources; and a control unit that controls output of the K pieces of partial image data from the memory resources to the K light-emitting chips. The control unit controls allocation of the memory resources to the K light-emitting chips based on information indicating which ones of odd-numbered and even-numbered light-emitting chips of the K light-emitting chips are arranged on downstream side with respect to the photosensitive body which rotates.

BACKGROUND

Technical Field

The aspect of the embodiments relates to an exposure-controlling apparatus and an image-forming apparatus.

Description of the Related Art

A generally known type of electro-photographic image-forming apparatus includes a solid-state exposure apparatus that forms a latent image by exposing a photosensitive drum with light emitted by an LED (for example, an organic EL element) rather than a laser beam. An exposure head of this type of apparatus includes a light-emitting element set including a plurality of light-emitting elements arranged parallel to a rotation axis of the photosensitive drum and a rod lens array for focusing the light from the light-emitting element set on the surface of the photosensitive drum. Compared to a laser scanning image-forming apparatus, a solid-state exposure image-forming apparatus has an advantage in that the size and the cost of the apparatus can be easily reduced.

Japanese Patent Laid-Open No. 2017-183436 discloses a configuration of an exposure head of a solid-state exposure image-forming apparatus in which a plurality of light-emitting chips each including a plurality of LEDs are arranged in a staggered manner along a direction parallel to a rotation axis of a photosensitive drum. This configuration with the plurality of light-emitting chips arranged in a staggered manner is advantageous as the size of the exposure head can be easily changed. Japanese Patent Laid-Open No. 2006-305763 discloses a technique of compensating for effects of a deviation in implementation of chips arranged in a staggered manner in a recording head by adaptively controlling a timing of printing operation for each chip though the technique is directed not at a solid-state type apparatus but at an inkjet type apparatus.

In a case where one line of an image is formed by a plurality of chips arranged in a staggered manner as in the case of Japanese Patent Laid-Open No. 2006-305763, it is required to output, to the chips, respective pieces of partial image data corresponding to the chips at different timings instead of outputting them all at the same time. In general, such timing control is based on using memory to buffer the image data and delay data output. At this time, if the minimum amount of memory that can handle the delay amount required for each light-emitting chip is implemented in an apparatus, the manufacturing cost of the apparatus can be minimized. However, such implementation would impose constraints on where the light-emitting chips can be arranged in the exposure head, making it difficult to flexibly change the design. On the other hand, by associating a large-capacity memory with all of the light-emitting chips, flexibility in terms of how to arrange the light-emitting chips in the exposure head is ensured, but the manufacturing cost of the apparatus is significantly increased.

SUMMARY

An apparatus for controlling exposure of a photosensitive body with light by an exposure head is provided. The exposure head includes K (K is an integer equal to or larger than two) light-emitting chips that are arranged in a staggered manner along a first direction that is parallel to a rotation axis of the photosensitive body. Each of the K light-emitting chips includes at least a plurality of light-emitting elements arranged along the first direction. The plurality of light-emitting elements of the K light-emitting chips emit light whereby a latent image for each line of an input image is formed on a surface of the photosensitive body. The apparatus includes: a dividing unit configured to divide image data of each line of the input image into K pieces of partial image data that are respectively output to the K light-emitting chips; a first storage unit that is a set of memory resources for temporarily storing the K pieces of partial image data; and a control unit configured to control output of the K pieces of partial image data from the first storage unit to the K light-emitting chips. The control unit is configured to control allocation of the memory resources to the K light-emitting chips based on first information indicating which ones of odd-numbered light-emitting chips and even-numbered light-emitting chips out of the K light-emitting chips are arranged on downstream side with respect to the photosensitive body which rotates.

DESCRIPTION OF THE EMBODIMENTS

1. SCHEMATIC CONFIGURATION OF IMAGE-FORMING APPARATUS

FIG.1is a diagram illustrating an example of a schematic configuration of an image-forming apparatus1according to an embodiment. The image-forming apparatus1includes a reading unit100, a forming unit103, a fixing unit104, and a conveying unit105. The reading unit100optically reads a document placed on a platen and generates read image data. The image-forming unit103, for example, forms an image on a sheet based on the read image data generated by the reading unit100or based on image data for printing received from an external apparatus via a network.

The forming unit103includes image-forming units101a,101b,101c, and101d. The image-forming units101a,101b,101c, and101drespectively form a black, yellow, magenta, and cyan toner image. The configurations of the image-forming units101a,101b,101c, and101dare the same, and hereinafter they are collectively referred to as image-forming units101. A photosensitive body102of the image-forming unit101is rotationally driven in the clockwise direction of the diagram when image-forming is performed. A charging device107charges the photosensitive body102. An exposure head106exposes the photosensitive body102with light in accordance with the image data to form an electrostatic latent image on the surface of the photosensitive body102. A developing device108develops the electrostatic latent image on the surface of the photosensitive body102using toner to form a toner image. The toner image formed on the surface of the photosensitive body102is transferred to a sheet conveyed on a transfer belt111. By transferring the toner images of the four photosensitive bodies102to the sheet on top of one another, a color image including the four color components black, yellow, magenta, and cyan can be formed.

The conveying unit105controls the feeding and conveying of sheets. Specifically, the conveying unit105feeds a sheet to the conveyance path of the image-forming apparatus1from the unit specified from among internal storage units109aand109b, an external storage unit109c, and a manual insertion unit109d. The fed sheet is conveyed to a registration roller110. The registration roller110conveys the sheet onto the transfer belt111at the appropriate timing so that the toner images of the photosensitive bodies102are transferred to the sheet. As described above, the toner images are transferred to the sheet while the sheet is being conveyed on the transfer belt111. The fixing unit104applies heat and pressure to the sheet with the toner images transferred to fix the toner images to the sheet. After the toner images are fixed, the sheet is discharged to the outside of the image-forming apparatus1by a discharge roller112. An optical sensor113is disposed at a position facing the transfer belt111. The optical sensor113is used to detect misalignment (color misalignment) between the color components on a test image formed on the transfer belt111by the image-forming unit101. In a case where color misalignment is detected, under the control of an image controller800described below, the image-forming positions of the image-forming units101a,101b,101c, and101dare corrected to compensate for the detected color misalignment.

Note that in the example described above, the toner images are directly transferred from the photosensitive bodies102to the sheet on the transfer belt111. However, the toner images may be indirectly transferred from the photosensitive bodies102to the sheet via an intermediate transfer member. Though an example in which a color image is formed using a plurality of colors has been described here, the technology according to the present disclosure is also applicable to an image-forming apparatus that forms a monochrome image using a toner of a single color.

2. CONFIGURATION OF EXPOSURE HEAD

FIGS.2A and2Bare diagrams illustrating the photosensitive body102and the exposure head106. The exposure head106includes a light-emitting element set201, a printed substrate202on which the light-emitting element set201is implemented, a rod lens array203, and a housing204that supports the printed substrate202and the rod lens array203. The photosensitive body102has a cylindrical shape. The exposure head106is disposed with its longitudinal direction parallel to the rotation axis of the photosensitive body102and the surface where the rod lens array203is attached facing the surface of the photosensitive body102. While the photosensitive body102rotates in the circumferential direction (indicated by a dashed line arrow in the diagram) about the rotation axis, the light-emitting element set201of the exposure head106emits light, and the rod lens array203focuses the light on the surface of the photosensitive body102.

FIGS.3A and3Bare diagrams illustrating an example of the configuration of the printed substrate202. Note thatFIG.3Aillustrates the surface where a connector305is implemented, andFIG.3Billustrates the surface where the light-emitting element set201is implemented (the surface on the opposite side to the surface where the connector305is implemented). In the present embodiment, the printed substrate202of the exposure head106includes K (K being an integer equal to or larger than two) light-emitting chips400-1to400-K arranged in a staggered manner along a first direction D1. These light-emitting chips400-1to400-K cover the maximum width (for example, approximately 313 mm) in the first direction D1of an image to be formed. Note that in the present specification, when there is no need to discriminate between the light-emitting chips400-1to400-K, the branch number on the back half of the reference number is omitted and a light-emitting chip400is used as a collective term. This also applies to branch numbers of the reference numbers of other components.

The first direction D1is parallel to the rotation axis of the photosensitive body102and is orientated to correspond to the scan order in each line of image data described below. For the sake of convenience, the smaller branch numbers k (k=1, 2, . . . , K) of the light-emitting chips400-kcorrespond to a position on the upstream side in the first direction D1. As illustrated inFIG.3B, the light-emitting chips400-kwhere k is an odd number (k=1, 3, . . . ) form one row, and the light-emitting chips400-kwhere k is an even number (k=2, 4, . . . ) form another row, and the two rows have different positions in a second direction D2. Hereinafter, the light-emitting chips400in the former row may be referred to as odd-numbered light-emitting chips400, and the light-emitting chips400in the latter row may be referred to as even-numbered light-emitting chips400. The second direction D2is orthogonal to the first direction D1in the surface of the printed substrate202and is orientated to match the rotation direction of the opposing photosensitive body102. In the example inFIG.3B, the even-numbered light-emitting chips400are located on the downstream side in the second direction D2with respect to the odd-numbered light-emitting chips400.

FIG.4is a diagram schematically illustrating the positional relationship among light-emitting elements602in light-emitting chips400, focusing on two adjacent light-emitting chips400-1and400-2. Each light-emitting chip400includes a plurality of light-emitting elements602arranged at least along the first direction D1. Though not illustrated inFIG.4, the light-emitting element array in each light-emitting chip400may be a two-dimensional array including a plurality of light-emitting elements602arranged along the first direction D1and the second direction D2. A pitch L1of the light-emitting elements602adjacent in the first direction D1is equal to approximately 21.16 μm (L1≈21.16 μm) supporting a resolution of 1200 dpi. The pitch L1is maintained across the boundary between the two light-emitting chips400-1and400-2. A gap L2between the light-emitting chip400-1(odd-numbered light-emitting chip) and the light-emitting chip400-2(even-numbered light-emitting chip) in the second direction D2may be approximately 846.4 μm (L2≈846.4 μm), for example. In this case, assuming a resolution of 1200 dpi, L2corresponds to the length of 40 pixels. Note that the values for the pitch L1and the gap L2described above are merely examples, and other values may be used.

Returning toFIG.3A, each light-emitting chip400is connected to the image controller800(seeFIG.7) via the connector305. Each light-emitting element602of the K light-emitting chips400of the printed substrate202are driven in accordance with a data signal input via the connector305as is further described below. The position of the connector305in the image-forming apparatus1may be designed taking into account the wiring situation and the ease of tasks including attachment and maintenance.

Note that at the boundary between the two adjacent light-emitting chips400-1and400-2, one or more of the light-emitting elements602at one end of one of the chips and one or more of the light-emitting elements602at one end of the other chip may overlap in the first direction D1. By overlapping the light-emitting elements602, it is possible to avoid a situation where a blank region is formed which has been insufficiently exposed by the light-emitting elements602at the boundary between chips due to implementation misalignment of the light-emitting chips in the first direction D1or thermal expansion of the substrate. One of the two overlapping light-emitting elements602may be controlled to not emit light as necessary.

FIG.5is a diagram schematically illustrating the configuration of light-emitting chips400, focusing again on two adjacent light-emitting chips400-1and400-2. A light-emitting element array404of each light-emitting chip400is formed on a light-emitting substrate that is a silicon substrate, for example. Also, the light-emitting substrate is provided with a circuit unit406for driving the plurality of light-emitting elements602and a plurality of pads408. The plurality of pads408are used for connecting a signal line for communicating with the image controller800, a power supply line for connecting to a power supply, and a ground line for connecting to a ground to the circuit unit406. The signal line, the power supply line, and the ground line are wires made of gold, for example. The circuit unit406may include both an analog drive circuit and a digital control circuit.

In the example inFIG.5, the pads408of light-emitting chip400-1are located on the upstream side in the second direction D2with respect to the circuit unit406, while the pads408of the light-emitting chip400-2are located on the downstream side in the second direction D2with respect to the circuit unit406. In other words, the positional relationship between the pads408and the circuit unit406are inverted in the two adjacent light-emitting chips400. In this manner, providing the pads408at a position far from a center line401extending in the first direction D1between the two rows of light-emitting chips400makes a good situation for wiring on the printed substrate202. Alternatively, the positional relationship between the pads408and the circuit unit406may not be inverted in the two adjacent light-emitting chips400.

FIG.6is a diagram illustrating a part of a cross section taken along line A-A′ inFIG.5. A plurality of lower electrodes504are formed on a light-emitting substrate402. A light-emitting layer506is provided on the lower electrodes504, and an upper electrode508is provided on the light-emitting layer506. The upper electrode508is one common electrode for the plurality of lower electrodes504. When a voltage is applied between the lower electrodes504and the upper electrode508, a current runs from the lower electrodes504to the upper electrode508, causing the light-emitting layer506to emit light. Accordingly, one lower electrode504and partial regions of the light-emitting layer506and the upper electrode508corresponding to the lower electrode504form one light-emitting element602. In the diagram, dx corresponds to the gap between two adjacent lower electrodes504. dz corresponds to the gap between the lower electrode504and the upper electrode508. By making dx larger than dz, leak current between the adjacent lower electrodes504can be suppressed, and light emission by light-emitting elements602not meant to emit light can be prevented.

In the present embodiment, each light-emitting element602may be constituted as an organic Electro-Luminescence (EL) element. For example, an organic EL film can be used for the light-emitting layer506. In other embodiments, by using an inorganic EL film for the light-emitting layer506, each light-emitting element602may be constituted as an inorganic EL element. Each light-emitting element602may be any type of Light-Emitting Diode (LED).

The upper electrode508is constituted by a transparent electrode made of indium tin oxide (ITO) or the like to be light-transmitting for the light emission wavelength of the light-emitting layer506. In the example inFIG.6, the entire upper electrode508is light-transmitting for the light emission wavelength of the light-emitting layer506, but the entire upper electrode508does not need to be light-transmitting for the light emission wavelength. Specifically, it is sufficient that the partial regions where lights from respective light-emitting elements602pass through are light-transmitting.

Note that inFIG.6, one continuous light-emitting layer506is formed. However, a plurality of the light-emitting layers506each with the same width as the width of the lower electrodes504may be formed on the lower electrodes504. Also, inFIG.6, the upper electrode508is formed as one common electrode for the plurality of lower electrodes504. However, a plurality of the upper electrodes508each with the same width as the width of the lower electrodes504may be formed corresponding to the lower electrodes504. Also, a first plurality of lower electrodes504from among the lower electrodes504of each light-emitting chip400may be covered by a first light-emitting layer506, and a second plurality of lower electrodes504may be covered by a second light-emitting layer506. In a similar manner, a first upper electrode508may be formed in common for a first plurality of lower electrodes504from among the lower electrodes504of each light-emitting chip400, and a second upper electrode508may be formed in common for a second plurality of lower electrodes504. Still in such configurations, one lower electrode504and regions of the light-emitting layer506and the upper electrode508corresponding to the lower electrode504form one light-emitting element602.

3. CONFIGURATION OF IMAGE CONTROLLER

FIG.7is a diagram illustrating an example of the configuration of a control circuit relating to exposure control. Note that in this example, for the sake of simplicity, the processing about a single color component will be described. However, in practice, the processing is executed in parallel for four color components.

The image controller800illustrated on the left inFIG.7is an exposure control apparatus for controlling the exposure of the photosensitive body102by the exposure head106. The image controller800is connected to each light-emitting chip400on the printed substrate202via a plurality of signal lines805to809. The data signal lines805-k(k=1, 2, 3, . . . ) are connected to the light-emitting chips400-k, respectively, and convey image data DATA-k. A clock signal line806conveys a clock signal CLK. A synchronizing signal line808conveys a line synchronizing signal Lsync for identifying line periods of the image data. A communication signal line809conveys a control signal CTL.

An image data generation unit801executes image processing on the image data received from the reading unit100or an external apparatus and generates image data in binary bitmap format for controlling the on/off of light emission of the light-emitting elements602of the light-emitting chips400on the printed substrate202. The image processing here may include raster conversion and halftone processing (for example, dithering), for example. The image data after halftone processing is a set of bits indicating, for each of pixel positions constituting the image to be formed, whether or not to cause the corresponding light-emitting element602to emit light. In a case where a bit at a certain pixel position indicates “light emission”, the corresponding spot region on the surface of the photosensitive body102is exposed to light by the corresponding light-emitting element602. In a case where a bit indicates “no light emission”, the corresponding spot region is not exposed to light. The image data generation unit801outputs the generated image data to a data conversion unit802.

The data conversion unit802converts the image data of each line input from the image data generation unit801into K pieces of partial image data DATA-k at each line period identified by the line synchronizing signal Lsync. Then, the data conversion unit802sends the K pieces of partial image data DATA-k to the data signal lines805-k. The configuration of the data conversion unit802will be described in more detail below.

A clock generation unit803generates the clock signal CLK and sends the clock signal CLK to the clock signal line806for synchronization of timings for transmitting and receiving the signal values between the data conversion unit802and the K light-emitting chips400. A synchronizing signal generation unit804determines break points of lines for the image data, generates the line synchronizing signal Lsync, and supplies the generated line synchronizing signal Lsync to the synchronizing signal line808.

A storage unit810of the printed substrate202is a memory (for example, a non-volatile memory) for storing control information for controlling the light emission by the light-emitting chips400. For example, the control information is written from an external apparatus to the storage unit810when the exposure head106is manufactured. The control information stored by the storage unit810may include setting values relating to the drive current amount supplied to the light-emitting chips400and the chip arrangement information described below, for example.

Each light-emitting chip400drives the light-emitting elements602in accordance with the image data input from the data conversion unit802at each line period identified by the line synchronizing signal Lsync. Specifically, each light-emitting chip400-kreceives partial image data DATA-k for its own chip via the data signal lines805-k. Then, each light-emitting chip400-kdrives each light-emitting element602of the light-emitting element array in accordance with the pixel values included in the received partial image data DATA-k. Next, the light-emitting elements602of the K light-emitting chips400emit light in accordance with the image data, and an electrostatic latent image for each line of the input image is formed on the surface of the photosensitive body102. Then, as the result of a continuous formation of the lines in the circumferential direction of the photosensitive body102, a two-dimensional electrostatic latent image is created.

A CPU811controls the entire image-forming apparatus1. For example, the CPU811causes the image data generation unit801to generate the image data described above when a job for image-formation is executed and send the image data from the data conversion unit802to the printed substrate202. The CPU811, before executing the job, outputs the chip arrangement information read out from the storage unit (control information storage unit)810of the printed substrate202connected to the image controller800to the data conversion unit802. The output of the image data from the data conversion unit802is controlled based on the chip arrangement information.

4. ENSURING FLEXIBILITY IN CHIP ARRANGEMENT

4.1 Chip Position

Manufacturers of an image-forming apparatus have been trying to supply the market with various types of products of different size and shape and with different circuit configurations to meet a diverse range of needs. To suppress an increase in the manufacturing cost of such products and realize product diversity, in one embodiment, the reusability of components between different types of products are increased. For example, as described usingFIGS.3A to5, even-numbered light-emitting chips are located on the downstream side with respect to the odd-numbered light-emitting chips in a product of a certain type while the even-numbered light-emitting chips may be located on the upstream side with respect to the odd-numbered light-emitting chips in a product of a different type.FIGS.8A and8Bare explanatory diagrams for describing such product variation.

InFIG.8A, a positional relationship among the photosensitive body102, the exposure head106, the developing device108, and the transfer belt111of the image-forming unit101similar to that illustrated inFIG.1is illustrated. The exposure head106is located above the photosensitive body102and emits light from up to down. The odd-numbered light-emitting chips400of the exposure head106are located on the left side of the diagram, and the even-numbered light-emitting chips400are located on the right side of the diagram. Since the photosensitive body102rotates in the clockwise direction in the diagram as indicated by the dashed line arrow, the odd-numbered light-emitting chips400of the exposure head106are located on the upstream side, and the even-numbered light-emitting chips400are located on the downstream side. In this manner, the chip arrangement of the even-numbered light-emitting chips400on the downstream side with respect to the rotation direction (the second direction D2) of the photosensitive body102may be referred to herein as the even-numbered-downstream arrangement.

InFIG.8B, a positional relationship among the photosensitive body102, the exposure head106, the developing device108, and the transfer belt111different to that illustrated inFIG.8Ais illustrated. The exposure head106is located below the photosensitive body102and emits light from down to up. The odd-numbered light-emitting chips400of the exposure head106are located on the right side of the diagram, and the even-numbered light-emitting chips400are located on the left side of the diagram. Since the photosensitive body102rotates in the anticlockwise direction in the diagram as indicated by the dashed line arrow, the odd-numbered light-emitting chips400of the exposure head106are located on the downstream side, and the even-numbered light-emitting chips400are located on the upstream side. In this manner, the chip arrangement of the odd-numbered light-emitting chips400on the downstream side with respect to the rotation direction of the photosensitive body102may be referred to herein as the odd-numbered-downstream arrangement.

As described usingFIGS.3A and3B, whether to use the even-numbered-downstream arrangement or the odd-numbered-downstream arrangement for the image-forming apparatus may be decided in relation to the position of the connector305of the exposure head106and taking into account the wiring situation and the ease of tasks including attachment and maintenance. In such a situation, if an image controller800that is connectable to both an exposure head106using the even-numbered-downstream arrangement and an exposure head106using the odd-numbered-downstream arrangement is provided, the reusability of components is increased.

Here, the data conversion unit802of the image controller800divides the image data of each line of the input image into K pieces of partial image data and outputs the partial image data to the K light-emitting chips400. At this time, the timing for outputting the pieces of partial image data of each line to the light-emitting chips400on the downstream side is to be delayed by an amount corresponding to the chip gap L2with respect to the timing for outputting the pieces of partial image data of the same line to the light-emitting chips400on the upstream side. For example, by setting the pixel pitch in the second direction D2to 21.16 μm and the chip gap L2to 846.4 μm, L2corresponds to 40 lines. In this case, a memory resource for buffering at least 40 lines of partial image data for a light-emitting chip400on the downstream side is required for each of the number of light-emitting chips400on the downstream side. However, if the image controller800is made able to support both the even-numbered-downstream arrangement and the odd-numbered-downstream arrangement, any of the light-emitting chips400has eventually a possibility to be located on the downstream side. Thus, with a uniform allocation of memory resources, the memory resources for 40 lines for all of the light-emitting chips400is to be prepared. This means an increase in the manufacturing cost of the image controller800.

In the embodiment described below, to suppress an increase in the manufacturing costs without decreasing the flexibility in chip arrangement in the exposure head106, in the data conversion unit802of the image controller800, a mechanism is implemented for variably allocating memory resources. For example, the manufacturer of an apparatus writes first control information indicating whether the positional relationship between the photosensitive body102and the exposure head106used in the image-forming unit101is the even-numbered-downstream arrangement or the odd-numbered-downstream arrangement from an external apparatus to the control information storage unit810. The first control information is, more specifically, information indicating whether, from among the K light-emitting chips, the odd-numbered light-emitting chips or the even-numbered light-emitting chips are arranged on the downstream side with respect to the rotating photosensitive body. Hereinafter, the first control information may be referred to as the chip position information. The data conversion unit802, as described in detail below, controls the allocation of memory resources for the K light-emitting chips400based on the chip position information.

Furthermore, in a product of a certain type, as described usingFIG.5, the positional relationship between the pads408and the circuit unit406is inverted in two adjacent light-emitting chips400. By inverting two light-emitting chips400with the same circuit design in this manner, the order of outputting signals to the plurality of light-emitting elements602in one of the light-emitting chips400becomes inverted with respect to the order of outputting signals in the other light-emitting chip400. In this case, the order of outputting signals of one light-emitting chip400corresponds to the forward direction and the order of outputting signals of the other light-emitting chip400corresponds to the reverse direction with respect to the order of scanning pixel values of an input image.FIGS.9A and9Bare explanatory diagrams for describing variation relating to the order of outputting signals among light-emitting chips.

The example inFIG.9Acorresponds to the positional relationship between the pads408and the circuit unit406described usingFIG.5. The first light-emitting chip400-1is illustrated on the left of the diagrams, and the second light-emitting chip400-2is illustrated on the right. Each light-emitting chip400includes the plurality of light-emitting elements602-1,602-2,602-3, and so on. The branch number of the plurality of light-emitting elements602in the diagrams indicates the order of outputting signals to the light-emitting elements602, and outputting a signal to a light-emitting element602with a lower branch number precedes outputting a signal to a light-emitting element602with a higher branch number. In the first light-emitting chip400-1illustrated inFIG.9A, the light-emitting elements602-1,602-2,602-3, and so on are arranged from the left along the first direction D1. Thus, the order of outputting signals to the light-emitting elements602is the forward direction with respect to the order of scanning of pixel values of image data. On the other hand, in the second light-emitting chip400-2, the light-emitting elements602-1,602-2,602-3, and so on are arranged from the right. Thus, the order of outputting signals to the light-emitting elements602is the reverse direction with respect to the order of scanning of pixel values of image data.

Moving toFIG.9B, in both the first light-emitting chip400-1and the second light-emitting chip400-2, the light-emitting elements602-1,602-2,602-3, and so on are arranged from the left along the first direction D1. Thus, the order of outputting signals to the light-emitting elements602is the forward direction with respect to the order of scanning of pixel values of image data for both light-emitting chips400.

In a comparison of the two examples, the example inFIG.9Bin which the order of outputting signals to the light-emitting elements602never becomes the reverse direction is advantageous in that the signal output control is simple. On the other hand, as described in relation toFIG.5, the example inFIG.9Ahas a good situation for wiring as the pads408come at a position distanced from the center line401in all of the light-emitting chips400. Accordingly, whether to use the orientation with the forward direction or the reverse direction with respect to the order of outputting signals to the light-emitting elements602still depends on the design of the manufacturer of the apparatus. Note that in the example illustrated inFIG.9A, from among the odd-numbered light-emitting chips and the even-numbered light-emitting chips, the signal output order of the former is the forward direction and the signal output order of the latter is the reverse direction. However, naturally a variation in which the signal output order of the former is the reverse direction and the signal output order of the latter is the forward direction can be conceived.

In the embodiment described below, to be able to use the image controller800no matter which orientation out of the forward direction and the reverse direction is used, a mechanism that can switch the order of reading out pixel values from the memory resources is introduced. For example, the manufacturer of an apparatus writes second control information for controlling the order of reading out pixel values from the memory resources from an external apparatus to the control information storage unit810. The second control information is, more specifically, information indicating the orientation in which each of the K light-emitting chips400is implemented in the exposure head106. Hereinafter, the second control information may be referred to as the chip orientation information. As described in detail below, the data conversion unit802controls the order of reading out pixel values constituting partial image data based on the chip orientation information when the corresponding partial image data is output to each light-emitting chip400.

4-3. Configuration Example of Chip Arrangement Information

In the present specification, the chip position information (the first control information) and the chip orientation information (the second control information) described above may be collectively referred to as the chip arrangement information.

The chip position information may be 1-bit information indicating whether the odd-numbered light-emitting chips from among the K light-emitting chips are arranged on the upstream side or the downstream side. For example, the chip position information indicating “0” means that the odd-numbered light-emitting chips are arranged on the upstream side and the even-numbered light-emitting chips are arranged on the downstream side. The chip position information indicating “1” means that the odd-numbered light-emitting chips are arranged on the downstream side and the even-numbered light-emitting chips are arranged on the upstream side. Naturally, the bit values (0/1) and their meaning may be reversed.

The chip orientation information may be 1-bit information indicating whether the forward direction or the reverse direction is implemented in each of light-emitting chips. For example, the chip orientation information indicating “0” means that each of the odd-numbered light-emitting chips is implemented in the forward direction and each of the even-numbered light-emitting chips is implemented in the reverse direction. The chip orientation information indicating “1” means that each of the odd-numbered light-emitting chips is implemented in the reverse direction and each of the even-numbered light-emitting chips is implemented in the forward direction. Naturally, the bit values (0/1) and their meaning may be reversed. In this example, the state with all of the light-emitting chips400implemented in the forward direction as illustrated inFIG.9Bis not indicated by the chip orientation information. The chip arrangement information including the chip position information described above and this chip orientation information is information totaling 2 bits and covers four types of chip arrangement variations.

The chip orientation information may include 1 bit indicating whether the forward direction or the reverse direction is implemented in each of the odd-numbered light-emitting chips and 1 bit indicating whether the forward direction or the reverse direction is implemented in each of the even-numbered light-emitting chips. For example, the bit value “0” means that the related light-emitting chips400are implemented in the forward direction, and the bit value “1” means that the related light-emitting chips400are implemented in the reverse direction. In this example, the state with all of the light-emitting chips400implemented in the forward direction as illustrated inFIG.9Bcan be indicated by the chip orientation information. The chip arrangement information combining the 1-bit chip position information with the 2-bit chip orientation information is information totaling 3 bits and covers eight types of chip arrangement variations.

Note that the configuration of the chip arrangement information is not limited to the examples described above. To cover a broader range of types of chip arrangement variations, the chip arrangement information may include more bits.

5. DETAILS OF DATA CONVERSION UNIT

The data conversion unit802, for example, may be implemented using a dedicated processing circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Alternatively, the data conversion unit802may be implemented using a combination of a general-purpose processor and a memory. In the latter case, a computer program for implementing the functions of the data conversion unit802is stored in advance in a non-transitory computer-readable storage medium, loaded on random access memory (RAM), and executed by a processor.

(1) CIRCUIT EXAMPLE CONFIGURATION

FIG.10is a block diagram illustrating a detailed configuration of the data conversion unit802according to the present embodiment. As illustrated inFIG.10, the data conversion unit802includes a data dividing unit721, an input selection unit722, a data storage unit723, an output selection unit725, and a memory control unit726.

The data dividing unit721divides image data IM of each line of the input image into K pieces of partial image data to be output to the K light-emitting chips400. Then, the data dividing unit721outputs the K pieces of partial image data to the input selection unit722.

The data storage unit723is a set of memory resources for temporarily storing the K pieces of partial image data. For example, the memory resources may be constituted by static random access memory (SRAM). In the example inFIG.10, the data storage unit723includes K line memories724-1to724-K. The capacity of each line memory724-kin a case where k is an odd number is less than the capacity of each line memory724-kin a case where k is an even number. Note that the K line memories724-1to724-K may be individual memories or may be different memory regions statically or dynamically allocated in a solitary memory.

The input selection unit722is a selector arranged between the data dividing unit721and the data storage unit723. The input selection unit722switches writing paths of partial image data from the data dividing unit721to the line memories724-1to724-K in accordance with memory resource allocation by the memory control unit726.

The output selection unit725is a selector arranged between the data storage unit723and the K data signal lines805-1to805-K. The output selection unit725switches output paths of partial image data from the line memories724-1to724-K in accordance with memory resource allocation by the memory control unit726.

(2). VARIABLE ALLOCATION OF MEMORY RESOURCES

The memory control unit726controls allocation of memory resources to the K light-emitting chips400and output of the partial image data from allocated memory resources to corresponding light-emitting chips400. Specifically, first, the memory control unit726decides which of the line memories724of the data storage unit723to allocate to each light-emitting chip400based on the chip position information read out from the storage unit810.

In a first example, the chip position information indicates that the odd-numbered light-emitting chips are arranged on the upstream side. In other words, the even-numbered-downstream arrangement is used. In this case, the memory control unit726allocates the odd-numbered line memories724-kto the odd-numbered light-emitting chips400-k(k=1, 3, and so on). Also, the memory control unit726allocates the even-numbered line memories724-kto the even-numbered light-emitting chips400-k(k=2, 4, and so on).

In a second example, the chip position information indicates that the even-numbered light-emitting chips are arranged on the upstream side. In other words, the odd-numbered-downstream arrangement is used. In this case, the memory control unit726allocates the even-numbered line memories724-(k+1) to the odd-numbered light-emitting chips400-k(k=1, 3, and so on). Also, the memory control unit726allocates the odd-numbered line memories724-(k−1) to the even-numbered light-emitting chips400-k(k=2, 4, and so on).

Here, the amount of memory resources allocated to each of the light-emitting chips400determined to be arranged on the upstream side is defined as a first amount C1, and the amount of memory resources allocated to each of the light-emitting chips400determined to be arranged on the downstream side is defined as a second amount C2. Then, in both the first example and the second example, the second amount C2is larger than the first amount C1. In this manner, buffering can be performed for the partial image data for the light-emitting chips400on the downstream side using the data storage unit723over a longer interval.

The memory control unit726causes the partial image data for the light-emitting chips400on the upstream side to be output from the data storage unit723to the corresponding light-emitting chips400at a first point in time t1. Thereafter, the memory control unit726causes the partial image data for the light-emitting chips400on the downstream side to be output from the data storage unit723to the corresponding light-emitting chips400at a second point in time t2later than the first point in time t1.

The difference between the amount C1of memory resources allocated to the light-emitting chips400on the upstream side and the amount C2of memory resources allocated to the light-emitting chips400on the downstream side is based on the number of line periods that advance during an interval from the first point in time t1to the second point in time t2. A duration Δt of the interval described above from the first point in time t1to the second point in time t2is typically calculated as Δt=L2/V, based on the chip gap L2along the rotation direction of the photosensitive body102and a peripheral speed V of the photosensitive body102. In a case where Δt is equal to a times of the line period, and the data amount of one unit of partial image data is defined as Z, C2=C1+αZ may hold. Accordingly, compared to the case of a method of uniformly allocating memory resources instead of variably allocating memory resources, with the present embodiment, an amount of memory resources equal to the product of αZ and the number of light-emitting chips on the upstream side can be saved.

FIGS.11A and11Bare explanatory diagrams for how memory resources are variably allocated in the data conversion unit802.FIG.11Acorresponds to the first example described above, that is the even-numbered-downstream arrangement. In this case, the partial image data DATA-1, DATA-3, and so on for the odd-numbered light-emitting chips400are written to the odd-numbered line memories724-1,724-3, and so on via the input selection unit722. The line memories724-1,724-3, and so on temporarily store the written data. Then, the partial image data DATA-1, DATA-3, and so on are promptly read out via the output selection unit725and sent to the corresponding data signal lines805-1,805-3, and so on. On the other hand, the partial image data DATA-2, DATA-4, and so on for the even-numbered light-emitting chips400are written to the even-numbered line memories724-2,724-4, and so on via the input selection unit722. The line memories724-2,724-4, and so on temporarily store the written data. Then, the partial image data DATA-2, DATA-4, and so on are read out via the output selection unit725after a delay of the duration Δt and sent to the corresponding data signal lines805-2,805-4, and so on.

FIG.11Bcorresponds to the second example described above, that is the odd-numbered-downstream arrangement. In this case, the partial image data DATA-1, DATA-3, and so on for the odd-numbered light-emitting chips400are written to the even-numbered line memories724-2,724-4, and so on via the input selection unit722. The line memories724-2,724-4, and so on temporarily store the written data. On the other hand, the partial image data DATA-2, DATA-4, and so on for the even-numbered light-emitting chips400are written to the odd-numbered line memories724-1,724-3, and so on via the input selection unit722. The line memories724-1,724-3, and so on temporarily store the written data. Then, the partial image data DATA-2, DATA-4, and so on are promptly read out via the output selection unit725and sent to the corresponding data signal lines805-2,805-4, and so on. The partial image data DATA-1, DATA-3, and so on are read out via the output selection unit725after a delay of the duration Δt and sent to the corresponding data signal lines805-1,805-3, and so on.

FIG.12Ais a timing chart illustrating a first example of output timing for the partial image data from the data conversion unit802. The chip arrangement is the even-numbered-downstream arrangement. The horizontal axis inFIG.12Arepresents the passage of time. The highest level in the diagram indicates the timing asserted by the line synchronizing signal Lsync, and the period of the assertion corresponds to the line period. The second to fifth levels represent the output timings of signal sequences LNxx-k of the partial image data DATA-k for the light-emitting chip400-k, where k=1, 2, 3, and 4 and xx represents the line number.

First, in the line period from time T0to T1, the signal sequence LN01-1for the light-emitting chip400-1and the signal sequence LN01-3for the light-emitting chip400-3of the first line are output. In the next line period from time T1to T2, the signal sequence LN02-1for the light-emitting chip400-1and the signal sequence LN02-3for the light-emitting chip400-3of the second line are output. During this time, data is not output to the light-emitting chips400-2and400-4(and the other even-numbered light-emitting chips400).

When time T40is reached, the signal sequence for 40 lines has been output to the odd-numbered light-emitting chips400-1,400-3, and so on. The signal sequence LN41-1for the light-emitting chip400-1of the next forty-first line is written to the line memory724-1. The signal sequence LN41-3for the light-emitting chip400-3of the next forty-first line is written to the line memory724-3. However, partial image data has not been output to the even-numbered light-emitting chips400-2,400-4, and so on. The line memory724-2has the signal sequence for 40 lines for the light-emitting chip400-2stored therein, and in addition, the signal sequence LN41-2of the forty-first line is written. The line memory724-4has the signal sequence for 40 lines for the light-emitting chip400-4stored therein, and in addition, the signal sequence LN41-4of the forty-first line is written.FIG.13Ais a diagram illustrating how the data storage unit723stores the partial image data at this point in time. In each light-emitting chip400, since necessary and sufficient amounts of memory resources for timing control of the data output have been allocated, the memory resources are efficiently used without waste as seen from the diagram.

Returning toFIG.12A, in the line period from time T40to T41, the signal sequence LN41-1for the light-emitting chip400-1and the signal sequence LN41-3for the light-emitting chip400-3of the forty-first line are output. Also, in the same line period, the signal sequence LN01-2for the light-emitting chip400-2and the signal sequence LN01-4for the light-emitting chip400-4of the first line are output. In the next line period from time T41to T42, the signal sequence LN42-1for the light-emitting chip400-1and the signal sequence LN42-3for the light-emitting chip400-3of the forty-second line are output. Also, in the same line period, the signal sequence LN02-2for the light-emitting chip400-2and the signal sequence LN02-4for the light-emitting chip400-4of the second line are output.

FIG.12Bis a timing chart in a format similar toFIG.12Aillustrating a second example of output timing for the partial image data from the data conversion unit802. The chip arrangement is the odd-numbered-downstream arrangement.

First, in the line period from time T0to T1, the signal sequence LN01-2for the light-emitting chip400-2and the signal sequence LN01-4for the light-emitting chip400-4of the first line are output. In the next line period from time T1to T2, the signal sequence LN02-2for the light-emitting chip400-2and the signal sequence LN02-4for the light-emitting chip400-4of the second line are output. During this time, data is not output to the light-emitting chips400-1and400-3(and the other odd-numbered light-emitting chips400).

When time T40is reached, the signal sequence for 40 lines has been output to the even-numbered light-emitting chips400-2,400-4, and so on. The signal sequence LN41-2for the light-emitting chip400-2of the next forty-first line is written to the line memory724-1. The signal sequence LN41-4for the light-emitting chip400-4of the next forty-first line is written to the line memory724-3. However, partial image data has not been output to the odd-numbered light-emitting chips400-1,400-3, and so on. The line memory724-2has the signal sequence for 40 lines for the light-emitting chip400-1stored therein, and in addition, the signal sequence LN41-1of the forty-first line is written. The line memory724-4has the signal sequence for 40 lines for the light-emitting chip400-3stored therein, and in addition, the signal sequence LN41-3of the forty-first line is written.FIG.13Bis a diagram illustrating how the data storage unit723stores the partial image data at this point in time. In each light-emitting chip400, since necessary and sufficient amounts of memory resources for timing control of the data output have been allocated as again seen from the diagram, the memory resources are efficiently used without waste.

Returning toFIG.12B, in the line period from time T40to T41, the signal sequence LN41-2for the light-emitting chip400-2and the signal sequence LN41-4for the light-emitting chip400-4of the forty-first line are output. Also, in the same line period, the signal sequence LN01-1for the light-emitting chip400-1and the signal sequence LN01-3for the light-emitting chip400-3of the first line are output. In the next line period from time T41to T42, the signal sequence LN42-2for the light-emitting chip400-2and the signal sequence LN42-4for the light-emitting chip400-4of the forty-second line are output. Also, in the same line period, the signal sequence LN02-1for the light-emitting chip400-1and the signal sequence LN02-3for the light-emitting chip400-3of the second line are output.

(3) VARIABLY SWITCH ORDER OF READING OUT PIXEL VALUES

In addition to the variable allocation of memory resources based on the chip position information described above, in the present embodiment, the memory control unit726also variably switches the order of reading out pixel values from the memory resources.

Specifically, the memory control unit726decides whether to read out pixel values constituting the partial image data in the forward direction or the reverse direction when outputting the partial image data from the data conversion unit802to each light-emitting chip400based on the chip orientation information obtained from the storage unit810. Take an example in which the chip orientation information indicates the forward direction orientation for a certain light-emitting chip400. In this example, the memory control unit726sets the output selection unit725such that the pixel values constituting the partial image data corresponding to the light-emitting chip400are read out from the corresponding line memory724in the forward direction to output them. Alternatively, take an example in which the chip orientation information indicates the reverse direction orientation for a certain light-emitting chip400. In this example, the memory control unit726sets the output selection unit725such that the pixel values constituting the partial image data corresponding to the light-emitting chip400are read out from the corresponding line memory724in the reverse direction to output them.

FIGS.14A and14Bare explanatory diagrams of the variable switching of the order of reading out pixel values based on the chip orientation information.FIG.14A, similar toFIG.11A, illustrates the allocation of memory resources to the light-emitting chips400for the even-numbered-downstream arrangement. Herein, it is assumed that the chip orientation information indicates the forward direction orientation for the odd-numbered light-emitting chips400and the reverse direction orientation for the even-numbered light-emitting chips400. In this case, when the partial image data DATA-1 is output, the pixel values are read out from the corresponding line memory724-1in the same order as when they are written. This also applies to the partial image data DATA-3 and the partial image data for the other odd-numbered light-emitting chips400. On the other hand, when the partial image data DATA-2 is output, the pixel values are read out from the corresponding line memory724-2in the reverse order as when they are written. This also applies to the partial image data DATA-4 and the partial image data for the other even-numbered light-emitting chips400. In the diagram, the reversing of the order of reading out is indicated by the curved arrows.

FIG.14B, similar toFIG.11B, illustrates the allocation of memory resources to the light-emitting chips400for the odd-numbered downstream arrangement. Herein again, the chip orientation information indicates the forward direction orientation for the odd-numbered light-emitting chips400and the reverse direction orientation for the even-numbered light-emitting chips400. In this case, when the partial image data DATA-1 is output, the pixel values are read out from the corresponding line memory724-2in the same order as when they are written. This also applies to the partial image data DATA-3 and the partial image data for the other odd-numbered light-emitting chips400. On the other hand, when the partial image data DATA-2 is output, the pixel values are read out from the corresponding line memory724-1in the reverse order as when they are written. This also applies to the partial image data DATA-4 and the partial image data for the other even-numbered light-emitting chips400.

FIG.15is a timing chart illustrating an example of the reversing of the order of reading out pixel values. Herein, an even-numbered-downstream arrangement similar to that used in the example inFIG.12Ais employed. In the lower half ofFIG.15, the signal sequence LN41-1for the light-emitting chip400-1and the signal sequence LN01-2for the light-emitting chip400-2output in the line period from time T40to T41are indicated in an enlarged manner. The timing of the rise and the fall of the clock signal CLK indicating the clock period is also illustrated, and each signal sequence includes one pixel value dxxx for each clock period, where xxx is an index that is incremented in the scanning order of pixel values in each piece of partial image data. As an example, each piece of partial image data includes 800 pixel values.

In the example inFIG.15, the chip orientation information indicates the forward direction orientation for the odd-numbered light-emitting chips400and the reverse direction orientation for the even-numbered light-emitting chips400. Accordingly, the signal sequence LN41-1for the light-emitting chip400-1includes the pixel values d001 to d800 arranged in a time series in ascending order of the index that are read out in the forward direction from the line memory724-1. On the other hand, the signal sequence LN01-2for the light-emitting chip400-2includes the pixel values d800 to d001 arranged in a time series in descending order of the index that are read out in the reverse direction from the line memory724-2. By outputting the pixel values read out from the memory in the reverse order in this manner for the light-emitting chips400arranged in the reverse direction orientation, the photosensitive body102can be exposed with light such that the images of each line are appropriately represented.

(4) MODIFIED EXAMPLES

In a modified example of the embodiment described above, each line memory724of the data storage unit723may include additional capacity that can be used for compensating for the effects of implementation misalignment of each light-emitting chip400along the second direction D2. In addition, the chip arrangement information written to the storage unit810of the printed substrate202may include third control information indicating the degree of implementation misalignment of each light-emitting chip400measured in the test phase after manufacture. The degree of implementation misalignment, for example, may be represented by an integer value indicating how many times the line period the output timing of the partial image data to each light-emitting chip400should be additionally delayed.

FIG.16is a timing chart illustrating an example of output timings of partial image data from the data conversion unit802according to such a modified example. Herein, the chip arrangement is the even-numbered-downstream arrangement. The third control information obtained from the storage unit810indicates that the light-emitting chip400-3has been misaligned by an amount equal to one line period to the downstream side.

First, in the line period from time T0to T1, the signal sequence LN01-1for the light-emitting chip400-1of the first line is output. At this time, the signal sequence LN01-3for the light-emitting chip400-3of the first line is not output. In the next line period from time T1to T2, the signal sequence LN02-1for the light-emitting chip400-1of the second line and the signal sequence LN01-3for the light-emitting chip400-3of the first line are output. On the other hand, the signal sequences for the light-emitting chips400-2and400-4are not output until time T40is reached in accordance with the chip position information.

According to this modified example, the effects of implementation misalignment of each light-emitting chip400along the second direction D2, which is the rotation direction of the photosensitive body102, is compensated for by delay control of output timings of respective pieces of data, so that a decrease in image quality due to implementation misalignment can be avoided.

6. PROCESSING FLOW

FIG.17is a flowchart illustrating an example of a flow of the exposure control processing that can be executed in the present embodiment. The exposure control processing inFIG.17can be executed by the data conversion unit802of the image controller800. Note that herein, processing step is abbreviated to “S”.

First, in S11, the memory control unit726of the data conversion unit802obtains the chip arrangement information read out by the CPU811from the storage unit810of the exposure head106connected to the image controller800. The chip arrangement information includes the chip position information and the chip orientation information.

Next, in S12, the memory control unit726determines if the odd-numbered light-emitting chips, from among the plurality of light-emitting chips400arranged in a staggered manner in the exposure head106, are positioned on the downstream side based on the chip position information. When the odd-numbered light-emitting chips are on the upstream side, the processing proceeds to S13. When the odd-numbered light-emitting chips are on the downstream side, the processing proceeds to S15.

In S13, the memory control unit726allocates a first amount of memory resources of the data storage unit723to each odd-numbered light-emitting chip400located on the upstream side. Next, in S14, the memory control unit726allocates a second amount of memory resources of the data storage unit723to each even-numbered light-emitting chip400located on the downstream side. In this example, the second amount is larger than the first amount.

In S15, the memory control unit726allocates the second amount of memory resources of the data storage unit723to each odd-numbered light-emitting chip400located on the downstream side. Next, in S16, the memory control unit726allocates the first amount of memory resources of the data storage unit723to each even-numbered light-emitting chip400located on the upstream side. In this example as well, the second amount is larger than the first amount.

Thereafter, in S17, the processing on the input image data is started, and the data dividing unit721divides one line of the input image data into K pieces of partial image data. The data dividing unit721writes the K pieces of partial image data to the corresponding line memories724of the data storage unit723via the input selection unit722in accordance with the memory resource allocation by the memory control unit726. In S18, the data storage unit723buffers the partial image data for the light-emitting chips on the downstream side. Buffering of the partial image data may be continued for an interval corresponding to the chip gap L2. For the partial image data for the light-emitting chips on the upstream side, the buffering in S18may not be performed. In S19, the output selection unit725, under control by the memory control unit726, reads out pieces of the partial image data at respective output timings from the corresponding line memory724and outputs them to the corresponding light-emitting chips400. At this time, the output selection unit725reverses the order of reading out pixel values from the line memory724as necessary based on the chip orientation information.

Thereafter, in S20, the memory control unit726determines whether output for all of the lines of the input image data has ended. In a case where there remains a line that has not been output, the processing returns to S17, and S17to S19are repeated for the next line. In a case where there remains no line that has not been output, the exposure control processing inFIG.17ends.

Various embodiments have been described in detail usingFIGS.1to17. According to the embodiments described above, the exposure control apparatus controls the exposure of the photosensitive body by the exposure head including the K light-emitting chips arranged in a staggered manner along a direction parallel to the rotation axis of the photosensitive body. The exposure control apparatus includes a set of memory resources that temporarily store K pieces of partial image data constituting the image data of each line of an input image. Then, the exposure control apparatus described above controls memory resource allocation to the K light-emitting chips based on the first control information indicating whether the odd-numbered light-emitting chips or the even-numbered light-emitting chips are arranged on the downstream side. Variably allocating memory resources in this manner can remove the need to associate memory resources with a large uniform capacity to all of the light-emitting chips and can suppress an increase in the manufacturing costs of the apparatus. At the same time, the manufacturer will be allowed to provide any one of the odd-numbered light-emitting chips and the even-numbered light-emitting chips on the downstream side in a staggered arrangement. Thus, flexibility in the arrangement of the light-emitting chips in the exposure head is ensured. This contributes to enhancement of reusability of components among products of different types and makes it easier for the manufacturer of image-forming apparatuses to cater to various needs of the market.

In the embodiments described above, based on the first control information, the first amount of memory resources is allocated to each light-emitting chip determined to be arranged on the upstream side and the second amount, larger than the first amount, of memory resources is allocated to each light-emitting chip determined to be arranged on the downstream side. Accordingly, appropriate delay control of output timings of the partial image data can be performed, and the required amount of memory resources for the delay control can be reduced.

In the embodiments described above, the difference between the first amount of memory resources allocated to the light-emitting chips on the upstream side and the second amount of memory resources allocated to the light-emitting chips on the downstream side is based on the number of line periods that advance between points in time of outputting data to the light-emitting chips. By deciding the amount of memory resources to be allocated in this manner, the memory resources allocated to each light-emitting chip are utilized to the maximum, and waste in memory resources is removed.

In the embodiments described above, the exposure control apparatus obtains the control information which has been written in the storage unit of the exposure head by an external apparatus. Accordingly, as long as the appropriate control information has been written in the storage unit of the exposure head, the exposure control apparatus can perform exposure control suitable for the chip arrangement employed in that exposure head.

In the embodiments described above, the exposure control apparatus may control the order of reading out pixel values constituting the partial image data when outputting the partial image data from the memory resources based on the second control information indicating the implemented orientation of each of the K light-emitting chips. By controlling the order of reading out pixel values in this manner, it will be possible to arrange light-emitting chips of the same type in any orientation in the exposure head, allowing the reusability of components to be further enhanced.

In the embodiments described above, specific numerical values have been used for description, but these specific numerical values are examples. The disclosure is not limited to the specific numerical values used in the embodiments. For example, the number of light-emitting elements arranged in the first direction in one light-emitting chip is not limited to 800, and any number equal to or larger than one can be used. Also, the pitch of the light-emitting elements is not limited to 21.16 μm, and any other value can be used. Also, the chip gap is not limited to approximately 846.4 μm, and any other value can be used.

8. OTHER EMBODIMENTS

This application claims the benefit of priority from Japanese Patent Application No. 2022-177362, filed on Nov. 4, 2022, which is hereby incorporated by reference herein in its entirety.