Mixer with shorting switch

A double-balanced mixer is provided having a shorting switch connecting the signal inputs to the mixer core. A timer circuit provides pulses to close the switch, thereby shorting those inputs at times when the switches of the mixer core are switching. This is done because non-linear components in the output are produced at those times and therefore they can be removed if the signal input is shorted at those times.

The present invention relates to double-balanced mixers used in modulators and demodulators, especially linear modulators for wireless communications.

BACKGROUND OF THE INVENTION

Modulators for wireless transmission schemes such as EDGE or WCDMA, in which part or all of the information is carried in the signal amplitude, need to be linear. Non-linearity causes transmission in frequencies outside the intended channel, causing interference in neighbouring channels. These problems are acute in modulators providing relatively high power outputs, where large signal currents cannot be switched instantaneously.

A typical double-balanced mixer1, commonly used in a linear modulator, is shown inFIG. 1. A pair of nodes2and3is provided as an input for a differential modulating signal. The latter is marked as voltage Viand −Vibeing applied to2and3, respectively. Another pair of nodes7and8is provided as an input for a local oscillator signal. In the remainder of the text we will refer to the local oscillator signal actually applied to nodes7and8as the clock signal. This facilitates the description of the various versions of the local oscillator signal typically found in a modulator, such as the signals generated by the local oscillator or synthesizer (the LO signal), its phase shifted and possibly frequency-divided versions, and the final in-phase (I) and quadrature (Q) switching signals at the radio carrier frequency that actually open and close the commutating switches in a double balanced mixer. The output of the double-balanced mixer is also in differential form and is provided by nodes10and11. A first pair of transistors M1and M2, having their source terminals connected to node4, gate terminals respectively connected to2and3, and drain terminals respectively connected to nodes5and6, form a transconductor to convert the differential signal Viinto a differential current signal i. InFIG. 1the said differential current signal is marked together with the bias current IB(connected between node4and ground) as IB/2+i for node5and IB/2−i for node6. A second pair of NMOS transistors M3and M4have their sources connected to node5and their drains respectively connected to outputs10and11. A third pair of NMOS transistors M5and M6have their sources connected to node6and their drains respectively connected to outputs10and11. A pair of clock signals LO+and LO−in antiphase is provided by a local oscillator9(or clock generator9if it receives the local oscillator signal and generates the clocking signals with appropriate phasing and delays). These are applied respectively to input nodes7and8of the double balanced mixer and used to open and close its switches, which are typically provided as MOSFET or BJT transistors and shown here as M3, M4, M5and M6. Clock signal LO+at node7is connected to the gates of transistors M3and M6, while clock signal LO+at node8is connected to the gates of transistors M4and M5. Since the clocks are in anti-phase transistors M3and M6are generally on while transistors M4and M5are off, in which state node5is connected to output node10via M3and node6is connected to output node11via M6, and vice versa, in which state node5is connected to node11via M4and node6is connected to node10via M5.

Ideally the transitions between the said two states should be instantaneous, so that mathematically the four commutating switches M3, M4, M5and M6, referred to as the mixer core, serve to realize a multiplication of the input current i by an alternating sequence of 1s and −1s at the frequency of the clock signal. In practical implementations, however, the transition time τ between the two states is non-zero and depends both on the dimensions of the switches and the magnitude of the current being switched. During the transition all four transistors M3, M4, M5and M6are on and harmonics of the signal current i are created in the output. With dimensions of the switching transistors limited by speed and noise considerations in a particular application, increasing magnitude of the signal current will result in increasing transition time τ, and consequently nonlinearity of the mixer core.

SUMMARY OF THE INVENTION

According to the present invention there is provided a mixer and a method of mixing as defined in the appended claims.

The invention substantially reduces the nonlinearity caused by switching transitions in double balanced mixers. By blanking out the output of the mixer core by shorting the inputs during the transition times no harmonics of the signal current will be created in the output. Any reduction of signal gain due to blanking is outweighed by improved mixer linearity and larger input signal that the mixer core is capable of processing.

DETAILED DESCRIPTION

FIG. 2is a circuit diagram of a first example of a circuit according to the invention. The circuit is a double balanced mixer similar to that ofFIG. 1. It has the same inputs2and3for the differential input signal, inputs7and8for anti-phase clocks, differential outputs10and11, a pair of transistors M1and M2forming a transconductor and four switching transistors M3, M4, M5and M6forming the mixer core, all having the same connections to those inputs and outputs. According to the present invention, the circuit has in addition a further switch transistor M7connected between nodes5and6, which nodes serve both as the differential output of the transconductor and the differential input of the mixer core. Switch M7is controlled to open and close by a control and clock generation circuit9. The control and clock generation circuit is connected to receive the local oscillator signals LO and in response to provide both clock signals LOI+LOI−(being a delayed version of the local oscillator signals LO) for the mixer core and pulses that cause switch M7to close for the transition period when the transistors M3, M4, M5and M6are switching.FIG. 3illustrates the timing of one set of clock signals (LOI+, LOI−) relative to the shorting pulses provided by control and clock generation circuit9, as well as an example of their combined effect on the differential output current ioutof the double balanced mixer. In many applications an additional set of clock signals and shorting pulses are generated for a second double balanced mixer. This is optionally and preferably provided by the same control and clock generation circuit9, as shown in dotted form inFIG. 2.

The closing of switch M7shorts nodes5and6, which are the input terminals to the mixer core. This causes the differential signals i+, i−to cancel each other out and the shorted node is then driven by the sum (IB) of the drain currents of M1and M2, which equals their shared bias current. This combined current then passes through the mixer core, each of the two outputs receiving an equal share due to the symmetry between transistors M3and M6(they share the same gate and source voltages) and that between M4and M5(for the same reason).

These output currents being equal of course means that their difference—the differential output is zero and neither the signal nor its harmonics appear in the mixer response during these periods. The blanking of the signal during these periods means that the mixer core now effectively multiplies the signal current by an alternating sequence of 1s and −1s, separated by zeros, as illustrated also inFIG. 3. The resulting duty cycle reduction of the 1s and −1s reduces the gain of the mixer so there is a trade off between loss of gain and improved linearity.

The control and clock generation circuit needs to be fairly accurate in its timing with regard to when the shorting switch is closed relative to when the transistors of the mixer are switching but inaccuracies are tolerable. If the shorted period extends into the state when the switches have switched and are full on or off then gain is sacrificed; if the period is too short and there is no shorting during some of the period when the non-linearity is generated then the reduction of the non-linearity will be less effective.

The control signal for switch M7could be generated in various ways. Two suitable circuits are described later below. In these examples and as shown inFIG. 4the control circuit9generates both the shorting pulses that control M7and the clock signals that control switches of the mixer core. It would also be entirely possible for the local oscillator signals LO to be applied directly to the mixer core switches and arrange the control circuit9to provide the shorting pulses both in response to and aligned with the local oscillator signals LO.

FIG. 4shows a second example of a circuit according to the invention. This is similar to the first example except that a pair of inductors L1and L2have been inserted between the transconductor output (drain terminals of M1and M2, which are now marked as13and14, respectively) and the input to the mixer core (marked5and6as before). This overcomes a potential limitation of the first example. The transconductor may require large transistors, for example large gate widths for M1and M2, in order to carry substantial current without significantly compromising the output voltage range. As a consequence the parasitic capacitances associated with the output connections of the transconductor, marked as CD1and CD2inFIGS. 2 and 4and shown as dotted to highlight their spurious nature, may also become too large for the blanking scheme outlined in the previous example to function effectively as may be desired. When the shorting switch is closing the said parasitic capacitors do not affect the shorting of the two nodes because the charges on them can redistribute quickly to allow their voltages to become equal with relatively little influence from the current sources.

After the shorting pulse transistor M7opens and nodes5and6become separated again. Signal current needs to be established in the pair of switches that are conducting after the transition, each of which carried half the bias current immediately before the end of the shorted period. This requires node5and node6inFIG. 2to resume the voltages appropriate for carrying the corresponding signal currents, which in turn requires CD1and CD2each to be charged by part of the corresponding transconductor output current. During such voltage resumption process that is input signal dependent, the said charging current is diverted from the corresponding conducting switch and goes missing from the desired output current. Secondary distortion may thus be introduced into the output.

The inductors introduced in the second example mitigate the voltage resumption problem by shielding CD1and CD2from the input of the mixer core that is periodically shorted. Acting as short-term current memories inductors L1and L2each absorbs the voltage jump at the corresponding mixer core input node5or6, while keeping the voltages on CD1(now connected between node13and ground) and CD2(now connected between node14and ground) substantially unchanged during the closing of M7. While large value inductors generally perform the said current memory/voltage isolation function better, small inductors (from a few to tens of nanohenries) easily realizable as spirals in an integrated circuit can already be very effective at frequency ranges specified for popular wireless applications such as EDGE, WCDMA and wireless LAN. In integrated circuit realizations spiral inductors L1and L2may be constructed to maximize the mutual inductance between them (i.e. forming a mutual inductor) so as to increase the effective value of each self-inductance for differential input currents, for example by integrating them overlaid.

There are two aspects to the shorting pulses that control the closing of transistor M7. The first is the alignment of the said pulses to both the rising and the falling edges of the clock signal and the second is a brief yet controlled duration for each pulse. There are a number of ways to construct a circuit that fulfils the requirements.

FIG. 5ashows a first example of the control and clock generation circuit of the circuit ofFIGS. 2 and 4that generates both the clock signals and the shorting pulses, which are correctly aligned with one another for the purpose of the present invention. InFIG. 5a, control and clock generation circuit9receives a local oscillator signal LO at its input (node901) and provides a first output PIof shorting pulses at node902, a second output LOI at node903for opening and closing the switches in the mixer core of the double balanced mixer1. Optionally, a third output PQof shorting pulses is provided at node904and a fourth output LOQ is provided at node905for opening and closing the switches in the mixer core of a second double balanced mixer as may be required in a linear quadrature modulator.

A phase shifting circuit6is provided that generates a first signal I at node906and a second signal Q at node907from the said LO signal. Both I and Q are at the desired carrier frequency used to switch the double-balanced mixers but are shifted from each other in phase such that both the rising and falling edges of either I or Q can be extracted using an exclusive-or logic. Known quadrature phase generators used to create clock signals in a quadrature modulator, in which the I signal is shifted nominally by 90° (quarter of the period) ahead of the Q signal, can be used for the said phase shifting circuit16. According to one aspect of the present invention an exclusive-nor (XOR_B) logic gate, which receives signals I and Q respectively at its input nodes906and907, is used to detect both the rising and falling edges of I and convert them to falling edges in its output IFat node908, as illustrated inFIG. 5b. A pulse duration circuit17receives the XOR_B output IF, detects its falling edges and provides an output of pulses of desired duration that are synchronized to the said falling edges. In the example shown inFIG. 5athe pulse duration circuit17consists of a NOR gate receiving IFon a first input at node908while its output PIat node902is delayed by two delay elements (shown inFIG. 5aas a cascade of two inverters), then fed back to the second input of the NOR gate (node909), whose delay is preferably substantially smaller than those of the delay elements. The delay of each inverter is preferably set to τ/2, so that the resulting pulse duration τ is the expected transition time between the +1 state and −1 state of a double balanced mixer. To match the centre of PIto the switching transition of the clock signal LOI at node903, the I output of the phase shifting circuit6is preferably delayed by an exclusive-nor gate (receiving I on its first input at node906and a logic one on the other) matching that used for edge detection, followed by a NOR gate (receiving the output of the exclusive_nor gate on its first input and a logic zero on the other) matching that in the pulse duration circuit17, and finally by the delay element between node910(input of the delay element and output of the NOR gate) and node903(output of the delay element) that is nominally identical to either of the two delay elements in the pulse duration circuit17. Both PIand the clock signal LOI at node903are illustrated inFIG. 5b, where the rising edge of LOI is centred between the rising and falling edges of PI. The optional circuit8for generating the quadrature clock signal LOQ at node905and the corresponding shorting pulses PQat node904is similar to those boxed within5, except the roles of I and Q inputs are exchanged and that the exclusive-nor gates are replaced by exclusive-or (XOR) gates.

FIG. 6ashows a second example of the control and clock generation circuit. Generally it again consists of a phase shifting circuit16, an edge detection circuit14and a pulse duration circuit17. It enables full advantage to be taken of quadrature clock generator circuits typically already in place in quadrature modulators so that the additional hardware and power consumption for generating shorting pulses, which can be significant at radio frequencies, are kept low. The phase-shifting circuit16inFIG. 6ais based on a well-known master-slave flip-flop, three examples of which are shown inFIG. 6bwith NOR gates,FIG. 6cwith NAND gates andFIG. 6demploying inverters and transmission gates, respectively. Mater slave latches per se are, of course, well known to the skilled person and as can be seen each of the master and slave latches comprise a gating portion controlled by the clock signal and a latching portion comprising cross coupled gates.

Returning to their use in the invention, inFIG. 6b, for example, four NOR gates on the left half of the circuit form the master latch receiving the clock input CK on node601and the differential output of the slave latch (formed by the four NOR gates on the right hand half of the circuit) Q and Qb (which is also the output of the overall flip-flop) on its differential input nodes602and603, respectively, and provides a differential output I and Ib, on nodes604and605, respectively. The slave latch receives I and Ib, on its input nodes604and605as well as the inverse of CK, CKb, on its clock input node606. The feedback of the flip-flop output to its (inverted) input makes it toggle upon the rising edges of the clock so that the output Q of the flip-flop is a square wave at double the period, or half the frequency, of the clock. Symmetry dictates that the master latch output I is of the same waveform as Q except that the toggling is triggered at falling clock edges, half a clock period before Q, or a quarter of the toggling period.FIG. 7illustrates the timing relationship between the clock signal CK, the quadrature output Q and the in-phase output I. In standard quadrature modulators the local oscillator signal is often generated at twice the carrier frequency and applied to the CK input of the toggle flip-flop, and the differential outputs of the master stage, I, Ib, and those of the slave stage, Q, Qb, both at the carrier frequency, are the only signals of interest. In these examples signals at the internal nodes of the master latch, A at607and B at608, and those of the slave latch, C at609and D at610, are also provided as the outputs of the phase shifting circuit to simplify the realization of the edge detection and pulse duration circuits.

The edge detection circuit14receives I, Ib, A and B respectively at its four inputs604,605,607and608and provides an output PIDat node803, as shown inFIG. 8a. Similarly a second copy of the edge detection circuit (seeFIG. 6a), when needed, receives Q, Qb, C and D at its inputs (signal names and corresponding connections to those inFIG. 6aare marked in brackets inFIG. 8a) and provides an output PQD. Two examples of the realization of the edge detection circuit14are given inFIGS. 8band8c, respectively.

The edge detection example inFIG. 8bcomprises a first AND logic gate, connected to receive I on its first input on node604and A on its second input on node607, and to provide an output P1on node801; a second AND gate, connected to receive Ib on its first input on node605and B on its second input on node608, and to provide an output P2on node802; an OR logic gate (shown inFIG. 8bas a NOR gate followed by an inverter buffer) is connected to receive P1and P2respectively on its inputs at801and802and to provide an output PIDat node803. Because the phase-shifting circuit output I is only a slightly delayed inversion (inFIG. 6bby a NOR gate, for example) of A, the said output P1rises on the rising edge of A and falls on the corresponding falling edge of I, and remains zero otherwise. Similarly P2rises on the rising edge of B (occurring at about the same time as the falling edge of A) and falls on the corresponding falling edge of Ib (occurring at about the same time as the rising edge of I), and remains zero otherwise. The edge detector output PID, being the sum (logic OR) of P1and P2, therefore contains narrow impulses aligned with both the rising and the falling edges of I, as illustrated also inFIG. 7.

The circuit ofFIG. 8cis an alternative to that ofFIG. 8band provides the same function but uses NOR gates instead of AND gates.

To convert such impulses into pulses of defined duration an edge triggered delay (ETD) element is required for the pulse duration circuit17, as shown inFIG. 9a. The said pulse duration circuit comprises an ETD circuit connected to receive the edge detection circuit output PIDon'its first input at node803, the reset signal on its second (reset) input at node901and to provide a logic 1 in its output PIat node902in response to each rising (or each falling) edge in PIDand a logic zero in PIin response to each reset signal on the second input; a delay circuit connected to receive PIon its input at node902and in response to provide a delayed replica of PIat its output on node901.FIG. 9bshows an example of the realization of the said ETD circuit, which comprises a D-flip-flop receiving a logic 1 at its D input, its clock input providing a first input node803, its reset input providing a second input node901and its output providing the ETD output PIat node902.

Although the diagrams inFIGS. 9aand9bgive a working example and clearly illustrate the concepts of the second example of the pulse duration generation, in practical realizations many simplifications are possible to merge the edge detection circuit14and pulse duration circuit17into a single schematic with fewer transistors.FIG. 9cillustrates an example of such simplification. There is provided a first NMOS transistor MN1with its source terminal connected to ground, its gate terminal providing a first input for the edge detection circuit14inFIG. 6a, its drain terminal connected to node911; a second NMOS transistor MN2with its source terminal connected to node911, its gate terminal providing a second input for14, its drain terminal connected to node912; a third transistor MN3with its source terminal connected to ground, its gate terminal providing a third input for14and its drain terminal connected to node913, a fourth transistor MN4with its source terminal connected to node913, gate terminal providing a fourth input for14and its drain terminal connected to node912. The said first and second inputs are used to receive A and I outputs of the phase shifting circuit16inFIG. 6a. Both pairing A to first input, I to second input or vice versa achieve the same objective. Similarly the third and fourth inputs are used to receive B and Ib. There is also provided a first PMOS transistor MP1with its source terminal connected to the voltage supply VDD, its gate terminal connected to node914and its drain terminal connected to node912; a second PMOS transistor MP2with its source terminal connected to VDD, its gate terminal connected to node912and its drain terminal connected to node915that provides the output PIof the pulse duration circuit17ofFIGS. 6aand9a; a fifth NMOS transistor MN5with its source terminal connected to ground, its gate terminal connected to node912and its drain terminal connected to node915; and a sixth NMOS transistor MN6with its source terminal connected to ground, its gate terminal connected to node916that provides the reset input ofFIGS. 9aand9band its drain terminal connected to node915; a first logic inverter INV1having its input connected to node915and its output connected to node917; a second logic inverter INV2having its input connected to node917and its output connected to node916; and a third logic inverter INV3having its input connected to node916and it output connected to node914.

Each time the output PIon node915rises from logic zero to logic one, it is followed by node916rising to logic one after a delay of τ (twice τ/2), causing transistor MN6to conduct and resetting PIto logic zero. Node916continues to be high for a period of τ until the logic zero of PIpropagates through delaying inverters INV1and INV2, during which period transistor MP1is on, charging node912and setting its voltage Y to logic one, turning on MN5and turning off MP2at the same time. Once node916follows PIto logic zero MN6is turned off and the output of INV3rises to logic one, turning off MP1. As long as inputs I, A, Ib, and B are not in transition, paths through MN1and MN2, MN3and MN4, as well as MP1are in high impedance state and the charge stored on the Parasitic capacitance (marked in dotted form as CY) at node912will keep Y at logic one, which keeps PIlatched to logic zero through the inverter formed by MN5and MP2. Either the rising transition of A followed by the falling transition of I or the rising transition of B followed by the falling transition of Ib (hence the rising transition of I) will short node912to ground through either MN1and MN2because of the brief moment during which both A and I are high or MN3and MN4because of the brief moment during which both B and Ib are high. The shorting of912to ground causes node915to rise through the inverter formed by MP2and MN5, which sets PIto logic one, and the subsequent events will continue as have been described at the beginning of the present paragraph.

The delay inFIG. 6bbetween B rising to logic one (A falling to logic zero), followed by Ib falling to logic zero, and I subsequently rising to logic one is the sum of two inversion delays by NOR-gate. InFIG. 9cthe delay between A (or B) rising to logic one, Y falling to logic zero and PIrising to logic one is also the sum of two inversion delays by NOR gate. Hence the rising (and falling) edges of I are aligned with those of PI. Delaying I by one inverter matched to INV1(or INV2) to generate LOI therefore will centre each of the latter's rising edges in the middle of the corresponding pulse in PI.

In the above examples the edge detector has used I and Q versions of the oscillator signals. If they are not being used (and it is not desired to add a phase shifting network to generate them) the control circuit can comprise an edge detector that is responsive to just a single phase of the local oscillator signals; this would comprise, for example, two edge detectors respectively for detecting the positive and negative going edges of the local oscillator signal and ORing together their outputs.

InFIGS. 5 through 9standard logic and circuit symbols in single ended notation have been used to illustrate the underlying ideas of the present invention. It will be clear to those skilled in the art, however, that the same ideas can be easily realized using differential or pseudo-differential logic, which is especially preferable in radio frequency applications.