Output buffer circuit

An output buffer circuit of the invention comprises a first output transistor connected between a power supply potential node and an output node, a second output transistor connected between a ground potential node and the output node, a first control circuit for controlling a conductive state of the first output transistor, a first clamp circuit for supplying a given potential to a first node to which the first control circuit is connected, a control circuit for controlling a conductive state of the second output transistor, and a second clamp circuit for supplying a given potential to a second node to which the second control circuit is connected. The first clamp circuit supplies a given potential to the first node when the first control circuit is inactivated, and stops the supply of the given potential when the first control circuit is activated. The second clamp circuit supplies a given potential to the second node when the second control circuit is inactivated, and stops the supply of the given potential when the second control circuit is activated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an edge rate control type output buffer circuit.

2. Description of the Related Art

An output buffer circuit has been described in a literature entitled “Design Guide For A Low Speed Buffer For The Universal Serial Bus” Revision 1.1 December 1996 by Intel Corporation as a conventional edge rate control type output buffer circuit. The conventional output buffer circuit is a CMOS output buffer circuit that is used as a buffer circuit of a USB (Universal Serial Bus).

This conventional output buffer circuit has a PMOS transistor and an NMOS transistor, connected to an output pad, respectively, as an output transistor. The PMOS transistor is controlled in a conductive state by an amplifier. The NMOS transistor is controlled in a conductive state by an amplifier that is different from the amplifier for controlling the PMOS transistor. These two amplifiers are controlled in operation respectively, in response to an enable signal. Inverted input terminals of these two amplifiers are connected to a bias circuit, respectively, and a given bias potential is supplied to these amplifiers. Non-inverted input terminals of these two amplifiers are commonly connected to each other. The common connection node is connected to a clamp circuit and a given potential is always supplied to the common connection node. A feedback capacitor element is connected between the common connection node and an output pad. The conventional output buffer circuit having the foregoing structure controls a throughput rate of an output waveform at the rising edge and the throughput rate of the output waveform at the falling edge (hereinafter referred to simply as rising edge rate and falling edge rate).

However, there is a case where the conventional output buffer circuit can not satisfy an AC standard of a USB, particularly, VCRS (crossover voltage) standard owing to change of operational environment such as variation of a power supply potential, change of an operational temperature or the like. There are following two reasons. One reason is that there occurs distortion in an output waveform because a given bias potential is always supplied to a common node. The second reason is that there occurs a distortion in an output waveform owing to influence of current which flows into through a pull-up resistor in the case where the conventional output buffer circuit is used as a low speed buffer of the USB.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an output buffer circuit capable of realizing interface which outputs waveforms having a given edge rate even if an operational environment is changed.

To achieve the above object, the output buffer circuit of the invention comprises a first output transistor connected between a power supply potential node and an output node, a second output transistor connected between a ground potential node and the output node, a first control circuit for controlling a conductive state of the first output transistor, a first clamp circuit for supplying a given potential to a first node to which the first control circuit is connected, a second control circuit for controlling a conductive state of the second output transistor, and a second clamp circuit for supplying a given potential to a second node to which the second control circuit is connected.

The first clamp circuit supplies a given potential to the first node when the first control circuit is inactivated, and stops the supply of the given potential when the first control circuit is activated.

The second clamp circuit supplies a given potential to the second node when the second control circuit is inactivated, and stops the supply of the given potential when the second control circuit is activated.

PREFERRED EMBODIMENT OF THE INVENTION

First Preferred Embodiment

A first embodiment of the invention is now described.FIG. 1is a circuit diagram of an output buffer circuit according to the first embodiment of the invention. The output buffer circuit of the first embodiment comprises an output node101, a first output transistor P4(hereinafter referred to as output transistor P4) and a second output transistor N4(hereinafter referred to as output transistor N4), a first control circuit102for controlling a conductive state of the output transistor P4(i.e., the amount of current which flows from a power supply potential node to the output node101through the output transistor P4), a second control circuit103for controlling a conductive state of the output transistor N4(i.e., the amount of current which flows from the output node101to a ground potential node through the output transistor N4), a first capacitor element C1(hereinafter referred to as capacitor element C1) for controlling a rising edge rate, a second capacitor element C2(hereinafter referred to as capacitor element C2) for controlling the falling edge rate, a first current source104(hereinafter referred to as current source104) connected between a first node (node SUMP) and the ground potential node, a second current source105(hereinafter referred to as current source105) connected between a second node (node SUMN) and the power supply potential node, a first clamp circuit CL1(hereinafter referred to as clamp circuit CL1) for supplying a given potential to the node SUMP, a second clamp circuit CL2(hereinafter referred to as clamp circuit CL2) for supplying a given potential to the node SUMN, a switch element P3for connecting between a node PDRV and the power supply potential node when the first control circuit102is in “inactive state”, and a switch element N3for connecting between a node NDRV and the ground potential node when the second control circuit103is in “inactive state”.

The output transistor P4is made up of a P-channel MOS transistor (hereinafter referred to as PMOS transistor) comprising a source (first electrode) connected to a power supply potential node to which a power supply potential VCC is supplied, a drain (second electrode) connected to the output node101, and a gate (control electrode) connected to the first control circuit102. The output transistor N4is made up of an N-channel MOS transistor (hereinafter referred to as NMOS transistor) comprising a source (first electrode) connected to a ground potential node to which a ground potential GND is supplied, a drain (second electrode) connected to the output node101, and a gate (control electrode) connected to the second control circuit103.

The first control circuit102is made up of an amplifier comprising an input terminal DM (first input terminal) connected to the node SUMP, an input terminal DP (second input terminal) to which a bias potential is supplied, an output terminal connected to the gate of the output transistor P4, and an enable terminal EN (control terminal) to which a first enable signal P_EN (first control signal) representing enable/disable of operation is applied. The bias potential to be supplied to the input terminal DP is one half of the power supply potential VCC (hereinafter represented by VCC/2). The first enable signal P_EN to be inputted to the enable terminal EN represents enable of operation of the first control circuit102at “H” (first logical level) while it represents disable of operation of the first control circuit102at “L” (second logical level). The first control circuit102is activated in response to the first enable signal P_EN of “H” while it is in inactivated in response to the first enable signal P_EN of “L”. The first control circuit102is hereinafter referred to as amplifier102.

The amplifier102is now described more in detail.FIG. 2is a circuit diagram showing the structure of the amplifier102. The amplifier102comprises a first current mirror circuit201, a second current mirror circuit202, a first input transistor N21(hereinafter referred to as input transistor N21) that is connected between a current input side of the first current mirror circuit201and the ground potential node, a second input transistor P21(hereinafter referred to as input transistor P21) that is connected between a current input side of the second current mirror circuit202and the power supply potential node, a first node (node n1) to which a current output side of the first current mirror circuit201and a current output side of the second current mirror circuit202are connected, a first resistor element P24connected between the node n1and the power supply potential node, a second resistor element N24connected between the node n1and the ground potential node, an inverter INV203, switch elements P25and P26operable in response to an inversion signal of the enable signal P_EN, and switch elements N25and N26operable in response to the enable signal P_EN.

The first current mirror circuit201comprises a PMOS transistor P22and a PMOS transistor P23. The PMOS transistor P22is the current input side of the first current mirror circuit201. The PMOS transistor P23is the current output side of the first current mirror circuit201. A source of the PMOS transistor P22is connected to the power supply potential node through the switch element P25, a drain thereof is connected to the input transistor N21, and a gate thereof is connected to a drain of a PMOS transistor P22and a gate of the PMOS transistor P23. A source of the PMOS transistor P23is connected to the power supply potential node through the switch element P25, a drain thereof is connected to the node n1, and a gate thereof is connected to the gate of the PMOS transistor P22.

The second current mirror circuit202comprises an NMOS transistor N22and an NMOS transistor N23. The NMOS transistor N22is the current input side of the second current mirror circuit202. The NMOS transistor N23is the current output side of the second current mirror circuit202. A source of the NMOS transistor N22is connected to the ground potential node though the switch element N25, a drain thereof is connected to the input transistor P21, and a gate thereof is connected to a drain of the NMOS transistor N22and a gate of the NMOS transistor N23. A source of the NMOS transistor N23is connected to the ground potential node through the switch element N25, a drain thereof is connected to the node n1, and a gate thereof is connected to the gate of the NMOS transistor N22.

The input transistor N21is made up of an NMOS transistor. A source of the input transistor N21is connected to the ground potential node through the switch element N26, and a drain thereof is connected to a drain of the PMOS transistor P22forming the current input side of the first current mirror circuit201, and a gate thereof is connected to the input terminal DM. The input transistor P21is made up of a PMOS transistor. A source of the input transistor P21is connected to the power supply potential node through the switch element P26, a drain there of is connected to a drain of the NMOS transistor N22forming the current input side of the second current mirror circuit202, and a gate thereof is connected to the input terminal DM.

The first resistor element P24is made up of a PMOS transistor. The first resistor element P24is hereinafter referred to as a transistor P24. A source of the transistor P24is connected to the power supply potential node through the switch element P26, a drain thereof is connected to the node n1and a gate thereof is connected to the input terminal DP. The second resistor element N24is made up of an NMOS transistor. The second resistor element N24is hereinafter referred to as a transistor N24. A source of the transistor N24is connected to the ground potential node through the switch element N26, a drain thereof is connected to the node n1, and a gate thereof is connected to the input terminal DP. The bias potential VCC/2 is supplied to the input terminal DP.

Both the switch element P25and switch element P26are made up of a PMOS transistor, respectively, and they are controlled to turn ON or OFF in response to an inversion signal of the enable signal P_EN to be inputted to the enable terminal EN. Both the switch element N25and switch element N26are made up of an NMOS transistor, respectively, and they are controlled to turn ON or OFF in response to the enable signal P_EN. The node n1is connected to the output terminal.

The second control circuit103is made up of an amplifier comprising an input terminal DM (first input terminal) connected to the node SUMN, an input terminal DP (second input terminal) to which a bias potential is supplied, an output terminal connected to a gate of the output transistor N4, and an enable terminal EN# (control terminal) to which a second enable signal N_EN# (second control signal) representing enable/disable of operation. The bias potential to be supplied to the input terminal DP is VCC/2. Further, the enable signal N_EN# to be inputted to the enable terminal EN# represents enable of operation at “L” (second logical level) while it represents disable of operation at time “H” (first logical level). The second control circuit103is activated in response to the enable signal N_EN# of “L” while it is inactivated in response to the enable signal N_EN# of “H”. The second control circuit103is hereinafter referred to as an amplifier103.

The amplifier103is now described more in detail.FIG. 3is circuit diagram showing the structure of the amplifier103. The difference between the amplifier103and the amplifier102shown inFIG. 2is that the enable signal N_EN# is inputted to a gate of a PMOS transistor forming the switch elements P25and P26, and an inversion signal of the enable signal N_EN# is inputted to a gate of an NMOS transistor forming the switch elements N25and N26. The other configuration of the amplifier103is the same as that of the amplifier102.

The capacitor element C1is connected between the output node101and the node SUMP. The capacitor element C2is connected between the output node101and the node SUMN.

The current source104comprises a first resistor element (resistor means) R1and a first switch element N2which are serially connected to each other between the node SUMP and the ground potential node. The first resistor element R1is connected between the node SUMP and the first switch element N2. The first resistor element R1is made up of polycrystal silicon. The first switch element N2is made up of an NMOS transistor comprising a source connected to the ground potential node, a drain connected to the first resistor element R1and a gate to which the enable signal P_EN is inputted. A value of current flowing to the current source104is determined by a resistance of the first resistor element R1and an ON resistance of the NMOS transistor forming the first switch element N2. The current source104is in “active state” in response to the enable signal P_EN of “H” (first logical level) to allow a given current to flow. The current source104is in “inactive state” in response to the enable signal P_EN of “L” (second logical level).

Another example of the current source104is illustrated in FIG.4.FIG. 4is a circuit diagram showing another structure of the current source104. Another example of the current source104is made up of a first switch element N2and a first resistor element N1which are serially connected to each other between the node SUMP and the ground potential node. The first switch element N2is made up of an NMOS transistor comprising a source connected to the first resistor element N1, a drain connected to the node SUMP and a gate to which the enable signal P_EN is inputted. The first resistor element N1is made up of an NMOS transistor comprising a source connected to the ground potential node, a drain connected to a source of the NMOS transistor forming the first switch element N2and a gate to which the bias potential NBIASI is supplied. A value of current flowing to the current source104is determined by an ON resistance of the NMOS transistor forming the first switch element N2and an ON resistance of the NMOS transistor forming the first resistor element N1.

The current source105is made up of a second switch element P2and a second resistor element (resistor means) R2which are serially connected to each other between the power supply potential node and the node SUMP. The second switch element P2is made up of a PMOS transistor comprising a source connected to the power supply potential node, a drain connected to the second resistor element R2and a gate to which the enable signal N_EN# is inputted. The second resistor element R2is connected between a drain of a PMOS transistor forming the second switch element P2and the node SUMP. The second resistor element R2is made up of polycrystal silicon. A value of current flowing to the current source105is determined by an ON resistance of the NMOS transistor forming the second switch element N2and a value of resistance of the second resistor element R2. The current source105is in “active state” in response to the enable signal N_EN# of “L” (second logical level) to allow a given current to flow. The current source105is in “inactive state” in response to the enable signal N_EN# of “H” (first logical level).

Another example of the current source105is illustrated in FIG.5.FIG. 5is a circuit diagram showing another structure of the current source105. Another example of the current source105is made up of the second resistor element P1and the second switch element P2which are serially connected to each other between the power supply potential node and the node SUMN. The second resistor element P1is made up of a PMOS transistor comprising a source connected to the power supply potential node, a drain connected to the second switch element P2, and a gate to which the bias potential PBIASI is supplied. The second switch element P2is made up of a PMOS transistor comprising a source connected to the second resistor element P1, a drain connected to the node SUMN, and a gate to which the enable signal N_EN# is inputted. A value of current flowing to the current source105is determined by an ON resistance of the PMOS transistor forming the second resistor element P1and an ON resistance of the PMOS transistor forming the second switch element P2.

The clamp circuit CL1is connected to the node SUMP. The clamp circuit CL1supplies a given potential to the node SUMP when the amplifier102is in “inactive state”, and stops the supply of the given potential when it is in “active state”. More in detail, the clamp circuit CL2supplies the bias potential VCC/2 to the node SUMP when the enable signal P_EN inputted to the enable terminal EN# is “L” while it stops the supply of the same potential when the enable signal P_EN is “H”. The clamp circuit CL1is described more in detail with reference to FIG.6.FIG. 6is a circuit diagram showing the structure of the clamp circuit CL1. The clamp circuit CL1comprises a third resistor element N5connected between the power supply potential node and the node SUMP, a fourth resistor element P5connected between the node SUMP and the ground potential node. The third resistor element N5is made up of an NMOS transistor comprising a first electrode connected to the power supply potential node, a second electrode connected to the node SUMP and a control electrode to which an inversion signal of the enable signal P_EN is inputted. The fourth resistor element P5is made up of a PMOS transistor comprising a first electrode connected to the ground potential node, a second electrode connected to the node SUMP and a control electrode to which the enable signal P_EN is inputted.

The clamp circuit CL2is connected to the node SUMN. The clamp circuit CL2supplies a given potential to the node SUMN when the amplifier103is in “inactive state”, and the stopping the supply of the given potential when it is in “active state”. More in detail, the clamp circuit CL1supplies the bias potential VCC/2 to the node SUMN when the enable signal N_EN# to be inputted to the enable terminal EN is “H” while it stops the supply of the same potential when the enable signal N_EN# is “L”. The clamp circuit CL2is described more in detail with reference to FIG.7.FIG. 7is a circuit diagram showing the structure of the clamp circuit CL2. The clamp circuit CL2comprises a fifth resistor element N6connected between the-power supply potential node and the node SUMN, a sixth resistor element P6connected between the node SUMN and the ground potential node. The fifth resistor element N6is made up of an NMOS transistor comprising a first electrode connected to the power supply potential node, a second electrode connected to the node SUMN and a control electrode to which the enable signal N_EN# is inputted. The sixth resistor element P6is made up of a PMOS transistor comprising a first electrode connected to the ground potential node, a second electrode connected to the node SUMN, and a control electrode to which the inversion signal of the enable signal N_EN# is inputted.

The operation of the output buffer circuit of the first embodiment of the invention is described next with reference to FIG.8(a) to FIG.8(d) showing waveforms generated when the output buffer circuit operates, wherein FIG.8(a) shows levels of the enable signal P_EN and enable signal N_EN #, FIG.8(b) shows the potential of the node SUMP and node SUMN, FIG.8(c) shows potentials of the node PDRV and node NDRV, and FIG.8(d) shows the potential of the output node, wherein the axis of abscissas shows a time, and the axis of ordinates shows a potential.

At time t1, both the enable signal P_EN and enable signal N_EN# become “H” (FIG.8(a)). Since the enable signal N_EN# becomes “H”, the second switch element P2turns OFF so that the amplifier103is in “inactive state” while the clamp circuit CL2is in “active state” and the switch element N3turns ON. Since the second switch element P2turns OFF, the current source105is interrupted in its current path. Since the clamp circuit CL2is in “active state” to output the bias potential VCC/2, a potential of the node SUMN which has been the level of the power supply potential VCC is fixed to the bias potential VCC/2 (FIG.8(b)). When the node NDRV becomes the level of the ground potential GND (FIG.8(a)). Further, the switch element N3turns ON and the node NDRV becomes the level of the ground potential GND. Since the node NDRV becomes the level of the ground potential GND, the output transistor N4turns OFF.

Further, the enable signal P_EN becomes “H”, the first switch element N2turns ON and the amplifier102is in “active state” while the clamp circuit CL1is in “inactive state” and the switch element P3turns OFF. Since the first switch element N2turns ON, a current flows to the current source104. Since the clamp circuit CL1is in “inactive state”, the operation of the amplifier102(control the a rising edge rate) is not influenced thereby.

The amplifier102outputs a potential to the node PDRV in response to the potential of the node SUMP occurring (inputted) to the input terminal DM. Since the node SUMP is fixed to the bias potential VCC/2 when the enable signal P_EN is “L”, the amplifier102can start the control the a rising edge rate at a given timing.

The operation of the amplifier102is described now with reference to FIG.2. The bias potential VCC/2 is inputted to the input terminal DM until time t1. The bias potential VCC/2 is always inputted to the input terminal DP so that the ON resistance of the transistor P24and that of the transistor N24are equal to each other. Since the current flowing to the transistor P24and that flowing to the transistor N24are equal to each other so that a potential of the node n1, namely a potential of the output terminal is set to become the level of the bias potential VCC/2. When the potential of the input terminal DM increases, a current IN21flowing to the input transistor N21increases. Since the current IN21increases, a current IP22flowing to the PMOS transistor P22increases. Since the PMOS transistor P22and PMOS transistor P23form current mirrors, when the current IP22of the first current mirror circuit201at the current input side increases, a current IP23of the first current mirror circuit201at the current output side increases. Meanwhile, if a potential to be supplied to the input terminal DM increases, the current IP21flowing to the input transistor P21decreases. Since the current IP21decreases, a current IN22flowing to the NMOS transistor N22decreases. Since the NMOS transistor N22and the NMOS transistor N23form the current mirrors, when the current IN22of the second current mirror circuit202at the current input side decreases so that the current IN23of the second current mirror circuit202at the current output side decreases. Since the current IP23increases and the current IN23decreases, a current by the difference between the current IP23−current IN23flows to the transistor N24. Since the bias potential VCC/2 is supplied to the gates of both the transistors N24and P24, values of ON resistance of both the transistors become equal to each other, so that current IN24flowing to the transistor N24increases, and hence a potential of the node n1increases.

When a potential of the input terminal DM lowers, the current IP21flowing to the input transistor P21increases. Since the current IP21increases, the current IN22flowing to the NMOS transistor N22increases. Since the NMOS transistor N22and NMOS transistor N23form current mirrors, when the current IN22of the second current mirror circuit202at the current input side increases, the current IN23of the second current mirror circuit202at the current input side increases. Meanwhile, since a potential to be supplied to the input terminal DM lowers, the current IN21flowing to the input transistor N21decreases. Since the current IN21decreases, the current IP22flowing to the PMOS transistor P22decreases. Since the PMOS transistor P22and PMOS transistor P23form the current mirrors, when the current IP22of the first current mirror circuit201at the current input side decreases so that the current IP23of the first current mirror circuit201at the current output side decreases. Since the current IN23increases and the current IP23decreases, a current by the difference between the current IN23−current IP23flows from the transistor P24into the NMOS transistor N23. Since the bias potential VCC/2 is supplied to the gates of both the transistor P24and transistor N24, values of ON resistance of both transistors are equal to each other, so that a current IN24flowing to the transistor P24increases, and hence a potential of the node n1lowers. The amplifier102operates as set forth above to control the conductive state of the output transistor P4.

During a period from time t1to time t2, both the node SUMP and the node PDRV fluctuate near the bias potential VCC/2 by the operation of the amplifier102set forth above (FIG. 8(b),FIG. 8(c)). A current flowing from the power supply potential node into the output node101through the output transistor P4is controlled by the amplifier102and capacitor element C1, a potential of the output node101increases from the ground potential GND to the power supply potential VCC at a given edge rate (FIG. 8(d)).

At time t2, the control the a rising edge rate is completed. The potential of the node SUMP lowers to a level of the ground potential GND by the current source104(FIG. 8(b)). Since the potential of the node SUMP lowers to a level of the ground potential GND, the node PDRV lowers to the level of the ground potential GND (FIG. 8(c)). Since the the node PDRV lowers to the level of the ground potential GND, the output transistor P4keeps ON state and the potential of the output node101is held at the level of the power supply potential VCC (FIG. 8(d)).

At time t3, both the enable signal P_EN and enable signal N_EN# become “L” (FIG.8(a)). Since the enable signal N_EN# becomes “L”, the first switch element N2turns OFF so that the amplifier102is in “inactive state” while the clamp circuit CL1is in “active state” and the switch element P3turns ON. Since the first switch element N2turns OFF, the current source104is interrupted in its current path. Since the clamp circuit CL1is in “active state” and outputs the bias potential VCC/2, a potential of the node SUMP which has been the level of the ground potential GND is fixed to the bias potential VCC/2 (FIG.8(b)). When the switch element P3turns ON and the node PDRV becomes power supply potential VCC (FIG.8(c)). Since the node PDRV becomes power supply potential VCC, the output transistor P4turns OFF.

Further, since the enable signal N_EN# becomes “L”, the second switch element P2turns ON and the amplifier103is in “active state” while the clamp circuit CL2is in “inactive state” and the switch element N3turns OFF. Since the second switch element P2turns OFF, a current flows to the current source105. Since the clamp circuit CL2is in “inactive state”, the operation of the amplifier103(control of the falling edge rate) is not influenced thereby.

The amplifier103outputs a potential to the node NDRV in response to the potential of the node SUMN occurring (or inputted) to the input terminal DM. Since the node SUMN is fixed to the bias potential VCC/2 when the enable signal N_EN# is “H”, the amplifier103can start the control of the falling edge rate at a given timing. The operation of the amplifier103is described with reference to FIG.3. The bias potential VCC/2 is inputted to the input terminal DM during a period from time t1to time t3. The bias potential VCC/2 is always inputted to the input terminal DP so that the ON resistance of the transistor P24and that of the transistor N24are equal to each other. Since the current flowing to the transistor P24and that flowing to the transistor N24are equal to each other so that a potential of the node n1, namely a potential of the output terminal is set to become the level of the bias potential VCC/2. When the potential at the input terminal DM increases, the current IN21flowing to the input transistor N21increases. Since the current IN21increases, the current IP22flowing to the PMOS transistor P22increases. Since the PMOS transistor P22and PMOS transistor P23form current mirrors, when the current IP22of the first current mirror circuit201at the current input side increases, the current IP23of the first current mirror circuit201at the current output side increases. Meanwhile, since the potential to be supplied to the input terminal DM increases, the current IP21flowing to the input transistor P21decreases. Since the current IP21decreases, the current IN22flowing to the NMOS transistor N22decreases. Since the NMOS transistor N22and the NMOS transistor N23form the current mirrors, when the current IN22of the second current mirror circuit202at the current input side decreases so that the current IN23of the second current mirror circuit202at the current output side decreases. Since the current IP23increases and the current IN23decreases, a current by the difference between the current IP23−current IN23flows into the transistor N24. Since the bias potential VCC/2 is supplied to the gates of both the transistors N24and P24, values of ON resistance of both the transistors become equal to each other, so that the current IN24flowing to the transistor N24increases, and hence a potential of the node n1increases.

When a potential of the input terminal DM lowers, the current IP21flowing to the input transistor P21increases. When the current IP21increases, the current IN22flowing to the NMOS transistor N22increases. Since the NMOS transistor N22and NMOS transistor N23form current mirrors, when the current IN22of the second current mirror circuit202at the current input side increases, the current IN23of the second current mirror circuit202at the current input side increases. Meanwhile, since a potential to be supplied to the input terminal DM lowers, the current IN21flowing to the input transistor N21decreases. Since the current IN21decreases, the current IP22flowing to the PMOS transistor P22decreases. Since the PMOS transistor P22and PMOS transistor P23form the current mirrors, when the current IP22of the first current mirror circuit201at the current input side decreases, the current IP23of first current mirror circuit201at the current output side decreases. Since the current IN23increases and the current IP23decreases, a current by the difference between the current IN23−current IP23flows into the transistor P24. Since the bias potential VCC/2 is supplied to the gates of both the transistors P24and N24, values of ON resistance of both the transistors become equal to each other, so that the current IN24flowing to the transistor P24increases, and hence a potential of the node n1lowers. The amplifier103operates as set forth above, and controls the conductive state of the output transistor N4.

During a period from time t3to time t4, the node SUMN and the node NDRV fluctuate near the bias potential VCC/2 by the operation of the amplifier103set forth above (FIG. 8(b),FIG. 8(c)). A current flowing to the ground potential node from the output node101through the output transistor N4is controlled by the amplifier103and the capacitor element C2, a potential of the output node101lowers from the power supply potential VCC to the ground potential GND at a given edge rate (FIG. 8(d)).

At time t4, the control of the falling edge rate is completed. Since a current is supplied by the current source105, the potential of the node SUMN increases to a level of the power supply potential VCC (FIG. 8(b)). Since the node SUMN rises to the level of the power supply potential VCC, the node PDRV increases to the level of the power supply potential VCC (FIG. 8(c)). Since the node NDRV becomes the level of the power supply potential VCC, the output transistor N4keeps ON state. Since the output transistor N4keeps ON state, the potential of the output node101is held at the level of the ground potential GND (FIG. 8(d)). Subsequent operations are carried out by repeating the foregoing operations.

As explained above, since the output buffer circuit according to the first embodiment is provided with the clamp circuit CL1for supplying the bias potential VCC/2 to the node SUMP when the amplifier102is inactivated while stopping the supply of the same potential when the amplifier102is activated, and the clamp circuit CL2for supplying the bias potential VCC/2 to the node SUMN when the amplifier103is inactivated and stopping supply of the same potential when the amplifier103is activated, it is possible to achieve an output buffer circuit having a sufficient operation speed without influencing upon the control of the edge rate. Accordingly, the output buffer circuit of the first embodiment can fully satisfy an AC standard of a USB output buffer circuit, particularly a VCRS (crossover voltage) standard.

Second Preferred Embodiment

An output buffer circuit according to a second embodiment of the invention is described.FIG. 9is a circuit diagram showing the structure of the output buffer circuit according to the second embodiment of the invention. The output buffer circuit shown inFIG. 9is different from that of the first embodiment in respect of the provision of one common node instead of the node SUMP and node SUMN provided in the first embodiment. The common node is hereinafter referred to as a node SUM (first node). A capacitor element C1is connected between the node SUM and an output node101. A clamp circuit CL1which operates in response to an enable signal CL_EN (third control signal) is connected to the node SUM. A first current source104and a second current source105may be formed of circuit configurations as shown inFIGS. 4 and 5and they are not limited to the circuit configuration shown in FIG.9. Other circuit configurations are the same as those of the output buffer circuit according to the first embodiment of the invention.

The clamp circuit CL1supplies a given potential to the node SUM during a given period that before the control of the edge rate is started (a first given period before a first or second control circuit is activated), and stops the supply of the given potential during a given period that the control of the edge rate is effected (during a second given period that the first or second control circuit is activated). More in detail, the clamp circuit CL1supplies a bias potential VCC/2 to the node SUM during a period that the enable signal CL_EN of “H” (first logical level) is inputted to an enable terminal EN and stops the supply of the same potential during a period that the enable signal CL_EN of “L” (second logical level) is inputted thereto. The enable signal CL_EN to be inputted to the clamp circuit CL1is a signal which becomes “H” during a given period that immediately before the enable signal P_EN and enable signal N_EN# are switched to from “H” to “L” or “L” to “H” (immediately before the control of the rising edge rate and falling edge rate is started). The period that the enable signal CL_EN becomes “H” is a period which is, for example, about one eighth of a period that the enable signal P_EN and enable signal N_EN# become “H” or “L”. The enable signal CL_EN is outputted from a pre-driver (not shown) provided in a front stage of the output buffer circuit in the same manner as the enable signal P_EN and enable signal N_EN #.

The clamp circuit CL1is described more in detail with reference to FIG.10.FIG. 10is a circuit diagram showing the structure of the clamp circuit CL1. The clamp circuit CL1comprises a first resistor element N10connected between a power supply potential node and the node SUM, and a second resistor element P10connected between the node SUM and a ground potential node GND. The first resistor element N10is made up of an NMOS transistor comprising a first electrode connected to the power supply potential node, a second electrode connected to the node SUM, and a control electrode to which the enable signal CL_EN is inputted. The second resistor element P10is made up of a PMOS transistor comprising a first electrode connected to the ground potential node, a second electrode connected to the node SUM, and a control electrode to which an inverted signal of the enable signal CL_EN is inputted.

The operation of the output buffer circuit according to the second embodiment is described next with reference to FIG.11(a) to FIG.11(d). FIG.11(a) to FIG.11(d) show waveforms generated when the output buffer circuit operates, wherein FIG.11(a) shows levels of the enable signal CL_EN, enable signal P_EN and enable signal N_EN #, FIG.11(b) shows the potential of the node SUM, FIG.11(c) shows potentials of the node PDRV and node NDRV, and FIG.11(d) shows the potential of the output node101, wherein the axis of abscissas shows a time, and the axis of ordinates shows a potential.

At time t1, the enable signal CL_EN becomes “H” (FIG.11(a)). At this time, both the enable signal P_EN and enable signal N_EN# are held at “L”. Since the enable signal CL_EN becomes “H”, the clamp circuit CL1is in “active state” to output the bias potential VCC/2 to the node SUM. Accordingly, the node SUM which has been the level of the ground potential GND is instantly fixed to bias potential VCC/2 (FIG.11(b)).

At time t2, the enable signal CL_EN becomes “L”, while the enable signal P_EN and enable signal N_EN# become “H” (FIG.11(a)). Since the enable signal CL_EN becomes “L”, the clamp circuit CL1is in “inactive state”. Since the clamp circuit CL1is in “inactive state”, it does not influence upon the operation of an amplifier102(control of the rising edge rate). Since the enable signal N_EN# becomes “H”, a switch element P2turns OFF, and the amplifier103is in “inactive state”, and a switch element N3turns ON. Since the switch element P2turns OFF, the current source105is interrupted in its current path. Since the switch element N3turns ON, the node NDRV becomes a level of the ground potential GND (FIG.11(c)). Since the node NDRV becomes the level of the ground potential GND, an output transistor N4turns OFF.

Since the enable signal P_EN becomes “H”, the switch element N2turns ON, and the amplifier102is in “active state”, while a switch element P3turns OFF. Since the switch element N2turns ON, a current flows to the current source104. The amplifier102outputs a potential to the node PDRV in response to a potential to be inputted to an input terminal DM. Since the node SUM is already fixed to bias potential VCC/2 by the clamp circuit CL1, the amplifier102can start the control of the a rising edge rate in a given timing. The amplifier102operates in the same manner as set forth in the first embodiment, and controls a conductive state of the output transistor P4.

Both the node SUM and node PDRV fluctuate near the bias potential VCC/2 by the operation of the amplifier102during a period from time t2to time t3(FIG.11(b) and FIG.11(c)). A current which flows from the power supply potential node to the output node101is controlled by the amplifier102and capacitor element C1so that the potential of the output node101increases from the ground potential GND to the power supply potential VCC at a given edge rate.

During a period from time t2to time t3, both the node SUM and node NDRV fluctuate near the bias potential VCC/2 by the operation of the amplifier102(FIG.11(b) and FIG.11(c)). A current which flows from the ground potential node to the output node101is controlled by the amplifier102and capacitor element C1so that the potential of the output node101rises from the ground potential GND to the power supply potential VCC (FIG.11(d)).

At time t3, the control the a rising edge rate is completed. The node SUM lowers to the level of the ground potential GND by the current source104(FIG.11(b)). Since the node SUM lowers to the level of the ground potential GND, the node PDRV lowers to the level of the ground potential GND (FIG.11(c)). Since the node PDRV lowers to the level of the ground potential GND, the output transistor P4keeps ON state and the potential of the output node101keeps the power supply potential VCC (FIG.11(d)).

At time t4, the enable signal CL_EN becomes “H” (FIG.11(a)). At this time, both the enable signal P_EN and enable signal N_EN# are held at “H” (FIG.11(a)). Since the enable signal CL_EN becomes “H”, the clamp circuit CL1is in “active state” to output the bias potential VCC/2 to the node SUM. Accordingly, the node SUM which has been the level of the ground potential GND is instantly fixed to the bias potential VCC/2 (FIG.11(b)).

At time t5, both the enable signal CL_EN, and the enable signal N_EN# become “L” (FIG.11(a)). Since the enable signal CL_EN becomes “L”, the clamp circuit CL1is in “inactive state”. Since the clamp circuit CL1is in “inactive state”, it does not influence upon the operation of the amplifier103(control of the falling edge rate). Since the enable signal P_EN becomes “L”, the switch element N2turns OFF, and the amplifier102is in “inactive state” while the switch element P3turns ON. Since the switch element N2turns OFF, the current source104is interrupted in its current path. Accordingly, the switch element P3turns ON, and the node PDRV becomes a level of the power supply potential VCC (FIG.11(c)). Since the node PDRV becomes a level of the power supply potential VCC, the output transistor P4turns OFF.

Since the enable signal N_EN# becomes “L”, the switch element P2turns ON and the amplifier103is in “active state” while the switch element N3turns OFF. Since the switch element P2turns ON, a current flows to the current source105. The amplifier103outputs a potential to the node NDRV in response to a potential to be inputted to the input terminal DM. Since the node SUM is already fixed to bias potential VCC/2 by the clamp circuit CL1, the amplifier103can start the control of the falling edge rate in a given timing. The amplifier103operates in the same manner as set forth in the first embodiment, and controls a conductive state of the output transistor N4.

During a period from time t5to time t6, both the node SUM and node NDRV fluctuate near the bias potential VCC/2 by the operation of the amplifier103(FIG.11(b) and FIG.11(c)). A current which flows from the output node101to the ground potential node is controlled by the amplifier103and capacitor element C1so that the potential of the output node101lowers from the power supply potential VCC to the ground potential GND (FIG.11(d)).

At time t6, the control of the falling edge rate is completed. Since the electric charge from the current source105is accumulated in the capacitor element C1, the node SUM rises to the level of the power supply potential VCC (FIG.11(b)). Since the node SUM becomes the level of the power supply potential VCC, the the node NDRV becomes the level of the power supply potential VCC (FIG.11(c)). Since the node NDRV becomes the level of the power supply potential VCC and the output transistor N4keeps ON state, the output node101is held at the level of the ground potential GND (FIG.11(d)). Subsequently, the foregoing operations are repeated.

As explained above, since the output buffer circuit of the second embodiment is provided with the clamp circuit CL1for supplying a given potential to the node SUM during a first given period that before both the amplifiers102and103are activated while stopping the supply of the given potential to the node SUM during a second given period that both the amplifiers102and103are inactivated upon elapse of the first given period, it can start the control of the edge rate at a given timing without influencing upon the control of the edge rate. Accordingly, the output buffer circuit of the first embodiment can fully satisfy an AC standard of a USB output buffer circuit, particularly a VCRS (crossover voltage) standard. Further, according to the output buffer circuit of the second embodiment, since both the rising edge rate and falling edge rate are controlled by use of a common feedback capacitor element, it is possible to avoid the increase of a circuit area.

Third Preferred Embodiment

An output buffer circuit according to a third embodiment of the invention is described.FIG. 12is a circuit diagram showing the structure of the output buffer circuit according to the third embodiment of the invention. The output buffer circuit of the third embodiment is different from that of the first embodiment in respect of the provision of a switch circuit SW1. Other circuit configurations are the same as those of the first embodiment. The switch circuit SW1is connected between a node PDRV and a node NDRV. The switch circuit SW1connects between the node PDRV and node NDRV during a period that it controls the rising edge rate. More in detail, the switch circuit SW1turns ON when an enable signal P_EN becomes “H” while it turns OFF when the enable signal P_EN becomes “L”. The circuit configuration of the switch circuit SW1is described with reference to FIG.13.FIG. 13is a circuit diagram showing the structure of the switch circuit SW1. InFIG. 13, the switch circuit SW1comprises a switch element N13and a switch element P13. The switch element N13is made up of an NMOS transistor comprising a first electrode connected to the gate of the output transistor P4, a second electrode connected to the gate of the output transistor N4, and a gate (control electrode) to which the enable signal P_EN (control signal) is applied. The switch element P13is made up of a PMOS transistor comprising a first electrode connected to a gate of the output transistor P4, a second electrode connected to a gate of the output transistor N4, and a gate (control electrode) to which an inverted signal of the enable signal P_EN is applied.

The operation of the output buffer circuit according to the second embodiment of the invention is described next. FIG.14(a) to FIG.14(d) show waveforms generated when the output buffer circuit operates, wherein FIG.14(a) shows levels of the enable signal P_EN and enable signal N_EN #, FIG.14(b) shows the potential of the node SUMP and node SUMN, FIG.14(c) shows potentials of the node PDRV and node NDRV, and FIG.14(d) shows the potential of the output node101, wherein the axis of abscissas shows a time, and the axis of ordinates shows a potential.

At time t1, both the enable signal P_EN and enable signal N_EN# become “H” (FIG.14(a)). Since the enable signal P_EN becomes “H”, the switch circuit SW1turns ON, a switch element N2turns ON, and an amplifier102is in “active state”, while a clamp circuit CL1is in “inactive state”, and a switch element P3turns OFF. Since the switch element N2turns ON, a constant current flows to the current source104. A current which flows when the electric charge accumulated in the capacitor element C1is discharged and a current from the input terminal DM of the amplifier102flows into the current source104. The operation of the amplifier102is same as that of the amplifier102of the first embodiment.

Since the enable signal N_EN# becomes “H”, the switch element P2turns OFF and the amplifier103is in “inactive state” while the clamp circuit CL2is in “active state”. Since the switch element P2turns OFF, the current source105is interrupted in its the current path. Since the clamp circuit CL2is in “active state” and outputs the bias potential VCC/2, a potential of the node SUMN which has been the level of the power supply potential VCC is fixed to the bias potential VCC/2 (FIG.14(b)). Since the switch circuit SW1turns ON, the node NDRV is connected to the node PDRV and it becomes the level of the bias potential VCC/2 like the node PDRV (FIG.14(c)). Since the node NDRV becomes the level of the bias potential VCC/2, the output transistor N4turns ON.

In the case where the output buffer circuit of the third embodiment is used as a low speed (LS) driver of a USB, a pull-up resistor is connected into the output node101. A current flows from the power supply potential node to the output node101through the pull-up resistor. Supposing that the node NDRV is the level of the ground potential GND without providing the switch circuit SW1, the output transistor N4turns OFF, thereby losing an electric path for letting off a current which flowed thereinto through the pull-up resistor. As a result, the current keeps flowing into the output node101, which influences upon the control of the rising edge rate. However, according to the output buffer circuit of the third embodiment, since the switch circuit SW1turns ON and is electrically connected to the node PDRV, the node NDRV becomes the level of the bias potential VCC/2 in the same manner as the node PDRV. Accordingly, the output transistor N4turns ON and an electric path is provided between the output terminal and ground potential node GND, so that a current which flowed thereinto through the pull-up resistor flows to the ground potential node GND through the output transistor N4. As a result, it is possible to prevent the current which flowed thereinto through the pull-up resistor from influencing upon the control of the rising edge rate.

At time t2, the control of the rising edge rate is completed. Since a current is pulled out toward the ground potential node by the current source104, the node SUMP lowers to the level of the ground potential GND (FIG.14(b)). Since the node SUMP lowers to the level of the ground potential GND, the node PDRV lowers to the level of the ground potential GND (FIG.14(c)). Since the node NDRV is connected to the node PDRV, it lowers to the level of the ground potential GND (FIG.14(c)). Since the node NDRV lowers to the level of the ground potential GND, the output transistor N4turns OFF. Further, since the node PDRV lowers to the level of the ground potential GND, the output transistor P4keeps ON state and the potential of the output node101keeps the level of the power supply potential VCC (FIG.14(d)).

At time t3, both the enable signal P_EN and enable signal N_EN# become “L” (FIG.14(a)). Since the enable signal P_EN becomes “L”, the switch circuit SW1turns OFF and the switch element N2turns OFF while the amplifier102is in “inactive state”, the clamp circuit CL1is in “active state” and the switch element P3turns ON. Since the switch circuit SW1turns OFF, an electric path between the node PDRV and node NDRV is interrupted. Since the switch element N2turns OFF, the current source104is interrupted in its current path. Since the clamp circuit CL1is in “active state” to output the bias potential VCC/2, the potential of the node SUMP which has been the level of the ground potential GND is fixed to the bias potential VCC/2 (FIG.14(b)). Further, the switch element P3turns ON, the node PDRV becomes the level of the power supply potential VCC (FIG.14(c)). Since the node PDRV becomes the level of the power supply potential VCC, the output transistor P4turns OFF.

Since the enable signal N_EN# becomes “L”, the switch element P2turns ON and the amplifier103is in “active state” while the clamp circuit CL2is in “inactive state”. Since the switch element P2turns ON, a constat current flows to the current source105. A current flowing to the current source105is divided into a current for charging a capacitor element C2and a current flowing to the input terminal DM of the amplifier103. A value of current flowing to the current source105is determined by a resistance of a resistor element R2and ON resistance of a PMOS forming the switch element P2. The amplifier103controls a conductive state of the output transistor N4when it operates in the same manner as the first embodiment.

During a period from time t3to time t4, both the node SUM and node NDRV fluctuate near the bias potential VCC/2 (FIG. 14(b),FIG. 14(c)). A current flowing from the output node101to the ground potential node is controlled by the amplifier103and capacitor element C1, so that a potential of the output node101lowers from the power supply potential VCC to the ground potential GND at a given edge rate (FIG. 14(d)).

At time t4, the control of the falling edge rate is completed. Since the electric charge from the current source105is accumulated in the capacitor element C1, the node SUM rises to the level of the power supply potential VCC (FIG.14(b)). Since the node SUM becomes the level of the power supply potential VCC, the node NDRV becomes the level of the power supply potential VCC (FIG.14(c)). Since the node NDRV becomes the level of the power supply potential VCC and the output transistor N4keeps ON state, the output node101keeps the level of the ground potential GND (FIG.14(d)). Subsequently, the foregoing operations are repeated.

As explained above, since the output buffer circuit of the third embodiment is provided with the switch circuit SW1for connecting between the node PDRV and node NDRV during a period for controlling the rising edge rate (during a period that the amplifier102is in “active state”), it is possible to prevent the occurrence of distortion of the output waveform by a current flowing from the power supply potential node to the output node101through the pull-up resistor. Accordingly, the output buffer circuit of the third embodiment can fully satisfy an AC standard of a USB output buffer circuit, particularly a VCRS (crossover voltage) standard.

Fourth Preferred Embodiment

An output buffer circuit according to a fourth embodiment of the invention is described.FIG. 15is a circuit diagram showing the structure of the output buffer circuit according to the fourth embodiment of the invention. The output buffer circuit of the fourth embodiment is different from that of the second embodiment in respect of the provision of a switch circuit SW1. Other circuit configurations are the same as those of the second embodiment. The switch circuit SW1is connected between a node PDRV and a node NDRV. The switch circuit SW1connects between the node PDRV and node NDRV during a period that it controls the rising edge rate. More in detail, the switch circuit SW1turns ON when an enable signal P_EN becomes “H” while it turns OFF when the enable signal P_EN becomes “L”. The detailed circuit configuration of the switch circuit SW1is the same as that shown in FIG.13.

In the case where the output buffer circuit of the fourth embodiment is used as a low speed (LS) driver of a USB, a pull-up resistor is connected to the output node101. A current flows from the power supply potential node into the output node101through the pull-up resistor. Supposing that the node NDRV is the level of the ground potential GND without providing the switch circuit SW1, an output transistor N4turns OFF, thereby losing an electric path for letting off a current which flowed thereinto through the pull-up resistor. As a result, the current keeps flowing into the output node101, which influences upon the control of the rising edge rate. However, according to the output buffer circuit of the fourth embodiment, since the switch circuit SW1turns ON and the node NDRV is electrically connected to the node PDRV, the node NDRV becomes the level of a bias potential VCC/2 in the same manner as the node PDRV. Accordingly, the output transistor N4turns ON and an electric path is provided between the output terminal and ground potential node GND, so that a current which flowed thereinto through the pull-up resistor flows to the ground potential node GND through the output transistor N4. As a result, it is possible to prevent the current which flowed thereinto through the pull-up resistor from influencing upon the control of the rising edge rate.

As explained above, since the output buffer circuit of the fourth embodiment is provided with the switch circuit SW1for connecting between the node PDRV and node NDRV during a period for controlling the rising edge rate (during a period that the amplifier102is in “active state”), it is possible to prevent the occurrence of distortion of the output waveform by a current flowing from the power supply potential node into the output node101through the pull-up resistor.

As explained above in detail, since the typical output buffer circuit according to the invention has the first clamp circuit for supplying a given potential to the first node when the first control circuit is inactivated and stops the supply of the given potential when the first control circuit is activated, and a second clamp circuit for supplying a given potential to the second node when the second control circuit is inactivated, and stops the supply of the given potential when the second control circuit is activated, the output buffer circuit can start the control of the edge rate at a given timing without influencing upon the control of the edge rate.