High mobility devices and methods of forming same

An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.

BACKGROUND

Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits typically include field-effect transistors (FETs).

Conventionally, planar FETs have been used in integrated circuits. However, with the ever increasing density and decreasing footprint requirements of modern semiconductor processing, planar FETs may generally incur problems when reduced in size. Some of these problems include sub-threshold swing degradation, significant drain induced barrier lowering (DIBL), fluctuation of device characteristics, and leakage. Fin field-effect transistors (finFETs) have been studied to overcome some of these problems.

In a typical finFET, a vertical fin structure is formed over a substrate. This vertical fin structure is used to form source/drain regions in the lateral direction and a channel region in the fin. A gate is formed over the channel region of the fin in the vertical direction forming a finFET. Subsequently, an inter-layer dielectric (ILD) and a plurality of interconnect layers may be formed over the finFET.

DETAILED DESCRIPTION

Various embodiments include a method for forming finFETs of two different types (e.g., n-type and p-type) over a strain relaxed buffer (SRB) layer and a corresponding structure. The process for forming the finFETs may include growing a first semiconductor layer of a first type (e.g., n-type or p-type) over a SRB layer and replacing a first portion of the first semiconductor layer of the first type with a second semiconductor layer of a second type (e.g., the other of n-type or p-type). The process may include using various barrier and/or sacrificial layers to protect the second portion of the first semiconductor layer while the second semiconductor layer is formed. The process may further include using various selective etching and/or planarization processes in combination with the barrier and/or sacrificial layers.

FIG. 1illustrates an example of a finFET30in a three-dimensional view. FinFET30includes a strain relaxed buffer (SRB)34and fin36on a substrate32. FinFET30may further include isolation regions38, and fin36protrudes above and from between neighboring isolation regions38. A gate dielectric40extends along sidewalls and over a top surface of the fin36, and a gate electrode42is disposed over the gate dielectric40. Source/drain regions44and46are disposed in opposite sides of the fin36with respect to the gate dielectric40and gate electrode42.FIG. 1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is across a channel, gate dielectric40, and gate electrode42of the finFET30. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin36and in a direction of, for example, a current flow between the source/drain regions44and46. Subsequent figures may refer to these reference cross-sections for clarity.

FIGS. 2 through 17are cross-sectional views of various intermediary stages in the manufacturing finFETs in accordance with various embodiments, andFIG. 18is a process flow of the process shown inFIGS. 2 through 17.FIGS. 2 through 17illustrate reference cross-section A-A illustrated inFIG. 1, except for multiple finFETs and/or finFETs having multiple fins.

FIGS. 2 and 3illustrate the formation of semiconductor regions over a substrate. Referring first toFIG. 2, a wafer100having a substrate102is illustrated. Substrate102may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of substrate102may include silicon (Si); germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

As further illustrated byFIGS. 2 and 3, additional semiconductor layers may be formed over substrate102. In some embodiments, a one or more epitaxies may be performed to form a strain relax buffer (SRB) layer104over substrate102(seeFIG. 2) and a semiconductor layer106of a first type over SRB layer104(seeFIG. 3). Any suitable epitaxy processes may be used, such as by metal-organic (MO) chemical vapor deposition (CVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), combinations thereof, or the like.

In some embodiments, SRB layer104and semiconductor layer106may comprise Si, SiGe, or Ge having differing atomic percentages of Ge. SRB layer104may be substantially relaxed when the material of the SRB layer104is lattice mismatched to the material underlying SRB layer104, such as the material of the substrate102. SRB layer104may be substantially relaxed through plastic relaxation by dislocations being generated in SRB layer104and/or through elastic relaxation. SRB layer104may further induce a strain in an overlying material, such as the upper semiconductor layer106. When a relaxed layer, such as a SRB layer104, is lattice mismatched with an overlying layer, such as semiconductor layer106, the overlying layer may be strained through pseudomorphic epitaxial growth. The type of strain in the overlying semiconductor layer106(e.g., compressive strain or tensile strain) may vary depending on whether n-type or p-type devices are desired, and the type of strain achieved may be adjusted by selecting a suitable atomic percentage of Ge in SRB layer104and semiconductor layer106.

For example, for n-type devices, tensile strain may be desirable. In such embodiments, SRB layer104may comprise a higher atomic percentage of Ge than semiconductor layer106. For example, SRB layer104may comprise SiGe having about 25% to about 50% Ge while overlying semiconductor layer106may comprise SiGe or Si having about 0% to about 25% Ge. In alternative embodiments, an SRB layer104comprising SiGe having about 50% to about 75% Ge and a semiconductor layer106comprising SiGe having about 25% to about 50% Ge may also be used to achieve tensile strain in semiconductor layer106. Other material combinations (e.g., having other semiconductor materials and/or other atomic percentages of germanium) may also achieve a tensile strain in semiconductor layer106.

In other embodiments, semiconductor layer106may be compressively strained, which may be advantageous for p-type devices. In such embodiments, SRB layer104may comprise a lower atomic percentage of Ge than semiconductor layer106. For example, SRB layer104may comprise SiGe having about 25% to about 50% Ge while overlying semiconductor layer106may comprise SiGe having about 50% to about 75% Ge. In alternative embodiments, an SRB layer104comprising SiGe having about 50% to about 75% Ge and a semiconductor layer106comprising SiGe or pure Ge having about 75% to about 100% Ge may also be used to achieve compressive strain in semiconductor layer106. Other material combinations (e.g., having other semiconductor materials and/or other atomic percentages of germanium) may also achieve a compressive strain in semiconductor layer106.

FIGS. 4 through 6illustrate the formation of STI regions120in wafer100. Referring first toFIG. 4, pad layers108and110may be disposed over semiconductor layer106. Pad layer108may include an oxide (e.g., silicon oxide) while pad layer110may include a nitride (e.g., silicon nitride). Pad layers110and108may act as etch stop and/or protective layers for portions of semiconductor layer106, SRB layer104, and/or substrate102during the formation of additional features in wafer100in subsequent process steps.

As further illustrated byFIG. 4, a patterned photoresist112may be formed over pad layer110. For example, photoresist112may be blanket deposited over pad layer110and exposed using a photomask. Exposed or unexposed portions of photoresist112may then be removed depending on whether a positive or negative resist is used. Thus, openings114may be formed in photoresist112.

Subsequently, as illustrated byFIG. 5, openings114may be extended into SRB layer104by etching pad layer110, pad layer108, semiconductor layer106, and SRB layer104, for example. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Subsequently, photoresist112is removed in an ashing and/or wet strip processes, for example. In some embodiments, a hard mask (not shown) might be formed atop pad layer110prior to formation of photoresist112, in which embodiments the pattern from photoresist112would first be imposed upon the hard mask and the patterned hard mask would be used in patterning the underlying layers110,108,106, and104.

Thus, fins116are formed in wafer100. Fins116extend upwards from SRB layer104between adjacent openings114. Each fin116includes a SRB layer104portion, a semiconductor layer106portion, an oxide pad layer108portion, and a nitride pad layer110portion. Solely for the ease of description, semiconductor layer106in wafer100will be described as an n-type semiconductor layer, which is tensilely strained and doped with n-type impurities as described above. Furthermore, after patterning fins116, semiconductor layer106is patterned as individual semiconductor strips extending upwards from SRB layer104. Thus, remaining portions of semiconductor layer106in fins116may be referred to as n-type semiconductor strips106hereinafter. However, one or ordinary skill in the art would recognize that various embodiments may apply to alternative structures where semiconductor layer106is a p-type layer.

As further illustrated byFIG. 5, a liner118, such as a diffusion barrier layer, may be disposed along sidewalls of bottom surfaces of openings114. In some embodiments, liner118may comprise a semiconductor (e.g., silicon) nitride, a semiconductor (e.g., silicon) oxide, a thermal semiconductor (e.g., silicon) oxide, a semiconductor (e.g., silicon) oxynitride, a polymer dielectric, combinations thereof, and the like formed using any suitable method, such as, atomic layer deposition (ALD), CVD, high density plasma (HDP) CVD, physical vapor deposition (PVD), and the like.

Referring next toFIG. 6, openings114may be filled with a dielectric material, such as, silicon oxide, or the like. In some embodiments, the resulting STI regions120may be formed using a high-density-plasma (HDP) CVD process, using silane (SiH4) and oxygen (O2) as reacting precursors. In other embodiments, STI regions120may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), wherein process gases may comprise tetraethylorthosilicate (TEOS) and ozone (O3). In yet other embodiments, STI regions120may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). An annealing may be performed to cure the material of STI regions120, and liner118may prevent (or at least reduce) the diffusion of semiconductor material from fins116(e.g., Si and/or Ge) into the surrounding STI regions120during the annealing. Other processes and materials may be used. A chemical mechanical polish (CMP) or etch back process may be used to level a top surface of the dielectric material of STI regions120using pad layer110(e.g., a nitride) as an etch stop layer. After planarization, top surfaces of fins116and STI regions120may be substantially level with each other. Furthermore, in embodiments where semiconductor layer106is tensilely strained, n-type anti-punch through (APT) impurities (e.g., boron or BF2) may be implanted in semiconductor layer106.

As further illustrated byFIG. 6, a barrier layer122may be formed over STI regions120and fins116. In various embodiments, barrier layer122may be blanket deposited using any suitable process (e.g., CVD, and the like). Barrier layer122may act as a mask layer, an etch stop layer, and/or a protective layer for various underlying features during the formation of additional features in wafer100as will be explained in greater detail in subsequent paragraphs. In some embodiments, barrier layer122may comprise a different material than pad layer110, which may allow for selective patterning of barrier layer122or pad layer110. For example, when pad layer110comprises a nitride, barrier layer122may comprise an oxide (e.g., SiO, ALD OX, plasma enhanced oxide (PEOX)). In some embodiments, barrier layer122may have a thickness of about 15 nm to about 30 nm, for example.

FIGS. 7 through 10illustrate the removal of top portions of certain fins116(labeled116′). Referring first toFIG. 7, barrier layer122is patterned using a combination of photolithography and etching, for example, to form an opening126extending through barrier layer122. The patterning of barrier layer122may include using photoresist124as a patterning mask and an anisotropic etching process. Opening126may partially expose a top surface of STI regions120and top surfaces (e.g., pad layer portions110′) of semiconductor fins116′. In such embodiments, pad layer portions110′ may act as an etch stop layer for the etching of barrier layer122. The fins exposed by opening126may be one selected for the formation of finFETs of a different type (e.g., p-type) than n-type semiconductor strips106. In alternative embodiments where semiconductor layer106is a p-type layer, n-type finFETs may be formed in fins116′. Other fins116in wafer100may remained masked by barrier layer122. Subsequently, photoresist124may be removed using a photoresist stripping solution, such as, “Caro's Solution” or “Caro's PR Solution,” for example.

Next, inFIG. 8, pad layer portions110′ (e.g., a nitride) of fins116′ are removed using one or more etching processes, for example. The removal of pad layer portions110′ may include a dry etching process to break through a native oxide (not shown) formed on a top surface of exposed STI regions120followed by a dry etching to remove pad layer portions110′. The removal of pad layer portions110′ may further use pad layer portions108′ (e.g., an oxide) as an etch stop layer.

As a result of break through etching, a top surface of STI regions120in opening126may be recessed by a distance D1from a top surface of masked portions of STI regions120. For example, barrier layer122may prevent damage to masked portions of STI regions120and fins116during the break through etching process. In various embodiments, the break through etching process may use a chemical etchant that selectively etches STI regions120at a higher rate than barrier layer122. For example, a ratio of the etching rate of barrier layer122to the etching rate of STI regions120may be about 1:1.5. In such embodiments, barrier layer122may also be etched during the break through etching (not explicitly illustrated).

Referring next toFIG. 9, pad layer portions108′ and n-type semiconductor strips106′ of fins116′ are removed using one or more etching processes, for example. The removal of pad layer portions108′ (e.g., an oxide) may include a break through etching process, and subsequently, a channel recess (e.g., a dry or wet etching process) may be employed to remove n-type semiconductor strips106′. The removal of pad layer portions108′ may comprise a similar process as the break through etching used to remove the native oxide (not shown) of exposed STI regions120. In such embodiments, distance D1may be increased during the removal of pad layer portions108′, and embodiments, barrier layer122may prevent damage to masked portions of STI regions120and fins116during the removal of pad layer portions108′. The removal of pad layer portions108′ and n-type semiconductor strips106′ may further recess portions of liner118exposed by opening126(e.g., by a distance D2inFIG. 9). In some embodiments (not illustrated), liner118may even be recessed past a top surface of SRB layer104. Subsequently, an ashing process may be used to clean out byproducts of the etching processes (e.g., break through etching and/or channel recessing). Thus, trenches128are formed in wafer100disposed between neighboring STI regions120. Trenches128may be connected to opening126and expose top surfaces of SRB layer104in fins116′.

InFIG. 10, an epitaxial pre-cleaning is performed to remove a native oxide (not shown) formed on a top surface of SRB layer104in trenches128. The pre-cleaning process may include using an HF-based gas or a SiCoNi-based gas, for example. As a result of pre-cleaning, a top surface of STI regions120in opening126may be recessed even further from a top surface of masked portions of STI regions120(e.g., D1may be further increased).

As also illustrated byFIG. 10, liner118may substantially cover sidewalls of trenches128. For example, top surfaces of liner118and STI regions120may be substantially level after the pre-cleaning process. Alternatively, liner118may be recessed from the top surface of SRB layer104. In subsequent process steps (e.g., inFIG. 11), semiconductor strips130may be grown in trenches128on SRB layer104. In embodiments where liner118is recessed, semiconductor strips130may be grown on multiple surfaces of SRB layer104(e.g., a lateral top surface and sidewall surfaces). This increased bonding area may reduce the occurrence of voids and other interface defects at the interface between SRB layer104and semiconductor strips130.

Throughout the various etching and/or pre-cleaning processes illustrated byFIGS. 8 through 10, barrier layer122may prevent damage to masked portions of STI regions120and fins116. As a result of various etching/pre-cleaning processes, barrier layer122may also be thinned. Thus, the deposition of barrier layer122may include depositing a sufficiently thick layer to withstand these various process steps. For example, barrier layer122may have an initial thickness (after deposition) of about 15 nm to about 30 nm.

After pre-cleaning, inFIG. 11, an epitaxy is performed to epitaxially grow semiconductor strips130are formed in trenches128. In various embodiments, semiconductor strips130may be of a different type than n-type semiconductor strips106. For example, in wafer100, semiconductor strips130may be p-type layer, and will be referred to as p-type semiconductor strips130hereinafter. Various embodiments may also be applied to structures where semiconductor layer106is p-type and semiconductor strips130are n-type. During the epitaxy of p-type semiconductor strips130, a p-type APT impurity (e.g., phosphorus or arsenic) may be in-situ doped with the proceeding or the epitaxy. Furthermore, p-type semiconductor strips130may be compressively strained as described above.

The epitaxy of p-type semiconductor strips130may overgrow trenches128and extend into opening126. InFIG. 12, a high-selectively CMP may be used to remove such overgrown portions and planarize top surfaces of p-type semiconductor strips130. For example, the CMP process may comprise using a chemical slurry that selectively removes the material of p-type semiconductor strips130(e.g., SiGe or Ge) at a higher rate than barrier layer122(e.g., an oxide) and/or STI regions120. In some embodiments, the slurry may etch p-type semiconductor strips130at about five times (or even greater) a rate than barrier layer122and/or STI regions120. After CMP, top surfaces of p-type semiconductor strips130and STI regions120in opening126may be substantially level. Furthermore, the selective CMP process may further recess or even remove barrier layer122. In embodiments where barrier layer122is removed during the selective CMP, pad layers108and/or110may protect n-type semiconductor strips106from damage.

Exposed portions of STI regions120may also be recessed (e.g., distance D1may be increased). For example, inFIG. 11, a total dimension of distance D1as a result of various etching, pre-cleaning, and/or CMP processes may be about 20 nm or even more. As a further result of the various etching, pre-cleaning, and/or CMP processes used to form p-type semiconductor strips130, top surfaces of p-type semiconductor strips130and n-type semiconductor strips106may not be substantially level. For example, a top surface of p-type semiconductor strips130may be recessed from a top surface of n-type semiconductor strips106by a distance D3. In some embodiments, D3may be about 12 nm to about 22 nm, for example. Such a height variation between n-type semiconductor strips106and p-type semiconductor strips130may result in various manufacturing and/or device defects. Thus, additional processing may be used to further level top surfaces of n-type semiconductor strips106and p-type semiconductor strips130.

FIGS. 13 through 15illustrate further process steps to level top surfaces of n-type semiconductor strips106and p-type semiconductor strips130. Referring toFIG. 13, a sacrificial layer132is blanket deposited over a top surface of wafer100. In some embodiments, sacrificial layer132comprises a plasma-enhanced oxide (PEOX) deposited using any suitable method, such as CVD, PVD, ALD, and the like. Sacrificial layer132may be used to planarize a top surface of wafer100and to mitigate the height variation between n-type semiconductor strips106and p-type semiconductor strips130. In some embodiments, sacrificial layer132is sufficiently thick to fill (and even overflow) opening126. For example, sacrificial layer132may have a thickness D4of about 200 nm to about 300 nm. Other dimensions may also be used depending on wafer configuration.

InFIG. 14, a planarization may be performed to remove barrier layer122and portions of sacrificial layer132extending over pad layer110. For example, an end-point CMP process may be used to planarize a top surface of wafer100. During the end-point CMP process, pad layer110(e.g., a nitride) may be used as an end point detection layer. During the CMP, sacrificial layer132may be used to resist CMP and prevent damage to underlying p-type semiconductor strips130.

Next, inFIG. 15, a further planarization may be performed to remove pad layer110, pad layer108, and sacrificial layer132. For example, a non-selective CMP process may be used to further planarize wafer100. In some embodiments, the non-selective CMP process may comprise using a chemical slurry which etches pad layer110(e.g., a nitride), pad layer108/sacrificial layer132(e.g., oxides), and n-type semiconductor strips106/p-type semiconductor strips130at a rate of about 1.1 to about 1 to about 0.5, for example.

After planarization, top surfaces of STI regions120, n-type semiconductor strips106, and p-type semiconductor strips130may be substantially level. It has been observed that by using the various processing steps described above with respect toFIGS. 1 through 15, improved fin height uniformity may be achieved. For example, in fins formed using the above described process steps, a height difference between top surfaces of n-type semiconductor strips106and p-type semiconductor strips130may be about 3 nm to about 5 nm, while fins formed using other processing methods may exhibit a height difference be about 12 nm to about 22 nm or even more. Furthermore, the use of various barrier layers/sacrificial layers allows for a relatively small amount of non-selective planarization techniques (e.g., non-selective CMP) while still achieving a suitably planar top surface. Thus, the total height of n-type semiconductor strips106and p-type semiconductor strips130may be maintained at a desired level (e.g., at a desired channel height), which allows for improved device performance and/or reliability in resulting finFETs. For example, in some embodiments, a height of n-type semiconductor strips106and p-type semiconductor strips130(e.g., distance D5) may be about 40 nm. Other dimensions may also be used depending on wafer configuration.

After the formation of fins116and116′ (e.g., comprising semiconductor strips of different types), additional processing may be performed to create finFETs in wafer100. For example, inFIG. 16, STI regions120are recessed, so that top portions of semiconductor strips106and130are higher than the top surfaces of STI regions120. The recessing of STI regions120may include a chemical etch process, for example, using ammonia (NH3) in combination with hydrofluoric acid (HF) or nitrogen trifluoride (NF3) as reaction solutions either with or without plasma. When HF is used as the reaction solution, a dilution ratio of HF may be between about 1:50 to about 1:100.

Channel regions of two different types (e.g., corresponding to n-type semiconductor strips106and p-type semiconductor strips130) are thus formed in fins116/116′. In the completed finFET structures, one or more gate stacks wrap around and covers sidewalls of such channel regions (seeFIG. 17). The resulting structure is shown inFIG. 17. For example, referring toFIG. 17, gate stacks are formed on the top surface and the sidewalls of semiconductor strips106and130. Such gate stacks may include a gate dielectric152and a gate electrode154.

In accordance with some embodiments, gate dielectric152includes silicon oxide, silicon nitride, or multilayers thereof. In alternative embodiments, gate dielectric152includes a high-k dielectric material. In such embodiments, gate dielectric50may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and combinations thereof. The formation methods of gate dielectric152may include molecular beam deposition (MBD), ALD, plasma enhanced CVD (PECVD), or the like. Gate electrode154is formed over gate dielectric152and may include a metal-containing material such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbon (TaC), colbalt (Co), ruthenium (Ru), aluminum (Al), combinations thereof, or multi-layers thereof, for example.

Thus, NMOS finFETS200and PMOS finFETS202may be formed in wafer100having substantially level channel regions (e.g., n-type semiconductor strips106and p-type semiconductor strips130). Although not explicitly illustrated, the formation of finFETS200and202may include additional processing steps including, without limitation, the formation of various dummy gate features prior to gate dielectric153/gate electrode154, the replacement of portions of semiconductor strips106/130(e.g., portions not covered by dummy gate structures) with epitaxially grown source/drain regions doped with p-type impurities (e.g., boron or BF2) or n-type impurities (e.g., phosphorus or arsenic) appropriate type (see e.g.,FIG. 1), the formation of gate spacers on sidewalls of gate electrode154, source/drain and/or gate contacts, and the like. Furthermore, while wafer100illustrates a particular configuration of NMOS finFETs200and PMOS finFETS202, other configurations may be formed in alternative embodiments depending on device configuration.

FIG. 18illustrates an example process flow300for forming finFETs in accordance with some embodiments. In step302, a first fin (e.g., fin116) and a second fin (e.g., fin116′) are formed in a wafer. The first fin includes a first semiconductor strip (e.g., semiconductor strip106) and a first pad nitride layer portion (e.g., pad layer portion110) over the first semiconductor strip, the second fin includes a second semiconductor strip (e.g., semiconductor strip106′) and a second pad nitride layer portion (e.g., pad layer portion110′) over the second semiconductor strip. The first and second semiconductor strips may be of a same type (e.g., either n-type or p-type). Furthermore, the first and second fins may extend upwards from a semiconductor substrate (e.g., SRB layer104), and thus, the first and second fins may further include a first SRB layer portion and a second SRB layer portion, respectively.

In step304, a barrier layer (e.g., barrier layer122) may be blanket deposited over the wafer. In some embodiments, the barrier layer may be deposited over the first and second pad nitride layer portions, and the barrier layer may comprise a different material (e.g., an oxide) than the pad layer portions. In step306, the barrier layer patterned to expose the second fin (e.g., the second pad nitride layer portion of the second fin) while masking the first fin.

Continuing on to steps308through312, the second semiconductor strip is replaced with a third semiconductor strip. The barrier layer may mask the first semiconductor fin while the second semiconductor strip is replaced. In step308, the second semiconductor strip and the second pad nitride layer portion are removed. In step310, a third semiconductor strip (e.g., semiconductor strip130) is epitaxially grown in the second fin. For example, the third semiconductor strip may be epitaxially grown over a SRB layer portion of the second fin. The third semiconductor strip may be of a different type than the first semiconductor strip. For example, when the first semiconductor strip is n-type, the third semiconductor strip may be p-type and vice versa. Epitaxially growing the third semiconductor strip may include growing the third semiconductor strip over top surfaces of adjacent features (e.g., STI regions120). Thus, in step312, a selective CMP is performed to planarize the third semiconductor strip. The selective CMP may include using a chemical slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In step314, after performing the selective CMP, the entire wafer surface is further planarized to remove remaining portions of the barrier layer and the first pad nitride layer. In some embodiments, a sacrificial layer (e.g., sacrificial layer132) may be deposited to level step height variations between different sections of the wafer (e.g., sections masked and exposed by the patterned barrier layer). After the wafer planarization, top surfaces of the first and second fins may be substantially level.

Various embodiments include a method for forming fins of two different types (e.g., n-type and p-type) over a strain relaxed buffer (SRB) layer and a corresponding structure. The process for forming the fins may include forming fins of a first type (e.g., n-type or p-type) by growing a first semiconductor layer over a SRB layer. Subsequently, he first semiconductor layer in a first subset of fins are is with a second semiconductor layer of a second type (e.g., the other of n-type or p-type). The process may include using various barrier and/or sacrificial layers to protect a second subset of fins while the second semiconductor layer is formed. Thus, fins of two different types may be formed having substantially level top surfaces.

In accordance with an embodiment, a method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip. Performing the CMP includes using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer.

In accordance with another embodiment, a method includes forming a first fin and a second fin extending upwards from a strain relaxed buffer (SRB) layer. The first fin includes a first semiconductor strip and a nitride layer over the first semiconductor strip. The second fin includes a second semiconductor strip. The method further includes forming an oxide layer over nitride layer and the second fin, patterning the oxide layer to expose the second fin while masking the first fin, and replacing the second semiconductor strip with a third semiconductor strip. After replacing the second semiconductor strip, remaining portions of the oxide layer and the first nitride layer are removed.

In accordance with yet another embodiment, a method includes forming a first fin and a second fin in a wafer. The first fin includes a first strain relax buffer (SRB) layer portion, a first semiconductor strip on the first SRB layer portion, and a first pad nitride layer portion over the first semiconductor strip. The second fin includes a second strain relax buffer (SRB) layer portion, a second semiconductor strip on the second SRB layer portion, and a second pad nitride layer portion over the second semiconductor strip. A barrier layer is blanket deposited on a top surface of the wafer, wherein the barrier layer is disposed over the first pad nitride layer portion and the second pad nitride layer portion. The method further includes removing the second pad nitride portion and the second semiconductor strip, epitaxially growing a third semiconductor strip over the second SRB layer portion, and performing a selective chemical mechanical polish (CMP) on the third semiconductor strip. Performing the selective CMP includes using a slurry that selectively planarizes the third semiconductor strip at a higher rate than the barrier layer. After performing the selective CMP, removing remaining portions of the barrier layer and the first pad nitride layer to expose the first semiconductor strip.