Thermal management solutions for cored substrates

An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.

TECHNICAL FIELD

Embodiments of the present description generally relate to the removal of heat from integrated circuit packages, and, more particularly, to thermal management solutions for substrates, which are used to form the integrated circuit packages.

BACKGROUND

Higher performance, lower cost, increased miniaturization, and greater packaging density of integrated circuits within integrated circuit devices are ongoing goals of the electronics industry. As these goals are achieved, integrated circuit packages become smaller, which can make thermal management challenging.

These integrated circuit packages may have a variety of configurations. For example, the integrated circuit package may be a “flip chip” package, wherein integrated circuit devices are assembled on a surface of a substrate using interconnects, such as solder bumps or balls. In another example, the integrated circuit package may be an embedded package, wherein the integrated circuit devices (either active or passive) are embedded inside the substrate or a mold layer, and/or at least some of the package redistribution layers are formed directly over the integrated circuit device (e.g. the wafer level, the reconstituted wafer level, or the panel level). Regardless of the type of integrated circuit package, they can run at high temperatures due to embedded integrated circuit devices (active or passive) and/or to self-heating of the metallization (conductive traces and conductive vias) within the substrate from electrical resistance, particularly when high power devices are used in the integrated circuit packages. The high temperatures can cause thermal damage to the materials used to form the substrate, particularly when organic materials are used, which can degrade at temperatures above about 300 degrees Celsius or if kept at extended periods of time at temperatures between about 200 and 250 degrees Celsius. The high temperatures can also cause damage or destruction to integrated circuits within the embedded integrated circuit device (active or passive).

One option to mitigate damage to the materials used to form the substrate is to use ceramic materials rather than using organic materials. Ceramic materials can support considerably higher temperature without degradation. However, they are generally significantly more expensive compared to organic materials and, generally, result in lower density than organic materials, e.g. requiring more layers for the same number of conductive routes within the substrate, as will be understood to those skilled in the art.

Another option to mitigate this thermal issue is to use integrated circuit devices having thermal throttling control that are capable of reducing their operating frequency and, thus, their power in order to operate at a lower temperature and avoid failures. However, this results in a lower overall performance.

A further option is to use metal layers within the substrate for heat dissipation. However, this is generally not sufficiently efficient due to the thinness of the metal layers compared to a traditional heat dissipation device.

DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

The term “package” generally refers to a self-contained carrier of one or more dice, where the dice are attached to the package substrate, and may be encapsulated for protection, with integrated or wire-boned interconnects between the dice and leads, pins or bumps located on the external portions of the package substrate. The package may contain a single die, or multiple dice, providing a specific function. The package is usually mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components, forming a larger circuit.

Here, the term “cored” generally refers to a substrate of an integrated circuit package built upon a board, card or wafer comprising a non-flexible stiff material. Typically, a small printed circuit board is used as a core, upon which integrated circuit device and discrete passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials.

Here, the term “coreless” generally refers to a substrate of an integrated circuit package having no core. The lack of a core allows for higher-density package architectures, as the through-vias have relatively large dimensions and pitch compared to high-density interconnects.

Here, the term “land side”, if used herein, generally refers to the side of the substrate of the integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term “die side”, which is the side of the substrate of the integrated circuit package to which the die or dice are attached.

Here, the term “dielectric” generally refers to any number of non-electrically conductive materials that make up the structure of a package substrate. For purposes of this disclosure, dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dice mounted on the substrate.

Here, the term “metallization” generally refers to metal layers formed over and through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of a package substrate may be confined to a single layer or in multiple layers separated by layers of dielectric.

Here, the term “bond pad” generally refers to metallization structures that terminate integrated traces and vias in integrated circuit packages and dies. The term “solder pad” may be occasionally substituted for “bond pad” and carries the same meaning.

Here, the term “solder bump” generally refers to a solder layer formed on a bond pad. The solder layer typically has a round shape, hence the term “solder bump”.

Here, the term “substrate” generally refers to a planar platform comprising dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC dies on a single platform, with encapsulation of the one or more IC dies by a moldable dielectric material. The substrate generally comprises solder bumps as bonding interconnects on both sides. One side of the substrate, generally referred to as the “die side”, comprises solder bumps for chip or die bonding. The opposite side of the substrate, generally referred to as the “land side”, comprises solder bumps for bonding the package to a printed circuit board.

Here, the term “assembly” generally refers to a grouping of parts into a single functional unit. The parts may be separate and are mechanically assembled into a functional unit, where the parts may be removable. In another instance, the parts may be permanently bonded together. In some instances, the parts are integrated together.

The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluidic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The vertical orientation is in the z-direction and it is understood that recitations of “top”, “bottom”, “above” and “below” refer to relative positions in the z-dimension with the usual meaning. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.

Views labeled “cross-sectional”, “profile” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.

Embodiments of the present description may include an integrated circuit assembly having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.

FIG.1illustrates a substrate core110having a first surface112, an opposing second surface114, at least one sidewall116extending between the first surface112and the second surface114, and at least one heat transfer fluid channel118formed within the substrate core110. In one embodiment, as shown inFIG.1, the heat transfer fluid channels118of the substrate core110may be designed to allow a heat transfer fluid (illustrated as arrows120) to enter (arrow120on left side ofFIG.1) and an exit (arrow on right side ofFIG.1) along the at least one sidewall116of the substrate core110. The substrate core110may be any appropriate substantially rigid material, including, but not limited to, fire retardant grade4material, glass reinforced epoxy matrix material, glass, ceramics, and the like.

The heat transfer fluid120may be any appropriate gas or liquid, or a combination thereof. In one embodiment, the heat transfer fluid120may comprise air. In another embodiment, the heat transfer fluid120may comprise water. In still another embodiment, the heat transfer fluid120may comprise a dielectric refrigerant. In a further embodiment, the heat transfer fluid120may comprise an oil. In other embodiments, the heat transfer fluid120may be comprised of two phases (such as liquid water and water vapor, or liquid-phase and gas-phase dielectric refrigerant) that exist simultaneously in one or more regions of the heat transfer fluid channel(s)118.

The heat transfer fluid channel(s)118may have any appropriate configuration to facilitate heat removal. In one embodiment, shown inFIG.2, which is a view along line2-2ofFIG.1, the heat transfer fluid channel118may be a single structure, which, in general, directs the heat transfer fluid120linearly (illustrated left to right). In another embodiment, shown inFIG.3, the substrate core110may have a plurality of heat transfer fluid channels that are substantially aligned in parallel.

In one embodiment of the present description, shown inFIGS.4and5, the heat transfer fluid channels118of the substrate core110may be designed to allow the heat transfer fluid120) to enter through an inlet port122extending from the first surface112of the substrate core110and an exit through an outlet port124extending from the first surface112of the substrate core110.

In one embodiment, as shown inFIGS.6-9, the heat transfer fluid channels118may be formed in a “defect” mode. As shown inFIG.6, a trench132may be formed in the substrate core110extending from the first surface112thereof, such as by etching, laser ablation, ion bombardment, and the like. A metal layer134, such as copper, aluminum, alloys thereof, and the line, may then be formed, such as by plating, over the first surface112of the substrate core110and into the trench132. It is understood, that a seed layer, as known in the art, may be deposited over the first surface112of the substrate core110and into the trench132prior to the formation of the metal layer134. As the metal layer134is formed, an overhang136forms at the first surface112of the substrate core110, as shown in theFIG.7. As the formation of the metal layer134continues, the overhang136(seeFIG.7) seals the trench132to form a void which becomes the heat transfer fluid channel118, as shown inFIG.8. This void is generally considered a defect when trying to fill a trench, such as the trench132; however, in this process, the defect is used advantageously to form the heat transfer fluid channel118. As shown inFIG.9, the metal layer134may be planarized, such as by chemical mechanical polishing (CMP) to expose the first surface112of the substrate core110.

In another embodiment, as shown inFIGS.10-14, the heat transfer fluid channels118may be formed by etching. As shown inFIG.10, a metal block142, such as copper, aluminum, alloys thereof, and the line, may be formed as a part of the substrate core110. An etch mask144, such as a layer of nickel, may be formed over the substrate core110and the metal block142with an opening146patterned over the metal block142, as shown inFIG.11. As shown inFIG.12, the metal block142may be isotropically etched (shown as arrow140), such that the etch undercuts the etch mask144to form a cavity148, which becomes the heat transfer fluid channel118(seeFIG.1). If there is a potential of the subsequent processing materials (not shown) entering the cavity148, a capping layer138may be formed over the etch mask144to seal the opening146in the etch mask144. In one embodiment, the capping layer138may be a metal plated on the etch mask144. As discussed with regard to the embodiment ofFIGS.6-9, the plated metal layer may form an overhang (not shown) which seals over the opening146of the etch mask136. In another embodiment, as shown inFIG.14, the etch mask144may be removed and the capping layer138may be formed over the substrate core110, the metal block142, and the cavity148to form the heat transfer fluid channel118. In one embodiment ofFIG.14, the capping layer138may be laminated over the substrate core110, the metal block142, and the cavity148.

As shown inFIGS.15and16, the substrate core110ofFIG.1andFIG.4, respectively, may be incorporated into a substrate100. As shown inFIG.15, a first build-up layer150may be formed adjacent the first surface112of the substrate core110, and a second build-up layer160may be formed adjacent the second surface114of the substrate core110to form the substrate100. The first build-up layer150may comprise a plurality of dielectric layers (not shown) with a plurality of conductive routes158(shown as dashed lines) extending through the first build-layer150. The conductive routes158of the first build-up layer150may be comprise a plurality of conductive traces (not shown) formed on the plurality of dielectric layers (not shown) with a plurality of conductive vias (not shown) extending through respective dielectric layers (not shown) to electrically connect the plurality of conductive traces (not shown). Likewise, the second build-up layer160may comprise a plurality of dielectric layers (not shown) with a plurality of conductive routes168(shown as dashed lines) extending through the second build-up layer160. The conductive routes168of the second build-up layer160maybe comprise a plurality of conductive traces (not shown) formed on the plurality of dielectric layers (not shown) with a plurality of conductive vias (not shown) extending through respective dielectric layers (not shown) to electrically connect the plurality of conductive traces (not shown). As shown inFIG.15, at least one of the conductive routes158of the first build-up layer150and at least one of the conductive routes168of the second build-up layer160may be electrically connected to one another with an electrical connector170, such as a plated through-hole, extending from the first surface112of the substrate core110to the second surface114of the substrate core110, which allows for electrical signals to be transmitted through the substrate core110. The conductive routes158of the first build-up layer150and the conductive routes158of the second build-up layer160may be referred to herein as “metallization”. The processes for layering the dielectric material layers and forming the conductive routes158,168for the first build-up layer150and the second build-up layer160, respectively, as well as the processes for forming the electrical connector170, are well known in the art and for purposes of brevity and conciseness will not be described herein.

The substrate100may be any appropriate structure, including, but not limited to, an interposer, a printed circuit board, a motherboard, and the like. The dielectric material layers (not shown) of the substrate100may include build-up films and/or solder resist layers, and may be composed of an appropriate dielectric material, including, but not limited to, bismaleimide triazine resin, polyimide materials, silica filled epoxy, and the like, as well as laminates or multiple layers thereof. The conductive routes158and168may be composed of any conductive material, including but not limited to metals, such as copper, aluminum, and alloys thereof.

In one embodiment of the present description, an integrated circuit device180may be electrically attached to the substrate100with a plurality of interconnects186, to form an integrated circuit assembly, such as an integrated circuit package190. In one embodiment, the interconnects186may extend between bond pads184on a first surface182of the integrated circuit device180, which are in electrical communication with integrated circuitry (not shown) within the integrated circuit device180, and bond pads154on a first surface152of the first build-up layer150of the substrate100, which are in contact with the conductive routes158. As will be understood to those skilled in the art, the substrate100may reroute a fine pitch (center-to-center distance between the bond pads) of the bond pads184of the integrated circuit device180to a relatively wider pitch of bond pads164on a first surface162of the second build-up layer160of the substrate100. It is further understood that the bond pads164may be connected through interconnects (not shown) to a motherboard or other external components (not shown).

The integrated circuit device180may be any appropriate device, including, but not limited to a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, combinations thereof, stacks thereof, or the like. The interconnects186may be any appropriate electrically conductive material, including, but not limited to metal filled epoxies and solders, such as tin, lead/tin alloys (for example, 63% tin/37% lead solder), and high tin content alloys (e.g. 90% or more tin—such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys).

The substrate100may include embedded components that generate significant heat, such as an inductor, shown as a first inductor172and a second inductor174, formed in at least one of the first build-up layer150and the second build-up layer160. Inductors are passive two-terminal electrical devices that store energy in a magnetic field when electrical current flows through it and are used to store an electrical charge. Inductors are generally a portion of a voltage regulator circuit, which precisely controls the voltage and current of integrated circuit devices, such as the integrated circuit device180. In one embodiment, the first inductor172may be electrically attached to the integrated circuit device180through respective conductive routes158of the first build-up layer150. In an embodiment of the present description, the second inductor174may be electrically attached to the integrated circuit device180through respective conductive routes168of the second build-up layer160, electrical connectors170, and conductive routes158of the first build-up layer150. In one embodiment of the present description, at least one of the first inductor172and the second inductor174may be formed separately and embedded in the substrate100. In another embodiment of the present description, at least one of the first inductor172and the second inductor174may be formed as a part of the substrate100during the fabrication thereof using the conductive traces (not shown) and conductive vias (not shown). In a further embodiment of the present description, at least one of the first inductor172and the second inductor174may be an air coil inductor, as known in the art.

As shown inFIG.16, the substrate core110ofFIG.4, may be incorporated into the substrate100in a manner described with regard to the embodiment ofFIG.15. As shown inFIG.16, the substrate100may include a first heat transfer fluid conduit126, which may extend from the first surface152of the first build-up layer150to the inlet port122of the substrate core110, and a second heat transfer fluid conduit128, which may extend from the outlet port124of the substrate core110to the first surface152of the first build-up layer150. The heat transfer fluid120(illustrated generically as a down arrow (left side) and an up arrow (right side)), which may be used to remove heat from the substrate100, may flow into the at least one heat transfer fluid channel118from the first heat transfer conduit126and out of the at least one heat transfer fluid channel118through the second heat transfer conduit128.

AlthoughFIGS.15and16illustrate a single integrated circuit device180, the embodiments of the present description are not so limited, as the integrated circuit package190may have a plurality of integrated circuit devices. In further embodiments of the present description, integrated circuit devices may be embedded in the substrate100in the first build-up layer150and/or the second build-up layer160.

FIG.17is a flow chart of a process200of fabricating an integrated circuit assembly according to an embodiment of the present description. As set forth in block202, a substrate core may be formed having a first surface and an opposing second surface. At least one heat transfer fluid channel may be formed within the substrate core between the first surface and the second surface, as set forth in block204. As set forth in block206, a first build-up layer may be formed adjacent the first surface of the substrate core. A second build-up layer may be formed adjacent the second surface of the substrate core, as set forth in block208.

FIG.18illustrates an electronic or computing device300in accordance with one implementation of the present description. The computing device300may include a housing301having a board302disposed therein. The board302may include a number of integrated circuit components, including but not limited to a processor304, at least one communication chip306A,306B, volatile memory308(e.g., DRAM), non-volatile memory310(e.g., ROM), flash memory312, a graphics processor or CPU314, a digital signal processor (not shown), a crypto processor (not shown), a chipset316, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the integrated circuit components may be physically and electrically coupled to the board302. In some implementations, at least one of the integrated circuit components may be a part of the processor304.

At least one of the integrated circuit components may include an integrated circuit assembly, comprising a substrate core having a first surface and an opposing second surface, at least one heat transfer fluid channel within the substrate core between the first surface and the second surface, a first build-up layer adjacent the first surface of the substrate core, and a second build-up layer adjacent the second surface of the substrate core.

It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated inFIGS.1-18. The subject matter may be applied to other integrated circuit devices and assembly applications, as well as any appropriate electronic application, as will be understood to those skilled in the art.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.