ELECTROSTATIC DISCHARGE PROTECTION DEVICE

An ESD protection device includes a substrate, an epitaxial layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxial layer. The third well region is disposed between the first and second well regions. The first and second doped regions are disposed on the first well region and coupled to a pad. The third and fourth doped regions are disposed on the second well region and coupled to a ground terminal. The fifth doped region is disposed on the third well region, and the sixth doped region is disposed in the fifth doped region. The third, fifth, and sixth doped regions have the same conductive type. In response to an electrostatic discharge event occurring on the pad, a discharge path is formed between the pad and the ground terminal.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an electrostatic discharge (ESD) protection device, and more particularly, to a bidirectional electrostatic discharge protection device.

Description of the Related Art

As the process of manufacturing integrated circuits has developed, the size of semiconductor components has been reduced to the sub-micron level to improve the performance and operation speed of the integrated circuits. However, this reduction of the size of components has caused some reliability problems. This is particularly true for integrated circuits, in which protection against electrostatic discharge (ESD) is seriously affected. Therefore, there is a need in the art for devices that can effectively provide paths for electrostatic discharge.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention provides an electrostatic discharge protection device. The electrostatic discharge protection device comprises a semiconductor substrate, an epitaxial layer, a first well region, a second well region, a third well region, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, and a sixth doped region. The semiconductor substrate has a first conductivity type. The epitaxial layer is located on the semiconductor substrate and has the first conductivity type. The first well region is disposed in the epitaxial layer and has the first conductivity type. The second well region is disposed in the epitaxial layer and has the first conductivity type. The third well region is set in the epitaxial layer and is located between the first well region and the second well region. The third well region has a second conductivity type that is the opposite of the first conductivity type. The first doped region is disposed on the first well region and has the first conductivity type. The second doped region is disposed on the first well region, and the second doped region has a second conductivity type. The third doped region is disposed on the second well region and has the first conductivity type. The fourth doped region is disposed on the second well region and has the second conductivity type. The fifth doped region is disposed on the third well region and has the second conductivity type. The sixth doped region is disposed in the fifth doped region and has the second conductivity type. The first doped region and the second doped region are coupled to a bonding pad, and the third doped region and the fourth doped region are coupled to a ground terminal. When an electrostatic discharge event occurs on the bonding pad, a discharge path is formed between the bonding pad and the ground.

DETAILED DESCRIPTION OF THE INVENTION

FIG.1is a schematic cross-sectional view of an electrostatic discharge (ESD) protection device according to one embodiment of the present invention. Referring toFIG.1, the electrostatic discharge protection device1is a bidirectional electrostatic discharge protection device. When an electrostatic discharge event occurs on a bonding pad10, the electrostatic discharge protection device1provides a discharge path in the direction from the bonding pad10to a ground terminal TGND or provides a discharge path in the direction from the ground terminal TGND to the bonding pad10. The electrostatic discharge protection device1comprises a semiconductor substrate100, an epitaxial layer101, a buried layer102, well regions103-106, doped regions107-112, isolation patterns113-116, and gate structures117and118. The doped regions107and108and the gate structure117are coupled to the bonding pad10, and the doped regions109and110and the gate structure118are coupled to the ground terminal TGND.

In the embodiment, the semiconductor substrate100may comprise a silicon substrate. Alternatively, SiGe, a bulk semiconductor, a strained semiconductor, a compound semiconductor or other commonly used semiconductor substrates may be used as the semiconductor substrate100. In the embodiment, the semiconductor substrate100may be doped with P-type or N-type dopants to change its conductive type according to customer designs. In the embodiment ofFIG.1, the semiconductor substrate100may have a first conductive type such as P-type.

Referring toFIG.1, an epitaxial layer101is formed on a semiconductor substrate100. In the embodiment, the conductivity type of the epitaxial layer101is P-type (first conductivity type). The buried layer102is disposed at an interface119between the epitaxial layer101and the semiconductor substrate100. In the embodiment, the buried layer102has a second conductivity type such as N-type.

As shown inFIG.1, the well regions103-106are disposed in the epitaxial layer101. In the embodiment, the conductivity types of the well regions103and104are P-type (the first conductivity type), and the conductivity types of the well regions105and106are N-type (the second conductivity type). In order to clearly illustrate the arrangement and the conductivity types of the well regions103-106, hereinafter, the well regions103and104are referred to as P-type well regions, and the well regions105and106are referred to as N-type well regions. Referring toFIG.1, the P-type well region103is disposed between the N-type well regions105and106, and the N-type well region106is disposed between the P-type well regions103and104. The bottom surface of the P-type well region103, the bottom surface of the N-type well region105, and the bottom surface of the N-type well region106are all connected to or contact with the buried layer102.

Referring toFIG.1, both of the doped regions107and108are disposed on the P-type well region103. Referring toFIG.1, the doped region107is adjacent to the N-type well region105, and the doped region108is adjacent to the N-type well region106. The doped regions107and108are coupled to the bonding pad10. In the embodiment, the conductivity type of the doped region107is P-type, and the doped region107may be implemented as a P-type heavily doped (P+) region. The conductivity type of the doped region108is N-type, and the doped region108may be implemented as an N-type heavily doped (N+) region. In order to clearly illustrate the arrangement and the conductivity types of the doped regions107and108, hereinafter, the doped region107is referred to as a P-type doped region, and the doped region108is referred to as an N-type doped region.

As shown inFIG.1, both of the doped regions109and110are disposed on the P-type well region104. Referring toFIG.1, the doped region110is adjacent to the N-type well region106, and the doped region109is far away from the N-type well region106. The doped regions109and110are coupled to the ground terminal TGND. In the embodiment, the conductivity type of the doped region109is P-type, and the doped region109may be implemented as a P-type heavily doped (P+) region. The conductivity type of the doped region110is N-type, and the doped region110may be implemented as an N-type heavily doped (N+) region. In order to clearly illustrate the arrangement and the conductivity types of the doped regions109and110, hereinafter, the doped region109is referred to as a P-type doped region, and the doped region110is referred to as an N-type doped region.

Referring toFIG.1, the doped region111is disposed on the N-type well region106. The doped region112is disposed in the doped region111, and the boundary of the doped region112is surrounded by the doped region111. In the embodiment, the conductivity type of the doped region111is N-type, and the doped region111may be implemented as an N-type doped drift (NDD) region. The conductivity type of the doped region112is N-type, and the doped region112may be implemented as an N-type heavily doped (N+) region. In order to clearly illustrate the arrangement and the conductivity types of the doped regions111and112, hereinafter, the doped region111is referred to as an NDD region, and the doped region112is referred to as an N-type doped region. The NDD region111has two sidewalls W111A and W111B that are opposite to each other. In the embodiment ofFIG.1, the NDD region111extends from the N-type well region106toward the P-type well region103so that the sidewall W111A of the NDD region111is in contact with the P-type well region103. Moreover, the NDD region111is formed by the N-type well region106extends toward the P-type well region104so that the sidewall W111B of the NDD region111is in contact with the P-type well region104. Therefore, the NDD region111is disposed on the P-type well regions103and104and the N-type well region106. Specifically, the NDD region111completely overlaps the N-type well region106, the NDD region111partially overlaps the P-type well region103, and the NDD region111also partially overlaps the P-type well region104.

As shown inFIG.1, the isolation patterns113-116are disposed on the epitaxial layer101. In the embodiment, the isolation patterns113-116may be shallow trench isolation (STI) features. Referring toFIG.1, the isolation pattern113fully covers the N-type well region105and partially covers the P-type well region103, the isolation pattern114is disposed between the P-type doped region107and the N-type doped region108, the isolation pattern115is disposed between the P-type doped region109and the N-type doped region110, and the isolation pattern116partially covers the P-type well region104.

Referring toFIG.1, the gate structures117and118are respectively disposed on the P-type well regions103and104. The gate structure117is disposed between the N-type doped region108and the NDD region111and coupled to the bonding pad10. The gate structure118is disposed between the N-type doped region110and the NDD region111and coupled to the ground terminal TGND. According to the embodiment, each of the gate structures117and118may be constructed by a lower gate insulating layer and an upper gate layer. In the embodiment, the gate insulating layer may comprise commonly used dielectric materials such as oxide, nitride, oxynitride, oxycarbide, or combinations thereof. In another embodiment, the gate insulating layer may comprise high-dielectric constant (k) dielectric material such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO4), zirconium oxide, (ZrO2), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO4), yttrium oxide (Y2O3), lanthanum oxide (La2O3), cerium oxide (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), or combinations thereof. Further, in an embodiment, the gate layer may comprise silicon or polysilicon. In another embodiment, the gate layer may comprise amorphous silicon.

FIG.2is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device1. As shown inFIG.2, the equivalent circuit of the electrostatic discharge protection device1comprises equivalent elements20-24. Referring toFIG.1andFIG.2, the P-type doped region107, the P-type well region103, the N-type buried layer102, the N-type well region106, the P-type well region104, and the P-type doped region109are commonly form a PNP-type bipolar junction transistor (PNP BJT)20, wherein the P-type doped region107and the P-type well region103serve as the first collector/emitter of the PNP BJT20, the N-type buried layer102and the N-type well region106serve as the base of the PNP BJT20, and the P-type well region104and the P-type doped region109serve as the second collector/emitter of the PNP BJT20. The first collector/emitter of the PNP BJT20is coupled to the bonding pad10, and the second collector/emitter of the PNP BJT20is coupled to the ground terminal TGND. Whether the first collector/emitter and the second collector/emitter of the PNP BJT20serves as a collector and an emitter respectively or as an emitter and a collector respectively depends on the polarity of the voltage caused by an electrostatic discharge event on the bonding pad10(a positive electrostatic discharge event or a negative electrostatic discharge event). Therefore, inFIG.2, a solid arrow and a hollow arrow are used to indicate the emitter of the PNP BJT20respectively the different polarities of the above-mentioned voltage, and the related details will be described later.

The N-type doped region108, the P-type well region103, the NDD region111, and the N-type doped region112commonly forms an N-P-N-type bipolar junction transistor (NPN BJT)21, wherein the N-type doped region108serves as the emitter of the NPN BJT21, the P-type well region103serves as the base of the NPN BJT21, and the NDD region111and the N-type doped region112serve as the collector of the NPN BJT21. The N-type doped region110, the P-type well region104, the NDD region111, and the N-type doped region112commonly form an NPN BJT22, wherein the N-type doped region110serves as the emitter of the NPN BJT22, and the P-type well region103serves as the base of the NPN BJT22, and the NDD region111and the N-type doped region112serve as the collector of the NPN BJT22. Referring toFIG.2, according to the structure shown inFIG.1, the emitter and the base of the NPN BJT21are coupled to the bonding pad10, the collector of the NPN BJT21, the base of the PNP BJT20, and the collector of the NPN BJT22are commonly coupled to the node N20, the emitter and the base of the NPN BJT22are coupled to the ground terminal TGND. The node N20corresponds to the N-type buried layer102, the N-type well region106, the NDD region111, and the N-type doped region112whose conductivity types are N-type and which are connected to each other inFIG.1.

Referring toFIG.1andFIG.2, the N-type doped region108, the gate structure117, and the N-type doped region112commonly form an N-type metal oxide semiconductor (NMOS) transistor23, wherein, the N-type doped region108serves as the source of the NMOS transistor23, the gate structure117serves as the gate of the NMOS transistor23, and the N-type doped region112serves as the drain of the NMOS transistor23. The N-type doped region110, the gate structure118, and the N-type doped region112commonly form an NMOS transistor24, wherein the N-type doped region110serves as the source of the NMOS transistor24, and the gate structure118serves as the gate of the NMOS transistor24, and the N-type doped region112serves as the drain of the NMOS transistor24. Referring toFIG.2, according to the structure ofFIG.1, the gate and the source of the NMOS transistor23are coupled to the bonding pad10, the drain of the NMOS transistor23and the drain of the NMOS transistor24are coupled to the node N20, and the gate and the source of the transistor24are coupled to the ground terminal TGND.

Referring toFIG.1, when an electrostatic discharge event occurs on the bonding pad10to cause a positive voltage (or, when a positive electrostatic discharge event occurs on the bonding pad10), the bonding pad10, a discharge path is formed through the P-type The doped region107, the P-type well region103, the NDD region111, the N-type doped region112, the P-type well region104, the N-type doped region110, and the ground terminal TGND so that the electrostatic charges on the bonding pad10are conducted to the ground terminal TGND through this discharge path. That is, the above discharge path is from the bonding pad10and finally to the ground terminal TGND through a P-N-P-N junction. From the viewpoint of the equivalent circuit of the electrostatic discharge protection device1, referring toFIG.2, when an electrostatic discharge event occurs on the bonding pad10to cause a positive voltage, the PNP BJT20and the NPN BJT22are turned on. At this time, the first collector/emitter of the PNP BJT20serves as the emitter (indicated by the solid arrow). The PNP BJT20and the NPN BJT22form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure shown inFIG.1, the electrostatic charges on the bonding pad10are conducted to the ground terminal TGND through the emitter and the base of the PNP BJT20and the collector, the base and the emitter of the NPN BJT22in sequence. In addition, the NMOS transistor24is turned on, and, thus, some of the electrostatic charges are conducted to the ground terminal TGND through the NMOS transistor24.

Referring toFIG.1, when an electrostatic discharge event occurs on the bonding pad10to cause a negative voltage (or, when a negative electrostatic discharge event occurs on the bonding pad10), a discharge path is formed through the ground terminal TGND, the P-type doped region109, the P-type well region104, the NDD region111, the N-type doped region112, the P-type well region103, the N-type doped region108, and the bonding pad10so that the charges on the ground terminal TGND are conducted to the bonding pad10through this discharge path. That is, the above discharge path is from the ground terminal TGND and finally to the bonding pad10through a P-N-P-N junction. From the viewpoint of the equivalent circuit of the electrostatic discharge protection device1, referring toFIG.2, when an electrostatic discharge event occurs on the bonding pad10to cause a negative voltage, the PNP BJT20and the NPN BJT21are turned on. At this time, the second collector/emitter of the PNP BJT20serves as the emitter (indicated by the hollow arrow). The PNP BJT20and the NPN BJT21form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure in FIG., the charges on the ground terminal TGND are conducted to the bonding pad10through the emitter and the base of the PNP BJT20, the collector, the base, and the emitter of the NPN BJT21in sequence. In addition, the NMOS transistor23is turned on, and, thus, some of the electrostatic charges are conducted to the ground terminal TGND through the NMOS transistor23.

Referring toFIG.1, the P-type well region103and the NDD region111form a first parasitic diode, and the P-type well region104and the NDD region111form a second parasitic diode. When a positive electrostatic discharge event occurs on the bonding pad10, the second parasitic diode is reversely biased; when a negative electrostatic discharge event occurs on the bonding pad10, the first parasitic diode is reversely biased. Therefore, the respective breakdown voltages of the first parasitic diode and the second parasitic diode affect the performance of the electrostatic discharge in the embodiment. According to an embodiment of the present invention, the respective breakdown voltages of the first parasitic diode and the second parasitic diode may be determined by changing the position of the NDD region111relative to the N-type well region106.

Referring toFIG.3, the position of the NDD region111relative to the N-type well region106is different from the embodiment shown inFIG.1. As shown inFIG.3, the NDD region111extends from the N-type well region106toward the P-type well region104, so that the sidewall W111B of the NDD region111is in contact with the P-type well region104. That is, the NDD region111extends above the P-type well region104and partly overlaps the P-type well region104. However, the NDD region111does not extend above the P-type well region103. The sidewall W111A of the NDD region111is in contact with the N-type well region106, that is, the sidewall W111A is in the N-type well region106. Compared with the embodiment shown inFIG.1, the breakdown voltage of the first parasitic diode formed in the P-type well region103and the N-type well region106inFIG.3is higher. In addition, in the embodiment ofFIG.3, the breakdown voltage of the first parasitic diode is greater than the breakdown voltage of the second parasitic diode formed in the P-type well region104and the NDD region111, which is beneficial to trigger formation of a discharge path when a positive electrostatic discharge event occurs on the bonding pad10.

In another embodiment, as shown inFIG.4, the NDD region111extends from the N-type well region106toward the P-type well region103so that the sidewall W111A of the NDD region111is in contact with the P-type well region103. That is, the NDD region111extends above the P-type well region103and partially overlaps with the P-type well region103. However, the NDD region111does not extend above the P-type well region104. The sidewall W111B of the NDD region111is in contact with the N-type well region106, that is, the sidewall W111B is in the N-type well region106. Compared withFIG.1, the breakdown voltage of the second parasitic diode formed in the P-type well region104and the N-type well region106inFIG.4is higher. In addition, in the embodiment ofFIG.4, the breakdown voltage of the second parasitic diode is greater than the breakdown voltage of the first parasitic diode formed in the P-type well region103and the NDD region111, which is beneficial to trigger formation of a discharge path when a negative electrostatic discharge event occurs on the bonding pad10.

FIG.5is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. Referring toFIG.1andFIG.5, the difference between the electrostatic discharge protection device5shown inFIG.5and the electrostatic discharge protection device1shown inFIG.1is that the electrostatic discharge protection device5further comprises doped regions500-502and the isolation patterns503-505. Moreover, the electrostatic discharge protection device5does not comprise the gate structures117and118of the electrostatic discharge protection device1. In the embodiment, the conductivity types of the doped regions500and501are P-type, and the doped regions500and501may be implemented as P-type doped drift (PDD) regions. The conductivity type of the doped region502is N-type, and the doped region502may be implemented as an N-type heavily doped (N+) region. In order to clearly illustrate the arrangement and the conductivity types of the doped regions500-502, hereinafter, the doped regions500and501are referred to as PDD regions, and the doped region502is referred to as an N-type doped region.

As shown inFIG.5, the PDD region500is disposed on the P-type well region103, and the boundary of the PDD region500is surrounded by the P-type well region103. The PDD region501is disposed on the P-type well region104, and the boundary of the PDD region501is surrounded by the P-type well region104. Under this arrangement, the P-type doped region107and the N-type doped regions108and502are disposed in the PDD region500, and the P-type doped region109and the N-type doped region110are disposed in the PDD region501. The N-type doped region502is adjacent to the N-type well region105and coupled to the bonding pad10. The P-type doped region107is disposed between the N-type doped regions108and502.

Different from the embodiments shown inFIGS.1,3, and4, the boundary of the NDD region111inFIG.5is surrounded by the N-type well region106, that is, the NDD region111does not overlap the P-type well regions103and104. In addition, the isolation patterns503-505are disposed on the epitaxial layer101. In the embodiment, the isolation patterns503-505may be shallow trench isolation (STI) features. The isolation pattern503is disposed between the P-type doped region107and the N-type doped region502. The isolation pattern504is disposed between the PDD region500and the NDD region111and partially covers the P-type well region103and the N-type well region106. The isolation pattern505is disposed between the PDD region501and the NDD region111and partially covers the P-type well region104and the N-type well region106.

FIG.6is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device5. According to the above description, the PDD region500has the same conductivity type as the P-type well region103, and the PDD region501has the same conductivity type as the P-type well region104. Therefore, like the electrostatic discharge protection circuit1, equivalent components of the electrostatic discharge protection device5comprise a PNP BJT20, an NPN BJT21, and an NPN BJT22. In the embodiment ofFIG.5, since the electrostatic discharge protection device5does not comprise the gate structures117and118of the electrostatic discharge protection device1, the equivalent elements of the electrostatic discharge protection device5do not comprises the NMOS transistors23and24.

In the embodiments ofFIG.5andFIG.6, when a positive electrostatic discharge event or a negative electrostatic discharge event occurs on the bonding pad10, a current path is formed through a P-N-P-N junction of a silicon controlled rectifier (SCR), which similar to the embodiments inFIG.1andFIG.2. Thus, the related description is omitted here.

Similarly, the respective breakdown voltages of the first parasitic diode formed between the P-type well region103and the NDD region111and the second parasitic diode formed between the P-type well region104and the NDD region111inFIG.1can be determined by changing the position of the NDD region111relative to the N-type well region106.

Referring toFIG.7, the NDD region111extends from the N-type well region106toward the P-type well region103so that the sidewall W111A of the NDD region111is in contact with the P-type well region103. That is, the NDD region111extends above the P-type well region103and partly overlaps the P-type well region103. However, the NDD region111does not extend above the P-type well region104. The sidewall W111B of the NDD region111is in contact with the N-type well region106, that is, the sidewall W111B is in the N-type well region106. Compared withFIG.5, the NDD region111extends from the N-type well region106toward the P-type well region103, resulting in that the breakdown voltage of the first parasitic diode between the P-type well region103and the NDD region111is lower, which is beneficial to triggering the formation of a discharge path when a negative electrostatic discharge event occurs on the bonding pad10.

Referring toFIG.8, the NDD region111extends from the N-type well region106toward the P-type well region104so that the sidewall W111B of the NDD region111is in contact with the P-type well region104. That is, the NDD region111extends above the P-type well region104and partly overlaps with the P-type well region104. However, the NDD region111does not extend above the P-type well region103. The sidewall W111A of the NDD region111is in contact with the N-type well region106, that is, the sidewall W111A is in the N-type well region106. Compared toFIG.5, the NDD region111extends from the N-type well region106toward the P-type well region104inFIG.8, resulting in that the breakdown voltage of the second parasitic diode between the P-type well region104and the NDD region111is lower, which is beneficial to trigger formation of a discharge path when a positive electrostatic discharge event occurs on the bonding pad10.

FIG.9is a schematic cross-sectional view showing an electrostatic discharge (ESD) protection device according to another embodiment of the present invention. Referring toFIG.9, the electrostatic discharge protection device9is a bidirectional electrostatic discharge protection device. When an electrostatic discharge event occurs on a bonding pad90, the electrostatic discharge protection device9provides a discharge path in the direction from the bonding pad90to a ground terminal TGND or a discharge path in the direction from the ground terminal TGND to the bonding pad90. The electrostatic discharge protection device9comprises a semiconductor substrate900, an epitaxial layer901, a buried layer902, well regions903-906, doped regions907-916, and isolation patterns917-923. The doped regions910-912are coupled to the bonding pad90, and the doped regions913-915are coupled to the ground terminal TGND. In the embodiment, the electrostatic discharge protection device9is formed by a process for manufacturing high-voltage devices.

In the embodiment, the semiconductor substrate900may comprise a silicon substrate. Alternatively, SiGe, a bulk semiconductor, a strained semiconductor, a compound semiconductor or other commonly used semiconductor substrates may be used as the semiconductor substrate900. In the embodiment, the semiconductor substrate900may be doped with P-type or N-type dopants to change its conductive type according to customer designs. In the embodiment ofFIG.9, the semiconductor substrate900may have a first conductive type such as P-type.

Referring toFIG.9, an epitaxial layer901is formed on a semiconductor substrate900. In the embodiment, the conductivity type of the epitaxial layer901is P-type (first conductivity type). The buried layer902is disposed at an interface924between the epitaxial layer901and the semiconductor substrate900. In the embodiment, the buried layer902has a second conductivity type such as N-type.

As shown inFIG.9, well regions903-906are disposed in the epitaxial layer901. In the embodiment, the conductivity types of the regions903and904are P-type (first conductivity type), and the regions903and904may be implemented as high-voltage P-type well regions (HVPW). The conductivity types of the well regions905and906are N-type (second conductivity type), and the well regions905and906may be implemented as N-type deep well regions (DHVNW). In order to clearly illustrate the arrangement and the conductivity types of the well regions903-906, hereinafter, the well regions903and904are referred to as high-voltage P-type well regions, and the well regions905and906are referred to as N-type deep well regions. Referring toFIG.9, the high-voltage P-type well region903is disposed between the N-type deep well regions905and906, and the N-type deep well region906is disposed between the high-voltage P-type well regions903and904. The bottom surface of the high-voltage P-type well region903, the bottom surface of the high-voltage P-type well region904, the bottom surface of the N-type deep well region905, and the bottom surface of the N-type deep well region906are all connected to or contact with the buried layer902.

As shown inFIG.9, the doped region907is disposed on the high-voltage P-type well region903, the doped region908is disposed on the high-voltage P-type well region903and the N-type deep well region906, and the doped region909is disposed on the high-voltage P-type well region906. The conductivity types of the doped regions907and909are P-type, and the doped regions907and909may be implemented as P-type well regions. The conductivity type of the doped region908is N-type, and the doped region908may be implemented as an N-type well region. In order to clearly illustrate the arrangement and the conductivity types of the well regions907-909, hereinafter, the doped regions907and909are referred to as P-type well regions, and the doped region908is referred to as a N-type well region. Referring toFIG.9, the P-type well region907is disposed on the high-voltage P-type well region903, and the boundary of the P-type well region907is surrounded by the high-voltage P-type well region903.

The N-type well region908has two sidewalls W908A and W908B that are opposite to each other. The N-type well region908extends from the N-type deep well region906to the high-voltage P-type well region903so that the sidewall W111A of the N-type well region908is in contact with the high-voltage P-type well region903, that is, the sidewall W908A is in the high-voltage P-type well region903. The sidewall W908B of the N-type well region908is in contact with the N-type deep well region906, that is, the sidewall W908B is in the N-type deep well region906. Therefore, the N-type well region908partially overlaps with the high-voltage P-type well region903and further partially overlaps the N-type deep well region906.

The P-type well region909partially overlaps the N-type deep well region906and further partially overlaps the high-voltage P-type well region904. The P-type well region909has two sidewalls W909A and W909B that are opposite to each other. As shown inFIG.9, the sidewall W909A of the P-type well region909is in contact with the N-type deep well region906, that is, the side wall W909A is in the N-type deep well region906; the sidewall W909B of the P-type well region909is in contact with the high-voltage P-type well region904, that is, the sidewall W909B is in the high-voltage P-type well region904.

As shown inFIG.9, the doped regions910-912are all disposed on the P-type well region907. The doped region910is adjacent to the N-type deep well region905, the doped region912is adjacent to the N-type well region908, and the doped region911is disposed between the doped regions910and912. The doped regions910-912are coupled to the bonding pad90. In the embodiment, the conductivity type of the doped region911is P-type, and the doped region911may be implemented as a P-type heavily doped (P+) region. In addition, the conductivity types of the doped regions910and912are N-type, and the doped regions910and912may be implemented as N-type heavily doped (N+) regions. In order to clearly illustrate the arrangement and the conductivity types of the doped regions910-912, hereinafter, the doped region911is referred to as a P-type doped region, and the doped regions910and912are referred to as N-type doped regions.

Referring toFIG.9, the doped region916is disposed on the N-type well region908. In the embodiment, the conductivity type of the doped region916is N-type, and the doped region916may be implemented as an N-type heavily doped (N+) region. In order to clearly illustrate the arrangement and the conductivity type of the doped region916, hereinafter, the doped region916is referred to as an N-type doped region.

As shown inFIG.9, both of the doped regions913and914are disposed on the P-type well region909. The doped region913is adjacent to the N-type deep well region906, and the doped region914is adjacent to the high-voltage P-type well region904. The doped regions913and914are coupled to the ground terminal TGND. In the embodiment, the conductivity type of the doped region913is P-type, and the doped region913is implemented as a P-type heavily doped (P+) region. The conductivity type of the doped region914is N-type, and the doped region914may implemented as an N-type heavily doped (N+) region. In order to clearly illustrate the arrangement and the conductivity types of the doped regions913and914, hereinafter, the doped region913is referred to as a P-type doped region, and the doped region914is referred to as an N-type doped region.

The doped region915is disposed on the high-voltage P-type well region904and coupled to the ground terminal TGND. In the embodiment, the conductivity type of the doped region914is P-type, and the doped region914may be implemented as a P-type heavily doped (P+) region.

Referring toFIG.9, the isolation patterns917-923are disposed on the epitaxial layer901. In the embodiment, the isolation patterns917-923may be shallow trench isolation (STI) features. Referring toFIG.9, the isolation pattern917fully covers the N-type deep well region905and further partially covers the high-voltage P-type well region903, the isolation pattern918is disposed between the N-type doped region910and the P-type doped region911, and the isolation pattern919is disposed between the P-type doped region911and the N-type doped region912, and the isolation pattern920is disposed between the N-type doped region912and the N-type doped region916. In addition, the isolation pattern921is disposed between the N-type doped region916and the P-type doped region913, the isolation pattern922is disposed between the N-type doped region914and the P-type doped region915, and the isolation pattern923partially covers the high-voltage P-type well region904.

In the embodiment shown inFIG.9, the equivalent circuit of the electrostatic discharge protection device9comprises equivalent elements20-24shown inFIG.6. Referring toFIG.9andFIG.6, the P-type doped region911, the P-type well region907, the high-voltage P-type well region903, the N-type buried layer902, the N-type deep well region906, the P-type well region909, and the P-type doped region913commonly form the PNP BJT20, wherein the P-type doped region911, the P-type well region907, and the high-voltage P-type well region903serve as the first collector/emitter of the PNP BJT20, and the N-type buried layer902and the N-type deep well region906serve as the base of the PNP BJT20, and the P-type well region909and the P-type doped region913serve as the second collector/emitter of the PNP BJT20. The first collector/emitter of the PNP BJT20is coupled to the bonding pad90, and the second collector/emitter of the PNP BJT20is coupled to the ground terminal TGND.

The N-type doped region912, the P-type well region907, the high-voltage P-type well region903, the N-type well region908, and the N-type doped region916commonly form the NPN BJT21, wherein the N-type doped region912serves as the emitter of the NPN BJT21, the P-type well region907and the high-voltage P-type well region903serve as the base of the NPN BJT21, and the N-type well region908and N-type doped region916serve as the collector of the NPN BJT21. The N-type doped region914, the P-type well region909, the N-type deep well region906, the N-type well region908, and the N-type doped region916commonly form the NPN BJT22, wherein the N-type doped region914serves as the emitter of the NPN BJT22, the P-type well region909serves as the base of the NPN BJT22, and the N-type deep well region906, the N-type well region908, and the N-type doped region916serve as the collector of the NPN BJT22. Referring toFIG.6, according to the structure inFIG.9, the emitter and the base of the NPN BJT21are coupled to the bonding pad90, and the collector of the NPN BJT21, the base of the PNP BJT20, and the collector of the NPN BJT22are coupled to the node N20, the emitter and the base of the NPN BJT22are coupled to the ground terminal TGND. The node N20corresponds to the N-type buried layer902, the N-type deep well region906, the N-type well region908, and the N-type doped region916whose conductivity types are N-type and which are connected to each other inFIG.9.

Referring toFIG.9, when an electrostatic discharge event occurs on the bonding pad90to cause a positive voltage (or, when a positive electrostatic discharge event occurs on the bonding pad10), a discharge path is formed through the bonding pad90, the P-type doped region911, the P-type well region907, the high-voltage P-type well region903, the N-type well region908, the N-type deep well region906, the P-type well region909, the N-type doped region914, and the ground terminal TGND so that the electrostatic charges on the bonding pad90are conducted to the ground terminal TGND through this discharge path. That is, the above discharge path is from the bonding pad90and finally to the ground terminal TGND through a P-N-P-N junction. From the viewpoint of the equivalent circuit of the electrostatic discharge protection device9, referring toFIG.6, when an electrostatic discharge event occurs on the bonding pad90to cause a positive voltage, the PNP BJT20and the NPN BJT22are turned on. At this time, the first collector/emitter of the PNP BJT20serves as the emitter (indicated by the solid arrow). The PNP BJT20and the NPN BJT22form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure shown inFIG.9, the electrostatic charge on the bonding pad90is conducted to the ground terminal TGND through the emitter and the base of the PNP BJT20and the collector, the base and the emitter of the NPN BJT22in sequence.

Referring toFIG.9, when an electrostatic discharge event occurs on the bonding pad90to cause a negative voltage (or, when a negative electrostatic discharge event occurs on the bonding pad90), a discharge path is formed through the ground terminal TGND, the P-type doped region913, the P-type well region909, the N-type deep well region906, the N-type well region908, the high-voltage P-type well region903, the P-type well region907, the N-type doped region912, and the bonding pad90so that the charges on the ground terminal TGND are conducted to the bonding pad90through this discharge path. That is, the above discharge path is from the ground terminal TGND and finally to the bonding pad10through a P-N-P-N junction. From the viewpoint of the equivalent circuit of the electrostatic discharge protection device9, referring toFIG.6, when an electrostatic discharge event occurs on the bonding pad90to cause a negative voltage, the PNP BJT20and the NPN BJT21are turned on. At this time, the second collector/emitter of the PNP BJT20serves as the emitter (indicated by the hollow arrow). The PNP BJT20and the NPN BJT21form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure inFIG.1, the charges on the ground terminal TGND are conducted to the bonding pad90through the emitter and the base of the PNP BJT20and the collector, the base, and the emitter of the NPN BJT21in sequence.

Referring toFIG.9, the high-voltage P-type well region903and N-type well region908form a third parasitic diode, and the P-type well region909and the N-type deep well region906form a fourth parasitic diode. The respective breakdown voltages of the third parasitic diode and the fourth parasitic diode may be determined by changing the position of the N-type well region908relative to the N-type deep well region906.

Referring toFIG.10, the boundary of the N-type well region908is surrounded by the N-type deep well region906. Both of the sidewalls W908A and W908B of the N-type well region908contact with the N-type deep well region906, that is, both of the sidewalls W908A and W908B are in the N-type deep well region906. Therefore, the N-type well region908does not overlap the high-voltage P-type well region903. Compared withFIG.9, inFIG.10, the breakdown voltage of the third parasitic diode formed in the high-voltage P-type well region903and the N-type deep well region906is higher. In addition, in the embodiment ofFIG.10, the breakdown voltage of the third parasitic diode is higher than the breakdown voltage of the fourth parasitic diode formed in the P-type well region909and the N-type deep well region906, which is beneficial to trigger formation of a discharge path when a positive electrostatic discharge event occurs on the bonding pad90.

Referring toFIG.11, the boundary of the P-type well region909is surrounded by the high-voltage P-type well region904. Both of the sidewalls W909A and W909B of the P-type well region909contact with the high-voltage P-type well region904, that is, both of the sidewalls W909A and W909B are in the high-voltage P-type well region904. Therefore, the P-type well region909does not overlap the N-type deep well region906. Compared withFIG.9, the breakdown voltage of the fourth parasitic diode formed in the high-voltage P-type well region904and the N-type deep well region906inFIG.11is higher. In addition, in the embodiment ofFIG.11, the breakdown voltage of the fourth parasitic diode is higher than the breakdown voltage of the third parasitic diode formed in the high-voltage P-type well region903and the N-type well region908, which is beneficial to trigger formation of a discharge path when a negative electrostatic discharge event occurs on the bonding pad90.

According to the above-mentioned embodiments, the electrostatic discharge protection device1(or the electrostatic discharge protection device5, or the electrostatic discharge protection device9) proposed by the present invention provides a bidirectional discharge path. When a positive electrostatic discharge event or a negative electrostatic discharge event occurs on the bonding pad10(or the bonding pad90), a current path formed by a P-N-P-N junction of a silicon controlled rectifier is provided, which result in a fast discharge rate.