A closed-loop switch-mode boost converter includes a switching signal generator circuit, a switch-mode boost amplifier, a filter circuit, and an error amplifier circuit. The switching signal generator circuit receives an input signal and outputs a switching signal. A duty-cycle of the switching signal has a first non-linear relationship to an amplitude of the input signal. The switch-mode boost amplifier receives the switching signal and produces an output signal. An amplitude of the output signal has a second non-linear relationship to the duty-cycle of the switching signal, and the output signal has a linear relationship to the input signal based on the first and second non-linear relationships. The filter circuit receives the output signal and outputs a filtered output signal. The error amplifier circuit receives the input signal and the filtered output signal and produces a feedback control signal. The filtered output signal is adjusted based on the feedback control signal.

BACKGROUND

Some systems that amplify high-bandwidth signals use a first power converter circuit (typically a switch-mode boost power converter) to boost a DC voltage up to a fixed high-voltage rail. The fixed high-voltage rail is used as an input voltage to a second power converter circuit. The second power converter circuit is suitable for amplifying time-varying signals which have a high maximum frequency component or signal bandwidth. The second power converter is often realized as a linear power converter circuit, and in some cases, as a switch-mode buck converter circuit. In such systems, the second power converter circuit receives the time-varying signal and steps down the input voltage of the fixed high-voltage rail to generate an amplified form of the time-varying signal.

In some systems, the first power converter circuit generates the high-voltage rail such that it follows an outer amplitude envelope of the amplified time-varying signal (i.e., a low frequency component of the time-varying signal) and the second power converter generates a high-frequency component of the amplified time varying signal. In such systems, a voltage difference between an amplitude of the amplified high-frequency component and the outer amplitude envelope may result in power efficiency losses.

SUMMARY

In some embodiments, a closed-loop switch-mode boost converter includes a switching signal generator circuit, a switch-mode boost amplifier circuit, a filter circuit, and an error amplifier circuit. The switching signal generator includes a signal input node for receiving a time-varying input signal, and a switching signal output node for outputting a switching signal. A duty-cycle of the switching signal has a first non-linear relationship to an amplitude of the time-varying input signal. The switch-mode boost amplifier circuit includes an input voltage node for receiving an input voltage, a switch driver input node coupled to the switching signal output node for receiving the switching signal, and a signal output node for outputting a time-varying output signal. An amplitude of the time-varying output signal has a second non-linear relationship to the duty-cycle of the switching signal, and the time-varying output signal has a linear relationship to the time-varying input signal based on the first non-linear relationship and the second non-linear relationship. The filter circuit includes a filter input node coupled to the signal output node of the switch-mode boost amplifier circuit to receive the time-varying output signal, and a filter output node for outputting a filtered time-varying output signal. The error amplifier circuit has a first input node coupled to the signal input node for receiving the time-varying input signal, and a second input node coupled to the filter output node of the switch-mode boost amplifier circuit to receive the filtered time-varying output signal. The error amplifier circuit produces a feedback control signal using the time-varying input signal and the filtered time-varying output signal, the filtered time-varying output signal being adjusted based on the feedback control signal. The time-varying input signal has a first maximum frequency component, the first maximum frequency component being substantially greater than DC, and the filtered time-varying output signal has a second maximum frequency component, the second maximum frequency component being substantially the same as the first maximum frequency component.

DETAILED DESCRIPTION

Some embodiments described herein provide a high-speed closed-loop switch-mode boost (“closed-loop”) converter for amplifying a time-varying signal. In some embodiments, the closed-loop converter receives a time-varying input signal and generates a filtered time-varying output signal that advantageously has a substantially linear relationship to the time-varying input signal, and has a maximum frequency component, significantly higher than DC, that is substantially the same as a maximum frequency component of the time-varying input. The closed-loop converter advantageously includes a feedback path to further improve the fidelity with which the time-varying input signal is amplified, and amplifies the time-varying signal without using an intermediate high-voltage rail signal, thereby improving a power efficiency of the closed-loop converter as compared to conventional converters.

In some embodiments, the closed-loop converter generally includes a switching signal generator circuit. The switching signal generator circuit generates a switching signal based on a time-varying input signal. A duty-cycle of the switching signal has a first non-linear relationship to the time-varying input signal. The switching signal drives a switch of a switch-mode boost converter. Based on the switching signal, the switch-mode boost converter generates an amplified time-varying output signal. A second non-linear relationship of the switch-mode boost converter, when “counteracted” by the first non-linear relationship, results in a linear relationship between the time-varying output signal and the time-varying input signal. A high-order (e.g., greater than second-order) filter circuit coupled to an output of the switch-mode boost converter substantially passes frequency components of the time-varying input signal that are present in the time-varying output signal. The high-order filter circuit also substantially attenuates frequencies higher than maximum frequency components of the time-varying input signal that are present in the time-varying output signal. As will be discussed, such embodiments can advantageously simplify and improve the power efficiency of circuits that typically require two or more power converters, such as envelope tracking circuits used in radio frequency (RF) amplifier circuits. A feedback path of the closed-loop converter produces a feedback control signal based on the time-varying input signal and the amplified time-varying output signal. The feedback control signal is received by the switching signal generator circuit of the closed-loop converter to adjust the time-varying output signal such that the time-varying output signal accurately reproduces and amplifies the time-varying input signal while maintaining a linear relationship between the time-varying input signal and the time-varying output signal.

Some conventional systems that amplify a high-bandwidth signal use a first power converter (typically a switch-mode boost power converter) to boost a DC voltage up to a fixed high-voltage rail. The fixed high-voltage rail is used as an input voltage for a second power converter that is capable of amplifying high-bandwidth signals. Such second converters include linear power converters, and in some cases, switch-mode buck converters. The second power converter circuit receives the high-bandwidth signal and steps the input voltage of the high-voltage rail down to generate an amplified form of the high-bandwidth signal. Conventional two-stage amplifiers may produce power efficiency losses due to a voltage difference between the high-voltage rail and the stepped-down amplified signal. Some conventional two-stage amplifiers reduce such power efficiency losses using envelope tracking techniques, in which the high-voltage rail tracks a low frequency component of the time varying input signal. However, power efficiency losses still occur due to a difference in voltage between the high-voltage rail and the amplified output signal.

In instances where the second power converter is a switch-mode buck converter, an output voltage Vout of the converter relates linearly to the input voltage Vin of the converter as a function of a converter switching duty-cycle D, the relationship being:
Vout=D×Vin  (Equation 1).

By contrast, the first power converter when implemented as a switch-mode boost power converter has a non-linear relationship between an output voltage Vout of the boost converter and an input voltage Vin of the boost converter as a function of switching duty-cycle D, the relationship being:

FIG. 1Ashows a simplified circuit diagram of a prior art switch-mode boost power converter (“converter”)100. The converter100receives a fixed input voltage Vin at an input voltage node102and generates a boosted DC voltage Vout at an output voltage node104to provide power to a load119. The converter100generally includes a comparator circuit106, a ramp generator circuit108, an error amplifier circuit110, a pulse generator circuit114, a switch driver circuit118, a compensator circuit121, a switch S1, an inductor L1, an output rectifier (e.g., a diode D1), and a capacitor C1. The converter100also generally includes a feedback path112that includes the error amplifier circuit110and the compensator circuit121.

The comparator circuit106receives a ramp signal Vramp from the ramp generator circuit108. The comparator circuit106performs a comparison between the ramp signal Vramp and a control signal Vc that is received from the error amplifier circuit110on the feedback path112. The compensator circuit121is coupled to the error amplifier circuit110. The error amplifier circuit110compares a reference voltage Vref to a (typically) scaled value of the boosted voltage Vout (received from the compensator circuit121) and amplifies an error between Vref and the scaled value of the boosted voltage Vout to generate the control signal Vc. Comparison results from the comparator circuit106are passed to the pulse generator circuit114(e.g., a Schmitt Trigger). The pulse generator circuit114generates well-defined pulses based on the comparison results (e.g., pulses having a minimum pulse width and clearly defined pulse edges). These pulses form a pulse-width-modulation (PWM) signal Vpwm at signal node116. The PWM signal Vpwm is received at a switch driver input node of the switch driver circuit118. The switch driver circuit118buffers, level-shifts, or otherwise conditions the PWM signal Vpwm to make a suitable gate drive signal for turning the switch S1on and off. When the switch S1is on, the switch S1conducts current from a high-side of the switch S1to a low-side of the switch S1. In some designs, the switch S1is a field-effect-transistor (FET). The high-side of the switch S1is coupled to the input voltage node102through the inductor L1. The low-side of the switch S1is coupled to a ground node or another bias voltage (e.g., Vss). The high-side of the switch S1is additionally coupled to the load119through the output rectifier, realized inFIG. 1Aas the diode D1. The capacitor C1couples the output voltage node104to the ground or other bias voltage node. The capacitor C1typically filters out non-DC frequency components of the boosted voltage Vout, thereby passing a DC voltage and substantially blocking non-DC frequencies. The boosted voltage Vout is received at the load119.

As was discussed with reference to Equation 2, Vout relates non-linearly to Vin as a function of a duty-cycle D of the PWM signal Vpwm. A simplified signal diagram120ofFIG. 1Bshows a ramp signal Vramp122and a control signal Vc124received at the comparator circuit106ofFIG. 1Aover time t. A simplified signal diagram140ofFIG. 1Bshows a PWM signal Vpwm142generated from the ramp signal Vramp122and the control signal Vc124via the comparator circuit106and the pulse generator circuit114. In the example shown, the control signal Vc124is shown as constant over time t for simplicity. However, it is understood that the control signal Vc124can change over time.

The ramp signal Vramp122, and by extension the PWM signal Vpwm142, are shown to have a period T1. A duration of time that the ramp signal Vramp122is below the control signal Vc124is designated as duration T1′. The comparator circuit106ofFIG. 1Aoutputs a comparison value that is positive when the control signal Vc124is greater than the ramp signal Vramp122and negative (or zero) when the control signal Vc124is less than the ramp signal Vramp122. The pulse generator circuit114receives the comparison value and generates pulses (e.g.,144) based on the received comparison value. Accordingly, a pulse width of the pulse144is also of duration T1′. The ratio of the pulse duration T1′ to the period T1is the duty-cycle D of the PWM signal Vpwm142for that period. As shown in Equation 2, for a fixed input voltage Vin, the boosted output voltage Vout increases and decreases non-linearly as the duty-cycle D increases and decreases, respectively. This non-linear relationship is illustrated in a simplified signal diagram160ofFIG. 1B. As shown, the boosted output voltage Vout162is a non-linear function of the duty-cycle D of the PWM signal Vpwm142for a fixed input voltage Vin164.

FIG. 2Aillustrates a simplified circuit diagram of a high-speed closed-loop switch-mode boost converter (“closed-loop converter”)240with linear signal characteristics, in accordance with some embodiments. Like-numbered elements of the closed-loop converter240may have similar descriptions as corresponding like-numbered elements of the converter100ofFIG. 1A, although design considerations may cause actual implementations of these elements to be rendered differently in the two circuits. Some elements of the closed-loop converter240have been omitted fromFIG. 2Ato simplify the description of the closed-loop converter240but are understood to be present.

In general, the closed-loop converter240includes a switching signal generator circuit242, a switch-mode boost amplifier (“amplifier”) circuit portion243, a filter circuit244to provide power to a load246, and an error amplifier circuit270on a feedback path272of the closed-loop converter240. The amplifier circuit portion243generally includes the input voltage node102, the switch driver circuit118, the switch S1, the inductor L1, a signal output node252, and an output rectifier realized here as the diode D1. In some embodiments, the switch S1is a power FET. For example, in some embodiments, the switch S1is an n-FET or a p-FET. In some embodiments, the switch driver circuit118is part of the switching signal generator circuit242.

A first input of the error amplifier circuit270is coupled to a signal input node248of the closed-loop converter240, a second input of the error amplifier circuit270is coupled to a signal output node254(i.e., a filter output node) of the closed-loop converter240, and an output of the error amplifier circuit270is coupled to the switching signal generator circuit242. In some embodiments, the error amplifier circuit270includes a compensator circuit (not shown) that is similar to, or the same as the compensator circuit121.

The switching signal generator circuit242receives a time-varying input signal Vsig(t) at the signal input node248and generates a switching signal Vpwm'(t) at an output node250. A duty-cycle of the switching signal Vpwm'(t) has a non-linear relationship to an amplitude of the time-varying input signal Vsig(t). In some embodiments, the relationship of amplitude to duty-cycle is described as:

D⁡(t)=1-KVsig⁡(t),(Equation⁢⁢3)
where D(t) is a duty-cycle of the switching signal Vpwm'(t) that varies over time t in accordance with an amplitude of the time-varying input signal Vsig(t), and K is a constant. The time-varying input signal Vsig(t) is a signal that has rising and falling amplitudes which vary over time, resulting in frequency components that are substantially greater than DC. In some embodiments a signal bandwidth VsigBW, or a maximum frequency component fMAX(Vsig(t)), of the time-varying input signal Vsig(t) is 20 Hz-20 kHz. In other embodiments, the signal bandwidth VsigBWor the maximum frequency component fMAX(Vsig(t)) is greater than 1 MHz, greater than 10 MHz, and in some embodiments, is on the order of 100 MHz. In some embodiments, the time-varying input signal Vsig(t) is a sinusoid. In some embodiments, the time-varying input signal Vsig(t) is a modulated sinusoid. In some embodiments, the time-varying input signal Vsig(t) is a signal having a time-varying amplitude having frequency content up to and including fMAX(Vsig(t)). In some embodiments, the time-varying input signal Vsig(t) is an audio signal. In some embodiments, the time-varying input signal Vsig(t) is an envelope signal. In some embodiments, the time-varying input signal Vsig(t) is a communication signal, or another signal suitable for amplification.

The switch driver circuit118receives the switching signal Vpwm'(t) at a switch driver input node and generates a suitable gate driver signal (as described with reference toFIG. 1A) for turning the switch S1on and off in accordance with Vpwm'(t) to generate a boosted time-varying output signal Vout'(t) at the signal output node252. The time-varying output signal Vout'(t) has a non-linear relationship to the duty-cycle D(t) of the switching signal Vpwm'(t) (similar to that of Equation 2), expressed here as:

Thus, by substituting the first non-linear relationship for duty-cycle D(t) as shown in Equation 3 into the second non-linear relationship for the time-varying output signal Vout'(t) of Equation 4, it is shown that a linear relationship between the time-varying input signal Vsig(t), the time-varying output signal Vout'(t), and a filtered time-varying output signal VsigOut(t) is advantageously achieved. This linear relationship can be expressed as:
VsigOut(t)=K′+Vsig(t)+Vin  (Equation 5),
where constant K′ includes the constant K and the constant input voltage Vin.

The filter circuit244receives the time-varying output signal Vout'(t) at a filter input node (i.e., the signal output node252) and substantially filters out frequency components that are greater than the signal bandwidth VsigBWor a maximum frequency component fMAX(Vsig(t)), of the time-varying input signal Vsig(t) (e.g., switching frequencies and harmonics thereof). The filter circuit244outputs the filtered time-varying output signal VsigOut(t) at a filter output node (i.e., the signal output node254). The filtered time-varying output signal VsigOut(t) is received at the load246. The filtered time-varying output signal VsigOut(t) advantageously has a signal bandwidth that is substantially the same as the signal bandwidth of the input signal Vsig(t) and has a maximum frequency component fMAX(VsigOut(t)) that is the same as a maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t). That is, Vsig(t) and VsigOut(t) both include a range of frequency components, ranging from a minimum frequency component to a maximum frequency component, the ranges being substantially the same. This contrasts with the converter100, which due to the capacitor C1, substantially filters out non-DC frequency components of Vout.

The error amplifier circuit270receives a first time-varying sense signal SenseVsig(t) from the signal input node248and a second time-varying sense signal SenseVsigOut(t) from the signal output node254(i.e., a filter output node) and uses one or both of the first sense signal SenseVsig(t) and/or the second sense signal SenseVsigOut(t) to produce a time-varying feedback control signal ErrorCtrl(n) that is received by the switching signal generator circuit242. The first sense signal SenseVsig(t) is representative of one or both of a voltage level and/or a current level sensed (e.g., using an analog to digital converter (ADC) or using an analog circuit) at the signal input node248. Similarly, the second sense signal SenseVsigOut(t) is representative of one or both of a voltage level and/or a current level sensed (e.g., using an ADC or using an analog circuit) at the signal output node254. In some embodiments, the error amplifier circuit270includes a compensator circuit (not shown) that is similar to the compensator circuit121, and the second sense signal SenseVsigOut(t) is a signal that is output from the compensator circuit. The error amplifier circuit270compares the second sense signal SenseVsigOut(t), or a signal that is based on the second sense signal (e.g., a scaled, buffered, filtered, phase-shifted, or otherwise compensated signal), to a reference signal that is, or is based on, the first sense signal SenseVsig(t) (e.g., a scaled signal, buffered, phase-shifted, or filtered signal) to generate the feedback control signal ErrorCtrl(n). In some embodiments, the feedback control signal ErrorCtrl(n) is a time-varying digital signal. In other embodiments, the feedback control signal ErrorCtrl(n) is a time-varying analog signal.

The feedback control signal ErrorCtrl(n) is received by the switching signal generator circuit242to ultimately adjust an output level of the filtered time-varying output signal VsigOut(t) produced at the signal output node254such that the filtered time-varying output signal VsigOut(t) accurately produces (i.e., with high fidelity) an amplified version of the time-varying input signal Vsig(t). By the inclusion of the feedback path272, residual errors (e.g., non-linearities) that remain after linearization performed by the switching signal generator circuit242are advantageously corrected, though a maximum bandwidth of the closed-loop converter240may be lower than that of an open-loop converter that performs linearization using the switching signal generator circuit242.

In some embodiments, at least the switching signal generator circuit242, the switch driver circuit118, the error amplifier circuit270, and the switch S1are integrated into a signal integrated circuit (IC) package. In some embodiments, an IC package includes a semiconductor device that integrates multiple circuit elements of the closed-loop converter240. In some embodiments, the semiconductor device includes a substrate and an active layer formed on a monolithic substrate. The active layer includes all or part of the switching signal generator circuit242, all or part of the switch driver circuit118, all or part of the error amplifier circuit270, and includes the switch S1. In some embodiments, the active layer is formed using silicon (Si). In some embodiments, the active layer is formed using silicon carbide (SiC). In other embodiments, the active layer is formed using other materials known in the art.

FIG. 2Billustrates a simplified circuit diagram of a high-speed, closed-loop switch-mode boost converter (“closed-loop converter”)260with linear signal characteristics, in accordance with some embodiments where a synchronous switch S2is used as the output rectifier in lieu of the diode D1. The closed-loop converter260generally includes like-numbered elements as shown and described with reference toFIG. 2A. A switch driver circuit262is shown to have a second signal output coupled to a gate node of the switch S2to, in general, synchronously turn the switch S2on when the switch S1is turned off and turn the switch S2off when the switch S1is turned on. As is known in the art, replacing a diode output rectifier with a synchronously switched output rectifier can increase system power efficiency.

FIG. 3Aillustrates a simplified circuit diagram of an example embodiment of a switching signal generator circuit342, in accordance with some embodiments. In some embodiments, the switching signal generator circuit242shown inFIG. 2Aand/orFIG. 2Bis realized as the switching signal generator circuit342. In general, the switching signal generator circuit342generates a time-varying ramp signal Vramp'(t) which is used to generate the switching signal Vpwm'(t). The ramp signal Vramp'(t) relates non-linearly to the time varying input signal Vsig(t). Each ramp peak of the ramp signal Vramp'(t) may substantially vary in amplitude from one or more other peaks of the ramp signal Vramp'(t). By comparison, conventional ramp generator circuits typically generate a conventional ramp signal where each ramp peak is of substantially the same amplitude as the other ramp peaks of the conventional ramp signal.

The switching signal generator circuit342generally includes a voltage-to-current conversion circuit portion301, an integrator circuit portion302, and a pulse generation circuit portion303. The voltage-to-current conversion circuit portion301receives the time varying input signal Vsig(t) at the signal input node248and produces a charging current flow Isig(t) based on time varying input signal Vsig(t). The integrator circuit portion302receives the charging current flow Isig(t) and generates the time-varying ramp signal Vramp'(t) based on the charging current flow Isig(t). The pulse generation circuit portion303receives the time-varying ramp signal Vramp'(t) and generates the switching signal Vpwm'(t) at the output node250based on the time-varying ramp signal Vramp'(t), the switching signal Vpwm'(t) having a duty-cycle D(t) in accordance to Equation 3. In other embodiments, the switching signal generator circuit242/342includes other circuit portions (not shown) suitable for generating the switching signal Vpwm'(t) having a duty-cycle D(t) in accordance with Equation 3.

In some embodiments, the voltage-to-current conversion circuit portion301and/or the pulse generation circuit portion303are operable to receive the feedback control signal ErrorCtrl(n) from the error amplifier circuit270and to adjust the time-varying current Isig(t) and/or a trigger voltage level of a comparator based on values of the feedback control signal ErrorCtrl(n) to produce the switching signal Vpwm'(t) such that a high-fidelity amplified time-varying output signal is generated.

FIG. 3Billustrates a simplified circuit diagram of a first example embodiment of a switching signal generator circuit342a, in accordance with some embodiments. In some embodiments, the switching signal generator circuit242shown inFIG. 2Aand/orFIG. 2Bis realized as the switching signal generator circuit342a. In the example embodiment shown, the switching signal generator circuit342aincludes a voltage-to-current conversion circuit portion301a, an integrator circuit portion302a, and a pulse generation circuit portion303a. These circuit portions301a,302a,303a, given the time-varying input signal Vsig(t) received from the signal input node248, generate the switching signal Vpwm'(t) having a duty-cycle D(t) in accordance to Equation 3.

In the embodiment shown, the example voltage-to-current conversion circuit portion301agenerally includes an optional adjustable current source circuit301b, as well as a switch S3. The switch S3is coupled to a positive voltage node Vdd through a resistor R1. In some embodiments, the switch S3is a field-effect-transistor (FET). In some embodiments, the switch S3is an n-FET, a p-FET or a bi-polar junction transistor (BJT). Other voltage-to-current conversion circuit portions suitable for generating a time-varying current based on a received time-varying voltage signal, a time varying digital signal, or a static digital signal, as are known in the art, could be used for the voltage-to-current conversion portions described herein.

The integrator circuit portion302agenerally includes a capacitor C2coupled between the voltage-to-current conversion circuit portion301aand a ground node (or another bias voltage Vss), a switch S4(i.e., a discharge switch) coupled in parallel to the capacitor C2, and a switch control circuit305coupled to a switch control node of the switch S4.

The pulse generation circuit portion303agenerally includes a comparator circuit307(i.e., a voltage comparison circuit similar to the comparator circuit106), a trigger level generation circuit309, and an optional pulse-generator circuit311. A first input of the comparator circuit307is coupled to the capacitor C2, and a second input of the comparator circuit307is coupled to a trigger level generation circuit309. The comparator circuit307is powered between a high voltage rail VcompH and a low voltage rail VcompL. An output of the comparator circuit307is coupled to an input of the pulse-generator circuit311(which is similar to the pulse generator circuit114). In some embodiments, the high voltage rail VcompH is Vdd and the low voltage rail VcompL is the ground node (or the other bias voltage Vss). In some embodiments, the comparator circuit307is suitable for generating well-defined pulses and the pulse-generator circuit311is optional. In some embodiments, the bias voltage node Vss is a ground node. In some embodiments, the bias voltage node Vss is another bias voltage. The trigger level generation circuit309is optionally configured to receive the feedback control signal ErrorCtrl(n) and to adjust (i.e., raise or lower) a level of a trigger voltage Vtrig produced by the trigger level generation circuit309based on a value of the feedback control signal ErrorCtrl(n) (e.g., using a digital to analog converter (DAC) or an analog circuit).

When driven at a current conduction control node (e.g., a gate or body node) by the time-varying input signal Vsig(t), the switch S3provides the proportional time-varying current Isig(t) to the integrator circuit portion302a. In the embodiment shown, an amplitude of the time-varying current Isig(t) is 180 degrees out of phase with the time-varying input signal Vsig(t). In other embodiments (e.g., as shown inFIG. 3D), the time-varying current Isig(t) is in phase with the time-varying input signal Vsig(t). The ramp signal Vramp'(t) is generated by the integrator circuit portion302a. The time-varying current Isig(t) charges the capacitor C2of the integrator circuit portion302a. The switch S4, when triggered by the switch control circuit305such that the switch S4is in a conduction state, discharges the capacitor C2through the switch S4to the ground voltage node via a discharge current flow. A value of the capacitor C2and a switch rate of the switch S4are chosen for a corresponding voltage-to-current conversion circuit portion301asuch that a frequency of the resultant ramp signal Vramp'(t) is at least two times greater than a maximum frequency of the time-varying input signal Vsig(t), thereby producing a switching frequency of the switching signal Vpwm'(t) that is at least two times greater than a maximum frequency of the time-varying input signal Vsig(t). The frequency of the ramp signal Vramp'(t) can be selected at design time through the realization of the voltage-to-current conversion circuit portion301a, a chosen capacitance value of the capacitor C2, a discharge frequency/period of the switch S4as driven by the switch control circuit305, and a discharge duty-cycle of the switch S4as driven by the switch control circuit305. In some embodiments, the discharge frequency/discharge period of the switch S4is set to be equal to, or greater than, a time duration to fully discharge the capacitor C2to the ground node when the switch S4is conducting. In the example shown inFIG. 3B, amplitudes of the time-varying input signal Vsig(t) are 180-degrees out of phase with corresponding amplitudes of a generated ramp signal Vramp'(t). That is, the integrator circuit portion302aas shown generates a ramp signal Vramp'(t) having maximum ramp peak amplitudes that correspond to minimum amplitudes of the time-varying input signal Vsig(t) and minimum ramp peak amplitudes that correspond to maximum amplitudes of the time-varying input signal Vsig(t).

The comparator circuit307receives the ramp signal Vramp'(t) at a first input and compares amplitudes of the ramp signal Vramp'(t) to an amplitude of the trigger voltage Vtrig received from the trigger level generation circuit (Vtrigger)309. Comparison results from the comparator circuit307are passed to the pulse-generator circuit311. The pulse-generator circuit311generates well-defined pulses based on the comparison results. These pulses form the switching signal Vpwm'(t) at the output node250.

In some embodiments, elements of the circuit portions301a,302aare selected to generate a Vramp'(t) signal having a maximum ramp peak amplitude (i.e., a maximum ramp voltage) that is equal to, or slightly less, than the high voltage rail VcompH (i.e., an upper voltage comparison limit) of the comparator circuit307and a minimum ramp peak amplitude (i.e., a minimum ramp voltage) that is equal to, or slightly greater, than the low voltage rail VcompL of the comparator circuit307(i.e., a lower voltage comparison limit). In some embodiments, the amplitude of the trigger voltage Vtrig is set at design time to be greater than zero and less than or equal to a minimum ramp peak amplitude of the ramp signal Vramp'(t). In some embodiments, the trigger voltage Vtrig is set to be a fixed percentage of a voltage rail of the comparator circuit307. In other embodiments, the trigger voltage Vtrig is based on a difference between the high voltage rail VcompH and the low voltage rail VcompL. In yet other embodiments, such as one discussed below with reference toFIG. 3C, an amplitude of the trigger voltage Vtrig is determined during operation of the closed-loop converter240/260. In some embodiments, the trigger voltage Vtrig is adjusted (e.g., raised or lowered) relative to a fixed value based on the feedback control signal ErrorCtrl(n).

In some embodiments, the optional adjustable current source circuit301bis operable to generate an error current Ierr(t) having a current level that is adjusted based on values of the feedback control signal ErrorCtrl(n). The error current Ierr(t) contributes to a current level of the current Isig(t) to control a rate at which the capacitor C2is charged by the voltage-to-current conversion circuit portion301a. By adjusting the rate at which the capacitor C2is charged, the feedback control signal ErrorCtrl(n) is operable to adjust the duty cycle of the switching signal Vpwm'(t) to thereby adjust an output level of the filtered time-varying output signal VsigOut(t) of the closed-loop converter240/260in response to a determined difference between the filtered time varying output signal VsigOut(t) and a time varying reference signal that is based on the time-varying input signal Vsig(t). Similarly, in some embodiments, the trigger level generation circuit (Vtrigger)309is operable to receive the feedback control signal ErrorCtrl(n) and adjust a level of the trigger voltage Vtrig relative to a fixed value based on the feedback control signal ErrorCtrl(n) to adjust the duty cycle of the switching signal Vpwm'(t) to thereby adjust an output level of the filtered time-varying output signal VsigOut(t) of the closed-loop converter240/260. By adjusting the output level of the filtered time-varying output signal VsigOut(t) of the closed-loop converter240/260using the feedback control signal ErrorCtrl(n), fidelity of a signal amplified by the closed-loop converter240/260is advantageously higher than a signal amplified by a conventional converter.

FIG. 3Cillustrates a simplified circuit diagram of an example embodiment of a switching signal generator circuit342b, in accordance with some embodiments. In some embodiments, the switching signal generator circuit242shown inFIG. 2A/2B is realized as the switching signal generator circuit342b. The switching signal generator circuit342bgenerally includes the voltage-to-current conversion circuit portion301a, the integrator circuit portion302a, and a pulse generation circuit portion303b. Like-numbered circuit elements correspond to like-numbered circuit elements shown and discussed with reference toFIG. 3B. In the embodiment shown, a trigger level generation circuit (Vtrigger)313is coupled to the capacitor C2to receive the ramp signal Vramp'(t). The trigger level generation circuit313detects a minimum ramp peak voltage amplitude and generates a trigger voltage Vtrig having an amplitude that is greater than zero and equal to, or less than, the detected minimum ramp peak voltage amplitude. Thus, rather than being set to an arbitrary amplitude, or the amplitude being set at design time, the amplitude of the trigger voltage Vtrig advantageously corresponds to a specific amplitude of the ramp signal Vramp'(t). In some embodiments, the detection occurs when an external control signal En is received by the trigger level generation circuit313(e.g., from a control circuit or a reset control circuit, not shown). In some embodiments, the amplitude of the trigger voltage Vtrig that corresponds to a specific amplitude of the ramp signal Vramp'(t) is further adjusted based on values of the feedback control signal ErrorCtrl(n).

FIG. 3Dillustrates a simplified circuit diagram of an example embodiment of a switching signal generator circuit342c, in accordance with some embodiments. In some embodiments, the switching signal generator circuit242shown inFIG. 2A/2B is realized as the switching signal generator circuit342c. The switching signal generator circuit342cgenerally includes a voltage-to-current conversion circuit portion301c, the integrator circuit portion302a, and the pulse generation circuit portion303a(or the pulse generation circuit portion303bshown inFIG. 3C). Like-numbered circuit elements correspond to like-numbered circuit elements shown and discussed with reference toFIG. 3B. In the embodiment shown, the voltage-to-current conversion circuit portion301cis realized using a current-mirror topology, the circuit portion301cgenerally including the optional adjustable current source circuit301b, resistors R2-4and switches S5-7, coupled as shown. In some embodiments, any of the switches S5-S7can be an n-FET, a p-FET, an n-type power FET, a BJT, or a p-type power FET.

In the example shown, amplitudes of the time-varying input signal Vsig(t) are in phase with corresponding amplitudes of the generated ramp signal Vramp'(t). That is, the integrator circuit portion302agenerates a ramp signal Vramp'(t) having maximum ramp peak amplitudes that correspond in time to maximum amplitudes of the time-varying input signal Vsig(t) and minimum ramp peak amplitudes that correspond in time to minimum amplitudes of the time-varying input signal Vsig(t).

This correspondence is further illustrated in simplified signal diagram470FIG. 4A, which shows a ramp signal Vramp'(t)474and a trigger voltage Vtrig476received at the comparator circuit307(ofFIG. 3D) over time t. The ramp signal Vramp'(t)474is generated based on a time-varying input signal Vsig(t)472received at the signal input node248. In the example shown, maximum peak amplitudes of the ramp signal Vramp'(t)474correspond to maximum amplitudes of the time-varying input signal, Vsig(t)472. Minimum peak amplitudes of the ramp signal Vramp'(t)474correspond to minimum amplitudes of the time-varying input signal, Vsig(t)472. Thus, Vsig(t)472and Vramp'(t)474are in phase. As shown, an amplitude of the trigger voltage Vtrig476is equal to or less than a minimum peak amplitude of the ramp signal Vramp'(t)474. In some embodiments, as was discussed with reference toFIG. 3B, the amplitude of the trigger voltage Vtrig476is set at design time. In other embodiments, as was discussed with reference toFIG. 3C, the amplitude of the trigger voltage Vtrig476is set based a determination of a minimum generated peak amplitude of the ramp signal Vramp'(t)474. In some embodiments, the amplitude of the trigger voltage Vtrig476is adjusted based on values of the feedback control signal ErrorCtrl(n).

A simplified signal diagram480ofFIG. 4Ashows a switching signal Vpwm'(t)482that corresponds to the relationship between the ramp signal Vramp'(t)474and the trigger voltage Vtrig476. In contrast to the control signal Vc124as described with reference toFIG. 1B, in some embodiments the trigger voltage Vtrig476does not change over time t. In other embodiments, the trigger voltage Vtrig476does not change over time t, with the exception of adjustments made to the trigger voltage Vtrig476based on values of the feedback control signal ErrorCtrl(n). In embodiments similar to that ofFIG. 3C, a new amplitude of trigger voltage Vtrig476can be generated if the enable signal En is triggered again. In such embodiments, an amplitude of the trigger voltage Vtrig476may still be adjusted by the trigger level generation circuit309based on the feedback control signal ErrorCtrl(n) received by the trigger level generation circuit309from the error amplifier circuit270.

The ramp signal Vramp'(t)474, and by extension the switching signal Vpwm'(t)482, are shown to have a period T2. An example duration of time that the ramp signal Vramp'(t)474is greater than the trigger voltage Vtrig476is designated as duration T2′. The comparator circuit307, in some embodiments, outputs a positive value when an amplitude of the ramp signal Vramp'(t)474is greater than the trigger voltage Vtrig476. The pulse-generator circuit311receives the comparison value and generates pulses (e.g.,484) based on the received comparison value. Accordingly, a pulse width of the pulse484is also of duration T2′. The ratio of the pulse duration T2′ to the period T2is the duty-cycle D(t) of the switching signal Vpwm'(t) for that period. This time-varying duty-cycle D(t) of the switching signal Vramp'(t) is in accordance with Equation 3.

As shown in the simplified signal diagram490ofFIG. 4A, by substituting the first non-linear relationship for duty-cycle D(t) as shown in Equation 3 into the second non-linear relationship for the time-varying output signal Vout'(t) of Equation 4, it is shown that a linear relationship492between the time-varying input signal Vsig(t) and the filtered time-varying output signal VsigOut(t) is advantageously achieved.

In some embodiments, the period T2of the ramp signal Vramp'(t) is selected such that a frequency of the ramp signal Vramp'(t), and thereby that of the switching signal Vpwm'(t), is two or more times greater than one or both of a maximum frequency component fMAX(Vsig(t)) or signal bandwidth VsigBW of the time-varying input signal Vsig(t). In some embodiments, the period T2of the ramp signal Vramp'(t) is selected such that a frequency of the ramp signal Vramp'(t), and thereby that of the switching signal Vpwm'(t), is eight or more times greater than one or both of the maximum frequency component fMAX(Vsig(t)) or signal bandwidth VsigBW of the time-varying input signal Vsig(t).

In some embodiments, a slope of the ramp signal Vramp'(t)474is adjusted using the error current Ierr(t) generated by the adjustable current source circuit301bbased on values of the feedback control signal ErrorCtrl(n). Similarly, in some embodiments, a voltage level of the trigger voltage Vtrig476is adjusted (e.g., using a digital-to-analog voltage converter (DAC)) based on values of the feedback control signal ErrorCtrl(n). By adjusting one or both of the slope of the ramp signal Vramp'(t)474and/or the voltage level of the trigger voltage Vtrig476, a voltage level of the filtered time-varying output signal VsigOut(t) is adjusted to advantageously minimize or eliminate a difference between the filtered time-varying output signal VsigOut(t) and a time-varying reference signal generated using the time-varying input signal Vsig(t) while still advantageously providing a linear relationship492between the time-varying input signal Vsig(t) and the filtered time-varying output signal VsigOut(t).

FIG. 4Billustrates a simplified signal diagram402of an example comparison performed by the error amplifier circuit270between a first signal f(Vsig(t))404and a second signal f(VsigOut(t))406to generate the feedback control signal ErrorCtrl(n). The first signal f(Vsig(t)) is the time-varying input signal Vsig(t), is representative of the time-varying input signal Vsig(t), or is a scaled representation of the time-varying input signal Vsig(t), e.g., SenseVsig(t). Similarly, the second signal f(VsigOut(t)) is the filtered time-varying output signal VsigOut(t), is a representation of the filtered time-varying output signal VsigOut(t), or is a scaled representation of the filtered time-varying output signal VsigOut(t), e.g., SenseVsigOut(t). In some embodiments, values of the feedback control signal ErrorCtrl(n), are representative of a determined difference408between the first signal f(Vsig(t))404and the second signal f(VsigOut(t))406. In other embodiments, values of the feedback control signal ErrorCtrl(n), are based on, are proportional to, or are inversely proportional to the determined difference408between the first signal f(Vsig(t))404and the second signal f(VsigOut(t))406. In some embodiments, a phase of the first signal f(Vsig(t))404and/or the second signal f(VsigOut(t))406is adjusted before the difference408is determined.

As described above, the feedback control signal ErrorCtrl(n) may be received by one or both of the adjustable current source circuit301band/or the trigger level generation circuit313to adjust an output level of the closed-loop converter240/260so that the time varying input signal Vsig(t) is amplified with high fidelity.

As shown in a simplified signal diagram410ofFIG. 4C, which is similar to the simplified signal diagram470ofFIG. 4A, by varying a current level of the error current Ierr(t) generated by the adjustable current source circuit301bbased on values of the feedback control signal ErrorCtrl(n), a slope of a ramp signal Vramp'(t)412may be adjusted, as shown by a dashed line414, such that a duration of time T3that the adjusted ramp signal Vramp'(t)414exceeds a trigger voltage Vtrig416is greater than or less than a duration of time T4that the unadjusted ramp signal T4exceeds the trigger voltage Vtrig416. As a result, as shown in a simplified signal diagram420ofFIG. 4C, the duration T3of an adjusted pulse422of a switching signal Vpwm'(t)424is less than or greater than a duration T4of an unadjusted pulse426of the switching signal Vpwm'(t)424, thereby adjusting an output level of the filtered time varying output signal VsigOut(t). As shown in a simplified signal diagram430ofFIG. 4C, a linear relationship432for the fixed input voltage Vin164is advantageously_maintained between the time varying input signal Vsig(t) and the filtered time varying output signal VsigOut(t).

As shown in a simplified signal diagram440ofFIG. 4D, by adjusting a level Vtrig'444of a trigger voltage Vtrig446generated by the trigger level generation circuit309/313based on values the feedback control signal ErrorCtrl(n), a duration of time T5that a ramp signal Vramp'(t)442exceeds the adjusted trigger voltage Vtrig'444is greater than or less than a duration of time T6that the ramp signal Vramp'(t)442exceeds the unadjusted trigger voltage Vtrig446. As a result, as shown in a simplified signal diagram450ofFIG. 4D, a duration T5of an adjusted pulse452of the switching signal Vpwm'(t)454is greater than or less than a duration T6of an unadjusted pulse456of the switching signal Vpwm'(t)454, thereby adjusting an output level of the filtered time varying output signal VsigOut(t). As shown in a simplified signal diagram460ofFIG. 4D, a linear relationship462for the fixed input voltage Vin164is advantageously maintained between the time varying input signal Vsig(t) and the filtered time varying output signal VsigOut(t).

FIG. 5Aillustrates a simplified circuit diagram of an example embodiment of a filter circuit544of the closed-loop converter240/260, in accordance with some embodiments. In some embodiments, the filter circuit244ofFIG. 2A/2B is realized as the filter circuit544. In the embodiment shown, the filter circuit544is realized as an N-pole PI filter. The filter circuit544receives the time varying output signal Vout'(t) at the signal output node252and outputs the filtered time-varying output signal VsigOut(t) at the signal output node254. The order of the filter circuit544is higher than a second-order filter. That is, the filter circuit544is not realized as a first-order filter, such as an RC or RL filter, or as a second-order filter, such as an RLC filter. The filter circuit544generally includes N cascaded filter sections, each generally including a filtering inductor Ln, a filtering capacitor Cn, and a filtering capacitor Cn+1, coupled as shown. In some embodiments, the number of cascaded filter sections N is 1 and thus the filter circuit544includes first and second filtering capacitors and a first filtering inductor. In other embodiments, the number of cascaded filter sections N is 2 and thus the filter circuit544includes first, second, third, and fourth filtering capacitors and first and second filtering inductors. In some embodiments, parallel capacitors may be realized as individual capacitors or as a single capacitor. In still yet other embodiments, the number of cascaded filter sections N is greater than 2. In some embodiments, the filter circuit544is implemented as one of a Chebyshev filter circuit, a Butterworth filter circuit, an Elliptic filter circuit, a Bessel filter circuit, an active filter circuit (e.g., using one or more op-amps), a digital filter circuit (e.g., using a digital-signal-processor), or another filter circuit that is suitable for substantially passing frequencies that are equal to or less than the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t) and substantially attenuating frequencies that are greater than the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t), where fMAX(Vsig(t)) is substantially greater than DC. In some embodiments, the filter circuit544has a 3 dB cutoff frequency that is greater than the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t), as illustrated in the simplified signal diagram520ofFIG. 5B. The simplified signal diagram520shows an example transfer function522of the filter circuit244/544having a 3 db cutoff524at a frequency f that is greater than or equal to the maximum frequency component fMAX(Vsig(t)) of the time-varying input signal Vsig(t). Aspects of the transfer function such as passband/stopband ripple (when present) have been omitted for simplicity. In some embodiments, roll-off of the filter circuit244/544may be significantly steeper than illustrated.

FIG. 6illustrates a simplified circuit diagram of a multi-phase high-speed closed-loop switch-mode boost converter (“closed-loop converter”)640with linear signal characteristics, in accordance with some embodiments. Like numbered elements of the closed-loop converter640may have similar descriptions as corresponding like-numbered elements of the converter100ofFIG. 1Aand the closed-loop converter240/260, although design considerations may cause actual implementations of these elements to be rendered differently in the different circuits. In general, the closed-loop converter640includes m switch-mode boost amplifier sections of an amplifier circuit643, each of which generally includes a respective inductor of the inductor L1-m, a switch of the switches S1-mand a synchronous or passive output rectifier, shown here as diodes D1-m. A switching signal generator circuit642, similar to the switching signal generator circuit242, outputs m copies of the switching signal Vpwm'(t), each copy of which is separated by a respective phase offset θ-θm. The m copies of the switching signal Vpwm'(t), with varying phase offsets, are received by m respective switch driver circuits6181-m. The m switch-mode boost amplifier sections of the amplifier circuit643generate m time-varying output signals Vout'1-m(t) which are recombined at the signal output node252to generate the time-varying output signal Vout'(t).

FIG. 7illustrates a simplified circuit diagram of a high-speed, closed-loop switch-mode boost converter (“closed-loop converter”)740with linear signal characteristics, in accordance with some embodiments. Like numbered elements of the closed-loop converter740may have similar descriptions as corresponding like-numbered elements of the converter100ofFIG. 1Aand the closed-loop converter240ofFIG. 2A, although design considerations may cause actual implementations of these elements to be rendered differently in the different circuits. Additionally, the closed-loop converter740includes an embodiment of a switching signal generator circuit portion742bsimilar to the switching signal generator circuit342bofFIG. 3Cand a filter circuit744similar to the filter circuit544ofFIG. 5A. The closed-loop converter740advantageously generates a filtered time-varying output signal VsigOut(t) that relates substantially linearly to the time-varying input signal Vsig(t).

FIG. 8illustrates a simplified circuit diagram of a radio-frequency (RF) amplifier circuit840capable of high-speed closed-loop envelope tracking, in accordance with some embodiments. The RF amplifier circuit840includes an embodiment of the closed-loop converter740as shown and described with reference toFIG. 7. Additionally, the RF amplifier circuit840generally includes an envelope detector circuit872, a signal delay circuit874, and a power amplifier circuit876. The RF amplifier circuit840receives an RF input signal RFsigIn(t) at an input node878. The envelope detector circuit872is a circuit suitable for generating, at an envelope signal output node, a time-varying envelope signal Venv(t) that corresponds to an envelope of the RF input signal RFsigIn(t). The time-varying envelope signal Venv(t) is received at the signal input node248of the closed-loop converter740. In some embodiments, a maximum frequency component fMAX(Venv(t)) of the time-varying envelope signal Venv(t) is greater than 10 MHz. The closed-loop converter740generates a filtered time-varying output signal VenvOut(t) (i.e., an amplified envelope signal) at the signal output node254. The filtered time-varying output signal VenvOut(t) is received by the power amplifier circuit876and is used thereby as a power rail. The power amplifier circuit876receives the RF input signal RFsigIn(t) or a signal based on the RF input signal RFsigIn(t) (e.g., a delayed RF input signal RFsigIn(t+T)), delayed by the signal delay circuit874, and generates an amplified signal RFsigOut(t) at an RF signal output node880. The RF amplifier circuit840implemented with the closed-loop converter740advantageously uses a single boost stage (e.g., the switch S1) and does not require an additional switch-mode buck power converter or linear power converter. Thus, the overall efficiency of the RF amplifier circuit840is improved over typical RF amplifier circuits having additional switch-mode converters, and/or linear power converters.

FIG. 9illustrates a simplified circuit diagram of an audio amplifier circuit940with high-speed closed-loop envelope tracking, in accordance with some embodiments. The audio amplifier circuit940includes an embodiment of the closed-loop converter740as shown and described with reference toFIG. 7. Additionally, the audio amplifier circuit940generally includes an audio signal source942(i.e., an audio input circuit) and an audio transducer circuit or downstream audio circuitry944(e.g., a speaker, additionally amplification, or additional signal conditioning circuitry). The audio amplifier circuit940receives a time-varying audio signal Vaud(t) from the audio signal source942at the signal input node248of the closed-loop converter740. In some embodiments, a maximum frequency component fMAX(Vaud(t)) of the time-varying audio signal Vaud(t) is greater than 20 Hz and less than or equal to 20 kHz. The closed-loop converter740generates a filtered time-varying output signal VaudOut(t) (i.e., an amplified audio signal) at the signal output node254. The filtered time-varying output signal VaudOut(t) is received by the audio transducer or downstream audio circuitry944. The audio amplifier circuit940, implemented with the closed-loop converter740, advantageously uses a single boost stage (e.g., the switch S1) and does not use an additional switch-mode buck power converter or linear power converter. Thus, the overall efficiency of the audio amplifier circuit940is improved over audio amplifier circuits having additional switch-mode converters, and/or linear power converters.

In the preceding description, like reference numbers were used to identify like elements. Furthermore, drawings are intended to illustrate major features of example embodiments in a diagrammatic manner. The drawings are not intended to depict every feature of actual embodiments nor relative dimensions of the depicted elements and are not drawn to scale. Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.