Low overhead soft error tolerant flip flop

A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic circuits, and more particularly, to an efficient method of soft error recovery within a flip-flop.

2. Description of the Relevant Art

Modern microprocessors may include one or more processor cores, or processors, wherein each processor is capable of executing instructions of a software application. Modern processors are typically pipelined, wherein the processors include one or more data processing stages connected in series with storage elements placed between the stages. The storage elements typically are flip-flop circuits. The output of one stage is made the input of the next stage during each transition of a clock signal.

Some processors may have multiple pipelines. Therefore, the number of flip-flop circuits, which has reached the hundreds of thousands on modern designs, has been increasing with each generation of processors. Further, the geometric dimensions of devices and metal routes on each generation of processors is decreasing. This geometric decrease causes a decrease in the capacitance used for storage of charge on nodes of the semiconductor chip, although the cross-capacitance of metal routes increase. Also as the channel lengths of transistors decrease, electrostatic fields at the source and drain terminals of transistors increase, which increases both the hot-electron effects and the potential failure.

In order to both reduce the power consumption of the chip, which is proportional to the square of the power supply voltage, and reduce the electrostatic fields within the transistors, the power supply voltage is decreased as well. There is a limit to the power supply voltage reduction, since this reduction deceases the amount of current that may flow through a transistor and, thus, increases the propagation delays through transistors. If the threshold voltages are reduced in order to turn-on the transistors sooner and aid in maintaining performance, then transistor leakage current increases. An increase in transistor leakage current both increases power consumption and the potential for logic failure.

With both the node capacitance and the supply voltage decreasing over time with the next generations of new processors, the amount of electrical charge stored on a node decreases. Due to this fact, nodes used for storage are more susceptible to radiation induced soft errors caused by high energy particles such as cosmic rays, alpha particles, and neutrons. This radiation creates minority carriers at the source and drain regions of transistors to be transported by the source and drain diodes. The change in charge compared to the total charge, which is decreasing with each generation, stored on a node may be a large enough percentage that it surpasses the circuit's noise margin and alters the stored state of the node. Although the circuit is not permanently damaged by this radiation, a logic failure may occur.

For the above reason, memories such as static random access memory (SRAM) use error correcting code (ECC) to detect and correct soft errors. Sequential elements, such as flip-flops, may use larger capacitance nodes or redundant latches within their design in order to combat soft errors. However, these techniques significantly increase the area and propagation delay of the flip-flop.

In view of the above, an efficient method for detecting and correcting soft errors in a flip-flop circuit is desired.

SUMMARY OF THE INVENTION

Systems and methods for soft error recovery within a flip-flop are contemplated.

In one embodiment, a flip-flop circuit comprises a first stage, a second stage, and soft error recovery (SER) circuitry. The first stage may receive an ungated input clock signal. The second stage may receive a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The SER circuitry may be used to recover the prebuffered data output and any feedback storage value without a transition of any clock signal.

Also contemplated is a method to store a prebuffered data output and one or more feedback storage values on separate nodes. Both an ungated input clock signal and a gated input clock signal are received in order to store an input data value on the prebuffered data output node. The method is able to recover the prebuffered data output and any feedback storage value without a transition of any clock signal.

These and other embodiments will be appreciated upon reference to the following description and accompanying figures.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention.

Referring toFIG. 1one embodiment of a series of timing paths100using flip-flop circuits is shown. This embodiment does not include all examples of timing paths such as replacing a flip-flop circuit with a single latch circuit, replacing combinatorial logic with dynamic logic, or replacing logic with a memory such as a random access memory (RAM) cell or a register file circuit. The embodiment shown is for a simple illustrative purpose.

Flip-flop circuits130a-130cmay use a master-slave latch configuration. Flip-flop circuits130a-130cmay also include single or double output lines, and one of many embodiments for feedback circuits and scan circuitry. As used herein, elements referred to by a reference numeral followed by a letter may be collectively referred to by the numeral alone. For example, flip-flop circuits130a-130cmay be collectively referred to as flip-flop circuits130. A data input signal is received by line Datain102. In this embodiment, flip-flops130aand130creceive a same clock signal, ClkA, on line104.

A first timing path exists between the output of flip-flop130aand the input of flip-flop130b. Combinatorial logic, Logic120a, receives the output of flip-flop130a, performs combinatorial computations dependent on the output of flip-flop130a, and conveys an output value to the input of flip-flop130b. A second timing path including logic120bexists between flip-flops130b-130c.

FIG. 2illustrates one embodiment of a flip-flop circuit200. This particular embodiment is a positive-edge triggered flip-flop comprising pass-gates, or transmission gates, to implement a master latch and a slave latch. One skilled in the art knows other embodiments may include a negative-edge triggered design, and the master-slave configuration may be implemented with other transistor topologies such as sense amps, C2MOS topology, dynamic circuits, differential inputs, and other design choices. Output data from combinatorial logic, dynamic logic, sequential elements such as latches, other flip-flop circuits, or other is received by the data input line Din202. A clock signal is received by input clock line204. A transition of the clock signal (i.e. changing from a logic low value to a logic high value in the positive-edge triggered example) initiates logic value state changes within the flip-flop circuit200. A logic high value may be equivalent to the value of a power reference and a logic low value may be equivalent to the value of a ground reference. Inverters206and242provide inverted values of the received clock signal on lines208and244, respectively. Inverters210and240provide non-inverted values of the received clock signal on lines212and238, respectively. Also, it is possible to use only two inverters, rather than four inverters, to supply the appropriate value of the clock signal to the master and slave latches. However, the use of four inverters may be used to reduce the capacitive loading on the clock line204. For example, inverters206and242may isolate the internal nodes of the flip-flop from the clock line204, which may aid in reducing the sizing of clock buffers higher up in the clock distribution system. Also, inverters206,210,242, and240provide unconditional buffered clock signals, since the output clock signals from these inverters do not depend on any other signals or logic.

In this embodiment, a master latch may be implemented by devices214,218, and220. Inverter214provides an inverted value, Din_n216, of the value on line Din202to a transmission gate implemented by transistors218and220. A slave latch is implemented by devices230,234, and236. Inverter230provides an inverted value, a_n232, of the output value, a222, of the master latch transmission gate. The slave latch transmission gate is implemented by transistors234and236. An inverter254buffers the output of the slave latch, b246, and provides the output of the flip-flop circuit, Qbar256. Node b246is the prebuffered data output of the flip-flop200. Also node b246is the internal stored state of flip-flop200. Output inverter254also isolates the output capacitance of the flip-flop circuit from the slave latch transmission gate.

The master latch and slave latch receive inverted clock signals respective of one another. In the positive-edge triggered embodiment shown, the clock lines208and212are coupled to the transmission gates in a manner to provide the respective inverted clocking. When the received clock signal on line204has a logic low value, the master latch is transparent and transmits values from the data input line202to node222. At the same time, the slave latch is opaque and no data transmission from node232to node246occurs. When the clock signal on line204transitions from a logic low value to a logic high value, the reverse scenario occurs and the master latch is opaque and the slave latch is transparent.

In this manner, the output node256is dependent on the data input line202and the clock signal on line204. In one embodiment, inverters224,228,248, and252are used as feedback circuits on the output nodes of the transmission gates. Without the feedback circuits, when the transmission gates are opaque, there is no driver to ensure their output values are not lost. In the embodiment shown the output value on node256is an inverted value of the data input line202when the master latch becomes opaque. In alternative embodiments, a separate output may be included in circuit200to convey a non-inverted value. Also, in alternative embodiments, modern designs may have one of many embodiments of scan circuitry included in the flip-flop circuit200for testing purposes. For simplicity, a scan circuit is not shown.

FIG. 3illustrates one embodiment of a flip-flop circuit300with a simplified conditional technique for reducing power consumption and reducing the time the slave latch is susceptible to soft errors. Circuit300is the same flip-flop as shown in circuit200except for the replacement of inverter242with an OR-AND-Inverter (OAI) gate310. One input to the OAI gate310is the received ungated clock signal on line204. A second input is an inverted value of the stored state of the flip-flop, or an inverted value of the output of the slave latch transmission gate, node fbb250. The third input is the output of the master latch transmission gate, node a222, or the inverted value of the input data, D202.

The OAI gate310conditionally disables the received ungated clock input204and provides a gated clock input signal S_n244to the slave transmission gate. When the stored state of the flip-flop, node fbb250, and the data input, node a222, have a same logic low value, the slave latch clock lines244and238continue to keep the slave transmission gate opaque. Any toggling of the received clock line204is not able to turn on the slave latch transmission gate.

Following modern CMOS design techniques, the inputs to the OAI gate310are arranged with the earliest arriving signal routed the farthest away from the output node S_n242. This technique allows intermediate nodes of gate310to charge or discharge before the latest arriving signal does arrive. Therefore, the propagation delay of gate310is reduced. Here, the earliest arriving signal is the stored state of the flip-flop, fbb250. Its value is set when a new value is stored in the flip-flop upon the rise of the received clock204. Therefore, signal fbb250is routed the farthest away from the output node.

The middle input of gate310is node a222. A value arrives on this node when computations performed by logic between flip-flops have completed during the clock cycle and meet the flip-flop setup time requirement. Finally, the rising edge of the received clock signal204arrives last and it is routed to the nearest input of gate310to the output of gate310as shown inFIG. 3.

Gate310may take advantage of the fact that a flip-flop stored state does not change often, such as less than 2% of the time, and that the majority of flip-flops store a state of a logic low value. Therefore, if a flip-flop is not going to change state, or nodes222and250have the same value prior to the arrival of the received clock signal204, then there is no need to supply a clock signal to the slave latch. Further, a full comparison, implemented by an XOR gate, of the values of the nodes222and250is not needed if the majority of the time node250has a logic low value. Then gate310may be used in place of a full XOR gate. Gate310requires less transistors and has a smaller delay penalty than a full XOR gate. Circuit designers, both custom designers and synthesis designers, may aid the reduction of power consumption by designing logic to provide inputs to flip-flop circuits, such as flip-flop300, that place a logic low value on internal nodes222and250.

As stated above, motivation for implementing the OAI gate310in a flip-flop, such as inFIG. 3may be to both reduce power consumption by decreasing the time internal nodes switch and to reduce the time the slave latch is susceptible to soft errors. For example, in one embodiment, a processor may have a duty cycle for the clock signals of 50%, which allows the slave transmission gate to be transparent 50% of the time. Also, power reduction techniques may disable the clock signal in the global distribution system at one or more stages prior to the clock signals arriving to the flip-flops. This global or block-level clock gating may disable the clock signal 70% of the time. Therefore, the slave transmission gate may be transparent only 30% of the original 50% of the time, which is 15% of the time.

In one embodiment, now clock gating performed by circuits such as OAI gate310, which take advantage of the fact that flip-flops may not need to change a stored internal state of a logic high value, such as node b246, 63% of the time. Thus, the slave transmission gate may be transparent 37% of the 15% derived above, which is 5.6% of the time. By making the transmission gate opaque 94.4% of the time, the slave latch internal nodes are not susceptible to soft errors that occur in the master latch. However, these internal nodes are susceptible to soft errors within the slave latch during this 94.4% time period. Circuitry to detect and correct soft errors in the slave latch while the slave transmission gate is opaque is shown inFIG. 11and will be described later.

FIG. 4Aillustrates a method400for reducing soft errors occurring on a semiconductor chip. Method400may be modified by those skilled in the art in order to derive alternative embodiments. Also, the steps in this embodiment are shown in sequential order. However, some steps may occur in a different order than shown, some steps may be performed concurrently, some steps may be combined with other steps, and some steps may be absent in another embodiment. In the embodiment shown, a semiconductor chip is floorplanned and individual blocks and cells are placed according to the floorplan in block402.

In block404, architectural logic is verified and design checks are performed. Some of these design checks may be used to ensure circuits meet noise thresholds, migration current thresholds, and other predetermined criteria. Another design check may be utilized to encourage conditional gating of a second stage, or a slave latch, of a flip-flop. For example, in one embodiment, storage of a logic low value, or a value equivalent to a ground reference, in flip-flops may be used to conditionally gate, or turn-off, the clock signal to the slave latch. An example of such a technique is further described later. Custom circuit designers and synthesis designers, such as programmers using register transfer language (RTL) synthesis tools, may design their cells and blocks to place a logic low value both on the input data line and the internal stored node of the slave latch of flip-flop circuits. Such a design requirement may be used in a complex gate used to disable a clock signal to the slave latch. In this manner, the slave transmission gate is opaque the majority of the time and internal switching of flip-flop nodes is decreased. Therefore, both power consumption reduces and soft error susceptibility reduces. The reduction in soft error susceptibility is due to the slave transmission gate being opaque and any voltage noise on nodes prior to the slave transmission gate is not able to affect nodes subsequent the slave transmission gate.

Pre-silicon timing analysis is performed in block406. Timing paths and circuits are redesigned and transistors are resized in order to meet the target clock cycle for the chip design. If a flip-flop is determined to be architecturally critical to the design of the chip (conditional block408), then a flip-flop utilizing soft error detection and recovery circuitry may be inserted in a corresponding timing path in block410. In one embodiment, the architecturally critical flip-flop may not be in a timing critical path and a low-power flip-flop utilizing a complex gate to conditionally disable a slave latch clock input may be inserted in the timing path in block410. If the timing path does not meet a predetermined timing threshold or the corresponding stored data is not architecturally critical (block408), then another flip-flop version may be chosen to be inserted in the timing path in block416.

If all timing paths have been inspected and the appropriate flip-flop circuit has been inserted in the timing paths (block412), then the chip is ready for tape-out as long as all other design requirements not affecting flip-flop insertion have been satisfied also in block414. If all timing paths have not yet been inspected (block412), control flow returns to conditional block408.

FIG. 4Billustrates one embodiment of a method for detecting and correcting soft errors within a flip-flop. As with method400, method440may be modified by those skilled in the art in order to derive alternative embodiments. Also, the steps in this embodiment are shown in sequential order. However, some steps may occur in a different order than shown, some steps may be performed concurrently, some steps may be combined with other steps, and some steps may be absent in another embodiment. In the embodiment shown, a processor executes instructions in block442. Flip-flop circuits store states used by logic on the semiconductor chip. A particular flip-flop that uses soft error recovery circuitry as described by the invention later stores an architecturally critical state on an internal node of its second state, or slave latch, in block444.

An input clock signal to the slave latch of the flip-flop is disabled in block446. This clock gating may be performed when the input data to the flip-flop and the stored internal state of the flip-flop have the same logic value. In this case, the output of the flip-flop is not going to change value, and it is unnecessary to have switching of internal nodes of the flip-flop. In one embodiment, the clock gating may only occur when the input data and the stored internal state have a same value of only a particular value, such as a logic high value and not a logic low value. This further restriction allows the clock gating to require less area and less delay penalty. Referring again toFIG. 3, in one embodiment, the OAI gate310may provide clock gating of the slave latch. When the input data D202and the stored internal state b246both have a logic low value, the input clock to the slave latch, S_n244, is disabled, which causes the slave latch to remain opaque. Power consumption is reduced. Also, any voltage noise caused by radiation on a node between node202and node232can not affect the stored internal state b246.

If radiation hits a node in the slave latch (conditional block448), soft error recovery circuitry either disallows a stored state to occur or it recovers the lost state in block450. The circuitry can perform both operations without a clock pulse. In short, this circuitry uses feedback nodes and transistor sets to perform these operations without a clock pulse. This circuitry is shown inFIG. 11and is described later.

If no radiation hits a node in the slave latch (conditional block448), or the internal state was restored or unaffected by a radiation hit (block450), then flow control goes to block452. In block452, eventually the slave latch clock needs to be enabled. For example, the input data to the flip-flop provides a logic low value that meets the setup time of the flip-flop. The slave latch clock is enabled and the new data value propagates through the slave transmission gate to the stored internal state node. Afterwards, control flow of the method returns to block444.

Referring toFIG. 5, one embodiment of a flip-flop circuit500with split clocks is shown. The flip-flop circuit300is provided, but with an additional clock signal, a separate slave clock signal, provided on line504. This additional clock signal along with nodes222and250determines when the slave transmission gate is transparent or opaque. The master clock signal may have the same duty cycle as the slave clock signal and be in phase with the slave clock signal, but a delay may exist between the rising and falling edges of the slave clock signal and the respective edges of the master clock signal. A design with the split clocks and a delayed master clock signal may be used to shift the rising edge of the master clock, which is used to define the setup time of the flip-flop. This shifting allows a timing path prior to the flip-flop to have more time for logic computations without increasing the clock cycle. Timing waveforms that display this shifting and increase in computation time is described later.

FIG. 6illustrates one embodiment of a series of timing paths600using flip-flop circuits with split clocks. This embodiment as with the embodiment shown inFIG. 1does not include all examples of timing paths, but shows one example for a simple illustrative purpose.

Flip-flop circuits500may use a master-slave latch configuration. Flip-flop circuits500may also include single or double output lines, and one of many embodiments for feedback circuits and scan circuitry. A data input signal is received by line Datain102. In this embodiment, flip-flops500aand500creceive a same master clock signal, ClkA, on line104. Flip-flop circuit500breceives a master clock signal, ClkB, on line612. Each flip-flop500receives a slave clock signal ClkC on line606. A description of these clock waveforms is described next.

FIG. 7illustrates one embodiment of the clock waveforms700used for the timing requirements of timing paths shown inFIG. 6. As can be seen here, master clock waveform ClkB612has a same duty cycle as master clock waveform ClkA104, but is delayed from ClkA104by a programmable delay value702. In one embodiment, this delay may be implemented by clock delay circuits within the clock distribution system and delay702may be set in post-silicon in order to ease fixing timing paths in post-silicon. In one embodiment, the Programmable Delay702, may be implemented in post-silicon, or after the semiconductor chip is fabricated and returned for testing. Failing timing paths, such as the timing path with Logic220a, may be fixed in post-silicon by changing the clock signal supplied to flip-flop230bfrom ClkA104to ClkB612.

Slave clock waveform ClkC606is shown to have the same duty cycle as master clock waveform ClkA104with no delay. In alternative embodiments, a non-zero delay may exist between master clock ClkA104and slave clock ClkC606and this delay value may be different from the value of the programmable delay702.

Flip-flop500amay have a clock-to-Q value, C2Q710a, which represents the delay between the time the clock signal rises and the output of flip-flop500ais present on its output line. Flip-flop500amay have a setup time of Setup704athat requires the input signal on its input line to remain stable for a minimum duration prior to the rise of the master clock signal. This duration may be defined by the delay of the inverter supplying the inverted input data value to the master transmission gate and the delay of the master transmission-gate. Further, the delay is extended by a transistor delay by OAI gate310. If the data input signal is not stable for the setup duration prior to the clock rising, then the input data value may not have time to be stored by the master latch.

Also, flip-flop500amay have a hold time value of Hold706athat requires the input signal on its input line to remain stable for a minimum duration subsequent the rise of the clock signal. This duration may be defined by the delay of the inverter supplying the inverted input data value to the master transmission gate and the delay of the master transmission gate. If the data input signal is not stable for the hold duration subsequent to the clock rising, then the input data value may have time to over-write the required value to be stored by the master latch.

Flip-flop500bmay have a setup time, Setup704b. Due to the programmable delay702that delays the clock edge transitions of master clock waveform ClkB612with respect to master clock waveform ClkA104, Logic220ahas more time for computations represented by Logic Time708b. If flip-flop500breceived master clock ClkA104instead, then Logic220aonly has time for computations represented by Logic Time708a, which is smaller. Since the duty cycles of ClkA104and ClkB612are the same, the frequency of the design did not change, but more time was given to Logic220ato perform computations by the use of master clock Clk B612provided to flip-flop500b.

Because the slave clock Clk C606provided to flip-flop500bis not delayed as its master clock Clk B612, this implementation does not increase the perceived C2Q value of the subsequent timing path. Therefore, the C2Q delay of flip-flop500bis shown as C2Q710d. If flip-flop500bdid not have split clocks, but only received a single clock, and its slave clock was delayed the same amount as the master clock, then the C2Q delay of flip-flop500b, C2Q710b, would be delayed and provide the perceived delay value of C2Q710c. However, this is not the case as flip-flop500bhas a separate slave clock, ClkC606, which is not delayed.

However, the split clocks do provide a design trade-off. The hold time of flip-flop500b, Hold706b, is delayed, since its master clock waveform, ClkB612, is delayed. Therefore, Logic220amust provide a stable value to the input of flip-flop500bfor a longer duration than required without a delayed master clock. However, this timing requirement may be easily many for many paths.

Referring toFIG. 8, an alternative embodiment of a low power flip-flop circuit800is shown. Flip-flop800is similar to flip-flop500shown inFIG. 5, but the master latch and slave latch include different feedback circuits and include scan test circuitry, which will be shown shortly.

A data input signal is provided on line202as before. A master clock signal and a separate slave clock signal are provided on lines502and504, respectively, as described above. One input to the OAI gate310is the received separate slave clock signal on line504. A second input is an inverted value of the stored state of the flip-flop, or an inverted value of the output of the slave transmission gate within slave latch1000. This value is routed on line IntQB816. The third input is the output of the master transmission gate within master latch900. This value is routed on line D_n812.

Again, the OAI gate310conditionally disables the received slave clock input504. When the values on the lines812and816have a same logic low value, the gated clock signal ClkGated814continues to keep the slave transmission gate opaque within slave latch1000. Any toggling of the received separate slave clock line504is not able to turn on the slave transmission gate.

The output of the master transmission gate is routed to the input of the slave transmission gate on line DS820. A scan test control signal, ScanCtrl806, and a scan test data signal, ScanData808, are provided to the master latch900. A scan output signal, ScanOut822, and the flip-flop data output signal, Qbar256, are conveyed by the slave latch1000.

FIG. 9illustrates an alternative embodiment of a master latch with circuit900. Inverter912provides an inverted value of the received data input value on line DM904to a master transmission gate implemented by transistors916and918. Inverter910provides an inverted value of the received input clock signal on line902. Inverter914provides a buffered non-inverted value of the received input clock signal on line902. Inverter950buffers the output of the master transmission gate and conveys the output DB948to an outside slave latch. The output of the master transmission gate, D_n946, is routed out of the master latch and to the outside OAI gate310.

When the received clock signal on line902has a high logic value and causes the master transmission gate to become opaque, the node D_n946needs a driver to maintain the value latched by the master latch900. During operation, the scan test inputs, SC906and SDI908, are each set to a logic low value. Therefore, transistors938and942are turned off and do not conduct. Therefore, the set of transistors936-942do not drive the feedback node FB952.

The set of transistors928-934has at least one conduction path to a power reference or to a ground reference and, therefore, this set does drive the feedback node FB952. An inverted value of the node D_n946is driven onto node FB952by this set of transistors. The set of transistors920-926has at least one conduction path to a power reference or to a ground reference and this set drives a non-inverted value of the node D_n946back onto this same node and completes the feedback network.

During testing, the received scan test control signal SC906is asserted to a logic high value. The set of transistors928-934now do not have a conducting path to a power reference or a ground reference and this set does not drive the node FB952. Now the set of transistors936-942has at least one conducting path to a power reference or a ground reference dependent upon the received scan test data input SDI908. An inverted value of the input SDI908is driven onto node FB952. Again, the received clock signal on line902has a high logic value and causes the master transmission gate to become opaque. The set of transistors920-926has at least one conducting path to a power reference or a ground reference dependent upon the node FB952. An inverted value of node FB952is driven onto node D_n946. This value is the same as the received input SDI908.

FIG. 10illustrates an alternative embodiment of a slave latch1000without soft error detection and correction circuitry. The output data of a master latch, whether it is during normal operation or during testing, is received on line DS1004, which is provided to a slave transmission gate implemented by transistors1006and1008. The gated clock output of the OAI gate310is received on line1002. Inverter1010provides an inverted value of the received input clock signal to the slave transmission gate. Both the non-inverted and inverted values of the received clock signal on line1002are provided to the set of transistors1012-1018used as a feedback network.

A transparent slave transmission gate provides the received data input DS1004to inverters1022and1026. Inverter1026buffers this value and provides an inverted value as the output of the slave latch on line QB1030. Inverter1022provides the same logic value as QB1030to the feedback network implemented by the set of transistors1012-1018and to the output node IntQB1020, which is received by the outside OAI gate310.

When the slave transmission gate is opaque, transistors1014and1016are on and may conduct. The logic value of the node IntQB1020determines if the set of transistors1012-1018has a conducting path to a ground reference or to a power reference. Therefore, the output of the slave transmission gate is still driven. The input of inverter1024has an inverted logic value of the node IntQB1020. Inverter1024provides the output value SDO1028, which is the same logic value as the output value QB1030.

Referring toFIG. 11, one embodiment of a slave latch1100with soft error detection and correction circuitry is shown. Input and output signals1002,1004,1028, and1030are the same as for circuit1000. Devices1006-1018and1024-1026are also the same as for circuit1000. The set of transistors1122-1132drive values onto a pair of feedback nodes fbp1120and fbn1156that are used for soft error detection and correction. The value on node fbp1120is also provided to a slave clock conditional gating circuitry such as the OAI gate310described earlier. The set of transistors1134-1144drive a value onto feedback node fb1154, which is used as an input to transistors1122-1124and1130-1132in order to derive values for the feedback nodes fbp1120and fbn1156, respectively. Also, the node qf1152, the output of the slave transmission gate, is used as an input to derive values for these feedback nodes. Nodes qf1152and fb1154are inputs to inverters1026and1028in order to convey outputs QB1030and SDO1028, respectively.

There are four storage nodes in circuit1100that are susceptible to radiation. They are nodes qf1152, fb1154, fbp1120and fbn1156. Below is a description of a radiation hit, or a strike case, for each node and how circuit1100detects and recovers from each strike case. For each strike case, the input clock signal is disabled, which makes the slave transmission gate opaque. The reason for inspecting the opaque case is provided in the description above forFIG. 3. Due to this requirement, for each strike case, transistors1014and1016are always on and conduct. Also, transistors1136and1142are always off and do not conduct. Detection and recovery of soft errors described below does not require a clock pulse.

Strike Case 1: Negative charge is injected on node qf1152

In this case, transistor1144turns on, transistor1134turns off, transistor1138remains on, and transistor1140remains off. Node fb1154is unaffected and remains at a logic high value. Therefore, the stored internal state is not lost by a temporary voltage pulse, or noise, induced by radiation. The feedback provided by the conducting transistors within the set1012-1144will remove the voltage noise on node qf11152.

Strike Case 2: Positive charge is injected on node qf1152

In this case, transistor1144turns off and transistor1134turns on. Series transistors1134and1136contend with parallel transistors1140and1142. However, the channel width sizing may be done in order to ensure that transistors1140and1142are stronger and are able to discharge their output node. For example, in one embodiment, transistors1134,1136,1140, and1142may all have equal channel widths. Node fb1154is unaffected and remains at a logic low value. The feedback provided by the conducting transistors within the set1012-1144will remove the voltage noise on node qf1152.

Strike Case 3: Negative charge is injected on node fb1154

In this case, transistor1122turns on, node fbp1120rises to a logic high value temporarily, and turns off transistor1012. Node fbn1156is not charged up by transistor1130since transistor1128remains turned off. Transistor1140turns on, but transistor1144remains turned off. Node qf1152is unaffected, and therefore, node fb1154is allowed to recover.

Strike Case 4: Positive charge is injected on node fb1154

In this case, transistor1132turns on, node fbn1156discharges, and transistor1018turns off. Transistor1124turns on, but it doesn't discharge node fbp1120since transistor1126remains off. Therefore, node qf1152remains at a logic low value and later node fb1154recovers.

Strike Case 5: Negative charge is injected on node fbp1120

In this case, transistor1012turns on. Now series transistors1012and1014contend with series transistors1016and1018. Node qf1152may be briefly charged up, but node fbn1156remains at a logic high value. Transistor1128may have been briefly turned off, but transistor1130remains on and transistor1132remains off. Therefore, node fbn1156does not discharge and node fb1154is unaffected.

Strike Case 6: Positive charge is injected on node fbn1156

In this case, transistor1018turns on. Now series transistors1012and1014contend with series transistors1016and1018. Node qf1152may be briefly discharged. Transistor1126may turn off, but transistor1122remains off. Therefore, node fbp1120remains at a logic low value. Transistor1140remains off and node fb1154is unaffected.