Display device including process key

The present disclosure relates to a display device including a process key, and more particularly, to a process key with an improved recognition rate in a display device implementing a narrow bezel. The feature of the present disclosure is such that a process key is divided into and formed as a first key pattern made of a metal material and a second key pattern made of a black matrix material, and the process key is positioned in a green pixel area in which a green color filter pattern is provided among pixels positioned at outermost peripheries corresponding to four corners of an active area of a display panel such that a narrow bezel can be implemented and a recognition rate of the process key can also be improved. Consequently, the display panel can be accurately aligned with manufacturing equipment or other objects such that a process defect can be minimized and process efficiency cab also be improved. Further, the process key can be recognized from both upper and lower sides of the display panel so that the process can be improved.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(a) of Republic of Korea Patent Application No. 2017-0143331, filed on Oct. 31, 2017, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to a display device including a process key, and more particularly, to a process key with an improved recognition rate in a display device implementing a narrow bezel.

2. Discussion of the Related Art

Recently, as society has entered a full-fledged information age, display fields for processing and displaying mass information have rapidly advanced, and various display devices have been developed and have been getting attention in response to such advance.

Specific examples of the display devices include liquid crystal displays (LCDs) device, plasma display panel (PDP) devices, field emission display (FED) devices, electroluminescent display (ELD) devices, and organic light emitting diode (OLED) devices, and these display devices are excellent in performance of reducing thickness, weight, and power consumption to rapidly replace existing cathode ray tubes (CRTs).

Among these display devices, the LCD device includes an array substrate including a thin film transistor, a color filter substrate having a color filter and/or a black matrix, and a liquid crystal layer formed between the array substrate and the color filter substrate, thereby constituting a display panel. The alignment state of the liquid crystal layer is controlled according to an electric field applied between both electrodes of a pixel area so that light transmittance is controlled and thus an image is displayed.

Further, the OLED device includes a switching thin film transistor, a driving thin film transistor, first and second electrodes, a first substrate including an organic light emitting layer that is disposed between first and second electrodes, and a second substrate compressed and bonded to the first substrate, thereby constituting a display panel. A degree of light emission of an organic material is controlled according to a level of a voltage or an amount of a current applied between both electrodes of a pixel area, and thus an image is displayed.

When various processes (scribing, grinding, a module process, etc.) are performed on such display devices in states of the display panels, a process key for various purposes may be used for alignment with manufacturing equipment or other objects.

A process key is formed in a non-active area which is a bezel area of each of display panels and the process key may include a plurality of key patterns, each of which has a unique pattern or shape, so as to allow equipment of each process to recognize the plurality of key patterns. Although research has been actively conducted in recent years to reduce the bezel area of a display device, a process key positioned in the bezel area impose a limit on how narrow small the bezel area can become.

SUMMARY

Embodiments relate to providing a display device in which a bezel area is minimized.

Further, embodiments relate to allow a process key to be definitely detected at an upper side or a lower side of a display panel.

One or more embodiments relate to a display device including: a first substrate and a second substrate which face each other and in which an active area, in which an image is implemented, and a non-active area formed along an edge of the active area are defined; and a process key including a first key pattern provided on the first substrate to correspond to a corner in the active area, wherein the first key pattern is positioned on the first substrate.

It is to be understood that both the foregoing general description and the following detailed description are explanatory, and are intended to provide further explanation of the embodiments as claimed.

DETAILED DESCRIPTION

FIG. 1Ais a plan view schematically illustrating a display panel according to an embodiment of the present disclosure, andFIG. 1Bis a cross-sectional view ofFIG. 1A. As shown in the drawings, a display panel100is made by bonding a first substrate101(e.g., a lower substrate) and a second substrate102(e.g., an upper substrate). When the display panel100is embodied as a liquid crystal display (LCD) device, a thin film transistor T (ofFIG. 3) is provided on the first substrate101, and a color filter pattern133(ofFIG. 4) and/or a black matrix131(ofFIG. 4) are provided on the second substrate102, and a liquid crystal layer (ofFIG. 4) is interposed between the first substrate101and the second substrate102.

Further, when the display panel100is formed as an organic light emitting diode (OLED) device, a switching and drive thin film transistor, first and second electrodes311and315(ofFIG. 8), an organic light emitting layer313(ofFIG. 8) between the first and second electrodes311and315(ofFIG. 8) are provided on the first substrate101, and the second substrate102is spaced apart from the first substrate101by a protective layer303(ofFIG. 8) having adhesiveness and is bonded to the first substrate101through the protective layer303. Such a structure will be described in more detail below.

The thin film transistor T (ofFIG. 3) and/or the first and second electrodes311and315(ofFIG. 8) are positioned on the first substrate101of the display panel100so that a plurality of lines (not shown) are formed and a pad160is connected to a distal end of each of the plurality of lines (not shown). In this case, the plurality of lines (not shown) may be configured with signal lines such as gate and data lines103and105(ofFIG. 3) and common bus lines107(ofFIG. 3) or may be configured with non-signal lines such as antistatic lines (not shown).

In the display panel100according to the embodiment of the present disclosure, the first substrate101and the second substrate102are formed in the same shape, and thus one ends of the first substrate101and the second substrate102coincide with each other, and a side surface of the pad160provided at the distal end of each of the plurality of lines (not shown) is exposed to a side surface between the first substrate101and the second substrate102.

A printed circuit board (PCB)190is connected to one side of the display panel100via a connecting member170such as a flexible PCB, and in this case, the connecting member170is attached and connected to a side surface of the display panel100. That is, the connecting member170is electrically connected to the side surface of the pad160, which is exposed to the side surface between the first substrate101and the second substrate102, though an adhesive layer180bincluding a conductive ball180a. Although the connecting member170and the PCB190are illustrated as being connected to only one side of the display panel100, the connecting member170and the PCB190may be additionally formed at the other side of the display panel100.

Further, the pad160may be formed of the plurality of lines (not shown) as one body on the same layer, or the plurality of lines (not shown) may be formed of the data lines105(ofFIG. 3) provided on a gate insulating layer113(ofFIG. 4) and the pad160may be formed of a data pad provided below the gate insulating layer113(ofFIG. 4), and in this case, the data pad is connected to the data lines105(ofFIG. 3) through a contact hole (not shown) provided in the gate insulating layer113(ofFIG. 4).

In such a display panel100, the side surface of the pad160is exposed to a side surface of the first substrate101, and the connecting member170is attached and connected to the side surfaces of the first and second substrates101and102such that a separate pad formation area (i.e., a pad area) is not required on the first and second substrates101and102.

That is, when viewed from above, the entire area of the display panel100is formed to constitute an active area A/A in which an image is implemented, only excepting an edge area (i.e., a non-active area N/A) for an area in which an actual pattern120is formed. As the edge area (i.e., the non-active area N/A) is reduced, a display panel100with a narrower bezel can be achieved.

As described above, the display panel100with reduced the non-active area N/A has process keys200positioned in the active area A/A according to embodiments of the present disclosure. Particularly, the process key200is configured with a first key pattern210made of a metal material capable of reflecting light, and a second key pattern220made of a black pigment provided along an edge of the first key pattern210, and the process key200is positioned in a green pixel area G-SP (ofFIG. 3). Consequently, in the display panel100of the present disclosure, a recognition rate of the process key200is increased, and the process key200can be easily aligned with manufacturing equipment or other objects when performing various manufacturing processes, such as scribing, grinding, a module process, and the like, on the display panel100. Particularly, the process key200is recognized at both upper and lower sides of the display panel100so that process efficiency can be further improved.

FIG. 2is a plan view schematically illustrating a portion of an LCD device according to a first embodiment of the present disclosure, andFIG. 3is an enlarged plan view schematically illustrating a single pixel positioned at an outermost periphery ofFIG. 2. Further,FIG. 4is a cross-sectional view taken along the line IV-IV ofFIG. 3,FIGS. 5A to 6Fare schematic diagrams illustrating process keys, andFIGS. 7A to 7Care diagrams illustrating experimental results of measuring recognition rates of the process keys according to a color of a color filter pattern. As shown in the drawings, the LCD device according to the first embodiment of the present disclosure includes a display panel100, first and second polarizers140aand140b, and a backlight150for supplying light to the display panel100.

In this embodiment, the display panel100is made by bonding faces of the first substrate101and the second substrate102with the liquid crystal layer104interposed therebetween. The first substrate101, which is referred to as a lower substrate or an array substrate, and the second substrate102, which is referred to as an upper substrate or a color filter substrate, are formed in the same shape so that one ends of the first substrate101and the second substrate102coincide with each other.

The display panel100includes an active area A/A, which displays an image, and a non-active area N/A, which is provided along an edge of the active area A/A and is not used to display an image, the non-active area N/A is defined along an edge of the display panel100, and the active area A/A is positioned inside the non-active area N/A.

The actual pattern120is positioned in the non-active area N/A to prevent leakage of the liquid crystal layer104which fills in a space between the first substrate101and the second substrate102. In the LCD device according to this embodiment, since the pad160is exposed to the side surface of the display panel100, a separate pad formation area is not required on the first and second substrates101and102. Therefore, the non-active area N/A is formed to correspond to a width of the actual pattern120.

A plurality of pixel areas R-SP, G-SP, and B-SP are defined in the active area A/A of the display panel100, and each of the pixel areas R-SP, G-SP, and B-SP is defined through the plurality of data lines105and a plurality of gate lines103, which are provided at the first substrate101, vertically and horizontally intersect with each other, and the thin film transistor T which is a switching element is provided at a crossing point between the two lines103and105.

More specifically, on the first substrate101, the plurality of gate lines103are formed in parallel to be spaced at predetermined intervals, the common bus lines107are formed adjacent and parallel to the gate lines103, and the data lines105are formed to intersect with the gate lines103and the common bus lines107, and particularly, with the gate lines103, thereby defining the R (red), G (green), and B (blue) pixel areas R-SP, G-SP, and B-SP.

The thin film transistor T is formed in a switching area which is the crossing point of the gate line103and the data line105of each of the R, G and B pixel areas R-SP, G-SP and B-SP, and a common electrode125connected to the common bus line107and a pixel electrode123connected to the thin film transistor T are formed in the active area A/A in which an image is actually implemented.

The thin film transistor T includes a gate electrode111, a gate insulating layer113, a semiconductor layer115which includes an active layer115amade of pure amorphous silicon, and an ohmic contact layer115bmade of amorphous silicon doped with impurities, and source and drain electrodes117and118.

The pixel electrode123is electrically connected to the drain electrode118of the thin film transistor T. A plurality of bar-shaped pixel electrodes123and a plurality of bar-shaped common electrodes125are alternately positioned and spaced apart and are formed in the R, G and B pixel areas R-SP, G-SP and B-SP.

The gate electrode111may extend from the gate line103, or the gate electrode111may be made of a portion of the gate line103, and in this case, the gate electrode111may have a width that is wider than other portions of the gate line103.

The protective layer121is formed on a front surface of the first substrate101including the thin film transistor T. In this case, a drain contact hole118afor exposing the drain electrode118of the thin film transistor T is provided in the protective layer121.

In an alternative embodiment, the pixel electrode123may be formed in a plate shape in each of the R, G and B pixel areas R-SP, G-SP and B-SP. In this case, a portion of the pixel electrode123may be formed to overlap the gate line103to constitute a storage capacitor.

Further, when a plurality of pixel electrodes123and a plurality of common electrodes125are formed to be spaced apart from each other in each of the R, G and B pixel areas R-SP, G-SP and B-SP, the display panel100operating in an in-plane switching (IPS) mode is formed, and only a plate-shaped pixel electrode123is formed at the first substrate101except the common electrode, the display panel100, which operates in one mode among a twisted-nematic (TN) mode, an electrically controlled birefringence (ECB) mode, and a vertical alignment (VA) mode, is formed. An example of the display panel100operating in the IPS mode will be described with reference to the drawings.

Further, the black matrix131corresponding to the gate line103, the data line105, and the thin film transistor T of each of the R, G and B pixel areas R-SP, G-SP and B-SP, which are formed at the first substrate101, is formed on the second substrate102facing the first substrate101.

Accordingly, the black matrix131has an aperture corresponding to each of the R, G and B pixel areas R-SP, G-SP and B-SP, and a color filter layer including an R color filter pattern (not shown), the G color filter pattern133, and a B color filter pattern (not shown) (corresponding to the apertures and are sequentially and repetitively disposed) is formed.

A pixel area with the R color filter pattern (not shown) is defined as the R pixel area R-SP, a pixel area with the G color filter pattern133is defined as the G pixel area G-SP, and a pixel area with the B color filter pattern (not shown) is defined as the B pixel area B-SP. These R, G and B pixel areas R-SP, G-SP and B-SP collectively form a single pixel P which exhibits various colors.

In this case, although not shown in the drawing, the color filter layer may be omitted, and a white pixel area having a transparent overcoat layer (not shown) may be further provided on an entire surface below the R color filter pattern (not shown), the G color filter pattern133, and the B color filter pattern (not shown).

The LCD device according to the embodiment of the present disclosure has the process key200positioned in the active area A/A in which a plurality of pixel areas SP are provided. That is, the process keys200are positioned in at least four corners of the display panel100, and in this case, the process key200is positioned in the G pixel area G-SP with the G color filter pattern133, to correspond to the four corners of the active area A/A among a plurality of pixels P positioned at outermost peripheries along the edge of the active area A/A.

For example, when a single pixel P is configured with the R, G and B pixel areas R-SP, G-SP and B-SP, and the R, G, and B pixel areas R-SP, G-SP, and B-SP are sequentially positioned from the actual pattern120in the order thereof, the process key200is positioned in the G pixel area G-SP that is secondarily adjacent to the actual pattern120, and when the R, G and B pixel areas R-SP, G-SP and B-SP are positioned from the process key200in the order of the R, B and G pixel areas R-SP, B-SP and G-SP, the process key200is positioned in the G pixel area G-SP that is thirdly adjacent to the actual pattern120. That is, in an array structure of the various pixel areas R-SP, G-SP and B-SP in the single pixel P, the process key200is positioned to correspond to the G pixel area G-SP in the single pixel P positioned at the outermost periphery of the active area A/A.

When R, G1, B and G2pixel areas constitute the single pixel P, the process key200may be positioned in the G1pixel area and the G2pixel area among the R, G2, B and G2pixel areas, and in this case, the process key200may be positioned in a G pixel area positioned at the outermost periphery of the active area A/A among the G1pixel area and the G2pixel area.

The process key200includes the first key pattern210positioned on the first substrate101, and the second key pattern220positioned on the second substrate102and corresponding to an edge of the first key pattern210. The first key pattern210may be made of a material the same as those of the gate line103and the gate electrode111on the same layer and may reflect light. Further, the second key pattern220and the black matrix131are formed of the same material on the same layer.

As described above, the process key200is formed of the first and second key patterns210and220, and particularly, the first key pattern210is formed of a metal material capable of reflecting light, and the second key pattern220and the black matrix131are formed of the same material so that it is possible to generate a large contrast difference between the first key pattern210and the second key pattern220. In this way, the recognition rate of the process key200is increased by a larger contrast difference between the first key pattern210and the second key pattern220.

The first key pattern210is formed of a material the same as those of the gate line103and the gate electrode111on the same layer, and the second key pattern220and the black matrix131are formed of the same material on the same layer so that a separate process of forming the first and second key patterns210and220of the process key200is not additionally required.

Although a shape of the first key pattern210has been shown as a cross shape, the first key pattern210may be formed of various shapes such as “−,” “L,” “O,” and “T” shapes in addition to the cross shape, and alternatively, the first key pattern210may be formed in a shape including at least one among such various shapes.

The second key pattern220may have a shape the same as that of the first key pattern210along an edge thereof, and alternatively, the second key pattern220may be formed of a closed curve shape or a closed polygonal shape which surrounds the first key pattern210. Further, the second key pattern220is formed in the outermost black matrix131on the second substrate102, and the black matrix131may be formed to correspond to the shape of the first key pattern210by being opened or perforated.

The process key200may be formed by performing a sealing process (a bonding process) after positions of the first and second substrates101and102are aligned so as to dispose the first key pattern210on the first substrate101at a center of the second key pattern220which is perforated by compression bonding equipment using a camera such as a charge-coupled device (CCD) camera or the like.

Alternatively, the second key pattern220may be integrated with the first key pattern210to have a single shape, and when the first key pattern210is formed in a half-circle shape, the second key pattern220is also formed of a half-circle corresponding to the first key pattern210so that the first key pattern210and the second key pattern220form a single circle.

Alternatively, as shown inFIG. 5A, when the first key pattern210is formed of a line shape in a first direction, the second key pattern220is formed of a line shape perpendicular to the first direction as shown inFIG. 5Bsuch that, as shown inFIG. 5C, the first key pattern210and the second key pattern220may overlap each other to form a cross shape.

In yet another modification, as shown inFIG. 6A, when the first key pattern210is configured with a first direction pattern210amade of a line shape in a first direction and a second direction pattern210bmade of a line shape in a second direction perpendicular to the first direction, the second key pattern220may be formed in a shape the same as that of the first direction pattern210aalong only an edge of the first direction pattern210aas shown inFIG. 6B, or the second key pattern220may be formed along only a portion of the edge of the first direction pattern210aas shown inFIG. 6C.

Alternatively, as shown inFIG. 6D, the second key pattern220may be formed in a shape the same as that of the second direction pattern210bof the first key pattern210along an edge of the second direction pattern210b, or as shown inFIG. 6E, the second key pattern220may be formed along only a portion of the edge of the second direction pattern210b.

As yet another modification, as shown inFIG. 6F, the second key pattern220may be formed to overlap an interior of the first key pattern210by having a width that is smaller than those of the first and second direction patterns210aand210b.

The second key pattern220is shown to have a shape the same as that of the first key pattern210, but the second key pattern220and the first key pattern210may be formed of different shapes. Particularly, in the display panel100of the present disclosure, the process key200is located in the G pixel area G-SP including the G color filter pattern133among the R, G and B pixel areas R-SP, G-SP and B-SP so that, even when the process key200is located in the active area A/A, the process key200may be better detected.

Particularly, the process key200is detected at both the upper and lower sides of the display panel100so that process efficiency may be improved. To describe in more detail, the process key200positioned in the display panel100is recognized by detecting light reflected from the process key200after light is irradiated to the process key200.

The LCD device according to the first embodiment of the present disclosure, the first key pattern210is formed of a material the same as those of the gate line103and the gate electrode111on the same layer on the first substrate101, and the second key pattern220and the black matrix131are formed of the same material on the same layer on the second substrate102, and thus, when light passes through only the transparent first substrate101, the first key pattern210made of a metal material may be detected from a lower side of the display panel100so that the first key pattern210may be recognized more definitely.

On the other hand, when the process key200is detected at an upper side of the display panel100, light irradiated from the upper side is absorbed and blocked by the R color filter pattern (not shown), the G color filter pattern133, and the B color filter pattern (not shown), such that the first key pattern210provided on the first substrate101is not detected and only the second key pattern220provided on the second substrate102is detected.

Since the second key pattern220and the black matrix131are made of the same material, a portion of the light is absorbed by the second key pattern220without being reflected, such that the second key pattern220is also not definitely recognized.

As shown in Table 1 below, it can be seen that REF., in which a color filter pattern is not provided, has 100% transmittance, while transmittance of each of the R, G and B pixel areas R-SP, G-SP and B-SP having the R color filter pattern (not shown), the G color filter pattern133, and the B color filter pattern (not shown), respectively, is lower than that of REF., in which the color filter pattern is not provided.

Meanwhile, referring to Table 1, it can be seen that a difference in transmittance occurs according to a difference in color of the color filter patterns, and the G pixel area G-SP having the G color filter pattern133has transmittance of 50% or more among the R, G and B pixel areas R-SP, G-SP and B-SP, and thus it can be seen that the transmittance of the G pixel area G-SP is much higher than those of the R and B pixel areas R-SP and B-SP having the R and B color filter patterns (not shown).

Consequently, the process key200is positioned in the G pixel area G-SP in which the G color filter pattern133is positioned so that the process key200may be detected even from the upper side of the display panel100.

Referring toFIGS. 7A to 7C, it can be confirmed that the process key200is recognizable in the B pixel area G-SP in which the G color filter pattern133is provided, as shown inFIG. 7C, when compared with the R pixel area R-SP in which the R color filter pattern (not shown) is located, as shown inFIG. 7A, and the B pixel area B-B in which the B color filter pattern (not shown) is provided, as shown inFIG. 7B.

Particularly, in the process key200according to the first embodiment of the present disclosure, the first key pattern210is made of a metal material, and the second key pattern220is made of a black matrix material to surround the first key pattern210, and thus a difference in contrast between the key pattern210and the second key pattern220may be formed to be larger, such that the process key200can be better recognized.

That is, in the process key200according to the first embodiment of the present disclosure, the difference in contrast between the first key pattern210and the second key pattern220is formed to be larger, and thus the process key200can be primarily recognized more definitely, and also the process key200is positioned in the G pixel area G-SP in which the G color filter pattern133having transmittance higher than those of the R and B color filter patterns (not shown) is positioned, such that the process key200can be secondarily recognized more definitely.

Particularly, as described above, as the recognition rate of the process key200is improved, the process key200may be definitely recognized from both the upper and lower sides of the display panel100so that process efficiency of the display panel100can also be improved. That is, as described above, the process key200is recognizable from both the upper and lower sides of the display panel100so that when the display panel100is aligned with manufacturing equipment or other objects through the process key200to perform various manufacturing processes on the display panel100, the process key200may be detected from the upper and lower sides of the display panel100as necessary so that the process efficiency can be improved.

Meanwhile, although the process key200is positioned in the active area A/A where an image is displayed, a size of the process key200is very small as compared with that of the display panel100and is positioned to correspond to only the four corners of the display panel100so that the process key200is difficult to be visually recognized by a viewer and there is no influence in displaying an image on the display panel100. As described above, in the LCD device according to the first embodiment of the present disclosure, the process key200includes the first key pattern210made of a metal material and the second key pattern220made of a black matrix material. The process key200is positioned in the G pixel area G-SP having the G color filter pattern133among the pixels P positioned at the outermost peripheries corresponding to the four corners of the active area A/A so that a narrow bezel can be implemented and the recognition rate of the process key200can also be improved.

Consequently, the display panel100may be accurately aligned with manufacturing equipment or other objects, reducing process defects and increasing efficiency. Further, the process key200is detected at both the upper and lower sides of the display panel100so that the process efficiency can be improved.

Although not shown in the drawing, in the LCD device, a dummy pixel area (not shown) in which an image is not implemented may further be positioned in the active area A/A, and the dummy pixel area (not shown) may be positioned to surround edges of the R, G and B pixel areas R-SP, G-SP and B-SP where the image is displayed in the active area A/A, may be positioned at upper and lower ends and/or left and right sides in the active area A/A, or may be positioned to correspond to one corner of the active area A/A.

The process key200according to the first embodiment of the present disclosure may be positioned in the dummy pixel area (not shown), and when the dummy pixel area (not shown) includes R, G and B color filter patterns (not shown), the process key200may also be positioned in a G dummy pixel area (not shown) in which the G color filter pattern (not shown) is positioned.

The dummy pixel area (not shown) is not occluded by an actual pattern (not shown) or a black matrix (not shown) so that while various processes are performed, the display panel100may be accurately aligned with manufacturing equipment or other objects through the process key200positioned in the dummy pixel area (not shown). Alternatively, the G color filter pattern133may be positioned above the thin film transistor T on the first substrate101, and at this point, the black matrix131may also be positioned on the second substrate102, or both the G color filter pattern133and the black matrix131may also be positioned on the first substrate101in which the thin film transistor T is provided, and even in this case, the first key pattern210of the process key200may be formed of a material the same as that of an electrode or a line constituting the thin film transistor T, and the second key pattern220of the process key200and the black matrix131may be formed of the same material.

FIG. 8is a schematic cross-sectional view illustrating an OLED device according to a second embodiment of the present disclosure.FIG. 8illustrates a G pixel area G-SP in which a G color filter pattern is provided to correspond to four corners of an active area among a plurality of pixels positioned at outermost peripheries along an edge of the active area. Further,FIG. 9is a cross-sectional view schematically illustrating another OLED device, according to the second embodiment of the present disclosure.

Generally, OLED devices are classified into a top emission type OLED device and a bottom emission type OLED device, depending on a transmission direction of emitted light. Hereinafter, an example of a top emission type OLED device according to the present disclosure is described.

For convenience of description, an area in which a drive thin film transistor DTr is formed is defined as a non-emission area NEA, and an area in which a light emitting diode E is formed is defined as an emission area EA.

As shown in the drawings, in a display panel100of the OLED device according to the second embodiment of the present disclosure, a first substrate301on which the drive thin film transistor and the light emitting diode E are formed is encapsulated by an encapsulated substrate302.

More specifically, a semiconductor layer303is positioned in the non-emission area NEA of a G pixel area G-SP on the first substrate301. The semiconductor layer303is formed of silicon and includes an active region303aconstituting a channel at a central portion of the semiconductor layer303and includes source and drain regions303band303cdoped with a high concentration of impurities and provided at both lateral surfaces of the active region303a.

A gate insulating layer305is positioned above the semiconductor layer303.

A gate electrode307corresponding to the active region303aof the semiconductor layer303and a gate line (not shown) extending in one direction are provided on the gate insulating layer305.

Further, a first interlayer insulating layer309ais positioned above the gate electrode307and the gate line (not shown). First and second semiconductor layer contact holes316in the first interlayer insulating layer309aexpose the source and drain regions303band303cthat are positioned at both lateral surfaces of the active region303a. The gate insulating layer305is provided below the first interlayer insulating layer309a.

Source and drain electrodes310aand310bare spaced apart from each other and are in contact with the source and drain regions303band303cexposed through the first and second semiconductor layer contact holes316. The source and drain electrodes310aand310bare provided on the first interlayer insulating layer309aincluding first and second semiconductor layer contact holes316. Further, a second interlayer insulating layer309bis positioned above the source and drain electrodes310aand310band the first interlayer insulating layer309aexposed between the source and drain electrodes310aand310b.

The semiconductor layer303includes the source and drain regions303band303cin contact with the source and drain electrodes310aand310b. The gate insulating layer305and the gate electrode307are positioned above the semiconductor layer303. The source and drain electrodes310aand310b, the semiconductor layer303, the insulating layer306and the gate electrode307collectively form the drive thin film transistor DTr.

Although not shown in the drawing, a data line (not shown) is provided to define the G pixel area G-SP by intersecting with the gate line (not shown). A switching thin film transistor (not shown) has a structure the same as that of the drive thin film transistor DTr and is connected to the drive thin film transistor DTr.

Further, as shown in the drawing, the switching thin film transistor (not shown) and the drive thin film transistor DTr are an example of a top gate type in which the semiconductor layer303is formed of a polysilicon semiconductor layer or an oxide semiconductor layer. As a modified example, the switching thin film transistor (not shown) and the drive thin film transistor DTr may be provided in a bottom gate type made of pure amorphous silicon or amorphous silicon doped with impurities.

Furthermore, the first and second interlayer insulating layers309aand309binclude a drain contact hole317exposing the drain electrode310b. A first electrode311connected to the drain electrode310bof the drive thin film transistor DTr and is made of, for example, a material having a relatively high work function value to constitute an anode of the light emitting diode E, is positioned above the second interlayer insulating layer309b.

The first electrode311may be formed of a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), a mixture of a metal and oxide such as ZnO:Al or SnO2:Sb, or a conductive polymer such as poly(3-methylthiophene), poly[3,4-(ethylene-1,2-dioxy)thiophene](PEDT), polypyrrole, or polyaniline. Further, the first electrode311may be formed of a carbon nanotube (CNT), a graphene, a silver nano wire, or the like.

The first electrode311is positioned on only the G pixel area G-SP, and a bank319is positioned between the first electrodes311positioned in adjacent pixel regions. That is, the first electrode311has a structure in which pixel areas are divided using the bank319as a boundary for each pixel area.

Further, an organic light emitting layer313is positioned above the first electrode311, and the organic light emitting layer313may be formed of a single layer made of a light emitting material, and alternatively, in order to increase light emitting efficiency, the organic light emitting layer313may be formed as a multilayer including a hole injection layer, a hole transport layer, an emitting material layer, an electron transport layer, and an electron injection layer.

Furthermore, a second electrode315constituting a cathode is formed on the entire organic light emitting layer313.

The second electrode315may be made of a material having a relatively low work function value. The second electrode315may have a dual-layered structure and may be configured as a single layer or a multilayer which is made of an alloy in which a first metal such as Ag or the like which is a metal material having a low work function, and a second metal such as Mg or the like are mixed with a predetermined ratio.

In the display panel100of the OLED device, when a predetermined voltage is applied to the first electrode311and the second electrode315according to a selected signal, holes injected from the first electrode311and electrons provided from the second electrode315are transported to the organic light emitting layer313to form excitons, and when the excitons transit from an excited state to a ground state, light is generated and emitted in the form of visible light. The emitted light passes through the second electrode315and exits to the outside so that the display panel100of the OLED device displays an image.

Further, a protective layer330in the form of a thin film type film is positioned above the drive thin film transistor DTr and the light emitting diode E, and the encapsulated substrate302having the color filter pattern333is provided on the protective layer330so that the OLED device is encapsulated. That is, a black matrix331is formed on the encapsulated substrate302facing the substrate301to correspond to the gate line (not shown) and the data line (not shown) of the G pixel area G-SP, which are formed on the first substrate301, and the drive thin film transistor DTr.

Accordingly, the black matrix331has an aperture corresponding to the G pixel area G-SP, and a color filter layer including B color filter patterns333, which correspond to the apertures and are sequentially and repetitively disposed, is formed.

The process key200is positioned at one side of the G pixel area G-SP. The process key200is divided into a first key pattern210positioned on the first substrate301and a second key pattern220positioned on the encapsulated substrate302and corresponding to an edge of the first key pattern210.

The first key pattern210may be made of a material the same as those of the gate line (not shown) and the gate electrode307on the same layer to reflect light, and the second key pattern220and the black matrix331may be formed of the same material on the same layer.

As described above, the process key200is divided into the first and second key patterns210and220, and particularly, the first key pattern210is formed of a metal material capable of reflecting light, and the second key pattern220and the black matrix331are formed of the same material so that it is possible to generate a large contrast difference between the first key pattern210and the second key pattern220so that a recognition rate of the process key200is increased by the contrast difference between the first key pattern210and the second key pattern220.

The first key pattern210is formed of a material the same as those of the gate line (not shown) and the gate electrode307on the same layer, and the second key pattern220and the black matrix331are formed of the same material on the same layer so that a separate process of forming the first and second key patterns210and220of the process key200is not additionally required.

Although the shape of the first key pattern210has been shown as a cross shape, the first key pattern210may be formed in various shapes such as “−,” “L,” “O,” “T,” and the like, and the second key pattern220may be formed in a shape the same as that of the first key pattern210along an edge thereof, or the second key pattern220may be formed in a closed curve shape or a closed polygonal shape surrounding the first key pattern210.

Alternatively, the second key pattern220may be integrated with the first key pattern210to have a single shape, the second key pattern220may be formed in a shape the same as that of the first key pattern210along an edge of a portion of the first key pattern210, and the second key pattern220may be formed to overlap an interior of the first key pattern210.

In yet another modification, the second key pattern220is formed in the outermost black matrix331on the encapsulated substrate302, and the black matrix331may be formed to correspond to the shape of the first key pattern210by being opened or perforated.

Particularly, in the display panel100of the OLED device according to the present disclosure, the process key200is positioned in the G pixel area G-SP including the G color filter pattern333so that even when the process key200is located in the active area A/A ofFIG. 2, the process key200can be detected more definitely.

Particularly, the process key200is detected at both the upper and lower sides of the display panel100so that process efficiency can be improved. That is, in the process key200according to the second embodiment of the present disclosure, the difference in contrast between the first key pattern210and the second key pattern220is enhanced, and thus, the process key200can be better recognized. Also, the process key200is positioned in the G pixel area G-SP in which the G color filter pattern333having transmittance higher than those of the R and B color filter patterns (not shown) is positioned, such that the process key200can further enhance the recognition. Particularly, as described above, as the recognition rate of the process key200is improved, the process key200may be definitely recognized from both the upper and lower sides of the display panel100so that process efficiency of the display panel100can also be improved.

Although the process key200is positioned in the active area A/A ofFIG. 2where an image is displayed, the size of the process key200is very small compared to that of the display panel100and is positioned to correspond to only the four corners of the display panel100so that the process key200is difficult to be visually recognized by a viewer and there is no or reduced effect in displaying an image on the display panel100.

Referring toFIG. 9, in an OLED device of a bottom emission type in which the G color filter pattern333is provided on the second interlayer insulating layer309bon the drive thin film transistor DTr, when the semiconductor layer303is formed as an oxide semiconductor layer, a light blocking layer340made of a black pigment may be further positioned below the semiconductor layer303, and a buffer layer350may be positioned between the light blocking layer340and the semiconductor layer303.

The first key pattern210of the process key200may be made of a material the same as that of the gate line (not shown) and the gate electrode307of the drive thin film transistor DTr on the same layer, and the second key pattern220may be formed of a material the same as that of the light blocking layer340positioned below the semiconductor layer303of the drive thin film transistor DTr.

As described above, in the display panel100of the OLED device according to the second embodiment of the present disclosure, the process key200is divided into the first key pattern210made of a metal material and the second key pattern220made of a material of the black matrix331, and the process key200is positioned in the G pixel area G-SP in which the G color filter pattern333is provided among the pixels P ofFIG. 3positioned at the outermost peripheries corresponding to the four corners of the active area A/A ofFIG. 2of the display panel100so that a narrow bezel may be implemented and a recognition rate of the process key200can also be improved.

Consequently, the display panel100can be accurately aligned with manufacturing equipment or other objects, such that a process defect can be minimized and process efficiency can also be improved. Further, the process key200is detected at both the upper and lower sides of the display panel100so that the process efficiency can be improved.

Although not shown in the drawing, the display panel100of the OLED device may emit R, G, or B color from the light emitting diode E positioned in each pixel area, and at this point, the color filter pattern333may be omitted.

The black matrix331may be positioned inside or outside the encapsulated substrate302, and the second key pattern220may be positioned inside or outside the encapsulated substrate302to correspond to a position of the black matrix331.

Further, both the color filter pattern333and the black matrix331may be positioned outside the encapsulated substrate302, and at this point, the second key pattern220is also positioned outside the encapsulated substrate302.

As described above, according to the present disclosure, a process key is divided into a first key pattern made of a metal material and a second key pattern made of a black matrix material. The process key is positioned in a G pixel area in which a G color filter pattern is provided among pixels positioned at outermost peripheries corresponding to four corners of an active area of a display panel so that there are effects of being capable of implementing a narrow bezel and improving a recognition rate of the process key.

Consequently, the display panel can be accurately aligned with manufacturing equipment or other objects, such that a process defect is reduced and the process efficiency is enhanced. Further, the process key can be recognized from both upper and lower sides of the display panel so that there is an effect of being capable of improving the process.

Accordingly, the embodiments disclosed herein are not intended to limit but explain the technical concept of the present disclosure, and the scope of the present disclosure should not be limited by the above embodiments.

Therefore, the above-described embodiments should be understood to be exemplary and not limiting in every aspect.

It should be understood that the scope of the present disclosure should be interpreted by the following claims and all technical concepts within the equivalent scope thereof should be interpreted as being included in the scope of the present disclosure.