LOW RESISTANCE STAIRCASE RIVET CONTACT USING METAL-TO-METAL STRAP CONNECTION

Methods, systems, and devices for low resistance staircase rivet contact using metal-to-metal strap connection are described. The described techniques provide for usage of a metallic material that adheres to a dielectric material when deposited via a chemical vapor deposition (CVD) process or atomic layer deposition (ALD) process to connect to a word line contact. For example, a strap may be formed between a layer of conductive material and a word line contact that extends at least partially through a stack of layers, and may be filled with such a metallic material. Such techniques may support a connection between the word line contact and the layer of conductive material without usage of a liner material, which may mitigate a resistance of the connection.

TECHNICAL FIELD

The following relates to one or more systems for memory, including low resistance staircase rivet contact using metal-to-metal strap connection.

BACKGROUND

Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells.

DETAILED DESCRIPTION

Memory devices may include one or more arrays of memory cells and supporting circuitry formed over a substrate for operating and accessing the memory cells. For example, a memory device may include one or more memory arrays that have multiple levels of memory cells, where a level may refer to a plane above and, in some cases, parallel to the substrate (e.g., in a horizontal direction). In some cases, such architectures may include access circuitry formed from one or more levels. For example, a stack of materials may be formed and may alternate between a dielectric material and a metallic material (e.g., used for word lines), where layers may be accessed via a contact cavity (e.g., extending through the stack of materials). In some examples, the contact cavity may be filled with a metallic material during a process step in which some of the dielectric material between the word lines or on an upper surface of the stack of materials may be exposed. The metallic material (e.g., Tungsten) may fail to adhere directly to a surface of the dielectric material (e.g., an oxide material). If the metallic material is deposited directly on the surface including the exposed portions of the dielectric material, portions of the metallic material that do not adhere to the dielectric material may cause contamination of other portions of the stack of materials. Thus a liner material (e.g., TiN) may be deposited prior to the metallic material to support the metallic material adhering to the stack of materials. However, usage of a such a liner material may result in a portion of the liner material separating the metallic material of the contact and the metallic material of the word line, which may increase a resistance between the contact and the word line.

To support mitigating resistance at a word line contact, a different metallic material (e.g., Molybdenum or other suitable metal) may be deposited to a contact cavity without depositing a liner material (e.g., due to adhering to the oxide material). In some cases, a strap may be formed at the layer associated with the contact cavity by transforming a sacrificial material to a different sacrificial material, which may support separate etching of other layers of the sacrificial material and the strap for the word line contact. For example, a first set of layers that correspond to the metallic material (e.g., layers for word line contacts) may initially be formed from a sacrificial material (e.g., SiN). In some cases, a cavity may be formed to expose a layer of the sacrificial material, and the exposed sacrificial material may be transformed to the different sacrificial material (e.g., SiCN). By transforming the exposed layer, the other layers of the sacrificial material may be etched (e.g., pulled back from the cavity) independently from the exposed layer. The exposed layer of the different sacrificial material (e.g., the strap) may then be filled with the different metallic material (e.g., Molybdenum) via the contact cavity or via a slit (e.g., used to exhume and fill the word line structures). In some cases, such techniques may support a reduced resistance between the contact material and the word line material.

Features of the disclosure are initially described in the context of memory devices and arrays with reference toFIGS.1,2,3A, and3B. Features of the disclosure are described in the context layouts with reference toFIGS.4through6. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to low resistance staircase rivet contact using metal-to-metal strap connection as described with reference toFIGS.7and8.

FIG.1shows an example of a memory device100that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with examples as disclosed herein. In some examples, the memory device100may be referred to as or include a memory die, a memory chip, or an electronic memory apparatus. The memory device100may be operable to provide locations to store information (e.g., physical memory addresses) that may be used by a system (e.g., a host device coupled with the memory device100, for writing information, for reading information).

The memory device100may include one or more memory cells105that each may be programmable to store different logic states (e.g., a programmed one of a set of two or more possible states). For example, a memory cell105may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell105(e.g., a multi-level memory cell105) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells105may be arranged in an array.

A memory cell105may store a logic state using a configurable material, which may be referred to as a memory element, a storage element, a memory storage element, a material element, a material memory element, a material portion, or a polarity-written material portion, among others. A configurable material of a memory cell105may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase change memory cell, a thresholding memory cell, or a self-selecting memory cell, among other architectures.

In some examples, the material of a memory cell105may include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG-alloy. In some examples, a SAG-alloy may also include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some examples, SAG-alloy may include silicon (Si) or indium (In) or a combination thereof and such chalcogenide materials may be referred to as SiSAG-alloy or InSAG-alloy, respectively, or a combination thereof. In some examples, the chalcogenide material may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms.

In some examples, a memory cell105may be an example of a phase change memory cell. In such examples, the material used in the memory cell105may be based on an alloy (such as the alloys listed above) and may be operated so as to change to different physical state (e.g., undergo a phase change) during normal operation of the memory cell105. For example, a phase change memory cell105may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). A relatively disordered atomic configuration may correspond to a first logic state (e.g., a RESET state, a logic 0) and a relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different than the first logic state, a SET state, a logic 1).

In some examples (e.g., for thresholding memory cells105, for self-selecting memory cells105), some or all of the set of logic states supported by the memory cells105may be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., the material in an amorphous state may be operable to store different logic states). In some examples, the storage element of a memory cell105may be an example of a self-selecting storage element. In such examples, the material used in the memory cell105may be based on an alloy (e.g., such as the alloys listed above) and may be operated so as to undergo a change to a different physical state during normal operation of the memory cell105. For example, a self-selecting or thresholding memory cell105may have a high threshold voltage state and a low threshold voltage state. A high threshold voltage state may correspond to a first logic state (e.g., a RESET state, a logic 0) and a low threshold voltage state may correspond to a second logic state (e.g., a logic state different than the first logic state, a SET state, a logic 1).

During a write operation (e.g., a programming operation) of a self-selecting or thresholding memory cell105, a polarity used for a write operation may influence (e.g., determine, set, program) a behavior or characteristic of the material of the memory cell105, such as a thresholding characteristic (e.g., a threshold voltage) of the material. A difference between thresholding characteristics of the material of the memory cell105for different logic states stored by the material of the memory cell105(e.g., a difference between threshold voltages when the material is storing a logic state ‘0’ versus a logic state ‘1’) may correspond to the read window of the memory cell105.

The memory device100may include access lines (e.g., row lines115each extending along an illustrative x-direction, column lines125each extending along an illustrative y-direction) arranged in a pattern, such as a grid-like pattern. Access lines may be formed with one or more conductive materials. In some examples, row lines115, or some portion thereof, may be referred to as word lines. In some examples, column lines125, or some portion thereof, may be referred to as digit lines or bit lines. References to access lines, or their analogues, are interchangeable without loss of understanding. Memory cells105may be positioned at intersections of access lines, such as row lines115and the column lines125. In some examples, memory cells105may also be arranged (e.g., addressed) along an illustrative z-direction, such as in an implementation of sets of memory cells105being located at different levels (e.g., layers, decks, planes, tiers) along the illustrative z-direction. In some examples, a memory device100that includes memory cells105at different levels may be supported by a different configuration of access lines, decoders, and other supporting circuitry than shown.

Operations such as read operations and write operations may be performed on the memory cells105by activating access lines such as one or more of a row line115or a column line125, among other access lines associated with alternative configurations. For example, by activating a row line115and a column line125(e.g., applying a voltage to the row line115or the column line125), a memory cell105may be accessed in accordance with their intersection. An intersection of a row line115and a column line125, among other access lines, in various two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell105. In some examples, an access line may be a conductive line coupled with a memory cell105and may be used to perform access operations on the memory cell105. In some examples, the memory device100may perform operations responsive to commands, which may be issued by a host device coupled with the memory device100or may be generated by the memory device100(e.g., by a local memory controller150).

Accessing the memory cells105may be controlled through one or more decoders, such as a row decoder110or a column decoder120, among other examples. For example, a row decoder110may receive a row address from the local memory controller150and activate a row line115based on the received row address. A column decoder120may receive a column address from the local memory controller150and may activate a column line125based on the received column address.

The sense component130may be operable to detect a state (e.g., a material state, a resistance state, a threshold state) of a memory cell105and determine a logic state of the memory cell105based on the detected state. The sense component130may include one or more sense amplifiers to convert (e.g., amplify) a signal resulting from accessing the memory cell105(e.g., a signal of a column line125or other access line). The sense component130may compare a signal detected from the memory cell105to a reference135(e.g., a reference voltage, a reference charge, a reference current). The detected logic state of the memory cell105may be provided as an output of the sense component130(e.g., to an input/output component140), and may indicate the detected logic state to another component of the memory device100or to a host device coupled with the memory device100.

The local memory controller150may control the accessing of memory cells105through the various components (e.g., a row decoder110, a column decoder120, a sense component130, among other components). In some examples, one or more of a row decoder110, a column decoder120, and a sense component130may be co-located with the local memory controller150. The local memory controller150may be operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with the memory device100), translate the information into a signaling that can be used by the memory device100, perform one or more operations on the memory cells105and communicate data from the memory device100to a host device based on performing the one or more operations. The local memory controller150may generate row address signals and column address signals to activate access lines such as a target row line115and a target column line125. The local memory controller150also may generate and control various signals (e.g., voltages, currents) used during the operation of the memory device100. In general, the amplitude, the shape, or the duration of an applied signal discussed herein may be varied and may be different for the various operations discussed in operating the memory device100.

The local memory controller150may be operable to perform one or more access operations on one or more memory cells105of the memory device100. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller150in response to access commands (e.g., from a host device). The local memory controller150may be operable to perform other access operations not listed here or other operations related to the operating of the memory device100that are not directly related to accessing the memory cells105.

In some cases, access operations for one or more memory cells105may be performed via a word line contact, which may extend through a stack of materials to contact one or more word lines. For example, the stack of materials may include a staircase structure where each step of the staircase corresponds to a respective layer of conductive material and a respective contact opening. In some cases, a connection between the contact opening and the layer of conductive material may be achieved by depositing a metallic material that extends between the layer and the contact opening. However, the metallic material may be deposited on top of a dielectric material, and some metallic materials (e.g., Tungsten) may flake or otherwise fail to adhere to the dielectric material. In such cases, a liner material may be deposited in between the metallic material and the dielectric material, which may increase a resistance between the metallic material of the contact opening and the layer of conductive material.

To support a low resistance connection between the metallic material of a contact opening and a layer of conductive material, a metallic material that adheres to the dielectric material without usage of a liner material may be used. For example, a strap extending between the contact opening and the conductive layer may be filled with such a metallic material, which may be Molybdenum, or other metallic material that adheres to the dielectric material when deposited via a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

In addition to applicability in memory systems as described herein, techniques for low resistance staircase rivet contact using metal-to-metal strap connection may be generally implemented to improve the performance (including gaming) of various electronic devices and systems. Some electronic device applications, including gaming and other high-performance applications, may be associated with relatively high processing requirements while also benefitting from relatively quick response times to improve user experience. As such, increasing processing speed, decreasing response times, or otherwise improving the performance electronic devices may be desirable. Implementing the techniques described herein may improve the performance of electronic devices by improving a density of memory arrays, which may improve computing power and efficiency, among other benefits.

The memory device100may include any quantity of non-transitory computer readable media that support low resistance staircase rivet contact using metal-to-metal strap connection. For example, a local memory controller150, a row decoder110, a column decoder120, a sense component130, or an input/output component140, or any combination thereof may include or may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the memory device100. For example, such instructions, if executed by the memory device100, may cause the memory device100to perform one or more associated functions as described herein.

FIGS.2,3A, and3Bshow an example of a memory array200that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with examples as disclosed herein. The memory array200may be included in a memory device100, and illustrates an example of a three-dimensional arrangement of memory cells105that may be accessed by various conductive structures (e.g., access lines).FIG.2illustrates a top section view (e.g., SECTION A-A) of the memory array200relative to a cut plane A-A as shown inFIGS.3A and3B.FIG.3Aillustrates a side section view (e.g., SECTION B-B) of the memory array200relative to a cut plane B-B as shown inFIG.2.FIG.3Billustrates a side section view (e.g., SECTION C-C) of the memory array200relative to a cut plane C-C as shown inFIG.2. The section views may be examples of cross-sectional views of the memory array200with some aspects (e.g., dielectric structures) removed for clarity. Elements of the memory array200may be described relative to an x-direction, a y-direction, and a z-direction, as illustrated in each ofFIGS.2,3A, and3B. Although some elements included inFIGS.2,3A, and3Bare labeled with a numeric indicator, other corresponding elements are not labeled, although they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features. Further, although some quantities of repeated elements are shown in the illustrative example of memory array200, techniques in accordance with examples as described herein may be applicable to any quantity of such elements, or ratios of quantities between one repeated element and another.

In the example of memory array200, memory cells105and word lines205may be distributed along the z-direction according to levels230(e.g., decks, layers, planes, tiers, as illustrated inFIGS.3A and3B). In some examples, the z-direction may be orthogonal to a surface of a substrate (not shown) of the memory array200, which may be below the illustrated structures along the z-direction. Although the illustrative example of memory array200includes four levels230, a memory array200in accordance with examples as disclosed herein may include any quantity of one or more levels230(e.g., 64 levels, 128 levels) along the z-direction.

Each word line205may be an example of a portion of an access line that is formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, a word line205may be formed in a comb structure, including portions (e.g., projections, tines) extending along the y-direction through gaps (e.g., alternating gaps) between pillars220. For example, as illustrated, the memory array200may include two word lines205per level230(e.g., according to odd word lines205-a-n1and even word lines205-a-n2for a given level, n), where such word lines205of the same level230may be described as being interleaved (e.g., with portions of an odd word line205-a-n1projecting along the y-direction between portions of an even word line205-a-n2, and vice versa). In some examples, an odd word line205(e.g., of a level230) may be associated with a first memory cell105on a first side (e.g., along the x-direction) of a given pillar220and an even word line (e.g., of the same level230) may be associated with a second memory cell105on a second side (e.g., along the x-direction, opposite the first memory cell105) of the given pillar220. Thus, in some examples, memory cells105of a given level230may be addressed (e.g., selected, activated) in accordance with an even word line205or an odd word line205.

Each pillar220may be an example of a portion of an access line (e.g., a conductive pillar portion) that is formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, the pillars220may be arranged in a two-dimensional array (e.g., in an xy-plane) having a first quantity of pillars220along a first direction (e.g., eight pillars along the x-direction, eight rows of pillars), and having a second quantity of pillars220along a second direction (e.g., five pillars along the y-direction, five columns of pillars). Although the illustrative example of memory array200includes a two-dimensional arrangement of eight pillars220along the x-direction and five pillars220along the y-direction, a memory array200in accordance with examples as disclosed herein may include any quantity of pillars220along the x-direction and any quantity of pillars220along the y-direction. Further, as illustrated, each pillar220may be coupled with a respective set of memory cells105(e.g., along the z-direction, one or more memory cells105for each level230). A pillar220may have a cross-sectional area in an xy-plane that extends along the z-direction. Although illustrated with a circular cross-sectional area in the xy-plane, a pillar220may be formed with a different shape, such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in an xy-plane.

The memory cells105each may include a chalcogenide material. In some examples, the memory cells105may be examples of thresholding memory cells. Each memory cell105may be accessed (e.g., addressed, selected) according to an intersection between a word line205(e.g., a level selection, which may include an even or odd selection within a level230) and a pillar220. For example, as illustrated, a selected memory cell105-aof the level230-a-3may be accessed according to an intersection between the pillar220-a-43and the word line205-a-32.

A memory cell105may be accessed (e.g., written to, read from) by applying an access bias (e.g., an access voltage, Vaccess, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, an access bias may be applied by biasing a selected word line205with a first voltage (e.g., Vaccess/2) and by biasing a selected pillar220with a second voltage (e.g., −Vaccess/2), which may have an opposite sign relative to the first voltage. Regarding the selected memory cell105-a, a corresponding access bias (e.g., the first voltage) may be applied to the word line205-a-32, while other unselected word lines205may be grounded (e.g., biased to 0V). In some examples, a word line bias may be provided by a word line driver (not shown) coupled with one or more of the word lines205.

To apply a corresponding access bias (e.g., the second voltage) to a pillar220, the pillars220may be configured to be selectively coupled with a sense line215(e.g., a digit line, a column line, an access line extending along the y-direction) via a respective transistor225coupled between (e.g., physically, electrically) the pillar220and the sense line215. In some examples, the transistors225may be vertical transistors (e.g., transistors having a channel along the z-direction, transistors having a semiconductor junction along the z-direction), which may be formed above the substrate of the memory array200using various techniques (e.g., thin film techniques). In some examples, a selected pillar220, a selected sense line215, or a combination thereof may be an example of a selected column line125described with reference toFIG.1(e.g., a bit line).

The transistors225(e.g., a channel portion of the transistors225) may be activated by gate lines210(e.g., activation lines, selection lines, a row line, an access line extending along the x-direction) coupled with respective gates of a set of the transistors225(e.g., a set along the x-direction). In other words, each of the pillars220may have a first end (e.g., towards the negative z-direction, a bottom end) configured for coupling with an access line (e.g., a sense line215). In some examples, the gate lines210, the transistors225, or both may be considered to be components of a column decoder120(e.g., as pillar decoder components). In some examples, the selection of (e.g., biasing of) pillars220, or sense lines215, or various combinations thereof, may be supported by a column decoder120, or a sense component130, or both.

To apply the corresponding access bias (e.g., −Vaccess/2) to the pillar220-a-43, the sense line215-a-4may be biased with the access bias, and the gate line210-a-3may be grounded (e.g., biased to 0V) or otherwise biased with an activation voltage. In an example where the transistors225are n-type transistors, the gate line210-a-3being biased with a voltage that is relatively higher than the sense line215-a-4may activate the transistor225-a(e.g., cause the transistor225-ato operate in a conducting state), thereby coupling the pillar220-a-43with the sense line215-a-4and biasing the pillar220-a-43with the associated access bias. However, the transistors225may include different channel types, or may be operated in accordance with different biasing schemes, to support various access operations.

In some examples, unselected pillars220of the memory array200may be electrically floating when the transistor225-ais activated, or may be coupled with another voltage source (e.g., grounded, via a high-resistance path, via a leakage path) to avoid a voltage drift of the pillars220. For example, a ground voltage being applied to the gate line210-a-3may not activate other transistors coupled with the gate line210-a-3, because the ground voltage of the gate line210-a-3may not be greater than the voltage of the other sense lines215(e.g., which may be biased with a ground voltage or may be floating). Further, other unselected gate lines210, including gate line210-a-5as shown inFIG.3A, may be biased with a voltage equal to or similar to an access bias (e.g., −Vaccess/2, or some other negative bias or bias relatively near the access bias voltage), such that transistors225along an unselected gate line210are not activated. Thus, the transistor225-bcoupled with the gate line210-a-5may be deactivated (e.g., operating in a non-conductive state), thereby isolating the voltage of the sense line215-a-4from the pillar220-a-45, among other pillars220.

In a write operation, a memory cell105may be written to by applying a write bias (e.g., where Vaccess=Vwrite, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, a polarity of a write bias may influence (e.g., determine, set, program) a behavior or characteristic of the material of the memory cell105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity may set the material of the memory cell105with a first threshold voltage, which may be associated with storing a logic 0. Further, applying a write bias with a second polarity (e.g., opposite the first polarity) may set the material of the memory cell with a second threshold voltage, which may be associated with storing a logic 1. A difference between threshold voltages of the material of the memory cell105for different logic states stored by the material of the memory cell105(e.g., a difference between threshold voltages when the material is storing a logic state ‘0’ versus a logic state ‘1’) may correspond to the read window of the memory cell105.

In a read operation, a memory cell105may be read from by applying a read bias (e.g., where Vaccess=Vread, which may be a positive voltage or a negative voltage) across the memory cell105. In some examples, a logic state of the memory cell105may be evaluated based on whether the memory cell105thresholds in the presence of the applied read bias. For example, such a read bias may cause a memory cell105storing a first logic state (e.g., a logic 0) to threshold (e.g., permit a current flow, permit a current above a threshold current), and may not cause a memory cell105storing a second logic state (e.g., a logic 1) to threshold (e.g., may not permit a current flow, may permit a current below a threshold current).

In some examples, such techniques may be extended to a memory architecture supporting NAND memory cells. For example, the memory cells105may be connected in a 3D NAND configuration. In such an example, a pillar220may be an example of a string of the memory cells105, where multiple strings may form a block of memory cells105(e.g., a collection of pages of the memory cells105). In some examples, each string may include a set of memory cells105connected in series (e.g., along the z-direction, in which a drain of one memory cell105in the string may be coupled with a source of another memory cell105in the string). Each memory cell105in a string may be associated with a different word line205, such that a quantity of word lines205in the memory architecture may be equal to the quantity of memory cells105in a string. Accordingly, a string may include memory cells105from multiple pages, and a page may include memory cells105from multiple strings.

In some cases, access operations for one or more memory cells105may be performed via a word line contact, which may extend through a stack of materials to contact one or more word line gates. For example, the stack of materials may include a staircase structure where each step of the staircase corresponds to a respective layer of conductive material and a respective contact opening. In some cases, the contact opening may be filled with a metallic material during a process step in which some of the dielectric material between the word lines or on an upper surface of the stack of materials may be exposed. In some cases, a connection between the contact opening and the layer of conductive material may be achieved by depositing a metallic material that extends between the layer the contact opening. However, the metallic material may be deposited on top of a dielectric material, and some metallic materials (e.g., Tungsten) may flake or otherwise fail to directly adhere to the dielectric material. If the metallic material is deposited directly on the surface including the exposed portions of the dielectric material, portions of the metallic material that do not adhere to the dielectric material may cause contamination of other portions of the stack of materials. In such cases, a liner material may be deposited in between the metallic material and the dielectric material, which may increase a resistance between the metallic material of the contact opening and the layer of conductive material.

To support a low resistance connection between the metallic material of a contact opening and a layer of conductive material, a metallic material that adheres to the dielectric material without usage of a liner material may be used. For example, a strap extending between the contact opening and the conductive layer may be filled with such a metallic material, which may be Molybdenum, or other metallic material that adheres to the dielectric material when deposited via a CVD process or an ALD process.

FIG.4shows an example of a layout400that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with various aspects of the present disclosure. The layout400may illustrate an example of a first set of manufacturing operations for a memory device that supports a metal-to-metal strap connection at a word line contact as described herein. In some cases, the layout400may include one or more layers of a metallic material405(e.g., layers forming word lines205as described with reference toFIGS.2,3A, and3B), one or more layers of a dielectric material410, a top layer of a dielectric material415, a dielectric fill420(e.g., a same or different material as the dielectric material415and the dielectric material410), one or more staircase contact pads425, a sacrificial material430corresponding to one or more straps for word line contacts, or any combination thereof. It should be noted that the layout400may support any quantity of layers, any type of material, and various patterns of the materials, among other examples. The layout400may include a cross section view of a memory device associated with the first set of manufacturing operations.

In some examples, the first set of manufacturing operations may include forming a stack of materials including multiple layers. The multiple layers may alternate between a first material (e.g., the dielectric material410) and a second material (e.g., a first sacrificial material, which may be a dielectric material). In some cases, a staircase structure may be formed by cutting a cavity (e.g., a first cavity) into the stack of materials to a layer that is being contacted. For example, a first step435-aof the staircase may be formed by cutting a cavity that extends to a layer440-aof the stack of materials and a second step435-bof the staircase may be formed by cutting a cavity that extends to a layer440-bof the stack of materials. In some cases, the cavities formed for each step435may expose a portion of the corresponding layer440(e.g., a layer of the first sacrificial material). It should be noted that while the layout400illustrates two steps of the staircase structure, any quantity of steps may be formed for any quantity of corresponding layers.

In some cases, the first set of manufacturing operations may include transforming the exposed layer of the first sacrificial material to a different sacrificial material via first cavity. For example, an operation may be performed on the exposed layer to transform the first sacrificial material of the exposed layer to a second sacrificial material, which may be the sacrificial material430. For example, the exposed layer of the first sacrificial (e.g., SiN) material may be implanted (e.g., with carbon) to form the second sacrificial material (e.g., SiCN) within the portion of a layer440exposed by the cavity. In some cases, the first sacrificial material and the second sacrificial material may be etched using different chemistries (e.g., selectively etched). In some cases, the cavity may be filled with the dielectric fill420subsequent to transforming the exposed layer to the second sacrificial material (e.g., the sacrificial material430).

In some cases, the first set of manufacturing operations may include cutting a second cavity at least partially within the filled first cavity to form a cavity445(e.g., a second cavity for forming a word line contact for each step435). For example, a cavity445-amay be formed for the step435-aand a cavity445-bmay be formed for the step435-b. In some examples, a cavity445may extend to the exposed layer of the corresponding step435(e.g., a top down contact). For example, the cavity445-amay extend to the layer440-aand the cavity445-bmay extend to the layer440-b(e.g., terminating at the exposed layer).

In some other examples, the cavity445may extend through the stack to a corresponding staircase contact pad425(e.g., a rivet contact). In such an example, an additional etching step (e.g., subsequent to forming the second cavity) may be performed to pull back one or more layers of the first sacrificial material that extend to the cavity445. As an example, for the step435-a, one or more layers of the first sacrificial material that are below the layer440-amay be etched to create cavities between the one or more layers and the cavity445-a(e.g., to prevent the one or more layers from contacting the word line contact). In some cases, the cavities formed between the one or more layers and the cavity445may be filled with a dielectric material, which may be the dielectric material410(e.g., the first material of the alternating layers).

In some examples, the first set of manufacturing instructions may include forming a slit (e.g., a third cavity) to support exhuming the first sacrificial material from the stack of materials. For example, the slit may be formed in a location that is exclusive of the first cavity and the second cavity (e.g., in a space between steps435) and may be cut in a plane that is parallel or orthogonal to the cross section illustrated by the layout400.

In some examples, the first set of manufacturing instructions may include exhuming, via the slit, the first sacrificial material from the stack of materials. For example, the first sacrificial material may be exhumed to form voids corresponding to the layers of the first sacrificial material. In some cases, the second sacrificial material (e.g., associated with the contact strap) may not be exhumed with the first sacrificial material (e.g., due to having a different etch chemistry).

In some examples, the first set of manufacturing instructions may include depositing, via the slit, the metallic material405within the voids corresponding to the layers of the first sacrificial material. For example, the metallic material405may be deposited to create word lines between the layers of the dielectric material410. Such operations may result in an arrangement of materials as illustrated in the layout400.

FIG.5shows an example of a layout500that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with various aspects of the present disclosure. The layout500may illustrate an example of a second set of manufacturing operations for a memory device that supports a metal-to-metal strap connection at a word line contact as described herein. In some cases, the second set of manufacturing operations may follow the first set of manufacturing operations described with reference toFIG.4(e.g., applying the second set of manufacturing operations to the layout400may result in the layout500). The layout500may include one or more aspects of the layout400, such as one or more layers of the metallic material405, one or more layers of the dielectric material410, a top layer of the dielectric material415, the dielectric fill420(e.g., a same or different material as the dielectric material415and the dielectric material410), the staircase contact pad425, or any combination thereof. It should be noted that the layout500may support any quantity of layers, any type of material, and various patterns of the materials, among other examples. The layout500may include a cross section view of a memory device associated with the second set of manufacturing operations.

The layout500may support a staircase structure for a memory device, which may include the one or more steps435associated with the one or more layers of the metallic material405, as described with reference toFIG.4. For example, the step435-amay be associated with the layer440-aand the step435-bmay be associated with the layer440-b. In some cases, the cavity445-aand the cavity445-bmay be cut at least partially within the step435-aand the step435-b, respectively, and may extend through the stack and terminate at a staircase contact pad425(e.g., a rivet) or may extend to the corresponding layer440(e.g., a top down contact), which may be included in the first set of manufacturing instructions as described with reference toFIG.4.

In some cases, the second set of manufacturing instructions may include exhuming a sacrificial material (e.g., the sacrificial material430described with reference toFIG.4) from one or more exposed layers. For example, a portion of the layer440-athat overlaps with the step435-amay include the sacrificial material, which may be a second sacrificial material (e.g., SiCN) that is a transformed from a first sacrificial material (e.g., SiN) via implantation (e.g., implanting carbon). In some cases, the first sacrificial material and the second sacrificial material may have different etch chemistries, and may be etched separately. For example, the one or more layers of the metallic material405may initially be filled with the first sacrificial material, and may be exhumed separately from the exposed layer of the second sacrificial material. In some cases, the first sacrificial material may be exhumed via a slit, which may be formed in a location that is exclusive of the step cavity and the contact cavity (e.g., in a space between steps435) and may be cut in a plane that is parallel or orthogonal to the cross section illustrated by the layout500.

In some cases, the second sacrificial material may be exhumed to form a void that connects to a corresponding cavity445(e.g., a cavity505-aand a cavity505-b). For example, the second sacrificial material may be exhumed via a corresponding cavity445(e.g., as illustrated in the layout500) to form the cavity505-aand the cavity505-b. As another example, the second sacrificial material may be exhumed via the slit and may be exhumed prior to depositing the metallic material505(e.g., and after exhuming the first sacrificial material via the slit). For example, after exhuming the first sacrificial material from the layer440-aand prior to depositing the metallic material405in the layer440-a, the second sacrificial material may be exhumed and the metallic material405may be deposited in the exposed portion of the layer440-a(e.g., extending to the cavity445-aon either side).

FIG.6shows an example of a layout600that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with various aspects of the present disclosure. The layout600may illustrate an example of a third set of manufacturing operations for a memory device that supports a metal-to-metal strap connection at a word line contact as described herein. In some cases, the third set of manufacturing operations may follow the second set of manufacturing operations described with reference toFIG.5(e.g., applying the third set of manufacturing operations to the layout500may result in the layout600). The layout600may include one or more aspects of the layouts400and500, such as one or more layers of the metallic material405(e.g., a first metallic material), one or more layers of the dielectric material410, a top layer of the dielectric material415, the dielectric fill420(e.g., a same or different material as the dielectric material415and the dielectric material410), the staircase contact pads425, or any combination thereof, which may be examples of corresponding aspects described with reference toFIGS.4and5. Additionally, the layout600may include a metallic material605(e.g., a second metallic material), a metallic material610(e.g., a third metallic material), a liner material615, or any combination thereof. It should be noted that the layout600may support any quantity of layers, any type of material, and various patterns of the materials, among other examples. The layout600may include a cross section view of a memory device associated with the third set of manufacturing operations.

In some cases, the third set of manufacturing operations may include depositing the metallic material605to form one or more contacts620. For example, the metallic material605may be deposited in cavities (e.g., the cavities445described with reference toFIGS.4and5) corresponding to a contact620-aand a contact620-b, and may be deposited using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some cases, the contacts620may extend through the stack and terminate at a corresponding staircase contact pad425(e.g., a rivet contact). In some other cases, the contacts620may extend through the stack and terminate at a corresponding layer425(e.g., a top down contact).

The metallic material605may be an example of a metallic material that can adhere to a dielectric material (e.g., an oxide material such as the dielectric material410) using the CVD process or the ALD process. By way of example, some metallic materials (e.g., Tungsten) may flake or otherwise fail to adhere to the dielectric material410when deposited in contact with the dielectric material410. In such examples, a liner material (e.g., TiN) may be deposited in between the metallic material and the dielectric material410. However, such techniques may result in a greater resistance between the contact620and a corresponding layer440(e.g., due to the liner separating the direct connection). To support a reduced resistance between the contact620and the corresponding layer440, the metallic material605may be chosen such that the metallic material605adheres to the dielectric material410using a CVD process or ALD process. For example, the metallic material605may be Molybdenum (e.g., or any other metallic material that can be deposited using a CVD process or an ALD process and adheres to the dielectric material410without usage of a resistive liner).

In some cases, the metallic material605may directly contact the metallic material405(e.g., to form a word line contact between a contact620and a corresponding layer440). For instance, the third set of manufacturing instructions may include filling the portion of a layer440that is exposed by a step cavity (e.g., a strap of the layer440spanning the width of the cavity for a step435) using various techniques. In one example, as illustrated in the layout600, the strap may be filled with the metallic material605. For example, as part of depositing the metallic material605to form the contact620-aand the contact620-b, the metallic material605may be deposited in the respective straps (e.g., extending to contact the metallic material405of the layer440-aand the layer440-b). As another example, the strap may be filled with the metallic material405. For example, as part of depositing the metallic material405via the slit (e.g., after exhuming the second sacrificial material via the slit as described with reference toFIG.5), the metallic material405may be deposited in the strap of the layers440(e.g., extending to the corresponding contact620). Such techniques (e.g., filling the strap with the metallic material405or the metallic material605) may mitigate a resistance between each contact620and a corresponding layer440.

In some examples, the contacts620may be filled with the metallic material605(e.g., without another material present in the contacts655). Additionally, or alternatively, the contacts620may be filled with the metallic material610(e.g., a plug of the metallic material610that is surrounded by the metallic material605), as illustrated in the layout600. For example, after depositing the metallic material605into the contacts620(e.g., covering the surface of the contacts620), the metallic material610may be deposited in the contacts620within the remaining space of the contacts620. In some cases, a liner material615may be deposited in the contacts620and may be located in between the metallic material605and the metallic material610, as illustrated in the layout600. For example, the liner material615(e.g., TiN) may be deposited after depositing the metallic material605and prior to depositing the metallic material610, and may support a low-resistance contact (e.g., due to a relatively large surface area of the liner material615).

FIG.7shows a block diagram700of a manufacturing system720that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with examples as disclosed herein. The manufacturing system720may be an example of aspects of a manufacturing system as described with reference toFIGS.1through6. The manufacturing system720, or various components thereof, may be an example of means for performing various aspects of low resistance staircase rivet contact using metal-to-metal strap connection as described herein. For example, the manufacturing system720may include a stack formation component725, a cavity formation component730, a material deposition component735, a material exhuming component740, an implantation component745, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The stack formation component725may be configured as or otherwise support a means for forming, on a substrate, a stack of materials including a plurality of layers, the plurality of layers alternating between a first material and a second material, where the first material is a first dielectric material. The cavity formation component730may be configured as or otherwise support a means for forming a first cavity in the stack of materials, where a bottom of the first cavity exposes a layer of the plurality of layers of the second material. The material deposition component735may be configured as or otherwise support a means for filling the first cavity with a second dielectric material. In some examples, the cavity formation component730may be configured as or otherwise support a means for forming a second cavity in the stack of materials, the second cavity at least partially within the filled first cavity. In some examples, the cavity formation component730may be configured as or otherwise support a means for forming a third cavity in the stack of materials, the third cavity exclusive of the first cavity and the second cavity. The material exhuming component740may be configured as or otherwise support a means for exhuming, via the third cavity, the second material of the plurality of layers to form voids corresponding to the second material. In some examples, the material deposition component735may be configured as or otherwise support a means for depositing, via the third cavity, a first metallic material within the voids of the plurality of layers. In some examples, the material deposition component735may be configured as or otherwise support a means for depositing, via the second cavity, a second metallic material, where the second metallic material is in contact with the first metallic material and is deposited using a chemical vapor deposition process or an atomic layer deposition process.

In some examples, the implantation component745may be configured as or otherwise support a means for transforming the exposed layer of the plurality of layers from the second material to a third material prior to forming the second cavity.

In some examples, the material exhuming component740may be configured as or otherwise support a means for exhuming, via the third cavity, the third material of the exposed layer prior to depositing the first metallic material within the voids of the plurality of layers, where depositing the first metallic material via the third cavity includes depositing the first metallic material within a void formed by exhuming the third material of the exposed layer.

In some examples, the material exhuming component740may be configured as or otherwise support a means for exhuming, via the second cavity, the third material of the exposed layer, where depositing the second metallic material via the second cavity includes depositing the second metallic material within a void formed by exhuming the third material of the exposed layer.

In some examples, the material deposition component735may be configured as or otherwise support a means for filling the second cavity with a third metallic material.

In some examples, the material deposition component735may be configured as or otherwise support a means for depositing a fourth material in the second cavity prior to filling the second cavity with the third metallic material, where the fourth material is in between the second metallic material and the third metallic material.

In some examples, the second metallic material includes Molybdenum.

FIG.8shows a flowchart illustrating a method800that supports low resistance staircase rivet contact using metal-to-metal strap connection in accordance with examples as disclosed herein. The operations of method800may be implemented by a manufacturing system or its components as described herein. For example, the operations of method800may be performed by a manufacturing system as described with reference toFIGS.1through7. In some examples, a manufacturing system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the wireless manufacturing system may perform aspects of the described functions using special-purpose hardware.

At805, the method may include forming, on a substrate, a stack of materials including a plurality of layers, the plurality of layers alternating between a first material and a second material, where the first material is a first dielectric material. The operations of805may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of805may be performed by a stack formation component725as described with reference toFIG.7.

At810, the method may include forming a first cavity in the stack of materials, where a bottom of the first cavity exposes a layer of the plurality of layers of the second material. The operations of810may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of810may be performed by a cavity formation component730as described with reference toFIG.7.

At815, the method may include filling the first cavity with a second dielectric material. The operations of815may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of815may be performed by a material deposition component735as described with reference toFIG.7.

At820, the method may include forming a second cavity in the stack of materials, the second cavity at least partially within the filled first cavity. The operations of820may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of820may be performed by a cavity formation component730as described with reference toFIG.7.

At825, the method may include forming a third cavity in the stack of materials, the third cavity exclusive of the first cavity and the second cavity. The operations of825may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of825may be performed by a cavity formation component730as described with reference toFIG.7.

At830, the method may include exhuming, via the third cavity, the second material of the plurality of layers to form voids corresponding to the second material. The operations of830may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of830may be performed by a material exhuming component740as described with reference toFIG.7.

At835, the method may include depositing, via the third cavity, a first metallic material within the voids of the plurality of layers. The operations of835may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of835may be performed by a material deposition component735as described with reference toFIG.7.

At840, the method may include depositing, via the second cavity, a second metallic material, where the second metallic material is in contact with the first metallic material and is deposited using a chemical vapor deposition process or an atomic layer deposition process. The operations of840may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of840may be performed by a material deposition component735as described with reference toFIG.7.

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming, on a substrate, a stack of materials including a plurality of layers, the plurality of layers alternating between a first material and a second material, where the first material is a first dielectric material; forming a first cavity in the stack of materials, where a bottom of the first cavity exposes a layer of the plurality of layers of the second material; filling the first cavity with a second dielectric material; forming a second cavity in the stack of materials, the second cavity at least partially within the filled first cavity; forming a third cavity in the stack of materials, the third cavity exclusive of the first cavity and the second cavity; exhuming, via the third cavity, the second material of the plurality of layers to form voids corresponding to the second material; depositing, via the third cavity, a first metallic material within the voids of the plurality of layers; and depositing, via the second cavity, a second metallic material, where the second metallic material is in contact with the first metallic material and is deposited using a chemical vapor deposition process or an atomic layer deposition process.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for transforming the exposed layer of the plurality of layers from the second material to a third material prior to forming the second cavity.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for exhuming, via the third cavity, the third material of the exposed layer prior to depositing the first metallic material within the voids of the plurality of layers, where depositing the first metallic material via the third cavity includes depositing the first metallic material within a void formed by exhuming the third material of the exposed layer.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 2 through 3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for exhuming, via the second cavity, the third material of the exposed layer, where depositing the second metallic material via the second cavity includes depositing the second metallic material within a void formed by exhuming the third material of the exposed layer.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for filling the second cavity with a third metallic material.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a fourth material in the second cavity prior to filling the second cavity with the third metallic material, where the fourth material is in between the second metallic material and the third metallic material.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6, where the second metallic material includes Molybdenum.

Aspect 8: An apparatus, including: a stack of materials including a plurality of layers, the plurality of layers alternating between a first material and a second material, the second material including a first metallic material, the stack of materials including a cavity at least partially filled with a third material, where a bottom of the cavity is in contact with a layer of the plurality of layers of the second material; and a contact extending at least partially through the stack of materials and at least partially within the filled cavity, the contact including a second metallic material that is in contact with the first metallic material of the layer of the plurality of layers.

Aspect 9: The apparatus of aspect 8, where the contact is lined with the second metallic material.

Aspect 10: The apparatus of aspect 9, where the contact is at least partially filled with a third metallic material.

Aspect 11: The apparatus of aspect 10, where the contact is at least partially filled with a fourth material, the fourth material between the third material and the second metallic material.

Aspect 12: The apparatus of any of aspects 8 through 11, where the contact extends through each layer of the plurality of layers of the stack of materials.

Aspect 13: The apparatus of any of aspects 8 through 12, where the contact extends partially through the stack of materials to a depth of the layer of the plurality of layers.

Aspect 14: The apparatus of any of aspects 8 through 13, where the second metallic material includes Molybdenum.

Aspect 15: The apparatus of any of aspects 8 through 14, where the first metallic material of the layer of the plurality of layers forms a plurality of word lines each coupled with respective pluralities of memory cells.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels.