Memory controller managing temperature of memory device and memory system having the memory controller

There are provided a memory controller and a memory system having the same. The memory controller includes: a temperature monitor device configured to count values that vary according to operation statuses of memory devices; a status check device configured to output status information of the memory devices based on the count values; and a scheduler configured to store the status information according to arrangements of the memory devices, and output the status information in response to a request received from a host.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2018-0045717, filed on Apr. 19, 2018, the entire disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of Invention

The present disclosure generally relates to a memory controller and a memory system having the same, and more particularly, to a memory controller for controlling access of a memory device, based on temperature information of the memory device, and a memory system having the memory controller.

2. Description of Related Art

A memory system may include a memory device for storing data and a memory controller for controlling the memory device.

The memory device may be a nonvolatile memory device in which data is retained even when the supply of power is interrupted or a volatile memory device in which data is lost when the supply of power is interrupted. The memory system may be implemented with a nonvolatile memory device or a volatile memory device according to the memory system.

The memory controller may communicate between a host and the memory device. For example, when a request is received from the host, the memory controller controls the memory device to execute the received request. When a program request is received from the host, the memory controller may generate a program command for controlling the memory device, and sequentially transmit the program command and data received from the host to the memory device. When a read request and a logical address are received from the host, the memory controller may generate a read command for controlling the memory device and then sequentially transmit the read command and a physical address corresponding to the logical address to the memory device.

The memory device may include many highly integrated cells to support a large capacity. However, a heat generation phenomenon may occur, in which the temperature in a specific area of the memory device is increased. Heat generation may cause degradation of the performance is and lifespan of the memory device, which results in deterioration of the reliability of the memory system.

SUMMARY

Embodiments provide a memory controller capable of suppressing a phenomenon in which the temperature in a specific area of a memory device is increased, and a memory system having the memory controller.

In accordance with an aspect of the present disclosure, there is provided a memory controller including: a temperature monitor device configured to count values varied according to operation statuses of memory devices; a status check device configured to output status information of the memory devices by calculating the count values; and a scheduler configured to store the status information according to various arrangements of the memory devices, and output the status information in response to a request received from a host.

In accordance with another aspect of the present disclosure, there is provided a memory controller including: a host interface configured to receive requests from a host, and output data read from memory devices to the host; and a command/address controller configured to update, in real time, temperature statuses of the memory devices, and access the memory devices by considering the temperature statuses when the requests are received.

In accordance with still another aspect of the present disclosure, there is provided a memory system including: memory devices configured to store data; and a memory controller configured to control the memory devices in response to requests received from a host, wherein the memory system includes a memory controller configured to store status information on temperature statuses of the memory devices and output the status information to the host.

In accordance with still another aspect of the present disclosure, there is provided a memory system including: a plurality of memory devices, each including a plurality of memory groups, each of which includes a plurality of memory elements, wherein the memory devices are stacked on each other, and wherein, for each memory device, the memory groups thereof are arranged adjacently on a surface of the corresponding memory device, and, for each memory group, the memory elements thereof are arranged adjacently on a surface of the corresponding memory group; and a memory controller suitable for: receiving an address and a command for accessing at least one of the memory devices, and generating temperature monitoring information for each of the memory elements, based on spatial arrangements of other memory elements with the corresponding memory element indicated by the address and the type of the command

DETAILED DESCRIPTION

In the following detailed description, various embodiments of the present disclosure are shown and described, simply by way of example. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.

FIG. 1is a diagram illustrating a memory system1000in accordance with an embodiment of the present disclosure.

Referring toFIG. 1, the memory system1000may include a memory device1100for storing data and a memory controller1200for communicating between a host2000and the memory device1100.

The memory device1100may be implemented with a nonvolatile memory device in which stored data is retained even when the supply of power is interrupted or a volatile memory device in which stored data is lost when the supply of power is interrupted.

The memory device1100may include a plurality of memory cells for storing data, and the memory cells may be divided in units of various groups. For example, the memory device1100includes at least one high level memory device, which includes at least one middle level memory device, which includes at least one low level memory device. A plurality of memory cells may be included in the low level memory device. Therefore, the high level memory device, the middle level memory device, and the low level memory device may be distinguished and managed by different addresses.

The high level memory device, the middle level memory device, and the low level memory device are names for distinguishing storage areas within the memory device1100. However, in addition to the above-described names, the name of a storage area may be expressed as a rank, a bank, a bank group, a slice, a channel, a plane, a block, or the like. Thus, although the terms high level memory device, middle level memory device, and low level memory device are described in embodiments, the names of the storage areas are not limited thereto. The high level memory device, the middle level memory device, and the low level memory device will be described later.

The memory controller1200may control overall operations of the memory system1000, and control data exchange between the host2000and the memory device1100. For example, the memory controller1200programs or reads data by controlling the memory device1100in response to a request from the host2000.

A buffer memory1300may be further included in the memory system1000. The buffer memory1300may control data exchange between the host2000and the memory device1100or temporarily store system data for controlling the memory device1100. For example, the buffer memory1300is used as a working memory or cache memory of the memory controller1200. Also, the buffer memory1300may temporarily store codes and commands, which are executed by the memory controller1200.

The memory controller1200may temporarily store data received from the host2000in the buffer memory1300and then transmit the data temporarily stored in the buffer memory1300to the memory device1100to be stored in the memory device1100. Also, the memory controller1200may receive data and a logical address from the host2000, and translate the logical address into a physical address of the memory device1100. Also, the memory controller1200may store, in the buffer memory1300, logical-to-physical address mapping information that establishes a mapping relationship between the logical address and the physical address.

In some embodiments, the buffer memory1300may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a DDR4 SDRAM, a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (DDDR) SRAM, a low power DDR (LPDDR), and a Rambus dynamic random access memory (RDRAM).

The memory device1100, the memory controller1200, and the buffer memory1300may be arranged adjacent to each other along a plane defined by a first direction X and a second direction Y. The first direction X and the second direction Y may be orthogonal to each other.

The host2000may communicate with the memory system1000by using at least one of various communication schemes such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high speed intership (HSIC), a small computer system interface (SCSI), a peripheral component interconnection (PCI), a PCI express (PCIe), a non-volatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multi-media card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

FIG. 2is a diagram illustrating a memory device in accordance with an embodiment of the present disclosure, for example, the memory device1100ofFIG. 1.

Referring toFIG. 2, the memory device1100may include at least one high level memory device HMD. In an embodiment, a first high level memory device HMD1is illustrated inFIG. 2.

The first high level memory device HMD1may include at least one middle level memory device MMD. In an embodiment, first to fourth middle level memory devices MMD1to MMD4included in the first high level memory device HMD1are illustrated inFIG. 2. However, the number of middle level memory devices MMD included in one high level memory device HMD may be changed depending on the memory device1100. Different physical addresses may be designated to the first to fourth middle level memory devices MMD1to MMD4.

The first to fourth middle level memory devices MMD1to MMD4may be arranged adjacent to each other along a plane defined by the first direction X and the second direction Y.

FIG. 3is a diagram illustrating a middle level memory device in accordance with an embodiment of the present disclosure, for example, the middle level memory device ofFIG. 2.

Referring toFIG. 3, the middle level memory device MMD may include at least one low level memory device LMD. In an embodiment, first to fourth low level memory devices LMD1to LMD4included in the first middle level memory device MMD1are illustrated inFIG. 3. However, the number of low level memory devices LMD included in one middle level is memory device MMD may be changed depending on the memory device1100. Different physical addresses may be designated to the first to fourth low level memory devices LMD1to LMD4.

The low level memory device LMD may include a plurality of memory cells and a peripheral circuit for performing a program, read or erase operation on the memory cells. Also, the low level memory device LMD may include a plurality of groups of memory cells, which are designated by different physical addresses.

The first to fourth low level memory devices LMD1to LMD4may be arranged adjacent to each other along a plane defined by the first direction X and the second direction Y.

FIG. 4is a perspective view illustrating an exemplary arrangement of a high level memory device, middle level memory devices, and low level memory devices.

Referring toFIG. 4, middle level memory devices MMD # (where # is a positive integer) may be arranged in parallel to each other on the top of their associated high level memory device HMD #, and low level memory devices LMD # may be arranged in parallel to each other on the top of each of the middle level memory devices MMD #. For example, the high level memory device HMD #, the middle level memory devices MMD #, and the low level memory devices LMD # are stacked along a third direction Z vertical to the first and second directions X and Y, the middle level memory devices MMD # may be arranged in parallel to each other along the first and second directions X and Y, and the low level memory devices LMD # may be arranged in parallel to each other along the first and second directions X and Y.

FIG. 5is a perspective view illustrating a memory device having a multi-stack structure in accordance with an embodiment of the present disclosure.

Referring toFIG. 5, the memory device1100having the multi-stack structure may include a plurality of high level memory devices HMD stacked on each other. In an embodiment, a structure in which first to eighth high level memory devices HMD1to HMD8are stacked is illustrated inFIG. 5. In addition, the middle level memory devices MMD # and the low level memory devices LMD #, which are shown inFIG. 4, are included in each of the first to eighth high level memory devices HMD1to HMD8. However, inFIG. 5, the middle level memory devices MMD # and the low level memory devices LMD # are omitted to illustrate a structure in which eight high level memory devices HMD1to HMD8are stacked on each other along the third direction Z.

A structure in which a plurality of high level memory devices HMD # are stacked may be referred to as the multi-stack structure, and the middle level memory devices MMD # and the low level memory devices LMD # may also be stacked along the third direction Z.

As described above, when the high level, middle level, and low level memory devices HMD #, MMD #, and LMD # are densely arranged, the degree of integration of the memory device1100is increased. Hence, the size of the memory device1100may be decreased, and the capacity of the memory device1100may be increased. However, the distance or margin between the high level, middle level, and low level memory devices HMD #, MMD #, and LMD # may be decreased due to high degree of integration. Therefore, a heat generation phenomenon may occur, in which when a specific operation is performed, the temperature in a specific area is increased.

In this embodiment, in order to suppress the heat generation phenomenon, a command may be queued or a memory device to be accessed may be changed, based on temperature statuses of memory devices, which are monitored in real time. Also, in this embodiment, the memory controller may update the temperature statuses of the memory devices according to a number of times of accessing to a memory device and an operation performed in the memory device.

To this end, the memory controller1200will be described in detail as follows.

FIG. 6is a diagram illustrating a memory controller in accordance with an embodiment of the present disclosure, for example, the memory controller1200ofFIG. 1.

Referring toFIG. 6, the memory controller1200may include an internal (IN.) memory210, a central processing unit (CPU)220, a command/address (CMD/ADD) controller230, a host interface240, a buffer interface250, and a memory interface260.

The internal memory210may store various system information necessary for an operation of the memory controller1200. In addition, the internal memory210may store address mapping information, debugging information, and the like, which are necessary for an operation of the memory system1000. For example, the internal memory210is implemented with a static random access memory (SRAM).

The CPU220may perform various operations for controlling the memory device1100or run firmware. The CPU220may transmit a request received from the host2000to the CMD/ADD controller230. The CPU220may control overall operations of the internal memory210, the CMD/ADD controller230, the host interface240, the buffer interface250, and the memory interface260.

The CMD/ADD controller230may update, in real time, a temperature status of the memory device1100according to a command executed in the memory device1100, and control access of high level, middle level, and low level memory devices included in the memory device1100.

The host interface240may communicate with the host2000coupled to the memory system1000under the control of the CPU220. For example, the host interface240receives a program, read or erase request and data from the host2000, and outputs data read from the memory device1100to the host2000.

When the buffer memory1300is disposed at the outside of the memory controller1200, the buffer interface250may transmit information to the buffer memory1300under the control of the CPU220, or transmit information stored in the buffer memory1300to the CPU220.

The memory interface260may communicate with the memory device1100under the control of the CPU220. For example, the memory interface260transmits a command, an address, and data to the memory device1100under the control of the CPU220, and transmits data read from the memory device1100to the CPU220.

The CPU220may transmit data between the internal memory210, the CMD/ADD controller230, the host interface240, the buffer interface250, and the memory interface260through a bus270. In some embodiments, the CMD/ADD controller230, the host interface240, and the memory interface260may independently communicate with each other without passing through the bus270. For example, the CMD/ADD controller230and the host interface240directly communicate with each other without passing through the bus270, the CMD/ADD controller230and the memory interface260directly communicate with each other without passing through the bus270, and the host interface240and the memory interface260directly communicate with each other without passing through the bus270.

FIG. 7is a diagram illustrating a command and address controller and a host interface in accordance with an embodiment of the present disclosure, for example, the CMD/ADD controller230and the host interface240ofFIG. 6.

Referring toFIG. 7, the CMD/ADD controller230may update, in real time, a temperature status of the memory device1100. Also, when a request is received from the host2000, the CMD/ADD controller230may generate a command corresponding to the request, and transmit the command to the memory device1100through the memory interface260by scheduling the command according to the temperature status of the memory device1100. That is, the CMD/ADD controller230may control access of the memory device1100according to the temperature status of the memory device1100.

The host interface240may include a request (RQ) buffer11, a data input buffer12, and a data output buffer13.

The RQ buffer11may receive requests from the host2000to temporarily store the received requests, and sequentially transmit the received requests to the memory controller1200. For example, the RQ buffer11may sequentially transmit the temporarily stored requests to the CMD/ADD controller230under the control of the CPU220.

The data input buffer12may temporarily store data received from the host2000, and transmit the data to the memory interface260under the control of the CPU220. For example, in a program operation, data received from the host2000is temporarily stored in the data input buffer12.

The data output buffer13may temporarily store data received from the memory interface260, and output the received data to the host2000under the control of the CPU220. For example, in a read operation, data read from the memory device1100is received through the memory interface260. When data is transmitted from the memory interface260to the data output buffer13, the data output buffer13may output the data to the host2000. Also, the data output buffer13may output status information STIF of the memory device1100, which is received from a scheduler310of the CMD/ADD controller230, to the host2000.

The CMD/ADD controller230may include the scheduler310, a CMD/ADD generator320, a status check device330, and a temperature monitor device340.

The scheduler310may receive status information STIF of the memory device1100from the status check device330, and queue requests received from the RQ buffer11, based on the status information STIF. An operation command and a logical address may be included in the request received from the host2000. Also, the scheduler310may output the stored status information STIF to the data output buffer13in response to the request of the host2000, and the data output buffer13may output the status information STIF to the host2000. The host2000may monitor a temperature status of the memory device1100, based on the received status information STIF.

The CMD/ADD generator320may receive requests from the scheduler310, generate a command and a physical address, which respectively correspond to the requests, and simultaneously transmit the generated command and the generated physical address to the memory interface260and the temperature monitor device340. The physical address may be received from a map table stored in the buffer memory1300ofFIG. 1. Also, the CMD/ADD generator320may transmit the physical address to the status check device330before the command and the physical address are output, and output the command and the physical address after it is checked whether the physical address is in a state in which it is accessible.

The status check device330may update, in real time, a check value of a physical address, and output the check value of a physical address to be accessed. Also, the status check device330may receive temperature information from the temperature monitor device340, calculate a temperature influence value between storage devices corresponding to the physical address, based on the temperature information, and output the temperature influence value as status information.

The temperature monitor device340may update, in real time, count information according to the command and the physical address, which are received from the CMD/ADD generator320. The updated count information of the physical address may be transmitted to the status check device330.

FIG. 8is a diagram illustrating a command and address controller and a host interface in accordance with an embodiment of the present disclosure, for example, the CMD/ADD controller230and the host interface240ofFIG. 6.

The CMD/ADD controller230shown inFIG. 8has the same configuration as that described in connection withFIG. 7except the former includes a host interface240. Therefore, description of common components is omitted below.

Referring toFIG. 8, the host interface240may further include a status information (STIF) output buffer14. The status information output buffer14may receive status information STIF of the memory device1100from the scheduler310, and output the received status information STIF to the host2000. The data output buffer13may output only data received from the memory interface260to the host2000.

When the status information output buffer14outputs status information STIF to the host2000, the data output buffer13outputs data to the host2000regardless of the status information STIF, so that the operation time of the memory controller1200may be reduced.

The configuration of the CMD/ADD controller230described inFIG. 7 or 8will be described in detail as follows.

FIG. 9is a diagram illustrating a scheduler in accordance with an embodiment of the present disclosure, for example, the scheduler310ofFIG. 7 or 8.

Referring toFIG. 9, the scheduler310may include a status table21for storing status information STIF and a request (RQ) queue22. The RQ queue22may queue an output order of a request RQ with reference to the status table21. The scheduler310may receive and store status information STIF corresponding to a logical address from the status check device330in the status table21. Further, the scheduler310may queue, based on the status information SFIF in the status table21, the request RQ in the RQ queue22such that heat generated in the memory device1100is not increased or that the temperature of the memory device1100is distributed, by comparing a logical address included in a request RQ received from the host interface240with an arbitrary address to be compared with the logical address.

A number of cases or situations subject to various degrees of temperature influence stored in the status table21. The number of cases to include may be different depending on specific structural details of the memory devices. An embodiment of various temperature influences is illustrated inFIG. 10.

FIG. 10is a diagram illustrating information stored in a status table in accordance with an embodiment of the present disclosure, for example, the status table21ofFIG. 9.

Referring toFIG. 10, temperature influences with respect to various cases may be stored as data in the status table21. The temperature influences may be different according to current statuses of memory devices and the request RQ received from the host interface240. For example, the temperature influences are different according to whether memory cells indicated by an address selected by the request RQ and an arbitrary address to be compared are physically stacked on each other or are parallel to each other. The memory cell indicated by each address may correspond to one memory cell or a plurality of memory cells. In addition, the temperature influences may be different according to how much the physical distance between the memory cells indicated by the address selected by the request RQ and the arbitrary address to be compared is.

In the status table21, ‘MY’ means a case where the memory cells indicated by the requested address and the address to be compared are the same. ‘VTN’ in the status table21means a case where the memory cells indicated by the requested address and the address to be compared are physically and vertically arranged adjacent to each other. The temperature influence with respect to the case of ‘VTN’ may be largest as compared with other cases. ‘VA’ in the status table21means a case where the memory cells indicated by the requested address and the address to be compared are physically and vertically arranged but are not arranged adjacent to each other. Therefore, the case of ‘VA’ may be less influenced by temperature than the case of ‘VTN.’ ‘TS’ in the status table21means a case where the memory cells indicated by the requested address and the address to be compared are hardly influenced by temperature. For example, ‘TS’ is a case where the memory cells indicated by the requested address and the address to be compared are physically vertically arranged but are respectively arranged at the uppermost end and the lower most end.

‘LN’ in the status table21may be a case where the memory cells indicated by the requested address and the address to be compared are physically and horizontally arranged but are arranged adjacent to each other. This case may be one in which the memory cells indicated by the requested address and the address to be compared are horizontally most influenced by temperature. ‘VXN’ in the status table21may be a case where the memory cells indicated by the requested address and the address to be compared are physically and horizontally arranged but are arranged in a diagonal direction. Therefore, the case of ‘VXN’ may be less influenced by temperature than the case of ‘LN.’

‘DN’ in the status table21may be a case where the memory cells indicated by the requested address and the address to be compared have physical positions vertically and horizontally symmetrical to each other. ‘EN’ in the status table21may be a case where the memory cells indicated by the requested address and the address to be compared are physically and vertically arranged but are symmetrical to each other on the same row. In the case of ‘EN,’ the distance between the physical positions of the memory cells indicated by the requested address and the address to be compared is short as compared with the case of ‘DN,’ and therefore, the temperature influence of the case of ‘EN’ may be larger than that of the case of ‘DN.’

Data about temperature influences with respect to various other cases, in addition to the above-described cases, may be stored in the status table21. In general, when the number of memory devices or the number of physical addresses increases, the number of cases stored in the status table21may increase.

Referring back toFIG. 9, the RQ queue22may select, with reference to the status table21, a case where the temperature influence of the memory device1100is small, and queue a request RQ according to the selected case. Subsequently, the RQ queue22may transmit the queued request RQ to the CMD/ADD generator320.

The status information STIF stored in the scheduler310may be output to the host interface240, and the host interface240may output the received status information STIF to the host2000.

FIG. 11is a diagram illustrating a command and address generator in accordance with an embodiment of the present disclosure, for example, the CMD/ADD generator320ofFIG. 7 or 8.

The ADD generator31may generate a physical address corresponding to the logical address included in the request RQ. The CMD generator32may generate a command CMD corresponding to the command in the request RQ22of the scheduler310inFIG. 9. For example, the ADD generator31receives a physical address corresponding to the logical address from a map address stored in the buffer memory1300ofFIG. 1. When a physical address ADD corresponding to the logical address is received, the ADD generator31may transmit the physical address ADD to the status check device330and receive a check signal CH_S from the status check device330. The ADD generator31may output the command CMD and the physical address ADD to the memory interface260in response to the check signal CH_S from the status check device330. For example, when the check signal CH_S is activated, the ADD generator31and the CMD generator32respectively output the physical address ADD and the command CMD to the memory interface260. When the check signal CH_S is inactivated, the ADD generator31and the CMD generator32do not output the physical address ADD and the command CMD, respectively. The check signal CH_S may be activated when the average temperature of the memory device1100is lower than a threshold temperature. The check signal CH_S may be inactivated when the average temperature of the memory device1100is higher than the threshold temperature.

The command CMD and the physical address ADD, which are output from the CMD/ADD generator320, may be transferred to the temperature monitor device340so as to update the temperature status of the memory device1100.

FIG. 12is a diagram illustrating a status check device in accordance with an embodiment of the present disclosure, for example, the status check device330ofFIG. 7 or 8.

Referring toFIG. 12, the status check device330may include a status register41, a counter42, and a calculator43.

The status register41may store status values of memory devices, and output the check signal CH_S, based on a status value corresponding to the physical address ADD received from the CMD/ADD generator320. When the average temperature of the memory device1100is lower than the threshold temperature, the status register41may activate the check signal CH_S. When the average temperature of the memory device1100is higher than the threshold temperature, the status register41may inactivate the check signal CH_S. Also, when the physical address ADD is received, the status register41may transmit an address reception signal to the counter42.

The counter42may output a count value CNT whenever the address reception signal is received from the status register41. When the address reception signal is received within a certain time, the counter42may increase the count value CNT. When the address reception signal is not received within the certain time, the counter42may decrease the count value CNT. That is, the counter42may increase the count value CNT of a memory device in which an operation is consecutively performed, and decrease the count value CNT of a memory device in which an operation is not performed or an idle state is continued.

The calculator43may receive count information CNTIF, and may output status information STIF by adding up count values for the respective addresses. Specifically, the calculator43may generate a count value of each of the high level memory devices, a count value of each of the middle level memory devices, and a count value of each of the low level memory devices from the count values of all of the high level, middle level, and low level memory devices included in the count information CNTIF. Then, the calculator43may match the generated count values to the respective addresses, and output the matched count values as the status information STIF.

FIG. 13is a diagram illustrating a temperature monitor device in accordance with an embodiment of the present disclosure, for example, the temperature monitor device340ofFIG. 7 or 8.

Referring toFIG. 13, the temperature monitor device340may include an address (ADD) decoder51, a command (CMD) decoder52, and a temperature table53.

The ADD decoder51may decode a physical address ADD received from the CMD/ADD generator320and output the decoded physical address ADD as a decoded address D_ADD. The decoded address D_ADD may be an address for distinguishing upper level, middle level, and low level memory devices from one another. That is, the ADD decoder may decode the physical address ADD transmitted to the memory device1100as an address to be managed in the temperature table53.

The CMD decoder52may decode a command CMD received from the CMD/ADD generator320and output the decoded command CMD as a decoded command D_CMD. The decoded command D_CMD may be a command for distinguishing different operations from one another. That is, the CMD decoder52may decode the command CMD to the memory device1100as a command to be managed in the temperature table53.

The temperature table53may update a count value for each address according to the decoded address D_ADD, the decoded command D_CMD, and the count value CNT. An embodiment of the temperature table53is illustrated inFIG. 14.

FIG. 14is a diagram illustrating a temperature table in accordance with an embodiment of the present disclosure, for example, the temperature table53ofFIG. 13.

Referring toFIG. 14, the temperature table53may store count values CNT of high level, middle level, and low level memory devices HMD, MMD, and LMD in the memory device1100. The temperature table53may receive the decoded addresses D_ADD and the decoded commands D_CMD from the ADD decoder51and the CMD decoder52, respectively, and receive the count values CNT from the status check device330. For example, the decoded addresses D_ADD may include addresses of the high level, middle level, and low level memory devices HMD, MMD, and LMD. The temperature table53may update a count value for each address according to the decoded address D_ADD. Each of the count values may be increased according to the count value CNT received from the status check device330.

FIG. 14shows that first to fourth high level memory devices HMD1to HMD4are included in the memory device1100, first to fourth middle level memory devices MMD1to MMD4are included in each of the first to fourth high level memory devices HMD1to HMD4, and first to eighth low level memory devices LMD1to LMD8are included in each of the first to fourth middle level memory devices MMD1to MMD4. The following discussion is also based on this arrangement.

The count value CNT corresponding to each of the eight low level memory devices LMD1to LMD8may be updated. For example, the count value CNT of the first low level memory device LMD1of the first middle level memory device MMD1of the first high level memory device HMD1is increased according to the decoded command D_CMD. That is, the decoded address D_ADD may select an address to be updated, and the degree of heat generation of the address to be updated may be determined according to the decoded command D_CMD. For example, assuming that the degree of heat generation in a program operation is greater than that in a read operation, the count value CNT may be increased relatively more when the decoded command D_CMD is a command corresponding to the program operation, and be increased relatively less when the decoded command D_CMD is a command corresponding to the read operation.

When count information CNTIF on each memory device is output from the temperature table53, the calculator43ofFIG. 12may calculate a count value of the first middle level memory device MMD1by adding up all count values CNT # of the first to eighth low level memory devices LMD1to LMD8. Further, the calculator43may calculate a count value of the first high level memory device HMD1by adding up all count values CNT # of the first to fourth middle level memory devices MMD1to MMD4. When the added-up count value of corresponding memory devices, that is, associated low level, middle level and high level memory devices, is increased, it indicates that the temperature of the corresponding memory devices is increased.

FIG. 15is a flowchart illustrating an operating method in accordance with an embodiment of the present disclosure.

Referring toFIG. 15, the operating method using the devices described inFIGS. 7 to 14.

When a request RQ is received from the host2000(S41), the memory controller1200may process the received request RQ. Specifically, the scheduler310ofFIG. 8may schedule the request RQ, and that request RQ may be transmitted to the CMD/ADD generator320ofFIG. 7 or 8. As described inFIG. 9, the scheduler310may determine a case where heat generation is low by comparing a requested address with an address to be compared, queue the request RQ according to the determined case, and transmit the queued request RQ to the CMD/ADD generator320.

The CMD/ADD generator320may generate a command CMD and a physical address ADD in response to the received request RQ (542),

When the command CMD and the physical address ADD are received from the CMD/ADD generator320, the scheduler310may update status information corresponding to the corresponding physical address (S43).

After the command CMD is again queued or the physical address ADD is again mapped according to the updated status information (S44), the memory controller1200may access the memory device1100according to the mapped address (S45).

FIG. 16is a diagram illustrating an effect of the present disclosure.

Referring toFIG. 16, in a memory device1100having a multi-stacked structure, a command and an address are controlled by considering all temperature influences in the first direction X, the second direction Y, and the third direction Z with respect to the memory devices in the memory device1100. Such an arrangement may prevent a phenomenon in which the temperature in a specific area is increased. That is, in this embodiment, a temperature influence with respect to a request received from the host2000and an arbitrary memory device may be calculated, and the command and address may be controlled such that the temperature influence is minimized.

Accordingly, degradation of the performance and shortening of the lifespan of the memory device may be suppressed, and the reliability of the memory controller and the memory system having the same may be improved.

FIG. 17is a diagram illustrating a memory system30000including a memory controller in accordance with an embodiment of the present disclosure, for example, the memory controller1200shown inFIG. 1.

Referring toFIG. 17, the memory system30000may be implemented as a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), or a wireless communication device.

The memory system30000may include a memory device1100and the memory controller1200capable of controlling an operation of the memory device1100. The memory controller1200may control a data access operation of the memory device1100, e.g., a program operation, an erase operation, a read operation, or the like under the control of a processor3100.

Data programmed in the memory device1100may be output through a display3200under the control of the memory controller1200.

A radio transceiver3300may transmit and receive radio signals through an antenna ANT. For example, the radio transceiver3300converts a radio signal received through the antenna ANT into a signal that can be processed by the processor3100. Therefore, the processor3100may process a signal output from the radio transceiver3300and transmit the processed signal to the memory controller1200or the display3200. The memory controller1200may transmit the signal processed by the processor3100to the memory device1100. Also, the radio transceiver3300may convert a signal output from the processor3100into a radio signal, and output the converted radio signal to an external device through the antenna ANT. An input device3400is a device capable of inputting a control signal for controlling an operation of the processor3100or data to be processed by the processor3100, and may be implemented as a pointing device such as a touch pad or a computer mount, a keypad, or a keyboard. The processor3100may control an operation of the display3200such that data output from the memory controller1200, data output from the radio transceiver3300, or data output from the input device3400can be output through the display3200.

FIG. 18is a diagram illustrating a memory system40000including a memory controller in accordance with an embodiment of the present disclosure, for example, the memory controller1200shown inFIG. 1.

Referring toFIG. 18, the memory system40000may be implemented as a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The memory system40000may include a memory device1100and the memory controller1200capable of controlling a data processing operation of the memory device1100.

A processor4100may output data stored in the memory device1100through a display4300according to data input through an input device4200. For example, the input device4200is implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The processor4100may control overall operations of the memory system40000, and control an operation of the memory controller1200.

FIG. 19is a diagram illustrating a memory system50000including a memory controller in accordance with an embodiment of the present disclosure, for example, the memory controller1200shown inFIG. 1.

Referring toFIG. 19, the memory system50000may be implemented as an image processing device, e.g., a digital camera, a mobile terminal having a digital camera attached thereto, a smart phone having a digital camera attached thereto, or a tablet personal computer (PC) having a digital camera attached thereto.

The memory system50000may include a memory device1100and the memory controller1200capable of controlling a data processing operation of the memory device1100, e.g., a program operation, an erase operation, or a read operation.

An image sensor5200of the memory system50000may convert an optical image into digital signals, and the converted digital signals may be transmitted to a processor5100. Under the control of the processor5100, the converted digital signals may be output through a display5300, or be stored in the memory device1100through the memory controller1200. In addition, data stored in the memory device1100may be output through the display5300under the control of the processor5100.

FIG. 20is a diagram illustrating a memory system70000including a memory controller in accordance with an embodiment of the present disclosure, for example, the memory controller1200shown inFIG. 1.

Referring toFIG. 20, the memory system70000may be implemented as a memory card. The memory system70000may include a memory device1100, the memory controller1200, and a card interface7100.

The memory controller1200may control data exchange between the memory device1100and the card interface7100. In some embodiments, the card interface7100may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but the present disclosure is not limited thereto. The card interface7100may interface data exchange between a host60000and the memory controller1200according to a protocol of the host60000. In some embodiments, the card interface7100may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. The card interface7100may mean hardware capable of supporting a protocol used by the host60000, software embedded in the hardware, or a signal transmission scheme.

The host60000may include a microprocessor (μP)6100and a host interface6200. The microprocessor6100may control overall operations of the host60000, and communicate with the memory system70000through the host interface6200.

In accordance with embodiments of the present disclosure, a phenomenon in which the temperature in a specific area of the memory device is increased in an operation of the memory device can be prevented. Accordingly, degradation of the performance and shortening of the lifespan of the memory device can be suppressed, and the reliability of the memory controller and the memory system having the same can be improved.