Parallel digital-to-time converter architecture

This document discusses, among other things, digital-to-time converters (DTCs) and more particularly to parallel implementations of DTCs. In an example, an apparatus can include a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information of a polar transmitter and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information of the polar transmitter and to provide a second portion of phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal.

TECHNICAL FIELD

This document discusses, among other things, wireless communications and, more particularly, parallel digital-to-time converter (DTC) architecture for wideband or high-speed communication applications.

BACKGROUND

Digital-to-time converters (DTCs) are being considered for use in cellular communication electronics as well as some newer wireless network environments. DTC are showing promise in simplifying wireless transmission and reception architectures. However, target bandwidths and carrier frequencies of these future communication protocols are stretching beyond the limits of current DTC technologies.

DESCRIPTION OF THE EMBODIMENTS

The present inventors have recognized that bandwidth and frequency requirements of future wireless communication protocols are pushing beyond what present technology can reliably provide. Recent developments using DTC in polar transmitters show promise in simplifying the transmission and reception electronic architecture. The inventors have further recognized a parallel DTC architecture that can address the high bandwidth and high frequency limitations of current phased locked loop PLL architectures.

In general, a DTC based architecture can simplify transmission and reception architectures by allowing a single PLL or reference frequency to be shared between communication functions such as being shared between two or more transmitters, two or more receivers or a combination of transmitters and receivers. In certain examples, a DTC can be used to shift a PLL frequency or frequency of a frequency generator for use in a receiver processing path. In certain examples, a DTC can be used to shift frequency and optionally provide modulation for transmission processing path. The parallel DTC architecture discussed below can be used in a variety of communication devices as well as non-communication application. With regards to communication devices, the parallel DTC architecture can be used to generate a frequency different from a reference frequency of a central oscillator or central frequency generator by using a frequency ramp to offset or shift the reference frequency. Such frequency shifting can be implemented in a variety of communication circuits including receivers, transmitters, such as polar transmitters and Cartesian transmitters, and transceivers. In some examples, the parallel DTC architecture can be used to provide phase modulation. In some examples, the parallel DTC architecture can be used to provide frequency shifting and phase modulation.

FIG. 1Aillustrates generally an example parallel DTC architecture100for a transmitter. In certain examples, the transmission architecture can include a first DTC101, a second DTC102, a logic circuit103for receiving modulation information (ψ) and providing the modulation information to each DTC101,102and a combiner104. The two DTCs101,102can work together to share a reference frequency signal, such as a reference frequency signal from a PLL, local oscillator (LO) or a digitally controlled oscillator (DCO), and provide a modulated output signal (DTC1, DTC2). In certain examples, using two DTCs101,102can allow independent rising and falling edge modulation of the output signal (DTCOUT) using lower frequency components. In some examples, an output frequency of the transmitter can be the same as a frequency of the output signal (DTC1, DTC2) of the DTCs101,102. In some examples, the output frequency of the transmitter can be double a frequency of the output signal (DTC1, DTC2) of the DTCs101,102. In certain examples, the first DTC101and the second DTC102can receive a reference signal from a frequency generator (LO), and can receive modulation information from an optional rate converter, such as a fractional sample rate converter (FSRC), based on modulation information (ψ) received from a processor, such as a baseband processor. In some examples, the DTCs101,102can independently modulate rising and falling edges of an output signal of the transmitter to support very high frequency and wide channel bandwidths. In certain examples, each DTC can include a coarse phase adjustment111,121and a fine phase adjustment112,122for shifting each edge of the reference signal to generate an output signal (DTC1, DTC2) of the respective DTC101,102. In certain examples, the combiner can receive the output signal (DTC1, DTC2) of the individual DTCs101,102, can process the DTC output signals (DTC1, DTC2) and to provide a signal (DTCOUT) representative of a combination of the DTC output signals (DTC1, DTC2). In some examples, the combiner104can include a latch circuit105(FIG. 1B), such as an Set-Reset latch (SR-latch) circuit, to provide a first method of processing and combining the output signals (DTC1, DTC2) of the individual DTCs101,102. In some examples, the combiner104can include a doubler circuit106(FIG. 1C) to provide a second method of processing and combining the output signals (DTC1, DTC2) of the individual DTCs101,102.

FIGS. 1A-1Cillustrate examples of DTC-based transmitters with parallel DTC architectures. It is understood that DTC-based receivers can also employ parallel DTC architectures as shown inFIGS. 1A-1C. In certain examples, a logic circuit103for a DTC-based transmitter can include a sample rate converter, such as a fractional sample rate converter, to convert the phase modulation information received from a processor to a proper format for each DTC101,102. A logic circuit103for a DTC-based receiver can be optional and can include, in certain examples, logic to provide the phase information received from the processor to each DTC101,102. In certain examples, the modulation information (ψ) can include, but is not limited to, phase modulation information, phase ramp information, or combinations thereof.

FIG. 2illustrates graphically an example method200of using an example parallel DTC architecture to modulate a transmitter signal. The graphical plot shows a reference signal (LO) received by each of the parallel DTCs, the output (DTC1) of the first DTC, the output (DTC2) of the second DTC and the output of the combiner (DTCOUT). In the illustrated method200, the combiner can use the output (DTC1) of the first DTC to generate the rising edge201of the output signal (DTCOUT) of the combiner, and can use the output (DTC2) of the second DTC to generate the falling edge202of the output signal (DTCOUT) of the combiner. As can be seen, the first DTC can use an edge of the reference signal (LO) to provide rising edge modulation203of the output signal (DTCOUT) of the combiner and the second DTC can use an edge of the reference signal (LO) provide falling edge modulation204of a falling edge of the output signal (DTCOUT) of the combiner. In certain examples, the combiner can include an SR-latch circuit to combine the output signals (DTC1, DTC2) of the first DTC and the second DTC.

FIG. 3illustrates graphically an example method300of using an example parallel DTC architecture to generate and modulate a transmitter signal. The graphical plot shows a reference signal (LO) received by each of the DTCs, the output of the first DTC (DTC1), the output of the second DTC (DTC2), and the output of the combiner (DTCOUT). In the illustrated method, the combiner can use the output (DTC1) of the first DTC to generate a first pulse301of the output signal (DTCOUT) of the combiner, and can use the output (DTC2) of the second DTC to generate a second pulse302of the output signal (DTCOUT) of the combiner. As can be seen, the first DTC can use an edge of the reference signal (LO) to individually modulate303the first pulse301of the output signal (DTCOUT) of the combiner and the second DTC can use an edge of the reference signal (LO) to individually modulate304a second pulse302of the output signal (DTCOUT) of the combiner. In certain examples, the combiner can include a doubler circuit to combine the output signals (DTC1, DTC2) of the first DTC and the second DTC. As can be seen fromFIG. 3, the output signal (DTCOUT) of the doubler circuit can have a frequency twice as high as an output frequency of the DTCs. In certain examples, the doubler can include a first pulser responsive to the output signal (DTC1) of the first DTC and a second pulser responsive to the output signal (DTC2) of the second DTC. In certain examples, the outputs of the first and second pulsers can be OR'd to form the output signal (DTCOUT) of the doubler circuit. In some examples, the first pulser can be responsive to a rising edge of the output signal (DTC1) of the first DTC and the second pulser can be responsive to a falling edge of the output signal (DTC2) of the second DTC. In some examples, the first pulser can be responsive to a falling edge of the output signal (DTC1) of the first DTC and the second pulser can be responsive to a rising edge of the output signal (DTC2) of the second DTC.

FIG. 4illustrates generally an example parallel DTC architecture400for a transmitter. In certain examples, the architecture can include a local oscillator (LO), a sample rate converter403including, but not limited to, a fractional sample rate converter, a first DTC401, a second DTC402, and a combiner404. The local oscillator (LO) can provide a reference frequency for reception by the first DTC401. The sample rate converter403can receive phase modulation information, for example, from a baseband processor (not shown) and can provide properly sample phase information to the first and second DTCs401,402. For systems that can predictably provide phase correction using the fine stage of a DTC, coarse phase modulation can be provided by a coarse stage411of the first DTC401and fine phase modulation can be provided by the fine stage421of the first DTC401and the fine stage422of the second DTC402. In certain examples, the architecture400can save power since the coarse stage412of the second DTC402does not need to be enabled. In certain examples, circuit area can be saved by omitting the coarse stage412of the second DTC402. In some examples, the combiner404can include a latch to combine the outputs of each fine stage412,422. In some examples, the combiner404can include a doubler to combine the outputs of the fine stages412,422and provide a modulated phase signal for a polar transmitter, for example. It is understood that a DTC-based receiver can also incorporate the parallel architecture shown in the example ofFIG. 4without departing from the scope of the present subject matter. In certain examples, a DTC-based receiver can operate without the sample rate converter403and may include a logic circuit to receive the phase modulation information and provide the phase modulation information to each of the DTCs401,402.

FIG. 5illustrates generally an example DTC-based transceiver500for exchanging information between a processor of a wireless device and a processor of one or more other devices using a wireless network or communication link. The transceiver500can include a transmitter501and a receiver503. The transmitter501can include a processor505, such as a digital signal processor (DSP), a polar transmitter540and a power amplifier510. The processor505can receive transmit data from a host processor (not shown), such as a baseband processor of a cell phone, for example, and can provide transmit information to the polar transmitter540. The polar transmitter540can process the transmit information to provide a modulated radio frequency (RF) signal to the power amplifier510. The power amplifier510can amplify and process the RF signal for transmission using an antenna (not shown). The polar transmitter540can include an amplitude processing path541for processing digital amplitude symbols of the transmit data and a phase processing path542for processing digital phase symbols of the transmit information. The phase processing path542can include a transmitter frequency synthesizer515, to provide central frequency information, and a transmitter DTC543to modulate the frequency of the RF signal using the central frequency information. In certain examples, a mixer509can add the amplitude information to the envelope of the RF signal to provide the modulated RF signal. In certain examples, the polar transmitter540can include a cordic converter506to convert the transmit information of the DSP from Cartesian symbols (I, Q) to polar symbols (AM, PM+f). In certain examples, the transmitter DTC can include multiple DTCs operating in parallel with a combiner to provide reliable high-frequency, high-bandwidth communications.

The receiver503can include an amplifier511, demodulator544, a receiver frequency synthesizer516, a receiver DTC545, an analog-to-digital converter (ADC)546and a processor547, such as a receiver DSP. In certain examples, an antenna coupled to the receiver503can receive a wireless signal. The amplifier511can amplify the wireless signal; or certain portions of the wireless signal. The demodulator544can extract information from the wireless signal using a frequency provided by the receiver DTC545. The ADC546can convert the information from an analog form to digital information for further processing by the processor547. The processor547can provide at least a portion of the information to a host processor such as the baseband processor. In certain examples, the receiver DTC can include multiple DTCs operating in parallel with a combiner to provide reliable high-frequency, high-bandwidth communications.

As discussed above, it is understood that parallel DTC architecture can be employed with other communication devices in addition to a polar transmitter as shown inFIG. 5without departing from the scope of the present subject matter. Such other communication devices can include, but are not limited to, receivers, other transmitters such as Cartesian transmitters, and transceivers.

Additional Notes

In Example 1, an apparatus can include a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information and to provide a second portion of phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal.

In Example 2, the combiner of Example 1 optionally includes a Set-Reset (SR) latch.

In Example 3, the SR latch of any one or more of Examples 1-2 optionally is configured to position a first edge of a pulse of the phase modulation signal using the first portion and to position a second edge of the pulse using the second portion.

In Example 4, the second DTC of any one or more of Examples 1-3 optionally is configured to receive the oscillator information, and to provide the second portion using the oscillator signal.

In Example 5, the combiner of any one or more of Examples 1-4 optionally includes a first pulse module configured to provide a plurality of first pulses based on the first portion.

In Example 6, the combiner of any one or more of Examples 1-5 optionally includes a second pulse module configured to provide a plurality of second pulses based on the second portion.

In Example 7, the combiner of any one or more of Examples 1-6 optionally includes an OR-gate configured to combine the plurality of first pulses with the plurality of second pulses to provide the phase modulation signal.

In Example 8, a frequency of the first and second DTCs of any one or more of Examples 1-7 optionally is approximately half of a frequency of the phase modulation signal.

In Example 9, the first DTC of any one or more of Examples 1-8 optionally includes a coarse stage configured to coarsely adjust a first edge and a second edge of the phase modulation signal and a first fine stage configured to finely adjust the first edge using the first phase information to provide the first portion, and the second DTC of any one or more of Examples 1-8 optionally includes a second fine stage configured to receive an output of the coarse stage and to finely adjust the second edge using the second phase information to provide the second portion.

In Example 10, the second DTC of any one or more of Examples 1-9 optionally does not include a coarse stage.

In Example 11, a method of providing a phase modulation signal can include receiving oscillator information and first phase information at a first digital-to-time converter (DTC), providing a first portion of phase modulation information using the first DTC, the oscillator information and the first phase information, receiving second phase information at a second DTC, providing a second portion of phase modulation information using the second DTC and the second phase information, receiving the first portion and the second portion of phase modulation information at a combiner, and combining the first portion and the second portion using the combiner to provide the phase modulation signal.

In Example 12, the combining of any one or more of Examples 1-11 optionally includes generating a first edge of a pulse of the phase modulation signal using the first portion, and generating a second edge of the pulse using the second portion.

In Example 13, the generating the first edge of the pulse and the generating the second edge of the pulse of any one or more of Examples 1-12 optionally includes using a set-reset (S-R) latch of the combiner.

In Example 14, the phase modulation signal of any one or more of Examples 1-13 optionally includes a first plurality of pulses and a second plurality of pulses, and the combining of any one or more of Examples 1-13 optionally includes interleaving the first plurality of pulses with the second plurality of pulses using an OR-gate of the combiner.

In Example 15, the combining of any one or more of Examples 1-14 optionally includes receiving the first portion of the phase modulation information at a first pulse module of the combiner, generating the first plurality of pulses using the first pulse module and the first portion of phase modulation information, receiving the second portion of the phase modulation information at a second pulse module of the combiner, and generating the first plurality of pulses using the second pulse module and the second portion of phase modulation information.

In Example 16, a frequency of the phase modulation signal of any one or more of Examples 1-15 optionally is twice the operating frequency of the first and second DTCs.

In Example 17, the method of any one or more of Examples 1-16 optionally includes receiving the oscillator information at the second DTC, and the providing a second portion of the phase modulation information of any one or more of Examples 1-16 optionally includes using the oscillator information.

In Example 18, a system comprising an antenna, a wireless communication module coupled to the antenna. The wireless communication module can include a frequency synthesizer to provide reference frequency information, a first digital-to-time converter (DTC) configured to receive the reference frequency information and first phase information and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information and to provide a second portion of the phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal.

In Example 19, the wireless communication module of any one or more of Examples 1-18 optionally includes a wireless transmitter.

In Example 20, the wireless communication module of any one or more of Examples 1-19 optionally includes a wireless receiver.

In Example 21, the wireless communication module of any one or more of Examples 1-20 optionally includes a wireless transceiver.