Synthesizer and method for generating an output signal that has a desired period

A frequency synthesizer includes a circuit which selectively outputs multiple output signals having different respective periods to drive the average period of a combined output signal to substantially equal a desired period.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to electronic circuits and, more particularly, to electronic circuits which generate a sequence of pulses with a desired period.

2. Description of the Related Art

Electronic circuits can generate a sequence of pulses which can be used in many applications, such as clocks and pulse generators. In various applications it may be desired to generate a sequence of pulses with a period which is either an integer multiple or a non-integer multiple of a reference clock period. A non-integer multiple can be represented as M/N=P.Q, where M and N are natural numbers and P and Q are integer and decimal numbers, respectively. Hence, M/N is a rational number expressed as a fraction and P.Q is its equivalent expressed as a decimal. In an example, if the reference clock period is 10 ns (i.e. 100 MHz), then to produce a signal with a period of 48.8 ns (i.e. 20.5 MHz), the reference clock period can be multiplied by 4.88 (i.e. M=488, N=100, P=4, and Q=0.88). This is equivalent to dividing the reference clock frequency by 4.88 (i.e. 100 MHz/4.88=20.5 MHz).

Several approaches have been proposed to generate output signals with a period which is a non-integer multiple of a reference period. However, these approaches have jitter which limits their usefulness. Jitter refers to variations in the pulse positions caused by switching between two signals with different phases and appears in the output signal as noise and/or an unintended frequency modulation. Noise typically decreases the signal-to-noise ratio of the system.

Jitter can cause errors in the phase determination of the output signal and, consequently, can reduce the phase margin. The phase of the output signal can be used in many applications, such as analog-to-digital and digital-to-analog converters to define time-points at which the data is sampled. If the phase of the output signal jitters, then there can be errors in the time-points which will affect the overall signal quality.

One way to generate signals with non-integer multiple periods is the rational-rate approach. This approach, as disclosed in U.S. Pat. No. 5,088,057, divides the reference clock frequency by two different integer values to generate two sub-frequencies. The system then switches between the two sub-frequencies to produce an average clock frequency. However, one problem with the rational-rate approach is that the average clock frequency appears to jitter between the phases of the two sub-frequencies. Because the sub-frequencies are generated by dividing by integer numbers, the jitter is on the order of a clock cycle.

Another approach is referred as fractional-frequency divider. As disclosed in U.S. Pat. No. 6,157,694, the system provides several phase-shifted reference signals which have pulse edges shifted over the reference signal period. One pulse edge is outputted at a particular time in response to a trigger signal to provide a high-to-low or a low-to-high pulse edge for the output signal. Hence, the timing of the triggering events determines the frequency of the output signal. However, the fractional-frequency approach also generates jitter in the output signal because the switching is between two phase-shifted signals whose pulse edges, in general, do not always occur at the correct time.

In the rational-rate and fractional frequency approaches, jitter can be reduced by increasing the frequency of the reference signal. Jitter can also be reduced in the fractional frequency approach by increasing the number of phase-shifted signals. However, increasing the reference frequency and the number of phase-shifted signals increases the complexity and cost of the circuitry. Consequently, there is a need for a frequency synthesizer which provides an output signal with an arbitrary period and less jitter, using a lower frequency reference signal and fewer phase shifted signals.

SUMMARY OF THE INVENTION

The Embodiments of the present invention provide a frequency synthesizer which selectively outputs multiple output signals having different periods so that an average period of a combined output signal is driven to substantially equal a desired period. The multiple output signals can be outputted in response to an error signal which is proportional to the difference between the average and desired periods.

In one aspect of the present invention, a signal processing system with a frequency synthesizer includes a signal selection circuit which outputs a selected phase-shifted reference signal in a plurality of phase-shifted reference signals in response to a control signal. A toggle circuit is coupled to an output of the signal selection circuit and alternately outputs multiple output signals in response to a select signal. A control circuit is coupled to an output of the signal selection circuit and provides the control and select signals to the signal selection and toggle circuits, respectively.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a simplified block diagram of a communication system30which implements one embodiment of the invention. System30includes a signal processing system31coupled to a digital phase locked loop (PLL)10through an analog PLL11. System31includes an analog-to-digital converter (ADC)32which receives inputs from a digital-to-analog converter (DAC)36through a data transmission system34. PLLs10and11can be included in communication systems other than the one illustrated inFIG. 1to provide a sequence of pulses with a desired period, where the period can be an integer or a non-integer multiple of a reference clock period. However, PLLs10and11are shown in communication system30to illustrate one particular embodiment of the invention.

PLL10provides a clock signal S(Tout,Φout) in response to both an input signal S(Tin,Φin) and a reference signal Sref(T0,Φ0), in which Toutcan be an integer (i.e. 5) or a non-integer multiple (i.e. 4.33) of Tin. PLL11provides a clock signal S(T′out, Φout), in response to S(Tout,Φout), to ADC32, DAC36, and system34. T refers to a signal period, f refers to a signal frequency (f=1/T), and Φ refers to a signal phase.

PLL11is an optional component in system30, and is included to multiply Toutby a small value to provide T′out. Analog PLLs can typically multiply signal periods by smaller numbers faster and more accurately than digital PLLs. Analog PLLs can also filter out high frequency noise better than digital PLLs. Hence, digital PLL10can provide Toutby multiplying Tinby a larger integer or non-integer number. Analog PLL11can then multiply Toutby a smaller integer number to provide T′out, and filter high frequency noise that may be in signal S(Tout,Φout).

In operation, ADC32samples signal SAnalogat a frequency foutto provide a corresponding digital signal SDigital. SDigitalis processed by and transmitted through system34, where system34outputs a digital signal S′Digital. S′Digitalis provided to converter36, where it is converted back into an analog signal S′Analog. Hence, ADC32and DAC36sample the corresponding data at a rate determined by T′out, where T′outcan be within one phase step of the desired period. This reduces the jitter and also increases the signal-to-noise ratio of the converted signals when T′outis an integer or non-integer multiple of Tin.

DAC36is illustrated for simplicity and ease of discussion and can be replaced with another digital system, such as a display device or a data processing system. A display device can be used when it is desired to provide information included in S′Digitalin a visual format, such as in a video system. A data processing system can be used when it is desired to perform calculations or otherwise manipulate data in response to S′Digital.

FIG. 2illustrates a more detailed view of digital PLL10. PLL10includes a phase detector12coupled to a frequency synthesizer16through a digital filter13. A multiphase signal generator15is also connected to frequency synthesizer16. Detector12receives SAnalog, generator15receives Sref(T0,Φ0), and synthesizer16provides S(Tout,Φout).

Filter13can include a finite impulse response filter, an infinite impulse response filter, or another digital filter. If filter13includes an analog filter, then PLL10corresponds to an analog PLL. In this case, the analog filter can include a low pass filter or another analog filter which can filter a desired range of frequencies and/or provide signal amplification. For the analog PLL case, an external reference signal may not be needed because Sref(T0,Φ0) can be generated internally by the analog filter and provided to generator15. PLL11can be an analog version of PLL10, which can multiply Toutby an integer or a non-integer number, with filter13replaced with an analog filter.

Generator15provides phase-shifted signals of Sref(T0,Φ0), denoted as S(T0, Φ0), S(T0,Φ1),S(T0,Φ2), and S(T0,Φ3) (i.e. “the phase-shifted signals”). Generator15can include a multi-phase ring oscillator, a digital delay line, or a delayed locked loop to generate the phase-shifted signals.

A divider circuit18is coupled between synthesizer16and phase detector12. If the divisor of divider circuit18is N, then the period of a signal fed back to phase detector12is equal to N·Toutand is denoted as S(N·Tout,Φout). Hence, synthesizer16can provide a signal with a period that is a multiple of Tin, where Φinequals Φoutwhen S(Tin,Φin) and S(Tout,Φout) are locked.

Period T0is typically much smaller than both Tinand Toutso that frequency f0is greater than finand fout. In this way, Sref(T0,Φ0) will have pulse edges positioned (i.e. phase-shifted) at closely spaced time intervals compared to both S(Tin,Φin) and S(Tout,Φout) These pulse edges can be selected at particular times by synthesizer16to provide signals which approximate S(Tout,Φout), as will be discussed in more detail below.

In operation, input signal S(Tin,Φin) is provided to phase detector12which detects Φin. PLL10adjusts the period and phase of S(Tout,Φout) in response to Sref(T0,Φ0) and S(Tin,Φin). Detector12compares phase Φinwith phase Φoutand provides to filter13a signal denoted as S(Φin−Φout) which is proportional to the difference between the two phases (i.e. Φin−Φout). The frequency response of filter13is chosen to minimize high frequency fluctuations in the phases between signals S(Tin,Φin) and S(Tout,Φout) so that S(Φin−Φout) is approximately a constant signal. Frequency synthesizer16determines which phase-shifted signal should be outputted at a particular time so that Tout=(M/N)·Tin=P.Q·Tiin. This equation can be rewritten as Tout=(M·m/N)·Tin=(P.Q)·m·Tin, where m is the number of phase steps per clock cycle. One phase step is the time spacing between the phase-shifted reference signals.

FIG. 3illustrates one embodiment of synthesizer16. Synthesizer16includes a signal selection circuit21which outputs a clock signal SClockto a toggle circuit23and a control circuit26. Control circuit26provides a phase control signal SControlto circuit21and an enable signal SEnableto toggle circuit23. Circuit21outputs a desired phase-shifted signal to circuits23and26in response to SControl. Hence, SClockis a composite signal determined by SControland formed from the phase-shifted signals. Trigger circuit23outputs high-to-low or low-to-high pulse edges at predetermined times in response to SClockto form an output signal.

Generally, two or more output signals are selectively outputted so that the average is S(Tout,φout) For simplicity and ease of discussion, it is assumed that two signals, denoted as S(Tout1,φout1) and S(Tout2,φout2), are outputted by circuit23. The predetermined times can be chosen so that the periods of the two output signals average to Tout(Tout=(Tout1+Tout2)/2). Control circuit26can choose Tout1and Tout2similar to the rational rate approach so that the jitter is driven to a predetermined number of phase steps. The predetermined number of phase steps is generally less than m phase steps and, preferably, one phase step.

FIG. 4illustrates a timing diagram51showing the phase-shifted reference signals and signals S(Tout1, φout1), S(Tout2, φout2), and S(Tout, φout). A blown-up portion50of timing diagram51is also illustrated. As shown in blown-up portion50, the phase-shifted signals are same as signal Sref(Tout, φout) except for having shifted phases (i.e. φ1=0°, φ2=90°, f3=180°, and φ4=270°, for example) so that the phase-shifted signals are spaced apart over T0. The phases can be shifted in a manner similar to the fractional frequency divider approach. The accuracy of the output signal generally increases and the jitter decreases with more phase-shifted signals because there is better time resolution (i.e. the spacing between the phase shifted signals decreases).

In an example, assume it is desired to make Toutequal to 4.85·T0. Control circuit26determines that 4.85·T0is between Tout1=4.75·T0and Tout2=5.0·T0, where 4.75·T0is four reference signal periods and four phase steps and 5.0·T0is five reference signal periods and zero phase steps. If circuit23alternately outputs S(Tout1,Φout1) and S(Tout2,Φout2) an equal number of times over M clock cycles, then Toutwill be 4.875·T0((4.75·T0+5.0·T0)/2=4.875·T0) which is within one phase step of 4.85·T0.

However, if circuit23outputs S(Tout1,Φout1) slightly more, then Toutcan be driven closer to 4.85·T0. This is because the average will be reduced since Tout1is less then Tout2. Tout1can equal Tout2if Toutis an integer multiple of T0. In this case, Tout1and Tout2will also be integer multiples of T0and the jitter will be minimal if toggle circuit23outputs only Tout1or Tout2without alternating between them.

Hence, synthesizer16provides S(Tout,Φout) with a period T0that is an average of Tout1and Tout2. The average can be adjusted by changing SControland SEnableso that Tout1and Tout2are outputted a certain number of times over N clock cycles. If S(Tout1,Φout1) is outputted more, then Toutwill decrease and if S(Tout2,Φout2) outputted more, then Toutwill increase. In this way, the jitter of S(Tout,Φout) can be driven to be on the order of one phase step if Tout1and Tout2are chosen to be within one phase step of T0.

FIG. 5illustrates a more detailed block diagram of synthesizer16illustrated inFIG. 3. InFIG. 5, signal selection circuit21includes a multiplexer and toggle circuit23includes a D-Flip Flop. Control circuit26includes a pre-calculation logic circuit27coupled to a clock synthesizer logic circuit28. Clock synthesizer logic circuit28determines the reference clock cycles and the phase steps to provide S(Tout1, φout1) and S(Tout2, φout2). Circuit21can include other electronic circuitry which can receive multiple input signals and output one of the signals in response to a control signal, but a multiplexer is illustrated here for simplicity. Toggle circuit23can include other toggling circuitry, such as a J-K Flip Flop or a latch which can change the state of its output in response to an input signal.

Precalculation logic circuit27receives M, m, and N and, in response, outputs to logic circuit28P′, P′+1, −N·Q′, and (1−Q′)·N according to the equality given by M·m/N=(P.Q)·m=P′.Q′. M and N are natural numbers and P and Q are integer and decimal numbers, respectively. Hence, M/N is a rational number expressed as a fraction and P.Q is its equivalent expressed as a decimal. P′ is an integer number and Q′ is a decimal number, respectively, of (P.Q)·m, which is the number of phase steps per clock cycle.

Hence, P′ can be the number of phase steps in Tout1and P′+1 can be the number of phase steps in Tout2. Values −N·Q′ and (1−Q′)·N are the error in the number of phase steps over N clock cycles if only S(Tout1,Φout1) or S(Tout2,Φout2), respectively, are outputted. Logic circuit28can provide SEnableand SControlto toggle circuit23and selection circuit21, respectively, so that circuit23selectively outputs S(Tout1,Φout1) and S(Tout2,φout2), as discussed above, in response to signals P′, P′+1, −N·Q′, and (1−Q′)·N. In this way, S(Tout, Φout) is driven to be the average of S(Tout1,Φout1) and S(Tout2,Φout2).

In an example, assume it is desire to make Toutequal to 4.58·T0. This can be rewritten as (458/100)·T0, so that M=458 and N=100. If there are m=32 phase steps per clock cycle, then M·m/N=(P.Q)·m=146.56 phase steps per reference signal period and P′=146 and Q′=0.56. In other words, 14,656 phase steps should be provided for every 100 reference clock cycles (i.e. N=100). In this case, precalculation circuit27will make Tout1=P′=146 phase steps, Tout2=P′+1=147 phase steps, −Q′.N=−56 phase steps, and (1−Q′)·N=44 phase steps.

If Tout1is outputted for N=100 clock cycles, then Toutwill be 14,600 phase steps which is underestimated by −Q′·N=−56 phase steps. If Tout2is outputted for N=100 clock cycles, then Toutwill be 14,700 phase steps which is overestimated by (1−Q′)·N=44 phase steps. Hence, values −Q′·N and (1−Q′)·N are the errors in estimating Toutby Tout1and Tout2, respectively, over mM phase steps. Logic circuit28controls circuits21and23so that they alternately output one of Tout1=146 phase steps and Tout2=147 phase steps in response to logic circuit28so that an average of 14,566 phase steps are outputted after N=100 clock cycles. This will provide an average period of 146.56 phase steps per clock cycle, as desired.

FIG. 6illustrates a simplified block diagram of circuit27. Circuit27includes an A/B divider81where an input A is coupled to signals M and m through a multiplier80. Multiplier80multiplies signal M by m and signal N is provided to input B. Signals N, m, and M can be provided from a memory element included in synthesizer16or they can be provided externally. Divider81forms the ratio m·M/N and outputs P′ and Q′ at respective outputs. An adder84adds one to P′ to provide P′+1. A multiplier83provides signal −Q′·N and a logic circuit82is coupled to divider81to provide signal (1−Q′)·N.

In operation, circuit70determines which signal period, Tout1=P′ or Tout2=P′+1, is outputted to circuit71. This can be done by forming an error signal, denoted as SError, which is equal to the error in the number of phase steps in providing mM phase steps. For example, if the average output period is less than the desired output period (i.e. Tout) then circuit28is underestimating the desired period. In this case, circuit70will output Tout2more to overestimate the period for a certain number of clock cycles so that the average period is increased to the desired period. If the average period is greater than the desired period, then circuit70will output Tout1more to underestimate the desired period for a certain number of clock cycles so that the average period is decreased to the desired period.

Circuit72determines the number of full clock cycles, as indicated by P, that are in Tout1and Tout2. Circuit72can determine the number of clock cycles by counting up, down, or by delaying for a predetermined amount of time before triggering SEnable. SEnableis also provided to toggle circuit23so that it will be triggered at the correct time points to provide S(Tout1,Φout1) and S(Tout2,Φout2) with the correct high-to-low and low-to-high pulse edges as provided by signal selection circuit21.

In response to SEnable, phase selection circuit71determines the number of phase steps as indicated by Q′. The phase steps correspond to the fractional portion of Tout1or Tout2as provided by signal selection circuit70. Circuit71can determine the correct number of phases by counting up, down, or by delaying for a predetermined amount of time. Once the correct number of phases has been determined, circuit71outputs this value to signal selection circuit21as SControland, in response, circuit21outputs the correct phase shifted reference signal.

FIG. 8illustrates a more detailed diagram of clock synthesizer logic circuit28. Signal selection circuit70includes an error register41clocked by Sclock. An output of register41is coupled to an adder64and a comparator circuit43through an adder42. An output of comparator43is coupled to enables of signal selects40and44. Signals −Q′.N and (1−Q′).N are provided to respective inputs of signal select40and signals P′ and P′+1 are provided to respective inputs of signal select44. An output of signal select44is coupled to phase circuit71and an output of signal select40is coupled to the input of register41through adder64.

In operation, register41outputs its stored value during the current clock cycle, which can be zero at start-up. This value is added to −Q′·N (a negative number) by adder42to produce SErrorwhich is then compared to zero. If SErroris less then zero, then signal select40outputs (1−Q′)·N (a positive number) in response to SSelect. Signal (1−Q′)·N is then added to the current stored value in register41and the result is stored in register41during the next clock cycle. The sequence is then repeated and SErrorbecomes less negative until it is greater than zero. During the first clock cycle that SErroris greater than zero, signal select40will output (1−Q′)·N to adder64in response to SSelect. In this way, register41keeps a running total of the number of phase steps and adjusts the total so that m·M phase steps are provided for every N clock cycles.

Phase selection circuit71includes a phase step register45with an input coupled to the output of signal select44. An output of register45is coupled to a delay register46and an adder47. An output of register46is coupled to clock selection circuit72. An output of adder47is coupled to an input of a phase select register51. An output of register51is coupled to its input through adder47and also provides SControlto signal selection circuit21(SeeFIG. 3).

Register45receives P′ or P′+1 from signal select44which are typically in digital form. The bits in P′ or P′+1 that correspond to the clock cycle are outputted by register46to clock selection circuit72. Circuit72includes a signal select57with an output coupled to a clock select register58. An output of register58is coupled to a comparator60and a subtractor61. The output of register46and an output of subtractor61are coupled to respective inputs of signal select57. An output of comparator60is coupled to an enable of signal select57. The output of register46is also coupled to an input of an OR gate63through a comparator59. The output of comparator60is coupled to another input to gate63through an enable register62. Registers58and62are clocked by SClock.

Clock selection circuit72receives the bits in P′ or P′+1 that correspond to the number of clock cycles and counts down to zero from this number during which time SEnableis switched from low to high for one clock cycle. SEnableis outputted to toggle circuit21(SeeFIG. 3) and is also coupled to the enables of registers41,45, and46. In response to SEnablebeing high, phase selection circuit71determines which phase step should be outputted by signal selection circuit21in response to SControl.

Phase selection circuit71determines SControlby receiving the bits that correspond to the phase steps in signals P′ or P′+1 from register45. These bits correspond to the phase step that is to be outputted by signal select circuit21. This value is stored in register51so that it can be added to the phase steps in the next clock cycle when SEnableis high again.

Adder47and register51form a phase select circuit56which can be substituted for by a phase select circuit74, as indicated by substitution arrow73. Circuit74can be used to reduce timing errors when counting phase steps. Circuit73includes an adder52coupled to the output of register51. The output of adder52and the input of register51are coupled to respective inputs of a signal select53. The output of register51and the output of signal select53are coupled to respective inputs of a signal select54. An output of signal select54is coupled to a phase delay register55which provides SControlat its output. The output of register45is also coupled to inputs of comparator48and a comparator49. Outputs of comparators48and49are coupled to respective inputs of an OR gate50. An output of gate50is coupled to an enable of signal select53and an enable of signal select54is coupled to SEnable.

Phase selection circuit74determines SControlby receiving the bits that correspond to the phase steps in signals P′ or P′+1 from register45. These bits are compared to zero by comparator48and to (m/2)−1 by comparator49. If the bits are equal to zero or greater than (m/2)−1, then gate50enables signal select53to output the input of register51to signal select54. This value is then outputted by register55as SControlon the next clock cycle.

However, if the bits are between zero and (m/2)−1, then circuit72counts one fewer clock cycles in response to an indication from register46. In these instances, gate50makes the enable of signal select53low so that m/2 phase steps (i.e. one-half a clock cycle) are added to SControlduring the next clock cycle. The phase steps are then counted as before and SControlis outputted. For example, assume m=32 and it desired to provide 133 phase steps. This corresponds to four clock cycles and five phase steps. Circuit72will count three clock cycles which corresponds to 96 phase steps (3·32 phase steps=96 phase steps). Adder52will then add 16 phase steps to give 112 phase steps and circuit74will count 21 more phase steps to give a total of 133 phase steps, as desired.

Hence, circuit74ensures that SControldoes not count by a number of phase steps less then m/2. This avoids timing errors which can result when counting between one or two phase steps, for example. The timing errors can occur because the probability of missing a clock edge increases as the number of phase-shifted reference signals increases. Hence, the timing errors are significantly reduced when counting a number of phase steps larger than m/2.

FIG. 9illustrates another embodiment of pre-calculation logic circuit27.FIG. 9includes a logic circuit120which receives signal P′ from the output of A/B divider81and logic circuits121and122which receive signals Q′ and N. Logic circuit120provides values P′+2 and P′−1 to respective inputs of a signal select123, P′+1 and P′ to respective inputs of a signal select124, and P′ and P′−1 to respective inputs of a signal select125. Logic circuit122provides (2−Q′)·N and (−1+Q′)·N to respective inputs of a signal select126, (1−Q′)·N and −Q′·N to respective inputs of a signal select127, and −Q′·N and (1−Q′)·N to respective inputs of a signal select128.

In operation, circuit27provides three signals to circuit28to dither between instead of two. The signals can be chosen based on how close −Q′N is to P′ or P′+1 as determined by logic circuit121. For example, if signal −Q′N is closer to P′, then SEnable1is high and the dithering is between P′−1, P′, and P′+1. However, if −Q′N is closer to P′+1, then SEnable1is low and the dithering is between P′, P′+1, and P′+2. By dithering between three signals, low frequency fluctuations in S(Tout,φout) are reduced. For example, if the period is close to P′ and the dithering is only between P′ and P′+1 as discussed in conjunction withFIG. 6, then the period will be P′ for most of the M-m phase steps before it changes to P′+1 for a few phase steps towards the end. This change for only a few phase steps will cause low frequency fluctuation in the period which can increase the signal-to-noise ratio.

FIG. 10illustrates another embodiment of signal selection circuit70. InFIG. 10, circuit70is coupled to pre-calculation circuit27as illustrated inFIG. 9. Signal selection circuit70includes error register41clocked by Sclockwith the output coupled to adder64and comparator circuit43through adder42. The output of comparator43is coupled to enables of signal selects40and44. The output of signal select40is coupled to an input of a signal select75and the output of signal select75is coupled to adder64.

A D flip-flop77has an enable coupled to the enable of register41and a clock terminal coupled to SClock. The inverting output of flip-flop77is coupled to its D input and its non-inverting output is coupled to enables of signal select75and a signal select76. The output of signal select44is coupled to an input of signal select76and the output of signal select76is coupled to circuit71.

Respective inputs of signal select44receive signals P′+2 and P′+1 when SEnable1is low and receive P′−1 and P′ when SEnable1is high. The other input of signal select76receives P′ when SEnable1is low and P′+1 when SEnable1is high. Signals (2−Q′)·N and (1−Q′)·N are provided to respective inputs of signal select40when SEnable1is high and (−1+Q′)·N and −Q′·N are provided when SEnable1is low. Signal −Q′·N is provided to the other input of signal select75when SEnable1is low and (1−Q′)·N is provided when SEnable1is high.

In operation and assuming SEnable1is low, register41outputs its stored value during the current clock cycle, which can be zero at start-up. This value is added to (1−Q′)·N by adder42to produce SErrorwhich is then compared to zero. If SErroris less then zero, then a signal SSelect1is low and signal select40outputs (2−Q′)·N and signal select44outputs P′+2. Signal (1−Q′)·N is then added to the current stored value in register41and the result is stored in register41during the next clock cycle.

When SErrorbecomes greater than zero, SSelect 1will be high and signal selects40and44will output (1−Q′)′N and P′+1, respectively, and the process will repeat. Flip-Flop77behaves as an oscillator which alternately makes a signal SSelect 2and low. In this way, the value outputted to circuit71by signal select76is different for every clock cycle. Hence, the period is moving between three sub-frequencies instead of two so that if the desired period is close to P′ or P′+1, then the circuit will not output these values too many times in a row. It will instead alternate between outputting P′−1, P′, and P′+1 if the period is near P′ or P′, P′+1, and P′+2 if the period is near P′+1. In this way, low frequency oscillations in Toutwill be reduced because the jitter in S (Tout, φout) is always changing.

FIG. 11illustrates a simplified flow diagram100of a method of generating an output signal with a desired period. The method includes a step102of providing phase-shifted reference signals. The phase-shifted reference signals generally have the same period and an equal spacing across the reference signal period. A step104includes generating first and second signals in response to the phase-shifted reference signals. A step106includes a step of outputting one of the first and second signals so that an average period of an output signal is driven to within a predetermined number of phase steps of a desired period.

The first and second signals are typically generated by choosing edges of the reference signals so that the first and second signals have periods which are a certain number of phase steps from the desired period. The first and second signals can be generated by counting periods and/or phase steps in the phase-shifted reference signals. If counting phase steps, then step104can include a step of counting a predetermined minimum number of phase steps to reduce timing errors. This can be done if the phase steps are closely spaced to avoid missing a clock edge.

Step106can include a step of outputting one of the first and second signals in response to an error signal. The error signal can be proportional to the difference between the average and desired periods. The first and second signals can be outputted with periods an integer multiple of the reference clock period or the multiple can be given by P.Q. Hence, the first and second signals can be generated by counting a number of reference signal periods equal to P and a number of phase steps equal to N·Q.

In step106, the first and second signals can be alternately outputted in response to the error signal, where the error signal is typically chosen to drive (P.Q)·m to be M·m/N. Hence, the error signal can be adjusted in response to an indication that M·m/N does not equal (P.Q)·m. To do this, the error signal can be decreased by N·Q phase steps in response to an indication that (P.Q)·m is greater than M·m/N or it can be increased by (1−Q)·N phase steps in response to an indication that (P.Q)·m is less than M·m/N. The error signal is typically adjusted to drive the average period to be within one phase step of the desired period to minimize the jitter in the output signal.

FIG. 12illustrates a simplified flow diagram130of another method of generating the output signal with a desired period. The method includes a step132of providing the phase-shifted reference signals. A step134includes generating first, second, and third signals in response to the phase-shifted signals. The first, second, and third signals can be generated as in method100. A step136includes a step of outputting one of the first, second, and third signals so that the average period of the output signal is driven to within a predetermined number of phase steps of a desired period.

Step136can include a step of providing the second signal with a period greater than the first signal when the desired period is a non-integer multiple of the reference signal period. The period of the third signal can be chosen based on how close the desired period is to P′ or P′+1 phase steps. If the desired period is closer to P′ phase steps, then the third signal can have a period less than P′ and if the desired period is closer to P′+1 phase steps, then the third signal can have a period greater than P′+1. In this way, the first, second, and third signals can be selectively outputted in step136so that the jitter is different in each sequential clock cycle. By changing the jitter, low frequency signals in the desired output signal can be minimized.

Step136can include a step of alternating between outputting the first, second, and third signals in response to the error signal. The error signal can be adjusted in response to an indication that M·m/N does not equal P.Q in a manner similar to method100. Hence, the error signal can be decreased by N·Q or (Q+1)·N in response to an indication that (P.Q)·m is greater than M·m/N. The error signal can also be increased by (1−Q)·N or (2−Q)·N in response to an indication that (P.Q)·m is less than M·m/N.

If the desired period is close to P′, then step136can include a step of adjusting the error signal by one of (Q+1)·N, Q·N, and (N−Q) in response to an indication that M·m is within a predetermined number of phase steps from (P.Q)·m·N. If the desired period is close to P′+1, then step136can include a step of adjusting the error signal by one of Q·N, (1−Q)·N, and (2−Q)·N in response to an indication that M·m is within a predetermined number of phase steps from (P+1)·N·m.

Thus, a frequency synthesizer that can provide an output signal with a period being a multiple of another signal period has been disclosed. The synthesizer can selectively output two or more signals with periods close to the desired period of the output signal. The periods of the signals can be provided by phase shifted reference signals. The signals can be selectively outputted so that the average period of the output signal is driven to the desired period. More than two output signals can be used and dithered between to minimize low frequency signals in the output signal. In this way, the frequency synthesizer can provide less jitter at a given reference frequency.