Radio frequency (RF) amplifier device on silicon-on-insulator (SOI) and method for fabricating thereof

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune device performance and enable higher cut-off frequencies without compromising resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A narrow-highly-doped channel may be formed under a narrow gate extension to improve operating frequencies. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

FIELD OF THE INVENTION

The present invention relates to a semiconductor device. More particularly, the present invention relates to a radio frequency (RF) amplifier device on silicon-on-insulator (SOI) and a method for fabricating thereof.

BACKGROUND OF THE INVENTION

Transistors are frequently used as elements in switches and amplifiers. Silicon-based metal-oxide-semiconductor field effect transistor (MOSFET) technology has been refined for decades to improve high-frequency performance and reduce costs. Silicon MOSFETs are particularly attractive for their relative ease of fabrication and large-scale integration facilitated by the high demand for microprocessors, as well as their power-efficiency compared to older bipolar transistor devices. Variations on conventional low-power MOSFETs used in microprocessors have been developed for use in high-power and high-frequency applications. Improved doping profiles and device geometries may be used to allow for operation at voltages of tens of volts or more. Modified material systems such as silicon-on-insulator technology and III-V semiconductor technology may be used to achieve higher power operation and higher maximum operating frequencies through improved carrier mobility.

There have been continuous development efforts in refining lateral double diffused MOSFET (LDMOS) transistors as the silicon device to meet RF transmitter requirements. An example of LDMOS transistor structure for radio frequency communication shown in the U.S. Pat. No. 7,888,735 features a drift region to provide high breakdown voltages and a split gate dielectric to enhance transconductance to offer improvements over conventional MOSFETs. The inversion channel length variation due to gate to split dielectric alignment causes significant variation in unit gain cut-off frequency (fT). Another split gate device proposed in the U.S. Pat. No. 6,121,666 uses a spacer gate to resolve gate to split dielectric alignment issue, however the lack of critical dimension control due to sloped spacer gate gives rise to variation in performance figures and difficulty in forming reliable subsequent spacer to prevent metal silicide short between spacer gate and source can cause yield loss in mass production. The device lacks structures necessary for high voltage operation such as graded channel well to drift region and thick dielectric on drain side. Therefore, improvements in these areas over the LDMOS transistors is highly desirable.

SUMMARY OF THE INVENTION

This paragraph extracts and compiles some features of the present invention; other features will be disclosed in the follow-up paragraphs. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune device performance and enable higher cut-off frequencies without compromising resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A narrow-highly-doped channel may be formed under a narrow gate extension to improve operating frequencies without significantly increasing gate capacitance

In one aspect, the present invention provides a radio frequency (RF) amplifier device on silicon-on-insulator (SOI) including: a substrate, having a semiconductive region extending below a top surface of the substrate, the semiconductive region having first and second ends opposing one another along a direction parallel to the top surface of the substrate; a first dielectric layer, formed above the semiconductive region of the substrate, having a first thickness; a first gate electrode, disposed on the first dielectric layer over the semiconductive region between the first and second ends; a second dielectric layer, having a second thickness, formed on the top surface of the substrate adjacent to the first dielectric layer below the first gate electrode and near the first end, wherein the second dielectric layer is formed separately after the first dielectric layer is formed; and a second gate electrode, disposed over the second dielectric layer and in electrical contact with the first gate electrode, wherein a sidewall of the second gate electrode opposite the first gate electrode is substantially perpendicular to a top surface of the substrate.

Preferably, the second thickness is not equal to the first thickness.

Preferably, the RF amplifier device further includes a first spacer, formed above the semiconductive region of the substrate and adjacent to the second gate electrode.

Preferably, the RF amplifier device further includes a third gate electrode adjacent to the first gate electrode disposed over the semiconductive region near the second end and separated from the semiconductive region by a third dielectric layer, wherein the third dielectric layer has a third thickness.

Preferably, the second thickness is less than the first thickness and the third thickness; and the first thickness is less than the third thickness.

Preferably, a sidewall of the third gate electrode opposite the first gate electrode is substantially perpendicular to a top surface of the substrate.

Preferably, the RF amplifier device further includes a second spacer, formed above the semiconductive region of the substrate and adjacent to the third gate electrode.

Preferably, a doped source is formed within the semiconductive region at the first end; a doped drain is formed within the semiconductive region at the second end; and a doped channel is formed between the doped source and the doped drain, at least a portion of the doped channel is disposed beneath the first gate electrode and separated from the first gate electrode by the first dielectric layer, the doped channel having a majority carrier type opposite a majority carrier type of the doped source and the doped drain.

Preferably, a doped source well is formed within the semiconductive region at the first end; a doped drain well is formed within the semiconductive region at the second end; and a doped channel is in contact with the doped source well at an end of the doped source well distal from the first end of the semiconductive region, the doped channel well is disposed beneath the second gate electrode and separated from the second gate electrode by the second dielectric layer, the doped channel well has a majority carrier type opposite a majority carrier type of the doped source well and the doped drain well.

Preferably, the RF amplifier device further includes a doped drift region extending within the semiconductive region between the doped channel well and the doped drain well, the doped drift region is disposed beneath the first gate electrode and separated from the first gate electrode by the first dielectric layer, the doped drift region has a majority carrier type opposite the majority carrier type of the doped channel and has a majority carrier density lower than majority carrier densities of the doped channel, the doped source well, and the doped drain well.

Preferably, the RF amplifier device further includes a graded doping profile between the doped channel and the doped drift region.

Preferably, the RF amplifier device further includes an electrically-conductive material formed on the first gate electrode and the second gate electrode to electrically couple the first gate electrode and the second gate electrode.

Preferably, the second dielectric layer is: a thermal oxide layer having the second thickness less than twenty A; or another dielectric layer with the second thickness between fourteen and twenty A.

In another aspect, the present invention provides a method for fabricating the aforementioned RF amplifier device. The method includes the steps of: providing a substrate having a semiconductive region extending below a top surface of the substrate, the semiconductive region having first and second ends opposing one another along a direction parallel to the top surface of the substrate; forming a first dielectric layer above the semiconductive region; disposing a first gate electrode over the semiconductive region between the first and second ends; forming a second dielectric layer having a second thickness on the top surface of the substrate adjacent to the first dielectric layer below the first gate electrode and near the first end; and disposing a second gate electrode over the second dielectric layer.

Preferably, the method further includes after the first gate electrode is disposed and before the second dielectric layer is formed the steps of: forming a third dielectric layer over the first gate electrode and the first dielectric layer; and patterning the first and third dielectric layers to expose the first region of the top surface of the substrate.

Preferably, the method further includes a step of: applying a first dopant to form a first doped volume within a first volume of the substrate corresponding to the first region, the first doped volume having a width determined at least in part by a width of the first region.

Preferably, the method further includes the steps of: forming a first spacer adjacent to the second gate electrode; and applying a second dopant to form a second doped volume within the first doped volume of the substrate, the second doped volume having a width determined by at least a width of the first region, a position of the second gate electrode, and a width of the first spacer; wherein the second doped volume has a majority carrier type opposite to a majority carrier type of the first doped volume.

Preferably, the second gate electrode is formed by the steps of: forming an electrically-conductive layer above the first gate electrode and the first region; and patterning the electrically-conductive layer by an anisotropic reactive ion etching (RIE) process that leaves behind a portion of the electrically-conductive layer on the second dielectric layer to form the second gate electrode, the second gate electrode having vertical sidewalls that are substantially perpendicular to the top surface of the substrate.

Preferably, the electrically-conductive layer is patterned after forming above the first gate electrode and above the first region without forming any layer that acts as a mask defining dimensions of the second gate electrode; and a width of the second gate electrode is defined by an as-formed thickness of the electrically-conductive layer.

Preferably, patterning the electrically conductive layer includes the steps of: forming a protective dielectric material layer above the electrically-conductive layer with a protective layer thickness; and etching the protective dielectric material layer using the anisotropic RIE process; wherein the anisotropic RIE process preferentially etches the protective dielectric layer and the electrically-conductive layer along a direction perpendicular to the top surface of the substrate; wherein the anisotropic RIE process removes the protective dielectric layer with a greater etching rate than an etching rate for the electrically-conductive layer; wherein the protective layer thickness and the anisotropic RIE process are jointly configured such that residual protective dielectric material adheres to a vertical sidewall of the second gate electrode farthest from the first gate electrode that faces the first gate electrode; and wherein the protective layer thickness and the anisotropic RIE process are jointly configured such that residual protective dielectric material adheres to a vertical sidewall of the third gate electrode farthest from the first gate electrode that faces the first gate electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described more specifically with reference to the following embodiments.

It should be understood that the figures are for purposes of illustration and that various elements are not to scale for ease of understanding. Directional references such as “top,” “bottom,” “side,” “above,” “over,” “below” and similar references refer to the orientation of the figures unless explicitly stated and are not meant to require any particular orientation unless explicitly stated.

While conventional silicon and silicon-on-insulator devices are attractive for their low costs and ease of integration with other ubiquitous silicon-based semiconductor devices such as conventional microprocessors, these devices have disadvantages. In particular, conventional silicon devices have limited maximum switching speeds and poor power-handling. The operation frequency of a silicon MOSFET may be tuned by varying structural details such as gate dielectric materials and thicknesses. However, modifications that raise operating frequencies such as thinning the gate dielectric typically result in lower breakdown voltages and other undesirable characteristics such as increased gate-induced drain leakage (GIDL).

Compound semiconductor devices including III-V semiconductor devices (e.g., GaAs, GaN, et al.) can achieve higher operating frequencies and better power handling (i.e., greater current densities) in RF amplifier applications. However, compound semiconductor manufacturing is not as cost effective as silicon-based semiconductor manufacturing. And further, compound semiconductor devices are not readily integrated with pervasive silicon devices. Although silicon-on-insulator (SOI) technologies can improve performance through reduced substrate capacitance and other factors, SOI-based RF devices are still subject to trade-offs between operation frequency, breakdown voltages, and leakage.

Important performance characteristics of MOSFETs include maximum operating frequency (as represented by a unity gain cut-off frequency), various breakdown voltages (e.g., gate-to-drain breakdown, gate-to-source breakdown, gate-to-well breakdown, drain-to-source breakdown), on-state resistance, parasitic capacitance, and so on. For MOSFETs used as amplifiers, derived performance characteristics such as the product of the voltage gain and the operating bandwidth (“gain-bandwidth product”) and the product of the breakdown voltage and cut-off frequency (“BVCEO-Ft product”). Typically, the high gain comes at the expense of operating bandwidth and vice versa. Similarly, high breakdown voltage typically comes at the expense of unity gain cut-off frequency and vice versa. Doping choices and device geometry influence breakdown voltages in addition to other parameters. Another component of device breakdown is the gate dielectric. Thin gate dielectrics may improve on-state resistance, but they are more susceptible to breakdown at high voltage. Thus, in conventional MOSFETs, it is impossible to improve device performance by thinning the gate dielectric without compromising resistance to breakdown at high operating voltages. Other performance characteristics such as gate-induced drain leakage (GIDL) are also subject to trade-offs.

In conventional MOSFET structures, increased drain voltages may cause the depletion region formed at junction between the drain and channel regions to extend beneath the gate electrode, resulting in a shortened effective channel length, lower output resistance, and degraded gain when operated as an amplifier. It is therefore preferable to extend the depletion region into the drain side drift region instead, thereby increasing the breakdown voltage and increasing the output resistance, resulting in higher gain when the MOSFET is operated as an amplifier.

In conventional silicon MOSFETs, switching speeds may be increased by reducing the channel length. In order to avoid drain-induced barrier lowering (DIBL), the channel doping must be increased, which will tend to raise the threshold voltage (Vt) of the device. When the channel doping is increased, the gate dielectric must be made thinner to avoid raising Vt. However, thinning the gate dielectric will typically result in undesired effects such as lowered breakdown voltages and increased GIDL.

Devices and methods disclosed herein allow for increased effective channel doping without the usual unwanted side effects of reduced breakdown voltages, enabling silicon-based RF amplifiers, switches, and other devices that can realize higher operating frequencies than conventional silicon devices (including SOI devices) without suffering from the same compromises in terms of breakdown-free operation at high voltages and other important characteristics. For example, devices and methods disclosed herein can enable RF switches with reduced spurious harmonic generation. Harmonics in MOSFET-based RF switches are associated with gate-induced drain leakage (GIDL). Because GIDL is related to tunneling between energy bands, it increases exponentially with increased voltage. Silicon-based devices with a low GIDL and methods for fabricating such devices according to embodiments disclosed herein are described further below. Such devices may be desirable for their low costs, reduced device sizes, and ease of integration with ubiquitous wireless devices utilized in silicon semiconductor technologies.

Some aspects of the present disclosure are discussed below with reference to example devices and methods for manufacturing such devices. Although certain example devices and methods disclosed herein are discussed in the context of silicon-on-insulator technology, it should be understood that the disclosed improvements may be applied to bulk-silicon-based devices and other device semiconductor platforms.

FIG. 1is a cross-sectional schematic view of an example silicon-on-insulator device100suitable for use as a radio-frequency (RF) amplifier. The device100is a MOSFET fabricated on a SOI substrate110having a buried oxide112with an n-type silicon body120above it. For purposes of illustration, the example device100and other devices are shown as n-channel transistors having n-type source and drain (e.g. the source130and drain135) and a p-type channel (e.g., the p-type well131forming a channel). However, it will be appreciated that methods disclosed herein are equally applicable to fabrication of p-channel transistors by substituting n-type doping for p-type doping and vice versa as appropriate.

A source130may be formed by a highly-doped n-type (n+) well132formed within a p-type-doped p-type well131, which forms a channel together with the n-type body120. A drain135is formed by a highly-doped n-type (n+) well. The device100may be gated by a gate150that includes gate electrodes152,154, and156, each separated from electrical contact with the active regions of the device by one or more dielectrics. The gate electrodes152,154,156may be formed from any combination of materials with suitable electrical conductivity and other properties. In some embodiments, the gate electrodes152,154,156may be formed from highly-doped (including degenerately-doped) polysilicon. Notably, the dielectric thickness between the active region(s) and gate150is different beneath each of the gate electrodes152,154,156. The first dielectric material140and the second dielectric material144may be any suitable material(s) including, as non-limiting examples, silicon dioxide, silicon nitride, cerium oxide, hafnium oxide, et al.). The first dielectric material140may include one or more portions formed at different times (e.g., as indicated by the dashed line inFIG. 3Aand by the spacers343ofFIG. 3F).

As shown (and described further in connection withFIGS. 3A-Ebelow), the gate electrodes152,156are separated from the active regions by the first dielectric material140, while the gate electrode154nearest the source130is separated from the p-type well131by a thinner, second dielectric material144. A suitable electrically-conductive material155(e.g., any suitable metal or metal silicide) acts as a top contact for gate150as well as for source130and drain135. Example of the electrically-conductive material155is such as but not limited to silicide formed with Titanium or Cobalt silicon diffusion salicidation process. Silicide with metal diffusion material such as Nickel is also viable with epitaxial growth of silicon that closes gaps between gates prior to the silicidation process.

In some embodiments, the gate electrodes152,154,156may have substantially vertical sidewalls, forming an angle of approximately 90° with a surface of the active regions, allowing the gate electrodes152,154,156to be used as masks for dopant diffusion during manufacturing of the device100(e.g., as described further in connection toFIGS. 3A-Ebelow).

Compared to a conventional laterally-diffused metal-oxide semiconductor (LDMOS) device, the greater thickness of the first dielectric material140in the region146under the gate electrode156compared to the second dielectric material144can enable higher breakdown voltage by reducing the effective electric fields from the drain135. Meanwhile, the relatively low thickness of the second dielectric material144can enable high gain without substantially compromising the ability of the device100to withstand high applied voltages. The dimensions of the example device100may be chosen to obtain desired performance characteristics. Notably, using methods disclosed herein it is possible to achieve a breakdown-voltage-cutoff-frequency product of at least 150 GHz-Volts in a device similar to the example device100. It will be understood that the thickness of the dielectric material140in the region146under the gate electrode156, the thickness of the dielectric material144, and the thickness of the dielectric material140in the region142under the gate electrode152may be independently tuned to suit various applications.

For instance, the use of a relatively thin dielectric material144enables high transconductance. Meanwhile, choosing a larger thickness for the dielectric material140in region146relative to the thickness of the dielectric material140in region142(together with the lateral dimensions of the gate electrode152) can be used to improve the high-voltage endurance of the device near the drain135. Typically, a thickness of 20 nm for the dielectric material140in the region146with proper drain engineering is sufficient for the example device100to withstand applied drain-to-gate voltages of ˜20V when the dielectric material140is silicon dioxide. Breakdown-free operation at higher voltages is also possible by further increasing the thickness of the dielectric140in the region146underneath the gate electrode156.

The example device100is a modified n-channel laterally-diffused metal-oxide-semiconductor (LDMOS) transistor. When device100is in the active mode, current may travel from the source130to the drain135under an applied drain-source bias voltage. Since the current is carried by electrons, device characteristics may be understood by considering an electron current flowing from the source130to the drain135. The gate electrode154nearest the source130is separated from the p-type channel well131by a thin second dielectric material144that may be made significantly thinner than the thickness of the first dielectric material140under the other gate electrodes152,156in the region142and the region146, respectively. Breakdown voltage may be further improved by separating the channel well131from the drain135with a lightly n-doped body120, resulting in a wide depletion region through which electrons may drift to the drain well135when the device is operated.

In some embodiments, the thin, second dielectric material144has a thickness of or less than 20 Å. The high effective capacitance between the gate electrode154nearest the source130, and the channel well131, can result in a higher carrier concentration there, resulting in lower on-state resistance compared to a conventional LDMOS FET with a uniform gate dielectric. While a similarly reduced on-state resistance may be achieved by thinning the gate dielectric of a conventional device, doing so would result in undesirable increases in leakage currents (due to GIDL) and undesirable decreases in blocking voltage.

Features of the example device100may be further understood using example parameters. For example, the breakdown voltage of the example device100will depend on the depletion region formed near the drain underneath the region146. If the dielectric material146is silicon dioxide with a thickness of 200 Å, and no lightly doped drain (LDD) implant is used for the drain135, the dielectric breakdown voltage may be expected to be at least 20V, allowing safe operation at 15V peak. A drift region is formed under the gate electrode152. During active mode operation in which Vd>Vg the drift region is depleted of carriers near the surface and carriers flow at depth away from the surface. As a result, the effective gate dielectric thickness in the drift region under the gate electrode152is equivalent to the thickness of the dielectric material140in that region plus the depth of the depleted surface region (modified by the appropriate dielectric constants). As a result, the thickness of the dielectric material140in the region142under the gate electrode152may be made thinner to improve the linear mode on-state conductance of the channel. In addition, the pn junction formed between the body120and the p-well131is now gated, thereby enhancing the breakdown voltage and overall BVCEO of the parasitic npn bipolar transistor formed by the n-type source132, the p-type well131and the n-type body120(together with the n-type well at the drain135) which partly limits the high-voltage handling capacity of the example device100. The doping of the p-well131may be in the range of 1.0E18 cm-3, which is considerably higher than typical high-voltage LDMOS devices thanks to the use of the thin dielectric material144. The high doping of the p-well131reduces the injection ratio and current gain of the parasitic BJT and thus improves the breakdown voltage of the example device100.

The dimensions of the example device100may be chosen such that the total drift length from the edge of the drain135to the edge of the p-well131is greater than four times the thickness of the body120in order to nearly eliminate drain induced barrier lowering (DIBL) effects. As a non-limiting example, a thickness of the body region120may be chosen to be 500 Å and a length defining a drift region of ˜200 nm. The lateral distance between the edge of the gate electrode152nearest the drain135and the drain135may be chosen as 100 nm or any other suitable value.

By way of example, a device similar to the example device100may be configured for use as an RF amplifier with a breakdown voltage between 5V and 20V. The thickness of the body120in this example is 50 nm, with a buried oxide of 400 nm beneath it. A length of the first gate electrode152between ˜200 and 1000 nm is desirable for certain applications and will determine the breakdown voltage of the device.

The thickness of the dielectric material142under the central gate152may be chosen to optimize the drain current at the onset of pinch-off, which partially determines the power handling capability of the device100. The thickness of the thin dielectric material144under the second gate electrode154is selected thin for best performance now that high voltage bias is shielded. The thickness of dielectric material in region146on the third gate electrode156is selected to withstand the drain voltages applied during operation of the device.

For certain applications, it is desirable for the cumulative width of the gate electrode152and156to be ˜4× the thickness of the body120to suppress DIBL effects. The width of the gate electrode154and the doping underneath it may be adjusted to set threshold voltage and to tune the on-state resistance. The high-voltage tolerance of the device100may be further increased by using a larger width of the gate electrode156and underneath gate dielectric thickness.

FIG. 2is a cross-sectional schematic view of an example silicon-on-insulator device200(a modified n-channel MOSFET) suitable for use as an RF switch. Although the device200is similar to the device100and may be fabricated using many of the same processing steps, it is optimized for use as a switch rather than an amplifier. For this reason, an ultrathin gate dielectric (e.g., the second dielectric material144ofFIG. 1) is not necessary under gate254. Thus, in example device200, the gate250is separated into the central gate electrode252and two symmetrically-located and dimensioned extension gate electrodes254,256. The gate electrodes252,254,256may be formed from any combination of materials with suitable electrical conductivity and other properties. In some embodiments, the gate electrodes252,254,256may be formed from highly-doped (including degenerately-doped) polysilicon. As will be described below, the dielectric material240is patterned to create a smaller gap between the central gate electrode252and the channel220than between the additional gate electrodes254,256and the channel220. The gate electrodes252,254,256may be electrically coupled (e.g., shorted to each other) by electrically-conductive material255(e.g., the electrically-conductive material155) which may be any suitable metal or metal silicide, and which may also be patterned to form electrical contacts to the source230and the drain235.

By way of example, a device similar to the example device200may be configured for use as an RF switch or an RF antenna tuner with a breakdown voltage between 5V and 20V. The thickness of the body220in this example is 50 nm, with a buried oxide of 400 nm beneath it. A length of the first gate electrode252between ˜50 and 1000 nm is desirable for certain applications. The thickness of dielectric material in the regions244,246under the second and third gate electrodes254,256, respectively is selected to withstand the drain voltages applied during operation of the device and to reduce harmonics due to GIDL thus a thickness higher than 252. For these purposes the thickness of 20 nm for the dielectric layer240in the regions244,246may be suitable. For certain applications it is desirable for the cumulative width of the gate electrodes250to be ˜4× the thickness of the body220to reduce DIBL effects.

Suitable gate electrodes (e.g., the gate electrodes252,254,256) may be polysilicon with a thickness of ˜200 nm, with a spacing of 20 nm between each of the gate electrodes254,256and the gate electrode252.

In the device200, the gap between the central gate252and the extension gate electrodes254,256, considered in isolation might be expected to increase on-state resistance. However, when a conventional FET is over-driven (i.e., Vg>>Vth), carrier mobility often suffers. When the device200is over-driven, the dielectric thicknesses under the gates254,256may be chosen such that the carrier mobility remains normal under the regions244,246, the low GIDL current resulting in low harmonic distortion and higher breakdown voltage than in a conventional device with a modest increase in on-state resistance (˜10-15%) when compared to a conventional transistor without the extension gates254,256as described herein.

FIGS. 3A-3Fare cross-sectional schematic views of an example device300at selected points during an exemplary manufacturing process, provided to illustrate steps in an example process suitable for manufacturing an example device300(e.g., the example device100ofFIG. 1). WhileFIGS. 3A-3Fillustrate fabrication of a device suitable for use as an RF amplifier, it should be understood that the methods disclosed herein are applicable to other devices and other semiconductor technologies (e.g., non-SOI silicon-based devices, compound semiconductor devices, etc.), with appropriate modifications, as discussed below.

As shown inFIG. 3A, a semiconductor substrate310is provided. For purposes of illustration, the substrate310is shown as an SOI wafer with a buried oxide layer312and a silicon body320over the buried oxide312. As shown, the semiconductor substrate310may be provided with a gate electrode352formed above the region body320to form what will become part of a gate structure350(e.g., the gate150ofFIG. 1). As shown the gate electrode352is surrounded by a dielectric material340. In some embodiments, the substrate310may be provided with only a lower dielectric material340A forming the lower portion of the first dielectric material340present (denoted by dashes), in which case an upper dielectric material340B may be formed later. The substrate310is shown as a partially-depleted SOI wafer. However, in some embodiments, a fully-depleted SOI wafer may be used.

In some embodiments, the substrate310may be provided without the first dielectric material340and without the gate electrode352. In such embodiments, a method may include forming the lower portion340A of the first dielectric material340and the gate electrode352using any suitable method. The first dielectric material340may be any suitable material including, as non-limiting examples, various oxides and nitrides (e.g., silicon dioxide, hafnium oxide, cerium oxide, silicon nitride, boron nitride, et al.) and combinations thereof.

As shown inFIG. 3C, the first dielectric material340may be patterned via photolithography and etching, or any other suitable combination of processes to expose the region325on the top surface322of the substrate310next to the gate electrode352. In some embodiments, the first dielectric material340is silicon dioxide and may be patterned by etching areas exposed after photolithographic resist development using a solution of hydrofluoric acid (HF). As shown, the gate electrode352may be used as a hard mask for a dopant implantation362. As shown, the dopant implantation362may create a p-type well331within the body320, which may be lightly n-doped. As will be discussed, part of this volume may form a source well330of a completed device300(as described further below in connection withFIG. 3F). The dimensions of the p-type well331, or at least a portion of its dimensions, may thus be self-aligned to the nearest edge(s) of the gate electrode352.

Due to carrier mobility with the silicon material, the compact device size is necessary to yield desirable high speed RF performance. Prior arts feature split gate structure form split gate oxides followed by aligning a gate structure over the split gate oxide through common alignment target, which render device miniature difficult. The proposed method places the alignment over gate152as shown inFIG. 3Cto effectively eliminate the alignment tolerance burden on device size reduction.

As shown inFIG. 3C, a thin dielectric material344may be formed over the region325. In some embodiments the thin dielectric material344may be silicon dioxide formed using a thermal oxide process. The thickness of the second dielectric material344may be chosen to achieve desired performance characteristics of the device300. In particular, since the dielectric material344will form the gate dielectric between the gate electrode354and the body320of the finished transistor in the region325(as will be described further below), that thickness will at least partially determine the on-state resistance of the device300and its cut-off frequency. As shown, the dielectric material340may be patterned such that the thickness of the dielectric material340is thicker in the region346than in the region344.

In some embodiments, thicknesses as low as realistically achievable without causing shorting may be desirable. Device performance can be tuned to optimize for different characteristics. For instance, as the dielectric material is made thinner, the drive current will increase. Similarly, as the thickness of the dielectric material344is increased, the drive current will be decreased. Any suitable thicknesses of the various dielectric materials may be chosen depending on characteristics desired for a particular application.

For most applications, an oxide layer having a thickness of 16-100 Å may be used for the dielectric material344. It will be appreciated that other materials, including high-K dielectrics, and any other suitable dielectric may be used to further tune desired performance characteristics.

As shown inFIG. 3D, an electrically-conductive layer353may be deposited over the structure ofFIG. 3Cand patterned to form the structure inFIG. 3E. The conductive layer353may be any suitable material including metals and/or highly-doped polysilicon. Notably, the thickness of the conductive layer353may be chosen such that the electrically-conductive layer353can be patterned using anisotropic etching without the need for a separate lithographic step. By choosing a suitably anisotropic etching process (e.g., reactive ion etching at low pressures as a non-limiting example) the portions of the electrically-conductive layer353above the gate electrode352and above the region325, may be removed while leaving portions of the layer353along the sidewall355of the gate electrode352and the sidewall357of the patterned dielectric material340intact, thereby forming the extension gate electrodes354,356(e.g., the gate electrodes154,156of FIG.1). Such non-lithographic processes may be used to produce fine nanometer-scale structures without requiring the expense of additional masks and equipment capable of nanometer (or sub-nanometer) mask alignment. An over etch required to clear layer353residue may cause extension gate electrodes354,356height lower than central gate electrode352.

In some embodiments, to aid in subsequent patterning of the structure ofFIG. 3Dto form the structure ofFIGS. 3E and 3F, a thin oxide layer (e.g., the oxide layer359) or other layer may be deposited over the electrically-conductive layer353as shown inFIG. 3D. When subject to a suitably anisotropic selective etching process (e.g., low-pressure etching in HBr:Cl plasma) that preferentially removes material in a direction perpendicular to the surface of the substrate, this oxide coating protects the sidewalls of the electrically-conductive layer353from etching, resulting in the substantially vertical sidewalls355A,B and357A,B of the respective extension gate electrodes354,356as shown inFIGS. 3E-3F. The protective oxide coating ensures vertical gate electrodes354,356has a consistent dimension, are not shorted to the source or drain doped well in the volume production.

It will be appreciated that the descriptions herein are for the purposes of illustrating key features of embodiments disclosed herein and may omit various well-known processing steps. For instance, in some embodiments where polysilicon is used as a gate electrode material, a liner oxide may be deposited or thermally grown as part of a polysilicon annealing process to drive diffusion of heavy n-type dopants into the polysilicon. Such liner oxide layers may be ˜50-200 Å thick and may be removed by RIE before etching the polysilicon to pattern the gate electrodes. This allows for control of critical dimensions (“CD control”). Subsequent formation of the dielectric spacers343formation prevent shorting of the source and drain to the respective gate electrodes354,356during silicide formation.

As shown inFIG. 3F, dielectric spacers343may be patterned adjacent to the extended gate electrodes354,356. The dielectric spacers343may be used as a hard mask for a dopant implantation process364that may be used to form source and drain wells. As shown the source and drain wells are doped n+. The extents of the source well332and drain well335, as well as the interface between the source well332and the channel well331, and between the drain well335and the body320, may be further defined by one or more thermal annealing steps. In some embodiments in which the gate electrodes354,356are polysilicon, one or more annealing steps may also be used to diffuse dopants within the gate electrodes354,356to ensure that they have sufficient electrical conductivity. In some embodiments, a thermal annealing step may be used to repair etching damage introduced by reactive ion etching of the gate electrodes354,356and additional annealing to further diffuse dopants introduced by the doping process364and/or the doping process362. In some embodiments, the doping profiles of the source, drain, and channel are configured to transition gradually at the interface between the channel well331and the body320, thereby reducing high field gradients associated with abrupt junctions.

Additional conventional steps not shown explicitly may include lateral dopant diffusion to form the arrangement of the doped source and drain regions shown inFIG. 3F, and deposition and patterning of the spacers343, as well as deposition of source and drain contacts which may be formed from a silicide, metal, or any other suitable material. It will be understood that geometries of the doped regions pictured will be altered if fully-depleted SOI is used; for example, the p-type well331and the n-type well forming the drain335may extend to the bottom of the body320at the interface with the buried oxide312.

FIG. 4shows a flow diagram illustrating an example process400for fabricating a transistor (e.g., the example device100). As described below, some or all illustrated features may be omitted in a particular implementation within the scope of the present disclosure, and some illustrated features may not be required for the implementation of all embodiments. The example process400has steps402,404,406,408,410,412,414,416. These steps may be performed by a human operating semiconductor fabrication equipment, automated control systems operating such equipment, or by any combination thereof, described for purposes of illustration as a single “operator.” In some examples, process400may be carried out by any suitable apparatus or means for carrying out the functions or algorithm described below. In some examples, the sequence of steps406and408may be reversed to allow implantation through the oxide.

At step402, an operator provides a substrate having a semiconductive region (e.g., body320ofFIG. 3) extending below a top surface of the substrate. The substrate has first and second ends (e.g., the source330and drain335ofFIGS. 3A-3F) opposing one another along a direction parallel to the top surface of the substrate; a first dielectric material disposed over the semiconductive region (e.g., the lower dielectric material340A ofFIG. 3); and a first gate electrode (e.g., the gate electrode352ofFIG. 3) disposed over the semiconductive region between the first and second ends.

At step404, an operator forms a second dielectric material (e.g., the upper dielectric material340B ofFIG. 3) over the first gate electrode and the substrate. The second dielectric may be silicon dioxide, silicon nitride, or any other suitable dielectric or combinations thereof and may be deposited by sputtering, physical vapor deposition, chemical vapor deposition, or any other suitable method.

At step406, the operator patterns the first and second dielectric materials to expose a first region of the top surface of the substrate (e.g., the region electrode325as shown inFIG. 3C) adjacent to at least a first sidewall of the first gate electrode and near the first end. In some embodiments, patterning the second dielectric material includes first patterning photoresist to create an etch mask. The exposed areas of the second dielectric material as well as the first dielectric material within the first region may be removed using any suitable wet or dry etching process. As one non-limiting example, silicon dioxide may be removed by using a solution of hydrofluoric acid.

At step408, the operator applies a first dopant (e.g., the dopant362shown inFIG. 3C) to the substrate to form a first doped volume within a first volume of the substrate corresponding to the first region. Because the substrate is exposed within the first region, the first doped volume has a width determined at least in part by a width of the first region. The first dopant may be applied using any suitable process(es) including diffusion of dopant from a coated layer or ion implantation. If the transistor is an n-channel transistor, the first dopant is chosen to create a p-doped region. If the transistor is a p-channel transistor, the first dopant is chosen to create an n-doped region.

At step410the operator forms a third dielectric material (e.g., the thin dielectric material344shown inFIG. 3C) on the first region with a thickness less than the thickness of the first dielectric material between the first gate electrode and the top surface of the substrate. The third dielectric may be silicon dioxide, silicon nitride, or any other suitable dielectric or combinations thereof and may be deposited by sputtering, physical vapor deposition, chemical vapor deposition, or any other suitable method. In some embodiments, the third dielectric material may be formed on the first region by using thermal oxidation of the top surface of a substrate in the first region.

At step412, the operator forms a second gate electrode by patterning an electrically-conductive layer (e.g., conductive layer353shown inFIG. 3D, patterned as shown inFIG. 3Eto form the two extension gate electrodes354and356). The electrically conductive layer may be deposited by any suitable processes (e.g., chemical vapor deposition, sputtering, etc.) The second gate electrode is near the first end of the semiconductive region and disposed adjacent to at least the first sidewall of the first gate electrode and disposed over at least a portion of the second dielectric material and the first doped volume. In some embodiments, the second gate electrode may be patterned without the need to perform a lithographic step. For instance, as a non-limiting example, the electrically-conductive layer may be etched via highly anisotropic etching process such as reactive ion etching (RIE) that effectively removes the bulk of the electrically-conductive layer while leaving one or more portions of the electrically-conductive layer intact along sidewalls of the first gate electrode. The width of the second gate electrode may be controlled by choosing an initial thickness of the electrically-conductive layer.

The second gate electrode may be made as narrow as desired down to at least the scale of tens of nanometers without the need to perform high-resolution lithography and high-precision mask alignment. This step may optionally include forming a third gate electrode opposite the second gate electrode along an opposite sidewall of the first gate electrode (and near the second end of the semiconductive region). The second dielectric material need not be removed in the area corresponding to the third gate electrode. As a result, the third gate electrode may be separated from the semiconductive region by a greater thickness of dielectric material than the first gate electrode and/or the second gate electrode (seeFIG. 1for example). A significant benefit of the thick dielectric under the third gate electrode is reduced capacitance between the overall gate structure and the drain (“Cgd”). Reduced Cgd enables higher power gain and higher maximum operation frequencies (as measured by the highest frequency at which the gain is greater or equal to unity power gain). The extended gate structure enables high speed performance without power gain degrade due to high gate resistance Rg seen with conventional narrow gate structure.

At step414, the operator forms a first dielectric spacer adjacent to the second gate electrode (e.g., one of the dielectric spacers343adjacent to the second gate electrode354as shown inFIG. 3F) by patterning a fourth dielectric material. The fourth dielectric material may be any suitable dielectric as previously described and may be deposited and patterned using any suitable process, including reactive-ion etching such as described above in connection to step412. The first spacer may be used as a hard mask for application of a dopant which may be used to form a source well within the first doped volume. Accordingly, at step416, the operator applies a second dopant to the substrate to form a second doped volume (e.g., the n+ well332shown inFIG. 3F) within the first doped volume of the substrate. The second doped volume has a width determined by at least a width of the first region, a position of the second gate electrode, and a width of the first spacer (see, for example,FIG. 3Fand descriptions thereof). Step414may also include forming a second spacer adjacent to the third gate electrode in embodiments that include forming a third gate electrode as described above. In such embodiments, the second spacer may be used as mask through which the second dopant forms a third doped region usable as a drain of the transistor (e.g., see the third gate electrode356, the spacers343, and the drain335ofFIG. 3F). The second dopant is chosen to introduce an opposite majority carrier type as the first dopant such that the source has opposite doping to the channel formed underneath the second gate electrode.

In a further aspect of this disclosure, methods disclosed herein may be but not limited to non-SOI based devices, e.g., as illustrated byFIGS. 5A-5C.FIG. 5Bshows an example device500suitable for use as a low loss power management device having similar features to the example device100ofFIG. 1, fabricated using a conventional bulk semiconductor substrate510. A SOI version is also desirable for compact device isolation and high speed switching to reduce external passive components size. The source well is formed by an n+ doped well533formed within a p-doped well532. A p+ doped well534forms an Ohmic contact to p-doped well532and connect the n-doped source well533. The extended gate electrode554width may be greater than 0.1 um.

A parasitic npn bipolar junction transistor is formed by the n-type well533, the p-type well532, and the n-type substrate510. Leakage current under high voltage operation across the pn junction formed between the p-type body531and n-type body510flow toward the p-well contact534acts as a base current in the parasitic BJT. In a conventional device with a single thick gate dielectric, doping of the p-well532is usually approximately 5.0E16 cm-3 to achieve an acceptable threshold voltage. However, the high p-well resistance may forward bias the pn junction formed between the p-type well532and the n-type source well533, causing failure. Using an extended gate electrode554enabled using a thin dielectric material544, allows much higher dopant concentrations in p-type well532(e.g., ˜1.0E17-1.0E18 cm-3) while retaining low on state resistance (Ron). This reduces the current gain of the parasitic BJT, thereby increasing BVCEO and overall high voltage handling capacity.

Further, the deep lightly-doped p-type body well531can isolate the source well530from the substrate510, which may be doped lightly n-type. The lightly-doped p-type well531increases device breakdown voltage with a suitably large depletion region at the junction with the background doping of the substrate. Meanwhile, the thin dielectric material544enabled by methods disclosed herein allows the p-type well532to be heavily-doped, allowing a low-resistance path for reverse-bias current.

As shown, the n+ doped drain well535is coupled to the source well530through the lightly-doped substrate510and the p-type channel well532. In this arrangement, the portion of the substrate510through which carries flow when the device is operated functions as a drift region, which acts as a depletion mode transistor channel when positively biased via the gate550which comprises a first gate electrode552and a second gate electrode554(similar to the gate electrodes152,154of the device100ofFIG. 1). The isolation trench557may be used to protect gate from high drain voltage where conventional thermal local oxidation (LOCOS) is also preferred for low cost. A large depletion region is formed between the deep p-body531and the n-substrate510. The isolation trench reduces field concentration at the drain. Current is concentrated toward the channel which, together with a thin gate dielectric over the channel reduces the on-state loss while maintaining the high-voltage endurance of device.

Similar to device100, device500has a thin dielectric material544between the gate electrode554and the effective channel, and a dielectric material540in the region542with a greater thickness than that of the dielectric material544between the gate electrode552and the drift region below it. The gate electrodes552,554, and the source well530and drain well535may be provided with electrical contacts by patterning a suitably electrically conductive layer555(e.g., a suitable metal or metal silicide). For purposes of illustration, the example device500is shown as an n-p-n transistor having n-type source and drain wells, and a p-type channel well. However, it will be appreciated that methods disclosed herein are equally applicable to fabrication of p-n-p transistors with a p-type channel by substituting n-type doping for p-type doping and vice versa as appropriate.

FIG. 5Adepicts an example doping procedure useful in the fabrication of the structures shown forming the source well530inFIG. 5B. As shown, a layer of photoresist559is patterned over the structure including the drain well535(not shown), exposing the source well530. An angled dopant implantation560may be used to form the deep p-doped body well531. A second dopant implantation565may be used to form the shallower, more highly doped p-well532. Additional deep implant may be beneficial in further reduce parasitic path resistance. After the resist559is removed, similar processes to those described above in connection toFIGS. 3A-3Fmay be used to complete the fabrication of the device500. The extension gate556and thick dielectric546may replace trench for more compact device shown inFIG. 5C. Additional mask may be patterned to block p-well532implant in drain area535.

Although embodiments have been described herein with respect to particular configurations and sequences of operations, it should be understood that alternative embodiments may add, omit, or change elements, operations and the like. Accordingly, the embodiments disclosed herein are meant to be examples and not limitations.