Semi-embedded trace structure with partially buried traces

Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

BACKGROUND

Field of the Disclosure

Certain aspects of the present disclosure generally relate to electronic components and, more particularly, to semi-embedded trace structures with partially buried traces.

Description of Related Art

A continued emphasis in semiconductor technology is to create improved performance semiconductor devices at competitive prices. This emphasis over the years has resulted in extreme miniaturization of semiconductor devices, made possible by continued advances in semiconductor processes and materials in combination with new and sophisticated device designs. Large numbers of transistors are employed in integrated circuits (ICs) in many electronic devices. For example, components such as central processing units (CPUs), graphics processing units (GPUs), and memory systems each employ a large quantity of transistors for logic circuits and memory devices. To form a packaged assembly, one or more IC dies may be coupled to a rigid substrate or to a flexible substrate, such as an embedded trace substrate (ETS).

SUMMARY

The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description” one will understand how the features of this disclosure provide advantages that include reduction in conductive pattern peeling (e.g., trace, conductive pad, or other conductive element peeling) from a package substrate, such as an embedded trace substrate.

Certain aspects of the present disclosure provide a method of fabricating an embedded trace substrate. The method generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

Certain aspects of the present disclosure provide an embedded trace substrate. The embedded trace substrate generally includes a first dielectric layer and a pattern of conductive traces disposed above the first dielectric layer, wherein lower portions of the conductive traces are buried in the first dielectric layer and wherein upper portions of the conductive traces are exposed above the first dielectric layer.

Certain aspects of the present disclosure provide a packaged assembly. The packaged assembly comprises an embedded trace substrate and an integrated circuit die disposed above the embedded trace substrate. The embedded trace substrate generally includes a dielectric layer and a pattern of conductive traces disposed above the dielectric layer, wherein lower portions of the conductive traces are buried in the dielectric layer and wherein upper portions of the conductive traces are exposed above the dielectric layer. The integrated circuit die has one or more conductive terminals coupled to the upper portions of the conductive traces.

DETAILED DESCRIPTION

Certain aspects of the present disclosure generally relate to semi-embedded trace structures having a pattern of conductive elements that are partially buried.

FIG.1illustrates a cross-sectional view of an example chip package100(also referred to as a “packaged assembly”), in accordance with certain aspects of the present disclosure. As shown, the chip package100includes a substrate102and an integrated circuit (IC) die126disposed above and coupled to the substrate102.

The chip package100may be implemented as a chip scale package, such as a wafer level chip scale package having a package size that is near the die size. For certain aspects, a chip scale package may have package size that is <1.2 times the size of the die and surface mountable. The chip package100may be used to package various electronic circuits, such as a system-on-a-chip (SoC), a modem, a radio frequency front-end (RFFE) circuit, memory, a general purpose processor, a digital signal processor (DSP), an image processor, a graphics processing unit (GPU), a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The IC die126may represent one or more of these or other electronic circuits.

In certain aspects, the substrate102may be a coreless embedded trace substrate (ETS), which may include a plurality of metal layers and one or more dielectric layers disposed between each adjacent pair of metal layers. For example, the dielectric layer(s) may be composed of a pre-impregnated (PPG) dielectric material. Each of the metal layers may include a pattern of conductive elements, such as traces, pads, and/or other shapes. As illustrated inFIG.1, the substrate102has four metal layers131-134and three dielectric layers142-144, but the reader is to understand that the substrate may include more or less than four metal layers and more or less than three dielectric layers. For example, the substrate102may include a first metal (M1) layer131, a second metal (M2) layer132, a third metal (M3) layer133, and a fourth metal (M4) layer134. As shown, the M1 layer131may be the topmost layer and include a plurality of traces106. Furthermore, the M2 layer132may be disposed below the M1 layer131and include a plurality of traces110. Furthermore, the M3 layer133may be disposed below the M2 layer132and include a plurality of traces112. Furthermore, the M4 layer134may be disposed below the M3 layer133and include a plurality of traces114. The substrate102may have conductive pads122on its upper surface for coupling to the IC die with conductive pillars124(e.g., copper (Cu) pillars), bumps, or other suitable structures. The substrate102may also include vias111for connecting the conductive elements of adjacent metal layers (e.g., a trace106in the M1 layer131to a trace110in the M2 layer132).

In certain aspects, the substrate102may include a primer layer104, as shown inFIG.1. A primer layer may be disposed adjacent to one or more of the dielectric layers that compose the substrate102, such as the topmost dielectric layer142and/or the bottommost dielectric layer144. The traces106may be disposed partially within the primer layer104. In other aspects, there may be no primer layer104. In this case, the pattern of traces106may be partially embedded in a material of the substrate102, such as in the topmost dielectric layer142. The primer layer104may be a continuous layer with holes at various locations exposing the conductive pads122.

Layers of solder resist108and116may be applied to the upper and lower surfaces of the substrate102, as shown. For example, a top layer of solder resist108may be arranged above the topmost metal layer to cover the traces in the conductive pattern (e.g., the M1 layer131to cover the traces106). The top layer of solder resist108may have one or more trenches for exposing the conductive pads122. In certain aspects, a bottom layer of solder resist116may be arranged below the bottommost metal layer to cover the traces in the conductive pattern (e.g., the M4 layer134to cover the traces114). The bottom layer of solder resist116may also have trenches for exposing conductive pads118(e.g., under-bump metallization) in the bottommost layer for coupling to an electronic component via solder balls120.

Traces disposed on a surface of an embedded trace substrate may experience peeling from the substrate. In other words, the traces may peel away from the substrate and may become disconnected, causing an open circuit.

Example Semi-Embedded Trace Structures

Certain aspects of the present disclosure generally relate to semi-embedded trace structures having a pattern of conductive elements (e.g., traces) that are partially buried in a substrate (e.g., an embedded trace substrate), which may enable a more secure attachment of the conductive elements to the substrate. Having such partially buried conductive elements may lead to improved reliability of the traces (and other conductive elements) in the structure. In particular, the more secure attachment of conductive elements may allow handheld and other portable devices to pass drop tests more easily, since the traces may not peel off from the substrate within a packaged assembly incorporated in the device. Accordingly, certain aspects of the present disclosure relate to mechanically pressing traces (and other conductive elements) into a dielectric layer to reduce the probability of the traces peeling.

Aspects of the present disclosure may be applicable to package assemblies, such as processors, memory, and/or power management dies in high lead count ball grid array (BGA) packages used in handheld devices or tablets, where fine ball pitches may be utilized. In particular, aspects of the present disclosure may be used for both wire-bond (WB) and flip chip (FC) BGA packages and for packages of one or more dies (including stacks of dies).

FIG.2Adepicts a cross-sectional view of an example embedded trace substrate200, in accordance with certain aspects of the present disclosure. In certain aspects, the embedded trace substrate200may include a dielectric layer202. The dielectric layer202may comprise a dielectric material, such as pre-impregnated composite fibers, also referred to as prepreg or PPG. The embedded trace substrate200may further include a primer layer204disposed above the dielectric layer202. In certain aspects, the embedded trace substrate200may have one or more traces206A,206B,206C (collectively referred to herein as “traces206”) partially buried in the primer layer204. For example, the traces206may be partially buried in the primer layer204by being mechanically pressed into the primer layer. The traces206may comprise copper (Cu), platinum (Pt), silver (Ag), gold (Au), aluminum (Al), or any other suitable material.

In certain aspects, each of the traces206may be partially buried (e.g., implanted) in the primer layer to a depth. For example, trace206A may be partially buried in the primer layer204to a depth208A. Similarly, trace206B may be partially buried in the primer layer to a depth208B, and trace206C may be partially buried in the primer layer to a depth208C. The depths208A,208B, and208C may be collectively referred to herein as “depths208.” The depths208may be equal, or at least some of the depths208may vary in whatever combination of implanted depths may be suitable. For example, each of the traces206may be partially buried into the primer layer204to a depth208of 2 to 7 μm. In certain aspects, the depth(s)208may be less than 2 μm, while in other aspects the depth(s)208may be more than 7 μm.

FIG.2Bdepicts a partial isometric view of the example embedded trace substrate200, in accordance with certain aspects of the present disclosure. In certain aspects, the primer layer204may not cover an entire surface (e.g., top) of the dielectric layer202(e.g., the topmost dielectric layer of the embedded trace substrate200). Alternatively, the primer layer204may cover the entire top of the dielectric layer202, at least other than trenches for conductive pads.

FIG.3Adepicts a cross-sectional view of an example embedded trace substrate300A, in accordance with certain aspects of the present disclosure. In certain aspects, the embedded trace substrate300A may include a dielectric layer302. The dielectric layer302may comprise a dielectric material such as prepreg. However, unlike the embedded trace substrate200ofFIGS.2A and2B, the embedded trace substrate300A ofFIG.3Adoes not include a primer layer. Rather, the embedded trace substrate300A may have one or more traces304A,304B, and304C (collectively referred to herein as “traces304”) partially buried in the dielectric layer302. For example, the traces304may be partially buried in the dielectric layer302by being mechanically pressed into the dielectric layer302. The traces304may comprise copper, platinum, silver, gold, aluminum, or any other suitable material.

In certain aspects, each of the traces304may be partially buried (e.g., implanted) in the dielectric layer302to a depth. For example, trace304A may be partially buried in the dielectric layer302to a depth306A. Similarly, trace304B may be partially buried in the dielectric layer302to a depth306B, and trace304C may be partially buried in the dielectric layer302to a depth306C. The depths306A,306B, and306C may be collectively referred to herein as “depths306.” The depths306may be equal, or at least some of the depths306may vary in whatever combination of implanted depths may be suitable. For example, each of the traces304may be partially buried in the dielectric layer302to a depth306of 2 to 7 μm. In certain aspects, the depth(s)306may be less than 2 μm, while in other aspects the depth(s)306may be more than 7 μm.

FIG.3Bdepicts an isometric view of an example embedded trace substrate300B, in accordance with certain aspects of the present disclosure. The embedded trace substrate300B may be similar in construction to the embedded trace substrate300A ofFIG.3A. However, the view of the embedded trace substrate300B inFIG.3Bdepicts multiple dielectric and metal layers arranged in multiple laminate layers. For example, the embedded trace substrate300B may include a lower laminate layer310and an upper laminate layer303. Within the lower laminate layer310may be a dielectric layer311and buried traces318,320,322, and324. The upper laminate layer303may include a dielectric layer305and both fully buried traces and partially buried traces. For example, in the upper laminate layer303, traces312,314, and316may be fully buried and form a metal layer at a lower surface of the dielectric layer305, while traces307,308, and326may be partially buried at an upper surface of the dielectric layer305to form another metal layer. For certain aspects, the laminate layers303,310may comprise .Ajinomoto build-up film (ABF).

Example Fabrication Processes

FIG.4Ais a cross-sectional view400A of an exemplary fabrication operation of an embedded trace substrate (e.g., the embedded trace substrate200), in accordance with certain aspects of the present disclosure. As shown, the dielectric layer202may be formed with the primer layer204disposed above the dielectric layer202. In certain aspects, the primer layer204may not be fully cured at the stage depicted inFIG.4A. Fabrication of the embedded trace substrate may continue by disposing at least one of the traces206above the primer layer204. At the stage depicted, the traces206may be disposed entirely above the primer layer204, but may be resting on the upper surface of the primer layer.

In a subsequent exemplary operation depicted in the cross-sectional view400B ofFIG.4B, the traces206may be mechanically pressed down (e.g., by a plate402of a mechanical press or other object) to partially bury (e.g., implant) each of the traces206into the primer layer204to the depths208. During the mechanical pressing, the primer layer204may be partially cured. In certain aspects, the plate402may be shaped such that the depths208are substantially equal. Alternatively, the plate402may be shaped such that at least some of the depths208may vary. For example, the portion of the plate402in contact with the trace206A may have a different thickness compared to another portion of the plate402in contact with the trace206C. The difference in thickness may cause the traces206A and206C to be partially buried to depths such that the depth208A is not equal to the depth208C.

In another subsequent exemplary operation depicted in the cross-sectional view400C ofFIG.4C, an insulative material404may be formed above the primer layer204and the partially buried traces206. The insulative material404may comprise solder resist, for example, such as the solder resist108or116ofFIG.1. In certain aspects, the insulative material404may be formed after the primer layer204has fully cured. In other aspects, the insulative material404may be formed before the primer layer204has fully cured. In still other aspects, the insulative material404may be partially formed before the primer layer204has fully cured, and fully formed after the primer layer204has fully cured. By forming the insulative material404after the primer layer204is fully cured, the traces206may be less subject to lateral forces and less likely to peel than traces206of an embedded trace substrate200in which the insulative material404is formed before the primer layer204has fully cured.

FIG.5Ais a cross-sectional view500A of an exemplary fabrication operation of an embedded trace substrate (e.g., the embedded trace substrate300A), in accordance with certain aspects of the present disclosure. As shown, the dielectric layer302may be formed without a primer layer disposed thereabove. Fabrication of the embedded trace substrate may continue by disposing at least one of the traces304above the dielectric layer302. At the stage depicted, the traces304may be disposed entirely above of the dielectric layer302, such as resting on an upper surface of the dielectric layer.

In a subsequent exemplary operation depicted in the cross-sectional view500B ofFIG.5B, the traces304may be mechanically pressed down (e.g., by the plate402) to partially bury (e.g., implant) each of the traces304in the dielectric layer302to the depths306. In certain aspects, the plate402may be shaped such that the depths306are substantially equal. Alternatively, the plate402may be shaped such that at least some of the depths306associated with various traces may be different. For example, the portion of the plate402in contact with the trace304B may have a different thickness compared to another portion of the plate402in contact with trace304C. The difference in thickness may cause the traces304B and304C to be partially buried to depths such that the depth306B is not equal to the depth306C.

In another subsequent exemplary operation depicted in the cross-sectional view500C ofFIG.5C, an insulative material404may be formed above the dielectric layer302and the partially buried traces304.

FIG.6is a flow diagram of example operations600for fabricating an embedded trace substrate (e.g. the embedded trace substrate200depicted inFIG.2Aor the embedded trace substrate300A portrayed inFIG.3A), in accordance with certain aspects of the present disclosure. The operations600may be performed by a semiconductor fabrication facility (also referred to as a foundry), for example.

The operations600may begin at block605by creating a pattern of conductive traces (e.g., the traces206or the traces304) above a dielectric layer (e.g., the dielectric layer302or the dielectric layer202plus the primer layer204). The dielectric layer may be formed before the pattern of conductive traces is created.

At block610, the operations600may continue by mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer (e.g., as shown inFIG.4BorFIG.5B). In other words, the conductive traces may be partially buried (i.e., not fully buried) in the dielectric layer.

In certain aspects, the dielectric layer is partially cured during the mechanically pressing of block610. For example, the dielectric layer being partially cured may allow the conductive traces to become partially embedded in the dielectric layer, but may provide some structural stability such that the traces do not shift while the dielectric layer is curing. In other aspects, the operations600may further include curing the dielectric layer after the lower portions of the conductive traces are buried in the dielectric layer.

In certain aspects, the dielectric layer comprises Ajinomoto build-up film (ABF).

In certain aspects, the dielectric layer comprises a primer layer (e.g., the primer layer204). Additionally, the operations600may further include forming the primer layer above at least a portion of another dielectric layer (e.g., the dielectric layer202) before creating the pattern of conductive traces. In certain aspects, the other dielectric layer comprises a pre-impregnated (prepreg) material.

In certain aspects, the lower portions of the conductive traces are buried in the dielectric layer to a depth (e.g., depths208) between 2 and 7 μm inclusive.

In certain aspects, the pattern of conductive traces resides in a first metal layer (e.g., the M1 layer131) of the embedded trace substrate. In certain aspects, the operations600may further include forming a second metal layer below the dielectric layer (e.g., the M2 layer132). In this case, the operations600may further include forming another dielectric layer (e.g., the dielectric layer142) below the second metal layer.

The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using hardware, for example.

One or more of the components, steps, features, and/or functions illustrated herein may be rearranged and/or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from features disclosed herein. The apparatus, devices, and/or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein.