Per die voltage programming for energy efficient integrated circuit (IC) operation

Methods and apparatus to provide per die voltage programming for energy efficient integrated circuit (IC) operation are described. In some embodiments, the voltage potential supplied to an IC component is lowered below a peak performance voltage level, e.g., to reduce power consumption by the component. Other embodiments are also described.

BACKGROUND

The present disclosure generally relates to the field of electronics. More particularly, some embodiments of the invention relate to per die voltage programming that may provide energy efficient integrated circuit (IC) operation.

As integrated circuit fabrication technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of these functionalities increases, however, so does the number of components on a single IC chip. Additional components add additional signal switching, in turn, generating more heat. The additional heat may damage an IC chip by, for example, thermal expansion. Also, the additional heat may limit usage locations and/or applications of a computing device that includes such chips. For example, a portable computing device may solely rely on battery power. Hence, as additional functionality is integrated into portable computing devices, the need to reduce power consumption becomes increasingly important, for example, to maintain battery power for an extended period of time. Non-portable computing systems also face cooling and power generation issues as their IC components use more power and generate more heat.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of some embodiments. However, some embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, or circuits have not been described in detail so as not to obscure the particular embodiments of the invention. Moreover, various aspects of embodiments of the invention may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware, software, or some combination thereof.

Some of the embodiments discussed herein may provide efficient techniques for reducing the voltage potential supplied to an IC component, e.g., to reduce power consumption or provide energy efficiency. Such techniques may allow for thermally optimized product distribution of IC components that may be sold or distributed based on predefined frequency boundaries (e.g., divided into frequency bins). Furthermore, some of the embodiments discussed herein may be applied in various computing systems, such as the computing systems discussed with reference toFIGS. 1,5, and6. More particularly,FIG. 1illustrates a block diagram of a computing system100, according to some embodiments. The system100may include one or more domains102-1through102-M (collectively referred to herein as “domains102” or “domain102”). Each of the domains102-1through102-M may include various components (e.g., including one or more transistors or other electronic circuit elements such as one or more resistors, capacitors, inductors, etc.). For clarity, sample components are only shown with reference to domains102-1and102-2. Also, each domain102may correspond to one or more portions of a computing system (such as the components discussed with reference toFIGS. 5 and 6). In some embodiments, each of the domains102may include various circuitry (or logic) that is clocked by a clock signal which may be the same or different from the clock signal used in other domains. In some embodiments, one or more of the clock signals may be mesosynchronous, or otherwise related (e.g., with a relationship that may or may not repeat itself over time).

In some embodiments, each domain may communicate data with other domains through one or more buffers104. In some embodiments, the buffers104may be first-in, first-out (FIFO) buffers. Each domain may include one or more programmable voltage supplies (e.g.,106-1and106-2, and more generally referred to herein as the “voltage supply106” or “voltage supplies106”), one or more storage devices to store one or more voltage values (such as device(s)108-1and108-2shown with reference to domains102-1and102-2, respectively), and/or other power or energy consuming circuitry (such as logics110-1and110-2shown with reference to domains102-1and102-2, respectively, and generally referred to herein as “logic110” or “logics110”). The voltage supplies106may be any type of a voltage supply such as a high frequency mode (HFM) voltage supply or a switched-mode power supply (SMPS).

In some embodiments, the stored voltage values for each domain may be different than voltage values for other domains. As will be further discussed herein, e.g., with reference toFIG. 4, the voltage values stored in devices108may be used to adjust the output voltage level of the corresponding voltage supply106, e.g., to provide reduced power or energy consumption while maintaining the corresponding IC component (e.g., provided in domains102) operationally within a preset frequency bin. In some embodiments, the voltage values stored in devices108may be provided as one or more bits. For example, in systems with multiple power states, one or more bits may indicate the appropriate voltage value to which the corresponding supply106is to be tuned for each power state. Furthermore, in some embodiments, the value(s) stored in devices108may be determined during high volume manufacturing (HVM) testing. Moreover, in some embodiments, the voltage values stored in devices108may be an optimal (e.g., the minimum possible) voltage value for a given IC component in order to yield sufficient volume to a given frequency bin with minimized power or energy consumption. Also, any type of a memory device such as those discussed with reference toFIGS. 5 and 6may be utilized to provide the storage devices108, including a non-volatile storage device such as on-die fuse(s).

FIG. 2illustrates a graph200of thermal design power (TDP) versus frequency, according to some embodiments. In some embodiments, the graph200shows that energy or power efficient IC components may be provided through adjustment of supply voltage such as discussed with reference toFIG. 1. More particularly, IC components may be divided into one or more frequency bins202-1through202-Z (generally referred to herein as “bins202”) in accordance with valid bin frequency boundaries204boundaries. For example, in bin202-1, components206A and208A are shown at their peak (or maximum) performance configuration frequency and TDP, e.g., such as determined during testing. For example, components206A and208A may operate in accordance with a peak performance voltage level that corresponds to a voltage level which allows the components to operate successfully (e.g., without (or with limited) errors or failures) at peak operational speed. As discussed with reference toFIG. 1, supply voltage to the components206A and208A may be reduced to an optimal (e.g., minimum) level while maintaining these components in the same bin (202-1). Alternatively, the supply voltage to the components206A and208A may be modified such that these components move into a different bin.

As shown inFIG. 2, components206A and208A may be moved further down on the TDP axis (e.g., resulting in reduced power or energy usage) as shown by the resulting components206B and208B, respectively. Similarly, as shown in bin202-Z, components210A may be moved down on the TDP axis to components210B, e.g., to provide components that are still in the same bin (202-Z) while consuming less power or energy. As discussed with reference to components206A and208A, the supply voltage to the components210A may be modified such that one or more of these components move into a different bin in some embodiments. As can be readily seen inFIG. 2, the TDP limit212may also be lowered in accordance of some of the embodiments discussed herein, in part, because the resulting components (e.g., components206B,208B, and/or210B) will be consuming less power or energy.

FIG. 3illustrates a block diagram of a processor core300, according to some embodiments. In some embodiments, the core300may represent various components that may be present in a processor or number of processors (such as those discussed with reference toFIGS. 5 and 6). The processor core300may include one or more domains such as a second level cache domain302, a frontend domain304, and one or more backend domains306. Components within each of the domains302,304, and306may be supplied by a different programmable voltage supply106such as discussed with reference toFIG. 1. Moreover, each of the domains (e.g.,302,304, and306) may include more or less components than those shown inFIG. 3in some embodiments.

The second level (L2) cache domain302may include an L2 cache308(e.g., to store data including instructions), device(s)108, and programmable voltage supply106. In some embodiments, the L2 cache308may be shared by multiple cores in a multi-core processor such as those discussed with reference toFIGS. 5 and 6. Also, the L2 cache308may be off of the same die as the processor cores. Accordingly, in some embodiments of the invention, a processor may include the domains304and306, and may or may not include the L2 cache308.

As shown inFIG. 3, the frontend domain304may include one or more of the device(s)108, voltage supply106, a reorder buffer318, a rename and steer unit320, an instruction cache322, a decode unit324, a sequencer326, and/or a branch prediction unit328. In some embodiments, the frontend domain304may include other components such as an instruction fetch unit.

The backend domains306may include one or more of a first level (L1) cache domain328and one or more execution domains330-1through330-N. The L1 cache domain328may include an L1 cache332(e.g., to store data including instructions), the device(s)108, and voltage supply106. Furthermore, the execution domains330-1through330-N may include one or more of an integer execution unit and/or a floating point execution unit. The execution domains330-1through330-N may each comprise an issue queue (338-1through338-N, respectively), a register file (340-1through340-N, respectively), the device(s)108, voltage supply106, and/or an execution unit (346-1through346-N, respectively).

In some embodiments, each of the domains302,304, and306may include one or more first-in, first-out (FIFO) buffer(s)348to synchronize communication between the various domains (e.g., between the domains302,304, and/or306).

Additionally, the processor core300(and, in some embodiments, such as the one shown inFIG. 3, the backend domains306) may include an interconnection or bus350to facilitate communication between various components of the processor core300. For example, after an instruction is successfully executed (e.g., by the execution domains330-1through330-N), the instruction commit may be communicated to the ROB318(e.g., via the interconnection350) to retire that instruction. Additionally, the domains within the backend (e.g., domains328and330-1through330-N) may communicate via the interconnection350. For example, communication among execution units (330-1through330-N) may occur for type conversion instructions. Further operations of components ofFIGS. 1-3will be discussed with reference to the method400ofFIG. 4.

Furthermore, even thoughFIG. 3illustrates that each of the domains302,304, and306may include the device(s)108and voltage supply106, various domains may share the same device(s)108and/or the voltage supply106. For example, a single set of the device(s)108and voltage supply106may be utilized for some or all domains of the processor core300.

FIG. 4illustrates a flow diagram of a method400to generate supply voltage in accordance with stored voltage value(s), according to some embodiments. In some embodiments, the operations of the method400may be performed by one or more components, such as the components discussed with reference toFIGS. 1-3and5-6. Also, some of the operations discussed with reference toFIG. 4may be performed by hardware, software, or combinations thereof. Furthermore, an external device such as a circuit analyzer or testing device may be used to perform various operations discussed with reference to the method400.

Referring toFIGS. 1-4, at an operation402, an IC component may be tested at a select voltage supply level after manufacturing. For example, the voltage supply106may be programmed to supply one of the components discussed with reference toFIGS. 1-3and/or5-6with a select voltage level. At operations404and406, the power leakage and dynamic capacitance of the component of operation402may be determined, e.g., by a circuit analyzer or testing device. At an operation408, the corresponding TDP value of the component may be determined in accordance with the following equation:
TDP=(Cdyn*Voltage2*Frequency)+Leakage

In the above equation, TDP corresponds to the thermal design power, Cdyncorresponds to the measured value of the dynamic switching capacitance of the silicon die when executing a realistic worst case (high power) application, Voltage corresponds to the voltage level of operation402(or operation412as will be discussed further below), Frequency corresponds to the bin frequency, and Leakage corresponds to the measured leakage power. In some embodiments, a lookup table may be utilized to look up the TDP value based on stored values of voltage, frequency, power leakage, capacitance, etc.

At an operation410, it is determined (e.g., based on the TDP value of operation408) whether the tested component yields to a select frequency bin. As discussed with reference toFIGS. 1-2, the voltage supply (e.g., used to test the component at operation402) provided to a component may be lowered to reduce the TDP of the component and as a result of the component may successfully operate in accordance with a selected frequency (e.g., corresponding to a frequency bin). Hence, operation410may determine whether the test component fits into a predefined frequency bin. If the component fails to yield to a select frequency bin, at an operation412, the component may be tested at a next voltage supply level (which may be lower or higher than the voltage supply level of the previous test, e.g., at a previous operation402or412).

At an operation414, e.g., once the operation410determines that the tested component yields to a select frequency bin, the determined TDP of operation408may be compared with select TDP limit(s). The TDP limits of operation414may correspond to various environments or applications where the component is to be utilized. For example, components used for mobile devices may have a different TDP limit (e.g., lower TDP value) at operation414than components used in desktop or server computing environments. Other types of product differentiation criteria may be utilized to determine the frequency at operation410and/or the TDP value at operation414, such as pricing per sector, country of usage, available cooling solutions, acoustic specifications, form factor, etc.

If a component fails to comply with the TDP limit(s) at operation414, the method400may resume at operation412. Otherwise, the voltage value corresponding to the successful performance of operations410and414may be stored (e.g., in the device(s)108) at operation416. The stored values of operation416may be utilized at an operation418(e.g., by the programmable voltage supplies106) to generated supply voltages for the corresponding component during operation.

In some embodiments, the voltage values stored in devices108at operation416may be provided as one or more bits. For example, in systems with multiple predefined power states, one or more bits may indicate the appropriate voltage value to which the corresponding supply106is to be tuned at operation418, e.g., for each power state. Further, in some embodiments, one or more of the operations402-416may be performed by a computing device (such as those discussed with reference toFIGS. 5-6) through software, hardware, or combinations thereof.

FIG. 5illustrates a block diagram of a computing system500in accordance with some embodiments of the invention. The computing system500may include one or more central processing unit(s) (CPUs)502or processors that communicate via an interconnection network (or bus)504. The processors502may be any type of a processor such as a general purpose processor, a network processor (that processes data communicated over a computer network503), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, the processors502may have a single or multiple core design. The processors502with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors502with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors. In some embodiments, one or more of the processors502may utilize the embodiments discussed with reference toFIGS. 1-4. For example, one or more of the processors502may include one or more processor cores (300). Also, the operations discussed with reference toFIGS. 1-4may be performed by one or more components of the system500.

A chipset506may also communicate with the interconnection network504. The chipset506may include a memory control hub (MCH)508. The MCH508may include a memory controller510that communicates with a memory512. The memory512may store data and sequences of instructions that are executed by the CPU502, or any other device included in the computing system500. In some embodiments of the invention, the memory512may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or the like. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via the interconnection network504, such as multiple CPUs and/or multiple system memories.

The MCH508may also include a graphics interface514that communicates with a graphics accelerator516. In some embodiments of the invention, the graphics interface514may communicate with the graphics accelerator516via an accelerated graphics port (AGP). In some embodiments of the invention, a display (such as a flat panel display) may communicate with the graphics interface514through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.

A hub interface518may allow the MCH508to communicate with an input/output control hub (ICH)520. The ICH520may provide an interface to I/O devices that communicate with components of the computing system500. The ICH520may communicate with a bus522through a peripheral bridge (or controller)524, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or the like. The bridge524may provide a data path between the CPU502and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH520, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with the ICH520may include, in some embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or the like.

The bus522may communicate with an audio device526, one or more disk drive(s)528, and a network interface device530(which communicates with the computer network503). Other devices may be in communication with the bus522. Also, various components (such as the network interface device530) may be in communication with the MCH508in some embodiments of the invention. In addition, the processor502and the MCH508may be combined to form a single chip. Furthermore, the graphics accelerator516may be included within the MCH508in other embodiments of the invention.

Furthermore, the computing system500may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g.,528), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media capable of storing electronic instructions and/or data.

FIG. 6illustrates a computing system600that is arranged in a point-to-point (PtP) configuration, according to some embodiments of the invention. In particular,FIG. 6shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces. The operations discussed with reference toFIGS. 1-5may be performed by one or more components of the system600.

As illustrated inFIG. 6, the system600may include several processors, of which only two, processors602and604are shown for clarity. The processors602and604may each include a local memory controller hub (MCH)606and608to allow communication with memories610and612. The memories610and/or612may store various data such as those discussed with reference to the memory512.

The processors602and604may be any type of a processor such as those discussed with reference to the processors502ofFIG. 5. The processors602and604may exchange data via a point-to-point (PtP) interface614using PtP interface circuits616and618, respectively. The processors602and604may each exchange data with a chipset620via individual PtP interfaces622and624using point to point interface circuits626,628,630, and632. The chipset620may also exchange data with a high-performance graphics circuit634via a high-performance graphics interface636, using a PtP interface circuit637.

At least some embodiments of the invention may be provided within the processors602and604. For example, one or more of the domains102discussed with reference toFIG. 1and/or processor core(s)300may be located within the processors602and604. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system600ofFIG. 6. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated inFIG. 6.

The chipset620may communicate with a bus640using a PtP interface circuit641. The bus640may have one or more devices that communicate with it, such as a bus bridge642and I/O devices643. Via a bus644, the bus bridge643may be in communication with other devices such as a keyboard/mouse645, communication devices646(such as modems, network interface devices, etc. that may be in communication with the computer network503), audio I/O device, and/or a data storage device648. The data storage device648may store code649that may be executed by the processors602and/or604.

In some embodiments of the invention, the operations discussed herein, e.g., with reference toFIGS. 1-6, may be implemented by hardware (e.g., circuitry), software, firmware, microcode, or combinations thereof, which may be provided as a computer program product, e.g., including a machine-readable or computer-readable medium having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein. Also, the term “logic” may include, by way of example, software, hardware, or combinations of software and hardware. The machine-readable medium may include a storage device such as those discussed with respect toFIGS. 1-6. Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection). Accordingly, herein, a carrier wave shall be regarded as comprising a machine-readable medium.

Reference in the specification to “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least an implementation. The appearances of the phrase “in some embodiments” in various places in the specification may or may not be all referring to the same embodiments.