STACKED FETs WITH BACKSIDE ANGLE CUT

A semiconductor structure is provided that includes a first stacked FET cell including a second FET stacked over a first FET, and a second stacked FET cell located adjacent to the first stacked FET cell and including a fourth FET stacked over a third FET. The structure further includes a first backside source/drain contact structure located beneath the first stacked FET cell and contacting a source/drain region of the first FET, a second backside source/drain contact structure located beneath the second stacked FET cell and contacting a source/drain region of the third FET, and an angled cut region laterally separating the first backside source/drain contact structure from the second backside source/drain contact structure.

BACKGROUND

The present application relates to semiconductor technology, and more particularly to a semiconductor structure including stacked field effect transistors (FETs) having improved cell height scaling.

Stacking of FETs is an attractive architecture for future complementary metal oxide semiconductor (CMOS) scaling, and potentially for ultimately scaled technology. By directly stacking FETs one over the other (for example, pFETs over nFETs, nFETs over pFETs, pFETs over pFETs, or nFETs over nFETs) significant area scaling can be achieved.

SUMMARY

In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a first stacked FET cell including a second FET stacked over a first FET. The structure further includes a second stacked FET cell located adjacent to the first stacked FET cell and including a fourth FET stacked over a third FET. The structure even further includes a first backside source/drain contact structure located beneath the first stacked FET cell and contacting a source/drain region of the first FET, a second backside source/drain contact structure located beneath the second stacked FET cell and contacting a source/drain region of the third FET, and an angled cut region laterally separating the first backside source/drain contact structure from the second backside source/drain contact structure.

DETAILED DESCRIPTION

In stacked FETs, backside power rails and backside power distribution networks can greatly improve the routablity of the stacked FETs. However, when backside contacts need to be wired not only to the backside interconnects, but also to the frontside interconnects, the space for the routing can become tight. The present application address this issue.

Referring first toFIG.1, there is illustrated a device layout that can be employed in the present application. The illustrated device layout includes a plurality of gate structures, GS, which are oriented perpendicular to different active areas, AA. In the illustrated device layout, three gate structures, GS, and four device areas, AA, are shown by way of one example. The illustrated device layout ofFIG.1includes cut A-A, cut B-B, and cut C-C. Cut A-A is through a length-wise direction of one of the active areas, AA, cut B-B is partially through a length-wise direction of one of the gate structures, GS, and cut C-C is located in between two neighboring gate structures, GS, and it passes through source/drain (S/D) regions of the two neighboring gate structures, GS.

In the present application, a semiconductor structure is described and illustrated as containing stacked nanosheet transistors. A transistor includes a source region, a drain region, a semiconductor channel region located between the source region and the drain region, and a gate electrode located above the semiconductor channel region. A nanosheet transistor is a non-planar transistor that includes a vertical stack of spaced apart semiconductor channel material nanosheets as the semiconductor channel region with a pair of source/drain regions located at each of the ends of the vertical stack of spaced apart semiconductor channel material nanosheets. The gate structure including a gate dielectric and a gate electrode wraps around each of the spaced apart semiconductor channel material nanosheets. Although stacked nanosheet transistors are described and illustrated, the present application can used with stacked planar transistors, or other stacked non-planar transistors such as, for example, semiconductor nanowire transistors or finFET transistors.

In the present application, the semiconductor structure includes a frontside and a backside. The frontside of the semiconductor structure of the present application includes a side of the structure that includes the transistors, MOL level, and all frontside BEOL structures. The backside of the semiconductor structure of the present application is the side of the structure that is opposite the frontside. In a stacked nanosheet transistor, the frontside can be located on a first side of a bottom dielectric isolation layer, while the backside can be located on a second side of the bottom dielectric isolation layer that is opposite the first side.

Referring now toFIGS.2A,2B and2C, there are illustrated an exemplary structure that can be employed in the present application;FIG.2Ais a cross sectional view through cut A-A shown inFIG.1,FIG.2Bis a cross sectional view through cut B-B shown inFIG.1andFIG.2Cis a cross sectional view through cut C-C shown inFIG.1. The illustrated structure shown inFIGS.2A-2Cincludes a substrate (10/12/14), a first placeholder material layer18L located on the substrate (10/12/14), a first material stack, MS1, located on the first placeholder material layer18L, a second placeholder material layer24L located on the first material stack, MS1, a second material stack, MS2, located on the second placeholder material layer24L, and a plurality of sacrificial gate structures30(three of which are shown by way one example inFIG.2A) located on the second material stack, MS2. Each sacrificial gate structure30can be capped with a sacrificial gate cap32. Each sacrificial gate structure30is present on a topmost surface of the second material stack, MS2, and along a sidewall of each of the first placeholder material layer18L, the first material stack, MS1, the second placeholder material layer24L, and the second material stack, MS2. In some embodiments, the sacrificial gate cap32can be omitted. In the illustrated embodiment shown inFIGS.2A-2C, shallow trench isolation structures16are present in an upper portion of the substrate (10/12/14). The shallow trench isolation structures16would be located in the region of the device layout shown inFIG.1that is located between each of the active areas, AA.

The semiconductor structure illustrated inFIGS.2A-2Ccan be formed utilizing various processing steps that are well known to those skilled in the art. The processing steps can include, for example, various deposition and patterning steps. The depositions can include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In some embodiments, an epitaxial growth process (as defined later herein) can be used to form semiconductor materials that are present in the illustrated semiconductor structure. Patterning can include lithography and etching (dry etching and/or chemical wet etching). Dry etching can include, for example, reactive ion etching (RIE), ion beam etching (IBE), and plasma etching. Chemical wet etching includes the use of an appropriate chemical etchant that has a high etch rate for one material as compared to at least one another material. So as not to obscure the method of the present application, the processing steps used in providing the structure shown inFIGS.2A-2Chave been omitted from this application. Each of the elements/components of the structure illustrated inFIGS.2A-2Cwill now be described in greater detail.

In some embodiments, and as illustrated inFIGS.2A-2C, the substrate can include a first semiconductor layer10, an etch stop layer12and a second semiconductor layer14. In other embodiments, the etch stop layer12and the second semiconductor layer14can be omitted and in such embodiments, the substrate is composed of the first semiconductor layer10. In yet other embodiments, the etch stop layer12can be omitted and in such embodiments, the substrate is composed of the first semiconductor layer10and the second semiconductor layer14(in such embodiments the semiconductor material that provides the first and second semiconductor layers10,14are compositionally different from each other).

The first semiconductor layer10is composed of a first semiconductor material. The second semiconductor layer14is composed of a second semiconductor material. The term “semiconductor material” is used throughout the present application to denote a material having semiconducting properties. Examples of semiconductor materials that can be used in the present application in providing the first semiconductor material and the second semiconductor material include, but are not limited to, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide (SiGeC) alloy, germanium (Ge), III/V compound semiconductors or II/VI compound semiconductors. The second semiconductor material that provides the second semiconductor layer14can be compositionally the same as, or compositionally different from, the first semiconductor material that provides the first semiconductor layer10. In some embodiments of the present application, the etch stop layer12can be composed of a dielectric material such as, for example, silicon dioxide and/or boron nitride. In other embodiments of the present application, the etch stop layer12is composed of a third semiconductor material that is compositionally different from the first semiconductor material that provides the first semiconductor layer10and the second semiconductor material that provides the second semiconductor layer14. In one example, the first semiconductor layer10is composed of silicon, the etch stop layer12is composed of silicon dioxide, and the second semiconductor layer14is composed of silicon. In another example, the first semiconductor layer10is composed of silicon, the etch stop layer12is composed of silicon germanium, and the second semiconductor layer14is composed of silicon. The substrate including the first semiconductor layer10, the etch stop layer12and the second semiconductor layer14can be formed utilizing techniques well known to those skilled in the art.

The shallow trench isolation structures16can be formed into the substrate; in the illustrated embodiment the shallow trench isolation structures16are formed into the second semiconductor layer14. Each shallow trench isolation structure16is composed of a trench dielectric material such as, for example, silicon oxide. In some embodiments, a trench dielectric liner composed of, for example, SiN, can be present along a sidewall and a bottom wall of the trench dielectric material. Each shallow trench isolation structure16can have a topmost surface that is coplanar with a topmost surface of the non-etched portion of the substrate; in the illustrated embodiment each shallow trench isolation structure16can have a topmost surface that is coplanar with a topmost surface of the non-etched portion of the second semiconductor layer14.

The first placeholder material layer18L is composed of fourth semiconductor material that is compositionally different from the second semiconductor material that provides the second semiconductor layer14of the substrate (10/12/14). In one example, the fourth semiconductor material that provides the first placeholder material layer18L is composed of a SiGe alloy including from55to70atomic percent germanium.

The first material stack, MS1, is composed of alternating layers of a first sacrificial semiconductor material layer20L and a first semiconductor channel material layer22L. In some embodiments and as is illustrated inFIGS.2A-2C, there are “n+1” numbers of first sacrificial semiconductor material layers20L and “n” number of first semiconductor channel material layers22L, wherein n is an integer starting from one. Thus, each first semiconductor channel material layer22L is sandwiched between a bottom and top first sacrificial semiconductor material layer20L. By way of one example, the first material stack, MS1, includes three first sacrificial semiconductor material layers20L and two first semiconductor channel material layers22L. Each first sacrificial semiconductor material layer20L is composed of a fifth semiconductor material, while each first semiconductor channel material layer22L is composed of a sixth semiconductor material. In the present application, the sixth semiconductor material is compositionally different from the fifth semiconductor material, and both the fifth and sixth semiconductor materials are compositionally different from the fourth semiconductor material.

In some embodiments, the sixth semiconductor material that provides each first semiconductor channel material layer22L is capable of providing high channel mobility for n-type field effect transistor (FET) devices. In other embodiments, the sixth semiconductor material that provides each first semiconductor channel material layer22L is capable of providing high channel mobility for p-type FET devices. The fifth semiconductor material that provides each first sacrificial semiconductor material layer20L, and the sixth semiconductor material that provides each first semiconductor channel material layer22L can include one of the semiconductor materials mentioned above. In one example, each first sacrificial semiconductor material layer20L is composed of a silicon germanium alloy having a germanium content from20atomic percent to40atomic percent, and each first semiconductor channel material layer22L is composed of silicon. Other combinations of semiconductor materials are possible as long as the fifth semiconductor material that provides each first sacrificial semiconductor material layer20L is compositionally different from the sixth semiconductor material that provides each first semiconductor channel material layer22L, and that both the fifth and sixth semiconductor materials are different from the fourth semiconductor material.

Each first sacrificial semiconductor material layer20L can have a first thickness, and each first semiconductor channel material layer22L can have a second thickness. In the present application, the first thickness can be equal to, greater than, or less than, the second thickness.

The second placeholder material layer24L is compositionally the same as the first placeholder material layer18L. Thus, the second placeholder material layer24L is composed of the fourth semiconductor material. In one example, the fourth semiconductor material that provides both the first placeholder material layer18L and the second placeholder material layer24L is composed of a SiGe alloy including from55to70atomic percent germanium.

The second material stack, MS2, is composed of alternating second sacrificial semiconductor material layers26L and second semiconductor channel material layers28L. In some embodiments and as is illustrated inFIGS.2A-2C, there is an equal number of second sacrificial semiconductor material layers26L and second semiconductor channel material layers28L. That is, the material stack can include ‘y’ number of second semiconductor channel material layers28L and ‘y’ number of second sacrificial semiconductor material layers26L, wherein y is an integer starting from one. By way of one example, the second nanosheet material stack, MS2, includes two second sacrificial semiconductor material layers26L and two second semiconductor channel material layers28L. Each second sacrificial semiconductor material layer26L is composed of a seventh semiconductor material, while each second semiconductor channel material layer28L is composed of eighth semiconductor material; the eighth semiconductor material is compositionally different from the seventh semiconductor material. In the present application, the seventh semiconductor material is typically compositionally the same as the fifth semiconductor material, while the eighth semiconductor material can be compositionally the same as, or compositionally different from, the sixth semiconductor material. In the present application, the seventh and eighth semiconductor materials are compositionally different from the fourth semiconductor material.

In some embodiments, the eighth semiconductor material that provides each second semiconductor channel material layer28L is capable of providing high channel mobility for n-type field effect transistor (FET) devices. In other embodiments, the eighth semiconductor material that provides each second semiconductor channel material layer28L is capable of providing high channel mobility for p-type FET devices. The seventh and eighth semiconductor materials can include one of the semiconductor materials mentioned above.

In one embodiment, the first placeholder material layer18L and the second placeholder material layer24L are both composed of a SiGe alloy including from55to70atomic percent germanium, the first sacrificial semiconductor material layers20L and the second sacrificial semiconductor material layers26L are composed of a silicon germanium alloy having a germanium content from20atomic percent to40atomic percent, and the first semiconductor channel material layers22L are composed of silicon, and the second semiconductor channel material layers28L are composed of germanium.

Each second sacrificial semiconductor material layer26L can have a third thickness, and each second semiconductor channel material layer28L can have a fourth thickness. In the present application, the third thickness can be equal to, greater than, or less than, the fourth thickness. In the present application, the third and fourth thicknesses can be equal to, greater than, or less than the first thickness and/or the second thickness.

Each sacrificial gate structure30includes at least a sacrificial gate material. In some embodiments, each sacrificial gate structure30can also include a sacrificial gate dielectric material. In such embodiments, the sacrificial gate dielectric material would be located beneath the sacrificial gate material. The optional sacrificial gate dielectric material can be composed of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material can be composed of, for example, polysilicon, amorphous silicon, amorphous silicon germanium or amorphous germanium.

The sacrificial gate cap32is composed of a hard mask material such as, for example, silicon nitride. In some embodiments, the sacrificial gate cap32can be omitted from on top of the sacrificial gate structure30.

Referring now toFIGS.3A,3B and3C, there are illustrated the exemplary semiconductor structure shown inFIGS.2A,2B and2C, respectively, after removing the first placeholder material layer18L and the second placeholder material layer24L, depositing a dielectric material to form a gate spacer38, a bottom dielectric isolation layer34and a device isolation layer36, patterning the second material stack, MS2, the device isolation layer36and the first material stack, MS1, and forming an inner spacer40, these steps form a plurality of patterned nanosheet containing structures including a second nanosheet material stack, NS2, located over a first nanosheet material stack, NS1.

The removal of the first placeholder material layer18L and the second placeholder material layer24L can be performed utilizing a selective etching process. This removal forms a first cavity beneath the first material stack, MS1, and a second cavity between the second material stack, MS2, and the first material stack, MS2. During this removal process, the structure is anchored by the sacrificial gate structures30, and if present, the sacrificial gate caps32.

After forming the first and second cavities mentioned above, a dielectric material is formed to provide the gate spacer38along a sidewall of each sacrificial gate structure30, the bottom dielectric isolation layer34(in the first cavity beneath the first material stack, MS1) and the device isolation layer36(in the second cavity that is located between the second material stack, MS2, and the first material stack, MS1. The dielectric material used in forming the bottom dielectric isolation layer34, the device isolation layer36, and the gate spacer38includes, but is not limited to, silicon dioxide, SiN, SiBCN, SiOCN or SiOC. The dielectric material can be formed utilizing a deposition process including, for example, CVD, PECVD or ALD.

The patterning step employed in providing the structure illustrated inFIGS.3A-3Cincludes an etch such as, for example, a RIE, in which each gate spacer38, sacrificial gate structure30and, if present, the sacrificial gate cap32serve as an etch mask. The etch removes portions of the second material stack, MS2, (including portions of each second sacrificial semiconductor material layer26L and each second semiconductor channel material layer28L), portions of the device isolation layer36, portions of the first material stack, MS1, (including portions of each first sacrificial semiconductor material layer20L and each first semiconductor channel material layer22L), and portions of the bottom dielectric isolation layer34that are not protected by the etch mask. After this patterning steps, a portion of the second material stack, MS2, (including a portion of each second sacrificial semiconductor material layer26L and each second semiconductor channel material layer28L), a portion of the device isolation layer36, and a portion of the first material stack, MS1, (including a portion of each first sacrificial semiconductor material layer20L and each first semiconductor channel material layer22L) remain beneath the etch mask. The etch used in this patterning step stops on the bottom dielectric isolation layer34.

The portion of the second material stack, MS2, that remains beneath each sacrificial gate structure30can be referred to as a second nanosheet material stack, NS2. Each second nanosheet material stack, NS2, includes unetched portions of each second sacrificial semiconductor material layer26L and each second semiconductor channel material layer28L. The unetched portion of each second sacrificial semiconductor material layer26L can be referred to herein as a second sacrificial semiconductor material nanosheet26, and the unetched portion of each second semiconductor channel material layer28L can be referred to as a second semiconductor channel material nanosheet28.

The portion of the first material stack, MS1, that remains beneath each sacrificial gate structure30can be referred to as a first nanosheet material stack, NS1. Each first nanosheet material stack, NS1, includes unetched portions of each first sacrificial semiconductor material layer20L and each first semiconductor channel material layer22L. The unetched portion of each first sacrificial semiconductor material layer20L can be referred to herein as a first sacrificial semiconductor material nanosheet20, and the unetched portion of each first semiconductor channel material layer22L can be referred to as a first semiconductor channel material nanosheet22.

In the present application, each nanosheet has a length along the A-A cut that is less than the length of each of the original first sacrificial semiconductor material layers20L, original first semiconductor channel material layers22L, original second sacrificial semiconductor layers26L, and original second semiconductor channel material layers28L.

As is illustrated, an individual second nanosheet material stack, NS2is stacked above, one of the first nanosheet material stacks, NS1. Collectively, each stacked NS1and NS2configuration can be referred to as a patterned nanosheet containing structure.

After the patterning process mentioned above, each first sacrificial semiconductor material nanosheet20and each second sacrificial semiconductor material nanosheet26is subjected to a lateral etch that removes end portions each of first sacrificial semiconductor material nanosheet20and each second sacrificial semiconductor material nanosheet26. The lateral etch can include a single lateral etching process or two different lateral etching process can be used. The inner spacer40is then formed at the ends of each first sacrificial semiconductor material nanosheet20and each second sacrificial semiconductor material nanosheet26that were subjected to the lateral etch. The inner spacer40is composed of one of dielectric materials mentioned above for providing the bottom dielectric isolation layer34, the device isolation layer36, and the gate spacer38. The dielectric material that provides each inner spacer40can be compositionally the same as, or compositionally different from, the dielectric material that provides the bottom dielectric isolation layer34, the device isolation layer36, and the gate spacer38. Inner spacer40can be formed by a deposition process, followed by a spacer etch.

Referring now toFIGS.4A,4B and4C, there are illustrated the exemplary semiconductor structure shown inFIGS.3A,3B and3C, respectively, after forming openings42into an upper portion of the substrate (10/12/14); in the illustrated embodiment the openings42are formed into the second semiconductor layer14and can remove one of the shallow trench isolation structures16from the structure. The openings42can be formed by first forming an organic planarization layer (OPL)41utilizing a deposition process (e.g., CVD, PECVD or spin-on coating), patterning the OPL41by lithography and etching, and thereafter transferring the pattern formed into the OPL layer41utilizing a transfer etching process. The transfer etching process removes physically exposed portions of the bottom dielectric isolation layer34, the shallow trench isolation structure16(in some areas) and upper portion of the substrate (10/12/14); in the illustrated embodiment an upper portion of the second semiconductor layer14is removed by this transfer etching process.

After forming the openings42and prior to performed the processing steps illustrated inFIGS.5A-5C, the remaining OPL41can be removed from the structure utilizing any material removal process that is selective in removing the OPL41from the structure.

Referring now toFIGS.5A,5B and5C, there are illustrated the exemplary semiconductor structure shown inFIGS.4A,4B and4C, respectively, after forming a sacrificial material structure44in each of the openings42, forming bottom source/drain regions46, a first frontside interlayer dielectric (ILD) layer48, top source/drain regions50, and a second frontside ILD layer52, removing each sacrificial gate structure30, removing each first sacrificial semiconductor material nanosheet20and each second sacrificial semiconductor material nanosheet26, and forming a gate structure54wrapped around each first semiconductor channel material nanosheet22and each second semiconductor channel material nanosheet28.

The sacrificial material structure44can be formed by deposition of a dielectric material, followed by a recess etch to reduce the height of the deposited dielectric material. Illustrative examples of dielectric materials that can be used in providing the sacrificial material structure44include, but are not limited to, SiC, SiOC or AlOx.

The bottom source/drain regions46are typically formed by an epitaxial growth process. Throughout the present application, the terms “epitaxial growth” or “epitaxially growing” mean the growth of a semiconductor material on a growth surface of another semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the growth surface of the another semiconductor material. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the growth surface of the another semiconductor material with sufficient energy to move around on the growth surface and orient themselves to the crystal arrangement of the atoms of the growth surface. Examples of various epitaxial growth process apparatuses that can be employed in the present application include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. Following the epitaxial growth process, a recess etch can be used to reduce the height of the bottom source/drain regions. The bottom source/drain regions46do not extend above the bottommost layer of the device isolation layer36.

The bottom source/drain regions46extend outward from a sidewall of each first semiconductor channel material nanosheet22. The bottom source/drain regions46are located on an upper surface of the sacrificial material structure44or an upper surface of bottom dielectric isolation layer34. Each of the bottom source/drain regions46is composed of a semiconductor material and a first dopant. As used herein, a “source/drain” region can be a source region or a drain region depending on subsequent wiring and application of voltages during operation of the transistor. The semiconductor material that provides each bottom source/drain region46is composed of one of the semiconductor materials mentioned above for the first semiconductor layer10. The semiconductor material that provides the bottom source/drain regions46can be compositionally the same, or compositionally different from each first semiconductor channel material nanosheet22. The first dopant that is present in the bottom source/drain regions46can be either a p-type dopant or an n-type dopant. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus and indium. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. In one example, each of the bottom source/drain regions44can have a dopant concentration of from 4×1020atoms/cm3to 3×1021atoms/cm3.

After bottom source/drain region46formation, the first frontside ILD layer48is formed. The first frontside ILD layer48is composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. The term “low-k” as used throughout the present application denotes a dielectric material that has a dielectric constant of less than 4.0 (all dielectric constants mentioned herein are relative to a vacuum unless otherwise noted). The first frontside ILD layer48can be formed by a deposition process including, but not limited to, CVD, PECVD or spin-on coating. A recess etch typically follows the deposition process. The first frontside ILD layer48is formed on physically exposed surfaces (including a topmost surface and sidewall surfaces) of each bottom source/drain region46. The first frontside ILD layer48has a height that does not extend to the bottommost surface of the bottommost second semiconductor channel material nanosheet28.

Next, the top source/drain regions50are formed. The top source/drain regions50are typically formed by an epitaxial growth process. A recess etch can follow the epitaxial growth process. The top source/drain regions50extend outward from a sidewall of each second semiconductor channel material nanosheet28. The top source/drain regions50are located on an upper surface of the first frontside ILD layer48. The first frontside ILD layer48thus separates the bottom source/drain regions46from the top source/drain regions50. Each top source/drain region50is composed of a semiconductor material and a second dopant. The semiconductor material that provides each top source/drain region50is composed of one of the semiconductor materials mentioned above for the first semiconductor layer10. The semiconductor material that provides the top source/drain regions50can be compositionally the same, or compositionally different from each second semiconductor channel material nanosheet28. The second dopant that is present in the top source/drain regions50can be either a p-type dopant or an n-type dopant, both of which have been defined above. The second dopant can be the same as, or different from, the first dopant. In one example, the first dopant is an n-type dopant, and the second dopant is a p-type dopant. In another example, the first dopant is a p-type dopant, and the second dopant is an n-type dopant. In yet another example, the first dopant and the second dopant are both n-type. In yet a further example, the first dopant and the second dopant are both p-type. Each of the top source/drain regions50can have a dopant concentration of from 4×1020atoms/cm3to 3×1021atoms/cm3. The present application thus contemplates forming stacked FETs including. for example, pFETs over nFETs, nFETs over pFETs, pFETs over pFETs, or nFETs over nFETs.

The second frontside ILD layer52is then formed on physically exposed surfaces (including topmost and sidewall surfaces) of the topmost source/drain regions50and on a topmost surface of the first frontside ILD layer48. The second frontside ILD layer52can include one of the dielectric materials mentioned above for the first frontside ILD layer48. The dielectric material that provides the second frontside ILD layer52can be compositionally the same as, or compositionally different from, the dielectric material that provides the first frontside ILD layer48. The second frontside ILD layer52can be formed utilizing a deposition process such as mentioned above for forming the first frontside ILD layer48. A planarization process such as, for example, chemical mechanical polishing (CMP) follows the deposition process that provides the second frontside ILD layer52. The planarization process removes the sacrificial gate cap32(if the same is present) and an upper portion of each gate spacer38. The sacrificial gate structures30are physically exposed after this planarization process has been performed.

The physically exposed sacrificial gate structures30are removed utilizing any material removal process such as, for example, etching, which is selective in removing the sacrificial gate structures30. The removal of the sacrificial gate structures30reveals each of the patterned nanosheet containing structures. Next, each first sacrificial semiconductor material nanosheet20and each second sacrificial semiconductor material nanosheet26are removed so as to suspend each first semiconductor channel material nanosheet22and each second semiconductor channel material nanosheet28within each patterned nanosheet containing structure. The removal of the first sacrificial semiconductor material nanosheets20and second sacrificial semiconductor material nanosheets26includes any material removal process such as, for example, etching, which is selective in removing the first sacrificial semiconductor material nanosheets20and second sacrificial semiconductor material nanosheets26.

Gates structures54are then formed. The gate structures54include a gate dielectric material and a gate electrode, both of which are not separately shown, but intended to be within region defined by the gate structures54. As is known to those skilled in the art, the gate dielectric material directly contacts a physically exposed surface(s) of each semiconductor channel material nanosheet, and the gate electrode is formed on the gate dielectric material. The gate dielectric material has a dielectric constant of 4.0 or greater. Illustrative examples of gate dielectric materials include, but are not limited to, silicon dioxide, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and/or lead zinc niobite (Pb(Zn,Nb)O). The gate dielectric material can further include dopants such as lanthanum (La), aluminum (Al) and/or magnesium (Mg).

The gate electrode can include a work function metal (WFM) and optionally a conductive metal. The WFM can be used to set a threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to effectuate an n-type threshold voltage shift. “N-type threshold voltage shift” as used herein means a shift in the effective work-function of the work-function metal-containing material towards a conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that can effectuate an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations and thereof. In other embodiments, the WFM can be selected to effectuate a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. The term “p-type threshold voltage shift” as used herein means a shift in the effective work-function of the work-function metal-containing material towards a valence band of silicon in the silicon containing material. Examples of such materials that can effectuate a p-type threshold voltage shift include, but are not limited to, titanium nitride, and tantalum carbide, hafnium carbide, and combinations thereof. The optional conductive metal can include, but is not limited to aluminum (Al), tungsten (W), or cobalt (Co). The gate structures54can be formed by deposition of the gate dielectric material, and gate electrode material, followed by a planarization process. At this point of the present application, the gate structures54have a topmost surface that is coplanar with a topmost surface of the second frontside ILD layer52.

Referring now toFIGS.6A,6B and6C, there are illustrated the exemplary semiconductor structure shown inFIGS.5A,5B and5C, respectively, after forming a third frontside ILD layer (not specifically labeled; collectively, the second frontside ILD layer52and the third frontside ILD dielectric layer provide a middle-of-the-line (MOL) dielectric layer56), and cutting at least one gate structure54. The third frontside ILD layer can include one of the dielectric materials mentioned above for the first frontside ILD layer48. The dielectric material that provides the third frontside ILD layer can be compositionally the same as, or compositionally different from, the dielectric material that provides the first frontside ILD layer48and/or the second frontside ILD layer52. The third frontside ILD layer can be formed utilizing a deposition process such as mentioned above for forming the first frontside ILD layer48. A planarization process such as, for example, chemical mechanical polishing (CMP) follows the deposition process that provides the third frontside ILD layer.

The at least one gate structure54can be cut utilizing any gate cut process that includes lithography and etching. The etch forms gate cut openings58as illustrated inFIGS.6B and6Cof the present application. The etch can include RIE. It is noted that the gate cutting occurs in between the different active areas, AA, shown inFIG.1. Some of the gate cut openings58physically exposed sacrificial material structures44that contacts the bottom source/drain region48present in adjacent active areas.

Referring now toFIGS.7A,7B and7C, there are illustrated the exemplary semiconductor structure shown inFIGS.6A,6B and6C, respectively, after forming a bi-layered dielectric structure including an outer dielectric liner60and an inner dielectric plug62in each gate cut opening58. The outer dielectric liner60is composed of a first dielectric material and the inner dielectric plug62can be composed of a second dielectric material that is compositionally different from the first dielectric material. In one example, the first dielectric material is composed of silicon nitride and the second dielectric material is composed of silicon dioxide. The bi-layered dielectric structure can be formed by first depositing a layer of the first dielectric material. A directional etch can then be employed to remove the first dielectric material from the bottom of each gate cut opening58and from the topmost horizontal surface of the structure. The first deposition and the directional etch provide the outer dielectric liner60. A layer of the second dielectric material is then deposited in a remaining volume of each gate cut opening58and atop the structure, and thereafter a planarization process is used to remove the second dielectric material that is formed outside of gate cut opening58. The deposition of the second dielectric material, followed by the planarization step provide the inner dielectric plug62. In some regions of the structure, the bi-layered dielectric structure lands on a surface of one of the shallow trench isolation structures16, while in other regions of the structure the bi-layered dielectric structure lands on a sacrificial material structure44that contacts the bottom source/drain region46present in adjacent active areas.

Referring now toFIGS.8A,8B and8C, there are illustrated the exemplary semiconductor structure shown inFIGS.7A,7B and7C, respectively, after forming deep via openings65,66in the structure by removing the inner dielectric plug62from some of the bi-layered dielectric structures. The forming of the deep via openings65,66includes first forming a patterned OPL layer64on the surface of the structure. The patterned OPL layer64includes openings that would be used in forming the deep via openings65,66. The patterned OPL layer64can be formed by lithography and etching. The openings in the patterned OPL layer64are aligned over the inner dielectric plug62from some of the bi-layered dielectric structures. The inner dielectric plugs62of the bi-layered dielectric structures that are not protected by the patterned OPL64are then removed utilizing an etching process that is selective in removing the inner dielectric plug62as compared to the outer dielectric liner60. In some cases, this etching process can also remove an upper portion of the shallow trench isolation structure16as is shown inFIGS.8B and8Cto form the deep via opening65, while in other cases and as shown inFIG.8Bthis etching process can stop on a topmost surface of the sacrificial material structure44that contacts the bottom source/drain region46present in adjacent active areas to form the deep via opening66. Deep via opening65is a deeper via opening than deep via opening66.

Referring now toFIGS.9A,9B and9C, there are illustrated the exemplary semiconductor structure shown inFIGS.8A,8B and8C, respectively, after forming frontside contact openings into the MOL dielectric layer56. Prior to forming the frontside contact openings, the patterned OPL layer64is removed from the structure utilizing any material removal process that is selective in removing the patterned OPL layer64. The frontside contact openings can be formed by lithography and etching. The frontside contact openings that are formed include top source/drain contact opening68A, gate contact openings68B, bottom source/drain contact openings68C, and a merged contact opening68D. Merged contact opening68D includes a combination of a top source/drain contact opening and deep via opening65.

Referring now toFIGS.10A,10B and10C, there are illustrated the exemplary semiconductor structure shown inFIGS.9A,9B and9C, respectively, after forming frontside contact structures and deep vias, an initial frontside BEOL structure including lower interconnect levels, an additional frontside BEOL structure, and a carrier wafer. The frontside contact structures and the deep vias are formed into each of the contact openings and deep via openings shown inFIGS.9A,9B and9Cutilizing a metallization process that includes filling (including deposition and planarization) each of the frontside contact openings and deep via openings with at least a contact conductor material. The contact conductor material can include, for example, a silicide liner, such as Ni, Pt, NiPt, an adhesion metal liner, such as TiN, and conductive metals such as W. Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. The frontside contact structures can also include one or more contact liners (not shown). In one or more embodiments, the contact liner (not shown) can include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, an alloy thereof, or a stack thereof such as Ti/TiN and Ti/WC. In one or more embodiments in which a contact liner is present, the contact liner (not shown) can include a silicide liner, such as Ti, Ni, NiPt, etc., and a diffusion barrier material, as defined above.

The metallization forms top source/drain contact structures70A, top gate contact structures70B, combined top and bottom source/drain contact structures70C, first deep via71A, second deep via71B and a combined top source/drain contact structure/deep via71C. In the present application, each top source/drain structure70A contacts one of the top source/drain regions50, each top gate contact structure70B contacts one of the gate structures54, and each combined top and bottom source/drain contact structure70C contacts both a top source/drain region50and a bottom source/drain region46. In the present application, the term “deep via” is used to denote a contact conductor material-containing structure that is present in a via opening.

In the present application, the first deep via71A and the combined top source/drain contact structure/deep via71C land on a subsurface of one of the shallow trench isolation structures16, and the second deep via71B lands on a surface of one of the sacrificial material structures44. In the present application, the outer dielectric liner60is present on a sidewall of each of the first deep via71A, the second deep via71B and the combined top source/drain contact structure/deep via71C. In the present application, a lower portion of the first deep via71A is present in one of the shallow trench isolation structures16, a middle portion of the first deep via71A is located laterally adjacent to two neighboring gate structures54, and a top portion of the first deep via71A is located in the MOL dielectric layer56. In the present application, the second deep via71B is present between the bottom and top source/drain regions of two neighboring gate structures54. In the present application, a lower portion of the combined top source/drain contact structure/deep via71C is present in one of the shallow trench isolation structures16, a middle portion of the combined top source/drain contact structure/deep via71C is located laterally adjacent to two neighboring gate structures54, and a top portion of the combined top source/drain contact structure/deep via71C is located in the MOL dielectric layer56.

The initial frontside BEOL structure including lower interconnect levels is then formed. The initial frontside BEOL structure includes a fourth frontside ILD layer74and wiring structures including a first via structure, V0, and a first metal line, M1. The V0are typically merged with one of the M1s.The fourth frontside ILD layer74is composed of one of the dielectric materials mentioned above for the first frontside ILD layer48. The fourth frontside ILD layer74is formed via a deposition process on the MOL dielectric layer56and each of the frontside contact structures and deep vias that are present in the structure shown inFIGS.9A-9C. The wiring structures including the first via structure, VO, and the first metal line, M1are composed of at least an electrically conductive metal or electrically conductive metal alloy. In some embodiments, Cu or a Cu—Al alloy can be used as the electrically conductive material that provides the wiring structures including the first via structure, VO, and the first metal line, M1, that are present in the initial frontside BEOL structure. The wiring structure present in the initial frontside BEOL structure are formed utilizing a metallization process that includes forming openings into the fourth frontside ILD layer74, filling each opening with an electrically conductive material, and then performing a planarization process.

The additional frontside BEOL structure76is then formed on the initial frontside BEOL structure. The additional frontside BEOL structure76can include one or more interconnect dielectric material layers (including one of the dielectric materials mentioned above for the first frontside ILD layer48) that contain frontside metal wires (the metal wires can be composed of any electrically conductive metal or electrically conductive metal alloy) embedded therein. The additional frontside BEOL structure76can include “x” numbers of frontside metal levels, wherein “x” is an integer starting from 1. The additional frontside BEOL structure76can be formed utilizing techniques well known to those skilled in the art.

As is illustrated inFIGS.10A-10C, the wiring structures including the first via structure, V0, and the first metal line, M1, are used in connecting the top source/drain contact structures70A, the top gate contact structures70B, the first deep via71A, and the second deep via71B to the additional frontside BEOL structure76. The combined top source/drain contact structure/via bar power71C is not however connected to any wiring structures present in the initial frontside BEOL structure and thus is not directly connected to the additional BEOL structure76.

The carrier wafer78can include one of the semiconductor materials mentioned above for the first semiconductor layer10. Carrier wafer78is bonded to the additional frontside BEOL structure78after additional frontside BEOL structure76formation.

Referring now toFIGS.11A,11B and11C, there are illustrated the exemplary semiconductor structure shown inFIGS.10A,10B and10C, respectively, after removing the first semiconductor layer10of the substrate (10/12/14) to expose the etch stop layer12of the substrate (10/12/14). The removal of the first semiconductor layer10typically includes flipping the wafer 180° to physically expose a backside of the substate. This flipping step is not shown in the drawings of the present application for clarity. In the illustrated embodiment, the substrate includes the first semiconductor layer10, the etch stop layer12, and the second semiconductor layer14. Thus, the flipping can physically expose the first semiconductor layer10of the substrate (10/12/14). This flipping step will allow backside processing of the exemplary structure. In the present application the backside of the wafer can be defined as the area of the wafer that is beneath the bottom dielectric isolation layer34. Flipping of the structure can be performed by hand or by utilizing a mechanical means such as, for example, a robot arm.

In the illustrated embodiment, the removal of the physically exposed first semiconductor layer10physically exposes the etch stop layer12. The removal of the first semiconductor layer10can be performed utilizing a material removal process that is selective in removing the first semiconductor material that provides the first semiconductor layer10.

Referring now toFIGS.12A,12B and12C, there are illustrated are cross sectional views of the exemplary semiconductor structure shown inFIGS.11A,11B and11C, respectively, after removing the etch stop layer12and a second semiconductor layer14of the substrate (10/12/14). The removal of the etch stop layer12includes a material removal process that is selective in removing the etch stop layer12. The removal of the etch stop layer12physically exposes the second semiconductor layer14of the substrate (10/12/14). The physically exposed second semiconductor layer14can be removed utilizing a material removal process that is selective in removing that layer from the structure. Other material removal processes can be used depending on the type of substrate used. For example, in some embodiments in which substrate is a composed entirely of one semiconductor material, one material removal process can be used instead of the multiple material removal processing steps described herein. As is illustrated inFIGS.12A-12C, the removal of the substrate (10/12/14) reveals a surface of each sacrificial material structure44and a surface of each bottom dielectric isolation layer34.

Referring now toFIGS.13A,13B and13C, there are illustrated the exemplary semiconductor structure shown inFIGS.12A,12B and12C, respectively, after forming a first backside interlayer dielectric (ILD) layer80. The first backside ILD layer80includes one of the dielectric materials mentioned above for the first frontside ILD layer48. The first backside ILD layer80can be formed by a deposition process. A planarization process can follow the deposition that provides the dielectric material of the first backside ILD layer80. As is illustrated, the first backside ILD layer80contacts a physically exposed surface of each of the bottom dielectric isolation layers34and the first backside ILD layer80is located adjacent to the sacrificial material structures44and shallow trench isolation structures16. Each dielectric structure44has a surface that is physically exposed as is shown inFIGS.13A-13C.

Referring now toFIGS.14A,14B and14C, there are illustrated the exemplary semiconductor structure shown inFIGS.13A,13B and13C, respectively, after removing each sacrificial material structure44and forming backside source/drain contact structures82A,82B. The removal of the sacrificial material structures44can be performed utilizing an etching process that is selective in removing the dielectric material that provides the sacrificial material structures44. Backside source/drain contact structures82A,82B are then formed in the voids created by removing the sacrificial material structures44. The backside source/drain contact structures82A,82B include one of the contact conductor materials defined above for the frontside contact structures and can be formed utilizing a metallization process. Backside source/drain contact structures82A contact a single bottom source/drain region46, while backside source/drain contact structure82B contacts the bottom source/drain region46present in adjacent active areas.

Referring now toFIGS.15A,15B and15C, there are illustrated the exemplary semiconductor structure shown inFIGS.14A,14B and14C, respectively, after performing a backside angle cut of one of the backside source/drain contact structures. In the present application, the backside angle cut is performed on the backside source/drain contact structure82B that contacts the bottom source/drain region46present in adjacent active areas. The backside angle cut forms angle cut region84and splits backside source/drain contact structure82B into a first backside source/drain contact structure83A and a second backside source/drain contact structure83B. As is illustrated inFIG.15C, the angled cut region84laterally separates the first backside source/drain contact structure83A from the second backside source/drain contact structure83B. As is also illustrated inFIG.16C, the angled cut region84contacts a lower portion (including bottommost surface and sidewall) surface of the bottom source/drain region46that the first backside source/drain contact structure83A is in contact with.

The first backside source/drain contact structure83A includes a first portion, P1, having a first critical dimension, CD1, and a second portion, P2, having a second critical dimension CD2, wherein the first critical dimension is less than the second critical dimension. The second backside source/drain contact structure83B includes a first portion, P1, having a first critical dimension, CD1, and a second portion, P2, having a second critical dimension, CD2, wherein the first critical dimension is greater than the second critical dimension.

Referring now toFIGS.16A,16B and16C, there are illustrated the exemplary semiconductor structure shown inFIGS.15A,15B and15C, respectively, after forming an initial backside BEOL structure including lower interconnect levels. The initial backside BEOL structure including lower interconnect levels is then formed. The initial backside BEOL structure includes a second backside ILD layer86and wiring structures including a first backside via structure, BV0, and a first backside metal line, BM1. The second backside ILD layer86is composed of one of the dielectric materials mentioned above for the first frontside ILD layer48. The second backside ILD layer86is formed via a deposition process. The wiring structures including the first backside via structure, BV0, and the first backside metal line, BM1are composed of at least an electrically conductive metal or electrically conductive metal alloy. In some embodiments, Cu or a Cu—Al alloy can be used as the electrically conductive material that provides the wiring structures including the first backside via structure, BV0, and the first backside metal line, BM1, that are present in the initial backside BEOL structure. The wiring structure present in the initial backside BEOL structure are formed utilizing a metallization process that includes forming openings into the second backside ILD layer86, filling each opening with an electrically conductive material, and then performing a planarization process.

Referring now toFIGS.17A,17B and17C, there are illustrated the exemplary semiconductor structure shown inFIGS.16A,16B and16C, respectively, after forming an additional backside BEOL structure. Additional backside BEOL structure88is then formed on the initial backside BEOL structure. The additional backside BEOL structure88can include one or more interconnect dielectric material layers (including one of the dielectric materials mentioned above for the first frontside ILD layer48) that contain frontside metal wires (the metal wires can be composed of any electrically conductive metal or electrically conductive metal alloy) embedded therein. The additional backside BEOL structure88can include “y” numbers of backside metal levels, wherein “y” is an integer starting from1. The additional backside BEOL structure88can be formed utilizing techniques well known to those skilled in the art.

Notably,FIGS.17A,17B and17Cillustrates a semiconductor structure in accordance with an embodiment of the present application. The semiconductor structure includes a first stacked FET cell, C1, including a second FET, FET_2, stacked over a first FET, FET_1. The structure further includes a second stacked FET cell, C2, located adjacent to the first stacked FET cell, C1, and including a fourth FET, FET_4stacked over a third FET, FET_3; SeeFIG.17B. Note that FET_3and FET_4are not specifically shown inFIG.17B, nor do the labels FET_3and FET_4appear in any of the drawings. FET_3and FET_4would look similar to FET_1and FET_2shown inFIG.17B. The structure even further includes first backside source/drain contact structure83A located beneath the first stacked FET cell, C1, and contacting a source/drain region (i.e., bottom source/drain region40) of the first FET, FET_1, second backside source/drain contact structure83B located beneath the second stacked FET cell, C2, and contacting a source/drain region (i.e., the bottom source/drain region40) of the third FET, FET_3, and angled cut region84(now filled with a backside ILD material) laterally separating the first backside source/drain contact structure83A from the second backside source/drain contact structure83B.

In embodiments of the present application, and as mentioned above. the first backside source/drain contact structure83A includes a first portion, P1, having a first critical dimension, and a second portion, P2, having a second critical dimension, wherein the first critical dimension is less than the second critical dimension. As is illustrated, the first portion, P1, of the first backside source/drain contact structure83A is in contact with the source/drain region (i.e., bottom source/drain region40) of the first FET, FET_1, and the second portion, P2, of the first backside source/drain contact structure83A is electrically connected to additional backside BEOL structure88by the backside wiring structures, BV0and BM1, present in the initial backside BEOL structure.

In embodiments of the present application, and as is mentioned above, the second backside source/drain contact structure83B includes a first portion, P1, having a first critical dimension, and a second portion, P2, having a second critical dimension, wherein the first critical dimension is greater than the second critical dimension. As is illustrated, the second portion, P2, of the second backside source/drain contact83B is in contact with the source/drain region (bottom source/drain region40) of the third FET, FET_3.

In embodiments of the present application, the structure includes the initial frontside BEOL structure and the additional frontside BEOL structure76above both the first stacked FET cell, C1, and the second stacked FET cell, C2, wherein the source/drain region (i.e., bottom source/drain region46) of the third FET, FET_3, is electrically connected to the additional frontside BEOL structure76by second deep via71B and frontside metal wiring structures present in the initial frontside BEOL structure.

In embodiments of the present application, the second deep via71B is a vertical extending pillar located laterally between the first stacked FET cell, C1, and the second stacked FET cell, C2. In embodiments, outer dielectric liner62is present on a sidewall of the second deep via71B.

In embodiments of the present application, a source/drain region (top source/drain region50of the second transistor, FET_2, is electrically connected to the additional frontside BEOL76structure by other frontside metal wiring structures, i.e., V0and M1, present in the initial frontside BEOL structure.

In embodiments of the present application, a source/drain region (i.e., top source/drain region50) of the fourth transistor, FET_4, is electrically connected to the additional backside BEOL structure76by combined top source/drain contact structure/deep via71C, and other backside wiring structures, BV0and BM1, present in the initial backside BEOL structure.

In embodiments, combined top source/drain contact structure/dep via71C includes a frontside source/drain contact structure merged with deep via.

In embodiments, the first backside source/drain contact structure83A has an angled sidewall facing an angled sidewall of second backside source/drain contact structure83B. In embodiments, each of the first backside source/drain contact structure83A and the second backside source/drain contact structure83B has a perpendicular sidewall opposite the angled sidewall.

In embodiments, the first FET, FET_1, and the second FET, FET_2, share a common gate structure54, and the third FET, FET_3, and the fourth FET, FET_4, share a common gate structure54.

In embodiments, a third stacked FET cell, C3, is located adjacent to the first stacked FET cell, C1, wherein the first stacked FET cell and the third stacked FET cell are separated by bilayer sacrificial material structure including outer dielectric liner60and inner dielectric plug62.