Production-test die temperature measurement

A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.

BACKGROUND

This invention relates generally to measuring die temperature during experimental characterization of integrated circuits, and more specifically during factory testing of System-on-Chip (SoC) products.

2. Related Art

The operating characteristics of integrated circuits are commonly temperature dependent. It is generally required to characterize, validate, and/or calibrate a set of product specifications in respect to the die temperature. This requires some procedure to measure die temperature during test with appropriate accuracy.

To perform validation and calibration of products with high-precision temperature-related specifications, a highly-accurate method to measure die temperature is needed. Solutions based on external temperature sensors, such as thermocouples, commonly provide poor measurement accuracy of die temperature, typically worse than ±7° C. This is mainly due to the significant thermal gradient between the measurement point of interest (silicon junction) and the sensor locus (outside package). This error is higher on System-on-Chip (SoC) products with high power dissipation. Solutions based on fully integrated temperature sensors are not sensitive to thermal gradients beyond the silicon interface, but are commonly limited by the complexity of the measurement and signal-conditioning circuitry that may be completely integrated. Another factor that compromises the precision of internal temperature sensors is that their output is commonly accessible through a pad that is subject to leakage effect. Leakage currents will create signal offsets that result in measurement errors. In integrated circuits, the pads are small areas of metal, typically copper or a copper alloy, in predetermined shapes normally used to make a connection to a component pin. The pad leakage is often a limitation to signal measurement precision, especially at high temperatures, turning production-testing at elevated die temperatures a particularly challenging task.

DETAILED DESCRIPTION

Any benefits, advantages or solutions to problems described herein with regard to specific examples are not intended to be construed as a critical, required or essential feature or element of any or all the claims. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The term “coupled,” as used herein, is defined as “connected,” and encompasses the coupling of devices that may be physically, electrically or communicatively connected (according to context), although the coupling may not necessarily be directly, and not necessarily be mechanically. The term “configured to” describes hardware, software or a combination of hardware and software that is adapted to, set up, arranged, built, composed, constructed, designed or that has any combination of these characteristics to carry out a given function. The term “adapted to” describes hardware, software or a combination of hardware and software that is capable of, able to accommodate, to make, or that is suitable to carry out a given function. The abbreviation I/O is being used to mean “input/output”, such as an I/O pad to the circuit.

Die temperature is sensed using an integrated temperature sensing structure. The integrated temperature sensing structure is placed at a point of interest (i.e., a silicon junction) and is insensitive to thermal gradients between silicon and external medium. The integrated temperature sensing structure relies on external test instrumentation to perform highly accurate signal conditioning and measurement. Therefore, the integrated temperature sensing structure does not require any complex processing circuitry, and exploits the fact that external test instrumentation commonly provides much higher accuracy than is possible through fully integrated test circuitry. The elimination of any complex processing circuitry also favors a low silicon area usage which minimizes cost. Methods in accordance with the present disclosure include techniques to eliminate main sources of error related to die temperature measurement.

Embodiments of sensors and methods disclosed herein measure die temperature with very high precision during factory test. Unlike other solutions that rely on fully internal (integrated) reference thermal sensors, embodiments disclosed herein eliminate the need for high-performance signal conditioning being done internally to the integrated circuit. Rather, the high-performance signal conditioning is done by external test instrumentation commonly used during factory test. Unlike other solutions that employ fully external thermal sensors, embodiments disclosed herein has the sensing element internal to the integrated circuit therefore achieving better match between temperature measured and the actual temperature of interest.

Embodiments of the sensors and methods disclosed herein improve the accuracy of die temperature measurements. This improved accuracy enables product designs to be validated and tested. Products can also achieve more accurate calibration to support high-precision temperature-related specifications.

Embodiments of the sensors and methods disclosed herein employ bipolar transistors as die-temperature sensing structures. It is possible to determine the junction temperature by exciting a sequence of input signals to a bipolar transistor, observing the temperature-dependent output signals, and calculating the temperature from the relationship between these signals.FIG. 1is an example diagram of a bipolar transistor100. Shown is a voltage VBapplied at a base, a voltage VCapplied to a collector, and a voltage VEapplied at an emitter.

Continuing further,FIG. 2is a diagram of the bipolar transistor100ofFIG. 1being used a temperature sensing element within an integrated circuit202. Shown are the currents and the parasitic resistances for the collector, the base and the emitter along with eight I/O pads220. Parasitic resistance is a resistance encountered in a circuit board or integrated circuit but not included in the original design. The parasitic resistance is typically an undesirable, unintended consequence of putting a design into manufacturing. The value of parasitic resistance can be estimated in order to make sure the circuit still functions as designed. One example of a parasitic resistance is the resistance of a transistor or a resistance of a diode. Another example of parasitic resistance is the resistance of the traces in a circuit board or metal interconnects in an integrated circuit (IC), the purpose of which is to connect components electrically according to the circuit diagram, but these connecting structures are not ideal.

The parasitic resistances of the bipolar transistor are rC, rBand rE, which correspond to the collector parasitic resistance, the base parasitic resistance, and the emitter parasitic resistance, respectively. The parasitic resistances rC, rBand rEof the bipolar transistor typically include a routing resistance, as well. Also shown are the current flowing into the collector IC, the current flowing into the base IB, and the current flowing out of the emitter IE.

The junction temperature can be determined through the change in emitter-base voltage of a bipolar transistor in response to a change in collector current density:

Δ⁢⁢VBE=VBE⁢⁢1-VBE⁢⁢2=kTq⁢ln⁢⁢IC⁢⁢1IC⁢⁢2⁢=>⁢T=Δ⁢⁢VBE·qk·1ln⁢⁢IC⁢⁢1IC⁢⁢2(Equation⁢⁢1)
where VBEis the forward-bias voltage between the base and the emitter at two different successive time intervals, i.e., “1” and “2” (VBE1, VBE2), k is Boltzmann's constant, q is the electron charge, T is the absolute temperature measured in kelvin, ln is the natural logarithm function, IC1is the collector current at the first time interval, and IC2is the collector current at the second time interval.

However, a method to extract die temperature based on Equation 1 must be refined to avoid potential error sources. The measure of bipolar terminal voltages is subject to the effect of current flowing through terminal resistances or other parasitic resistances which contribute with offset (error) components. Also, the measurement being made at a pin of the integrated circuit is subject to the effect of leakage currents, mainly from reverse-biased junctions at the I/O pad220, which are especially problematic at higher temperatures. Finally, there is a weak dependence of Equation 1 with process technology which is commonly captured by a process model parameter called non-ideality factor. The present disclosure addresses each of these potential error sources in order to provide optimum accuracy.

FIG. 3is an example schematic diagram of an embodiment of a die temperature measurement system300with pad leakage cancellation. The die temperature measurement system300is divided into two major sections, an external test environment352and the integrated circuit302. The test environment352is now described. An external voltage VBIN354is applied between a first I/O pad362and a third I/O pad382of the integrated circuit302. Also, the external voltage VBIN354is applied to an external resistance rext358coupled in series to the first I/O pad362. The nominal resistance of external resistance rext358is typically defined by a designer of the integrated circuit302. A voltage meter356is coupled to measure voltage VMEASbetween the first I/O pad362and a second I/O pad372of the integrated circuit302. Alternatively, the external voltage VBIN354in series with resistance rextcan be replaced by an external current source IBIN(not shown) with resistance rextin parallel (Norton equivalent).

Now, the integrated circuit302is described. A bipolar transistor325has a base322with a base parasitic resistance rB320, a collector326with a collector parasitic resistance rC324, and an emitter328with an emitter parasitic resistance rE329. The parasitic resistances rB320, rC324, rE329of the bipolar transistor325typically include the routing resistance as well. A first I/O pad362of the integrated circuit302has a resistance rt1345in series with a first terminal341of a switch340. A second terminal343of the switch340is coupled to the base322of the bipolar transistor325. This switch340is used to carry out the pad leakage current cancellation as described further below. The switch340has two or more resistances that can be selectively coupled in series with the resistance rt1345and the base322of bipolar transistor325. In this example, the first resistance342is a shunt with substantially zero resistance. The second resistance344has a resistance rSW. In this example, two resistance values342,344are shown. In other examples, two or more resistance values may be selectively coupled in series with the resistance rt1345and the base322of bipolar transistor325. The resistance rt1345, the resistance rt2346, the resistance rGRD348, represent the routing and connectivity resistances. The resistances rt1, rt2and rGRDrepresent routing resistances, transmission gate resistances and wirebonding resistances, i.e., all un-desired resistances that may appear on the signal path. These are also known as parasitic or undesirable resistances.

A driver315is shown coupled with an input316coupled to the collector326of the bipolar transistor325. The output317of the driver315is coupled to the collector322of the bipolar transistor325. A selectable-gain current mirror circuit310with a control input gs312that is used to select a current mirror gain Ngs316is coupled to the collector326. The selectable-gain current mirror circuit310includes an internal current source with a current output IBIAS318. The current output IBIAS318is coupled in series with a resistance rGND346to the third I/O pad382of integrated circuit302. This selectable-gain current mirror circuit310provides for precise control of biasing current ratios. A skilled designer may replace the selectable-gain current mirror by some other implementation that supports precise control of the biasing current ratios which includes the alternative of providing the biasing currents through an I/O pad (not shown).

Zero or more bipolar transistors335are coupled in series between the emitter328of bipolar transistor325and the resistance rGND347and resistance rt2346. Each of the bipolar transistors335has a base332with a base resistance rB330, a collector336with a collector resistance rC334, and an emitter338with an emitter resistance rE339. Each of the bipolar transistors335can be realized as a diode. The base332and collector336of each of the bipolar transistors335are coupled together to form the diode. These diodes are placed in a cascaded series configuration to produce the temperature-related voltages with adequate excursion and thermal sensitivity. Transistors335and325can be made identical in order to conduct an equal collector current.

Procedure to Extract Die Temperature

The die temperature extraction method with cancellation of pad leakage current effect using the die temperature sensor measurement system300ofFIG. 3is now described. The bipolar transistors (shown as transistors325and335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is measured and stored. Die temperature is obtained through algebraic manipulation of these temperature-dependent voltage values.

Each voltage value can be obtained through a sequence of measurements that rely on test instrumentation and a switched-resistance connection arrangement340between voltage meter VMEAS356and output pads362,372. The effects of bipolar terminal parasitic resistances (rB320rC324rE326of the bipolar transistors325and335) and pad leakage current are canceled as described hereinbelow. Finally, the non-ideality factor of the technology can be taken into account to achieve maximum accuracy.

FIG. 4is a flow diagram of a procedure to extract die temperature to the circuit inFIG. 3. The process begins at step410and immediately proceeds to an iterative loop starting in step420. A next value of current from the selectable-gain current mirror310is set to flow through the bipolar transistors325and335. The value of the current in one example is a sequence I, 2I (twice I), NI (where N is an integer higher than 2), 2NI (where 2N is twice N). The values of the extreme values, I and 2NI, are selected such that β=Ic/Ib current gain variation is negligible. The common-emitter current gain is represented by β or βFor hFE, and is approximately the ratio of the DC collector current to the DC base current in forward-active region. In step430, the measured voltage VMEASis obtained. The details of step430are further described inFIG. 5below. In step440, a determination is made whether measured voltage VMEAShas been recorded for each current in the set. In this example, there are at least four (4) values of current: I, 2I, NI and 2NI. If the measured voltage VMEAShas not been recorded for all the values of current in the set, the process returns to step420. Otherwise, once all the measured voltages VMEAShave been recorded for all of the current values in the current set, the process continues to step450.

Using the measurements from step430the terminal resistance effect can be canceled. Specifically, the measured voltage VMEAS, i.e., VBEfor IC=I, 2I, NI and 2NI are written as:

By combining the expressions above (Equations 2) in the form 2*(c−a)−(d−b), the terms rBand rCcancel, which represent the effect of the terminal resistances.

Therefore, to cancel the effect of the terminal resistances (i.e., rBand rC) and alternatively adding more BJTs in series to increase sensitivity, Equation 3 can be re-written as:

T=1kq⁢ln⁡(N)×⌊2·(VMEAS⁡(Ngs=N)-VMEAS⁡(Ngs=1))-(VMEAS⁡(Ngs=2⁢N)-VMEAS⁡(Ngs=2))⌋1+Number_of⁢_Additional⁢_Cascaded⁢_BJTs(Equation⁢⁢4)
where VMEAS(Ngs=N)is the measured voltage between the first I/O pad362and the second I/O pad372with an N value selected as the current mirror gain. The term Ngs316is the current gain through which one collector current is selected from the set of currents I, 2I, NI and 2NI provided by the selectable gain current mirror310. Boltzmann's constant is k, and q is the electron charge. T is the absolute temperature measured in kelvin. The term ln is the natural logarithm function, I is the collector current at the first time interval, 2I is the collector current at the second time interval, NI is the collector current at the third time interval, and 2NI is the collector current at the fourth time interval. The term Number_of_Additional_Cascaded_BJTs is the integer number of the optional cascaded series configuration335. After the temperature is calculated in step450the process ends in step460.

Procedure to Compensate for Pad Leakage

FIG. 5is a flow diagram of a procedure inFIG. 4to compensate for leakage at the pad. The process begins in step530and immediately proceeds to step531in which an upper bound voltage VMAXis set. Typically, the upper bound voltage VMAXis set to the positive supply voltage which is also referred to as VDD. Also in step531, a lower bound voltage is set, typically to ground or zero. The process continues to step532in which an iterative loop is entered where the external voltage VBIN354is set to a value between VMAXand VMIN. In one example, the value is set to:

In step533, at least two voltage measurements VMEASare taken. The first voltage measurement VMEAS(SW=0)is measured when the switch340is in a first position (SW=0) with a resistance rSW344. The second voltage measurement VMEAS(SW=1)is measured when the switch340is in a second position (SW=1). This second position may be a shunt with substantially zero resistance. A test in step534is made to determine if VMEAS(SW=0)is equal to VMEAS(SW=1). If the measured voltages are equal the process ends in step538. Otherwise, if the measured voltages are different, a second test is made in step535. If VMEAS(SW=1)is greater than VMEAS(SW=0)the process continues to step536to set VMIN≦VBINand then loops back to step532. Otherwise, if VMEAS(SW=1)is less than or equal to VMEAS(SW=0), the process continues to step537to set VMAX≧VBINand then loops back to step532.

FIG. 6is a plot corresponding to the measured voltage VMEASversus the applied voltage VBINfor SW=0 and SW=1. Note that a nonlinear characteristic of VMEAS(VBIN) derives from the nonlinear characteristic of the pad leakage current. Also note the line620(SW=0) and the line630(SW=1) have different slopes and intersect when VMEASequals the node voltage of interest, also known as VS650. When VMEASis not equal to VS, there is a non-zero current flowing through the path that connects the nodes VMEASand VS. In this case, the VMEASvoltage value changes when a state of the switch340is toggled because the magnitude of the current between nodes VMEASand VSchanges in response to a change of the path resistance between these nodes. When the voltages at nodes VMEASand VSare equal, there is no current through the path that connects these nodes regardless of the state of the switch340and therefore the voltage value at node VMEASis not affected by a toggle on the state of the switch340(intersect point inFIG. 6). In this case, all I/O pad leakage current is provided by the external source (no current flowing from or into the node of interest) and the voltage measured VMEASequals the voltage of interest VS.

For a unique value of externally forced voltage VBIN, all I/O pad leakage current is drained/sourced by the external supply; therefore, no current flows through the resistive path between the pad and internal signal node. For this condition, the measured voltage VMEASat the I/O pads362,372are equal to the voltage of interest (VMEAS=VS), i.e., the pad leakage current effect is canceled. In one example, the optimum voltage VBINto be forced is obtained through an iterative procedure (voltage weep or binary search). At each iteration, the serial resistance between the pad220and the internal signal node is changed (using a switched-resistance arrangement340) and the voltage measurements VMEASthat are derived are compared. VBINis set higher if VMEAS(SW=1)>VMEAS(SW=0)and set lower otherwise, until no change is detected.

There are circumstances when an iterative process to cancel pad leakage is not desirable because it causes a longer time to achieve leakage cancelation. In such circumstances, the following procedure is used: A first V1voltage is applied to VBINwhile a first VMEASis acquired (VM1), the switch340is then closed and a new VMEASis acquired (VM2). A new V2voltage is then applied to VBIN, and the procedure is repeated resulting in voltages VM3and VM4. Assuming that the internal resistances and leakage currents remain reasonably constant over a range of the voltage of interest, then the voltage of interest VSis approximated by:

VS=[VM⁢⁢2-VM⁢⁢1(VM⁢⁢4-VM⁢⁢3)+(VM⁢⁢2-VM⁢⁢1)]⁢(V2-V1)+V1(Equation⁢⁢6)
This method can also be used in an iterative fashion resulting in a much faster convergence than other iterative methods and also relaxing the assumptions made previously.

Note that the adequate values of resistance can be chosen to relax forcing precision requirements of VBINwhile maintaining fast settling characteristic. Precision of measurement of VScan be limited by voltmeter precision on measuring VMEAS. The resistance rSW344can also be removed (switch's on and off resistance changes only) if rEXT358is low enough for fast settling. Also note that VBINand rEXT358can be replaced by a Norton equivalent if the use of an external current source is more convenient.

For high-precision products, one needs to consider that ΔVBEactually shows a weak dependence with process technology. This dependence is captured by the non-ideality factor n (or forward emission coefficient) extracted for the technology which is known to show negligible variance between samples obtained from a single process. The more accurate expression for ΔVBEis:

The non-ideality factor n should be extracted for each specific technology in order to guarantee maximum accuracy (n is typically equal to “1”). However, the parameter is known to show negligible variation over samples from a same technology so it is sufficient to extract it once as a technology constant. This is common-practice among high-precision temperature sensors from the market that exploit thermal properties of bipolar transistors.

Embodiments of circuits and methods disclosed herein measure die temperature with very high precision during factory test. Highly accurate current-mirrors provide precise control of biasing current ratios. The use of a switched-resistance scheme supports pad leakage current cancellation. Embodiments disclosed herein can include cascading devices for optimum coupling with test instrumentation. Therefore, die temperature is extracted during factory-test with higher accuracy and over a wider temperature range.

The specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages or solutions to problems described herein with regard to specific embodiments are not intended to be construed as a critical, required or essential feature or element of any or all the claims. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. Note that the term “couple” has been used to denote that one or more additional elements may be interposed between two elements that are coupled.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below.