Twin gate field effect diode

A semiconductor diode including a first conductivity type region on an upper surface of a semiconductor substrate, a fin structure atop the first conductivity type region providing a vertically orientated semiconductor base region, and a second conductivity type region at a second end of the fin structure opposite a first end of the fin structure that is in contact with the first conductivity type region. The semiconductor diode may also include a vertically orientated dual gate that is present around the fin structure. The vertically orientated dual gate including a first gate structure that is present abutting the semiconductor substrate and a second gate structure that is in closer proximity to the second conductivity type region than the first conductivity type region. The first gate structure separated from the second gate structure by a dielectric inter-gate spacer.

BACKGROUND

Technical Field

The methods and structures described herein relate to electronic devices, such as diodes.

Description of the Related Art

In electronics, a diode is a two-terminal electronic component that conducts primarily in one direction (asymmetric conductance); it has low (ideally zero) resistance to the current in one direction, and high (ideally infinite) resistance in the other. A semiconductor diode, the most common type today, is a crystalline piece of semiconductor material with a p-n junction connected to two electrical terminals.

SUMMARY

In one aspect, a semiconductor diode is provided having a vertical orientation. In one embodiment, the semiconductor diode includes a first conductivity type region on an upper surface of a semiconductor substrate, a fin structure atop the first conductivity type region providing a vertically orientated semiconductor base region, and a second conductivity type region at a second end of the fin structure opposite a first end of the fin structure that is in contact with the first conductivity type region. The semiconductor diode may also include a vertically orientated dual gate structure that is present around the fin structure. In one embodiment, the length of a first gate in the vertically orientated dual gate structure to a first junction is the same as the length of a second gate to a second junction. In another embodiment, the length of the first gate in the vertically orientated dual gate structure to the first junction is the greater than a length of a second gate to the second junction.

In another embodiment, the semiconductor diode includes a first conductivity type region on an upper surface of a semiconductor substrate, a fin structure atop the first conductivity type region providing a vertically orientated semiconductor base region, and a second conductivity type region at a second end of the fin structure opposite a first end of the fin structure that is in contact with the first conductivity type region. The semiconductor diode may also include a vertically orientated dual gate that is present around the fin structure. The vertically orientated dual gate including a first gate structure that is present abutting the semiconductor substrate and a second gate structure that is in closer proximity to the second conductivity type region than the first conductivity type region. The first gate structure separated from the second gate structure by a dielectric inter-gate spacer. In one embodiment, the length of the first gate structure in the vertically orientated dual gate structure to a first junction is the same as the length of the second gate structure to a second junction. In another embodiment, the length of the first gate structure in the vertically orientated dual gate structure to a first junction is the greater than a length of the second gate structure to the second junction.

In another aspect, a method of forming a vertically orientated semiconductor diode is provided having a dual gate structure with a vertical orientation. In one embodiment, the method of forming the semiconductor diode includes forming a fin structure of a base semiconductor material having a first end present on a first conductivity type semiconductor material, wherein a second conductivity type semiconductor material is present at a second end of the fin structure opposite the first end. The method may continue with forming a vertically orientated dual gate structure on the fin structure. In one embodiment, the length of a first gate in the vertically orientated dual gate structure to a first junction is the same as the length of a second gate to a second junction. In another embodiment, the length of the first gate in the vertically orientated dual gate structure to the first junction is the greater than a length of the second gate to the second junction.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The terms “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

As microelectronics and nanoelectronic devices continue to scale to increasingly smaller devices it can be advantageous to provide different device orientations for planar devices, such as a four diode lateral semiconductor on insulator (SOI), e.g., silicon on insulator, stack with a lateral twin gated diode. As will be further described herein, in some embodiments, the methods and structures of the present disclosure configure a dual gated field effect diode in a vertical design, which can be referred to as a vertical dual gated field effect diode. A field effect diode (FED) is a semiconductor diode, in which the charge carriers are of only one polarity. The methods and structures of the present disclosure are now described with greater detail with reference toFIGS. 1-7.

FIG. 1depicts one embodiment of a semiconductor diode100, e.g., field effect diode (FED), having a first conductivity type region15on an upper surface of a semiconductor substrate10, a fin structure20atop the first conductivity type region15that provides a vertically orientated semiconductor base region, and a second conductivity type region25,80at a second end of the fin structure20opposite a first end of the fin structure20that is in contact with the first conductivity type region15. The term “conductivity type” as used herein denotes a p-type conductivity or an n-type conductivity. In some embodiments, the first conductivity type region15may be composed of a first conductivity type semiconductor material, such as a type IV semiconductor having an n-type conductivity. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In some embodiments, the second conductivity type region25,80may be composed of at least one second conductivity type semiconductor material, such as a type IV semiconductor having a p-type conductivity. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons.

Examples of type IV semiconductors that are suitable for use as the semiconductor material for the first conductivity type region15, and the second conductivity type region25,80may include silicon (Si), crystalline silicon (c-Si), monocrystalline silicon, germanium, silicon germanium (SiGe), silicon doped with carbon (Si:C), silicon germanium doped with carbon (SiGe:C) and a combination thereof, and similar semiconductors, e.g., semiconductor materials including at least one element from Group IVA (i.e., Group 14) of the Periodic Table of Elements. In a type IV semiconductor material, examples of n-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium. The dopant that provides the n-type conductivity for the first conductivity type semiconductor material that provides the first conductivity type region15may be present in a concentration ranging from 1×1019atoms/cm3to 4×1020atoms/cm3. The dopant that provides the p-type conductivity of the second conductivity type semiconductor material that provides the second conductivity type region25,80may be present in a concentration ranging from 1×1017atoms/cm3to 2×1019atoms/cm3.

The at least one second conductivity type semiconductor material25,80may include a first portion25that is formed on the material stack that includes the material layer for the fin structure20, in which the first portion25is patterned during the process sequence that patterns the fin structure20. The second portion80of the at least one second conductivity type semiconductor material25,80may be an epitaxially formed material that is formed after the fin structure20has been patterned. In some embodiments, the dopant concentration of the epitaxial formed material the provides the second portion80of the at least one second conductivity type semiconductor material25,80is greater than the dopant concentration of the first portion25of the second conductivity type semiconductor material25,80.

The first conductivity type region15and the second conductivity type region25are present on opposing ends of a fin structure20that provides the vertically orientated semiconductor base region of the semiconductor diode. As used herein, a “fin structure” refers to a semiconductor material, which is employed as the body of a semiconductor diode, in which the gate structure is positioned around the fin structure such that charge flows down the fin structure. Fin structures20have a greater height H1than width W1. For example, the fin structure20can have a height H1ranging from 5 nm to 200 nm. In another embodiment, the fin structure20has a height H1ranging from 10 nm to 100 nm. In one example, the fin structure20has a height H1ranging from 20 nm to 50 nm. In one embodiment, the fin structure20can have a width W1of less than 15 nm. In another embodiment, the fin structure20has a width W1ranging from 3 nm to 8 nm.

The fin structure20may be composed of an intrinsic semiconductor, such as an intrinsic type IV semiconductor material. By “intrinsic” it is meant that the region is not doped with an extrinsic dopant, e.g., n-type or p-type dopant. In some embodiments, an intrinsic semiconductor, also called an undoped semiconductor or i-type semiconductor, is a pure semiconductor without any significant dopant species present. The number of charge carriers is therefore determined by the properties of the material itself instead of the amount of impurities. In some embodiments, in intrinsic semiconductors the number of excited electrons and the number of holes are substantially equal. In one example, the maximum amount of n-type or p-type dopant that may be present in the semiconductor material that provides the fin structure20may be no greater than 5×1018atoms/cm3. In another example, the maximum amount of n-type or p-type dopant that may be present in the semiconductor material that provides the fin structure20may be no greater than 5×1017atoms/cm3. In yet another example, the fin structure20may be doped with p-type dopant, i.e., having a same conductivity as the anode region, in which the dopant is present at a concentration of 5×1016atoms/cm3.

Examples of type IV semiconductor that are suitable for the fin structure20include silicon (Si), crystalline silicon (c-Si), monocrystalline silicon, germanium, silicon germanium (SiGe), silicon doped with carbon (Si:C), silicon germanium doped with carbon (SiGe:C) and a combination thereof, and similar semiconductors, e.g., semiconductor materials including at least one element from Group IVA (i.e., Group 14) of the Periodic Table of Elements.

The fin structure20that provides a semiconductor base region for the semiconductor diode100, e.g., field effect diode (FED), that is vertically orientated. By “vertical” semiconductor diode it is meant that the first conductivity type region15, the semiconductor base region provided by the fin structure20and the second conductivity type region25,80are arranged perpendicular to the plane of the substrate10surface, which is referred to as a vertical stack. A vertically stacked semiconductor diode can have a longer gate length (i.e., height) than a horizontal semiconductor diode in which the first conductivity type region, the second conductivity type region, and the semiconductor base region components are arranged parallel with the plane of the substrate surface).

Still referring toFIG. 1, the semiconductor device, e.g., field effect diode (FED), includes a vertically orientated dual gate structure110around the fin structure20. The vertically orientated dual gate structure110includes a first gate structure70that is present closest to the first conductivity type region15and the supporting substrate10, and a second gate structure75that is in closer proximity to the second conductivity type region25,80than the first conductivity type region15. In some embodiments, the first gate structure70is separated from the second gate structure75by a dielectric inter-gate spacer50. The term “vertically orientated” when describing the dual gate structure means that the first gate structure70, the inter-gate spacer50and the second gate structure75arranged perpendicular to the plane of the substrate10surface.

The first gate structure70includes a first gate dielectric65aand a first gate conductor66a. In some embodiments, the first gate structure70is separated from the first conductivity type region15by a first dielectric spacer41. The first dielectric spacer41may be composed of any dielectric material, such as an oxide, nitride or oxynitride material. In one example, the first dielectric spacer41is composed of a nitride, such as silicon nitride. In some embodiments, a dielectric liner40is present between the first dielectric spacer41and the first conductivity type region15. The dielectric liner40may be composed of any dielectric material, such as an oxide, nitride or oxynitride material. In one embodiment, the dielectric liner40is composed of an oxide, such as silicon oxide.

In one embodiment, the at least one gate dielectric65aof the first gate structure70includes, but is not limited to, an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides. In one example, when the at least one gate dielectric layer65ais comprised of an oxide, the oxide may be selected from the group including, but not limited to, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixture thereof. In some embodiments, the at least one gate dielectric layer65acan be composed of a high-k dielectric material. High-k dielectric materials have a dielectric constant greater than silicon oxide (SiO2). For example, high-k dielectrics having a dielectric constant greater than 4.0 at room temperature, e.g., 20° C. to 25° C. and atmospheric pressure, e.g., 1 atm. In one embodiment, the least one gate dielectric layer65amay be provided by a high-k dielectric material. In one embodiment, the least one gate dielectric layer65ais composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixtures thereof. Other examples of high-k dielectric materials for the at least one first gate dielectric layer65ainclude hafnium silicate, hafnium silicon oxynitride or combinations thereof. The at least one first gate dielectric65amay be in direct contact with a sidewall of a lower portion of the fin structure20. The physical thickness of the at least one first gate dielectric layer65amay vary, but typically, the at least one first gate dielectric layer65acan have a thickness from 1 nm to 10 nm. In another embodiment, the at least one first gate dielectric layer65ahas a thickness from 1 nm to 3 nm. The thickness of the at least one first gate dielectric layer65ais uniform and continuous.

The at least one first gate dielectric layer65amay have a U-shaped geometry when viewed from a side cross-sectional view, as depicted inFIG. 1. A vertical portion of the at least one first gate dielectric layer65ais present on a lower portion of the fin structure20, and horizontal portions of the at least one first gate dielectric layer65aare present on the first dielectric spacer41and the dielectric inter-gate spacer50.

The conductive material that provides the first gate conductor66amay comprise polysilicon, SiGe, a silicide, a metal or a metal-silicon-nitride such as Ta—Si—N. Examples of metals that can be used as the first gate conductor66ainclude, but are not limited to, Al, W, Cu, and Ti or other like conductive metals.

The second gate structure75includes a second gate dielectric65band a second gate conductor66b. A second dielectric spacer42may be present on an uppermost surface of the second gate structure75. The second dielectric spacer42may be composed of any dielectric material, such as an oxide, nitride or oxynitride material. In one example, the second dielectric spacer42is composed of a nitride, such as silicon nitride.

The second gate structure75is similar to the first gate structure70, in which the second gate structure75is present on an upper portion of the fin structure20that is closest to the second conductivity type region25,80and the first gate structure70is present on a lower portion of the fin structure20. Similar to the first gate structure70, the second gate structure includes at least one gate dielectric (referred to as the at least one second gate dielectric65b) and a gate conductor (referred to as the second gate conductor66b). Therefore, the above description of the composition and geometry for the at least one first gate dielectric65aand the first gate conductor66afor the first gate structure70is suitable for describing at least one embodiment of the composition and geometry for the at least one second gate dielectric65band the second gate conductor66b. For example, the second gate dielectric65bmay have a U-shaped geometry when viewed from a side cross-sectional perspective, as depicted inFIG. 1.

The inter-gate spacer50separates the first gate structure70from the second gate structure75. The inter-gate spacer50may be composed of a dielectric material. Any dielectric material may be suitable for the inter-gate spacer50. For example, the dielectric used for the inter-gate spacer50may be an oxide containing material, nitride containing material, oxynitride containing material or a combination thereof. In some examples, the dielectric material for the integrate spacer50may be a low-k dielectric material. As used herein, the term “low-k” denotes a dielectric material having a dielectric constant equal to the dielectric constant of silicon oxide (SiO2) or less at room temperature, e.g., 20° C. to 25° C. and atmospheric pressure, e.g., 1 atm. Examples of materials suitable for the low-k dielectric material include SiBCN, SiOCN, SiOC diamond like carbon (DLC), organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, carbon doped silicon nitride, porous silicon dioxide, porous carbon doped silicon dioxide, boron doped silicon nitride, spin-on organic polymeric dielectrics (e.g., SILK™) spin-on silicone based polymeric dielectric (e.g., hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinations thereof. In some examples, the dielectric material for the integrate spacer50may be a high-k dielectric material. High-k dielectric materials have a dielectric constant greater than silicon oxide (SiO2). For example, high-k dielectrics having a dielectric constant greater than 4.0 at room temperature, e.g., 20° C. to 25° C. and atmospheric pressure, e.g., 1 atm. In one embodiment, the least one gate dielectric layer may be provided by a high-k dielectric material. In one embodiment, the least one gate dielectric layer is composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3and mixtures thereof. Other examples of high-k dielectric materials for the dielectric inter-gate spacer50include hafnium silicate, hafnium silicon oxynitride or combinations thereof.

In some embodiments, the inter-gate spacer50has a height H2as great as 150 nm. In one embodiment, the inter-gate spacer50has a height H2ranging from 2 nm to 100 nm. In some embodiments, the inter-gate spacer50has a width W2that is selected to be as small as possible to provide higher device density. In one example, the inter-gate spacer50has a width W2ranging from 10 nm to 100 nm.

In one embodiment, the length of a first gate structure70in the vertically orientated dual gate structure is the same as the length of a second gate structure75. In another embodiment, the length of the first gate structure70in the vertically orientated dual gate structure is the greater than a length of the second gate structure75.

Still referring toFIG. 1in some embodiments, an interlevel dielectric layer85can be present overlying the fin structure20, the first conductivity type semiconductor material that provides the first conductivity type region15, the second conductivity type semiconductor material that provides the second conductivity type region25,80and the vertically orientated dual gate structure110. The interlevel dielectric layer80may be composed of any dielectric material, such as an oxide, nitride or oxynitride material. For example, the interlevel dielectric layer85may be composed of any dielectric material used in microelectronic and nanoelectronic structures, which can include SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H).

The semiconductor diode100, e.g., field effect diode (FED), can further include an anode contact90aextending through an interlevel dielectric layer85to the first conductivity type region15, and a cathode contact90cextending through the interlevel dielectric layer85to the second conductivity type region25,80. The semiconductor diode100can also include a first gate contact90bextending through the interlevel dielectric layer85to the first gate structure70, and a second gate contact90dthrough the interlevel dielectric layer85to the second gate structure75. Each of the anode contact90a, first gate contact90b, cathode contact90cand second gate contact90dmay be composed of an electrically conductive material, such as a metal or a doped semiconductor material. The metal may be one of copper, aluminum, titanium, tungsten, platinum or combinations thereof. The doped semiconductor material may be polysilicon doped with an n-type dopant. The first gate contact90bin reaching the first gate structure70may extend past the second gate structure75, wherein electrical isolation from the second gate structure75may be provided by a dielectric via liner86that is present on the sidewall of the portion of via containing the first gate contact90bat the depth at which the second gate structure75is present. The dielectric via liner86separates the electrically conductive portion of the first gate contact90bfrom the second gate structure75. The dielectric via liner86is not present at the base of the via at which the first gate contact90bis in electric contact, i.e., direct contact, with the first gate structure70. The dielectric via liner86may be composed of any dielectric material, such as oxide containing dielectrics, nitride containing dielectrics, oxynitride containing dielectrics or combinations thereof.

In some embodiments, the semiconductor diode100, e.g., field effect diode (FED), depicted inFIG. 1includes a vertically orientated channel having length defined by its height H1that is encapsulated by two independent gate structures, the first gate structure70and the second gate structure75, in which the gate structures70,75are separated by the inter-gate spacer50(also referred to as gap dielectric). The semiconductor device100, e.g., field effect diode (FED), depicted inFIG. 1has oppositely doped terminals, i.e., first conductivity type region15and second conductivity type region25,80.

In operation, the first gate structure70is biased high with respect to the second gate structure75creating an inverted n-type body device proximate to the first gate structure70. In this state, the semiconductor diode100, e.g., field effect diode (FED), acts as PNPN diode structure. In some embodiments, which the voltage to the first gate structure70is high with respect to the second gate structure75most of the anode voltage is dropped across the reversed biased junction that is present between the two gate structures, thus preventing current from passing through the dual gated semiconductor diode100, in which the dual gated semiconductor diode100is in an “OFF” state. In some embodiments, during an electrostatic discharge event (ESD), the dual gated semiconductor diode100is changed to a different state, in which the first gate structure70is left floating, or shorted to the second gate structure75, hence allowing the field effect diode (FED), i.e., semiconductor diode100, to act as one PN junction. In some embodiments, the dual gated field effect diode (FED) has reduced capacitance in the “OFF”, i.e., normal operation, state due to the existence of three junctions in series, one of which is reverse biased (PNPN).FIG. 2includes field effect diode (FED) states for different gate and anode biases in accordance with one embodiment of the semiconductor device100.

It is noted that the device described herein is symmetrical in geometry. Therefore, the anode and cathode may be reversed. For example, if the structure identified by reference number90cis a cathode, and the structure identified by reference number90ais an anode, then the structures identified by reference numbers80and25can be n-type doped, i.e, n+, whereas the structure identified by reference number15is to be p-type doped, i.e., p+. In another example, if the structure identified by reference number90cis an anode and the structure identified by reference number90ais a cathode, then the structures identified by reference numbers80and25can be p-type doped, i.e., p+, whereas the structure identified by reference number15is to be n-type doped, i.e., n+. Following the orientation inFIGS. 1 and 2, the gate structure next to the anode is the first gate structure, while the gate next to the cathode is the second gate structure. In the embodiments, in which the anode and cathode are swapped, the first gate structure and second gate structure are also swapped.

FIGS. 3-7depict one embodiment of a method for forming the vertically orientated semiconductor diode100including the vertically orientated dual gate structure110that has been described above with reference toFIGS. 1 and 2. In one embodiment, the method of forming the semiconductor diode100, e.g., field effect diode (FED), includes the steps of forming a fin structure20of a base semiconductor material having a first end present on a first conductivity type semiconductor material that provides a first conductivity type region15, wherein a second type conductivity semiconductor material is present at a second end of the fin structure20that provides a second conductivity type region25,80; and forming a vertically orientated dual gate structure110on the fin structure30.

FIG. 3depicts one embodiment of a material stack5for forming one embodiment of a semiconductor diode100, e.g., field effect diode (FED). In one embodiment, the material stack5may be provided by forming a layer of the first conductivity type semiconductor material (for the first conductivity type region15) present on a supporting substrate10, and forming a layer of the base semiconductor material (for the fin structure20) on the layer of the first conductivity type semiconductor material. Thereafter, a layer for the second conductivity type semiconductor material (for the second conductivity type region25) is formed on layer of the first conductivity type semiconductor material.

The supporting substrate10may be composed of semiconductor material, such as a type IV semiconductor or a type III-V semiconductor. For example, the supporting substrate10may be composed of silicon (Si). In some embodiments, the supporting substrate10is a bulk substrate, as depicted inFIG. 3. It is noted that the supporting substrate10may also be provided by a semiconductor on insulator (SOI) substrate, i.e., silicon on insulator substrate.

The first conductivity type semiconductor material for the first conductivity type region15may be epitaxially formed on the supporting substrate10using an epitaxial growth process. The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown,” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline over layer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. A material that is “epitaxial” is a material that has been formed using an epitaxial deposition process.

The first conductivity type semiconductor material for the first conductivity type region15may can be a type IV semiconductor containing material layer. For example, the first conductivity type semiconductor material for the first conductivity type region15may be composed of silicon (Si), germanium (Ge), silicon germanium (SiGe) and other semiconductor materials. The epitaxial deposition process may employ the deposition chamber of a chemical vapor deposition type apparatus, such as a PECVD apparatus. In some embodiments, the gas source for the epitaxial deposition of the first conductivity type semiconductor material for the first conductivity type region15may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane and combinations thereof. The temperature for epitaxial silicon germanium deposition typically ranges from 450° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.

The first conductivity type semiconductor material for the first conductivity type region15is doped with either an n-type or p-type dopant. In the embodiment that is described with reference toFIGS. 1-7, the first conductivity type is n-type and the second conductivity type is p-type. In other embodiments, the first conductivity type may be p-type and the second conductivity type can be n-type.

The dopant that provides the conductivity type for the first conductivity type semiconductor material for the first conductivity type region15may be introduced to the semiconductor material using “in situ” doping. The term “in situ” denotes that the dopant, e.g., n-type or p-type dopant, is introduced to the base semiconductor material, e.g., silicon or silicon germanium, during the formation of the base material. For example, an in situ doped epitaxial semiconductor material may introduce n-type or p-type dopants to the material being formed during the epitaxial deposition process that includes n-type or p-type source gasses. In one embodiment, the n-type gas dopant source may include arsine (AsH3), phosphine (PH3) or combinations thereof. In one example, the first conductivity type semiconductor material for the first conductivity type region15may be in-situ doped to provide the n-type conductivity that is provided by a phosphorus dopant.

Following the formation of the first conductivity type semiconductor material for the first conductivity type region15, a base semiconductor material is formed for the fin structure20. The semiconductor base region provided by the fin structure20may be epitaxially formed directly on the first conductivity type semiconductor material for the first conductivity type region15. Similar to the first conductivity type region15, the semiconductor material for the semiconductor base region for the fin structure20may be a type IV semiconductor material, such as silicon or silicon germanium. Therefore, the above description of the epitaxial deposition process for forming the first conductivity type semiconductor material for the first conductivity type region15is suitable for describing at least one embodiment of forming the base semiconductor material for the fin structure20. The deposition process is continued until the thickness of the semiconductor base region is equal to the desired height of the fin structure20.

Still referring toFIG. 3, the layer for the second conductivity type semiconductor material for the second conductivity type region25is formed on layer of the first conductivity type semiconductor material using an epitaxial deposition process. Similar to the first conductivity type semiconductor material, the second conductivity type semiconductor material may be composed of a type IV semiconductor, such as silicon, silicon germanium and/or germanium. Therefore, the above description of the epitaxial deposition process for forming the first conductivity type semiconductor material for the first conductivity type region15is suitable for describing at least one embodiment of forming the second conductivity type semiconductor material for the second conductivity type region25. The second conductivity type region25is doped to an opposite conductivity type than the conductivity type of the first conductivity type region15. For example, if the first conductivity type region15is doped to an n-type conductivity, the second conductivity type region25is doped a p-type conductivity. The p-type dopant may be introduced to the second conductivity type region25by in situ doping. The p-type dopant that provided the p-type conductivity for the second conductivity type region25may be boron. The p-type gas dopant source may include diborane (B2H6).

FIG. 4depicts one embodiment of patterning and etching the material stack5depicted inFIG. 3to form a fin structure20that provides a vertically orientated semiconductor base region on a surface of a first type conductivity semiconductor material15, wherein a second conductivity type semiconductor material25is present at an end of the fin structure20opposite the end of the fin structure20that is in contact with the first type conductivity semiconductor material15. In one embodiment, the patterning and etching of the material stack5includes etching at least the layer of the second conductivity type semiconductor material25and the layer of the base semiconductor material of the material stack to form the fin structure30of the base semiconductor material having a first end present on a first conductivity type semiconductor material15. The second type conductivity semiconductor material25is present at a second end of the fin structure20opposite the first end.

Patterning and etching the material stack5may begin with forming a hardmask, i.e., dielectric fin cap35, atop the material layer of the second type conductivity semiconductor material25. Any dielectric material may be present in the dielectric fin cap35. For example, the dielectric fin cap35may be provided by an oxide, e.g., silicon oxide, or nitride, e.g., a silicon nitride. The hardmask layer may be deposited using chemical vapor deposition process, such as chemical vapor deposition (CVD).

Following formation of the hardmask layer, an etch mask may be formed over the hard mask layer that is patterned to define the dielectric fin cap35using an etch process. The etch mask may be a photoresist mask that is formed using deposition, photolithography and development steps. The width of the etch mask is selected to provide the width of the dielectric fin cap35. The dielectric fin cap35can be used to etch the underlying second conductivity semiconductor material for the second conductivity type region25, and the underlying base semiconductor material that provides the fin structure20. Following formation of the etch mask, the pattern of the etch mask may be transferred into the hardmask layer to provide the dielectric fin cap35. The pattern transfer may be achieved by utilizing at least one etching process that can include dry etching, such as reactive ion etching (RIE), plasma etching, ion beam etching or laser ablation, chemical wet etch processes or a combination thereof. In one embodiment, the etch process for forming the dielectric fin cap35is an anisotropic etch process. In one example, the etch process used to transfer the pattern may include one or more reactive ion etching (RIE) steps. In some embodiments, the etch process may be an etch process including a chemistry that is selective to the semiconductor material for the second conductivity type region25. In this example, following patterning the hardmask dielectric layer to provide the dielectric fin cap35, a second etch process may etch the semiconductor material layers that provide the second conductivity type region25, and the base semiconductor material that provides the fin structure20. In some embodiments, the second etch process may be selective to first conductivity type semiconductor material of the first conductivity type region15. The etch mask may then be removed. It is noted that the aforementioned process flow is only one example of forming a fin structure20. In another embodiment, the fin structure25may be formed using a spacer image transfer (SIT) process.

FIGS. 5-7illustrate one embodiment of forming a vertically orientated dual gate structure110. The vertically orientated dual gate structure110is present around the fin structure20and includes a first gate structure70that is present overlying the semiconductor substrate10and a second gate structure75that is in closer proximity to the second conductivity type semiconductor material of the second conductivity type region25than the first conductivity type semiconductor material of the first conductivity type region15. The first gate structure70is separated from the second gate structure75by a dielectric inter-gate spacer50. In some embodiments forming the vertically orientated dual gate structure110includes applying a replacement gate structure that can begin with forming a dielectric liner40on at least the fin structure20.

FIG. 5depicts forming a thin dielectric liner40on the structure depicted inFIG. 4, and forming sacrificial gate structures45a,45bon the thin dielectric liner40over the fin structure20that provides the vertically orientated semiconductor base region of the device. The thin dielectric liner40may be deposited using a deposition process, such as chemical vapor deposition (CVD). Variations of CVD processes include, but not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. The thin dielectric liner40may be a continuous layer of a conformal thickness. The term “conformal” denotes a layer having a thickness that does not deviate from greater than or less than 30% of an average value for the thickness of the layer. The thin dielectric liner40may have a thickness ranging from 1 nm to 10 nm. In one example, the thin dielectric liner40is composed of silicon oxide.

Following the formation of the thin dielectric liner40, the method may continue with forming a gate stack comprising a first dielectric spacer41on a portion of the dielectric liner40overlying the first conductivity type semiconductor material15present on the supporting substrate10; forming a first sacrificial gate structure45aon the first dielectric spacer41; forming a dielectric inter-gate spacer50on the first sacrificial gate structure45a; and forming a second sacrificial gate structure45bon the dielectric inter-gate spacer50, as depicted inFIG. 5.

The first dielectric spacer41is composed of a dielectric material, such as a nitride, e.g., silicon nitride, which is formed directly atop the thin dielectric liner40. The first dielectric spacer41may be deposited using a chemical vapor deposition (CVD) process like the CVD processes described for forming the dielectric liner40. For example, the first dielectric spacer41can be deposited using plasma enhanced chemical vapor deposition (PECVD), and can have a thickness ranging from 5 nm to 20 nm. The material layer for the first dielectric spacer41is blanket deposited.

Following the material layer for the first dielectric spacer41, a material layer for the first sacrificial gate structure45ais formed. The first sacrificial gate structure45ais composed of a material that may be removed selectively to at least the dielectric inter-gate spacer50. The term “selective” means that a first material may be etched at a faster rate to a second material. For example, the selective etch rate may remove a first material at a rate greater than 20:1, e.g., greater than 100:1, in comparison to a second material. In some embodiments, the first sacrificial gate structure45amay be composed of a material that can be removed selectively to the dielectric liner40that is present on the sidewall of the fin structure20. In one example, the first sacrificial gate structure45ais composed of polysilicon. The material layer for the first sacrificial gate structure45amay be deposited using a chemical vapor deposition (CVD) process, such as Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof. The thickness of the material layer for the second sacrificial gate structure45bis selected to provide the dimensions for the second functional gate structure, i.e., second gate structure75. In one example, the thickness of the material layer for the first sacrificial gate structure45amay range from 10 nm to 100 nm.

Following the material layer for the first sacrificial gate structure45a, a material layer for the dielectric inter-gate spacer50is formed. The dielectric inter-gate spacer50provides that the first gate structure70and the second gate structure75are electrically isolated from one another, in which the thickness of the material layer for the dielectric inter-gate spacer50dictates the vertical offset separating the first gate structure70from the second gate structure75. In one example, the material layer for the inter-gate spacer50can be composed of a nitride, such as silicon nitride. The material layer for the dielectric inter-gate spacer50may be deposited using a chemical vapor deposition (CVD) process, such as Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereof. The thickness of the material layer for the dielectric inter-gate spacer50may range from 10 nm to 100 nm.

Following the formation of the material layer for the dielectric inter-gate spacer50, a material layer for the second sacrificial gate structure45bmay be formed directly on the dielectric inter-gate spacer50. The second sacrificial gate structure45bis similar to the first sacrificial gate structure45a. Therefore, the description of forming the first sacrificial gate structure45ais suitable for describing one embodiment of forming the second sacrificial gate structure45b. For example, the second sacrificial gate structure45bmay be composed of polysilicon. The thickness of the material layer for the second sacrificial gate structure45bis selected to provide the dimensions for the second functional gate structure, i.e., second gate structure75. In one example, the thickness of the material layer for the second sacrificial gate structure45bmay range from 10 nm to 100 nm.

A material layer for the second dielectric spacer42may be formed directly on the second sacrificial gate structure45b. The second dielectric spacer42is similar to the first dielectric spacer41. Therefore, the description of forming the first dielectric spacer41is suitable for describing one embodiment of forming the second dielectric spacer42. For example, the second dielectric spacer42may be composed of a nitride, such as silicon nitride. In one example, the thickness of the material layer for the second dielectric spacer42may range from 5 nm to 20 nm.

Following the formation of the material layer for the second dielectric spacer42, an oxide capping layer55is formed atop the second dielectric spacer42. The oxide capping layer55may be composed of silicon oxide. The oxide capping layer55may be deposited using a CVD deposition process followed by a planarization process, such as chemical mechanical planarization to provide an upper surface that is coplanar with the portion of the dielectric liner40that is present atop the dielectric fin cap35.

The aforementioned material layers may then be patterned and etched to provide the geometry of the vertically orientated dual gate structure110. More specifically, a photoresist etch mask may be formed atop the oxide capping layer55. The material stack can then be etched with an etch process, such as an anisotropic etch process, e.g., reactive ion etching (RIE), to provide the geometry of the vertically orientated dual gate structure110.

Forming the vertically orientated dual gate structure110may also include substituting the first and second sacrificial gate structures45a,45bwith first and second functional gate structures70,75, as described with reference toFIGS. 6 and 7.

FIG. 6depicts one embodiment of removing the sacrificial gate structures45a,45band removing the exposed portion of the thin dielectric liner40selectively to the fin structure20providing the vertically orientated semiconductor base region. In one embodiment, removing the sacrificial gate structures45a,45bincludes etching the first and second sacrificial gate structures45a,45bselectively to at least the dielectric inter-gate spacer50and the dielectric liner40that is present on the fin structure20. Thereafter, the exposed portions of the dielectric liner50may be removed by an etch process that is selectively to the fin structure20. The etch process for removing the exposed portions of the dielectric liner40can be an isotropic etch process.

Functional gate structures70,75are formed in the openings produced by removing the sacrificial gate structures45a,45b. The functional gate structures70,75function to switch a semiconductor diode100from an “on” to “off” state, and vice versa.

FIG. 7depicts forming gate structures70,75including forming a gate dielectric65a,65bon exposed portions of the fin structure20that provides the vertically orientated semiconductor base region of the device, and forming a gate conductor66a,66bon the gate dielectric65a,65b. The gate dielectric65a,65bmay be deposited using a conformal deposition process, e.g., plasma enhanced chemical vapor deposition. Each gate dielectric65a,65bmay have a U-shaped geometry when viewed from the side cross-sectional view depicted inFIG. 7. For example, a vertically orientated portion of each gate dielectric65a,65bmay be present on the fin structure20, and horizontally orientated portions of the gate dielectrics65a,65bmay be formed on the sidewalls of the first dielectric spacer41, the second dielectric spacer42and the dielectric inter-gate spacer50that are exposed by removing the sacrificial gate structures45a,435b. In some embodiments, the gate dielectric65afor the first gate structure70may have a same composition as the gate dielectric65bfor the second gate structure75. In some embodiments, the first gate dielectric65afor the first gate structure70may have a different composition as the second gate dielectric65bfor the second gate structure75. In some embodiments, the gate dielectrics65a,65bmay be composed of high-k dielectric materials, such as hafnium oxide.

Following the formation of the gate dielectrics65a,65b, gate conductors66a,66bmay be formed directly on the gate dielectrics65a,65b. The gate conductors66a,66bfill the openings formed by removing the sacrificial gate structures45a,45b. In some embodiments, the gate conductor66afor the first gate structure70may have a same composition as the gate conductor66bfor the second gate structure75. In some embodiments, the gate conductor66afor the first gate structure70may have a different composition as the gate conductor66bfor the second gate structure75. The gate conductors66a,66bmay be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating and/or plating.

Referring toFIG. 1, in some embodiments, the oxide capping layer55, the dielectric fin structure35and the dielectric liner40that are present on a portion of the second conductivity type region25are removed to expose the portion of the second conductivity type region25that is present atop the fin structure20. The oxide capping layer55, the dielectric fin structure35and the exposed portion of the dielectric liner40may be removed by an etch process, such as an etch process that is selective to the second conductivity type region25. Thereafter, a second conductivity type epitaxial semiconductor material80is formed on the second conductivity type region25. The second conductivity type epitaxial semiconductor material80has the same conductivity type as the second conductivity region25on which the second conductivity type epitaxial semiconductor material80is directly formed. In some embodiments, the second conductivity type epitaxial semiconductor material80has a diamond geometry. In some embodiments, the second conductivity type epitaxial semiconductor material80may be composed of silicon, a silicon carbon alloy (e.g., silicon doped with carbon (Si:C), silicon germanium, a silicon germanium and carbon alloy (e.g., silicon germanium doped with carbon (SiGe:C), silicon alloys, germanium, germanium alloys, gallium arsenic, indium arsenic, indium phosphide, as well as other III/V and II/VI compound semiconductors. The second conductivity type epitaxial semiconductor material80is grown using an epitaxial growth or deposition process that may be a selective deposition process. For example, although the epitaxially semiconductor material for the second conductivity type epitaxial semiconductor material80orientates to the crystal arrangement of a semiconductor material, the material may not be deposited on the dielectric material of the second dielectric spacer42.

In some embodiments, an interlevel dielectric layer85is formed overlying the fin structure20, the first conductivity type semiconductor material for the first conductivity type region15, the second conductivity type semiconductor material for the second conductivity type region25,80and the vertically orientated dual gate structure110. The interlevel dielectric layer85may be deposited using chemical vapor deposition (CVD) and/or spin on deposition.

Still referring toFIG. 1, in some embodiments, the method may further include forming an anode contact90a, first gate contact90b, cathode contact90cand second gate contact90dthrough the interlevel dielectric layer85. The anode contact90aextends into contact with the first conductivity type semiconductor material15. The cathode contact90cextends into contact with the second conductivity type epitaxial semiconductor material80. The second gate contact90dextends into contact with the gate conductor66bof the second gate structure75. The first gate contact90bextends past the second gate structure77into contact with the gate conductor66aof the first gate structure70. The electrically conductive structure of the first gate contact90bis separated from the second gate conductor66bby a dielectric via liner86. In some embodiments, the contacts90a,90b,90c,90dare formed by forming vias, i.e., openings, through the interlevel dielectric layer85, and then filling the openings with electrically conductive material, e.g., metals, doped semiconductors and combinations thereof. The via opening may be formed using photolithography and etch processes. For example, a photoresist mask may be formed exposing the portion of the dielectric material layers in which the via opening is to be formed, wherein following formation of the photoresist mask, the via opening may be etched into the interlevel dielectric85using an etch process, such as reactive ion etch (RIE). The via opening may be filled with a metal, such as copper, aluminum, titanium, tungsten, platinum or combinations thereof. The electrically conductive material may be deposited into the via opening using physical vapor deposition (PVD). Examples of PVD processes suitable for depositing the metal for the contacts90a,90b,90c,90dinclude plating, electroplating, electroless plating, sputtering and combinations thereof.

In some embodiments, the dielectric via liner86for the first gate contact90bis formed on the via sidewalls before filling the via with an electrically conductive fill, e.g., metal. The dielectric via liner86may be composed of an oxide, nitride or oxynitride material. In one example, the dielectric via liner86may be composed of silicon nitride. The dielectric via liner86may be deposited using chemical vapor deposition, e.g., plasma enhanced chemical vapor deposition (PECVD). After depositing the material for the dielectric via liner86, an anisotropic etch process, such as reactive ion etch (RIE) may remove a portion of the dielectric via liner86that is present at the base of the via. Thereafter, the via is filled with electrically conductive material to provide the first gate structure contact90bthat is in electric communication with the gate conductor66aof the first gate structure70.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.