Semiconductor data processor

A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.

FIELD OF THE INVENTION

The present invention relates to the access control of a data processor having an on-chip memory, particularly, the on-chip memory, and to a technique which is effectively applied to the microcomputer of a single chip, for example.

BACKGROUND OF THE INVENTION

In a data processor, a high speed memory has been built in to enhance a performance. For example, a high speed memory having a built-in data processor is provided in the address space of a CPU (central processing unit) in the same manner as an external memory and is thus used. Moreover, the built-in memory is utilized as a cache memory to constitute a cache system, thereby increasing the speed of a memory access. The former example has been disclosed in JP-A-5-307485 publication and the latter case has been disclosed in JP-A-6-103064 publication.

SUMMARY OF THE INVENTION

In the former example, a performance cannot be enhanced even if the memory is simply built in the data processor. It is necessary to previously investigate a memory area to which reference is often made in an operating program and to allocate the same portion to a data processor built-in memory. In short, the way of the address mapping of the built-in memory corresponding to an operating program to be executed by the data processor greatly influences a data processing performance.

In the latter example, moreover, the frequency of the access of the memory area is automatically decided and is stored in a cache memory every memory access from the program. For this reason, it is not necessary to previously investigate the memory area to which reference is often made. However, an access pattern which cannot obtain an enhancement in a performance is present according to an algorithm for deciding the frequency of the access. More specifically, the memory access performance of the cache memory can be enhanced when the same data are accessed plural times. To the contrary, the memory access performance is deteriorated for image data to be sequentially scanned in series in some cases. For example, in a general algorithm, the performance cannot be enhanced in some situations in which a program for sequentially memory accessing (sequential access) a certain memory area from a start address to an end address at each time and a program for randomly accessing (random access) various addresses are artificially executed at the same time by time sharing.

It is an object of the invention to provide a semiconductor data processor which can easily enhance an access performance for a built-in memory.

It is another object of the invention to provide a semiconductor data processor capable of efficiently carrying out a sequential access without deteriorating the performance of a random access for a built-in memory.

It is a further object of the invention to provide a semiconductor data processor capable of easily enhancing an access performance for both a sequential access and a random access for a built-in memory.

The above and other objects and novel features of the invention will be apparent from the following description of this specification and the accompanying drawings.[1] A semiconductor data processor has a first memory constituting a cache memory, a second memory capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.

There is supposed a utilization configuration which is hard to expect the advantages of an increase in the speed of the access by the cache memory as in a sequential access. When the second memory to be the non-cacheable area is to be sequentially accessed, data responding to the sequential access are output from the read buffer so that a sequential read access can be carried out at a high speed. In the sequential access, the cache operation of the first memory is not carried out and cache entry data retained in the first memory can be prevented from being undesirably rewritten or replaced based on sequential access data which have a low possibility of a re-access. Consequently, it is possible to efficiently carry out the sequential access without deteriorating the performance of a random access for a built-in memory.

As a desirable manner of the invention, the read buffer temporarily holds predetermined access data and address when the second memory is accessed as the non-cacheable area. For example, when the second memory is accessed, data and an address corresponding to the access are newly held if the read buffer does not retain the data corresponding to the access. The data thus held are output from the read buffer in place of the read access of the second memory. In short, the read buffer is operated to hold data including the contents of a last memory access and to output the held data in place of the access of the second memory in response to the detection of the access of the same data as the held data if any.

As a desirable manner of the invention, the read buffer is connected to a first bus at an upstream side of a read request and is connected to a second bus at a downstream side of the read request. The second bus can transmit data in the number of parallel bits which is equal to or larger than the number of parallel access data bits by the first bus. The data to be sequentially accessed can be collectively stored in the read buffer via the second bus. The read buffer can output the stored data in response to a read access to the second memory corresponding to some times.

As a desirable manner of the invention, the read buffer has a data register for holding read data to be transmitted from the first memory through the second bus, an address register for holding an address of the data, and a control circuit for causing the first bus to output the data of the data register for a read request of an address which is coincident with the address held in the address register.

As a desirable manner of the invention, the first bus and the second bus are dedicated sequential access buses. Moreover, there is provided a third bus capable of connecting the first memory to the second memory in a different path from a path formed by the first and second buses when the second memory is accessed as the cacheable area. A peripheral bus interface controller is connected to the third bus if any. An interface control for the second bus dedicated for a dedicated sequential access bus is dedicated. Therefore, the interface control is simple and is convenient to a high speed access.

As a desirable manner of the invention, there is provided an internal memory controller connected to the second bus and the third bus and serving to carry out an access interface control for the second memory. Moreover, the third bus is provided with a secondary cache memory controller for controlling the second memory as a secondary cache memory for the first memory. The secondary cache memory controller cache invalidates the second memory in response to a signal indicative of a cache invalidation of the first memory. Information stored in the primary cache and the secondary cache are conveniently matched with each other. According to the utilization configuration for the second memory, it is preferable that the internal memory controller and the secondary cache memory controller should be exclusively operable. This is preferably set by a control register.[2] A semiconductor data processor has a first memory constituting a cache memory, a second memory capable of being a secondary cache memory or a memory which is not a cache memory for the first memory, and designating means for selectively designating the second memory to the secondary cache memory or the memory which is not the cache memory. The means described above can properly correspond to both the case in which it is desirable that the second memory should be used as the secondary cache memory in respect of a data processing and the case in which it is desirable that the second memory should be used as a memory provided in the address space of a CPU in respect of the data processing. Accordingly, it is easy to enhance an access performance for the second built-in memory corresponding to the data processing configuration of the data processor.

As a desirable manner of the invention, the second memory has a secondary cache memory controller for carrying out an access interface control as the secondary cache memory of the first memory. Moreover, there is provided an internal memory controller for carrying out the access interface control as the memory which is not the cache memory for the second memory. The second memory selected to be the memory which is not the cache memory may be set to be a cacheable area or a non-cacheable area by the first memory. It is also possible to have a read buffer capable of carrying out an operation for outputting data corresponding to the read access of the second memory as the non-cacheable area when performing the same access.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1illustrates a microcomputer according to an example of the invention. A microcomputer1shown inFIG. 1is formed on one semiconductor substrate (semiconductor chip) such as a monocrystalline silicon by a well-known CMOS integrated circuit manufacturing technique.

FIG. 1typically shows an interface portion between a processor core and a built-in memory. A processor core2has a CPU (central processing unit)3, an FPU (floating-point operation unit)4, a primary cache memory controller (L1CC)5, and a primary cache memory (L1CM)6to be a first memory, for example. The CPU3is constituted by an instruction control portion and an executing portion. The instruction control portion fetches an instruction, decodes the instruction thus fetched, and generates a control signal. The executing portion has a general purpose register and an ALU (Arithmetic Logical Unit), and an operation thereof is generated by the control signal and an operation using a fetched operand is carried out. The FPU4is not particularly restricted but receives a floating-point operation command from the CPU3when the CPU3fetches a floating-point instruction, and the CPU3carries out a floating-point operation upon receipt of an accessed operation operand.

The primary cache memory6is not particularly restricted but has an associative memory structure in a set associative configuration. The primary cache memory controller5associatively searches the primary cache memory6when a cacheable area (a cacheable area) is accessed, accesses the primary cache memory6when a cache hit is obtained, and gives a memory access to a lower side of an internal memory20which will be described below if a cache error is made, and thus fetches necessary data and instructions and controls a cache fill for the primary cache memory6and the replacement of a cache entry if necessary. The internal memory20is constituted by an SRAM (static random access memory), for example.

As a path to be used in the memory access on the lower side, an interface bus11for a sequential access which acts as a first bus and an interface bus10for a random access which acts as a third bus are connected to the primary cache memory controller5. The interface bus11for a sequential access is connected to one of the access ports of a read buffer12and the other access port of the read buffer12is connected to an interface bus13to be a second bus. The interface buses10,11and13include signal lines for address, data and access control signals. The number of the parallel access data bits of the interface bus13is set to be equal to or larger than the number of the parallel access data bits of the interface bus11. For example, the number of the parallel access data bits of the interface bus13is 256 and the number of the parallel access data bits of the interface bus11is 64. The number of the parallel access data bits of the interface bus10is 64.

The read buffer12transmits data retained in the read buffer12to the primary cache memory controller5when an access request given from the interface bus11is read and an access request address is coincident with an address stored in the read buffer12. When the access request is the read and the addresses are not coincident with each other, the read buffer12replaces the data width of the access request, for example, replaces 64 bits with 256 bits to issue an interface request to the interface bus13. In case of a write access, moreover, the access request transmitted from the interface bus11is exactly output as an interface request to the interface bus13.

The access request given from the interface bus13is transmitted to an internal memory controller (RAMC)14. The access request given from the interface bus10is transmitted to a peripheral bus interface controller (PBIC)15, and is transmitted therefrom to one peripheral circuit24or more through a peripheral bus23and to the internal memory controller14, and furthermore, a secondary cache memory controller21through an interface bus16to be a third bus.

The internal memory controller14carries out an access interface control for the internal memory20. The secondary cache memory controller21controls the internal memory20as a secondary cache memory for the cache memory6.

The peripheral bus interface controller15has information about address mapping for the peripheral circuit24and the internal memory20, and outputs an access request to the peripheral bus23if an access request given from the interface bus10is to be sent to the peripheral circuit, and outputs the access request to the interface bus16if the same access request is to be sent to the internal memory20. In some cases, the peripheral circuit24includes a bus master module of a DMAC (direct memory access controller) or a bus slave module of a timer counter or a serial interface.

The internal memory controller14mediates the access request given from the interface bus13and the access request given from the interface bus16, and outputs, to a bus17, an access control signal to be sent to the internal memory20. The access request is given from the interface bus13when the internal memory20is to be accessed as the non-cacheable area of the primary cache memory6. On the other hand, the access request is sent through10and16when the internal memory20is to be accessed as the cacheable area of the primary cache memory6. Whether the access request to be given to the internal memory20is the cacheable area of the primary cache memory6is decided by the primary cache memory controller5based on an access address. The designation of a cacheable area (cacheable) and a non-cacheable area (non-cacheable) for the internal memory20is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the internal memory20is mapped. The designation is carried out in the operation mode of a microcomputer1or by setting a control register (not shown), for example.

Moreover, the secondary cache memory controller21compares the address tag of an access address included in an access request given from the interface bus16with a cache tag in the secondary cache memory controller21in response to the same access request, and outputs, to a bus18, the access control signal of a cache entry manipulation for manipulating the internal memory20as a cache memory if a cache hit is obtained.

Either the access control signal sent from the bus17or the access control signal sent from the bus18is transmitted to the internal memory20through a selector19. The internal memory20is accessed in response to the access control signal thus transmitted. If an access operation instruction for the internal memory20is a read access, the internal memory20outputs read data to a bus26and transmits the same data to the internal memory controller14or the secondary cache memory controller21. In case of a write operation, write data are given from the internal memory controller14or the secondary cache memory controller21to the memory20through the bus26. A write instruction given from the secondary cache memory controller21to the memory20through the bus26is given in a cache fill operation caused by a read error or a cache fill operation caused by a write error in the secondary cache memory.

The selection of the selector19is determined in accordance with the set value of a mode control register22. Moreover, the ON/OFF operations of the internal memory controller14and the secondary cache memory controller21are also determined in accordance with the set value of the register22. In the case in which the operation of the internal memory controller14is selected (valid), the secondary cache memory controller21is not operated but the output of the internal memory controller14is selected by the selector19. To the contrary, if the secondary cache memory controller21is valid, the internal memory controller14is not operated but the output of the secondary cache memory controller21is selected by the selector19.

The internal memory controller14outputs, to the interface bus13or16, a result of a response to the access request. Moreover, the secondary cache memory controller21outputs, to the interface bus16, a result of a response to the access request.

When a flush for the primary cache memory6is carried out, the primary cache memory controller5outputs a cache flush request signal30to the secondary cache memory controller21. The signal30is generated by the indication of a program during the execution of a flush manipulation instruction for the primary cache memory6by CPU3. The flush request signal30is supplied as a flush request signal31to the secondary cache memory controller21through the peripheral bus interface controller15. The secondary cache memory controller21invalidates the valid bits of all cache entries of a cache tag retained in the secondary cache memory controller21and clears a cache entry in the internal memory20in response to the signal31.

FIG. 2illustrates the details of the read buffer12.41to45denote portions obtained by dividing the interface bus11.41denotes a type of an access request which indicates a read request, a write request or no access request (NOP).42denotes a data width of the access request which has 1 byte, 2 bytes, 4 bytes, 8 bytes and 32 bytes.43denotes an address of the access request which has a 22-bit width.44denotes a signal which serves to return read data when the access request is the read request and has a 64-bit width (corresponding to 8 bytes).45denotes a signal for transferring write data when the access request is the write.46and47denote an address signal corresponding to higher 17 bits of the address43.

51denotes a data register having a 256-bit width which holds last access data.52denotes an address register having a 17-bit width which holds higher 17 bits of a last access address.53denotes a 1-bit register which holds “1” when contents held in the register51and the register52are valid and holds “0” when they are invalid.

54denotes a comparator which outputs “1” when the signal41is the read request.55denotes a comparator which outputs “1” when the contents held in the signal47and the address register52are coincident with each other.56denotes a NAND gate. The output of the NAND gate56is “0” when “the signal41is the read request, the contents held in the signal47and the register52are coincident with each other, and the register53is “1” indicative of validation”. More specifically, when the output of the NAND gate56is “0”, the hit of the read buffer12is indicated.57denotes a comparator which outputs “1” when the signal41is the write request.

When the output of the comparator54is “1”, that is, the signal41is the read request, the output of the signal49is replaced with a 32-byte access request by a selector60. When the output of the comparator54is “0”, that is, the signal41is not the read request, the input of the signal42is exactly output to the signal49.

When the output of the NAND gate56is “0”, that is, the read buffer12is hit, the output of the signal48is replaced with NOP by a selector61. When the output of the NAND gate56is “1”, the output of the signal41is exactly sent to the signal48.

When the output of the NAND gate56is “0”, moreover, the output of the register51is input to an aligner (ALGN)63by a selector62. When the output of the NAND gate56is “1”, the input of the signal50is sent to the aligner63. The aligner63rearranges the bit positions of input data and outputs them to the signal44in accordance with the contents of the signals42and43.

When the output of the NAND gate56is “1”, the registers51and52fetch the contents of the signals50and46respectively. The contents held in53are changed to “0” when the output of the comparator57is “1”. The reason is that data and an address are input to the registers51and52in a write in the same manner as the case of a read buffer error. When the output of the comparator54is “1” and the output of the NAND gate56is “1”, a change to “1” is carried out. The reason is that the data of the register51are to be available in accordance with the result of the address comparison of the register52in a next read operation.

FIG. 3is a timing chart according to a comparative example, in which data are read from the interface bus11for a sequential access when the read buffer12is not utilized or the read buffer12is not provided.FIG. 4is a timing chart showing the case in which the read buffer12is utilized to read the data from the interface bus11for a sequential access.

Herein, the read buffer12and the processor core2are operated at the same frequency, the ratio of the operating frequency of the read buffer12to the operating frequency of the internal memory20is assumed to be 2:1, and there is continuously carried out a read in which the sequential access from the processor core2is performed every 8 bytes (64 bits).

InFIG. 3,301denotes a clock signal of the processor core2,302denotes a clock signal of the internal memory20,303denotes an access request based on the signals41and42sent from the processor core2,304denotes a data output to be sent from the internal memory20to the bus44, and305denotes the operations of the internal memory20and the internal memory controller14. Moreover,311to320denote a clock cycle of the processor core2.

321denotes an 8-byte read request given from the processor core2, and the internal memory controller14carries out a read operation over the request as shown in322for a period of312to313, and outputs read data323for a period of314.331to333,341to343, and351to353also carry out the same operations as321to323, and the 8-byte read requests of321,331,341and351have continuous addresses. In this case, an operating period of 10 cycles is required at the clock of the processor core2from the first read request321to the final data output353.

In the timing chart ofFIG. 4showing the case in which the read buffer12is provided,401,402and403are the same as301,302and303.404denotes a hit signal of the read buffer which corresponds to the output of the NAND gate56inFIG. 2. 405denotes a data output from the read buffer12to the bus44, and406denotes the operations of the internal memory20and the internal memory controller14. Moreover,411to417denote a clock cycle of the processor core2.

421denotes an 8-byte read request given from the processor core2.422denotes the operation of an internal memory corresponding thereto. This operation carries out the replacement of a request in the read buffer12and is not the 8-byte read but a 32-byte read.423denotes a data output to be sent to the processor core2which is carried out for a period of414after the end of the operation of422. While a second 8-byte read request431is issued from the processor core2for the period of414, moreover, the 32-byte read is carried out in the first read request421. Therefore, the read buffer12is hit so that the signal of404(the output signal of the NAND gate56) is changed from “1” to “0”. A data output433for431is carried out for a period of415. The read buffer12is also hit for third and fourth 8-byte read requests441and451. Consequently, data outputs443and453are carried out for periods416and417, respectively.

FIG. 5shows another example of the microcomputer. In a microcomputer shown inFIG. 5, the peripheral bus interface controller15shown inFIG. 1is omitted, and the processor core2is directly connected to the internal memory controller14and the secondary cache memory controller21through an interface bus34to be a third bus. Moreover, the signal30indicative of a flush request output from the primary cache memory controller5to the secondary cache memory controller21is exactly supplied to the secondary cache memory controller21. The same structures as those inFIG. 1have the same reference numerals and detailed description thereof will be omitted.

The structures ofFIGS. 1 and 5are compared with each other. In the example shown inFIG. 1, the peripheral bus interface controller15decides an access request destination from an address for an access request given from the primary cache memory controller5and outputs an access control signal required for the access request destination thus decided. Alternatively, a data transfer request destination is decided from an address in the same manner for a data transfer request given from the peripheral circuit24constituting the bus master module such as a DMAC, and an access control signal required for the access request destination thus decided is output. Accordingly, the interface buses10and16are not dedicated buses for a specific memory and a peripheral circuit. On the other hand, the interface buses11and13are dedicated sequential access buses. By employing a structure in which an access path for accessing the same internal memory20via the memory controller14is divided through a sequential access and a random access, accordingly, it is possible to dedicate a path for a sequential access. Consequently, it is preferable that a specific interface protocol should be implemented, and a general purpose utilization with other memories or peripheral circuits does not need to be considered. Correspondingly, it is advantageous to an increase in the speed of an interface operation for the sequential access. In the structure shown inFIG. 5, the peripheral bus interface controller15is not provided on the interface bus34but a connection to both the memory controller14and the secondary cache memory controller21is carried out. In this sense, the driving load of the bus34is comparatively increased in respect of the input capacities of both of the circuits. Also in the case in which the peripheral bus interface controller15is not provided, it is advantageous that the bus for the sequential access is dedicated by the buses11and13in order to increase the speed of the sequential access operation in that respect.

In the structure shown inFIG. 1, moreover, in the case in which the internal memory20is caused to be valid by setting the register22, a program which is being executed in the processor core2can also accept an internal memory access request from the peripheral bus (processor bus)23side through the interface bus16for a random access while accessing the internal memory20through the interface buses11and13for a sequential access.

According to the microcomputer described above, a normal memory mode (an operation mode for causing the internal memory controller14to be valid) is used in a program in which the sequential access to the internal memory20is present, for example, image data or music data. In particular, it is possible to expect an enhancement in the performance of the read buffer12for a sequential access. Moreover, the read buffer12has a small amount of circuits and an operation can be expected at a higher frequency than that in the internal memory20. As described based onFIG. 1, in the case in which the read buffer12and the processor core2are operated at the same frequency and the ratio of the operating frequency of the read buffer12to the operating frequency of the internal memory20is 2:1, 10 cycles are required at the clock of the processor core2from a first read request to a final data output if the read buffer12is not provided, while a reduction to 7 cycles is carried out so that a performance can be enhanced if the read buffer12is provided. Moreover, the number of accesses of the internal memory20is also decreased from four to one.

In the sequential access, the cache operation of the primary cache memory6is not carried out and cache entry data retained in the primary cache memory6can be prevented from being undesirably rewritten by sequential access data such as image data having a low possibility of a re-access.

Moreover, it is possible to switch the control of the internal memory to a normal memory mode and a secondary cache mode (an operation mode for causing the secondary cache memory controller21to be valid). Consequently, it is possible to practically use the internal memory20in an optimum configuration corresponding to the contents of the processing of a program, thereby contributing to an enhancement in a data processing performance. In a program having a large number of random accesses to the memory20, it is possible to decrease the penalty of a primary cache error by practically using the secondary cache mode, resulting in a contribution to the enhancement in the data processing performance.

While the invention has specifically been described above, the invention is not restricted thereto but various changes can be made without departing from a scope thereof. For example, the processor core may be provided with a memory management unit for converting a logical address to a physical address. The primary cache memory may be provided separately for data and an instruction, respectively. In that case, a data cache memory may be mainly connected to the read buffer restrictively. Moreover, a flush request output from the primary cache memory controller5to the secondary cache memory controller21is not restricted to an indication by an individual signal but an indication may be given in a command through the interface bus. While an external input/output circuit to be interfaced with the outside of the microcomputer is not shown in the examples ofFIGS. 1 and 5, it is apparent that the external input/output circuit is actually provided. The invention can be widely applied to a microcomputer, a microprocessor, and furthermore, an electronic circuit utilizing them.