PLASMA UNIFORMITY CONTROL USING A STATIC MAGNETIC FIELD

A system for performing a plasma process on a wafer is provided, including: a chamber configured to receive a wafer for plasma processing and having an interior defining a plasma processing region in which a plasma is provided for the plasma processing of the wafer; a first magnetic coil disposed above the chamber and centered about an axis perpendicular to a surface plane of the wafer and through an approximate center of the wafer; a first DC power supply configured to apply a first DC current to the first magnetic coil during the plasma processing, the applied first DC current producing a magnetic field in the plasma processing region that reduces non-uniformity of the plasma.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to semiconductor device fabrication.

2. Description of the Related Art

Plasma etching processes are often used in the manufacture of semiconductor devices on semiconductor wafers. In the plasma etching process, a semiconductor wafer that includes semiconductor devices under manufacture is exposed to a plasma generated within a plasma processing volume. The plasma interacts with material(s) on the semiconductor wafer so as to remove material(s) from the semiconductor wafer and/or modify material(s) to enable their subsequent removal from the semiconductor wafer. The plasma can be generated using specific reactant gases that will cause constituents of the plasma to interact with the material(s) to be removed/modified from the semiconductor wafer, without significantly interacting with other materials on the wafer that are not to be removed/modified. The plasma is generated by using radiofrequency signals to energize the specific reactant gases. These radiofrequency signals are transmitted through the plasma processing volume that contains the reactant gases, with the semiconductor wafer held in exposure to the plasma processing volume. The transmission paths of the radiofrequency signals through the plasma processing volume can affect how the plasma is generated within the plasma processing volume. For example, the reactant gases may be energized to a greater extent in regions of the plasma processing volume where larger amounts of radiofrequency signal power is transmitted, thereby causing spatial non-uniformities in the plasma characteristics throughout the plasma processing volume. The spatial non-uniformities in plasma characteristics can manifest as spatial non-uniformity in ion density, ion energy, and/or reactive constituent density, among other plasma characteristics. The spatial non-uniformities in plasma characteristics can correspondingly cause spatial non-uniformities in plasma processing results on the semiconductor wafer. Therefore, the manner in which radiofrequency signals are transmitted through the plasma processing volume can have an effect on the uniformity of plasma processing results on the semiconductor wafer. It is within this context that the present disclosure arises.

SUMMARY

Broadly speaking, embodiments of the present disclosure provide methods and systems for plasma uniformity control using a static magnetic field.

In some implementations, a system for performing a plasma process on a wafer is provided, including: a chamber configured to receive a wafer for plasma processing and having an interior defining a plasma processing region in which a plasma is provided for the plasma processing of the wafer; a first magnetic coil disposed above the chamber and centered about an axis perpendicular to a surface plane of the wafer and through an approximate center of the wafer; a first DC power supply configured to apply a first DC current to the first magnetic coil during the plasma processing, the applied first DC current producing a magnetic field in the plasma processing region that reduces non-uniformity of the plasma.

In some implementations, the magnetic field is configured to be substantially vertical through a central region of the plasma processing region.

In some implementations, the magnetic field through the central region of the plasma processing region has a strength that is less than approximately 10 Gauss.

In some implementations, the magnetic field is configured to reduce a radial non-uniformity of etching that is performed by the plasma processing.

In some implementations, the first magnetic coil is substantially annular in shape.

In some implementations, the first magnetic coil is oriented along a horizontal plane parallel to the surface plane of the wafer.

In some implementations, an inner diameter of the first magnetic coil is in the range of approximately 15 to 20 inches.

In some implementations, the first magnetic coil includes a plurality of turns of magnet wire.

In some implementations, the system further includes: a second magnetic coil disposed above the chamber, the second magnetic coil being concentric with the first magnetic coil; a second DC power supply configured to apply a second DC current to the second magnetic coil during the plasma processing, the applied second DC current contributing to producing the magnetic field in the plasma processing region that reduces non-uniformity of the plasma.

In some implementations, the second magnetic coil is substantially oriented along a same horizontal plane as the first magnetic coil.

In some implementations, the first DC current and the second DC current are configured to have a same magnitude or a different magnitude.

In some implementations, the first DC current and the second DC current are configured to be applied in a same direction or in opposite directions.

In some implementations, an inner diameter of the first magnetic coil is in the range of approximately 10 to 15 inches; and, an inner diameter of the second magnetic coil is in the range of approximately 15 to 25 inches.

In some implementations, the system further includes: a second magnetic coil configured to laterally surround the plasma processing region; a second DC power supply configured to apply a second DC current to the second magnetic coil during the plasma processing, the applied second DC current contributing to producing the magnetic field in the plasma processing region that reduces non-uniformity of the plasma.

In some implementations, the system further includes: a second magnetic coil disposed below the plasma processing region; a second DC power supply configured to apply a second DC current to the second magnetic coil during the plasma processing, the applied second DC current contributing to producing the magnetic field in the plasma processing region that reduces non-uniformity of the plasma.

In some implementations, a method for performing a plasma process on a wafer is provided, including: moving a wafer into a chamber configured for plasma processing, an interior of the chamber defining a plasma processing region; providing a plasma in the plasma processing region for the plasma processing of the wafer; and applying a DC current to a magnetic coil during the plasma processing, the applied DC current producing a magnetic field in the plasma processing region that reduces non-uniformity of the plasma;

wherein the magnetic coil is disposed above the chamber and centered about an axis perpendicular to a surface plane of the wafer and through an approximate center of the wafer.

In some implementations, the magnetic field is configured to be substantially vertical through a central region of the plasma processing region.

In some implementations, the magnetic field through the central region of the plasma processing region has a strength that is less than approximately 10 Gauss.

In some implementations, the magnetic field is configured to reduce a radial non-uniformity of etching that is performed by the plasma processing.

In some implementations, the magnetic coil is substantially annular in shape.

In some implementations, the magnetic coil is oriented along a horizontal plane parallel to the surface plane of the wafer.

In some implementations, an inner diameter of the first magnetic coil is in the range of approximately 15 to 20 inches.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide an understanding of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present disclosure.

In plasma etching systems for semiconductor wafer fabrication, spatial variation of etching results across the semiconductor wafer can be characterized by radial etch uniformity and azimuthal etch uniformity. Radial etch uniformity can be characterized by the variation in etch rate as a function of radial position on the semiconductor wafer, extending outward from the center of the semiconductor wafer to the edge of the semiconductor wafer at a given azimuthal position on the semiconductor wafer. And, azimuthal etch uniformity can be characterized by the variation in etch rate as a function of azimuthal position on the semiconductor wafer, about the center of the semiconductor wafer, at a given radial position on the semiconductor wafer. In some plasma processing systems, such as in the system described herein, the semiconductor wafer is positioned on an electrode from which radiofrequency signals emanate to generate a plasma within a plasma generation region overlying the semiconductor wafer, with the plasma having characteristics controlled to cause a prescribed etching process to occur on the semiconductor wafer.

In capacitive coupled plasma (CCP) systems, there is a tendency to exhibit center plasma non-uniformity due to standing waves and localized accumulation of positive and negative ions. This results in radial non-uniformity of etch rate. For example, many CCP tools may exhibit dramatic increases in etch rate towards the center of the wafer.

Furthermore, there is tool-to-tool variation with respect to radial non-uniformity. Some tools may exhibit significant spikes in etch rate at the center, whereas other tools may not. Often this is correlated to the presence or absence of magnetic fields, as the flux from chamber parts, which may vary in configuration from tool to tool, differs. Further, the local environment or specific location of a given tool, and surrounding hardware, may affect the local magnetic fields which are present, and which in turn affect etch radial non-uniformity.

In view of the foregoing problems in existing CCP systems, some implementations of the disclosure provide for the application of a static B-field to the plasma to minimize localized charged species accumulation and improve plasma/etch uniformity across the wafer.

In some implementations, a pulsed magnetic field is applied to create a time-varying radial gradient of B-field to control radial electron diffusion, and, therefore, radial negative and positive ion acoustic waves.

FIG.1shows a vertical cross-section view through a plasma processing system100for use in semiconductor chip manufacturing, in accordance with some embodiments. The system100includes a chamber101formed by walls101A, a top member101B, and a bottom member101C. The walls101A, top member101B, and bottom member101C collectively form an interior region103within the chamber101. The bottom member101C includes an exhaust port105through which exhaust gases from plasma processing operations are directed. In some embodiments, during operation, a suction force is applied at the exhaust port105, such as by a turbo pump or other vacuum device, to draw process exhaust gases out of the interior region103of the chamber101. In some embodiments, the chamber101is formed of aluminum. However, in various embodiments, the chamber101can be formed of essentially any material that provides sufficient mechanical strength, acceptable thermal performance, and is chemically compatible with the other materials to which it interfaces and to which it is exposed during plasma processing operations within the chamber101, such as stainless steel, among others. At least one wall101A of the chamber101includes a door107through which a semiconductor wafer W is transferred into and out of the chamber101. In some embodiments, the door107is configured as a slit-valve door.

In some embodiments, the semiconductor wafer W is a semiconductor wafer undergoing a fabrication procedure. For ease of discussion, the semiconductor wafer W is referred to as wafer W hereafter. However, it should be understood that in various embodiments, the wafer W can be essentially any type of substrate that is subjected to a plasma-based fabrication process. For example, in some embodiments, the wafer W as referred to herein can be a substrate formed of silicon, sapphire, GaN, GaAs or SiC, or other substrate materials, and can include glass panels/substrates, metal foils, metal sheets, polymer materials, or the like. Also, in various embodiments, the wafer W as referred to herein may vary in form, shape, and/or size. For example, in some embodiments, the wafer W referred to herein may correspond to a circular-shaped semiconductor wafer on which integrated circuit devices are manufactured. In various embodiments, the circular-shaped wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or of another size. Also, in some embodiments, the wafer W referred to herein may correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, or the like, among other shapes.

The plasma processing system100includes an electrode109positioned on a facilities plate111. In some embodiments, the electrode109and the facilities plate111are formed of aluminum. However, in other embodiments, the electrode109and the facilities plate111can be formed of another electrically conductive material that has sufficient mechanical strength and that has compatible thermal and chemical performance characteristics. A ceramic layer110is formed on a top surface of the electrode109. The ceramic layer110is configured to receive and support the wafer W during performance of plasma processing operations on the wafer W. In some embodiments, the top surface of the electrode190that is located radially outside of the ceramic layer110and the peripheral side surfaces of the electrode109are covered with a spray coat of ceramic.

The ceramic layer110includes an arrangement of one or more clamp electrodes112for generating an electrostatic force to hold the wafer W to the top surface of the ceramic layer110. In some embodiments, the ceramic layer110includes an arrangement of two clamp electrodes112that operate in a bipolar manner to provide a clamping force to the wafer W. The clamp electrodes112are connected to a direct current (DC) supply117that generates a controlled clamping voltage to hold the wafer W against the top surface of the ceramic layer110. Electrical wires119A,119B are connected between the DC supply117and the facilities plate111. Electrical wires/conductors are routed through the facilities plate111and the electrode109to electrically connect the wires119A,119B to the clamp electrodes112. The DC supply117is connected to a control system120through one or more signal conductors121.

The electrode109also includes an arrangement of temperature control fluid channels123through which a temperature control fluid is flowed to control a temperature of the electrode109and in turn control a temperature of the wafer W. The temperature control fluid channels123are plumbed (fluidly connected) to ports on the facilities plate111. Temperature control fluid supply and return lines are connected to these ports on the facilities plate111and to a temperature control fluid circulation system125, as indicated by arrow126. The temperature control fluid circulation system125includes a temperature control fluid supply, a temperature control fluid pump, and a heat exchanger, among other devices, to provide a controlled flow of temperature control fluid through the electrode109in order to obtain and maintain a prescribed wafer W temperature. The temperature control fluid circulation system125is connected to the control system120through one or more signal conductors127. In various embodiments, various types of temperature control fluid can be used, such as water or a refrigerant liquid/gas. Also, in some embodiments, the temperature control fluid channels123are configured to enable spatially varying control of the temperature of the wafer W, such as in two dimensions (x and y) across the wafer W.

The ceramic layer110also includes an arrangement of backside gas supply ports (not shown) that are fluidly connected to corresponding backside gas supply channels within the electrode109. The backside gas supply channels within the electrode109are routed through the electrode109to the interface between the electrode109and the facilities plate111. One or more backside gas supply line(s) are connected to ports on the facilities plate111and to a backside gas supply system129, as indicated by arrow130. The facilities plate111is configured to supply the backside gas(es) from the one or more backside gas supply line(s) to the backside gas supply channels within the electrode109. The backside gas supply system129includes a backside gas supply, a mass flow controller, and a flow control valve, among other devices, to provide a controlled flow of backside gas through the arrangement of backside gas supply ports in the ceramic layer110. In some embodiments, the backside gas supply system129also includes one or more components for controlling a temperature of the backside gas. In some embodiments, the backside gas is helium. Also, in some embodiments, the backside gas supply system129can be used to supply clean dry air (CDA) to the arrangement of backside gas supply ports in the ceramic layer110. The backside gas supply system129is connected to the control system120through one or more signal conductors131.

Three lift pins132extend through the facilities plate111, the electrode109, and the ceramic layer110to provide for vertical movement of the wafer W relative to the top surface of the ceramic layer110. In some embodiments, vertical movement of the lift pins132is controlled by a respective electromechanical and/or pneumatic lifting device133connected to the facilities plate111. The three lifting devices133are connected to the control system120through one or more signal conductors134. In some embodiments, the three lift pins132are positioned to have a substantially equal azimuthal spacing about a vertical centerline of the electrode109/ceramic layer110that extends perpendicular to the top surface of the ceramic layer110. It should be understood that the lift pins132are raised to receive the wafer W into the chamber101and to remove the wafer W from the chamber101. Also, the lift pins132are lowered to allow the wafer W to rest on the top surface of the ceramic layer110during processing of the wafer W.

Also, in various embodiments, one or more of the electrode109, the facilities plate111, the ceramic layer110, the clamp electrodes112, the lift pins132, or essentially any other component associated therewith can be equipped to include one or more sensors, such as sensors for temperature measurement, electrical voltage measurement, and electrical current measurement, among others. Any sensor disposed within the electrode109, the facilities plate111, the ceramic layer110, the clamp electrodes112, the lift pins132, or essentially any other component associated therewith is connected to the control system120by way of electrical wire, optical fiber, or through a wireless connection.

The facilities plate111is set within an opening of a ceramic support113, and is supported by the ceramic support113. The ceramic support113is positioned on a supporting surface114of a cantilever arm assembly115. In some embodiments, the ceramic support113has a substantially annular shape, such that the ceramic support113substantially circumscribes the outer radial perimeter of the facilities plate111, while also providing a supporting surface116upon which a bottom outer peripheral surface of the facilities plate111rests. The cantilever arm assembly115extends through the wall101A of the chamber101. In some embodiments, a sealing mechanism135is provided within the wall101A of the chamber101where the cantilever arm assembly115is located to provide for sealing of the interior region103of the chamber101, while also enabling the cantilever arm assembly115to move upward and downward in the z-direction in a controlled manner.

The cantilever arm assembly115has an open region118through which various devices, wires, cables, and tubing is routed to support operations of the system100. The open region118within the cantilever arm assembly is exposed to ambient atmospheric conditions outside of the chamber101, e.g. air composition, temperature, pressure, and relative humidity. Also, a radiofrequency signal supply rod137is positioned inside of the cantilever arm assembly115. More specifically, the radiofrequency signal supply rod137is positioned inside of an electrically conductive tube139, such that the radiofrequency signal supply rod137is spaced apart from the inner wall of the tube139. The sizes of the radiofrequency signal supply rod137and the tube139may vary. The region inside of the tube139between the inner wall of the tube139and the radiofrequency signal supply rod137is occupied by air along the full length of the tube139.

In some embodiments, the radiofrequency signal supply rod137is substantially centered within the tube139, such that a substantially uniform radial thickness of air exists between the radiofrequency signal supply rod137and the inner wall of the tube139, along the length of tube139. However, in some embodiments, the radiofrequency signal supply rod137is not centered within the tube139, but the air gap within the tube139exists at all locations between the radiofrequency signal supply rod137and the inner wall of the tube139, along the length of the tube139. A delivery end of the radiofrequency signal supply rod137is electrically and physically connected to a lower end of a radiofrequency signal supply shaft141. In some embodiments, the delivery end of the radiofrequency signal supply rod137is bolted to a lower end of a radiofrequency signal supply shaft141. An upper end of the radiofrequency signal supply shaft141is electrically and physically connected to the bottom of the facilities plate111. In some embodiments, the upper end of the radiofrequency signal supply shaft141is bolted to the bottom of the facilities plate111. In some embodiments, both the radiofrequency signal supply rod137and the radiofrequency signal supply shaft141are formed of copper. In some embodiments, the radiofrequency signal supply rod137is formed of copper, or aluminum, or anodized aluminum. In some embodiments, the radiofrequency signal supply shaft141is formed of copper, or aluminum, or anodized aluminum. In other embodiments, the radiofrequency signal supply rod137and/or the radiofrequency signal supply shaft141is formed of another electrically conductive material that provides for transmission of radiofrequency electrical signals. In some embodiments, the radiofrequency signal supply rod137and/or the radiofrequency signal supply shaft141is coated with an electrically conductive material (such as silver or another electrically conductive material) that provides for transmission of radiofrequency electrical signals. Also, in some embodiments, the radiofrequency signal supply rod137is a solid rod. However, in other embodiments, the radiofrequency signal supply rod137is a tube. Also, it should be understood that a region140surrounding the connection between the radiofrequency signal supply rod137and the radiofrequency signal supply shaft141is occupied by air.

A supply end of the radiofrequency signal supply rod137is connected electrically and physically to an impedance matching system143. The impedance matching system143is connected to a first radiofrequency signal generator147and a second radiofrequency signal generator149. The impedance matching system143is also connected to the control system120through one or more signal conductors144. The first radiofrequency signal generator147is also connected to the control system120through one or more signal conductors148. The second radiofrequency signal generator149is also connected to the control system120through one or more signal conductors150. The impedance matching system143includes an arrangement of inductors and capacitors sized and connected to provide for impedance matching so that radiofrequency power can be transmitted along the radiofrequency signal supply rod137, along the radiofrequency signal supply shaft141, through the facilities plate111, through the electrode109, and into a plasma processing region182above the ceramic layer110. In some embodiments, the first radiofrequency signal generator147is a high frequency radiofrequency signal generator, and the second radiofrequency signal generator149is a low frequency radiofrequency signal generator. In some embodiments, the first radiofrequency signal generator147generates radiofrequency signals within a range extending from about 50 MegaHertz (MHz) to about 70 MHz, or within a range extending from about 54 MHz to about 63 MHz, or at about 60 MHz. In some embodiments, the first radiofrequency signal generator147supplies radiofrequency power within a range extending from about 5 kiloWatts (kW) to about 25 kW, or within a range extending from about 10 kW to about 20 kW, or within a range extending from about 15 kW to about 20 kW, or of about 10 kW, or of about 16 kW. In some embodiments, the second radiofrequency signal generator149generates radiofrequency signals within a range extending from about 50 kiloHertz (kHz) to about 500 kHz, or within a range extending from about 330 kHz to about 440 kHz, or at about 400 kHz. In some embodiments, the second radiofrequency signal generator149supplies radiofrequency power within a range extending from about 15 kW to about 100 kW, or within a range extending from about 30 kW to about 50 kW, or of about 34 kW, or of about 50 kW. In an example embodiment, the first radiofrequency signal generator147is set to generate radiofrequency signals having a frequency of about 60 MHz, and the second radiofrequency signal generator149is set to generate radiofrequency signals having a frequency of about 400 kHz.

A coupling ring161is configured and positioned to extend around the outer radial perimeter of the electrode109. In some embodiments, the coupling ring161is formed of a ceramic material. A quartz ring163is configured and positioned to extend around the outer radial perimeters of both the coupling ring161and the ceramic support113. In some embodiments, the coupling ring161and the quartz ring163are configured to have substantially aligned top surfaces when the quartz ring163is positioned around both the coupling ring161and the ceramic support113. Also, in some embodiments, the substantially aligned top surfaces of the coupling ring161and the quartz ring163are substantially aligned with a top surface of the electrode109, said top surface being present outside of the radial perimeter of the ceramic layer110. Also, in some embodiments, a cover ring165is configured and positioned to extend around the outer radial perimeter of the top surface of the quartz ring163. In some embodiments, the cover ring165is formed of quartz. In some embodiments, the cover ring165is configured to extend vertically above the top surface of the quartz ring163. In this manner, the cover ring165provides a peripheral boundary within which an edge ring167is positioned.

The edge ring167is configured to facilitate extension of the plasma sheath radially outward beyond the peripheral edge of the wafer W to provide improvement in process results near the periphery of the wafer W. In various embodiments, the edge ring167is formed of a conductive material, such as crystalline silicon, polycrystalline silicon (polysilicon), boron doped single crystalline silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide, or a silicon carbide layer on top of an aluminum oxide layer, or an alloy of silicon, or a combination thereof, among other materials. It should be understood that the edge ring167is formed as an annular-shaped structure, e.g. as a ring-shaped structure. The edge ring167can perform many functions, including shielding components underlying the edge ring167from being damaged by ions of a plasma180formed within a plasma processing region182. Also, the edge ring167improves uniformity of the plasma180at and along the outer peripheral region of the wafer W.

A fixed outer support flange169is attached to the cantilever arm assembly115. The fixed outer support flange169is configured to extend around an outer vertical side surface of the ceramic support113, and around an outer vertical side surface of the quartz ring163, and around a lower outer vertical side surface of the cover ring165. The fixed outer support flange169has an annular shape that circumscribes the assembly of the ceramic support113, the quartz ring163, and the cover ring165. The fixed outer support flange169has an L-shaped vertical cross-section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the fixed outer support flange169has an inner vertical surface that is positioned against the outer vertical side surface of the ceramic support113, and against the outer vertical side surface of the quartz ring163, and against the lower outer vertical side surface of the cover ring165. In some embodiments, the vertical portion of the L-shaped cross-section of the fixed outer support flange169extends over an entirety of the outer vertical side surface of the ceramic support113, and over an entirety of the outer vertical side surface of the quartz ring163, and over the lower outer vertical side surface of the cover ring165. In some embodiments, the cover ring165extends radially outward above a top surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange169. And, in some embodiments, an upper outer vertical side surface of the cover ring165(located above the top surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange169) is substantially vertically aligned with an outer vertical surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange169. The horizontal portion of the L-shaped cross-section of the fixed outer support flange169is positioned on and fastened to the supporting surface114of a cantilever arm assembly115. The fixed outer support flange169is formed of an electrically conductive material. In some embodiments, the fixed outer support flange169is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange169can be formed of another electrically conductive material, such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross-section of the fixed outer support flange169is bolted to the supporting surface114of a cantilever arm assembly115.

An articulating outer support flange171is configured and positioned to extend around the outer vertical surface169D of the vertical portion of the L-shaped cross-section of the fixed outer support flange169, and to extend around the upper outer vertical side surface of the cover ring165. The articulating outer support flange171has an annular shape that circumscribes both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange169and the upper outer vertical side surface of the cover ring165. The articulating outer support flange171has an L-shaped vertical cross-section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the articulating outer support flange171has an inner vertical surface that is positioned proximate to and spaced apart from both the outer vertical side surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange169and the upper outer vertical side surface of the cover ring165. In this manner, the articulating outer support flange171is moveable in the vertical direction (z-direction) along both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange169and the upper outer vertical side surface of the cover ring165. The articulating outer support flange171is formed of an electrically conductive material. In some embodiments, the articulating outer support flange171is formed of aluminum or anodized aluminum. However, in other embodiments, the articulating outer support flange171can be formed of another electrically conductive material, such as copper or stainless steel.

A number of electrically conductive straps173are connected between the articulating outer support flange171and the fixed outer support flange169, around the outer radial perimeters of both the articulating outer support flange171and the fixed outer support flange169. In the example embodiment, the electrically conductive straps173are shown to have an “outward” configuration, in that the electrically conductive straps173bend outward away from the fixed outer support flange169. In some embodiments, the electrically conductive straps173are formed of stainless steel. However, in other embodiments, the electrically conductive straps173can be formed of another electrically conductive material, such as aluminum or copper, among others.

In some embodiments, forty-eight (48) electrically conductive straps173are distributed in a substantially equally spaced manner around the outer radial perimeters of the articulating outer support flange171and the fixed outer support flange169. It should be understood, however, that the number of electrically conductive straps173can vary in different embodiments. In some embodiments, the number of electrically conductive straps173is within a range extending from about 24 to about 80, or within a range extending from about 36 to about 60, or within a range extending from about 40 to about 56. In some embodiments, the number of electrically conductive straps173is less than 24. In some embodiments, the number of electrically conductive straps173is greater than 80. Because the number of electrically conductive straps173has an effect on the ground return paths for the radiofrequency signals around the perimeter of the plasma processing region182, the number of electrically conductive straps173can have an effect on the uniformity of process results across the wafer W. Also, the size of the electrically conductive straps173can vary in different embodiments.

In some embodiments, the electrically conductive straps173are connected to the fixed outer support flange169by a clamping force applied by securing a clamp ring175to a top surface of the horizontal portion of the L-shaped cross-section of the fixed outer support flange169. In some embodiments, the clamp ring175is bolted to the fixed outer support flange169. In some embodiments, the bolts that secure the clamp ring175to the fixed outer support flange169are positioned at locations between the electrically conductive straps173. However, in some embodiments, one or more bolts that secure the clamp ring175to the fixed outer support flange169can be positioned to extend through electrically conductive straps173. In some embodiments, the clamp ring175is formed of a same material as the fixed outer support flange169. However, in other embodiments, the clamp ring175and the fixed outer support flange169can be formed of different materials.

In some embodiments, the electrically conductive straps173are connected to the articulating outer support flange171by a clamping force applied by securing a clamp ring177to a bottom surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange171. Alternatively, in some embodiments, the first end portion of each of the plurality of electrically conductive straps173is connected to the upper surface of the horizontal portion of the articulating outer support flange171by the clamp ring177. In some embodiments, the clamp ring177is bolted to the articulating outer support flange171. In some embodiments, the bolts that secure the clamp ring177to the articulating outer support flange171are positioned at locations between the electrically conductive straps173. However, in some embodiments, one or more bolts that secure the clamp ring177to the articulating outer support flange171can be positioned to extend through electrically conductive straps173. In some embodiments, the clamp ring177is formed of a same material as the articulating outer support flange171. However, in other embodiments, the clamp ring177and the articulating outer support flange171can be formed of different materials.

A set of support rods201are positioned around the cantilever arm assembly115to extend vertically through the horizontal portion169B of the L-shaped cross-section of the fixed outer support flange169. The upper end of the support rods201are configured to engage with the bottom surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange171. In some embodiments, a lower end of each of the support rods201is engaged with a resistance mechanism203. The resistance mechanism203is configured to provide an upward force to the corresponding support rod201that will resist downward movement of the support rod201, while allowing some downward movement of the support rod201. In some embodiments, the resistance mechanism203includes a spring to provide the upward force to the corresponding support rod201. In some embodiments, the resistance mechanism203includes a material, e.g. spring and/or rubber, that has a sufficient spring constant to provide the upward force to the corresponding support rod201. It should be understood that as the articulating outer support flange171moves downward to engage the set of support rods201, the set of support rods201and corresponding resistance mechanisms203provide an upward force to the articulating outer support flange171. In some embodiments, the set of support rods201includes three support rods201and corresponding resistance mechanisms203. In some embodiments, the support rods201are positioned to have a substantially equal azimuthal spacing relative to a vertical centerline of the electrode109. However, in other embodiments, the support rods201are positioned to have a non-equal azimuthal spacing relative to a vertical centerline of the electrode109. Also, in some embodiments, more than three support rods201and corresponding resistance mechanisms203are provided to support the articulating outer support flange171.

With continued reference backFIG.1, the plasma processing system100further includes a C-shroud member185positioned above the electrode109. The C-shroud member185is configured to interface with the articulating outer support flange171. Specifically, a seal179is disposed on the top surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange171, such that the seal179is engaged by the C-shroud member185when the articulating outer support flange171is moved upward toward the C-shroud member185. In some embodiments, the seal179is electrically conductive to assist with establishing electrical conduction between the C-shroud member185and the articulating outer support flange171. In some embodiments, the C-shroud member185is formed of polysilicon. However, in other embodiments, the C-shroud member185is formed of another type of electrically conductive material that is chemically compatible with the processes to be formed in the plasma processing region182, and that has sufficient mechanical strength.

The C-shroud is configured to extend around the plasma processing region182and provide a radial extension of the plasma processing region182volume into the region defined within the C-shroud member185. The C-shroud member185includes a lower wall185A, an outer vertical wall185B, and an upper wall185C. In some embodiments, the outer vertical wall185B and the upper wall185C of the C-shroud member185are solid, non-perforated members, and the lower wall185A of the C-shroud member185includes a number of vents186through which process gases flow from within the plasma processing region182. In some embodiments, a throttle member196is disposed below the vents186of the C-shroud member185to control a flow of process gas through the vents186. More specifically, in some embodiments, the throttle member196is configured to move up and down vertically in the z-direction relative to the C-shroud member185to control the flow of process gas through the vents186. In some embodiments, the throttle member196is configured to engage with and/or enter the vents186.

The upper wall185C of the C-shroud member185is configured to support an upper electrode187A/187B. In some embodiments, the upper electrode187A/187B includes an inner upper electrode187A and an outer upper electrode187B. Alternatively, in some embodiments, the inner upper electrode187A is present and the outer upper electrode187B is not present, with the inner upper electrode187A extending radially to cover the location that would be occupied by the outer upper electrode187B. In some embodiments, the inner upper electrode187A is formed of single crystal silicon and the outer upper electrode187B is formed of polysilicon. However, in other embodiments, the inner upper electrode187A and the outer upper electrode187B can be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the processes to be performed within the plasma processing region182. The inner upper electrode187A includes a number of throughports197defined as holes extending through an entire vertical thickness of the inner upper electrode187A. The throughports197are distributed across the inner upper electrode187A, relative to the x-y plane, to provide for flow of process gas(es) from a plenum region188above the upper electrode187A/187B to the plasma processing region182below the upper electrode187A/187B.

It should be understood that the distribution of throughports197across the inner upper electrode187A can be configured in different ways for different embodiments. For example, a total number of throughports197within the inner upper electrode187A and/or a spatial distribution of throughports197within the inner upper electrode187A can vary between different embodiments. Also, a diameter of the throughports197can vary between different embodiments. In general, it is of interest to reduce the diameter of the throughports197to a size small enough to prevent intrusion of the plasma180into the throughports197from the plasma processing region182. In some embodiments, as the diameter of the throughports197is reduced, the total number of throughports197within the inner upper electrode187A is increased to maintain a prescribed overall flowrate of process gas(es) from the process gas plenum region188through the inner upper electrode187A to the plasma processing region182. Also, in some embodiments, the upper electrode187A/187B is electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode187A and/or the outer upper electrode187B is/are electrically connected to either a respective direct current (DC) electrical supply or a respective radiofrequency power supply by way of a corresponding impedance matching circuit.

The plenum region188is defined by an upper member189. One or more gas supply ports192are formed through the chamber101and the upper member189to be in fluid communication with the plenum region188. The one or more gas supply ports192are fluidly connected (plumbed) to a process gas supply system191. The process gas supply system191includes one or process gas supplies, one or more mass flow controller(s), one or more flow control valve(s), among other devices, to provide controlled flow of one or more process gas(es) through the one or more gas supply ports192to the plenum region188, as indicated by arrow193. In some embodiments, the process gas supply system191also includes one or more components for controlling a temperature of the process gas(es). The process gas supply system191is connected to the control system120through one or more signal conductors194.

A processing gap (g1) is defined as the vertical (z-direction) distance as measured between the top surface of the ceramic layer110and the bottom surface of the inner upper electrode187A. The size of the processing gap (g1) can be adjusted by moving the cantilever arm assembly115in the vertical direction (z-direction). As the cantilever arm assembly115moves upward, the articulating outer support flange171eventually engages the lower wall185A of the C-shroud member185, at which point the articulating outer support flange171moves along the fixed outer support flange169as the cantilever arm assembly115continues to move upward until the set of support rods201engage the articulating outer support flange171and the prescribed processing gap (g1) size is achieved. Then, to reverse this movement for removal of the wafer W from the chamber, the cantilever arm assembly115is moved downward until the articulating outer support flange171moves away from the lower wall185A of the C-shroud member185. It should be understood thatFIG.1shows the system100in a closed configuration with the wafer W position on the ceramic layer110for plasma processing.

During plasma processing operations within the plasma processing system100, the one or more process gas(es) are supplied to the plasma processing region182by way of the process gas supply system191, plenum region188, and throughports197within the inner upper electrode187A. Also, radiofrequency signals are transmitted into the plasma processing region182, by way of the first and second radiofrequency signal generators147,149, the impedance matching system143, the radiofrequency signal supply rod137, the radiofrequency signal supply shaft141, the facilities plate111, the electrode109, and through the ceramic layer110. The radiofrequency signals transform the process gas(es) into the plasma180within the plasma processing region182. Ions and/or reactive constituents of the plasma interact with one or more materials on the wafer W to cause a change in composition and/or shape of particular material(s) present on the wafer W. The exhaust gases from the plasma processing region182flow through the vents186in the C-shroud member185and through the interior region103within the chamber101to the exhaust port105under the influence of a suction force applied at the exhaust port105, as indicated by arrows195.

In various embodiments, the electrode109can be configured to have different diameters. However, in some embodiments, to increase the surface of the electrode109upon which the edge ring167rests, the diameter of the electrode109is extended. In some embodiments, an electrically conductive gel226is disposed between a bottom of the edge ring167and the top of the electrode109and/or between the bottom of the edge ring167and the top of the coupling ring161. In these embodiments, the increased diameter of the electrode109provides more surface area upon which the conductive gel is disposed between the edge ring167and the electrode109.

It should be understood that the combination of the articulating outer support flange171, the electrically conductive straps173, and the fixed outer support flange169are electrically at a reference ground potential, and collectively form a ground return path for radiofrequency signals transmitted from the electrode109through the ceramic layer110into the plasma processing region182. The azimuthal uniformity of this ground return path around the perimeter of the electrode109can have an effect on uniformity of process results on the wafer W. For example, in some embodiments, the uniformity of etch rate across the wafer W can be affected by the azimuthal uniformity of the ground return path around the perimeter of the electrode109. To this end, it should be understood that the number, configuration, and arrangement of the electrically conductive straps173around the perimeter of the electrode109can affect the uniformity of process results across the wafer W.

With reference back toFIG.1, a Tunable Edge Sheath (TES) system is implemented to include a TES electrode225disposed (embedded) within the coupling ring161. The TES system also includes a number of TES radiofrequency signal supply pins223in physical and electrical connection with the TES electrode225. Each TES radiofrequency signal supply pin223extends through a corresponding insulator feedthrough member231configured to electrically separate the TES radiofrequency signal supply pin223from surrounding structures, such as from the ceramic support113and the cantilever arm assembly115structure. In some embodiments, o-rings227and229are disposed to ensure that the region inside of the insulator feedthrough member231is not exposed to any materials/gases present within the plasma processing region182. In some embodiments, the TES radiofrequency signal supply pins223are formed of copper, or aluminum, or anodized aluminum, among others.

The TES radiofrequency signal supply pins223extend into the open region118inside of the cantilever arm assembly115, where each of the TES radiofrequency signal supply pins223is electrically connected to a TES radiofrequency signal supply conductor219through a corresponding TES radiofrequency signal filter221. In some embodiments, three TES radiofrequency signal supply pins223are positioned to physically and electrically connect with the TES electrode225at substantially equally spaced azimuthal locations about the centerline of the electrode109. It should be understood, however, that other embodiments can have more than three TES radiofrequency signal supply pins223in physical and electrical connection with the TES electrode225. Also, some embodiments can have either one or two TES radiofrequency signal supply pins223in physical and electrical connection with the TES electrode225. Each TES radiofrequency signal supply pin223is electrically connected to a corresponding TES radiofrequency signal filter221, with each TES radiofrequency signal filter221electrically connected to the TES radiofrequency signal supply conductor219. In some embodiments, each TES radiofrequency signal filter221is configured as an inductor. For example, in some embodiments, each TES radiofrequency signal filter221is configured as a coiled conductor, such as a metal coil wrapped around a dielectric core structure. In various embodiments, the metal coil can be formed of solid copper rod, copper tubing, aluminum rod, or aluminum tubing, among others. Also, in some embodiments, each TES radiofrequency signal filter221can be configured as a combination of inductive and capacitive structures. In the interest of improving plasma processing result uniformity across the wafer W, each of the TES radiofrequency signal filters221has a substantially same configuration.

In some embodiments, the TES radiofrequency signal supply conductor219is formed as a ring-shaped (annular-shaped) structure, so as to extend around the open region118inside of the cantilever arm assembly115to enable physical and electrical connection of the azimuthally distributed TES radiofrequency signal filters221with the TES radiofrequency signal supply conductor219. In some embodiments, the TES radiofrequency signal supply conductor219is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES radiofrequency signal supply conductor219is formed as a tubular structure. In some embodiments, the TES radiofrequency signal supply conductor219is formed of copper, or aluminum, or anodized aluminum, among others.

The TES radiofrequency signal supply conductor219is electrically connected to a TES radiofrequency supply cable217. Also, a capacitor218is connected between the TES radiofrequency signal supply conductor219and a reference ground potential, such as the structure of the cantilever arm assembly115. More specifically, the capacitor218has a first terminal electrically connected to both the TES radiofrequency supply cable217and the TES radiofrequency signal supply conductor219, and the capacitor218has a second terminal electrically connected to the reference ground potential. In some embodiments, the capacitor218is a variable capacitor. In some embodiments, the capacitor218is a fixed capacitor. In some embodiments, the capacitor218is set to have a capacitance within a range extending from about 10 picoFarads to about 100 picoFarads. The TES radiofrequency supply cable217is connected to a TES impedance matching system211. The TES impedance matching system211is connected to a TES radiofrequency signal generator213. Radiofrequency signals generated by the TES radiofrequency signal generator213are transmitted through the TES impedance matching system211to the TES radiofrequency supply cable217, then to the TES radiofrequency signal supply conductor219, then through the TES radiofrequency signal filters221to the respective TES radiofrequency signal supply pins223, and to the TES electrode225within the coupling ring161. In some embodiments, the TES radiofrequency signal generator213is configured and operated to generate radiofrequency signals within a frequency range extending from about 50 kiloHertz to about 27 MHz. In some embodiments, the TES radiofrequency signal generator213supplies radiofrequency power within a range extending from about 50 Watts to about 10 kiloWatts. The TES radiofrequency signal generator213is also connected to the control system120through one or more signal conductors215.

The TES impedance matching system211includes an arrangement of inductors and capacitors sized and connected to provide for impedance matching so that radiofrequency power can be transmitted from the TES radiofrequency signal generator213along the TES radiofrequency supply cable217, along the TES radiofrequency signal supply conductor219, through the TES radiofrequency signal filters221, through the respective TES radiofrequency signal supply pins223, to the TES electrode225within the coupling ring161, and into the plasma processing region182above the edge ring167. The TES impedance matching system211is also connected to the control system120through one or more signal conductors214.

By transmitting radiofrequency signals/power through the TES electrode225disposed (embedded) within the coupling ring161, the TES system is capable of controlling characteristics of the plasma180near the peripheral edge of the wafer W. For example, in some embodiments, the TES system is operated to control the plasma180sheath properties near the edge ring167, such as by controlling a shape of the plasma180sheath and/or by controlling a size (either increase in sheath thickness or decrease in sheath thickness). Also, in some embodiments, by controlling the shape of the plasma180sheath near the edge ring167, it is possible to control various properties of the bulk plasma180over the wafer W. Also, in some embodiments, the TES system is operated to control a density of the plasma180near the edge ring167. For example, in some embodiments, the TES system is operated to either increase or decrease the density of the plasma180near the edge ring167. Also, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring167, which in turn controls/influences movement of ions and other charged constituents within the plasma180near the edge ring167. For example, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring167to attract more ions from the plasma180toward the edge of the wafer W. And, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring167to repel ions from the plasma180away from the edge of the wafer W. It should be understood that the TES system can be operated to perform a variety of different functions, such as those mentioned above, among others, either separately or in combination.

In some embodiments, the coupling ring161is formed of a dielectric material, such as quartz, or ceramic, or alumina (Al2O3), or a polymer, among others.

A bottom surface of the edge ring167has a portion that is coupled to the upper surface of the coupling ring161through a layer of thermally and electrically conductive gel to thermally sink the coupling ring161to the edge ring167. Also, the bottom surface of the edge ring167has another portion that is coupled to an upper surface of the electrode109through a layer of thermally and electrically conductive gel. Examples of the thermally and electrically conductive gel include polyimide, polyketone, polyetherketone, polyether sulfone, polyethylene terephthalate, fluoroethylene propylene copolymers, cellulose, triacetates, and silicone, among others. In some embodiments, the thermally and electrically conductive gel is formed as a double-sided tape. In some embodiments, the edge ring167has an inner diameter sized to be proximate to the outer diameter of the ceramic layer110.

In various embodiments, the TES electrode225is formed of an electrically conductive material, such as platinum, steel, aluminum, or copper, among others. During operation, capacitive coupling occurs between the TES electrode225and the edge ring167, such that the edge ring167is electrically powered to influence processing of the wafer W near the outer perimeter of the wafer W.

Broadly speaking, implementations of the disclosure provide for a CCP chamber having at least one magnetic coil positioned outside the chamber. In some implementations, a single magnetic coil or multiple magnetic coils are positioned above or on top of the chamber. A DC current is applied to the magnetic coil to generate a magnetic field (B-field). With the B-field from these currents, control over center non-uniformity is achieved. In some implementations, using a combination of different coils provides for different magnetic fields to enable more control over overall uniformity.

Standard plasma systems are prone to non-uniformities where there is accumulation of positive and negative ions, as their densities are at least partially controlled by electron density and further based on temperature. To address such non-uniformities, implementations of the disclosure contemplate the application of a static B-field to the plasma to minimize localized charged species accumulation and thereby improve uniformity.

Without being bound by any particular theory of operation, it is believed that in accordance with implementations of the disclosure, the B-field is configured to be relatively weak, so that it does not completely magnetize the plasma. However, electrons which are sensitive to the B-field are affected. Thus, it is believed that the B-field is used to change the direction of diffusion of the electrons so that the electrons travel approximately along the field lines. In this manner, the B-field can be utilized to affect and control the amount of electrons in the middle that discharge. By providing an approximately vertical B-field in the central portion of the plasma, from top to bottom, then electrons that tend to collect in the middle can magnetize so that the electrons move approximately along the B-field lines. Hence, there will be more losses to the upper and lower electrons, and therefore a consequent reduction in the amount of electrons in the center portion.

FIG.2Aconceptually illustrates a cross-section of a process chamber having a single magnetic coil for applying a magnetic field during plasma processing, in accordance with implementations of the disclosure. As shown, a single magnetic coil200is disposed over the chamber101. It will be appreciated that the magnetic coil200is substantially circular in shape or ring-shaped or annular in shape. Further, the magnetic coil200is disposed along a plane that is parallel to the surface plane of the wafer. That is, the windings/turns of the magnetic coil are substantially along a horizontal plane that is parallel to the plane of the wafer, so that the magnetic coil itself is horizontally oriented, and centered about an axis perpendicular through the center of the wafer. In some implementations, the magnetic coil200has a diameter (center to center diameter, or inner diameter, or outer diameter) in the range of approximately 15 to 20 inches (approximately 38 to 51 cm) for a chamber configured to process a 300 mm wafer; in some implementations, the diameter is in the range of approximately 16 to 18 inches (approximately 41 to 46 cm).

In some implementations, the height of the magnetic coil200above the surface level of the wafer is in the range of approximately 3 to 15 inches (approximately 8 to 38 cm); in some implementations, in the range of approximately 5 to 12 inches (approximately 13 to 30 cm); in some implementations, approximately 7 to 8 inches (approximately 18 to 20 cm).

In accordance with implementations of the disclosure, a DC current is applied to the magnetic coil200to produce a static B-field in the chamber101.

FIG.2Bconceptually illustrates a cross-section of a process chamber having two magnetic coils for applying a magnetic field during plasma processing, in accordance with implementations of the disclosure. As shown, a first magnetic coil200and a second magnetic coil202are concentric coils disposed over the chamber101. In some implementations, the first and second magnetic coils200and202are approximately coplanar. In some implementations, the first and second magnetic coils200and202are not coplanar, but positioned in parallel planes, while being concentric about the same central axis. In some implementations, the first magnetic coil200has a diameter as described above with respect toFIG.2A.

In some implementations, the second magnetic coil202has a diameter (center to center diameter, or inner diameter, or outer diameter) in the range of approximately 20 to 25 inches (approximately 51 to 63 cm) for a chamber configured to process a 300 mm wafer; in some implementations, the diameter of the second magnetic coil202is in the range of approximately 22 to 24 inches (approximately 56 to 61 cm).

In accordance with implementations of the disclosure, DC currents are applied to the magnetic coils200and202to produce a static B-field in the chamber101. In various implementations, the DC currents applied to each of the coils can be approximately the same or different, and in the same direction or opposite directions.

Though not specifically shown, it will be appreciated that in other implementations, there can be additional magnetic coils disposed over the chamber101. For example, in some implementations, a third magnetic coil is provided, also disposed over the chamber101, and having a diameter smaller than the first magnetic coil200. In some implementations, such a third magnetic coil has a diameter in the range of approximately 10 to 15 inches (approximately 25 to 38 cm) for a chamber configured to process a 300 mm wafer; in some implementations, the third magnetic coil has a diameter in the range of approximately 11 to 13 inches (approximately 28 to 33 cm).

In some implementations, the first, second and third magnetic coils are approximately coplanar. In some implementations, the first, second, and third magnetic coils are not coplanar, but positioned in parallel planes, while being concentric about the same central axis. In some implementations, two of the magnetic coils are coplanar, while the other magnetic coil is not coplanar with either of the two that are coplanar.

In some implementations, there can be additional magnetic coils disposed over the chamber101.

FIG.2Cconceptually illustrates a cross-section of a process chamber having three magnetic coils for applying a magnetic field during plasma processing, in accordance with implementations of the disclosure. As shown in the illustrated implementation, two magnetic coils200and202are disposed over the chamber101. In some implementations, the magnetic coils200and202are configured similar to the implementation ofFIG.2B. Furthermore, a bottom magnetic coil204is disposed below the electrode109, so as to be below the plasma processing region182. In some implementations, the bottom magnetic coil204has a diameter (center to center diameter, or inner diameter, or outer diameter) in the range of approximately 10 to 25 inches (approximately 25 to 63 cm). In accordance with implementations of the disclosure, a DC current is applied to the magnetic coil204, alone or in combination with DC current applied to other magnetic coils, to produce a static B-field in the chamber101.

Though a single bottom magnetic coil204is shown and described in the illustrated implementation, in other implementations, there can be more than one bottom magnetic coil. In the case of multiple bottom magnetic coils, such bottom magnetic coils can be coplanar or not coplanar with each other.

FIG.2Dconceptually illustrates a cross-section of a process chamber having four magnetic coils for applying a magnetic field during plasma processing, in accordance with implementations of the disclosure. As shown in the illustrated implementation, similar to the configuration ofFIG.2C, there are two magnetic coils200and202disposed over the chamber101, and a bottom magnetic coil104disposed below the electrode109. Furthermore, a side magnetic coil206is positioned so as to laterally surround the plasma processing region182. In some implementations, the side magnetic coil206is positioned adjacent to the C-shroud member185. In some implementations, the side magnetic coil206is positioned adjacent to the walls101aof the chamber101. In some implementations, the side magnetic coil206is vertically positioned so as to be approximately at the height of at least a portion of the plasma processing region182. In some implementations, the side magnetic coil206has a diameter (center to center diameter, or inner diameter, or outer diameter) in the range of approximately 25 to 30 inches (approximately 63 to 76 cm) for a chamber configured to process a 300 mm wafer. In accordance with implementations of the disclosure, a DC current is applied to the magnetic coil206, alone or in combination with DC currents applied to other magnetic coils, to produce a static B-field in the chamber101.

Though a single side magnetic coil206is shown and described in the illustrated implementation, in other implementations, there can be more than one side magnetic coil. In some implementations, multiple side magnetic coils are provided and configured to have the same diameter and are vertically aligned with one another. In some implementations, multiple side magnetic coils can have different diameters and may be coplanar or non-coplanar with one another.

As described, in various implementations, there can be one or more magnetic coils positioned above, below, and/or surrounding the plasma processing region182. Each magnetic coil is supplied with a DC current to generate a static B-field in the plasma processing region182. Broadly speaking, in some implementations, the B-field is created substantially in the z-direction in the central portion of the plasma processing region182, so as to effect suppression of the center etch rate. Thus, if a given CCP chamber exhibits a peak in etch rate at the center portion of the wafer, then the B-field can be applied to the plasma to suppress the center peak.

In some implementations, a magnetic coil in accordance with implementations of the disclosure is formed from insulated copper wire, or magnet wire. In some implementations, the magnet wire is approximately 16 to 10 AWG magnet wire. In some implementations, the coiling of the magnet wire is configured to have approximately 30 to 60 turns for a given magnetic coil. In some implementations, the coiling is configured to have approximately 40 to 50 turns. In some implementations, the magnetic coil has a cross sectional width or height of approximately 1 to 3 cm.

In some implementations, a magnetic coil in accordance with implementations of the disclosure is supported by a support structure formed from an insulating material (e.g. plastic insulator), so as to further insulate the magnetic coil from other components or hardware.

By comparison to other applications of magnetic fields in the context of plasma processing, the B-field generated in accordance with implementations of the disclosure is a low strength field, so that there is minimal effect on other components. However, electrons in the plasma are affected by the B-field in such a manner as to promote reduced localized accumulation of charged species and therefore improve plasma and etch uniformity. In some implementations, the strength of the generated B-field is configured to be less than approximately 10 Gauss (measured at the wafer level and approximately in the center); in some implementations, less than approximately 5 Gauss.

It will be appreciated that correspondingly low current levels are applied to produce the weak magnetic fields in accordance with implementations of the disclosure. In some implementations, the applied current to a given magnetic coil is approximately 10 amps or less; in some implementations, approximately 7 amps or less; in some implementations, approximately 5 amps or less; in some implementations, approximately 3 amps or less.

Though a low strength magnetic field is provided, the chamber walls are typically constructed from an aluminum and/or silicon-containing material, and therefore the B-field penetrates the chamber.

Still, even a low strength magnetic field may interfere with nearby devices. Hence, in some implementations, a cover constructed from a nickel-containing material is provided, to shield nearby devices from the magnetic field.

Previous applications of a magnetic field in plasma processing have employed a much stronger magnetic field, where the direction of the field is parallel to the wafer. This promoted electron movement along B-field lines parallel to the surface of the wafer, and was performed as a way to control overall uniformity. However, such applications were prone to device damage, as there was also charge accumulation on the device, and the interaction of the strong B-field tended to produce device damage.

However, in contrast to these prior uses of a strong magnetic field, implementations of this disclosure employ a very low strength B-field by comparison. It has been observed that B-fields generated by magnetized steel parts, and even very weak electric fields, can have an effect on uniformity at the center. Further, as device sizes shrink and the tolerance for non-uniformity is reduced (e.g. significantly below 1%), so changes in ion density can have a significant impact on uniformity. Generally, in accordance with implementations of the disclosure, the greater the strength of the B-field that is applied, the greater the suppression of etch rate in the center portion of the wafer.

FIG.3Ais a graph illustrating etch rate results for a continuous wave plasma under different applied B-fields, in accordance with implementations of the disclosure. In the illustrated implementation, etch rate as a function of radius is shown for a continuous wave plasma process carried out on a blanket oxide wafer. The curve300is a plot showing etch rate results with zero applied current to a magnetic coil as described in the above implementations. The curve302is a plot showing etch rate results with a 5 Amp current applied to the magnetic coil. The curve304is a plot showing etch rate results with a 10 Amp current applied to the magnetic coil. As can be seen from the results, with zero current applied to the magnetic coil as shown by curve300), there is significant peaking of the etch rate in the central portion of the wafer. However, as current in the magnetic coil is increased to 5 Amps (curve302) and to 10 Amps (curve304), so the etch rate in the central portion of the wafer is reduced. This result demonstrates the effectiveness of increasing the B-field to reduce center etch rate peaking, and thereby reduce the non-uniformity of etch rate.

FIG.3Bis a graph illustrating the change in etch rate that is effected by the applied B-field, in accordance with the implementation ofFIG.3A. As indicated inFIG.3B, the curve306is a plot showing the change (or delta) in etch rate of the continuous wave plasma process performed with the 5 Amp current applied to the magnetic coil (as previously indicated by curve302) versus the zero current condition (as previously indicated by curve300). The curve308is a plot showing the change in etch rate of the continuous wave plasma process performed with the 10 Amp current applied to the magnetic coil (as previously indicated by curve304) versus the zero current condition.

As shown by the etch rate delta results, the application of a B-field, in accordance with implementations of the disclosure, provides a significant reduction in etch rate principally in the central portion of the wafer (e.g. within an approximate 50 mm radius). Also, the reduction in etch rate is greater with a stronger applied B-field.

FIG.4Ais a graph illustrating etch rate as a function of wafer radius for a plasma process with different applied B-fields, in accordance with implementations of the disclosure. In the illustrated implementation, etch rate on a blanket oxide wafer is shown for a pulsed plasma process. In the illustrated implementation, the curve400illustrates etch rate as a function of wafer radius for a pulsed plasma process with zero current applied to a magnetic coil, as described above in accordance with implementations of the disclosure. The curve402illustrates etch rate as a function of wafer radius for the pulsed plasma process with 5 Amps current applied to the magnetic coil. The curve404illustrates etch rate as a function of wafer radius for the pulsed plasma process with 10 Amps current applied to the magnetic coil. As shown, in the zero current condition, such that no additional B-field is applied (other than existing ambient fields), there is a significant peak in etch rate towards the center of the wafer. However, as current is applied to the magnetic coil at 5 Amps, so the center peak in etch rate is reduced. And as current is applied to the magnetic coil at 10 Amps, the center etch rate is further reduced. This, as the applied B-field is increased, the etch rate in the center portion of the wafer becomes more diminished, thereby reducing non-uniformity across the center of the wafer.

FIG.4Bis a graph showing the change in etch rate as a result of applied B-fields, in accordance with the implementation ofFIG.4A. The curve406illustrates the change in etch rate for the pulsed plasma process with the 5 Amp current applied to the magnetic coil as compared to the zero current condition. The curve408illustrates the change in etch rate for the pulsed plasma process with the 10 Amp current applied to the magnetic coil as compared to the zero current condition. As can be seen, the effect of the applied B-field primarily reduces etch rate in the center portion of the wafer (e.g. within approximately a 50 mm radius of the center).

FIG.5shows cross-section images of portions of wafers having etched features thereon, demonstrating the effect of an applied B-field on feature tilting, in accordance with implementations of the disclosure. The upper images provide cross-sectional views of wafer portions having etched features which were processed without an applied B-field. Whereas the lower images provide cross-sectional views of wafer portions having etched features which were processed with an applied B-field (resulting from application of a 1 Amp current to a magnetic coil). As can be seen, features etched under an applied B-field exhibit less tilting and are more vertical than features etched in the absence of the applied B-field. Applying the B-field improves tilt because the applied B-field changes the shape of the plasma sheath at the wafer. Non-uniform plasma results in tilting at some radiuses, and therefore applying a magnetic field to the plasma that reduces non-uniformity also can reduce tilting and enable more vertical etching.

In accordance with some implementations, a system having four magnetic coils disposed above the chamber is provided. The four magnetic coils are substantially coplanar, and concentric about the same axis, which is substantially perpendicular through the center of the wafer. The four magnetic coils are referenced as coil “A”, “B”, “C”, and “D”. Coil A has an inner diameter of approximately 12 inches (approximately 30 cm); coil B has an inner diameter of approximately 14 inches (approximately 36 cm); coil C has an inner diameter of approximately 17 inches (approximately 43 cm); and coil D has an inner diameter of approximately 23 inches (approximately 58 cm). By varying which coils receive current, the amount of current applied to a given coil, and the direction of current applied to a given coil, various magnetic profiles can be achieved, which can be tuned, for example, to reduce radial etch non-uniformity.

FIG.6Aillustrates magnetic field strength at the wafer level in the z-direction (vertical direction, or perpendicular to the wafer surface) versus radial position along a 300 mm diameter wafer, for various single coil current configurations, in accordance with implementations of the disclosure. That is, currents were applied to a single one of coils A, B, C, and D, and the strength of the magnetic field in the z-direction was measured in Gauss.

A positive current indicates current applied in a counterclockwise direction, when considered from an overhead view of the coil. Accordingly, a negative current indicates current applied in a clockwise direction.

In the illustrated implementation, the legend for the graph is of the following form: (coil #)(current)_(coil #)(current)_(coil #)(current)_(coil #)(current). Thus, the curve indicated as “A5_B0_C0_D0” can be understood as the result for a 5 Amp current applied to coil A, and zero currents applied to coils B, C, and D. The curve indicated as “A-5_B0_C0_D0” can be understood as the result for a −5 Amp current applied to coil A, and zero currents applied to coils B, C, and D. The curve indicated as “A0_B5_C0_D0” can be understood as the result for a 5 Amp current applied to coil B, and zero currents applied to coils A, C, and D, and so forth.

FIG.6Billustrates magnetic field strength at the wafer level in the radial direction (in Gauss) versus radial position along a 300 mm diameter wafer, for various single coil current configurations, in accordance with the implementations ofFIG.6A. As can be seen from these results, radial B-field strength at the wafer edge is comparable to z-direction B-field strength.

In some implementations, it will be appreciated that magnetic field strength at the wafer level is approximately one-third of the magnetic field strength at the level of the magnetic coils.

FIG.7Ais a graph illustrating thermal oxide etch rate versus radial position along a 300 mm wafer, for various positive currents (counterclockwise) applied to single coils A (12″), B (14″), C (17″), and D (23″), in accordance with implementations of the disclosure.

FIG.7Bis a graph illustrating thermal oxide etch rate versus radial position along a 300 mm wafer, for various negative currents (clockwise) applied to single coils A (12″), B (14″), C (17″), and D (23″), in accordance with implementations of the disclosure.

As the results ofFIGS.7A and7Bdemonstrate, different coil sizes and currents can have different impacts on oxide etch rates. For the same coil, opposite current directions can have different impacts on oxide etch rates, especially at lower current magnitudes. This can be understood, as when the coil induced B-field is lower, then the ambient B-field offset has a more significant effect.

FIG.8Aillustrates magnetic field strength at the wafer level in the z-direction (vertical direction, or perpendicular to the wafer surface) versus radial position along a 300 mm diameter wafer, for various two-coil current configurations, in accordance with implementations of the disclosure. That is, currents were applied to two of coils A, B, C, and D, and the strength of the magnetic field in the z-direction was measured in Gauss.

FIG.8Billustrates magnetic field strength at the wafer level in the radial direction (in Gauss) versus radial position along a 300 mm diameter wafer, for various two-coil current configurations, in accordance with the implementations ofFIG.8A.

As these results demonstrate, by combining different coil currents with the same or different directions, it is possible to create different B-field profiles along the wafer radius, and thereby achieve different effects on plasma and etch profiles.

FIG.9Aillustrates magnetic field strength at the wafer level in the z-direction (vertical direction, or perpendicular to the wafer surface) versus radial position along a 300 mm diameter wafer, for various three-coil current configurations, in accordance with implementations of the disclosure. That is, currents were applied to three of coils A, B, C, and D, and the strength of the magnetic field in the z-direction was measured in Gauss.

FIG.9Billustrates magnetic field strength at the wafer level in the radial direction (in Gauss) versus radial position along a 300 mm diameter wafer, for various three-coil current configurations, in accordance with the implementations ofFIG.9A.

As these results demonstrate, by combining different coil currents with the same or different directions, it is possible to create different B-field profiles along the wafer radius, and thereby achieve different effects on plasma and etch profiles.

FIG.10Ais a graph illustrating etch rate as a function of radial position along a 300 mm wafer, for a two coil combination, in accordance with implementations of the disclosure. In the illustrated implementation, the specific two-coil combination includes coil A (12″ diameter) and coil D (23″ diameter).

FIG.10Bis a graph illustrating the etch rate delta as compared to a zero current condition, in accordance with the implementations ofFIG.10A.

As shown, different current combinations between the 12″ and 23″ coils can provide adjustability affecting the etch rate uniformity.

FIG.11is a conceptual schematic diagram of a system for controlling power to multiple magnetic coils, in accordance with implementations of the disclosure. In the illustrated implementation, the control system120is operatively connected to, and controls the operation of, several DC power supplies1100,1102,1104, and1106. The DC power supplies respectively apply a DC current to magnetic coils1108,1110,1112, and1114. The control system120can control the magnitude/strength of the DC current (e.g. Amperage) and the polarity (e.g. positive or negative; or, counterclockwise or clockwise) of the DC current supplied by a given one of the DC power supplies.

In some implementations, the magnetic coils1108,1110,1112, and1114are the coils A, B, C, and D described above. In some implementations, the magnetic coils1108,1110,1112, and1114can be any of the magnetic coils described in accordance with the various implementations of the disclosure. Though four magnetic coils and four corresponding DC power supplies are shown, it will be appreciated that there can be additional magnetic coils and DC power supplies in other implementations.

In some implementations, a user interface is provided to enable an operator to adjust the parameters of the DC power supplies, such as by providing settings for adjustment of the DC current magnitude, and its polarity, for any given DC power supply.

As has been discussed, in some implementations, application of a B-field during plasma processing can be used to reduce plasma non-uniformity, and thereby reduce etch non-uniformity. Furthermore, in some implementations, application of the B-field can be used for chamber matching, to compensate for variation between tools due to environmental magnetic fields. Ambient magnetic fields can vary from tool to tool, and therefore an applied B-field can be used to counter/offset such ambient environmental fields, and thereby provide consistency from tool to tool.

It will be appreciated that any of the methods described in the present disclosure can be implemented to run automatically by the control system120.

FIG.12shows an example schematic of the control system120ofFIG.1, in accordance with some embodiments. In some embodiments, the control system120is configured as a process controller for controlling the semiconductor fabrication process performed in plasma processing system100. In various embodiments, the control system120includes a processor1401, a storage hardware unit (HU)1403(e.g. memory), an input HU1405, an output HU1407, an input/output (I/O) interface1409, an I/O interface1411, a network interface controller (NIC)1413, and a data communication bus1415. The processor1401, the storage HU1403, the input HU1405, the output HU1407, the I/O interface1409, the I/O interface1411, and the NIC1413are in data communication with each other by way of the data communication bus1415. The input HU1405is configured to receive data communication from a number of external devices. Examples of the input HU1405include a data acquisition system, a data acquisition card, etc. The output HU1407is configured to transmit data to a number of external devices. An examples of the output HU1407is a device controller. Examples of the NIC1413include a network interface card, a network adapter, etc. Each of the I/O interfaces1409and1411is defined to provide compatibility between different hardware units coupled to the I/O interface. For example, the I/O interface1409can be defined to convert a signal received from the input HU1405into a form, amplitude, and/or speed compatible with the data communication bus1415. Also, the I/O interface1407can be defined to convert a signal received from the data communication bus1415into a form, amplitude, and/or speed compatible with the output HU1407. Although various operations are described herein as being performed by the processor1401of the control system120, it should be understood that in some embodiments various operations can be performed by multiple processors of the control system120and/or by multiple processors of multiple computing systems in data communication with the control system120.

In some embodiments, the control system120is employed to control devices in various wafer fabrication systems based in-part on sensed values. For example, the control system120may control one or more of valves1417, filter heaters1419, wafer support structure heaters1421, pumps1423, and other devices1425based on the sensed values and other control parameters. The valves1417can include valves associated with control of the backside gas supply system129, the process gas supply system191, and the temperature control fluid circulation system125. The control system120receives the sensed values from, for example, pressure manometers1427, flow meters1429, temperature sensors1431, and/or other sensors1433, e.g. voltage sensors, current sensors, etc. The control system120may also be employed to control process conditions within the plasma processing system100during performance of plasma processing operations on the wafer W. For example, the control system120can control the type and amounts of process gas(es) supplied from the process gas supply system191to the plasma processing region182. Also, the control system120can control operation of the first radiofrequency signal generator147, the second radiofrequency signal generator149, the impedance matching system143, the TES radiofrequency signal generator213, and the TES impedance matching system211. Also, the control system120can control operation of the DC supply117for the clamping electrode(s)112. The control system120can also control operation of the lifting devices133for the lift pins132and operation of the door107. The control system120also controls operation of the backside gas supply system129and the temperature control fluid circulation system125. The control system120also control vertical movement of the cantilever arm assembly115. The control system120also controls operation of the throttle member196and the pump that controls suction at the exhaust port105. The control system120also controls operation of the hold-down control mechanisms913of the hold-down rods911of the TES system1000. The control system120also receives input from the temperature probe of the TES system1000. It should be understood that the control system120is equipped to provide for programmed and/or manual control any function within the plasma processing system100.

In some embodiments, the control system120is configured to execute computer programs including sets of instructions for controlling process timing, process gas delivery system temperature, and pressure differentials, valve positions, mixture of process gases, process gas flow rate, backside cooling gas flow rate, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequencies, RF pulsing, impedance matching system143settings, cantilever arm assembly position, bias power, and other parameters of a particular process. Other computer programs stored on memory devices associated with the control system120may be employed in some embodiments. In some embodiments, there is a user interface associated with the control system120. The user interface include a display1435(e.g. a display screen and/or graphical software displays of the apparatus and/or process conditions), and user input devices1437such as pointing devices, keyboards, touch screens, microphones, etc.

Software for directing operation of the control system120may be designed or configured in many different ways. Computer programs for directing operation of the control system120to execute various wafer fabrication processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. Compiled object code or script is executed by the processor1401to perform the tasks identified in the program. The control system120can be programmed to control various process control parameters related to process conditions such as, for example, filter pressure differentials, process gas composition and flow rates, backside cooling gas composition and flow rates, temperature, pressure, plasma conditions, such as RF power levels and RF frequencies, bias voltage, cooling gas/fluid pressure, and chamber wall temperature, among others. Examples of sensors that may be monitored during the wafer fabrication process include, but are not limited to, mass flow control modules, pressure sensors, such as the pressure manometers1427and the temperature sensors1431. Appropriately programmed feedback and control algorithms may be used with data from these sensors to control/adjust one or more process control parameters to maintain desired process conditions.

In some implementations, the control system120is part of a broader fabrication control system. Such fabrication control systems can include semiconductor processing equipment, including a processing tools, chambers, and/or platforms for wafer processing, and/or specific processing components, such as a wafer pedestal, a gas flow system, etc. These fabrication control systems may be integrated with electronics for controlling their operation before, during, and after processing of the wafer. The control system120may control various components or subparts of the fabrication control system. The control system120, depending on the wafer processing requirements, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, the delivery of backside cooling gases, temperature settings (e.g. heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

The control system120, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the plasma processing system100, or otherwise networked to the system100, or a combination thereof. For example, the control system120may be in the “cloud” of all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system100to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to the system100over a network, which may include a local network or the Internet.

The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system100from the remote computer. In some examples, the control system120receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed within the plasma processing system100. Thus as described above, the control system120may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on the plasma processing system100in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process performed on the plasma processing system100.

Without limitation, example systems that the control system120can interface with may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers. As noted above, depending on the process step or steps to be performed by the tool, the control system120might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

Embodiments described herein may also be implemented in conjunction with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. Embodiments described herein can also be implemented in conjunction with distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network. It should be understood that the embodiments described herein, particularly those associated with the control system120, can employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus may be specially constructed for a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. In some embodiments, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network, the data may be processed by other computers on the network, e.g. a cloud of computing resources.

Various embodiments described herein can be implemented through process control instructions instantiated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit that can store data, which can be thereafter be read by a computer system. Examples of the non-transitory computer-readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. The non-transitory computer-readable medium can include computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

Although the foregoing disclosure includes some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features of any other embodiment disclosed herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and what is claimed is not to be limited to the details given herein, but may be modified within the scope and equivalents of the described embodiments.