Implementing memory device with sub-bank architecture

A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method, system and memory controller for implementing memory devices with a sub-bank architecture.

DESCRIPTION OF THE RELATED ART

As computer system performance continues to increase the number of cores and threads per processor socket also increase, which requires more memory performance.

Memory performance could be improved by increasing the average bandwidth. Memory bandwidth is limited by several DRAM core parameters, while the bank cycle time is one of most critical factors. However, it is very difficult to shorten the bank cycle time because it is limited by RC time constant that cannot be decreased without significant area overhead. The other way to overcome this is to have a larger number of banks per chip, which is also difficult due to die size overhead.

A need exists for an effective mechanism for implementing memory devices with sub-bank architecture to improve performance in a computer system.

As used in the following description and claims, the terms controller or memory controller should be broadly understood to include a memory controller, a storage controller, an input/output (IO) adapter (IOA), and a storage interface.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method, system and memory controller for implementing memory devices with a sub-bank architecture in a computer system. Other important aspects of the present invention are to provide such method, system and memory controller substantially without negative effects and that overcome many of the disadvantages of prior art arrangements.

In brief, a method, system and memory controller for implementing memory devices with q sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.

In accordance with features of the invention, an addressing method or protocol is provided where read or write command carry a sub-block address.

In accordance with features of the invention, a row decoder or word line driver circuit enables activation of multiple word lines in one row decoder block.

In accordance with features of the invention, a controller converts an address into bank/block/row/column addresses.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with features of the invention, a method, system and memory controller are provided for implementing memory devices with a sub-bank architecture. The number of banks per chip is effectively increased by enabling use a single bank as multiple banks or sub-banks.

Having reference now to the drawings, inFIG. 1, there is shown a computer system embodying the present invention generally designated by the reference character100for implementing memory devices with a sub-bank architecture in accordance with the preferred embodiment. Computer system100includes one or more processors102or general-purpose programmable central processing units (CPUs)102, #1-N. As shown, computer system100includes multiple processors102typical of a relatively large system; however, system100can include a single CPU102. Computer system100includes a cache memory104connected to each processor102.

Computer system100includes a memory system106including a memory controller108and a main memory110connected by a bus112. Bus112is one or more busses that send address/command information to main memory110and send and receive data from the memory110. Main memory110is a random-access semiconductor memory for storing data, including programs. Main memory110is comprised of, for example, a dynamic random access memory (DRAM), a synchronous direct random access memory (SDRAM), a current double data rate (DDRx) SDRAM, non-volatile memory, optical storage, and other storage devices.

I/O bus interface114, and buses116,118provide communication paths among the various system components. Bus116is a processor/memory bus, often referred to as front-side bus, providing a data communication path for transferring data among CPUs102and caches104, memory controller108and I/O bus interface unit114. I/O bus interface114is further coupled to system I/O bus118for transferring data to and from various I/O units.

As shown, computer system100includes a storage interface120coupled to storage devices, such as, a direct access storage device (DASD)122, and a CD-ROM124. Computer system100includes a terminal interface126coupled to a plurality of terminals128, #1-M, a network interface130coupled to a network132, such as the Internet, local area or other networks, and a I/O device interface134coupled to I/O devices, such as a first printer/fax136A, and a second printer136B.

I/O bus interface114communicates with multiple I/O interface units120,126,130,134, which are also known as I/O processors (IOPs) or I/O adapters (IOAs), through system I/O bus116. System I/O bus116is, for example, an industry standard PCI bus, or other appropriate bus technology.

In accordance with features of the invention, memory devices with a sub-bank architecture in accordance with the preferred embodiments advantageously are used for a selected one of or both the main memory110, and processor cache104.

Computer system100is shown in simplified form sufficient for understanding the present invention. The illustrated computer system100is not intended to imply architectural or functional limitations. The present invention can be used with various hardware, software and firmware implementations and systems, various other internal software and firmware, and other internal hardware devices.

Referring toFIGS. 2A,2B, and2C, there is shown an example memory device generally designated by the reference character200in accordance with the preferred embodiments.

InFIG. 2A, the memory device200advantageously embodying memory devices with a sub-bank architecture in accordance with the preferred embodiments includes a plurality of memory banks 0-3,202. A memory device200, for example, a dynamic random access memory (DRAM), is usually composed of several banks. The memory banks 0-3,202are storage resources or cell arrays that can be accessed independently of each other, and looking like several chips inside a single chip. This increases performance.

As shown inFIG. 2B, each of the plurality of memory banks 0-3,202of the memory device200includes a respective column decode204and a row decode206, costing more area with an increased number of banks.

InFIG. 2C, each of the plurality of memory banks 0-3,202(one shown) of the memory device200includes a plurality of cell sub-array210located between adjacent bit-line sense amplifier (BLSA) regions or BLSA rows212.FIG. 2Cincludes a detail view of the cell sub-array302including a plurality of cells214with a respective BL (bit line)216and WL (word line)218.

In accordance with features of the invention, cell sub-array or sub-blocks210are alternated with rows of sense amplifiers220. The alternated rows222,224of sense amplifiers220include a particular row222of sense amplifiers110that connects only to odd bit lines and a next row224of sense amplifiers220that connects only to even bit lines.

FIG. 3illustrates a problem of an example memory bank including a only pair of sense amplifier (SA) rows so that with each bit line having so many junction loadings sensing would be extremely slow. As a result, the illustrated example memory bank would not be implemented in actual memory banks, which are composed of many SA rows.

Referring toFIGS. 4A,4B,4C,4D, and4E, which together provide example prior art operations of a memory device.

InFIG. 4A, one word line is activated a sense amplifier in a bit-line sense amplifier (BLSA) region at the bottom of the cell block including the activated word line is used. InFIG. 4B, one word line is activated, a sense amplifier in the bit-line sense amplifier (BLSA) region at the top of the cell block including the activated word line is used.

InFIG. 4C, one word line is activated, a sense amplifier in the bit-line sense amplifier (BLSA) region at the top and the bottom of the cell block including the activated word line are used. As shown, the word line in the adjacent block can not be activated, since the sense amplifier can sense only one cell at a time.

InFIG. 4D, two word lines are activated, a sense amplifier in the bit-line sense amplifier (BLSA) region at the top and the bottom of the respective cell blocks including the activated word line are used. As shown, the word line in each adjacent block is not be activated, the three activated word lines are within blocks that are spaced-apart by at least one cell block.

InFIG. 4E, three word lines are activated, a sense amplifier in the bit-line sense amplifier (BLSA) region at the top and the bottom of the respective cell blocks including the activated word line are used. As shown, the word line in the adjacent block is not activated; the two activated word lines are within blocks that are spaced-apart by a cell block. Any word line can be also activated as long as the block is not adjacent to any of the blocks with word lines already activated. This way, for example, more than one WL (maximum=# blocks/2) can be activated within a bank.

Referring toFIG. 5, there is shown an example memory device having a sub-bank architecture generally designated by the reference character500in accordance with the preferred embodiments. Memory device500includes a plurality of sub-banks or sub-blocks 0-7,502, as shown, each including, for example512WL per sub-block. Each of the sub-blocks 0-7,502having odd and even bit lines, are alternated with rows of sense amplifiers504,506; where for example, a particular row of sense amplifiers504connects only to even bit lines and a next row of sense amplifiers506connects only to odd bit lines. Memory device500includes a row decoder520for the 8 sub-blocks502receiving address RA[0:17] and BLA[0:2], where BLA represent sub-block address, which is sent only for a RD/WR command.

Referring toFIG. 6, there are shown example addresses for the memory device having a sub-bank architecture generally designated by the reference character600in accordance with the preferred embodiments. Memory device addresses600include a pin602, ACT (Row Activation command)604and RD/WR command606.

FIG. 7illustrates an example prior art or conventional word line driver circuit. The prior art word line driver includes a word buffer producing a word line driver output WLxyz. The prior art word line driver includes a stack of a first P-channel field effect transistor (PFET) and a plurality of N-channel field effect transistors (NFETs) connected between a supply voltage and ground, respectively receiving respective gate inputs of RAx, RAx, RAy, RAz, RAw and a plurality of pull-up P-channel field effect transistors (PFETs) connected between the supply voltage and the word buffer receive respective gate inputs of RAx, RAy, RAz, RAw.

Referring toFIG. 8, there is shown an example word line driver circuit generally designated by the reference character800in accordance with the preferred embodiments for the memory device having a sub-bank architecture, such as memory device500. The word line driver circuit includes a transistor stack802of a first P-channel field effect transistor (PFET)804and a plurality of N-channel field effect transistors (NFETs)806,808,810,812, and814connected between a supply voltage and ground, respectively receiving respective gate inputs of pPRE, RAx, RAy, RAz, RAw, and Pact. A word line driver output WLxyz is provided by a driver hold state816defined by cross-coupled inverters818,820connected to the transistor stack802at a series connection between PFET804and NFET806.

Referring toFIG. 9, there is shown an example command, address, and data timing chart generally designated by the reference character900in accordance with the preferred embodiments for the memory device having a sub-bank, such as memory device500. An illustrated CMD902includes commands ACT and READ following a time delay tRCD; addresses ADDR904include BA, RA (bank Addr, row Addr for the command ACT, and further include BA, BLA, CA (bank Addr, block Addr, column Addr) for the command READ, and data906following a time delay CAS latency after the command READ.

Referring toFIG. 10, there are shown example operations of a memory controller for implementing memory devices with a sub-bank architecture, the memory device having a sub-bank architecture, such as memory device500in accordance with the preferred embodiments. First as indicated in a block1000, a read request is received. The memory controller converts the address of the received read request into bank/sub-block/row/column addresses as indicated in a block1002. The read or write command includes the added sub-block address in accordance with the preferred embodiments.

As indicated in a decision block1004, checking for a sub-block hit is performed. When not a sub-block hit, checking for a page hit is performed as indicated in a decision block1006. When not a page hit, then the sub-block is closed as indicated in a block1008. With a sub-block hit at decision block1004, then checking if the adjacent sub-block is open is performed as indicated in a decision block1010. When the adjacent sub-block is open, then the adjacent sub-block or sub-blocks are closed as indicated in a block1012. When the adjacent block is not open, then the target sub-block is activated as indicated in a block1014. The read command is issued as indicated in a block1016. The operations end as indicated in a block1018.

Referring now toFIG. 11, an article of manufacture or a computer program product1100of the invention is illustrated. The computer program product1100is tangibly embodied on a non-transitory computer readable storage medium that includes a recording medium1102, such as, a floppy disk, a high capacity read only memory in the form of an optically read compact disk or CD-ROM, a tape, or another similar computer program product. Recording medium1102stores program means1104,1106,1108, and1110on the medium1102for carrying out the methods for implementing memory devices with a sub-bank architecture in accordance with the preferred embodiments in the system100ofFIG. 1.

A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means1104,1106,1108, and1110, direct the computer system100, for implementing memory devices with a sub-bank architecture in accordance with the preferred embodiments.