Optoelectronic semiconductor device

An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

BACKGROUND

1. Technical Field

An optoelectronic semiconductor device is disclosed, especially related to a layout of an electrode structure of the optoelectronic semiconductor device.

2. Reference to Related Application

This application claims the right of priority based on TW application Ser. No. 097146075, filed Nov. 26, 2008, entitled “OPTOELECTRONIC SEMICONDUCTOR DEVICE”, and the contents of which are incorporated herein by reference.

3. Description of the Related Art

The current crowding effect refers to an uneven distribution of current density occurred commonly in conventional light emitting devices. It accumulates heat locally in the lighting device and decreases the lighting efficiency. For the worse case, it damages the lighting device.

The layout of the electrode structure of the light emitting device is for the purpose of spreading the current driving into the semiconductor layer more evenly and solving the issue of current crowding. The key factors for consideration are the distance of the p-type electrode and the n-type electrode, and the positions of the pads and the fingers. However, as the chip size and the driving voltage of the light emitting device increases, the current flow to the end side of the finger is influenced by the accumulated resistance and therefore is not spread uniformly.

The layout of the electrode structure of the vertical type chip has the n-type electrode and the p-type electrode positioned in the opposite sides of the chip. But in this design, the epitaxial substrate needs to be removed to expose the first conductivity type semiconductor layer connected to the substrate so the first electrode can be formed on the exposed surface. Besides, a reflecting layer, a second electrode and a permanent substrate are formed on the second conductivity type semiconductor layer of the surface of the epitaxial structure. The process is complicated so it is difficult to maintain the yield and the cost is high.

SUMMARY

An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and a portion of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

With the three-dimensional crossover arrangement, the design of the electrodes of different conductivity types in the light emitting diode (including the bonding pads and the extension electrodes) is more flexible, and its manufacturing process is more stable with low cost.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference is made in detail to the preferred embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1shows a top view of the electrode structure of the optoelectronic semiconductor device in accordance with the first embodiment of the present application. The device includes at least a p-type bonding pad101, a plurality of p-type extension electrodes102, a plurality of n-type contact zones103, a plurality of n-type extension electrodes104and at least an n-type bonding pad105. The p-type extension electrodes102form a plurality of symmetrical closed patterns, and at least a p-type bonding pad101is formed on the p-type extension electrodes102. The n-type contact zone103is disposed in the symmetrical closed pattern mentioned above and electrically connected to the plurality of n-type extension electrodes104. Besides, the p-type extension electrodes102and the n-type extension electrodes104are electrically connected to the p-type bonding pad101and the n-type bonding pad105respectively. In this embodiment, the p-type extension electrodes102and the n-type extension electrodes104is separated by an insulating layer at the three-dimensional crossover106. The material of the electrode structure mentioned above can be metal material such as Cr, Ti, Ni, Pt, Cu, Au, Al, or Ag.

The first embodiment is described hereinafter in accompany with drawingsFIG. 1,FIG. 2AandFIG. 2B. An optoelectronic semiconductor device includes a semiconductor system formed on a substrate201and an electrode structure formed on the semiconductor system. A semiconductor system is referred as a semiconductor device, equipment, product, circuit, or application that can proceed or induce the light energy and electrical energy transfer. Specifically speaking, a semiconductor system includes a light-emitting diode (LED), a laser diode (LD), a solar cell, a liquid crystal display, or an organic light-emitting diode. The phrase “semiconductor system” in the specification does not require that all the sub-systems or units in the system are semiconductor materials. Other non-semiconductor materials such as metal, oxide, insulator and so on can also be optionally integrated in the semiconductor system.

In accordance with the first embodiment in the application, a semiconductor system includes at least a first conductivity type layer202, an active layer203, and a second conductivity type layer204. The first conductivity type layer202and the second conductivity type layer204are two single-layer structures or two multiple layers structure (“multiple layers” means two or more than two layers) having different electrical properties, polarities, dopants for providing electrons or holes respectively. If the first conductivity type layer202and the second conductivity type layer204are composed of the semiconductor materials, and the conductivity type can be any two of p-type, n-type, and i-type. The active layer203disposed between the first conductivity type layer202and the second conductivity type layer204is a region where the light energy and the electrical energy could transfer or could be induced to transfer. The device transferring the electrical energy to the light energy can be a light-emitting diode, a liquid crystal display, or an organic light-emitting diode; the device transferring the light energy to the electrical energy can be a solar cell or an optoelectronic diode.

Taking the light-emitting diode as an example, the light emission spectrum after transformation can be adjusted by changing the physical or chemical arrangement of one layer or more layers in the semiconductor system. The materials commonly used are aluminum gallium indium phosphide (AlGaInP) series material, aluminum gallium indium nitride (AlGaInN) series material, zinc oxide (ZnO) series material and so on. The active layer203can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MWQ). Besides, the wavelength of the emitting light can also be adjusted by changing the number of the pairs of the quantum well.

The substrate201is used for growing or carrying the semiconductor system, and the suitable material includes but is not limited to germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire, silicon carbide (SiC), silicon (Si), lithium aluminum oxide (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), glass, composite material, diamond, CVD diamond, diamond-like carbon (DLC) and so on.

A transition layer (not shown) is optionally formed between the substrate201and the semiconductor system. The transition layer is disposed between two material systems to transit a material system like the substrate to another material system like the semiconductor material system. For the light-emitting diode structure, on one hand, the transition layer can be a layer like the buffer layer to reduce the lattice mismatch between two material systems. On the other hand, the transition layer can also be a single layer, multiple layers, or a structure to combine two materials or two separated structures where the material can be organic, inorganic, metal, semiconductor and so on, and the structure can be a reflective layer, a heat conducting layer, an electrical conducting layer, an ohmic contact layer, an anti-deformation layer, a stress release layer, a stress adjustment layer, a bonding layer, a wavelength converting layer, a mechanical fixing structure and so on.

A contact layer (not shown) can also be optionally formed on the second conductivity layer204. The contact layer is disposed on the side of the second conductivity layer204away from the active layer203. Specifically speaking, the contact layer could be an optical layer, an electrical layer or the combination of the two. An optical layer can change the electromagnetic radiation or the light from or entering the active layer203. The term “change” here means to change at least one optical property of the electromagnetic radiation or the light. The abovementioned property includes but is not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field, and angle of view. An electrical layer can change or be induced to change the value, density, or distribution of at least one of the voltage, resistance, current, or capacitance between any pair of the opposite sides of the contact layer. The composition material of the contact layer includes at least one of oxide, conductive oxide, transparent oxide, oxide with 50% or higher transmittance, metal, relatively transparent metal, metal with 50% or higher transmittance, organic material, inorganic material, fluorescent material, phosphorescent material, ceramic, semiconductor, doped semiconductor, and undoped semiconductor. In certain applications, the material of the contact layer is at least one of indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. If the material is relatively transparent metal, the thickness is about 0.005 μm˜0.6 μm.

The second conductivity layer204and the active layer203are etched to expose a portion of the continuous first conductivity type layer202. An insulating layer205is formed on a specific region of the second conductivity layer204to avoid short when an n-type contact zone208formed in the following process directly contacts with the second conductivity layer204and the active layer203. Afterwards, according to the layout design of the electrode structure, the positions of the n-type contact zone208, a p-type extension electrode206and a p-type bonding pad (not shown) are defined by lithography, and metal material is formed on the defined area mentioned above by evaporation or electroplating to form the n-type contact zone208, the p-type extension electrode206and the p-type bonding pad (not shown).

Next, the insulating layer205covers the surface of the device with high dielectric constant material like inorganic oxide or dielectric organic material such as SiOxSiNxAl2O3TiOx. The n-type contact zone208and the p-type bonding pad (not shown) are exposed by lithography and etching process. Finally, the n-type bonding pad and the n-type extension electrode207are defined by lithography and metal material formed on the defined area mentioned above by evaporation or electroplating to form the n-type bonding pad and the n-type extension electrode207to complete the three-dimensional crossover electrode design of this application.

FIG. 2Aillustrates a cross-sectional view of the crossover (A-A′) of the p-type extension electrode102and the n-type extension electrode104of the optoelectronic semiconductor device in accordance with the first embodiment of the present application. The p-type extension electrode206is formed on the second conductivity type layer204, and an insulating layer205is formed on the p-type extension electrode206and the second conductivity type layer204. Finally, the n-type extension electrode207is formed on the insulating layer205and is electrically insulated from the p-type extension electrode206. The three-dimensional crossover design of the electrode structure is formed accordingly.

FIG. 2Billustrates a cross-sectional view of the n-type contact zone (B-B′) of the optoelectronic semiconductor device in accordance with the first embodiment of the present application. After the insulating layer205is formed to cover the second conductivity type layer204and the active layer203mentioned above, an n-type extension electrode207is formed on the insulating layer205and is electrically insulated from the second conductivity type layer204, and the n-type contact zone is formed with metal material. The metal material of the n-type contact zone208directly contacts with the first conductivity type layer202, and the n-type extension electrode is formed on the active layer203.

FIG. 3andFIG. 4illustrate top views of the layout of the electrode structure of the optoelectronic semiconductor device in accordance with the second and the third embodiments of the present application. The device shown in the drawings includes at least one p-type bonding pad301,401; a plurality of p-type extension electrodes302,402; a plurality of n-type contact zones303,403; a plurality of n-type extension electrodes304,404and at least one n-type bonding pad305,405wherein the p-type extension electrode302,402forms a plurality of symmetrical closed patterns, and the n-type contact zones303,403are formed in the symmetrical closed pattern mentioned above and electrically connected to each other by a plurality of n-type extension electrode304,404. Besides, the p-type extension electrodes302,402and the n-type extension electrodes304,404are electrically connected to the p-type bonding pads301,401and the n-type bonding pads305,405respectively. In this embodiment, the crossover of the p-type extension electrodes302,402and the n-type extension electrodes304,404are separated by the insulating layer to form a three-dimensional design for the electrode structure of this application.

FIG. 5andFIG. 6illustrate another layout of the electrode structure of the optoelectronic semiconductor device of the present application.FIG. 5illustrates a top view of the layout of the electrode structure of the optoelectronic semiconductor device in accordance with the fourth embodiment of the present application. The device shown in the drawing including at least one p-type bonding pad501, a plurality of p-type extension electrodes502, a plurality of n-type extension electrodes503, at least an n-type bonding pad504and a plurality of insulating layers505.

The p-type extension electrode502includes a plurality of perpendicular p-type extension electrodes5021and a plurality of lateral p-type extension electrodes5022to form a plurality of symmetrical closed patterns. A plurality of straight n-type extension electrodes5031and a plurality of lateral n-type extension electrodes5032are formed at the p-type extension electrodes502wherein part of the perpendicular p-type extension electrode5021and the lateral n-type extension electrode5032form the three-dimensional crossover. At least a p-type bonding pad is formed on the crossover of the perpendicular p-type extension electrode5021and the lateral p-type extension electrode5022.

In this embodiment, the perpendicular n-type extension electrodes5031and the lateral n-type extension electrodes5032are formed in a trench506(represented by the line around the n-type extension electrodes in theFIG. 5andFIG. 6) formed by etching the second conductivity type layer and the active layer to expose a portion of the first conductivity type layer so the n-type extension electrodes503are electrically connected to the first conductivity type layer. The detailed process is substantially the same with the first embodiment and can be referred thereto.

After the trench of the lateral n-type extension electrode5032is formed, the insulating layer505is formed on the crossover of the perpendicular p-type extension electrode5021and the lateral n-type extension electrode5032. The perpendicular p-type extension electrode5021is then formed on the insulating layer505to form the three-dimensional crossover for two different conductivity type electrodes.

At least one n-type bonding pad504is formed on the crossover of the perpendicular n-type extension electrode5031and the lateral n-type extension electrode5032. The n-type bonding pad504is disposed on the active layer by forming the insulating layer505on the trench506of the n-type extension electrode503. The n-type bonding pad504is electrically connected to the n-type extension electrode503on the insulating layer through the wire (not shown).

FIG. 6illustrates a top view of the layout of the electrode structure of the optoelectronic semiconductor device in accordance with the fifth embodiment of the present application. The embodiment includes at least one p-type bonding pad601, a plurality of p-type extension electrodes602, a plurality of n-type extension electrodes603, at least one n-type bonding pad604and at least one lateral insulating layer605.

The p-type extension electrode602forms a plurality of symmetrical closed patterns including a plurality of perpendicular p-type extension electrodes6021and a plurality of lateral p-type extension electrodes6022. A plurality of perpendicular n-type extension electrodes6031and a plurality of lateral n-type extension electrodes6032are formed at the p-type extension electrode602wherein a portion of the perpendicular p-type extension electrode6021and the lateral n-type extension electrode6032form the three-dimensional crossover. At least one p-type bonding pad601is formed on the crossover of the p-type extension electrode6021and the lateral p-type extension electrode6022.

In this embodiment, the perpendicular n-type extension electrode6031is formed in a trench606(represented by the line around the n-type extension electrode in theFIG. 5andFIG. 6) by etching the second conductivity type layer and the active layer to expose a portion of the first conductivity type layer so the n-type extension electrodes603are electrically connected to the first conductivity type layer. The detailed process is substantially the same with the first embodiment and can be referred thereto.

After the trench of the perpendicular n-type extension electrode6031is formed, the lateral insulating layer605is formed on the crossover of the perpendicular p-type extension electrode6021and the later formed lateral n-type extension electrode6032. The lateral n-type extension electrode6032is electrically connected to the perpendicular n-type extension electrode6031wherein the lateral n-type extension electrode6032and the perpendicular p-type extension electrode6021are formed on the lateral insulating layer605to form the three-dimensional crossover for two different conductivity type electrodes.

At least one n-type bonding pad604is formed on the crossover of the perpendicular n-type extension electrode6031and the lateral n-type extension electrode6032, and is electrically connected to the lateral n-type extension electrode6032. Instead of forming a trench, the n-type bonding pad604is exposed for wiring. In other embodiment, the n-type bonding pad604can be formed in the trench and electrically connected to the first conductivity layer and other wires directly.

The optoelectronic semiconductor device mentioned above may be mounted with the substrate side down onto a submount via a solder bump or a glue material to form a light-emitting apparatus. Besides, the submount further comprises at least one circuit electrode layout structure electrically connected to the electrode of the light-emitting device via an electrical conductive structure, such as a metal wire. The submount mentioned above can be a lead frame or a mounting substrate to make the circuit design easily and improve the heat dissipation.

Comparing to the prior art, the layout of the electrode structure of the application has more advantages such as: there is no need to keep the p-type extension electrode a certain distance from the n-type extension electrode. In this application, the second conductivity type extension electrode forms a semi-enclosed or closed pattern and the first conductivity type extension electrode is formed in the central region of the closed pattern to contact the surface of the second conductivity type layer by leaps. The layout of the electrode structure of this application is separated into several geometric symmetry subunit (semi-enclosed or closed patterns) and makes the current spread into the light emitting diode uniformly. Therefore, when the chip size of the light emitting diode is extensively increased, the electrode layout can be easily modified by increasing the subunit mentioned above.

Besides, the n-type extension electrode and the n-type contact zone or the n-type bonding pad in this application is designed to form at the opposite sites of the active layer and to have three-dimensional crossover with the p-type extension electrode. There is no need to remove excessive semiconductor layer in comparison with the prior art method. The area loss caused by the design is decreased and the light-emitting efficiency is increased.

Although the drawings and the illustrations above are corresponding to the specific embodiments individually, the element, the practicing method, the designing principle, and the technical theory can be referred, exchanged, incorporated, collocated, coordinated except they are conflicted, incompatible, or hard to be put into practice together.

Although the present application has been explained above, it is not the limitation of the range, the sequence in practice, the material in practice, or the method in practice. Any modification or decoration for present application is not detached from the spirit and the range of such.