METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides a metal oxide semiconductor device and a method for manufacturing the same. The metal oxide semiconductor device includes a semiconductor substrate, a patterned field oxide layer, first JFET implantation regions and second JFET implantation regions. Active regions and gate regions are formed on an upper surface of the semiconductor substrate, each active region is surrounded by two or more of the gate regions, and the gate regions form a grid and some gate regions overlap to form gate intersections. The first JFET implantation regions are formed by implanting ions underneath the gate intersections of the upper surface of the semiconductor substrate. Orthogonal projections of the first JFET implantation regions and the field oxide layer onto the substrate don't overlap. The second JFET implantation regions are formed by implanting ions into the upper surface of the semiconductor substrate and located underneath the gate regions that are not gate intersections.

FIELD OF TECHNOLOGY

The present disclosure relates to a semiconductor device, in particular to a metal oxide semiconductor (MOS) device and method for manufacturing the same for increasing the breakdown voltage.

BACKGROUND

FIG.1andFIG.2show a structure of a conventional planar MOS device.FIG.1is a top view illustrating the cellular structure of the MOS device.FIG.2shows the cross-sectional view of the MOS device. In this case no implantation mask is used for junction-gate field-effect transistor (JFET) implantation in the manufacturing process of the MOS device. The JFET region150and the semiconductor substrate130are of the same dopant type. Meanwhile, the dopant concentration of the JFET region150is greater than that of the semiconductor substrate130.

On the left ofFIG.2is a cross-section of the MOS device passing through the line A-A′ and the gate intersection123. A gate intersection is where two or more gate regions overlap. On the right ofFIG.2is a cross-section of the MOS device passing through the line B′-B and the gate region121. JFET regions150are formed by implanting dopant ions to under gate regions121and122. Gate intersections123have more dopants implanted underneath, so that the JFET regions150under the gate intersections123have longer lengths along the diagonals of the gate intersections123than lengths of JFET regions150under gate regions other than the gate intersections123. When reverse-biased, depletion layers, formed by PN junctions, at two ends of each of the JFET regions150under the gate intersections123are unlikely to get in contact with each other and therefore the device has a lowered breakdown voltage along the diagonals, making the planar MOS device unstable, thereby narrowing the device's operating range.

SUMMARY

The present disclosure provides a metal oxide semiconductor device, comprising a semiconductor substrate, comprising active regions and gate regions disposed on an upper surface of the semiconductor substrate, wherein each of the active regions is surrounded by two or more of the gate regions, wherein the gate regions form a grid, comprising a plurality of gate intersections which are formed from intersecting gate regions; a patterned field oxide layer, wherein the patterned field oxide layer is configured to overlap with one of the plurality of gate intersections; wherein the semiconductor substrate further comprises ion-implanted regions, wherein the ion-implanted regions comprise first JFET implantation regions and second JFET implantation regions; wherein each of the first JFET implantation regions is configured to be underneath one of the plurality of gate intersections, wherein an orthogonal projection of each of the first JFET implantation regions and an orthogonal projection of said patterned field oxide layer onto the semiconductor substrate do not overlap; and wherein each of the second JFET implantation regions is configured to be underneath non-intersecting gate regions.

The present disclosure provides a method for manufacturing a metal oxide semiconductor device, comprising: providing a semiconductor substrate, which is of a first dopant type; forming an oxide layer on an upper surface of the semiconductor substrate, and patterning the oxide layer to form a patterned field oxide layer with a photolithography and a first etching process, wherein the patterned field oxide layer serves as an implantation mask to form a ring shaped implantation region, wherein said ring shaped implantation region covers a cell region, wherein the cell region comprises active regions and gate regions, wherein each of the active regions is surrounded by two or more of the gate regions, wherein the gate regions form a grid, comprising a plurality of gate intersections which are formed from intersecting gate regions; performing a drive-in process on the ring shaped implantation region, wherein the patterned field oxide layer has grown larger after the drive-in process; etching the patterned field oxide layer for a second time, wherein the plurality of gate intersections is partially protected in the etching by the patterned field oxide layer, and wherein the gate regions that are not one of the plurality of gate intersections are not protected in the etching and are exposed by the patterned field oxide layer; wherein the plurality of gate intersections forms shapes which surround areas protected by the patterned field oxide layer; and performing JFET implantation for the gate regions and the plurality of gate intersections, using the patterned field oxide layer as another ion implantation mask. followed by a diffusion process, to form first JFET implantation regions configured to be underneath the plurality of gate intersections, and second JFET implantation regions configured to be underneath non-intersecting gate regions; wherein an orthogonal projection of each of the first JFET implantation regions and an orthogonal projection of said patterned field oxide layer onto the semiconductor substrate do not overlap.

DETAILED DESCRIPTION

The present disclosure is described below by specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present disclosure from the content disclosed by the specification herein. The present disclosure may be embodied or applied in various other specific embodiments, and the details of the present disclosure may also be modified or changed based on different perspectives and applications without departing from the spirit and scope of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments may be combined with each other if no conflict will result.

Embodiments of the present disclosure are illustrated in each accompanying drawing, wherein like reference numerals refer to same elements throughout. For the sake of clarity, the drawings are not necessarily drawn to scale. Additionally, some well-known parts may be omitted. For the sake of simplicity, among drawings showing various step of the method, a certain one may show an intermediate semiconductor structure obtained after several steps performed on the structure shown in its previous drawing.

It should be understood that when a first element is positioned “above”, “over”, or “on” a second element, the first element may either be directly on the top of the second element, or there might be additional elements in between the first and the second elements. Moreover, if the device in the figures is turned upside-down, the first element will be “under”, “below”, or “beneath” the second element

In the disclosure, the term “semiconductor structure” is a collective term for all the intermediate semiconductor structures formed as a result of each step of fabricating a semiconductor device, including all the layers or regions formed as of the corresponding step. The term “laterally” means being substantially parallel to the substrate. The term “vertical” means being substantially perpendicular to the substrate.

FIG.3is a top view of a cellular structure of a metal oxide semiconductor (MOS) device according to an embodiment of the present disclosure. As shown inFIG.3, the cellular structure includes an array of regions in shapes of regular polygons. The portion encircled by dashed lines inFIG.3represents one cell, and the cellular structure may include multiple cells. The cellular structure includes a plurality of active regions110connected in parallel, and a plurality of gate regions121,122distributed around the active regions110. The plurality of active regions110and the plurality of gate regions121,122are disposed on an upper surface of the semiconductor substrate130. Two or more of the gate regions121,122surround one of the active regions110. The plurality of gate regions121,122include a first group of gate regions121extending in a first direction, and a second group of gate regions122extending in a second direction perpendicular to the first direction, and they are connected to form a grid so that active regions110can be isolated from each other. Taking the layout shown inFIG.3as an example, the first group of gate regions121are spaced apart and parallel to each other, the second group of gate regions122are spaced apart and parallel to each other, and each of the first group of gate regions121overlaps with one or more of the second group of gate regions122to form one or more gate intersections123; two adjacent ones of the first group of the gate regions121and two adjacent ones of the second group of gate regions122encloses one cell, which is in the shape of a rectangle. In other embodiments, each cell may be in the shape of a square, a hexagon, etc. The shape of the gate intersections123in the cellular structure is the same as that of the cells; that is, when the cells are rectangular, the gate intersections123are also rectangular, and when the cells are hexagonal, the gate intersections123are also hexagonal.

Referring toFIG.4, on the left of the figure is a cross-sectional view of the MOS device along the line A-A′ inFIG.3, with the line A-A′ representing the diagonals of the gate intersections123; on the right of the figure is a cross-section of the MOS device along the line B-B′ inFIG.3, with line B-B′ perpendicular to the direction in which the first group of gate regions121extend. As shown inFIG.4, the MOS device includes a semiconductor substrate130, and the semiconductor substrate130is of a first dopant type. As shown in theFIGS.3and4, the plurality of gate intersections123and the plurality of gate regions121,122are located on the upper surface of the semiconductor substrate130. Each of the active regions110includes a source region of a second dopant type and a well region of the second dopant type, and the source region and the well region are adjacent to each other. Each gate intersection123and each gate region121are respectively located between two adjacent active regions110; a field oxide layer140is formed over each gate intersection123, and partially covers the corresponding gate intersection123. Using the patterned field oxide layer140as a mask, JFET implantation is performed on the gate intersections123, so that the JFET implantation does not affect portions of the semiconductor substrate130under the field oxide layers140; as a result, first JFET implantation regions151are formed, and are ring-shaped around the field oxide pattern, and a portion of the semiconductor substrate130underneath each field oxide layer140is surrounded by one of the first implantation regions151. Orthogonal projections of the first JFET implantation regions151and the field oxide layers140onto the semiconductor substrate130do not overlap. In each gate intersection123, a gate electrode150basically overlays only some portions of the gate intersection123outside the field oxide layer140. On the contrary, no overlay between the gate regions121,122and the field oxide layer, so that second JFET implantation regions152overlaps to the entire gate regions121,122. Two PN junctions and depletion layers corresponding to the PN junctions are formed between each of the JFET implantation regions151,152and an adjacent region; each two depletion layers are formed on two sides of each JFET implantation region151,152, and are formed in pairs in a substantially symmetrical manner.

As shown inFIG.4, one of the first JFET implantation regions151is formed underneath one of the gate intersections123and surrounds a non-implanted region, and the non-implanted region is located underneath one of the field oxide layers140. Although two isolated cross-sections of each first JFET implantation region151are shown inFIG.4, every first JFET implantation region151as shown inFIG.4is actually of a continuous circular structure. Other structural regions are formed adjacent to each first JFET implantation region151, and PN junctions and depletion layers corresponding to the PN junctions are also formed between the other structural regions and each first JFET implantation region151. As shown in the cross sections ofFIG.4, each first JFET implantation region151can be seen to include two smaller portions arranged in the lateral direction, so that it is easier for depletion regions at two ends of the corresponding gate intersection123to merge, which can increase the breakdown voltage of the device in the A-A′ direction and improve the stability of the device.

As shown inFIGS.4,5and6, each field oxide layer140partially covers a central region of the corresponding gate intersection123, while regions of the gate intersection123not covered by the field oxide layer140substantially surround the field oxide layer140. The field oxide layers140can be polygonal, circular, or of more complex configuration. As shown inFIG.5, the field oxide layers140are substantially squares, and their sides are at an angle of 45 or 135 degrees to the first direction or the second direction. Nevertheless, laterally or vertically extending blocks may be formed on corners of the squares, so that the field oxide layers140have a more complex configuration. The field oxide layers140shown inFIG.5are in the shape of a square or rectangle. The field oxide layers140shown inFIG.6are round.

FIG.7AandFIG.7Bcombined are flowcharts illustrating a method for manufacturing a MOS device according to an embodiment of the present disclosure;FIG.8toFIG.15shows cross-sections of intermediate structures obtained in various steps of the method for the manufacturing the MOS device according to an embodiment of the present disclosure.

S110: As shown inFIG.8andFIG.9, a semiconductor substrate130is first provided, a field oxide layer140is then formed on an upper surface of the semiconductor substrate130, and etched to serve as a first mask, wherein a ring shaped implantation region132is exposed by the first mask and a region predetermined to be a cell region131is covered by the first mask, as shown in step S110. In one embodiment, the field oxide layer140is etched by using a photolithography mask.

S120: Afterwards, Ring implantation and a drive-in process are performed on the ring shaped implantation region132to obtain a completed ring shaped implantation region132, and the field oxide layer140continues to grow after the drive-in process, as shown in step S120.

In one embodiment, the semiconductor substrate130may include an epitaxial layer formed on a base133, which is of the first dopant type, in which case the epitaxial layer and the base133constitute the semiconductor substrate130, that is of the first dopant type.

As shown inFIG.10, the cell region131may include a plurality of active regions110and a plurality of gate regions121,122, wherein each of the active regions110is surrounded by two or more gate regions121,122. The plurality of gate regions121,122include a first group of gate regions121extending in a first direction, and a second group of gate regions122extending in a second direction perpendicular to the first direction, and they are connected to form a gate grid so that active regions110can be isolated from each other. Each of the first group of gate regions121overlaps with one or more of the second group of gate regions122to form one or more gate intersections123.

S130: The field oxide layer140formed in S110is again etched to remove portions over the gate regions121,122and the active regions110, so that the field oxide layer140etched for the second time serves as a second mask, and the gate intersections123are partially covered by the etched field oxide layer140, as shown in step S130. Each field oxide layer140obtained in S130is located around a central position of one of the gate intersections123.

In one embodiment, the field oxide layer140in S110˜120is a unpatterned film layer, which is etched in S130to obtain patterns of isolated smaller portions, which may also be referred to as field oxide layers when describing relationships between the smaller portions and other regions, like the first JFET implantation regions151.

S140: As shown inFIG.10, JFET implantation is performed on the gate regions121,122and the gate intersections123by using the field oxide layer140as a second mask, as shown in step S140.

The above JFET implantation treatment includes using the field oxide layer140as an implantation mask, implanting ions of the first dopant type into the cell region131, after which the ions are diffused to form first JFET implantation regions151located underneath the gate intersections123and second JFET implantation regions152located underneath the gate regions121,122. The dopant concentration of the JFET implantation regions151,152is greater than the dopant concentration of the semiconductor substrate130. By using the patterned field oxide layer140as an implantation mask, JFET implantation is not performed on portions of the semiconductor substrate130underneath the field oxide layers140, so that each of the first JFET implantation regions151surrounds a orthogonal projection orthogonal projection of a corresponding field oxide layer140under a corresponding gate intersection123. That is, orthogonal projections of the first JFET implantation regions151and the second mask (i.e., the patterned field oxide layers after the two etching processes) onto the semiconductor substrate do not overlap

S150: As shown inFIG.11, gate dielectric layers153are formed above the gate regions121,122and the gate intersections123, and gate electrode layers154are formed on the gate dielectric layers153to form gate electrodes150, as shown in step S150.

As shown inFIG.11, in each gate intersection123, other portions of the gate intersection123and the field oxide layer140are substantially covered by the gate electrode150. Portions of the gate electrodes150corresponding to the field oxide layers140protrude upwards. Each gate dielectric layer153can include, but is not limited to, an oxide layer, interlayer dielectric materials, or other insulating materials. Each gate electrode layer154can include, but is not limited to, polysilicon, metal, or other conductive material. In one embodiment, during the process of forming the gate electrode layers154, polysilicon is directly deposited on the semiconductor substrate130, and etched to retain only the polysilicon on the gate dielectric layers153as the gate electrode layers154.

S160: As shown inFIG.12, after forming the gate electrodes150, well implantation based on self-alignment and a drive-in process is performed on the active regions110to form well regions112, which are of the second dopant type, and each two of the well regions112are located on two sides of one of the gate regions121,122, as shown in step S160. When the second dopant type is P, the well regions112are P-body, which are part of the structure of the gate regions121,122.

As shown inFIG.13, ions of the first dopant type (N+, for example) are implanted at a high concentration between the active regions110and the gate regions121,122, and between the active regions110and the gate intersections123using a patterned layer as the mask, and a drive-in diffusion process is then performed, forming source regions111, as shown in step S170.

As shown inFIG.14, a passivation material is deposited on the upper surface of the semiconductor substrate130to form a passivation layer, and the passivation layer is etched to form through holes in upper portions of the well regions112; and ions of the second dopant type (P+, for example) are implanted by using the through holes as a mask at a high concentration to form contact regions160located in and exposed from the well regions112, as shown in step S180.

As shown inFIG.15, after the contact regions160are formed, a front metal layer is deposited over the upper surface of the semiconductor substrate130. The front metal layer is etched to form source electrodes170over the contact regions160, and both the contact regions160and the well regions112are in contact with lower surfaces of the source electrodes170, as shown in step S190. At the same time or afterwards, a back metal layer may also be deposited on a lower surface of the semiconductor substrate130to form a drain electrode180.

In the MOS device, each of the first JFET implantation regions151, formed by using the field oxide layer140as a mask, can be deemed to include two smaller portions arranged in the lateral direction, so that it is easier for depletion regions at two ends of the corresponding gate intersection123to merge, which can increase the breakdown voltage of the device in the A-A′ direction and improve the stability of the device.

Persons skilled in the art should also understand that for clarity of illustration, the elements (such as components, regions, layers, etc.) in each accompanying drawing are not necessarily drawn to scale, and the various elements in the drawings are not necessarily depicted in their actual shapes. Persons skilled in the art should also understand that the shapes depicted are for exemplary purposes. For example, in the above embodiments, regions like the source regions, well regions, and JFET implantation regions are all shown with clear boundaries in the cross sections, which are for illustration purposes only; in actual applications, there may be transition zones between regions that are differently doped, and the corresponding gradients of dopant concentration may be continuous at boundaries between the regions.

The above embodiments merely illustrate the principles and effects of the present disclosure. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with general knowledge in the technical field without departing from the spirit and technical concept disclosed in the present disclosure should still be covered by the scope of the claims of the present disclosure.