Method of fabricating isolated capacitors and structure thereof

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

FIELD OF THE INVENTION

The invention relates to a semiconductor structure and methods of manufacture and, more particularly, to a method of fabricating isolated capacitors and a resulting structure.

BACKGROUND

The performance of the CMOS logic devices has been greatly improved by using SOI (Silicon-On-Insulator) substrate. Yet, further improvement of the SOI logic chip was achieved by integrating DRAM compartments within the logic chip (e.g., Embedded DRAM on SOI). Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. The advantage of DRAM is its structural simplicity; i.e., only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. DRAM cell structures have been successfully scaled for several decades to increasingly smaller dimensions that allow for reducing manufacturing costs and increasing levels of integration within the DRAM cell structures.

While DRAM cell structures have been successfully scaled for several decades, the scaling of DRAM cell structures is not entirely without problems. In particular, such scaling, while physically achievable for both a field effect transistor and a storage capacitor within a dynamic random access memory cell structure, is problematic for the storage capacitor insofar as storage capacitors when aggressively scaled may not have adequate storage capacitance for proper operation of a dynamic random access memory cell structure.

However, it is becoming more and more difficult to maintain enhanced performance at decreased dimensions. Particularly, forming buried plate electrodes became extremely challenging. For example, with deep trench capacitors in SOI, the conventional diffusion doping or implanting process is becoming very difficult through smaller and smaller deep trench openings. That is, as the openings of the deep trench become smaller, it is becoming increasingly more difficult to implant dopants into the opening in order to form one of the plates from the substrate material. Also, during the doping process, unwanted implants are being implanted into the SOI. Additionally, due to the small spacing between the deep trenches, leakage between DT arrays become problematic. This leakage (i.e., lack of isolation between the deep trenches) results in adjacent capacitors turning on and off at the same time. Moreover, it has been found that after the SOI bonding/anneal process, dopants such as, for example, phosphorous, tend to diffuse from an epi layer into the underlying substrate, which may cause isolation issues.

SUMMARY

In a first aspect of the invention, a method comprises simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further comprises lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further comprises filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

In another aspect of the invention, a method comprises forming an insulator layer on a substrate. The method further comprises forming a doped poly layer on the insulator layer. The method further comprises bonding a silicon on insulator (SOI) structure to the doped poly layer. The method further comprises forming a plurality of deep trenches and one or more isolation trenches surrounding an array or group of the plurality of deep trenches into the doped poly layer and SOI structure. The method further comprises forming an insulator layer on sidewalls of the deep trenches and the one or more isolation trenches. The method further comprises forming a conductive metal over the insulator layer.

In yet another aspect of the invention, a structure comprises one or more groups of deep trench capacitors formed in an SOI and n+ doped poly layer. The deep trench capacitors comprise an insulator material between and in direct contact with the n+ doped poly layer and a conductive plate formed in a trench. The structure further comprises one or more deep trench isolation structures formed in the SOI and n+ doped poly layer, which isolate at least one of the one or more groups of deep trench capacitors from another group.

In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of isolated capacitor structures (ISC), which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the ISC. The method comprises generating a functional representation of the structural elements of the ISC.

DETAILED DESCRIPTION

The invention relates to a semiconductor structure and methods of manufacture and, more particularly, to a method of fabricating isolated capacitors and a resulting structure. More specifically, the present invention is directed to a method of fabricating eDRAM on SOI using buried isolation plates. In embodiments, the buried isolation plates are polysilicon plates. Advantageously, the buried isolation plates provide an isolation between each array or grouping of capacitors, while eliminating leakage between n-bands. The present invention also eliminates unwanted implants in the SOI, as well as improves scaling capabilities over conventional methodologies. For example, by using the present invention, it is possible to scale the device, without concern for implanting through small deep trench openings.

FIG. 1shows a starting structure in accordance with the present invention. The starting structure includes, for example, a donor substrate10having an oxide layer12. In embodiments, the donor substrate10is silicon (SOI). The oxide12can be deposited using a thermal oxidation process known to those of skill in the art. The oxide12can have a thickness of about 150 nm; although other dimensions are also contemplated by the present invention.

FIG. 2shows an ion implantation process. For example, the ion implantation process is a H+ ion implantation process that forms layer14. The structures ofFIGS. 1and2are conventional structures, well known to those of skill in the art and, as such, further explanation is not required herein.

FIG. 3shows another structure and processing steps in accordance with the present invention. InFIG. 3, an insulator layer18is deposited on a substrate16. The insulator layer18can have a thickness of about 1000 Å; although other dimensions are also contemplated by the present invention. In embodiments, the insulator layer18may be, for example, an oxide, nitride, hafnium oxide, high-k material or other dielectric material. In embodiments, the insulator layer18acts as a diffusion barrier layer to prevent dopants from diffusing into the underlying layer. A doped poly layer20is deposited on the insulator layer18. In embodiments, the doped poly layer20is an N+ poly layer, which can be deposited using a conventional chemical vapor deposition process. The doped poly layer20is about 4 microns thick. This thickness advantageously provides enough material to form a deep trench, while ensuring that the doped poly layer20can act as a plate of a capacitor.

The use of the doped poly layer20eliminates the need for doping a trench structure, as in conventional fabrication processes. Also, by using the doped poly layer20, it is easy to scale the structure to smaller nodes, since there is no further processing requirements for doping within a deep trench structure. Advantageously, the doped poly layer20also prevents unwanted implants in the SOI layer10.

InFIG. 4, the structures ofFIGS. 2 and 3are bonded together using conventional bonding techniques. For example, the structure ofFIG. 2can be flipped over and bonded to the structure ofFIG. 3using, for example, adhesion bonding techniques. Accordingly, after the doped poly layer20is formed, it can be bonded directly to the oxide layer12. InFIG. 5, the donor substrate10is split using conventional splitting processes to form a SOI layer10.

InFIG. 6, a photoresist mask22is placed over the SOI layer10using conventional processes. For example, the photoresist mask22may be deposited by spin-coating over pad films (oxide/nitride) deposited on the SOI layer10using CVD processes. In embodiments, the photoresist mask22is then patterned using conventional lithographic processes. For example, the photoresist mask22can be exposed to light to open holes therein. The holes will correspond with trenches formed within the structure.

InFIG. 7a, the structure undergoes an etching process to simultaneously form deep trenches24aand24b. In embodiments, the deep trenches24asurround the deep trenches24b, thereby isolating the deep trenches24b. Advantageously, the deep trenches24aare used to form buried isolation plates (or moats) which provide an isolation structure between each array or grouping of capacitors, while eliminating leakage between the arrays. In this way, the deep trenches24bcan be formed as isolation plates for a capacitor structure such as, for example, eDRAM. The deep trenches24ashould be formed extending to the insulator layer18to provide an adequate electrical isolation. In embodiments, the deep trenches24bcan be formed within the Poly layer (FIG. 7b) or extended to the insulator layer18for maximum capacitance. Also, in embodiments, as the deep trenches24a,24bare formed simultaneously, the deep trenches24a,24bcan be etched to a same depth.

InFIG. 8, an insulator material26is provided within the deep trenches24a,24b. More specifically, the deep trenches24a,24bare simultaneously lined with the insulator material26, which includes sidewalls and a bottom thereof. In embodiments, the insulator material26can be a high-k dielectric, nitride or oxide, amongst other types of known insulator materials used for forming capacitors. In embodiments, the oxide, for example, can be thermally grown. In embodiments, the insulator material26is about 100 Å; although other dimensions are also contemplated by the present invention. The thickness of the insulator material26should not pinch off the trenches24a,24b.

InFIG. 9, the trenches24a,24bare simultaneously filled with a conductive material28using conventional deposition processes, for example. In embodiments, the conductive material is a poly silicon layer28, which acts as a conductive plate to form trench capacitors24b1. The insulator material26is between and in direct contact with the poly silicon layer28and doped poly layer20. In embodiments, any excess conductive material28on the surface of the SOI layer10may be cleaned using conventional etchants or planarization processes. The trench capacitors24b1remain surrounded by isolation plates24a1, which act as an isolation moat.

FIG. 10shows a top view of the structure ofFIG. 9. As shown inFIG. 10, the isolation plates24a1surround and isolate the trench capacitors24b1. In embodiments, the isolation plates24a1can be formed to surround and isolate any group or array of trench capacitors24b1. In embodiments, the trench capacitors24b1are electrically connected to transistors30.

Design process910employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure920together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure990.