Clock generation circuit and semiconductor memory device employing the same

A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2011-0140277, filed on Dec. 22, 2011, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a clock generation circuit for generating an internal clock signal and a semiconductor memory device employing the clock generation circuit.

2. Description of the Related Art

Generally, semiconductor memory devices including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) device receives an external clock signal and generates an internal clock signal, and performs diverse operations based on the generated internal clock signal. Therefore, the semiconductor memory devices may include an internal clock generation circuit for generating an internal clock signal.

Semiconductor memory devices are demanded to operate faster and faster, and this causes new phenomena such as electro-magnetic interference. The electro-magnetic interference usually occurs when a highly integrated circuit operates at a fast speed, and the electro-magnetic interference causes malfunction of a circuit. The Federal Communications Commission (FCC) provides restriction on the occurrence of the electro-magnetic interference, and semiconductor memory devices are designed in conformity with the recommended value prescribed by the FCC.

The electro-magnetic interference occurs as the length of an internal line becomes as short as the wavelength of an internal clock signal. The short internal line functions as an antenna and increases the radiation of electro-magnetic wave, eventually causing electro-magnetic interference. As semiconductor memory devices operate faster, while occupying smaller areas, the electro-magnetic interference may become worse and the circuit malfunction may be serious. Therefore, it may be desirable to develop a technology for getting rid of, or alleviating the electro-magnetic interference.

SUMMARY

An exemplary embodiment of the present invention is directed to a semiconductor memory device that modulates an internal clock signal based on an operation frequency and modulates output data by using the modulated internal clock signal.

In accordance with an exemplary embodiment of the present invention, a semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock signal by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.

In accordance with another exemplary embodiment of the present invention, a clock generation circuit includes a control voltage generation circuit configured to generate a control voltage changing in response to a profile selection signal, and a voltage controlled delay line configured to generate an internal clock signal by delaying a reference clock signal by a time corresponding to the control voltage.

The control voltage may have a voltage level changing in response to the profile selection signal.

The semiconductor memory device in accordance with an exemplary embodiment of the present invention may decrease electro-magnetic interference both inside and outside of the semiconductor memory device by modulating an internal clock signal based on an operation frequency and modulating output data by using the modulated internal clock signal.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating a semiconductor memory device in accordance with an exemplary embodiment of the present invention.

Referring toFIG. 1, the semiconductor memory device includes an internal clock generation circuit110, a voltage controlled delay line120, a control voltage generation circuit130, a selection output circuit140, and a data output circuit150.

The internal clock generation circuit110receives an external clock signal CLK_EXT and generates a first internal clock signal CLK_INN1for the synchronization in outputting a data. The internal clock generation circuit110may be a Delay Locked Loop (DLL) or a Phase Locked Loop (PLL). The first internal clock signal CLK_INN1has a fixed frequency. The internal clock generation circuit110generate the first internal clock signal CLK_INN1by compensating the external clock signal CLK_EXT for the transfer delay thereof in the semiconductor memory device.

The voltage controlled delay line120generates a second internal clock signal CLK_INN2by reflecting a voltage level of a control voltage V_CTR into the first internal clock signal CLK_INN1. The first internal clock signal CLK_INN1is delayed by a time corresponding to the voltage level of the control voltage V_CTR and the delayed first internal clock signal is outputted as the second internal clock signal CLK_INN2. The voltage level of the control voltage V_CTR is varied according to the time. The second internal clock signal CLK_INN2is generated as a clock signal corresponding to a voltage level profile (profile) of the control voltage V_CTR, and this signifies that the second internal clock signal CLK_INN2does not have a fixed frequency but a frequency corresponding to the voltage level of the control voltage V_CTR, which is described below in detail.

The control voltage generation circuit130generates the control voltage V_CTR having the voltage level profile determined by a profile selection signal SEL_PF. The profile of a signal may mean the waveform of the signal having a particular shape. The voltage level of control voltage V_CTR may change corresponding to the profile thereof. Meanwhile, the control voltage V_CTR according to the exemplary embodiment of the present invention may have a voltage level of various profiles, but for the sake of convenience in description, a chopping waveform of the control voltage V_CTR is described as an example. In short, the control voltage V_CTR has the voltage level profile corresponding to chopping wave.

The selection output circuit140selects one of the first internal clock signal CLK_INN1and the second internal clock signal CLK_INN2in response to a path selection signal SEL_OUT and outputs the selected signal as a synchronization clock signal CLK_SYN. The path selection signal SEL_OUT may be determined based on an operation frequency of the semiconductor memory device. In this case, the selection output circuit140may output the first internal clock signal CLK_INN1as the synchronization clock signal CLK_SYN when a semiconductor memory device operates at a low frequency, and the selection output circuit140may output the second internal clock signal CLK_INN2as the synchronization clock signal CLK_SYN when a semiconductor memory device operates at a high frequency.

The data output circuit150synchronizes an internal data DAT_IN with the synchronization clock signal CLK_SYN and outputs an external data DAT_OUT. In other words, the data output circuit150synchronizes the internal data DAT_IN with the first internal clock signal CLK_INN1in a semiconductor memory device operating at a low frequency and outputs the external data DAT_OUT, and the data output circuit150synchronizes the internal data DAT_IN with the second internal clock signal CLK_INN2in a semiconductor memory device operating at a high frequency and outputs the external data DAT_OUT.

Meanwhile, the voltage controlled delay line120consumes relatively much power. Thus, it is desirable to disable the voltage controlled delay line120for the duration that the second internal clock signal CLK_INN2is not used. Another control signal may be used for this kind of control but the path selection signal SEL_OUT may be used for such control.

According to the exemplary embodiment of the present invention, when the semiconductor memory device operates at a low frequency, the internal data DAT_IN is synchronized with the first internal clock signal CLK_INN1having a fixed frequency and the external data DAT_OUT is outputted. When the semiconductor memory device operates at a high frequency, the internal data DAT_IN is synchronized with the second internal clock signal CLK_INN2having a frequency corresponding to the profile and the external data DAT_OUT is outputted.

Meanwhile, as described above, the semiconductor memory device operating at a high frequency synchronizes the internal data DAT_IN with the second internal clock signal CLK_INN2having a frequency corresponding to the profile and outputs the external data DAT_OUT. In short, the external data DAT_OUT in accordance with the exemplary embodiment of the present invention is outputted at the frequency corresponding to the profile, and when the external data DAT_OUT is inputted into another circuit, the electro-magnetic interference may not occur.

FIG. 2is a circuit diagram illustrating a control voltage generation circuit130shown inFIG. 1. Herein, the control voltage generation circuit130generates a chopping wave.

Referring toFIG. 2, the control voltage generation circuit130includes a feedback unit210, a variable resistance unit220, and an output unit230.

The feedback unit210receives a feedback voltage V_FD. The feedback unit210compares the feedback voltage V_FD with a reference voltage VDD/2 and outputs a comparison result. The variable resistance unit220varies a resistance value in response to first to third profile selection signals SEL_PF1<1:3>, SEL_PF2<1:3> and SEL_PF3<1:3>. The output unit230outputs the control voltage V_CTR based on the resistance value of the variable resistance unit220. The output unit230compares an output voltage of the variable resistance unit220with the reference voltage VDD/2 and outputs the result as the control voltage V_CTR.

The resistance value of the variable resistance unit220is determined by the first to third profile selection signals SEL_PF1<1:3>, SEL_PF2<1:3> and SEL_PF3<1:3>. Therefore, the control voltage V_CTR generated based on the resistance value of the variable resistance unit220has a voltage level corresponding to the profile as well.

FIG. 3is a waveform diagram illustrating an operation waveform of the control voltage generation circuit130shown inFIG. 2.

Hereinafter, the operation of the control voltage generation circuit130is described with reference toFIGS. 2 and 3.

In the first place, when the voltage level of a ‘V_ND’ node drops from ‘VDD’ to ‘0’, the output unit230of the control voltage generation circuit130performs an integral calculation on a control voltage V_CTR terminal based on a time constant determined by a resistance value of a first variable resistor221and a capacitance value C. Therefore, the voltage level of the control voltage V_CTR is increased linearly. Conversely, when the voltage level of the ‘V_ND’ node surges from ‘0’ to ‘VDD’, the voltage level of the control voltage V_CTR is decreased linearly.

As illustrated inFIG. 3, the control voltage V_CTR has a waveform of chopping wave swinging between the maximum voltage level UTP and the minimum voltage level LIP based on the reference voltage VDD/2. Here, the maximum voltage level UTP and the minimum voltage level LTP may be controlled by varying the resistance values of first to third variable resistors221,222, and223shown inFIG. 2.

That is, the first to third profile selection signals SEL_PF1<1:3>, SEL_PF2<1:3> and SEL_PF3<1:3> are determined according to the profile. For example, the profile of the control voltage V_CTR is controlled by adjusting the first to third profile selection signals SEL_PF1<1:3>, SEL_PF2<1:3> and SEL_PF3<1:3> in order to change an amplitude of the waveform and a frequency of the waveform.

FIG. 4is a circuit diagram illustrating the first to third variable resistors221,222, and223shown inFIG. 2. Since the first to third variable resistors221,222, and223have a similar structure, the first variable resistor221is representatively described here for the sake of convenience in description.

Referring toFIG. 4, the first variable resistor221includes first to third resistors410,420, and430whose resistance values are decided in response to the first profile selection signal SEL_PF1<1:3>.

Each of the first to third resistors410,420, and430includes a transfer gate that is turned on/off by receiving the first profile selection signal SEL_PF1<1:3> and a resistor having a set resistance value. The total resistance value of the first variable resistor221is controlled to diverse levels by the transfer gate that is turned on/off based on the first profile selection signal SEL_PF1<1:3>.

Therefore, the semiconductor memory device in accordance with the exemplary embodiment of the present invention may vary the maximum voltage level UTP and the minimum voltage level LTP of the chopping wave by controlling the resistance values of the first to third variable resistors221,222, and223.

FIG. 5is a circuit diagram illustrating the voltage controlled delay line120shown inFIG. 1.

Referring toFIG. 5, the voltage controlled delay line120includes a signal transfer line510and a delay control unit520. The signal transfer line510receives and transfers the first internal clock signal CLK_INN1and outputs the second internal clock signal CLK_INN2. The delay control unit520controls a delay amount that is reflected into the signal transfer line510in response to the control voltage V_CTR according to the profile.

The signal transfer line510includes inverters coupled in series, and the delay control unit520includes an MOS transistor coupled between the signal transfer line510and a ground voltage VSS terminal to control the capacitance based on the control voltage V_CTR.

FIG. 6is a waveform diagram illustrating a relationship between an input signal and an output signal of a voltage controlled delay line120shown inFIG. 5.

As shown inFIG. 6, when the voltage level of the control voltage V_CTR becomes large, a phase difference between the first internal clock signal CLK_INN1and the second internal clock signal CLK_INN2becomes large. That is, delay amount of the voltage controlled delay line120is increased.

When the voltage level of the control voltage V_CTR is the highest level, the phase difference between the first internal clock signal CLK_INN1and the second internal clock signal CLK_INN2has the peak value.

Also, when the voltage level of the control voltage V_CTR becomes small, the phase difference between the first internal clock signal CLK_INN1and the second internal clock signal CLK_INN2becomes small. That is, the delay amount of the voltage controlled delay line120is decreased.

As described above, the semiconductor memory device in accordance with the exemplary embodiment of the present invention may generate an internal clock signal having a frequency corresponding to the profile and output data by using the internal clock signal. Therefore, the internal clock signal and the data synchronized with the internal clock signal come to have a frequency corresponding to the profile instead of a fixed frequency, and the electro-magnetic interference may be reduced both inside and outside of the semiconductor memory device.

According to an exemplary embodiment of the present invention, a semiconductor memory device may prevent malfunction from being caused by electro-magnetic interference by modulating an internal clock signal of the semiconductor memory device.

Moreover, the logic gates and transistors illustrated in the embodiment of the present invention described above may be realized to have different positions and types depending on the polarity of an input signal.