Semiconductor memory device and method of fabricating the same

A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

CROSS REFERENCE TO A RELATED APPLICATION

This application is based upon and claims benefit of priority from the prior Japanese Patent Application No. 2000-284710, filed on Sep. 20, 2000; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory having ferroelectric capacitors. Particularly, this invention relates to non-volatile semiconductor memories having ferroelectric capacitors in high density and methods of fabricating such non-volatile semiconductor memories.

2. Discussion of the Background

A memory which includes series connected memory cells each having a transistor with a source terminal and a drain terminal and a ferroelectric capacitor in between the two terminals (hereinafter named “Series connected TC unit type ferroelectric RAM”) have been developed for highly reliable non-volatile semiconductor memories with low power consumption and high density.

Such non-volatile semiconductor memories are described inFIG. 34. The feature of this type of memory is a memory cell including one transistor and one capacitor, and a plurality of memory cells are connected in series. Namely, a lower electrode of a capacitor of the memory cell is connected to one of the source-drain regions formed adjacent to a gate, and an upper electrode of a capacitor of the memory cell is connected to the other of the source-drain regions.

In this structure, one block of memory cells usually includes eight bits unit cells or 16 bits unit cells. Each block is electrically disconnected in consideration of an increase of the capacitance of bit lines or resistance of performing a switching operation on switching transistors. One block of memory cells is usually disconnected by block selecting transistors. Further, it is necessary to arrange a plate line which drives a capacitor electrode in an opposite direction of a capacitor connected to the bit lines on the opposite direction in one block. Such a feature is disclosed in the “JSSCC, pp 787–792, May, 1998, D. Takashima et al.” and U.S. Pat. No. 5,903,492, the entire contents of these references being incorporated herein by reference.

The conventional semiconductor device having the ferroelectric capacitors in the “Series connected TC unit type ferroelectric RAM” is described with respect toFIGS. 35–40. InFIG. 35, an upper side of the conventional semiconductor device of the block selector portion is shown. In this drawing, there are two block selectors and two memory cell blocks on regions arranged on two parallel lines.FIG. 36illustrates a sectional drawing as the line “S-T” ofFIG. 35.

A block selecting transistor includes a first gate100, a first impurity-diffused region101, and a second impurity-diffused region102formed on a semiconductor substrate103. A first bit line contact wire104is connected to the first impurity-diffused region101and a first metal wire contact105is connected to the first bit line contact wire104. A second bit line contact wire106is connected to the first metal wire contact105, and a bit line107is connected to the second bit line contact wire106.

Further, a first cell transistor includes the second impurity-diffused region102, a second gate108and a third impurity-diffused region109formed on the semiconductor substrate103and adjoined to the block selecting transistor.

In addition, a first capacitor includes a first lower electrode110, a first ferroelectric layer112and a first upper electrode113formed over the second-impurity diffused region102and the second gate108. The first lower electrode110is connected to the second-impurity diffused region102by a polysilicon plug114.

A contact plug115is connected to the third impurity-diffused region109. A first metal wiring116is connected to the contact plug115, and a first metal contact117is formed and connected between the first upper electrode113and the first metal wiring116.

Note a first memory cell includes the first cell transistor and the first capacitor. A second cell transistor includes the third impurity-diffused region109, a third gate118and a fourth impurity-diffused region119. A second capacitor includes a second lower electrode450formed over the third gate118and the fourth impurity-diffused region119. The second ferroelectric layer120is formed on the second lower electrode450, and a second upper electrode121is formed on the second ferroelectric layer120. The second lower electrode450is connected to the fourth impurity-diffused region119by a second polysilicon plug122. Further, a second metal contact123is formed and connected between the second upper electrode121and the first metal wiring116.

Note a second memory cell includes the second cell transistor and the second capacitor. In addition, as shown, an isolation region124is formed on the semiconductor substrate103adjacent to the first impurity-diffused region101.

Because of a micro loading effect, the cross sectional shape of the first upper electrode113may be damaged or changed in comparison with the second upper electrode121. In more detail, the micro loading effect is caused by the difference of the distance between upper electrodes. Particularly, the length between the first upper electrode and another upper electrode is longer than the length between the first upper electrode and the second upper electrode.

In the memory cell, there are cyclical patterns of each memory capacitor, so there is the same length between each upper electrode in the memory cell area in each block. In a similar way, the lower electrodes are easily affected by the micro loading effect and the sectional shape thereof is easily varied in a neighbor of the block selecting transistor.

The micro loading effect is a significant physical phenomenon for the 0.3 micrometer scale. This effect is caused by a resist shape shrink because of over-etching of the resist at the specific point of an inperiodically portion, which is a different scale from the other portion.

Namely, while the etching step is performed, the etching speed of the non-periodical portion of the upper electrode is varied from the other upper electrode of the periodically portion. Thus, the edge portion of the resist for the upper electrode of the inperiodically portion may be varied from a predetermined shape. Further, in the end portion of the memory block, there is a relatively wide opening of the resist for the upper electrode. Therefore, the desired shape of resist of the portion in the end portion of the memory block is hardly acquired, in comparison with the other portion of the memory block, which have memory cells at even intervals.

Further, two memory blocks are facing each other by positioning two block selecting transistors between them. At the end portion of the memory blocks, the distance between upper electrodes in the end portions in each neighboring memory block is equal to the length of the two block selecting transistors and is 1.5 times the distance between two upper electrodes in a normal capacitor portion of the memory block. Therefore, the upper electrode of the end portion is reduced 70–90 percent compared to other normal upper electrodes.

In more detail, the step of forming a conventional upper electrode is shown inFIGS. 40(A) and 40(B). InFIG. 40(A), an overview of the resist pattern as the desired shape disposed on the upper electrode is shown. As shown, two resists190,191facing a block selecting transistor are largely isolated a length of “L” greater than the interval length “M” of other resists192,193.

InFIG. 40(B), the cross sectional view on the line of “Y-Z” of theFIG. 40(A)is shown. In this figure, an upper electrode material196is provided on the ferroelectric layer195. Also shown are the resists190,191,192,193for forming the upper electrode on the upper electrode material196. Further, the broken line portions show the over etched portions of the resists for forming the upper electrodes. Note if there are even intervals between the upper electrodes, such broken line portions may become portions of the resists for forming the upper electrodes.

After forming the upper electrodes, the ferroelectric layers and lower layers are formed in sequence. Because of this manufacturing sequence, the sizes of the upper electrodes are relatively smaller than those of the ferroelectric layers or lower electrodes. Namely, a redundant area for etching the ferroelectric layers or lower electrodes is needed, and thus positioning margins on the ferroelectric layers uncovered by the upper electrodes are provided. In addition, the sizes of the upper electrodes are formed smaller than those of the ferroelectric layers for preparing the redundant area without the upper electrode on the ferroelectric layers.

In addition, as discussed above,FIG. 36illustrates a cross section of the line “S-T” inFIG. 35.FIG. 37illustrates a memory block adjacent to the memory block inFIG. 36including a block selecting transistor and memory cells of the cross sectional view of the line “U-V” and its extension inFIG. 35.

As shown inFIG. 37, a second block selecting transistor includes a fourth gate130, a fifth impurity-diffused region131, and a sixth impurity-diffused region132formed on the semiconductor substrate103. Further, a third bit line contact wire133is connected to the fifth impurity-diffused region131, and a second metal wire contact134is connected to the third bit line contact wire133. A fourth bit line contact wire135is connected to the second metal wire contact134, and a second bit line136is connected to the fourth bit line contact wire135.

In addition, an isolation layer137is formed on the semiconductor substrate103and is adjacent to the sixth impurity-diffused region132. A passing word line is formed on the isolation layer137, and in which the passing word line is the first gate100of the block selecting transistor as shown inFIG. 36.

Also, a third cell transistor includes a seventh impurity-diffused region138, a second gate108and an eighth impurity-diffused region139formed on the semiconductor substrate103, and the seventh impurity-diffused region138is adjoined to the isolation layer137.

A third capacitor includes a third lower electrode140, a third ferroelectric layer141and a third upper electrode142formed over the eighth impurity-diffused region139and the second gate108. The third lower electrode140is connected to the eighth impurity diffused region139by a third polysilicon plug143.

In addition, a second contact plug144is connected to the seventh impurity-diffused region138, and a second metal wiring145is connected to the second contact plug144. A third metal contact146is also formed between the third upper electrode142and the second metal wiring145and is connected to them.

Note a fourth cell transistor includes the eighth impurity-diffused region139, the third gate118and a ninth impurity-diffused region147. Further, the third lower electrode140and the third ferroelectric layer141are formed over the third gate118and the eighth impurity diffused region139. A fourth capacitor includes the third lower electrode140, the third ferroelectric layer141, and a fourth upper electrode148formed over the third gate118.

Note a fourth memory cell includes a fourth cell transistor and a fourth capacitor.

The fourth upper electrode148is formed on the third ferroelectric layer141and over the third gate118. Also, a fourth metal contact149is formed on the fourth upper electrode148, and a third metal wiring150is formed on the fourth metal contact149. A third contact plug151is formed on the sixth impurity diffused region132and is connected to the second metal wiring145. Further, as described above, the third memory cell placed in the end portion of the memory block is connected to the second block selecting transistor.

In this structure shown inFIG. 37, the connection between the sixth impurity-diffused region132and the seventh impurity-diffused region138with the isolation layer137therebetween includes a second metal wiring145in the same level as the metal layer between the upper electrode and the impurity-diffused region, so another word line such as a multilevel word line has to be formed by using other layers of the second metal wiring145or the second bit line136formed on the second metal wiring145. It is inconvenient to use three layers for connecting over the isolation layer, bit line and multilevel word line. That is, if more layers are used, the manufacturing process is becomes more complicated.

By using a Capacitor On Plug (COP) type structure, the area size is reduced in half compared to the offset type. However, the area of the block selecting transistor is increased. In addition, the connection between the sixth impurity-diffusion region132and the seventh impurity diffusion region138with the second metal wiring145may cause the area of the block selecting transistor to be determined by the density of the second metal wiring145.

Thus, the memory cell area is mainly determined and increased by the distance between the second contact plug144and the third metal contact146, the distance between the second contact plug144and the forth metal contact149, or the distance between the second metal wiring145and the third metal wiring150. In contrast, the distance between the second contact plug144and the second gate108, or the distance between the second gate108and the far end point of the seventh impurity-diffused region138does not significantly affect the area of the memory cell.

Further,FIG. 38shows an overview of the portion of the plate line area of two memory blocks andFIG. 39shows a cross sectional view of the line “W-X” inFIG. 38. As shown inFIG. 39, the memory block includes a plurality of memory cells, and a fifth cell transistor on an end portion of the memory block includes a tenth impurity-diffused region160, a fifth gate161, and an eleventh impurity-diffused region162formed on the semiconductor substrate103.

Further, a sixth cell transistor placed in the second end portion of the memory block includes the eleventh impurity-diffused region162, a sixth gate163, and a twelfth impurity-diffused region164on the semiconductor substrate103. Also, a seventh cell transistor placed in a third end portion of the memory block includes the twelfth impurity-diffused region164, a seventh gate165and a thirteenth impurity-diffused region166.

In addition, a fifth metal contact167is connected to the tenth impurity-diffused region160, and is also connected to a first plate line168arranged over the tenth impurity-diffused region160. A second plate line169connected to the other memory block is arranged over the eleventh impurity-diffused region162and has the same position as the first plate line168in the vertical direction.

A fifth capacitor includes a fourth lower electrode170, a fourth ferroelectric layer171and a fifth upper electrode172formed over the tenth impurity-diffused region160. A sixth metal contact173is formed between the first plate line168and the fifth upper electrode172. A fifth memory cell includes the fifth cell transistor and the fifth capacitor.

A sixth capacitor includes a fifth lower electrode174formed over the eleventh impurity-diffused region162and the sixth gate163, a fifth ferroelectric layer175formed on the fifth lower electrode174, and a sixth upper electrode176formed on the fifth ferroelectric layer175and over the sixth gate163. The fifth lower electrode174is connected to the eleventh impurity-diffused region162by a fourth polysilicon plug177.

A fifth metal contact178is connected to the twelfth impurity-diffused region164, and a fourth metal wiring179is connected to the seventh metal contact178. An eighth metal contact180is formed and connected between the sixth upper electrode176and the fourth metal wiring179.

Note a sixth memory cell includes the sixth cell transistor and the sixth capacitor.

A seventh capacitor includes a sixth lower electrode181formed over the seventh gate165and the thirteenth impurity-diffused region166, a sixth ferroelectric layer182formed on the sixth lower electrode181, and a seventh upper electrode183formed on the sixth ferroelectric layer182and over the seventh gate165. The sixth lower electrode181is connected to the thirteenth impurity-diffused region166by a fifth polysilicon plug184, and a ninth metal contact185is formed and connected between the seventh upper electrode183and the fourth metal wiring179.

A seventh memory cell includes a seventh cell transistor and a seventh capacitor.

In this structure, the distance “L” between the fifth upper electrode172and the sixth upper electrode176is larger than the distance “M” between the sixth upper electrode176and the seventh upper electrode183. This difference is caused by the fifth upper electrode172being offset from the fifth gate161in a horizontal direction. The distance “M” is same as the distance between other memory capacitors respectively placed in an adjacent location in the same memory block.

Because of the micro loading effect, the fifth upper electrode172is formed smaller in size compared with the sixth upper electrode176, the seventh upper electrode183and other upper electrodes in the same memory block. Because of the different size of the fifth upper electrode172, the fifth capacitor may have deteriorated characteristics compared to other memory capacitors.

Further, a block selecting transistor in the block selecting section is provided in the end portion of the memory cell block. The capacitors are provided in an even interval in the memory cell block, except in the end portion of the memory cell block (where a capacitor is not provided). Therefore, in the end portion of the memory cell block, the periodicity of the memory cells is not maintained, and thus the distance between the capacitors is larger than that of capacitors in a normal area because of the length of the block selecting transistor.

Further, if the periodicity of the capacitors is not maintained, the characteristics of the capacitor in the end portions of the memory block may deteriorate. This deterioration is caused by a change of resist dimension for the change of the cross sectional shape of the upper electrode or lower electrode, or the increase of the distance between the capacitors by a micro loading effect during the fabricating process.

In addition, in the end portion of memory block which has relatively large opening area of resist, the amount of etching is larger than the amount of etching in other portions of memory cells.

Further, in the memory cell neighboring the plate line, the periodicity of the memory cell is not maintained. Therefore, the characteristic of the memory in the memory cell neighboring the plate line may also be damaged. In addition, a high density of memory cells may be reduced by using metal wiring for connecting the impurity-diffused regions.

The above deterioration of the memory capacitor adjacent to the block selecting transistor or plate line does not meet the demands for a more integrated and reliable semiconductor memory. Further, the above scale increase of memory cell occurs from using the first metal contact wire between the impurity-diffused regions with an isolation region between them and does not meet the demands for a more integrated and reliable semiconductor memory.

SUMMARY OF THE INVENTION

The present invention provides a novel semiconductor memory device including a memory cell block with a plurality of transistors formed in series on a semiconductor substrate. The memory transistors have first and second impurity-diffused regions and gates respectively formed therebetween, a plurality of memory cells each having a lower electrode connected to the first impurity-diffused region, a ferroelectric film formed on the lower electrode, and a first upper electrode formed on the ferroelectric film and being connected to the second impurity-diffused region. Also included is a block selecting transistor formed on the semiconductor substrate and being connected to one end of the memory cell block. A second upper electrode is also formed adjoined to the block selecting transistor and is disconnected from the first upper electrode of the memory cell. The present invention also relates to a method of fabricating the novel semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the present invention will now be described with reference to the accompanying drawings, in which the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. Note also that the drawings are not drawn to scale and in particular that the layer thickness are arbitrarily drawn for facilitating the reading of the drawings.

An object of the present invention is to solve the above-noted and other problems. Another object of the invention is to provide high-density non-volatile semiconductor memories and a method of manufacturing such memories.

The first embodiment according to the present invention will now be described with reference toFIGS. 1 to 7and34. In more detail,FIG. 1is a cross sectional view of the line “A-B” inFIG. 2of a semiconductor memory having ferroelectric capacitors, andFIG. 2is an overview of the semiconductor memory shown inFIG. 1. Further,FIG. 3is an over view of the right portion of the semiconductor memory shown inFIG. 2, andFIG. 4is a sectional view of the line “AR-BR” inFIG. 3.

Further, each element shown inFIG. 1corresponds to the position of each element in the lateral direction inFIG. 2, and each element shown inFIG. 4corresponds to the position of each element in the lateral direction inFIG. 3. Note the circuit of this embodiment is also illustrated using the circuit diagram shown inFIG. 34.

For example, as shown inFIG. 34, several memory blocks1are arranged between a pair of bit lines BL, BLB, a first pair of plate lines PL, PLB, a second pair of plate lines PLA, PLBA, several groups of word lines WL1, WL2, . . . , WL8, WLA1, . . . , WLA8, and several pairs of block select lines BS, BSB, BSA, BSAB.

Each word line is connected to a word line selecting circuit2, and the word line selecting circuit2is connected with a multilevel word line MWL. Further, the pair of bit lines BL, BLB is connected to a sense amplifier circuit3, and each memory block1includes a plurality of cell transistors4, a same number of ferroelectric capacitors5and a block selecting transistor6.

The number of the cell transistors4and the ferroelectric capacitors5in one memory block1is usually eight or sixteen, however, another number may be selected. Further, each transistor4is connected in series in each memory block1, and each gate of the cell transistors4is respectively connected to one of the word lines.

Turning now toFIG. 1, which illustrates a p-type silicon semiconductor substrate10and the block selecting transistor6including a first impurity-diffused region11, a second impurity-diffused region12and a first gate13.

Further, a first cell transistor420includes the second impurity-diffused region12, a third impurity-diffused region14, and a second gate15. Also, a second cell transistor421has the third-impurity diffused region14, a fourth impurity-diffused region16, and a third gate17.

A first capacitor has a first lower electrode18, a first ferroelectric layer19, and a first upper electrode20. The first lower electrode18is formed over the first gate13, the second impurity-diffused region12and the second gate15and is connected to the second impurity-diffused region12via a first polysilicon plug21.

In addition, a first metal plug22is connected to the third impurity-diffusion region14, and a first metal layer23is connected to the first metal plug22and the first upper electrode20via a first metal contact24. Further, the first cell transistor420and first capacitor perform as a first memory cell.

Also, a first dummy upper electrode25is formed on the first ferroelectric layer19and over the first gate13. Note the first dummy upper electrode25is not connected to the block selecting transistor6, the first cell transistor420and the second cell transistor421.

In addition, a second capacitor includes a second lower electrode26, a second ferroelectric layer27and a second upper electrode28respectively formed over the third gate17and the fourth impurity-diffused region16. The second lower electrode26is connected to the fourth impurity-diffused region16via a second polysilicon plug29, and the second upper electrode28is connected to the first metal layer23via a second metal contact30. Further, the second cell transistor421and the second capacitor perform as a second memory cell.

In addition, the block selecting transistor6, the first memory cell, and the second memory cell are included in one memory block. Also, capacitors and cell transistors are arranged repeatedly in the direction of the right side ofFIG. 1. The number of the capacitors and the cell transistors is same as the number of the memory cells in one memory block, and the memory block is repeatedly arranged in the same direction in plural number.

Further, a first bit line plug31is connected to the first impurity-diffused region11, a first bit line contact32is connected to the first bit line plug31, and a second bit line plug33is connected to the first bit line contact32. Also, a first bit line34is formed over the block selecting transistor6, the first memory cell, and the second memory cell, and is connected to the second bit line plug33.

In addition, a first isolation region35is formed on the semiconductor substrate10and is adjacent to the first impurity-diffused region11. A passing word line36is also formed on the first isolation region35. Further, a fifth impurity-diffused region40is formed on the semiconductor substrate10, and is adjoined to the opposing side of a side facing the first impurity-diffused region11of the first isolation region35.

A second metal plug41is connected to the fifth impurity-diffused region40and the first bit line contact32, a fourth gate42is formed on the semiconductor substrate10and is adjoined to the fifth impurity-diffused region40, and a sixth impurity-diffused region43is formed on the semiconductor substrate10and is adjoined to the fourth gate42.

Further, a second block selecting transistor422includes the fifth impurity-diffused region40, a sixth impurity-diffused region43, and the fourth gate42. A second isolation region410is formed on the semiconductor substrate10and is adjoined to the sixth impurity-diffused region43. Also, a second passing word line411is formed on the second isolation region410.

Also, a third lower electrode37is formed over the second passing word line411, a third ferroelectric layer38is formed on the third lower electrode37, and a second dummy electrode39is formed on the third ferroelectric layer38.

In addition, a seventh impurity-diffusion region50is formed on the semiconductor substrate and is adjacent to the second isolation region410. A fifth gate49is formed on the semiconductor substrate10and is adjacent to the seventh impurity-diffusion region50, and an eighth impurity-diffusion region415is formed on the semiconductor substrate10and is adjacent to the fifth gate49.

A third cell transistor423includes the seventh impurity-diffused region50, the eighth impurity-diffused region415and the fifth gate49. Further, a third polysilicon plug44is connected to the eighth impurity-diffused region415, and a fourth lower electrode45is connected to the third polysilicon plug44and is formed over the fifth gate49and the eighth impurity-diffused region415.

Also, a fourth ferroelectric layer46is formed on the fourth lower electrode45, and a third upper electrode47is formed on the fourth ferroelectric layer46. The third upper electrode47is connected to the fourth metal layer413via a third metal contact48.

A third capacitor includes the fourth lower electrode45, the fourth ferroelectric layer46, and the third upper electrode47. In addition, a sixth gate416is formed on the semiconductor substrate10and is adjacent to the eighth impurity-diffused region415, and a ninth impurity-diffused region417is formed on the semiconductor substrate10and is adjacent to the sixth gate416. A fourth cell transistor424includes the eighth impurity-diffused region415, the sixth gate416and the ninth impurity-diffused region417.

Further, a fourth upper electrode51is formed on the fourth ferroelectric layer46and over the sixth gate416, and a fourth metal contact52is formed on the fourth upper electrode51. A third metal layer53is formed over the sixth gate416and the ninth impurity-diffused region417and is connected to the fourth metal contact52. The fourth capacitor includes the fourth lower electrode45, the fourth ferroelectric layer46, and the fourth upper electrode51.

Also, a third metal plug412is connected to the sixth impurity-diffused region43and to the fourth metal layer413. In addition, a fourth metal plug414is connected to the seventh impurity-diffused region50and to the fourth metal layer413.

The second block selecting transistor422, the third capacitor, the fourth capacitor, the second dummy upper electrode39, the third cell transistor423, and the fourth cell transistor424are provided in the same memory block. Further, both of the capacitors and cell transistors are repeatedly provided toward the left direction (as discussed previously with respect to the right direction).

The fourth memory cell includes the fourth cell transistor and the fourth capacitor and the third and fourth memory cells are placed in the same block. Further, as noted above, this structure is repeated in the longitudinal direction. Also, the elements described inFIGS. 1 and 2are covered by an insulating layer60.

As described above, the first dummy upper electrode25is isolated from the first metal layer23and every other metal layer. Therefore, the first dummy upper electrode25does not function as a capacitor.

In this embodiment, the ferroelectric layer and lower electrode are under the first dummy upper electrode25. However, it is not necessary to provide such a ferroelectric layer or lower electrode under the dummy upper electrode. That is, the dummy upper electrode may be provided on the insulating layer without the ferroelectric layer or over the lower electrode without the ferroelectric layer or on the ferroelectric layer without the lower electrode.

In addition, the area of the dummy upper electrode may be the same size as the other upper electrode. In other situations, the area of the dummy upper electrode may be smaller or larger than the other upper electrode. If the size of dummy upper electrode is larger than the other upper electrode, the area of the block selection transistor needs to be larger than usual.

In the structure described above, the ferroelectric layer and lower electrode are under the first dummy upper electrode25, and are commonly used with another neighboring memory cell. However, the ferroelectric layer or the lower electrode under the dummy upper electrode may be independently formed for the dummy upper electrode.

In addition, inFIG. 2, a width of the lower electrodes18,26,45in their shorter direction is around 1.2 micrometer, for example, and a width of the upper electrodes20,28,47,51and the first dummy electrode25in their shorter direction is around 1.0 micrometer. Also, a length of the lower electrodes18,26,45in their longer direction is around 2.2 micrometer, and a length of the upper electrode20,28,47,51in their longer direction is around 1.0 micrometer. Further, a length of the first dummy upper electrode25in its longer direction is around 0.5 micrometer.

InFIG. 1, a thickness of the lower electrodes18,26,37,45is approximately 0.1 micrometer to 0.2 micrometer, for example, and a thickness of the ferroelectric layers19,27,38,46is approximately 0.1 micrometer to 0.3 micrometer, for example. Further, a thickness of the upper electrodes20,28,47,51, the first dummy upper electrode25and the second dummy electrode39is approximately 0.1 micrometer to 0.2 micrometer, for example.

Also, a thickness of the gates13,15,17,42,49,416and the passing word lines36,411is around 0.2 micrometer, for example, and a thickness of the polysilicon plugs21,29,44is around 0.6 micrometer, for example. In addition, a distance from an upper surface of the upper electrodes20,28,47,51to a lower surface of the metal layers23,32,53,413and the first bit line contact32are around 0.5 micrometer, for example. In addition, a thickness of the metal layers23,53,413and the first bit line contact32is around 0.4 micrometer, and a distance from an upper surface of the metal layers23,53,413and the first bit line contact32to a lower surface of the bit line34is around 0.5 micrometer, for example.

In general, the area of the upper electrode is smaller than that of the lower electrode or ferroelectric layer. This is because two upper electrodes are formed on one ferroelectric layer and one lower electrode.

Because of the sequence of manufacturing steps, these sizes are predetermined. In the manufacturing process, the upper electrode is etched to be a predetermined shape in an earlier step, and then the ferroelectric layer and the lower electrode are etched to be a predetermined shape. If the sequence of manufacturing step is changed, the upper electrode may be formed larger than the ferroelectric layer or the lower electrode. In this case, one upper electrode may be used for two neighboring memory cells.

Also note the specific features described above are shown as an example, and these features may be changed depending on particular technical specifications.

Turning now toFIGS. 3 and 4, which illustrate the right side of the semiconductor memory shown inFIGS. 1 and 2. As shown, a fifth cell transistor425includes the fourth impurity-diffused region16, a seventh gate61and a tenth impurity-diffused region62on the semiconductor substrate10. The seventh gate61is adjacent to the fourth impurity diffusion region16.

Further, a fifth upper electrode63is formed on the second ferroelectric layer27and over the seventh gate61. A fifth metal plug64is connected to the tenth impurity-diffused region62, and a fifth metal layer65is formed over the fifth upper electrode63and the tenth impurity-diffused region62and is connected to the fifth metal plug64. A fifth metal contact66is also formed between and connected to the fifth upper electrode63and the fifth metal layer65.

A fifth capacitor includes the second lower electrode26, the second ferroelectric layer27, and the fifth upper electrode63. Further, a fifth memory cell includes the fifth cell transistor425and the fifth capacitor.

In addition, a sixth cell transistor426includes the tenth impurity-diffused region62, an eighth gate67and an eleventh impurity-diffused region68respectively formed on the semiconductor substrate10. The eighth gate67is adjacent to the tenth impurity-diffused region62, and the eleventh impurity-diffused region68is adjacent to the eighth gate67.

Further, a fourth polysilicon plug69is connected to the eleventh impurity-diffused region68. A fifth lower electrode70is connected to the fourth polysilicon plug69and is formed over the eighth gate67and the eleventh impurity-diffused region68. In addition, a fifth ferroelectric layer71is formed on the fifth lower electrode70, and a sixth upper electrode72is formed on the fifth ferroelectric layer71and over the eighth gate67. A sixth metal contact73is formed between and connected to the fifth metal layer65and the sixth upper electrode72.

A sixth capacitor includes the fifth lower electrode70, the fifth ferroelectric layer71and the sixth upper electrode72, and a sixth memory cell includes the sixth cell transistor426and the sixth capacitor.

In the above structure, the distance between the first dummy upper electrode25and the first upper electrode20, and the distance between the second upper electrode28and the fifth upper electrode63are set to “X”. The distance between the first upper electrode20and the second upper electrode28is set to “Y”. Usually, the length “Y” is larger than the length “X”, because there is first metal plug22between the first upper electrode20and the second upper electrode28. Further, a marginal space is needed for manufacturing the first metal plug22between the first lower electrode18and the second lower electrode26.

Turning now toFIG. 5, which is a cross sectional view of the semiconductor memory inFIG. 2as depicted on the line C-D. Each element inFIG. 5is shown in positions corresponding to the each position in the longitudinal direction shown inFIG. 2. Note,FIG. 5shows a memory block neighboring in parallel in the longitudinal direction to the memory block shown inFIGS. 1 and 2.

As shown, a seventh cell transistor427includes a second gate15, a twelfth impurity-diffused region74, and a thirteenth impurity-diffused region75respectively formed on the semiconductor substrate10. The twelfth impurity-diffused region74and the thirteenth impurity-diffused region75are adjacent to the second gate15.

Further, a fifth polysilicon plug76is connected to the thirteenth impurity-diffused region75, and a sixth lower electrode77is connected to the fifth polysilicon plug76and is formed over the second gate15and the thirteenth impurity-diffused region75. A sixth ferroelectric layer78is formed on the sixth lower electrode77, and a seventh upper electrode79is formed on the sixth ferroelectric layer78and over the second gate15. Also, a seventh metal contact80is formed on the seventh upper electrode79, and a sixth metal plug81is connected to the twelfth impurity-diffused region74.

Further, a sixth metal layer82is formed over the second gate15and the twelfth impurity-diffused region74, and is connected to the seventh metal contact80and the fifth metal plug81. A seventh capacitor includes the sixth lower electrode77, the sixth ferroelectric layer78, and the seventh upper electrode79. Further, a seventh memory cell includes a seventh cell transistor427and a seventh capacitor.

Also, an eighth cell transistor428has a third gate17, a thirteen impurity-diffused region75, and a fourteenth impurity-diffused region83. The thirteenth impurity-diffused region75and the fourteenth impurity-diffused region83is adjacent to the third gate17.

The sixth lower electrode77and the sixth ferroelectric layer78are formed over the third gate17. An eighth upper electrode84is also formed on the sixth ferroelectric layer78and over the third gate17, and an eighth metal contact85is formed on the eighth upper electrode84. In addition, a seventh metal layer86is formed over the third gate17and the fourteenth impurity-diffused region83, and is connected to the eighth metal contact85. Note, an eighth capacitor includes the sixth lower electrode77, the sixth ferroelectric layer78, and the eighth upper electrode84. Note an eighth memory cell includes the eighth cell transistor428and an eighth capacitor.

Further, a second bit line87is formed over the sixth metal layer82and the seventh metal layer86. A fifteenth impurity-diffused region88is formed on the semiconductor substrate10and is adjacent to the first isolation region35, and a seventh metal plug89is connected to the fifteenth impurity-diffused region88and the sixth metal layer82.

Also, a seventh lower electrode90is formed over the first isolation region35, and a seventh ferroelectric layer91is formed on the seventh lower electrode90. A third dummy upper electrode92is formed on the seventh ferroelectric layer91and is disconnected from other transistors. Further, the elements as described above in connection withFIG. 5are covered by an insulating layer60, and the structure is repeated in the longitudinal direction. Also, the sixth metal layer82is used for connecting the twelfth impurity-diffused region74and the fifteenth impurity-diffused region88.

InFIG. 1, when the block selecting transistor6is selected, the memory block shown inFIG. 1is selected and is connected to the first bit line34, and the memory block shown inFIG. 5is not selected and is disconnected from the second bit line87.

The procedure for selecting the memory block described above uses the folded bit line formation for selecting a pair of neighboring memory blocks. For example, as shown inFIG. 34, the folded bit line formation includes a pair of complement bit lines respectively connected to neighboring memory blocks in the extending direction of block selection lines which are activated alternatively.

In addition, the structure of the neighboring region around the plate line inFIG. 34is shown inFIGS. 6 and 7. The top view is shown inFIG. 6and the sectional view of line “E-F” is shown inFIG. 7. The position of each element inFIG. 7corresponds to the position in the longitudinal direction of each element inFIG. 6.

As shown, a sixteenth impurity-diffused region93is formed on the semiconductor substrate10, and a ninth gate94is formed on the semiconductor substrate10and is adjacent to the sixteenth impurity-diffused region93. A seventeenth impurity-diffused region95is formed on the semiconductor substrate10and is adjacent to the ninth gate94. The sixteenth impurity-diffused region93, the ninth gate94and the seventeenth impurity-diffused region95form a ninth cell transistor429.

Further, a sixth polysilicon plug96is connected to the sixteenth impurity-diffused region93, and an eighth lower electrode97is connected to the sixth polysilicon plug96and is formed over the sixteenth impurity-diffused region93and the ninth gate94. An eighth ferroelectric layer99is formed on the eighth lower electrode97, and a ninth upper electrode200is formed on the eighth ferroelectric layer99and over the eighth gate94. A seventh metal plug201is also formed on the seventeenth impurity-diffused region95.

The eighth lower electrode97, the eighth ferroelectric layer99, and the ninth upper electrode200form a ninth capacitor. Further, the ninth cell transistor429and the ninth capacitor form a ninth memory cell.

In addition, a tenth gate202is formed on the semiconductor substrate10and is adjacent to the seventeenth impurity-diffused region95, and an eighteenth impurity-diffused region203is formed on the semiconductor substrate10and is adjacent to the tenth gate202. A tenth cell transistor430includes the seventeenth impurity-diffused region95, the ninth gate202and the eighteenth impurity-diffused region203.

Also, a ninth lower electrode205is connected to the seventh polysilicon plug204and is formed over the tenth gate202and the eighteenth impurity-diffused region203. A ninth ferroelectric layer206is formed on the ninth lower electrode205, and a tenth upper electrode207is formed on the ninth ferroelectric layer206and over the tenth gate202.

A ninth metal contact208is connected to the ninth upper electrode200, and a tenth metal contact209is connected to the tenth upper electrode207. An eighth metal layer210is connected to the seventh metal plug201, the ninth metal contact208and the tenth metal contact209. Further, a fourth dummy upper electrode211is formed on the ninth ferroelectric layer206.

A tenth capacitor includes the ninth lower electrode205, the ninth ferroelectric layer206, and the tenth upper electrode207. Further, a tenth memory cell includes the tenth cell transistor430and the tenth capacitor.

In addition, a first plate line212is used for selecting the memory cell block positioned in an upper direction of the memory cell block on the “E-F” line shown inFIG. 6. The first plate line212is formed over the fourth dummy upper electrode211and is positioned in the same level of the eighth metal layer210in a vertical direction inFIG. 7. Also, an eighth metal plug213is connected to the eighteenth impurity diffused region203.

A second plate line214is connected to the eighth metal plug213(hereinafter the area around the eighth metal contact213is called a plate line contact area). Further, an eleventh metal contact215is connected to the second plate line214, an eleventh upper electrode216is connected to the eleventh metal contact215, and a tenth ferroelectric layer217is formed under the eleventh upper electrode216. A tenth lower electrode218is also formed under the tenth ferroelectric layer217.

In addition, note that by providing the fourth dummy upper electrode211, the space between the upper electrodes in the plate line contact area becomes smaller, so the increase of space when an upper electrode is not in the plate line contact area is prevented. Therefore, the upper electrode performing circuit operation is not located in the outer side of the memory block and a regular distance between the upper electrodes is maintained in every portion in the memory blocks.

Further, the memory block positioned on the line of “A-B” inFIG. 2and the memory block positioned on the line of “C-D” inFIG. 2are formed as a folded bit line manner in each memory cell block.

Also, the first gate13performs a block selecting gate of the memory cell block positioned on the “A-B” line. The first passing word line36performs a selecting gate of the memory cell block positioned on the “C-D” line. Further, the first gate13performs a passing gate of the memory cell block positioned on “C-D”, and the first passing word line36performs a passing gate of memory cell block positioned on “A-B”.

In addition, the first bit line contact32is used for connecting the impurity-diffused regions11,40of the element region positioned on both sides of the first passing word line36. The memory cell blocks formed in two steps toward the longitudinal direction are shown inFIG. 2.

As discussed above, each memory cell block includes eight or sixteen memory cells and transistors, for example. In addition, the pattern shown inFIG. 2is repeated eight or sixteen times.

Further, the lower electrode is made from multi-layered platinum layers formed on a Ti layer, and a thickness of the platinum layer is around 100 nanometers, for example. The lower electrode may be formed as Pt layers on a silicon layer or metal layer. In addition, an Ir layer or IrO2layer may be used as the lower electrode, and a stacked layer structure of Ti layer, TiN layer, and Pt layer may be used as a lower electrode. Further, each SrRuO layer, Ru layer, RuO layer may be used as a lower electrode.

A composite layer such as SrBiTaO or PbZrTiO, e.g., PZT, (i.e., Pb(ZrXTi1-x)O3is used as the ferroelectric layer, and thickness of the PZT layer is around 150 nanometers, for example. A composite layer of BaSrTiO may also be used as the ferroelectric layer. Further, BaTiO3, LiNbO3, K3Li2Nb5O15may be used as the ferroelectric layer. Namely, an oxidized ferroelectric layer having characteristics of ion bonding may be used as the ferroelectric layer.

In addition, a platinum layer may be used as the upper electrode with a thickness of the Pt layer being around 20 nanometers, for example. A metal layer, (e.g., A1 layer) or a Silicon layer may be deposited on the Pt layer as the upper electrode. In addition, Ir, IrO2may also be used as the upper electrode, and each of the SrRuO, Ru, RuO layer is used as the upper electrode. Also, a BPSG layer or TEOS layer is used as the mid-layer insulating film, and an A1 layer may be used as the metal layer.

Further, the dielectric polarization of a capacitor increases and the characteristics of a memory improve by expanding the area of the upper electrode. Note the area of the upper electrode is determined by each specification.

In the first embodiment, the dummy capacitor which is disconnected from every cell unit, every impurity diffusion region, and every gate electrode is provided on the block selecting transistor and under the plate line. By providing the dummy capacitor, each capacitor used for a memory cell is not provided on the most outer position. Thus, according to the first embodiment, the characteristics of the memory capacitor are improved by using a dummy upper electrode adjacent to the block selecting transistor or the plate line.

The second preferred embodiment according to the present invention will now be described with reference toFIGS. 8 to 13. In this embodiment, the lower electrode of the memory capacitor is used as a connecting layer for impurity-diffused regions separated by an isolation region.

FIG. 8shows a plane view of this embodiment, with cross section of the line “G-H” being shown inFIG. 9. Further, each element inFIG. 9is provided in the same positions corresponding to the elements positioned in the lateral direction inFIG. 8.

As shown inFIG. 9, a semiconductor substrate230, which is p-type silicon, is provided. A first cell transistor231has a first impurity-diffused region232, a second impurity-diffused region233and a first gate234. A second cell transistor235includes the second impurity-diffused region233, a third impurity-diffused region236and a second gate237.

Further, a first capacitor has a first lower electrode238, a first ferroelectric layer239, and a first upper electrode240formed over the first gate234. The first lower electrode238is formed over the first impurity-diffused region232and the first gate234and is connected to the first impurity-diffused region232via a first polysilicon plug241. A first metal plug242is connected to the second impurity-diffused region233, and a first metal layer243is connected to the first metal plug242. The first metal layer243is also connected to the first upper electrode240via a first metal contact244.

Note, a first memory cell includes the first cell transistor231and the first capacitor.

A second capacitor includes a second lower electrode245, a second ferroelectric layer246, and a second upper electrode247respectively formed over the second gate237. The second lower electrode245is formed over the third impurity-diffused region236and is connected to the third impurity-diffused region236via a second polysilicon plug248. Further, a second metal contact249is connected between the first metal layer243and the second upper electrode247.

Note, a second memory cell includes the second cell transistor235and the second capacitor.

In addition, an isolation region250is formed on the semiconductor substrate230and is adjacent to the first impurity-diffused region232. A fourth impurity-diffused region251is formed on the semiconductor substrate230and is adjacent to the isolation region250. A passing word line252is formed on the isolation region250, and a third polysilicon plug253is formed between the fourth impurity-diffused region251and the first lower electrode238.

Further, a first dummy upper electrode254is formed on the first ferroelectric layer239and over the passing word line252. Note that the first dummy upper electrode254is not connected to any cell transistors. A first layer word line255is also formed over the first dummy upper electrode254.

In addition, the first cell transistor231, the first capacitor, the second cell transistor235, and the second capacitor are included in one memory block, and a first bit line256is formed over the memory block. Further, the structure above-described structure is repeated in the longitudinal direction inFIG. 9, and each element shown inFIG. 9is covered by an insulating layer257.

Also, the first lower electrode238is connected between the first impurity-diffused region232and the fourth impurity-diffused region251. Therefore, there is no need to provide a metal layer to connect the first impurity-diffused region232and the fourth impurity-diffused region251. By using this structure, a multi layered word line as the first folded bit lines255is provided on the isolation region.

In this structure, an increase in area of the block selecting transistor is prevented by using the lower electrode for connection of the impurity-diffused regions. Further, the resistance of the lower electrode of the capacitor for connection of the impurity-diffused regions is preferably set lower than one tenth of a resistance of the block selecting transistor during on state. Namely, the lower electrode has a resistance below several hundreds ohm. The series resistance of the lower electrodes is preferably around several hundreds ohm. In general, the resistance of a normal lower electrode is around 10K ohm.

Further, in this embodiment, the dummy upper electrode may be optionally omitted, and a width of the multi layered bit lines has a smaller size rather than the width of the dummy upper electrode in their shorter direction. Note also the block selecting transistor is omitted inFIG. 9, which is actually located in a left outer portion of the fourth impurity-diffused region251.

As described above, the first dummy upper electrode254is isolated from the cell transistor. Therefore, the first dummy upper electrode254does not perform as a capacitor. Also, in this embodiment, the ferroelectric layer and the lower electrode are under the dummy upper electrode. However, it is not necessary to provide such a ferroelectric layer or a lower electrode under the dummy upper electrode. That is, the dummy upper electrode may be provided on the insulating layer, over the lower electrode without the ferroelectric layer, or on the ferroelectric layer without the lower electrode. Further, the area of the dummy upper electrode may be the same size as the upper electrode, or may be smaller or larger than the area of the upper electrode.

In the above-described structure, the ferroelectric layer and lower electrode under the dummy upper electrode are commonly used respectively with other neighboring memory cells. However, the ferroelectric layer or the lower electrode under the dummy upper electrode may be independently formed for the dummy upper electrode. In addition, each size of the elements described above may be the same size as corresponding elements in the first embodiment.

Turning now toFIG. 10, which is a cross sectional view of the semiconductor memory inFIG. 8as depicted on line “I-J”. Further, each element is positioned similarly to the elements inFIG. 8in a lateral direction.

As shown, a third cell transistor431includes the first gate234, a fifth impurity-diffusion region260, and a sixth impurity-diffused region261. The fifth impurity-diffused region260and the sixth impurity diffused region261are adjacent to the first gate234. A fourth polysilicon plug262is connected to the sixth impurity diffused region261. In addition, a third lower electrode263is connected to the fourth polysilicon plug262and is formed over the first gate234and the sixth impurity-diffused region261. Further, a third ferroelectric layer264is formed on the third lower electrode263, and a third upper electrode265is formed on the third ferroelectric layer264and over the first gate234.

A third metal contact266is also formed on the third upper electrode265, and a second metal plug267is connected to the fifth impurity-diffused region260. A second metal layer268is formed over the first gate234and the fifth impurity-diffused region260, and is connected to the third metal contact266and the second metal plug267.

Further, a third capacitor includes the third lower electrode263, the third ferroelectric layer264, and the third upper electrode265. Also, a third memory cell includes a third cell transistor431and a third capacitor, and a fourth cell transistor432has a second gate237, the sixth impurity-diffused region261, and a seventh impurity-diffused region269. Note the seventh impurity-diffused region269is adjacent to the second gate237.

In addition, a fourth upper electrode270is formed over the second gate237, and a fourth metal contact271is formed on the fourth upper electrode270. Also, a third metal layer272is formed over the second gate237and the seventh impurity-diffused region269, and is connected to the fourth metal contact271. A fourth capacitor includes the third lower electrode263, the third ferroelectric layer264, and the fourth upper electrode270, and a fourth memory cell includes a fourth cell transistor432and a fourth capacitor.

In addition, a block selecting transistor433includes the fifth impurity-diffused region260, the passing word line252and a ninth impurity-diffused region273. Note the ninth impurity-diffused region273is formed on the semiconductor substrate230and is adjacent to the passing word line252.

Also, a third metal plug274is connected to the ninth impurity-diffused region273, a fourth metal layer275is connected to the third metal plug274, and a fourth lower electrode276is formed over the third gate252. Also, a fourth ferroelectric layer277is formed on the fourth lower electrode276, a second dummy upper electrode278is formed on the fourth ferroelectric layer277, and a first layer word line255is formed over the second dummy upper electrode278.

Note, the third memory cell, the fourth memory cell, and the block selecting transistor are included in same memory block. Further, a second bit line280is formed on the memory cell block, and every element described above in connection withFIG. 10is covered by an insulating layer257.

In addition, the elements shown inFIG. 10are repeated in a longitudinal direction of the memory block inFIG. 8, and the pattern of the neighboring area of the plate line is the same as the first embodiment and thus a description is omitted. When the block selecting transistor433shown inFIG. 10is selected, the memory block shown inFIG. 10is selected and is connected to the second bit line280, and the memory block shown inFIG. 9is not selected and is disconnected from first bit line256.

By using the lower electrode wire to connect element regions on both sides of the passing gate, the area of block selecting transistor is not determined by the design rule of the first metal layer. Further, there is a passing word line over the lower electrode wire. Also, by using a COP structure, a plug may be provided in the capacitor area. Therefore, reduction of the plug area is possible and high density is achieved.

In the procedure of the selecting memory block described above, the folded bit line formation is used for selecting a pair of neighboring memory blocks. As discussed above, and as shown inFIG. 34, the folded bit line formation is the manner in which a pair of complement bit lines is respectively connected to each neighboring memory block in an extending direction of block selection lines and is activated alternately.

In this embodiment, there is no need to increase the number of wires of the multi-layered word line, nor is there is no need to increase the area of block selecting transistor. Further, according to the second embodiment, a direct connection is provided by using the lower electrode between the impurity-diffused regions combining the isolation region. The direct connection in this embodiment markedly reduces the space around the isolation region for placing the multi-layered bit line.

Turning now to the third preferred embodiment according to the present invention, which will be described with reference toFIGS. 11 to 14. InFIG. 11, the cross section of the line “K-L” is shown inFIG. 12, and each element inFIG. 12is provided in the same position corresponding to the elements positioned in the lateral direction inFIG. 11.

As shown inFIG. 12, a semiconductor substrate300, which is p-type silicon, is provided. A first cell transistor301has a first impurity-diffused region302, a second impurity-diffused region303and a first gate304. A second cell transistor305has the second impurity-diffused region303, the third impurity-diffused region306and a second gate307.

Further, a first capacitor includes a first lower electrode308, a first ferroelectric layer309, and a first upper electrode310formed over the first gate304. The first lower electrode308is also formed over the first impurity-diffused region302and the first gate304, and is connected to the first impurity-diffused region302via a first polysilicon plug311. In addition, a first metal plug312is connected to the second impurity-diffused region303, a first metal layer313is connected to the first metal plug312, and the first metal layer313is connected to the first upper electrode310via a first metal contact314.

Note the first cell transistor301and the first capacitor form a first memory cell.

Also, a second capacitor has a second lower electrode315, a second ferroelectric layer316, and a second upper electrode317respectively formed over the third impurity-diffused region306and the second gate307. The second lower electrode315is formed over the third impurity-diffused region306and the second gate307, and is connected to the third impurity-diffused region306via a second polysilicon plug318. In addition, a second metal contact319is connected between the first metal layer313and the second upper electrode317.

Note, the second cell transistor305and a second capacitor form a second memory cell.

Also, an isolation region320is formed on the semiconductor substrate300and is adjacent to the first impurity-diffused region302. A fourth impurity-diffused region321is formed on the semiconductor substrate300and is adjacent to the isolation region320. Further, a passing word line322is formed on the isolation region320.

As shown, a second metal plug323is connected to the fourth impurity-diffused region321, a second metal layer324is connected to the second metal plug323, and a bit line contact325is connected between the second metal layer324and a bit line326. In addition, a first dummy upper electrode327is formed on the first ferroelectric layer309and over the passing word line322. Note the first dummy upper electrode327is not connected to any memory transistors. Further, a first layer word line328is formed over the first dummy upper electrode327.

Also, the first layer word line328has a narrower width rather than the dummy upper electrode, and the first memory cell and the second memory cell are included in same memory block. The bit line326is also formed over the memory cell block. Further, the structure described inFIG. 12is repeated in a longitudinal direction of the memory block, and each element shown inFIG. 12is covered by an insulating layer329. The block selecting transistor is also omitted inFIG. 12, which is located in a left outer portion of the fourth impurity-diffused region321.

As described above, the first dummy upper electrode327is isolated from the first metal layer313and the second metal layer324. Therefore, the first dummy upper electrode327does not perform as a capacitor.

Further, in this embodiment, the ferroelectric layer and lower electrode are under the first dummy upper electrode. However, it is not necessary to provide the ferroelectric layer or lower electrode under the dummy upper electrode. That is, the dummy upper electrode may be provided on the insulating layer, on the lower electrode without the ferroelectric layer, or on the ferroelectric layer without the lower electrode.

In addition, the area of dummy upper electrode may be the same size as the other upper electrodes or may be smaller or larger than the other upper electrodes. If the size of the dummy upper electrode is larger than the other upper electrodes, the area of the block selecting transistor needs to be larger than usual.

In the above-described structure, the ferroelectric layer and the lower electrode under the dummy upper electrode are commonly used respectively with other neighboring memory cells. However, the ferroelectric layer or the lower electrode under the dummy upper electrode can be independently formed for dummy upper electrode (as discussed above).

In addition, each size of the elements described above may be the same size as the corresponding elements in the first embodiment. Further, the semiconductor memory shown inFIG. 11, as depicted on line “M-N”, is the same as the semiconductor memory shown inFIG. 12as a cross sectional view. Namely, in the neighboring memory block in the word line extending direction, there is the same structure between them.

In addition, the structure of the neighboring region around the plate line inFIG. 34adapted to this embodiment is shown inFIGS. 13 and 14. The top view is shown inFIG. 13and the sectional view of line “O-P” inFIG. 13is shown inFIG. 14. Each element inFIG. 14positioned in the lateral direction corresponds to each element position in lateral direction inFIG. 13.

As shown, a fifth impurity-diffusion region330is formed on the semiconductor substrate300, and a third gate331is formed on the semiconductor substrate300and is adjacent to the fifth impurity-diffused region330. Further, a sixth impurity-diffused region332is formed on the semiconductor substrate300and is adjacent to the third gate331. Note, the fifth impurity-diffused region330, the third gate331and the sixth impurity-diffused region332form a third cell transistor434.

In addition, a third polysilicon plug333is connected to the sixth impurity-diffused region332, and a third lower electrode334is connected to the third polysilicon plug333and is formed over the sixth impurity-diffused region332and the third gate331. Also, a third ferroelectric layer335is formed on the third lower electrode334, a third upper electrode336is formed on the third ferroelectric layer335and over the third gate331, and a third metal plug337is formed on the fifth impurity-diffused region330. The third lower electrode334, the third ferroelectric layer335, and the third upper electrode336form a third capacitor.

Note, the third cell transistor434and the third capacitor form a third memory cell.

Further, a fourth gate338is formed on the semiconductor substrate300and is adjacent to the sixth impurity-diffused region332. A seventh impurity-diffused region339is formed on the semiconductor substrate300and is adjacent to the fourth gate338. Note a fourth cell transistor435includes the sixth impurity-diffused region332, the fourth gate338, and the seventh impurity-diffused region339.

In addition, a fourth metal plug340is connected to the seventh impurity diffused region339, and a second dummy upper electrode341is formed on the third ferroelectric layer335and over the fourth gate338. A third metal contact342is also connected to the third upper electrode336, and a third metal layer343is connected to the third metal plug337and the third metal contact342. Further, a first plate line344is formed on the fourth metal plug340, and a second plate line345for another memory block is formed over the second dummy upper electrode341and is positioned in the same level of the third metal layer343and the first plate line344in a vertical direction.

By providing the second dummy upper electrode341, the space between each upper electrode neighboring the plate line becomes smaller, so the increase of space caused by no upper electrode neighboring the plate line is prevented. Therefore, the upper electrode performing the circuit operation is not located in the most outer side of memory block and a regular distance between upper electrodes is maintained in every portion.

According to the third embodiment, the characteristics of the memory capacitor are improved by using the dummy upper electrode adjacent to the block selecting transistor or the plate line.

The fourth preferred embodiment according to the present invention will now be described with reference toFIGS. 15 to 22, and relates to a method of fabricating a semiconductor memory device according to the first embodiment. In more detail,FIGS. 15 to 22correspond to the portion on the line “AR-B” inFIG. 1, and each element shown inFIGS. 15toFIG. 22are positioned in a corresponding location as inFIG. 1.

As shown inFIG. 15, the first isolation region35, the first to fourth impurity-diffused regions11,12,14,16, the first to third gate13,15,17, the passing word line36, the insulating layer60, and the first and second polysilicon plug21,29are formed in sequence.

The trench having around a 0.3 micrometer depth is formed in the semiconductor substrate to form the isolation region35. In the next step, an SiO2layer is deposited on the entire surface of the semiconductor substrate by using a mixture gas of TEOS gas and ozone gas according to the vapor growth method. After these fabricating steps, an element isolation layer including the SiO2layer is filled into the trench and the isolation region is formed.

Then, the first to the third gate electrodes13,15,17are formed on the semiconductor substrate. Further, there are gate insulating films between the first to the third gate electrodes and the semiconductor substrate, but they are omitted in each figure. Next, the first to the fourth impurity diffusion regions11,12,14,16for the source and drain regions are formed and the MOS transistors are also formed.

Then, as shown inFIG. 16, the lower electrodes18,26, ferroelectric layers19,27, upper electrodes20,28and the dummy upper electrode25are formed on the insulating layer60, and the first and second polysilicon plugs21,29are formed in sequence. Namely, after the insulating layer60is deposited on the entire surface of the semiconductor surface, the surface of the semiconductor substrate is flattened by using the CMP method. After this step, a Ti/Pt layer for the lower electrode of the capacitor, ferroelectric PZT layer19,27, and Pt layer for the upper electrode20,28or the dummy upper electrode25of the capacitor is deposited on the entire surface of the semiconductor substrate. Then, after the ferroelectric layer is deposited or the Pt layer is deposited on the ferroelectric layer, the ferroelectric layer is annealed and crystallized.

Then, as shown inFIG. 17, the first upper electrode20, the first dummy upper electrode25, and the second upper electrode28are formed by respectively using resists in the etching method. Namely, the upper electrode layer is only left on the portion of the ferroelectric layer or the dummy upper electrode to be formed.

Then, as shown inFIG. 18, the first ferroelectric layer19, the second ferroelectric layer27, the first lower electrode18, and the second lower electrode26are respectively formed by etching. Next, the insulating layer60except under the first lower electrode18and the second lower electrode26is removed by etching. Then, as shown inFIG. 19, the insulating layer60is deposited over the entire surface of the semiconductor substrate. The surface of the insulating layer60is then flattened by the CMP method.

Next, as shown inFIG. 20, an opening is formed in the insulating layer60by removing the insulating layer60on the first upper electrode20and the second upper electrode28. As shown inFIG. 21, an opening is formed in the insulating layer60by removing the insulating layer60on the first impurity-diffused region11and the third impurity-diffused region14. As shown inFIG. 22, the first metal plug22, the first metal layer23, the first metal contact24, the second metal contact30, the first bit line plug31, and the first bit line contact32are formed by a forming metal layer (e.g., aluminum) in the opening provided in the insulating layer60.

The insulating layer60is then deposited on the surface shown inFIG. 22, and a contact hole is formed on the second bit line contact formation portion. The second bit line plug33is also formed in the contact hole, the first bit line34is formed on the second bit line plug33, and the insulating layer60is formed on the entire surface, resulting in the structure shown inFIG. 1. Namely, A1 stacked layers, i.e., Ti/TiN/A1 for the first bit line34are deposited on the entire surface and the first bit line34in a desired shape is formed by the RIE method.

By using the above fabricating method, the dummy upper electrode may be fabricated by using the same steps as a normal upper electrode. Therefore, highly integrated capacitors may be fabricated without micro loading effects.

The fifth preferred embodiment according to the present invention will now be described with reference toFIGS. 23 and 24.

Each embodiment described above is a COP type capacitor structure and is used for this invention. However, this invention is not limited to a COP type capacitor. Namely, this invention may also use the offset type capacitor. In the below description, the offset type capacitor means a capacitor which is located apart from the cell transistors in a shorter direction of the memory cell block and is not provided right above the cell transistor.

FIG. 23shows the upper plane view of this embodiment, in which the cross section of the line “Q-R” is shown inFIG. 24. Further, each element shown inFIG. 24positioned in the lateral direction corresponds to each element shown inFIG. 23positioned in the lateral direction.

InFIG. 23, the memory cell blocks are provided in two pairs in the upper and lower side, which is elongated in the lateral direction. In this embodiment, a first to the third impurity-diffused regions351,355,377are formed on the semiconductor substrate350. Further, a first isolation region353is formed adjacent to the first impurity-diffused region351, and a first gate352is formed on the first isolation region353.

The first impurity-diffused region351, the first gate352, and a portion which faces the first gate on the reverse side of the first impurity-diffused region351form a block selecting transistor. Also, a second gate354is formed on the semiconductor substrate between the first isolation region353and the second impurity-diffused region355.

A second isolation region357is also provided in the semiconductor substrate350separated from and neighboring to the second impurity-diffused region. A third gate356is formed on the semiconductor substrate350and is between the second impurity-diffused region355and the second isolation region357. A third isolation region358is formed adjacent to the first impurity-diffused region351, and a passing word line359is formed on the third isolation region358.

Further, a first lower electrode360and a first ferroelectric layer361are stacked over the first gate352, the first isolation region353, and the second gate354. A first upper electrode362is also formed on the first ferroelectric layer361and over the second gate354. A first dummy upper electrode363is also formed on the first ferroelectric layer361and over the first gate352. A first metal contact364for connecting the first lower electrode360is formed as penetrating in some portion of the first ferroelectric layer361. The first metal contact364is connected to a first one of the first layer of the metal layer365.

The first one of the first layer of the metal layer365is connected to the first metal contact364in an impurity region in the element region, which is shown as being surrounded by dotted lines inFIG. 23via the contact450. The first one of the first layer of the metal layer365is in the same position as the first metal contact364in the longitudinal direction of the memory cell block. However, the impurity region in the element region is not shown inFIG. 23.

Further, a second metal contact366is formed on the first upper electrode362, and is connected to a second one of the first layer of the metal layer367. A first metal plug368is also connected to the second impurity-diffused region355and the second one of the first layer of the metal layer367. Further, a second lower electrode369is formed over the third gate356and the second isolation region357, and a second ferroelectric layer370is provided on the second lower electrode369. Also, a second upper electrode372is provided on the second ferroelectric layer370and over the third gate356.

The second upper electrode372is connected to the second one of the first layer of the metal layer367via the third metal contact373. A fourth metal contact374for connecting the second lower electrode369is formed as penetrating in some portion of the second ferroelectric layer370. The fourth metal contact374is further connected to the third one of the first layer of the metal layer375.

A third one of the first layer of the metal layer375is connected to the fourth metal contact365in the impurity-diffused region in element region, which is shown as surrounded by dotted lines inFIG. 23via the contact451. The third one of the first layer of the metal layer375is in the same position as the fourth metal contact374in a longitudinal direction of the memory cell block. However, the impurity-diffused region in the element region is not shown inFIG. 23.

In addition, a second metal plug376is connected to the first impurity-diffused region351, and a third impurity-diffused region377is formed on an opposite face of the first impurity-diffused region351of the third isolation region358. A first bit line plug378is also connected to the third impurity-diffused region377, and is connected to the second metal plug376via fourth one of the first layer of the metal layer379. The fourth one of the first layer of the metal layer379is connected to a bit line contact380over the first bit line plug378. Further, the bit line contact380is connected to the first bit line381over the fourth one of the first layer of the metal layer379.

Note, there is a connection between the first lower electrode360of the first capacitor and the first one of the first layer of the metal layer365as shown in the cross section inFIG. 24. Also, there is no connection between the first lower electrode360of the first capacitor and the cell transistor shown inFIG. 24. However, as shown inFIG. 23, there is a connection between the first lower electrode360of the first capacitor and the first cell transistor by using a wire extending toward a direction below from the first one of the first layer of the metal layer.

Thus, there is a capacitor provided on the region separated from the element region which cell transistor is provided. Further, the element region and the upper electrode of the capacitor are connected via the contact, and the element region and the lower electrode of the capacitor are connected via the first layer of the metal layer. Thus, the cell transistor and the capacitor are provided respectively in a different region. Therefore, the area of this embodiment is larger than the area of the COP type ferroelectric memory cell structure. Further, each elements described above is covered by an insulating layer382.

In this fifth embodiment, a dummy capacitor not connected to each cell units, impurity diffusion regions, and gate electrodes is disposed above the block selecting transistor. Thus, capacitors used as memory cells located on an outer most area is prevented. Further, according to this embodiment, it is possible to improve the characteristics of memory capacitors by using a dummy upper electrode neighboring to the block selecting transistor.

The sixth preferred embodiment according to the present invention will now be described with reference toFIGS. 25 to 33. The sixth embodiment is a method of fabricating a semiconductor memory device according to the fifth embodiment, and show fabricating steps corresponding toFIG. 24.

As shown inFIG. 25, the first to third impurity diffusion regions351,355,377, the first isolation region353, the second isolation region357, the third isolation region358, the first to fourth gate352,354,356, and the passing word line359are formed on the semiconductor substrate350. Then, the insulating layer382is formed on the surface of those elements. The insulating layer382is formed by a LP-CVD method, and the insulating layer382is an interlayer insulating layer (e.g., BPSG layer). The surface of the insulating layer382is also flattened by a chemical mechanical polishing (CMP) method.

Then, the insulating layer382in the first metal plug368formation region, the second metal plug376formation region, and the first bit line plug378formation region are removed and a metal layer (e.g., tungsten) is buried into each formation region. Note, the polysilicon layer may be used instead of tungsten to be buried into each formation region.

Next, as shown inFIG. 26, the insulating layer400,401, lower electrode360,369, ferroelectric layer361,370, and upper electrode362,372, and the dummy upper electrode363is formed on the entire surface over the semiconductor substrate. In this step, a thin silicon nitride layer as the insulating layer400is first formed over the entire surface of the semiconductor substrate by using a Liquid Phase Chemical Vapor Deposition (LP-CVD) method. Then, the thin silicon oxide layer as the insulating layer401is formed by using either the LP-CVD method, Plasma CVD method, or an ordinary pressure CVD method.

Further, the TiN layer, Ti layer, Pt conductive layer are deposited as the lower electrodes360,369by using a sputter vaporized adhesion method in sequence. Then, the PZT layer as a ferroelectric layer361,370for the capacitor insulating layer is formed on the lower electrode. The Pt conductive layer as a capacitor upper electrode362,372, and the dummy upper electrode363is then formed by using the sputter vaporized adhesion method.

Then, as shown inFIG. 27, the upper electrode is formed in a predetermined shape by using the etching method. Thus, the first upper electrode362, the first dummy upper electrode363and the second upper electrode372are formed. As shown inFIG. 28, a first ferroelectric layer361, a second ferroelectric layer370, a first lower electrode360, and a second lower electrode369are formed in sequence from an upper direction by using etching with the RIE method.

Then, as shown inFIG. 29, the insulating layer382is formed by using the plasma CVD method toward the entire surface. The surface of the insulating layer382is then flattened by using CMP method. Next, as shown inFIG. 30, each region of the insulating layer382in the first one of the first layer of the metal layer365formation region, the second one of the first layer of the metal layer367formation region, the third one of the first layer375formation region, and the fourth one of the first layer371are removed.

As shown inFIG. 31, each region of the insulating layer382in the first metal contact364formation region, second metal contact366formation region, third metal contact373formation region, fourth metal contact374formation region is then removed by etching. Further, each region of the first ferroelectric layer361and the second ferroelectric layer370in the first metal contact364formation region and the fourth metal contact374formation region is removed by etching.

Then as shown inFIG. 32, each region of the insulating layer382in the first metal plug368formation region, the second metal plug376formation region, and bit line plug378formation region is removed by etching.

Next, as shown inFIG. 33, a metal layer (e.g., aluminum) is deposited. Then, the first metal contact364, the first one of the first layer of the metal layer365, the second metal contact366, the second one of the first layer of the metal layer367, the first metal plug368, the third metal contact373, the fourth metal contact374, the third one of the first layer of the metal layer375, the second metal plug376, bit line plug378, and the fourth one of the first metal layer379are formed.

The insulating layer382is then deposited on the entire surface and a region of the insulating layer382in the bit line contact formation region380is etched. Next, a metal layer is formed on the bit line contact formation region380. Then, the bit line contact380is formed. The bit line381is also formed over the fourth one of the first layer of the metal layer to connect the bit line contact380, and the structure shown inFIG. 24is achieved.

In the method of fabricating the offset type semiconductor memory device, the dummy upper electrode may be made by using the same steps as the normal electrode. Therefore, a highly integrated capacitor may be fabricated without micro loading effects.

It is further understood by those skilled in the art that the foregoing description are preferred embodiments of the disclosed devices and methods and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.