Analog-to-digital conversion with multiple kernels

An analog-to-digital conversion system includes at least two analog-to-digital conversion units configured to receive a plurality of analog signals and convert the analog signals to digital signals. The system further includes a delay unit including at least one delay circuit, wherein the analog-to-digital conversion system is configured to convey trigger signals to the analog-to-digital conversion units, and wherein at least one of the trigger signals is delayed via the at least one delay circuit.

FIELD

Embodiments of the present invention relate to a device that may be used in the domain of analog-to-digital conversion.

BACKGROUND

Analog-to-digital converters (ADCs) convert analog signals to digital signals. Innumerable embodiments have been known for many years and require no further explanation. Several types of measurements, e.g., “burst conversion” (i.e., several measurements in a short period of time, e.g., 100 ns, logarithmic distribution of measurements, etc.) are not supported by present ADCs without supplying several timer units that need to be specially synchronized. Power conversion topologies like solar inverters, switched-mode power supplies (SMPS) or DC-DC-converters use operating frequencies in a high megahertz range (amounting to, e.g., 30 MHz), which leads to a need for faster conversion sequences.

SUMMARY

A first embodiment relates to an analog-to-digital conversion system comprising at least two analog-to-digital conversion units for receiving a plurality of analog signals and converting the analog signals to digital signals. The system also comprises a delay unit comprising at least one delay circuit, wherein the analog-to-digital conversion system is configured to convey trigger signals to the analog-to-digital conversion units, wherein at least one of the trigger signals is delayed via the at least one delay circuit.

The analog-to-digital conversion unit may be implemented as and/or referred to as a kernel.

A second embodiment relates to an analog-to-digital converter comprising at least two analog-to-digital conversion units for receiving a plurality of analog signals and converting the analog signals to digital signals. The converter also comprises a delay unit comprising at least one delay circuit. The delay unit is configured to asynchronously trigger the analog-to-digital conversion units via the at least one delay circuit.

A third embodiment relates to an analog-to-digital conversion system comprising several analog-to-digital conversion units for receiving a plurality of analog signals and converting the analog signals to digital signals. The system also comprises a delay unit comprising several delay circuits. The analog-to-digital conversion system is configured to successively convey trigger signals to each of the analog-to-digital conversion units, wherein a delay between conveying the trigger signals is adjustable via the delay circuits of the delay unit.

A forth embodiment is directed to a microcontroller comprising at least one analog-to-digital converter as described herein.

A fifth embodiment relates to a method for converting analog signals into digital signals comprising converting a plurality of analog signals into digital signals based on trigger signals that are successively provided to several analog-to-digital conversion units, wherein the trigger signals are supplied by a delay unit via delay circuits.

A sixth embodiment is directed to an analog-to-digital conversion system comprising means for converting a plurality of analog signals into digital signals based on trigger signals that are successively provided to several analog-to-digital conversion units, and means for supplying the trigger signals.

DETAILED DESCRIPTION

The ADC described in greater detail can be part of a microcontroller. However, it is noted that there is no limitation to use the disclosed ADC converter: The microcontroller may comprise an arbitrary plurality of ADC converters of the type described herein, and ADC converters of the type described herein can also be utilized outside microcontrollers (i.e., in other devices or as separate ADC converter modules comprising one or more ADC converters).

An embodiment presented allows for sampling of different signals in different analog-to-digital conversion units, which are herein referred to as “kernels” of an analog-to-digital converter (ADC). For example, four different signals can be sampled in four or fewer different kernels.

A delay unit can be provided externally to the kernels, in particular within or separate to the ADC. The delay unit comprises delay elements that are added, e.g., within a synchronization or trigger path to the respective kernels. Hence, it is possible to provide a fast series of several (e.g., four in case of the four signals mentioned above) consecutive conversions within a time frame (also referred to as a time window). Advantageously, this conversion can be configurable in a flexible manner and it provides a very fast conversion capability. Due to its configurability, the distribution of measurements can be adjusted within the time frame, e.g., on a logarithmic or an exponential time scale.

This approach allows for new possibilities and applications utilizing various types of measurements in a fast and/or configurable way.

It is noted that using four different kernels and/or four signals is only one embodiment to illustrate the approach presented herein. The delay unit may comprise several stages that allow for a different number of delays and thus triggers and/or measurements in particular within the time frame. Basically, by supplying the delay unit (advantageously separate to at least two kernels), small and configurable amounts of delay between different trigger signals can be provided. The (at least partially) delayed trigger signals are, e.g., fed to the kernels of the ADC analog-digital-converter. By adjusting the delay of these triggers, the time for each kernel when to conduct a measurement can be flexibly adjusted, e.g., pre-configured. Such configuration can be a feature of the ADC and/or the microcontroller comprising at least one ADC.

FIG. 1shows a schematic diagram comprising several kernels101to104of an ADC100. In this embodiment, the kernel101is an ADC master kernel and the kernels102to104are ADC slave kernels. Each kernel101to104has, for example, eight analog input channels (referenced as “ch0” to “ch7”) and a trigger input105to108. Via the trigger input105to108, a conversion of a measurement is initialized for the kernels101to104, i.e. based on a trigger signal applied to the trigger input105to108. The respective kernel101to104then conducts an analog-to-digital conversion and provides the result of such conversion via, e.g., an output register (not shown inFIG. 1).

The ADC100further comprises a delay unit109, which is located separate to the kernels101to104. The delay unit109comprises several delay circuits110,111,112and121, which can be adjusted via a delay control113,114,115and120(applied, e.g., via a delay control unit, not shown inFIG. 1). In addition, the delay circuits110,111,112and121could each be skipped (indicated by a connection116to119, which could be controlled by the delay unit109).

It is noted that the delay unit109may be allocated outside of the ADC as well.

An output of the delay circuit121and a trigger signal123are fed to a logic unit122, which allows combining and/or masking the two input signals and supplies a trigger signal105to the kernel101and to the delay circuit110. The output of the delay circuit110provides a trigger signal106to the kernel102and to the delay circuit111. The output of the delay circuit111feeds a trigger signal107to the kernel103and to the delay circuit112. The output of the delay circuit112is fed to the kernel104and to the delay circuit121.

The last trigger108can be fed back via the delay circuit121(or directly) towards the kernel101for daisy chaining and for a repetition of the sequence.

As an option, electronic switches124to127can be provided connecting the triggers signals105to108and the kernels101to104. Hence, the trigger signals105to108can be disabled for at least one of the kernels101to104, which is to be excluded from the conversion sequence. The switches124to127can be located within or external to the delay unit109.

Hence, the delay unit109, which in one embodiment is located outside of any kernel101to104, provides delayed trigger signals105to108in a configurable manner, e.g., advantageously as multiples of clock cycles.

The master kernel does not have to be a fixed kernel, i.e. all kernels are able to receive delayed triggers. Hence, each of the kernels can act as master or slave kernel. Therefore, the order of the kernels can be flexibly selected.

In addition, each delay provided by the delay circuits110,111,112and121can be flexibly configured. For example, the amount of delay introduced by the delay circuits110,111,112and121may each be the same or may be partially different.

It may be advantageous to determine the amount of delay in multiples of a clock cycle (e.g., multiples of 8.33 ns). The actual delays selected may in one embodiment be based on a sensor and on pin impedances as well as a current source loading the pin and/or sensor after the sampling process has been conducted. The individual setup of the amounts of delay may depend on a particular use case and can be set individually for each type of implementation.

FIG. 2shows a schematic diagram of an example implementation of a delay unit209supplying trigger signals205to208to several kernels201to204. An ADC200may comprise the kernels201to204and the delay unit209.

The delay unit209comprises a selection unit216with a master kernel selection unit215, several delay circuits210to213and a delay control unit214. The output of the delay circuits210to213is conveyed as trigger signals205to208(also referred to as “Trigger0” to “Trigger3”) to the kernels201to204, respectively.

The delay control unit214may convey enable signals to electronic switches217to220, which may be used to bypass trigger signals otherwise conveyed to at least one of the kernels201to204. The switches217to220may be implemented as an option.

It is also an option to change the configuration of the selection unit216during runtime. For example, the first initial trigger could be TR0, then the selection unit216changes to TR1as initial trigger, then to TR2, then to TR3and then again to TR0, etc. Of course, the order is just an example and various successions could be used accordingly.

The kernel201(also referred to as “ADC KERNEL0” or “MASTER” kernel) obtains the trigger signal205“Trigger0” from the delay unit209and supplies a signal TR0to the selection unit216. The kernel202(also referred to as “ADC KERNEL1” or “SLAVE0” kernel) obtains the trigger signal206“Trigger1” from the delay unit209and supplies a signal TR1to the selection unit216. The kernel203(also referred to as “ADC KERNEL2” or “SLAVE1” kernel) obtains the trigger signal207“Trigger2” from the delay unit209and supplies a signal TR2to the selection unit216. The kernel204(also referred to as “ADC KERNEL3” or “SLAVE2” kernel) obtains the trigger signal208“Trigger1” from the delay unit209and supplies a signal TR3to the selection unit216.

Any of the signals TR0to TR3can be used by the selection unit216to map it as an initial trigger signal conveyed to any of the kernels201to204and then select the remaining kernels based on the delays accordingly after that initial trigger signal. According to the example shown inFIG. 2, the signal TR0is the initial trigger signal (also referred to as master signal) for the kernel201. The trigger signal “Trigger0” from the delay circuit210is a trigger signal without delay, i.e. the delay unit is bypassed for the master kernel201. Hence, the signal TR0is used as the initial trigger signal; the first kernel to be triggered via the signal205based on the initial trigger signal is the kernel201with no delay. Next, the kernel202is triggered via the signal206after a delay set by the delay circuit211. Then, the kernel203is triggered via the signal207after a delay set by the delay circuit212and finally the kernel204is triggered via the signal208set by the delay circuit213. After that, a new burst conversion cycle can be started. Burst conversions may be chained after one another by using the last trigger as first trigger input.

It is also an option to configure the delay units in such a way that all kernels convert at the same time or substantially at the same time. Hence, the trigger signal Trigger2does not have to come after the trigger signal Trigger1(because of the varying amounts of delay). For example, in an embodiment all kernels may start at the same time, in another embodiment, a trigger signal may not be generated (it may be skipped) and in a further embodiment, e.g., the trigger signal Trigger2may be issued before the trigger signal Trigger1thus commencing conversion of the kernel203before the kernel202. In addition, aspects of these embodiments could be combined in a particular use case.

FIG. 3shows a conversion sequence without any delay, i.e. without the solution presented herein for comparison purposes. The trigger signals301trigger the MASTER kernel as well as the other kernels KERNEL1to KERNEL3in parallel. An analogue channel—for example channel2“ch2”—is converted into a digital signal, the conversion being processed before reaching idle time for each of the kernels.

FIG. 4shows an example conversion sequence with different delays according to the proposal set forth herein. KERNEL0corresponds to the kernel201and KERNEL1to KERNEL3correspond to kernels202to204shown inFIG. 2.

The trigger401corresponds to the trigger signal205“Trigger0” supplied to the KERNEL0201(not introducing any delay by the delay circuit210). KERNEL1202is triggered with a delay402introduced by the delay circuit211, which supplies the delayed signal Trigger1206. Accordingly, KERNEL2203is triggered with a delay403introduced by the delay circuit212, which supplies the delayed signal Trigger2207. Finally, KERNEL3204is triggered with a delay404introduced by the delay circuit213, which supplies the delayed signal Trigger3208.

Example Embodiment: Burst Measurement of a Signal

The solution presented allows utilizing channels of an ADC in a flexible manner. According to the example embodiment shown inFIG. 5, a sensor501is connected to two pins508and509of a microcontroller502. The microcontroller502comprises an ADC503with four kernels504to507. Pin508is connected to the kernels504,505and pin509is connected to the kernels506,507.

FIG. 6shows a timing diagram visualizing a burst conversion provided by the arrangement ofFIG. 5. The sensor501supplies a sensor voltage606to the microcontroller502. Based on a trigger signal601, the kernels504to507subsequently convert the analog measurements602to605into digital signals. This can be achieved after the trigger signal601within a time frame of, e.g., 100 ns. In the example shown inFIG. 6, the delays between the conversions can be set (substantially) uniformly distributed over time.

Such scenario can be used in power converters, e.g., in the domain of motor control algorithms.

By utilizing a burst conversion, i.e. subsequent measurements of analog signals in a very short period of time, it is possible to ensure a good reproduction of the analog signal606and thus an accurate control loop can be provided based on such samples of the analog signal606.

For example, the digital representations of the analog measurements602to605can be used for generating an averaging value (in addition to other filtering means) from these measurements, in particular for additional noise rejection purposes.

In a particular use case, a trigger signal could be provided, e.g., by a timer unit. In some scenarios it may be beneficial to add some delay before sampling the signal. One reason could be a sensor that requires a few microseconds to provide signals that are suitable for sampling. Hence, a first kernel could be configured such that it does not convert the signal, but a first delay circuit could be used to produce the amount of delay required for the sensor to settle to a stable state. In addition or as an alternative, a delay circuit could be provided for the initial trigger signal as well; this delay circuit may in other cases be set to zero or be cut short (skipped), but for this example scenario it can be set to a value other than zero to give the sensor time to settle.

Example Embodiment: Measurement via Four Sensors in a Short Time Frame Window

FIG. 7shows an example block diagram with four sensors703to706being connected to kernels707to710of an ADC702within a microcontroller701.

FIG. 8shows a timing diagram visualizing a conversion of measurements provided by the four sensors703to706according to the arrangement ofFIG. 7. The sensor703provides an analog voltage signal801, the sensor704provides an analog voltage signal802, the sensor705provides an analog voltage signal803and the sensor706provides an analog voltage signal804.

Based on a trigger signal805, the kernel707conducts a conversion of the measurement809. After a delay806, a trigger signal813causes the kernel708to conduct a conversion of the measurement810. After a delay807, a trigger signal814causes the kernel709to conduct a conversion of the measurement811and after a delay808, a trigger signal815causes the kernel710to conduct a conversion of the measurement812.

The conversions of the measurements809to812from the various sensors703to706can be conducted within a time window amounting to, e.g., 100 ns. The delay between the conversions may be constant or variable. In one embodiment, the delay may amount to 25 ns.

As an example embodiment, the kernels707and709can be based on the same kernel hardware; the same may apply for the kernels708and710. Alternatively, the kernels can be implemented in separate hardware portions.

The solution can be advantageously utilized in combination with applications that require, e.g., a compensation of delay or phase shift, in particular based on measurement delay. Hence, a useful and efficient tool for calibration can be implemented based on the suggested solution.

Example Embodiment: Logarithmic or Exponential Conversion Sequence

As indicated, the amounts of delay for issuing trigger signals that cause the respective kernel(s) to conduct conversions may be set and/or adjusted in a fixed or flexible manner.

FIG. 9shows an example graph of an analog voltage signal905of logarithmic shape over time. Based on a trigger signal901, a first conversion of the measurement K0is conducted. After a delay902, a next conversion of the measurement K1is conducted and after a subsequent delay903a conversion of the measurement K2is conducted. Next, after a delay904a conversion of the measurement K3is conducted. The amounts of delay increase exponentially from the delay902towards the delay904in this embodiment.

Of course, delays may be adjusted flexibly based on a particular use case scenario, e.g., linearly, logarithmically, based on a predefined values or any kind of distribution or function.

Such flexibly adjusted or adjustable delays can be used during start-up phases of machines or power converters and/or for sensor calibration purposes. This solution is in particular useful as the advantage of such measurement distribution increases with the number of kernels available in the ADC, because more conversions can be done and a better tracking of the signal can thus be achieved. For example, the “last” trigger could be fed back to close the loop, which results in an sequencing/sampling solution with an specific shape being independent from a particular trigger signal.