Pixel test in a liquid crystal on silicon chip

An example embodiment includes a continuity testing method of a pixel in a liquid crystal on silicon integrated circuit. The method includes writing a first voltage to a pixel. The pixel is isolated and a wire that is selectively coupled to the pixel is discharged. The method also includes enabling a sensing amplifier configured to sense voltage on the wire. The pixel is electrically coupled to the wire and a resultant voltage on the wire is sensed.

BACKGROUND

1. Field of the Invention

Embodiments described herein relate generally to optical switches. More particularly, example embodiments relate to liquid crystal on silicon integrated circuits (LCOS ICs) that may be included into optical switches.

2. Related Technology

Signal-carrying light may be multiplexed onto an optical fiber to increase the capacity of the optical fiber and/or enable bidirectional transmission. Optical switches are generally used to multiplex, de-multiplex, or dynamically route a particular channel of the signal-carrying light. One type of optical switch is a wavelength selector switch (WSS) which routes the particular channel based on the wavelength of the particular channel.

In some WSS, liquid crystal on silicon (LCOS) technology is used to create a display engine that deflects a wavelength of the particular channel. In LCOS technology, liquid crystals may be applied to a surface of a silicon chip. The silicon chip may be coated with a reflective layer. For example, the reflective layer may include an aluminized layer. Additionally, in LCOS technology, the display engine may include multiple pixels. Through introduction and alteration of electrical voltage applied to the pixels, the pixels create an electrically controlled grating that routes the particular channel in a deflected direction.

BRIEF SUMMARY OF SOME EXAMPLE EMBODIMENTS

Embodiments described herein relate generally to optical switches. More particularly, example embodiments relate to liquid crystal on silicon integrated circuits (LCOS ICs) that may be included in optical switches.

An example embodiment includes a continuity testing method of a pixel in a LCOS IC. The method includes writing a first voltage to a pixel. The pixel is isolated and a wire that is selectively coupled to the pixel is discharged. The method also includes enabling a sensing amplifier configured to sense voltage on the wire. The pixel is electrically connected to the wire and a resultant voltage on the wire is sensed.

Another example embodiment includes a pixel continuity testing system on a LCOS IC. The testing system includes a first pixel, a first wire, a yank structure, and a sensing amplifier. The first wire is selectively coupled to the first pixel via a first pixel switch. The yank structure includes a yank up switch configured to couple the first pixel to a first voltage source and a yank down switch configured to couple the first wire to a second voltage source. The sensing amplifier is configured to be selectively coupled to the first wire via a sensing amplifier switch and configured to sense a first resultant voltage on the first wire following the first pixel being coupled to the first voltage source.

Another embodiment includes a LCOS IC. The LCOS IC includes multiple pixels, a yank structure, and multiple sensing amplifiers. The pixels are arranged in rows of pixels and in columns of pixels, the columns of pixels are electrically coupled via column wires. The yank structure includes a yank up switch configured to couple the columns of pixels to a first voltage source and a yank down switch configured to couple the columns of pixels to an electrical ground. Each of the sensing amplifiers is configured to sense a resultant voltage on at least one of the column wires.

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

Embodiments described herein relate generally to optical switches. More particularly, example embodiments relate to liquid crystal on silicon integrated circuits (LCOS ICs) that may be included in optical switches. An example embodiment includes a pixel continuity testing system for a LCOS IC. The testing system includes a wire that is selectively coupled to a pixel via a pixel switch. The wire is also selectively coupled to a sensing amplifier via a sensing amplifier switch. A yank up switch couples the pixel to a first voltage. The yank down switch couples the wire to a second voltage. The sensing amplifier senses a resultant voltage on the first wire when the wire is coupled to the first pixel. Some additional example embodiments of the present invention will be explained with reference to the accompanying drawings.

FIG. 1is a block diagram of an example liquid crystal on silicon (LCOS) system100in which the embodiments disclosed herein may be implemented. Generally, the LCOS system100writes images used to select wavelength or channels of optical signal-carrying light (optical signals). The LCOS system100can include a driver chip such as a field-programmable gate array (FPGA)102that controls the liquid crystal on silicon integrated circuit (LCOS IC)124. To control the LCOS IC124, the FPGA102communicates commands, synchronization signals, digital data, varying analog and/or digital signals, or some combination thereof. Additionally, the FPGA102may receive various analog and/or digital data signals, output synchronization signals, etc. from the LCOS IC124.

The FPGA102is an integrated circuit (IC) with logic blocks, which may be configured to perform one or more control functions of the LCOS IC124. The FPGA102may be configured and/or programmed after the LCOS system100is delivered to a user or following manufacturing of the FPGA102. In some alternative embodiments the driver chip may include an application-specific integrated circuit (ASIC) or another suitable driver chip having substantially equivalent capabilities of the FPGA102.

The FPGA102may include a digital port142which may communicate with a demultiplexing module116included in the LCOS IC124. An example of the digital port142may include a low-voltage differential signal (LVDS) pair. The FPGA102may communicate digital data through the digital port142to the demultiplexing module116. InFIG. 1, arrow132represents the communication of digital data to the demultiplexing module116. Digital data may include, but is not limited to, a digital clock signal that may be used as a synchronization signal and digital image data for one or more pixels126A-126I (generally, pixel126or pixels126) included in the LCOS IC124. The digital image data includes a digital representation of an image the LCOS IC124displays. The digital image data may be formatted as 6 bit per pixel, 7 bit per pixel, or 8 bit per pixel, for example. The digital data, or some portion thereof, may be communicated to one or more column drivers112A-112C (generally, column driver112or column drivers112) which may then be communicated to the pixels126.

Some embodiments of the FPGA102may include multiple digital ports142and/or the LCOS IC124may include multiple demultiplexing modules116. In embodiments in which the FPGA102includes multiple digital ports142, the FPGA102may communicate a specific or a set amount of digital data through each of the digital ports142in parallel. For example, in some embodiments, the FPGA102includes thirty-two digital ports142. Each of the thirty-two digital ports142may communicate digital image data for a bank of pixels126, including sixty columns of pixels126.

The FPGA102may also include a command port144that communicates commands to a command decoder108. InFIG. 1, arrow136represents the communication of commands to the command decoder108. The commands may include one or more actions and/or functions for the LCOS IC124to perform. For example, a command may include timing of operations to write a row of the pixels126. A timing command may be controlled by the FPGA102via the command port144. Additionally or alternatively, a command may include a digital clock signal that may be used as a synchronization signal. In some embodiments, the FPGA102may include multiple command ports144.

The command decoder108and the command port144may also communicate additional signals. InFIG. 1, double-ended arrow134represents the communication of additional signals between the command port144and the command decoder108. For example, the additional signals may include, but are not limited to, an auxiliary digital data signal, a reset signal, data out signals from the LCOS IC124, and output clock signals from the LCOS IC124. The reset signal and the auxiliary digital data signal may include a digital clock signal as a synchronization signal. The data out signals and the output clock signals may communicate information regarding synchronization and operational status of the LCOS IC124to the FPGA102.

The FPGA102may also include an analog module104that communicates analog signals with an LCOS analog module118. InFIG. 1, the double-ended arrow146represents the communication between the analog module104and the LCOS analog module118.

The FPGA102may also communicate a digital ramp signal to a digital to analog converter (DAC)106. InFIG. 1, arrow138represents the communication of the digital ramp signal to the DAC106. The DAC106receives the digital ramp signal and outputs an analog ramp signal related to the digital ramp signal. The digital ramp signal is a binary number that represents and is proportional to an analog voltage of the analog ramp signal output from the DAC106.

In some embodiment, the digital ramp signal includes a series of binary numbers that are converted to a monotonically varying voltage which ramps from an initial voltage to a final voltage. The term “ramp” refers to the behavior of incrementally varying at a defined rate. That is, in some embodiments, an initial binary number of the digital ramp signal is converted to an initial voltage which may be as high as about 12 volts (V). The digital ramp signal may subsequently include binary numbers resulting in an analog ramp signal that monotonically steps down to a final voltage. Alternatively, an initial binary number of the digital ramp signal can be converted to an initial voltage which may be as low as 0 V. The digital ramp signal may subsequently include binary numbers that result in voltages that monotonically step up to a final voltage. In some embodiments, each step may be a predetermined time interval during which the digital ramp signal includes a binary number that results in a predetermined change in voltage. Additionally, the digital ramp signal may vary according to a gamma curve, which can correct for nonlinear optical response of LCOS material.

The digital ramp signal is not limited to the series of binary numbers that result in the monotonically ramping voltage. The digital ramp signal can include a series of binary numbers that result in multiple patterns or progressions of voltages. For example, the digital ramp signal can include binary numbers that result in a set of increasing voltages and then a set of decreasing voltages, vice versa, or some other suitable pattern resulting in voltages covering the range of voltages to drive the pixels126of the LCOS IC124A.

As stated above, the DAC106converts the digital ramp signal to an analog ramp signal representative of the binary number included in the digital ramp signal. Accordingly, the analog ramp signal is an analog representation of the digital ramp signal. The analog ramp signal may exhibit incrementally varying behavior equivalent or related to the digital ramp signal. Thus, in some embodiments, the analog ramp signal monotonously varies from the initial voltage to the final voltage, supplying a varying voltage signal to the pixels126. More specifically, the analog ramp signal supplies target voltages to the pixels126. The target voltages are defined voltages within the inclusive range of the initial voltage to the final voltage of the analog ramp signal. The LCOS IC124A operates, at least partially, through driving the target voltages to the pixels126.

A brightness of a pixel126may be determined by the magnitude of a target voltage supplied to the pixel126. Thus, the brightness of the pixel126is controlled by driving the analog ramp signal during the time in which the target voltage of the analog ramp signal is equal to the voltage corresponding to a desired brightness. Pixels126may include multiple levels of brightness. For example, in some embodiments the pixel126can be programmed to display 256 or more levels of brightness. The process of supplying the pixels126with target voltages may be referred to as “writing an image.”

Additionally, the analog ramp signal may monotonically vary from the initial voltage to the final voltage once per writing cycle of the pixels126. The initial voltage and the final voltage may periodically change, interchange, or turn around. That is, in a first writing cycle, the final voltage may be greater than the initial voltage. In a second writing cycle, the initial voltage may be greater than the final voltage. In a third cycle, the final voltage may again be greater than the initial voltage. The initial voltage and the final voltage may continue to change in this pattern.

To determine when to supply the analog ramp signal to the pixels126, the FPGA102may also communicate a ramp counter enable signal to a ramp counter114included in the LCOS IC124. InFIG. 1, arrow140represents the communication of the ramp counter enable signal to the ramp counter114. Generally, the ramp counter114receives the ramp counter enable signal from the FPGA102, which enables or turns on the ramp counter114. Once enabled, the ramp counter114counts or tracks the number of predetermined time intervals of the digital ramp signal that have occurred since receiving the ramp counter enable signal. The number of predetermined time intervals of the digital ramp signal may be equivalent and/or related to the number of predetermined time intervals of the analog ramp signal. More specifically, in some embodiments, the digital ramp signal may include a ramp clock signal. The ramp clock signal may act as a synchronization signal. The ramp counter114may track and/or count the number of predetermined time intervals included in the ramp clock signal following the reception of the ramp counter enable signal. The ramp counter114may output or otherwise make available a ramp step signal indicating the number of predetermined time intervals.

The ramp counter114may be coupled to the column drivers112. The ramp counter114may communicate the ramp step signal to the column drivers112. Thus, the ramp counter114and the ramp step signal may be used to determine the voltage of the analog ramp signal at a specific time. That is, the voltage of the analog ramp signal may be calculated if the initial voltage resulting from an initial binary number of the digital ramp signal, the predetermined voltage change per predetermined time interval, and the ramp step signal are known.

Referring back to the DAC106, the analog ramp signal exiting the DAC106, which is indicated by the line148, enters an external buffer150. The external buffer150may buffer the DAC106and/or the FPGA102from the LCOS IC124. From the external buffer150, the analog ramp signal enters the LCOS IC124and supplies the column drivers112, which then supplies the pixels126or some subset thereof included in an array core120.

Each of the pixels126may include a NMOS/PMOS complementary switch, a metal insulator-metal (MIM) capacitor, and a piece of top-layer metal. The complementary switch may enable linear transfer of voltage supplied by the column drivers112to enter the pixel126. The MIM capacitor may be included to provide enough capacitive storage to limit charge leakage during a field time. In the depicted embodiment, the array core120includes nine pixels126. However, this depiction is not limiting. The ellipses are included to illustrate that the array core120may include more than nine pixels126. In some embodiments, the array core120may be separated into banks of columns which banks of columns may be coupled to one of the digital port142(described above).

In this and other embodiments, the array core120includes the pixels126that may be organized into columns and rows. The pixels126in each row may be electrically coupled to a row decode110via a row wire128A-128C (generally, row wire128or row wires128). The row decode110may receive commands from the command decoder108. Specifically, the row decode110may receive commands related to activation of the pixels126in a row. The row decode110may then communicate the command related to activation through a row enable amplifier122A-122C (generally, row enable amplifier122or row enable amplifiers122), along one of the row wires128to the pixels126in the row. The activation signal enables or triggers the receiving pixels (i.e., the pixels126in the row coupled to the row enable amplifier122) to become activated such that the pixels126may receive one or more signals supplied by one of the column drivers112.

In some embodiments, the pixels126may be activated row by row. That is, the first row enable amplifier122A communicates the activation signal to the first pixel126A, the second pixel126B, and the third pixel126C through the first row wire128A. After the first pixel126A, the second pixel126B, and the third pixel126C are written, the second row enable amplifier122B then communicates the activation signal to the fourth pixel126D, the fifth pixel126E, and the sixth pixel126F through the second row wire128B.

The pixels126in each column may be electrically coupled to one of the column drivers112via one or more column wires130A-130C (generally, column wire130or column wires130). Each of the column drivers112supplies one or more signals to the pixels126in a column via the column wire130.

FIG. 2is a block diagram of a pixel continuity testing system (testing system)200which may be integrated into the LCOS system ofFIG. 1. Generally, the testing system200may perform a continuity test on pixels202A-202D (generally, pixel202or pixels202). A continuity test may detect, for example, pixels202that may be damaged and/or nonfunctional. The testing system200depicted inFIG. 2includes four pixels202: a first pixel202A, a second pixel202B, a third pixel202C, and a fourth pixel202D. However, the testing system200inFIG. 2represents a simplified version of the testing system200. The principles disclosed with respect to the testing system200may be scaled to be integrated into a testing system including more than four pixels202.

In general, the pixels202may be substantially similar to and/or correspond to the pixels126described with respect toFIG. 1and may be essentially identical to one another. The pixels202may be organized into columns and rows with a yank wire236, row wires228A and228B, and column wires222A and222B. The row wires228A and228B are substantially similar to the row wires128and the column wires222A and222B are substantially similar to the column wires130discussed with reference toFIG. 1. The first pixel202A and the third pixel202C may be selectively coupled to a first column wire222A and the second pixel202B and the fourth pixel202D may be selectively coupled to a second column wire222B. Each pixel202is selectively coupled to one of the column wires222A or222B through operation of corresponding pixel switches218A-218D. The pixel switches218A-218D may be operated by one or more row enable amplifiers230A and230B positioned at an end of each of the row wires228A and228B.

As depicted inFIG. 2, the row enable amplifiers230A and230B are operational amplifiers. However, this depiction is not meant to be limiting. The row enable amplifiers230A and230B may be switches or some other suitable structure, for instance.

For example, the first pixel202A may be coupled to the first column wire222A by a first row enable amplifier230A communicating a signal to close a first pixel switch218A. Likewise, the fourth pixel202D may be isolated from the second column wire222B by a second row enable amplifier230B communicating a signal to open a fourth pixel switch218D. In a similar fashion, the second pixel202B and the third pixel202C may be selectively coupled to the first column wire222A and the second column wire222B, respectively. As used herein the term “open” refers to a state of a switch or amplifier in which the flow of electricity stops. Conversely, the term “closed” refers to a state of a switch or amplifier in which the flow of electricity is enabled.

The yank wire236selectively couples the first column wire222A and the second column wire222B to a yank structure232. More specifically, operation of a first column yank switch226A selectively couples the yank structure232to the first column wire222A and a second column yank switch226B selectively couples the yank structure232to the second column wire222B. Some additional details of the yank structure232are provided below.

In some embodiments, the testing system200may also include column drivers204A and204B which may be similar to and/or correspond to the column drivers112described with respect toFIG. 1. That is, the column drivers204A and204B may write images to one or more of the pixels202. A first column driver204A may be selectively coupled to the first column wire222A via a first column driver switch224A and a second column driver204B may be selectively coupled to the second column wire222B via a second column driver switch224B. Accordingly, the column drivers204A and204B may be isolated from the column wires222A and222B by opening the column driver switches224A and224B.

The testing system200may also include one or more sensing amplifiers300A and300B (generally, sensing amplifier300or sensing amplifiers300). A first sensing amplifier300A may be selectively coupled to the first column wire222A via a first sensing amplifier switch220A. For example, the first sensing amplifier300A may be isolated from the first column wire222A by opening a first sensing amplifier switch220A. Additionally, the testing system200may include a second sensing amplifier300B that may be selectively coupled to the second column wire222B via a second sensing amplifier switch220B. For example, the second sensing amplifier300B may be isolated from the second column wire222B by opening a second sensing amplifier switch220B.

In some embodiments, instead of including the second sensing amplifier300B, the first sensing amplifier300A may also be selectively coupled to the second column wire222B. In these and other embodiments, the testing system200may include an additional sensing amplifier switch (not shown) that isolates the first sensing amplifier300A from the second column wire222B.

FIG. 3is a block diagram of an example sensing amplifier300that may be implemented in the testing system200depicted inFIG. 2. With combined reference toFIGS. 2 and 3, the sensing amplifier300may include the sensing amplifier switch220, which may selectively couple the sensing amplifier300to one of the column wires222A or222B. The sensing amplifier switch220is depicted in bothFIGS. 2 and 3.

Referring toFIG. 3, the sensing amplifier300may generally include a differential amplifier sensing circuit302, a sample switch304, and one or more inverting amplifiers310. Generally, the sensing circuit302obtains a voltage at an input308when the sample switch304in a feedback leg is closed. The sensing circuit302amplifies and charges the voltage to trigger the inverting amplifiers310. When the sample switch304is open, the sensing circuit302becomes a comparator circuit, thereby resetting the sensing circuit302.

With combined reference toFIGS. 2 and 3, the sensing amplifier300may be selectively coupled to one of the column wires222A or222B via a sensing amplifier switch220A or220B. With the sensing amplifier switch220A or220B closed, the column wire222A or222B is electrically coupled to the input308of the sensing circuit302. When the sample switch304closes, the sensing amplifier300can sense a voltage on the column wire222A or222B.

In some embodiments, the sensing amplifier300may include a trigger (not shown) including a programmable threshold. The threshold of the trigger may accommodate for process, voltage, and temperature (PVT) variation. Additionally or alternatively, in some embodiments, the capture time may be programmable.

Referring back toFIG. 2, the yank structure232may include a yank down switch210and a yank up switch212that selectively couple the column wires222A and222B to a second voltage source214and a first voltage source206, respectively. To couple the first column wire222A to the second voltage source214, the yank down switch210and a first column yank switch226A may be closed. When the first column wire222A is coupled to the second voltage source214, the rest of the testing system200may be isolated from the second voltage source214. Specifically, the second column yank switch226B, the first pixel switch218A, the third pixel switch218C, the first sensing amplifier switch220A, and the first column driver switch224A may be open.

Likewise to couple the second column wire222B to the second voltage source214, the yank down switch210and the second column yank switch226B may be closed. When the second column wire222B is coupled to the second voltage source214, the rest of the testing system200may be isolated from the second voltage source214. Additionally, the first column yank switch226A, the second pixel switch218B, the fourth pixel switch218D, the second sensing amplifier switch220B, and the second column driver switch224B may be open.

In a similar fashion, through operation of the yank up switch212and the first and second column yank switches226A and226B, the column wires222A and222B may be selectively coupled to the first voltage source. The first voltage source206may be coupled to the first column wire222A by closing the yank up switch212and the first column yank switch226A. Likewise, the first voltage source206may be coupled to the second column wire222B by closing the yank up switch212and the second column yank switch226B. In either configuration, e.g., the first voltage source206being coupled to the first column wire or second column wire222A or222B, the rest of the testing system200may be isolated from the first voltage source206.

In some embodiments, the first voltage source206may be greater than the second voltage source214. For example, in some embodiments, the first voltage source206may be approximately equal to 10 V and the second voltage source214may be an electrical ground.

The testing system200includes the yank structure232and the column yank switches226A and226B to sequentially couple the column wires222A or222B and the pixels202to the first voltage source206and the second voltage source214. By sequentially coupling the column wires222A or222B and the pixels202to the first voltage source206and the second voltage source214, a resultant voltage (not shown) may be produced on the column wires222A and222B. The resultant voltage may be sensed by the sensing amplifier300. The resultant voltage may be an indication of continuity of the pixels202. A pixel continuity test may include sensing and analyzing the resultant voltage for each of the pixels202. In the testing system200, by changing the states of the switches (e.g.,212,210,226A,226B,218A-218D,220A,220B, and224A-224D) described above in a particular sequence, the resultant voltages for each of the pixels202may be sensed by the sensing amplifiers208A and208B.

Additionally, in some embodiments, the testing system200may include a scan register216. The scan register216may be selectively coupled to the first sensing amplifier208A and the second sensing amplifier208B. When coupled to the first sensing amplifier208A or the second sensing amplifier208B, the scan register216may record or store the resultant voltages sensed by the sensing amplifiers208A and208B. In alternative embodiments, the resultant voltages may be fed to a remote storage component.

FIG. 4is an example signal diagram400depicting an example sequence of the testing system200depicted inFIG. 2. With combined reference toFIGS. 2 and 4, the signal diagram400depicts a sequence to sense a resultant voltage of the first pixel202A. In the depicted embodiment, the first pixel202A is tested; however, through a similar sequence any of the pixels202may be tested.

InFIG. 4, there are five signal lines representing the states of various switches in the testing system200depicted inFIG. 2and the sensing amplifier300depicted inFIG. 3. Also, inFIG. 4there are thirteen dashed, vertical lines402-426representing time included in the example sequence. The state of the switch is closed when the signal line is high and the state of the switch is open when the signal line is low. Specifically, with combined reference toFIGS. 2-4, a first signal428represents the state of the yank down switch210. A second signal430represents the state of the sample switch304. A third signal432represents the state of the first sensing amplifier switch220A. A fourth signal434represents the state of the first pixel switch218A. A fifth signal436represents the state of the yank up switch212.

Throughout the example sequence, the first column yank switch226A remains closed and the state of the first pixel switch218A is controlled by the row enable amplifier230A. The remaining switches (e.g.,224B,218B,218D,220B,226B,218C, and224A) depicted inFIG. 2remain open during the example sequence.

Beginning at a first time426, the yank down switch210is closed, the sample switch304is open, the first sensing amplifier switch220A is open, the first pixel switch218A is open, and the yank up switch212is open.

At a second time424, the first sensing amplifier switch220A closes. Thus, at time424the first column wire222A and the first sensing amplifier208A are coupled to the second voltage source214. In embodiments in which the second voltage source214is an electrical ground, the first column wire222A is grounded.

At times422-416, a series of switches change state that results in an image being written to the first pixel202A. First, at a third time422the yank down switch opens. At a fourth time420, the first sensing amplifier switch220A opens. At a fifth time418, the first pixel switch218A closes. At a sixth time416, the yank up switch closes. In this configuration, a voltage from the first voltage source206is applied through the yank up switch212to the first pixel202A. The voltage applied to the first pixel202A writes the image to the first pixel202A.

Additionally, in some embodiments, because the first row enable amplifier230A controls the second pixel switch218B, the first voltage source206may be coupled to the second pixel202B as well. The image written to the first pixel202A may be identical to the image written to the second pixel202B.

At times414-412a series of switches change state that isolate the first pixel202A, and thereby store charge in the first pixel202A. At a seventh time414, the first pixel switch218A opens. At an eighth time412, the yank up switch212opens. In this configuration, the first pixel202A is isolated from the first column wire222A.

At times408-410a series of switches change state that couple the first column wire222A to the second voltage source214. At a ninth time410, the yank down switch210closes. At a tenth time408, the first sensing amplifier switch220A closes. Again, in this configuration, the first column wire222A and the first sensing amplifier208A are coupled to the second voltage source214. In embodiments in which the second voltage source214is an electrical ground, in this configuration the first column wire222A is discharged.

At an eleventh time406, the yank down switch210opens. At a twelfth time404, the sample switch304closes such that the first sensing amplifier208A may sense the voltage on the first column wire222A. At a thirteenth time402, the first pixel switch218A closes, coupling the first pixel202A to the first column wire222A. The charge stored in the first pixel202A is shared with the first column wire222A. The first sensing amplifier208A can sense a resultant voltage on the first column wire222A. In some embodiments, the pixels202may include a pixel capacitance, which may be different from a column wire capacitance. A difference in capacitance may result in the charge sharing discussed above.

FIG. 5is a flowchart of an example pixel continuity testing method (method)500. The method500can be implemented with the testing system200ofFIG. 2in some embodiments. One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Furthermore, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the disclosed embodiments.

The method500may begin at502by writing a first voltage to a pixel. In some embodiments, writing the first voltage to the pixel may include closing a yank up switch coupled to a first voltage source.

At504, the method500may include isolating the pixel. Isolating the pixel may include opening a pixel switch, which may be controlled by an enable amplifier. By isolating the pixel, the first voltage written to the pixel may be stored as a charge in the pixel.

At506, the method500may include discharging a wire that is selectively coupled to the pixel. Discharging the wire may include closing a yank down switch coupled to an electrical ground. In some embodiments, the wire may be a column wire that electrically couples to the pixel and a second pixel. In this and other embodiments, the wire may be selectively coupled to the pixel and the second pixel via the pixel switch and a second pixel switch, respectively.

At508, the method500may include enabling a sensing amplifier that senses voltage on the wire. The sensing amplifier may include a sensing circuit that includes a trigger with a threshold. In some embodiments, the threshold for the trigger of the sensing amplifier may be programmed to compensate for process, voltage, and temperature (PVT) variation. Additionally or alternatively, the sensing circuit may include a capture time that holds the voltage sensed by the sensing amplifier. In some of these embodiments, the capture time may be programmed.

At510, the method500may include electrically connecting the pixel to the wire and connecting the pixel to the wire may include closing the pixel switch such that the charge stored in the pixel may be shared with the wire. The charge sharing may be a result of differences between a pixel capacitance of the pixel and a wire capacitance of the wire. For example, in some embodiments, the pixel capacitance is less than the wire capacitance.

At512, the method500may include sensing a resultant voltage on the wire. The resultant voltage may include the charge shared between the pixel and the wire. The resultant voltage may indicate proper continuity of the pixel. In some embodiments, one sensing amplifier may be selectively coupled to multiple columns and/or multiple pixels in some sequence. This may enable the one sensing amplifier to sense the resultant voltage for the multiple pixels. In some embodiments including one sensing amplifier, the method500may be performed for each of the pixels individually.

Additionally, in some embodiments, a LCOS IC may include a system such as the testing system200ofFIG. 2that implements the method500. The LCOS IC may record or store the resultant voltage in a scan register, for instance. Alternatively, the resultant voltage may be fed off the LCOS IC and/or stored remotely.