Relaxation oscillator

A relaxation oscillator and a method for offset cancellation in a relaxation oscillator. The relaxation oscillator comprises two comparator units, each comparator unit comprising a comparator element and a memory element; and a switch control generator coupled to each of the comparator units; wherein each comparator unit, in a reset state, stores an input-offset voltage on the memory element under the control of the switch control generator such that, in a comparison state, the input-offset voltage is applied to both inputs of the comparator for implementing an offset-free threshold.

FIELD OF INVENTION

The present invention relates broadly to a relaxation oscillator, and to a method for offset cancellation in a relaxation oscillator.

BACKGROUND

In a complementary metal-oxide-semiconductor (CMOS) integrated-circuit (IC) systems with extreme constrains on area and power consumption, a monolithic implementation of clock oscillator is essential.

A ring of digital logic gate with negative feed-back, (e.g. ring oscillator) is one of the possible monolithic implementation of an oscillator, and the oscillation frequency is inversely proportional to the sum of each logic gates' delay. The oscillation frequency range can cover from a few mega-hertz to giga-hertz. However, the ring oscillator suffers from huge deviation in its oscillation frequency as environmental conditions change. Therefore, the ring oscillator is almost always used with a frequency locking system such as phase-locked loop where an external reference clock is required.

For a mid-to-high frequency range, inductor-capacitor (LC) tuned oscillator is a popular choice for a time reference. Since both inductors and capacitors do not generate any intrinsic noises, the LC tuned oscillator has one of the best frequency stability. However, although modern CMOS fabrication process provides well-controlled on-chip inductance, inductors occupy significant die area that is sometimes not acceptable for an area-limited application. This becomes worse as the target oscillation frequency goes low because of the inverse proportionality between inductance and the oscillation frequency.

For a low-to-mid frequency range, a resistor-capacitor (RC) pair is another choice for a time reference. Relaxation oscillator is one of the most widely studied and implemented oscillators that utilize readily available RC time reference on a CMOS fabrication process. Since a large RC time constant can be implemented on chip more readily than a large LC value, this oscillator occupies smaller area than LC tuned oscillator. However, monolithic relaxation oscillator circuits also suffer from large errors in oscillation period due to process and temperature variation. Beside the capacitance and resistance, the threshold value of a threshold device is also affected by process and temperature variations. An automatic offset canceling technique can be used in order to compensate for the threshold variation. However, since offset canceling techniques are based on switched-capacitor circuits, offset canceling requires an additional clock signal.

In a relaxation oscillator, a capacitor is periodically charged and discharged by a resistor (or a current source). The timing when to switch between charging and discharging is provided by threshold devices, e.g. CMOS comparators. The oscillation period is directly proportional to the capacitance-resistance product (or capacitance-to-current ratio).

Process variation affects the absolute value of the capacitance-resistance product and may cause errors as large as ±25%. However, this error can be significantly reduced if on-chip calibration for the capacitor (or resistor) is employed. Temperature variation commonly causes an increase of the capacitance-resistance product as temperature rises. This variation can be compensated for by device with a complementary temperature dependency.

A need therefore exists to provide a relaxation oscillator that seeks to address at least one of the above-mentioned problems.

SUMMARY

In accordance with a first aspect of the invention, there is provided a relaxation oscillator comprising two comparator units, each comparator unit comprising a comparator element and a memory element; and a switch control generator coupled to each of the comparator units; wherein each comparator unit, in a reset state, stores an input-offset voltage on the memory element under the control of the switch control generator such that, in a comparison state, the input-offset voltage is applied to both inputs of the comparator for implementing an offset-free threshold.

The memory elements may comprise capacitors.

Each comparator unit may comprise an AND element coupled at respective inputs to an output of the comparator and to the switch control generator respectively, and at an output to a memory block; such that the output of the comparator is decoupled from an input of the memory block in the reset state, and coupled to the input of the memory block in the comparison state under the control of the switch signal generator.

The memory block may provide clock signals to the switch control generator based on current states of the comparator units.

The memory block may comprise an RS flip-flop.

Each comparator may comprise a feedback switchable under the control of the switch control generator such that the feedback is active in the reset state.

Each comparator unit may further comprise a switch coupled to the switch control generator, for charging of the memory element from a reference voltage, including the input-offset voltage, in the reset state.

The switch control generator may comprise a RS flip-flop with multiple delay stages along each feedback path.

In accordance with a second aspect of the invention, there is provided a method for offset cancellation in a relaxation oscillator, the method comprising the steps of for each of two comparators, storing an input-offset voltage on a memory element in a reset phase; and applying, in a comparison phase, a reference voltage, including the input-offset voltage, at a first input of the respective comparators and simultaneously applying the input-offset voltage from the memory element at a second input of the respective comparators for implementing an offset-free threshold.

The method may further comprise decoupling an output of the respective comparators from an input of a memory block in the reset phase, and coupling the output to the input of the memory block in the comparison phase.

The method may further comprise implementing a time delay between decoupling the output of the comparators from the input of the memory block, and entering the reset state for the respective comparators.

The method may further comprise implementing a time delay between entering the comparison state for the respective comparators, and coupling the outputs of the respective comparators to the input of the memory block.

The amount of delay may be controlled by a selected number of delay stages in a switch control generator of the relaxation oscillator.

The memory block may provide clock signals for generating switch control signals based on current states of the comparators.

The method may further comprise applying a feedback across the respective comparator in the reset phase.

The method may comprise charging of the memory element from a reference voltage, including the input-offset voltage, in the reset state.

The switch control generator may comprise a RS flip-flop with two delay stages along each feedback path.

DETAILED DESCRIPTION

The example embodiments described can provide for cancelling errors in the oscillation period due to comparator input-offset voltages, without the need for external signals the example embodiments compensate for the threshold variation with self-clocked offset cancelling comparators.

Before description of the example embodiments, in the following a conventional implementation of a relaxation oscillator will be described with reference toFIG. 1.

FIG. 1shows a conventional implementation of a relaxation oscillator100. The two capacitors, C1and C2are alternately charged and discharged depending on the state of the RS flip-flop102. The input-referred offset voltage of the comparators, U1and U2are modeled as VOFF1and VOFF2, respectively.

Assume that, at time t=0, C1is charged to VDD. Also assume that the RS flip-flop is in the set state at t=0. This state causes transistor MN1to be turned on while MP1is turned off; the voltage across C1, vC1(t) decreases, starting from vC1(0)=VDD, as C1is discharged by the constant current source, ISRC. If we denote the time duration when the RS flip-flop is in the set state as τH, vC1(t) is found out to be as follows.

At the same time, MP2is turned on while MN2is off. This makes C2to be clamped to VDD. Thus the output of U2is held low.

While continuously compared by U1, vC1(t) reaches the trip point of U1, i.e. VREF+VOFF1at t=τHthen the output of U1goes high causing the RS flip-flop102to transit to the reset state. τHcan be found by letting t=τHand vC1(t)=VREF+VOFF1into (1) and solving it for τHas follows.

The transition of the RS flip-flop102to the reset state causes MP1to be turned on while MN1is turned off. Then vC1(t) is rapidly increased back to VDD making the output of U1, i.e. the RST input of the RS flip-flop102to be low again. At the same time, MN2is turned on while MP2is turned off. The voltage across C2, vC2(t) decreases as C2is discharged by ISRC. Since C2was charged to VDD during the previous state of the RS flip-flop102, vC2(t) starts from VDD. If we denote the time duration when the RS flip-flop102is in the reset state as τL, vC2(t) during the reset state is defined as follows.

While continuously compared by U2, vC2(t) reaches the trip point of U2, i.e. VREF+VOFF2at t=τH+τL. τLcan be found by letting t=τH+τLand vC2(τH+τL)=VREF+VOFF2into (3) and solving it for τLas follows.

At t=τH+τL, the output of U2goes high causing the RS flip-flop to be set again, and completing an oscillation cycle. Therefore, the oscillation period of the relaxation oscillator100, tOSCis given as follows.

FIG. 2shows a schematic diagram of a relaxation oscillator200according to an example embodiment. C3and C4are added in addition to C1and C2to store and cancel out the input-offset voltage of each comparator U1and U2. A switch-control generator202is added to generate φ1, φ1a, φ2and φ2a.

It is understood in the art to employ cascaded offset cancelling comparator(s) in order to further reduce charge injections. Assuming that there are two cascaded offset cancelling comparators and let φ1band φ2bbe the feedback control signals for the additional comparator. In this case, φ1band φ2bshould be turned on-and-off slightly later than φ1aand φ2bbut earlier than φ1and φ2. One can readily generate φ1band φ2bby using one more delay stage along each feedback path310,312. This can be expanded to n-stages of cascaded comparator(s) with n+1 delay stages.

FIG. 5shows only the activated connections of the relaxation oscillator200awhen the RS flip-flop is in the set state, i.e. Q=φ1=φ1a=high while Qn=φ2=φ2a=low. Both U1and U2have an input-offset voltage error that is modelled by VOFF1and VOFF2, respectively. It is assumed that C1is initially charged to VDD and C3to VOFF1. The voltage across C1, vC1(t) decreases linearly as C1is being discharged by the constant current source, ISRC. The voltage at the inverting input of U1, vIN1−(t) is given by vC1(t)+VC3where VC3denotes the voltage across C3. Since VC3is assumed to be VOFF1, U1compares vIN1−(t)=vC1(t)+VOFF1with VREF+VOFF1cancelling out VOFF1. On the other hand, the voltage across C2, VC2(t) is clamped to VDD. The voltage at the inverting input of U2, vIN2−(t) is given by VREF+VOFF2due to the negative feedback across U2. Since the bottom-side of C4is connected to VREF, C4is charged to VOFF2. An AND gate, AND2, is inserted between U2and the RS flip-flop202. During φ2=low, U2is disconnected from the SET input of the RS flip-flop. This is to prevent the RS flip-flop from being set by the output of U2when U2is in the follower configuration.

Once the output of U1is asserted high, the RS flip-flop204proceeds to the reset state.FIG. 6shows only the activated connections of the relaxation oscillator200bin the reset state, i.e. Q=φ1=φ1a=low while Qn=φ2=φ2a=high. Just after the RS flip-flop204is reset by U1, C1is disconnected from U1, and then rapidly charged back to VDD. In order to prevent the RS flipflop204from being reset erroneously by charging C1to VDD, AND1decouples U1from the RS flipflop204at the moment when C1is being charged to VDD. Note that this happens before the feedback of U1is activated by φ2a. Therefore, any glitches that can be seen at the output of U1during activation of U1's feedback are also decoupled from the RS flipflop. The negative feedback across U1is activated, thus vIN1−(t) is driven to VREF+VOFF1storing VOFF1into C3; this corresponds to the initial assumption for C3. The AND gate, AND1, hold its output low causing the RST input of the RS flip-flop204to be low again. Since V4has been charged to VOFF2during the previous state (i.e. the set state), vIN2−(t) is given by vC2(t)+VOFF2. Then U2compares vIN2−(t) with the voltage at the non-inverting input, i.e. VREF+VOFF2. Both the inverting and non-inverting inputs of U2have the term VOFF2causing VOFF2to be cancelled out during the comparison. Once vIN2−(t) reaches VREF+VOFF2, U2sets the RS flip-flop204again by asserting its output high. This completes one oscillation cycle.

Mathematically, vC1(t) during the RS flip-flop204being in the set state can be expressed as follows.

Therefore, vIN1−(t) during the set state becomes
vIN1−(t)=vC1(t)+VC3.  (7)

Since vIN1−(t) is compared with VREF+VOFF1, the time duration τHwhen the RS flip-flop204stays in the set state can be found to be

The time duration τLwhen the RS flip-flop204stays in the reset state also can be found symmetrically to be

Since the VC3=VOFF1and VC4=VOFF2, the second and the third term of (10) cancel out and thus we can write tOSCas follows.

In equation (11), the dependency of the oscillation period on the input-offset voltage errors, VOFF1and VOFF2is cancelled out, advantageously providing cancelling of errors in the oscillation period due to comparator input-offset voltages in the example embodiment. As will be appreciated by a person skill in the art, this cancellation in the example embodiment does not require any external signals, thus addressing one of the problems in existing relaxation oscillators with automatic offset cancelling techniques based on switch-capacitors circuits requiring an additional clock signal.

FIG. 10shows a flowchart1000illustrating a method for offset cancellation in the relaxation oscillator200(FIG. 2), in this example embodiment. After power on at step1002, C1is discharged, C2is clamped to VDD and at U2, VC4=VOFF2during the cycle where the condition in step1004is not fulfilled. Once the condition in step1004is fulfilled, the RS flip flop is reset at step1006. During the next cycle, where the condition in step1008is not fulfilled, C1is clamped to VDD, C2is discharged and at U1, VC3=VOFF1. Once the condition in step1008is fulfilled, the RS flip flop is set at step1010, and the process loops back to step1004.

It will be appreciated that the relaxation oscillator of example embodiments can be implemented utilizing readily available RC time reference on a CMOS fabrication process. The proposed relaxation oscillator200(FIG. 2) was simulated using a device model for 0.13-μm, 1.5V CMOS process and results were compared with those of a conventional relaxation oscillator. The reference capacitors, C1and C2are considered ideal in order to clearly see the effectiveness of the offset cancelling scheme in the example embodiment.

FIG. 7shows simulated results of variations in the oscillation period, tOSCas ambient temperature change. tOSCaccording to an example embodiment (curve700) shows 65.0 PPM/° C. of sensitivity to temperature whereas the conventional relaxation oscillator (curve702) has 153.0 PPM/° C.FIG. 8shows peak-to-peak variations in the oscillation period for approximately 99.73% of possible process variation, as a function of temperature. The proposed oscillator (curve800) shows approximately 1% of variation in oscillation period over the investigated temperature range, whereas the conventional oscillator (curve802) shows >10% in the worst case.

FIG. 9shows a flowchart900illustrating a method for offset cancellation in a relaxation oscillator, according to an example embodiment. At step902, for each of two comparators, an input-offset voltage is stored on a memory element in a reset phase. At step904, in a comparison stage, a reference voltage, including the input-offset voltage, is applied at a first input of the respective comparator and simultaneously the input-offset voltage from the memory element is applied at a second input of the respective comparator for implementing an offset-free threshold.