Integrated fan-out package with dummy vias

Disclosed herein is a device comprising a first redistribution layer (RDL) having first lands disposed on a bottom surface of the first RDL and active contact pads disposed on a top surface of the first RDL. The first RDL electrically connects the first lands to the active contact pads. A molding compound layer is disposed on the top surface of the first RDL. Active vias extend through the molding compound layer and are in electrical contact with the active contact pads. Dummy vias extending through the molding compound layer. Top surfaces of the active vias and top surfaces of the dummy vias are substantially planar with a top surface of the molding compound layer, and the dummy vias are electrically insulated from the active vias and the first lands.

BACKGROUND

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. In some devices, multiple dies or packages with active devices or circuits are stacked vertically to reduce the footprint of a device package and permit dies with different processing technologies to be interconnected. Interconnections for this vertical stacking are created on the top and bottom surfaces of a substrate by forming redistribution layers (RDLs) with conductive lines in insulating layers. The RDLs and the dies external to a particular package are electrically connected to dies in the substrate, or dies on opposing sides of the substrate by vias extending through the substrate. Additionally, studs extend through the substrate to a die within the substrate and provide electrical connectivity between the die and external devices.

DETAILED DESCRIPTION

Three dimensional integrated circuit (3D IC) packages are formed by stacking one or more devices or dies vertically. These devices are attached by way of connectors such as, for example, a ball grid array (BGA), a land grid arrays (LGA), solder balls, studs, wire bonds, or other conductive connectors. Conductive elements are disposed in redistribution layers (RDLs) on both sides of the package to provide connectivity between the connectors and the package. The connectors are disposed on each side of a package to permit connection to adjoining packages on top and bottom of the package. Conductive vias are disposed in an electrically insulating substrate and extend through the substrate between the RDLs to provide electrical connectivity between RDLs on opposing sides of the package. Additionally, dies are disposed within the package between the RDLs, with conductive studs electrically connecting contact pads in the die to the RDLs.

Disclosed herein is a method for forming dummy vias and studs in the substrate. The dummy vias are used to provide a uniform metal distribution within the substrate and increase the density of metal elements so that grinding of the substrate does not dish or over grind areas with lower densities of metal features. The dummy vias provide a system for increasing and homogenizing the density of metal features in the substrate, preventing irregularities in the ground substrate surface. Thus, subsequent layers, such as RDL layers, are formed on a uniform and planar surface.

FIG. 1is a cross-sectional view illustrating a step in forming a first RDL102according to some embodiments. In some embodiments, the first RDL102is formed on a carrier114such as a glass or insulating carrier, wafer or other supporting structure. The first RDL102comprises one or more dielectric layers104that are, for example, an oxide such as silicon dioxide, a nitride such as silicon nitride, a carbide such as silicon carbide, polybenzoxazole (PBO), a polymer, a polyimide or another dielectric material. The first RDL102also comprises lands108disposed on the bottom surface of the first RDL102and conductive elements106disposed in the dielectric layers104. The conductive elements106are formed though, for example, deposition and patterning of the conductive elements106. The conductive elements106are formed from a conductive material such as copper (Cu) aluminum (Al), aluminum-copper alloy (AlCu), tungsten (W), gold (Au) or another conductive material or alloy. The lands108are formed by, for example, a physical vapor deposition (PVD) process such as sputtering or the like, or by electroplating, electroless plating or another process. The conductive elements106extend through the dielectric layers104to provide electrical connections between contact pads110and lands108.

Contact pads110are formed at the top surface of the first RDL102. In some embodiments, the contact pads110are formed of copper, aluminum, or another metal by way of PVD or another deposition process. In some embodiments, some contact pads110are active contact pads110A that are disposed on, and electrically connected to, the conductive elements106. The active contact pads110A are electrically connected to lands108by way of the conductive elements106. Additionally, in some embodiments, one or more contact pads110are dummy contact pads110B that are electrically insulated from other contact pads110and from the lands108. Dummy contact pads110B provide a mounting point for subsequent formation of dummy vias.

While the contact pads110are illustrated as being formed directly on the top surface of the topmost dielectric layer104, the structure is not limited to such an embodiment. In other embodiments, the contacts pads110are post passivation interconnects (PPIs), and are formed over a passivation layer (not shown) on the top surface of the first RDL102. In such embodiments, the passivation layer is formed from a nitride such as silicon nitride (SiN), silicon oxynitride (SiON) or another material. Additionally, in some embodiments, a protection layer112is formed over the topmost dielectric layer104and has openings exposing the contact pads110. In such embodiments, the protection layer112is PBO, a polyimide, an oxide, nitride or oxynitride, or another material.

One or more lands108are formed from a conductive material The metal used to form the lands108is patterned to provide individual lands108that are each configured to accept a subsequently formed connector for mounting the package to an external device, die, package, wafer or the like. Additionally, while the lands108are shown as being formed on the bottom surface of the bottommost dielectric layer104, the lands108are not limited to such embodiments. In other embodiments, the lands108are embedded in the lowermost dielectric layer104, or are formed over a passivation layer on the bottommost dielectric layer104as a PPI. Additionally, in some embodiments, a protective layer or the like is formed on the lands108, and has openings over the lands108to permit the mounting of a connector such as a solder ball, stud or the like for connection to an external device.

FIG. 2is a cross-sectional view illustrating mounting a structure212according to some embodiments. The structure212has a substrate202and is mounted by attaching the substrate202to, for example, the protection layer112, where used, or the back side of the first RDL102. In some embodiments, the substrate202is a die, chip, package or the like, and has one or more transistors or devices such as MOSFETs, FinFETs, capacitors, or another substrate, or has a circuit comprising one or more substrates or another circuit element. The substrate202is attached to the protection layer112using a die attachment film204, adhesive, heat transfer film, or the like.

The substrate202has one or more contact pads208exposed at the surface of a device body206. In some embodiments, the contact pads208are arranged in a regular pattern with one or more dummy contact pads. In other embodiments, the contact pads208are arranged in an irregular pattern with spaces or open portions between the contact pads208.

In some embodiments, the structure212comprises one or more studs210disposed on the substrate202with a molding compound layer214formed around the studs210. For clarity, active studs216and dummy studs218are referred to collectively as studs210. Conductive studs210are formed over the substrate202, with active studs216disposed on contact pads208to provide electrical connectivity between the substrate202and subsequently formed layers. Dummy studs218are formed in subsequent steps on the surface of the substrate202between the contact pads208to raise the density of metal features. In some embodiments, the substrate202has dummy contact pads (not shown) and the dummy studs218are formed on the dummy contact pads with the dummy contact pads providing increased support and adhesion for the dummy studs218. The molding compound layer214fills gaps between the studs210and in some embodiments, is an epoxy, resin, PBO, polyimide, oxide, nitride or another electrically insulating material. In some embodiments, the molding compound layer214is formed on a wafer having multiple substrates prior to singulation of the wafer into individuals dies or substrates.

In some embodiments, the studs210are formed by applying the molding compound layer214over the surface of the substrate202, and then patterning the molding compound layer214before plating, or otherwise depositing, a conductive material in the openings to form the studs210. In some embodiments, the studs210are formed by patterning a mask, plating openings in the mask with a metal or otherwise depositing a conductive material in the openings, and removing the mask to leave the studs210. In such an embodiment, the molding compound layer214is formed around the studs210after the studs210are formed. In other embodiments, the studs210are formed using a wirebonder, creating the studs210from a wire that is wirebonded upright on a contact pad208and subsequent formation of the molding compound layer214. In yet other embodiments, the studs210are formed through placement of a pre-formed rigid structure, or another formation process.

FIG. 3is a cross-sectional view illustrating formation of vias300according to some embodiments. For clarity, active vias302and dummy vias304are referred collectively as vias300. In some embodiments, one or more vias300are formed on the first RDL102in regions adjacent to the substrate202. Active vias302are formed on active contact pads110A and are electrically connected to the conductive elements106in the first RDL102through the active contact pads110A. In some embodiments, dummy vias304are formed on dummy contact pads110B, where used. In other embodiments, the dummy vias304are formed on the protective layer112or directly on the first RDL102.

Conductive studs210are formed over the substrate202. The vias300are formed around the structure212using a process similar to those described above with respect to the formation of the studs210. For example, the vias300are formed by patterning a mask and plating openings in the mask, using a wirebonder, through placement of a pre-formed rigid structure, or another formation process. While the structure212is illustrated as having the studs formed on the substrate202when the structure is mounted, the process for forming the structure212and vias300is not limited to such an embodiment. In other embodiments, the structure212is mounted without studs210and the studs210are formed in a same procedure as the vias300.

FIG. 4is a cross-sectional view illustrating formation of a molding compound layer402according to some embodiments. The molding compound layer402is formed around the substrate202, around the vias300and the molding compound layer214. In some embodiments, the molding compound layer402extends over the molding compound layer214. The molding compound layer402fills gaps between the vias300, and fills the gaps between the substrate202or molding compound layer214and the vias300. In some embodiments, the molding compound layer402extends over the topmost surfaces of the vias300.

In some embodiments, the molding compound layer402is formed from an epoxy, resin, PBO, polyimide, oxide, nitride or another electrically insulating material. In embodiments where the molding compound is formed from a flowable material such as a gel or liquid, a mold, molding chase or form is used to retain the molding compound during application and subsequent curing.

FIG. 5is a cross-sectional view illustrating reduction of the molding compound layers402and214according to some embodiments. In some embodiments, the molding compound layers402and214are reduced by planarizing the top surfaces of the molding compound layers402and214, by, for example, grinding, a chemical-mechanical polish (CMP), etch, or the like. The resulting top surface of the molding compound layers402and214is then substantially coplanar with the vias300and studs210. After reducing the molding compound layer402, the vias300extend through the molding compound layer402from the first RDL102to the top surface of molding compound layer402, and the studs210extend through the molding compound layer214from the top surface of the substrate202to the top surface of the molding compound layer214. The vias300and studs210extending through the molding compound layer402and214permit electrical connection of the first RDL102and the substrate202to subsequently formed features such as a second RDL (SeeFIG. 6).

The metal material of the vias300and studs210tends to be harder than the material of the molding compound layers402and214, resulting in a lower removal rate during a grinding, CMP, polishing or other reduction processes. A polishing head used to perform the reduction of the molding compound layers402and214will, in some instances, cause dishing of softer material. Thus, in molding compound layers402and214where the vias300and studs210have an irregular pattern, the molding compound material, and in some cases, the metal features, will be reduced at a greater rate, resulting in an uneven surface. It has been discovered that having dummy vias304and dummy studs218extending through the molding compound layers402and214during grinding increases the uniformity of the surface of the molding compound layer402after grinding. The increased metal density and more regular distribution of metal features in the molding compound layers402and214provided by the dummy vias304prevents the polishing head from removing excess material in regions of lower metal density. In some embodiments, active vias302are arranged in an irregular pattern, with the active vias302having spaces in the via pattern. In such embodiments, dummy vias304are formed in such spaces, raising the density of metal features at the surface of the molding compound layer402during grinding. For example, grinding a molding compound layer402without dummy vias304and with irregular spacing of the active vias302can result in a surface topography variation around 5 μm. However, providing dummy vias304to raise the metal density results in a surface topography variation of 2 μm or less.

Similarly, dummy studs218are formed in the spaces of an irregular pattern for the active studs216. Additionally, in some embodiments, the vias300are formed in an integrated fan-out (InFO) arrangement; with the vias300arranged around and outside of the substrate202and studs210. In such an embodiment, dummy vias304are disposed between the active vias302and the studs210to increase the metal density between the active vias302and the studs210.

It has been further discovered that raising the global density of the metal features in one or both molding compound layers402and214across the surface of a die to between about 40% and about 60% results in a substantially planar molding compound surface after reducing the molding compound layers402or214.

Additionally, raising the local density of the metal features in the molding compound layers402and214in regions with active vias302and active studs216to between about 15% and about 60% results in a substantially planar surface in the local region. For example, in a die with an area of 5 mm×5 mm the global density of vias300and studs210is about 40% to about 60% of the surface area of the die, while 125 μm×125 μm local regions on the surface of the die have a density of vias300and studs210between about 15% and about 60%, with the global density of metal vias300and studs210depending on the density of features in the local regions.

FIG. 6is a cross-sectional view illustrating for mounting a second RDL602to form the package600according to some embodiments. In some embodiments, the second RDL602is formed using a process similar to that described above with respect to the first RDL102. The bottom surface of the second RDL602is substantially planar, matching the topography of the top surfaces of the molding compound layers402and214. The second RDL602has one or more dielectric layer604with conductive features606disposed therein. The conductive features606extend through the dielectric layers604to connect the active vias302to lands608disposed on the top surface of the second RDL602. In some embodiments, the dielectric layers604cover the topmost surfaces of the dummy vias304and the dummy studs218, electrically insulating the dummy vias304from the lands608. While the conductive features606are illustrated herein as being separated from, and not contacting, the dummy vias304and dummy studs218, in some embodiments, or more conductive features606are formed on, or in electrical contact with, the dummy vias304or dummy studs218, but are electrically isolated from, or not electrically connected to the lands608. Thus, the dummy vias304and dummy studs218are electrically insulated from external devices.

FIG. 7is a cross-sectional view illustrating mounting the package600on a second substrate702according to some embodiments. In some embodiments, package600is inverted and mounted to a second substrate702such as a PCB, package, die, interposer, carrier or other structures. The connectors704are formed on lands706on the second substrate702, with the package600attached to the connectors704at the lands608. In other embodiments, the connectors704are formed on the lands608prior to joining the package600to the second substrate702. One or more connectors704are used to electrically connect the package600to the second substrate702. The connectors704are, for example, solder balls, conductive bumps, pillars, studs or another conductive structure. In an embodiment where the connectors704are solder balls, the package600is mounted on the second substrate702and then the solder ball connectors704are heated to reflow the solder, providing a rigid electrical connection between the lands608of the package600and the lands706of the second substrate702.

FIG. 8is a cross-sectional view illustrating mounting of a third substrate812on the top of the package600to form a device800. In some embodiments, a protective layer816is formed over the first RDL120with openings exposing the lands108, and the third substrate812is mounted on the first RDL102. Additionally, in some embodiments, the third substrate812comprises an interposer802, RDL, or other mounting surface, with one or more dies804disposed thereon. The dies804are in electrical communication with lands808disposed on the bottom of the interposer802by way of conductive elements810disposed in one or more insulating or dielectric layers814. The third substrate812is mounted to the package600by connectors806that are, in some embodiments, solder balls, conductive bumps, pillars, studs, or another conductive structure.

While the third substrate812is shown as being mounted on the package600after the package600is mounted to the second substrate702, the device800is not limited to such embodiments. For example, in some embodiments, the third substrate812is mounted to the package600prior to the package600being mounted to the second substrate702. For example, in some embodiments, the substrate202is a processor, with the dies804being memory dies such as DRAM, signal processing dies, or another die.

FIG. 9is a top view of a molding compound layer402with dummy vias304arranged with active vias302according to some embodiments. In such embodiments, active studs216and dummy studs218are disposed over the substrate in substrate regions902. The active studs216and dummy studs218are arranged in a regular pattern, with the dummy studs218disposed in place of missing or omitted active studs216.

The active vias302are disposed in active via regions904surrounding the substrate region902in an InFO pattern. In some embodiments, dummy vias304are disposed in the active via regions904with the active vias302. Additionally, in some embodiments, some of the active via regions904are spaced apart from the substrate region902. Dummy via regions906are disposed in the space between the active via regions904and the substrate region902. The dummy via regions906have dummy vias304arranged in a pattern and disposed between the active via regions904and the substrate region902. The dummy vias304in the dummy via region906raise the metal density in the spaces between the active via regions904and the substrate region902, preventing dishing or overgrinding of the molding compound layer402in the spaces between the substrate and active vias302. Additionally, the dummy vias304in the dummy via regions906are spaced apart from the vias302and304in the active via regions904based on the pitch or spacing of the active vias302. It should be noted that the spacing between the dummy vias in the dummy via region906is, in some embodiments, different from the pitch of the active vias302or studs216and218. It has been determined that a spacing of the dummy vias304in the dummy via region906from the vias302and304in the active via regions904of about 50% to about 150% of the active via pitch provides a density and pattern regularity resulting in a substantially planar molding compound layer402surface. For example, if the pitch of the active vias302is about 200 μm, then the dummy vias304in the dummy via regions906would be spaced apart from the active vias302by between 100 μm and about 300 μm. Additionally, the dummy vias304in the dummy via region906are spaced apart from the edge of the substrate by between about 50 μm and about 100 μm. The studs216and218are spaced apart from the substrate edge by about 50 μm, resulting in a spacing between the dummy vias304in the dummy via region906and the studs that is between about 100 μm and about 150 μm.

While the active vias302and dummy vias302are generally shown as being round, it should be understood that the dummy vias304are, in some embodiments, a different shape than the active vias302. For example, the dummy vias304may have a square shape, as shown by square dummy via304A, a polygon shape, as shown by octagon dummy via304B, a rectangle shape, as shown by rectangle dummy via304C, or any other shape. Additionally, the dummy vias304have, in some embodiments, a larger or smaller cross section than the active vias302. For example, rectangle dummy via304C has a cross-sectional area that is larger than an active via302, and extends past multiple active vias302. The larger or smaller cross-section area can be used to tune the metal density for a particular region to provide more grinding resistance during the reduction of the molding compound layer402. Similarly, in some embodiments, the active studs216and dummy studs218have different shapes, with the dummy studs218being formed from a polygon, square, rectangle round or other shape.

FIGS. 10A through 10Care cross-sectional views illustrating dummy vias304formed according to various embodiments.FIG. 10Ais a cross-sectional view illustrating a dummy via304formed on the protection layer112of the first RDL102according to some embodiments. In such embodiments, the dummy via304has a bottommost surface that is electrically insulated from other conductive structures. In other embodiments, the protection layer has an opening under the dummy via304, permitting the dummy via to extend through the protection layer112and contact an underlying layer, such as a dielectric layer104. Additionally, in embodiments where the protection layer112is absent, the dummy vias304is formed on the dielectric layer104, or another layer over the dielectric layer104.

FIG. 10Bis a cross-sectional view illustrating a dummy via304formed on a dummy contact pad110according to some embodiments. In such embodiments, the protection layer112has an opening exposing the dummy contact pad110. The dummy via304extends through the opening and contacts the dummy contact pad110. In some embodiments, the dummy contact pad110is formed at the same time as the active contact pads (not shown, seeFIGS. 1 and 3, element110A), but is not electrically connected to any of the lands (seeFIGS. 1 and 3, element108). The dummy contact pad110has a metal surface that, depending on the method of forming the dummy via304, provides a level surface with improved metal-to-metal adhesion. Additionally, the dummy contact pad110increases the density and regularity of metal features in the first RDL102.

FIG. 10Cis a cross-sectional view illustrating a dummy via304formed over multiple dummy contact pads110according to some embodiments. As discussed above, the shapes of the dummy vias304are tuned to provide a desired metal distribution and density in the molding compound layer402. In such an embodiment, the dummy via304may extend over two or more dummy contact pads110, extending through multiple openings in the protection layer112, where provided, and contacting multiple dummy contact pads110. In such an embodiment, the dummy via304extends contiguously over multiple dummy contact pads110. However, the dummy via304is still electrically isolated from the lands108and from the active contact pads110since the dummy contact pads110and the dummy vias304are electrically isolated from the other conductive structures. Additionally, while the dummy contact pads110are shown as being separated, the embodiments are not limited to such a structure. In other embodiments, one or more dummy contact pads110are electrically connected by metal features in the first RDL102. For example a single dummy contact pad110may extend under multiple openings in the protection layer112, with one or more dummy vias304formed thereon. However, in such an embodiment, the dummy vias304and dummy contact pads110are still electrically isolated from the lands, substrate or active vias.

FIG. 11is a flow diagram illustrating a method1100of forming and using dummy vias and dummy studs according to some embodiments. Initially, a first RDL is formed in block1102. A substrate with active and dummy studs, such as a die, package or the like, is mounted on the first RDL in block1104. Vias, including active and dummy vias are formed on the first RDL in block1106. Additionally, in embodiments where the studs are not on the substrate when the substrate is mounted, active and dummy studs are formed on the substrate in block1106. A molding compound layer is formed over the first RDL and around the vias, studs and substrate in block1108. The molding compound layer is reduced in block1110to expose, and in some embodiments, reduce, the top surfaces of the vias and studs. A second RDL is formed on the top surface of the molding compound layer in block1112. In block1114, the package is mounted on a substrate, and another substrate is mounted on the package.

Thus, a device according to an embodiment comprises a first RDL having first lands disposed on a bottom surface of the first RDL and active contact pads disposed on a top surface of the first RDL and the first RDL electrically connects the first lands to the active contact pads. A molding compound layer is disposed on the top surface of the first RDL. Active vias extend through the molding compound layer and are in electrical contact with the active contact pads. Dummy vias extending through the molding compound layer. Top surfaces of the active vias and top surfaces of the dummy vias are substantially planar with a top surface of the molding compound layer, and the dummy vias are electrically insulated from the active vias and the first lands.

A device according to another embodiment comprises a first RDL having first lands disposed on a bottom surface of the first RDL. A molding compound layer is disposed on a top surface of the first RDL. Dummy vias extend through the molding compound layer, and the dummy vias are electrically insulated from the first lands. A substrate is disposed in the molding compound layer and dummy studs extend from the top surface of the substrate to a top surface of the molding compound layer. The dummy vias are electrically insulated from the first lands and from contact pads of the substrate. Top surfaces of the dummy vias and top surfaces of the dummy studs are substantially planar with the top surface of the molding compound layer.

A method according to an embodiment comprises forming a first RDL having first lands disposed on a bottom surface of the first RDL and active contact pads disposed on a top surface of the first RDL. The first RDL electrically connects the first lands to the active contact pads. A substrate is mounted on the top surface of the first RDL. Active vias are formed on the top surface of the first RDL and in electrical contact with the active contact pads and dummy vias are formed on the top surface of the first RDL. The active vias and the dummy vias are disposed around the substrate, and the dummy vias are electrically isolated from the active vias and the first lands. A molding compound layer is formed on the top surface of the first RDL and around the active vias, the dummy vias and the substrate. The top surface of the molding layer is reduced, and after the reducing the top surface of the molding compound layer, the top surface of the molding compound layer is substantially planar with top surfaces of the active vias and the dummy vias.