FORMING NANOSHEET TRANSISTORS WITH DIFFERING CHARACTERISTICS

A method of forming a transistor in an integrated circuit device can include forming a first and second nanosheet structure with alternating sheets of silicon and silicon germanium. A first and second transistor structure are constructed using the first and second nanosheet structures as first and second channels. The sheets of silicon germanium are removed from the first and second nanosheet structures. A mask is placed over the first transistor structure, leaving the second transistor structure exposed. The second channel is thinned while the first transistor is protected by the mask. Thereafter, semiconductor processing continues, with the first transistor having a thicker channel than the second transistor.

BACKGROUND

The present invention relates in general to integrated circuit device structures and their fabrication. More specifically, the present invention relates to the fabrication of transistors with varying characteristics in integrated circuit devices.

Integrated circuit devices are a set of electronic circuits on one small chip of semiconductor material. A typical integrated circuit device includes many transistors. Sometime, chip designers wish to have transistors with different characteristics. For example, there can be a desire for a “wimpy” transistor, also known as a transistor with a “wimpy” gate. Such a transistor can have a higher threshold voltage than other (also known as “nominal”) transistors in an integrated circuit. While it can be desirable to create transistors with differing characteristics in a single integrated circuit device, such a process is much easier in an integrated circuit using planar transistor technology. In an integrated circuit using FinFET or nanosheet technology, making transistors with such varying characteristics can be difficult.

SUMMARY

Embodiments herein are directed to a method of forming a structure of a semiconductor device. The method includes forming a first and second nanosheet structure including alternating sheets of silicon and silicon germanium. A first transistor structure is formed using the first nanosheet structure as a first channel. A second transistor structure is formed using the second nanosheet structure as a second channel. The sheets of silicon germanium are removed from the first and second nanosheet structures. A mask is placed over the first transistor structure, leaving the second transistor structure exposed. The second channel is thinned. The creation of the first transistor structure and the second transistor structure is finalized.

Embodiments described herein are also directed to an integrated circuit device that includes a first transistor and a second transistor. The integrated circuit device is formed by forming a first and second nanosheet structure including alternating sheets of silicon and silicon germanium. A first transistor structure is formed using the first nanosheet structure as a first channel. A second transistor structure is formed using the second nanosheet structure as a second channel. The sheets of silicon germanium are removed from the first and second nanosheet structures. A mask is placed over the first transistor structure, leaving the second transistor structure exposed. The second channel is thinned. The creation of the first transistor and the second transistor is finalized.

Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the features, refer to the description and to the drawings.

DETAILED DESCRIPTION

It is understood in advance that although a detailed description of an exemplary transistor configuration is provided, implementation of the teachings recited herein are not limited to the particular structure described herein. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of integrated circuit device, now known or later developed.

Described herein is a method of forming transistors with differing gate structures in a single integrated circuit device. As semiconductor feature sizes become smaller, conventional methods of forming transistors with differing gate structures in an integrated circuit becomes impractical.

Turning now to an overview of the present invention, one or more embodiments form transistors with a different gate dimensions from other transistors in the integrated circuit device, allowing a single integrated circuit device to have transistors with different gate structures, such that transistors can have different operating characteristics. Among the differing operating characteristics can be the threshold voltage. In particular, a “wimpy” transistor is a transistor with a higher threshold voltage than a nominal transistor. The higher threshold voltage can lead to a smaller leakage current for the wimpy transistor compared to a nominal transistor and lower power consumption. While a wimpy transistor will not have performance that matches the nominal transistor, wimpy transistors can be used to for less critical functions of an integrated circuit. Thus, an integrated circuit designer can find it desirable to have both nominal transistors and wimpy transistors in the integrated circuit device. In an integrated circuit that uses nanosheet technology in the channel, creating wimpy transistors using traditional techniques can be problematic. It has been found that using a thinner channel can create a wimpy transistor. For example, if a nominal transistor has a thickness of 10 nm, a wimpy transistor with a 5.5 nm channel will have a 30 mV (0.03 V) higher threshold voltage.

Turning now to a more detailed description of an embodiment of the present invention, a preliminary fabrication methodology for forming transistors with differing characteristics in accordance with one or more embodiments will now be described with reference toFIGS. 1 through 6.

Referring now toFIG. 1, an initial structure with two transistors,130and160. These transistors130and160will be formed on a single substrate102. At this point in the formation of the transistors, a standard nanosheet transistor formation process has taken place up to the formation of the dummy gate.

Each of transistor130and160have identical structures at this point. Transistor130includes shallow trench isolation regions104above substrate102, epitaxial regions106,108,110, and112, a dummy gate (typically made of polysilicon)114, a spacer118, a nitride120, and an inter-layer dielectric122. Below dummy gate114are a series of nanosheet channels132. Separating the nanosheet channel layers are a series of SiGe sacrificial layers134. In future steps, transistor130will become a “nominal” transistor, or a transistor with the default channel thickness.

Transistor160includes shallow trench isolation regions104above substrate102, epitaxial regions106,108,110, and112, a dummy gate (typically made of polysilicon)114, a spacer168, a nitride120, and an inter-layer dielectric122. Below dummy gate114are a series of nanosheet channels162. Separating the nanosheet channel layers are a series of SiGe sacrificial layers164. At this point in the process, nanosheet channel132of transistor130and nanosheet channel162of transistor160are identical. In future steps, transistor160will become a “wimpy” transistor, or a transistor with a smaller channel thickness.

While only two devices, transistor130and transistor160, are shown in these drawing figures, it should be understood that a typical integrated circuit device will contain millions of transistors, some of which will have a traditional or conventional construction, and some of which will have a “wimpy” construction.

A poly-open chemical mechanical polish (CMP) is performed to remove nitride120without affecting the remainder of the structures. Thereafter, the polysilicon gate114can be removed by an etch, such as a reactive ion etch (RIE). The result is illustrated inFIG. 2. Atop substrate102are shallow trench isolation104, epitaxial regions106,108,110, and112, spacer118, and inter-layer dielectric122. There are a series of nanosheet channels132and162. Separating the nanosheet channel layers are a series of SiGe layers134and164. These can be referred to as sacrificial layers. At this point in the process, nanosheet channel132of transistor130and nanosheet channel162of transistor160remain identical.

Thereafter, the SiGe sacrificial layers134and164are removed, resulting in the structure ofFIG. 3. This removal can be accomplished in one of a variety of different manners known in the art. In some embodiments, a selective etch can be performed for the removal. The etch can be a reactive ion etch (RIE), a gaseous etch, or a wet etch, as long as it is selective to the SiGe layers.

Thereafter, a mask440is placed over transistor130, resulting in the structure illustrated inFIG. 4, with transistor130having an overlying mask130and transistor160being exposed. The mask440is used to protect the nominal transistors from the following steps. Mask440can be one of a variety of different materials. In some embodiments, mask400is a nitride, such as a silicon nitride.

Thereafter, operations can be performed on the “wimpy” transistor160. The nanosheet channels162can be thinned in one of a variety of different methods. In some embodiments, to ensure control over the thinning process, a combination of oxidation and followed by etching using hydrofluoric acid can be performed such to perform the thinning of nanosheet channels162. Other methods, such as atomic layer etching, also can be used. In some embodiments, an oxide etching that is specifically directed towards materials that have been oxidized. Quantum mechanical effects of the thinner nanosheet channel result in the transistor160having a higher threshold voltage Vt. Such acts have no effect on transistor130because the presence of mask400prevents the above-described steps from affecting transistor130.

Thereafter, mask400is removed. Thereafter, conventional processing steps can be performed on both transistor130and wimpy transistor160. Processing steps can include the placement of high-K dielectrics, a metal gate, and contacts for the source and drain areas. A simplified version of the resulting structure can be as shown inFIG. 5.

As shown inFIG. 5, there are contacts550coupled to each of the source/drain epitaxial regions. In addition, there is a spacer560between each of the device channels on both transistor130and wimpy transistor160. A high-k dielectric570can also be present. In some embodiments, the high-k dielectric is formed from hafnium oxide. Other features also can be present, but are not illustrated inFIG. 5.

As described above, thinning a channel from 10 nm to 5-6 nm can result in a change in threshold voltage of 30 mV. In some embodiments, such a change can be all that is used. An advantage of limiting the thinning is that process control variations can be too difficult to control if more material is removed from the channel. However, it should be understood that other levels of thinning, both those resulting in thicker or thinner channels (down to approximately 3 nm or even lower), can be used.

FIG. 6is a flow diagram illustrating a methodology600according to one or more embodiments. At block602, a nanosheet transistor including alternating sheets of epitaxially deposited silicon and epitaxially deposited silicon germanium is provided or created. The transistor includes at least two transistors. A typical structure will include a substrate. On the substrate are epitaxial regions that will later form the source and drain areas. Also present is a nanosheet channel region, with a dummy gate region atop the nanosheet channel region. At block604, a chemical-mechanical polish (CMP) or similar procedure is performed to remove the dummy gate structure. At block606, layers of silicon germanium are removed from the nanosheet channel region. This can be performed in one of a variety of different manners known in the art. At block608, a mask is placed over some of the transistors. The transistors covered by the mask will be protected from subsequent processing steps. At block610, operations are performed on the transistors that are not covered by the mask (the “exposed” transistors). In some embodiments, a combination of oxidation of the channel layers followed by an etching can be performed that serve to thin the channel layers. Such a thinning of the channel layers results in a rise of the threshold voltage of the transistor. At block612, the mask is removed. Thereafter, at block614, conventional processing steps can be performed on both normal transistors and “wimpy” transistors to complete the fabrication of the transistors on the integrated circuit device.

Thus, it can be seen from the forgoing detailed description and accompanying illustrations that embodiments of the present invention provide structures and methodologies for providing transistors with differing operating characteristics, such as different threshold voltages.

The diagrams depicted herein are just one example. There can be many variations to this diagram or the operations described therein without departing from the spirit of the invention. For instance, the operations can be performed in a differing order or operations can be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While various embodiments have been described, it will be understood that those skilled in the art, both now and in the future, can make various modifications which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.