Semiconductor device for transferring first data to a setting/resetting circuit block

A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-255830, filed Sep. 2, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, more particularly to a semiconductor integrated circuit comprising a circuit block which operates based on initializing data and a circuit which transfers the initializing data.

2. Description of the Related Art

The amount of analog data output from a circuit made up of transistors inevitably varies depending upon the characteristic variation among the transistors. The variation amount of analog data can be corrected to be a predetermined value, and this correction operation is known as “trimming.” Redundancy is also known in the art as a technology for remedying defective cells of a memory by use of a redundancy circuit.

To put the trimming or redundancy to practical use, a data distribution circuit is provided to send trimming data based on which the trimming is performed, or redundancy data based on which the redundancy is performed. The data distribution circuit comprises programmable nonvolatile elements for retaining initializing data such as trimming data or redundancy data. It also comprises a shift register made up of flip-flops and configured to store the initializing data. The shift register is made up of flip-flops which are equal in number to the pieces of the initializing data. The data distribution circuit sends the initializing data to a group of circuit blocks located far away. Each circuit block performs trimming and redundancy, using the initializing data it receives.

The above configuration is disadvantageous in the following points: (i) it is not possible to externally confirm whether the initializing data of the nonvolatile elements are correctly set in the shift register, and (ii) it is not possible to externally confirm whether the initializing data are correctly supplied to the circuit blocks. Furthermore, the nonvolatile elements are programmable only once. After the nonvolatile element is programmed, the data used for programming is the only data that is available, and the circuit blocks cannot use data other than the programming data.

When the data of the nonvolatile elements is set in the shift register, the above configuration uses pulse signals. The shift register is made up of a plurality of flip-flops. Where the initializing data have a large data width, the number of flip-flops required is large. Therefore, a plurality of shift registers, each corresponding to a predetermined number of bits, are used, and these shift registers are connected in series to deal with the initializing data. To transmit pulse signals to the multi-stage shift register, a plurality of buffers made up of transistors are used.

Where a plurality of buffers are used for data setting, the characteristic difference among the transistors becomes more marked in accordance with an increase in the number of pieces of data, and the pulse signals may not be transmitted to the final stage with a satisfactory margin. In other words, the characteristic difference among the transistors gives rise to a decrease in the pulse width of the pulse signals. In the worst case, the pulse signals may be lost during the transmission. Owing to this, data may not be set in the shift register of the final stage.

A semiconductor device related to the above art enables external setting of trimming data. Such a semiconductor device is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2003-110029, for example.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to the first aspect of the present invention transfers first data to a circuit block and comprises: a storage circuit configured to store the first data; a shift register configured to set the first data; a transfer circuit configured to transfer the first data from the shift register to the circuit block; a first input terminal configured to receive a first signal indicating the end of a transfer operation; a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal; a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset; and an output circuit configured to externally output the first data that has been set again.

A semiconductor device according to the second aspect of the present invention comprises: an output circuit configured to output a first signal; a transmission circuit including a plurality of circuit sections connected in series, each of the circuit sections including a load capacitance element that operates based on the first signal, and a buffer circuit serving to supply the first signal to subsequent ones of the circuit sections; and a generation circuit configured to generate a pulse signal by inverting the polarity of the first signal after the first signal is transmitted to the circuit sections.

A semiconductor device according to the third aspect of the present invention comprises: a storage circuit configured to store first data; a shift register configured to set or reset the first data; a first resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register; and a second resetting signal-generating circuit configured to generate a first detection signal indicating that the shift register has been reset after the resetting signal is transferred to the shift register, the first resetting signal-generating circuit disabling the resetting signal based on the first detection signal.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described with reference to the accompanying drawings. In the descriptions below, structural elements that are similar or correspond to each other will be denoted by the same reference numerals, and a repeated description will be given only where necessary.

First Embodiment

FIG. 1is a schematic diagram illustrating a semiconductor integrated circuit1according to the first embodiment of the present invention. The semiconductor integrated circuit1comprises a data distribution apparatus2and a group of circuit blocks3(which will be collectively referred to as “circuit block group3” hereinafter).

The data distribution apparatus2has a clock terminal T2. Clock signal CLK is externally supplied to the clock terminal T2. The data distribution apparatus2operates in synchronism with the clock signal CLK.

The data distribution apparatus2transfers initializing data to the circuit block group3. The data distribution apparatus2includes a control section4, a shift register5and a storage circuit6.

The storage circuit6stores the initializing data. The storage circuit6can be programmed only once to store the initializing data. The storage circuit6is made up of a plurality of nonvolatile elements (ROM: read only memories), the number of which corresponds to the number of bits of the initializing data.

The shift register5sets the initializing data in itself. Specifically, the shift register5fetches and holds the initializing data. On the basis of the clock signal CLK, the shift register5shifts the initializing data. Then, the shift register5sends the initializing data to the circuit block group3.

FIG. 2is a block diagram showing the configurations of the shift register5and storage circuit6depicted inFIG. 1. The storage circuit6includes a plurality of nonvolatile elements ROM1-ROMm, the number of which corresponds to the number of bits of the initialing data. The shift register5includes a plurality of flip-flops FF1-FFm. These flip-flops are arranged in correspondence to the nonvolatile elements.

The data stored in the nonvolatile elements are set in the flop-flops FF. The flip-flop FF outputs the set data in synchronism with the clock signal CLK. Furthermore, The flip-flop FF outputs data input from the flip-flop FF adjacent to the input side in synchronism with the clock signal CLK. In this manner, the shift register5outputs all data stored in the storage circuit6. Externally-supplied input data may be set in the flip-flops FF of the shift register5. After being retained for a predetermined time, the input data is output from the shift register5.

The control section4controls the operation of setting the initializing data in the shift register5. The control section4also controls the operation of transferring the initializing data from the shift register5to the circuit block group3.

The circuit block group3is initialized based on the initializing data. The circuit block group3includes a reference voltage generating circuit, for example. The reference voltage generating circuit performs a trimming operation on the basis of the initializing data. In other words, the reference voltage generating circuit corrects an output voltage to a predetermined value on the basis of the initializing data (which is trimming data in the example).

The circuit block group3may include a semiconductor storage device. The semiconductor storage device has a redundancy circuit and performs a redundancy on the basis of the initializing data. In other words, the semiconductor storage device remedies a defective cell of the memory by use of the redundancy circuit.

The data distribution apparatus2has input terminal T3which enables access to the shift register5, and output terminal T1from which data is output. External input data EDI is supplied to input terminal T3. External output data EDO is supplied from output terminal T1.

A description will now be given as to how the semiconductor integrated circuit1operates. First of all, the control section4sets the data of the storage circuit6in the shift register5. Then, the control section4transfers the set data from the shift register5to the circuit block group3. Subsequently, the control circuit4resets the shift register5.

The control circuit4sets data in the shift register5once again. Upon receipt of clock signal CLK externally supplied thereto, the data is externally output from output terminal T1.

In synchronism with clock signal CLK supplied from input terminal T2, the shift register5is supplied with external input data EDI from the input terminal T3. The control circuit4sends this data to the circuit block group3.

The circuit configuration and circuit operation of the semiconductor integrated circuit1shown inFIG. 1will be described in more detail, referring to the drawings.FIG. 3is a block diagram showing an example of the configuration of the semiconductor integrated circuit1depicted inFIG. 1.

The data distribution apparatus2and the circuit block group3are connected to each other through an input/output signal line9. The data distribution apparatus2has output terminals T1and T6and input terminals T2, T3, T4and T5. Input terminal T2receives clock signal CLK externally supplied thereto. Input terminal T3receives external input data EDI externally supplied thereto. Input terminal T3also receives commands externally supplied thereto.

Input terminal T4receives a transfer start signal FXOK externally supplied thereto. The transfer start signal FXOK designates the start of the operation of transferring the initializing data. The transfer start signal FXOK is supplied from the control block group3, from a control circuit controlling this control block group3, or from another circuit.

Input terminal T5receives a transfer end signal FXDONE externally supplied thereto. The transfer end signal FXDONE designates the end of the operation of transferring the initializing data. Like the transfer start signal FXOK, the transfer end signal FXDONE is supplied from the control block group3, from the control circuit controlling the control block group3, or from another circuit. The signals received at these terminals are supplied to the control section4through the terminals of the control section4.

Output terminal T1outputs an external output data EDO provided by the control section4. Output terminal T6outputs output data DO provided by the control section4. The output data DO is supplied to the circuit block group3through the input/output signal line9.

FIG. 4is a block diagram showing the configuration of the control section4depicted inFIG. 3. The control section4comprises an output circuit4a,a resetting signal-generating circuit4b,a setting signal-generating circuit4c,a transfer circuit4d,an input circuit4eand a command decode circuit4f.

The output circuit4aoutputs data which is set in the shift register5again. The resetting signal-generating circuit4bgenerates a resetting signal FCLRS used for resetting the shift register5or for releasing it from the reset state. To be more specific, the resetting signal-generating circuit4bgenerates a signal FCLRS used for reset-releasing, upon reception of signal FXOK, and generates the signal FCLRS used for resetting, upon reception of signal FXDONE.

The setting signal-generating circuit4cgenerates a setting signal FSETS used for setting data in the shift register5. To be more specific, the setting signal-generating circuit4cgenerates the setting signal FSETS after the shift register5is released from the reset state. The transfer circuit4dtransfers data from the shift register5to the circuit block group3.

The input circuit4ereceives external input data EDI, which is externally supplied thereto. The input circuit4esupplies the external input data EDI to the shift register5. The command decode circuit4finterprets the command supplied to the input terminal T3. Based on the command, the command decode circuit4fcontrols the circuits of the control section4. The clock signal CLK input to the control section4is supplied to the circuits provided in the control section4. The clock signal CLK is supplied from the control section4to the shift register5.

The data distribution circuit2comprises a plurality of flip-flop sections7.FIG. 5is a circuit block diagram showing the configuration of each flip-flop section7. Each flip-flop section7is made up of, for example, five flip-flop circuits8connected in series. Each flip-flop circuit8includes one nonvolatile element and one flip-flop FF.

Resetting signal FCLRIN, setting signal FSETIN and clock signal CLKIN are supplied to the flop-flop section7. Signal FCLRIN is supplied to buffer BF1. This buffer BF1includes two inverter circuits IV1and IV2connected in series. The buffer BF1outputs resetting signal FCLR. This signal, FCLR, is supplied to the five flip-flop circuits8of the flip-flop section7, and also to the flip-flop section7of the next stage.

Signal FSETIN is supplied to buffer BF2. This buffer BF2includes two inverter circuits IV3and IV4connected in series. The buffer BF2outputs setting signal FSET. This signal, FSET, is supplied to the flip-flop circuits8of the flip-flop section7, and also to the flip-flop section7of the next stage.

Signal CLKIN is supplied to buffer BF3. This buffer BF3includes two inverter circuits IV5and IV6connected in series. Inverter circuit IV5inverts clock signal CLKIN, thereby producing clock signal CLKB. This clock signal, CLKB, is supplied to the flip-flop circuits8of the flip-flop section7. Buffer BF3outputs clock signal CLK. This clock signal, CLK, is supplied to the flip-flop circuits8of the flip-flop section7, and also to the flip-flop section7of the next stage.

Input data IN is supplied to the flip-flop section7. In synchronism with the clock signal CLK, the input data IN is shifted, and is produced as output data OUT by the flip-flop section7.

FIG. 6is a circuit diagram showing the configuration of the flip-flop circuit8. The flip-flop circuit8comprises clocked inverter circuits8aand8c,inverter circuits8b,8eand8f,a transfer gate8d,N-type MOS transistors8h,8kand8l,P-type MOS transistors8g,8iand8j,and a nonvolatile element ROM. The nonvolatile element is a fuse element, for example.

When clock signal CLK is “0”, clocked inverter circuit8aoutputs data obtained by inverting input data INX. When clock signal CLK is “1”, clocked inverter circuit8coutputs data which is obtained by inverting the input data thereto. Inverter circuit8band clocked inverter circuit8cconstitute a holding circuit. This holding circuit holds the data output from clocked inverter circuit8awhen clock signal CLK is “1.”

Transfer gate8dis made of an N-type MOS transistor and a P-type MOS transistor that are connected in parallel to each other. When clock signal CLK is “1”, transfer gate8dallows outputting data. The output terminal of the transfer gate8dis connected to node FNODE. This node is connected to the input terminal of inverter circuit8e.

Transistors8ito8ljointly constitute a clocked inverter circuit. This clocked inverter circuit and inverter circuit8econstitute a holding circuit. When clock signal CLK is “0”, the holding circuit holds the data appearing at node FNODE.

FIG. 7is a timing chart illustrating an operation of the flip-flop circuit8. When signal FCLR is “0” and signal FSET is “0”, transistor8gis turned on and transistor8his turned off. In this case, the potential at node FNODE is Vdd (i.e., data “1”). Accordingly, the flip-flop circuit8is reset.

When signal FCLR is “1” and signal FSET is “1”, transistor8gis turned off and transistor8his turned on. In this case, the potential at node FNODE is the same as the data stored in the nonvolatile element. In other words, where the fuse element is cut off, the data appearing at node FNODE is data “1.” Where the fuse element is not cut off, the data appearing at node FNODE is data “0.” In this manner, the flip-flop circuit8stores the data held in the nonvolatile element.

In synchronism with clock signal, the flip-flop circuit8outputs the data held at node FNODE, and the input data supplied to the flip-flop circuit8is held at node FNODE. In this manner, the shift register5outputs the data stored in each nonvolatile element.

A description will now be given of how the semiconductor integrated circuit1of the above configuration operates.FIG. 8is a timing chart illustrating an operation of the data distribution apparatus2.

The data distribution apparatus2is supplied with transfer start signal FXOK. Upon receipt of transfer start signal FXOK, the data distribution circuit starts a transfer operation. To be more specific, when signal FXOK changes from “0” to “1”, the control section4changes resetting signal FCLRS from “0” to “1.” As a result, all flip-flops FF are released from the reset state. It should be noted here that flip-flops FF are reset when resetting signal FCLRS is “0” and released from the reset state when resetting signal FCLRS is “1.”

After all flip-flops FF are released from the reset state, the control section4outputs setting signal FSETS, which is a pulse signal of data “1.” This pulse signal is supplied to the flip-flop circuit8. Upon receipt of it, the flip-flop circuit8stores data held in the nonvolatile element. When clock signal CLK is supplied thereafter, the control section4transfers data from the shift register5to the circuit block group3.

After the data is transferred to the circuit block group3, transfer end signal FXDONE is input. To be more specific, signal FXDONE changes from “0” to “1”, the control section outputs signal FCLRS, which is a pulse signal of data “0.” This pulse signal is supplied to each flip-flop circuit8. As a result, all flip-flop circuits8are reset.

When signal FCLRS changes from “0” to “1”, all flip-flops FF are released from the reset state. In response to this, the control section4outputs signal FSETS, which is a pulse signal of data “1.” This pulse signal is supplied to each flip-flop circuit8. As a result, each flip-flop circuit8stores the data held in the nonvolatile element one more time. When clock signal CLK is externally supplied, the control section4outputs external output data EDO from output terminal T1.

A description will now be given as to how external input data EDI is transferred from the data distribution apparatus2to the circuit block group3.

When external input data EDI is input, the control section4produces output data DOX corresponding to data EDI and supplies it to the shift register5. Thereafter, when clock signal CLK is input, the shift register5stores output data DOX. When clock signal CLK is input, the control section4transfers the data from the shift register5to the circuit block group3.

The operation of the data distribution apparatus2is controlled by supplying commands to it. For example, the control section4may be so configured as not to perform a data transfer operation despite the receipt of transfer start signal FXOK. Alternatively, the control section may be so configured as to transfer only the data stored in some of the nonvolatile elements. Furthermore, after the data transfer operation, the control section4may reset the nonvolatile elements without storing data in them. Still further, the control section4may be so designed as to write “0” in all flip-flops FF, or to write “0” and “1” alternately in flip-flops FF.

As detailed above, in the present embodiment, the data stored in the nonvolatile elements are output from the data distribution apparatus2, and externally input data are transferred to the circuit block group3.

The present embodiment enables the nonvolatile elements and the shift register to be accessed externally. This leads to improvement of the performance of semiconductor integrated circuits1and the improvement of the manufacturing yield.

The data stored in the nonvolatile elements can be externally read out. The readout data may be compared with the data that is used for programming the semiconductor integrated circuit1at the time of manufacture, and the results of this comparison can be used for evaluating the nonvolatile elements and the shift register.

The externally input data may be transferred to the circuit block group3. This transfer operation is useful to the case where the data in the nonvolatile elements are used for redundancy or trimming. This is because there may be a case where the data in the nonvolatile elements need to be rewritten inside the chip after they are used for programming.

Second Embodiment

FIG. 9is a schematic diagram illustrating a semiconductor integrated circuit10according to the second embodiment of the present invention. The semiconductor integrated circuit10comprises a control section11and a transmission circuit12.

FIG. 10is a circuit diagram showing the configuration of the transmission circuit12depicted inFIG. 9. The transmission circuit12comprises a plurality of circuits13connected in series. The transmission circuit12receives input signal IN1supplied from the control section11, and produces output signal OUT1. The input signal IN1is sequentially transmitted to the circuits13of the transmission circuit12.

Each circuit13includes a buffer BF and a load capacitance element LC. The buffer BF is made of two inverter circuits, such as a P-type MOS transistor and an N-type MOS transistor. The load capacitance element LC is, specifically, a parasitic capacitance produced in the wiring line of the circuit13, a gate capacitance produced in the gate electrodes of the transistors of the circuit13, a junction capacitance produced in the buffer BF, etc.

Input signal IN1is supplied to the buffer BF. Using the input signal IN1, the buffer BF drives the load capacitance element LC. The buffer BF sends the input signal it receives to the subsequent circuit13(i.e., to the buffer BF of the subsequent circuit13).

The circuit13may be any type of circuit as long as it includes a buffer BF supplied with input signal IN1and operates based on input signal IN1.

FIG. 11is a block diagram showing the configuration of the control section11. The control section11comprises an output circuit11aand a pulse generating circuit11b.The output circuit11areceives signal IN2and outputs the same signal as signal OUT2. Based on signal IN3supplied from the transmission circuit12, the pulse generating circuit11binverts the polarity of signal IN2. As can be seen from this, the control section produces pulse signals on the basis of signals IN2and IN3.

A description will now be given of an operation of the semiconductor integrated circuit of the above configuration.FIG. 12is a timing chart illustrating the operation of the semiconductor integrated circuit10. First of all, signal IN2indicating the start of pulse transmission is supplied to the control section11. The polarity of signal IN2is predetermined. In response to signal IN2, the control section11outputs signal OUT2. Signal OUT2is supplied to the transmission circuit12as signal IN1. After rising (falling), signal IN1is transmitted through the circuits13of the transmission circuit12. When signal IN1is transmitted to the circuit13of the last stage, the transmission circuit12produces signal OUT1.

The control section11receives the signal OUT1produced from the transmission circuit12. The signal OUT1is received as signal IN3. Upon receipt of this signal, the control section lowers the level of signal OUT2(raises the level of signal OUT2). After this, signal OUT1falls (rises).

As detailed above, the present embodiment is featured in that signal IN1rises in response to the rise of signal IN2, which indicates the start of transmission. Using signal OUT1output from the transmission circuit12, signal IN1is lowered in level.

The present embodiment is advantageous in that pulse signals for driving the circuits13(load capacitance elements) can be transmitted to the circuits13without fail. Hence, all load capacitance elements LC can be reliably driven.

To enable the pulse signals to have a sufficient margin, a delay element may be used. The use of the delay element provides a long time between the reception of signal IN3and the falling (rising) of signal OUT2. This configuration is effective in providing a pulse width corresponding to the length of time delayed by the delay element. It is therefore possible to properly determine the pulse width in accordance with the number of circuits13incorporated in the transmission circuit.

Third Embodiment

The third embodiment is obtained by applying the transmission system described in relation to the second embodiment to the first embodiment.

FIG. 13is a schematic diagram illustrating a semiconductor integrated circuit20according to the third embodiment of the present invention. A semiconductor integrated circuit20comprises a first control section21, a second control section22, a shift register5and a storage circuit6. The first and second control sections21and22are connected to each other by means of signal line STPSET and signal line STPCLR.

Illustration of a circuit block group3to which data is supplied is omitted. Each of the first and second control sections21and22is provided with an output circuit4a,a transfer circuit4d,an input circuit4eand a command decode circuit4f(none of which is shown).

The first control section21receives transfer start signal FXOK and transfer end signal FXDONE. The first control section21supplies signal FCLR1to the shift register5. The shift register5receives the signal FCLR1as signal FCLRIN. The first control section21supplies signal SSOUT to the second control section22. The second control section22receives signal SSOUT as signal SSIN.

The second control section22supplies signal FSET2to the shift register5. The shift register5receives signal FSET2as FSETIN. The second control section22supplies signal SCOUT to the first control section21. The first control section21receives signal SCOUT as signal SCIN.

Signal FSETIN is transmitted sequentially to the flip-flop sections7of the shift register5. When signal FSETIN has been transmitted to all flip-flop sections7, the shift register5supplies signal FSETOUT to the first control section21. The first control section21receives signal FSETOUT as signal FSET1.

Signal FCLRIN is transmitted sequentially to the flip-flop sections7of the shift register5. When signal FCLRIN has been transmitted to all flip-flop sections7, the shift register5supplies signal FCLROUT to the second control section22. The second control section22receives signal FCLROUT as signal FCLR2.

FIG. 14is a block diagram showing the configuration of the first control section21depicted inFIG. 13. The first control section21comprises a first resetting signal-generating circuit21aand a first setting signal-generating circuit21b.The first resetting signal-generating circuit21areceives signal FXOK, signal FXDONE and signal SCIN. The first resetting signal-generating circuit21aoutputs signal FCLR1.

The first setting signal-generating circuit21breceives signal FSET1and outputs signal SSOUT.

FIG. 15is a block diagram showing the configuration of the second control section22depicted inFIG. 13. The second control section22comprises a second resetting signal-generating circuit22aand a second setting signal-generating circuit22b.The second resetting signal-generating circuit22areceives signal FCLR2and outputs signal SCOUT.

The second setting signal-generating circuit22breceives signal FCLR2and signal SSIN and outputs signal FSET2.

The first resetting signal-generating circuit21aand the second resetting signal-generating circuit22aproduce pulse signals whose polarity is negative (“1”→“0”→“1”). The first setting signal-generating circuit21band the second setting signal-generating circuit22bproduce pulse signals whose polarity is positive (“0”→“1”→“0”).

In the present embodiment, the setting and resetting operations are controlled by two control sections (namely, the first control section21and the second control section22). Needless to say, these control sections may be realized as one block. In this case, the first resetting signal-generating circuit21aand the second resetting signal-generating circuit22aare realized as one block, and the first setting signal-generating circuit21band the second setting signal-generating circuit22bare also realized as one block.

FIG. 16is a circuit diagram showing a specific configuration of the first control section21depicted inFIG. 14. The first control section21comprises inverter circuits30,31,36and38, an AND circuit32, NAND circuits33,34and35, and a delay element37. NAND circuits34and35jointly constitute a holding circuit. This holding circuit holds the data from inverter circuit38when signal FXDONE becomes “1.” After being held, the data is output to NAND circuit33. The delay element37receives the signal supplied from inverter circuit36, delays the rising of this signal for a predetermined time, and then outputs it. The delay time can be arbitrarily determined in accordance with the number of flip-flops FF included in the shift register5.

FIG. 17is a circuit diagram showing a specific configuration of the second control section22depicted inFIG. 15. The second control section22comprises an AND circuit40, NAND circuits41and42, a delay element43and an inverter circuit44. NAND circuits41and42jointly constitute a holding circuit. This holding circuit holds the data from inverter circuit44when signal FCLROUT (FCLR2) becomes “1.” After being held, the data is output. The delay element43delays the rising of signal SSIN for a predetermined time and then outputs it.

A description will now be given as to how the semiconductor integrated circuit20operates.FIG. 18is a timing chart illustrating the operation of the semiconductor circuit20. First of all, signal FXOK rises, and in response thereto, the first control section21raises the level of signal FCLRIN. When this signal, FCLRIN, is transmitted to signal FCLROUT (i.e. the signal FCLRIN is output from the shift register5as the signal FCLROUT), all flip-flops FF are released from the reset state.

In response to the rising of signal FCLROUT, the second control circuit22raises the level of signal FSETIN. Simultaneous with this, the second control section22raises the level of signal SCOUT (SCIN). When signal FSETIN is transmitted to signal FSETOUT, the first control section21raises the level of signal SSOUT (SSIN). Upon reception of signal SSIN, the second control section22lowers the level of signal FSETIN. Signal FSETIN is transmitted to signal FSETOUT.

As a result of the above operation, the data in all nonvolatile elements is set in flop-flops FF. Then, the data is transferred to the circuit block group3.

After the data transfer operation, signal FXDONE rises. In response to signal FXDONE, the first control section21lowers the level of signal FCLRIN. When this signal, FCLRIN, is transmitted to signal FCLROUT, the second control section22lowers the level of signal SCOUT (SCIN). Upon receipt of signal SCIN, the first control section21raises the level of signal FCLRIN.

Thereafter, the data in the nonvolatile elements is set in flip-flops FF once again, as it was at the start of the data transfer operation. After resetting all flip-flops FF at the end of the data transfer operation in this manner, the data in the nonvolatile elements can be set in the flop-flops FF.

The time between the rise of signal SSIN and the fall of signal FSETIN is provided by the delay element43. This enables the pulse signals of signal FSETIN to have a sufficient margin. The time between the fall of signal SCIN and the rise of signal FCLRIN is provided by the delay element37. This enables the pulse signals of signal FCLRIN to have a sufficient margin.

As described above, the present embodiment enables pulse signals, used for setting or resetting the shift registers5, to be transmitted to all flip-flops FF of the shift register5. Hence, the flip-flops can set or reset data in a reliable manner.

In addition, since the delay element is used for ensuring a sufficient pulse width, the pulse signals have a sufficient margin.