An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2015/083717 having an international filing date of 1 Dec. 2015, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2015-042633 file 4 Mar. 2015, the disclosures of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The disclosure relates to an analog-to-digital converter that converts an analog signal into a digital signal, and to a solid-state imaging apparatus and an electronic apparatus each including the analog-to-digital converter.

BACKGROUND ART

Examples of a solid-state imaging apparatus that images an image may include a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor. In recent years, the CMOS image sensor has attracted attention for requests such as downsizing.

The CMOS image sensor includes an analog to digital (AD) conversion section (hereinafter, referred to as an AD conversion section). The AD conversion section performs AD conversion on an analog electric signal supplied from a pixel that performs photoelectric conversion. A so-called column-parallel AD conversion section is employed as the AD conversion section of the CMOS image sensor for requests such as process acceleration. (for example, PTL 1).

The column-parallel AD conversion section is able to perform AD conversion, for each column, on electric signals supplied from two or more (for example, all) pixels of a pixel group arranged in each row. For example, in the column-parallel AD conversion section, AD converters (ADCs: Analog-to-digital converters) of the number equivalent to the number of columns of the pixels are arranged side by side along the row direction. Each of the ADCs is configured to perform AD conversion of the electric signal that is supplied from a pixel of corresponding column.

Examples of the ADC may include a so-called reference signal comparative ADC. The reference signal comparative ADC includes a comparator and a counter, and compares a predetermined reference signal with an electric signal supplied from a pixel to perform the AD conversion of the electric signal. In PTL 1 mentioned above, a single slope ADC is used as the reference signal comparative ADC.

In the single slope ADC, the comparator compares a reference signal whose level is varied with a fixed gradient, such as a ramp signal, with the electric signal supplied from the pixel. The counter counts a time necessary for level change of the reference signal until the reference signal and the electric signal are coincident with each other in level. As a result, the signal is converted into a digital signal.

Sampling capacitances are coupled in series with respective paired differential input terminals of the comparator. To obtain favorable characteristics of the ADC, small fluctuation of a capacitance value (small bias dependency of the capacitance value) with respect to the input signal is desired in the sampling capacitances.

In contrast, a comb-shaped wiring capacitor (for example, PTL 2) has been proposed in which paired comb-shaped wiring lines are so oppositely disposed as to engage with each other and a parasitic capacitance caused between the opposite wiring lines is used. The comb-shaped wiring capacitor is small in bias dependency of the capacitance value and is mountable on a semiconductor substrate at a low cost.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Crosstalk characteristics of the signal is one of important performance indices for the column-parallel AD conversion section as mentioned above. In the column-parallel AD conversion section, the crosstalk characteristics between comparators configuring the respective ADCs (a comparator of an ADC in a certain column and a comparator of an ADC in a column adjacent to the certain column) influence crosstalk characteristics of the entire AD conversion section.

One of factors deteriorating the crosstalk characteristics between the adjacent comparators is a parasitic capacitance (a coupling capacitance) that occurs between the comparators to join the two comparators.

When, in the column-parallel ADC described in the foregoing PTL 1, the sampling capacitances configuring a portion of the comparator are replaced with, for example, the comb-shaped wiring capacitors as described in the foregoing PTL 2, it is desired to design the capacitor with layout arrangeable within a predetermined space of the pixel array section while retaining a certain capacitance value or more.

In recent years, however, precision of semiconductor process has been improved and a pixel size has been reduced, for example. When a device is designed to be arrangeable within a predetermined space while obtaining a desired capacitance value, the following defects may occur. In other words, a facing area between the sampling capacitances of the comparator is increased between the adjacent ADCs, which results in large parasitic capacitance between the adjacent ADCs. This causes deterioration of the crosstalk characteristics as mentioned above.

Such deterioration of the crosstalk characteristics between the ADCs and deterioration of the crosstalk characteristics of the AD conversion section may cause deterioration of image quality, for example, color mixture of an image captured by a CMOS image sensor, bleeding of brightness, and expansion of influence of a defective pixel.

Therefore, it is desirable to provide an analog-to-digital converter, a solid-state imaging apparatus, and an electronic apparatus that make it possible to suppress crosstalk of a signal.

An analog-to-digital converter according to an embodiment of the disclosure includes: a comparator having paired differential input ends; and first and second capacitors provided at the respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

In the analog-to-digital converter according to an embodiment of the disclosure, the first and the second capacitors provided at the respective differential input ends of the comparator respectively include the plurality of first sub-capacitors and the plurality of second sub-capacitors that are coupled side by side with one another. The first and second sub-capacitors are mixedly arranged in each column of a plurality of columns. This reduces a facing area of the capacitors between the comparators in adjacent columns, for example, even if the first and second sub-capacitors are used in a state of being arranged side by side, as compared with the case where the capacitors are linearly arranged for each column.

A solid-state imaging apparatus according to an embodiment of the disclosure includes the above-described analog-to-digital converter according to an embodiment of the disclosure.

An electronic apparatus according to an embodiment of the disclosure includes the above-described analog-to-digital converter according to an embodiment of the disclosure.

According to the analog-to-digital converter of an embodiment of the disclosure, the first and second capacitors are provided at the respective differential input ends of the comparator, and the first and second capacitors respectively include the plurality of first and second sub-capacitors that are coupled side by side with one another. The first and second sub-capacitors are mixedly arranged in each column of a plurality of columns. This reduces a facing area of the capacitors between the comparators in adjacent columns, for example, even if the first and second sub-capacitors are used in a state of being arranged side by side. This makes it possible to suppress a parasitic capacitance occurring between the adjacent converters. Thus, it is possible to suppress crosstalk of a signal.

According to the solid-state imaging apparatus and the electronic apparatus of an embodiment of the disclosure, provision of the above-described analog-to-digital converter according to an embodiment of the disclosure makes it possible to suppress crosstalk of a signal occurring between the analog-to-digital converters. Thus, it is possible to suppress deterioration of a captured image.

Note that the above-described contents are examples of the disclosure. Effects of an embodiment of the disclosure are not limited to those described above, and may be effects other than those described above or may thither include other effects.

DESCRIPTION OF EMBODIMENTS

Some embodiments of the disclosure are described in detail below with reference to drawings. Note that description is given in the following order.

1. First embodiment (an example of a solid-state imaging apparatus using an ADC in which sampling capacitances are each divided into a plurality of sub-capacitances, and the plurality of sub-capacitances are coupled side by side with one another and are so arranged as to meander in a plane direction)
2. First configuration example (an example in a case where sampling capacitances are disposed in four layers)
3. Modification example of first configuration example (an example in a case where sampling capacitances are disposed in three layers)
4. Second embodiment and second configuration example (an example in a case where sampling capacitances are so disposed as to meander in both of a plane direction and a stacked-layer direction)
5. Third embodiment and third configuration example (an example in a case where sampling capacitances are so disposed as to meander in a stacked-layer direction)
6. Fourth embodiment and fourth configuration example (an example in a case where electrostatic shielding layers are disposed to sandwich sampling capacitances)
7. Modification example of fourth embodiment (an example in a case where an electrostatic shielding layer is disposed to cover sampling capacitances)
8. Modification example 1 (another example of a circuit configuration of sampling capacitances)
9. Modification examples 2-1 and 2-2 (configuration examples of an MOS capacitor and an MIM capacitor)
10. Application examples 1 to 6 (examples of an electronic apparatus)

First Embodiment

FIG. 1is a diagram illustrating an entire configuration of a solid-state imaging apparatus (a solid-state imaging apparatus1) according to a first embodiment of the disclosure. The solid-state imaging apparatus1may be, for example, a CMOS image sensor mounted with an analog-to-digital converter (ADC50A) of the disclosure. The solid-state imaging apparatus1includes a pixel array section10serving as an imaging section, a row selection circuit20serving as a pixel drive section, a horizontal transfer scanning circuit30, and a timing control circuit40. The solid-state imaging apparatus1also includes an AD conversion section50, a digital analog converter (DAC)60serving as a ramp signed generator, a horizontal transfer line70, an amplifier (S/A)80, and a signal processing circuit90.

The pixel array section10is configured of pixels (pixel circuits) that are arranged in matrix. Each of the pixels may include, for example, a photoelectric conversion element such as a photodiode (PD) and an in-pixel amplifier.

FIG. 2is a diagram illustrating an example of the pixel circuit. For example, the pixel circuit may include a photoelectric conversion element211, and four transistors of a transfer transistor212, a reset transistor213, an amplification transistor214, and a selection transistor215as active elements.

The photoelectric conversion element211is an element that converts incident light into charges (for example, electrons) of an amount corresponding to a quantity of the light, and may include, for example, a photodiode.

The transfer transistor212is coupled between the photoelectric conversion element211and a floating diffusion FD serving as an input node. A gate (a transfer gate) of the transfer transistor212is coupled with a transfer control line LTRG. A predetermined control signal (a transfer signal TRG) is provided to the gate of the transfer transistor212through the transfer control line line LTRG. The electrons photoelectrically converted by the photoelectric conversion element211are transferred to the floating diffusion FD by the transfer transistor212.

The reset transistor213is coupled between the floating diffusion FD and a power line LVDD through which a power voltage VDD is supplied, and a reset signal RST that is a control signal is provided to a gate of the reset transistor213through a reset control line LRST. The potential of the floating diffusion FD is reset to the potential of the power line LVDD by the reset transistor213.

The floating diffusion FD is coupled with a gate of the amplification transistor214. In other words, the floating diffusion FD functions as an input node of the amplification transistor214.

The amplification transistor214and the selection transistor215are coupled in series with each other between the power line LVDD and a perpendicular signal line LSGN. The amplification transistor214is coupled with the perpendicular signal line LSGN through the selection transistor215, and configures, together with a constant current source IS outside the pixel array section10, a source follower. A selection signal SEL that is a control signal corresponding to an address signal is provided to a gate of the selection transistor215through a selection control line LSEL, thereby turning on the selection transistor215. When the selection transistor215is turned on, the amplification transistor214amplifies the potential of the floating diffusion FD, and supplies a voltage corresponding to the potential, to the perpendicular signal line LSGN. The voltage supplied from each of the pixels is provided to the AD conversion section50through the perpendicular signal line LSGN.

The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL that are wired in the pixel array section10are wired for each row unit of the pixel array. The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL are coupled with the row selection circuit20.

The row selection circuit20may include, for example, an unillustrated shift register circuit and an unillustrated predetermined logic circuit, and controls operation of the pixels arranged on each row of the pixel array section10through the control lines (the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL). The row selection circuit20may perform image drive control by so-called a rolling shutter method (a line sequential driving method) or a global shutter method (a face collective driving method), for example, according to a driving method of an unillustrated exposure shutter.

The horizontal transfer scanning circuit30may include, for example, an unillustrated shift register circuit and an unillustrated address decoder, and transfers the AD converted signals of the respective pixel rows to the signal processing circuit90through the horizontal transfer line70.

The timing control circuit40controls operation of the row selection circuit20, the horizontal transfer scanning circuit30, the AD conversion section50, and the DAC60. More specifically, the timing control circuit40includes a timing generator that generates various kinds of timing signals (control signals), and performs drive control of the row selection circuit20, the horizontal transfer scanning circuit30, the AD conversion section50, and the DAC60, based on the various kinds of timing signals.

The AD conversion section50is a column-parallel AD conversion section, and includes a plurality of ADCs50A that are each arranged (in columns) along a column direction of the pixel array. Each of the ADCs50A may be a so-called single slope ADC that includes a comparator51, a counter52, and a latch53, for example. Each of the ADCs50A may have, for example, an n-bit digital signal conversion function, and is disposed for each perpendicular signal line LGSN.

The comparator51is a differential circuit that compares a reference voltage generated by the DAC60(a reference voltage Vslop (a RAMP signal) having RAMP waveform) with an analog signal supplied from the pixels for each row through the perpendicular signal line LSGN.

FIG. 3is a diagram illustrating a configuration example of the comparator51. The comparator51includes sampling capacitances (sampling capacitances C1and C2) at respective paired differential input ends. More specifically, the comparator51may include, for example, a first amplifier511, an isolator512, a second amplifier513, and an automatic zeroing switch AZSW. The sampling capacitance C1is coupled in series with one (node a) of input ends of the first amplifier511, and the sampling capacitance C2is coupled in series with the other input end (node b). Note that the specific configurations of the sampling capacitances C1and C2are described later.

The first amplifier511includes a transconductance (Gin) amplifier. The isolator512is disposed to be coupled with an output end (node c) of the first amplifier511and has a function of suppressing voltage fluctuation. More specifically, the isolator512is so configured as to separate the voltage of the node c from node d of a large amplitude voltage and to maintain the voltage of the node c constant as much as possible. The second amplifier513is provided at an output stage of the comparator51. Note that two or more amplifiers may be provided at the output stage of the comparator51. The automatic zeroing switch AZSW is coupled between the node d on the output side of the isolator512and the node b of the high impedance.

The counter52is a circuit section that counts a comparison time of the comparator51. An output of each latch53may be coupled with, for example, the horizontal transfer line70having 2n-bit width. The signal supplied to the horizontal transfer line70is provided to the signal processing circuit90through the amplifier80.

The pixel circuits, the row selection circuit20, the horizontal transfer scanning circuit30, the timing control circuit40, the AD conversion section50, the DAC60, the horizontal transfer line70, the amplifier80, and the signal processing circuit90mentioned above are provided on an unillustrated semiconductor substrate. These circuits may be configured by coupling, for example, a photodiode, two or more MOSFETs having different gate insulation film thickness, a bipolar transistor, a resistor, and a capacitor with one another on the semiconductor substrate through multilayer wiring. These circuits may be formed on the semiconductor substrate through a typical CMOS process. In the following, the layout of the sampling capacitances according to a present embodiment is described.

(Layout Configuration of Sampling Capacitances)

As mentioned above, in the column-parallel AD conversion section50, two sampling capacitances C1and C2are disposed at the respective differential input ends of the comparator51of each ADC50A. The specific layout configuration of the sampling capacitances C1and C2is described below.

FIG. 4is a diagram illustrating an outline of layout of sampling capacitances (C1and C2) that are disposed in an ADC(n) on a certain column of the plurality of ADCs50A and sampling capacitances (denoted by “C3” and “C4” for convenience) that are disposed in an ADC(n+1) adjacent to the ADC(n). The sampling capacitances C1and C3are coupled in series with the input terminal on DAC side of the comparator51(a terminal to which the reference voltage (Vslop) is provided from the DAC60). The sampling capacitances C2and C4are coupled in series with an input terminal on VSL side of the comparator51(a terminal to which the analog signal supplied for each pixel row through the perpendicular signal line LSGN is provided).

As illustrated, in the present embodiment, each of the sampling capacitances C1and C2is divided into a plurality of sub-capacitances. More specifically, in the ADC(n), the sampling capacitance C1includes a plurality of (four, in this case) sub-capacitances C11, C12, C13, and C14that are coupled side by side with one another. The sampling capacitance C2includes a plurality of (four, in this case) sub-capacitances C21, C22, C23, and C24that are coupled side by side with one another. Likewise, in the ADC(n+1), the sampling capacitance C3corresponds to the sampling capacitance C1, and includes four sub-capacitances C31, C32, C33, and C34that are coupled side by side with one another. The sampling capacitance C4corresponds to the sampling capacitance C2, and includes four sub-capacitances C41, C42, C43, and C44that are coupled side by side with one another. Note that the sub-capacitances C31to C34and C41to C44are reference numerals assigned for description, and are arranged in layout equivalent to the layout of the sub-capacitances C11to C14and C21to C24.

In other words, the sampling capacitance C1corresponds to a combined capacitance of the sub-capacitances C11to C14, and has a capacitance value that is a sum of capacitance values of the respective sub-capacitances C11to C14. The sampling capacitance C2corresponds to a combined capacitance of the sub-capacitances C21to C24, and has a capacitance value that is a sum of capacitance values of the respective sub-capacitances C21to C24.

Note that the sampling capacitances C1and C2respectively correspond to a specific but non-limiting example of a “first capacitor” and a “second capacitor” in one embodiment of the disclosure. Also, the sub-capacitances C11to C14and the sub-capacitances C21to C24respectively correspond to a specific but non-limiting example of “first sub-capacitors” and “second sub-capacitors” in one embodiment of the disclosure.

In the present embodiment, the four sub-capacitances C11to C14that configure the sampling capacitance C1and the four sub-capacitances C21to C24that configure the sampling capacitance C2are arranged in a plurality of columns (two columns in this case). Also, in each column, the sub-capacitances C11to C14and the sub-capacitances C21to C24are mixedly arranged. More specifically, the sub-capacitances C11to C14and the sub-capacitances C21to C24are each so arranged as not to form a straight line (linearly) but to meander (in a zigzag manner) in a planar view (in a plane direction).

More specifically, in two columns of the ADC(n), the sub-capacitances C11to C14and the sub-capacitances C21to C24are arranged to alternate with each other (alternately). In other words, any of the sub-capacitances C11to C14and any of the sub-capacitances C21to C24are so arranged as to be adjacent to each other in a row direction d1or in a column direction d2. The sub-capacitances C11to C14and the sub-capacitances C21to C24, however, may not be necessarily arranged alternately (at every other sub-capacitance). The arrangement and the shapes of the sub-capacitances may be departed from the above-described example as long as unevenness of the capacitances between the sampling capacitances C1and C2is allowed.

Each of the sub-capacitances C11to C14and C21to C24may have, for example, paired electroconductive layers (wiring layers). For example, in the sub-capacitance C11, paired comb-shaped electroconductive layers c111and c112are so oppositely disposed as to engage with each other. A dielectric film (not illustrated) such as an interlayer insulation film is disposed between the electroconductive layers c111and c112. The capacitance value of the sub-capacitance C11is designed depending on, for example, a facing area and a distance between the electroconductive layers c111and c112. Likewise, each of other sub-capacitances C12to C14and C21to C24also has paired comb-shaped electroconductive layers. The capacitance values of the respective sub-capacitances C12to C14and C21to C24may be designed to be equivalent to one another.

FIG. 5is a diagram schematically illustrating a cross-sectional configuration as viewed in an arrow direction of line IA-IA inFIG. 4. Each of the sub-capacitances C11to C14and C21to C24includes the paired electroconductive layers c111and c112, and the electroconductive layers c111and c112may be formed through interlayer coupling (through coupling with each other through an unillustrated via), for example, in two or more layers. More specifically, the electroconductive layers c111and c112are formed with use of two or more wiring layers that are stacked with an interlayer insulating film in between. In this case, the electroconductive layers c111and c112are formed with use of four wiring layers M1to M4. In other words, the sub-capacitances C11to C14and C21to C24are formed throughout the wiring layers M1to M4. The electroconductive layers c111and c112of each of the sub-capacitances C11to C14and C21to C24face each other in each of the wiring layers M1to M4.

The sub-capacitances C11to C14may desirably have the layout that is mirror-inverted to the layout of the sub-capacitances C21to C24, in order to equalize the capacitance values of the respective sub-capacitances C11to C14and the capacitance values of the respective sub-capacitances C21to C24and to eliminate unevenness of the capacitance values between the sampling capacitances C1and C2.

In the solid-state imaging apparatus1according to the present embodiment, when light enters the pixel array section10, the incident light is received by the photoelectric conversion element211in each pixel and is photoelectrically converted. A signal charge generated by the photoelectric conversion element211is transferred to the floating diffusion FD by the transfer transistor212. Thereafter, when the selection transistor215is turned on, the potential of the floating diffusion FD is amplified by the amplification transistor214and the voltage corresponding to the potential is supplied to the perpendicular signal line LSGN. The voltage supplied from each pixel through the perpendicular signal line LSGN is provided to the AD conversion section50. In the AD conversion section50, a signal for one pixel row is provided to the ADC50A in the corresponding column, and is subjected to the AD conversion. The AD-converted signal is transmitted to the horizontal transfer line70, and is provided to the signal processing circuit90through the amplifier80.

In this case, in the AD conversion section50, the ADCs50A are arranged side by side for each pixel column. The comparator51is provided in each of the ADCs50A, and the sampling capacitances C1and C2are disposed at the respective paired differential input ends of the comparator51. Effects by the layout of the sampling capacitances C1and C2are described below.

One of important performance indices of the ADC conversion section50lies in crosstalk characteristics of a signal. In the column-parallel AD conversion section50, crosstalk characteristics between the comparators51of the respective ADCs50A influence crosstalk characteristics of the entire AD conversion section50. One of factors deteriorating the crosstalk characteristics between the adjacent comparators51is a parasitic capacitance (a coupling capacitance) occurring between the adjacent comparators51.

Here, as a comparative example, a configuration is described, in which, in the column-parallel ADC, the sampling capacitance configuring a portion of the comparator is replaced with, for example, a comb-shaped wiring capacitor illustrated inFIG. 6. In the comparative example, a sampling capacitance100is configured of paired comb-shaped electroconductive layers101and102. The electroconductive layers101and102respectively include a plurality of comb teeth101aand a plurality of comb teeth102athat are so arranged alternately as to engage with each other. This makes it possible to increase a facing area between the electroconductive layers101and102and to secure a capacitance value equal to or larger than a certain value.

When such a sampling capacitance100is used in the column-parallel ADC, however, an arrangement space is restricted. Thus, to secure the capacitance value equal to or larger than the certain value, the layout extends long in a column direction, for example, as illustrated inFIG. 7. For example, when the above-described comb-shaped wiring capacitor is formed with use of four wiring layers and the wiring space is designed with a minimum value of a process rule in the CMOS process having a process rule of 45 nm, the capacitance value per unit area may be about 2.5 fF/μm2. When the comb-shaped wiring capacitor having the structure is used, if the capacitance value of about 250 fF is necessary for one sampling capacitance, the sampling capacitance100is disposed with a pitch of about 2 μm whereas the pixel pitch is about 3 μm. As a result, the length of the sampling capacitance100in the column direction may be, for example, about 150 μm, which results in layout in which rectangular comb-shaped wiring capacitors each extremely elongated in the column direction are arranged in the row direction. Such layout is not practical.

Also, as illustrated inFIG. 8andFIG. 9, in the above-described comb-shaped wiring capacitor, sampling capacitances C101and C102that are disposed in an ADC(n) and sampling capacitances C103and C104that are disposed in an ADC(n+1) adjacent to the ADC(n) are disposed in proximity to each other. Thus, the sampling capacitance C102and the sampling capacitance C103are disposed to face each other between the ADC(n) and the ADC(n+1), and the facing area therebetween (a dashed part X) is increased. As a result, the parasitic capacitance between the adjacent ADCs is increased, which causes deterioration of the crosstalk characteristics of the signal.

In addition, in recent years, the size reduction of the pixel size is progressed, for example, and a column pitch, namely, the distance between the adjacent ADCs tends to be further decreased (shortened). When the column pitch of the ADCs is decreased, the distance between the two comparators of the ADCs in the adjacent columns is also decreased. This causes the above-described parasitic capacitance between the sampling capacitances to be increased, and the crosstalk characteristics are easily deteriorated accordingly.

In contrast, in the present embodiment, the sampling capacitances C1and C2provided at the respective differential input ends of the comparator51of each of the ADCs50A respectively include the plurality of sub-capacitances C11to C14and C21to C24that are coupled side by side with one another. The plurality of sub-capacitances C11to C14and C21to C24are disposed in two columns while being mixed in each column. For example, the plurality of sub-capacitances C11to C14and C21to C24may be alternately disposed in a zigzag manner in two columns. This reduces the facing area (the dashed part X) between the sampling capacitances C2and C3to about a half of the facing area compared with the case where the sampling capacitances are so arranged to extend linearly in the column direction as with the above-described comparative example. Also, flexibility of the layout of the sampling capacitances C1and C2is enhanced.

Accordingly, the parasitic capacitance between the adjacent ADCs50A is reduced, which makes it possible to improve deterioration of the crosstalk characteristics of the signal without increase in the pixel pitch.

For example, as illustrated in a simulation result ofFIG. 10, in Example using the above-described sampling capacitances C1and C2, a crosstalk amount is reduced to about a half of the crosstalk amount of the comparative example using the sampling capacitance100. Note that the abscissa in the characteristic diagram ofFIG. 10indicates a level of a signal supplied to the sampling capacitance C3of the ADC(n+1), and the ordinate indicates a standardized value of a signal amount detected in the sampling capacitance C2of the ADC(n).

Also, the mirror-inverted layout between the sub-capacitances C11to C14and the sub-capacitances C21to C24provides the following advantages. Since the sub-capacitances C11to C14(C21to C24) are disposed separately (discretely) from one another in the sampling capacitance C1(C2), film thickness gradient of each wiring (of the electroconductive layers c111and c112) may be varied. Even in such a case, the combined capacitance is easily equalized due to symmetric property between the sampling capacitances C1and C2. Therefore, the capacitance variation is reduced and reduction of the characteristic variation in the ADCs50A for each column is expected, as compared with the comparative example.

FIG. 11is a diagram illustrating the variation in the capacitance value of the sampling capacitances in the comparative example and Example. The capacitance values are measured data acquired from some prototype wafers. As compared with the comparative example, it was confirmed that the variation in the capacitance value was reduced by about 30% in Example.

As mentioned above, in the present embodiment, the sampling capacitances C1and C2provided at the respective differential input ends of the comparator51of each of the ADCs50A respectively include the plurality of sub-capacitances C11to C14and C21to C24that are coupled side by side with one another. The plurality of sub-capacitances C11to C14and C21to C24are arranged in two columns while being mixed in each column. This makes it possible to reduce the facing area between the sampling capacitances C2and C3. Thus, it is possible to suppress the crosstalk of the signal.

Accordingly, the solid-state imaging apparatus1includes the AD conversion section50that is configured of such an ADC50A, which makes it possible to suppress deterioration of an image such as color mixture and brightness bleeding of a captured image.

In the following, specific configuration examples of the sampling capacitances C1and C2described in the foregoing first embodiment are described.

First Configuration Example

FIG. 12is a schematic diagram to explain the sampling capacitances C1and C2according to a first configuration example.FIG. 13is a circuit diagram to explain ends for wiring coupling (extraction electrodes) of the sampling capacitances C1and C2.FIG. 14is a schematic plan view illustrating wiring layout of each of the wiring layer (M1) to the wiring layer (M4) of the sampling capacitances C1and C2.FIG. 15Ais a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line IB-IB inFIG. 12, andFIG. 15Bis a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line IC-IC inFIG. 12.

Note that,FIG. 12illustrates an outline of layout of sampling capacitances (C1and C2) that are disposed in an ADC(n) in a certain column of the plurality of ADCs50A and sampling capacitances (denoted by “C3” and “C4” for convenience) that are disposed in an ADC(n+1) adjacent to the ADC(n). As described in the foregoing first embodiment, the sampling capacitance C1corresponds to the combined capacitance of the sub-capacitances C11to C14, and the sampling capacitance C2corresponds to the combined capacitance of the sub-capacitances C21to C24. Also, the sub-capacitances C11to C14and the sub-capacitances C21to C24are arranged in two columns, and the sub-capacitances C11to C14and the sub-capacitances C21to C24are so disposed as to meander (in a zigzag manner).

The sampling capacitances C1and C2may be, for example, comb-shaped wiring capacitances that are each configured of two or more wiring layers provided on an unillustrated semiconductor substrate. Note that,FIG. 14illustrates the wiring layout of only the sampling capacitances C1and C2; however, the sampling capacitances C3and C4are also arranged in the layout similar to that of the sampling capacitances C1and C2. For example, as illustrated inFIG. 14,FIG. 15A, andFIG. 15B, the sub-capacitances C11to C14and C21to C24may be formed with use of the four wiring layers M1to M4. In this example, the positions of the respective sub-capacitances C11to C14and C21to C24are the same among the wiring layers M1to M4in a planar view (in a plane direction). In other words, the electroconductive layer disposed in each of the wiring layers M1to M4is coupled with the electroconductive layer right thereabove through interlayer coupling.

For example, each of the sub-capacitances C11to C14may include paired electroconductive layers521and522(FIG. 15AandFIG. 15B) that are disposed to face each other. The electroconductive layer521is configured through interlayer coupling of an electroconductive layer521aof the wiring layer M1, an electroconductive layer521bof the wiring layer M2, an electroconductive layer521cof the wiring layer M3, and an electroconductive layer521dof the wiring layer M4. The electroconductive layer522is configured through interlayer coupling of an electroconductive layer522aof the wiring layer M1, an electroconductive layer522bof the wiring layer M2, an electroconductive layer522cof the wiring layer M3, and an electroconductive layer522dof the wiring layer M4. The wiring layers M1to M4are electrically coupled with one another through vias Ha, Hb, and Hc. Note that, in the wiring layers M1to M4ofFIG. 14, portions configuring the sub-capacitances C11to C14are surrounded by dashed lines.

Likewise, each of the sub-capacitances C21to C24includes paired electroconductive layers523and524(FIG. 15AandFIG. 15B) that are disposed to face each other. The electroconductive layer523is configured through interlayer coupling of an electroconductive layer523aof the wiring layer M1, an electroconductive layer523bof the wiring layer M2, an electroconductive layer523cof the wiring layer M3, and an electroconductive layer523dof the wiring layer M4. The electroconductive layer524is configured through interlayer coupling of an electroconductive layer524aof the wiring layer M1, an electroconductive layer524bof the wiring layer M2, an electroconductive layer524cof the wiring layer M3, and an electroconductive layer524dof the wiring layer M4. The wiring layers M1to M4are electrically coupled with one another through the vias Ha, Hb, and Hc. Note that, in the wiring layers M1to M4ofFIG. 14, portions configuring the sub-capacitances C21to C24are surrounded by alternate long and short dash lines.

The wiring layer525(the first wiring layer) to couple the sub-capacitances C11to C14side by side with one another is disposed in a layer different from a layer of the wiring layer526(the second wiring layer) to couple the sub-capacitances C21to C24side by side with one another. In this case, the wiring layer525is disposed in the wiring layer M1, and the wiring layer526is disposed in the wiring layer M3. In the wiring layer M1, the electroconductive layers521aand522aconfiguring the sub-capacitances C11to C14and the wiring layer525are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. Also, in the wiring layer M3, the electroconductive layers523cand524cconfiguring the sub-capacitances C21to C24and the wiring layer526are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. Note that the rectangular wave shape including the wiring layers525and526may be disposed in other layers without being limited to the wiring layers M1and M3, or may be disposed in three or more layers.

In the wiring layer M4, portions of the electroconductive layers521d,522d,523d, and524dare extended as ends a1, a2, b1, and b2(the extraction electrodes), respectively, illustrated inFIG. 13. More specifically, a portion of the electroconductive layer521dconfiguring the sub-capacitance C11serves as the end a1, and a portion of the electroconductive layer522dconfiguring the sub-capacitance C14serves as the end a2. A portion of the electroconductive layer523dconfiguring the sub-capacitance C21serves as the end b1, and a portion of the electroconductive layer524dconfiguring the sub-capacitance C24serves as the end b2.

As mentioned above, it is possible to arrange the sub-capacitances C11to C14and the sub-capacitances C21to C24in a meandering layout in a planar view while being coupled side by side with one another with use of the four wiring layers M1to M4.

Modification Example of First Configuration Example

In the above-described first configuration example, the sub-capacitances C11to C14and C21to C24are formed with use of the four wiring layers M1to M4. The number of the wiring layers, however, is not limited to four, and two or more layers are sufficient. Also, the number of the wiring layers is not limited to an even number, and an odd number of layers may also be used. In addition, other layers may be interposed among the wiring layers. In this way, the combination of the wiring layers may be selected in various ways. As an example, a case where three wiring layers M1to M3are used is described in the present modification example.

FIG. 16is a schematic plan view illustrating wiring layout of each of the wiring layer (M1) to the wiring layer (M3) of the sampling capacitances C1and C2according to the present modification example.FIG. 17Ais a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line1B-1B ofFIG. 12, andFIG. 15Bis a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line IC-IC ofFIG. 12.

Also in the present modification example, the sub-capacitances C11to C14and the sub-capacitances C21to C24are arranged in two columns, and the sub-capacitances C11to C14and the sub-capacitances C21to C24are so disposed as to meander (in a zigzag manner). Further, the sampling capacitances C1and C2may be, for example, comb-shaped wiring capacitances that are provided on an unillustrated semiconductor substrate. Note that,FIG. 16illustrates the wiring layout of only the sampling capacitances C1and C2; however, the sampling capacitances C3and C4are also disposed in the layout similar to that of the sampling capacitances C1and C2.

In the present modification example, however, the sub-capacitances C11to C14and C21to C24are formed with use of the three wiring layers M1to M3. Also in this modification example, the positions of the respective sub-capacitances C11to C14and C21to C24are the same among the wiring layers M1to M3in a planar view, as with the above-described first configuration example. In other words, the electroconductive layer disposed in each of the wiring layers M1to M3is coupled with the electroconductive layer right thereabove through interlayer coupling.

For example, each of the sub-capacitances C11to C14may include the paired electroconductive layers521and522. (FIG. 17AandFIG. 17B) that are disposed to face each other. The electroconductive layer521is configured through interlayer coupling of the electroconductive layer521aof the wiring layer M1, the electroconductive layer521bof the wiring layer M2, and the electroconductive layer521cof the wiring layer M3. The electroconductive layer522is configured through interlayer coupling of the electroconductive layer522aof the wiring layer M1, the electroconductive layer522bof the wiring layer M2, and the electroconductive layer522cof the wiring layer M3. The wiring layers M1to M3are electrically coupled with one another through the vias Ha and Hb. Note that, in the wiring layers M1to M3ofFIG. 16, portions configuring the sub-capacitances C11to C14are surrounded by dashed lines.

Likewise, each of the sub-capacitances C21to C24includes the paired electroconductive layers523and524(FIG. 17AandFIG. 17B) that are disposed to face each other. The electroconductive layer523is configured through interlayer coupling of the electroconductive layer523aof the wiring layer M1, the electroconductive layer523bof the wiring layer M2, and the electroconductive layer523cof the wiring layer M3. The electroconductive layer524is configured through interlayer coupling of the electroconductive layer524aof the wiring layer M1, the electroconductive layer524bof the wiring layer M2, and the electroconductive layer524cof the wiring layer M3. The wiring layers M1to M3are electrically coupled with one another through the vias Ha and Hb. Note that, in the wiring layers M1to M3ofFIG. 16, portions configuring the sub-capacitances C21to C24are surrounded by alternate long and short dash lines.

The wiring layer525(the first wiring layer) to couple the sub-capacitances C11to C14side by side with one another is disposed in a layer different from a layer of the wiring layer526(the second wiring layer) to couple the sub-capacitances C21to C24side by side with one another. In this case, the wiring layer525is disposed in the wiring layer M1, and the wiring layer526is disposed in the wiring layer M3. In the wiring layer M1, the electroconductive layers521aand522aconfiguring the sub-capacitances C11to C14and the wiring layer525are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. Also, in the wiring layer M3, the electroconductive layers523cand524cconfiguring the sub-capacitances C21to C24and the wiring layer526are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. Note that the rectangular wave shape including the wiring layers525and526may be disposed in other layers without being limited to the wiring layers M1and M3, or may be disposed in all of the three layers.

In the wiring layer M2portions of the electroconductive layers521b,522b,523b, and524bare extended as the ends a1, a2, b1, and b2, respectively, illustrated inFIG. 13. More specifically, a portion of the electroconductive layer521bconfiguring the sub-capacitance C11serves as the end art, and a portion of the electroconductive layer522bconfiguring the sub-capacitance C14serves as the end a2. A portion of the electroconductive layer523bconfiguring the sub-capacitance C21serves as the end b1, and a portion of the electroconductive layer524bconfiguring the sub-capacitance C24serves as the end b2.

As mentioned above, it is possible to arrange the sub-capacitances C11to C14and the sub-capacitances C21to C24in the meandering layout in a planar view while being coupled side by side with one another with use of the three wiring layers M1to M3.

Hereinafter, other embodiments of the above-described embodiment are described. Not that the components similar to those of the above-descried embodiment are denoted by the same reference numerals, and the description thereof is omitted.

Second Embodiment

FIG. 18is a diagram illustrating an outline of layout of sampling capacitances according to a second embodiment of the disclosure.FIG. 19is a circuit diagram to explain ends for wiring coupling (extraction electrodes) of the sampling capacitances C1and C2.FIG. 20is a schematic plan view illustrating wiring layout of each of the wiring layer (M1) to the wiring layer (M4) of the sampling capacitances C1and C2according to a second configuration example.FIG. 21Ais a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line ID-ID inFIG. 18, andFIG. 219is a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line IE-IE inFIG. 18.

Note that,FIG. 18illustrates an outline of layout of sampling capacitances (C1and C2) that are disposed in an ADC(n) in a certain column of the plurality of ADCs50A and sampling capacitances (denoted by “C3” and “C4” for convenience) that are disposed in an ADC(n+1) adjacent to the ADC(n). As described in the foregoing first embodiment, the sampling capacitance C1corresponds to the combined capacitance of the sub-capacitances C11to C14, and the sampling capacitance C2corresponds to the combined capacitance of the sub-capacitances C21to C24.

Also,FIG. 20illustrates the wiring layout of only the sampling capacitances C1and C2; however, the sampling capacitances C3and C4(C31to C34and C41to C44) are also arranged in the layout similar to that of the sampling capacitances C1and C2.

The sampling capacitances C1and C2according to the present embodiment are disposed at respective paired differential input ends of the comparator51that is similar to that of the above-described first embodiment, and are suitably used in the ADC50A or the AD conversion section50including the comparator51. Also in the present embodiment, as illustrated inFIG. 20,FIG. 21A, andFIG. 21B, the sub-capacitances C11to C14and C21to C24are provided on an unillustrated semiconductor substrate with use of the four wiring layers M1to M4, as with the above-described first embodiment. The sub-capacitances C11to C14and the sub-capacitances C21to C24are arranged in two columns, and the sub-capacitances C11to C14and the sub-capacitances C21to C24are so disposed as to meander (in a zigzag manner) in a planar view.

In the present embodiment, however, the sub-capacitances C11to C14and the sub-capacitances C21to C24are so arranged as to meander (in a zigzag manner) not only in the plane direction but also in a stacked-layer direction (in both the plane direction and the stacked-layer direction). The positions of the sub-capacitances C11to C14and the positions of the sub-capacitances C21to C24are inverted between adjacent two layers.

More specifically, each of the sub-capacitances C11to C14and C21to C24is divided into upper and lower sub-capacitances, and the divided upper and lower sub-capacitances are also coupled side by side with each other. In other words, the sub-capacitance C11includes sub-capacitances C11aand C11bthat are coupled side by side with each other. Likewise, the sub-capacitance C12includes sub-capacitances C12aand C12bthat are coupled side by side with each other, the sub-capacitance C13includes sub-capacitances C13aand C13bthat are coupled side by side with each other, and the sub-capacitance C14includes sub-capacitances C14aand C14bthat are coupled side by side with each other. Also, likewise, the sub-capacitance C21includes sub-capacitances C21aand C21bthat are coupled side by side with each other, the sub-capacitance C22includes sub-capacitances C22aand C22bthat are coupled side by side with each other, the sub-capacitance C23includes sub-capacitances C23aand C23bthat are coupled side by side with each other, and the sub-capacitance C24includes sub-capacitances C24aand C24bthat are coupled side by side with each other.

For example, each of the sub-capacitances C11ato C14amay include the electroconductive layers521aand522athat are disposed in the wiring layer M1and the electroconductive layers521band522bthat are disposed in the wiring layer M2. The electroconductive layer521adisposed in the wiring layer M1and the electroconductive layer521bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Likewise, the electroconductive layer522adisposed in the wiring layer M1and the electroconductive layer522bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Note that portions configuring the sub-capacitances C11ato C14aare surrounded by dashed lines in the wiring layers M1and M2ofFIG. 20.

Each of the sub-capacitances C11bto C14bincludes the electroconductive layers521cand522cthat are disposed in the wiring layer M3and the electroconductive layers521dand522dthat are disposed in the wiring layer M4. The electroconductive layer521cdisposed in the wiring layer M3and the electroconductive layer521ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Likewise, the electroconductive layer522cdisposed in the wiring layer M3and the electroconductive layer522ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Note that portions configuring the sub-capacitances C11bto C14bare surrounded by dashed lines in the wiring layers M3and M4ofFIG. 20.

In contrast, each of the sub-capacitances C21ato C24amay include the electroconductive layers523aand524athat are disposed in the wiring layer M1and the electroconductive layers523band524bthat are disposed in the wiring layer M2. The electroconductive layer523adisposed in the wiring layer M1and the electroconductive layer523bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Likewise, the electroconductive layer524adisposed in the wiring layer M1and the electroconductive layer524bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Note that portions configuring the sub-capacitances C21ato C24aare surrounded by alternate long and short dash lines in the wiring layers M1and M2ofFIG. 20.

Each of the sub-capacitances C21bto C24bincludes the electroconductive layers523cand524cthat are disposed in the wiring layer M3and the electroconductive layers523dand524dthat are disposed in the wiring layer M4. The electroconductive layer523cdisposed in the wiring layer M3and the electroconductive layer523ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Likewise, the electroconductive layer524cdisposed in the wiring layer M3and the electroconductive layer524ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Note that portions configuring the sub-capacitances C21bto C24bare surrounded by alternate long and short dash lines in the wiring layers M3and M4ofFIG. 20.

The wiring layer525(the first wiring layer) to couple the sub-capacitances C11to C14with one another is disposed in a layer different from a layer of the wiring layer526(the second wiring layer) to couple the sub-capacitances C21to C24with one another. In this case, the wiring layer525is disposed in the wiring layers M1and M3, and the wiring layer526is disposed in the wiring layers M2and M4.

In the wiring layer M1, the electroconductive layers521aand522aconfiguring the sub-capacitances C11ato C14aand the wiring layer525are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. In the wiring layer M3, the electroconductive layers521cand522cconfiguring the sub-capacitances C11bto C14band the wiring layer525are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. In the wiring layer M2, the electroconductive layers523band524bconfiguring the sub-capacitances C21ato C24aand the wiring layer526are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view. In the wiring layer M4, the electroconductive layers523dand524dconfiguring the sub-capacitances C21bto C24band the wiring layer526are integrally formed, and have a shape meandering in a rectangular wave shape in a planar view.

Such a configuration results in layout in which the positions of the respective sub-capacitances C11ato C14aand C21ato C24aand the positions of the respective sub-capacitances C11bto C14band C21bto C24bare inverted between the wiring layer M2and the wiring layer M3. Thus, portions of the respective electroconductive layers521b,522b,523b, and524band portions of the respective electroconductive layers521c,522c,523c, and524care extended for interlayer coupling of the wiring layers M2and M3.

A portion of the electroconductive layer521bconfiguring the sub-capacitance C11ais extended, and a via H11is provided in the extended portion. The electroconductive layer521band the electroconductive layer521care electrically coupled with each other through the via H11. A portion of the electroconductive layer522bconfiguring the sub-capacitance C14ais extended, and a via H13is provided in the extended portion. The electroconductive layer522band the electroconductive layer522care electrically coupled with each other through the via H13.

A portion of the electroconductive layer523bconfiguring the sub-capacitance C21ais extended, and a via H21is provided in the extended portion. The electroconductive layer523band the electroconductive layer523care electrically coupled with each other through the via H21. A portion of the electroconductive layer524bconfiguring the sub-capacitance C24ais extended, and a via H22is provided in the extended portion. The electroconductive layer524band the electroconductive layer524care electrically coupled with each other through the via H22.

In the wiring layers M3and M4, portions of the electroconductive layers521c,522c,523c, and524care extended as ends a1, a2, b1, and b2, respectively, illustrated inFIG. 19. More specifically, a portion of the electroconductive layer521cconfiguring the sub-capacitance C11bis extended, and a via H12is provided in the extended portion. The electroconductive layer521cis led out to the wiring layer M4through the via H12, thereby serving as the end a1. A portion of the electroconductive layer522cconfiguring the sub-capacitance C14bserves as the end a2. A portion of the electroconductive layer523cconfiguring the sub-capacitance C21bserves as the end b1. A portion of the electroconductive layer524cconfiguring the sub-capacitance C24bis extended, and a via H23is provided in the extended portion. The electroconductive layer524cis led out to the wiring layer M4through the via H23, thereby serving as the end b2.

As mentioned above, it is possible to arrange the sub-capacitances C11to C14and the sub-capacitances C21to C24in the layout meandering in a zigzag manner in both the plane direction and the stacked-layer direction while being coupled side by side with one another with use of the four wiring layers M1to M4. Also, causing the arrangement of the sub-capacitances to meander in the stacked-layer direction makes it possible to further reduce the facing area between the sampling capacitances C2and C3, thereby further reducing the crosstalk amount, as illustrated inFIG. 21AandFIG. 21b.

Third Embodiment

FIG. 22is a diagram illustrating an outline of layout of sampling capacitances according to a third embodiment of the disclosure.FIG. 23is a circuit diagram to explain ends for wiring coupling (extraction electrodes) of the sampling capacitances C1and C2.FIG. 24is a schematic plan view illustrating wiring layout of each of the wiring layer (M1) to the wiring layer (M4) of the sampling capacitances C1and C2according to a third configuration example.FIG. 25Ais a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line IF-IF inFIG. 22, andFIG. 25Bis a diagram illustrating a cross-sectional configuration as viewed in an arrow direction of line IG-IG inFIG. 22.

Note that,FIG. 22illustrates an outline of layout of sampling capacitances (C1and C2) that are disposed in an ADC(n) in a certain column of the plurality of ADCs50A and sampling capacitances (denoted by “C3” and “C4” for convenience) that are disposed in an ADC(n+1) adjacent to the ADC(n). As described in the foregoing first embodiment, the sampling capacitance C1corresponds to the combined capacitance of the sub-capacitances C11and C12, and the sampling capacitance C2corresponds to the combined capacitance of the sub-capacitances C21and C22. Likewise, the sampling capacitance C3corresponds to the combined capacitance of the sub-capacitances C31and C32, and the sampling capacitance C4corresponds to the combined capacitance of the sub-capacitances C41and C42.

Also,FIG. 24illustrates the wiring layout of only the sampling capacitances C1and C2; however, the sampling capacitances C3and C4are also disposed in the layout similar to that of the sampling capacitances C1and C2.

The sampling capacitances C1and C2according to the present embodiment are disposed at respective paired differential input ends of the comparator51that is similar to that of the above-described first embodiment, and are suitably used in the ADC50A or the AD conversion section50including the comparator51. Also in the present embodiment, as illustrated inFIG. 24,FIG. 25A, andFIG. 25B, the sub-capacitances C11, C12, C21, and C22are provided on an unillustrated semiconductor substrate with use of the four wiring layers M1to M4, as with the above-described first embodiment. Also, the sub-capacitances C11and C12and the sub-capacitances C21and C22are arranged in two columns, and the sub-capacitances C11and C12and the sub-capacitances C21and C22are so arranged as to meander (in a zigzag manner).

In the present embodiment, however, the sub-capacitances C11and C12and the sub-capacitances C21and C22are so arranged as to meander (in a zigzag manner) not in the plane direction but in the stacked-layer direction (only in the stacked-layer direction). The positions of the sub-capacitances C11and C12and the positions of the sub-capacitances C21and C22are inverted between adjacent two layers.

More specifically, each of the sub-capacitances C11, C12, C21, and C22is divided into upper and lower sub-capacitances, and the divided upper and lower sub-capacitances are coupled side by side with each other. In other words, the sub-capacitance C11includes sub-capacitances C11aand C11bthat are coupled side by side with each other. Likewise, the sub-capacitance C12includes sub-capacitances C12aand C12bthat are coupled side by side with each other, the sub-capacitance C21includes sub-capacitances C21aand C21bthat are coupled side by side with each other, and the sub-capacitance C22includes sub-capacitances C22aand C22bthat are coupled side by side with each other.

The sub-capacitances C11aC12a, C21a, and C22aare each disposed in the wiring layers M1and M2. The sub-capacitances C11b, C12b, C21b, and C22bare each disposed in the wiring layers M3and M4. In such a stacked-layer structure, the sub-capacitances C11aand C11bconfiguring the sub-capacitance C11are vertically disposed at shifted positions (are disposed at inverted positions in the plane direction). Likewise, the sub-capacitances C12aand C12b, the sub-capacitances C21aand C21b, and the sub-capacitances C22aand C22brespectively configuring the sub-capacitances C12, C21, and C22are vertically disposed at corresponding shifted positions.

For example, each of the sub-capacitances C11aand C12amay include the electroconductive layers521aand522athat are disposed in the wiring layer M1and the electroconductive layers521band522bthat are disposed in the wiring layer M2. The electroconductive layer521adisposed in the wiring layer M1and the electroconductive layer521bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Likewise, the electroconductive layer522adisposed in the wiring layer M1and the electroconductive layer522bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Note that portions configuring the sub-capacitances C11aand C12aare surrounded by dashed lines in the wiring layers M1and M2ofFIG. 24.

Each of the sub-capacitances C11band C12bincludes the electroconductive layers521cand522cthat are disposed in the wiring layer M3and the electroconductive layers521dand522dthat are disposed in the wiring layer M4. The electroconductive layer521cdisposed in the wiring layer M3and the electroconductive layer521ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Likewise, the electroconductive layer522cdisposed in the wiring layer M3and the electroconductive layer522ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Note that portions configuring the sub-capacitances C11band C12bare surrounded by dashed lines in the wiring layers M3and M4ofFIG. 24.

In contrast, each of the sub-capacitances C21aand C22aincludes the electroconductive layers523aand524athat are disposed in the wiring layer M1and the electroconductive layers523band524bthat are disposed in the wiring layer M2. The electroconductive layer523adisposed in the wiring layer M1and the electroconductive layer523bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Likewise, the electroconductive layer524adisposed in the wiring layer M1and the electroconductive layer524bdisposed in the wiring layer M2right above the wiring layer M1face each other, and are coupled with each other through the via Ha through interlayer coupling. Note that portions configuring the sub-capacitances C21aand C22aare surrounded by alternate long and short dash lines in the wiring layers M1and M2ofFIG. 24.

Each of the sub-capacitances C21band C22bincludes the electroconductive layers523cand524cthat are disposed in the wiring layer M3and the electroconductive layers523dand524dthat are disposed in the wiring layer M4. The electroconductive layer523cdisposed in the wiring layer M3and the electroconductive layer523ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. The electroconductive layer524cdisposed in the wiring layer M3and the electroconductive layer524ddisposed in the wiring layer M4right above the wiring layer M3face each other, and are coupled with each other through the via Hc through interlayer coupling. Note that portions configuring the sub-capacitances C21band C22bare surrounded by alternate long and short dash lines in the wiring layers M3and M4ofFIG. 24.

Such a configuration results in layout in which the positions of the respective sub-capacitances C11a, C12a, C21a, and C22aand the positions of the respective sub-capacitances C11b, C12b, C21b, and C22bare inverted between the wiring layer M2and the wiring layer M3. Thus, portions of the respective electroconductive layers521b,522b,523b, and524band portions of the respective electroconductive layers521c,522c,523c, and524care extended for interlayer coupling of the wiring layers M2and M3.

A portion of the electroconductive layer522bconfiguring the sub-capacitance C11ais extended, and a via H14is provided in the extended portion. The electroconductive layer522band the electroconductive layer522care electrically coupled with each other through the via H14. Portions of the electroconductive layer522bconfiguring the sub-capacitance C12aare extended, and vias H15and H16are provided in the extended portions. The electroconductive layer522band the electroconductive layer522care electrically coupled with each other through the vias H15and H16.

Portions of the electroconductive layer524bconfiguring the sub-capacitance C21aare extended, and vias H24and H25are provided in the extended portions. The electroconductive layer524band the electroconductive layer524care electrically coupled with each other through the vias H24and H25. A portion of the electroconductive layer524bconfiguring the sub-capacitance C22ais extended, and a via H26is provided in the extended portion. The electroconductive layer524band the electroconductive layer524care electrically coupled with each other through the via H26.

In the wiring layers M2and M3, portions of the electroconductive layers522b,524b,522c, and524care extended as the ends a1, a2, b1, and b2, respectively, illustrated inFIG. 23. More specifically, a portion of the electroconductive layer522bconfiguring the sub-capacitance C11ais extended, and the extended portion serves as the end a1. A portion of the electroconductive layer522cconfiguring the sub-capacitance C12bis extended, and the extended portion serves as the end a2. A portion of the electroconductive layer524cconfiguring the sub-capacitance C21bis extended, and the extended portion serves as the end b1. A portion of the electroconductive layer524bconfiguring the sub-capacitance C22ais extended, and the extended portion serves as the end b2.

As mentioned above, it is possible to arrange the sub-capacitances C11to C14and the sub-capacitances C21to C24in the layout meandering in a zigzag manner in both the plane direction and the stacked-layer direction while being coupled side by side with one another with use of the four wiring layers M1to M4. Also, causing the arrangement of the sub-capacitances to meander in the stacked-layer direction makes it possible to reduce the facing area between the sampling capacitances C2and C3, thereby reducing the crosstalk amount, as illustrated inFIG. 25AandFIG. 25B.

Fourth Embodiment

FIG. 26is a diagram illustrating an outline of layout of sampling capacitances according to a fourth embodiment of the disclosure.FIG. 27is a diagram schematically illustrating a cross-sectional configuration as viewed in an arrow direction of line inFIG. 26.FIG. 28is a schematic plan view illustrating wiring layout of each of the wiring layer (M1) to the wiring layer (M4) of the sampling capacitances C1and C2according to a fourth configuration example.

An electrostatic shielding layer (an electrostatic shielding layer530) may be further disposed between the adjacent ADCs50A, in addition to the layout of the sampling capacitances C1and C2described in the foregoing first to third embodiments. The electrostatic shielding layers530are provided to sandwich the sampling capacitances C1and C2, along the extending direction of the arrangement of the sampling capacitances C1and C2. Each of the electrostatic shielding layers530may be formed with use of the wiring layers M1to M4, as with the sampling capacitances C1and C2.

For example, as illustrated inFIG. 27andFIG. 28, electrostatic shielding layers530ato530dare respectively provided in the wiring layers M1to M4, and the electrostatic shielding layers530ato530dare coupled with one another through vias H3through interlayer coupling. Note that,FIG. 28illustrates the layout of the sampling capacitances C1and C2according to the above-described first configuration example as an example. The electrostatic shielding layer530may desirably have a fixed potential. For example, as illustrated inFIG. 29, the electrostatic shielding layers530ato530dmay be desirably provided on a semiconductor substrate540with a contact portion531in between. A shallow trench isolation (STI) layer540ais provided on a surface of the semiconductor substrate540, and a p-type diffusion layer540bis provided in an opening of the STI layer540a. Electrically coupling the p-type diffusion layer540bwith the electrostatic shielding layer530athrough the contact portion531makes it possible to fix the potential of the electrostatic shielding layer530to the potential same as the substrate potential. The electrostatic shielding layers530ato530dare electrically coupled with one another through the H3.

A plurality of the vias H3may be arranged, for example, along the extending direction of the electrostatic shielding layers530ato530cin each of the wiring layers M1to M3. The shielding effect is more enhanced as a distance between the vias H3is smaller.FIG. 30AtoFIG. 30Ceach illustrate an example of the layout of the vias H3. The plurality of vias H3may be arranged in line along the extending direction of the electrostatic shielding layers530ato530cas illustrated inFIG. 30A, or the plurality of the vias H3may be arranged alternately in a plurality of lines (two lines in this case) (so as to fill the gap between the vias H3) as illustrated inFIG. 30B. Also, as illustrated inFIG. 30C, the via H3may have a rectangular shape (having a long side along the extending direction) elongated along the extending direction of the electrostatic shielding layers530ato530d.

As with the present embodiment, the electrostatic shielding layers530may be disposed to sandwich the sampling capacitances C1and C2. This makes it possible to suppress occurrence of the parasitic capacitance between the adjacent ADCs50A. Thus, it is possible to exert effects equivalent to those of the first embodiment.

Modification Example of Fourth Embodiment

FIG. 31is a diagram illustrating a configuration of the electrostatic shielding layer530according to a modification example of the above-descried fourth embodiment. Although die configuration is described, in which the electrostatic shielding layers530are so disposed between the ADCs50A as to sandwich the sampling capacitances C1and C2in the foregoing fourth embodiment, the electrostatic shielding layer530may be so provided as to cover the sampling capacitances C1and C2.

For example, the electrostatic shielding layers530ato530dmay be stacked on the semiconductor substrate540with use of the wiring layers M1to M4, and an electrostatic shielding layer530emay be further formed with use of a wiring layer M5provided thereon. This shields, in addition to the side walls, upper side of the sampling capacitances C1and C2, thereby further enhancing the effect of suppressing the parasitic capacitance.

Further, in a case where the electrostatic shielding layer is disposed also on the sampling capacitances C1and C2, when wiring density is restricted by the design rule in the wiring layer M5, a wiring layer M6that is an upper layer of the wiring layer M5may be used as illustrated inFIG. 32. This allows for a configuration in which the wiring layer M5is opened and the opening is shielded by an electrostatic shielding layer530fof the wiring layer M6.

Other modification examples of the sampling capacitances described in the foregoing first to fourth embodiments are described below.

Modification Example 1

FIG. 33is a diagram illustrating an example of a circuit configuration of the sampling capacitances C1and C2according to a modification example 1. As illustrated, the sampling capacitances C1and C2respectively include the plurality of sub-capacitances C11to C14and the plurality of sub-capacitances C21to C24. The sub-capacitances C11to C14are coupled side by side with one another, and the sub-capacitances C21to C24are coupled side by side with one another.

Modification Example 2-1

The above-described embodiments, for example, describes the case in which the sampling capacitances C1and C2are formed with use of two or more wiring layers that are provided on the semiconductor substrate. Alternatively, each of the sampling capacitances C1and C2may be, for example, a metal-oxide-semiconductor (MOS) capacitor using each layer of an MOSFET as illustrated inFIG. 34. In the MOSFET, for example, an n-type P—Si gate electrode124may be provided on a p-type substrate120, which includes an STI layer121and an n-type diffusion layer122provided on the surface thereof, with a gate insulation film123in between. An interlayer insulation film127is provided to cover the n-type P—Si gate electrode124, and a lower electrode126is disposed on the interlayer insulation film127. A contact layer125is provided in the interlayer insulation film127, and the lower electrode126is electrically coupled with the n-type diffusion layer122through the contact layer125. In such a configuration, it is possible to configure a capacitor with use of the electroconductive layers such as the lower electrode126.

Also, each of the sampling capacitances C1and C2may be, for example, a metal-insulator-metal (MIM) capacitor as illustrated inFIG. 35. For example, an STI layer131, an interlayer insulation film132, a lower electrode133, a dielectric film134, and a wiring layer135may be provided in this order on a p-type substrate130. An upper electrode137is disposed on the wiring layer135with a contact portion136in between. In such a configuration, a capacitor may be formed with use of the electroconductive layers such as the lower electrode133, the wiring layer135, and the upper electrode137.

The solid-state imaging apparatus1described, for example, in the foregoing embodiments is applicable to various image input apparatuses. Also, the analog-to-digital converter according to the disclosure is applicable to a drive circuit of various electronic apparatuses that do not use the solid-state imaging apparatus. Examples thereof are described below.

Application Example 1

FIG. 36is a block diagram illustrating a configuration of a digital camera (a digital still camera, or a digital video camera)300A. The digital camera300A includes a pixel sensor section301in which pixels are two-dimensionally arranged, an ADC group302, and a signal processing circuit303. The ADC50A including the sampling capacitances C1and C2according to any of the above-described embodiments is disposed in the ADC group302. Also, when the pixels are arranged two-dimensionally, the ADC50A is applicable to an XY scanner, in addition to the digital camera.

Application Example 2

FIG. 37is a block diagram illustrating a configuration of a barcode reader300B. The barcode reader300B includes a pixel sensor section305in which pixels are one-dimensionally arranged, an ADC group306, a signal processing circuit307, and an illumination LED308that applies light to a barcode304. The ADC50A including the sampling capacitances C1and C2according to any of the above-described embodiments is disposed in the ADC group306.

Application Example 3

FIG. 38is a block diagram illustrating a configuration of a display apparatus300C. The display apparatus300C may be, for example, a plasma display, and includes ADC groups309provided for each image signal of R, G, and B, a detection circuit310, a signal processing circuit311, a drive circuit312, a display panel313, a control pulse power supply314, and a drive power supply315. The ADC50A including the sampling capacitances C1and C2according to any of the above-described embodiments is disposed in the ADC group309. Note that the ADC50A is applicable to other displays such as an CRT display, a liquid crystal display, and an organic EL display, without limitation to the plasma display.

Application Example 4

FIG. 39is a block diagram illustrating a configuration of a projector300D. The projector300D includes a CPU316performing processing of image data, an image signal processing circuit317including an ADC, and a projection unit318. The ADC50A including the sampling capacitances C1and C2according to any of the above-described embodiments is disposed in the image signal processing circuit317.

Application Example 5

FIG. 40is a block diagram illustrating a configuration of a measurement instrument300E. The measurement instrument300E includes a comparator group319that receives an analog signal and a reference signal, and an encoder320. The sampling capacitances C1and C2according to any of the above-described embodiments are disposed at respective differential input ends of the comparator group319. In this way, the disclosure is applicable also to a typical comparator of a parallel ADC. Examples of the electronic apparatus having such a configuration may include an audio apparatus, in addition to the measurement instrument.

Application Example 6

FIG. 41is a block diagram illustrating a configuration of an X-ray detector300G. The X-ray detector300G includes an optical sensor321, an amplifier322, an ADC323, a signal processor324, and a display unit325. The ADC50A including the sampling capacitances C1and C2according to any of the above-described embodiments is disposed in the ADC323.

Although some embodiments, modification examples, and application examples have been described above, the contents of the disclosure are not limited thereto, and various modification may be made. For example, although the configuration in which the sampling capacitances C1and C2are each divided into four sub-capacitances and the four sub-capacitances are coupled side by side with one another has been exemplified, for example, in the above-described embodiments, the number of sub-capacitances (a division number) is not limited to four, and may be two, three, or five or more.

Also, the case in which the sampling capacitances C1and C2are coupled with the comparator of the analog-to-digital converter has been described as an example in the above-described embodiments, for example. The above-described sampling capacitances C1and C2, however, are applicable to a differential circuit other than the analog-to-digital converter.FIG. 42andFIG. 43each illustrate an example of a differential circuit. The examples relate to an amplification circuit using a differential amplifier (an operational amplifier), and one differential amplifier is configured of a plurality of differential amplifiers that are coupled side by side with one another. Such a configuration makes it possible to increase a maximum output current value of the differential amplifier and to reduce noise of the differential amplifier.

In the example ofFIG. 42, four AC amplifiers are coupled side by side with one another. The AC amplifiers each include resistors550A to550C, capacitors C1ato C1d(the sampling capacitance C1), an unillustrated MOSFET (a field effect transistor), and a differential amplifiers (operational amplifiers551). In this configuration, a parasitic capacitance caused by coupling between the capacitors C1band C1cbecomes large in the capacitors C1ato C1dthat are each coupled with an input terminal of corresponding operational amplifier551, which deteriorates frequency characteristics of a gain of the AC amplifiers.

In the example ofFIG. 43, four AC amplifiers are coupled side by side with one another. The AC amplifiers each include the resistors550A to5500, the capacitors C1ato C1d(the sampling capacitance C1), capacitors C2ato C2d(the sampling capacitance C2), an unillustrated MOSFET (a field effect transistor), and the operational amplifiers551. In this configuration, the parasitic capacitances caused by coupling between the capacitors C2aand C1band coupling between the capacitors C2cand C1dbecome large, which deteriorates frequency characteristics of a gain of the AC amplifiers.

Even in the above-described examples, however, the capacitors C1ato C1dand C2ato C2dare designed with layout similar to that of the above-described sampling capacitances C1and C2, which makes it possible to suppress deterioration of the frequency characteristics of the gain and to achieve both increase in the output current value and noise reduction.

Note that the effects described, for example, in the foregoing embodiments are illustrative and non-limiting. Effects achieved by the technology may be effects other than those described above or may further include other effects.

It is to be noted that the disclosure may have the following configurations.

a comparator having paired differential input ends; and

a first capacitor and a second capacitor each provided at respective differential input ends, wherein

the first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another,

the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another, and

the plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

The analog-to-digital converter according to (1), wherein the plurality of first sub-capacitors and the plurality of second sub-capacitors are alternately arranged in two columns.

The analog-to-digital converter according to (1) or (2), wherein the plurality of first sub-capacitors have layout that is mirror-inverted to layout of the plurality of second sub-capacitors.

The analog-to-digital converter according to any one of (1) to (3), wherein each of the first sub-capacitors and the second sub-capacitors includes first and second electroconductive layers that are each provided in two or more layers and are coupled with each other through interlayer coupling, and are disposed to face each other.

The analog-to-digital converter according to (4), wherein a first wiring layer that couples the first sub-capacitors with one another and a second wiring layer that couples the second sub-capacitors with one another are disposed in selective layers that are different from each other.

The analog-to-digital converter according to (5), wherein

the first and second electroconductive layers that configure each of the first sub-capacitors and the first wiring layer are integrally formed and have a shape meandering in a rectangular wave shape in a planar view, in a layer including the first wiring layer, and

the first and second electroconductive layers that configure each of the second sub-capacitors and the second wiring layer are integrally formed and have a shape meandering in a rectangular wave shape in a planar view, in a layer including the second wiring layer.

The analog-to-digital converter according to any one of (2) to (6), wherein the plurality of first sub-capacitors and the plurality of second sub-capacitors are each arranged in a zigzag manner in a planar view.

The analog-to-digital converter according to any one of (2) to (6), wherein the plurality of first sub-capacitors and the plurality of second sub-capacitors are each arranged in a zigzag manner in a stacked-layer direction.

The analog-to-digital converter according to (8), wherein

each of the first sub-capacitors and the second sub-capacitors includes first and second electroconductive layers that are each provided in two or more layers and are coupled with each other through interlayer coupling, and are disposed to face each other,

positions of the first sub-capacitors and positions of the second sub-capacitors are inverted between adjacent two layers, and

one of the first and second electroconductive layers is extended, and a through hole for the interlayer coupling is provided in the extended portion.

The analog-to-digital converter according to (9), wherein

the plurality of first sub-capacitors are integrally formed and have a shape meandering in a rectangular wave shape in a planar view, and a portion of the meandering shape is extended to have the through hole, in a first layer of the adjacent two layers, and

the plurality of second sub-capacitors are integrally formed and have a shape meandering in a rectangular wave shape in a planar view, and a portion of the meandering shape is extended to have the through hole, in a second layer of the adjacent two layers.

The analog-to-digital converter according to (9), wherein, in the adjacent two layers,

a portion of one of the first and second electroconductive layers of each of the first sub-capacitors is extended, and the extended portion has the through hole, and

a portion of one of the first and second electroconductive layers of each of the second sub-capacitors is extended, and the extended portion has the through hole.

The analog-to-digital converter according to any one of (1) to (11), further including electrostatic shielding layers that are provided to sandwich the first sub-capacitors and the second sub-capacitors.

The analog-to-digital converter according to (12), wherein each of the electrostatic shielding layers extends along arrangement of the plurality of first sub-capacitors and the plurality of second sub-capacitors, and is provided in two or more layers through interlayer coupling via a through hole.

The analog-to-digital converter according to (13), wherein the through hole includes a plurality of through holes arranged along an extending direction of the electrostatic shielding layers.

The analog-to-digital converter according to (14), wherein the through holes are arranged alternately in two lines along the extending direction.

The analog-to-digital converter according to (13), wherein the through hole is provided in a rectangular region that has a long side along the extending direction.

The analog-to-digital converter according to any one of (12) to (16), wherein one of the electrostatic shielding layer is provided to further cover the plurality of first sub-capacitors and the plurality of second sub-capacitors.

The analog-to-digital converter according to any one of (1) to (17), wherein each of the first capacitor and the second capacitor is a metal-oxide-semiconductor capacitor or a metal-insulator-metal capacitor.

A solid-state imaging apparatus provided with an analog-to-digital converter, the analog-to-digital converter including:

a comparator having paired differential input ends; and

a first capacitor and a second capacitor each provided at respective differential input ends, wherein

the first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another,

the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another, and

the plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

An electronic apparatus provided with an analog-to-digital converter, the analog-to-digital converter including:

a comparator having paired differential input ends; and

a first capacitor and a second capacitor each provided at respective differential input ends, wherein

the first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another,

the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another, and

the plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.

This application is based upon and claims the benefit of priority of the Japanese Patent Application No. 2015-042633 filed in the Japan Patent Office on Mar. 4, 2015, the entire contents of which are incorporated herein by reference.