Supporting hang detection and data recovery in microprocessor systems

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to hardware processors, and more specifically, but without limitation, to supporting hang detection and data recovery in microprocessor systems.

BACKGROUND

A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, a register architecture, addressing modes, memory architecture, interrupt/exception handling, and instructions for controlling input and output (I/O) of the processor.

DETAILED DESCRIPTION

Increasing demands for processing greater volumes of data at faster speeds continues to drive developments in the area of computer processors. In some situations, sporadic system failures can occur during certain high volume testing by a system Original Equipment Manufacturer (OEM) before a product launch. Issues in various hardware components (e.g., processors, bus controllers, drivers), software components (e.g., operating systems, applications), or any combination thereof can sometimes cause these types of system failures. Because of the complexity of the hardware and software used, many systems experience various types of errors, including complete hangs.

A hang is an unexpected unresponsive state of a system or process, such as when a processor or central processing unit (CPU) becomes unresponsive due to a processor stalling, locking up or crashing in response to some type of error. Currently, such hangs can cause data loss, as well as halting operations on the entire computer system. Due to the constant introduction of new hardware and software to the system and the large number of possible combinations there between, it may be difficult to identify and eliminate the possible cause of such errors.

Some methods used to detect the cause of the hangs have relied on out-of-band (OOB) data signals that transfer data through a stream independent from a main in-band data stream of the system, such as using a certain interface and network to read all the state information. These methods would analyze the hang source based on a snapshot of content collected via the OOB stream. This type of analysis using the OOB stream can become very complicated in which many resources are often wasted when each system manufacturer desires a new OOB data flow that is specifically created for their particular system configuration. In some situations, using an OOB path is better than using an in-band path to collect data since the in-band path has a high likelihood of getting stuck during a hang.

Another method used to detect the cause of a hang is to use a type of hardware probe (e.g., Direct Connect Interface (DCI)) that allows for the debugging of hardware components by using an external physical I/O port. Some systems, however, may include thousands of machines making it physically challenging to connect a DCI to each one. In such cases, the data at many hang points may be lost and the system or component manufacturer may not become aware of certain problems with a particular system configuration until it permeates a large number of their systems. Thus, causing the OEMs further wasted efforts and frustrations to identify the faulty component.

Embodiments of the disclosure address the above-mentioned and other deficiencies by providing techniques to detect certain hang events and gather crashlogs relevant to the event. In this regard, the crash logs are gathered in a manner in which they can survive even a global reset by the system. The crash logs comprise data retrieved from a determined list of registers associated with various system components, such as a processing core, other elements outside the processing cores (also referred to as an uncore) which may encompass system agents, memory, graphics controller, display controller, memory controller, etc., and a controller hub which controls certain data paths and support functions used in conjunction with the CPU, as well as data from other types of registers. This crash data may be the lowest granularity of data to be collected when a crash is detected. This is typically in the form of a single register or a single trace message. The techniques of the disclosure may be implemented as processing logic in a crashlog unit (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.) to provide the benefits described herein. The crashlog unit, in one embodiment, includes instructions to implement techniques for detecting various types of hangs and collect data from the determined list of registers associated with the core, uncore and controller hub components. In this way, there is a hang detector and a data collection flow for each component that may work independently, but also work in tandem with each other to form one integrated collection flow of crash data. This allows portions of the crash data collection to continue to work in case a hang occurs during any part of the collection flow.

Once the first hang detector logic detects a hang with a particular core, the crashlog unit is activated to produce a first log by reading contents of a pre-determined set of core registers. The crashlog unit exposes the contents of the log by saving the logs in a memory region outside of the core. The core then alerts a second hang detector logic associated with the uncore component (e.g., other processor elements outside the processing cores) that the core experienced a hang. This activates the crashlog unit to produce a second log based on contents of registers within the uncore component. For example, the contents of the uncore registers may be retrieved by using a state machine that saves the entire state of the system including, but not limited to, the state of the CPU registers, the power management status, the CPU cache, the system memory, the system cache, the video registers, the video memory, and the other device registers. Once the call is complete, the logs are then copied to a shared memory, such as static random access memory (SRAM) of a power management controller (PMC), associated with the controller hub. A hang detector associated with the controller hub is then alerted that the CPU experienced a hang. This activates the crashlog unit to produce a third log containing data from registers of the controller hub and store the third log in the shared SRAM.

The crash logs are stored together in the shared SRAM of the PMC associated with the controller hub to persist the data even in the case of a reset. For example, the crash logs may survive the reset because they are stored in controller hub, which has voltage rails that are kept powered in most reset situations. For example, the voltage rail coupled to the controller hub is the primary voltage rail on the platform, which is directly from the battery or power supply on the platform. In some embodiments, after a reset to recover from the hang, a basic input output system (BIOS) associated with the CPU may be configured to check for the existence of the crash logs. If the logs are present, the BIOS may copy the logs into a data structure that can later be stored onto a file in a hard drive. Hence, in the event of a hang, this additional persistence of the crash logs allows certain smart post-processing tools (e.g., Intel System Studio™) to analyze the content and provide further guidance as to the source of the hang, and how to proceed with debugging procedures including possible corrective measures. One advantage of the techniques disclosed herein is that they utilize existing in-band data paths to work in conjunction with the crashlog unit to reduce cost and increase the compatibility of the implementations with various system manufacture specifications.

In alternative embodiments, the techniques of the disclosure can also implement support to trigger the production and extraction of the crash logs via an enhanced serial peripheral interface (eSPI) Out of Band (OOB) messaging. For example, an embedded controller (EC) agent may be connected to the controller hub via the eSPI. The EC may use this eSPI connection to detect a platform error and obtain crash records via the OOB path. For example, when a certain command is read from the eSPI message buffer, the PMC checks if a crash log has already been collected in the shared SRAM of the controller hub. If a crash log is not detected, the PMC triggers the crashlog unit to perform a crash log collection. Thereupon, the crashlog unit writes the contents of the crash log to the eSPI write data buffer for passage to EC agent, such as flash storage. An advantage of the capability using the EC is that it allows for the crash log information to be collected before the platform initiates a global reset or is shutdown as a result of a crash, which would normally result in loss of the crash log

FIGS. 1A-1Cillustrates a block diagram of a system101according to various embodiments. In one embodiment, the system101includes a processing device100and a memory (not shown). The memory for one such system is a dynamic random access memory (DRAM) memory. The DRAM memory can be located on the same chip as the processing device100and other system components. Additionally, other logic blocks such as a memory controller120, graphics controller (not shown) or other types of controllers can also be located on the chip.

As shown inFIG. 1A, system101includes a processing device100to support hang detection and data recovery in microprocessor systems according to one embodiment. The processing device100may be generally referred to as “processor” or “CPU”. “Processor” or “CPU” herein shall refer to a device that is capable of executing instructions113encoding arithmetic, logical, or I/O operations. In one illustrative example, a processor may include an arithmetic logic unit (ALU), a control unit, and a plurality of registers. In a further aspect, a processor may include one or more processing cores, and hence may be a single core processor which is typically capable of processing a single instruction pipeline, or a multi-core processor which may simultaneously process multiple instruction pipelines. In another aspect, a processor may be implemented as a single integrated circuit, two or more integrated circuits, or may be a component of a multi-chip module (e.g., in which individual microprocessor dies are included in a single integrated circuit package and hence share a single socket).

As shown inFIG. 1, processing device100may include multiple domains112and114which may include a core domain comprising one or more processors cores110-1,110-2, and an uncore domain135which may include other circuitry of the processing device100such as cache memories, a memory controller120, other fixed function units, logic circuitry and so forth, coupled to each other as shown. The processing device100may also include a communication component (not shown), such as a bus, that may be used for point-to-point communication between various components of the processing device100. The processing device100may be used in a computing system (not shown) that includes, but is not limited to, a desktop computer, a tablet computer, a laptop computer, a netbook, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device.

In an illustrative example, processing core110-1may have a micro-architecture including processor logic and circuits. Processor cores with different micro-architectures may share at least a portion of a common instruction set. For example, similar register architectures may be implemented in different ways in different micro-architectures using various techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a register alias table (RAT), a reorder buffer (ROB) and a retirement register file). The processor core110-1may execute instructions113for the processing device100. The instructions may include, but are not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like.

Memory controller (MC)120may perform functions that enable the processing device100to access and communicate with memory (not shown) that includes a volatile memory and/or a non-volatile memory. In some embodiments, the memory controller120is located on a processor die associated with processing device100, while the memory is located off the processor die. In some embodiments, processing device100includes a cache memory (not shown) to cache data from and to memory via memory controller120. The cache includes, but is not limited to, a level one, level two, and a last level cache (LLC), or any other configuration of the cache memory within the processing device100. In some embodiments, the L1 cache and L2 cache can transfer data to and from the LLC. In some embodiments, the cache memory can be integrated into the processing cores110-1through N. The cache memory may store data including instructions that are utilized by one or more components of the processing device100.

System101further includes a power control unit (PCU)130, which includes various circuitry, logic to perform power management operations for the processing device100. In some embodiments, PCU130may be physically part of uncore domain114. The uncore domain refers to other elements of the processing device100that are outside the processing cores. These other elements may include, but not limited to, system agents, memory, graphics controller, display controller, memory controller, etc.

The PCU130may receive power status information (which can be received in an encoded form) from controller hub150and based on this information may regulate power consumption by components of processing device101. The processing device100may be coupled to the controller hub150via one or more communication bus(es)117. The controller hub device150is configured to relieve the processing device100from performing certain functions of system100, such as providing peripheral device support. In some embodiments, the controller hub may include interface and control circuitry to provide an interface between the processing device100and a variety of peripheral devices, such as input/output (TO) devices (not shown), e.g., user input devices (e.g., keyboard, touchpad, mouse or other pointing device, or so forth) and storage devices such as a mass storage, portable or other such storage, among many other peripheral devices.

The processing device100may be used with a computing system (e.g., system101) on a single integrated circuit (IC) chip. The instructions113may include, but are not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. The computing system may be representative of processing systems based on the Pentium® family of processors and/or microprocessors available from Intel® Corporation of Santa Clara, Calif., although other systems (including computing devices having other microprocessors, engineering workstations, set-top boxes and the like) may also be used. In one embodiment, a sample computing system may execute a version of an operating system, a virtual machine monitor (VMM), a hypervisor, application programs, embedded software, and/or graphical user interfaces. Thus, embodiments of the disclosure are not limited to any specific combination of hardware circuitry and software.

System101, in embodiments, may experience (in certain situations) various types of errors, including complete hangs due to the complexity of the hardware circuitry and software used therein. Embodiments of the disclosure providing techniques to detect certain condition in which the system hangs and gather crash logs based on these hangs. These crash logs can then be analyzed to provide further guidance as to the source of the hang, and how to proceed with debugging procedures including possible corrective measures. In some embodiments, system101includes processing logic in a crashlog unit140(e.g., circuitry, dedicated logic, programmable logic, microcode, etc.) to provide the benefits described herein. The crashlog unit140, in one embodiment, includes instructions to implement techniques for detecting various types of hangs and collect data from registers115,125and155that are respectively in the core region112, uncore region114and controller hub150region. In this way, there is hang detection logic and a data collection flow for each region that may work independently of each other, but also together to form one integrated collection flow of crash data. This allows portions of the crash data collection to continue to work in case a hang occurs during any part of the collection flow.

In some embodiments, the processing device100may detect an error associated with the core region112of processing device100to initiate the collection of crash log data145in accordance with embodiments of the disclosure. The processing device100may implement a reporting architecture that uses hardware-level code (e.g., power control code (pCode) and microcode (uCode)) for certain macroinstructions. The crashlog unit140utilizes this reporting architecture to detect certain errors associated with at least one core of the core region112of the processing device100. For example, if the amount of time to retire an operation of a pending instruction113executed by a particular core110-1exceeds a determined timeout threshold143(e.g., 2-6 seconds), this indicates that the core may be experiencing a hang.

When the core issues an error core due to the hang, the processing device100initiates a collection of crash log data145. In some embodiments, the uCode of processing device100causes the crashlog unit140to collect and store the content of data registers115that are relevant for debugging. For example, the data registers115may include, but not limited to, registers of a machine check architecture (MCA) whose values provide detailed information about errors occurring in the system that may include core/thread identifiers, error codes, last branch record (LBR), last event record (LER), super queue state that contains the last attempted transaction, architecture state information as well as other type of relevant information.

Once the hang is detected, the uCode instructs the crashlog unit140to collect content of data registers115. In some embodiments, a mailbox142(e.g., a dedicated region of shared memory) is used to transfer the collected data to a shared memory152(e.g., SRAM) of the controller hub150. For example, each of the cores110-1through N may be associated with a mailbox142, which is a dedicated region of shared memory, such as lower level cache (LLC) shared by the processor cores. The crashlog unit140inserts a header record into the mailbox142that includes a total number of bytes to be stored and format information of the crashlog data145. The crashlog data145is written to the mailbox142in a certain quantity (64-bits) at a time.

A busy flag141is set to a value (e.g., 0 or 1) by the crashlog unit140to indicate that the crashlog data145is being written to the mailbox142. For example, when the flag is set to 1, this is used to communicate from ucode to pcode that crashlog data145is ready for the pcode to consume. When the flag is set to 0, this is used to communicate from pcode to ucode that the crashlog data145has been consumed so that ucode can populate the next data in the mailbox142and set the flag again. Once the contents of the data registers115is completely written to mailbox142, the crashlog unit140copies the data of the mailbox142to the shared memory152of the controller hub150and clears the busy flag.

When the hang occurs, the processing device100may transmit a signal, such as an internal error signal (IERR), which indicates an unrecoverable error. The core (e.g., core110-1) that experienced the hang generates this IERR signal, which may also be propagated to other cores of the processing device100. For example, the core generates an OOB signal that can still go through even if the primary or in band bus is hung. In some embodiments, the IERR signal is used to identify the core of interest to gather relevant crash log data. For example, upon detection of a hang, a broadcast message is sent to all of the cores110-1, and the uCode in each thread of the cores through N simultaneously starts collecting crash log data. The crashlog unit140, however, will access the mailbox142of the first core that signaled the IERR.

A collection flow for crash data of the uncore region114of processing device100may begin when a core signals an IERR. In some embodiments, the collection flow may also be independently initiated. For example, the collection flow can be manually trigger or a catastrophic error (CATERR) signal or other type of error codes generated by system100. For example, the manual trigger is performed by writing a command to the BIOS pcode mailbox, which can be accessed via memory mapped I/O write or MSR write. When the collection flow is triggered, the contents of the uncore registers125may be retrieved by using a save/restore (S/R) state machine to save the entire state of the system including, but not limited to, the state of the CPU registers, the power management status, the CPU cache, the system memory, the system cache, the video registers, the video memory, and the other device registers. The S/R machines read the registers125in the uncore region114which are then stored in memory (e.g., SR SRAM) of the processing device100. The crashlog unit140then flushes the SR SRAM entries containing contents of the registers125into shared SRAM152of the controller hub150via a connection bridge (e.g., an On-Chip System Fabric Side Band (IOSF-SB)).

A collection flow for crash data of the controller hub150starts after the uncore's flow is complete. In some embodiments, the collection flow may also be independently initiated. For example, a hang in the controller hub150can be detected independently based on the expiration of a timer, such as a connection timeout or internal timers, or based on a reset or shutdown cycle from the processing device100. For example, the PMC153may trigger the crashlog unit140, if it encounters an error or reset that is caused by a timeout of an internal timer or a shutdown special cycle from the CPU. In some embodiments, a power management controller (PMC)153of the controller hub150may detect the hang call the crashlog unit140to store the controller hub crashlog data145into a location inside the shared SRAM152. The PMC153, in embodiments, may implement firmware that includes programmable logic to call the crashlog unit140. The controller hub crashlog data145will store in all controller hub data registers155, including PMC, PCIE controllers, USB, OPI/DMI, and P2SB (Primary to Sideband Bridge) registers into the shared SRAM153. Thereupon, a post-processing software tool (e.g. Intel® System Debugger) may be used to analyze the contents of the crashlog data145to guide the users in debug triage.

Turning toFIG. 1B, system101further includes a basic input output system (BIOS)160associated with the processing device100. The BIOS160is used to perform hardware initialization to get system101started during a booting process. When system101is rebooted either through an automatic reset from the detected error (hang) or by manual reset, the BIOS160checks for the existence of the crashlog data145. In one embodiment, before a shutdown of system101leading to a reset, the crashlog unit140may write the crash log data145for the core region112, uncore region114and controller hub150. The presence of the crashlog data145is an indication that a hang occurred prior to the reset. On the next BIOS boot after the hang, if the crashlog data145is present, the BIOS160copies the log into a data structure (e.g., advanced configuration power interface (ACPI) table) in the main memory. This data structure can later be stored onto a file in the hard drive or some non-volatile storage by, for example, a host application. Once the crash log data is on the hard drive or any non-volatile storage, it is safe and secured. Thereupon, post processing software (e.g., Intel® System Debugger) can be used to analyze the data and provide triage results.

With regards toFIG. 1C, system101further includes an embedded controller (EC) trigger the production and extraction of the crash logs data145in the event of a global reset by system101. For example, the EC of some original equipment manufacturers (OEMs) can issue a global reset to system101after receiving a CATERR signal from processing device100. The signal may be sent to the controller hub150a connection185to the EC150. For example, the controller hub150of system101may be connected to the EC180via an enhanced serial peripheral interface (eSPI) connection. In some embodiments, PMC firmware can escalate to a global reset, even if the EC requests a warm reset that does not restart the whole system101.

The EC150may use this eSPI connection185to detect when a platform error occurs and obtain the crash log data145stored in the shared SRAM152. For example, the CATERR pin from the CPU that is signaled whenever there is a catastrophic error detected on the CPU. For example, when a certain command is read from the eSPI185, the PMC153checks if a crash log has already been collected in the shared SRAM152of the controller hub152. If a crash log data145is not detected, the PMC153triggers the crashlog unit140to perform a crash log collection for the crash log data145of the core region112, uncore region114and the controller hub150. Thereupon, the crashlog unit140writes the contents of the crash log data145to the eSPI185write data buffer for passage to EC agent190, which may store the crash log data to flash storage connected to the EC. An advantage of the capability using the EC180is that it allows for the crash log information to be collected before the platform initiates a global reset or is shutdown as a result of a crash.

FIG. 2is block diagram illustrating a request command data structure200according to various embodiments. The request command data structure200may be issued by an EC (e.g., EC180) to trigger the production and extraction of the crash logs data145. For example, the EC180may issue the request command data structure200in response to receiving a CATERR signal from processing device100. The request command data structure200includes the following fields, which is a non-exhaustive list:

Tag: Unique identifier of the transaction

Length: Length of the entire transaction in bytes

Dest Slave Address: Address of the eSPI slave to which the transaction is being sent

Command Code: The opcode of the transaction

Byte Count: Number of bytes of the payload of the transaction

Source Slave Address: Address of the eSPI slave from which the transaction was generated

FIG. 3is block diagram illustrating a response command data structure300according to various embodiments. In response to the request from the EC180, the response command data structure300comprising crash log data is written to the eSPI185write data buffer for passage to EC agent190. The response command data structure300includes the following fields, which is a non-exhaustive list:

Tag: Unique identifier of the transaction

Length: Length of the entire transaction in bytes

Dest Slave Address: Address of the eSPI slave to which the transaction is being sent

Command Code: The opcode of the transaction

Byte Count: Number of bytes of the payload of the transaction

Crash Data Record: Aggregate Crash Data from a Crash Node.

FIG. 4illustrates a flow diagram400for initiating data flow collections420,440,460and480according to various embodiments. In some embodiments, each data flow collection is associated with collect crash log data. The crash log data is the lowest granularity of data to be collected when a crash is detected. This is typically in the form of a single register or a single trace message. For example, the crash log data may be collected from certain registers relevant to a particular event. In some embodiments, a crash data requestor is responsible for generating crash data requests and either stores or forwards the data to crash data storage (e.g., shared SRAM152of the controller hub150). The crash data requestor is typically the P-unit, PMC, CSME, external baseboard controller (e.g., BMC). When a crash detector identifies a subsystem that has failed, the crash data requestor may execute a crash data collector (e.g., crashlog unit140) to implement the data flow collections420,440,460and480. For example, data flow collection420collects data from registers of the core region112of a processing device100, data flow collection440collects data from registers of the uncore region114, data flow collection460collects data from registers of the core region112, data flow collection460collects the crashlog data based on a global reset event. In some embodiment, the data flow collections420,440,460and480may be triggered and work independently, but also work in tandem to form one integrated collection flow of crash data. The crash data collector then makes the data in the crash data storage (e.g., shared SRAM152of the controller hub150) available to software (e.g., system firmware) after a platform reset. In some embodiments, a crash data extractor (e.g., system agent) gathers the crash log data145and publishes this data for a consumer, such as operating system or management server.

Data flow collection420for the core region112, begins in block421where an error signal (e.g., IERR/CATERR) is detected. In block422, it is determined whether the crashlog unit140is enabled. If not, the system101enters a shutdown sleep state in block425. Otherwise, crashlog unit140collects crashlog data145for the core region112in a mailbox142in block423. In block424, the crashlog unit140exposes the crashlog data so that it can be copied to the shared memory152of the controller hub150.

In some embodiments, the data flow collection440for the uncore region140, begins with a hand off the crashlog data collection in block446. In other embodiments, the data flow collection440for the uncore region140can be trigger manual or by detecting a CATERR in block441. In block442, it is determined whether the crashlog unit140is enabled. If not, the data flow collection440ends. Otherwise, crashlog unit140writes data associated with the uncore registers125to the shared SRAM152of the controller hub150in block443. In block444, the crashlog unit140then reads the crashlog data for the mailbox142of the core that signaled the error. In block445, it is determined whether the crashlog data is present. If not, the PMC153is instructed to hold off on the reset until receiving an acknowledgement signal that the data collection is complete.

In some embodiments, the data flow collection460for the controller hub150, begins with a hand off the crashlog data collection in block464. In other embodiments, the data flow collection460for the controller hub150is initiated in block461when the PMC153receives a reset signal. In block462, it is determined whether the crashlog unit140is enabled. If it is, then in block463it is determined what type of crash has occurred. In block464, the crashlogs for the core and uncore are collected. In block465, it is determined whether the crashlogs are present. In block466, data from registers in the controller hub150are collected and stored in the shared SRAM152. In block468, the PMC sends the reset signal to the controller hub150. In block469, the PMC waits for an acknowledgment from the platform. In block470, it is determined whether the acknowledgment is received or a timeout is triggered. In block471, the PMC153completes the reset.

Data flow collection480, begins in block481where it is determined whether the crashlog data145is present in the shared SRAM. If so, the BIOS160reads the log into a data structure (e.g., advanced configuration power interface (ACPI) table) in main memory. This data structure can later be stored onto a file in the hard drive or some non-volatile storage by, for example, a host application.

FIG. 5illustrates a flow diagram of a method500for supporting hang detection and data recovery in microprocessor systems according to one embodiment. Method500may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing device), firmware, or a combination thereof. In one embodiment, the crashlog unit140of processing device100inFIG. 1may perform method500. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated implementations should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every implementation. Other process flows are possible.

Method500begins, at block510, where an indication221,241,261of an unresponsive state in an execution of a pending instruction113by a core110-1is received. In block520, a crash log145is produced in response to receiving the indication221,241,261. The crash log224,246and266comprises data from registers115,125,155of at least one of: a core region112, a non-core region114and a controller hub150associated with a processing device101. In block530, the crash log145is stored in shared memory152of a power management controller (PMC)153associated with the controller hub150.

FIG. 6Ais a block diagram illustrating a micro-architecture for a processor600that implements techniques for supporting hang detection and data recovery in microprocessor systems in accordance with one embodiment of the disclosure. Specifically, processor600depicts an in-order architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the disclosure. In one implementation, processor600is the same as processor100to perform hang detection and data recovery described with respect toFIG. 1.

Processor600includes a front-end unit630coupled to an execution engine unit650, and both are coupled to a memory unit670. The processor600may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, processor600may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like. In one embodiment, processor600may be a multi-core processor or may part of a multi-processor system.

The front end unit630includes a branch prediction unit632coupled to an instruction cache unit634, which is coupled to an instruction translation lookaside buffer (TLB)636, which is coupled to an instruction fetch unit638, which is coupled to a decode unit640. The decode unit640(also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder640may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware embodiments, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit634is further coupled to the memory unit670. The decode unit640is coupled to a rename/allocator unit652in the execution engine unit650.

The execution engine unit650includes the rename/allocator unit652coupled to a retirement unit654and a set of one or more scheduler unit(s)656. The scheduler unit(s)656represents any number of different schedulers, including reservations stations (RS), central instruction window, etc. The scheduler unit(s)656is coupled to the physical register file(s) unit(s)658. Each of the physical register file(s) units658represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s)658is overlapped by the retirement unit654to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The execution engine unit650may include for example a power management unit (PMU)690that governs power functions of the functional units.

Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit654and the physical register file(s) unit(s)658are coupled to the execution cluster(s)660. The execution cluster(s)660includes a set of one or more execution units662and a set of one or more memory access units664. The execution units662may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)656, physical register file(s) unit(s)658, and execution cluster(s)660are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units664is coupled to the memory unit670, which may include a data prefetcher680, a data TLB unit672, a data cache unit (DCU)674, and a level 2 (L2) cache unit676, to name a few examples. In some embodiments DCU674is also known as a first level data cache (L1 cache). The DCU674may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency. The data TLB unit672is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces. In one exemplary embodiment, the memory access units664may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit672in the memory unit670. The L2 cache unit676may be coupled to one or more other levels of cache and eventually to a main memory.

In one embodiment, the data prefetcher680speculatively loads/prefetches data to the DCU674by automatically predicting which data a program is about to consume. Prefeteching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., lower level caches or memory) to a higher-level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.

In one embodiment, processor600may be the same as processing device100described with respect toFIG. 1supporting hang detection and data recovery in microprocessor systems as described with respect to embodiments of the disclosure.

The processor600may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.).

FIG. 6Bis a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processor600ofFIG. 6Aaccording to some embodiments of the disclosure. The solid lined boxes inFIG. 6Billustrate an in-order pipeline, while the dashed lined boxes illustrates a register renaming, out-of-order issue/execution pipeline. InFIG. 6B, a processor pipeline601includes a fetch stage602, a length decode stage604, a decode stage606, an allocation stage608, a renaming stage610, a scheduling (also known as a dispatch or issue) stage612, a register read/memory read stage614, an execute stage616, a write back/memory write stage618, an exception handling stage622, and a commit stage624. In some embodiments, the ordering of stages602-624may be different than illustrated and are not limited to the specific ordering shown inFIG. 6B.

FIG. 7illustrates a block diagram of the micro-architecture for a processor700that includes logic circuits to implement techniques for supporting hang detection and data recovery in microprocessor systems in accordance with one embodiment of the disclosure. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as data types, such as single and double precision integer and floating point data types. In one embodiment the in-order front end701is the part of the processor700that fetches instructions to be executed and prepares them to be used later in the processor pipeline.

The front end701may include several units. In one embodiment, the instruction prefetcher726fetches instructions from memory and feeds them to an instruction decoder728, which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache730takes decoded uops and assembles them into program ordered sequences or traces in the uop queue734for execution. When the trace cache730encounters a complex instruction, the microcode ROM732provides the uops needed to complete the operation.

Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder728accesses the microcode ROM732to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder728. In another embodiment, an instruction can be stored within the microcode ROM732should a number of micro-ops be needed to accomplish the operation. The trace cache730refers to an entry point programmable logic array (PLA) to determine a correct microinstruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM732. After the microcode ROM732finishes sequencing micro-ops for an instruction, the front end701of the machine resumes fetching micro-ops from the trace cache730.

The out-of-order execution engine703is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler702, slow/general floating point scheduler704, and simple floating point scheduler706. The uop schedulers702,704,706, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. The fast scheduler702of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files708,710sit between the schedulers702,704,706, and the execution units712,714,716,718,720,722,724in the execution block711. There is a separate register file708,710, for integer and floating-point operations, respectively. Each register file708,710, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file708and the floating-point register file710are also capable of communicating data with the other. For one embodiment, the integer register file708is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data. The floating-point register file710of one embodiment has 128 bit wide entries because floating-point instructions typically have operands from 64 to 128 bits in width.

The execution block711contains the execution units712,714,716,718,720,722,724, where the instructions are actually executed. This section includes the register files708,710that store the integer and floating point data operand values that the microinstructions need to execute. The processor700of one embodiment is comprised of a number of execution units: address generation unit (AGU)712, AGU714, fast ALU716, fast ALU718, slow ALU720, floating point ALU722, floating point move unit724. For one embodiment, the floating-point execution blocks722,724, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU722of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the disclosure, instructions involving a floating-point value may be handled with the floating-point hardware.

In one embodiment, the ALU operations go to the high-speed ALU execution units716,718. The fast ALUs716,718, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU720as the slow ALU720includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. The AGUs712,714may execute memory load/store operations. For one embodiment, the integer ALUs716,718,720, are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs716,718,720, can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating-point units722,724, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating-point units722,724, can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, the uops schedulers702,704,706, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor700, the processor700also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

The processor700also includes logic according to embodiments of the disclosure. In one embodiment, the execution block711of processor700may include a crashlog unit140for implementing techniques for supporting hang detection and data recovery in microprocessor systems in accordance with one embodiment of the disclosure. In some embodiments, processor700may be the processing device100ofFIG. 1.

The term “registers” may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store thirty-two bit integer data. In one embodiment, a register file also includes eight (8) multimedia SIMD register(s) for the packed data.

For the discussions below, the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMX™ registers (also referred to as ‘mm’ registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as “SSEx”) technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

Embodiments may be implemented in many different system types. Referring now toFIG. 8, shown is a block diagram illustrating a system800in which an embodiment of the disclosure may be used. As shown inFIG. 8, multiprocessor system800is a point-to-point interconnect system, and includes a first processor870and a second processor880coupled via a point-to-point interconnect850. While shown with only two processors870,880, it is to be understood that the scope of embodiments of the disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor. In one embodiment, the multiprocessor system800may implement techniques for supporting hang detection and data recovery in microprocessor systems as described herein. In some embodiments, the two processors870,880are the processing device100ofFIG. 1.

Processors870and880are shown including integrated memory controller units872and882, respectively. Processor870also includes as part of its bus controller units point-to-point (P-P) interfaces876and878; similarly, second processor880includes P-P interfaces886and888. Processors870,880may exchange information via a point-to-point (P-P) interface850using P-P interface circuits878,888. As shown inFIG. 8, IMCs872and882couple the processors to respective memories, namely a memory832and a memory834, which may be portions of main memory locally attached to the respective processors.

Processors870,880may exchange information with a chipset890via individual P-P interfaces852,854using point-to-point interface circuits876,894,886,898. Chipset890may also exchange information with a high-performance graphics circuit838via a high-performance graphics interface839.

Chipset890may be coupled to a first bus816via an interface896. In one embodiment, first bus816may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the disclosure is not so limited.

As shown inFIG. 8, various I/O devices814may be coupled to first bus816, along with a bus bridge818, which couples first bus816to a second bus820. In one embodiment, second bus820may be a low pin count (LPC) bus. Various devices may be coupled to second bus820including, for example, a keyboard and/or mouse822, communication devices827and a storage unit828such as a disk drive or other mass storage device, which may include instructions/code and data830, in one embodiment. Further, an audio I/O824may be coupled to second bus820. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 8, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 9, shown is a block diagram of a system900in which one embodiment of the disclosure may operate. The system900may include one or more processors910,915, which are coupled to graphics memory controller hub (GMCH)920. The optional nature of additional processors915is denoted inFIG. 9with broken lines. In one embodiment, processors910,915provide for supporting hang detection and data recovery in microprocessor systems according to embodiments of the disclosure. In some embodiments, the processors910,915are the processing device100ofFIG. 1.

Each processor910,915may be some version of the circuit, integrated circuit, processor, and/or silicon integrated circuit as described above. However, it should be noted that it is unlikely that integrated graphics logic and integrated memory control units would exist in the processors910,915.FIG. 9illustrates that the GMCH920may be coupled to a memory940that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non-volatile cache.

The GMCH920may be a chipset, or a portion of a chipset. The GMCH920may communicate with the processor(s)910,915and control interaction between the processor(s)910,915and memory940. The GMCH920may also act as an accelerated bus interface between the processor(s)910,915and other elements of the system900. For at least one embodiment, the GMCH920communicates with the processor(s)910,915via a multi-drop bus, such as a front side bus (FSB)995.

Furthermore, GMCH920is coupled to a display945(such as a flat panel or touchscreen display). GMCH920may include an integrated graphics accelerator. GMCH920is further coupled to an input/output (I/O) power controller hub (controller hub)950, which may be used to couple various peripheral devices to system900. Shown for example in the embodiment ofFIG. 9is an external graphics device960, which may be a discrete graphics device, coupled to controller hub950, along with another peripheral device970.

Alternatively, additional or different processors may also be present in the system900. For example, additional processor(s)915may include additional processors(s) that are the same as processor910, additional processor(s) that are heterogeneous or asymmetric to processor910, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There can be a variety of differences between the processor(s)910,915in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processors910,915. For at least one embodiment, the various processors910,915may reside in the same die package.

Referring now toFIG. 10, shown is a block diagram of a system1000in which an embodiment of the disclosure may operate.FIG. 10illustrates processors1070,1080. In one embodiment, processors1070,1080may provide for supporting hang detection and data recovery in microprocessor systems as described above. Processors1070,1080may include integrated memory and I/O control logic (“CL”)1072and1082, respectively and intercommunicate with each other via point-to-point interconnect1050between point-to-point (P-P) interfaces1078and1088respectively. Processors1070,1080each communicate with chipset1090via point-to-point interconnects1052and1054through the respective P-P interfaces1076to1094and1086to1098as shown. For at least one embodiment, the CL1072,1082may include integrated memory controller units. CLs1072,1082may include I/O control logic. As depicted, memories1032,1034coupled to CLs1072,1082and I/O devices1014are also coupled to the control logic1072,1082. Legacy I/O devices1015are coupled to the chipset1090via interface1096. The embodiments of the processing device100ofFIG. 1may be implemented in processor1070, processor1080, or both.

Embodiments may be implemented in many different system types.FIG. 11is a block diagram of a SoC1100in accordance with an embodiment of the disclosure. Dashed lined boxes are optional features on more advanced SoCs. InFIG. 11, an interconnect unit(s)1112is coupled to: an application processor1120which includes a set of one or more cores1102A-N and shared cache unit(s)1106; a system agent unit1110; a bus controller unit(s)1116; an integrated memory controller unit(s)1114; a set of one or more media processors1118which may include integrated graphics logic1108, an image processor1124for providing still and/or video camera functionality, an audio processor1126for providing hardware audio acceleration, and a video processor1128for providing video encode/decode acceleration; an static random access memory (SRAM) unit1130; a direct memory access (DMA) unit1132; and a display unit1140for coupling to one or more external displays. In one embodiment, a memory module may be included in the integrated memory controller unit(s)1114. In another embodiment, the memory module may be included in one or more other components of the SoC1100that may be used to access and/or control a memory. The SoC1100also includes logic to implement crashlog unit140according to embodiments of the disclosure. In one embodiment, the execution block711of SoC1100may include the crashlog unto140for implementing techniques for supporting hang detection and data recovery in microprocessor systems in accordance with one embodiment of the disclosure. In some embodiments, SoC1100may be the processing device100ofFIG. 1.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units1106, and external memory (not shown) coupled to the set of integrated memory controller units1114. The set of shared cache units1106may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

In some embodiments, one or more of the cores1102A-N are capable of multi-threading. The system agent1110includes those components coordinating and operating cores1102A-N. The system agent unit1110may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1102A-N and the integrated graphics logic1108. The display unit is for driving one or more externally connected displays.

The cores1102A-N may be homogenous or heterogeneous in terms of architecture and/or instruction set. For example, some of the cores1102A-N may be in order while others are out-of-order. As another example, two or more of the cores1102A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

The application processor1120may be a general-purpose processor, such as a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, Atom™ or Quark™ processor, which are available from Intel™ Corporation, of Santa Clara, Calif. Alternatively, the application processor1120may be from another company, such as ARM Holdings™, Ltd, MIPS™, etc. The application processor1120may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor1120may be implemented on one or more chips. The application processor1120may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

FIG. 12is a block diagram of an embodiment of a system on-chip (SoC) design in accordance with the disclosure. As a specific illustrative example, SoC1200is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

Here, SOC1200includes 2 cores—1206and1207. Cores1206and1207may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores1206and1207are coupled to cache control1208that is associated with bus interface unit1209and L2 cache1210to communicate with other parts of system1200. Interconnect1210includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described disclosure. In one embodiment, cores1206,1207may provide for supporting hang detection and data recovery in microprocessor systems as described in embodiments herein. In some embodiments, the cores1206,1207are the processing cores110ofFIG. 1.

Interconnect1210provides communication channels to the other components, such as a Subscriber Identity Module (SIM)1230to interface with a SIM card, a boot ROM1235to hold boot code for execution by cores1206and1207to initialize and boot SoC1200, a SDRAM controller1240to interface with external memory (e.g. DRAM1260), a flash controller1247to interface with non-volatile memory (e.g. Flash1265), a peripheral control1250(e.g. Serial Peripheral Interface) to interface with peripherals, video codecs1220and Video interface1225to display and receive input (e.g. touch enabled input), GPU1215to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the disclosure described herein. In addition, the system1200illustrates peripherals for communication, such as a Bluetooth module1270, 3G modem1275, GPS1280, and Wi-Fi1185.

The computer system1300includes a processing device1302, a main memory1304(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory1306(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device1318, which communicate with each other via a bus1330.

Processing device1302represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device1302may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device1302may include one or more processing cores. The processing device1302is configured to execute the processing logic1326for performing the operations and steps discussed herein. In one embodiment, processing device1302is the same as processing device100described with respect toFIG. 1that implement techniques for supporting hang detection and data recovery in microprocessor systems as described herein with embodiments of the disclosure.

The computer system1300may further include a network interface device1308communicably coupled to a network1320. The computer system1300also may include a video display unit1310(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device1312(e.g., a keyboard), a cursor control device1314(e.g., a mouse), and a signal generation device1316(e.g., a speaker). Furthermore, computer system1300may include a graphics-processing unit1322, a video processing unit1328, and an audio processing unit1332.

The data storage device1318may include a machine-accessible storage medium1324on which is stored software1326implementing any one or more of the methodologies of functions described herein, such as implementing crashlog unit140in processing device100forFIG. 1, as described above. The software1326may also reside, completely or at least partially, within the main memory1304as instructions1326and/or within the processing device1302as processing logic1326during execution thereof by the computer system1300; the main memory1304and the processing device1302also constituting machine-accessible storage media. In some embodiments, data storage device1318may include a non-transitory computer-readable storage medium, such as computer-readable storage medium1324, on which may store instructions1326encoding any one or more of the methods or functions described herein, including instructions encoding the techniques including the crashlog unit140ofFIG. 1.

The following examples pertain to further embodiments.

Example 1 Example 1 includes a processing device comprising: a processing core; and a crashlog unit, operatively coupled to the core, to receive an indication of an unresponsive state in an execution of a pending instruction by the core; responsive to receiving the indication, produce a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device; and store the crash log in a shared memory of a power management controller (PMC) associated with the controller hub.

Example 2 includes the processing device of example 1, wherein the crashlog unit is further to: responsive to detecting a system reset, determine, using a basic input output system (BIOS), that the crash logs are stored in the shared memory of the PMC; and copy, using the BIOS, the crash logs to advanced configuration power interface (ACPI) data structure.

Example 3 includes the processing device of example 1, wherein the crashlog unit is further to: responsive to detecting that a time to retire an operation of the pending instruction exceeds a timeout threshold, retrieve the crash log comprising the data from registers of the core region.

Example 4 includes the processing device of example 1, wherein the crashlog unit is further to, responsive to detecting that a hardware error code associated with the core, retrieve the crash log comprising the data from registers of the uncore region.

Example 5 includes the processing device of example 1, wherein the crashlog unit is further to, responsive to detecting a reset event associated with the controller hub, retrieve the crash log comprising the data from registers of the controller hub region.

Example 6 includes the processing device of example 1, wherein the crashlog unit is further to write the crash log associated with the core region to a communication channel outside of the core that is in the unresponsive state.

Example 7 includes the processing device of example 1, wherein the crashlog unit is further to: receive a command via an enhanced serial peripheral interface (eSPI); determine whether the crash logs are stored in the shared memory of the PMC; and retrieve the data associated with the crash logs to transmit, via the eSPI, to an embedded controller (EC).

Example 8 includes a method comprising: receiving, by a processing device, an indication of an unresponsive state in an execution of a pending instruction by the core; responsive to receiving the indication, producing, by the processing device, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device; and storing, by the processing device, the crash log in a shared memory of a power management controller (PMC) associated with the controller hub.

Example 9 includes the method of example 8, further comprising: responsive to detecting a system reset, determining, using a basic input output system (BIOS), that the crash logs are stored in the shared memory of the PMC; and copying, using the BIOS, the crash logs to advanced configuration power interface (ACPI) data structure.

Example 10 includes the method of example 8, further comprising: responsive to detecting that a time to retire an operation of the pending instruction exceeds a timeout threshold, retrieving the crash log comprising the data from registers of the core region.

Example 11 includes the method of example 8, further comprising: responsive to detecting that a hardware error code associated with the core, retrieving the crash log comprising the data from registers of the uncore region.

Example 12 includes the method of example 8, further comprising: responsive to detecting a reset event associated with the controller hub, retrieving the crash log comprising the data from registers of the controller hub region.

Example 13 includes the method of example 8, further comprising: writing the crash log associated with the core region to a communication channel outside of the core that is in the unresponsive state.

Example 14 includes the processing device of example 1, further comprising: receiving a command via an enhanced serial peripheral interface (eSPI); determining whether the crash logs are stored in the shared memory of the PMC; and retrieving the data associated with the crash logs to transmit, via the eSPI, to an embedded controller (EC).

Example 15 includes a system comprising: a controller hub; and a crashlog unit, operatively coupled to the controller hub, to receive an indication of an unresponsive state in an execution of a pending instruction by the core; responsive to receiving the indication, produce a crash log comprising data from registers of at least one of: a core region, a non-core region and the controller hub; and store the crash log in a shared memory of a power management controller (PMC) associated with the controller hub.

Example 16 includes the system of example 15, wherein the crashlog unit is further to: responsive to detecting a system reset, determine, using a basic input output system (BIOS), that the crash logs are stored in the shared memory of the PMC; and copy, using the BIOS, the crash logs to advanced configuration power interface (ACPI) data structure.

Example 17 includes the system of example 15, wherein the crashlog unit is further to: responsive to detecting that a time to retire an operation of the pending instruction exceeds a timeout threshold, retrieve the crash log comprising the data from registers of the core region.

Example 18 includes the system of example 15, wherein the crashlog unit is further to, responsive to detecting that a hardware error code associated with the core, retrieve the crash log comprising the data from registers of the uncore region.

Example 19 includes the system of example 15, wherein the crashlog unit is further to, responsive to detecting a reset event associated with the controller hub, retrieve the crash log comprising the data from registers of the controller hub region.

Example 20 includes the system of example 15, wherein the crashlog unit is further to write the crash log associated with the core region to a communication channel outside of the core that is in the unresponsive state.

While the disclosure has been described respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations there from. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this disclosure.

Furthermore, use of the phrases ‘to,’ capable of/to,′ and/or ‘operable to,’ in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.