Trimming apparatus

A trimming apparatus for adjusting an electric property of a trimming object circuit. The trimming apparatus includes a data input pad that receives an input of serial data, a shift register that outputs parallel setting data by shifting the received serial data, a trimming data generating circuit, and a cutting control circuit that controls application of an electric signal to the trimming data generating circuit. The trimming data generating circuit includes a plurality of trimming elements, each having a conductive part cuttable by a flow of the electric signal, a plurality of pull-up resistors respectively connected to high potential sides of the trimming elements, and a plurality of switches respectively connected to low potential sides of the trimming elements. The trimming data generating circuit is configured to generate trimming data for the trimming object circuit by switching the plurality of switches in accordance with a level of the setting data.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-240358, filed on Dec. 9, 2015, and Japanese Patent Application No. 2016-201404, filed on Oct. 13, 2016, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The embodiments discussed herein relate to a trimming apparatus.

2. Background of the Related Art

In general, manufacturing variations result that electric properties of circuit components, such as ICs (Integrated Circuits), deviate from their standard values. The deviation beyond a tolerable value would cause an error and affect circuit operation. Consequently, in manufacturing semiconductor devices, trimming is performed to correct deviations from the standard values of electric properties.

In a trimming circuit, usually a bit value is set in a trimming object by cutting a prescribed fuse with a signal inputted from a pad. In this application, “cutting” a fuse refers to causing the fuse to blow.

Conventionally, there has been proposed a technique of creating, prior to cutting a fuse within ICs, a state simulating the fuse being cut so as to allow estimation of the result of fuse cutting.

Some conventional trimming circuits do not allow estimation of an after-fuse-cutting state before the fuse is actually cut. Some electric properties may not necessarily fall within their standards after fuse cutting, and therefore failing to estimate the after-fuse-cutting state before cutting the fuse may result in a problem of reduced manufacturing yield rate (percentage of non-defective products among those released from the production line).

Meanwhile, in a trimming circuit of the above literatures, an after-fuse-cutting state may be preliminarily estimated by processing input data coming from a pad through a shift register and a selector. In the configuration of the trimming circuit in the above literatures, however, there exists a problem that an increase of bit width to be set in a circuit to be trimmed causes the number of pads, i.e., external input terminals to increase, accompanied with an increase of chip area as well.

SUMMARY OF THE INVENTION

According to an aspect, there is provided a trimming apparatus for adjusting an electric property value of a trimming object circuit. The trimming apparatus includes: a single data input pad that receives input of serial data to allow input of an n-bit value to the trimming object circuit; a shift register that outputs parallel setting data by shifting the serial data received through the data input pad by n bits; a trimming data generating circuit that includes trimming elements having conductive parts which are cuttable by a flow of an electric signal, pull-up resistors respectively connected to high potential sides of the trimming elements, and switches respectively connected to low potential sides of the trimming elements, and that generates trimming data to be inputted to the trimming object circuit from nodes by switching the switches in accordance with a level of the setting data, the nodes respectively connecting the pull-up resistors and the trimming elements; and a cutting control circuit that controls application of the electric signal to the trimming data generating circuit.

DETAILED DESCRIPTION OF THE INVENTION

Several embodiments will be described below with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

First Embodiment

FIG. 1illustrates an exemplary hardware configuration of a trimming apparatus. A trimming apparatus1according to a first embodiment includes a data input pad p, a trimming object circuit1a, a shift register1b, a trimming data generating circuit1c, and a cutting control circuit1d.

The trimming object circuit1acorresponds to a device or the like which may be trimmed to have a bit value set therein.FIG. 1illustrates a case of a 3-bit (trim0to trim2) circuit.

The data input pad p is a single pad which receives input of serial data d0to allow input of an n (=1, 2, 3, . . . ) bit value to the trimming object circuit1a. The shift register1bshifts the serial data d0received through the data input pad p by n bits and outputs parallel setting data d1.

Each of the trimming elements f0to f2is an element having a conductive part which is cuttable by a flow of an electric signal c0having at least a rated electric current or voltage, and an example of using fuses is illustrated inFIG. 1(a trimming element is hereunder referred to as a fuse). Note that Zener-zap trimming may be applied by using Zener diodes, besides fuses. In this application, “cutting” a conductive part of a trimming element refers to causing the conductive part to fuse or blow.

The connection relationship between components in the interior of the trimming data generating circuit1cis as follows. One ends of the pull-up resistors R0to R2are connected to a power source VCC. The other ends of the pull-up resistors R0to R2are connected to output terminals of the cutting control circuit1d, input terminals of the buffers IC0to IC2, and one ends of the fuses f0to f2, respectively. Output terminals of the buffers IC0to IC2are connected to the terminals trim0to trim2in the trimming object circuit1a, respectively.

Terminals s0of the switches sw0to sw2are switch control terminals connected to output terminals of the shift register1b, respectively. Terminals s1of the switches sw0to sw2are connected to the other ends of the fuses f0to f2, respectively, and terminals s2of the switches sw0to sw2are connected to GND.

In the configuration, the trimming data generating circuit1cgenerates trimming data d2that is supplied to the trimming object circuit1afrom nodes n0to n2where the pull-up resistors R0to R2are connected to the trimming elements f0to f2, respectively, by switching the switches sw0to sw2in accordance with the levels of the setting data d1. The trimming data d2is generated by buffering the voltages of the nodes n0to n2by the buffers IC0to IC2, and transmitted to the trimming object circuit1a, respectively.

The cutting control circuit1dcontrols the application of an electric signal c0to the trimming data generating circuit1c. Here, when applying the electric signal c0to the trimming data generating circuit1c, the electric signal c0of n bits is applied collectively.

In the trimming apparatus1configured as above, an after-fuse-cutting state may be estimated before the fuse is actually cut and hence the manufacturing yield rate may be improved. Further, it becomes possible to suppress an increase of the number of pads, i.e., external input terminals and hence reduce the chip area, even when the bit width of the trimming object circuit1aincreases.

Problems to be Solved

Problems to be solved are hereunder explained in reference toFIGS. 2 and 3before the details of the technique are explained.FIG. 2illustrates an exemplary configuration of a trimming circuit. The configuration of a conventional trimming circuit incapable of estimating an after-fuse-cutting state before the fuse cutting is illustrated.

The connection relationship between the constituent elements is as follows. A power source VCC is connected to one ends of the resistors R20to R22. The pad P0is connected to the other end of the resistor R20, an input terminal of the buffer IC20, and one end of the fuse f20, and the other end of the fuse f20is connected to GND. An output terminal of the buffer IC20is connected to a terminal trim0of the trimming object circuit20a.

The pad P1is connected to the other end of the resistor R21, an input terminal of the buffer IC21, and one end of the fuse f21, and the other end of the fuse f21is connected to GND. An output terminal of the buffer IC21is connected to a terminal trim1of the trimming object circuit20a.

The pad P2is connected to the other end of the resistor R22, an input terminal of the buffer IC22, and one end of the fuse f22, and the other end of the fuse f22is connected to GND. An output terminal of the buffer IC22is connected to a terminal trim2of the trimming object circuit20a.

Here, the relationship between the resistance values of the resistors R20to R22and the resistance values of the fuses f20to f22satisfies inequality expressions R20>>f20, R21>>f21, and R22>>f22.

Here, it is assumed that an electric property of the trimming object circuit20adeviates from a standard and the respective bit values of the trimming object circuit20aneed to be corrected to {trim2, trim1, trim0}={0, 0, 1}.

In an initial state, because the inequality expressions R20>>f20, R21>>f21, and R22>>f22hold, nodes N0to N2conduct to the GND side and the outputs of the buffers IC20to IC22take an L level. Therefore, the respective bit values of the trimming object circuit20aare given as {trim2, trim1, trim0}={0, 0, 0}.

Accordingly, when trimming is applied, a voltage is applied to the pad P0to cut the fuse f20. As a result, the node N0is pulled up to the power source VCC by the resistor R20and hence only the output terminal of the buffer IC20takes an H level. Therefore, the respective bit values of the trimming object circuit20aare set to {trim2, trim1, trim0}={0, 0, 1}, and in this way, the electric property of a trimming object is corrected.

FIG. 3illustrates an exemplary configuration of a trimming circuit. The configuration of a conventional trimming circuit, disclosed in Japanese Laid-open Patent Publication No. 05-63090, capable of estimating an after-fuse-cutting state before the fuse cutting is illustrated.

Here, a shift register30bhas the flip-flops IC35to IC37and a selector30chas the inverter IC38and the selector elements IC39to IC41. Further, each of the selector elements IC39to IC41has two AND elements and one NOR element.

The connection relationship between the constituent elements is as follows. The pad P10is connected to one end of the fuse f30, one end of the resistor R30, and an input terminal of the inverter IC30, the other end of the fuse f30is connected to GND, and the other end of the resistor R30is connected to a power source VCC.

The pad P11is connected to one end of the fuse f31, one end of the resistor R31, and an input terminal of the inverter IC31, the other end of the fuse f31is connected to GND, and the other end of the resistor R31is connected to the power source VCC.

The pad P12is connected to one end of the fuse f32, one end of the resistor R32, and an input terminal of the inverter IC32, the other end of the fuse f32is connected to GND, and the other end of the resistor R32is connected to the power source VCC.

The pad P13is connected to one end of the resistor R33and an input terminal of the buffer IC33, and the other end of the resistor R33is connected to GND.

The pad P14is connected to one end of the resistor R34and an input terminal of the buffer IC34, and the other end of the resistor R34is connected to GND.

An output terminal of the inverter IC30is connected to an input terminal a4of the selector element IC39, an output terminal of the inverter IC31is connected to an input terminal a4of the selector element IC40, and an output terminal of the inverter IC32is connected to an input terminal a4of the selector element IC41.

An output terminal of the buffer IC33is connected to clock terminals (C) of the flip-flops IC35to IC37, an input terminal of the inverter IC38, and input terminals a2of the selector elements IC39to IC41.

An output terminal of the buffer IC34is connected to an input terminal (D) of the flip-flop IC37. An output terminal of the inverter IC38is connected to input terminals a3of the selector elements IC39to IC41.

An output terminal (QN) of the flip-flop IC35is connected to an input terminal a1of the selector element IC39, and an input terminal (D) of the flip-flop IC35is connected to an output terminal (QN) of the flip-flop IC36and an input terminal a1of the selector element IC40. An input terminal (D) of the flip-flop IC36is connected to an output terminal (Q) of the flip-flop IC37. Output terminals of the selector elements IC39to IC41are connected to terminals trim0to trim2of the trimming object circuit30a, respectively.

The trimming circuit30of such a configuration sends data to the shift register30bby changing the voltage of the pad P13from an L level to an H level, selects an output of the shift register30bby the selector30c, and sends the output to the trimming object circuit30a. As a result, the state of the trimming object circuit30aafter fuse cutting may be estimated without cutting a fuse.

Here, the trimming circuit20illustrated inFIG. 2may not estimate an after-fuse-cutting state before the fuse cutting. Consequently, an electric property may not necessarily fall within a standard after fuse cutting, which may result in a reduced manufacturing yield rate.

In contrast, the trimming circuit30illustrated inFIG. 3allows an after-fuse-cutting state to be preliminarily estimated. In such a circuit configuration, however, an increase of the bit width of the trimming object circuit30acauses increases in the number of flip-flops in the shift register30band in the number of selector elements in the selector30c, accompanied with an increase of the number of pads as well. An increase of the number of pads, i.e., external input terminals causes a chip area to increase.

Note that the problem of the circuit configuration disclosed in Japanese Laid-open Patent Publication No. 05-63090 has heretofore been described and the problem of the circuit configuration disclosed in Japanese Laid-open Patent Publication No. 2010-267922 is likewise that, when the bit width of the trimming object circuit increases, the number of pads, i.e., external input terminals, increases and a chip area also increases.

The embodiments discussed herein are established in view of such aspects and provide a trimming apparatus that may improve a yield and may reduce a chip area even when a bit width to be set for a trimming object increases.

Second Embodiment

A trimming apparatus according to a second embodiment is hereunder explained in detail.FIG. 4illustrates an exemplary configuration of a trimming apparatus. A trimming apparatus10according to the second embodiment includes a 3-bit (trim0to trim2) trimming object circuit10a, a shift register10b, a trimming data generating circuit10c, and a cutting control circuit10d.

A pad p0is a control signal input pad which receives input of a control signal for fuse cutting, a pad p1is a voltage applying pad for fuse cutting (electric signal input pad), and a pad p2is a set disable signal input pad of the shift register10b.

Further, a pad p3is a data input pad, and a pad p4is a clock input pad. Here, prescribed values are set in data to be input to the pads p0to p4, by an upper device (processor or the like) not illustrated inFIG. 4.

The connection relationship between the constituent elements is as follows. A power source VCC is connected to one ends of the resistors R10to R12and R14. The pad p0is connected to the other end of the resistor R14and the gates of the PMOS transistors M10to M12. The pad p1is connected to one end of the resistor R15and the sources of the PMOS transistors M10to M12, and the other end of the resistor R15is connected to GND.

The drain of the PMOS transistor M10is connected to the other end of the resistor R10, an input terminal of the buffer IC10, and one end of the fuse f10. The drain of the PMOS transistor M11is connected to the other end of the resistor R11, an input terminal of the buffer IC11, and one end of the fuse f11. The drain of the PMOS transistor M12is connected to the other end of the resistor R12, an input terminal of the buffer IC12, and one end of the fuse f12.

An output terminal of the buffer IC10is connected to the terminal trim0of the trimming object circuit10a, an output terminal of the buffer IC11is connected to the terminal trim1of the trimming object circuit10a, and an output terminal of the buffer IC12is connected to the terminal trim2of the trimming object circuit10a.

The drain of the NMOS transistor M0is connected to the other end of the fuse f10, and the source of the NMOS transistor M0is connected to GND. The drain of the NMOS transistor M1is connected to the other end of the fuse f11, and the source of the NMOS transistor M1is connected to GND. The drain of the NMOS transistor M2is connected to the other end of the fuse f12, and the source of the NMOS transistor M2is connected to GND.

The pad p2is connected to one end of the resistor R16and set terminals (S) of the flop-flops IC110to IC112, and the other end of the resistor R16is connected to GND. The pad p3is connected to one end of the resistor R17and an input terminal (D) of the flip-flop IC112, and the other end of the resistor R17is connected to GND. The pad p4is connected to one end of the resistor R18and clock terminals (C) of the flop-flops IC110to IC112, and the other end of the resistor R18is connected to GND.

An output terminal (Q) of the flip-flop IC110is connected to a gate of the NMOS transistor M0. An output terminal (Q) of the flip-flop IC111is connected to a gate of the NMOS transistor M1and an input terminal (D) of the flip-flop IC110. An output terminal (Q) of the flip-flop IC112is connected to a gate of the NMOS transistor M2and an input terminal (D) of the flip-flop IC111.

Operations of the apparatus will be explained below. The operation mode of the trimming apparatus10is divided into three phases: a trimming estimation phase, a fuse cutting phase, and an actual operation phase.

The trimming estimation phase is a phase for estimating an after-fuse-cutting state before the fuse is actually cut. The fuse cutting phase is a phase for cutting a prescribed fuse. The actual trimming phase is an operation phase in a state after trimming is performed in the fuse cutting phase. The phases will be explained hereunder.

The PMOS transistors M10to M12are turned off, and data and a clock are inputted to the shift register10b. The data is inputted through the pad p3and the clock is inputted through the pad p4to the shift register10b.

In the case where the outputs of the flip-flops IC110to IC112included in the shift register10bare at an H level when the shift register10breceives the data and the clock, H level signals (corresponding to first-level setting data) are applied to the gates of the NMOS transistors M0to M2.

In this instance, since the NMOS transistors M0to M2connected to the GND side of the fuses f10to f12are turned on, nodes n0to n2conduct to the GND side and the outputs of the buffers IC10to IC12take an L level. Consequently, the respective bit values of the trimming object circuit10aare given as {trim2, trim1, trim0}={0, 0, 0}.

In contrast, when the outputs of the flip-flops IC110to IC112are L level signals (corresponding to second-level setting data), the L levels are applied to the gates of the NMOS transistors M0to M2.

In this instance, the NMOS transistors M0to M2are turned off, the nodes n0to n2are pulled up to the power source VCC, and hence the outputs of the buffers IC10to IC12take the H level. Consequently, the respective bit values of the trimming object circuit10aare given as {trim2, trim1, trim0}={1, 1, 1}.

As thus described, inputting prescribed serial data through the pad p3and changing an output level (level of setting data) of the shift register10ballows H- or L-level signals to be inputted to the terminals trim0to trim2of the trimming object circuit10a.

As a result, an optimum combination of the respective bit values (trim0to trim2) of the trimming object circuit10aafter fuse cutting may be preliminarily found before fuse cutting.

In the fuse cutting phase, output of the shift register10bis first inverted. For example, it is assumed that the bit values to be set in the trimming object circuit10ahas been estimated to be {trim2, trim1, trim0}={0, 1, 0} in the trimming estimation phase.

Here, when {trim2, trim1, trim0}={0, 1, 0} is settled, the outputs of the shift register10bare {1, 0, 1}. That is to say, the outputs of the flip-flops IC110to IC112are {1, 0, 1} in the trimming estimation phase.

As a result, in the fuse cutting phase, serial data of {0, 1, 0} obtained by inverting the outputs {1, 0, 1} of the shift register10bis inputted to the shift register10bthrough the pad p3, and {0, 1, 0} are outputted from the shift register10b.

Here, since the gates of the NMOS transistors M0and M2take the L level and the gate of the NMOS transistor M1takes the H level, the NMOS transistor M1turns into an ON state, whereas the NMOS transistors M0and M2turn into an OFF state.

Subsequently, a control signal of the L level is inputted to the pad p0, all of the PMOS transistors M10to M12corresponding to fuse cutting switches are turned on, and moreover, an electric signal for fuse cutting is inputted to the pad p1.

Here, among the NMOS transistors M0to M2, the NMOS transistors M0and M2have been turned off, and therefore an electric signal for fuse cutting does not flow in the fuses f10and f12connected to the NMOS transistors M0and M2, and the fuses f10and f12remain connected (uncut).

In contrast, among the NMOS transistors M0to M2, the NMOS transistor M1has been turned on, and therefore an electric signal for fuse cutting flows in the fuse f11connected to the NMOS transistor M1, and only the fuse f11is cut.

The PMOS transistors M10to M12are turned off. Meanwhile, the set function of the shift register10bis active low and the set terminals (S) of the flip-flops IC110to IC112are pulled down by the resistor R16.

As a result, when an H-level set disable signal is not inputted through the pad p2, all of the outputs of the flip-flops IC110to IC112are maintained at the H level. Here, all of the NMOS transistors M0to M2connected to the GND side of the fuses f10to f12turn into the ON state.

Consequently, among the fuses f10to f12, the fuses f10and f12are uncut, the nodes n0and n2turn into the state of conducting to the GND side, hence the nodes n0and n2take the L level, and L-level trimming data is outputted from the buffers IC10and IC12.

Further, the fuse f11is cut, the node n1turns into the Pulled-up state, hence the node n1takes the H level, and H-level trimming data is outputted from the buffer IC11.

That is to say, operation may be performed by fixing the bit values {trim2, trim1, trim0} of the trimming object circuit10ato {0, 1, 0} that are desired values estimated in the trimming estimation phase.

There will be explained below a configuration of the trimming apparatus according to the embodiment in which the number of pads does not increase even when the bit width of a trimming object increases.

FIG. 5illustrates an exemplary configuration of a trimming apparatus having an increased bit width. Although the trimming apparatus10illustrated inFIG. 4has the 3-bit trimming object circuit10a, a trimming apparatus10-1has a 4-bit trimming object circuit10a-1, i.e., the bit width being increased by one.

InFIG. 5, the components surrounded by the dotted-line square frames are components newly added in response to the addition of one bit. The constituent elements newly added to the trimming apparatus10ofFIG. 4are a resistor R13, a PMOS transistor M13, a buffer IC13, a fuse f13, an NMOS transistor M3, and a flip-flop IC113.

Only the connection relationship between the added constituent elements is as follows. An end of the resistor R13is connected to a power source VCC, an end of a resistor R14, and one ends of resistors R10to R12and the other end of the resistor R13is connected to the drain of the PMOS transistor M13, an input terminal of the buffer IC13, and one end of the fuse f13.

The gate of the PMOS transistor M13is connected to a pad p0, the other end of the resistor R14, and the gates of PMOS transistors M10to M12. The source of the PMOS transistor M13is connected to a pad p1, an end of a resistor R15, and the sources of the PMOS transistors M10to M12.

The other end of the fuse f13is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3is connected to GND. An output terminal of the buffer IC13is connected to a terminal trim3of the trimming object circuit10a-1. A gate of the NMOS transistor M3is connected to an input terminal (D) of a flip-flop IC112and an output terminal (Q) of the flip-flop IC113.

An input terminal (D) of the flip-flop IC113is connected to a pad p3and an end of a resistor R17, and a set terminal (S) of the flip-flop IC113is connected to a pad p2and set terminals (S) of the flip-flops IC110to IC112.

Here, in the trimming apparatus10-1, although the bit width of a trimming object increases in comparison with the trimming apparatus10ofFIG. 4, the above addition of the constituent elements as surrounded by the dotted-line frames is sufficient to deal with the increase in the bit width, and therefore it is not needed to change the number (=5) of pads.

In this way, in the trimming apparatus according to the embodiment, a circuit configuration not allowing the number of pads to increase even when the bit width of a trimming object increases is obtained and hence a chip area may reduce.

Third Embodiment

FIG. 6illustrates an exemplary configuration of a trimming apparatus. A trimming apparatus10-2according to a third embodiment includes a 3-bit (trim0to trim2) trimming object circuit10a, a binary counter10b-2, a trimming data generating circuit10c-2, and a cutting control circuit10d.

The circuit sections different from the trimming apparatus10ofFIG. 4are the binary counter10b-2and the trimming data generating circuit10c-2. In the trimming apparatus10-2, the binary counter10b-2is used instead of the shift register10billustrated inFIG. 4. Further, the new trimming data generating circuit10c-2is configured by adding EXCLUSIVE-OR elements (hereunder XOR elements) IC50to IC52, each of the XOR elements having two inputs and one output, as circuit elements to the trimming data generating circuit10cillustrated inFIG. 4. The other circuit configurations are identical toFIG. 4and hence the explanations are made while attention is hereunder focused on the different components.

A pad p0is a control signal input pad which receives input of a control signal for fuse cutting, and a pad p1is a voltage application pad for fuse cutting. Further, a pad p2-2is a set disable signal input pad to input a set disable signal to the binary counter10b-2.

A pad p4-2is a clock input pad to input a clock to the binary counter10b-2. Here, prescribed values are set in the data to be inputted to the pads by upper devices not illustrated inFIG. 6.

The connection relationship in the vicinity of the binary counter10b-2is as follows. The pad p2-2is connected to an end of a resistor R16and set terminals (S) of the flip-flops IC120to IC122, and the other end of the resistor R16is connected to GND. The pad p3-2is connected to an end of a resistor R19and an input terminal of each of the XOR elements IC50to IC52, and the other end of the resistor R19is connected to GND.

The pad p4-2is connected to an end of a resistor R18and a clock terminal of the flip-flop IC122, and the other end of the resistor R18is connected to GND.

An output terminal (Q) of the flip-flop IC120is connected to another input terminal of the XOR element IC50. An output terminal (Q) of the flip-flop IC121is connected to another input terminal of the XOR element IC51and a clock terminal of the flip-flop IC120. An output terminal (Q) of the flip-flop IC122is connected to another input terminal of the XOR element IC52and a clock terminal of the flip-flop IC121.

An input terminal (D) of the flip-flop IC120is connected to an output terminal (QN) of the flip-flop IC120, an input terminal (D) of the flip-flop IC121is connected to an output terminal (QN) of the flip-flop IC121, and an input terminal (D) of the flip-flop IC122is connected to an output terminal (QN) of the flip-flop IC122.

An output terminal of the XOR element IC50is connected to the gate of the NMOS transistor M0, an output terminal of the XOR element IC51is connected to the gate of the NMOS transistor M1, and an output terminal of the XOR element IC52is connected to the gate of the NMOS transistor M2.

As stated above, in the trimming apparatus10-2, the NMOS transistors (trimming estimation MOSs) M0to M2are connected to the GND side of the fuses f10to f12, respectively, and moreover, the output terminals of the XOR elements IC50to IC52are connected to the gates of the NMOS transistors M0to M2, respectively.

Subsequently, one of the input terminals of each of the XOR elements IC50to IC52is connected to the pad p3-2to receive input of a binary counter output inversion signal, and the other input terminals of the XOR elements IC50to IC52are connected to the output terminals (Q) of the binary counter10b-2, respectively, to receive input of setting data representing count-up values outputted from the binary counter10b-2.

In such a configuration, a state where the fuses f10to f12are uncut is created when the NMOS transistors M0to M2are turned on, and a state equivalent to a state where the fuses f10to f12have been cut is created when the NMOS transistors M0to M2are turned off.

Moreover, by inputting a clock through the pad p4-2after the setting of the binary counter10b-2is cancelled, the binary counter10b-2may scan all bit patterns in the state where all the bits (all setting data) take the H level to the L level. As a result, it becomes possible to estimate all possible combinations of the fuses f10to f12being cut or uncut, thereby facilitating a search for a combination of fuse cutting that provides an optimum electric property value of the trimming object circuit10a.

Operations of the trimming apparatus10-2will be explained hereunder. The operation mode of the trimming apparatus10-2is divided into three phases: a trimming estimation phase, a fuse cutting phase, and an actual operation phase, as with the trimming apparatus10illustrated inFIG. 4. The phases will be explained hereunder.

A set disable signal is set to the H level through the pad p2-2, and a binary counter output inversion signal is fixed to the L level through the pad p3-2(first polarity control data is inputted to the pad p3-2). In the state, a clock is inputted to the binary counter10b-2through the pad P4-2. In the state, the levels of the output signals (logic signals) of the XOR elements IC50to IC52are identical to the output levels of the binary counter10b-2.

As a result, when setting data (also referred to as Q outputs hereunder) outputted from the output terminals (Q) of the flip-flops IC120to IC122included in the binary counter10b-2are at the H level, the XOR elements IC50to IC52also output the H level (first level) and hence the NMOS transistors M0to M2that are trimming estimation MOSs are turned on.

Therefore, the relevant bit outputs (signals inputted to the trimming object circuit10a) when the NMOS transistors M0to M2are at the L level, here.

In contrast, when the Q outputs of the flip-flops IC120to IC122are at the L level, the XOR elements IC50to IC52also output the L level (second level) and hence the NMOS transistors M0to M2are turned off. Therefore, the relevant bit outputs are at the H level, here.

As thus described, fixing the binary counter output inversion signal to the L level allows an H- or L-level signal to be inputted to the trimming object circuit10adue to the change of the output level caused by the binary count-up by the binary counter10b-2. As a result, an optimum combination to cut the fuses f10to f12may be preliminarily found before fuse cutting.

For example, all the combinations of the H and L levels may be scanned using 8 clocks when the binary counter is 3 bits and using 16 clocks when the binary counter is 4 bits.

FIG. 7is a time chart representing the gate input state of the trimming estimation MOSs. The gate input state of the NMOS transistors M0to M2in a trimming estimation phase is represented. In the trimming estimation phase, a set disable signal is set to the H level, a binary counter output inversion signal is set to the L level, and a clock is inputted to the binary counter10b-2.

(S0) The set disable signal is at the H level but the clock, which has not been inputted, is at the L level. Consequently, the Q outputs of the flip-flops IC120to IC122are at the H level.

Further, since the binary counter output inversion signal is at the L level, the outputs of the XOR elements IC50to IC52are at the H level and the gate inputs of the NMOS transistors M0to M2are at the H level.

Consequently, the NMOS transistors M0to M2are turned on and the buffers IC10to IC12output the L level. Here, in the trimming estimation phase, since the Q output levels of the flip-flops IC120to IC122are identical to the gate input levels of the NMOS transistors M0to M2, only the gate input levels of the NMOS transistors M0to M2are described hereunder.

(S1) During the first clock, the gate input (gate input M0) of the NMOS transistor M0takes the H level, the gate input (gate input M1) of the NMOS transistor M1takes the H level, and the gate input (gate input M2) of the NMOS transistor M2takes the L level.

Here, the NMOS transistor M0is turned on, the NMOS transistor M1is turned on, and the NMOS transistor M2is turned off. Consequently, the buffer IC10outputs the L level, the buffer IC11outputs the L level, and the buffer IC12outputs the H level.

(S2) During the second clock, the gate input of the NMOS transistor M0takes the H level, the gate input of the NMOS transistor M1takes the L level, and the gate input of the NMOS transistor M2takes the H level.

Here, the NMOS transistor M0is turned on, the NMOS transistor M1is turned off, and the NMOS transistor M2is turned on. Consequently, the buffer IC10outputs the L level, the buffer IC11outputs the H level, and the buffer IC12outputs the L level.

(S3) During the third clock, the gate input of the NMOS transistor M0takes the H level, the gate input of the NMOS transistor M1takes the L level, and the gate input of the NMOS transistor M2takes the L level.

Here, the NMOS transistor M0is turned on, the NMOS transistor M1is turned off, and the NMOS transistor M2is turned off. Consequently, the buffer IC10outputs the L level, the buffer IC11outputs the H level, and the buffer IC12outputs the H level.

(S4) During the fourth clock, the gate input of the NMOS transistor M0takes the L level, the gate input of the NMOS transistor M1takes the H level, and the gate input of the NMOS transistor M2takes the H level.

In this instance, the NMOS transistor M0is turned off, the NMOS transistor M1is turned on, and the NMOS transistor M2is turned on. Consequently, the buffer IC10outputs the H level, the buffer IC11outputs the L level, and the buffer IC12outputs the L level.

(S5) During the fifth clock, the gate input of the NMOS transistor M0takes the L level, the gate input of the NMOS transistor M1takes the H level, and the gate input of the NMOS transistor M2takes the L level.

Here, the NMOS transistor M0is turned off, the NMOS transistor M1is turned on, and the NMOS transistor M2is turned off. Consequently, the buffer IC10outputs the H level, the buffer IC11outputs the L level, and the buffer IC12outputs the H level.

(S6) During the sixth clock, the gate input of the NMOS transistor M0takes the L level, the gate input of the NMOS transistor M1takes the L level, and the gate input of the NMOS transistor M2takes the H level.

Here, the NMOS transistor M0is turned off, the NMOS transistor M1is turned off, and the NMOS transistor M2is turned on. Consequently, the buffer IC10outputs the H level, the buffer IC11outputs the H level, and the buffer IC12outputs the L level.

(S7) During the seventh clock, the gate input of the NMOS transistor M0takes the L level, the gate input of the NMOS transistor M1takes the L level, and the gate input of the NMOS transistor M2takes the L level.

Here, the NMOS transistor M0is turned off, the NMOS transistor M1is turned off, and the NMOS transistor M2is turned off. Consequently, the buffer IC10outputs the H level, the buffer IC11outputs the H level, and the buffer IC12outputs the H level.

Here, when the Q outputs of the flip-flops IC120to IC122included in the binary counter10b-2are at the H level, the NMOS transistors M0to M2are turned on and the outputs of the buffers IC10to IC12take the L level. This state is equivalent to the state of the fuses f10to f12being uncut.

Meanwhile, when the Q outputs of the flip-flops IC120to IC122are at the L level, the NMOS transistors M0to M2are turned off and the outputs of the buffers IC10to IC12take the H level. This state is equivalent to the state of the fuses f10to f12being cut.

In this way, an optimum combination state for the bit values (trim0to trim2) of the trimming object circuit10aafter fuse cutting may be preliminarily found before fuse cutting.

When an electric property value of the trimming object circuit10ais in the optimized state, the clock inputted to the binary counter10b-2is stopped and the binary counter output inversion signal is changed from the L level to the H level (second polarity control data is inputted to the pad p3-2).

As a result, the polarities of the gate inputs of the NMOS transistors M0to M2are inverted. Subsequently, all of the PMOS transistors M10to M12(fuse cutting switches) are turned on and voltage for fuse cutting is applied to the pad p1. Consequently, electric current flows only in the NMOS transistors that were turned off (equivalent to fuses being cut) during trimming estimation, and only desired fuses may be cut.

FIG. 8is a time chart representing the gate input state of the trimming estimation MOSs. The gate input state of the NMOS transistors M0to M2in a fuse cutting phase is represented. In the fuse cutting phase, a binary counter output inversion signal is set to the H level, and moreover, a clock input is stopped.

InFIG. 8, as an example of fuse cutting, the operation when cutting only the fuse f10is illustrated. That is to say, there is illustrated a case in the trimming estimation phase where an electric property value of the trimming object circuit10ais confirmed to be optimized when the trimming data inputted to the trimming object circuit10ais {trim2, trim1, trim0}={0, 0, 1}.

(S14) During the fourteenth clock, the gate input of the NMOS transistor M0takes the L level, the gate input of the NMOS transistor M1takes the H level, and the gate input of the NMOS transistor M2takes the H level.

Here, the NMOS transistor M0is turned off, the NMOS transistor M1is turned on, and the NMOS transistor M2is turned on. Consequently, the buffer IC10outputs the H level, the buffer IC11outputs the L level, and the buffer IC12outputs the L level. Consequently, the trimming data inputted to the trimming object circuit10ais {trim2, trim1, trim0}={0, 0, 1}.

(S15) At step S14, the gate input levels in the fourteenth clock are (gate input M2, gate input M1, gate input M0)=(H, H, L), and {trim2, trim1, trim0}={0, 0, 1} is obtained. Consequently, in the period corresponding to the fifteenth and subsequent clocks, the binary counter output inversion signal is set to the H level, and moreover, the clock input is stopped.

Subsequently, the polarities of the gate inputs of the NMOS transistors M0to M2are inverted and (gate input M2, gate input M1, gate input M0)=(L, L, H) is obtained. That is to say, the gate input of the NMOS transistor M0takes the H level, the gate input of the NMOS transistor M1takes the L level, and the gate input of the NMOS transistor M2takes the L level.

Consequently, the NMOS transistor M0is turned on, the NMOS transistor M1is turned off, and the NMOS transistor M2is turned off.

Subsequently, in this state, the PMOS transistors M10to M12are turned on by inputting a control signal for fuse cutting through the pad p0, and a prescribed voltage is applied through the pad p1. As a result, only the fuse f10is cut and the fuses f11and f12turn into an uncut state.

In an actual operation, since the binary counter output inversion signal is pulled down by the resistor R19, the XOR elements IC50to IC52outputs the received outputs of the binary counter10b-2as they are.

Since the set disable signal of the binary counter10b-2is L active and is pulled down by the resistor R16, all the outputs of the binary counter10b-2take a set state (the H level) and all the NMOS transistors M0to M2are turned on.

Consequently, the L level is outputted from a relevant buffer in the bit of an uncut fuse and the H level is outputted from a relevant buffer in the bit of an already-cut fuse. As has been described above, a desirable operation after fuse trimming may be achieved.

The effects of the embodiments will be explained hereunder while the trimming apparatuses according to the embodiments and conventional technologies are compared.FIG. 9is a table listing the results of relationship between “Estimation of result before fuse cutting” and “number of pads”. The table T1 includes the description items of “Estimation of result before fuse cutting” and “Number of necessary pads” in a bit width of a trimming object circuit.

An impossible “Estimation of result before fuse cutting” means that an after-fuse-cutting state may not be estimated before fuse cutting. In contrast, a possible “Estimation of result before fuse cutting” means that an after-fuse-cutting state may be estimated before fuse cutting.

Here, in the trimming circuit20illustrated inFIG. 2, “Estimation of result before fuse cutting” is impossible and “Number of necessary pads” increases in accordance with an increase in the bit width of a trimming object.

Further, in the trimming circuit30illustrated inFIG. 3, although “Estimation of result before fuse cutting” is possible, “Number of necessary pads” increases in accordance with an increase in the bit width of the trimming object.

In contrast, in the trimming apparatus10according to the embodiment illustrated inFIG. 4and the trimming apparatus10-2illustrated inFIG. 6, “Estimation of result before fuse cutting” is possible and “Number of necessary pads” remains five, meaning that the number of pads does not increase, even when the bit width of a trimming object increases.

FIG. 10is a table listing comparison results of effects. In table T2, “Compared against”, “Effect”, and “Reason for effect” are described. The comparison of the trimming apparatuses10and10-2against the trimming circuit20indicates that the trimming apparatuses10and10-2improve manufacturing yield rates. This is because the after-fuse-cutting state may be estimated before cutting the fuse.

Furthermore, when the bit width of the trimming object is 6 bits or more, a chip cost turns out to be lower in the trimming apparatuses10and10-2. The reason is that, when the bit width of a trimming object is 6 bits or more, the trimming apparatuses10and10-2use fewer pads than the trimming circuit20, whereby the trimming apparatuses10and10-2need smaller chip areas.

Meanwhile, in the comparison of the trimming apparatuses10and10-2against the trimming circuit30, the chip manufacturing cost turns out to be lower for the trimming apparatuses10and10-2, regardless of the bit width of the trimming object circuit.

This is because, regardless of the bit width of the trimming object, the trimming apparatuses10and10-2need fewer pads than the trimming circuit30, whereby the trimming apparatuses10and10-2need smaller chip areas. Furthermore, in the trimming apparatus10-2in particular, the reason is that the results of all trimming data patterns may be confirmed with a smaller number of clocks and hence the test time is shorter.

According to one aspect, it becomes possible to improve the manufacturing yield rate and reduce the chip area.