Semiconductor package without chip carrier and fabrication method thereof

A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure, and the chip is electrically connected to the electrical contacts; and an encapsulant for encapsulating the chip, the insulating structure and the electrical contacts, wherein bottom surfaces of the insulating structure, the electroplated die pad and the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant. A fabrication method of the semiconductor package is also provided.

FIELD OF THE INVENTION

The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package without a chip carrier and a fabrication method of the semiconductor package.

BACKGROUND OF THE INVENTION

Conventional Quad Flat Non-leaded (QFN) semiconductor package is structured as disclosed in U.S. Pat. No. 6,583,499 and is shown in FIG. 4, wherein a chip 41 is attached to a die pad 420 of a lead frame 42 and is electrically connected to leads 421 of the lead frame 42 via gold wires 43, and an encapsulant 44 is formed for encapsulating the chip 41, the lead frame 42 and the gold wires 43, with bottom surfaces of both the die pad 420 and the leads 421 being exposed from the encapsulant 44, such that the leads 421 can be implanted with solder balls or electrically connected to a printed circuit board (PCB) by solder paste.

The above QFN package advantageously does not have the leads extended out of the encapsulant and thus does not occupy a relatively larger area of the PCB unlike a Quad Flat Package (QFP). In view of the size and thickness requirements for the current semiconductor package, the QFN package has a satisfactorily small size, but it is still not considered thin enough or cannot be further reduced in thickness with the thickness of the lead frame (usually up to 200 μm) being taken into account.

Accordingly, to solve the above problem in terms of thickness, a semiconductor package without a lead frame is provided as disclosed in U.S. Pat. No. 5,830,800. This semiconductor package 5, as shown in FIG. 5, includes a plurality of electroplated pads 51 formed on a copper carrier (not shown), wherein the thickness of the electroplated pads 51 is only about 6 μm. A chip 52 is mounted on the copper carrier by silver paste, and is electrically connected to the electroplated pads 51 via a plurality of gold wires 53. An encapsulant 54 is formed for encapsulating the electroplated pads 51, the chip 52 and the gold wires 53. After forming the encapsulant 54, the copper carrier is removed by a chemical etching process, such that bottom surfaces of the electroplated pads 51 are exposed from the encapsulant 54. Finally, a plurality of solder balls 55 are implanted to the exposed electroplated pads 51.

Although the above semiconductor package 5 is thinner than a conventional lead-frame-based semiconductor package, only the electroplated pads 51 under the chip 52 serve as a heat dissipating medium for the chip 52 and thus make the total heat dissipating area of the semiconductor package 5 limited. Consequently, heat generated from the chip 52 during operation cannot be dissipated effectively only through the electroplated pads 51, such that electrical performance of the semiconductor package 5 may be adversely affected and even the chip 52 may be damaged.

To address the problem of heat dissipation for the chip, it is preferable to incorporate the die pad used in the QFN package into the above semiconductor package 5 by a plating technique to have the chip connected to the electroplated die pad such that the heat from the chip can be dissipated directly to an external environment through the electroplated die pad having a relatively larger heat dissipating area. This forms a semiconductor package 6 as shown in FIG. 6. However, if the surface area of the electroplated die pad 61 is larger than or equal to that of the chip 62 and if there are signal pads (not shown) or passive components 630 provided in a region, corresponding to the electroplated die pad 61, of a circuited board 63 to which the semiconductor package 6 is mounted, when the electroplated die pad 61 is bonded to the corresponding region of the circuit board 63 by solder paste 64, the solder paste 64 would cover and/or come into contact with the signal pads or the passive components 630, thereby resulting in short circuit.

In order to avoid short circuit, a strategy is to position the signal pads or the passive components 630 outside the region of the circuit board 63 covered by the solder paste 64. However, this undesirably alters the circuit layout of the circuit board, and thus increases the costs, sets a limitation on the circuit layout, as well as increases the design difficulty.

As an alternative, a semiconductor package 7 without altering the circuit layout of the circuit board is provided as shown in FIG. 7, wherein the electroplated die pad 71 is reduced to a size smaller than that of the chip 75, such that the solder paste 74 for bonding the electroplated die pad 71 to the circuit board 73 would not cover or come into contact with the signal pads or passive components 730 that are formed on the circuit board 73 and under the chip 75. However, if the thickness of the electroplated die pad 71 is smaller than 10 μm, space S between a bottom surface of the chip 75 and a bottom surface of the encapsulant 76 may become relatively small, for example, there may be a small distance (between 20 μm and 30 μm) left from the bottom surface of the chip 75 to the bottom surface of the encapsulant 76. As a result, a resin compound for forming the encapsulant 76 cannot be filled into the space S completely during a molding process of forming the encapsulant 76, such that voids 760 and/or recesses 761 are possibly formed, thereby degrading the reliability of the semiconductor package due to the voids 760 and/or adversely affecting the appearance of the semiconductor package due to the recesses 761.

As another alternative, if it is to alter the circuit layout of the circuit board, a semiconductor package 8 is provided as shown in FIG. 8, wherein signal pads or passive components 830 of the circuit board 83 are relocated to positions outside the region under the electroplated die pad 81, making the solder paste 84 not cover or come into contact with the signal pads or the passive components 830. Moreover, a ground ring 850 and a power ring 851 are additionally provided and are electrically connected to the chip 85. However, during a reflowing process for bonding the semiconductor package 8 to the circuit board 83 via the solder paste 84, since the ground ring 850 is located very close to the power ring 851, the solder paste 84 being reflowed may come into contact with the power ring 851 and ground the power ring 851 to the circuit board 83, thereby causing short circuit as indicated by S1in FIG. 8. Accordingly, even by altering the circuit layout of the circuit board 83, none of the foregoing semiconductor packages without chip carriers can be adapted to incorporate a power ring to improve the electrical performance thereof without having the aforementioned drawbacks.

Therefore, the problem to be solved here is to provide a semiconductor package without a chip carrier, which can effectively overcome or eliminate the foregoing drawbacks.

SUMMARY OF THE INVENTION

In light of the above drawbacks of the prior art, an objective of the present invention is to provide a semiconductor package without a chip carrier and a fabrication method thereof, so as not to affect a circuit layout of a circuit board to which the semiconductor package is mounted.

Another objective of the present invention is to provide a semiconductor package without a chip carrier and a fabrication method thereof, which can avoid voids being formed under a chip, thereby ensuring the reliability of the semiconductor package.

Still another objective of the present invention is to provide a semiconductor package without a chip carrier and a fabrication method thereof, which can ground a chip to a circuit board and avoid voids being formed under the chip, thereby ensuring the reliability of the semiconductor package.

A further objective of the present invention is to provide a semiconductor package without a chip carrier and a fabrication method thereof, which can provide a ground ring in a way without having the ground ring coming into contact with components of a circuit board, so as to prevent short circuit.

A further objective of the present invention is to provide a semiconductor package without a chip carrier and a fabrication method thereof, which can provide a ground ring and a power ring in a way without having the power ring grounded to a circuit board, so as to prevent short circuit.

In accordance with the above and other objectives, the present invention proposes a semiconductor package without a chip carrier, comprising: an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure; a plurality of electrical connection members for electrically connecting the chip to the electrical contacts; and an encapsulant for encapsulating the chip, the insulating structure, the electrical connection members and the electrical contacts, wherein a bottom surface of the insulating structure, a bottom surface of the electroplated die pad, and bottom surfaces of the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant.

The insulating structure may be made of thermoelastic resin or other insulating compounds, and preferably, the insulating structure is made of a material to provide elasticity for the insulating structure. With the insulating structure having elasticity, the effect of thermal stress from the encapsulant on the chip can be reduced, such that the semiconductor package is less likely to be warped or is subject to less degree of warpage.

The size of the electroplated die pad may be equal to or larger than the cross-sectional area of the opening, such that a peripheral portion of the electroplated die pad may cover a portion of the insulating structure.

By the above arrangement of the insulating structure and the electroplated die pad, there is no space present under the chip in the semiconductor package, thereby avoiding voids being formed under the chip. Moreover, the size of the electroplated die pad in the opening of the insulating structure can be desirably reduced, such that the electroplated die pad does not affect a circuit layout of a circuit board to which the semiconductor package is mounted but provides a heat dissipating path for the chip.

The present invention also proposes a fabrication method of a semiconductor package without a chip carrier, comprising the steps of: forming an insulating structure on a carrier, the insulating structure having an opening; forming a plurality of electrical contacts on the carrier and an electroplated die pad in the opening by an electroplating process, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure; attaching a chip to the electroplated die pad by a thermally conductive adhesive, so as to allow heat generated from the chip to be transmitted to the electroplated die pad through the thermally conductive adhesive; electrically connecting the chip to the electrical contacts by a plurality of electrical connection members; forming an encapsulant for encapsulating the chip, the insulating structure, the electrical contacts and the electrical connection members, wherein a bottom surface of the insulating structure, a bottom surface of the electroplated die pad, and bottom surfaces of the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant; and removing the carrier.

It should be understood that the above fabrication method is not limited to the use of a single chip but is also applicable to a batch-type manner of fabricating semiconductor packages through the use of a plurality of chips at one time. It should also be understood that the above fabrication method is not only for packaging a single chip with a larger size but also suitable for packaging a plurality of smaller chips in a batch-type manner. In the case of packaging a plurality of chips at one time, the fabrication method should include a step of performing a singulation process after the carrier is removed.

The insulating structure may be formed by screen-printing a material such as a resin compound on the carrier, or the insulating structure can be preformed and then attached to a predetermined position of the carrier.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of a semiconductor package without a chip carrier and a fabrication method thereof as proposed in the present invention are described as follows with reference toFIGS. 1,2A-2F and3A-3H. It should be noted that the drawings are simplified schematic diagrams only showing components or elements relevant to the present invention, and the layout of components or elements of the semiconductor package could be more complicated in the practical implementation.

FIG. 1shows a cross-sectional view of a semiconductor package1without a chip carrier according to a first embodiment of the present invention. The semiconductor package1comprises an insulating structure10having an opening100; an

electroplated die pad11coupled to the insulating structure10and exposed in the opening100; a chip12attached to the electroplated die pad11; a plurality of electrical contacts13,130,131provided around the insulating structure10; a plurality of electrical connection members such as gold wires14for electrically connecting the chip12to the electrical contacts13,130,131; and an encapsulant15for encapsulating the chip12, the insulating structure10, the electrical contacts13,130,131and the gold wires14.

The cross-sectional area of the opening100of the insulating structure10may be larger than, equal to or smaller than the size of the electroplated die pad11. As shown inFIG. 1, the cross-sectional area of the opening100is smaller than the size of the electroplated die pad11and larger than the size of the chip12, such that a portion of the insulating structure10is covered by a peripheral portion of the electroplated die pad11, and besides covering the insulating structure10, a bottom surface110of the electroplated die pad11is also exposed in the opening100. The insulating structure10is primarily made of an insulating material, preferably thermoelastic resin. With the insulating structure10having elasticity, the effect of thermal stress on the chip12due to mismatch in coefficient of thermal expansion (CTE) between different materials of components can be reduced, thereby increasing the reliability of the semiconductor package1. Moreover, a top surface101of the insulating structure10, besides being partly covered by the electroplated die pad11, is also formed with the electrical contacts such as a ground ring131and a power ring130thereon. The electrical contacts130,131formed on the top surface101of the insulating structure10are not exposed from a bottom surface150of the encapsulant15, such that the electrical contacts130,131do not affect a circuit layout of a circuit board (not shown) to which the semiconductor package1is mounted, as well as the electrical contact (ground ring)131does not come into contact with components of the circuit board and the electrical contact (power ring)130is prevented from being grounded to the circuit board, thereby avoiding short circuit and eliminating the drawbacks of the prior art. By providing the insulating structure10, the semiconductor package1can incorporate various electrical contacts such as the ground ring131and the power ring130, without having to alter the circuit layout of the circuit board and with the foregoing advantage of avoiding short circuit of the electrical contacts130,131.

In this embodiment, the size of the electroplated die pad11is equal to or larger than that of the chip12. Since the peripheral portion of the electroplated die pad11covers the portion of the insulating structure10, the actual size of the bottom surface110of the electroplated die pad11exposed from the bottom surface150of the encapsulant15is close to or slightly larger than the size of the chip12, thereby not affecting the circuit layout of the circuit board to which the semiconductor package1is bonded. The electroplated die pad11and the electrical contacts13,130,131are formed by an electroplating process. As the electroplated die pad11is larger than the chip12in size, there is no space present under the chip12, such that incomplete filling of the encapsulant15during a molding process of forming the encapsulant15and formation of voids are avoided in the semiconductor package1, making the semiconductor package1have desirable reliability.

The chip12is attached to a top surface111of the electroplated die pad11by a thermally conductive adhesive16such as silver paste or an adhesive mixed with thermally conductive particles, wherein the thermally conductive adhesive16fills the space between the chip12and the electroplated die pad11. Thus, heat generated from the chip12during operation can be transmitted to the electroplated die pad11through the thermally conductive adhesive16and then dissipated out of the semiconductor package1through the electroplated die pad11. Such heat dissipating path allows the heat from the chip12to be effectively dissipated and the electroplated die pad11larger in size than the chip12provides a large heat dissipating area, such that a satisfactory heat dissipating efficiency of the semiconductor package1can be ensured.

After the encapsulant15is formed, a bottom surface102of the insulating structure10, the bottom surface110of the electroplated die pad11, and bottom surfaces of the electrical contacts13are exposed from the encapsulant15and are flush with the bottom surface150of the encapsulant15. This arrangement prevents poor flatness and incomplete electrical connection between the semiconductor package1and the circuit board (not shown) when the electroplated die pad11and the electrical contacts13are bonded to corresponding regions of the circuit board via solder paste.

FIG. 2Ashows a cross-sectional view of a semiconductor package1awithout a chip carrier according to a second embodiment of the present invention, wherein like components in the first and second embodiments are designated with like reference numerals, and the detailed descriptions of these components are omitted in the second embodiment in order to make the disclosure of the present invention easier to be understood.

The semiconductor package1aof the second embodiment has a similar structure and achieves similar effects to the semiconductor package1of the first embodiment. Compared with the semiconductor package1, the semiconductor package1adiffers in having the opening100aof the insulating structure10asmaller than the chip12in size, but similarly has the size of the electroplated die pad11alarger than that of the chip12, such that a peripheral portion of the electroplated die pad11acovers more of the insulating structure10a. The electrical contacts such as a ground ring131aand a power ring130aare similarly formed on the insulating structure10a, but the actual size of the bottom surface110aof the electroplated die pad11aexposed from the bottom surface150of the encapsulant15is smaller than the size of the chip12. Accordingly, more space for the circuit layout of the circuit board (not shown) to which the semiconductor package1ais bonded can be provided, so as to increase the flexibility of the circuit layout of the circuit board.

FIG. 2Bshows a cross-sectional view of a semiconductor package1bwithout a chip carrier according to a third embodiment of the present invention, wherein like components in the first and third embodiments are designated with like reference numerals, and the detailed descriptions of these components are omitted in the third embodiment in order to make the disclosure of the present invention easier to be understood.

The semiconductor package1bof the third embodiment has a similar structure and achieves similar effects to the semiconductor package1of the first embodiment. Compared with the semiconductor package1, the semiconductor package1bdiffers in having the size of the opening100bof the insulating structure10bequal to the size of the electroplated die pad11band larger than the size of the chip12, but similarly has the size of the electroplated die pad11bequal to or larger than the size of the chip12, such that a peripheral portion of the electroplated die pad11bdoes not cover the insulating structure10b. The electrical contacts such as a ground ring131band a power ring130bare similarly provided on the insulating structure10b.

FIG. 2Cshows a cross-sectional view of a semiconductor package1cwithout a chip carrier according to a fourth embodiment of the present invention, wherein like components in the first and fourth embodiments are designated with like reference numerals, and the detailed descriptions of these components are omitted in the fourth embodiment in order to make the disclosure of the present invention easier to be understood.

The semiconductor package1cof the fourth embodiment has a similar structure and achieves similar effects to the semiconductor package1of the first embodiment. Compared with the semiconductor package1, the semiconductor package1cdiffers in increasing the size of the opening100cof the insulating structure10cto be larger than both the chip12and the electroplated die pad11c, but similarly has the electroplated die pad11clarge in size than the chip12, such that a peripheral portion of the electroplated die pad11cdoes not cover the insulating structure10c. Moreover in the semiconductor package1c, an electrical contact such as power ring130cis similarly formed on the insulating structure10c, but an electrical contact such as ground ring131cis not provided on the insulating structure10c.

FIG. 2Dshows a cross-sectional view of a semiconductor package1dwithout a chip carrier according to a fifth embodiment of the present invention, wherein like components in the second and fifth embodiments are designated with like reference numerals, and the detailed descriptions of these components are omitted in the fifth embodiment in order to make the disclosure of the present invention easier to be understood.

The semiconductor package1dof the fifth embodiment has a similar structure and achieves similar effects to the semiconductor package1aof the second embodiment. Compared with the semiconductor package1a, the semiconductor package1ddiffers in that the electrical contact131dprovided on the insulating structure10dincludes a ground ring but not a power ring, but the semiconductor package1dsimilarly has the size of the electroplated die pad11dlarger than the size of the chip12, such that the actual size of the bottom surface110dof the electroplated die pad11dexposed from the bottom surface150of the encapsulant15is much smaller than the size of the chip12. This arrangement similarly provides more space for the circuit layout of the circuit board (not shown) to which the semiconductor package1dis bonded, thereby increasing the flexibility of the circuit layout of the circuit board.

FIG. 2Eshows a cross-sectional view of a semiconductor package1ewithout a chip carrier according to a sixth embodiment of the present invention, wherein like components in the second and sixth embodiments are designated with like reference numerals, and the detailed descriptions of these components are omitted in the sixth embodiment in order to make the disclosure of the present invention easier to be understood.

The semiconductor package1eof the sixth embodiment has a similar structure and achieves similar effects to the semiconductor package1aof the second embodiment. Compared with the semiconductor package1a, the semiconductor package1ediffers in that there is no electrical contact provided on the insulating structure10eand the size of the insulating structure10eis approximately equal to the size of the electroplated die pad11e, but the semiconductor package1esimilarly has the size of the opening100eof the insulating structure10esmaller than the size of the chip12and has the size of the electroplated die pad1elarger than the size of the chip12. As a result, the actual size of the bottom surface10eof the electroplated die pad11eexposed from the bottom surface150of the encapsulant15is much smaller than the size of the chip12, such that more space for the circuit layout of the circuit board (not shown) to which the semiconductor package1eis bonded can be provided, thereby increasing the flexibility of the circuit layout of the circuit board.

FIG. 2Fshows a cross-sectional view of a semiconductor package1fwithout a chip carrier according to a seventh embodiment of the present invention, wherein like components in the second and seventh embodiments are designated with like reference numerals, and the detailed descriptions of these components are omitted in the seventh embodiment in order to make the disclosure of the present invention easier to be understood.

The semiconductor package1fof the seventh embodiment has a similar structure and achieves similar effects to the semiconductor package1aof the second embodiment. Compared with the semiconductor package1a, the semiconductor package1fdiffers in that the size of the electroplated die pad11fis smaller than the size of the chip12, but the semiconductor package1fsimilarly has the size of the insulating structure10flarger than the size of the electroplated die pad11fand has the opening100fof the insulating structure10fsmaller in size than the chip12. As such, the actual size of the bottom surface110fof the electroplated die pad11fexposed from the bottom surface150of the encapsulant15is much smaller than the size of the chip12, and the chip12is attached to both the electroplated die pad11fand the insulating structure10f. This arrangement provides more space for the circuit layout of the circuit board (not shown) to which the semiconductor package1fis bonded, so as to increase the flexibility of the circuit layout of the circuit board.

A fabrication method of the semiconductor package1according to the first embodiment of the present invention is illustrated as follows with reference toFIGS. 3A to 3H.

Referring toFIG. 3A, firstly, an insulating structure10made of an insulating material is printed on a carrier17by a screen-printing process or any other suitable conventional techniques, and the fabricated insulating structure10is formed with an opening100at a central position thereof, making the insulating structure10have a ring shape. The insulating structure10may be made of a polymer material such as epoxy resin or solder mask. Alternatively, the insulating structure10may be preformed, for example by cutting and shaping a polyimide resin tape to fabricate the insulating structure10with the opening100, and then the preformed insulating structure10is directly adhered to the carrier17. The carrier17is a metallic plate such as a copper plate to provide a current conduction path for a subsequent plating process.

Referring toFIG. 3B, secondly, a thin metal layer170such as a copper layer is formed on the carrier17by electroless plating, sputtering, vapor deposition or any other suitable conventional techniques, wherein the thickness of the thin metal layer170is about 0.05 μm to 0.2 μm. The thin metal layer170covers the insulating structure10. Then, as shown inFIG. 3C, a plating mask171such as a dry film is applied on the thin metal layer170by a suitable conventional technique, and is formed with openings predetermined for plating a plurality of electrical contacts (such as signal pads, a ground ring, a power ring, etc.) and a die pad. Subsequently, as shown inFIG. 3D, a metal layer is plated in each of the openings of the plating mask171. After removing the plating mask171and etching off the thin metal layer170under the plating mask171, the plating process for forming the plurality of electrical contacts13,130,131and the electroplated die pad11is completed, as shown inFIGS. 3E and 3F. The electrical contacts such as a ground ring131and a power ring130are provided on a top surface101of the insulating structure10, and the electrical contacts such as signal pads13are provided around the insulating structure10. The electroplated die pad11is formed in the opening100of the insulating structure10and covers a portion of the top surface101of the insulating structure10around the opening100, that is, the size of the electroplated die pad11is larger than the cross-sectional area of the opening100. The electrical contacts13,130,131can be thin pads each made of gold/palladium/nickel/palladium metal layers.

Next, as shown inFIG. 3G, a thermally conductive adhesive16such as silver paste is applied on a top surface111of the electroplated die pad11, and a chip12is attached to the top surface111of the electroplated die pad11via the thermally conductive adhesive16, wherein the size of the chip12is slightly smaller than the cross-sectional area of the opening100of the insulating structure10, such that heat generated from the chip12can be transmitted to the electroplated die pad11through the thermally conductive adhesive16and then dissipated to an external environment through the electroplated die pad11. Then, a wire-bonding process is performed to form a plurality of bonding wires such as gold wires14for electrically connecting the chip12to the electrical contacts13,130,131. The wire-bonding process is well known in the art and is not to be further detailed herein. Subsequently, a molding process is performed to form an encapsulant15on the carrier17to encapsulate the chip12, the electrical contacts13,130,131, the gold wires14, the insulating structure10and a portion of the electroplated die pad11, wherein the encapsulant15is made of a conventional material such as epoxy resin. The molding process is also well known in the art and is not to be further detailed herein.

Finally, as shown inFIG. 3H, after the encapsulant15is formed, the carrier17is removed from the encapsulant15by a chemical etching process, and subsequently, a singulation process is performed to form a singulated semiconductor package1without a chip carrier. As shown inFIG. 3H, a bottom surface102of the insulating structure10, a bottom surface110of the electroplated die pad11and bottom surfaces of the electrical contacts13are exposed from the encapsulant15and are flush with a bottom surface150of the encapsulant15, such that the semiconductor package1can be electrically connected to an external device such as a circuit board by solder paste (not shown), and the electrical contacts130,131are electrically isolated from the external device by the insulating structure10. It should be noted that the sequence of removing the carrier17and performing the singulation process can be altered or reversed.

In addition, compared with the semiconductor package1, the semiconductor packages1ato1fof the second to seventh embodiments of the present invention structurally differ primarily in the size of the opening of the insulating structure or the number of the electrical contacts, such that the above fabrication steps shown inFIGS. 3A to 3Hare also applicable for forming the semiconductor packages1ato1fwith the changes of the opening size or the number of the electrical contacts being taken into account, which are modifications understandable for a person skilled in the art, such that details for fabricating the semiconductor packages1ato1fare not further described herein.