Metal oxide semiconductor field effect transistor

A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer, and source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate. The germanium layer supplies carriers into the epitaxial layer so that short channel effects are reduced.

RELATED APPLICATIONS

This application is based on and claims priority to Korean Patent Application No. 10-2004-0117129, filed Dec. 30, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The present invention relates to a transistor, and more particularly, to a metal oxide semiconductor field effect transistor (MOSFET) and a method of fabricating the same.

2. Description of the Related Art

To achieve a higher integration of semiconductor devices, the size of the semiconductor devices needs to be reduced. Particularly, a critical dimension (CD), which generally equals a length of a gate electrode of a metal oxide semiconductor field effect transistor (MOSFET), needs to be reduced. However, a reduced CD results in a reduced channel length of a MOSFET, which causes various problems often referred to as short-channel effects.

Short channel effects deteriorate the characteristics of the MOSFET. For instance, as the channel length decreases, a threshold voltage decreases, a drain induced barrier lowering (DIBL) phenomenon occurs, and a leakage current between a drain and a source increases.

In order to prevent or alleviate the short channel effects, there is proposed a method for implanting impurities for threshold voltage adjustment over an entire surface of a channel. However, this method does not allow high integration of semiconductor devices.

Alternative methods for alleviating the short channel effects have also been proposed. For example, in order to adjust a vertical doping profile, a super steep retrograde (SSR) well or a pocket implantation may be formed. However, these methods do not prevent the decrease in the threshold voltage due to the short channel effects. For another example, halo ion implantation regions formed in lower portions of the source/drain regions may also be formed to reduce the short channel effects.

FIG. 1is a cross-sectional view of a semiconductor device illustrating a related art method for forming halo ion implantation regions.

Referring toFIG. 1, a gate oxide7and a gate electrode9are formed on a semiconductor substrate1. Semiconductor substrate1may comprise silicon. Semiconductor substrate1includes a low concentration impurity region3and a high concentration impurity region5acting as a source or drain region on each side of gate oxide7and gate electrode9. Oxide spacers11are formed on sidewalls of gate electrode9and gate oxide7.

To form halo ion implantation regions13, impurities are implanted into lower portions of the source/drain regions using gate electrode9and oxide spacers11as an ion implantation mask. Halo ion implantation regions13prevent the reduction in the threshold voltage and preserve the channel mobility.

However, a problem with the related art halo ion implantation method is that a junction capacitance may be increased and a junction depth is affected because the halo ion implantation regions are formed in source/drain regions as well as the semiconductor substrate region. Accordingly, when the integration density is high, the threshold voltage of devices with halo ion implantation regions is difficult to control.

SUMMARY

The present invention is directed to a metal oxide semiconductor field effect transistor (MOSFET) and a method for fabricating the same that substantially obviate one or more problems due to limitations and disadvantages of the related art. In particular, the present invention provides a MOSFET with reduced short channel effects and a method for fabricating the same.

A MOSFET consistent with embodiments of the present invention includes a semiconductor substrate; a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate; an epitaxial layer doped with a high concentration of impurities over the germanium layer; a gate structure on the epitaxial layer; and source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate.

A MOSFET also consistent with embodiments of the present invention includes an epitaxial layer doped with high concentration impurity ions as a channel in a semiconductor substrate; a germanium layer in the semiconductor substrate and under the epitaxial layer for supplying carriers into the epitaxial layer; a gate structure on the epitaxial layer; and source/drain regions with lightly doped drain (LDD) regions, the source/drain regions being spaced apart from each other by the epitaxial layer and the germanium layer.

Consistent with embodiments of the present invention, there is also provided a method for fabricating a MOSFET that includes forming a germanium layer with a predetermined thickness by implanting germanium ions into a semiconductor substrate; etching an overlying portion of the semiconductor substrate disposed over the germanium layer to expose the germanium layer; forming an epitaxial layer doped with high concentration impurities on the exposed germanium layer; forming a gate structure on the epitaxial layer; and forming source/drain regions in the semiconductor substrate, wherein the source/drain regions are spaced apart from each other by the germanium layer and the epitaxial layer.

The MOSFET consistent with embodiments of the present invention and as described below allows carriers in the germanium layer formed under a channel region to be supplied into the channel region so that short channel effects may be reduced. Also, as a result of the increase in the concentration in the channel region, a decrease in the threshold voltage of the MOSFET is prevented.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments are not limited to the scope of this invention, and can easily encompass added elements, variations, and deletions which fall within the scope of the present invention.

In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements.

FIGS. 2 to 7are cross-sectional views illustrating a metal oxide semiconductor field effect transistor (MOSFET) and a method for fabricating the same consistent with embodiments of the present invention.

InFIG. 2, an ion implantation process is performed to form a well in a semiconductor substrate100such as a silicon substrate or the like. The ion implantation for forming the well includes a punch through (P/T) implantation and a threshold (Vt) implantation. In detail, arrows111inFIG. 2denote the impurities implanted into semiconductor substrate100. Impurities111may comprise any impurities suitable for a desired semiconductor device.

Additional ion implantation processes may be performed using different implantation masks to form additional impurity regions. For example, if the ion implantation process shown inFIG. 2forms an n-type well region, an additional ion implantation process may be performed to form a p-type well region. Similarly, if the ion implantation process shown inFIG. 2forms a p-type well region, an additional ion implantation process may be performed to form an n-type well region.

Referring toFIG. 3, germanium (Ge) is implanted into semiconductor substrate100by an ion implantation process112to form a germanium layer120at a predetermined depth in semiconductor substrate100. As a result, semiconductor substrate100is divided by germanium layer120into an overlying portion110and an underlying portion still denoted as100.

Referring toFIG. 4, overlying portion110on germanium layer120is removed to expose an upper surface of germanium layer120. Overlying portion110may be removed by a wet etching process such as silicon etching, silicon oxide (SiO2) etching, silicon nitride (Si3N4) etching, aluminum (Al) etching, gallium arsenide (GaAs) etching, or the like.

Referring toFIG. 5, an epitaxial growth is performed to form an epitaxial layer130on germanium layer120. Epitaxial layer130may be doped with a high concentration of impurities. A process for doping impurity ions may be performed in advance before performing the epitaxial growth so that epitaxial layer130is doped with impurity ions of high concentration.

Referring toFIG. 6, a gate structure140is formed on epitaxial layer130. Gate structure140includes a gate insulating layer141and a gate conductive layer142stacked in sequence. A lightly doped drain (LDD) ion implantation is performed using gate structure140as a mask to form shallow source/drain extension regions151.

Referring toFIG. 7, after forming LDD regions151, gate spacers160are formed on sidewalls of gate structure140. An ion implantation is performed using gate structure140and gate spacers160as a mask to form deep source/drain regions152. Deep source/drain regions152and shallow source/drain regions151together form source/drain regions150. Source/drain regions150are spaced apart from each other by epitaxial layer130and germanium layer120.

Next, a conventional selective epitaxial growth is performed to form a selective epitaxial layer170on a surface of source/drain regions150on both sides of gate structure140. Selective epitaxial layer170prevents defects in a metal silicide layer to be formed later. Selective epitaxial layer170may have a thickness of about 300±100 Å.

Thus, a transistor including gate structure140, epitaxial layer130as the channel thereof, and source/drain regions150is formed. When voltages are applied to gate conductive layer142and source/drain regions150, carriers move through the channel and a current flows through the transistor.

Meanwhile, a number of carriers in germanium layer120may move into epitaxial layer130and thereby increase a carrier concentration in epitaxial layer130. As a result, the transistor may effectively prevent the threshold voltage decrease due to a reduction in the thickness of gate insulating layer141and also due to short channel effects as the semiconductor device is highly integrated. Referring toFIG. 8, to ensure that carriers in germanium layer120are effectively supplied to epitaxial layer130, epitaxial layer130and germanium layer120may be formed such that a ratio of a thickness a of epitaxial layer130to a thickness b of germanium layer120is a predetermined ratio, such as 1:2 to 1:4. For instance, referring toFIG. 3, when germanium layer120has a thickness of 200 Å, epitaxial layer130may be formed to have a thickness of about 100 Å.

In addition, referring toFIG. 8, which is an enlarged view of a portion A illustrated inFIG. 7, a ratio of a total thickness c of epitaxial layer130and germanium layer120to a critical dimension (CD) d, which is equal to the length of gate structure140may be in a range of 1:3 to 1:4. Also referring toFIG. 8, the critical dimension d may be equal to or greater than a horizontal length e of epitaxial layer130between source/drain regions150, but equal to or less less than a horizontal length f of germanium layer120between source/drain regions150.

Although not illustrated in the figures or described above, a halo ion implantation region and/or a pocket ion implantation region may be formed to further reduce short channel effects.