Analog-to-digital converter having amplifier and comparator stages

The first amplifier stage in the A/D converter receives an analog input signal and generates an analog residue signal and a digital output signal. Any other amplifier stage in the A/D converter receives the analog residue signal and the digital output signal from the previous amplifier stage, and generates another analog residue signal and another digital output signal. The comparator stage receives the analog residue signal and the digital output signal from the last amplifier stage, and generates one or more additional digital output signals. The digital output signals from all of the stages are used to generate the digitized equivalent of the original analog input signal. Because the comparator stage can be designed without an amplifier, the total number of amplifiers required to implement the A/D converter is reduced, as compared to prior art techniques.

BACKGROUND OF THE INVENTION 
This patent application is being filed concurrently with U.S. patent 
application Ser. No. 08/828,977, entitled "Amplifier for Use in 
Analog-to-Digital Signal Conversion," by Krishnaswamy Nagaraj (Attorney 
Docket No. "Nagaraj 16"), assigned to the same assignee and herein 
incorporated by reference. 
1. Field of the Invention 
The present invention is related to electrical circuits, and, in 
particular, to pipelined analog-to-digital converters. 
2. Description of the Related Art 
Pipelined analog-to-digital (A/D) converters are very commonly used in 
high-speed data converters. For example, a switched-capacitor algorithmic 
pipelined A/D converter is described in Lewis et al., "A 10-b 20-Msample/s 
Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, Vol. 
27, No. 3, pp. 351-358, March 1992, the teachings of which are 
incorporated herein by reference. Such a converter employs a pipeline of 
N-1 stages for an N-bit converter, where each stage comprises an analog 
arithmetic unit followed by a two-level decision circuit and the analog 
arithmetic unit operation is performed by using a switched-capacitor 
network and an operational amplifier. The first stage accepts the analog 
input and produces a pair of decision bits (containing the equivalent of 
1.5 binary bits of information) and an analog residue. These are passed on 
to the second stage, which treats the analog residue as its input and 
produces another 1.5 bits of information, as well as a new analog residue. 
This process continues until the residue reaches the last stage. The 
decision bits from all the stages represent a total of 1.5(N-1) bits of 
information. This means that redundancy exists within the bits of 
information. These are processed by a digital correction block that 
removes the redundancy and produces the final N-bit output. Any decision 
errors are corrected in this process. 
Nagaraj, "Efficient Circuit Configurations For Algorithmic 
Analog-To-Digital Converters," IEEE Transactions On Circuits Systems-II: 
Analog and Digital Signal Processing, Vol. 40, No. 2, December, 1993, pp. 
777-785 ("the Nagaraj article"), herein incorporated by reference, 
describes an A/D converter in which each amplifier is time-shared between 
two stages of the A/D converter, thereby reducing the total number of 
amplifiers used in such an A/D converter by a factor of two. For example, 
for a 10-bit pipelined A/D converter, five amplifiers are employed using 
the technique described in the Nagaraj article. 
Despite the time-sharing technique for reducing the number of amplifiers, 
it is nonetheless desirable to continue to come up with approaches in 
which the number of amplifiers for an A/D converter may be further 
reduced. This is largely because such amplifiers typically employ 
significant chip area (for solid-state implementations) and consume 
significant amounts of power, and therefore increase the cost of the A/D 
converter. Thus, a need exists for other techniques for reducing the 
number of amplifiers employed in an A/D converter, such as a pipelined A/D 
converter, without reducing the number of bits the A/D converter can 
process. 
Further aspects and advantages of this invention will become apparent from 
the detailed description which follows. 
SUMMARY OF THE INVENTION 
Embodiments of the present invention are directed to analog-to-digital 
converters having both one or more amplifier-based stages and a 
comparator-based stage. 
According to one embodiment, an A/D converter comprises an amplifier stage 
and a comparator stage, wherein the amplifier stage is adapted to receive 
an analog signal and to generate an analog residue signal and the 
comparator stage is adapted to receive the analog residue signal from the 
amplifier stage and to generate a digital output signal.

DETAILED DESCRIPTION 
FIG. 1 shows a block diagram of a pipelined analog-to-digital converter 
100, according to one embodiment of the present invention. AID converter 
100 is an N-stage converter that converts an analog input signal V.sub.IN 
into an (N+1)-bit digital output signal. In one implementation, A/D 
converter 100 has three different types of stages: initial stage 102 
(Stage 1), intermediate stages 104 (Stages 2 through N-1), and final stage 
106 (Stage N). 
Initial stage 102 receives the analog input signal V.sub.IN and generates 
two output signals: an analog residue signal V.sub.RES (1) and a two-bit 
(one-of-three) digital output signal D.sub.1. The j.sup.th intermediate 
stage 104 receives the two output signals generated by the previous stage 
(i.e., the analog residue signal V.sub.RES (j-1) and the two-bit digital 
output signal D.sub.j-1) and generates two output signals: an analog 
residue signal V.sub.RES (j) and a two-bit digital output signal D.sub.j. 
The final stage 106 receives the two output signals from the (N-1).sup.th 
stage (i.e., the analog residue signal V.sub.RES (N-1) and the two-bit 
digital output signal D.sub.N-1) and generates a two-bit digital output 
signal D.sub.N. 
For each analog input signal V.sub.IN, encoding logic 108 receives N 
two-bit digital output signals (D.sub.1, . . . , D.sub.N) from the N 
stages. Those skilled in the art will understand that each two-bit digital 
output signal corresponds to 1.5 bits of information. Encoding logic 108 
applies error-correction logic processing to the N two-bit digital output 
signals to remove redundancy and generate the (N+1)-bit digital equivalent 
to V.sub.IN. 
This approach to A/D conversion is described generally in the Nagaraj 
article. In alternative implementations, each stage of an A/D converter of 
the present invention may generate a digital output signal having other 
than two bits (i.e., one bit or more than two bits). 
A/D converter 100 may be operated in a pipelined manner. Consider the 
sequence of analog input signals (V.sub.INA, V.sub.INB, V.sub.INC, 
V.sub.IND, . . . ), where V.sub.INA is the first input, V.sub.INB is the 
second input, and so forth. A/D converter 100 may be used to digitize that 
sequence in the following steps: 
Step (1): Stage 1 receives V.sub.INA and generates V.sub.RES (1) and 
D.sub.1 for V.sub.INA. 
Step (2): While Stage 2 receives V.sub.RES (1) and D.sub.1 for V.sub.INA 
and generates V.sub.RES (2) and D.sub.2 for V.sub.INA, Stage 1 receives 
V.sub.INB and generates V.sub.RES (1) and D.sub.1 for V.sub.INB. 
Step (3): While Stage 3 receives V.sub.RES (2) and D.sub.2 for V.sub.INA 
and generates V.sub.RES (3) and D.sub.3 for V.sub.INA, and while Stage 2 
receives V.sub.RES (1) and D.sub.1 for V.sub.INB and generates V.sub.RES 
(2) and D.sub.2 for V.sub.INB, Stage 1 receives V.sub.INC and generates 
V.sub.RES (1) and D.sub.1 for V.sub.INC. 
Step (4): While Stage 4 receives V.sub.RES (3) and D.sub.3 for V.sub.INA 
and generates V.sub.RES (4) and D.sub.4 for V.sub.INA, and while Stage 3 
receives V.sub.RES (2) and D.sub.2 for V.sub.INB and generates V.sub.RES 
(3) and D.sub.3 for V.sub.INB, and while Stage 2 receives V.sub.RES (1) 
and D.sub.1 for V.sub.INC and generates V.sub.RES (2) and D.sub.2 for 
V.sub.INC, Stage 1 receives V.sub.IND and generates V.sub.RES (1) and 
D.sub.1 for V.sub.IND. 
Step (5): etc. 
In this way, AID converter 100 can efficiently convert a sequence of analog 
input signals V.sub.IN into a sequence of (N+1)-bit digital output 
signals. It will be understood, of course, that A/D converter 100 can be 
operated to convert analog input signals into digital output signals one 
at a time in a non-pipelined manner. 
FIG. 2 shows a schematic diagram of initial stage 102 of A/D converter 100 
of FIG. 1, according to one embodiment of the present invention. Initial 
stage 102 receives the analog input signal V.sub.IN and generates the 
first analog residue signal V.sub.RES (1) and the first two-bit digital 
output signal D.sub.1. Initial stage 102 may be a conventional 
sample-and-hold circuit. In one implementation, the analog residue signal 
V.sub.RES (1) generated by initial stage 102 is approximately equal to the 
original analog input signal V.sub.IN. 
Initial stage 102 has two clock phases of operation. During the first clock 
phase, switches 1 are closed and switches 2 are opened. During this first 
clock phase, capacitor C1 samples V.sub.IN. During the second clock phase, 
switches 1 are opened and switches 2 are closed. During this second clock 
phase, amplifier 204 generates V.sub.RES (1) based on the signal stored in 
capacitor C1. Within decision circuit 206, comparators 208 and 210 compare 
the residue signal V.sub.RES (1) to the reference signals +V.sub.R /4 and 
-V.sub.R /4, respectively, to generate the two-bit digital output signal 
D.sub.1. 
FIG. 3 shows a schematic diagram of each intermediate stage 104 of A/D 
converter 100 of FIG. 1, according to one embodiment of the present 
invention. In general, the j.sup.th intermediate stage 104 receives analog 
residue signal V.sub.RES (j-1) and digital output signal D.sub.j- 1from 
the previous stage of A/D converter 100 and generates analog residue 
signal V.sub.RES (j) and digital output signal D.sub.j. 
Like initial stage 102 of FIG. 2, intermediate stage 104 has two clock 
phases of operation. During the first clock phase, switches 1 are closed 
and switches 2 are opened. During this first clock phase, capacitors C1 
and C2 simultaneously sample V.sub.RES (j) as received from the previous 
stage. During the second clock phase, switches 1 are opened and switches 2 
are closed. During this second clock phase, a reference signal generated 
by reference generator 302 is applied to capacitor C1 and amplifier 304 
generates V.sub.RES (j) according to Equation (1) as follows: 
EQU V.sub.RES (j)=2 V.sub.RES (j-1)-D.sub.j-1 V.sub.R (1) 
where V.sub.R is the maximum allowable input voltage. Those skilled in the 
art will recognize that Equation (1) is typically applied in successive 
approximation A/D conversion. Reference generator 302 selects which 
reference signal to apply to capacitor C1 based on the two-bit digital 
value D.sub.j-1, as follows: 
If D.sub.j-1 =-1 (corresponding to the two-bit value (00)), then reference 
generator 302 selects -V.sub.R as the reference signal; 
If D.sub.j-1 =0 (corresponding to the two-bit value (01)), then reference 
generator 302 selects ground as the reference signal; and 
If D.sub.j-1 =+1 (corresponding to the two-bit value (11), then reference 
generator 302 selects +V.sub.R as the reference signal. 
Within decision circuit 306, comparators 308 and 310 compare the new 
residue signal V.sub.RES (j) to the reference signals +V.sub.R /4 and 
-V.sub.R /4, respectively, to generate the new two-bit digital output 
signal D.sub.j. 
FIG. 4 shows a schematic diagram of final stage 106 of A/D converter 100 of 
FIG. 1, according to one embodiment of the present invention. Final stage 
106 receives analog residue signal V.sub.RES (N-1) and digital output 
signal D.sub.N-1 from the second-to-last stage (i.e., Stage N-1 of FIG. 
1), and generates the final two-bit digital output signal D.sub.N. 
Referring again to intermediate stage 104 of FIG. 3, the two-bit digital 
output signal is generated by (a) generating V.sub.RES (j), according to 
Equation (1), as (2 V.sub.RES (j-1)-D.sub.j-1 V.sub.R) and then (b) 
comparing V.sub.RES (j) to +V.sub.R /4 and -V.sub.R /4. These operation 
are equivalent to comparing the signal (V.sub.RES (j-1)-D.sub.j-1 V.sub.R 
/2) to +V.sub.R /8 and -V.sub.R /8. This is what happens in final stage 
106 in FIG. 4. In particular: 
If D.sub.N-1 =-1, then reference generator 402 selects +5/8 V.sub.R as the 
reference signal for comparator 406 and reference generator 404 selects 
+3/8 V.sub.R as the reference signal for comparator 408; 
If D.sub.N-1 =0, then reference generator 402 selects +1/8 VR as the 
reference signal for comparator 406 and reference generator 404 selects 
-1/8 V.sub.R as the reference signal for comparator 408; and 
If D.sub.N-1 =+1, then reference generator 402 selects -3/8 V.sub.R as the 
reference signal for comparator 406 and reference generator 404 selects 
-5/8 V.sub.R as the reference signal for comparator 408. 
Comparators 406 and 408 compare the selected reference signals to V.sub.RES 
(N-1) in order to generate the two bits of D.sub.N. 
Since final stage 106 does not have to generate another analog residue 
signal since there are no more downstream stages, the design of final 
stage 106 does not rely on an amplifier. As such, A/D converter 100 of 
FIG. 1 can be designed with fewer amplifiers than even those A/D 
converters described in the Nagaraj article. For example, a 10-bit A/D 
converter having nine stages can be designed to have only four amplifiers: 
one time-shared amplifier for each of Stages 1 and 2, Stages 3 and 4, 
Stages 5 and 6, and Stages 7 and 8, with Stage 9 being implemented without 
an amplifier using the circuit of FIG. 4. This means that solid-state 
implementations of A/D converters of the present invention require less 
chip area and may therefore be less expensive to make. 
FIG. 5 shows a schematic diagram of circuit 500. In an alternative 
embodiment of the present invention, circuit 500 may be used to replace 
the last three stages of A/D converter 100 of FIG. 1 (i.e., Stages N-2, 
N-1, and N). For each original analog input signal V.sub.IN, circuit 500 
receives the analog residue signal V.sub.RES (N-3) and the two-bit digital 
output signal D.sub.N-3 from Stage N-3, and sequentially generates three 
two-bit digital output signals (i.e., D.sub.n-2, D.sub.N-1, and D.sub.N). 
Circuit 500 has three parallel sub-stages (Sub-Stages A, B, and C) that 
operate in analogous fashion. 
In particular, referring, for example, to Sub-Stage A, when switches A are 
closed and switch 502 is opened, capacitor CA samples V.sub.RES (N-3) as 
received from previous Stage N-3. When switches A are opened and switch 
502 is closed (for the first time), reference generator A applies a 
reference signal to capacitor CA and decision circuit 504 generates the 
two-bit digital output signal D.sub.N-2. In a preferred embodiment, each 
sub-stage in circuit 500 has two sets of capacitors, reference generators, 
and decision circuits, which generate the two bits of D.sub.N-2, analogous 
to the two sets of reference generators and decision circuits in FIG. 4. 
The two-bit digital output signal D.sub.N-2 is transmitted to both 
multiplexer 506 and register A, which temporarily stores D.sub.N-2. 
With switch 502 remaining closed, when reference generator A receives 
D.sub.N-2 from register A, it (potentially) changes the selected reference 
signal applied to capacitor CA and decision circuit 504 generates the next 
two-bit digital output signal D.sub.N-1. This processing is repeated one 
more time to generate the last two-bit digital output signal D.sub.N. Each 
time reference generator A applies a different reference signal to 
capacitor CA, the voltage applied to comparator 504 is altered. By 
selecting reference signals appropriately, the signal stored in capacitor 
CA can be altered to reflect the value of the previously resolved digital 
output signal. In general, for each successive digital output 
corresponding to a given input, the magnitudes of the reference voltages 
are decreased. 
In order to be used in an A/D converter that can operate in a pipelined 
manner, circuit 500 is designed to have three parallel sub-stages (i.e., 
Sub-Stages A, B, and C of FIG. 5). These three parallel sub-stages are 
used to process simultaneously the last three bits of three consecutive 
analog input signals (e.g., V.sub.INA, V.sub.INB, and V.sub.INC). In 
particular, circuit 500 can operate in a pipelined manner in the following 
steps: 
Step (1): With switches A closed and switches B and C opened, Sub-Stage A 
samples V.sub.RES (N-3) and D.sub.N-3 for the first analog input signal 
V.sub.INA and then generates the digital output signal D.sub.N-2 for 
V.sub.INA for V.sub.INA (after switches A are opened and switch 502 is 
closed). 
Step (2): With switches B closed and switches A and C opened, while 
Sub-Stage A generates D.sub.N-1 for V.sub.INA, Sub-Stage B samples 
V.sub.RES (N-3) and D.sub.N-3 for the second analog input signal V.sub.INB 
and then generates the digital output signal D.sub.N-2 for V.sub.INB. 
Step (3): With switches C closed and switches A and B opened, while 
Sub-Stage A generates D.sub.N for V.sub.INA and Sub-Stage B generates 
D.sub.N-1 for V.sub.INB, Sub-Stage C samples V.sub.RES (N-3) and D.sub.N-3 
for the third analog input signal V.sub.INC and then generates the digital 
output signal D.sub.N-2 for V.sub.INC. 
Step (4): With switches A closed and switches B and C opened, while 
Sub-Stage B generates D.sub.N for V.sub.INB and Sub-Stage C generates 
D.sub.N-1 for V.sub.INC, Sub-Stage A samples V.sub.RES (N-3) and D.sub.N-3 
for the fourth analog input signal V.sub.IND and then generates the 
digital output signal D.sub.N-2 for V.sub.IND. 
(5): etc. Mux 506 appropriately handles the distribution of the various 
digital output signals D.sub.N-2, D.sub.N-1, and D.sub.N corresponding to 
the various analog input signals V.sub.IN, for example, to encoding logic 
108 of FIG. 1. 
In this way, circuit 500 supports efficient pipelined A/D conversion of a 
stream of analog input signals (V.sub.INA, V.sub.INB, V.sub.INC, 
V.sub.IND, . . . ). It will understood that alternative embodiments of 
circuit 500 can be designed with different numbers of parallel sub-stages 
to replace different numbers of stages in A/D converter 100 of FIG. 1. For 
example, a circuit consisting of only Sub-Stages A and B of FIG. 5 could 
be used to replace only Stages N-1 and N of A/D converter 100 of FIG. 1. 
Circuit 500 of FIG. 5 can be used to replace yet another amplifier 
otherwise needed in A/D converter 100 of FIG. 1. For example, when circuit 
500 of FIG. 5 is used to replace Stages 7, 8, and 9 of a 10-bit A/D 
converter, the resulting A/D converter requires only three amplifiers: one 
for each of Stages 1 and 2, Stages 3 and 4, and Stages 5 and 6. In 
general, for every two additional parallel sub-stages built into a circuit 
like circuit 500, another amplifier can be omitted from a time-sharing 
implementation of an A/D converter, such as that discussed in the Nagaraj 
article. 
The number of stages of A/D converter 100 of FIG. 1 replaced by a circuit 
like circuit 500 of FIG. 5 and therefore the overall reduction in the 
number of amplifiers in A/D converter 100 may be limited by the accuracy 
requirements for the A/D converter. In general, the comparator-based 
scheme of circuit 500 of FIG. 5 and circuit 106 of FIG. 4 is less accurate 
(i.e., in resolving bits correctly) than the amplifier-based scheme of 
circuit 104 of FIG. 3. Thus, the accuracy requirements of the A/D 
converter will dictate (at least in part) the design of the last few 
stages of the A/D converter. 
Those skilled in the art will understand that the present invention may be 
applied to A/D converters that employ the time-sharing technology, such as 
that described in the Nagaraj article, as well as to A/D converters that 
do not employ time-sharing technology. 
Those skilled in the art will also understand that the present invention 
may be implemented as a single integrated circuit using solid-state 
technology or as a circuit having a plurality of discrete elements. 
It will be further understood that various changes in the details, 
materials, and arrangements of the parts which have been described and 
illustrated in order to explain the nature of this invention may be made 
by those skilled in the art without departing from the principle and scope 
of the invention as expressed in the following claims.