METHOD FOR MANUFACTURING A PHOTONIC CHIP

This method comprises:          before bonding a substrate to a layer of encapsulated semiconductor material in which a first part of an optical component is produced, producing indented pads inside a buried layer of silicon oxide, with each of these pads comprising an embedded face that extends parallel to an interface between the buried layer and the layer of encapsulated semiconductor material to a predetermined depth inside the buried layer, with each of the embedded faces being made of a material different from silicon oxide; then     thinning the buried layer in order to leave a residual silicon oxide layer on the layer of encapsulated semiconductor material, with this thinning comprising an operation involving thinning the buried layer, with this thinning stopping as soon as the embedded face of the pads is exposed.

The invention relates to a method for manufacturing a photonic chip and to a photonic chip manufactured using this method.

Photonic chips often comprise parts of optical components that are optically or capacitively coupled to each other through a thin layer of dielectric material, also referred to in this text as “thin dielectric layer”. The thickness of this thin dielectric layer is less than the thickness of the buried silicon oxide layer of standard SOI (Silicon-On-Insulator) substrates. Thus, in order to manufacture such a photonic chip from a standard SOI substrate, it has been proposed for the thin dielectric layer to be obtained by thinning the buried layer of a standard SOI substrate. Such a manufacturing method is disclosed, for example, in application US 2017/0237229. This method is advantageous in that it uses standard SOI substrates and therefore in that it can be easily implemented.

However, when the thin dielectric layer is obtained by thinning the buried layer of a standard SOI substrate, the precision with respect to the thickness of the thin dielectric layer is low. However, an error in the thickness of this thin dielectric layer changes the coupling between the two parts of the optical components and therefore the performance capabilities of the manufactured photonic chip.

It is therefore beneficial for a method to be proposed for manufacturing such a photonic chip that allows the use of a standard SOI substrate, while improving the precision with respect to the thickness of the thin dielectric layer.

Therefore, the aim of the invention is such a manufacturing method.

A further aim of the invention is a photonic chip manufactured using the aforementioned manufacturing method.

Throughout these figures, the same reference signs are used to designate the same elements.

Throughout the remainder of this description, the features and functions that are well known to a person skilled in the art are not described in detail.

FIG.1shows a photonic chip2comprising photonic components that guide and/or modulate the phase or the amplitude of an optical signal. Typically, the wavelength of the guided and/or modulated optical signal ranges between 1,250 nm and 1,590 nm.

In practice, such a photonic chip2comprises a plurality of optical components. For example, each of these optical components is selected from the group made up of the following optical components:a waveguide;a laser source;a phase and/or amplitude modulator;an optical filter;a mirror;an interface for connecting the photonic chip to an optical fibre.

More specifically, the photonic chip2comprises:at least two parts of optical components optically coupled to each other by means of an optical coupling; orat least two parts of optical components capacitively coupled to each other by means of a capacitive coupling.

InFIG.1, the parts of optical components coupled to each other by means of optical or capacitive coupling are denoted using numerical reference signs4and6, respectively.

By way of an illustration, parts of optical components optically coupled to each other are typically portions of waveguides that are close enough to each other so that at least 50%, and preferably more than 80%, of the power of the optical signal propagating in one of these two waveguides is transmitted to the other one of these two waveguides. For example, such optical coupling is adiabatic coupling as described in detail in the following article: B. Ben Bakir et al., “Hybrid Si/III-V lasers with adiabatic coupling”, 2011.

Parts of optical components capacitively coupled to each other are, for example, the two electrodes of a phase and/or amplitude modulator. Such a modulator is disclosed, for example, in application US 2017/0237229.

In order to achieve such optical or capacitive coupling, the two parts4and6of optical components are separated from each other by a thin dielectric layer8. A thin dielectric layer is a layer of dielectric material with a thickness of less than 250 nm and, typically, less than 150 nm. In the case of optical coupling, the thickness of the thin dielectric layer often ranges between 100 nm and 250 nm or between 100 nm and 200 nm. In the case of capacitive coupling, the thickness of the thin dielectric layer generally ranges between 5 nm and 50 nm and most often ranges between 5 nm and 30 nm or between 5 nm and 20 nm. In order to remain compatible with the use of a standard SOI substrate to manufacture the photonic chip2, the thin dielectric layer is a thin silicon oxide layer.

In order to simplifyFIG.1and the following figures, only a portion of the photonic chip2comprising the two parts4and6of optical components coupled together through the thin dielectric layer8is shown.

In this case, the description is provided in the particular case where the parts4and6are, respectively, the lower electrode and the upper electrode of a phase and/or amplitude modulator10of the optical signal. In this particular case, the parts4and6of optical components are capacitively coupled to each other. For example, the architecture of the modulator10is identical or similar to the architecture of the modulator described in application US 2017/0237229. Thus, hereafter, the precise architecture of the modulator10is not described in detail. However, everything described hereafter in this particular case also applies to the case where the parts4and6are coupled to each other by means of optical coupling.

The figures are oriented with respect to an orthogonal XYZ reference frame. The X and Y directions are horizontal. The X direction is perpendicular to the cutting plane. The Z direction is vertical. Throughout this text, terms such as “above”, “below”, “upper”, “lower” are defined relative to the Z direction.

The photonic chip2successively comprises, from the bottom to the top:—a substrate18made up of, from the bottom to the top, a support20and a layer22of dielectric material;a layer24of encapsulated semiconductor material, directly located on an upper face of the layer22of dielectric material;the thin layer8of silicon oxide; anda layer26, inside which the part6is encapsulated.

The thickness of the support20is typically greater than 200 μm or 400 μm. For example, the support20is made of silicon or of polycrystalline silicon.

The layer22is made of a dielectric material having optical and electrical properties similar or identical to the optical and electrical properties of silicon oxide. In this embodiment, the layer22is a silicon oxide layer. The thickness of the layer22is typically greater than 500 nm or 1 μm or more. Throughout this text, a dielectric material is a material with electrical conductivity at 20° C. that is less than 10-7 S/m and, preferably, less than 10-9 S/m or 10-15 S/m. Furthermore, its refractive index is lower than the refractive index of the encapsulated semiconductor material in the layer24.

The layer24contains a semiconductor material30, in which the part4encapsulated in a dielectric encapsulation material32is produced. As with the layer22, the dielectric encapsulation material32is a dielectric material with optical and electrical properties that are close or identical to those of silicon oxide. In this example, the material32is silicon oxide.

In this embodiment, the semiconductor material30is single-crystal silicon. Thus, the part4is made of single-crystal silicon. For example, the thickness of the single-crystal silicon in the layer24ranges between 100 nm and 800 nm and typically between 300 nm and 500 nm. Still in this embodiment, the layer24also comprises residues34of a masking layer36(FIG.5) used to structure the single-crystal silicon in order to produce the parts of optical components encapsulated inside the layer24. These residues34are located inside the layer24and each extend along the interface between the layers22and24. In this case, one such residue34separates the lower end of the part4from the layer22. The masking layer36and the residues34are made, in this embodiment, of a dielectric material different from silicon oxide. In this case, the layer36is made of silicon nitride.

The thickness of the residues34and of the layer36is typically three or five times less than the thickness of the single-crystal silicon30encapsulated in the layer24. For example, the thickness of the layer36is less than 100 nm.

The layer26comprises the part6of an optical component encapsulated inside a dielectric encapsulation material38. The material38can be the same as the material32or can be a different dielectric material from the material32. In this case, the material38is the same as the material32. Therefore, the material38is silicon oxide. The part6of an optical component is made of the same material as the part4of an optical component or of another semiconductor material, such as InP alloy, for example.

The thickness of the thin dielectric layer8is generally much less than the thickness of the buried layer of standard SOI substrates. Indeed, typically, the thickness of the buried silicon oxide layer of a standard SOI substrate is more than 500 nm or 1 μm and, generally, less than 10 μm or 20 μm. It is therefore necessary, when manufacturing the photonic chip2, for the buried layer of a standard SOI substrate to be thinned, while maintaining good precision with respect to its thickness in order to manufacture this thin dielectric layer8.

To this end, the photonic chip2comprises a plurality of pads evenly distributed over the entire horizontal face of the layer22. In order to simplify the figures, only one pad50is shown. In this case, the other pads of the photonic chip2are structurally identical to the pad50except that they are located at other sites on the upper face of the layer22. Under these conditions, hereafter, only the pad50is described in detail and numerical reference50is also used to collectively denote all these pads of the photonic chip2.

The pad50vertically extends from a face52flush with the upper face of the layer22, to a face54that is referred to in this text as “embedded face”. The face54is flush with the upper face of the thin dielectric layer8in this embodiment. Therefore, in this case it is located at the interface between the layers8and26. Thus, the pad50completely passes through the layers8and24.

The pad50is a straight cylinder with vertical generating lines. Its horizontal section is, for example, rectangular or circular. The surface area of the face54is typically greater than 1 μm 2 or 5 μm2and, generally, less than 50 μm2or 20 μm2. The density of the pads50in the photonic chip2is greater than 10% and, preferably, greater than or equal to 20%. Advantageously, the density of the pads50is also less than 40% or 30%. In this embodiment, the density of the pads50is equal to 20%. The density of the pads50is equal to the ratio C54/S22×100, where:C54is the total of the surface areas of the faces54of all the pads50of the photonic chip2;S22is the total surface area of the upper horizontal face of the layer22;the symbol “x” denotes the scalar multiplication operation.

The face54is made of a material that allows this face54to be used as a barrier layer when thinning a buried silicon oxide layer. Therefore, the face54is made of a material different from silicon oxide. For example, in this first embodiment, the face54is made of silicon nitride. More specifically, in this embodiment, the pad50comprises a core56made of silicon oxide and a thin film58made of silicon nitride that covers this core56.

The method for manufacturing the photonic chip2will now be described with reference to the flow chart ofFIG.2and with reference toFIGS.3to11.

Initially, during a step80, a standard SOI substrate82is provided (FIG.3). The substrate82comprises a stack of the following three layers immediately stacked on top of each other, from the bottom to the top:a support84;a buried layer86of silicon oxide; anda layer88of single-crystal silicon.

For example, the support84is made of silicon. Its thickness is conventionally greater than 400 μm or 700 μm.

The thickness of the buried layer86is conventionally greater than 500 nm or 1 μm and, generally, less than 10 μm or 20 μm.

In the particular case where the part4is an electrode of a phase modulator, during a step90, the layer88of single-crystal silicon undergoes localized doping one or more times at the site where the part4must be formed.

During a step91, the pads50are produced. In this case and to this end, during an operation92, a cavity94(FIG.4) is produced at the site of each pad50. The cavity94completely passes through the layer88of single-crystal silicon and has a bottom96that is located inside the layer86. The bottom96extends horizontally. It is located at a depth P96inside the layer86. The depth P96is measured from the upper surface of the layer86. The depth P96is less than, and typically two or five times less than, the thickness e86of the layer86. Preferably, the depth P96is less than 150 nm or 100 nm. In this case, the depth P96is equal to the thickness e8of the thin dielectric layer8and is therefore less than 30 nm.

In this case, the cavity94is, for example, hollowed out implementing one or more chemical etching techniques.

Selecting the shallow depth P96increases the precision over this depth. Indeed, if the precision of the etching of the layer86is plus or minus 5%, then, if the depth P96is equal to 100 nm, this corresponds to a maximum error of plus or minus 5 nm. Conversely, if the depth P96is much greater, for example, equal to 1 μm, then the maximum error is plus or minus 50 nm and therefore ten times greater. Thus, by limiting the depth P96, the precision is increased.

During an operation100, the masking layer36of dielectric material is deposited onto the entire upper surface. This layer36covers the entire upper surface of the layer88of single-crystal silicon. A portion of this layer36also covers the bottom96of the cavity94and forms the film58of the pad50.

The thickness of the layer36along the vertical walls of the cavity94is more difficult to control than the thickness of the layer36along the horizontal faces. Thus, in order to ensure that the core56is systematically isolated from the layer86by the film58, in this case, the thickness e36of the layer36is selected so as to be greater than the depth P96. Under these conditions, the core56, which is formed during the next step, is only located above the layer86.

During an operation104, the centre of the cavity94is filled with a material different from silicon in order to form the core56. In this case, the cavity94is filled, at this stage, with silicon oxide. For example, a silicon oxide layer that is thicker than the remaining depth of the cavity94is deposited. This silicon oxide layer is deposited, for example, onto the entire upper surface of the masking layer36implementing a chemical vapour deposition method such as the method known as PECVD (Plasma Enhanced Chemical Vapour Deposition).

Then, the upper surface is polished using the layer36as the barrier layer for this polishing. The state shown inFIG.6is then obtained. The production of the pad is then completed.

During a step110, the layer88of single-crystal silicon is structured in order to notably form the part4of an optical component.

To this end, during an operation112, the masking layer36is etched in order to leave residues34of this masking layer36only above the sites where part of an optical component must be produced. The state shown inFIG.7is then obtained on completion of the operation112.

Preferably, the total of the surface areas of the upper faces of the residues34obtained on completion of the operation112is greater than 10% and, preferably, greater than or equal to 20% of the horizontal surface area of the layer88. To this end, in this case, residues34are formed around each of the produced pads50in order to increase the remaining silicon nitride surface area and thus be able to use these residues34as a barrier layer during a subsequent step.

During an operation114, the layer88is etched through the etching mask formed by the residues34. For example, during this operation114, an etchant that dissolves the single-crystal silicon is applied to the upper face of the etching mask. This etchant can be liquid or gaseous.

On completion of the operation114, the state shown inFIG.8is obtained. Etching the layer88forms hollows at the sites where the single-crystal silicon has been removed. Step110of structuring the single-crystal silicon is then completed and the part4of an optical component is obtained.

During a step120, the structured layer of single-crystal silicon is encapsulated in the encapsulation material32in order to form the layer24of encapsulated single-crystal silicon. On completion of step120, the state shown inFIG.9is obtained. During step120, a layer of the encapsulation material32is deposited onto the entire upper surface of the etching mask. This layer of material32completely fills the hollows in the single-crystal silicon layer. To this end, the thickness of the layer of encapsulation material32is greater than the depth of the hollows to be filled. For example, the layer of encapsulation materials32is deposited using a chemical vapour deposition method. Subsequently, the encapsulation material32that is located outside the hollows is removed and the upper face of the layer24is prepared for bonding, for example, direct or molecular bonding. To this end, the upper face of the layer24is polished using a CMP (“Chemical-Mechanical Polishing”) method. This CMP method is stopped when the upper face of the residues34is exposed.

During a step124, the substrate18is bonded to the layer24. The state shown inFIG.10is then obtained. InFIG.10and in the following figure, the stack of layers84,86and24is turned over, so that the layer24is now at the bottom of this stack with its face bonded to the upper face of the layer22of the substrate18. For example, during step124, the layer24is bonded to the layer22by molecular bonding, i.e., without the addition of any external material.

During a step126, the substrate84is removed in order to expose the rear face of the buried layer86.

Then, during a step128, the buried layer86is thinned in order to leave only a residual layer129of silicon oxide deposited on the layer24. This residual layer129in this case forms the whole of the thin dielectric layer8. The state shown inFIG.11is then obtained.

During step128, thinning of the layer86is stopped by using the embedded faces54of the pads50as a barrier layer. In other words, thinning of the layer86is stopped as soon as the embedded faces54are exposed.

Since the embedded faces54are located at the depth P96inside the buried layer86, when thinning of the buried layer86is stopped, the thickness e129of the residual layer129is exactly equal to the depth P96. In this first embodiment, the thickness e129is equal to the thickness es of the thin dielectric layer8. Thus, using the pads50allows the thin dielectric layer8to be produced simply with a high degree of precision with respect to its thickness. For example, thinning the buried layer86is carried out using a CMP method.

During a step130, the part6of an optical component is produced on the thin dielectric layer8.

Then, during a step132, the produced part6of an optical component is encapsulated in the dielectric material38in order to obtain the layer26. For example, steps130and132are carried out as described in application US 2017/0237229.

On completion of steps130and132, the photonic chip2shown inFIG.1is obtained.

Then, additional steps are implemented in order to complete the manufacture of the photonic chip2. For example, in the particular case where the optical component is a modulator, a step of producing electric contacts on the parts4and6is carried out.

FIG.12shows a first alternative embodiment of the manufacturing method ofFIG.2. This first alternative embodiment is identical to the manufacturing method ofFIG.2except that a step150is introduced between steps128and130.

Step150is a step of depositing an additional dielectric layer152(FIG.13) directly onto the residual layer129obtained on completion of step128. The state obtained on completion of step150is shown inFIG.13. In this alternative embodiment, it is the stacking of the residual layer129and of the additional dielectric layer152that forms a thin dielectric layer154through which the parts4and6are coupled. The thin layer154is functionally identical to the thin layer8. However, in this alternative embodiment, the thin layer154is generally thicker than the thin layer8. Thus, this alternative embodiment is rather intended for producing parts4and6of optical components optically coupled through the thin layer154. The additional dielectric layer152is made of silicon oxide or another dielectric material such as silicon nitride. Depositing this additional dielectric layer152hardly degrades the precision with respect to the thickness of the thin layer154located between the parts4and6of optical components. Indeed, the precision with respect to the thickness of the dielectric layer152obtained by depositing dielectric material is much higher than the precision with respect to the thickness of a dielectric layer obtained by thinning a thicker dielectric layer. For example, in this alternative embodiment, the thickness of the residual layer129ranges between 30 nm and 50 nm and the thickness of the additional dielectric layer152ranges between 50 nm and 150 nm.

FIG.14shows a second alternative embodiment of the method ofFIG.2. This second alternative embodiment is identical to the method ofFIG.2except that steps91,110,128are replaced by steps160,162,164, respectively.

The step160is identical to the step91except that the operations100and104are replaced by the operations170and174, respectively.

The operation170is an operation for oxidizing the single-crystal silicon in order to form a layer176(FIG.15) of thermal oxide that covers the entire upper surface of the layer88of single-crystal silicon, as well as the portions of the vertical walls of the cavity94made of single-crystal silicon.

The layer176thus obtained does not cover the walls of the cavity94made of silicon oxide. Thus, the layer176does not cover the bottom96of the cavity94since this bottom is made of silicon oxide.

The operation174is an operation for filling the cavity94with a filler material different from silicon oxide. In this embodiment, the filler material is polycrystalline silicon. To this end, the procedure is as described for the operation104except that:instead of depositing silicon oxide, polycrystalline silicon is deposited; andpolishing the upper face uses the layer176as a barrier layer.

On completion of the step160, the state shown inFIG.15is obtained. InFIG.15, the produced pad is denoted using reference number180. This pad180, like the previously described pad50, comprises:an embedded face184that extends horizontally inside the layer86to the depth P96;a polycrystalline silicon core186; anda silicon oxide film188that covers the portion of the vertical faces of the core186located inside the silicon layer88.

The step162is identical to the step110except that it comprises, before the operation112, an operation192of depositing a masking layer194(FIG.16) on the upper faces of the pads180and the thermal oxide layer176. On completion of the operation194, the state shown inFIG.16is obtained.

For example, the masking layer194is identical to the masking layer36except that, in this alternative embodiment, this layer194additionally covers the upper faces of the pads180. Furthermore, during the operation192, the thickness of the deposited layer194can be less than the depth P96.

During the step112, it is the masking layer194that is etched in order to leave the residues34only above the sites of the layer88of single-crystal silicon that must not be etched. In this alternative embodiment, the upper face of each pad180is completely covered by a respective residue34in order to protect the polycrystalline silicon core186during the subsequent etching operation114. This simply allows a larger cumulative horizontal area of residue34to be obtained than with the method ofFIG.2, and therefore allows a barrier layer used during the step120to be obtained with a larger surface area.

The step164is identical to the step128except that it is the buried face184that is used as a barrier layer. On completion of the step164, the state shown inFIG.17is obtained. InFIG.17, the encapsulated layer of single-crystal silicon is denoted using reference number198and functionally corresponds to the layer24of the photonic chip2.

The following steps are identical to those described in the case ofFIG.2.

Chapter III: Alternative Embodiments

Alternative Embodiments of the Method ofFIG.2:

The cavities94can be filled with any other filler material different from silicon. For example, the cavities are filled with silicon nitride.

In the event that the filler material is different from silicon oxide or if the thickness of the masking layer36deposited onto the vertical walls of the cavity94is systematically enough to properly isolate the core56from the buried layer86, then the thickness e36of the layer36can be less than the depth P96.

Alternative Embodiments of the Method ofFIG.14:

The polysilicon used to fill the cavities94can be replaced by any material, different from silicon oxide, that can be polished using a CMP method while stopping on the thermal oxide layer. For example, polysilicon can be replaced by polygermanium or silicon nitride.

The masking layer194can be made of a material other than silicon nitride. For example, as an alternative embodiment, the masking layer194is made of titanium nitride or silicon oxide.

As an alternative embodiment, the masking layer194is completely removed after structuring the layer88of semiconductor material. For example, in this case, the masking layer is made of a photosensitive material such as a photosensitive resin.

Alternative Embodiments Common to all the Manufacturing Methods:

Other dielectric encapsulation materials can be used instead of silicon oxide to encapsulate the single-crystal silicon. However, preferably, the selected encapsulation material has similar optical and electrical properties to silicon oxide. Furthermore, preferably, the selected encapsulation material can be deposited using chemical vapour deposition and advantageously using a PECVD method. For example, as an alternative embodiment, the dielectric encapsulation material is tetraethyl orthosilicate, better known as TEOS, or silane.

Other shapes are possible for the pads50. For example, the horizontal cross-section of the pads50can assume any shape. The horizontal cross-sections of all the pads of the photonic chip2do not need to be identical. For example, as an alternative embodiment, a portion of the pads of the photonic chip has a rectangular cross-section, while another portion of the pads has a different horizontal cross-section, for example, circular.

In the case where the parts4and6of the optical components do not need to be doped, then the step90of doping these parts4and6is omitted.

Other embodiments of the operation114for etching the layer of single-crystal silicon are possible. For example, in order to structure, in the layer of single-crystal silicon, a part of an optical component that has multiple thicknesses, a multi-level etching operation can be implemented.

The step128of thinning the buried layer can be carried out by means other than chemical mechanical polishing. For example, as an alternative embodiment, the thinning is carried out using only chemical etching. In this latter case, the chemical etching is stopped as soon as components originating from the etching of the embedded faces54are detected in the bath of etchant used to carry out this chemical etching.

In another alternative embodiment, the step128of thinning the buried layer comprises a first and a second thinning operation. The first thinning operation is a thinning operation that stops on the embedded faces54of the pads50. This first thinning operation is identical to that described in the previous embodiments. This first thinning operation allows the residual layer129to be obtained. On completion of the first thinning operation, the second thinning operation is executed in order to thin the residual layer129. The first and second thinning operations differ from each other in terms of the chemistry and/or physics involved. For example, typically, the etchant used during the second thinning operation is different from the etchant used during the first thinning operation. In particular, during the second thinning operation, the etchant is a non-selective etchant that etches the silicon oxide and the embedded face54of the pads at the same rate. Conversely, during the first thinning operation, the etchant that is used does not need to etch the silicon oxide and the embedded faces54of the pads at the same rate. For example, the first thinning operation is used to obtain the residual layer129with a thickness ranging between 40 nm and 150 nm, then the second thinning operation is used to obtain a thin dielectric layer with a thickness of less than 30 nm.

The parts of optical components can be optically or capacitively coupled to each other through the thin dielectric layer. In the case of optical coupling, the desired thickness for the thin dielectric layer is generally greater than the desired thickness for the thin dielectric layer in the case of capacitive coupling.

The electric contacts and the electric interconnections can be produced in the substrate18or in an additional interconnection layer deposited onto the layer26.

The semiconductor material30that is used is not necessarily single-crystal silicon. For example, as an alternative embodiment, the semiconductor material is germanium or silicon carbide. In the case of germanium, the initial stack from which the manufacturing method begins is then known using the acronym GOI (“Germanium-On-Insulator”).

Several of the embodiments described herein can be combined with each other.

Chapter III: Advantages of the Described Embodiments

Using the embedded faces of the pads50,180as barrier faces when thinning the buried layer86increases the precision with respect to the thickness of the resulting residual layer129. Ultimately, this limits the dispersion of the features of the photonic chips manufactured according to the manufacturing methods described herein. Furthermore, this manufacturing method remains compatible with the use of standard SOI substrates, i.e., with the use of SOI substrates in which the thickness of the buried layer is greater than several hundred nanometers. Finally, the residual layer129is obtained without complete removal of the buried layer86after the substrate has been turned over. Such a complete removal of the buried layer is disadvantageous in that the complete removal of the buried layer86is then stopped by using the structured semiconductor material as a barrier layer. This leads to an increase in the roughness of the parts of optical components manufactured in the semiconductor material and therefore to a degradation of the performance capabilities of the manufactured photonic chip. Furthermore, the complete removal of the buried layer increases the consumption of silicon oxide. By avoiding the complete removal of the buried layer86, the methods described herein avoid these disadvantages.

The use of a thermal oxide layer176as a barrier layer when producing the pads180avoids an operation of depositing another material in order to form this barrier layer.

Depositing the masking layer194even above the pads180allows a masking layer to be obtained with a larger surface area than when the method ofFIG.2is implemented in order to produce the same photonic chip. In other words, the density of masking material on the face to be polished at the end of the encapsulation step is greater. The higher density of masking material on the face to be polished allows a flatter layer of encapsulated semiconductor material to be obtained, since the masking layer is also used as a barrier layer for the polishing of the layer of encapsulated semiconductor material. Ultimately, this improves the bonding of the substrate18to the layer198of encapsulated semiconductor material.

Using the same layer36to form the etching mask and the embedded faces84of the pads50simplifies the manufacturing method. In particular, this provides the possibility of using silicon oxide as a filler material for the cavities94.

The fact that the thickness e36of the masking layer36is greater than the predetermined depth P96allows the core56of the pad50to be made of silicon oxide, thus simplifying the manufacturing method.

The fact that the etching mask formed on the layer88of single-crystal silicon covers more than 10% of the upper horizontal surface of this layer88also allows this etching mask to be used as a barrier layer when polishing the layer24of encapsulated semiconductor material. This simplifies the manufacturing method.

The fact that the depth P96is less than 150 nm allows the precision to be increased with respect to the thickness of the resulting residual layer129. Indeed, the margin of error with respect to the depth P96is typically plus or minus 5% with conventional etching methods. The magnitude of the error with respect to the thickness of the residual layer129is therefore less than 7.5 nm. This is much more precise than when known methods are implemented in order to form such a residual silicon oxide layer.

The fact that the total of the buried surface areas54represents more than 10% of the surface area of the buried layer improves the flatness of the residual layer129.