Vertical Doping and Capacitive Balancing for Power Semiconductor Devices

Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described.

The Figures illustrate specific aspects of the power semiconductor devices and methods for making such devices. Together with the following description, the Figures demonstrate and explain the principles of the methods and structures produced through these methods. In the drawings, the thickness of layers and regions are exaggerated for clarity. The same reference numerals in different drawings represent the same element, and thus their descriptions will not be repeated. As the terms on, attached to, or coupled to are used herein, one object (e.g., a material, a layer, a substrate, etc.) can be on, attached to, or coupled to another object regardless of whether the one object is directly on, attached, or coupled to the other object or there are one or more intervening objects between the one object and the other object. Also, directions (e.g., above, below, top, bottom, side, up, down, under, over, upper, lower, horizontal, vertical, “x,” “y,” “z,” etc.), if provided, are relative and provided solely by way of example and for ease of illustration and discussion and not by way of limitation. In addition, where reference is made to a list of elements (e.g., elements a, b, c), such reference is intended to include any one of the listed elements by itself, any combination of less than all of the listed elements, and/or a combination of all of the listed elements.

DETAILED DESCRIPTION

The following description supplies specific details in order to provide a thorough understanding. Nevertheless, the skilled artisan would understand that the semiconductor devices and associated methods of making and using the devices can be implemented and used without employing these specific details. Indeed, the semiconductor devices and associated methods can be placed into practice by modifying the illustrated devices and methods and can be used in conjunction with any other apparatus and techniques conventionally used in the industry. For example, while description refers to trench MOSFET devices, it could be modified for other power semiconductor devices formed with trenches, such as Static Induction Transistor (SIT) devices, Static Induction Thyristor (SITh) devices, IGBT devices, BJT devices, JFET devices, Mos Controlled thyristor (MCT) devices, and Trench Barrier Schottky (TMBS).

Some embodiments of the power semiconductor devices and methods for making such devices are shown inFIGS. 1-14. The methods begin in some embodiments, as depicted inFIG. 1, when a semiconductor substrate105is first provided. Any substrate known in the art can be used in the invention. Suitable substrates include silicon wafers, epitaxial Si layers, bonded wafers such as used in silicon-on-insulator (SOI) technologies, and/or amorphous silicon layers, all of which may be doped or undoped. Also, any other semiconducting material used for electronic devices can be used, including Ge, SiGe, SiC, GaN, GaAs, InxGayAsz, AlxGayAsz, and/or any pure or compound semiconductors, such as III-V or II-VIs and their variants. In some embodiments, the substrate105can be heavily doped with any n-type dopant.

In some embodiments, the substrate105contains one or more epitaxial (“epi”) Si layers (individually or collectively depicted as epitaxial layer110) located on an upper surface thereof. The epitaxial layer(s)110can be provided using any process, including any epitaxial deposition process. In some embodiments, the epitaxial layer110can be configured so that it comprises a lower dopant concentration the upper portion of the epitaxial layer and a higher dopant concentration in the bottom portion of the epitaxial layer.

Some conventional power trench MOSFET devices contain a dopant profile that is consistent throughout the epitaxial layer so that the dopant concentration in the bottom portion of the epitaxial layer is the same as the concentration of the upper portion of the epitaxial layer. This conventional dopant profile is depicted by the red line X and blue line Y inFIG. 13, which shows the dopant concentration along the length of the epitaxial layer110with the upper surface of the epitaxial layer110shown on the left and the substrate on the right. As seen inFIG. 13, the dopant concentration in these conventional semiconductor devices is generally higher in the substrate region (section C) and then decreases to a relatively constant level in the epitaxial layer110(sections A and B).

FIG. 13also illustrates those embodiments where the epitaxial layer110comprises a lightly doped upper potion (near the upper surface of the epitaxial layer110). These embodiments are shown by the black line C inFIG. 13. Like the conventional devices, they contain a dopant concentration that is generally higher in the substrate105and then decreases to a constant level in bottom portion (B) of the epitaxial layer110. But unlike these conventional devices, the dopant concentration is reduced in the upper portion (A) near the upper surface of the epitaxial layer110.

In other embodiments, the semiconductor devices may include graded epitaxial layers for either the bottom portion (B) and upper epitaxial portion (A) that have higher doping near the substrate and lighter doping towards the surface. To achieve higher breakdown voltage devices or the desired electrical effect, multiple intermediate epitaxial layers maybe inserted between the bottom portion (B) and the top portion (A) that have a doping that is lower than the bottom portion (B) and heavier than the top portion (A). Each inserted epitaxial layer may progressively be lighter doping as it is grown towards the upper surface and may contain a graded doping profile that becomes lower towards the upper surface.

In some configurations of the semiconductor devices described herein, the dopant concentration in the substrate105can range from about 1e18 atoms/cm3to about 1e21 atoms/cm3and the dopant concentration in the bottom portion of the epitaxial layer can range from about 5e15 atoms/cm3to about 3e17 atoms/cm3. In other configurations, the dopant concentration in the substrate105can be about 5e19 atoms/cm3and the dopant concentration in the bottom portion of the epitaxial layer can be about 8e16 atoms/cm3.

In the embodiments illustrated inFIG. 13, the dopant concentration in the upper portion (A) can remain substantially constant. In these embodiments, the dopant concentration near the upper surface can range from about 1e13 atoms/cm3to about 1e16 atoms/cm3. In other embodiments, though, this lower dopant concentration can range from about 1e14 atoms/cm3to about 1e15a/cm3. In yet other embodiments, though, this lower dopant concentration can be about 1×1015atoms/cm3in the upper portion of the epitaxial layer110. In other configurations, though, the dopant concentration in the upper portion (A) need not remain substantially constant.

The thickness of this region of lower dopant concentration (i.e., the upper portion) depends on the well junction depth, the thermal exposure during the processing that can redistribute the doping, the reduction of the layer thickness due to oxidations and etches that consume or remove silicon from the surface, as well as the characteristics of the device that will be formed in the epitaxial layer (i.e., the shield gate trench MOSFET). In some embodiments, the thickness of this lower dopant region can range from about 1 micron to about 10 microns. In other embodiments, the thickness of this lower dopant region can range from about 3 microns to about 6 microns. In yet other embodiments, the thickness of this lower dopant region can be about 3 microns. This thickness compares to the thickness of the bottom portion (B) of the epitaxial layer110(where the dopant concentration is relatively constant) which can range from about 5 microns to about 50 microns and, in some embodiments can be about 9 microns.

The dopant concentration (of the black line Z) illustrated inFIG. 13can be obtained using any process that will provide the doping profile illustrated and described herein. In some embodiments, this doping profile can be obtained by growing the bottom portion of the epitaxial layer110on the substrate105using first epitaxial process that uses a higher dopant concentration in the atmosphere. Then, the upper portion of the epitaxial layer110can be grown over the bottom portion of layer using a second epitaxial process with a lower dopant concentration. Alternatively, all of the epi layers can be grown using an in situ process.

Next, as shown inFIG. 2, a first trench structure120(or trench) can be formed in the epitaxial layer110. The bottom of the first trench120can reach anywhere in epitaxial layer110or substrate105. The first trench structure120can be formed by any process yielding the desired structure. In some embodiments, a mask115can be formed on the upper surface of the epitaxial layer110. The mask115can be formed by first depositing a layer of the desired mask material and then patterning it using a photolithography and an etch process so the desired pattern for the mask115is formed. After the etching process used to create the trench120is complete, a mesa structure (or mesa)112has been formed between adjacent trenches120, as shown inFIG. 2.

The epitaxial layer110can then be etched by any process until the first trench120has reached the desired depth and width in the epitaxial layer110(or substrate105). The depth and width of the trench120, as well as the aspect ratio of the width to the depth, can be controlled so that so a later deposited oxide layer properly lines the trench sidewalls and bottom or fills in the trench and avoids the formation of voids. In some embodiments, the depth of the first trench structure120can range from about 0.1 to about 100 μm and the width can range from about 0.1 to about 50 μm. With such depths and widths, the aspect ratio of the trench can range from about 1:1 to about 1:50.

In some embodiments, the sidewalls of the trenches120are not perpendicular to the upper surface of the epitaxial layer110. Instead, the angles of the trench sidewall can range from about 90 degrees (a vertical sidewall) to about 60 degrees relative to the upper surface of the epitaxial layer110. The trench angle can be controlled so a later deposited oxide layer or any other material properly lines the trench sidewalls and/or fills in the trench and avoids the formation of voids. The mask115can next be removed using any process.

In some embodiments, as shown inFIG. 3, an oxide layer130(or other insulating or semi-insulating material) can then be formed on the trench sidewalls120. The oxide layer130can be formed by any process, including depositing an oxide material, growing an oxide layer or combination thereof on the trench120sidewalls. The thickness of the oxide layer130can be adjusted to any thickness needed on the trench120sidewalls required to support a desired device breakdown voltage or obtain a desired electric field profile. The deposition of the oxide material can be carried out using any known deposition process, including any chemical vapor deposition (CVD) processes, such as SACVD which can produce a highly conformal step coverage within the trench. If needed, a reflow process can be used to reflow the oxide material, which will help reduce voids or defects within the oxide layer130and densify the oxide material.

Then, as shown inFIG. 3, a conductive layer140can be deposited over the oxide layer130in the trenches120. The conductive layer140can comprise any conductive and/or semiconductive material known in the art including any metal, silicide, semiconducting material, doped polysilicon, or combinations thereof. In some embodiments, the conductive layer comprises doped or undoped polysilicon. This conductive layer140can be deposited by any known deposition process, including chemical vapor deposition processes (CVD, PECVD, LPCVD, etc.) or sputtering processes using the desired metal as the sputtering target.

The conductive layer140can be deposited so that it fills and overflows over the trenches120and the insulating layer130, as shown inFIG. 3. Then, as shown inFIG. 4, a shield electrode150(or shield150) can be formed from the conductive layer140using any process. In some embodiments, the shield150can be formed by removing the upper portion of the conductive layer140using any process, including any etchback process. The result of the removal process leaves a conductive layer (the shield150) overlying the oxide layer130on the bottom of the trench120and between the sidewall oxide layers130, as shown inFIG. 4.

An insulating layer145can then be formed in the trenches120. The insulating layer145can be deposited so that it fills and overflows over the trenches120, as shown inFIG. 5. The insulating layer145can be formed by any process. In some embodiments, the insulating layer can be formed by depositing an insulating material (such as an oxide) until it overflows the trenches120. The deposition of the oxide material can be carried out using any known deposition process, including any chemical vapor deposition (CVD) processes, such as SACVD which can produce a highly conformal step coverage within the trench. The insulating layer145is then etched back to remove the excess material above shield electrode150in the trenches120to form an interpoly dielectric (IPD) layer155, as shown inFIG. 6.

After the etch back process, an insulating layer (or gate oxide layer165) can be formed on the sidewalls of the trench120above the shield electrode150, as shown inFIG. 7. In these embodiments, a high quality material for the gate oxide layer can be formed by oxidizing the epitaxial layer110in an oxide-containing atmosphere until the desired thickness of the high-quality oxide layer has been grown. The high quality material in the gate oxide layer165can be used to improve the oxide integrity and thereby making the insulating layer a better insulator.

Next, a gate electrode (or gate)160of the MOSFET device can be formed in the trench120as shown inFIG. 7. The gate160can comprise any conductive and/or semiconductive material including any metal, silicide, semiconducting material, doped polysilicon, or combinations thereof. The conductive material for the gate160can be deposited by any known deposition process, including chemical vapor deposition processes (CVD, PECVD, LPCVD, etc.) or sputtering processes using the desired metal as the sputtering target. The conductive material can be deposited so that it fills and overflows over the trenches120after which the gate electrode160can be formed by removing the upper portion of the conductive layer using any process, including any etchback process. The result of the removal process leaves a conductive layer (the gate160, typically made of polysilicon) overlying the IPD layer155, as shown inFIG. 7.

In some embodiments, as shown inFIG. 8, the mesa region112can be doped with a p-type dopant so that a well region is formed in the epitaxial layer110between two trenches and along trench sidewalls120. The mesa doping process can be performed using any doping process which implants the p-type dopants to the desired depth. After the doping process, the p-type dopants can be further diffused by any known diffusion or drive-in process to the desired depth of the junction with the epitaxial layer110, known as the p-well junction (Pwell Xj)172.

An insulating layer (such as BPSG) can then be formed in the top of the trenches120above the gate electrode160. The insulating layer can be formed by any process, including by depositing an oxide material until it overflows the trenches120. The thickness of the insulating layer can be adjusted to any thickness needed to fill the top of the trenches120. The deposition of the insulating material can be carried out using any known deposition process, including any chemical vapor deposition (CVD) processes, such as SACVD which can produce a highly conformal step coverage within the trench. After the insulating layer has been deposited, an etchback process can be used to remove the excess material above the trenches120, thereby forming an interlevel dielectric (ILD) layer177in the upper part of the trench120.

Then, a n-type source region can be formed in an upper portion of the p-well region until it reaches the junction (Xj) depth175, as shown inFIG. 10. The source region175can be formed using the n-type dopants implanted and diffused from the surface of epitaxial region110. Then, a dimple180can be etched in the surface of epitaxial region110to form the source and body contacts, as shown inFIG. 11. A conductive material185can then be deposited and annealed to make ohmic contacts to the source and body regions, as shown inFIG. 12.

FIG. 13illustrates some embodiments of the shield gate semiconductor devices described herein. These semiconductor structures formed herein are illustrated in the top part ofFIG. 13with the upper surface of the epitaxial layer110(containing the p-well region) on the left side of the upper part ofFIG. 13and the lower part of the epitaxial layer110on the right side. The other parts of the shielded gate trench MOSFET structure are also illustrated in the top part ofFIG. 13.

These shield gate trench MOSFET devices can be operated until breakdown condition is achieved. The final dopant profile of the device after processing is measured along the cross-section of the device shown by the dashed line (which runs through the center of the mesa112of the semiconductor device in the top ofFIG. 14) and is displayed in the bottom graph ofFIG. 14. At that breakdown point, the electric profile of the device is also measured along the same cross-section and then displayed in the middle portion ofFIG. 14.

In the middle portion ofFIG. 14, the graph shows the electric field profile (shown by lines C and D) at the breakdown point of the devices described herein as compared to the electric field profile at breakdown of conventional devices (shown by lines A and B). As shown inFIG. 14, a minimum shield oxide thickness130is required for the desired break down voltage. The shield oxide thickness, mesa doping profile and mesa charge can determine the electric profile in the mesa12. The A lines inFIG. 14represent a doping profile and electric field profile of a some conventional devices having a single epitaxial layer represented by initial doping profile X inFIG. 13with the same doping concentration as the bottom epitaxial layer doping profile Z inFIG. 13of the devices described herein.

As seen in the Table at the top ofFIG. 14, for some conventional semiconductor device containing a single epitaxial layer, the mesa charge is too high and results in a breakdown voltage of only 38 volts because the critical electric field is reached in the silicon close to the top of the trench near p-well junction. The B lines inFIG. 14represent a doping profile and electric field profile of some conventional devices having a single epitaxial layer represented by doping profile Y inFIG. 13. For these conventional devices containing a single epitaxial layer, the mesa charge is optimized to achieve the highest breakdown with same shield oxide thickness as the semiconductor devices described herein. The specific on-resistance (RSP) is higher and an electric field profile that is not efficient resulting in a breakdown voltage of only 101V.

Compared to these drawbacks, the lightly doped region near the surface of the epitaxial layer110(as described herein) provides two benefits. First, as shown by line C, the lightly doped region contributes to reducing and suppressing the increase of the electric field near the p-well junction to achieve a breakdown voltage, thereby allowing an increase in epitaxial doping in the bottom epitaxial layer to reduce the on-resistance (Rdson). And second, as shown by line D, the lightly doped region near the epitaxial surface contributes to reducing and suppressing the increase of the electric field near the p-well junction and along the entire mesa depth between the trenches to achieve a breakdown voltage, thereby allowing an increase in epitaxial doping in the bottom epitaxial layer to reduce the on-resistances (Rdson).

As shown in the lower part ofFIG. 14, the graph shows the final dopant profile (shown by lines C and D) after processing of the devices described herein when compared to the dopant profile after processing of conventional devices (shown by lines A and B). This final dopant profile increases the doping in the bottom epitaxial layer to reduce on-resistance while preventing the silicon from reaching critical field near the P-well junction172, resulting in reduced breakdown voltage.

These methods of manufacturing and the power semiconductor devices formed have several useful features. First, they allow for higher mesa drift doping between the trenches120to achieve lower on-resistance performance while maintaining a high breakdown voltage. Second, the optimization of the shield oxide thickness130with the drift doping profile and mesa width between the trenches120can achieve a balanced condition that does not result in the mesa regions between adjacent trenches120to be fully depleted when a drain to source voltage (Vds) is applied that is equal to or lower than the rated device voltage.

Both the drift doping profile and the optimization of the balance condition result in a performance improvement during body diode recovery for peak reverse recovery current (Irrm), di/dt of the recovery current during the time it takes the drain current to go from Irrm to 25% of Irrm (tb), drain voltage overshoot, and recovery losses. One factor contributing to the performance improvement and minimizing the time from the point the current crosses zero and decreases to Irrm (ta), as shown inFIG. 16, is achieving a level of hole carrier injection below—or as close as possible to—the background concentration and low minority carrier lifetime in the mesa region. Thus, when the current crosses zero, the semiconductor device is the ta phase for a shorter time and Irrm and Qrr can be reduced. A second contributing factor in charge-balanced semiconductor devices is that when the mesa becomes fully depleted, the depletion edge cannot expand anymore since it reaches the bottom of the trench or drift region below the trench. At that point, an abrupt change in the dv/dt can occur that can drive the device into avalanche. But this situation can be avoided if the applied voltage is lower than the voltage at which the mesa is full depleted, as noted in the capacitance curve for the conventional devices inFIG. 15. In the semiconductor devices described herein, though, the mesa does not fully deplete up to the 100 volt rating of the device.

The body diode recovery for some conventional semiconductor devices (on the left) compared to the semiconductor devices described herein (on the right) is shown inFIG. 16. These conventional devices have a single epi doping profile of 1.26e16 atoms/cm3, which is inferior to the body diode recovery of the semiconductor devices described herein. The conventional body diode recovery (in the left ofFIG. 16) has higher peak reverse current (Irrm) labeled as IdsMOSD inFIG. 16, reverse recovery charge (Qrr), snappy recovery (low ratio of tb/ta), and device is driven into avalanche shown by VsdMOSD inFIG. 16posing a risk for device failure. The poor body diode recovery for these conventional devices results from a minority carrier hole concentration level during forward body diode conduction that is higher than the drift doping level labeled as Vsd inFIG. 17, as shown by the profile labeled Vsd.

At the same time, a slower recombination of minority carriers below background doping results from a higher minority carrier concentration dependent lifetime of the lower drift doping that increases the time to onset of reverse blocking. This situation occurs when the minority carrier concentration level falls below the mesa drift doping near the p-well junction, as shown inFIG. 17in the carrier profile labeled “start reverse blocking.” Thus, to and Irrm become too large in these conventional devices and the recovery current tb does not transition to mostly capacitive shield charging current labeled IsMOSD inFIG. 16. The lower output capacitance (Coss) at a Vdd of 50V, as shown inFIG. 15, and the depletion of the mesa region occurring at a voltage less than the applied Vdd causes a secondary fast drain dv/dt, thereby driving these conventional devices into avalanche during tb, as shown inFIG. 16.

The improved body diode recovery performance of the devices described herein is due, in part, to an injected hole carrier concentration that is below the background labeled as Vsd inFIG. 17, a slower rate of voltage rise (dv/dt), optimization of shield capacitance and balance condition to prevent full mesa depletion at voltages less than the applied voltage, and lower minority carrier lifetime due to enabling the use of higher concentration doping in the lower drift region or regions. The body diode recovery shown on the right inFIG. 16with a starting epitaxial doping profile Z inFIG. 13and finished processed doping profile D inFIG. 14is superior to the body diode recovery of the conventional device inFIG. 16. The body diode recovery shown on the right inFIG. 16has lower Irrm labeled as IdsMOSD inFIG. 16, lower Qrr, softer recovery (high ratio of tb/ta), and lower drain overshoot voltage labeled as VsdMOSD inFIG. 16. This improved body diode recovery results from a minority carrier hole concentration level during forward body diode conduction that is lower than the drift doping level, as shown in theFIG. 17profile labeled Vsd. A faster recombination of minority carriers below the background doping resulting from a lower minority carrier concentration dependent lifetime of lower drift doping decreases the time to the onset of reverse blocking, as shown in theFIG. 17carrier profile labeled “start reverse blocking.” Thus, to and Irrm become lower for the devices described herein. The recovery current during tb can transition to mostly capacitive shield charging current labeled IsMOSD inFIG. 16and a higher Coss at Vdd of 50V, as shown inFIG. 15, and a mesa region that is not fully depleted at voltages less than the applied Vdd, thereby resulting in a slower dv/dt that can be controlled by the charging of the Coss and a low Vds overshoot during tb, as shown inFIG. 16.

It is understood that all material types provided herein are for illustrative purposes only. Accordingly, while specific dopants are names for the n-type and p-type dopants, any other known n-type and p-type dopants (or combination of such dopants) can be used in the semiconductor devices. As well, although the devices of the invention are described with reference to a particular type of conductivity (P or N), the devices can be configured with a combination of the same type of dopant or can be configured with the opposite type of conductivity (N or P, respectively) by appropriate modifications.

In some embodiments, the application relates to a shielded gate MOSFET device comprising a semiconductor substrate; an epitaxial layer on the substrate, the epitaxial layer containing a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; a trench in the epitaxial layer; an insulating layer on the bottom and sidewalls of the trench; a conductive shield on the insulating layer; an interlevel dielectric layer on the conductive shield; a gate on the interlevel dielectric layer; an insulation cap on the gate; and a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type.

In addition to any previously indicated modification, numerous other variations and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of this description, and appended claims are intended to cover such modifications and arrangements. For example, the upper portion of the epitaxial layer can extend below the well region by about 0.5 microns, the upper portion of the epitaxial layer can extend below the well region by more than about 0.5 microns, the upper portion dopant concentration can decrease towards the surface, the bottom portion dopant concentration can decrease towards the surface, the bottom portion dopant concentration can be higher than the upper portion dopant concentration and both can have decreasing concentration towards the surface, the intermediate portions can be inserted between the lower portion and the upper portion and some (or all) can have successively increasing dopant levels toward the substrate, the second concentration in the upper portion of the epitaxial layer reduces and flattens the electric field near the junction with well region, a higher mesa drift doping can be created between the trenches and achieve a lower on-resistance performance while maintaining a high breakdown voltage, the mesa region is not full depleted at about 50% rated drain voltage, the mesa region is not full depleted at about 80% rated drain voltage, the mesa region is not full depleted at the rated drain voltage, and/or the minority carrier concentration level during body diode conduction is lower than the bottom portion dopant concentration.