Generic bit error rate analyzer for use with serial data links

Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

TECHNICAL FIELD

This disclosure related to a generic bit error rate analyzer that is usable in both on-chip and off-chip environments, and is capable of analyzing the bit error rate of multiple different types of serial data links.

BACKGROUND

High speed serial transceivers undergo bit error rate (BER) testing during characterization. The BER is the rate of occurrence of erroneous bits in data transmission or reception. This testing is performed using a BER analyzer, which can be located on-chip or off-chip.

An example of an off-chip BER analyzer10is now described with reference toFIG. 1A. The BER analyzer10includes a test data generator12and a BER analysis circuit13. The device under test16includes a receiver17and a transmitter18. A physical PHY receive channel14couples the test data generator12to the receiver17, and a physical PHY transmit channel15couples the BER analysis circuit13to the transmitter18.

The test data generator12generates a psuedo-random binary sequence for use as test data and transmits it to the device under test16over the PHY receive channel14. The device under test16then transmits the test data back to the test apparatus11, via the transmitter18and over the PHY transmit channel15. The BER analysis circuit13receives the test data and determines the BER thereof by comparing the received test data to expected check data.

This off-chip BER analyzer10has a variety of drawbacks, however. For example, errors in the PHY receive channel14can affect the determined BER of the PHY receive channel14. In addition, this off-chip BER analyzer10is unable to test a single channel protocol, such as USB 2.0. Furthermore, such off-chip BER analyzers10can be prohibitively costly. In addition, the BER testing of a variable burst-to-burst latency protocol (e.g. MIPI, MPHY, etc) with such off-chip BER analyzers10is not possible. In addition, in some cases, loopback between the PHY receive channel14and PHY transmit channel15may not be feasible, as these interfaces may not be pin to pin mapped.

The cost of an on-chip BER analyzer20, such as that shown inFIG. 1B, may be less than that of an off-chip BER analyzer. Here, the device under test is an integrated circuit chip22, and includes two separate and distinct physical channels, PHY123and PHY225, that use different voltage levels and protocols in some cases. The channel PHY123is coupled to a first BER analyzer circuit24, while the channel PHY225is coupled to a second BER analyzer circuit26.

In operation, a test data generator21generates a psuedo-random binary sequence for use as test data and transmits it to the BER analyzer20, over the channels PHY123and PHY225, to BER analyzers24and26. The BER analyzer circuits24and26determine the bit error rates of the channels PHY123and PHY225.

As mentioned, this on-chip BER analyzer20is cheaper than an off-chip BER analyzer. However, it has drawbacks as well. For example, separate BER analyzer circuits24and26are needed for each channel PHY123and PHY225. This means that this on-chip BER analyzer20increases the area overhead for applications in which multiple PHY channels are to be tested.

Consequently, further development in the area of bit error rate analyzers is needed.

SUMMARY

Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

In some cases, a psuedorandom binary sequence generator may be configured to generate the check data and to send the check data to the bit error rate determination circuit.

In other cases, a memory may be configured to store the check data and send the check data to the bit error rate determination circuit.

An interface block may be configured to receive the check data, over a physical interface, and to send the check data to the memory. In some cases, the interface block may instead receive the check data, over a system bus, and to send the check data to the memory.

The programmable interface may be configurable to receive the test data at a plurality of data rates. The programmable interface may include a programmable state machine, and the interface with the physical interface can be customized by changing values of registers to meet specifications of a desired high speed serial PHY. This makes the system adaptable to different high speed serial standards.

The programmable interface may cooperate with the voltage translator to receive the test data from the device under test, over the physical interface, using one of the plurality of I/O standards. The programmable interface may be capable of communication using each of the plurality of I/O standards. In some cases, the programmable case may communicate using one I/O standard.

A controller may be configured to control operation of at least one of the bit error rate determination circuit and the programmable interface. The programmable interface may be configurable to receive the test data at a plurality of data rates, and may include at least one register configured to store configuration bits determining the data rate at which the programmable interface is configured to receive the test data. The programmable interface may be configurable to communicate with any high speed serial link physical interface by changing the values of its registers to meet the specifications of any high speed serial physical interface. The controller may be configured to set the configuration bits of the at least one register, or each register, of the programmable interface.

An interface block may be configured to receive user configuration settings for at least one of the programmable interface and the bit error rate determination circuit, over a physical interface, from an electronic device, and to send the user configuration settings to the controller.

Another aspect is directed to a system on a chip including a plurality of devices, with a multiplexer configured to receive, as input, test data from a selected one of the plurality of devices. A bit error analysis circuit includes a voltage translator coupled to receive test data from the multiplexer, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator and send the test data to the bit error rate determination circuit. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of transmission of the test data over the physical interface based upon a comparison of the test data to check data. An interface block configured to receive the check data, over a physical interface.

A method aspect includes testing a device with a test apparatus. The method performs this testing by receiving test data from the device, over a physical interface, using one of a plurality of input output (IO) standards, using a voltage translator capable of communication using each of the plurality of IO standards. The test data is received from the voltage translator at a programmable interface and is sent the test data to a bit error rate determination circuit. The test data is received at a bit error rate determination circuit and a bit error rate of received test data over the physical interface is determined based upon a comparison of the test data to check data.

The test apparatus may be configured for the testing by writing configuration bits to registers inside the programmable interface to configure the programmable interface to use the one of the plurality of IO standards so as to enable cooperation with the voltage translator to receive the test data over the physical interface. Stated another way, the test apparatus may be configured for the testing by writing configuration bits to registers inside the programmable interface to configure the programmable interface to interface it with parallel interface of any high speed serial link PHY. The voltage translator may be configured to communicate using the one of the plurality of I/O standards.

Testing may include enabling the bit error rate determination circuit, and then by the test apparatus by receiving the check data at an interface block, over a physical interface, using an interface block. In some cases, the device may receive the check data from the interface block at a memory, may store the check data in the memory, and may send the check data to the bit error rate determination circuit. In some cases, the check data may be generated using a psuedorandom binary sequence generator, and sending the check data to the bit error rate determination circuit.

DETAILED DESCRIPTION

One or more embodiments of the present disclosure will be described below. These described embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description, some features of an actual implementation may not be described in the specification. When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Like numbers refer to like elements throughout, and prime notation is used to indicate alternative structures in similar embodiments.

With reference toFIG. 2, an off-chip bit error rate (BER) analyzer50for a physical layer PHY51of a device under test is now described. This BER analyzer50is, in this application, external to the PHY51, and is not incorporated within the same chip as the device under test. The BER analyzer50includes a voltage translator53receiving test data from the PHY51over a parallel interface52. The voltage translator53sends the received test data to programmable interface54.

The programmable interface54sends the received test data to the BER determination circuitry55. The BER determination circuitry55receives known good check data from a psuedo-random binary sequence generator56, and compares the received test data to the check data to determine the bit error rate. This is performed in real time, with update results being stored in memory registers or registers together with statistics of these comparisons. The determined bit error rate can be saved to any suitable form of memory, such as block ram (BRAM).

It should be appreciated that this off-chip BER analyzer50is generic and may work with any type of physical interface or physical layer PHY. The voltage translator53is configurable to work with any of a variety of physical interfaces physical layers PHY, and serves to translate the received voltages of the test data to suitable device voltages for receipt by the programmable interface54for use in testing. The programmable interface54is configurable to operate using any type of interface protocol, such as USB 2.0, USB 3.0, or ethernet.

The programmable interface54, as shown inFIG. 3, is comprised of a programmable state machine60for enabling the use of any interface protocol as described above, and registers1through N (shown as registers61and62) contain settable configuration bits for determining how the state machine60operates. For example, the configuration bits may configure the state machine60, and thus the programmable interface54, for using any communication protocol.

A controller59is coupled to the programmable interface54, BER determination circuitry55, and PRBS generator56, and serves to configure, control, activate, and deactivate these components. The controller59receives input from the interface block57, which itself is configured to communicate with an external device58over a suitable interface, such as USB or ethernet. The external device58may be a computer, or any suitable electronic device. The interface block57may receive instructions from the external device58, such as on how to configure the various components of the BER analyzer50, what kind of physical interface is to be used by the PHY51, what communication protocol is to be used, what kind of check data is to be used, etc. These configuration, control, activation, and deactivation functions may be performed in an initial set-up phase for the BER analyzer50, or may be performed on the fly.

The interface block57can not only pass information and commands from the external device58to the controller59, but can also pass information back from the controller59to the external device58. This information from the controller59can include information received from the programmable interface54, BER determination circuitry55, and/or PRBS generator56, such as the current configurations thereof, and such as the bit error rate.

In the case where an initial configuration phase for the BER analyzer50is performed, it includes, not necessarily in this order, (1) using the controller59to configure the PRBS generator56to generate a desired PRBS for use as check data (or to write a desired PRBS sequence into a memory, as will be explained below), (2) setting the registers61,62within the programmable interface54to use a desired communications protocol, and (3) configuring the voltage translator53to receive as input the voltages of the transmitted test data using the desired communications protocol. Then, the BER determination circuitry55is enabled, and the test data is transmitted to the PHY51. Operation thereafter proceeds as described above, with the BER determination circuitry55comparing the received test data to received check data to determine the bit error rate of the BER analyzer50.

Other configurations will now be discussed. As can be seen in the configuration of the BER analyzer50′ shown inFIG. 4, the BER analyzer50′ may be located on the same integrated circuit chip49as the devices it tests, and the interface block57may be connected to the system bus70of the integrated circuit chip49. Other devices connected over the system bus70may, for example, be a processor71, memory72, and other peripheral73(for example, a MAC interface for ethernet communications, or a USB interface). The processor71may serve the same function as the external device58described above, and may thus send or receive data to the interface block57. As can also be seen in this configuration, here, a memory48is used in place of a PRBS generator, and the memory stores the check data. The memory48can be any suitable type of memory, such as block ram (BRAM). Rather than using a separate memory, system memory can be shared.

It should be appreciated that, due to its capability of being controlled and reconfigured on the fly and in real time, the single BER analyzer50′ may function to test more than one PHY interface on-chip, without the use of additional BER analyzers50′, and without the use of more than one set of BER determination circuitry55. These PHY interfaces may use different communications protocols.

This configuration is shown inFIG. 5. Here, the integrated circuit chip49′ includes a multiplexer80receiving test data from both an ethernet physical PHY interface82and a USB physical PHY interface84. The ethernet PHY interface82and USB PHY interface84are respectively coupled to a media access control (MAC) device81and a USB controller83, both of which are coupled to the system bus70. The multiplexer80selectively switches which of the ethernet PHY interface82and USB PHY interface84are coupled to the generic BER analyzer50′, which determines the bit error rate thereof.

The off-chip BER analyzer50′ and on-chip BER analyzers50described above cure the deficiencies and drawbacks of prior art devices, and have a variety of advantages. For example, similar architecture can be used for both off-chip and on-chip designs, and can be used for any sort of physical interfaces or communications protocols, as explained above. In addition, as also described above, a single BER analyzer50′ can function to determine the bit error rate of multiple different PHY standards (that require different test patterns) in an on-chip environment, such as a system on a chip. Further, a true and accurate bit error rate is calculated, and be calculated for single channel protocols and variable burst-to-burst latency protocols. It should be appreciated that the BER analyzer50′ can be used to implement a built in self test for any suitable device.

The BER analyzer50could be implemented within a field programmable gate array (FPGA) or within an application specific integrated circuit (ASIC), and used for determining the bit error rate of any device under test It should also be understood that the BER analyzer50′ may function to switch between determining the bit error rate of any number of on-chip devices.