Wiring board and method of manufacturing wiring board

A wiring board includes an insulating layer; an insulating oxide film that is formed by forming a film of metal oxide or semimetal oxide on a surface of the insulating layer; a seed layer that is made of metal and that is stacked on the insulating oxide film; and an electrode that is made of metal and that is formed on the seed layer, wherein the insulating oxide film and the seed layer are removed from an area not overlapping the electrode to expose the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2020-132588, filed on Aug. 4, 2020, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a wiring board and a method or manufacturing a wiring board.

BACKGROUND

In general, a wiring board including fine wirings is manufactured, for example, by forming a seed layer serving as a cathode on a surface of an insulating base material, such as polyimide, and forming electrodes of metal, such as copper, on the seed layer, for example, by electrolytic plating. Like the electrodes, the seed layer is a layer made of metal, such as copper, and covers the entire surface of the base material. In order to increase adhesion between the seed layer and the base material, for example, an adhesion layer using metal, such as titanium, may be formed between the seed layer and the base material.

The seed layer and the adhesion layer are formed by, for example, sputtering. In other words, titanium sputtering on the surface of the base material forms the adhesion layer and copper sputtering on the surface of the adhesion layer forms the seed layer. For example, oxide of transition metal, such as titanium or hafnium, may be used as the adhesion layer and, in that case, an insulating adhesion layer is formed.

After the electrodes are formed on the seed layer, the seed layer is removed by, for example, etching between adjacent electrodes. In other words, for example, when the seed layer is formed using copper, the seed layer between the electrodes is removed by wet etching using a copper etching solution (etching solution A).

In a wiring board in which an adhesion layer, seed laver, and electrodes are stacked in sequence on a base material however has a problem in that short circuit between the electrodes and decrease in reliability would occur. Specifically, on removal of the seed layer and the adhesion layer between the electrodes by wet etching from an intermediate structure in which the electrodes are formed by electrolytic copper plating on the seed layer, when the time in which the intermediate structure is immersed in an etching solution (etching solution A) is long, side etching in which side surfaces of the electrodes that are formed using copper like the seed layer are etched occurs. Thus, the intermediate structure not immersed excessively in the etching solution (etching solution A) for a long time. When the etching time is excessively shortened in order to reduce side etching, however, residue of the seed layer may remain on the adhesion layer. As a result, even when the adhesion layer is insulating, the residue remaining on the surface of the adhesion layer cause short circuit between the adjacent electrodes and decrease in reliability.

When the adhesion layer is formed of metal, such as titanium, the adhesion layer is etched after the seed layer is etched and a titanium etching solution (etching solution B) etches copper faster than titanium and accordingly the copper etching rate increases. For this reason, when the adhesion layer is etched, side etching in which the side surfaces of the electrodes are etched occurs. When the time in which the intermediate structure is immersed in the titanium etching solution (etching solution B) is shortened excessively in order to inhibit side etching, titanium that is a conductor remains between the electrodes and short circuit between the electrodes and decrease in reliability occur. Such short circuit between electrodes and decrease in reliability highly likely occur particularly in a wiring board having fine wirings in which the distance between adjacent electrodes is small.

SUMMARY

According to an aspect of an embodiment, a wiring board includes: an insulating layer; an insulating oxide film that is formed by forming a film of metal oxide or semimetal oxide on a surface of the insulating layer; a seed layer that is made of metal and that is stacked on the insulating oxide film; and an electrode that is made of metal and that is formed on the seed layer. The insulating oxide film and the seed layer are removed from an area not overlapping the electrode to expose the insulating layer.

DESCRIPTION OF EMBODIMENTS

Embodiments of a wiring board and a method of manufacturing a wiring board disclosed herein will be described in detail below with reference to the drawings. The embodiments do not limit the present invention.

[a] First Embodiment

FIG.1is a cross-sectional view illustrating a configuration of a wiring board100according to a first embodiment.FIG.1illustrates a cross section of a surface of the wiring board100on which electrodes containing wirings are formed and the vicinity of the surface. The wiring board100illustrated inFIG.1includes an insulating layer110, an oxide film120, a seed layer130, and electrodes141and142.

The insulating layer110is, for example, a base material of the wiring board100that is formed using insulating resin, such as polyimide. The insulating layer110may be one obtained by impregnating inorganic material fillers or glass fibers with epoxy resin, one obtained by impregnating paper with phenol resin, or Teflon (trademark). The insulating layer110has a thickness of, for example, approximately 50 μm

The oxide film120is an insulating film that is formed on a surface of the insulating layer110and is a layer that increases adhesion of the seed layer130to the insulating layer110. The oxide film120is formed by a film formation technique, such as plasma CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) using oxide of metal or semimetal, and the oxide film120can have a thickness of, for example, 1 to 500 nm, more preferably, 1 to 100 nm. The oxide film120is, for example, a film that is formed by ALD and thus the oxide film120has a high adhesion strength to the insulating layer110and has high adherence to a stereoscopic structure, such as a through hole, and side walls. As a result, even when a reliability test in which the wiring board100is under a condition of a high temperature and a high humidity as in HAST (Highly Accelerated Stress Test), it is possible to inhibit decrease or adhesion of the seed layer130to the insulating layer110.

It is preferable to use, as a material of the oxide film120, for example, hafnium oxide (hafnia), titanium oxide (titania), zirconium oxide (zirconia), niobium pentoxide, or the like. Vanadium pentoxide, chrome oxide, aluminum oxide (alumina), silicon oxide, indium oxide, tin oxide, antimony oxide, or the like, is also usable as a material of the oxide film120.

The oxide film120is formed on the surface of the insulating layer110in positions in which the electrodes141and142are formed and the oxide film120is removed between the electrodes141and142. Specifically, after the seed layer130is etched, the oxide film120is dry etched by, for example, argon reverse sputtering, ion trimming, laser processing, or the like, and is removed from an area not overlapping the electrodes141and142. As a result, the insulating layer110is exposed in the area between the electrodes141and142.

Accordingly, residue of the seed layer130remaining on the surface of the oxide film120is removed together with the oxide film120the area between the electrodes141and142, which makes it possible to prevent short circuit between the electrodes141and142and decrease in reliability. The oxide film120is a film that is made of insulating oxide and therefore, even when residue of the oxide film120remains on the surface of the insulating layer110, short circuit between the electrodes141and142and decrease in reliability do not occur.

Furthermore, as described above, because removal of the oxide film120is performed by, for example, dry etching, such as argon reverse sputtering, it is possible to inhibit side etching of the seed layer130and the electrodes141and142and reduce damage of the surface of the insulating layer110that is exposed in the area not overlapping the electrodes141and142.

The seed layer130is a conductive layer that is formed on the surface of the oxide film120and that serves as a cathode with respect to the electrodes141and142. The seed layer130is formed, for example, by sputtering using metal, such as copper, and the seed layer130can have a thickness of, for example, 30 to 3000 nm.

The electrodes141and142serve as wirings and electrodes that are formed on the wiring board100and are formed on a surface of the seed layer130by, for example, electrolytic copper plating. The electrodes141and142can have a height of, for example, 1 to 500 μm from the surface of the seed layer130. The electrodes141and142are adjacent to each other and, because the oxide film120and the seed layer130are removed in the area between the electrodes141and142, the electrodes141and142are insulated.

A method of manufacturing the wiring board100that is configured as described above will be described next with reference to the flowchart inFIG.2, taking an example specifically.

First of all, the oxide film120is formed by a film formation technique, such as ALD, on the surface of the insulating, layer110made of, for example, polyimide (step S101). Specifically, as illustrated inFIG.3, the oxide film120having a thickness of 1 to 500 nm is formed on the surface of the insulating layer110having a thickness of approximately 50 μm. The oxide film120is made of, for example, metal or semimetal oxide, such as hafnium oxide (hafnia), titanium oxide (titania), zirconium oxide (zirconia) or niobium pentoxide, and is formed by a film formation technique, such as ALD enabling formation of a film. Forming the oxide film120by ALD makes it possible to inhibit decrease in strength of adhesion of the oxide film120, for example, even after a reliability test, such as HAST.

The seed layer130is then formed by sputtering on the surface of the oxide film120(step S102). In other words, for example, as illustrated inFIG.4, the seed layer130having a thickness of 30 to 3000 nm is formed on the surface of the oxide film120by, for example, copper sputtering.

After the seed layer130is formed, a resist is formed on an area excluding areas in which electrodes containing wirings are to be formed (step S103). In other words, for example, as illustrated inFIG.5, a resist150having openings in areas in which the electrodes141and142are to be formed is formed. Using the resist150as a mask, for example, for example, electrolytic copper plating is performed (step S104). In other words, for example, as illustrated inFIG.6, copper is stacked in the openings of the resist150, so that the electrodes141and142are formed.

After the electrodes141and142are formed, the resist150is removed (step S105) and, for example, as illustrated inFIG.7, an intermediate structure having the electrodes141and142on the oxide film120and the seed layer130that are stacked on the insulating layer110is obtained. In the intermediate structure, the adjacent electrodes141and142are short-circuited via the seed layer130that is a conductor and thus the seed layer130in the area between the electrodes141and142is removed by copper etching (step3106). In other words, for example, as illustrated inFIG.8, the intermediate structure is immersed in a copper etching solution (etching solution A) using the electrodes141and142as an etching mask, so that the seed layer130in an area121not overlapping the electrodes141and142is removed. For example, a solution obtained by mixing sulfuric acid and hydrogen peroxide as main components is usable as the copper etching solution (etching solution A).

Wet etching in which the intermediate structure is immersed in the copper etching solution (etching solution A) is performed and thus side etching in which side surfaces of the electrodes141and142formed and made of copper are etched occurs. For this reason, it is preferable that the time during which the intermediate structure is immersed in the etching solution (etching solution A) would not be excessively long to inhibit side etching. As a result, residue of the seed layer130may remain in the area121but the residue is removed simultaneously with the following etching of the oxide film120.

In other words, after the wet etching of the seed layer130, for example, the oxide film120in the area121is removed by dry etching, such as argon reverse sputtering (step S107). The oxide film120is removed and accordingly the residue of the seed layer130remaining on the surface of the oxide film120is removed simultaneously and the insulating layer110is exposed in the area between the electrodes141and142. As a result, it is possible to prevent short circuit between the electrodes141and142and decrease reliability resulting from residue of the seed layer130. Furthermore, because dry etching, such as argon reverse sputtering, is performed, side etching of the seed layer130and the electrodes141and142is inhibited, which reduces damage of the side surfaces of the seed layer130and the electrodes141and142. Furthermore, different from wet etching in which the insulating layer110is immersed in the etching solution, dry etching, such as argon reverse sputtering, enables reduction of damage of the surface of the insulating layer110that is exposed in the area not overlapping the electrodes141and142.

As described above, according to the first embodiment, the insulating oxide film is formed as an adhesion layer on the surface of the insulating layer, the seed layer is formed on the surface of the oxide film, and the electrodes are formed on the seed layer. After the seed layer in the area not overlapping the electrodes is removed, the oxide film is removed by dry etching. Thus, even when residue of the seed layer remains in the area in which the electrodes are not formed, the residue is removed together with the oxide film, which makes it possible to prevent short circuit between the adjacent electrodes and decrease in reliability. Furthermore, because the oxide film is removed by dry etching, such as argon reverse sputtering, it is possible to inhibit side etching of the seed layer and the electrodes and reduce damage of the surface of the insulating layer more than when the residue is removed by performing reverse sputtering simply.

[b] Second Embodiment

FIG.9is a cross-sectional view illustrating a configuration of the wiring board100according to a second embodiment. InFIG.9, the same components as those inFIG.10are denoted with the same reference numbers.FIG.9illustrates a cross section of a surface of the wiring board100on which electrodes containing wirings are formed and the vicinity of the surface. The wiring board100illustrated inFIG.9includes the insulating layer110, an insulating layer115, the oxide film120, the seed layer130, the electrodes141and142, conductive layers210and215, a via220, second seed layer230, and a via240.

The wiring board100according to the second embodiment is a multi-layer board obtained by layering the multiple insulating lavers110and115and the multiple conductive layers210and215. Under the conductive layer illustrated inFIG.9, another insulating layer and another conductive layer may be further stacked.

The insulating layers110and115are insulating layers that are made of, for example, insulating resin, such as polyimide. The insulating layer110covers the conductive layer210that is formed on a surface of a lower insulating layer and the conductive layer215is formed on a surface of the insulating layer110. The conductive layer215is covered with the insulating layer115. As described above, the wiring board100has a build-up layer obtained by stacking the insulating layers110and115and the conductive layers210and215.

The conductive layers210and215are formed on upper surfaces of the respective insulating layers by, for example, patterning metal, such as copper. The conductive layers210and215that are formed on the upper surfaces of the insulating layers that are different from each other are electrically connected via the via220that penetrates the insulating layer110. The conductive layer215that is formed on the upper surface of the insulating layer110and the electrode141that is formed on the upper surface of the insulating layer115are electrically connected via the via240that penetrates the insulating layer115.

The oxide film120is an insulating film that is formed on a surface of the insulating layer115and is a layer that increases adhesion of the seed layer130to the insulating layer115. The oxide film120is formed by a film formation technique, such as plasma CVD or ALD using metal or semimetal oxide, and the oxide film120can have a thickness of, for example, 1 to 500 nm. The oxide film120is a film that is formed by, for example, ALD and thus the oxide film120has a high strength of adhesion to the insulating layer115and, even when a reliability test in which the wiring board100is under a condition of a high temperature and a high humidity as in HAST, it is possible to inhibit decrease of adhesion of the seed layer130to the insulating layer115.

It is preferable to use, as a material of the oxide film120, for example, hafnium oxide (hafnia), titanium oxide (titania), zirconium oxide (zirconia), niobium pentoxide, or the like. Vanadium pentoxide, chrome oxide, aluminum oxide (alumina), silicon oxide, indium oxide, tin oxide, antimony oxide, or the like, is also usable as a material of the oxide film120.

The oxide film120is formed on the surface of the insulating layer115in positions in which the electrodes141and142are formed and the oxide film120is removed between the electrodes141and142. In the second embodiment, the oxide film120is removed also in the position of the via240. Specifically, after the seed layer130is etched, the oxide film120dry etched by, for example, argon reverse sputtering, ion trimming, laser processing, or the like, and is removed from an area between the electrodes141and142and an area in which the via240is formed.

The seed layer130is a conductive layer that is formed on the surface of the oxide film120and that serves as a cathode with respect to the electrodes141and142. The seed layer130is formed by, for example, sputtering using metal, such as copper, and the seed layer130can have a thickness of, for example, 30 to 3000 nm.

The electrodes141and142serve as wirings and electrodes that are formed on the surface of the wiring board100and the electrodes141and142are formed on the surface of the second seed layer230by, for example, electrolytic copper plating. The electrodes141and142can have a height of, for example, 1 to 500 μm from the surface of the second seed layer230. The electrodes141and142are adjacent to each other and, because the oxide film120, the seed layer130, and the second seed layer230are removed the area between the electrodes141and142, the electrodes141and142are insulated. The electrode141is electrically connected to the conductive layer215via the via240.

The second seed layer230is a conductive layer that is formed on a surface of the seed layer130and the an outer circumference of the via240and that serves as a cathode together with the seed layer130with respect to the electrodes141and142. Like the seed layer130, the second seed layer230is formed by, for example, sputtering using metal, such as copper.

Because of formation of the second seed layer230and the electrode141in the via hole penetrating the insulating layer115, the via240electrically connects the electrode141and the conductive layer215. In other words, the second seed layer230that is formed on the inner surface of the via hole makes contact with the conductive layer215and the electrode141extends to the inner concave of the second seed layer230.

A method of manufacturing the wiring board100that is configured as described above will be described next with reference to the flowchart inFIG.10, taking an example specifically. InFIG.10, the same components as those inFIG.2are denoted with the same reference numbers.

First of all, a build-up layer is formed by stacking insulating lavers and conductive lavers (step S201). Specifically, for example, as illustrated inFIG.11, after the conductive layer210is formed on an upper surface of an insulating layer, the insulating layer110is stacked such that the insulating layer110covers the conductive layer210. The via220penetrating the insulating layer110is then formed and the conductive layer215is formed on the upper surface of the insulating layer110. Furthermore, the insulating layer115is stacked such that the insulating layer115covers the conductive layer215.

The oxide film120is formed by a film formation technique, such as ALD, on the surface of the insulating layer115(step S101). Specifically, as illustrated inFIG.12, the oxide film120having a thickness of 1 to 500 nm is formed on the surface of the insulating layer115that is the top layer of the build-up layer. The oxide film120is made of, for example, metal or semimetal oxide, such as hafnium oxide (hafnia), titanium oxide (titania), zirconium oxide (zirconia) or niobium pentoxide, and is formed by a film formation technique, such as ALD enabling formation of a film. Forming the oxide film120by ALD, for example, makes it possible to inhibit decrease in strength of adhesion of the oxide film120even after a reliability test, such as HAST.

The seed layer130is then formed on the surface of the oxide film120by sputtering (step S102). Furthermore, a resist is formed on the upper surface of the seed layer130in an area excluding the area in which the via240is to be formed (step S202). In other words, for example, as illustrated inFIG.13, the seed layer130having a thickness of 30 to 3000 nm is formed on the surface of the oxide film120by, for example, copper sputtering. Thereafter, a resist250having an opening in the area in which the via240is to be formed is formed.

The seed layer130is then etched, using the resist250as an etching mask (step S203). Specifically, for example, as illustrated inFIG.14, the seed layer130in the opening of the resist250is removed and the oxide film120is exposed in an area122in which the via240is to be formed.

After the seed layer130in the area122is removed, the resist250is removed (step S204) and, as illustrated inFIG.15, the oxide film120is exposed in the area122and the oxide film120is covered with the seed layer130in the area excluding the area122. Thus, the oxide film120is etched, sing the seed layer130as an etching mask (step S205). Specifically, for example, as illustratedFIG.16, the oxide film120in the area122is removed by, for example, dry etching, such as argon reverse sputtering. Dry etching, such as argon reverse sputtering, is performed and accordingly only the oxide film120is removed, which makes it possible to reduce damage of the seed layer130and the insulating layer115.

For example, anisotropic etching or laser processing is performed on the insulating layer115that is exposed because of removal of the oxide film120, so that a via hole that penetrates the insulating layer115is formed (step S206). In other words, as illustrated inFIG.17, in the area in which the oxide film120and the seed layer130are removed, a via hole115ais formed in the insulating layer115. The via hole115apenetrates the insulating layer115and reaches the conductive layer215and the conductive layer215is exposed at the bottom surface of the via hole115a.

After the via hole115ais formed, the second seed layer230is formed by sputtering on the upper surface of the seed layer130and the inner surface of the via hole115a(step S207). On the upper surface of the second seed layer230, a resist is formed in the area excluding areas in which electrodes containing wirings are to be formed (step S103). In other words, for example, as illustrated inFIG.18, the second seed layer230having a thickness of 30 to 3000 nm is formed by, for example, copper sputtering on the surface of the seed layer130and the inner surface of the via hole115a. Thereafter, a resist260having openings in the areas in which the electrodes141and142are to be formed is formed.

Using the resist260as a mask, for example, electrolytic copper plating is performed (step S104). In other words, for example, as illustrated inFIG.19, copper is stacked in the openings of the resist260and the electrodes141and142are formed. In this case, the electrode141extends to the inner concave of the second seed is230that is formed on the inner surface of the via hole115aand the via240that electrically connects the electrode141and the conductive layer215is formed.

After the electrodes141and142are formed, the resist260is removed (step S105) and, for example, as illustrated inFIG.20, an intermediate structure including the electrodes141and142on the oxide film120, the seed layer130, and the second seed layer230that are stacked on the surface of the insulating layer115and including the via240that connects the electrode141and the conductive layer215is obtained. In the intermediate structure, the adjacent electrodes141and142are short-circuited via the seed layer130and the second seed layer230that are conductors and thus the seed layer130and the second seed layer230in the area between the electrodes141and142are removed by copper etching (step S208). In other words, for example, as illustrated inFIG.21, the intermediate structure is immersed in a copper etching solution, using the electrodes141and142as an etching mask, so that the seed layer130and the second seed layer230in the area121not overlapping the electrodes141and142are removed.

Wet etching in which the intermediate structure is immersed in the copper etching solution is performed and thus side etching in which side surfaces of the electrodes141and142formed and made of copper are etched occurs. For this reason, it preferable that the time during which the intermediate structure is immersed in the etching solution would not be excessively long to inhibit side etching. As a result, residue of the seed layer130or the second seed layer230may remain in the area121but the residue is removed also during the following etching of the oxide film120.

In other words, after wet etching of the seed layer130and the second seed layer230, the oxide film120in the area121is removed by, for example, dry etching, such as argon reverse sputtering (step S107). The oxide film120is removed and accordingly the residue of the seed layer130or the second seed layer230remaining on the surface of the oxide film120is simultaneously removed, which makes it possible to prevent short circuit between the electrodes141and142and decrease in reliability. Furthermore, because dry etching, such as argon reverse sputtering, is performed, side etching of the seed layer130, the second seed layer230and the electrodes141and142is inhibited, which makes it possible to reduce damage of the side surfaces of the seed layer130, the second seed layer230and the electrodes141and142. Furthermore, different from wet etching in which the insulating layer115is immersed in the etching solution, dry etching, such as argon reverse sputtering, enables decrease of damage of the surface of the insulating layer115.

As described above, according to the second embodiment, after the oxide film and the seed layer are formed on the surface of the insulating layer, the via is formed by removing the oxide and the seed layer in the position in which the electrode is to be formed and the electrode that is connected to the inter-layer wiring via the via is formed. After the seed layers in the area not overlapping the electrodes are removed, the oxide film is removed by dry etching. Thus, it is possible to manufacture a multi-laver board including an oxide film as an adhesion layer and, even when residue of the seed layer remains in the area in which the electrodes are not formed, the residue is removed together with the oxide film, which makes it possible to prevent short circuit between the adjacent electrodes and decrease in reliability. Furthermore, because the oxide film is removed by dry etching, such as argon reverse sputtering, it is possible to inhibit side etching of the seed layers and the electrodes and more reduce damage of the surface of the insulating layer than when residue of the seed layer is dry etched independently.

In the second embodiment, after the oxide film120and the seed layer130are formed on the surface of the insulating layer115, the oxide film120and the seed layer130in the area in which the via240is to be formed are removed and the via hole115ais formed. It is, however, also possible to form the via hole115aat an early stage before the oxide film120and the seed layer130are formed. Thus, in the third embodiment, a method of manufacturing the wiring board100in the case where the via hole115ais formed at an initial stage will be described.

The configuration of the wiring board100according to the third embodiment is the same as that of the second embodiment (FIG.9) and thus description thereof will be omitted. In the third embodiment, the method of manufacturing the wiring hoard100differs from that of the second embodiment. The method of manufacturing the wiring board100according to the third embodiment will be described with reference to the flowchart illustratedFIG.22, taking an example specifically. InFIG.22, the same components as those inFIG.2andFIG.10are denoted with the same reference numbers and detailed description will be omitted.

First of all, a build-up layer is formed by stacking insulating layers and conductive layers (step S201). In other words, a build-up layer including the insulating layers110and115and the conductive layers210and215that are stacked and including the via220that electrically connects the conductive layers210and215is formed.

For example, anisotropic etching or laser processing is performed on the insulating layer115that is the top layer of the build-up layer, so that a via hole that penetrates the insulating layer115is formed (step S301). In other words, as illustrated inFIG.23, in the area in which the via240is to be formed, the via hole115ais formed in the insulating layer115. The via hole115apenetrates the insulating layer115and reaches the conductive layer215and the conductive layer215is exposed at the bottom surface of the via hole115a.

The oxide film120is then formed by a film formation technique, such as ALD, on the surface of the insulating layer115and the inner surface of the via hole115a(step S101). Specifically, for example, as illustrated inFIG.24, the oxide film120having a thickness of 1 to 500 nm is formed on the surface of the insulating layer115and the inner surface of the via hole115a. The oxide film120is formed by a film formation technique, such as ADD enabling formation of a film, using, for example, metal or semimetal oxide, such as, hafnium oxide (hafnia), titanium oxide (titania), zirconium oxide (zirconia) or niobium pentoxide, as a material. Forming the oxide film120by ADD makes it possible to inhibit decrease in strength of adhesion of the oxide film120, for example, also after a reliability test, such as HAST.

The seed layer130is then formed on the surface of the oxide film120by sputtering (step3102). In other words, for example, as illustrated inFIG.25, the seed layer130having a thickness of 30 nm to 3000 nm is formed on the surface of the oxide film120by, for example, copper sputtering. In the via hole115a, because the oxide film120and the seed layer130are formed along the inner surface of the via hole115aand the upper surface of the conductive layer215, the concave is formed.

After the seed layer130is formed, a resist is formed in an area excluding the area of the via hole115aon the upper surface of the seed layer130(step S202). In other words, for example, as illustrated inFIG.26, the resist250having an opening in the area of the via hole115ais formed. The seed laser130is then etched, using the resist250as an etching mask (step S203). Specifically, as illustrated inFIG.27, the seed layer130in the opening of the resist250is removed and the oxide film120is exposed in the area containing the concave in the via hole115a.

After the seed layer130in the area of the via hole115ais removed, the resist250is removed (step S204) and, for example, as is ratedFIG.28, the oxide film120is exposed in the area of the via hole115aand the oxide film120is covered with the seed layer130in the area other than the area of the via hole115a. Thus, using the seed layer130as an etching mask, the oxide film120is etched (step S205). This leads to the same state as the state (FIG.17) in which the via hole115ais formed in the second embodiment and accordingly, as in the second embodiment, the electrodes141and142and the via240are formed.

In other words, the second seed layer230is formed by sputtering on the upper surface of the seed layer130and the inner surface of the via hole115a(step S207) and a resist is formed in the area excluding the areas in which the electrodes141and142are to be formed on the upper surface of the second seed layer230(step S103). For example, copper plating is performed, using the resist as a mask (step S104), the electrodes141and142and the via240are formed accordingly, and then the resist is removed (step S105). Thereafter the seed layer130and the second seed layer230in the area not overlapping the electrodes141and142are removed by copper etching (step S208) and the oxide film120in the area not overlapping the electrodes141and142is removed by, for example, dry etching, such as argon reverse sputtering (step S107).

As described above, according to the third embodiment, after the via hole is formed in the insulating layer, the oxide film and the seed layer are formed on the surface of the insulating layer and the inner surface of the via hole, the oxide film and the seed layer in the area of the via hole are then removed, and the electrodes and the via are formed. After the seed layers in the area not overlapping the electrodes is removed, the oxide film is removed by dry etching. Thus, it is possible to manufacture a multi-layer board including an oxide film as an adhesion layer and, even when residue of the seed layer remains in the area in which no electrode is formed, the residue is removed together with the oxide film and this makes it possible to prevent short circuit between the adjacent electrodes and decrease of reliability. Furthermore, because the oxide film is removed by dry etching, such as argon reverse sputtering, it is possible to inhibit side etching of the seed layers and the electrodes and reduce damage of the surface of the insulating layer.

With respect to the embodiments and the variety thereof described above, the following notes are further disclosed.

(Note 1) A method of manufacturing a wiring board including:forming an insulating oxide film by forming a film of metal oxide or semimetal oxide on a surface of an insulating layer;stacking a seed layer made of metal on the insulating oxide film;forming an electrode that is made of metal on the seed layer,removing the seed layer from an area not overlapping the electrode; andremoving the insulating oxide film in the area from which the seed layer is removed to expose the insulating layer.

(Note 2) The method according to Note 1, wherein the forming the insulating oxide film includes forming a film of hafnium oxide that is oxide of hafnium.

(Note 3) The method according to Note 2, wherein the forming the insulating oxide film includes forming a film of hafnium oxide that has a thickness of 1 to 100 nm by ALD (Atomic Layer Deposition).

(Note 4) The method according to Note 1, wherein the removing the insulating oxide film includes removing the insulating oxide film by dry etching using the seed layer as an etching mask.

(Note 5) The method according to Note 4, wherein the removing the insulating oxide film includes removing the insulating oxide film by argon reverse sputtering.

(Note 6) The method according to Note 1, further including:removing the seed layer and the insulating oxide film in a partial area;forming a via hole that penetrates the insulating layer in the area from which the seed layer and the oxide film are removed; andforming a second seed layer on a surface of the seed layer and an inner surface of the via hole,wherein the forming the electrode includes forming the electrode on the second seed layer, andthe removing the seed layer includes removing the seed layer and the second seed layer.

(Note 7) The method according to Note 1, further comprising forming a via hole penetrating the insulating layer,wherein the forming the insulating oxide film includes forming the insulating oxide film on a surface of the insulating layer and an inner surface of the via hole,the forming the electrode includesremoving the seed layer and the insulating oxide film in an area of the via hole,forming a second seed layer on a surface of the seed layer and the inner surface of the via hole, andforming the electrode on the second seed layer.

According to a mode of a wiring board and a method of manufacturing a wiring hoard disclosed herein, an effect that it is possible to prevent short circuit between electrodes and decrease in reliability is achieved.