Device and method for providing filtering for an analog-to-digital converter (ADC)

Devices and methods for providing filtering for an analog-to-digital converter (ADC) are described. In one embodiment, a method for providing filtering for an ADC involves obtaining a filter coefficient of a post-filtering filter that is located after the ADC on a signal path and generating a filter coefficient of a pre-filtering filter that is located before the ADC on the signal path based on the filter coefficient of the post-filtering filter. Other embodiments are also described.

Embodiments of the invention relate generally to electronic systems and methods and, more particularly, to systems and methods for operating filters.

In a communications system, an analog-to-digital converter (ADC) based architecture can be used to reduce the total cancellation of intersymbol interference (ISI) and echo presence in received signals. Signal quality of received signals can be improved by increasing ADC dynamic range and resolution. However, increasing dynamic range and resolution in an ADC can result in increment in substrate area and power consumption of an Integrated Circuit (IC) chip. For example, every extra bit requirement in a high speed ADC can roughly double the silicon area and power consumption of an IC chip.

Typically, filters can be used in the signal path before and/or after an ADC to improve the signal-to-noise ratio (SNR), which reduces the ADC resolution requirement. For example, filters, such as a non-adaptive analog high pass filter or an adaptive analog equalizer, can be placed in the signal path before an ADC. However, a non-adaptive analog high pass filter generally does not cope well with a communications channel that varies over time. An analog adaptive filter with an independent adaptive algorithm can work with the time varying channel. However, an analog adaptive filter with an independent adaptive algorithm typically has a maximum of 2 taps because of design complexity and reduction in algorithm accuracy associated with a high number of taps.

Devices and methods for providing filtering for an ADC are described. In one embodiment, a method for providing filtering for an ADC involves obtaining a filter coefficient of a post-filtering filter that is located after the ADC on a signal path and generating a filter coefficient of a pre-filtering filter that is located before the ADC on the signal path based on the filter coefficient of the post-filtering filter. Other embodiments are also described.

In one embodiment, a device for providing filtering for an ADC includes a monitoring module configured to obtain a filter coefficient of a post-filtering filter that is located after the ADC on a signal path and a filter coefficient generation module configured to generate a filter coefficient of a pre-filtering filter that is located before the ADC on the signal path based on the filter coefficient of the post-filtering filter.

In one embodiment, a method for providing filtering for an ADC involves obtaining a filter coefficient of a post-filtering filter that is located after the ADC on a signal path by adjusting the filter coefficient of the post-filtering filter iteratively according to a least mean square (LMS) algorithm and generating a filter coefficient of a pre-filtering filter that is located before the ADC on the signal path based on the filter coefficient of the post-filtering filter by linearly converting an amplitude of the filter coefficient of the post-filtering filter into an amplitude of the filter coefficient of the pre-filtering filter.

Other aspects and advantages of embodiments of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, depicted by way of example of the principles of the invention.

FIG. 1is a schematic block diagram of an ADC device100in accordance with an embodiment of the invention. The ADC device can be used for various applications. In an embodiment, the ADC device is a part of a communication network that is used for an automotive application. For example, the communication network facilitates communication among communication devices, such as electronic controller nodes in an automobile system, which may be located within a single vehicle or distributed across multiple vehicles. The communication network may be an in-vehicle network (IVN), for example, a Local Interconnect Network (LIN), a Controller Area Network (CAN) or a FlexRay™ compatible network. The ADC device can be embodied in various physical forms. For example, the ADC device may be implemented as an Integrated Circuit (IC) chip. In an embodiment, the ADC device is a physical layer (PHY) chip, such as an Ethernet PHY chip, which may be a part of an automotive device.

In the embodiment depicted inFIG. 1, the ADC device100includes a pre-filtering filter102, an ADC104, a post-filtering filter106, and a control device108. Although the ADC device is shown inFIG. 1as being including one pre-filtering filter, in some embodiments, the ADC device includes multiple pre-filtering filters. In addition, although the ADC device is shown inFIG. 1as including one post-filtering filter, in some embodiments, the ADC device includes multiple post-filtering filters.

The pre-filtering filter102of the ADC device100is located on the signal path130before the ADC104. The pre-filtering filter can be used to improve the SNR, which reduces the ADC resolution requirement. The pre-filtering filter can be any suitable type of analog filter. In some embodiments, the pre-filtering filter is an analog finite impulse response (FIR) filter whose impulse response is of finite duration.

The ADC104of the ADC device100is configured to convert an analog signal from the pre-filtering filter102into a digital signal that is transmitted to the post-filtering filter106. For example, the ADC can convert an analog signal with certain amplitude and phase into a digital signal with a corresponding number of bits.

The post-filtering filter106of the ADC device100is located on the signal path130after the ADC104. The post-filtering filter can be any suitable type of digital filter. In some embodiments, the post-filtering filter is a digital FIR filter whose impulse response is of finite duration. For a digital filter, such as a FIR filter, the output signal of the digital filter is a weighted sum of the current and previous values of an input signal to the digital filter, which include a signal sample and one or more delayed versions of the signal sample. The current and previous values of the input signal to the digital filter are referred to as the taps of the digital filter. In other words, taps of a digital filter are variations (undelayed/delayed) of the input signal of the digital filter that are included in the output signal of the digital filter. For example, the output signal, y[n], and the input signal, d[n], of a discrete time FIR filter may satisfy:

y⁡[n]=∑i=0N⁢Ci⨯d⁡[n-i],(1)
where Cirepresents filter coefficients, N represents the filter order, d[n−1] represents filter taps, and N is a positive integer. Herein, n represents the signal index of a discrete signal, which is a non-negative integer.

The control device108of the ADC device100is configured to generate a filter coefficient of the pre-filtering filter102based on a filter coefficient of the post-filtering filter106. Consequently, the filter coefficient of the post-filtering filter can be re-used for generating the filter coefficient of the pre-filtering filter. By reusing the filter coefficient of the post-filtering filter to generate the filter coefficient of the pre-filtering filter, the complexity of the pre-filtering filter can be reduced while the requirements for the pre-filtering filter in terms of coefficient accuracy and the number of taps can be satisfied. For example, compared to a typical pre-filtering filter that has a maximum of 2 taps because of design complexity and the accuracy of adaptive algorithm associated with a high number of filter taps, the pre-filtering filter depicted inFIG. 1can have more than two taps. In addition, instead of having a separate adaptive algorithm for a pre-filter with number of taps that is more than two, reusing the filter coefficient of the adaptive post-filtering filter can allow the accuracy of the adaptive algorithm of the pre-filtering filter to be close to the accuracy of the adaptive algorithm of the post-filtering adaptive filter and reduce the area overheard of the pre-filtering filter.

In the embodiment depicted inFIG. 1, the control device108includes a monitoring module110configured to obtain the filter coefficient of the post-filtering filter106and a filter coefficient generation module112configured to generate a filter coefficient of the pre-filtering filter102based on the filter coefficient of the post-filtering filter. In some embodiments, the control device is configured to monitor, manipulate and/or control of the filter coefficient of the pre-filtering filter or the post-filtering filter. For example, the control device is configured to linearly convert the filter coefficient amplitude of the post-filtering filter into the required filter coefficient amplitude of the pre-filtering filter, which is set to be lower than a predefined amplitude threshold. In another example, the control device is configured to vary the filter coefficient amplitude of the pre-filtering filter depending on the timing or a mode of operation of the pre-filtering filter. In one embodiment, the control device is configured to evaluate the filter coefficient amplitude of the pre-filtering filter after monitoring parameters such as amplitude and timing. The filter coefficient amplitude of the pre-filtering filter may be identical to the filter coefficient amplitude of the post-filtering filter. Alternatively, the filter coefficient amplitude of the pre-filtering filter is different from the filter coefficient amplitude of the post-filtering filter.

In an example operation of the ADC device100, an input analog signal is inputted into the pre-filtering filter102in which the input analog signal is filtered into a filtered analog signal. The filtered analog signal is inputted into the ADC104in which the filtered analog signal is converted into a digital signal. The digital signal is inputted into the post-filtering filter106in which the digital signal is filtered into a filtered digital signal. The control device108obtains the filter coefficient of the post-filtering filter and sets the filter coefficient for the pre-filtering filter based on the filter coefficient of the post-filtering filter.

FIGS. 2 and 3depict two embodiments of the ADC device100depicted inFIG. 1. ADC devices200,300depicted inFIGS. 2 and 3are merely two of the possible implementations of the ADC device100depicted inFIG. 1. However, the ADC device100depicted inFIG. 1can be implemented differently from the ADC devices200,300depicted inFIGS. 2 and 3. The invention is not restricted to the particular implementation of the devices depicted inFIGS. 2 and 3.

FIG. 2depicts a first embodiment of the ADC device100depicted inFIG. 1. In the embodiment depicted inFIG. 2, the ADC device200includes an analog pre-filtering filter202, an ADC204, a digital post-filtering filter206, and a control interface device208. The pre-filtering filter and the ADC are analog devices while the post-filtering filter and the control interface device are digital devices.

In the embodiment depicted inFIG. 2, the post-filtering filter206is located in digital domain216while the pre-filtering filter and the ADC204are located in analog domain214. Consequently, the filter coefficient of the analog pre-filtering filter202is computed in digital domain and an existing adaptive filter algorithm used by the digital post-filtering filter, such as a least mean square (LMS) algorithm or a recursive least square (RLS) algorithm, can be used to update the filter coefficient of the analog pre-filtering filter through the control interface device208. By reusing the filter coefficient of the digital post-filtering filter to generate the filter coefficient of the analog pre-filtering filter, the complexity of the analog pre-filtering filter can be reduced while the requirements for the analog pre-filtering filter in terms of coefficient accuracy and the number of taps can be satisfied. In addition, ADC bits can be reduced significantly by improving the SNR in the signal path before ADC. For example, without a partial adaptive pre-filtering filter, an 8-bit ADC is required while with a partial adaptive pre-filtering filter, a 5-bit ADC can be used to replace the 8-bit ADC. Further, the number of feed forward equalizer (FFE) and decision feedback equalizer (DFE) taps can be reduced, e.g., by a factor of 2, and ISI removal and echo cancellation can be improved. Compared to a typical ADC device, the ADC device200can reduce power consumption and the complexity of signal processing blocks.

The analog pre-filtering filter202of the ADC device200is located on the signal path before the ADC204. In some embodiments, the pre-filtering filter is an analog FIR filter whose impulse response is of finite duration. In the embodiment depicted inFIG. 2, the pre-filtering filter is used to provide partial equalization. In some embodiments, the pre-filtering filter may be used for echo cancellation.

The ADC204of the ADC device200is configured to convert an analog signal from the analog pre-filtering filter202into a digital signal that is transmitted to the post-filtering filter206.

The digital post-filtering filter206of the ADC device200is located on the signal path after the ADC204. In some embodiments, the post-filtering filter may be a digital FIR filter whose impulse response is of finite duration. In the embodiment depicted inFIG. 2, the post-filtering filter includes a feed forward equalizer (FFE)220, a decision feedback equalizer (DFE)222, a slicer224, an adaptive controller226and two adders228,230. In an embodiment, the post-filtering filter is an adaptive filter that adjusts the coefficients of the post-filtering filter iteratively to minimize the error signal, “e(n),” of the post-filtering filter.

The FFE220of the digital post-filtering filter206is configured to correct a received waveform with information about the waveform itself and not information about the logical decisions made on the waveform. In some embodiments, the FFE uses the voltage levels of a received waveform associated with previous and current bits to correct the voltage level of a current bit.

The DFE222of the digital post-filtering filter206is configured to calculate a correction value that is added to the logical decision threshold. The DFE allows new logical decisions to be made on the signal waveform based upon a new threshold level.

The slicer224of the digital post-filtering filter206is configured to process the combination signal from the FFE and the DFE and to generate a signal for the DFE.

The adaptive controller226of the digital post-filtering filter206is configured to control the FFE and the DFE based on the error signal, “e(n).” In some embodiments, the adaptive controller is configured to control the FFE and the DFE to minimize the error signal. The adaptive controller adjusts the filter coefficients according to an adaptive algorithm. In some embodiments, the adaptive controller adjusts the filter coefficients iteratively according to a distance-based algorithm, such as a least mean square (LMS) algorithm or a recursive least square (RLS) algorithm.

In one embodiment, the adaptive controller226adjusts the filter coefficients iteratively according to the LMS algorithm. For example, the adaptive controller calculates an error signal e(n) as:
e(n)=d(n)−y(n),  (2)
where y(n) represents an output signal from the adder228, d(n) represents an output signal from the slicer224, and n is a positive integer. The output signal y(n) can be represented as:
y(n)=X(n).CFFE(n)−D(n).CDFE(n),  (3)
where CFFE(n) represents the filter coefficients of the FFE220and CDFE(n) represents the filter coefficients of the DFE222. The adaptive controller updates the FFE filter coefficients by using the following equation:
FFE(n+1)=CFFE(n)+u.e(n).X(n),  (4)

Similarly, the adaptive controller updates the DFE filter coefficients by using the follow equation:
DFE(n+1)=CDFE(n)+u.e(n).D(n),  (5)
where η represents the step size of the adaptive filter, C(n) represents the filter coefficients vector D(n) represents the slicer output vector, and X(n) represents the filter (FFE) input vector. However, in another embodiment, Eqs. (4) and (5) can be derived as a function of an ideal integrator or a non-ideal integrator.

The control interface device208of the ADC device200is configured to monitor or manipulate the filter coefficient of the post-filtering filter206and to control the filter coefficient of the pre-filtering filter202based on the filter coefficient of the post-filtering filter. In some embodiments, the control interface device is configured to monitor, manipulate and/or control of the filter coefficient of the pre-filtering filter or the post-filtering filter. In one embodiment, the control interface device is configured to linearly convert the filter coefficient amplitude of the post-filtering filter into the required filter coefficient amplitude of the pre-filtering filter, which is set to be lower than a predefined amplitude threshold. In one embodiment, the control interface device is configured to vary the filter coefficient amplitude of the pre-filtering filter depending on timing or mode of operation. In one embodiment, the control interface device is configured to evaluate the filter coefficient amplitude of the pre-filtering filter after monitoring parameters such as amplitude and timing. In some embodiments, the filter coefficient of the pre-filtering filter is identical to the filter coefficient of the post-filtering filter. Alternatively, the filter coefficient of the pre-filtering filter is different from the filter coefficient of the post-filtering filter. In some embodiments, the control interface device includes one or more digital-to-analog converters (DACs), which are used to convert a digital control signal into an analog control signal for setting the filter coefficient of the pre-filtering filter.

In some embodiments, the control interface device208does not have capability of converting digital control signals into analog control signals. In these embodiments, one or more DACs are used to convert a digital control signal from the control interface device208into an analog control signal for setting the filter coefficient of the pre-filtering filter.FIG. 3depicts a second embodiment of the ADC device100depicted inFIG. 1. In the embodiment depicted inFIG. 3, the ADC device300includes an analog pre-filtering filter302, an ADC304, the digital post-filtering filter306, a control interface device308and one or more DACs330. The pre-filtering filter and the ADC are analog devices while the control interface device, the post-filtering filter and the DACs are digital devices. In the embodiment depicted inFIG. 3, the filter coefficient of the analog pre-filtering filter302is computed in digital domain316while the pre-filtering filter and the ADC304are located in analog domain314.

The analog pre-filtering filter302, the ADC304and the digital post-filtering filter306depicted inFIG. 3may be the same as or similar to the analog pre-filtering filter202, the ADC204and the digital post-filtering filter206depicted inFIG. 2, respectively. For example, the analog pre-filtering filter302of the ADC device300is located on the signal path before the ADC and is used to provide partial equalization. The ADC is configured to convert an analog signal from the analog pre-filtering filter into a digital signal that is transmitted to the post-filtering filter306. The digital post-filtering filter is located on the signal path after the ADC and includes an FFE320, a DFE322, a slicer324, an adaptive controller326and two adders328,330.

The FFE320, the DFE322, the slicer324and the adaptive controller326depicted inFIG. 3may be the same as or similar to the FFE220, the DFE222, the slicer224and the adaptive controller226depicted inFIG. 2, respectively. For example, the FFE of the digital post-filtering filter306can be configured to correct a received waveform with information about the waveform itself and not information about the logical decisions made on the waveform. The DFE can be configured to calculate a correction value that is added to the logical decision threshold. The DFE allows new logical decisions to be made on the signal waveform based upon the new equalized threshold level. The slicer can be configured to process the combination signal from the FFE and the DFE and to generate a signal for the DFE. The adaptive controller can be configured to control the FFE and the DFE based on the error signal, “e(n).”

The control interface device308of the ADC device300is configured to monitor or manipulate the filter coefficient of the post-filtering filter and to control the filter coefficient of the pre-filtering filter based on the filter coefficient of the post-filtering filter. The digital-to-analog converters (DACs)330are used to convert a digital control signal into an analog control signal for setting the filter coefficient of the pre-filtering filter.

FIG. 4is a process flow diagram of a method for providing filtering for an analog-to-digital converter (ADC) in accordance with an embodiment of the invention. At block402, a filter coefficient of a post-filtering filter that is located after the ADC on a signal path is obtained. At block404, a filter coefficient of a pre-filtering filter that is located before the ADC on the signal path is generated based on the filter coefficient of the post-filtering filter. The pre-filtering filter may be similar to or same as the pre-filtering filter102,202, or302depicted inFIG. 1, 2 or 3. The ADC may be similar to or same as the ADC104,204, or304depicted inFIG. 1, 2 or 3. The post-filtering filter may be similar to or same as the post-filtering filter106,206, or306depicted inFIG. 1, 2 or 3.

The various components or units of the embodiments that have been described or depicted (e.g., the control device108, the control interface devices208,308, the FFEs220,320, the DFEs222,322, the slicers224,324, and the adaptive controllers226,326) may be implemented in hardware, software that is stored in a non-transitory computer readable medium or a combination of hardware and software that is stored in a non-transitory computer readable medium. The non-transitory computer readable medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device), or a propagation medium. Examples of a non-transitory computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), a digital video disk (DVD), and a Blu-ray disk. Furthermore, the various components or units of the embodiments (e.g., the control device, the control interface devices, the FFEs, the DFEs, the slicers and the adaptive controllers) that have been described or depicted may be implemented in a processor, which may include a multifunction processor and/or an application-specific processor.

In addition, although specific embodiments of the invention that have been described or depicted include several components described or depicted herein, other embodiments of the invention may include fewer or more components to implement less or more feature.

Furthermore, although specific embodiments of the invention have been described and depicted, the invention is not to be limited to the specific forms or arrangements of parts so described and depicted. The scope of the invention is to be defined by the claims appended hereto and their equivalents.