Display device

A display device includes a plate-like substrate having a first surface and a second surface, pixel units on the first surface, and a power supply voltage feeder on the second surface. The power supply voltage feeder outputs first and second power supply voltages applicable to the pixel units. The second power supply voltage is lower in potential than the first power supply voltage. The display device includes a first wiring conductor electrically connecting the power supply voltage feeder and the pixel units and a second wiring conductor electrically connecting the power supply voltage feeder and the pixel units. At least one of the first or second wiring conductor includes a planar conductive portion covering the first surface. The planar conductive portion includes connectors connected to the power supply voltage feeder on at least two sides of the substrate.

FIELD

The present disclosure relates to a display device.

BACKGROUND

A known technique is described in, for example, Patent Literature 1.

CITATION LIST

Patent Literature

BRIEF SUMMARY

A display device according to one or more aspects of the present disclosure includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of pixel units on the first surface, and a power supply voltage feeder on the second surface. The power supply voltage feeder outputs a first power supply voltage and a second power supply voltage applicable to the plurality of pixel units. The second power supply voltage is lower in potential than the first power supply voltage. The display device includes a first wiring conductor electrically connecting the power supply voltage feeder and the plurality of pixel units to apply the first power supply voltage to the plurality of pixel units and a second wiring conductor electrically connecting the power supply voltage feeder and the plurality of pixel units to apply the second power supply voltage to the plurality of pixel units. At least one of the first wiring conductor or the second wiring conductor includes a planar conductive portion covering the first surface. The planar conductive portion includes connectors connected to the power supply voltage feeder on at least two sides of the substrate.

DETAILED DESCRIPTION

A known display device with the structure that forms the basis of a display device according to one or more embodiments of the present disclosure includes multiple pixel units including, for example, light-emitting diodes or organic electroluminescent (EL) elements (e.g., Patent Literature 1). Such a display device includes a substrate that includes terminals for providing power supply voltage signals to the pixel units in a peripheral portion along one side of the substrate.

In the display device with the structure that forms the basis of the display device according to one or more embodiments of the present disclosure, a potential difference between a high-potential power supply voltage and a low-potential power supply voltage may vary across the display surface. This may cause image quality deterioration such as unevenness in luminance or color.

A display device according to one or more embodiments of the present disclosure will now be described with reference to the drawings. Each figure referred to below shows main components and other elements of the display device according to the embodiments of the present disclosure. The display device according to the embodiments of the present disclosure may thus include known components not shown in the figures, such as circuit boards, wiring conductors, control integrated circuits (ICs), and large-scale integration (LSI) circuits.

FIG.1Ais a schematic plan view of a display device according to one embodiment of the present disclosure as viewed from a first surface.FIG.1Bis a schematic plan view of the display device according to the embodiment of the present disclosure as viewed from a second surface.FIG.2Ais a diagram showing the voltage distribution of a first power supply voltage across the first surface of the display device according to the embodiment of the present disclosure.FIG.2Bis a diagram showing the voltage distribution of a second power supply voltage across the first surface of the display device according to the embodiment of the present disclosure.FIG.3Ais a diagram showing the voltage distribution of a first power supply voltage across a first surface of a display device in a comparative example.FIG.3Bis a diagram showing the voltage distribution of a second power supply voltage across the first surface of the display device in the comparative example.

A display device1includes a substrate2, multiple pixel units3, a power supply voltage feeder4, a first wiring conductor5, and a second wiring conductor6.

The substrate2is, for example, a transparent or opaque glass substrate, a plastic substrate, or a ceramic substrate. The substrate2is a rectangular plate. The substrate2has a first surface2aand a second surface2bopposite to the first surface2a. The substrate2has a third surface2cincluding a first side2aaof the first surface2aand connecting the first surface2aand the second surface2b, and a fourth surface2dopposite to the third surface2c. The substrate in one or more embodiments of the present invention may be a polygonal plate. The substrate may not be rectangular, and may be hexagonal or octagonal.

The substrate2includes a first area21extending from an edge portion along the first side2aaon the first surface2aover the third surface2cand to the second surface2b. The substrate2includes a second area22extending from an edge portion along a second side2abfacing the first side2aaon the first surface2aover the fourth surface2dand to the second surface2b. The first wiring conductor5is located in the first area21and the second area22. As described later, the first wiring conductor5connects the power supply voltage feeder4and each pixel unit3and applies a first power supply voltage, which is a high voltage, to each pixel unit3.

The substrate2includes a third area23extending from an edge portion along the first side2aaon the first surface2aover the third surface2cand to the second surface2b. The substrate2includes a fourth area24extending from an edge portion along the second side2abon the first surface2aover the fourth surface2dand to the second surface2b. The second wiring conductor6is located in the third area23and the fourth area24. The second wiring conductor6connects the power supply voltage feeder4and each pixel unit3and applies a second power supply voltage, which is a voltage lower than the first power supply voltage, to each pixel unit3.

In the present embodiment, the first surface2aof the substrate2is rectangular, and the first side2aaand the second side2abare the short sides of the first surface2a, as shown in, for example,FIGS.1A and1B.

The pixel units3are on the first surface2aof the substrate2. The pixel units3are arranged in a matrix as viewed in a direction orthogonal to the first surface2a. Each pixel unit3includes at least one light emitter31. Each pixel unit3includes, for example, a thin-film transistor (TFT) as a switch, a TFT as a driving element, and a capacitor.

The light emitter31is a self-luminous light emitter such as a micro-light-emitting diode (LED), an EL element, an inorganic EL element, or a semiconductor laser element. In the present embodiment, the light emitter31is a micro-LED. The micro-LED may be rectangular as viewed in plan, or in other words, in the direction orthogonal to the first surface2a. In this case, the micro-LED may have each side with a length of about 1 to 100 μm inclusive, or about 3 to 10 μm inclusive.

Each pixel unit3may include a single light emitter31. Each pixel unit3may include a subpixel unit including a light emitter31R that emits red light, a subpixel unit including a light emitter31G that emits green light, and a subpixel unit including a light emitter31B that emits blue light. Each pixel unit3may include, instead of the subpixel unit including the light emitter31R that emits red light, a subpixel unit including a light emitter that emits orange, red-orange, red-violet, or violet light. Each pixel unit3may include, instead of the subpixel unit including the light emitter31G that emits green light, a subpixel unit including a light emitter that emits yellow-green light.

The power supply voltage feeder4is on the second surface2bof the substrate2. The power supply voltage feeder4includes a first power supply voltage terminal and a second power supply voltage terminal. The power supply voltage feeder4outputs a first power supply voltage VDD applicable to the pixel units3from the first power supply voltage terminal. The power supply voltage feeder4outputs a second power supply voltage VSS applicable to the pixel units3from the second power supply voltage terminal. The second power supply voltage VSS is lower in potential than the first power supply voltage VDD. The first power supply voltage VDD, which is a high-potential power supply voltage, is an anode voltage of, for example, about 10 to 15 V. The second power supply voltage VSS, which is a low-potential power supply voltage, is a cathode voltage of, for example, about 0 to 3 V.

The power supply voltage feeder4includes a control circuit for controlling the emission or non-emission state and the light intensity of the light emitters31. The power supply voltage feeder4may be, for example, a thin film circuit on the second surface2bof the substrate2. In this case, the thin film circuit may include, for example, a semiconductor layer including low-temperature polycrystalline silicon (LTPS) formed directly on the second surface2bby thin film deposition such as chemical vapor deposition (CVD). An IC chip may be mounted as a control circuit.

The display device1includes multiple scanning signal lines7arranged in each row in the matrix of the pixel units3. The display device1includes multiple emission control signal lines8arranged in each column in the matrix of the pixel units3. The scanning signal lines7and the emission control signal lines8are driven by the power supply voltage feeder4. Fifth areas25are located in edge portions along the first side2aaof the first surface2a. Multiple electrode pads71electrically connected to the corresponding scanning signal lines7are located in the fifth areas25. A sixth area26is located in an edge portion along one long side of the first surface2a. Multiple electrode pads81electrically connected to the corresponding emission control signal lines8are located in the sixth area26.

The first wiring conductor5is formed from a conductive material. The first wiring conductor5electrically connects the first power supply voltage terminal in the power supply voltage feeder4and the pixel units3. The first wiring conductor5includes multiple first side conductors51and multiple second side conductors52.

The first side conductors51are located in the first area21in the substrate2. The first side conductors51may be formed from a conductive paste including conductive particles of, for example, Ag, Cu, Al, or stainless steel, an uncured resin component, an alcohol solvent, and water. The conductive paste may be applied to intended portions in the first area21and cured by heating, photocuring using ultraviolet (UV) ray irradiation, or a combination of photocuring and heating. The first side conductors51may also be formed by plating or thin film deposition, such as vapor deposition or CVD. The third surface2cmay have grooves in the portions to receive the first side conductors51in advance. This allows the conductive paste that forms the first side conductors51to be easily received in the intended portions on the third surfaces2c.

The second side conductors52are located in the second area22in the substrate2. The material for the second side conductors52and the method of forming the second side conductors52are the same as the material for the first side conductors51and the method of forming the first side conductors51, and will not be described in detail.

The second wiring conductor6is formed from a conductive material. The second wiring conductor6electrically connects the second power supply voltage terminal in the power supply voltage feeder4and the pixel units3. The second wiring conductor6includes multiple third side conductors61and multiple fourth side conductors62.

The third side conductors61are located in the third area23in the substrate2. The material for the third side conductors61and the method of forming the third side conductors61are the same as the material for the first side conductors51and the method of forming the first side conductors51, and will not be described in detail.

The fourth side conductors62are located in the fourth area24in the substrate2. The material for the fourth side conductors62and the method of forming the fourth side conductors62are the same as the material for the first side conductors51and the method of forming the first side conductors51, and will not be described in detail.

In the display device1, the first wiring conductor5includes the first side conductors51in the first area21adjacent to the first side2aaof the substrate2and the second side conductors52in the second area22adjacent to the second side2abof the substrate2. The first side conductors51and the second side conductors52at both sides reduce the variation in the first power supply voltage VDD across the first surface2a. In the display device1, the second wiring conductor6includes the third side conductors61in the third area23adjacent to the first side2aaof the substrate2and the fourth side conductors62in the fourth area24adjacent to the second side2abof the substrate2. The third side conductors61and the fourth side conductors62at both sides reduce the variation in the second power supply voltage VSS across the first surface2a. The display device1thus reduces the variation in the potential difference between the first power supply voltage VDD and the second power supply voltage VSS across the first surface2a. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

In one example, the voltage distributions of the first power supply voltage VDD and the second power supply voltage VSS across the first surface2aof the display device1according to the present embodiment are determined by computer simulation. This simulation uses the substrate2having the first surface2awith a diagonal length of 9 inches. The substrate2includes 100 first side conductors51in the first area21, 100 second side conductors52in the second area22, 100 third side conductors61in the third area23, and 100 fourth side conductors62in the fourth area24. At a voltage of 15V applied as the first power supply voltage VDD and a voltage of 3V as the second power supply voltage VSS, the voltage distributions across the substrate are determined.

In a comparative example, a display device having the same structure as the display device1except for the absence of the second side conductors52and the fourth side conductors62is prepared, and the voltage distributions of the first power supply voltage VDD and the second power supply voltage VSS across the first surface2aof the display device are determined by simulation.

FIG.2Ashows the voltage distribution of the first power supply voltage VDD in the display device1in the example.FIG.2Bshows the voltage distribution of the second power supply voltage VSS in the display device1in the example.FIG.3Ashows the voltage distribution of the first power supply voltage VDD in the display device in the comparative example.FIG.3Bshows the voltage distribution of the second power supply voltage VSS in the display device in the comparative example. In the figures, the voltage distributions are shown by shading, with the shading levels expressed in a voltage range indicated on the left. InFIG.2A, the voltage value is 15.00 V at a high level and is 14.68 V at a low level, with a variation of 0.32 V in the distribution. Similarly, inFIG.2B, the voltage value is 3.959 V at a high level and is 3.008 V at a low level, with a variation of 0.951 V in the distribution. In the comparative example, the voltage value has a variation of 0.88 V as shown inFIG.3A, and the voltage value has a variation of 2.924 V as shown inFIG.3B.

The simulation results inFIGS.2A and3Ashow that the variation in the first power supply voltage VDD across the first surface2ais less in the display device1in the example than in the display device in the comparative example. The simulation results inFIGS.2B and3Bshow that the variation in the second power supply voltage VSS across the first surface2ais less in the display device1in the example than in the display device in the comparative example. This shows that the variation in the potential difference between the first power supply voltage VDD and the second power supply voltage VSS across the first surface2ais less in the display device1in the example than in the display device in the comparative example.

The structures of the first wiring conductor5, the second wiring conductor6, and the pixel units3in the display device1will now be described.

FIG.4Ais a schematic plan view of the first side conductor51, a first electrode pad53, and a second electrode pad54in the display device according to the embodiment of the present disclosure.FIG.4Bis a cross-sectional view taken along line A-A inFIG.4A.FIG.4Cis a cross-sectional view of the first side conductor51, the first electrode pad53, and the second electrode pad54in the display device according to the embodiment of the present disclosure.FIG.5Ais a plan view of a pixel unit in the display device according to the embodiment of the present disclosure.FIG.5Bis a cross-sectional view taken along line B-B inFIG.5A.FIG.5Cis a plan view of a first wiring pattern in the display device according to the embodiment of the present disclosure.FIG.5Dis a plan view of a third wiring pattern in the display device according to the embodiment of the present disclosure.

The first wiring conductor5includes, in addition to the first side conductors51and the second side conductors52, the multiple first electrode pads53, the multiple second electrode pads54, multiple third electrode pads55, multiple fourth electrode pads56, a first wiring pattern57, and a second wiring pattern58. As described later, the first wiring pattern57is on the first surface2a. The first wiring pattern57includes a planar conductive portion formed entirely on the area for the pixel units excluding the first area21, the second area22, the third area23, the fourth area24, the fifth areas25, and the sixth area26. The second wiring pattern58includes linear conductive portions on the second surface.

The first electrode pads53are located in the first area21on the first surface2a. The first electrode pads53are arranged along the first side2aaas shown in, for example,FIG.1A. The second electrode pads54are located in the first area21on the second surface2band overlap the corresponding first electrode pads53as viewed in plan.

A first electrode pad53on the first surface2aand a second electrode pad54on the second surface2boverlapping the first electrode pad53as viewed in plan are electrically connected with each other with a first side conductor51as shown in, for example,FIGS.4A and4B. The first electrode pads53are routed inward (rightward inFIGS.4B and4C) on the first surface2aand connected to the first wiring pattern57. The second electrode pads54are routed inward on the second surface2band connected to the second wiring pattern58. A lower insulating layer10of, for example, SiO2or Si3N4is located between the substrate2and the first electrode pads53as shown in, for example,FIG.4C. Components such as a control element for controlling the pixel units3and a wiring conductor may be located in the lower insulating layer10or between the substrate2and the lower insulating layer10.

The first electrode pad53and the second electrode pad54are formed from a conductive material. The first electrode pad53and the second electrode pad54may include a single metal layer, or multiple metal layers stacked on one another.FIG.4Cshows an example first electrode pad53including two metal layers53aand53bstacked on each other and an example second electrode pad54including a single metal layer.

The first electrode pad53and the second electrode pad54include, for example, Al, Al/Ti, Ti/Al/Ti, Mo, Mo/Al/Mo, MoNd/AlNd/MoNd, Cu, Cr, Ni, or Ag. The Al/Ti refers to a stack of a Ti layer on an Al layer. The same applies to the others.

The first electrode pad53and the second electrode pad54being a stack of multiple metal layers may partly include an insulating layer11between the metal layers as shown in, for example,FIG.4C. The first electrode pad53may include an insulating layer12at its inward end on the first surface2a, and the second electrode pad54may include an insulating layer13at its inward end on the first surface2aas shown in, for example,FIG.4C. This reduces the likelihood of short-circuiting between the first electrode pad53or the second electrode pad54and the wiring conductor located inward on the first surface2a. The insulating layers11,12, and13are formed from, for example, SiO2, Si3N4, or a polymeric material. The first electrode pad53and the second electrode pad54may have their surfaces coated with a transparent conductive layer17of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

The third electrode pads55are located in the second area22on the first surface2a. The fourth electrode pads56are located in the second area22on the second surface2band overlap the corresponding third electrode pads as viewed in plan.

A third electrode pad55on the first surface2aand a fourth electrode pad56on the second surface2boverlapping the third electrode pad55as viewed in plan are electrically connected with each other with a second side conductor52. The structures of the second side conductor52, the third electrode pad55, and the fourth electrode pad56are the same as the structures of the first side conductor51, the first electrode pad53, and the second electrode pad54, and will not be described in detail.

The first wiring pattern57electrically connects the pixel units3to the first electrode pads53and to the third electrode pads55. The first wiring pattern57includes a planar conductive portion formed on substantially the entire first surface2awithout the conductive portion in specific areas as shown in, for example,FIG.5C. The first wiring pattern57has openings in the areas for cathode pads33(described later) as shown inFIG.5C. The positive electrodes (anode electrodes) of the light emitters31are electrically connected to anode pads being parts of the first wiring pattern57. The negative electrodes (cathode electrodes) of the light emitters31are electrically connected to cathode pads in the openings in the first wiring pattern57. The anode pads and the cathode pads are electrically insulated from each other.

The second wiring pattern58electrically connects the power supply voltage feeder4to the second electrode pads54and to the fourth electrode pads56. The second wiring pattern58includes linear conductive portions on the second surface2bas shown in, for example,FIG.1B.

The first wiring pattern57and the second wiring pattern58include, for example, a single layer of Al or Ag or a multilayer of Mo/Al/Mo or MoNd/AlNd/MoNd.

The first wiring conductor5with the above structure can have a narrower resistance distribution with the wiring pattern including the planar conductive portion and can also input the voltage to the planar conductive portion from both sides, thus reducing the variation in the first power supply voltage VDD across the first surface2a. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

The second wiring conductor6includes, in addition to the third side conductors61and the fourth side conductors62, multiple fifth electrode pads63, multiple sixth electrode pads64, multiple seventh electrode pads65, multiple eighth electrode pads66, a third wiring pattern67, and a fourth wiring pattern68. The third wiring pattern67is on the first surface2a. The third wiring pattern67includes a planar conductive portion formed on the area for the pixel units excluding the first area21, the second area22, the third area23, the fourth area24, the fifth areas25, and the sixth area26. The fourth wiring pattern68includes linear conductive portions on the second surface. The third wiring pattern67is formed in a layer different from the layer for the first wiring pattern on the first surface2awith an insulating film between the layers.

The fifth electrode pads63are located in the third area23on the first surface2a. The fifth electrode pads63are arranged along the first side2aaas shown in, for example,FIG.1A. The sixth electrode pads64are located in the third area23on the second surface2band overlap the corresponding fifth electrode pads63as viewed in plan.

A fifth electrode pad63on the first surface2aand a sixth electrode pad64on the second surface2boverlapping the fifth electrode pad63as viewed in plan are electrically connected with each other with a third side conductor61. The structures of the third side conductor61, the fifth electrode pad63, and the sixth electrode pad64are the same as the structures of the first side conductor51, the first electrode pad53, and the second electrode pad54, and will not be described in detail.

The seventh electrode pads65are located in the fourth area24on the first surface2a. The seventh electrode pads65are arranged along the second side2abas shown in, for example,FIG.1A. The eighth electrode pads66are located in the fourth area24on the second surface2band overlap the corresponding seventh electrode pads65as viewed in plan.

A seventh electrode pad65on the first surface2aand an eighth electrode pad66on the second surface2boverlapping the seventh electrode pad65as viewed in plan are electrically connected with each other with a fourth side conductor62. The structures of the fourth side conductor62, the seventh electrode pad65, and the eighth electrode pad66are the same as the structures of the first side conductor51, the first electrode pad53, and the second electrode pad54, and will not be described in detail.

The third wiring pattern67electrically connects the pixel units3to the fifth electrode pads63and to the seventh electrode pads65. The third wiring pattern67includes a planar conductive portion formed on substantially the entire first surface2a. The third wiring pattern67has openings in the areas for receiving the light emitters31. The third wiring pattern67is nearer the first surface2alocated lower than the first wiring pattern57. The first wiring pattern57and the third wiring pattern67are insulated from each other with insulating layers14and15. The insulating layers14and15are formed from, for example, SiO2, Si3N4, or a polymeric material.

The fourth wiring pattern68electrically connects the power supply voltage feeder4to the sixth electrode pads64and to the eighth electrode pads66. The fourth wiring pattern68includes linear conductive portions on the second surface2bas shown in, for example,FIG.1B.

The third wiring pattern67and the fourth wiring pattern68include, for example, a single layer of Al or Ag or a multilayer of Mo/Al/Mo or MoNd/AlNd/MoNd.

The second wiring conductor6with the above structure can have a narrower resistance distribution with the wiring pattern including the planar conductive portion and can also input the voltage to the planar conductive portion from both sides, thus reducing the variation in the second power supply voltage VSS across the first surface2a. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

The pixel units3each include the light emitter31R that emits red light, the light emitter31G that emits green light, and the light emitter31B that emits blue light as shown in, for example,FIG.5A. Each pixel unit3thus enables display of color tones.

The light emitters31R,31G, and31B may be arranged in an L shape as viewed in plan as shown in, for example,FIG.5A. This allows the pixel unit3to be smaller as viewed in plan, and to be compact and square as viewed in plan. The display device1thus includes pixels with higher density, enabling high-quality image display.

The light emitter31includes a positive electrode (anode electrode)31aelectrically connected to an anode pad32being a part of the first wiring pattern57. The light emitter31includes a negative electrode (cathode electrode)31belectrically connected to a cathode pad33included in the same layer as the first wiring pattern57. The anode pad32and the cathode pad33are insulated from each other by the opening (cutout) around the cathode pad33in the first wiring pattern57. The cathode pad33is electrically connected to a first end34aof a routing wiring conductor34through a contact hole. The routing wiring conductors34are in the same layer as the third wiring pattern67. The third wiring pattern67and the routing wiring conductors34in the same layer are insulated from each other by cutouts around the routing wiring conductors34. A second end34bof the routing wiring conductor34is electrically connected to a source electrode of a TFT for electrically driving the light emitter31as described later. Although not shown, the third wiring pattern67is electrically connected to the source electrodes of the TFTs through contact holes in the lower insulating layer10and applies the power supply voltage VSS to the pixel units3.

The anode pad32and the cathode pad33may have their surfaces coated with the transparent conductive layer17of, for example, ITO or IZO. An insulating layer16of, for example, SiO2, Si3N4, or a polymeric material may be arranged around the anode pad32and the cathode pad33as shown in, for example,FIG.5B.

The display device1includes, on the first surface2aof the substrate2, the lower insulating layer10of an insulating material such as SiO2and Si3N4. The lower insulating layer10may include a single insulating layer, or multiple insulating layers stacked on one another. TFTs35are located between the substrate2and the lower insulating layer10as shown in, for example,FIG.5B.

The TFT35is, for example, an n-channel TFT and is used as a driving element for driving the light emitter with a current. The TFT35is a three-terminal element having a gate electrode35aas a gate terminal, a source electrode35bas a source terminal, and a drain electrode35cas a drain terminal. In the TFT35, the source electrode35bis electrically connected to the cathode pad33through a conductive connector36such as a through-hole as shown in, for example,FIG.5B. The gate electrode35ais electrically connected to a pixel node. The drain electrode35cis electrically connected to the second end34bof the routing wiring conductor34through a conductive connector such as a through-hole.

Example structures of the first to fourth areas in the display device according to the embodiment of the present disclosure will now be described.

The display device1includes the first area21apart from the third area23and the second area22apart from the fourth area24as shown in, for example,FIG.1A. This reduces the likelihood of short-circuiting between the first wiring conductor5and the second wiring conductor6. The display device can thus have improved reliability.

The display device1includes the first area21and the fourth area24apart from each other and the third area23and the second area22apart from each other as viewed in a direction orthogonal to the third surface2c, as shown in, for example,FIG.1A. Multiple display devices1may be arranged and tiled on the same plane. This can achieve a composite and large display device (hereafter also referred to as a multi-display). In this case, the third surface2cof one display device1and the fourth surface2dof another display device1may be connected together. This reduces the likelihood of short-circuiting between the first side conductors51and the fourth side conductors62and the likelihood of short-circuiting between the third side conductors61and the second side conductors52. The multi-display can thus have improved reliability.

The display device1may include the first area21overlapping the second area22and the third area23overlapping the fourth area24as viewed in the direction orthogonal to the third surface2c, as shown in, for example,FIG.1A. This structure facilitates routing of the second wiring pattern58and the fourth wiring pattern68on the second surface2bof the substrate2.

As shown in, for example,FIG.1A, the display device1may include the substrate2including a pair of fifth areas25in the edge portions along the first side2aaon the first surface2athat sandwich the first area21and the third area23in a direction along the first side2aa. The multiple electrode pads71electrically connected to the corresponding scanning signal lines7may be located in the pair of fifth areas25.

The first wiring conductor5applies the first power supply voltage VDD to the pixel units3. The second wiring conductor6applies the second power supply voltage VSS to the pixel units3. The first electrode pad53in the first wiring conductor5and the fifth electrode pad63in the second wiring conductor6may thus have larger surface areas than the electrode pad71electrically connected to the scanning signal line7to prevent heat from being generated or connection faults such as disconnection resulting from the heat in the first electrode pad53and the fifth electrode pad63. In this case, the first area21in which the first electrode pads53are located and the third area23in which the fifth electrode pads63are located are separated from the fifth areas25in which the electrode pads71are located. This allows the first electrode pads53, the fifth electrode pads63, and the electrode pads71to be efficiently located.

A display device according to another embodiment of the present disclosure will now be described.

FIG.6is a schematic plan view of the display device according to the other embodiment of the present disclosure. A display device1A according to the present embodiment basically has the same structure as the display device1in the embodiment described above except for the structure of the first to fourth areas. The same components will not be shown and will not be described in detail.

Similarly to the display device1, the display device1A includes a first area21and a third area23apart from each other and a second area22and a fourth area24apart from each other. Similarly to the display device1, the display device1A includes the first area21overlapping the second area22and apart from the fourth area24as viewed in a direction orthogonal to a third surface2c. Similarly to the display device1, the display device1A includes the third area23overlapping the fourth area24and apart from the second area22as viewed in the direction orthogonal to the third surface2c.

As shown in, for example,FIG.6, the display device1A includes the second area22having a greater length along a second side2abthan the length of the first area21along a first side2aa. This structure allows use of more third electrode pads than first electrode pads or allows adjacent third electrode pads to have a greater distance between them than the distance between adjacent first electrode pads. This effectively reduces the variation in a first power supply voltage VDD across a first surface2a. The electrode pad can be upsized. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

As shown in, for example,FIG.6, the display device1A includes the fourth area24with a greater length along the second side2abthan the length of the third area23along the first side2aa. This structure allows use of more seventh electrode pads than fifth electrode pads or allows adjacent seventh electrode pads to have a greater distance between them than the distance between adjacent fifth electrode pads. This effectively reduces the variation in a second power supply voltage VSS across the first surface2a. The electrode pad can be upsized. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

FIG.7is a schematic plan view of a display device according to another embodiment of the present disclosure. A display device1B according to the present embodiment basically has the same structure as the display device1in the embodiment described above except for the structure of the first to fourth areas. The same components will not be shown and will not be described in detail.

Similarly to the display device1, the display device1B includes a first area21and a third area23apart from each other and a second area22and a fourth area24apart from each other. Similarly to the display device1, the display device1B includes the first area21overlapping the second area22and apart from the fourth area24as viewed in a direction orthogonal to a third surface2c. Similarly to the display device1, the display device1B includes the third area23overlapping the fourth area24and apart from the second area22as viewed in the direction orthogonal to the third surface2c.

As shown in, for example,FIG.7, the display device1B may include the first area21including multiple first subareas21aand21band the third area23including multiple third subareas23aand23b. This structure allows first electrode pads53and fifth electrode pads63to be located dispersedly in a direction along a first side2aa. This effectively reduces the variation in a first power supply voltage VDD and a second power supply voltage VSS across a first surface2a. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality. The first subareas21aand21band the third subareas23aand23bmay be arranged alternately along the first side2aaas shown in, for example,FIG.7.

As shown in, for example,FIG.7, the display device1B includes the second area22including multiple second subareas22aand22band the fourth area24including multiple fourth subareas24aand24b. This structure allows third electrode pads55and seventh electrode pads65to be located dispersedly in a direction along a second side2ab. This effectively reduces the variation in the first power supply voltage VDD and the second power supply voltage VSS across the first surface2a. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality. The second subareas22aand22band the fourth subareas24aand24bmay be arranged alternately along the second side2abas shown in, for example,FIG.7.

FIG.8is a schematic plan view of a display device according to another embodiment of the present disclosure. A display device1C according to the present embodiment basically has the same structure as the display device1in the embodiment described above except for the structure of the first to fourth areas. The same components will not be shown and will not be described in detail.

Similarly to the display device1, the display device1C includes a first area21and a third area23apart from each other and a second area22and a fourth area24apart from each other. Similarly to the display device1, the display device1C includes the first area21apart from the fourth area24and the third area23apart from the second area22as viewed in a direction orthogonal to a third surface2c.

The display device1C includes the first area21and the second area22apart from each other and the third area23and the fourth area24apart from each other as viewed in the direction orthogonal to the third surface2c, as shown in, for example,FIG.8. This structure allows first electrode pads53and fifth electrode pads63to be located dispersedly in a direction along a first side2aaand allows third electrode pads and seventh electrode pads to be located dispersedly in a direction along a second side2ab. This effectively reduces the variation in a first power supply voltage VDD and a second power supply voltage VSS across a first surface2a, thus reducing the variation in the potential difference between the first power supply voltage VDD and the second power supply voltage VSS. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

A multi-display according to one embodiment of the present disclosure will now be described.

FIG.9is a schematic plan view of the multi-display according to the embodiment of the present disclosure.

A multi-display100according to the present embodiment includes multiple display devices1. The display devices1are arranged in a grid on the same plane with their first surfaces2afacing in the same direction. Adjacent display devices1are connected together with their side surfaces bonded with, for example, an adhesive. The display devices1include a first display device1and a second display device1. A third surface1cof the first display device1and a fourth surface1dof the second display device1are connected together.

The multi-display100including the multiple display devices1reduces the likelihood of unevenness in luminance and display, and can thus be a large multi-display with higher image quality. The multi-display100reduces the likelihood of short-circuiting between first side conductors51or second side conductors52in the first display device1and third side conductors61or fourth side conductors62in the second display device1, and can thus be highly reliable.

Although the multi-display100includes the multiple display devices1in the embodiment described above, the multi-display100may include multiple display devices1A, multiple display devices1B, or multiple display devices1C.

The present disclosure may be implemented in the following forms.

A display device according to one or more embodiments the present disclosure includes a plate-like substrate having a first surface and a second surface opposite to the first surface, a plurality of pixel units on the first surface, and a power supply voltage feeder on the second surface. The power supply voltage feeder outputs a first power supply voltage and a second power supply voltage applicable to the plurality of pixel units. The second power supply voltage is lower in potential than the first power supply voltage. The display device includes a first wiring conductor electrically connecting the power supply voltage feeder and the plurality of pixel units to apply the first power supply voltage to the plurality of pixel units and a second wiring conductor electrically connecting the power supply voltage feeder and the plurality of pixel units to apply the second power supply voltage to the plurality of pixel units. At least one of the first wiring conductor or the second wiring conductor includes a planar conductive portion covering the first surface. The planar conductive portion includes connectors connected to the power supply voltage feeder on at least two sides of the substrate.

The display device according to one or more embodiments of the present disclosure can reduce the variation in a potential difference between a high-potential power supply voltage and a low-potential power supply voltage. This can reduce the likelihood of unevenness in luminance and display, thus improving the image quality.

INDUSTRIAL APPLICABILITY

Although the embodiments of the present disclosure have been described in detail, the present disclosure is not limited to the embodiments described above, and may be changed or modified in various manners without departing from the spirit and scope of the present disclosure. The components described in the above embodiments may be entirely or partially combined as appropriate unless any contradiction arises. The display device according to one or more embodiments of the present disclosure can be used in various electronic devices. Such electronic devices include, for example, composite and large display devices (multi-displays), automobile route guidance systems (car navigation systems), ship route guidance systems, aircraft route guidance systems, smartphones, mobile phones, tablets, personal digital assistants (PDAs), video cameras, digital still cameras, electronic organizers, electronic dictionaries, personal computers, copiers, terminals for game devices, television sets, product display tags, price display tags, programmable display devices for industrial use, car audio systems, digital audio players, facsimile machines, printers, automatic teller machines (ATMs), vending machines, digital display watches, and smartwatches.

REFERENCE SIGNS LIST