Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming an inductor within an interconnect layer with vertical separation from a semiconductor die.

BACKGROUND OF THE INVENTION

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

Another goal of semiconductor manufacturing is to produce higher performance semiconductor devices. Increases in device performance can be accomplished by forming active components that are capable of operating at higher speeds. In high frequency applications, such as radio frequency (RF) wireless communications, integrated passive devices (IPDs) are often contained within the semiconductor device. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions.

The inductor can be formed within the semiconductor die. However, integrated die inductors often suffer with low Q factor, due in part to eddy current losses. The integrated inductors consume considerable die area and reduce design flexibility.

SUMMARY OF THE INVENTION

A need exists for a high Q factor inductor within a semiconductor device. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, forming an adhesive layer over the carrier, providing a semiconductor die having a plurality of bumps formed over an active surface of the semiconductor die, mounting the semiconductor die to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer, depositing an encapsulant over the semiconductor die and within the gap between the semiconductor die and adhesive layer, removing the carrier and adhesive layer to expose the bumps from the encapsulant, forming an insulating layer over the encapsulant, and forming a first conductive layer over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The first conductive layer has a separation from the semiconductor die as determined by the encapsulant within the gap and the insulating layer.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, providing a semiconductor die, forming a first insulating layer over a surface of the semiconductor die, leading with the first insulating layer, mounting the semiconductor die to the carrier, depositing an encapsulant over the semiconductor die, removing the carrier, forming a second insulating layer over the semiconductor die, and forming a first conductive layer over the second insulating layer in a wound configuration to exhibit inductive properties. The first conductive layer has a separation from the semiconductor die as determined by the first and second insulating layers.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die, forming a first insulating layer over a first surface of the semiconductor die, depositing an encapsulant over a second surface of the semiconductor die opposite the first surface, forming a second insulating layer over the first surface of the semiconductor die, and forming a first conductive layer over the second insulating layer in a wound configuration to exhibit inductive properties. The first conductive layer has a separation from the semiconductor die.

In another embodiment, the present invention is a semiconductor device comprising a semiconductor die and first insulating layer formed over a first surface of the semiconductor die. An encapsulant is deposited over a second surface of the semiconductor die opposite the first surface. A second insulating layer is formed over the first surface of the semiconductor die. A first conductive layer is formed over the second insulating layer in a wound configuration to exhibit inductive properties. The first conductive layer has a separation from the semiconductor die.

DETAILED DESCRIPTION OF THE DRAWINGS

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50may be a subcomponent of a larger system. For example, electronic device50may be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. The miniaturization and the weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including wire bond package56and flip chip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and wire bonds82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74or wire bonds82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Wire bonds94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and wire bonds94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flip chip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flip chip style first level packaging without intermediate carrier106.

FIG. 3ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by saw streets126as described above.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back surface128and active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die124is a flipchip type semiconductor die.

An electrically conductive layer132is formed over active surface130using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer132can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer132operates as contact pads electrically connected to the circuits on active surface130. Bumps134are formed on contact pads132.

InFIG. 3c, semiconductor wafer120is singulated through saw street126using a saw blade or laser cutting tool136into individual semiconductor die124.

FIGS. 4a-4killustrate, in relation toFIGS. 1 and 2a-2c, a process of forming an inductor within an interconnect layer with vertical separation from a semiconductor die.FIG. 4ashows a substrate or carrier140containing temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape142is formed over carrier140as a temporary adhesive bonding film or etch-stop layer. A penetrable adhesive layer144is formed over interface layer142. In one embodiment, penetrable adhesive layer144is a B-stage material.

InFIG. 4b, semiconductor die124fromFIGS. 3a-3cis positioned over and mounted to carrier140using a pick and place operation. Bumps134are partially embedded within adhesive layer144to leave a gap145between semiconductor die124and adhesive layer144, as shown inFIG. 4c. In one embodiment, semiconductor die124contains an electrically conductive layer146(later used as an inductor bridge) and analog and digital circuits148as part of active surface130, as described inFIG. 3b.

InFIG. 4d, an encapsulant or molding compound152is deposited over semiconductor die124and adhesive layer144using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant152extends between semiconductor die124and adhesive layer144. In one embodiment, encapsulant152is injected under pressure from a dispensing needle into gap145between semiconductor die124and adhesive layer144around bumps134using a mold underfill (MUF) process. A vacuum assist can draw encapsulant152to aid with uniform distribution. Encapsulant152can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant152is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Due to the gap145between semiconductor die124and adhesive layer144, the thickness of encapsulant152under the semiconductor die124is 15-90 micrometers (μm).

FIG. 4eshows an optional back grinding operation with a portion of surface154of encapsulant152removed by grinder156to planarize the encapsulant and expose back surface128of semiconductor die124for electrostatic discharge (ESD) control.

InFIG. 4g, an insulating or dielectric layer158is formed over surface160of encapsulant152, opposite surface154, using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer158contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. The insulating layer158has a thickness of 5-50 μm. A portion of insulating layer158is removed to expose bumps134.

InFIG. 4h, an electrically conductive layer162is conformally applied over insulating layer158and exposed bump134using a patterning and metal deposition process such as PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer162can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer162can be a seed layer following the contour of insulating layer158, including into the removed portion of the insulating layer and around exposed bumps134. In another embodiment, conductive layer162is a multi-metal stack with adhesion layer, barrier layer, and seed or wetting layer. The adhesion layer is formed over insulating layer158and bumps134and can be titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer is formed over the adhesion layer and can be Ni, NiV, platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). The barrier layer inhibits the diffusion of Cu into the active area of the die. The seed layer is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al.

An insulating or photoresist layer164is formed over conductive layer162. A portion of insulating layer164is removed by an etching process to pattern conductive layer166a-166h. An electrically conductive material is deposited in the removed portions of insulating layer164by electrolytic plating, electroless plating, or other suitable metal deposition process. The remaining insulating layer164and conductive layer162below the insulating layer are removed by an etching process leaving conductive layer166a-166has one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material, as shown inFIG. 4i. Conductive layer166a-166hcan be electrically common or electrically isolated depending on the design and function of semiconductor die124.

The individual sections of conductive layer166can be wound or coiled in plan-view to produce or exhibit inductive properties. For example, conductive layer166d,166e,166f, and166gconstitute wound or spiral inductor wings, as shown inFIG. 4j. The inductor wings166d-166gare disposed within an interconnect layer partially or completely within a footprint of semiconductor die124. The inductor wings166d-166gare electrically connected through conductive layer162, bump134, and contact pad132to conductive layer146, which operates as an inductor bridge to electrically connect the inductor wings to analog and digital circuit148. Due to the thickness of encapsulant152under semiconductor die124(15-90 μm) and thickness of insulating layer158(5-50 μm), inductor wings166d-166gare separated from semiconductor die124by 20-140 μm. In one embodiment, inductor wings166d-166gare separated from semiconductor die124by 100 μm. The gap between inductor wings166d-166gand semiconductor die124reduces eddy current losses and increases Q factor.

InFIG. 4k, an insulating or passivation layer168is formed over insulating layer158and conductive layer166using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer168contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer168is removed to expose conductive layer166a,166c, and166h.

An electrically conductive bump material is deposited over the exposed conductive layer166a,166c, and166husing an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer166using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps170. In some applications, bumps170are reflowed a second time to improve electrical contact to conductive layer166. The bumps can also be compression bonded to conductive layer166. Bumps170represent one type of interconnect structure that can be formed over conductive layer166. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

FIGS. 5a-5fshow another embodiment with substrate or carrier172containing temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support. InFIG. 5a, an interface layer or double-sided tape173is formed over carrier172as a temporary adhesive bonding film or etch-stop layer.

A plurality of semiconductor die174is provided in wafer form, similar toFIG. 3a. Each semiconductor die174has a back surface178and active surface180containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface180to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die174may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer182is formed over active surface180using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer182can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer182is used later as an inductor bridge to analog and digital circuits188as part of active surface180.

An electrically conductive layer192is formed over insulating layer190using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer192can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer192is electrically connected to conductive layer182and analog and digital circuits188.

A conductive plug196is formed on192and190, by Cu plating, solder ball attach, or wire bonding. An insulating or dielectric layer194is formed over insulating layer190and conductive layer192, and expose conductive plug196, prior to dicing while in wafer form, seeFIGS. 3a-3b, using PVD, CVD, screen printing, spin coating, spray coating, lamination, molding, sintering or thermal oxidation. The insulating layer194contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. In one embodiment, insulating layer194has a thickness of 15-90 μm and contains high resistivity material, such as a polymer material with filler.

Alternatively, a plurality of vias is formed through insulating layer194prior to dicing while in wafer form using laser drilling, mechanical drilling, or deep reactive ion etching (DRIE). The vias extend down to conductive layer192. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect conductive plug196. Conductive plugs196are electrically connected to conductive layer192. Conductive layer192provides alignment tolerance for conductive plugs196.

After dicing the semiconductor wafer, similar toFIG. 3c, semiconductor die174is positioned over and mounted to carrier172and interface layer173using a pick and place operation. The insulating layer194provides a spacing or separation198of 15-90 μm between semiconductor die174and interface layer173, as shown inFIG. 5b.

InFIG. 5c, an encapsulant or molding compound200is deposited over semiconductor die174and interface layer173using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant200can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant200is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

A portion of surface202of encapsulant200can be removed in an optional back grinding operation, similar toFIG. 4e, to planarize the encapsulant and expose back surface178of semiconductor die174for ESD control.

An insulating or dielectric layer204is formed over surface205of encapsulant200, opposite surface202, using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer204contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. The insulating layer204has a thickness of 5-50 μm. A portion of insulating layer204is removed to expose conductive plugs196.

InFIG. 5e, an electrically conductive layer206is formed over insulating layer204as segments206a-206hby electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer206a-206hcontains one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer206a-206hcan be electrically common or electrically isolated depending on the design and function of semiconductor die174.

The individual sections of conductive layer206can be wound or coiled in plan-view to produce or exhibit inductive properties. For example, conductive layer206d,206e,206f, and206gconstitute wound or spiral inductor wings, similar toFIG. 4j. The inductor wings206d-206gare disposed within an interconnect layer partially or completely within a footprint of semiconductor die174. The inductor wings206d-206gare electrically connected through conductive plugs196and conductive layer192to conductive layer182, which operates as an inductor bridge to electrically connect the inductor wings to analog and digital circuits188. Due to the thickness of insulating layer194(15-90 μm) and thickness of insulating layer204(5-50 μm), inductor wings206d-206gare separated from semiconductor die174by 20-140 μm. In one embodiment, inductor wings206d-206gare separated from semiconductor die174by 100 μm. The separation between inductor wings206d-206gand semiconductor die174reduces eddy current losses and increases Q factor.

InFIG. 5f, an insulating or passivation layer208is formed over insulating layer204and conductive layer206using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer208contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer208is removed to expose conductive layer206a,206c, and206h.

An electrically conductive bump material is deposited over the exposed conductive layer206a,206c, and206husing an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer206using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps210. In some applications, bumps210are reflowed a second time to improve electrical contact to conductive layer206. The bumps can also be compression bonded to conductive layer206. Bumps210represent one type of interconnect structure that can be formed over conductive layer206. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

FIGS. 6a-6gshow another embodiment with substrate or carrier212contains temporary or sacrificial base material such as silicon, polymer, beryllium oxide, or other suitable low-cost, rigid material for structural support. InFIG. 6a, an interface layer or double-sided tape213is formed over carrier212as a temporary adhesive bonding film or etch-stop layer.

A plurality of semiconductor die214is provided in wafer form, similar toFIG. 3a. Each semiconductor die214has a back surface218and active surface220containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface220to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die214may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer222is formed over active surface220using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer222can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer222is used later as an inductor bridge to analog and digital circuits228as part of active surface220.

An electrically conductive layer232is formed over insulating layer230using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer232can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer232is electrically connected to conductive layer222.

A sacrificial layer234is formed over insulating layer230and conductive layer232prior to dicing while in wafer form, seeFIG. 3a-3b. The sacrificial layer234contains one or more layers of dry film and back grinding tape, liquid photo resist, or protection paste. In one embodiment, the thickness of insulating layer234is 15-90 μm.

After dicing the semiconductor wafer, similar toFIG. 3c, semiconductor die214is positioned over and mounted to carrier212and interface layer213using a pick and place operation. The sacrificial layer234provides a spacing or separation238of 15-90 μm between semiconductor die214and interface layer213, as shown inFIG. 6b.

InFIG. 6c, an encapsulant or molding compound240is deposited over semiconductor die214and interface layer213using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant240can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant240is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

A portion of surface242of encapsulant240can be removed in an optional back grinding operation, similar toFIG. 4e, to planarize the encapsulant and expose back surface218of semiconductor die214for ESD control.

InFIG. 6e, an insulating or dielectric layer252is formed over surface254of encapsulant240, opposite surface242, and into cavity246using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer252contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. In one embodiment, insulating layer252is deposited as a single or double layer dielectric material. The insulating layer252has a thickness of 5-50 μm. A portion of insulating layer252is removed to expose conductive layer232.

InFIG. 6f, an electrically conductive layer256is formed over insulating layer252as segments256a-256hby electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer256a-256hcontains one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. For example, conductive layer256may include a seed layer of Ti/Cu or TiW/Cu with selective Cu plating followed by seed layer wet etching. Conductive layer256band256fextends into the removed portion of insulating layer252to contact conductive layer232. Conductive layer256a-256hcan be electrically common or electrically isolated depending on the design and function of semiconductor die214.

The individual sections of conductive layer256can be wound or coiled in plan-view to produce or exhibit inductive properties. For example, conductive layer256d,256e,256f, and256gconstitute wound or spiral inductor wings, similar toFIG. 4j. The inductor wings256d-256gare disposed within an interconnect layer partially or completely within a footprint of semiconductor die214. The inductor wings256d-256gare electrically connected through conductive layer232to conductive layer222, which operates as an inductor bridge to electrically connect the inductor wings to analog and digital circuits228. Due to the thickness of thickness of insulating layer252, inductor wings256d-256gare separated from semiconductor die214by 25-160 μm. In one embodiment, inductor wings256d-256gare separated from semiconductor die214by 120 μm. The separation between inductor wings256d-256gand semiconductor die214reduces eddy current losses and increases Q factor.

InFIG. 6g, an insulating or passivation layer258is formed over insulating layer252and conductive layer256using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer258contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer258is removed to expose conductive layer256a,256c, and256h.

An electrically conductive bump material is deposited over the exposed conductive layer256a,256c, and256husing an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer256using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps260. In some applications, bumps260are reflowed a second time to improve electrical contact to conductive layer256. The bumps can also be compression bonded to conductive layer256. Bumps260represent one type of interconnect structure that can be formed over conductive layer256. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

FIGS. 7a-7eshows another embodiment, continuing fromFIG. 6d, with cavity246exposing semiconductor die214by stripping sacrificial protection layer234. An electrically conductive bump material is deposited over the exposed conductive layer232within cavity246while in wafer form using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process, as shown inFIG. 7a. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer232using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps270. In some applications, bumps270are reflowed a second time to improve electrical contact to conductive layer232. The bumps can also be compression bonded to conductive layer232. Bumps270represent one type of interconnect structure that can be formed over conductive layer232. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

FIG. 7bshows an embodiment with backgrinding tape262and protection liner264formed over bumps270and insulating layer230while in wafer form. In one embodiment, tape262can be a thermal resistant resin. The backgrinding tape262and protection liner264provide structural support during backgrinding and dicing operations, such as shown inFIGS. 3cand4e.

InFIG. 7c, an insulating or dielectric layer272is formed over surface274of encapsulant240, opposite surface242, and into cavity246over bumps270using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer272contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. In one embodiment, insulating layer272is deposited as a single or double layer dielectric material. The insulating layer272has a thickness of 5-50 μm. A portion of insulating layer272is removed to expose bumps270.

InFIG. 7d, an electrically conductive layer276is formed over insulating layer272as segments276a-276hby electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer276a-276hcontains one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. For example, conductive layer276may include a seed layer of Ti/Cu or TiW/Cu with selective Cu plating followed by seed layer wet etching. Conductive layer276band276fextends into the removed portion of insulating layer272to contact bumps270. Conductive layer276a-276hcan be electrically common or electrically isolated depending on the design and function of semiconductor die214.

The individual sections of conductive layer276can be wound or coiled in plan-view to produce or exhibit inductive properties. For example, conductive layer276d,276e,276f, and276gconstitute wound or spiral inductor wings, similar toFIG. 4j. The inductor wings276d-276gare disposed within an interconnect layer partially or completely within a footprint of semiconductor die214. The inductor wings276d-276gare electrically connected through bumps270and conductive layer232to conductive layer222, which operates as an inductor bridge to electrically connect the inductor wings to analog and digital circuits228. Due to the thickness of insulating layer272, inductor wings276d-276gare separated from semiconductor die214by 25-160 μm. In one embodiment, inductor wings276d-276gare separated from semiconductor die214by 120 μm. The separation between inductor wings276d-276gand semiconductor die214reduces eddy current losses and increases Q factor.

InFIG. 7e, an insulating or passivation layer278is formed over insulating layer272and conductive layer276using PVD, CVD, screen printing, spin coating, spray coating, sintering or thermal oxidation. The insulating layer278contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer278is removed to expose conductive layer276a,276c, and276h.

An electrically conductive bump material is deposited over the exposed conductive layer276a,276c, and276husing an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer276using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps280. In some applications, bumps280are reflowed a second time to improve electrical contact to conductive layer276. The bumps can also be compression bonded to conductive layer276. Bumps280represent one type of interconnect structure that can be formed over conductive layer276. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.