Bridge interconnect with air gap in package assembly

Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

FIELD

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly.

BACKGROUND

Integrated circuit (IC) product architecture has evolved to incorporate a number of heterogeneous functions such as central processing unit (CPU) logic, graphics functions, cache memory and other system functions to create integrated system-on-chip (SOC) designs, which may lower product design complexity and number of components for each product. Previously, products may have required that an end customer design a system board using separate packages for the different functions, which may increase a system board area, power loss, and, thus, cost of an integrated solution.

Emerging multichip package substrate solutions may provide chip-to-chip interconnection structures to address the issues above. Electrical performance of current chip-to-chip interconnect solutions may be adversely affected by electrical resistivity of an interconnection substrate that is too low and a dielectric constant of dielectric materials adjacent to electrically conductive features of the interconnection that is too high.

DETAILED DESCRIPTION

In various embodiments, the phrase “a first layer formed, deposited, or otherwise disposed on a second layer,” may mean that the first layer is formed, deposited, or disposed over the second layer, and at least a part of the first layer may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other layers between the first layer and the second layer) with at least a part of the second layer.

FIG. 1schematically illustrates a cross-section side view of an example integrated circuit (IC) package assembly100including an embedded bridge interconnect assembly (hereinafter “bridge106” or “bridge108”), in accordance with some embodiments. The IC package assembly100may include a package substrate104having a plurality (e.g., two or more) of dies102mounted on the package substrate104. The dies102can be attached to the package substrate104according to a variety of suitable configurations including, a flip-chip configuration, as depicted, or other configurations such as wirebonding and the like. In the flip-chip configuration, an active side of the dies102is attached to a surface of the package substrate104using die interconnect structures110such as bumps or pillars, as can be seen. The active side of the dies102may have one or more transistor devices formed thereon. Each of the dies102may represent a discrete chip. The dies102may be, include, or be a part of a processor, memory, or application specific integrated circuit (ASIC) in some embodiments.

The die interconnect structures110may be configured to route electrical signals between the dies102and the package substrate104. In some embodiments, the die interconnect structures110may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the dies102.

The package substrate104may include electrical routing features configured to route electrical signals to or from the dies102. The electrical routing features may be internal and/or external to the bridge106or108. For example, in some embodiments, the package substrate104may include electrical routing features such as pads or traces (not shown) configured to receive the die interconnect structures110and route electrical signals to or from the dies102. Package level interconnects112such as, for example, solder balls, may be coupled to a surface of the package substrate104to further route the electrical signals to other electrical devices (e.g., motherboard or other chipset). In some embodiments, the package substrate104is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate104may include other suitable types of substrates in other embodiments.

In some embodiments, the dies102are electrically coupled with a bridge106or108that is configured to route electrical signals between the dies102. The bridge106or108may be a dense interconnect structure that provides a route for electrical signals. The bridge106or108may include a bridge substrate composed of glass or a semiconductor material (e.g., high resistivity silicon) having electrical routing features formed thereon to provide a chip-to-chip connection between the dies102. The bridge106or108may be composed of other suitable materials in other embodiments.

The bridges106,108may be embedded in a cavity of the package substrate104in some embodiments. The bridge106or108may comport with embodiments described in connection with other figures herein. For example, in some embodiments, the bridge106or108may include an air gap to serve as a dielectric material between electrical routing features of the bridge106or108. In some embodiments, a portion of the dies102may overly the embedded bridge106or108, as can be seen.

Although three dies102and two bridges106,108are depicted in connection withFIG. 1, other embodiments may include more or fewer dies and bridges connected together in other possible configurations including three-dimensional configurations. For example, another die that is disposed on the package substrate104in or out of the page relative to the dies102ofFIG. 1may be coupled to the dies102using another bridge.

FIG. 2schematically illustrates a top view of the example integrated circuit (IC) package assembly100ofFIG. 1, in accordance with some embodiments. A bridge (e.g., bridge106or108) may be disposed between each of the dies102. In some embodiments, a bridge may be disposed between some dies on the package substrate104and not between other dies.

Dashed lines indicate an example boundary of the bridges106,108underlying the dies102. In some embodiments, the bridges106,108may not be visible from a top view. Intervening materials or layers may be formed on the bridges106,108in some embodiments. Line AB depicts an example cross-section configuration as described in connection withFIGS. 3 and 6.

FIG. 3schematically illustrates a cross-section side view of the example IC package assembly100ofFIG. 2showing a configuration300of a bridge interconnect assembly (hereinafter “bridge306”), in accordance with some embodiments. The configuration300may schematically represent a cross-section side view of the IC package assembly100ofFIG. 2along line AB. The dies102are omitted from the view for the sake of clarity. The bridge306is demarcated with a dashed line to depict an approximate boundary of the bridge306(e.g., components of the bridge306prior to embedding in the package substrate104). The configuration300may represent only a portion of the package substrate104(e.g., top layers of the package substrate104).

The bridge306includes a bridge substrate314, which may be composed of a high resistivity/low conductivity material such as, for example, glass or semiconductor material such as silicon. One or more electrical routing features may be formed on and through the bridge substrate314. In some embodiments, one or more through hole vias (THVs)316are formed through the bridge substrate314, as can be seen, to provide an electrical pathway between opposing surfaces (e.g., surfaces S1and S2) of the bridge substrate314. In an embodiment where the bridge substrate314is composed of glass, the one or more THVs316may be through glass vias (TGVs) and in an embodiment where the bridge substrate314is composed of silicon, the one or more THVs316may be through silicon vias (TSVs). In embodiments where the bridge substrate314is composed of low temperature co-fired ceramic (LTCC), the THVs316may be through ceramic vias (TCVs).

Additional electrical routing features such as, for example, pads or traces and the like (referred to generally as “surface routing features318”) may be formed on surfaces (e.g., surfaces S1and S2) of the bridge substrate314to route the electrical signals between dies (e.g., dies102ofFIG. 1) on the package substrate104. For example, the surface routing features318may be electrically coupled with package routing features formed in the package substrate104such as, for example, vias320, pads322, or other routing structure such as trenches or traces. The package routing features (e.g., vias320, pads322, and the like) may be configured to be electrically coupled with the dies (e.g., dies102ofFIG. 1). The surface routing features318on surface S1may be electrically coupled with the one or more THVs316to route electrical signals sent between the dies through the vias320over the THVs316to surface routing features318formed on surface S2of the bridge substrate314.

According to various embodiments, electrically conductive interconnect structures (e.g., one or more THVs316, surface routing features318, vias320, pads322) of the configuration300are patterned with a first hatching (e.g., indicated by324) to indicate that such marked interconnect structures are configured to route I/O signals and patterned with a second hatching (e.g., indicated by326) that is perpendicular to the first hatching to indicate that such marked interconnect structures are configured to route power and/or ground signals. In some embodiments, the second hatching (e.g.,326) indicates routing for ground signals. The electrically conductive structures may be composed of any suitable material including metals such as copper.

In some embodiments, the surface routing features318(e.g., ground pads) with the second hatching (e.g.,326) may be electrically coupled with a ground plane328that is configured to provide a ground signal. The ground plane328may be electrically and physically coupled with the surface routing features318on the surface S2of the bridge substrate314using an interconnect structure such as, for example, a solder bond330(e.g., solder bump) or pillar. The ground plane328may be configured to route the ground signal to one or both of the dies (e.g., dies102ofFIG. 1) through the one or more THVs316.

According to various embodiments, the bridge306may include an air gap332disposed between surface S2of the bridge substrate314and the ground plane328, as can be seen. The air gap332may provide air as a dielectric material between surface routing features318configured to route I/O signals and the ground plane328. The air gap332may further provide air as a dielectric material between adjacent surface routing features318on the surface S2, as can be seen. The air gap332may have a lower dielectric constant than other dielectric materials and may increase electrical performance of the bridge306by, e.g., reducing a capacitance of the routing features318. The interconnect structure (e.g., solder bond330) that is formed to connect the ground plane328with the surface routing features318may be formed to control a distance of the air gap332between the surface S2of the bridge substrate314and the ground plane328and, thus, control a distance between surface routing features318and the ground plane328. In some embodiments, a distance of the air gap between the surface S2and the ground plane328may range from 3 microns to 5 microns. The distance may have other values in other embodiments.

In some embodiments, the bridge306may further include a strengthening layer334coupled with the ground plane328. The strengthening layer334may be composed of any suitable material that lends structural integrity to the ground plane328during manufacturing process that forms the air gap332. The strengthening layer334may include, for example, solder, metal (e.g. Cu, Ni, Au formed by electroplating), or silicon (Si) (e.g., wafer).

The bridge306may be placed in a cavity formed in the package substrate104to provide the embedded bridge306as depicted in the configuration300ofFIG. 3. In some embodiments, a suitable adhesive (e.g., die attach adhesive) may be applied to surfaces of the bridge substrate314to couple material of the bridge substrate314with material (e.g., epoxy material) of the package substrate104. A solder reflow or electroplating process may be performed to couple surface routing features318of the bridge306with package routing structures (e.g., vias320and the like). In some embodiments, the bridge306may be exposed instead of being fully embedded inside the package substrate104as depicted. For example, the vias320may not be used in some embodiments and the bridge306may be mounted on a surface of the package substrate104using any suitable surface mounting technique or partially embedded in the package substrate104using techniques described herein for the fully embedded bridge306.

A finishing layer336(e.g., die backside film) may be formed on the strengthening layer334, as can be seen, to enhance adhesion between the bridge306and the package substrate104or control the depth by which the bridge306is embedded into the package substrate104. In some embodiments, the finishing layer336may be composed of an epoxy material. The finishing layer336may include multiple layers or other materials in other embodiments. In embodiments where a strengthening layer334is not used, the finishing layer336may be formed on the ground plane328. In some embodiments, a finishing layer336may not be used at all (e.g., exposed bridge306).

FIG. 4schematically illustrates a bottom view of an arrangement400of routing features (e.g., surface routing features318ofFIG. 3) on a bridge interconnect assembly (e.g., bridge306ofFIG. 3), in accordance with some embodiments. The arrangement400may represent the surface S2of the bridge substrate314in the configuration300ofFIG. 3, in some embodiments.

The routing features of the arrangement400include ground pads438, I/O vias440and I/O traces442, configured as can be seen. The ground pads438may be configured to form a grounding connection with the ground plane (e.g., ground plane328ofFIG. 3), structurally support the bridge (e.g., bridge306ofFIG. 3) and control an air gap (e.g., air gap332ofFIG. 3) distance. The I/O vias440and I/O traces442may route I/O signals between the dies (e.g., dies102ofFIG. 1). The I/O vias440and I/O traces442are marked with the first hatching (e.g., indicated at324ofFIG. 3) to indicate routing for I/O signals and the ground pads438are marked with the second hatching (e.g., indicated at326ofFIG. 3) to indicate routing for the ground signal.

The ground pads438may be configured to surround the I/O vias440and the I/O traces442, as can be seen. Such arrangement400may provide additional shielding effects on I/O traces442in addition to the ground plane (e.g., ground plane328ofFIG. 3), and also provide even mechanical support to the bridge (e.g., bridge306ofFIG. 3).

FIG. 5schematically illustrates a bottom view of another arrangement500of routing features (e.g., surface routing features318ofFIG. 3) on a bridge interconnect assembly (e.g., bridge306ofFIG. 3), in accordance with some embodiments. The arrangement500may represent the surface S2of the bridge substrate314in the configuration300ofFIG. 3, in some embodiments.

The routing features of the arrangement500include ground pads438, I/O vias440and I/O traces442, configured as can be seen. The ground pads438may be configured to form a grounding connection with the ground plane (e.g., ground plane328ofFIG. 3), structurally support the bridge (e.g., bridge306ofFIG. 3) and control an air gap (e.g., air gap332ofFIG. 3) distance. The I/O vias440and I/O traces442may route I/O signals between the dies (e.g., dies102ofFIG. 1). The I/O vias440and I/O traces442are marked with the first hatching (e.g., indicated at324ofFIG. 3) to indicate routing for I/O signals and the ground pads438are marked with the second hatching (e.g., indicated at326ofFIG. 3) to indicate routing for the ground signal.

The ground pads438may be configured in a row or other array along opposite edges of the bridge substrate314with a row of ground pads438positioned between groups of I/O traces442across a center portion of the bridge substrate314, as can be seen. Such arrangement500may provide additional shielding effects to separate the I/O traces442(e.g., by separating I/O traces442of the of the upper group and the I/O traces442of the lower group). The arrangements400and500may depict an orientation of the bridge substrate314where a first die may be coupled with a left side of the arrangement400or500and a second die may be coupled with a right side of the arrangement400or500. The I/O traces442may extend in a lengthwise direction (left and right on the page) towards each of the first die and the second die.

FIG. 6schematically illustrates a cross-section side view of the example IC package assembly100ofFIG. 2showing another configuration of a bridge interconnect assembly (hereinafter “bridge606”), in accordance with some embodiments. The configuration600may schematically represent a cross-section side view of the IC package assembly100ofFIG. 2along line AB. The dies102are omitted from the view for the sake of clarity. The bridge606is demarcated with a dashed line to depict an approximate boundary of the bridge606(e.g., components of the bridge606prior to embedding in the package substrate104). The configuration600may represent only a portion of the package substrate104(e.g., top layers of the package substrate104).

The bridge606may include bridge substrate314coupled with bridge substrate614using one or more interconnect structures such as, a solder bond330(e.g., solder bump or pillar). The solder bond330may be formed to control a distance of an air gap332between the bridge substrates314and614. The air gap may provide a dielectric material between surface routing features318and618(e.g., pads, traces and the like) formed on respective adjacent surfaces of the bridge substrate314and614. Using air as a dielectric material between the surface routing features318and618may enhance electrical performance of the bridge606by reducing capacitance between traces. The bridge substrates314and614may comport with embodiments described in connection with the bridge substrate314ofFIG. 3unless otherwise indicated.

Routing features of the I/O signals are patterned with first hatching indicated by324and routing features of the power and/or ground signals are patterned with second hatching indicated by326. In some embodiments, the configuration600ofFIG. 6includes a different configuration for routing of I/O signals and routing power and/or ground signals compared with the configuration300ofFIG. 3. As can be seen, the surface routing features318and the surface routing features618are configured in a staggered arrangement to provide ground shielding from cross-talk of I/O signals. In some embodiments, each of the surface routing features318and618that is configured to route I/O signals is positioned adjacent to a surface routing feature318and618that is configured to route ground signals in at least two dimensions (e.g., up/down and left/right on page ofFIG. 6). In some embodiments, surface routing features318and618on the bridge substrate314and614are configured to route both I/O signals and ground signals. Such configuration to provide coaxial routing may improve electrical performance of the bridge606.

In some embodiments, the bridge606may be exposed instead of being fully embedded inside the package substrate104as depicted. For example, the vias320may not be used in some embodiments and the bridge606may be mounted on a surface of the package substrate104using any suitable surface mounting technique or partially embedded in the package substrate104using techniques described herein for the fully embedded bridge606. In some embodiments, a finishing layer336may not be used at all (e.g., exposed bridge606).

FIGS. 7a-7fschematically illustrate a bridge interconnect assembly (“bridge”) subsequent to various fabrication operations, in accordance with some embodiments. The bridge may comport with embodiments described in connection withFIGS. 1-5.

Referring toFIG. 7a, a bridge700ais depicted subsequent to forming one or more electrical routing features such as, for example, THVs316through the bridge substrate314and surface routing features318on surfaces of the bridge substrate314. The surface routing features318may include pads, traces, and the like.

Referring toFIG. 7b, the bridge700bis depicted subsequent to forming a sacrificial layer744on the surface of the bridge substrate314. The sacrificial layer744may include a material that can be selectively removed to provide an air gap (e.g., air gap332ofFIG. 3). The sacrificial layer744can include a variety of materials including, for example, semiconductor materials such as silicon oxide (SiO2) or silicon nitride (SiN) and the like.

Referring toFIG. 7c, the bridge700cis depicted subsequent to forming openings in the sacrificial layer744to expose one or more of the surface routing features318. In some embodiments, the openings are formed over surface routing features318(e.g., ground pads) that are configured to route a ground signal, as can be seen. The openings may provide an area for formation of electrical connections (e.g., bump interconnects or other deposition of electrically conductive material) on the exposed surface routing features318.

Referring toFIG. 7d, the bridge700dis depicted subsequent to depositing an electrically conductive material (e.g., solder or metal) into the openings formed in the sacrificial layer744and forming an electrically conductive layer746on the sacrificial layer744. In this manner, the electrically conductive layer746may be coupled with the surface of the bridge substrate314through the sacrificial layer744by an electrically conductive material. Interconnect structures may be formed in the openings to couple the electrically conductive layer746with the surface routing features318. The openings may be filled with a first electrically conductive material followed by deposition of the electrically conductive layer746using a second electrically conductive material that is different than the first electrically conductive material in some embodiments. In other embodiments, deposition of the electrically conductive layer746and filling of the openings may occur in a simultaneous deposition process of a single material. The electrically conductive layer746may function as a ground plane (e.g., ground plane328ofFIG. 3) in some embodiments.

Referring toFIG. 7e, the bridge700eis depicted subsequent to forming a strengthening layer748on the electrically conductive layer746. The strengthening layer748may provide structural rigidity to the electrically conductive layer746to avoid collapse or other structural defect of the electrically conductive layer746during manufacturing operations such as an operation that removes material of the sacrificial layer744. The strengthening layer748may be composed of a variety of suitable materials including, for example, solder or metal. The strengthening layer748may include multiple layers or other materials in other embodiments. In some embodiments, a strengthening layer748is composed of an insulating layer (e.g., silicon oxide) with an electroplating metal layer on its top. In another embodiment, the strengthening layer748can be another Si wafer.

Referring toFIG. 7f, the bridge700fis depicted subsequent to removing material of the sacrificial layer744to provide an air gap332between the surface of the bridge substrate314and the electrically conductive layer746. Material of the sacrificial layer744may be removed according to a variety of suitable processes including, for example, a selective etch process (e.g., HF acid vapor etch process) that selectively removes the material of the sacrificial layer744relative to other exposed materials. The bridge700fmay be embedded into a cavity formed in a package substrate.

FIG. 8schematically illustrates a flow diagram for a method800of fabricating an IC package assembly (e.g., the IC package assembly100ofFIG. 1), in accordance with some embodiments. The method800may comport with actions described in connection withFIGS. 1-7in some embodiments.

At802, the method800includes providing a bridge substrate composed of glass, ceramic, or a semiconductor material. At804, the method800may further include forming electrical routing features through the bridge substrate and on the bridge substrate, the electrical routing features including through-hole vias, traces and pads. At806, the method800may further include forming a sacrificial layer on a surface of the bridge substrate. At808, the method800may further include forming openings in the sacrificial layer to expose one or more of the pads.

At810, the method800may further include forming interconnect structures on the pads. At812, the method800may further include forming an electrically conductive layer on the sacrificial layer, the electrically conductive layer being coupled with the interconnect structures. At814, the method800may further include forming a strengthening layer on the electrically conductive layer. At816, the method800may further include removing material of the sacrificial layer to provide an air gap between the bridge substrate and the electrically conductive layer. At818, the method800may further include embedding the bridge substrate into a cavity formed in a package substrate using an adhesive. At820, the method800may further include depositing a finishing film on the strengthening layer.

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.FIG. 9schematically illustrates a computing device900in accordance with one implementation of the invention. The computing device900may house a board such as motherboard902. The motherboard902may include a number of components, including but not limited to a processor904and at least one communication chip906. The processor904may be physically and electrically coupled to the motherboard902. In some implementations, the at least one communication chip906may also be physically and electrically coupled to the motherboard902. In further implementations, the communication chip906may be part of the processor904.

The computing device900may include a plurality of communication chips906. For instance, a first communication chip906may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip906may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor904of the computing device900may include a die (e.g., dies102ofFIG. 1) in an IC package assembly (e.g., IC package assembly100of FIG.1) as described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip906may also include a die (e.g., dies102ofFIG. 1) in an IC package assembly (e.g., IC package assembly100ofFIG. 1) as described herein. In further implementations, another component (e.g., memory device or other integrated circuit device) housed within the computing device900may contain a die (e.g., dies102ofFIG. 1) in an IC package assembly (e.g., IC package assembly100ofFIG. 1) as described herein. Such dies may be configured to send or receive signals through a bridge as described herein.