LDMOS transistors and associated systems and methods

A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.

BACKGROUND

Metal-oxide-semiconductor field effect transistors, often referred to as MOSFETS, are widely used in electronic devices, such as for switching or amplification. MOSFETS are capable of achieving fast switching speeds, which makes them well suited for use in high-frequency applications. Additionally, MOSFETS are relatively simple to control because they are voltage-controlled, instead of current-controlled, devices.

Lateral double-diffused metal-oxide-semiconductor field effect transistors, often referred to as LDMOS transistors, are a class of MOSFETS where drain-to-source voltage is blocked within the transistors' semiconductor material primarily in a lateral direction. LDMOS transistors are often combined with other circuitry in integrated circuits, especially in power applications or radio-frequency applications.

FIG. 1is a cross-sectional view of a conventional n-channel LDMOS transistor100including a silicon semiconductor structure102, a source electrode104, a gate structure106, and a drain electrode108. Source electrode104is stacked on a top surface110of silicon semiconductor structure102in a source region112of LDMOS transistor100, and drain electrode108is stacked on top surface110in a drain region114of LDMOS transistor100. Gate structure106includes a gate electrode116, a polysilicon layer117, and a silicon dioxide layer118stacked in a gate region120of LDMOS transistor100. Silicon semiconductor structure102includes a p-type substrate122, an n-well124, a p-body126, a source p+ region128, a source n+ region130, and a drain n+ region132. N-well124is formed on p-type substrate122, and p-body126is formed in n-well124under source electrode104. Drain n+ region132is formed in n-well124and contacts drain electrode108. Each of source p+ region128and source n+ region130is formed in p-body126and contacts source electrode104. Each of source n+ region130and drain n+ region132is more heavily doped than n-well124, and source p+ region128is more heavily doped than p-body126.

When positive voltage VDSis applied across drain electrode108and source electrode104, a p-n junction at the interface of n-well124and p-body126is reversed biased. Consequentially, essentially no current flows from drain electrode108to source electrode104by default. The relative dopant concentration of drain n+ region132and n-well124causes a portion of n-well124referred to as a drift region134to carry the majority of voltage VDS, thereby enabling LDMOS transistor100to support a relatively large value of VDSwithout breakdown.

A positive voltage VGSapplied between gate electrode116and source electrode104creates negative charges in silicon semiconductor structure102under silicon dioxide layer118, causing a minority-carrier channel to form in a region136of p-body126. This channel has excess electrons and will therefore conduct electric current. Consequentially, current will flow in the lateral138direction through silicon semiconductor structure102from drain n+ region132to source n+ region130when VGSexceeds a threshold value and VDSis a positive value. The current can encounter substantial resistance, however, in drift region134due to relatively light n-type dopant concentration in n-well124.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Applicant has developed LDMOS transistors and associated systems and methods which significantly advance the state of the art. Certain embodiments include a plurality of gate conductors to promote low on-resistance and high breakdown voltage. Additionally, some embodiments include one or more structures at least partially formed in a trench of a silicon semiconductor structure, to promote high transistor performance and small transistor pitch.

FIG. 2is a cross-sectional view of a dual-gate structure LDMOS transistor200including a silicon semiconductor structure202, a source electrode204, a drain electrode206, a first gate structure208, a second gate structure210, and a trench dielectric layer212. Source electrode204and drain electrode206are each disposed on a first outer surface214of silicon semiconductor structure202. First gate structure208and second gate structure210are separated from each other in a lateral direction218orthogonal to a thickness direction216. First gate structure208includes a first gate dielectric layer220, a first gate conductor222, and a first gate electrode224stacked on first outer surface214in the thickness216direction. Second gate structure210includes a second gate dielectric layer226, a second gate conductor228, and a second gate electrode230stacked on first outer surface214in the thickness216direction. Second gate structure210is optionally longer in the lateral218direction than first gate structure208to promote high breakdown voltage of LDMOS transistor200and/or to promote low accumulation resistance.

Trench dielectric layer212is embedded in a trench232of silicon semiconductor structure202such that trench dielectric layer212extends at least partially under each of first and second gate structures208and210in the thickness216direction. First gate dielectric layer220, second gate dielectric layer226, and trench dielectric layer212are each formed, for example, of silicon dioxide.

First and second gate conductors222and228are each formed, for example, of polysilicon. Although first gate dielectric layer220, second gate dielectric layer226, and trench dielectric layer212are illustrated as being separate elements, one or more of these dielectric layers may be combined without departing from the scope hereof

Silicon semiconductor structure202includes a p-type substrate234, an n-well236, a p-body238, a source p+ region240, a source n+ region242, and a drain n+ region244. Source p+ region240has a greater p-type dopant concentration than p-body238, and each of source and drain n+ regions242and244has a greater n-type dopant concentration than n-well236. N-well236is formed on substrate234, and p-body238is formed in n-well236at least partially under source electrode204. Drain n+ region244is formed in n-well236and contacts drain electrode206. Each of source p+ region240and drain n+ region242is formed in p-body238and contacts source electrode204. Trench dielectric layer212is disposed between at least a portion of p-body238and drain n+ region244in the lateral218direction. P-type substrate234could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure202can include additional impurity regions without departing from the scope hereof

One or more regions of silicon semiconductor structure202optionally has a graded dopant concentration. For example, in some embodiments, n-well236has a graded n-type dopant concentration where n-type dopant concentration is greatest near drain n+ region244, and p-body238has a graded p-type dopant concentration where p-type dopant concentration is greatest near source n+ region242. P-body238optionally extends at least partially under each of first gate structure208and second gate structure210, as illustrated, to achieve a reduced surface field effect, thereby enabling n-well236to have a relatively high n-type dopant concentration to promote low on-resistance of LDMOS transistor200, without diminishing breakdown voltage of the transistor200.

When positive voltageVDSis applied across drain electrode206and source electrode204, a p-n junction formed at the interface of n-well236and p-body238is reversed biased, so that very little current flows between drain electrode206and source electrode204by default. However, a positive voltage VGSapplied between first gate electrode224and source electrode204creates negative charges in semiconductor structure202under first gate dielectric layer220, causing a minority-carrier channel to form in a region246of p-body238. This channel has excess electrons and therefore conducts electric current through p-body238from n-well236to source n+ region242. Consequentially, current will flow predominately in the lateral218direction through silicon semiconductor structure202from drain n+ region244to source n+ region242when VGSexceeds a threshold value and VDSis a positive value. The threshold value is established, in part, by the dopant concentration in p-body238and by the thickness of first gate dielectric layer220. For example, threshold voltage can be reduced by decreasing p-type dopant concentration in p-body238adjacent to first gate structure208and/or by decreasing thickness of first gate dielectric layer220. Source p+ region240forms an ohmic contact between p-body238and source electrode204to help prevent a parasitic bipolar junction transistor (not shown) in silicon semiconductor substrate202from activating.

Second gate structure210can advantageously be used to promote both low on-resistance and high breakdown of LDMOS transistor200. In particular, a positive bias voltage applied to second gate electrode230relative to source electrode204causes negative charges to collect in n-well236under trench dielectric layer212. These negative charges create a majority-carrier channel in n-well236adjacent to trench dielectric layer212, thereby providing a low-resistance current path through n-well236. Additionally, applying a positive bias voltage to second gate electrode230reduces potential difference between drain n+ region244and second gate conductor228, thereby promoting high breakdown voltage of LDMOS transistor200. A constant bias voltage is optionally applied to second gate electrode230, i.e., bias voltage on second gate electrode230remains constant even as voltage on first gate electrode224changes during switching of LDMOS transistor200, to promote low switching losses in LDMOS transistor200and simplicity of circuitry (not shown) biasing second gate electrode230.

One possible application of LDMOS transistor200is in a switching power converter. For example,FIG. 3schematically illustrates a buck converter300including two instances of LDMOS transistor200, hereinafter referred to as LDMOS transistor200(1) and LDMOS transistor200(2). LDMOS transistors200(1) and200(2) are schematically illustrated inFIG. 3to promote illustrative clarity. Buck converter300further includes an input port302electrically coupled to an input power source (not shown), an input capacitor304, an inductor306, an output capacitor308, an output port310electrically coupled to a load (not shown), first driver circuitry312, first bias circuitry314, second driver circuitry316, second bias circuitry318, and a controller320.

Input port302is electrically coupled across a positive input node322and a reference node324. Input capacitor304is electrically coupled across positive input node322and reference node326, and input capacitor304provides a path for input ripple current drawn by buck converter300. Drain electrode206of LDMOS transistor200(1) is electrically coupled to positive input node322, and source electrode204of LDMOS transistor200(1) is electrically coupled to a switching node Vx. First gate electrode224and second gate electrode230of LDMOS transistor200(1) are electrically coupled to first driver circuitry312and first bias circuitry314, respectively. Drain electrode206of LDMOS transistor200(2) is electrically coupled to switching node Vx, and source electrode204of LDMOS transistor200(2) is electrically coupled to reference node324. First gate electrode224and second gate electrode230of LDMOS transistor200(2) are electrically coupled to second driver circuitry316and second bias circuitry318, respectively. LDMOS transistors200(1) and200(2), first driver circuitry312, first bias circuitry314, second driver circuitry316, and second bias circuitry318collectively form a switching circuit328. Inductor306is electrically coupled between switching node Vxand a positive output node330, and output port310is electrically coupled across positive output node330and reference node324. Output capacitor308is electrically coupled across positive output node330and reference node324, and output capacitor308provides a path for output ripple current generated by buck converter300.

Controller320controls switching of switching circuit328to transfer power from the power source (electrically coupled to input port302) to the load (electrically coupled to output port310). In particular, controller320controls first driver circuitry312to repeatedly switch first gate electrode224of LDMOS transistor200(1) between two different voltage magnitudes, to repeatedly create and destroy a minority-carrier channel in p-body238of LDMOS transistor200(1). Consequentially, LDMOS transistor200(1) repeatedly switches between its conductive and non-conductive states under the control of controller320. Controller320also controls second driver circuitry316to repeatedly switch first gate electrode224of LDMOS transistor200(2) between two different voltage magnitudes to cause LDMOS transistor200(2) to repeatedly switch between its conductive and non-conductive states. Controller320controls switching of LDMOS transistor200(2) such that it performs a freewheeling function, or in other words, so that LDMOS transistor200(2) provides a path for current flowing through inductor306when LDMOS transistor200(1) is in its non-conductive state. In some embodiments, controller320controls switching of switching circuit328to regulate one or more parameters of buck converter300, such as input voltage Vin, input current Iin, input power Pin, output voltage Vout, output current Iout, and output power Pout. Connections between controller320and other components of buck converter300are not shown to promote illustrative clarity.

First bias circuitry314maintains a constant voltage on second gate electrode230of LDMOS transistor200(1) to establish a majority-carrier channel in n-well236of the transistor, thereby promoting low on-resistance and high breakdown voltage of the transistor. Similarly, second bias circuitry318maintains a constant voltage on second gate electrode230of LDMOS transistor200(2) to establish a majority-carrier channel in n-well236of the transistor, thereby promoting low on-resistance and high breakdown voltage of the transistor.

It should be appreciated that LDMOS transistor200is not limited to use in a buck converter, or even to use in a switching power converter. For example, LDMOS transistor200could alternately be used in an amplifier.

FIG. 4illustrates a method400for reducing on-resistance in a LDMOS transistor. In step402, a first gate electrode is repeatedly switched between at least two different voltage magnitudes relative to a source electrode to repeatedly create and destroy a minority-carrier channel in a p-body of the transistor. In one example of step402, first driver circuitry312repeatedly switches first gate electrode224of LDMOS transistor200(1) between two different voltage magnitudes, to repeatedly create and destroy a minority-carrier channel in p-body238of LDMOS transistor200(1). (SeeFIGS. 2 and 3). In step404, a second gate electrode is maintained at a positive voltage relative to the source electrode to create a majority-carrier channel in an n-doped portion of the LDMOS transistor. In one example of step404, first bias circuitry314maintains a constant positive voltage on second gate electrode230of LDMOS transistor200(1) to establish a majority-carrier channel in n-well236of LDMOS transistor200(1). (SeeFIGS. 2 and 3).

Applicant has additionally determined that a second gate region can be at least partially formed in a trench, to further promote high breakdown voltage and small transistor size. For example,FIG. 5is a cross-sectional view of a LDMOS transistor500including two gate structures, where one of the two gate structures is partially formed in a trench. LDMOS transistor500includes a silicon semiconductor structure502, a source electrode504, a drain electrode506, a first gate structure508, and a second gate structure510. Source electrode504and drain electrode506are each disposed on a first outer surface514of silicon semiconductor structure502.

First gate structure508and second gate structure510are at least partially separated from each other in a lateral direction518. First gate structure508includes a first gate dielectric layer520, a first gate conductor522, and a first gate electrode524stacked on first outer surface514in a thickness516direction orthogonal to lateral518direction. Second gate structure510includes a second gate conductor528, a second gate dielectric layer526, and a gate electrode530. Second gate conductor is528embedded in second gate dielectric layer526in a trench532of silicon semiconductor structure502, and second gate electrode530contacts second gate conductor528. First gate dielectric layer520and second gate dielectric layer526are each formed, for example, of silicon dioxide. First gate conductor522and second gate conductor528are each formed, for example, of polysilicon.

Silicon semiconductor structure502includes a p-type substrate534, an n-well536, a p-body538, a source p+ region540, a source n+ region542, and a drain n+ region544. Source p+ region540has a greater p-type dopant concentration than p-body538, and each of source and drain n+ regions542and544has a greater n-type dopant concentration than n-well536. N-well536is formed on substrate534, and p-body538is formed in n-well536at least partially under source electrode504. Drain n+ region544is formed in n-well536and contacts drain electrode506. Each of source p+ region540and source n+ region542is formed in p-body538and contacts source electrode504. Second gate dielectric layer526and second gate conductor528are disposed between p-body538and drain n+ region544in the lateral518direction. P-type substrate534could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure502can include additional impurity regions without departing from the scope hereof.

One or more regions of silicon semiconductor structure502optionally has a graded dopant concentration. For example, in some embodiments, n-well536has a graded n-type dopant concentration where n-type dopant concentration is greatest near drain n+ region544, and p-body538has a graded p-type dopant concentration where p-type dopant concentration is greatest near source n+ region542. P-body538optionally extends deeper into silicon semiconductor structure502than second gate structure510, as illustrated, to achieve a reduced surface field effect, thereby enabling n-well536to have a relatively high n-type dopant concentration to promote low on-resistance of LDMOS transistor500, without diminishing breakdown voltage of LDMOS transistor500.

LDMOS transistor500may be operated in a manner similar to that discussed above with respect to LDMOS transistor200ofFIG. 2. For example, a positive voltage VGSmay be applied between first gate electrode524and source electrode504to create negative charges in semiconductor structure502under first gate dielectric layer520, causing a minority-carrier channel to form in a region546of p-body538. Additionally, a positive bias voltage can be applied to second gate electrode530relative to source electrode504to cause negative charges to collect in n-well536in the vicinity of second gate dielectric layer526, to create a majority-carrier channel in n-well536around second gate dielectric layer526, thereby promoting low on-resistance and high breakdown voltage of LDMOS transistor500.

Possible applications of LDMOS transistor500include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor500. LDMOS transistor500could also be used with method400ofFIG. 4.

Applicant has determined that use of additional gate conductors can further improve transistor performance, with the possible drawback of increased manufacturing cost.FIG. 6is a cross-sectional view of a LDMOS transistor600including three gate conductors, where two of the gate conductors are at least partially formed in a trench. LDMOS transistor600includes a silicon semiconductor structure602, a source electrode604, a drain electrode606, a first gate structure608, and a second gate structure610. Source electrode604and drain electrode606are each disposed on a first outer surface614of silicon semiconductor structure602.

First gate structure608and second gate structure610are at least partially separated from each other in a lateral direction618. First gate structure608includes a first gate dielectric layer620, a first gate conductor622, and a first gate electrode624stacked on first outer surface614in a thickness616direction, where the thickness direction616is orthogonal to the lateral direction618. Second gate structure610includes a second gate conductor628, a third gate conductor629, a second gate dielectric layer626, and a second gate electrode630. Second and third gate conductors628and629are each embedded in second gate dielectric layer626in a trench632of silicon semiconductor structure602. Second gate conductor628and third gate conductor629are separated from each other in the lateral618direction. Second gate electrode630contacts second gate conductor628, while third gate conductor629is optionally electrically floating, i.e., it does not contact a gate electrode. First gate dielectric layer620and second gate dielectric layer626are each formed, for example, of silicon dioxide. First gate conductor622, second gate conductor628, and third gate conductor629are each formed, for example, of polysilicon.

Silicon semiconductor structure602includes a p-type substrate634, an n-well636, a p-body638, a source p+ region640, a source n+ region642, and a drain n+ region644. Source p+ region640has a greater p-type dopant concentration than p-body638, and each of source and drain n+ regions642and644has a greater n-type dopant concentration than n-well636. N-well636is formed on substrate634, and p-body638is formed in n-well636at least partially under source electrode604. Drain n+ region644is formed in n-well636and contacts drain electrode606. Each of source p+ region640and source n+ region642is formed in p-body638and contacts source electrode604. N-well636includes a first portion648, a second portion650, and third portion652. First portion648is between p-body638and second gate structure610, and second portion650is below second gate structure610in the thickness616direction. Third portion652is below drain n+ region644.

Second gate dielectric layer626, second gate conductor628, and third gate conductor629are laterally618disposed between p-body638and drain n+ region644. Second gate conductor628is laterally disposed between p-body638and third gate conductor629, and third gate conductor629is laterally disposed between second gate conductor628and drain n+ region644. Second gate conductor628is separated from first portion648of n-well636by a first lateral separation distance654, and first and second gate conductors628and629are separated from each other by a second lateral separation distance656. Third gate conductor629is separated from third portion652of n-well636by a third lateral separation distance658. In some embodiments, second lateral separation distance656is greater than each of first lateral separation distance654and third lateral separation distance658. In a particular embodiment, each of first lateral separation distance654and third lateral separation distance658is0.12 microns, and second lateral separation distance656is 0.18 microns.

Use of two gate conductors, i.e. first and second gate conductors628and629in second gate structure610helps achieve optimization of both on-resistance and breakdown voltage. In particular, first lateral separation distance654significantly affects source resistance, while third lateral separation distance658significantly affects breakdown voltage. Use of first and second gate conductors628and629enables first lateral separation distance654and third lateral separation distance658to be individually selected, thereby promoting optimization of both on-resistance and breakdown voltage. If second gate conductor629were instead omitted, it would not be feasible to optimize both on-resistance and breakdown voltage. Second lateral separation distance656is, for example, sufficiently large to support a desired voltage between first and second gate conductors628and629, as well as to promote manufacturability of LDMOS transistor600.

One or more regions of silicon semiconductor structure602optionally has a graded dopant concentration. For example, in some embodiments, n-well636has a graded n-type dopant concentration where n-type dopant concentration is greatest near drain n+ region644, and p-body638has a graded p-type dopant concentration where p-type dopant concentration is greatest near source n+ region642. Second gate structure610optionally extends deeper into silicon semiconductor structure602than p-body638in the thickness616direction, as illustrated, to effectively embed the drain drift region into silicon semiconductor structure602, thereby promoting small device pitch, i.e. small lateral618spacing of adjacent LDMOS transistors600. Small device pitch, in turn promotes low on-resistance, as well as low capacitance by shielding miller capacitance. P-type substrate634could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure602can include additional impurity regions without departing from the scope hereof.

LDMOS transistor600may be operated in a manner similar to that discussed above with respect to LDMOS transistor200ofFIG. 2. For example, a positive voltage VGSmay be applied between first gate electrode624and source electrode604to create negative charges in semiconductor structure602under first gate dielectric layer620, causing a minority-carrier channel to form in a region646of p-body638. Additionally, a positive bias voltage applied to second gate electrode630relative to source electrode604causes negative charges to collect in first portion648of n-well636in the vicinity of second gate dielectric layer626, to create a majority-carrier channel in first portion648of n-well636. Third gate conductor629increases spacing between second gate conductor628and drain n+ region644, thereby advantageously promoting low gate-to-drain capacitance and high breakdown voltage. Third gate conductor629will typically become capacitively charged to a voltage between that of drain electrode606and second gate conductor628during switching of LDMOS transistor600, due to the third gate conductor629being electrically floating. Third gate conductor629could alternately be biased with respect to source electrode604without departing from the scope hereof.

Possible applications of LDMOS transistor600include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor600. LDMOS transistor600can also be used with method400ofFIG. 4.

FIGS. 7 and 8collectively illustrate how biasing a second gate conductor can promote high breakdown voltage of an LDMOS transistor.FIG. 7is a cross-sectional view of an LDMOS transistor700, which is similar to LDMOS transistor600ofFIG. 6. LDMOS transistor700includes a first gate structure708, a second gate structure710, an n-well736, a p-body738, a source n+ region742, and a drain n+ region744. Second gate structure710includes a second gate dielectric layer726, a second gate conductor728, and a third gate conductor729. Third gate conductor729is electrically floating. Second gate conductor728is not biased relative to the source electrode inFIG. 7. Lines748illustrate simulated electric potential in LDMOS transistor700when the transistor is operating in its conductive state. Only some lines748are illustrated to promote illustrative clarity. There is large potential gradient between p-body738and second gate dielectric layer726, as can be observed inFIG. 7.

FIG. 8is a cross-sectional view of LDMOS transistor700like that ofFIG. 7, but with second gate conductor728biased at20volts with respect to the source electrode. As can be appreciated by comparingFIGS. 7 and 8, electric potential is significantly more evenly distributed when second gate conductor728is biased at20volts than when second gate conductor728is not biased. Consequentially, biasing second gate conductor728with respect to the source electrode promotes high breakdown voltage in LDMOS transistor700.

FIG. 9is a cross-sectional view of a LDMOS transistor900including a symmetrical gate structure formed in a trench. LDMOS transistor900includes a silicon semiconductor structure902, a source electrode904, a gate electrode906, a drain electrode908, a dielectric layer910, a gate conductor912, and spacers914and916. A trench918is formed in silicon semiconductor structure902in a thickness920direction, and dielectric layer910is disposed in trench918and extends to a first outer surface922of silicon semiconductor structure902. Gate conductor912is embedded in dielectric layer910and extends into trench918in the thickness920direction. Gate conductor912is separated from silicon semiconductor structure902by dielectric layer910. Spacers914and916are separated from each other in a lateral924direction, where the lateral direction924is orthogonal to the thickness920direction. Spacers914and916bound dielectric layer910and gate conductor912on first outer surface922of silicon semiconductor structure922.

A gate structure926formed of gate conductor912and dielectric layer910is at least substantially symmetrical. In particular, each of dielectric layer910and gate conductor912is at least substantially symmetrical with respect to a center axis928of trench918extending in the thickness920direction, when LDMOS transistor900is view cross-sectionally in a direction orthogonal to the thickness920and lateral924directions (i.e., into the page ofFIG. 9). Such substantially symmetrical configuration advantageously promotes manufacturing simplicity, thereby helping achieve high conductivity of LDMOS transistor900in its on-state, in applications where acceptable on-resistance and breakdown voltage ratings can be achieved with similar thicknesses of dielectric layer910on both the source and drain sides of LDMOS transistor900. In this document, “substantially symmetrical” mean symmetrical within plus or minus ten percent.

Silicon semiconductor structure902includes a p-type substrate930, an n-well932, a p-body934, a source p+ region936, a source n+ region938, and a drain n+ region940. Source p+ region936has a greater p-type dopant concentration than p-body934, and each of source and drain n+ regions938and940has a greater n-type dopant concentration than n-well932. N-well932is formed on substrate930, and p-body934is formed in n-well932. Drain n+ region938is formed in n-well932, and each of source p+ region936and source n+ region938is formed in p-body934. Drain n+ region940is separated from source n+ region938in the lateral924direction. One or more regions of silicon semiconductor structure902optionally has a graded dopant concentration. For example, in some embodiments, n-well932has a graded n-type dopant concentration where n-type dopant concentration is greatest near drain n+ region940, and p-body934has a graded p-type dopant concentration where p-type dopant concentration is greatest near source n+ region938. P-type substrate930could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor902can include additional impurity regions without departing from the scope hereof.

Source electrode904contacts each of source p+ region936and source n+ region938. Gate electrode906contacts gate conductor912, and drain electrode908contacts drain n+ region940. Source electrode904and drain electrode908are each disposed on first outer surface922of silicon semiconductor structure902. Gate conductor912is formed, for example, of polysilicon, and dielectric layer910is formed, for example, of silicon dioxide.

When positive voltage VDSis applied across drain electrode908and source electrode904, a p-n junction formed at the interface of n-well932and p-body934is reversed biased, so that very little current flows between drain electrode908and source electrode904by default. However, a positive voltage VGSapplied between gate electrode906and source electrode904creates negative charges in silicon semiconductor structure902around gate conductor912, causing a minority-carrier channel to form in a region942of p-body934. The channel has excess electrons and therefore conducts electric current through p-body934from n-well932to source n+ region938. Consequentially, current will flow through silicon semiconductor structure902from drain n+ region940to source n+ region938when VGSexceeds a threshold value Vthand VDSis a positive value.

Threshold value Vthis established, in part, by the dopant concentration in p-body934and by the lateral924thickness of dielectric layer910separating gate conductor912from p-body934. For example, threshold voltage Vthcan be reduced by decreasing p-type dopant concentration in p-body934adjacent to gate conductor912and/or by decreasing thickness of dielectric layer910between gate conductor912and p-body934. Source p+ region936forms an ohmic contact between p-body934and source electrode904to help prevent a parasitic bipolar junction transistor (not shown) in silicon semiconductor substrate902from activating.

Possible applications of LDMOS transistor900include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor900, with first and second bias circuitry314and318omitted since LDMOS transistor900does not include a second gate structure.

Applicant has further developed quasi-trench LDMOS transistors, where the drain region is at about the same height as the bottom of the gate region. This configuration potentially achieves lower on-resistance than full-trench configurations, with the potential tradeoff of potentially greater manufacturing complexity.

For example,FIG. 10is a cross-sectional view of a quasi-trench LDMOS transistor1000including a silicon semiconductor structure1002, a body conductive plug1004, a source conductive plug1006, a gate conductor1008, a drain conductive plug1010, a source electrode1012, a gate electrode1014, a drain electrode1016, a dielectric layer1018, and spacers1020and1022. A trench1024is formed in silicon semiconductor structure1002in a thickness1026direction such that silicon semiconductor structure1002has a stepped first outer surface1028.

Silicon semiconductor structure1002includes a p-type substrate1030, an n-well1032, a p-body1034, a source p+ region1036, a source n+ region1038, and a drain n+ region1040. Source p+ region1036has a greater p-type dopant concentration than p-body1034, and each of source and drain n+ regions1038and1040has a greater n-type dopant concentration than n-well1032. N-well1032is formed on substrate1030, and p-body1034is formed in n-well1032. Drain n+ region1040is formed in n-well1032, and each of source p+ region1036and source n+ region1038is formed in p-body1034. Drain n+ region1040is separated from source n+ region1038in a lateral1042direction, where the lateral1042direction is orthogonal to the thickness1026direction. P-type substrate1030could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure1002can include additional impurity regions without departing from the scope hereof.

One or more regions of silicon semiconductor structure1002optionally has a graded dopant concentration. For example, in some embodiments, n-well1032has a graded n-type dopant concentration where n-type dopant concentration is greatest near drain n+ region1040, and p-body1034has a graded p-type dopant concentration where p-type dopant concentration is greatest near source n+ region1038.

Dielectric layer1018is disposed on first outer surface1028of silicon semiconductor structure1002in the thickness1026direction, and dielectric layer1018has an outer surface1044away from silicon semiconductor structure1002. In some embodiments, outer surface1044of dielectric layer1018is at least substantially planar. Body conductive plug1004extends through dielectric layer1018in the thickness1026direction to contact source p+ region1036, and source conductive plug1006extends through dielectric layer1018in the thickness1026direction to contact source n+ region1038. Gate conductor1008is embedded in dielectric layer1018and extends into trench1024in the thickness1026direction. Gate conductor1008is separated from silicon semiconductor structure1002by dielectric layer1018. Drain conductive plug1010extends through dielectric layer1018and trench1024to contact drain n+ region1040.

Source electrode1012contacts each of body conductive plug1004and source conductive plug1006. Gate electrode1014contacts gate conductor1008, and drain electrode1016contacts drain conductive plug1010. Spacer1020laterally1042separates gate conductor1008from source conductive plug1006, and spacer1022laterally1042separates gate conductor1008from drain conductive plug1010. Each of body conductive plug1004, source conductive plug1006, and drain conductive plug1010is formed of metal, for example. Gate conductor1008is formed, for example, of polysilicon, and dielectric layer1018is formed, for example, of silicon dioxide.

When positive voltage VDSis applied across drain electrode1016and source electrode1012, a p-n junction formed at the interface of n-well1032and p-body1034is reversed biased, so that very little current flows between drain electrode1016and source electrode1012by default. However, a positive voltage VGSapplied between gate electrode1014and source electrode1012creates negative charges in silicon semiconductor structure1002around gate conductor1008, causing a minority-carrier channel to form in a region1046of p-body1034. This channel has excess electrons and therefore conducts electric current through p-body1034from n-well1032to source n+ region1038. Consequentially, current will flow through silicon semiconductor structure1002from drain n+ region1040to source n+ region1038when VGSexceeds a threshold value Vthand VDSis a positive value.

It should be appreciated that the distance current must flow through n-well1032is relatively short due to the quasi-trench configuration of LDMOS transistor1000. In particular, current only needs to flow along one side and the bottom of gate conductor1008, in LDMOS transistor1000. This relatively short current path promotes low on-resistance. In full-trench devices, in contrast, current needs to flow along two sides, as well as the bottom, of the gate conductor.

Threshold value Vthis established, in part, by the dopant concentration in p-body1034and by the lateral1042thickness of dielectric layer1018separating gate conductor1008from p-body1034. For example, threshold voltage Vthcan be reduced by decreasing p-type dopant concentration in p-body1034adjacent to gate conductor1008and/or by decreasing thickness of dielectric layer1018between gate conductor1008and p-body1034. Source p+ region1036forms an ohmic contact between p-body1034and body conductive plug1004to help prevent a parasitic bipolar junction transistor (not shown) in silicon semiconductor substrate1002from activating.

Possible applications of LDMOS transistor1000include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor1000, with first and second bias circuitry314and318omitted since LDMOS transistor1000does not include a second gate structure.

FIG. 11is a cross-sectional view of a LDMOS transistor1100including two source regions. LDMOS transistor1100includes a silicon semiconductor structure1102, a first source conductive plug1104, a second source conductive plug1106, a drain conductive plug1108, a dielectric layer1110, a first gate conductor1112, a second gate conductor1114, a source electrode1116, a gate electrode1118, and a drain electrode1120. A trench1122is formed in silicon semiconductor structure1102in a thickness1124direction, and dielectric layer1110is disposed in trench1122.

Silicon semiconductor structure1102includes a p-type substrate1126, an n-well1128, a first p-body1130, a second p-body1132, a first source p+ region1134, a first source n+ region1136, a second source p+ region1138, a second source n+ region1140, an n-type laterally diffused drain1142, and a drain n+ region1144. First source p+ region1134has a greater p-type dopant concentration than first p-body1130, and second source p+ region1138has a greater p-type dopant concentration than second p-body1132. Each of first source n+ region1136, second source n+ region1140, and drain n+ region1144has a greater n-type dopant concentration than n-type laterally diffused drain1142, and n-type laterally diffused drain1142has a greater n-type dopant concentration than n-well1128.

N-well1128is formed on substrate1126. Each of first and second p-bodies1130and1132is formed in n-well1128and disposed in a lateral1146direction on opposite respective sides of trench1122, where the lateral1146direction is orthogonal to the thickness1124direction. First source p+ region1134and first source n+ region1136are formed in first p-body1130adjacent to a first outer surface1148of silicon semiconductor structure1102. Second source p+ region1138and second source n+ region1140are formed in second p-body1132adjacent to first outer surface1148. N-type laterally diffused drain1142is formed in n-well1128and partially surrounds trench1122. Drain n+ region1144is formed in n-type lateral diffused drain1142below trench1122in the thickness1124direction, and drain region1144is laterally1146separated from each of first p-body1130and second p-body1132. One or more regions of silicon semiconductor structure1102optionally have a graded dopant concentration. P-type substrate1126could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure1102can include additional impurity regions without departing from the scope hereof.

Drain conductive plug1108extends through dielectric layer1110and trench1122in the thickness1124direction to contact drain n+ region1144. First source conductive plug1104extends along each of first source p+ region1134and first source n+ region1136in the thickness1124direction to contact first p-body1130. This configuration promotes small device pitch by using a single conductive plug to contact each of first source n+ region1136and first p-body1130. Similarly, second source conductive plug1106extends along each of second source p+ region1138and second source n+ region1140in the thickness1124direction to contact second p-body1132, thereby also promoting small device pitch by using a single conductive plug to contact each of source n+ region1140and second p-body1132. Each of first and second gate conductors1112and1114is embedded in dielectric layer1110and extends into trench1122in the thickness1124direction, and first and second gate conductors1112and1114are laterally1146disposed on opposite respective sides of drain conductive plug1108. Each of first gate conductor1112and second gate conductor1114is separated from silicon semiconductor structure1102by dielectric layer1110.

Source electrode1116contacts each of first source conductive plug1104and second source conductive plug1106. Gate electrode1118contacts each of first gate conductor1112and second gate conductor1114. Drain electrode1120contacts drain conductive plug1108. Each of first source conductive plug1104, second source conductive plug1106, and drain conductive plug1108is formed of metal, for example. First and second gate conductors1112and1114are each formed, for example, of polysilicon, and dielectric layer1110is formed, for example, of silicon dioxide.

When positive voltage VDSis applied across drain electrode1120and source electrode1116, a p-n junctions formed at each of (a) the interface of n-well1128and first p-body1130, (b) the interface of n-type laterally diffused drain1142and first p-body1130, (c) the interface of n-well1128and second p-body1132, and (d) the interface of n-type laterally diffused drain1142and second p-body1132are reversed biased, so that very little current flows between drain electrode1120and source electrode1116by default. However, a positive voltage VGSapplied between gate electrode1118and source electrode1116creates negative charges in silicon semiconductor structure1102around each of first and second gate conductors1112and1114, causing a respective minority-carrier channel to form in each of a region1150of first p-body1130and a region1152of second p-body1132. Each channel has excess electrons and therefore conducts electric current through its respective p-body1130or1132. Consequentially, current will flow through silicon semiconductor structure1102from drain n+ region1144to each of first and second source n+ regions1136and1140when VGSexceeds a threshold value Vthand VDSis a positive value. Threshold value Vthis established, in part, by the dopant concentration in each of first p-body1130and second p-body1132, as well as the lateral1146thickness of dielectric layer1110separating first and second gate conductors1112and1114from first and second p-bodies1130and1132, respectively.

That LMDOS transistor1100has two source regions promotes low on-resistance by providing two parallel paths for current flow. However, lateral1146dimensions of first and second gate conductors1112and1114must be relatively large to obtain high breakdown voltage, resulting in LDMOS transistor1100having a relatively large pitch at high breakdown voltage ratings.

Possible applications of LDMOS transistor1100include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor1100, with first and second bias circuitry314and318omitted since LDMOS transistor1100does not include a second gate structure.

FIG. 12is a cross-sectional view of a LDMOS transistor1200including a plurality of drift regions. LDMOS transistor1200includes a silicon semiconductor structure1202, a source conductive plug1204, a dielectric layer1206, a gate conductor1208, a source electrode1210, a gate electrode1212, and a drain electrode1214. A trench1216is formed in silicon semiconductor structure1202in a thickness1218direction, and dielectric layer1206is disposed in trench1216.

Silicon semiconductor structure1202includes a p-type substrate1220, an n-well1222, a p-body1224, a first n-type drift region1226, a source p+ region1228, a source n+ region1230, an n-type laterally diffused drain1232, a second n-type drift region1234, and a drain n+ region1236. Source p+ region1228has a greater p-type dopant concentration than p-body1224. Each of source n+ region1230and drain n+ region1236has a greater n-type dopant concentration than n-type laterally diffused drain1232, and n-type laterally diffused drain1232has a greater n-type dopant concentration than each of first and second n-type drift regions1226and1234. Each of first and second n-type drift regions1226and1234, in turn, has a greater n-type dopant concentration than n-well1222.

N-well1222is formed on substrate1220. P-body1224is formed in n-well1222and is adjacent to trench1216in a lateral1240direction, where the lateral1240direction is orthogonal to the thickness1218direction. Source p+ region1228and source n+ region1230are formed in p-body1224adjacent to a first outer surface1238of silicon semiconductor structure1202. Source p+ region1228and source n+ region1230are also laterally1240adjacent to each other. First n-type drift region1226is disposed below each of source p+ region1228and source n+ region1230in the thickness1218direction. N-type laterally diffused drain1232is disposed below trench1216in the thickness1218direction. Second n-type drift region1234is formed in n-well1222such that first and second n-type drift regions1226and1234are disposed on opposite respective sides of trench1216in the lateral1240direction. Drain n+ region1236is disposed in second n-type drift region1234adjacent to first outer surface1238of silicon semiconductor structure1202. Drain n+ region1236is separated from source n+ region1230in the lateral1240direction. One or more regions of silicon semiconductor structure1202optionally have a graded dopant concentration. P-type substrate1220could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure1202can include additional impurity regions without departing from the scope hereof.

Source conductive plug1204extends along each of source p+ region1228and source n+ region1230and through first n-type drift region1226in the thickness1218direction to contact p-body1224. Gate conductor1208is embedded in dielectric layer1206and extends into trench1216in the thickness1218direction, and gate conductor1212is separated from silicon semiconductor structure1202by dielectric layer1206. A lateral separation distance1242between gate conductor1208and first n-type drift region1226is less than a lateral separation distance1243between gate conductor1208and second n-type drift region1234. A portion1244of dielectric layer1206between gate conductor1208and second n-type drift region1234achieves a reduced surface field effect, thereby enabling second drift region1234to have a relatively high n-type dopant concentration to promote low on-resistance of LDMOS transistor1200, without diminishing breakdown voltage of the transistor.

When positive voltage VDSis applied across drain electrode1214and source electrode1210, a p-n junction formed at the interface of n-well1222and p-body1224is reversed biased, so that very little current flows between drain electrode1214and source electrode1210by default. However, a positive voltage VGSapplied between gate electrode1212and source electrode1210creates negative charges in silicon semiconductor structure1202around gate conductor1208, causing a minority-carrier channel to form in a region1246of p-body1224. This channel has excess electrons and therefore conducts electric current through p-body1224. Consequentially, current will flow through silicon semiconductor structure1202from drain n+ region1236to source n+ region1230when VGSexceeds a threshold value Vthand VDSis a positive value. Threshold value Vthis established, in part, by the dopant concentration in p-body1224and by the lateral1240thickness of dielectric layer1206separating gate conductor1208from p-body1224.

That LMDOS transistor1200includes two drift regions, i.e., first n-type drift region1226and second n-type drift region1234, helps enable optimization of LDMOS transistor1200by allowing gate dimensions LG1and LG2to be independently defined. In particular, LG1is primarily defined by first n-type drift region1226, and LG2is primarily defined by second n-type drift region1234. A desired breakdown voltage of LDMOS transistor1200is obtained, for example, by optimizing dimension LG2during the design of LDMOS transistor1200. First and second n-type drift regions1226and1234are formed in separate process steps in some embodiments.

Possible applications of LDMOS transistor1200include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor1200, with first and second bias circuitry314and318omitted since LDMOS transistor1200does not include a second gate structure.

FIG. 13is a cross-sectional view of a LDMOS transistor1300including two gate conductors in a trench. LDMOS transistor1300includes a silicon semiconductor structure1302, a source conductive plug1304, a dielectric layer1306, a first gate conductor1308, a second gate conductor1310, a source electrode1312, a first gate electrode1314, a second gate electrode1315, and a drain electrode1316. A trench1318is formed in silicon semiconductor structure1302in a thickness1320direction, and dielectric layer1306is disposed in trench1318.

Silicon semiconductor structure1302includes a p-type substrate1322, an n-well1324, a p-body1326, a first n-type drift region1328, a source p+ region1330, a source n+ region1332, a second n-type drift region1334, and a drain n+ region1336. Source p+ region1330has a greater p-type dopant concentration than p-body1326. Each of source n+ region1332and drain n+ region1336has a greater n-type dopant concentration than each of first and second n-type drift regions1328and1334. Each of first and second n-type drift regions1328and1334, in turn, has a greater n-type dopant concentration than n-well1324.

N-well1324is formed on substrate1322. P-body1326is formed in n-well1324below trench1318in the thickness1320direction. Additionally, p-body1326is adjacent to trench1318in a lateral1338direction in a source region1340of LDMOS transistor1300, where the lateral1338direction is orthogonal to the thickness1320direction. Source p+ region1330and source n+ region1332are each formed in p-body1326adjacent to a first outer surface1342of silicon semiconductor structure1302. Source p+ region1330and source n+ region1332are also laterally1338adjacent to each other. First n-type drift region1328is disposed below each of source p+ region1330and source n+ region1332in the thickness1320direction. Second n-type drift region1334is formed in n-well1324such that first and second n-type drift regions1328and1334are disposed on opposite respective sides of trench1318in the lateral1338direction. Drain n+ region1336is disposed in second n-type drift region1334adjacent to first outer surface1342of silicon semiconductor structure1302. One or more regions of silicon semiconductor structure1302optionally have graded dopant concentrations. P-type substrate1322could be replaced with a different type of substrate, such as an n-type substrate or an intrinsic substrate, without departing from the scope hereof. Silicon semiconductor structure1302can include additional impurity regions without departing from the scope hereof.

Source conductive plug1304extends along each of source p+ region1330and source n+ region1332and through first n-type drift region1328in the thickness1320direction to contact p-body1326. Each of first and second gate conductors1308and1310is embedded in dielectric layer1306and extends into trench1318in the thickness1320direction. Second gate conductor1310is disposed above first gate conductor1308in the thickness1320direction in trench1318, such that first gate conductor1308is closer to a bottom1344of trench1318than second gate conductor1310. First and second gate conductors1308and1310are separated from each other, as well as from silicon semiconductor structure1302, by dielectric layer1306.

Source electrode1312contacts source conductive plug1304. First gate electrode1314contacts first gate conductor1308, and second gate electrode1315contacts second gate conductor1310. Drain electrode1316contacts drain n+ region1336. Source conductive plug1304is formed of metal, for example. Each of first and second gate conductors1308and1310is formed, for example, of polysilicon, and dielectric layer1306is formed, for example, of silicon dioxide.

When positive voltage VDSis applied across drain electrode1316and source electrode1312, p-n junctions formed at each of the interfaces of (a) n-well1324and p-body1326and (b) second n-type drift region1334and p-body1326are reversed biased, so that very little current flows between drain electrode1316and source electrode1312by default. However, a positive voltage VGSapplied between first gate electrode1314and source electrode1312creates negative charges in silicon semiconductor structure1302around first gate conductor1308, causing a minority-carrier channel to form in a region1346of p-body1326. This channel has excess electrons and therefore conducts electric current through p-body1326. Consequentially, current will flow through silicon semiconductor structure1302from drain n+ region1336to source n+ region1332when VGSexceeds a threshold value Vthand VDSis a positive value. Threshold value Vthis established, in part, by the dopant concentration in p-body1326and by the thickness of dielectric layer1306separating first gate conductor1308from p-body1326.

Second gate conductor1310can advantageously be used to promote both low on-resistance and high breakdown of LDMOS transistor1300. In particular, a positive bias voltage can be applied to second gate electrode1315relative to source electrode1312to cause negative charges to collect in each of first and second n-type drift regions1328and1334adjacent to second gate conductor1310. These negative charges create respective majority-carrier channels in each of first and second n-type drift regions1328and1334adjacent to second gate conductor1310, to promote low resistance in the current path through each n-type drift region. Additionally, applying a positive bias voltage to second gate electrode1315reduces potential difference between drain n+ region1336and second gate conductor1310, thereby promoting high breakdown voltage of LDMOS transistor1300. A constant bias voltage is optionally applied to second gate electrode1315, i.e., bias voltage on second gate electrode1315remains constant even as voltage on first gate electrode1314changes during switching of LDMOS transistor1300, to promote low switching losses in LDMOS transistor1300and simplicity of circuitry (not shown) biasing second gate electrode1315.

Possible applications of LDMOS transistor1300include, but are not limited to, switching power converter applications. For example, each of LDMOS transistors200(1) and200(2) in buck converter300ofFIG. 3could be replaced with a respective instance of LDMOS transistor1300. LDMOS transistor1300could also be used with method400ofFIG. 4.

A plurality of the LDMOS transistors disclosed herein could be formed on a common substrate. Such plurality of transistors need not necessarily have the same configuration. For example, an instance of LDMOS transistor1000ofFIG. 10and an instance of LDMOS transistor1100ofFIG. 11could be formed on a common p-type substrate. As another example, an instance of LDMOS transistor1200ofFIG. 12and an instance of LDMOS transistor1300ofFIG. 13could be formed on a common substrate.

Combinations of Features

Features described above may be combined in various ways without departing from the scope hereof. The following examples illustrate some possible combinations:

(A1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures may be disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer may be disposed in a trench in the silicon semiconductor structure and extend at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.

(A2) In the LDMOS transistor denoted as (A1), the silicon semiconductor structure may include a substrate, an n-well formed on the substrate, a p-body formed in the n-well, a source n+ region formed in the p-body, and a drain n+ region formed in the n-well. Additionally, the trench dielectric layer may be disposed between the p-body and the drain n+ region in the lateral direction.

(A3) In the LDMOS transistor denoted as (A2), the silicon semiconductor structure may further include a source p+ region formed in the p-body. The source p+ region may have a greater p-type dopant concentration than the p-body, and each of the source and drain n+ regions may have a greater n-type dopant concentration than the n-well.

(A4) In any of the LDMOS transistors denoted as (A2) through (A3), the p-body may extend under the trench dielectric layer in the thickness direction, and the p-body may have a graded p-type dopant concentration.

(A5) In any of the LDMOS transistors denoted as (A2) through (A4), the first gate structure may include a first gate dielectric layer and a first gate conductor stacked on a first outer surface of the silicon semiconductor structure in the thickness direction. Additionally, the second gate structure may include a second gate dielectric layer and a second gate conductor stacked on the first outer surface of the silicon semiconductor structure in the thickness direction.

(A6) In the LDMOS transistor denoted as (A5), each of the first and second gate conductors may be formed of polysilicon, and each of the first and second gate dielectric layers may be formed of silicon dioxide.

(A7) Any of the LDMOS transistors denoted as (A5) or (A6) may further include a source electrode disposed on the first outer surface of the silicon semiconductor structure and contacting each of the source p+ region and the source n+ region, a drain electrode disposed on the first outer surface of the silicon semiconductor structure and contacting the drain n+ region, a first gate electrode stacked on the first gate conductor, and a second gate electrode stacked on the second gate conductor.

(A8) A switching circuit may include the LDMOS transistor denoted as (A7), driver circuitry for repeatedly driving the first gate electrode between at least two different voltage magnitudes relative to the source electrode, and bias circuitry for maintaining the second gate electrode at a positive voltage relative to the source electrode.

(A9) In the switching circuit denoted as (A8), the bias circuitry may be configured to maintain the second gate electrode at a fixed positive voltage relative to the source electrode.

(B1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure, a first gate structure disposed on the silicon semiconductor structure, and a second gate structure partially disposed in a trench of the silicon semiconductor structure.

(B2) In the LDMOS transistor denoted as (B1), the silicon semiconductor structure may include a substrate, an n-well formed on the substrate, a p-body formed in the n-well, a source n+ region formed in the p-body, and a drain n+ region formed in the n-well. The first gate structure may be disposed on the silicon semiconductor structure at least partially over the p-body in a thickness direction, and the second gate structure may be disposed between the p-body and the drain n+ region in a lateral direction orthogonal to the thickness direction.

(B3) In the LDMOS transistor denoted as (B2), the silicon semiconductor structure may further include a source p+ region formed in the p-body.

(B4) In any of the LDMOS transistors denoted as (B2) and (B3), the p-body may extend deeper into the silicon semiconductor structure in the thickness direction than the second gate structure, and the p-body may have a graded p-type dopant concentration.

(B5) In any of the LDMOS transistors denoted as (B2) through (B4), the first gate structure may include a first gate dielectric layer and a first gate conductor stacked on a first outer surface of the silicon semiconductor substrate in the thickness direction, and the second gate structure may include a second gate conductor embedded in a second gate dielectric layer in the trench.

(B6) In the LDMOS transistor denoted as (B5), the second gate structure may further include a third gate conductor embedded in the second gate dielectric layer in the trench, and the second and third gate conductors may be separated from each other in the lateral direction.

(B7) In the LDMOS transistor denoted as (B6), the second gate conductor may be disposed between the p-body and the third gate conductor in the lateral direction, and the third gate conductor may be disposed between the second gate conductor and the drain n+ region in the lateral direction.

(B8) In any of the LDMOS transistors denoted as (B5) through (B7), each of the first and second gate conductors may be formed of polysilicon, and each of the first and second gate dielectric layers may be formed of silicon dioxide.

(B9) Any of the LDMOS transistors denoted as (B5) through (B8) may further include a source electrode disposed on the first outer surface of the silicon semiconductor structure and contacting the source n+ region, a drain electrode disposed on the first outer surface of the silicon semiconductor structure and contacting the drain n+ region, a first gate electrode stacked on the first gate conductor, and a second gate electrode stacked on the second gate conductor.

(B10) A switching circuit may include the LDMOS transistor denoted as (B9), driver circuitry for repeatedly driving the first gate electrode between at least two different voltage magnitudes relative to the source electrode, and bias circuitry for maintaining the second gate electrode at a positive voltage relative to the source electrode.

(B11) In the switching circuit denoted as (B10), the bias circuitry may be configured to maintain the second gate electrode at a fixed positive voltage relative to the source electrode.

(C1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure including a substrate, an n-well formed on the substrate, a p-body formed in the n-well below a trench in the silicon semiconductor substrate in a thickness direction, where the p-body is additionally adjacent to the trench in a lateral direction in a source region of the LDMOS transistor, the lateral direction being orthogonal to the thickness direction, a first n-type drift region formed in the p-body, and a second n-type drift region formed in the n-well such that the first and second n-type drift regions are disposed on opposite respective sides of the trench in the lateral direction. The LDMOS transistor may further include a dielectric layer disposed in the trench and first and second gate conductors embedded in the dielectric layer and extending into the trench in the thickness direction. The second gate conductor may be disposed above the first gate conductor in the thickness direction.

(C2) In the LDMOS transistor denoted as (C1), the silicon semiconductor structure may further include a source p+ region and a source n+ region formed in the p-body, the source p+ region and the source n+ region being adjacent in the lateral direction, and a drain n+ region formed in the second drift region. Additionally, the first n-type drift region may be formed in the p-body below each of the source p+ region and the source n+ region in the thickness direction.

(C3) In LDMOS transistor denoted as (C2), the source p+ region may have a greater p-type dopant concentration than the p-body, each of the source n+ region and the drain n+ region may have a greater n-type dopant concentration than each of the first and second n-type drift regions, and each of the first and second n-type drift regions may have a greater n-type dopant concentration than the n-well.

(C4) In any of the LDMOS transistors denoted as (C2) through (C3), each of the first and second gate conductors may be formed of polysilicon, and the dielectric layer may be formed of silicon dioxide.

(C5) Any of the LDMOS transistors denoted as (C2) through (C4) may further include a source conductive plug extending along each of the source p+ region and the source n+ region and through the first n-type drift region in the thickness direction, to contact the p-body.

(C6) In the LDMOS transistor denoted as (C5), the first and second gate conductors may be separated from the silicon semiconductor structure by the dielectric layer.

(C7) In any of the LDMOS transistors denoted as (C5) through (C6), the dielectric layer may separate each of the two gate conductors in the thickness direction.

(C8) In any of the LDMOS transistors denoted as (C5) through (C7), the first gate conductor may be disposed closer to a bottom of the trench than the second gate conductor.

(C9) Any of the LDMOS transistors denoted as (C5) through (C8) may further include a source electrode contacting the source conductive plug, a first gate electrode contacting the first gate conductor, a second gate electrode contacting the second gate conductor, and a drain electrode contacting the drain n+ region.

(C10) A switching circuit may include the LDMOS transistor denoted as (C9), driver circuitry for repeatedly driving the first gate electrode between at least two different voltage magnitudes relative to the source electrode, and bias circuitry for maintaining the second gate electrode at a positive voltage relative to the source electrode.

(C11) In the switching circuit denoted as (C10), the bias circuitry may be configured to maintain the second gate electrode at a fixed positive voltage relative to the source electrode.

(D1) A method for reducing on-resistance in a lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include (1) repeatedly switching a first gate electrode between at least two different voltage magnitudes relative to a source electrode of the LDMOS transistor to repeatedly create and destroy a minority-carrier channel in a p-body of the LDMOS transistor and (2) maintaining a second gate electrode at a positive voltage relative to the source electrode to create a majority-carrier channel in an n-doped portion of the LDMOS transistor.

(D2) In the method denoted as (D1), the n-doped portion of the LDMOS transistor may be an n-well.

(D3) In the method denoted as (D1), the n-doped portion of the LDMOS transistor may be an n-type drift region.

(D4) In any of the methods denoted as (D1) through (D3), the step of maintaining may include maintaining the second gate electrode at a fixed voltage relative to the source electrode.

(E1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure including a substrate, an n-well formed on the substrate, a p-body formed in the n-well, a source n+ region formed in the p-body, and a drain n+ region formed in the n-well and separated from the source n+ region in a lateral direction. The LDMOS transistor may further include a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor may be at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.

(E2) In the LDMOS transistor denoted as (E1), the silicon semiconductor structure may further include a source p+ region formed in the p-body.

(E3) In the LDMOS transistor denoted as (E2), the source p+ region may have a greater p-type dopant concentration than the p-body and each of the source and drain n+ regions may have a greater n-type dopant concentration than the n-well.

(E4) In any of the LDMOS transistors denoted as (E2) and (E3), the gate conductor may be formed of polysilicon, and the dielectric layer may be formed of silicon dioxide.

(E5) Any of the LDMOS transistors denoted as (E2) through (E4) may further include a source electrode contacting each of the source p+ region and the source n+ region, a gate electrode contacting the gate conductor, and a drain electrode contacting the drain n+ region.

(E6) A switching circuit may include the LDMOS transistor denoted as (E5) and driver circuitry for repeatedly driving the gate electrode between at least two different voltage magnitudes relative to the source electrode.

(F1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure including a substrate, an n-well formed on the substrate, a p-body formed in the n-well, a source n+ region formed in the p-body, and a drain n+ region formed in the n-well and separated from the source n+ region in a lateral direction. The LDMOS transistor may further include a dielectric layer formed on the silicon semiconductor structure in a thickness direction orthogonal to the lateral direction, a gate conductor embedded in the dielectric layer and extending into a trench of the silicon semiconductor substrate in the thickness direction, and a drain conductive plug extending through the dielectric layer and the trench in the thickness direction to contact the drain n+ region.

(F2) In the LDMOS transistor denoted as (F1), the gate conductor may be formed of polysilicon, and the dielectric layer may be formed of silicon dioxide.

(F3) Either of the LDMOS transistors denoted as (F1) through (F2) may further include a source conductive plug extending through the dielectric layer in the thickness direction and contacting the source n+ region.

(F4) In the LDMOS transistor denoted as (F3), the silicon semiconductor structure may further include a source p+ region formed in the p-body, and the LDMOS transistor may further include a body conductive plug extending through the dielectric layer in the thickness direction and contacting the source p+ region.

(F5) In the LDMOS transistor denoted as (F4), the source p+ region may have a greater p-type dopant concentration than the p-body, and each of the source and drain n+ regions may have a greater n-type dopant concentration than the n-well.

(F6) Either of the LDMOS transistors denoted as (F4) or (F5) may further include a source electrode contacting each of the body conductive plug and the source conductive plug, a gate electrode contacting the gate conductor, and a drain electrode contacting the drain conductive plug.

(F7) A switching circuit may include the LDMOS transistor of (F6) and driver circuitry for repeatedly driving the gate electrode between at least two different voltage magnitudes relative to the source electrode.

(G1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure including a substrate, an n-well formed on the substrate, first and second p-bodies formed in the n-well and laterally disposed on opposite respective sides of a trench in the silicon semiconductor structure, an n-type laterally diffused drain formed in the n-well and partially surrounding the trench, and a drain n+ region formed in the n-type laterally diffused drain below the trench in a thickness direction. The drain n+ region may be separated from each of the first and second p-bodies in a lateral direction. The LDMOS transistor may further include a dielectric layer disposed in the trench, a drain conductive plug extending through the dielectric layer and the trench in the thickness direction to contact the drain n+ region, and first and second gate conductors embedded in the dielectric layer and extending into the trench in the thickness direction, where the first and second gate conductors are laterally disposed on opposite respective sides of the drain conductive plug.

(G2) In the LDMOS transistor denoted as (G1) each of the first and second gate conductors may be formed of polysilicon, and the dielectric layer may be formed of silicon dioxide.

(G3) In any of the LDMOS transistors denoted as (G1) through (G2), the silicon semiconductor structure may further include a first source p+ region and a first source n+ region disposed in the first p-body, and a second source p+ region and a second source n+ region disposed in the second p-body. Additionally, the LDMOS transistor may further include a first source conductive plug extending along each of the first source p+ region and the first source n+ region in the thickness direction to contact the first p-body and a second source conductive plug extending along each of the second source p+ region and the second source n+ region in the thickness direction to contact the second p-body.

(G4) In the LDMOS transistor denoted as (G3), the first source p+ region may have a greater p-type dopant concentration than the first p-body, the second source p+ region may have a greater p-type dopant concentration than the second p-body, each of the first source n+ region, the second source n+ region, and the drain n+ region may have a greater n-type dopant concentration than the n-type laterally diffused drain, and the n-type laterally diffused drain may have a greater n-type dopant concentration than the n-well.

(G5) Any of the LDMOS transistors denoted as (G3) through (G4) may further include a source electrode contacting each of the first and second source conductive plugs, a gate electrode contacting each of the first and second gate conductors, and a drain electrode contacting the drain conductive plug.

(G6) A switching circuit may include the LDMOS transistor denoted as (G5) and driver circuitry for repeatedly driving the gate electrode between at least two different voltage magnitudes relative to the source electrode.

(H1) A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor may include a silicon semiconductor structure including a substrate, an n-well formed on the substrate, a p-body formed in the n-well and adjacent in a lateral direction to a trench formed in the silicon semiconductor structure, a first n-type drift region formed in the p-body, an n-type laterally diffused drain formed below the trench in a thickness direction, and a second n-type drift region formed in the n-well such the first and second n-type drift regions are disposed on opposite respective sides of the trench in the lateral direction. The LDMOS transistor may further include a dielectric layer disposed in the trench and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction.

(H2) In the LDMOS transistor denoted as (H1), a lateral separation distance between the gate conductor and the first drift region may be less than a lateral separation distance between the gate conductor and the second drift region.

(H3) In any of the LDMOS transistors denoted as (H1) through (H2), the gate conductor may be separated from the silicon semiconductor structure by the dielectric layer.

(H4) In any of the LDMOS transistors denoted as (H1) through (H3), the gate conductor may be formed of polysilicon, and the dielectric layer may be formed of silicon dioxide.

(H5) In any of the LDMOS transistors denoted as (H1) through (H4), the silicon semiconductor structure may further include (1) a source p+ region and a source n+ region formed in the p-body, where the source p+ region and the source n+ region are adjacent in the lateral direction, and (2) a drain n+ region formed in the second drift region, where the drain n+ region is separated from the source n+ region in the lateral direction. Additionally, the first n-type drift region may be formed in the p-body below each of the source p+ region and the source n+ region in the thickness direction, and the LDMOS transistor may further include a source conductive plug extending along each of the source p+ region and the source n+ region and through the first n-type drift region in the thickness direction, to contact the p-body.

(H6) In the LDMOS transistor denoted as (H5), the source p+ region may have a greater p-type dopant concentration than the p-body, each of the source n+ region and the drain n+ region may have a greater n-type dopant concentration than the n-type laterally diffused drain, the n-type laterally diffused drain may have a greater n-type dopant concentration than each of the first and second n-type drift regions, and each of the first and second n-type drift regions may have a greater n-type dopant concentration than the n-well.

(H7) Any of the LDMOS transistors denoted as (H5) and (H6) may further include a source electrode contacting the source conductive plug, a gate electrode contacting the gate conductor, and a drain electrode contacting the drain n+ region.

(H8) A switching circuit may include the LDMOS transistor of claim (H7) and driver circuitry for repeatedly driving the gate electrode between at least two different voltage magnitudes relative to the source electrode.

Changes may be made in the above devices, methods, and systems without departing from the scope hereof. For example, the n-channel LDMOS transistors discussed above could be modified to be p-channel LDMOS transistors. It should thus be noted that the matter contained in the above description and shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.