Canceller device and data transmission system

Disclosed is a canceller device comprising a subcanceller for compensating the sampling phase shift of a plurality of analog-to-digital convert circuits for receiving a common input analog signal, converting the analog signal into digital signals responsive to respective sampling clock signals with different phases to each other, and for outputting the digital signals, a main canceller for canceling echo/cross-talk from the signal output from analog-to-digital convert circuits whose the sampling phase shifts have been compensated, and a compensation range selection circuit for determining the range of the sampling phase shift for being compensated by the subcanceller based on the tap coefficients of the main canceller.

FIELD OF THE INVENTION

The present invention relates to a data transmission system and particularly a canceller device that cancels echo and/or cross-talk from a received signal.

BACKGROUND OF THE INVENTION

First, the outline of data transmission system will be given.FIG. 2is a diagram showing a typical configuration of a data transmission system comprising echo cancellers. InFIG. 2, a structural example of a transmission system (full duplex transmission system) using a twisted pair cable is shown as a data transmission system to which a canceller circuit relating to the present invention may also be applied.

Referring toFIG. 2, in a transmission device of this data transmission system, each transmission symbol (digital signal) is converted into an analog signal by digital-to-analog converters10and20, driven out by driver circuits11and21, and transmitted to a transmission line30via hybrid circuits16and26, and transformers17and27. A transmission signal sent from the opposite device to the transmission line30is received by a receiver device via the transformers17and27, and the hybrid circuits16and26. In the receiver device, after the received analog signal is converted into a digital signal by analog-to-digital converters12and22, the waveform is equalized by waveform equalizers13and23, and then a received symbol is output from identifiers not shown in the drawing. In the transmission line30, a transmission signal and a received signal are simultaneously and bi-directionally transmitted. An echo occurs when a transmission signal sneaks into a received signal, and it is caused by mismatches among the transformers17and27, and the hybrid circuits16and17, and mismatches between the connectors of the transmission line30.

The echo cancellers14and24receive the transmission symbols and error signals obtained by subtractors15and25which subtract the output of echo cancellers14and24(echo hereplica) from the output of the analog-to-digital converters12and22respectively, so that the echo and noise such as near-end cross-talk (NEXT) are cancelled.

As a concrete example of the data transmission system, for instance, “IEEE Standard 802.ab 10000BASE-T” specifies the physical layer (PHY) for Gigabit Ethernet (Registered Trademark) over CAT-5 cabling systems where, for every incoming data byte, a trellis encoder outputs four PAM-5 symbols to four pairs of wires at 125 MBaud/s. Signals are transmitted bi-directionally on each of the four wires (four pairs of the transmission line inFIG. 2), therefore echo must be removed on each wire. In addition, near-end cross-talk (NEXT) from the other wires can also be removed in a way similar to removal of echo cancellation (refer to Non-Patent Document 1: Runsheng, et al., “A DSP Based Receiver for 1000BASE-T PHY,” IEEE International Solid State Circuits Conference 19-6, 2001). In Non-Patent Document 1, the configuration of a DSP based receiver for 1000BASE-T physical layer (PHY) shown inFIG. 12is disclosed. Although a data path shown inFIG. 12is only for one channel, all four channels have similar structure.

Referring toFIG. 12, a block before a 9-bit pipeline analog-to-digital (A/D) converter607includes a hybrid603, a baseline wander correction circuit604, a programmable gain stage605, and an anti-aliasing analog low-pass filter (LPF)606. The hybrid603performs coarse echo cancellation by subtracting a replica of a band-limited waveform from a received waveform. Residual echo is removed by a digital echo canceller (ECHO & NEXT)610. Since the discrete-time response of echo is sensitive to timing phase of the A/D converter607, the ECHO & NEXT canceller610has jitter noise caused by timing jitter. The LPF606reduces the jitter noise by removing the high-frequency component of echo and near-end cross-talk responses. The baseline wander correction circuit604removes baseline distortion caused by the low-cut nature (the high-pass nature) of the transformer, and is controlled by a decision directed adaptive loop. A FIFO (First-In First-Out circuit)608provides compensation for delay skew on four different wires. The output signals of the A/D converter607are written into the FIFO608on A/D sampling clocks with different phases for four different channels, and are read on a single clock (that clocks all DSP blocks). Putting the FIFO608before the DSP block, resolves the latency skew at the earliest stage, and all DSP blocks operate on the same clock domain. The delay of the FIFO608on each channel is found by matching the idle symbol on all four channels during start up. The delay of the FIFO608is determined by the maximum delay skew. The digital ECHO & NEXT canceller610removes NEXT (near-end cross-talk) as well as the residual echo of the hybrid. The ECHO & NEXT canceller610for each channel is implemented by four FIR (Finite Impulse Response) filters (three for NEXT (20×3 taps), one for echo (160 taps)), and local transmitted data (TX data) from an encoder602is supplied to the FIR filters. A delay circuit (Delay Adjust)611at the input of the ECHO & NEXT canceller610matches the path delay from the input of the A/D converter607to the output of the FIFO608. Each tap of the FIR filter in the ECHO & NEXT canceller610is adaptive. Since changes of responses are slow compared to the 125 M/s symbol rate, the loop gain of the ECHO & NEXT canceller is set to a small value to reduce gradient noise. A least mean-square (LMS) algorithm is used for adapting taps of the ECHO & NEXT canceller610. The output (echo and cross-talk replica) of the ECHO & NEXT canceller610is subtracted from the output of the FIFO608, and the result is supplied to a feed-forward equalizer (FFE)612. The FFE612is a filter for canceling the pre-cursor ISI (InterSymbol Interference). The output of the gain stage is fed to a DFSE (Decision Feedback Sequence Estimation)614. The DFSE614implements a trellis code decoder and a DFE (Decision Feedback Estimator). To generate branch metrics of the trellis code decoder, the absolute value of error is used. To compare the gain of the DFSE614, a 5-level threshold detector is implemented. Digital timing recovery (not shown in the drawing) controls the sampling phases of the A/D converter607. The digital timing recovery includes a phase loop for each channel and a frequency loop shared by all four channels. Note that reference symbols615,616,617, and618indicate error generator, error monitor, adaptation algorithm, and control circuit respectively, however, since they are not directly relevant to the subject of the present invention, explanations of them will be omitted.

FIG. 13is a diagram illustrating the configuration of the ECHO & NEXT canceller610shown inFIG. 12.FIG. 13is newly created by the present inventor in order to describe the prior art in more detail. As shown inFIG. 13, it comprises an echo canceller702(for instance a160tap FIR filter) which receives a transmission symbol pair1and a residual echo and outputs an echo replica, and three NEXT canceller circuits703,704, and705(20 tap FIR filters). Out of four pairs of twisted pair cables, an echo error signal from a twisted pair1, near-end cross-talk from a twisted pair2, near-end cross-talk from a twisted pair3, and near-end cross-talk from a twisted pair4are sneaked into an input signal pair1from the twisted pair1. The transmission symbol and the error signal (residual echo) are supplied to the echo canceller702, its output is supplied to a subtractor706and subtracted from an output waveform of an A/D converter701. The output of the subtractor706(the waveform obtained by subtracting the echo replica from the received waveform) is supplied to a subtractor707, and the subtractor707subtracts the outputs of the NEXT canceller circuits703,704, and705from it, outputting the result as an error signal. The NEXT canceller circuits703,704, and705receive transmission symbol pairs2,3, and4, respectively, and the error signal in common. The NEXT canceller circuits703,704, and705adaptively control respective tap coefficients according to the LMS algorithm and respectively generate the cross-talk replicas. Note that near-end cross-talk (NEXT) means cross-talk between a signal pair (twisted pair) within the same cable. Echo can be considered to be cross-talk between the same pair (twisted pair).

In recent years, as the transmission speed of transmission system increases, high speed and high accuracy A/D converter is demanded for the receiver device shown inFIG. 2. Increasing the speed of A/D converter means increasing conversion rate (sampling frequency), and in order to realize high accuracy in A/D converter, not only DC characteristics such as resolution, offset, and linearity need to be improved, but also the improvement of dynamic characteristics (A/D converter characteristics) such as reducing sampling clock skew is necessary. The resolution of high-speed A/D converter is relatively coarse, and- it is difficult and expensive for an A/D converter to be high speed and high accuracy. Therefore, in order to realize a high-speed and high-accuracy A/D converter, an architecture in which a plurality of A/D converters are arrayed and each A/D converter operates in a time-interleaved system (called “interleaved A/D converter system” or “time-interleaved A/D converter system”) has been conventionally employed (refer to Non-Patent Document 2 for instance). In an interleaved A/D converter system, high-speed operation is achieved while suppressing the increase in the conversion rate of each A/D converter by driving a plurality of A/D converters connected in common to an analog input terminal with multi-phase frequency-divided clock signals having respective phases spaced apart.

FIG. 11illustrate a model of a noise occurrence caused by phase shift, and is a diagram for schematically explaining how noise caused by the phase sift of sampling clocks between two A/D converters occurs in an interleaved A/D converter system of two A/D converters. InFIG. 11, the abscissa indicates time and the ordinate signal amplitude. Further, inFIG. 11, timings indicated by phase1show the sampling phases of the first A/D converter, and phase2shows the ideal sampling phases of the second A/D converter when phase2is a reference phase. An analog signal inFIG. 11shows the waveform of a time-continuous analog signal fed to the two A/D converters as an input signal, and intersections of the analog signal waveform and the timings indicated by the phases1and2show time-discrete sample values (the ideal sample values) of the first and second A/D converters. Further, inFIG. 11, timings indicated by respective arrows (designated by ‘phase shift’) are the timings at which the sampling phase of the second A/D converter is shifted by the phase shift of the sampling clock. The phase shift of the sampling clock is termed a sampling phase shift.

As shown inFIG. 11, the sampling phase of the second A/D converter is shifted by a sampling phase shift, and as a result, a difference between the sampled value under the condition when a sampling phase shift exists and the ideal sample value (the intersection of the A/D converter2and the analog signal) occurs (refer to noise indicated by arrows). Here, when the sampling phase shift is Δt, the amplitude of the noise ΔV is given by ΔV=[df (t)/dt] Δt (where f(t) is the time-continuous analog signal waveform), the amplitude depends on the value of the sampling phase shift Δt, and it increases in the area where the differential coefficient df(t) of the signal waveform variation rate f(t) increases (where the slew rate increases).

In order to cope with such a phase shift, a correction circuit correcting the phase shift is provided in a conventional interleaved A/D converter system (refer to Patent Document 1 for instance).

Runsheng, et al., “A DSP Based Receiver for 1000BASE-T PHY,” IEEE International Solid State Circuits Conference 19-6, 2001.

SUMMARY OF THE DISCLOSURE

As described above, in order to achieve high-speed and high-accuracy operation in an interleaved A/D converter system, a correction circuit for correcting the sampling phase shift is necessary. In this case, circuits, processing, and sequences unnecessary to a normal adaptive equalizer of a receiver device in a data transmission system have to be added, and it is very difficult to reduce circuit size and simplify processing.

Further, after correcting the sampling phase shift of A/D converter, echo must be cancelled, increasing circuit scale and costs. Meanwhile, as the demand for high-speed operation increases, supplying sampling clocks whose phase shift have been corrected in advance to a plurality of A/D converters will makes designing difficult.

Accordingly, a canceller device that makes it possible to cancel echo and/or cross-talk when a phase shift occurs in an interleaved A/D converter system without incurring the increases in circuit scale and power consumption is desired.

The outline of the present invention is as follows.

A canceller device according to the present invention comprises a first canceller which compensates sampling phase shift of an interleaved analog-to-digital converter circuit and a second canceller which cancels echo and/or cross-talk from a signal whose sampling phase shift has been compensated.

The canceller device according to the present invention preferably comprises a compensation range selection circuit which determines the compensation range of the first canceller based on the tap coefficients of the second canceller.

Preferably, the canceller device according to the present invention, based on a prescribed training algorithm, carries out cancellation of echo and/or cross-talk from signals output from a plurality of analog-to-digital converter circuits. The analog-to-digital converter circuits have analog input terminals for receiving an analog input signal connected in common and convert said analog input signal into digital signals to output the resultant digital signals, responsive to respective sampling clock signals having respective phase spaced apart. The canceller device comprises: a first canceller for receiving a digital transmission signal and an error signal, outputting a replica of echo and/or cross-talk, and for compensating sampling phase shift of said plurality of analog-to-digital converter circuits; a second canceller for receiving said digital transmission signal and said error signal, and canceling echo and/or cross-talk from signals output from said plurality of analog-to-digital converter circuits, each having sampling phase shift compensated; and a compensation range selection circuit for controlling to select a position of the sampling phase shift subjected to compensation by said first canceller. The compensation range selection circuit estimates a tap position at which the sampling phase shift needs to be compensated based on the tap coefficients of said second canceller after training and selects taps used by said first canceller.

In the present invention, the first canceller and the second canceller may share a part of the circuit.

According to the present invention, it is possible to cancel echo and near-end cross-talk when phase shifting occurs in an interleaved analog-to-digital converter system while suppressing the increases in the circuit scale and power consumption.

Further, according to the present invention, echo and near-end cross-talk are suppressed although the sampling phase shift is allowed to be present, thus the delay design such as timing is simplified.

PREFERRED EMBODIMENTS OF THE INVENTION

Hereinafter, the embodiments of the present invention will be described with reference to the drawings in order to further explain the above-described present invention in detail. First, the principle of the present invention will be explained.FIG. 9is a diagram showing the response waveform of an echo solitary wave in the data transmission system shown inFIGS. 2 and 3with the abscissa indicating time (the unit is 1 UI (Unit Interval)) and the ordinate amplitude. In the echo waveform, the tail of the echo remains even after several hundred sample times (several hundred UIs) because of the reflections on the far end side.

FIG. 10is a diagram showing the waveform obtained by subtracting the response waveform shifted by, for instance, 0.05 UIs from the original response waveform of the echo solitary wave. The abscissa indicates time (the unit is 1 UI (Unit Interval)) and the ordinate amplitude inFIG. 10as well. As shown inFIG. 10, the influence of the sampling phase shift of the A/D converters can be reduced by compensating only the areas with high amplitudes in the echo solitary wave response (refer toFIG. 9). Further, near-end cross-talk from other wires can be reduced similarly as the echo cancellation.

In a canceller device according to the present invention, which has been invented based on the above observation and knowledge, there is provided a canceller (104inFIG. 1) which compensates the sampling phase shift of an interleaved A/D converter, and in addition to this canceller for correcting the sampling phase shift (termed a sub canceller), there is provided another canceller (termed a main canceller) (103inFIG. 1) which suppresses echo and/or cross-talk (referred to as echo/cross-talk hereinafter) after the sampling phase shift has been compensated. The canceller device according to the present invention further comprises a compensation range selection circuit (105inFIG. 1) which selects a position of the sampling phase shift for being subjected to compensation, and variably controls tap coefficient of the canceller (104inFIG. 1) for correcting the sampling phase shift by estimating a tap position where the compensation of the sampling phase shift is necessary based on tap coefficients of the canceller (103inFIG. 1), thereby canceling echo/cross-talk from the signal after the sampling phase shift has been compensated.

Since it is not necessary to provide taps for the canceller (104inFIG. 1) for correcting the sampling phase shift except for the taps where phase shift compensation is necessary, the number of multipliers and adders for the taps of the canceller (104inFIG. 1) for correcting the sampling phase shift can be reduced. Further, since echo/cross-talk is suppressed in the main canceller and only the differential is compensated in the subcanceller, the word length for calculation can be reduced.

As a comparison, for instance if taps matching the response length of the echo solitary wave are provided for each of multiple A/D converters constituting an interleaved A/D converter system, the circuit scale will increase.

According to the present invention, even when there is a phase shift of the sampling clock of an A/D converter, the sub canceller (104inFIG. 1) for compensating the phase shift compensates the phase shift, and the main canceller (103inFIG. 1) cancels echo/cross-talk after the phase shift has been compensated, thereby suppressing the deterioration of the characteristics even when a sampling phase shift exists. Further, the timing design of the circuit is made easier and high-speed operation can be realized by achieving a design where the existence of the sampling phase shift is allowed. Hereinafter, detailed explanations will be given about the embodiments.

FIG. 1is diagram illustrating the configuration of a receiver device of a first embodiment of the present invention, using a signal diagram. Note that the embodiment shown below may be used as the receiver device shown inFIG. 2or12.

Referring toFIG. 1, the receiver device according to the present embodiment comprises two A/D converters101and102, a main canceller103, a sub canceller104, a compensation range selection circuit105, subtractors106107and109, a parallel-to-serial converter circuit (multiplexer)108, a serial-to-parallel converter circuits (demultiplexers)110and111. The A/D converters101and102, which have analog inputs to which a received analog signal is supplied, convert the received analog signal into digital signals and output the digital signal responding to sampling clock signals (not shown) of different phases to each other, respectively. The main canceller103cancels echo/near-end cross-talk (NEXT) from the received signal. The subcanceller104corrects sampling phase shifts of A/D converters101and102. The subtractors106and107that subtract the output (replica) of the subcanceller104from the digital signals output from the two A/D converters101and102, respectively. The parallel-to-serial converter circuit (multiplexer)108receives and multiplexes the outputs of the subtractors106and107to output the multiplexed signal. The subtractor109subtracts the output (replica) of the main canceller103from the multiplexed output of the parallel-to-serial converter circuit108.

The main canceller103includes an adaptive filter which receives an error signal output from the subtractor109and a transmission symbol (digital transmission signal) and carries out cancellation of echo/near-end cross-talk (NEXT). The main canceller103cancels echo/near-end cross-talk (NEXT) of the signals output from the A/D converters101and102, whose sampling phase shifts have been compensated.

The error signal is demultiplexed into two signals by the serial-to-parallel converter circuit (demultiplexer)110, and supplied to the subcanceller104. The compensation range selection circuit105selects a range of a sampling phase shift in the subcanceller104based on tap coefficients of the main canceller103.

The serial-to-parallel converter circuit111which has an input terminal for receiving the transmission symbol, and which demultiplexes the transmission symbol and outputs the demultiplexed transmission symbols in parallel. The subcanceller104includes an adaptive filter which variably controls taps under the control of the compensation range selection circuit105. The subcanceller104receives the demultiplexed transmission symbols from the serial-to-parallel converter circuit111and the demultiplexed error signals output from the serial-to-parallel converter circuit110, and outputs replicas of echo/near-end cross-talk to the subtractors106and107respectively.

The subtractors106and107subtract two outputs of the subcanceller104from the outputs of the A/D converters101and102, respectively, and output received signals, from which sampling phase shifts of the A/D converters101and102have been corrected. This follows the principle of the present invention described with reference toFIGS. 9 and 10. And the main canceller103cancels echo/near-end cross-talk from the received signals (i.e., the outputs of the subtractors106and107), whose sampling phase shifts have been corrected.

FIG. 3is a diagram illustrating an example of the configuration of the main canceller103shown inFIG. 1. Referring toFIG. 3, the adaptive equalizer is constituted as an adaptive filter comprising: a filter unit200which is composed by an FIR (Finite Impulse Response) filter; and a tap updating unit210which updates the filter coefficient of the FIR filter unit200. The adaptive filter shown inFIG. 3adopts, for example, the LMS (Least Mean Square) algorithm. By the way, the algorithm in the present invention is as a matter of course is not limited to the LMS. Assuming that the degree of the filter is M, the following equation is given:
yn=b0,nxn+b1,nxn−1+ . . . +bM,nxn−M(1)

where xnand ynare an input signal (discrete-time digital signal) and an output signal, respectively,

enis a discrimination error, and

Note that xn−1is a signal obtained by having a delay element delay the input signal by one unit time, and xn−Mis a signal obtained by having M number of delay elements delay the input signal by M unit time.

The Equation (1) is represented as follows:
yn=BnTXn(2)

where

T is a transpose operator, and

(where Col is an operator that sets a row to a column (a vector)).

According to the well-known LMS algorithm by B. Widrow for tap updating, the filter coefficient Bn+1of timen+1is given by the following equation:
Bn+1=Bn+venXn(3).

In other words, inFIG. 3, while the tap updating unit210supplies Bnof the current time n to multipliers208to206, the tap updating unit210also stores Bnin memory elements (D registers)220, . . . ,217, and214, and updates the filter coefficient vector at the following time n+1 to Bn+1=[b0,n+1, b1, n+1, . . . , bN, n+1]. Bn+1is obtained by having adders219, . . . ,216, and213respectively add the values output from multipliers218, . . . ,215, and212, which multiply Xn=Col[xn, xn−1, . . . , xn−M] by a gain v and the error en, and the values of the memory elements (D registers)220, . . . ,217, and214Bn=[b0,n, b1,n, . . . , bN,n]. This LMS algorithm gradually gets closer to the optimum tap gain. Note that the filter coefficients may also be-variably controlled according to the RLS (Recursive Least Squares) algorithm. Further, an example using an FIR filter having a linear phase characteristic has been described inFIG. 3for the sake of simplicity, however, an adaptive filter is not limited to the FIR filter. Further, as an adaptive equalizer, a time domain equalizer has been described as an example, however, an equalizer adaptively equalizing in the frequency domain can be applied as well (refer to Non-Patent Document 3 for instance). Since a convolution in the time domain (refer to Equation (1)) correspond to a multiplication in the frequency domain, a structure where the adaptive equalization is carried out in the frequency domain is suitable for high-speed operation.

FIG. 4is a diagram showing an example of the configuration of the subcanceller104shown inFIG. 1. It is not limited to this, but the subcanceller104is constituted by MIMO (Multiple Inputs, and Multiple Outputs) filters in the example shown inFIG. 4. The subcanceller104comprises first to fourth adaptive equalizers301-304and adders305and306. The first adaptive equalizers301receives data1which is the result of serial-to-parallel conversion by the serial-to-parallel converter circuit111inFIG. 1and an error signal1which is the result of serial-to-parallel conversion by the serial-to-parallel converter circuit110inFIG. 1. The second adaptive equalizers302receives data2which is the result of serial-to-parallel converted by the serial-to-parallel converter circuit111inFIG. 1and the error signal1. The adder305adds the outputs of first and second adaptive equalizer301and302and supplies the added result to the first subtractor106inFIG. 1. The third adaptive equalizers303receives the data1and an error signal2which is the result of serial-to-parallel conversion by the serial-to-parallel converter circuit110inFIG. 1. The forth adaptive equalizers304receives the data2and the error signal1. The adder306add the outputs of the third and fourth adaptive equalizers303and304and supplies the added result to the first subtractor107inFIG. 1. Each of the adaptive equalizers may be composed by for an adaptive filter (FIR filter for instance) shown inFIG. 3.

Referring toFIG. 1again, the compensation range selection circuit105receives the tap coefficients (the values of the D registers214to220inFIG. 3) of the main canceller103, and calculates a tap position for correcting the phase shift in the subcanceller104.

In the present embodiment, the following technique can be used to carry out training of each tap coefficient in respective filters of the main canceller103and sub canceller104:

(A1) Train the tap coefficient of the main canceller103. (The training of the tap coefficient is continuous.)

(A2) A tap position of the subcanceller104for compensating the phase shift is determined by the value of the tap coefficient of the main canceller103.

(A3) The tap coefficient of the subcanceller104is trained.

(A4) In case the compensation range of the subcanceller104is not variable, each tap coefficient of the subcanceller104and the main canceller103may be trained simultaneously.

FIG. 5is a diagram showing how the compensation range selection circuit105sets the compensation range of the subcanceller104which is for correcting sampling phase shift of A/D converters101and102.

First, the adaptation of the main canceller103(XC1) is performed (a step S1). Next, whether or not the adaptation is complete is determined (a step S2). At this time of the determination, it is not necessary to stop the adaptation. The completion of the adaptation may also be determined by a timer in such a manner that when a timeout of the timer occurs, the adaptation is regarded to be completed.

At the completion of the main canceller103(XC1) adaptation (a step S3), the tap coefficients (the D registers214to220inFIG. 3) of the main canceller103(XC1) are sorted in, for instance, in descending order (a step S4), and as many taps as the provided tap coefficients of the subcanceller104(XC2) are selected in descending order (a step S5).

Next, the adaptation of the subcanceller104(XC2) is performed (a step S6), and then the main canceller103(XC1) and the subcanceller104(XC2) operate normally (a step S7).

Or after the completion of the adaptation of the main canceller103, the tap coefficients (the D registers214to220inFIG. 3) of the main canceller103may be searched from the top and compared with a predetermined threshold value, assigning the taps higher than the threshold value as the taps of the subcanceller104(XC2).FIG. 6is a flowchart illustrating these procedures. InFIG. 6, steps S11, S12, and S13are the same as the steps SI, S2, and S3inFIG. 5.

When the adaptation of the main canceller103is completed, the tap coefficients (the D registers214to220inFIG. 3) of the main canceller103are read out from the top (a step S14), the tap coefficients read out are compared with the threshold value (a step S15), and the tap coefficients higher the threshold value (Yes branch of the step S15) are selected as the tap coefficients used by the subcanceller (XC2)104(a step S16).

If the number of the tap coefficients used is more than the tap coefficients provided for the subcanceller (XC2)104(Yes branch of a step S17), the adaptation of the subcanceller (XC2)104is performed (a step S18). After this, the main canceller (XC1)103and the subcanceller (XC2)104operate normally (a step S19).

Next, another embodiment of the present invention will be described. The signal diagram of the present embodiment is the same as the one shown inFIG. 1. In the present embodiment, the main canceller103and the subcanceller104inFIG. 1share a part of the circuit.

FIG. 7is a diagram illustrating the configuration of the present embodiment, and the structures of the main canceller103, the subcanceller104, and the compensation range selection circuit105are shown. Referring toFIG. 7, a shift register (delay circuit array)400made up of plurality of delay circuits401to405, plurality of multipliers406to410respectively multiplying the outputs of the delay circuits401to405by tap coefficients received, and an FIR filter made up of plurality of adders411to414constitute the main canceller103inFIG. 1. Further, plurality of multipliers421to423respectively multiplying the outputs of delay circuits selected by a tap selector420from the shift register (delay circuit array)400made up of plurality of delay circuits401to405by tap coefficients received, and an FIR filter made up of plurality of adders424and425constitute the subcanceller104for correcting phase shift. The main canceller103and the subcanceller104share the shift register (delay circuit array)400that constitutes their FIR filters. The tap selector420constitutes the compensation range selection circuit105inFIG. 1and selects taps for the subcanceller104according to the procedures described referring toFIG. 5or6. The tap selector420selects the taps used by the subcanceller104based on the tap coefficients after the completion of the adaptation of the main canceller103. As a concrete example, regarding the multipliers421to423, no multiplier is assigned to unused taps; the multipliers are assigned to used taps only.

FIG. 8is a diagram illustrating the configuration of yet another embodiment of the present invention, in which a part of the circuits of the main canceller103and the subcanceller104is shared. In the present embodiment, adaptive filters are realized by memories and a DSP (digital signal processor); the canceller103and the subcanceller104inFIG. 1are constituted by memories and accumulators (multiply and add calculators), and the canceller103and subcanceller104share data memory. In the present embodiment, the canceller103and the subcanceller104are realized, by for instance, a DSP and the control software thereof.

Referring toFIG. 8, the main canceller103inFIG. 1is comprises a memory (termed “XC1coefficient memory”)502for storing the tap coefficients of the main canceller103, a multiplier505for multiplying the tap coefficients read out from the XC1coefficient memory502by transmission data read out from data memory504, and an accumulator (constituted by a adder506and a delay circuit (D register)507) for accumulating the output of the multiplier505. Further, the subcanceller104inFIG. 1comprises a memory (termed “XC2coefficient memory”)503for storing the tap coefficients of the subcanceller104, a multiplier508for multiplying the tap coefficients read out from the XC2coefficient memory503by the transmission data read out from data memory504, and an accumulator (constituted by a adder509and a delay circuit (D register)510) for accumulating the output of the multiplier508. Further, a read address generator501which generates readout addresses of the XC1coefficient memory502and the XC2coefficient memory503and a readout address of the data memory504is provided. In the present embodiment, the XC2coefficient memory503outputs the value zero to the multiplier508for the taps that the compensation range selection circuit105did not select to be used by the subcanceller104.

According to the present embodiment described above, even when the phase shift is present in the sampling phase in an A/D converter, echo/cross-talk can be reduced by generating a replica signal of echo/near-end cross-talk for every interleaved sampling phase. As described with reference toFIGS. 9 and 10, for instance, the influence of phase shifting can be suppressed by compensating only the areas with high amplitudes in the response waveform of the echo solitary wave. According to the present embodiment, echo/cross-talk can be compensated on the top of compensating phase shift in the structure where the tap coefficients of the subcanceller104for correcting phase shift are controlled by having the compensation range selection circuit105estimate the tap position where the phase shift needs to be compensated based on the tap coefficients of the main canceller103reducing echo/cross-talk after phase shift has been compensated. Further, the number of the taps and the adders in the subcanceller104can be reduced, decreasing the circuit scale and power dissipation.

Further, according to a system to which the present invention is applied, the present invention can be optionally utilized as the following devices:a canceller device that only cancels echo as a noise signal that should be removed from a received signala canceller device that only cancels cross-talk as a noise signal that should be removed from a received signala canceller device that cancels echo and cross-talk as noise signals that should be removed from a received signal.

The present invention has been illustrated using the above-described embodiments, however, it is to be understood that the present invention is not limited to the structures of the above-mentioned embodiments and covers various modifications and revisions in accordance with the principles of the present invention.