Apparatus for emulation of electronic systems

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

FIELD OF THE INVENTION

The present invention relates to electronic hardware systems. More particularly, the present invention relates to apparatus for emulation of electronic hardware system.

THE PRIOR ART

As electronic components and electronic systems have become more complex, the design of these components and systems has become a more time consuming and demanding task. Recently software simulation of electronic components and systems has become an important tool for designers. Simulation of a design is the execution of an algorithm that models the behavior of the actual design. Simulation provides the ability to analyze and verify a design without actually constructing the design and has many benefits in the design process. However, simulation suffers from three major limitations: the speed of the simulation, the need for simulation models, and the inability to actually connect a simulation of one part of a design to an actual physical implementation of another part of the design.

Simulation accelerators have come to be used to address the problems of the execution speed of simulation. A simulation accelerator uses special purpose hardware to execute simulation algorithms in order to achieve higher speeds than can be achieved using general purpose computers. None the less, simulation accelerators still execute an algorithm that models the actual design and consequently remain substantially slower than a real hardware implementation. Accelerators do not in any way obviate the need for software models of all devices to be simulated.

Physical modeling systems such as the Valid Real Chip or Daisy PMX address the problem of the lack of availability of software models for complex standard parts. They also address to some degree the speed of execution of complex software models. Physical modelers are also used in conjunction with software simulators. The modeling engine and an actual part plugged into it are used in lieu of a model of that part and are connected to a simulator which can then use the actual responses of the part in lieu of a simulation model of the part. The primary innovations in the arena of physical modeling have been associated with this connection between the modeler and the simulator.

Similar design and verification problems that arise with the use of standard microprocessors have been addressed through the use of microprocessor in-circuit emulators supplied by a number of companies. A microprocessor in-circuit emulator uses an actual microprocessor, or a specially modified version of the standard microprocessor, combined with special purpose instrumentation logic to make the job of debugging a design easier. A microprocessor in-circuit emulator includes a cable which can be plugged into a system in lieu of the actual microprocessor so that the actual system can be run at or near real time during debugging.

While all of these techniques provide advantages in the design and verification process, none satisfy all of the needs for designing and debugging including: near real time operation for non-standard parts, in-circuit emulation for other than standard parts, and freedom from the need for software models for all devices.

BRIEF DESCRIPTION OF THE INVENTION

An apparatus is disclosed and claimed which aids in the development of integrated circuit and system design by quickly and automatically generating a hardware prototype of the integrated circuit or system to be designed from the user's schematics or net list. The prototype is electrically reconfigurable and may be modified to represent an indefinite number of designs with little or no manual wiring changes or device replacement. The prototype runs at real time or close to real time speed and may be plugged directly into a larger system. VLSI chips or ASIC devices may be plugged into the prototype and run as part as the emulated design.

The apparatus of the present invention includes an emulation array, which is an array of an electrically programmable gate arrays used to implement the necessary logic functions and connect them together into a complete design. The gate arrays provide both logic implementation and signal routing between fixed printed circuit board traces. Few or no manual steps such as wire wrapping, or replacement of PALs are required to modify the design.

External cables along with a series of adaptor plugs allow the programmable breadboard to be connected directly to an existing system or printed circuit board. The apparatus of the present invention replaces a chip or board as a part of a larger system. Additional debugger hardware is included to allow internal nodes of the design to be probed and the resulting wave forms displayed without requiring the user to manually move wires. Internal nodes may also be stimulated.

A user supplied netlist or schematic is converted into a correct configuration file for use by the apparatus.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

A preferred embodiment of the apparatus of the present invention is depicted inFIG. 1a. Emulation apparatus10includes a data entry workstation12, at which a user enters information describing the electronic circuit or system which it is desired to emulate. Configuration information created by the data entry work station12is passed to configuration unit14. Configuration unit14contains the circuitry necessary to accomplish the programming of the programmable gate arrays which are contained within emulation array16.

The heart of the system of the present invention is emulation array16. Emulation array16includes a plurality of programmable gate array devices18. The programmable gate array devices18are arranged in a matrix. For illustrative purposes only, emulation array16ofFIG. 1is shown as a 3×3 matrix containing 9 total gate arrays, denoted by reference numerals18a-18i. Those of ordinary skill in the art will readily recognize that the 3×3 array depicted inFIG. 1is for illutration only and that, in an actual embodiment, the size of emulation array16is limited only by simple design choice.

In an actual implementation, emulation array16may be a three dimensional array and, in a presently preferred embodiment, consists of a plurality of circuit boards each containing a matrix of individual programmable gate array integrated circuit devices18. In a presently preferred embodiment, each card contains a 6×6 matrix of programmable gate arrays18. In the presently-preferred embodiment, an additional row of 6 programmable gate arrays exists on each card for use in test probing.

In a presently preferred embodiment, programmable gate array integrated circuit devices18may be XC3090 integrated circuits manufactured by Xilinx Corporation of San Jose, Calif. These integrated circuits and their use are described in the publicationProgrammable Gate Array Data Book, Publication No. PN0010048 01 which is expressly incorporated herein by reference.

The I/O pin wiring in between programmable gate array chips18in the present invention is illustrated with respect toFIG. 1b. FIG1bshows six programmable gate arrays in a matrix. The programmable gate array in the center, reference numeral18x, is shown having connections to its neighbors.

Each one of the programmable gate arrays18has a fixed number of its input/output (I/O) pins wired to a backplane. These I/O pins are used for intercard wiring, and inclusion of VLSI integrated circuits to be included in the emulated circuit. In a presently preferred embodiment, twenty-eight I/O pins on each gate array18xare wired to a back plane and are used for inclusion of VLSI devices in the emulated circuit. These same I/O pins may be connected, fourteen each, to corresponding programmable gate arrays (i.e., those in corresponding positions) on the circuit boards immediately above and below the board containing programmable gate array18x. These are denoted by the up and down arrows indicating fourteen lines, reference numerals19aand19b. Ten I/O pins on each gate array18are dedicated to the input/output lines of the emulated system, (not shown inFIG. 1b) and nine I/O pins are used for probing internal nodes (not shown inFIG. 1b).

The remaining ninety-six I/O pins on each gate array18are used to interconnect to input/output pins on other programmable gate arrays in the matrix. In a presently-preferred embodiment, eighteen I/O pins (reference numerals19c-f) are connected to each adjacent programmable gate array. Four I/O pins are connected to a global four bit bus connecting all gate arrays, four I/O pins are connected one each to the gate arrays in the corners of the matrix (reference numerals19g-j) and four I?O pins in each horizontal and vertical direction (reference numerals19k-n) leapfrog; i.e., are connected to the chip once removed.

To increase the richness of the interconnect possibilities of the emulation array of the present invention, the interchip connections are “wrapped around” the ends of the matrix. This means that, for instance, I/O pins of the programmable gate array chip18ainFIG. 1aare connected to the I/O pins on the programmable gate array chip18c, I/O pins on the programmable gate array18dare connected to I/O pins on the programmable gate array chip18f, and I/O pins on the programmable gate array chip18gare connected to I/O pins on the programmable gate array chip18i.

Likewise, I/O pins on the programmable gate array chip18a, are connected to I/O pins on the programmable gate array chip18g, I/O pins on the programmable gate array chip18bare connected to I/O pins on the programmable gate array chip18h, and I/O pins on the programmable gate array chip18care connected to I/O pins on the programmable gate array chip18i.

In a preferred embodiment of the system of the present invention, the emulation array16is a three dimensional array, and is composed of a plurality of cards each containing a 6×6 matrix. The intercard technique is extended in the vertical third dimension such that I/O pins on the programmable gate arrays on one level of the matrix on a given card have connections to I/O pins on the corresponding programmable gate arrays on the cards immediately above and below. In addition, connections from the arrays on the top card are wrapped around to corresponding arrays on the bottom card. In this manner, the richest possibility of interconnects and routing choices is presented.

Data entry work station12may be a presently-available work station such as those manufactured by Daisy, Mentor, and Valid Logic. Data entry workstation12generates a gate level net list from data input by the user in the manner well known in the art. Using several software programs, the operation of which is disclosed infra, data entry workstation12produces a set of files necessary to program the interconnections and logic functions within each of the programmable gate array chips in emulation array16, probing logic section20, logic analyzer/pattern generator22and interface25. Configuration unit14then configures the system using the files produced by data entry workstation12.

Probing logic section unit20includes a plurality of probing logic programmable gate arrays which, in a preferred embodiment, per circuit board, are equal in number to one of the dimensions of the matrix per card. As illustrated inFIG. 1c, six probing logic programmable gate arrays are utilized in the presently preferred embodiment where the matrix is a 6×6 matrix. These gate arrays have I/O pin interconnections to each of the programmable gate arrays in the matrix column located adjacent to these arrays. For example, the first probing logic array has a number of interconnections to programmable gate arrays18a,18d, and18gofFIG. 1a.

In a presently preferred embodiment, fifty-four I/O connections on each of the probing logic programmable gate arrays are provided to the six programmable gate arrays in the column of the matrix above it, nine of these connections per programmable gate array. In addition, each probing logic programmable gate array has connections to others. In this manner, a probing logic programmable gate array may be connected to any of the other programmable gate arrays in the entire matrix.

Probing logic unit20provides a means of connecting the logic anlayzer/pattern generator22to the desired nodes in the design contained in the emulation array16. Configuration unit14makes the connections between probing logic20and logic analyzer/pattern generator22. The pattern generator provides signals to the design configured in and running in emulation array16and the logic analyzer monitors circuit activity in the design.

The emulation array16connects to the user's external system24, such that the protion of the external system which is being emulated by the emulation array16may actually be connected into the user's external system24. One or more VLSI devices, shown at reference number26, may also be incorporated into the design being emulated by system10. In addition to VLSI devices, other circuit functions utilizing discrete components and/or integrated circuits, may be placed in reference numbers26. Provision is made for incorporated these devices by providing a number of I/O pin connections from the programmable gate arrays18out to a circuit card upon which the one or more VLSI devices, such as microprocessors and the like may be located. Outboard devices placed at reference number26may be placed there because they cannot, for one or more reasons, be effectively implemented in the array. High speed or analog circuits are two such examples.

Additionally, memory devices shown at reference numeral28inFIG. 1may be connected into the emulation array. The preferred configurations of the VLSI devices26and the memory devices28will be explained with respect toFIGS. 3 and 4respectively.

Referring now toFIG. 2, a portion of the emulation array16of the system10of the present invention is shown to include programmable gate array devices18a,18b,18d, and18e, interconnected as they would be in the matrix. In the example shown inFIG. 2, an AND-gate30is shown in programmable gate array18e, having its first input connected through conductor32on programmable gate array18a, conductor34in between gate arrays18aand18bconductor33in gate array18b, and conductor36in between gate arrays18band18e. A second input to AND-gate30is connected via conductor38in programmable gate array18dand conductor40between programmable gate array18dand18e. The output of AND-gate30is connected to conductor42out of programmable gate array18e. The connections in between programmable gate array chips, i.e.,34,36and40, are hard wired, preferably by means of printed circuit board traces, while internal connections in programmable gate array chips, i.e.,32,33and38, are made by means of the configuration information loaded into them by configuration unit14.

Those of ordinary skill in the art will readily recognize that the example shown inFIG. 2is a simplified example for illustrative purposes only and that in an actual circuit emulation, programmable gate arrays18a,18b,18d, and18eshown inFIG. 2will contain more logic functions and will be much more richly connected. In fact, once configured, the emulation array will contain the entire circuit to be emulated, with the exception of any VLSI components, which may be externally connected to the emulation array as shown with respect to FIG.3.

Referring now toFIG. 3, VLSI devices26aand26bare shown connected to emulation array16via a plurality of conductors44a-gand46a-g. In addition, bus48is shown connected both to each VLSI device and to emulation array16. Bus48is provided for bus architecture oriented VLSI devices such as microprocessors, having address and data busses, etc.

Those of ordinary skill in the art will readily recognize that the VLSI devices26aand26bare shown illustratively connected to emulation array16with only seven signal lines44a-gand46-a-gand bus48, respectively. In practice, any number of single signal connections may be made to these devices, the exact number being a matter of design choice based upon the maximum likely number of such connections which would be needed as well as the total number of signal lines available for the devices.

Referring not toFIG. 4, a presently-preferred embodiment of a memory device emulation circuit is shown. Memory devices50a,50b, and50care shown having their address, data and control lines connected to a programmable gate array device18in emulation array16. Thus, address busses52a,52b, and52cof memory devices50a,50b, and50crespectively are shown connected to programmable gate array device18as are data lines54a-cand control lines56a-c. Master address bus58, master data bus60and master control bus62connect from programmable gate array18to the emulation array16. By the appropriate programming of the interconnects in the programmable gate array matrix16the memory devices50a,50b, and50cin the circuit ofFIG. 4, may be configured to emulate memory arrays of varying widths and depths as required by the circuit being emulated.

As will be appreciated by those of ordinary skill in the art, the memory devices50a,50b, and50ccan be virtually any type of memory. The numbers of address data and control lines will vary with size and type of memory and those of ordinary skill in the art will have no difficulty realizing how to configure a memory emulation array as depicted inFIG. 4using any type of memory chips.

Referring now toFIG. 5, the interface between the emulation array16and the users external system24will be described. The interface unit (reference25ofFIG. 1) may be configured from a programmable gate array70. Programmable gate array70may also be a Xilinx XC3090 programmable gate array integrated circuit. The function of the programmable gate array70will be to provide signal mapping between the emulation array16and the user's external system24. Programmable gate array70provides connections and signal paths between the plurality of conductors coming into the programmable gate array70on lines72, and the lines74connecting programmable gate array70to the user's external system24. Another function of the programmable gate array70to provide buffering of the signals on lines72and74.

A third function of programmable gate array70is to provide local implementation of high speed logic. For certain circuit design, there may be some critical signal paths which, if routed through the emulation array, would cause system failure because of the time delay associated with signal paths involved in the emulation array16. For such circuits, the critical path logic may be implemented in the interface unit close to the user s external system to cut down the signal path time and the signal delay.

A presently-preferred embodiment, line72is a 75 ohm cable transmission line. Those of ordinary skill in the art will recognize that termination resistors, useful to prevent signal reflections at the ends of the cables should be provided at each end of the transmission lines since the line72is bi-directional and will be conducting signals in one direction or another direction depending on the particular design being emulated.

Referring now toFIG. 6, the logic analyzer and pattern generator circuitry of the present invention is seen to include a plurality of programmable gate arrays. In a presently preferred embodiment, a first data channel programmable gate array80is connected between an I/O bus82and a plurality of random access memory (RAM) chips84a-h. A common address bus86is connected to all of the RAM chips84a-hfrom data channel programmable gate array80. A data bus88is connected from the data channel programmable gate array80to the data inputs of the RAM chips84athrough84f.

A second data channel programmable gate array90is connected to the I/O bus82. A plurality of Ram chips92a-hare connected to data channel programmable gate array90via an address bus94. A data bus96connects the second data channel programmable gate array90to the data inputs of random access memory chips92a-92f. Together, first and second data channel programmable gate arrays80and90, and their associated RAM chips84a-hand92a-h, constitute a data module. The present invention may use one or more data modules. In a presently preferred embodiment, there are four data modules.

The data channel programmable gate array80and90are controlled by a control logic programmable gate array98which is connected to I/O bus82. Control lines100connect control logic programmable gate array98to data channel programmable gate arrays80and90. A time stamp bus102connects control logic programmable gate array98to the data inputs of random access memories84gandhand92gandh. The time stamp signal from control logic programmable gate array98places event time information into random access memories84gandhand92gandhsimultaneous with data from events being written into random access memories84a-fand92a-f.

Referring now toFIG. 7, the probing logic of a preferred embodiment of the present invention is disclosed. The probing logic section20contains probe programmable gate arrays110a,110band110c. Probe programmable gate arrays110a-care connected to I/O bus82.

Each of probe programmable gate arrays110a,110b, and110care connected to the programmable gate arrays in the emulation array in the column of the matrix above it. Thus, probe programmable gate array110ahas connections to emulation array programmable gate arrays18a,18d, and18g; probe programmable gate array110bhas connections to emulation array programmable gate arrays18b,18e, and18h, and probe programmable gate array110chas connections to emulation array programmable gate arrays18c,18f, and18i.

The operation of the probing logic will be shown using example illustrated in FIG.7. Those of ordinary skill in the art will readily recognize thatFIG. 7is merely an illustration and the probing logic shown inFIG. 7is generally applicable.

In the illustration ofFIG. 7, emulation array programmable gate array18ais shown to include a pair of inverters112and114. A line116is shown extending from emulation array programmable gate array18ato probe programmable gate array110a. Similarly, lines118and1209connect emulation array programmable gate arrays18dand18gto probe programmable gate array110a.

In the second column of the matrix of emulation array16, a D flip-flop122is shown in emulation array programmable gate array18e. Lines124,126, and128are shown connecting emulation array programmable gate arrays18b,18e, and18h, respectively, to probe programmable gate array110b.

In a similarly manner, lines130132, and134are shown connecting emulation array programmable gate arrays18c,18f, and18i, respectively, to probe programmable gate array110c. Those of ordinary skill in the art will readily recognize that lines116,118,120,124,126,128,130,132, and134are shown as single lines for illustrative purposes only. In any practical embodiment, a plurality of such lines may be provided so that multiple points in any of the emulation array programmable gate arrays can be probed by the probe programmable gate arrays. In a presently preferred embodiment, there are 9 lines connected from each probe programmable gate array to each emulation array programmable gate array in the column above it.

Returning to the illustrative embodiment ofFIG. 7, suppose it is desired to probe the output of invertor112. Emulation array programmable gate array18ais programmed, creating a connection between the I/O pin to which line116is connected and the node comprosing the output of inverter112and the input of inverter114.

Similarly, if the clock input of D flip-flop122inside emulation array programmable gate array18eis to be probed, that programmable gate array is programmed to create a connection between line126and the clock input of D flip-flop122. A second connection is created within one of the probe PGAs (10a-cto route the probed signal to one of the I/O Bus Signals.

The programmable gate arrays used in the various protions of the present invention are programmed by configuration unit14. The programming of the programmable gate arrays by configuration unit14may be best understood with reference to FIG.8. This discloses one presently preferred method of configuring programmable gate arrays. Other methods are available and are explained in the Xilinx data book.

For purposes of the explanation of configuration unit14, illustrative programmable gate arrays150,152,154, and156are shown inFIG. 8, although it is to be understood by those of ordinary skill in the art that programmable gate arrays150,152,154and156represent all such gate arrays in the system and that by understanding the principles herein disclosed, a particular system configured according to the present invention could have an arbitrary number of programmable gate arrays.

Data entry work station12ofFIG. 1amay be connected to the standard VME bus well understood by those of ordinary skill in the art. VME bus158inFIG. 8is the bus connected to the output of data entry work station12. The VME bus158is connected to serial to parallel converter160, and to address latch172and to Strobe generator164. The output of address latch172is address bus174, which is connected to strobe demultiplexer162, clock demultiplexer166, and verify demultiplexer170.

The serial output and serial input of serial/parallel converter160are connected to the data inputs and the data outputs, respectively, of programmable gate arrays150,152,154, and156. Strobe demultiplexer162, connected on one end to address bus174, has an output for each of the programmable gate arrays150,152,154, and156. Verify demultiplexer170is likewise connected on one end to address bus174and has an output for each of programmable gate arrays150,152,154, and156. Both strobe demultiplexer162and verify demultiplexer170are connected to strobe generator164. The function of strobe generator164is to provide an edge-activated strobe signal which either strobe demultiplexer162or verify demultiplexer170will route to the appropriate one of the programmable gate arrays150,152,154, or156. Strobe generator164is connected to the DSO data strobe line in the VME bus158.

Clock demultiplexer166is connected on one end to address bus174and has an output corresponding to each of programmable gate arrays150,152,154, and156. Clock demultiplexer166is also connected to clock generator168which is used to clock the data into programmable gate arrays150,152,154, and156.

The configuration software which runs in data entry work station12results in a series o files each of which programs one of the programmable gate array chips in the system. Information from these files is transferred to the configuration unit14as a plurality of bytes. A software routine running in the data entry work station directs the programming of all programmable gate arrays in the system using the hardware of configuration unit14. Three signals are needed to program the programmable gate arrays. The first, a clock signal, is decoded from a master clock signal by clock demultiplexer166. The second signal is a strobe signal, which is an edge triggered strobe and is decoded by strobe demultiplexer162. The strobe signal acts as an enable signal to the selected one of illustrative programmable gate arrays150,152,154, or156. The third signal used to program the programmable gate arrays is the data itself, which is sent as a serial data stream. Clock demultiplexer166is necessary because upon system power up, the nature of the presently-preferred programmable gate array devices is such that they all are enabled to receive data, thus requiring some selection process to prevent the nonselected programmable gate array chips from programming.

The data entry work station first sends an address across the VME bus which specifies address latch172. A data byte is latched into address latch172and appears on address bus174. Once the address information in address-latch172is valid, data entry workstation12sends a strobe signal over VME bus158to strobe generator164which then provides the necessary strobe signal to strobe demultiplexer162. Strobe demultiplexer162routes the strobe signal to the selected one of the programmable gate arrays150,152,154, or156. Data from VME bus158is then loaded into serial/parallel converter160. The data is then clocked out onto serial out line176which is commonly connected to the data input lines of programmable gate arrays150,152,154, and156. The clocking serial/parallel converter160is coordinated with the clocking from168, providing the clock signal to clock demultiplexer166. The clock signals from clock generator168, routed via clock demultiplexer166to the selected one of programmable gate arrays150,152,154, and156allow the serial data appearing on Sout line176of serial/parallel converter160to be taken into the appropriate programmable gate array one bit at a time. After serial/parallel converter160has been emptied, the VME bus supplies another data byte to serial/parallel converter160. The clocking of the data into the selected programmable gate array is then repeated. Each successive data byte is delayed by withholding the VME DTACK signal until the preceding byte has been shifted out of the serial/parallel converter. Another byte is loaded into serial/parallel converter160and clocked into the selected programmable gate array until all of the data bytes for the selected programmable gate array have been loaded into the array. VME bus158then loads another address into address latch172, thus selecting another programmable gate array for programming. This process is repeated until all of the programmable gate arrays in the system have been loaded with information.

After all the programmable gate arrays in the system have been loaded, the information which has been loaded into them may be verified for correctness. Verify demultiplexer170selects a programmable gate array for verification and provides a strobe signal started by VME bus158, generated by strobe generator164and routed by verify demultiplexer170. Clock168, routed to the appropriate programmable gate array via clock demultiplexer166clocks serial data out of the data output of the selected programmable gate array and into the Sin input of serial/parallel converter160. Once serial/parallel converter160has been loaded, its parallel data is placed out onto the VME bus.

This process is completely analogous to the loading process except for the data direction.

Although the data in and data out connections of programmable gate arrays150,152,154, and156are shown connected to a single serial/parallel converter176, those of ordinary skill in the art will realize that both the data in and data out connections of the programmable gate arrays may be split and buffered as is known in the art to reduce loading and noise.

Referring now toFIG. 9, a preferred routine for the loading of information into the gate arrays of the present invention is disclosed. First, at step180, the files to be loaded are inventoried. Next, at step182, the first file name is used to generate an address. Next, at step184, that address is written into address latch172. Next, at step186, a strobe signal is generated by writing to strobe generator164. At step188, a data byte is written into serial/parallel to converter160.

Next, at step190, the decision is made whether the data byte just written is the last data byte in the file. If is not, step188is repeated. If the data byte just written was the last data byte in the file, a verify signal is generated by the strobe generator at step192. Next, at step194, the data byte is read from the serial/parallel converter160. Next, at step196, it is determined whether the byte just read is the last byte in the file. If not, step194is repeated. If it was the last byte, the data read is compared to the data written at step198.

At step200it is determined whether the written data matches the read data, and if the data does not match an error is reported at step202. If the data does match, at step204it is determined whether the file just operated on is the last file. If not, the program returns to step182to process the next file. If so, the program terminates.

Data entry workstation12runs several software programs which convert the information input by the system user into information which may be used directed by configuration unit14to program all the programmable gate arrays used in the present invention. An additional software program is used to control the hardware in configuration unit14for the purposes of both programming and verifing the information in the programmable gate arrays. A block diagram of a presently-preferred software structure useful in the present invention is shown in FIG.10.

Referring now toFIG. 10, a schematics data file210is created in data entry workstation12by the user. Netlister212converts schematics data file210into netlist file214. Library file216contains information about the individual logic components which will be configured into the user's real circuit or system and which the system of the present invention will emulate. Library file216may be made up of any number of individual component model library files readily available from information provided by semiconductor and component manufacturers. The choice of which of such library files to incorporate into a system constructed in accordance with the present invention is purely a matter of the marketeer's choice, and is in no way within the scope of the present invention.

Netlister212, and library216are readily available in commercially available data entry workstations; however, the library is sometimes provided in a proprietary format, which must either be converted or substituted by a conventional format library. Schematic file210is of course, created by the user.

Netlist file214is read by netlist parser218, which places data from netlist file214into memory.

Information from netlist parser218is processed by hierarchical netlist expander220and the resulting data is linked with the data from library file216in library linker222. Parsers, linkers and netlist expanders are well-understood by those of ordinary skill in the art and are straightforwardly implemented.

The netlist information, linked with the library information by library linker222, is now a gate level net list224in a form suitable for functional implementation and timing analysis as is well understood by those of ordinary skill in the art.

The next step, shown at reference numeral226, is to partition the circuit to be emulated among the gate arrays in the emulation system. In a presently preferred embodiment, this may be accomplished by software such as that disclosed herein with respect toFIGS. 11a-e.

After partitioning, the next step in the process of configuring is a system routing, shown at reference numeral228, which assigns the connection between circuit elements to available chip to chip wiring resources. This may be accomplished by using a Lee-Moore maze router as described inLee, C. An Algorithm for Path Connections and its Applications, IRE Trans, on Electronic Computers. Vec-10 pp. 346-365, September 1961, which is expressly incorporated by reference herein.

Once the gate level netlist has been partitioned on to the programmable gate arrays, the information may be processed by software which produces information for programming the gate arrays. This step is shown at reference numeral230. Such software is available from Xilinx, Inc., of San Jose, Calif., and is known as XNF2LCA, APR, and XACT. This processing produces a set of bit stream files which may be directly loaded into the programmable gate arrays. The loading of the files into the programmable gate arrays is disclosed elsewhere herein.

At step232, timing analysis is performed. In a presently-preferred embodiment, software known as “Motive”, available from Quad Design Technology of Camarillo, Calif., may be used.

In a presently preferred embodiment,FIGS. 11a-eillustrate how partitioning may be accomplished.

Referring first inFIG. 11a, at step250, the total number of gate array chips are divided into two equal groups called “bins”. Next, at step252the fixed resources, which consist of I/O connections, probes to the circuit, VSLI connections, memory, etc., shown inFIG. 1, for example, at reference numerals24,2026and28, are placed in appropriate bins which are physically located close to the circuit elements to which they will connect.

Next, at step254all blocks in the hierarchical net list with a size greater than 66% of the bin capacity are expanded. This step breaks up large blocks into smaller pieces.

Next, at step256, all blocks are constructively placed into bins. This process is described in more detail with reference toFIG. 11c.

Next, at step258, the bin placement is iteratively improved. This process is more clearly described with reference toFIG. 11d.

Referring now toFIG. 11b, the placement by block is iteratively improved at step26. This procedure is described in detail with reference toFIG. 11e. At step262, the determination is made whether or not the size of all bins is equal to the size of a chip. If so, the placement is finished and the program terminates. If not, all blocks in the hierarchical net list with a size greater than 33% of the smallest bin presently defined are expanded. First, at step266, a bin, which this sub-routine has not yet operated on, is selected. Next, at step268, a determination is made whether the bin size is greater than the chip size. If the bin size is not greater than the chip size, this bin is marked as expanded at step270. If the bin size is greater than the chip size, the bin is expanded.

First, at step272, all blocks are removed from the bin. Next, at274the bin is divided into two bins. The division of bins is accomplished such that bins are multiples of chip sizes. For instance, if a bin is the size of three chips, this step may break the bin into one bin having the size of two chips and one bin having size of one chip.

Next at step276, the fixed resources which were in the old bin are placed into the two newly-created bins. At278, the blocks are constructively placed into the new bins. This procedure is described in detail with reference toFIG. 11c. Next, at step280these new bins are marked as having been expanded. Next, at step280a determination is made whether there are any more unexpanded bins left. If so, the program returns to step266and repeats. If not, the placement by bin is iteratively improved at step282. This routine is described in detail with reference toFIG. 11d. Next, at step284, the placement by block is iteratively improved as shown with respect toFIG. 11e. After step284, the program returns to step262to determine whether the size of all bins is equal to or greater than the size of the single chip.

Referring now toFIG. 11c, a subroutine which constructively places blocks into bins is disclosed. First, at step286the unplaced block with the most connections to already-placed blocks is selected. Next, at step288the resultant wire length if the block is placed in each bin is estimated. Next, at step290the bin having the lowest estimated wire length and space for the block is picked. Next, at step292, the block is placed in this selected bin. Next, at step294, it is determined whether there remain any more unplaced blocks. If not, the subroutine terminates. If so, the routine repeats286with respect to one of these unplaced blocks.

Referring now toFIG. 11d, the subroutine for iteratively improving the bin placement is disclosed. First, at step296, a bin is selected, next, at step298, it is determined whether the bin size or cutset size is greater than a threshold. The cutset size is equal to the number of connections which traverse bin boundaries. The threshold is based on the available wires which traverse the bin boundaries. In a presently-preferred embodiments the threshold is 80%. Therefore, if greater than 80% of the wires traversing the bin boundaries are used up, the answer is affirmative. If the bin size or cutset size does not exceed the threshold, the decision is made at step300whether all bins have been improved. If yes, the subroutine is terminated, if not the subroutine returns to step296.

If the bin size or cutset size is greater than the threshold, a block within that bin having the lowest cost to move is picked up at step302. Choosing which block to move is related to the cutset reduction and size of the block. For example, a relatively small block having a large reduction in cutset size if moved is an ideal candidate to move. On the other hand a large block having a small cutset reduction if moved is less than ideal to move.

Next, at step304, a better available bin with space is sought. The criteria for selecting this best bin include whether the block fits into the bin, whether adding the block would make the cutset exceed threshold, and whether the bin into which the block is placed, will result in the lowest overall estimated wire length. Next, at step306, it is determined whether such a bin with space has been found. If a better bin with space has been found, the block is moved to a new bin at310. If no better bin with any space has been found the unimproved bin having the lowest penalty is selected at step308and at step310the block is moved to this new bin. The subroutine than returns to step298.

Referring now toFIG. 11e, the iterative improvement by block subroutine is disclosed. First, at step312a block is randomly picked. Next, at step314, the desired location for that block in a bin is chosen. It is desired to move the block, if at all, towards the direction in which the block has the most connections. The facts which are used to make this determination are the desire to minimize the cutset count and to minimize the estimated wire length. If both of these factors have already been minimized, there is no need to move the block.

At step316, the determination is made whether there is enough room in the desired bin to place the block. If not, the block is not moved and it is determined at step318whether there are any more unpicked blocks. If not, the routine ends. If so, it returns to step312to randomly pick another block. If, at step316is has been determined that there is room in the bin for the block, the block is moved to the desired bin at step320. The routine then continues to step318at previously described.

While a presently-preferred embodiment of the invention has been disclosed, those of ordinary skill in the art will be enabled to contemplate variations from the information given in this disclosure. Such variations are intended to fall within the scope of the present invention which shall be limited only by the apended claims.