Method for manufacturing LTPS type TFT

The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.

RELATED APPLICATIONS

This application is a National Phase of PCT Patent Application No. PCT/CN2018/099101 having International filing date of Aug. 7, 2018, which claims the benefit of priority of Chinese Patent Application No. 201810396846.X filed on Apr. 28, 2018. The contents of the above applications are all incorporated by reference as if fully set forth herein in their entirety.

FIELD AND BACKGROUND OF THE INVENTION

The present disclosure relates to the field of flat panel display technology, and more particularly to an LTPS type TFT and a method for manufacturing the same.

Low temperature polysilicon (LTPS) has advantage of high electron mobility, which effectively helps reduce an area of a thin film transistor (TFT), and thus increases pixel aperture ratio of display panels. Brightness of display panels is increased, while power consumption of panels is reduced. This is helpful in decreasing manufacturing costs of panels as well. Therefore, LTPS and method for manufacturing the same have become one of the mainstream techniques used for field of liquid crystal display.

However, conventional methods for manufacturing LTPS are complicated. There are as many as ten or more film layers formed on an array substrate. Many mask processes are needed to form these films. This not only prolongs display panel manufacturing time, but also results in high manufacturing cost and high operation cost for formation thereof.

For this reason, panel manufacturers endeavor to shorten array substrate manufacturing periods, increase product manufacturing yields, increase product manufacturing efficiency, and decrease product manufacturing costs.

In the prior art, TFT generally includes a metal layer. Using a mask to form a through-hole is required in order to make electrical connection between the metal layer and a polysilicon layer, and using another mask to form another through-hole is also required in order to make electrical connection between the metal layer and a pixel electrode. Thus, according to the prior art, many masks are required to achieve electrical connection among layers in the manufacturing process of LTPS type TFT. The subject invention provides a technical scheme to solve this problem.

SUMMARY OF THE INVENTION

The present disclosure provides an LTPS type TFT and a method for manufacturing the same to solve the problem encountered by the prior art, where the method for manufacturing an LTPS type TFT is complicated.

To solve the aforementioned problem, the present disclosure provides the following technical schemes.

The present disclosure provides a method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT), comprising steps of:

providing a substrate, and forming a silicon channel layer on the substrate;

forming a first insulating layer on the silicon channel layer;

forming a first gate electrode of the TFT on the first insulating layer;

performing an ion implantation on a portion of the silicon channel layer to form a doped area, wherein the doped area includes a lightly doped area and a heavily doped area, and the heavily doped area includes a first heavily doped area and a second heavily doped area;

forming a second insulating layer, a source/drain electrode, and a third insulating layer on the first gate electrode;

forming a first contact hole on the LTPS type TFT, wherein the first contact hole exposes a portion of the source/drain electrode and a portion of the doped area; and

forming a first transparent electrode on the third insulating layer, wherein the first transparent electrode is electrically connected to the source/drain electrode and the first heavily doped area.

In accordance with one preferred embodiment of the present disclosure, the step of forming the silicon channel layer on the substrate comprises:

providing the substrate, and forming a light-shielding film on the substrate;

patterning the light-shielding film to form a light-shielding layer;

forming a buffer layer on the light-shielding layer;

forming a silicon channel film on the buffer layer; and

patterning the silicon channel film to form the silicon channel layer.

In accordance with one preferred embodiment of the present disclosure, the first contact hole passes through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that the first heavily doped area is exposed.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second contact hole, and the second contact hole passes through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that the second heavily doped area is exposed.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second gate electrode, and the second gate electrode and the first gate electrode are made of a same metal.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second transparent electrode; and

wherein the second contact hole exposes a portion of the second gate electrode and the second heavily doped area, and the second gate electrode is electrically connected to a portion of the heavily doped area via the second transparent electrode.

Additionally, the present disclosure provides a low temperature poly silicon (LTPS) type thin film transistor (TFT), comprising:

a substrate;

a light-shielding layer disposed on the substrate;

a buffer layer disposed on the light-shielding layer;

a silicon channel layer disposed on the buffer layer, wherein the silicon channel layer includes a lightly doped area and a heavily doped area formed by an ion implantation;

a first insulating layer disposed on the silicon channel layer;

a first gate electrode disposed on the first insulating layer;

a second insulating layer disposed on the first gate electrode;

a source/drain electrode disposed on the second insulating layer;

a third insulating layer disposed on the source/drain electrode;

a first contact hole passing through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, and configured to expose a portion of the heavily doped area; and

a first transparent electrode disposed on the third insulating layer, wherein the first transparent electrode is electrically connected to the source/drain electrode and the heavily doped area.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second gate electrode, and the second gate electrode and the first gate electrode are made of a same metal.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second contact hole, wherein the second contact hole passes through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area and a portion of the second gate electrode are exposed; and

the second gate electrode is electrically connected to a portion of the heavily doped area via the second transparent electrode.

The present disclosure further provides a method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT), comprising steps of:

providing a substrate and forming a silicon channel layer on the substrate;

forming a first insulating layer on the silicon channel layer;

forming a first gate electrode of the TFT on the first insulating layer;

performing an ion implantation on a portion of the silicon channel layer to form an doped area;

forming a second insulating layer, a source/drain electrode, and a third insulating layer on the first gate electrode;

forming a first contact hole on the LTPS type TFT, wherein the first contact hole exposes a portion of the source/drain electrode and a portion of the doped area; and

forming a first transparent electrode on the third insulating layer, wherein the first transparent electrode is electrically connected to the source/drain electrode and the silicon channel layer.

In accordance with one preferred embodiment of the present disclosure, the step of forming the silicon channel layer on the substrate comprises:

providing the substrate, and forming a light-shielding film on the substrate;

patterning the light-shielding film to form a light-shielding layer;

forming a buffer layer on the light-shielding layer;

forming a silicon channel film on the buffer layer; and

patterning the silicon channel film to form the silicon channel layer.

In accordance with one preferred embodiment of the present disclosure, the first contact hole passes through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that the first heavily doped area and a portion of the source/drain electrode are exposed.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second contact hole, and the second contact hole passes through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that the second heavily doped area and a portion of the second gate electrode are exposed.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second gate electrode, and the second gate electrode and the first gate electrode are made of a same metal.

In accordance with one preferred embodiment of the present disclosure, the LTPS type TFT further comprises a second transparent electrode; and

wherein the second contact hole exposes a portion of the second gate electrode and the second heavily doped area, and the second gate electrode is electrically connected to a portion of the heavily doped area via the second transparent electrode.

According to the present disclosure, the TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area. Therefore, quantity of masks used to form the contact hole is reduced, decreasing manufacturing time of a panel and decreasing manufacturing cost thereof.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

The following embodiments refer to the accompanying drawings for exemplifying specific implementable embodiments of the present disclosure. Moreover, directional terms described by the present disclosure, such as upper, lower, front, back, left, right, inner, outer, side, etc., are only directions by referring to the accompanying drawings, and thus the used directional terms are used to describe and understand the present disclosure, but the present disclosure is not limited thereto. In the drawings, the same reference symbol represents the same or similar components.

FIG. 1shows a flowchart of a method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT) according to a first embodiment of the present disclosure. The method includes the following steps.

In a step S101, a substrate101is provided, and a silicon channel layer104is formed on the substrate101.

Specifically, as shown inFIGS. 2A-2B, this step includes the following steps.

In a step S1011, a substrate101is provided, and then a light-shielding film is formed on the substrate101.

The substrate101can be a glass substrate, a silicon substrate, or a resin substrate.

The light-shielding film is made of a black light-shielding material, but is not limited thereto.

In a step S1012, the light-shielding film is patterned to form a light-shielding layer102.

Specifically, a first mask process is performed on the light-shielding film. That is, a first photoresist layer (not shown) is formed on the light-shielding film first, and then a mask (not shown) is used to perform an exposure treatment. Next, after a development treatment and a first etching process are carried out, the light-shielding film is patterned to form the light-shielding layer102, as shown inFIG. 2A. Finally, the first photoresist layer is removed.

In a step S1013, a buffer layer103is formed on the light-shielding layer102.

In a step S1014, a silicon channel film is formed on the buffer layer103.

In a step S1015, the silicon channel film is patterned to form the silicon channel layer104.

In one preferred embodiment, the silicon channel film is made of polysilicon. A second mask process is performed on the silicon channel film. That is, a second photoresist layer (not shown) is formed on the silicon channel film first, and then a mask (not shown) is used to perform an exposure treatment. Next, after a development treatment and a second etching process are carried out, the silicon channel film is patterned to form the silicon channel layer104, as shown inFIG. 2B. Finally, the second photoresist layer is removed.

In a step S102, a first insulating layer105is formed on the silicon channel layer.

In one preferred embodiment, the first insulating layer105is a gate insulating layer. The gate insulating layer covers the silicon channel layer104. The gate insulating layer is configured to isolate the silicon channel layer104from other metal layers. Preferably, the gate insulating layer is made of silicon nitride, silicon oxide, or silicon oxynitride.

In a step S103, a first gate electrode106of the TFT is formed on the first insulating layer105.

Specifically, a first metal layer is formed on the first insulating layer105first. The first metal layer can be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or any combination thereof.

Thereafter, a third mask process is performed on the first metal layer. That is, a third photoresist layer107is formed on the first metal layer first, and then a mask (not shown) is used to perform an exposure treatment. Next, after a development treatment and a third etching process are carried out, the first metal layer is patterned to form the first gate electrode106of the TFT, as shown inFIG. 2C. The third photoresist layer107is retained.

In a step S104, an ion implantation is performed on a portion of the silicon channel layer104to form a doped area.

Specifically, as shown inFIGS. 2C-2D, this step includes the following steps.

In a step S1041, a first ion implantation is performed on a portion of the silicon channel layer104to form a heavily doped area1041and1042.

In this step, the third photoresist layer107and the first gate electrode106server as a barrier layer, and a first ion implantation is performed on the silicon channel layer104to form a heavily doped area. In one preferred embodiment, the implanted ions are high concentration of N+ions. The doped area is a heavily doped area1041and1042. The heavily doped area includes a first heavily doped area1041and a second heavily doped area1042, which are disposed at two ends of the silicon channel layer104, as shown inFIG. 2C.

In a step S1042, an exposure treatment and a development treatment are carried out on the third photoresist layer107, and the first gate electrode106is patterned by a fourth etching process.

This step is performed for etching the first gate electrode106in order to reduce area occupied by the first gate electrode106. In other words, a mask process is required to be carried out for the third photoresist layer107.

In a step S1043, a second ion implantation is performed on a portion of the silicon channel layer104to form a lightly doped area1043.

In this step, the third photoresist layer107and the first gate electrode106after being further patterned server as a barrier layer, and a second ion implantation is performed on the silicon channel layer104to form a lightly doped area1043. The lightly doped area1043is disposed between the heavily doped area1041and1042and the silicon channel layer104. In one preferred embodiment, the implanted ions are high concentration of N−ions, as shown inFIG. 2D.

In a step S1044, the third photoresist layer107is removed.

For formation of the third photoresist layer107, a half-tone mask could be used for the third photoresist layer, so as to form the third photoresist layer107having different thicknesses after being developed. The area of the photoresist layer having smaller thickness corresponds to the lightly doped area1043, and the area of the photoresist layer having larger thickness corresponds to the silicon channel layer104that is not doped by ion implantation.

After the heavily doped area1041and1042are doped by ion implantation, an oxygen plasma ashing treatment is carried out on the third photoresist layer107, so that the area of the photoresist layer having larger thickness is thinned, and the area of the photoresist layer having smaller thickness is removed, so as to form a pattern of the photoresist layer as shown inFIG. 2D. Thereafter, a second etching process is carried out on the first gate electrode106.

In a step S105, a second insulating layer108, a source/drain electrode109, and a third insulating layer110are formed on the first gate electrode106.

Specifically, as shown inFIGS. 2E-2F, this step includes the following steps.

In a step S1051, a second insulating layer108is formed on the first gate electrode106.

In a step S1052, a source/drain electrode109is formed on the second insulating layer108.

In a step S1053, a third insulating layer110is formed on the source/drain electrode109.

The second insulating layer108formed is an interdielectric layer, which covers the first gate electrode106, and is configured to isolate the first gate electrode106from the source/drain electrode109.

Then, a second metal layer is formed on the second insulating layer108. The second metal layer can be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, titanium-aluminum alloy, or any combinations thereof.

Thereafter, a fourth mask process is performed on the second metal layer. That is, a fourth photoresist layer (not shown) is formed on the second metal layer first, and then a mask (not shown) is used to perform an exposure treatment. Next, after a development treatment and a fifth etching process are carried out, the second metal layer is patterned to form the source/drain electrode109of the TFT, as shown inFIG. 2E. Then, the fourth photoresist layer is removed. Finally, a third insulating layer110is formed on the source/drain electrode109. The third insulating layer110serves as a planarization layer.

In a step S106, a first contact hole111is formed on the LTPS type TFT, where the first contact hole111exposes a portion of the source/drain electrode109and a portion of the doped area.

Specifically, as shown inFIG. 2F, an etching process is carried out on the TFT to form a contact hole111. The contact hole111passes through the third insulating layer110, the second insulating layer108, and a portion of the first insulating layer105, and exposes the first heavily doped area1041or the second heavily doped area1042and a portion of the source/drain electrode109. Since the first insulating layer105, the second insulating layer108, and the third insulating layer110are made of generally the same material, only a single one etching process is required to form the first contact hole111.

In a step S107, a first transparent electrode112is formed on the third insulating layer110, where the first transparent electrode is electrically connected to the source/drain electrode109and the silicon channel layer104.

Specifically, as shown inFIG. 2G, a first transparent electrode112is formed on the third insulating layer110. The first transparent electrode112is electrically connected to the source/drain electrode109and the first heavily doped area1041or the second heavily doped area1042via the first contact hole111.

According to the present disclosure, a single one etching process is carried out to form the first contact hole passing through the third insulating layer, the second insulating layer, and a portion of the first insulating layer. In addition, the position of the source/drain electrode is adequately adjusted to have the source/drain electrode not cover the heavily doped area. The first transparent electrode is electrically connected to the source/drain electrode and the first heavily doped area or the second heavily doped area via the first contact hole111. Therefore, quantity of masks used to form the contact hole is reduced, decreasing manufacturing time of a panel and decreasing manufacturing cost thereof.

FIG. 3shows a flowchart of a method for manufacturing a low temperature poly silicon (LTPS) type thin film transistor (TFT) according to a second embodiment of the present disclosure. The method includes the following steps.

In a step S201, a substrate201is provided, and a silicon channel layer204is formed on the substrate201.

Specifically, as shown inFIGS. 4A-4B, this step includes the following steps.

In a step S2011, a substrate201is provided, and then a light-shielding film is formed on the substrate201.

In a step S2012, the light-shielding film is patterned to form a light-shielding layer202.

In a step S2013, a buffer layer203is formed on the light-shielding layer202.

In a step S2014, a silicon channel film is formed on the buffer layer203.

In a step S2015, the silicon channel film is patterned to form the silicon channel layer204.

In a step S202, a first insulating layer205is formed on the silicon channel layer204.

In the present embodiment, the steps S201and S202are the same as the steps S101and S102of EMBODIMENT 1, and thus description thereof is omitted to avoid redundancy.

In a step S203, a first gate electrode206and a second gate electrode207of the TFT are formed on the first insulating layer205.

Specifically, a first metal layer is formed on the first insulating layer205first. The first metal layer can be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or any combinations thereof.

Thereafter, a third mask process is performed on the first metal layer. That is, a third photoresist layer208is formed on the first metal layer first, and then a mask (not shown) is used to perform an exposure treatment. Next, after a development treatment and a third etching process are carried out, the first metal layer is patterned to form the first gate electrode206and the second gate electrode207of the TFT, as shown inFIG. 4C. The third photoresist layer208on the first gate electrode206and the second gate electrode207is retained.

In a step S204, an ion implantation is performed on a portion of the silicon channel layer204to form a doped area.

Specifically, as shown inFIGS. 4C-4D, this step includes the following steps.

In a step S2041, a first ion implantation is performed on a portion of the silicon channel layer204, which is not blocked by the first gate electrode206, to form a heavily doped area2041and2042.

In a step S2042, an exposure treatment and a development treatment are carried out on the third photoresist layer208, and the first gate electrode206is patterned by a fourth etching process.

In a step S2043, a second ion implantation is performed on a portion of the silicon channel layer204, which is not blocked by the first gate electrode206after the first gate electrode206is patterned, to form a lightly doped area2043.

In a step S2044, the third photoresist layer208is removed.

In a step S205, a second insulating layer209, a source/drain electrode210, and a third insulating layer211are formed on the first gate electrode206and the second gate electrode207.

Specifically, as shown inFIG. 4E, this step includes the following steps.

In a step S2051, a second insulating layer209is formed on the first gate electrode206and the second gate electrode207.

In a step S2052, a source/drain electrode210is formed on the second insulating layer209.

In a step S2053, a third insulating layer211is formed on the source/drain electrode210.

In the present embodiment, the steps S204and S205are the same as the steps S104and S105of EMBODIMENT 1, and thus description thereof is omitted to avoid redundancy.

In a step S206, a first contact hole212and a second contact hole213are formed on the LTPS type TFT, where the first contact hole212exposes a portion of the source/drain electrode210and a portion of the doped area, and the second contact hole213exposes a portion of the second gate electrode207and a portion of the doped area.

Specifically, as shown inFIG. 4F, an etching process is carried out on the TFT to form a first contact hole212and a second contact hole213.

The first contact hole212passes through the third insulating layer211, the second insulating layer209, and a portion of the first insulating layer205, and exposes the first heavily doped area2041and a portion of the source/drain electrode210.

The second contact hole213passes through the third insulating layer211, the second insulating layer209, and a portion of the first insulating layer205, and exposes the second heavily doped area2042and a portion of the second gate electrode207.

Since the first insulating layer205, the second insulating layer209, and the third insulating layer211are made of generally the same material, only a single one etching process is required to form the first contact hole212and the second contact hole213.

In a step S207, a first transparent electrode214and a second transparent electrode215are formed on the third insulating layer211, where the first transparent electrode214is electrically connected to the source/drain electrode210and the silicon channel layer204, and the second transparent electrode215is electrically connected to the second gate electrode207and the silicon channel layer204.

Specifically, as shown inFIG. 4G, a first transparent electrode214and a second transparent electrode215are formed on the third insulating layer211.

The first transparent electrode214is electrically connected to the source/drain electrode210and the first heavily doped area2041via the first contact hole212. The second transparent electrode215is electrically connected to the second gate electrode207and the second heavily doped area2042via the second contact hole213.

According to the present disclosure, a single one etching process is carried out to form the first contact hole and the second contact hole passing through the third insulating layer, the second insulating layer, and a portion of the first insulating layer. In addition, the first contact hole and the second contact hole expose a portion of the heavily doped area. And, the transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area. Therefore, quantity of masks used to form the contact hole is reduced, decreasing manufacturing time of panels and decreasing manufacturing costs thereof.

FIG. 5is a schematic diagram showing a cross-sectional view of a structure of an LTPS type TFT according to a third embodiment of the present disclosure. The LTPS type TFT includes a substrate301, a light-shielding layer302, a buffer layer303, a silicon channel layer304, a first insulating layer305, a first gate electrode306, a second insulating layer308, a source/drain electrode309, a third insulating layer310, a first contact hole311, and a first transparent electrode312.

The substrate101can be a glass substrate, a silicon substrate, or a resin substrate.

The light-shielding layer302is formed on the substrate301. The light-shielding layer302is made of a black light-shielding material, but is not limited thereto.

The buffer layer303is formed on the light-shielding layer302.

The silicon channel layer304is formed on the buffer layer303. The silicon channel layer304is composed polysilicon. The silicon channel layer304includes a lightly doped area3043and a heavily doped area3041and3042that are doped by ion implantation. The heavily doped area3041and3042includes a first heavily doped area3041and a second heavily doped area3042, which are disposed at two ends of the silicon channel layer304. The lightly doped area3043is disposed between the silicon channel layer304and the heavily doped area3041and3042. The heavily doped area3041and3042are doped by high concentration of N+ions, and the lightly doped area3043is doped by low concentration of N−ions.

The first insulating layer305is formed on the silicon channel layer304. The first insulating layer305is a gate insulating layer. The gate insulating layer covers the silicon channel layer304. The gate insulating layer is configured to isolate the silicon channel layer304from other metal layers. Preferably, the gate insulating layer is made of silicon nitride, silicon oxide, or silicon oxynitride.

The first gate electrode306is formed on the first insulating layer305. The first gate electrode306can be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, copper, or any combinations thereof.

The second insulating layer308is formed on the first gate electrode306. The second insulating layer308is an interdielectric layer, which covers the first gate electrode306, and is configured to isolate the first gate electrode306from the source/drain electrode309.

The third insulating layer310is formed on the source/drain electrode309. The third insulating layer310serves as a planarization layer or a passivation layer.

The first contact hole311passes through the third insulating layer310, the second insulating layer308, and a portion of the first insulating layer305, and exposes the heavily doped area and a portion of the source/drain electrode309. Since the first insulating layer305, the second insulating layer308, and the third insulating layer310are made of generally the same material, only a single one etching process is required to form the first contact hole311.

The first transparent electrode312is formed on the third insulating layer310. The first transparent electrode312is electrically connected to the source/drain electrode309and the heavily doped area via the first contact hole311.

FIG. 6is a schematic diagram showing a cross-sectional view of a structure of an LTPS type TFT according to a fourth embodiment of the present disclosure. The LTPS type TFT further includes a second gate electrode407. The second gate electrode407and the first gate electrode406are formed from a metal layer at the same time.

The LTPS type TFT further includes a second contact hole413. The second contact hole413passes through the third insulating layer411, the second insulating layer409, and a portion of the first insulating layer405, and exposes the second heavily doped area4042and a portion of the second gate electrode407.

The LTPS type TFT further includes a second transparent electrode415. The second transparent electrode415and the first transparent electrode414are formed in a same process. A portion of the second gate electrode407is electrically connected to a portion of the second heavily doped area4042via the second transparent electrode415.

The present disclosure provides an LTPS type TFT and a method for manufacturing the same. According to the present disclosure, the TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area. Therefore, quantity of masks used to form the contact hole is reduced, decreasing manufacturing time of a panel and decreasing manufacturing cost thereof.

While the present disclosure has been described with the aforementioned preferred embodiments, it is preferable that the above embodiments should not be construed as limiting of the present disclosure. Anyone having ordinary skill in the art can make a variety of modifications and variations without departing from the spirit and scope of the present disclosure as defined by the following claims.