Three-dimensional processor for parallel computing

A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.

BACKGROUND

1. Technical Field of the Invention

The present invention relates to the field of integrated circuit, and more particularly to processors.

2. Prior Art

Conventional processors use logic-based computation (LBC), which carries out computation primarily with logic circuits (e.g. XOR circuit). Conventional logic circuits are suitable for arithmetic functions, whose operations include only basic arithmetic operations, i.e. the arithmetic operations performable by the conventional logic circuits per se. As is well known in the art, the basic arithmetic operations consist of addition, subtraction and multiplication. However, the conventional logic circuits are not suitable for non-arithmetic functions, whose operations include more than the basic arithmetic operations. Because they cannot be represented by a combination of the basic arithmetic operations, the non-arithmetic functions cannot be implemented by the conventional logic circuits alone. Exemplary non-arithmetic functions include transcendental functions and special functions. Non-arithmetic functions are computationally hard and their hardware implementation has been a major challenge.

For the conventional processors, only few basic non-arithmetic functions (e.g. basic algebraic functions and basic transcendental functions) are implemented by hardware and they are referred to as built-in functions. These built-in functions are realized by a combination of logic circuits and look-up tables (LUT). For example, U.S. Pat. No. 5,954,787 issued to Eun on Sep. 21, 1999 taught a method for generating sine/cosine functions using LUTs; U.S. Pat. No. 9,207,910 issued to Azadet et al. on Dec. 8, 2015 taught a method for calculating a power function using LUTs.

Realization of built-in functions is further illustrated inFIG.1A. A conventional processor300generally comprises a logic circuit380and a memory circuit370. The logic circuit380comprises an arithmetic logic unit (ALU) for performing arithmetic operations, while the memory circuit370stores an LUT for the built-in function. To obtain a desired precision, the built-in function is approximated to a polynomial of a sufficiently high order. The LUT370stores the coefficients of the polynomial; and the ALU380calculates the polynomial. Because the ALU380and the LUT370are formed side-by-side on a semiconductor substrate0, this type of horizontal integration is referred to as two-dimensional (2-D) integration.

Computation has been developed along the directions of computational density and computational complexity. The computational density is a figure of merit for parallel computation and it refers to the computational power (e.g. the number of floating-point operations per second) per die area. The computational complexity is a figure of merit for scientific computation and it refers to the total number of built-in functions supported by a processor. The 2-D integration severely limits computational density and computational complexity.

For the 2-D integration, inclusion of the LUT370increases the die size of the conventional processor300and lowers its computational density. This has an adverse effect on parallel computation. Moreover, because the ALU380is the primary component of the conventional processor300and occupies a large die area, the LUT370is left with a small die area and only supports few built-in functions.FIG.1Blists all built-in transcendental functions supported by an Intel Itanium (IA-64) processor (referring to Harrison et al. “The Computation of Transcendental Functions on the IA-64 Architecture”, Intel Technical journal, Q4 1999, hereinafter Harrison). The IA-64 processor supports a total of 7 built-in transcendental functions, each using a relatively small LUT (from 0 to 24 kb) in conjunction with a relatively high-degree Taylor-series calculation (from 5 to 22).

This small set of built-in functions (˜10 types, including arithmetic operations) is the foundation of scientific computation. Scientific computation uses advanced computing capabilities to advance human understandings and solve engineering problems. It has wide applications in computational mathematics, computational physics, computational chemistry, computational biology, computational engineering, computational economics, computational finance and other computational fields. The prevailing framework of scientific computation comprises three layers: a foundation layer, a function layer and a modeling layer. The foundation layer includes built-in functions that can be implemented by hardware. The function layer includes mathematical functions that cannot be implemented by hardware (e.g. non-basic non-arithmetic functions). The modeling layer includes mathematical models, which are the mathematical descriptions of the input-output characteristics of a system component.

The mathematical functions in the function layer and the mathematical models in the modeling layer are implemented by software. The function layer involves one software-decomposition step: mathematical functions are decomposed into combinations of built-in functions by software, before these built-in functions and the associated arithmetic operations are calculated by hardware. The modeling layer involves two software-decomposition steps: the mathematical models are first decomposed into combinations of mathematical functions; then the mathematical functions are further decomposed into combinations of built-in functions. Apparently, the software-implemented functions (e.g. mathematical functions, mathematical models) run much slower and less efficient than the hardware-implemented functions (i.e. built-in functions), and extra software-decomposition steps (e.g. for mathematical models) would make these performance gaps even more pronounced.

Because the arithmetic operations performable by the ALC consist of addition, subtraction and multiplication, the mathematical models that can be represented by the ALC alone are linear models only. Typical mathematical models are nonlinear and cannot be represented by a combination of these arithmetic operations. To illustrate how computationally intensive a mathematical model could be,FIGS.2A-2Bdisclose a simple example—the simulation of an amplifier circuit20. The amplifier circuit20comprises a transistor24and a resistor22(FIG.2A). All transistor models (e.g. MOS3, BSIM3 V3.2, BSIM4 V3.0, PSP ofFIG.2B) model the transistor behaviors based on the small set of built-in functions provided by the conventional processor300. Due to the limited choice of the built-in functions, calculating even a single current-voltage (I-V) point for the transistor24requires a large amount of computation (FIG.2B). As an example, the BSIM4 V3.0 transistor model needs 222 additions, 286 multiplications, 85 divisions, 16 square-root operations, 24 exponential operations, and 19 logarithmic operations. This large amount of computation makes simulation extremely slow and inefficient.

Three-dimensional memory (3D-M) has a larger storage capacity than the conventional two-dimensional memory (2D-M). U.S. Pat. No. 5,835,396, issued to Zhang on Nov. 10, 1998, discloses a three-dimensional read-only memory (3D-ROM) comprising a plurality of memory levels vertically stacked on a semiconductor substrate. Because all of its address lines are horizontal, the 3D-ROM of Zhang is a horizontal 3D-M. On the other hand, U.S. Pat. No. 8,638,611, issued to Sim et al. on Jan. 28, 2014, discloses another 3D-M. It comprises a plurality of memory strings disposed on a semiconductor substrate. Each vertical string contains a plurality of vertically stacked memory cells. Because a set of its address lines are vertical, the 3D-M of Sim is a vertical 3D-M. Being monolithic, the memory cells of the 3D-M are not in contact with any semiconductor substrate and there is no semiconductor substrate between these memory cells.

Disposed above the semiconductor substrate, the memory cells of the 3D-M are made of semiconductor materials in polycrystalline or amorphous form, i.e. the memory cells of the 3D-M do not comprise any single-crystalline semiconductor material. On the other hand, the memory cells of the conventional 2D-M, disposed in the semiconductor substrate, are made of semiconductor materials in a single-crystalline form, i.e. the memory cells of the 2D-M comprise at least a single-crystalline semiconductor material. Because the non-single-crystalline (e.g. polycrystalline or amorphous) semiconductor materials are inferior in performance than the single-crystalline semiconductor materials, a 3D-M cell is generally slower in speed than a 2D-M cell. Accordingly, although it has a larger storage capacity, the 3D-M was considered not suitable for high-performance computation (HPC), e.g. as an embedded memory in a high-speed processor.

Objects and Advantages

It is a principle object of the present invention to provide a paradigm shift for scientific computation.

It is a further object of the present invention to reverse the general expectation that the three-dimension memory is not suitable for high-performance computation (HPC).

It is a further object of the present invention to provide a processor with improved computational complexity.

It is a further object of the present invention to provide a processor with a large set of built-in functions.

It is a further object of the present invention to realize non-arithmetic functions rapidly and efficiently.

It is a further object of the present invention to realize rapid and efficient modeling and simulation.

It is a further object of the present invention to provide a processor with improved computational density.

In accordance with these and other objects of the present invention, the present invention discloses a three-dimensional processor (3D-processor) for parallel computing.

SUMMARY OF THE INVENTION

The present invention discloses a three-dimensional processor (3D-processor) for parallel computing. It comprises a semiconductor substrate and an array of computing elements thereon. Each computing element comprises an arithmetic logic circuit (ALC) formed on the semiconductor substrate and at least a three-dimensional memory (3D-M) array stacked above the ALC. The 3D-M array stores at least a portion of a look-up table (LUT, or 3DM-LUT) for a mathematical function, while the ALC performs arithmetic operations on selected 3DM-LUT data. The mathematical function implemented by the computing element is a non-arithmetic function, which includes more operations than arithmetic operations performable by the ALC. The 3D-M array and the ALC are communicatively coupled through a plurality of inter-storage-processor (ISP) connections, e.g. contact vias.

The present invention further discloses a memory-based computation (MBC), which carries out computation primarily with the 3DM-LUT. Compared with the conventional logic-based computation (LBC), the 3DM-LUT used by the MBC has a much larger capacity than the conventional LUT. Although arithmetic operations are still performed for most MBCs, using a larger LUT as a starting point, the MBC only needs to calculate a polynomial to a smaller order. For the MBC, the fraction of computation done by the 3DM-LUT is significantly more than the ALC.

Because the 3D-M array is stacked above the ALC, this type of vertical integration is referred to as three-dimensional (3-D) integration. The 3-D integration has a profound effect on the computational density. Because the 3D-M array does not occupy any substrate area, the footprint of the computing element is roughly equal to that of the ALC. However, the footprint of a conventional processor is roughly equal to the sum of the footprints of the LUT and the ALU. By moving the LUT from aside to above, the computing element becomes smaller. The 3D-processor would contain more computing elements, become more computationally powerful and support massive parallelism. Preferably, a 3D-processor comprises at least one thousand computing elements, and in some cases, at least ten thousand computing elements. Although each individual 3D-M cell is slower than a 2D-M cell, this deficiency in speed can be offset by a significantly larger scale of parallelism. As a result, the 3D-processor becomes suitable for high-performance computation.

The 3-D integration also has a profound effect on the computational complexity. Because it supports the 3-D integration and has a much larger storage capacity than the conventional 2D-M, the 3D-M in the preferred 3D-processor has a total LUT capacity of at least one gigabit, and in some cases, at least ten gigabits, which is large enough to support a larger LUT for each mathematical functions and a significantly larger scale of parallelism. For example, since the total 3DM-LUT capacity for a single 3D-processor die could reach 100 Gb (for example, a 3D-XPoint die has a storage capacity of 128 Gb), a single 3D-processor die could support as many as ten thousand built-in functions, which are orders of magnitude more than the conventional processor.

Significantly more built-in functions shall flatten the prevailing framework of scientific computation (including the foundation, function and modeling layers). The hardware-implemented functions, which were only available to the foundation layer, now become available to the function and modeling layers. Not only mathematical functions in the function layer can be directly realized by hardware, but also mathematical models in the modeling layer can be directly described by hardware. In the function layer, mathematical functions can be realized by a function-by-LUT method, i.e. the function values are calculated by reading the 3DM-LUT plus polynomial interpolation. In the modeling layer, mathematical models can be described by a model-by-LUT method, i.e. the input-output characteristics of a system component are modeled by reading the 3DM-LUT plus polynomial interpolation. Rapid and efficient computation would lead to a paradigm shift for scientific computation.

Accordingly, the present invention discloses a three-dimensional processor (3D-processor) for parallel computing, comprising a single-crystalline semiconductor substrate and a plurality of computing elements including first and second computing elements disposed thereon, each of said computing elements comprising: at least a three-dimensional memory (3D-M) array including a plurality of vertically stacked memory cells for storing at least a portion of a look-up table (LUT) for a mathematical function, wherein said memory cells are neither in contact with nor interposed by any semiconductor substrate including said single-crystalline semiconductor substrate; and, said memory cells do not comprise any single-crystalline semiconductor material; an arithmetic logic circuit (ALC) disposed on said single-crystalline semiconductor substrate, wherein said ALC performs at least one arithmetic operation on selected data from said LUT; and, transistors in said ALC comprise at least a single-crystalline semiconductor material; a plurality of inter-storage-processor (ISP) connections entirely disposed between said 3D-M array and said single-crystalline semiconductor substrate for communicatively coupling said memory cells and said single-crystalline semiconductor substrate, wherein said ISP-connections do not penetrate through any semiconductor substrate including said single-crystalline semiconductor substrate; wherein said first and second computing elements calculate the values of respective mathematical function in parallel.

The present invention further discloses a 3D-processor for parallel computing, comprising a single-crystalline semiconductor substrate and a plurality of computing elements including first and second computing elements disposed thereon, each of said computing elements comprising: at least a three-dimensional vertical memory (3D-MV) array including a plurality of vertically stacked memory cells for storing at least a portion of a look-up table (LUT) for a mathematical function, wherein said memory cells are neither in contact with nor interposed by any semiconductor substrate including said single-crystalline semiconductor substrate; and, said memory cells do not comprise any single-crystalline semiconductor material; an arithmetic logic circuit (ALC) disposed on said single-crystalline semiconductor substrate, wherein said ALC performs at least one arithmetic operation on selected data from said LUT; and, transistors in said ALC comprise at least a single-crystalline semiconductor material; a plurality of inter-storage-processor (ISP) connections entirely disposed between said 3D-MVarray and said single-crystalline semiconductor substrate for communicatively coupling said memory cells and said single-crystalline semiconductor substrate, wherein said ISP-connections do not penetrate through any semiconductor substrate including said single-crystalline semiconductor substrate; wherein said first and second computing elements calculate the values of respective mathematical function in parallel.

It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments.

Throughout this specification, the phrase “mathematical functions” refer to non-arithmetic functions only, it could also refer to mathematical models; the phrase “memory” is used in its broadest sense to mean any semiconductor-based holding place for information, either permanent or temporary; the phrase “permanent” is used in its broadest sense to mean any long-term storage; the phrase “communicatively coupled” is used in its broadest sense to mean any coupling whereby information may be passed from one element to another element; the phrase “on the substrate” means the active elements of a circuit (e.g. transistors) are formed on the surface of the substrate, although the interconnects between these active elements are formed above the substrate and do not touch the substrate; the phrase “above the substrate” means the active elements (e.g. memory cells) are formed above the substrate and do not touch the substrate; the term “3DM-LUT” refers to the look-up table (LUT) stored in the three-dimensional memory (3D-M) array(s), or the physical LUT circuit in the form of the 3D-M array(s); the symbol “/” means a relationship of “and” or “or”.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.

Referring now toFIG.3A-3B, a preferred three-dimensional processor (3D-processor)100is disclosed. It comprises a semiconductor substrate0and an array of computing elements110-1,110-2. . .110-i. . .110-N formed thereon (FIG.3A). These computing elements110-1. . .110-N could realize a same function or different functions. Each computing element110-ihas one or more input variables150, and one or more output variables190(FIG.3B). It further comprises at least a three-dimensional memory (3D-M) array170for storing at least a portion of the 3DM-LUT for a mathematical function and an arithmetic logic circuit (ALC)180for performing arithmetic operations on selected 3DM-LUT data. The mathematical function implemented by the computing element110-iis a non-arithmetic function, which includes more operations than arithmetic operations performable by the ALC180. The ALC180and the 3D-M array170are communicatively coupled by inter-storage-processor (ISP) connections160. Examples of the ISP connections160include contact vias between the 3D-M array170and the ALC180. Formed on a different physical level than the ALC180, the 3D-M array170is represented by dotted line in all figures.

The 3D-processor100uses memory-based computation (MBC), which carries out computation primarily with the 3DM-LUT170. Compared with the conventional logic-based computation (LBC), the 3DM-LUT170used by the MBC has a much larger capacity than the conventional LUT370. Although arithmetic operations are still performed for most MBCs, using a larger LUT as a starting point, the MBC only needs to calculate a polynomial to a smaller order. For the MBC, the fraction of computation done by the 3DM-LUT170could be more than the ALC180.

FIGS.4A-4Care the block diagrams of three preferred ALC180. The first preferred ALC180comprises an adder180A, the second preferred ALC180comprises a multiplier180M, with the third preferred ALC180comprising a multiply-accumulator (MAC), which includes an adder180A and a multiplier180M. The preferred ALC180could perform integer arithmetic operations, fixed-point arithmetic operations, or floating-point arithmetic operations.

Referring now toFIGS.5A-5D, four preferred computing elements110-1comprising different 3D-M arrays170are disclosed. Since the ALC180of the preferred computing element110-1is formed on a single-crystalline semiconductor substrate0, transistors in the ALC180comprises at least a single-crystalline semiconductor material. On the other hand, each 3D-M array170comprises a plurality of vertically stacked memory cells. Because they are not in contact with any semiconductor substrate and there is no semiconductor substrate between memory cells, memory cells do not comprise any single-crystalline semiconductor material. Note that the ALC180is formed on a top surface of the single-crystalline semiconductor substrate0, while the 3D-M array170is formed above the top surface of the single-crystalline semiconductor substrate0.

3D-M can be categorized into 3D-RAM (random access memory) and 3D-ROM (read-only memory). As used herein, the phrase “RAM” is used in its broadest sense to mean any memory which holds information temporarily. Exemplary RAM includes SRAM and DRAM; the phrase “ROM” is used in its broadest sense to mean any memory which holds information for a long time, even when power goes off. ROM is also referred to as non-volatile memory (NVM). The 3D-ROM is further categorized into 3-D writable memory (3D-W) and 3-D printed memory (3D-P).

For 3D-W, data can be electrically written (or, programmable). Based on the number of programmings allowed, a 3D-W can be categorized into three-dimensional one-time-programmable memory (3D-OTP) and three-dimensional multiple-time-programmable memory (3D-MTP). The 3D-OTP can be written once, while the 3D-MTP is electrically re-programmable. 3D-MTP include memristor, resistive random-access memory (RRAM or ReRAM), phase-change memory, programmable metallization cell (PMC), conductive-bridging random-access memory (CBRAM), and the like. For 3D-W, the 3DM-LUT170can be configured in the field. This becomes even better for 3D-MTP, as the 3DM-LUT170would become re-configured.

For 3D-P, data are recorded thereto using a printing method during manufacturing. These data are fixedly recorded and cannot be changed after manufacturing. The printing methods include photo-lithography, nano-imprint, e-beam lithography, DUV lithography, and laser-programming, etc. An exemplary 3D-P is three-dimensional mask-programmed read-only memory (3D-MPROM), whose data are recorded by photo-lithography. Because electrical programming is not required, a memory cell in the 3D-P can be biased at a larger voltage during read than the 3D-W and therefore, the 3D-P is faster than the 3D-W.

Based on its physical structure, the 3D-M can be categorized into horizontal 3D-M (3D-MH) and vertical 3D-M (3D-MV). In a 3D-MH, all address lines are horizontal. The memory cells form a plurality of horizontal memory levels which are vertically stacked above each other. A well-known 3D-MHis 3D-XPoint. In a 3D-MV, at least one set of address lines are vertical. The memory cells form a plurality of vertical memory strings which are placed side-by-side on/above the substrate. A well-known 3D-MVis 3D-NAND. In general, the 3D-MH(e.g. 3D-XPoint) is faster, while the 3D-MV(e.g. 3D-NAND) is denser.

FIG.5Adiscloses a preferred computing element110-icomprising at least a 3D-W array170. It comprises a substrate circuit0K formed on the substrate0. The ALC180is a portion of the substrate circuit0K. The 3D-W array170is a 3D-MHarray including two memory levels16A,16B, with a first memory level16A stacked above the substrate circuit0K and a second memory level16B stacked above the first memory level16A. The substrate circuit0K includes the peripheral circuits of the memory levels16A,16B. It comprises transistors0tand the associated interconnect0M. Each of the memory levels (e.g.16A,16B) comprises a plurality of first address lines (i.e. y-lines, e.g.2a,4a), a plurality of second address lines (i.e. x-lines, e.g.1a,3a) and a plurality of 3D-W cells (e.g.6aa). The first and second memory levels16A,168are coupled to the ALC180through contact vias1av,3av, respectively. The LUTs stored in all 3D-M arrays coupled to the ALC180are collectively referred to as the 3DM-LUT170. Coupling the 3DM-LUT170with the ALC180, the contact vias1av,3avare collectively referred to as IPS-connections160.

FIG.5Bdiscloses a preferred computing element110-icomprising at least a 3D-P array170. It has a structure similar to that ofFIG.5Aexcept for the memory cells. 3D-P has at least two types of memory cells: a high-resistance 3D-P cell5aa, and a low-resistance 3D-P cell5ac. The low-resistance 3D-P cell5accomprises a diode layer14, while the high-resistance 3D-P cell5aacomprises at least a high-resistance layer13. The diode layer14is similar to that in the 3D-W. The high-resistance layer13, on the other hand, could simply be a layer of insulating dielectric (e.g. silicon oxide, or silicon nitride). It is physically removed at the location of the low-resistance 3D-P cell5acduring manufacturing.

InFIGS.5C-5D, the preferred configurable processor100comprises a substrate circuit0K and a plurality of 3D-MVarrays170vertically stacked thereon. The substrate circuit0K is similar to those inFIG.5A. The 3D-MVarray170comprises a plurality of vertically stacked horizontal address lines15. The 3D-MVarray170also comprises a set of vertical address lines, which are perpendicular to the surface of the substrate0. The 3D-MVhas the largest storage density among semiconductor memories. For reason of simplicity, the ISP-connections (e.g. contact vias)160between the 3D-MVarrays170and the substrate circuit0K are not shown. They are similar to those in the 3D-MHarrays170ofFIG.5Aand well known to those skilled in the art.

The preferred 3D-MVarray170inFIG.5Cis based on transistors or transistor-like devices. It comprises a plurality of vertical memory strings16X,16Y placed side-by-side. Each memory string (e.g.16Y) comprises a plurality of vertically stacked memory cells (e.g.18ay-18hy). Each memory cell (e.g.18fy) comprises a vertical transistor, which includes a gate (acts as a horizontal address line)15, a storage layer17, and a vertical channel (acts as a vertical address line)19. The storage layer17could comprise oxide-nitride-oxide layers, oxide-poly silicon-oxide layers, or the like. This preferred 3D-MVarray170is a 3D-NAND and its manufacturing details are well known to those skilled in the art.

The preferred 3D-MVarray170inFIG.5Dis based on diodes or diode-like devices. In this preferred embodiment, the 3D-MVarray comprises a plurality of vertical memory strings16U-16W placed side-by-side. Each memory string (e.g.16U) comprises a plurality of vertically stacked memory cells (e.g.18au-18hu). The 3D-MVarray170comprises a plurality of horizontal address lines (e.g. word lines)15which are vertically stacked above each other. After etching through the horizontal address lines15to form a plurality of vertical memory wells11, the sidewalls of the memory wells11are covered with a programmable layer12. The memory wells11are then filled with a conductive materials to form vertical address lines (e.g. bit lines)19. The conductive materials could comprise metallic materials or doped semiconductor materials. The memory cells18au-18huare formed at the intersections of the word lines15and the bit line19. Similar to that inFIG.5A, the programmable layer12could be one-time-programmable (OTP, e.g. an antifuse layer) or multiple-time-programmable (MTP, e.g. an RRAM layer).

To minimize interference between memory cells, a diode or a diode-like device is preferably formed between the word line15and the bit line19. In a first preferred embodiment, the programmable layer12acts as a diode. In a second preferred embodiment, this diode is formed by depositing an extra diode layer on the sidewall of the memory well (not shown in this figure). In a third preferred embodiment, this diode is formed naturally between the word line15and the bit line19, i.e. to form a built-in junction (e.g. P-N junction, or Schottky junction). More details on the built-in diode are disclosed in U.S. patent application Ser. No. 16/137,512, filed on Sep. 20, 2018.

FIG.5Eis a perspective view of the preferred computing element110-i. The ALC180is formed on the substrate0. The 3DM-LUT170is vertically stacked above and at least partially covers the ALC180. The 3-D integration moves the 3DM-LUT170physically close to the ALC180. Because the contact vias1av,3avcoupling them are short (i.e. their length are on the order of microns) and numerous (thousands), the IPS-connections160have a much larger bandwidth than the conventional processor300. As the 2-D integration places the ALU380and the LUT370side-by-side on the substrate0, the interconnects coupling them are much longer (hundreds of ums in length) and fewer (hundreds at most).

FIGS.6A-6Bshow two types of the preferred 3D-M cell5ab. In the preferred embodiment ofFIG.6A, the 3D-M cell5abcomprises a variable resistor12and a diode (or a diode-like device)14. The variable resistor12is realized by the programmable layer ofFIG.5A. It can be varied during manufacturing or after manufacturing. The diode (or diode-like device)14is realized by the diode layer ofFIG.5A. It is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage.

In the preferred embodiment ofFIG.6B, the 3D-M cell5abcomprises a transistor or a transistor-like device16. The transistor or transistor-like device16is broadly interpreted as any three- (or, more-) terminal device whose resistance between the first and second terminals can be modulated by an electrical signal on a third terminal. In this preferred embodiment, the device16further comprises a floating gate18for storing electrical charge which represents the digital information stored in the 3D-M cell5ab. To those skilled in the art, the devices16can be organized into NOR-arrays or NAND-arrays. Depending on the direction of the current flow between the first and second terminals in the devices16, the 3D-M could be categorized into horizontal 3D-M (e.g. 3D-XPoint) and vertical 3D-M (e.g. 3D-NAND).

Referring now toFIGS.7A-7C, the substrate layout views of three preferred computing elements110-iare shown. In the embodiment ofFIG.7A, the ALC180is only coupled with a single 3D-M array170oand processes the 3DM-LUT data therefrom. The 3DM-LUT170is stored in the 3D-M array170o. The ALC180is covered by the 3D-M array170. The 3D-M array170ohas four peripheral circuits, including X-decoders15o,15o′ and Y-decoders17o,17o′. The ALC180is bound by these four peripheral circuits. As the 3D-M array is stacked above the substrate circuit0K and does not occupy any substrate area, its projection on the substrate0is shown by dotted lines in this and following figures.

In the embodiment ofFIG.7B, the ALC180is coupled with four 3D-M arrays170a-170dand processes the 3DM-LUT data therefrom. The 3DM-LUT170is stored in four 3D-M arrays170a-170d. Different fromFIG.7A, each 3D-M array (e.g.170a) has two peripheral circuits (e.g. X-decoder15aand Y-decoder17a). The ALC180is bound by eight peripheral circuits (including X-decoders15a-15dand Y-decoders17a-17d) and located below four 3D-M arrays170a-170d. Apparently, the ALC180ofFIG.7Bcould be four times as large as that ofFIG.7A.

In the embodiment ofFIG.7C, the ALC180is coupled with eight 3D-M arrays170a-170d,170w-170zand processes the 3DM-LUT data therefrom. The 3DM-LUT170is stored in eight 3D-M arrays170a-170d,170w-170z. These 3D-M arrays are divided into two sets: a first set150aincludes four 3D-M arrays170a-170d, and a second set150bincludes four 3D-M arrays170w-170z. Below the four 3D-M arrays170a-170dof the first set150a, a first component180aof the ALC180is formed. Similarly, below the four 3D-M array170w-170zof the second set150b, a second component180bof the ALC180is formed. In this embodiment, adjacent peripheral circuits (e.g. adjacent x-decoders15a,15c, or, adjacent y-decoders17a,17b) are separated by physical gaps G. These physical gaps allow the formation of the routing channel182,184,186, which provide coupling between different components180a,180b, or between different ALCs180a,180b. Apparently, the ALC180ofFIG.7Ccould be eight times as large as that ofFIG.7A.

Because the 3D-M array170is stacked above the ALC180, this type of vertical integration is referred to as 3-D integration. The 3-D integration has a profound effect on the computational density of the 3D-processor100. Because the 3D-M array170does not occupy any substrate area0, the footprint of the computing element110-iis roughly equal to that of the ALC180. This is much smaller than a conventional processor300, whose footprint is roughly equal to the sum of the footprints of the LUT370and the ALC380. By moving the LUT from aside to above, the computing element becomes smaller. The 3D-processor100would contain more computing elements110-1, become more computationally powerful and support massive parallelism. Preferably, a 3D-processor comprises at least one thousand computing elements, and in some cases, at least ten thousand computing elements. Although each individual 3D-M cell is slower than a 2D-M cell, this deficiency in speed can be offset by a significantly larger scale of parallelism. As a result, the 3D-processor becomes suitable for high-performance computation.

The 3-D integration also has a profound effect on the computational complexity. Because it supports the 3-D integration and has a much larger storage capacity than the conventional 2D-M, the 3D-M in the preferred 3D-processor100has a total LUT capacity of at least one gigabit, and in some cases, at least ten gigabits, which is large enough to support a larger LUT for each mathematical functions and a significantly larger scale of parallelism. For example, since the total 3DM-LUT capacity for a single 3D-processor die100could reach 100 Gb (for example, a 3D-XPoint die has a storage capacity of 128 Gb), a single 3D-processor die100could support as many as ten thousand built-in functions, which are orders of magnitude more than the conventional processor300.

Significantly more built-in functions shall flatten the prevailing framework of scientific computation (including the foundation, function and modeling layers). The hardware-implemented built-in functions, which were only available to the foundation layer, now become available to the function and modeling layers. Not only mathematical functions in the function layer can be directly realized by hardware (FIGS.8A-9B), but also mathematical models in the modeling layer can be directly described by hardware (FIGS.10A-10B). In the function layer, mathematical functions can be realized by a function-by-LUT method, i.e. the function values are calculated by reading the 3DM-LUT data plus polynomial interpolation. In the modeling layer, mathematical models can be described by a model-by-LUT method, i.e. the input-output characteristics of a system component are modeled by reading the 3DM-LUT data plus polynomial interpolation. Rapid and efficient computation would lead to a paradigm shift for scientific computation.

Referring now toFIGS.8A-8C, a first preferred computing element110-iimplementing a built-in function Y=f(X) is disclosed. It uses the function-by-LUT method.FIG.8Ais its circuit block diagram. The ALC180comprises a pre-processing circuit180R, a 3DM-LUT170P, and a post-processing circuit180T. The pre-processing circuit180R converts the input variable (X)150into an address (A) of the 3DM-LUT170P. After the data (D) at the address (A) is read out from the 3DM-LUT170P, the post-processing circuit180T converts it into the function value (Y)190. A residue (R) of the input variable (X) is fed into the post-processing circuit180T to improve the calculation precision.

FIG.8Bis its substrate-circuit layout view. The 3D-M storing the 3DM-LUT170P comprises at least a 3D-M array170p, as well as its X-decoder15pand Y-decoder17p. The 3D-M array170pcovers the pre-processing circuit180R and the post-processing circuit180T. Although a single 3D-M array170pis shown in this figure, the preferred embodiment could use multiple 3D-M arrays, as those shown inFIGS.7B-7C. Because the 3D-M array170pdoes not occupy any substrate area, the 3-D integration between the 3D-M array170pand the ALC180(including the pre-processing circuit180R and the post-processing circuit180T) leads to a smaller footprint for the computing element110-i.

FIG.8Cdiscloses the first preferred computing element110-iwhich realizes a single-precision built-in function Y=f(X). The input variable X150has 32 bits (x31. . . x0). The pre-processing circuit180R extracts the higher 16 bits (x31. . . x16) thereof and sends it as a 16-bit address A to the 3DM-LUT170P. The pre-processing circuit180R further extracts the lower 16 bits (x15. . . x0) and sends it as a 16-bit residue R to the post-processing circuit180T. The 3DM-LUT170P comprises two 3DM-LUTs170Q,170R. Both 3DM-LUTs170Q,170R have 2 Mb capacities (16-bit input and 32-bit output): the 3DM-LUT170Q stores the functional value D1=f(A), while the 3DM-LUT170R stores the first-order derivative value D2=f′(A). The post-processing circuit180T comprises a multiplier180M and an adder180A. The output value (Y)190has 32 bits and is calculated from polynomial interpolation. In this case, the polynomial interpolation is a first-order Taylor series: Y(X)=D1+D2*R==f(A)+f′(A)*R. To those skilled in the art, higher-order polynomial interpolation (e.g. higher-order Taylor series) can be used to improve the calculation precision.

When calculating a built-in function, combining the LUT with polynomial interpolation can achieve a high precision without using an excessively large LUT. For example, if only LUT (without any polynomial interpolation) is used to realize a single-precision function (32-bit input and 32-bit output), it would have a capacity of 232*32=128 Gb, which is impractical. By including polynomial interpolation, significantly smaller LUTs can be used. In the above embodiment, a single-precision function can be realized using a total of 4 Mb LUT (2 Mb for function values, and 2 Mb for first-derivative values) in conjunction with a first-order Taylor series calculation. This is significantly less than the LUT-only approach (4 Mb vs. 128 Gb).

Referring now toFIGS.9A-9B, a second preferred computing element110-iimplementing a composite function Y=exp[K*log(X)]=XKis disclosed. It uses the function-by-LUT method.FIG.9Ais its schematic circuit block diagram. The preferred computing element110-icomprises two 3DM-LUTs170S,170T and a multiplier180M. The 3DM-LUT170S stores the Log( ) values, while the 3DM-LUT170T stores the Exp( ) values. The input variable X is used as an address150for the 3DM-LUT170S. The output Log(X)160afrom the 3DM-LUT170S is multiplied by an exponent parameter K at the multiplier180M. The multiplication result K*Log(X) is used as an address160bfor the 3DM-LUT170T, whose output190is Y=XK.

FIG.9Bis its substrate-circuit layout view. The substrate circuit0K comprises the X-decoders15s,15tand the Y-decoders17s,17tfor the 3D-M arrays170s,170t, as well as a multiplier180M. Placed side-by-side, both 3D-M arrays170s,170tpartially cover the multiplier180M. Note that both embodiments inFIG.8CandFIG.9Acomprise two 3DM-LUTs. These 3DM-LUTs could be stored in a single 3D-M array170p(as inFIG.8B), in two 3D-M arrays170s,170tplaced side-by-side (as inFIG.9B), or in two vertically stacked 3D-M arrays (i.e. on different memory levels16A,16B, as inFIGS.5A-5C). Apparently, the 3DM-LUT can be stored in more 3D-M arrays.

Referring now toFIGS.10A-10B, a third preferred computing element110-ito simulate the amplifier circuit20ofFIG.2Ais disclosed. It uses the model-by-LUT method.FIG.10Ais its schematic circuit block diagram. The preferred computing element110-icomprises a 3DM-LUT170U, an adder180A and a multiplier180M. The 3DM-LUT170U stores the data associated with the behaviors (e.g. input-output characteristics) of the transistor24. By using the input voltage value (VIN) as an address150for the 3DM-LUT170U, the readout160of the 3DM-LUT170U is the drain-current value (ID). After the IDvalue is multiplied with the minus resistance value (−R) of the resistor22by the multiplier180M, the multiplication result (−R*ID) is added to the VDDvalue by the adder180A to generate the output voltage value (VOUT)190.

The 3DM-LUT170U stores different forms of mathematical models. In one case, the mathematical model data stored in the 3DM-LUT170U is raw measurement data, i.e. the measured input-output characteristics of the transistor24. One example is the measured drain current vs. the applied gate-source voltage (ID-VGS) characteristics. In another case, the mathematical model data stored in the 3DM-LUT170U is the smoothed measurement data. The raw measurement data could be smoothed using a purely mathematical method (e.g. a best-fit model). Or, this smoothing process can be aided by a physical transistor model (e.g. a BSIM4 V3.0 transistor model). In a third case, the mathematical data stored in the 3DM-LUT include not only the measured data, but also its derivative values. For example, the 3DM-LUT data include not only the drain-current values of the transistor24(e.g. the ID-VGScharacteristics), but also its transconductance values (e.g. the Gm-VGScharacteristics). With derivative values, polynomial interpolation can be used to improve the modeling precision using a reasonable-size 3DM-LUT, as in the case ofFIG.8C.

FIG.10Bis its substrate-circuit layout view. The substrate circuit0K comprises the X-decoder15uand the Y-decoder17ufor the 3D-M array170u, as well as the multiplier180M and the adder180A. The 3D-M array170ucovers the multiplier180M and the adder180A. Although a single 3D-M array170uis shown in this figure, the preferred embodiment could use multiple 3D-M arrays170u, as those shown inFIGS.7B-7C.

Model-by-LUT offers many advantages. By skipping two software-decomposition steps (from mathematical models to mathematical functions, and from mathematical functions to built-in functions), it saves substantial modeling time and energy. Model-by-LUT may need less LUT than function-by-LUT. Because a transistor model (e.g. BSIM4 V3.0) has hundreds of model parameters, calculating the intermediate functions of the transistor model requires extremely large LUTs. However, if we skip function-by-LUT (namely, skipping the transistor models and the associated intermediate functions), the transistor behaviors can be described using only three parameters (including the gate-source voltage VGS, the drain-source voltage VDS, and the body-source voltage VBS). Describing the mathematical models of the transistor24requires relatively small LUTs.

While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that many more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. For example, the processor could be a micro-controller, a controller, a central processing unit (CPU), a digital signal processor (DSP), a graphic processing unit (GPU), a network-security processor, an encryption/decryption processor, an encoding/decoding processor, a neural-network processor, or an artificial intelligence (AI) processor. These processors can be found in consumer electronic devices (e.g. personal computers, video game machines, smart phones) as well as engineering and scientific workstations and server machines. The invention, therefore, is not to be limited except in the spirit of the appended claims.