Methods and apparatus for translating write request messages in a computing system

Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request in a second protocol responsive to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the memory write request in the generated memory write request in the second protocol to produce a translated memory write request. The method may also include receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types. The predefined code in the received memory write request is then used to determine the type of memory write request (posted or non-posted).

FIELD OF ENDEAVOR

The present disclosure relates to methods and apparatus used to translate messages within a computing system and, more particularly for translating types of write message requests formatted according to one protocol to another protocol in order to transmit the write message requests.

BACKGROUND

In certain types of computing systems that include a central processing unit (CPU) and a host bridge or what is known as a “Northbridge,” such devices are connected by an interface using a particular protocol in order for the CPU and Northbridge to communicate. One such protocol known in the art is HyperTransport™, which provides a high speed, point-to-point link for interconnecting integrated circuits within a computing system. Typically, however, Northbridge circuits communicate with other devices in the system, such as input-output bridges (e.g., a “Southbridge”) according to different protocols, including PCI Express. Different protocols may use different packet formats and different commands in the packets. Accordingly, when a CPU is trying to communicate with a Southbridge via the Northbridge and the CPU communicates with the Northbridge via HyperTransport™ protocol and the Northbridge, in turn, communicates with the Southbridge via PCI Express protocol, not all message types or packet formats are easily passed through the Northbridge to communicate the commands in requests (e.g. packets) from the CPU to the South bridge.

Particularly, certain protocols, such as HyperTransport™, utilize two types of memory write commands in memory write requests. In the example of HyperTransport™, in particular, it is known to utilize both “posted” and “non-posted” memory write commands. Posted commands are simply sent from a CPU to a Southbridge via a Northbridge, for example, without the need for a return acknowledgment. On the other hand, non-posted commands require that the receiving device issue an acknowledgement that the memory write request with the non-posted command has been made. PCI Express, on the other hand, only utilizes the concept of the equivalent of posted memory write requests of HyperTransport™ protocol. This difference becomes particularly problematic with Southbridges incorporating an internal bridge to a low pin count (LPC) interface, which is an interface that may connect to devices having both slave and/or master interfaces and also converts to LPC protocols.

The LPC protocol, however, does not account for or allow memory write requests to be retried with the master interfaces. In particular, once a bus master is granted control of the LPC interface, it will not release the interface before a transaction or write request is successfully completed. When the Southbridge grants an external LPC interface master control of the interface, the Southbridge is unable to service transactions, namely memory write requests, from the CPU that are targeting a particular device connected to the LPC interface. Thus, when the LPC interface master is performing direct memory access reads from a main system memory, it is possible that the CPU may also be performing “posted” memory write requests to another device connected to the LPC interface. However, because the LPC interface master “owns” the LPC interface at the time, the posted memory write requests cannot be completed. This situation is further complicated in that known ordering rules for such interfaces prevent read response data from passing the posted memory write requests, which may result in deadlock of the Southbridge as well as the entire computing system.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

The present disclosure relates to methods and apparatus to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. An example of a disclosed method includes generating a memory write request using a second protocol responsive to a memory write request of a first protocol from the first processor, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the generated memory write request of the second protocol to produce a translated memory write request. The method may also include first receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types. The second protocol only recognizes the first memory write command type of the first protocol and does not recognize the memory write command types of the second memory request format.

Additionally, apparatus are disclosed for translating memory write requests transmitted from the first processor to a second processor in a computing system, which includes a bridge circuit having an interface configured to receive the memory write request from the first processor where the memory write requests are operable according to a first protocol having at least first and second memory write command types. The bridge circuit also includes logic operable to generate a write command request using a second protocol in response to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The logic is also operative to insert a predefined code into the write request in order to translate the request of the first protocol to a second write request of the second protocol where the second protocol only recognizes the first memory write command type of the first protocol and does not recognize the second memory write command type.

The disclosed methods and apparatus for translating memory write requests, (e.g. a HyperTransport™ packet with a write command therein indicating the packet is for a memory write operation) transmitted from a first processor to a second processor are useful to allow a first processor, such as a CPU, utilizing a packet protocol for sending multiple types of memory requests (e.g., posted and non-posted memory write requests in HyperTransport™ that are posted and non-posted memory write commands in the packets) to another processor in a computing system, such as a Southbridge, via a Northbridge circuit, which communicates to the Southbridge via a second protocol, such as PCI Express. Furthermore, in Southbridge circuits employing low pin count (LPC) interfaces, the addition of a predetermined code inserted into PCI Express formatted memory write requests from the Northbridge to the Southbridge allows the Southbridge to receive non-posted memory requests. In particular, the predefined code tells the Southbridge to send an acknowledgement that is translated by the Northbridge and sent to the CPU in order to ensure that the Southbridge and CPU are not causing the system to get stuck.

FIG. 1illustrates an example of a computer system100in which the presently-disclosed apparatus and methods may be utilized. As shown, the system100includes a processor102, which may be a central processing unit (CPU), multiple processors, or any other similar processing unit. The processor102is interfaced to a bridge circuit, such as a memory interface bridge, host bridge, or a Northbridge104via an interface106. In particular, for purposes of example, this interface106operates according to the HyperTransport™ protocol, but may be any other suitable interface in which write commands are of the posted and non-posted type. The system100also may include a system memory108connected directly to the processor102with an interface110, such as an interface operating according to PCI Express, PCI, AGP or any other suitable interface standard.

The Northbridge circuit104is also connected to a memory112, which may be a system memory and also may include graphics memory or simply the graphics memory utilized by a graphics processing unit116connected to the Northbridge104or graphics processing circuitry118internal to the Northbridge circuit104. The memory112is interfaced with the Northbridge104via an interface114, which may operate according to DDR1/DDR2 or any other suitable standard for interfacing with memory. Additionally, the graphics processing unit116is interfaced by an interface120with the Northbridge circuit104and also may operate according to any suitable standard, such as PCI, PCI Express or AGP or other suitable communication system that utilizes only posted memory write commands. The graphics processing unit116may drive a display media122, such as a monitor, printer, or any other suitable display device122via an analog bus124.

The Northbridge circuit104, as shown inFIG. 1also interfaces with a Southbridge circuit, which may be used to interface with any one of numerous types of devices, such as keyboards, mouse devices, hard drives, floppy drives, USB devices, ROMs and PCI bus cards. The Northbridge104and Southbridge126are interfaced with an interface128, which may operate according to any suitable standard. For purposes of the present disclosure, the interface128operates according to PCI Express or any other suitable equivalent interface protocol that, for example, utilizes only posted memory write commands.

The Southbridge circuit126also includes a low pin count (LPC) interface130, which is used to interface any number of output devices to the Southbridge circuit126. The LPC interface130operates according to the low pin count interface standard developed by Intel as defined in, for example, “Intel Low Pin Count (LPC) Interface Specification,” Revision 1.1., Document No. 251289-001, August 2003, which is incorporated herein by reference.

Particular to the presently disclosed methods and apparatus, the Northbridge circuit104includes translation logic132that is used to translate or correlate between requests and messages from the CPU102via interface106operating according to HyperTransport™ protocol and the interface128between the Northbridge104and Southbridge126operating according to PCI Express, for example. Furthermore, the Southbridge circuit126includes write interpretation logic134that is used, for example, to effect acknowledgement of memory write requests from the CPU, which have been translated by the translation logic132in the Northbridge circuit104.

It is also noted that the translation logic132and write interpretation logic134may be comprised of hardware, firmware or software. In the case of firmware or software, logic132may be executable instructions stored in a memory, such as memory108or memory112(or a memory within the Northbridge circuit104), or a combination of a number of different memories in computer system100such that when processed by the one or more processors (e.g., CPU102, Northbridge circuit104, Southbridge126or any combination of processing devices) will perform the translation.

Translation logic132may also be configured to translate memory write requests issued by the CPU102to the Southbridge circuit126. As discussed previously, under HyperTransport™ protocol, two types of memory requests may be issued according to the standard-posted and non-posted memory write commands. However, as discussed previously, PCI Express, according to the standard, only recognizes the equivalent of posted memory write requests.

As discussed previously, the LPC bus or interface130can have devices with both slave and/or master interfaces. However, the LPC protocol does not allow for retrying bus masters. Once a bus master has been granted the LPC bus, it will not release the bus before a transaction is successfully completed. Once the Southbridge circuit126grants an external LPC bus master control of the LPC bus, the Southbridge circuit126will not be able to service transactions from the CPU102that target an LPC device. When an LPC bus-master is performing direct memory access (DMA) reads from main memory (e.g., memory108), it is possible that the CPU102is also performing posted writes to another LPC device. Since the LPC bus-master “owns” the LPC bus, the posted writes cannot complete. Normal ordering rules prevent read-response data from passing posted write requests, which result in deadlock.

Thus, in the presently disclosed system all transactions targeting the LPC bus or interface130are placed into a non-posted request queue136, which is shown within the Northbridge circuit104. Consequently, DMA read responses can pass the non-posted memory write requests. In order to ensure correct operation, the concept of non-posted memory writes must also be extended across the PCI Express interface128from the Northbridge circuit104to the Southbridge circuit126. This is achieved by defining a specific transaction type or command type (e.g. changing content of a type field to indicate a non-posted memory write command) in the PCI Express packets with the translation logic132for non-posted memory writes (e.g., Type [4:0]=0—1110), while all other fields in PCI Express packets transmitted from the Northbridge circuit104to the Southbridge circuit126are defined the same as a posted memory write (e.g., 0—0000 as illustrated in Table 2-52-3 of the PCI Express specification). Hence, the PCT Express packet format is used to accommodate non-posted write commands. It is noted that in an example of translation of non-posted memory write requests according to the present disclosure, the HyperTransport requests (which are, at maximum, 64 bytes) may be split down to one PCI Express dword packet consisting of 4 bytes. Because the Southbridge circuit126must save the write request in holding registers in the event the LPC bus is busy, reducing the packet to one dword minimizes the amount of holding register storage required in the Southbridge circuit126.

In the Northbridge circuit104and the Southbridge circuit126, these specific memory write transactions are then configured to follow the same path as posted writes, and a completion acknowledgement is returned from the write interpretation logic134in the Southbridge circuit126to the Northbridge circuit104. The write interpretation logic134in the Southbridge circuit126will only send an acknowledgement once the LPC interface130write is completed. Otherwise, the Northbridge circuit104would attempt to send further non-posted writes to the LPC interface130. Any non-posted memory write request not targeting the LPC interface130is converted to a posted write and acknowledged by the Northbridge circuit104.

FIG. 2illustrates a flow diagram of the processes by which the translation logic132follows to convert non-posted memory write requests from the CPU102to the Southbridge126. As illustrated, the process200is initialized at block202. Flow then proceeds to block204where the logic132receives a memory write request from the CPU102. It is noted that the memory write request may be a request with either a posted write command or a non-posted write command therein. Flow then proceeds to decision block206where the logic132determines whether or not the message is a posted or non-posted type (contains a posted or non-posted write command). If the message is determined at block206to be a posted type, flow proceeds to block208where logic132simply transmits the message write request to the Southbridge circuit via PCI Express bus128.

Alternatively, at block206, if the logic132determines that the message is of a non-posted type, flow proceeds to block210where logic132generates a write command request in a second protocol responsive to the non-posted message type and inserts a predetermined code recognizable by PCI Express and that is also recognizable by write interpretation logic134in the Southbridge circuit126. Flow then proceeds to block608where the request is transmitted from the Northbridge104to the Southbridge126. The process then ends as shown at block612.

As discussed in the foregoing description, the disclosed methods and apparatus for translating memory write requests transmitted from a first processor to a second processor are useful to allow a first processor, such as a CPU, utilizing a protocol for sending multiple types of memory requests (e.g., posted and non-posted command write requests in HyperTransport™) to another processor in a computing system, such as a Southbridge, via a Northbridge circuit, which communicates to the Southbridge via a second protocol, such as PCI Express. Furthermore, in Southbridge circuits employing low pin count (LPC) interfaces, the addition of a predetermined code inserted into PCI Express formatted memory write requests from the Northbridge to the Southbridge allows the Southbridge to receive non-posted memory requests. The write interpretation logic134includes logic to interpret the predefined code. In particular, the predefined code may be data in a type field of the packet and tells the Southbridge to send an acknowledgement that is translated by the Northbridge and sent to the CPU in order to ensure that the Southbridge and CPU are not causing the system to get stuck.

The above detailed description of the examples described herein have been presented for the purposes of illustration and description only and not by limitation. It is therefore contemplated that the present application cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and the appended claims.