Processor interface controller for interfacing peripheral devices to a processor

A generic interface controller for a processor to peripheral device interface. This circuit eliminates marginal timing between a processor and a plurality of different peripheral devices while providing read and write operations within a minimum amount of cycle time. The processor interface controller generates read, write and acknowledge signals. This controller is particularly useful for ASIC applications where some of the peripheral devices such as memory, may be co-located on the ASIC circuit while other peripheral devices may be remotely located from the application Specific Integrated Circuit (ASIC) circuit.

BACKGROUND OF THE INVENTION 
The present invention relates to a processor's interface with peripheral 
devices and more particularly to circuitry for the elimination of marginal 
timing between a microprocessor and its associated peripheral devices. 
It is desirable for microprocessors to achieve a high data transfer rate 
between itself and its associated peripheral devices. This high data 
transfer rate provides the highest microprocessor throughput. High 
microprocessor throughput is desirable since this allows the 
microprocessor to perform more functions per unit of time. 
Peripheral devices may include memories, disk drives, tape drives, internal 
or external registers. These peripheral devices have markedly different 
access times for reading and writing under microprocessor control. 
Typically, a different peripheral device interface may be required for 
these different peripheral devices. Several different interface circuits 
is not economical. This would conserve considerable space and power. 
In addition, a processor is required to interface to a number of different 
peripheral devices. These peripheral devices have different data transfer 
rates and different timing. A solution to this problem is to design, 
simulate and test a unique interface circuit for each peripheral. This 
requires physical space for each of the circuits as well as being wasteful 
of components, power and design effort. 
Accordingly, it is an object of the present invention to provide a generic 
processor interface controller which eliminates marginal and different 
timings between a processor and a number of peripheral devices. 
SUMMARY OF THE INVENTION 
In accomplishing the object of the present invention, a novel processor 
interface controller is shown. 
A processor system includes a system clock. The processor system also 
includes a processor which is coupled to a number of peripheral devices 
via a processor interface controller. The processor provides a number of 
control signals such as a read request signal, a write request signal and 
a data strobe signal. 
The processor interface controller includes an enabling circuit which is 
connected to the processor. The enabling circuit operates in response to 
the data strobe signal to produce an enabling signal. A latching 
arrangement of the processor interface controller is connected to the 
system clock and to the enabling circuit. The latching arrangement 
operates in response to the system clock and to the enabling signal to 
produce an acknowledge signal at a predetermined time interval with 
respect to the enabling signal. 
A read generator is connected to the processor, to the latching arrangement 
and to the peripheral devices. The read generator operates in response to 
the read request signal of the processor to the latching arrangement and 
to the peripheral devices and operates to produce a read signal for use by 
the peripheral devices. The read signal is produced at a predetermined 
time interval with respect to the enabling signal. 
A write generator is connected to the processor, to the latching 
arrangement and to the peripheral devices. The write generator operates in 
response to the write request signal to produce a write signal at a 
predetermined time interval with respect to the enabling signal.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 1 is a block diagram of a microprocessor system. Microprocessor 10 is 
connected to processor interface controller 20 via address and data busses 
and a control bus including a number of control signals. Processor 
interface controller (PIC) 20 connects the address and data bus leads to 
each of the peripheral devices 1 through N. The address and data busses 
are passed through directly from the microprocessor to each of the 
peripheral devices 1 through N. Signals which indicate whether a 
peripheral device is to be read from or written to are transmitted from 
the microprocessor 10 to PIC 20. PIC 20 interprets the signals and 
provides the proper timing so that valid data is presented to 
microprocessor 10 by the particular peripheral device selected or vice 
versa. Specifically, individual read and write signals which are active 
low are required by a large majority of peripheral devices. In addition, 
the read and write signals have and extended (longer) pulse width which 
will meet the pulse width specifications of most of these peripheral 
devices. The RW signal from the microprocessor 10 is not active low for 
both read and write bus cycles and does not meet the pulse width 
requirement for most peripheral devices. 
Select signals (not shown) which indicate the particular peripheral device 
to be written or read are transmitted directly from microprocessor 10 to 
each of the peripheral devices. When the appropriate select signal is 
initiated, the particular peripheral device indicated by that select 
signal will respond to the RD and WR signals. 
Since different peripheral devices have different response and set up 
times, PIC 20 insures that the microprocessor will see valid data from any 
peripheral device which it selects and vice versa. Since the different 
peripheral devices have different setup and response times, stable data 
will be presented to the microprocessor or taken from the microprocessor 
at different times. The PIC 20 provides uniform timing between the 
microprocessor 10 and each of the peripheral devices 1 through N, while 
keeping the cycle time of the read or write operation to a minimum. 
Marginal timing is eliminated because the read pulse (RD) which is 
generated by the peripheral interface controller is of an extended length 
which allows the peripheral devices with slower response times to present 
valid data to the microprocessor within the required data setup time. 
During the write cycle, the peripheral interface controller generates a 
write pulse (WR) of an extended length to provide adequate data setup 
margins for the peripheral devices. Another feature is that the WR signal 
is clocked high on the rising edge of cycle S6 instead of going high 
during S7 as the UDS and LDS signals do. This provides additional data 
hold time for the peripheral devices because of inadequate data hold times 
provided by the microprocessor. 
The PIC 20 may be implemented within an integrated circuit. PIC 20 may be 
implemented on an ASIC (Application Specific Integrated Circuit) along 
with some of the internal peripheral devices and other circuitry. These 
internal peripheral devices may include memories. Different timing 
problems result from having peripheral devices located within the same 
ASIC circuit and from those peripheral devices located external to the 
ASIC circuit such as tape or disk drives. All data transfers between the 
microprocessor 10 and peripheral devices 1 through N are performed with 
the same bus timing. As a result, the amount of circuitry required is 
minimized. In addition, simulation of such ASIC circuitry is significantly 
facilitated. 
Referring to FIG. 2, a schematic diagram of PIC 20 of FIG. 1 is shown. The 
read/write signal RW connects microprocessor 10 to NAND GATE 30, NAND GATE 
41 and inverter 40. The upper data strobe (UDS) and the lower data strobe 
(LDS) connect microprocessor 10 through corresponding buffers to inputs of 
NAND GATE 30. The read/write signal and the upper data strobe and lower 
data strobe signals are a portion of the control bus which connects 
microprocessor 10 to PIC 20. The read/write signal, upper data strobe and 
lower data strobe signals are all active upon transition from the high 
logic level to the low logic level (i.e., from logic 1 to logic 0). 
The RESET signal is connected from the microprocessor 10 to an input of 
NAND GATE 32. The system clock signal SYSCLK is also connected from 
microprocessor 10 to the clear input of D-type flip-flops 35, 36, 37 and 
through inverter 39 to flip-flop 38. 
The output of NAND GATE 30 is connected to another input of NAND GATE 32. 
The output of NAND GATE 32 is connected to inverter 33. The output of 
inverter 33 is connected to the NMR inverting input of D-type flip-flops 
35 through 38. The D input of flip-flop 35 is connected to a voltage 
source of logic 1 (+V). The Q output (control signal) of flip-flop 35 is 
connected to an input of NAND GATE 41 to send the read signal to the 
peripheral devices, to the D input of flip-flop 37 and to the D input of 
flip-flop 38. The NQ (not Q) output of flip-flop 37 is connected to the D 
input of flip-flop 36. 
The Q output (control signal) of flip-flop 36 is connected to an input of 
NAND GATE 42 to send the write signal to the peripheral devices. The Q 
output of flip-flop 38 is the acknowledge signal ACK. The acknowledge 
signal ACK is transmitted back to the microprocessor in response to a read 
or write request. In the case of a read request, the acknowledge signal 
indicates that stable data has been presented by the peripheral device and 
it may be read by the microprocessor. In the case of a write request, the 
acknowledge signal indicates that stable data has been received by the 
particular peripheral device. The acknowledge signal is responsible for 
the longer (extended) pulse widths of the read (RD) and write (WD) signals 
because the processor signals LDS, UDS, and RW re held at their asserted 
(active low) levels until the acknowledge signal is recognized by the 
microprocessor. Since acknowledge signal is not generated until after the 
falling edge of cycle S4 (see FIG. 3), the processor extends (or waits) 
its bus cycles and therefore its bus signals UDS, LDS, and RD by the 
minimum number of wait states (W1 and W2) and therefore the peripheral 
interface controller generates longer (extended) read (RD) and write (WR) 
pulse widths. Latches 35-38 cause processor 10 to wait for the acknowledge 
signal the minimum number of wait states. 
The output of inverter 40 is connected to an input of NAND GATE 42. The 
output of NAND GATE 41 is connected to an input of NOR GATE 43. The 
address strobe signal is transmitted to the other input of NOR GATE 43. 
The address strobe signal AS indicates that the particular address on the 
address bus (not shown) is stable. The address strobe AS is generated by 
the microprocessor and is one of the control signals of the control bus. 
The output of NAND GATE 42 is the write signal. This signal is transmitted 
to each of the peripheral devices. One particular peripheral devices is 
selected. The selected peripheral device respond to this write signal by 
transferring data from the data bus (not shown) and writing it into the 
particular peripheral device. 
The output of NOR GATE 43 is the read signal RD. The read signal RD is 
transmitted to the peripheral devices 1-N and indicates that the selected 
peripheral device is to place its data on the data bus and this data is to 
be read into the microprocessor. As can be seen, a single circuit handles 
a number of peripheral devices, thereby achieving great economy. 
Referring now to FIGS. 2 and 3 taken in combination, the description of the 
processor interface controller is explained. The system clock signal 
SYSCLK is shown at the top of FIG. 3 waveform 100. The clock is shown 
passing through states S0 through S4, to wait states W1 and W2 and states 
S5 through S7. The system clock is generated by the clock circuit included 
in microprocessor 10 which is not shown. On the falling edge of state S2 
an address strobe signal AS, upper data strobe UDS and lower date strobe 
LDS are produced by transition from the logic 1 to logic 0 state as shown 
by waveform 101 of FIG. 3. The RW signal waveform 108, determines read 
signal RD and write signal WR. During state S4, either the read signal RD 
or the write signal WR is produced. These signals indicate read and write 
functions by microprocessor 10 respectively. The read function will be 
explained first. 
When the UDS and LDS signals (generated by the microprocessor) are at a 
logic 1, the flip-flops are disabled from accepting inputs from being 
clocked and therefore cannot change state. When the RESET signal makes a 
transition from logic 1 to logic 0, flip-flops through 35 through 38 are 
cleared and disabled. When the UDS and LDS signals are applied to NAND 
GATE 30 and the read/write signal from the microprocessor is applied to 
NAND GATE 30, a logic 1 is input to flip-flops 35 through 38 via the NMR 
input. This causes flip-flips 35 through 38 to become active in response 
to the system clock signal SYSCLK. Since the D input of flip-flop 35 is at 
logic 1, the Q output of flip-flop 35 outputs a logic 1. The output of 
flip-flop 35 and the read/write signal RW are combined by NAND GATE 41 and 
a logic 1 will be output from NAND GATE 41 to NOR GATE 43. The output of 
NOR GATE 43 is the read signal RD. The RD signal is shown as waveform 102 
of FIG. 3. This occurs on the rising edge of state S4. 
The Q output of flip-flop 35 is transmitted to the D input of flip-flop 38. 
Flip-flop 38 produces the acknowledge signal ACK. The acknowledge signal 
is generated after the failing edge of S4 and therefore the microprocessor 
extends its bus cycle by the minimum number of wait states W1 and W2. Only 
two wait states occur because the acknowledge signal is generated during 
the W1 wait state. Waveform 103 of FIG. 3 depicts this signal occurring 
during the wait state W1. From the time of W1 until the end of the cycle 
S7, the data on the data bus is stable and may be read by the 
microprocessor 10. This is depicted in waveform 104 of FIG. 3, which shows 
the data signals D0 through D15. At the end of the cycle, state S7, the 
processor then returns to state S0. 
The write cycle is shown by the waveforms 105-107 of FIG. 3. The operation 
of the address strobe signal AS, reset signal RESET, UDS and LDS, and 
system clock signal SYSCLK, are as described above for the read operation. 
The output of flip-flop 36 is obtained in response to the output of 
flip-flop 35, which is a result of flip-flop 37 The output of flip-flop 37 
is the input to flip-flop 36 and enables the output of flip-flop 36, which 
is transmitted to NAND GATE 42. With the read/write signal RW inverted by 
inverter 40, NAND GATE 42 produces a logic 0 on the WR lead as shown by 
waveform 106 of FIG. 3. This signal is transmitted to the particular 
peripheral device which is to be written to. The data bus D0 through D15 
is then stable for this writing process as shown by waveform 107 of FIG. 
3. 
FIG. 4 is a block diagram depicting application specific integrated circuit 
(ASIC) 21 which includes a processor interface controller 20 and internal 
peripheral devices 22-23. These internal peripheral devices may be 
memories, for example. 
It can be seen that a novel processor interface controller is shown which 
introduces a minimum number of wait states to achieve data transfer 
between a microprocessor and a number of peripherals. 
Although the preferred embodiment of the invention has been illustrated, 
and that form described in detail, it will be readily apparent to those 
skilled in the art that various modifications may be made therein without 
departing from the spirit of the invention or from the scope of the 
appended claims.