Backside contact structures with stacked metal silicide layers for source/drain region of fin field transistors

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

BACKGROUND

With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs, To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). Such scaling down has increased the complexity of semiconductor manufacturing processes.

DETAILED DESCRIPTION

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled m relevant art(s) in light of the teachings herein.

With increasing demand for lower power consumption, higher performance, and smaller area (collectively referred to as “PPA”) of semiconductor devices, backside power rails (BPR) can be implemented in semiconductor devices to reduce the device area and the metal interconnect length, thus reducing parasitic capacitances and parasitic resistances and improving device performance. For example, backside power rails can improve performance of power delivery network (PDN) for advanced technology nodes. To implement backside power rails, reducing contact resistances is an Objective of the process development. With the continuous scaling down of the dimensions, reducing contact resistance of the semiconductor devices can be challenging.

Contact resistance of a field effect transistor (FET) can depend on a Schottky barrier height (SBH) between metal silicide layers of source/drain (S/D) contact structures and S/D regions of the FET. SBH is a potential energy barrier for electrons formed at a metal-semiconductor junction. High SBH can result in high contact resistance. SBH can depend on the metal used to form the metal silicide layers. Different metal silicide layers on the same S/D regions of the FET can have different SBHs. For metal silicide layers formed with the same metal, n-type FET (NFET) and p-type FET (PFET) can have different SBHs due to different dopings of the S/D regions of the NFET and PEET. The term “p-type” can be associated with a structure, layer, and/or region doped with p-type dopants, such as boron. The term “n-type” can be associated with a structure, layer, and/or region doped with n-type dopants, such as phosphorus. A single metal silicide layer may not provide low contact resistances for both NFETs and PFETs in the semiconductor device.

In addition, the contact resistance of the FETs in the semiconductor device can depend on the contact areas between the metal suicide layers and the S/D regions of the FETs. Furthermore, the processing temperatures of backside processes may be limited, as the metals at the front side of the semiconductor devices may diffuse at higher temperatures (e.g., above about 450° C.) and degrade device performance.

Various embodiments in the present disclosure provide methods for forming a semiconductor device with backside contact structures. According to some embodiments, the backside contact structures can include an epitaxial contact structure. The epitaxial contact structure can have a first portion in contact with a source/drain (S/D) region of the semiconductor device and a second portion on the first portion. A width of the second portion can be larger than a width of the first portion. The contact area between the epitaxial contact structure and the metal contacts can be increased and the contact resistance of the backside contact structures can be reduced by about 30% to about 70%. In some embodiments, the epitaxial contact structure can include an active dopant higher than about 1×1021cm−3to further reduce the contact resistance of the backside contact structures.

In some embodiments, the backside contact structures can include different metal silicide layers in contact with the S/D regions of different types of FETs in the semiconductor device. For example, the backside contact structures of one type of FET (e.g., PITT) can have a first metal silicide layer on the S/D regions and a second metal silicide layer on the first metal silicide layer. The backside contact structures of an opposite type of FET (e.g., NFET) can include the second metal silicide layer on the S/D regions. The first metal silicide layer can include a metal different from the second metal silicide layer, which can reduce the SBH between the first metal silicide layer and the S/D region of the semiconductor device and thus reduce the contact resistance of the backside contact structures by about 30% to about 70%. With the first metal suicide layer in one type of FET (e.g., PFET) and the second metal silicide layer in an opposite type of FET (e.g., NFET), the contact resistance of the one type of ITT in the semiconductor device can be reduced without increasing the contact resistance of the opposite type of FET.

FIG.1Aillustrates an isometric view of a semiconductor device100with backside contact structures having an epitaxial contact structure, in accordance with some embodiments. Semiconductor device100can include a FET102A connected to a FET102B at an S/D region. S/D contact structure104A of FET102A and S/D contact structure104B of FET102B can connect to backside power rails103(also referred to as “backside contact structures104A and104B”).FIG.1Billustrates a cross-sectional view of semiconductor device100along line B-B inFIG.1A, in accordance with some embodiments.FIG.1Cillustrates region CFIG.1B, according to some embodiments.FIG.1Dillustrate region D inFIG.1C, according to another embodiment,FIG.1Eillustrate partial cross-sectional views of semiconductor device100along line E-E for FET102A and line E′-E′ for102B inFIG.1A, according to some embodiments. In some embodiments,FIGS.1A-1Eshow a portion of an IC layout where the dimensions of the fin structures and the dimensions of the gate structures can be similar or different from the ones shown inFIGS.1A-1E.

Referring toFIGS.1A-1E, semiconductor device100can include FETs102A and102B, S/D contact structures104A and104B connected to backside power rails103, and gate structures112A and112B (collectively referred to as “gate structures112”) connected to respective gate contact structures114A and114B (collectively referred to as “gate contact structures114”), which are further connected to front-side power rails105. FETs102A and102B can further include stacked fin structures108A and108B, S/D regions110A and110B, gate spacers116, and inner spacer structures118.

In some embodiments, FETs102A and102B can be both p-type finFETs (PFETs), both n-type finFETs (NFETs), or one of each conductivity type of finFET. In some embodiments, FET102A can be n-type (also referred to as “NFET102A”), FET102B can be p-type (also referred to as “PFET102B”) and semiconductor device100can be an inverter logic device. ThoughFIGS.1A and1Bshow two finFETs, semiconductor device100can have any number of finFETs. In addition, semiconductor device100can be incorporated into an integrated circuit through the use of other structural components, such as conductive vias, conductive lines, dielectric layers, and passivation layers, that are not shown for simplicity. The discussion of elements of FETs102A and102B with the same annotations applies to each other, unless mentioned otherwise.

As shown inFIG.1B, semiconductor device100can include stacked fin structures108A and108B extending along an X-axis and through FET102A and FET102B, respectively. Each of stacked fin structures108A and108B can include a stack of semiconductor layers122, Which can be nanosheets or nanowires. Each of semiconductor layers122can form a channel region underlying gate structures112A and112B of FETs102A and102B, respectively. Embodiments of the fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes can combine photolithography and self-aligned processes, forming patterns that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures.

In some embodiments, semiconductor layers122can include semiconductor materials similar to or different from substrate406. In some embodiments, each of semiconductor layers122can include silicon germanium (SiGe) with Ge in a range from about 5 atomic percent to about 50 atomic percent with any remaining atomic percent being Si or can include Si without any substantial amount of Ge. The semiconductor materials of semiconductor layers122can be undoped or can be in-situ doped during its epitaxial growth process using: (i) p-type dopants, such as boron, indium, and gallium; and/or (ii) n-type dopants, such as phosphorus and arsenic. Though three layers of semiconductor layers122for each of FET102A and FET102B are shown inFIG.1B, FET102A and FET102B can each have any number of semiconductor layers122.

Referring toFIGS.1A and1B, S/D regions110A and110B can be disposed adjacent to stacked fin structures108A and108B, respectively. In some embodiments, S/D regions110A and110B can have any geometric shape, such as a polygon, an ellipsis, and a circle. S/D regions110A and110B can include an epitaxially-grown semiconductor material. In some embodiments, the epitaxially-grown semiconductor material is the same material as substrate406. In some embodiments, the epitaxially-grown semiconductor material includes a different material from substrate406. In some embodiments, the epitaxially-grown semiconductor material for S/D regions110A and110B can be the same as or different from each other. The epitaxially-grown semiconductor material can include: (i) a semiconductor material, such as germanium and silicon; (ii) a compound semiconductor material, such as gallium arsenide and aluminum gallium arsenide; or (iii) a semiconductor alloy, such as silicon germanium and gallium arsenide phosphide. In some embodiments, S/D regions110A and110B can have a first width110w1along an X-axis adjacent to gate spacers116and a second width110w2along an X-axis adjacent to backside contact structures104A and104B. In some embodiments, first width110w1can be larger than second width110w2and a ratio of first width110w1to second width110w2can range from about 1.1 to about 5.

In some embodiments, S/D region110A can be n-type for FET102A (also referred to as “n-type S/D region110A”) and S/D region110B can be p-type for FET102B (also referred to as “p-type S/D region110B”). In some embodiments, n-type S/D region110A can include Si and can be in-situ doped during an epitaxial growth process using n-type dopants, such as phosphorus and arsenic. In some embodiments, n-type S/D region110A can have multiple n-type epitaxial fin sub-regions that can differ from each other based on, for example, doping concentration and/or epitaxial growth process conditions. In some embodiments, p-type S/D region110B can include SiGe and can be in-situ doped during an epitaxial growth process using p-type dopants, such as boron, indium, and gallium. In some embodiments, p-type S/D region110B can have multiple sub-regions that can include SiGe and can differ from each other based on, for example, doping concentration, epitaxial growth process conditions, and/or relative concentration of Ge with respect to Si.

Referring toFIGS.1A and1B, stacked fin structures108A and108B can be current-carrying structures for respective FET102A and FET102B. Channel regions of FET102A and FET102B can be formed in portions of their respective stacked fin structures108A and108B underlying gate structures and112B. S/D regions110A and110B can function as source/drain regions of respective FET102A and FET102B.

Referring toFIGS.1A-1E, gate structures112A and112B can be multi-layered structures and can be wrapped around semiconductor layers122of stacked fin structures108A and108B. In some embodiments, each of semiconductor layers122of stacked fin structures108A and108B can be wrapped around by one of gate structures112A and112B, respectively, and gate structures112A and112B can be referred to as “gate-all-around (GAA) structures” and FETs102A and102B can be referred to as “GAA FETs” or “GAA finFETs.”

In some embodiments, gate structures112A and1121can include gate dielectric layers113and gate electrodes111wrapping around semiconductor layers122. In some embodiments, gate dielectric layers113can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (HfO2), (iii) a negative capacitance (NC) dielectric material doped with aluminum (Al), gadolinium (Gd), silicon (Si), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), lanthanum (La), or (iv) a combination thereof. The term “high-k” can refer to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k can refer to a dielectric constant that is greater than the dielectric constant of SiO2 (e.g., greater than about 3.9). In some embodiments, gate dielectric layers113can include a single layer or a stack of insulating material layers. In some embodiments, gate electrodes111can include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), metal alloys, or combinations thereof.

Referring toFIG.1B, gate spacers116can be disposed along sidewalk of gate structures112A and112B, and inner spacer structures118can be disposed between S/D regions110A and110B and portions of gate structures112A and112B. Each of gate spacers116and inner spacer structures118can include a dielectric material, such as silicon oxide (SiOx), silicon oxynitride (SiOyN), silicon nitride (SiNx), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitricarbide (SiOCN), and a combination thereof. In some embodiments, each of gate spacers116and inner spacer structures118can include a single layer or multiple layers of insulating materials. In some embodiments, gate spacers116and inner spacer structures118can isolate gate structures112A and112E and S/D regions110A and110B.

Referring toFIGS.1A-1E, gate contact structures114A and1149can connect gate structures112A and112B respectively to front-side power rails105, and S/D contact structures104A and104B can connect S/D regions110A and110B respectively to backside power rails103. In some embodiments, gate contact structures114A and114B can connect to gate power supply lines in front-side power rails105. In some embodiments, both FET102A and FET102B can be connected to backside power rails103, as shown inFIG.1A-1E. S/D contact structures104A and104B of FETs102A and102B can connect to S/D power supply lines and ground lines in backside power rails103(also referred to as “backside contact structures104A and104B”), In some embodiments, one of FETs102A and102B can be connected to backside power rails103(not shown). In some embodiments, backside power rails103can have a thickness103tranging from about 10 to about 60 nm.

As shown inFIGS.1A-1E, backside contact structure104A can include a metal silicide layer148and a metal contact150, and backside contact structure104B can include an epitaxial contact structure146, metal silicide layer148, and metal contact150. Metal silicide layers148can include metal silicides and can reduce the contact resistance between respective metal contacts150and corresponding S/D regions of FETs102A and102B. Examples of metals used for forming the metal silicide can include cobalt (Co), titanium (Ti), nickel (Ni), ruthenium (Ru), tungsten (W), Bismuth (Bi), or germanium-tin (GeSn). In some embodiments, metal silicide layers148can have a thickness148tranging from about 3 nm to about 5 nm. If thickness148tis less than about 3 nm, the contact resistance between S/D regions110A and110B and metal contacts150may not be reduced. If thickness148tis greater than about 5 nm, the dimensions of metal contacts150can be reduced and the resistance of backside contact structures104A and104B may be increased due to higher resistivity of metal silicides than metals. Metal contacts150can include metals, for example, tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), ruthenium. (Ru), rhodium (Rh), iridium (Ir), titanium (Ti), tantalum (Ta), silver (Ag), metal alloys, or other suitable metals. In some embodiments, metal contacts150can have a vertical dimension150h(e.g., height) along a Z-axis ranging from about 10 nm to about 60 nm. In some embodiments, metal contacts150can have a horizontal dimension150w(e.g., width) along an X-axis ranging from about 20 nm to about 40 nm. In some embodiments, as shown inFIG.1C, an angle150jbetween sidewalk and a bottom surface of metal contacts150can range from about 80 degrees to about 89 degrees.

In some embodiments, epitaxial contact structure146can include a first portion146-1in contact with S/D region110B of FET102B and a second portion146-2capping over first portion146-1. Epitaxial contact structure146can include semiconductor materials similar to S/D region110B epitaxially grown at a temperature ranging from about 350° C. to about 450° C. If the temperature is lower than about 350° C., the growth rate of the semiconductor materials may not be high enough for manufacturing processes. If the temperature is higher than about 450° C., the metals in front-side power rails105may diffuse and decrease device performance. In some embodiments, the semiconductor materials can be in-situ doped during its epitaxial growth process using: (i) p-type dopants, such as boron, indium, and gallium; and/or (ii) n-type dopants, such as phosphorus, arsenic, and antimony. In some embodiments, epitaxial contact structure146can include an active dopant at a concentration higher than about 1×1021cm−3to reduce the resistance of epitaxial contact structure146.

In some embodiments, first portion146-1of epitaxial contact structure146can have a horizontal dimension146w1(e.g., width) along an X-axis ranging from about 8 nm to about 20 nm, Second portion146-2of epitaxial contact structure146can have a horizontal dimension146w2(e.g., width) along an X-axis ranging from about 8 nm to about 30 nm. In some embodiments, a ratio of horizontal dimension146w2to horizontal dimension146w1can range from about 1.1 to about 3. If the ratio is less than about 1.1, the contact resistance between S/D region110B and metal contact150may not be reduced. If the ratio is greater than about 3, the dimensions of metal contact150can be reduced and the resistance of backside contact structure104B may increase. In some embodiments, S/D region110B can have a recess110rat the interface between epitaxial contact structure146and S/D region110B ranging from about 0 nm to about 10 nm. In some embodiments, S/D region110B can have no recess.

Second portion146-2of epitaxial contact structure146can have any geometric shape. In some embodiments, second portion146-2of epitaxial contact structure146can have a rounded top surface and horizontal dimension146w2can be a diameter of second portion146-2, as shown inFIG.1C, In some embodiments, second portion146-2of epitaxial contact structure146can have one or more sloped facets and horizontal dimension146w2can be a width of second portion146-2over first portion146-1, as shown inFIG.1D. In some embodiments, epitaxial contact structure146with one or more sloped facets can have horizontal dimension146w2(e.g., width) ranging from about 8 nm to about 30 nm. In some embodiments, epitaxial contact structure146with one or more sloped facets can have a vertical dimension146h2(e.g., height) along a Y-axis ranging from about 2.5 nm to about 25 nm. An angle146jbetween the one or more facets and first portion146-1can range from about 30 degrees to about 70 degrees, as shown inFIG.1D.

In some embodiments, metal silicide layers148can include a metal silicide (e.g., titanium silicide) that has a low SBH (e.g., about 0.1 eV) and contact resistance on n-type S/D region110A. Compared with FET's without epitaxial contact structures, semiconductor device100with epitaxial contact structure146on p-type S/D region110B can reduce contact resistances of backside contact structure104B by about 30% to about 70% without increasing contact resistances of backside contact structure104A.

Referring toFIGS.1A-1E, semiconductor device100can further include a barrier layer115, a first interlayer dielectric (ILD) layer120, a second ILD layer124, a third ILD layer128, an etch stop layer (ESL)126, a capping layer130, a bonding layer132, a carrier substrate134, a backside ILD layer136, a backside ESL138, a backside barrier layer140, and backside dielectric structure144.

Barrier layer115and backside barrier layer140can include a dielectric material to isolate gate structures112and backside contact structures104A and104B from surrounding structures. In some embodiments, barrier layer115and backside barrier layer140can include silicon nitride. In some embodiments, backside barrier layer140can have a thickness140tranging from about 1 nm to about 3 nm. Each of first ILD layer120, second ILD layer124, third ILD layer128, and backside ILD layer136can include a dielectric material deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, flowable silicon oxycarbide, or flowable silicon oxynitricarbide). In some embodiments, the dielectric material can be silicon oxide. In some embodiments, backside ILD layer136can have a thickness136tranging from about 0 nm to about 40 nm. In some embodiments, semiconductor device100may not include backside ILD layer136.

ESL126and backside ESL138can protect underlying structures from etching during the formation of contact structures. In some embodiments, ESL126and backside ESL138can include, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or a combination thereof. In some embodiments, the dielectric material can be silicon oxide. In some embodiments, backside ESL138can have a thickness138tranging from about 10 nm to about 30 nm.

Backside dielectric structure144can isolate backside contact structures104A,104B, and other adjacent contact structures. In some embodiments, backside dielectric structure144can include a dielectric material deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide).

Capping layer130can protect front-side power rails105and include a dielectric material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and a combination thereof. Bonding layer132can include silicon oxide or other suitable materials to bond carrier substrate134to substrate406, Carrier substrate134can include semiconductor materials similar to or different from substrate406. In some embodiments, carrier substrate134can include silicon.

FIG.2Aillustrates an isometric view of a semiconductor device200with backside contact structures having dual metal silicide layers, in accordance with some embodiments.FIG.2Billustrates a cross-sectional view of semiconductor device200along line B-B inFIG.2A, in accordance with some embodiments.FIG.2Cillustrates region C inFIG.29, according to some embodiments.FIG.2Dillustrate partial cross-sectional views of semiconductor device200along line D-D or FET102A and D′-D′ for FET102B inFIG.2A, according to some embodiments. Elements inFIGS.2A-2Dwith the same annotations as elements inFIGS.1A-1Eare described above.

As shown inFIGS.2A-2D, backside contact structure104B can include a first metal silicide layer148B-1, a second metal silicide layer148B-2, and metal contact150. Backside contact structure104B can include second metal silicide layer148B-2and metal contact150. In some embodiments, first and second metal silicide layers148B-1and148B-2can include a different metal silicide. In some embodiments, second metal silicide layer148B-2can include a metal silicide (e.g., titanium silicide) that has a low (e.g., about 0.1 eV) and contact resistance on n-type S/D region110A. First metal silicide layer148B-1can include a metal silicide (e.g., nickel silicide) that has a low SBH (e.g., about 0.1 eV) and contact resistance on p-type S/D region110B. As a result, semiconductor device200can have low contact resistances for both NFETs and PFETs. Compared with a same metal silicide on both NFETs and PFETs, semiconductor device200with different metal silicide on different type of FETs can reduce contact resistances of backside contact structure104B by about 30% to about 70% without increasing contact resistances of backside contact structure104A.

In some embodiments, first metal silicide layer148B-1can have a thickness148t-1ranging from about 0.1 nm to about 3 nm. In some embodiments, second metal silicide layer148B-2can have a thickness148t-2ranging from about 3 nm to about 5 nm. A ratio of thickness148t-1to148t-2can range from about 0.02 to about 1. If thickness148t-1is less than about 0.1 nm, or the ratio is less than about 0.02, first metal silicide layer148B-1may not reduce contact resistance between backside contact structure104B and S/D region110B. If thickness148t-1is greater than about 3 nm, or the ratio is greater than about 1, resistances of first metal silicide layers148B-1may increase and the resistance of backside contact structure104B may increase.

FIG.3is a flow diagram of a method300for fabricating semiconductor device100with backside contact structures having an epitaxial contact structure, in accordance with some embodiments. Method300may not be limited to GAA FETs and can be applicable to devices that would benefit from backside contact structures with reduced contact resistance, such as planar FETs, fin FETs, etc, Additional fabrication operations may be performed between various operations of method300and may be omitted merely for clarity and ease of description. Additional processes can be provided before, during, and/or after method300; one or more of these additional processes are briefly described herein. Moreover, not all operations may be needed to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously or in a different order than shown inFIG.3. In some embodiments, one or more other operations may be performed in addition to or in place of the presently described operations. For example purposes, the operations illustrated inFIG.3will be described with reference to the example fabrication process for fabricating semiconductor device100as illustrated inFIGS.4-12,FIGS.4-12are cross-sectional views of semiconductor device100. AlthoughFIGS.4-12illustrate fabrication processes of semiconductor device100with epitaxial contact structure146in FET102B, method300can be applied to semiconductor device100with epitaxial contact structures in ITT102A and other semiconductor devices. Elements inFIGS.4-12with the same annotations as elements inFIGS.1A-1Eare described above.

In referring toFIG.3, method300begins with operation310of forming a semiconductor device on a first side of a substrate, where the semiconductor device includes a source/drain (S/D) region. For example, as shown inFIGS.4-6, semiconductor device100includes FETs102A and102B that can be formed on a first side406S1of substrate406. The formation of semiconductor device100can include formation of stacked fin structures108* and formation of FETs102A and102B. Stacked fin structure108* can be formed on first side406S1of substrate406. In some embodiments, substrate406can be an SOI wafer and can include a bulk layer452, an insulating layer454, and a device layer456. In some embodiments, bulk layer452can include silicon. In some embodiments, device layer456can include silicon and have a thickness456tranging from about 40 nm to about 200 nm. Thickness456tcan depend on requirements of devices fabricated on device layer456. In some embodiments, insulating layer454can include silicon oxide and have a thickness454tranging from about 20 nm to about 100 mm.

The formation of stacked fin structure108* can include epitaxially growing semiconductor layers458,460,462, and122* on substrate406followed by a vertical etch to form openings555, as shown inFIGS.4and5. In some embodiments, semiconductor layers458,460,462, and122* can include semiconductor materials with oxidation rates and/or etch selectivity different from each other. The term “etch selectivity” can refer to the ratio of the etch rates of two different materials under the same etching conditions. In some embodiments, semiconductor layer458can include silicon germanium (SiGe) with Ge in a range from about 30 atomic percent to about 40 atomic percent with any remaining atomic percent being Si. In some embodiments, semiconductor layer460can include Si and can be in-situ doped during its epitaxial growth process. In some embodiments, semiconductor layers462can include silicon germanium (SiGe) with Ge in a range from about 10 atomic percent to about 20 atomic percent with any remaining atomic percent being Si. In some embodiments, semiconductor layers122can include Si without any substantial amount of Ge. A hard mask layer can be deposited on semiconductor layers458,460,462, and122* and patterned to form openings555and stacked fin structures108* as shown inFIG.5by the vertical etch. In some embodiments, S/D regions can be formed in openings555in subsequent processes. In some embodiments, the vertical etch of semiconductor layers458,460,462, and122* can include a biased directional etching process. In some embodiments, device layer456can be partially etched or fully removed by the vertical etch.

The formation of semiconductor device100with FETs102A and102B can include formation of S/D regions110A and110B, formation of inner spacer structures118and gate spacers116, formation of gate structures112, formation of backside ESL138and backside ILD layer136, formation of first, second, and third ILD layers120,124, and128, formation of gate contact structures114, formation of front-side power rails105, and formation of capping layer130. The details for the formation of semiconductor device100on first side40651is omitted merely for clarity and ease of description.

In operation320ofFIG.3, a portion of the S/D region on a second side of the substrate is etched to form an opening. The second side is opposite to the first side. For example, as shown inFIGS.7-10, a portion of S/D regions110A and110B on a second side406S2of substrate406can be etched to form openings1064A and1064B. Second side406S2can be a back side of substrate406opposite to first side40651having semiconductor device100and front-side power rails105. Prior to etching a portion of S/D regions110A and110B on second side406S2, semiconductor device100can be bonded to a carrier substrate134and backside dielectric structure144can be formed on second side406S2of substrate406, As shown inFIG.7, a bonding layer132can be formed on capping layer130, and carrier substrate134can be bonded to bonding layer132. In some embodiments, bonding layer132can include a dielectric material of silicon oxide deposited by a high-density plasma (HDP) deposition process. In some embodiments, bonding layer132can include other suitable materials to bond carrier substrate134to capping layer130. In some embodiments, carrier substrate134and bonding layer132can be bonded together by a pressure bonding process.

The bonding of carrier substrate134to bonding layer132can be followed by flipping substrate406above carrier substrate134and a substrate polishing process on second side406S2of substrate406, as shown inFIGS.8A and8B.FIG.8Bis an enlarged cross-sectional view of region B shown inFIG.8A. In some embodiments, the substrate polishing process can include a grinding process, a trimming process, a thinning process, and a chemical mechanical polishing (CMP) process. After the substrate polishing process, substrate406can have a thickness ranging from about 100 nm to about 1 μm. A patterning process can be performed on second side406S2to form backside contact structures.

The bonding of semiconductor device100to carrier substrate134can be followed by the formation of backside dielectric structure144, as shown inFIG.9. A mask layer can be deposited on second side406S2of substrate406and the mask layer can be patterned to mask substrate406above S/D regions110A and110B. Substrate406can be removed from connected S/D regions of FETs102A and102B to form an opening. Backside barrier layer140can be formed on sidewalk of the opening and backside dielectric structure144can fill the opening. In some embodiments, backside barrier layer140can be conformally deposited in the opening and a portion of backside barrier layer140can be selectively etched on the connected S/D regions of FETs102A and102B by a directional etching process. In some embodiments, backside dielectric structure144can be deposited using a deposition method suitable for flowable dielectric materials. In some embodiments, backside dielectric structure144can include flowable oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide. In some embodiments, backside dielectric structure144can isolate FETs102A and102B, and other adjacent devices and structures.

The formation of backside dielectric structure144can be followed by etching a portion of S/D regions110A and110B, as shown inFIG.10, Substrate406above S/D regions110A and110B can be etched and a portion of S/D regions110A and110B can be etched to form openings1064A and1064B, In some embodiments, the etching process can include a directional etching process, such as a reactive ion etching (RIE) process. In some embodiments, each of S/D regions110A and110E can be etched with a depth110dranging from about 10 nm to about 80 nm. In some embodiments, a top surface of S/D regions110A and110B after the etching process can have a rounded surface due to process variations, Recess110rat the top surface can range from about 0 nm to about 10 nm.

In operation330ofFIG.3, an epitaxial contact structure can be formed on the S/D region. The epitaxial contact structure can include a first portion and a second portion and the width of the second portion is larger than the first portion. For example, as shown inFIGS.11and12, epitaxial contact structure146can be formed on S/D region110B. Epitaxial contact structure146can include first portion146-1and second portion146-2. First portion146-1can have a width smaller than the width of second portion146-2. Prior to the formation of epitaxial contact structure146, a hard mask layer1166can be deposited and patterned to cover the top surface of S/D region110A and exposed surfaces of FET102A. In some embodiments, hard mask layer1166can block S/D region110A while forming epitaxial contact structure146on S/D region110B. In some embodiments, hard mask layer1166can include aluminum oxide, silicon nitride, or other suitable dielectric materials and have a thickness ranging from about 3 nm to about 5 nm. Epitaxial contact structure146can be epitaxially grown on S/D region110B in opening1064B.

In some embodiments, epitaxial contact structure146can be deposited on S/D region110E at a temperature ranging from about 350° C., to about 450° C. under a pressure ranging from about 5 Torr to about 300 Torr. In some embodiments, epitaxial contact structure146can be deposited at a deposition rate ranging from about 0.1 nm/min to about 5 nm/min. If the temperature is lower than about 350° C., or the pressure is lower than about 5 Torr, or the deposition rate is less than about 0.1 nm/min, the growth rate of epitaxial contact structure146may be lower than the requirement of semiconductor manufacturing processes. If the temperature is higher than about 450° C., metals in front-side interconnects and power rails may diffuse and device performance may be degraded. If the pressure is higher than about 300 Torr, or the deposition rate is higher than about 5 nm/min, epitaxial contact structure146may have more defects.

In some embodiments, epitaxial contact structure146can be epitaxially grown on p-type S/D regions using precursors including a silicon precursor, a germanium precursor, and a doping precursor. The silicon precursor can include silane (SiH4) or disilane (Si2H6). The germanium precursor can include germane (GeH4), digermane (Ge2H6), or germanium tetrachloride (Ge2Cl4), The doping precursor can include diborane (B2H6) or other p-type doping precursor. The deposition process can further include a selectivity gas of hydrogen chloride (HCl) and a carrier gas of nitrogen or hydrogen. The selectivity gas can remove porous epitaxial structures grown on areas other than S/D regions and improve the selectivity of the epitaxial growth on S/D regions. The carrier gas can carry the precursors during the epitaxial process. In some embodiments, epitaxial contact structure146can include an active dopant higher than about 1×1021cm−3to reduce its resistance.

In some embodiments, epitaxial contact structure146can be epitaxially grown on n-type S/D regions using precursors including a silicon precursor and a doping precursor. The silicon precursor can include silane (SiH4) or disilane (Si2H6). The doping precursor can include phosphine (PH3), arsine (AsH3), or other it-type doping precursor. The deposition process can further include a selectivity gas of hydrogen chloride (HCl) or chlorine (Cl2) and a carrier gas of nitrogen or hydrogen. The selectivity gas can improve the selectivity of the epitaxial process. The carrier gas can carry the precursors during the epitaxial process. In some embodiments, epitaxial contact structure146can include an active dopant higher than about 1×1021cm−3to reduce its resistance.

According to some embodiments, first portion146-1can be a plug portion of epitaxial contact structure1146in contact with S/D region110B in opening1064B. Second portion146-2can be cap portion of epitaxial contact structure146on first portion146-1. In some embodiments, horizontal dimension146w1of first portion146-1of epitaxial contact structure146can range from about 8 nm to about 20 nm. Horizontal dimension146w2of epitaxial contact structure146can range from about 8 nm to about 30 nm. In some embodiments, the ratio of horizontal dimensions146w2to146w1can range from about 1 to about 3. In some embodiments, second portion146-2can have one or more sloped facets capping first portion146-1, as shown inFIG.1D. In some embodiments, second portion146-2can have a rounded top surface capping on first portion146-1, as shown inFIGS.1C and11. Epitaxial contact structure146can be grown by a cyclic deposition/etch process. The repeated cycles of deposition and etching can result in a rounded profile as illustrated inFIGS.1C and11. In some embodiments, the rounded profile is not a perfect circular shape; the cross-sectional profile may vary.

The formation of epitaxial contact structure146can be followed by removal of mask layer1166, formation of backside barrier layer140, formation of metal silicide layers148, and formation of metal contacts150. Mask layer1166can be removed by an etching process. Backside barrier layer140can be conformally deposited in openings1064A and1064B, followed by a directional etching process to expose top surfaces of S/D region110A and epitaxial contact structure146. In some embodiments, backside barrier layer140can have a thickness140tranging from about 1 nm to about 3 nm. Backside barrier layer140can prevent metal diffusion during the formation of metal contacts150.

The formation of backside barrier layer140can be followed by the formation of metal silicide layers148. In some embodiments, metal silicide layers148can be deposited and annealed at a temperature below about 450° C. In some embodiments, metal layers148can include metals having lower SBH (e.g., about 0.1 eV) and lower contact resistance on S/D region110A. Examples of the metals used for forming metal silicide layers148can include Ti. The formation of metal silicide layers148can be followed by the formation of metal contacts150. Metal contacts1150can be formed by chemical vapor deposition (CVD) or other suitable deposition methods. In some embodiments, metal contacts150can include conductive materials with low resistivity, such as W, Al, Co, Ru, Rh, Ir, Ti, Ta, Ag, metal alloys, and other suitable metals.

In some embodiments, epitaxial contact structure146can reduce the contact resistance of backside contact structure104B between S/D region110B and metal contacts150. For example, as shown inFIG.16, embodiment 1 can include no epitaxial contact structures and embodiments 2 and 3 can include epitaxial contact structure146with high concentration of active dopants (e.g., higher than about 1×1021cm−3). The width axis inFIG.16can be a horizontal dimension of S/D regions110E (e.g.,146w1) for embodiment 1 and horizontal dimension146w2of epitaxial contact structure146for embodiment 2 (as shown inFIG.1C). Compared with embodiment 1 at the same width, embodiment 2 can reduce the contact resistance by about 30% to about 70% via epitaxial contact structure146with a high active dopant concentration. In addition, with the increase of the width of epitaxial contact structure146(e.g.,146w2), the contact resistance of embodiment 2 can further reduce because of the increased contact area at the interface between epitaxial contact structure146and metal silicide layer148. Embodiment 3 can include epitaxial contact structure146with a different flow to optimize the dimensions of epitaxial contact structure146and to further reduce the contact resistance. In some embodiments, epitaxial contact structure146may be in contact with backside ILD layer136and backside ESL138. Epitaxial contact structure146may not include metals that can diffuse into backside ILD layer136and backside ESL138, thereby backside barrier layer may not be needed between epitaxial contact structure146and backside ILD layer136and between epitaxial contact structure146and backside ESL138. As such, horizontal dimension146w1of epitaxial contact structure146can increase, the resistance of epitaxial contact structure146can be reduced, and the contact resistance of backside contact structure104B can be reduced.

FIG.13is a flow diagram of a method1300for fabricating semiconductor device200with backside contact structures having dual metal silicide layers, in accordance with some embodiments. Method1300may not be limited to GAA FETs and can be applicable to devices that would benefit from backside contact structures with reduced contact resistance, such as planar FETs, fin FETs, etc. Additional fabrication operations may be performed between various operations of method1300and may be omitted merely for clarity and ease of description. Additional processes can be provided before, during, and/or after method1300; one or more of these additional processes are briefly described herein. Moreover, not all operations may be needed to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously or in a different order than shown inFIG.13. In some embodiments, one or more other operations may be performed in addition to or in place of the presently described operations. For example purposes, the operations illustrated inFIG.13can be described with reference to the example fabrication process for fabricating semiconductor device200as illustrated inFIGS.4-10and14-15.FIGS.4-10and14-15can be cross-sectional views of semiconductor device200with backside contact structures having dual metal silicide layers at various stages of its fabrication process, in accordance with some embodiments. AlthoughFIGS.4-10and14-15illustrate fabrication processes of semiconductor device200with dual metal silicide layers in FEY102B, method1300can be applied to semiconductor device200with dual metal silicide layers in FET102A and other semiconductor devices, Elements inFIGS.14-15with the same annotations as elements inFIGS.1A-1E and4-10are described above.

Referring toFIG.13, operations1310and1320are similar to operations310and320respectively, which are described above with reference toFIGS.4-10. For example, in operation1310, FET102A including S/D region110A and FET102B including S/D region110E can be formed on first side406S1of substrate406. In operation1320, a portion of S/D region110A can be etched on second side406S2of substrate406to form opening1064A and a portion of S/D region110B can be etched on second side406S2to form opening1064B.

In referring toFIG.13, operation1330continues with the process of selectively forming a first metal silicide layer on the second S/D region in the second opening. For example, as shown inFIG.14, first metal silicide layer148B-1can be selectively formed on S/D region1109in opening1064B without a mask layer and a patterning process (also referred to as “maskless metal silicide layer1489-1”). In some embodiments, first metal silicide layer148B-1can include metals having lower SBH (e.g. 0.1 eV) and lower contact resistance on S/D region110B. Examples of the metals used for forming first metal silicide layer1488-1can include Ni, Ru, and Co. In some embodiments, first metal silicide layer148B-1can have a thickness148t-1ranging from about 0.1 nm to about 3 nm. Prior to the selective formation of first metal silicide layer148B-1, backside barrier layer140can be can be conformally deposited in openings1064A and1064B, followed by a directional etching process to expose top surfaces of S/D regions110A and110B. In some embodiments, backside barrier layer140can include silicon nitride and have a thickness140tranging from about 1 nm to about 3 nm. Backside barrier layer140can prevent metal diffusion during the formation of metal contacts150.

In some embodiments, first metal silicide layer148B-1can be selectively deposited on S/D region110B by atomic layer deposition (ALD), CVD, or other suitable methods. A selectivity between S/D region110B and S/D region110A can range from about 5 to about 15. In some embodiments, first metal silicide layer148B-1can be formed by thermal ALD with ammonia (NH3) using a precursor of Ni at a temperature from about 150° C. to about 250° C. under a pressure from about 1 mTorr to about 100 mTorr. The deposition rate can range from about 0.1 Å/cycle to about 1.0 Å/cycle and the deposition cycles can range from about 200 to about 600. The deposited metal can be annealed under a temperature below 400° C. to form first metal silicide layer148B-1. If the temperature is lower than about 150° C., the pressure is lower than about 1 mTorr, the deposition rate is less than 0.1 Å/cycle, or the deposition cycles are less than about 200, first metal silicide layer148B-1may not be continuous. If the temperature is higher than about 250° C., the pressure is higher than about 100 mTorr, the deposition rate is greater than 1.0 Å/cycle, or the deposition cycles are greater than about 600, first metal silicide layer148B-1may be thicker than required and can increase the contact resistance between S/D region110B and metal contact150. If the annealing temperature is higher than about 400° C., metals in front-side interconnects and power rails may diffuse and device performance may be negatively impacted.

In some embodiments, first metal silicide layer148B-1can be formed by thermal, ALD with an oxidizing agent using a precursor of Ru at a temperature from about 150° C. to about 300° C. under a pressure from about 1 mTorr to about 100 mTorr. The deposition rate can range from about 0.1 Å/cycle to about 1.0 Å/cycle and the deposition cycles can range from about 50 to about 300. The deposited metal can be annealed under a temperature below 400° C. to form first metal, silicide layer148B-1. If the temperature is lower than about 150° C., the pressure is lower than about 1 mTorr, the deposition rate is less than 0.1 Å/cycle, or the deposition cycles are less than about 50, first metal silicide layer148B-1may not be continuous. If the temperature is higher than about 300 the pressure is higher than about 100 mTorr, the deposition rate is greater than 1.0 Å/cycle, or the deposition cycles are greater than about 300, first metal silicide layer148B-1may be thicker than required and can increase the contact resistance between S/D region110B and metal contact150. If the annealing temperature is higher than about 400° C., metals in front-side interconnects and power rails may diffuse and device performance may be negatively impacted.

In some embodiments, first metal silicide layer148B-1can be formed by thermal ALD with ammonia (NH3) using a precursor of Co at a temperature from about 200° C. to about 350° C. under a pressure from about 1 mTorr to about 100 mTorr. The deposition rate can range from about 0.1 Å/cycle to about 1.0 Å/cycle and the deposition cycles can range from about 200 to about 600. The deposited metal can be annealed under a temperature below 400° C. to form first metal silicide layer148B-1. If the temperature is lower than about 200° C., the pressure is lower than about 1 mTorr, the deposition rate is less than 0.1 Å/cycle, or the deposition cycles are less than about 200, first metal silicide layer148B-1may not be continuous. If the temperature is higher than about 350° C., the pressure is higher than about 100 mTorr, the deposition rate is greater than 1.0 Å/cycle, or the deposition cycles are greater than about 600, first metal silicide layer148B-1may be thicker than required and can increase the contact resistance between S/D region110B and metal contact150. If the annealing temperature is higher than about 400° C., metals in front-side interconnects and power rails may diffuse and device performance may be negatively impacted.

In operation1340ofFIG.13, a second metal silicide layer is formed on the first metal silicide layer and on the first S/D region. For example, as shown inFIG.15, second metal silicide layer148B-2can be deposited non-selectively on first metal silicide layer148B-1in opening1064B and S/D region110A in opening1064A, followed by an anneal at a temperature below about 450° C. In some embodiments, second metal silicide layer148B-2can include metals having lower SBH (e.g., about 0.1 eV) and lower contact resistance on S/D region110A. Examples of the metals used for forming second metal silicide layer148B-2can include Ti. The formation of second metal silicide layer148B-2can be followed by formation of metal contacts150and backside power rails103.

After the formation of metal silicide layers and metal contacts, backside contact structure104A can have second metal silicide layer148B-2having lower SBH (e.g., about 0.1 eV) and lower contact resistance on S/D region1110A. Backside contact structure104B can have first metal silicide layer148B-1having lower SBH (e.g., about 0.1 eV) and lower contact resistance on S/D region1108and second metal silicide layer148B-2on first metal silicide layer148B-1. First metal silicide layer148B-1on S/D region110E and second metal silicide layer148B-2can S/D region110A can be referred to as “dual metal silicide layers.” As a result of dual metal silicide layers, semiconductor device200can reduce contact resistances of backside contact structure104B by about 30% to about 70% without increasing contact resistances of backside contact structure104A. In some embodiments, backside contact structure104B can include both epitaxial contact structure146and metal silicide layers148B-1and148B-2to further reduce the contact resistances (not shown).

Various embodiments in the present disclosure provide methods for forming a semiconductor device (e.g.,100and200) with backside contact structures104A and1048. According to some embodiments, backside contact structures104A and104B can include epitaxial contact structure146. Epitaxial contact structure146can have first portion146-1in contact with source/drain (S/D) region110B of semiconductor device100and second portion146-2on first portion146-1, A width (e.g.,146w2) of second portion146-2can be larger than a width (e.g.,146w1) of first portion146-1. The contact area between epitaxial contact structure146and metal contact150can be increased and the contact resistance of backside contact structure104B can be reduced by about 30% to about 70%. In some embodiments, epitaxial contact structure146can include an active dopant higher than about 1×1021cm−3to further reduce the contact resistance of backside contact structure104B.

In some embodiments, backside contact structures104A and104B can include different metal silicide layers in contact with the S/D regions of different types of FETs in semiconductor device200. For example, backside contact structure104B of one type of FET (e.g., PFET102B) can have first metal silicide layer148B-1on S/D region110B and second metal silicide layer148B-2on first metal silicide layer148B-1, Backside contact structure104A of an opposite type of FET (e.g., NFET102A) can include second metal silicide layer148B-2on the S/D regions. First metal silicide layer148B-1can include a metal different from second metal silicide layer148B-2, Which can reduce the SBH between first metal silicide layer148B-1and the S/D region110E of semiconductor device200and thus reduce the contact resistance of backside contact structure104B by about 30% to about 70%. With first metal silicide layer148B-1in one type of FET (e.g., PFET102B) and second metal silicide layer148B-2in an opposite type of PET (e.g., NFET102A), the contact resistance of backside contact structure104B in the semiconductor device200can be reduced without increasing the contact resistance of backside contact structure104A.

In some embodiments, a method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

In some embodiments, a method includes forming first and second semiconductor devices on a first side of a substrate. The first semiconductor device includes a first source/drain (S/D) region and the second semiconductor device includes a second S/D region. The method further includes etching a portion of the first S/D region to form a first opening and a portion of the second S/D region to form a second opening on a second side of the substrate, electively forming a first metal silicide layer on the second S/D region in the second opening, and forming a second metal silicide layer on the first metal silicide layer and on the first S/D region. The second side is opposite to the first side. The second metal silicide layer includes a metal different from the first metal silicide layer

In some embodiments, a semiconductor device includes a fin structure on a first side of a substrate, a gate structure wrapped around the fin structure, a source/drain (S/D) region in contact with the fin structure, and an epitaxial contact structure in contact with the S/D region on a second side of the substrate. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region and a second portion above the first portion. A width of the second portion is larger than the first portion.