CHARGE-INJECTION SAR ADC FOR CORRECTING FULL SCALE PVT VARIATION

A charge-injection SAR ADC device has a modified charge-injection cell (CIC), and a complementary to absolute temperature (CTAT) circuit for generating a bias voltage. The CIC and CTAT circuits cooperate to correct for process, voltage, and temperature (PVT) variation that affect SAR ADC input full scale. The CIC has been modified to have transistors that are in a cascoded relationship with transistors operating to maintain a reservoir of charge. The CTAT circuit is designed to substantially replicate the CIC, and it tracks the CIC operation to correct variations in transistor threshold voltage due to variations in PVT.

1. FIELD OF THE INVENTION

The present disclosure relates generally to the area of analog-to-digital converters, and specifically to charge-injection cell-based SAR ADC design.

Various types of analog-to-digital converters (ADC) are employed in electronic devices to convert analog signal information to a format that is suitable for storage in computer memory, or that is suitable to be operated on by a digital signal processor. One application for an ADC can be an audio communication system (i.e., audio or video conferencing system) that comprises a microphone for capturing environmental sound (i.e., voice signals) that are then converted for processing by the system in order to remove certain unwanted information from the signal, such as background noise or acoustic echo. ADCs can also be incorporated into CAP-RAM memory circuits used for in-memory computing applications. In this case the ADC can be connected to one or more CAP-RAM macros and operate to receive a charge maintained on capacitors comprising the CAP-RAM. The output of each ADC can be sent to digital periphery functionality which operates to shift and add the partial sums sampled by the ADC.

One type of ADC that has come into use is a Successive Approximation Register (SAR) ADC.FIG.1is a diagram illustrating the functional elements comprising a SAR-ADC10. The SAR-ADC10inFIG.1, has a relatively small form factor, is energy efficient, and can perform the analog-to-digital conversion process very rapidly. The SAR-ADC10is comprised of sample and hold functionality11, a comparator12, a sequential approximate register (SAR)13and a DAC14.

Generally, a SAR-ADC has a capacitive-type DAC element.FIG.2is a diagram showing a SAR-ADC20having such a capacitive DAC21. The DAC21is comprised of a comparator23an array of capacitors labeled22A-22N, with N being an integer. The DAC can occupy more or less space depending upon the number of bits supported by the DAC design. In operation, an analog signal level is sampled by each capacitor and made available to the comparator23under control of the logic (CL). Note, that the SAR-ADC20has a reference voltage (Vref) that is employ by the DAC21to generate an analog voltage that is proportional to the reference voltage. The accuracy of the DAC output voltage is a function of the accuracy/stability of the Vref. However, incorporating an internal or external voltage reference into the design of a DAC can, depending upon the requirements of an application, take to much device real estate or require to much power to operate.

Certain applications require that the space occupied by a SAR-ADC be relatively small, or at least smaller than that occupied by a SAR ADC comprising a capacitive type DAC. In order to satisfy this requirement, the size of the DAC can be reduced by replacing the capacitor array with charge injection cells (CICs). Such a charge-injection cell SAR-ADC (ci-SAR ADC) is shown with reference toFIG.3. Each CIC, labeled CIC.1 to CIC.N. comprising the SAR ADC30inFIG.3can be reused for different steps of a SAR process, which has the effect of reducing the overall size of this type of SAR-ADC.

3. BRIEF DESCRIPTION OF THE DRAWINGS

FIG.1is a diagram showing functional elements comprising a SAR-ADC10.

FIG.2is a diagram showing functional elements comprising a SAR-ADC20.

FIG.3is a diagram showing functional elements comprising a Charge-Injection Cell SAR-ADC30.

FIG.4is a diagram showing elements comprising a Charge-Injection Cell associated with a SAR ADC.

FIG.5is a diagram showing elements comprising an embodiment of a Charge-Injection Cell50.

FIG.6is a diagram showing functional elements comprising an embodiment of a Charge-Injection Cell SAR ADC60.

4. Detailed Description

Depending upon variations in the process used to fabricate a ci-SAR ADC, and depending upon variations in a temperature at which a ci-SAR ADC operates (i.e., together referred to generally as ProcesVoltageTemperature or PVT), a ci-SAR input full scale can vary. Further, a charge stored by a ci-SAR ADC typically also is comprised of a parasitic capacitance (Cp) stored at a FET drain terminal comprising a CIC, such as the drain node on FET M4 inFIG.4. The Cp can also vary depending upon variations in PVT. Variations in ci-SAR input can affect the operation of a DAC and comparator combination associated with the ci-SAR, which can result in a false ADC output, and ultimately denigrate the integrity of information that is being converted.

According to one embodiment, we have mitigated the above problem by modifying a standard charge-injection cell (CIC) to have a cascoded device, which in combination with a novel bias circuit design operates to correct PVT related variations in the ci-SAR ADC input full scale by adjusting the cascoded device gate voltage. This bias circuit tracks and substantially replicates the CIC, and operates to correct variations in the FET threshold voltage (Vt) due to variations in Process, Voltage and Temperature (PVT).

More specifically, a ci-SAR ADC device has circuit elements that operate to generate a PVT corrected voltage used to control the operation of a cascoded device added to a standard CIC. The PVT corrected voltage value is applied to a CIC replica circuit, and the resulting voltage is used to bias a device cascoded with respect to the CIC. Accordingly, the CIC can operate to inject a correct charging current into the DAC.

The above and other embodiments will now be described with reference to the figures, in whichFIG.5illustrates an embodiment of a CIC50having two FETs M0 and M1 cascoded with respect to FETs M3 and M2. A voltage (Vcas) generated by a biasing circuit (described later with reference toFIG.6), is applied to each of the cascoded FETs M0 and M1, which operate in conjunction with the FETs M3 and M2 to inject an amount of capacitive charge (i.e., corrected current) via the FETs M5 and M4 to a DAC labeled DAC− and DAC+. This capacitive charge is maintained by the CIC50in a charge reservoir labeled Cr, and in a parasitic capacitance labeled Cp. In operation the CIC50is controlled by a signal generated by the gates G1, G2 and G3, which are in turned controlled by signals received from an ADC comparator (not shown) and SAR logic. More specifically, the amount of charge injected by the CIC50is a function of an Xfer/Enable pulse width generated by the gate labeled G3. The longer this gate enables the transfer/injection, the greater the charge that is injected to the DAC. The operation of the comparator and SAR logic will not be described here in any detail, as the design and operation of a CIC type SAR ADC is well known the those skilled in this art.

Continuing to refer toFIG.5, and as mentioned earlier with reference toFIG.2, since incorporating a voltage reference (Vref) into a DAC comprising a CIC, or providing an external Vref, either occupies to much device real estate or requires to much power to operate. In light of the above, CICs are typically designed to operate without a Vref. From one perspective, the charge transfer functionality of a CIC has replaced a Vref, which is otherwise used with a DAC. As mentioned above, the amount of charge transferred by a CIC is a function of a predetermined/programmable pulse width of a G3 Xfer/Enable signal, and this pulse width is sensitive to the value of Vdd. As such, the value of Vdd is employed by a CIC as a defacto voltage reference. Unfortunately, the value of Vdd can vary depending upon the temperature at which the FETs operate, and this variation in the value of Vdd can affect the code generated by the ADC. Depending upon the application, occasional errors in code generated by an ADC may be tolerated. However, errors may not be satisfactory for applications that require a high degree of stability/accuracy in an analog signal to digital signal conversion operation. One such application can be the detection of keyword information in a voice signal captured by a microphone. If the digital information used for the detection process (typically by some sort of a neural network) does not accurately represent the analog information captured by the microphone, then the keyword detection process may not arrive at the correct conclusion.

FIG.6illustrates the circuit elements comprising a ci-SAR ADC60according to an embodiment of the invention. The ADC60is comprised of a biasing circuit61, a CIC62controlled by logic gates G1, G2 and G3, and a SAR and control logic63. The CIC62is similar to the CIC50inFIG.5, and in this vein a voltage Vss (and not a Vref) is applied to the source nodes of the FETs M3 and M2. Generally, the FET threshold voltage (Vt) trends lower as the FET operating temperature trends higher. This has the effect of lowering the value of the voltage at the node Vx, which results in the value of the capacitance Cr trending higher. In order to compensate for this, the ADC60is designed to have the bias circuit60that operates to generate a correcting voltage (Vcas) which is applied to the gates of the cascoded FETs labeled M0 and M1 comprising the CIC62. Applying the Vcas bias voltage to the cascoded FETs raises or lowers, as necessary, the current through these devices, which has the effect of correcting the stored capacitive charge injected into the DAC.

InFIG.6, a FET labeled M10 is the same or matches the FETs labeled M0 and M1, and the FET labeled M12 matches the FETs labeled M3 and M3, and this correspondence allows the behavior of M0/M3 to automatically track the M10/M12 behavior. Further, according to this circuit arrangement, the value of Vout (Vcas) changes with respect to PVT which results in the value of Vx changing with respect to PVT.

The biasing circuit61is designed to generate a current/voltate that is complementary to absolute temperature (CTAT), which in this case is the temperature at which the CIC FETs operate. The current/voltage generated by the CTAT circuit has a reciprocal relationship with respect to the temperature at which the CIC operates (i.e, the voltage increases or decreases in value as the temperature decrease or increases respectively). The FETs labeled M1, M2, M3, M4 and M5 in the circuit61match (i.e., are the same type of device) M1′, M2′, M3′, M4 and M5 in the CIC62. Further, the FETs labeled M10 and M12 match FETs M0 and M3, while some of the other FETs may not have a matching relationship.