Semiconductor package and method for making the same

The present invention relates to a semiconductor package and a method for making the same. The semiconductor package comprises a substrate, a first metal layer, a first dielectric layer, a first upper electrode, a first protective layer, a second metal layer and a second protective layer. The substrate has at least one via structure. The first metal layer is disposed on a first surface of the substrate, and comprises a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first capacitor. The second metal layer is disposed on the first protective layer, and comprises a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor package and method for making the same, and more particularly to a semiconductor package having passive device and method for making the same.

2. Description of the Related Art

FIG. 1shows a cross-sectional view of a conventional semiconductor package. The conventional semiconductor package1comprises a substrate11, a package unit12and a molding compound13. The package unit12comprises a plurality of passive devices (not shown in the FIGs). The package unit12is disposed on the substrate11, and electrically connects the substrate11. The molding compound13encapsulates the package unit12.

The conventional semiconductor package1has the following defects. The passive devices are integrated into the package unit12by a semiconductor packaging process. Then, the package unit12electrically connects the substrate11by wire-bonding method or flip-chip method (not shown in the FIGs). Therefore, the process for integrating the passive devices in the semiconductor package1are complex and increase cost.

Therefore, it is necessary to provide a semiconductor package and method for making the same to solve the above problems.

SUMMARY OF THE INVENTION

The present invention is directed to a method for making a semiconductor package. The method comprises the steps of: (a) providing a substrate, the substrate having at least one groove and at least one conductive via structure, the conductive via structure disposed in the groove; (b) forming a first metal layer on the substrate, the first metal layer having a first lower electrode, the first metal layer directly contacting the conductive via structure; (c) forming a first dielectric layer and a first upper electrode on the first lower electrode, wherein the first dielectric layer is disposed between the first upper electrode and the first lower electrode, and the first upper electrode, the first dielectric layer and the first lower to electrode form a first capacitor; (d) forming a first protective layer, encapsulating the first capacitor, the first protective layer having at least one first opening, part of the first upper electrode exposed on the first opening; (e) forming a second metal layer on the first protective layer, the second metal layer having a first inductor, the second metal layer directly contacting the first upper electrode; and (f) forming a second protective layer, encapsulating the first inductor.

Therefore, the method of the invention can simplify the process of the first inductor and the first capacitor, and the first inductor, the first capacitor and the via structure can be integrated into the semiconductor package so as to reduce the size of the product.

The present invention is further directed to a semiconductor package. The semiconductor package comprises a substrate, a first metal layer, a first dielectric layer, a first upper electrode, a first protective layer, a second metal layer and a second protective layer. The substrate has a first surface, a second surface, at least one groove and at least one via structure. The groove penetrates through the first surface and the second surface. The via structure is disposed in the groove and is exposed on the first surface and the second surface of the substrate. The first metal layer is disposed on the first surface of the substrate, and has a first lower electrode. The first metal layer directly contacts the via structure. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer. The first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first capacitor. The first protective layer has at least one first opening. Part of the first upper electrode is exposed on the first opening. The second metal layer is disposed on the first protective layer, and has a first inductor. The second metal layer directly contacts the first upper electrode. The second protective layer encapsulates the first inductor.

Therefore, the first inductor, the first capacitor and the via structure can be integrated into the semiconductor package so as to reduce the size of the product.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2 to 22show schematic views for illustrating a method for making a semiconductor package according to a first embodiment of the present invention. Referring toFIG. 2, a substrate21is shown. The substrate21has a first surface211, a lower surface212, at least one groove213and at least one conductive via structure217. The groove213has an opening disposed on the first surface211of the substrate21. The conductive via structure217is disposed in the groove213, and is exposed on the first surface211of the substrate21.

In this embodiment, the substrate21is non-insulated material, for example silicon or germanium. The conductive via structure217comprises an outer insulation layer2141, a conductor2142and an inner insulation layer2143. The outer insulation layer2141is disposed on the side wall of the groove213, and the outer insulation layer2141defines a second central groove2144. The conductor2142is disposed on the side wall of the second central groove2144, and the conductor2142defines a first central groove2145. The inner insulation layer2143is filled up the first central groove2145. In other embodiments, the outer insulation layer2141can also be disposed on the bottom wall of the groove213(not shown). Since the substrate21is non-insulated material, the outer insulation layer2141is used for insulating the substrate21and the conductor2142so as to prevent the current which passes through the conductive via structure217being conducted to the substrate21and reducing the electrical character of the conductive via structure217.

However, in other embodiments, as shown inFIG. 3, the conductive via structure217may only comprise an outer insulation layer2141and a conductor2142, and does not comprise the inner insulation layer2143(FIG. 2). The outer insulation layer2141is disposed on the side wall of the groove213, and the outer insulation layer2141defines a second central groove2144. The conductor2142is filled up the second central groove2144. Besides, the substrate21can be made of insulation material, for example glass or silicon oxide, and the conductive via structure217may not comprise the outer insulation layer2141(FIG. 2). Therefore, as shown inFIG. 4, the conductive via structure217may only comprise a conductor2142and an inner insulation layer2143, wherein the conductor2142is disposed on the side wall and the bottom of the groove213to define a first central groove2145, and the first central groove2145is filled with the inner insulation layer2143. In addition, as shown inFIG. 5, the conductive via structure217may only comprise a conductor2142, wherein the groove213is filled with the conductor2142. As shown inFIG. 6, a first insulation bottom layer22is formed on the substrate21. In this embodiment, the first insulation bottom layer22is disposed on the first surface211of the substrate21, and has a first through via221. The conductive via structure217is exposed in the first through via221.

Then, a first metal layer23(FIG. 9) is formed on the substrate21, the first metal layer23has a first lower electrode232. In this embodiment, the first metal layer23is disposed on the first insulation bottom layer22, and the first metal layer23directly contacts the conductive via structure217. The steps of forming the first metal layer23are described as follows. Referring toFIG. 7, a first seed layer233is formed on the substrate21. Referring toFIG. 8, a first photo resist234is formed on the first seed layer233to cover part of the first seed layer233and to expose part of the first seed layer233. And, a first plating layer235is formed on the exposed part of the first seed layer233. Referring toFIG. 9, the first photo resist234(FIG. 8) and the covered part of the first seed layer233are removed, and the first plating layer235and part of the first seed layer233form the first metal layer23.

Then, a first dielectric layer24(FIG. 11) and a first upper electrode25(FIG. 11) are formed on the first lower electrode232. The first dielectric layer24is disposed between the first upper electrode25and the first lower electrode232, and the first upper electrode25, the first dielectric layer24and the first lower electrode232form a first capacitor26(FIG. 11). The steps of forming the first dielectric layer24are described as follows. Referring toFIG. 10, a third metal layer is formed on the first lower electrode232, for example by sputtering method, and proceeding anodic oxidation process to the third metal layer to form a first oxide layer241. The material of the third metal layer is Tantalum (Ta), and the material of the first oxide layer241is Tantalum Pentoxide (Ta2O5). Then, a fourth metal layer251is formed on the first oxide layer241, for example by sputtering method. The material of the fourth metal layer251is AlCu. Then, a second photo resist261is forming on the fourth metal layer251. Referring toFIG. 11, part of the first oxide layer241(FIG. 10) and part of the fourth metal layer251(FIG. 10) are removed to form the first dielectric layer24and the first upper electrode25respectively, and form the first capacitor26. The second photo resist261(FIG. 10) is removed.

Referring toFIG. 12, a first protective layer27is formed for encapsulating the first capacitor26. The first protective layer27has at least one first opening271, and part of the first upper electrode25is exposed on the first opening271.

Then, a second metal layer35(FIG. 15) is formed on the first protective layer27. The second metal layer35has a first inductor351, and the second metal layer35directly contacts the first upper electrode25. In this embodiment, the steps of forming the second metal layer35are described as follows. Referring toFIG. 13, a second seed layer352is formed on the first protective layer27. Referring toFIG. 14, a third photo resist353is formed on the second seed layer352to cover part of the second seed layer352and to expose part of the second seed layer352. And, a second plating layer354is formed on the exposed part of the second seed layer352. Referring toFIG. 15, the third photo resist353(FIG. 14) and the covered part of the second seed layer352are removed, and the second plating layer354and part of the second seed layer352form the second metal layer35. Referring toFIG. 16, a second protective layer36is formed for encapsulating the first inductor351. The second protective layer36comprises at least one second opening361, and part of the second metal layer35is exposed on the second opening361.

Then, at least one first bump28(FIG. 19) is formed in the second opening361of the second protective layer36, and the first bump28is electrically connected to the second metal layer35. In this embodiment, the steps of forming the first bump28are described as follows. Referring toFIG. 17, a third seed layer281is formed on the second protective layer36. Referring toFIG. 18, a fourth photo resist282is formed on the third seed layer281to cover part of the third seed layer281and to expose part of the third seed layer281. And, a third plating layer283is formed on the exposed part of the third seed layer281. Referring toFIG. 19, the fourth photo resist282and the covered part of the third seed layer281are removed to form the first bump28.

Referring toFIG. 20, the substrate21is mounting on a carrier29, wherein the first surface211of the substrate21faces the carrier29. And, part of the substrate21is removed from the lower surface212(FIG. 19) of the substrate21to form a second surface215, and the conductor2142of the conductive via structure217(FIG. 19) is exposed on the second surface215of the substrate21to form a via structure214. In other embodiments, the substrate21can be removed further to expose the inner insulation layer2143of the conductive via structure217(FIG. 19) on the second surface215of the substrate21so as to ensure that the conductor2142of the conductive via structure217(FIG. 19) is exposed on the second surface215.

Referring toFIG. 21, at least one electrical device is formed on the second surface215of the substrate21. In this embodiment, the electrical device is a second bump31. The method for forming the second bump31is the same as that for the first bump28. Referring toFIG. 22, the carrier29is removed so as to obtain the semiconductor package2according to the first embodiment of the present invention. The electrical device may be a second inductor32or a second capacitor33, as shown inFIG. 23. The method for forming the second inductor32and the second capacitor33is the same as that for forming the first inductor351and the first capacitor26, that is, the process on the second surface215can be the same as that on the first surface211.

Therefore, the method of this invention can simplify the process of the first inductor351and the first capacitor26, and the first inductor351, the first capacitor26and the via structure214can be integrated into the semiconductor package2so as to reduce the size of the product.

Referring toFIG. 22again, it shows a cross-sectional view of the semiconductor package according to the first embodiment of the present invention. The semiconductor package2of this embodiment comprises a substrate21, a first insulation bottom layer22, a second insulation bottom layer34, a first metal layer23, a first dielectric layer24, a first upper electrode25, a first protective layer27, a second metal layer35, a second protective layer36, at least one first bump28and at least one electrical device. In this embodiment, the electrical device is a second bump31.

The substrate21has a first surface211, a second surface215, at least one groove213and at least one via structure214. The groove213penetrates through the first surface211and the second surface215. The via structure214is disposed in the groove213, and is exposed on the first surface211and the second surface215of the substrate21.

In this embodiment, the substrate21is non-insulated material, for example silicon or germanium. The via structure214comprises an outer insulation layer2141, a conductor2142and an inner insulation layer2143. The outer insulation layer2141is disposed on the side wall of the groove213, and the outer insulation layer2141defines a second central groove2144. The conductor2142is disposed on the side wall of the second central groove2144, and the conductor2142defines a first central groove2145. The inner insulation layer2143is filled up the first central groove2145. In other embodiments, the outer insulation layer2141can also be disposed on the bottom wall of the groove213(not shown). Since the substrate21is non-insulated material, the outer insulation layer2141is used for insulating the substrate21and the conductor2142so as to prevent the current which passes through the via structure214being conducted to the substrate21and reducing the electrical character of the via structure214.

In other embodiments, the via structure214may only comprise an outer insulation layer2141and a conductor2142, and does not comprise the inner insulation layer2143. The outer insulation layer2141is disposed on the side wall of the groove213, and the outer insulation layer2141defines a second central groove2144. The conductor2142is filled up the second central groove2144. Besides, the material of the substrate may be made of insulation material, for example glass or silicon oxide, and the conductive via structure217may not comprise the outer insulation layer2141. Therefore, the via structure214may only comprise a conductor2142and an inner insulation layer2143. The conductor2142is disposed on the side wall of the groove213, and the conductor2142defines a first central groove2145. The inner insulation layer2143is filled up the first central groove2145. In addition, the via structure214may only comprise a conductor2142, and the conductor2142is filled up the groove213.

Referring toFIG. 22again, the first insulation bottom layer22is disposed on the first surface211of the substrate21, and has a first through via221. The via structure214is exposed in the first through via221. The second insulation bottom layer34is disposed on the second surface215of the substrate21, and has a second through via341. The via structure214is exposed in the second through via341. The first metal layer23is disposed on the first surface211of the substrate21, preferably, is disposed on the first insulation bottom layer22, and has a first lower electrode232. The first metal layer23directly contacts the via structure214. The first dielectric layer24is disposed on the first lower electrode232. In this embodiment, the material of the first dielectric layer24is Tantalum Pentoxide (Ta2O5). The first upper electrode25is disposed on the first dielectric layer24. The first upper electrode25, the first dielectric layer24and the first lower electrode232form a first capacitor26. The material of the first upper electrode25is AlCu.

The first protective layer27encapsulates the first capacitor26. In is this embodiment, the first protective layer27has at least one first opening271. Part of the first upper electrode25is exposed on the first opening271. The second metal layer35is disposed on the first protective layer27, and has a first inductor351. The second metal layer35directly contacts the first upper electrode25. The second protective layer36encapsulates the first inductor351. In this embodiment, the second protective layer36comprises at least one second opening361, and part of the second metal layer35is exposed on the second opening361. The first bump28is disposed in the second opening361of the second protective layer36, and the first bump28is electrically connected to the second metal layer35. The electrical device is disposed on the second surface215of the substrate21. The electrical device is a second bump31.

Therefore, the first inductor351, the first capacitor26and the via structure214can be integrated into the semiconductor package so as to reduce the size of the product.

FIG. 23shows a cross-sectional view of a semiconductor package according to a second embodiment of the present invention. The semiconductor package3according to the second embodiment is substantially the same as the semiconductor package2(FIG. 22) according to the first embodiment, and the same elements are designated by the same reference numbers. The difference between the semiconductor package3according to the second embodiment and the semiconductor package2according to the first embodiment is that the semiconductor package3further comprises a plurality of electrical devices on the second surface215, for example a second inductor32, a second capacitor33and a second bump31.

FIGS. 24 to 32are schematic views for illustrating a method for making a semiconductor package according to the third embodiment of the present invention. Referring toFIG. 24, the substrate21is shown. In this embodiment, the substrate21has an upper surface216and a second surface215, at least one groove213and at least one conductive via structure217. The groove213has an opening disposed on the second surface215of the substrate21, and the conductive via structure217is disposed in the groove213, and is exposed on the second surface215of the substrate21. Referring toFIG. 25, a second insulation bottom layer34is formed on the substrate21. In this embodiment, the second insulation bottom layer34is disposed on the second surface215of the substrate21, and has a second through via341. The conductive via structure217is exposed in the second through via341. Then, at least one electrical device is formed on the second surface215of the substrate21, preferably, on the second insulation bottom layer34. In this embodiment, the electrical device is a second bump31. Referring toFIG. 26, the substrate21is mounting on a carrier29, and the second surface215of the substrate21faces the carrier29. And, part of the substrate21is removed from the upper surface216(FIG. 25) of the substrate21to form a first surface211, and the conductive via structure217is exposed on the first surface211of the substrate21to form a via structure214.

Referring toFIG. 27, a first metal layer23is formed on the substrate21, preferably, on the first surface211of the substrate21. A first plating layer235and a first seed layer233form the first metal layer23. The first metal layer23has a first lower electrode232. Referring toFIG. 28, a first dielectric layer24and a first upper electrode25are formed on the first lower electrode232. The first dielectric layer24is disposed between the first upper electrode25and the first lower electrode232, and the first upper electrode25, the first dielectric layer24and the first lower electrode232form a first capacitor26. Referring toFIG. 29, a first protective layer27is formed for encapsulating the first capacitor26. The first protective layer27has at least one first opening271, and part of the first upper electrode25is exposed on the first opening271. Referring toFIG. 30, a second metal layer35is formed on the first protective layer27. A second plating layer354and a second seed layer352form the second metal layer35. The second metal layer35has a first inductor351, and the second metal layer35directly contacts the first upper electrode25. Referring toFIG. 31, a second protective layer36is formed for encapsulating the first inductor351. The second protective layer36comprises at least one second opening361, and part of the second metal layer35is exposed on the second opening361. Referring toFIG. 32, at least one first bump28is formed in the second opening361of the second protective layer36, and the first bump28is electrically connected to the second metal layer35. Then, the carrier29is removed so as to obtain the semiconductor package2according to the third embodiment of the present invention.

FIGS. 33 to 35show schematic views for illustrating a method for making a semiconductor package according to a fourth embodiment of the present invention. The method for making a semiconductor package according to the fourth embodiment is substantially the same as the method for making a semiconductor package according to the first embodiment, and the same elements are designated by the same reference numbers. Referring toFIG. 33, the substrate21has a first surface211, a second surface215, at least one groove213and at least one conductive via structure. The groove213penetrates through the first surface211and the second surface215. The conductive via structure is disposed in the groove213, and is exposed on the first surface211and the second surface215of the substrate21to form a via structure214. Then, referring toFIG. 34, a first inductor351and a first capacitor26are formed on the first surface211of the substrate21. Referring toFIG. 35, at least one electrical device is formed on the second surface215of the substrate21so as to obtain the semiconductor package according to the forth embodiment of the present invention. In other embodiments, the electrical device can be formed on the second surface215of the substrate21first, then the first inductor351and the first capacitor26are formed on the first surface211of the substrate21.

While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined by the appended claims.