Rapid discharging circuit upon detection of abnormality

Provided is a protection circuit that is connected between a power supply terminal and an output terminal, and turns off an output transistor when an abnormality occurs in a system, the output transistor outputting a current to a load connected to the output terminal, the protection circuit including: a first discharge unit that is connected between a gate electrode of the output transistor and the power supply terminal, and discharges an electric charge of the gate electrode until a potential of the gate electrode becomes equal to a power supply potential, when an abnormality occurs in the system, and a second discharge unit that is connected between the gate electrode and a source electrode of the output transistor, and discharges the electric charge of the gate electrode until the potential of the gate electrode becomes equal to an output potential, when an abnormality occurs in the system.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-160513, filed on Jul. 7, 2009, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a function of rapidly turning off upon detection of an abnormality.

2. Description of Related Art

In recent years, semiconductor devices have been used in systems having a switch function capable of driving a large current, as typified by electrical components for automobiles. Each system that drives a large current has a function of switching itself off upon detection of an overheat, an overcurrent, or the like so as to protect the system when an abnormality occurs in which a load is short-circuited and a large current flows, for example.

In the operation in which the system switches itself off upon detection of an abnormality, it is important to reduce a heat loss that occurs upon turn-off. This is because if a large heat loss occurs upon turn-off, a breakdown may occur, since it is highly possible that a large amount of heat is generated when an abnormality is detected. Accordingly, in the turn-off operation upon detection of an abnormality, it is important to rapidly turn off.

Japanese Unexamined Patent Application Publication No. 2005-123666 (Kojima et al.) discloses a technique for an output circuit that rapidly turns off.FIG. 7is a diagram showing the configuration of the output circuit according to the technique disclosed by Kojima et al. Referring toFIG. 7, an output circuit300includes an output MOS100which is connected between a power supply terminal and an output terminal. The output MOS100is an N-type enhancement transistor having a circuit switching function. A transistor Q1and a transistor Q2are N-type depletion or enhancement transistors. A transistor Q3is an N-type enhancement transistor. A resistor R1is connected between the transistor Q1and the output terminal, and a resistor R2is connected between the transistor Q2and the output terminal. Thus, the transistors Q1to Q3form three discharge paths between the gate terminal of the output MOS100and the output terminal. The output circuit300also includes a state determination circuit304that controls the discharge of an electric charge stored in the gate electrode of the output MOS100by selecting the discharge paths. The output circuit300further includes a control signal input circuit301, a booster circuit302, and a rise rate303, which are blocks for controlling the output MOS100in the normal state.

In the normal state, the control signal input circuit301receives a signal for turning on and off the output MOS100. Based on the signal, the booster circuit302outputs a boosted voltage to the gate terminal through the rise rate303. In the case of turning off the output MOS in the normal state, the booster circuit302suspends operation and the state determination circuit304detects a voltage between the power supply terminal and the output terminal, based on the signal output from the control signal input circuit301. The output circuit300includes a discharge path formed of the transistor Q1and the resistor R1, a discharge path formed of the transistor Q2and the resistor R2, and a discharge path formed of the transistor Q3. Based on the signal output from the state determination circuit304, one or more discharge paths are activated to discharge a gate charge of the output MOS to the output terminal, thereby turning off the output MOS.

The state determination circuit304measures a voltage between the power supply terminal and the output terminal and detects whether an overcurrent flows, for example, thereby detecting an abnormality. In this case, an OFF signal for forcibly turning off the MOS100is input to the control signal input circuit301. Further, based on the signal output from the state determination circuit304, one or more of the three discharge paths are activated to discharge the gate charge of the output MOS to the output terminal, thereby turning off the output MOS.

In the turn-off operation in the normal state, the transistor Q1is activated. In a rapid turn-off operation in an overcurrent state, only the transistor Q3or both the transistor Q1and the transistor Q2are activated at the same time. In the turn-off operation when a current which is larger than that in the normal state and smaller than an overcurrent flows, only the transistor Q2or both the transistor Q2and the transistor Q1are activated at the same time, thereby adjusting the slew rate.

In the overcurrent state, the operation of the transistor Q3, which is an enhancement transistor, is especially important. The rapid turn-off operation is accomplished in such a manner that the transistor Q3rapidly discharges the gate charge of the output MOS. Next, the operation of the transistor Q3will be described in detail. Herein, a description is given to the following two cases:(1) a case where the rapid turn-off operation is accomplished by activating only the transistor Q3; and(2) a case where the rapid turn-off operation is accomplished by activating all the transistors Q1to Q3.

(1) The Case where the Rapid Turn-Off Operation is Accomplished by Activating only the Transistor Q3

Assuming that a gate-source voltage of the transistor Q3is Vgs3and a threshold voltage is Vthn, Vgs3>Vthn should be satisfied in order to turn on the transistor Q3. Assuming that a gate voltage is Vx, the threshold voltage of the transistor Q3is Vthn, and an output voltage is OUT, Vx−OUT>Vthn is established, so it is necessary to apply a signal having a potential level, which satisfies Vx>OUT+Vthn, to the gate. Also, it is necessary to generate the signal in the state determination circuit.

Assuming herein that a voltage at the power supply terminal is VCC, an ON-resistance of the output MOS is Ron, and a current driven by the output MOS is lout, an output potential OUT is given by OUT=VCC−Iout·Ron. For example, assuming that VCC=12 V, Iout=70 A, Ron=10 mΩ, and Vthn=1 V, OUT=12 V−70 A×10 mω=11.3 V is established, and therefore Vx>11.3 V+1 V=12.3 V. Accordingly, it is necessary that the gate voltage Vx be equal to or higher than the power supply voltage VCC. This is merely an example, and even if the voltage equal to or higher than the power supply voltage VCC is not applied, the transistor Q3can be turned on. In the case where the transistor Q3turns on at a voltage equal to or lower than the power supply voltage VCC, the transistor Q3operates in a saturation region at the start of the turn-off operation, with the result that the discharge current is limited immediately after the discharge operation is started. In order to achieve the rapid discharge operation using only the transistor Q3immediately after the start of the discharge operation, it is necessary to apply a high voltage to the gate so that the transistor Q3can sufficiently drive the current. Also, it is necessary to apply a voltage equal to or higher than the power supply voltage VCC to the gate voltage Vx. Therefore, a booster circuit such as a bootstrap is required.

(2) The Case where the Rapid Turn-Off Operation is Accomplished by Activating all the Transistors Q1to Q3

A potential equal to the power supply voltage level is applied to the gate of the transistor Q3, and the transistors Q1and Q2are activated at the same time. In the case where the transistors Q1and Q2are depletion transistors, the transistors Q1and Q2turn on upon application of a potential equal to the power supply voltage VCC or the output voltage OUT. When the transistors Q1and Q2discharge the gate charge of the output MOS and a predetermined amount of electric charge is discharged, the output potential OUT starts to decrease. This enables the transistor Q3to turn on. Further, when the output voltage OUT decreases with the progress of the discharge operation and when Vgs3>Vds3−Vthn, i.e., Vx−OUT>GATE−OUT+Vthn (where GATE represents the potential of the gate electrode of the output MOS) is satisfied, the transistor Q3can cause a large discharge current to flow, because the transistor Q3operates in a linear region.

Thus, when the rapid discharge operation is accomplished by using the transistors Q1to Q3, the transistor Q3is not necessarily turned on after the turn-off operation. Therefore, it is sufficient that the voltage GATE to be applied to the gate is equal to the power supply voltage VCC. This eliminates the need to provide a special circuit such as a bootstrap. However, in order to increase the discharge current, it is necessary to increase the size of the transistors, since the transistors Q1and Q2carry out the discharge operation immediately after the turn-off operation and the transistors Q1and Q2are depletion transistors.

SUMMARY

The present inventors have found a problem as described below. As described above, in order to accomplish the rapid discharge operation using only the transistor Q3in the output circuit of the prior art shown inFIG. 7, a booster circuit such as a bootstrap is required. Further, in order to accomplish the rapid discharge operation by turning on the transistors Q1to Q3, it is necessary to increase the size of the transistors Q1and Q2which carry out the discharge operation at the start of the turn-off operation. This results in an undesirable increase in the area of the transistors.

A first exemplary aspect of the present invention is a protection circuit that is connected between a power supply terminal and an output terminal, and turns off an output transistor when an abnormality occurs in a system, the output transistor outputting a current to a load connected to the output terminal, the protection circuit including: a first discharge unit that is connected between a gate electrode of the output transistor and the power supply terminal, and discharges an electric charge of the gate electrode until a potential of the gate electrode becomes equal to a power supply potential, when an abnormality occurs in the system, and a second discharge unit that is connected between the gate electrode and a source electrode of the output transistor, and discharges the electric charge of the gate electrode until the potential of the gate electrode becomes equal to an output potential, when an abnormality occurs in the system.

A second exemplary aspect of the present invention is a method of turning off an output transistor when an abnormality occurs in a system, the output transistor being connected between a power supply terminal and an output terminal and outputting a current to a load connected to the output terminal, the method including: discharging, upon detection of an abnormality in the system, an electric charge of the gate electrode of the output transistor until a potential of the gate electrode becomes equal to a power supply potential; and discharging, upon detection of an abnormality in the system, the electric charge of the gate electrode of the output transistor until the potential of the gate electrode becomes equal to an output potential.

According to an exemplary aspect of the present invention, a rapid turn-off operation can be accomplished with a small area by positively utilizing a parasitic bipolar transistor and discharging a gate charge to the power supply terminal at the start of a discharge operation.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

First Exemplary Embodiment

Exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.FIG. 1Ais a block diagram showing a high-side output circuit1according to a first exemplary embodiment of the present invention. The high-side output circuit according to the first embodiment includes an output MOS100. The output MOS100is connected between a power supply terminal102and an output terminal103, and outputs a current to a load connected to the output terminal103. The high-side output circuit1also includes abnormality detection circuits and a protection circuit. The abnormality detection circuits detect an abnormality in a system. The protection circuit rapidly turns off the output MOS100when the abnormality detection circuits detect an abnormality in the system.

In the first exemplary embodiment, the protection circuit is included in a discharge circuit5. A voltage sensor7, a temperature sensor8, and a current sensor6are provided as the abnormality detection circuits. The high-side output circuit1further includes an internal power supply2, a control unit3, and a booster circuit4.

In order to interrupt energization to the output MOS100and to the load when the input is turned off (deactivated) or when an abnormality is detected, the discharge circuit5discharges a gate charge of the output MOS100to the output terminal103so that a potential difference between the gate electrode of the output MOS100and the output terminal103becomes 0 V.

The booster circuit4turns on and off the output MOS100during normal operation. The internal power supply2supplies power to circuits that need not directly receive a power supply voltage from the outside. The control unit3controls a control signal supplied from the outside, an abnormal state detected within the circuit, and other blocks upon restoration to the normal state.

As described above, the high-side output circuit1includes the current sensor6, the temperature sensor8, and the voltage sensor7, each of which serves as the abnormality detection circuit that detects an abnormality in the system. The current sensor6monitors a load current flowing through the load. The temperature sensor8monitors the temperature of the output MOS100. The voltage sensor7monitors a voltage OUT of the output terminal103. These abnormality detection circuits output an abnormality detection signal to each of the control unit3and the discharge circuit5, upon detection of an abnormality in the circuit. Specifically, the abnormality detection signal is output when the current sensor6detects an abnormal magnitude of the load current flowing through the load, when the voltage sensor7detects an abnormal voltage OUT of the output terminal103, or when the temperature sensor8detects an abnormal temperature of the output MOS100. Note that the first exemplary embodiment is described assuming that the high-side output circuit1includes the current sensor6, the voltage sensor7, and the temperature sensor8. However, the high-side output circuit1may include at least one of these sensors as means for detecting an abnormality in the system.

FIG. 1Bis a timing diagram showing potential variations when the high-side output circuit1turns on and off in the normal state.FIG. 1Bshows an input potential IN, a gate potential GATE of the output MOS100, a power supply voltage VCC, and a potential of the output voltage OUT. When a switch S turns on and the input voltage IN becomes equal to the ground level, the booster circuit4generates a boosted voltage which is higher than the power supply voltage VCC, and supplies the boosted voltage to the gate terminal of the output MOS100. This allows the output MOS100to turn on and allows a current to flow through the load.

Next, the discharge circuit5according to the first exemplary embodiment will be described in detail below.FIG. 2Ais a circuit diagram showing the discharge circuit5according to the first exemplary embodiment. As shown inFIG. 2A, the discharge circuit5includes a normal turn-off circuit10that performs a turn-off operation in the normal state, and a protection circuit (hereinafter, referred to as a rapid turn-off circuit)20athat rapidly turns off the output MOS100in an abnormal state.

The rapid turn-off circuit20aincludes a first discharge unit and a second discharge unit. The first discharge unit is connected between a gate electrode104of the output MOS100and the power supply terminal102. When an abnormality occurs in the system, the first discharge unit discharges the potential GATE of the gate electrode104until the potential GATE becomes equal to the power supply potential VCC. The second discharge unit is connected between the gate electrode and the source electrode of the output MOS100. When an abnormality occurs in the system, the second discharge unit discharges an electric charge of the gate electrode until the potential of the gate electrode becomes equal to the output voltage OUT.

FIG. 2Aillustrates only the components located on the surface of a silicon device of the rapid turn-off circuit20a. Meanwhile,FIG. 2Billustrates the components located on the surface of the silicon device, as well as parasitic bipolar transistors of a second transistor M212and a third transistor M213.

The first discharge unit includes a first depletion-type transistor M214, the second enhancement-type transistor M212, and the third enhancement-type transistor M213. The first depletion-type transistor M214has a drain connected to the gate electrode of the output MOS transistor100, and a gate and a source that are short-circuited. The second enhancement-type transistor M212has a drain connected to the gate electrode of the output MOS transistor100, and a gate and a source that are short-circuited. The third enhancement-type transistor M213is connected between the second transistor M212and the source electrode of the output MOS transistor100. Parasitic bipolar transistors Q21to Q23of the second transistor M212discharge the electric charge of the gate electrode until the potential of the gate electrode becomes equal to the power supply potential. A parasitic bipolar transistor Q24of the third transistor M213discharges the electric charge of the gate electrode until the potential GATE of the gate electrode becomes equal to the output voltage OUT. The second discharge unit includes a transistor M215which is connected between the gate electrode and the source electrode of the output MOS100.

The output MOS100is an N-type enhancement transistor having a drain connected to the power supply terminal102, and a source connected to the output terminal103. A transistor M211of the normal turn-off circuit and the first transistor M214are N-type depletion transistors having a gate and a source that are short-circuited, and operate as constant current sources. The second transistor M212is an N-type enhancement transistor that is disposed so as to utilize the parasitic bipolar transistors. The third transistor M213is a P-type enhancement transistor that is disposed so as to prevent the first transistor M214from discharging the gate charge of the output MOS100to the output terminal103in the normal state or upon turn-on. The transistor M215is an N-type enhancement transistor having a source connected to the output terminal103.

Reference symbols VdepBG1, VdepBG2, and VenhG denote control signals which are generated using circuits shown inFIGS. 4A to 4Das described later.

Next, the parasitic bipolar transistors will be described.FIG. 2Bshows the four parasitic bipolar transistors Q21, Q22, Q23, and Q24that operate during a rapid turn-off operation.

The first to third parasitic bipolar transistors Q21to Q23are parasitic bipolar transistors of the second transistor M212. The fourth parasitic bipolar transistor Q24is a parasitic bipolar transistor of the third transistor213.

The first parasitic bipolar transistor Q21discharges the electric charge of the gate electrode of the output MOS100to the power supply terminal102by using a current from the first transistor M214as a base current. The second parasitic bipolar transistor Q22supplies a current to the third and fourth parasitic bipolar transistors Q23and Q24by using a current from the first transistor M214as a base current.

The third parasitic bipolar transistor Q23discharges the electric charge of the gate electrode of the output MOS100to the power supply terminal102with a current from the second parasitic bipolar transistor Q22, by using a current from the first transistor M214as a base current. The fourth parasitic bipolar transistor Q24discharges the electric charge of the gate electrode of the output MOS100to the output terminal103with a current from the second parasitic bipolar transistor Q22.

In general, an amplification factor “hfe1” of each of the transistors Q21and Q23formed in the longitudinal direction of the transistor is large, while an amplification factor “hfe2” of each of the transistors Q22and Q24formed in the lateral direction of the transistor is small.

FIGS. 3A to 3Care sectional views each showing a silicon device according to an exemplary embodiment of the present invention.FIG. 3Ais a sectional view of the second transistor M212. The parasitic bipolar transistor Q21operates using the drain of the transistor M212as a collector, an N-substrate, which is a substrate region, as an emitter, and a P-well, which is formed in the N-substrate, as a base. The parasitic bipolar transistor Q23operates using the source of the second transistor M212as a collector, the N-substrate as an emitter, and the P-well as a base. The parasitic bipolar transistor Q22operates using the drain of the second transistor M212as a collector, the source of the second transistor M212as an emitter, and the P-well as a base.

FIG. 3Bis a sectional view showing the third transistor M213. The parasitic bipolar transistor Q24operates using the source of the third transistor M213as an emitter, the drain of the third transistor M213as a collector, and the N-substrate as a base.

FIG. 3Cis a sectional view showing the transistors M211, M214, and M215. Since the transistors M211, M214, and M215are N-type transistors, parasitic bipolar transistors Q251to Q259exist in the longitudinal direction. The backgate voltage VdepBG2of the transistor M214is lower than the source potential of the transistor M214(the gate potential GATE of the MOS100) and the drain potential of the transistor M214(a voltage V2). Therefore, the parasitic bipolar transistors Q251to Q259do not operate. The same is true of the transistors M211and M215.

FIGS. 4A to 4Dare diagrams each showing a control signal generation circuit according to an exemplary embodiment of the present invention.FIG. 4Ashows a circuit that generates a voltage GNDX from the power supply voltage VCC. Transistors M216and M217are N-type depletion transistors. A transistor M218is an N-type enhancement transistor. A diode D21is a Zener diode.

The control signal generation circuit shown inFIG. 4Bis a circuit that operates between VCC and GNDX, receives an input signal SIN, and generates the control signal VdepBG1for controlling the backgate of the transistor M211shown inFIGS. 2A and 2B. A transistor M219is an N-type depletion transistor. A transistor M220is a P-type enhancement transistor.

The control signal generation circuit shown inFIG. 4Cis a circuit that receives an abnormality detection signal OC and generates the control signal VdepBG2for controlling the backgate of the transistor M214shown inFIGS. 2A and 2B. A transistor M221is an N-type depletion transistor. A transistor M222is a P-type enhancement transistor.

The control signal generation circuit shown inFIG. 4Dis a circuit that receives the abnormality detection signal OC and generates the control signal VenhG for controlling the gate of the transistor M215shown inFIGS. 2A and 2B. Transistors M223and M225are P-type enhancement transistors. Transistors M224and M226are N-type depletion transistors.

Next, the operation of each element will be described. The operations shown inFIGS. 4A to 4Dare first described. Herein, the input signal SINand the abnormality detection signal OC are defined as follows.(1) Normal ON state (input is active and abnormality detection is inactive) input signal SIN=IN, abnormality detection signal OC=IN(2) Normal OFF state (input is inactive and abnormality detection is inactive) input signal SIN=VCC, OC=IN(3) Abnormality detection state (input is active and abnormality detection is inactive) input signal SIN=IN, abnormality detection signal OC=VCC
(1) Normal ON State

The transistor M218shown inFIG. 4Afully turns on, because the transistor M218receives an input inversion signal SIN—B=VCC at the gate. The transistor M216operates as a constant current source. Assuming that the diode D21has a breakdown voltage of VZe, GNDX=VCC−VZe is satisfied. In the normal ON state, the transistor M217also causes a constant current to flow. Thus, the constant current flowing through the transistor M217and the current flowing through the diode D21flow through the transistor M216.

The transistor M219shown inFIG. 4Boperates as a constant current source. The transistor M220turns on upon receiving SIN=GND at the gate, and the control signal VdepBG1becomes “L” level. Note that it is necessary to connect an n+region serving as a backgate of a P-type transistor to the potential VCC of the N-substrate, because the discharge circuit according to the first exemplary embodiment includes the P-well formed in the N-substrate. Accordingly, in the connected state of the transistor M220, the backgate effect is produced. As a result, VdepBG2=GNDX is not met, and a voltage which is about 2 V higher than GNDX is obtained, for example. Such a state is hereinafter represented by VdepBG2=GNDX+α.

The transistor M222shown inFIG. 4Creceives OC=IN and operates in a similar manner as inFIG. 4B, and VdepBG2=IN+α is satisfied. Referring toFIG. 4D, the transistor M223receives OC=IN, and an inverter composed of the transistors M223and M224outputs the potential VCC. Further, an inverter composed of the transistors M225and M226outputs the potential OUT. Each of the input and output levels is equal to the “L” level, but the level is shifted from the input voltage IN to the output voltage OUT.

(2) Normal OFF State

The transistor M218shown inFIG. 4Areceives the input inversion signal SIN—B=VCC at the gate, and the transistor M218is cut off. As a result, the transistors M216and M217also turn off and the drain-source voltage becomes 0 V. Accordingly, GNDX=VCC is satisfied. The transistor M220shown inFIG. 4Breceives the input signal SIN=IN and is cut off. As a result, the transistor M219also turns off and the drain-source voltage Vds becomes 0 V (Vds=0 V). Accordingly, VdepBG1=OUT is satisfied. Referring toFIGS. 4C and 4F, in the normal OFF state, OC=IN is maintained as in the normal ON state. Therefore, VdepBG2=GNDX+α and VenhG=OUT are satisfied.

(3) Abnormality Detection State

Referring toFIGS. 4A and 4B, SIN—B=VCC and SIN=IN are maintained as in the normal ON state. Accordingly, GNDX=VCC−VZe and VdepBG1=GNDX+α are satisfied. Referring toFIG. 4C, the transistor M222receives OC=VCC at the gate, so the transistor M222is cut off and VdepBG2=OUT is satisfied. Referring toFIG. 4D, the transistor M223receives OC=VCC at the gate and outputs VenhG=VCC through the two-stage inverters.

Thus, the signal output in the normal ON state, the signal output in the normal OFF state, and the signal in the abnormality detection state are defined as follows.

(1) Normal ON State

Next, a description is given of the operation of the discharge circuit shown inFIG. 2Bwhich receives these signals.

(1) Normal ON State

The transistor M211receives VdepBG1=GNDX+α at the backgate, and thus a backgate-source voltage Vbs211=VdepBG1−OUT is satisfied. In the normal ON state, the output MOS transistor100fully turns on, so the voltage OUT is nearly equal to the voltage VCC (OUT≈VCC). Accordingly, Vbs211=(GNDX+α)−VCC=(VCC−VZe+α)−VCC=−VZe+α is satisfied. Assuming that VZe=5V and α=2V, the backgate-source voltage Vbs211is −3 V (Vbs211=−3 V), and thus the transistor M211is cut off.

Further, the second transistor M212turns off in any state, since the gate and source thereof are short-circuited. The third transistor M213turns off in any state, as with the second transistor M212, since the third transistor M213receives the voltage VCC at the gate. The transistor M214receives IN+α at the backgate, so a backgate-source voltage Vbs214=VdepBG2−OUT=(IN+α)−VCC=−VCC+α is established, for example. Assuming that VCC=12 V and α=2 V, the backgate-source voltage is −10 V (Vbs214=−10 V), and thus the transistor M214is cut off.

Since the transistor M214is cut off, the base current of each of the parasitic bipolar transistors Q21to Q23is zero, with the result that the parasitic bipolar transistors Q21to Q23turn off. Further, since the second transistor M212and the first transistor M214are cut off, no current flows to the parasitic bipolar transistor Q24, with the result that the parasitic bipolar transistor Q24turns off. The transistor M215receives the potential of VenhG=OUT at the gate, and a gate-source voltage Vgs215is 0 V (Vgs215=0 V), and thus the transistor M215is cut off. As described above, since all the transistors turn off, the gate charge of the output MOS100is not discharged. Therefore, the normal ON state is maintained.

(2) Turn-Off Operation in the Normal State

In the normal OFF state, the transistor M211receives the signal VdepBG1=OUT at the backgate, so the transistor M211operates as a constant current source and discharges the gate charge of the output MOS100to the output terminal103. The second transistor M212, the third transistor M213, the transistor M214, and the transistor M215turn off, because the transistors remain in the same state as the normal ON state. The parasitic bipolar transistors Q21to Q24also turn off. As described above, only the transistor M211turns on to serve as a constant current source, and discharges the gate charge of the output MOS100to be turned off. The slew rate in the turn-off operation can be adjusted through adjustment of the current ability of the transistor M211.

(3) Turn-Off Operation in the Abnormality Detection State

In the abnormality detection state, the transistor M211is cut off in the same manner as in the normal ON state. Further, the second transistor M212and the third transistor M213are cut off as in the same manner as in the normal ON state and the normal OFF state.

Now, a description is given of the first discharge unit that discharges the gate potential GATE until the gate potential GATE becomes equal to the power supply voltage VCC when an abnormality occurs in the system. The first transistor M214receives the potential OUT of the output terminal103at the backgate, and operates as a constant current source. A current flowing through the first transistor M214serves as a base current of the parasitic bipolar transistors Q21to Q23. The parasitic bipolar transistor Q21amplifies the base current, which is received from the first transistor M214, by hfe1, and discharges the gate charge of the output MOS100to the power supply terminal102.

Similarly, the parasitic bipolar transistor Q22causes a current obtained by amplifying the base current by hfe2to flow through the parasitic bipolar transistors Q23and Q24. Note that the parasitic bipolar transistor Q22has a current amplification factor smaller than that of the parasitic bipolar transistor Q23, since the parasitic bipolar transistor Q22is a lateral bipolar transistor. Also the parasitic bipolar transistor Q23receives the base current of the first transistor M214, and causes a part of a current flowing through the parasitic bipolar transistor Q22to flow as a discharge current for discharging the gate charge of the output MOS100to the power supply terminal102.

Further, a part of a current flowing through the parasitic bipolar transistor Q22flows from the emitter to the base of the parasitic bipolar transistor Q24. Thus, a part of the current flowing through the parasitic bipolar transistor Q22flows as a discharge current from the gate of the output MOS100to the output terminal103. Note that the current flowing through the parasitic bipolar transistors Q23and Q24is determined by the parasitic bipolar transistor Q22located on the collector side, and the parasitic bipolar transistor Q22has a small amplification factor. Thus, the amount of discharge current flowing through the parasitic bipolar transistors Q23and Q24is not as large as that of the parasitic bipolar transistor Q21. By these operations, the electric charge is discharged from the gate of the output MOS100to the power supply terminal102.

Next, a description is given of the second discharge unit that discharges the potential GATE of the gate electrode until the potential GATE becomes equal to the output potential OUT. When the first discharge unit discharges the gate charge of the output MOS100to the power supply terminal102, the gate voltage GATE of the output MOS100starts to decrease. When a predetermined amount of gate charge is discharged, the potential OUT starts to decrease. The transistor M215receives VenhG=VCC at the gate. Accordingly, when the output voltage OUT decreases and the gate-source voltage Vgs215of the transistor M215=VCC−OUT>Vthn is satisfied, the transistor M215turns on and contributes to the discharge operation. Further, when the output voltage OUT decreases and Vgs215>Vds215−Vthn⇄(VCC−OUT)>(GATE−OUT)>Vthn is satisfied, the transistor M215operates in a linear region. This allows a large discharge current to flow. Thus, the second discharge unit discharges the electric charge until the gate potential of the output MOS100becomes equal to the potential of the output voltage OUT.

The operations to be performed upon detection of an abnormality are summarized below. At the start of the turn-off operation, the parasitic bipolar transistors Q21to Q24that constitute the first discharge unit discharge the gate charge of the output MOS100to the power supply terminal102, and discharge the gate electrode of the output MOS100to the output terminal103, thereby lowering the potential of the output voltage OUT. Then, the transistor M215that constitutes the second discharge unit turns on to discharge the remaining gate charge of the output MOS100to the output terminal103, thereby turning off the output MOS100. Such a configuration in which both the first discharge unit and the second discharge unit discharge the gate charge makes it possible to accomplish the rapid turn-off operation.

The distribution of the current, which flows through the first transistor M214and serves as a base current, to the bases of the parasitic bipolar transistors Q21to Q23is determined by a resistance across the source of the first transistor M214and the base of each of the parasitic bipolar transistors Q21to Q23. To increase the discharge current from the gate of the output MOS100, the current is amplified to a larger degree. In order to this, it is effective to increase the base current of the parasitic bipolar transistor Q21, and it is desirable to reduce the resistance across the source of the first transistor M214and the base of the parasitic bipolar transistor Q21.

Next, a modified example of the exemplary embodiment of the first exemplary embodiment will be described. In the first exemplary embodiment, the control signal generation circuit shown inFIG. 4Cis provided between OUT and GND. Alternatively, even if the control signal generation circuit is provided between OUT and GNDX, the same effects of the rapid turn-off operation can be obtained. Note that when the voltage GNDX is used instead of the GND voltage, VdepBG2=OUT is satisfied also in the normal OFF state. Accordingly, the first transistor M214turns on and the parasitic bipolar transistors Q21to Q24operate, with the result that the discharge process advances rapidly immediately after the turn-off operation is started.

However, when the gate voltage GATE of the output MOS100decreases to a voltage in the vicinity of the power supply voltage VCC, the parasitic bipolar transistors Q21to Q23stop discharging the electric charge of the gate electrode of the output MOS100to the power supply terminal102, and only the parasitic bipolar transistor Q24continues to discharge the gate charge of the gate electrode to the output terminal103. The parasitic bipolar transistor Q24does not amplify the current flowing through the first transistor M214to a large extent, since the parasitic bipolar transistor Q24has a small amplification factor. Further, the transistor M215does not perform the rapid discharge operation, since the transistor M215receives the voltage OUT at the gate and is cut off. After the parasitic bipolar transistors Q21to Q23stop the discharge operation, the slew rate is determined by the parasitic bipolar transistor Q24and the transistor M211. Accordingly, the slew rate is suppressed during the turn-off operation.

At the start of the turn-off operation, noise may occur, because the slew rate increases owing to the operation of the parasitic bipolar transistors Q21to Q24. However, the noise may be negligible depending on the application. Further, the circuit shown inFIG. 4Cmay be provided between OUT-GNDX.

Second Exemplary Embodiment

Next, a second exemplary embodiment of the present invention will be described. As described in the first exemplary embodiment, the rapid discharge operation is accomplished using the parasitic bipolar transistor Q21of the second transistor M212. However, the channel region of the second transistor M212does not contribute to the discharge operation, and each discharge path formed of the parasitic bipolar transistors Q22to Q24has a current amplification factor smaller than that of the parasitic bipolar transistor Q21. Therefore, it is desirable to cause the current flowing through the first transistor M214to flow not to the base of each of the parasitic bipolar transistors Q22to Q24but to the base of the parasitic bipolar transistor Q21. In the second exemplary embodiment, this situation is improved.

FIG. 5Ais a diagram showing a discharge circuit according to the second exemplary embodiment of the present invention. Components of the discharge circuit shown inFIG. 5Athat are identical to those of the discharge circuit according to the first exemplary embodiment shown inFIG. 2Bare denoted by the same reference symbols, and the detailed description thereof is omitted.

The discharge circuit shown inFIG. 5Aincludes the normal turn-off circuit10that performs a turn-off operation in the normal state, and a rapid turn-off circuit20cthat rapidly turns off the output MOS100in the abnormality state. As withFIG. 2A, the output MOS100is an N-type enhancement transistor having a drain connected to the power supply terminal102, and a source connected to the output terminal103. The transistors M211and M214are N-type depletion transistors whose gate and source are short-circuited, and serve as constant current sources. The transistor M215is an N-type enhancement transistor having a source connected to the output terminal103. A diode D32includes p+and n+regions. A parasitic bipolar transistor Q26is formed by adding the diode D32. Reference symbols VdepBG1, VdepBG2, VenhG inFIG. 5Adenote control signals which are generated using the control signal generation circuits shown inFIGS. 4A to 4D.

FIG. 5Bis a sectional view showing the diode D32. The parasitic bipolar transistor Q21operates using the cathode of the diode D32as a collector, the P-well as a base, and the N-substrate as an emitter.

Next, the operation of the discharge circuit according to the second exemplary embodiment will be described. The normal turn-off operation of the second exemplary embodiment is similar to that of the first exemplary embodiment.

Now, the turn-off operation in the abnormality detection state will be described. As with the first exemplary embodiment, the first transistor M214receives the voltage OUT at the backgate and operates as a constant current source.

The operation of the first discharge unit is described below. A current flowing through the first transistor M214serves as a base current of the parasitic bipolar transistor Q26. The parasitic bipolar transistor Q26amplifies the base current, which is received from the first transistor M214, by hfe1, and discharges the gate charge of the output MOS100to the power supply terminal102.

Next, the operation of the second discharge unit is described below. When the first discharge unit discharges the electric charge of the gate electrode of the output MOS100to the power supply terminal102, the gate potential GATE of the output MOS100starts to decrease. When a predetermined amount of gate charge is discharged, the potential OUT starts to decrease. The transistor M215receives VenhG=VCC at the gate, so when the potential of the output terminal103decreases and the gate-source voltage Vgs215of the transistor M215=VCC−OUT>Vthn is satisfied, the transistor M215turns on and contributes to the discharge operation. Further, when the potential OUT decreases and Vgs215>Vds215−Vthn⇄(VCC−OUT)>(GATE−OUT)>Vthn is satisfied, the transistor M215operates in the linear region. This allows a large discharge current to flow. The second discharge unit discharges the potential GATE of the gate electrode of the output MOS100until the potential GATE becomes equal to the potential of the output voltage OUT.

The operations to be performed upon detection of an abnormality are summarized below. At the start of the turn-off operation, the whole current flowing through the first transistor M214of the first discharge unit serves as the base current of the parasitic bipolar transistor Q26. Further, the parasitic bipolar transistor Q26discharges the gate charge of the output MOS100to the power supply terminal102, and discharges the gate charge of the output MOS100to the output terminal103, thereby lowering the potential of the output terminal103. Then, the transistor M215that constitutes the second discharge unit turns on to discharge the remaining gate charge of the output MOS100to the output terminal103, thereby turning off the output MOS100. Such a configuration in which both the first discharge unit and the second discharge unit discharge the gate charge makes it possible to accomplish the rapid turn-off operation.

In the second exemplary embodiment, the diode D32including the p+and n+regions is disposed so as to generate only the bipolar transistor corresponding to the paratactic bipolar transistor Q21shown inFIG. 2B, unlike the first exemplary embodiment in which parasitic bipolar transistors are obtained by disposing the N-type enhancement transistor such as the transistor M212. The parasitic bipolar transistor Q26equivalent to the parasitic bipolar transistor Q21shown inFIG. 2Bis obtained by disposing the diode formed in the P-well. Consequently, the same effects as those of the first exemplary embodiment can be obtained. Further, the path existing between the transistor M214and the output terminal103inFIG. 2Bis eliminated. This eliminates the need to provide the third transistor M213.

According to the second exemplary embodiment, the whole current flowing through the first transistor M214serves as the base current of the parasitic bipolar transistor Q26in the first discharge unit. Accordingly, the whole current flowing through the first transistor M214is amplified by hfe1. This makes it possible to increase the discharge current compared to the first exemplary embodiment. Further, there is no need to provide the third transistor M213shown inFIG. 2Band the n+region which constitutes the channel region of the transistor shown inFIG. 3Aand the parasitic bipolar transistor Q23. Therefore, the rapid turn-off circuit can be produced with a small area.

Note that the present invention is not limited to the above exemplary embodiments, and can be modified in various manners without departing from the scope of the present invention. For example,FIG. 6Ais a block diagram showing another system according to an exemplary embodiment of the present invention. A high-side output circuit according to this exemplary embodiment shown inFIG. 6Aincludes a GND terminal106which is not included in the high-side output circuit shown inFIG. 1A. Also in the circuit having the GND terminal, the rapid turn-off operation for the output MOS can be accomplished using the discharge circuit similar to that described above. Since the high-side output circuit shown inFIG. 6Ahas the GND terminal, each circuit shown inFIG. 4can use the GND potential instead of the input voltage IN.

The first and second exemplary embodiments can be combined as desirable by one of ordinary skill in the art.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.