Reference voltage generation circuit

Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a reference voltage generation circuit mounted on a semiconductor device, for generating a reference voltage.

2. Description of the Related Art

In recent years, advanced electronic devices have been marketed all over the world and used in various environments. For example, electronic devices are used also in frigid and heavy snowfall areas, tropical areas right on the equator, and other areas. The electronic devices are required to operate normally in almost any temperature environment of human life. Characteristics of a semiconductor device mounted on an electronic device are thus required not to change due to temperature. One reason for deterioration of temperature characteristics of such semiconductor device is that a reference voltage generated by a reference voltage generation circuit in the semiconductor device changes due to temperature.

A related-art reference voltage generation circuit is described with reference toFIG. 4.

The reference voltage generation circuit includes a depletion type NMOS transistor (D-type NMOS transistor)91and an enhancement type NMOS transistor (E-type NMOS transistor)92. The D-type NMOS transistor91has a gate connected to a source thereof so as to function as a constant current circuit. The E-type NMOS transistor92is diode-connected. Those transistors are connected in series between a power supply terminal and a ground terminal. The D-type NMOS transistor91supplies a constant current to the E-type NMOS transistor92. This constant current generates a reference voltage VREF at a drain of the E-type NMOS transistor92.

In this case, the reference voltage VREF is determined by threshold voltages of those transistors and the sizes thereof. Japanese Patent Application Laid-open No. Sho 59-200320 (FIG. 3 and Expression (3)) describes that, by adjusting the sizes of those transistors, temperature dependence of the reference voltage VREF can be reduced.

However, the reference voltage generation circuit disclosed in Japanese Patent Application Laid-open No. Sho 59-200320 has a problem in that the threshold voltages of the transistors may fluctuate due to fluctuations in manufacturing step in a semiconductor manufacturing process and the reference voltage VREF may change due to temperature.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above-mentioned problem, and it is an object thereof to provide a reference voltage generation circuit that has flat temperature characteristics even when there are fluctuations in manufacturing step.

In order to solve the above-mentioned problem, according to one embodiment of the present invention, there is provided a reference voltage generation circuit mounted on a semiconductor device, for generating a reference voltage. The reference voltage generation circuit includes a plurality of unit reference voltage generation circuits, each of which includes: a depletion type NMOS transistor for generating a constant current, which includes a gate doped with N-type impurities and connected to a source thereof; an enhancement type NMOS transistor, which includes a gate doped with P-type impurities, has the same channel impurity profile as a channel impurity profile of the depletion type NMOS transistor, and is diode-connected in series to the depletion type NMOS transistor; a first current interruption circuit for interrupting a current; and a second current interruption circuit provided between a drain of the enhancement type NMOS transistor and a reference voltage terminal. The plurality of unit reference voltage generation circuits has different channel impurity profiles and is connected in parallel.

According to one embodiment of the present invention, even when there are fluctuations in manufacturing step in a semiconductor manufacturing process and when the reference voltages of the plurality of unit reference voltage generation circuits each fluctuate in the reference voltage generation circuit, only a unit reference voltage generation circuit having the most flat temperature characteristics is selected to operate. Consequently, the reference voltage generation circuit can have flat temperature characteristics.

DETAILED DESCRIPTION OF THE INVENTION

First, a configuration of a reference voltage generation circuit is described below with reference toFIG. 1.

The reference voltage generation circuit includes three unit reference voltage generation circuits10.

Each of the unit reference voltage generation circuits10includes a depletion type NMOS transistor (D-type NMOS transistor)11, an enhancement type NMOS transistor (E-type NMOS transistor)12, and fuses13and14.

In the reference voltage generation circuit, power supply terminals of the three unit reference voltage generation circuits10are each connected to a power supply terminal of a semiconductor device. Ground terminals of the three unit reference voltage generation circuits10are each connected to a ground terminal of the semiconductor device. In other words, the three unit reference voltage generation circuits10are connected in parallel between the power supply terminal and the ground terminal of the semiconductor device.

In each of the unit reference voltage generation circuits10, a gate, a source, and a substrate potential of the D-type NMOS transistor11are connected to a reference voltage terminal of the unit reference voltage generation circuit10via the fuse14, and a drain thereof is connected to the power supply terminal of the unit reference voltage generation circuit10. In other words, the D-type NMOS transistor11is connected so as to function as a constant current circuit. A gate and a drain of the E-type NMOS transistor12are connected to the reference voltage terminal of the unit reference voltage generation circuit10via the fuse14, and a source and a substrate potential thereof are connected to the ground terminal of the unit reference voltage generation circuit10via the fuse13. In other words, the E-type NMOS transistor12is diode-connected. Further, the D-type NMOS transistor11, the E-type NMOS transistor12, and the fuse13are connected in series.

Next, a method of manufacturing the reference voltage generation circuit is described below.

In each of the unit reference voltage generation circuits10, both channels of the D-type NMOS transistor11and the E-type NMOS transistor12are doped with the same impurities in the same amount in the same environment. In other words, the D-type NMOS transistor11and the E-type NMOS transistor12have the same channel impurity profile. After that, a gate insulating film and a gate electrode made of polysilicon are formed on both the channels. After that, the gate of the D-type NMOS transistor11is doped with N-type impurities to have N-type conductivity. Further, the gate of the E-type NMOS transistor12is doped with P-type impurities to have P-type conductivity. Accordingly, although the D-type NMOS transistor11and the E-type NMOS transistor12are different in transistor type, namely the depletion type and the enhancement type, because the channel doping into the semiconductor substrate under the gate insulating film is the same therebetween, the D-type NMOS transistor11and the E-type NMOS transistor12have substantially the same device characteristics and hence have substantially the same temperature dependence of the device characteristics.

In this case, in the reference voltage generation circuit, the three unit reference voltage generation circuits10are provided, and the channel doping is set to be different among the three unit reference voltage generation circuits10. In other words, three unit reference voltage generation circuits10having different channel impurity profiles are provided.

Next, an operation of the unit reference voltage generation circuit10is described below.

When the fuses13and14are not cut, the D-type NMOS transistor11supplies a constant current to the E-type NMOS transistor12. This constant current generates the reference voltage VREF at the drain of the E-type NMOS transistor12.

When the fuses13and14are cut, the D-type NMOS transistor11does not supply a constant current to the E-type NMOS transistor12. In other words, the unit reference voltage generation circuit10does not operate.

Next, the reference voltage VREF to be output from the reference voltage generation circuit is described below.

After a semiconductor manufacturing process is finished, electrical characteristics of the semiconductor device are evaluated. In this case, temperature characteristics of the reference voltages VREF of the three unit reference voltage generation circuits10are also each evaluated. Alternatively, temperature characteristics of alternatives to the three unit reference voltage generation circuits10, which are each provided on a scribe line, are each evaluated. After that, only a unit reference voltage generation circuit10having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits10. Only the fuses13and14of the selected unit reference voltage generation circuit10are not cut, but the other fuses13and14are cut. In other words, only the selected unit reference voltage generation circuit10operates, but the other unit reference voltage generation circuits10do not operate. Consequently, the reference voltage VREF output from the selected unit reference voltage generation circuit10serves as the reference voltage VREF output from the reference voltage generation circuit. Then, even when there are fluctuations in manufacturing step in the semiconductor manufacturing process and when the reference voltages VREF of the three unit reference voltage generation circuits10each fluctuate in the reference voltage generation circuit, only a unit reference voltage generation circuit10having the most flat temperature characteristics is selected to operate, and hence the reference voltage generation circuit can have flat temperature characteristics.

Note that, although three unit reference voltage generation circuits10are provided, the present invention is not limited thereto.

Further, in the constant current circuit formed of the D-type NMOS transistor11in the unit reference voltage generation circuit10, the circuit ofFIG. 2Ais used inFIG. 1, where an output terminal of the constant current circuit is the source of the D-type NMOS transistor11. Alternatively, however, as illustrated inFIG. 2B, a circuit including a current mirror circuit11amay be used, where an output terminal of the constant current circuit is an output terminal of the current mirror circuit11a.

Further, in the unit reference voltage generation circuit, the gate of the D-type NMOS transistor11may be connected to the substrate potential as illustrated inFIG. 5, which is another embodiment of the present invention.

Further, the fuse13inFIG. 1is provided on the ground terminal side, but although not illustrated, the fuse13may be provided on the power supply terminal side.

Further, each of the fuses13and14is a current interruption circuit for interrupting a current. As illustrated inFIG. 3, the fuses13and14may be replaced by switches15and16formed of MOS transistors. In this case, the reference voltage generation circuit includes three unit reference voltage generation circuits10and a control circuit20. Although not illustrated, the control circuit20includes a memory element such as a one-time programmable (OTP) memory element. Based on information of the memory element, the control circuit20sends three signals for controlling ON/OFF of the switches15and16included respectively in the three units of reference voltage generation circuit10.

Further, the fuse13may be omitted when current consumption of an IC can be ignored.