Output device for static random access memory

An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger connects to a common output node of a plurality of memory cells. When one of the memory cells is to be read, the common output node is precharged to a high potential. The charge and discharge path circuit connects to the common output node and controls an output voltage on its output node in accordance with an internal first grounding path on or not. The voltage hold circuit connects to both the output node of the path circuit and the common output node and controls a voltage of the common output node in accordance with both the output voltage of the path circuit and an internal second grounding path. When the precharger is precharging, the second grounding path is disconnected.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the technical field of static random access memory (SRAM) and, more particularly, to an output device for static random access memory.

2. Description of Related Art

FIG. 1is a schematic diagram of a typical SRAM and the output device thereof. As shown, for illustrative purpose, only one memory cell100is described, while others are schematically represented by dotted lines. The memory cell100consists of a plurality of metal oxide semiconductor (MOS) transistors and its output end has an N-type metal oxide semiconductor (NMOS) transistor MR. The transistor MR has a drain connected to a node E of an output device120, a gate connected to a control signal RWL (read word line) in order to control data of the memory cell100to be sent to the node E or not. The output device120consists of P-type metal oxide semiconductor (PMOS) transistors101,103,105and107and NMOS transistors102,104and106.

FIG. 2shows a timing diagram of the output device120. As shown inFIG. 2, when data of the memory cell is to be read, the node E of the output device120maintains at high potential for a pre-charging process. Accordingly, in T1interval, control signals PRE and RWL are at low potential, the transistor MR is in off state, and the transistor101is turned on such that a source of the transistor101connects to a voltage Vdd in order to precharge the node E and further maintain the node E at high potential. Next, in T2interval, the potential of the control signal PRE changes from low to high, which represents that the pre-charge on the node E is complete. Then, in the T3interval, the potential of the control signal RWL changes from low to high, which turns on NMOS transistor MR. It represents that data of the memory cell100is sending to the output device120. Next, after T3interval, when data of the memory cell100is in high potential, a node F of the memory cell100is in low potential, such that the transistor MP of the memory cell100is in off state. At this point, the node E maintains at high potential due to the pre-charge. Therefore, the NMOS transistor102is turned on such that a node G is at low potential. Next, in the output device120, a high potential (the same high potential as data of the memory100) on a node OUT is outputted through an inverter122consisting of MOS transistors106and107. On the other hand, when data of the memory100sent is in low potential, the node F of the memory cell100is in high potential, and the transistor MP of the memory cell100is turned on. At this point, a source of the transistor MP is in a potential GND and it pulls down the potential on the node E. Thus, the potential on the node E changes from high to low. Meanwhile, the PMOS transistor103is turned on such that the node G is at high potential. It induces a low potential (the same low potential as data of the memory cell100) on the node OUT, which is outputted through the inverter122consisting of MOS transistors106and107. However, as cited, the node E connects to multiple memory cells so that the load of the node E is higher (indicated by a capacitor108) and when a potential of the node E changes from high to low, it needs more time to pull the potential down. This is why changing the node G to high potential requires a long duration, which wastes time. Besides, the NMOS transistor102needs to be in the turn-on state as node E is in high potential, it will postpone the transistor103to pull the node G to high potential. Thus the node G maintains at low potential when receiving the source potential of the MOS transistor102, which causes the PMOS transistor105turned on. Therefore, a voltage Vdd is provided to the node E through a source of the PMOS transistor105, so that the potential of the node E cannot quickly change from high to low and it wastes a long duration. Accordingly, a long switching time is required when data of the memory cell100sent is low potential.

Further, when a previous memory cell is read as low potential, the node E is at low potential. Since the PMOS transistor103is turned on when the node E is low potential, its source voltage is provided to the node G so as to turn on the NMOS transistor104. Therefore, a voltage GND is provided to the node E through a source of the transistor104. When a pre-charging is performed in T1interval, the node E is charged by the source voltage Vdd of the transistor101to high potential. The transistors101,104function as shown inFIG. 3. The transistor104maintains the node E at low potential, and conversely the transistor101maintains the node E at high potential. Accordingly, a very small size is applied to the transistor104in design, which is much smaller than that to the transistor101, thereby obtaining a higher driving force to achieve the precharge to the node E.

However, by contrast, the very small transistor104has poorer driving capability. This may affect transmitting data of the memory cell100with low potential because when the node G changes to high potential after a certain time waste and thus the NMOS transistor104is turned on to provide the node E with its source voltage GND. The effect of speeding the node E down to a low voltage is relatively reduced due to the cited poorer driving force. Thus, read speed of the memory cell cannot be increased.

Therefore, it is desirable to provide an improved output device for SRAM to mitigate and/or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

The object of the present invention is to provide an output device for static random access memory (SRAM), which can speed up potential transition on nodes of the output device and further increase read speed of the memory.

To achieve the object, the output device of the present invention essentially includes a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger has a common output node connected to output nodes of a plurality of memory cells. When one of the memory cells is to be read, the common output node is precharged to a high potential. The charge and discharge path circuit connects to the common output node and controls an output voltage on its output node in accordance with an internal first grounding path on or not. The voltage hold circuit connects to both the output node of the path circuit and the common output node of the precharger and controls a voltage of the common output node in accordance with both the output voltage of the path circuit and an internal second grounding path. When the precharger is precharging, the second grounding path is disconnected. The output inverter generates a phase inverse voltage to output in accordance with an output voltage at an output node of a discharge path controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 4shows a preferred embodiment of a detail circuit of an output device for SRAM in accordance with the invention, wherein multiple memory cells are connected to a node E, whereas only one memory cell251is shown for illustrative purpose. InFIG. 4, the output device200includes a precharger210, a charge and discharge path circuit220, a voltage hold circuit230and an output inverter240. As shown, the precharger210is a PMOS transistor301to precharge the node E to a high potential before accessing the memory cell251for data transfer. The output inverter240consists of PMOS transistor308and NMOS transistor309, which function identically to the prior art and thus a detailed description is deemed unnecessary. The output device for SRAM is characterized in the charge and discharge path circuit220and the voltage hold circuit230. The charge and discharge path circuit220consists of PMOS transistor302and NMOS transistors303,304. The transistor302has a gate connected to both the node E and a gate of the transistor303, a source connected to a high potential Vdd, and a drain connected to a drain of the transistor303. The transistor303has a source connected to a drain of the transistor304. The transistor304has a source connected to a low potential (such as a ground voltage GND) and a gate connected to an enable signal EN. As compared with the prior art, the NMOS transistor304is added and the enable signal EN is added to control the NMOS transistor304on and off for further controlling a grounding path I1active and inactive. Thus, a potential on a node G can completely be controlled by the transistor302, avoiding the prior problem that the node E cannot quickly changed from a high potential to a low potential.

The voltage hold circuit230consists of PMOS transistor305and NMOS transistors306,307. The transistor305has a gate connected to drains of the transistors302and303and a gate of the transistor306, a source connected to a high potential Vdd, and a drain connected to a drain of the transistor306and the node E. The transistor306has a source connected to a drain of the transistor307. The transistor307has a source connected to a low potential (such as a ground voltage GND) and a gate connected to a precharge signal PRE that controls the PMOS transistor301of the precharger210. The voltage hold circuit230adds an NMOS transistor307and using the precharge signal PRE to control the NMOS transistor307on and off for further controlling another grounding path I2active (to impact on a potential of the node E). Due to the inherent difference between a PMOS and an NMOS, the PMOS transistor301or the NMOS transistor307can not be active both as receiving the same signal. Therefore, interference between the transistors301and307will not occur and the size design for transistors (such as, in this case, transistors306,307) of the voltage hold circuit230can be enlarged to enhance the driving force and speed the feedback transition.

Next, a read timing diagram ofFIG. 4is described inFIG. 5as an operation example of the output device200. The output device200can be operable at an input voltage ranging between 0–1.8V, for example. As shown inFIG. 5, in T1and T2intervals, the output device200is in pre-charging. Meanwhile, the enable signal EN changes from high potential to low potential as T1interval changes to T2interval, so as to disconnect the grounding path I1of the transistor303for controlling the potential of the node G, which is active in a T4interval and described hereinafter.

In T1and T2intervals, the pre-charge signal PRE is in low potential such that the PMOS transistor301is turned on and its source voltage Vdd pre-charges the node E to a high potential. If the node E is in low potential before pre-charged, at this point, the PMOS transistor302is turned on and thus its source voltage Vdd is provided to the node G to turn on the NMOS transistor306. In this case, the NMOS transistor307cannot be turned on due to the low potential of the pre-charge signal PRE, and thus the grounding path I2is blocked (disconnected). As cited, interaction between two transistors ofFIG. 3(i.e., transistors301and306in this embodiment) to the node E does not occur and thus the size limit of the transistor306smaller than the transistor301is not required and accordingly the driving capability of the transistor306is enhanced. This is shown in T4interval.

In T3interval, the pre-charge signal PRE changes from low potential to high potential, which represents that the pre-charge on the node E to a high potential is complete. Next, in T4interval, the control signal RWL changes from low potential to high potential and the NMOS transistor MR is turned on, which represents that data of the memory cell251starts sending to the output device200.

When data stored in the memory cell251is at high potential (not shown), the node F is at low potential, the transistors MR,305and307are turned on, and the-transistors MP,301,302,304and306are turned off. At this point, the node E retains high potential precharged, and the node G retains low potential through the grounding path provided by turning on the NMOS transistor304due to the enable signal EN with high potential in T1interval. Finally, the node G with low potential is changed by the inverter204such that the node OUT outputs a high potential.

Conversely, when data stored in the memory cell251is low potential (i.e., the node E from high potential to low potential inFIG. 5), the node F is high potential, and the transistors MR, MP are turned on. Because the enable signal EN changes from high potential to low potential as T1interval changes to T2interval, the grounding path I1consisting of the transistors303and304are disconnected. Thus, the voltage on the node G cannot be maintained at low potential (at this point, the transistor302is turned on and starts providing the node G with high potential), which causes the PMOS transistor305turned on for providing the node E with high potential and thus the speed of changing from high potential to low potential on the node E is reduced. However, by contrast, the transistor302provides the node G with high potential such that the transistor306is turned on and further the NMOS transistor is turned on when combining the transistor306active and the precharge signal PRE with high potential. As cited, sizes of the transistors306and307cannot be limited by a size of the PMOS301and thus a configuration with higher driving force can be designed. Accordingly, a graph ofFIG. 5shows the voltage change on the node E in a curve change from curve (1) to curve (2), which illustrates that curve (2) has shorter switching time than curve (1) as comparing G and OUT voltage change under the node E active.

Finally, in an appropriate time such as T5interval, the enable signal EN is changed from low potential to high potential. If the node E is low potential, the NMOS transistor303is inactive and thus data transfer is not affected. On the other hand, if the node E goes to a high potential, the grounding path I1is provided to avoid floating the node G after a certain interval.

As cited, in T1interval, because the NMOS transistor is added in the voltage hold circuit, which has active time different from the precharger, and thus no interference occurs. Therefore, the precharger can precharge the node E to a high potential quickly. In T4interval, the NMOS transistor of the charge and discharge path circuit turns the grounding path off and the voltage hold circuit can be designed as large-size transistor driving to speed up the node E to a low potential and increase read speed of the memory cell.