High voltage integration for HKMG technology

The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first oxide component is disposed on a substrate within a medium voltage region. A first high-k dielectric component is disposed on the substrate within a low voltage region and a second high-k dielectric component disposed on the first oxide component within the medium voltage region. A first gate electrode separates from the substrate by the first high-k dielectric component. A second gate electrode separates from the substrate by the first oxide component and the second high-k dielectric component.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth over the last few decades. In the course of IC evolution, high voltage technology has been widely used in power management, regulator, battery protector, DC motor, automotive relative, panel display driver (STN, TFT, OLED, etc.), color display driver, power supply relative, telecom, etc. On the other hand, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. One advancement implemented as technology nodes shrink, in some IC designs, has been the replacement of the polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Semiconductor devices of the replacement gate technology which supports a logic core to accomplish an intended function are integrated on the same chip with the logic core. This integration reduces undesired communication loss between the semiconductor devices and the supported logic core. However, there are challenges to embed high voltage devices to replacement gate technology, also known as high-k metal gate (HKMG) technology, especially on 28 nm node and beyond process.

DETAILED DESCRIPTION

High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. HKMG technology incorporates a high-k dielectric to increase transistor capacitance and reduce gate leakage. A metal gate electrode is used to help with Fermi-level pinning and to allow the gate to be adjusted to low threshold voltages. By combining the metal gate electrode and the high-k dielectric, HKMG technology makes further scaling possible and allows integrated chips to function with reduced power. HKMG technology can be used for memory devices, display devices, sensor devices, among other applications where a high voltage region is incorporated in the integrated circuits to provide higher power and have higher breakdown voltage than conventional MOS devices. Factors associated with fabrication such integrated circuits may include integrating fabrication of devices with varies dimensions, such as different gate dielectric thicknesses, channel lengths, and/or channel widths of devices with different operating voltages. Also, since planarization processes are needed when fabricating the integrated circuits (planarizing metals, interlayer dielectrics for example), dishing effects (especially to the high voltage devices with large device area) may limit channel dimensions of the high voltage device.

The present disclosure relates to an integrated circuit (IC) that comprises a low voltage region, a medium voltage region, and a high voltage region integrated in a substrate, and a method of formation the integrated circuit. In some embodiments, referring toFIG. 1for example, an integrated circuit100comprises a low voltage region102, a medium voltage region103, and a high voltage region104respectively having a first transistor gate stack112, a second transistor gate stack113, and a third transistor gate stack114. In some embodiments, a first gate electrode122in the low voltage region102may be a metal gate formed by a metal gate replacement process, and a first gate dielectric132may comprise a high-k dielectric layer. A second gate electrode123in the medium voltage region103may comprise polysilicon. A second gate dielectric133may be thicker than the first gate dielectric132and comprise a high-k dielectric layer and an additional oxide layer. Further, a third metal line128cof a metal layer of an interconnect structure may be used as a third gate electrode124within the high voltage region. A corresponding third gate dielectric134may comprise a high-k dielectric layer110c, an oxide component108b, and an interlayer dielectric layer116. By applying fabrication processes disclosed below with replacement gate technology, forming varies gate electrodes (e.g. the first gate electrode122of metal, the second gate electrode123of polysilicon, and/or the third gate electrode124of a metal line of an interconnect structure), and forming varies gate dielectrics (e.g. the first gate dielectric132, the second gate dielectric133, and/or the third gate dielectric134) having different heights and compositions, device performance is improved and manufacturing process is simplified, such that further scaling becomes possible in emerging technology nodes.

As shown inFIG. 1, an integrated circuit100is disposed over a substrate106and includes a low voltage region102, a medium voltage region103, and a high voltage region104. A first transistor gate stack112is disposed within the low voltage region102. The first transistor gate stack112is configured to operate at a first operation voltage. Example first operation voltages can be 1V, 1.5V, or 2.5V or other voltages smaller than around 3V. The first transistor gate stack112comprises a first gate electrode122, and a first gate dielectric132separating the first gate electrode122from the substrate106. A barrier layer118may be disposed between the first gate electrode122and a first high-k dielectric component110a. The barrier layer118may comprise metal or metal alloy material such as Ti or TiN. In some embodiments, the first gate electrode122may be made of metal or metal alloy material. The first gate dielectric132comprises a first high-k dielectric component110a. The first high-k dielectric component110amay contact an upper surface of the substrate106. The first gate electrode122may be coupled to a first metal line128athrough a first contacting via120a.

A second transistor gate stack113is disposed within the medium voltage region103. The second transistor gate stack113is configured to operate at a second operation voltage greater than the first operation voltage of the first transistor gate stack112. Example second operation voltages can be 6V, 8V, 12V or other voltages greater than around 3V but smaller than around 20V. The second transistor gate stack113comprises a second gate electrode123and a second gate dielectric133separating the second gate electrode123from the substrate106. In some embodiments, the second gate electrode123may be made of polysilicon material. The second gate dielectric133comprises a second high-k dielectric component110band a first oxide component108a. The first oxide component108amay contact the upper surfaces of the substrate106. With the first oxide component108ain place, the second gate dielectric133can have a thickness greater than that of the first gate dielectric132. Such that the breakdown voltage of the second transistor gate stack113is greater than the first transistor gate stack. In some embodiments, the thickness of the second gate dielectric133is about 2 to 10 times of a thickness of the first gate dielectric132. For example, the first gate dielectric132can have a thickness in a range of from about 30 angstroms (Å) to about 100 ∈, while the second gate dielectric133can have a thickness in a range of from about 150 ∈ to about 400 ∈. As can be appreciated, theses dimensions and other dimensions discussed herein can be scaled for different process nodes. In some embodiments, the first oxide component108amay contact an upper surface of the substrate106. The second high-k dielectric component110bmay be disposed directly onto the first oxide component108a. The barrier layer118may be disposed between the second gate electrode123and the second high-k dielectric component110b. In some embodiments, a silicide layer130may be disposed on a top surface of the second gate electrode123. The second gate electrode123may be coupled to a second metal line128bthrough a second contacting via120b. In some embodiments, the first contacting via120aand the second contacting via120bare surrounded by a first interlayer dielectric layer116. The first interlayer dielectric layer116extends across the low voltage region102and the medium voltage region103over the first gate electrode122and the second gate electrode123. In some embodiments, the first interlayer dielectric layer116may comprise a low-k dielectric layer, an ultra-low-k dielectric layer, an extreme low-k dielectric layer, and/or a silicon dioxide layer. A top surface of the first gate electrode122is positioned higher relative to an upper surface of the substrate106than a top surface of the second gate electrode123. The first gate electrode122has a first thickness greater than a second thickness of the second gate electrode123. The first contacting via120ahas a vertical height greater than that of the second contacting via120b. The first metal line128aand the second metal line128bare located within a first metal layer (for example, metal layer M1of an interconnect structure) and surrounded by a second interlayer dielectric layer126.

A third transistor gate stack114disposed within the high voltage region104. The third transistor gate stack114is configured to operate at a third operation voltage greater than the second operation voltage of the second transistor gate stack113. Example third operation voltage can be 25V, 32V or even higher voltages. The third transistor gate stack114comprises a third gate electrode124and a third gate dielectric134that separates the third gate electrode124from the substrate106. The third gate dielectric134comprises a second oxide component108b, a third high-k dielectric component110c, and the first interlayer dielectric layer116. The second oxide component108bmay contact the upper surfaces of the substrate106. With the first interlayer dielectric layer116functioned as a part of the third gate dielectric134, the third gate dielectric134can have a thickness greater than that of the second gate dielectric layer133. Such that the breakdown voltage of the third transistor gate stack114is further increased. In some embodiments, the thickness of the third gate dielectric134is about 5 to 10 times of a thickness of the second gate dielectric133. For example, the second gate dielectric133can have a thickness in a range of from about 150 angstroms (Å) to about 300 Å, while the third gate dielectric133can have a thickness in a range of from about 1000 Å to about 1500 Å. In some embodiments, a third metal line128ccan be used as the third gate electrode124. The third metal line128cmay also be disposed within the first metal layer of the first metal line128aand the second metal line128b.

As will be described in details below, in some embodiments, the first, second and third high-k dielectric components110a,110b,110cmay be made from a same type of high-k dielectric layer (e.g. the second gate dielectric layer502shown inFIG. 5), such that the first, second and third high-k dielectric components110a,110b,110chave substantially the same composition and thickness. The first and second oxide components108a,108bmay be made from a same oxide layer (e.g. the first gate dielectric layer302shown inFIG. 3), such that the first and second oxide components108a,108bhave substantially the same composition and thickness. The oxide layer may be formed directly on the upper surface of the substrate106and the first and second oxide components108a,108bhave top surfaces substantially aligned.

FIG. 2illustrates a cross-sectional view of some additional embodiments of an integrated circuit comprising a low voltage region, a medium voltage region, and a high voltage region integrated in a substrate. As shown inFIG. 2, an integrated circuit200is disposed over a substrate106and includes a low voltage region102, a medium voltage region103, and a high voltage region104. A first oxide component108ais disposed on the substrate106within the medium voltage region103, and a second oxide component108bis disposed on the substrate106within the high voltage region104. A first high-k dielectric component110ais disposed on the substrate106within the low voltage region102, and a second high-k dielectric component110bis disposed on the first oxide component108awithin the medium voltage region103, and a third high-k dielectric component110cis disposed on the second oxide component108bwithin the high voltage region104. A first gate electrode122is disposed within the low voltage region102, separate from the substrate106by the first high-k dielectric component110a. A second gate electrode123is disposed within the medium voltage region103, separating from the substrate106by the first oxide component108aand the second high-k dielectric component110b. A first interlayer dielectric layer116is disposed over the first gate electrode122and the second gate electrode123and the third high-k dielectric component110cextending across the low voltage region102, the medium voltage region103, and the high voltage region104. A first metal layer128is disposed over the first interlayer dielectric layer116and surrounded by a second interlayer dielectric layer126. The first metal layer128comprises a first metal line128aelectrically coupled to the first gate electrode122, a second metal line128belectrically coupled to the second gate electrode123, and a third metal line128cdisposed overlying the third high-k dielectric component110c. The third metal line128cis configured as a third gate electrode124separating from the substrate106by the second oxide component108b, the third high-k dielectric component110c, and the first interlayer dielectric layer116. A first vertical distance from a top surface of the first gate electrode122to an upper surface of the substrate106is greater than a second vertical distance from a top surface of the second gate electrode123to the upper surface of the substrate106, such that a first contacting via120athat couples the first gate electrode122and the first metal line128ahas a vertical height greater than that of a second contacting via120bthat couples the second gate electrode123and the second metal line128b.

Thus, the low voltage region102comprises a first transistor gate stack112configured to operate at a first operation voltage and having the first gate electrode122disposed over a first gate dielectric layer132. The first gate dielectric132comprises the first high-k dielectric component110a. The first transistor gate stack112can be part of an NMOS transistor or a PMOS transistor, or a fin-type field effect transistor (FinFET). The first gate electrode122can be a metal gate electrode having different metal compositions for NMOS transistor and PMOS transistor. By making use of HKMG structure in transistors of the low voltage region102, transistor capacitance (and thereby drive current) is increased and gate leakage and threshold voltage are reduced. In some embodiments, the first gate electrode122comprises a core metal layer separated from the first high-k dielectric component110aby a barrier layer118. The barrier layer118protects the core metal layer from diffusing into surrounding materials. In some embodiments, the core metal layer comprises copper (Cu), tungsten (W) or aluminum (Al), or their alloys, for example; and the barrier layer can comprise metal materials such as titanium (Ti), tantalum (Ta), zirconium (Zr), or their alloys, for example. In some embodiments, the first high-k dielectric component110acomprises hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HMO), for example. Though not shown inFIG. 2, in some embodiments, the low voltage region102may comprise memory devices. The medium voltage region103comprises a second transistor gate stack113configured to operate at a second operation voltage greater than the first operation voltage of the first transistor gate stack112. The second transistor gate stack113comprises the second gate electrode123and a second gate dielectric133separating the second gate electrode123from the substrate106. The second gate electrode123may be made of polysilicon material. The second gate dielectric133comprises the second high-k dielectric component110band the first oxide component108a. The high voltage region104comprises a third transistor gate stack114configured to operate at a third operation voltage greater than the second operation voltage of the second transistor gate stack113. The third transistor gate stack114can be a driver transistor, a power transistor, among applications. The third transistor gate stack114can be an LDMOS (laterally diffused metal oxide semiconductor) transistor designed for high blocking voltage. The third transistor gate stack114comprises the third gate electrode124and a third gate dielectric134separating the third gate electrode124from the substrate106. The third gate dielectric134comprises the second oxide component108b, the third high-k dielectric component110c, and the first interlayer dielectric layer116. The first gate electrode122, the second gate electrode123, and the third gate electrode124are respectively disposed between source/drain regions144. The source/drain regions144may be asymmetrical. Isolation regions (such as a shallow trench isolation (STI) structure or a deep trench isolation (DTI) structure) are not shown but can be disposed under and aside from the gate electrodes within the substrate106. The third gate electrode124and the second gate electrode123may have a gate length and a gate width greater than that of the first gate electrode122. Notably, for simplification reason, some features described inFIG. 1are not repeatedly described forFIG. 2but could be incorporated and applied toFIG. 2. For example, the first, second and third high-k dielectric components110a,110b,110cinFIG. 2may also be made from one high-k dielectric layer (e.g. the second gate dielectric layer502shown inFIG. 5). The first and second oxide components108a,108binFIG. 2may also be made from a same oxide layer (e.g. the first gate dielectric layer302shown inFIG. 3).

In some embodiments, a sidewall spacer140can be disposed along sidewalls of the first gate electrodes122and the first gate dielectric132within the low voltage region102, the second gate electrode123and the second gate dielectric133within the medium voltage region103, and the second oxide component108band the third high-k dielectric component110cwithin the high voltage region104. In some embodiments, the sidewall spacer140may comprise one or more layers of oxide or nitride. A third interlayer dielectric layer136comprises portions136a,136b,136crespectively surrounds the sidewall spacer140within the low voltage region102, the medium voltage region103, and the high voltage region104. A contact etch stop layer142may separate the third interlayer dielectric layer136from the sidewall spacer140. The contact etch stop layer142may comprise a planar lateral component connecting a first vertical component abutting the sidewall spacer140arranged along a side of the structures within the medium voltage region103and a second vertical component abutting the sidewall spacer140arranged along a side of the structures within the low voltage region102or the high voltage region104. Using the third interlayer dielectric layer136and the contact etch stop layer142to isolate the devices and structures allows for high device density to be achieved. In some embodiments, a hard mask138can be disposed on the first gate electrode122and contact top surfaces of the sidewall spacer140and the contact etch stop layer142. The third interlayer dielectric layer136may comprise an upper surface aligned with those of the sidewall spacer140and/or the contact etch stop layer142. One or more of the plurality of contacts may extend through the first interlayer dielectric layer116, the third interlayer dielectric layer136and the hard mask138within the low voltage region and be coupled to the source/drain regions144. In some embodiments, the plurality of contacts may comprise a metal such as tungsten, copper, and/or aluminum.

FIGS. 3-15illustrate a series of cross-sectional views300-1500of some embodiments of a method for manufacturing an IC comprising a low voltage region, a medium voltage region, and a high voltage region integrated in a substrate.

As shown in cross-sectional view300ofFIG. 3, a substrate106having a low voltage region102, a medium voltage region103, and a high voltage region104defined thereon is provided. In various embodiments, the substrate106may comprise any type of semiconductor body (e.g., silicon bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. A first gate dielectric layer302is formed on the substrate106. The first gate dielectric layer302can be an oxide layer, such as a silicon dioxide layer, but other suitable gate dielectric material is also applicable. The first gate dielectric layer302may be formed by a thermal process, for example, by forming a silicon dioxide layer on a silicon substrate at high temperatures from 800° C.-1100° C. using a dry thermal growth method. The thickness of the first gate dielectric layer302depends on applications, ranging from about several or tens of nanometers (nm) for current nodes to several angstroms (Å) for emerging nodes.

As shown in cross-sectional view400ofFIG. 4, the first gate dielectric layer302is patterned and selectively removed from the low voltage region102(while being kept within the medium voltage region103and the high voltage region104). A lithography process is performed having a photomask402applied to pattern a photoresist layer (not shown in the figure) over the first gate dielectric layer302ofFIG. 3. The photoresist layer comprises openings corresponding to the low voltage region102to expose the first gate dielectric layer302within the low voltage region102and to protect the first gate dielectric layer302within the medium voltage region103and the high voltage region104from a series of etching processes. In various embodiments, the etching processes may comprise a wet etch or a dry etch (e.g., a plasma etch with tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), etc.). The mask layer402will be substantially removed after the etching processes.

As shown in cross-sectional view500ofFIG. 5, a second gate dielectric layer502is formed on the substrate106within the low voltage region102, and on the first gate dielectric layer302within the medium voltage region103and the high voltage region104. A barrier layer504, a first polysilicon layer506, and a hard mask layer508are subsequently formed over the second gate dielectric layer502. In some embodiments, the second gate dielectric layer may comprise a high-k dielectric layer having a dielectric constant greater than that of silicon dioxide, such as hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HMO), for example. The barrier layer504may comprise metal or metal alloy material such as Ti or TiN. The hard mask layer508may comprise silicon dioxide and/or silicon nitride. In some embodiments, the second gate dielectric layer502, the barrier layer504, the first polysilicon layer506, and the hard mask layer508can be formed by using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.).

As shown in cross-sectional view600ofFIG. 6, the hard mask layer508is patterned to be removed from the low voltage region102to expose an upper surface of the first polysilicon layer506within the low voltage region102, and to be kept within the medium voltage region103and the high voltage region104. Similar to the patterning process described above, lithography process is performed having a photomask602applied to pattern a photoresist layer (not shown in the figure) having openings corresponding to the low voltage region102to expose the first polysilicon layer506within the low voltage region102and to protect the hard mask layer508within the medium voltage region103and the high voltage region104from a series of etching processes.

As shown in cross-sectional view700ofFIG. 7, a second polysilicon layer702is formed on the first polysilicon layer506within the low voltage region102and on the hard mask layer508within the medium voltage region103and the high voltage region104. Then the second polysilicon layer702is then removed from the medium voltage region103and the high voltage region104(e.g., by a planarization process). In some embodiments, the second polysilicon layer702is formed by using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). As a processing result, the second polysilicon layer702can have a top surface aligned with a top surface of the hard mask layer508.

As shown in cross-sectional view800ofFIG. 8, a first dielectric layer802and a second dielectric layer804are formed over the second polysilicon layer702and the hard mask layer508. The first dielectric layer802and the second dielectric layer804are then patterned (not shown in the figure) and collectively function as a hard mask for the subsequent gate stack patterning processes. In some embodiments, the first dielectric layer802may comprise silicon dioxide and the second dielectric layer804may comprise silicon nitride. The first dielectric layer802is thinner than the second dielectric layer804. For example, the first dielectric layer802can be 1/10 of the collective thickness of the first dielectric layer802and the second dielectric layer804.

As shown in cross-sectional view900ofFIG. 9, according to the patterned second dielectric layer804and first dielectric layer802, the second polysilicon layer702, the hard mask layer508, the first polysilicon layer506, the barrier layer504, the second gate dielectric layer502, and the first gate dielectric layer302are patterned and etched to form a first gate stack902within the low voltage region102, a second gate stack903within the medium voltage region103, and a third gate stack904within the high voltage region104. As an example, the first gate stack902may comprise portions of the second polysilicon layer702, the first polysilicon layer506, the barrier layer504and the second gate dielectric layer502. The second gate stack903may comprise portions of the hard mask layer508, the first polysilicon layer506, the barrier layer504, the second gate dielectric layer502, and the first gate dielectric layer302. The third gate stack904may comprise the same composite as the second gate stack903. Outer sidewalls of the corresponding portions the first gate stack902, the second gate stack903, and the third gate stack904can be respectively aligned one another.

As shown in cross-sectional view1000ofFIG. 10, a sidewall spacer140can be formed along sidewalls of the first gate stack902, the second gate stack903, and the third gate stack904. The sidewall spacer140may comprise one or more layers of oxide or nitride. Source/drain regions144are formed between opposing sides of the first gate stack902, the second gate stack903, and the third gate stack904within the substrate106. In some embodiments, the source/drain regions144may be formed by an implantation process that selectively implants the substrate106with a dopant, such as boron (B) or phosphorous (P), for example. In some other embodiments, the source/drain regions may be formed by performing an etch process to form a trench followed by an epitaxial growth process. In such embodiments, the source/drain regions144may have a raised portion that is higher than the upper surface of the substrate106. In some embodiments, a salicidation process is performed to form a silicide layer (not shown in the figure) on upper surfaces of the source/drain regions144. In some embodiments, the salicidation process may be performed by depositing a nickel layer and then performing a thermal annealing process (e.g., a rapid thermal anneal).

As shown in cross-sectional view1100ofFIG. 11, a contact etch stop layer142may be then subsequently formed lining sidewalls of the sidewall spacer140. The contact etch stop layer may comprise silicon nitride formed by way of a deposition process (e.g., CVD, PVD, etc.). A third interlayer dielectric layer136is then formed between and over the contact etch stop layer142. The contact etch stop layer142and the third interlayer dielectric layer136may be formed by way of deposition processes (e.g., CVD, PVD, etc.). After the deposition processes, the contact etch stop layer142and the third interlayer dielectric layer136are subject to etching processes (including but not limiting to a planarization process), so as to be removed from the top of the first gate stack902, the second gate stack903, and the third gate stack904, such that top surfaces of the second polysilicon layer702and the hard mask layer508are exposed and aligned with those of the sidewall spacer140, the contact etch stop layer142, and/or the third interlayer dielectric layer136.

As shown in cross-sectional view1200ofFIG. 12, the second polysilicon layer702and the first polysilicon layer506within the low voltage region102is removed, resulting in the formation of trenches between the sidewall spacers140. Metal gate materials are then filled into the trenches to form a first gate electrode122. The first gate electrode122is formed through one or more deposition processes (e.g., chemical vapor deposition, physical vapor deposition, etc.). The first gate electrode122may comprise core metal materials such as titanium (Ti), tantalum (Ta), zirconium (Zr), or their alloys, for example. A series of deposition and etching processes can be performed that form different metal compositions within the trenches for different devices or different components of the same devices, to achieve desired work functions.

As shown in cross-sectional view1300ofFIG. 13, a hard mask layer1302is formed over the first gate stack902, the second gate stack903, the third gate stack904, and the third interlayer dielectric layer136. The hard mask layer1302is then patterned to leave an opening1304at the medium voltage region103and to expose the first polysilicon layer506. A second portion136bof the third interlayer dielectric layer136is also etched such that a top surface is aligned with the first polysilicon layer506, and/or the sidewall spacer140and the contact etch stop layer142within the medium voltage region103. In some embodiments, a salicidation process is performed to form a silicide layer on upper surfaces of the first polysilicon layer506. In some other embodiments, the first polysilicon layer506is fully silicide to achieve sufficient conductivity. As a result, a second gate electrode123is formed.

As shown in cross-sectional view1400ofFIG. 14, a portion of the hard mask layer1302within the high voltage region104(shown inFIG. 13) is removed. A masking layer1402is formed and patterned to cover the low voltage region102and the medium voltage region103. The high voltage region104is exposed and subsequently etched to form a third portion136cof the third interlayer dielectric layer136having a top surface aligned with the second gate dielectric layer502, and/or the sidewall spacer140and the contact etch stop layer142within the high voltage region104.

As shown in cross-sectional view1500ofFIG. 15, a first interlayer dielectric layer116is formed over the first gate electrode122and the second gate electrode123and the second gate dielectric layer502extending across the low voltage region102, the medium voltage region103, and the high voltage region104. A first metal layer128is disposed over the first interlayer dielectric layer116and surrounded by a second interlayer dielectric layer126. The first metal layer128comprises a first metal line128aelectrically coupled to the first gate electrode122, a second metal line128belectrically coupled to the second gate electrode123, and a third metal line128cdisposed overlying the second gate dielectric layer502. The third metal line128cis configured as a third gate electrode124separating from the substrate106by the first gate dielectric layer302, the second gate dielectric layer502, and the first interlayer dielectric layer116. A first contacting via120ais formed to couple the first gate electrode122and the first metal line128a. A second contacting via120bis formed to couple the second gate electrode123and the second metal line128b. Other contacts or contacting vias can also be formed through the first interlayer dielectric layer116and/or the third interlayer dielectric layer136. The contacts may be formed by selectively etching the interlayer dielectric layers to form openings (e.g. with a patterned photoresist mask in place), and by subsequently depositing a conductive material within the openings. In some embodiments, the conductive material may comprise tungsten (W) or titanium nitride (TiN), for example.

FIG. 16illustrates a flow diagram of some embodiments of a method1600for manufacturing an IC comprising a low voltage region, a medium voltage region, and a high voltage region integrated in a substrate.

At1602, a substrate is provided including a low voltage region, a medium voltage region, and a high voltage region. A dielectric layer is formed on the substrate. The dielectric layer is then patterned to be removed from the low voltage region and be kept within the medium voltage region and the high voltage region to form a first gate dielectric layer.FIGS. 3-4illustrate some embodiments of cross-sectional views300,400corresponding to act1602.

At1604, a second gate dielectric layer and a first polysilicon layer are subsequently formed. The second gate dielectric layer may be a high-k dielectric layer. A barrier layer and a hard mask layer may also be formed. The second gate dielectric layer and the first polysilicon layer may be formed by deposition.FIG. 5illustrates some embodiments of a cross-sectional view500corresponding to act1604.

At1606, the hard mask layer is patterned to be removed from the low voltage region to expose an upper surface of the first polysilicon layer, and to be kept within the medium voltage region and the high voltage region.FIG. 6illustrates some embodiments of a cross-sectional view600corresponding to act1606.

At1608, a second polysilicon layer is formed on the first polysilicon layer within the low voltage region and on the hard mask layer within the medium voltage region and the high voltage region. The second polysilicon layer within the low voltage region and the hard mask layer within the medium voltage region and the high voltage region can have top surfaces aligned.FIG. 7illustrates some embodiments of a cross-sectional view700corresponding to act1608.

At1610, a hard mask is formed and patterned over the second polysilicon layer and the hard mask layer. In some embodiments, the hard mask can be formed by more than one dielectric layers, such as a composition of silicon dioxide and silicon nitride.FIG. 8illustrates some embodiments of a cross-sectional view800corresponding to act1610.

At1612, the second polysilicon layer, the hard mask layer, the first polysilicon layer, the barrier layer, the second gate dielectric layer, and the first gate dielectric layer are patterned and etched to form a first gate stack within the low voltage region, a second gate stack within the medium voltage region, and a third gate stack within the high voltage region.FIG. 9illustrates some embodiments of a cross-sectional view900corresponding to act1612.

At1614, a sidewall spacer is formed along sidewalls of the first gate stack, the second gate stack, and the third gate stack. A contact etch stop layer is formed lining sidewalls of the sidewall spacer.FIGS. 10-11illustrate some embodiments of cross-sectional views1000,1100corresponding to act1614.

At1616, a replacement gate process is subsequently performed by forming metal materials within the formed trenches. The second polysilicon layer and the first polysilicon layer are removed from the low voltage region, resulting in the formation of trenches between the sidewall spacers. Metal gate materials are then filled into the trenches to form a first gate electrode.FIG. 12illustrates some embodiments of a cross-sectional view1200corresponding to act1616.

At1618, a second gate electrode is formed within the medium voltage region. A hard mask layer is formed and patterned to leave an opening at the medium voltage region. An etch is performed to expose the first polysilicon layer. A second portion of the third interlayer dielectric layer is also etched such that a top surface is aligned with the first polysilicon layer, and/or the sidewall spacer and the contact etch stop layer within the medium voltage region. The first polysilicon layer is processed to form the second gate electrode within the medium voltage region.FIG. 13illustrates some embodiments of a cross-sectional view1300corresponding to act1618.

At1620, a third gate electrode is formed within the high voltage region. A portion of the hard mask layer within the high voltage region is removed. A masking layer is formed and patterned to cover the low voltage region and the medium voltage region. The high voltage region is exposed and subsequently etched to form a third portion of the third interlayer dielectric layer having a top surface aligned with the second gate dielectric layer, and/or the sidewall spacer and the contact etch stop layer within the high voltage region. A first interlayer dielectric layer is formed over the first gate electrode and the second electrode and the high-k dielectric layer extending across the low voltage region, the medium voltage region, and the high voltage region. A first metal layer is disposed over the first interlayer dielectric layer116and surrounded by a second interlayer dielectric layer. The first metal layer comprises a first metal line electrically coupled to the first gate electrode, a second metal line electrically coupled to the second gate electrode, and a third metal line disposed overlying the high-k dielectric layer. The third metal line is configured as the third gate electrode separating from the substrate by the first gate dielectric layer, the second gate dielectric layer, and the first interlayer dielectric layer. A first contacting via is formed to couple the first gate electrode and the first metal line. A second contacting via is formed to couple the second gate electrode and the second metal line. Other contacts or contacting vias can also be formed through the first interlayer dielectric layer and/or the third interlayer dielectric layer.FIGS. 14-15illustrate some embodiments of cross-sectional views1400,1500corresponding to act1620.

Therefore, the present disclosure relates to an integrated circuit (IC) that a boundary structure of a low voltage region, a medium voltage region, and a high voltage region integrated in a substrate, and a method of formation and that provides small scale and high performance, and a method of formation.

In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit comprises a first transistor gate stack disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. The first gate dielectric comprises a first high-k dielectric component. The integrated circuit comprises a second transistor gate stack disposed in a medium voltage region defined on the substrate. The second transistor gate stack comprises a second gate electrode and a second gate dielectric separating the second gate electrode from the substrate. The second gate dielectric comprises a second high-k dielectric component and a first oxide component. The integrated circuit further comprises a third transistor gate stack disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises a third high-k dielectric component, a second oxide component, and a first interlayer dielectric layer.

In other embodiments, the present disclosure relates to a method of forming an integrated circuit. The method comprises providing a substrate having a low voltage region, a medium voltage region, and a high voltage region defined on the substrate and forming and patterning an oxide layer on the substrate within the medium voltage region and the high voltage region. The method further comprises forming a high-k dielectric layer over the substrate within the low voltage region and over the oxide layer within the medium voltage region and the high voltage region and forming a first polysilicon layer over the high-k dielectric layer. The method further comprises forming and patterning a hard mask layer to cover the first polysilicon layer within the low voltage region and the medium voltage region and forming and patterning a second polysilicon layer directly on the first polysilicon layer within the low voltage region. The hard mask layer and the second polysilicon layer are formed having aligned top surfaces.

In yet other embodiments, the present disclosure relates to a method of forming an integrated circuit. The method comprises providing a substrate comprising a low voltage region, a medium voltage region and a high voltage region defined on the substrate and forming and patterning an oxide layer on the substrate within the medium voltage region and the high voltage region. The method further comprises forming a high-k dielectric layer over the substrate within the low voltage region and over the oxide layer within the medium voltage region and the high voltage region and forming a first polysilicon layer over the high-k dielectric layer. The method further comprises forming and patterning a second polysilicon layer directly on the first polysilicon layer within the low voltage region and forming and patterning a first hard mask over the first polysilicon layer within the low voltage region and a second hard mask over the first polysilicon layer within the medium voltage region. The method further comprises replacing the first polysilicon layer and the second polysilicon layer within the low voltage region by a metal material to form a first gate electrode.