A voltage-controlled oscillator is implemented with a succession of delay cells coupled in series to form an oscillator loop. The oscillator loop is supplied with reference voltages produced by a voltage generator. The reference voltages produce stable operation of the voltage-controlled oscillator. Cascode reference current generators are incorporated within the voltage generator to supply a cross-coupled arrangement of pull-up devices within each delay cell. The cross-coupled pull-up devices are instrumental in producing complementary output signaling from each delay cell. A pair of cascode current generators is configured in parallel to produce a magnitude of current according to an applied voltage and to be selectable for dual or single operation with a corresponding frequency determination.

BACKGROUND

The present invention relates to integrated circuits in general and, in particular, to optimized delay cells for voltage-controlled oscillators.

A voltage-controlled oscillator (VCO) is a key component in a typical phase-lock loop, or PLL. Along with a phase-frequency detector, a charge pump, and a loop filter, a VCO is capable of generating a clock whose frequency and phase have a well-defined (deterministic) relationship to the frequency and phase of a reference clock. As a set, they form the PLL. PLLs are used in various applications such as clock synthesis, clock distribution, signal de-skewing, and as filters in reducing jitter within other applications. VCOs therefore, are a commonly occurring circuit element in clock circuitry.

BRIEF SUMMARY

Among other advantages and features, the VCO, according to an embodiment of the invention, provides a number of differential delay cells and a configurable voltage generator. The voltage generator provides a number of reference voltage levels which are provided to the delay cells. The delay cells form an oscillator loop. With the reference voltage levels supplied from the voltage generator, stable operation of the voltage-controlled oscillator is produced. The number of differential delay cells is coupled in series and to the voltage generator. Each of the differential delay cells includes a first and second pull-up device cross coupled to one another and are further coupled to a plurality of current sources. The number of current sources is each supplied with one of the number of reference voltage levels and is configured to produce a reference magnitude of current. The cross coupled pull-up devices are instrumental in providing complementary output signaling from each delay cell. A pair of cascode current generators is configured in parallel and produces a magnitude current according to an applied reference voltage level from the voltage generator.

DETAILED DESCRIPTION

Among other things, systems and methods are described for providing voltage-controlled oscillator (VCO) functionality having a number of differential delay cells and a configurable voltage generator. The VCO functionality may be implemented, along with a phase-frequency detector, a charge pump, and a loop filter, as a phase-lock loop (PLL) capable of generating a clock whose frequency and phase have a well-defined (e.g., deterministic) relationship to the frequency and phase of a reference clock. Embodiments described herein provide support for wide ranges of frequencies and current levels.

A central component of VCO functionality (e.g., for use in a PLL) is the provision of delay. For example, multiple delay cells may be used in a ring oscillator configuration to provide VCO functionality. In some embodiments, each delay cell receives an input signal (e.g., an output from an adjacent delay cell) and generates a phase-shifted output signal. An embodiment of a delay cell for providing VCO functionality is shown inFIGS. 1-3.

FIG. 1shows a simplified block diagram of a delay cell100for use in providing VCO functionality, according to various embodiments of the invention. The delay cell100includes a current source110, two delay buffer blocks120, a clamping switch block130, and two output clamping blocks150. Some embodiments include two current density compensation blocks140.

The current source110is coupled between a source voltage, VDD106, and a TOP terminal115. Embodiments of the current source110are configured to provide a programmable, substantially constant current to flow through the TOP terminal115. The current source110is programmable by a current control input112. In some embodiments, the current control input112includes a bias voltage, and/or additional signals for controlling the amount of current sourced by the current source110.

Power to each delay buffer block120is tied to the TOP terminal115. In some embodiments, input signals102are received at inputs to each delay buffer block120. The delay buffer block120then generates an output signal104as a function of the input signal102. For example, a first input signal102ais received at an input of the first delay buffer block120a, which generates a first output signal104a; and a second input signal102b, the complement to the first input signal102a, is received at an input to the second delay buffer block120b, which generates a second output signal104b.

In some embodiments, each delay buffer block120includes a number of transistors and/or other components configured as an inverter, whereby its respective output signal104has an inverted relationship to the input signal102. In other embodiments, components of each delay buffer block120delay the input signal102(e.g., due to propagation delay of the delay buffer block120components), buffer the input signal102(e.g., to isolate the input signal from effects of other components of the delay cell100by providing high output impedance), and/or to assist with TOP clamping, as described below.

The output signal104coming from each delay buffer block120may be clamped by a respective output clamping block150. Each output clamping block150is coupled between the output signal104of its respective delay buffer block120and ground108(e.g., analog ground). The output signal104, and therefore one side of the output clamping block150, may be indirectly coupled with the TOP terminal115(e.g., through the clamping switch block130), such that the output clamping block150can assist with both output clamping and TOP clamping, as described below.

Embodiments of the clamping switch block130are coupled between the TOP terminal115and each output signal104. In some embodiments, the clamping switch block130includes transistors in a latch configuration. Typically, the second input signal102bis the complement of the first input signal102a, causing the second output104bto be the complement of the first output104a(e.g., to support use of the delay cell100in a ring oscillator configuration). The clamping switch block130may be configured to ensure this complementary relationship between the signals. For example, when the first output signal104agoes HIGH, the clamping switch block130may force the second output signal104bto pull LOW, and vice versa.

In certain embodiments, the clamping switch block130is further configured to assist with TOP clamping. It will be appreciated that a minimum voltage differential may be required between VDD106and the TOP terminal115to maintain desirable operation of the current source110. For example, it may be desirable to run the current source110in its saturated region (e.g., for optimized efficiency, noise characteristics, etc.). When the voltage at the TOP terminal115comes too close to VDD106, the current source110may not operate in saturation, potentially yielding sub-optimal or undesirable results. As the current being sourced by the current source110increases, the voltage at the TOP terminal115may be pulled toward VDD106. It may, therefore, be desirable to clamp the TOP terminal115to maintain a maximum voltage level sufficiently below VDD106over a desirably large range of output currents from the current source110. Components of the clamping switch block130, the delay buffer block120(e.g., PMOS transistors), and/or the output clamping block150may assist with clamping the TOP terminal115voltage level.

Some embodiments of the delay cell100include current density compensation blocks140. When using the delay cell100over large ranges of frequencies, it may be desirable to adapt the current source110output for optimized performance. For example, at high frequencies, increased current may allow for decreased phase noise and more optimal performance. However, changing the current through components of the delay cell100may also affect the delay provided by the delay cell100. As such, embodiments of the current density compensation blocks140compensate for changes in current density to limit the effect of changes in current on delay provided by the delay cell100. Typically, each current density compensation block140may be coupled between its respective output signal104and ground108.

It will be appreciated that many implementations of the functionality of the delay cell100inFIG. 1are possible, according to various embodiments. One exemplary implementation is shown inFIG. 2A.FIG. 2Ashows a simplified schematic diagram of an embodiment of a delay cell200, like the delay cell100shown inFIG. 1, according to various embodiments of the invention.

The delay cell200includes a first input102aand a second input102bcoupled to a first inverter205aand a second inverter205b, respectively. Embodiments of the inverters205may implement functionality of the delay buffer blocks120ofFIG. 1. Each inverter205is coupled to a core circuitry supply node, TOP node115. In some embodiments, full inverters (e.g., inverters using multiple transistors) are used to provide improved clamping of TOP node115, as described above.

Outputs of the first inverter205aand the second inverter205bcouple to outputs of a first pull-up PMOS transistor210aand a second pull-up PMOS transistor210b, respectively. The first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bare cross-coupled between a first output node104aand a second output node104b. Source nodes of the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bcouple to a core circuitry supply node, TOP node115. Control input nodes of the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bcouple to the second output node104band the first output node104a, respectively. In some embodiments, the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bimplement some or all of the functionality of the clamping switch block130ofFIG. 1.

The first output node104afurther couples to a first capacitor215aand a first diode220a. The second output node104bfurther couples to a second capacitor215band a second diode220b. In some embodiments, the first capacitor215aand the second capacitor215bimplement functionality of the first current density compensation block140aand the second current density compensation block140bofFIG. 1, respectively. Further, in some embodiments, the first diode220aand the second diode220bimplement functionality of the first output clamping block150aand the second output clamping block150bofFIG. 1, respectively. It will be appreciated that other components may be used to implement substantially the same functionality of the capacitors215and diodes220. For example, each functional component or block of components may be implemented using transistors (e.g., as shown below inFIG. 3).

A voltage reference node VDD106couples to inputs of a first current source225aand a second current source225b. Control inputs of the first current source225aand the second current source225bcouple to a bias-voltage node PBIAS204. Output nodes of the first current source225aand the second current source225bcouple to inputs of a first cascode switch235aand a second cascode switch235b, respectively. Control inputs of the first cascode switch235aand the second cascode switch235bcouple to a first supply-select node PCAS202aand a second supply-select node PCAS2202b, respectively. Outputs of the first cascode switch235aand the second cascode switch235bcouple to TOP node115.

In some embodiments, the first current source225a, the second current source225b, the first cascode switch235a, and/or the second cascode switch235bimplement functionality of the current source110ofFIG. 1. Further, in some embodiments, the bias-voltage node PBIAS204, the first supply-select node PCAS202a, and/or the second supply-select node PCAS2202bare used as the current control input112inFIG. 1. Further, in some embodiments, TOP node115is coupled to ground108by a filter capacitor230.

FIG. 2Bshows a VCO delay cell symbol250for use in schematic diagrams. The VCO delay cell symbol250portrays various inputs, outputs, and power connections, according to an exemplary embodiment of a delay cell, like the delay cell200ofFIG. 2A. Specifically, the VCO delay cell symbol250shows terminals corresponding to VDD106, PBIAS204, TOP node115, the first input signal102a, the second input signal102b, PCAS202a, PCAS2202b, ground108, the first output signal104a, and the second output signal104b.

It will be appreciated that many circuit components and topologies are possible for implementing the functionality of the delay cell200ofFIG. 2A. For example,FIG. 3shows transistor-based circuit implementation of an embodiment of a delay cell schematic300, according to an embodiment of the invention. In some embodiments, the delay cell schematic300is implemented within an integrated circuit packaged substantially according to the delay cell symbol250shown inFIG. 2B. It will be appreciated by those of skill in the art that the component blocks of the delay cell schematic300constitute an illustrative embodiment of the delay cell200ofFIG. 2A. As such,FIG. 3is labeled with reference numerals corresponding to corresponding functional components ofFIG. 2A.

Notably, the first pull-up device PM3A and the second pull-up device PM3B of the first inverter (INV_P)205aand the second inverter (INV_N)205b, respectively, may be relatively strong PMOS transistors, capable of providing a voltage limit for the TOP node115. This may help clamp the TOP node115, as discussed above. Clamping the TOP node115may ensure a minimum voltage across the first current source (PM0A)225aand across the second current source (PM0B)225b, ensuring the current sources maintain operation in a saturation region and making the respective supplied currents less sensitive to changes in the voltage at the TOP node115in relation to VDD106.

The first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bare cross-coupled transistors, which may serve at least two purposes. One purpose of the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bmay be to force the first output node104aand the second output node104bto transition in a complementary mode. Another purpose of the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bmay be to contribute to the clamping characteristics provided to the TOP node115. The larger the sizes of the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210b, the better the TOP node115may be clamped. In some embodiments, the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bimplement functionality of the clamping switch block130ofFIG. 2A.

The first capacitor (NM2A)215aand the second capacitor (NM2B)215bmay reduce phase noise by operating related circuit structures at higher current densities for a given VCO frequency. The first diode (NM1A)220aand the second diode (NM1B)220bmay provide additional clamping of the TOP node115. As explained above, clamping of the TOP node115may increase a supply noise rejection quotient by virtue of maintaining a lower voltage at the TOP node115, allowing the current sources225to operate at a larger voltage across them and producing high-output-impedance-current sources. As illustrated inFIG. 3, the capacitors215and/or the diodes220are implemented in certain embodiments using transistors. In one embodiment, each diode220is an NMOS transistor with a source node connected with ground108and a gate node and a drain node each connected with an output node104. In another embodiment, each diode220is a PMOS transistor with a source node connected with a reference supply voltage level and a gate node and a drain node each connected with an output node104.

A magnitude of transconductance of the first current source225aand the second current source225b, and corresponding output current value, may contribute to the determination of an operating frequency of the VCO. The first cascode switch235aand the second cascode switch235bform a cascode supply structure, which may create, in conjunction with the current sources225, a high-output-impedance current source, which may provide enhanced noise rejection. The filter capacitor230may strongly couple the TOP node115to ground108. The strong coupling may provide a more consistent core voltage (i.e., the voltage between the TOP node115and ground108) in the presence of substrate and power-supply noise, and may produce better noise rejection functionality.

It will be appreciated that embodiments of delay cells, such as those shown inFIGS. 1-3, may provide a number of features. Some embodiments provide current sources in a cascode configuration (e.g., as shown inFIGS. 2A and 3), which may provide high power-supply-noise immunity. Other embodiments provide an ability to selectively apply current from an alternate cascode current branch (e.g., using the first supply-select node PCAS202aand the second supply-select node PCAS2202bofFIG. 2A). Switching in the extra current branch increases current provided to a delay cell, which may enable operation at higher current densities, resulting in the VCO having lower phase noise. For a given current in the delay cell, this may allow operation at a higher PBIAS level (see element204ofFIG. 2A), which may maintain the high power-supply-noise rejection for situations with limited head-room voltage.

Other embodiments allow operation at high current levels with a resulting lower phase noise. Still other embodiments provide an ability to operate at high PBIAS voltages in cases of reduced voltage headroom and with fixed current requirements through each delay cell. Yet other embodiments provide a decoupling capacitor at the TOP voltage (e.g., filter capacitor230ofFIG. 2A) for greater substrate noise immunity and high power-supply-noise rejection. Other embodiments provide capacitors at delay cell outputs (e.g., capacitors215ofFIG. 2A) that may lower phase noise by providing more current when running at a given frequency. Still other embodiments provide clamping devices that limit the voltage level of TOP supply voltage and the delay cell output voltages resulting in higher power supply-noise rejection (e.g., components of the clamping switch block130, the delay buffer block120, and/or the output clamping block150ofFIG. 1). Yet other embodiments provide cross-coupled PMOS structure (e.g., the first pull-up PMOS transistor210aand the second pull-up PMOS transistor210bofFIGS. 2A and 3) that produce a complementary transition at the delay cell output and further reduces transition time of output signals.

Some embodiments provide a configurable voltage generator for controlling certain components of the delay cell. For example, it may be desirable to generate the current control input112signal(s) ofFIG. 1(e.g., the bias-voltage node PBIAS204, the first supply-select node PCAS202a, and/or the second supply-select node PCAS2202b) using a configurable voltage generator.FIG. 4shows a simplified schematic diagram of an embodiment of a configurable voltage generator400, according to various embodiments of the invention.

Embodiments of the configurable voltage generator400generate signals for use by a delay cell, like the delay cell200shown inFIG. 2A, including signals desired as the bias-voltage node PBIAS204, the first supply-select node PCAS202a, and/or the second supply-select node PCAS2202bof the delay cell200. The configurable voltage generator400includes a mirror pull-up device405aand a reference pull-down device405bthat are coupled in series at a first series-coupling node410and between a source voltage, VDD106and ground108. A first reference pull-up device415aand a pull-down-mirror device415bare coupled in series at a second series-coupling node420and between VDD106and ground108. The first series-coupling node410is coupled to a control input of the first pull-down-mirror device415b.

A second reference pull-up device425couples to VDD106and a current-control node402. For example, a current control device may couple to the current-control node402. The current-control node402couples to a control input of the mirror pull-up device405aand an input of a first resistor440a. An output node of the first resistor440acouples to a first noise-filter capacitor445aand a bias-output node204. Together, the first resistor440aand the first noise-filter capacitor445amay form a low-pass filter to reduce noise coupled to a ring oscillator coupled with the configurable voltage generator400through the bias-output node204. The first noise-filter capacitor445acouples between VDD106and the bias-output node204.

The second series-coupling node420couples to an input of a second resistor440b. An output node of the second resistor440bcouples to a second noise-filter capacitor445b, the first supply-select node202a, and a current-increase switch430. The second noise-filter capacitor445bcouples between VDD106and the first supply-select node202a. The current-increase switch430couples between the first supply-select node202aand the second supply-select node202b. A switch control input of the current-increase switch430couples to an increase-current node404. Together, the second resistor440band the second noise-filter capacitor445bmay form a low-pass filter to reduce noise coupled to a ring oscillator coupled with the configurable voltage generator400through the first supply-select node202aand the second supply-select node202b(through the current-increase switch430).

In some VCO embodiments, the configurable voltage generator400is in communication with at least one delay cell, like the delay cell200ofFIG. 2A, via the bias-output node204, the first supply-select node202a, and the second supply-select node202b. A voltage seen at the bias-output node204contributes to a magnitude of current available for coupling through the first cascode switch235aand/or the second cascode switch235b(e.g., as partially determined by switching the second supply-select node202busing the current-increase switch430). The clamping structure of the first diode220aand the second diode220bat a given frequency may determine the current available for coupling at the cascode switches235and may determine the operating voltage level at the TOP node115.

In certain embodiments, voltage levels seen by the configurable voltage generator400at the bias-output node204, the first supply-select node202a, and the second supply-select node202b, are dependent on current produced at the current control node402of the configurable voltage generator400. The current produced at the current control node402may determine an operating frequency of the VCO. Increasing the magnitude of the current produced at the current control node402may decrease the magnitude of the voltage level seen on the bias-output node204and, thus, increase the current flowing through the one or more connected delay cells200. Additionally, the voltage produced at the second supply-select node202bcan be switched on and off by applying an appropriate signal to the increase-current node404to switch the current-increase switch430. For example, voltage is enabled at the second supply-select node202bto reduce phase noise by providing higher current density through the delay cell(s)200. It will now be appreciated that using the configurable voltage generator400in combination with one or more delay cells200may implement a VCO with a frequency that is controlled at least in part by the current at the current control node402.

Different embodiments of VCO implementations are possible, using a configurable voltage generator400in communication with a series of delay cells, according to various embodiments of the invention. Particularly, embodiments of delay cells can be used in either even numbers or odd numbers, to form ring oscillator configurations for providing delay in support of the VCO functionality. For example, embodiments provide the functionality to maintain, for odd-numbered-delay-cell ring oscillators, an odd number of inverters in any given signal path that results in a solid oscillation structure.FIGS. 5A and 5Bshow simplified block diagrams of an odd-numbered-delay-cell ring oscillator500and an even-numbered-delay-cell ring oscillator555, respectively, according to various embodiments of the invention.

Turning first toFIG. 5A, an embodiment of an odd-numbered-delay-cell ring oscillator500is shown, having a configurable voltage generator in communication with three delay cells. Each delay cell is represented by a delay cell symbol250, as described with reference toFIG. 2Babove. The configurable voltage generator is represented by a configurable voltage generator symbol550. The configurable voltage generator symbol550portrays various inputs, outputs and power connections, according to an embodiment of a configurable voltage generator, like the configurable voltage generator400ofFIG. 4. Specifically, the configurable voltage generator symbol550includes terminals corresponding to the increase-current node404, the current-control node402, the bias-output node204, the first supply-select node202a, and the second supply-select node202bofFIG. 4.

As shown, a current control device505is in communication with the current control node402of the voltage generator symbol550, and has a voltage-control input node502. Using the current control device505, the current at the current control node402may be controlled by adjusting a voltage level applied to the voltage-control input node502. In one embodiment, the current control device505is a MOS transistor with a transconductance characteristic determined by a voltage on the voltage-control input node502. The voltage on the voltage-control input node502may be directly related to the current flowing through the second reference pull-up device (e.g., element225ofFIG. 2A), which may directly determine a voltage level on the bias-output node204. Also as shown, the increase-current node404is tied to VDD106. This may increase the current density of the delay cell symbols250by enabling the second supply-select node202b. It will be appreciated that other signals may be applied to the voltage-control input node502and/or the increase-current node404in different embodiments or applications, as desired.

The bias-output node204, the first supply-select node202a, and the second supply-select node202bare connected in parallel from the voltage generator symbol550to each of the delay cell symbols250. Further, the output nodes (O_P and O_N) of each delay cell symbol250are in communication with respective input nodes (I_P and I_N) of an adjacent delay cell symbol250. It will be appreciated that this configuration of the voltage generator symbol550in communication with the delay cell symbols250a,250b, and250cmay be used to implement a three-stage VCO.

For example, each of the three delay cell symbols250in the ring-oscillator configuration shifts the phase of its input signal by negative 120 degrees. As such, the three delay cell symbols250form two complementary rings, with oscillating phase sequence characteristics. Specifically, the first ring can be illustrated as beginning with a 0-degree-phase signal at the O_P output of the first delay cell symbol250aand the I_P input of the second delay cell symbol250b. The second delay cell symbol250bphase-shifts the signal, outputting a 240-degree-phase signal at the O_N output of the second delay cell symbol250band the I_N input of the third delay cell symbol250c. The third delay cell symbol250cphase-shifts the signal, outputting a 120-degree-phase signal at the O_P output of the third delay cell symbol250cand the I_N input of the first delay cell symbol250a. The first delay cell symbol250aphase-shifts the signal, outputting the same 0-degree-phase signal at the O_P output of the first delay cell symbol250aand the I_P input of the second delay cell symbol250bwith which the first ring began.

In a complementary fashion, the second ring can be illustrated as beginning with a 180-degree-phase signal at the O_N output of the first delay cell symbol250aand the I_N input of the second delay cell symbol250b. The second delay cell symbol250bphase-shifts the signal, outputting a 60-degree-phase signal at the O_P output of the second delay cell symbol250band the I_P input of the third delay cell symbol250c. The third delay cell symbol250cphase-shifts the signal, outputting a 300-degree-phase signal at the I_N output of the third delay cell symbol250cand the I_P input of the first delay cell symbol250a. The first delay cell symbol250aphase-shifts the signal, outputting the same 180-degree-phase signal at the O_N output of the first delay cell symbol250aand the I_N input of the second delay cell symbol250bwith which the second ring began. Notably, each phase propagation path (i.e., each ring) has a robust start-up structure with an odd number of delay cell symbols250, which produces complementary switching between phases according to, for example, cross coupled PMOS transistors210ofFIG. 2A. According to embodiments of the invention, a similarly robust start-up structure may be achieved with an even number of delay cell symbols250, as illustrated inFIG. 5B.

FIG. 5Bshows an embodiment of an even-numbered-delay-cell ring oscillator555, having a configurable voltage generator in communication with four delay cells. As inFIG. 5A, each delay cell is represented by a delay cell symbol250, and the configurable voltage generator is represented by a configurable voltage generator symbol550. A current control device505is in communication with the current control node402of the voltage generator symbol550, and has a voltage-control input node502. The bias-output node204, the first supply-select node202a, and the second supply-select node202bare connected in parallel from the voltage generator symbol550to each of the delay cell symbols250. Further, the output nodes (O_P and O_N) of each delay cell symbol250are in communication with respective input nodes (I_P and I_N) of adjacent delay cell symbols250. It will be appreciated that this configuration of the voltage generator symbol550in communication with the delay cell symbols250a,250b,250c, and250dmay be used to implement a four-stage VCO.

For example, each of the four delay cell symbols250in the ring-oscillator configuration shifts the phase of its input signal by negative 135 degrees. As configured, complete propagation through the ring includes propagation through the four delay cell symbols250twice, causing eight 135-degree phase shifts (i.e., 1080-degrees of total phase shift, or 3 complete 360-degree oscillations). Specifically, the ring can be illustrated as beginning with a 0-degree-phase signal at the O_P output of the first delay cell symbol250aand the I_P input of the second delay cell symbol250b. The second delay cell symbol250bphase-shifts the signal, outputting a 225-degree-phase signal at the I_N input of the third delay cell symbol250c. The third delay cell symbol250cphase-shifts the signal, outputting a 90-degree-phase signal at the I_P input of the fourth delay cell symbol250d. The fourth delay cell symbol250dphase-shifts the signal, outputting a 315-degree-phase signal at the O_N output of the fourth delay cell symbol250dand the I_P input of the first delay cell symbol250a. The first delay cell symbol250aphase-shifts the signal, outputting a 180-degree-phase signal at the I_N input of the second delay cell symbol250b. The second delay cell symbol250bphase-shifts the signal, outputting a 45-degree-phase signal at the I_P input of the third delay cell symbol250c. The third delay cell symbol250cphase-shifts the signal, outputting a 270-degree-phase signal at the I_N input of the fourth delay cell symbol250d. The fourth delay cell symbol250dphase-shifts the signal, outputting a 135-degree-phase signal at the O_P output of the fourth delay cell symbol250dand the I_N input of the first delay cell symbol250a. The first delay cell symbol250aphase-shifts the signal, outputting the same 0-degree-phase signal at the I_P input of the second delay cell symbol250bwith which the ring began.

It will be appreciated that the above mentioned exemplary embodiments of VCO implementations may represent a minimum configuration of elements forming a VCO. In practice, there may be additional blocks allowing programmability of a VCO. For example, embodiments may include or be in communication with components configured to control frequency gain (e.g., degree of sensitivity of the frequency to changes in the voltage at the voltage-control input node502) or to provide frequency offset. It will be further appreciated that the VCO functionality (e.g., as illustrated inFIGS. 1-5) may be integrated as a component of a circuit arrangement.

FIG. 6shows a simplified block diagram of a circuit arrangement600using a VCO, according to various embodiments of the invention, as part of a phase-lock loop (PLL). The circuit arrangement600is shown as an integrated circuit component680with a number of pins690. Each of the pins provides certain input/output functionality, and may be optimized according to its function. For example, the VDDpin690-1and the VSSpin690-5may be metalized as power pins.

The circuit arrangement600includes a reference control block610, a phase-lock loop (PLL) block620, an I/O control block640, a programmable configuration register block650, and a power conditioning block660. In some embodiments, a crystal oscillator or other clock source is in communication with the XINpin690-3and the XOUTpin690-2. In one embodiment, variable capacitance elements612are used to tune the external clock source (e.g., when a crystal or ceramic oscillator is used). A gain stage614, buffer616, and/or other components of the reference control block610may be used to further control the output of the reference clock control block610to generate a master clock signal for use by other blocks of the circuit arrangement600. In some embodiments, the output of the reference control block610is used as a master clock signal for the PLL block620.

The PLL block620is programmable to provide a reference clock signal as a function of the frequency and/or phase of the output of the reference control block610. For example, the PLL block620uses negative feedback to maintain a stable reference clock signal that is mathematically related to the master clock signal. In some embodiments, the PLL block620includes a VCO622. As described above, embodiments of the VCO include a configurable voltage generator400(e.g., as described with reference toFIG. 4) and a set of delay cells200(e.g., as described with reference toFIG. 2A). For example, the VCO may be configured according to the odd-numbered-delay-cell ring oscillator500embodiment ofFIG. 5Aor the even-numbered-delay-cell ring oscillator555ofFIG. 5B.

Embodiments of the programmable configuration register block650provide configuration signals for use by various components of the circuit arrangement600. The programmable configuration register block650may include a number of programmable registers distributed throughout the integrated circuit. For example, the registers may provide distributed, small-scale, volatile memory that are set by a centralized non-volatile memory on power-up. In one embodiment, the programmable configuration register block650is affected in part by input pins, including a PD#/OE pin690-4and an SSon#/FS1pin690-8. For example, the PD#/OE pin690-4provides either a Power Down signal (e.g., if PD#=0(Low), the device is powered down and both SSCLK and REFOUT outputs are weakly pulled low to VSS) or an Output Enable signal (e.g., if OE=1(High)), the SSCLK and REFOUT outputs are enabled; and the SSon#/FS1pin690-8provides either a Programmable Spread Spectrum ON signal (e.g., if SSon#=0 (Low), spread spectrum clocking is on, and if SSon#=1 (High), spread spectrum clocking is off) or a Frequency Select signal (e.g., if FS function is programmed, the clock frequencies can be switched between two sets of frequencies, as programmed).

In some embodiments of the circuit arrangement600, outputs from the reference control block610, the PLL block620, and the programmable configuration register block650are passed to the I/O control block640. Embodiments of the I/O control block640include an output divider block625, a multiplexer (mux) block630, and a programmable I/O buffer block635. The component blocks of the I/O control block640are used to control the characteristics and operation of I/O terminals, like the CLK1pin690-6and the CLK2pin690-7. For example, the programmable I/O buffer block635may be implemented according to embodiments described in U.S. patent application Ser. No. 12/370,163, filed Feb. 12, 2009, entitled “PROGRAMMABLE IO ARCHITECTURE”, which is hereby incorporated by reference in its entirety for all purposes.

It will be appreciated that other functionality may be provided by embodiments of the circuit arrangement600. In some embodiments, the power conditioning block660is included to provide certain power management and/or conditioning functionality. In the embodiment shown, the VDDpin690-1ins coupled with the power conditioning block660. The power conditioning block660then generates an I/O power signal664and a core power signal662, providing appropriate power for driving various I/O and core components, respectively. For example, the integrated circuit680may be coupled, via the VDDpin690-1, with a 3.8-volt supply. The power conditioning block660may be used to convert the 3.8-volt source voltage to a 1.8-volt signal, which may be desired for use by various components of the circuit arrangement600.

FIG. 7illustrates another simplified block diagram of a circuit arrangement700, for use with various embodiments of the invention. An external crystal couples to a voltage controlled crystal oscillator (VCXO)710in an exemplary embodiment. A pair of capacitors715couple crystal oscillator inputs X1, X2to ground. VCXO power (VDDX), VCXO ground (VSSX), and VCXO input voltage (VI) are external inputs to the VCXO710. In some embodiments, the VCXO710is implemented as the reference control block410ofFIG. 6.

An output of the VCXO710is connected with an input multiplexer (mux) of a phase lock loop (PLL1)720, providing a reference signal for the PLL720. Embodiments of the first phase lock loop720are implemented as block620ofFIG. 6. In other embodiments, additional PLLs720may be used to allow for additional I/Os and further programmability. An output of the phase lock loop720is connected with an input multiplexer (mux) of a PLL divider (DIV1)725. An output of the PLL divider725is fed to a MUX730. A first set of outputs of the MUX730are connected with programmable input/output buffers735. Additional outputs from the MUX730may be connected with the input mux of PLL1720and the input mux of the PLL divider725. Embodiments of the PLL divider725, the MUX730, and the programmable input/output buffers735are implemented as the output divider block625, mux block630, and programmable I/O buffer block635, respectively, of the I/O control block640ofFIG. 6.

The clock generator circuit700, including a nonvolatile storage array740, may be fabricated, for example, in a single monolithic semiconductor substrate or alternately, the nonvolatile storage array740may reside on a second semiconductor substrate743. An output of the nonvolatile storage array740may be in communication with a power-on sequencer745. The power-on sequencer745may communicate with a volatile storage array750. In some embodiments, portions of the nonvolatile storage array740, the power-on sequencer745, and/or the volatile storage array750are implemented as the programmable configuration register block650ofFIG. 6.

The volatile storage array750is in communication with a digital-to-analog (D/A) block755, a power conditioner block760, a serial I/O block765, the programmable input/output buffers735, the mux730, the PLL720, the PLL divider725, and the VCXO710. The serial I/O block765communicates with serial data and serial clock inputs SD, SC, the power-on sequencer745, and the MUX730. The power conditioner block760is connected with PLL power inputs VDDA, VSSA. In some embodiments, the power conditioner block760is implemented as the power conditioning block660ofFIG. 6.

It should also be appreciated that the following systems and methods may individually or collectively be components of a larger system, wherein other procedures may take precedence over or otherwise modify their application. Also, a number of steps may be required before, after, or concurrently with the following embodiments. Specific details are given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments.

Accordingly, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.