Vertical transistor with late source/drain epitaxy

VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

FIELD OF THE INVENTION

The present invention relates to vertical field-effect transistor (VFET) devices, and more particularly, to VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process.

BACKGROUND OF THE INVENTION

As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical transport field effect transistor (VFET) devices are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFET devices are being pursued as a viable device option for continued CMOS scaling.

There are, however, some notable challenges associated with implementing a VFET design. For instance, one challenge is being able to precisely control the gate length (Lg) of a VFET. Namely, unlike a planar FET, the physical gate length (Lg) of a VFET is not defined by lithography. Instead, the physical gate length (Lg) of a VFET is defined by a timed recess process of a metal gate, causing a significant variation.

Another challenge for VFET fabrication lies in the ability to produce sharp channel-to-source/drain junctions. With conventional approaches, the bottom source/drain epitaxy is grown in the substrate in between the vertical fin channels, followed by a thermally-driven diffusion of the dopant species. Doing so, however, means that the source/drain region dopant species has to diffuse a relatively long distance through the substrate in order to form channel-to-source/drain junctions. This diffusion process can be difficult to control in order to achieve a well-defined junction. Furthermore, the large volume of substrate material between the epitaxy can result in a relatively high bottom source/drain resistance.

Therefore, improved techniques for VFET device fabrication that produce symmetric, sharp channel-to-source/drain junctions would be desirable.

SUMMARY OF THE INVENTION

The present invention provides vertical field-effect transistor (VFET) devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process. In one aspect of the invention, a VFET device is provided. The VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel; and a top source/drain region over the at least one vertical fin channel.

In another aspect of the invention, another VFET device is provided. The VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel offset from the gate stack by bottom spacers, wherein the bottom source/drain region has an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel offset from the gate stack by top spacers.

In yet another aspect of the invention, a method of fabricating a VFET device is provided. The method includes: forming a stack on a substrate comprising a bottom sacrificial layer disposed on the substrate, an active layer disposed on the bottom sacrificial layer, and a top sacrificial layer disposed on the active layer; patterning at least one fin in the stack, wherein the at least one fin includes a patterned portion of the bottom sacrificial layer, a patterned portion of the active layer and a patterned portion of the top sacrificial layer, and wherein the patterned portion of the active layer serves as a vertical fin channel of the VFET device; forming gate stacks alongside the at least one fin; and removing and replacing the patterned portion of the bottom sacrificial layer and the patterned portion of the top sacrificial layer with an epitaxial material to simultaneously form a bottom source/drain region and a top source/drain region of the VFET device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Provided herein are improved techniques for fabricating vertical field-effect transistor (VFET) devices using a late source/drain epitaxy process meaning that the epitaxy for the top and bottom source/drain regions is formed near the end of the fabrication flow. To do so, sacrificial layers are employed in the process that serve as placeholders for the top and bottom source/drain regions. Later, these sacrificial layers are removed and replaced with the epitaxy for the top and bottom source/drain. Thus, the term ‘sacrificial,’ as used herein, generally refers to a structure that is removed, in whole or in part, during fabrication.

Advantageously, by way of this unique process the top and bottom source/drain epitaxy will be grown on pristine {100} planes which are the optimal crystalline planes to grow the best quality epitaxy in silicon technology. Further, as will be described in detail below, the epitaxy is grown for the top and bottom source/drain regions at the same time, thus requiring only a one-time thermal budget for the channel-to-source/drain junction formation. Notably, doing so enables the formation of symmetric, sharp channel-to-source/drain junctions, improving device performance and reducing variability.

Also, as provided above, conventional approaches to VFET fabrication typically involve growing the bottom source/drain epitaxy in the substrate at the base of the fins, and then using a thermal treatment to diffuse the dopant species. However, this process requires that the dopant species be diffused through a large volume of substrate material. This diffusion process can be difficult to control, and oftentimes results in a relatively high bottom source/drain resistance. Advantageously, the present techniques enable the formation of a uniform epitaxy for the bottom source/drain regions thereby minimizing bottom source/drain region resistance variability and thus device variability.

Given the above overview, an exemplary methodology for fabricating a VFET device using the present late source/drain epitaxy-based process is now described by way of reference toFIGS.1-28. In the following figures, different views of the device structure will be used to depict the fabrication process, including top-down views and various cross-sectional cuts. For instance, as shown inFIG.1(a cross-sectional view A-A′), the process begins with the formation of a stack104of sacrificial/active layers on a substrate102.

According to an exemplary embodiment, substrate102is a bulk semiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe) and/or bulk III-V semiconductor wafer. Alternatively, substrate102can be a semiconductor-on-insulator (SOI) wafer. A SOI wafer includes a SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide it is also referred to herein as a buried oxide or BOX. The SOI layer can include any suitable semiconductor material(s), such as Si, Ge, SiGe and/or a III-V semiconductor. Further, substrate102may already have pre-built structures (not shown) such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc.

As shown inFIG.1, stack104includes a bottom sacrificial layer106disposed on the substrate102, an active layer108disposed on the bottom sacrificial layer106, and a top sacrificial layer110disposed on the active layer108. As highlighted above, the bottom sacrificial layer106and the top sacrificial layer110will serve as placeholders for the (late) bottom and top source/drain regions, respectively.

The active layer108will be used to form the vertical fin channels of the VFET device. As provided above, being able to precisely control the gate length (Lg) of a conventional VFET can be challenging. However, forming the active layer108in this manner as the basis for the vertical fin channels precisely determines the Lg of the resulting VFET device.

In general, the materials chosen for bottom sacrificial layer106and the top sacrificial layer110need to have etch selectivity relative to, among other things, the active layer108and the substrate102. This will enable these sacrificial layers to be removed later on in the process and replaced with the (late) epitaxy for the bottom source/drain regions. For instance, according to an exemplary embodiment, the bottom sacrificial layer106and the top sacrificial layer110are each formed from SiGe, while the active layer108is formed from intrinsic (i.e., undoped) Si.

In one embodiment, an epitaxial growth process is employed to grow alternating epitaxial SiGe, epitaxial intrinsic Si, and epitaxial SiGe on the substrate102to form the bottom sacrificial layer106, the active layer108, and the top sacrificial layer110, respectively. According to an exemplary embodiment, the bottom sacrificial layer106and the top sacrificial layer110each has a thickness of from about 5 nanometers (nm) to about 30 nm and ranges therebetween, and the active layer108has a thickness of from about 10 nm to about 40 nm and ranges therebetween.

FIG.2, a top-down view from viewpoint A (seeFIG.1), illustrates the orientation of the A-A′ cuts (of the actual device region) depicted inFIG.1and in the various other figures described below. From the top-down view ofFIG.2, only the topmost layer of the stack, i.e., the top sacrificial layer110, is visible.

At least one fin304is then patterned in the stack104. SeeFIG.3(a cross-sectional view A-A′). To do so, a fin hardmask302is first formed on the stack104marking the footprint and location of the at least one fin. Suitable hardmask materials include, but are not limited to, nitride hardmask materials such as silicon nitride (SiN), silicon oxynitride (SiON) and/or silicon carbide nitride (SiCN). Standard lithography and etching techniques can be employed to form the fin hardmask302. With standard lithography and etching techniques, a lithographic stack (not shown), e.g., photoresist/organic planarizing layer (OPL)/anti-reflective coating (ARC), is used to pattern the fin hardmask302with the footprint and location of the features to be patterned (in this case the at least one fin). Alternatively, the hardmask can be formed by other suitable techniques, including but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and other self-aligned multiple patterning (SAMP).

An etch is then used to transfer the pattern from the fin hardmask302to the underlying layers of stack104to form the fin(s)304. A directional (anisotropic) etching process such as reactive ion etching (RIE) can be employed for the fin etch. As shown inFIG.3, as-patterned, the fins304extend through the top sacrificial layer110, the active layer108, and partway through the bottom sacrificial layer106. For clarity, the patterned portions of the active layer and the top sacrificial layer are now given the reference numerals108aand110a, respectively. It is notable that patterning the fin(s)304in this manner results in the patterned bottom sacrificial layer now having a first portion106a′ that is part of the fin(s)304and a second portion106a″ underlying the first portion106a′. As shown inFIG.3, these first and second portions106a′ and106a″ of the patterned bottom sacrificial layer have an inverted T-shape configuration in cross-section. As will be described in detail below, subsequent removal and replacement of these first and second portions106a′ and106a″ of the patterned bottom sacrificial layer with the (late) epitaxy will result in the bottom source/drain regions also having this unique inverted T-shape.

Following the patterning of the fin(s)304, isolation regions402(e.g., shallow trench isolations (STIs) are formed in the substrate102at the base of the fin(s)304. SeeFIG.4(a top-down view). By way of example only, the isolation regions402can be formed by depositing a dielectric material and chemical-mechanical polishing (CMP) of the dielectric material, followed by dielectric recess. Suitable dielectric materials for isolation regions402include, but are not limited to, oxide materials such as silicon oxide (SiOx) which can be deposited using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

Bottom spacers502are then formed at the base of the fin(s)304on the second portion106a″ of the patterned bottom sacrificial layer. SeeFIG.5(a cross-sectional view A-A′). Suitable materials for the bottom spacers502include, but are not limited to, oxide spacer materials such as SiOx and/or silicon oxycarbide (SiOC) and/or nitride spacer materials such as SiN, silicon-boron-nitride (SiBN), siliconborocarbonitride (SiBCN) and/or silicon oxycarbonitride (SiOCN).

According to an exemplary embodiment, the bottom spacers502are formed using a directional deposition process whereby a greater amount of the spacer material is deposited on horizontal surfaces (including on top of the second portion106a″ of the patterned bottom sacrificial layer) as compared to vertical surfaces (such as along sidewalls of the fin(s)304). Thus, when an etch is used on the spacer material, the timing of the etch needed to remove the spacer material from the vertical surfaces will leave the bottom spacers502shown inFIG.5on since a greater amount of the spacer material was deposited on the second portion106a″ of the patterned bottom sacrificial layer. By way of example only, a high-density plasma (HDP) chemical vapor deposition (CVD) or physical vapor deposition (PVD) process can be used for directional film deposition, and an oxide- or nitride-selective (depending on the spacer material) isotropic etch can be used to remove the (thinner) spacer material deposited onto the vertical surfaces. According to an exemplary embodiment, the bottom spacers502have a thickness of from about 5 nm to about 20 nm and ranges therebetween.

Gate stacks are then formed alongside the fin(s)304. As shown inFIG.5, the gate stacks include a gate dielectric504disposed on the fin(s)304and at least one workfunction-setting metal506disposed on the gate dielectric504. Although not explicitly shown in the figures, an interfacial oxide may be formed on the exposed surfaces of the fin(s)304prior to the gate dielectric504such that the gate dielectric504is disposed on the fin(s)304over the interfacial oxide. By way of example only, the interfacial oxide can be formed on the exposed surfaces of the fin(s)304by a thermal oxidation, a chemical oxidation, or any other suitable oxide formation process. According to an exemplary embodiment, the interfacial oxide has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween, e.g., about 1 nm.

Suitable materials for the gate dielectric504include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiOxNy), high-κ materials, or any combination thereof. The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ is about 25 for hafnium oxide (HfO2) rather than 3.9 for SiO2). Suitable high-κ materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3) and/or lead zinc niobite (Pb(Zn,Nb)O). The high-κ material can further include dopants such as lanthanum (La), aluminum (Al) and/or magnesium (Mg). The gate dielectric504can be deposited using a process or combination of processes such as, but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, CVD, ALD, etc. According to an exemplary embodiment, the gate dielectric504has a thickness of from about 1 nm to about 5 nm and ranges therebetween.

Suitable workfunction-setting metals506include, but are not limited to, titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium carbide (TiC) titanium aluminum carbide (TiAlC), tantalum carbide (TaC) and/or hafnium carbide (HfC). The workfunction-setting metal(s)506can be deposited using a process or combination of processes such as, but not limited to, CVD, ALD, PVD, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc. According to an exemplary embodiment, the workfunction-setting metal(s)506has a thickness of from about 5 nm to about 10 nm and ranges therebetween.FIG.6provides a top-down view of the VFET device structure following formation of the bottom spacers and gate stack (of which only the workfunction-setting metal(s)506is visible).

A (conformal) liner702is then formed on the gate stack (i.e., on the workfunction-setting metal(s)506) over the fin(s)304. SeeFIG.7(a cross-sectional view A-A′). Suitable materials for liner702include, but are not limited to, nitride materials such as SiN and/or SiCN, which can be deposited using a process such as CVD, ALD or PVD. According to an exemplary embodiment, liner702has a thickness of from about 1 nm to about 3 nm and ranges therebetween.

An interlayer dielectric (ILD)704is then deposited over the gate stack and liner702. Suitable materials for ILD704include, but are not limited to, oxide materials such as SiOx and/or organosilicate glass (SiCOH) and/or ultralow-κ interlayer dielectric (ULK-ILD) materials, e.g., having a dielectric constant κ of less than 2.7. Suitable ultralow-κ dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH). A process such as CVD, ALD, or PVD can be used to deposit the ILD704. Following deposition, the ILD704can be polished down to the liner702using a process such as CMP.

FIG.8provides a top-down view of the VFET device structure following formation of the liner702and ILD704. As shown inFIG.8, following deposition, the ILD704has been polished down to the liner702, thereby exposing a portion of the liner702over the fin(s)304.

Exposure of the liner702enables its removal, as well as the underlying fin hardmask302and gate stack materials over the fin(s)304. SeeFIG.9(a cross-sectional view A-A′). Ultimately, the goal will be to uncover the patterned top sacrificial layer110a, which can then be removed and replaced with the epitaxy for the top source/drain region. As shown inFIG.9, the exposed liner702, the workfunction-setting metal(s)506, gate dielectric504, and fin hardmask302have been removed from the top of the fin(s)304. According to an exemplary embodiment, a RIE or a series of RIE steps is used to remove the liner702, the workfunction-setting metal(s)506, gate dielectric504, and fin hardmask302from the top of the fin(s)304. For instance, an etch-back of the liner702at the top of the fin(s)304exposes the underlying gate stack materials, i.e., the workfunction-setting metal(s)506and the gate dielectric504, which are then removed. In turn, removal of the workfunction-setting metal(s)506and the gate dielectric504exposes the underlying fin hardmask302which is then removed. Removal of the fin hardmask302exposes the underlying patterned top sacrificial layer110a.

FIG.10provides a top-down view of the VFET device structure following removal of the liner702, the workfunction-setting metal(s)506, gate dielectric504, and fin hardmask302from the top of the fin(s)304. Notably, as shown inFIG.10, doing so exposes underlying patterned top sacrificial layer110a.

Referring briefly back toFIG.9, it can be seen that the top-down patterning of the liner702, gate stack materials and fin hardmask302in this manner leaves portions902of the liner702, workfunction-setting metal(s)506and gate dielectric504remaining along the sidewalls above the patterned top sacrificial layer110a. These portions902of the liner702, workfunction-setting metal(s)506and gate dielectric504will need to be recessed in order to form top spacers alongside the patterned top sacrificial layer110a.

Namely, an etch is next performed to remove the portions902of the liner702, gate stack (i.e., workfunction-setting metal(s)506and gate dielectric504) alongside the patterned top sacrificial layer110a. A non-directional (i.e., isotropic) etching process such as a wet chemical or gas phase etch can be employed. SeeFIG.11(a cross-sectional view A-A′). As shown inFIG.11, the liner702, workfunction-setting metal(s)506and gate dielectric504are now recessed below a top surface of the patterned top sacrificial layer110a, forming a trench1101in the ILD704over the fin(s)304(which exposes the patterned top sacrificial layer110a) and forming divots1102(shown outlined with dashes) alongside the patterned top sacrificial layer110a.

Top spacers1104are then formed in the divots1102alongside the patterned top sacrificial layer110a. Suitable materials for the top spacers1104include, but are not limited to, oxide spacer materials such as SiOx and/or SiOC and/or nitride spacer materials such as SiN, SiBN, SiBCN and/or SiOCN. According to an exemplary embodiment, the top spacers1104are formed by conformal deposition of the spacer material over the ILD704and into the trench1101and divots1102, pinching off the gaps between the ILD704and the patterned top sacrificial layer110a, and filling the divots1102. An etch-back of the spacer material (e.g., using an oxide- or nitride-selective RIE as the case may be) forms top spacers1104in the divots1102.

As shown inFIG.11, according to an exemplary embodiment, a top surface of the top spacers1104is coplanar with or slightly below a top surface of the patterned top sacrificial layer110a, while a bottom surface of the top spacers1104is above a bottom surface of the patterned top sacrificial layer110a. As will be described in detail below, this configuration at the top of the fin(s)304will result in a unique T-shaped (late) epitaxy for the top source/drain region.

FIG.12provides a top-down view of the VFET device structure following formation of the top spacers1104. As shown inFIG.12, the top spacers1104are now present alongside the patterned top sacrificial layer110a. The liner702, workfunction-setting metal(s)506and gate dielectric504are no longer visible from this view as they are now covered by the top spacers1104.

The trench1101is then filled with an ILD1302covering top spacers1104. SeeFIG.13(a cross-sectional view A-A′). For clarity, the terms ‘first’ and ‘second’ may also be used herein when referring to ILD704and ILD1302, respectively. Suitable materials for ILD1302include, but are not limited to, oxide materials such as SiOx and/or SiCOH and/or ULK-ILD materials such as pSiCOH. A process such as CVD, ALD, or PVD can be used to deposit the ILD1302. Following deposition, the ILD1302can be polished using a process such as CMP.

FIG.14provides a top-down view of the VFET device structure following deposition of the ILD1302. The top spacers1104are no longer visible from this view as they are now covered by the ILD1302.

In order to help illustrate the following steps of the fabrication process, the views of the device structure will now shift to cross-sectional views B-B′ which depict cuts through one of the fin(s)304along the length of that fin304. By contrast, the cross-sectional views A-A′ employed above depict cuts through one of the fin(s)304perpendicular to that fin304. For instance, referring toFIG.15(a cross-sectional view B-B′), it can be seen that the patterned active layer108ais present between the first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110a. The patterned active layer108awill serve as a vertical fin channel of the VFET device. The gate stack (i.e., the workfunction-setting metal(s)506and gate dielectric504) is present alongside the vertical fin channel. As highlighted above, the first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110awill eventually be removed (at the same time) and replaced with the (late) epitaxy for the bottom and top source/drain regions, respectively. Notably, the first/second portions106a′/106a″ of the patterned bottom sacrificial layer have the above-described inverted T-shaped configuration that will be imparted to the epitaxy for the bottom source/drain region. As will be described in detail below, the epitaxy for the top source/drain region will mirror that T-shaped design.FIG.16, a top-down view from viewpoint B (seeFIG.15), illustrates the orientation of the B-B′ cuts depicted inFIG.15and in the various other figures described below.

Standard lithography and etching techniques (see above) are then used to pattern a (first) contact trench1702in the (first) ILD704(through the liner702and bottom spacers502) down to the second portion106a″ of the patterned bottom sacrificial layer, and a (second) contact trench1704in the (second) ILD1302down to the patterned top sacrificial layer110a. SeeFIG.17(a cross-sectional view B-B′). Any other suitable patterning technique in lieu of the standard lithography and etching techniques can also be used to form contact trenches1702and1704. A directional (anisotropic) etching process such as RIE can be employed for the contact trench etch. As shown inFIG.17, depending on the selectivity of the etch, the contact trenches1702and1704can extend partway into the second portion106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110a, respectively. What is important is that the second portion106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110aare exposed at the bottoms of the contact trenches1702and1704. As will be described in detail below, this will enable the top and bottom sacrificial layers to be selectively removed from the device structure.

FIG.18provides a top-down view of the VFET device structure following formation of the contact trenches1702and1704(the outlines of which are shown using dashes). As highlighted above, and as exemplified inFIG.18, formation of contact trenches1702and1704exposes the second portion106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110awhich will enable the select removal of the top and bottom sacrificial layers (see below).

The first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110aare then selectively removed from the VFET device structure simultaneously (i.e., at the same time) through the contact trenches1702and1704, forming a (first) void1902and a (second) void1904below and above the patterned active layer108a(i.e., vertical fin channel), respectively. SeeFIG.19(a cross-sectional view B-B′). As provided above, the first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110acan be formed from SiGe while the patterned active layer108acan be formed from Si. In that case, the first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110acan be removed using an etchant such as wet hot SCl (an aqueous etch solution containing ammonia and hydrogen peroxide), vapor phase hydrogen chloride (HCl), vapor phase chlorine trifluoride (ClF3) and/or other reactive clean processes (RCP) that are selective for etching of SiGe relative to Si. These etchants will remove the first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110arelative to, among other things, the patterned active layer108a. It is notable that, following removal of the first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110a, the patterned active layer108ais anchored in place by the surrounding ILD704.

FIG.20provides a top-down view of the VFET device structure following removal of first/second portions106a′/106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110a. As shown inFIG.20, the substrate102and the patterned active layer108a(i.e., vertical fin channel) are now visible from the top-down view through contact trenches1702and1704, respectively.

An epitaxy is then grown simultaneously (i.e., at the same time) in the voids1902and1904to form bottom source/drain region2102and top source/drain region2104, respectively. SeeFIG.21(a cross-sectional view B-B′). According to an exemplary embodiment, the bottom/top source/drain regions2102and2104are formed from an in-situ doped (i.e., where a dopant(s) is introduced during growth) or ex-situ doped (e.g., where a dopant(s) is introduced by ion implantation) epitaxial material such as epitaxial Si, epitaxial SiGe, etc. Suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As). Suitable p-type dopants include, but are not limited to, boron (B).

By way of this unique process, the epitaxy for the bottom/top source/drain regions2102and2104will be grown on the surfaces of the patterned active layer108a(i.e., vertical fin channel) exposed within the voids1902and1904. Advantageously, these exposed surfaces of the patterned active layer108aprovide pristine {100} planes for the epitaxial growth thereby enabling the formation of a high-quality material for the bottom/top source/drain regions2102and2104.

Following growth of the epitaxy for the bottom/top source/drain regions2102and2104, an anneal is performed to form the channel-to-source/drain junction. According to an exemplary embodiment, the anneal is performed at a temperature of from about 400 degrees Celsius (° C.) to about 600° C. and ranges therebetween, for a duration of from about 1 minute to about 10 minutes and ranges therebetween. Advantageously, since the epitaxy is grown for the bottom/top source/drain regions2102and2104at the same time, only a one-time thermal budget is required for the channel-to-source/drain junction formation. Notably, doing so enables the formation of symmetric, sharp channel-to-source/drain junctions, improving device performance and reducing variability.

FIG.22provides a top-down view of the VFET device structure following formation of the bottom/top source/drain regions2102and2104. As shown inFIG.22, the bottom/top source/drain regions2102and2104are now visible from the top-down view through contact trenches1702and1704, respectively.

The next task is to pattern a contact trench over the gate stack. To do so, the (first/second) contact trenches1702and1704are first filled with a sacrificial fill material2302. SeeFIG.23(a cross-sectional view B-B′). A casting process such as spin-coating or spray casting can be employed to deposit the sacrificial fill material2302into, and filling, the contact trenches1702and1704. Following deposition, the sacrificial fill material2302can be planarized (e.g., using a process such as CMP or any other suitable planarization technique). The sacrificial fill material2302will serve to protect the bottom/top source/drain regions2102and2104during the subsequent lithography and etching processes. In some embodiments, the sacrificial material is an organic planarizing layer (OPL) material. In other embodiments, the sacrificial material is spin-on-glass (SOG).

Namely, standard lithography and etching techniques (see above) are then used to pattern a (third) contact trench2304in the (first) ILD704(through the liner704) down to the gate stack (in particular the workfunction-setting metal(s)506). SeeFIG.23. A directional (anisotropic) etching process such as RIE can be employed for the contact trench etch. As shown inFIG.23, depending on the selectivity of the etch, the contact trench2304can extend partway into the workfunction-setting metal(s)506. However, what is important is that the workfunction-setting metal(s)506is exposed at the bottom of the contact trench2304.

FIG.24provides a top-down view of the VFET device structure after the contact trenches1702and1704have been filled with sacrificial fill material2302and following formation of the contact trench2304(the outline of which is shown using dashes) in ILD704. As shown inFIG.24, the workfunction-setting metal(s)506is now visible from the top-down view through contact trench2304. Sacrificial fill material2302covers the bottom/top source/drain regions2102and2104that are present at the bottoms of the contact trenches1702and1704, respectively.

Following formation of contact trench2304, the sacrificial fill material2302is removed from the contact trenches1702and1704, and (first/second/third) contacts2502,2504and2506to the bottom/top source/drain regions2102/2104and gate stack (in particular workfunction-setting metal(s)506) are formed in the contact trenches1702,1704and2304, respectively. SeeFIG.25(a cross-sectional view B-B′). By way of example only, the sacrificial fill material2302can be removed from the contact trenches1702and1704using a process such as ashing.

Contacts2502,2504and2506are formed by filling the contact trenches1702,1704and2304with a metal or a combination of metals. Suitable metals include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni) and/or platinum (Pt) which can be deposited into the contact trenches1702,1704and2304using a process such as evaporation, sputtering, or electrochemical plating. Following deposition, the metal overburden can be removed using a process such as CMP. Prior to depositing the metal(s), a barrier layer (not shown) can be deposited into and lining the contact trenches1702,1704and2304. Use of such a barrier layer helps to prevent diffusion of the metal(s) into the surrounding ILD704/1302. Suitable barrier layer materials include, but are not limited to, tantalum (Ta), TaN, titanium (Ti) and/or TiN. Additionally, a seed layer (not shown) can be deposited into and lining the contact trenches1702,1704and2304prior to metal deposition, i.e., to facilitate plating of the metal into the contact trenches1702,1704and2304.

A unique feature of the present VFET device design is illustrated inFIG.25. Namely, based on the above-described process whereby the (late) epitaxy for the bottom/top source/drain regions2102and2104is grown through the contact trenches1702and1704, a portion of that epitaxy can extend into the contact trenches1702and1704. As a result, a portion2508of the bottom source/drain region2102extends up through the bottom spacers502beneath the contact2502. Notably, a width W1 of this portion2508of the bottom source/drain region2102is substantially the same as a width W2 of a bottom of the contact2502, i.e., W1 W2. For instance, W1 differs from W2 by less than or equal to about 0.5 nm.FIG.26provides a top-down view of the VFET device structure following the formation of contacts2502,2504and2506in the contact trenches1702,1704and2304.

FIG.27provides another view (a cross-sectional view A-A′) of the present VFET device structure. As shown inFIG.27, the gate stack (i.e., gate dielectric504and workfunction-setting metal(s)506) is present alongside the patterned active layer108a(i.e., vertical fin channel). The bottom/top source/drain regions2102and2104are present below and above the vertical fin channel, offset from the gate stack by the bottom and top spacers502and1104, respectively. Contact2504is visible in this depiction, and is disposed over the top source/drain region2104.

Other unique features of the present VFET device design are illustrated inFIG.27. Namely, based on the above-described late epitaxy process, the bottom source/drain region2102is present directly below the patterned active layer108a(i.e., vertical fin channel). By comparison, as highlighted above, with conventional approaches to VFET fabrication the bottom source/drain epitaxy is grown in the substrate in between the vertical fin channels. As a result, with the conventional approach the bottom source/drain region will not be present directly below the channel.

As also shown inFIG.27, the bottom source/drain region2102has an inverted T-shape configuration below the patterned active layer108a(i.e., vertical fin channel), while the top source/drain region2104has a T-shaped configuration over the patterned active layer108a(i.e., vertical fin channel). This unique configuration of the bottom/top source/drain regions2102and2104is a result of the late epitaxy approach to replace the first and second portions106a′ and106a″ of the patterned bottom sacrificial layer and the patterned top sacrificial layer110aas described in detail above. Also, as a result of this process, the bottom source/drain region has a flat bottom2702directly below the patterned active layer108a(i.e., vertical fin channel). SeeFIG.27.

As yet another point of comparison, with conventional approaches to VFET fabrication, the bottom and top source/drain epitaxy are grown at different times. Namely, the bottom source/drain epitaxy is typically grown early on in the process (i.e., prior to placement of the bottom spacers, gate, etc.). The top source/drain epitaxy is grown late in the process (i.e., after placement of the top spacers). In that case, asymmetry in bottom and top channel-to-source/drain junctions is inevitable. By comparison, with the present late epitaxy process, the bottom/top source/drain regions2102and2104are formed at the same time, followed by a junction forming anneal. See above. As a result, a junction2704between the vertical fin channel and the bottom source/drain region and a junction2706between the vertical fin channel and the top source/drain region are symmetric. SeeFIG.27. By symmetric, it is meant for example that a portion2708of the bottom source/drain region2102overlaps the gate stack (i.e., gate dielectric504and workfunction-setting metal(s)506) by substantially the same amount as a portion2710of the top source/drain region2104overlaps the gate stack (i.e., gate dielectric504and workfunction-setting metal(s)506). For instance, the amount of overlap between portions2708and2710and the gate stack differs by less than or equal to about 0.5 nm.FIG.28, a top-down view from viewpoint C (seeFIG.27), illustrates the orientation of the A-A′ cut (of the actual device region) depicted inFIG.27.