Methods of forming a replacement gate structure for a transistor device

One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various novel methods of forming a replacement gate structure for a transistor device and various novel embodiments of an integrated circuit (IC) product comprising such transistor devices.

Description of the Related Art

In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NFET or PFET type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices.

The gate structures of many advanced transistor devices are formed by performing known replacement-gate manufacturing techniques, wherein a so-called “dummy” or sacrificial gate structure, including a sacrificial gate cap layer, is formed above the substrate by depositing layers of material and thereafter patterning those layers of material to define line-type structures across the substrate. Thereafter, sidewall spacers are formed adjacent the patterned sacrificial gate structure/sacrificial gate cap. The dummy gate structure remains in place as many process operations are performed to form the device, e.g., the formation of raised, doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate cap is removed by performing a chemical mechanical polishing (CMP) process relative to a layer of insulating material so as to expose the dummy gate structure for further processing. Thereafter, one or more etching processes are performed to remove the dummy gate structure which results in the formation of a gate cavity that is laterally defined by the spacer where the final gate structure for the device will be formed. For example, after the dummy gate structure is removed, various deposition processes were performed to form the materials of the final gate structure in the gate cavity and above the upper surface of the layer of insulating material. Next, one or more CMP process operations are then performed to remove excess portions of the deposited layers of material for the final gate structure that are positioned outside the gate cavity.

As described above, the final CMP process operation essentially defines the vertical height of the final gate structures. Unfortunately, CMP process operations are not uniform across an area and, as a result, there can be significant variations in the final height of the final gate structures, which can lead to significant device and yield performance deficiencies and later processing problems that have to account for such variations in gate height. The variations in the CMP process operation may vary from CMP tool to CMP tool. For example, one CMP tool may have a polishing profile where it removes more material toward the center of the wafer and less material at the edge of the wafer—a “center-fast, edge-slow” polishing profile. Yet another processing tool may have just the opposite polishing profile—a “center-slow, edge-fast” polishing profile—whereby more material is removed from areas near the edge of the wafer as compared to areas near the center of the wafer. Additionally, the polishing profile may not be uniform across the substrate, e.g., there may be localized regions where polishing variations occur. Such CMP variations occur on a lot-to-lot basis, a wafer-to-wafer basis and on a within wafer basis, thereby leading to corresponding variations in the gate height of the final gate structures on a similar basis.

The present disclosure is generally directed to various novel methods of forming a replacement gate structure for a transistor device and various novel embodiments of an IC product comprising such transistor devices that may at least reduce one or more of the problems identified above.

SUMMARY

Generally, the present disclosure is directed to various novel methods of forming a replacement gate structure for a transistor device and various novel embodiments of an IC product comprising such transistor devices. One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.

One illustrative method disclosed herein includes forming at least one layer of material above a semiconductor substrate, forming a sacrificial gate cavity in the at least one layer of material, forming at least a sacrificial gate electrode in the sacrificial gate cavity and forming a sacrificial gate cap above the sacrificial gate electrode. In this illustrative example, the method also includes forming at least one sidewall spacer adjacent at least the sacrificial gate electrode, removing at least the sacrificial gate cap and the sacrificial gate electrode to form a replacement gate cavity between at least the first sidewall spacer, and forming a final replacement gate structure in the replacement gate cavity.

DETAILED DESCRIPTION

As will be appreciated by those skilled in the art after a complete reading of the present application, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components, structures and layers of material depicted herein may be formed using a variety of different materials and by performing a variety of known process operations, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS. 1-58depict various novel methods of forming a replacement gate structure for a transistor device and various novel embodiments of an IC product100comprising such transistor devices. In the depicted example, the IC product100comprises a plurality of PFET transistors101P and a plurality of NFET transistors101N (collectively referenced using the numeral101). The IC product100will be formed on and above a semiconductor substrate102. The semiconductor substrate102may have a variety of configurations, such as a bulk silicon configuration. The substrate102may also have a semiconductor-on-insulator (SOI) configuration that includes a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer, wherein transistor devices (not shown) that are formed on the substrate are formed in and above the active semiconductor layer. The substrate102may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.

As will be appreciated by those skilled in the art after a complete reading of the present application, the transistor devices101disclosed herein may be either NFET devices or PFET devices. Moreover, the transistor devices101disclosed herein may have any configuration, e.g., FinFET devices, planar devices, vertical devices, etc. The gate length of the transistor devices101need not all be the same, but that may be the case in some applications. For purposes of disclosure, the transistor devices101depicted herein are FinFET devices, the gate structure for the transistor devices will be formed using a replacement gate manufacturing technique and the transistors101will be depicted as all having substantially the same gate length. However, the presently disclosed subject matter should not be considered to be limited to the illustrative examples depicted herein.

FIG. 1is a simplistic plan view of the transistor devices101. As shown therein, each of the PFET transistors101P comprises first and second fins103A,103B and a gate structure104A,104B. Each of the NFET transistors101N comprises first and second fins103C and103D and a gate structure104C,104D. The fins will be collectively referenced using the numeral103. In the illustrative case where the transistor devices101are FinFET devices, each of the transistor devices101may be formed with any desired number of fins103, and each of the transistor devices101need not have the same number of fins103, but that may be the case in some applications. The height and cross-sectional configuration of the fins103may also vary depending upon the particular application. In the examples depicted herein, the fins103will be depicted as have a simplistic rectangular cross-sectional configuration having a substantially uniform thickness throughout the height of the fins103. In a real-world device, the fins103may have a tapered cross-sectional configuration, wherein the width of the upper surface of the fin103(i.e., the top critical dimension) in the gate width direction of the devices101is less than the width of the bottom of the fin103in the gate width direction. Additionally, the axial length of the fins103may also vary depending upon the particular application, e.g., the axial length of the fins103on the PFET transistors101P may be different than the axial length of the fins103on the NFET transistors101N, but that may not be the case in all applications. Thus, the size and configuration of the fins103, and the manner in which they are made, should not be considered a limitation of the presently disclosed subject matter.

FIG. 1also indicates where various cross-sectional views (views “A-A”, “B-B”, “C-C” and “D-D”) of the transistor devices101depicted in the attached drawings are taken. More specifically, the cross-sectional view A-A is taken through the axial length of the fin103A in the gate length (GL—current transport) direction of the PFET transistors101P. The cross-sectional view B-B is taken through the gate structure104A of one of the PFET transistors101P in the gate width (GW) direction of the PFET transistors101P, i.e., transverse to the long axis of the fin103A. Similarly, the cross-sectional view C-C is taken through the axial length of the fin103C in the gate length (GL—current transport) direction of one of the NFET transistors101N. The cross-sectional view D-D is taken through the gate structure104C of one of the NFET transistors101N in the gate width (GW) direction of the NFET transistor101N, i.e., transverse to the long axis of the fin103C. The plan view in the drawings does not reflect the processing shown in the cross-sectional views of the transistor devices101.

FIGS. 2-5depict the IC product100after several process operations were performed. First, the fins103were formed by performing known masking and etching processes to form fin-formation trenches105in the substrate102. Then, a layer of insulating material106was formed so as to over-fill the trenches105between the fins103. The layer of insulating material106may be comprised of, for example, silicon dioxide, a HARP oxide, HDP oxide, flowable oxide, SiOC, SiOCN, etc. Next, one or more planarization processes (e.g., a CMP and/or etch-back process) were performed to planarize the upper surface of the layer of insulating material106. At that point, a timed, recess etching process was performed to remove a portion of the vertical thickness of the layer of insulating material106such that the layer of insulating material106has a substantially planar recessed upper surface106R that is positioned at a desired height level within the trenches105. The amount of recessing of the layer of insulating material106may vary depending upon the particular application. This recess etching process exposes the desired final fin height of the fins103.

With continued reference toFIGS. 2-5, a sacrificial gate insulation layer107was formed for the transistor devices101. The sacrificial gate insulation layer107may be comprised of a variety of different materials, e.g., silicon dioxide, it may be formed to any desired thickness, e.g., 1-10 nm, and it may be formed by performing a conformal deposition process. Next, a layer of polish-stop material109was formed above the sacrificial gate insulation layer107so as to over-fill the trenches105between the fins103. The layer of polish-stop material109may be comprised of, for example, silicon carbon nitride (SiCN), SiBN, SiCNB, etc., and it may be formed by performing a conformal deposition process. The layer of polish-stop material109has a vertical thickness109X at a location above the upper surface of the substrate102(e.g., above the upper surface of the fin103in the case of a FinFET device or above a planar upper surface of a substrate for a planar transistor device), the magnitude of which may vary depending upon the particular application, e.g., 5-100 nm. Thereafter, a layer of sacrificial material111was formed above the layer of polish-stop material109. The layer of sacrificial material111may be comprised of a variety of different materials, e.g., amorphous carbon, SiOH, SiON, etc., and it may be formed by performing a blanket deposition process. In some cases, the upper surface of the layer of sacrificial material111may be planarized after it is initially deposited. The layer of sacrificial material111has a vertical thickness111X at a location above the upper surface of the substrate102, the magnitude of which may vary depending upon the particular application, e.g., 5-1000 nm.

FIGS. 6-9depict the IC product100after a patterned etch mask113, e.g., a patterned layer of photoresist/BARC, was formed on the product100by performing traditional manufacturing techniques.

FIGS. 10-13depict the IC product100after one or more etching processes were performed to remove exposed portions of the layer of sacrificial material111and the layer of polish-stop material109. This process operation stops on the sacrificial gate insulation layer107and results in the formation of a plurality of sacrificial gate cavities114.

FIGS. 14-17depict the IC product100after several process operations were performed. First, the patterned etch mask113was removed. Thereafter, sacrificial (or “dummy”) gate electrode structures115, with a sacrificial gate cap117formed thereabove, were formed in the sacrificial gate cavity114for each of the transistors101. Collectively, the sacrificial gate electrode115and the sacrificial gate insulation layer107may be referred to as the sacrificial gate structure for the transistor devices101. In one illustrative embodiment, the sacrificial gate electrode115may comprise polysilicon or amorphous silicon and the sacrificial gate cap117may comprise silicon nitride. In one illustrative process flow, the sacrificial gate electrodes115may be formed by depositing the material of the sacrificial gate electrodes115across the product100so as to over-fill the sacrificial gate cavities114. Then, one or more CMP process and/or etch-back process operations were performed to remove all of the material of the sacrificial gate electrodes115positioned outside of the sacrificial gate cavities114and above the upper surface of the layer of sacrificial material111. At that point, a recess etching process was performed to remove some of the vertical thickness of the sacrificial gate electrode115within the sacrificial gate cavities114so as to make room for the sacrificial gate caps117that will be formed above the recessed materials of the sacrificial gate electrodes115within the sacrificial gate cavities114. Note that the process of forming at least the sacrificial gate electrode115and the sacrificial gate cap117in a previously formed sacrificial gate cavity114is fundamentally different from prior art techniques wherein the sacrificial gate electrodes and the sacrificial gate caps were formed by blanket depositing the materials for the sacrificial gate electrodes and the sacrificial gate caps above the substrate and thereafter patterning those materials to form elongated line-type features that comprise the patterned sacrificial gate electrode and the sacrificial gate cap. At that point, one or more sidewall spacers were formed adjacent the line-type structures and one or more layers of insulating material were formed in remaining spaces between the spacers positioned adjacent the sacrificial gate structures.

FIGS. 18-21depict the IC product100after one or more etching processes were performed to remove the layer of sacrificial material111selectively relative to the surrounding materials. This process operation exposes the upper surface of the layer of polish-stop material109as well the sidewalls of an upper portion of the sacrificial gate electrodes115.

FIGS. 22-25depict the IC product100after several process operations were performed. First, a liner layer127was formed on both of the devices101. The liner layer127may be comprised of a variety of different materials (e.g., a low-k material (k value of 3.3 or less), etc.), it may be formed to any desired thickness (e.g., 2-50 nm), and it may be formed by performing a conformal deposition process. Next, as shown inFIGS. 24-25, a patterned mask layer119, e.g., a patterned layer of photoresist/BARC, was formed on the product100by performing traditional manufacturing techniques. The patterned mask layer119covers the NFET transistors101N while leaving the PFET transistors101P exposed for further processing.

FIGS. 26-29depict the IC product100after several process operations were performed. First, an illustrative sidewall spacer structure127A (e.g., a low-k material (k value of 3.3 or less), etc.) was formed adjacent the exposed sidewalls of the sacrificial gate electrodes115of the PFET transistors101P and above the layer of polish-stop material109. The spacer structure127A may be formed by performing an anisotropic etching process on the liner layer127. In the examples depicted herein, the spacer structure127A is depicted as a single sidewall spacer. In practice, the spacer structure127A may be comprised of a plurality of sidewall spacers that may or may not be comprised of different materials. The lateral width of the spacer structure127A (in the gate length direction of the devices101) at the base of the spacer structure127A may vary depending upon the particular application, e.g., 2-50 nm. Next, an anisotropic etching process was performed to remove exposed portions of the layer of polish-stop material109wherein the spacer structure127A acts as an etch mask. This process operation exposes the sacrificial gate insulation layer107results in the formation of a polish-stop sidewall spacer109S1positioned adjacent the sidewalls of a lower portion of the sacrificial gate electrodes115of the PFET transistors101P. The lateral width of the spacer structure127A (in the gate length direction of the devices101) at the base of the spacer structure127A substantially defines the lateral width of the polish-stop sidewall spacer109S1(in the gate length direction of the devices101), which may impact downstream etch cavity and proximity and, as a result, may affect device performance. This process operation results in the formation of a composite spacer structure123that comprises the spacer structure127A positioned above (or in some cases on and in physical contact with) the polish-stop sidewall spacer109S1. Given the nature of the process performed to form the polish-stop sidewall spacer109S1, at a location above the upper surface of the substrate102(e.g., above the upper surface of the fin103in the case of a FinFET device or above a planar upper surface of a substrate for a planar transistor device), the polish-stop sidewall spacer109S1, when viewed in a cross-section taken through the polish-stop sidewall spacer109S1in a direction corresponding to the gate length direction of the devices101, may have a substantially rectangular configuration. That is, the polish-stop sidewall spacer109S1, at a location above the upper surface of the substrate102, may have a substantially uniform width109W1throughout substantially an entire vertical height109H1of the polish-stop sidewall spacer109S1. In some applications, the width109W1may range from about 2-50 nm and the vertical height109H1may range from about 5-100 nm. The polish-stop sidewall spacer109S1, at a location above the upper surface of the substrate102, may also have a substantially planar upper surface109U that is substantially parallel to the upper surface of the substrate102.

With reference toFIG. 58, at the time the layer of polish-stop material109was formed on the substrate102(seeFIGS. 2-5), the layer of polish-stop material109may also be blanket deposited in areas of the substrate102where active transistor devices will not be formed (e.g., one or more “dummy” areas of the substrate102). At some point in the process flow, such as, for example, when performing the etching process to form the polish-stop sidewall spacer109S1, the layer of polish-stop material109may be patterned to define one or more regions of polish-stop material109T at one or more locations on the substrate102, as shown inFIG. 58. In the depicted example, the regions of polish-stop material109T are depicted as being discrete islands of polish-stop islands of material. However, as will be appreciated by those skilled in the art after a complete reading of the present application, the regions of polish-stop material109T may be of any size or configuration (when viewed from above), and the regions of polish-stop material109T need not be formed as discrete islands of material. Moreover, some IC products100may not have any of the regions of polish-stop material109T. If present, the one or more regions of polish-stop material109T may be formed at any desired location on the substrate102. For example, such regions of polish-stop material109T may be formed in one or more die on the substrate102, in the scribe lines, etc. If present, the regions of polish-stop material109T may be formed in an organized pattern or array or they may be formed randomly across the substrate102.

FIGS. 30-33depict the IC product100after several process operations were performed. First, known manufacturing techniques were performed to form epi cavities124in the substrate102in the source/drain regions of the PFET transistors101P. Thereafter, known manufacturing techniques were performed to form epi semiconductor material125in the epi cavities124. The source/drain epi semiconductor material125for the PFET transistors101P may be comprised of a variety of different materials, e.g., silicon (Si), silicon germanium (SiGe), etc.

FIGS. 34-37depict the IC product100after a layer of spacer material129was formed on both of the devices101. The layer of spacer material129may be comprised of a variety of different materials (e.g., a low-k material (k value of 3.3 or less), etc.), it may be formed to any desired thickness (e.g., 2-50 nm), and it may be formed by performing a conformal deposition process.

FIGS. 38-41depict the IC product100after several process operations were performed. First, as shown inFIGS. 38-39, a patterned mask layer131, e.g., a patterned layer of photoresist/BARC, was formed on the product100by performing traditional manufacturing techniques. The patterned mask layer131, covers the PFET transistors101P while leaving the NFET transistors101N exposed for further processing. Next, as shown inFIGS. 40-41, an illustrative composite sidewall spacer structure132was formed adjacent the exposed sidewalls of the sacrificial gate electrode115of the NFET transistors101N and above (and in some cases on and in physical contact with) the layer of polish-stop material109. The composite spacer structure132may be formed by performing one or more anisotropic etching processes on the layer of spacer material129and the liner layer127. As depicted, these process operations result in the format of the composite spacer structure132that comprises the L-shaped liner127L and the sidewall spacer129S positioned on the L-shaped liner127L. The lateral width of the composite spacer structure132(in the gate length direction of the NFET transistors101N) at the base of the composite spacer structure132may vary depending upon the particular application, e.g., 2-50 nm.

Thereafter, with continued reference toFIGS. 38-41, an anisotropic etching process was performed to remove exposed portions of the layer of polish-stop material109wherein the composite spacer structure132acts as an etch mask. This process operation exposes the sacrificial gate insulation layer107and results in the formation of a polish-stop sidewall spacer109S2positioned adjacent the sidewalls of a lower portion of the sacrificial gate electrode115of the NFET transistors101N. The lateral width of the composite spacer structure132(in the gate length direction of the devices101) at the base of the composite spacer structure132substantially defines the lateral width of the polish-stop sidewall spacer109S2(in the gate length direction of the devices101). This process operation results in the formation of an overall composite spacer structure133that comprises the composite spacer structure132and the polish-stop sidewall spacer109S2, wherein the composite spacer structure132is positioned above (or in some cases on and in physical contact with) the polish-stop sidewall spacer109S2. Given the nature of the process performed to form the polish-stop sidewall spacer109S2, at a location above the upper surface of the substrate102(e.g., above the upper surface of the fin103in the case of a FinFET device or above a planar upper surface of a substrate for a planar transistor device), the polish-stop sidewall spacer109S2, when viewed in a cross-section taken through the polish-stop sidewall spacer109S2in a direction corresponding to the gate length direction of the devices101, may have a substantially rectangular configuration. That is, the polish-stop sidewall spacer109S2, at a location above the upper surface of the substrate102, may have a substantially uniform width109W2throughout substantially an entire vertical height109H2of the polish-stop sidewall spacer109S2. In some applications, the width109W2may range from about 2-50 nm and the vertical height109H2may range from about 5-100 nm. The above-referenced regions of polish-stop material109T could also be formed at the same time the etching process was performed to form the polish-stop sidewall spacer109S2.

FIGS. 42-45depict the IC product100after several process operations were performed. First, the patterned mask layer131was removed from the PFET transistors101P. Then, known manufacturing techniques were performed to form epi cavities134in the substrate102in the source/drain regions of the NFET transistors101N. Next, known manufacturing techniques were performed to form epi semiconductor material135in the epi cavities134. The source/drain epi semiconductor material135for the NFET transistors101N may be comprised of a variety of different materials, e.g., silicon (Si), silicon phosphorus, etc.

FIGS. 46-49depict the IC product100after several process operations were performed that ultimately result in the formation of illustrative and simplistically depicted replacement or final gate structures139for the devices101. The final gate structures139are intended to be representative in nature of any type of gate structure that may be employed in manufacturing integrated circuit products using replacement-gate manufacturing techniques. Of course, the final gate structure139for the PFET transistors101P may contain different materials, e.g., different work function materials, than the final gate structure139for the NFET transistors101N. In general, the final gate structures139may comprise one or more gate insulation layers (not separately shown), such as, for example, silicon dioxide, a so-called high-k (k greater than 10) insulation material, etc., and one or more conductive material layers (not separately shown) that act as the gate electrode, e.g., a metal, a metal alloy, titanium nitride, tantalum nitride, tungsten, aluminum, polysilicon, etc.

Still referencingFIGS. 46-49, a layer of insulating material137was deposited on the product100so as to overfill the spaces above the regions of epi semiconductor material125,135and such that the as-deposited upper surface of the layer of insulating material137is positioned above the upper surface of the sacrificial gate caps117. Thereafter, one or more CMP process operations were then performed to remove the sacrificial gate caps117(and other materials) relative to a layer of insulating material137so as to expose the sacrificial gate electrodes115for further processing. Next, one or more etching processes were performed to remove the sacrificial gate electrodes115and the sacrificial gate insulation layer107in the space between the spacer structure123(FIG. 26) and the spacer structure133(FIG. 40) so as to form a replacement gate cavity138for each of the devices101between the spacer structures123,133.

Still referencingFIGS. 46-49, several deposition processes were performed to form the materials of the final gate structures139in the replacement gate cavities138. For example, a conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process may be performed to conformably deposit a gate insulation layer comprised of a high-k layer of insulating material, e.g., hafnium oxide, in the gate cavities138. Thereafter, one or more metal or metal alloy layers and/or polysilicon layers (that will become the gate electrode) may be deposited in the gate cavities138above the gate insulation layer. One or more CMP process operations may then be performed to remove excess portions of the deposited layers of material for the final gate structures139that are positioned outside the gate cavities138. These operations result in the schematically depicted final gate structures139. Note that, in one embodiment, the composite spacer structure123and the overall composite spacer structure133are positioned on and in physical contact with the sidewalls of their associated final gate structures.

FIGS. 50-53depict the IC product100after one or more CMP process operations were performed to reduce the vertical height of the final gate structures139using the polish-stop spacers109S1and109S2as a final polish stop. If present on the IC product100, the regions of polish-stop material109T may also act as a final polish stop. In the depicted example, at this point in the process flow, the upper surface of the final gate structures139is substantially coplanar with the upper surface of the polish-stop spacers109S1and109S2(and the regions of polish-stop material109T if present). At this point in the process flow, at a location above the upper surface of the substrate102(e.g., above the upper surface of the fin103in the case of a FinFET device or above a planar upper surface of a substrate for a planar transistor device), the upper surface139S of the final gate structures139may be about 5-100 nm above the upper surface102S of the substrate102, based upon current-day technology. As will be appreciated by those skilled in the art after a complete reading of the present application, reducing the vertical height of the final gate structures139will result in a reduction of the parasitic gate to source/drain capacitance and thereby result in improved performance of the resulting devices101. Additionally, the methods and structures disclosed herein can lead to more uniform gate height across the substrate102and reduce or eliminate the problems associated with variations of CMP process operations in terms of controlling the final vertical height of the final gate structures139. As will be appreciated by those skilled in the art after a complete reading of the present application, at least some CMP process operations performed to remove the materials of the gate structures139are timed operations without an effective polish-stop material positioned adjacent the gate structure to effectively control the final gate height of the final gate structures139. Typically, silicon dioxide, a common ILD, has a significantly higher removal rate as compared to SiCN or SiN. The unique selectivity of the materials during polishing operations (relative to silicon dioxide) make these materials effective polish-stop materials that can promote more uniform gate heights across a substrate and thereby improve device performance.

Although the steps shown inFIGS. 46-49and inFIGS. 50-53are depicted as being separate steps, in practice, they may be performed as a substantially continuous one or more CMP process operations until such time as the CMP process stops on the polish-stop sidewall spacers109S1and109S2(and, if present, the regions of polish-stop material109). More specifically, after the materials for the final gate structures139are deposited in the replacement gate cavities128and above the upper surface of the layer of insulating material137(as described in the discussion aboutFIGS. 46-49), then one or more CMP process operations may be performed to remove the materials of the final gate structures139positioned outside of the replacement gate cavities138and to thereafter reduce the height of the materials of the final gate structures139to the height shown inFIGS. 50-53.

In one illustrative process flow, at the point of processing depicted inFIGS. 50-53, a layer of insulating material (not shown), e.g., a gate capping layer of silicon nitride, SiCN, etc., may be deposited above the final gate structures139and the recessed layer of insulating material137. At that point, one or more etching processes may be performed through a patterned etch mask (not shown) to form openings that expose the regions of epi semiconductor materials125,135on the devices101. Then, known manufacturing techniques may be performed to form conductive source/drain metallization structures (not shown) so as to conductively contact the regions of epi semiconductor materials125,135. At that point, the above-described source-drain metallization structure may be formed by performing known manufacturing techniques.

In another illustrative process flow, and with reference toFIGS. 54-57, after the processing depicted inFIGS. 50-53, final gate caps141were formed above the final gate structures139. More specifically, a timed, recess etching process was performed to recess the final gate structures139shown inFIGS. 50-53so as to thereby make room for the final gate caps141to be formed in the replacement gate cavities138above the recessed final gate structures139. The final gate caps141were formed by depositing a layer of gate cap material, e.g., silicon nitride, SiCN, etc., across the substrate and thereafter performing a CMP process to remove the excess gate cap material positioned above the layer of insulating material137. In this embodiment, the recessed upper surface139R of the final gate structures139may be about 2-10 nm above the upper surface102S of the substrate102, based upon current-day technology. At that point, the above-described source-drain metallization structure may be formed by performing known manufacturing techniques.

In the examples above, the polish-stop spacer109S1was formed on the PFET transistors101P prior to the formation of the polish-stop spacer109S2on the NEFT devices101N. However, as will be appreciated by those skilled in the art after a complete reading of the present application, the process flow could have been reversed. Stated another way, the processing steps performed on the PFET transistors101P could have been performed on the NFET transistors101N and vice-versa.