Method of manufacturing nonvolatile memory device

A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.

CROSS-REFERENCE TO RELATED APPLICATION

Priority to Korean patent application number 10-2010-0017052 filed on Feb. 25, 2010, the entire disclosure of which is incorporated by reference herein, is claimed.

BACKGROUND

Exemplary embodiments relate to a method of manufacturing a nonvolatile memory device and, more particularly, to a method of manufacturing a nonvolatile memory device, which is capable of compensating for the concentration of impurity ions in a charge trap layer.

Among nonvolatile memory devices, a NAND flash memory device having a structure advantageous for a high degree of integration is being actively developed. In the NAND flash memory device, a memory cell can be programmed with a desired threshold voltage by controlling electrons trapped/stored in the charge trap layer of the memory cell. The amount of charges trapped into the charge trap layer when the program is performed can be controlled by supplying a specific voltage to a control gate formed over the charge trap layer with a dielectric layer formed therebetween. Accordingly, a coupling ratio, which is a ratio of a voltage supplied to the control gate to a voltage induced to the charge trap layer, becomes an important factor to determine the operating characteristics of the NAND flash memory device. In particular, when the coupling ratio remains consistent, a distribution characteristic with respect to threshold voltages of the device can be prevented from being deteriorated without the occurrence of an Abnormal Program Cell (APC). Further, the failure of a read operation can be prevented as well.

However, the coupling ratio may vary due to a depletion phenomenon occurring in the charge trap layer. The charge trap layer is mainly made of polysilicon including impurity ions. The impurity ions included in the charge trap layer may continue to be discharged externally because of heat generated in subsequent processes. If the concentration of impurity ions included in the charge trap layer is excessively lowered, the depletion phenomenon occurs, which may deteriorate a distribution characteristic of threshold voltages of the device and cause a read operation to fail.

In order to address the above concerns, after forming the charge trap layer including the impurity ions, additional impurity ions may be implanted into the charge trap layer through an additional impurity ion implantation process. However, the additional impurity ions may also be implanted into a portion which is not intended to be implanted (e.g., the active region of a semiconductor substrate used as a channel), and thus the threshold voltage Vt of a memory cell can shift.

BRIEF SUMMARY

Exemplary embodiments relate to a method of manufacturing a nonvolatile memory device, which is capable of compensating for the concentration of impurity ions in a charge trap layer in such a way that impurity ions within a compensation layer are diffused into the charge trap layer.

A method of manufacturing a nonvolatile memory device according to an exemplary aspect of the present disclosure includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on the surface of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.

A method of manufacturing a nonvolatile memory device according to another exemplary aspect of the present disclosure includes forming tunnel insulating layer over a semiconductor substrate, forming charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a first dielectric layer, including second impurity ions of a second concentration, along the surface of the charge trap layer, diffusing the second impurity ions within the first dielectric layer toward the charge trap layer, stacking second and third dielectric layers over the first dielectric layer, and forming a conductive layer for a control gate on the third dielectric layer.

Before the forming of the first dielectric layer, the method may further include patterning the tunnel insulating layer and the charge trap layer to expose the semiconductor substrate, etching the exposed semiconductor substrate to form trenches, and filling the trenches with isolation insulation layers.

A top surface of the isolation insulation layers may be lower than a top surface of the charge trap layer, and higher than a top surface of the tunnel insulating layer.

After forming the isolation layers, the surface of the patterned charge trap layer may be oxidized during the forming of the first dielectric layer.

After forming the isolation layers, the method may further include forming an oxide layer by oxidizing the surface of the patterned charge trap layer, and removing the oxide layer to reduce the width of an upper side of the charge trap layer.

The first dielectric layer may be made of Phospho Silicate Glass (PSG) or Boron Silicate Glass (BSG) of a solid solution state.

The second dielectric layer may be formed of a nitride layer, and the third dielectric layer is formed of an oxide layer.

The charge trap layer may include a doped polysilicon layer formed using gas, including the first impurity ions, and a silicon (Si) source gas.

The charge trap layer may include a doped polysilicon layer formed by implanting the first impurity ions into an undoped polysilicon layer formed using a silicon (Si) source gas.

The first impurity ions may include 3-valence or 5-valence ions, and the second concentration may be higher than the first concentration. Further, the second impurity ions may have identical 3-valence or 5-valence ions as the first impurity ions.

A method of manufacturing a nonvolatile memory device according to another exemplary aspect of the present disclosure includes forming a charge trap layer doped with first impurity ions, having a first concentration, over a semiconductor substrate, patterning the charge trap layer to form trenches in the substrate between the patterned charge trap layer, filling the trenches with isolation layers to expose the upper side of the patterned charge trap layer, forming a compensation layer doped with second impurity ions, having a higher concentration than the first concentration, over the charge trap layer, and diffusing the second impurity ions within the compensation layer toward the charge trap layer.

DESCRIPTION OF EMBODIMENTS

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to enable those of ordinary skill in the art to make and use the exemplary embodiments of the disclosure.

FIGS. 1A to 1Hare cross-sectional views illustrating a method of forming the patterns of a nonvolatile memory device according to a first exemplary embodiment of this disclosure. In particular, a method of manufacturing a NAND flash memory device is described below as an example with reference toFIGS. 1A to 1H.

Referring toFIG. 1A, a semiconductor substrate101in accordance with the exemplary embodiment includes active regions A and isolation regions. Isolation structures, including trenches107and isolation layers109, are formed in the respective isolation regions of the semiconductor substrate101. Furthermore, patterned tunnel insulating layers103and charge trap layers105are formed over the active regions A of the semiconductor substrate101. The active regions A are defined as portions of the substrate between the plurality of isolation structures which are spaced from each other.

Examples of a method of forming the isolation structures and a method of patterning the tunnel insulating layers103and the charge trap layers105are described in detail below.

First, a well (not shown) is formed in the semiconductor substrate101. Next, the tunnel insulating layer103, the charge trap layer105, and an isolation hard mask pattern (not shown) are stacked over the semiconductor substrate101on which an ion implantation process for controlling the threshold voltage of memory cells has been performed.

The tunnel insulating layer103may include an oxide layer and can be formed by using an oxidization process or a deposition process.

The charge trap layer105may be formed of a polysilicon layer including first impurity ions (i.e., a doped polysilicon layer). The polysilicon layer including the first impurity ions can be formed by using silicon (Si) source gas and gas including the first impurity ions. Alternatively, the polysilicon layer including the first impurity ions can be formed by forming an undoped polysilicon layer by using silicon (Si) source gas and implanting the first impurity ions into the undoped polysilicon layer.

SiH4or SiH2Cl2gas can be used as the silicon (Si) source gas. The gas including the first impurity ions can be gas including a 3-valence or 5-valence ion depending on the type of impurity ions to be doped into the polysilicon layer. For example, where a 3-valence ion, such as phosphorus (P), is sought to be doped into the polysilicon layer, PH3gas can be used as the gas including the impurity ions.

The isolation hard mask pattern is formed over the active regions A of the semiconductor substrate101. Furthermore, the isolation hard mask pattern is formed to expose the charge trap layer105formed over the isolation regions. The exposed charge trap layer105is removed by using the isolation hard mask pattern as an etch mask. Thus, the tunnel insulating layer103formed over the isolation regions of the semiconductor substrate101is exposed. Next, the exposed tunnel insulating layer103is removed by using the isolation hard mask pattern as an etch mask, thereby exposing the isolation regions of the semiconductor substrate101. Next, the exposed semiconductor substrate101is etched to a predetermined depth by using the isolation hard mask pattern as an etch mask, thereby forming the plurality of trenches107. Next, the isolation hard mask pattern can be removed.

After forming the trenches107, the isolation layer109having a thickness sufficient to fill the insides of the trenches107is formed over the semiconductor substrate101. Next, a polishing process is performed to expose the charge trap layer105. The polishing process can be performed by using a Chemical Mechanical Polishing (CMP) process. Thus, the isolation layers109having the same height as the charge trap layer105can be formed. Through the formation of the isolation layers109, the plurality of active regions A spaced apart from one another by the isolation layers109and the trenches107is defined. Furthermore, the tunnel insulating layer103and the charge trap layer105remain over each of the active regions A of the semiconductor substrate101. Thus, the active regions A are spaced apart from one another with the isolation layer109in between them, and the tunnel insulating layers103and the charge trap layers105are patterned as shown inFIG. 1A. Each of the patterned charge trap layers105has a first width W1.

Here, the isolation layers109can be made of oxide-series materials. For example, the isolation layer109can be formed of a High Temperature Oxide (HTO) layer, a High Density Plasma (HDP) oxide layer, a Tetra Ethyl Ortho Silicate (TEOS) layer, a Boron-Phosphorus Silicate Glass (BPSG) layer, or an Undoped Silicate Glass (USG) layer.

The isolation layers109have their height lowered by an etch process, such as etch-back, thereby forming the isolation structures having an Effective Field Height (EFH) controlled by the etch process. Here, a top surface of the isolation structures is preferably controlled to be lower than a top surface of the charge trap layers105such that the area where the charge trap layer105of a gate pattern comes into contact with a control gate layer can be increased and so the coupling ratio between them can be improved. Furthermore, the top surface of the isolation structures is preferably controlled to be higher than a top surface of the tunnel insulating layers103in order to prevent a leakage current from being generated because of the exposed active regions A.

As a result of the etch process for forming the isolation structures with the appropriate EFH, the charge trap layers105protrude from the isolation structures and thus sidewalls on the upper side of the charge trap layer105are exposed, while sidewalls on the lower side of the charge trap layer105are shielded by the isolation structures.

Referring toFIG. 1B, a process for reducing the width of the upper side of the charge trap layer105, protruding from the isolation structure, (i.e., the first width W1, hereinafter referred to as a stop width'), to a second width W2smaller than the first width W1can be further performed. In this process, space between the patterned charge trap layers105is widened so that the space is not filled with a dielectric layer in a subsequent process and so a conductive layer for a control gate is formed therein.

In order to reduce the top width of the charge trap layer105, the exposed surface of the top side of the charge trap layers105can be oxidized to a predetermined thickness. Accordingly, an oxide layer111is formed on the exposed surface of the charge trap layer105, and the top width of the charge trap layer105becomes the second width W2, which is narrower than the first width W1.

Referring toFIG. 1C, the oxide layers111are removed by using a wet cleaning process, thereby exposing the charge trap layers105.

Referring toFIG. 1D, a compensation layer113is formed over the exposed charge trap layers105and the isolation layers109. The compensation layer113preferably includes second impurity ions which are the same kind as the first impurity ions included in the charge trap layers105. Furthermore, the compensation layer113preferably includes the second impurity ions having a concentration higher than that of the first impurity ions included in the charge trap layer105.

That is, in case where n type (i.e., a 3-valence) impurity ions are included in the charge trap layer105, the compensation layer113also includes the n type impurity ions, but the n type impurity ions in the compensation layer113preferably have a higher concentration than that in the charge trap layer105. For example, in case where phosphorous (P) is included in the charge trap layer105, the compensation layer113can be formed of a Phospho Silicate Glass (PSG) oxide layer of a solid solution state, having a higher concentration of phosphorous (P) than the charge trap layer105.

The above PSG oxide layer can be formed through a deposition process using an Atmospheric Pressure Chemical Vapor Deposition (APCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Low Pressure Chemical Vapor Deposition (LPCVD) method. Furthermore, the PSG oxide layer can be formed using silicon (Si) source gas, source gas including impurity ions, and oxygen. For example, the PSG oxide layer (SiO2P2O5) can be formed by using the silicon (Si) source gas of TEOS (Tetraethyl orthosilicate: Si(OC2H5)4), the source gas including an n type impurity ion, such as P(OCH3)3or TMOP (Trimethyl Phosphate: PH3), and O3. The PSG oxide layer preferably includes phosphorous (P) of 1 wt % or higher. The PSG oxide layer preferably has a thickness of 5 Å or more. The temperature for forming the PSG oxide layer is preferably 25° C. Also, the pressure for forming the PSG oxide layer is preferably 10 torr or higher. However, the concentration of impurity ions included in the PSG oxide layer and the temperature and pressure for forming the PSG layer can be set in various ways depending on the step coverage characteristic of the PSG oxide layer and the amount of impurity ions to be diffused into the charge trap layer105in a subsequent process.

Meanwhile, where p type (i.e., a 5-valence) impurity ions, such as boron (B), are included in the charge trap layer105, the compensation layer113can be formed of a Boron Silicate Glass (BSG) oxide layer, including a higher concentration of boron (B) than the charge trap layer105.

Referring toFIG. 1E, the second impurity ions within the compensation layer113are diffused toward the charge trap layers105. The diffusion can be performed through an annealing process, such as a furnace process or a Rapid Thermal Process (RTP). During the diffusion process, temperature can be set in the range of 100° C. to 1000° C., preferably set to 780′C, so that the second impurity ions within the compensation layer113can be diffused toward the charge trap layers105.

The second impurity ions within the compensation layer113are diffused and added to the charge trap layers105. As the second impurity ions are added to the charge trap layer105, they compensate for the lack of first impurity ions of the charge trap layer105, which are lost after the charge trap layer105are formed.

As a result of the process of reducing the top width of the charge trap layer105as shown inFIGS. 1B and 1C, the concentration of the first impurity ions included in the charge trap layer105can be greatly lowered for reasons described below.

In general, the first impurity ions included in the charge trap layer105are gathered on a surface of the charge trap layer105because of heat generated during the process. Therefore, if the first impurity ions gathered on the surface of the charge trap layer105are removed by oxidizing the surface of the top side of the charge trap layer105as shown inFIGS. 1B and 1C, the concentration of the first impurity ions doped into the charge trap layer105becomes very low. In the first exemplary embodiment of this disclosure, as described above, the top width of the charge trap layer105is reduced, and the second impurity ions of the compensation layer113are then diffused into the charge trap layer105. Accordingly, the concentration of the first impurity ions of the charge trap layer105, lowered in the process of reducing the top width of the charge trap layer105, can be compensated for.

As described above, in an exemplary embodiment of this disclosure, impurity ions are added to the charge trap layers105by using not an ion implantation process, but a diffusion process. Accordingly, a shift in the threshold voltage Vt of a channel can be prevented because the impurity ions are concentrated to the edges of the active regions A by the ion implantation process.

Referring toFIG. 1F, after performing the diffusion process, the compensation layer113is removed to expose the charge trap layers105and the isolation layers109.

Referring toFIG. 1G, a dielectric layer115is formed on the exposed top surfaces and sidewalls of the charge trap layers105and the exposed top surfaces of the isolation layers109. The dielectric layer115can be formed of a stack layer of an oxide layer, a nitride layer, and an oxide layer or can be formed of a high-k layer, such as an Al2O3layer, a ZrO2layer, an HfO2layer, or a stack layer of them.

Meanwhile, the dielectric layer115is formed in the state in which the top width of the charge trap layer105is reduced though processes described inFIGS. 1B and 1C, and a gap between the charge trap layers105becomes wider than that at the previous process, i.e., inFIG. 1A. Accordingly, the dielectric layers115formed on the sidewalls of the charge trap layers105can be spaced apart from one another.

Referring toFIG. 1H, a conductive layer121for a control gate is formed over the dielectric layers115. The conductive layer121can be formed of a polysilicon layer into which impurities are doped, a stack layer of a polysilicon layer and a metal silicide layer, or a stack layer of a polysilicon layer and a metal layer.

The conductive layer121is formed to fill the space between the sidewalk of the charge trap layers105. The reason why the conductive layer121can be formed in the space between the sidewalls of the charge trap layers105is that the dielectric layers115formed on the sidewalls of the charge trap layers105are spaced apart from one another.

In the first exemplary embodiment of this disclosure, impurity ions within the compensation layer113are diffused into the charge trap layers105by means of the compensation layer113, including the impurity ions having a higher concentration than impurity ions within the charge trap layers105. Accordingly, a concentration of the impurity ions included in the charge trap layers105can be increased. Consequently, in an exemplary embodiment, the deterioration of a distribution characteristic with respect to threshold voltages of a NAND flash memory device and occurrence of a read operation failure because the concentration of the impurity ions within the charge trap layers105is lowered, can be prevented.

Meanwhile, in the first exemplary embodiment of this disclosure, impurity ions are added to the charge trap layers105by using a diffusion process, not an ion implantation process. Accordingly, the threshold voltage Vt of a channel can be prevented from shifting due to the impurity ions concentrated to the edges of the active regions A by the ion implantation process.

FIGS. 2A to 2Care cross-sectional views illustrating a method of forming the patterns of a nonvolatile memory device according to a second exemplary embodiment of this disclosure. In particular, a method of manufacturing a semiconductor memory device, for example, a NAND flash memory device, is described below with reference toFIGS. 2A to 2C.

Referring toFIG. 2A, there is provided a semiconductor substrate201, including active regions A and isolation regions. Trenches207and isolation insulation layers209are formed in the respective isolation regions of the semiconductor substrate201. Furthermore, a tunnel insulating layer203and a charge trap layer205, including first impurity ions of a first concentration, are patterned to be formed with a first width W1over the respective active regions A of the semiconductor substrate201which are spaced apart from one another by the trenches207and the isolation insulation layers209.

A method of forming the trenches207and the isolation insulation layers209and a method of patterning the tunnel insulating layer203and the charge trap layer205are the same as those ofFIG. 1A, and so descriptions thereof are omitted below.

Meanwhile, the isolation insulation layers209are etched by an etch process, such as etch-back, thereby forming isolation structures having a controlled Effective Field Height (EFH). Here, a top surface of the isolation structures is preferably controlled to be lower than a top surface of the charge trap layers205such that the area where the charge trap layer205of a gate pattern comes into contact with a control gate layer can be increased and so the coupling ratio between the charge trap layer205and the control gate layer can be improved. Furthermore, the top surface of the isolation structures is preferably controlled to be higher than a top surface of the tunnel insulating layers203in order to prevent a leakage current from being generated because of the exposed active regions A.

As a result of the etch process for forming the isolation structures with the appropriate EFH, sidewalls on the upper side of the charge trap layer205, protruding from the isolation structure, are exposed, but sidewalls on the lower side of the charge trap layer205are shielded by the isolation structures.

Next, a process for reducing the width of the upper side (hereinafter referred to as a ‘top width’) of the charge trap layer205, protruding from the isolation structure, to a second width W2smaller than the first width W1can be further performed. The above process can be performed by using the same method as described with reference toFIGS. 1B and 1C. Next, a first dielectric layer213is formed on the exposed top surfaces and sidewalls of the charge trap layers205and the top surfaces of the isolation insulation layers209. The first dielectric layer213preferably includes 3-valence or 5-valence second impurity ions which are the same kind as the first impurity ions included in the charge trap layers205. Furthermore, the first dielectric layer213preferably is formed of a compensation layer, including the second impurity ions having a second concentration higher than the first concentration of the first impurity ions included in the charge trap layers205.

That is, where n type (i.e., a 3-valence) impurity ions are doped into the charge trap layers205, a concentration of the n type impurity ions included in the first dielectric layer213is higher than a concentration of impurity ions included in the charge trap layers205. For example, where phosphorous (P) is doped into the charge trap layers205, the first dielectric layer213can be formed of a Phospho Silicate Glass (PSG) oxide layer of a solid solution state into which phosphorous (P), having a higher concentration than phosphorous (P) doped into the charge trap layers205, has been doped. A method of forming the PSG oxide layer is the same as that described with reference toFIG. 1D, and thus, a description thereof is omitted below.

Alternatively, where p type (i.e., a 5-valence) impurity ions, such as boron (B), are included in the charge trap layers205, the first dielectric layer213can be formed of a Boron Silicate Glass (BSG) oxide layer, including a higher concentration of boron (B) than the charge trap layers205. Next, the second impurity ions included in the first dielectric layer213are diffused toward the charge trap layers205. The diffusion can be performed through an annealing process, such as a furnace process or a Rapid Thermal Process (RTP). During the diffusion process, temperature can be set in the range of 100° C. to 1000° C., but is preferably set to 780° C., so that the second impurity ions within the first dielectric layer213can be diffused toward the charge trap layers205.

The second impurity ions of the first dielectric layer213are diffused toward the charge trap layers205and added thereto. Accordingly, in the second exemplary embodiment of this disclosure, although the first impurity ions included in the charge trap layers205are externally discharged and lost after forming the charge trap layers205, the loss of the first impurity ions of the charge trap layers205can be compensated for by the second impurity ions.

Meanwhile, in the process of reducing the top width of the charge trap layer205, the first impurity ions gathered on the surfaces of the charge trap layer205can be lost. In the second exemplary embodiment of this disclosure, after reducing the top width of the charge trap layer205, the second impurity ions within the first dielectric layer213are diffused into the charge trap layer205. Accordingly, the first impurity ions of the charge trap layer205, lost in the process of reducing the top width of the charge trap layer205, can be compensated for.

Furthermore, in the second exemplary embodiment of this disclosure, impurity ions are added to the charge trap layers205by using not an ion implantation process, but a diffusion process. Accordingly, the threshold voltage Vt of a channel can be prevented from shifting due to the impurity ions concentrated to the edges of the active regions A by the ion implantation process.

Referring toFIG. 2B, after performing the diffusion process, a second dielectric layer215formed of a nitride layer and a third dielectric layer217formed of an oxide layer are formed over the first dielectric layer213. Thus, a dielectric layer219, having an Oxide/Nitride/Oxide (ONO) stack structure including the oxide layer, the nitride layer, and the oxide layer, is formed.

Referring toFIG. 2C, after forming the dielectric layer219, a conductive layer221for a control gate is formed over the dielectric layer219. The conductive layer221can be formed of a polysilicon layer into which impurities are doped, a stack layer of a polysilicon layer and a metal silicide layer, or a stack layer of a polysilicon layer and a metal layer.

In the second exemplary embodiment of this disclosure, impurity ions within the first dielectric layer213are diffused into the charge trap layers205by means of the first dielectric layer213, including the impurity ions having a higher concentration than impurity ions within the charge trap layers205. Accordingly, the concentration of the impurity ions within the charge trap layers205can be increased. Consequently, in an exemplary embodiment, the deterioration of a distribution characteristic with respect to threshold voltages of a NAND flash memory device and occurrence of a read operation failure because the concentration of the impurity ions within the charge trap layers205is lowered, can be prevented.

Meanwhile, in the second exemplary embodiment of this disclosure, impurity ions are added to the charge trap layers205by using a diffusion process, not an ion implantation process. Accordingly, the threshold voltage Vt of a channel can be prevented from shifting due to the impurity ions concentrated to the edges of the active regions A by the ion implantation process.

Furthermore, in the second exemplary embodiment of this disclosure, the first dielectric layer213(i.e., the lowest layer of the ONO structure) is made of materials which can be used to compensate the concentration of impurity ions included in the charge trap layers205. Accordingly, the process can be simplified, as compared with the first exemplary embodiment, because there is no need to have an additional process for forming the compensation layer.

FIGS. 3A to 3Care cross-sectional views illustrating a method of forming the patterns of a nonvolatile memory device according to a third exemplary embodiment of this disclosure. In particular, a method of manufacturing a NAND flash memory device is described below as an example with reference toFIGS. 3A to 3C.

Referring toFIG. 3A, there is provided a semiconductor substrate301, including active regions A and isolation regions. Trenches307and isolation insulation layers309are formed in the respective isolation regions of the semiconductor substrate301. Furthermore, a tunnel insulating layer303and a charge trap layer305, including first impurity ions of a first concentration, are patterned to be formed with a first width W1over the active regions A of the semiconductor substrate301, spaced apart from one another by the trenches307and the isolation insulation layers309.

A method of forming the trenches307and the isolation insulation layers309and a method of patterning the tunnel insulating layer303and the charge trap layer305are the same as those ofFIG. 1A, and so descriptions thereof are omitted below.

Meanwhile, the isolation insulation layers309are etched by an etch process, such as etch-back, thereby forming isolation structures having a controlled Effective Field Height (EFH). Here, a top surface of the isolation structures is preferably controlled to be lower than a top surface of the charge trap layers305such that the area where the charge trap layer305of a gate pattern comes into contact with a control gate layer can be increased and so the coupling ratio between them can be improved. Furthermore, the top surface of the isolation structures is preferably controlled to be higher than a top surface of the tunnel insulating layers303in order to prevent a leakage current from being generated because of the exposed active regions A.

As a result of the etch process for forming the isolation structures with the appropriate EFH, sidewalls on the upper side of the charge trap layer305, protruding from the isolation structure, are exposed, while sidewalls on the lower side of the charge trap layer305are shielded by the isolation structures.

Next, a process for reducing the width of the upper side (hereinafter referred to as a ‘top width’) of the charge trap layer305, protruding from the isolation structure, to a second width W2smaller than the first width W1and a process of forming a compensation layer313can be performed at the same time.

The compensation layer313preferably includes 3-valence or 5-valence second impurity ions which are the same kind as the first impurity ions included in the charge trap layers305. Furthermore, the compensation layer313preferably includes the second impurity ions having a second concentration higher than the first concentration of the first impurity ions included in the charge trap layers305.

That is, in case where n type (i.e., a 3-valence) impurity ions are doped into the charge trap layers305, a concentration of the n type impurity ions included in the compensation layer313is preferably higher than a concentration of impurity ions included in the charge trap layers305. For example, where phosphorous (P) is doped into the charge trap layers305, the compensation layers313can be formed of a Phospho Silicate Glass (PSG) oxide layer of a solid solution state into which phosphorous (P), having a higher concentration than phosphorous (P) doped into the charge trap layers305, has been doped. A method of forming the PSG oxide layer is the same as that described with reference toFIG. 1D, and thus, a description thereof is omitted below. Alternatively, where p type (i.e., a 5-valence) impurity ions, such as boron (B), are included in the charge trap layers305, the compensation layer313can be formed of a Boron Silicate Glass (BSG) oxide layer, including a higher concentration of boron (B) than the charge trap layers305.

In the process of forming the PSG oxide layer, the top surface and sidewalls of the charge trap layers305, protruding from the isolation layers309, can be oxidized. Accordingly, although an additional oxidization process for reducing the top width of the charge trap layer305to the second width W2smaller than the first width W1is not performed, the top width of the charge trap layer305can be narrowed to the second width W2through the process of forming the compensation layer313.

Referring toFIG. 3B, the second impurity ions included in the compensation layer313are diffused toward the charge trap layers305. The diffusion can be performed through an annealing process, such as a furnace process or a Rapid Thermal Process (RTP). During the diffusion process, the temperature can be set in the range of 100° C. to 1000° C., and is preferably set to 780° C., so that the second impurity ions within the compensation layer313can be diffused toward the charge trap layers305.

The second impurity ions of the compensation layer313are diffused toward the charge trap layers305and added thereto. Accordingly, in the third exemplary embodiment of this disclosure, although the first impurity ions included in the charge trap layers305are externally discharged and lost after forming the charge trap layers305, the lost first impurity ions of the charge trap layers305can be compensated for by the second impurity ions.

Furthermore, in the third exemplary embodiment of this disclosure, impurity ions are added to the charge trap layers305by using not an ion implantation process, but a diffusion process. Accordingly, the threshold voltage Vt of a channel can be prevented from shifting due to the impurity ions concentrated to the edges of the active regions A by the ion implantation process.

Referring toFIG. 3C, after performing the diffusion process, the compensation layer313is removed to expose the charge trap layers305and the isolation layers309.

Next, a dielectric layer315is formed on the exposed top surface and sidewalls of the charge trap layers305and the exposed top surface of the isolation layers309. The dielectric layer315can be formed of a stack layer of an oxide layer, a nitride layer, and an oxide layer or can be formed of a high-k layer, such as an Al2O3layer, a ZrO2layer, an HfO2layer, or a stack layer of them.

Meanwhile, the dielectric layer315is formed in the state in which the top width of the charge trap layer305is reduced, and so the gap between the patterned top surfaces of the charge trap layers305is widened. Accordingly, the dielectric layers315formed on the sidewalls of the charge trap layers305can be spaced apart from one another.

Next, a conductive layer321for a control gate is formed over the dielectric layers315. The conductive layer121can be formed of a polysilicon layer into which impurities are doped, a stack layer of a polysilicon layer and a metal silicide layer, or a stack layer of a polysilicon layer and a metal layer.

The conductive layer321is formed to fill the space between the patterned charge trap layers305. The reason why the conductive layer321can be formed in the space between the charge trap layers305is that the dielectric layer315formed on the sidewalls of the charge trap layer105are spaced apart from one another.

Although not shown, in the third exemplary embodiment of this disclosure, the compensation layer can be used as the lowest layer of an ONO structure.

In accordance with an exemplary embodiment of this disclosure, impurity ions within the compensation layer are diffused into the charge trap layers, thus compensating for impurity ions lost in the charge trap layers. Accordingly, the deterioration of a distribution characteristic with respect to threshold voltages of a device and the occurrence of a read operation failure because a concentration of the impurity ions within the charge trap layers is lowered, can be prevented.

Furthermore, in accordance with an exemplary embodiment of the present disclosure, impurity ions are added to the charge trap layers by using a diffusion process, not an ion implantation process. Accordingly, the threshold voltage of a channel can be prevented from shifting due to the impurity ions concentrated to the edges of the active regions by the ion implantation process.