Vector instruction for accumulating and compressing values based on input mask

A processor includes a decode circuit to decode an instruction into a decoded instruction and an execution circuit to execute the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block.

TECHNICAL FIELD

Embodiments of the invention relate to the field of computer instruction set architecture; and more specifically, to vector instructions for accumulating and compressing values based on an input mask.

BACKGROUND

A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction as used herein generally refers to a macro-instruction (e.g., an instruction that is provided to the processor for execution), as opposed to a micro-instruction (e.g., an instruction that results from a processor's decoder decoding macro-instructions).

Modern processors often include instructions to provide operations that are computationally intensive, but offer a high level of data parallelism that can be exploited through an efficient implementation using various data storage devices, such as for example, single-instruction multiple-data (SIMD) vector registers. In SIMD execution, a single instruction operates on multiple data elements concurrently or simultaneously. This is typically implemented by extending the width of various resources such as registers and arithmetic logic units (ALUs), allowing them to hold and operate on multiple data elements, respectively.

Run-length encoding is a simple form of lossless data compression in which “runs” of data (e.g., sequences in which the same data value occurs in multiple consecutive data elements) are stored as a single data value and a corresponding count. For example, run-length encoding may compress the sequence “AAAAABBBCCDDDDDDDEEEE” to “A5B3C2D7E4”. This can also be encoded as a sequence of values and a sequence of corresponding counts (e.g., “ABCDE” and “53274”). Run-length encoding can be vectorized with SIMD execution. However, conventional techniques for performing vectorized run-length encoding may only produce the correct result for certain sequences and/or may be inefficient.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail to not obscure the understanding of this description.

FIG. 1is a block diagram illustrating a hardware processor and a memory for executing instructions, according to some embodiments. Depicted hardware processor100includes a hardware decoder102(e.g., decode unit or decode circuit) and a hardware execution unit104(e.g., execution circuit). Depicted hardware processor100includes register(s)106. Registers106may include one or more registers to perform operations in, e.g., additionally or alternatively to access of (e.g., load or store) data in memory110. Note that the figures herein may not depict all data communication connections. One of ordinary skill in the art will appreciate that this is to not obscure certain details in the figures. Note that a double headed arrow in the figures may not require two-way communication. For example, it may indicate one-way communication (e.g., to or from that component or device). Any or all combinations of communications paths may be utilized in certain embodiments herein.

Hardware decoder102may receive an instruction (e.g., macro-instruction) and decode the instruction (e.g., into micro-instructions and/or micro-operations). Execution unit104may execute the decoded instruction to perform one or more operations. The decoder102and the execution unit104may decode and execute any of the instructions disclosed herein (e.g., instructions disclosed with reference toFIGS. 1-9). Certain embodiments disclosed herein introduce a vector accumulation instruction that can be decoded and executed by the decoder102and execution unit104, respectively. Certain embodiments disclosed herein introduce a vector accumulation and compression instruction that can be decoded and executed by the decoder102and execution unit104, respectively. As will be described in additional detail below, these instructions may be utilized to perform vectorized run-length encoding for vectors.

Run-length encoding is a simple form of lossless data compression in which “runs” of data (e.g., sequences in which the same data value occurs in multiple consecutive data elements) are stored as a single data value and a corresponding count. For example, run-length encoding may compress the sequence “AAAAABBBCCDDDDDDDEEEE” to “A5B3C2D7E4”. This can also be encoded as a sequence of values and a sequence of corresponding counts (e.g., “ABCDE” and “53274”).

According to conventional techniques, the following sequence of instructions may be executed to perform vectorized run-length encoding for an input vector ZMM_VALUE:(1) ZMM1=VCONFLICT_SQR(ZMM_VALUE);(2) ZMM2=VPAND(ZMM1, ZMM_MASK);(3) K1=VPTESTNM(ZMM2);(4) ZMM_VAL=VCOMPRESS(K1, ZMM_VALUE);(5) ZMM_COUNT=VPOPCNT(ZMM1);(6) ZMM_CNT1=VCOMPRESS(K1, ZMM_COUNT);

In the above sequence of instructions, ZMM_VALUE is the vector containing the sequence of values that is to be compressed (the input vector) and ZMM_MASK is a predefined (constant) mask that masks out bits from the output of the VCONFLICT_SQR instruction. In the above sequence of instructions, (1) is an instruction to perform a square conflict operation (e.g., take an element of an input vector and compare it to all other elements of the input vector; and repeat the same for all elements of the input vector). In the above sequence of instructions, (2) is an instruction to perform a bitwise logical AND operation. In the above sequence of instructions, (3) is an instruction to perform a vector packed test for zero (e.g., if element is zero, then mask bit corresponding to element is set to 1; if element is non-zero, then mask bit corresponding to element is set to 0). In the above sequence of instructions, (4) is an instruction to perform vector compression. In the above sequence of instructions, (5) is an instruction to perform vector population count (e.g., count number of bits set to binary ‘1’). In the above sequence of instructions, (6) is an instruction to perform vector compression.

FIG. 2is a diagram illustrating a sequence of instructions being executed to perform vectorized run-length encoding using a left-border compression mask, according to conventional techniques. In the figures, each vertical column represents bit positions of the same lane of a vector register. The “offset” refers to the position of an element. In this example and other examples provided herein, there are eight (KL=8) elements in a vector. The values and sizes of the input vector and other vectors are provided by way of example for purposes of illustration. It should be understood that other values and sizes may be utilized. ZMM_VALUE is the vector containing the sequence of values that is to be compressed (the input vector). In this example, ZMM_VALUE contains the sequence of values “AAABBCCD” (from least significant bit (LSB) to most significant bit (MSB)). Executing the VCONFLICT_SQR(ZMM_VALUE) instruction produces ZMM1. ZMM_MASK_LEFT is a predefined left-border compression mask. Executing the VPAND(ZMM1, ZMM_MASK_LEFT) instruction produces ZMM2. Executing the VPTESTNM(ZMM2) instruction produces K1. Executing the VCOMPRESS(K1, ZMM_VALUE) instruction produces ZMM_VAL1. Executing the VPOPCNT(ZMM1) instruction produces ZMM_COUNT. Executing the VCOMPRESS(K1, ZMM_COUNT) instruction produces ZMM_CNT1. As a result, ZMM_VAL1contains the sequence of values “ABCD” and ZMM_CNT1 contains the sequence of corresponding counts “3221”, which is the compressed form of the original sequence of values “AAABBCCD” contained in ZMM_VALUE.

FIG. 3is a diagram illustrating a sequence of instructions being executed to perform vectorized run-length encoding using a right-border compression mask, according to conventional techniques. As shown inFIG. 3, the same sequence of instructions mentioned above with reference toFIG. 2can be executed with a right-border compression mask (e.g., ZMM_MASK_RIGHT) instead of a left-border compression mask (e.g., ZMM_MASK_LEFT) to produce the same result.

The conventional techniques described above produce the correct result when all of the runs contained in the input vector (e.g., ZMM_VALUE) have unique values. However, if there are any duplicated runs contained in the input vector (e.g., the input vector contains at least two runs that have the same value), then the VCONFLICT_SQR instruction produces additional binary ‘1’s that appear outside of the diagonal blocks, which causes the VPOPCNT instruction to produce an incorrect sequence of counts in ZMM_COUNT (although, it should be noted that the conventional techniques still produce the correct sequence of values in ZMM_VAL1).

FIG. 4is a diagram illustrating a sequence of instructions being executed to perform vectorized run-length encoding that produces an incorrect result due to the input vector containing duplicated runs, according to conventional techniques. In this example, ZMM_VALUE (the input vector) contains the sequence of values “AAABBAAB” (from LSB to most MSB). ZMM_VALUE thus contains duplicated runs. For example, ZMM_VALUE contains two runs having value “A” (run “AAA” and run “AA”) and two runs having value “B” (run “BB” and run “B”). As a result, the VCONFLICT_SQR instruction produces additional binary ‘1’s that appear outside of the diagonal blocks, which causes the VPOPCNT instruction to produce an incorrect sequence of counts in ZMM_COUNT. In this example, ZMM_VAL1contains the correct sequence of values (“ABAB”). However, ZMM_COUNT contains an incorrect sequence of counts (“5353”) (the correct sequence of counts is “3221”).

As can be seen from the example described above, conventional techniques for performing vectorized run-length encoding are not applicable for arbitrary input vectors. The conventional techniques are only applicable when all of the runs contained in the input vector have unique values. If the input vector contains any duplicated runs, then the input vector needs to be processed in a scalar manner or split into blocks that do not contain duplicated runs, after which conventional techniques can be applied. This requires additional overhead to perform dynamic checks and/or serialization, which degrades performance. Certain embodiments disclosed herein overcome the disadvantages of the conventional techniques by providing a vector accumulation instruction that can be utilized to perform run-length encoding for arbitrary input vectors (and not just for input vectors where all of the runs have unique values).

In one embodiment, a vector accumulation instruction has the following definition:

VMASKREDUCTION_R{B, W, D, Q} dest{k1}, src(KL, VL) = (64, 512), (32, 512), (16, 512), (8, 512) // where KL is thenumber of elements in the source/destination vector and VL is the vectorlengthtmp = 0 // temporary scalar accumulatorfor (i = KL − 1; i >= 0; i−−) {tmp += src[i]if (k1[i]) {dest[i] = tmptmp = 0}}
In this instruction, {B, W, D, Q} indicates the size of supported elements (e.g., byte (B), word (W), doubleword (D), and quadword (Q). In this instruction, {k1} indicates the input mask. In one embodiment, operation of this instruction may be described as follows: in a loop going through all KL elements of a source operand, cumulatively add the value of each element and store it in a temporary scalar accumulator (e.g., tmp) until the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’). If the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’), then store the value of the temporary scalar accumulator in the corresponding element of the destination operand and reset the value of the temporary scalar accumulator. With this instruction, the elements of the source operand are processed from left to right (e.g., MSB to LSB) and the value of the temporary scalar accumulator is stored in the destination operand when a non-zero value is encountered in the corresponding bit of the input mask. The input mask effectively dictates how to divide the source operand (e.g., an input vector) into blocks of contiguous elements. When the elements of the source operand are processed from left to right, the input mask indicates the right border of each block. The values contained in each block are summed to produce an accumulated value for that block, which is stored in the destination operand.

In one embodiment, a vector accumulation instruction has the following definition:

VMASKREDUCTION_L{B, W, D, Q} dest{k1}, src(KL, VL) = (64, 512), (32, 512), (16, 512), (8, 512) // where KL is thenumber of elements in the source/destination vector and VL is the vectorlengthtmp = 0 // temporary scalar accumulatorfor (i = 0; i < KL; i++) {tmp += src[i]if (k1[i]) {dest[i] = tmptmp = 0}}
In this instruction, {B, W, D, Q} indicates the size of supported elements (e.g., byte (B), word (W), doubleword (D), and quadword (Q). In this instruction, {k1} indicates the input mask. In one embodiment, the operation of this instruction may be described as follows: in a loop going through all KL elements of a source operand, cumulatively add the value of each element and store it in a temporary scalar accumulator (e.g., tmp) until the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’). If the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’), then store the value of the temporary scalar accumulator in the corresponding element of the destination operand and reset the value of the temporary scalar accumulator. With this instruction, the elements of the source operand are processed from right to left (e.g., LSB to MSB) and the value of the temporary scalar accumulator is stored in the destination operand when a non-zero value is encountered in the corresponding bit of the input mask. The input mask effectively dictates how to divide the source operand (e.g., an input vector) into blocks of contiguous elements. When the elements of the source operand are processed from right to left, the input mask indicates the left border of each block. The values contained in each block are summed to produce an accumulated value for that block, which is stored in the destination operand.

FIG. 5is a diagram illustrating a hardware processor that decodes and executes a vector accumulation instruction, according to some embodiments. Vector accumulation instruction500may be decoded by the decoder102and executed by the execution unit104. Data may be accessed in register(s)106and/or memory110. The vector accumulation instruction500may take an input mask (e.g., K1) and an input vector (e.g., ZMM ALL_1S) as operands. In this example, the input mask indicates the left border of each block. According to the input mask, the elements at positions2,4,6, and7, are the left borders of the respective blocks. As such, elements at positions0-2are grouped as a block, with the element at position2being the left border of the block. Elements at positions3and4are grouped as a block, with the element at position4being the left border of the block. Elements at positions5and6are grouped as a block, with the element at position6being the left border of the block. The element at position7is a block (with a single element), with this element also being the left border of the block. In this example, the input vector contains all binary ‘1’s. In one embodiment, the execution unit104executes the vector accumulation instruction500(e.g., VMASKREDUCTION_L) to cause the elements of the destination vector (e.g., ZMM_COUNT) corresponding to the left border of each block (as indicated by the input mask) to be populated with an accumulated value for that block. The accumulated value for a block is a sum of the values of the elements within the block. In this example, the element at position2of the destination vector has a value of ‘3’, the element at position4of the destination vector has a value of ‘2’, the element at position6of the destination vector has a value of ‘2’, and the element at position7of the destination vector has a value of ‘1’. Other elements of the destination vector (positions0,1,3, and5) may be undefined. In one embodiment, they may be set to zero or remain unchanged depending on the masking mode of the instruction. In the diagram, they are shown as being set to zero.

The following sequence of instruction may be executed to perform vectorized run-length encoding for an input vector ZMM_VALUE:(1) ZMM1=VCONFLICT SQR(ZMM_VALUE);(2) ZMM2=VPAND(ZMM1, ZMM_MASK);(3) K1=VPTESTNM(ZMM2);(4) ZMM_VAL1=VCOMPRESS(K1, ZMM_VALUE);(5) ZMM_COUNT=VMASKREDUCTION L(K1, ZMM_ALL_1S);(6) ZMM_CNT1=VCOMPRESS(K1, ZMM_COUNT);
In the above sequence of instructions, ZMM_VALUE is the vector containing the sequence of values that is to be compressed (the input vector). In the above sequence of instructions, ZMM_MASK is a predefined (constant) mask that masks out bits from the output of the VCONFLICT_SQR instruction. In the above sequence of instructions, ZMM_ALL_1S is a predefined vector containing all binary ‘1’s. In the above sequence of instructions, (1) is an instruction to perform a square conflict operation (e.g., take an element of an input vector and compare it to all other elements of the input vector; and repeat the same for all elements of the input vector). In the above sequence of instructions, (2) is an instruction to perform a bitwise logical AND operation. In the above sequence of instructions, (3) is an instruction to perform a vector packed test for zero. In the above sequence of instructions, (4) is an instruction to perform vector compression. In the above sequence of instructions, (5) is an instruction to perform vector accumulation. In the above sequence of instructions, (6) is an instruction to perform vector compression.

FIG. 6is a diagram illustrating a sequence of instructions being executed to perform vectorized run-length encoding for a vector containing duplicated runs using a left-border compression mask, according to some embodiments. In this example, ZMM_VALUE (the input vector) contains the sequence of values “AAABBAAB” (from LSB to MSB). It is to be noted that the conventional techniques for performing vectorized run-length encoding described above produced an incorrect result for this particular sequence of values (as illustrated inFIG. 4). The sequence of instructions described herein below, which utilizes a vector accumulation instruction (e.g., VMASKREDUCTION_L), however, produces the correct result for arbitrary input vectors (even when the input vector contains duplicated runs).

Executing the VCONFLICT_SQR(ZMM_VALUE) instruction produces ZMM1. ZMM_MASK_LEFT is a predefined left-border compression mask. Executing the VPAND(ZMM1, ZMM_MASK_LEFT) instruction produces ZMM2. Executing the VPTESTNM(ZMM2) instruction produces K1. Executing the VCOMPRESS(K1, ZMM_VALUE) instruction produces ZMM_VAL1. Executing the VMASKREDUCTION_L(K1, ZMM_ALL_1S) instruction produces ZMM_COUNT. Executing the VCOMPRESS(K1, ZMM_COUNT) instruction produces ZMM_CNT1. As a result, ZMM_VAL1contains the sequence of values “ABAB” and ZMM_CNT1contains the sequence of corresponding counts “3221”, which is the compressed form of the original sequence of values “AAABBAAB” contained in ZMM_VALUE. It should be noted that vectorized run-length encoding can be performed using a right-border compression mask (e.g., ZMM MASK RIGHT) instead of a left-border compression mask to produce the same result. In this case, the VMASKREDUCTION_R instruction is executed in place of the VMASKREDUCTION_L instruction.

In one embodiment, the vector accumulation and compression can be performed by a single instruction, referred to herein as a vector accumulation and compression instruction. In one embodiment, a vector accumulation and compression instruction has the following definition:

VMASKREDUCTIONCOMP_L{B, W, D, Q} dest{k1}, src(KL, VL) = (64, 512), (32, 512), (16, 512), (8, 512) // where KL is thenumber of elements in the source/destination vector and VL is the vectorlengthtmp = 0 // temporary scalar accumulatorn = 0 // starting position in destinationfor (i = 0; i < KL; i++) {tmp += src[i]if (k1[i]) {dest[n] = tmpn++tmp = 0}}
In this instruction, {B, W, D, Q} indicates the size of supported elements (e.g., byte (B), word (W), doubleword (D), and quadword (Q). In this instruction, {k1} indicates the input mask. In one embodiment, operation of this instruction may be described as follows: in a loop going through all KL elements of a source operand, cumulatively add the value of each element and store it in a temporary scalar accumulator (e.g., tmp) until the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’). If the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’), then store the value of the temporary scalar accumulator in the element at the current position (e.g., n) in the destination operand, update the current position (e.g., increment n), and reset the value of the temporary scalar accumulator. With this instruction, the elements of the source operand are processed from right to left (e.g., LSB to MSB) and the value of the temporary scalar accumulator is stored in the destination operand in a compressed manner when a non-zero value is encountered in the corresponding bit of the input mask.

In one embodiment, a vector accumulation and compression instruction has the following definition:

VMASKREDUCTIONCOMP_R{B, W, D, Q} dest{k1}, src(KL, VL) = (64, 512), (32, 512), (16, 512), (8, 512) // where KL is thenumber of elements in the source/destination vector and VL is the vectorlengthtmp = 0 // temporary scalar accumulatorn = popcnt(k1) // starting position in destinationfor (i = KL − 1; i >= 0; i−−) {tmp += src[i]if (k1[i]) {dest[n] = tmpn−−tmp = 0}}
In this instruction, {B, W, D, Q} indicates the size of supported elements (e.g., byte (B), word (W), doubleword (D), and quadword (Q). In this instruction, {k1} indicates the input mask. In one embodiment, operation of this instruction may be described as follows: set the current position in the destination operand (e.g., n) to the number of binary ‘1’s in the input mask (e.g., using popcnt instruction). In a loop going through all KL elements of a source operand, cumulatively add the value of each element and store it in a temporary scalar accumulator (e.g., tmp) until the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’). If the corresponding bit of the input mask has a non-zero value (e.g., binary ‘1’), then store the value of the temporary scalar accumulator in the element at the current position (e.g., n) in the destination operand, update the current position (e.g., decrement n), and reset the value of the temporary scalar accumulator. With this instruction, the elements of the source operand are processed from left to right (e.g., MSB to LSB) and the value of the temporary scalar accumulator is stored in the destination operand in a compressed manner when a non-zero value is encountered in the corresponding bit of the input mask.

FIG. 7is a diagram illustrating a hardware processor that decodes and executes a vector accumulation and compression instruction, according to some embodiments. Vector accumulation and compression instruction700may be decoded by the decoder102and executed by the execution unit104. Data may be accessed in register(s)106and/or memory110. The vector accumulation and compression instruction700may take an input mask (e.g., K1) and an input vector (e.g., ZMM_ALL_1S) as operands. In this example, the input mask indicates the left border of each block. According to the input mask, the elements at positions2,4,6, and7, are the left borders of the respective blocks. As such, elements at positions0-2are grouped as a block, with the element at position2being the left border of the block. Elements at positions3and4are grouped as a block, with the element at position4being the left border of the block. Elements at positions5and6are grouped as a block, with the element at position5being the left border of the block. The element at position7is a block (with a single element), with this element also being the left border of the block. In this example, the input vector contains all binary ‘1’s. In one embodiment, the execution unit104executes the vector accumulation and compression instruction (e.g., VMASKREDUCTIONCOMP_L) to cause the elements of the destination vector (e.g., ZMM_CNT1) to be populated with the accumulated values of the respective blocks in a compressed manner. The accumulated value for a block is a sum of the values of the elements within the block. In this example, the element at position0of the destination vector has a value of ‘3’, the element at position I of the destination vector has a value of ‘2’, the element at position2of the destination vector has a value of ‘2’, and the element at position3of the destination vector has a value of ‘1’. The upper elements of the destination vector (positions4-7) are undefined. In one embodiment, they may be set to zero or remain unchanged depending on the masking mode of the instruction.

The following sequence of instruction may be executed to perform vectorized run-length encoding for an input vector ZMM_VALUE:(1) ZMM1=VCONFLICT_SQR(ZMM_VALUE);(2) ZMM2=VPAND(ZMM1, ZMM_MASK);(3) K1=VPTESTNM(ZMM2);(4) ZMM_VAL1=VCOMPRESS(K1, ZMM_VALUE);(5) ZMM_COUNT=VMASKREDUCTIONCOMP_L(K1, ZMM_ALL_1S);

In the above sequence of instructions, ZMM_VALUE is the vector containing the sequence of values that is to be compressed (the input vector). In the above sequence of instructions, ZMM_MASK is a predefined (constant) mask that masks out bits from the output of the VCONFLICT_SQR instruction. In the above sequence of instructions, ZMM_ALL_1S is a predefined vector containing all binary ‘1’s. In the above sequence of instructions, (1) is an instruction to perform a square conflict operation (e.g., take an element of an input vector and compare it to all other elements of the input vector; and repeat the same for all elements of the input vector). In the above sequence of instructions, (2) is an instruction to perform a bitwise logical AND operation. In the above sequence of instructions, (3) is an instruction to perform a vector packed test. In the above sequence of instructions, (4) is an instruction to perform vector compression. In the above sequence of instructions, (5) is an instruction to perform vector accumulation and compression. By combining vector accumulation and vector compression into a single instruction, the number of instructions for performing vectorized run-length encoding can be reduced.

FIG. 8is a diagram illustrating a sequence of instructions being executed to perform vectorized run-length encoding for a vector containing duplicated runs using a left-border compression mask, according to some embodiments. In this example, ZMM_VALUE (the input vector) contains the sequence of values “AAABBAAB” (from LSB to MSB). It is to be noted that the conventional techniques for performing vectorized run-length encoding described above produced an incorrect result for this particular sequence of values (as illustrated inFIG. 4). The sequence of instructions described herein below, which utilizes a vector accumulation and compression instruction (e.g., VMASKREDUCTIONCOMP_L), however, produces the correct result for arbitrary input vectors (even when the input vector contains duplicated runs).

Executing the VCONFLICT_SQR(ZMM_VALUE) instruction produces ZMM1. ZMM_MASK_LEFT is a predefined left-border compression mask. Executing the VPAND(ZMM1, ZMM_MASK_LEFT) instruction produces ZMM2. Executing the VPTESTNM(ZMM2) instruction produces K1. Executing the VCOMPRESS(K1, ZMM_VALUE) instruction produces ZMM_VAL1. ZMM_ALL_1S is a predefined vector containing all binary ‘1’s. Executing the VMASKREDUCTIONCOMP_L(K1, ZMM_ALL_1S) instruction produces ZMM_CNT1. As a result, ZMM_VAL1contains the sequence of values “ABAB” and ZMM_CNT1contains the sequence of corresponding counts “3221”, which is the compressed form of the original sequence of values “AAABBAAB” contained in ZMM_VALUE. It should be noted that vectorized run-length encoding can be performed using a right-border compression mask (e.g., ZMM MASK RIGHT) instead of a left-border compression mask to produce the same result. In this case, the VMASKREDUCTIONCOMP_R instruction is executed in place of the VMASKREDUCTIONCOMP_L instruction.

FIG. 9is a flow diagram of a process for processing a vector accumulation instruction, according to some embodiments. The operations in the flow diagrams will be described with reference to the exemplary embodiments of the other figures. However, it should be understood that the operations of the flow diagrams can be performed by embodiments other than those discussed with reference to the other figures, and the embodiments discussed with reference to these other figures can perform operations different than those discussed with reference to the flow diagrams.

In one embodiment, the process is initiated when a decode circuit102decodes an instruction (e.g., a vector accumulation instruction or a vector accumulation and compression instruction) into a decoded instruction (block910). An execution circuit104executes the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block (block920). In one embodiment, the execution circuit is to also sum one or more values of one or more other contiguous elements of the input vector that form a second block to produce an accumulated value for the second block and store the accumulated value for the second block in the destination vector, where the input mask dictates the one or more other contiguous elements that form the second block. In one embodiment, the execution circuit is to process the one or more contiguous elements of the input vector from left to right (e.g., MSB to LSB). In one embodiment, the execution circuit is to process the one or more contiguous elements of the input vector from right to left (e.g., LSB to MSB). In one embodiment, the input vector is a vector containing all binary ‘1’s. This can be used to count the number of elements in each block. In one embodiment, a bit of the input mask is set to binary ‘1’ to indicate a border of the block. When elements of the input vector are processed from left to right, a bit of the input mask set to binary ‘1’ may indicate the right border of a block. When elements of the input vector are processed from right to left, a bit of the input mask set to binary ‘1’ may indicate the left border of a block. In one embodiment, the execution circuit is to store the accumulated value for the block in an element of the destination vector corresponding to the bit of the input mask that is set to binary ‘1’. In one embodiment, the left or right border of a block may be indicated in the input mask using a binary ‘0’ instead of a binary ‘1’. In one embodiment, the execution circuit is to store the accumulated value for the block in the destination vector in a compressed manner. In one embodiment, the instruction is a VMASKREDUCTION_L or VMASKREDUCTION_R instruction. In one embodiment, the instruction is a VMASKREDUCTIONCOMP_L or VMASKREDUCTIONCOMP_R instruction.

Instruction Sets

Exemplary Instruction Formats

Generic Vector Friendly Instruction Format

FIGS. 10A-10Bare block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention.FIG. 10Ais a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the invention; whileFIG. 10Bis a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the invention. Specifically, a generic vector friendly instruction format1000for which are defined class A and class B instruction templates, both of which include no memory access1005instruction templates and memory access1020instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

The class A instruction templates inFIG. 10Ainclude: 1) within the no memory access1005instruction templates there is shown a no memory access, full round control type operation1010instruction template and a no memory access, data transform type operation1015instruction template; and 2) within the memory access1020instruction templates there is shown a memory access, temporal1025instruction template and a memory access, non-temporal1030instruction template. The class B instruction templates inFIG. 10Binclude: 1) within the no memory access1005instruction templates there is shown a no memory access, write mask control, partial round control type operation1012instruction template and a no memory access, write mask control, vsize type operation1017instruction template; and 2) within the memory access1020instruction templates there is shown a memory access, write mask control1027instruction template.

The generic vector friendly instruction format1000includes the following fields listed below in the order illustrated inFIGS. 10A-10B.

Base operation field1042—its content distinguishes different base operations.

Augmentation operation field1050—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field1068, an alpha field1052, and a beta field1054. The augmentation operation field1050allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field1060—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).

Displacement Field1062A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).

Displacement Factor Field1062B (note that the juxtaposition of displacement field1062A directly over displacement factor field1062B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field1074(described later herein) and the data manipulation field1054C. The displacement field1062A and the displacement factor field1062B are optional in the sense that they are not used for the no memory access1005instruction templates and/or different embodiments may implement only one or none of the two.

Class field1068—its content distinguishes between different classes of instructions. With reference toFIGS. 10A-B, the contents of this field select between class A and class B instructions. InFIGS. 10A-B, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A1068A and class B1068B for the class field1068respectively inFIGS. 10A-B).

Instruction Templates of Class A

In the case of the non-memory access1005instruction templates of class A, the alpha field1052is interpreted as an RS field1052A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round1052A.1and data transform1052A.2are respectively specified for the no memory access, round type operation1010and the no memory access, data transform type operation1015instruction templates), while the beta field1054distinguishes which of the operations of the specified type is to be performed. In the no memory access1005instruction templates, the scale field1060, the displacement field1062A, and the displacement scale filed1062B are not present.

In the no memory access full round control type operation1010instruction template, the beta field1054is interpreted as a round control field1054A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field1054A includes a suppress all floating point exceptions (SAE) field1056and a round operation control field1058, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field1058).

SAE field1056—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's1056content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

In the no memory access data transform type operation1015instruction template, the beta field1054is interpreted as a data transform field1054B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access1020instruction template of class A, the alpha field1052is interpreted as an eviction hint field1052B, whose content distinguishes which one of the eviction hints is to be used (inFIG. 10A, temporal1052B.1and non-temporal1052B.2are respectively specified for the memory access, temporal1025instruction template and the memory access, non-temporal1030instruction template), while the beta field1054is interpreted as a data manipulation field1054C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access1020instruction templates include the scale field1060, and optionally the displacement field1062A or the displacement scale field1062B.

Memory Access Instruction Templates—Temporal

Memory Access Instruction Templates—Non-Temporal

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field1052is interpreted as a write mask control (Z) field1052C, whose content distinguishes whether the write masking controlled by the write mask field1070should be a merging or a zeroing.

In the case of the non-memory access1005instruction templates of class B, part of the beta field1054is interpreted as an RL field1057A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round1057A.1and vector length (VSIZE)1057A.2are respectively specified for the no memory access, write mask control, partial round control type operation1012instruction template and the no memory access, write mask control, VSIZE type operation1017instruction template), while the rest of the beta field1054distinguishes which of the operations of the specified type is to be performed. In the no memory access1005instruction templates, the scale field1060, the displacement field1062A, and the displacement scale filed1062B are not present.

In the no memory access, write mask control, partial round control type operation1010instruction template, the rest of the beta field1054is interpreted as a round operation field1059A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field1059A—just as round operation control field1058, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field1059A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's1050content overrides that register value.

In the no memory access, write mask control, VSIZE type operation1017instruction template, the rest of the beta field1054is interpreted as a vector length field1059B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access1020instruction template of class B, part of the beta field1054is interpreted as a broadcast field1057B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field1054is interpreted the vector length field1059B. The memory access1020instruction templates include the scale field1060, and optionally the displacement field1062A or the displacement scale field1062B.

With regard to the generic vector friendly instruction format1000, a full opcode field1074is shown including the format field1040, the base operation field1042, and the data element width field1064. While one embodiment is shown where the full opcode field1074includes all of these fields, the full opcode field1074includes less than all of these fields in embodiments that do not support all of them. The full opcode field1074provides the operation code (opcode).

The augmentation operation field1050, the data element width field1064, and the write mask field1070allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

Exemplary Specific Vector Friendly Instruction Format

FIG. 11Ais a block diagram illustrating an exemplary specific vector friendly instruction format according to embodiments of the invention.FIG. 11Ashows a specific vector friendly instruction format1100that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format1100may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields fromFIG. 10into which the fields fromFIG. 11Amap are illustrated.

It should be understood that, although embodiments of the invention are described with reference to the specific vector friendly instruction format1100in the context of the generic vector friendly instruction format1000for illustrative purposes, the invention is not limited to the specific vector friendly instruction format1100except where claimed. For example, the generic vector friendly instruction format1000contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format1100is shown as having fields of specific sizes. By way of specific example, while the data element width field1064is illustrated as a one bit field in the specific vector friendly instruction format1100, the invention is not so limited (that is, the generic vector friendly instruction format1000contemplates other sizes of the data element width field1064).

The generic vector friendly instruction format1000includes the following fields listed below in the order illustrated inFIG. 11A.

Format Field1040(EVEX Byte0, bits [7:0])—the first byte (EVEX Byte0) is the format field1040and it contains 0×62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the invention).

The second-fourth bytes (EVEX Bytes1-3) include a number of bit fields providing specific capability.

Data element width field1064(EVEX byte2, bit [7]-W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.U1068Class field (EVEX byte2, bit [2]-U)—If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.

Alpha field1052(EVEX byte3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with α)—as previously described, this field is context specific.

Real Opcode Field1130(Byte4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field1140(Byte5) includes MOD field1142, Reg field1144, and R/M field1146. As previously described, the MOD field's1142content distinguishes between memory access and non-memory access operations. The role of Reg field1144can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field1146may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte6)—As previously described, the scale field's1050content is used for memory address generation. SIB.xxx1154and SIB.bbb1156—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field1062A (Bytes7-10)—when MOD field1142contains 10, bytes7-10are the displacement field1062A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Full Opcode Field

FIG. 11Bis a block diagram illustrating the fields of the specific vector friendly instruction format1100that make up the full opcode field1074according to one embodiment of the invention. Specifically, the full opcode field1074includes the format field1040, the base operation field1042, and the data element width (W) field1064. The base operation field1042includes the prefix encoding field1125, the opcode map field1115, and the real opcode field1130.

Register Index Field

FIG. 11Cis a block diagram illustrating the fields of the specific vector friendly instruction format1100that make up the register index field1044according to one embodiment of the invention. Specifically, the register index field1044includes the REX field1105, the REX' field1110, the MODR/M.reg field1144, the MODR/M.r/m field1146, the VVVV field1120, xxx field1154, and the bbb field1156.

Augmentation Operation Field

FIG. 11Dis a block diagram illustrating the fields of the specific vector friendly instruction format1100that make up the augmentation operation field1050according to one embodiment of the invention. When the class (U) field1068contains 0, it signifies EVEX.U0 (class A1068A); when it contains 1, it signifies EVEX.U1 (class B1068B). When U=0 and the MOD field1142contains 11 (signifying a no memory access operation), the alpha field1052(EVEX byte3, bit [7]-EH) is interpreted as the rs field1052A. When the rs field1052A contains a1(round1052A.1), the beta field1054(EVEX byte3, bits [6:4]-SSS) is interpreted as the round control field1054A. The round control field1054A includes a one bit SAE field1056and a two bit round operation field1058. When the rs field1052A contains a 0 (data transform1052A.2), the beta field1054(EVEX byte3, bits [6:4]-SSS) is interpreted as a three bit data transform field1054B. When U=0 and the MOD field1142contains 00, 01, or 10 (signifying a memory access operation), the alpha field1052(EVEX byte3, bit [7]-EH) is interpreted as the eviction hint (EH) field1052B and the beta field1054(EVEX byte3, bits [6:4]-SSS) is interpreted as a three bit data manipulation field1054C.

When U=1, the alpha field1052(EVEX byte3, bit [7]-EH) is interpreted as the write mask control (Z) field1052C. When U=1 and the MOD field1142contains 11 (signifying a no memory access operation), part of the beta field1054(EVEX byte3, bit [4]-S0) is interpreted as the RL field1057A; when it contains a 1 (round1057A.1) the rest of the beta field1054(EVEX byte3, bit [6-5]-S2-1) is interpreted as the round operation field1059A, while when the RL field1057A contains a 0 (VSIZE1057.A2) the rest of the beta field1054(EVEX byte3, bit [6-5]-S2-1) is interpreted as the vector length field1059B (EVEX byte3, bit [6-5]-L1-10). When U=1 and the MOD field1142contains 00, 01, or 10 (signifying a memory access operation), the beta field1054(EVEX byte3, bits [6:4]-SSS) is interpreted as the vector length field1059B (EVEX byte3, bit [6-5]-L1-0) and the broadcast field1057B (EVEX byte3, bit [4]-B).

Exemplary Register Architecture

FIG. 12is a block diagram of a register architecture1200according to one embodiment of the invention. In the embodiment illustrated, there are 32 vector registers1210that are 512 bits wide; these registers are referenced as zmm0through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format1100operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field1059B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field1059B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format1100operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers1215—in the embodiment illustrated, there are 8 write mask registers (k0through k7), each 64 bits in size. In an alternate embodiment, the write mask registers1215are 16 bits in size. As previously described, in one embodiment of the invention, the vector mask register k0cannot be used as a write mask; when the encoding that would normally indicate k0is used for a write mask, it selects a hardwired write mask of 0×FFFF, effectively disabling write masking for that instruction.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 13A, a processor pipeline1300includes a fetch stage1302, a length decode stage1304, a decode stage1306, an allocation stage1308, a renaming stage1310, a scheduling (also known as a dispatch or issue) stage1312, a register read/memory read stage1314, an execute stage1316, a write back/memory write stage1318, an exception handling stage1322, and a commit stage1324.

FIG. 13Bshows processor core1390including a front end unit1330coupled to an execution engine unit1350, and both are coupled to a memory unit1370. The core1390may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core1390may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit1330includes a branch prediction unit1332coupled to an instruction cache unit1334, which is coupled to an instruction translation lookaside buffer (TLB)1336, which is coupled to an instruction fetch unit1338, which is coupled to a decode unit1340. The decode unit1340(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit1340may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core1390includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit1340or otherwise within the front end unit1330). The decode unit1340is coupled to a rename/allocator unit1352in the execution engine unit1350.

The execution engine unit1350includes the rename/allocator unit1352coupled to a retirement unit1354and a set of one or more scheduler unit(s)1356. The scheduler unit(s)1356represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)1356is coupled to the physical register file(s) unit(s)1358. Each of the physical register file(s) units1358represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit1358comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)1358is overlapped by the retirement unit1354to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit1354and the physical register file(s) unit(s)1358are coupled to the execution cluster(s)1360. The execution cluster(s)1360includes a set of one or more execution units1362and a set of one or more memory access units1364. The execution units1362may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)1356, physical register file(s) unit(s)1358, and execution cluster(s)1360are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)1364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units1364is coupled to the memory unit1370, which includes a data TLB unit1372coupled to a data cache unit1374coupled to a level 2 (L2) cache unit1376. In one exemplary embodiment, the memory access units1364may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit1372in the memory unit1370. The instruction cache unit1334is further coupled to a level 2 (L2) cache unit1376in the memory unit1370. The L2 cache unit1376is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline1300as follows: 1) the instruction fetch1338performs the fetch and length decoding stages1302and1304; 2) the decode unit1340performs the decode stage1306; 3) the rename/allocator unit1352performs the allocation stage1308and renaming stage1310; 4) the scheduler unit(s)1356performs the schedule stage1312; 5) the physical register file(s) unit(s)1358and the memory unit1370perform the register read/memory read stage1314; the execution cluster1360perform the execute stage1316; 6) the memory unit1370and the physical register file(s) unit(s)1358perform the write back/memory write stage1318; 7) various units may be involved in the exception handling stage1322; and 8) the retirement unit1354and the physical register file(s) unit(s)1358perform the commit stage1324.

Specific Exemplary In-Order Core Architecture

FIG. 14Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network1402and with its local subset of the Level 2 (L2) cache1404, according to embodiments of the invention. In one embodiment, an instruction decoder1400supports the x86 instruction set with a packed data instruction set extension. An L1 cache1406allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit1408and a vector unit1410use separate register sets (respectively, scalar registers1412and vector registers1414) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache1406, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 14Bis an expanded view of part of the processor core inFIG. 14Aaccording to embodiments of the invention.FIG. 14Bincludes an L1 data cache1406A part of the L1 cache1404, as well as more detail regarding the vector unit1410and the vector registers1414. Specifically, the vector unit1410is a 16-wide vector processing unit (VPU) (see the 16-wide ALU1428), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit1420, numeric conversion with numeric convert units1422A-B, and replication with replication unit1424on the memory input. Write mask registers1426allow predicating resulting vector writes.

FIG. 15is a block diagram of a processor1500that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes inFIG. 15illustrate a processor1500with a single core1502A, a system agent1510, a set of one or more bus controller units1516, while the optional addition of the dashed lined boxes illustrates an alternative processor1500with multiple cores1502A-N, a set of one or more integrated memory controller unit(s)1514in the system agent unit1510, and special purpose logic1508.

Thus, different implementations of the processor1500may include: 1) a CPU with the special purpose logic1508being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores1502A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores1502A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores1502A-N being a large number of general purpose in-order cores. Thus, the processor1500may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor1500may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units1506, and external memory (not shown) coupled to the set of integrated memory controller units1514. The set of shared cache units1506may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit1512interconnects the integrated graphics logic1508(integrated graphics logic1508is an example of and is also referred to herein as special purpose logic), the set of shared cache units1506, and the system agent unit1510/integrated memory controller unit(s)1514, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units1506and cores1502-A-N.

In some embodiments, one or more of the cores1502A-N are capable of multi-threading. The system agent1510includes those components coordinating and operating cores1502A-N. The system agent unit1510may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1502A-N and the integrated graphics logic1508. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 16, shown is a block diagram of a system1600in accordance with one embodiment of the present invention. The system1600may include one or more processors1610,1615, which are coupled to a controller hub1620. In one embodiment the controller hub1620includes a graphics memory controller hub (GMCH)1690and an Input/Output Hub (IOH)1650(which may be on separate chips); the GMCH1690includes memory and graphics controllers to which are coupled memory1640and a coprocessor1645; the IOH1650couples input/output (I/O) devices1660to the GMCH1690. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1640and the coprocessor1645are coupled directly to the processor1610, and the controller hub1620in a single chip with the IOH1650.

The optional nature of additional processors1615is denoted inFIG. 16with broken lines. Each processor1610,1615may include one or more of the processing cores described herein and may be some version of the processor1500.

The memory1640may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1620communicates with the processor(s)1610,1615via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1695.

In one embodiment, the coprocessor1645is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1620may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1610,1615in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1610executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1610recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1645. Accordingly, the processor1610issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1645. Coprocessor(s)1645accept and execute the received coprocessor instructions.

Referring now toFIG. 17, shown is a block diagram of a first more specific exemplary system1700in accordance with an embodiment of the present invention. As shown inFIG. 17, multiprocessor system1700is a point-to-point interconnect system, and includes a first processor1770and a second processor1780coupled via a point-to-point interconnect1750. Each of processors1770and1780may be some version of the processor1500. In one embodiment of the invention, processors1770and1780are respectively processors1610and1615, while coprocessor1738is coprocessor1645. In another embodiment, processors1770and1780are respectively processor1610coprocessor1645.

Processors1770and1780are shown including integrated memory controller (IMC) units1772and1782, respectively. Processor1770also includes as part of its bus controller units point-to-point (P-P) interfaces1776and1778; similarly, second processor1780includes P-P interfaces1786and1788. Processors1770,1780may exchange information via a point-to-point (P-P) interface1750using P-P interface circuits1778,1788. As shown inFIG. 17, IMCs1772and1782couple the processors to respective memories, namely a memory1732and a memory1734, which may be portions of main memory locally attached to the respective processors.

Processors1770,1780may each exchange information with a chipset1790via individual P-P interfaces1752,1754using point to point interface circuits1776,1794,1786,1798. Chipset1790may optionally exchange information with the coprocessor1738via a high-performance interface1792. In one embodiment, the coprocessor1738is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1790may be coupled to a first bus1716via an interface1796. In one embodiment, first bus1716may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 17, various I/O devices1714may be coupled to first bus1716, along with a bus bridge1718which couples first bus1716to a second bus1720. In one embodiment, one or more additional processor(s)1715, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1716. In one embodiment, second bus1720may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1720including, for example, a keyboard and/or mouse1722, communication devices1727and a storage unit1728such as a disk drive or other mass storage device which may include instructions/code and data1730, in one embodiment. Further, an audio I/O1724may be coupled to the second bus1720. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 17, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 18, shown is a block diagram of a second more specific exemplary system1800in accordance with an embodiment of the present invention. Like elements inFIGS. 17 and 18bear like reference numerals, and certain aspects ofFIG. 17have been omitted fromFIG. 18in order to avoid obscuring other aspects ofFIG. 18.

FIG. 18illustrates that the processors1770,1780may include integrated memory and I/O control logic (“CL”)1772and1782, respectively. Thus, the CL1772,1782include integrated memory controller units and include I/O control logic.FIG. 18illustrates that not only are the memories1732,1734coupled to the CL1772,1782, but also that I/O devices1814are also coupled to the control logic1772,1782. Legacy I/O devices1815are coupled to the chipset1790.

Referring now toFIG. 19, shown is a block diagram of a SoC1900in accordance with an embodiment of the present invention. Similar elements inFIG. 15bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 19, an interconnect unit(s)1902is coupled to: an application processor1910which includes a set of one or more cores1502A-N, which include cache units1504A-N, and shared cache unit(s)1506; a system agent unit1510; a bus controller unit(s)1516; an integrated memory controller unit(s)1514; a set or one or more coprocessors1920which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1930; a direct memory access (DMA) unit1932; and a display unit1940for coupling to one or more external displays. In one embodiment, the coprocessor(s)1920include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

FIG. 20is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG. 20shows a program in a high level language2002may be compiled using an x86 compiler2004to generate x86 binary code2006that may be natively executed by a processor with at least one x86 instruction set core2016. The processor with at least one x86 instruction set core2016represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler2004represents a compiler that is operable to generate x86 binary code2006(e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core2016. Similarly,FIG. 20shows the program in the high level language2002may be compiled using an alternative instruction set compiler2008to generate alternative instruction set binary code2010that may be natively executed by a processor without at least one x86 instruction set core2014(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter2012is used to convert the x86 binary code2006into code that may be natively executed by the processor without an x86 instruction set core2014. This converted code is not likely to be the same as the alternative instruction set binary code2010because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter2012represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code2006.

EXAMPLES

Example 1 is a processor. The processor includes a decode circuit to decode an instruction into a decoded instruction and an execution circuit to execute the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block.

Example 2 includes the substance of example 1. In this example, the execution circuit is to sum one or more values of one or more other contiguous elements of the input vector that form a second block to produce an accumulated value for the second block and store the accumulated value for the second block in the destination vector, where the one or more other contiguous elements that form the second block are dictated by the input mask.

Example 3 includes the substance of example 1. In this example, the execution circuit is to process the one or more contiguous elements of the input vector from left to right.

Example 4 includes the substance of example 1. In this example, the execution circuit is to process the one or more contiguous elements of the input vector from right to left.

Example 5 includes the substance of example 1. In this example, the input vector is a vector containing all binary ‘1’s.

Example 6 includes the substance of example 1. In this example, a bit of the input mask is set to binary ‘1’ to indicate a border of the block.

Example 7 includes the substance of example 6. In this example, the execution circuit is to store the accumulated value for the block in an element of the destination vector corresponding to the bit of the input mask that is set to binary ‘1’.

Example 8 includes the substance of example 1. In this example, the execution circuit is to store the accumulated value for the block in the destination vector in a compressed manner.

Example 9 is a method performed by a processor. The method includes decoding an instruction into a decoded instruction and executing the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block.

Example 10 includes the substance of example 9. In this example, the execution is to sum one or more values of one or more other contiguous elements of the input vector that form a second block to produce an accumulated value for the second block and store the accumulated value for the second block in the destination vector, where the one or more other contiguous elements that form the second block are dictated by the input mask.

Example 11 includes the substance of example 9. In this example, the execution is to process the one or more contiguous elements of the input vector from left to right.

Example 12 includes the substance of example 9. In this example, the execution is to process the one or more contiguous elements of the input vector from right to left.

Example 13 includes the substance of example 9. In this example, the input vector is a vector containing all binary ‘1’s.

Example 14 includes the substance of example 9. In this example, a bit of the input mask is set to binary ‘1’ to indicate a border of the block.

Example 15 includes the substance of example 14. In this example, the execution is to store the accumulated value for the block in an element of the destination vector corresponding to the bit of the input mask that is set to binary ‘1’.

Example 16 includes the substance of example 9. In this example, the execution is to store the accumulated value for the block in the destination vector in a compressed manner.

Example 17 is a non-transitory machine readable medium. The non-transitory machine readable medium has instruction stored therein, which when executed by a processor, causes the processor to decode an instruction into a decoded instruction and execute the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block.

Example 18 includes the substance of example 17. In this example, the execution is to sum one or more values of one or more other contiguous elements of the input vector that form a second block to produce an accumulated value for the second block and store the accumulated value for the second block in the destination vector, where the one or more other contiguous elements that form the second block are dictated by the input mask.

Example 19 includes the substance of example 17. In this example, the execution is to process the one or more contiguous elements of the input vector from left to right.

Example 20 includes the substance of example 17. In this example, the execution is to process the one or more contiguous elements of the input vector from right to left.

Example 21 includes the substance of example 17. In this example, the input vector is a vector containing all binary ‘1’s.

Example 22 includes the substance of example 17. In this example, a bit of the input mask is set to binary ‘1’ to indicate a border of the block.

Example 23 includes the substance of example 22. In this example, the execution is to store the accumulated value for the block in an element of the destination vector corresponding to the bit of the input mask that is set to binary ‘1’.

Example 24 includes the substance of example 17. In this example, the execution is to store the accumulated value for the block in the destination vector in a compressed manner.

Example 25 is a hardware processor. The hardware processor includes a decoding means to decode an instruction into a decoded instruction and an executing means to execute the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block.

Example 26 includes the substance of example 25. In this example, the executing means is to sum one or more values of one or more other contiguous elements of the input vector that form a second block to produce an accumulated value for the second block and store the accumulated value for the second block in the destination vector, where the one or more other contiguous elements that form the second block are dictated by the input mask.

Example 27 includes the substance of example 25. In this example, the executing means is to process the one or more contiguous elements of the input vector from left to right.

Example 28 includes the substance of example 25. In this example, the executing means is to process the one or more contiguous elements of the input vector from right to left.

Example 29 includes the substance of example 25. In this example, the input vector is a vector containing all binary ‘1’s.

Example 30 includes the substance of example 25. In this example, a bit of the input mask is set to binary ‘1’ to indicate a border of the block.

Example 31 includes the substance of example 30. In this example, the executing means is to store the accumulated value for the block in an element of the destination vector corresponding to the bit of the input mask that is set to binary ‘1’.

Example 32 includes the substance of example 25. In this example, the executing means is to store the accumulated value for the block in the destination vector in a compressed manner.