Targets for measurements in semiconductor devices

Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to targets used for measurements in semiconductor devices.

BACKGROUND

Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically comprise thin films of conductive, semiconductive and insulating materials that are patterned to form integrated circuits using lithography.

Semiconductor lithography involves placing a patterned mask between a semiconductor workpiece, and using an energy source to expose portions of a resist deposited on the workpiece, transferring the mask pattern to the resist. The resist is then developed during which either the exposed or unexposed regions of the resist are removed. The removal of exposed or unexposed regions depends whether the resist is positive or negative tone. The resist is then used as a mask while regions of a material corresponding to areas opened during resist development on the workpiece are etched.

In many designs, the individual features of an integrated circuit, such as gate lines or signal lines, as examples, have extremely small dimensions and may have widths of about 0.2 to 0.4 μm or less, with their lengths being considerably greater, about 0.8 to 2.0 μm or greater, for example. These thin lines may be intended for connection to other layers of the integrated circuit by narrow vias filled with conductive material. It is important in semiconductor designs that each layer is aligned properly to adjacent material layers to ensure electrical connection, and that the dimensions of patterned features are being correctly printed on the various material layers. The size integrity of critical dimensions (CD) may be compromised because of various processing and/or optical effects, for example. In particular, the accuracy of forming and positioning conductive lines and vias of an integrated circuit becomes increasingly critical as dimensions decrease. Relatively minor errors in positioning such features can cause a via to miss a conductive line altogether, or to contact the line over a surface area that is insufficient to provide the necessary conductivity for a fully functional circuit.

Optical measurements are used in semiconductor technology to measure a variety of parameters of semiconductor devices. The measurements may be used for critical dimension measurement, line shortening measurements, and alignment and overlay measurements, as examples. Gratings are often used as a target for measurement in semiconductor lithography. The gratings typically comprise a line and space pattern. For example, a row of gratings is typically used in scatterometry to measure CD.

Scatterometry involves measuring order diffraction responses of a grating at multiple wavelengths, as described in a paper entitled “Specular Spectroscopic Scatterometry in DUV Lithography” by Xinhui Niu et al., Proc. SPIE 1999, Vol. 3677, pp. 159-168, which is incorporated herein by reference. As described in the paper, scatterometry is a library-based methodology for CD profile extraction. Measurements of the gratings are compared to those stored in a library, e.g., in a look-up table, and any variations from the library data indicate the amount that the CD is too large or too small, for example.

However, many optical measurements require targets having dimensions that exceed the design rule limitations. For example, lithography of extremely long and thin patterns may be limited by the wavelength and photoresist used to pattern the target. One requirement, particularly in scatterometry, is to manufacture targets comprising line and space pairs that are sufficiently large for measurement by an optical measurement tool.

What are needed in the art are improved targets or test structures for optical measurements of semiconductor devices, wherein the targets have features that have dimensions within the design rule limitations of the semiconductor devices.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide improved methods of forming targets for optical measurements and structures thereof. Long lines of gratings of targets or test structures are divided into segments, wherein each segment of a line comprises a dimension that is within the design rule limitations of the semiconductor device. In some embodiments, the segments of lines in adjacent lines either comprise substantially the same length and are staggered, or comprise different lengths, to avoid creating periodicity in a direction parallel with the length of the lines. In other embodiments, the segments of lines have periodicity in the direction parallel with the length of the lines.

In accordance with a preferred embodiment of the present invention, a test structure for a semiconductor device includes at least one grating, the grating comprising a plurality of parallel lines, each of the plurality of parallel lines having a first length, wherein each line is divided into a plurality of discrete segments along the first length of the line.

In accordance with another preferred embodiment of the present invention, a method of designing a test structure for a semiconductor device includes designing a test structure comprising at least one grating, the grating comprising a plurality of parallel lines, each of the plurality of parallel lines having a first length. Each line of the grating is divided into a plurality of discrete segments along the first length of the line.

Advantages of embodiments of the present invention include providing improved methods of forming targets for optical measurements and structures thereof. In some embodiments, because there is a lack of periodicity in one direction of the test structures, accurate optical measurements with less complications using scatterometry and other measurement techniques may be performed.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely in patterns for targets used in optical measurements of semiconductor devices. The invention may also be applied, however, to other aspects of semiconductor devices, such as targets used for other types of measurements and patterned features of material layers of semiconductor devices, as examples.

Targets or test structures of optical measurements for semiconductor devices typically comprise grating structures. In some semiconductor designs, the test structures may comprise sacrificial structures that are formed on a scribe line region. When the die of a wafer are singulated, the test structures are destroyed and discarded, for example. In other semiconductor designs, the test structures are located in die regions of a wafer, and the test structures are discarded after the semiconductor devices are manufactured.

Scatterometry typically requires the use of periodic structures in one direction, so that the periodic structures have scattering and diffraction effects.

Some test structures require high aspect ratio features, e.g., the gratings include parallel long lines that have a large height (e.g., in a dimension from a substrate to the top surface). When patterned, the long lines have a tendency to stick together and are mechanically unstable. The long lines present problems in etch processes, due to undercutting of the high aspect ratio features. Furthermore, the long lines exhibit loading effects, wherein more material is etched in the testing structure than in the array or the active chip area. The aspect ratios can be as high as 1:50 or greater, for example. A feature may be about 6 to 7 μm deep into a substrate or material layer, and may have a length of about 100 nm, as examples, although the test features may alternatively comprise other dimensions.

To alleviate the etching problems and loading effects of the test structures, design rules are developed, which involve determining a maximum feature size that can be optimally etched for a particular semiconductor device. For example, a design rule may require that a feature may not be etched that is longer than about 10 μm×about 50 nm, as an example, although design rules may comprise other dimensions in other applications, typically depending on the minimum feature size of the integrated circuit or chip.

FIG. 1shows a top view of a less-preferred embodiment of the present invention, wherein a semiconductor device100includes a target (also referred to herein as a test structure) for optical measurements comprising a line and space pattern. The semiconductor device100may include a workpiece or substrate with a layer of insulating material104formed thereon. The target may comprise a plurality of lines106formed a conductive or semiconductive material, for example. Each line106of the target comprises a length L1that exceeds the design rule limitations, e.g., length L2, in this less-preferred embodiment. The length L1of the lines106of the test structure may comprise about 100 μm, for example, although length L1may alternatively comprise other dimensions, for example. The test structure comprises a plurality of long lines106separated by spaces, wherein the width W1of the lines106may comprise a minimum feature size of the semiconductor device100, such as about 100 nm, although alternatively, the width W1of the lines106may comprise other dimensions, for example. The distance between adjacent and parallel lines106may also comprise a minimum feature size of the semiconductor device100, for example. The target pattern comprises a periodicity in a direction108perpendicular to the length of the lines106, as shown.

A disadvantage of the test structure shown inFIG. 1is that because the line106comprise a length L1that exceeds the design rule limitations, e.g., length L2, attempting to pattern the long lines106using lithography would result in collapse of some of the lines106, and thus would render the lines106of the test structure unusable as a test structure. The design rule (or ground rule) L2may comprise a maximum dimension of about 2 to 50 μm, for example, although alternatively, the design rule L2may alternatively comprise other dimensions, typically depending on the minimum feature size of the semiconductor device100, for example.

The design rules comprise rules for designers that design a layer or set of layers of a semiconductor device. The design rules define a minimum and maximum features size that may be patterned with respect to a particular layer or process, for example. The ground rules (also referred to herein as ‘design rules’) for a semiconductor device are a function of a variety of parameters, such as the thickness of the material layers, the type of materials used, and the processes used, for example. If the material layer is relatively deep, then the design rules are typically shorter, and if the material layer is relatively thin, then the maximum feature size is typically longer, for example.

One approach to forming a test structure that has features that are within the design rule limitations is to segment the lines, as shown in a top view inFIG. 2, in accordance with an embodiment of the present invention. Like numerals are used inFIG. 2as were used inFIG. 1, and to avoid repetition, each element inFIG. 2is not described in detail.

FIG. 2illustrates an embodiment of the present invention, wherein each line206of the target (e.g., lines106shown inFIG. 1) is divided into a plurality of segments210having substantially an equal length L3. Length L3is preferably less than or equal to the design rule limitations, e.g., length L2shown inFIG. 1, in this embodiment. The length L3of the segments210may comprise a dimension of about 50 μm, as an example, although the segment length L3may alternatively comprise other dimensions.

However, this test structure has a periodicity in the horizontal direction208, e.g., in a direction perpendicular to the length L1of the lines206, and also has a periodicity in direction212parallel to the length L1of the lines206. The periodicity in direction212is created by the ends of the segments210in adjacent lines206being aligned. The periodicity in direction212makes the test structure challenging as a target in some measurement techniques, such as scatterometry. Because the gratings of the test structure have periodicity in two directions208and212, the calculations required to determine CD, for example, are more complicated. It is desirable to have periodicity on only one direction in a test pattern for scattterometry, for this reason, for example. Thus, it would be desirable to eliminate the second periodicity in the test structure, e.g., in the direction212parallel to the length of the lines206.

FIG. 3shows a top view of a preferred embodiment of the present invention, wherein a target for optical measurement on a semiconductor device300comprises a line and space pattern, wherein each line306is divided into segments320, and wherein the segments320in adjacent lines306(e.g., as illustrated by referring to two adjacent lines306aand306b) are staggered, avoiding periodicity in the direction312parallel to the length L1of the lines306. Again, like numerals are used for the elements inFIG. 3as were used inFIGS. 1 and 2, and each element is not described again in detail herein, to avoid repetition.

In particular, the ends of the segments320in adjacent lines are staggered in this embodiment, for example. The staggering of the ends of the segments320in adjacent lines306eliminates the periodicity in direction312parallel to the length L1of the plurality of parallel lines306, advantageously allowing the novel test structure to be used for optical measurements using a variety of optical measurement techniques, including scatterometry, for example.

In the embodiment shown inFIG. 3, preferably, the majority of the segments320of the lines306comprise discrete segments that comprise substantially the same dimension. However, segments320at the ends314of the lines306preferably comprise a smaller dimension than segments320in a central region of the lines. The shorter segments320at the ends314are a result of the staggering of the ends of the segments320, for example, because the lines306comprise substantially the same dimension.

Length L3is preferably less than or equal to the design rule limitations, e.g., length L2shown inFIG. 1, in this embodiment. The length L3of the segments320may comprise a dimension of about 50 μm or less, as an example, although the segment length L3may alternatively comprise other dimensions.

Like numerals are used for the elements inFIGS. 4 through 6as were used inFIGS. 1 through 3, and each element is not described again in detail herein, to avoid repetition.

FIG. 4shows another preferred embodiment of the present invention, wherein a target for optical measurements on a semiconductor device comprises a line and space pattern, wherein each line406is divided into a plurality of segments422having unequal lengths L4, L5, L6, L7, L8, L8, . . . LN. The ends of the varying length segments422are staggered or unaligned in adjacent lines406(e.g., as illustrated in adjacent lines406aand406b), avoiding periodicity in the direction412parallel to the length L1of the lines406.

In particular, in one embodiment, the plurality of parallel lines406preferably comprise a first line406aand at least one second line406bparallel to the first line406a, wherein the first line406acomprises a first segment422and at least one second segment422, the first segment422and second segment422comprising different lengths. The at least one second line406bcomprises a third segment422and a fourth segment422, the third segment422and the fourth segment422comprising different lengths, wherein the first segment422of the first line406ais proximate the third segment422of the at least one second line406b. A first end of the first segment422is preferably not aligned with a first end of the third segment422, and a second end of the first segment422is not aligned with a second end of the second segment422. The second segment422of the first line406ais preferably proximate the fourth segment422of the at least one second line406b, wherein a first end of the second segment422is not aligned with a first end of the fourth segment422, and wherein a second end of the second segment422is not aligned with a second end of the fourth segment422.

FIG. 5shows a top view of a semiconductor wafer530, illustrating that the targets described herein may be located at the scribe line regions534between the individual die532. In this embodiment, the targets or test structures are sacrificial structures that are destroyed and/or discarded after the die are singulated. In another embodiment, the test structures may be formed in a die532region and may be discarded after singulation, for example.

FIG. 6shows a more detailed view ofFIG. 7, showing a target536formed in a scribe line region534in one embodiment of the present invention, wherein the lines506of the target comprise a length L1and are not segmented (thus violating the design rules) and exhibit periodicity in a direction508perpendicular to the length L1of the lines506.

Like numerals are used for the elements inFIGS. 7 and 8as were used inFIG. 6, and each element is not described again in detail herein, to avoid repetition.

FIG. 7shows a more detailed view ofFIG. 5, illustrating a target650or test structure formed in a scribe line region634according to a preferred embodiment of the present invention, wherein the lines606in the line and space pattern are divided into segments622that lack a periodicity in a direction612coincident (or parallel) with the length L1of the lines606. The lines606are preferably arranged in a single horizontal row, as shown, and may be used for scatterometry measurements of CD, for example. Alternatively, the lines606may be arranged in other patterns, for example. The test structures may be formed in a scribe line634as shown inFIG. 7, or in a die region, such as in the location of a die632, as examples.

Embodiments of the present invention may be implemented in other test structures comprising gratings. As an example, two rows and two columns of gratings arranged in a box that may be used as alignment and overlay measurement marks, as examples, are illustrated inFIG. 8. The grating patterns are often referred to in the art as a box-in-box structure, for example, with a first box being defined by the exterior ends of the rows and columns of the gratings, and a second box being defined by the interior ends of the rows and columns of the gratings. These box-in-box structures may be used to check the positioning and registration between two patterned material layers, for example.

In accordance with this embodiment of the present invention, a test structure750includes a plurality of gratings706, wherein each grating is divided into a plurality of segments722comprising a variety of lengths to avoid a periodicity in a direction712parallel with the length of the lines or gratings706, for example.

Advantages of embodiments of the present invention include providing improved methods of forming targets for optical measurements and structures thereof. In some embodiments, because there is a lack of periodicity in one direction of the test structures, more accurate optical measurements using scatterometry and other measurement techniques may be performed. The test structures may be formed in scribe line regions or die regions of a semiconductor device. Embodiments of the invention are useful in applications having test structures comprised of gratings, such as those used for scatterometry, alignment measurement, and overlay measurement, as examples.