Error recovery handling

A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.

TECHNICAL FIELD

The present description relates generally to error recovery handling including error recovery handling for flash memory devices.

BACKGROUND

In a flash memory system, when a read error occurs an error recovery request may be generated and forwarded to an error recovery handler. The error recovery handler may utilize one or more error recovery techniques to attempt to recover the data for which the read error occurred. The error recovery handler may select a particular error recovery technique to attempt to recover the data based on the type of read error that occurred.

SUMMARY

The disclosed subject matter relates to a device that includes at least one processor. The at least one processor may be configured to receive an error recovery request comprising error type information and an address of a page of a flash memory circuit for which a read error has occurred, wherein the error type information of the error recovery request is mapped to a first error recovery technique. The at least one processor may be further configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and a block error map associated with the flash memory circuit satisfies a second criterion, wherein the error count indicates a number of read errors that have occurred on the flash memory circuit and the block error map indicates one or more blocks of the flash memory circuit in which the read errors have occurred. The at least one processor may be further configured to utilize a second error recovery technique to attempt to recover data stored in the page when the first and second criterions are satisfied, otherwise utilize the first error recovery technique to attempt to recover the data stored in the page, wherein the second error recovery technique is associated with recovering data stored in an offline flash memory circuit.

In another aspect, a method may include receiving an error recovery request corresponding to a page of a flash memory circuit, wherein the error recovery request indicates an error type that is mapped to a first error recovery technique. The method may further include determining a likelihood that data stored in the page of the flash memory circuit can be recovered using the first error recovery technique. The method may further include, when the likelihood that the data stored in the page of the flash memory circuit can be recovered using the first error recovery technique satisfies a criterion, utilizing the first error recovery technique to attempt to recover the data stored in the page of the flash memory circuit, otherwise utilizing a second error recovery technique to attempt to recover the data stored in the page of the flash memory circuit without utilizing the first error recovery technique.

In another aspect, a system may include flash memory circuits each comprising blocks, each of the blocks including one or more pages, a random access memory (RAM) configured to store: a mapping between error types and error recovery techniques, an error count for each of the flash memory circuits, and a block error map for each of the flash memory circuits, wherein the error count for each respective flash memory circuit indicates a number of read errors that have occurred on each respective flash memory circuit and the block error map for each respective flash memory circuit indicates each of the blocks of each respective flash memory circuit in which at least one of the read errors has occurred, an interface communicatively coupled to a host device, and a controller. The controller may be configured to receive error recovery requests corresponding to read errors that have occurred on the flash memory circuits, each of the error recovery requests indicating a page of one of the flash memory circuits and one of the error types. The controller may be further configured to, for each of the error recovery requests, identify one of the error recovery techniques mapped to the one of the error types, determine whether the error count for the one of the flash memory circuits on which the corresponding read error occurred exceeds a first threshold and whether the block error map for the one of the flash memory circuits indicates that the read errors occurred in at least a number of the blocks of the one of the flash memory circuits, and utilize an other one of the error recovery techniques to attempt to recover data stored in the page when the error count exceeds the first threshold and the block error map indicates that the read errors occurred in the at least the number of the blocks, otherwise utilize the one of the error recovery techniques to attempt to recover the data stored in the page.

In another aspect, a system may include means for receiving an error recovery request comprising error type information and an address of a page of a flash memory circuit for which a read error has occurred, wherein the error type information of the error recovery request is mapped to a first error recovery technique. The system may further include means for determining whether an error count associated with the flash memory circuit satisfies a first criterion and a block error map associated with the flash memory circuit satisfies a second criterion, wherein the error count indicates a number of read errors that have occurred on the flash memory circuit and the block error map indicates one or more blocks of the flash memory circuit in which the read errors have occurred. The system may further include means for utilizing a second error recovery technique to attempt to recover data stored in the page when the first and second criterions are satisfied, otherwise utilize the first error recovery technique to attempt to recover the data stored in the page, wherein the second error recovery technique is associated with recovering data stored in an offline flash memory circuit.

DETAILED DESCRIPTION

In the subject system for error recovery handling, an error recovery manager of a flash memory device maintains an error count and a block error map for each flash memory circuit (e.g. a single flash memory die/chip) in the flash memory device. The error count for a flash memory circuit indicates the total number of read errors that have occurred with respect to the flash memory circuit and the block error map for a flash memory circuit indicates the particular blocks of the flash memory circuit in which the read errors have occurred. When the error count of a given flash memory circuit exceeds a first threshold, and the block error map of the flash memory circuit indicates that the errors have occurred across a threshold percentage of the blocks, the error recovery manager handles error recovery requests for pages of the flash memory circuit by utilizing an error recovery technique for recovering data from offline flash memory circuits, rather than selecting an error recovery technique based on the error types corresponding to the error recovery requests.

For example, the error recovery manager may bypass performing error recovery for the flash memory circuit using error recovery techniques that rely on the flash memory circuit being online, such as read retry and error correction coding error recovery techniques, and the error recovery manager may instead perform error recovery for the flash memory circuit using error recovery techniques that rely on redundancy data that is stored on other flash memory circuits in the flash memory device, such as redundant array of independent disks (RAID) error recovery techniques. In this manner, the subject system avoids utilizing processing, power, memory, and/or bandwidth resources to perform error recovery techniques that are unlikely to recover data from a given flash memory circuit of the flash memory device.

The system100includes a flash memory device110and a host device130. The flash memory device110includes one or more flash memory circuits112A-N, a controller114, a random access memory (RAM)122and an interface124. The controller114includes one or more decoders116, such as error-correcting code (ECC) decoders, one or more encoders118, such as ECC encoders, and error recovery handler115. The one or more decoders116, the one or more encoders118, and/or the error recovery handler115may be one or more dedicated circuits of the controller114, may be implemented via firmware running on the controller114, and/or may be one or more circuits separate from the controller114.

The interface124of the flash memory device110couples the flash memory device110to the host device130. The interface124may be a wired interface, such as a Personal Computer Memory Card International Association (PCMCIA) interface, a Serial AT Attachment (SATA) interface, a universal serial bus (USB) interface, or generally any wired interface. Alternatively, or in addition, the interface124may be a wireless interface, such as wireless SATA, Bluetooth, or generally any wireless interface.

The controller114is operable to read data from, and write data to, the flash memory circuits112A-N. For example, the controller114receives data, such as a stream of data, from the host device130via the interface124, where the data is then written to one or more of the flash memory circuits112A-N. The flash memory circuits112A-N may each include one or more physical blocks, such as NAND blocks and/or NOR blocks. The physical blocks may each include one or more physical pages. The controller114may utilize the RAM122to assist with reading/writing data to/from the flash memory circuits112A-N.

For example, the RAM122may be used as a buffer for rate control, or may otherwise be used to store information (e.g., error counts, block error maps, variables, physical block status, logical to physical address mapping tables, endurance/retention data, settings, etc.) utilized by the controller114to read/write data to/from the flash memory circuits112A-N, as well as recover data from the flash memory circuits112A-N. Since the RAM122may be volatile memory, the controller114may permanently store information in one or more of the flash memory circuits112A-N. When the flash memory device110is powered on, the controller114may retrieve the information from the one or more flash memory circuits112A-N and store the information in the RAM122.

The controller114may implement one or more algorithms or techniques in conjunction with reading and/or writing data to the flash memory circuits112A-N, such as security techniques (e.g. encryption), error correction coding techniques (e.g. low-density parity-check (LDPC)), compression techniques, redundancy techniques (e.g. redundant array of independent disks (RAID) techniques), etc. For example, the controller114may use redundancy techniques by generating logical sets of physical blocks across multiple flash memory circuits112A-N, which may be referred to as stripes, superblocks, or sets of blocks. The controller114may write data to a given set of blocks as a single unit. In this manner, the data is spread out across multiple of the flash memory circuits112A-B and may therefore be recoverable if one or more of the flash memory circuits fails. Example logical groupings of physical blocks of the flash memory circuits112A-N are discussed further below with respect toFIG. 2

The error recovery handler115may include one or more circuits for recovering data when a read error occurs, such as by utilizing the error correction coding and/or redundancy of the data written to the flash memory circuits112A-N. For example, the error recovery handler115may receive error recovery requests, such as from the controller114, that indicate a page of one of the flash memory circuits112A-N in which a read error has occurred and include error type information that indicates an error type of the read error that occurred. The error recovery handler115may select an error recovery technique for attempting to recover the data associated with the read error based on, for example, the error type information included in the error recovery request.

For example, each error type that may occur in the flash memory device110may be mapped to an error recovery technique. The error recovery technique mapped to a given error type may be based on the severity of the read error corresponding to the error type. For example, less severe error types may be mapped to read retry error recovery techniques, more severe error types may be mapped to error correction coding error recovery techniques, and the most severe error types may be mapped to redundancy error recovery techniques. If the error recovery handler115is unable to recover the data using the error recovery technique mapped to the error type, the error recovery handler115may progress through the error recovery techniques mapped to each successively more severe error type until the redundancy error recovery technique is reached. An example error recovery handler115and example error recovery techniques are discussed further below with respect toFIG. 3.

In the subject system, the error recovery handler115maintains read error information for each of the flash memory circuits112A-N. The read error information may include, for example, an error count that indicates a total number of read errors that have occurred on a given flash memory circuit112A and a block error map that indicates the blocks of the given flash memory circuit112A where at least one read error occurred. Example error counts and block error maps are discussed further below with respect toFIG. 4. The read error information may be used by the error recovery handler115to determine when the error recovery technique that is mapped to a given error type is unlikely to be able to recover the requested data. In this instance, the error recovery handler115may bypass the error recovery technique mapped to the error type and move to the error recovery technique mapped to the next successive error type in severity, and/or the error recovery handler115may move directly to the redundancy data error recovery technique.

Thus, the error recovery handler115is able to avoid utilizing resources for the error recovery technique mapped to the error type when the error recovery technique mapped to the error type is unlikely to be successful in recovering the requested data. An example process of error recovery handling that utilizes error counts and block error maps of the flash memory circuits112A-N is discussed further below with respect toFIG. 5.

In one or more implementations, one or more of the controller114, the error recovery handler115, the decoder116, the encoder118, and/or the interface124, and/or one or more portions thereof, may be implemented in software (e.g., firmware, subroutines, and/or code), may be implemented in hardware (e.g., an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a state machine, gated logic, discrete hardware components, and/or any other suitable devices) and/or a combination of both.

The example flash memory device110includes the interface124, the controller114, and one or more flash memory circuits112A-N. The flash memory circuits112A-N each include one or more physical blocks202A-P of flash memory, which may also be referred to as blocks202A-P. The flash memory circuit112A includes the blocks202A-D, the flash memory circuit112B includes the blocks202E-H, the flash memory circuit112C includes the blocks202I-L, and the flash memory circuit112N includes the blocks202M-P. Each of the blocks202A-P may include one or more physical pages of flash memory. The individual physical pages of the blocks202A-P may be the smallest unit that can be written to in the flash memory circuits112A-N and may be, for example, 8-16 kilobytes in size. In one or more implementations, a flash memory circuit112A may be 16 Gigabytes in size and may include 4,252 blocks each of which includes 256 pages with each page storing 17,760 bytes.

As shown inFIG. 2, the controller114logically groups the blocks202A-P of the flash memory circuits112A-N into logical sets of blocks210A-N, where each of the sets of blocks210A-N includes at least one block from each of the flash memory circuits112A-N. The error recovery handler115may use each of the sets of blocks210A-N as individual RAID stripes with parity/ECC data to perform data recovery when requested data cannot be read one or more blocks202A-P within the individual sets of blocks210A-N. In this manner, data written to the flash memory circuits112A-N can still be recovered when one or more of the flash memory circuits112A-N, and/or one more of the blocks202A-P therein, fails. In one or more implementations, the sets of blocks210A-N may be referred to as stripes, superblocks, logical units, etc.

As shown inFIG. 2, the set of blocks210A includes the block202A of the flash memory circuit112A, the block202E of the flash memory circuit112B, the block202I of the flash memory circuit112C, and the block202M of the flash memory circuit112N. The set of blocks210B includes the block202B of the flash memory circuit112A, the block202F of the flash memory circuit112B, the block202I of the flash memory circuit112C, and the block202N of the flash memory circuit112N. The set of blocks210C includes the block202C of the flash memory circuit112A, the block202G of the flash memory circuit112B, the block202K of the flash memory circuit112C, and the block202O of the flash memory circuit112N. The set of blocks210N includes the block202D of the flash memory circuit112A, the block202H of the flash memory circuit112B, the block202L of the flash memory circuit112C, and the block202P of the flash memory circuit112N.

In one or more implementations, one or more of the controller114and/or the interface124, and/or one or more portions thereof, may be implemented in software (e.g., firmware, subroutines, and/or code), may be implemented in hardware (e.g., an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a state machine, gated logic, discrete hardware components, and/or any other suitable devices) and/or a combination of both.

FIG. 3illustrates an example error recovery handler115in an example flash memory device110in accordance with one or more implementations. Not all of the depicted components may be required, however, and one or more implementations may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, or fewer components may be provided.

The example flash memory device110includes RAM122and the controller114which includes the error recovery handler115. The error recovery handler115includes an error recovery manager circuit302, a read retry error recovery circuit306A, an error correction coding (ECC) error recovery circuit306B, and a redundancy data error recovery circuit306C. For explanatory purposes, the error recovery manager circuit302and the error recovery circuits306A-C are illustrated as being part of the controller114. However, one or more of the error recovery manager circuit302and/or the error recovery circuits306A-C may be physically separate from the controller114, such as separate circuits and/or separate hardware.

The error recovery circuits306A-C each implements a different error recovery technique that may be utilized to attempt to recover data from a page (or multiple pages) in which a read error occurred. For example, the read retry error recovery circuit306A may implement an error recovery technique that performs one or more read retries, the ECC error recovery circuit306B may implement an error recovery technique that utilizes the error correction coding (e.g., LDPC) of the data stored on the flash memory circuits112A-N, and the redundancy data error recovery circuit306C may implement an error recovery technique that utilizes the redundancy, such as through RAID, of the data stored on the flash memory circuits112A-N.

Accordingly, each of the error recovery circuits306A-C performs one or more read accesses on one or more of the flash memory circuits112A-N to implement the error recovery techniques. For example, the read retry error recovery circuit306A may perform one or two read accesses on one of the flash memory circuits112A-N that includes the page in which a read error occurred. The ECC error recovery circuit306B may perform, for example, eight or nine read accesses on one of the flash memory circuits112A-N that includes the page in which the read error occurred. The redundancy data error recovery circuit306C may perform, for example, thirty to forty read accesses on one or more of the flash memory circuits112A-N.

The error recovery manager circuit302may store (e.g., in the RAM122), and/or be preconfigured with, a mapping between each different error type and one of the error recovery circuits306A-C to be utilized for attempting to recover the data stored in the page when a read error having the error type occurs. Since, the number of read accesses utilized by the error recovery circuits306A-C increases from the read retry error recovery circuit306A (e.g., 1-2 read accesses) to the ECC error recovery circuit306B (e.g., 8-9 read accesses) to the redundancy data error recovery circuit306C (e.g., 30-40 read accesses), the error types may be mapped to the error recovery circuit that is capable of recovering data when the error type occurs utilizing the fewest number of read accesses.

For example, data integrity error types (e.g., the returned data is not what the host device130expected) and erased page error types (e.g., the host device130requested a page that returned no data) may be mapped to the read retry error recovery circuit306A, unrecoverable error types may be mapped to the ECC error recovery circuit306B, and flash memory circuit offline (e.g. die offline) error types and cyclic redundancy check (CRC) error types may be mapped to the redundancy data error recovery circuit306C.

In operation, when the controller114encounters a read error when attempting to read data from a page of one of the blocks202A-P of one of the flash memory circuits112A-N, the controller114communicates an error recovery request to the error recovery manager circuit302. The error recovery request may include error type information that identifies an error type corresponding to the read error and may also include an address or identifier of the page in which the read error occurred. The error recovery manager circuit302attempts to recover the data stored in the page in which the read error occurred using the one of the error recovery circuits306A-C mapped to the error type of the error recovery request. For example, the error recovery manager circuit302may pass the error recovery request to the one of the error recovery circuits306A-C that is mapped to the error type.

If the error recovery request is passed to the read retry error recovery circuit306A and the read retry error recovery circuit306A is unable to recover the data stored in the page, the error recovery manager circuit302passes the error recovery request to the ECC error recovery circuit306B. If the ECC error recovery circuit306B is unable to recover the data stored in the page, the error recovery manager circuit302passes the error recovery request to the redundancy data error recovery circuit306C. Thus, if an error recovery request having an error type mapped to the read retry error recovery circuit306A is passed to the ECC error recovery circuit306B and then to the redundancy data error recovery circuit306C, an additional 9-11 read accesses may be performed as compared to if the error recovery request had been passed directly to the redundancy data error recovery circuit306C. In instances when one of the flash memory circuits112A-N is beginning to malfunction, e.g., due to age or other factors, the number of read errors may increase dramatically and the extra 9-11 read accesses for each such read error may overwhelm the flash memory device110.

In the subject system, the error recovery manager circuit302maintains, e.g., in the RAM122, an error count and a block error map for each of the flash memory circuits112A-N. Example data structures storing the error counts and the block error maps are discussed further below with respect toFIG. 4. The error count for a given flash memory circuit112A indicates the total number of read errors that have occurred on the flash memory circuit112A. The block error map indicates the particular blocks of the given flash memory circuit112A in which at least one of the read errors has occurred. In one or more implementations, the error recovery manager circuit302may reset the error counts and/or the block error maps at periodic intervals, such as every second, every ten seconds, or generally any periodic or aperiodic interval.

When the error recovery manager circuit302receives an error recovery request for a page that has an error type mapped to the read retry error recovery circuit306A or the ECC error recovery circuit306B, the error recovery manager circuit302determines a likelihood of the respective error recovery circuits306A-B being able to recover the data stored in the page, such as based on the error count and/or block error map of the one of the flash memory circuits112A-N that includes the page. For example, if the error count exceeds a certain threshold and/or the block error map indicates that the read errors are occurring in at least a certain percentage (or number) of blocks of the one of the flash memory circuits112A-N, the error recovery manager circuit302may determine that there is a low likelihood of either of the respective error recovery circuits306A-B being able to recover the data stored in the page.

When the error recovery manager circuit302determines that there is a low likelihood of the respective error recovery circuits306A-B being able to recover the data stored in the page, the error recovery manager circuit302bypasses the one of the error recovery circuits306A-B mapped to the error type and passes the error recovery request directly to the redundancy data error recovery circuit306C. An example process of bypassing the one of the error recovery circuits306A-B mapped to the error type of error recovery requests is discussed further below with respect toFIG. 5.

In one or more implementations, one or more of the controller114, the error recovery handler115, the error recovery manager circuit302, the read retry error recovery circuit306A, the ECC error recovery circuit306B, and/or the redundancy data error recovery circuit306C, and/or one or more portions thereof, may be implemented in software (e.g., firmware, subroutines, and/or code), may be implemented in hardware (e.g., an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a state machine, gated logic, discrete hardware components, and/or any other suitable devices) and/or a combination of both.

The example data structures stored in the random access memory122include an error count table402and one or more block error maps404A-N. The error count table402may store a separate error count for each of the flash memory circuits112A-N. Each error count may reflect the total number of read errors that have occurred in the corresponding one of the flash memory circuits112A-N. Thus, when an error recovery request is received by the error recovery manager circuit302for one of the flash memory circuits112A-N, such as the flash memory circuit112A, the error recovery manager circuit302may increment the error count for the flash memory circuit112A.

The block error maps404A-N may be, e.g., bitmaps and may indicate the particular blocks202A-P of each of the flash memory circuits112A-N in which at least one read error has occurred. Thus, the block error map404A indicates that at least one read error has occurred in three of the blocks202A-D of the flash memory circuit112A. The block error map404B indicates that at least one read error has occurred in all of the blocks202E-H of the flash memory circuit112B. The block error map404C indicates that at least one read error has occurred in most of the blocks202I-L of the flash memory circuit112C. The block error map404N indicates that at least one read error has occurred in only one of the blocks202M-P of the flash memory circuit112N.

Thus, when an error recovery request is received by the error recovery manager circuit302for a page of one of the flash memory circuits112A-N, such as the flash memory circuit112A, the error recovery manager circuit302retrieves the block error map404A for the flash memory circuit112A and sets the bit of the block error map404A to one for the one of the blocks202A-D of the flash memory circuit112A that contains the page. If the bit of the block error map404A is already set to one, the error recovery manager circuit302does not change the block error map404A.

Accordingly, the error recovery manager circuit302may utilize the error counts of the error count table402to determine when a sufficiently large sample size of read errors has occurred in one or more of the flash memory circuits112A-N, such as the flash memory circuit112A. When the error count of the given flash memory circuit112A indicates that the sample size of read errors is sufficiently large, the error recovery manager circuit302can then retrieve and analyze the block error map404A corresponding to the flash memory circuit112A. The analysis of the block error map404A may be used to determine whether the read errors are occurring in one or a few bad blocks of the flash memory circuit112A, or the read errors are occurring throughout the flash memory circuit112A, which may be an indication that the flash memory circuit112A is going bad and will soon be unusable and/or offline.

FIG. 5illustrates a flow diagram of an example process500of error recovery handling in accordance with one or more implementations. For explanatory purposes, the example process500is described herein with reference to the error recovery manager circuit302and the error recovery circuits306A-C ofFIG. 3; however, the example process500is not limited to the error recovery manager circuit302or the error recovery circuits306A-C ofFIG. 3, and one or more blocks of the example process500may be performed by one or more other components of the error recovery handler115and/or the controller114. Further for explanatory purposes, the blocks of the example process500are described herein as occurring in serial, or linearly. However, multiple blocks of the example process500may occur in parallel. In addition, the blocks of the example process500need not be performed in the order shown and/or one or more of the blocks of the example process500need not be performed.

The example process500begins when the error recovery manager circuit302receives an error recovery request (502). For example, the controller114may encounter a read error when attempting to read data from one or more pages of one of the blocks202A-P of one of the flash memory circuits112A-N, such as a page of the block202A of the flash memory circuit112A. Responsive to the read error, the controller114generates an error recovery request that includes an address (or otherwise identifies) the page of the block202A of the flash memory circuit112A in which the read error occurred, and that includes error type information that indicates the error type of the read error. In one or more implementations, the error type information may also include information indicating whether the read error occurred while attempting to recover the data stored in the page using one of the error recovery circuits306A-C.

The error recovery manager circuit302obtains the error type information and the address of the page from the error recovery request (504). The error recovery manager circuit302identifies the flash memory circuit112A and the block202A that contain the page, such as based on the address of the page (506). The error recovery manager circuit302determines whether the flash memory circuit112A has been marked as offline (508). For example, when certain criteria are met with respect to the flash memory circuit112A (as is discussed further below), the error recovery manager circuit302may mark the flash memory circuit112A as offline, such as by storing an indication of the same in the RAM122. In one or more implementations, the error recovery manager circuit302may mark the flash memory circuit112A as being offline when the criteria is met regardless of whether the flash memory circuit112A is actually offline (or is potentially going bad and will soon be offline).

If the error recovery manager circuit302determines that the flash memory circuit112A is marked as offline (508), the error recovery manager circuit302utilizes the redundancy data error recovery circuit306C to attempt to recover the data stored in the page identified in the error recovery request irrespective of the one of the error recovery circuits306A-C that is mapped to the error type information included in the error recovery request (532). If the error recovery manager circuit302determines that the flash memory circuit112A is not marked as offline, the error recovery manager circuit302increments the error count for the flash memory circuit112A, such as in the error count table402stored in the RAM122(510).

The error recovery manager circuit302also updates the block error map for the flash memory circuit112A, such as the block error map404A stored in the RAM122, to reflect that the read error occurred in the block202A (512). For example, the block error map404A may be a bitmap that stores a value of 1 at each index corresponding to a block number of a block in which a read error occurred, and stores a value of 0 at each index corresponding to a block number of a block in which a read error has not occurred. Thus, for the block202A, the error recovery manager circuit may set the bit at the first index (e.g.,0) to a value of 1, if the bit is not already set to a value of 1. If the bit is already set to a value of 1, the value of the bit remains unchanged, e.g., remains a value of 1.

The error recovery manager circuit302determines whether the error type information included in the error recovery request is mapped to the redundancy data error recovery circuit306C (514). Alternatively, or in addition, the error recovery manager circuit302may determine whether the error recovery request corresponds to a failed attempt to recover the data stored in the page using the ECC error recovery circuit306B. In either instance, the error recovery manager circuit302utilizes the redundancy data error recovery circuit306C to attempt to recover the data stored in the page (532).

If the error recovery manager circuit302determines that the error type information included in the error recovery request is not mapped to the redundancy data error recovery circuit306C, the error recovery manager circuit302retrieves the error count for the flash memory circuit112A, such as from the error count table402stored in the RAM122(516). The error recovery manager circuit302determines whether the error count for the flash memory circuit112A satisfies an error count criterion (518). The error count criterion may be satisfied, for example, when the error count exceeds an error count threshold, such as 2000 errors, 3000 errors, or generally any number of errors. If the error recovery manager circuit302determines that the error count for the flash memory circuit112A does not satisfy the error count criterion (518), the error recovery manager circuit302utilizes the one of the error recovery circuits306A-B that is mapped to the error type information included in the error recovery request to attempt to recover the data stored in the page (520).

In one or more implementations, if the error recovery request was generated from an attempt to recover the data using one of the error recovery circuits306A-B (e.g., as indicated by the error type information), the error recovery manager circuit302may utilize the next error recovery circuit306B or306C in error severity, rather than the one of the error recovery circuits306A-B that is mapped to the error type.

If the error recovery manager circuit302determines that the error count for the flash memory circuit112A satisfies the error count threshold (518), the error recovery manager circuit302retrieves the block error map for the flash memory circuit112A, such as the block error map404A stored in the RAM122(522). The error recovery manager circuit302determines whether the block error map404A for the flash memory circuit112A satisfies a block error map criterion (524). For example, the block error map criterion may be satisfied when the block error map indicates that read errors have occurred in at least a percentage of the blocks202A-D of the flash memory circuit112A, such as at least 80% of the block202A-D, at least 90% of the blocks202A-D, or generally at least any percentage of the blocks202A-D.

Thus, in order to determine the number of blocks202A-D of the flash memory circuit112A in which the read errors have occurred, the error recovery manager circuit302may have to count the number of indices of the block error map404A that store a value of 1. Since this analyzing of the block error map404A may consume processing, memory, and/or power resources of the flash memory device110, the error recovery manager circuit302may only process the block error map404A when the error count for the flash memory circuit112A has been determined to satisfy the error count criterion (518), which may be a simpler determination than processing the block error map404A. Thus, the error count of the flash memory circuit112A may be considered as a read error sample size when the error count is used to determine whether to expend the processing, memory, and/or power resources on analyzing the block error map404A for flash memory circuit112A.

If the error recovery manager circuit302determines that the block error map404A does not satisfy the block error map criterion (524), the error recovery manager circuit302utilizes the one of the error recovery circuits306A-B that is mapped to the error type information included in the error recovery request to attempt to recover the data stored in the page (520). If the error recovery manager circuit302determines that the block error map404A satisfies the block error map criterion (524), the error recovery manager circuit302determines whether the flash memory circuit112A is marked as potentially offline (526).

For example, the first time the error recovery manager circuit302determines that both criterions (518,524) are satisfied for a given flash memory circuit112A, the error recovery manager circuit302marks the flash memory circuit112A as potentially offline, and the next time that both criterions are satisfied for the flash memory circuit112A, the error recovery manager circuit302marks the flash memory circuit112A as being offline. Once a given flash memory circuit112A has been marked as offline, the error recovery manager circuit302can move directly to utilizing the redundancy data error recovery circuit306C for subsequently error recovery requests for pages of the flash memory circuit112A, thereby bypassing steps (514)-(530) and conserving the processing, memory, and/or power resources associated therewith.

If the error recovery manager circuit302determines that the flash memory circuit112A is not marked as potentially offline (526), the error recovery manager circuit302marks the flash memory circuit112A as potentially offline, such as by storing an indication of the same in the RAM122(528). In one or more implementations, the error recovery manager circuit302may reset the error count and the block error map404A for the flash memory circuit112A upon marking the flash memory circuit112A as being potentially offline. Alternatively, or in addition, the error recovery manager circuit302may reset all of the error counts stored in the error count table402, and all of the error maps404A-N on a periodic basis, such as every 500 milliseconds, 1 second, 5 seconds, 10 seconds, or any amount of time. However, the indications of whether the flash memory circuits112A-N are offline or potentially offline may not be reset at the periodic intervals.

If the error recovery manager circuit302determines that the flash memory circuit112A is marked as potentially offline (526), the error recovery manager circuit302marks the flash memory circuit112A as offline, such as by storing an indication of the same in the RAM122(530). After marking the flash memory circuit112A as potentially offline or offline, the error recovery manager circuit302utilizes the redundancy data error recovery circuit306C to attempt to recover the data stored in the page identified in the error recovery request irrespective of the one of the error recovery circuits306A-C that is mapped to the error type information included in the error recovery request (532).

In one or more implementations, the outcome of the error count determination (518) and the outcome of the block error map determination (524) may be collectively indicative of a likelihood that the data stored in the page can be recovered using the one of the error recovery circuits306A-B that is mapped to the error type information of the error recovery request. For example, when the error count does not satisfy the error count criterion (518) or the block error map does not satisfy the error map criterion (524), the error recovery manager circuit302may determine that the likelihood is high that the page can be recovered using the one of the error recovery circuits306A-B that is mapped to the error type information of the error recovery request. In such instances, the high likelihood may be construed as satisfying a likelihood criterion and the error recovery manager circuit302may attempt to recover the data using the one of the error recovery circuits306A-B that is mapped to the error type information of the error recovery request.

However, when the error count satisfies the error count criterion and the block error map satisfies the error map criterion, the error recovery manager circuit302may determine that there is a low likelihood that the data can be recovered using the one of the error recovery circuits306A-B that is mapped to the error type information included in the error recovery request (520). In this instance, the error recovery manager circuit302may determine that the low likelihood does not satisfy the likelihood criterion and the error recovery manager circuit302utilizes the redundancy data error recovery circuit to attempt to recover the data (532), rather than the one of the error recovery circuits306A-B that is mapped to the error type information included in the error recovery request.

While the above discussion primarily refers to microprocessor or multi-core processors that execute software, one or more implementations are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In one or more implementations, such integrated circuits execute instructions that are stored on the circuit itself.