Methods of programming different portions of memory cells of a string of series-connected memory cells

Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

TECHNICAL FIELD

The present disclosure relates generally to memory and, in particular, in one or more embodiments, the present disclosure relates to memory architecture and its operation.

BACKGROUND

Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.

Memory cells are typically erased before they are programmed to a desired data state. For example, memory cells of a particular block of memory cells may first be erased and then selectively programmed. For a NAND array, a block of memory cells is typically erased by grounding all of the access lines (e.g., word lines) in the block and applying an erase voltage to the channel regions of the memory cells (e.g., through data lines and source connections) in order to remove charges that might be stored on data-storage structures (e.g., floating gates or charge traps) of the block of memory cells. Typical erase voltages might be on the order of 25V before completion of an erase operation.

A general goal in semiconductor memory seeks to increase the size of blocks of memory cells, e.g., increasing the number of memory cells in a column of memory cells and/or increasing the number of memory cells in a row of memory cells. However, increasing block size may lead to latency issues as memories perform housekeeping tasks on these larger blocks of memory cells. This, in turn, may limit the physical size of the blocks of memory in order to meet customer and/or industry standard requirements.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions. The term conductive as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term connecting as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

FIG. 1is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device)100, in communication with a second apparatus, in the form of a processor130, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones and the like. The processor130, e.g., a controller external to the memory device100, may be a memory controller or other external host device.

Memory device100includes an array of memory cells104logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown inFIG. 1) of at least a portion of array of memory cells104are capable of being programmed to one of at least two data states.

A row decode circuitry108and a column decode circuitry110are provided to decode address signals. Address signals are received and decoded to access the array of memory cells104. Memory device100also includes input/output (I/O) control circuitry112to manage input of commands, addresses and data to the memory device100as well as output of data and status information from the memory device100. An address register114is in communication with I/O control circuitry112and row decode circuitry108and column decode circuitry110to latch the address signals prior to decoding. A command register124is in communication with I/O control circuitry112and control logic116to latch incoming commands. A count register126may be in communication with the control logic116to store count data, such as data representative of respective numbers of read cycles for different portions of the array of memory cells104. Although depicted as a separate storage register, count register126may represent a portion of the array of memory cells104.

A controller (e.g., the control logic116internal to the memory device100) controls access to the array of memory cells104in response to the commands and generates status information for the external processor130, i.e., control logic116is configured to perform access operations (e.g., read operations, program operations and/or erase operations) in accordance with embodiments described herein. The control logic116is in communication with row decode circuitry108and column decode circuitry110to control the row decode circuitry108and column decode circuitry110in response to the addresses.

Control logic116is also in communication with a cache register118. Cache register118latches data, either incoming or outgoing, as directed by control logic116to temporarily store data while the array of memory cells104is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data is passed from the cache register118to data register120for transfer to the array of memory cells104; then new data is latched in the cache register118from the I/O control circuitry112. During a read operation, data is passed from the cache register118to the I/O control circuitry112for output to the external processor130; then new data is passed from the data register120to the cache register118. A status register122is in communication with I/O control circuitry112and control logic116to latch the status information for output to the processor130.

Memory device100receives control signals at control logic116from processor130over a control link132. The control signals might include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, a write enable WE#, a read enable RE#, and a write protect WP#. Additional or alternative control signals (not shown) may be further received over control link132depending upon the nature of the memory device100. Memory device100receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor130over a multiplexed input/output (I/O) bus134and outputs data to processor130over I/O bus134.

For example, the commands are received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and are written into command register124. The addresses are received over input/output (I/O) pins [7:0] of I/O bus134at10control circuitry112and are written into address register114. The data are received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry112and are written into cache register118. The data are subsequently written into data register120for programming the array of memory cells104. For another embodiment, cache register118may be omitted, and the data are written directly into data register120. Data are also output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins may be used in the various embodiments.

FIG. 2Ais a schematic of a portion of an array of memory cells200A as could be used in a memory of the type described with reference toFIG. 1, e.g., as a portion of array of memory cells104. Memory array200A includes access lines, such as word lines2020to202N, and a data line, such as bit line204. The word lines202may be connected to global access lines (e.g., global word lines), not shown inFIG. 2A, in a many-to-one relationship. For some embodiments, memory array200A may be formed over a semiconductor that, for example, may be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

Memory array200A might be arranged in rows (each corresponding to a word line202) and columns (each corresponding to a bit line204). Each column may include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings2060to206M. Each NAND string206might be connected (e.g., selectively connected) to a common source216and might include memory cells2080to208N. The memory cells208may represent non-volatile memory cells for storage of data. The memory cells208of each NAND string206might be connected in series between a select gate210(e.g., a field-effect transistor), such as one of the select gates2100to210M(e.g., that may be source select transistors, commonly referred to as select gate source), and a select gate212(e.g., a field-effect transistor), such as one of the select gates2120to212M(e.g., that may be drain select transistors, commonly referred to as select gate drain). Select gates2100to210Mmight be commonly connected to a select line214, such as a source select line, and select gates2120to212Mmight be commonly connected to a select line215, such as a drain select line. Although depicted as traditional field-effect transistors, the select gates210and212may utilize a structure similar to (e.g., the same as) the memory cells208. The select gates210and212might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

A source of each select gate210might be connected to common source216. The drain of each select gate210might be connected to a memory cell2080of the corresponding NAND string206. For example, the drain of select gate2100might be connected to memory cell2080of the corresponding NAND string2060. Therefore, each select gate210might be configured to selectively connect a corresponding NAND string206to common source216. A control gate of each select gate210might be connected to select line214.

The drain of each select gate212might be connected to the bit line204for the corresponding NAND string206. For example, the drain of select gate2120might be connected to the bit line2040for the corresponding NAND string2060. The source of each select gate212might be connected to a memory cell208Nof the corresponding NAND string206. For example, the source of select gate2120might be connected to memory cell208Nof the corresponding NAND string2060. Therefore, each select gate212might be configured to selectively connect a corresponding NAND string206to the common bit line204. A control gate of each select gate212might be connected to select line215.

The memory array inFIG. 2Amight be a three-dimensional memory array, e.g., where NAND strings206may extend substantially perpendicular to a plane containing the common source216and to a plane containing a plurality of bit lines204that may be substantially parallel to the plane containing the common source216.

Typical construction of memory cells208includes a data-storage structure234(e.g., a floating gate, charge trap, etc.) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate236, as shown inFIG. 2A. The data-storage structure234may include both conductive and dielectric structures while the control gate236is generally formed of one or more conductive materials. In some cases, memory cells208may further have a defined source/drain (e.g., source)230and a defined source/drain (e.g., drain)232. Memory cells208have their control gates236connected to (and in some cases form) a word line202.

A column of the memory cells208may be a NAND string206or a plurality of NAND strings206selectively connected to a given bit line204. A row of the memory cells208may be memory cells208commonly connected to a given word line202. A row of memory cells208can, but need not, include all memory cells208commonly connected to a given word line202. Rows of memory cells208may often be divided into one or more groups of physical pages of memory cells208, and physical pages of memory cells208often include every other memory cell208commonly connected to a given word line202. For example, memory cells208commonly connected to word line202Nand selectively connected to even bit lines204(e.g., bit lines2040,2042,2044, etc.) may be one physical page of memory cells208(e.g., even memory cells) while memory cells208commonly connected to word line202Nand selectively connected to odd bit lines204(e.g., bit lines2041,2043,2045, etc.) may be another physical page of memory cells208(e.g., odd memory cells). Although bit lines2043-2045are not explicitly depicted inFIG. 2A, it is apparent from the figure that the bit lines204of the array of memory cells200A may be numbered consecutively from bit line2040to bit line204M. Other groupings of memory cells208commonly connected to a given word line202may also define a physical page of memory cells208. For certain memory devices, all memory cells commonly connected to a given word line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to word lines2020-202N(e.g., all NAND strings206sharing common word lines202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

FIG. 2Bis another schematic of a portion of an array of memory cells200B as could be used in a memory of the type described with reference toFIG. 1, e.g., as a portion of array of memory cells104. Like numbered elements inFIG. 2Bcorrespond to the description as provided with respect toFIG. 2A.FIG. 2Bprovides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array200B may incorporate vertical structures which may include semiconductor pillars where a portion of a pillar may act as a channel region of the memory cells of NAND strings206. The NAND strings206may be each selectively connected to a bit line2040-204Mby a select transistor212(e.g., that may be drain select transistors, commonly referred to as select gate drain) and to a common source216by a select transistor210(e.g., that may be source select transistors, commonly referred to as select gate source). Multiple NAND strings206might be selectively connected to the same bit line204. Subsets of NAND strings206can be connected to their respective bit lines204by biasing the select lines2150-215Kto selectively activate particular select transistors212each between a NAND string206and a bit line204. The select transistors210can be activated by biasing the select line214. Each word line202may be connected to multiple rows of memory cells of the memory array200B. Rows of memory cells that are commonly connected to each other by a particular word line202may collectively be referred to as tiers.

FIG. 3is a conceptual depiction of a portion of a block (e.g., physical block) of memory cells300as could be used in a memory of the type described with reference toFIG. 1. Data Lines2040and2041ofFIG. 3might correspond to data lines2040and2041ofFIG. 2B. Channel regions23800and23801might represent the channel regions of different strings of series-connected memory cells (e.g., NAND strings206ofFIGS. 2A-2B) selectively connected to the data line2040in response to select lines2150and2151, respectively. Similarly, channel regions23810and23811might represent the channel regions of different strings of series-connected memory cells (e.g., NAND strings206ofFIGS. 2A-2B) selectively connected to the data line2041in response to select lines2150and2151, respectively. The access lines2020-202Ndepicted inFIG. 2Amight be represented inFIG. 3by the access lines202a0-202aL,202d0-202d3and202b0-202bU, where N might be equal to L+U+6 in this example. A memory cell (not depicted inFIG. 3) may be formed at each intersection of an access line202and a channel region238, and the memory cells corresponding to a signal channel regions may collectively form a series-string of memory cells (e.g., a NAND string ofFIGS. 2A-2B).

Access lines202d0-202d3may represent separator (e.g., dummy) access lines. While four dummy access lines202dare depicted, other numbers might be used. In addition, these dummy access lines202dmay correspond to dummy memory cells, e.g., memory cells not intended to store user data. The dummy memory cells are typically not accessible to a user of the memory, and are typically incorporated into the string of series-connected memory cells for operational advantages. For example, as the number of access lines202between a source216and a data line204becomes larger, e.g., in response to increasing demands for memory capacity, physical limitations of technology may warrant forming the structure channel regions238in two parts as the aspect ratio of the hole becomes too large to form the entire structure reliably. As an example, the structure of the block of memory cells300might be formed to include up to access line202d1before a first portion of a channel region238is formed, and then a subsequent portion of the block of memory cells300might be formed to include up to the select lines215before a remaining portion of the channel region238is formed. To improve the conductivity between the two portions of the channel region238, a conductive region might be formed between them. However, this may lead to different operating characteristics of the memory cells formed near this conductive region, such as is common for memory cells nearest the source216and those nearest a data line204. By operating these memory cells as dummy memory cells, such differences in operating characteristics might generally be mitigated.

Such dummy access lines202dmay collectively form a separator portion245between one portion (e.g., deck)2401of a block of memory cells300(or one portion2401of each string of series-connected memory cells) and another portion (e.g., deck)2400of the block of memory cells300(or another portion2400of each string of series-connected memory cells). The portion240, is closer to one end of the strings of series-connected memory cells, e.g., closer to the select lines215and data lines204, and the portion2400is closer to an opposite end of the strings of series-connected memory cells, e.g., closer to the select lines214and source216. Each portion240might be considered a logical block of memory cells. The structure depicted and described with reference toFIG. 3will be used to describe various embodiments herein.

As the access lines of the separator portion245may not be operated to stored user data, the might be used to shield one portion240of the block of memory cells300from operations on the other portion240of the block of memory cells300. For example, an erase operation might be performed on memory cells of the portion2400without erasing memory cells of the portion2401. This might be accomplished by applying an erase voltage (e.g., 20V) to the channel regions238, such as through the data lines204and the source216while applying an erase select voltage (e.g., 1V) to access lines202corresponding to the memory cells intended for erasure, and while applying an erase inhibit voltage (e.g., 20V) to access lines202corresponding to the memory cells for which erasure is not desired. For example, to erase the portion2400, the erase voltage might be applied to the channel regions238of the block of memory cells while applying the erase select voltage to the access lines202aof the portion2400, and while applying the erase inhibit voltage to the access lines202bof the portion2401. The access lines202dmight receive an intermediate voltage (e.g., 10V) during this time to mitigate stress between the access lines202aand202b. Additional detail of performing an erase operation on this type of structure might be found with reference to U.S. Patent Application Publication No. 2017/0076805 A1 issued to Goda et al.

Programming of a block of memory cells that can be erased in portions may present certain disadvantages. For example, it is common to program a block of memory cells from one end (e.g., from an access line202closest to the source216) to the other end (e.g., to an access line202closest to the data line204). However, in this scenario, if the memory cells of the portion2401are already programmed, the memory cells of the portion240omay experience unacceptable levels of program disturb in one or more lower data states (e.g., a lowest or initial data state). Various embodiments seek to mitigate this issue.

FIGS. 4A-4Bare flowcharts of methods of operating a memory in accordance with embodiments. InFIG. 4A, at401, a first portion (e.g., portion2400or2401) of memory cells of a string of series-connected memory cells closer to a particular end of the string of series-connected memory cells (e.g., the end nearest the source216or the end nearest the data line204, respectively) than a second portion (e.g., portion2401or2400, respectively) of memory cells is programmed in an order from a different (e.g., opposite) end of the string of series-connected memory cells (e.g., the end nearest the data line204or the end nearest the source216, respectively) to the particular end. For example, if the first portion of memory cells corresponds to those memory cells of the portion2400, programming of the memory cells of the portion2400might begin with the memory cells coupled to the access line202aLand proceed in order to the memory cells coupled to the access line202a0, while programming of the memory cells of the portion2401might begin with the memory cells coupled to the access line202b0and proceed in order to the memory cells coupled to the access line202bU. Note that the memory cells of the portion2400might be programmed prior to programming the memory cells of the portion2401, and vice versa. Programming of a portion of memory cells may further include programming memory cells corresponding to one or more of the dummy access lines, e.g., the dummy access lines closest to that portion of memory cells.

For some embodiments, it may be desirable to make the order of programming one portion of memory cells dependent on whether the other portion of memory cells has previously been programmed.FIG. 4Bis a flowchart of such a method. InFIG. 4B, at411, it is determined whether a first portion (e.g., portion2400or2401) of memory cells of a string of series-connected memory cells closer to a particular end of the string of series-connected memory cells (e.g., the end nearest the source216or the end nearest the data line204, respectively) than a second portion (e.g., portion2401or2400, respectively) of memory cells of the string of series-connected memory cells is deemed to be programmed. Determination that the first portion of memory cells of the string of series-connected memory cells is deemed programmed might include determining whether the first portion of memory cells of the string of series-connected memory cells has been subjected to programming voltages after a most recent erase operation, e.g., in response to a programming operation. For example, where a portion2401of a block of memory cells300is the subject of a programming operation, each string of series-connected memory cells of the portion2401might be deemed to have been programmed even if each memory cell of a particular string of series-connected memory cells of the portion2401remains in its initial (e.g., erased) data state. Such determinations might include reading a flag having a value indicating that the portion240has experienced a programming operation. As an example, the flag might be stored in a reserved portion of the block of memory cells. The reserved portion of the block of memory cells might include memory cells of the portion2400or the portion2401.

If the first portion of memory cells is deemed to be programmed at413, the second portion of memory cells is programmed at415in an order from the particular end to a different (e.g., opposite) end of the string of series-connected memory cells. Alternatively, if the first portion of memory cells is not deemed to be programmed at413, the second portion of memory cells is programmed at417in an order from a different (e.g., opposite) end of the string of series-connected memory cells to the particular end.

It is noted that while programming one portion of a block of memory cells, the other portion may experience Vpass disturb. As is typical in the prior art, a programming operation may include a first portion used to precharge or seed the channel regions of memory cells of a block of memory cells to a precharge voltage level, a second portion used to boost the voltage level of the channel regions of strings of series-connected memory cells of the block of memory cells not intended for programming (e.g., to be inhibited) to a voltage level sufficient to inhibit programming of any memory cell of those strings of series-connected memory cells receiving a programming voltage, and a third portion used for programming one or more selected memory cells of other strings of memory cells of the block of memory cells. The first portion typically involves applying a voltage (e.g., Vcc or other supply voltage) to at least those data lines to be inhibited from programming (e.g., unselected data lines) while those data lines are connected to their respective channel regions (e.g., unselected channel regions) through the activation of the drain select gates and all memory cells associated with those channel regions. The second portion typically involves electrically floating those unselected channel regions, and then increasing the access line voltages to a pass voltage (e.g., Vpass) in order to boost the voltage level of the unselected channel regions. The voltage level of the pass voltage might be selected to reach a boosted voltage level of the unselected channel regions to a level sufficient to inhibit programming of any corresponding memory cell receiving a programming voltage in the third portion of the programming operation. For situations where a portion of the block of memory cells is already programmed, voltage levels necessary to activate those memory cells during the precharge portion would be higher.

Reductions in the voltage level of the pass voltage may facilitate a reduction in Vpass disturb. Various embodiments may alter the precharge portion of a programming operation and use GIDL (gate-induced drain leakage) as a mechanism to seed the unselected channel regions. GIDL would not need to rely on the activation of select gates or memory cells in order to seed the channel region, thus also avoiding the need to use higher access line voltages during the precharge portion of the programming operation.FIG. 5is a timing diagram generally depicting voltage levels of various nodes of a block of memory cells such as depicted inFIG. 3at various stages of a programming operation in accordance with such embodiments. WhileFIG. 5will be described in relation to the type of programming operation performed in response to a write command to store user data to the block of memory cells, the programming operation may further include preprogramming as is often used as part of an erase operation to mitigate risks of over erasing memory cells already in the erased data state.

Consider the block of memory cells300ofFIG. 3, wherein the memory cell formed at the intersection of the access line202b0and the channel region23800is selected for programming, but remaining memory cells are to be inhibited from programming. In this example, the access line202b0would be a selected access line, e.g., an access line selected for programming, while access lines202a0-202aL,202d0-202d3, and202b1-202bUwould be unselected access lines, e.g., access lines unselected for programming. Similarly, the channel region23800would be a selected channel region, while the channel regions23801,23810and23811would be unselected channel regions. Data line2040would be a selected data line, while data line2041would be an unselected data line. Select line2150would be a selected select line, while select line2151would be an unselected select line.

InFIG. 5, waveform550(WL sel) represents the waveform of a voltage level of the selected access line during a programming operation in accordance with an embodiment, while the waveform550′ represents the waveform of a voltage level of the selected access line during a programming operation of the prior art. The waveform552(WL unsel) represents the waveform of a voltage level of the unselected access lines during the programming operation in accordance with an embodiment, while the waveform552′ represents the waveform of a voltage level of an unselected access line during the programming operation of the prior art.

The waveform554(SGD sel) represents the waveform of a voltage level of a selected select line (e.g., drain select line) during the programming operation in accordance with an embodiment, while the waveform554′ represents the waveform of a voltage level of a selected select line during the programming operation of the prior art. The waveform556(SGD unsel) represents the waveform of a voltage level of an unselected select line (e.g., drain select line) during the programming operation in accordance with an embodiment, while the waveform556′ represents the waveform of a voltage level of an unselected select line during the programming operation of the prior art.

The waveform558(BL sel) represents the waveform of a voltage level of a selected data line (e.g., bit line) during the programming operation in accordance with an embodiment, while the waveform558′ represents the waveform of a voltage level of a selected data line during the programming operation of the prior art. The waveform560(BL unsel) represents the waveform of a voltage level of an unselected data line (e.g., bit line) during the programming operation in accordance with an embodiment, while the waveform560′ represents the waveform of a voltage level of an unselected data line during the programming operation of the prior art.

The waveform562(Chan sel) represents the waveform of a voltage level of a selected channel region during the programming operation in accordance with an embodiment, while the waveform562′ represents the waveform of a voltage level of a selected channel region during the programming operation of the prior art. The waveform564(Chan unsel) represents the waveform of a voltage level of an unselected channel region during the programming operation in accordance with an embodiment, while the waveform564′ represents the waveform of a voltage level of an unselected channel region during the programming operation of the prior art.

In the prior art programming operation, at time t0, the voltage level550′ of the selected access line, the voltage level552′ of the unselected access line, the voltage level554′ of the selected select line and the voltage level556′ of the unselected select line might be raised (e.g., biased) to some voltage level sufficient to activate their corresponding memory cells and select gates (e.g., drain select gates) while the voltage level558′ of the selected data and the voltage level560′ of the unselected data line might be raised (e.g., biased) to a voltage level such as Vcc. As a result, the voltage level562′ of the selected channel region and the voltage level564′ of the unselected channel region might be brought up to the voltage level data lines, such as Vcc. At time t1, the voltage level558′ of the selected data line might be lowered (e.g., discharged) to a reference voltage level, such as Vss (e.g., ground or 0V), and the voltage level556′ of the unselected select line might be lowered (e.g., discharged) to the reference voltage level. As a result, the voltage level562′ of the selected channel region may lower to the reference voltage due to its connection to the selected data line, while the unselected channel region may be left electrically floating as the select gate to the unselected data line is deactivated. The time period from time t0to time t2might correspond to the precharge portion of the programming operation.

At time t2, the voltage level550′ of the selected access line and the voltage level552′ of the unselected access line might be raised (e.g., biased) to some voltage level sufficient to boost the voltage level of the unselected channel region to a particular voltage level566sufficient to inhibit programming of a memory cell corresponding to the unselected channel region receiving a programming voltage on its corresponding selected access line. The time period from time t2to time t3might correspond to the boost portion of the programming operation.

At time t3, the voltage level550′ of the selected access line might be raised (e.g., biased) to a programming voltage, e.g., some voltage level sufficient to cause accumulation of charge on a data-storage structure of a memory cell corresponding to the selected access line and a selected channel region. At time t4, the voltage level550′ of the selected access line and the voltage level552′ of the unselected access line might be lowered (e.g., discharged) to the reference voltage, while at time t5, remaining voltage levels might be lowered (e.g., discharged) to the reference voltage. The time period from time t3to time t4might correspond to the programming portion of the programming operation.

In contrast to the prior art programming operation, at time t0for an embodiment, the voltage level550of the selected access line, the voltage level552of the unselected access line, the voltage level554of the selected select line and the voltage level556of the unselected select line might maintained at the reference voltage while the voltage level558of the selected data and the voltage level560of the unselected data line might be raised (e.g., biased) to a voltage level sufficient to induce GIDL, e.g., 3V. As a result, the voltage level562of the selected channel region and the voltage level564of the unselected channel region might be brought up to the voltage level data lines, e.g., 3V. At time t1, the voltage level558of the selected data line might be lowered (e.g., discharged) to the reference voltage, and the voltage level554of the selected select line might be raised (e.g., biased) to some voltage level sufficient to inhibit GIDL, e.g., 2V. As a result, the voltage level562of the selected channel region may lower to the reference voltage due to its connection to the selected data line, while the unselected channel region may be left electrically floating as the select gate to the unselected data line is deactivated. The time period from time t0to time t2might correspond to the precharge portion of the programming operation.

At time t2for the embodiment, the voltage level550of the selected access line and the voltage level552of the unselected access line might be raised (e.g., biased) to some voltage level sufficient to boost the voltage level of the unselected channel region to the particular voltage level566sufficient to inhibit programming of a memory cell corresponding to the unselected channel region receiving a programming voltage on its corresponding selected access line. Note that the voltage level550of the selected access line and the voltage level552of the unselected access line may be less than their corresponding voltage levels of the prior art programming operation. This is due in part to seeding the channel regions to a higher level, but because the access lines started at the reference voltage prior to boost, the boost may also be more efficient. The time period from time t2to time t3might correspond to the boost portion of the programming operation.

At time t3for the embodiment, the voltage level550of the selected access line might be raised (e.g., biased) to a programming voltage, e.g., some voltage level sufficient to cause accumulation of charge on a data-storage structure of a memory cell corresponding to the selected access line and a selected channel region. At time t4, the voltage level550of the selected access line and the voltage level552of the unselected access line might be lowered (e.g., discharged) to the reference voltage, while at time t5, remaining voltage levels might be lowered (e.g., discharged) to the reference voltage. The time period from time t3to time t4might correspond to the programming portion of the programming operation.

For some embodiments, apparatus may perform housekeeping operations. One such housekeeping operation is read count leveling. Read count leveling takes into account basic physics of the apparatus. When a page of memory cells of a block of memory cells of the type depicted inFIG. 3is accessed via a read command, that read command affects (e.g., disturbs) other pages of memory cells in the same block of memory cells. For example, in a block of memory cells with 256 logical pages of memory cells, accessing page 0 via a read command disturbs pages 1 through 255. No matter what page is accessed, the other pages in the block may be subject to the same disturb.

NAND providers typically provide a specification on a page level read capability. This number is generally not expressed as a limit for total page reads of a block of memory cells, however. Instead, it is typical to express the specification as a total number of supported reads for a block of memory cells divided by the number of pages contained in that block of memory cells. For example, in a block of memory cells having 256 logical pages of memory cells, and a page level read capability of 100,000, each page of memory cells of that block of memory cells might be read 100,000 times, or a single page of memory cells of that block of memory cells might be read 25,600,000. Each of these possibilities might produce the same level of read disturb on any memory cell of that block of memory cells.

When the number of reads for a block of memory cells exceeds the specification or other threshold (e.g., some threshold value less than the specification), valid data in that block of memory cells might be copied to a free block of memory cells, and then the initial block of memory cells might be erased an returned to the pool of free blocks of memory cells. This type of housekeeping operation on an array of memory cells might be performed in response to a stored value representative of the number of reads performed on the block of memory cells. This value may be stored in a register (e.g., the count register128ofFIG. 1), or it may be stored in a reserved portion of the block of memory cells or in some other predetermined block of memory cells. This value is typically updated each time a read operation is performed on the block of memory cells.

Where only a portion of a block of memory cells is erased, e.g., an upper deck of memory cells or a lower deck of memory cells, a read count maintained for the entire block of memory cells might lead to a premature indication that read count leveling is warranted. For example, the block of memory cells might be approaching a threshold value of its read count when one portion of the block of memory cells, e.g., a lower deck of memory cells, is erased. As the erase operation moots the read disturb with regard to the erased memory cells, it would be premature to perform read count leveling on the entire block of memory cells in response to the read count reaching the threshold value. In particular, while the upper deck of memory cells in this example may warrant read count leveling due to read disturb, the lower deck of memory cells would not have experienced the same level of disturb due to its recent erasure, e.g., it was not subjected to the same number of read as the upper deck of memory cells. To address this issue, various embodiments institute respective read counts for each portion (e.g., deck) of memory cells of the block of memory cells. Table 1 demonstrates the action on the read count for each portion of the block of memory cells.

As can be seen from Table 1, when a read operation is performed for any memory cell (e.g., any logical page of memory cells) of a block of memory cells where different portions (e.g., decks) may be individually erased, the respective read count may be incremented, e.g., increased by one, for both the count register corresponding to one portion (e.g., deck) of memory cells of that block of memory cells and the count register corresponding to another portion (e.g., deck) of memory cells of that block of memory cells. However, when one portion is erased, only its count register might be reset, e.g., to zero, while no action might be taken with respect to the other count register, e.g., it might maintain its existing read count value.

When the value of a read count reaches a read count threshold (e.g., a value corresponding to a page level read capability or some lesser value) for either portion of memory cells of the block of memory cells, that portion of memory cells might be copied to a block of memory cells having a free portion of memory cells, which could include the same block of memory cells if the other portion is free (e.g., erased) or some other block of memory cells. The portion of memory cells of the block of memory cells reaching the read count threshold might then be erased while taking no action on the other portion of memory cells of the block of memory cells, e.g., if the value of its read count is below the read count threshold. The erased portion of memory cells could then be marked as free, e.g., setting a flag within the block to a value indicating that the block is available for storage of new data, and its read count could be reset, e.g., to 0.

CONCLUSION