Semiconductor device and memory device

A semiconductor device includes a substrate, a controller chip, and memory chips. Wiring is formed on the substrate. The controller chip has a rectangular surface area, and is mounted on the substrate. The memory chips have quadrangular surface areas, and are superposed on the substrate on a first major side of the controller chip. The first major side defines a first direction and a first controller terminal block is formed along a first minor side thereof orthogonal to the first direction, and a second controller terminal block is formed along a second major side opposite to the first major side.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-188501, filed Sep. 11, 2013, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a memory device.

BACKGROUND

A semiconductor device having a controller and a memory chip mounted on a substrate is used as an exemplary semiconductor device equipped with a memory chip and a controller. In such semiconductor devices, a resin may be applied between the controller and the memory chip.

There is a need to reduce the cost of applying the resin between the controller and the memory chip. In addition, there is a need to increase the operational speed of the memory chip.

DETAILED DESCRIPTION

Embodiments provide a semiconductor device capable of increasing the operational speed of a memory chip while reducing cost of applying a resin between a controller and a memory chip.

In general, according to one embodiment, a semiconductor device includes a substrate, a controller chip and memory chips. Wiring is formed on the substrate. The controller chip has a rectangular surface area, and is mounted on the substrate. The memory chips have quadrangular surface areas, and are superposed on the substrate on a first major side of the controller chip. The first major side defines a first direction and a first controller terminal block is formed along a first minor side thereof orthogonal to the first direction, and a second controller terminal block is formed along a second major side opposite to the first major side.

A semiconductor device according to an embodiment will be described below in detail with reference to the accompanying drawings. It is not intended that the present disclosure is limited by this embodiment.

First Embodiment

FIG. 1is a plan view illustrating a schematic internal configuration of a semiconductor device according to a first embodiment.FIG. 2is aside view of the semiconductor device shown inFIG. 1as seen from a side of a controller chip. A semiconductor device (memory device)50includes a substrate1(shown inFIG. 2), a first memory chip (first nonvolatile semiconductor storage element)2, a second memory chip (second nonvolatile semiconductor storage element)3and a controller chip (semiconductor control element)4.

The substrate1is a wiring substrate which has wiring5on the surface layer and the inner layer. The first memory chip2and the second memory chip3are nonvolatile semiconductor storage elements, such as a NAND flash memory. The first memory chip2and the second memory chip3have quadrangular surfaces2aand3a, respectively, in plan view as shown inFIG. 1.

The controller chip4is a semiconductor control element for controlling the first memory chip2and the second memory chip3. For example, the controller chip4controls writing/reading of data to/from the first memory chip2and the second memory chip3. The controller chip4has a rectangular surface4ain plan view as shown inFIG. 1.

In the following description, among sides of the surface4aof the controller chip4, one long side is referred to as a first major side41aand the other long side is referred to as a second major side41b. Further, among sides of the surface4aof the controller chip4, one short side is referred to as a first minor side42aand the other short side is referred to as a second minor side42b. Furthermore, it is assumed that a direction along the first major side41aof the controller chip4is a direction parallel to the direction shown by the arrow X (first direction) and the direction along the first minor side42ais a direction parallel to the direction shown with the arrow Y (second direction).

The controller chip4, the first memory chip2and the second memory chip3are mounted on a mounting surface1aof the substrate1so that the surfaces4a,2aand3aare positioned opposite to the mounting surface1aof the substrate1. The first major side41aof the controller chip4faces the first memory chip and the second memory chip3. The peripheries of the memory chips2and3and the controller chip4on the mounting surface1aof the substrate1are sealed within a resin mold part8. The resin mold part8is omitted inFIG. 1in order to show the internal configuration of the semiconductor device50. Further, the resin mold part8is shown as a transparent layer inFIG. 2in order to show the internal configuration of the semiconductor device50.

Since the memory chips2and3and the controller chip4are arranged in a layered or overlapping configuration on the substrate1, the process for filling spaces between the memory chips2and3and the controller chip4with resin is eliminated since the memory chips2and3are superposed, allowing the manufacture cost to be reduced.

A first controller terminal block (first control element terminal block)43is formed on the surface4aof the controller chip4adjacent one first minor side42athereof orthogonal to the arrow X. Further, a second controller terminal block (second control element terminal block)44is formed adjacent the second major side41bopposite to the first major side41a. Furthermore, a third controller terminal block (third control element terminal block)45is formed adjacent the first major side41aas a terminal block other than the first controller terminal block43and the second controller terminal block44. Therefore, no terminal block is formed in the area along the second minor side42b.

The first to third controller terminal blocks43to45are terminal (electrode pad) blocks for connecting bonding wire6. The first to third controller terminal blocks43to45are electrically connected to the wiring5through the bonding wire6to the controller4.

The first memory chip2and the second memory chip3are superposed (stacked but offset) on the mounting surface1aof the substrate1. A first memory terminal block (first storage element terminal block)22is formed on the surface2aof the first memory chip2adjacent one side21that is orthogonal to the arrow X. A distance U between the first memory terminal block22and a side24thereof opposite to the controller chip4is less than a distance T between the first memory terminal block22and a side23on the controller chip4side. In other words, the first memory terminal block22is closer to the side24than the side23.

The first memory terminal block22is a terminal (electrode pad) for connecting the bonding wire6. The first memory terminal block22is electrically connected to the wiring5through the bonding wire6.

A second memory terminal block (second storage element terminal block)32is formed on a surface3aof the second memory chip3adjacent a side31orthogonal to the arrow X. The second memory chip3, which is the same as the first memory chip2, is superposed on the first memory chip2so that the second memory chip3is rotated 180 degrees in a plane. Therefore, a distance W between the second memory terminal block32and a side34on the controller chip4side is less than a distance V between the second memory terminal block32and a side33opposite to the controller chip4side. In other words, the second memory terminal block32is closer to the side34than the side33.

The second memory terminal block32is a terminal (electrode pad) for connecting the bonding wire6thereto. The second memory terminal block32is electrically connected to the wiring5through the bonding wire6.

An external terminal7is formed on a rear face1bopposite to the mounting surface1aof the substrate1. The external terminal7is electrically connected to the wiring5through a via (not shown) formed on the substrate1.

Summarizing the electrical connection between each chip and each terminal, the first memory chip2and the controller chip4are electrically connected through the first memory terminal block22, the wiring5, the first controller terminal block43and the bonding wire6. Further, the second memory chip3and the controller chip4are electrically connected through the second memory terminal block32, the wiring5, the second controller terminal block44and the bonding wire6. Furthermore, the external terminal7and the controller chip4are electrically connected through the wiring5, the third controller terminal block45and the bonding wire6.

Next, the route of the wiring5which electrically connects each chip and each terminal with each other will be described in detail. Wiring5a, which connects the controller chip4and the first memory chip2, links the first minor side42aside of the controller chip4and the side21side of the first memory chip2.

Wiring5b, which connects the controller chip4and the external terminal7, links the first major side41aof the controller chip4and the external terminal7. The wiring5bextends toward the external terminal7from the first major side41a(the side that is closer to the external terminal7) of the surface4aof the controller chip4, allowing the length of the wiring5bto be shortened. This allows the operational speed of the semiconductor device50to be increased.

Wiring5c, which connects the controller chip4and the second memory chip3, links the second major side41bside of the controller chip4and the side31of the second memory chip3. The wiring5cpasses through an area overlapped by the controller chip4in a plan view (underneath the controller chip4) and intersects the second minor side42bin a plan view. Note that although a plurality of wirings5a,5band5care provided to each electrode pad of a respective terminal block, only one representative wiring is described while the others are omitted for the purpose of simplification of the diagram. Also, wirings are preferably formed as conductive traces on the mounting surface1aof the mounting substrate1.

Here, in the present embodiment, no terminal block is formed in the area along the second minor side42bof the surface4aof the controller chip4. If a terminal block is formed in the area along the second minor side42b, it is necessary that an electrode pad which connects the bonding wire, and wiring which extends therefrom are formed in the vicinity of the second minor side42bof the controller chip4on the mounting surface1aof the substrate1. In this case, if the wiring5cis formed so as to intersect the second minor side42b, the number of substrate layers may have to be increased in order to bypass an electrode pad, or the like, formed on the substrate.

On the other hand, in the present embodiment, since no terminal block is formed in the area along the second minor side42bas described above, it is not necessary that an electrode pad which connects the bonding wire, and wiring which extends therefrom, are formed in the vicinity of the second minor side42bof the controller chip4on the mounting surface1aof the substrate1. Therefore, the wiring5ccan be formed so as to intersect with the second minor side42bwithout increasing the number of layers of the semiconductor device50.

In addition, in the present embodiment, the second memory terminal block32is closer to the controller chip4than the first memory terminal block22. Thus, the first controller terminal block43is formed in a location that is closer to a memory chip on the surface4aof the controller chip4, and the second controller terminal block44is formed in the location that is farther from the memory chip.

That is, as described above, the first controller terminal block43connected to the first memory terminal block22that is farther from the controller chip4is formed along the first minor side42athat is closer to the first memory chip2, and the second controller terminal block44connected to the second memory terminal block32that is closer to the controller chip4is formed along the second major side41bthat is farther from the second memory chip3.

This allows the lengths of the wiring5aand the wiring5bto be reduced. The reduction of the lengths of the wiring5aand the wiring5ballows the operational speed of the first memory chip2and the second memory chip3to be increased.

FIG. 3is a schematic diagram illustrating the connection between terminal blocks formed on the surfaces of the memory chips2and3and the controller chip4. As shown inFIG. 3, a terminal number is assigned to each terminal included in a terminal block, and terminals having the same terminal number are electrically connected to each other through the wiring5.

In the present embodiment, data input/output terminal (I/O terminal) numbers (0 to 7) in the first controller terminal block43, and data input/output terminal numbers (0 to 7) in the second controller terminal block44both decrease from the side closest to the corner where the first minor side42aand the second major side41bintersect each other.

As described above, since the first memory chip2and the second memory chip3are the same and are rotated 180 degrees with respect to each other in a plane, the first memory terminal block22and the second memory terminal block32have the terminal numbers reversed from one another along the direction shown with the arrow Y (shown inFIG. 1). For example, inFIG. 3, the first memory terminal block22has the data input/output terminal numbers (0 to 7) increasing from the terminal that is farthest from the controller chip4to the terminal that is closer to the controller chip4. Conversely, in the second memory terminal block32, the data input/output terminal numbers (0 to 7) decrease from the terminal that is farther from the controller chip4to the terminal that is closer to the controller chip4.

Therefore, the first controller terminal block43and the first memory terminal block22have data input/output terminals connected through the wiring5a, successively, from the terminal on the side that is closer to the first major side41afor the first controller terminal block43, and successively from the terminal on the side24, which is the side opposite to the controller chip4, for the first memory terminal block22. On the other hand, the second controller terminal block44and the second memory terminal block32have data input/output terminals connected through the wiring5c, successively, from the terminal on the side that is closer to the corner where the first minor side42aand the second major side41bintersect each other for the second controller terminal block44, and successively from the terminal on the side33, which is the side opposite to the controller chip4, for the second memory terminal block32. Therefore, the wirings5a, which connect the first memory terminal block22and the first controller terminal block43, can be formed without intersecting. Further, the wirings5c, which connect the second memory terminal block32and the second controller terminal block44, can be formed without intersecting. Therefore, an increase in the number of layers of the semiconductor device50due to intersection of the wirings5aand5cis not necessary, allowing manufacturing costs to be reduced.

When the assignments of the terminal numbers of the first memory terminal block22and the second memory terminal block32formed on the first memory chip2and the second memory chip3, respectively, are reversed from the example shown inFIG. 3, the wirings5aand5ccan be formed without intersection if the terminal numbers of the first controller terminal block43and the terminal numbers of the second controller terminal block44are such that both increase from the side that is closer to the corner where the first minor side42aand the second major side41bintersect.

Next, a circuit area formed on the controller chip4will be described.FIG. 4is a drawing illustrating a circuit area formed on the controller chip4. Various circuit areas are formed on the controller chip4including a circuit area VA1 controlling input and output of the third controller terminal block45, a circuit area VA2 controlling input and output of the first controller terminal block43and the second controller terminal block44, and a storage circuit area VA3 of the controller chip4.

In the present embodiment, the first controller terminal block43and the second controller terminal block44are formed adjacent to each other along the first minor side42aand the second major side41b. Further, since the first controller terminal block43and the second controller terminal block44are both connected to memory chips, standby voltages and operating voltages in the circuit areas controlling the inputs and outputs of respective terminal blocks are equal. For example, in the standby state, in which no input/output to/from a memory chip is performed, the standby voltage is 0V, and in the operating state in which input/output of information to/from the memory chip is performed, the operating voltage is 1.2V.

Although the circuit areas VA1, VA2 and VA3 are placed so as to be adjacent to one another, since the first controller terminal block43and the second controller terminal block44are respectively formed along the first minor side42aand the second major side41b, which are adjacent to each other, and the standby voltage and the operating voltage are equal, with the circuit area VA2 controlling the input and output of the first controller terminal block43and the second controller terminal block44serving as one section, by surrounding the circuit area VA2 with a ground line9, it is possible to separate a power supply line to the circuit area VA2 from power supply lines to the other circuit areas VA1, VA3.

Further, for example, in the circuit area VA1 controlling the input and output of the third controller terminal block45, both of the standby voltage and the operating voltage are 1.2V. Furthermore, in the storage circuit area VA3 of the controller chip4, the standby voltage is 0.8V, and the operating voltage is 1.2V. In this manner, the circuit areas VA1, VA2 and VA3 have different standby voltages. Therefore, by respectively surrounding the circuit area VA1 and the circuit area VA3 with ground lines10and11similarly to the circuit area VA2, it is possible to separate respective power supply lines to the circuit area VA1 and the circuit area VA3 from the power line to the circuit area VA2.

FIG. 5is a drawing illustrating a circuit area formed on a controller chip140shown as a comparative example. In the controller chip140shown as a comparative example, a first controller terminal block143and a second controller terminal block144, which are connected to the memory chips (not shown), are formed along sides opposite to each other.

Here, it is necessary to separate a circuit area VA2-1 controlling the first controller terminal block143and a circuit area VA2-2 controlling the second controller terminal block144so that the circuit area VA1 controlling a third controller terminal block145and the storage circuit area VA3 of the controller chip140are adjacent to each other.

On the other hand, in the present embodiment, since the power supply can be separated into a circuit area controlling the first controller terminal block43and a circuit area controlling the second controller terminal block44as a single circuit area VA2, the planar area is VA2<(VA2−1)+(VA2−2). Therefore, the controller chip4according to the present embodiment may be downsized as compared to the controller chip140shown as a comparative example.

FIG. 6is a side view of a semiconductor device60according to a variation of the first embodiment seen from the side of the controller chip4. Note that, inFIG. 6, the resin mold part8is shown as being transparent in order to show the internal configuration of the semiconductor device60.

As shown inFIG. 6, a plurality of the first memory chips2and the second memory chips3may be superposed on the substrate1. With this configuration, by increasing the number of memory chips, memory capacity can be increased while increasing the operational speed of the memory chip and downsizing the controller chip4similarly to the semiconductor device50described above may be achieved.