A semiconductor device may include a first gate structure including first gate lines each first gate line being exposed by a first step structure extending in a first direction, a second gate structure disposed on the first gate structure to expose the first step structure and including second gate lines each second gate line being exposed by a second step structure extending in the first direction, a channel structure extending through the first gate structure and the second gate structure, the channel structure having a first width, a first support extending through the first step structure, the first support having a second width that is greater than the first width, and a second support extending through the second step structure and the first gate structure, the second support having a third width that is greater than the first width.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0094529 filed on Jul. 20, 2023, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device.

2. Related Art

An integration degree of a semiconductor device is mainly determined by an area occupied by a unit memory cell. Recently, as improvement in the integration degree of a semiconductor device in which a memory cell is formed as a single layer on a substrate reaches a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate is being proposed. In addition, various structures and manufacturing methods are being developed in order to improve operation reliability of the semiconductor device.

SUMMARY

According to an embodiment of the present disclosure, a semiconductor device may include a first gate structure including first gate lines each first gate line being exposed by a first step structure extending in a first direction, a second gate structure disposed on the first gate structure to expose the first step structure and including second gate lines each second gate line being exposed by a second step structure extending in the first direction, a channel structure extending through the first gate structure and the second gate structure, the channel structure having a first width, a first support extending through the first step structure, the first support having a second width that is greater than the first width, and a second support extending through the second step structure and the first gate structure, the second support having a third width that is greater than the first width.

According to an embodiment of the present disclosure, a semiconductor device may include a first gate structure including first gate lines each exposed by a first step structure extending in a first direction, a second gate structure disposed on the first gate structure to expose the first step structure and including second gate lines each exposed by a second step structure extending in the first direction, an etch stop layer positioned between the first gate structure and the second gate structure to expose the first step structure, a channel structure extending through the first gate structure, the etch stop layer, and the second gate structure, and including a stepped sidewall, a first support extending through the first step structure and including a non-stepped sidewall, and a second support extending through the second step structure, the etch stop layer, and the first gate structure.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a first stack including a first cell region and a first contact region, forming an etch stop layer on the first stack, forming a second stack including a second cell region and a second contact region on the etch stop layer, forming a trench extending through the second stack and the etch stop layer and partially exposing the first contact region, and forming a first step structure positioned in the first stack and a second step structure positioned in the second stack, by patterning the first contact region and the second contact region in a step shape.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a first stack including first material layers, forming an etch stop layer on the first stack, forming a second stack including second material layers on the etch stop layer, exposing the etch stop layer by etching the second stack, exposing the first stack by etching the etch stop layer, forming a first step structure exposing each of the first material layers and a second step structure exposing each of the second material layers and the etch stop layer, by patterning the first stack and the second stack in a step shape, replacing the first material layers, the etch stop layer, and the second material layers with third material layers, and forming contact plugs connected to the third material layers, respectively.

DETAILED DESCRIPTION

An embodiment of the present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device having a stable structure and improved characteristic.

An integration degree of a semiconductor device may be improved by stacking memory cells in a three dimension. In addition, a semiconductor device having a stable structure and improved reliability may be provided.

Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

FIGS.1A to1Care diagrams illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.FIG.1Ais a plan view,FIG.1Bis a cross-sectional view taken along a line A-A′ ofFIG.1A, andFIG.1Cis a cross-sectional view taken along a line B-B′ ofFIG.1A.

Referring toFIGS.1A to1C, the semiconductor device may include a first gate structure GST1, a second gate structure GST2, a channel structure CH, a first support SP1, and a second support SP2. The semiconductor device may further include at least one of an insulating layer18, a first contact plug CT1, and a second contact plug CT2.

The first gate structure GST1may include first gate lines11. The first gate structure GST1may include the first gate lines11and first insulating layers13that are alternately stacked. The first gate line11may be a select line or a word line, and may include a conductive material such as polysilicon or metal. The first insulating layers13may insulate the stacked first gate lines11from each other, and may include an insulating material such as oxide, nitride, an air gap, or a void.

The first gate structure GST1may include a first cell region CR1and a first contact region CTR1. The first cell region CR1and the first contact region CTR1may be adjacent to each other in a first direction I. The first gate structure GST1may include a first step structure SS1positioned in the first contact region CTR1. The first step structure SS1may have a step shape extending in the first direction I, and each of the first gate lines11may be exposed by the first step structure SS1.

The second gate structure GST2may be positioned on the first gate structure GST1and may expose the first step structure SS1. The second gate structure GST may include second gate lines12. The second gate structure GST2may include the second gate lines12and second insulating layers14that are alternately stacked. The second gate line12may be a select line or a word line, and may include a conductive material such as polysilicon or metal. The second insulating layers14may insulate the stacked second gate lines12from each other, and may include an insulating material such as oxide, nitride, an air gap, or a void.

The second gate structure GST2may include a second cell region CR2and a second contact region CTR2. The second cell region CR2and the second contact region CTR2may be adjacent to each other in the first direction I. The first cell region CR1and the second cell region CR2may overlap in a stack direction, and the first contact region CTR1and the second contact region CTR2may overlap in a stack direction.

The second gate structure GST2may include a second step structure SS2positioned in the second contact region CTR2. The second step structure SS2may have a step shape extending in the first direction I, and each of the second gate lines12may be exposed by the second step structure SS2. The first step structure SS1and the second step structure SS2may be adjacent to each other in a second direction II and may be mutually aligned in the second direction II. Here, the second direction II may be a direction crossing the first direction I. An insulating layer18may be positioned on the second gate structure GST2. The insulating layer18may cover the first step structure SS1and the second step structure SS2.

The channel structure CH may extend through the first gate structure GST1and the second gate structure GST2. The channel structure CH may extend through the first cell region CR1of the first gate structure GST1and the second cell region CR2of the second gate structure GST2. The channel structure CH may include a channel layer15, a memory layer16, and an insulating core17, or may include a combination thereof. The memory layer16may include at least one of a tunneling layer, a data storage layer, and a blocking layer, and the data storage layer may include a floating gate, polysilicon, a charge trap material, nitride, a variable resistance material, or the like.

The first support SP1may extend through the first step structure SS1. The first support SP1may pass through the insulating layer18and extend into the first step structure SS1. The second support SP2may extend through the second step structure SS2and the first gate structure GST1. The second support SP2may pass through the insulating layer18and extend into the second step structure SS2.

The first support SP1and the second support SP2may have a shape similar to that of the channel structure CH. In an embodiment, the first support SP1may include a first dummy channel layer15A, a first dummy memory layer16A, and a first dummy insulating core17A, or may include a combination thereof. The second support SP2may include a second dummy channel layer15B, a second dummy memory layer16B, and a second dummy insulating core17B, or may include a combination thereof.

Sidewall shapes of the first support SP1, the second support SP2, and the channel structure CH may be similar to or different from each other. In an embodiment, the channel structure CH may be formed in an opening formed through a plurality of etching processes and may include a stepped sidewall. The stepped sidewall may include a step difference S positioned between the first gate structure GST1and the second gate structure GST2. The first support SP1and the second support SP2may be formed in an opening formed through one etching process, and may include a non-stepped sidewall.

The first support SP1, the second support SP2, and the channel structure CH may have substantially the same width or different widths. The channel structure CH may have a first width W11, the first support SP1may have a second width W12greater than the first width W11, and the second support SP2may have a third width W13greater than the first width W11. In an embodiment, the second width W12and the third width W13may be greater than the first width W11, and the second width W12and the third width W13may be substantially the same. The width may be a width of an upper surface, a width of a lower surface, or an average width of a corresponding structure. The upper surface may be a top surface. The lower surface may be a bottom surface. In an embodiment, a width of an upper surface of the first support SP1may be greater than a width of an upper surface of the channel structure CH, a width of an upper surface of the second support SP2may be greater than the width of the upper surface of the channel structure CH. In the illustrated embodiments, the cross-sections of the channel structure CH, the first support SP1, and the second support SP2may have a circle-shape and the width refers to the diameter of the cross-section. In other embodiments, (not shown), the cross-sections of the channel structure CH, the first support SP1, and the second support SP2may have a square-shape and the width may refer to the diagonal of the square.

The first contact plugs CT1may be positioned between the first supports SP1, and may be connected to the first gate lines11, respectively. The second contact plugs CT2may be positioned between the second supports SP2, and may be connected to the second gate lines12, respectively. Each of the first contact plugs CT1may be positioned centrally between four adjacent first supports SP1positioned at the vertices of a square. Each of the second contact plugs CT2may be positioned centrally between four adjacent second supports SP2positioned at the vertices of a square.

According to the structure described above, the first step structure SS1and the second step structure SS2of the first gate structure GST1may be adjacent to each other in the second direction II. The first step structure SS1and the second step structure SS2of the first gate structure GST1may be in contact to each other. The first step structure SS1and the second step structure SS2may be formed through the same patterning process. First steps included in the first step structure SS1and second steps included in the second step structure SS2may be aligned in the second direction II. Therefore, the first step structure SS1and the second step structure SS2may be efficiently disposed, and a manufacturing process of the semiconductor device may be improved.

FIGS.2A to2Care diagrams illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.FIG.2Ais a plan view,FIG.2Bis a cross-sectional view taken along a line A-A′ ofFIG.2A, andFIG.2Cis a cross-sectional view taken along a line B-B′ ofFIG.2A. Hereinafter, content overlapping the above-described content is omitted.

Referring toFIGS.2A to2C, the semiconductor device may include the first gate structure GST1, the second gate structure GST2, the channel structure CH, the first support SP1, and the second support SP2. The semiconductor device may further include at least one of an insulating layer28, a third support SP3, the first contact plug CT1, and the second contact plug CT2.

The first gate structure GST1may include first gate lines21and first insulating layers23that are alternately stacked. The first gate structure GST1may include the first step structure SS1. The second gate structure GST2may include second gate lines22and second insulating layers24that are alternately stacked. The second gate structure GST2may include the second step structure SS2.

The channel structure CH may extend through the first gate structure GST1and the second gate structure GST2. The channel structure CH may include a channel layer25, a memory layer26, and an insulating core27, or may include a combination thereof. The first support SP1may extend through the first step structure SS1. The first support SP1may include a first dummy channel layer25A, a first dummy memory layer26A, and a first dummy insulating core27A, or may include a combination thereof. The second support SP2may extend through the second step structure SS2and the first gate structure GST1. The second support SP2may include a second dummy channel layer25B, a second dummy memory layer26B, and a second dummy insulating core27B, or may include a combination thereof.

The third support SP3may be positioned in the cell regions CR1/CR2or in the contact regions CTR1/CTR2. The third support SP3may be positioned between the channel structure CH and the first support SP1or may be positioned between the channel structure CH and the second support SP2. The third support SP3may extend through the second gate structure GST2and the first gate structure GST1. The third support SP3may have a shape similar to that of the channel structure CH. In an embodiment, the third support SP3may include a third dummy channel layer25C, a third dummy memory layer26C, and a third dummy insulating core27C, or may include a combination thereof.

Side wall shapes of the first support SP1, the second support SP2, and the third support SP3may be similar to or different from each other. At least one of the first support SP1, the second support SP2, and the third support SP3may include a stepped sidewall. In an embodiment, the second support SP2and the third support SP3may include a stepped sidewall, and the first support SP1may include a non-stepped sidewall.

The first support SP1, the second support SP2, and the third support SP3may have substantially the same width or different widths. The channel structure CH may have a first width W21. The second support SP2may have a third width W23greater than the first width W21. The first support SP1may have a second width W22greater than the first width W21and the third width W23. The third support SP3may have a fourth width W24greater than the first width W21and less than the second width W22. The fourth width W24may be substantially the same as the third width W23.

The first contact plugs CT1may be positioned between the first supports SP1or may be positioned between the first support SP1and the third support SP3. The second contact plugs CT2may be positioned between the second supports SP2or may be positioned between the second support SP2and the third support SP3.

According to the structure as described above, the first step structure SS1and the second step structure SS2may be efficiently disposed, and the manufacturing process of the semiconductor device may be improved.

FIGS.3A to3Care diagrams illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.FIG.3Ais a plan view,FIG.3Bis a cross-sectional view taken along a line A-A′ ofFIG.3A, andFIG.3Cis a cross-sectional view taken along a line B-B′ ofFIG.3A. Hereinafter, content overlapping the above-described content is omitted.

Referring toFIGS.3A to3C, the semiconductor device may include the first gate structure GST1, the second gate structure GST2, the channel structure CH, the first support SP1, and the second support SP2. The semiconductor device may further include at least one of an insulating layer38, the first contact plug CT1, the second contact plug CT2, and an etch stop layer39.

The first gate structure GST1may include first gate lines31and first insulating layers33that are alternately stacked. The first gate structure GST1may include the first step structure SS1. The second gate structure GST2may include second gate lines32and second insulating layers34that are alternately stacked. The second gate structure GST2may include the second step structure SS2.

The etch stop layer39may be positioned between the first gate structure GST1and the second gate structure GST2. The etch stop layer39may be used as an etch barrier when etching a stack in a manufacturing process. The etch stop layer39may include a material having an etch selectivity with respect to the stack. In an embodiment, the etch stop layer39may include aluminum oxide (Al2O3), polysilicon, or the like.

The channel structure CH may extend through the first gate structure GST1, the etch stop layer39, and the second gate structure GST2. The channel structure CH may include a channel layer35, a memory layer36, and an insulating core37, or may include a combination thereof. The first support SP1may extend through the first step structure SS1. The second support SP2may extend through the second step structure SS2, the etch stop layer39, and the first gate structure GST1. The first support SP1, the second support SP2, and the channel structure CH may have substantially the same width or different widths.

For reference, during a manufacturing process, the etch stop layer39may be replaced with a third gate line39A, and the third gate line39A may be included in the first gate structure GST1. The third gate line39A may include the same material as the first gate line31and the second gate line32or may include a material different from a material of the first gate line31and the second gate line32. In an embodiment, the first gate line31, the second gate line32, and the third gate line39A may include a metal such as tungsten (W) or molybdenum (Mo). In an embodiment, the first gate line31and the second gate line32may include polysilicon, and the third gate line39A may include a metal such as tungsten (W) or molybdenum (Mo). At least one of the second contact plugs CT2may be electrically connected to the third gate line39A.

As described above with reference toFIGS.1A to1C and2A to2C, the semiconductor device may further include the third support SP3. Side wall shapes of the first support SP1, the second support SP2, and the third support SP3may be similar to or different from each other. The first support SP1, the second support SP2, and the third support SP3may have substantially the same width or different widths.

The first contact plugs CT1may be positioned between the first supports SP1or may be positioned between the first support SP1and the third support SP3. The second contact plugs CT2may be positioned between the second supports SP2or may be positioned between the second support SP2and the third support SP3.

According to the structure as described above, the first step structure SS1and the second step structure SS2may be efficiently disposed, and the manufacturing process of the semiconductor device may be improved.

FIGS.4A to10A,4B to10B, and6C to10Care diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. A of each FIG. is a plan view, FIG. B of each number is a C-C′ cross-sectional view of FIG. A, and FIG. C of each number is a D-D′ cross-sectional view of FIG. A. Hereinafter, content overlapping the above-described content is omitted.

Referring toFIGS.4A and4B, a first stack ST1including the first cell region CR1and the first contact region CTR1may be formed. The first cell region CR1may be a region in which stacked memory cells are formed. The first contact region CTR1may be a region in which an interconnection structure for applying a bias to each of stacked gate lines is formed. The interconnection structure may include a contact plug, a line, and the like.

The first stack ST1may include first material layers41. In an embodiment, the first stack ST1may include the first material layers41and first insulating layers42that are alternately stacked. The first material layers41may be for forming a gate line such as a select line or a word line. The first material layers41may include a sacrificial material such as nitride or may include a conductive material such as polysilicon or tungsten. The first insulating layer42may insulate the stacked gate lines from each other. The first insulating layer42may include an insulating material such as oxide, nitride, an air gap, or a void.

Subsequently, the etch stop layer43may be formed on the first stack ST1. The etch stop layer43may control an etching depth when a second stack is etched in a subsequent process. The etch stop layer43may include a material having a great etch selectivity with respect to the second stack. In an embodiment, the etch stop layer43may include at least one of aluminum oxide (Al2O3) and polysilicon. Subsequently, an insulating layer44may be formed on the etch stop layer43. For reference, the etch stop layers43and the insulating layers44may be alternately stacked.

Referring toFIGS.5A and5B, a first mask pattern45may be formed on the etch stop layer43. The first mask pattern45may include an opening positioned in the first cell region CR1. Subsequently, the insulating layer44, the etch stop layer43, and the first stack ST1may be etched using the first mask pattern45as an etch barrier to form a first sub-channel hole SCH1. The first sub-channel hole SCH1may be positioned in the first cell region CR1.

Referring toFIGS.6A to6C, a sacrificial layer46may be formed in the first sub-channel hole SCH1. The sacrificial layer46may include a material having a great etch selectivity with respect to the first material layer41and the first insulating layer42.

Subsequently, a second stack ST2including the second cell region CR2and the second contact region CTR2may be formed on the etch stop layer43and the insulating layer44. The second stack ST2may include second material layers47. In an embodiment, the second stack ST2may include the second material layers47and second insulating layers48that are alternately stacked. The second material layers47may be for forming a gate line such as a select lines and a word line. The second material layers47may include a sacrificial material such as nitride or may include a conductive material such as polysilicon or tungsten. The second insulating layer48may insulate stacked gate lines from each other. The second insulating layer48may include an insulating material such as oxide, nitride, an air gap, or a void.

Subsequently, a second mask pattern49may be formed on the second stack ST2. The second mask pattern49may be formed to partially expose the first contact region CTR1. The second mask pattern49may have a shape covering the second cell region CR2and partially exposing the second contact region CTR2. The second mask pattern49may expose a region of the first contact region CTR1where the first step structure is to be formed and may cover a region of the second contact region CTR2where the second step structure is to be formed. The second mask pattern49may include photoresist.

Subsequently, the second stack ST2may be etched using the second mask pattern49as an etch barrier. At this time, the second stack ST2may be etched to expose the etch stop layer43. Because an etching depth is controlled using the etch stop layer43, the first material layer41and the first insulating layer42may be alternately etched using the same etching recipe. Because the second stack ST2is etched without changing the etching recipe, occurrence of an inclination of etch surfaces of the first material layer41and the second insulating layer42may be improved.

Subsequently, the exposed etch stop layer43may be etched. In an embodiment, the etch stop layer43may be etched using the second mask pattern49as an etch barrier. In an embodiment, after removing the second mask pattern49, the etch stop layer43may be etched by a wet etching method using phosphoric acid or the like. Through this, a trench T extending through the second stack ST2and the etch stop layer43and partially exposing the first contact region CTR1may be formed. A sidewall of the trench T may have a vertical profile and may expose a region of the first contact region CTR1where the first step structure is to be formed.

Referring toFIGS.7A to7C, the first step structure SS1and the second step structure SS2may be formed. The first step structure SS1positioned in the first stack ST1and the second step structure SS2positioned in the second stack ST2may be formed, by patterning the first and second contact regions CTR1and CTR2, respectively, in a step shape.

Each of the first material layers41may be exposed by the first step structure SS1. Each of the second material layers42and the etch stop layer43may be exposed by the second step structure SS2. The first and second step structures SS1, and SS2may extend in the first direction I and may be adjacent to each other in the second direction II. The first and second step structures SS1, and SS2may be in contact to each other. The first steps S1included in the first step structure SS1and the second steps S2included in the second step structure SS2may be aligned in the second direction II.

The first step structure SS1and the second step structure SS2may be formed using the same mask pattern. In an embodiment, a third mask pattern51may be formed on the second stack ST2. The third mask pattern51may cover the second cell region CR2and expose a portion of the second contact region CTR2and a portion of the first contact region CTR1. Subsequently, the first contact region CTR1and the second contact region CTR2may be etched using the third mask pattern51as an etch barrier. Subsequently, the third mask pattern51may be reduced in the first direction I, and the first contact region CTR1and the second contact region CTR2may be etched using the reduced third mask pattern51as an etch barrier. The first contact region CTR1and the second contact region CTR2may be patterned in a step shape extending in the first direction I, by repeatedly performing reduction of the third mask pattern51and an etching process. Through this, the first step structure SS1and the second step structure SS2having the same shape may be formed in the first contact region CTR1and the second contact region CTR2, respectively.

Referring toFIGS.8A to8C, an insulating layer52may be formed on the second stack. The insulating layer52may cover the first step structure SS1and the second step structure SS2. Subsequently, a fourth mask pattern53may be formed on the second stack ST2and the insulating layer52. Subsequently, the insulating layer52and the second stack ST2may be etched using the fourth mask pattern53as an etch barrier to form second sub-channel holes SCH2connected to corresponding first sub-channel holes SCH1.

The second sub-channel holes SCH2may be positioned in the second cell region CR2of the second stack ST2. The second sub-channel holes SCH2may extend through the second stack ST2and expose the sacrificial layer46. The second sub-channel holes SCH2may have a first depth D1and a first width W41. Through this, channel holes CHH, each including a first sub-channel hole SCH1and a corresponding second sub-channel hole SCH2may be formed. A bottom width of the first sub-channel hole SCH1and a top width of the second sub-channel hole SCH2may be different from each other, thus, a sidewall of the channel hole CHH may include a step difference S due to a width difference. The step difference S may be positioned between the first stack ST1and the second stack ST2.

The insulating layer52and the second stack ST2may be etched using the fourth mask pattern53as an etch barrier to form a first opening OP1extending through the first step structure SS1. The first opening OP1may pass through the insulating layer52and extend into the first step structure SS1. The first opening OP1may have a second depth D2and a second width W42. The second depth D2may be greater than the first depth D1, and the second width W42may be greater than the first width W41.

The second stack ST2may be etched using the fourth mask pattern53as an etch barrier to form a second opening OP2extending through the second step structure SS2. The second opening OP2may pass through the insulating layer52, the second step structure SS2, and the etch stop layer43and extend into the first stack ST1. The second opening OP2may be adjacent to the first opening OP1in the second direction II. The second opening OP2may have a third depth D3and a third width W43. The third depth D3may be greater than the first depth D1, and the third width W43may be greater than the first width W41. The second depth D2and the third depth D3may be substantially the same. The second width W42and the third width S43may be substantially the same.

The first opening OP1may be formed when forming the second sub-channel hole SCH2or may be formed in a separate process. The second opening OP2may be formed when forming the second sub-channel hole SCH2or may be formed in a separate process. In an embodiment, the second sub-channel hole SCH2, the first opening OP1, and the second opening OP2may be formed using the fourth mask pattern53. When forming the second sub-channel hole SCH2, the first and second openings OP1and OP2may be formed.

The first and second openings OP1and OP2may be formed to have a width greater than the width of the second sub-channel hole SCH2. In this case, an etching amount of the first and second openings OP1and OP2may be greater than an etching amount of the second sub-channel hole SCH2by a loading effect. Therefore, the first and second openings OP1and OP2may be formed in a depth greater than that of the second sub-channel hole SCH2. The first and second openings OP1and OP2may be formed in a single etching process and may not include a step difference on the sidewall.

Referring toFIGS.9A to9C, the first sub-channel hole SCH1may be reopened by removing the sacrificial layer46. Subsequently, the channel structure CH may be formed in the channel hole CHH. According to the illustrated embodiment, the channel structure CH may include a channel layer55, a memory layer56, and an insulating core57. However, in other embodiments, (not shown), the channel structure CH may include at least one of a channel layer55, a memory layer56, and an insulating core57. A sidewall of the channel structure CH may include a step difference S transferred from the channel hole CHH.

The first support SP1may be formed in the first opening OP1. In the illustrated embodiment, the first support SP1may include a first dummy channel layer55A, a first dummy memory layer56A, and a first dummy insulating core57A. However, in other embodiments, (not shown), the first support SP1may include at least one of a first dummy channel layer55A, a first dummy memory layer56A, and a first dummy insulating core57A. A sidewall of the first support SP1may have a shape transferred from the first opening OP1. The sidewall of the first support SP1may not include a step change in its width and may be referred to as a non-stepped sidewall. The first support SP1may have a width greater than that of the channel structure CH.

The second support SP2may be included in the second opening OP2. The second support SP2may include at least one of a second dummy channel layer55B, a second dummy memory layer56B, and a second dummy insulating core57B. A sidewall of the second support SP2may have a shape transferred from the second opening OP2. The sidewall of the second support SP2may not have a step change in its width, and may be referred to as a non-stepped sidewall. The second support SP2may have a width greater than that of the channel structure CH.

The first support SP1may be formed when forming the channel structure CH or may be formed in a separate process. The second support SP2may be formed when forming the channel structure CH or may be formed in a separate process. In an embodiment, when forming the channel structure CH, the first support SP1and the second support SP2may be formed. At least one of the first and second supports SP1and SP2may include a dummy channel layer.

Subsequently, an insulating layer58may be formed to cover the channel structures CH, the first supports SP1, and the second supports SP2. Subsequently, the first material layers41and the second material layers47may be replaced with conductive layers. In an embodiment, a slit SL extending through the insulating layers58and52, the second stack ST2, the etch stop layer43, and the first stack ST1may be formed. Subsequently, the first material layers41and the second material layers47may be replaced with conductive layers through the slit SL. Openings may be formed by selectively etching the first material layers41and the second material layers47through the slit SL, and conductive layers may be formed in the openings.

Through this, the first gate structure GST1including first gate lines41A and the first insulating layers42that are alternately stacked may be formed. The second gate structure GST2including second gate lines47A and the second insulating layers48that are alternately stacked may be formed. When replacing the first material layers41and the second material layers47with the conductive layers, the etch stop layer43may remain or may be replaced with a gate line43A. The gate line43A may be included in the first gate structure GST1.

In a variation of the described embodiment, when the first material layers41and the second material layers47include a conductive material, the above-mentioned replacement process may be omitted. In this case, the first stack ST1may be the first gate structure GST1, the second stack GST2may be the second gate structure GST2, and the etch stop layer43may remain.

At least one of the first material layers41, the second material layers47, and the etch stop layer43may be replaced with a conductive layer. When replacing the first material layers41and the second material layers47with conductive layers, the etch stop layer43may remain or may be replaced with the gate line43A. The gate line43A may be included in the first gate structure GST1. In an embodiment, openings may be formed by selectively etching the first material layers41, the second material layers47, and the etch stop layer43, and conductive layers may be formed in the openings. When the first material layers41, the second material layers47, and the etch stop layer43include nitride, the first material layers41, the second material layers47, and the etch stop layer43may be selectively etched in a dip-out process using phosphoric acid. In an embodiment, when the etch stop layer43includes polysilicon, the etch stop layer43may be selectively etched using nitric acid or a dry cleaning process.

Subsequently, a slit structure SLS may be formed in the slit SL. The slit structure SLS may include at least one of an insulating material, a conductive material, and a semiconductor material. In an embodiment, the slit structure SLS may include a source contact plug and an insulating spacer surrounding a sidewall of the source contact plug.

Referring toFIGS.10A to10C, the first and second contact plugs CT1and CT2may be formed. The first contact plug CT1may be positioned between the first supports SP1. The first contact plug CT1may be positioned centrally between adjacent first supports SP1. In the illustrated embodiment, one first contact plug CT1may be positioned centrally between four adjacent first supports SP1. Forming the first contact plugs CT1may include first forming openings exposing each of the first gate lines41A through the insulating layers52and58, then a first barrier layer61B may be formed in the openings, and following the formation of the first barrier layer61B, a first metal layer61A may be formed to fill the remaining gap formed by first barrier layer61B. The first contact plugs CT1may extend through the insulating layers52and58and may be electrically connect to a corresponding one of the first gate lines41A.

The second contact plugs CT2may be positioned between the second supports SP2. The second contact plugs CT2may be positioned centrally between the second supports SP2. In the illustrated embodiment, one second contact plug CT1may be positioned centrally between four adjacent second supports SP2. Forming the second contact plugs CT1may include first forming openings exposing each of the second gate lines47A through the insulating layers52and58, then a second barrier layer62B may be formed in the openings, and a second metal layer62A may be formed following the formation of the second barrier layer62B to fill the remaining gap formed by the second barrier layer62B. The second contact plug CT2may extend through the insulating layers52and58and may be electrically connected to the second gate line47A. The first and second metal layers61A and62A may include a metal such as tungsten or molybdenum. The first and second barrier layers61B and62B may include metal nitride such as tungsten nitride, molybdenum nitride, titanium nitride, or tantalum nitride.

According to the manufacturing method as described above, after exposing the first contact region CTR1by forming the trench T, the first contact region CTR1and the second contact region CTR2may be patterned in a step shape. Therefore, when forming the second step structure SS2in the second contact region CTR2, the first step structure SS1may be formed in the first contact region CTR1. A process cost may be reduced by simultaneously patterning the first stack ST1and the second stack ST2to simultaneously form the first step structure SS1and the second step structure SS2positioned at different levels.

Because the trench T is formed using the etch stop layer43, the second material layers47and the second insulating layers48may be etched using the same recipe. Therefore, compared to a case where the second material layers47and the second insulating layers48are alternately etched while changing a recipe, the trench T may have a vertical profile, and an increase in an area of a step structure due to an inclination of the trench T may be improved.

FIGS.11A to16A,11B to16B, and11C to16Care diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. A of each FIG. is a plan view, FIG. B of each number is an E-E′ cross-sectional view of FIG. A, and FIG. C of each number is an F-F′ cross-sectional view of FIG. A. Hereinafter, content overlapping the above-described content is omitted.

Referring toFIGS.1A and11B, the first stack ST1including the first cell region CR1and the first contact region CTR1may be formed. The first stack ST1may include first material layers71and first insulating layers72that are alternately stacked. Subsequently, an etch stop layer73and an insulating layer74may be formed on the first stack ST1.

Subsequently, a first mask pattern75may be formed on the etch stop layer73. Subsequently, the etch stop layer73and the first stack ST1may be etched using the first mask pattern75as an etch barrier to form the first sub-channel hole SCH1and a first sub-opening OP2A. The first sub-channel hole SCH1may be positioned in the first cell region CR1, and the first sub-opening OP2A may be positioned in the first contact region CTR1. The first contact region CTR1may include a region where the first step structure is to be formed and a remaining region, and the first sub-opening OP2A may be positioned in the remaining region.

The first sub-channel hole SCH1and the first sub-opening OP2A may have substantially the same width or may have different widths. The first sub-channel hole SCH1may have a first width W51, and the first sub-opening OP2A may have a third width W53greater than the first width W51.

Referring toFIGS.12A to12C, a first sacrificial layer76A may be formed in the first sub-channel hole SCH1. A second sacrificial layer76B may be formed in the first sub-opening OP2A. When forming the first sacrificial layer76A, the second sacrificial layer76B may be formed. The first sacrificial layer76A and the second sacrificial layer76B may include a material having a great etch selectivity with respect to the first material layer71and the first insulating layer72.

Subsequently, the second stack ST2including the second cell region CR2and the second contact region CTR2may be formed on the etch stop layer73. The second stack ST2may include second material layers77and second insulating layers78that are alternately stacked.

Subsequently, a second mask pattern79may be formed on the second stack ST2. The second mask pattern79may cover the second cell region CR2and partially expose the second contact region CTR2. The second mask pattern79may expose a region of the first contact region CTR1where the first step structure is to be formed and may cover a region of the second contact region CTR2where the second step structure is to be formed.

Subsequently, the second stack ST2is etched using the second mask pattern79as an etch barrier to expose the etch stop layer73, and the exposed etch stop layer73may be etched. Through this, the trench T extending through the second stack ST2and the etch stop layer73and exposing a region of the first contact region CTR1where the first step structure is to be formed may be formed.

Referring toFIGS.13A to13C, a third mask pattern81may be formed on the second stack ST2. The first step structure SS1and the second step structure SS2may be formed by repeatedly performing reduction of the third mask pattern81and an etching process. Because the first sub-opening OP2A and the second sacrificial layer76B are not formed in the region where the first step structure SS1is to be formed, the first material layers71and the insulating layers72may be etched to form the first step structure SS1. The second step structure SS2may be formed on the first sub-opening OP2A and the second sacrificial layer76B. The first step structure SS1and the second step structure SS2may extend in the first direction I and may be adjacent to each other in the second direction II. The first step structure SS1and the second step structure SS2may be in contact to each other. The first steps S1included in the first step structure SS1and the second steps S2included in the second step structure SS2may be aligned in the second direction II.

Referring toFIGS.14A to14C, a fourth mask pattern83may be formed on the second stack ST2. The insulating layer82and the second stack ST2may be etched using the fourth mask pattern83as an etch barrier to form the second sub-channel hole SCH2connected to the first sub-channel hole SCH1. The second sub-channel holes SCH2may be positioned in the second cell region CR2of the second stack ST2. The second sub-channel hole SCH2may have the first depth D1and a first width W51. Through this, the channel hole CHH including the first sub-channel hole SCH1and the second sub-channel hole SCH2may be formed.

The insulating layer82and the second stack ST2may be etched using the fourth mask pattern83as an etch barrier to form the second sub-opening OP2B. The second sub-opening OP2B may extend through the second step structure SS2and may be connected to the first sub-opening OP2A. The second sacrificial layer76B may be exposed through the second sub-opening OP2B. The second opening OP2may have the third depth D3and a third width W53. The third depth D3may be substantially the same as the first depth D1, and the third width W53may be greater than the first width W51. Through this, the second opening OP2including the first sub-opening OP2A1and the second sub-opening OP2B may be formed.

The insulating layer82and the second stack ST2may be etched using the fourth mask pattern83as an etch barrier to form the first opening OP1extending through the first step structure SS1. The first opening OP1may pass through the insulating layer82and extend into the first step structure SS1. The first opening OP1may have the second depth D2and a second width W52. The second depth D2may be greater than the first depth D1and the third depth D3, and the second width W52may be greater than the first width W51and the second width W52.

The second sub-channel hole SCH2, the first opening OP1, and the second sub-opening OP2B may be formed using the fourth mask pattern83as an etch barrier. When forming the second sub-opening OP2B and the second sub-channel hole SCH2, the first opening OP1may be formed. The first opening OP1may be formed to have a width greater than that of the second sub-channel hole SCH2and the second sub-opening OP2B, and an etching amount of the first opening OP1may be greater than an etching amount of the second sub-channel hole SCH2and the second sub-opening OP2B by a loading effect. Therefore, the first opening OP1may be formed in a depth greater than that of the second sub-channel hole SCH2and the second sub-opening OP2B. Therefore, the first opening OP1may be formed in a single etching process and may not include a step difference on a sidewall.

Referring toFIGS.15A to15C, the first sub-channel hole SCH1may be reopened by removing the first sacrificial layer76A. Subsequently, the channel structure CH may be formed in the channel hole CHH. In the illustrated embodiment, the channel structure CH may include a channel layer85, a memory layer86, and an insulating core87. However, in other embodiments, the channel structure CH may include at least one of a channel layer85, a memory layer86, and an insulating core87. A sidewall of the channel structure CH may include a step difference S transferred from the channel hole CHH.

The first support SP1may be formed in the first opening OP1. The first support SP1may include a first dummy channel layer85A, a first dummy memory layer86A, and a first dummy insulating core87A. In some embodiments, (not shown) the first support SP1may include at least one of a first dummy channel layer85A, a first dummy memory layer86A, and a first dummy insulating core87A. A sidewall of the first support SP1may have a shape transferred from the first opening OP1and may include a non-stepped sidewall. The first support SP1may have a width greater than the width of the channel structure CH.

The first sub-opening OP2A may be reopened by removing the second sacrificial layer76B. When the first sacrificial layer76A is removed, the second sacrificial layer76B may be removed. Subsequently, the second support SP2may be formed in the second opening OP2. The second support SP2may be adjacent to the first support SP1in the second direction II. The second support SP2may include a second dummy channel layer85B, a second dummy memory layer86B, and a second dummy insulating core87B. In some embodiments, the second support SP2may include at least one of a second dummy channel layer85B, a second dummy memory layer86B, and a second dummy insulating core87B. A sidewall of the second support SP2may have a shape transferred from the second opening OP2and may include a step difference S on a sidewall. The second support SP2may have a width greater than that of the channel structure CH and may have a width less than that of the first support SP1.

The third support SP3may be formed in the second opening OP2. The third support SP3may be positioned between the channel structure CH and the first support SP1, and may be adjacent to the first support SP1in the first direction I. The third support SP3may include at least one of a third dummy channel layer85C, a second dummy memory layer86C, and a second dummy insulating core87C. A sidewall of the third support SP3may have a shape transferred from the second opening OP2and may include a step difference S on a sidewall. The third support SP3may have a width greater than that of the channel structure CH and may have a width less than that of the first support SP1.

The first support SP1, the second support SP2, and the third support SP3may be formed when forming the channel structure CH or may be formed in a separate process. In an embodiment, when forming the channel structure CH, the first support SP1, the second support SP2, and the third support SP3may be formed. At least one of the first support SP1, the second support SP2, and the third support SP3may include a dummy channel layer.

Subsequently, an insulating layer88may be formed to cover the channel structure CH, the first support SP1, the second support SP2, and the third support SP3. Subsequently, the first material layers71and the second material layers77may be replaced with conductive layers. Through this, the first gate structure GST1including first gate lines71A and first insulating layers72that are alternately stacked may be formed. The second gate structure GST2including second gate lines77A and second insulating layers78that are alternately stacked may be formed. When replacing the first material layers71and the second material layers77with conductive layers, the etch stop layer73may remain or may be replaced with a gate line73A. The gate line73A may be included in the first gate structure GST1. For reference, when the first material layers71and the second material layers77include a conductive material, a replacement process may be omitted. In this case, the first stack ST1may be the first gate structure GST1, the second stack GST2may be the second gate structure GST2, and the etch stop layer73may remain.

Referring toFIGS.16A to16C, the first and second contact plugs CT1and CT2may be formed. Each of the first contact plugs CT1may be positioned between adjacent first supports SP1or may be positioned between adjacent first supports SP1and adjacent third supports SP3. Each of the second contact plugs CT2may be positioned between adjacent second supports SP2. The first contact plug CT1may include a first metal layer91A and a first barrier layer91B. The second contact plug CT2may include a second metal layer92A and a second barrier layer92B.

According to the manufacturing method as described above, the second stack ST2may be partially etched using the etch stop layer73to open the first contact region CTR1, thereby simultaneously forming the first step structure SS1and the second step structure SS2positioned at different levels. An etching process may be improved by dividing the second opening OP2into the first sub-opening OP2A and the second sub-opening OP2B and forming the second opening OP2.

Although embodiments according to the technical concepts of the present disclosure have been described with reference to the accompanying drawings, these embodiments are only for describing examples according to the concepts of the present disclosure, and the present disclosure is not limited to the above-described embodiments. Within the scope of the technical concepts of the present disclosure, various substitutions, modifications, and changes of the embodiments will be possible by those skilled in the art to which the present disclosure belongs without departing from the scope of the present invention disclosure as defined in the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.