Replacement data buffer pointers

Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.

BACKGROUND

The present disclosure relates to technology for non-volatile storage.

One type of non-volatile storage is semiconductor memory. For example, non-volatile semiconductor memory is used in solid state drives, mobile computing devices, non-mobile computing devices and other non-volatile memory systems. Typically, the non-volatile memory device has a memory controller which controls data transfers between the non-volatile memory device and a host system over a communication interface. The host system could be computer system, cellular telephone, server, etc. The non-volatile memory device and host system may exchange data over, for example, a Peripheral Computer Interface Express (PCIe) bus. Non-volatile Memory Express (NVMe) is a logical device interface specification for accessing non-volatile storage attached via a PCIe bus. NVMe takes advantage of parallelism offered by semiconductor memory such as, but not limited to, solid state drives.

The host system may have data buffers that are used to store data to be written to the non-volatile memory device, as well as to store data read from the non-volatile memory device. The host system may make data buffer pointers to the data buffers available to the memory controller. Thus, the memory controller may use the data buffer pointers to access data to be written to the non-volatile memory device, as well as to transfer data that is read from the non-volatile memory device into the data buffers.

DETAILED DESCRIPTION

Technology is described herein for operating non-volatile storage. One embodiment is a non-volatile memory device that manages data buffer pointers to data buffers in host memory. Note that, in some memory access protocols (e.g., NVMe), data buffer pointers to data buffers in host memory may be generated by and managed by the host system. Furthermore, the non-volatile memory device is not allowed to change the data buffer pointers in some memory access protocols. One embodiment is a non-volatile memory device that replaces an original data buffer pointer (or pointers) to a host memory data buffer (or buffers) with a replacement data buffer pointer (or pointers) to a different data buffer (or buffers) in the host memory. Such data buffer pointer replacement can save time and power when responding to memory access requests.

The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. In one embodiment, the replacement data buffer pointer(s) point to a region of host memory that is allocated for exclusive use of the memory controller.

In some cases, the data needed to respond to the specific read command may already be cached in the host memory. Replacing the original data buffer pointers associated with the specific command with replacement data buffer pointers to the data already cached in host memory is a very efficient way to respond to the specific read command. In one embodiment, the data is cached in a region of the host memory that is dedicated for the exclusive use of a memory controller of the non-volatile memory device. For example, the data might be cached in an NVMe Host Memory Buffer (HMB) region of host memory that is allocated for the memory controller's exclusive use. Replacing the data buffer pointers is more efficient than reading the needed data from the non-volatile storage, and sending the data across the (e.g., PCIe) bus from the non-volatile memory device to data buffers associated with the specific read command. Thus, replacing the data buffer pointers can save time and energy. Replacing the original data buffer pointers is more efficient than copying the cached data from the host over a bus to the non-volatile memory device, and then back across the bus to the data buffers associated with the specific read command. Therefore, replacing the data buffer pointers can also reduce traffic over the (e.g., PCIe) bus.

In some cases, the data needed to respond to a read command is already cached in the non-volatile memory device. However, the memory controller has not yet obtained the data buffer pointers to the data buffers to which the memory controller is to transfer the data. Replacing the original data buffers pointers for this read command with replacement data buffer pointer can save time in responding to the read command. Note that the original data buffer pointers to the data buffers in the host memory are not necessarily included in the specified read command. Rather, the memory controller may need to fetch the original data buffer pointers separately from fetching the read command. In one embodiment, the memory controller uses data buffer pointers that it has already fetched for another read command to replace the original data buffer pointers associated with the specified read command. For example, the data needed to satisfy the specified read command may already be cached in Random Access Memory (RAM) on non-volatile memory device. However, the original data buffer pointers to the host memory buffers have not yet been fetched, in this example. Moreover, the memory controller could have some other data buffer pointers to other data buffers in the host memory that it cannot use at the time. For example, these other data buffer pointers might be for a read command that is waiting to be executed in the non-volatile memory device. Rather than delay the data transfer of the already cached data (for the specified read command) to the host memory, the memory controller may transfer the cached data to other data buffers that were to be used for the other read command waiting to be executed. Thus, the cached data can be transferred earlier. The memory controller may fetch the original data buffer pointers for the specified read command in time to use them for the other read command that is waiting to be executed (or another read command).

In some cases, the first data buffer pointer provided by the host may contain an offset while all other data buffers must be aligned to, for example, a multiple of 4 KB. The fact that the first data buffer pointer has an offset complicates the data-transfer operation since host and internal non-volatile memory device buffers may be unaligned for the entire transfer. Replacing the original data buffer pointers with replacement data buffer pointers can simplify the data transfer by causing the host and non-volatile memory device buffers to be aligned.

There are many other possible uses of replacing the one or more data buffer pointers associated with a read command with another set of one or more data buffer pointers. Note that replacing the original data buffer pointers with replacement data buffer pointers may have the effect of swapping the original data buffers with replacement data buffers that are pointed to by the replacement data buffer pointers.

In some embodiments, at least the original data buffer pointers are NVMe Physical Region Page (PRP) entries in a PRP list, which may reside in memory of a host system connected to the non-volatile memory device. The replacement data buffer pointers could be NVMe PRP entries. The replacement data buffer pointers could be from a descriptor list that the host used to point to an NVMe HMB. Note that data buffer pointers are not limited to NVMe. Hence, embodiments of non-volatile memory devices may operate with memory access protocols other than NVMe.

Technology described herein may be used with a variety of types of non-volatile memory. One example is a three-dimensional (3D) non-volatile memory device. However, embodiments may also be practiced in two-dimensional (2D) non-volatile memory device.FIG. 1Ais a perspective view of a set of blocks in a 3D stacked non-volatile memory device100. The non-volatile memory device100includes a substrate101. On the substrate are example blocks BLK0, BLK1, BLK2and BLK3of memory cells (storage elements) and a peripheral area104with circuitry for use by the blocks. For example, the circuitry can include voltage drivers105which can be connected to control gate layers of the blocks. In one approach, control gate layers at a common height in the blocks are commonly driven. The substrate101can also carry circuitry under the blocks, along with one or more lower metal layers which are patterned in conductive paths to carry signals of the circuitry. The blocks are formed in an intermediate region102of the memory device. In an upper region103of the memory system, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block comprises a stacked area of memory cells, where alternating levels of the stack represent control gate layers. In one possible approach, the control gate layers of each block at a common height are connected to one another and to a voltage driver. While four blocks are depicted as an example, two or more blocks can be used, extending in the x- and/or y-directions.

The length of the plane, in the x-direction, may represent a direction in which signal paths to word lines extend in the one or more upper metal layers (e.g., a word line or drain side select gate (SGD) line direction), and the width of the plane, in the y-direction, represents a direction in which signal paths to bit lines extend in the one or more upper metal layers (e.g., a bit line direction). The z-direction represents a height of the memory device.

FIG. 1Bis a functional block diagram of a non-volatile memory device such as the 3D stacked non-volatile memory device100ofFIG. 1A. The functional block diagram may also be used for a 2D non-volatile memory device. The non-volatile memory device100may include one or more memory die108. The set of blocks ofFIG. 1Acan be on one die. The memory die108includes a memory structure126of memory cells, such as an array of memory cells, control circuitry110, and read/write circuits128. In a 3D configuration, the memory structure can include the blocks ofFIG. 1A. The memory structure126is addressable by word lines via a row decoder124and by bit lines via a column decoder132. The read/write circuits128include multiple sense blocks SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically a memory controller122is included in the same non-volatile memory device100(e.g., a removable storage card) as the one or more memory die108. Commands and data are transferred between the host system140and memory controller122via an interface (e.g., data bus)120and between the memory controller and the one or more memory die108via lines118. The host system140may send memory access commands to access the memory structure126, and hence may be referred to as a requestor.

Multiple memory elements in memory structure126may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory systems in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors comprising memory cells and select gate transistors.

A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.

Other types of non-volatile memory in addition to NAND flash memory can also be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), phase change memory (e.g., PCRAM), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory elements can be formed from passive and/or active elements, in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse or phase change material, and optionally a steering element, such as a diode or transistor. The phase change material may include a chalcogenide material. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

The memory structure126can be two-dimensional (2D) or three-dimensional (3D). The memory structure126may comprise one or more arrays of memory elements (also referred to as memory cells). In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-y direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

One of skill in the art will recognize that this technology is not limited to the two dimensional and three dimensional exemplary structures described but covers all relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of skill in the art.

The control circuitry110cooperates with the read/write circuits128to perform memory operations on the memory structure126, and includes a state machine112, an on-chip address decoder114, and a power control module116. The state machine112provides chip-level control of memory operations. A storage region113may be provided for parameters for operating the memory device such as programming parameters for different rows or other groups of memory cells. These programming parameters could include bit line voltages and verify voltages.

The on-chip address decoder114provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders124and132. The power control module116controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word line layers (WLLs) in a 3D configuration, SGS and SGD select gates and source lines. The sense blocks can include bit line drivers, in one approach. A source side select gate (SGS) is a gate transistor at a source-end of a NAND string, and a drain side select gate (SGD) is a transistor at a drain-end of a NAND string.

In some implementations, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure126, can be thought of as one or more control circuits which are configured to perform the actions described herein. For example, one or more control circuits may include any one of, or a combination of, control circuitry110, state machine112, decoders114/124/132, power control module116, sense blocks SB1, SB2, . . . , SBp, read/write circuits128, memory controller122, processor122c, and so forth.

The memory controller122may comprise a processor122cand storage devices (memory) such as read only memory (ROM)122aand RAM122b. RAM122bmay be, but is not limited to, SRAM and DRAM. The storage devices comprise code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor can access code from a storage device region126aof the memory structure, such as a reserved area of memory cells in one or more word lines.

The code is used by the memory controller122to access the memory structure126such as for programming, read and erase operations. The code can include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the memory controller during a booting or startup process and enables the memory controller to access the memory structure. The code can be used by the memory controller to control one or more memory structures. Upon being powered up, the processor122cfetches the boot code from the ROM122aor storage device region126afor execution, and the boot code initializes the system components and loads the control code into the RAM122b. Once the control code is loaded into the RAM122b, it is executed by the processor122c. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

FIG. 2Ais a block diagram of example non-volatile memory device100, depicting more details of one embodiment of a memory controller122and host system140. In one embodiment, the system ofFIG. 2Ais a solid state drive. As used herein, a memory controller is a device that manages data stored on a non-volatile memory device and communicates with a host system, such as a computer or electronic device. In some embodiments, the memory die108contains flash (e.g., NAND, NOR) memory cells, in which case the memory controller122may be a flash memory controller. A memory controller can have various functionality in addition to the specific functionality described herein. For example, the memory controller can format the memory to ensure the memory is operating properly, map out bad memory cells, and allocate spare memory cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the memory controller and implement other features. In operation, when a host needs to read data from or write data to the memory, it will communicate with the memory controller. If the host provides a logical address (LA) to which data is to be read/written, the memory controller can convert the logical address received from the host to a physical address in the memory. The logical address may be a logical block address (LBA), and the physical address may be a physical block address (PBA). (Alternatively, the host can provide the physical address). The memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).

The host system140has one or more processor(s)150and host memory160. In one embodiment, host memory160includes command submission queues (SQs)162and command completion queues (CQs)164. Commands to access the memory structure126in the memory die108may be placed by the host into a command submission queue162. For example, a command might be to read from or write to the memory structure126. Note that a command to read from the memory structure126might be responded to without a physical read of the memory structure126at that time if there a cached version of the data somewhere (such as in data cache266or HMB170). In one embodiment, a command submission queue162is a circular buffer with a fixed size slot. In one embodiment, the host informs the non-volatile memory device when a new command has been placed on a command submission queue162. One such mechanism is referred to herein as a “doorbell.”

The memory controller122may write to an associated command completion queue164to post status for completed commands. In one embodiment, a command completion queue164is a circular buffer with a fixed size slot. The term “queue,” as used herein (including, but not limited to SQ162and CQ164) means non-transitory storage containing a data structure. The non-transitory storage could be, for example, RAM122b, memory structure126, etc.

Data buffers168may be used to store data to be written to the memory structure126or to store data that was read from the memory structure126. The memory controller122may perform a Direct Memory Access (DMA) of data from data buffers168, as a part of writing data to the memory structure126. For example, the memory controller122may transfer write data from data buffers168to write buffers in the non-volatile memory device100. The memory controller122may perform a DMA of data to data buffers168, as a part of reading data from the memory structure126. For example, the memory controller122may transfer read data from read buffers in the non-volatile memory device100to data buffers168.

The host memory160also includes data buffer pointers166. The data buffer pointers166identify locations in the data buffers168. In certain embodiments, the memory controller122uses the data buffer pointers166to perform DMAs to satisfy a read or write command. Note that in one embodiment, a data buffer pointer is located in a command on the command submission queue162.

In one embodiment, the memory controller122replaces one or more of the data buffer pointers166associated with a memory access command with one or more other data buffer pointers. Further details are discussed below.

In one embodiment, the submission queues (SQs)162, command completion queues (CQs)164, and data buffer pointers166are compliant with NVM Express. In one embodiment, the data buffer pointers166are NVMe “Physical Region Page” (PRP) entries. However, the submission queues (SQs)162, command completion queues (CQs)164, and data buffer pointers166are not required to be compliant with NVM Express.

The host memory160also includes a host memory buffer (HMB)170. The HMB170may be a buffer that is allocated by the host system140for use of the memory controller122. In some embodiments, the HMB170is for exclusive usage of the memory controller122. For example, the memory controller122could use the HMB170to cache data. The host system140guarantees that the data in the HMB170will be valid and is obliged to notify the memory controller122before any operation which might cause data loss (e.g., power loss, host might need this buffer, etc., . . . ), in one embodiment. The host system140lets the memory controller122acknowledge this operation before the data is lost, in one embodiment. In one embodiment, NVMe specifies the requirements for the HMB170, which state that the HMB170is allocated for exclusive use by the memory controller122and the data is guaranteed to be valid. In one embodiment, the host system140allocates the HMB170to the memory controller122when the memory controller122is initialized. The memory controller122is initialized when the non-volatile memory device100is powered on, in one embodiment.

The interface120between the host system140and the memory controller122may be any suitable interface. In one embodiment, the interface120is a Peripheral Component Interconnect Express (PCIe) bus. In one embodiment, the non-volatile memory device100may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternative embodiment, the non-volatile memory device100may be part of an embedded non-volatile memory device. For example, the non-volatile memory device100may be embedded within the host system140, such as in the form of a solid state disk (SSD) drive installed in a personal computer.

As depicted inFIG. 2A, the memory controller122includes a front end module208that interfaces with host system140, a back end module210that interfaces with the one or more memory die108, each containing various other components or modules that perform functions which will now be described in detail.

The memory controller122may interface with one or more memory dies108. In one embodiment, the memory controller122and multiple memory dies (together comprising the non-volatile memory device100) implement a solid state drive (SSD), which can emulate, replace or be used instead of a hard disk drive inside a host, as a Network Attached Storage (NAS) device, etc. Additionally, the SSD need not be made to work as a hard drive.

In some embodiments, the non-volatile memory device100includes a single channel between the memory controller122and memory die108, the subject matter described herein is not limited to having a single memory channel. For example, in some non-volatile memory device architectures, 2, 4, 8 or more channels may exist between the memory controller122and the memory die, depending on memory controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the memory controller and the memory die, even if a single channel is shown in the drawings.

Referring again to modules of the memory controller122, front end module208includes a physical layer interface (PHY)222that provide the electrical interface with the host system140or a next level storage memory controller. In one embodiment, PHY222includes hardware that is compliant with Peripheral Component Interconnect Express (PCIe). However, PHY222is not limited to PCIe.

The front end module208typically facilitates transfer for data, control signals, and timing signals. In some embodiments, the front end module208is capable of processing commands (e.g., memory access commands to read or write the memory structure126in the memory dies108) that are described in NVM Express (NVMe). NVMe is a logical device interface that may be used to access non-volatile storage attached when using a PCIe bus between the host system140and the non-volatile memory device100. However, note that the logical device interface is not limited to NVMe. Also, the bus is not limited to a PCIe bus.

A host queue manager246is configured to fetch and parse commands from the command submission queue162. The host queue manager246may also queue the commands internally (i.e., within the memory controller122) for execution. In one embodiment, the host queue manager246determines when to send a command from the internal queue (within the memory controller122) to a command executer228within a backend module210of the memory controller122. In one embodiment, the host queue manager246also sends an indication to the host system140when a command is complete. For example, the host queue manager246could store information on command completion queue162when a command (such as a read or write command) is complete.

The control path242has host pointer manager250. The control path242has access to storage251that may have stored therein data buffer pointers252, management tables256, and HMB pointers172. Storage251may be volatile or non-volatile memory. The host pointer manager250is configured to fetch data buffer pointers166from the host memory160. For example, a command (such as a read or write command) that is fetched by the host queue manager246may have one or more data buffer pointers associated with it. In certain embodiments, the host pointer manager250is configured to fetch the data buffer pointers associated with a command, and to store them as data buffer pointers252in storage251. In one embodiment, data buffer pointers252are NVMe PRP entries.

The host pointer manager250may also be configured to replace one or more of the original data buffer pointers associated a given command (e.g., read command) with one or more replacement data buffer pointers. In one embodiment, the host pointer manager250writes one or more replacement data buffer pointers to a command on the command submission queue162in host memory160to perform the data buffer pointer replacement. In one embodiment, the host pointer manager250replaces one or more original data buffer pointers166in host memory160to perform the data buffer pointer replacement. Numerous techniques are described herein for such replacements. Numerous reasons for such replacements are also described herein.

The storage251to which control path242has access also includes management tables256. In one embodiment, the management tables256include L2P tables (logical to physical mappings) and P2L tables (physical to logical mappings). The memory controller122can use the management tables256to map logical addresses (LAs) to physical addresses (PAs). Such tables256can be used to directly map LAs to the PAs, or LAs can be mapped to intermediate or virtual addresses, which are mapped to PAs. In some embodiments, the logical addresses are logical block addresses, and the physical addresses are physical block addresses. Other variations are also possible.

The management tables256may also be used to manage caching of data in locations other than the memory structure126in the memory die108. In one embodiment, the memory controller122caches data in the HMB170. For example, the memory controller122may use the HMB170to cache data that is associated with some LA (or range of LAs). The management tables256may also be used to manage caching of data in the HMB170. In one embodiment, the memory controller122caches data in the data cache266. For example, the memory controller122may use the data cache266to cache data that is associated with some LA (or range of LAs). The management tables256may also be used to manage caching of data in the data cache266. The data cache266is volatile memory (such as RAM122bofFIG. 1B), in one embodiment.

The storage251to which control path242has access also includes HMB pointers172. The HMB pointers172are data buffer pointers to the HMB170. For example, each HMB pointer172could point to one unit of memory. Each unit of memory could be a page, wherein the page size is set by the host system140. In one embodiment, the HMB pointers172are Host Memory Buffer Descriptors, in accordance with the NVMe protocol. However, the HMB pointers172are not limited to the NVMe protocol.

The front end module208can include other elements not expressly depicted inFIG. 2A. In one embodiment, front end module208includes various registers. In one embodiment, one of the registers is a “doorbell register,” which the host system140may write in to inform the non-volatile memory device100that a new command is on the SQ162.

DMA logic253is configured to control DMA transfer of data between the non-volatile memory device100and the host memory160in the host system140. For example, DMA logic253may access data from data buffers168and transfer it to write buffers in RAM (e.g.,FIG. 1B, 122b). DMA logic253may use data buffer pointers166to access the correct location in data buffers168. DMA logic253may transfer data from read buffers in RAM122band transfer to data buffers168. DMA logic253may use data buffer pointers166to access the correct location in data buffers168to transfer data read from memory structure126in a memory die108. DMA logic253is also able to make a direct memory access to the host memory buffer170. For example, DMA logic253may cache data into the HMB170.

Back end module210includes a Scheduler226, command executer228, an error correction Controller (ECC) engine224, and a memory interface230.

Command scheduler226generates command sequences, such as program, read, and erase command sequences, to be transmitted to memory die108. Command executer228oversees execution of those commands.

Memory interface230provides the command sequences to memory die108and receives status information from memory die108. In one embodiment, memory interface230may be a double data rate (DDR) interface. In some embodiments, the memory interface203is a flash memory interface. However, the memory cells in memory die108are not limited to flash. Hence, memory interface230is not limited to a flash memory interface. In the event that memory cells in memory die108are flash, the back end module210may include a flash control layer, which controls the overall operation of back end module210.

ECC engine224encodes the data bytes received from the host system140, and decodes and error corrects the data bytes read from the memory die108. In one embodiment, the ECC engine224comprises a low-density parity check (LDPC) decoder. Note that for both reads and writes, back end module210may perform additional processing of the data such as Error correction, scrambling, etc. Thus, for example, the data that is transferred to the data buffers168is typically not the raw data read from memory die108.

The components of memory controller122depicted inFIG. 2Amay take the form of a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry (or one or more processors) that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. For example, each module (including, but not limited to, host queue manager246and host pointer manager250) may include an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or in addition, each module may include or comprise software stored in a processor readable device (e.g., memory) to program a one or more processors for memory controller122to perform the functions described herein. The architecture depicted inFIG. 2Ais one example implementation that may (or may not) use the components of memory controller122depicted inFIG. 1B(e.g., RAM122b, ROM122a, processor122c).

Note that as a matter of convenience of explanation, storage251is depicted as within the memory controller122. For example, storage251(containing data buffer pointers252, management tables256, and HMB pointers172) is depicted within the control path242. Note that storage251can be located within the memory controller122or external to the memory controller122. Also, storage251could be implemented in volatile memory (e.g., RAM122bofFIG. 1B) or non-volatile memory (e.g., memory structure126). For example, the management tables256could be stored in the memory structure126, with a portion of the management tables256cached in RAM122b.

FIG. 2Bis a diagram of another embodiment of a non-volatile memory device100and host system140. In this embodiment, SQs162, CQs164, and data buffer pointers166are stored in the non-volatile memory device100. The SQs162, CQs164, and data buffer pointers166may be stored in volatile memory (e.g., RAM122b) or non-volatile memory (e.g., memory structure126). For example, the SQs162, CQs164, and data buffer pointers166can be stored in flash memory cells in a memory array. The portion of storage that stores the SQs162, CQs164, data buffer pointers166, and HMB pointers172may be referred to as a controller memory buffer (CMB). The submission queues (SQs)162in the non-volatile memory device100allow the host system140to directly write commands to the memory controller's internal memory space, in one embodiment. This alleviates the need for the memory controller122to access commands from the host memory160. The data buffer pointers166in the non-volatile memory device100allow the host system140to directly write the data buffer pointers to the memory controller's internal memory space, in one embodiment. Likewise, the HMB pointers172in the non-volatile memory device100allow the host system140to directly write the data buffer pointers to the memory controller's internal memory space, in one embodiment. A controller memory buffer based SQs162, CQs164, and data buffer pointers166may be used in a similar manner when the SQs162, CQs164, and data buffer pointers166are stored on the host system140. A difference being that the memory controller's memory space is used instead of the host memory160.

In the embodiment ofFIG. 2B, the host memory160contains data buffers168and HMB170. Thus, the memory controller122may initiate DMAs to/from data buffers168based on data buffer pointers166.

Other variations to the embodiments depicted inFIGS. 2A and 2Bare possible. For example, any subset of the SQs162, CQs164, and data buffer pointers166may be stored in the non-volatile memory device100. For example, SQs162and CQs164are stored in the non-volatile memory device100, but data buffer pointers166are stored in the host memory160, in one embodiment.

FIG. 3Ais a diagram of one example of a host command320, data buffers168, and lists304of data buffer pointers322. In some embodiments, the memory controller122replaces one or more of the original data buffer pointers with another set of one or more replacement data buffer pointers. Such replacement can save time and/or power when responding to a read command.

In one embodiment, each of the data buffers168is a physical page in the host memory160. Also, each of the lists304is a physical page in the host memory160, in one embodiment. The lists304reside in data buffer pointers166in the host memory160, in one embodiment. However, note that the lists304could alternatively reside in the non-volatile memory device100. For example, with respect to the embodiment ofFIG. 2B, the lists304could reside in data buffer pointers166.

The host system140may place the host command320on SQs162in host memory160, in one embodiment. The host system140may place the host command320on SQs162in RAM122b, in one embodiment. Note that the host command320could be for a memory access operation, such as write (also referred to as “program”) or read. The command identifier340may be used to identify the command. In other words, the command identifier340may distinguish one read command from another read command, etc. The memory controller122may use this command identifier340to provide status for the completed command on the completion queue (e.g.,FIG. 2A, 164orFIG. 2B, 164). The command type342indicates the type of command (e.g., read, write, etc.). The starting LBA field344indicates the starting logical block address (LBA) for a read or write. The length field346is for the length of the read or write. The length could be specified as a number of logical blocks. Note that the memory controller122may convert the starting LBA, as well as other LBAs as indicated by the length of the read or write, to physical addresses in memory structure126.

In an embodiment, the host command320includes a field that may contain a data buffer pointer322, and a field that may contain a list pointer324(1). For example, data buffer pointer322in host command320may point to a data buffer168in the host memory160. List pointer324(1), if used, may point to a list304of data buffer pointers in the host memory160, in one embodiment. Note that in some embodiments, list pointer324(1), if used, may point to a list of data buffer pointers in the non-volatile memory device100(e.g.,166,FIG. 2B). The host command320may have other fields as well. For example, various fields may be used for data management, such as whether the data is compressible, whether this command is part of a sequential request, latency requirements, etc.

InFIG. 3A, data buffer pointer322in the host command320points to the first data buffer in host memory, in this example. In some embodiments, data buffer pointer322in the host command320has an offset which may be zero or non-zero. The offset may be used to refine the starting location of the data buffer.

List pointer324(1) points to a list304(1) of data buffer pointers, in this example. List304(1) contains a number of entries. All but the last entry contains a data buffer pointer322, which each point to a data buffer in the host memory. The last entry324(2) in list304(1) contains a pointer to another list304(2). List304(2) contains a number of entries. All but the last entry contains a pointer322to a data buffer in the host memory. The last entry324(3) in list304(2) may contain a pointer to still another list304(not depicted inFIG. 3A). Herein, the term “list pointer” may be used to refer to a pointer to a list that includes data buffer pointers322. However, note that the list could also include entries that are not data buffer pointers, such as a pointer to another list. Note that the least entry is not always a pointer to another list304. The last entry may simply be a pointer to a data buffer.

In one embodiment, the entry for each data buffer pointer322is a physical region page (PRP) entry as the term is used in NVMe. A physical region page (PRP) entry may be a pointer to a physical memory page in host memory. The PRPs may be used as a scatter/gather mechanism for data transfers between the non-volatile memory controller122and the host memory160. In one embodiment, the size of a physical memory page in host memory160is configured by the host system140. For example, the host system140might specify that each physical memory page is 4 KB, 8 KB, 16 KB, or some other size.

In one embodiment, the PRP entries are a fixed size. In one embodiment, a PRP entry may be a 64-bit (e.g., 8 Byte) physical memory page address. However, the PRP entries could be larger or smaller than 64-bits. A PRP entry may have a page base address and an offset. In one embodiment, the lower bits of a PRP entry indicate an offset within a physical memory page in host memory. For example, if the memory page is 4 KB, then bits 11:02 may form the offset, if the memory page is 8 KB, then bits 12:02 may form the offset, etc.

In one embodiment, the entries for the list pointers324are each a pointer to a list of NVMe PRPs. Thus, in one embodiment, lists304are PRP lists. As one example, a PRP list could have 512 PRP entries. For example, the PRP list could be 4 KB in size, with 512 PRP entries that are each 64 bits. However, there may be more or fewer PRP entries in a PRP list. Also, the PRP list could be larger or smaller than 4 KB. For example, an 8 KB PRP list might contain 1024 entries that are each 64 bits. In one embodiment, the PRP list has a size equal to one single page of contiguous memory in the host memory.

Note that the host command320may be associated with more than one list304of data buffer pointers. The total number of data buffer pointers that are needed for a command may be implied by the command parameters and the physical memory page size. The last entry in the list304may either be a pointer to a data buffer or a pointer to the next list. In the event that the last entry is a pointer to the next list, that entry points to a host memory address that contains the next list304. Note that the next list304may comprise one physical memory page.

In one embodiment, the memory controller122is able to determine the location of the last entry in a given list304based on the size of one physical memory page. The memory controller122is able to determine whether the last entry is a pointer to another list304or is a data buffer pointer based on whether more data buffer pointers are needed to satisfy the read or write command, in one embodiment.

There could be a large number of lists304. For example, a command might be to read 256 MB in the non-volatile memory device. If each data buffer is 4 KB, this might require about 64,000 data buffers—and hence 64,000 list entries. With each list entry being 64 bits, this means that the data buffer pointers could use about 512 KB of storage.

Note that for some read or write commands, list pointer324(1) in the host command320is not used. For example, if a read is for just a one data buffer, then just the data buffer322in the host command320might be used. Also, in some cases, there might be just one list304. Again, this may be the case if there is a relatively small amount of data to be read or written.

As briefly mentioned above, the memory controller122may replace one or more of the original data buffer pointers with another set of one or more replacement data buffer pointers, in one embodiment. In one embodiment, the memory controller122replaces the data buffer pointer322in the host command with a replacement data buffer pointer that points to a different data buffer in host memory. In one embodiment, the memory controller122replaces the list pointer324(1) with a list pointer that points to a different list of data buffer pointers. This in effect will replace the list304(1) with a replacement list. Thus, the data buffer pointers322in the original list will be replaced with the data buffer pointers322in the replacement list. In one embodiment, the memory controller122replaces the list pointer324(2) with a list pointer that points to a replacement list. This in effect will replace the list304(2) with another list. Likewise, list pointer324(3) could be replaced with another list pointer. In one embodiment, the memory controller122replaces one or more of the original data buffer pointers322in a list with a corresponding one or more replacement data buffer pointers. Note that the host system140may obtain the replacement data buffer pointers simply by accessing the host command320and associated lists304, in one embodiment.

Replacing one or more of the original data buffer pointers with another set of one or more replacement data buffer pointers may save time and/or power when responding to a read command. For example, in some cases, the data needed to respond to a read command may already be cached in the host memory. Replacing the original data buffer pointers associated with the read command with replacement data buffer pointers to the data already cached in host memory is a very efficient way to respond to the specific read command.FIGS. 8A-8Cdepict one embodiment of replacing the original data buffer pointers associated with the read command with replacement data buffer pointers to the data already cached in host memory.

Note that many of the data buffer pointers322inFIG. 3Aare not in the host command320. Thus, even after the memory controller122has fetched a specific read command, it may take some time to obtain the data buffer pointers in the lists304. In some cases, the data needed to respond to the specific read command is already cached in the non-volatile memory device. However, as noted, the memory controller might not have obtained the data buffer pointers to the data buffers to which the memory controller is to transfer the data. However, the memory controller122might have already obtained data buffer pointers for another read command. Moreover, the memory controller122might not be able to use those data buffer pointers at this time because the data for the other read command has not yet been read from memory structure126. Replacing the original data buffers pointers for the specific read command with the data buffer pointers for the other read command (which may be referred to as replacement data buffer pointers) can save time in responding to the specific read command.FIG. 9depicts one embodiment of replacing the original data buffer pointers associated with a read command for which data is cached in the non-volatile memory device with replacement data buffer pointers that were originally for a read command that is presently waiting to be executed (and hence data has not yet been obtained from non-volatile storage126).

In one embodiment, the first data buffer pointer in the command from the host system140may have an offset.FIG. 3Bshows a diagram of another example of a host command320, data buffers168, and list of data buffer pointers similar toFIG. 3A. List304(2) fromFIG. 3Ais not depicted so as to simplify the diagram. Also, the data buffer pointer322in host command320inFIG. 3Bhas a non-zero offset323. With this offset323, the size of the first data buffer168(0) is less than the size of other buffers. For example, buffers168(1) through168(24) may each be 4 KB. However, the used portion of buffer168(0) may be less than 4 KB by the size of the offset323. Note that a data buffer may be defined by the size of a data buffer (which may be a fixed value specified by the host) and the host memory address to which a data buffer pointer points. For example, the pointers to data buffers168(1),168(2), etc. point to the beginning of the data buffer, in one embodiment.

The offset323may potentially cause all transfers between the host system140and the non-volatile memory device100to be unaligned. For example, the non-volatile memory device may want to transfer the first 64 KB. Assuming a 4 KB data buffer, this corresponds to eight complete data buffers. In this example, the pointer322to the first buffer is needed for the data transfer as well as the eight data buffer pointers in the first list304(1). These eight data buffer pointers point to data buffers168(1) to168(8). However, the last data buffer (e.g., 168(8)) associated with this example 64 KB transfer will not be fully populated from this 64 KB data due to the offset. In one embodiment, a replacement of one or more original data buffer pointers is used to cause the data transfer to be aligned, thereby creating a more efficient data transfer.FIG. 10and its description are one embodiment of replacing an original data buffer pointer when there is an offset323associated with a data buffer pointer.

FIG. 4is a flowchart of one embodiment of a process400of operating a non-volatile memory device. The process400may include replacing one or more original data buffer pointers associated with a memory access command with one or more replacement data buffer pointers. In one embodiment, a memory controller122performs the process400. In one embodiment, the process400is performed in an environment such as depicted inFIG. 2Ain which the host system140contains SQs162, CQs164, and data buffer pointers166. In one embodiment, the process400is performed in an environment such as depicted inFIG. 2Bin which the non-volatile memory device100contains SQs162, CQs164, and data buffer pointers166. In one embodiment, process400is performed in an environment in which the host system140contains data buffer pointers166, but non-volatile memory device has SQs162and CQs164. In some embodiments, the host system140has data buffer pointers166. In some embodiments, the data buffer pointers166are NVMe PRP entries.

In step402, the memory controller122accesses a read command that was provided by the host system140. The read command contains an address (e.g., logical address) and length, in one embodiment. The memory controller122may translate the logical address to a physical address. The physical address may be in memory structure126. Note that the memory controller122might not need to access the memory structure126to respond to the read command if, for example, the data for the logical address is cached in data cache266or HMB170. In one embodiment, the memory controller122accesses the command from SQs162in the host memory160. In one embodiment, the memory controller122accesses the command from SQs162on the non-volatile memory device100.

The read command may be associated with at least one original data buffer. The original data buffer(s) are locations in host memory160at which the memory controller122is to store data for the logical address(es) specified by the read command. The read command may also be associated with at least one data buffer pointer322to the original data buffers. One or more of the data buffer pointers322may be in the read command itself. For example, host command320inFIG. 3Ahas a data buffer pointer322in the command. However, the data buffer pointer need not be in the command itself. For example, host command320inFIG. 3Ahas a list pointer324(1) that points to a list304(1) of data buffer pointers322. Also, list304(1) itself has a list pointer324(2), which points to another list304(2) of data buffer pointers322.

Step402may include the memory controller122responding to a “doorbell.” The doorbell is a mechanism by which the host system140informs the non-volatile memory device100that a new command is ready on a submission queue (SQ)162, in one embodiment. In one embodiment, the memory controller122has a doorbell register, which the host system writes to “ring the doorbell.” The memory controller122may fetch the new command from the SQ162in response to the doorbell. In one embodiment, memory controller122accesses the read command from host memory160(e.g., command submission queue162,FIG. 2A). In one embodiment, memory controller122accesses the read command from RAM122bin the non-volatile memory device (e.g., command submission queue162,FIG. 2B).

In step404, the memory controller122determines whether there are more original data buffers for which replacement data buffers might instead be used. Note that some original data buffers might be used, while replacement data buffers might be used for other original data buffers associated with the read command. In one embodiment, the memory controller122may replace one or more original data buffer pointers with one or more replacement data buffer pointers in order to cause the replacement data buffers to be used. Thus, some original data buffer pointers may be replaced while others might not be replaced. Hence, the process400describes processing different groups of original data buffers for the read command. One technique for determining whether there are more original data buffers to process is to access the length of the data to be read from the read command, and factor in the size of data buffers168. Assuming that there are more original data buffers associated with the read command, the process400continues as step406.

Step406includes the memory controller122determining whether to use one or more replacement data buffers instead of a corresponding one or more original data buffers. In one embodiment, the memory controller122determines whether to perform replacement of one or more original data buffer pointers associated with the read command. Note that the original data buffer pointers may be referred to as a “set” of original data buffer pointers, wherein the set includes one or more original data buffer pointers. The determination of whether to replace the original data buffer pointers may be based on a variety of factors. In one embodiment, the memory controller122determines whether to replace one or more original data buffer pointers responsive to a determination that the HMB170has data needed to respond to the command. Further details of one such embodiment are shown and described with respect toFIGS. 8A-8C.

In one embodiment, the memory controller122replaces a data buffer pointer (to host memory) that has not yet been obtained by the memory controller with a data buffer pointer (to host memory) that has already been obtained by the memory controller. In one embodiment of step404, the memory controller122replaces one or more original data buffer pointers responsive to a determination that there is a command (e.g., read command) waiting to be executed and for which one or more data buffer pointers have already been obtained. In this case, the already obtained data buffer pointer(s) may be used to replace the original data buffer pointer(s). Further details of one such embodiment are shown and described with respect toFIG. 9.

In one embodiment, the memory controller122replaces one or more original data buffer pointers responsive to a determination that the data buffer pointer322in the host command322has a non-zero offset. Further details of one such embodiment are shown and described with respect toFIG. 10.

The determination of whether to replace the original data buffer pointers may be based on many other factors than the embodiments inFIGS. 8A-10. Other factors include, but are not limited to, data transfer size, host memory page size, PCIe bus turnaround time, avoidance of a copy operation, and number of available data buffer pointers.

Step408includes selecting replacement data buffer pointer(s) for the data buffer pointers(s) associated with the command (e.g., read command). In one embodiment, the replacement data buffer pointer(s) are data buffer pointers associated with another command (e.g., read command) to access the non-volatile storage. For example, data buffer pointers of one read command may be used to replace data buffer pointer of the present command (e.g., read command). In one embodiment, the replacement pointer(s) are HMB pointers172. Thus, note that the replacement data buffers could be in the HMB170.

Step410includes replacing the data buffer pointers associated with the command with the selected replacement data buffer pointers. There are numerous techniques for replacing the original data buffer pointers.FIGS. 5A-5C, 6A-6C, and 7A-7Cshow a few embodiments for replacing the original data buffer pointers.

Step412includes transferring data to the replacement data buffer(s), if needed. Step410may include populating the replacement data buffers that are pointed to by the replacement data pointers with data. Note that step410might be performed prior to accessing the read command in step402. For example, step410might have been performed when transferring data for a different command from the non-volatile memory device100to the host memory160. Thus, also note that step410may be performed prior to selecting the replacement pointers in step408.

Step412may include the memory controller122performing a DMA between the non-volatile memory device100and the host memory data buffers specified by the replacement data buffer pointers. The DMA is from a read buffer in the non-volatile memory device100to a data buffer in the host memory160, in one embodiment.

The process400then returns to step404to determine whether there are more original data buffers for which replacement data buffers might be used instead. Alternatively, this step may be described as determining whether there are more original data buffer pointers to consider for replacement. For the sake of discussion, there are additional original data buffers to consider. Returning again to the discussion of step406, in the event that the memory controller122determines to not use replacement data buffers for at least some of the original data buffers, then step414is performed. The path down step414may result in using original data buffer pointers and original data buffers associated with the read command. Step414includes transferring data to the original data buffers (for which replacement data buffers are not used).

The process400then returns to step404to determine whether there are more original data buffers for which replacement data buffers might be used instead. Assuming that there are not, then step416may be performed. Step416includes the memory controller122indicating to the host system140which data (if any) for the read command is stored in replacement data buffers and which data (if any) was stored in original data buffers. As noted, in some cases, it is possible to use some of the original data buffers and some replacement data buffers. Thus, for a single command it is possible to perform steps408-412for some original data buffers (and their pointers), while performing step414for other original data buffers (and their pointers).

Step416may include the memory controller122indicating to the host system140that the data for at least one logical address specified by the read command was stored in one or more replacement data buffers. Step416may also include the memory controller122specifying the location of the one or more replacement data buffers to the host system140. Step416may include the memory controller122instructing the host system140to use the one or more replacement data buffers instead of one or more original data buffer pointers to obtain the data for at least one logical address.

Step416may include the memory controller122sending a command completion for the command of step402to the host system140. In one embodiment, the memory controller122places a command response on the command completion queue164. Note that to “place a command response on the command completion queue”164the memory controller122writes information to host memory160in one embodiment in which CQ164is stored in host memory160. Note that to “place a command response on the command completion queue”164the memory controller122writes information to storage251in one embodiment in which CQ164is stored in storage251in the non-volatile memory system100. The memory controller122may also provide some indication to the host system140that the command response has been placed on the command completion queue164. Note that step416is performed after transforming data to the replacement data buffers, in step412. Also, step416is performed after replacing the replacing the original data buffer pointers in step410. Moreover, note that when the host system140looks for the data for the read command, the host system140will obtain the replacement data buffer pointers simply by reading at the location at which the host system140placed the original data buffer pointers, in one embodiment. For example, with respect toFIG. 3A, the host system140may access the host command320from a submission queue162, and use list pointer324(1) to locate lists304. Thus, the act of sending the command completion informs the host system140that one or more of the original data buffer pointers have been replaced by a corresponding one or more replacement data buffer pointers, in one embodiment. Also, the act of sending the command completion specifies the location of the one or more replacement data buffers to the host system140, in one embodiment. Also, the act of sending the command completion instructs the host system140to use the one or more replacement data buffers instead of one or more original data buffer pointers to obtain the data for at least one logical address, in one embodiment.

FIGS. 5A-5Cdepict one embodiment of replacing a data buffer pointer in the host command itself.FIG. 5Ais a flowchart of one embodiment of a process500of replacing a data buffer pointer in the command itself. The process500may be used for some steps (e.g.,406,408,410, and414) of process400.FIGS. 5B and 5Cdepict simplified versions of the host command320that was previously discussed with respect toFIG. 3A.FIG. 5Bdepicts the host command320as it was received in step402of process400. Thus,FIG. 5Bdepicts what the memory controller122may access from a command submission queue162. The host command320has an original data buffer pointer322ato an original data buffer168a. The original data buffer168amay be anywhere in the host memory160. The host command320is a read command, in one embodiment.

Step502includes a determination of whether the data buffer pointer in the host command320can be replaced. In one embodiment, the memory controller122determines whether original data buffer pointer322ato original data buffer168acan be replaced with a pointer to another data buffer. In one embodiment, the host queue manager246fetches the host command320from command submission queue162. The host pointer manager250determines whether there is another data buffer pointer that might be used instead of the original data buffer pointer322a. Step502is one embodiment of step406in process400. The memory controller122may determine the data buffer pointer in the host command320can be replaced based on factors already discussed in step406. Further details of embodiments of making this determination are discussed below with respect toFIG. 8A(see for example step804),FIG. 9(see for example steps904and906); andFIG. 10(see for example step1004).

Step504is performed if the original data buffer pointer can be replaced. Step504includes replacing the original data buffer pointer in the host command320with a replacement data buffer pointer to a different data buffer in host memory160. In one embodiment, the memory controller122modifies the host command320that is on the command submission queue162. Note that to “modify the host command320” the memory controller122changes information in memory that stores the host command320. With reference toFIGS. 5B and 5C, the original data buffer pointer322ato the original data buffer168amay be replaced with a replacement data buffer pointer322bto a replacement data buffer168b. Step504is one embodiment of steps408and410in process400.

The replacement data buffer168bcould be anywhere in host memory160. The replacement data buffer168bmay be data buffers168. In one embodiment, the replacement data buffer168bis in the HMB170. In this case, the replacement data buffer pointer322bmay be one of the HMB pointers172.

Note that at some point the memory controller122populates the replacement data buffer168bwith data, in one embodiment. However, this could happen prior to or after process500. For example, one reason why the replacement data buffer168bmay have been selected was that it already contained the data needed to respond to a read command. For example, the data to respond to a read command might have been cached in the HMB, in which case the replacement data buffer168bwould have been populated prior to process500.

Note that if the data buffer pointer in the read command could not be replaced, then the original data buffer pointer (and original data buffer) is used (step526). Step506is one embodiment of step414in process400.

In one embodiment, the data buffer pointer replacement is achieved by replacing a list pointer. Note that to “replace a list pointer” the memory controller122changes information in memory that stores the list pointer. The list pointer may be a pointer to a list of data buffer pointers.FIGS. 6A-6Cdepict one embodiment of replacing an original list pointer with a replacement list pointer.FIG. 6Ais a flowchart of one embodiment of a process600of replacing a list pointer324. The process600may be used for some steps (e.g.,406,408,410, and414) of process400.FIGS. 6B and 6Cdepict simplified versions of the host command320that was previously discussed with respect toFIG. 3A. Note that the host command320is a read command, in one embodiment.FIG. 6Bdepicts the host command320as it was received in step402. Thus,FIG. 6Bdepicts what the memory controller122may access from a command submission queue162. The host command320has an original list pointer324a, which points to an original list304aof data buffer pointers. The original list304aof data buffer pointers points to original data buffers168a. Note that the original list pointer324ais not required to be in the host command320. An alternative is for the original list pointer324ato be in one of the lists304of data buffer pointers. Note thatFIGS. 6B and 6Cdo not show the data buffer pointers in the lists304. However, each list304contains data buffer pointers322, each of which may point to a data buffer168, as depicted inFIG. 3Afor example.

Step602includes a determination of whether the original list pointer324acan be replaced. In one embodiment, the memory controller122determines whether the original list pointer324ato the original list304aof data buffer pointers can be replaced. This may be based in part on whether the original data buffers168acan be replaced with a set of replacement data buffers. Step602is one embodiment of step406in process400. The memory controller122may determine whether the original list pointer324ato the original list304aof data buffer pointers can be replaced based on factors already discussed in step406. Further details of embodiments of making this determination are discussed below with respect toFIG. 8A(see for example step804),FIG. 9(see for example steps904and906); andFIG. 10(see for example step1004).

Step604is performed if the original list pointer324acan be replaced. Step604is one embodiment of steps408and410in process400. With reference toFIGS. 6B and 6C, step604may include replacing the original list pointer324awith a replacement list pointer324bto a replacement list304bof pointers. The replacement list304bcontains data buffer pointers322that point to replacement data buffers168b. Thus, original data buffers168aare replaced by replacement data buffers168b, in this embodiment. The replacement data buffers168bcould be anywhere in host memory160. In one embodiment, the replacement data buffers168bare in the region of host memory that was allocated to memory controller122as the HMB170. In this case, the replacement list304bmay be a list of HMB pointers172. However, the replacement data buffers168bare not required to be in the region of host memory160that was allocated to memory controller122as the HMB170. It follows that the replacement list304bis not required to be a list of HMB pointers172.

Note that the data buffer pointers in the original list304astill point to the original data buffers168aafter step604(see also,FIG. 6C). Furthermore, note that at some point, the memory controller122may fetch the data buffer pointers in the original list304a, such that the memory controller122may use those original data buffer pointers for another purpose (such as for another host command320). Also note that no changes are needed to the data buffer pointers in the replacement list304bto implement step604.

In one embodiment, memory controller122modifies the host command320that is on the command submission queue162in step604. With reference toFIG. 3A, the memory controller may modify list pointer324(1). The list pointer324that is modified need not be in the host command320. In one embodiment, the list pointer is in a list304. For example, the memory controller may modify list pointer324(2) and/or list pointer324(3), with reference toFIG. 3A.

Note that at some point the memory controller122populates the replacement data buffers168bwith data, in one embodiment. However, this could happen prior to or after process600. For example, one reason why the replacement data buffers168bmay have been selected was that they already contained the data needed to respond to a read command. For example, the data to respond to a read command might have been cached in the HMB170, in which case the replacement data buffers168bwould have been populated prior to process600.

Note that step602can be performed for each list pointer324associated with the command. Step606may be performed for any list pointers324that are not to be replaced. In step606, the original list pointer (and original data buffers) are used. Step606is one embodiment of step414in process400.

In one embodiment, the data buffer pointer replacement is achieved by replacing one or more data buffer pointers322in a list304of data buffer pointers. Note that to “replace one or more data buffer pointers322” the memory controller122changes information in memory that stores the one or more data buffer pointers322.FIGS. 7A-7Cdepict one embodiment of replacing one or more original data buffer pointers322ain a list304of data buffer pointers with one or more replacement data buffer pointers322b.FIG. 7Ais a flowchart of one embodiment of a process700of replacing one or more data buffer pointers322in a list304. The process700may be used for some steps (e.g.,406,408,410, and414) of process400. The process700could be performed separately for each pointer in a list.FIGS. 7B and 7Ceach depict a list304of data buffer pointers322. In this embodiment, the location of the list304does not change. For example, the lists304inFIGS. 7B and 7Cmay occupy the same location in host memory160. However, the content of the two lists inFIGS. 7B and 7Care different in this embodiment.

FIG. 7Bdepicts the list304as it was when a read command is received in step402of process400. Thus,FIG. 7Bdepicts the list304that the memory controller122may access from host memory160.

Step702includes a determination of whether an original data buffer pointer in the list304can be replaced. This may be based in part on whether the original data buffer168acan be replaced with a replacement data buffer. Step702is one embodiment of step406in process400. The memory controller122may determine whether the original data buffer pointer in the list304can be replaced based on factors already discussed in step406. Further details of embodiments of making this determination are discussed below with respect toFIG. 8A(see for example step804),FIG. 9(see for example steps904and906); andFIG. 10(see for example step1004).

Step704is performed if the original data buffer pointer can be replaced. Step704is one embodiment of steps408and410in process400. With reference toFIGS. 7B and 7C, step704may include replacing the original data buffer pointer322awith a replacement data buffer pointer322b. Each replacement data buffer pointer322bpoints to a replacement data buffer168b. Thus, original data buffers168aare replaced by replacement data buffers168b, in this embodiment. The replacement data buffers168bcould be anywhere in host memory160. In one embodiment, the replacement data buffers168bare in the region of host memory that was allocated to memory controller122as the HMB170. In this case, the replacement data buffer pointers322bmay be HMB pointers172. However, the replacement data buffer pointers322bare not required to be HMB pointers172. Also, the replacement data buffers168bare not required to be in the region of host memory that was allocated to memory controller122as the HMB170.

Note that at some point the memory controller122populates the replacement data buffers168bwith data, in one embodiment. However, this could happen prior to or after process700. For example, one reason why the replacement data buffers168bmay have been selected was that they already contained the data needed to respond to a read command. For example, at least some of the data to respond to a read command might have been cached in the HMB170, in which case the replacement data buffers168bwould have been populated prior to process700.

Note that step702can be performed for each original data buffer pointer322ain each list304associated with the host command320. Step706may be performed for any original data buffer pointers322athat are not to be replaced. In step706, the original data buffer pointer322a(and original data buffer168a) are used. Step706is one embodiment of step414in process400.

FIG. 8Ais a flowchart of one embodiment of a process800of replacing original data buffer pointers with replacement data buffer pointers in response to determining data for a read command is cached in host memory. Process800may result in replacing original data buffers for a command with replacement data buffers for that command. Process800may be used in some of the steps of process400(e.g., steps402,406,408,410, and/or414).FIG. 8Awill be discussed in connection withFIGS. 8B and 8C, which depict usage of host memory160and HMB pointers172on the non-volatile memory device100, in one embodiment. Recall that HMB pointers172may be stored in volatile or non-volatile memory on the non-volatile memory device100.

Step802includes fetching a read command. This is a command to read at some LBA (for some length), in one embodiment. Thus, a read command may be for some LBA range (wherein the range might include one or more LBAs). The data to be read may be stored in the memory structure126. Typically, the memory controller122translates the LBA to a PBA when the data is stored in the memory structure126. Note, however, that a copy of the data for at least some of the LBA range could be stored elsewhere than the memory structure126. For example, a copy of the data could be stored in HMB170. Note that although an example of LBAs is used, the logical addresses are not limited to blocks. In some cases, the data might be stored in the HMB170instead of in the memory structure126. For example, the memory controller122might not have written the data to the memory structure126yet. In other cases, there might be a copy of the data in both the memory structure126and the HMB170. Hence, in some cases, the memory controller122will not need to read from the memory structure126in order to provide data for at least some of the LBA range in the read command. The read command may be fetched from the command submission queue162. The command submission queue162is in host memory160, in one embodiment. The command submission queue162is in RAM122bon the non-volatile memory device100, in one embodiment. Step802is one embodiment of step402of process400.

Step804includes determining whether data needed to respond to the read command is already cached in host memory160. By “data needed to respond to the read command” it is meant data for at least one logical address (e.g., LBA) in the logical address range, in one embodiment. The data might be anywhere in host memory160. In some cases, the data could be in the HMB170. In one embodiment, the memory controller122examines the starting LBA in field344of the read command, as well as the length in field346(see, for example, the host command inFIG. 3A). The memory controller122may consult management tables256to determine whether the data for at least one of the LBAs is cached in HMB170. Note that the use of LBAs is just one way to manage addresses. The address in the read command need not be an LBA. Step804is one embodiment of step406of process400.

Step806is to select the data buffer pointers to the cached data as the replacement data buffer pointers.FIG. 8Bshows a portion of host memory160and a portion of memory on the non-volatile memory device that stores HMB pointers172to illustrate. The host memory160has data buffers168, and the HMB170. Also depicted are data buffer pointers166. Note that the HMB pointers172each point to a data buffer in the host memory160. Hence, an HMB pointer is an example of a data buffer pointer. Recall that the HMB170is a region of the host memory160that was allocated to the memory controller122for its exclusive use, in one embodiment. This allocation is made when the memory controller122was initialized, in one embodiment. The memory controller122may be initialized in response to a power on reset of the non-volatile memory device100. Step806is one embodiment of step408of process400.

FIG. 8Bshows the original data buffer pointers322a, which point to the original data buffers168a. In other words, at least a portion of the data for the read command is to be transferred by the memory controller122to original data buffers168a. For example, the data for a certain LBA range is to be transferred to original data buffers168a. The memory controller122has determined that the data for that LBA range is cached in the HMB170(cached data868). The cached data is pointed to by HMB pointers822a(which may be a set of the HMB pointers172on the non-volatile memory device100). Thus, the memory controller122determines that HMB pointers822amay be used as the replacement data buffer pointers.

Referring again toFIG. 8A, step808is to replace the original data buffer pointers with the data buffer pointers to the cached data in the host memory. In one embodiment, step808includes replacing the original pointers with HMB pointers822a. Step808is one embodiment of step410of process400.

Step810is to replace the data buffer pointers to the cached data with the original data buffer pointers.FIG. 8Cdepicts results after one embodiment of step810.FIG. 8Cshows reference numerals822aand322ain parenthesis to show how pointers fromFIG. 8Bmay be physically copied to new locations. The original data buffer pointers322ahave been replaced with replacement data buffer pointers322b. The replacement data buffer pointers322bpoint to the replacement data buffers168b. The replacement data buffers168bcontain the cached data. Thus, the replacement data buffers168binFIG. 8Care the same buffers as the cached data868inFIG. 8B.

FIG. 8Calso shows that the original HMB pointers822ahave been replaced with replacement HMB pointers822b. The replacement HMB pointers822bpoint to data buffers170a. Note that data buffers170amay now be considered to be a part of the HMB170. Thus, note that the HMB170now contains data buffers170a,170b, and170c. Moreover, note that data buffers170aare physically located outside of the region originally allocated to the memory controller122. In one embodiment, the host system140will treat the replacement HMB pointers822bas pointers to the HMB170. In other words, data buffers170a,170b, and170care now for the exclusive use of the memory controller122, in one embodiment. Thus, the location of the HMB170is dynamic, in one embodiment. However, note that the location of the HMB pointers172is static, in one embodiment.

Returning again to the discussion of step804inFIG. 8A, if data for the present read command is not cached in host memory, then step812may be performed. In step812, the original data buffer pointers are used. Note that for a given read command it is possible that step812will be performed for some data buffers, and steps806-810for other data buffers. Step812is one embodiment of step414of process400.

Note that process800may result in some fragmentation of the HMB170. Also, process800may be performed multiple times. In one embodiment, at some point there is a switch in ownership of the data buffers back to the original ownership. For example, at some point the data buffer pointers in HMB pointers172can be restored to the state inFIG. 8B, in which all of the data buffer pointers in HMB pointers172point to the HMB170inFIG. 8B(note that HMB170inFIG. 8Brefers to the region that was allocated to the memory controller122at initialization, in one embodiment). This switchover need not be done in an atomic way (e.g., the pointers in HMB pointers172do not all have to be replaced to the original pointer at the same time).

FIG. 9is a flowchart of one embodiment of a process900of replacing original data buffer pointers with replacement data buffer pointers in response to determining that there is an outstanding command having suitable replacement data buffer pointers. Process900may result in replacing original data buffers for a command (e.g., read command) with replacement data buffers for that command. Process900may be used in some of the steps of process400(e.g., steps402,406,408,410, and/or414).

Step902includes fetching a read command. This is a command to read at some logical address (e.g., LBA) for some length, in one embodiment. The data to be read may be stored in the memory structure126. Note, however, that a copy of the data for at least a portion of the LBA range could be stored elsewhere than the memory structure126. For example, a copy of the data could be cached in data cache266in non-volatile memory device100. In some cases, the data might be stored in the data cache266instead of in the memory structure126. For example, the memory controller122might not have written the data to the memory structure126yet. In other cases, there might be a copy of the data in both the memory structure126and the data cache266. Hence, in some cases, the memory controller122will not need to read from the memory structure126in order to provide the data for some portion of the LBA range. The read command may be fetched from the command submission queue162. The command submission queue162is in host memory160, in one embodiment. The command submission queue162is in RAM122bon the non-volatile memory device100, in one embodiment. Step902is one embodiment of step402of process400.

Step904includes determining whether data needed to respond to the read command is in data cache266. In one embodiment, the memory controller122examines the starting LBA in field344of the read command, as well as the length in field346(see, for example, the host command inFIG. 3A). The memory controller122may consult management tables256to determine whether the data for some portion of the LBA range is in data cache266.

Step906is a determination of whether there is an outstanding read command that can provide replacement data buffer pointers. In one embodiment, the memory controller122examines an internal command queue to determine whether there is a read command that is waiting to execute, but for which data buffer pointers have already been fetched. In one embodiment, waiting to execute means that the command executer228has not yet sent the read command to the memory interface230. For example, after the memory controller122fetches read commands from the command submission queue162, the memory controller may add the read commands to an internal queue. While the commands are on the internal queue, the memory controller122may fetch the data buffer pointers for the commands. Thus, there may be several read commands for which data buffer pointers have already been fetched, but that are waiting to execute. Together, steps904and906are one embodiment of step406of process400.

Step908includes the memory controller122selecting data buffer pointers for the outstanding read command as the replacement data buffer pointers. Note that the any subset of the data buffer pointers may be selected. Step908is one embodiment of step408of process400.

Step910includes replacing data buffer pointers for the present read command with the replacement data buffer pointers. A variety of replacement techniques could be used. Step910could include performing any combination of process500,600and/or700. Thus, step910may include, but is not limited to, replacing an original data buffer pointer322ain a host command320with a replacement data buffer pointer322b(see, for example,FIGS. 5B and 5C); replacing an original list pointer324a(which might or might not be in a host command320) with a replacement list pointer324b(see, for example,FIGS. 6B and 6C); and/or replacing an original data buffer pointer322ain a list304with a replacement data buffer pointer322b(see, for example,FIGS. 7B and 7C). Step910is one embodiment of step410of process400.

Step912includes populating the replacement data buffers with the cached data. Step910may include the DMA logic253performing a DMA from the data cache266to data buffers in the host memory160. The data buffers are those from the outstanding command that is waiting to execute. With respect to the embodiment ofFIGS. 5A-5C, step912may include populating replacement data buffer168binFIG. 5Cwith data from the data cache266. With respect to the embodiment ofFIGS. 6A-6C, step912may include populating replacement data buffers168binFIG. 6Cwith data from the data cache266. With respect to the embodiment ofFIGS. 7A-7C, step912may include populating replacement data buffers168binFIG. 7Cwith data from the data cache266. Step912is one embodiment of step412of process400.

Step914includes indicating to the host system140that the present read command is complete. In one embodiment, the memory controller122writes to the command completion queue164. The host may go to an entry in the command completion queue164for the present read command to determine the location of the data buffer pointers for the present read command. The host will be able to locate the replacement data buffer pointers, and thus be able to access the replacement data buffers.

Step916includes fetching the original data buffer pointers for the present read command. Note that step916may be performed at an earlier stage of process900. For example, step916might be performed any time after the present read command is fetched. The original data buffer pointers may be stored in storage251.

Step918includes using the original data buffer pointers for the command that provided the replacement data buffer pointers. For example, at some point, the command that was waiting to execute will be executed to return data from the memory structure126. The memory controller122may replace the data buffers pointers for that command with the original data buffer pointers from the command that was accessed in step902. The memory controller may populate the original data buffers with the data for the command that was waiting to execute. Thus, in effect, the memory controller122may swap data buffers for the two commands. However, note that it is not required that a swap of data buffers be performed. Rather, the original data buffers for the command in step902might be used for some other read command.

Returning again to step904, in some cases there will not be cached data for the present command. In this case, one option is to use the original data buffer pointers (in step920).

Returning again to step906, in some cases there will not be an outstanding command for replacement data buffer pointers. In this case, one option is to use the original data buffer pointers (in step920).

Recall that it is possible for there to be an offset to a data buffer. Referring toFIG. 3B, for example, the data buffer pointer322in the host command320could have a non-zero offset. This means that the first data buffer168(0) could, in effect, be smaller than the other data buffers168(1) to168(24). This may complicate data transfer between the host memory160and the non-volatile memory device100. For example, this may result data buffers in the non-volatile memory device100being unaligned with the data buffers168(0) to168(24).

FIG. 10is a flowchart of one embodiment of a process1000of replacing an original data buffer pointer with a replacement data buffer pointer in response a data buffer pointer in the host command320having a non-zero offset. Process1000may simply data transfer when a data buffer pointer in the host command320has a non-zero offset.FIG. 10provides further details of one embodiment of process400. Step1002includes fetching a host command320. Step1002is one embodiment of step402of process400.

Step1004is a determination of whether there is a data buffer offset in the host command320. With reference toFIG. 3Bas one example, the memory controller122determines whether offset323is non-zero. If not, then one option is to use the original data buffer pointers in step1012. Note that the original data buffer pointers still could be replaced by performing another process such as process800or process900. Step1004is one embodiment of step406of process400.

In the event that there is a non-zero offset, then control passes to step1006. Step1006includes selecting a data buffer pointer to replace the data buffer pointer322in the host command320. This data buffer pointer could be one of the HMB pointers172or be one of the other data buffer pointers166. The selection may include finding a data buffer having an alignment that matches buffer168(0). Step1006is one embodiment of step408of process400.

Step1008includes replacing the original data buffer pointer in the host command320with the replacement data buffer pointer.FIGS. 5B and 5Cdepict one example of such a replacement. Step1008is one embodiment of step410of process400.

Process1000may result in a more efficient transfer of data between the host system140and non-volatile memory device100. For example, process1000may result in aligned data transfers for data buffers168(1) to168(24), with reference to the example ofFIG. 3B. In other words, the data buffers in the non-volatile memory device100may be aligned with data buffers168(1) to168(24), which results in an efficient data transfer.

A first embodiment disclosed herein includes an apparatus comprising non-volatile memory; a communication interface configured to communicate with a host; and a memory controller coupled to the non-volatile memory and the communication interface. The memory controller is configured to control access by the host to the non-volatile memory via the communication interface. The memory controller is configured to access a read command. The read command is associated with an original data buffer pointer to an original data buffer in host memory of the host. The memory controller is configured to replace the original data buffer pointer with a replacement data buffer pointer to a replacement data buffer in the host memory. The memory controller is configured to populate the replacement data buffer with data. The memory controller is configured to indicate a command completion for the read command to the host after the original data buffer pointer has been replaced by the replacement data buffer pointer.

In a second embodiment, in furtherance of the first embodiment, the memory controller is further configured to replace the original data buffer pointer with the replacement data buffer pointer in response to a determination that the data in the replacement data buffer is data needed to respond to the read command.

In a third embodiment, in furtherance of the first embodiment, the memory controller is further configured to replace the original data buffer pointer with the replacement data buffer pointer in response to a determination that there is another read command waiting to be executed and for which the replacement data buffer pointer has already been obtained.

In a fourth embodiment, in furtherance of the first embodiment, the memory controller is configured to replace the original data buffer pointer with the replacement data buffer pointer in response to the original data buffer pointer having an offset.

In a fifth embodiment, in furtherance of any of the first to fourth embodiments, the memory controller is configured to replace the original data buffer pointer in the read command with the replacement data buffer pointer in response to the original data buffer pointer being in the read command.

In a sixth embodiment, in furtherance of any of the first to fourth embodiments, the memory controller is configured to replace at least the original data buffer pointer in a list pointed to by a list pointer the read command with the replacement data buffer pointer in response to the original data buffer pointer being in the list.

In a seventh embodiment, in furtherance of any of the first to fourth embodiments, the memory controller is configured to replace an original list pointer with a replacement list pointer to a replacement list of data buffer pointers in response to the original data buffer pointer being in an original list of data buffer pointers pointed to by the original list pointer.

In an eighth embodiment, in furtherance of any of the first to seventh embodiments, wherein to replace the original data buffer pointer with the replacement data buffer pointer the memory controller is configured to replace a copy of the original data buffer pointer that resides in the host memory with the replacement data buffer pointer.

In a ninth embodiment, in furtherance of any of the first to seventh embodiments, wherein to replace the original data buffer pointer with the replacement data buffer pointer the memory controller is configured to replace a copy of the original data buffer pointer that resides in memory on the memory controller side of the communication interface that is accessible to the host with the replacement data buffer pointer.

In a tenth embodiment, in furtherance of any of the first to ninth embodiments, the read command contains a logical address; the memory controller is configured to determine whether data for the logical address is cached in volatile memory; and the memory controller is configured to provide the cached data to respond to the read command when the data for the logical address is cached in the volatile memory.

One embodiment includes a method of operating a memory device having non-volatile memory. The method comprises accessing, by a memory controller that is configured to control access of a host to the non-volatile memory via a communication interface, a read command having a range of logical addresses. The read command is associated with a set of original data buffers in host memory in the host at which data for the range of logical addresses is to be stored by the memory controller. The method further includes determining to use one or more replacement data buffers in the host memory instead of a corresponding one or more of the original data buffers. The method further includes transferring data for at least one logical address from the memory device to the one or more replacement data buffers. The method further includes indicating, by the memory controller, that the data for the at least one logical address has been stored in the one or more replacement data buffers instead of the corresponding one or more original data buffers.

One embodiment includes a memory device, comprising: non-volatile memory; and communication means for receiving commands from a host to access the non-volatile memory. The memory device further comprises command access means for accessing a read command having a logical address and a length. The read command is associated with a range of logical addresses. The read command is associated with a set of original data buffer pointers to a set of original data buffers in host memory of the host at which data for the range of logical addresses is to be stored by the memory device. The memory device further comprises pointer management means for replacing at least one original data buffer pointer in the set of original data buffer pointers with a set of replacement data buffer pointers to a set of replacement data buffers in the host memory. The memory device further comprises data transfer means for performing a direct memory access to populate the set of replacement data buffers with data for at least one logical address in the range of logical addresses. The memory device further comprises command response means for indicating a command completion for the read command to the host after the pointer management means has replaced the at least one original data buffer pointer with the set of replacement data buffer pointers and after the data transfer means has performed the direct memory access.

In one embodiment, the command access means comprises one or more of front end module208, PHY222, processor122c, interface120, host queue manager246, an electrical circuit, an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and/or a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry (or one or more processors). However, the command access means could include other hardware and/or software.

In one embodiment, the pointer management means comprises one or more of host pointer manager250, processor122c, an electrical circuit, an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and/or a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry (or one or more processors). However, the pointer management means could include other hardware and/or software.

In one embodiment, the data transfer means comprises one or more of DMA logic253, processor122c, PHY222, interface120, host queue manager246an electrical circuit, an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and/or a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry (or one or more processors). However, the data transfer means could include other hardware and/or software.

In one embodiment, the command response means comprises one or more of host queue manager246, processor122c, PHY222, interface120, host queue manager246, an electrical circuit, an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and/or a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry (or one or more processors). However, the command response means could include other hardware and/or software.

One embodiment includes a memory device, comprising non-volatile memory; a communication interface configured to transfer data read from the non-volatile memory to requestor memory of a requestor; and one or more control circuits in communication with the non-volatile memory and the communication interface. The one or more control circuits are configured to access a read command that has a logical address and a length. The read command is associated with a range of logical addresses. The read command is associated with a set of original data buffer pointers to a set of original data buffers in the requestor memory at which data for the range of logical addresses is to be stored by the memory device. The one or more control circuits are further configured to replace at least one original data buffer pointer in the set of original data buffer pointers with a corresponding at least one replacement data buffer pointer to at least one replacement data buffer in the requestor memory. The one or more control circuits are further configured to transfer data for at least one logical address in the range of logical addresses to the at least one replacement data buffer. The one or more control circuits are further configured to instruct the requestor to use the at least one replacement data buffer pointer instead of the at least one original data buffer pointer to obtain the data for at least one logical address in the range.

Corresponding methods, systems and computer- or processor-readable storage devices which have executable code for performing the methods provided herein may also be provided.

For the purpose of this document, the numeric terms first (i.e., 1st) and second (i.e., 2nd) may be used to generally specify an order of when commands (e.g., write commands) are received by a memory controller from a host, as well as to generally specify an order in which data (e.g., 1stand 2nddata) is to be stored in non-volatile memory. However, it is noted that the term first (i.e., 1st) should not be interpreted as implying that nothing else precedes it.

For purposes of this document, the terms “based on” and “in dependence on” may be read as “based at least in part on.”

For purposes of this document, a “set” may include one or more elements.