Compensation circuit for generating read/program/erase voltage

A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0066044 filed on Jun. 8, 2018, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference herein in their entireties.

FIELD

Embodiments of the inventive concepts disclosed herein relate to electronic circuits, and more particularly, relate to electronic circuits included in a memory device.

BACKGROUND

As the development of information devices such as a computer, a mobile phone, and a smartphone progresses, large amounts of information may be stored in and processed by the information devices. Accordingly, memory devices of higher performance may be used as components of information devices. Since semiconductor memory may operate with a low power, the semiconductor memory may be used in a memory device.

Examples of semiconductor memory may include volatile memories and nonvolatile memories. Examples of volatile memories may include static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. Examples of nonvolatile memories may include flash memory, phase-change RAM (PRAM), magneto-resistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc.

A semiconductor memory may include a memory cell for storing data. Data stored in the memory cell may be read as a voltage of a specific magnitude is supplied to the memory cell. Characteristics of the memory cell may be affected by conditions such as a temperature. Accordingly, to accurately sense (read/program/erase) data stored in the memory cell, a magnitude of a supplied voltage having a magnitude that may be determined in consideration of the conditions having an influence on the memory cell.

SUMMARY

Some embodiments of the inventive concepts may provide an electronic circuit configured to generate a voltage for sensing data stored in a memory device.

According to some embodiments, a compensation circuit may be provided. The compensation circuit may include a reference current generating circuit, a compensation current generating circuit, a current mirror circuit, and an output transistor. The reference current generating circuit may include a first transistor of a first width configured to transfer a first current and may be configured to output a reference current based on the first current. The compensation current generating circuit may include a second transistor of a first width that is selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may be configured to output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The current mirror circuit may be configured to output a compensation voltage having a magnitude that is based on a magnitude of the second current. The output transistor may be configured to output a sensing voltage based on the compensation voltage. The code may have a first value, a second value, and a third value. A difference between the first value and the second value may be identical to a difference between the second value and the third value. A difference between a first magnitude of the voltage output based on the first value and a second magnitude of the voltage output based on the first value may correspond to a difference between the second magnitude and a third magnitude of the voltage output based on the third value.

According to some embodiments, a compensation circuit may be provided. The compensation circuit may include a reference current generating circuit configured to output a reference current of a fixed magnitude. The compensation circuit may include a compensation current generating circuit configured to output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on a code. The compensation circuit may include a current mirror circuit configured to output to the reference current generating circuit a first current based on the reference current, to output a second current based on the compensation current, and to output a compensation voltage based on the first current and the second current. The compensation circuit may include an output transistor configured to output a sensing voltage based on the compensation voltage. A magnitude of the sensing voltage may be associated with a magnitude of the second current such that the magnitude of the sensing voltage is a reference magnitude when the code is a reference value, and the magnitude of the second current is increased by the reference magnitude when a value of the code is increased by the reference value.

According to some embodiments, a voltage generating circuit may be provided. The voltage generating circuit may include a compensation circuit configured to output a compensation voltage having a magnitude that is based on a code, based on a first temperature dependent voltage, and based on a second temperature dependent voltage. The first voltage may have a magnitude which varies with a temperature and the second voltage may have a magnitude that is uniform regardless of the temperature. The voltage generating circuit may include an output transistor configured to output a sensing voltage having a magnitude that is based on a magnitude of the compensation voltage. The voltage generating circuit may be configured to produce the sensing voltage having a magnitude that is proportional to a value of the code, and is associated with a difference between a magnitude of the first temperature dependent voltage and a magnitude of the second temperature dependent voltage.

DETAILED DESCRIPTION

Some embodiments of the inventive concepts may be described in detail and clearly to such an extent to enable a person of ordinary skill in the art to easily implement the inventive concepts.

As used herein, the term “width” may refer to a width of a channel of a transistor. That is, the width may refer to a length of a direction (e.g., a vertical direction) crossing a direction in which charges transfer in the channel of the transistor. The transistor may be configured to have a width of a specific size.

As used herein, the term “code” may refer to data expressed in the form of a binary number. An n-bit code may be expressed by “n” successive logical values (logical value “1” or logical value “0”). For example, values of a 2-bit code may include “00”, “01”, “10”, and “11”.

As used herein, expressions “a level of a voltage is proportional to a value of a code” or “a level of a voltage varies linearly to a value of a code” may be used. That a level of a voltage is proportional to a value of a code or varies linearly to the value of the code may refer to a difference between the magnitude of a voltage corresponding to a value of a “q-th” code of “n” codes and the magnitude of a voltage corresponding to a “(q+1)-th” code being substantially identical to a difference between the magnitude of a voltage corresponding to a value of a “(q+1)-th” code and the magnitude of a voltage corresponding to a “(q+2)-th” code (q being a natural number).

For example, in embodiments where a difference between the magnitude of a voltage corresponding to a code value of “000” and the magnitude of a voltage corresponding to a code value of “001” is substantially identical to a difference between the magnitude of a voltage corresponding to a code value of “001” and the magnitude of a voltage corresponding to a code value of “010”, the magnitude of a voltage may be proportional to a code value in a range of a code value from “000” to “010”. Alternatively, the magnitude of a voltage may vary linearly to a code value in the range the code value from “000” to “010”. However, that two values are substantially identical to each other may include embodiments where two values are not completely identical to each other but only a slight difference is present between the two values, as well as embodiments where the two values are completely identical to each other.

FIG. 1is a circuit diagram illustrating a read voltage generating circuit according to some embodiments of the inventive concepts. A read voltage generating circuit1000configured to generate a read voltage Vreal used for reading data will be described with reference toFIG. 1, however, it may be understood that the read voltage generating circuit1000may generate not only read voltage Vread1but, in some embodiments, also other voltages for various purposes. For example, the read voltage generating circuit1000may generate a voltage for sensing (reading, programming, erasing etc.) data.

Referring toFIG. 1, the read voltage generating circuit1000may include a compensation circuit1100, a transistor TR0, a resistor R1, and a resistor R2.

The compensation circuit1100may receive codes TC1and TC2, voltages Vztc, Vntc, Vpwr, and Vss, a reference voltage Vref, and a feedback voltage Vfb. For example, as will be described with reference toFIG. 16, the compensation circuit1100may be a component of a memory device included in a memory system. The memory system may include a logic circuit for generating the codes TC1and TC2. For example, the logic circuit may be included in a component such as a memory controller. The compensation circuit1100may receive the codes TC1and TC2from the logic circuit.

For example, the memory system may include a voltage generator. The voltage generator may generate the voltages Vztc, Vntc, and Vpwr and the reference voltage Vref, which may be used to operate the read voltage generating circuit1000. The compensation circuit1100may receive the voltages Vztc, Vntc, and Vpwr and the reference voltage Vref from the voltage generator. The compensation circuit1100may be electrically connected to a node between the resistor R1and the resistor R2. The compensation circuit1100may receive the feedback voltage Vfb from the node between the resistor R1and the resistor R2. The voltage Vss may be a voltage of an equipotential terminal. For example, the voltage Vss may be a ground voltage.

The compensation circuit1100may output a voltage Vout1based on the codes TC1and TC2and the voltages Vztc, Vntc, Vref, Vpwr, and Vss. The compensation circuit1100may output the voltage Vout1to a gate terminal of the transistor TR0. A configuration and an operation of the compensation circuit1100will be described with reference toFIGS. 2 and 3.

The transistor TR0may include a gate terminal receiving the voltage Vout1from the compensation circuit1100. The transistor TR0may include a first end receiving the voltage Vpwr. A second end of the transistor TR0may be electrically connected to a first end of the resistor R1. A read voltage Vread1may be output from a node between the transistor TR0and the first end of the resistor R1. A second end of the resistor R1may be electrically connected to a first end of the resistor R2. A second end of the resistor R2may be electrically connected to the equipotential terminal supplying the voltage Vss.

As the voltage Vout1is applied to the gate terminal of the transistor TR0, a current may flow through the transistor TR0. As the current flows through the transistor TR0, the read voltage Vread1may be formed at the node between the transistor TR0and the resistor R1. The magnitude of the voltage Vread1may be associated with the magnitude of the voltage Vout1. The read voltage generating circuit1000may output the read voltage Vread1to another component of the memory system (e.g., a memory cell in a memory device). The memory device may output a data signal indicating data stored in a memory cell, based on the read voltage Vread1(refer toFIG. 16).

The voltage Vread1may be divided by the resistor R1and the resistor R2. In embodiments where the magnitude of the voltage Vss is “Vss”, the magnitude of the voltage Vread1is “Vread1”, the magnitude of the resistor R1is “R1”, and the magnitude of the resistor R2is “R2”, the magnitude of the feedback voltage Vfb may be expressed by the equation “(Vread1−Vss)*R2/(R1+R2)”. In embodiments where the magnitude of the feedback voltage Vfb is “Vfb” and the magnitude of the voltage Vss is “0”, the magnitude of the voltage Vread1may be expressed by the equation “(1+(R1/R2))*Vfb”. Accordingly, the magnitude of the feedback voltage Vfb may be associated with the magnitude of the voltage Vread1and the magnitude of the feedback voltage Vfb may be associated with the magnitude of the voltage Vout1.

Each of the codes TC1and TC2may be expressed as being composed of “n” bits (n being a natural number). In some embodiments, the codes TC1and TC2may have values complementary to each other. For example, when a value of the code TC1is “000000”, a value of the code TC2may be “111111”. The code TC1may include a least significant bit TC1<0> to a most significant bit TC1<n−1>. The code TC2may include a least significant bit TC2<0> to a most significant bit TC2<n−1>. For example, in embodiments where the code TC1and the code TC2are each a 6-bit code, the code TC1and the code TC2may have one of values from “000000” to “111111” and a complementary one of the values from “000000” to “111111”, respectively.

The logic circuit may generate the codes TC1and TC2based on various conditions associated with the memory device of the memory system. The memory device may supply a read voltage of a specific magnitude for the purpose of reading data stored in a memory cell. The magnitude of a threshold voltage of the memory cell may vary with various conditions (e.g., a temperature and a stress etc.). Accordingly, the magnitude of the read voltage useful to accurately read data may also vary with the various conditions. As used herein, a temperature may refer to a temperature of the memory system including the read voltage generating circuit1000.

For example, the magnitude of the threshold voltage of the memory cell may increase as a temperature decreases. The read voltage of an increased magnitude may be used to accurately read data stored in the memory cell having the threshold voltage of the increased magnitude. The logic circuit may track the threshold voltage of the memory cell. The logic circuit may determine the magnitude of the read voltage useful to accurately read data stored in the memory cell, based on the tracked threshold voltage. The logic circuit may determine the magnitude of the voltage Vout1, based on a relationship between the read voltage Vread1and the voltage Vout1. The logic circuit may determine the codes TC1and TC2such that the read voltage Vread1having the determined magnitude is output from the read voltage generating circuit1000.

One or more of the magnitudes of the voltages Vztc and/or Vntc may be associated with a temperature. For example, the magnitude of the voltage Vztc may be uniform regardless of a change in temperature. The magnitude of the voltage Vntc may decrease as a temperature increases. In the specification, for convenience of description, an ideal embodiment may be described with regard to the voltage Vztc having the uniform magnitude regardless of a change of a temperature and the voltage Vntc having a magnitude proportional to a temperature. However, in some embodiments, the actual magnitudes of the voltages Vztc and Vntc may be slightly different from the magnitudes of the voltages Vztc and Vntc of the ideal embodiment. A relationship between the voltages Vztc and Vntc and a temperature will be described with reference toFIG. 12.

FIG. 2is a block diagram illustrating an example configuration of the compensation circuit ofFIG. 1according to some embodiments of the inventive concepts.

Referring toFIG. 2, the compensation circuit1100may include a current mirror circuit1110, a reference current generating circuit1120, and a compensation current generating circuit1130. The current mirror circuit1110may receive the voltage Vpwr. The current mirror circuit1110may output the voltage Vout1to the gate terminal of the transistor TR0ofFIG. 1. The current mirror circuit1110may be electrically connected to the reference voltage generating circuit1120. The current mirror circuit1110may be electrically connected to the compensation current generating circuit1130.

The reference current generating circuit1120may receive the reference voltage Vref, the feedback voltage Vfb, and the code TC1. The compensation current generating circuit1130may receive the voltage Vztc, the voltage Vntc, and the code TC2. The reference current generating circuit1120and the compensation current generating circuit1130may be electrically connected to the equipotential terminal supplying the voltage Vss.

The reference current generating circuit1120may generate a reference current Iref1based on the received reference voltage Vref, the received feedback voltage Vfb, and the received code TC1. The reference current generating circuit1120may output the reference current Iref1to the equipotential terminal. The compensation current generating circuit1130may generate a compensation current ITC1based on the received voltage Vztc, the received voltage Vntc, and the received code TC2. The compensation current generating circuit1130may output the compensation current ITC1to the equipotential terminal.

As the reference current Iref1is generated by the reference current generating circuit1120, the reference current generating circuit1120may receive a current I1from the current mirror circuit1110. As the compensation current ITC1is generated by the compensation current generating circuit1130, the compensation current generating circuit1130may receive a current I2from the current mirror circuit1110. As the current I1and the current I2are output from the current mirror circuit1110, the voltage Vout1may be formed in the current mirror circuit1110. The current mirror circuit1110may output the voltage Vout1to the transistor TR0ofFIG. 1.

The current mirror circuit1110may be a first stage amplifier configured to output the voltage Vout1. The transistor TR0may be a second stage amplifier configured to output the read voltage Vread1.

The magnitude of the voltage Vout1may be associated with a temperature. Also, the magnitude of the voltage Vout1may be associated with the code TC1and the code TC2. Accordingly, the magnitude of the read voltage Vread1may be associated with the temperature and the codes TC1and TC2. Hereinafter, operations of the current mirror circuit1110, the reference current generating circuit1120, and the compensation current generating circuit1130will be described with reference toFIG. 3.

FIG. 3is a circuit diagram illustrating an example configuration of the compensation circuit ofFIG. 1according to some embodiments of the inventive concepts.

Referring toFIG. 3, the current mirror circuit1110may include a transistor TR1and a transistor TR2. The reference current generating circuit1120may include a transistor TR3, a transistor TR4, and a current source CS1. The compensation current generating circuit1130may include a transistor TR5, a transistor TR6, and a current source CS2.

The transistor TR1may include a first end receiving the voltage Vpwr. A second end of the transistor TR1may be electrically connected to a node N1. The transistor TR2may include a first end receiving the voltage Vpwr. A gate terminal of the transistor TR1may be electrically connected to a gate terminal of the transistor TR2, a second end of the transistor TR2, and a node N2.

The transistor TR3may include a gate terminal receiving the reference voltage Vref. A first end of the transistor TR3may be electrically connected to the node N1. A second end of the transistor TR3may be electrically connected to the current source CS1. The transistor TR4may include a gate terminal receiving the feedback voltage Vfb. A first end of the transistor TR4may be electrically connected to the node N2. A second end of the transistor TR4may be electrically connected to the current source CS1. The current source CS1may be electrically connected to the equipotential terminal supplying the voltage Vss.

The transistor TR5may include a gate terminal receiving the voltage Vntc. A first end of the transistor TR5may be electrically connected to the node N1. A second end of the transistor TR5may be electrically connected to the current source CS2. The transistor TR6may include a gate terminal receiving the voltage Vztc. A first end of the transistor TR6may be electrically connected to the node N2. A second end of the transistor TR6may be electrically connected to the current source CS2. The current source CS2may be electrically connected to the equipotential terminal supplying the voltage Vss.

The current source CS1may output the reference current Iref1having a variable. The current source CS1may control the magnitude of the reference current Iref1based on the code TC1. For example, the current source CS1may control the magnitude of the reference current Iref1to be negatively proportional to a value of the code TC1. A sum of the magnitude of a current I11flowing through the transistor TR3and the magnitude of a current I12flowing through the transistor TR4may correspond to the magnitude of the reference current Iref1.

The current source CS2may output the compensation current ITC1having a variable. For example, the current source CS2may control the magnitude of the compensation current ITC1based on the code TC2. For example, the current source CS2may control the magnitude of the compensation current ITC1to be positively proportional to a value of the code TC2. A sum of the magnitude of a current I21flowing through the transistor TR5and the magnitude of a current I22flowing through the transistor TR6may correspond to the magnitude of the compensation current ITC1.

The magnitude of the current I11flowing through the transistor TR3and the magnitude of the current I12flowing through the transistor TR4may vary as the magnitude of the reference current Iref1varies. The magnitude of the current I21flowing through the transistor TR5and the magnitude of the current I22flowing through the transistor TR6may vary as the magnitude of the compensation current ITC1varies. As the magnitude of the current I1flowing through the transistor TR3and the magnitude of the current I21flowing through the transistor TR5vary, the magnitude of a current ID1flowing through the transistor TR1may vary. As the magnitude of the current I12flowing through the transistor TR4and the magnitude of the current I22flowing through the transistor TR6vary, the magnitude of a current ID2flowing through the transistor TR2may vary.

Referring together toFIGS. 2 and 3, the magnitude of the current I1ofFIG. 2may correspond to a sum of the magnitude of the current I11and the magnitude of the current I12. The magnitude of the current I2ofFIG. 2may correspond to a sum of the magnitude of the current I21and the magnitude of the current I22. As the current I11and the current I2flow, the voltage Vout1may be formed at the node N1. As described with reference toFIG. 1, the feedback voltage Vfb may be formed at the node between the resistor R1and resistor R2, and the read voltage Vread1may be output from the read voltage generating circuit1000. The magnitude of the feedback voltage Vfb may be expressed by Equation 1.
Vfb=Vref+α*(Vntc−Vztc)  [Equation 1]

In Equation 1, “Vfb” may represent the magnitude of the feedback voltage Vfb, “Vref” may represent the magnitude of the reference voltage Vref, “Vntc” may represent the magnitude of the voltage Vntc, and “Vztc” may represent the magnitude of the voltage Vztc. “α” in Equation 1 may be expressed by Equation 2.

In Equation 2, “W_4” may represent a width of the transistor TR4, “I12” may represent the magnitude of the current I12, “W_5” may represent a width of the transistor TR5, “I21” may represent the magnitude of the current I21, “k” may be a proportional constant which is independent of a temperature, a value of the code TC1, and a value of the code TC2.

The current source CS1may be configured to output the reference current Iref1having a magnitude that is negatively proportional to a value of the code TC1. The current source CS2may be configured to output the compensation current ITC1having a magnitude that is positively proportional to a value of the code TC2. The magnitude of the current I12and the magnitude of the current I21may vary with the magnitudes of the reference current Iref1and the compensation current ITC1. As such, “α” may vary depending on Equation 2, and the magnitude of the feedback voltage Vfb may vary depending on Equation 1.

As described with reference withFIG. 1, the magnitude of the read voltage Vread1may correspond to the magnitude of the feedback voltage Vfb. Accordingly, the magnitude of the read voltage Vread1may vary based on Equation 1. Hereinafter, the read voltage Vread1may be described with reference to Equation 1 and Equation 2.

The read voltage generating circuit1000may be configured to output the read voltage Vread1having a magnitude that varies with a value of the code TC1and a value of the code TC2. For example, the read voltage generating circuit1000may be configured to output the read voltage Vread1having a magnitude that becomes greater as a value of the code TC1and a value of the code TC2vary.

As described with reference toFIG. 1, the magnitude of the voltage Vntc and/or the magnitude of the voltage Vztc may be associated with a temperature. For example, the magnitude of the voltage Vntc may be negatively proportional to a temperature, and the magnitude of the voltage Vztc may be uniform regardless of a change in temperature. Accordingly, the read voltage generating circuit1000may be configured to output the read voltage Vread1having a magnitude associated with a temperature. For example, the read voltage generating circuit1000may be configured to output the read voltage Vread1having a magnitude that becomes smaller as a temperature increases.

As the magnitude of the read voltage Vread1varies with a temperature and the codes TC1and TC2, the magnitude of the read voltage Vread1may vary with the threshold voltage of the memory cell, which varies with various conditions.

FIG. 4is a circuit diagram illustrating a read voltage generating circuit according to some embodiments of the inventive concepts. Compared toFIG. 1, a read voltage generating circuit2000ofFIG. 4may include a compensation circuit2100instead of the compensation circuit1100. Some elements of the read voltage generating circuit2000ofFIG. 4may be the same as or similar to corresponding elements of the read voltage generating circuit1000described with respect toFIGS. 1 to 3and redundant descriptions may be omitted for brevity.

The compensation circuit2100may receive one code TC from the logic circuit. The code TC may be expressed as being composed of “n” bits (n being a natural number). The code TC may include a least significant bit TC<0> to a most significant bit TC<n−1>. For example, in embodiments where the code TC is a 6-bit code, the code TC may have one of values from “000000” to “111111”.

For example, a logic circuit may generate the code TC based on various conditions associated with the memory system. A configuration and operations of the read voltage generating circuit2000may be similar to the configuration and the operations of the read voltage generating circuit1000. Thus, additional description may be omitted to avoid redundancy.

FIG. 5is a block diagram illustrating an example configuration of the compensation circuit ofFIG. 4according to some embodiments of the inventive concepts.

Referring toFIG. 5, the compensation circuit2100may include a current mirror circuit2110, a reference current generating circuit2120, and a compensation current generating circuit2130. The current mirror circuit2110may receive the voltage Vpwr. The current mirror circuit2110may output a voltage Vout2to the gate terminal of the transistor TR0ofFIG. 4. The current mirror circuit2110may be electrically connected to the reference current generating circuit2120and the compensation current generating circuit2130.

The reference current generating circuit2120may receive the reference voltage Vref and the feedback voltage Vfb. The compensation current generating circuit2130may receive the voltage Vztc, the voltage Vntc, and the code TC. The reference current generating circuit2120and the compensation current generating circuit2130may be electrically connected to the equipotential terminal supplying the voltage Vss.

The reference current generating circuit2120may generate a reference current Iref2, based on the received reference voltage Vref and the received feedback voltage Vfb. The reference current generating circuit2120may output the reference current Iref2to the equipotential terminal. The compensation current generating circuit2130may generate a compensation current ITC2, based on the received voltage Vztc, the received voltage Vntc, and the received code TC. The compensation current generating circuit2130may output the compensation current ITC2to the equipotential terminal.

As the reference current Iref2is generated by the reference current generating circuit2120, the reference current generating circuit2120may receive a current I3from the current mirror circuit2110. As the compensation current ITC2is generated by the compensation current generating circuit2130, the compensation current generating circuit2130may receive a current I4from the current mirror circuit2110. As the current I3and the current I4are output from the current mirror circuit2110, the current mirror circuit2110may output the voltage Vout2to the transistor TR0ofFIG. 4.

Some operations of the current mirror circuit2110, the reference current generating circuit2120, and the compensation current generating circuit2130will be described with reference toFIG. 6.

FIG. 6is a circuit diagram illustrating an example configuration of the compensation circuit ofFIG. 4according to some embodiments of the inventive concepts.

The compensation circuit2100ofFIG. 4may include a compensation circuit2100aofFIG. 6. The compensation current generating circuit2130ofFIG. 5may include a compensation current generating circuit2131ofFIG. 6. Referring toFIG. 6, the current mirror circuit2110may include a transistor TR1and a transistor TR2. The reference current generating circuit2120may include a transistor TR7, a transistor TR8, and a current source CS3. The compensation current generating circuit2131may include a transistor TR9, a transistor TR10, and a current source CS4.

The transistor TR1may include a first end receiving the voltage Vpwr. A second end of the transistor TR1may be electrically connected to a node N3. The transistor TR2may include a first end receiving the voltage Vpwr. A gate terminal of the transistor TR1may be electrically connected to a gate terminal of the transistor TR2, a second end of the transistor TR2, and a node N4. The transistor TR1may transfer the current ID3. The transistor TR2may transfer the current ID4.

The transistor TR7may include a gate terminal receiving the reference voltage Vref. A first end of the transistor TR7may be electrically connected to the node N3. A second end of the transistor TR7may be electrically connected to a first end of the current source CS3. The transistor TR7may transfer a current I31. The transistor TR8may include a gate terminal receiving the feedback voltage Vfb. A first end of the transistor TR8may be electrically connected to the node N4. A second end of the transistor TR8may be electrically connected to the first end of the current source CS3. The transistor TR8may transfer a current I32. A second end of the current source CS3may be electrically connected to the equipotential terminal supplying the voltage Vss.

The transistor TR9may include a gate terminal receiving the voltage Vntc. A first end of the transistor TR9may be electrically connected to the node N3. A second end of the transistor TR9may be electrically connected to a first end of the current source CS4. The transistor TR9may transfer a current I41. The transistor TR10may include a gate terminal receiving the voltage Vztc. A first end of the transistor TR10may be electrically connected to the node N4. A second end of the transistor TR01may be electrically connected to the first end of the current source CS4. The transistor TR10may transfer a current I42. A second end of the current source CS4may be electrically connected to the equipotential terminal supplying the voltage Vss.

InFIG. 6, each of the transistor TR9and the transistor TR10is illustrated as being implemented with one transistor. However, as illustrated for example inFIG. 8, each of the transistor TR9and the transistor TR10may be one or more transistors that are selected based on the code TC, from among a plurality of transistors. Transistors which may be selected as the transistor TR9and the transistor TR10may have different widths. Accordingly, a width of the transistor TR9and a width of the transistor TR01may be selected according to the code TC.

The current source CS3may output the reference current Iref2. A sum of the magnitude of the current I31flowing through the transistor TR7and the magnitude of the current I32flowing through the transistor TR8may correspond to the magnitude of the reference current Iref2. In embodiments where characteristics of the transistor TR7and the transistor TR8are substantially identical to each other, the magnitude of the current I31may be substantially identical to the magnitude of the current I32.

For better understanding, in the specification, embodiments in which the magnitude of the current I31is substantially identical to the magnitude of the current I32may be described. However, it may be understood that the inventive concepts may include some embodiments in which the currents I31and I32have different magnitudes depending on the magnitude of the reference voltage Vref, the magnitude of the feedback voltage Vfb, and characteristics of the transistors TR7and TR8.

The current source CS4may output the compensation current ITC2having a magnitude that is selected by the code TC2. A sum of the magnitude of the current I41flowing through the transistor TR9and the magnitude of the current I42flowing through the transistor TR10may correspond to the magnitude of the compensation current ITC2. In embodiments where characteristics of the transistor TR9and the transistor TR10are substantially identical to each other, the magnitude of the current I41may be substantially identical to the magnitude of the current I42. The magnitude of the compensation current ITC2may be selected based on the code TC. Accordingly, the magnitude of the compensation current I41may be selected based on the code TC.

For better understanding, in the specification, embodiments in which the magnitude of the current I41is substantially identical to the magnitude of the current I42may be described. However, it may be understood that the inventive concepts may include some embodiments in which the currents I41and I42have different magnitudes depending on the magnitude of the voltage Vntc, the magnitude of the voltage Vztc, and characteristics of transistors (TR9and TR10) selected by the code TC.

The reference current generating circuit1120ofFIG. 3may output the reference current Iref1having a magnitude that varies with the code TC1and a temperature, but the reference current generating circuit2120ofFIG. 6may output the reference current Iref2of a fixed value. The compensation circuit2100amay adjust the magnitude of the voltage Vout2depending primarily on an operation of the compensation current generating circuit2131, which varies due to the code TC and a temperature.

Referring together toFIGS. 5 and 6, the magnitude of the current I3ofFIG. 5may correspond to a sum of the magnitude of the current I31and the magnitude of the current I32. The magnitude of the current I4ofFIG. 5may correspond to a sum of the magnitude of the current I41and the magnitude of the current I42. As the current I3and the current I4flow, the voltage Vout2may be formed at the node N3. As described with reference toFIG. 4, the feedback voltage Vfb may be formed at the node between the resistor R1and resistor R2, and the read voltage Vread2may be output from the read voltage generating circuit2000. The magnitude of the feedback voltage Vfb may be expressed by Equation 3.
Vfb=Vref+α*(Vntc−Vztc)  [Equation 3]

In Equation 3, “Vfb” may represent the magnitude of the feedback voltage Vfb, “Vref” may represent the magnitude of the reference voltage Vref, “Vntc” may represent the magnitude of the voltage Vntc, and “Vztc” may represent the magnitude of the voltage Vztc. As described with reference toFIG. 1, the magnitude of the voltage Vntc and/or the magnitude of the voltage Vztc may be associated with a temperature. For example, the magnitude of the voltage Vntc may be configured to have a value proportional to a temperature, and the magnitude of the voltage Vztc may be configured to have a uniform value regardless of a change in temperature. The magnitude “Vfb” of the feedback voltage Vfb may be determined based on a difference between the magnitude of the voltage Vntc and the magnitude of the voltage Vztc. “α” in Equation 3 may be expressed by Equation 4.

In Equation 4, “W_8” may represent a width of the transistor TR8, “I32” may represent the magnitude of the current I32, “W_9” may represent a width of the transistor TR9, “I41” may represent the magnitude of the current I41, “k” may be a proportional constant which is independent of a temperature and a value of the code TC.

Referring to Equation 3 and Equation 4, the magnitude of the feedback voltage Vfb may include a non-linear term with respect to both the code TC and temperature caused by “α”. That is, due to the term

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
included in “α”, the magnitude of the feedback voltage Vfb may include a value which non-linearly varies with a temperature and a value of the code TC.

In detail, since the currents I41and I32are drain currents of the transistors TR9and TR8, respectively, the magnitude of the current I41and the magnitude of the current I32may vary with a temperature. According to the relation described with reference to Equation 3 and Equation 4, a rate of change in feedback voltage Vfb to a temperature

“δ⁢⁢Vfbδ⁢⁢T”
may be calculated as

“C*(δδ⁢⁢T)⁢(Vgs⁢⁢9-VtVgs⁢⁢8-Vt)+α*δδ⁢⁢T⁢(Vnct-Vztc)”.
“Vntc−Vztc” may be linear with regard to temperature but

“(Vgs⁢⁢9-VtVgs⁢⁢8-Vt)”
may not be linear with regard to temperature.

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
corresponds to the square root of a value that may vary with a temperature,

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
may be a non-linear term for a change in temperature. Accordingly, the magnitude of the feedback voltage Vfb that is calculated according to Equation 3 and Equation 4 may include a non-linear term for a change in temperature.

Also, as described with reference to the transistors TR9and TR10, “W_9” and “I41” may vary with a value of the code TC. Since the

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
term is the square root of a value that may vary with a value of the code TC,

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
may be a non-linear term for a value of the code TC. Accordingly, the magnitude of the feedback voltage Vfb that is calculated according to Equation 3 and Equation 4 may include a non-linear term with regard to a value of the code TC.

As described with reference withFIG. 4, the magnitude of the read voltage Vread2may correspond to the magnitude of the feedback voltage Vfb. Accordingly, the magnitude of the read voltage Vread2may vary based on Equation 3. Hereinafter, the read voltage Vread2may be described with reference to Equation 3 and Equation 4.

In embodiments where the magnitude of the feedback voltage Vfb is non-linear to a temperature and a value of the code TC, the computational burden of the logic circuit may be increased to calculate the read voltage Vread2having a magnitude that is useful to accurately read data of a memory cell. A logic circuit that is configured to process a lot of operations may consume a lot of power. Also, the logic circuit that is configured to process a lot of operations may be implemented with a chip which is placed in a wide area.

According to the inventive concepts, “W_9” and “I41” may be varied with the code TC in an operation of the compensation circuit2100asuch that the magnitude of the feedback voltage Vfb calculated according to Equation 3 and Equation 4 does not include a non-linear term with regard to a change in temperature and a value of the code TC (e.g.,

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
may have a value independent of a temperature and a value of the code TC). For example, “W_9” and “I41” may be set to multiples of “W_8” and “I32” respectively, thereby improving a linearity of temperature compensation.

Examples of “W_9” and “I41” that are variously selected according to the code TC will be described with reference toFIGS. 8 to 11.

FIG. 7is a circuit diagram illustrating an example configuration of the compensation circuit ofFIG. 4according to some embodiments of the inventive concepts.

The compensation circuit2100ofFIG. 4may include a compensation circuit2100bofFIG. 7. Compared with the compensation circuit2100aofFIG. 6, the compensation circuit2100bofFIG. 7may further include a direction selecting circuit2132. Some elements of the read compensation circuit2100bofFIG. 7may be the same as or similar to corresponding elements of the compensation circuit2100aofFIG. 6described with respect toFIG. 6and redundant descriptions may be omitted for brevity.

The direction selecting circuit2132may receive the voltage Vztc and the voltage Vntc. The direction selecting circuit2132may receive a selection signal SEL from the logic circuit. The direction selecting circuit2132may output a voltage Va and a voltage Vb in response to the selection signal SEL. The direction selecting circuit2132may output the voltage Va to the gate terminal of the transistor TR9. The direction selecting circuit2132may output the voltage Vb to the gate terminal of the transistor TR10.

The direction selecting circuit2132may output the voltage Va and the voltage Vb, each of which selectively has one of values corresponding to the voltage Vztc and the voltage Vntc based on a logical value of the selection signal SEL. For example, in some embodiments when the selection signal SEL indicates a logical value of “1”, the voltage Va may correspond to the voltage Vztc, and the voltage Vb may correspond to the voltage Vntc and when the selection signal SEL indicates a logical value of “0”, the voltage Va may correspond to the voltage Vntc, and the voltage Vb may correspond to the voltage Vztc. However, embodiments of the inventive concepts are not limited thereto.

Below, for convenience of description, embodiments in which, in response to the selection signal SEL having a logical value of “1”, the voltage Vztc is applied to the gate terminal of the transistor TR9(i.e., the voltage Vztc is selected as the voltage Va) and the voltage Vntc is applied to the gate terminal of the transistor TR10(i.e., the voltage Vntc is selected as the voltage Vb) and in which, in response to the selection signal SEL having a logical value of “0”, the voltage Vntc is applied to the gate terminal of the transistor TR9(i.e., the voltage Vntc is selected as the voltage Va) and the voltage Vztc is applied to the gate terminal of the transistor TR10(i.e., the voltage Vztc is selected as the voltage Vb) will be described.

However, it may be understood that the inventive concepts may include other embodiments in which, in response to any logical value of the selection signal SEL, one of a voltage having a magnitude corresponding to the magnitude of the voltage Vntc and a voltage having a magnitude corresponding to the magnitude of the voltage Vztc is applied to the gate terminal of the transistor TR9, and the other thereof is applied to the gate terminal of the transistor TR10.

As the magnitude of the voltage Vout2may vary as the voltage Va and the voltage Vb are selected by the selection signal SEL, and magnitudes of the feedback voltage Vfb and the read voltage Vread2may vary as the voltage Va and the voltage Vb are selected by the selection signal SEL. A relationship between the selection signal SEL and the read voltage Vread2will be described with reference toFIG. 13.

FIG. 8is a circuit diagram illustrating an example configuration of the compensation current generating circuit ofFIGS. 6 and/or 7according to some embodiments of the inventive concepts.FIG. 8illustrates a transistor TR9receiving a voltage Va and a transistor TR10receiving a voltage Vb (an example corresponding toFIG. 7). For example, the transistor TR9may receive a voltage Vntc and the transistor TR10may receive a voltage Vztc in response to “0” of a selection signal SEL.

Referring toFIG. 8, the transistor TR9ofFIGS. 6 and/or 7may be at least one enabled transistor selected from a plurality of transistors (transistors of a group corresponding to a reference numeral “TR9”). The transistor TR10ofFIGS. 6 and/or 7may be at least one enabled transistor selected from a plurality of transistors (transistors of a group corresponding to a reference numeral “TR10”). For example, the transistor TR9may be an enabled one or more of transistors TR9_1to TR9_4, transistors of a group G1, and transistors of a group G2. The transistor TR10may be an enabled one or more of transistors TR10_1to TR10_4, transistors of a group G3, and transistors of a group G4.

Widths of transistors which may be selected as the transistor TR9may be different. For example, a width of the transistor TR9_1may be “8 W”, a width of the transistor TR9_2may be “4 W”, a width of the transistor TR9_3may be “2 W”, and a width of the transistor TR9_4may be “W”. A width of each of the transistors in the groups G1and G2may be “W”. In other words, the width of the transistor TR9_1may be about eight times the width “W”, the width of the transistor TR9_2may be about four times the width “W”, and the width of the transistor TR9_3may be about two times the width “W”. In embodiments where the serially connected transistors of the group G1are selected together, the transistors of the group G1may operate together. In embodiments where the serially connected transistors of the group G2are selected together, the transistors of the group G2may operate together.

In embodiments where transistors are serially connected, a length of a channel through which a current flows may increase, and thus, a ratio of a channel width to a channel length may decrease. Accordingly, the serially connected transistors may operate like a transistor, the width of which is narrower than a width of each transistor. For example, the serially connected transistors may operate like a transistor, the width of which is inversely proportional to the number of serially connected transistors. Accordingly, in embodiments where the serially connected transistors of the group G1operate together, an operation of two transistors in the group G1may be similar to an operation of a transistor having a width of “(½)*W”, or about half of the width “W”. As in the above description, an operation of four transistors in the group G2may be similar to an operation of a transistor having a width of “(¼)*W”, or about one fourth of the width “W”.

In the embodiments ofFIG. 8, transistors which may be selected for the transistor TR9may operate as transistors having widths of “(¼)*W”, “(½)*W”, “W”, “2 W”, “4 W”, and “8 W”. That is, transistors which may be selected for the transistor TR9may operate as transistors having widths of “(2i)*W” (i being an integer −2≥i≥3). In embodiments where each of the transistors TR7and TR8of the current source CS3have a width “W”, widths of transistors which may be selected as the transistor TR9may be proportional to widths of the transistors TR7and TR8, respectively. While some embodiments with values of I within a range of “−2≤i≤3” may be described with reference toFIG. 8, it is understood that the inventive concepts may include embodiments for other ranges for the integer “i”.

Accordingly, one of various values may be selected as a width “W_9” of the transistor TR9in Equation 4. In embodiments where a width “W_8” of the transistor TR8is “W”, values which may be selected as “W_9” may be proportional to “W_8”. The transistor TR9may be configured such that values proportional to “W_8” may be selected as “W_9”. The transistor TR10may have a configuration which is similar to the configuration of the transistor TR9. Thus, additional description will be omitted to avoid redundancy.

In the embodiments ofFIG. 8, the code TC may be expressed by 6-bit data (i.e., each of TC<0> to TC<5> may be expressed by 1-bit data). TC<0> to TC<5> may respectively indicate values of “20” to “25” positions of the 6-bit data. For example, in some embodiments, when the code TC is expressed by “100010”, “TC<1>” and “TC<5>” may be “1”, “TC<0>”, “TC<2>”, “TC<3>”, and “TC<4>” may be “0”.

Referring toFIG. 8, the current source CS4may include a switch unit SW. The switch unit SW may include switches SW1to SW6. The switches SW1to SW6may receive corresponding bits of the code TC including TC<5> to TC<0>. Each of TC<0> to TC<5> may be a logical value of “0” or a logical value of “1”. Each of the switches SW1to SW6may be turned on in response to a logical value of “1” and may be turned off in response to a logical value of “0” of a corresponding bit of the code TC. For example, the logical value of “1” and the logical value of “0” of TC<0> to TC<5> may correspond to specific magnitudes of voltages, respectively.

For example, in some embodiments, when the code TC is expressed by “100010” (i.e., when TC<1> and TC<5> are “1” and TC<0>, TC<2>, TC<3>, and TC<4> are “0”), the switch SW1and the switch SW5may be turned on, and the switch SW2, the switch SW3, the switch SW4, and the switch SW6may be turned off.

When a specific switch of the switches SW1to SW6is turned on, a current may flow through the specific switch, and bias transistors in the current source CS4and differential pairs in the transistor TR9and the transistor TR10connected to the specific switch. For example, in some embodiments, when the switch SW1is turned on, a current may flow through a transistor TR11_1connected to the switch SW1. For example, in some embodiments when the switch SW5is turned on, a current may flow through transistors of a group G5and differential pairs in the transistor TR9and the transistor TR10connected to the switch SW5.

The current source CS4may be a current mirror circuit corresponding to a replica of the current source CS3. A voltage Vbias may be a bias voltage supplied in common to the current source CS3and the current source CS4. Accordingly, in some embodiments when the switches SW1to SW6are turned on, a mirrored current obtained by mirroring the reference current Iref2may flow through bias transistors TR11_1to TR11_4, transistors of the group G5, and transistors of a group G6, which are connected to the switches SW1to SW6. In detail, the magnitude of the current flowing through the current source CS4may be proportional to the magnitude of the reference current Iref2.

Also, as a width of a transistor becomes larger, the magnitude of a current flowing through the transistor may become greater. For example, the magnitude of the current flowing through the transistor may be proportional to a width of the transistor. Widths of the bias transistors TR11_1to TR11_4may be “16 W”, “8 W”, “4 W”, and “2 W”, respectively. Each of the transistors in the group G5and the group G6may be “2 W”. As described with reference to transistors of the groups G1to G4, the serially connected transistors of the group G5may operate as a transistor having a width of “W”. The serially connected transistors of the group G6may operate as a single transistor having a width of “(½)*W”.

For example, in some embodiments when only the switch SW1is turned on (in some embodiments when only TC<5> is “1” and TC<0> to TC<4> are “0”), a current having a magnitude of “(Iref2)/2” may flow through the transistor TR11_1having a width of “16 W”. As in the above description, a current having a magnitude of “(Iref2)/4” may flow through the transistor TR11_2, a current having a magnitude of “(Iref2)/8” may flow through the transistor TR11_3, a current having a magnitude of “(Iref2)/16” may flow through the transistor TR11_4, a current having a magnitude of “(Iref2)/32” may flow through the transistors of the group G5, and a current having a magnitude of “(Iref2)/64” may flow through the transistors of the group G6. That is, a current having a magnitude of “(2j)*(Iref2)” may flow through the transistors TR11_1to TR11_4, the transistors of the group G5, and the transistors of the group G6(j being an integer, −6≥j≥−1). An example range of “−6≤j≤−1” is described with reference toFIG. 8, however, it is understood that the inventive may include embodiments for other ranges of the integer “j”.

In some embodiments when only one of the switches SW1to SW6is turned on, the magnitude of the current flowing through a current source CS may be one of “(Iref2)/2”, “(Iref2)/4”, “(Iref2)/8”, “(Iref2)/16”, “(Iref2)/32”, and “(Iref2)/64”. In some embodiments when two or more of the switches SW1to SW6are turned on, the magnitude of the current flowing through a current source CS may correspond to a sum of the magnitudes of currents, which flow through turned-on switches, from among “(Iref2)/2”, “(Iref2)/4”, “(Iref2)/8”, “(Iref2)/16”, “(Iref2)/32”, and “(Iref2)/64”. Accordingly, the magnitude of the current flowing through the current source CS4may correspond to a sum of numbers expressed by “(2j)*(Iref2)”. That is, the magnitude of the current flowing through the current source CS4may be selected to be proportional to the magnitude of the reference current Iref2depending on the code TC.

The compensation current ITC2may be output as a current flows through the switch unit SW. Accordingly, the magnitude of the compensation current ITC2may correspond to the magnitude of the current flowing through the current source CS4(e.g., the magnitudes may be substantially identical to each other). This may mean that the magnitude of the compensation current ITC2is selected to be proportional to the magnitude of the reference current Iref2.

For example, in some embodiments when the code TC has a reference value, the compensation current ITC2which has the smallest magnitude (e.g., a reference current magnitude: for example, 2−6*(Iref2)) of magnitudes which may be selected may be output. Accordingly, in some embodiments when a value of the code TC is increased by the reference value, the magnitude of the compensation current ITC2may be increased by the reference current magnitude.

For example, in some embodiments when the reference value of the code TC is “000001”, whenever a value of the code TC is increased by “000001”, the magnitude of the compensation current ITC2may be increased by “(Iref2)/64” which may be the magnitude of a current flowing through the switch SW6and transistors of the group G6. For example, the magnitude of the compensation current ITC2selected by the code TC having the value of “000100” is “(Iref2)/16”, and the magnitude of the compensation current ITC2selected by the code TC having the value of “000101” is “(Iref2)/64+(Iref2)/16”.

As described with reference toFIG. 6, in embodiments where characteristics of the transistor TR9and the transistor TR10selected by the code TC are substantially identical to each other, the magnitude of the current I41may be substantially identical to the magnitude of the current I42. Accordingly, the magnitude of the current flowing through the current source CS4may be proportional to the magnitude of the reference current I41. Also, in embodiments where characteristics of the transistor TR7and the transistor TR8are substantially identical to each other, the magnitude of the current I31may be substantially identical to the magnitude of the current I32. Accordingly, the magnitude of the current I32ofFIG. 6may be proportional to the magnitude of the reference current Iref2.

The magnitude of the current I32may be proportional to the magnitude of the reference current Iref2, and the magnitude of the current I41may also be proportional to the reference current Iref2. According to the above description, in Equation 3 and Equation 4, “I41” may have a value proportional to “I32”. The compensation current generating circuit2131may be configured to output the current I41having a magnitude proportional to the magnitude of the current I32, based on the process described with reference to the operation of the current source CS4.

In Equation 3 and Equation 4, in embodiments where “W_9” has a value proportional to “W_8” and “I41” has a value proportional to “I32”,

“W_⁢9*I⁢⁢41W_⁢8*I⁢⁢32”
may have a value independent of a temperature and a value of the code TC. Accordingly, the magnitude of the feedback voltage Vfb calculated according to Equation 3 and Equation 4 may be linear to a temperature and a value of the code TC. As a magnitude of the read voltage Vread2corresponds to the magnitude of the feedback voltage Vfb, the magnitude of the read voltage Vread2may be linear to a temperature and a value of the code TC. For example, the magnitude of the read voltage Vread2may have a reference voltage value in response to the code TC of the reference value. Also, whenever a value of the code TC is increased by the reference magnitude, the magnitude of the read voltage Vread2may be increased by the reference voltage magnitude.

The read voltage generating circuit2000may be configured to output the read voltage Vread2of a magnitude linear to a temperature and a value of the code TC. As a magnitude of the read voltage Vread2may correspond to the magnitude of the feedback voltage Vfb, the read voltage generating circuit2000may be configured to output the read voltage Vread2including a magnitude that is linear to the temperature and the value of the code TC. Some embodiments in which the transistor TR9and the transistor TR10are selected by the code TC will be described with reference toFIGS. 9 to 11.

FIG. 9is a circuit diagram for describing an example operation of the compensation current generating circuit ofFIG. 8according to some embodiments of the inventive concepts. In the operation illustrated inFIG. 9, one transistor TR9_1may be selected as the transistor TR9, and one transistor TR10_1may be selected as the transistor TR10.

For example, the switch unit SW of the current source CS4may receive the code TC having “100000” from the logic circuit (i.e., only a code value TC<5> is “1”, and the remaining values are “0”). As the switch SW1is turned on in response to the logical value of “1”, a current of “(Iref2)/2” may flow through the transistor TR11_1.

As the current of “I41+I42” flows through the transistor TR11_1, a current I41may flow through the transistor TR9_1and a current I42may flow through the transistor TR01_1electrically connected to the transistor TR11_1. As the current of I41and the current I42flow through the transistors TR9_1and TR10_1respectively, the current I41and the current I42may be respectively input to the transistor TR9and the transistor TR10. In embodiments where the transistor TR7and the transistor TR8of the reference current generating circuit2120are symmetrical to each other, the magnitude of the current I32may be “I41+I42”.

Accordingly, based on the code TC of “100000”, the magnitude of a magnitude of the current I41and the current I42may be selected as a specific value, the transistor TR9_1may be selected as the transistor TR9, and the transistor TR10_1may be selected as the transistor TR10.

FIG. 10is a circuit diagram for describing an example operation of the compensation current generating circuit ofFIG. 8according to some embodiments of the inventive concepts. In the operation illustrated inFIG. 10, two or more transistors TR9_5and TR9_6may be selected as the transistor TR9, and two or more transistors TR10_5and TR10_6may be selected as the transistor TRI0.

For example, the switch unit SW of the current source CS4may receive the code TC having “000010” from the logic circuit (i.e., only a code value TC<1> is “1”, and the remaining values are “0”). As the switch SW_5is turned on in response to the logical value of “1”, a current of “I41+I42” may flow through transistors TR11_5and TR11_6of the group G5.

As the current of “I41+I42” flows through the transistors TR11_5and TR11_6, a current I41may flow through transistors TR9_5and TR9_6of the group G1electrically connected to the transistor TR11_5and a current I42may flow through transistors TR10_5and TR10_6of the group G3electrically connected to the transistor TR11_5. As the current I41flows through the transistors TR9_5and TR9_6and through transistors TR10_5and TR10_6, the current I41and the current I42may be respectively input to the transistor TR9and the transistor TR10. In embodiments where the transistor TR7and the transistor TR8of the reference current generating circuit2120are symmetrical to each other, the magnitude of the current I32may be “I41+I42”.

Accordingly, based on the code TC of “000010”, the magnitude of the current I41and the current I42may be selected as a specific value, the transistors TR9_5and TR9_6of the group G1may be selected as the transistors TR9, and the transistors TR10_5and TR10_6of the group G3may be selected as the transistor TR10.

FIG. 11is a circuit diagram for describing an example operation of the compensation current generating circuit ofFIG. 8according to some embodiments of the inventive concepts. In the operation illustrated inFIG. 11, the transistor TR9_1and the transistors TR9_5and TR9_6of the group G1may be selected as the transistor TR9together. The transistor TR10_1and the transistors TR10_5and TR10_6of the group G3may be selected as the transistor TR10together.

In embodiments where transistors are connected in parallel, a current may flow through a channel of a wider width. Accordingly, an operation of the transistors connected in parallel may be similar to an operation of one transistor, the width of which corresponds to a sum of widths of the transistors. In operations where the transistors connected in parallel are selected as the transistor TR9, “W_9” of Equation 4 may correspond to a sum of widths of the selected transistors. For example, in operations where the transistor TR9_1and the transistors TR9_5and TR9_6together operate as the transistor TR9, “W_9” may be “(8+½)*W” which corresponds to a sum of “8 W” and “(½)*W”.

In the operation illustrated inFIG. 11, the switch unit SW of the current source CS4may receive the code TC expressed by “100010” from the logic circuit (i.e., code values TC<1> and TC<5> are “1”, and the remaining values are “0”). As the switch SW_5is turned on in response to the logical value of “1”, a current of “I41_2+I42_2” may flow through transistors TR11_5and TR11_6of the group G5. As the switch SW_1is turned on in response to the logical value of “1”, a current of “I41_1+I42_1” may flow through the transistor TR11_1.

For example, as the current of “I41_2+I42_2” flows through the transistors TR11_5and TR11_6, a current I41_2may flow through the transistors TR9_5and TR9_6of the group GI electrically connected to the transistor TR11_5and a current I42_2may flow through the transistors TR10_5and TR10_6of the group G3electrically connected to the transistor TR11_5. As the current of “I41_1+I42_1” flows through the transistor TR11_1, a current I41_1may flow through the transistors TR9_1and a current I42_1may flow through the transistor TR10_1.

As currents flow through the transistors TR9_5and TR9_6, the transistors TR10_5and TR10_6, the transistor TR9_1, and the transistor TR10_1, the current I41and the current I42may be respectively input to the transistor TR9and the transistor TR10. Also, in embodiments where the transistor TR7and the transistor TR8of the reference current generating circuit2120are symmetrical to each other, the magnitude of the current I32may be “I41+I42”.

That is, based on the code TC of “100010”, the magnitudes of the current I41and the current I42may be selected as specific values, the transistors TR9_5and TR9_6of the group G1and the transistor TR9_1may be selected as the transistor TR9, and the transistors TR10_5and TR10_6of the group G3and the transistor TR01_1may be selected as the transistor TR10.

As described with reference toFIGS. 9 to 11, in the embodiments ofFIG. 8, “W_9” of Equation 4 may selectively have one of “(¼)*W”, “(½)*W”, “W”, “2 W”, “4 W”, and “8 W” or a sum of two or more of “(¼)*W”, “(½)*W”, “W”, “2 W”, “4 W”, and “8 W”, depending on a value of the code TC. That is, a width “W_9” of the transistor TR9in Equation 4 may be variously selected to have a value proportional to a width “W” of the transistor TR8.

Also, as described with reference toFIG. 8, depending on a value of the code TC, the magnitude of the compensation current ITC2may selectively have one of “(Iref2)/2”, “(Iref2)/4”, “(Iref2)/8”, “(Iref2)/16”, “(Iref2)/32”, and “(Iref2)/64”, or a sum of two or more of “(Iref2)/2”, “(Iref2)/4”, “(Iref2)/8”, “(Iref2)/16”, “(Iref2)/32”, and “(Iref2)/64”.

Since the magnitude of the current I41may be proportional to the magnitude of the compensation current ITC2(e.g., the magnitude of the current I41may be ½ times the magnitude of the compensation current ITC2), “I41” may be variously selected to have a value proportional to the magnitude of the reference current Iref2. Since the magnitude of the current I32may be proportional to the magnitude of the reference current Iref2(e.g., the magnitude of the current I32may be ½ times the magnitude of the reference current Iref2), “I32” may be variously selected to have a value proportion to the magnitude of the reference current Iref2. Accordingly, “I41” in Equation 4 may be variously selected to have a value proportional to “I32”.

FIG. 12is a graph illustrating voltages received by the compensation circuit ofFIG. 4according to some embodiments of the inventive concepts. In the graph ofFIG. 12, an x-axis may represent a temperature expressed in terms of a unit oC, and a y-axis may represent a magnitude of a voltage expressed in terms of a unit V. Graphs ofFIG. 12indicate the magnitudes of the voltages Vztc and Vntc varying with a temperature at a specific value of the code TC.

Referring toFIG. 12, the magnitude of the voltage Vntc may be negatively proportional to a temperature. The magnitude of the voltage Vztc may be uniform regardless of a change in temperature. As described with reference toFIG. 1, the voltage Vztc and the voltage Vntc may be received from the voltage generator included in the memory system. For example, the voltage generator may detect a change in temperature of the memory system. The voltage generator may output the voltages Vztc and Vntc of magnitudes corresponding to the detected temperature. For example, in an operation where a temperature is “T1”, the voltage generator may output the voltage Vztc of “V1” and the voltage Vntc of “V2”. For example, in an operation where a temperature is “T2”, the voltage generator may output the voltage Vztc of “V1” and the voltage Vntc of “V1” identical to the magnitude of the voltage Vztc.

FIG. 13is a graph illustrating the read voltage ofFIG. 4depending on the selection signal according to some embodiments of the inventive concepts. In the graph ofFIG. 13, an x-axis may represent a value of the code TC, and a y-axis may represent a magnitude of a read voltage Vread2.

The graph ofFIG. 13is illustrated with regard to continuous values of the code TC, but in some embodiments actual values of the code TC may be discontinuous. However, to easily describe how the magnitude of the read voltage Vread2varies with a value of the code TC, the graph may be illustrated as being continuous with regard to a value of the code TC.

As described with reference toFIG. 7, in some embodiments when the selection signal SEL has a logical value of “1”, the voltage Vztc may be selected as the voltage Va, and the voltage Vntc may be selected as the voltage Vb. Also, when the selection signal SEL has a logical value of “0”, the voltage Vntc may be selected as the voltage Va, and the voltage Vztc may be selected as the voltage Vb.

Referring to Equation 3, the magnitude of the voltage Vout2inFIG. 7may be expressed by Equation 5.
Vfb=Vref+α*(Va−Vb)  [Equation 5]

“Vntc” may have a value negatively proportional to a temperature. Also, “Vztc” may have a uniform value regardless of a temperature. In Equation 5, in operations where “Va” is “Vntc” and “Vb” is “Vztc” (e.g., where a logical value of the selection signal SEL is “0”), “Vfb” may be calculated as a value negatively proportional to a temperature. In Equation 5, in operations where “Va” is “Vztc” and “Vb” is “Vntc” (e.g., where a logical value of the selection signal SEL is “1”), “Vfb” may be calculated as a value positively proportional to a temperature.

As described with reference toFIG. 4, a magnitude of a read voltage Vread2may correspond to the magnitude of the feedback voltage Vfb and a magnitude of a feedback voltage Vfb may correspond to the magnitude of the voltage Vout2.

As a threshold voltage of a memory cell varies with various conditions, the read voltage Vread2having a magnitude that varies with the threshold voltage of the memory cell, may be provided to read accurately a data stored in the memory cell. In embodiments where the read voltage Vread2is desired to have a magnitude that increases according to an increase in a value of the code TC, the logic circuit may output the selection signal SEL having a logical value of “1”. In embodiments where the read voltage Vread2is desired to have a magnitude that decreases according to an increase in a value of the code TC, the logic circuit may output the selection signal SEL having a logical value of “0”.

FIG. 14is a graph illustrating voltages output from the read voltage generating circuits ofFIGS. 1 and/or 4according to some embodiments of the inventive concepts. In the graph ofFIG. 14, an x-axis may represent a temperature expressed in terms of a unit oC, and a y-axis may represent a magnitude of a voltage expressed in terms of a unit V.

Referring toFIG. 14, the magnitude of the read voltage Vread1and the magnitude of the read voltage Vread2may decrease as a temperature increases. On a temperature domain ofFIG. 14, a variation of a differential non-linearity (DNL) value of the voltage Vout1may be greater than a variation of a DNL value of the read voltage Vread2.

The DNL value may be associated with a difference between a magnitude of an ideally linear voltage and a magnitude of an actual voltage on a specific domain. That is, the DNL value may be associated with a linearity of a magnitude of a voltage on a specific domain. In the specification, that the linearity of the voltage is high may refer to the variation of the DNL value of the magnitude of the voltage on a specific domain being small.

As described with reference toFIGS. 4 to 11, since the voltage generating circuit2000is configured to output the read voltage Vread2having a magnitude that is proportional to a temperature, the magnitude of the read voltage Vread2output from the voltage generating circuit2000may have a high linearity on a temperature domain. Referring toFIGS. 1 and 4, on the temperature domain, the linearity of the read voltage Vread2output from the voltage generating circuit2000may be higher than a linearity of the read voltage Vread1output from the voltage generating circuit1000.

As described with reference toFIG. 8, “W_9” and “I41” of Equation 4 may be selected to have a value proportional to “W_8” and “I32”. Accordingly, “α” of Equation 4 may be calculated as a constant independent of a temperature. However, “α” of Equation 2 may include a square root term (a term non-linear to a temperature). Accordingly, on the temperature domain, the linearity of the read voltage Vread2may be higher than the linearity of the read voltage Vread1.

FIG. 15is a graph illustrating voltages output from the read voltage generating circuits ofFIGS. 1 and/or 4according to some embodiments of the inventive concepts. In the graph ofFIG. 15, an x-axis may represent a value of the code TC, TC1, or TC2, and a y-axis may represent a magnitude of a voltage expressed in terms of a unit V.

Referring toFIG. 15, the magnitude of the read voltage Vread1and the magnitude of the read voltage Vread2may increase as a value of the code TC increases. On a code domain, a variation of a DNL value of the read voltage Vread1may be greater than a variation of a DNL value of the read voltage Vread2.

As described with reference toFIGS. 4 to 11, since the read voltage generating circuit2000is configured to output the read voltage Vread2having a magnitude that is proportional to a value of the code TC, the magnitude of the read voltage Vread2output from the compensation circuit2100may have a high linearity on the code domain. Referring toFIGS. 1 and 4, on the code domain, the linearity of the read voltage Vread2output from the voltage generating circuit2000may be higher than a linearity of the read voltage Vread1output from the read voltage generating circuit1000.

As described with reference toFIG. 8, “W_9” and “I41” of Equation 4 may be selected to have a value proportional to “W_8” and “I32”. Accordingly, “α” of Equation 4 may be calculated as a constant independent of a value of the code TC. However, “α” of Equation 2 may include a square root term (a term non-linear to the codes TC1, and TC2). Accordingly, on the code domain, the linearity of the read voltage Vread2may be higher than the linearity of the read voltage Vread1.

FIG. 16is a block diagram illustrating an example memory system including the read voltage generating circuits ofFIGS. 1 and/or 4according to some embodiments of the inventive concepts.

A memory system3000may include a host3100, a memory controller3200and a memory device3300. The memory device3300may include memory devices3300_1to3300_n. Each of the memory devices3300_1to3300_n may include a logic circuit and a voltage generator. For example, the memory device3300_1may include a logic circuit3210_1and a voltage generator3220_1.

The memory controller3200may exchange a command signal CMD, a data signal DAT, and an address signal ADDR with the host3100. The command signal CMD may be associated with operations of the memory device3300. The data signal DAT may indicate data which are stored or will be stored in the memory device3300. The address signal ADDR may indicate an address of a specific memory cell in the memory device3300corresponding to a location where data are stored or will be stored.

The voltage generator3220_1may generate the voltages Vztc and Vntc and the reference voltage Vref ofFIGS. 1 and 4. For example, the voltage generator3220_1may generate the voltages Vztc and Vntc based on a temperature of the memory system3000. The logic circuit3210_1may generate the codes TC1and TC2ofFIG. 1and the code TC ofFIG. 4.

Each of the memory devices3300_1to3300_n may include at least one of the read voltage generating circuits1000and2000ofFIGS. 1 and 4. Each of the memory devices3300_1to3300_n may generate the read voltage Vread1or Vread2based on the voltages Vztc and Vntc, the reference voltage Vref, the codes TC1and TC2, and the code TC. For example, the logic circuit3220may track a change of threshold voltages of memory cells in the memory device3300to determine values of the codes TC1and TC2and a value of the code TC. The logic circuit3220may output the codes TC1, TC2, and TC of the determined values to the memory device3300.

The memory devices3300_1to3300_n of the memory device3300may store or output data under control of the memory controller3200. The memory devices3300_1to3300_n may read data by using the read voltage Vread1or Vread2. The memory devices3300_1to3300_n may have the same configuration or may have similar configurations. Alternatively, the memory devices3300_1to3300_n may have different configurations.

For example, each of the memory devices3300_1to3300_n may include a volatile memory such as an SRAM, a DRAM, an SDRAM, etc. or a nonvolatile memory such as a flash memory, a PRAM, an MRAM, a ReRAM, a FRAM, etc. Alternatively, the memory devices3300_1to3300_n may include heterogeneous memories.

According to some embodiments of the inventive concepts, an electronic circuit which generates a read voltage having a magnitude that varies as a temperature and a value of a code vary, may be provided.

While the inventive concepts has been described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the following claims.