A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

FIELD OF THE INVENTION

The present invention relates to retention flip-flops, and more specifically to retention flip-flops with master-slave latches.

BACKGROUND OF THE INVENTION

Many circuit designs require fast resumption of operation after wakeup from sleep mode. In these designs, it is necessary to save the current data state before going into sleep mode and to restore the state at wakeup. One such on-chip retention method is the so-called dual pin balloon register, which uses separate save and restore control pins and a second slave latch for retention. This dual pin balloon register is illustrated inFIG. 1.

FIG. 1is a high level block diagram of a prior art retention register10. The retention register10is based on a conventional D-type flip-flop, which is represented by master-slave latches12,14. As will be familiar to those in this art, the Q output of the D flip-flop always takes on the state of the D input at the moment of a positive edge (or negative edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and delays it by one clock count. The retention register has an extra data preserving circuit sometimes referred to as a “shadow” latch or “balloon” latch16. The latches12,14of the D flip-flop are designed from standard, low Vt transistors whereas the balloon latch16is designed with weak high Vt transistors. This third latch16is connected to an always on power supply (True VDD) and holds the register state while the leaky master-slave register latches are powered down in sleep mode. This design requires complicated timing for transferring data back and forth between the balloon latches and the flip-flop on any transition from power-down to active mode and vice versa. The design complexities come in part from allowing the retention register to restore the retained data value regardless of the state of the clock. If the clock is low and the master latch is open and sampling input data the retained value is forced into the slave latch. If the clock is high, however, the retention latch value is forced into the master latch and then propagates to the slave latch when the clock goes low. The design also suffers from large size, power and delay related problems.

A lower power, small area retention flip-flop is desired.

SUMMARY OF THE INVENTION

In an embodiment of the present invention, a master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. Relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning communication, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein features communicate with one another either directly or indirectly through intervening structures, unless expressly described otherwise.

An improved retention flip flop design is presented herein. The retention flip-flop exhibits excellent layout size, reduced leakage power in both operational and sleep modes and good timing performance.

FIGS. 2A and 2Billustrate high level depictions of embodiments of retention flip-flops100A,100B. InFIG. 2A, the retention flip-flop100A includes a master latch110A coupled to a slave latch120A. A retention latch130A responsive to a power down control signal PD is embedded within the master latch110A for retaining data during a power down mode. InFIG. 2B, the retention latch130B is embedded within the slave latch120B rather than master latch110B. As discussed in more detail below, embedding the retention latch in one of the master and slave latches removes the retention circuitry from the critical path between the master and slave latches (compareFIG. 1retention flip-flop10), which reduces design complexity and timing issues as well as allows for improved power efficiency.

FIG. 3Aillustrates an embodiment of a retention flip-flop200embodied as a D type flip-flop. The retention flip-flop includes a master latch circuit210coupled to a slave latch circuit240. In this embodiment, a retention latch is embedded within the slave latch240. The devices (i.e., inverter and transmission/pass gates) shown in dark shading represent devices that are powered by a virtual VDD source, i.e., a VDD source that goes low during power down/sleep mode. The devices shown in light gray shading (also illustrated by block250) represent devices that are powered by a true, always on VDD source (i.e., a VDD source that is available during power down). These two sets of devices may have different threshold voltages (Vt), gate lengths, junction doping concentrations, gate oxide thicknesses, substrate biases, etc. In embodiments, the device that are powered by the True VDD exhibit lower leakage current than devices powered by the virtual VDD, as leakage current is a significant concern during sleep mode.

The input data signal is represented as data signal D and the output data signal is represented as output Q. A clock signal CK, more specifically clock bar and clock signals CKB, CKD, respectively, control CMOS pass gates212,214,216and242. Clock signal CK is inverted twice in order to address loading issues due to the number of gates controlled by the clock signal. Power down signal PD controls CMOS transmission gates252,254.

The operation of the master latch210is controlled by the clock signal CKB/CKD. Data signal D is initially inverted by inverter218. When CKD is low, the inverted data passes through transmission gate212and the value of D is held by the output of inverter220, with pass gate216off. On the next clock transition, i.e., when CKD is high, the pass gates214and216turn on and gate212is off. With pass gate216on, the inverter ring of inverters220and222hold the data state as the master latch210passes the data to the slave latch240through gate214.

The slave latch240includes a primary storage ring formed from inverter244, CMOS transmission gate252, inverter256and CMOS transmission gate242. The slave latch240also include a secondary storage ring formed from inverter256, inverter258and transmission gate254. The slave latch240also includes an output inverter246. During normal operation, when CKD goes high, the data held by master latch210is passed through transmission gate214and then twice inverted by inverters244,246to provide data signal Q. Since the circuit is not in power down/sleep mode, power down signal PD is low and the transmission gate252is on. When CKD goes low, gate214is off and gate242is on. Inverters244and256maintain the inverter data state at the input of inverter246and the data is outputted as data signal Q. During sleep mode, transmission gate254is off, deactivating the secondary storage ring.

During power down/sleep mode, all of the devices powered by the virtual VDD are powered down. The primary storage ring is inactive. However, in power down mode, all of the true VDD powered devices in block250are active. Signal PD goes high, which turns off CMOS transmission gate252. CMOS transmission gate254is on, activating the secondary storage ring. The data held in the slave latch at the time of power down is held in the secondary storage ring (i.e., by the inverters256and258).

FIG. 3Cis a timing diagram illustrating the transition from power up mode to sleep mode, and vice versa, for a retention register200illustrated inFIG. 3A.FIG. 3Cshows signals (a) during normal device operation, (b) as the devices enter the sleep mode, (c) during the sleep mode, and (d) as the device leaves the sleep mode. As can be seen fromFIG. 3C, during the sleep mode the virtual VDD power supply switches from high to low to conserve power. The signal NSLEEP is a block turn off signal and further discussion of this signal is not required in order to understand the operation of the retention flip-flop. The power down signal PD is high during the sleep mode and as the device is transitioning in and out of the sleep mode. Of particular note, the clock signal CK can be turned off in all states but the normal/active operation mode. In order to enter the sleep mode, the clock signal CK is first turned off. Then, signal PD goes high, followed by signal NSLEEP going low to power down a block of devices. Finally, Virtual VDD goes low. This order is reversed to bring the device out of sleep mode.

The embodiment ofFIG. 3A, where the retention latch is embedded in the slave latch240to preserve data in power down mode, provides excellent timing and power performance as well as area savings. Because the retention latch is embedded in the slave latch, the retention register does not require a balloon latch. As such, the size of the retention latch is kept to a minimum. Timing is improved as there is no balloon latch present that introduces additional capacitive loading on the Q output path. Moreover, the power performance of the device is excellent as only transmission gates252,254and inverters256,258are active in sleep mode. Further, only a single control pin PD is required in order to add save/restore functionality to an existing flip-flop design. In a CPU, for example, which may have tens of thousands of retention registers, requiring only one pin saves a large amount of routing area and complexity when compared to multiple pin designs. Finally, as mentioned above, the power hungry clock pin need not be functional in the sleep mode, which itself can improve power efficiency.

FIG. 3Billustrates an alternative embodiment200A of the retention flip-flop ofFIG. 3A. Similar components are identified with the same reference numbers fromFIG. 3A. The retention register200A is identical to the register200ofFIG. 3Aexcept for a slightly modified slave latch240A. Within block250a, which includes devices that are active in sleep mode, an inverter251is added in the primary storage ring. The inverter251helps to reduce leakage current from the transmission gate252during sleep mode. Additional inverter243is also added in the primary storage ring to account for the inversion of the data signal by inverter251, and to overcome the high leakage current of transmission gate242during normal operation mode.

FIGS. 4A and 4Billustrate embodiments of a retention flip-flop where the retention latch is embedded in the master latch rather than the slave latch. Again, all devices illustrated with the heavier gray shading are powered by Virtual VDD whereas the devices in block350having the lighter shading are powered by True VDD. The slave latch340includes inverters344,346, and348and transmission gate342. The operation of the slave latch should be apparent. Like the master latch210ofFIGS. 3A and 3B, the master latch310includes an input inverter318, a transmission gate312for passing data when CKD is low, and an output transmission gate314for passing data to the slave latch340when CKD is high. As with the slave latch in the embodiment ofFIG. 3A, where the retention latch is embedded therein, the master latch310has a primary storage ring formed from inverter320, pass gate352, inverter356and pass gate316. Since PD is low during normal operation, this primary storage ring is operational during normal operation. A secondary storage ring for storing data during sleep mode is provided in the master latch310and is formed from inverters356,358and pass gate354. The secondary storage ring is operational when PD goes high.

FIG. 4Billustrates an alternative embodiment300A of the retention flip-flop ofFIG. 4A. Similar components are identified with the same reference numbers fromFIG. 4A. The retention flip-flop300A is identical to the flip-flop300ofFIG. 3Aexcept that master latch310ais slightly modified in the manner described above in connection with slave latch240A ofFIG. 3B. Within block350a, which includes devices that are active in sleep mode, an inverter351is added in the primary storage ring. The inverter351helps to reduce leakage current from the transmission gate352during sleep mode. Additional inverter319is also added in the primary storage ring to account for the inversion of the data signal by inverter351, and to overcome the high leakage current of transmission gate316during normal operation mode.

FIG. 4Cis a timing diagram illustrating the transition from active to sleep modes and vice versa for the circuits ofFIGS. 4A and 4B. As can be seen from the timing diagram, the timing is identical to that shown inFIG. 3Cexcept for clock signal CK remaining high during the transitional enter/leave sleep periods.

Because the retention latch is embedded in the master latch in the embodiments ofFIGS. 4A and 4B, the retention flip-flop does not require a balloon latch. As such, the size of the retention latch is kept to a minimum. Timing is also improved as discussed above. Moreover, the power performance of the device is excellent as only transmission gates352,354and inverters356,358are active in sleep mode for the embodiment ofFIG. 4A. Additional inverter351is active in sleep mode for the embodiment ofFIG. 4B. Further, only a single control pin PD is required in order to add the save/restore functionality to the register, which leads to savings in routing area and complexity when compared to multiple pin designs. Finally, as mentioned above, the power hungry clock pin need not be functional in the sleep mode, which improves power efficiency.

FIG. 3Dillustrates an alternative embodiment of a retention register200B having a retention latch embedded within the slave latch. The retention register200B is identical to flip-flop200A ofFIG. 3Bexcept for slightly modified master and slave latches210band240b, respectively. More specifically, inverters220and243are replaced with NAND gates270,275, respectively. The NAND gates270,275are responsive to control signal set_n. This embodiment implements a set function into a flip flop having an embedded retention latch. That is, when control signal set n is low, the Q output will be set high regardless of the D input value.

FIG. 4Dillustrates an alternative embodiment of a retention register400B having a retention latch embedded within the master latch. The retention register400B is identical to flip-flop400A ofFIG. 4Bexcept for slightly modified master and slave latches310band340b, respectively. More specifically, inverters320and348are replaced with NAND gates370,375, respectively. The NAND gates370,375are responsive to control signal set_n. This embodiment implements of a set function into a flip flop having an embedded retention latch.

FIG. 3Eillustrates an alternative embodiment of a retention flip-flop200C having a retention latch embedded within the slave latch. The retention flip-flop200C is identical to flip-flop200A ofFIG. 3Bexcept for slightly modified master and slave latches210cand240c, respectively. More specifically, inverters222and244are replaced with NAND gates280,285, respectively. The NAND gates280,285are responsive to control signal reset_n. This embodiment implements a reset function into a flip flop having an embedded retention latch. That is, when reset is low, the Q output will be reset as low regardless of the D input data. While not shown, it should be understood that the NAND gates270,275of the embodiment illustrated inFIG. 3Dcould be added to this embodiment to implement both set and reset functionality into the flip-flop.

FIG. 4Eillustrates an alternative embodiment of a retention flip-flop400C having a retention latch embedded within the master latch. The retention flip-flop400C is identical to flip-flop400A ofFIG. 4Bexcept for slightly modified master and slave latches310cand340c, respectively. More specifically, inverters319and344are replaced with NAND gates380,385, respectively. The NAND gates380,385are responsive to control signal reset_n. This embodiment implements of a reset function into a flip flop having an embedded retention latch. While not shown, it should be understood that the NAND gates370,375of the embodiment illustrated inFIG. 4Dcould be added to this embodiment to implement both set and reset functionality into the register.

FIG. 5illustrates a power connectivity layout for a system on chip (SoC) design500having a single block510with retention flip flops502embedded therein. The retention flip flops502may be of the type described above. Each retention flip flop502is coupled to a True VDD power source506and to a Virtual VDD power source504. The Virtual VDD power source504is connected to the true VDD power source506through a header switch508. The number of header switches needed in a block depends on the power (current) requirement of that block to achieve necessary functional operation. In embodiments where sleep control signal NSLEEP is normally high, as shown inFIGS. 3C and 4C, the header switch506can have a PMOS transistor as the power gate. Before switching to sleep mode, the clock should be frozen and the PD signal should be activated to save data into the retention latch of retention flip flop502. When NSLEEP goes low, the header switch is off and the virtual VDD source504is disconnected from the true VDD source506. In this way, only the retention latch in each retention flip flop502is activated to preserve data in sleep mode. When switching back to normal functional operating mode, the signal NSLEEP must go high to resume the connection of the virtual VDD source504to the True VDD source506. Signal PD is then deactivated to restore the corresponding data back to the slave latch of each retention flip flop502. The signal “NSLEEP_ACK” has the value of “NSLEEP” after it propagates through each power gate. This signal is used to tell when the power up/down operation has been finished.

FIG. 5Aillustrates an alternative embodiment of a power connectivity layout for a system on chip (SoC) design500A having a single block510awith retention flip flops502embedded therein. Each retention flip flop502is coupled to a True VSS power source506A and to a Virtual VSS power source504A. Each Virtual VSS power source504is connected to the true VSS power source506avia a footer switch508a. The number of footer switches needed in a block depends on the power (current) requirement of that block to achieve necessary functional operation. The footer switches508aare controlled by signal SLEEP. Each footer switch508acan use an NMOS transistor as the power gate such that pad504ais disconnected from pad506awhen SLEEP goes low. Before switching to sleep mode, the clock should be frozen and the power down control signal PD should be activated to save data into retention latch of retention flip flops502, which may be of the type described above. In this way, only the retention latch in each retention flip flop is activated to preserve data in sleep mode. When switching back to normal operational mode, the signal SLEEP must go high to resume virtual VDD. Signal PD is then deactivated to restore corresponding data back to the slave latch of each retention flip flop502. The signal “SLEEP_ACK” has the value of “SLEEP” after it propagates through each power gate. This signal is used to tell when the power up/down operation has been finished.