Semiconductor memory device and control method of semiconductor memory device

According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Applications No. 2018-051546, filed Mar. 19, 2018; the entire content which is incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memory device and a control method of the semiconductor memory device.

BACKGROUND

Some semiconductor memory devices adopt a hierarchical structure having a global bit line and a local bit line due to a reading speed and also to prevent an erroneous operation caused by cell leakage.

In such a semiconductor memory device, charging and discharging occurs in both the local bit line and the global bit line when reading data, leading to large power consumption.

Also, the reading speed of data depends on the cell current and there is a problem that the reading speed is slow. Further, there are circuits other than the cells (a precharge/discharge circuit, a column selector, S/A (sense amplifier), and a buffer) for each bank, which increases the area of the bank.

DETAILED DESCRIPTION

According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.

Hereinafter, an embodiment will be described with reference to the drawings. In the description that follows, the same reference signs are attached to components having substantially the same function and configuration and a duplicate description is provided only when necessary. Each embodiment shown below exemplifies an apparatus or a method of embodying technical ideas of the present embodiment and technical ideas of an embodiment do not limit the materials, shapes, structures, arrangements and the like of components to those described below. Technical ideas of an embodiment can be modified in various ways in claims.

Each functional block can be implemented as either hardware or computer software, or a combination of both. For this reason, each block will be described below generally in terms of its function, so that it becomes clear how the block is implemented. Whether such a function is executed as hardware or software depends on the specific implementation or design constraints imposed on the overall system. Those skilled in the art can implement these functions in various ways for each specific embodiment, but determining such implementation is included within the scope of the present invention.

When it is not necessary to distinguish and describe the constituent elements in an embodiment, a description will be given by omitting reference signs. For example, when it is not necessary to distinguish and describe the word lines WL0, WL1, WL2, WL3, the “word line WL” will be described by omitting the reference signs. The same applies to other components.

FIG. 1is a block diagram of the mask ROM51as a semiconductor memory device according to an embodiment.

As shown inFIG. 1, the mask ROM (Read Only Memory)51according to an embodiment includes a row decoder1, a word line driver2, a memory cell array3, a column decoder4, a column switch5of the memory cell array3, a control circuit6, a precharge circuit7, a sense amplifier (S/A)8, and a buffer9.

The row decoder1receives a row address section of an address signal and supplies a word line selection signal for a corresponding bank of the memory cell array3to the word line driver2. The word line driver2applies a row selection signal (H active) to the word line WL corresponding to the word line selection signal. Note that the selection of the word line W may be made asynchronously with a synchronization signal on which the semiconductor memory device operates.

The column decoder4receives a column address section of an address signal and applies a column selection signal for the corresponding bank of the memory cell array3to the column switch5.

The memory cell array3has four banks BK0to BK3. The number of banks BK is not limited to four. The bank BK0includes four memory cells C connected to a local bit line LB0and selected by the local bit line LB0and word lines WL0to WL3, four memory cells C connected to a local bit line LB1and selected by the local bit line LB1and the word lines WL0to WL3, four memory cells C connected to a local bit line LB2and selected by the local bit line LB2and the word lines WL0to WL3, and four memory cells C connected to a local bit line LB3and selected by the local bit line LB3and the word lines WL0to WL3, The other banks BK1to BK3have the same configuration.

The memory cell C has a cell transistor and is selected by the word line WL and the local bit line LB.

The column switch5has a column selection switch CSL connected to each of the local bit lines LB and connects the local bit line LB of the memory cell C selected by the word line driver2to the global bit line GBL in response to a column selection signal from the column decoder4. The bank Bk0has column selection switches CSL0to CSL3connected to the local bit lines LB0to LB3respectively and connects the local bit line LB of the local memory cell C selected by the word line driver2to the global bit line GBL in response to a column selection signal from the column decoder4.

When the selected memory cell C is read, read data from the memory cell C is output via the column selection switch CSL selected by a column selection signal, the global bit line GBL, the sense amplifier (S/A)8, and the buffer9.

Based on a clock CLK and a control signal CTL supplied from outside, the control circuit6controls each unit (such as the local bit line LB, the global bit line GBL, the word line driver2, the column decoder4, the precharge circuit7, etc.) of the mask ROM51. The control signal includes, for example, a read signal RE.

The precharge circuit7precharges the global bit line GBL and a reference global bit line RGBL described below.

The sense amplifier (S/A)8compares the voltage read out from the selected memory cell C via the local bit line LB, the column selection switch CSL, and the global bit line GBL with the reference voltage, determines a data value, and amplifies the determined data value before storing the data value in the buffer9.

The buffer9stores and outputs the data value determined by the sense amplifier8.

(2) Operation of the Semiconductor Memory Device According to an Embodiment

Next, a charge sharing operation of the semiconductor memory device according to an embodiment will be described.

FIG. 2is a diagram showing the relationship between the local bit lines LB0to LB3to which the four memory cells C are connected in the bank BK0and the global bit line GBL. As shown inFIG. 2, the local bit lines LB0to LB3are connected to the global bit line GBL via the column selection switches CSL0to CSL3.

FIG. 3is a timing chart illustrating a charge sharing operation of the semiconductor memory device according to an embodiment shown inFIG. 1.

As shown inFIG. 3, the word line WL of the selected address is first turned on. The timing of turning on the word line WL may be synchronized with the clock of the semiconductor memory device or may be asynchronous.

Then, after charging the global bit line GBL, the column selection switch CSL selected is turned on in synchronization with the clock.

Accordingly, when the selected memory cell C is an off-cell, the potential of the global bit line GBL falls by charges of the global bit line. GBL being charge-shared with the local bit line LB. The potential of the local bit line LB rises by being charge-shared with the global bit line GBL.

The control circuit6may set a potential of the local bit line LB of the selected address to an initial potential which is different from an initial potential (for example, the ground potential) of the global bit line GBL before the column selection switch CSL selected is turned on. For, example, a timing of setting the potential of the local bit line LB of the selected address to the initial potential is between a timing of turning on the column selection switch CSL selected and a timing of setting the potential of the global bit line GBL.

When the selected memory cell C is an on-cell, the potential of the global bit line GBL falls to the potential (for example, the ground potential) while the selected memory cell C is an on-cell when the column selection switch CSL is turned on. When the column selection switch CSL is turned on, the potential of the local bit line LB rises instantaneously because the potential of the global bit line is in the on state, but then falls to the potential in the case of an on-cell.

(3-1) Comparative Example

FIG. 4is a block diagram of the mask ROM61as a comparative example. The same units as those inFIG. 1are denoted with the same reference signs, and a description thereof will be omitted here. As shown inFIG. 4, the mask ROM51differs from the mask ROM51shown inFIG. 1in that each bank BK0to BK3of the memory cell array3has a precharge/discharge circuit101, a column switch102, a sense amplifier103, and a buffer104.

The precharge/discharge circuit101is a circuit for precharging and discharging the local bit line LB.

The column switch102selects the local bit line LB of the memory cell array3.

The sense amplifier (S/A)103compares the voltage read from the selected memory cell C via the local bit line LB with the reference voltage to determine the data value and amplifies the determined data value before storing the data value in the buffer104.

The buffer104outputs the determined data value from the sense amplifier (S/A)103to the global bit line GBL.

FIG. 5is a timing chart illustrating a read operation of the mask ROM61as a comparative example shown inFIG. 4.

As shown inFIG. 5, the selected local bit line LB is charged and also the selected column switch102is turned on. Then, the selected word line WL is turned on in synchronization with the clock.

Accordingly, when the selected memory cell C is an on-cell, the memory cell C of the selected local bit line LB is discharged, and the potential of the selected local bit line LB gradually falls. On the other hand, when the memory cell C of the selected local bit line is an off-cell, the potential of the local bit line LB is maintained until the word line selection signal turns off.

The sense amplifier103compares the voltage read from the selected memory cell C via the local bit line LB with the reference voltage to determine the data value and amplifies the determined data value before storing the data value in the buffer104. The determined data value is output from the buffer104to the global bit line GBL.

The sense amplifier8senses the potential of the global bit line GBL, brings the potential of the global bit line GBL into an on state or an off state, and outputs the potential to the buffer9.

That is, in the comparative example, charging and discharging occurs in both the local bit line LB and the global bit line GBL when reading data, leading to large power consumption. In addition, the reading speed of data depends on the cell current of the memory cell C and so the reading speed of data slows down. Further, for each bank Bk, the precharge/discharge circuit101, the column switch102, the sense amplifier103, and the buffer104other than the memory cell C are present, increasing the area.

(3-2) Effects of Semiconductor Memory Device According to Embodiment

According to the semiconductor memory device in an embodiment, the power consumption when data is read is only for charging/discharging the global bit line GBL, which can reduce the power consumption. In addition, the reading speed of data depends on the column selection switch CSL and thus, as compared with the case of having other circuits (the precharge/discharge circuit101, the column switch102, the sense amplifier103, and the buffer104) in the bank Bk, the reading speed of data can be improved and also, the area of the semiconductor memory device can be reduced.

(4-1) First Modification

FIG. 6is a diagram showing the relationship between the global bit line GBL connected to the sense amplifier8and the reference local bit line RLBL.

InFIG. 6, the local bit lines LB0to LB3to which four memory cells C are connected, the global bit line GBL, two reference local bit lines RLBL0, RLBL1, and the reference global bit line RGBL in bank BK0are shown.

As shown inFIG. 6, the local bit lines LB0to LB3to which the four memory cells C are connected respectively are connected to the global bit line GBL via the column selection switches CSL0to CSL3.

The two reference local bit lines RLBL0, RLBL1to which four memory cells C are connected are connected to the reference global bit line RGBL via reference voltage selection switches RCSL0to RCSL3.

That is, the number of cell transistors of the memory cell C connected to reference local bit line RLBL is larger than the number of cell transistors of the memory cell C connected to the local bit line LB0.

The number of cell transistors connected to the local bit line LB is the number of cell transistors in accordance with data to be memorized. In contrast, the number of cell transistors connected to the reference local bit line RLBL is a unique. The number of cell transistors connected to the reference local bit line RLBL may be changed in accordance with a connection condition of the cell transistors electrically connected to the local bit line LB.

Column selection signals supplied to the column selection switches CSL0to CSL3are supplied to the reference voltage selection switches RCSL0to RCSL3respectively. When the column selection signal is supplied to the selected reference voltage selection switch RCSL, the two reference local bit lines RLBL0, RLBL1are connected to the reference global bit line RGBL.

Accordingly, when the selected memory cell C is read, the read data from the memory cell C is input into the sense amplifier (S/A)8via the column selection switch CSL selected by the column selection signal and the global bit line GBL.

The reference voltage obtained by the four memory cells C connected to the reference local bit line RLBL0and the four memory cells C connected to the reference local bit line RLBL1is input into the sense amplifier (S/A)8via the reference voltage selection switch RCSL and the reference global bit line RGBL.

The sense amplifier8compares the potential of the selected memory cell C input via the global bit line GBL with the reference voltage input via the reference global bit line RGBL to determine the data value and amplifies the determined data value before storing the data value in the buffer9.

The value of the memory cell C connected to the local bit line LB and the reference local bit line RLBL is determined in the fabrication process of the mask ROM according to an embodiment. For example, the memory cell C connected to the reference local bit line RLBL is formed of an off-cell having via.

The reference voltage obtained from the four memory cells C (total of eight memory cells C) connected to each of the reference local bit lines RLBL0, RLBL1is designed so as to be an intermediate voltage between a voltage when the selected memory cell C is on and a voltage when the selected memory cell C is off.

It should be noted that the reference voltage selection switches RCSL0to RCSL3and the column selection switches CSL0to CSL3may be the same signal line.

The number of the reference voltage selection switches RCSL0to RCSL3may be one (for example, only RCSL0). Even with such a configuration, the reference voltage can be supplied to the sense amplifier8when the memory cell C is selected.

Further, the present example has been described as a case where the number of reference local bit lines RLBL is two, but three or more reference local bit lines RLBL may be used.

FIG. 7is a timing chart illustrating the charge sharing operation of the semiconductor memory device including the reference local bit line RLBL shown inFIG. 6and the reference global bit line RGBL.

The control of the word line WL, the global bit line GBL, the column selection switch CSL, and the local bit line LB is the same as the control described with reference toFIG. 3. That is, the word line WL of the selected address is turned on, then the global bit line GBL is turned on, and then the column selection switch CSL selected in synchronization with the clock is turned on.

Note that the selection of the word line W may be made asynchronously with a synchronization signal on which the semiconductor memory device operates.

Accordingly, when the selected memory cell C is an off-cell, the potential of the global bit line GBL instantaneously falls by charges of the global bit line GBL being charge-shared with the local bit line LB. The potential of the local bit line LB rises by being charge-shared with the global bit line GBL.

When the selected memory cell C is an on-cell, the potential of the global bit line GBL falls to the potential (for example, the ground potential) while the selected memory cell C is an on-cell when the column selection switch CSL is turned on. When the column selection switch CSL is turned on, the potential of the local bit line LB rises instantaneously because the potential of the global bit line is in the on state, but then falls to the potential in the case of an on-cell.

Further, the potential of the reference global bit line. RGBL is turned on at the same timing as the timing at which the potential of the global bit line GBL is charged. Then, the corresponding reference column selection switch RCSL is turned on at the same timing as the timing at which the column selection switch CSL selected in synchronization with the clock is turned on.

Accordingly, the reference voltage of the memory cell C connected to the reference local bit line RLBL appears on the reference global bit line RGBL and is supplied to the sense amplifier8. The reference voltage is set so as to be an intermediate voltage between a voltage when the memory cell C connected to the local bit line LB is in an off state and a voltage when the memory cell C is in an on state.

Note that the reference voltage may be generated by a regulator or a resistance dividing circuit.

Further, reading of data by the sense amplifier8may be performed independently of external timing.

In addition, even if an off-cell having via or an on-cell having no via is used for the memory cell C connected to the reference local bit line RLBL and read control of data as described in an embodiment is exercised, an on/off range (for example, 50 mV or more) in which the sense amplifier8normally operates can be secured.

(4-2) Second Modification (Example of Arrangement of Discharge Circuit)

The second modification shows the arrangement of the discharge circuit31for discharging the memory cell C connected to the local bit line LB of the mask ROM51according to an embodiment.

FIG. 8is a diagram showing an example in which the discharge circuit31is connected to the local bit line LB to which four memory cells C are connected. The selected memory cell C is connected to the global bit line GBL via the column selection switch CSL.

Charges of the memory cells C other than the selected memory cell C are discharged to the discharge circuit31after a read process. The discharge circuit31is, for example, a transistor connected to the local bit line LB.

FIG. 9is a diagram showing an example in which the discharge circuit31is connected to the global bit line GBL. After the read process, charges of the memory cells C other than the selected memory cell C are discharged to the discharge circuit31connected to the global bit line GBL via the column selection switch CSL.

FIG. 10is a diagram showing an example in which the discharge circuits31are connected to the respective local bit lines LB0, LB1. The local bit lines LB0, LB1are connected to the global bit line GBL via the column selection switches CSL0, CSL1respectively.

Charges of the memory cells C other than the selected memory cell C are discharged to the discharge circuits31connected to the respective local bit lines LB0, LB1after the read process.

FIG. 11is a diagram showing an example in which the local bit lines LB0, LB1to which the discharge circuit31is connected are collectively connected to the common local bit line LBCbefore being connected to the global bit line GBL. The local bit lines LB0, LB1are connected to the common local bit line LBCvia the column selection switches CSL0, CSL1respectively. The common local bit line LBCis connected to the global bit line GBL via the common column selection switch CSLC.

Charges of the memory cells C other than the selected memory cell C are discharged to the discharge circuits31connected to the respective local bit lines LB0, LB1after the read process.

FIG. 12is a diagram showing an example in which the two discharge circuits31shown inFIG. 11are shared by one discharge circuit31. That is, instead of the discharge circuits31connected to the respective local bit lines LBLB0, LB1, the discharge circuit31is connected to the common local bit line LBC.

Charges of the memory cells C other than the selected memory cell C are discharged to the discharge circuit31connected to the common local bit line LBCvia the column selection switches CSL0, CSL1after the read process.

Therefore, according to such a configuration, the area of the mask ROM51according to an embodiment can be reduced by sharing the discharge circuit31.

In an embodiment, the mask ROM has been described as an example of the semiconductor memory device, but it is also possible to apply the read control based on charge sharing according to an embodiment to other semiconductor memory devices such as RAM, SRAM and the like.