Reliability enhancement of metal thermal interface

A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

BACKGROUND OF THE INVENTION

The present invention relates to microelectronic circuit fabrication and structure, and more particularly, to improving the reliability of solid-solder based cooling schemes used in electronic packages.

Solder thermal interface may be used between a processor chip and a heat spreader to effectively remove heat from the processor. Typically, the processor chip is silicon and the heat spreader is Ni-plated copper, an alloy or a composite. However, the relatively rigid solder thermal interface compared to a polymeric TIM or grease, even with the use of softer metals such as indium or its alloys, is prone to cracking in thermal or power cycling due to thermomechanical stresses generated by the coefficient of thermal expansion (CTE) mismatch between the heat-spreader and the silicon chip. The CTE mismatch is exacerbated with a copper heat-spreader which is often used due to cost and thermal conductivity advantages. The dynamic warp of the chip-carrier is another contributor to the propensity for solder TIM cracking and/or thermal degradation in organic, laminate chip-carrier packages. The cracked solder interface results in thermal degradation and an increase in processor operating temperature or a reduction in reliability.

An increase in thermal interface material (TIM) thickness may reduce strain in the TIM and consequently may mitigate the thermal cycling related solder TIM cracking. An increase in TIM bondline may decrease the thermal performance. It is preferable to use a thinner bondline to obtain good thermal performance. Also, due to the dynamic warp associated with laminate chip-carriers, organic packages with solder thermal interface are susceptible to TIM cracking and associated thermal performance deterioration in the field. The proclivity for solder cracking may increase as the die size increases.

A liquid metal TIM may be used to benefit from the higher thermal conductivity of a metal TIM, while eliminating the fatigue cracking related degradation of a solid metal TIM (solder). Liquid metal cooling schemes may benefit from the high thermal conductivity of liquid metal alloys. However, the liquid metal cooling requires containment schemes to prevent the material from leaving the interface and shorting exposed components adjacent to the die or on the board. Oxidation and corrosion barriers may be required to protect the liquid metal TIM from degrading and impacting thermal performance or reliability.

For applications involving large chips, high chip-powers, multi-core chips with non-uniform power distribution and hot spots, or devices requiring more power cycles to accommodate power management applications, a high thermal performance, reliable thermal interface solution is needed.

SUMMARY OF THE INVENTION

In a first aspect of the invention, a method of forming an electronic package includes providing a chip having a frontside and a backside. The method includes providing a chip carrier having a top surface and a bottom surface. The method includes bonding the frontside of the chip to the top surface of the chip carrier. The method includes dispensing a seal material at a periphery of the top surface of the chip carrier. The method includes providing a lid. The method includes providing a solder TIM having a first side and a second side, wherein the first side of the TIM contacts the backside of the chip and the second side of the TIM contacts the lid. The method includes performing a reflow to melt the TIM, wherein the first side of the TIM is bonded to the backside of the chip and the second side of the TIM is bonded to the lid. The method includes curing the seal material, wherein the lid is attached to the top surface of the chip carrier. The method further includes injecting backfill material into a space between the top surface of the chip carrier and the lid, wherein the backfill material abuts sides of the TIM and fills the space. The method also includes curing the backfill material.

In a further aspect of the invention, a method of forming an electronic package includes providing a chip having a frontside and a backside. The method includes providing a chip carrier having a top surface and a bottom surface. The method includes bonding the frontside of the chip to the top surface of the chip carrier. The method includes dispensing a seal material at a periphery of the top surface of the chip carrier. The method includes providing a lid having at least one fill hole and at least one vent hole. The method includes providing a TIM having a first side and a second side, wherein the first side of the TIM contacts the backside of the chip and the second side of the TIM contacts the lid. The method includes performing a solder reflow to melt the TIM, wherein the first side of the TIM is bonded to the chip and the second side of the TIM is bonded to the lid. The method further includes injecting backfill material through the fill hole and the vent hole, wherein the backfill material abuts sides of the TIM and fills a cavity between the chip carrier and the lid. The method also includes curing the seal material and the backfill material simultaneously, wherein the lid is bonded to the top surface of the chip carrier.

In a yet further aspect of the invention, an electronic package includes a chip having a frontside and a backside. The electronic package includes a chip carrier having a top surface and a bottom surface, wherein the frontside of the chip is bonded to the top surface of the chip carrier. The electronic package includes a lid. The electronic package further includes a TIM having a first side and a second side, wherein the first side of the TIM is in contact with the backside of the chip, the second side of the TIM is bonded to the lid and the lid is attached to the top surface of the chip carrier at a periphery with a seal. The electronic package also includes backfill material in a space between the top surface of the chip carrier and the lid, wherein the backfill material abuts sides of the TIM.

DETAILED DESCRIPTION OF THE INVENTION

The present invention generally relates to enhancing the reliability of an electronic package cooled with a solder thermal interface material (TIM). In embodiments, the invention provides a structure and method including a backfill material to mitigate TIM solder cracking and associated thermal degradation. In more specific embodiments, the backfill material may be a polymeric resin.

Referring toFIG. 1A, an electronic package10comprises a semiconductor device or chip11bonded to a chip carrier21. Chip11may be a single chip or multichips. A frontside of chip11may be flip chip bonded through C4 bumps (not shown) to a top surface of chip carrier21and underfilled with an underfill material using conventional processes known in the art. The underfill material may be cured with fillets31,32. A lid41may be bonded to a backside of chip11through a solder thermal interface material (TIM)61. Lid41may be bonded at the periphery to the top surface of chip carrier21with a polymeric seal71. Lid41may include fill and vent holes81,91.

In an embodiment of the invention, the backside of chip11may be metallized for an intimate metallurgical bond with a first side of TIM61. TIM61may be bonded on a second side to lid41. The second side of TIM61may also be bonded to a pedestal51on lid41. The metallization on the backside of chip11may include a multilayer stack of Cr/Ni/Au. Alternatively, the metallization may include a stack of Ti/NiV/Au. TIM61may be In, In—Ag alloy, In—Sn alloy, Bi or its alloys, Sn—Ag—Cu (SAC) lead-free solder or other high thermal conductivity material. Preferably, TIM61is In or its alloys. More preferably, TIM61is In. Preferably, TIM61has a thickness of about 1 mil to 20 mil. More preferably, TIM61has a thickness from 4 mil to 12 mil. Lid41may be bonded at the periphery to a top surface of chip carrier21with polymeric seal71. Polymeric seal71may be a silicone elastomer adhesive, an epoxy adhesive, a modified epoxy or a modified silicone adhesive. Chip carrier21may be an organic laminate or a multi-layer ceramic substrate. The space between chip carrier21and lid41may be filled with a backfill material111,112, such as a resin, through fill and vent holes81,91.

Referring toFIG. 3A, fill and vent holes81,91of lid41may be diagonally across from each other. Alternatively, fill and vent holes81,91may be adjacent to each other as shown inFIG. 3B. Fill and vent holes81,91may also be on opposite sides as shown inFIG. 3C

Referring toFIG. 1B, backfill material111,112may also be introduced through a gap in polymeric seal71. Backfill material111,112may be an epoxy or a modified epoxy, a modified silicone or a polyimide with a modulus of elasticity in the range of about 1 GPa to 20 GPa. More preferably, backfill material111,112is an epoxy with a modulus in the range of 3 GPa to 15 GPa. Even more preferable backfill material111,112is an epoxy with a modulus in the range of 5 GPa to 10 GPa.

Referring toFIGS. 1A and 2, a method of forming an electronic package according to an embodiment of the invention will now be described. A frontside of semiconductor chip11may be bonded to a top surface of chip carrier21through C4 bumps (not shown). The space between chip11and laminate chip carrier21and in between the C4 bumps may be underfilled with conventional underfill materials and processes. The underfill material may be cured with fillets31,32along the chip periphery. This sub-assembly of chip joined carrier may be placed in a fixture. Polymeric seal material71may dispensed at a periphery of the top surface of laminate chip carrier21. Solder TIM61may be pre-attached to lid41. Lid41may be positioned such that a first side of solder TIM61makes contact with a backside of metallized chip11. A nominal load may be applied to lid41in the fixture to assure TIM61contacts chip11during TIM reflow. The assembly may be subjected to a solder reflow profile to melt TIM61and make a metallurgical bond between TIM61and the backside of chip11. Simultaneously, polymeric seal material71may be set up to bond lid41to chip carrier21. Subsequently, the assembly may be subjected to another heat cycle to complete the polymeric seal cure. At the end of this process, lid41is attached to the backside of chip11with solder TIM61and the periphery of lid41is attached to chip carrier21as shown inFIG. 1. Subsequently, backfill resin111,112may be introduced into the space between lid41and chip carrier21through fill and vent holes81,91. Backfill resin111,112abuts the sides of underfill fillets31,32and TIM solder fillets101,102and may fill the cavity between the top-side of the chip carrier and the lid. Backfill resin111,112may be cured in another heat cycle.

In an alternative process, after solder TIM61is reflowed and bonded to chip11, the space between lid41and chip carrier21may be filled with backfill resin111,112. Polymeric seal71and backfill resin111,112may be cured simultaneously. The cured backfill resin111,112abutting solder TIM61and bonding laminate chip carrier21to lid41mitigates TIM solder cracking and associated thermal degradation.

FIG. 4Ashows a cross-sectional view of a laminate chip-carrier electronic package after accelerated thermal cycling (ATC) stress testing. The electronic package underwent 1000 hours of 85 deg. C. at 85% RH and approximately 1200 ATC (0 deg. C.-100 deg. C.) thermal stress cycles.FIG. 4Bis a higher magnification view of the electronic package ofFIG. 4A. No edge TIM cracking is indicated.

FIG. 5is a plot of thermal resistance data as a function of ATC stress duration for a laminate chip-carrier electronic package with solder TIM according to an embodiment of the invention and laminate chip-carrier electronic packages with no backfill. The thermal resistance data are shown for edge sensors that track the thermal reliability performance close to the edges of the chip for thermal degradation. The first group of data represents an electronic package with backfill stressed to 1100 ATC (0 deg. C.-100 deg. C.) thermal stress cycles. No thermal degradation is observed. There is stable thermal performance. The subsequent sets of data represent electronic packages with no backfill. There is thermal degradation without the backfill. Thermal resistance increases at 8 and 12 mil bondline solder TIM without the backfill. The backfill mitigates thermal degradation and TIM solder cracking and improves reliability performance.