Integrated circuit and method for its manufacture

An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of <100> crystalline orientation and a second region of <110> crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of <110> crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of <100> crystalline orientation.

TECHNICAL FIELD

The present invention generally relates to a FET IC and to a method for its manufacture, and more particularly relates to a FET IC having SOI devices as well as PFET and NFET Hybrid Orientation (HOT) devices and to a method for its manufacture.

BACKGROUND

The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS circuit. Certain improvements in performance of FET ICs can be realized by forming the FETs in a thin layer of silicon overlying an insulator layer. Such silicon on insulator (SOI) FETs, for example, exhibit lower junction capacitance and hence can operate at higher speeds. The silicon substrate in which the FETs are fabricated, whether a bulk silicon substrate or SOI, is usually of <100> crystalline orientation. This crystalline orientation is selected because the <100> crystalline orientation results in the highest electron mobility and thus the highest speed N-channel FETs. Additional performance enhancements can be realized in a CMOS circuit by enhancing the mobility of holes in the P-channel FETs. The mobility of holes can be enhanced by fabricating the P-channel FETs on silicon having a <110> crystalline orientation. Hybrid orientation techniques (HOT) use <100> crystalline orientation for N-channel FETs and <110> crystalline orientation for P-channel FETs.

Accordingly, it is desirable to combine in a single integrated circuit the favorable characteristics of silicon on insulator FETs with the favorable characteristics that can be realized with hybrid orientation techniques. In addition, it is desirable to provide a method for manufacturing CMOS integrated circuits that combine SOI FETs on the same substrate with bulk HOT N-channel and P-channel FETs. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

A CMOS integrated circuit is provided that takes advantage of the characteristics of bulk hybrid oriented (HOT) transistors in combination with silicon on insulator transistors. The integrated circuit takes advantage of the increased mobility of holes in bulk silicon of <110> crystalline orientation and electrons in bulk silicon of <100> orientation. The integrated circuit comprises a bulk silicon substrate having a first region of <100> crystalline orientation and a second region of <110> crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of <110> crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of <100> crystalline orientation.

A method is provided for manufacturing such a CMOS integrated circuit. The method comprises the steps of providing a silicon substrate having a first crystalline orientation with an overlying silicon layer of second crystalline orientation. A silicon on insulator layer is formed overlying a portion of the silicon layer. A first epitaxial layer having the first crystalline orientation is grown on a portion of the silicon substrate and a second epitaxial layer having the second crystalline orientation is grown on a portion of the silicon layer. A first HOT field effect transistor is formed in the first epitaxial layer, a second HOT field effect transistor is formed in the second epitaxial layer, and a third field effect transistor is formed in the silicon on insulator layer.

DETAILED DESCRIPTION

FIGS. 1–13schematically illustrate a CMOS integrated circuit20and method steps for the manufacture of such a CMOS integrated circuit in accordance with various embodiments of the invention. In these illustrative embodiments only a small portion of CMOS integrated circuit20is illustrated. Various steps in the manufacture of CMOS devices are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

As illustrated inFIG. 1, the method in accordance with one embodiment of the invention begins with a silicon layer22bonded to a silicon carrier substrate24. As used herein, the terms “silicon layer” and “silicon substrate” will be used to encompass the relatively pure silicon materials typically used in the semiconductor industry as well as silicon admixed with other elements such as germanium, carbon, and the like to form crystalline semiconductor material. Silicon layer22and silicon carrier substrate24will be used in the formation of bulk hybrid orientation (HOT) transistors. Silicon layer22is bonded to silicon carrier substrate24by well known wafer bonding techniques, and the silicon layer is thinned, for example, by chemical mechanical planarization (CMP) techniques to a thickness of about 300 nanometers (nm). The silicon layer and the silicon carrier substrate have different crystalline orientations. One of the silicon layer or the silicon carrier substrate is selected to have a <100> crystalline orientation and the other is selected to have a <110> crystalline orientation. In a preferred embodiment, but without limitation, the silicon layer will have a <100> crystalline orientation and the silicon carrier substrate will have a <110> crystalline orientation. In an alternate embodiment of the invention the silicon layer will have a <110> crystalline orientation and silicon carrier substrate will have a <100> crystalline orientation. By <100> crystalline orientation or <110> crystalline orientation is meant a crystalline orientation that is within about ±2° of the true crystalline orientation. Both the silicon layer and the silicon carrier substrate preferably have a resistivity of at least about 18–33 Ohms per square. The silicon can be impurity doped either N-type or P-type, but is preferably doped P-type.

FIG. 2illustrates one method andFIGS. 3 and 4illustrate an alternate method, both in accordance with embodiments of the invention, for forming a silicon on insulator (SOI) layer26overlying silicon layer22.FIG. 2illustrates a process for forming a thin SOI layer26by the SIMOX process. The SIMOX process is a well known process in which oxygen ions are implanted into a sub-surface region of silicon layer22as indicated by arrows28. The silicon layer and the implanted oxygen are subsequently heated to form a sub-surface silicon oxide layer30that electrically isolates SOI layer26from the remaining portion of silicon layer22. The SOI layer has a thickness of about 10–100 nm. The thickness of SOI layer26is determined by the energy of the implanted ions; that is, the implant energy is adjusted so that the range of the implanted oxygen ions just exceeds the intended thickness of SOI layer26. SOI layer26will have the same crystalline orientation as does silicon layer22, and preferably has a <100> crystalline orientation.

In the alternate embodiment illustrated inFIGS. 3 and 4, SOI layer26is formed by a process of wafer bonding. As illustrated inFIG. 3, a layer of insulating material30such as silicon dioxide is formed on the upper surface of silicon layer22and/or on the surface of a second silicon wafer34. Wafer34is bonded to silicon carrier substrate24so that insulating material30separates silicon layer22and second silicon wafer34. As illustrated inFIG. 4, the second silicon wafer is thinned, for example by CMP, to leave thin silicon layer26on insulating layer30overlying silicon layer22. Thin silicon layer26, in this embodiment, can have a thickness of 10–200 nm and can be lightly impurity doped either N-type or P-type. Preferably thin silicon layer26is impurity doped P-type to about 30 Ohms per square and has a <100> crystalline orientation. In accordance with this embodiment of the invention thin silicon layer26does not have to have the same crystalline orientation as silicon layer22. Additionally, silicon layer22can be thinner in this embodiment because silicon on insulator layer26is formed by bonding to silicon layer22and is not formed from silicon layer22.

As illustrated inFIG. 5, the SOI substrate, whether formed by a SIMOX process or by a wafer bonding process, is oxidized to form a thin pad oxide36having a thickness of about 5–20 nm on the surface of silicon on insulator layer26. A layer38of silicon nitride having a thickness of about 50–200 nm is then deposited on top of pad oxide36. The pad oxide can be grown by heating the SOI substrate in an oxygen ambient. The silicon nitride can be deposited, for example, by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) from the reaction of dichlorosilane and ammonia. The silicon nitride layer will subsequently be used as a CMP polish stop as explained below.

A layer40of photoresist is applied to the surface of silicon nitride layer38and is photolithographically patterned as illustrated inFIG. 6. The patterned photoresist layer is used as an etch mask and a trench42is etched through the layers of silicon nitride38, oxide36, silicon on insulator26, insulator30, silicon layer22, and into the upper portion of silicon carrier substrate24. The trench can be etched by a reactive ion etch (RIE) process using a CF4or CHF3chemistry to etch the insulator layers and a chlorine or hydrogen bromide chemistry to etch the silicon. Layer40of photoresist is removed after completing the etching of trench42. Alternatively, photolithographically patterned layer40of photoresist can be removed after being used as an etch mask for the etching of silicon nitride layer38. The etched layer of silicon nitride can then be used as a hard mask to mask the etching of oxide36, silicon on insulator26, insulator30, and silicon layer22. Also in this alternate process the etch step is terminated after etching into the top portion of silicon carrier substrate24.

After removing layer40of photoresist, another layer44of photoresist is applied covering trench42and the remaining portion of silicon nitride layer38and is photolithographically patterned as illustrated inFIG. 7. Patterned photoresist layer44is used as an etch mask and a second trench, trench46, is etched through the overlying layers and into the upper portion of silicon layer22. As with trench42, trench46can be etched by reactive ion etching. Layer44of photoresist can be removed after completing the etching of trench46or, alternatively, after the etching of silicon nitride layer38. In the alternative process the patterned silicon nitride layer is then used as a hard mask to mask the etching of a trench through oxide layer36, SOI layer26, insulator layer30and into the upper portion of silicon layer22. In this exemplary trench42extending into a portion of silicon carrier substrate24was etched before trench46extending into a portion of silicon layer22. In accordance with an alternate embodiment of the invention (not illustrated) the order of formation of the two trenches can be reversed and trench46can be formed first.

After removing photoresist layer44, a layer of silicon oxide or silicon nitride is deposited over the surface of the structure including into trenches42and44. The layer of oxide or nitride is anisotropically etched, for example by RIE, to form sidewall spacers48on the vertical sidewalls of trench42and trench46as illustrated inFIG. 8.

In accordance with an embodiment of the invention, selective epitaxial silicon layers49and50are then grown on the exposed silicon surfaces. Epitaxial silicon layer49is grown on the exposed surface of silicon carrier substrate24at the bottom of trench42and epitaxial silicon layer50is grown on the exposed surface of silicon layer22at the bottom of trench46. The epitaxial silicon layers can be grown by the reduction of silane (SiH4) or dichlorosilane (SiH2Cl2) in the presence of HCl. The presence of the chlorine source promotes the selective nature of the growth, that is, the growth of the epitaxial silicon preferentially on the exposed silicon surfaces as opposed to on the insulator (silicon oxide or nitride) surfaces. The epitaxial silicon layers grow with crystalline orientation that mimics the crystalline orientation of the silicon material upon which they are grown. In the preferred embodiment, epitaxial silicon layer49is grown with the same <110> crystalline orientation as silicon carrier substrate24and epitaxial silicon layer50is grown with the same <100> crystalline orientation as silicon layer22. Sidewall spacers48retard nucleation of the depositing silicon on edges of trench46and especially on the edges of trench42. In the absence of the sidewall spacers, the epitaxial growth might nucleate on the exposed silicon at the edges of the trenches as well as on the bottom of the trenches resulting in less than ideal epitaxial silicon layers. This is especially true of the epitaxial silicon layer grown in trench42because the growing layer might nucleate on <100> crystalline oriented silicon layer22exposed at the edges of the trench as well as on <110> crystalline oriented silicon carrier substrate24exposed at the bottom of the trench. Some overgrowth of silicon may occur above the level of the top surface of silicon nitride layer38, and some silicon in the form of polycrystalline silicon52may deposit on silicon nitride layer38. Polycrystalline silicon52may result because the epitaxial growth process may not be perfectly selective. The silicon deposited on the silicon nitride layer will be polycrystalline rather than monocrystalline because the silicon nitride does not provide a crystalline structure that the depositing silicon can mimic.

The selective epitaxial silicon that overgrows the level of the top of silicon nitride layer38as well as polycrystalline silicon52is removed by CMP as illustrated inFIG. 10. Silicon nitride layer38is used as a polish stop for the CMP.

Following the planarization of the epitaxial silicon layers, another silicon nitride layer54is deposited on the structure. A layer56of photoresist is applied to silicon nitride layer54and is patterned as illustrated inFIG. 11. Spacers48are removed and trenches58are formed by reactive ion etching using the patterned layer of photoresist as an etch mask.

After removing spacers48and forming trenches58, layer56of photoresist is removed and trenches58are filled with a deposited oxide or other insulator59, for example, by LPCVD or PECVD. Deposited insulator59fills trenches58, but is also deposited onto silicon nitride layer54. The excess insulator on silicon nitride layer54is polished back using CMP to complete the formation of shallow trench isolation (STI)60as illustrated inFIG. 12. Silicon nitride layer54is used as a polish stop during the CMP process. Those of skill in the art will recognize that many known processes and many known materials can be used to form STI or other forms of electrical isolation between devices making up the integrated circuit, and, accordingly, those known processes and materials need not be discussed herein. The structure illustrated inFIG. 12includes a silicon on insulator region62and two bulk silicon regions64and66, one of which has a <100> crystalline orientation and the other of which has a <110> crystalline orientation. Following the formation of the shallow trench isolation, epitaxial silicon49and50in bulk regions64and66, respectively, can be appropriately impurity doped in known manner, for example, by ion implantation. In accordance with the preferred embodiment of the invention, bulk region64has <110> crystalline orientation and is impurity doped with N-type impurities and bulk region66has <100> crystalline orientation and is impurity doped with P-type impurities. Regardless of whether silicon carrier substrate24is <110> crystalline orientation and silicon layer22is <100> crystalline orientation, or whether silicon carrier substrate24is <100> crystalline orientation and silicon layer22is <110> crystalline orientation, the <100> crystalline orientation region is impurity doped with P-type impurities and the <110> crystalline orientation region is impurity doped with N-type impurities. SOI region62can also be appropriately impurity doped in the same manner. If SOI region62is to be used for the fabrication of CMOS devices, portions70of region62may be doped with P-type impurities to form P-type wells for the formation of N-channel FETs and other portions72of region62may be doped with N-type impurities to form N-type wells for the formation of P-channel FETs. Impurity doping of the various regions can be carried out in well known manner, with implant species, doses, and energies determined by the type of devices to be fabricated. Implantation of selected regions can be carried out by masking other areas, for example, with patterned photoresist.

After stripping the remainder of layers36,38, and54, the substantially coplanar surfaces of SOI layer26and of each of the bulk silicon regions64and66are exposed and the structure is ready for the fabrication of FETs necessary for implementing the desired integrated circuit function. The fabrication of the various devices, CMOS devices in portions70and72of SOI region62and bulk HOT P-channel and N-channel FETs in regions64and66, can be carried out using conventional CMOS processing techniques. Various processing flows for fabricating CMOS devices are well known to those of skill in the art and need not be described herein. Those of skill in the art know that the various processing flows depend on parameters such as the minimum geometries being employed, the power supplies available for powering the IC, the processing speeds expected of the IC, and the like. Regardless of the processing flow employed for completing the fabrication of the IC, IC20in accordance with one embodiment of the invention includes a bulk N-channel HOT FET90fabricated in bulk silicon region66having <100> crystalline orientation, a bulk P-channel HOT FET92fabricated in bulk silicon region64having <110> crystalline orientation, and CMOS transistors N-channel SOIFET96and P-channel SOIFET98fabricated in portions70and72of SOI region62, respectively. Although not illustrated, some form of electrical isolation such as shallow trench isolation could be implemented between FETs96and98or, alternatively, junctions104could be butted together with electrical isolation being provided by the nature of the pn junction. In the illustrated embodiment silicon carrier substrate24and epitaxial silicon49are of <110> crystalline orientation and P-channel HOT FET92is formed in region64. Also in accordance with the illustrated embodiment, silicon layer22and epitaxial silicon50are of <100> orientation and N-channel HOT FET90is formed in region66. The selection of <110> crystalline orientation for silicon carrier substrate in this illustrative embodiment is arbitrary; those of skill in the art will appreciate that the crystalline orientation of silicon carrier substrate24and silicon layer22can be interchanged without departing from the scope and intent of the invention.

As illustrated inFIG. 13, each of bulk HOT FETs90and92and each of SOIFETs96and98include a gate electrode100overlying a gate insulator102with source and drain regions104positioned on each side of the gate electrode. The gate electrodes can be polycrystalline silicon, metal, silicide, or the like. The gate insulators can be silicon dioxide, silicon oxynitride, a high dielectric constant material, or the like, as required for the particular circuit function being implemented. The source and drain regions can consist of a single impurity doped region or a plurality of aligned impurity doped regions. Although not illustrated, conductive contacts and conductive traces can be coupled to appropriate gate electrodes and source drain regions to interconnect the various transistors of the integrated circuit.

In the illustrative example, especially as illustrated inFIGS. 6–10, the <100> and <110> crystalline orientation epitaxial regions49and50are grown in the same step and the surfaces thereof are planarized in the same step. In accordance with a further embodiment of the invention the two epitaxial regions can be grown separately as illustrated inFIGS. 14–18. The method according to this embodiment of the invention is similar to the previous method up to the steps illustrated inFIG. 6. Instead of etching a second trench as illustrated inFIG. 7, however, a layer of silicon oxide or silicon nitride is deposited on the surface of nitride layer38and into trench42. The deposited layer is reactive ion etched to form sidewall spacers152on the edges of trench42as illustrated inFIG. 14.

In accordance with this embodiment of the invention, as illustrated inFIG. 15, selective silicon epitaxial layer154is grown in trench42by a selective epitaxial growth process as described above. The growth of layer154is nucleated on the portion of silicon carrier substrate24exposed at the bottom of trench42and grows in the same crystalline orientation as that of substrate24.

Another layer156of photoresist is applied covering the surface of nitride layer38and the surface of silicon epitaxial layer154. The layer of photoresist is photolithographically patterned and is used as an etch mask for the etching of an additional trench158that extends into silicon layer22as illustrated inFIG. 16. Trench158can be etched by a RIE process.

Following the etching of trench158, photoresist layer156is removed and another layer of silicon oxide or silicon nitride is deposited over the surface of nitride layer38and the surface of silicon epitaxial layer154. The deposited layer of silicon oxide or silicon nitride is reactive ion etched to form sidewall spacers162on the walls of trench158as illustrated inFIG. 17. In accordance with a further embodiment of the invention, as illustrated, the deposited layer is etched through a patterned photoresist layer that is retained over the surface of epitaxial layer154so that the layer is not removed from epitaxial layer154.

In accordance with this embodiment of the invention, as illustrated inFIG. 18, selective silicon epitaxial layer164is grown in trench158by a selective epitaxial growth process as described above. The growth of layer164is nucleated on the portion of silicon layer22exposed at the bottom of trench158and grows in the same crystalline orientation as that of silicon layer22. If the deposited layer used to form spacers162is retained over epitaxial layer154, that layer prevents further growth of epitaxial silicon on layer154during the growth of layer164.

Any excess epitaxial silicon grown on nitride layer38can be removed by CMP either in a single CMP step following the growth of epitaxial layer164or in two separate steps, one after each of the of the separate epitaxial silicon growth steps. The CMP step or steps can also be used to remove any remaining portion of the deposited layer used to form spacers162. Following the CMP removal of excess epitaxial silicon, the structure is the same as that illustrated inFIG. 10. The process of fabricating an integrated structure can be can be completed by following the steps illustrated inFIGS. 11–13. As with the previously described embodiment, the order in which the two trenches are etched and subsequently filled with epitaxial silicon can be reversed without departing from the scope of the invention.