High linearity capacitor using a damascene tungsten stud as the bottom electrode

The present invention sets forth a process of making, and a device comprising, a capacitor with a damascene tungsten lower electrode. The capacitor is manufactured by first depositing an insulating nitride layer on a field oxide layer, followed by deposition of a layer of oxide on the nitride layer. A gap is etched into both the nitride and oxide layers, wherein a lower electrode comprising a damascene tungsten stud is deposited following deposition of a Ti/TiN liner for the stud. An oxide layer is next formed over the stud having a conducting tungsten channel with another Ti/TiN liner disposed therethrough and connecting with the stud. Then, a metal layer is deposited and etched to form both a contact for the stud via connection to the channel, and an upper electrode insulated from the contact. The resulting capacitor is one having a damascene tungsten lower electrode exhibiting high linearity and sound matching characteristics, and is versatile for use with analog circuits and manufacturable at a thickness of significantly less than one micron.

TECHNICAL FIELD 
The present invention relates to the manufacture of integrated circuit (IC) 
devices and, in particular, to fabrication of a high linearity capacitor 
using a damascene tungsten stud as the bottom electrode for use in an 
integrated circuit device. 
DISCUSSION OF THE RELATED ART 
Perhaps the most widely used material for forming capacitors in integrated 
circuit devices is polysilicon (poly). The oxide layer thickness that 
separates the two electrodes of the poly to poly capacitor is in the range 
of 400-500 angstroms. Poly to poly capacitors exhibit good matching and 
have fair to good linearity, compared with typical semiconducting material 
capacitors. 
However, each polysilicon electrode has a depletion region associated with 
it which produces a nonlinear capacitance, especially as compared with 
that of a typical metal to metal capacitor. To minimize depletion region 
effects, the doping level in each polysilicon plate has to be optimized. 
The usual dopant is phosphorus. The optimization is not straight forward, 
and depends on the thermal budget and dopant distribution. Polysilicon 
capacitor fabrication is expensive and even with optimized dopant 
distribution in each plate, the linearity of the polysilicon capacitor is 
not as good as that which metal to metal capacitors can provide. 
Conventional metal to metal capacitors exhibit great linearity since there 
is no depletion region associated with the metal electrodes. In fact, 
nearly all the stored charge resides at the inner surfaces of the metal 
electrodes. Metal to metal capacitors are also very inexpensive to 
fabricate. However, it is difficult to minimize the variation in the 
thickness of the oxide layer between the metals. This difficulty gives 
rise to poor matching characteristics. Also, the oxide layer of the metal 
to metal is typically on the order of 1 micron thick. It is desired, 
however, to have capacitors as IC elements which are significantly less 
than a micron in thickness, in order to minimize area without reducing 
capacitance. 
A third type of capacitor utilized in IC devices is a crystalline silicon 
to metal capacitor. These capacitors are little used because they exhibit 
larger parasitic effects than their poly to poly counterparts, and the 
silicon must be optimally doped to minimize depletion effects in the 
capacitor electrodes. Also, capacitor coupling to silicon generates noise 
problems. 
Damascene Tungsten has been used in IC devices before. Particularly, it has 
been used as a low resistance, planar local interconnect in CMOS embedded 
SRAM cells, to significantly improve SRAM density and wireability. 
SUMMARY OF THE INVENTION 
It is desired to have a capacitor which exhibits high linearity and 
suitable matching characteristics. The capacitor of the present invention 
exhibits high linearity much as would a conventional metal to metal 
capacitor, and further exhibits sound matching characteristics. 
It is further desired to have a capacitor whose thickness is versatile to 
suit analog circuit applications, and is yet manufacturable with an oxide 
layer having a thickness of significantly less than one micron. The 
capacitor of the present invention is versatile to suit analog circuit 
applications and may be fabricated with a thickness of significantly less 
than one micron. 
The present invention solves the aforementioned problems associated with 
conventional IC capacitor technology by setting forth a process of making, 
and a device comprising, a capacitor with a damascene tungsten lower 
electrode. The capacitor is manufactured by first depositing an insulating 
nitride layer on a field oxide, followed by forming a layer of oxide on 
the nitride layer. A gap is etched into both the nitride and oxide layers, 
wherein a lower electrode comprising a damascene tungsten stud is 
deposited following deposition of a Ti/TiN liner for the stud. An oxide 
layer is next formed over the stud having a conducting channel disposed 
therethrough and connecting with the stud. Then, a metal layer is 
deposited and etched to form both a contact for the stud via connection to 
the channel and an upper electrode insulated from the contact. The 
resulting capacitor is one having a damascene tungsten lower electrode and 
metal upper electrode exhibiting high linearity and sound matching 
characteristics, and is versatile for use with analog circuits and 
manufacturable at a thickness of significantly less than one micron.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIGS. 1A-1D illustrate a method of fabricating a high linearity capacitor 
according to a preferred embodiment of the present invention. FIG. 1A 
shows a nitride layer 10 deposited onto a field oxide 6. The field oxide 6 
preferably has a thickness around 0.5 microns. The field oxide 6 may or 
may not be on a silicon substrate 7, as shown in FIG. 1A. The silicon 
substrate 7 may be undoped or doped, p-type or n-type, and may be lightly 
or heavily doped. A plurality of IC device components may be fabricated on 
the substrate 7 along with the high linearity capacitor. These several 
device components may be electrically interconnected or may be isolated 
electrically from each other and/or the high linearity capacitor. The 
substrate 7 may be cut after processing into several substrates or 
integrated circuit chips or devices. 
The nitride layer 10 is deposited using a conventional deposition 
technique, such as low pressure chemical vapor deposition (LPCVD). 
Constituents of the nitride layer are preferably characterized by the 
chemical formula Si.sub.3 N.sub.4. An undoped oxide or phosphosilicate 
glass (PSG) layer 12 is next deposited on the upper surface of the nitride 
layer 10. If PSG is used, any technique specifically conventionally used 
for deposition of PSG may be performed to produce the PSG layer 12. CMP is 
preferably performed after deposition of the oxide or PSG layer 12 to 
smooth and pacify the upper surface of the layer 12. 
FIG. 1B shows a portion of the oxide layer 12 etched away down to the 
nitride layer 10. This etching is dry and may be reactive ion etching 
(RIE). FIG. 1C next shows the portion of the nitride layer 10 beneath the 
portion of the oxide layer 12 just etched away, also etched away down to 
the field oxide 6. Preferably an etchant which is selective to the nitride 
layer 10 is used to ensure that the underlying material(s) is/are not 
attacked. Two separate etching steps are preferably performed, one for 
each of the oxide layer 12 and the nitride layer 10. After the etching is 
completed, a gap remains defined by the field oxide 6 at the bottom and by 
the sidewalls of the etched oxide 12 and the nitride 10. The inner wall 
surfaces of the gap are preferably substantially vertical. 
Referring to FIG. 1D, a first thin liner 14 of titanium and titanium 
nitride (Ti/TiN) is then deposited onto the surfaces defining the gap. The 
Ti/TiN deposition may be performed in any conventional manner including 
CVD, electron beam or thermal evaporation vacuum deposition or sputtering. 
A damascene tungsten stud 16 is next deposited into the gap over the first 
liner 14. The tungsten stud 16 is deposited to fill the gap entirely such 
that it is substantially level with remaining portions of the oxide layer 
12. A CMP step is next performed to smooth and pacify the upper surface 18 
of the tungsten stud 16 and to planarize it with the upper surfaces 20 of 
the remaining oxide portions 12. 
At this point, the tungsten stud 16 is preferably only making electrical 
and/or physical contact with the first liner 14, while the first liner 14 
is in contact at various portions with the inner walls of the remaining 
oxide 12 and nitride 10 layers, and the field oxide 6. Referring to FIG. 
2, an insulating layer 22, which is preferably an oxide layer, is then 
formed on the upper surfaces 18,20 of the tungsten stud 16 and the 
remaining portions of the oxide layer 12. The oxide layer 22 is deposited 
on these upper surfaces 18,20 using CVD either at low or high pressure, 
and either low or high density plasma enhanced, or traditionally. The 
oxide layer 22 may be pure SiO.sub.2 or a doped layer of SiO.sub.2, with 
any dopant conventionally used. 
A conducting channel 24 is next formed through the oxide layer 22 using 
conventional oxide etch techniques. Material filling the conducting 
channel 24 electrically couples with the damascene tungsten stud 16. A 
second liner 26, which is preferably also Ti/TiN, is preferably deposited 
within the channel 24, after the channel 24 is formed and defined by the 
walls of the oxide layer 22 and the damascene tungsten stud 16 beneath. 
Next, a conducting conduit 28, which is preferably tungsten is deposited 
into the channel 24 to fill the channel 24. The tungsten conduit 28 is 
deposited to fill the gap entirely such that it is substantially level 
with the remaining portions of the oxide layer 22. Then, a CMP step is 
performed to smooth the upper surface of the tungsten conduit and to 
planarize it with the upper surface of the oxide layer 22. 
A metal layer is then deposited and patterned to define, in part, an upper 
electrode 32 on the upper surface 30 of the oxide layer 22. The upper 
electrode 32 lies above the damascene tungsten stud 16, and is 
electrically insulated from it by the oxide 22. As shown in FIG. 2, the 
patterned metal layer also includes a contact 34 which is in electrical 
contact with the damascene tungsten stud 16 via the damascene tungsten 
conduit 24 and second liner 26. The arrangement of the damascene tungsten 
stud 16, the upper electrode 32 and the intermediate oxide layer 22 define 
the capacitor electrodes and the separating dielectric layer, 
respectively. Alternatively, polysilicon may be used instead of metal as 
the upper electrode 32. 
Referring to FIG. 3, in another embodiment of the present invention, 
multiple high-linearity capacitors 2 of the type described above are 
connected in series to reduce the overall capacitance of the combination. 
In this embodiment, a plurality of damascene tungsten studs 16 are formed 
in gaps in a manner similar to that described above. The upper electrodes 
38 of adjacent capacitors serve as contacts to the lower electrodes of 
their neighboring capacitors as shown in FIG. 3. In this way, the voltage 
applied over the entire series combination is divided over the individual 
capacitors, and the capacitance is reduced. For example, if n capacitors 
of equal capacitance, C, are connected in series, the overall capacitance 
of the combination is C.sub.Total =C/n.