High speed conditional back bias virtual ground restoration circuit

A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, VSS, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic “0” to the true ground level. This eliminates sneak current and logic level corruption.

TECHNICAL FIELD

The present disclosure relates to integrated circuit devices having logic circuits capable of low power levels, and more particularly, to a ground restoration circuit (GRC) that substantially reduces sneak leakage current paths in the logic circuits caused when a logic “0” signal is asserted that is not at substantially true ground of the logic circuits, and is used to provide a logic “0” that is substantially true ground.

BACKGROUND

An integrated circuit device may electrically alter the threshold voltage of its NMOS transistors by raising the Vss power rail voltage above the bulk (e.g., well, tub, or substrate) voltage of the integrated circuit substrate (sometimes referred to as a “virtual ground”). This technique is commonly used to reduce the power consumption of the integrated circuit device due to sub-threshold leakage. Generally, the integrated circuit device will have two or more independent voltage domains to service respective logic circuits that have signal paths therebetween; some of these voltage domains may operate on the virtual ground, and other voltage domains may operate on true ground.

A problem exists in an integrated circuit device when a virtual ground of a signal source at a logic “0” is higher, e.g., more positive, than true ground, VSS, in that a logic gate may sneak current and/or logic state corruption when a logic “0” signal to that logic gate does not have the ground level thereof restored to true ground.

SUMMARY

Therefore, a need exists for an apparatus that will substantially prevent sneak leakage current from occurring in the logic circuits of an integrated circuit device when a logic “0” signal is biased at a voltage level above the true ground, VSS, of these logic circuits and restore the logic “0” level to the substantially true ground level.

A high speed conditional back bias virtual ground level shifter is disclosed herein. The standby e.g., sleep, control signal and previous status controls the sneak leakage path conditionally. The high speed conditional back bias virtual ground level shifter is advantageous for critical path or high speed communication signals.

According to a specific example embodiment of this disclosure, an integrated circuit device having conditional back bias virtual ground restoration circuits for preventing sneak leakage currents and shifting a virtual ground level logic “0” to a true ground level logic “0” when logic “0” signals at the virtual ground level are applied in the integrated circuit device comprises: at least one independent voltage domain operating at a virtual ground and at least one other independent voltage domain operating at a true ground, wherein the virtual ground is at a more positive voltage than the true ground; a plurality of conditional back bias virtual ground restoration circuits, each of the plurality of conditional back bias virtual ground restoration circuits is coupled between one of a plurality of first logic circuits operating in the virtual ground voltage domain and one of a plurality of second logic circuit operating in the true ground voltage domain, wherein the plurality of first and second logic circuits operating in the virtual and true ground voltage domains, respectively, are fabricated on an integrated circuit die, and wherein each of the plurality of ground restoration circuits comprises: a level shifter circuit having a logic input and a logic output, wherein the logic output follows logic levels at the logic input; and a switch transistor having a standby input, the switch transistor is coupled between the level shifter circuit and the true ground, wherein when the logic input is at logic “0” and the standby input is at logic “1” the switch transistor is off and prevents sneak leakage current through the level shifter circuit.

According to another specific example embodiment of this disclosure, an integrated circuit device having conditional back bias virtual ground restoration circuits for preventing sneak leakage currents and shifting a virtual ground level logic “0” to a true ground level logic “0” when logic “0” signals at the virtual ground level are applied in the integrated circuit device comprises: at least one independent voltage domain operating at a virtual ground and at least one other independent voltage domain operating at a true ground, wherein the virtual ground is at a more positive voltage than the true ground; a plurality of conditional back bias virtual ground restoration circuits, each of the plurality of conditional back bias virtual ground restoration circuits is coupled between one of a plurality of first logic circuits operating in the virtual ground voltage domain and one of a plurality of second logic circuit operating in the true ground voltage domain, wherein the plurality of first and second logic circuits operating in the virtual and true ground voltage domains, respectively, are fabricated on an integrated circuit die, and wherein each of the plurality of ground restoration circuits comprises: a first P-channel metal oxide semiconductor (PMOS) transistor (202) having a gate, source, drain and bulk; a second PMOS transistor (204) having a gate, source, drain and bulk; a first N-channel metal oxide semiconductor (NMOS) transistor (208) having a gate, source, drain and bulk; a second NMOS transistor (206) having a gate, source, drain and bulk; a third NMOS transistor (212) having a gate, source, drain and bulk; a fourth NMOS transistor (210) having a gate, source, drain and bulk; a first inverter (222) having an input and an output, wherein the first inverter (222) is coupled to the power source voltage and the virtual ground; a first NAND gate (216) having first and a second inputs and an output; a second NAND gate (218) having first and a second inputs and an output; the sources and bulk of the first PMOS transistor (202) and the second PMOS transistor (204) are coupled to the power source voltage; the drains of the first PMOS transistor (202) and the first NMOS transistor (208), the gate of the second PMOS transistor (204) and the first input of the first NAND gate (216) are coupled together; the drains of the second PMOS transistor (204) and second NMOS transistor (206), the gate of the first PMOS transistor (202) and the first input of the second NAND gate (214) are coupled together; the gate of the first NMOS transistor (208) and the input of the first inverter (222) are coupled to a logic signal from a logic circuit operating in the virtual ground voltage domain; the output of the first inverter (222) is coupled to the gate of the second NMOS transistor (206); the source of the first NMOS transistor (208) are coupled to the drain of the fourth NMOS transistor (212) and the bulk of the first NMOS transistor (208) is coupled to true ground; the source of the second NMOS transistor (206) are coupled to the drain of the third NMOS transistor (210) and the bulk of the second NMOS transistor (206) is coupled to true ground; the sources and bulks of the third NMOS transistor (210) and the fourth NMOS transistor (212) are coupled to the true ground; and the second inputs of the first and second NAND gates (216,214) are coupled to a standby signal, wherein when the logic signal from the logic circuit is at logic “0” and the standby signal is at logic “1” the output of the first NAND gate (216) is at logic “0” whereby the fourth NMOS transistor (212) is off and thereby prevents sneak leakage current therethrough.

According to yet another specific example embodiment of this disclosure, a conditional back bias virtual ground restoration circuit for preventing sneak leakage currents and shifting a virtual ground level logic “0” to a true ground level logic “0” when a logic “0” signal at a virtual ground level is present comprises: a first P-channel metal oxide semiconductor (PMOS) transistor (202) having a gate, source, drain and bulk; a second PMOS transistor (204) having a gate, source, drain and bulk; a first N-channel metal oxide semiconductor (NMOS) transistor (208) having a gate, source, drain and bulk; a second NMOS transistor (206) having a gate, source, drain and bulk; a third NMOS transistor (212) having a gate, source, drain and bulk; a fourth NMOS transistor (210) having a gate, source, drain and bulk; a first inverter (222) having an input and an output, wherein the first inverter (222) is coupled to the power source voltage and the virtual ground; a first NAND gate (216) having first and a second inputs and an output; a second NAND gate (218) having first and a second inputs and an output; the sources and bulk of the first PMOS transistor (202) and the second PMOS transistor (204) are coupled to the power source voltage; the drains of the first PMOS transistor (202) and the first NMOS transistor (208), the gate of the second PMOS transistor (204) and the first input of the first NAND gate (216) are coupled together; the drains of the second PMOS transistor (204) and second NMOS transistor (206), the gate of the first PMOS transistor (202) and the first input of the second NAND gate (214) are coupled together; the gate of the first NMOS transistor (208) and the input of the first inverter (222) are coupled to a logic signal operating in the virtual ground voltage domain; the output of the first inverter (222) is coupled to the gate of the second NMOS transistor (206); the source of the first NMOS transistor (208) is coupled to the drain of the fourth NMOS transistor (212); the source of the second NMOS transistor (206) is coupled to the drain of the third NMOS transistor (210); the bulk of the first and second NMOS transistors (208,206) are coupled to the true ground; the sources and bulks of the third NMOS transistor (210) and the fourth NMOS transistor (212) are coupled to the true ground; and the second inputs of the first and second NAND gates (216,214) are coupled to a standby signal, wherein when the logic signal is at logic “0” and the standby signal is at logic “1” the output of the first NAND gate (216) is at logic “0” whereby the fourth NMOS transistor (212) is off and thereby prevents sneak leakage current therethrough.

DETAILED DESCRIPTION

Referring now to the drawing, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

Referring toFIG. 1, depicted is a schematic block diagram of an integrated circuit device comprising a conditional level shifter circuit coupled between two logic circuit modules having independent voltage domains, all fabricated on the integrated circuit device, according to the teachings of this disclosure. An integrated circuit device102comprises first logic circuits110, a conditional level shifter circuit200and second logic circuits104. The first logic circuits110are in a first voltage domain, and the second logic circuits104are in a second voltage domain. The first and second voltage domains may not have substantially the same common or ground voltage potential, e.g., the first voltage domain is at a virtual ground potential while the second voltage domain is at a true ground potential. The virtual and true ground potentials may be different enough wherein if a logic “0” signal is directly coupled between the first and second logic circuits110and104, sneak current will occur in one or both of the first and second logic circuits110and104.

According to the teaching of this disclosure, when a signal on input106is at a logic “0” level that is biased above the true ground, VSS, of the second logic circuits104, the conditional level shifter circuit200will shift the logic “0” signal to a non-biased logic “0” level, or true ground, VSS, and effectively block sneak leakage path current resulting from the shifted logic “0” input signal. A plurality of conditional level shifter circuits200may be implemented in the integrated circuit device102, one for each of a plurality of second logic circuits104operating at the true ground, VSS, as shown inFIGS. 1-3. A signal input112may be used to indicate when logic circuits of the integrated circuit device102are to go into a standby or sleep mode from a normal or operational mode.

Referring toFIG. 2, depicted is a schematic diagram of a conditional level shifter circuit that prevents sneak current when a signal at logic “0” is biased at a voltage level above a true ground of an integrated circuit device, according to a specific example embodiment of this disclosure. A virtual ground is always at a higher, e.g., more positive, voltage than is true ground, VSS. Logic level signals on input106may be at substantially the power source voltage, VDD, for logic “1” or at substantially virtual ground for logic “0”. The signal voltage level at the input106is dependent upon the operational modes of the integrated circuit device102, e.g., normal or standby (sleep) mode controlled by signal112, as more fully described hereinbelow.

In a normal operation mode, the virtual ground of the signal source, e.g., first logic circuits110, that is coupled to the signal line106may be substantially the same as VSS. When in the standby mode (controlled by signal line112) and having a back bias input, the virtual ground of the signal source coupled to the signal input106may be higher, e.g., more positive, than VSSwhen the signal from the signal source is at a logic low (“0”).

VSS lowrepresents the true ground (e.g., 0 volts). VSS highrepresents the virtual ground that is always higher (more positive) than the true ground, VSS low. Virtual ground, VSS high, may range from about 0 volts to several hundred millivolts (mV). When the signal input106is a logic high (“1”), the voltage at the input106is at substantially the power supply voltage, VDD. However, when the signal input106is a logic low (“0”), the voltage at the input106may be from about 0 volts to the virtual ground voltage, VSS high, depending on the operating mode selected, e.g., normal or standby mode controlled by the standby signal on input112of a logic low (“0”) or a logic high (“1”), respectively.

Transistors206and208are N-channel metal oxide semiconductor (NMOS) transistors that are arranged in a differential input configuration. Inverter222provides differential signals to the inputs for the NMOS transistors206and208. The inverter222is coupled to VDDand to a voltage at approximately the virtual ground. Transistors202and204are P-channel metal oxide semiconductor (PMOS) transistors. PMOS transistors202and204in combination with N-channel metal oxide semiconductor (NMOS) transistors206and208create a cross-coupled latch that holds the signal levels stable on the output nodes108aand108b. Inverters218and220provide load isolation to the output nodes108band108a, respectively. Connections of each source, S; drain, D; gate, G; and bulk (e.g., well, tub, or substrate), B; of the transistors202-212are as shown inFIG. 2.

In the normal operation mode, virtual ground, VSS high, is at substantially the same voltage as the true ground, VSS low, both are at the true ground (e.g., 0 volts). The standby signal on input112is at logic “0” (true ground) and causes the outputs of the NAND gates214and216to a logic “1” that turns on NMOS transistors210and212. In this normal operation mode, the conditional level shifter circuit200passes the input logic levels to the output substantially unchanged.

In the standby or sleep mode having a back bias input, virtual ground, VSS high, can be at a voltage higher (more positive) than the true ground, VSS low, e.g., by several hundred mV, for example 0.3 volts, when the input106is at logic “0.” When input106is at about 0.3 volts, the node at the drain connections of the NMOS transistor208and the PMOS transistor202will be at a logic high “1” (e.g., substantially VDD). However, the logic low signal on the input106will not be able to completely shut off the NMOS transistor208and will furthermore introduce a sneak leakage path to ground in a conventional lever shifter circuit.

According to the teachings of this disclosure, NMOS transistor212is added between the NMOS transistor208and the true ground, VSS low, so as to conditionally control (shut off) any sneak leakage current path to the true ground, VSS low, through NMOS transistor208. This conditional operation is controlled by NAND gate216as follows: when the node at the drain connections of the NMOS transistor208and the PMOS transistor202is at a logic high “1” (substantially VDD) and the standby signal on input112is at logic high “1” (substantially VDD), the output of NAND gate216will be at logic low “0,” effectively shutting off NMOS transistor212and thereby automatically preventing any sneak leakage current path therethrough. NMOS transistor210and NAND gate214operate in similar fashion when logic “1” is on the input106because the conditional level shifter circuit200shown inFIG. 2is substantially symmetric. Therefore by introducing NMOS transistors210and212, and NAND gates214and216connected as shown inFIG. 2, a sneak leakage current path is effectively eliminated, according to the teachings of this disclosure.

In standby mode, the ground restoration circuit (GRC) will shift virtual ground level logic “0” to true ground level logic “0”.

It is contemplated and within the scope of this disclosure that other logic configurations can be used to control the NMOS transistors210and212for preventing sneak leakage currents. One having ordinary skill in the art of digital logic circuits and the benefit of this disclosure could readily design such other logic configurations.

Referring toFIG. 3, depicted is a schematic diagram of a portion of the conditional level shifter circuit shown inFIG. 2. The inverter222may comprise totem pole connected PMOS transistor226and NMOS transistor224coupled to the input106and the gate of the NMOS transistor208. The inverters218and220may each comprise totem pole connected PMOS transistor230and NMOS transistor228coupled to the drains of the respective PMOS and NMOS transistors and having an output108. Connections of each source, S; drain, D; gate, G; and (e.g., well, tub, or substrate), B; of the transistors224,226,228and230are as shown inFIG. 3.