Noise reduction device and semiconductor device having the same

A semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit when the output signal is maintained for a specific period of time after the output signal is varied. The second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage.

BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT

The present invention relates to a noise reduction device and a semiconductor device having the noise reduction device. More specifically, the present invention relates to a noise reduction device including a plurality of noise reduction circuits and a semiconductor device having the noise reduction device.

In general, a conventional semiconductor device may include a conventional noise reduction circuit for reducing an external turbulent noise, a power source noise, and the like superimposed on an input signal. Such a conventional noise reduction circuit may include a Schmitt circuit and a low pass filter formed of a capacitance element and a resistor element.

Patent Reference 1 has disclosed such a conventional noise reduction circuit. The conventional noise reduction circuit is formed of a first delay circuit for receiving an input signal and outputting a first delayed signal delayed by a first delayed amount; a first logic circuit for receiving the input signal and the first delayed signal and performing a first logic calculation to output a first signal; a second delay circuit for receiving the first signal and outputting a second delayed signal delayed by a second delayed amount; and a second logic circuit for receiving the first signal and the second delayed signal and performing a second logic calculation to output a second signal. In the conventional noise reduction circuit disclosed in Patent Reference, it is configured such that the second delayed amount is greater than the first delayed amount.Patent Reference: Japanese Patent Publication No. 2009-55470

An example of a conventional semiconductor device110having the conventional noise reduction circuit will be shown inFIG. 8.FIG. 8is a circuit diagram showing the conventional semiconductor device110having a conventional noise reduction circuit127and an external circuit115.

As shown inFIG. 8, the external circuit115is disposed outside the conventional semiconductor device110. Further, an output signal of the external circuit115is input into the conventional noise reduction circuit127through an input terminal123.

The external circuit115has a function of outputting a signal input into the conventional semiconductor device110through the input terminal123. As shown inFIG. 8, the external circuit115is a crystal oscillation circuit including an inverter133, a crystal oscillation element137, a resistor element R11, a capacitor element C11, and a capacitor element C12. In the external circuit115, when the capacitor element C11and the capacitor element C12are repeatedly charged and discharged, the crystal oscillation element137is oscillated to perform an oscillation operation. Then, the inverter133amplifies an oscillation signal, and the external circuit115outputs the oscillation signal.

Accordingly, the oscillation signal output from the external circuit115is input into the input terminal123of the conventional semiconductor device110. When the oscillation signal is input into the input terminal123, an external turbulent noise due to an external turbulence and the like may be superimposed on the oscillation signal.

As shown inFIG. 8, the conventional noise reduction circuit127includes a low pass filter formed of a resistor element R12and a capacitor element C13for removing noise superimposed on the oscillation signal, and a Schmitt circuit143.

In the conventional noise reduction circuit127, a time constant of the low pass filter141and a Schmitt width of the Schmitt circuit143are adjusted according to the noise superimposed on the oscillation signal. Accordingly, the conventional noise reduction circuit127passes the oscillation signal in an original form to be output to an internal circuit (not shown), while removing the noise superimposed on the oscillation signal.

In the conventional noise reduction circuit127shown inFIG. 8, however, it is difficult to remove a noise (a power source noise) superimposed by a power source and accompanied by a fluctuation of the power source. Accordingly, the oscillation signal thus output may be inverted due to the power source noise.

FIG. 9is a chart showing an example of a relationship among a power source voltage, threshold values of the Schmitt circuit143, a voltage of a node A, and a voltage of a node B in the conventional noise reduction circuit127when the power source noise is generated.

As shown inFIG. 9, when the signal input from the external circuit115through the input terminal123has a high (H) level, if the power voltage is suddenly increased due to the power source noise, the input of the Schmitt circuit143(the node A) does not follow the sudden increase due to a filter characteristic.

On the other hand, the threshold values (the Schmitt threshold value H and the Schmitt threshold value L) of the Schmitt circuit143vary following the sudden increase in the power source voltage. Accordingly, the voltage of the note A becomes smaller than the threshold values of the Schmitt circuit143. As a result, when the Schmitt circuit143outputs the output signal having the high (H) level, an unexpected glitch having a low (L) level pulse is generated in the output of the Schmitt circuit143(the node B).

When the unexpected glitch is generated and the output signal is inverted, a whole system (the internal circuit) may malfunction.

Further, in general, there have been many cases in which a same noise reduction circuit is used relative to different input signals when an extent of the noise is small as long as the noise is a similar type. For example, there have been many cases in which it is possible to use the conventional noise reduction circuit127described above. However, when the noise reduction circuit is used at the input terminal (the input pad), it is difficult to use the same noise reduction circuit due to other restrictions according to the input signal if the extent of the noise is not small.

In view of the problems described above, an object of the present invention is to provide a semiconductor device and a noise reduction device capable of solving the problems of the conventional noise reduction device. In the present invention, it is possible to reduce the noise more effectively through applying various measures depending on a type of an input terminal according to an input signal relative to the noise accompanying the fluctuation in the power source voltage.

SUMMARY OF THE INVENTION

In order to attain the objects described above, according to a first aspect of the present invention, a semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit.

According to the first aspect of the present invention, in the semiconductor device, the first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit output to the internal circuit when the output signal is maintained for a specific period of time after the output signal is varied.

According to the first aspect of the present invention, in the semiconductor device, the second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage, so that the second noise reduction outputs the output signal of the second Schmitt circuit to the internal circuit.

According to a second aspect of the present invention, a noise reduction device includes a first noise reduction circuit and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving a first signal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit output to an internal circuit when the output signal is maintained for a specific period of time after the output signal is varied.

According to the second aspect of the present invention, in the noise reduction device, the second noise reduction circuit includes a second Schmitt circuit for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to the internal circuit; and an input signal adjusting unit for adjusting a second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage, so that the second noise reduction outputs the output signal of the second Schmitt circuit to the internal circuit.

In the present invention, when a noise is generated associated with the fluctuation of the power source voltage, it is possible to improve the noise resistance of the device through applying various methods according to the type of input terminal corresponding to the input signal.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereunder, preferred embodiments of the present invention will be explained with reference to the accompanying drawings.

An embodiment of the present invention will be explained. First, a configuration of a semiconductor integrated circuit1having a semiconductor device10will be explained with reference toFIG. 1.FIG. 1is a block diagram view showing an example of a configuration of the semiconductor integrated circuit1having the semiconductor device10according to the embodiment of the present invention.

As shown inFIG. 1, the semiconductor integrated circuit1includes the semiconductor device10, an external circuit12disposed outside the semiconductor device10, and an external circuit14disposed outside the semiconductor device10.

In the embodiment, the semiconductor device10includes an input terminal20; an input terminal22; a noise reduction circuit24; and a noise reduction circuit26. When a signal is input from the external circuit12through the input terminal20, the signal is input into the noise reduction circuit24. After the noise reduction circuit24removes an external turbulent noise and a power source noise, the noise reduction circuit24outputs an output signal into an internal circuit (now shown) of the semiconductor device10. Similarly, when a signal is input from the external circuit14through the input terminal22, the signal is input into the noise reduction circuit26. After the noise reduction circuit26removes an external turbulent noise and a power source noise, the noise reduction circuit26outputs an output signal into an internal circuit (now shown) of the semiconductor device10.

In the embodiment, the external turbulent noise is defined as a noise superimposed on the signals input from the external circuit12and the external circuit14(oscillation signals, described later) due to an external turbulence and the like. The power source noise is defined as a noise superimposed on a power voltage and causing a fluctuation in the power source voltage. The external turbulent noise and the power source noise may be collectively referred to as a noise.

In the embodiment, it is noted that a power source (not shown) such as a power source supplying unit and the like is disposed in the semiconductor integrated circuit1for supplying the power voltage to the circuits (the internal circuits and the like) disposed in the semiconductor device10including the noise reduction circuit24and the noise reduction circuit26, the external circuit12, and the external circuit14. The present invention is not limited to the configuration. It may be possible to supply the power voltage from outside the semiconductor integrated circuit1. Alternatively, it may be possible to separately supply the power voltage to each of the external circuit12, the external circuit14, and the semiconductor device10from separate power sources.

In the embodiment, the signal input from the external circuit14through the input terminal22has more restrictions related to a delay of transmission to the internal circuit compared with the signal input from the external circuit12through the input terminal20. Further, the signal input from the external circuit14through the input terminal22has a higher oscillation frequency.

A process of reducing the noise in each of the noise reduction circuit24and the noise reduction circuit26will be explained next. First, the process of reducing the noise in the noise reduction circuit24will be explained. As describe above, the noise reduction circuit24has the function of reducing the noise of the signal (the oscillation signal) input from the external circuit12, and outputting the signal to the internal circuit.

FIG. 2is a circuit diagram showing an example of a configuration of the external circuit12of the semiconductor integrated circuit1according to the embodiment of the present invention.

As shown inFIG. 2, the external circuit12is a crystal oscillation circuit including an inverter30; a crystal oscillation element34; a resistor element R1; a capacitor element C1; and a capacitor element C2.

In the embodiment, when the external circuit12outputs the oscillation signal, the capacitor element C1and the capacitor element C2are repeatedly charged and discharged, so that the crystal oscillation element34is oscillated to perform an oscillation operation. Then, the inverter30amplifies the oscillation signal, and the external circuit12outputs the oscillation signal. It should be noted that, when the oscillation signal is at a high (H) level, the capacitor element C1is in a charged state and the capacitor element C2is in a discharged state. When the oscillation signal is at a low (L) level, the capacitor element C1is in the discharged state and the capacitor element C2is in the charged state.

In the embodiment, when the external circuit12outputs the oscillation signal, the oscillation signal is input into the noise reduction circuit24through the input terminal20.FIG. 3is a circuit diagram showing an example of a configuration of the noise reduction circuit24of the semiconductor integrated circuit1according to the embodiment of the present invention. As shown inFIG. 3, the noise reduction circuit24includes a low pass filter40, a Schmitt circuit42, and an output signal adjusting unit44.

In the embodiment, the low pass filter40is formed of a resistor element R2and a capacitor element C3. Further, the low pass filter40has a function of cutting a high frequency component of the oscillation signal input from the external circuit12, on which the noise is superimposed, so that it is possible to minimize a rapid voltage fluctuation due to the external turbulent noise.

In the embodiment, the Schmitt circuit42has a Schmitt threshold value H and a Schmitt threshold value L (the Schmitt threshold value H>the Schmitt threshold value L).

In the embodiment, when a potential of the oscillation signal thus input exceeds the Schmitt threshold value H, the Schmitt circuit42outputs a signal having the H level. When the potential of the oscillation signal thus input is less than the Schmitt threshold value L, the Schmitt circuit42outputs the signal having the L level. Further, when the potential of the oscillation signal thus input is between the Schmitt threshold value H and the Schmitt threshold value L, the Schmitt circuit42maintains the level of the signal output immediately before.

In the embodiment, the noise reduction circuit24is configured such that a time constant of the low pass filter40and a Schmitt width of the Schmitt circuit42are adjusted according to the external turbulent noise superimposed on the oscillation signal input from the external circuit12. The Schmitt width of the Schmitt circuit42is defined to be equal to a difference between the Schmitt threshold value H and the Schmitt threshold value L (the Schmitt threshold value H−the Schmitt threshold value L). Accordingly, the noise reduction circuit24has the function of removing the external turbulent noise superimposed on the oscillation signal thus input.

In the embodiment, the output signal adjusting unit44is formed of a delay circuit46and an OR circuit48. It is configured such that the output signal of the Schmitt circuit42is input into the delay circuit46. It should be noted that the delay circuit46includes a D latch circuit and the like, and the present invention is not limited thereto. Further, a delay time t of the output signal through the delay circuit46is determined based on the power source noise superimposed on the power source voltage, a period of time that the delay of the signal transmission to the internal circuit is possible, and the like.

In the embodiment, the OR circuit48is a logic sum circuit for outputting a logic sum of the output signal from the Schmitt circuit42and the output signal delayed by the delay circuit46. Accordingly, when both of the output signal from the Schmitt circuit42and the output signal delayed by the delay circuit46have the H level, the OR circuit48outputs the signal having the L level. Otherwise, the OR circuit48outputs the signal having the H level.

FIG. 4is a schematic chart view showing a relationship among the power source voltage, the Schmitt threshold value H and the Schmitt threshold value L of the Schmitt circuit42, and a voltage of each of nodes of the noise reduction circuit24when the power source noise is generated according to the embodiment of the present invention.

As shown inFIG. 4, during a period of time when the noise reduction circuit24outputs the signal having the H level to the internal circuit, the power source voltage has the rapid fluctuation (the rapid increase) due to the power source noise. When the power source voltage has the rapid fluctuation, the Schmitt threshold value H and the Schmitt threshold value L of the Schmitt circuit42are fluctuated according to the rapid fluctuation. At this moment, the potential of the node A does not follow the fluctuation of the power source voltage, and becomes less than the Schmitt threshold value H and the Schmitt threshold value L. As a result, as shown inFIG. 4, the potential of the output signal of the Schmitt circuit42(the node B) has a glitch of an L level pulse.

In the embodiment, the delay circuit46is configured to delay and transmit the glitch. Accordingly, the glitch having the L level is generated in the potential of the node C (the delayed signal) as the later stage of the delay circuit46at the delayed timing. The output signal (the node B) of the Schmitt circuit42and the delayed signal (the node C) are input into the OR circuit48, so that the OR circuit48outputs the logic sum thereof.

As shown inFIG. 4, when the glitch is generated in the output signal at the node B to have the L level, the delayed signal at the node C has the H level. On the other hand, when the glitch is generated in the delayed signal at the node C to have the L level, the output signal at the node B has the H level. In either case, the glitch is masked in the output signal (the node D) of the OR circuit48. Accordingly, the potential of the output signal has the H level, and the output signal is not inverted to the L level. As a result, it is possible to prevent the output signal output from the noise reduction circuit24to the internal circuit from being inverted to the L level due to the power source noise, thereby preventing a malfunction of the internal circuit (the system).

As described above, in the embodiment, when the external circuit12outputs the oscillation signal to the semiconductor device10through the input terminal20, the noise reduction circuit24removes the noise and outputs the oscillation signal to the internal circuit. Accordingly, it is possible to normally operate the internal circuit without the influence of the noise.

Next, the process of reducing the noise in the noise reduction circuit26will be explained. As describe above, the noise reduction circuit26has the function of reducing the noise of the signal (the oscillation signal) input from the external circuit14, and outputting the signal to the internal circuit. It should be noted that the internal circuit to which the noise reduction circuit26outputs the signal may or may not be the same as the internal circuit to which the noise reduction circuit24outputs the signal, and the present invention is not limited to either case.

FIG. 5is a circuit diagram showing an example of a configuration of the external circuit14of the semiconductor integrated circuit1according to the embodiment of the present invention.

As shown inFIG. 5, the external circuit14is a crystal oscillation circuit including an inverter32; a crystal oscillation element36; a resistor element R3; a capacitor element C4; and a capacitor element C5. It should be noted that the external circuit14has the configuration similar to that of the external circuit12(refer toFIG. 2).

In the embodiment, similar to the external circuit12, when the external circuit14outputs the oscillation signal, the capacitor element C3and the capacitor element C5are repeatedly charged and discharged, so that the crystal oscillation element36is oscillated to perform an oscillation operation. Then, the inverter32amplifies the oscillation signal, and the external circuit14outputs the oscillation signal. It should be noted that the external circuit14is configured to output the oscillation signal oscillating at a higher rate (the oscillation frequency is high) as compared with the external circuit12.

In the embodiment, when the external circuit14outputs the oscillation signal, the oscillation signal is input into the noise reduction circuit26through the input terminal22.FIG. 6is a circuit diagram showing an example of a configuration of the noise reduction circuit26of the semiconductor integrated circuit1according to the embodiment of the present invention. As shown inFIG. 6, the noise reduction circuit26includes a low pass filter50, a Schmitt circuit52, and a capacitor element C7having a function of adjusting the input signal.

In the embodiment, the low pass filter50is formed of a resistor element R4and a capacitor element C6. Further, similar to the low pass filter40of the noise reduction circuit24, the low pass filter50has a function of cutting the high frequency component of the oscillation signal input from the external circuit14, on which the noise is superimposed, so that it is possible to minimize the rapid voltage fluctuation due to the external turbulent noise.

In the embodiment, the Schmitt circuit42has the Schmitt threshold value H and the Schmitt threshold value L (the Schmitt threshold value H>the Schmitt threshold value L).

In the embodiment, similar to the Schmitt circuit42of the noise reduction circuit24, when the potential of the oscillation signal thus input exceeds the Schmitt threshold value H, the Schmitt circuit52outputs the signal having the H level. When the potential of the oscillation signal thus input is less than the Schmitt threshold value L, the Schmitt circuit52outputs the signal having the L level. Further, when the potential of the oscillation signal thus input is between the Schmitt threshold value H and the Schmitt threshold value L, the Schmitt circuit52maintains the level of the signal output immediately before.

In the embodiment, the noise reduction circuit26is configured such that the time constant of the low pass filter50and the Schmitt width of the Schmitt circuit52are adjusted according to the external turbulent noise superimposed on the oscillation signal input from the external circuit14. The Schmitt width of the Schmitt circuit52is defined to be equal to the difference between the Schmitt threshold value H and the Schmitt threshold value L (the Schmitt threshold value H−the Schmitt threshold value L). Accordingly, the noise reduction circuit26has the function of removing the external turbulent noise superimposed on the oscillation signal thus input.

In the embodiment, in the noise reduction circuit26, the capacitor element C7is connected between the input terminal and the output terminal of the Schmitt circuit52. The capacitor element C7has a function of adjusting the potential of the input signal of the Schmitt circuit52. More specifically, the capacitor element C7has the function of adjusting the potential of the input signal (the node A) according to the potential of the output signal of the Schmitt circuit52.

FIG. 7is a schematic chart view showing a relationship among the power source voltage, the Schmitt threshold value H and the Schmitt threshold value L of the Schmitt circuit52, and a voltage of each of nodes of the noise reduction circuit26when the power source noise is generated according to the embodiment of the present invention.

As shown inFIG. 7, during a period of time when the noise reduction circuit26outputs the signal having the H level to the internal circuit, the power source voltage has the rapid fluctuation (the rapid increase) due to the power source noise. When the power source voltage has the rapid fluctuation, the Schmitt threshold value H and the Schmitt threshold value L of the Schmitt circuit52are fluctuated according to the rapid fluctuation. At this moment, the potential of the node A does follow the fluctuation of the output signal (the node B) and fluctuates (is increased) due to the capacitor element C7connected between the input terminal and the output terminal of the Schmitt circuit52. Accordingly, the potential of the node A follows and fluctuates according to the fluctuation of the power source voltage, and does not become less than the Schmitt threshold value H and the Schmitt threshold value L.

As a result, as shown inFIG. 7, the potential of the output signal (the node B) of the Schmitt circuit52does not have the glitch of the L level pulse, so that the output signal is not inverted to the L level. Accordingly, it is possible to prevent the output signal output to the internal circuit from the noise reduction circuit26from being inverted to the L level due to the power source noise, thereby making it possible to prevent a malfunction of the internal circuit (the system).

As described above, in the embodiment, when the external circuit14outputs the oscillation signal to the semiconductor device10through the input terminal22, the noise reduction circuit26removes the noise and outputs the oscillation signal to the internal circuit. Accordingly, it is possible to normally operate the internal circuit without the influence of the noise.

In the embodiment, the glitch is generated in the noise reduction circuit24. Depending on the width of the glitch thus generated, it may be difficult to mask the glitch within the oscillation cycle of the oscillation signal thus input. This phenomenon becomes more prominent as the oscillation frequency is increased. On the other hand, in the noise reduction circuit26, the generation of the glitch itself is prevented, thereby preventing the phenomenon described above. Accordingly, it is possible to effectively remove the noise with respect to the external circuit14(the crystal oscillation circuit) having the high oscillation frequency, thereby making it possible to apply to the high operation speed system.

Further, as described above, the noise reduction circuit26is not provided with the delay circuit46that is disposed in the noise reduction circuit24. Accordingly, the delay of the output signal is restricted. As a result, it is possible to apply to the output signal having the strict restriction with respect to the delay of the transmission.

As explained above, in the embodiment, the semiconductor device10of the semiconductor integrated circuit1includes the input terminal20, the input terminal22, the noise reduction circuit24, and the noise reduction circuit26. The oscillation signal from the external circuit12as the crystal oscillation circuit is input into the input terminal20. After the oscillation signal is input into the input terminal20, the noise reduction circuit24removes the noise from the oscillation signal, and the oscillation signal is output to the internal circuit disposed in the semiconductor device10. Further, the noise reduction circuit24includes the low pass filter40, the Schmitt circuit42, and the output signal adjusting unit44. Further, the output signal adjusting unit44includes the delay circuit46and the OR circuit48.

In the embodiment, the low pass filter40and the Schmitt circuit42are provided for removing the external turbulent noise superimposed on the oscillation signal input through the input terminal20. When the power source voltage is rapidly fluctuated due to the generation of the external turbulent noise, the Schmitt threshold value H and the Schmitt threshold value L of the Schmitt circuit42follow and fluctuate according to the rapid fluctuation. On the other hand, the potential (the node A) of the input signal of the Schmitt circuit42does not follow the rapid fluctuation. Accordingly, the potential (the node B) of the output signal has the glitch of the L level pulse, thereby inverting the output signal. However, the output signal and the output signal (the delayed signal) delayed by the delay circuit46are input into the OR circuit48. The output signal has the glitch (the inversion) at the timing shifted from that of the glitch of the delayed signal. As a result, the output signal (the oscillation signal) output from the OR circuit48is not inverted and maintains the H level. Accordingly, it is possible to minimize the influence of the power source noise.

In the embodiment, the oscillation signal having the higher frequency that the oscillation signal input into the input terminal20is input into the input terminal20. Further, the oscillation signal input into the input terminal22has more restriction with respect to the delay of the signal. Accordingly, it is possible to apply to the input signal (the oscillation signal) having the strict restriction with respect to the delay of the signal transmission. Further, the glitch is not generated in the output signal of the Schmitt circuit52. Accordingly, it is possible to effectively remove the power source noise relative to the oscillation signal having the high frequency (oscillating at a high frequency).

As described above, in the semiconductor device10in the embodiment, it is possible to improve the noise tolerance with respect to the power source noise causing the fluctuation in the power source voltage through the different processes (the noise reduction circuit24and the noise reduction circuit26) at the input terminal20and the input terminal22according to the oscillation signals thus input.

In the embodiment, the capacitor element C7is disposed between the input terminal and the output terminal of the Schmitt circuit52, and the capacitor element C7has the function of adjusting the potential of the signal input into the Schmitt circuit52. The present invention is not limited to the configuration. Alternatively, for example, the capacitor element C7may be disposed between the input terminal of the Schmitt circuit52and the power source. In this case, with the capacitor element C7, the input signal (the node A) of the Schmitt circuit52fluctuates following the fluctuation of the power source voltage.

In the embodiment, the noise reduction circuit24and the noise reduction circuit26are disposed in the semiconductor device10, so that the noise reduction circuit24and the noise reduction circuit26are configured to remove the noise of the signals (the oscillation signals) input from the external circuit12and the external circuit14disposed in the semiconductor integrated circuit1through the input terminal20and the input terminal22, respectively. The present invention is not limited to the configuration. Alternatively, for example, the noise reduction circuit24and the noise reduction circuit26may be configured to remove the noise of a signal input from an apparatus disposed outside the semiconductor integrated circuit1into the semiconductor integrated circuit1through an external input terminal. Further, it may be configured as the noise reduction device including the noise reduction circuit24and the noise reduction circuit26(refer to the noise reduction device29shown inFIG. 1).

Further, in the embodiment, the semiconductor integrated circuit1, the semiconductor device10, the noise reduction circuit24, and the noise reduction circuit26have the specific configurations for performing the specific operations as an example. The present invention is not limited to the configurations and the operations, and may be modified depending on a situation as long as the scope of the present invention is maintained.

The disclosure of Japanese Patent Application No. 2011-231615, filed on Oct. 21, 2011, is incorporated in the application by reference.