Interleaved correction code transmission

An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units.

BACKGROUND

Optical networks transmit data over optical fiber. In an optical network, multiplexing protocols such as synchronous optical networking (SONET) and synchronous digital hierarchy (SDH) may be used to transfer multiple digital bit streams over the same optical fiber or link. Lasers or light emitting diodes (LEDs) may be used to generate optical signals that carry the digital bit streams.

Bit streams traversing an optical network may pass through transponder switches. Such a switch may, for example, connect to multiple different fiber ports. Bit streams may be received at the switch, converted to an electrical signal, switched to the appropriate output port based on the electrical signal, converted back to an optical signal, and output as an optical signal on the determined output port.

Data transmitted over the optical links in the optical network may be encoded with error correction information. For example, an error-correcting code (ECC) may be added to the data. The ECC may include redundant data that is used to correct transmission errors in the data. If the number of errors experienced during transmission is within the capability of the ECC being used, the receiving transponder switch may use the extra information to discover the locations of the errors and correct the errors.

When a data signal is transmitted over an optical link, errors on the link may tend to occur in groups. For example, a multi-bit error that occurs over four consecutive bits may be more likely than four independent single bit errors. Although ECC information added to data may allow for the correction of single bit and some multi-bit error, at some point, too many errors in a codeword will prohibit correction of the error at the receiver.

SUMMARY

According to one implementation, a device may include a number of input lines, the input lines carrying data; an ECC circuit coupled to the input lines, the ECC circuit supplying a codewords in series, the codewords being generated by the ECC circuit based on the data, each of the codewords including error correction information and a portion of the data; a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply a first data units in parallel, each of the first data units including information from a corresponding one of the plurality of codewords; an interleaver circuit configured to receive the first data units in parallel and output second data units in parallel, each of the second data units including bits from different ones of the first data units; and output lines, each of which supplying a corresponding one of the second data units.

According to another implementation, a device may include an ECC circuit to generate error correction information for sequentially received input data and output sequential ECC codewords, each of the sequential ECC codewords including the received data and error correction information corresponding to the received data; a serial-to-parallel circuit to convert the sequential codewords generated by the ECC circuit to codewords that overlap one another; an interleaver circuit to interleave the overlapping codewords; and optical output lines connected to transmit the interleaved codewords, where consecutive bits transmitted on each of the optical output lines includes bits corresponding to different ones of the sequential codewords.

In another implementation, an ECC device may include input data lines, each of the input data lines receiving serial data in which ECC information is interleaved in the serial data so that multiple sequential bits received on the input data lines are bits corresponding to different ECC codewords, where each ECC codeword includes data and error correction information generated for the data; a serial-to-parallel circuit to convert the received serial data to parallel data; an interleaver to de-interleave the parallel data so that groups of bits within the parallel data include bits from a same one of the different ECC codewords; a parallel-to-serial circuit to receive the de-interleaved parallel data to convert the de-interleaved parallel data to serial data; and an ECC circuit connected to receive the serial data and correct errors in the serial data based on the ECC codewords.

In yet another implementation, an ECC device may include means for generating, based on data received on a plurality of input lines, a plurality of sequential ECC codewords, the plurality of codewords being generated based on the data, each of the codewords including error correction information and a portion of the data. The device may further include means for receiving each of the codewords in succession and supplying first data units in parallel, each of the first data units including information from a corresponding one of the codewords; means for receiving the first data units in parallel and outputting second data units in parallel, each of the second data units including bits from different ones of the first data units; and means for outputting a corresponding one of the second data units

DETAILED DESCRIPTION

Implementations, described herein, may provide for transmission of ECC codewords using an interleaved technique in which a single codeword is transmitted over multiple optical links and where consecutive bits on optical link correspond to different codewords. The interleaving of the codewords may be performed by a serial-to-parallel circuit, interleaver circuit, and parallel-to-serial circuit. By spreading (interleaving) codewords over multiple optical links, a multi-bit error on a link may correspond to single bit errors in multiple different codewords. The interleaved data may thus be more resistant to clusters of multi-bit errors that may tend to occur on a particular optical link.

Exemplary Network

FIG. 1is a diagram of an exemplary network100in which systems and/or methods described herein may be implemented. Network100may include clients110-1and110-2(referred to collectively as “clients110,” and generally as “client110”) and nodes120-1, . . . ,120-8(referred to collectively as “nodes120,” and generally as “node120”). WhileFIG. 1shows a particular number and arrangement of devices, network100may include additional, fewer, different, or differently arranged devices than those illustrated inFIG. 1. Also, the connections between devices may include direct or indirect connections.

Client110may include any type of network device, such as a router, a switch, or a central office, that may transmit data traffic. In one implementation, client110may transmit a client signal (e.g., a synchronous optical network (SONET) signal, a synchronous digital hierarchy (SDH) signal, an Ethernet signal, or another type of signal) to node120. The client signal may conform to any payload type, such as Gigabit Ethernet (GbE), 2xGbE, Fibre Channel (FC), 1GFC, 10 GbE local area network (LAN) physical layer (Phy), 10 GbE wide area network (WAN) Phy, Synchronous Transport Mode 16 (STM-16), STM-64, Optical Carrier level48(OC-48), or OC-192.

Nodes120may be nodes in an optical network, or an optical portion of a network. Nodes120may be connected via optical links. Data traffic may flow from node-to-node over a series of channels/sub-channels forming a path. Any two nodes120may connect via multiple optical links. For bidirectional communication, for example, a first optical link may be used for data traffic transmitted in one direction, a second optical link may be used for data traffic transmitted in the opposite direction, and a third optical link may be used in case of a failure on the first link or the second link.

Each node120may act as, among other things, an optical switching device in which data is received over an optical link, converted to electrical signals, switched based on the electrical signals, and then output, as an optical signal, to an optical link determined by the switching.

Exemplary Node Components

FIG. 2is a diagram of exemplary components of node120. As shown inFIG. 2, node120may include line modules210-1, . . . ,210-Y (referred to collectively as “line modules210,” and generally as “line module210”) (where Y≧1) and tributary modules220-1, . . . ,220-YY (referred to collectively as “tributary modules220,” and generally as “tributary module220”) (where YY≧1) connected to a switch fabric230. As shown inFIG. 2, switch fabric230may include switching planes232-1,232-2, . . .232-Z (referred to collectively as “switching planes232,” and generally as “switching plane232”) (where Z≧1). WhileFIG. 2shows a particular number and arrangement of components, node120may include additional, fewer, different, or differently arranged components than those illustrated inFIG. 2. Also, it may be possible for one of the components of node120to perform a function that is described as being performed by another one of the components.

Line module210may include hardware components, or a combination of hardware and software components, that may provide network interface operations. Line module210may receive a multi-wavelength optical signal and/or transmit a multi-wavelength optical signal. A multi-wavelength optical signal may include a number of optical signals of different optical wavelengths. In one implementation, line module210may perform retiming, reshaping, regeneration, time division multiplexing, and/or recoding services for each optical wavelength. Line module210may also convert input optical signals into signals represented as electrical signals.

Tributary module220may include hardware components, or a combination of hardware and software components, that may support flexible adding or dropping of multiple services, such as SONET/SDH services, GbE services, optical transport network (OTN) services, and FC services. Tributary module220may be particularly used to connect nodes120to clients110. Tributary module220may also convert input optical signals into signals represented as electrical signals.

Switch fabric230may include hardware components, or a combination of hardware and software components, that may provide switching functions to transfer data between line modules210and/or tributary modules220. In one implementation, switch fabric230may provide fully non-blocking transfer of data. Each switching plane232may be programmed to transfer data from a particular input to a particular output. Switching planes232may generally operate by storing data into multi-port digital memories, where data may be read into the digital memories at one port and read out at another port.

As shown inFIG. 2, each of line modules210and tributary modules220may connect to each of switching planes232. The connections between line modules210/tributary modules220and switching planes232may be bidirectional. While a single connection is shown between a particular line module210/tributary module220and a particular switching plane232, the connection may include a pair of unidirectional connections (i.e., one in each direction).

Error Correction Operation of Nodes120

FIG. 3is a diagram conceptually illustrating the use of error correcting codes as performed by a node120or between nodes120. A node may use ECC techniques when transmitting data over switch fabric230to provide error correction over the switch fabric. An exemplary node120-2is shown inFIG. 3as using an ECC technique for sending data over its switch fabric230. In an alternative possible implementation, two nodes, such as nodes120-2and120-3may communicate with one another through a number of optical signals sent over optical channel310, in which the interleaved ECC technique described herein is used to interleave signals sent over multiple links.

Node120-2may include error correction code (ECC) components320-2and320-3, respectively. The ECC components320may be implemented in line modules210and/or tributary modules220. ECC component320-2may operate as an ECC transmitter to receive incoming data signals, add error correction information to the data signals, and transmit the signals over channel230. In practice, each line module210and/or tributary module220may include an ECC component320that includes functionality to implement both transmitting and receiving of ECC data. ECC component320-3may operate as an ECC receiver to receive the data signals, including the error correction information, and remove the error correction information to obtain the original data signals.

In the example ofFIG. 3, three input data signals330are received by ECC component320-2. Consistent with aspects described herein, data bits in the data signals330may be “shuffled” (i.e., interleaved) by ECC component320-2and output as data signals335, where each of data signals335may include bits from different ones of input data signals330. As shown, the three input data signals330may be output as four ECC data signals335. Each of the four ECC data signals335may be transmitted over switch fabric230or over another serial link. After processing by ECC component320-3, the original three serial data signals340may be obtained. To the extent possible based on the ECC being used, bit errors introduced during the transmission over switch fabric230may be corrected by ECC component320-3. Advantageously, by interleaving data bits from the original three data signals over optical channel310, multi-bit errors introduced on the transmission channel may be corrected.

Although the example ofFIG. 3illustrates ECC components that operate on three input data signals and generates four signals for transmission on the optical channel, in other implementations, more or fewer than three input signals and four signals for transmission over the channel may be used. Further, the data bit width of the signals, described as four bits wide in the description that follows, may in alternative implementations, be greater or less than four bits wide.

ECC Component

FIG. 4is a diagram illustrating an exemplary implementation of ECC component320-2. Signals input to ECC component320-2may be successively processed by ECC generation circuit410, serial-to-parallel circuit420, interleaver circuit430, and parallel-to-serial circuit440.

Input signals330may include, as shown in this implementation, three digital signals, each of which may be one or more bits wide. In this example, each input signal330includes a four-bit wide signal. Thus, for each input clock cycle, 12 data bits may be received by ECC component320-2, corresponding to four bits for each of three signals. Four four-bit output signals335may be output by ECC component320-2every clock cycle. Each one of four-bit output signals335may include a bit from four different ECC codewords, where consecutive bits on any of the output signals335may correspond to different codewords.

ECC generation circuit410may receive input signals330and output the input signals along with one or more additional error correcting (ECC) bits. In this example, four ECC bits are generated for each input cycle, resulting in a total of 16 bits output from ECC generation circuit410. A number of possible ECC techniques may be used to generate the ECC bits. For example, parity check codes, Hamming code, Reed-Solomon codes, or other known ECC techniques may be used to generate the ECC bits. The ECC technique used may particularly be a block code technique, in which information is processed on a block-by-block basis. Each “block” of ECC data may include both the original data and the ECC bits for the data. An ECC data block will be referred to as a codeword herein. As used herein, data that “includes” the original data and ECC bits may refer to a codeword in which the ECC bits are simply appended to the original data (i.e., the original data is present in the codeword in its original form) and codewords in which the ECC version of the codeword includes the ECC bits and the original data “mixed” (i.e., the original data may not be evident in the codeword by visual inspection until the codeword is decoded using the ECC technique that was used to encode the codeword).

FIGS. 5A and 5Bare diagrams illustrating exemplary implementations of ECC generation circuit410in additional detail.FIG. 5Ais a block diagram illustrating operation of ECC generation circuit410.FIG. 5Bis a diagram illustrating one possible implementation of ECC generation circuit410using parity check codes.

InFIG. 5A, the input signals330are labeled as signals D0, D1, and D2, respectively. The output of ECC generation circuit410includes output signals O0, O1, and O2, which may be copies of input signals D0, D1, and D2. Additionally, a signal labeled P is also output from ECC generation circuit410. P may include the ECC data bits. The set of O0, O1, O2, and P may be referred to as a single codeword, labeled as codeword515. Codeword515, after transmission over the channel (e.g., copper backplane or optical channel), may be examined and the values in P may potentially be used to determine whether there are errors in O0, O1, and/or O3, and potentially to correct the errors. As is further shown inFIG. 5A, codeword515may include four bits corresponding to D0(group520-0), four bits corresponding to D1(group520-1), four bits corresponding to D3(group520-2), and four bits corresponding to the ECC data bits (group520-3).

FIG. 5Bis a diagram illustrating an exemplary implementation of ECC generator circuit410using a parity check operation. ECC generator circuit410may include exclusive-OR (XOR) circuits530and540. XOR circuit530may perform an XOR operation on corresponding bits in D0and D1. Thus, the first bit of D0may be XORed with the first bit of D1, the second bit of D0may be XORed with the second bit of D1, etc. The four output bits of XOR circuit530may be input to XOR circuit540and XORed with corresponding bits of D2. Thus, the first output bit from XOR circuit530may be XORed with the first bit of D2, the second output bit from XOR circuit530may be XORed with the second bit of D2, etc.

Successive codewords output from ECC generation circuit410may be converted by serial-to-parallel circuit420into a 16-bit parallel output units that each includes four-bit groups from four successive codewords.FIG. 6is a diagram conceptually illustrating exemplary operation of serial-to-parallel circuit420.

Each clock cycle, a codeword610-0through610-3, may be received by serial-to-parallel circuit420. As previously mentioned, each codeword, such as codeword610-0, may include four-bit groups from each data signal D0, D1, D2, and the ECC data P. Successive codewords are denoted by subscript numbering inFIG. 6, so the first codeword output from ECC generator circuit410is represented with the subscript 0, the second codeword with the subscript 1, and so on. After serial-to-parallel conversion, each 16-bit output may include successive data corresponding to a single signal D0, D1, D2, or P. Each 16-bit output is labeled inFIG. 6as “mixed” or “overlapped” codewords620-0through620-3. As can be seen, each mixed codeword620may include groups from four different codewords610. The original codewords610are staggered in time.

One particular possible implementation of serial-to-parallel circuit420will be described in more detail below with reference toFIGS. 10-12.

Referring back toFIG. 4, interleaver circuit430may operate on mixed codewords620to rearrange the bits of each group so that each four-bit output group of interleaver circuit430contains one bit from each input group.FIG. 7is a diagram illustrating an exemplary implementation of interleaver circuit430.

As shown inFIG. 7, for each four-bit group of data, such as group710(e.g., corresponding to D00inFIG. 6), each of the four bits are interleaved to a different output group. More specifically, interleaver circuit430may group bits based on the order of the bits in a codeword, so bit zero of four successive codewords may be grouped, bit one of the four codewords may be grouped, and so on. In this manner, each output group may include bits from different input groups.

Although interleaver430is shown inFIG. 7as a hardwired re-routing of groups of data, in other possible implementations, other interleaving techniques could be used. For example, switching memory could be used to interleave data.

The parallel interleaved data output from interleaver circuit430may next be processed by parallel-to-serial circuit440. Parallel-to-serial circuit440may generally operate to convert the parallel groups of interleaved data to serial groups of data.FIG. 8is a timing diagram conceptually illustrating exemplary operation of parallel-to-serial circuit440.

Inputs to parallel-to-serial circuit410are illustrated inFIG. 8in columns810-0through810-3. As shown, column810-0, for example, includes data from signal D0. Due to the interleaving, each row (group) in column810-0may include bits from four successive samples of D0, represented by the subscript notation “0-3”. Because each successive time sample may correspond to a new ECC codeword, each group in column810-0therefore includes a bit from four different codewords. Similarly, for columns810-1,810-2, and810-3, each group in these columns includes a bit from four different codewords.

After operation of parallel-to-serial circuit440, each column810may be transposed and the data units in each column arranged serially. Thus, as shown, column810-0may be arranged as row820-0, column810-1may be arranged as row820-1, column810-2may be arranged as row820-2, and column810-3may be arranged as row820-3. Each row may be transmitted over a serial link in channel230. Advantageously, because each group of data within a row includes bits from different codewords, multi-bit contiguous errors on the optical link may be spread among multiple codewords, thus potentially allowing for the correct reconstruction of all of the codewords using the ECC technique. For instance, in the example implementation discussed, where each group of data includes four bits, corresponding to four different codewords, an N-bit contiguous error on the optical link may correspond to an N/4 bit error in each codeword that be reconstructed at the receiving ECC component320-3.

FIG. 9is a diagram illustrating an exemplary implementation of ECC component320-3. ECC component320-3may generally operate to process the data received over channel230by reconstructing codewords610and using the ECC technique to determine, and possibly correct, codewords with errors.

ECC component320-3may include circuits similar to those in ECC component320-2. As shown inFIG. 9, ECC component320-3may include serial-to-parallel circuit920, interleaver circuit930, parallel-to-serial circuit940, and ECC processing circuit950. Serial-to-parallel circuit920may receive the signals received over optical channel310and convert the serial streams into 16-bit parallel interleaved codewords, each corresponding to a particular data signal O0, O1, O2, or P. After processing by serial-to-parallel circuit920, the interleaved parallel codewords may be similar to the interleaved codewords shown in columns810(FIG. 8). Interleaver930may then interleave the interleaved codewords to effectively de-interleave the codewords. Interleaver circuit930may be implemented similarly to interleaver circuit430. At this point, the parallel codewords may be similar to the mixed codewords620(FIG. 6). Parallel-to-serial circuit940may next process the mixed codewords to obtain codewords similar to codewords610(FIG. 6). At this point, codewords610may be in the original form generated by ECC generation circuit410and may be processed by ECC processing circuit940. ECC processing circuit950may, based on the ECC technique being used, examine the ECC bits for each codeword to determine if the codeword contains errors. Some ECC techniques additionally allow errors to be corrected within the codeword.

Serial-to-parallel circuits420and920may be implemented using a number of possible parallelization techniques. One example of a circuit that may be used to efficiently perform the serial-to-parallel conversion will now be described with reference toFIGS. 10-12.

FIG. 10is a diagram illustrating an exemplary serial-to-parallel circuit1000. For simplicity, serial-to-parallel circuit1000will be described as receiving four one-bit serial data streams and converting four successive data bits on each stream to a single four-bit parallel output. It can be appreciated that the width of each input data stream or the number of input data streams may be changed in different implementations. In the previous exemplary implementation of serial-to-parallel circuits420and920, for instance, the serial-to-parallel circuits were described as operating on four four-bit wide data streams.

Serial-to-parallel circuit1000may include a number of delay elements1010, a rotator1020, and 4-deep registers1030. Serial-to-parallel circuit1000may operate on input data streams1005-0through1005-3.

Data streams1005-0through1005-3may be initially delayed by delay elements1010. Each of delay elements1010may be implemented as, for example, a capacitive delay element, a digital latch, or another delay element. Each delay element may delay its input one clock cycle. As shown inFIG. 10, data stream1005-0is not delayed, data stream1005-1may pass through three delay elements1010(i.e., three clock cycles), data stream1005-2may pass through two delay elements1010(i.e., two clock cycles), and data stream1005-3may pass through one delay element1010(i.e., one clock cycle). In this manner, incoming data bits for different data streams are offset from one another when reaching rotator1020.

Rotator1020may receive, in each clock cycle, the group of data bits (e.g., four bits in the illustrated implementation) from signal lines1005-0through1005-3. Rotator1020may generally operate to “rotate” its input based on a rotate count value. In rotating its input, rotator1020may switch signals on the four input lines to various ones of the four output lines. Which input lines get switched to which output lines may depend on the rotate count value.

FIG. 11is a diagram illustrating an exemplary implementation of rotator1020. The four input signals received by rotator1020may be input to a first multiplexer1110. The output of first multiplexer1110may be output to second multiplexer1120. Multiplexers1110and1120may each be eight input, four output (8:4) multiplexers. Multiplexers1110and1120may each receive the eight inputs, replicated into two groups of four, and output four signals (one of the two groups) based on an input control line. The input control line for multiplexer1110may be the most significant bit (MSB) of a two-bit output of rotation counter1140and the input control line for multiplexer1120may be the least significant bit (LSB) of the two-bit output of rotation counter1140. Rotation counter1140may be implemented as a two-bit counter. In one implementation, multiplexers1110and1120may be implemented using four separate 2:1 multiplexers (e.g., controlled switches).

Table I, below, illustrates a rotation operation as performed by rotator1020. In Table I, assume the input signals to rotator1020are labeled “a”, “b”, “c”, and “d”. The output, rotated signals, for each of the four rotation count values are shown in the table. For example, when the rotation count equals two (i.e, MSB=1 and LSB=0), the output signals would be “c”, “d”, “a”, “b”. As can be observed in Table I, over the course of the rotation count, the signal at any particular input location is switched to be output once at each of the output locations (i.e., the input at “a” is variously output at “a”, “d”, “c”, and “b”; the input at “b” is variously output at “b”, “a”, “d”, and “c”, etc.).

Returning toFIG. 10, 4-deep registers1030may receive the values output from rotator1020. Each of 4-deep register1030may include four registers to store four parallel bits. At each clock cycle, each 4-deep register1030may output one bit, providing, in total, a four-bit data unit. The four-bit data unit represents four parallel bits from one of input signal lines1005.

FIG. 12is a diagram illustrating an exemplary implementation of one of 4-deep registers1030. As shown, each of 4-deep registers1030may include four 1-bit registers1205, each connected to one of the input signal lines and a multiplexer1210. Multiplexer1210may include a 4:1 multiplexer that selects one of the outputs of the 1-bit registers1205to output. 1-bit registers1205and multiplexer1210may be controlled by control logic1215based on the output of rotation counter1140. In particular, control logic1215may, in each clock cycle, enable one of 1-bit registers1205to write its input data bit. Control logic1215may simultaneously control multiplexer1210to select the output of another of 1-bit registers1205to output from 4-deep register1030.

Collectively, each of the four 4-deep registers1030may be controlled to output four parallel bits from one of signal lines1005-0through1005-3.

Parallel-to-serial circuits440and940may be implemented using a number of possible serialization techniques. One example of a circuit that may be used to efficiently perform the parallel-to-serial conversion will now be described with reference toFIG. 13.

Parallel-to-serial circuits440and940generally operate to reverse the parallelization performed by serial-to-parallel circuits420and920.

FIG. 13is a diagram illustrating an exemplary parallel-to-serial circuit1300. For simplicity, parallel-to-serial circuit1300will be described as serializing a four-bit wide data stream and converting the four-bit wide data stream into four successive bits in each of four output signals. It can be appreciated that the width of the input data stream or the number of output data streams may be changed in different implementations. In the previous exemplary implementation of parallel-to-serial circuits440and940, four four-bit wide data streams were described. Parallel-to-serial circuit1300may include 4-deep registers1310, rotator1320, and delay elements1330.

A data unit input to parallel-to-serial circuit1300may be input to 4-deep registers1310. Each of 4-deep registers1310may receive one of the four bits in the data unit. Each of 4-deep registers1310may also output one of its stored bits. The outputs may be rotated by rotator1320, delayed by delay elements1330, and output as output data streams1340-0through1340-3.

As with delay elements1010, each of delay elements1330may be implemented as, for example, a capacitive delay element, a digital latch, or another delay element. Each delay element1330may delay its input by one clock cycle. As shown inFIG. 13, output data stream1340-0may pass through three delay elements1330(i.e., delayed three clock cycles), output data stream1340-1is not delayed, output data stream1340-2may pass through one delay element1330(i.e., one clock cycle), and output data stream1340-3may pass through two delay elements1330(i.e., two clock cycles).

CONCLUSION

ECC codewords transmitted over optical links may be interleaved before being transmitted over the optical links. The interleaved data may be more resistant to clusters of multi-bit errors that may tend to occur on a particular optical link.

Also, certain portions of the implementations have been described as “components” that perform one or more functions. The term “component,” may include hardware, such as a processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), or a combination of hardware and software.

Further, while implementations have been described in the context of an optical network, this need not be the case. These implementations may apply to any form of circuit-switching network.