Metal patterning for internal cell routing

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The second supply metal tract is wider than the first supply metal tract. The first supply metal tract has a thickness substantially same as the first pattern metal layer. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

BACKGROUND

Industry trends have led to a continuing increase in the number of transistors formed on a given substrate. Over the last four decades the semiconductor fabrication industry has been driven by a continual demand for greater performance (e.g., increased processing speed, memory capacity, etc.), a shrinking form factor, extended battery life, and lower cost. In response to this demand, the industry has continually reduced a size of semiconductor device components, such that modern day integrated chips may comprise millions or billions of semiconductor devices arranged on a single semiconductor die. Accordingly, the metal pitch of a semiconductor device has decreased to accommodate smaller transistors. A conventional semiconductor device includes a substrate, a circuit above the substrate, and metal lines that interconnect components of the circuit and that comply with electromigration (EM) rules.

EM is a phenomenon in which ions/atoms of a metal line of a semiconductor device migrate from a first region to a second region of the metal line and involves formation of voids at the first region of the metal line, which may cause an open circuit in the semiconductor device, and accumulation of the ions/atoms at the second region of the metal line, which may cause a short circuit in the semiconductor device. EM rules are established limiting a current flowing through a metal line to limit EM to an acceptable level.

DETAILED DESCRIPTION

A semiconductor device cell may include transistors with metal pattern structures above the transistors. The metal pattern structures include metal routing resource lines, e.g. for interconnecting polysilicon structures, as well as power metal planes or lines for providing power to the cell components. A cell may have multiple pattern structures. For example, a first metal pattern structure may be formed over cell transistors, and a second metal pattern structure may be formed over the first metal pattern structure. A transistor polysilicon structure extends transverse to the resource lines of a first metal pattern structure and a second metal pattern structure. Those resource lines may be parallel to each other, or perpendicular to each other in distinct parallel planes.

As transistor density increases, interconnection metal patterning is scaled to provide sufficient power and signal routes, or resource routes, to the increased number of transistors in a given space. As the metal pitch decreases to accommodate smaller transistors, the overlaying issues between successive exposures and the cost of lithographic methods capable of patterning the metal pattern structures have become key obstacles in mass production. Such interconnection scaling must consider the effect of a decreasing cell height. As the cell height decreases, the pitch of the first metal patterning will fail to provide enough internal cell routing resources. Thus, in complicated standard cells, the minimum area cannot be achieved, which affects the die area.

As technology scales, the design area is an increasingly important factor in evaluating cost. One factor that can be reduced when scaling is to reduce a cell height, causing a corresponding decrease in cell area. But, a competing design technique is to increase the cell height or cell pitch when the first metal patterning fails to provide enough signal connection.

The present disclosure provides exemplary device(s)/method(s) for providing sufficient power and routing resources while accommodating a shorter cell height. It is typical for a first metal pattern to use symmetric power/ground structures, that is the power and ground structures have a same width. But, disclosed embodiments include a metal patterning structure that provides additional cell routing resources in the first metal pattern structure by relying on asymmetric power/ground structures. Similarly, second metal pattern structures having asymmetric power/ground structures may be formed and employed. In each case, the power/ground structures may be a first metal. In embodiments an asymmetric power/ground structure has a power or ground structure that has the same width as internal cell routing resource lines, and thus a portion of the power or ground structure is utilized as an internal cell routing resource. In order to mitigate IR/EM effects, a second metal is employed to interconnect power/ground structures within a cell. The second metal may be employed to interconnect power/ground structures within a first metal pattern or a second metal pattern structure, but also second metal may be employed to interconnect power/ground structures of the first metal pattern structure and the second metal pattern structure. Additionally, in embodiments, a power/ground structure relying on the third metal are employed to mitigate IR/EM effects by coupling narrower power metals in adjacent metal pattern structures.

As will be described hereafter, the present disclosure is based on a technique for decreasing the width of power metal planes in order to provide additional local routing recourses. By decreasing the width of one or more power/ground structures, additional resource metal lines, or routes, are provided within the same cell height. Additional resource metals may include both routing resources and power lines. The present disclosure is further based on a technique for decreasing the width of power/ground structures in order to provide additional power/ground structures. By decreasing the width of a power/ground structure, additional power/ground structures are accommodated within the same cell height. Additional power/ground structures having a same width as resource metals may include additional resource metal lines or routes.

A semiconductor cell interconnection metal pattern structure may be a first metal pattern structure or second metal pattern structure as discussed above. Metal pattern structures include two power/ground structures between which is a plurality of layers of metal resource lines or tracts. Metal resources include internal cell resource lines, or routes, for interconnecting transistor elements within the cell. In a conventional semiconductor cell interconnection metal pattern structure the power/ground structures are symmetric, meaning that the metal lines or planes or tracts of the power structure have the same width as the metal lines or planes or tracts of the ground structure.

FIG. 1illustrates an embodiment of a semiconductor cell interconnection metal pattern structure100in accordance with the present disclosure. Metal pattern structure100may be a first metal pattern structure or a second metal pattern structure as discussed above. Metal pattern structure100includes asymmetric power/ground structures102aand102b. While102ais labeled power and102bis labeled ground, depending on the design of the semiconductor cell, the purpose of102aand102bmay be interchanged. Between the asymmetric power/ground structures102a,102bare a plurality of layers of metal resources103that may include internal cell resource lines or routes for interconnecting transistor elements within the cell. Also between asymmetric power/ground structures102a,102bis an additional power/ground structure layer104that includes an additional metal resource105for local in-cell routing and additional power/ground structures106aand106b. Structures102aand104have a same width, or substantially the same width, as the metal resources103. In this way, interconnection metal pattern structure100may have the same height as a conventional interconnection metal pattern while including additional resource metal, e.g.105.

FIG. 2illustrates two semiconductor interconnection metal pattern structures210and220. Metal pattern structure210is an exemplary odd metal tract structure in accordance with the present disclosure and includes asymmetric power/ground structures212having one power/ground tract and power/ground structure214having two power/ground tracts. Power/ground structure214comprises two metal layers each having a width substantially the same as the width of an individual resource metal layer within resource metal layers213, and which is less than the width of power/ground structure212. Power/ground structure214may also include additional metal resource tracts within either of power ground tract. Metal pattern structure220is an exemplary even metal tract structure in accordance with the present disclosure and includes asymmetric power/ground structures222having one power/ground tract and power/ground structure224having three power ground tracts. Power/ground structure224comprises three metal layers each having a width substantially the same as the width of an individual resource metal layer within resource metal layers223, and which is less than the width of power/ground structure222. Power/ground structure214may also include additional metal resource tract.

Both of the structures210,220provide distinct benefits over conventional structures. For example, a conventional structure provides strong power and ground coupling, but lacks internal routing resources within the cell. Whereas, the odd metal tract configuration structure210includes two additional layers for including additional metal resource tracts for routing, while the even metal tract configuration structure220includes three additional layers for internal metal resource tracts. These benefits are gained in both210and220these at the expense of possible IR/EM issues, and the additional power/ground tracts occupy spaces that could be devoted to additional routing resources.

FIG. 3illustrates an exemplary semiconductor cell interconnection metal pattern structure300in accordance with the present disclosure. Structure300may be a 1stmetal pattern, e.g. M0, structure formed over transistors for providing signal routing between transistor elements. Structure300includes an asymmetric power structures302a/302bin accordance with this disclosure, thereby allowing additional metal resource lines305. Structure300includes multiple metal patterning layers interconnecting multiple transistor polysilicon gate structures307for applying routed signals within a semiconductor cell to transistor elements. As depicted, various parameters overlaying structure300for characterizing the features of structure300. Structure300includes a ground structure302a, a power structure302b, additional power structure304, a plurality of metal resource tracts303, and an additional metal resource tract305. In embodiments, power and ground are interchangeable such that302aprovides power and structure302bprovides ground.FIG. 3also illustrates two polysilicon structures307and two follow pins308. Follow pins308connect power/ground structures, e.g.304,302b, together as much as possible. Follow pins308may be of a first metal or a second metal, in embodiments a second metal structure is referred to as a M1structure.

Features of metal pattern structures, such as an M0patterning or metal pattern structure300, may be characterized by a number of different parameters. Structure300has a height Hcell. The power/ground structures302a,302b, and304each have a width; ground structure302ahaving a width Wground, while power structures302b,304have a width Wpower. The metal resource lines303have a width W1st_metaland the additional metal resource line or tract has a width Wadd. The polysilicon structures307define a pitch, Ppoly, and similarly the follow pins308define a pitch, P2ndpin. Additionally, a follow pin defines a length L2ndpin. A semiconductor structure in accordance with this disclosure, e.g. structure300, has an asymmetric power/ground structure meaning that is Wground≠Wpower.

FIG. 4illustrates an exemplary semiconductor cell interconnection metal pattern structure400. When a first metal pattern has sufficient resource lines, such that some metal resource lines may be devoted to power metal, an in cell follow pin can be used within the cell to mitigate EM and IR issues. But, when additional metal resource lines are needed within a cell, metal power resources outside a cell may be used to mitigate EM and IR issues, for example, by coupling two or more thin power metals together using a pillar or strap. Metal pattern structure400illustrates these various techniques.

Metal pattern structure400includes a first interconnection metal pattern structure410and second interconnection metal pattern450. Metal pattern structures410and450may each be a first metal or an M0metal pattern structure. The first interconnection metal pattern structure410includes a power metal402a, a ground metal402b, metal resource lines403, and an additional metal resource line404. The second interconnection metal pattern structure450includes a power metal452a, a ground metal452b, metal resource lines453, an additional metal resource line455, and an additional power metal456sharing the same layer as additional metal resource line455. Semiconductor interconnection metal pattern structure400includes an in-cell follow pin470coupling, or interconnecting, power metal402awith power metal452aand with a third power metal480that may be formed in a layer that extends to lengths external to both structures410and450, and may be formed in a layer a portion of which is shared by structures410and450, and the third power metal480may be formed in a layer that is separate and distinct from the layers of structures410and450. Semiconductor interconnection metal pattern structure400also includes a second in-cell follow pin472coupling, or interconnecting, the power metals402a,452a,480with the additional power resource metal456.

When the metal resource tracts, e.g.403,453, are sufficient for desired in-cell routing (e.g., to interconnect polysilicon structures (not illustrated inFIG. 4)) the in-cell follow pins are utilized, for example as in structure410. Also, power structures external to a semiconductor cell may be employed. For example, semiconductor interconnection metal pattern structure400also includes pillar structure474, that is external to both structures410and450, interconnecting power metals402a,452a, and480. As illustrated here, pillar structure474is a single pin pillar structure. A strap structure476may also be employed to connect power metals402a,452a,480to other metal power structures478within a semiconductor device, but external to a particular cell. In embodiments, the metal interconnection pattern structures, including power/ground structures, e.g.402a,402b,452a,452b,456, and resource tracts/lines, e.g.403,453,455, may be of a first metal, e.g. M0; the follow pins, pillar structures, and strap structures may be of a second metal, e.g. M1; and the additional power structures478,480may be of a third metal, e.g. M2. In alternative embodiments, strap structure476is employed to couple power/ground metals that are disposed distally from each other, e.g. power/ground metal402band452b.

In embodiments, employing asymmetric power/ground metals having different widths enables additional space within the cell for additional metal resources, such that a power ground structure may have an even number or an odd number of layers. Additional metal resources may be formed within an added metal resource layer, or alternatively metal resource lines may be formed within a thinner power metal layer.FIG. 5illustrates exemplary even-tract first metal structures500and550. Each even-tract first metal structure includes an even number of power/ground structure layers. Structure500has a height of 1×Hcelland may be an interconnection structure for transistors comprising an AND/OR/NOT device and having polysilicon structures507adefining a pitch. Structure500includes first metal power/ground structures502a,502band resource tracts503. As illustrated first metal power/ground structure502ais voltage source source (VDD) and first metal power/ground structure502bis voltage drain drain (VSS), but in other exemplary embodiments of structure500VSS and VDD may be exchanged such that structure502awould correspond to VSS and structure502bwould correspond to VDD. Even-tract metal structure550has a height of 2×Hcelland may be an interconnection structure for transistors comprising a flip-flop and having polysilicon structures507bdefining a pitch. Structure550includes first metal power/ground structures512a,512b,552a,552band556. As illustrated structures512a,552a, and556provide VDD while512b,552bprovide VSS, but in other exemplary embodiments of structure550VSS and VDD may be exchanged such that structures512a,552a, and556provide VSS and512b,552bprovide VDD.

In both exemplary even-tract embodiments structures500,550have characteristic parameters assuming Wground<Wpower. In each structure500,550there are an even number of power/ground structures502a,502bin structure500and512a,512b,552a,552bin structure550. In structure550, power metal512alayer includes additional resource metal line555. In exemplary structures500,550, Hcell is between approximately 3*Wpowerand approximately 3*Wpower. And Wground≠Wpower, but instead Wpoweris between approximately 1.5*Wgroundand 2.5 Wground, and the width of the resource tracts, W1st_metal, is between approximately 1*Wpowerand approximately 2.5*Wground. Similarly, the width of the additional resource tracts555, Wadd, is approximately 1*Wgroundand approximately 2.5*Wground. As a result of the asymmetric power structures, each of structures500and550may suffer from EM effects and an IR drop without additional enhancement.

In order to address the EM/IR effects that may arise in structures500and550as a result of their asymmetric power structures, enhanced power coupling features are employed.FIG. 6illustrates enhanced power coupling features for mitigating EM effects and preventing an IR drop in exemplary in even-tract structures500and550. Structure500employs a second metal pillar pin structure568for coupling power/ground metal structure502ato a power/ground metal structure622that external to the structure500. In the exemplary embodiment illustrated, pillar pin structure568comprises a dual pin674second metal structure. Also, structure550includes a short second metal follow pin676under structure674for coupling resource lines. Structure550employs a series of single pin pillar structures672in order to couple power/ground structures512a,552a, and556of two metal structures. Second metal single follow pin structures672couple the metal power/ground lines that are disposed proximate to each other (as opposed to512b,552bwhich are disposed distal to each other). Second metal follow pins672define a pitch P2ndpinand a length L2ndpin. Also depicted is a pair of polysilicon structures607defining a pitch Ppoly. P2ndpinis between approximately 1*Ppolyand approximately 24*Ppoly, and L2ndpinis between approximately 0.2*Hcelland approximately 0.5*Hcell.

To mitigate the IR/EM effects to within acceptable levels second metal pillar structures can be employed in an even-tract embodiment for coupling to power/ground structures external to a cell.FIG. 7illustrates exemplary embodiments of pillar power structures employed in an even-tract first metal interconnection pattern structures, which may be exemplary structure500or550. Pillar power structure700includes pillar structures668, each including two pillar pins674, coupled to a power network metal622. Dual pin pillar structures668define a pitch P2pillarthat is between approximately 48*Ppolyand approximately 60*Ppoly. Pillar power structure750includes pillar power structures768, each including single pillar pins, coupled to power network722. Single pin pillar structures768define a pitch P1pillarthat is between approximately 24*Ppolyand approximately 30*Ppoly. Each pillar power structure700,750additionally include a strap structure702a,702bthat couples to a power/ground structure corresponding to ground network as illustrated. In both cases, the length of the 2ndmetal pillar pins, in a single or dual pillar pin configuration, is between 0.2*Hcelland 0.5*Hcell. In each of structures700,750the designation of power and ground for the pillar structure power networks622,722and the strap structures702a,702bmay be freely interchanged as needed depending on design considerations, without modifying the pitch defined by the one pin or two pin pillar structures above.

An even-tract power structure is suitable for interconnecting transistors over which the structures depicted inFIG. 8are formed.FIG. 8illustrates another exemplary embodiment of an even-tract structure formed of first metal power structures802a,802b; second metal power structures804; and third metal power structure852. The depicted exemplary even power metal tract structure is shown in two portions800and850for ease of depiction. Portion800illustrates the first metal power structures802a,802band second metal804. The exemplary first power metal tract structure is depicted interconnecting transistors in a number of cells corresponding to AND/OR/NOT devices820and a flip flop device822. The first metal power structure802acomprises two first power lines802acoupled together via pillar structures806as well as via second metal follow pins808. The first metal power structure802ais further coupled to a second metal resource line810within cell822which is thereby also used for VDD. Each tract of first metal power structure802adefines a width W1st_metal_power. The first metal power structure further includes two first metal power structures802b, labeled VSS. The first metal power structures802bare coupled together via second metal power straps804. A third metal power structure852is further coupled to first metal power structures by pillar structures806and similarly internal metal resource tract810is coupled to third metal power852by in-cell follow pins808. The third metal power strap852defines a width W3rd_metal_powerthat is between approximately 1.5*Wfirst_metal_powerand approximately 3*Wfirst_metal_power.

In embodiments, employing asymmetric power/ground metals having different widths enables additional space within the cell for additional metal resource layers, such that a power ground structure may have an odd number of layers. Additional metal resources may be formed within an added metal resource layer, or alternatively metal resource lines may be formed within a thin power metal layer.FIG. 9illustrates exemplary odd-tract first metal structures900and950. Each odd-tract first metal structure900,950includes an odd number of power/ground structure layers, e.g.902a,902b,902cor952a,952b,952c,962a,962b. Odd-tract structure900is a single height embodiment and has a height of 1×Hcelland may be an interconnection structure for transistors comprising an AND/OR/NOT device and having polysilicon structures defining a pitch. Structure900includes first metal power/ground structures902a,902b,902cand resource tracts903. As illustrated first metal power/ground structures902aand902bis VDD and first metal power/ground structure902cis VSS, but in other exemplary embodiments of structure900VSS and VDD may be exchanged such that structures902a,902bwould correspond to VSS and structure902cwould be VDD.

Odd-tract first metal structure950is a double height structure having a height of 2×Hcelland may be an interconnection structure for transistors comprising a flip flop and having polysilicon structures defining a pitch. Structure950includes first metal power/ground structures952a,952b,952c,962a,962band956, where the tract layer including952cand956also includes an additional routing resource955. As illustrated structures952a,952b, and956provide VDDwhile structures962a,962bprovide VSS, but in other exemplary embodiments of structure950VSSand VDDmay be exchanged such that structures952a,952b, and956provide VSSand962a,962bprovide VDD. In both exemplary odd first metal tract embodiments structures900,950have characteristic parameters, assuming Wground<Wpower. In each structure900,950there are an odd number of first metal power tract layers corresponding to952a,952b,952c,962a, and962b, where structure956is associated with the same layer as952c. In the embodiments900,950depicted inFIG. 9, Hcellis between approximately 3*Wpowerand approximately 6*Wpower. And Wground≠Wpower, but instead Wpoweris between approximately 1.5*Wgroundand 2.5 Wground. The width of the resource tracts903,953, W1st_metal, is between approximately 1*Wgroundand approximately 2.5*Wground. Similarly, the width of the additional resource tracts955, Wadd, is approximately 1*Wgroundand approximately 2.5*Wground. As a result of the asymmetric power structures, odd-tract structures have additional routing resources, but as each of structures900and950may suffer from EM effects and an IR drop without additional enhancement.

In order to address the EM/IR effects that may arise in structures900and950as a result of their asymmetric power structures, enhanced power coupling features are employed.FIG. 10illustrates enhanced power coupling features for mitigating EM effects and preventing an IR drop in exemplary odd-tract structures900and950. Structure900employs a second metal in-cell follow pin structure1068for coupling power/ground metal structures902aand902bresulting in a combined power/ground structure1002. In the exemplary embodiment power ground structure1002provides VDD to structure1000. Structure950employs in-cell second metal follow pins1072,1074in order to couple power/ground structures952a,952b, and956to form a combined power/ground structure1052. In-cell second metal follow pins1072and1074define a pitch P2ndpinand second metal follow pin1072defines length L2ndpin1while second metal follow pin1074defines a second length L2ndpin2. Also depicted is a pair of polysilicon structures1007defining a pitch Ppoly. In embodiments, P2ndpinof structure950is between approximately 1*Ppolyand approximately 24*Ppoly, and L2ndpin1and L2ndpin2are each between approximately 0.2*Hcelland approximately 1*Hcell. The L2ndpin1and L2ndpin2connect the power/ground1052together as much as possible. The second metal follow pins1068,1072,1074should connect each of first metal VDD (or each first metal of VSS in an alternative embodiment interchanging VSS and VDD as discussed above).

Additional techniques may be employed in an odd-tract configuration for mitigating EM/IR effects in the resulting structure. For example second metal structures outside a cell can be employed to couple first metal power/ground lines together.FIG. 11illustrates power structure enhancements1100incorporating first metal power structures1152. For example, first metal power structure1152may be extended portions of structure1052. In order to couple all the power metal tracts, second metal power straps1102may be employed outside of the cell boundary. Second metal power strap structures1102are formed to define a pitch P2nd_metal_powerthat is between approximately 4*Ppolyand approximately 30*Ppoly.

An odd-tract power structure is suitable for interconnecting transistors over which the structures depicted inFIG. 12are formed.FIG. 12illustrates an exemplary embodiment of an odd first power metal tract structure and is formed of layers1252a,1252band a layer including distinct lines1253,1254and1255. Thus, the odd-tract structure includes an odd number of first metal layers depicted as providing VDD, first metal structures1202aand1202bdepicted as providing VSS; second metal power structures1204aand1204bforming VDD power straps for coupling each of power metal lines of1252a,1252b, and1253,1255, and a third metal power metal1260also providing VDD. Each of the depicted VDD metals, including layers1252a,1252band the layer including1253,1255and metal1260, are coupled together via second metal straps1240aand1240b. The depicted exemplary odd-tract power metal structure is shown in two portions1210and1250for ease of depiction. Portion1210illustrates the first metal power structures1202a,1202b,1252a,1252b,1253,1255, and second metal1204a,1204b. The exemplary illustrated odd-tract first power metal structure1200is depicted interconnecting transistors in a number of cells corresponding to AND/OR/NOT devices and a flip flop device. The first metal power structure including1252a,1252b,1253,1255comprises three first metal power layers coupled together via in-cell follower pins1222,1224,1226,1228as well as via second metal power straps1204a,1204b. Distinct metal line1254remains uncoupled to the first metal power structure including1252a,1252b,1253,1255so that it may be utilized as an additional metal resource route, or resource tract. Each tract of first metal power structure including1252a,1252b,1253,1255defines a width W1st_metal_power. The first metal power structure further includes two additional first metal power structures,1202aand1202b, depicted as VSS. A third metal power structure1260is further coupled to first metal power structures by the in-cell follower pins1222,1224,1226,1228. The third metal power strap1260defines a width W3rd_metal_powerthat is between approximately 1.5*Wfirst_metal_powerand approximately 3*Wfirst_metal_power.

FIG. 13depicts an example flow chart of operation1300for forming a semiconductor device or structure. The process ofFIG. 13is relevant to many structures. The process is described here with reference toFIGS. 5, 6, 9, 10, and 12for ease in understanding. As shown inFIG. 13, at1301a first supply metal layer, such as supply metal layer512b,902c,962a, or1202b, is formed. A first supply metal layer may be formed of a first metal. The first supply metal layer may be a power supply or a ground supply layer. At1302, a metal pattern layer is formed over the first supply metal layer and includes a plurality of distinct metal lines. A metal pattern layer may be, for example, a layer including lines512a,555,556, or952c,955,956, or1253,1254,1255. The metal pattern layer is formed to a width less than the width of the first supply metal layer. The lines of the metal pattern layer may also be formed of a first metal. A second supply metal layer is formed at1303such that the metal pattern layer lies between the first supply metal layer and the second supply metal layer. The second supply metal layer, such as layers552a,952a, and1252a, also has a width that is less than the first supply metal layer, thus resulting in asymmetric power structures. In embodiments, the second supply metal layer has substantially the same width as the metal pattern layer. In other embodiments, the width of the second supply metal layer is less than or between the width of the metal pattern layer and the first supply metal layer. At1304, a follow pin is formed within the semiconductor structure or device such that it couples the second supply metal layer to one of the distinct lines of the first metal pattern layer such as lines512a,556,952c,956, or1253,1255, such that the coupled lines provide the same supply as the second supply layer. In embodiments the follow pin is formed of a second metal different from the first metal. In embodiments uncoupled metal pattern layer lines, such as555,955,1254may be used as additional first metal resource lines.

In one embodiment a semiconductor device cell comprises a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. In variations, the second supply metal tract may be wider than the first supply metal tract. The first supply metal tract may have a thickness substantially same as the first pattern metal layer. In some aspects a second pattern metal layer is disposed between the first supply metal tract and the second supply metal tract, where the second pattern metal layer also includes a second internal route, and a second power route, such that the follow pin couples the first supply metal tract to the second power route. In some aspects, the first supply metal tract is a power supply or a voltage source source (“VSS”), and the second supply metal tract is a ground supply or a voltage drain drain (“VDD”). In some aspects, the first supply metal tract and the second supply metal tract comprise a first metal and a follow pin comprises a second metal.

In another embodiment a semiconductor structure comprises a first cell having a first supply metal line, a second supply metal line having a width greater than a width of the first supply metal line, and a first pattern metal layer disposed between the first supply metal line and the second supply metal line. The first pattern metal layer has a width substantially the same as a width of the first supply metal line. The first pattern metal layer includes a first internal route, a first power route. The semiconductor structure also comprises a second cell formed above the first cell having a third supply metal line proximal to the first supply metal line and having a width substantially the same as the first supply metal line, and a fourth supply metal line distal to the second supply metal line and having a width greater than a width of the third supply metal line. A second pattern metal layer is disposed between the third supply metal line and the fourth supply metal line and has a width substantially the same as a width of the third supply metal line. The second pattern metal layer comprises a second internal route and a second power route.

In some aspects the semiconductor structure further includes a first in-cell follow pin coupling the first supply metal line to the third supply metal line. In some aspects, the semiconductor structure further comprising a fifth supply metal line between the first supply metal line and the third supply metal line and having a width between 1.5 and 3 times the width of the third supply metal line, and the first in-cell follow pin is further coupled to the fifth supply metal line. In some aspects, the first in-cell follow pin is coupled to the first power route or the second power route. In some aspects, a first pillar metal structure external to the first cell and the second cell couples the first supply metal line to the third supply metal line, and a second pillar metal structure external to the first cell and the second cell couples the first supply metal line to the third supply metal line. In some aspects, the semiconductor structure includes at least two polysilicon structures within the first cell that define a first pitch wherein the first pillar metal structure and the second pillar metal structure are each single pillar pins and the first pillar metal structure and the second pillar metal structure define a second pitch that is greater than the first pitch by a factor of between 24 and 30. Alternatively, the first pillar metal structure and the second pillar metal structure each comprise two pillar pins and the pitch of the first pillar metal structure and the second pillar metal structure is greater than the first pitch by a factor of between 48 and 60. In some aspects, the semiconductor structure also includes a fifth metal supply line between the first metal supply line and the third metal supply line, a first pillar metal structure external to the first cell and coupled to the first supply metal line, the third supply metal line, and the fifth supply metal line, and a second pillar metal structure external to the first cell and coupled to the first supply metal line, the third supply metal line, and the fifth supply metal line. In some aspects, the first supply metal line and the third supply metal line are power supply lines or VSS lines, and the second supply metal lines and the fourth supply metal lines are ground lines or VDD lines. In some aspects, the semiconductor structure includes a first strap structure coupled to the second supply metal line and the fourth supply metal line; and a second strap structure coupled to the second supply metal line and the fourth supply metal line wherein the first strap structure and the second strap structure define a second pitch larger than the first pitch by a factor of between 4 and 30.

In embodiments, a semiconductor structure comprises a first supply metal layer, a second supply metal layer having a width substantially the same as a width of the first metal supply layer, a third supply metal layer between the first supply metal layer and the second supply metal layer having a width greater than the first metal supply layer by a factor of 1.5 to 3, a first pattern metal layer disposed between the first supply metal layer and the third supply metal layer and having a width substantially the same as a width of the first supply metal layer and including a first internal route, and a first power route. The semiconductor structure also includes a second pattern metal layer disposed between the third supply metal layer and the second supply metal layer and having a width substantially the same as a width of the first metal supply layer, the second pattern metal layer comprising a second internal route, and a second power route, and a first follow pin coupled to the first supply metal layer and the first power route, and a second follow pin coupled to the second supply metal layer and the second power route. In some aspects, the semiconductor structure also may include a strap metal structure coupled to the first supply metal layer and the second supply metal layer, or a pillar metal structure coupled to the third supply layer and a third power route between the first supply metal layer and the second supply metal layer, the third supply power route having a width substantially equal to the first supply metal layer.

In an interrelated embodiment a method for forming a semiconductor structure, is disclosed. The method comprises forming a first supply metal layer, forming a first metal pattern layer over the first supply layer, the first metal pattern layer having a width less than the width of the first supply metal layer and having a plurality of distinct metal lines, forming a second supply metal layer over the first metal pattern layer, the second supply metal layer having substantially the same width as the first metal pattern layer, and coupling a follow pin to both the second supply metal layer and at least one distinct metal line of the plurality of distinct metal lines of the first metal pattern layer. In some aspects, the method includes forming each of first supply metal layer, the first metal pattern layer, and the second supply metal layer of a first metal, and forming the follow pin of a second metal different from the first metal.