Controlling apparatus and controlling method for controlling a pre-charge activity on a SRAM array

A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed and generate a row-changing signal according to the detection result; the controlling module is to detect an operation mode of the SRAM array and generate a disable signal according to the row-changing signal and the operation mode; and the pre-charge module is to generate a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation.

BACKGROUND

1. Field of Invention

The present invention relates to a controlling apparatus for controlling a pre-charge activity on a SRAM array. More particularly, the present invention relates to a controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array.

2. Description of Related Art

In a driver IC adapted in a liquid crystal display panel of a portable device, a SRAM can be embedded to store the data on the display panel. If a frame on the display panel is still, the system only have to take the display data from the SRAM and doesn't need to refresh the data continuously to avoid power consumption.

Nevertheless, the portable device provides more and more multimedia data. The motion pictures showed on the display panel will result in continuous refreshment of the SRAM. Thus, the power consumption rises a lot due to the multimedia data.

Accordingly, what is needed is a controlling apparatus and a method for controlling a pre-charge activity on the SRAM array to avoid dummy power consumption and overcome the above issues. The present invention addresses such a need.

SUMMARY

A controlling apparatus for controlling a pre-charge activity on a SRAM array is provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed and generate a row-changing signal according to the detection result; the controlling module is to detect an operation mode of the SRAM array and generate a disable signal according to the row-changing signal and the operation mode; and the pre-charge module is to generate a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation.

Another object of the present invention is to provide a controlling method for controlling a pre-charge activity on a SRAM array. The controlling method comprises the steps of: detecting an operation mode of the SRAM array; generating a row-changing signal when detecting that the row address of the SRAM array in operation is changed; generating a disable signal according to the row-changing signal and the operation mode; and generating a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation.

DETAILED DESCRIPTION

Please refer toFIG. 1, a controlling apparatus1for controlling a pre-charge activity on a SRAM array (not shown) in the first embodiment of the present invention. The controlling apparatus1comprises: a detecting module100, a controlling module102, a pseudo-pre-charge module104and a pre-charge module106. The detecting module100is to detect whether the row address101of the SRAM array in operation is changed and generate a row-changing signal S103according to the detection result. The controlling module102is to receive a read request signal S105and a write request signal S107to detect an operation mode of the SRAM array and generate a disable signal S109according to the row-changing signal S103and the operation mode. The controlling module102further generates a clock S111according to the operation mode. The pseudo-pre-charge module104generates a pseudo-pre-charge signal S113according to a first state and a second state of the clock S111, wherein the first state and the second state are opposite. The pre-charge module106is to generate a pre-charge signal SS115according to the pseudo-pre-charge signal S113and the disable signal S109, wherein the pre-charge signal S115substantially controls the pre-charge activity on the SRAM cell in operation. In the present embodiment, the pre-charge module106is an “OR” logic gate.

Please refer toFIG. 2, the second embodiment of the present invention is a controlling method for controlling a pre-charge activity on a SRAM array. At first, in step201, detecting an operation mode of the SRAM array; in step202, generating a row-changing signal when detecting that the row address of the SRAM array in operation is changed; in step203, generating a disable signal according to the row-changing signal and the operation mode; and in step204, generating a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein in step205, the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation.

The main factors to affect the pre-charge signal are the clock, the operation mode and the row address of the SRAM cell in operation. Thus, when the clock is in a first state, which is a high state in the present embodiment, the pseudo-pre-charge signal makes the pre-charge signal disable the pre-charge activity on the SRAM cell in operation. When the clock is in a second state, which is a low state in the present embodiment, the operation mode is write and the row address of the SRAM cell in operation is not changed, the pseudo-pre-charge signal and the disable signal disable the pre-charge activity on the SRAM cell in operation. When the clock is in a second state, i.e. low state, the operation mode is write and the row address of the SRAM cell in operation is changed, the pseudo-pre-charge signal and the disable signal enable the pre-charge activity on the SRAM cell in operation. When the clock is in a second state, i.e. low state, and the operation mode is read, the pseudo-pre-charge signal and the disable signal enable the pre-charge activity on the SRAM cell in operation. As shown inFIG. 3, a timing diagram of the row address S101of the SRAM, the column address S300of the SRAM, the data signal S301, the write request signal S105, the read request signal S107, the row-changing signal S103, the clock S111, the operation mode S302, the disable signal S109, the pseudo-pre-charge signal S113, the pre-charge signal S115, and the pre-charge activity of five SRAM cells in different address S303-S307. It's noticed that: (1) The operation mode S302specifies that a high state stands for a “read”, and a low state stands for a “write”; (2) The disable signal S109is related to the operation mode S302and the row-changing signal S103; (3) The pseudo-pre-charge signal S113is related to the clock S111; (4) The pre-charge signal S115is a logic operation result of the disable signal S109and the pseudo-pre-charge signal S113; (5) The pre-charge signal S115enables the pre-charge activity when the pre-charge signal S115is in low state; and (6) Each SRAM cell has a bit line and a bit line bar corresponding to the black and the gray line of the timing diagram of each of the five SRAM cells. The pre-charge activity is performed on both of the bit line and the bit line bar.

According to the description above, the controlling method results in four different conditions as depicted as inFIG. 4. In step401, determining whether the clock is in a first state. If the clock is in the first state, then the controlling method results in condition402, the pre-charge is set to 1 to disable the pre-charge activity. If the clock is in the second state, the step403is executed to determine whether the operation mode is read. If the operation mode is read, then the controlling method results in condition404, the operation mode is set to 1, and the pre-charge is set to 0 to enable the pre-charge activity. If the operation mode is write, the step405is executed to detect whether the row address of the SRAM array in operation is changed. If there is a difference, then the controlling method results in condition406, the operation mode is set to 0, the row-changing signal is set to 1 and the pre-charge signal is set to 0 to enable the pre-charge activity. If there is no difference, then the controlling method results in condition407, the operation mode is set to 0, the row-changing signal is set to 0 and the pre-charge signal is set to 1 to disable the pre-charge activity.

The controlling apparatus of the present invention detects (1) the operation mode (2) whether the row address of the SRAM array in operation is changed, and further controls the pre-charge activity on the SRAM array according to the detection result. The pre-charge activities only need to be performed on the SRAM array while necessary. Therefore, the dummy power consumption is avoided, and the overall power consumption is dramatically reduced.