Data transfer system interconnecting a computer and a display device

Disclosed is a data transfer system that effectively reduces EMI radiation, in a device wherein EMI radiation very easily occurs, without the need for filters, etc. A system for transmitting data across a bus having a plurality of data lines includes a modulating circuit for modulating data so as to reduce the EMI radiation attributable to the data lines and a demodulating circuit for restoring the original data after transmission.

FIELD OF THE INVENTION 
The present invention relates to the reduction of EMI (Electro-Magnetic 
Interference) radiation for various types of electronic devices, such as 
computer systems, and more particularly relates to the reduction of EMI 
radiation for video interface circuits. 
BACKGROUND 
When a signal is transmitted along an interface cable, an electro-magnetic 
wave is irradiated. This electromagnetic wave is called extraneous 
radiation (EMI radiation), and its allowable limits are specified by 
international standards. EMI radiation from an interface circuit that 
includes a wide bus (e.g. a large number of signal lines or individual 
buses), such as an LCD video interface, increases in proportion to the 
number of signal lines in the bus. 
As the transfer speed for interface signals, and more particularly, for 
video interface signals for liquid crystal displays (LCDs) increases, the 
bus width as well as the speeds for the signals transmitted across the bus 
also increase. For example, since an LCD bus normally communicates with an 
LCD module via an interface cable (bus) that consists of a plurality of 
data lines, EMI radiation attributable to this interface cable (bus) 
greatly affects the EMI radiation of the entire system. The EMI radiation 
attributable to the bus has the greatest impact on the system EMI 
radiation when the waveforms of the data transmitted across all the data 
lines of the bus are identical. Since the data lines of a bus in the LCD 
video interface correspond to luminescence, the data lines frequently all 
have the same value, for example, when it is desired to employ the display 
at the maximum luminescence. Since such occurrences are rather common, EMI 
radiation is a serious problem for LCD video interfaces. 
There are three types of interface signals: (1) parallel data bus signals 
(data 1! . . . data n!), (2) sampling clocks (clock signals), and (3) 
synchronization signals (SYNC signals). For example, FIG. 12 shows a 
sample of interface signals as transmitted by a conventional interface 
circuit. N-bit data, data 1! through data n! are transmitted. A clock 
signal is employed for timing the sampling of the data by a receiver. A 
synchronization signal (SYNC signal) is employed for informing the 
receiver of the start of data transmission. In this example, data 1! . . 
. data n!="00 . . . 0" are transmitted at time T1; data "11 . . . 1" are 
transmitted at time T2; data "00 . . . 0" are transmitted at time T3; and 
data "11 . . . 1" are transmitted at time T4. 
More particularly, for a red-green-blue (RGB) video signal, for example, 
the three bits associated with the RGB color signals can be regarded as 
parallel data bus signals. A dot clock signal is added as a sampling clock 
signal for the interface. A horizontal synchronization signal can be 
employed as a sync signal. 
In the alternative, for an LCD video signal, data signals for the colors 
red, green and blue (RGB) can be regarded as parallel data bus signals. 
More specifically, in the LCD, generally, each color signal (R,G, & B) has 
a plurality of bits, n, which determine the resolution of luminescence for 
the individual colors. The LCD video signal can be considered as a 
parallel data interface signal that is carried by 3.times.n bit data bus. 
A sampling clock signal is originally provided for the LCD interface. A 
conventional signal that indicates display timing can be employed as a 
sync signal. 
As a conventional EMI countermeasure, filters are generally installed for 
each signal line of a bus. When there are many buses provided, however, 
the installation of such items as filters for all the data lines of the 
buses, as a means of providing an EMI countermeasure, increases 
manufacturing costs. Further, as much space is required for installation 
on a printed circuit board (PCB), the manufacturing costs for the board 
also rise. In addition, it must be considered that the installation of the 
filters must not deteriorate the quality of waveforms. Moreover, as the 
constant of a filter is limited by recent advances in the speed of buses, 
a satisfactory effect cannot be expected. 
Such EMI radiation from an interface signal has the following 
characteristics: 
(1) EMI radiation that occurs when digital signals having the same 
waveforms are transmitted as n interface signals is n times the radiation 
that accompanies the transmission of a digital signal as a single 
interface signal. 
(2) The amount of EMI radiation that is produced is proportional to the 
frequency elements of a signal, and becomes greater as the rate of 
repetition of a signal is increased. For example, when a digital signal 
repeats HLHLHLHL, the EMI radiation with the greatest intensity occurs. 
(3) EMI radiation increases with the length of the interface cable, which 
acts like an antenna for EMI radiation. 
A video interface circuit for an LCD is a specific example of a digital 
parallel interface signal which exhibits the three characteristics recited 
above, thus resulting in maximum EMI radiation. For an LCD video signal, a 
plurality of data lines are provided that are employed to carry data 
signals that represent the luminescence of the individual RGB signals, the 
number of the data lines being determined by the color resolution of a 
pertinent system. To display white at its maximum luminescence on a 
screen, all the data lines carry the same waveforms. Thus, the first 
characteristic (1) is present. To repeatedly display the same characters 
on the screen, a short repetitive signal is transmitted. Thus, the second 
characteristic (2) is present. Since an LCD video signal usually has to be 
transmitted from the system to an LCD via a cable, the third 
characteristic (3) is also present. 
OBJECTS 
To overcome the above shortcomings, it is an object of the present 
invention to effectively reduce EMI radiation without requiring the 
employment of filters, etc., even under conditions where EMI radiation 
most easily occurs, such as at an LCD video interface. 
It is a further object of the present invention to limit EMI radiation with 
the characteristics (1) through (3), by carrying the n interface signals 
in an interface cable by different waveforms and by causing the interface 
signals to have waveforms with a long repetitive cycle. 
It is yet a further object of the present invention to provide an interface 
signal modulator for modulating data carried across an interface cable 
such that the interface signals are carried by different waveforms and 
have waveforms with a long repetitive cycle (which serves as an antenna 
(EMI generator)), and a receiver for demodulating the modulated signal to 
restore the original signal. 
SUMMARY 
According to the present invention, a computer system, which transfers data 
via a bus having a plurality of data lines, includes a circuit for 
reducing electro-magnetic radiation emanating from the plurality of data 
lines of the bus by modulating the data carried on the plurality of data 
lines prior to transmission and a circuit for recovering the original data 
by receiving and demodulating the modulated data. 
In another aspect of the invention, a computer system includes a data bus 
having a plurality of data lines for carrying data, a circuit for 
modulating the data prior to transmission across the bus, thereby 
randomizing the data, and a display device coupled to the bus for 
receiving and for demodulating the modulated data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 is an illustration of a computer system 10 according to the present 
invention. The computer system 10 includes a data signal generator 20, 
which has a video signal generator, etc. A data signal produced by the 
data signal generator 20 is transmitted to a display device 40 via a data 
transfer system 15. The data transfer system 15 includes a signal 
demodulator 100 that randomizes received data signals. The randomized data 
signals are carried to a signal demodulator 200 by an interface cable 30. 
The signal demodulator 200 demodulates the received data and supplies the 
demodulated data signals to the display device 40. 
The data transfer system 15 is shown in more detail in FIG. 2. As described 
above, the data transfer system 15 includes the signal modulator 100, the 
interface cable 30, and the signal demodulator 200. The individual circuit 
components of the signal modulator 100 are physically identical to those 
of the signal demodulator 200, and, accordingly, the circuit arrangements 
of both circuits are identical. As the identical arrangement is employed 
for both the signal modulator 100 and the signal demodulator 200, the 
function of either circuit is determined by the value of a control signal, 
i.e., the level of an "+encode/-decode" signal. 
The signal modulator 100 and the signal demodulator 200, respectively, have 
n-bit counters 110 and 210, n-bit adders 120 and 220, and timing 
controllers 130 and 230. It should be noted that "n" denotes a bit count 
value for a data bus. 
The n-bit counters 110 and 210 increment or decrement an initial value 
depending on whether the circuits 100 and 200 are employed as data 
modulators or data demodulators. Whether incrementing or decrementing is 
performed can be selected according to the level of a control signal 
"+encode/-decode." A high +encode/-decode signal enables the n-bit 
counters 110 and 210 to increment while a low +encode/-decode signal 
enables the n-bit counters 110 and 210 to decrement. The n-bit counters 
110 and 210 are reset when a SYNC signal, one of the interface signals, is 
true, while they perform the increment or decrement function when a SYNC 
signal is false. The counters 110 and 210 each have a clock input for 
receiving the interface clock signal, which signal controls the timing of 
the increment and decrement functions, once enabled and reset. 
With continued reference to FIG. 2, the adders 120 and 220 add the output 
values of the respective n-bit counters 110 and 220 to data 1! . . . n! 
for every bit, including the carry. 
The timing controllers 130 and 230 control the operational timing for the 
respective signal modulator 100 and the signal demodulator 200, so that 
the signal demodulator 200 correctly subtracts from data a value (the 
value output by the counter 110) that was previously added to data 1! . . 
. n! by the signal modulator 100. 
An enable signal is employed to determine whether or not the signal 
demodulator 100 and the signal demodulator 200 should modulate data and 
demodulate data, respectively. When a circuit, independent of these 
circuits (not shown), is employed that decodes data 1! . . . n! of the 
interface signals and then determines whether or not data modulation 
should be performed, the output of the circuit is supplied as an enable 
signal to the circuits 100 and 200. For example, when all the bits of data 
1! . . . n! are not changed within a specified period of time, EMI 
radiation is low and data modulation by the circuit 100 is not required. 
The addition of an enable signal to the interface signals provides the 
ability to dynamically determine whether or not data modulation should be 
performed. The decision to invoke data modulation performed by the signal 
modulator 100 must be synchronized with the decision to invoke data 
modulation by the signal demodulator (receiver) 200. 
Table 1 shows a data modulation method (randomization) for use with the 
arrangement in FIG. 2. An 8-bit parallel data interface example is 
employed in this case. 
TABLE 1 
______________________________________ 
Data Xdata Rdata 
1! . . . 8! 
Count 1 1! . . . 8! 
Count 2 
1! . . .8! 
______________________________________ 
FF 01 00 FF FF 
00 02 02 FE 00 
FF 03 02 FD FF 
00 04 04 FC 00 
FF 05 04 FB FF 
______________________________________ 
The columns of Table 1 represent the development over time of various 
signals. The first column of Table 1, "Data 1! . . . 8!," represents a 
data signal that is to be transmitted. "FF" is a number in the hexadecimal 
system that is equivalent to "11111111" in the binary system. In other 
words, the values of all the eight data bits are "1." The second column, 
"Count 1," represents the output value of the n-bit counter 110 in the 
signal modulator 100. Here, incrementation is performed. The third column, 
"Xdata 1! . . . 8!," represents a value that is obtained by adding the 
value of the data 1! . . . 8! in the first column to the output value of 
the counter 110 in the second column. The Xdata 1! . . . 8! are 
transmitted via the interface cable 30. The fourth column, "Count 2," 
represents the output value of the counter 210 in the signal demodulator 
200. Since the signal modulator 100 has incremented the value of a signal, 
the demodulator 200 decrements the value of a signal. The fifth column, 
"Rdata 1! . . . 8!," represents the result that is obtained by adding 
the signal value for "Xdata 1! . . . 8!" to the counter output value 
"count 2" of the demodulator 200. This result serves as the output for the 
demodulator 200. 
As described above, signals "data 1! . . . 8!," which are repeated 
rapidly and of which all the bits are operated with the same signal 
waveform, can be converted respectively into signals "Xdata 1! . . . 8! 
," which are operated with waveforms that differ from each other. Further, 
these modulated signals can be demodulated and the original signals can be 
recovered by the signal demodulator 200. 
To perform the above modulation, the counter 110 of the signal modulator 
100 must be fully synchronized with the counter 210 of the signal 
demodulator 200. The SYNC signal and the clock signal, which are included 
in the interface signals, are employed to synchronize the counters 110 and 
210. Further, a circuit that controls the timing that accompanies this 
calculation for the circuit is necessary. 
FIG. 3 is a diagram showing an exemplary embodiment of the signal modulator 
100 for an interface that has a 4-bit data bus. It should be noted that 
the present invention is not limited to a 4-bit data bus. For purposes of 
clarity, an enable signal is not represented in FIG. 3. 
FIG. 4 is a diagram showing the timing for 4-bit input signals. The signals 
shown in FIG. 4 correspond to data n=4 in the timing diagram of FIG. 12, 
and are the interface signals when data modulation is not performed by the 
signal modulator 100 (for 4-bit signals). 
FIG. 5 shows the input/output signals of the 4-bit counter 410 depicted in 
FIG. 3 when the 4-bit counter 410 is in a signal modulation mode. In 
signal modulation mode, a value incrementation example is shown. When the 
SYNC signal is high, the counter 410 is reset and its output count values 
1! . . . 4! are all zero. Since a +encode/-decode signal is true (high), 
the counter 410 increments beginning with an initial value, shown in FIG. 
5 as "0001". The counter 410 begins counting with the rise of the clock 
signal at time T2. The count value 4! . . . 1! is "0001" at time T2, 
"0010" at time T3, and "0011" at time T4. 
FIG. 6 is a timing diagram showing signals output by the adder 420 depicted 
in FIG. 3 as the result of the addition of the values output by the 
counter 410, count 1! . . . count n!, to the input data 1! . . . 4!. 
Signals "data latch 1! . . . 4!" are those obtained by sampling input 
signals "data 1! . . . 4!" at the leading edges of the clock signal. 
Signals "Xdata 1! . . . 4!" are the outputs of the adder 420. The same 
data modulation as shown in Table 1 is performed. 
In FIG. 7 is shown the timing diagram for the output signals supplied to 
the interface cable 30 depicted in FIG. 2 via the timing controller 430 
depicted in FIG. 3, as well as the input signals shown in FIG. 4. The X 
data are the modulated signals shown in FIG. 6. The XSYNC signal is a 
signal obtained by sampling a SYNC signal, which is input to the timing 
controller 430, at a time specified by the interface clock signal. The X 
clock signal is a signal obtained by inverting the polarity of the input 
clock signal. As is shown in FIG. 7, the modulated signal consists of X 
data, XSYNC, and X clock signals, which have the same general timing 
relationships as do the data, SYNC, and clock signals prior to modulation. 
It is therefore understood from such a timing analysis that the signal 
demodulator 200 can employ the same circuit arrangement as the signal 
modulator 100 to demodulate the received signals so as to recover the 
original signals. 
FIG. 8 shows the timing diagram for the input and output signals of the 
counter 210 of the demodulator 200 as depicted in FIG. 2. The operation of 
the signal demodulator 200 is exactly the same as that of the signal 
modulator, except that the counter 210 operates to decrement from an 
initial value, shown in FIG. 8 as "1111". FIG. 9 shows the input/output 
signals of an adder 220 of the demodulator 200. FIG. 10 shows data, clock, 
and SYNC signals, which have the identical transfer timings of the 
originals, that are reproduced by the timing controller 230 from the data 
demodulated by the demodulator 200. 
EXAMPLE 
FIGS. 11A and 11B are graphs depicting the results of an experiment during 
which EMI radiation was emitted while using the circuit shown in FIG. 3. 
In this experiment, 4-bit parallel data were transmitted. The vertical 
axis represents the magnitude of the EMI radiation that was emitted, while 
the horizontal axis represent the frequency at which such magnitudes were 
measured. The heavy solid lines indicate specified limits for EMI 
radiation across the frequency range. For the experiment, data, F, F, 0, 
0, 0, F, F, 0, were repeatedly transmitted. FIG. 11A shows the radiation 
characteristics of the above transmission pattern as a function of 
frequency when the circuit of FIG. 3 in NOT in modulation mode. FIG. 11B 
shows the radiation characteristics of the above transmission pattern as a 
function of frequency when the circuit of FIG. 3 is in modulation mode as 
described above. In comparing FIGS. 11A to 11B it is apparent that the 
circuit of the present invention effectively reduces EMI radiation to a 
level well below the specified limit. 
It would be obvious to one having ordinary skill in the art that the 
present invention is not limited to the above described embodiment. 
Although in this specification, the present invention is applied to a 
computer system, the present invention can be applied to other electronic 
devices. Further, although the signal modulator 100 and the signal 
demodulator 200 are arranged the same for the described embodiment, they 
may be arranged differently. In addition, although in this embodiment data 
modulation is performed by adding the counter output to the data, the 
output of a circuit, other than a counter, that repetitively outputs a 
specific pattern may be added instead. Data modulation may also be 
performed only on a part of a data signal. 
According to the present invention, data are modulated (randomized) and the 
transmission of an identical signal over multiple signal lines of a bus is 
prevented, so that EMI radiation can be reduced. Further, for the 
reduction of EMI radiation, the deterioration of the quality of waveforms 
due to the installation of filters need not be taken into account. 
Further, the component count and the manufacturing cost can be reduced by 
attaching the above described circuit to an LCD interface circuit or by 
producing a dedicated chip.