Integrated circuit packaging system with interposer

An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array over the first integrated circuit die; and singulating a base package from the base package substrate sheet and the interposer array by cutting the access opening generally through the center.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application contains subject matter related to U.S. patent application Ser. No 11/306,628, now U.S. Pat. No. 7,364,945. The related application is assigned to STATS ChipPAC Ltd.

TECHNICAL FIELD

The present invention relates generally to integrated circuit packaging, and more particularly to a system for forming three dimensional stacked packages with an interposer.

BACKGROUND ART

Integrated circuits are used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. They are also used in many larger electronic systems, such as cars, planes, industrial control systems, and the like. Across virtually all applications, there continues to be demand for reducing the size and increasing performance of the devices. The intense demand is now at a peak in portable electronics that have become so ubiquitous and are frequently shrinking in size.

Wafer manufacturing strives to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality. Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices. Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future. However, significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to semiconductor packaging as a means to fulfill the relentless demands for enhanced system performance and smaller component size.

Some of the functions that are required to support the new applications are based on different technologies. As an example, high capacity memory may be built in a different technology than a high speed processor. This situation prevents them from being fabricated on the same silicon wafer, but the different technologies can be packaged together to deliver highly space efficient components.

Drawbacks of conventional designs include a relatively large footprint of the package on the mounting surface of motherboard. The footprint reflects what is typically measured as the maximum dimension of the package, namely, the x-y dimension. In applications where mounting space is at a premium, such as pagers, portable telephones, and personal computers, among others, a large footprint is undesirable. With the goal of increasing the amount of circuitry in a package, but without increasing the area of the package so that the package does not take up any more space on the circuit board, manufacturers have been stacking two or more die within a single package. Unfortunately, sufficient overlap for electrical interconnect and large footprint top packages have plagued previous stacked package or package on package designs.

Thus, a need still remains for an integrated circuit packaging system with interposer, that can support high volume and high quality stacked package designs. In view of the ever-increasing demand for more functions in a smaller space, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides an integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array over the first integrated circuit die; and singulating a base package from the base package substrate sheet and the interposer array by cutting the access opening generally through the center.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Where multiple embodiments are disclosed and described, having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.

For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used. The term “processing” as used herein includes stamping, forging, patterning, exposure, development, etching, cleaning, and/or removal of the material or laser trimming as required in forming a described structure.

Referring now toFIG. 1, therein is shown a cross-sectional view of an integrated circuit packaging system100, in an embodiment of the present invention. The cross-sectional view of the integrated circuit packaging system depicts a base package substrate102having an upper surface104and a lower surface106. A first integrated circuit die108is attached to the upper surface104by an adhesive110, such as a die attach material. A second integrated circuit die112is attached over the first integrated circuit die108by the adhesive110. An interposer114is attached over the second integrated circuit die112by the adhesive110. Electrical interconnects116, such as bonding wires, couple the upper surface104of the base package substrate102, the first integrated circuit die108, the second integrated circuit die112, the interposer114, or a combination thereof.

An encapsulant118, such as an epoxy molding compound, may be formed over the electrical interconnects116, the upper surface104of the base package substrate102, the first integrated circuit die108, the second integrated circuit die112, the adhesive110, and a portion of the interposer114. Only the edges of the interposer114have the encapsulant118on it. The center area of the interposer114remains clear for mounting an additional integrated circuit package120thereon.

The base package substrate102may have an upper surface contact122. The upper surface contact122may provide a conductive path for the electrical interconnects116by contacting base package vias124, lower surface contacts126, and system interconnects128, such as a solder ball, solder column, solder bump, or stud bump. The structure of a base package130includes the base package substrate102, the adhesive110, the first integrated circuit die108, the second integrated circuit die112, the interposer114, the electrical interconnects116, the encapsulant118and the system interconnects128.

The embodiment shown inFIG. 1is an example only. The base package130is shown having the first integrated circuit die108and the second integrated circuit die112under the interposer114. An embodiment of the present invention may have more than two of the first integrated circuit die108mounted over the base package substrate102. While the integrated circuit dice108are shown as wire bond type, it is understood that flip chip type of the second integrated circuit die112may also be used. Interposer contacts132are distributed on the top surface of the interposer114for attaching the additional integrated circuit package120.

Referring now toFIG. 2, therein is shown a cross-sectional view of a base package array200in a pre-singulation phase of manufacturing. The cross-sectional view of the base package array200depicts a base package substrate sheet202having several of the first integrated circuit die108mounted thereon. The second integrated circuit die112is mounted over each the first integrated circuit die108. The adhesive110adheres an interposer array204, having access openings206, over the second integrated circuit die112. The electrical interconnects116may be coupled between the base package substrate sheet202and the interposer array204through the access openings206.

During the molding process, the encapsulant118flows through the access openings206in the interposer array204to surround the electrical interconnects116, the first integrated circuit die108, the second integrated circuit die112, the adhesive110, and a top surface of the base package substrate sheet202. The system interconnects128may be adhered to the bottom surface of the base package substrate sheet202for electrical connection to the next level system (not shown).

Attaching the interposer array204provides a stable surface that resists warping. This is significant to the manufacturing process as it reduces the amount of excess of the encapsulant118, known as flash, that may be extruded onto the contact surface of the interposer array204.

Referring now toFIG. 3, therein is shown a cross-sectional view of a stacked die assembly300of the base package130, ofFIG. 1, in a die attach phase of manufacturing. The cross-sectional view of the stacked die assembly depicts the base package substrate sheet202having a number of the first integrated circuit die108mounted thereon. The second integrated circuit die112is mounted over each of the first integrated circuit die108. The first integrated circuit die108and the second integrated circuit die112may be attached by the adhesive110, ofFIG. 1.

Referring now toFIG. 4, therein is shown a cross-sectional view of a stacked die assembly400in an electrical interconnect phase of manufacturing. The cross-sectional view of the stacked die assembly400depicts the base package substrate sheet202having a number of the first integrated circuit die108mounted thereon. The second integrated circuit die112is mounted over each of the first integrated circuit die108. The electrical interconnects116may be coupled between the first integrated circuit die108, the second integrated circuit die112, the base package substrate sheet202, or a combination thereof.

Referring now toFIG. 5, therein is shown a cross-sectional view of a stacked die assembly500in an interposer attach phase of manufacturing. The cross-sectional view of the stacked die assembly500depicts the stacked die assembly400with the interposer array204mounted over the second integrated circuit die112by the adhesive110. The application of the interposer array204provides a flat uniform surface for further manufacturing processes.

Referring now toFIG. 6, therein is shown a cross-sectional view of a stacked die assembly600in an interposer interconnect phase of manufacturing. The cross-sectional view of the stacked die assembly600depicts the stacked die assembly500having the electrical interconnects116for coupling the interposer array204to the base package substrate sheet202.

Referring now toFIG. 7, therein is shown a cross-sectional view of a stacked die assembly700in an encapsulation phase of manufacturing. The cross-sectional view of the stacked die assembly700depicts the stacked die assembly600having the encapsulant118molded over the electrical interconnects116, the first integrated circuit die108, the second integrated circuit die112, the adhesive110, the top surface of the base package substrate sheet202, and a portion of the interposer array204. The encapsulant118passes through the access opening206to flow around the electrical interconnects116, the first integrated circuit die108, the second integrated circuit die112, the adhesive110, and the top surface of the base package substrate sheet202.

Referring now toFIG. 8, therein is shown a cross-sectional view of a base package array800in a singulation phase of manufacturing. The cross-sectional view of the base package array800depicts the base package array200with a singulation device802, such as a singulation saw or a singulation shear, cutting the base package array200into single units. A singulation line804indicates the location of the next boundary of the single unit. The singulation device802passes through the center of the access opening206, ofFIG. 1, and through the base package substrate sheet202. ofFIG. 2. between the system interconnects128, of FIG .1. The resulting packaged device may be characterized as having been singulated by breaking, sawing, or cutting the package edges.

Referring now toFIG. 9, therein is shown a cross-sectional view of the base package130in a singulated state. The cross-sectional view of the base package130depicts the base package substrate102, the first integrated circuit die108is mounted over the base package substrate102. The electrical interconnects116couple the first integrated circuit die108to the base package substrate102. The second integrated circuit die112is mounted over the first integrated circuit die108and coupled to the base package substrate102by the electrical interconnects116.

The adhesive110is on the second integrated circuit die112for mounting the interposer114. The electrical interconnects116couple the base package substrate102, the first integrated circuit die108, the second integrated circuit die112, the interposer114, or a combination thereof.

Referring now toFIG. 10, therein is shown a top plan view of the base package130ofFIG. 1. The top plan view of the base package130depicts the interposer114partially enclosed by the encapsulant118. The exposed area of the interposer114may have the interposer contacts132distributed thereon. The base package substrate102may have the upper surface contacts122, for coupling the interposer114by the electrical interconnects116, and the lower surface contacts126. ofFIG. 1. with system interconnects128, of FIG. I mounted thereon. The shape of the interposer114reflects that it was part of the interposer array204ofFIG. 2. The stability provided by this invention reduces the likelihood of the interposer114becoming warped during the manufacturing process. The base package130may include the interposer114having recessed edges and corners that extend to a singulation edge1002and the space between the base package substrate102and the interposer114filled by the encapsulant118to embed the first integrated circuit die108, ofFIG. 1, and the second integrated circuit die112, ofFIG. 1. therebetween.

Referring now toFIG. 11, therein is shown a top view of an interposer array segment1100, in an embodiment of the integrated circuit packaging system100, of the present invention. The top view of the interposer array segment1100depicts the interposer array204having the access openings206, the interposer contacts132, singulation markers1102and singulation lines1104. The singulation lines1104are added for clarity and may not be implemented in the actual embodiment of the invention.

When the interposer array204is implemented for a particular design the position and number of the interposer contacts132may be different. The current figure is for example only and does not limit the number, type, or position of the interposer contacts132.

Referring now toFIG. 12, therein is shown a magnified top view of a single interposer1200from the interposer array1100ofFIG. 11. The magnified top view of the single interposer1200depicts the interposer array1100having the singulation markers1102and the singulation lines1104. The interposer contacts132are disposed across the surface of the single interposer1200in a contact array1202. The contact array1202may contain interposer bonding contacts1204, interposer pin pads1206, the interposer contacts132, or a combination thereof.

Referring now toFIG. 13, therein is shown a cross-sectional view of a casting mold1300used for the encapsulation phase of manufacturing. The cross-sectional view of the casting mold1300depicts a bottom mold chase1302having a mating section1304for attaching an upper mold chase1306. The stacked die assembly600may be loaded in the upper mold chase1306in preparation for molding the encapsulant118. A protrusion1308in the upper mold chase1306rests on the interposer array204ofFIG. 2. The protrusion1308prevents the encapsulant118from flowing onto the interposer contacts132ofFIG. 1and the interposer pin pads1206, ofFIG. 12, of the contact array1202, ofFIG. 12, during the injection molding process.

Referring now toFIG. 14, therein is shown a magnified perspective view of an electrical interconnect array1400during the interposer interconnect phase of manufacturing ofFIG. 6. The magnified perspective view of the electrical interconnect array1400depicts the interposer array204, having the interposer bonding contacts1204. Is coupled by the electrical interconnects116to the upper surface contacts122of the base package substrate sheet202.

The electrical interconnects116pass through the access opening206of the interposer array204. The access opening206also allows the encapsulant118to easily flow through the package forming a reliable stacked die package.

Referring now toFIG. 15, therein is shown a flow chart of an integrated circuit packaging system1500for manufacturing the integrated circuit packaging system in an embodiment of the present invention. The system1500includes fabricating an interposer array having an access opening in a block1502; fabricating a base package substrate sheet in a block1504; attaching a first integrated circuit die over the base package substrate sheet in a block1506; mounting the interposer array over the first integrated circuit die in a block1508; and singulating a base package from the base package substrate sheet and the interposer array by cutting the access opening generally through the center in a block1510.

It has been discovered that the present invention thus has numerous aspects.

A principle aspect of the present invention is that the interposer array of the integrated circuit packaging system prevents the interposer from becoming warped during the manufacturing process. This prevents the encapsulant from flowing onto the interposer contacts and the interposer pin pads.

Thus, it has been discovered that the integrated circuit packaging system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for high density integrated circuit packaging. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing stacked die integrated circuit devices fully compatible with conventional manufacturing processes and technologies. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.