3D integrated circuit structure, semiconductor device and method of manufacturing same

The present invention discloses a semiconductor device. In one embodiment, the semiconductor device comprises a substrate, a diffusion stop layer formed on the substrate, an SOI layer formed on the diffusion stop layer, an MOSFET transistor formed on the SOI layer, and a TSV formed in a manner of penetrating through the substrate, the diffusion stop layer, the SOI layer, and a layer where the MOSFET transistor is located; and an interconnect structure connecting the MOSFET transistor and the TSV.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor manufacturing, and in particular, to a three-dimension (3D) integrated circuit structure and a method of manufacturing the same.

BACKGROUND OF THE INVENTION

Conventional devices will be scaled down to its physical limitations in 10-15 years. However, during this period, new device structures, for example carbon nanotubes (CNT), spintronic devices and molecular switches, etc, may not be developed to a level of practical application. Therefore, in such a case where copper and low k dielectric materials are used for integration, new methods for device-level and system-level assembly are sought for industrial applications, so as to meet recent demands. Three-dimension (3D) integrated circuits (ICs) are the most advanced technique, which may shorten the length of interconnects, thereby improving speed of circuits, reducing power consumption, and increasing system storage bandwidth.

The current 3D IC integration is described as a system-level architecture formed by combination of a plurality of wafers, wherein each wafer is a stack of a plurality of planar device layers interconnected in a Z direction by though-silica-vias (TSVs). With the application of 3D ICs, the size of TSVs will be scaled continuously, the thickness of silicon layer will also be thinned, and the 3D integration circuits will be more widely used.

However, in some processes of forming a 3D integrated circuit structure, for example in a process of forming a TSV, metal materials such as copper, aluminum, and tungsten, etc., will be filled into the TSV. Besides, in a process of grinding the bottom of a wafer to expose the metal material in the TSV so as to be bonded with other wafers, the metal material or other dopants, for example metal ions such as iron and sodium, etc, exposed at the bottom of the TSV, will be diffused into the metal oxide semiconductor field effect transistor (MOSFET) in the wafer because of the grinding process. Further, in the following process of inter-bonding of wafers, the above variety of metal ions are rapidly diffused into the MOSFET due to the bonding high temperature. Thus, failures will occur to the formed MOSFET.

SUMMARY OF THE INVENTION

An objective of the present invention is to solve at least one of the above problems in the prior art.

Therefore, according to an embodiment of the present invention, there is provided a 3D integrated circuit structure, a semiconductor device, and a method of manufacturing thereof, so as to enhance the performance of 3D integrated circuit.

According to an aspect of the present invention, an embodiment of the present invention provides a 3D integrated circuit structure, comprising: a first wafer, comprising: a substrate; a diffusion stop layer formed on the substrate; a silicon-on-insulator (SOI) layer formed on the diffusion stop layer; a metal oxide semiconductor field effect transistor (MOSFET) formed on the SOI layer; a through-silicon-via (TSV) formed in a manner of penetrating through the substrate, the stop diffusion layer, the SOI layer and a layer where the MOSFET transistor is located; and a first interconnect structure for connecting the MOSFET transistor and the TSV; wherein the bottom of the first wafer is ground to expose the TSV filled with a metal material, and the bottom of the first wafer is connected to external circuits or a second interconnect structure of a second wafer by means of the TSV

According to another aspect of the present invention, an embodiment of the present invention provides a method of forming a 3D integrated circuit, comprising the following steps: forming a first wafer, wherein forming the first wafer comprises: forming a first wafer, wherein forming the first wafer comprises: forming a substrate; forming a diffusion stop layer on the substrate; forming an SOI layer on the diffusion stop layer; forming an MOSFET transistor on the SOI layer; forming a TSV in a manner of penetrating through the substrate, the stop diffusion layer, the SOI layer and a layer where the MOSFET transistor is located; and forming an interconnect structure for connecting the MOSFET transistor and the TSV; grinding the bottom of the first wafer to expose the TSV filled with a metal material; and connecting the bottom of the first wafer to external circuits or an interconnect structure of a second wafer by means of the TSV.

According to a further aspect of the present invention, an embodiment of the present invention provides a semiconductor device, comprising: a substrate; a diffusion stop layer formed on the substrate; an SOI layer formed on the diffusion stop layer; an MOSFET transistor formed on the SOI layer; a TSV formed in a manner of penetrating through the substrate, the stop diffusion layer, the SOI layer and a layer where the MOSFET transistor is located; and an interconnect structure for connecting the MOSFET transistor and the TSV.

In the present invention, for an MOSFET device constructed on the SOI layer, by setting a diffusion stop layer beneath the SOI layer, metal materials filled in the TSV or ions of other metal dopants in a wafer may be prevented from being diffused into the MOSFET transistor in the grinding of the wafer and the subsequent wafer bonding process, thereby providing an MOSFET device with a better performance and a 3D integrated circuit constructed of the same.

Additional aspects and advantages of the present invention will be partially provided in the following description, and will become partially apparent from the following description or understood through implementation of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the embodiments of the present invention will be described in detail. Examples of the embodiments are illustrated in the drawings, across which the same or like reference numbers indicate the same or like elements or elements with the same or like functions. The embodiments described hereinafter with reference to the drawings are exemplary and only for explaining the present invention, which should not be interpreted as limitations to the present invention.

The following disclosure provides a plurality of different embodiments or examples to achieve different structures of the present invention. To simplify the disclosure of the present invention, description of the components and arrangements of specific examples is given below. Of course, they are only illustrative and not limiting the present invention. Moreover, in the present invention, reference numbers and/or letters may be repeated in different embodiments. Such repetition is for the purposes of simplification and clearness, and does not denote the relationship between respective embodiments and/or arrangements being discussed. In addition, the present invention provides various examples for specific process and materials. However, it is obvious for a person of ordinary skill in the art that other process and/or materials may alternatively be utilized. Furthermore, the following arrangement in which a first object is “on” a second object may include an embodiment in which the first object and the second object are formed to be in direct contact with each other, and may also include an embodiment in which another object is formed between the first object and the second object such that the first and second objects might not be in direct contact with each other.

Referring toFIGS. 1ato1e, these diagrams show sectional structures of different phases in a process of manufacturing a wafer for a 3D integrated circuit according to an embodiment of the present invention.

As shown inFIG. 1a, the wafer device comprises a substrate2. In an embodiment of the present invention, the substrate2may comprise any semiconductor substrate material, specifically, but not limited to, a bulk wafer. The wafer device further comprises a first oxide layer4formed on the substrate2. The first oxide layer4may be a relatively thin oxide layer formed on the substrate2through a deposition process known in the art, with a thickness of 5-10 nm. The purpose for setting the first oxide layer4is to improve the contact performance of the substrate2and the subsequently formed diffusion stop layer6. Of course, the present invention is not limited to this embodiment. For example, in an embodiment, this wafer device may not comprise a first oxide layer4. Instead, a diffusion stop layer6for preventing the diffusion of metal ions is deposited on the first oxide layer4.

In an embodiment, the diffusion stop layer6is a nitride layer. The nitride has good compactness and thus may better prevent diffusion of metal ions. The nitride includes, but not limited to, Si3N4or SiCN. It may be insufficient for a too thin nitride deposited to preventing diffusion of metal ions. However, a too thick nitride may generate too large capacitance. In an embodiment, the thickness of the deposited nitride may be in the range between 5-100 nm.

A second oxide layer8may be further deposited on the diffusion stop layer6. The second oxide layer8may a relatively thick oxide layer, with a thickness of 5-200 nm. The purpose for setting the second oxide layer8is to reduce capacitance. Through the above steps, the wafer structure as shown inFIG. 1ais obtained. Of course, the present invention is not limited to this embodiment, For example, in an embodiment, this wafer device may not comprise the second oxide layer8.

As shown inFIG. 1b, a silicon-on-insulator (SOI) layer10is formed on the wafer structure formed inFIG. 1a. The SOI layer10may be bonded with the second oxide layer8by the method of for example smart-cut, thereby providing the SOI layer10on the top of the wafer structure. Then, a metal oxide semiconductor field effect transistor (MOSFET)14and its back end of line (BEOL)16are constructed on the SOI layer10. The BEOL structure16may be a copper interconnect formed by a metal wiring process. The MOSFET transistor14and its BEOL structure16are formed in the oxide layer12deposited on the SOI layer10. Here, the construction of the MOSFET transistor14and its BEOL structure16may utilize any applicable method known in the art.

FIG. 1cshows a diagram of the sectional structure for the formation of a through-silicon-via (TSV) in the semiconductor structure as shown inFIG. 1b. Steps of forming the TSV comprising: a via17is formed penetrating through the substrate2, the first oxide layer4, the diffusion stop layer6, the second oxide layer8, the SOI layer10, and the oxide layer12where the MOSFET transistor14is located. The via17may be formed by dry etching, for example reactive ion plasma etching, etc. Then, an isolating layer18may be formed on the sidewalls of the via17, for example, by depositing insolating materials such as an oxide or Si3N4 in the via17. Next, a buried layer20may be deposited on the sidewalls of the isolating layer18. The buried layer20may prevent the conductive metal material filled in the via17from migrating outwards to enter into the semiconductor device to thereby degrade the performance of the MOSFET transistor14in the subsequent processes. In an embodiment, the materials for the buried layer20may be selected from a group of Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW, WN and any combination thereof.

Finally, a conductive material22for example, metals like Copper (Cu), aluminum (Al), or tungsten (W), or a conductive polymer, metallic silicide, etc, is filled in the via17, thereby forming the TSV for interconnecting of the 3D integrated circuit wafers. In an embodiment of the present invention, the conductive material22is a metal material. Then, planarization and chemical-mechanical polishing (CMP) are performed to the metal material deposited in the via17, thereby forming the TSV. The TSV may be formed by any appropriate processing method in the prior art, and detailed description thereof is omitted here.

FIG. 1dshows a structural diagram of an interconnect structure connecting the MOSFET transistor14and the TSV, wherein the interconnect structure comprises a via26formed above the TSV and communicated with the TSV, a via24formed above a BEOL structure16corresponding to the MOSFET transistor14, and a metal interconnect line28connecting the via24and the via26. Thus, the TSV may be connected to the MOSFET transistor14by the above interconnect structure. Therefore, 3D integrated circuit structures may be implemented by further connecting the interconnect structure of this wafer with the corresponding interconnect structure of other wafers for multiple-wafer connection.

In order to connect the wafer device having the structure ofFIG. 1dwith other wafers, so as to form a 3D integrated circuit, supply power to the formed 3D integrated circuit, or perform input/output (I/O) of the external signals, the TVS at the bottom of the corresponding wafer is required to be grinded or thinned, to expose the metal material in the TSV for corresponding conductive connection.

As shown inFIG. 1e, it is necessary to turn the wafer device over to perform a grinding or thinning processing to its bottom, so as to expose the metal material22in the TSV at the bottom of the wafer. Thus, the exposed metal ions will be diffused into the wafer from the bottom in this grinding process. By means of the diffusion stop layer6of the present invention, the metal ions is blocked from entering into the SOI layer10and further into the MOSFET transistor14thereabove. Thus, the reliability of the MOSFET transistor14may be enhanced.

Through the above steps, the wafer device100for 3D integrated circuits as shown inFIG. 1eis obtained.

FIGS. 2 and 3illustrate partial structures of a 3D integrated circuit of a first embodiment formed by using the wafer device100of the embodiment ofFIG. 1.

InFIG. 2, a diagram of the connection of the formed wafer device100for the 3D integrated circuit to an external circuit300is shown. Here, the external circuit300may be an external power source or external signal I/O. As shown inFIG. 2, a conductive material22exposed from the wafer device100is connected to the external circuit300, thereby supplying power to the 3D integrated circuit or performing external signal transmission.

InFIG. 3, besides the connection of the wafer device100for the 3D integrated circuit to the external circuit300, a diagram of the connection for the wafer device100to another wafer device200of the 3D integrated circuit is also provided. As shown inFIG. 3, the wafer device200is turned over, with a via42being provided thereon, the via42being connected to a BEOL43of a MOSFET transistor45constructed on the wafer device200. The MOSFET transistor45, the BEOL43, and the via42of the wafer device200are constructed in the same manner as that of the wafer device100, i.e., the MOSFET transistor45is disposed in an oxide layer46above the SOI layer44, and the via42is disposed in the oxide layer48above the oxide layer46.

Thus, the wafer100is connected to the via42through its interconnect structure (i.e., the vias24,26and the metal interconnect line28), such that the TSV of the wafer device100is connected to the wafer device200, i.e., connecting the wafer device100and the wafer device200in a top-to-bottom manner, thereby implementing a multiplewafer stacking structure of the 3D integrated circuit.

In an embodiment, the wafer device200may have the same semiconductor structure arrangement as the wafer device100. Thus, when the bottom of the wafer device200is bonded with other wafers for forming the 3D integrated circuit, the metal ions exposed from the TSV at the bottom may also be prevented from being diffused into its MOSFET device45by means of the diffusion stop layer arranged inside. The diffusion stop layer may prevent diffusion of the metal ions into the MOSFET device45more effectively especially in the high-temperature bonding process.

FIG. 4is a diagram of a partial structure of a 3D integrated circuit of a second embodiment formed by using the wafer device100of the embodiment ofFIG. 1.

InFIG. 4, the connection of the wafer device100for the 3D integrated circuit to another wafer device400is provided. As shown inFIG. 4, the wafer device400is turned over, with a via52being provided thereon, the via52being connected to a BEOL53of a MOSFET transistor55constructed on the wafer device400. The MOSFET transistor55, the BEOL53, and the via52of the wafer device400are constructed in the same manner as those of the wafer device100, i.e., the MOSFET transistor55is disposed in an oxide layer56above the SOI layer54, and the via52is disposed in the oxide layer58above the oxide layer56.

Thus, the wafer100is connected to the via52through the metal conductive material exposed from its TSV, such that the TSV of the wafer device100is connected to the wafer device200, i.e., connecting the wafer device100and the wafer device400in a bottom-to-top manner, thereby implementing a multiple-wafer stacking structure of the 3D integrated circuit. The diffusion stop layer may prevent diffusion of the metal ions to the MOSFET device14more effectively especially in a high-temperature bonding process.

In an embodiment, the wafer device400may have the same semiconductor structure arrangement as the wafer device100. Thus, when the bottom of the wafer device400is further bonded with other wafers for forming the 3D integrated circuit or an external circuit, the metal ions exposed from the corresponding bottom TSV may be prevented from being diffused into its MOSFET device14by means of a diffusion stop layer arranged inside.

In the present invention, for an MOSFET device constructed on the SOI layer, by setting a diffusion stop layer, metal materials filled in the TSV, such as Cu, Al, W, etc, or other metal dopants in a wafer, for example ions of Fe, Na, etc., may be prevented from being diffused into the MOSFET transistor in the grinding of the wafer and the subsequent wafer bonding process, thereby providing an MOSFET device with a better performance and a 3D integrated circuit constructed of the same.

Though embodiments of the present invention have been illustrated and described, to a person of normal skill in the art, it may be understood that various variations, modifications, alternations and transformations may be conducted to these embodiments without departing from the principle and spirit of the present invention, and the scope of the present invention is defined by the appending claims and their equivalents.