Integrated antenna package and manufacturing method thereof

An integrated antenna package including a laminated structure and a multi-layered substrate is provided. The laminated structure includes at least a chip embedded therein and at least a plated through-hole structure penetrating the laminated structure. The multi-layered substrate is stacked on the laminated structure. The multi-layered substrate includes at least a metal layer located on one side of the multi-layered substrate away from the laminated structure and the metal layer includes at least an antenna pattern located above the chip. The multi-layered substrate includes at least a plated via and through-hole structure penetrating the multi-layered substrate and electrically connected to the chip, so that the antenna pattern is electrically connect with the chip. Also, the manufacturing method of the integrated antenna package is provided.

TECHNICAL FIELD

1. Field of the Invention

The present disclosure generally relates to a package structure and a manufacturing method thereof, and particularly relates to an integrated antenna package and the manufacturing method thereof.

2. Description of Related Art

Ever since the application of wireless receivers recently becomes the focus in the Consumer Electronics Show, it declares the coming of Wireless Gigabit Alliance (WiGi) and wireless high-definition (HD) standard applications. Although many manufacturers have developed chips of the millimeter-wave band (radio-frequency chips), there is no comprehensive solution regarding the package for the chips of the millimeter-wave band.

Traditional wire-bonding packages are not suitable for packaging radio frequency (RF) chips. However, for the low temperature co-fired ceramic (LTCC) and flip-chip packages, because of the substrate shrinkage caused by the process conditions and low process efficiency as well as very small pad sizes and pitches for the chips to be packaged, the yield of the package is unsatisfactory. It is advantageous to develop an integrated package of the antenna and RF chip(s).

SUMMARY

The present disclosure provides an integrated antenna package structure incorporating the radio frequency chip(s) and the antenna pattern(s). As the antenna pattern is arranged above or below the chip, the vertical arrangement helps to integrate the chip and the antenna pattern through vertical connection structure(s). By arranging the position of the antenna pattern vertically aligned with the position of the chip, the electrical connection structures electrically connect the RF chip(s) with the antenna pattern(s) located at different layers of the package structure, which shortens the signal transmission path and reduces the signal transmission loss.

The embodiment of the present disclosure provides a method for manufacturing an integrated antenna package. After providing a first metal layer, a chip is disposed on the first metal layer. The chip includes a first contact pad and a second contact pad, wherein the first contact pad and the second contact pad faces the first metal layer, and the first contact pad and the second contact pads are electrically connected with the first metal layer. A multilayer board is press laminated over the first metal layer and the chip. The multilayer board comprises a filling layer and a second metal layer, and the second metal layer is disposed on the filling layer and electrically connected to the first metal layer and the chip is embedded within the filling layer. After patterning the first metal layer, a multi-layered substrate is disposed to cover the patterned first metal layer, and one side of the multi-layered substrate away from the first patterned metal layer has a third metal layer. A through-hole is formed penetrating the multi-layered substrate and terminating at the patterned first metal layer electrically connected to the first contact pad. A plated via structure is then formed in the through-hole and the plated via structure connects the third metal layer and the first contact pad. The second metal layer and the third metal layer are patterned to form a patterned second metal layer and a patterned third metal layer, and the patterned third metal layer includes an antenna pattern located beneath the chip. The antenna pattern is electrically coupled to the chip through the plated via structure.

The embodiment of the present disclosure provides an integrated antenna package structure comprising a laminated structure and a multi-layered substrate. The laminated structure comprises a first metal layer, a second metal layer, a filling layer between the first metal layer and the second metal layer and at least one chip. The at least one chip is embedded within the filling layer, and the chip has a first contact pad and a second contact pad. The first metal layer and the first and second contact pads and the second metal layer are electrically connected. The multi-layered substrate is stacked on the laminated structure and covers over the first metal layer. The multi-layered substrate at least includes an insulating layer and a third metal layer, the third metal layer is located on one side of the multi-layered substrate away from the laminated structure and the metal layer includes at least an antenna pattern located below the chip. The multi-layered substrate includes at least a plated via structure penetrating through the multi-layered substrate and connected with the first contact pad, so as to electrically connect the antenna pattern with the chip.

DESCRIPTION

FIGS. 1 to 6show schematic cross-sectional views of process steps of a method for forming an integrated antenna package in accordance with an embodiment of the present disclosure.

Referring toFIG. 1, a carrier plate120is provided. Next, a first metal layer110is attached to the carrier plate120by lamination, and the first metal layer110is attached to the carrier plate120through an adhesive layer130. The bonding surface of the first metal layer110may have a release layer140, and the release layer140only partially covers the bonding surface, so that the first metal layer110is partially bonded to the carrier plate120through the release layer140and the adhesive layer130.

Referring toFIG. 1, an underfill150is then formed on the first metal layer110. The chip160is disposed on the underfill150, and the chip160is attached to the first metal layer110through the underfill150. The chip160has an active surface160aand a first contact pad162and a second contact pad164formed on the active surface160a. The active surface160aof the chip160is arranged downward and attached to the first metal layer110(i.e. the active surface160afacing the first metal layer110). Next, the underfill150is cured, and the chip160is fixed onto the first metal layer110.

Subsequently, as shown inFIG. 2, a multilayer board170is provided and covers over the first metal layer110and the chip160by press lamination. The multilayer board170includes at least a first filling layer172and a second metal layer174formed on the first filling layer172. The first filling layer172may include a core (plate) and prepregs. Because the prepreg is a semi-cured adhesive sheet impregnated in resins, the chip160can be enveloped within the multilayer board170by press lamination. The second metal layer174may be a resin-coated copper foil (RCC) or a copper foil. The resin-coated copper foil is a copper foil coated with at least one layer of the adhesive resin, and the adhesive resin layer can function as either an insulating layer or an adhesive layer, which can improve the binding between the copper foil and the substrate during press lamination. The material of the first filling layer172may include the Ajinomoto build-up film (ABF) or bismalemide triazine (BT).

Thereafter, following the press lamination, as shown inFIG. 2, the first filling layer172of the multilayer board170encapsulates the chip160and the second metal layer174is located above the first filling layer172and the chip160. Then, the carrier plate120is partially removed by removing the release layer140, so that the release layer140and the adhesive layer130and the carrier plate120beneath the release layer140are removed and separate from the first metal layer110. Next, a first borehole112and a second borehole114are formed in the first metal layer110penetrating through the first metal layer110, and the first borehole112exposes the first contact pad162and the second borehole114exposes the second contact pad164. The first borehole112and the second borehole114may be formed by laser drilling, for example.

Reference toFIG. 3, the remained adhesive layer130and the carrier plate120are removed, and a via filling process is performed to fill up the boreholes to respectively form a first metal filled via structure182and a second metal filled via structure184within the first borehole112and the second borehole114. The via filling process may be a copper electroplating via filling process, and the formed first and second metal filled via structures may be copper filled via structures (copper plugs). In the present embodiment, laser drilling is used to form the first borehole112and the second borehole114, and the via filling process is applied to fill the boreholes to form the first and second metal filled via structures182,184in the first and second boreholes112,114. Compared to the cylindrical stud bump used for connecting the chip and the package substrate having a height of approximately 80 μm, the first and second metal filled via structures182,184filled in the boreholes have a smaller height of no more than 40 μm, thereby reducing the overall height of the package structure. Also, by fouling the metal filled via structures, instead of the bumps, the high frequency parasitic effects caused by the bumps may be avoided and the electrical performance can be enhanced.

Referring toFIG. 4, at least one through-hole190is formed, penetrating through the first metal layer110and the multilayer board170. The through-hole190is formed by mechanical drilling, for example. Then, a plated through-hole structure192is formed in the through-hole190by electroplating, and the plated through-hole structure192electrically connects the first metal layer110and the second metal layer174. The plated through-hole structure192may be formed by, for example, a copper plating process.

Referring toFIG. 5, the first metal layer110is patterned to form a patterned first metal layer110a. So far, a lamination of the multilayer board170, the plated through-hole structure192, the chip160, the first and second metal filled via structures182,184and the patterned first metal layer110acan be viewed as the laminated structure177embedded with the chip160.

Referring toFIG. 6, a multi-layered substrate200is provided and covers over the patterned first metal layer110a. The multi-layered substrate200comprises at least an insulating layer230and a third metal layer210on the insulating layer230. The opposite side of the third metal layer210of the multi-layered substrate200is covered to the patterned first metal layer110aand then press laminated. The insulating layer230may further include at least one wiring layer220, located between the third metal layer210and the patterned first metal layer110a. The wiring layer220can be used as a ground layer. After the press lamination, a through-hole240is formed, penetrating through the multi-layered substrate200until the surface of the first metal filled via structure182is exposed. Subsequently, a plated via structure242is formed by electroless plating within the through-hole240, so that the third metal layer210is electrically connected to the first metal filled via structure182. Next, the second metal layer174and the third metal layer210are patterned to form a patterned second metal layer174aand a patterned third metal layer210a. Referring toFIG. 6, the patterned third metal layer210aincludes an antenna pattern211located below the chip160, and the patterned second metal layer174acomprises at least a plurality of bonding pads175. The through-hole240may be formed by mechanical drilling and laser drilling, for example, and may be formed by mechanical drilling a blind hole in the multi-layered substrate200and then continue drilling the aforementioned blind hole by laser drilling through the entire multi-layered substrate200. Thus, the through-hole240can be formed accurately to stop at the surface of the first metal filled via structure182. Finally, the solder balls or connectors are bonded to the bonding pads175and are electrically connected to the plated through-hole structure192. The solder balls or the connectors can be further connected to an external printed circuit board. In this embodiment, as the antenna pattern211is formed right above the location of the chip160and the plated via structure242is formed to directly electrically connect the antenna pattern211and the chip160, the signal transmission path is shortened and the high-frequency signal loss caused by wire bonding between the chip160and the antenna pattern211may be avoided, further lessening the signal loss along the transmission path.

FIGS. 7A and 7Bshow schematic cross-sectional views of an integrated antenna package in accordance with a first embodiment of the present disclosure.

With reference toFIGS. 7A and 7B, following the above manufacturing method, the integrated antenna packages70A and70B are obtained; each integrated antenna package comprises the laminated structure177and the multi-layered substrate200. The laminate structure177includes the patterned first metal layer110a, the patterned second metal layer174a, a filling layer172located between the patterned first and second metal layers and at least one chip160. The chip160is embedded within the filling layer172, and the chip160has an active surface160a, the first contact pad162and the second contact pad164. The first metal filled via structure182and the second metal filled via structure184respectively filled within the first and second boreholes of the patterned first metal layer110aare respectively connected to the first contact pad162and the second contact pad164. The laminated structure177includes at least one plated through-hole structure192, penetrating through the patterned first metal layer110a, the filling layer172and the patterned second metal layer174aand electrically connected the patterned first metal layer110aand the patterned second metal layer174a.

Referring toFIGS. 7A and 7B, the multi-layered substrate200is laminated on top of the laminated structure177and covers the first metal layer110a. The multi-layered substrate200comprises at least one insulating layer230and the patterned third metal layer210aon the insulating layer230. The patterned third metal layer210ais located on one side of the multi-layered substrate200away from the first metal layer110aand includes at least one antenna pattern211. The antenna pattern211is located above the chip160. Here, whether it is described to be above or beneath in the context, it depends on the placement direction of this package, and the artisan in this field understands that the position of the antenna pattern is mainly aligned with the position of the chip. Basically, the distribution area of the antenna pattern211should be equal to or greater than that of the underlying chip, but the positions of these two should coordinate. In addition, the multi-layered substrate200includes a through-hole240, penetrating through the multi-layered substrate200and terminating at the first metal layer110acorresponding to the first metal filled via structure182. The plated via structure242formed in the through-hole240electrically connects the antenna pattern211and the chip160. Moreover, the patterned second metal layer174amay comprise at least a plurality of bonding pads175. InFIG. 7A, the solder balls300provided on the bonding pads175are electrically connected to the plated through-hole structure192, and the solder balls300may further be connected to an external printed circuit board.

In another embodiment, with reference toFIG. 7B, the connector400may also be provided over the bonding pads175and electrically connected to the plated through-hole structure192. However, between the connector400and the package structure70B, additional connecting structures, such as multi-layer laminated structure or a single layer structure, a redistribution layer or a wiring layer (shown as dotted line), may be provided, and the present embodiment is not limited thereto. Through the additional connecting structures, the connector400is not limited to be located directly below the package70B. The connector400may be further connected to an external printed circuit board, or connected to the bonding pad(s)175.

The multi-layered substrate200further includes a wiring layer220located within the insulating layer230and between the antenna pattern211and the patterned first metal layer110a. The insulting layer (second filling layer)230is filled between the antenna pattern211, the wiring layer220and the patterned first metal layer110a. The wiring layer220may function as a ground layer or a redistribution layer. Finally, the solder balls300or the connector400are disposed on the patterned second metal layer174a, so that the solder ball300or the connector400at least connects to one plated through-hole structure192. The solder balls300or the connector400may further connect to an external circuit board.

FIG. 8shows a schematic cross-sectional view of an integrated antenna package in accordance with a second embodiment of the present disclosure. Similar to the package structure70A, for the integrated antenna package80in this embodiment, as shown inFIG. 8, the multi-layered substrate200includes wiring layers222and224, located within the insulating layer230and located between the antenna pattern211and the patterned first metal layer110a. One of the two wiring layers222&224functions as a redistribution layer and the other layer functions as a ground layer. The ground layer (plane) may also function as a shielding layer to protect the chip160from excessive electromagnetic interference (EMI), thus lessening the interference to the operation of the integrated antenna package. The scope of the present disclosure is not limited to the relative arrangements of the wire layer and the ground/shielding layer(s) as described in the embodiments, and the redistribution layer may be located above or below the ground/shielding layer(s). The integrated antenna package structure80may further include a metal filled via structure270connecting the wiring layer222, and the first metal filled via structure182, and a metal filled via structure280connecting the wiring layer222and the plated through-hole structure192. Through the arrangement of disposing one or more layers of wiring layers, the package structure can integrate more components or the layout design of the wirings or traces may be more flexible.

FIG. 9shows a schematic cross-sectional view of an integrated antenna package in accordance with a third embodiment of the present disclosure. Similar to the package structure70A, for the integrated antenna package90in this embodiment, as shown inFIG. 9, the chip160further includes a third contact pad166, and a third metal filled via structure186filled within a third borehole of the patterned first metal layer110ais connected with the third contact pad166. In addition, the multi-layered substrate200of the integrated antenna package structure90further includes a through-hole250penetrating through the multi-layered substrate200and terminating at the second metal filled via structure184and a plated via structure252formed within the through-hole250. Further, the patterned third metal layer210acomprises the antenna pattern211aand the antenna pattern211bpositioned above the chip160. The plated via structure242electrically connects the antenna pattern211aand the chip160, while the plated via structure252electrically connects the antenna pattern211band the chip160.

FIG. 10shows a schematic cross-sectional view of an integrated antenna package in accordance with a fourth embodiment of the present disclosure. Compared to the package structure90, the integrated antenna package100provided in this embodiment100has a through-hole250′ penetrating through the wiring layer220and the insulating layer230of the multi-layered substrate200and a plated via structure252′ formed within the through-hole250′ electrically connects the chip160and the wiring layer220. In addition, the multi-layered substrate200has a plated through-hole structure262penetrating through the patterned third metal layers210a, the insulating layer230and the wiring layer220, and the plated through-hole structure262electrically connects the wiring layer220and the antenna pattern211b. In other words, through the plated via structure252′ and the plated through-hole structure262, the chip160is electrically connected with the antenna pattern211b. Furthermore, the multi-layered substrate200of the package structure100further includes a plated through-hole structure292penetrating through the patterned third metal layers210a, the insulating layer230and the wiring layer220, and the plated through-hole structure292may offer the functions of grounding and shielding.

In the foregoing embodiments of the present disclosure, although only one or two antenna patterns, only one chip, and/or only two or three contact pads per chip are shown in the drawings, the scope of the present disclosure is not limited thereto, and the integrated antenna package can be configured to have multiple chips or multiple antenna patterns, and the chip may include a plurality of contact pads. In these embodiments, the chip160may be a radio frequency (RF) chip, the material of the first, second or third metal layer may include aluminum, copper, nickel, gold or silver, or combinations thereof. The antenna pattern may be a radio frequency antenna pattern, such as a patch antenna. According to the preferred embodiment, the antenna pattern is an antenna operated at the 77 GHz band.

In summary, for the 110 GHz band, compared to the insertion loss of 1.6 dB for the conventional package structure connecting the RF chip to the package substrate using flip-chip bonding and bumps, the insertion loss of the integrated antenna package structure of the present disclosure is lowered to be 1.0 dB by using the metal via-filled structure(s) formed within the borehole(s) of the metal layer for electrically connecting the embedded chip and the metal layer. Accordingly, for the integrated antenna package structure of the present disclosure that incorporates the embedded RF chip without using the bumps for connection, the feed-in insertion loss is at least 37.5% lower.

For the integrated antenna package structure of the present disclosure, the electrical connection structures formed within the borehole(s) and the through-hole(s) are utilized to electrically connect the RF chip(s) with the antenna pattern(s) located at different layers of the laminate structure, which shortens the signal transmission path and reduces the signal transmission loss. In the present disclosure, as the antenna pattern is arranged above or below the chip, the vertical arrangement helps to integrate the chip and the antenna pattern through vertical connection structure(s) so as to shorten the transmission distance between the antenna pattern(s) and the chip(s), thereby reducing the power loss and improving the performance of the package or the module for millimeter wave applications.