Systems and methods for feedforward process control in the manufacture of semiconductor devices

A method for process control in the manufacture of semiconductor devices including performing metrology on at least one Design of Experiment (DOE) semiconductor wafer included in a lot of semiconductor wafers, the lot forming part of a batch of semiconductor wafer lots, generating, based on the metrology, one or more correctables to a process used to manufacture the lot of semiconductor wafers and adjusting, based on the correctables, the process performed on at least one of; other semiconductor wafers included in the lot of semi-conductor wafers, and other lots of semiconductor wafers included in the batch.

FIELD OF THE INVENTION

The present invention relates generally to metrology and more particularly to the measurement of misregistration in the manufacture of semiconductor devices.

BACKGROUND OF THE INVENTION

Various systems and methods for the measurement of misregistration in the manufacture of semiconductor devices are known in the art.

SUMMARY OF THE INVENTION

The present invention seeks to provide novel systems and methods for feedforward control in the processing of semiconductor devices, based on misregistration measurements performed on Design of Experiment (DOE) semiconductor wafers.

There is thus provided in accordance with a preferred embodiment of the present invention a method for process control in the manufacture of semiconductor devices including performing metrology on at least one Design of Experiment (DOE) semiconductor wafer included in a lot of semiconductor wafers, the lot forming part of a batch of semiconductor wafer lots, generating, based on the metrology, one or more correctables to a process used to manufacture the lot of semiconductor wafers and adjusting, based on the correctables, the process performed on at least one of: other semiconductor wafers included in the lot of semiconductor wafers, and other lots of semiconductor wafers included in the batch.

Preferably, the process includes a lithographic patterning process performed by a lithographic patterning tool.

Preferably, the metrology includes measurement of misregistration between layers of the DOE semiconductor wafer.

Preferably, the method also includes performing the process used to manufacture the lot of semiconductor wafers during the performing of the metrology, prior to the adjusting of the process.

Preferably, the method also includes generating the DOE semiconductor wafer prior to the performing of the metrology thereon.

Preferably, the generating the DOE semiconductor wafer includes varying at least one DOE parameter across the DOE semiconductor wafer.

Preferably, the DOE parameter includes one of misalignment of targets used for measurement of misregistration between layers of the DOE semiconductor wafer and other parameters related to misregistration between the layers of the DOE semiconductor wafer.

Preferably, the other parameters related to misregistration include parameters of the lithography patterning tool including translation, rotation, focus and dose.

Preferably, the varying of the DOE parameter includes at least one of varying the DOE parameter per field of the DOE semiconductor wafer and per die of the DOE semiconductor wafer.

Additionally or alternatively, the method also includes generating, based on the metrology, one or more correctables to performance of the metrology, whereby the performance of the metrology is optimized.

There is also provided, in accordance with another preferred embodiment of the present invention, a system for process control in the manufacture of semiconductor devices including a metrology tool operative to perform metrology on at least one Design of Experiment (DOE) semiconductor wafer included in a lot of semiconductor wafers, the lot forming part of a batch of semiconductor wafer lots, a correctable generator operative to generate, based on the metrology, one or more correctables to a process used to manufacture the lot of semiconductor wafers, and a controller operative to receive the correctables generated by the correctable generator and to controllably adjust the process, in accordance with the correctables, performed on at least one of other semiconductor wafers included in the lot of semiconductor wafers, and other lots of semiconductor wafers included in the batch of lots.

Preferably, the process includes a lithographic patterning process performed by a lithographic patterning tool.

Preferably, the metrology includes measurement of misregistration between layers of the DOE semiconductor wafer.

Preferably, the lithographic patterning tool is operative to perform the process to manufacture the lot of semiconductor wafers during performance of the metrology, prior to the process being adjusted by the controller.

Preferably, the lithographic patterning tool is operative to generate the DOE semiconductor wafer.

Preferably, the lithographic patterning tool is operative to vary at least one DOE parameter across the DOE semiconductor wafer.

Preferably, the DOE parameter includes one of misalignment of targets used for measurement of misregistration between layers of the DOE semiconductor wafer and other parameters related to misregistration between the layers of the DOE semiconductor wafer.

Preferably, the other parameters related to misregistration include parameters of the lithography patterning tool including translation, rotation, focus and dose.

Preferably, the DOE parameter is varied per at least one of a field of the DOE semiconductor wafer and a die of the DOE semiconductor wafer.

Additionally or alternatively, the correctable generator is operative to generate, based on the metrology, one or more correctables to performance of the metrology by the metrology tool, whereby the performance of the metrology tool is optimized.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference is now made toFIG.1, which is a simplified schematic partially pictorial, partially block diagram illustration of a semiconductor wafer processing system including feedforward control, constructed and operative in accordance with a preferred embodiment of the present invention.

As seen inFIG.1, there is provided a semiconductor wafer processing system100preferably including a semiconductor processing tool102, a metrology tool104, a correctable generator106for generating correctables based on the output of metrology tool104and a controller108for controllably adjusting the processing performed by processing tool102in accordance with the correctables generated by correctable generator106.

Processing tool102is preferably operative to process at least one lot110of semiconductor wafers112. Lot110may be a member of a batch of semiconductor wafers including a number of wafer lots preferably, although not necessarily, of the same type as lot110, as is described henceforth with reference toFIG.3. Typically, lot110may include25semiconductor wafers112, although fewer wafers112are illustrated herein for the purpose of succinctness.

Processing tool102is preferably embodied as a lithographic patterning tool, such as a scanner. An example of a processing tool useful in the system ofFIG.1is the ASML scanner 1950i, commercially available from ASML of Veldhoven, Netherlands. During processing, lot110is preferably retained on a stage of processing tool102, typically on two chucks thereon.

Metrology tool104is preferably embodied as a misregistration measurement tool, for measuring misregistration between layers of each of semiconductor wafers112. Metrology tool104may be an imaging type tool or a scatterometry type tool. An example of a metrology tool useful in the system ofFIG.1is the Archer ATL100, commercially available from KLA of California, USA. Processing tool102and metrology tool104are preferably located at a common location such that semiconductor wafers112processed by processing tool102may be readily transferred to metrology tool104for the performance of metrology thereon.

It is a particular feature of a preferred embodiment of the present invention that lot110preferably includes at least one Design of Experiment (DOE) semiconductor wafer120. Here, by way of example, lot110is shown to include two DOE wafers120schematically indicated inFIG.1by hatching in order to distinguish DOE wafers120from the other, non-DOE wafers112included in lot110and manufactured using standard design parameters. In other preferred embodiments of the present invention, lot110may include 2-4 DOE wafers120, for example equally distributed between the two chucks of processing tool102.

Preferably, the one or more DOE wafers120are generated by processing tool102based on variation of DOE parameters across the DOE wafer120. Particularly preferably, the DOE parameters are parameters associated with misregistration of layers of wafer120with respect to each other, which misregistration is preferably measured by metrology tool104. By way of example, the DOE parameter variation may be a shift in the relative locations or pitches of misregistration measurement targets formed on adjacent layers of wafer120so as to deliberately create misregistration therebetween of various magnitudes, such as by 5 nm, 10 nm, 15 nm and so on. The DOE parameter may alternatively be a shift in the locations of misregistration targets, for example with respect to die edges, as well as variation in processing tool102parameters such as, by way of example only, rotation, translation, focus and dose.

Turning additionally toFIG.2, the DOE parameter of DOE wafer120may be varied across DOE wafer120in both an x-direction and a y-direction, as respectively indicated by x- and y-direction DOE parameter variation arrows130and132. Although not illustrated inFIG.2, it is understood that the DOE parameter may be varied at a wafer level, per field of wafer120or may be varied at a field level, per wafer die140. The DOE parameter may be varied in a predetermined continuous or discrete manner within the field and/or die, the variation being preferably repeated between fields and/or dies. Preferably, different. DOE parameters are varied per DOE wafer120included in each lot110. It is understood that, with the exception of the particular DOE parameter varied across DOE wafer120, an other characteristics of DOE wafer120are generally the same as those of other wafers112included in lot110to which DOE wafer120belongs.

Returning toFIG.1, following generation of DOE wafer120by processing tool102, the DOE wafer120is preferably physically transferred to metrology tool104for the performance of metrology thereon and particularly preferably, for the measurement of misregistration between targets formed on layers of DOE wafer120, which misregistration may be deliberately induced in DOE wafer120by way of variation of the DOE parameter thereacross.

Metrology tool104is preferably operative to perform metrology on at least one DOE wafer120and to output a metrology output150. Metrology output150is preferably provided to correctable generator106. Correctable generator106is preferably operative to receive and analyze metrology output150and to generate one or more correctables to the patterning process performed by processing tool102based thereon. Correctable generator106may be operative to generate one or more correctables based on correlating the misregistration as measured by metrology tool104to the actual known induced misregistration on the DOE wafer120. Additionally or alternatively, the correctables may be found by comparing the misregistration measured by metrology tool104to pre-existing models of misregistration and ascertaining differences therebetween. More generally, the correctables may be found by any approach for correlating the metrology output of metrology tool104to the DOE parameter of DOE wafer120, in order to ascertain correctables which may be applied to processing tool102in order to improve the processing of wafers112thereby, and particularly preferably to minimize misregistration between layers thereof.

Correctable generator106is preferably embodied as a hardware or software module, including computer code operative to automatically analyze metrology output150and calculate correctables applicable to the process performed by processing tool102based thereon. It is appreciated that although correctable generator106is illustrated inFIG.1as a separate module, outside of both metrology tool104and processing tool102, the functionality of correctable generator106may alternatively be included therein. It is further appreciated that correctable generator106may be a cloud-based module, in wireless communication at least with metrology tool102.

It is understood that during the performance of metrology on DOE wafer120by metrology tool104, as well as during the analysis of metrology output150by correctable generator106, processing tool102preferably, although not necessarily, continues to process other wafers112included in lot110in accordance with the non-adjusted processing parameters thereof.

Correctable generator106is preferably operative to output processing tool correctables170and to provide processing tool correctables170to controller108. Controller108is preferably operative to receive processing tool correctables170and to adjust the process performed by processing tool102in accordance with processing tool correctables170. It is appreciated that such adjustment is preferably carried out during the processing of other wafers112of lot110by processing tool102, such that the correctables found by correctable generator106based on DOE wafer120of a given lot are immediately applied to the processing tool102during processing of that given lot, in order to improve the processing of other wafers112within the same lot as DOE wafer120. Additionally or alternatively, such adjustment may be carried out during the processing of other lots of semiconductor wafers included the same batch as that to which lot110including DOE wafer120belongs.

It is appreciated that the rapid calculation and provision of correctables to processing tool102, allowing the adjustment of the processing performed by processing tool102within the same lot as that for which the correctables were calculated, is enabled in the present invention due to performance of metrology on at least one DOE wafer120, based on which correctables are calculated. This is in contrast to conventional processing systems, in which metrology measurements are typically performed on nominal wafers selected from a lot of wafers and correctables calculated based on the metrology measurements performed on the nominal wafers. In such conventional processing systems, the performance of metrology and calculation of correctables is relatively slow, such that adjustments to the processing tool are not feasible within the present lot for which the metrology is performed, but rather only applied to subsequent lots. However, in the present invention, metrology is advantageously performed on a DOE wafer, which metrology is both more rapid and more accurate than the performance of metrology on a nominal wafer. The performance of metrology on a DOE wafer is more rapid than that on a nominal wafer at least due to the necessity of sampling fewer sites on the DOE wafer and due to the lower re-work rate. By way of example, the metrology measurements may be performed on the DOE wafer120, correctables derived and the operation of processing tool102adjustably controlled accordingly within a time scale of several minutes, whereas the processing of the entirety of lot110may take several hours.

The feedforward control flow enabled by a system of the type shown inFIG.1is illustrated schematically inFIG.3. As seen inFIG.3, correctables generated based on metrology performed on a DOE wafer120belonging to an initial lot110, here indicated as LOT1, may be applied to other wafers within LOT1, as indicated by an arrow300. Additionally or alternatively, correctables generated based on metrology performed on a DOE wafer120of LOT1are preferably applied to other lots, such as LOT2and LOT N, as respectively indicated by arrows302and304. LOTS1,2and N all preferably belong to the same batch, here shown as BATCH1. It appreciated that feedforward control of the operation of processing tool102, so as to correct the operation of processing tool102within the current lot and/or current batch, improves the throughput of system100by minimizing the misregistration and thus reducing the re-work of wafers112processed thereby.

It is understood that correctables may be calculated per DOE wafer120of lot110and the operation of processing tool102adjusted accordingly, incrementally based on the metrology output per DOE wafer120. Alternatively, the correctables may be calculated per all of the DOE wafers120included in lot110and the operation of processing tool102adjusted based on the collective correctables derived from the metrology outputs for all of the DOE wafers120in a given lot110. It is appreciated that correctables derived based on the metrology output for one DOE wafer120typically differ and may be interdependent with respect to correctables derived based on the metrology output for another DOE wafer120having a different DOE parameter. The interdependency of the correctables may be accounted for by algorithms included in controller108and/or processing tool102.

The adjustments applied to processing tool102by controller108based on correctables170may include adjustments to a range of parameters of processing tool102. For example, in the case that the DOE parameter of DOE wafer120is rotation, the correctable derived may be a correctable to rotation and controller108may adjust the rotation of processing tool102so as to minimize the misregistration of wafers112produced thereby. Further by way of example, in the case that the DOE parameter of the DOE wafer120is induced misregistration by shift of misregistration targets, the correctable derived may be a correctable to the location at which misregistration targets are formed on wafer112.

In accordance with one preferred embodiment of the present invention, in addition to the calculation of correctables to the process performed by processing tool102, metrology performed on DOE120may also optionally be used to calculate correctables for the purpose of optimizing the operation of metrology tool104. This is based on the understanding that the metrology output150of metrology tool104represents the misregistration values of the DOE wafer120only as accurately measured by the metrology tool104, such that settings of the metrology tool104tend to influence the misregistration values measured thereby. As shown inFIG.1, correctable generator106may thus optionally be operative to find metrology tool optimization parameters, based on the metrology output150, and the operation of metrology tool104adjusted based thereon in order to optimize the accuracy of the metrology performed thereby. By way of example, metrology tool104may adjusted to operate in a more internally consistent manner.

Reference is now made toFIG.4, which is a simplified flow chart illustrating steps involved in process control in semiconductor wafer processing, in accordance with a preferred embodiment of the present invention.

As seen inFIG.4, a method400for the feedforward control of semiconductor processing may begin at a first step402, at which wafers of a given lot are processed or patterned by a processing tool, including the generation within the given lot of at least one DOE wafer. As seen at a second step404, the DOE wafer is preferably then transferred to a metrology tool. Preferably, second step404is carried out during the processing of other wafers of the lot as begun at first step402. As seen at a third step406, metrology is performed on the DOE wafer and metrology information collected, as seen at a fourth step408.

As seen at parallel fifth and sixth steps410and412, based on the metrology information collected at fourth step408, correctables respectively related to operation of the processing tool and metrology tool are preferably derived. As seen at fifth step410, correctables to the processing performed by the processing tool are preferably generated. As seen at sixth step412, which may or may not be performed simultaneously with fifth step410, optimized parameters relevant to the performance of the metrology tool may additionally be generated.

Following the performance of fifth step410, the correctables derived at fifth step410are preferably used as a basis for the controlled adjustment of the processing tool during the processing of the same given lot as referenced in first step402, as seen at a seventh step414.

Additionally or alternatively, following the performance of sixth step412, the optimized parameters derived as sixth step412are preferably used as a basis for the controlled adjustment of the settings of the metrology tool in order to improve the operation thereof, as seen at an eighth step416.

It is appreciated that as a result of the performance of metrology on a DOE wafer and the calculation of correctables based thereon, correctables may be rapidly and high accurately calculated in accordance with the preferred method400of the present invention. The correctables found may be used for feedforward control of the operation at least of the processing tool within the same lot or batch for which the correctables were found, thereby improving the throughput of the processing tool.

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. The scope of the present invention includes both combinations and subcombinations of various features described hereinabove as well as modifications thereof, all of which are not in the prior art.