Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines

A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

The present invention relates to a semiconductor memory device and, more 
specifically, to a technique that is effectively used for a defect relief 
circuit in a semiconductor memory device having a twist portion in 
complementary bit lines. 
BACKGROUND OF THE INVENTION 
There is known a dynamic RAM (random access memory) of a type which has 
reserve word lines or bit lines (also called data lines or digit lines) to 
compensate for defective bit lines or data lines. For example, Japanese 
Patent Laid-Open No. 214699/1991 discloses a defect relief technique in 
the above type of dynamic RAM. 
Conventional dynamic RAMs have a problem that a defect is not necessarily 
relieved even if, for instance, a defective word line is replaced with a 
reserve word line. To solve this problem, it may be conceivable to perform 
defect relief by testing reserve word lines to determine whether they are 
defective or not. However, to determine whether reserve word lines are 
defective or not, it is necessary to establish a test mode that is 
different from an ordinary operation and then perform a test by accessing 
memory cells that are connected to reserve word lines or bit lines. 
Therefore, its procedure and test pattern generation are different than 
the case of a usual test pattern. For this reason, in mass-production of 
dynamic RAMs, which requires shortening of a test period, it is presently 
difficult to test every reserve word line or bit line. 
In conventional dynamic RAMs, reserve word lines or bit lines are provided 
in an end portion of a memory mat. In accordance with the present 
invention, it was intended to increase a substantial defect relief 
probability paying attention to the fact that the rate of defect 
occurrence is higher in an end portion of a memory mat than in its central 
portion. Furthermore, in accordance with the present invention, a problem 
was found in that in a dynamic RAM having twisted bit lines in a central 
portion to reduce influences of capacitance coupling between adjacent bit 
lines, if reserve word lines are provided in an end portion of a memory 
mat, unbalance occurs in the numbers of crossing word lines, resulting in 
unbalanced bit line capacitances. 
An object of the present invention is to provide a semiconductor memory 
device which can increase a defect relief probability. 
Another object of the invention is to provide a semiconductor memory having 
an improved operational margin. 
The above and other objects and novel features of the invention will become 
apparent from the description of this specification and the accompanying 
drawings. 
SUMMARY OF THE INVENTION 
In accordance with the invention, a semiconductor memory device is provided 
which is equipped with reserve bit lines or word lines for replacing 
defective bit lines or word lines, wherein the reserve bit lines or word 
lines are provided approximately in a central portion of a memory mat. 
According to the semiconductor memory device of the invention, because of a 
low probability of defect occurrence in the reserve word lines or bit 
lines, the probability of defect occurrence can be made low when a 
defective word line or bit line is replaced with a reserve word line or 
bit line.

DESCRIPTION OF PREFERRED EMBODIMENT 
FIG. 1 is a schematic pattern diagram of an embodiment of a memory mat 
portion of a dynamic RAM according to the present invention. Respective 
circuits and a wiring of FIG. 1 are formed on a single semiconductor 
substrate such as a single crystal silicon by a known semiconductor 
integrated circuit manufacturing process. The respective circuits and the 
wiring of FIG. 1 are drawn so as to approximately conform to their actual 
geometrical arrangement on a semiconductor substrate. 
Word lines WL0-WLn are arranged in parallel with each other so as to extend 
vertically in FIG. 1. Pairs of complementary bit lines extend horizontally 
in parallel and each pair is connected to a pair of nodes (input/output 
nodes) of a sense amplifier SA. In this embodiment, to cancel out an 
influence of capacitance coupling between adjacent bit lines by the 
differential sense amplifier SA, complementary bit lines BL1T and BL1B, 
having an odd number have, are twisted in their central portion, though 
the invention is not intended to be limited to such a case. 
In this embodiment, to increase the defect relief probability by a simple 
configuration, two reserve word lines RWL0 and RWL1 are provided in the 
central portion on the left side of the twist portion, and another two 
reserve word lines RWL2 and RWL3 are provided in the central portion on 
the right side of the twist portion. 
With the above configuration, when viewed from the complementary bit lines, 
the numbers of word lines, including the reserve word lines, that cross 
those bit lines can be made the same. Therefore, the number of memory 
cells connected to the bit lines on the left side of the twist portion and 
that on the right side of the twist portion can be made the same, to 
enable proper balancing of the capacitances and thereby increase the 
operational margin. 
In general, one word line is selected from four word lines selected by a 
unit decoder. Therefore, when the twist portion as described above is 
provided, the part having reserve word lines becomes longer by a pitch of 
four word lines, and the number of memory cells connected to the word 
lines in that part becomes larger to cause an unbalance as mentioned 
above. On the other hand, in the invention, in which two reserve word 
lines can be arranged side by side on each side of the twist portion (four 
word lines in total), it is possible to provide a reserve decoder common 
to those word lines. 
In this embodiment, two pairs of reserve bit lines are provided in the 
central portion of the memory mat as denoted by RBL0T/RBL0B and 
RBL1T/RBL1B. Sense amplifiers SA are provided for the respective pairs of 
complementary bit lines RBL0T/RBL0B and RBL1T/RBL1B, and controlled in the 
same manner as the other sense amplifiers. Therefore, unlike the case of 
the reserve word lines, the sense amplifiers for the reserve bit lines 
RBL0T/RBL0B and RBL1T/RBL1B are rendered in an operational state 
irrespective of whether those bit lines are being used for defect relief. 
Since the bit lines RBL1T and RBL1B of one of the two pairs have a twist 
portion in the central portion, the bit lines, as a whole, maintain 
regularity involving pairs having the twist portion and pairs not having 
it. 
In FIG. 1, a memory cell MC is connected to an intersection (indicated by a 
mark 0) of a word line and a complementary bit line. As is well known, the 
memory cell MC comprises a MOSFET for address selection and a capacitor 
for information storage. The gate of the address selection MOSFET is 
connected to a word line and its source or drain is connected to a bit 
line. The remaining source or drain of the address selection MOSFET is 
connected to one electrode of the capacitor. 
In the above configuration, the probability of defect occurrence is lower 
in the central portion of the memory mat than in its end portion. 
Therefore, the defect relief probability can be increased in a defect 
relief scheme in which when a defect occurs in a certain regular word 
line, it is replaced with a reserve word line indiscriminately, i.e., 
without testing the reserve word lines. Since, as described above, the 
defect relief probability can be increased even without testing the 
reserve word lines, this embodiment can effectively be applied to dynamic 
RAMs etc., which are mass-produced general purpose memories. 
A data scramble logic can be simplified by use of row addresses centering 
the twist portion, as described below. Since the exchange of complementary 
bit lines reverses readout data levels, the data writing and reading for a 
test needs to be performed with correction of the above data level 
reversing by a logical measure. In this type of data scramble processing, 
since the physical levels of the memory cells located on both sides of the 
twist portion are input to the sense amplifier in a reversed manner, it is 
sufficient to perform inversion/non-inversion processing by use of 
high/low levels of a one-bit address corresponding to the twist portion. 
This is effective in a test mode at the time when a defective word line is 
replaced with a reserve word line. 
FIG. 2 is a circuit diagram showing an embodiment of a reserve word line 
selection circuit. A signal XEB turns to a high level when access to a 
defective word line is detected. The signal XEB and a RAS timing signal R2 
are input to a NAND gate circuit G1, and an output signal of the NAND gate 
circuit G1 enables reserve word line selection circuits via an inverter 
circuit N1. 
A signal MSi is a mat selection signal. Signals BX1B/BX1T and BX0B/BX0T 
correspond to address signals of the lower two bits, and serve to select 
one of the four word lines. NAND gate circuits G2-G5 are enabled by the 
output signal of the inverter circuit N1 and the mat selection signal MSi, 
and the internal address signals BX1B/BX1T and BX0B/BX0T are decoded to 
turn one of the reserve word line selection signals XR0B-XR3B to a low 
level. As a result, a reserve word line corresponding to one of the 
reserve word line selection signals XR0B-XR3B that has turned to a low 
level is selected to replace a defective word line. 
FIG. 3 is a timing chart of an embodiment to illustrate a word line 
selecting operation. When a row address strobe signal RASB turns to a low 
level, a row address signal is taken in. That is, when the signal RASB 
turns to the low level, an internal signal R1 turns to a high level and an 
address signal Ai is taken in as a row address ROW. 
The level of an internal signal BXi is determined in accordance with the 
row address ROW thus taken in. By decoding the internal signal BXi, a mat 
selection signal MS0 turns to a high level. Comparison with a defective 
address is performed by use of the signal R1. If access to a defective 
address is not attempted, a signal XE is turned to a high level. An 
internal signal R2 turns to a high level with a certain delay from the 
signal R1. Based on the signals R2 and XE, a word line selection timing 
signal X0B corresponding to one of the four word lines is turned to a low 
level. Since a selection signal for the four word lines has been generated 
by a predecoder circuit for decoding the other row address signals, the 
word line WL0 is turned to a high level, i.e., selected in synchronism 
with the turning of the signal X0B to the low level. 
When a memory access is directed to a defective word line in the next 
memory cycle, the signal XE is kept at the low level. As a result, 
selection of the defective word line is prohibited. The signal XEB as 
shown in FIG. 2 turns to the high level, and a selection signal XR0B 
corresponding to the reserve word line is turned to a low level at a 
timing when the signal R2 is at the high level. In synchronism with the 
turning of the signal XR0B to the low level, the reserve word line RWL0 
turns to a high level, i.e., rendered into a selected state. 
FIGS. 4 and 5 are block diagrams showing an embodiment of the main part of 
the dynamic RAM according to the invention. FIG. 4 shows a memory array 
and its peripheral circuit, and FIG. 5 shows an input/output interface 
section including an address buffer and an input/output buffer, and a 
timing control circuit. 
As shown in FIG. 4, a sense amplifier SA01 is provided between two memory 
mats MMAT0 and MMAT01. That is, the sense amplifier SA01 is a shared sense 
amplifier that is selectively used for the two memory mats MMAT0 and 
MMAT1. A selection switch (not shown) is provided in an input/output 
section of the sense amplifier SA01, and connected to complementary bit 
lines of the memory mat MMAT0 or MMAT1. 
The other pairs of memory mats MMAT2/MMAT3, MMAT4/MMAT5 and MMAT6/MMAT7 
share sense amplifiers SA23, SA45 and SA67, respectively. In this manner, 
one memory array MARY0 comprises the eight memory mats and the four sense 
amplifiers. A Y-decoder YD is provided for the memory array MARY0. A 
memory array MARY1 is provided on the other side of the Y-decoder YD in a 
symmetrical manner. The memory array MARY1 has a configuration similar to 
that of the memory array MARY0 though its internal configuration is 
omitted in FIG. 4. 
Decoders XD0-XD7 are provided for the respective memory mats MMAT0-MMAT7. 
Each of the decoders XD0-XD7 decodes an address signal AXi that is an 
output signal of a predecoder circuit XPD, and generates a selection 
signal for the four word lines. Word drivers WD0-WD7 are provided which 
generate word line selection signals based on output signals of the 
decoders XD0-XD7 and mat control circuits MATCTRL01-MATCTRL04 (described 
below). These word drivers include word drivers corresponding to the 
reserve word lines. 
The mat control circuit MATCTRL01 is provided for the pair of memory mats 
MMAT0 and MMAT1. The similar mat control circuits MATCTRL02, MATCTRL03 and 
MATCTRL04 are provided for the other memory mat pairs MMAT2/MMAT3, 
MMAT4/MMAT5 and MMAT6/MMAT7, respectively. In response to a mat selection 
signal MSi, signal XE, sense operation timing signal .PHI.SA and a decoded 
signal of the lower two bits of the address signal, one of the mat control 
circuits MATCTRL01-MATCTRL04 that corresponds to the selected memory mat 
outputs a selection signal XiB for selecting one of the four word lines. 
Further, the mat control circuit generates selection signals for keeping 
in an on state a bit line selection switch corresponding to a memory mat 
located on the right or left side of the selected memory mat and for 
keeping bit line switches corresponding to the non-selected memory mats in 
an off state, and a timing signal for starting the amplifying operation of 
the sense amplifier. 
When access to a defective word line is attempted, the output of the 
selection signal XiB etc. is prohibited by turning of the signal XE to the 
low level and, therefore, the operation of selecting the defective word 
line is stopped. Instead, a selection signal XRiB on the redundant circuit 
side is generated to select a reserve word line. 
With reference to FIG. 5, in response to a row address strobe signal RASB, 
a column address strobe signal CASB, a write enable signal WEB and an 
output enable signal OEB which are supplied through external terminals, a 
timing control circuit TG judges an operation mode and generates various 
timing signals that are necessary for the operation of the internal 
circuit in accordance with the judgment. 
The row internal timing signals R1 and R2 are used as described in 
connection with FIG. 3. A timing signal .PHI.XL, which serves to cause row 
addresses to be taken in and retained, is supplied to a row address buffer 
RAB. That is, in response to the timing signal .PHI.XL, the row address 
buffer RAB takes in addresses that are input through address terminals 
A0-Ai to retain those addresses in a latch circuit. 
A timing signal .PHI.YL, which serves to cause column addresses to be taken 
in and retained, is supplied to a column address buffer CAB. That is, in 
response to the timing signal .PHI.YL, the column address buffer CAB takes 
in addresses that are input through the address terminals A0-Ai to retain 
those addresses in a latch circuit. 
A signal .PHI.REF, which is generated in a refresh mode, is supplied to a 
multiplexer AMX that is provided in an input section of the row address 
buffer to effect switching to a refresh address signal that is generated 
by a refresh address counter RFC in the refresh mode. The refresh address 
counter circuit RFC generates the refresh address signal by counting 
refresh stepping pulses .PHI.RC generated by the timing control circuit 
TG. 
A word line selection timing signal .PHI.X is supplied to a decoder XIB, 
which generates four kinds of word line selection timing signals XiB based 
on a decoded signal of the lower two bits of the address signal. A column 
selection timing signal .PHI.Y is supplied to a column predecoder YPD, 
which outputs column selection signals AYix, AYjx and AYkx. 
A timing signal .PHI.W is a control signal for indicating a writing 
operation, and a timing signal .PHI.R is a control signal for indicating a 
reading operation. The timing signals .PHI.W and .PHI.R are supplied to an 
input/output circuit I/O to activate an input buffer and render an output 
buffer in an high impedance state in the writing operation, the input and 
output buffers being incorporated in the input/output circuit I/O. On the 
other hand, in the reading operation, the timing signals .PHI.W and .PHI.R 
activate the output buffer and render the input buffer in a high impedance 
state. 
A timing signal .PHI.MS, which is a signal for indicating a mat selecting 
operation, is supplied to the row address buffer RAB, which outputs the 
mat selection signal MSi in synchronism with this timing signal. A timing 
signal .PHI.SA indicates the operation of the sense amplifiers. Sense 
amplifier activation pulses are generated based on the timing signal 
.PHI.SA. Further, the timing signal .PHI.SA is used to generate control 
signals for operations of finishing precharging of complementary bit lines 
and separating bit lines on the side of non-selected memory mats. 
In the above embodiment, a row redundant circuit X-RED is shown as a 
representative example. That is, the circuit X-RED includes a memory 
circuit for storing a defective address and an address comparison circuit, 
which compares the defective address stored therein and the internal 
address signal BXi that is sent from the row address buffer RAB. If the 
two addresses do not coincide, the row redundant circuit X-RED turns the 
signals XE and XEB to a high level and a low level, respectively. If the 
two addresses coincide with each other, the row redundant circuit X-RED 
turns the signal XE to a low level to prohibit the operation of selecting 
the defective word line of the regular circuit, and turns the signal XEB 
to a high level to cause the selection circuit as shown in FIG. 2 to 
output the selection signal XRiB for selecting one reserve word line. 
Although omitted in FIG. 5, column circuits similar to the above row 
circuits are provided. When the column circuits detect a memory access to 
a defective bit line, they prohibit the operation of selecting the 
defective bit line by the column decoder YD, and generate a selection 
signal for selecting a reserve bit line. 
The following advantages are obtained by the above embodiments. 
(1) Since the reserve bit lines or word lines are located approximately in 
the central portion of the memory mat, in which case the reserve word 
lines or bit lines have a low probability of defect occurrence, the 
probability of defect occurrence when a defective word line or bit line is 
replaced with a reserve word line or bit line can be reduced. 
(2) By providing the same number of reserve word lines on each side of the 
twist portion of the complementary bit lines, the capacitances between the 
complementary bit lines can be balanced to improve the operational margin. 
While the invention has been described by way of certain embodiments, it 
should be understood that the invention is not limited to the embodiments 
but is capable of modification in a variety of ways within the scope of 
its essential features. For example, where, as described above, the same 
number of reserve word lines are separately provided on each side of the 
twist portion of the complementary bit lines to balance capacitances of 
the bit lines, the complementary bit lines may be provided in a peripheral 
portion of the memory mat in connection with, for instance, the layout of 
other components. 
A single dynamic RAM may comprise four memory arrays by using the same 
memory arrays and Y-decoders as those shown in FIG. 4. Similarly, a single 
dynamic RAM may comprise four sets of memory arrays, each set including 
four memory arrays. In this manner, in practice the memory array 
configuration of the dynamic RAM can take various forms. 
Semiconductor memory devices having complementary bit lines include static 
RAMs as well as folded bit line type dynamic RAMs. Also in static RAMs, 
influences of coupling between bit lines can be reduced by providing a 
twist portion in every other complementary bit line. Therefore, by 
providing the same number of reserve word lines on each side of the twist 
portion of the complementary bit lines, the operational margin can be 
improved similarly and, at the same time, the data scrambling can be 
simplified. 
The invention can be applied to dynamic RAMs and static RAMs having 
complementary bit lines (described above), but also to various ROMs. RAMs 
and ROMs are not limited to those that comprise an integrated circuit 
memory, but may be those incorporated in a digital integrated circuit such 
as a microcomputer. 
In accordance with the invention, by utilizing the fact that reserve word 
lines and bit lines have a low probability of defect occurrence when they 
are provided approximately in a central portion of a memory mat, the 
probability of defect occurrence when a defective word line or bit line is 
replaced with a reserve word line or bit line can be made low.