Graphic processing unit and method of performing, by graphic processing unit, tile-based graphics pipeline

Computing apparatus and methods are provided for performing a tile-based graphics pipeline. The graphics pipeline includes a binning pipeline configured to generate a tile list of objects indicating which tile vertices, primitives, or patches the objects belong to; and a rendering pipeline configured to render an object, per tile, based on the tile list generated in the binning pipeline. Each of the binning pipeline and the rendering pipeline is configured to implement a tessellation pipeline. The graphics pipeline may be configured to operate in an efficiency mode to defer or lower tessellation by performing tessellation in one of the binning and rendering pipelines or by setting a new lower tessellation factor.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of Korean Patent Application No. 10-2014-0166628, filed on Nov. 26, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to graphic processing units and methods of performing, by graphic processing units, a tile-based graphics pipeline.

2. Description of Related Art

A graphic processing unit (GPU) renders graphics data in a computing apparatus. Generally, the GPU generates a frame for display by converting graphics data corresponding to 2-dimensional (2D) or 3-dimensional (3D) objects to a 2D pixel expression. Examples of the computing apparatus include a PC, a laptop, a video game console, a smart phone, a tablet device, and a wearable device, to name but a few. It is difficult to provide the same graphic processing performance delivered by workstations, such as a PC, a laptop, and a video game console, which have sufficient memory spaces and processing power, in devices where the GPU is embedded, such as a smart phone, a tablet device, and a wearable device, due to the relatively low processing capability and high power consumption of the embedded devices. However, due to the recent widespread, worldwide supply of portable devices, such as smart phones or tablet devices, and the frequency which of users of these devices are employing them for graphics intense applications, such as playing games or viewing content, such as movies or series, manufacturers of GPUs are conducting many studies to increase the performance and throughput of the GPUs even in embedded devices to keep up with user demand and expectations.

SUMMARY

Provided are graphic processing units and methods of performing, by graphic processing units, a tile-based graphics pipeline.

In one general aspect, a method performing a graphics pipeline, by a graphic processing unit, on a frame including an object partitioned into one or more tiles comprises: performing a binning pipeline including: generating an output patch; determining the number of tiles that include the output patch; determining whether to perform tessellating on the output patch based on the determined number of tiles; and binning a tile list of one of the output patch or tessellated primitives of the output patch based on whether tessellating is performed; and performing a rendering pipeline per tile based on the binned tile list.

The performing of the binning pipeline may comprise determining no tessellating is performed on the output patch when the number of tiles that include the output patch is one.

The performing of the binning pipeline may further comprise: generating the output patch by a hull shader performing hull shading on an input patch; binning the tile list of the output patch; and determining whether the output patch is included in one tile.

The performing of the rendering pipeline may further comprise performing rasterizing using the binned tile list of the output patch when the output patch is included in one tile.

The performing of the binning pipeline may further comprise: tessellating, by a tessellator, the output patch to generate tessellating primitives when it is determined that the output patch is included in at least two tiles; domain shading, by a domain shader, the tessellated primitives; binning a tile list of the tessellated primitives; and the performing of the rendering pipeline may further comprise: performing the rasterizing using the binned tile list of the tessellated primitives.

The performing of the binning pipeline may comprise: storing a visibility stream of the output patch when the output patch is included in one tile; and storing a visibility stream of the tessellated primitives when the output patch is included in at least two tiles.

In another general aspect, a computing apparatus that performs a graphics pipeline on a frame including an object partitioned into one or more tiles comprises: a graphic processing unit (GPU) configured to perform a binning pipeline including: generating an output patch; determining the number of tiles that include the output patch; determining whether to perform tessellating on the output patch based on the determined number of tiles; and binning a tile list of one of the output patch or of tessellated primitives of the output patch based on whether tessellating is performed; store the binned tile list; access the stored binned tile list; and a rendering pipeline per tile based on the binned tile list; and a memory configured to store the binned tile list.

The binning pipeline performed by the GPU may further comprise determining no tessellating is performed on the output patch when the number of tiles that include the output patch is one.

The computing GPU may further include: a hull shader and the binning pipeline performed by the GPU may further comprise: generating the output patch performing hull shading on an input patch; binning the tile list of the output patch; and determining whether the output patch is included in one tile.

The rendering pipeline performed by the GPU may further comprise performing rasterizing using the binned tile list of the output patch when GPU determines the output patch is included in one tile.

The GPU may further include: a domain shader and a tessellator and the binning pipeline performed by the GPU may further comprise: tessellating the output patch to generate tessellating primitives when the GPU determines that the output patch is included in at least two tiles; domain shading the tessellated primitives; binning a tile list of the tessellated primitives; and the rendering pipeline performed by the GPU may further comprise: performing the rasterizing using the binned tile list of the tessellated primitives.

The binning pipeline performed by the GPU may comprise: storing a visibility stream of the output patch when the GPU determines the output patch is included in one tile; and storing a visibility stream of the tessellated primitives when the GPU determines the output patch is included in at least two tiles; and the memory is further configured to store the visibility stream.

In another general aspect, a method of performing a graphics pipeline, by a graphic processing unit (GPU), on a frame including an object partitioned into one or more tiles, comprises: performing a binning pipeline including: generating an output patch by a hull shader; tessellating the output patch with a second tessellation factor that is different from a first tessellation factor determined by the hull shader; determining by the GPU whether to perform tessellating with the first tessellation factor, based on the number of tiles including primitives tessellated with the second tessellation factor; and binning a tile list of one of primitives tessellated with the first tessellation factor or the output patch output from the hull shader based on a result of the determining; and performing a rendering pipeline per tile based on the binned tile list.

The performing of the binning pipeline may comprise binning the tile list of the output patch when the primitives tessellated with the second tessellation factor are included in one tile.

The second tessellation factor may be lower than the first tessellation factor.

The performing of the binning pipeline may comprise: performing hull shading that generates the output patch by the hull shader; determining the first tessellation factor; generating the primitives tessellated with the second tessellation factor by performing, on the output patch, tessellating using the second tessellation factor that is lower than the first tessellation factor by a tessellator and domain shading by a domain shader; and determining by the GPU whether the primitives tessellated with the second tessellation factor are included in one tile; and the performing of the rendering pipeline may further comprise performing rasterizing using the binned tile list of the output patch when the primitives tessellated with the second tessellation factor are included in one tile.

The performing of the binning pipeline may further comprise generating the primitives tessellated with the first tessellation factor by performing, on the output patch, tessellating using the first tessellation factor by the tessellator and the domain shading by the domain shader when the primitives tessellated with the second tessellation factor are included in at least two tiles, and the performing of the rendering pipeline may further comprise performing the rasterizing by using the binned tile list of the primitives tessellated with the first tessellation factor.

The performing of the binning pipeline may further comprise, storing a visibility stream of the output patch when the primitives tessellated with the second tessellation factor are included in one tile, and storing a visibility stream of the primitives tessellated with the first tessellation factor when the primitives tessellated with the second tessellation factor are included in at least two tiles.

In another general aspect, a computing apparatus that performs a graphics pipeline on a frame including an object partitioned into one or more tiles comprises: a graphic processing unit (GPU) including a hull shader, the GPU configured to perform: a binning pipeline including: generating an output patch by the hull shader; tessellating the output patch with a second tessellation factor that is different from a first tessellation factor determined by the hull shader; determining whether to perform tessellating with the first tessellation factor based on the number of tiles including primitives tessellated with the second tessellation factor; and binning a tile list of one of primitives tessellated with the first tessellation factor or the output patch output from the hull shader based on a result of the determining; and a rendering pipeline per tile based on the binned tile list; and a memory configured to store the binned tile list.

The binning pipeline may comprise binning the tile list of the output patch when the primitives tessellated with the second tessellation factor are included in one tile.

The second tessellation factor may be lower than the first tessellation factor.

In another general aspect, a method of performing a graphics pipeline by a graphic processing unit (GPU) comprises: performing a binning pipeline including: binning an output patch from a hull shader; determining whether the output patch output from the hull shader is included in a plurality of tiles; scheduling a rendering order of the plurality of tiles when the GPU determines that the output patch is included in the plurality of tiles; and performing a per tile rendering pipeline on the plurality of tiles based on the scheduled rendering order including: performing binning on a first tile that is scheduled in the rendering order that generates a visibility stream of a neighboring tile adjacent to the first tile.

The performing of the binning pipeline may comprise no tessellating of the output patch.

The performing of the binning pipeline further may comprise: generating the output patch as the hull shader performs hull shading on an input patch; binning a tile list of the output patch; determining whether the output patch is included in the plurality of tiles; and determining the first tile corresponding to the first tile in the rendering order when the GPU determines that the output patch is included in the plurality of tiles.

The performing of the rendering pipeline may further comprise: performing a first rendering pipeline on the first tile; and performing a second rendering pipeline on the neighboring tile comprising performing rendering on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile using the visibility stream generated in the first rendering pipeline.

In another general aspect, a computing apparatus that performs a graphics pipeline comprises: a graphic processing unit (GPU) including a hull shader, the GPU configured to perform: a binning pipeline including: binning an output patch from the hull shader, determining whether the output patch output from the hull shader is included in a plurality of tiles, scheduling a rendering order of the plurality of tiles when the GPU determines that the output patch is included in the plurality of tiles; and a per tile rendering pipeline on the plurality of tiles based on the scheduled rendering order including: performing binning, on a first tile that is scheduled in the rendering order, that generates a visibility stream of a neighboring tile adjacent to the first tile; and a memory that stores the visibility stream of the neighboring tile adjacent to the first tile.

The GPU may further comprise a tessellator and the binning pipeline comprises no tessellating of the output patch.

While the binning pipeline is performed, the GPU may generate the output patch as the hull shader performs hull shading on an input patch; bin a tile list of the output patch; determines whether the output patch is included in the plurality of tiles; and determine the first tile of the rendering order when the GPU determines that the output patch is included in the plurality of tiles.

The GPU may performs a first rendering pipeline on the first tile and performs a second rendering pipeline on the neighboring tile, the second rendering pipeline comprising performing rendering on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile using the visibility stream generated in the first rendering pipeline.

In another general aspect, a method of performing a graphics pipeline by a graphic processing unit (GPU) comprises: performing a binning pipeline including: binning, by a hull shader, primitives tessellated with a second tessellation factor that is different from a first tessellation factor; determining whether the primitives tessellated with the second tessellation factor are included in a plurality of tiles, scheduling a rendering order of the plurality of tiles when the GPU determines that the primitives tessellated with the second tessellation factor are included in the plurality of tiles; and performing a per tile rendering pipeline on the plurality of tiles based on the scheduled rendering order including: performing binning, on a first tile scheduled in the rendering order that generates a visibility stream of a neighboring tile adjacent to the first tile.

The performing of the binning pipeline may comprise no tessellating based on the first tessellation factor.

The second tessellation factor may be lower than the first tessellation factor.

The performing of the binning pipeline may further comprise: performing, by the hull shader, hull shading to generate an output patch; determining the first tessellation factor; generating the primitives tessellated with the second tessellation factor by performing, on the output patch, tessellating by a tessellator and domain shading by a domain shader, based on the second tessellation factor that is lower than the first tessellation factor; binning a tile list of the primitives tessellated with the second tessellation factor; determining whether the primitives tessellated with the second tessellation factor are included in the plurality of tiles; and determining the first tile corresponding to the rendering order when it is determined that the primitives tessellated with the second tessellation factor are included in the plurality of tiles.

The performing of the rendering pipeline may comprises: performing a first rendering pipeline on the first tile; and performing a second rendering pipeline on the neighboring tile comprising performing rendering on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile based on the visibility stream generated in the first rendering pipeline.

In another general aspect, a computing apparatus that performs a graphics pipeline comprises: a graphic processing unit (GPU) including a hull shader, the GPU configured to perform: a binning pipeline including: binning, by the hull shader, primitives tessellated with a second tessellation factor that is different from a first tessellation factor, determining whether the primitives tessellated with the second tessellation factor are included in a plurality of tiles, and scheduling a rendering order of the plurality of tiles when the GPU determines that the primitives tessellated with the second tessellation factor are included in the plurality of tiles; and a per tile rendering pipeline on the plurality of tiles based on the scheduled rendering order including performing binning, on a first tile scheduled in the rendering order, that generates a visibility stream of a neighboring tile adjacent to the first tile; and a memory that stores the visibility stream of a neighboring tile adjacent to a first tile scheduled as a first rendering order.

The binning pipeline may include tessellating based on the first tessellation factor.

The second tessellation factor may be lower than the first tessellation factor.

While the binning pipeline is performed, the GPU may perform, by the hull shader, hull shading to generate an output patch; determines the first tessellation factor; generate the primitives tessellated with the second tessellation factor by performing, on the output patch, tessellate by a tessellator and domain shading by a domain shader, based on the second tessellation factor that is lower than the first tessellation factor; bin a tile list of the primitives tessellated with the second tessellation factor; determines whether the primitives tessellated with the second tessellation factor are included in the plurality of tiles; and determines the first tile corresponding to the rendering order when it is determined that the primitives tessellated with the second tessellation factor are included in the plurality of tiles.

The GPU may perform a first rendering pipeline on the first tile and may perform a second rendering pipeline on the neighboring tile including performing rendering on at least one of a visible vertex, a visible primitive, and a visible patch on the neighboring tile based on the visibility stream generated in the first rendering pipeline.

In another general aspect, a non-transitory computer-readable recording medium having recorded thereon a program, which when executed by a computer, performs the method described above.

In another general aspect, a computing apparatus performing a tile-based graphics pipeline comprises: a graphic processing unit (GPU) including: a binning pipeline configured to generate a tile list of objects indicating which tile vertices, primitives, or patches the objects belong to; and a rendering pipeline configured to render an object, per tile, based on the tile list generated in the binning pipeline; and a memory to store the tile list, wherein each of the binning pipeline and the rendering pipeline is configured to implement a tessellation pipeline and the GPU is configured to operate in an efficiency mode to defer or lower tessellation by performing tessellation in one of the binning and rendering pipelines.

The efficiency mode may cause the GPU to operating in an efficient mode that reduces data throughput of a pipeline by performing one of: tessellating on the output patch in the binning pipeline; tessellating on an output patch in the binning pipeline using one of a first tessellating factor and a second tessellating factor that is lower than a first tessellating factor; tessellating in the rendering pipeline using the first tessellating factor; and rendering a first tile in the rendering pipeline and rendering a tile neighboring the first by rendering on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile using a visibility stream generated during rendering of the first tile.

The efficiency mode may cause the GPU determine one of: the number of tiles that include the output patch; and the number of tiles including primitives tessellated with a second tessellation factor that is lower than a first tessellating factor.

In another general aspect, a method of performing a tile-based graphics pipeline by a graphic processing unit (GPU) comprises: operating the GPU in an efficiency mode to defer or lower tessellation by performing tessellation in one of a binning and a rendering pipelines; performing a binning pipeline according to the efficiency mode generating a tile list of objects indicating which tile vertices, primitives, or patches the objects belong to; and performing a rendering pipeline according to the efficiency mode rendering an object, per tile, based on the tile list generated in the binning pipeline.

Operating in the efficiency mode may further comprise causing the GPU to operate in an efficient mode that reduces data throughput of a pipeline by performing one of: tessellating on the output patch in the binning pipeline; tessellating on an output patch in the binning pipeline using one of a first tessellating factor and a second tessellating factor that is lower than a first tessellating factor; tessellating in the rendering pipeline using the first tessellating factor; and rendering a first tile in the rendering pipeline and rendering a tile neighboring the first by rendering on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile using a visibility stream generated during rendering of the first tile.

Operating in the efficiency mode may further comprise causing the GPU to determine one of: the number of tiles that include the output patch; and the number of tiles including primitives tessellated with a second tessellation factor that is lower than a first tessellating factor.

DETAILED DESCRIPTION

All terms including descriptive or technical terms which are used herein should be construed as having meanings that are consistent with those understood by one of ordinary skill in the art. However, various terms also may have different meanings, for example, according to the intent of one of ordinary skill in the art, precedent cases, or the appearance of new technologies. Also, some terms may be selected by the applicant to have a particular meaning as described in the following detailed description of the invention.

In the following description, when an element is described as being “connected” to another element, the elements may not be “directly connected”, but may be “electrically connected” via another device or devices located there between. Also, when a part “includes” an element, the part may include additional elements without excluding the element, unless otherwise stated. In the following description, terms such as “unit” and “module” indicate an element for processing at least one function or operation, wherein the unit and the block may be embodied as hardware or combination of hardware and software.

In the following description, it is to be understood that the terms such as “including” or “having” are intended to be open terms and indicate the existence of the features or components; however, they are not intended to preclude the possibility that one or more additional features or components may exist or may be added.

It will be understood that although the terms “first”, “second”, etc. may be used herein to differentiate between various components; however, these components are not intended to connote order or otherwise be limited by these terms unless specifically states.

FIG. 1is a diagram illustrating an example of a computing apparatus according to one exemplary embodiment.

Referring toFIG. 1, the computing apparatus1includes a graphics processing unit (GPU)10, a central processing unit (CPU)20, a memory30, and a bus40. The components of the computing apparatus1are exemplary, and the computing apparatus1may include additional general-purpose components other than those shown inFIG. 1, as understood by one skilled in the art.

Examples of various devices that may be implemented using the computing apparatus1include a desktop computer, a laptop computer, a smart phone, a personal digital assistant (PDA), a portable media player, a video game console, a television set-top box, a tablet device, an e-book reader, and a wearable device, but are not limited thereto. In addition, the computing apparatus1may be implemented as any device or apparatus having a graphics processing function providing the display of content, and the category of the computing apparatus1may include various apparatuses.

The CPU20is hardware that controls overall operations and functions of the computing apparatus1. For example, the CPU20implements an operating system (OS), invokes a graphics application programming interface (API) for the GPU10, and executes a driver of the GPU10. Also, the CPU20may execute various other applications stored in the memory30, such as, for example, a web-browsing application, a game application, and a video application, among others.

The GPU10is a graphic-exclusive processor that performs a graphics pipeline. In one example, the GPU10may be implemented as hardware that executes a 3-dimensional (3D) graphics pipeline in order to display 3D objects of a 3D image as a 2D image for display. For example, the GPU10may perform various functions, such as shading, blending, illuminating, and generating pixel values of pixels to be displayed.

In one example, the GPU10may perform a tile-based graphics pipeline or a tile-based rendering (TBR). In this context, the term “tile-based” means that each frame of a moving image is divided or partitioned into a plurality of tiles, and rendering is performed per tile. Since a tile-based architecture may have a low throughput when compared to processing a frame per pixel, a mobile device or other embedded device that has a low processing performance, such as a smart phone or a tablet device, may use the tile-based architecture as a graphics rendering method.

Referring toFIG. 1, the GPU10performs a graphics pipeline including a binning pipeline101and a rendering pipeline102. The binning pipeline101is a process of generating a tile list indicating to which tile vertices, primitives, or patches making up 2D or 3D objects are included. Accordingly, other terms, such as a tiling pipeline or a binning phase are within the meaning of binning pipeline. The rendering pipeline102is a process of rendering an object per tile, based on the tile list generated in the binning pipeline101. When the rendering pipeline102is completed, pixel expressions of 2D or 3D objects to be displayed on a 2D display screen may be determined. Other terms, such as a rendering phase, are within the meaning of rendering pipeline102.

Each of the binning pipeline101and the rendering pipeline102may include a tessellation pipeline. In other words, the GPU10may perform deferred tessellation. Some graphics pipelines including DirectX11 (DX11) API or OpenGL 4.0 API of Microsoft include additional processing stages for tessellating graphics primitives (or graphics patches). Tessellation is a process of partitioning graphics patches to graphics primitives, which are smaller than the graphics patches, such that an image having finer details is displayable. The graphics pipeline, including the binning pipeline101and the rendering pipeline102that are performed by the GPU10of the computing apparatus1, may support such tessellation. One or more exemplary embodiments described hereinafter may be performed by the GPU10.

The memory30is hardware that stores various types of data processed in the computing apparatus1. For example, the memory30may store data processed or data to be processed by the GPU10and the CPU20. Also, the memory30may store applications and drivers to be executed by the GPU10and the CPU20. The memory30may include a random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), a CD-ROM, a Blu-ray or another optical disk storage device, a hard disk drive (HDD), a solid state drive (SSD), or a flash memory, and moreover, the memory30may include an external storage device accessible by the computing apparatus1.

The bus40is hardware that connects various pieces of hardware in the computing apparatus1allowing the pieces of hardware to transmit or receive data to or from each other. Examples of the bus40include a peripheral component interconnect (PCI) bus and a PCI express bus.

The binning pipeline101described herein includes a binning pipeline101-1,101-2,101-3, or101-4(shown inFIG. 7and described in further detail below). For example, the binning pipeline101may correspond to any one of the binning pipelines101-1through101-4. Also, the rendering pipeline102(also shown inFIG. 7and described in further detail below) includes a rendering pipeline102-1,102-2,102-3, or102-4. The rendering pipeline102may correspond to any one of the rendering pipelines102-1through102-4.

FIG. 2is a diagram including an example for describing TBR.FIG. 2includes a frame200presenting an object220including a plurality of tiles210. In one example, the object220may be a 3D object, such as a car object220which is presented in one frame200of a moving image. The GPU10partitions the frame200including the 3D car object220into N×M tiles210, wherein N and M are each natural numbers. In this example, the binning pipeline101partitions the frame including the car object220into the tiles210and determines which tiles210include the car object220. The GPU10renders the car object220per tile to convert the car object220to pixel expressions. For example, the rendering pipeline102renders the car object220per tile to convert the car object220to pixel expressions. As such, in TBR, the car object220included in one frame is not rendered per pixel but is rendered per tile using the tiles210.

FIGS. 3, 4, and 5provide examples to help illustrate a tessellation pipeline.FIGS. 3, 4, and 5are in conjunction with each other. The tessellation pipeline300described with reference toFIGS. 3, 4, and 5may include the binning pipeline101and the rendering pipeline102ofFIG. 1described above, or various modified examples of the binning pipeline101and the rendering pipeline102.

Referring toFIG. 3, the tessellation pipeline300is performed by a hull shader121, a tessellator123, and a domain shader125. In other words, the tessellation pipeline300described herein may include at least one stage from among processes (or stages) of hull shading performed by the hull shader121, tessellating performed by the tessellator123, and domain shading performed by the domain shader125.

The hull shader121converts input control points expressing a surface of a low order to output control points forming patches. For example, the hull shader121may convert input control points to generate an output patch410having a mesh shape, which includes control points P00, P01, P02, P03, P10, P11, P12, P13, P20, P21, P22, P23, P30, P31, P32, and P33shown inFIG. 4. Here, the output patch410has a polygonal shape, such as a triangular shape, a rectangular shape, or an isoline shape.

The hull shader121may generate output control points making up patches. At the same time, the hull shader121also may determine a tessellation factor TF or a tessellation level TL. The tessellation factor TF or the tessellation level TL is an index indicating how much of a patch is to be partitioned and how the patch is to be partitioned. An exemplary table500, shown inFIG. 5, defines a relationship between the tessellation factor TF and the number of triangles to be partitioned. According to the table500, when a tessellation factor TF is 1, the number of triangles is 1, and thus tessellation may not be performed on a patch. However, as a tessellation factor TF increases, the number of triangles geometrically increases. When the number of triangles to be partitioned increases as the tessellation factor TF increases, throughput to be performed by the GPU10on a patch also increases. When a tessellation factor TF increases, an expression of a patch of an object may be smoother. In the example provided by table500ofFIG. 5, the polygon to be partitioned is a triangle, but a patch may be partitioned using other polygons, such as rectangles or isolines.

The hull shader121transmits information about output control points of an output patch and a tessellation factor TF to the tessellator123and the domain shader125.

The tessellator123calculates uvw coordinates and weights of the output control points with respect to barycentric coordinates using the tessellation factor TF received from the hull shader121.

The domain shader125produces tessellated vertices using the information received from the hull shader121, the uvw coordinates (of which the w coordinate is optional), and the weights calculated by the tessellator123. Referring toFIG. 4, locations of the tessellated vertices form a boundary420. By performing the tessellation pipeline300, the output patches410may be converted to vertices (or primitives) to form a smoother boundary420.

FIG. 6is a block diagram showing an example of a detailed hardware structure of the GPU10ofFIG. 1.

Referring toFIG. 6, the GPU10includes a graphics pipeline100, a controller170, and buffers180. The graphics pipeline includes an input assembler110, a vertex shader115, the hull shader121, the tessellator123, the domain shader125, a geometry shader130, a binner135, a rasterizer140, a pixel shader150, and an output merger160. The components performing the graphics pipeline100in the GPU10may be classified based on function that are described in further detail below. Each of the components performing the graphics pipeline100are realized as program logic or software modules that are executed by the GPU10to perform certain functions. In another example, the components performing the graphics pipeline100may be implemented as sub-processing units or processor cores included in the GPU10. In other words, the various configurations of the components performing the graphics pipeline100provided herein are examples and are not to be considered limited thereto. Moreover, terms of the components performing the graphics pipeline100have been assigned based on the functions they perform, but it will be appreciated by one of ordinary skill in the art that these terms may vary. For example, according to one exemplary embodiment, the binner135and the controller170may be individual components, but according to another exemplary embodiment, the binner135may be included as part of the controller170, such that the controller170is provided by the GPU10without a separate binner.

For convenience of description, the following examples of the components performing the graphics pipeline100in the GPU10use terms found in association with application programming interfaces (APIs) provided by DirectX of Microsoft, for example DX11: however, the terms used in conjunction with the components described herein are not limited thereto. In other words, the components performing the graphics pipeline100in the GPU10also may correspond to similar components found in another API, such as the Open Graphics Library (OpenGL) 4.0 or the Compute Unified Device Architecture (CUDA) 6.0. For example, the domain shader125may correspond to a tessellation evaluation shader described in OpenGL 4.0, and it is understood by one of ordinary skill in the art that other components of the GPU10may correspond to components used in other APIs, such as OpenGL 4.0 or CUDA 6.0.

The input assembler110supplies data of vertices about objects stored in the memory30to the graphics pipeline100. The vertices supplied to the graphics pipeline100may correspond to a patch, for example, a mesh or surface expression, but are not limited thereto.

The vertex shader115transmits the vertices supplied by the input assembler110as input control points of the hull shader121. For example, vertex shading defined in DX9 performs world-view-projection on vertices. However, vertex shading defined in DX11, to which a tessellation pipeline is introduced does not perform world-view-projection on vertices and only transmits the vertices to a next stage. The vertex shader115, according to the current embodiment, may operate in the similar manner. In other words, the vertex shader115only transmits the input control points corresponding to the vertices supplied by the input assembler110to the hull shader121, and does not generate new control points.

The hull shader121, the tessellator123, and the domain shader125may perform the tessellation pipeline300described above with reference toFIG. 3. In other words, the input control points input to the hull shader121may be output by the domain shader125as tessellated vertices (or tessellated primitives) bounding an output patch.

The geometry shader130is an optional component that may be used to produce additional vertices (or primitives) from the tessellated vertices (or tessellated primitives) received from the domain shader125.

The binner135performs binning or tiling using output primitives from the domain shader125or the geometry shader130. In other words, the binner135generates (bins) a tile list indicating information about each of tiles to which the output primitives belong, by performing a depth test (or a tile Z test). According to another example, the binner135may be a component included in the controller170.

The rasterizer140converts the output primitives from the domain shader125or the geometry shader130to pixel values in a 2D space, based on the generated tile list. The pixel shader150may perform additional operations on pixels, such as a depth test, clipping, scissoring, and blending. A result of pixel-shading performed by the pixel shader150may be stored in the buffers180by the output merger160and displayed as a frame of a moving image.

The controller170controls overall functions and operations of the components performing the graphics pipeline100and the buffers180. Also, the controller170may control modes of the graphics pipeline100, as described below with reference toFIG. 7.

FIG. 7is a diagram of an example illustrating the selection of various types of graphics pipelines performed by the GPU10.

Referring toFIG. 7, the graphics pipelines may operate in mode {circumflex over (1)} through mode {circumflex over (8)} according to various embodiments that are described hereinafter, and the controller170may control which one of the pipelines is to be performed by the GPU

In detail, the controller170may turn off or turn on an efficiency mode providing one or more of the pipelines which operate in mode {circumflex over (1)} through mode {circumflex over (8)}. The turning on or off of the efficiency mode may be set by a user of the computing apparatus or may depend upon a processing environment (for example, resolution, capacity, or a performance of the computing apparatus1) of a moving image to be processed by a graphics pipeline.

When the efficiency mode is turned off, the controller170performs a general graphics pipeline109. Here, the general graphics pipeline109may be implemented using any of the well-known graphics pipelines, such as those provided by DX9, DX10, DX11, CUDA 6.0, or OpenGL 4.0, and therefore is not described in further detail.

When the efficiency mode is turned on, the controller170may perform any one of the graphics pipelines in mode {circumflex over (1)} through mode {circumflex over (8)}. Mode {circumflex over (1)} through mode {circumflex over (8)} may be selected in a number of ways. For example, the mode may be set by the user of the computing apparatus1, or the mode selected may depend upon a processing environment of a moving image to be processed by a graphics pipeline, for example, a tile size, a resolution, a capacity, or a performance of the computing apparatus1. In mode {circumflex over (1)}, the controller170controls a graphics pipeline including the binning pipeline101-1and the rendering pipeline102-1performed by the GPU10. In mode {circumflex over (2)}, the controller170controls a graphics pipeline including the binning pipeline101-2and the rendering pipeline102-1performed by the GPU10. In mode {circumflex over (3)}, the controller170controls a graphics pipeline including the binning pipeline101-3and the rendering pipeline102-1performed by the GPU10. In mode {circumflex over (4)}, the controller170controls a graphics pipeline including the binning pipeline101-4and the rendering pipeline102-1performed by the GPU10. In mode {circumflex over (5)}, the controller170controls a graphics pipeline including the binning pipeline101-3and the rendering pipeline102-2performed by the GPU10. In mode {circumflex over (6)}, the controller170controls a graphics pipeline including the binning pipeline101-4and the rendering pipeline102-2performed by the GPU10. In mode {circumflex over (7)}, the controller170controls a graphics pipeline including the binning pipeline101-3, the first rendering pipeline102-3, and the second rendering pipeline102-4performed by the GPU10. In mode {circumflex over (8)}, the controller170controls a graphics pipeline including the binning pipeline101-4, the first rendering pipeline102-3, and the second rendering pipeline102-4performed by the GPU10. Hereinafter, various exemplary embodiments of the graphics pipelines operating in mode {circumflex over (1)} through mode {circumflex over (8)} are described in detail.

FIGS. 8A and 8Bare diagrams illustrating examples of a relationship between graphics processing performance (or efficiency) and a number of tiles partitioning a 3D object.

FIG. 8Aillustrates an example of when the 3D object815is partitioned into 10×10 tiles810, andFIG. 8Billustrates an example of when the 3D object815is partitioned into 2×2 tiles820. Since the GPU10performs a tile-based rendering or tile-based graphics pipeline per tile, rendering with respect to the 3D object815ofFIG. 8Amay be performed on 100 tiles. On the other hand, rendering with respect to the 3D object815ofFIG. 8Bmay be performed on 4 tiles. InFIG. 8A, only about ⅓ of the tiles810overlap the 3D object815. As a result, rendering may be skipped on the other ⅔ of the tiles810; however, binning (or tiling) has to be pre-performed on the 100 tiles810. On the other hand, since the 4 tiles820ofFIG. 8Ball overlap the 3D object815, parallel graphics processes may be performed on the 4 tiles820.

Currently, many GPUs are manufactured having a single instruction, multiple thread (SIMT) architecture. The SIMT architecture is one of methods for implementing a single program multiple data (SPMD) processor for processing massive amounts of data with one program. The SIMT architecture is able to process a large amount of data using little control hardware, but processing efficiency may be decreased since thread divergence is difficult to process.

Comparing the examples provided inFIGS. 8A and 8B, the SIMT architecture may complete an operation after generating and processing 100 threads with respect to the 100 tiles810ofFIG. 8A; however, the SIMT architecture may complete an operation after generating and processing only 4 threads with respect to the 4 tiles820ofFIG. 8B. Since a size of one tile and a size of an object included in one tile inFIG. 8Aare smaller than those inFIG. 8B, the graphic data to be processed inFIG. 8Amay be less than that processed inFIG. 8B. However it may not be necessarily advantageous to partition the 3D object815into many tiles810, as shown inFIG. 8A, as compared to the fewer tiles820shown inFIG. 8B, since thread divergence increases. More recently developed GPUs that are implemented using the SIMT architecture tend to use a big tile size.

FIG. 9is a diagram illustrating an example of a relationship between output control points of the output patch and tessellated primitives.

As described above with reference toFIG. 8, when the GPU10uses a big tile size, a probability that the output patch410of a 3D object is included in a tile901(e.g., tile0) may increase. A tessellation pipeline, in the binning pipeline101ofFIG. 1, produces a greater number of the tessellated primitives425by tessellating the output patch410including the output control points415and performs binning (or tiling) on the tessellated primitives425. As shown inFIG. 9, even if the output patch410including the output control points415provided in the tile901is processed in the tessellation pipeline, the boundary420formed by the tessellated primitives425may be located within a tile902similar to the boundary formed by the output patch410, because a graphics pipeline of the GPU10may be programmed such that the boundary420formed by the tessellated primitives425is located within the boundary formed by the output patch410. If not, the graphics pipeline may be debugged by a compiler.

The tile901, which is the result of performing binning (or tiling) on the output patch410including the output control points415, may be the same as the tile902(tile0), which is the result of performing binning on the tessellated primitives425. Thus, even if the tessellator123skips tessellating of the tessellation pipeline in the binning pipeline101, it may be assumed that the final result of the binning pipeline101is the same as when the tessellator123does not skip the tessellating.

The same assumption is valid for the tessellation factor TF or the tessellation level TL of the output patch410for the output control points415. For example, a boundary formed by tessellated primitives that are produced by a lower tessellation factor (for example, TF=3) are included in a boundary formed by tessellated primitives produced by a higher tessellation factor (for example, TF=13). Accordingly, even if the binning pipeline101is set to perform a tessellation pipeline using a new, lower tessellation factor (for example, TF=3) instead of using the higher tessellation factor (for example, TF=13) that was determined by the hull shader121, the binning (or tiling) resulting from the newly set lower tessellation factor may be the same as that resulting from the higher tessellation factor.

Meanwhile, a compiler that designs and examines a graphics pipeline to be driven in the GPU10may debug any graphics pipeline that does not operate as described inFIG. 9and compile the graphics pipeline to operate as described inFIG. 9.

The following embodiments described hereinafter with reference toFIGS. 10 through 21may operate based on the above description, but are not limited thereto.

FIG. 10is a diagram illustrating an example of a graphics pipeline performed in the GPU10.

Referring toFIG. 10, the graphics pipeline, including the binning pipeline101-1and the rendering pipeline102-1, operate in mode {circumflex over (1)}, which is described above with reference toFIG. 7. The graphics pipeline ofFIG. 10is described with reference to the hardware components of the GPU10described above forFIG. 6; however, only the components and the pipeline stages relevant to the current example are described in detail. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described with reference toFIG. 10also may be included.

The vertex shader115performs vertex shading1011using vertices1001stored in the memory30. The vertex shader115converts the vertices1001to control points which are input to the hull shader121.

The hull shader121performs hull shading1012to convert the input control points expressing a surface of a low order to output control points that form patches. The hull shader121may determine a tessellation factor TF while producing the output control points. The hull shader121transmits information about the output control points of the output patch to the geometry shader130or the binner135.

As described above with reference toFIG. 3, the tessellation pipeline300includes all stages of the hull shader121, the tessellator123, and the domain shader125, but as shown inFIG. 10, the stages of the tessellator123and the domain shader125may be skipped because, as described above with reference toFIG. 9, the binning result of the output patch410may be the same as the binning result of the tessellated primitives425.

The geometry shader130is an optional component that performs geometry shading1013to produce additional vertices (or primitives) aside from output control points of an output patch that is output from the hull shader121. Thus, the geometry shading1013also may be skipped.

When the geometry shading1013is skipped, the binner135performs binning1014or tiling using the output primitives of an output patch this is received from the hull shader121. If the geometry shading1013is performed, the binner135performs the binning1014or tiling using the output primitives of an output patch that is received from the geometry shader130. For example, the binner135performs the binning1014using a depth test (or a tile Z test) to predict a tile list. The tile list indicates information about tiles to which the output primitives of an output patch belong. Here, the binned tile list may be stored in a bin stream1002of the memory30as a visibility stream. A visibility stream is a stream that indicates whether an input patch, an input control point, an input primitive, an output patch, an output control point, or an output primitive is viewable from a tile. A visibility stream of an input patch, an input control point, or an input primitive may be defined as an input visibility stream, and a visibility stream of an output patch, an output control point, or an output primitive may be defined as an output visibility stream.

The binner135determines whether output primitives of an output patch output from the hull shader121are included in one tile based on the result of performing the binning1014. When it is determined that the output primitives are included in one tile, the binner135stores a visibility stream in the bin stream1002. The stored visibility stream indicates that the output primitives are included in a tile according to a pass {circumflex over (1)}, and the binning pipeline101-1performed on an output patch is complete. As a result, tessellating1015performed by the tessellator123and domain shading1016performed by the domain shader125may be skipped in the pass {circumflex over (1)}.

On the other hand, when it is determined that the output primitives are not included in one tile, according to pass {circumflex over (2)}, the binner135controls the tessellator123to perform the tessellating1015on the output patch. The binner135also controls the domain shader125to perform the domain shading1016on the output patch. In other words, the pass {circumflex over (2)} is performed only when the binner1014determines that the output primitives are not included in one tile.

The tessellator123performs tessellating1015to calculate uvw coordinates and weights of the output control points in barycentric coordinates using a tessellation factor TF received from the hull shader121.

The domain shader125performs domain shading1016to produce tessellated vertices (or tessellated primitives) using the uvw coordinates (of which the w coordinate is optional) and the weights received from the tessellator123, in addition to information about the output control points and the tessellation factor TF received from the hull shader121.

The geometry shader130is an optional component that may be used to perform geometry shading1017to produce additional vertices (or primitives) from the tessellated vertices (or the tessellated primitives) received from the domain shader125. The geometry shading1017also may be skipped in pass {circumflex over (2)}.

According to pass {circumflex over (2)}, the binner135performs binning1018or tiling using the tessellated primitives (or the tessellated vertices) output from the domain shader125or the geometry shader130. In other words, the binner135performs the binning1018to predict a tile list indicating information about tiles to which the tessellated primitives (or the tessellated vertices) belong by performing a depth test (or a tile Z test). In this example, the binned tile list may be stored in the bin stream1002of the memory30as a visibility stream.

When the binning pipeline101-1is completed, the GPU10performs the rendering pipeline102-1per tile. The rendering pipeline102-1may include stages performed by the input assembler110, the vertex shader115, the hull shader121, the tessellator123, the domain shader125, the geometry shader130, the rasterizer140, the pixel shader150, and the output merger160of the graphics pipeline100, which have been described above with reference toFIG. 6.

The binning pipeline101-1ofFIG. 10operating according to mode {circumflex over (1)} described above may not produce tessellated vertices (or tessellated primitives) since the tessellating1015by the tessellator123may be skipped if output primitives of an output patch are included in one tile. Thus, the throughput of graphic data is lower when compared to that of the tessellation pipeline300shown inFIG. 3, wherein the tessellator123necessarily performs the tessellating.

FIG. 11is a flowchart of an example of a method for a graphics pipeline performed by the GPU10. The graphics pipeline implementing the method shown inFIG. 11is the graphics pipeline ofFIG. 10that includes the binning pipeline101-1and the rendering pipeline102-1operating according to mode {circumflex over (1)}. Thus, descriptions ofFIG. 10may apply to those ofFIG. 11, even if omitted in the following description.

In operation1101, the vertex shader115performs the vertex shading1011using the vertices1001stored in the memory30.

In operation1102, the hull shader121performs the hull shading1012to convert input control points to output control points to form an output patch. The hull shader121produces the output control points and, may determine a tessellation factor TF at the same time. The hull shader121transmits information about the output control points of the output patch to the binner135.

In operation1103, the binner135performs the binning1014or tiling using output primitives of the output patch.

In operation1104, the binner135determines whether the output primitives output from the hull shader121are included in one tile based on a result of the performed binning1014. The binning1014predicts a tile list indicating information about tiles to which the output primitives belong. Operation1105is performed directly when it is determined that the output primitives are included in one tile, and operations1107,1108, and1109are performed when it is determined that the output primitives are not included in one tile before performing operation1105.

In operation1105of (pass {circumflex over (1)}), a visibility stream of the binned tile list is stored in the bin stream1002of the memory30

In operation1106, the rasterizer140, the pixel shader150, and the output merger160perform the rendering pipeline102-1. Here, like the binning pipeline101-1, the rendering pipeline102-1may include the stages performed by the input assembler110, the vertex shader115, the hull shader121, the tessellator123, the domain shader125, and the geometry shader130.

In operation1107(pass {circumflex over (2)}), the tessellator123performs the tessellating1015and calculates uvw coordinates and weights of the output control points in barycentric coordinates using the tessellation factor TF received from the hull shader121.

In operation1108, the domain shader125performs the domain shading1016to produce tessellated vertices (or tessellated primitives) using the information about the output control points, the tessellation factor TF received from the hull shader121, the uvw coordinates (of which the w coordinate is optional), and the weights received from the tessellator123.

In operation1109, the binner135performs the binning1018or tiling using the tessellated primitives (the tessellated vertices). The binning1018predicts a tile list indicating information about tiles to which the tessellated primitives (tessellated vertices) belong by performing a depth test (or a tile Z test). After operation1109, a visibility stream of the binned tile list is stored in the bin stream1002of the memory30in operation1105, and in operation1106, the rasterizer140, the pixel shader150, and the output merger160perform the rendering pipeline102-1(as described above).

FIG. 12is a diagram illustrating another example of a graphics pipeline performed in the GPU10.

Referring toFIG. 12, the graphics pipeline, including the binning pipeline101-2and the rendering pipeline102-1, operate according to a mode {circumflex over (2)}, which is described above with reference toFIG. 7. The graphics pipeline ofFIG. 12is described in relation to the hardware components of the GPU10shown inFIG. 6, wherein only the components and the pipeline stages related to the exemplary embodiment are described. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described in relation toFIG. 12may be included.

The vertex shader115performs vertex shading1211using vertices1201stored in the memory30. The vertex shader115converts the vertices1201and inputs the converted the vertices1201to the hull shader121as control points.

The hull shader121performs hull shading1212to convert the input control points, which express a surface of a low order, to output control points that form an output patch. The hull shader121may generate the output control points and determine a first tessellation factor at the same time.

The tessellator123receives the first tessellation factor from the hull shader121, and sets a new, second tessellation factor that is lower than the first tessellation factor. Then the tessellator123performs tessellating1213to calculate uvw coordinates and weights of the output control points in barycentric coordinates using the second tessellation factor.

As described above, with reference to the tessellation pipeline300shown inFIG. 3, the tessellator123uses the tessellation factor TF determined by the hull shader121. However, as described above with reference toFIG. 9, the tessellator123may obtain the same binning result even if the tessellator123uses the second tessellation factor that is lower than the first tessellation factor determined by the hull shader121. In other words, the GPU10may obtain the same binning result even though throughput of the GPU10is decreased when a lower tessellation factor is used, since a lower number of primitives (triangles) is produced.

The domain shader125performs domain shading1214to produce tessellated vertices (or tessellated primitives) using information about the output control points, the second tessellation factor, the uvw coordinates (where the w coordinate is optional), and the weights received from the tessellator123.

The geometry shader130is an optional component that may be used to perform geometry shading1215to produce additional vertices (primitives) from the tessellated vertices (or the tessellated primitives) received from the domain shader125. Thus, the geometry shading1215may be skipped.

The binner135performs binning1216or tiling using the tessellated primitives (or the tessellated vertices) that are tessellated with the second tessellation factor. The binning1216includes a depth test (or a tile Z test) that predicts a tile list indicating information about tiles to which the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor belong.

Based on a result of the binning1216, the binner135determines whether the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in one tile.

When it is determined that the tessellated primitives (the tessellated vertices) are included in one tile, the binner135stores a visibility stream with information indicating that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in one tile in a bin stream1202according to pass {circumflex over (1)}), and the binning pipeline101-2using the second tessellation factor is completed. In other words, since the binning pipeline101-2is completed using the second tessellation factor that is lower than the first tessellation factor determined by the hull shader121, the GPU10completes the binning pipeline101-2with a lower throughput than possible with the first tessellation factor.

When it is determined that the tessellated primitives (the tessellated vertices) are not included in one tile, the binner135performs tessellating1217according to pass {circumflex over (2)}.

According to pass {circumflex over (2)}, the tessellator123performs the tessellating1217to calculate the uvw coordinates and the weights of the output control points in barycentric coordinates using the first tessellator factor, determined by the hull shader121, instead of the second tessellation factor.

The domain shader125performs domain shading1218to produce tessellated vertices (or tessellated primitives) using the uvw coordinates (of which the w coordinate is optional), the weights received from the tessellator123, information about the output control points, and the first tessellation factor.

The geometry shader130is an optional component that may perform geometry shading1219to produce additional vertices (or primitives) from the tessellated vertices (or the tessellated primitives) that are received from the domain shader125. Thus, the geometry shading1219may be skipped.

The binner135performs binning1220or tiling using the tessellated primitives (the tessellated vertices) that are tessellated with the first tessellation factor. The binning1220performs a depth test (or a tile Z test) to predict a tile list indicating information about tiles to which the tessellated primitives (or the tessellated vertices) that are tessellated with the first tessellation factor belong. Then, the binner135stores a visibility stream of the tessellated primitives (the tessellated vertices) in the bin stream1202to complete the binning pipeline101-2using the first tessellation factor.

Once the binning pipeline101-2is completed, the GPU10performs the rendering pipeline102-1per tile. The rendering pipeline102-1may include the stages performed by the input assembler110, the vertex shader115, the hull shader121, the tessellator123, the domain shader125, the geometry shader130, the rasterizer140, the pixel shader150, and the output merger160of the graphics pipeline100, which have been described above with reference toFIG. 6.

The binning pipeline101-2shown inFIG. 12, operating according to mode {circumflex over (2)} described above, may produce a lower number of tessellated vertices (or tessellated primitives) since the tessellator123performing the tessellating1213uses a low tessellator factor. Thus, the throughput of graphic data may be lower when compared to that of the tessellation pipeline300shown inFIG. 3.

FIG. 13is a flowchart of an example of another method for a graphics pipeline performed in the GPU10. The method shown inFIG. 13may be used to implement the graphics pipeline shown inFIG. 12that includes the binning pipeline101-2and the rendering pipeline102-1operating according to mode {circumflex over (2)}. Thus, descriptions ofFIG. 12may apply to those ofFIG. 13, even if omitted.

In operation1301, the vertex shader115performs the vertex shading1211using the vertices1201stored in the memory30.

In operation1302, the hull shader121performs the hull shading1212to convert input control points to output control points to form an output patch. The hull shader121produces the output control points and determines a first tessellation factor at the same time.

In operation1303, the tessellator123performs the tessellating1213on the output control patch using a second tessellation factor that is lower than the first tessellation factor determined by the hull shader121.

In operation1304, the domain shader125performs the domain shading1214to produce tessellated vertices (or tessellated primitives) using information about the output control points, the second tessellation factor, uvw coordinates (of which the w coordinate is optional), and weights received from the tessellator123.

In operation1305, the binner135performs the binning1216or tiling using the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor.

In operation1306, the binner135determines whether the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in one tile based on the result of the performed binning1216. When the binner135determines that the tessellated primitives (the tessellated vertices) are included in one tile, operation1307is performed, and when the binner135determines that the tessellated primitives (the tessellated vertices) are not included in one tile, operation1309is performed.

In operation1307, the binner135stores a visibility stream indicating information that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in one tile in the bin stream1201.

In operation1308, the rasterizer140, the pixel shader150, and the output merger160perform the rendering pipeline102-1. Here, like the binning pipeline101-2, the rendering pipeline102-1may include the stages performed by the input assembler110, the vertex shader115, the hull shader121, the tessellator123, the domain shader125, and the geometry shader130.

In operation1309, the tessellator123performs the tessellating1217on the output control points using the first tessellation factor determined by the hull shader121instead of the second tessellation factor.

In operation1310, the domain shader125performs the domain shading1218to produce tessellated vertices (or tessellated primitives) using information about the output control point, the first tessellation factor, the uvw coordinates (of which the w coordinate is optional), and the weights received from the tessellator123.

In operation1311, the binner135performs the binning1220or tiling using the tessellated primitives (or the tessellated vertices) that are tessellated with the first tessellation factor. After operation1311, the binner135stores a visibility stream of the tessellated primitives (the tessellated vertices) in the bin stream1201in operation1307.

FIG. 14is a diagram illustrating another example of a graphics pipeline performed in the GPU10.

Referring toFIG. 14, the graphics pipeline, including the binning pipeline101-3and the rendering pipeline102-1, operate according to the mode {circumflex over (3)}, which is described above with reference toFIG. 7. The graphics pipeline ofFIG. 14is described in relation to the hardware components of the GPU10shown inFIG. 6, wherein only components and pipeline stages related to this exemplary embodiment are described. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described in association withFIG. 14also may be included.

The vertex shader115performs vertex shading1411using vertices1401stored in the memory30. The vertex shader115converts the vertices1401, and inputs the converted vertices to the hull shader121as input control points expressing a surface of a low order.

The hull shader121performs hull shading1412that converts the input control points to output control points that form an output patch. The hull shader121transmits information about the output control points to the binner135.

As described above with reference toFIG. 3, the tessellation pipeline300includes all stages of the hull shader121, the tessellator123, and the domain shader125, but according to pipeline described in association withFIG. 14, the stages of the tessellator123and the domain shader125may be skipped because, as described above with reference toFIG. 9, the binning result of the output patch410and the binning result of the tessellated primitives425may be the same. However, even if the binning results are not the same, final pixel rendering results may be the same since stages, such as curling, clipping, and hidden surface removal (HSR) are performed in the rendering pipeline102-1.

The binner135performs binning1413or tiling using output primitives of the output patch output from the hull shader121. In other words, the binner135performs a depth test (or a tile Z test) to predict a tile list indicating information about tiles to which the output primitives belong. Here, the binned tile list may be stored in a bin stream1402of the memory30as a visibility stream.

Unlike the examples described above with reference toFIGS. 10, 11, 12, and13, the binner135does not determine whether the output primitives of the output patch output from the hull shader121are included in one tile. In other words, in this example, the output primitives may be included in one or more tiles.

When the binning pipeline101-3is completed, the GPU10performs the rendering pipeline102-1per tile. The rendering pipeline102-1may include stages of vertex shading1421performed by the vertex shader115, hull shading1422performed by the hull shader121, tessellating1423performed by the tessellator123, domain shading1424performed by the domain shader125, geometry shading1425optionally performed by the geometry shader130, rasterizing1426performed by the rasterizer140, and pixel shading1427performed by the pixel shader150. A result of performing the pixel shading1427by the pixel shader150may be stored in a buffer1403.

Since the graphics pipeline shown inFIG. 14operates according to the mode {circumflex over (3)} described above, the tessellating performed by the tessellator123in the binning pipeline101-3may be skipped and the tessellated vertices (or tessellated primitives) not be produced. Accordingly, the throughput of graphic data using the graphics pipeline shown inFIG. 14may be reduced as compared to the tessellation pipeline300shown inFIG. 3, which has to perform tessellating using the tessellator123.

FIG. 15is a flowchart showing another example of a method of implementing a graphics pipeline performed in the GPU10. In this example, the method shown inFIG. 15may be used to implement the graphics pipeline shown inFIG. 14, which includes the binning pipeline101-3and the rendering pipeline102-1operating according to mode {circumflex over (3)}. Thus, the descriptions ofFIG. 14may apply toFIG. 15, even if omitted.

A pipeline1510including operations1511through1514corresponds to the binning pipeline101-3and a pipeline1520including operation1521corresponds to the rendering pipeline102-1.

In operation1511, the vertex shader115performs the vertex shading1411using the vertices1401stored in the memory30.

In operation1512, the hull shader121performs the hull shading1412that converts input control points to output control points to form an output patch.

In operation1513, the binner135performs the binning1413or tiling on the output control points of the output patch.

In operation1514, the binner135stores a tile list indicating information about tiles to which output primitives of the output patch belong. The tile list is stored in the bin stream1402of the memory30as a visibility stream, based on a result of the binning1413. Unlike the examples described above with reference toFIGS. 10 through 13, the binner135does not determine whether the output primitives of the output patch output from the hull shader121are included in one tile. In other words, the output primitives may be included in one or more tiles.

In operation1521, the GPU10performs the rendering pipeline102-1per tile. The rendering pipeline102-1may include stages of vertex shading1421performed by the vertex shader115, hull shading1422performed by the hull shader121, tessellating1423performed by the tessellator123, domain shading1424performed by the domain shader125, geometry shading1425optionally performed by the geometry shader130, rasterizing1426performed by the rasterizer140, and pixel shading1427performed by the pixel shader150.

FIG. 16is a diagram illustrating an example of a graphics pipeline performed in the GPU10.

Referring toFIG. 16, the graphics pipeline, including the binning pipeline101-4and the rendering pipeline102-1, operates in the mode {circumflex over (4)}, described above with reference toFIG. 7. The graphics pipeline ofFIG. 16is described in relation to hardware components of the GPU10shown inFIG. 6, wherein only components and pipeline stages related to this example are described. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described in association withFIG. 16may be included.

The vertex shader115performs vertex shading1611using vertices1601stored in the memory30. The vertex shader115converts the vertices1601and transmits the converted vertices1601to the hull shader121as input control points expressing a surface of a low order.

The hull shader121performs hull shading1612that converts the input control points to output control points forming an output patch. The hull shader121produces the output control points and determines a first tessellation factor at the same time.

The tessellator123receives the first tessellation factor from the hull shader121, and sets a new, second tessellation factor that is lower than the first tessellation factor. Also, the tessellator123performs tessellating1613that calculates uvw coordinates and weights of the output control points in barycentric coordinates using the newly set second tessellation factor.

In the tessellation pipeline300shown and described above with reference toFIG. 3, the tessellator123uses the tessellation factor TF determined by the hull shader12. Yet, as described above with reference toFIG. 9, the binning results may be the same even if the tessellator123uses the second tessellation factor that is lower than the first tessellation factor determined by the hull shader121. However, even if the binning results are not the same, final pixel rendering results may still be the same since stages, such as curling, clipping, and HSR, are performed in the rendering pipeline102-1.

The domain shader125performs domain shading1614to produce tessellated vertices (or tessellated primitives) using information about the output control points of the output patch, the second tessellation factor, the uvw coordinates (of which the w coordinate is optional), and the weights received from the tessellator123.

The geometry shader130is an optional component that may be used to perform geometry shading1615to produce additional vertices (or primitives) from the tessellated vertices (or the tessellated primitives) received from the domain shader125. Accordingly, the geometry shading1615may be skipped.

The binner135performs binning1616or tiling using the tessellated primitives (or the tessellated vertices) that are tessellated with the second tessellation factor. In other words, the binner135performs a depth test (or a tile Z test) to predict a tile list indicating information about tiles to which the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor belong. Here, the binned tile list may be stored in a bin stream1602of the memory30as a visibility stream.

Unlike the examples described above with reference toFIGS. 10 through 13, the binner135does not determine based on a result of performing the binning1616whether the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in one tile. In other words, the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor may be included in one or more tiles.

When the binning pipeline101-4is completed, the GPU10performs the rendering pipeline102-1per tile. The rendering pipeline102-1may include stages of vertex shading1621performed by the vertex shader115, hull shading1622performed by the hull shader121, tessellating1623performed by the tessellator123, domain shading1624performed by the domain shader125, geometry shading1625optionally performed by the geometry shader130, rasterizing1626performed by the rasterizer140, and pixel shading1627performed by the pixel shader150. A result of performing the pixel shading1627by the pixel shader150may be stored in a buffer1603.

Since the binning pipeline101-4shown inFIG. 16operates according to the mode {circumflex over (4)} described above, tessellating1613may be performed by the tessellator123using a lower tessellation factor to produce a fewer number of tessellated vertices (or tessellated primitives). Accordingly, as compared to the tessellation pipeline300shown inFIG. 3, throughput of graphic data shown inFIG. 16may be reduced.

FIG. 17is a flowchart of another example of a method of implementing a graphics pipeline performed in the GPU10. The method shown in shown inFIG. 17may be used to implement the graphics pipeline shown inFIG. 16, which includes the binning pipeline101-4and the rendering pipeline102-1operating according to the mode {circumflex over (4)}. Thus, descriptions shown inFIG. 16may apply to those shown inFIG. 17, even if omitted.

A pipeline1710including operations1711through1716corresponds to the binning pipeline101-4, and a pipeline1720including operation1712corresponds to the rendering pipeline102-1.

In operation1711, the vertex shader115performs the vertex shading1611using the vertices1601stored in the memory30.

In operation1712, the hull shader121performs the hull shading1612to convert input control points to output control points and form an output patch.

In operation1713, the tessellator123performs the tessellating1613on the output control points using a second tessellation factor that is lower than a first tessellation factor determined by the hull shader121.

In operation1714, the domain shader125performs the domain shading1614to produce tessellated vertices (or tessellated primitives) using information about the output control points, the second tessellation factor, uvw coordinates (of which the w coordinate is optional), and weights received from the tessellator123.

In operation1715, the binner135performs the binning1616or tiling using the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor.

In operation1716, the binner135stores a tile list including information indicating the tiles to which output primitives of the output patch belong. The tile list is stored in the bin stream1602of the memory30as a visibility stream, based on a result of performing the binning1616. Unlike the examples described above with reference toFIGS. 10 through 13, the binner135does not determine whether the output primitives of the output patch output from the hull shader121are included in one tile. In other words, the output primitives may be included in one or more tiles.

In operation1721, the GPU10performs the rendering pipeline102-1per tile. The rendering pipeline102-1may include stages of the vertex shading1621performed by the vertex shader115, the hull shading1622performed by the hull shader121, the tessellating1623performed by the tessellator123, the domain shading1624performed by the domain shader125, the geometry shading1625optionally performed by the geometry shader130, the rasterizing1626performed by the rasterizer140, and the pixel shading1627performed by the pixel shader150. Here, the tessellating1623and the domain shading1624may be performed using the first tessellation factor.

FIG. 18is a diagram illustrating an example of a graphics pipeline performed in the GPU10.

Referring toFIG. 18, the graphic pipeline, including the binning pipeline101-3and the rendering pipeline102-2, operates in a mode {circumflex over (5)}, described above with reference toFIG. 7. The graphics pipeline shown inFIG. 18is described in relation to hardware components of the GPU10shown inFIG. 6, wherein only the components and the pipeline stages related to this example are described in detail. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described in association withFIG. 18may be included.

For convenience of description, it is assumed that the graphics pipeline shown inFIG. 18is performed on an example1900of an output patch crossing a plurality of tiles A through D shown inFIG. 19.

The vertex shader115performs vertex shading1811using vertices1801stored in the memory30. The vertex shader115converts the vertices1801and transmits the convert vertices1801to the hull shader121as input control points expressing a surface of a low order.

The hull shader121performs hull shading1812to convert the input control points to output control points to form the output patch1900. The hull shader121transmits information about the output control points to the binner135.

As described above with reference toFIG. 3, the tessellation pipeline300shown inFIG. 3includes all stages of the hull shader121, the tessellator123, and the domain shader125. Yet, according toFIG. 18, the stages of the tessellator123and the domain shader125may be skipped because, as described above with reference toFIG. 9, the binning result of the output patch410may be the same as the binning result of the tessellated primitives425. However, even if the binning results are not the same, the final pixel rendering results may be the same since stages, such as curling, clipping, and HSR, are performed in the rendering pipeline102-2.

The binner135performs binning1813or tiling using output primitives of the output patch1900output from the hull shader121. In other words, the binner135performs a depth test (or a tile Z test) to predict a tile list indicating information about tiles to which the output primitives belong. Here, the binned tile list may be stored in a bin stream1802of the memory30as a visibility stream.

The binner135determines whether the output primitives of the output patch1900output from the hull shader121are included in a plurality of tiles, i.e., tiles A through D shown inFIG. 19, based on a result of performing the binning1813. In other words, the binner135determines whether the output primitives of the output patch1900cross two or more tiles.

When it is determined that the output patch1900is tile-crossed (or when it is determined that the output patch1900is included in the plurality of tiles A through D), the binner135schedules an order in which tiles A through D are to be rendered. In this example, as a result of the scheduling, the binner135determines that tile A is a reference tile, since tile A is scheduled first in the rendering order from among tiles A through D. Here, it is assumed that the reference tile is disposed at an upper left location of the plurality of tiles, i.e., the location of tile A, but the location of the reference tile is not limited thereto. For example, the reference tile may be located as a lower left tile, an upper right tile, a lower right tile, or a center tile.

The binner135schedules a time of performing the rendering pipeline102-2on the reference tile, i.e., tile A, before any of the neighboring tiles, i.e., tiles B through D. The rendering pipeline102-2may be performed on tiles A through D sequentially by one processor unit (or one processor core) in the GPU10, or in parallel by a plurality of processor units (or a plurality of processor cores) in the GPU10. The determining of the reference tile and the scheduling of the performance timing may be executed by the controller170, or another component in the GPU10, instead of the binner135. In other words, a component that determines the reference tile and schedules the performance timing is not limited to the binner135.

When it is determined that the output patch1900is tile-crossed, the binner135stores the determined reference tile and the scheduled performance timing in the memory30.

On the other hand, when it is determined that the output patch1900is not tile-crossed (or when it is determined that the output patch1900is included only in one tile), the binner135does not determine a reference tile and schedule a performance timing.

After the binning pipeline101-3is completed, the GPU10performs the rendering pipeline102-2per tile. Here, since it is determined that tile A is the reference tile in the binning pipeline101-3, the GPU10performs the rendering pipeline102-2on tile A first.

The rendering pipeline102-2performed on tile A may include stages of vertex shading1821performed by the vertex shader115, hull shading1822performed by the hull shader121, tessellating1823performed by the tessellator123, domain shading1824performed by the domain shader125, geometry shading1825optionally performed by the geometry shader130, rasterizing1826performed by the rasterizer140, and pixel shading1827performed by the pixel shader150. The result of performing the pixel shading1827by the pixel shader150may be stored in a buffer1803.

Meanwhile, the rendering pipeline102-2performed on tile A additionally performs binning1828using the binner135. In detail, the binner135performs the binning1828to generate visibility streams indicating whether the output patch1900is visible in each of the neighboring tiles adjacent to tile A, i.e., tiles B through D. Here, the visibility stream may include any type of visibility stream described herein. Accordingly, the GPU10may process only visible vertices, visible primitives, or visible patches when the rendering pipeline102-2is independently performed on tiles B through D using the visibility streams of tiles B through D. The visibility streams of tiles B through D are generated when the rendering pipeline102-2is performed on tile A. As a result, data throughput in the rendering pipeline102-2performed on tiles B through D may be reduced.

Since the graphics pipeline shown inFIG. 18, operating according to mode {circumflex over (5)} described above, may skip tessellating performed by the tessellator123in the binning pipeline101-3, tessellated vertices (or tessellated primitives) may not be produced. Accordingly, throughput of graphic data may be lowered in the graphics pipeline shown inFIG. 18as compared to the tessellation pipeline300shown inFIG. 3because the tessellator123of pipeline300has to perform the tessellating1015.

FIG. 19is a flowchart of another example of a method for implementing a graphics pipeline performed in the GPU10. The method shown inFIG. 19may be used to implement the graphics pipeline shown inFIG. 18, which includes the binning pipeline101-3and the rendering pipeline102-2operating according to mode {circumflex over (5)}. Thus, descriptions associated withFIG. 18may apply toFIG. 19, even if omitted.

A pipeline1910including operations1911through1915corresponds to the binning pipeline101-3, and a pipeline1920including operations1921through1924corresponds to the rendering pipeline102-2performed on a reference tile, i.e., tile A.

In operation1911, the vertex shader115performs the vertex shading1811using the vertices1801stored in the memory30.

In operation1912, the hull shader performs the hull shading1812to convert input control points to output control points that form the output patch1900.

In operation1913, the binner135performs the binning1813or tiling on the output control points of the output patch1900. Then, the binner135creates a tile list including information indicating tiles to which output primitives of the output patch1900belong based on a result of performing the binning1813. The binner135stores the tile list in the bin stream1802of the memory30.

In operation1914, the binner135determines whether the output primitives of the output patch1900output from the hull shader121are included in the plurality of tiles, for example, tiles A through D. In other words, the binner135determines whether there is tile-crossing of the output primitives of the output patch1900. If the binner135determines that the output patch1900is tile-crossed, operation1915is performed, and if the binner135determines that the output patch1900is not tile-crossed, operation1930is performed.

In operation1915, the binner135schedules a rendering order of tiles A through D. Based on a result of the scheduling, the binner135may determine that tile A is a reference tile, since tile A is scheduled as the first tile in rendering order from among tiles A through D.

In operation1921, the vertex shader115performs the vertex shading1821on tile A using the vertices1801stored in the vertex shader115.

In operation1922, the GPU10performs a tessellation pipeline on tile A including the hull shading1822performed by the hull shader121, the tessellating1823performed by the tessellator123, and the domain shading1824performed by the domain shader125.

In operation1923, the GPU10renders tessellated primitives of tile A that are produced in the tessellation pipeline. In other words, the GPU10performs the rasterizing1826and the pixel shading1827on tile A.

In operation1924, the binner135performs the binning1828to generate visibility streams indicating whether the output patch1900is visible in each of neighboring tiles, i.e., tiles B through D, and the binner135stores the visibility stream of tiles B through D. Although not shown inFIG. 19, the GPU10performs the rendering pipeline102-2on tiles B through D using the stored visibility streams. Here, when the rendering pipeline102-2is performed on tiles B through D, only visible vertices, visible primitives, or visible patches are processed according to the visibility streams of tiles B through D.

If it is determined that the output patch1900is not tile-crossed (if it is determined that the output patch1900is included in only one tile), the GPU10performs the rendering pipeline102-2on the tile including the output patch1900.

FIG. 20is a diagram illustrating an example of a graphics pipeline performed in the GPU10.

Referring toFIG. 20, the graphic pipeline including the binning pipeline101-4and the rendering pipeline102-2operates in mode {circumflex over (6)}, as described above with reference toFIG. 7. The graphics pipeline shown inFIG. 20is described in relation to the hardware components of the GPU10shown inFIG. 6, wherein only the components and the pipeline stages related to this example are described. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described inFIG. 20may be included.

For convenience of description, it is assumed that the graphics pipeline shown inFIG. 20is performed on an output patch2100crossing a plurality of tiles A through D, as shown inFIG. 21.

The vertex shader115performs vertex shading2011using vertices2001stored in the memory30. The vertex shader115converts the vertices2001and transmits the converted vertices2001to the hull shader212as input control points expressing a surface of a low order.

The hull shader121performs hull shading2012to convert the input control points to output control points that form the output patch2100. The hull shader212generates the output control points forming the output patch2100and determines a first tessellation factor at the same time.

The tessellator123receives the first tessellation factor from the hull shader212, and sets a new, second tessellation factor that is lower than the first tessellation factor. Then, the tessellator123performs tessellating2013that calculates uvw coordinates and weights of the output control points in barycentric coordinates using the newly set second tessellation factor.

The domain shader125performs domain shading2014to produce tessellated vertices (or tessellated primitives) using information about the output control points of the output patch2100, the second tessellation factor, the uvw coordinates (of which the w coordinate is optional), and the weights received from the tessellator123.

The geometry shader130is an optional component that may be used to perform geometry shading2015to produce additional vertices (or primitives) from the tessellated vertices (or the tessellated primitives) received from the domain shader125. Accordingly, the geometry shading2015may be skipped.

The binner135performs binning2016or tiling using the tessellated primitives (or tessellated vertices) that are tessellated with the second tessellation factor. In other words, the binner135performs a depth test (or a tile Z test) to predict a tile list including information indicating tiles to which the tessellated primitives (tessellated vertices) that are tessellated with the second tessellation factor belong. Here, the binned tile list may be stored in a bin stream2002of the memory as a visibility stream.

The binner135determines whether the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in a plurality of tiles, for example, tiles A through D shown inFIG. 21. In other words, the binner135determines tile-crossing of the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor.

If it is determined that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are tile-crossed (or if it is determined that the output patch2100is included in the plurality of tiles A through D), the binner135schedules an order of the rendering of tiles A through D. Based on a result of the scheduling, the binner135may determine that tile A is a reference tile, since tile A is scheduled as the first tile in the rendering order from among tiles A through D. Here, it is assumed that the reference tile, i.e., tile A, is disposed at an upper left location from among a plurality of tiles. However, the location of the reference tile is not limited thereto, and the reference tile may be a lower left tile, an upper right tile, a lower right tile, or a center tile.

The binner135schedules a time of performing the rendering pipeline102-2on the reference tile, i.e., tile A, before any of the neighboring tiles, i.e., tiles B through D. The rendering pipeline102-2may be performed on tiles A through D sequentially by one processor unit (or one processor core) in the GPU10, or in parallel by a plurality of processor units (or a plurality of processor cores) in the GPU10. The determining of the reference tile and the scheduling of the performance timing may be performed by the controller170, or another component in the GPU10, instead of the binner135. In other words, a component that determines the reference tile and schedules the performance timing is not limited to the binner135.

When it is determined that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are tile-crossed, the binner135stores the determined reference tile and the scheduled performance timing in the memory30.

On the other hand, when it is determined that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are not tile-crossed (or when it is determined that the output patch2100is included only in one tile), the binner135does not determine a reference tile and schedule a performance timing.

When the binning pipeline101-4is completed, the GPU10performs the rendering pipeline102-2per tile. Here, the GPU10first performs the rendering pipeline102-2on tile A, since tile A is determined as the reference tile in the binning pipeline101-4.

The rendering pipeline102-2performed on tile A may include stages of vertex shading2021performed by the vertex shader115, hull shading2022performed by the hull shader121, tessellating2023performed by the tessellator123, domain shading2024performed by the domain shader125, geometry shading2025optionally performed by the geometry shader130, rasterizing2026performed by the rasterizer140, and pixel shading2027performed by the pixel shader150. The result of performing the pixel shading2027by the pixel shader150may be stored in a buffer2003.

Meanwhile, in the rendering pipeline102-2performed on the reference tile, i.e., tile A, binning2028is additionally performed by the binner135. In detail, the binner135performs the binning2028that generates visibility streams indicating whether the output patch2100is visible in each of neighboring tiles adjacent to tile A, i.e., tiles B through D. Here, the visibility streams may include all the types of visibility streams described herein. Accordingly, the GPU10may process only visible vertices, visible primitives, or visible patches when the rendering pipeline102-2is independently performed on tiles B through D, using the visibility streams of tiles B through D. The visibility streams of tiles B through D are generated in the rendering pipeline102-2performed on tile A. As a result, data throughput in the rendering pipeline102-2performed on tiles B through D may be reduced.

The binning pipeline101-4shown inFIG. 20, operating according to mode {circumflex over (6)} described above, produces fewer tessellated primitives using a lower tessellator factor. Thus, the throughput of graphic data for the graphics pipeline shown inFIG. 20may be lowered as compared to the tessellation pipeline300shown inFIG. 3.

FIG. 21is a flowchart of another example of a method implementing a graphics pipeline performed in the GPU10. The method shown inFIG. 21may be used to implement the graphics pipeline shown inFIG. 20, which includes the binning pipeline101-4and the rendering pipeline102-2operating according to mode {circumflex over (6)}. Thus, the descriptions associated withFIG. 20may apply to those ofFIG. 21, even if omitted.

A pipeline2110including operations2111through2117corresponds to the binning pipeline101-4, and a pipeline2120including operations2121through2124corresponds to the rendering pipeline102-2performed on a reference tile, i.e., tile A.

In operation2111, the vertex shader115performs the vertex shading2011using the vertices2001stored in the memory30.

In operation2112, the hull shader121performs the hull shading2012to convert input control points to output control points and forms the output patch2100.

In operation2113, the tessellator123performs the tessellating2013on the output control points using a second tessellation factor that is lower than a first tessellation factor determined by the hull shader121.

In operation2114, the domain shader125performs the domain shading2014to produce tessellated vertices (or tessellated primitives) using information about the output control points, the second tessellation factor, the uvw coordinates (of which the w coordinate is optional), and weights received from the tessellator123.

In operation2115, the binner135performs the binning2016or tiling using the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor. Then, the binner135stores a tile list including information indicating tiles to which the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor belong, based on a result of performing the binning2016. The binner stores the tile list in the bin stream2002of the memory30.

In operation2116, the binner135determines whether the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are included in a plurality of tiles, i.e., tiles A through D. In other words, the binner135determines tile-crossing of the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor. When the binner135determines that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are tile-crossed, operation2117is performed, and when the binner135determines that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are not tile-crossed, operation2130is performed.

In operation2117, the binner135schedules a rendering order of tiles A through D. Based on a result of the scheduling, the binner135may determine that tile A is a reference tile, since tile A is scheduled first in the rendering order among tiles A through D.

In operation2121, the vertex shader115performs the vertex shading2021on tile A using the vertices2001stored in the memory30.

In operation2122, the GPU10performs a tessellation pipeline on tile A including the hull shading2022performed by the hull shader121, the tessellating2023performed by the tessellator123, and the domain shading2024performed by the domain shader125.

In operation2123, the GPU10renders tessellation primitives of tile A, which are produced in the tessellation pipeline. In other words, the GPU10performs the rasterizing2026and the pixel shading2027on tile A.

In operation2124, the binner135performs the binning2028to generate visibility streams indicating whether the output patch2100is visible in each of the neighboring tiles, i.e., tiles B through D. The binner135stores the visibility streams of tiles B through D. Although not shown inFIG. 21, the GPU10performs the rendering pipeline102-2on tiles B through D using the stored visibility streams. Here, the rendering pipeline102-2performed on tiles B through D processes only visible vertices, visible primitives, or visible patches using the visibility streams of tiles B through D.

In operation2130, the GPU10performs the rendering pipeline102-2on tile including the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor when it is determined in operation2116that the tessellated primitives (the tessellated vertices) that are tessellated with the second tessellation factor are not tile-crossed (i.e., are included in one tile).

FIG. 22is a diagram illustrating an example of a case when a tile list to which a patch belongs and a tile list to which tessellated primitives belong are different based on a result of tessellating the patch.

Generally, in the tessellation pipeline300shown inFIG. 3, the hull shader121and the domain shader125are programmable, but the tessellator123is not programmable. Thus, a developer who codes the tessellation pipeline300may program the hull shader121and the domain shader125such that an output patch2213is included in one tile, i.e., tile0, but tessellated primitives2225are included in two tiles, i.e., tile0and tile1. In other words, primitives2230may be mispredicted and exist in the tessellated primitives2225. A graphics pipeline in which a mispredicted tile list occurs in a binning pipeline during a rendering pipeline is described below with reference toFIGS. 23 and 24.

FIG. 23is a diagram illustrating another example of a graphics pipeline performed in the GPU10.

Referring toFIG. 23, the graphics pipeline including the binning pipeline101-3and the first and second rendering pipelines102-3and102-4operates in mode {circumflex over (7)}, described above with reference toFIG. 7, and the graphics pipeline including the binning pipeline101-4and the first and second rendering pipelines102-3and102-4operates in mode {circumflex over (8)}, also described above with reference toFIG. 7. The graphics pipeline shown inFIG. 23is described in relation to hardware components of the GPU10shown inFIG. 6, wherein only the components and the pipeline stages related to this example are described. Thus, one of ordinary skill in the art will appreciate that general-purpose components and pipeline stages other than those described inFIG. 23may be included.

The GPU10performs the binning pipeline101-3or101-4described above. A binning result of the binning pipeline101-3or101-4may be stored as a visibility stream in a bin stream2302of the memory30. Then, the GPU10performs the first rendering pipeline102-3. The first rendering pipeline102-3is performed per tile. As shown inFIG. 23, it is assumed that tile X is the current tile on which the first rendering pipeline102-3is performed.

The vertex shader115performs vertex shading2311using vertices2301of tile X based on the binning result stored in the bin stream2302. The vertex shader115converts the vertices2301and transmits the converted vertices2301to the hull shader121as input control points expressing a surface of a low order.

The hull shader121performs hull shading2312that converts the input control points to output control points forming an output patch. The hull shader121generates the output control points determines a tessellation factor TF at the same time.

The tessellator123performs tessellating2313to calculate uvw coordinates and weights of the output control points in barycentric coordinates using the tessellation factor TF received from the hull shader121.

The domain shader125performs domain shading2314to produce tessellated vertices (or tessellated primitives) using information about the output control points, the tessellation factor TF, the uvw coordinates (of which the w coordinate is optional), and the weights received from the tessellator123.

The geometry shader130is an optional component that may be used to perform geometry shading2315to produce additional vertices (or primitives) from the tessellated vertices (or the tessellated primitives) received from the domain shader125. Accordingly, as the geometry shader130is optional, the geometry shading2315may be skipped.

The rasterizer140performs rasterizing2316on the tessellated vertices (or the tessellated primitives) included in the current tile, i.e., tile X, and the pixel shader150performs pixel shading2317on pixels corresponding to the rasterized primitives. The result of performing the pixel shading2317is stored in a buffer2304.

The buffer135performs binning2318or tiling on the tessellated primitives (the tessellated primitives) included in tile X. The buffer135determines whether there is a mispredicted tile from among tile locations of the tessellated primitives (the tessellated vertices) included in tile X by comparing the result of performing the binning2318with a tile list stored in the bin stream2302from the binning pipeline101-3or101-4. When it is determined that there is no mispredicted tile, the GPU10performs the first rendering pipeline102-3on a tile following tile X. On the other hand, when it is determined that there is a mispredicted tile, the binner135updates the tile list of the mispredicted tile in the bin stream2302or stores the tile list of the mispredicted tile in a mispredicted bin stream2303. Here, the tile list of the mispredicted tile is updated in the bin stream2302when rendering has not been started on the mispredicted tile; however, when rendering has already been completed on the mispredicted tile, the tile list of mispredicted tile is stored in the mispredicted bin stream2303.

After the first rendering pipeline102-3is performed per tile on all tiles, the GPU10determines whether there is a mispredicted tile in the mispredicted bin stream2303. When there is a mispredicted tile list in the mispredicted bin stream2303, the GPU10performs the second rendering pipeline102-4on tiles included in the mispredicted tile list. In this example, the tiles included in the mispredicted tile list are referred to as super tiles. The second rendering pipeline102-4is performed per super tile on the tiles included in the mispredicted tile list. In other words, the GPU10performs the second rendering pipeline102-4per super tile including stages of vertex shading2321performed by the vertex shader115, hull shading2322performed by the hull shader121, tessellating2323performed by the tessellator123, domain shading2324performed by the domain shader125, geometry shading2325optionally performed by the geometry shader130, rasterizing2326performed by the rasterizer140, and pixel shading2327performed by the pixel shader150per tile or. Results of performing the pixel shading2327on the super tiles are stored in the buffer2304, and thus the graphics pipeline is completed.

FIG. 24is a flowchart of another example of a method for implementing a graphics pipeline performed in the GPU10. The method shown inFIG. 24may be used to implement the graphics pipeline shown inFIG. 23, which includes the binning pipeline101-3or101-4, the first rendering pipeline102-3, and the second rendering pipeline102-4operating according to modes {circumflex over (7)} or {circumflex over (8)}. Thus, the descriptions associated withFIG. 23may apply to those ofFIG. 24, even if omitted.

In operation2401, the GPU10bins a tile list by performing the binning pipeline101-3or101-4.

In operation2402, the GPU10stores the binned tile list in a first bin stream, i.e., the bin stream2302shown inFIG. 23.

In operation2403, the GPU10performs a tessellation pipeline shown inFIG. 23on a current tile, i.e., a tile X, including the hull shading2312, the tessellating2313, and the domain shading2314from the first rendering pipeline102-3using the first bin stream2302.

In operation2404, the GPU10performs a remaining pipeline on tile X including the rasterizing2316and the pixel shading2317using tessellation primitives output from the tessellation pipeline.

In operation2405, the GPU10determines whether rendering of all tiles is completed. When it is determined that the rendering of all tiles is completed, operation2410is performed. When it is determined that the rendering of all tiles is not completed, operation2403is performed on a tile following tile X.

In operation2406, the GPU10performs the binning2318or tiling on tessellated primitives (tessellated vertices) included in the current tile, i.e., tile X. The GPU10determines whether there is a mispredicted tile from among tile locations of the tessellated primitives (the tessellated vertices) included in tile X by comparing the result of the binning2318and the tile list stored in the bin stream2302in the binning pipeline101-3or101-4. When it is determined that there is no mispredicted tile, operation2405is performed. When it is determined that there is a mispredicted tile, operation2407is performed.

In operation2407, the GPU10determines whether rendering on the mispredicted tile has already been completed. When it is determined that the rendering on the mispredicted tile has already been completed, operation2408is performed. When it is determined that the rendering on the mispredicted tile has not already been completed, operation2409is performed.

In operation2408, the GPU10stores a tile list of the mispredicted tile in a second bin stream, i.e., the mispredicted bin stream2303shown inFIG. 23.

In operation2409, the GPU10updates the tile list of the mispredicted tile in the first bin stream, i.e., the bin stream2302shown inFIG. 23.

In operation2410, the GPU10determines whether there is a mispredicted tile list in the second bin stream. When it is determined that there is no mispredicted tile list, the graphics pipeline ends. When it is determined that there is a mispredicted tile list, operation2411is performed.

In operation2411, the GPU10performs the second rendering pipeline102-4shown inFIG. 23on the mispredicted tile (i.e., a super tile) based on the second bin stream.

FIG. 25is a block diagram of an example of a detailed hardware structure of the computing device1.

Referring toFIG. 25, the computing apparatus1includes the GPU10, the CPU20, the memory30, buffers35, the bus40, a display unit2501, an input unit2503, and a communicator2505. Components of the computing apparatus1shown inFIG. 25are exemplary, and one of ordinary skill in the art will appreciate that the computing apparatus1may include general-purpose components other than those shown inFIG. 25.

The GPU10, the CPU20, and the memory30may perform operations and functions described above.

For example, the hardware components of the GPU10and the CPU20may be implemented by one or more processors or processing units. A processor or processing unit is implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices known to one of ordinary skill in the art that is capable of responding to and executing instructions in a defined manner to achieve a desired result. In one example, a processor or a processing unit includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or the processing unit. Hardware components implemented by a processor or a processing unit execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described herein with respect toFIGS. 3, 7, 10-21, 23, 24, 28, 29, and 32-35. The hardware components also access, manipulate, process, create, and store data in response to execution of the instructions or software. For simplicity, the singular term “processor” or “processing unit” may be used in the description of the examples described herein, but in other examples multiple processors or processing units are used, or a processor or processing unit includes multiple processing elements, or multiple types of processing elements, or both. In one example, a hardware component includes multiple processors, and in another example, a hardware component includes a processor and a controller. A hardware component has any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

The methods perform the operations described herein with respect toFIGS. 3, 7, 10-21, 23, 24, 28, 29, and 32-35are performed by a processor or a computer as described above executing instructions or software to perform the operations described herein.

The buffers35store tile information output via a tile-based graphics pipeline or tile-based rendering. For example, the buffers35may store a result of performing a depth test on a tile or a result of rendering a tile. InFIG. 25, the buffers35included in the computing apparatus1are separate from the GPU10, the CPU20, and the memory30; however, alternatively, the buffers35may be included in the GPU10, the CPU20, or the memory30.

The display unit2501is a display interfacing unit used to display various types of information to a user, such as information processed or to be processed by the computing apparatus1. The display unit2501may display a graphical user interface (GUI) to visually and intuitively provide information processed by the computing apparatus1to the user. For example, the display unit2501may display graphic data processed by the GPU10. The display unit2501may include any one of various displays, such as a liquid crystal display (LCD), a light-emitting diode (LED) display, and a plasma display panel (PDP).

The input unit2503is an input interfacing unit for receiving information from the user. The input unit2503may be realized as a touch pad, a trackball, a mouse, a keyboard, or a game controller. Alternatively, the display unit2501and the input unit2503may be realized as hardware of an integrated touch screen.

The communicator2505may include a mobile communication module or a wired/wireless local area network (LAN) module for mobile communication, or a Wi-Fi module, a Bluetooth module, or a near-field communication (NFC) module for NFC.

FIGS. 26Aand B are diagrams illustrating examples of conditions used for selecting a type of a graphics pipeline to be processed in the GPU10.

As described above inFIG. 7, any one of mode {circumflex over (1)} through mode {circumflex over (8)} may be selected according to a user input or a graphic processing environment. According to the examples shown inFIG. 26A or 26B, the GPU10may select any one of mode {circumflex over (1)} through mode {circumflex over (8)} based on a ratio of the size of an object2615or2625(or a size of a patch forming the object2615or2625) with respect to the size of one tile2610or2620. For example, the ratios of the sizes of the objects2615and2625(or the sizes of the patches forming the objects2615and2625) with respect to the sizes of the tiles2610and2620are different inFIGS. 26A and 26B. Thus, the GPU10may set a certain threshold range in each of mode {circumflex over (1)} through mode {circumflex over (8)} and control a graphics pipeline to be performed in an efficient mode corresponding to a range to which the ratio belongs.

FIGS. 27A and 27Bare diagrams illustrating examples of conditions used for selecting a type of graphics pipeline to be processed in the GPU10.

According toFIG. 27A or 27B, the GPU10may select any one of mode {circumflex over (1)} through mode {circumflex over (8)} based on a location of an object2715or2725(or a patch forming the object2715or2725) in one tile2710or2720. For example, the distance (a) and the distance (b) are the distance between the boundaries of the tiles2710and2720and the boundaries of the objects2715and2725(or the patches forming the objects2715and2725). The distance (a) and the distance (b) are different inFIGS. 27A and 27B. Thus, the GPU10may set a certain threshold range in each of mode {circumflex over (1)} through mode {circumflex over (8)} and efficiently control a graphics pipeline to be performed in a mode corresponding to the range to which a distance belongs.

FIG. 28is a flow diagram illustrating an example of applying a visibility stream stored in a bin stream of the memory in a graphics pipeline.

Referring toFIG. 28, if the binning pipeline101is performed, when the GPU10executes binning2811, an input-patch visibility stream may be stored in the bin stream2802of the memory30. Also, when the binning2811of the binning pipeline101is performed, an output-primitive visibility stream may be stored in the bin stream2802of the memory30. In this example, the binning2811may correspond to any one of the binning stages included in the various graphics pipelines described above.

The input-patch visibility stream may include information about an input-patch visibility mask indicating visibility of an input patch to be input to the hull shader121which performs hull shading2821of during the rendering pipeline102. For example, the input-patch visibility mask may be in a bit of 0 or 1 indicating whether the input patch is visible in a tile. Thus, using the input-patch visibility stream, the hull shader121is able to perform the hull shading2821only on visible input patches during the rendering pipeline102. As a result, throughput may be reduced in the rendering pipeline102.

Similarly, the output-primitive visibility stream may include information about an output-primitive visibility mask indicating visibility of output primitives. The information about an output-primitive visibility mask is input to perform primitive assembling2822during the rendering pipeline102. For example, the output-primitive visibility mask may include a bit of 0 or 1 indicating whether an output primitive is visible in a tile. Thus, using the output-primitive visibility stream, the GPU10may perform the primitive assembling2822only on visible output primitives during the rendering pipeline102. As a result, throughput may be reduced in the rendering pipeline102.

FIG. 29is a diagram of an example of applying a visibility stream stored in a bin stream of the memory in a graphics pipeline.

Referring toFIG. 29, as described above with reference toFIGS. 18 through 21, when binning2911of the rendering pipeline102is performed on a reference tile, for example, tile A ofFIGS. 19 and 21, a vertex visibility stream may be stored in the bin stream2902of the memory30. Also, when the binning2811of the rendering pipeline102is performed, a domain visibility stream may be stored in the bin stream2902of the memory30. In this example, the binning2911may correspond to any one of the binning stages included in the various graphics pipelines described above, such as, for example the graphics pipelines inFIGS. 19 and 21.

The vertex visibility stream may include information about a vertex visibility mask indicating visibility of a vertex input to the vertex shader115which performs vertex shading2921of during the rendering pipeline102on neighboring tiles, for example, tiles B through D that are adjacent to the reference tile, for example, tile A as shown inFIGS. 19 and 21. For example, the vertex visibility mask may include a bit of 0 or 1 indicating whether a vertex is viewable in a tile. Accordingly, using the vertex visibility stream, the vertex shader115may perform the vertex shading2921only on visible vertices during the rendering pipeline102. As a result, throughput in the rendering pipeline102may be reduced.

Similarly, the domain visibility stream may include information about a domain visibility stream indicating visibility of output patches, which is input to the domain shader125, which performs domain shading2922during the rendering pipeline102. For example, the domain visibility mask may include a bit of 0 or 1 indicating whether an output primitive is viewable in a tile. Accordingly, using the domain visibility stream, the domain shader125performs the domain shading2922only on visible output patches during the rendering pipeline102. As a result, throughput in the rendering pipeline102may be reduced.

Meanwhile, a visibility stream described herein may include an input-patch visibility stream, an output-primitive visibility stream, a vertex visibility mask, or a domain visibility stream, but is not limited thereto.

FIG. 30is a diagram illustrating an example of a visibility stream stored in a bin stream after binning pipeline is completed.

As described above, when the binning pipeline101is completed, the GPU10stores a visibility stream in the memory30. Referring toFIG. 30, the visibility stream may include an input visibility stream and an output visibility stream.

The input visibility stream may include a stream of 1s and 0s with respect to each patch. Each bit denotes whether at least a part of the patch is viewable from a final frame. For example, a bit having a value of 1 in a patch2indicates that the patch2is viewable in the final frame, and bits having values of 0 in other patches indicate that the other patches are not viewable in the final frame. The output visibility stream may include a stream of 1s and 0s with respect to each primitive, wherein a bit having a value of 1 indicates that a primitive contributes to a pixel that is viewable in a final scene (for example, a bit having a value of 1 in a primitive0), and a bit having a value of 0 indicates that a primitive does not contribute to a pixel that is viewable in a final scene (for example, a bit having a value of 0 in a primitive6).

The output visibility streams may be generated per patch. In other words, one output visibility stream may exist per patch of each tile. Alternatively, each tile may have one output visibility stream that connects output primitives produced from the input primitives.

FIG. 31is a diagram illustrating an example of a visibility stream stored in a bin stream after binning pipeline is completed.

Referring toFIG. 31, an output visibility stream3110may be generated with respect to an output patch output from the hull shader121, and an output visibility stream3120may be generated with respect to tessellated primitives output from the domain shader125, but output visibility streams are not limited thereto.

FIG. 32is a combined flow block diagram and flowchart of an example of a method of performing, by the computing apparatus1, a graphics pipeline. The method shown inFIG. 32is related to the examples of operation according to mode {circumflex over (1)} described above with reference toFIGS. 10 and 11. Thus, the descriptions ofFIGS. 10 and 11may apply to the method shown inFIG. 32, even if omitted.

In operation3201, the GPU10of the computing apparatus1performs the binning pipeline101-1in which it determines whether to skip tessellating an output patch output from the hull shader121based on the number of tiles including the output patch and binning a tile list of the output patch or tessellated primitives based on the result of the determination.

In operation3202, the GPU10of the computing apparatus1performs the rendering pipeline102-1per tile based on the binned tile list.

In detail, in operation3201, when the number of tiles that include the output patch is one, the tessellating performed by the tessellator123on the output patch may be skipped. In operation3201, the output patch is generated by the hull shader121which performs hull shading on an input patch, the tile list of the output patch is binned, and it is determined whether the output patch is included in one tile. If it is determined that the output patch is included in one tile, rasterizing may be performed using the binned tile list of the output patch in operation3202. Here, the rasterizing corresponds to a partial stage performed in the rendering pipeline102-1. The rendering pipeline102-1may include various stages, such as a pixel shading stage in addition to a rasterizing stage. When the tessellating is skipped in the binning pipeline101-1, a tessellation pipeline may be performed in operation3202using a bin stream stored with respect to the output patch from the binning pipeline101-1. Meanwhile, in operation3201, the tessellating may be programmed such that a boundary of the output patch includes boundaries formed by the tessellated primitives.

If it is determined that the output patch is included in at least two tiles (or if it is determined that the output patch is not included in one tile), tessellated primitives may be produced by performing tessellating, by the tessellator123, and domain shading, by the domain shader125, on the output patch, in operation3201. Here, rasterizing may be performed using a binned tile list of the tessellated primitives, in operation3202.

Meanwhile, the memory30of the computing apparatus1stores the tile list generated in the binning pipeline101-1and provides the stored tile list to the rendering pipeline102-1. In operation3201, if it is determined that the output patch is included in one tile, a visibility stream of the output patch may be stored in the memory30, and if it is determined that the output patch is included in at least two tiles, a visibility stream of the tessellated primitives may be stored in the memory30.

FIG. 33is a combined flow block diagram and flowchart showing an example of a method of performing, by the computing apparatus1, a graphics pipeline. The method shown inFIG. 33is related to the example of operation in mode {circumflex over (2)}, described above with reference toFIGS. 12 and 13. Thus, descriptions associated withFIGS. 12 and 13may apply to the method shown inFIG. 33, even if omitted.

In operation3301, the GPU10of the computing apparatus1performs the binning pipeline101-2by determining whether to skip tessellating based on a first tessellation factor determined by the hull shader121and the number of tiles including primitives tessellated with a second tessellation factor that is different from the first tessellation factor, and binning a tile list of an output patch output from the hull shader121or primitives tessellated with the first tessellation factor, based on the result of the determination.

In operation3302, the GPU10of the computing apparatus1performs the rendering pipeline102-1per tile based on the binned tile list.

In detail, when the number of tiles that include the primitives tessellated with the second tessellation factor is one, the tessellating based on the first tessellation factor, which is to be performed by the tessellator123, is skipped in operation3301. Here, the second tessellation factor may be lower than the first tessellation factor. In operation3301, the hull shader121performs hull shading to generate the output patch and determine the first tessellation factor. The tessellator123tessellates the output patch based on the second tessellation factor that is lower than the first tessellation factor to produce the primitives tessellated with the second tessellation factor. The domain shader125performs domain shading tessellated primitives, and it is determined whether the primitives tessellated with the second tessellation factor are included in one tile. Here, when it is determined that the primitives tessellated with the second tessellation factor are included in one tile, rasterizing may be performed using the binned tile list of the output patch in operation3302. Here, the rasterizing corresponds to a partial stage performed in the rendering pipeline102-1. The rendering pipeline102-1may include various stages, such as a pixel shading stage in addition to a rasterizing stage. Meanwhile, in operation3301, the tessellating may be programmed such that a boundary formed by the primitives tessellated with the first tessellation factor includes a boundary formed by the primitives tessellated with the second tessellation factor.

When it is determined that the primitives tessellated with the second tessellation factor are included in at least two tiles (or when it is determined that the primitives tessellated with the second tessellation factor are not included in one tile), the primitives tessellated with the first tessellation factor may be produced in operation3301by performing tessellating using the tessellator123and domain shading using the domain shader125on the output patch based on the first tessellation factor. Here, rasterizing and pixel shading may be performed in operation3302using the binned tile list of the primitives tessellated with the first tessellation factor.

Meanwhile, the memory30of the computing apparatus1stores the tile list generated in the binning pipeline101-2and provides the stored tile list to the rendering pipeline102-1. In operation3301, when it is determined that the primitives tessellated with the second tessellation factor are included in one tile, a visibility stream of the output patch is stored in the memory30, and when it is determined that the primitives tessellated with the second tessellation factor are included in at least two tiles, a visibility stream of the primitives tessellated with the first tessellation factor is stored in the memory30.

FIG. 34is a combined flow block diagram and flowchart of another example of a method of performing, by the computing apparatus1, a graphics pipeline. The method shown inFIG. 34is related to the examples of operating in mode {circumflex over (5)} described above with reference toFIGS. 18 and 19. Thus, the descriptions associated withFIGS. 18 and 19may apply to the method shown inFIG. 34, even if omitted.

In operation3401, the GPU10of the computing apparatus1performs the binning pipeline101-3by binning an output patch output from the hull shader121to determine whether the output patch is included in a plurality of tiles, and if it is determined that the output patch is included in the tiles, scheduling a rendering order of the tiles.

In operation3402, the GPU10of the computing apparatus1performs the rendering pipeline102-2per tile based on the scheduled rendering order.

In detail, in operation3401, tessellating on the output patch, which is to be performed by the tessellator123, may be skipped. In operation3401, the hull shader121performs hull shading on an input patch to generate the output patch, a tile list of the output patch is binned, it is determined whether the output patch is included in the plurality of tiles, and if it is determined that the output patch is included in the plurality of tiles, a first tile (a reference tile, for example, tile A shown inFIG. 19) corresponding to a first rendering order from among the plurality of tiles is determined.

In operation3402, a first rendering pipeline is performed on the first tile, and a second rendering pipeline is performed on a neighboring tile (for example, tiles B, C, or D shown inFIG. 19). The second rendering pipeline performs rendering on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile based on a visibility stream generated in the first rendering pipeline. The first and second rendering pipelines shown inFIG. 34are parts of the rendering pipeline102-2, and are different from the first and second rendering pipelines102-3and102-4shown inFIG. 7.

The memory30of the computing apparatus1stores a visibility stream generated in the rendering pipeline102-2performed on the first tile, and provides the stored visibility stream to the rendering pipeline102-2performed on the neighboring tile. In other words, in operation3401, a visibility stream generated in the rendering pipeline102-2performed on the first tile may be stored in the memory30.

FIG. 35is a combined flow block diagram and flowchart of another example of a method of performing, by the computing apparatus1, a graphics pipeline. The method shown inFIG. 35is related to the examples of operation in mode {circumflex over (6)}, described above with reference toFIGS. 20 and 21. Thus, the descriptions associated withFIGS. 20 and 21may apply to the method shown inFIG. 35, even if omitted.

In operation3501, the GPU10of the computing apparatus1bins primitives tessellated with a second tessellation factor that is different from a first tessellation factor determined by the hull shader121, to determine whether the primitives tessellated with the second tessellation factor are included in a plurality of tiles. When it is determined that the primitives tessellated with the second tessellation factor are included in the plurality of tiles, the GPU10schedules a rendering order of the plurality of tiles.

In operation3502, the GPU10of the computing apparatus1performs the rendering pipeline102-2per tile based on the scheduled rendering order.

In detail, in operation3501, tessellating based on the first tessellation factor, which is to be performed by the tessellator123, may be skipped. Here, the second tessellation factor has a lower value than the first tessellation factor. In operation3501, the hull shader121performs hull shading to generate an output patch and determines the first tessellation factor. The tessellator123performs tessellating on the output patch based on the second tessellation factor that is lower than the first tessellation factor to produce the primitives tessellated with the second tessellation factor. The domain shader125performs domain shading on the primitives tessellated with the second tessellation factor. A tile list of the primitives tessellated with the second tessellation factor is binned, it is determined whether the primitives tessellated with the second tessellation factor are included in the plurality of tiles, and when it is determined that the primitives tessellated with the second tessellation factor are included in the plurality of tiles, a first tile (a reference tile, for example, tile A shown inFIG. 21) corresponding to a first rendering order is determined.

In operation3502, a first rendering pipeline is performed on the first tile, and a second rendering pipeline is performed on a neighboring tile (for example, tiles B, C, or D shown inFIG. 21). In the second rendering pipeline, rendering is performed on at least one of a visible vertex, a visible primitive, and a visible patch of the neighboring tile based on a visibility stream generated in the first rendering pipeline. The first and second rendering pipelines shown inFIG. 35are parts of the rendering pipeline102-2, and are different from the first and second rendering pipelines102-3and102-4shown inFIG. 7.

The memory30of the computing apparatus1stores a visibility stream generated in the rendering pipeline102-2performed on the first tile, and provides the stored visibility stream to the rendering pipeline102-2performed on the neighboring tile. In other words, in operation3501, a visibility stream generated in the rendering pipeline102-2performed on the first tile may be stored in the memory30.

As described above, according to one or more exemplary embodiments, throughput of a GPU may be reduced and a processing speed may be increased in a tessellation pipeline that is a part of a graphics pipeline processed by the GPU, since a tessellator skips tessellating or performs tessellating using a lower tessellation factor.