Radio frequency peak detection with subthreshold biasing

A radio-frequency peak amplitude detection circuit includes a load capacitor, a current source that charges the load capacitor and set the bias current for the field effect transistors, and a pair of field effect transistors. The gates of the field effect transistors are biased at a level below the threshold voltage of the transistors. The transistors are arranged in parallel with the capacitor and are operable to drain the capacitor at a rate determined by a differential input at the gates of the transistors. The voltage across the load capacitor is low-pass filtered and has a voltage level representative of the amplitude of the differential input signal.

BACKGROUND OF THE INVENTION

Communications transceivers may utilize numerous architectures to recover data from a modulated carrier signal. These architectures include coherent demodulation, using either intermediate frequency conversion or direct-conversion receivers. Such receivers typically recover or regenerate the communications carrier signal using a phase-locked loop (PLL) and coherent demodulation. Recently, polar receiver architectures have been proposed that extract the modulation phase components from a received modulated signal without using a carrier recovery circuitry. However, the proposed polar receiver architectures and associated signal processing have deficiencies that result in poor performance and high bit error rates (BER). Accordingly, there is a need for improved polar receiver signal processing and architectures.

Various signal processing architectures often make use of peak detectors to measure the peak level of a radio frequency signal. However, such detectors frequently require the use of a relatively high signal input level. For example, the amplitude detector disclosed by C. Zhang, R. Gharpurey, and J. A. Abraham, “Built-In Test of RF Mixers Using RF Amplitude Detectors,” IEEE ISQUED, 2007, requires an input signal amplitude of at least around 100 mV. For wireless receiver applications, a signal of that level can often be achieved only with the use of an additional amplifier to amplify the input of the peak detector. However, the use of an amplifier can lead to undesirably high levels of power consumption.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIG. 1, a peak detection circuit100includes a load capacitor102with capacitance CL. The load capacitor102is connected between a common node106and ground. A current source104is connected to the common node106and operates to supply a current Ibiasto charge the load capacitor102and set the correct bias current for transistors M1and M2. The peak detection circuit100includes a first field effect transistor M1and a second field effect transistor M2. The field effect transistors M1and M2may be insulated-gate transistors such as MOSFET transistors. Transistors M1and M2preferably have matched electrical characteristics and physical size. For example, transistors M1and M2preferably have substantially the same length and width, and same values of the threshold voltage Vth, and the slope factor n, where n=1+CD/COX, with CDbeing the capacitance of the depletion layer and COXbeing the capacitance of the insulating layer.

The channels of transistors M1and M2are arranged between the common node106and ground. The channels of transistors M1and M2are thus arranged in parallel with each other and in parallel with the load capacitor102.

How the current is divided between the channels of transistors M1and M2is controlled by respective gates of those transistors. The gate of transistor M1is coupled to a first differential input node108through a first capacitive coupling112, and the gate of transistor M2is coupled to a second differential input node110through a second capacitive coupling114. Because the channels of the transistors M1and M2are arranged in parallel with the load capacitor102, the load capacitor102is permitted to discharge through the channels of transistors M1and M2at a rate determined by the voltage level at the gates of the transistors M1and M2.

A low-pass filter116is connected between the load capacitor102and an output node118. The low-pass filter116may be an RC (resistor-capacitor) circuit that includes a series resistor130and a parallel capacitor132. Other types of low-pass filter may also be implemented.

The gates of the transistors M1and M2are biased by the output of a biasing circuit120. The biasing circuit is operative to provide a biasing voltage VBthat is lower than the threshold voltage Vthof the first and second transistors M1and M2. The biasing circuit120has a bias output node122that is connected to the gates of transistors M1and M2through, respectively, bias resistors RB1and RB2.

The biasing circuit120includes a third field-effect transistor M3and a fourth field effect transistor M4. The transistors M3and M4preferably have electrical characteristics that are matched with the characteristics of transistors M1and M2. That is, the physical size (length and width), the threshold voltage Vth, and the slope factor n, preferably have substantially the same values for all four transistors M1, M2, M3, and M4. The gates of the third and fourth transistors M3and M4are connected to the bias output node122. The channels of the transistors M3and M4are connected in parallel with each other.

The biasing circuit120further includes a current source124, which is configured to provide substantially the same current Ibiasas the current provided by the current source104. The current source124provides the current Ibiasthrough the channels of transistors M3and M4. A comparator circuit126is operative to apply a voltage to the bias output node122. The comparator circuit126is responsive to a voltage level across the channels of the third and fourth transistors. In some embodiments, the comparator circuit126is implemented with a differential operational amplifier that has a first amplifier input connected to a reference voltage source128and a second amplifier input connected between the current source124and the channels of the third and fourth transistors M3and M4.

The first amplifier input connected to the reference voltage source128is an inverting input, and the second amplifier input connected between the current source124and the channels of the third and fourth transistors M3and M4is a non-inverting input. If the voltage across the channels of the third and fourth transistors M3and M4rises above the reference voltage VREF, then the operational amplifier126increases the output voltage on the bias output node122. This, in turn, increases the voltage at the gates of transistors M3and M4and thereby lowers the voltage drop across the channels of those transistors. Conversely, if the voltage across the channels of the third and fourth transistors M3and M4falls below the reference voltage VREF, then the operational amplifier126decreases the output voltage on the bias output node122. This, in turn, decreases the voltage at the gates of transistors M3and M4and thereby raises the voltage drop across the channels of those transistors. In this way the comparator circuit126operates to keep the voltage drop across the channels of the third and fourth transistors M3and M4at the same level as the reference voltage VREF. A resistor Rcand capacitor Ccform a compensation circuit to ensure the stability of the feedback.

Where the electrical characteristics of transistors M1, M2, M3, and M4are matched, and where the current Ibiasis the same at both current source104and current source124, then the voltage across the channels of M1and M2will be the same as the voltage across the channels of M3and M4. That is, the voltage VXat common node106will mirror the voltage VREFsupplied to the biasing circuit120in the absence of an input signal.

In the peak detection circuit100, the first and second transistors M1and M2each have a first end, which may be a drain terminal, and a second end, which may be a source terminal. The load capacitor102likewise has a first terminal and a second terminal. In the embodiment ofFIG. 1, the drain terminals of M1and M2are both attached to the common node106, as is one of the terminals of the load capacitor102. Also, the source terminals of M1and M2are both attached to ground, as is the other terminal of the load capacitor102.

The peak detection circuit100operates according to the following principles to provide an output representative of the peak radio frequency amplitude. Suppose that a radio-frequency differential input signal is applied to the signal input nodes108and110, and that the signal can be represented by the following equations:
vin+=A·sin(ωt),
vin−=−A·sin(ωt).

The gates of transistors M1and M2are biased at a level below the threshold voltage Vth. The current IMof each transistors M1and M2in the sub-threshold region is described to a reasonable approximation by the following equation:

where I0is the reverse saturation current, Vgsis the gate-source voltage of the transistor, Vthis the threshold voltage of the transistor, n is parameter determined by the doping of the transistor bulk and the oxide capacitor, and VTis the thermal voltage.

Absent an input signal, in a steady-state condition, the sum of the current of M1and M2is equal to the bias current Ibias:

When an alternating-current (AC) input is injected into the circuit:
Vgs1=VB+vin+=VB+A·sin(ωt),
Vgs2=VB+vin−=VB−A·sin(ωt).

Remembering the Taylor expansion for ex:

the sum of the current of M1and M2becomes, to a second-order approximation,

So the load current ILis:

As seen from this equation, the net current discharging the load capacitor is proportional to the square of the amplitude of the differential input signal. Assuming the resistor of the RC filter is large enough to isolate the circuit connected after the peak detector, the voltage VXat the common node106is

The time constant of the RC filter is set low enough to eliminate the undesired AC component at the output. In that way, the voltage VOUTat the output node118becomes a constant value representative of the amplitude of the radio-frequency input signal. The higher the input amplitude is, the lower the output voltage will be compared to the initial bias point.

In the absence of an input signal, voltage VXat the common node106mirrors the reference voltage VREF, and in the steady state, the filtered output voltage VOUTwill have this same value. As noted above, the introduction of a signal at the differential input nodes causes the values of VXand VOUTto drop. However, those values cannot drop below ground. Thus, the reference voltage VREFis selected to permit sufficient dynamic range for the expected uses of the circuit. For example, where the output voltage VOUTwill be provided to an analog-to-digital converter, the value of VREFmay be selected to represent the highest voltage level readable by the analog-to-digital converter. It should be noted that the mirroring by VXof the reference voltage VREFis not necessarily exact and may vary due to, for example, mismatch between the properties of the transistors M1, M2, M3, M4and in the current sources104and124due to the fabrication process. The value of VREFcan be adjusted accordingly to bring the quiescent level of VXto the desired value.

The physical sizes of the transistors M1, M2, M3, and M4are selected such that the bias voltage VBis maintained at a level below the threshold voltages of those transistors when the current Ibiasis provided. This is done because, for a given current, the small signal transconductance of transistors in the sub-threshold region is larger than the transconductance the transistors would have in the saturation region.

A peak detection circuit as describe herein is sensitive to radio frequency inputs with amplitudes of less than around 10 mV, whereas signal amplitudes of around at least 100 mV would be required for a peak detection circuit with transistors biased in the saturation region.

FIG. 2illustrates the operation of a peak detection circuit with the use of a flow chart. It should be understood that the functions illustrated inFIG. 2can be, and generally are, performed simultaneously. The arrows depicted inFIG. 2, thus illustrate logical relationships among functions, rather than a chronological sequence of steps.

Block200illustrates the charging of the load capacitor, performed by, for example, current source104ofFIG. 1. The load capacitor is capable of being discharged through the channels of field effect transistors, such as the first and second transistors M1and M2ofFIG. 1. As illustrated in block210, the gates of these field effect transistors are biased, preferably at a bias voltage below the threshold voltage of the transistors.

As illustrated in block212, a differential signal, such as a differential radio-frequency signal, is applied to the gates of the transistors, and in block214, the load capacitor at least partially discharges through the channels of the field effect transistors at a rate determined by the differential signal applied the gates of the transistors. In a preferred embodiment, the discharging through the gates of the transistors is performed simultaneously with the charging from the current source. Thus, the net amount of charge supplied to or removed from the load capacitor depends on the difference between the rates of charging and discharging. As reflected in the equations given above, the net rate of change in the charge of the load capacitor is proportional to the square of the amplitude of the differential signal.

The level of charge at the load capacitor, and thus the voltage across the load capacitor, includes a radio-frequency AC component. At block216, the voltage across the load capacitor is low-pass filtered to generate an output signal representative of the amplitude of the differential input signal.

The flow chart ofFIG. 2further illustrates the processes involved with the generation of a bias voltage. At block218, current is applied across the channels of replica field-effect transistors, such as the third and fourth transistors M3and M4ofFIG. 1, which replicate the electrical and physical properties of the first and second transistors. In block220, a bias voltage is generated based on the voltage level across the channels of the replica transistors. The operation of block220may be implemented by an operational amplifier such as the amplifier126ofFIG. 1. As noted above, the generated bias voltage is provided (block210) to the gates of the transistors in the peak detection circuit.

In block222, the voltage across the replica transistors is compared with a reference voltage, and in block224, the biasing voltage is adjusted such that the voltage across the channels of the replica transistors matches the reference voltage. Specifically, in response to a determination that the voltage across the channels of the replica transistors is higher than the reference voltage, the biasing voltage is increased. Conversely, in response to a determination that the voltage across the channels of the replica transistors is lower than the reference voltage, the biasing voltage is decreased. The adjustment of the biasing voltage preferably reaches a steady state such that the voltage across the channels of the replica transistors does not substantially vary from the reference voltage.

Accordingly, some embodiments of the present disclosure, or portions thereof, may combine one or more processing devices with one or more software components (e.g., program code, firmware, resident software, micro-code, etc.) stored in a tangible computer-readable memory device, which in combination form a specifically configured apparatus that performs the functions as described herein. These combinations that form specially programmed devices may be generally referred to herein “modules”. The software component portions of the modules may be written in any computer language and may be a portion of a monolithic code base, or may be developed in more discrete code portions such as is typical in object-oriented computer languages. In addition, the modules may be distributed across a plurality of computer platforms, servers, terminals, and the like. A given module may even be implemented such that separate processor devices and/or computing hardware platforms perform the described functions.