Systems and methods for reduced coupling between digital signal lines

Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.

TECHNICAL FIELD

This technical field relates to digital output circuitry and, more particularly, to techniques for improving performance of digital signaling.

BACKGROUND

Integrated circuits and other electronic systems often include signal lines that carry digital signals that transition between logic high voltage levels and logic low voltage levels. Undesirable capacitive coupling can develop between such digital signal lines if they are in close proximity to each other within the integrated circuit or electronic system.

FIG. 1(prior art) is an embodiment100of a block diagram for digital signal lines, for example, within an integrated circuit. Embodiment100represents a cross-section of an integrated circuit with the surface of the integrated circuit being parallel with signal lines102and104. Signal lines102and104represent digital signal lines that flow in one direction across the integrated circuit. Elements106,108,110,112, and114represent digital signal lines that are running perpendicular to signal lines102and104within the integrated circuit. During operation, capacitive coupling can occur between these digital signal lines, particularly, if they are changing voltage levels in close proximity to each other. For example, this can occur when one signal line is carrying a clock signal and another signal line is carrying a data output signal. The capacitor symbols shown between adjacent digital signal lines102,104,106,108,110,112, and114in embodiment100represent parasitic capacitances that can be created by this capacitive coupling between digital signal lines. This parasitic capacitance is often undesirable and can reduce the performance of digital signaling within an integrated circuit and/or electronic system that includes the digital signal lines.

Return-to-zero signaling, as described below with respect toFIG. 2(Prior Art) andFIG. 3(Prior Art), has been used to reduce capacitive coupling by keeping voltage levels for clock or a first data signals from moving in one direction while voltage levels for an adjacent second data signals move in an opposite direction.

FIG. 2(prior art) is a block diagram of an embodiment200for return-to-zero signaling circuitry that can be used to reduce capacitive coupling. As depicted, a data register204receives input data201and a clock signal (CLK)202. The data register204then outputs data206based upon a clock edge for the clock signal (CLK)202, such as a rising clock edge. Return-to-zero circuitry208receives the data206and the clock signal (CLK)202, and the return-to-zero circuitry208outputs return-to-zero (RTZ) data210. In particular, if data206is at a low logic level for a clock cycle, the return-to-zero circuitry208outputs a low logic level for the RTZ data210throughout the full clock cycle. However, if the data206is at a high logic level for a clock cycle, the return-to-zero circuitry208outputs a high logic level for the RTZ data210during a first portion of the clock cycle but then returns the RTZ data210to a low logic level during a second portion of the clock cycle before the end of the clock cycle.

FIG. 3(prior art) is an embodiment300of a timing diagram for return-to-zero signaling. The y-axis represents logic levels for the clock signal (CLK)202, data206, and RTZ data210. The x-axis represents time. Ten clock cycles are indicated from clock cycle T0 to clock cycle T9. Clock cycle T10 is started, but the complete cycle is not shown. The logic levels for the data206for these ten clock cycles (T0-T1-T2-T3-T4-T5-T6-T7-T8-T9) are 0-1-1-0-1-0-1-1-1-0, respectively. High logic levels are indicated as a logic “1,” and low logic levels are indicated as a logic “0.” While the logic levels for data206are indicated for each clock cycle, the logic levels for the RTZ data210are indicated for each half-cycle. For the embodiment300, the clock cycle begins at each rising edge of the clock signal (CLK)202, and the return-to-zero is configured to occur on the falling edge for the clock signal (CLK)202. Thus, each time the logic level for the data206is a high logic level, the RTZ data210will return to zero (e.g., low logic level) for the last half-cycle on the falling edge of the clock signal (CLK)202, as indicated by arrows302,304,306,308,310, and312. Thus, the logic levels for the RTZ data210for each half-cycle of the ten clock cycles (T0-T1-T2-T3-T4-T5-T6-T7-T8-T9) are 00-10-10-00-10-00-10-10-10-00, respectively. As depicted, the logic level for the RTZ data210stays low for both half-cycles when the data206is at a low logic level (e.g., cycles T0, T3, T5, T9). The logic level for the RTZ data210is high for the first half-cycle and returns to zero for the second half-cycle when the data206is at a high logic level (e.g., cycles T1, T2, T4, T6, T7, T8).

As indicated above, the return-to-zero signaling reduces capacitive coupling between clock and data signal lines by keeping the clock signal from moving in one direction while an adjacent data signal is moving in an opposite direction. In particular, because the RTZ data210has always transitioned to a low logic level by the next clock cycle, the clock signal (CLK)202and the RTZ data210are kept from moving in opposite directions at the same time.

DETAILED DESCRIPTION

Methods and systems are disclosed for reduced coupling between digital signal lines. As described herein, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling described herein reduces capacitive coupling between clock and data signal lines in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations. Different features and variations can be implemented, as desired, and related or modified systems and methods can be utilized, as well.

While return-to-zero signaling reduces capacitive coupling between clock or a first data and an adjacent second data signal lines by keeping the clock or first data signal and the second data signal from moving in opposite directions at the same time, the return-to-zero signaling still requires current flow for each return-to-zero of the signal line. In contrast, for the embodiments described herein, return-to-zero signaling is blocked when the current data being output and the next data to be output are both at high logic levels. As such, the output data stays at a high logic level throughout the current clock cycle and into the next clock cycle without dropping down to a low logic level. This high logic level continues until the next data to be output becomes a low logic level. At that point, the return-to-zero signaling is no longer blocked, and the current data output signal level will be allowed to drop from a high logic level to a low logic level within the clock cycle, as is done in typical return-to-zero signaling. Advantageously, the dynamically blocked return-to-zero signaling described herein reduces coupling between signal lines by blocking return-to-zero voltage level transitions when multiple high logic level data signals are being output. It is further noted that while the embodiments described primarily describe a single stream of two or more bits that are being stored and output in sequence, this single bit stream may be associated with a plurality of bit streams that are being output together in sequence. For example, a serial interface having a single-bit output stream can utilize the output circuitry described herein. Further, a parallel interface, which effectively includes has a plurality of single-bit output streams that are output in parallel with each other, can also utilize the output circuitry described herein. For example, each output stream can utilize the output circuitry described herein. Other variations could also be implemented, as desired.

FIG. 4is a block diagram of an embodiment400for circuitry that blocks return-to-zero signaling when multiple high logic level data signals are being output in sequence. For the embodiment400depicted, data storage circuitry401includes a next data register401and a current data register408. The next data register receives input data201and provides next data406to the current data register408based upon clock signal (CLK)202. The current data register408then outputs data206to return-to-zero (RTZ) circuitry208based upon the clock signal (CLK)202. The RTZ circuitry208then provides RTZ data210to block (BLK) circuitry412. The next data406and the current data206are also provided to return-to-zero (RTZ) block control circuitry414, along with clock signal (CLK)202. When the data206is at a low logic level, the RTZ block control circuitry414is configured to de-assert that RTZ block signal416. When the data206is at a high logic level, the RTZ block control circuitry414is configured to determine if the next data406is also at a high logic level. If so, the RTZ block control circuitry414asserts the RTZ block signal416to block (BLK) circuitry412. The block (BLK) circuitry412then operates to block the RTZ circuitry208from providing return-to-zero (RTZ) signaling until the RTZ block signal416is de-asserted. If the next data406is at a low logic level, then the RTZ block control circuitry414de-asserts the RTZ block signal416. When the RTZ block signal416is de-asserted, the block (BLK) circuitry412allows the RTZ circuitry208to provide return-to-zero signaling. Thus, the dynamically blocked return-to-zero (RTZ/BLK) data418output by the block (BLK) circuitry412is different from RTZ data210inFIG. 2(Prior Art) described above. It is noted that for embodiment400, the dynamically blocked return-to-zero (RTZ/BLK) output circuitry402includes the RTZ block control circuitry414, the return-to-zero circuitry208, and the block (BLK) circuitry412. It is further noted that the block (BLK) circuitry412could also receive the clock signal (CLK)202, if desired.

It is noted that return-to-zero signaling circuitry412can be implemented, for example, as logic circuitry that provides a data output that matches the data input upon each rising edge of a clock signal and that drives the data output to ground upon each a falling edge of a clock signal. The block (BLK) circuitry416can be implemented, for example, using multiplexer and logic circuitry that chooses data206as an output when the RTZ block signal416is asserted and chooses the RTZ data210when the RTZ block signal416is de-asserted. Further, the RTZ block control circuitry414can be implemented, for example, as logic circuitry that applies the RTZ block signal416according to the logic table provided in TABLE 1 below for the logic levels for the next data406and the current data206. It is noted that for this logic table, when either the next data406or the current data206is at a low logic level, the RTZ block signal416is de-asserted. Thus, in one implementation, the RTZ block control circuitry414can be configured to look at the next data406only if the current data206is a high logic level. In another implementation, the RTZ block control circuitry414could be configured to look at the current data206only if the next data206is a high logic level. Other implementations could also be utilized if desired.

FIG. 5is an embodiment500of timing diagram for dynamically blocked return-to-zero signaling associated with the example embodiment400ofFIG. 4. The y-axis represents logic levels for the clock signal (CLK)202, current data206, next data406, and RTZ/BLK data418. The x-axis represents time. Ten clock cycles are indicated from clock cycle T0 to clock cycle T9. Clock cycle T10 is started, but the complete cycle is not shown. The logic levels for the data206for the ten clock cycles (T0-T1-T2-T3-T4-T5-T6-T7-T8-T9) are 0-1-1-0-1-0-1-1-1-0, respectively. The logic levels for the next data406for these ten clock cycles leads the logic levels for the data206by one cycle and are 1-1-0-1-0-1-1-1-0-X, respectively. The “X” is used for cycle T9 because the logic level for data206in cycle T10 is not shown. High logic levels are indicated as a logic “1,” and low logic levels are indicated as a logic “0.” While the logic levels for data206are indicated for each clock cycle, the logic levels for the RTZ/BLK data418are indicated for each half-cycle. For the embodiment500, the clock cycle begins at each rising edge of the clock signal (CLK)202.

According to the dynamically blocked RTZ signaling described herein, each time the logic level for the data206is at a high logic level and the next data406is also at a high logic level, RTZ signaling is blocked by assertion of the RTZ block signal416. As such, RTZ/BLK data418will stay at a high logic level and not return to zero for the last half-cycle, as indicated by arrows502,504, and506. Each time the logic level for the data206is at a high logic level and the next data406is at a low logic level, RTZ signaling is allowed to occur by de-assertion of the RTZ block signal416. As such, the RTZ/BLK data418will return to zero (e.g., low logic level) for the last half-cycle on the falling edge of the clock signal (CLK)202, as indicated by arrows512and514. If the data206is at a low logic level, then the RTZ/BLK data418will also be at a low logic level. Thus, the logic levels for the RTZ/BLK data418for the ten clock cycles (T0-T1-T2-T3-T4-T5-T6-T7-T8-T9) are 00-11-10-00-10-00-11-11-10-00, respectively. The logic level for the RTZ/BLK data418, therefore, stays low for both half-cycles when the data206is at a low logic level. The logic level for the RTZ/BLK data418stays high for both half-cycles when the data206is at a high logic level and the next data406is also at a high logic level. The logic level for the RTZ/BLK data418is high for the first half-cycle and returns to zero for the second half-cycle when the data206is at a high logic level and the next data406is at a low logic level.

As indicated above, the dynamically blocked return-to-zero signaling described herein reduces capacitive coupling by reducing current flow generated by return-to-zero signaling when multiple high logic levels are being output in a sequence. In particular, because the RTZ/BLK data418remains at a high logic level until the next data406is at a low logic level, the RTZ/BLK data428is kept from moving to a low logic level and then back to a high logic level while the next data406stays at a high logic level. This blocking of return-to-zero signaling, therefore, reduces current flows, thereby reducing undesirable coupling between digital signal lines.

FIG. 6is an embodiment600of a process diagram for dynamically blocked return-to-zero signaling. In block602, data output is started. In determination block604, a determination is made whether the current data being output is at a high logic level. If the determination in block604is “NO,” then flow passes to block606where a low logic level is output for the data. Flow then passes to block614. If the determination in block604is “YES,” then flow passes to determination block608where a determination is made whether the next data to be output is at a high logic level. If the determination in block608is “NO,” then flow passes to block610where a high logic level is first output for the data and where the data output is then returned to a low logic level within the clock cycle to provide return-to-zero signaling. Flow then passes to block614. If the determination in block608is “YES,” then flow passes to block612where a high logic level is output for the data and where return-to-zero signaling is blocked so that the data output stays at a high logic level for the clock cycle. Thus, return-to-zero signaling is dynamically blocked when the current data and the next data are both at a high logic level. Flow then passes to block614. In block614, the clock cycle ends, and the next clock cycle begins. Flow then passes to determination block616where a determination is made whether there is more data to output. If “YES,” then flow passes back to determination block604. If “NO,” then flow passes to block618where data output is ended.

It is noted that the high logic levels and the low logic levels described herein, which are also indicated as logic “1s” and logic “0s,” represent sequences of data bits that are being output by the digital systems described herein based upon a clock signal having a plurality of clock cycles. It is further noted that the dynamically blocked return-to-zero signaling described herein can be applied to a variety of environments where clock signals and digital data signals are being generated in close proximity to each other within an integrated circuit and/or electronic system. As described above, the dynamically blocked return-to-zero signaling uses knowledge of current logic levels and next logic levels for digital data to determine whether or not to block return-to-zero signaling. Because current data and next data is utilized, the dynamically blocked return-to-zero signaling can be readily used in environments where multiple bits of data are stored and output using a clock signal.FIG. 7andFIG. 8provide example embodiments for such environments. However, it is noted that the dynamically blocked return-to-zero signaling described herein could be used in other environments, as well.

FIG. 7is a block diagram of an embodiment700for applying dynamically blocked return-to-zero signaling to circuitry that provides digital communication between different time domains. For the embodiment depicted, the dashed line712through FIFO (first-in-first-out) buffer710represents a time domain transition between first time domain driven by a first clock signal (CLK1)704and a second time domain driven by a second clock signal (CLK2)202. First domain circuitry702receives the first clock signal (CLK1)704and outputs input data201to FIFO buffer710based upon the first clock signal (CLK1)704. FIFO buffer710receives the input data201and the first clock signal (CLK1)704, and the FIFO buffer710outputs data206based upon the second clock signal (CLK2)202. The RTZ/BLK output circuitry402receives current data206and next data406from the FIFO buffer710and receives the second clock signal (CLK2)202. The RTZ/BLK output circuitry402then outputs RTZ/BLK data418based upon the second clock signal (CLK2)202, as described above with respect toFIG. 5. The second domain circuitry706then receives the RTZ/BLK data418and the second clock signal (CLK2)202.

FIG. 8is a block diagram of an embodiment800for applying dynamically blocked return-to-zero signal to circuitry that provides digital communication to a cache buffer. For the embodiment depicted, a cache buffer804receives input data201from system bus circuitry802. Cache buffer804also receives a clock signal (CLK)202and outputs data206based upon the clock signal (CLK)202to the RTZ/BLK output circuitry402. The RTZ/BLK output circuitry402receives the current data206and next data406from the cache buffer804and receives the clock signal (CLK)202. The RTZ/BLK output circuitry402then outputs RTZ/BLK data418based upon the clock signal (CLK)202, as described above with respect toFIG. 5. The cache memory806then receives the RTZ/BLK data418on its internal data bus for writing to the cache memory and the clock signal (CLK)202.

It is again noted thatFIGS. 7 and 8are providing example embodiments, and the dynamically blocked return-to-zero signaling could be used in other implementations, as desired.

As described herein, a variety of embodiments can be implemented and different features and variations can be implemented, as desired.

In one embodiment, a digital data output system is disclosed that includes data storage circuitry configured to store two or more data bits and to output the data bits in sequence based upon a clock signal and that includes output circuitry coupled to receive a current data bit and a next data bit from the data storage circuitry. The output circuitry is configured to output a low logic level for a clock cycle when the current data bit is a low logic level. The output circuitry is further configured to output a high logic level during a first portion of a clock cycle when the current data bit is a high logic level, to maintain the high logic level for the clock cycle if the next data bit is a high logic level, and to transition to a low logic level during the clock cycle if the next data bit is a low logic level.

In further embodiments, the output circuitry is configured to output the high logic level on a first clock edge for the clock cycle and to output the low logic level on a second clock edge for the clock cycle when the current data bit is a high logic level and the next data bit is a low logic level. Still further, the first clock edge can be a rising edge, and the second clock edge can be a falling edge. In other embodiments, the data storage circuitry includes a current data register configured to output the current data bit and a next data register configured to output the next data bit. Further, the output circuitry can be configured to output the high logic level for an entire clock cycle when the current data bit is a high logic level and the next data bit is a high logic level.

Still further, the output circuitry can include return-to-zero circuitry configured to receive current data bits and to output return-to-zero logic levels, and the output circuitry can further include block circuitry configured to selectively output a logic level associated with a current data bit or a return-to-zero logic level based upon a block control signal. In addition, the output circuitry can further include control circuitry configured to receive the current data bit and the next data bit, to assert the block control signal if the current data bit and the next data bit are both at a high logic level, and to de-assert the block control signal if the current data bit or the next data bit is at a low logic level.

In further embodiments, the data storage circuitry can include a buffer configured to receive the two or more data bits at a first clock rate and to output the data bits at a second clock rate, the second clock rate being associated with the clock signal. Further, the buffer can be a first-in-first-out buffer. In addition, the data storage circuitry can be a cache buffer configured to receive the two or more data bits from system bus circuitry and to output the data bits for a cache memory based upon the clock signal.

In one other embodiment, a method for outputting digital data is disclosed that includes storing two or more data bits to be output in sequence based upon a clock signal, and determining a logic level for a current data bit. Further, the method further includes outputting a low logic level for a clock cycle if the current data bit is a low logic level. And the method includes outputting a high logic level for a first portion of a clock cycle if the current data bit is a high logic level, maintaining the high logic level for the clock cycle if the next data bit is a high logic level, and transitioning to a low logic level during the clock cycle if the next data bit is a low logic level. Still further, the determining and outputting steps are repeated for a plurality of clock cycles until the two or more data bits are output.

In further embodiments, the method includes outputting a high logic level on a first clock edge for the clock cycle and a low logic level on a second clock edge for the clock cycle, when the current data bit is a high logic level and the next data bit is a low logic level. Still further, the first clock edge can be a rising edge, and the second clock edge can be a falling edge. In other embodiments, the storing step can include storing the current data bit in a current data register and storing the next data bit in a next data register. Further, the method can further include outputting the high logic level for an entire clock cycle, when the current data bit is a high logic level and the next data bit is a high logic level.

Still further, the outputting steps can include using return-to-zero circuitry to receive current data bits and to output return-to-zero logic levels, and selectively outputting a logic level associated with a current data bit or a return-to-zero logic level based upon a block control signal. In addition, the method can further include asserting the block control signal if the current data bit and the next data bit are both at a logic high level, and de-asserting the block control signal if the current data bit or the next data bit is at a low logic level.

In further embodiments, the storing step can include storing the two or more data bits in a buffer at a first clock rate that is different from a second clock rate associated with the clock signal. Further, the buffer can be a first-in-first-out buffer. In addition, the storing step can include storing the two or more data bits in a cache buffer, the data bits being received from system bus circuitry.

Further modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the described systems and methods are not limited by these example arrangements. It is to be understood that the forms of the systems and methods herein shown and described are to be taken as example embodiments. Various changes may be made in the implementations. Thus, although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and such modifications are intended to be included within the scope of the present invention. Further, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.