Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors

An electrostatic discharge (ESD) protection circuit includes a transistor with a gate electrode isolated from the semiconductor substrate by a thick oxide, a collector clamp coupled with a pad and the gate electrode, and an emitter clamp coupled between the gate electrode and the emitter of the transistor. Until the pad voltage reaches a trigger voltage, the collector clamp does not conduct, thereby preventing the transistor from conducting. However, when the pad voltage reaches the trigger voltage, the collector clamp turns on and triggers the latching of a parasitic thyristor that exists in the structure of the transistor. The latched parasitic thyristor (and thus the transistor) begins to conduct and rapidly dissipates the charge at the pad.

BACKGROUND

This disclosure relates to electrostatic discharge protection of integrated circuits and, in particular, to insulated gate bipolar transistors for electrostatic discharge protection of integrated circuits.

BACKGROUND

A problem in designing integrated circuits is dealing with electrostatic discharge (ESD). ESD is caused by static electricity built up by the human body and machines that handle integrated circuits. The static electricity is discharged onto the integrated circuit upon contact or close proximity with the integrated circuit. Static electricity follows any discharge path to alleviate the high electron build-up or deficiency. When an ESD sensitive device, such as an integrated circuit, becomes part of the discharge path, or is brought within the bounds of an electrostatic field, the sensitive integrated circuit can be permanently damaged.

ESD destruction of metal-oxide silicon field-effect transistor (MOSFET) devices occurs when the gate-to-source or gate-to-drain voltage is high enough to arc across the gate dielectric of a transistor device. The arc burns a microscopic hole in the gate oxide, which permanently destroys the MOSFET. Like any capacitor, the gate of a MOSFET must be supplied with a finite charge to reach a particular voltage. Larger MOSFETs have greater capacitance and are therefore less susceptible to ESD than are smaller MOSFETs. Also, immediate failure will not occur until the gate-to-source or gate-to-drain voltage exceeds the dielectric breakdown voltage by two to three times the rated maximum voltage of the gate oxide. The voltages required to induce ESD damage in some transistors can be as high as thousands of volts or as low as 50 volts, depending upon the oxide thickness.

Electrostatic fields can also destroy power MOSFETs by corona discharge. The failure mode is caused by ESD, but the effect is caused by placing the unprotected gate of the MOSFET in a corona discharge path. Corona discharge is caused by a positively or negatively charged surface discharging into small ionic molecules in the air.

When designing an integrated circuit a voltage rating is selected for the pad connecting a node in the circuit. The rating is the maximum voltage that the integrated circuit or pad is designed to withstand without causing damage. ESD protection circuits are generally designed to protect integrated circuits or pads from voltages above the rating for the integrated circuit or its housing.

Automotive applications, for example, demand robust protection (typically 8kV to 25kV in the human body model on a system level) against the threat of ESD or other transient pulses, such as load dump. General applications typically require a protection to a minimum of 2,000 volts. Unfortunately, many power MOSFET device designs are unable to meet this requirement.

Therefore, there exists a need to effectively protect circuits from the effects of ESD both cost effectively and efficiently.

SUMMARY OF THE DISCLOSURE

In accordance with the present invention, an electrostatic discharge (ESD) protection circuit that includes a transistor with a gate electrode isolated from the semiconductor substrate is disclosed. In some embodiments, the transistor-based ESD circuit improves the ability to withstand ESD events. In additional embodiments, pad designs that take advantage of the ESD circuits are disclosed.

In one embodiment, an electrostatic discharge protection circuit includes a transistor with a gate, an emitter and a collector. The gate of the transistor includes a gate electrode and an insulator material completely isolating the gate electrode from a semiconductor material of the transistor. The ESD protection circuit also includes a collector clamp coupled with a pad and the gate of the transistor, and a resistor coupled with the emitter and the gate of the transistor.

In another embodiment, a structure for electrostatic discharge protection of pads housing integrated circuits includes a pad and a transistor with a gate. The gate includes a gate electrode and an insulator material completely isolating the gate electrode from a semiconductor material of the transistor. The structure also includes a collector clamp coupled with the pad and the gate of the transistor, and a resistor coupled with the emitter and the gate of the transistor.

In a further embodiment, a transistor includes a substrate, a first well region within the substrate, a collector region within the first well region, a second well region within the substrate, a first emitter region within the second well region, a second emitter region within the second well region, a third well region within the substrate and between the first and second well regions, a gate electrode, and an insulator material completely separating the gate electrode from the third well region.

In the present disclosure, like objects that appear in more than one figure are provided with like reference numerals. Further, objects in the schematic diagram of and relationships in sizes between objects in the figures are not to scale.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring toFIG. 1, a circuit for electrostatic discharge protection is illustrated. As shown inFIG. 1, a pad15, along with any integrated circuits coupled to pad15, are protected by electrostatic discharge (ESD) protection circuit2. ESD protection circuit2includes an insulated gate bipolar transistor (IGBT)5that has a collector10coupled to pad15. IGBT5also has an emitter20that is coupled to a potential25that can be, for example, a ground potential, as shown. The ground potential can be a ground bus or a ground pad, as is known in the art. Gate30of IGBT5is coupled through a collector clamp35, which comprises one or more diodes, to pad15. An emitter clamp40, which also comprises diodes or resistors, is coupled between emitter20and gate30.

When the voltage at pad15is below the trigger voltage of collector clamp35, collector clamp35is in a blocking state. As long as collector clamp35is not triggered, i.e. does not conduct, emitter20and gate30are both at potential25, thus preventing IGBT5from conducting. At the onset of an ESD event, when a voltage greater than the trigger voltage of collector clamp35appears at pad15, collector clamp35will begin conduction. Conduction by collector clamp35causes a current to flow along path55through emitter clamp40.

Once a positive voltage that is greater than the threshold voltage of gate30with respect to emitter20appears, IGBT5will enter its forward conduction state, resulting in an increasing the collector to emitter voltage. As the collector to emitter voltage increases, it will reach a level at which the current through IGBT5latches a parasitic thyristor that exists in the structure of IGBT5. Latching of the parasitic thyristor causes a substantial decrease in the collector to emitter voltage. The substantial decrease in the collector to emitter voltage results in a dissipation of charge at the pad15, almost instantaneously. The parasitic thyristor structure of IGBT5will continue to conduct until all of the charge at the pad15is dissipated.

Collector clamp35and emitter clamp40can be, for example, zener diodes, diodes, or active clamps, e.g., gate shorted MOSFETs. Also, IGBT5has a gate electrode that is completely isolated from the semiconductor material of IGBT5by an insulator material. This is a thick gate oxide that allows emitter clamp40to be a resistor without the need for an additional emitter clamp in parallel to emitter clamp40. Therefore, a single conduction path between gate30and emitter20can be used, thus reducing components and surface area.

In some embodiments, ESD protection circuit2is fabricated upon pad15.FIG. 10illustrates embodiments of an ESD protection circuit formed on a pad.

Embodiments of ESD protection circuits and IGBTs capable of being used with the ESD circuits described herein are also depicted and described in copending U.S. patent application Ser. No. 10/336,129, entitled “Insulated Gate Bipolar Transistor And Electrostatic Discharge Cell Protection Utilizing Insulated Gate Bipolar Transistors,” which is assigned to the Assignee of the current application and is being filed on the same date herewith.

Referring toFIG. 2, a simplified diagram of an embodiment of lateral insulated gate bipolar transistor5is illustrated. InFIG. 2, n-well region80forms a junction with a p-well region82, which is isolated from gate electrode84by a field oxide86. P-well82further forms a junction with n-well88. A collector region90, which is a p+-type material, is formed in n-well88. A first emitter region92, which is a n+-type material, and a second emitter region94, which is a p+-type material, are formed in n-well80.

When a voltage is applied at gate electrode84of gate30that exceeds the threshold voltage of field oxide86of IGBT5, an inversion channel96is formed on the surface of p-well82and electrons flow from first emitter region92through inversion channel96into n-well88. The electrons provide base current for pnp-transistor98formed between second collector region90(transistor emitter), n-well88(transistor base) and p-well82(transistor collector). An isolation region (not shown) can be utilized to connect the second emitter region94and p-well82.

When collector region90has a voltage greater by about 0.7 volts than n-well88, collector region90gets forward biased and begins to inject holes into n-well88, which are collected by p-well82. The holes collected by p-well82forward bias the junction between p-well82and n-well80/first emitter region92, which causes parasitic thyristor100to latch up. Parasitic thyristor100is formed from collector region90, n-well88, p-well82, and n-well80/first emitter region92. At latch up, parasitic thyristor100will not respond to changes in the current or voltage at gate30of IGBT5. Current will flow through parasitic thyristor100until the charge at pad15is dissipated so that the voltage at the pad with respect to ground is below the trigger voltage for collector clamp35(FIG.1).

Triggering a parasitic thyristor in the structure of an IGBT to dissipate ESD induced voltages provides several advantages over MOSFET based ESD protection schemes. One advantage is improved power dissipation by ESD protection circuit2of FIG.1. The improved power dissipation also increases the useful life of ESD protection circuit2.

The IGBT sustaining voltage before the on-set of parasitic thyristor turn-on, reduces with increasing gate bias. That is, the higher the voltage at gate30ofFIG. 1with respect to emitter20, the larger the amount of holes that are collected by p-well82from collector region90through n-well88. The larger the amount of holes that are collected, the greater the forward bias the junction between first emitter region92and second emitter region94, which causes parasitic thyristor100to latch up.

Referring again toFIG. 1, when collector clamp35consists of diodes, the trigger voltage would be the sum of the reverse breakdown voltages of the one or more diodes that comprise collector clamp35. By changing the trigger voltage of collector clamp35, the voltage at which IGBT5begins conduction is altered, allowing a circuit designer to change the rating of pad15without having to redesign or change IGBT5. This results in a substantial cost saving and also in greater design flexibility, since IGBT5can be used regardless of the rating of the pad. In some embodiments, the breakdown voltage is altered by changing the number of diodes that make up collector clamp35, without having to resize the diodes or other circuit components.

Referring toFIG. 3, another circuit for electrostatic discharge protection is illustrated. InFIG. 3, another IGBT60is added to ESD protection circuit2. An emitter65of IGBT60is coupled to emitter20of IGBT5. The gate70of IGBT60is coupled to its emitter65through emitter clamp45. Collector80of IGBT60is coupled to pad81. Another collector clamp75couples gate70of IGBT60to pad81. IGBT5is coupled essentially the same way as illustrated in FIG.1.

The circuit inFIG. 3is especially advantageous in handling bi-directional ESD events, where a voltage at pad81is greater than a potential at pad15, or vice versa. This is because IGBT5responds to positive ESD events, while IGBT60responds to negative ESD events. Further, both collector clamps35and75can be optimized, either together or separately, to allow flexibility in the ESD rating of pad15and pad81.

It should be noted that the ESD protection circuits ofFIGS. 1 and 3can be integrated circuits for ease of use and manufacture onto pad15.

The circuits described inFIGS. 1 and 3can be utilized regardless of the desired voltage rating of pad15without changing IGBT5or IGBT60. IGBT5can, for example, withstand 5,000 volts during an ESD event, or any other amount. However, the circuit can operate for a pad15rated to almost any value, simply by changing the trigger voltage of collector clamp35or collector clamp75to the desired rating. In the case where either collector clamp35or collector clamp75comprises diodes, the trigger voltage can be changed by adding or removing diodes that constitute collector clamp35or collector clamp75. This greatly increases the utility and cost effectiveness of the ESD protection circuits illustrated inFIGS. 1 and 3over conventional ESD protection designs.

Referring toFIG. 4, a cross-sectional view of a lateral insulated gate bipolar transistor for electrostatic discharge protection is illustrated. InFIG. 4, IGBT5comprises a p-type substrate200. An epitaxial region205, which is n-type, is grown over substrate200. An isolation region210, which is an up-diffused p-type region, is also formed in substrate200. An n-well215is formed within substrate200. A first emitter region220, which may be p+-type, and a second emitter region225, which may be n+-type, are formed within n-well215. A collector region230, which may be p+-type, is formed in a n-well235that is formed in substrate200. A p-well240is formed in substrate200above which an insulator material245is formed. In some embodiments, insulator material245is a field oxide having a depth of approximately 0.7 to 1 micron.

A gate electrode250, which in one embodiment is comprised of a polycrystalline silicon material, is completely isolated from all of the layers diffused and formed in substrate200by insulator material245. An emitter electrode255is in common contact with both first emitter region220and second emitter region225. A collector electrode260is in contact with collector region230. An insulation film265formed of a chemically vapor deposited film, such as a boron phosphorus silicate glass (BPSG) or other insulation, is disposed over IGBT5for planarization and insulation of the surface.

Operation of IGBT5ofFIG. 4will now be described. Once a voltage, higher than the threshold voltage and positive with respect to a potential of emitter electrode255, is applied to gate electrode250, an inversion layer270is created. The inversion layer270is formed on the surface of p-well240between second emitter region225and n-well235. Electrons then flow from second emitter region225through p-well240into n-well235through inversion layer270. The electron flow into n-well235functions as a base current of a pnp-transistor275formed from of collector region230(transistor emitter), n-well235(transistor base), and p-well240(transistor collector).

Once collector region230reaches a voltage greater than about 0.7 volts above that of n-well235, collector region230begins to inject holes into n-well235that are collected by p-well240, which cause conduction by pnp-transistor275. The difference of about 0.7 volts for beginning hole injection can be altered by changing the doping of collector region230and n-well235.

Parasitic thyristor280latches up when the holes collected in p-well240forward bias p-well240with respect to n-well215. Parasitic thyristor280then will conduct all of the current flowing through IGBT5. Parasitic thyristor280consists of second emitter region225/n-well region215(thyristor cathode), p-well240(npn-transistor base), n-well235(pnp-transistor base), and collector region230(thyristor anode). Further, parasitic thyristor280will not cease conduction until all of the charge at collector electrode260is dissipated. The latching of parasitic thyristor280varies based upon the resistance of isolation region210, which is a function of the volume of the isolation region multiplied by it resistivity. Therefore, by changing the dimensions of isolation region210the latching of parasitic thyristor280can be altered.

Triggering parasitic thyristor280in an IGBT runs counter to the accepted and desired use of IGBTs. This is because, as described above, parasitic thyristor280will not cease conduction until the charge at collector electrode260is dissipated. The result is that, once parasitic thyristor280is latched up, the IGBT cannot be controlled by its bias circuitry and cannot operate in its linear amplification or switching region.

It should be noted that isolation region210is used to reduce the surface electric fields (RESURF) between n-well235and p-well240. Further, by varying the depth of isolation region210, the collector to emitter breakdown voltage, which is the forward blocking voltage of IGBT5of the IGBT, can be varied.

Referring toFIG. 5, a graph of the current-voltage characteristics of a collector of the lateral insulated gate bipolar transistor illustrated inFIG. 4is illustrated. InFIG. 5, as collector to emitter voltage300increases, it will snap-back at310when parasitic thyristor280latches up. Also, as the voltage at gate30is increased the latch-up voltage of the parasitic thyristor280decreases, as shown by gate voltage levels315,320,325, and330.

Additionally,FIG. 5illustrates the advantage of the use of an IGBT for ESD protection by showing operation of parasitic thyristor280. Specifically, parasitic thyristor280latches up at a voltage that is a sum of the clamp trigger voltage335and the voltage on the gate required to forward bias the junction between n-well215and p-well240. This can be altered by changing the resistance of isolation region210, and the thickness of insulator material245for a lower gate voltage. Upon latching up, the parasitic thyristor280begins conducting thereby reducing the charge at pad15until the charge at pad15is dissipated. The operation of parasitic thyristor280is shown by curve340.

The collector to emitter breakdown voltage345is the voltage at which IGBT5is not able to function in a forward blocking state. In ESD protection circuit2, the breakdown voltage of collector clamp35must be set to a voltage less than the difference between collector to emitter breakdown voltage345and the gate voltage of IGBT5required to trigger parasitic thyristor280.

Referring toFIG. 6, a cross-sectional view of another embodiment of a lateral insulated gate bipolar transistor for electrostatic discharge protection is illustrated. InFIG. 6, a second collector region400, which may be n+-type, is added, forming a junction with the collector region230. The second collector region400acts as a short between collector electrode260and n-well235during conduction by IGBT5. Thus a diode430is created between substrate200and n-well235.

Referring toFIG. 7, a cross-sectional view of another embodiment of a lateral insulated gate bipolar transistor for electrostatic discharge protection is illustrated. In the embodiment shown inFIG. 7, a contact420is then added to collector electrode260. The contact420, which is a Schottky contact, acts as a short between collector electrode260and n-well235. The short between collector electrode260and n-well235improves negative ESD event dissipation and allows for conduction by IGBT5at a lower voltage. Further, metal contact420improves the homogenous turn on of parasitic thyristor280.

Alternatively, collector electrode260can itself be completely or partially formed of a metallic material to form either an ohmic or a schottky contact to collector region230.

An advantage of the lateral IGBTs inFIGS. 6 and 7over that ofFIG. 4is the reaction of the IGBT to negative ESD events, where the charge at the pad is negative with respect to potential25. Substrate200and n-well235form a diode430between substrate200and collector electrode260. Diode430is formed due to the short between n-well235and collector electrode260. Diode430conducts current induced by negative ESD events from pad15to substrate200. Diode430allows IGBT5to dissipate voltages induced by negative ESD events. The use of the structures ofFIGS. 6 and 7improves the response to negative ESD events versus that of FIG.4.

FIG. 8is a graph of the current-voltage characteristics of a collector of a lateral insulated gate bipolar transistor as illustrated inFIGS. 6 and 7. As the collector to emitter voltage500increases, it will snap-back at510as parasitic thyristor280latches-up as described with respect to FIG.5. Also, as the voltage on gate30is increased, the latch-up voltage of the parasitic thyristor decreases, as shown by gate voltage levels515,520and530, as described with respect to FIG.5.

A feature of the IGBT structures ofFIGS. 6 and 7is collector conduction prior to the turn on of pnp-transistor275, as shown by early current flows535.

Although exemplary doping characteristics are discussed with respect toFIGS. 4,6and7, other doping characteristics, including those that result in complimentary structures to those disclosed, are possible and can be used in the circuits ofFIGS. 1 and 3.

Further, additional variations may be made to IGBT structures discussed with respect toFIGS. 4,6, and7. For example, a p-well or p-body region, or their complementary doping in a complementary IGBT, that is self-aligned on the emitter side with gate electrode250may be included.

Referring toFIG. 9, a cross-sectional view of a lateral insulated gate bipolar transistor with leakage current reduction is illustrated. The IGBTs shown inFIGS. 4,6, and7each have a small leakage current on the surface of pnp-transistor275due to punch through or surface charges. This leakage current, which is inherent to the structure of an IGBT, can cause erroneous latching of parasitic thyristor280due to the leakage current that occurs prior to triggering of collector clamp35. Inserting a punch through reduction region650that forms a butting junction with collector region230on the side of insulator material245can substantially reduce or eliminate the leakage current. This punch through reduction region650should be of a complementary doping to collector region230, which for example would be an n-type punch through reduction region for a p+-type collector region. The punch through reduction region650can be relatively small in width. In one embodiment the width is no more than two (2) microns. The use of a punch through reduction region650reduces inaccurate and premature latching of parasitic thyristor280.

Alternatively, to reduce the leakage current, a buffer region651can be added to the n-well235, as shown inFIG. 9a. The buffer region651can be formed by heavily doping the portion of the n-well235enclosing the collector region230.

Referring toFIG. 10, a pad15with an electrostatic discharge protection circuit fabricated upon it is illustrated. Pad15has a trace700that forms a resistor coupled between gate250and emitter220as described in the above-mentioned application Ser. No. 10/336,129, and diffusions705that form collector clamp35, which is made up of a number of diodes. Diffusions705have a number of contacts710to pad15.

Gate electrode250, which has rounded corners as depicted, overlies insulator material245, which has a similar shape to gate electrode250. A number of contacts720provide bonding to pad15. Field oxide245is below gate electrode250.

Collector region230is diffused along a periphery of pad15and also has a number or contacts720. Emitter regions220and225surround insulator material245in a similar oval configuration, and are grounded via ground pad GND.

By fabricating IGBT5on a pad, the ruggedness of IGBT5is increased due to the charge distribution on the device. Further, the response time of IGBT5improves by fabricating it on pad15, thereby reducing the potential for damage to integrated circuits bonded to pad15. In another embodiment IGBT5is fabricated on at least two sides of one of the surfaces of pad15.

WhileFIG. 10depicts IGBT5in a substantially oval configuration, other configurations of IGBT can be used. For example, racetrack or configurations having multiple fingers can be used. Further, IGBT5can be fabricated on two or three sides of a surface of pad15.

It should be noted that while IGBT5is illustrated as a lateral IGBT inFIGS. 4,6, and7, a vertical IGBT can also be utilized based upon the principles and utilizing the same region constituents as described herein. Further, it would be advantageous to use a vertical IGBT in an integrated ESD protection circuit.

It should be noted that whileFIGS. 1-10illustrate an IGBT, a metal oxide semiconductor field effect transistor (MOSFET) can be utilized in place of an IGBT. In such instances the structure would be altered, for example, by removing first emitter region220.

The detailed description provided above is merely illustrative, and is not intended to be limiting. While embodiments, applications and advantages of the present inventions have been depicted and described, there are many more embodiments, applications and advantages possible without deviating from the spirit of the inventive concepts described and depicted herein. The invention should only be restricted in accordance with the spirit of the claims appended hereto and is not restricted by the embodiments, specification or drawings.