Tunable antifuse element and method of manufacture

A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

TECHNICAL FIELD OF THE INVENTION

The present invention generally relates to semiconductor integrated circuit technology, and more particularly to tunable antifuse element structures, and a method of manufacturing tunable antifuse elements, in semiconductor devices.

BACKGROUND OF THE INVENTION

One-time programmable non-volatile memories (OTP) have been widely used in read only memory (ROM) integrated circuits for circuit trimming and can be realized using a circuit containing fuse or antifuse element structures. When a fuse element is utilized, the device is programmed by blowing fusible links at selected nodes to create an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data that a user wishes to store in OTP. A high power is normally required (e.g. ˜50 mA for a poly fuse link in a 0.25 um CMOS flow) to blow the link. In addition, a large area with supporting circuits is required as well as a large separation from adjacent circuits, including other fuse elements. If the resultant damage to the fuse is not extensive enough, the disconnected blown links may become reconnected during long-term operation of the links, resulting in a circuit malfunction and reliability issues.

When an antifuse element is utilized, the programming mechanism is opposite the process of causing an open circuit in the fuse structure to be formed. Instead, the antifuse element programming mechanism creates a short circuit or a low resistance path. The antifuse element can include an insulating dielectric layer, such as a gate oxide, between two conducting layers. The unprogrammed state of an antifuse element is an open circuit with intact dielectric. The programmed state is a shorting path at a damaged point or region, known as the rupture point or region, in the dielectric layer, such as a gate oxide, formed by applying a voltage higher than the dielectric rupture voltage. It is known that, as the insulating dielectric layer in complementary metal oxide semiconductor (CMOS) flows becomes thinner (below 50 Å), many NMOS or PMOS types of structures are useful as antifuses, because the gate oxide rupture voltage/current becomes lower with thinner oxides resulting in a smaller trim circuit. Furthermore, spontaneous healing of a ruptured the insulating dielectric layer is very unlikely, resulting in improved device reliability if power is constrained.

In general, previous antifuse elements are characterized by: (1) a program voltage higher than a low voltage CMOS transistor operation voltage; (2) long programming time (the charge-to-breakdown (QBD) is a function of gate oxide thickness, area and defects); and (3) large post program resistance and variation due to random rupture locations in the gate oxide.

Accordingly, it would be desirable to provide an antifuse element, a method of forming an antifuse element, in which the rupture location is controlled and the local rupture electric fields are enhanced. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

In accordance with the present invention, there is provided a tunable antifuse element including a tunable dielectric layer whereby a rupture voltage is tunable, a method of forming the tunable antifuse element, and incorporation of the tunable antifuse element in a bit cell array. The rupture voltage can be controlled (or tuned) through the manipulation of stepped transition regions between areas of different dielectric layer thickness. The formation process of the different dielectric layers, the geometries of the areas of different thicknesses and the physical properties of the substrate on which it is formed can all be used to modify the properties of these transition regions. The figures included herein illustrate a tunable antifuse element built on a CMOS capacitor, however, it should be understood that the tunable antifuse element of the present invention can be built on an NMOS transistor, a PMOS transistor, or MOS capacitor.

FIGS. 1-2illustrate a top and a cross sectional view taken along line2-2ofFIG. 1, of an embodiment of a tunable antifuse element according to the present invention. A semiconductor device100, more particularly a tunable antifuse element102, is formed as a unique gate capacitor comprising a gate material and an active area formed in a substrate material101, shown inFIG. 2. Tunable antifuse element102may optionally be bounded by shallow trench isolation (STI) (not shown) when isolation of antifuse element102is required.

Substrate material101may be a standard semiconductor substrate such as bulk or epitaxial silicon wafer. Tunable antifuse element102is comprised of a top gate electrode104and an active area106, that serves as a bottom electrode. The surface of active area106may include a heavily doped diffusion contact or a well contact114in the form of n-type or p-type implants to provide for good electrical contact.

Gate electrode104may be formed of polysilicon and serves as a top electrode for tunable antifuse element102. For maximum density, gate electrode104can have a minimum width, usually submicron, and is formed proximate active area106. In this preferred embodiment, gate electrode104is formed of a p-doped polysilicon material as is well known in the art and includes a contact108formed on an upper surface111thereof. A dielectric layer, also known as a gate oxide110, as shown inFIG. 2, is formed between gate electrode104and active area106. In a preferred embodiment, gate oxide110is a dielectric material, such as any material suitable for a dielectric or insulating layer. Gate electrode104is formed over gate oxide110. As illustrated in this particular embodiment, antifuse element102is formed on an uppermost surface of substrate101. Anticipated by this disclosure is the fabrication of antifuse element102on a sidewall of substrate101such as when fabricating a dual gate metal oxide field effect transistor (MOSFET) wherein the channel and gate oxide are formed on a sidewall of a silicon mesa. Accordingly, this disclosure is not limited to fabrication of the tunable antifuse element on an uppermost surface of a substrate, but includes fabrication on any surface of a silicon substrate.

FIG. 2illustrates tunable antifuse element102including a doped pwell112, also shown inFIG. 1, formed in a surface of substrate material101, to have the same doping type as p-doped gate electrode104. In an alternative, tunable antifuse element102may include a doped nwell112, when gate electrode104is n-doped. A diffusion contact or well contact114, in conjunction with an associated terminal115, serves as a contact to pwell112and can be formed proximate a rupture region (discussed below) of overlying gate oxide110. In addition, well contact114may act as a combination well contact and minority carrier injector. Anticipated by this disclosure is any combination of gate and well doping, including but not limited to a device including a doped pwell and p-doped gate electrode, or a doped pwell and n-doped gate electrode, or a doped nwell and p-doped gate electrode.

Referring again toFIG. 1, in one embodiment, device100is a CMOS capacitor that functions as an antifuse by becoming conductive after undergoing programming. Prior to any programming event, wherein a voltage is applied between contacts108and114, via a terminal109and terminal115respectively, the path between gate contact108and diffusion or well contact114is an open circuit. Generally, the programming voltage is a voltage that is equal to or above the rupture voltage that causes tunable antifuse element102to change from an open state to a closed state, by causing a rupture (i.e. a breakdown of gate oxide110between gate electrode104and active area106). During programming of tunable antifuse element102, a programming voltage is applied between gate electrode104and the active area, or bottom electrode,106. The programming event creates a vertical current path between gate electrode104and active area106, the bottom electrode. Rupture, or breakdown, of gate oxide110, formed there between, will occur at a rupture region130where the electric field is the highest. During programming, the highest electric fields will occur at a stepped portion (discussed below) of gate oxide110below gate electrode104that overlies or is positioned proximate active region106.

During the fabrication of tunable antifuse element102, a dual gate oxide (DGO) mask, illustrated by dashed line120inFIG. 1and described in detail below, allows for the fabrication of tunable gate oxide110. The term “dual gate oxide” is defined as gate oxide or dielectric having two or more thicknesses. In this particular embodiment, during fabrication, DGO mask layer120covers a left portion of semiconductor device100. Referring now toFIG. 3, as a result of the DGO process (described below), gate oxide110is described as including a stepped structure127, comprised of a thin oxide portion122having a thickness (T1) and a thick oxide portion124having a thickness (T2), formed under gate electrode104, wherein T1is less than T2. Gate oxide110will be stepped along an edge of DGO mask120that overlies gate oxide110. During antifuse programming, the highest electric field is generated along stepped structure127. The localization of the electric field promotes the gate rupture process at rupture point or region130using a low program voltage, energy, and time.

FIGS. 4-5are a top view and a cross sectional view taken along line5-5ofFIG. 4of another embodiment of a tunable antifuse element according to the present invention. A semiconductor device200, more particularly a plurality of tunable antifuse elements202and204, are formed as unique gate capacitors comprising gate materials and an active area106formed in a substrate material101. Antifuse elements202and204may optionally be bounded by shallow trench isolation (STI) (not shown). Antifuse elements202and204are formed similar to tunable antifuse element100ofFIGS. 1-3having like numerals to indicate like elements. Not all elements inFIGS. 4-5that are similar to elements inFIGS. 1-3will be described.

In this particular embodiment, device200includes two antifuse elements202and204formed side-by-side on a single substrate101. Tunable antifuse elements202and204share active area106and contact well114. During programming, the highest electric fields will occur in a stepped portion of gate oxide110(described below) of each element202and204below gate electrodes104.

Similar to the embodiment described with regard toFIGS. 1-3, during the fabrication of tunable antifuse elements202and204, a dual gate oxide (DGO) mask layer, illustrated by dashed line120inFIG. 4, covers a portion of antifuse elements202and204. Tunable gate oxides110are formed of dual dielectric thicknesses, and described as each including a stepped structure127comprised of a thin oxide portion122and a thick oxide portion124. Tunable gate oxide110will have a stepped structure along an edge of the DGO mask that overlies gate oxide110during fabrication. During antifuse programming, the highest electric field is generated at rupture points or regions130of each tunable antifuse element202and204. The localization of the electric field promotes the gate oxide rupture process at rupture points or regions130using a low program voltage, energy, and time.

FIGS. 6-11are examples of top schematic diagrams of a plurality of gate oxide geometries in accordance with a tunable antifuse element of the present invention. The shape and dimensions of tunable gate oxide110are chosen to produce a specific breakdown voltage with the given oxide thicknesses and etch profiles. It should be understood that inFIGS. 6-11, the specific thick and thin portions can be interchangeable to form additional gate oxide geometries. Gate oxide110is formed using DGO mask120and is described as tunable dependent upon the geometry of gate oxide110and the comparative thickness of the oxide layers that form the geometries.FIG. 6illustrates the most typical geometry for a tunable gate oxide according to the present invention. More specifically,FIG. 6illustrates a gate oxide310, generally similar to gate oxide110ofFIGS. 1-3, including a stepped structure327comprised of a thick oxide portion324and a thin oxide portion322. A transition area328is formed where thick oxide portion324and thin oxide portion322intersect. Gate oxide310has a rupture region located along transition area328where the electric field is most enhanced.

FIG. 7illustrates another geometry for a tunable gate oxide according to the present invention. More specifically,FIG. 7illustrates a gate oxide410, generally similar to gate oxide110ofFIGS. 1-3, including a stepped structure comprised of a plurality of thick oxide portions424, having a thin oxide portion422sandwiched between. Dual transition areas428are formed where thick oxide portions424intersect with thin oxide portion422. Gate oxide410has a rupture region located along transition areas428where the electric field is most enhanced.

FIG. 8illustrates another geometry for a tunable gate oxide according to the present invention. More specifically,FIG. 8illustrates a gate oxide510, generally similar to gate oxide110ofFIGS. 1-3, including a stepped structure comprised of a thick oxide portion524, having a thin oxide portion522formed to surround thick oxide portion524on at least two sides. A transition area528is formed where thick oxide portion524and thin oxide portion522intersect. Gate oxide510has a rupture region located along transition area528where the electric field is most enhanced.

FIG. 9illustrates another geometry for a tunable gate oxide according to the present invention. More specifically,FIG. 9illustrates a gate oxide610, generally similar to gate oxide110ofFIGS. 1-3, including a stepped structure comprised of a thick oxide portion624and a thin oxide portion622. A plurality of transition areas628are formed where oxide portion624and thin oxide portion622intersect. Gate oxide610has a rupture region located along transition areas628where the electric field is most enhanced.

FIG. 10illustrates another geometry for a tunable gate oxide according to the present invention. More specifically,FIG. 10illustrates a gate oxide710, generally similar to gate oxide110ofFIGS. 1-3, including a stepped structure comprised of a thick oxide portion724and a thin oxide portion722. This particular geometry of gate oxide710has thick oxide portion724completely surrounded by a thinner gate oxide, more particularly thin oxide portion722. A transition area728is formed where thick oxide portion724and thin oxide portion722intersect. Gate oxide710has a rupture region located along transition area728where the electric field is most enhanced.

FIG. 11illustrates another geometry for a tunable gate oxide according to the present invention. More specifically,FIG. 11illustrates a gate oxide810, generally similar to gate oxide110ofFIGS. 1-3, including a stepped structure comprised of a thick oxide portion824and a thin oxide portion822. This particular geometry of gate oxide810has thick oxide portion824completely surrounded by a thinner gate oxide, more particularly thin oxide portion822in a similar manner as gate geometry710shown inFIG. 10. In this particular geometry, thick oxide portion824is formed having a cross shape to promote formation of rupture points or a rupture region. A transition area828is formed where thick oxide portion824and thin oxide portion822intersect. Gate oxide810has a rupture region located along transition area824where the electric field is most enhanced.

FIGS. 12-19are cross-sectional schematic diagrams of a method of fabricating a tunable antifuse element according to the present invention. More specifically,FIGS. 12-19illustrate a method of fabricating a tunable antifuse element including a tunable gate oxide having a geometry as described inFIG. 10. It should be understood that the method described and illustrated inFIGS. 12-19could also be used to fabricate a tunable antifuse element similar to the tunable antifuse elements described with respect toFIGS. 1-5, or having any gate oxide geometry such as those described inFIGS. 6-9and11. In general, the tunable antifuse element of the present invention uses conventional DGO processes to create a tunable gate oxide comprised of a plurality of dielectric thicknesses and varying geometries.

FIGS. 12-19illustrate the fabrication steps of a tunable antifuse element904. The process steps are offered by way of example as one method for reduction to practice of conceived embodiments. Other methods are anticipated as would be obvious to one skilled in the art, and the scope of this description is not intended to be limited to this general process description. A substrate101is provided having a pwell112formed therein. Substrate material101may be a standard semiconductor substrate such-as bulk or epitaxial silicon substrate and is intended to encompass the relatively pure silicon materials typically used in the semiconductor industry, silicon-on-insulator, as well as silicon compound semiconductors, such as silicon germanium and the like. Metals and other conductive materials may be considered when forming metal-insulator-metal (MIM) capacitor. In addition, other suitable substrates, such as substrates including III-V materials and II-VI materials may also be considered in specific instances depending on device requirements. Pwell112is formed by ion implantation of boron or other means to a concentration of between ˜1×1014/cm3and ˜5×1017/cm3. If required, shallow trench isolation (STI)103is next formed by conventional etch and refill methods. STI103provides separation between tunable antifuse element904and any devices proximate antifuse element904.

Referring now toFIG. 13, subsequent to the formation of STIs103and Pwells112, a thick insulating layer906is formed over the entire substrate101. Thick insulating layer906is typically formed of silicon nitride, silicon oxide, a high K dielectric, or other similar insulating material. Thick insulating layer906is next patterned using a mask layer908as illustrated inFIG. 14, such as a DGO mask, such that a portion of thick insulating layer906formed on an active area of tunable antifuse element904, similar to active area106of tunable antifuse element102(FIG. 10) is etched way. Next, mask layer908is removed.

FIG. 15illustrates the possible subtraction of a portion909of substrate101due to over-etch when substrate101undergoes undesirable silicon loss due to the etch step to remove thick insulating layer906.FIG. 16illustrates a thin oxide layer910that is next grown over the active area of tunable antifuse element904. Layer of thin oxide910that is grown directly on substrate101in portions909will grow at a faster speed than layer of thin oxide910that is grown in an active area of tunable antifuse element904where growth is over thick oxide layer906. However, the resulting layers910formed in portions909will remain thinner than the combination layer grown in areas covered by thick oxide layer906. Growth of thin oxide layer910may be accomplished by using standard deposition techniques in which thin oxide layer910will grow on a surface of thick oxide layer906, or by using thermal oxidation techniques in which thin oxide layer910actually grows underneath layer906as illustrated inFIG. 16. The resultant dual oxide layers in active area106of tunable antifuse element904serve as a stepped tunable gate oxide comprising a geometry similar to that described inFIG. 10. More specifically, a single thin oxide layer910surrounds a central portion911, comprised of thick oxide layer906formed on top of thin oxide layer910. Gate oxide110has a stepped structure912defined by thin oxide layer910and thick oxide layer906as shown inFIG. 16.

To complete the fabrication of tunable antifuse element904, a layer of polysilicon914is deposited on the surface of the device as illustrated inFIG. 17. A mask layer918is next deposited providing for subsequent patterning and etching of polysilicon layer914and fabrication of gate916as illustrated inFIGS. 18 and 19. The formation of well contacts920by implantation follows, as illustrated inFIG. 19.

As stated previously tunable antifuse element904is fabricated in generally the same manner as a conventional antifuse element, except that additional photolithography and etch steps are performed during fabrication of tunable antifuse element904to provide for varying gate oxide thicknesses and geometries. The additional mask and wet etch step are actually part of standard CMOS process flow. Accordingly, the method described is most compatible with extant CMOS flows but other methods, such as an etchback, can also be used. In addition, one could design the structure to expose surfaces of two different crystallographic orientations and using the resulting natural differential rates of oxidation to make oxides of different thicknesses when grown thermally.

FIG. 20illustrates an antifuse array950, including a plurality of antifuse elements952, formed generally similar to tunable antifuse element102ofFIGS. 1-3. Antifuse elements952are capacitors and may optionally be combined with a series select transistor954to form a plurality of bit cells956. Antifuse array950is comprised of plurality of tunable antifuse elements952and a plurality of series select transistors954that in combination form plurality of bit cells956. In the embodiment illustrated inFIG. 20, a sector958, indicated by the dashed line, is being programmed. Once bit cells956are arranged to form array950, the use of low PROGRAM and READ biases allows low voltage (LV) and dual gate oxide (DGO) transistors to be used as select transistors954, and provide increased array density. Antifuse elements952have a dielectric breakdown that is below that of logic and DGO transistors. This low breakdown voltage allows for a high-density array and produces low cost per bit. Array950can be programmed one row at a time without PROGRAM DISTURB in unselected rows. During programming, only one row and certain select transistor954gates are at non-zero biases. The bits to be programmed experience a bias close to the programming voltage (Vp). Select gates protect the bits that are not being programmed in the selected rows.

FIG. 21illustrates reading of antifuse array950without READ DISTURB in unselected rows. In the embodiment illustrated, sector958, indicated by the dashed line, is being read. In addition, READ bias polarity in antifuse elements952can be opposite to the PROGRAM bias polarity. Shorted bits connect their wordlines960and source lines962, resulting in current flow on their word lines960. Unprogrammed bit cells956do not experience significant conduction at these lower biases. The architecture of array950and operation allows reliability to be maintained over many READ cycles and allows for reverse polarity programming and readings, adding a degree of freedom to further optimize reliability. The creation of a larger bit-count antifuse array in a cost-effective manner, allows for applications such as: (i) security applications; (ii) IC customization by customer; (iii) IC customization by manufacturer; (iv) IC identification and tracking; (v) “black-box” writes; (vi) more extensive and distributed trim; (vii) storage of very small programs; and (viii) field programmability.

Accordingly, provided is a tunable antifuse element comprising: a substrate material; an active area formed in a surface of the substrate material; a gate electrode having at least a portion positioned above the active area; and a tunable dielectric layer including a stepped structure, the tunable dielectric layer disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the tunable dielectric layer and a rupture of the tunable dielectric layer in a rupture region. In one embodiment, the tunable antifuse element is a capacitor. In one embodiment, the substrate material is a semiconductor material. The active area comprises an electrically conductive doped region. The tunable dielectric layer is a tunable gate oxide layer. In one embodiment, the tunable gate oxide layer is comprised of at least one thin oxide portion having a thickness T1and at least one thick oxide portion having a thickness T2, wherein T1is less than T2, the stepped structure defined by a thickness variation between the thin oxide portion and the thick oxide portion. The stepped structure includes a plurality of thick oxide portions and at least one thin oxide portion. The stepped structure includes a plurality of thin oxide portions and at least one thick oxide portion. The rupture region is located at a transition region between the at least one thick oxide portion and the at least one thin oxide portion.

In addition, provided is a method of fabricating a tunable antifuse element, the method comprising: providing a substrate material; forming an active area in a surface of the substrate material; forming a gate electrode having at least a portion positioned above the active area; and forming a tunable dielectric layer including a stepped structure, the tunable dielectric layer disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the tunable dielectric layer and a rupture of the tunable dielectric layer at a rupture region. The step of forming a tunable dielectric layer includes forming at least one thick oxide portion having a thickness T2and at least one thin oxide portion having a thickness T1, wherein T1is less than T2. The at least one thick oxide portion and the at least one thin oxide portion of the tunable gate oxide layer are formed using a dual gate oxide mask. The step of forming a tunable dielectric layer includes forming a first insulating layer over the substrate material, etching away a portion of the first insulating layer to expose a portion of the substrate material, and forming a second insulating layer, wherein a portion of the second insulating layer is formed as one of over or under the first insulating layer and a portion is formed over the exposed portion of the substrate material, thereby defining the stepped gate oxide structure.

Finally, provided is a tunable antifuse array comprising: a plurality of bit cells, each of the plurality of bit cells comprising at least one tunable antifuse element, wherein each of the at least one tunable antifuse elements is comprised of: a substrate material; an active area formed in a surface of the substrate material; a gate electrode having at least a portion positioned above the active area; and a tunable dielectric layer including a stepped structure, the tunable dielectric layer disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the tunable dielectric layer and a rupture of the tunable dielectric layer in a rupture region. In one embodiment, the tunable antifuse array further includes at least one select transistor. In one embodiment, the at least one tunable antifuse element is a capacitor. In one embodiment, the tunable dielectric layer is comprised of at least one thin oxide portion having a thickness T1and at least one thick oxide portion having a thickness T2, wherein T1is less than T2,a stepped structure defined by a thickness variation between the thin oxide portion and the thick oxide portion. In one embodiment, the stepped structure includes a plurality of thick oxide portions and at least one thin oxide portion. In one embodiment, the stepped structure includes a plurality of thin oxide portions and at least one thick oxide portion. The rupture region is located at a transition region between the at least one thick oxide portion and the at least one thin oxide portion.