SINGLE MEMORY BANK STORAGE FOR SERVICING MEMORY ACCESS COMMANDS

A method is described, which includes receiving a memory access command that requests access to data in a memory device and determining a location in the memory device for the memory access command. The location for the memory access command indicates a set of managed units in a row of a memory bank of the memory device. The memory access command is fulfilled using the data at the location as a complete response to the memory access command.

TECHNICAL FIELD

The present disclosure generally relates to memory bank storage, and more specifically, relates to storing data for each memory access command in a single memory bank.

BACKGROUND ART

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to management of data in memory devices, including storing data used for fulfilling memory access commands in a single memory bank of the memory devices to increase performance of the memory device. A memory subsystem can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG. 1. In general, a host system can utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dice. One example of non-volatile memory devices is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction withFIG. 1. The dice in the packages can be assigned to one or more channels for communicating with a memory subsystem controller. Each die can consist of one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells to store data. A cell is an electronic circuit that stores information.

Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one bit of information and has two logic states.

Memory subsystems, such as those that manage main memory (e.g., Double Date Rate (DDR) memory) and storage class memory (e.g., NAND memory devices), can require data to be striped across memory parts/banks. For example, a memory device of a memory subsystem can include a set of nine memory parts and each memory part can include a set of four memory banks (sometimes referred to as parallel banks), which is itself arranged into rows and columns of managed units. In this configuration, the memory device includes thirty-six memory banks split evenly across the nine memory parts. To access data within a memory bank, a memory controller must activate a row within a corresponding memory bank. Although each memory part can handle simultaneous access to separate memory banks, including reading and writing data from each memory bank, each memory bank only permits activation and corresponding access to a single row within the memory bank. Accordingly, before accessing data (i.e., data within a managed unit) in any particular row within a memory bank, all other rows must be closed/deactivated such that the row of interest can be opened/activated.

A memory controller manages access to memory parts, including reading and writing data. For example, a memory controller can receive a memory access command (sometimes referred to as a memory access request or a memory request) from a host system for access to data stored within managed units of a set of memory banks. As used herein, a managed unit is a basic unit of memory access that each memory access command is seeking to access. In particular, a managed unit can be 8-bytes, 16-bytes, 32-bytes, 64-bytes, 72-bytes, etc. and the memory access command can be directed to some number of managed units. For example, a memory access command can seek to access 64 bytes of user data and 8 bytes of parity data/information, which is used for error correction on the 64 bytes of user data. When data is striped across multiple memory banks, the memory controller divides the user and parity data across the multiple memory banks. For example, when a memory access command seeks to write 64 bytes of user data and 8 bytes of parity data (a total of 72 bytes) to a memory device managed by the memory controller, the memory controller divides the 72 bytes of data amongst a set of memory banks instead of writing the entire 72 bytes of data to a single row in a single memory bank. For instance, the memory controller can write 8 bytes to a memory bank in each of the nine memory parts of the memory device described above. To stripe data across the nine memory parts and memory banks in this fashion requires the issuance of row activation commands for each of the nine memory banks such that a memory access command (e.g., a read or write operation) can be performed on each corresponding row. Accordingly, a single memory access command results in significant command amplification when data being accessed is striped across multiple memory parts and corresponding memory banks. In particular, in the example provided above, a single memory access command results in nine row activation commands for nine separate memory banks (i.e., a command amplification of 9×).

Further, since a single memory access command results in data being read or written from/to nine separate memory banks and each memory bank can only facilitate a single access at a time (since only a single row can be activated at a time), as memory access commands begin to accumulate/queue in the memory controller, the probability of a memory bank collision (i.e., two memory access commands that seek to access the same memory bank) increases. For instance, in the example above in which there are thirty-six memory banks in a memory device (i.e., four memory banks in each of nine memory parts) and 72 bytes of data are evenly striped across nine memory banks, a single memory access command occupies one-quarter of the memory banks (e.g., nine of the thirty-six memory banks). Accordingly, a subsequent memory access command that seeks to access data in any one of these memory banks must be delayed. In an optimal situation, the memory controller and memory device can simultaneously handle four memory access commands. However, this optimal situation requires each of the four memory commands to access data in set of non-overlapping memory banks, which can be a rare/improbable occurrence.

Memory subsystems designed to stripe data across memory banks seek to efficiently process memory access commands that are directed to serial memory addresses. Namely, these memory subsystems assume that memory access commands that are serially processed are targeted at adjacent addresses/locations or at least memory locations in the same row of a memory bank. In this fashion, a single row activation can be performed to fulfill multiple, serial memory access commands. This approach attempts to saturate the bandwidth of a memory bus by exploiting memory bank interleaving (e.g., activation of multiple rows in multiple memory banks simultaneously) and open page hits. However, it is more common to receive non-serial memory access commands (e.g., memory access commands that are directed at non-serial locations/addresses). For instance, processes associated with artificial intelligence and search routines often request data from non-serial/random memory addresses/locations, which would be located outside a single row of a memory bank. Accordingly, the time-intensive task of opening a row needs to be incurred before the comparatively quicker task of accessing data can be performed. With heavy memory bank collisions, delays caused by these collisions are exacerbated, as all pending memory requests need to wait for rows to be activated for currently processed memory requests.

On the basis of various factors associated with striping data across memory banks, including command amplification and memory bank collisions, the performance of the memory subsystem is compromised. Namely, the number of memory access commands that the memory controller and the memory device can process during a specified time period is reduced based on overhead and inefficiencies associated with striping data across memory banks. In some cases, this overhead and associated inefficiencies can result in a reduction of performance of up to 90% from the capabilities of a memory controller and corresponding memory device (i.e., the maximum number of memory access commands that a memory controller and corresponding memory device will handle is 10% of the capabilities of these devices).

Aspects of the present disclosure address the above and other deficiencies by storing each segment of data sought by a memory access command in a single row of a single memory bank in a single memory part of a single memory device. Accordingly, to entirely/completely fulfill/process a memory access command received from a host system or otherwise generated by the memory controller, a memory controller that manages the memory device activates a single row of a single memory bank and without activation/access to any other row in the memory device or any other memory device (e.g., without activating or accessing another row in another memory bank). This allows each memory bank of each memory part within a memory device to be available for fulfillment of separate memory access commands. For instance, in the example above in which a memory device includes nine memory parts and each memory part includes four memory banks, a memory controller can simultaneously access each memory bank from each memory part (e.g., simultaneously access thirty-six memory banks) to fulfill thirty-six corresponding memory access commands. In comparison, when each managed unit is striped across separate memory banks in separate memory parts such that multiple memory banks and memory parts are needed to fulfill a single memory access command, at most four memory access commands can be processed/fulfilled simultaneously (assuming ideal conditions in which no memory access command requires access to a same memory bank). By maintaining all data needed to fulfill a single memory access command in a single row of a single memory bank, the memory controller relies on only a single memory bank to fully process/fulfill a memory access command. This configuration, in which a memory access command can be fulfilled through activation of a single row in a single memory bank, (1) prevents command amplification in which a single memory access command requires activation of multiple rows, as only a single row needs to be activated, (2) reduces the likelihood of collisions in which multiple memory access commands seek to access the same memory bank, as each memory access command is associated with a single memory bank instead of multiple (e.g., nine) memory banks, and (3) improves memory access command fulfillment performance and consequent memory access command latency since, with reduced collisions, the memory controller can simultaneously process/fulfill many more memory access commands with minimal delay. Accordingly, the number of memory access commands capable of being processed in a discrete period of time (e.g., the number of memory access commands that can be processed per second) can be increased by (1) reducing overhead associated with each memory access command (e.g., reduce/eliminate command amplification), (2) reducing delays caused by collisions, and (3) increasing the number of memory access commands that can be processed/fulfilled simultaneously. Additional details of these techniques will be described in further detail below.

A memory subsystem controller115(or controller115for simplicity) can communicate with the memory devices130to perform operations such as reading data, writing data, or erasing data at the memory devices130and other such operations (e.g., in response to commands scheduled on a command bus by controller115). The memory subsystem controller115can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The memory subsystem110includes a memory controller113that can fulfill memory access commends (e.g., read and write commands) using a single row in a single memory bank. In some embodiments, the controller115includes at least a portion of the memory controller113. For example, the controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, a memory controller113is part of the host system110, an application, or an operating system.

The memory controller113can fulfill memory access commends (e.g., read and write commands) using a single row in a single memory bank. Further details with regards to the operations of the memory controller113are described below.

FIG. 2is a flow diagram of an example method200to manage data in a set of memory devices130, in accordance with some embodiments of the present disclosure. The method200can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method200is performed by the memory controller113ofFIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation202, the processing device can receive a set of memory access commands from a host system120. For example,FIG. 3shows a memory configuration300, in accordance with some embodiments of the present disclosure. As shown inFIG. 3, the memory configuration300includes a memory controller302that receives a set of memory access commands3041-304Nfrom the host system120. As shown inFIG. 3, in some embodiments, the memory controller302is outside the host system120and the memory controller302is coupled to the host system120through a bus. For example, the memory controller302is coupled to the host system120through a peripheral interconnect bus of a processor of the host system120(e.g., the Peripheral Component Interconnect Express (PCIe) Compute Express Link (CXL)) instead of a memory slot (e.g., a non-volatile dual in-line memory module (NVDIMM) slot or a double data rate (DDR) slot) of the host system120. In this fashion, the memory controller302can bypass a memory controller integrated in processor of the host system120. In one embodiment (and for the purpose of describing the method200), the memory controller302is the memory controller113of the memory subsystem110. Although shown inFIG. 3as the memory controller302being outside of the host system120, in some embodiments the memory controller302can be integrated within the host system120. For example, the host system120can be/include a processing device (e.g., a central processing unit (CPU), graphics processing unit (GPU), system on a chip (SOC), etc.) with integrated memory (e.g., a cache hierarchy, including one or more of a level one (L1) cache and a level two (L2) cache). In either case (i.e., the memory controller302being inside or outside of the host system120), in response to a miss in the integrated memory of the host system120or a flush or clean from the integrated memory of the host system120, the memory controller302may receive the set of memory access commands3041-304Ndirected at the memory device130at operation202. In the case of a miss, the set of memory access commands3041-304Ncan include one or more of a read command, which seeks to read data from the memory components130, and a write command, which seeks to write data that has been evicted from the integrated memory to the memory devices130to make room for the newly read data.

Although described in relation to receiving each of the memory access commands304concurrently/simultaneously, in some embodiments, two or more memory access commands304from the set of memory access commands3041-304Ncan be received (1) during separate (potentially overlapping) time periods and/or (2) in relation to separate stimuli (e.g., separate read and/or write commands that correspond to separate flushes). Accordingly, at operation202, the memory controller113can receive memory access commands304that are separated by time and/or are unrelated to each other.

As noted above, the set of memory access commands3041-304Nseek to access data stored in the memory devices130. For example, the memory access command3041can seek to access 64 bytes of user data (e.g., data used for a video, artificial intelligence, a search application, etc.) stored in the memory devices130. To ensure the 64 bytes of user data does not contain errors, the memory access command3041can also retrieve 8 bytes of parity data, such that a total of 72 bytes of data is retrieved from the memory device130in response to the memory access command3041. Each of the other memory access commands304in the set of memory access commands3041-304Ncan be similarly directed to 64 bytes of user data and 8 bytes of corresponding parity data. Although described as including 64 bytes of user data and 8 bytes of parity data, in some embodiments, the data retrieved in response to each memory access command304can include more or less user data (e.g., 8 bytes, 32 bytes, or 128 bytes of user data) and more or less parity data (e.g., 0 bytes or 16 bytes of parity data). Accordingly, the use of 64 bytes of user data and 8 bytes of parity data is for illustrative purposes.

At operation206, the processing device entirely/completely fulfills each of the memory access commands304(e.g., read user data is returned to the host system120and/or user data with parity data is written to memory) in the set of memory access commands3041-304Nusing a single row310in a single memory bank308corresponding to the determined location for each memory access command304(i.e., each memory access command304is entirely/completely fulfilled with access to a single row310in a single memory device130and without access to another row310in a memory bank308of the memory device130or another memory device130). Fulfillment of the memory access commands304can include activating corresponding rows310in corresponding memory banks308based on the determined location. In particular, the memory controller302needs to activate a row310in a memory bank308corresponding to the determined location before the memory controller302can access data (e.g., read from or write to a set of managed units314) in the memory bank308. However, only a single row310in each memory bank308can be activated at any point in time. Thus, for a current memory access command304, the memory controller302determines whether a row310for this memory access command304is already activated in a corresponding memory bank308or, when the row310is not yet activated, whether any other row310in the memory bank308is activated and being used such that the memory controller304cannot activate the row310for the current memory access command304. When the memory controller302cannot activate a row310because of an already activated row310in the memory bank308, a collision has occurred and the current memory access command304is delayed.

As shown inFIG. 3, the memory controller302can independently signal each memory bank308using a set of signaling lines/pins316that are communicatively coupled to corresponding memory banks308. In particular, when data for each memory access command304is striped across multiple memory banks308, the memory controller302can commonly signal each corresponding row310in each memory bank308to activate these rows310. However, although this signaling is efficient in terms of using a single line/pin, it leads to command amplification as a single memory access command304results in multiple row activation commands to fulfill the single memory access command304. In contrast, when data for a single memory access command304, including both user data and parity data, is stored in a single row310of a single memory bank308, only a single row activation command is needed to fulfill the memory access command304. For example, in the example above in which nine rows310and corresponding memory banks308are needed to fulfill a single memory access command304when data for the memory access command304is striped across memory banks308, a single memory access command304requires nine row activation commands. In comparison, when all data for a memory access command304is included in a single row310of a single memory bank308, a single memory access command304requires one row activation command. Accordingly, this results in a command reduction of 9× in comparison to the striped storage case.

As described herein, each memory access command304is directed at a single row310in a single memory bank308. Accordingly, based on the determined location the memory controller302activates a row310in a single memory bank308to fulfill a single memory access command304.FIG. 4shows an example in which the memory access command3041is directed at data stored in a row310within the memory bank308A1(i.e., a single location in the memory device130). Accordingly, the memory controller302transmits a row activation signal4021to the corresponding row310in the memory bank308A1to access user data and parity data4041stored therein. The memory controller302can use the parity data to perform error correction on the user data and return the error corrected user data to the host system120as a response to the memory access command3041. Accordingly, the memory controller entirely/completely fulfills the memory access command3041based on access to a single row310in a single memory bank308and without access to any other rows310, in any other memory banks308, in any other memory parts306, in any other memory device130(e.g., without activating or accessing another row310in another memory bank308).

FIG. 5shows another example in which the memory access command3041is directed at data stored in a row310within the memory bank308A1, the memory access command3042is directed at data stored in a row310within the memory bank308B1, and the memory access command3043is directed at data stored in a row310within the memory bank308I1. Accordingly, the memory controller302transmits (1) a row activation signal4021to the corresponding row310in the memory bank308A1to access user data and parity data4041stored therein, (2) a row activation signal4022to the corresponding row310in the memory bank308B1to access user data and parity data4042stored therein, and (3) a row activation signal4023to the corresponding row310in the memory bank308I1to access user data and parity data4043stored therein. For each case, the memory controller302can use the parity data to perform error correction on the user data and return the error corrected user data to the host system120as respective responses to the memory access commands3041-3043. Accordingly, the memory controller entirely/completely fulfills each of the memory access command3041-3043based on access to a single row310in a single memory bank308and without access to any other rows310, in any other memory banks308, in any other memory parts306, in any other memory device130in each respective case. Although not shown, the procedure described above can apply to each of the memory banks308such that the memory controller302can simultaneously fulfill a number of memory access commands304equal to the number (M) of memory banks308in the memory device130(i.e., the memory controller302can simultaneously fulfill M memory access commands). In the case of the configuration300, the memory controller302can simultaneously fulfill thirty-six memory access commands304as there are thirty-six memory banks308in the memory device130.

In comparison to techniques in which data for a single memory access command304is striped across multiple memory banks308, by maintaining data for each memory access command304in a single memory bank308, the method200and the configuration300described herein can (1) prevent command amplification in which a single memory access command308requires activation of multiple rows310in multiple memory banks308as all data of a memory access command304requires activation of a single row310in a single memory bank308, (2) reduce the likelihood of collisions in which multiple memory access commands304seek to access the same memory bank308since all data of a memory access command304requires activation of a single row310in a single memory bank308, and (3) allow the memory controller302to simultaneously process/fulfill numerous memory access commands304since a single memory access command304does not require the use of a memory bank308in each or multiple memory parts306, which would consequently block and delay all other memory access commands304seeking to access any one of those memory banks308. For example, for a memory access command304that seeks to read or write 72 bytes of data, including 8 kilobytes of parity data, when data is striped across separate memory banks308in each memory part306(e.g., 8 bytes of data for the memory access command304is stored in a memory bank308A, 8 bytes of data for the memory access command304is stored in a memory bank308B, . . . , and 8 bytes of data (e.g., parity data/information) for the memory access command304is stored in a memory bank308I), fulfilling this memory access command304requires the activation of nine rows310in nine separate memory banks308. Accordingly, this use of multiple memory banks308to fulfill a single memory access command304will block those memory banks308from being used for processing/fulfilling other memory access commands304and will result in command amplification (e.g., 9× command amplification). In contrast, by storing the data for each memory access command304in a single memory bank308, the method200and configuration300prevents increases efficiency of the memory access command processing by the memory controller302.