Dimension measurement apparatus calibration standard and method for forming the same

A method for forming a dimension measurement apparatus calibration standard over a substrate is provided. The method includes forming strip structures over the substrate. The method includes depositing a calibration material layer over the substrate and the strip structures. The calibration material layer and the strip structures are made of different materials. The method includes removing the calibration material layer over top surfaces of the strip structures to expose the strip structures. The method includes removing the strip structures. The calibration material layer remaining over sidewalls of the strip structures forms linear calibration structures.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

However, since the feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

FIGS. 1A-1Fare cross-sectional views of various stages of a process for forming a dimension measurement apparatus calibration standard over a substrate, in accordance with some embodiments.FIG. 2Ais a partial top view of the patterned mask layer and the substrate ofFIG. 1A.FIG. 2Bis a partial top view of the dimension measurement apparatus calibration standard and the substrate ofFIG. 1F.

As shown inFIG. 1A, a substrate110is provided. The substrate110has a surface112, in accordance with some embodiments. In some embodiments, the surface112is a planar surface. In some embodiments, the substrate110is a wafer. In some embodiments, the substrate110is made of an elementary semiconductor material including silicon or germanium in a single crystal, polycrystal, or amorphous structure.

In some other embodiments, the substrate110is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe, GaAsP, or a combination thereof. The substrate110may also include a multi-layer semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a combination thereof. The SOI substrate includes, for example, a silicon-on-insulator substrate or a germanium-on-insulator substrate.

Thereafter, a material layer (not shown) is formed over the surface112of the substrate110, in accordance with some embodiments. The material layer includes, for example, polysilicon, tungsten, titanium nitride, or tantalum nitride. The material layer is formed by, for example, a sputtering process, a physical vapor deposition process, or a chemical vapor deposition process.

Afterwards, as shown inFIGS. 1A and 2A, a patterned mask layer120is formed over the material layer, in accordance with some embodiments. The patterned mask layer120includes, for example, oxides. Thereafter, an etching process is performed to remove the material layer exposed by the patterned mask layer120, in accordance with some embodiments. The remaining material layer forms strip structures130, in accordance with some embodiments. It should be noted that, for the sake of simplicity,FIGS. 1A-1Eshow only two strip structures130for illustration, but the invention is not limited thereto. For example, the number of the strip structures130may be three or more than three.

Thereafter, as shown inFIG. 1B, a calibration material layer140is deposited over the surface112of the substrate110and top surfaces132and sidewalls134of the strip structures130, in accordance with some embodiments. In some embodiments, the calibration material layer140is conformally deposited over the surface112of the substrate110and the sidewalls134of the strip structures130, in accordance with some embodiments.

The calibration material layer140and the strip structures130are made of different materials, in accordance with some embodiments. The calibration material layer140includes silicon, silicon nitride, silicon carbon nitride, silicon carbon oxide nitride (SiCON), silicon carbide (SiC), silicon oxide, silicon oxide nitride (SiON), aluminum, titanium nitride, tantalum nitride, tungsten, or titanium, in accordance with some embodiments.

The calibration material layer140is deposited by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, in accordance with some embodiments. In some embodiments, the calibration material layer140is deposited by an atomic layer deposition process, a plasma enhanced atomic layer deposition process, a low-pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or a hybrid physical-chemical vapor deposition process.

Thereafter, as shown inFIG. 1C, a cover layer150is formed over the calibration material layer140, in accordance with some embodiments. The cover layer150fills gaps G between the strip structures130to cover the calibration material layer140over the sidewalls134of the strip structures130, in accordance with some embodiments. The cover layer150includes photoresist materials or other suitable materials, which are different from the materials of the calibration material layer140and the strip structures130. The cover layer150is formed by a coating process or another suitable process.

Afterwards, as shown inFIG. 1D, a top portion of the cover layer150, the calibration material layer140over the top surfaces132, and the patterned mask layer120are removed, in accordance with some embodiments. After the removal process, the strip structures130are exposed. The removal process includes a dry etching process or another suitable removal process, which removes the cover layer150, the calibration material layer140, and the patterned mask layer120at substantially the same rate. In some embodiments, the removal process further removes a portion of the strip structures130.

Thereafter, as shown inFIG. 1E, the cover layer150is removed, in accordance with some embodiments. The removal process includes a photoresist stripping process or another suitable removal process. Afterwards, as shown inFIGS. 1F and 2B, the strip structures130are removed. The removal process includes, for example, a dry etching process, a wet etching process, or a combination thereof.

As shown inFIGS. 1E, 1F, and 2B, the calibration material layer140remaining over the sidewalls134of the strip structures130forms linear calibration structures142a,142b,142c, and142d, in accordance with some embodiments. In some embodiments, a dimension measurement apparatus calibration standard100includes the remaining calibration material layer140. The dimension measurement apparatus calibration standard100includes, for example, a critical dimension scanning electron microscope (CD-SEM) calibration standard.

The dimension measurement apparatus calibration standard100includes the linear calibration structures142a,142b,142c, and142dand connection structures144a,144b, and144c, in accordance with some embodiments. In some embodiments, the linear calibration structures142a,142b,142c, and142dare parallel to each other.

The connection structure144bconnects the linear calibration structures142band142c, in accordance with some embodiments. The connection structure144aconnects the linear calibration structure142aand another linear calibration structure (not shown), in accordance with some embodiments. The connection structure144cconnects the linear calibration structure142dand another linear calibration structure (not shown), in accordance with some embodiments.

In some embodiments, the connection structure144a,144b, or144cis thinner than the linear calibration structure142a,142b,142c, or142d. A height H is equal to the thickness difference between the linear calibration structure142a,142b,142c, or142dand the connection structure144a,144b, or144c. In some embodiments, the height H ranges from about 10 nm to about 200 nm. The linear calibration structures142a,142b,142c, and142dare kept at a proper height in order to provide sufficient contrast to make calibrating the CD-SEM easier and more accurate.

Since the calibration material layer140is formed by a deposition process, the calibration material layer140has a substantially uniform thickness. Therefore, the linear calibration structures142a,142b,142c, and142dmay have substantially similar line widths W. In some embodiments, the line width W ranging from about 5 nm to about 50 nm. In some embodiments, a line width uniformity (3-sigma) of the linear calibration structures142a,142b,142c, and142dranges from about 0.05 nm to about 1 nm.

Since critical dimensions (e.g., line widths or thicknesses) of features (e.g., metal lines or films) of current semiconductor devices are small, a critical dimension scanning electron microscope (CD-SEM) is used to measure the critical dimensions. However, the measured value of the critical dimension may fluctuate from tool to tool due to CD-SEM tools having tool offsets that vary from tool to tool.

Therefore, a calibration standard may be used to calibrate the CD-SEM tools for tool-to-tool matching. The different CD-SEM tools need to measure different features (e.g., linear calibration structures) of the calibration standard, respectively, to avoid a charging effect. Therefore, the uniformity of the critical dimensions (e.g., line widths) of the features of the calibration standard is important.

Since the linear calibration structures142a,142b,142c, and142dare not formed by a photolithography process and an etching process, the uniformity of the line widths W is not affected by the photolithography process and the etching process. As a result, the uniformity of the line widths W is improved, which benefits tool-to-tool matching and therefore improves the accuracy of the measured values of the critical dimensions of semiconductor devices.

In some embodiments, the substrate110is a calibration wafer. In some other embodiments, the substrate is an in-line wafer, and a dimension measurement apparatus calibration standard and semiconductor devices (not shown) are formed over the substrate simultaneously. The detailed process performed over the in-line wafer is illustrated as follows.

FIGS. 3A-3Fare cross-sectional views of various stages of a process for forming a dimension measurement apparatus calibration standard over a substrate, in accordance with some embodiments. It should be noted that the process ofFIGS. 3A-3Fis similar to the process ofFIGS. 1A-1F, except thatFIGS. 3A-3Fshow that a dimension measurement apparatus calibration standard and semiconductor devices are formed over a substrate simultaneously.

As shown inFIG. 3A, a substrate210is provided. The substrate210has a surface212, in accordance with some embodiments. In some embodiments, the surface212is a planar surface. In some embodiments, the substrate210is an in-line wafer. The substrate210has an active region214and a calibration region216, in accordance with some embodiments.

Thereafter, a material layer (not shown) is formed over the surface212of the substrate210, in accordance with some embodiments. The material layer includes, for example, polysilicon. The material layer is formed by, for example, a sputtering process. Afterwards, a patterned mask layer220is formed over the material layer, in accordance with some embodiments. The patterned mask layer220includes, for example, oxides.

Thereafter, an etching process is performed to remove the material layer exposed by the patterned mask layer220, in accordance with some embodiments. The remaining material layer forms gates231in the active region214and strip structures230in the calibration region216, in accordance with some embodiments. In some embodiments, a dielectric layer I is formed between the gates231and the substrate210. In some embodiments, the dielectric layer I is further formed between the strip structures230and the substrate210.

Thereafter, the calibration region216is covered by a mask layer (not shown), and lightly doped regions218are formed in the active region214, in accordance with some embodiments. The lightly doped regions218are formed by, for example, an ion implantation process. The ion implantation process may use the gates231as a mask, and the lightly doped regions218are at two opposite sides of each of the gates231.

The lightly doped regions218may be lightly doped source regions and lightly doped drain (LDD) regions. The dopants used in the ion implantation process may include boron or phosphorous. Thereafter, the mask layer covering the calibration region216is removed, in accordance with some embodiments.

Afterwards, a calibration material layer240is deposited over the surface212of the substrate210, top surfaces232and sidewalls234of the strip structures230, and the gates231, in accordance with some embodiments. The calibration material layer240and the strip structures230are made of different materials, in accordance with some embodiments.

The calibration material layer240includes insulating materials. The insulating materials include, for example, silicon nitride, silicon carbon nitride, silicon carbon oxide nitride (SiCON), silicon carbide (SiC), silicon oxide, or silicon oxide nitride (SiON), in accordance with some embodiments. The deposition method of the calibration material layer240is similar to that of the calibration material layer140, in accordance with some embodiments.

Thereafter, the calibration region216is covered by a mask layer (not shown), and an anisotropic etching process (e.g. a dry etching process) is performed to remove a portion of the calibration material layer240in the active region214. Afterwards, the mask layer is removed. As shown inFIG. 3B, the remaining calibration material layer240over the sidewalls of the patterned mask layer220, the gate231, and the dielectric layer I forms spacer layers310. The spacer layers310may be configured to electrically isolate the gates231from other devices.

Thereafter, the calibration region216is covered by a mask layer (not shown), and source/drain stressors219are formed in the active regions214and at two opposite sides of each of the gates231. Afterwards, the mask layer is removed. The formation method of the source/drain stressors219includes, for example, an etching process for removing a portion of the substrate210and a selective epitaxial growth (SEG) process.

Depending on the desired type of the resulting MOS device, either source/drain stressors applying a compressive stress to the channel region (such as SiGe stressors) or source/drain stressors applying a tensile stress to the channel region (such as SiC stressors) are formed.

In this step, transistors A are formed in the active regions214. Each of the transistors A includes a gate231and two source/drain stressors219at two opposite sides of the gate231, in accordance with some embodiments. In some embodiments, the transistors A are electrically connected in series with each other.

Afterwards, as shown inFIG. 3C, an etch stop layer250is deposited over the calibration material layer240, the spacer layer310, and the patterned mask layer220, in accordance with some embodiments. The etch stop layer250includes, for example, silicon nitride.

Thereafter, a bottom layer260(also referred to as a bottom anti-reflective coating layer) is deposited over the etch stop layer250, in accordance with some embodiments. The bottom layer260includes, for example, organic materials. Afterwards, a mask layer270is formed over the active region214, in accordance with some embodiments. In some embodiments, the mask layer270includes a photoresist layer.

Thereafter, as shown inFIG. 3D, top portions of the bottom layer260, the etch stop layer250, the calibration material layer240, and the patterned mask layer220in the calibration region216and a top portion of the mask layer270are removed, in accordance with some embodiments. The removal process includes, for example, a dry etching process.

As shown inFIG. 3E, the bottom layer260and the mask layer270are removed, in accordance with some embodiments. As shown inFIG. 3F, the strip structures230are removed. The removal process includes, for example, a dry etching process, a wet etching process, or a combination thereof.

As shown inFIGS. 3E and 3F, the calibration material layer240remaining over the sidewalls234of the strip structures230forms linear calibration structures242a,242b,242c, and242d, in accordance with some embodiments. In some embodiments, a dimension measurement apparatus calibration standard200includes the remaining calibration material layer240in the calibration region216.

The dimension measurement apparatus calibration standard200includes the linear calibration structures242a,242b,242c, and242dand connection structures244a,244b, and244c, in accordance with some embodiments. The connection structure244bconnects the linear calibration structures242band242c, in accordance with some embodiments.

The connection structure244aconnects the linear calibration structure242aand another linear calibration structure (not shown), in accordance with some embodiments. The connection structure244cconnects the linear calibration structure242dand another linear calibration structure (not shown), in accordance with some embodiments. In some embodiments, the dimension measurement apparatus calibration standard200further includes the etch stop layer250over the remaining calibration material layer240in the calibration region216.

Since the dimension measurement apparatus calibration standard200is formed over the in-line wafer, an in-line tool calibration procedure may be performed, in accordance with some embodiments. Therefore, an off-line tool calibration procedure is not needed, which may shorten the time consumed by the tool calibration, in accordance with some embodiments.

FIGS. 4A-4Fare cross-sectional views of various stages of a process for forming a dimension measurement apparatus calibration standard over a substrate, in accordance with some embodiments.FIG. 5is a top view of the dimension measurement apparatus calibration standard, the etch stop layer, and the substrate ofFIG. 4F, in accordance with some embodiments.

After the stage ofFIG. 1C, as shown inFIG. 4A, a top portion of the cover layer150, the calibration material layer140over the top surfaces132, and the patterned mask layer120are removed, in accordance with some embodiments. After the removal process, the strip structures130are exposed.

The removal process includes, for example, a dry etching process. The removal rates of the cover layer150and the calibration material layer140may be different due to the fact that the cover layer150and the calibration material layer140are made of different materials. Therefore, a top surface141of the calibration material layer140is a curved surface, in accordance with some embodiments.

As shown inFIG. 4B, the cover layer150is removed, in accordance with some embodiments. As shown inFIG. 4C, an etch stop layer410is deposited over the calibration material layer140and the strip structures130, in accordance with some embodiments. The etch stop layer410includes, for example, silicon nitride.

Thereafter, a filling layer420is formed over the calibration material layer140and the strip structures130to fill gaps G between the strip structures130, in accordance with some embodiments. In some embodiments, the filling layer420is formed over the etch stop layer410. The filling layer420includes dielectric materials, such as silicon oxides. The filling layer420is formed by, for example, a CVD process.

As shown inFIG. 4D, a planarization process is performed to remove a portion of the filling layer420, top portions of the etch stop layer410, top portions of the calibration material layer140, and top portions of the strip structures130, in accordance with some embodiments. The planarization process includes, for example, a chemical-mechanical polishing process.

The planarization process may have a first step and a second step, in accordance with some embodiments. The first step and the second step use different slurries. The first step includes removing a portion of the filling layer420until exposing the etch stop layer410. The second step includes removing the top portions of the etch stop layer410, the top portions of the calibration material layer140, and the top portions of the strip structures130. After the planarization process, the strip structures130are exposed.

As shown inFIG. 4E, the filling layer420is removed. The removal process includes, for example, a wet etching process. In some other embodiments (not shown), the etch stop layer410is removed by a wet etch process.

As shown inFIG. 4F, the strip structures130are removed. The removal process is similar to those of the strip structures130ofFIG. 1E. As shown inFIGS. 4E, 4F, and 5, the calibration material layer140remaining over the sidewalls134of the strip structures130forms linear calibration structures142a,142b,142c, and142d, in accordance with some embodiments. In some embodiments, a dimension measurement apparatus calibration standard400includes the remaining calibration material layer140. In some embodiments, the dimension measurement apparatus calibration standard400further includes the etch stop layer410.

The remaining calibration material layer140is substantially similar to the remaining calibration material layer140ofFIG. 1F. It should be noted that after the planarization process, the top surface141of the calibration material layer140becomes a planar surface, which helps to improve the accuracy of the measured values of the line widths W of the linear calibration structures142a,142b,142c, and142d.

In some embodiments, after the planarization process, the top surface411of the etch stop layer410also becomes a planar surface, which helps to improve the accuracy of the measured value of a line width W1of a linear structure constituted by the linear calibration structure142a,142b,142c, or142dand the etch stop layer410. In some embodiments, the top surface411of the etch stop layer410is coplanar with the top surface141of the calibration material layer140.

In some embodiments, the etch stop layer410covers a sidewall S1of the linear calibration structure142b, a sidewall S2of the linear calibration structure142c, and a top surface S3of the connection structure144b. The sidewalls S1and S2face each other.

In some embodiments, the substrate110is a calibration wafer. In some other embodiments, the substrate is an in-line wafer, and a dimension measurement apparatus calibration standard and semiconductor devices (not shown) are formed over the substrate simultaneously. The detailed process performed over the in-line wafer is illustrated as follows.

FIGS. 6A-6Hare cross-sectional views of various stages of a process for forming a dimension measurement apparatus calibration standard over a substrate, in accordance with some embodiments. It should be noted that the process ofFIGS. 6A-6His similar to the process ofFIGS. 4A-4F, except thatFIGS. 6A-6Hshows that a dimension measurement apparatus calibration standard and semiconductor devices are formed over a substrate simultaneously.

After the stage illustrated inFIG. 3B, as shown inFIG. 6A, a cover layer150is formed over the substrate210to cover the calibration material layer240, the spacer layer310, and the patterned mask layer220, in accordance with some embodiments. In some embodiments, the cover layer150includes a photoresist layer.

Thereafter, as shown inFIG. 6B, a top portion of the cover layer150, the calibration material layer240over the top surfaces232of the strip structures230, and the patterned mask layer220are removed, in accordance with some embodiments. After the removal process, the strip structures230are exposed.

The removal process includes, for example, a dry etching process. The removal rates of the cover layer150and the calibration material layer240may be different due to that the cover layer150and the calibration material layer240are made of different materials. Therefore, a top surface241of the calibration material layer240is a curved surface, in accordance with some embodiments. Thereafter, as shown inFIG. 6C, the cover layer150is removed.

As shown inFIG. 6D, an etch stop layer410is deposited over the calibration material layer240, the strip structures230, the gates231, and the spacer layer310, in accordance with some embodiments. Thereafter, a filling layer420is formed over the calibration material layer240, the strip structures230, the gates231, and the spacer layer310to fill gaps G between the strip structures230and gaps G1between the gates231, in accordance with some embodiments. In some embodiments, the filling layer420is formed over the etch stop layer410.

As shown inFIG. 6E, a planarization process is performed to remove a portion of the filling layer420, top portions of the etch stop layer410, top portions of the calibration material layer240, and top portions of the strip structures230, in accordance with some embodiments. The planarization process includes, for example, a chemical-mechanical polishing process.

After the planarization process, the top surface241of the calibration material layer240and the top surface411of the etch stop layer410both become planar surfaces, and the strip structures230and the gates231are exposed. In some embodiments, the top surface411of the etch stop layer410is coplanar with the top surface241of the calibration material layer240.

As shown inFIG. 6F, the strip structures230and the gates231are removed, in accordance with some embodiments. The removal process includes, for example, a dry etching process, a wet etching process, or a combination thereof. After the removal process, trenches T are formed in the spacer layer310. As shown inFIG. 6G, a mask layer610is formed over the substrate210to cover the active region214, in accordance with some embodiments. In some embodiments, the mask layer610includes a photoresist layer.

As shown inFIG. 6H, the filling layer420in the calibration region216is removed, in accordance with some embodiments. The removal process includes, for example, a wet etching process. Thereafter, the mask layer610is removed. The removal process includes a photoresist stripping process or another suitable removal process. In subsequent processes (not shown), gates (e.g., metal gates) may be formed in the trenches T.

The remaining calibration material layer240is substantially similar to the remaining calibration material layer240ofFIG. 3F. It should be noted that after the planarization process, the top surface241of the calibration material layer240becomes a planar surface, which helps to improve the accuracy of the measured values of the line widths W of the linear calibration structures242a,242b,242c, and242d.

In some embodiments, after the planarization process, the top surface411of the etch stop layer410also becomes a planar surface, which helps to improve the accuracy of the measured value of a line width W1of a linear structure constituted by the linear calibration structure242a,242b,242c, or242dand the etch stop layer410.

In accordance with some embodiments, dimension measurement apparatus calibration standards and methods for forming the same are provided. The methods form a dimension measurement apparatus calibration standard by a deposition process, not by a photolithography process and an etching process. Therefore, the uniformity of the line widths of linear calibration structures of the dimension measurement apparatus calibration standard is not affected by the photolithography process and the etching process. As a result, the uniformity of the line widths of the linear calibration structures is improved, which benefits tool-to-tool matching and therefore improves the accuracy of the measured values of the critical dimensions of semiconductor devices.

In accordance with some embodiments, a method for forming a dimension measurement apparatus calibration standard over a substrate is provided. The method includes forming strip structures over the substrate. The method includes depositing a calibration material layer over the substrate and the strip structures. The calibration material layer and the strip structures are made of different materials. The method includes removing the calibration material layer over the top surfaces of the strip structures to expose the strip structures. The method includes removing the strip structures. The calibration material layer remaining over sidewalls of the strip structures forms linear calibration structures.

In accordance with some embodiments, a method for forming a dimension measurement apparatus calibration standard over a substrate is provided. The method includes forming strip structures over the substrate. The method includes depositing a calibration material layer over the substrate and the strip structures. The calibration material layer and the strip structures are made of different materials. The method includes removing the calibration material layer over first top surfaces of the strip structures. The method includes forming a filling layer over the calibration material layer and the strip structures to fill gaps between the strip structures. The method includes performing a planarization process to remove a portion of the filling layer, top portions of the calibration material layer, and top portions of the strip structures. The method includes removing the filling layer. The method includes removing the strip structures. The calibration material layer remaining over sidewalls of the strip structures forms linear calibration structures.

In accordance with some embodiments, a dimension measurement apparatus calibration standard over a substrate is provided. The dimension measurement apparatus calibration standard includes linear calibration structures disposed on the substrate. The linear calibration structures at least include a first linear calibration structure and a second linear calibration structure. The dimension measurement apparatus calibration standard includes a connection structure connecting the first linear calibration structure and the second linear calibration structure. The connection structure is thinner than the linear calibration structures, and the connection structure and the linear calibration structures are made of the same material.