Rail-to-rail comparator circuit and method thereof

A circuit includes a PMOS transistor pair receiving a first voltage at a first circuit node and a second voltage at a second circuit node and outputting a third voltage at a third circuit node and a fourth voltage at a fourth circuit node; and an NMOS transistor pair receiving the third voltage at the third circuit node and the fourth voltage at the fourth circuit node and outputting the first voltage at the first circuit node and the second voltage at the second circuit node. The circuit further includes a first voltage-controlled resistor controlled by a first control voltage and a second control voltage in accordance with a clock signal providing a coupling between the third voltage at the third circuit node and the second voltage at the second circuit node; and a second voltage-controlled resistor controlled by the second control voltage and the first control voltage in accordance with the clock signal providing a coupling between the fourth voltage at the fourth circuit node and the first voltage at the first circuit node.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to comparator circuits and more particularly to comparator circuits exhibiting a relatively high-speed operation, while maintaining relatively low power consumption.

2. Description of Related Art

Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as PMOS (p-channel metal-oxide semiconductor) transistor, NMOS (n-channel metal-oxide semiconductor) transistor, “gate,” “source,” “drain,” “voltage,” “current,” “circuit,” “circuit node,” “power supply,” “ground,” “rail-to-rail,” “clock,” “comparator,” “inverter,” “pull-up,” “pull-down” and “latch”. Terms and basic concepts like these are apparent from prior art documents, e.g. text books such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), and thus will not be explained in detail here.

A clocked comparator is an apparatus for detecting a sign of a differential signal in accordance with a timing defined by a clock. A differential signal comprises a first end and a second end. A clocked comparator receives the differential signal and outputs a logical decision in accordance with a timing defined by a clock. In a phase of the clock, a level of the first end (of the differential signal) is compared with a level of the second end (of the differential signal), and the logical decision (which is a resolution as a result of the comparison) is made. The logical decision is set to “high” (“low”) if the level of the first end is higher (lower) than the level of the second end. Merits of a clocked comparator are usually assessed by two factors: speed and power consumption. Speed of a clocked comparator refers to how fast it can resolve a small differential signal, where a level of the first end is very close to a level of the second end. Power consumption of a clocked comparator refers to the energy it takes to fulfill the comparison function. In reality, there is a trade-off between the speed and the power consumption. As known in prior art, it takes a longer time to resolve a comparison for a small differential signal than for a large differential signal. Therefore, to achieve high speed, a pre-amplifier is usually used, so as to amplify the differential signal and thus facilitate the task of resolving the comparison. The use of a pre-amplifier, however, increases the overall power consumption.

BRIEF SUMMARY OF THIS INVENTION

An objective of this present invention is to have a comparator of relatively high speed, yet relatively low power consumption.

An objective of this present invention is to enable a comparator to rapidly resolve a comparison between two signals and automatically shut itself off to save power after the comparison is resolved.

In an embodiment, a circuit comprises: a PMOS transistor pair receiving a first voltage at a first circuit node and a second voltage at a second circuit node and outputting a third voltage at a third circuit node and a fourth voltage at a fourth circuit node; an NMOS transistor pair receiving the third voltage at the third circuit node and the fourth voltage at the fourth circuit node and outputting the first voltage at the first circuit node and the second voltage at the second circuit node; a first voltage-controlled resistor controlled by a first control voltage and a second control voltage in accordance with a clock signal providing a coupling between the third voltage at the third circuit node and the second voltage at the second circuit node; and a second voltage-controlled resistor controlled by the second control voltage and the first control voltage in accordance with the clock signal providing a coupling between the fourth voltage at the fourth circuit node and the first voltage at the first circuit node, wherein the first voltage-controlled resistor and the second voltage-controlled resistor are constructed using the same circuit but interfacing with the first control voltage and the second control voltage in a different way so that a difference between the first control voltage and the second control voltage leads to a difference between a resistance of the first voltage-controlled resistor and a resistance of the second voltage-controlled resistor.

In an embodiment, a method comprises: incorporating a PMOS transistor pair receiving a first voltage at a first circuit node and a second voltage at a second circuit node and outputting a third voltage at a third circuit node and a fourth voltage at a fourth circuit node; incorporating an NMOS transistor pair receiving the third voltage at the third circuit node and the fourth voltage at the fourth circuit node and outputting the first voltage at the first circuit node and the second voltage at the second circuit node; coupling the third voltage at the third circuit node to the second voltage at the second circuit node via a first voltage-controlled resistor controlled by a first control voltage and a second control voltage in accordance with a clock signal; and coupling the fourth voltage at the fourth circuit node to the first voltage at the first circuit node via a second voltage-controlled resistor controlled by the second control voltage and the first control voltage in accordance with the clock signal, wherein the first voltage-controlled resistor and the second voltage-controlled resistor are constructed using the same circuit but interfacing with the first control voltage and the second control voltage in a different way so that a difference between the first control voltage and the second control voltage leads to a difference between a resistance of the first voltage-controlled resistor and a resistance of the second voltage-controlled resistor.

DETAILED DESCRIPTION OF THIS INVENTION

The present invention relates to comparator circuits. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described herein or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

Throughout this disclosure: “VDD” denotes a power supply circuit node (or simply power supply node); a logical signal is a signal that is either “high” or “low”; it is said to be “high” when the logical signal is of a high voltage level that is equal to a voltage level of a power supply node (which is denoted by VDD in this disclosure); and it is said to be “low” when the logical signal is of a low voltage level that is equal to a voltage level of a ground node. It should be understood that, in this disclosure, “equal to” is stated in an engineering sense. For instance, if a difference between a first voltage A and a second voltage B is smaller than a specified tolerance of interest, the difference is negligible and as a result the first voltage A is said to be equal to the second voltage B in the engineering sense. Likewise, “zero” in this disclosure is also stated in an engineering sense; for instance, if a current is smaller than a specified tolerance of interest, the current is negligible and as a result is said to be zero in the engineering sense. In addition, a logical signal might be temporarily neither “high” nor “low”; this occurs, for instance, when the logical signal is in a process of transitioning from “high” to “low” or from “low” to “high,” or in a process of resolving a decision. However, the logical signal is still said to be “logical” in nature because the process of transitioning or resolving is only temporary.

A schematic diagram of a comparator circuit100in accordance with an embodiment of the present invention is shown inFIG. 1A. Comparator circuit100comprises: a PMOS transistor pair150(comprising PMOS transistors151and152) for receiving a first voltage V1at a first circuit node101and a second voltage V2at a second circuit node102and outputting a third voltage V3at a third circuit node103and a fourth voltage V4at a fourth circuit node104; an NMOS transistor pair110(comprising NMOS transistors111and112) for receiving the third voltage V3at the third circuit node103and the fourth voltage V4at the fourth circuit node104and outputting the first voltage V1at the first circuit node101and the second voltage V2at the second circuit node102; a first voltage-controlled resistor (VCR)130controlled by a first control voltage VC1and a second control voltage VC2in accordance with a clock signal CLK for providing a coupling between the third voltage V3at the third circuit node103and the second voltage V2at the second circuit node102; and a second voltage-controlled resistor (VCR)140controlled by the second control voltage VC2and the first control voltage VC1in accordance with the clock signal CLK for providing a coupling between the fourth voltage V4at the fourth circuit node104and the first voltage V1at the first circuit node101. Note that the NMOS transistor pair110and PMOS transistor pair150form a positive feedback loop: an increase (decrease) of V3leads to a decrease (increase) of V1(due to NMOS transistor111), which in turn leads to an increase (decrease) of V3(due to PMOS transistor151); an increase (decrease) of V4leads to a decrease (increase) of V2(due to NMOS transistor112), which in turn leads to an increase (decrease) of V4(due to PMOS152). Due to the positive feedback nature, a change at V3or V4is self-accelerating, resulting in either V3rising to VDD and V4falling to ground, or V3falling to ground and V4rising to VDD. If V3and V4are both falling down from VDD, a race condition occurs and the one that falls more rapidly will win the race and fall to ground while the other one will be pulled high to VDD. The first control voltage VC1and the second control voltage VC2determine which one between V3and V4rises to VDD and which one falls to ground.

Reference is now made toFIG. 1A. The clock signal CLK includes a first clock CLK[1] and a second clock CLK[2] that is a complementary (i.e., logically inverted) clock of the first clock CLK[1], as depicted in an exemplary timing diagram shown inFIG. 1B. The clock signal CLK defines a phase of the comparator circuit100; when CLK[1] is low and CLK[2] is high (e.g. region181), the comparator circuit100is in a preset phase where voltages at certain circuit nodes within VCR130and VCR140are preset to certain levels; when CLK[1] is high and CLK[2] is low (e.g., region182), the comparator circuit100is in an active phase where a task of comparison between VC1and VC2takes place. In the preset phase, V3and V4are both pulled high to VDD by VCR130and VCR140; upon entering the active phase, V3and V4are both falling from VDD; if the resistance of VCR130is greater (smaller) than the resistance of VCR140, a first current I1flowing into VCR130will be smaller (greater) than a second current I2flowing into VCR140; this causes V3(V4) to fall more slowly (rapidly) than V4(V3); due to the positive feedback mentioned earlier, V4(V3) will win the race and fall to ground while V3(V4) will be pulled up back to VDD. Comparator circuit100, therefore, can be used to resolve a difference between the first control voltage VC1and the second control voltage VC2via their respective impacts on the resistances of VCR130and VCR140.

VCR130and VCR140are of the same circuit, but controlled differently so that the difference between the resistance of VCR130and the resistance of VCR140represents the difference between VC1and VC2. Both VCR130and VCR140are a variable resistor providing a resistance between two terminals denoted as “VA” and “VB”; the resistance is determined by two control signals (either VC1and VC2, or VC2and VC1) received at two terminals denoted as “VP” and “VN” in accordance with a timing determined by the clock signal CLK received at a terminal denoted as “CK.”

A schematic diagram of a voltage-controlled resistor (VCR)200suitable for embodying VCR130and140ofFIG. 1Ais shown inFIG. 2. VCR200comprises a “VA” terminal for coupling to either V3or V4(seeFIG. 1A), a “VB” terminal for coupling to either V2or V1(seeFIG. 1A), a “VP” terminal for coupling to either VC1or VC2(seeFIG. 1A), a “VN” terminal for coupling to either VC2or VC1(seeFIG. 1A), and two clock terminals “CK[1]” and “CK[2]” for coupling to the clock signal CLK (seeFIG. 1A) that comprises CLK[1] and CLK[2] as mentioned earlier. (InFIG. 1A, “CLK” and “CK” are shown for brevity; it must be understood that CLK comprises two clocks CLK[1] and CLK[2], while CK comprises two terminals CK[1] and CK[2], for interfacing with CLK[1] and CLK[2], respectively.)

As shown inFIG. 2, VCR200comprises: PMOS VCR210(comprising a serial connection of PMOS transistor211controlled by the signal from terminal VP and PMOS transistor212controlled by the clock from terminal CK[2]), NMOS VCR220(comprising a serial connection of NMOS transistor221controlled by the signal from terminal VN and NMOS transistor222controlled by the clock from terminal CK[1]), and a set of preset circuits230comprising PMOS transistors231and232for pulling up the voltages at terminals VA and VC to VDD when the clock from terminal CK[1] is low and NMOS transistors233and234for pulling down the voltages at VB and VD to ground when the clock from terminal CK[2] is high. VCR200further comprises an optional CMOS resistor240comprising a PMOS transistor241controlled by the clock from terminal CK[2] and an NMOS transistor242controlled by the clock from terminal CK[1].

During the preset phase where the clock CLK[1] is low and the clock CLK[2] is high (seeFIG. 1AandFIG. 1B), the clock at terminal CK[1] is low and the clock at terminal CK[2] is high (seeFIG. 2); in this phase, the voltages at VA and VC are pulled up to VDD, the voltages at VB and VD are pulled down to ground, and the PMOS VCR210, the NMOS VCR220, and the CMOS resistor240are all disabled and behave like an open circuit. During the active phase where the clock CLK[1] is high and the clock CLK[2] is low (seeFIG. 1AandFIG. 1B), the clock at terminal CK[1] is high and the clock at terminal CK[2] is low (seeFIG. 2); in this phase, the preset circuits230are disabled, and the PMOS VCR210, the NMOS VCR220, and the CMOS resistor240are all enabled and behave like a resistor with a resistance controlled by the voltage at terminal “VP” and the voltage at terminal “VN”. As illustrated inFIG. 1A, the “VP” and the “VN” terminals of VCR130interface with VC1and VC2respectively, while the “VP” and the “VN” terminals of VCR140interface with VC2and VC1respectively. Due to the difference in the interfacing, in the active phase, a difference between VC1and VC2will result in a difference between the resistance of VCR130and the resistance of VCR140. As mentioned earlier, this will cause one of V3and V4to rise to VDD while the other fall to ground.

Now refer back toFIG. 2. The PMOS VCR210and NMOS VCR220together form a “rail-to-rail” topology so that the voltage-controlled resistor200can work for a range of voltages at VP and VN that spans from the ground level to the supply level VDD. In a particular application, one may choose to remove NMOS VCR220along with the “VN” terminal at one's discretion if one is sure that a mean value of the voltage at VN is not higher than a voltage needed for turning on NMOS transistor221, and may choose to remove PMOS VCR210along with the “VP” terminal at one's discretion if one is sure that a mean value of the voltage at VP is not lower than a voltage needed for turning on PMOS transistor211. This concept of removing unnecessary circuits and terminals in a particular application is obvious to those of ordinary skill in the art and thus not described in detail here. Also, one may choose to remove PMOS transistor241, or NMOS transistor242, or both, at one's discretion.

A schematic diagram of an alternative voltage-controlled resistor (VCR)300also suitable for embodying VCR130and140ofFIG. 1Ais shown inFIG. 3. VCR300comprises a “VA” terminal for coupling to either V3or V4(seeFIG. 1A), a “VB” terminal for coupling to either V2or V1(seeFIG. 1A), a “VP” terminal for coupling to either VC1or VC2(seeFIG. 1A), a “VN” terminal for coupling to either VC2or VC1(seeFIG. 1A), and two terminals “CK[1]” and “CK[2]” for coupling to the clock signal CLK (seeFIG. 1A) that comprises CLK[1] and CLK[2] as mentioned earlier.

As shown inFIG. 3, VCR300comprises: PMOS VCR310(comprising an inverter312, PMOS transistors311and313, and NMOS transistor314), NMOS VCR320(comprising an inverter322, PMOS transistor321, and NMOS transistors323and324), and a set of preset circuits230comprising PMOS transistor331for pulling the voltage at terminals VA to VDD when the clock from terminal CK[1] is low and NMOS transistors333for pulling down the voltages at VB to ground when the clock from terminal CK[2] is high. Besides, in an embodiment not shown in the figure due to purpose of brevity but will be obvious to those of ordinary skill in the art without explicitly showing the schematics, the voltages at circuit nodes315and325are pulled up to VDD via two PMOS transistors controlled by the clock from terminal CK[1], and the voltages at circuit nodes316and326are pulled down to ground via two NMOS transistors controlled by the clock from terminal CK[2]. VCR300further comprises an optional CMOS resistor340comprising a PMOS transistor341controlled by the clock from terminal CK[2] and an NMOS transistor342controlled by the clock from terminal CK[1]. During the preset phase where the clock CLK[1] is low and the clock CLK[2] is high (seeFIG. 1AandFIG. 1B), the clock at terminal CK[1] is low and the clock at terminal CK[2] is high (seeFIG. 2); in this phase, the voltage at VA is pulled up to VDD, the voltage at VB is pulled down to ground, and the PMOS transistor313, the NMOS transistor323, and the CMOS resistor340are all turned off and behave like an open circuit.

During the active phase where the clock CLK[1] is high and the clock CLK[2] is low (seeFIG. 1AandFIG. 1B), the clock at terminal CK[1] is high and the clock at terminal CK[2] is low (seeFIG. 2); in this phase, the present circuits330are disabled, and the PMOS VCR310, the NMOS VCR320, and the CMOS resistor340are all turned on and behave like a resistor with a resistance controlled by the voltage at terminal “VP” and the voltage at terminal “VN”. As illustrated inFIG. 1A, the “VP” and the “VN” terminals of VCR130interface with VC1and VC2respectively, while the “VP” and the “VN” terminals of VCR140interface with VC2and VC1respectively. In the active phase, a difference between VC1and VC2will result in a difference between the resistance of VCR130and the resistance of VCR140. As mentioned earlier, this will cause one of V3and V4to rise to VDD while the other fall to ground.

Reference is again made toFIG. 3. The PMOS VCR310and NMOS VCR320together form a “rail-to-rail” topology so that the voltage-controlled resistor300can work for a range of voltages at VP and VN that spans from the ground level to the supply level VDD. In a particular application, one may choose to remove NMOS VCR320along with the terminal “VN” at one's discretion if one is sure that a mean value of the voltage at VN is not lower than a voltage needed for turning on PMOS transistor321, and may choose to remove PMOS VCR310along with the terminal “VP” at one's discretion if one is sure that a mean value of the voltage at VP is not higher than a voltage needed for turning on NMOS transistor314. This concept of removing unnecessary circuits and terminals in a particular application is obvious to those of ordinary skill in the art and thus not described in detail here. Also, one may choose to remove PMOS transistor341, or NMOS transistor342, or both, at one's discretion.

Reference is made again toFIG. 1A. In the preset phase, by pulling up to VDD or pulling down to ground internal circuit nodes, VCR130and VCR140are preset so that I1and I2can be maximized upon entering the active phase. This helps to speed up the task of comparison. In the active phase, after a comparison between the resistance of VCR130and the resistance of VCR140is resolved, one of V3and V4will fall to ground while the other rise back to VDD. In any case, both I1and I2will be zero. Therefore, both objectives of relatively high-speed operation and low power consumption are fulfilled.