High-frequency amplifier circuitry and semiconductor device

High-frequency amplifier circuitry has a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential, a first switch to select whether to connect a first attenuator on an input signal path, a second switch to select whether to connect a first resistor between the input signal path and the first reference potential node, a third switch to select at least one of second resistors connected in parallel to the second inductor, and a fourth switch to select at least one of first capacitors connected in parallel on an output signal path connected to the drain of the second transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-124621, filed on Jun. 29, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the present disclosure relate to a high-frequency amplifier circuit and a semiconductor device.

BACKGROUND

In recent years, it has been considered to replace a fabrication process of a high-frequency low noise amplifier (LNA: Low Noise Amplifier) from an SiGe bipolar process (hereinafter, SiGe process) to an SOI (Silicon On Insulator) CMOS process (hereinafter, SOI process). The SOI process is lower in cost than the SiGe process and parasitic capacitance of an MOS transistor fabricated by the SOI process is small, so that power loss of a high frequency signal becomes small. Therefore, by using the SOI process, it is possible, without degrading electrical characteristics, to form a high frequency switch and a high-frequency low noise amplifier on the same SOI substrate, making one-chip configuration possible.

The LNA is often demanded to have a gain variable function. The specification of a plurality of gain modes may be defined in the wireless communication standards. In more specifically, an allowable range of reflection characteristics S11and S22, noise figure NF, and IIP3 (Input 3rd-order Intercept Point) may be defined in each gain mode. In a gain mode of a lower gain, it is not easier to make IIP3 fall into the allowable range. Moreover, as transmission phase discontinuity between gain modes, for example 20 degrees may be demanded. However, it is also not easy to satisfy the demand.

DETAILED DESCRIPTION

According to one embodiment, high-frequency amplifier circuitry has a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor to amplify further a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential, a first switch to select whether to connect a first attenuator on an input signal path from a node receiving the high-frequency input signal to a gate of the first transistor, a second switch to select whether to connect a first resistor between the input signal path and the first reference potential node, a third switch to select at least one of a plurality of second resistors connected in parallel to the second inductor, and a fourth switch to select at least one of a plurality of first capacitors connected in parallel on an output signal path connected to the drain of the second transistor.

Hereinbelow, embodiments will be explained with reference to the accompanying drawings. A part of the explanation in the specification and the accompanying drawings may be omitted, modified or simplified on the purpose of easy understanding and simplicity of the explanation. However, the technical contents to the extent that a similar function can be expected will be interpreted to be included in the embodiments. In the accompanying drawings of the present specification, for simplicity in drawings and easy understanding, the scale, the ratio of height to width, etc. are modified to be exaggerated from those of actual ones.

First Embodiment

A high-frequency amplifier circuit (hereinafter, LNA) according to a first embodiment is used in a wireless device2such as a mobile phone and a smart phone.FIG. 1is a block diagram schematically showing the configuration of a wireless device2having an LNA1according to a first embodiment built therein. The wireless device2ofFIG. 1is provided with an antenna3, an antenna switch4, a band-pass filter (BPF)5, the LNA1, a wireless IC (RFIC)6, a power amplifier (PA)7, and a low-pass filter (LPF)8.

The antenna switch4switches between transmission and reception.FIG. 1shows an example of a transmission side and a reception side each having one circuit system. However, the transmission side and the reception side may have a plurality of circuit systems for transmitting and receiving signals in a plurality of frequency bands, respectively. The antenna switch4and the LNA1ofFIG. 1can be arranged on the same SOI substrate to be formed into one chip. By arranging the antenna switch4and the LNA1ofFIG. 1on the SOI substrate, the reduction of power consumption and compactness become possible.

FIG. 2is a circuit diagram showing the internal configuration of the LNA1according to the first embodiment. The LNA1ofFIG. 2has a function of selecting any one of four gain modes G0to G3different in gain from one another. The gain is highest in the G0-mode, becoming lower in the order of G0→G1→G2→G3.

The LNA1ofFIG. 2is provided with a common-source first transistor Q1for amplifying a high-frequency input signal, a common-gate second transistor Q2for further amplifying a signal amplified by the first transistor Q1to generate an output signal, a bias generating circuit9, a first inductor Ls, a second inductor Ld, a first attenuator10, a first switch11, a first resistor Rsh23, a second switch12, a plurality of second resistors Rd0, Rd1and Rd2, a third switch13, a plurality of first capacitors Cout0, Cout1and Cout2, a fourth switch14, a second attenuator15, and a fifth switch16.

Although the first transistor Q1and the second transistor Q2ofFIG. 2are NMOS transistors, both can be configured with PMOS transistors in design. Nevertheless, since electrical characteristics are better in the form of NMOS, hereinafter, an example of the first transistor Q1and the second transistor Q2configured with NMOS transistors will be explained.

An input signal path is connected to the gate of the first transistor Q1. On the input signal path, an input terminal RFin, the first attenuator10, the first switch11, an externally-attached inductor (third inductor) Lext, and the first resistor Rsh23are connected.

The first switch11has first to third transistor switches SW1to SW3. The first transistor switch SW1is connected between the input terminal RFin and a node n1that is an end of the externally-attached inductor Lext. The second transistor switch SW2is connected between the input terminal RFin and an end of the first attenuator10. The third transistor switch SW3is connected between the other end of the first attenuator10and the node n1. To the gate of the first transistor switch SW1, a signal xG3, which becomes high in a gain mode other than the G3-mode, is input. The first transistor switch SW1turns on in a gain mode other than the G3-mode and turns off in the G3-mode. A signal G3which becomes high in the G3-mode is input to the gates of the second transistor switch SW2and the third transistor switch SW3. The second transistor switch SW2and the third transistor switch SW3turn on in the G3-mode and turn off in the G0- to G2-modes.

As described above, since the input and output of the first attenuator10are cut off in the G0- to G2-modes, the high-frequency input signal bypasses the first attenuator10by the first transistor switch SW1to be input to the externally-attached inductor Lext. The first attenuator10may be formed in a π-shape configuration as shown inFIG. 2or in a T-shape configuration.

The externally-attached inductor Lext is provided for impedance matching. A design is made so that the impedance viewed from the externally-attached inductor Lext to the input terminal RFin is 50Ω. The externally-attached inductor Lext can be formed on an SOI substrate, instead of being externally attached. In this case, however, a large pattern area is necessary, and hence it is highly likely that the inductor Lext is externally attached practically. Accordingly, in the present specification, the inductor Lext is referred to as an externally-attached inductor Lext. In the LNA1ofFIG. 2, the circuit components other than the externally-attached inductor Lext can be arranged on the SOI substrate. Practically, pads are provided to the node n1and to a node n2, and then the externally-attached inductor Lext is connected between these pads.

The first inductor Ls is connected between the source of the first transistor Q1and a ground node. To the gate of the first transistor Q1, a bias voltage VB1is supplied via an resistor RB1. A capacitor Cx is connected on an input signal path between the gate of the first transistor Q1and the node n2at the other end of the externally-attached inductor Lext. The capacitor Cx cuts D. C. components of a high-frequency input signal on the input signal path.

Between the node n2and a ground node, the first resistor Rsh23and the second switch12are connected in series. The second switch12has a fourth transistor switch SW4. A signal G23, which becomes high in the G2- or G3-mode, is input to the gate of the fourth transistor switch SW4. Therefore, the fourth transistor switch SW4turns on in the G2- or G3-mode and turns off in the other gain modes.

The first resistor Rsh23functions as a shunt resistor when the fourth transistor switch SW4in the second switch12is on. When the fourth transistor switch SW4is off, the first resistor Rsh23is cut off from the input signal path. Therefore, in the G2- or G3-mode, the first resistor Rsh23functions as the shunt resistor, and performs an operation of lowering the gain of the high-frequency input signal. In the G0- or G1-mode, the first resistor Rsh23does not perform the operation of lowering the gain of the high-frequency input signal.

A capacitor Cin, not shown, may be connected between the gate and source of the first transistor Q1. Since the source of the first transistor Q1is connected to the ground node via the first inductor Ls, the first transistor Q1acts as a common-source amplifier.

The externally-attached inductor Lext, the capacitors Cx and Cin, and the first inductor Ls constitute an input matching circuit. The element value of each component of the input matching circuit is set in consideration of gain matching and noise matching of the first transistor Q1.

To the gate of the second transistor Q2, a bias voltage VB2is supplied via a resistor RB2. A capacitor CB2is connected between the gate of the second transistor Q2and a ground node. Since the capacitance of the capacitor CB2and the resistance value of the resistor RB2are both large enough, the second transistor Q2acts as a common-gate amplifier.

Between the drain of the second transistor Q2and a first reference potential VDD_LNA, a second inductor Ld and the plurality of second resistors Rd0, Rd1and Rd2are connected in parallel, and a third switch13that selects at least one of the plurality of second resistors Rd0, Rd1and Rd2is provided.

The third switch13has a fifth transistor switch SW5and a sixth transistor switch SW6. The fifth transistor switch SW5is connected in series to the second resistor Rd1. The sixth transistor switch SW6is connected in series to the second resistor Rd2. The fifth transistor switch SW5turns on when a gate signal G1R is high. The gate signal G1R becomes high in the G1-mode. Therefore, the second resistor Rd1is connected in parallel to the second resistor Rd0and the second inductor Ld in the G1-mode. The sixth transistor switch SW6turns on when a gate signal G23R is high. The gate signal G23R becomes high in the G2- or G3-mode. Therefore, the second resistor Rd2is connected in parallel to the second resistor Rd0and the second inductor Ld in the G2- or G3-mode.

As described above, in the G0-mode, only the second resistor Rd0is connected in parallel to the second inductor Ld. In the G1-mode, the second resistors Rd0and Rd1are connected in parallel to the second inductor Ld. In the G2- or G3-mode, the second resistors Rd0and Rd2are connected in parallel to the second inductor Ld.

The plurality of second resistors Rd0, Rd1and Rd have a relation of Rd0>Rd1>Rd2in resistance value. Therefore, the resistance value of the second resistors connected in parallel to the second inductor Ld becomes maximum in the G0-mode, large in the G1-mode, and minimum in the G2- and G3-modes. As the resistance value of the second resistors is smaller, the gain of the output signal can be reduced.

Between the drain of the second transistor Q2and an output terminal RFout, the plurality of first capacitors Cout0, Cout1and Cout2are connected in parallel, and the fourth switch14that selects at least one of the plurality of first capacitors Cout0, Cout1and Cout2is provided. The fourth switch14has a seventh transistor switch SW7and an eighth transistor switch SW8. The seventh transistor switch SW7is connected in series to the first capacitor Cout1. The seventh transistor switch SW7turns on when a gate signal G1is high. The gate signal G1becomes high in the G1-mode. Therefore, the first capacitor Cout1is connected in parallel to the first capacitor Cout0in the G1-mode. The eighth transistor switch SW8is connected in series to the first capacitor Cout2. The eighth transistor switch SW8turns on when a gate signal G23is high. The gate signal G23becomes high in the G2- or G3-mode. Therefore, the first capacitor Cout2is connected in parallel to the first capacitor Cout0in the G2- or G3-mode.

Accordingly, the capacitance of the plurality of first capacitors Cout0, Cout1and Cout2in the G0- to G3-modes is the minimum Cout0in the G0-mode, Cout0+Cout1in the G1-mode, and Cout0+Cout2in the G2- and G3-modes, becoming larger in this order. By adjusting the combined capacitance of the plurality of first capacitors, the output matching in each gain mode can be optimized.

Since the LNA1according to the present embodiment is formed on the SOI substrate, the first inductor Ls and the second inductor Ld are formed in spiral inductors made of a spiral wiring pattern. Having large inductance as described above, the externally-attached inductor Lext is, not formed on the SOI substrate, but externally attached to the LNA1.

In the LNA1ofFIG. 1, the second attenuator15and the fifth switch16are connected between the first capacitor Cout0and the output terminal RFout. However, the second attenuator15and the fifth switch16may be omitted. The second attenuator15may be formed in a t-shape configuration or in a T-shape configuration, in the same manner as the first attenuator10.

The fifth switch16has a ninth transistor switch SW9and a tenth transistor switch SW10. The ninth transistor switch SW9is connected between a node n3that is one end of the first capacitor Cout and the output terminal RFout. The tenth transistor switch SW10is connected between the second attenuator15and a ground node. The ninth transistor switch SW9turns on when the signal xG3is high. The signal xG3becomes high in the modes other than the G3-mode. Therefore, the ninth transistor switch SW9turns on in the G0- to G2-modes to make the second attenuator15bypassed. The tenth transistor switch SW10turns on when a signal G3is high. The signal G3becomes high in the G3-mode. Therefore, the tenth transistor switch SW10connects the second attenuator15between the output signal path and the ground node in the G3-mode.

The bias generating circuit9generates the bias voltages VB1and VB2. The resistors RB1and RB2are provided to prevent the high-frequency input signal from being input to the bias generating circuit9. The bias voltage VB1is different in voltage value depending on the gain mode. Specifically, the voltage value of the bias voltages VB1and VB2are maximum in the G0- and G1-modes, large next to the maximum in the G2-mode, and minimum in the G3-mode.

FIG. 3is a figure showing the voltage values of the bias voltages VB1and VB2, and of the gate signals G1, G1R, G23, G23R, G3and xG3to be input to the gates of the first to tenth transistor switches SW1to SW10ofFIG. 2in the respective modes. As shown inFIG. 3, in the G0-mode, the bias voltage VB1and the bias voltage VB2are set to maximum VB1_G0and maximum VB2_G0, respectively. Moreover, in the G0-mode, the gates signals G1, G1R, G23, G23R, G3and xG3are set to −2 volts, 0 volts, −2 volts, 0 volts, −2 volts, and 3 volts, respectively. Therefore, the first transistor switch SW1turns on to make the first attenuator10bypassed. The first resistor Rsh23, which is a bypass resistor, is cut off from the input signal path. To the second inductor Ld, only the second resistor Rd0is connected in parallel. To the output signal path, only the first capacitor Cout0is connected. The second attenuator15is cut off from the output signal path. Accordingly, in the G0-mode, the high-frequency input signal is input to the gate of the first transistor Q1without being attenuated. The second resistors connected in parallel to the second inductor Ld have a maximum value. Therefore, a maximum gain can be obtained in the G0-mode.

The threshold voltage of each of the transistor switches SW1to SW10is 0 volts. There are two cases of applying 0 volts and −2 volts to the gates in turning off the transistor switches SW1to SW10. It is basically desirable to apply −2 volts to each gate because holes accumulated in the transistor body can be sucked into the gate. However, in the case where the drain of a transistor switch is connected to 1.8-volt power supply voltage, when the gate is at −2 volts, a voltage exceeding 3 volts is applied between the drain and gate, which exceeds a withstand voltage. For this reason, the gate is set at 0 volts when a high drain voltage is applied. InFIG. 2, a gate signal sign is followed by a sign “R” in the case of applying 0 volts to the gate of a transistor switch when the transistor switch is off. In the case where a gate signal sign is not followed by the sign “R”, −2 volts is applied to the gate of a transistor switch when the transistor switch is off.

In the G1-mode, as shownFIG. 3, the bias voltage VB1and the bias voltage VB2are set to VB1_G1and VB2_G1, respectively, each being a large value next to that in the G0-mode. The gate signals G1, G1R, G23, G23R, G3and xG3are set to 3 volts, 3 volts, −2 volts, 0 volts, −2 volts and 3 volts, respectively. Therefore, the first transistor switch SW1turns on to make the first attenuator10bypassed. The first resistor Rsh23is cut off from the input signal path. To the second inductor Ld, the second resistors Rd0and Rd1are connected in parallel. To the output signal path, the first capacitors Cout0and Cout1are connected in parallel. The second attenuator15is cut off from the output signal path. Accordingly, in the G1-mode, the high-frequency input signal is input to the gate of the first transistor Q1without being attenuated. The second resistors connected in parallel to the second inductor Ld have a small value next to that in the G0-mode. Therefore, in the G1-mode, a high gain next to that in the G0-mode can be obtained.

In the G2-mode, as shownFIG. 3, the bias voltage VB1and the bias voltage VB2are set to VB1_G2and VB2_G2, respectively, each being a large value next to that in the G1-mode. The gate signals G1, G1R, G23, G23R, G3and xG3are set to −2 volts, 0 volts, 3 volts, 3 volts, −2 volts and 3 volts, respectively. Therefore, the first transistor switch SW1turns on to make the first attenuator10bypassed. Moreover, the fourth transistor switch SW4turns on to connect the first resistor Rsh23between the input signal path and the ground node. To the second inductor Ld, the second resistors Rd0and Rd2are connected in parallel. To the output signal path, the first capacitors Cout0and Cout2are connected in parallel. The second attenuator15is cut off from the output signal path. Accordingly, in the G2-mode, the high-frequency input signal is attenuated by the first resistor Rsh23to be input to the gate of the first transistor Q1. The second resistors connected in parallel to the second inductor Ld have a small value next to that in the G1-mode. Therefore, in the G2-mode, a high gain next to that in the G1-mode can be obtained.

In the G3-mode, as shownFIG. 3, the bias voltage VB1and the bias voltage VB2are set to VB1_G3and VB2_G3, respectively, each being the minimum. The gate signals G1, G1R, G23, G23R, G3and xG3are set to −2 volts, 0 volts, 3 volts, 3 volts, 3 volts and −2 volts, respectively. Therefore, the first transistor switch SW1turns off while the second and third transistor switches SW2and SW3turn on, so that the high-frequency input signal, after being attenuated by the first attenuator10, passes through the externally-attached inductor Lext. The fourth transistor switch SW4turns on to connect the first resistor Rsh23between the input signal path and the ground node. Accordingly, the high-frequency input signal on the input signal path is attenuated further. To the second inductor Ld, the second resistors Rd0and Rd2are connected in parallel. On the output signal path, the first capacitors Cout0and Cout2are connected in parallel. Since the ninth transistor switch SW9turns off while the tenth transistor switch SW10turns on, the second attenuator15is connected between the output signal path and the ground node, to attenuate the output signal. Accordingly, in the G3-mode, the output signal has a minimum gain.

FIG. 4Ais a figure showing S-parameters of the LNA1ofFIG. 2in the G0-mode. InFIG. 4A, the abscissa is frequency [GHz] and the ordinate is S-parameter value [dB]. InFIG. 4A, curves cb1, cb2, cb3, and cb4represent input-side reflection characteristics S11, output-side reflection characteristics S22, transmission characteristics S21from the input side, and phase of S21, respectively.

FIG. 4Bis a figure showing noise figure NF of the LNA1ofFIG. 2in the G0-mode. InFIG. 4B, the abscissa is frequency [GHz] and the ordinate is noise figure NF.

InFIG. 4AandFIG. 4B, marks are put on 2.496 GHz, 2.593 GHz, and 2.690 GHz in a frequency range of Band 41 that is one of LTE (Long Term Evolution) bands. The LNA1according to the present embodiment is designed to be used in a frequency range of Band 41. As understood fromFIG. 4A, the S-parameters in the frequency range of Band 41 are satisfactory. For example, the gain at the band center frequency of 2.593 GHz is 18.0 dB, with S11and S22keeping generally-required standard values (−12 dB or lower).

FIGS. 5A to 7Aare figures showing S-parameters of the LNA1inFIG. 2in the G1- to G3-modes, respectively.FIGS. 5B to 7Bare figures showing noise figure NF of the LNA1inFIG. 2in the G1- to G3-modes, respectively. As understood from these figures, the gain lowers in the order of G0→G1→G2→G3. The LNA1ofFIG. 2is designed to have the gain of about 18 dB, about 15 dB, about 9 dB, and about −3 dB in the G0-, G1-, G2-, and G3-modes, respectively.

FIG. 8is a figure showing IIP3 of the LNA1inFIG. 2in the respective modes. InFIG. 8, the abscissa is input signal power Pin [dBm] and the ordinate is IIP3 [dBm]. As shown inFIG. 8, although lowering in the order of G3→G2→G1→G0, IIP3 keeps a value sufficiently larger than a generally-required value. Especially, in the G3-mode, IIP3 shows a value that is 3.3 dB larger than a generally-required value of 12 dBm.

FIG. 9is a figure showing a result of simulation in the G0- to G3-modes.FIG. 9shows, in each gain mode, a bias current Idd_Ina [mA], a band center value [dB] of S21, a band center value [dB] of noise figure NF, the worst value [dB] in Band 41 of S11, the worst value [dB] in Band 41 of S22, a band center value [dBm] of IIP3, and the phase [deg] of S21.

From S21-phase inFIG. 9, the inter-gain mode maximum phase discontinuity [deg] is 10.57. It is found that this value has an enough margin to a generally-required value of 20 [deg].

As described above, according to the first embodiment, in the LNA1having a plurality of gain modes, the input signal path is connected to the ground node by means of the shunt resistor Rsh23when the G3-mode of the minimum gain is selected, so that IIP3 can be improved.

Second Embodiment

A second embodiment is different from the first embodiment in shunt resistor circuit configuration.

FIG. 10is a circuit diagram of an LNA1according to the second embodiment. InFIG. 10, the components equivalent to those ofFIG. 2are given the same signs. In the following, the different points will be mainly explained. The LNA1ofFIG. 2is provided with the first resistor Rsh23that functions as a shunt resistor in the G2- and G3-modes. In contrast, the LNA1ofFIG. 10is provided with a first resistor Rsh2that functions as a shunt resistor in the G2-mode, a first resistor Rsh3that functions as a shunt resistor in the G3-mode, and a second capacitor Csh3connected in parallel to the first resistor Rsh3.

To the first resistor Rsh2, an eleventh transistor switch SW11is connected in series, and to the first resistor Rsh3, a twelfth transistor switch SW12is connected in series. The eleventh transistor switch SW11turns on when a signal G2is high. The twelfth transistor switch SW12turns on when a signal G3is high. Therefore, in the G2-mode, the first resistor Rsh2is connected between the input signal path and the ground node. In the G3-mode, the first resistor Rsh3and the second capacitor Csh3are connected in parallel between the input signal path and the ground node.

According to the examination of the present inventor, it is found that IIP3 in the G3-mode becomes higher by connecting the second capacitor Csh3in parallel to the first resistor Rsh3. Accordingly, according to the LNA1ofFIG. 10, IIP3 in the G3-mode can be made higher than that in the LNA1ofFIG. 1.

As described above, since the LNA1ofFIG. 10has the shunt resistor Rsh2only for the G2-mode, and the shunt resistor Rsh3and the second capacitor Csh3only for the G3-mode, IIP3 in the G2- and G3-modes can be optimized.

FIG. 11is a circuit diagram of an LNA1according to a modification example of that inFIG. 10. The LNA1ofFIG. 11is configured by adding a non-linearity compensation circuit17and a sixth switch18to the LNA1ofFIG. 10. The non-linearity compensation circuit17ofFIG. 11is connected to a connection node of the first transistor Q1and the second transistor Q2. In other words, the non-linearity compensation circuit17is connected to the drain of the first transistor Q1and to the source of the second transistor Q2. To the non-linearity compensation circuit17, the first reference potential VDD_LNA and the ground node are connected. Since it is enough for the non-linearity compensation circuit17to be connected between two reference potentials, the non-linearity compensation circuit17may be connected between a third reference potential other than VDD_LNA and a fourth reference potential other than the ground potential.

The non-linearity compensation circuit17is connected to the connection node of the first transistor Q1and the second transistor Q2to compensate for non-linearity of an output signal to a high-frequency input signal. The sixth switch18selects whether to make effective the non-linearity compensation circuit17that compensates for non-linearity of the output signal output from the output signal path to the high-frequency input signal.

The non-linearity compensation circuit17has a first rectifier circuitry19, a second rectifier circuitry20, a resistor R1A, a resistor R1B, a third capacitor C1A, and a fourth capacitor C1B. The sixth switch18has a thirteenth transistor switch SW13.

The first rectifier circuitry19and the resistor R1A are connected in series between the first reference potential VDD_LNA and the drain of the thirteenth transistor switch SW13. The resistor R1B and the second rectifier circuitry20are connected in series between the first reference potential VDD_LNA and the drain of the thirteenth transistor switch SW13.

The connection node of the first rectifier circuitry19and the resistor R1A is connected, via the third capacitor C1A, to the connection node of the first transistor Q1and the second transistor Q2. Likewise, the connection node of the resistor R1B and the second rectifier circuitry20is connected, via the fourth capacitor C1B, to the connection node of the first transistor Q1and the second transistor Q2.

The thirteenth transistor switch SW13turns on when a signal G01is high to make an end of the resistor R1A and an end of the second rectifier circuitry20conductive to the ground node. Therefore, in the G0- and G1-modes, the non-linearity compensation circuit17compensates for non-linearity of the output signal to the high-frequency input signal. In the G2- and G3-modes, the non-linearity compensation circuit17is cut off.

The first rectifier circuitry19has a diode-connected third transistor Q3. The second rectifier circuitry20has a diode-connected fourth transistor Q4. To the drain and gate of the third transistor Q3, the first reference potential VDD_LNA is connected, and to the source of the third transistor Q3, an end of the resistor R1A is connected. To the drain and gate of the fourth transistor Q4, an end of the resistor R1B is connected, and to the source of the third transistor Q3, the ground node is connected.

The third transistor Q3and the fourth transistor Q4have the same device constants. The device constants are various parameters such as a gate width, a gate length, a threshold voltage, and a gate-oxide film thickness, which define the transistor electrical characteristics. The resistors R1A and R1B have the same resistance value. The third capacitor C1A and the fourth capacitor C1B have the same capacity.

As described above, the non-linear compensation circuit17is provided with two series circuits each configured with of a transistor and a resistor, in a reverse order of transistor-resistor connection, vice versa, in these series circuits. According to this configuration, even-order intermodulation distortion can be canceled.

Moreover, in the non-linear compensation circuit17according to the present embodiment, in order to have high IIP3 as much as possible in the G0- and G1-modes, at least one of the device constants of the third transistor Q3and the fourth transistor Q4, the resistance values of the resistors R1A and R1B, and the capacitance of the third capacitor C1A and the fourth capacitor C1B can be adjusted. According to the adjustment, IIP3 can be raised without reducing the gain and noise figure so much.

FIG. 12is a figure showing the voltage values of the bias voltages VB1and VB2, and of the gate signals G1, G1R, G01, G23, G23R, G3and xG3to be input to the gates of the first to tenth transistor switches SW1to SW13of the LNA1inFIG. 11in the respective modes. InFIG. 12, compared toFIG. 3, logics for a signal G01and G2are added. The thirteenth transistor switch SW13, to which the signal G01is input, turns on in the G0- and G1-modes.

FIGS. 13A to 16Aare figures showing S-parameters of the LNA1inFIG. 11in the G0- to G3-modes, respectively.FIGS. 13B to 16Bare figures showing noise figure NF of the LNA1inFIG. 11in the G0- to G3-modes, respectively.

FIG. 17is a figure showing a result of simulation for the LNA1ofFIG. 11in the G0- to G3-modes. As understood from S21-phase inFIG. 17, the inter-gain mode maximum phase discontinuity [deg] is 9.76 which is smaller than that inFIG. 9.

FIG. 18is a figure graphing IIP3 in the respective gain modes shown inFIG. 17. InFIG. 18, the abscissa is gain mode and the ordinate is IIP3 [dBm]. As shown, by providing the non-linearity compensation circuit17, IIP3 becomes higher in the G0- and G1-modes. Moreover, since there are provided the first resistor Rsh3, which is a shunt resistor, only for the G3-mode and the second capacitor Csh3connected in parallel to the first resistor Rsh3, IIP3 becomes higher further in the G3-mode.

The non-linearity compensation circuit17provided to the LNA1ofFIG. 11may be added to the LNA1ofFIG. 2.FIG. 19is a circuit diagram configured by adding a non-linearity compensation circuit17of the same circuit configuration as that ofFIG. 11to the LNA1ofFIG. 2. According to the LNA1ofFIG. 19, IIP3 can be raised further in the G0- and G1-modes, in the same manner as the LNA1ofFIG. 11.

As described above, in the second embodiment, since the second capacitor Csh3is connected in parallel to the first resistor Rsh3, which is a shunt resistor, connected between the input signal path, which is connected to the gate of the first transistor Q1, and the ground node, IIP3 can be raised further in the G3-mode.

Moreover, in the second embodiment, since the non-linearity compensation circuit17is connected to the connection node of the first transistor Q1and the second transistor Q2to compensate for non-linearity of the output signal to the high-frequency input signal in the G0- and G1-modes, IIP3 can be raised further in the G0- and G1-modes.

Third Embodiment

A third embodiment selects whether to connect a fifth resistor in parallel to the externally-attached inductor Lext.

FIG. 20is a circuit diagram of an LNA1according to the third embodiment. In the LNA1ofFIG. 20, the components equivalent to those of the LNA1ofFIG. 10are given the same signs. In the following, the different points will be mainly explained. The LNA1ofFIG. 20is provided with a seventh switch21that selects whether to connect a fifth resistor Rt in parallel to the externally-attached inductor Lext. The seventh switch21is a fourteenth transistor switch SW14that connects the fifth resistor Rt in parallel to the externally-attached inductor Lext when a signal G3is high. In other words, in the G3-mode, the fifth resistor Rt is connected in parallel to the externally-attached inductor Lext whereas, in the G0- to G2-modes, the fifth resistor Rt is cut off, so that the externally-attached inductor Lext is left alone.

According to the examination of the present inventor, it is found that, by connecting the fifth resistor Rt in parallel to the externally-attached inductor Lext in the G3-mode, the input impedance varies to raise IIP3 further. Accordingly, the seventh switch21ofFIG. 20connects the fifth resistor Rt in parallel to the externally-attached inductor Lext only in the G3-mode.

FIG. 21is a circuit diagram configured by adding a non-linearity compensation circuit17of the same circuit configuration as that ofFIG. 11to the LNA1ofFIG. 20. The non-linearity compensation circuit17ofFIG. 21compensates for non-linearity of an output signal to a high-frequency input signal in the G0- to G2-modes. Accordingly, IIP3 becomes higher further in the G0- to G2-modes. The non-linearity compensation circuit17in the LNA1ofFIG. 11compensates for non-linearity only in the G0- and G1-modes. This is because a compensation effect is not so obtained in the G2-mode. Therefore, the non-linearity compensation circuit17ofFIG. 21may also compensate for non-linearity only in the G0- and G1-modes in the same manner as inFIG. 11. Or, conversely, the non-linearity compensation circuit17ofFIG. 11may compensate for non-linearity in the G0- to G2-modes.

FIG. 22is a figure showing the voltage values of the bias voltages VB1and VB2, and of the gate signals G1, G1R, G01, G23, G23R, G3and xG3to be input to the gates of the first to tenth transistor switches SW1to SW13of the LNA1inFIG. 21in the respective modes. The truth table ofFIG. 22is made by omitting the signal G01fromFIG. 12.

FIGS. 23B to 26Bare figures showing noise figure NF of the LNA1inFIG. 21in the G0- to G3-modes, respectively.

FIG. 27is a figure showing a result of simulation for the LNA1ofFIG. 21in the G0- to G3-modes. As understood from S21-phase inFIG. 27, the inter-gain mode maximum phase discontinuity [deg] is 12.8, which is larger than that inFIG. 17, however, practically not a problematic value.

FIG. 28is a figure graphing IIP3 in the respective gain modes shown inFIG. 27. InFIG. 28, the abscissa is gain mode and the ordinate is IIP3 [dBm]. The IIP3 in the G3-mode is 15.6 dBm which is lower than 20.3 dBm shown inFIG. 17. It is, however, noted thatFIG. 27shows a smaller bias current Idd_Ina. In other words, in the third embodiment, satisfactory IIP3 can be obtained even though the bias current Idd_Ina is small.

As described above, in the third embodiment, by connecting the fifth resistor Rt in parallel to the externally-attached inductor Lext in the G3-mode, satisfactory IIP3 can be obtained to a small current Idd_Ina.

Fourth Embodiment

A fourth embodiment is provided with a circuit (hereinafter, referred to as a first IIP3 improving circuitry) that selects whether to connect a series circuit of a resistor and a capacitor between the gate of the first transistor Q1and the ground node.

FIG. 29is a circuit diagram of an LNA1according to the fourth embodiment. The LNA1ofFIG. 29has a circuit configuration made by adding a first IIP3 improving circuitry22to the LNA1ofFIG. 2. The first IIP3 improving circuitry22has an eighth switch23that selects whether to connect a series circuit of a fifth capacitor Cx3and a sixth resistor Rb3connected in series between the gate of the first transistor Q1and the ground node.

The eighth switch23is a fifteenth transistor switch SW15that turns on when a signal G3is high. When the fifteenth transistor switch SW15turns on, the fifth capacitor Cx3and the sixth resistor Rb3are connected in series between the gate of the first transistor Q1and the ground node.

By optimizing the capacitance of the fifth capacitor Cx3and the resistance value of the sixth resistor Rb3of the first IIP3 improving circuitry22in the G3-mode, IIP3 can be raised further.

FIG. 30is a circuit diagram of an LNA1configured by adding a non-linearity compensation circuit17of the same circuit configuration as that ofFIG. 11to the LNA1ofFIG. 29. The non-linearity compensation circuit17ofFIG. 30compensates for non-linearity of the output signal in the G0- to G2-modes.

As described above, in the LNA1ofFIG. 29, the non-linearity compensation circuit17can raise further IIP3 in the G0- to G2-modes, and the first IIP3 improving circuitry22can raise IIP3 further in the G3-mode.

FIG. 31is a figure showing the voltage values of the bias voltages VB1and VB2, and of the gate signals G1, G1R, G23, G23R, G3and xG3to be input to the gates of the first to tenth transistor switches SW1to SW15of the LNA1inFIG. 30in the respective modes. The voltage value of each gate signal in each gain mode ofFIG. 31is the same as that ofFIG. 22.

FIGS. 32A to 35Aare figures showing S-parameters of the LNA1inFIG. 30in the G0- to G3-modes, respectively.FIGS. 32B to 35Bare figures showing noise figure NF of the LNA1inFIG. 30in the G0- to G3-modes, respectively.

FIG. 36is a figure showing a result of simulation for the LNA1ofFIG. 30in the G0- to G3-modes. As understood from S21-phase inFIG. 36, the inter-gain mode maximum phase discontinuity [deg] is 10.44, which is larger than that inFIG. 17, however, practically not a problematic value.

FIG. 37is a figure graphing IIP3 in the respective gain modes shown inFIG. 36. InFIG. 37, the abscissa is gain mode and the ordinate is IIP3 [dBm]. InFIG. 37, a solid line with circular marks indicates IIP3 of the LNA1inFIG. 30in each gain mode and a solid line with triangular marks indicates IIP3 of an LNA1in one modification example configured by removing the non-linearity compensation circuit17and the first IIP3 improving circuitry22from the LNA1ofFIG. 30. As shown, it is found that, by providing the non-linearity compensation circuit17and the first IIP3 improving circuitry22, IIP3 can be raised further in each gain mode.

As described above, in the fourth embodiment, since the fifth capacitor Cx3and the sixth resistor Rb3are connected in series between the gate of the first transistor Q1and the ground node in the G3-mode, IIP3 in the G3-mode can be raised further.

Fifth Embodiment

A fifth embodiment raises IIP3 in the G3-mode further by using an ESD (Electro-Static Discharge) protection circuitry connected to the gate of the first transistor Q1.

FIG. 38is a circuit diagram of an LNA1according to the fifth embodiment. The LNA1ofFIG. 38has a circuit configuration made by adding a second IIP3 improving circuitry24to the LNA1ofFIG. 2. An ESD protection circuitry25may be connected between the input signal path, which is connected to the gate of the first transistor Q1, and the source of the first transistor Q1. The second IIP3 improving circuitry24utilizes the ESD protection circuit25for the purpose of improving IIP3 in the G3-mode.

The ESD protection circuitry25has a first diode pair26having anodes and cathodes connected in parallel in a reverse direction and a second diode pair27having anodes and cathodes connected in parallel also in a reverse direction. The first diode pair26and the second diode pair27are connected in series between the input signal path, which is connected to the gate of the first transistor Q1, and the source of the first transistor Q1. In detail, one end of the first diode pair26is connected to the node n2and the other end of the first diode pair26is connected to an end of the second diode pair27, and the other end of the second diode pair27is connected to the source of the first transistor Q1. Since the first diode pair26has a larger junction area than the second diode pair27, the first diode pair26functions as a capacitor equivalently.

Moreover, a ninth switch28, which selects whether the second IIP3 improving circuitry24improves IIP3, is connected between the other end of the first diode pair26and the ground node.

The ninth switch28has a sixteenth transistor switch SW16that becomes high in the G3-mode. When the sixteenth transistor switch SW16becomes high, a seventh resistor Rsh3is connected between the other end of the first diode pair26and the ground node. In the G0- to G2-modes, the seventh resistor Rsh3is cut off. Therefore, in the G0- to G2-modes, the first diode pair26and the second diode pair27merely function as the ESD protection circuitry25.

The first diode pair26is a high impedance circuit to function as a capacitor equivalently. Therefore, when the sixteenth transistor switch SW16in the ninth switch28is on, a circuit of the capacitor and the seventh resistor Rsh3connected in series is provided between the gate of the first transistor Q1and the ground node. Accordingly, IIP3 can be raised further in the same manner as the first IIP3 improving circuitry22ofFIG. 29.

FIG. 39is a circuit diagram of an LNA1configured by connecting a non-linearity compensation circuit17having the same circuit configuration as that ofFIG. 11to the LNA1ofFIG. 38. The non-linearity compensation circuit17ofFIG. 39compensates for non-linearity of the output signal in the G0- to G2-modes.

As described above, in the LNA1ofFIG. 39, the non-linearity compensation circuit17can raise IIP3 in the G0- to G2-modes further and the second IIP3 improving circuitry24can raise IIP3 in the G3-mode further.

FIG. 40is a figure showing the voltage values of the bias voltages VB1and VB2, and of the gate signals G1, G1R, G23, G23R, G3and xG3to be input to the gates of the first to tenth transistor switches SW1to SW16of the LNA1inFIG. 39in the respective modes. The voltage value of each gate signal in each gain mode is the same as that ofFIG. 22.

FIGS. 41A to 44Aare figures showing S-parameters of the LNA1inFIG. 39in the G0- to G3-modes, respectively.FIGS. 41B to 44Bare figures showing noise figure NF of the LNA1inFIG. 39in the G0- to G3-modes, respectively.

FIG. 45is a figure showing a result of simulation for the LNA1ofFIG. 39in the G0- to G3-modes. As understood from S21-phase inFIG. 45, the inter-gain mode maximum phase discontinuity [deg] is 9. 88 which is sufficiently small.

FIG. 46is a figure graphing IIP3 in the respective gain modes shown inFIG. 45. InFIG. 46, the abscissa is gain mode and the ordinate is IIP3 [dBm]. InFIG. 46, a solid line with circular marks indicates IIP3 of the LNA1inFIG. 39in each gain mode and a solid line with triangular marks indicates IIP3 of an LNA1in one modification example configured by removing the non-linearity compensation circuit17and the second IIP3 improving circuitry24from the LNA1ofFIG. 39. As shown, it is found that, by providing the non-linearity compensation circuit17and the second IIP3 improving circuitry24, IIP3 can be raised further in each gain mode.

As described above, in the fifth embodiment, since the second IIP3 improving circuitry24is configured by using the general ESD protection circuitry25connected to the gate of the first transistor Q1, IIP3 in the G3-mode can be raised further, without increasing circuit scale so much.

Sixth Embodiment

Recent mobile communication equipment often performs wireless communication using a carrier aggregation technique for wireless communication utilizing a plurality of bands. In this case, it is required to arrange a plurality of LNAs1and a plurality of band selector switches on an SOI substrate.FIG. 47is a block diagram schematically showing the configuration of a wireless device2conforming to carrier aggregation.FIG. 47shows a block diagram of a reception circuit for signal reception from an antenna3. The block diagram of a transmission circuit is the same as that ofFIG. 1.

The wireless device2ofFIG. 47is provided with an antenna switch4, a plurality of band-pass filters5, a plurality of band selector switches29, and a plurality of LNAs1. The plurality of band selector switches29and the plurality of LNAs1are arranged on the same SOI substrate, which can be formed into one chip, or may be arranged on the same SOI substrate together with the antenna switch4to be formed into one chip.

The plurality of LNAs1ofFIG. 47each are the LNA1according to any one of the first to fifth embodiments. A reception signal at each frequency switched by the antenna switch4is, after passing through the corresponding band-pass filter5, input to the corresponding band selector switch29. An input signal selected by the band selector switch29is input to the corresponding LNA1to be amplified in a gain mode in any one of the G0- to G3-modes.

By arranging the plurality of band selector switches29and the plurality of LNAs1on the SOI substrate, compactness and low power consumption are possible.

Although, in the above-described first to sixth embodiments, the examples of arrangement of LNA1on the SOI substrate are explained, the LNA1according to the above-described first to sixth embodiments may be disposed on a bulk silicon substrate. Even in the LNA1disposed on the bulk silicon substrate, by providing the above-described non-linear compensation circuit17, shunt resistors, IIP3 improving circuitry, etc., it is possible to raise IIP3 further.