Air-gap formation in interconnect structures

A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps.

BACKGROUND

As the semiconductor industry introduces new generations of integrated circuits (ICs) having higher performance and greater functionality, the density of the elements that form the ICs is increased, while the dimensions and spacing between components or elements of the ICs are reduced. In the past, such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having smaller dimensions created new limiting factors. For example, for any two adjacent conductive features, when the distance between the conductive features decreases, the resulting capacitance (a function of the dielectric constant (k value) of the insulating material divided by the distance between the conductive features) increases. The increased capacitance results in an increased capacitive coupling between the conductors, increased power consumption, and an increase in the resistive-capacitive (RC) time constant. Therefore, the continual improvement in semiconductor IC performance and functionality is dependent upon developing materials with low k values.

Since the substance with the lowest dielectric constant is air (k=1.0), low-k dielectric materials typically comprise porous materials. Also, air-gaps are formed to further reduce the effective k value of interconnect structures.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

An interconnect structure that comprises air gaps therein and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the interconnect structure are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1illustrates wafer10, which includes semiconductor substrate12. In some embodiments, semiconductor substrate12is a bulk semiconductor substrate. In alternative embodiments, semiconductor substrate12is a Semiconductor-On-Insulator (SOI) substrate. The semiconductor material in semiconductor substrate12may comprise silicon, silicon germanium, silicon carbon, a III-V compound semiconductor material, and/or the like. In some embodiments, integrated circuits14are formed at a top surface of semiconductor substrate12. Integrated circuits14may include active devices such as transistors.

Over integrated circuit14is dielectric layer20, and conductive line22formed in dielectric layer20. Dielectric layer20may be an Inter-Layer Dielectric (ILD) layer or an Inter-Metal Dielectric (IMD) layer, and may have a low dielectric constant (k value) lower than about 2.5, for example. Conductive line22may include conductive barrier layer16and metal line18over barrier layer16. In some embodiments, barrier layer16comprises titanium, titanium nitride, tantalum, tantalum nitride, copper manganese, alloys thereof, and/or multi-layers thereof. Metal line18may comprise copper, tungsten, aluminum, nickel, and/or alloys thereof. Conductive line22may be electrically coupled to integrated circuits14, and may serve as the interconnection between the devices in integrated circuits14.

Etch Stop Layer (ESL)24is formed over dielectric layer20and conductive line22. ESL24may comprise a nitride, a silicon-carbon based material, a carbon-doped oxide, and/or combinations thereof. The formation methods include Plasma Enhanced Chemical Vapor Deposition (PECVD) or other methods such as High-Density Plasma CVD (HDPCVD), Atomic Layer CVD (ALCVD), and the like. In alternative embodiments, dielectric layer24is a diffusion barrier layer that is used for preventing undesirable elements, such as copper, from diffusing through. In further embodiments, dielectric layer24acts as both an etch stop layer and a diffusion barrier layer.

FIG. 1also illustrates the formation of low-k dielectric layer26, which provides insulation between conductive line22and the overlying conductive lines that will be formed subsequently. Low-k dielectric layer26is sometimes referred to as an Inter-Metal Dielectric (IMD) layer. Low-k dielectric layer26may have a k value lower than about 3.5, or lower than about 2.5. The materials comprised in low-k dielectric layer26may include a carbon-containing material, organo-silicate glass, a porogen-containing material, and/or combinations thereof. Low-k dielectric layer26may be deposited using PECVD, although other commonly used deposition methods, such as Low Pressure CVD (LPCVD), ALCVD, and spin-on, can also be used.

Hard mask layer28is formed over low-k dielectric layer26. Hard mask layer28may be a dielectric layer. In some embodiments, hard mask layer28comprises silicon nitride, silicon carbide, titanium nitride, or the like. Photo resist30is formed over hard mask layer28, and is then patterned. It is appreciated that although one photo resist30is illustrated, in alternative embodiments, a plurality of layers may be included, which includes, and is not limited to, a bottom layer (such as a carbon-containing material), a middle layer (such as a silicon-containing material, for example), an anti-reflective coating, and/or the like.

FIG. 2illustrates the formation of via opening32in low-k dielectric layer26. The formation of via opening32includes etching hard mask28(FIG. 1), and then etching low-k dielectric layer26using the patterned hard mask28as an etching mask. ESL24is then etched to expose the underlying conductive line22.

Next, as also shown inFIG. 2, conductive barrier layer34is formed. Conductive barrier layer34extends into via opening32, and includes a portion over low-k dielectric layer26. Conductive barrier layer34also has a bottom portion contacting the top surface of conductive line22. Barrier layer34may prevent the copper in the subsequently formed conductive material36(FIG. 3) from diffusing into low-k dielectric layer26. In some embodiments, conductive barrier layer34is formed of a conductive material comprising titanium, titanium nitride, tantalum, tantalum nitride, copper manganese, alloys thereof, or multi-layers thereof.

Referring toFIG. 3, conductive material36is formed. In some embodiments, conductive material36comprises copper, and may be formed of either substantially pure copper or a copper compound. Conductive material36is hence accordingly referred to as a copper-comprising material, although conductive material36may also be a non-copper material comprising aluminum, tungsten, and/or the like. The top surface of conductive material36is higher than the top surface of conductive barrier layer34. The formation of copper-comprising material36may include plating, Metal Organic Chemical Vapor Deposition (MOCVD), or the like. A planarization may be performed to flatten the top surface of copper-comprising material36. Next, hard mask38, which may be formed of a material selected from the same group of candidate materials of hard mask28, is formed over copper-comprising material36.

FIG. 4illustrates the formation and the patterning of photo resist40. Similar to photo resist30inFIG. 1, the illustrated photo resist40may represent a plurality of layers including, and not limited to, a bottom layer, a middle layer, an anti-reflective coating, and/or the like. Next, the pattern of photo resist40is transferred to the underlying hard mask38, and then to copper-comprising material36and to barrier34, followed by the removal of photo resist40and hard mask38. The portions of barrier34exposed to the openings in photo resist40are thus removed. The resulting structure is shown inFIG. 5. The patterning of copper-comprising material36may be performed by etching. Dielectric barrier layer44is then formed, for example, by deposition. Dielectric barrier layer44may be formed of a dielectric material, which may comprise silicon nitride, silicon carbide, silicon oxynitride, carbon nitride, carbon oxide, combinations thereof, and/or multi-layers thereof. After the patterning of copper-comprising material36, a portion of copper-comprising material36in low-k dielectric layer26forms via46along with the contacting portion of conductive barrier layer34. The portion of copper-comprising material36(that is over low-k dielectric layer26) and the respective contacting dielectric barrier layer44form metal lines48.

Referring toFIG. 6, decomposable layer50is formed over metal lines48, and in the spaces49(also referred to as openings49) between metal lines48. In some embodiments, decomposable layer50includes a polymer that may decompose and vaporize when exposed to Ultra-Violet light and/or heated to an elevated temperature, for example, between 250° C. and 500° C. Exemplary materials of decomposable layer50include P (neopentul methacrylate-co-ethylene glycol dimethacrylate) copolymer, polypropylene glycol (PPG), polybutadine (PB), polyethylene glycol (PEG), polycaprolactone diol (PCL), fluorinated amorphous carbon (a-FiC), silicon gel and/or organic silaxone. Decomposable layer50may be formed by spin coating or a deposition process such as a Chemical Vapor Deposition (CVD) process. Alternatively, decomposable layer50is formed using Plasma Enhanced Atomic Layer Deposition (PEALD) at a low temperature, for example, between about 30° C. and about 50° C. The PEALD may result in a good conformal profile for decomposable layer50.

Decomposable layer50may be formed as a conformal layer, wherein thickness T1 of the vertical portions of decomposable layer50is close to thickness T2 of the horizontal portions of decomposable layer50. Ratio T1/T2 may also be between about 0.7 and about 1, between about 0.8 and about 1, or between about 0.9 and about 1. Thicknesses T1 and T2 may be between about 5 nm and about 20 nm in some exemplary embodiments. It is appreciated, however, that the values recited throughout the description are merely examples, and may be changed to different values.

Decomposable layer50is then etched. The horizontal portions of decomposable layer50are removed, and the vertical portions of decomposable layer50on the sidewalls of metal lines48are left, forming decomposable spacers52, as shown inFIG. 7. The etching may be an anisotropic etching, and may be a dry etching, for example. As a result of the anisotropic etching, the upper portions52A of decomposable spacers52may have a tapered profile, with lower thicknesses of decomposable spacers52greater than upper widths. Decomposable spacers52may also have lower portions52B that have substantially vertical sidewalls.

Next, inFIG. 8, low-k dielectric material54is formed. Low-k dielectric material54may have a k value lower than about 3.0, or lower than about 2.5, and may be formed of carbon-containing low-k dielectric materials, for example. Low-k dielectric material54is porous. Openings49(FIG. 7) between metal lines48are filled with lower portions of low-k dielectric material54. Furthermore, low-k dielectric material54may include an upper portion over and contacting dielectric barrier layer44, which are top surface portions of metal lines48. The lower portions and the upper portions of low-k dielectric material54are formed in a same formation process, and hence there is no visible interface therebetween. Low-k dielectric material54may be formed using spin-on coating to take the advantage of its good gap filling capability, so that trenches49are filled with substantially no void therein, and the upper portion of low-k dielectric material54may have a substantially planar top surface.

As shown inFIG. 9A, decomposable spacers52are decomposed and turned into a vapor with molecules small enough to diffuse through the pores of low-k dielectric material54. Air-gaps56are thus formed. The decomposition and vaporization may be performed through an UV exposure and/or a heating process at an elevated temperature. In some exemplary embodiments, decomposable spacers52include decomposable layer50that includes P (neopentul methacrylate-co-ethylene glycol dimethacrylate) copolymer. The vaporization may thus be performed with a UV exposure, and the corresponding heating temperature may be between about 250° C. and about 500° C.

As a result of the vaporization, air gaps56are formed. Air gaps56may have essentially the same profile as that of decomposable spacers52inFIG. 8, for example, having the tapered upper portions, and lower portions having substantially vertical sidewalls. Low-k dielectric material54comprises edges exposed to air gaps56. Furthermore, some vertical portions of conductive barrier layer34may be exposed to air gaps56. The top ends of air gaps56may be substantially level with, or lower than, the top surfaces of metal lines48. Low-k dielectric material54includes a lower portion between metal lines48, and an upper portion over the lower portion of low-k dielectric material54and metal lines48. At the level lower than and close to the level of the top surfaces of metal lines48, the lower portion of low-k dielectric material54may have a tapered profile, and have lower widths W2 increasingly greater than the respective upper widths W1.

FIG. 9Billustrates a top view of the structure inFIG. 9A. It is shown that each of air gaps56may form a continuous air gap ring encircling one of metal lines48. In the top-view, low-k dielectric material54further encircles air gap rings56.

FIG. 10illustrates additional via60over metal lines48and in low-k dielectric material54, and metal lines62over via60in low-k dielectric material64. Via60is electrically coupled to the respective underlying metal line48. Air gaps66may be formed on the sidewalls of, and encircle, metal lines62. The formation processes may be essentially the same as inFIGS. 2 through 9A, and are not repeated herein.

In the previously discussed embodiments, the metal lines and the underlying vias are formed simultaneously. Similar process and materials as discussed in the embodiments can also be adopted in the formation of metal lines with no underlying vias. For example, as shown inFIG. 10, air gaps68may also be formed to encircle conductive line22. The formation process may be realized through the teaching of the embodiments.

In the embodiments, air gaps are formed in the interconnect structures. Since air gaps have a k value equal to 1, the equivalent k value of the dielectric material in the interconnect structures is lowered, resulting in a reduction in the parasitic capacitance between metal lines48(FIG. 10). The formation of the air gaps is uniform and controllable, and does not suffer from the permeable (porous) hard mask collapsing problem that may occur in conventional methods for forming the air gaps.

In accordance with embodiments, a structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps.

In accordance with other embodiments, a structure includes a substrate, and a metal line over the substrate. The metal line includes a copper-containing line, and a dielectric barrier layer having a top portion over and contacting the first metal line, and an edge portion contacting a sidewall of the first metal line. An air gap encircles the metal line, wherein the edge portion of the dielectric barrier layer is exposed to the air gap. A low-k dielectric region has a sidewall exposed to the first air gap.

In accordance with yet other embodiments, a method includes forming a conductive region, etching the conductive region to form an opening in the conductive region, and forming a decomposable layer. The decomposable layer includes a top portion over the conductive region, a sidewall portion on a sidewall of the conductive region, and a bottom portion at a bottom of the opening. The decomposable layer is etched to remove the top portion and the bottom portion of the decomposable layer. A low-k dielectric layer is formed in a remaining portion of the opening. The sidewall portion of the decomposable layer is decomposed to form an air gap.