Composite layered chip package

A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a composite layered chip package that includes a plurality of subpackages stacked on each other.

2. Description of the Related Art

In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.

As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.

Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.

The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation. The through electrode method is free from the above-mentioned problems of the wire bonding method.

U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In the method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip have their respective end faces exposed in a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed in the same side surface of the stack.

Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.

U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of electrically-conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated from each other into individual multilayer modules.

The yield of chips from a wafer that is to be cut later into a plurality of chips, i.e., the ratio of the number of conforming chips to the total number of chips in the wafer, is generally 90% to 99%. A layered chip package includes a plurality of chips. Therefore, the possibility that all the chips included in a layered chip package are conforming is lower than the yield of the chips. As the number of chips included in a layered chip package increases, the possibility that all the chips included in the layered chip package are conforming decreases.

A case will now be considered where a memory device such as a flash memory is constructed using a layered chip package. Generally, in a memory device such as a flash memory, a redundancy technique to replace a defective column of memory cells with a redundant column of memory cells is used so that the memory device can operate normally even when some memory cells are defective. Also in a memory device constructed using a layered chip package, if some of a plurality of memory cells included in a chip are defective, the redundancy technique can be used to allow the memory device to operate normally while allowing the use of the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells becomes defective due to, for example, a wiring failure in the control circuit, and even the redundancy technique cannot allow the chip to operate normally. In such a case, the defective chip is no longer usable. One possible solution to this case is to replace the defective chip with a conforming chip. However, this increases the manufacturing cost of the layered chip package.

Another possible solution is that a plurality of subpackages each of which includes no defective chips are electrically connected to each other to construct a memory device including a desired number of chips.

U.S. Pat. No. 7,745,259 B2 discloses a layered chip package having a configuration as described below. The layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each of the plurality of layer portions includes a semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The wiring is connected to the plurality of electrodes, the plurality of first terminals, and the plurality of second terminals of the plurality of layer portions. A plurality of such layered chip packages can be stacked on each other and electrically connected to each other.

When a plurality of layered chip packages having the same configuration are stacked on each other to construct a device such as a memory device, however, some of a plurality of signals to be associated with the chips in the respective corresponding layers of the plurality of layered chip packages may need to be varied from one layered chip package to another. This can cause the problem that the wiring of the device including the plurality of layered chip packages becomes complicated.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide a composite layered chip package that is formed by stacking a plurality of subpackages each of which includes one or more semiconductor chips, the composite layered chip package allowing some of a plurality of signal that are associated with the one or more semiconductor chips to be easily from one subpackage to another, and to provide a stackable chip package that can be used as a subpackage for constructing the composite layered chip package.

A composite layered chip package of the present invention includes a first subpackage and a second subpackage, the second subpackage being stacked on and electrically connected to the first subpackage. Each of the first and second subpackages includes a main body and wiring. The main body includes: a main part including at least one layer portion and having a top surface and a bottom surface; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. The plurality of first terminals and the plurality of second terminals are electrically connected to the wiring. The at least one layer portion includes a semiconductor chip. The plurality of first terminals of the first subpackage and those of the second subpackage are in the same layout. The plurality of second terminals of the first subpackage and those of the second subpackage are in the same layout.

The first subpackage and the second subpackage are arranged in a specific relative positional relationship with each other, the specific relative positional relationship being different from a reference relative positional relationship. The reference relative positional relationship is such that, when viewed in a direction perpendicular to the top surface of the main part of the second subpackage, the plurality of first terminals of the first subpackage and the plurality of first terminals of the second subpackage coincide with each other in position while the plurality of second terminals of the first subpackage and the plurality of second terminals of the second subpackage coincide with each other in position. The specific relative positional relationship is such that, with respect to the reference relative positional relationship, the second subpackage is displaced in a direction parallel to the top surface of the main part of the second subpackage.

The plurality of first terminals and the plurality of second terminals are shaped and arranged so that a plurality of pairs of first and second terminals are formed regardless of whether in the reference relative positional relationship or the specific relative positional relationship, each of the plurality of pairs of first and second terminals being made up of one of the plurality of first terminals of the first subpackage and one of the plurality of second terminals of the second subpackage that are in contact with each other. Combinations of the first and second terminals making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship.

In the composite layered chip package of the present invention, the main body may have a top surface, a bottom surface, and four side surfaces. The wiring may include a plurality of wires disposed on at least one of the side surfaces of the main body. In this case, the plurality of wires may include a chip connection wire that is used for electrical connection to the semiconductor chip, and a bypass wire that is not electrically connected to the semiconductor chip.

In the composite layered chip package of the present invention, the main body may further include a third terminal disposed on the top surface of the main part, and a fourth terminal disposed on the bottom surface of the main part. The third terminal and the fourth terminal are electrically connected to the wiring. The third terminal and the fourth terminal are shaped and arranged so that the third terminal of the first subpackage and the fourth terminal of the second subpackage are in contact with each other regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

In each of the first and second subpackages of the composite layered chip package of the present invention, the plurality of first terminals and the plurality of second terminals may be in the same layout when viewed in the direction perpendicular to the top surface of the main part.

The composite layered chip package of the present invention may be configured so that the plurality of first terminals include two or more first terminals that align in a first direction to form a first terminal row, and the plurality of second terminals include two or more second terminals that align in the first direction to form a second terminal row. At least either the plurality of first terminals or the plurality of second terminals may further include other two or more first or second terminals that align in the first direction to form a third terminal row. The third terminal row is adjacent to the first or second terminal row in a second direction orthogonal to the first direction. In this case, a plurality of pairs of terminals are formed across the first or second terminal row and the third terminal row, each of the plurality of pairs of terminals being made up of two terminals that are electrically connected to each other. The two terminals are one of the two or more first or second terminals that form the first or second terminal row and one of the other two or more first or second terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction. In this case, the specific relative positional relationship is such that the second subpackage is displaced in the second direction with respect to the reference relative positional relationship.

The composite layered chip package of the present invention may be configured so that the plurality of first terminals include two or more first terminals that align in a first direction to form a first terminal row, and the plurality of second terminals include two or more second terminals that align in the first direction to form a second terminal row. In this case, at least one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction. Of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In this case, the specific relative positional relationship is such that the second subpackage is displaced in the first direction with respect to the reference relative positional relationship.

In the composite layered chip package of the present invention, the main part may include a plurality of layer portions. In this case, each of the plurality of layer portions further includes a plurality of electrodes that are electrically connected to the wiring. The plurality of electrodes include a plurality of chip connection electrodes for electrical connection to the semiconductor chip. In at least one of the plurality of layer portions, the plurality of chip connection electrodes are in contact with and electrically connected to the semiconductor chip.

In the composite layered chip package of the present invention, when the main part includes a plurality of layer portions, the semiconductor chip may have a first surface and a second surface opposite to each other, and the plurality of electrodes may be located on the side of the first surface of the semiconductor chip. In this case, the plurality of layer portions may include a first layer portion located closest to the top surface of the main part, and a second layer portion located closest to the bottom surface of the main part. The first layer portion and the second layer portion may be arranged such that the second surfaces of the respective semiconductor chips included therein face each other. The plurality of first terminals may be formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals may be formed by using the plurality of electrodes of the second layer portion.

In the composite layered chip package of the present invention, when the main part includes a plurality of layer portions, the main body may have a top surface, a bottom surface, and four side surfaces, and the wiring may include a plurality of wires that are disposed on at least one of the side surfaces of the main body and pass through all the layer portions in the main part. In this case, the plurality of wires may include a common wire that is used for a purpose common to all the layer portions in the main part, and a plurality of layer-dependent wires that are used by different ones of the plurality of layer portions. The plurality of electrodes may include a common electrode that is electrically connected to the common wire, and a selective connection electrode that is selectively electrically connected to only one of the plurality of layer dependent wires that is used by the layer portion to which the selective connection electrode belongs. In this case, in at least one of the plurality of layer portions, the common electrode and the selective connection electrode are electrically connected to the semiconductor chip.

Stackable chip packages of first and second modes of the present invention are each usable as the first and second subpackages to constitute the composite layered chip package of the present invention. Each of the stackable chip packages of the first and second modes includes a main body and wiring. The main body includes: a main part including at least one layer portion and having a top surface and a bottom surface; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. The plurality of first terminals and the plurality of second terminals are electrically connected to the wiring. The at least one layer portion includes a semiconductor chip.

In the stackable chip package of the first mode, the plurality of first terminals include two or more first terminals that align in a first direction to form a first terminal row, while the plurality of second terminals include two or more second terminals that align in the first direction to form a second terminal row. At least either the plurality of first terminals or the plurality of second terminals further include other two or more first or second terminals that align in the first direction to form a third terminal row. The third terminal row is adjacent to the first or second terminal row in a second direction orthogonal to the first direction. A plurality of pairs of terminals are formed across the first or second terminal row and the third terminal row, each of the plurality of pairs of terminals being made up of two terminals that are electrically connected to each other. The two terminals are one of the two or more first or second terminals that form the first or second terminal row and one of the other two or more first or second terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction.

In the stackable chip package of the second mode, the plurality of first terminals include two or more first terminals that align in a first direction to form a first terminal row, while the plurality of second terminals include two or more second terminals that align in the first direction to form a second terminal row. At least one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction. Of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other.

In each of the stackable chip packages of the first and second modes, the main body may have a top surface, a bottom surface, and four side surfaces. The wiring may include a plurality of wires disposed on at least one of the side surfaces of the main body. In this case, the plurality of wires may include a chip connection wire that is used for electrical connection to the semiconductor chip, and a bypass wire that is not electrically connected to the semiconductor chip.

In each of the stackable chip packages of the first and second modes, the main body may further include a third terminal disposed on the top surface of the main part, and a fourth terminal disposed on the bottom surface of the main part. The third terminal and the fourth terminal are electrically connected to the wiring. The third terminal and the fourth terminal are shaped and arranged so that, when two stackable chip packages are used as the first and second subpackages, the third terminal of the first subpackage and the fourth terminal of the second subpackage are in contact with each other regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

In each of the stackable chip packages of the first and second modes, the plurality of first terminals and the plurality of second terminals may be in the same layout when viewed in the direction perpendicular to the top surface of the main part.

In each of the stackable chip packages of the first and second modes, the main part may include a plurality of layer portions. In this case, each of the plurality of layer portions further includes a plurality of electrodes that are electrically connected to the wiring. The plurality of electrodes include a plurality of chip connection electrodes for electrical connection to the semiconductor chip. In at least one of the plurality of layer portions, the plurality of chip connection electrodes are in contact with and electrically connected to the semiconductor chip.

In each of the stackable chip packages of the first and second modes, when the main part includes a plurality of layer portions, the semiconductor chip may have a first surface and a second surface opposite to each other, and the plurality of electrodes may be located on the side of the first surface of the semiconductor chip. In this case, the plurality of layer portions may include a first layer portion located closest to the top surface of the main part, and a second layer portion located closest to the bottom surface of the main part. The first layer portion and the second layer portion may be arranged such that the second surfaces of the respective semiconductor chips included therein face each other. The plurality of first terminals may be formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals may be formed by using the plurality of electrodes of the second layer portion.

In each of the stackable chip packages of the first and second modes, when the main part includes a plurality of layer portions, the main body may have a top surface, a bottom surface, and four side surfaces, and the wiring may include a plurality of wires that are disposed on at least one of the side surfaces of the main body and pass through all the layer portions in the main part. In this case, the plurality of wires may include a common wire that is used for a purpose common to all the layer portions in the main part, and a plurality of layer-dependent wires that are used by different ones of the plurality of layer portions. The plurality of electrodes may include a common electrode that is electrically connected to the common wire, and a selective connection electrode that is selectively electrically connected to only one of the plurality of layer-dependent wires that is used by the layer portion to which the selective connection electrode belongs. In this case, in at least one of the plurality of layer portions, the common electrode and the selective connection electrode are electrically connected to the semiconductor chip.

According to the composite layered chip package and the stackable chip packages (subpackages) of the present invention, arranging the first and second subpackages of the composite layered chip package in the specific relative positional relationship allows some of a plurality of signals associated with one or more semiconductor chips in the subpackages to be varied from one subpackage to another easily.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

Preferred embodiments of the present invention will now be described in detail with reference to the drawings. First, reference is made toFIG. 1toFIG. 7to describe the configurations of a composite layered chip package and a stackable chip package according to a first embodiment of the invention.FIG. 1is a perspective view of the composite layered chip package according to the present embodiment.FIG. 2is a perspective view of a composite layered chip package that is formed by arranging four subpackages ofFIG. 1in a reference relative positional relationship with each other.FIG. 3is a perspective view of the stackable chip package according to the present embodiment.FIG. 4is a perspective view showing the stackable chip package ofFIG. 3as viewed from below.FIG. 5is a plan view showing a plurality of terminals of the stackable chip package shown inFIG. 3.FIG. 6is a plan view showing a layer portion included in the stackable chip package shown inFIG. 3.FIG. 7is a perspective view of the layer portion shown inFIG. 6.

The composite layered chip package21according to the present embodiment includes a first subpackage and a second subpackage. The second subpackage is stacked on and electrically connected to the first subpackage. In particular, as shown inFIG. 1, the composite layered chip package21according to the present embodiment includes four subpackages stacked on each other. Hereinafter, the four subpackages will be designated by reference symbols1A,1B,1C, and1D in order from the top as shown inFIG. 1. In the composite layered chip package21, any two vertically adjacent subpackages are electrically connected to each other. Of any two vertically adjacent subpackages, the lower subpackage is the first subpackage and the upper subpackage is the second subpackage. Hereinafter, the first subpackage will be designated by reference symbol1L, and the second subpackage will be designated by reference symbol1U. Any subpackage will be designated by reference symbol1S. Each subpackage1S is the stackable chip package according to the present embodiment. For the sake of convenience, the subpackage1S shown inFIG. 3will be regarded as the second subpackage1U, and the subpackage1S shown inFIG. 4as the first subpackage1L. It follows that the second subpackage1U shown inFIG. 3is stacked on the first subpackage1L shown inFIG. 4.

The composite layered chip package22shown inFIG. 2is formed by arranging the four subpackages1A to1D ofFIG. 1in a reference relative positional relationship with each other. The composite layered chip package21according to the present embodiment shown inFIG. 1is a package formed by arranging the four subpackages1A to1D in a specific relative positional relationship, different from the reference relative positional relationship, with each other. The reference relative positional relationship and the specific relative positional relationship will be described in detail later.

As shown inFIG. 3andFIG. 4, the subpackage1S or the stackable chip package according to the present embodiment includes a main body2having a top surface2a, a bottom surface2b, and four side surfaces2c,2d,2e, and2f. The side surfaces2cand2dare mutually opposite to each other. The side surfaces2eand2fare mutually opposite to each other. The subpackage1S further has wiring3including a plurality of wires W disposed on at least one of the side surfaces of the main body2. In the example shown inFIG. 3andFIG. 4, the plurality of wires W are disposed on the side surface2conly. The main body2includes a main part2M having a top surface2Ma and a bottom surface2Mb. The main part2M includes a plurality of layer portions. In the present embodiment, in particular, the main part2M includes two layer portions10S1and10S2. The layer portion10S1is disposed on the layer portion10S2. Hereinafter, any layer portion will be designated by reference numeral10. The layer portion10S1is located closest to the top surface2Ma of the main part2M among the plurality of layer portions, and therefore corresponds to the first layer portion according to the invention. The layer portion10S2is located closest to the bottom surface2Mb of the main part2M among the plurality of layer portions, and therefore corresponds to the second layer portion according to the invention.

The main body2further includes: a plurality of first terminals4and a plurality of third terminals6disposed on the top surface2Ma of the main part2M; and a plurality of second terminals5and a plurality of fourth terminals7disposed on the bottom surface2Mb of the main part2M. The plurality of first terminals4, the plurality of second terminals5, the plurality of third terminals6, and the plurality of fourth terminals7are electrically connected to the wiring3(the plurality of wires W). The main body2further includes top wiring8and bottom wiring9. The top wiring8is disposed on the top surface2Ma of the main part2M and electrically connects the terminals4and6to the plurality of wires W. The bottom wiring9is disposed on the bottom surface2Mb of the main part2M and electrically connects the terminals5and7to the plurality of wires W.

The first and second subpackages1L and1U are the same in terms of the layout of the plurality of first terminals4, the layout of the plurality of second terminals5, the layout of the plurality of third terminals6, and the layout of the plurality of fourth terminals7. In the present embodiment, in particular, the four subpackages1A to1D are the same in terms of the layout of the plurality of first terminals4, the layout of the plurality of second terminals5, the layout of the plurality of third terminals6, and the layout of the plurality of fourth terminals7.

At least either the plurality of terminals4and6arranged on the top surface2Ma of the main part2M or the plurality of terminals5and7arranged on the bottom surface2Mb of the main part2M may include a solder layer that is made of a solder material and exposed in the terminal surfaces. The solder layer can be heated to melt and then solidified to electrically connect the plurality of the terminals5and7of the second subpackage1U to the plurality of terminals4and6of the first subpackage1L.

Here, as shown inFIG. 1toFIG. 4, X, Y, and Z directions will be defined as follows. The X direction is parallel to the top surface2Ma of the main part2M and the side surfaces2cand2dof the main body2. The Y direction is parallel to the top surface2Ma of the main part2M and the side surfaces2eand2fof the main body2. The Z direction is perpendicular to the top surface2Ma of the main part2M. The X, Y, and Z directions are orthogonal to each other.

In the present embodiment, each of the first and second subpackages1L and1U is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction. In the present embodiment, in particular, each of the four subpackages1A to1D is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the Z direction, and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.

As shown inFIG. 2, the reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the second subpackage1U, the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position while the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position. It should be appreciated that the phrase “the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position” refers to the situation where the plurality of first terminals4of the subpackage1L and the plurality of first terminals4of the subpackage1U coincide with each other in position in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U. Likewise, the phrase “the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position” refers to the situation where the plurality of second terminals5of the subpackage1L and the plurality of second terminals5of the subpackage1U coincide with each other in position in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U.

The specific relative positional relationship shown inFIG. 1is such that, with respect to the reference relative positional relationship shown inFIG. 2, the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U. The specific relative positional relationship may be said to be such that the second subpackage1U is offset from the first subpackage1L in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U. In the present embodiment, in particular, the specific relative positional relationship refers to such a positional relationship that the second subpackage1U is displaced in the Y direction with respect to the reference relative positional relationship.

The plurality of first terminals4and the plurality of second terminals5are shaped and arranged so that a plurality of pairs of first and second terminals4and5are formed regardless of whether in the reference relative positional relationship or the specific relative positional relationship, each of the plurality of pairs of first and second terminals4and5being made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other. Combinations of the first and second terminals4and5making up the plurality of pairs of first and second terminals4and5in the specific relative positional relationship are different from those in the reference relative positional relationship.

The plurality of third terminals6and the plurality of fourth terminal7are shaped and arranged so that the plurality of third terminals6of the first subpackage1L are in contact with the plurality of fourth terminals7of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship. The specific shape and arrangement of the plurality of terminals4,5,6, and7will be described in detail later.

A description will now be given of the layer portions10with reference toFIG. 6andFIG. 7.FIG. 6andFIG. 7show the layer portion10S1. Differences between the layer portion10S1and the layer portion10S2will be described later. Each layer portion10includes a semiconductor chip30. The semiconductor chip30has: a first surface30awith a device formed thereon; a second surface30bopposite to the first surface30a; a first side surface30cand a second side surface30dthat are mutually opposite to each other; and a third side surface30eand a fourth side surface30fthat are mutually opposite to each other.

Each layer portion10further includes an insulating portion31and a plurality of electrodes32. The insulating portion31covers at least one of the four side surfaces of the semiconductor chip30. The insulating portion31has at least one end face that is located in the at least one of the side surfaces of the main body2on which the plurality of wires W are disposed. In the example shown inFIG. 6andFIG. 7, the insulating portion31covers all the four side surfaces30c,30d,30eand30fof the semiconductor chip30, and has four end faces31c,31d,31eand31flocated in the four side surfaces of the main body2. The four end faces31c,31d,31e, and31fof the insulating portion31lie outside the four side surfaces30c,30d,30e, and30fof the semiconductor chip30, respectively. The plurality of electrodes32are disposed on the side of the first surface30aof the semiconductor chip30.

The layer portion10S1and the layer portion10S2are arranged so that the second surfaces30bof the respective semiconductor chips30included therein face each other. The layer portion10S1is arranged with the first surface30aof the semiconductor chip30upward and the side surfaces30c,30d,30e, and30fof the semiconductor chip30toward the side surfaces2c,2d,2e, and2fof the main body2, respectively. The layer portion10S2is arranged with the first surface30aof the semiconductor chip30downward and the side surfaces30c,30d,30e, and30fof the semiconductor chip30toward the side surfaces2c,2d,2f, and2eof the main body2, respectively. The layer portions10S1and10S2are bonded to each other with an adhesive, for example.

The plurality of electrodes32include a plurality of chip connection electrodes for electrical connection to the semiconductor chip30. In at least one of the layer portions10S1and10S2in each subpackage1S, the plurality of chip connection electrodes are in contact with and electrically connected to the semiconductor chip30, whereby the semiconductor chip30is electrically connected to two or more of the plurality of wires W via the plurality of chip connection electrodes.

Now, the plurality of terminals4,5,6, and7will be described in detail. In the present embodiment, as shown inFIG. 3andFIG. 4, each subpackage1S is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.FIG. 5shows the shape and arrangement of the plurality of terminals4,5,6, and7when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction). The shape and arrangement of the plurality of second terminals5when viewed from below the bottom surface2Mb of the main part2M are a mirror image to those of the plurality of first terminals4when viewed from above the top surface2Ma of the main part2M. Likewise, the shape and arrangement of the plurality of fourth terminals7when viewed from below the bottom surface2Mb of the main part2M are a mirror image to those of the plurality of third terminals6when viewed from above the top surface2Ma of the main part2M.

As shown inFIG. 5, the plurality of first terminals4include two or more first terminals4that align in a first direction to form a first terminal row. Specifically, the plurality of first terminals4include: four first terminals4C11,4C12,4C13, and4C14that align in the X direction to form a terminal row41C; four first terminals4R11,4R12,4R13, and4R14that align in the X direction to form a terminal row41R1; and four first terminals4R15,4R16,4R17, and4R18that align in the X direction to form a terminal row41R2. The X direction corresponds to the first direction. Each of the terminal rows41C,41R1, and41R2corresponds to the first terminal row.

The plurality of second terminals5include two or more second terminals5that align in the first direction to form a second terminal row. Specifically, the plurality of second terminals5include: four second terminals5C11,5C12,5C13, and5C14that align in the X direction to form a terminal row51C; four second terminals5R11,5R12,5R13, and5R14that align in the X direction to form a terminal row51R1; and four second terminals5R15,5R16,5R17, and5R18that align in the X direction to form a terminal row51R2. Each of the terminal rows51C,51R1, and51R2corresponds to the second terminal row.

At least either the plurality of first terminals4or the plurality of second terminals5further include other two or more first or second terminals that align in the first direction (the X direction) to form a third terminal row. The third terminal row is adjacent to the first or second terminal row in a second direction orthogonal to the first direction (the X direction). In the present embodiment, in particular, the plurality of first terminals4include other two or more first terminals that align in the first direction (the X direction) to form a third terminal row, and the plurality of second terminals5include other two or more second terminals that align in the first direction (the X direction) to form a third terminal row.

Specifically, the plurality of first terminals4include: four first terminals4C21,4C22,4C23, and4C24that align in the X direction to form a terminal row42C; four first terminals4R21,4R22,4R23, and4R24that align in the X direction to form a terminal row42R1; and four first terminals4R25,4R26,4R27, and4R28that align in the X direction to form a terminal row42R2. The terminal row42C is adjacent to the terminal row41C in the Y direction. The terminal row42R1is adjacent to the terminal row41R1in the Y direction. The terminal row42R2is adjacent to the terminal row41R2in the Y direction. The Y direction corresponds to the second direction. Each of the terminal rows42C,42R1, and42R2corresponds to the third terminal row.

A plurality of pairs of terminals are formed across a first terminal row and an adjacent third terminal row, each of the plurality of pairs of terminals being made up of two terminals that are electrically connected to each other. The two terminals are one of the two or more first terminals that form the first terminal row and one of the other two or more first terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). Specifically, across the first terminal row and the third terminal row, there are formed the following pairs of two electrically-connected terminals: (4C11,4C22), (4C12,4C23), (4C13,4C24), (4C14,4C21), (4R11,4R22), (4R12,4R23), (4R13,4R24), (4R14,4R21), (4R15,4R26), (4R16,4R27), (4R17,4R28), and (4R18,4R25).

The plurality of second terminals5include; four second terminals5021,5C22,5C23, and5024that align in the X direction to form a terminal row52C; four second terminals5R21,5R22,5R23, and5R24that align in the X direction to form a terminal row52R1; and four second terminals5R25,5R26,5R27, and5R28that align in the X direction to form a terminal row52R2. The terminal row52C is adjacent to the terminal row51C in the Y direction. The terminal row52R1is adjacent to the terminal row51R1in the Y direction. The terminal row52R2is adjacent to the terminal row51R2in the Y direction. Each of the terminal rows52C,52R1, and52R2corresponds to the third terminal row.

A plurality of pairs of terminals are formed across a second terminal row and an adjacent third terminal row, each of the plurality of pairs of terminals being made up of two terminals that are electrically connected to each other. The two terminals are one of the two or more second terminals that form the second terminal row and one of the other two or more second terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). Specifically, across the second terminal row and the third terminal row, there are formed the following pairs of two electrically-connected terminals: (5C11,5C22), (5C12,5C23), (5C13,5C24), (5C14,5C21), (5R11,5R22), (5R12,5R23), (5R13,5R24), (5R14,5R21), (5R15,5R26), (5R16,5R27), (5R17,5R28), and (5R18,5R25).

The plurality of third terminals6include four terminals6A1to6A4. The terminals6A1to6A4are each shaped to be elongated in the Y direction as compared with the first terminals4. The plurality of fourth terminals7include four terminals7A1to7A4. The terminals7A1to7A4are each shaped to be elongated in the Y direction as compared with the second terminals5.

Now, the plurality of wires W will be described in detail. The plurality of wires W are disposed on the side surface2cof the main body2and pass through all the layer portions10S1and10S2in the main part2M. The plurality of wires W include wires WC1, WC2, WC3, WC4, WR1, WR2, WR3, WR4, WR5, WR6, WR7, WR8, WA1, WA2, WA3, and WA4that electrically connect two terminals in the respective pairs of terminals (4C11,5C11), (4C12,5C12), (4C13,5C13), (4C14,5C14), (4R11,5R11), (4R12,5R12), (4R13,5R13), (4R14,5R14), (4R15,5R15), (4R16,5R16), (4R17,5R17), (4R18,5R18), (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4).

The wires WA1to WA4are used for a purpose common to all the layer portions10S1and10S2in the main part2M. Each of these wires therefore corresponds to the common wire according to the invention. The wires WR1and WR5are used by different ones of the plurality of layer portions. These wires therefore correspond to the layer-dependent wires according to the invention.

The wires WA1to WA4, WC1, WR1, and WR5are used for electrical connection to the semiconductor chip30. These wires therefore correspond to the chip connection wires according to the invention. The wires WC2to WC4, WR2to WR4, and WR6to WR8are electrically non-connected to the semiconductor chip30. These wires therefore correspond to the bypass wires according to the invention.

The plurality of electrodes32will now be described. In the present embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10S1, and the plurality of terminals5and7are formed by using the plurality of electrodes32of the layer portion10S2.

FIG. 6andFIG. 7illustrate the shape and arrangement of the plurality of electrodes32of the layer portion10S1. The shape and arrangement of the plurality of electrodes32of the layer portion10S2when viewed from the side of the first surface30aof the semiconductor chip30are a mirror image to those of the plurality of electrodes32shown inFIG. 6andFIG. 7.

The plurality of electrodes32include electrodes32C11to32C14,32C21to32C24,32R11to32R18,32R21to32R28,32A1to32A4,32D1, and32D2. InFIG. 7, the reference symbols of the electrodes other than the electrodes32A1to32A4,32D1, and32D2are omitted.

The electrodes32C11to32C14,32R11to32R18,32C21to32C24,32R21to32R28, and32A1to32A4of the layer portion10S1include terminal component parts that are used for forming the terminals4C11to4C14,4R11to4R18,4C21to4C24,4R21to4R28, and6A1to6A4.

The electrodes32C11to32C14,32R11to32R18,32C21to32C24,32R21to32R28, and32A1to32A4of the layer portion10S2include terminal component parts that are used for forming the terminals5C11to5C14,5R11to5R18,5C21to5C24,5R21to5R28, and7A1to7A4.

The electrodes32C11to32C14,32R11to32R18, and32A1to32A4have respective end faces located in the end face31cof the insulating portion31, and are electrically connected to the wires WC1to WC4, WR1to WR8, and WA1to WA4via those end faces. The electrodes32A1to32A4correspond to the common electrodes according to the invention.

A plurality of pairs of electrodes are formed across a group of electrodes32C11to32C14and32R11to32R18and a group of electrodes32C21to32C24and32R21to32R28, each of the plurality of pairs of electrodes being made up of two electrodes that are electrically connected to each other. The two electrodes are ones that are not adjacent to each other in the second direction (the Y direction). Specifically, there are formed the following pairs of two electrically-connected electrodes: (32C11,32C22), (32C12,32C23), (32C13,32C24), (32C14,32C21), (32R11,32R22), (32R12,32R23), (32R13,32R24), (32R14,32R21), (32R15,32R26), (32R16,32R27), (32R17,32R28), and (32R18,32R25).

The electrodes32A1to32A4,32D1, and32D2are in contact with and electrically connected to the semiconductor chip30. These electrodes therefore correspond to the chip connection electrodes according to the invention. InFIG. 6, the dashed squares in the electrodes32A1to32A4,32D1, and32D2represent the areas where these electrodes make contact with the semiconductor chip30. None of the electrodes32C11to32C14,32R11to32R18,32C21to32C24, and32R21to32R28are in contact with the semiconductor chip30. Neither of the electrodes32D1and32D2are used for forming any terminal.

The electrode32D1has an end face located in the end face31cof the insulating portion31. This end'face is located near the end face of the electrode32C11. The electrode32D2has first and second branch portions. Each of the first and second branch portions has an end face located in the end face31cof the insulating portion31. The end face of the first branch portion is located near the end face of the electrode32R11. The end face of the second branch portion is located near the end face of the electrode32R15.

In each of the layer portions10S1and10S2, the wire WC1is broadened to come into contact with the end face of the electrode32D1. The electrode32D1of each of the layer portions10S1and10S2is thereby electrically connected to the wire WC1. In the layer portion10S1, the wire WR1is broadened in part to come into contact with the end face of the first branch portion of the electrode32D2. The electrode32D2of the layer portion10S1is thereby electrically connected to the wire WR1. In the layer portion10S2, the wire WR5is broadened in part to come into contact with the end face of the second branch portion of the electrode32D2. The electrode32D2of the layer portion10S2is thereby electrically connected to the wire WR5. The electrode32D2corresponds to the selective connection electrode according to the invention.

In each of the layer portions10S1and10S2, the insulating portion31does not cover the terminal component parts of the plurality of electrodes but covers the other portions of the plurality of electrodes and the first surface30aof the semiconductor chip30. The terminal component parts not covered by the insulating portion31form conductor pads. Conductor layers are formed on the conductor pads. The terminal component parts and the conductor layers of the layer portion10S1constitute the plurality of terminals4and6. The terminal component parts and the conductor layers of the layer portion10S2constitute the plurality of terminals5and7. In the present embodiment, the plurality of terminals4and6are thus formed by using the plurality of electrodes (the plurality of terminal component parts) of the layer portion10S1. Part of the portions of the plurality of electrodes covered by the insulating portion31in the layer portion10S1forms the top wiring8. The plurality of terminals5and7are thus formed by using the plurality of electrodes (the plurality of terminal component parts) of the layer portion10S2. Part of the portions of the plurality of electrodes covered by the insulating portion31in the layer portion10S2forms the bottom wiring9. InFIG. 1toFIG. 4, the insulating portions31in the layer portions10S1and10S2are partly shown in broken lines.

The semiconductor chip30may be a memory chip that constitutes a memory such as a flash memory, DRAM, SRAM, MRAM, PROM, or FeRAM. In such a case, the semiconductor chip30includes a plurality of memory cells. It is possible in this case to construct a memory device of large capacity by using the composite layered chip package21including a plurality of semiconductor chips30. With the composite layered chip package21according to the present embodiment, it is also possible to easily construct a memory device of various capacities such as 64 GB (gigabytes), 128 GB, and 256 GB by varying the number of the semiconductor chips30to be included in the composite layered chip package21.

The semiconductor chips30are not limited to memory chips, and may be ones used for constructing other devices such as CPUs, sensors, and driving circuits for sensors.

Now, the reference relative positional relationship and the specific relative positional relationship will be described in detail. The reference relative positional relationship will be described first, with reference toFIG. 2. The reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the subpackage1U (the Z direction), the plurality of first terminals4of the subpackage1L and the plurality of first terminals4of the subpackage1U coincide with each other in position while the plurality of second terminals5of the subpackage1L and the plurality of second terminals5of the subpackage1U coincide with each other in position. When in the reference relative positional relationship, terminals4and6of the subpackage1L and terminals5and7of the subpackage1U that coincide with each other in position when viewed in the Z direction are in contact with each other and electrically connected to each other. In this way, there are formed a plurality of pairs of first and second terminals each of which is made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other.

The specific relative positional relationship shown inFIG. 1is such that the second subpackage1U is displaced in the Y direction (the second direction) with respect to the reference relative positional relationship. Combinations of the first terminals4of the first subpackage1L and the second terminals5of the second subpackage1U making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship. In the example shown inFIG. 1, the second subpackage1U is displaced in the direction from the side surface2cof the main body2toward the side surface2dof the main body2, with respect to the reference relative positional relationship. It should be noted that the specific relative positional relationship may be such that the second subpackage1U is displaced in the direction from the side surface2dtoward the side surface2c, with respect to the reference relative positional relationship.

When in the specific relative positional relationship shown inFIG. 1, the plurality of pairs of first and second terminals, each of which is made up of one of the first terminals4of the first subpackage1L and one of the second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other, are as follows: (4C21,5C11), (4C22,5C12), (4C23,5C13), (4C24,5C14), (4R21,5R11), (4R22,5R12), (4R23,5R13), (4R24,5R14), (4R25,5R15), (4R26,5R16), (4R27,5R17), and (4R28,5R18).

When in a not-shown specific relative positional relationship where the second subpackage1U is displaced in the direction from the side surface2dtoward the side surface2cwith respect to the reference relative positional relationship, the terminals5C21to5C24,5R21to5R28, and7A1to7A4of the second subpackage1U are in contact with and electrically connected to the terminals4C11to4C14,4R11to4R18, and6A1to6A4of the first subpackage1L.

Because of the shape and arrangement of the terminals6A1to6A4and7A1to7A4described above, there are formed a plurality of pairs of terminals (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4) in each of which the two terminals are in contact with and electrically connected to each other, across the terminals6A1to6A4of the first subpackage1L and the terminals7A1to7A4of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

Next, the flow of a plurality of signals in the composite layered chip package21shown inFIG. 1and the composite layered chip package22shown inFIG. 2will be described.FIG. 8is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package21shown inFIG. 1.FIG. 9is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package22shown inFIG. 2.

In each subpackage1S, the same signal appears on a plurality of terminals that are electrically connected to each other. More specifically, the signals to appear on the terminals4C21,4C22,4C23, and4C24are the same as those on the terminals4C14,4C11,4C12, and4C13, respectively. The signals to appear on the terminals5C21,5C22,5C23, and5C24are the same as those on the terminals5C14,5C11,5C12, and5C13, respectively. The signals to appear on the terminals5C11to5C14and5C21to5C24are the same as those on the terminals4C11to4C14and4C21to4C24, respectively.

FIG. 8shows an example where the signals S4,51, S2, and S3are supplied to the terminals5C11,5C12,5C13, and5C14of the subpackage1D as shown in portion (d) ofFIG. 8. In this case, in the subpackage1D, the signals S4, S1, S2, and S3appear on the terminals4C11,4C12,4C13, and4C14, respectively, while the signals S3, S4,51, and S2appear on the terminals4C21,4C22,4C23, and4C24, respectively.

When in the specific relative positional relationship shown inFIG. 1, the terminals5C11,5C12,5C13, and5C14of the subpackage1C are in contact with the terminals4C21,4C22,4C23, and4C24of the subpackage1D. Consequently, in the subpackage10, as shown in portion (c) ofFIG. 8, the signals S3, S4, S1, and S2are transmitted to the terminals5C11,5C12,5C13, and5C14. As a result, the signals S3, S4, S1, and S2appear on the terminals4C11,4C12,4C13, and4C14, respectively, while the signals S2, S3, S4, and S1appear on the terminals4C21,4C22,4C23, and4C24, respectively.

In the subpackage1B, as shown in portion (b) ofFIG. 8, the signals S2, S3, S4, and S1are transmitted to the terminals5C11,5C12,5C13, and5C14. As a result, the signals S2, S3, S4, and S1appear on the terminals4C11,4C12,4C13, and4C14, respectively, while the signals S1, S2, S3, and S4appear on the terminals4C21,4C22,4C23, and4C24, respectively.

In the subpackage1A, as shown in portion (a) ofFIG. 8, the signals S1, S2, S3, and S4are transmitted to the terminals5C11,5C12,5C13, and5C14. As a result, the signals S1, S2, S3, and S4appear on the terminals4C11,4C12,4C13, and4C14, respectively, while the signals S4, S1, S2, and S3appear on the terminals4C21,4C22,4C23, and4C24, respectively.

In each of the layer portions10S1and10S2, the terminals4C11and5C11are electrically connected to the semiconductor chip30through the wire WC1and the electrode32D1. As described above, when in the specific relative positional relationship shown inFIG. 1, the signal to appear on the terminals4C11and5C11varies from one subpackage1S to another. Consequently, in the composite layered chip package21shown inFIG. 1, the signals associated with the semiconductor chips30of the respective corresponding layers of different subpackages1S through the wire WC1and the electrodes32D1can be varied from one subpackage is to another. In the example shown inFIG. 8, the signal associated with the semiconductor chips30of the layer portions10S1and10S2through the wire WC1and the electrodes32D1in the subpackage1A is the signal S1. The signal S2is associated in the subpackage1B, the signal S3in the subpackage1C, and the signal S4in the subpackage1D.

On the other hand, when in the reference relative positional relationship shown inFIG. 2, the signals to appear on the terminals4C11to4C14,4C21to4C24,5C11to5C14, and5C21to5C24do not vary from one subpackage1S to another as shown inFIG. 9.FIG. 9shows an example where the signals S1, S2, S3, and S4are supplied to the terminals5C11,5C12,5C13, and5C14of the subpackage1D. In the composite layered chip package22shown inFIG. 2, the same signals are associated with the semiconductor chips30of the respective corresponding layers in all the subpackages1A to1D, through the wire WC1and the electrodes32D1.

The mode of signal flow described with reference toFIG. 8andFIG. 9also applies to the group of terminals4R11to4R14,4R21to4R24,5R11to5R14, and5R21to5R24, and the group of terminals4R15to4R18,4R25to4R28,5R15to5R18, and5R25to5R28.

For the composite layered chip package21shown inFIG. 1, suppose a case where signals S4,51, S2, and S3are associated with the terminals5R11to5R14of the subpackage1D, respectively. In this case, the signal associated with the semiconductor chip30of the layer portion10S1through the wire WR1and the electrode32D2in the subpackage1A is the signal S1. The signal S2is associated in the subpackage1B, the signal S3in the subpackage1C, and the signal S4in the subpackage1D. On the other hand, in the composite layered chip package22shown inFIG. 2, the signal associated with the semiconductor chip30of the layer portion10S1through the wire WR1and the electrode32D2is the same among all the subpackages1A to1D.

For the composite layered chip package21shown inFIG. 1, suppose also a case where signals S4, S1, S2, and S3are associated with the terminals5R15to5R18of the subpackage1D, respectively. In this case, the signal associated with the semiconductor chip30of the layer portion10S2through the wire WR5and the electrode32D2in the subpackage1A is the signal S1. The signal S2is associated in the subpackage1B, the signal S3in the subpackage1C, and the signal S4in the subpackage1D. On the other hand, in the composite layered chip package22shown inFIG. 2, the signal associated with the semiconductor chip30of the layer portion10S2through the wire WR5and the electrode32D2is the same among all the subpackages1A to1D.

In the present embodiment, a plurality of subpackages1S of the same configuration are arranged in the specific relative positional relationship shown inFIG. 1to construct the composite layered chip package21. This makes it possible that some of a plurality of signals associated with one or more semiconductor chips30in the subpackages1S are varied from one subpackage1S to another easily.

The composite layered chip package21according to the present embodiment will now be described in more detail with reference to a case where the composite layered chip package21is used to construct a memory device.FIG. 10is a block diagram showing the configuration of the memory device that uses the composite layered chip package21according to the present embodiment. The memory device includes eight memory chips MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a controller90which controls these memory chips.

The memory chips MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8are the respective semiconductor chips30in the layer portions10S1and10S2of the subpackage1A, the layer portions10S1and10S2of the subpackage1B, the layer portions10S1and10S2of the subpackage1C, and the layer portions10S1and10S2of the subpackage1D, which are shown inFIG. 1. Each of the memory chips includes a plurality of memory cells and a peripheral circuit such as an address decoder. The controller90is provided independent of the composite layered chip package21, and is electrically connected to the plurality of terminals4and6of the subpackage1A or the plurality of terminals5and7of the subpackage1D.

The memory device further includes a data bus91which electrically connects the controller90to the eight memory chips, and one or more common lines92which electrically connect the controller90to the eight memory chips. Each of the eight memory chips includes a plurality of electrode pads to which the data bus91is electrically connected, and one or more electrode pads to which the one or more common lines92are electrically connected. The data bus91transmits addresses, commands, data, etc. The one or more common lines92include power lines as well as signal lines for transmitting signals that are other than those transmitted by the data bus91and are used in common by the eight memory chips.

Each of the eight memory chips further includes an electrode pad CE for receiving a chip enable signal and an electrode pad RB for outputting a ready/busy signal. The chip enable signal is a signal for controlling whether to select or deselect the memory chip. The ready/busy signal is a signal for indicating the operating state of the memory chip.

The memory device shown inFIG. 10further includes signal lines93C1,93C2,93C3, and93C4. The signal line93C1electrically connects the controller90to the electrode pads CE of the memory chips MC1and MC2, and transmits a chip enable signal CE1. The signal line93C2electrically connects the controller90to the electrode pads CE of the memory chips MC3and MC4, and transmits a chip enable signal CE2. The signal line93C3electrically connects the controller90to the electrode pads CE of the memory chips MC5and MC6, and transmits a chip enable signal CE3. The signal line93C4electrically connects the controller90to the electrode pads CE of the memory chips MC7and MC8, and transmits a chip enable signal CE4. Thus, in the example shown inFIG. 10, the signal line93C1is used by the memory chips MC1and MC2in common, the signal line93C2is used by the memory chips MC3and MC4in common, the signal line93C3is used by the memory chips MC5and MC6in common, and the signal line93C4is used by the memory chips MC7and MC8in common. Nevertheless, eight signal lines for transmitting respective different chip enable signals to the memory chips may be provided instead of the signal lines93C1,93C2,93C3, and93C4.

The memory device shown inFIG. 10further includes signal lines93R1,93R2,93R3,93R4,93R5,93R6,93R7, and93R8. One end of each of the signal lines93R1to93R8is electrically connected to the controller90. The other ends of the signal lines93R1to93R8are electrically connected to the electrode pads R/B of the memory chips MC1to MC8, respectively. The signal lines93R1to93R8transmit ready/busy signals R/B1to R/B8, respectively.

Now, a description will be made as to the flow of a plurality of signals for the case where the composite layered chip package21shown inFIG. 1is used to construct the memory device shown inFIG. 10. In the subpackages1A to1D of the composite layered chip package21shown inFIG. 1, the terminals6A1and7A1are electrically connected to the wire WA1, the terminals6A2and7A2are electrically connected to the wire WA2, the terminals6A3and7A3are electrically connected to the wire WA3, and the terminals6A4and7A4are electrically connected to the wire WA4. As a result, there are formed a plurality of electrical paths that lead from the terminals6A1-6A4of the subpackage1A to the terminals7A1-7A4of the subpackage1D. The plurality of electrical paths constitute parts of the data bus91and the one or more common lines92.

The chip enable signal CE1is supplied to the terminal4C11of the subpackage1A or the terminal5C12of the subpackage1D. The chip enable signal CE2is supplied to the terminal4C12of the subpackage1A or the terminal5C13of the subpackage1D. The chip enable signal CE3is supplied to the terminal4C13of the subpackage1A or the terminal5C14of the subpackage1D. The chip enable signal CE4is supplied to the terminal4C14of the subpackage1A or the terminal5C11of the subpackage1D.

The chip enable signals CE1, CE2, CE3, and CE4correspond to the signals S1, S2, S3, and S4inFIG. 8, respectively. As can be seen from the description that has been made with reference toFIG. 8, in the composite layered chip package21, the chip enable signal CE1is supplied only to the semiconductor chips30of the layer portions10S1and10S2of the subpackage1A, i.e., the memory chips MC1and MC2. Likewise, the chip enable signal CE2is supplied only to the semiconductor chips30of the layer portions10S1and10S2of the subpackage1B, i.e., the memory chips MC3and MC4. The chip enable signal CE3is supplied only to the semiconductor chips30of the layer portions10S1and10S2of the subpackage1C, i.e., the memory chips MC5and MC6. The chip enable signal CE4is supplied only to the semiconductor chips30of the layer portions10S1and10S2of the subpackage1D, i.e., the memory chips MC7and MC8.

The semiconductor chip30outputs a ready/busy signal from the electrode32D2. In the layer portion10S1of the subpackage1A, the ready/busy signal R/B1is output from the electrode32D2. The signal R/B1is transmitted to the wire WR1of the subpackage1A and is output from the terminal4R11of the subpackage1A or the terminal5R12of the subpackage1D. In the layer portion10S2of the subpackage1A, the ready/busy signal R/B2is output from the electrode32D2. The signal R/B2is transmitted to the wire WR5of the subpackage1A and is output from the terminal4R15of the subpackage1A or the terminal5R16of the subpackage1D.

In the layer portion10S1of the subpackage1B, the ready/busy signal R/B3is output from the electrode32D2. The signal R/B3is transmitted to the wire WR1of the subpackage1B and is output from the terminal4R12of the subpackage1A or the terminal5R13of the subpackage1D. In the layer portion10S2of the subpackage1B, the ready/busy signal R/B4is output from the electrode32D2. The signal R/B4is transmitted to the wire WR5of the subpackage1B and is output from the terminal4R16of the subpackage1A or the terminal5R17of the subpackage1D.

In the layer portion10S1of the subpackage1C, the ready/busy signal R/B5is output from the electrode32D2. The signal R/B5is transmitted to the wire WR1of the subpackage1C and is output from the terminal4R13of the subpackage1A or the terminal5R14of the subpackage1D. In the layer portion10S2of the subpackage1C, the ready/busy signal R/B6is output from the electrode32D2. The signal R/B6is transmitted to the wire WR5of the subpackage1C and is output from the terminal4R17of the subpackage1A or the terminal5R18of the subpackage1D.

In the layer portion10S1of the subpackage1D, the ready/busy signal R/B7is output from the electrode32D2. The signal R/B7is transmitted to the wire WR1of the subpackage1D and is output from the terminal4R14of the subpackage1A or the terminal5R11of the subpackage1D. In the layer portion10S2of the subpackage1D, the ready/busy signal R/B8is output from the electrode32D2. The signal R/B8is transmitted to the wire WR5of the subpackage1D and is output from the terminal4R18of the subpackage1A or the terminal5R15of the subpackage1D.

As has been described, according to the composite layered chip package21shown inFIG. 1, the chip enable signals or ready/busy signals associated with the semiconductor chips30(memory chips) in the respective corresponding layers of the subpackages1A to1D of the same configuration can easily be varied between the subpackages1A to1D.

Reference is now made toFIG. 11to describe an example of the configuration of the memory cells included in the semiconductor chip30(memory chip). The memory cell60shown inFIG. 11includes a source62and a drain63formed near a surface of a P-type silicon substrate61. The source62and the drain63are both N-type regions. The source62and the drain63are disposed at a predetermined distance from each other so that a channel composed of a part of the P-type silicon substrate61is provided between the source62and the drain63. The memory cell40further includes an insulating film64, a floating gate65, an insulating film66, and a control gate67that are stacked in this order on the surface of the substrate61at the location between the source62and the drain63. The memory cell40further includes an insulating layer68that covers the source62, the drain63, the insulating film64, the floating gate65, the insulating film66and the control gate67. The insulating layer68has contact holes that open in the tops of the source62, the drain63and the control gate67, respectively. The memory cell40includes a source electrode72, a drain electrode73, and a control gate electrode77that are formed on the insulating layer68at locations above the source62, the drain63and the control gate67, respectively. The source electrode72, the drain electrode73and the control gate electrode77are connected to the source62, the drain63and the control gate67, respectively, through the corresponding contact holes.

A description will now be given of a method of manufacturing the subpackage1S, i.e., the stackable chip package according to the present embodiment. The method of manufacturing the subpackage1S according to the embodiment is a method by which a plurality of subpackages1S are manufactured. The method includes the step of fabricating a layered substructure by stacking a plurality of substructures and the step of producing a plurality of subpackages1S from the layered substructure. Each of the plurality of substructures includes a plurality of preliminary layer portions that are arrayed. Each of the preliminary layer portions is to become any one of the layer portions10included in the main part2M. The plurality of substructures are to be cut at the positions of boundaries between every adjacent preliminary layer portions.

The step of fabricating the layered substructure will now be described in detail with reference toFIG. 12toFIG. 24. In the step of fabricating the layered substructure, a pre-substructure wafer101is fabricated first. The pre-substructure wafer101includes a plurality of pre-semiconductor-chip portions that are arrayed. The pre-semiconductor-chip portions are to become individual semiconductor chips30.FIG. 12is a plan view of the pre-substructure wafer101.FIG. 13is a magnified plan view of a part of the pre-substructure wafer101shown inFIG. 12.FIG. 14shows a cross section taken along line14-14ofFIG. 13.

Specifically, in the step of fabricating the pre-substructure wafer101, the pre-substructure wafer101is fabricated by performing processing, such as a wafer process, on one of two mutually opposite surfaces of a semiconductor wafer100. The plurality of pre-semiconductor-chip portions30P, each of which includes a device, are arrayed in the pre-substructure wafer101. In the pre-substructure wafer101, the plurality of pre-semiconductor-chip portions30P may be in a row, or in a plurality of rows such that a number of pre-semiconductor-chip portions30P align both in vertical and horizontal directions. The following description assumes that the plurality of pre-semiconductor-chip portions30P in the pre-substructure wafer101are in a plurality of rows such that a number of pre-semiconductor-chip portions30P align both in vertical and horizontal directions. Hereinafter, pre-semiconductor-chip portions30P that are to become the semiconductor chips30of the layer portions10S1and pre-semiconductor-chip portions30P that are to become the semiconductor chips30of the layer portions10S2will be designated by reference symbols30P1and30P2, respectively, when a distinction is needed.

According to the present embodiment, in particular, in the step of fabricating the pre-substructure wafer101, the pre-substructure wafer101is fabricated such that the pre-semiconductor-chip portions30P1and the pre-semiconductor-chip portions30P2are arranged to alternate at least in one direction as shown inFIG. 12toFIG. 14. InFIG. 12, the pre-semiconductor-chip portions30P1and30P2are represented by reference symbols P1and P2, respectively.FIG. 12shows an example where the pre-semiconductor-chip portions30P1and30P2are arranged to alternate only in the vertical direction. However, the pre-semiconductor-chip portions30P1and30P2may be arranged to alternate only in the horizontal direction, or both in the vertical and horizontal directions. Taking two symmetrical positions of the pre-substructure wafer101about a virtual line that passes the center in the direction of alternate arrangement of the pre-semiconductor-chip portions30P1and30P2, a pre-semiconductor-chip portion30P1is arranged on one side and a pre-semiconductor-chip portion30P2on the other.

The semiconductor wafer100may be a silicon wafer, for example. The wafer process is a process in which a semiconductor wafer is processed into a plurality of devices yet to be separated into a plurality of chips. For ease of understanding,FIG. 12depicts the pre-semiconductor-chip portions (P1and P2) larger relative to the semiconductor wafer100. For example, if the semiconductor wafer100is a 12-inch wafer and the top surface of each pre-semiconductor-chip portion30is 8 to 10 mm long at each side, then 700 to 900 pre-semiconductor-chip portions are obtainable from a single semiconductor wafer100.

As shown inFIG. 14, the pre-semiconductor-chip portions30P1and30P2include a device-forming region47formed near one of the two surfaces of the semiconductor wafer100. The device-forming region47is a region where devices are formed by processing the one of the two surfaces of the semiconductor wafer100. The pre-semiconductor-chip portions30P1and30P2further include a plurality of electrode pads48disposed on the device-forming region47, and a passivation film49disposed on the device-forming region47. The passivation film49is made of an insulating material such as phospho-silicate-glass (PSG), silicon nitride, or polyimide resin. The passivation film49has a plurality of openings for exposing the top surfaces of the plurality of electrode pads48. The plurality of electrode pads48are located in the positions corresponding to the plurality of electrodes to be formed later, and are electrically connected to the devices formed in the device-forming region47. Hereinafter, the surface of the pre-substructure wafer101located closer to the plurality of electrode pads48and the passivation film49will be referred to as a first surface101a, and the opposite surface will be referred to as a second surface101b.

FIG. 15is a plan view showing a step that follows the step shown inFIG. 13.FIG. 16shows a cross section taken along line16-16ofFIG. 15. In this step, first, a protective layer103is formed to cover the first surface101aof the pre-substructure wafer101. The protective layer103is made of a photoresist, for example. Next, a plurality of grooves104that open in the first surface101aof the pre-substructure wafer101are formed in the pre-substructure wafer101so as to define the respective areas of the plurality of pre-semiconductor-chip portions30P1and30P2. Note that the protective layer103is not shown inFIG. 15.

In the positions of boundaries between every two adjacent pre-semiconductor-chip portions, the grooves104are formed to pass through the boundaries between every two adjacent pre-semiconductor-chip portions. The grooves104are formed such that their bottoms do not reach the second surface101bof the pre-substructure wafer101. The grooves104have a width in the range of 50 to 150 μm, for example. The grooves104have a depth in the range of 20 to 80 μm, for example.

The grooves104may be formed using a dicing saw or by performing etching, for example. The etching may be reactive ion etching or anisotropic wet etching using KOH as the etching solution, for example. When forming the grooves104by etching, an etching mask may be formed by patterning the protective layer103by photolithography. The protective layer103is removed after the grooves104are formed. As a result, there is formed a pre-polishing substructure main body105which is composed of the pre-substructure wafer101with the plurality of grooves104formed therein.

FIG. 17shows a step that follows the step shown inFIG. 16. In this step, an insulating film106P is formed to fill the plurality of grooves104of the pre-polishing substructure main body105and to cover the plurality of electrode pads48and the passivation film49. The insulating film106P is to later become part of the insulating portion31. The insulating film106P may be formed of a resin such as an epoxy resin or a polyimide resin. The insulating film106P may also be formed of a photosensitive material such as a sensitizer-containing polyimide resin. The insulating film106P may also be formed of an inorganic material such as silicon oxide or silicon nitride.

It is preferred that the insulating film106P be formed of a resin having a low thermal expansion coefficient. If the insulating film106P is formed of a resin having a low thermal expansion coefficient, it becomes easy to cut the insulating film106P when it is cut later with a dicing saw.

The insulating film106P is preferably transparent. If the insulating film106P is transparent, alignment marks that are recognizable through the insulating film106P can be formed on the insulating film106P. Such alignment marks facilitates alignment of a plurality of substructures to be stacked.

The insulating film106P may include a first layer that fills the plurality of grooves104, and a second layer that covers the first layer, the electrode pads48and the passivation film49. In such a case, the first layer and the second layer may be formed of the same material or different materials. The first layer is preferably formed of a resin having a low thermal expansion coefficient. The second layer may be formed of a photosensitive material such as a sensitizer-containing polyimide resin. The first layer may be flattened at the top by, for example, ashing or chemical mechanical polishing (CMP) before forming the second layer on the first layer.

Reference is now made toFIG. 18to describe the step of forming a plurality of openings in the insulating film106P that are intended to expose the plurality of electrode pads48.FIG. 18shows a step that follows the step shown inFIG. 17. Here, a description will initially be given of a case where either the entire insulating film106P or the second layer of the insulating film106P is formed of a negative photosensitive material and photolithography is employed to form the openings in the insulating film106P. In this example, first, all the pre-semiconductor-chip portions30P1and30P2are simultaneously subjected to the exposure of the insulating film106P by using a mask (not shown). The mask has such a pattern that the areas of the insulating film106P where to form the openings are not irradiated with light while the other areas are irradiated with light. The non-irradiated areas of the insulating film106P are soluble in a developing solution, and the irradiated areas become insoluble in the developing solution.

Next, the insulating film106P is developed with the developing solution. As a result, as shown inFIG. 18, a plurality of openings106afor exposing the plurality of electrode pads48are formed in the insulating film106P in each of the pre-semiconductor-chip portions30P1and30P2. Having undergone the development, the insulating film106P makes the insulating layer106.

Now, an example of the method for forming the plurality of openings106ain the insulating film106P will be described for the case where either the entire insulating film106P or the second layer of the insulating film106P is formed of a non-photosensitive material. In this example, first, a negative photoresist layer is formed on the insulating film106P. The photoresist layer is then exposed and developed by the same method as with the exposure and development of the insulating film106P described above. As a result, a plurality of openings are formed in the photoresist layer at positions corresponding to the plurality of electrode pads48. Next, the insulating film106P is selectively etched by using the photoresist layer as the etching mask, whereby the plurality of openings106aare formed in the insulating film106P. The photoresist layer may be subsequently removed, or may be left and used as part of the insulating layer106.

FIG. 19andFIG. 20show a step that follows the step shown inFIG. 18.FIG. 19shows a cross section taken along line19-19ofFIG. 20. In this step, the plurality of electrodes are formed on the insulating layer106by plating, for example. Among the plurality of electrodes, the electrodes32A1to32A4,32D1, and32D2are in contact with and electrically connected to the respective corresponding electrode pads48through the plurality of openings106aof the insulating layer106. The plurality of electrodes other than the electrodes32A1to32A4,32D1, and32D2are in non-contact with the pre-semiconductor-chip portions30P1and30P2.

In this way, there is fabricated a pre-polishing substructure109shown inFIG. 19andFIG. 20. The pre-polishing substructure109has a first surface109acorresponding to the first surface101aof the pre-substructure wafer101, and a second surface109bcorresponding to the second surface101bof the pre-substructure wafer101.

The electrodes are formed of a conductive material such as Cu. In the case of forming the electrodes by plating, a seed layer for plating is initially formed. Next, a photoresist layer is formed on the seed layer. The photoresist layer is then patterned by photolithography to form a frame that has a plurality of openings in which the electrodes are to be accommodated later. Next, plating layers that are intended to constitute respective portions of the electrodes are formed by plating on the seed layer in the openings of the frame. The plating layers have a thickness in the range of 5 to 15 μm, for example. Next, the frame is removed, and portions of the seed layer other than those lying under the plating layers are also removed by etching. The plating layers and the remaining portions of the seed layer under the plating layers thus form the electrodes.

FIG. 21shows a step that follows the step shown inFIG. 19. In this step, using an insulating adhesive, the pre-polishing substructure109is bonded to a plate-shaped jig112shown inFIG. 18, with the first surface109aof the pre-polishing substructure109arranged to face a surface of the jig112. InFIG. 21, the reference numeral113indicates an insulating layer formed by the adhesive. The insulating layer113is to become part of the insulating portion31later.

FIG. 22shows a step that follows the step shown inFIG. 21. In this step, the second surface109bof the pre-polishing substructure109is polished. The polishing is performed until the plurality of grooves104are exposed. The broken line inFIG. 21indicates the level of the second surface109bafter the polishing. By polishing the second surface109bof the pre-polishing substructure109, the pre-polishing substructure109is reduced in thickness, and a substructure110bonded to the jig112is thereby formed. The substructure110is 20 to 80 μm thick, for example. The substructure110has a first surface110acorresponding to the first surface109aof the pre-polishing substructure109, and a second surface110bopposite to the first surface110a. The second surface110bis the polished surface. By polishing the second surface109bof the pre-polishing substructure109until the plurality of grooves104are exposed, the plurality of pre-semiconductor-chip portions30P1and30P2are separated from each other into individual semiconductor chips30. Hereinafter, the semiconductor chip30of the layer portion10S1and the semiconductor chip30of the layer portion10S2will be designated by reference numerals301and302, respectively, when a distinction is needed. The first surface110aof the substructure110corresponds to the first surface30aof the semiconductor chip30shown inFIG. 7. The second surface110bof the substructure110corresponds to the second surface30bof the semiconductor chip30shown inFIG. 7.

FIG. 23shows a step that follows the step shown inFIG. 22. In this step, two substructures110bonded to the respective jigs112are bonded to each other with an insulating adhesive, with the respective second surfaces110barranged to face each other, whereby a stack of two substructures110is fabricated. The two substructures110are bonded to each other such that the semiconductor chip301and the semiconductor chip302are vertically laid over each other.

FIG. 24shows a step that follows the step shown inFIG. 23. In this step, first, the two jigs112are released from the stack of two substructures110. Next, part of the insulating layer113of each substructure110is removed by, for example, etching, so that the terminal component parts of the plurality of electrodes are exposed to form a plurality of conductor pads. Next, a plurality of conductor layers are formed on the plurality of conductor pads, whereby the plurality of terminals4,5,6, and7are formed.

At least either the terminals4and6or the terminals5and7may include a solder layer that is made of a solder material and exposed in the terminal surfaces. An example of the solder material is AuSn. The solder layer has a thickness in the range of 1 to 2 μm, for example. The solder layer is formed on the surface of each of the electrodes directly or via an underlayer by plating, for example.

AuSn is highly adhesive to Au. When either the terminals4and6or the terminals5and7include a solder layer made of AuSn, it is preferred that the other include an Au layer exposed in the terminal surfaces. The Au layer is formed by plating or sputtering, for example.

In this way, there is formed a first layered substructure115including two stacked substructures110, as shown inFIG. 24. Each of the substructures110includes a plurality of preliminary layer portions10P that are arrayed. Each of the preliminary layer portions10P is to become any one of the layer portions10included in the main part2M of the main body2. The substructures110are to be cut later in the positions of the boundaries between every adjacent preliminary layer portions10P. InFIG. 24, the reference symbol110C indicates the cutting positions in the substructures110.

Hereinafter, the preliminary layer portion10P to be the layer portion10S1and the preliminary layer portion10P to be the layer portion10S2will be designated by reference symbols10P1and10P2, respectively, when a distinction is needed. The first layered substructure115includes a plurality of pre-separation main bodies2P that are arrayed. The plurality of pre-separation main bodies2P are to be separated from each other into individual main bodies2later. Each single pre-separation main body2P includes a preliminary layer portion10P1and a preliminary layer portion10P2.

Now, with reference toFIG. 25toFIG. 28, a detailed description will be given of the step of producing a plurality of subpackages1S by using the first layered substructure115.

FIG. 25andFIG. 26show a step that follows the step shown inFIG. 24. In this step, a plurality of first layered substructures115are stacked on each other and every two vertically adjacent first layered substructures115are bonded to each other to fabricate a second layered substructure120.FIG. 25andFIG. 26show an example where 20 first layered substructures115are stacked to fabricate the second layered substructure120. Every two vertically adjacent first layered substructures115are bonded to each other with an adhesive so as to be easily detachable. In this example, as shown inFIG. 26, the second layered substructure120includes a stack of 20 first layered substructures115, each of the first layered substructures115including a stack of two substructures110. The second layered substructure120therefore includes a stack of 40 substructures110. Suppose that each individual substructure110has a thickness of 50 μm. Ignoring the thickness of the adhesive that bonds the two substructures110to each other and the thickness of the adhesive that bonds every two vertically adjacent first layered substructures115to each other, the second layered substructure120has a thickness of 50 μm×40, i.e., 2 mm.

FIG. 27shows a step that follows the step shown inFIG. 25andFIG. 26. In this step, first, the second layered substructure120is cut into at least one block121in which a plurality of pre-separation main bodies2P align both in the stacking direction of the first layered substructures115and a direction orthogonal to the stacking direction.FIG. 27shows an example of the block121. In the block121shown inFIG. 27, twenty pre-separation main bodies2P align in the stacking direction of the first layered substructures115, and four pre-separation main bodies2P align in the direction orthogonal to the stacking direction of the first layered substructures115. In this example, the block121includes eighty pre-separation main bodies2P.

Next, the wiring3is simultaneously formed on all the pre-separation main bodies2P included in the block121. In the case of forming the wiring3by plating, a seed layer for plating is formed first. Then, a photoresist layer is formed on the seed layer and the photoresist layer is patterned by photolithography to form a frame having a plurality of openings in which a plurality of units of wiring3corresponding to the plurality of pre-separation main bodies2P are to be accommodated later. Next, plating layers to constitute portions of the wiring3are formed by plating on the seed layer in the openings of the frame. The frame is then removed, and portions of the seed layer other than those lying under the plating layers are also removed by etching. The plating layers and the remaining portions of the seed layer under the plating layers thus form the wiring3. The wiring3is formed for each of the pre-separation main bodies2P.

The process for forming the subpackages1S then proceeds to the step of separating the plurality of pre-separation main bodies2P, each of which has the wiring3, from each other so that a plurality of subpackages1S are produced. This step will be described with reference toFIG. 28. In this step, first, the block121is cut in the positions of the boundaries between every two pre-separation main bodies2P that are adjacent to each other in the direction orthogonal to the stacking direction of the pre-separation main bodies2P. This produces a plurality of stacks shown in portion (a) ofFIG. 28. Each of the stacks includes a plurality of pre-separation main bodies2P stacked on each other. In each of the stacks, every two adjacent pre-separation main bodies2P are easily detachably bonded to each other by the adhesive that was used to bond every two vertically adjacent first layered substructures115when fabricating the second layered substructure120in the step shown inFIG. 25andFIG. 26. Next, the plurality of pre-separation main bodies2P included in the stack shown in portion (a) ofFIG. 28are separated from each other. This makes the pre-separation main bodies2P into main bodies2, and as a result, there are produced a plurality of subpackages1S each of which includes the main body2and the wiring3. Portion (b) ofFIG. 28shows one of the subpackages1S.

A plurality of subpackages1S are thus produced through the series of steps that have been described with reference toFIG. 12toFIG. 28. So far the description has dealt with the case where the first layered substructure115including two substructures110as shown inFIG. 24is used to produce a plurality of subpackages1S each of which includes two layer portions10. As will be described in relation to other embodiments, however, the number of the substructures110to be included in the first layered substructure115can be varied to produce subpackages1S with different numbers of layer portions10.

Now, a description will be made as to the effects of the composite layered chip package21and the stackable chip package (subpackage1S) according to the present embodiment:

In the composite layered chip package21according to the present embodiment, the plurality of first and second terminals4and5of the subpackages1S are shaped and arranged so that a plurality of pairs of first and second terminals4and5are formed regardless of whether in the reference relative positional relationship or the specific relative positional relationship, each of the plurality of pairs of first and second terminals4and5being made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other. Combinations of the first and second terminals4and5making up the plurality of pairs of first and second terminals4and5in the specific relative positional relationship are different from those in the reference relative positional relationship. In the composite layered chip package21, the first and second subpackages1L and1U are arranged in the specific relative positional relationship where the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U with respect to the reference relative positional relationship.

In the present embodiment, as shown inFIG. 5, the plurality of first terminals4include two or more first terminals4that align in the first direction (the X direction) to form a first terminal row (41C,41R1, and41R2). The plurality of first terminals4further include other two or more first terminals4that align in the first direction (the X direction) to form a third terminal row (42C,42R1, and42R2). The third terminal row is adjacent to the first terminal row in the second direction (the Y direction) orthogonal to the first direction (the X direction).

The plurality of second terminals5include two or more second terminals5that align in the first direction (the X direction) to form a second terminal row (51C,51R1, and51R2). The plurality of second terminals5further include other two or more second terminals5that align in the first direction (the X direction) to form a third terminal row (52C,52R1, and52R2). The third terminal row is adjacent to the second terminal row in the second direction (the Y direction) orthogonal to the first direction (the X direction).

A plurality of pairs of terminals are formed across the first or second terminal row and the third terminal row, each of the plurality of pairs of terminals being made up of two terminals electrically connected to each other. The two terminals are one of the two or more first or second terminals that form the first or second terminal row and one of the other two or more first or second terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). The specific relative positional relationship is such that the second subpackage1U is displaced in the second direction (the Y direction) with respect to the reference relative positional relationship.

According to the present embodiment, a plurality of subpackages1S of the same configuration are arranged in the specific relative positional relationship shown inFIG. 1to construct the composite layered chip package21. In such a composite layered chip package21, as has been described with reference toFIG. 8, some of a plurality of signals associated with the one or more semiconductor chips30in the subpackages1S can easily be varied from one subpackage1S to another. According to the present embodiment, it is therefore possible to stack a plurality of subpackages1S of the same configuration into a composite layered chip package21while varying the functions of the subpackages1S from one subpackage1S to another.

In the present embodiment, only either the plurality of first terminals4or the plurality of second terminals5may include the two or more first or second terminals that align in the first direction (the X direction) to form a third terminal row. In such a case also, it is possible to construct a composite layered chip package21by arranging a plurality of subpackages1S in the specific relative positional relationship with each other.

A plurality of subpackages1S according to the present embodiment may also be arranged in the reference relative positional relationship shown inFIG. 2to construct the composite layered chip package22. In the composite layered chip package22, a plurality of signals associated with the one or more semiconductor chips30in the subpackages1S are the same among all the subpackages1S. Such a composite layered chip package22is suited to the case of operating the plurality of subpackages1S in parallel, with the same function given to the plurality of subpackages1S.

According to the subpackage1S of the present embodiment, it is thus possible to construct a composite layered chip package in two ways of configuration by simply changing the relative positional relationship between a plurality of subpackages1S having the same configuration.

The plurality of third and fourth terminals6and7of the subpackage1S according to the present embodiment are shaped and arranged so that the plurality of third terminals6of the first subpackage1L are in contact with the plurality of fourth terminals7of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship. Consequently, according to the present embodiment, the composite layered chip package21can be configured so that some of a plurality of signals associated with the one or more semiconductor chips30in the subpackages1S vary from one subpackage1S to another while some others of the plurality of signals remain the same among all the subpackages1S.

In the subpackage1S according to the present embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10S1which is located closest to the top surface2Ma of the main part2M, whereas the plurality of terminals5and7are formed by using the plurality of electrodes32of the layer portion10S2which is located closest to the bottom surface2Mb of the main part2M. The present embodiment thus facilitates the formation of the plurality of electrodes4,5,6, and7.

In the subpackage1S according to the present embodiment, the plurality of wires W include the plurality of common wires WA1to WA4that are used for a purpose common to all the layer portions10S1and10S2in the main part2M, and the plurality of layer-dependent wires WR1and WR5that are used by different layer portions. The plurality of electrodes32include the common electrodes32A1to32A4that are electrically connected to the common wires WA1to WA4, and the selective connection electrode32D2that is selectively electrically connected to only one of the plurality of layer-dependent wires WR1and WR5that is used by the layer portion to which the selective connection electrode belongs. In at least one of the plurality of layer portions10S1and10S2, the common electrodes32A1to32A4and the selective connection electrode32D2are electrically connected to the semiconductor chip30. Consequently, according to the present embodiment, it is possible that the layer-dependent wire to which the semiconductor chip30is to be connected is varied from one layer portion10to another within a single subpackage1S.

Second Embodiment

A second embodiment of the invention will now be described. First, reference is made toFIG. 29toFIG. 35to describe the configurations of a composite layered chip package and a stackable chip package according to the present embodiment.FIG. 29is a perspective view of the composite layered chip package according to the present embodiment.FIG. 30is a perspective view of a composite layered chip package that is formed by arranging four subpackages ofFIG. 29in a reference relative positional relationship with each other.FIG. 31is a perspective view of the stackable chip package according to the present embodiment.FIG. 32is a perspective view showing the stackable chip package ofFIG. 31as viewed from below.FIG. 33is a plan view showing a plurality of terminals of the stackable chip package shown inFIG. 31.FIG. 34is a plan view showing a layer portion included in the stackable chip package shown inFIG. 31.FIG. 35is a perspective view of the layer portion shown inFIG. 34.

The composite layered chip package22shown inFIG. 30is formed by arranging the four subpackages1A to1D in the reference relative positional relationship with each other. The composite layered chip package21according to the present embodiment shown inFIG. 29is formed by arranging the four subpackages1A to1D in a specific relative positional relationship, different from the reference relative positional relationship, with each other.

Now, the plurality of terminals4,5,6, and7of the present embodiment will be described in detail. As shown inFIG. 31andFIG. 32, each subpackage1S is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.FIG. 33shows the shape and arrangement of the plurality of terminals4,5,6, and7when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction).

As shown inFIG. 33, the plurality of first terminals4include two or more first terminals4that align in a first direction to form a first terminal row. The plurality of second terminals5include two or more second terminals5that align in the first direction to form a second terminal row. At least one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction. Of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In the present embodiment, in particular, the first terminal row is formed by three or more first terminals that align in the first direction, and the second terminal row is formed by three or more second terminals that align in the first direction. Of the three or more first/second terminals, two that are located at opposite ends of the first/second terminal row are electrically connected to each other.

Specifically, the plurality of first terminals4include: five first terminals4C1,4C2,4C3,4C4, and4C01that align in the X direction to form a terminal row40C; five first terminals4R1,4R2,4R3,4R4, and4R01that align in the X direction to form a terminal row40R1; and five first terminals4R5,4R6,4R7,4R8, and4R05that align in the X direction to form a terminal row40R2. In each of the terminal rows, two terminals located at opposite ends are electrically connected to each other. The X direction corresponds to the first direction. Each of the terminal rows40C,40R1, and40R2corresponds to the first terminal row.

The plurality of second terminals5include: five second terminals5C1,5C2,5C3,5C4, and5C01that align in the X direction to form a terminal row50C; five second terminals5R1,5R2,5R3,5R4, and5R01that align in the X direction to form a terminal row50R1; and five second terminals5R5,5R6,5R7,5R8, and5R05that align in the X direction to form a terminal row50R2. In each of the terminal rows, two terminals located at opposite ends are electrically connected to each other. Each of the terminal rows50C,50R1, and50R2corresponds to the second terminal row.

In all the terminal rows, the five terminals making up each terminal row are at equal pitches. The amount of displacement of the second subpackage1U in the specific relative positional relationship with respect to the reference relative positional relationship is the same as the foregoing pitch.

The terminal rows40R1and40R2are offset from each other in the Y direction. The terminal rows50R1and50R2are offset from each other in the Y direction.

The plurality of third terminals6include four terminals6A1to6A4. The terminals6A1to6A4are each shaped to be elongated in the X direction as compared with the first terminals4. A pair of terminals6A1and6A3and a pair of terminals6A2and6A4are offset from each other in the Y direction. The interval between the terminals6A1and6A3and the interval between the terminals6A2and6A4are both greater than the amount of displacement of the second subpackage1U in the specific relative positional relationship with respect to the reference relative positional relationship. The plurality of fourth terminals7include four terminals7A1to7A4. The shape and arrangement of the terminals7A1to7A4are the same as those of the terminals6A1to6A4.

In each subpackage1S, two terminals in each of the following pairs of terminals coincide with each other in position when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction): (4C1,5C1), (4C2,5C2), (4C3,5C3), (4C4,5C4), (4C01,5C01), (4R1,5R1), (4R2,5R2), (4R3,5R3), (4R4,5R4), (4R01,5R01), (4R5,5R5), (4R6,5R6), (4R7,5R7), (4R8,5R8), (4R05,5R05), (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4).

Now, the plurality of wires W will be described in detail. The plurality of wires W are disposed on the side surface2cof the main body2and pass through all the layer portions10S1and10S2in the main part2M. The plurality of wires W include wires WC1, WC2, WC3, WC4, WC01, WR1, WR2, WR3, WR4, WR01, WR5, WR6, WR7, WR8, WR05, WA1, WA2, WA3, and WA4that electrically connect two terminals in the respective pairs of terminals (4C1,5C1), (4C2,5C2), (4C3,5C3), (4C4,5C4), (4C01,5C01), (4R1,5R1), (4R2,5R2), (4R3,5R3), (4R4,5R4), (4R01,5R01), (4R5,5R5), (4R6,5R6), (4R7,5R7), (4R8,5R8), (4R05,5R05), (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4). Note that the wires WC01, WR01, and WRO5may be omitted.

The plurality of electrodes32will now be described. As with the first embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10S1, and the plurality of terminals5and7are formed by using the plurality of electrodes32of the layer portion10S2.

FIG. 34andFIG. 35illustrate the shape and arrangement of the plurality of electrodes32of the layer portion10S1. The shape and arrangement of the plurality of electrodes32of the layer portion10S2when viewed from the side of the first surface30aof the semiconductor chip30are a mirror image to those of the plurality of electrodes32shown inFIG. 34andFIG. 35.

The plurality of electrodes32include electrodes32C1to32C4,32C01,32R1to32R8,32R01,32R05,32A1to32A4,32D1, and32D2. InFIG. 35, the reference symbols of the electrodes other than the electrodes32A1to32A4,32D1, and32D2are omitted.

The electrodes32C1to32C4,32C01,32R1to32R8,32R01,32R05, and32A1to32A4of the layer portion10S1include terminal component parts that are used for forming the terminals4C1to4C4,4C01,4R1to4R8,4R01,4R05, and6A1to6A4.

The electrodes32C1to32C4,32C01,32R1to32R8,32R01,32R05, and32A1to32A4of the layer portion10S2include terminal component parts that are used for forming the terminals5C1to5C4,5C01,5R1to5R8,5R01,5R05, and7A1to7A4.

The electrodes32C1to32C4,32C01,32R1to32R8,32R01,32R05, and32A1to32A4have respective end faces located in the end face31cof the insulating portion31, and are electrically connected to the wires WC1to WC4, WC01, WR1to WR8, WR01, WR05, and WA1to WA4via those end faces.

The electrodes32A1to32A4,32D1, and32D2are the same as those of the first embodiment. None of the electrodes32C1to32C4,32C01,32R1to32R8,32R01, and32R05are in contact with the semiconductor chip30.

The electrode32D1has an end face located in the end face31cof the insulating portion31. This end face is located near the end face of the electrode32C1. The electrode32D2has first and second branch portions. Each of the first and second branch portions has an end face located in the end face31cof the insulating portion31. The end face of the first branch portion is located near the end face of the electrode32R1. The end face of the second branch portion is located near the end face of the electrode32R5.

In each of the layer portions10S1and10S2, the wire WC1is broadened to come into contact with the end face of the electrode32D1, as with the first embodiment. In the layer portion10S1, the wire WR1is broadened in part to come into contact with the end face of the first branch portion of the electrode32D2. In the layer portion10S2, the wire WR5is broadened in part to come into contact with the end face of the second branch portion of the electrode32D2.

Now, the reference relative positional relationship and the specific relative positional relationship in the present embodiment will be described in detail. The reference relative positional relationship will be described first, with reference toFIG. 30. The reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the second subpackage1U (the Z direction), the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position while the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position. When in the reference relative positional relationship, terminals4and6of the subpackage1L and terminals5and7of the subpackage1U that coincide with each other in position when viewed in the Z direction are in contact with each other and electrically connected to each other. In this way, there are formed a plurality of pairs of first and second terminals each of which is made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other.

The specific relative positional relationship shown inFIG. 29is such that the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U with respect to the reference relative positional relationship shown inFIG. 30. In the present embodiment, the specific relative positional relationship is particularly such that the second subpackage1U is displaced in the X direction (the first direction) with respect to the reference relative positional relationship.

Combinations of the first terminals4of the first subpackage1L and the second terminals5of the second subpackage1U making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship. In the example shown inFIG. 29, the second subpackage1U is displaced in the direction from the side surface2eof the main body2toward the side surface2fof the main body2, with respect to the reference relative positional relationship. It should be noted that the specific relative positional relationship may be such that the second subpackage1U is displaced in the direction from the side surface2ftoward the side surface2e, with respect to the reference relative positional relationship.

When in the specific relative positional relationship shown inFIG. 29, the plurality of pairs of first and second terminals, each of which is made up of one of the first terminals4of the first subpackage1L and one of the second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other, are as follows: (4C2,5C1), (4C3,5C2), (4C4,5C3), (4C01,5C4), (4R2,5R1), (4R3,5R2), (4R4,5R3), (4R01,5R4), (4R6,5R5), (4R7,5R6), (4R8,5R7), and (4R05,5R8).

When in a not-shown specific relative positional relationship where the second subpackage1U is displaced in the direction from the side surface2ftoward the side surface2ewith respect to the reference relative positional relationship, the terminals5C2to5C4,5C01,5R2to5R4,5R01,5R6to5R8,5R05, and7A1to7A4of the second subpackage1U are in contact with and electrically connected to the terminals4C1to4C4,4R1to4R8, and6A1to6A4of the first subpackage1L.

Because of the shape and arrangement of the terminals6A1to6A4and7A1to7A4described above, there are formed a plurality of pairs of terminals (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4) in each of which the two terminals are in contact with and electrically connected to each other, across the terminals6A1to6A4of the first subpackage1L and the terminals7A1to7A4of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

Next, the flow of a plurality of signals in the composite layered chip package21shown inFIG. 29and the composite layered chip package22shown inFIG. 30will be described.FIG. 36is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package21shown inFIG. 29.FIG. 37is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package22shown inFIG. 30.

In each subpackage1S, the same signal appears on a plurality of terminals that are electrically connected to each other. More specifically, the signal to appear on the terminal4C01is the same as that on the terminal4C1. The signal to appear on the terminal5C01is the same as that on the terminal5C1. The signals to appear on the terminals5C1to5C4, and5C01are the same as those on the terminals4C1to4C4, and4C01, respectively.

FIG. 36shows an example where the signals S4, S3, S2, and S1are supplied to the terminals5C1,5C2,5C3, and5C4of the subpackage1D as shown in portion (d) ofFIG. 36. In this case, in the subpackage1D, the signals S4, S3, S2, S1, and S4appear on the terminals4C1,4C2,4C3,4C4, and4C01, respectively.

When in the specific relative positional relationship shown inFIG. 29, the terminals5C1,5C2,5C3, and5C4of the subpackage1C are in contact with the terminals4C2,4C3,4C4, and4C01of the subpackage1D. Consequently, in the subpackage1C, as shown in portion (c) ofFIG. 36, the signals S3, S2, S1, and S4are transmitted to the terminals5C1,5C2,5C3, and5C4. As a result, the signals S3, S2, S1, S4, and S3appear on the terminals4C1,4C2,4C3, and4C4, and4C01, respectively.

In the subpackage1B, as shown in portion (b) ofFIG. 36, the signals S2, S1, S4, and S3are transmitted to the terminals5C1,5C2,5C3, and5C4. As a result, the signals S2, S1, S4, S3, and S2appear on the terminals4C1,4C2,4C3,4C4, and4C01, respectively.

In the subpackage1A, as shown in portion (a) ofFIG. 36, the signals S1, S4, S3, and S2are transmitted to the terminals5C1,5C2,5C3, and5C4. As a result, the signals S1, S4, S3, S2, and S1appear on the terminals4C1,4C2,4C3, and4C4, and4C01, respectively.

In each of the layer portions10S1and10S2, the terminals4C1and5C1are electrically connected to the semiconductor chip30through the wire WC1and the electrode32D1. As described above, when in the specific relative positional relationship shown inFIG. 29, the signal to appear on the terminals4C1and5C1varies from one subpackage1S to another. Consequently, in the composite layered chip package21shown inFIG. 29, the signals associated with the semiconductor chips30of the respective corresponding layers of different subpackages1S through the wire WC1and the electrodes32D1can be varied from one subpackage1S to another. In the example shown inFIG. 36, the signal associated with the semiconductor chips30of the layer portions10S1and10S2through the wire WC1and the electrodes32D1in the subpackage1A is the signal S1. The signal S2is associated in the subpackage1B, the signal S3in the subpackage1C, and the signal S4in the subpackage1D.

On the other hand, when in the reference relative positional relationship shown inFIG. 30, the signals to appear on the terminals4C1to4C4,4C01,5C1to5C4, and5C01do not vary from one subpackage1S to another as shown inFIG. 37.FIG. 37shows an example where the signals S1, S2, S3, and S4are supplied to the terminals5C1,5C2,5C3, and5C4of the subpackage1D. In the composite layered chip package22shown inFIG. 30, the same signals are associated with the semiconductor chips30of the respective corresponding layers in all the subpackages1A to1D, through the wire WC1and the electrodes32D1.

The mode of signal flow described with reference toFIG. 36andFIG. 37also applies to the group of terminals4R1to4R4,4R01,5R1to5R4and5R01, and the group of terminals4R5to4R8,4R05,5R5to5R8and5R05.

The present embodiment may be configured so that only one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction (the X direction) and, of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In such a case also, it is possible to construct a composite layered chip package21by arranging a plurality of subpackages1S in the specific relative positional relationship with each other.

Third Embodiment

A third embodiment of the invention will now be described. First, reference is made toFIG. 38toFIG. 44to describe the configurations of a composite layered chip package and a stackable chip package according to the present embodiment.FIG. 38is a perspective view of the composite layered chip package according to the present embodiment.FIG. 39is a perspective view of a composite layered chip package that is formed by arranging two subpackages ofFIG. 38in a reference relative positional relationship with each other.FIG. 40is a perspective view of the stackable chip package according to the present embodiment.FIG. 41is a perspective view showing the stackable chip package ofFIG. 40as viewed from below.FIG. 42is a plan view showing a plurality of terminals of the stackable chip package shown inFIG. 40.FIG. 43is a plan view showing a layer portion included in the stackable chip package shown inFIG. 40.FIG. 44is a perspective view of the layer portion shown inFIG. 43.

The composite layered chip package23according to the present embodiment shown inFIG. 38includes a first subpackage1L and a second subpackage1U. The second subpackage1U is stacked on and electrically connected to the first subpackage1L. As with the first embodiment, any subpackage will be designated by reference symbol1S. Each subpackage1S is the stackable chip package according to the present embodiment.

The composite layered chip package24shown inFIG. 39is formed by arranging the two subpackages1L and1U shown inFIG. 38in the reference relative positional relationship with each other. The composite layered chip package23according to the present embodiment shown inFIG. 38is formed by arranging the two subpackages1L and1U in a specific relative positional relationship, different from the reference relative positional relationship, with each other.

As shown inFIG. 40andFIG. 41, the subpackage1S or the stackable chip package according to the present embodiment includes a main body2and wiring3. The main body2has a main part2M. The wiring3includes a plurality of wires W. The main part2M of the present embodiment includes four layer portions10S1,10S2,10S3, and10S4. The four layer portions10S1,10S2,10S3, and10S4are arranged in this order from the top. Hereinafter, any layer portion will be designated by reference numeral10. The layer portion10S1is located closest to the top surface2Ma of the main part2M among the plurality of layer portions, and therefore corresponds to the first layer portion according to the invention. The layer portion10S4is located closest to the bottom surface2Mb of the main part2M among the plurality of layer portions, and therefore corresponds to the second layer portion according to the invention.

The layer portion10S1and the layer portion10S4are arranged so that the second surfaces30bof the respective semiconductor chips30included therein face each other. The layer portion10S1is arranged with the first surface30aof the semiconductor chip30upward. The layer portion10S4is arranged with the first surface30aof the semiconductor chip30downward. The layer portions10S2and10S3may each be situated in the same orientation as that of the layer portion10S1or that of the layer portion10S4. In the example shown inFIG. 40andFIG. 41, the layer portion10S2is situated in the same orientation as that of the layer portion10S1, while the layer portion10S3is situated in the same orientation as that of the layer portion10S4. The layer portions10S1to10S4are bonded with an adhesive, for example.

Now, the plurality of terminals4,5,6, and7of the present embodiment will be described in detail. As shown inFIG. 40andFIG. 41, each subpackage1S is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.FIG. 42shows the shape and arrangement of the plurality of terminals4,5,6, and7when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction).

As shown inFIG. 42, the plurality of first terminals4include terminals4C11to4C14,4R11to4R18,4C21to4C24, and4R21to4R28. Pairs of terminals that align in the X direction, namely, (4C11,4C12), (4C13,4C14), (4R11,4R12), (4R13,4R14), (4R15,4R16), and (4R17,4R18), each form a first terminal row. Other pairs of terminals that align in the X direction, namely, (4C21,4C22), (4C23,4C24), (4R21,4R22), (4R23,4R24), (4R25,4R26), and (4R27,4R28), each form a third terminal row. The third terminal rows (4C21,4C22), (4C23,4C24), (4R21,4R22), (4R23,4R24), (4R25,4R26), and (4R27,4R28) are adjacent to the first terminal rows (4C11,4C12), (4C13,4C14), (4R11,4R12), (4R13,4R14), (4R15,4R16), and (4R17,4R18), respectively, in the Y direction. The X direction corresponds to the first direction according to the invention. The Y direction corresponds to the second direction according to the invention.

A plurality of pairs of terminals are formed across a first terminal row and an adjacent third terminal row, each of the plurality of pairs of terminals being made up of two terminals electrically connected to each other. The two terminals are one of two first terminals that form a first terminal row and one of other two first terminals that form a third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). Specifically, across the first terminal row and the third terminal row, there are formed the following pairs of two electrically-connected terminals: (4C11,4C22), (4C12,4C21), (4C13,4C24), (4C14,4C23), (4R11,4R22), (4R12,4R21), (4R13,4R24), (4R14,4R23), (4R15,4R26), (4R16,4R25), (4R17,4R28), and (4R18,4R27).

The plurality of second terminals5include terminals5C11to5C14,5R11to5R18,5C21to5C24, and5R21to5R28. Pairs of terminals that align in the X direction, namely, (5C11,5C12), (5013,5C14), (5R11,5R12), (5R13,5R14), (5R15,5R16), and (5R17,5R18), each form a second terminal row. Other pairs of terminals that align in the X direction, namely, (5C21,5C22), (5023,5C24), (5R21,5R22), (5R23,5R24), (5R25,5R26), and (5R27,5R28), each form a third terminal row. The third terminal rows (5C21,5C22), (5023,5024), (5R21,5R22), (5R23,5R24), (5R25,5R26), and (5R27,5R28) are adjacent to the second terminal rows (5011,5C12), (5C13,5C14), (5R11,5R12), (5R13,5R14), (5R15,5R16), and (5R17,5R18), respectively, in the Y direction.

A plurality of pairs of terminals are formed across a second terminal row and an adjacent third terminal row, each of the plurality of pairs of terminals being made up of two terminals electrically connected to each other. The two terminals are one of two second terminals that form a second terminal row and one of other two second terminals that form a third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). Specifically, across the second terminal row and the third terminal row, there are formed the following pairs of two electrically-connected terminals: (5C11,5C22), (5C12,5C21), (5C13,5C24), (5C14,5C23), (5R11,5R22), (5R12,5R21), (5R13,5R24), (5R14,5R23), (5R15,5R26), (5R16,5R25), (5R17,5R28), and (5R18,5R27).

The plurality of third terminals6include four terminals6A1to6A4. The plurality of fourth terminals7include four terminals7A1to7A4. The shape and arrangement of the terminals6A1to6A4and7A1to7A4are the same as in the first embodiment.

In the subpackage1S, there are a plurality of pairs of terminals in each of which the two terminals making up the pair coincide with each other in position when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction). Such a plurality of pairs of terminals are the same as in the first embodiment.

The plurality of wires W are disposed on the side surface2cof the main body2and pass through all the layer portions10S1to10S4in the main part2M. The plurality of wires W include wires WC1to WC4, WR1to WR8, and WA1to WA4which are the same as those of the first embodiment.

The plurality of electrodes32will now be described. In the present embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10S1, and the plurality of terminals5and7are formed by using the plurality of electrodes32of the layer portion10S4.

FIG. 43andFIG. 44illustrate the shape and arrangement of the plurality of electrodes32of the layer portions10S1and10S2. The shape and arrangement of the plurality of electrodes32of the layer portions10S3and10S4when viewed from the side of the first surface30aof each semiconductor chip30are a mirror image to those of the plurality of electrodes32shown inFIG. 43andFIG. 44.

The plurality of electrodes32include electrodes32C11to32C14,32C21to32C24,32R11to32R18,32R21to32R28,32A1to32A4,32D1, and32D2. InFIG. 44, the reference symbols of the electrodes other than the electrodes32A1to32A4,32D1, and32D2are omitted.

The electrodes32C11to32C14,32R11to32R18,32C21to32C24,32R21to32R28, and32A1to32A4of the layer portion10S1include terminal component parts that are used for forming the terminals4C11to4C14,4R11to4R18,4C21to4C24,4R21to4R28, and6A1to6A4.

The electrodes32C11to32C14,32R11to32R18,32C21to32C24,32R21to32R28, and32A1to32A4of the layer portion10S4include terminal component parts that are used for forming the terminals5C11to5C14,5R11to5R18,5C21to5C24,5R21to5R28, and7A1to7A4.

The electrodes32C11to32C14,32R11to32R18, and32A1to32A4have respective end faces located in the end face31cof the insulating portion31, and are electrically connected to the wires WC1to WC4, WR1to WR8, and WA1to WA4via those end faces. P A plurality of pairs of electrodes are formed across a group of electrodes32C11to32C14and32R11to32R18and a group of electrodes32C21to32C24and32R21to32R28, each of the plurality of pairs of electrodes being made up of two electrodes that are electrically connected to each other. The two electrodes are ones that are not adjacent to each other in the second direction (the Y direction). Specifically, there are formed the following pairs of two electrically-connected electrodes: (32C11,32C22), (32C12,32C21), (32C13,32C24), (32C14,32C23), (32R11,32R22), (32R12,32R21), (32R13,32R24), (32R14,32R23), (32R15,32R26), (32R16,32R25), (32R17,32R28), and (32R18,32R27).

The electrode32D1has first and second branch portions. Each of the first and second branch portions has an end face located in the end face31cof the insulating portion31. The end face of the first branch portion is located near the end face of the electrode32C11. The end face of the second branch portion is located near the end face of the electrode32C13.

The electrode32D2has first to fourth branch portions. Each of the first to fourth branch portions has an end face located in the end face31cof the insulating portion31. The end face of the first branch portion is located near the end face of the electrode32R11. The end face of the second branch portion is located near the end face of the electrode32R13. The end face of the third branch portion is located near the end face of the electrode32R15. The end face of the fourth branch portion is located near the end face of the electrode32R17.

In each of the layer portions10S1and10S2, the wire WC1is broadened in part to come into contact with the end face of the first branch portion of the electrode32D1. The electrode32D1of each of the layer portions10S1and10S2is thereby electrically connected to the wire WC1. In the layer portion10S1, the wire WR1is broadened in part to come into contact with the end face of the first branch portion of the electrode32D2. The electrode32D2of the layer portion10S1is thereby electrically connected to the wire WR1. In the layer portion10S2, the wire WR3is broadened in part to come into contact with the end face of the second branch portion of the electrode32D2. The electrode32D2of the layer portion10S2is thereby electrically connected to the wire WR3.

In each of the layer portions10S3and10S4, the wire WC3is broadened in part to come into contact with the end face of the second branch portion of the electrode32D1. The electrode32D1of each of the layer portions10S3and10S4is thereby electrically connected to the wire WC3. In the layer portion10S3, the wire WR5is broadened in part to come into contact with the end face of the third branch portion of the electrode32D2. The electrode32D2of the layer portion10S3is thereby electrically connected to the wire WR5. In the layer portion10S4, the wire WR7is broadened in part to come into contact with the end face of the fourth branch portion of the electrode32D2. The electrode32D2of the layer portion10S4is thereby electrically connected to the wire WR7.

The electrodes32D1and32D2each correspond to the selective connection electrode according to the invention. The wires WA1to WA4correspond to the common wires according to the invention. The wires WC1, WC3, WR1, WR3, WR5, and WR7are used by different ones of the plurality of layer portions. These wires therefore correspond to the layer-dependent wires according to the invention.

The wires WA1to WA4, WC1, WC3, WR1, WR3, WR5, and WR7are used for electrical connection to the semiconductor chip30. These wires therefore correspond to the chip connection wires according to the invention. The wires WC2, WC4, WR2, WR4, WR6, and WR8are electrically non-connected to the semiconductor chip30. These wires therefore correspond to the bypass wires according to the present invention.

Now, the reference relative positional relationship and the specific relative positional relationship in the present embodiment will be described in detail. The reference relative positional relationship will be described first, with reference toFIG. 39. The reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the second subpackage1U (the Z direction), the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position while the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position. When in the reference relative positional relationship, terminals4and6of the subpackage1L and terminals5and7of the subpackage1U that coincide with each other in position when viewed in the Z direction are in contact with each other and electrically connected to each other. In this way, there are formed a plurality of pairs of first and second terminals each of which is made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other.

The specific relative positional relationship shown inFIG. 38is such that the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U with respect to the reference relative positional relationship shown inFIG. 39. In the present embodiment, the specific relative positional relationship is particularly such that the second subpackage1U is displaced in the Y direction (the second direction) with respect to the reference relative positional relationship.

Combinations of the first terminals4of the first subpackage1L and the second terminals5of the second subpackage1U making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship. In the example shown inFIG. 38, the second subpackage1U is displaced in the direction from the side surface2cof the main body2toward the side surface2dof the main body2, with respect to the reference relative positional relationship. It should be noted that the specific relative positional relationship may be such that the second subpackage1U is displaced in the direction from the side surface2dtoward the side surface2c, with respect to the reference relative positional relationship.

When in the specific relative positional relationship shown inFIG. 38, the plurality of pairs of first and second terminals, each of which is made up of one of the first terminals4of the first subpackage1L and one of the second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other, are as follows: (4C21,5C11), (4C22,5C12), (4C23,5C13), (4C24,5C14), (4R21,5R11), (4R22,5R12), (4R23,5R13), (4R24,5R14), (4R25,5R15), (4R26,5R16), (4R27,5R17), and (4R28,5R18).

When in a not-shown specific relative positional relationship where the second subpackage1U is displaced in the direction from the side surface2dtoward the side surface2cwith respect to the reference relative positional relationship, the terminals5C21to5C24,5R21to5R28, and7A1to7A4of the second subpackage1U are in contact with and electrically connected to the terminals4C11to4C14,4R11to4R18, and6A1to6A4of the first subpackage1L.

As in the first embodiment, there are formed a plurality of pairs of terminals (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4) in each of which the two terminals are in contact with and electrically connected to each other, across the terminals6A1to6A4of the first subpackage1L and the terminals7A1to7A4of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

Next, the flow of a plurality of signals in the composite layered chip package23shown inFIG. 38and the composite layered chip package24shown inFIG. 39will be described.FIG. 45is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package23shown inFIG. 38.FIG. 46is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package24shown inFIG. 39.

In each subpackage1S, the same signal appears on a plurality of terminals that are electrically connected to each other. More specifically, the signals to appear on the terminals4C21and4C22are the same as those on the terminals4C12and4C11, respectively. The signals to appear on the terminals5C21and5C22are the same as those on the terminals5C12and5C11, respectively. The signals to appear on the terminals5C11,5012,5C21, and5022are the same as those on the terminals4C11,4C12,4C21, and4C22, respectively.

FIG. 45shows an example where the signals S2and S1are supplied to the terminals5C11and5C12of the subpackage1L as shown in portion (b) ofFIG. 45. In this case, in the subpackage1L, the signals S2and S1appear on the terminals4C11and4C12, respectively, while the signals S1and S2appear on the terminals4C21and4C22, respectively.

When in the specific relative positional relationship shown inFIG. 38, the terminals5011and5C12of the subpackage1U are in contact with the terminals4C21and4C22of the subpackage1L. Consequently, in the subpackage1U, as shown in portion (a) ofFIG. 45, the signals S1and S2are transmitted to the terminals5011and5012. As a result, the signals S1and S2appear on the terminals4C11and4C12, respectively.

In each of the layer portions10S1and10S2, the terminals4C11and5C11are electrically connected to the semiconductor chip30through the wire WC1and the electrode32D1. As described above, when in the specific relative positional relationship shown inFIG. 38, the signal to appear on the terminals4C11and5011varies between the subpackages1S (1L and1U). Consequently, in the composite layered chip package23shown inFIG. 38, the signal associated with the semiconductor chips30of the layer portions1051and10S2through the wire WC1and the electrodes32D1can be varied between the subpackages1S. In the example shown inFIG. 45, the signal associated with the semiconductor chips30of the layer portions10S1and10S2through the wire WC1and the electrodes32D1in the subpackage1U is the signal51, whereas the signal S2is associated in the subpackage1L.

On the other hand, when in the reference relative positional relationship shown inFIG. 39, the signals to appear on the terminals4C11,4C12,4C21,4C22,5C11,5C12,5C21, and5C22do not vary between the subpackages1S as shown inFIG. 46.FIG. 46shows an example where the signals51and S2are supplied to the terminals5C11and5C12of the subpackage1L. In the composite layered chip package24shown inFIG. 39, the signal associated with the semiconductor chips30of the layer portions1051and10S2through the wire WC1and the electrodes32D1is the same between the subpackages1U and1L.

The mode of signal flow described with reference toFIG. 45andFIG. 46also applies to groups of terminals similar to the group of terminals4C11,4C12,4C21,4C22,5C11,5C12,5C21, and5C22, such as a group of terminals4C13,4C14,4C23,4C24,5C13,5C14,5C23, and5C24.

Now, a description will be made as to the flow of a plurality of signals for the case where the composite layered chip package23shown inFIG. 38is used to construct the memory device shown inFIG. 10. In the subpackages1U and1L of the composite layered chip package23shown inFIG. 38, the terminals6A1and7A1are electrically connected to the wire WA1, the terminals6A2and7A2are electrically connected to the wire WA2, the terminals6A3and7A3are electrically connected to the wire WA3, and the terminals6A4and7A4are electrically connected to the wire WA4. As a result, there are formed a plurality of electrical paths that lead from the terminals6A1-6A4of the subpackage1U to the terminals7A1-7A4of the subpackage1L. The plurality of electrical paths constitute parts of the data bus91and the one or more common lines92.

The chip enable signal CE1is supplied to the terminal4C11of the subpackage1U or the terminal5C12of the subpackage1L. The chip enable signal CE3is supplied to the terminal4C12of the subpackage1U or the terminal5C11of the subpackage1L. The chip enable signal CE2is supplied to the terminal4C13of the subpackage1U or the terminal5C14of the subpackage1L. The chip enable signal CE4is supplied to the terminal4C14of the subpackage1U or the terminal5C13of the subpackage1L.

In the composite layered chip package23, the chip enable signal CE1is supplied only to the semiconductor chips30of the layer portions10S1and10S2of the subpackage1U, i.e., the memory chips MC1and MC2. The chip enable signal CE2is supplied only to the semiconductor chips30of the layer portions10S3and10S4of the subpackage1U, i.e., the memory chips MC3and MC4. The chip enable signal CE3is supplied only to the semiconductor chips30of the layer portions10S1and10S2of the subpackage1L, i.e., the memory chips MC5and MC6. The chip enable signal CE4is supplied only to the semiconductor chips30of the layer portions10S3and10S4of the subpackage1L, i.e., the memory chips MC7and MC8.

In the layer portion10S1of the subpackage1U, the ready/busy signal R/B1is output from the electrode32D2. The signal R/B1is transmitted to the wire WR1of the subpackage1U and is output from the terminal4R11of the subpackage1U or the terminal5R12of the subpackage1L. In the layer portion10S2of the subpackage1U, the ready/busy signal R/B2is output from the electrode32D2. The signal R/B2is transmitted to the wire WR3of the subpackage1U and is output from the terminal4R13of the subpackage1U or the terminal5R14of the subpackage1L.

In the layer portion10S3of the subpackage1U, the ready/busy signal R/B3is output from the electrode32D2. The signal R/B3is transmitted to the wire WR5of the subpackage1U and is output from the terminal4R15of the subpackage1U or the terminal5R16of the subpackage1L. In the layer portion10S4of the subpackage1U, the ready/busy signal R/B4is output from the electrode32D2. The signal R/B4is transmitted to the wire WR7of the subpackage1U and is output from the terminal4R17of the subpackage1U or the terminal5R18of the subpackage1L.

In the layer portion10S1of the subpackage1L, the ready/busy signal R/B5is output from the electrode32D2. The signal R/B5is transmitted to the wire WR1of the subpackage1L and is output from the terminal4R12of the subpackage1U or the terminal5R11of the subpackage1L. In the layer portion10S2of the subpackage1L, the ready/busy signal R/B6is output from the electrode32D2. The signal R/B6is transmitted to the wire WR3of the subpackage1L and is output from the terminal4R14of the subpackage1U or the terminal5R13of the subpackage1L.

In the layer portion10S3of the subpackage1L, the ready/busy signal R/B7is output from the electrode32D2. The signal R/B7is transmitted to the wire WR5of the subpackage1L and is output from the terminal4R16of the subpackage1U or the terminal5R15of the subpackage1L. In the layer portion10S4of the subpackage1L, the ready/busy signal R/B8is output from the electrode32D2. The signal R/B8is transmitted to the wire WR7of the subpackage1L and is output from the terminal4R18of the subpackage1U or the terminal5R17of the subpackage1L.

Next, a method for manufacturing the subpackage1S according to the present embodiment will be described. The manufacturing method is the same as that of the first embodiment up to the step of forming the substructure110bonded to the jig112as shown inFIG. 22. The substructure110bonded to the jig112will hereinafter be referred to as a first substructure110.

FIG. 47shows the next step. In this step, using an insulating adhesive, a pre-polishing substructure109is bonded to the first substructure110bonded to the jig112. The pre-polishing substructure109is bonded to the first substructure110with the first surface109aarranged to face the polished surface, i.e., the second surface110b, of the first substructure110. The pre-polishing substructure109bonded to the first substructure110will hereinafter be referred to as a second pre-polishing substructure109. The insulating layer113formed of the adhesive between the first substructure110and the second pre-polishing substructure109covers the plurality of electrodes of the second pre-polishing substructure109. The insulating layer113is to later become part of the insulating portion31.

FIG. 48shows a step that follows the step shown inFIG. 47. In this step, the second surface109bof the second pre-polishing substructure109is polished. The polishing is performed until the plurality of grooves104are exposed. The broken line inFIG. 47indicates the level of the second surface109bafter the polishing. By polishing the second surface109bof the second pre-polishing substructure109, the second pre-polishing substructure109is reduced in thickness, and a second substructure110bonded to the first substructure110is thereby formed.

FIG. 49shows a step that follows the step shown inFIG. 48. In this step, first, two stacks shown inFIG. 48, each including two substructures110, are prepared. The two stacks will be referred to as first and second stacks. Next, the first and second stacks are bonded to each other with a not-shown insulating adhesive, such that the surfaces of the stacks farther from the jigs112(the second surfaces110b) face each other. A third stack including four substructures110is thereby formed. The two jigs112are then released from the third stack.

Next, part of the insulating layer113of the uppermost substructure110in the third stack and part of the insulating layer113of the lowermost substructure110in the third stack are removed by, for example, etching, to expose the terminal component parts of the plurality of electrodes, and a plurality of conductor pads are then formed. Then, a plurality of conductor layers are formed on the plurality of conductor pads to thereby form the plurality of terminals4,5,6, and7. Consequently, a first layered substructure115including four stacked substructures110is formed as shown inFIG. 49. InFIG. 49, the semiconductor chips30of the layer portions10S1to10S4are designated by reference numerals301,302,303, and304, respectively. The subsequent steps are the same as those that follow the formation of the first layered substructure115of the first embodiment.

In the present embodiment, only either the plurality of first terminals4or the plurality of second terminals5may include the two or more first or second terminals that align in the first direction (the X direction) to form a third terminal row. In such a case also, it is possible to construct a composite layered chip package23by arranging a plurality of subpackages1S in the specific relative positional relationship with each other.

Fourth Embodiment

A fourth embodiment of the invention will now be described. First, reference is made toFIG. 50toFIG. 56to describe the configurations of a composite layered chip package and a stackable chip package according to the present embodiment.FIG. 50is a perspective view of the composite layered chip package according to the present embodiment.FIG. 51is a perspective view of a composite layered chip package that is formed by arranging two subpackages ofFIG. 50in a reference relative positional relationship with each other.FIG. 52is a perspective view of the stackable chip package according to the present embodiment.FIG. 53is a perspective view showing the stackable chip package ofFIG. 52as viewed from below.FIG. 54is a plan view showing a plurality of terminals of the stackable chip package shown inFIG. 52.FIG. 55is a plan view showing a layer portion included in the stackable chip package shown inFIG. 52.FIG. 56is a perspective view of the layer portion shown inFIG. 55.

The composite layered chip package24shown inFIG. 51is formed by arranging the two subpackages1L and1U in the reference relative positional relationship with each other. The composite layered chip package23according to the present embodiment shown inFIG. 50is formed by arranging the two subpackages1L and1U in a specific relative positional relationship, different from the reference relative positional relationship, with each other.

Now, the plurality of terminals4,5,6, and7of the present embodiment will be described in detail. As shown inFIG. 52andFIG. 53, each subpackage1S is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.FIG. 54shows the shape and arrangement of the plurality of terminals4,5,6, and7when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction).

As shown inFIG. 54, the plurality of first terminals4include two or more first terminals4that align in a first direction (the X direction) to form a first terminal row. The plurality of second terminals5include two or more second terminals5that align in the first direction (the X direction) to form a second terminal row. At least one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction (the X direction). Of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In the present embodiment, in particular, the first terminal row is formed by three or more first terminals that align in the first direction (the X direction), and the second terminal row is formed by three or more second terminals that align in the first direction (the X direction). Of the three or more first/second terminals, two that are located at opposite ends of the first/second terminal row are electrically connected to each other.

Specifically, the plurality of first terminals4include terminals4C1,4C2,4C01,4C3,4C4,4CO3,4R1,4R2,4R01,4R3,4R4,4R03,4R5,4R6,4R05,4R7,4R8, and4R07. Groups of three first terminals that align in the X direction, namely, (4C1,4C2,4C01), (4C3,4C4,4CO3), (4R1,4R2,4R01), (4R3,4R4,4R03), (4R5,4R6,4R05), and (4R7,4R8,4R07), form respective first terminal rows. In each of the terminal rows, two terminals located at opposite ends are electrically connected to each other.

The plurality of second terminals5include terminals5C1,5C2,5C01,5C3,5C4,5CO3,5R1,5R2,5R01,5R3,5R4,5R03,5R5,5R6,5R05,5R7,5R8, and5R07. Groups of three second terminals that align in the X direction, namely, (5C1,5C2,5C01), (5C3,5C4,5CO3), (5R1,5R2,5R01), (5R3,5R4,5R03), (5R5,5R6,5R05), and (5R7,5R8,5R07), form respective second terminal rows. In each of the terminal rows, two terminals located at opposite ends are electrically connected to each other.

In all the terminal rows, the three terminals making up each terminal row are at equal pitches. The amount of displacement of the second subpackage1U in the specific relative positional relationship with respect to the reference relative positional relationship is the same as the foregoing pitch. As shown inFIG. 54, two terminal rows adjacent in the X direction are offset from each other in the Y direction.

The plurality of third terminals6include four terminals6A1to6A4. The plurality of fourth terminals7include four terminals7A1to7A4. The shape and arrangement of the terminals6A1to6A4and7A1to7A4are the same as in the second embodiment.

In each subpackage1S, two terminals in each of the following pairs of terminals coincide with each other in position when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction): (4C1,5C1), (4C2,5C2), (4C01,5C01), (4C3,5C3), (4C4,5C4), (4CO3,5CO3), (4R1,5R1), (4R2,5R2), (4R01,5R01), (4R3,5R3), (4R4,5R4), (4R03,5R03), (4R5,5R5), (4R6,5R6), (4R05,5R05), (4R7,5R7), (4R8,5R8), (4R07,5R07), (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4).

Now, the plurality of wires W will be described in detail. The plurality of wires W include wires WC1to WC4, WR1to WR8, and WA1to WA4which are the same as those of the second embodiment, and further include wires WC01, WCO3, WR01, WR03, WR05, and WR07. The wires WC01, WCO3, WR01, WR03, WR05, and WRO7electrically connect two terminals in the respective pairs of terminals (4C01,5C01), (4CO3,5CO3), (4R01,5R01), (4R03,5R03), (4R05,5R05), and (4A07,5R07). Note that the wires WC01, WCO3, WR01, WR03, WR05, and WRO7may be omitted.

The plurality of electrodes32will now be described. In the present embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10S1, and the plurality of terminals5and7are formed by using the plurality of electrodes32of the layer portion10S4.

FIG. 55andFIG. 56illustrate the shape and arrangement of the plurality of electrodes32of the layer portions10S1and10S2. The shape and arrangement of the plurality of electrodes32of the layer portions10S3and10S4when viewed from the side of the first surface30aof each semiconductor chip30are a mirror image to those of the plurality of electrodes32shown inFIG. 55andFIG. 56.

The plurality of electrodes32include electrodes32C1to32C4,32C01,32CO3,32R1to32R8,32R01,32R03,32R05,32R07,32A1to32A4,32D1, and32D2. InFIG. 56, the reference symbols of the electrodes other than the electrodes32A1to32A4,32D1, and32D2are omitted.

The electrodes32C1to32C4,32C01,32CO3,32R1to32R8,32R01,32R03,32R05,32R07, and32A1to32A4of the layer portion10S1include terminal component parts that are used for forming the terminals4C1to4C4,4C01,4CO3,4R1to4R8,4R01,4R03,4R05,4R07, and6A1to6A4.

The electrodes32C1to32C4,32C01,32CO3,32R1to32R8,32R01,32R03,32R05,32R07, and32A1to32A4of the layer portion10S4include terminal component parts that are used for forming the terminals5C1to5C4,5C01,5CO3,5R1to5R8,5R01,5R03,5R05,5R07, and7A1to7A4.

The electrodes32C1to32C4,32C01,32CO3,32R1to32R8,32R01,32R03,32R05,32R07, and32A1to32A4have respective end faces located in the end face31cof the insulating portion31, and are electrically connected to the wires WC1to WC4, WC01, WCO3, WR1to WR8, WR01, WR03, WR05, WR07, and WA1to WA4via those end faces.

The electrode32D1has first and second branch portions. Each of the first and second branch portions has an end face located in the end face31cof the insulating portion31. The end face of the first branch portion is located near the end face of the electrode32C1. The end face of the second branch portion is located near the end face of the electrode32C3.

The electrode32D2has first to fourth branch portions. Each of the first to fourth branch portions has an end face located in the end face31cof the insulating portion31. The end face of the first branch portion is located near the end face of the electrode32R1. The end face of the second branch portion is located near the end face of the electrode32R3. The end face of the third branch portion is located near the end face of the electrode32R5. The end face of the fourth branch portion is located near the end face of the electrode32R7. The electrical connection relationships of the wires WC1, WC3, WR1, WR3, WR5, and WR7with the electrodes32D1and32D2are the same as in the third embodiment

Now, the reference relative positional relationship and the specific relative positional relationship in the present embodiment will be described in detail. The reference relative positional relationship will be described first, with reference toFIG. 51. The reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the second subpackage1U (the Z direction), the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position while the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position. When in the reference relative positional relationship, terminals4and6of the subpackage1L and terminals5and7of the subpackage1U that coincide with each other in position when viewed in the Z direction are in contact with each other and electrically connected to each other. In this way, there are formed a plurality of pairs of first and second terminals each of which is made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other.

The specific relative positional relationship shown inFIG. 50is such that the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U with respect to the reference relative positional relationship shown inFIG. 51. In the present embodiment, the specific relative positional relationship is particularly such that the second subpackage1U is displaced in the X direction (the first direction) with respect to the reference relative positional relationship.

Combinations of the first terminals4of the first subpackage1L and the second terminals5of the second subpackage1U making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship. In the example shown inFIG. 50, the second subpackage1U is displaced in the direction from the side surface2eof the main body2toward the side surface2fof the main body2, with respect to the reference relative positional relationship. It should be noted that the specific relative positional relationship may be such that the second subpackage1U is displaced in the direction from the side surface2ftoward the side surface2e, with respect to the reference relative positional relationship.

When in the specific relative positional relationship shown inFIG. 50, the plurality of pairs of first and second terminals, each of which is made up of one of the first terminals4of the first subpackage1L and one of the second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other, are as follows: (4C2,5C1), (4C01,5C2), (4C4,5C3), (4CO3,5C4), (4R2,5R1), (4R01,5R2), (4R4,5R3), (4R03,5R4), (4R6,5R5), (4R05,5R6), (4R8,5R7), and (4R07,5R8).

When in a not-shown specific relative positional relationship where the second subpackage1U is displaced in the direction from the side surface2ftoward the side surface2ewith respect to the reference relative positional relationship, the terminals5C2,5C01,5C4,5CO3,5R2,5R01,5R4,5R03,5R6,5R05,5R8,5R07, and7A1to7A4of the second subpackage1U are in contact with and electrically connected to the terminals4C1to4C4,4R1to4R8, and6A1to6A4of the first subpackage1L.

As in the second embodiment, a plurality of pairs of terminals (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4) in each of which the two terminals are in contact with and electrically connected to each other are formed across the terminals6A1to6A4of the first subpackage1L and the terminals7A1to7A4of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

Next, the flow of a plurality of signals in the composite layered chip package23shown inFIG. 50and the composite layered chip package24shown inFIG. 51will be described.FIG. 57is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package23shown inFIG. 50.FIG. 58is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package24shown inFIG. 51.

In each subpackage1S, the same signal appears on a plurality of terminals that are electrically connected to each other. More specifically, the signal to appear on the terminal4C01is the same as that on the terminal4C1. The signal to appear on the terminal5C01is the same as that on the terminal5C1. The signals to appear on the terminals5C1,5C2, and5C01are the same as those on the terminals4C1,4C2, and4C01, respectively.

FIG. 57shows an example where the signals S2and S1are supplied to the terminals5C1and5C2of the subpackage1L as shown in portion (b) ofFIG. 57. In this case, in the subpackage1L, the signals S2, S1, and S2appear on the terminals4C1,4C2, and4C01, respectively.

When in the specific relative positional relationship shown inFIG. 50, the terminals5C1and5C2of the subpackage1U are in contact with the terminals4C2and4C01of the subpackage1L. Consequently, in the subpackage1U, as shown in portion (a) ofFIG. 57, the signals S1and S2are transmitted to the terminals5C1and5C2. As a result, the signals S1, S2, and51appear on the terminals4C1,4C2, and4C01, respectively.

In each of the layer portions10S1and10S2, the terminals4C1and5C1are electrically connected to the semiconductor chip30through the wire WC1and the electrode32D1. As described above, when in the specific relative positional relationship shown inFIG. 50, the signal to appear on the terminals4C1and5C1varies between the subpackages1S (1L and1U). Consequently, in the composite layered chip package23shown inFIG. 50, the signals associated with the semiconductor chips30of the respective corresponding layers of different subpackages1S through the wire WC1and the electrodes32D1can be varied between the subpackages1S. In the example shown inFIG. 57, the signal associated with the semiconductor chips30of the layer portions10S1and10S2through the wire WC1and the electrodes32D1in the subpackage1U is the signal S1, whereas the signal S2is associated in the subpackage1L.

On the other hand, when in the reference relative positional relationship shown inFIG. 51, the signals to appear on the terminals4C1,4C2,4C01,5C1,5C2, and5C01do not vary between the subpackages1S as shown inFIG. 58.FIG. 58shows an example where the signals S1and S2are supplied to the terminals5C1and5C2of the subpackage1L. In the composite layered chip package24shown inFIG. 51, the signal associated with the semiconductor chips30of the layer portions10S1and10S2through the wire WC1and the electrodes32D1is the same between the subpackages1U and1L.

The mode of signal flow described with reference toFIG. 57andFIG. 58also applies to groups of terminals similar to the group of terminals4C1,4C2,4C01,5C1,5C2, and5C01, such as a group of terminals4C3,4C4,4CO3,5C3,5C4, and5CO3.

The present embodiment may be configured so that only one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction (the X direction) and, of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In such a case also, it is possible to construct a composite layered chip package23by arranging a plurality of subpackages1S in the specific relative positional relationship with each other.

Fifth Embodiment

A fifth embodiment of the invention will now be described. First, reference is made toFIG. 59toFIG. 65to describe the configurations of a composite layered chip package and a stackable chip package according to the present embodiment.FIG. 59is a perspective view of the composite layered chip package according to the present embodiment.FIG. 60is a perspective view of a composite layered chip package that is formed by arranging eight subpackages ofFIG. 59in a reference relative positional relationship with each other.FIG. 61is a perspective view of the stackable chip package according to the present embodiment.FIG. 62is a perspective view showing the stackable chip package ofFIG. 61as viewed from below.FIG. 63is a plan view showing a plurality of terminals of the stackable chip package shown inFIG. 61.FIG. 64is a plan view showing a layer portion included in the stackable chip package shown inFIG. 61.FIG. 65is a perspective view of the layer portion shown inFIG. 64.

The composite layered chip package25according to the present embodiment shown inFIG. 59includes eight subpackages stacked on each other. Hereinafter, the eight subpackages will be designated by reference symbols1A to1H in order from the top as shown inFIG. 59. In the composite layered chip package25, any two vertically adjacent subpackages are electrically connected to each other. Of any two vertically adjacent subpackages, the lower subpackage is a first subpackage1L and the upper subpackage is a second subpackage1U. Any subpackage will be designated by reference symbol1S. Each subpackage1S is the stackable chip package according to the present embodiment.

The composite layered chip package26shown inFIG. 60is formed by arranging the eight subpackages1A to1H in the reference relative positional relationship with each other. The composite layered chip package25according to the present embodiment shown inFIG. 59is formed by arranging the eight subpackages1A to1H in a specific relative positional relationship, different from the reference relative positional relationship, with each other.

As shown inFIG. 61andFIG. 62, the subpackage1S or the stackable chip package according to the present embodiment includes a main body2and wiring3. The main body2has a main part2M. The wiring3includes a plurality of wires W. The main part2M of the present embodiment includes only a single layer portion10. The layer portion10is arranged with the first surface30aof the semiconductor chip30upward. The main part2M further includes an insulating layer11. The insulating layer11has a top surface bonded to the second surface30bof the semiconductor chip30, and a bottom surface opposite to the top surface. In the present embodiment, the plurality of terminals5and7and the bottom wiring9are formed on the bottom surface of the insulating layer11. The bottom wiring9is covered with an insulating portion12. InFIG. 61andFIG. 62, the insulating portion12is shown by broken lines.

Now, the plurality of terminals4,5,6, and7of the present embodiment will be described in detail. As shown inFIG. 61andFIG. 62, each subpackage1S is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.FIG. 63shows the shape and arrangement of the plurality of terminals4,5,6, and7when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction).

As shown inFIG. 63, the plurality of first terminals4include two or more first terminals4that align in a first direction (the X direction) to form a first terminal row. Specifically, the plurality of first terminals4include eight first terminals4C11to4C18that align in the X direction to form a terminal row43C (seeFIG. 61), and eight first terminals4R11to4R18that align in the X direction to form a terminal row43R (seeFIG. 61). Each of the terminal rows43C and43R corresponds to the first terminal row.

The plurality of second terminals5include two or more second terminals5that align in the first direction to form a second terminal row. Specifically, the plurality of second terminals5include eight second terminals5C11to5C18that align in the X direction to form a terminal row53C (seeFIG. 62), and eight second terminals5R11to5R18that align in the X direction to form a terminal row53R (seeFIG. 62). Each of the terminal rows53C and53R corresponds to the second terminal row.

At least either the plurality of first terminals4or the plurality of second terminals5further include other two or more first or second terminals that align in the first direction (the X direction) to form a third terminal row. The third terminal row is adjacent to the first or second terminal row in a second direction (the Y direction) orthogonal to the first direction (the X direction). In the present embodiment, in particular, the plurality of first terminals4include other two or more first terminals that align in the first direction (the X direction) to form a third terminal row, and the plurality of second terminals5include other two or more second terminals that align in the first direction (the X direction) to form a third terminal row.

Specifically, the plurality of first terminals4include eight first terminals4C21to4C28that align in the X direction to form a terminal row44C (seeFIG. 61), and eight first terminals4R21to42R28that align in the X direction to form a terminal row44R (seeFIG. 61). The terminal row44C is adjacent to the terminal row43C in the Y direction. The terminal row44R is adjacent to the terminal row43R in the Y direction. Each of the terminal rows44C and44R corresponds to the third terminal row.

A plurality of pairs of terminals are formed across a first terminal row and an adjacent third terminal row, each of the plurality of pairs of terminals being made up of two terminals that are electrically connected to each other. The two terminals are one of the two or more first terminals that form the first terminal row and one of the other two or more first terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). Specifically, across the first terminal row and the third terminal row, there are formed the following pairs of two electrically-connected terminals: (4C11,4C22), (4C12,4C23), (4C13,4C24), (4C14,4C25), (4C15,4C26), (4C16,4C27), (4C17,4C28), (4C18,4C21), (4R11,4R22), (4R12,4R23), (4R13,4R24), (4R14,4R25), (4R15,4R26), (4R16,4R27), (4R17,4R28), and (4R18,4R21).

The plurality of second terminals5include eight second terminals5C21to5C28that align in the X direction to form a terminal row54C (seeFIG. 62), and eight second terminals5R21to5R28that align in the X direction to form a terminal row54R (seeFIG. 62). The terminal row54C is adjacent to the terminal row53C in the Y direction. The terminal row54R is adjacent to the terminal row53R in the Y direction. Each of the terminal rows54C and54R corresponds to the third terminal row.

A plurality of pairs of terminals are formed across a second terminal row and an adjacent third terminal row, each of the plurality of pairs of terminals being made up of two terminals that are electrically connected to each other. The two terminals are one of the two or more second terminals that form the second terminal row and one of the other two or more second terminals that form the third terminal row, the ones being non-adjacent to each other in the second direction (the Y direction). Specifically, across the second terminal row and the third terminal row, there are formed the following pairs of two electrically-connected terminals: (sell,5C22), (5C12,5C23), (5C13,5C24), (5C14,5C25), (5C15,5C26), (5C16,5C27), (5C17,5C28), (5C18,5C21), (5R11,5R22), (5R12,5R23), (5R13,5R24), (5R14,5R25), (5R15,5R26), (5R16,5R27), (5R17,5R28), and (5R18,5R21).

The plurality of third terminals6include four terminals6A1to6A4. The plurality of fourth terminals7include four terminals7A1to7A4. The shape and arrangement of the terminals6A1to6A4and7A1to7A4are the same as in the first embodiment.

The plurality of electrodes32will now be described. In the present embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10.FIG. 64andFIG. 65show the shape and arrangement of the plurality of electrodes32. The plurality of electrodes32include electrodes32C11to32C18,32C21to32028,32R11to32R18,32R21to32R28,32A1to32A4,32D1, and32D2. InFIG. 65, the reference symbols of the electrodes other than the electrodes32A1to32A4,32D1, and32D2are omitted. The electrodes32C11to32C18,32R11to32R18,32C21to32C28,32R21to32R28, and32A1to32A4include terminal component parts that are used for forming the terminals4C11to4C18,4R11to4R18,4C21to4C28,4R21to4R28, and6A1to6A4.

The electrodes32C11to32C18,32R11to32R18, and32A1to32A4have respective end faces located in the end face31cof the insulating portion31, and are electrically connected to the wires WC1to WC8, WR1to WR8, and WA1to WA4via those end faces. In the present embodiment, the electrode32D1is electrically connected to the electrode32C11, while the electrode32D2is electrically connected to the electrode32R11.

Now, the reference relative positional relationship and the specific relative positional relationship in the present embodiment will be described in detail. The reference relative positional relationship will be described first, with reference toFIG. 60. The reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the second subpackage1U (the Z direction), the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position while the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position. When in the reference relative positional relationship, terminals4and6of the subpackage1L and terminals5and7of the subpackage1U that coincide with each other in position when viewed in the Z direction are in contact with each other and electrically connected to each other. In this way, there are formed a plurality of pairs of first and second terminals each of which is made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other.

The specific relative positional relationship shown inFIG. 59is such that the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U with respect to the reference relative positional relationship shown inFIG. 60. In the present embodiment, the specific relative positional relationship is particularly such that the second subpackage1U is displaced in the Y direction (the second direction) with respect to the reference relative positional relationship.

Combinations of the first terminals4of the first subpackage1L and the second terminals5of the second subpackage1U making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship. In the example shown inFIG. 59, the second subpackage1U is displaced in the direction from the side surface2cof the main body2toward the side surface2dof the main body2, with respect to the reference relative positional relationship. It should be noted that the specific relative positional relationship may be such that the second subpackage1U is displaced in the direction from the side surface2dtoward the side surface2c, with respect to the reference relative positional relationship.

When in the specific relative positional relationship shown inFIG. 59, the plurality of pairs of first and second terminals, each of which is made up of one of the first terminals4of the first subpackage1L and one of the second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other, are as follows: (4C21,5C11), (4C22,5C12), (4C23,5C13), (4C24,5C14), (4C25,5C15), (4C26,5C16), (4C27,5C17), (4C28,5C18), (4R21,5R11), (4R22,5R12), (4R23,5R13), (4R24,5R14), (4R25,5R15), (4R26,5R16), (4R27,5R17), and (4R28,5R18).

When in a not-shown specific relative positional relationship where the second subpackage1U is displaced in the direction from the side surface2dtoward the side surface2cwith respect to the reference relative positional relationship, the terminals5C21to5C28,5R21to5R28, and7A1to7A4of the second subpackage1U are in contact with and electrically connected to the terminals4C11to4C18,4R11to4R18, and6A1to6A4of the first subpackage1L.

As in the first embodiment, there are formed a plurality of pairs of terminals (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4) in each of which the two terminals are in contact with and electrically connected to each other, across the terminals6A1to6A4of the first subpackage1L and the terminals7A1to7A4of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

Next, the flow of a plurality of signals in the composite layered chip package25shown inFIG. 59and the composite layered chip package26shown inFIG. 60will be described.FIG. 66is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package25shown inFIG. 59.FIG. 67is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package26shown inFIG. 60.

Portions (a) to (h) ofFIG. 66show the terminals4C11to4C18,4C21to4C28,5C11to5C18, and5C21to5C28in the subpackages1A to1H of the composite layered chip package25shown inFIG. 59and signals to appear thereon. Portions (a) to (h) ofFIG. 67show the terminals4C11to4C18,4C21to4C28,5C11to5C18, and5C21to5C28in the subpackages1A to1H of the composite layered chip package26shown inFIG. 60and signals to appear thereon. Symbols S1to S8inFIG. 66andFIG. 67represent respective signals. In each subpackage1S, the same signal appears on a plurality of terminals that are electrically connected to each other.

FIG. 66shows an example where the signals S8, S1, S2, S3, S4, S5, S6, and S7are supplied to the terminals5C11,5C12,5C13,5C14,5C15,5C16,5C17, and5C18of the subpackage1H as shown in portion (h) ofFIG. 66. In this case, the signals S1, S2, S3, S4, S5, S6, S7, and S8appear on the terminals4C11of the subpackages1A to1H. The electrodes32D1are electrically connected to the terminals4C11. Consequently, in the composite layered chip package25shown inFIG. 59, the signals associated with the semiconductor chips30in the subpackages1A to1H through the electrodes32D1are the signals S1, S2, S3, S4, S5, S6, S7, and S8, respectively.

On the other hand, when in the reference relative positional relationship shown inFIG. 60, the signals to appear on the terminals4C11to4C18,4C21to4C28,5C11to5C18, and5C21to5C28do not vary from one subpackage1S to another as shown inFIG. 67.FIG. 67shows an example where the signals S1to S8are supplied to the terminals5C11to5C18of the subpackage1H. In the composite layered chip package26shown inFIG. 60, the same signals are associated with the semiconductor chips30of all the subpackages1A to1H through the electrodes32D1.

The mode of signal flow described with reference toFIG. 66andFIG. 67also applies to the group of terminals4R11to4R18,4R21to4R28,5R11to5R18, and5R21to5R28.

Now, a description will be made as to the flow of a plurality of signals for the case where the composite layered chip package25shown inFIG. 59is used to construct the memory device shown inFIG. 10. In the subpackages1A to1H of the composite layered chip package25shown inFIG. 59, the terminals6A1and7A1are electrically connected to the wire WA1, the terminals6A2and7A2are electrically connected to the wire WA2, the terminals6A3and7A3are electrically connected to the wire WA3, and the terminals6A4and7A4are electrically connected to the wire WA4. As a result, there are formed a plurality of electrical paths that lead from the terminals6A1-6A4of the subpackage1A to the terminals7A1-7A4of the subpackage1H. The plurality of electrical paths constitute parts of the data bus91and the one or more common lines92.

As shown inFIG. 66, assume that each of the signals S1and S2is the chip enable signal CE1, each of the signals S3and S4is the chip enable signal CE2, each of the signals S5and S6is the chip enable signal CE3, and each of the signals S7and S8is the chip enable signal CE4. In this case, in the composite layered chip package25, the chip enable signal CE1is supplied only to the semiconductor chips30of the subpackages1A and1B, i.e., the memory chips MC1and MC2. Likewise, the chip enable signal CE2is supplied only to the semiconductor chips30of the subpackages1C and1D, i.e., the memory chips MC3and MC4. The chip enable signal CE3is supplied only to the semiconductor chips30of the subpackages1E and1F, i.e., the memory chips MC5and MC6. The chip enable signal CE4is supplied only to the semiconductor chips30of the subpackages1G and1H, i.e., the memory chips MC7and MC8.

The semiconductor chips30of the subpackages1A to1H output the ready/busy signals R/B1to R/B8, respectively, from the electrodes32D2. The signals R/B1to R/B8correspond to the signals S1to S8inFIG. 66, respectively. As can be seen fromFIG. 66, the signal R/B1is output from the terminal4R11of the subpackage1A or the terminal5R12of the subpackage1H. The signal R/B2is output from the terminal4R12of the subpackage1A or the terminal5R13of the subpackage1H. The signal R/B3is output from the terminal4R13of the subpackage1A or the terminal5R14of the subpackage1H. The signal R/B4is output from the terminal4R14of the subpackage1A or the terminal5R15of the subpackage1H. The signal R/B5is output from the terminal4R15of the subpackage1A or the terminal5R16of the subpackage1H. The signal R/B6is output from the terminal4R16of the subpackage1A or the terminal5R17of the subpackage1H. The signal R/B7is output from the terminal4R17of the subpackage1A or the terminal5R18of the subpackage1H. The signal R/B8is output from the terminal4R18of the subpackage1A or the terminal5R11of the subpackage1H.

In the present embodiment, only either the plurality of first terminals4or the plurality of second terminals5may include the two or more first or second terminals that align in the first direction (the X direction) to form a third terminal row. In such a case also, it is possible to construct a composite layered chip package25by arranging a plurality of subpackages1S in the specific relative positional relationship with each other.

Sixth Embodiment

A sixth embodiment of the invention will now be described. First, reference is made toFIG. 68toFIG. 74to describe the configurations of a composite layered chip package and a stackable chip package according to the present embodiment.FIG. 68is a perspective view of the composite layered chip package according to the present embodiment.FIG. 69is a perspective view of a composite layered chip package that is formed by arranging eight subpackages ofFIG. 68in a reference relative positional relationship with each other.FIG. 70is a perspective view of the stackable chip package according to the present embodiment.FIG. 71is a perspective view showing the stackable chip package ofFIG. 70as viewed from below.FIG. 72is a plan view showing a plurality of terminals of the stackable chip package shown inFIG. 70.FIG. 73is a plan view showing a layer portion included in the stackable chip package shown inFIG. 70.FIG. 74is a perspective view of the layer portion shown inFIG. 73.

The composite layered chip package26shown inFIG. 69is formed by arranging the eight subpackages1A to1H in the reference relative positional relationship with each other. The composite layered chip package25according to the present embodiment shown inFIG. 68is formed by arranging the eight subpackages1A to1H in a specific relative positional relationship, different from the reference relative positional relationship, with each other.

Now, the plurality of terminals4,5,6, and7of the present embodiment will be described in detail. As shown inFIG. 70andFIG. 71, each subpackage1S is configured so that the plurality of first terminals4and the plurality of second terminals5are in the same layout when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction), and that the plurality of third terminals6and the plurality of fourth terminals7are in the same layout when viewed in the Z direction.FIG. 72shows the shape and arrangement of the plurality of terminals4,5,6, and7when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction).

As shown inFIG. 72, the plurality of first terminals4include two or more first terminals4that align in a first direction (the X direction) to form a first terminal row. The plurality of second terminals5include two or more second terminals5that align in the first direction (the X direction) to form a second terminal row. At least one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction (the X direction). Of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In the present embodiment, in particular, the first terminal row is formed by three or more first terminals that align in the first direction (the X direction), and the second terminal row is formed by three or more second terminals that align in the first direction (the X direction). Of the three or more first/second terminals, two that are located at opposite ends of the first/second terminal row are electrically connected to each other.

Specifically, the plurality of first terminals4include nine first terminals4C1,4C2,4C3,4C4,4C5,4C6,4C7,4C8, and4C01that align in the X direction to form a terminal row45C (seeFIG. 70), and nine first terminals4R1,4R2,4R3,4R4,4R5,4R6,4R7,4R8, and4R01that align in the X direction to form a terminal row45R (seeFIG. 70). In each of the terminal rows, two terminals located at opposite ends are electrically connected to each other. The X direction corresponds to the first direction. Each of the terminal rows45C and45R corresponds to the first terminal row.

The plurality of second terminals5include nine second terminals5C1,5C2,5C3,5C4,5C5,5C6,5C7,5C8, and5C01that align in the X direction to form a terminal row55C (seeFIG. 71), and nine second terminals5R1,5R2,5R3,5R4,5R5,5R6,5R7,5R8, and5R01that align in the X direction to form a terminal row55R (seeFIG. 71). In each of the terminal rows, two terminals located at opposite ends are electrically connected to each other. Each of the terminal rows55C and55R corresponds to the second terminal row.

In all the terminal rows, the nine terminals making up each terminal row are at equal pitches. The amount of displacement of the second subpackage1U in the specific relative positional relationship with respect to the reference relative positional relationship is the same as the foregoing pitch.

The plurality of third terminals6include four terminals6A1to6A4. The plurality of fourth terminals7include four terminals7A1to7A4. The shape and arrangement of the terminals6A1to6A4and7A1to7A4are the same as in the second embodiment.

In each subpackage is, two terminals in each of the following pairs of terminals coincide with each other in position when viewed in the direction perpendicular to the top surface2Ma of the main part2M (the Z direction): (4C1,5C1), (4C2,5C2), (4C3,5C3), (4C4,5C4), (4C5,5C5), (4C6,5C6), (4C7,5C7), (4C8,5C8), (4C01,5C01), (4R1,5R1), (4R2,5R2), (4R3,5R3), (4R4,5R4), (4R5,5R5), (4R6,5R6), (4R7,5R7), (4R8,5R8), (4R01,5R01), (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4).

The plurality of electrodes32will now be described. In the present embodiment, the plurality of terminals4and6are formed by using the plurality of electrodes32of the layer portion10.FIG. 73andFIG. 74show the shape and arrangement of the plurality of electrodes32. The plurality of electrodes32include electrodes32C1to32C8,32C01,32R1to32R8,32R01,32A1to32A4,32D1, and32D2. InFIG. 74, the reference symbols of the electrodes other than the electrodes32A1to32A4,32D1, and32D2are omitted. The electrodes32C1to32C8,32C01,32R1to32R8,32R01, and32A1to32A4include terminal component parts that are used for forming the terminals4C1to4C8,4C01,4R1to4R8,4R01, and6A1to6A4.

The electrodes32C1to32C8,32C01,32R1to32R8,32R01, and32A1to32A4have respective end faces located in the end face31cof the insulating portion31, and are electrically connected to the wires WC1to WC8, WC01, WR1to WR8, WR01, and WA1to WA4via those end faces. In the present embodiment, the electrode32D1is electrically connected to the electrode32C1, while the electrode32D2is electrically connected to the electrode32R1.

Now, the reference relative positional relationship and the specific relative positional relationship in the present embodiment will be described in detail. The reference relative positional relationship will be described first, with reference toFIG. 69. The reference relative positional relationship is such that, when viewed in the direction perpendicular to the top surface2Ma of the main part2M of the second subpackage1U (the Z direction), the plurality of first terminals4of the first subpackage1L and the plurality of first terminals4of the second subpackage1U coincide with each other in position while the plurality of second terminals5of the first subpackage1L and the plurality of second terminals5of the second subpackage1U coincide with each other in position. When in the reference relative positional relationship, terminals4and6of the subpackage1L and terminals5and7of the subpackage1U that coincide with each other in position when viewed in the Z direction are in contact with each other and electrically connected to each other. In this way, there are formed a plurality of pairs of first and second terminals each of which is made up of one of the plurality of first terminals4of the first subpackage1L and one of the plurality of second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other.

The specific relative positional relationship shown inFIG. 68is such that the second subpackage1U is displaced in the direction parallel to the top surface2Ma of the main part2M of the second subpackage1U with respect to the reference relative positional relationship shown inFIG. 69. In the present embodiment, the specific relative positional relationship is particularly such that the second subpackage1U is displaced in the X direction (the first direction) with respect to the reference relative positional relationship.

Combinations of the first terminals4of the first subpackage1L and the second terminals5of the second subpackage1U making up the plurality of pairs of first and second terminals in the specific relative positional relationship are different from those in the reference relative positional relationship. In the example shown inFIG. 68, the second subpackage1U is displaced in the direction from the side surface2eof the main body2toward the side surface2fof the main body2, with respect to the reference relative positional relationship. It should be noted that the specific relative positional relationship may be such that the second subpackage1U is displaced in the direction from the side surface2ftoward the side surface2e, with respect to the reference relative positional relationship.

When in the specific relative positional relationship shown inFIG. 68, the plurality of pairs of first and second terminals, each of which is made up of one of the first terminals4of the first subpackage1L and one of the second terminals5of the second subpackage1U that are in contact with each other and electrically connected to each other, are as follows: (4C2,5C1), (4C3,5C2), (4C4,5C3), (4C5,5C4), (4C6,5C5), (4C7,5C6), (4C8,5C7), (4C01,5C8), (4R2,5R1), (4R3,5R2), (4R4,5R3), (4R5,5R4), (4R6,5R5), (4R7,5R6), (4R8,5R7), and (4R01,5R8).

When in a not-shown specific relative positional relationship where the second subpackage1U is displaced in the direction from the side surface2ftoward the side surface2ewith respect to the reference relative positional relationship, the terminals5C2,5C3,5C4,5C5,5C6,5C7,5C8,5C01,5R2,5R3,5R4,5R5,5R6,5R7,5R8,5R01and7A1to7A4of the second subpackage1U are in contact with and electrically connected to the terminals4C1to4C8,4R1to4R8, and6A1to6A4of the first subpackage1L.

As in the second embodiment, a plurality of pairs of terminals (6A1,7A1), (6A2,7A2), (6A3,7A3), and (6A4,7A4) in each of which the two terminals are in contact with and electrically connected to each other are formed across the terminals6A1to6A4of the first subpackage1L and the terminals7A1to7A4of the second subpackage1U regardless of whether in the reference relative positional relationship or the specific relative positional relationship.

Next, the flow of a plurality of signals in the composite layered chip package25shown inFIG. 68and the composite layered chip package26shown inFIG. 69will be described.FIG. 75is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package25shown inFIG. 68.FIG. 76is an explanatory diagram showing the flow of a plurality of signals in the composite layered chip package26shown inFIG. 69.

In each subpackage1S, the signal to appear on the terminal4C01is the same as that on the terminal4C1, and the signal to appear on the terminal5C01is the same as that on the terminal5C1. The signals to appear on the terminals5C1to5C8, and5C01are the same as those on the terminals4C1to4C8, and4C01, respectively.

FIG. 75shows an example where the signals S8, S7, S6, S5, S4, S3, S2, and S1are supplied to the terminals5C1,5C2,5C3,5C4,5C5,5C6,5C7, and5C8of the subpackage1H as shown in portion (h) ofFIG. 75. In this case, the signals S1, S2, S3, S4, S5, S6, S7, and S8appear on the terminals4C1of the subpackages1A to1H. The electrodes32D1are electrically connected to the terminals4C1. Consequently, in the composite layered chip package25shown inFIG. 68, the signals associated with the semiconductor chips30in the subpackages1A to1H through the electrodes32D1are the signals S1, S2, S3, S4, S5, S6, S7, and S8, respectively.

On the other hand, when in the reference relative positional relationship shown inFIG. 69, the signals to appear on the terminals4C1to4C8, and4C01do not vary from one subpackage1S to another as shown inFIG. 76.FIG. 76shows an example where the signals S1to S8are supplied to the terminals5C1to5C8of the subpackage1H. In the composite layered chip package26shown inFIG. 69, the same signals are associated with the semiconductor chips30of all the subpackages1A to1H through the electrodes32D1.

The mode of signal flow described with reference toFIG. 75andFIG. 76also applies to the group of terminals4R1to4R8, and4R01.

The present embodiment may be configured so that only one of the first and second terminal rows is formed by three or more first or second terminals that align in the first direction (the X direction) and, of the three or more first or second terminals, two that are located at opposite ends of the first or second terminal row are electrically connected to each other. In such a case also, it is possible to construct a composite layered chip package25by arranging a plurality of subpackages1S in the specific relative positional relationship with each other.

The present invention is not limited to the foregoing embodiments, and various modifications may be made thereto. For example, the number of the layer portion(s)10to be included in the main part2M may be other than the numbers shown in the foregoing embodiments.

It is apparent that the present invention can be carried out in various forms and modifications in the light of the foregoing descriptions. Accordingly, within the scope of the following claims and equivalents thereof, the present invention can be carried out in forms other than the foregoing most preferred embodiments.