Laminated chips package, semiconductor substrate and method of manufacturing the laminated chips package

In a laminated chip package, a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device are laminated. On a side surface for wiring of the laminated chip package, an end face of an inner electrode for examination formed inside the side surface for wiring in the semiconductor plate is formed. The laminated chip package further has an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates.

BACKGROUND

1. Field of the Invention

The present invention relates to a laminated chip package including a plurality of laminated chips, a semiconductor substrate for manufacturing the laminated chip package and a method of manufacturing the laminated chip package.

2. Related Background Art

In recent years, electronic devices such as cellular phones and notebook personal computers need to be reduced in weight and improved in performance. With such needs, higher integration of electronic components used for the electronic devices has been required. Further, the higher integration of electronic components has been required also for increase in capacity of a semiconductor memory device.

Recently, System in Package (hereinafter referred to as a “SIP”) has attracted attention as a highly integrated electronic component. The SIP is a device created by stacking a plurality of LSIs and mounting them in one package, and a SIP using the three-dimensional mounting technique of laminating a plurality of chips has received attention recently. Known as such a SIP is a package having a plurality of laminated chips, that is, a laminated chip package. The laminated chip package has an advantage that speed up of operation of circuits and reduction in stray capacitance of wiring become possible because the length of the wiring can be reduced as well as an advantage of capability of high integration.

Known as the three-dimensional mounting techniques for manufacturing the laminated chip package include a wire bonding system and a through electrode system. The wire bonding system is a system of laminating a plurality of chips on a substrate and connecting a plurality of electrodes formed on each of the chips and external connecting terminals formed on the substrate by wire bonding. The through electrode system is a system of forming a plurality of through electrodes in each of the laminated chips and realizing wiring between the chips by the through electrodes.

The wire bonding system has a problem of a difficulty in reducing the spaces between the electrodes in a manner that the wires are not in contact with each other, a problem of a difficulty in speeding up the operation of circuits because of a high resistance value of wires, and a problem of a difficulty in reducing the thickness.

Though the above-described problems in the wire bonding system are solved in the through electrode system, the through electrode system has a problem of increased cost of the laminated chip package because many processes are required for forming the through electrodes in each of the chips.

Conventionally known methods of manufacturing the laminated chip package are those disclosed, for example, in U.S. Pat. Nos. 5,953,588 and 7,127,807 B2, for example. In U.S. Pat. No. 5,953,588, the following manufacturing method is described. In this manufacturing method, first, a plurality of chips cut out of a wafer are embedded in an embedding resin. Then, a plurality of leads to be connected to the chips are formed to create a structure called Neo-Wafer. Subsequently, the Neo-Wafer is cut to create a plurality of structures called Neo-chips each including the chip, the resin surrounding the chip, and the plurality of leads. In this event, end faces of the plurality of leads connected to the chips are exposed on side surfaces of the Neo-chips. Then, a plurality of kinds of Neo-chips are laminated to create a laminated body. In this laminated body, the end faces of the plurality of leads connected to the chips at the respective layers are exposed on the same side surface of the laminated body.

Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December, 1999 describes that a laminated body is formed by the same method as the manufacturing method described in U.S. Pat. No. 5,953,588 and wiring is formed on two side surfaces of the laminated body.

On the other hand, U.S. Pat. No. 7,127,807 B2 discloses a multilayer module which is configured by laminating a plurality of active layers made by forming one or more electronic elements and a plurality of conductive traces on a flexible polymer substrate.

SUMMARY OF THE INVENTION

Incidentally, the laminated chip package is manufactured by the following procedure. First, a wafer (a device wafer) having a plurality of devices formed therein is created by performing wafer process. Then, a plurality of groove portions along scribe lines are formed in the device wafer. Further, a resin such as an epoxy resin, a polyimide resin or the like is embedded in the groove portions to form insulating layers to thereby create a grooved device wafer. Such grooved device wafers are bonded together with an insulating adhesive to create a laminated device wafer. The laminated device wafer is cut along the groove portions to manufacture laminated chip packages.

Meanwhile, in the laminated chip package, a plurality of device plates are stacked one on the other. When the laminated device wafer is cut along the groove portions, the grooved device wafers are also cut along the groove portions. Members in a plate shape formed by cutting the grooved device wafer along the groove portions are the device plates.

In order to manufacture the laminated chip package, the device plates need to be electrically connected with each other. Each of the device plates has a plurality of devices formed therein and side surfaces covered by an insulating layer. Therefore, the following 1) and 2) processes have been conventionally required for the manufacturing process of the laminated chip package. Specifically, 1) assuming that a structure in which device plates are stacked in the vertical direction is a device block, end faces of wirings formed in the device plates are made to appear at one side surface of the device block. 2) Then, secondary wirings (also referred to as connection electrodes) connecting the end faces of the wirings across each of the device plates are formed on the side surface of the device block.

On the other hand, the wiring formed in each device plate is formed to come into contact with not only the secondary wiring but also a connection pad connected to the device. Therefore, in the laminated chip package, a contact resistance may be generated at a portion where the wiring contacts with the secondary wiring and a portion where the wiring contacts with the connection pad.

However, since the secondary wiring connects all of the end faces of the wirings of the device plates in the vertical direction, the laminated chip package has a structure in which a test to confirm the contact resistance between the device plates is difficult to be conducted. As a result, the conventional laminated chip package requires much time for the test to confirm the contact resistance and thus has a problem of it being difficulty to simplify such a test.

The present invention is made to solve the above problem, and it is an object to provide a laminated chip package having a structure in which the process of examining the contact resistance is simplified and efficiently performed, a semiconductor substrate for manufacturing the laminated chip package, and a method of manufacturing the laminated chip package.

To solve the above problem, the present invention is a laminated chip package in which a plurality of semiconductor plates are laminated, each of the semiconductor plates having a semiconductor device and a wiring electrode connected to the semiconductor device, wherein on at least one side surface for wiring of a plurality of side surfaces, an end face of an inner electrode for examination formed inside of the side surface for wiring in the semiconductor plate is formed, and wherein an outer electrode for examination is provided, which connects the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates.

In the laminated chip package, since the outer electrode for examination only for two adjacent semiconductor plates is formed, an examination only for the two semiconductor plates can be conducted.

In the laminated chip package, it is preferable that a surface layer plate in which a wiring electrode for examination in common with the wiring electrode is formed in place of the inner electrode for examination is laminated at an uppermost position as one of the semiconductor plates, an end face of the wiring electrode for examination is formed on the side surface for wiring, and a plurality of the outer electrodes for examination are provided, and at least one of the outer electrodes for examination connects the end face of the wiring electrode for examination and the end face of the inner electrode for examination along the lamination direction.

Further, in the laminated chip package, it is preferable that two wiring electrodes for examination are provided, and a serial line for examination is formed to be continuous from one of the wiring electrodes for examination to another of the wiring electrodes for examination together with all of the outer electrodes for examination and the inner electrodes for examination.

Furthermore, in the laminated chip package, a plurality of the outer electrodes for examination are provided, and the outer electrodes for examination are intermittently arranged along the lamination direction.

Further, in the laminated chip package, a plurality of the outer electrodes for examination may be provided, and a plurality of outer electrode columns may be provided in each of which the outer electrodes for examination are intermittently arranged along the lamination direction.

The inner electrode for examination may be formed in a shape having end faces connected to the outer electrode for examination at both ends thereof.

Further, the outer electrode for examination may be formed having a height along the lamination direction larger than a thickness of the semiconductor plate.

Further, a plurality of the outer electrodes for examination may be provided, and each of the outer electrodes for examination may be provided for different semiconductor plates.

Further, the end faces of the wiring electrodes may be formed on the side surface for wiring, and a connection electrode may be further provided which connects the end faces of the wiring electrodes arranged along the lamination direction in a manner to step over all of the semiconductor plates.

Further, it is preferable that the semiconductor plate further includes a surface insulating layer formed to cover the semiconductor device, and the wiring electrode for examination is formed in a protruding shape rising above a surface of the surface insulating layer, and the end face thereof is formed in a projecting end face projecting outward from the surface of the surface insulating layer.

Further, the present invention provides a semiconductor substrate having a plurality of groove portions formed along scribe lines, including: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and an inner electrode for examination formed in a protruding shape rising above a surface of the surface insulating layer, and having extended terminal portions extended inside the groove portion which are formed on both end portions thereof.

It is preferable that the semiconductor substrate further includes a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer.

Further, in case of the above-described semiconductor substrate, it is preferable that the surface insulating layer is structured integrally with an in-groove insulating portion formed inside the groove portion, and the wiring electrode has an extended terminal portion extended from the device region to an inside of the groove portion and formed in a protruding shape rising above a surface of the in-groove insulating portion.

Further, it is preferable that the wiring electrode has a cross side surface projecting outward from the surface of the surface insulating layer and crossing with the surface of the surface insulating layer, a top end face projecting outward from the surface of the surface insulating layer and disposed along the surface of the surface insulating layer, and an embedded portion embedded inward from the surface of the surface insulating layer.

Besides, it is preferable that the semiconductor substrate has a connecting pad connected to the semiconductor device; and a protecting insulating layer having a connecting hole formed at a position for forming the connecting pad, the protecting insulating layer being disposed under the surface insulating layer and formed to cover the device region, the wiring electrode has an electrode pad having an expanded height from a side outer than the surface of the surface insulating layer to the connecting pad.

Further, the present invention provides a method of manufacturing a laminated chip package, including the steps of: a substrate manufacturing step of manufacturing a substrate with inner electrode including a semiconductor device, a plurality of groove portions along scribe lines, a surface insulating layer formed on a surface on a side where the groove portions are formed, and a wiring electrode connected to the semiconductor device and an inner electrode for examination which are formed in a protruding shape rising above a surface of the surface insulating layer; a lamination step of laminating a plurality of the substrates with inner electrode to manufacture a laminated device wafer; a block manufacturing step of making end faces of the inner electrodes for examination appear on a cut surface when the laminated device wafer is cut along the groove portions, as projecting end faces projecting outward from the surface of the surface insulating layer to manufacture a device block; and an outer electrode formation step of forming an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates only for two adjacent semiconductor plates among the plural semiconductor plates constituting the device block.

It is preferable that in the above-described manufacturing method, in the substrate manufacturing step, a substrate without inner electrode in which a wiring electrode for examination in common with the wiring electrode is formed in place of the inner electrode for examination is manufactured in addition to the substrate with inner electrode, that in the lamination step, the substrate without inner electrode is placed at an uppermost position and a plurality of the substrates with inner electrode are laminated under the substrate without inner electrode to manufacture the laminated device wafer, that in the block manufacturing step, the end faces of the inner electrodes for examination and the end faces of the wiring electrodes for examination are made to appear on the cut surface as the projecting end faces to manufacture the device block, and that in the outer electrode formation step, a plurality of the outer electrodes for examination are formed, and at least one of the outer electrodes for examination is formed to connect the end face of the wiring electrode for examination and the end face of the inner electrode for examination along the lamination direction.

Further, it is preferable that in the substrate manufacturing step, two wiring electrodes for examination are formed on the substrate without inner electrode, and that in the outer electrode formation step, the outer electrodes for examination are formed to form a serial line for examination which is continuous from one of the wiring electrodes for examination to another of the wiring electrodes for examination together with all of the outer electrodes for examination and the inner electrodes for examination.

Further, it is preferable that in the outer electrode formation step, a plurality of the outer electrodes for examination are formed in a manner to be intermittently arranged along the lamination direction.

Further, it is preferable that in the outer electrode formation step, a plurality of the outer electrodes for examination are formed such that a plurality of outer electrode columns are disposed in each of which the outer electrodes for examination are intermittently arranged along the lamination direction.

It is preferable that the manufacturing method further includes the step of: forming a connection electrode which connects the end faces of the wiring electrodes arranged along the lamination direction in a manner to step over all of the semiconductor plates.

It is preferable that in the lamination step, a base and an adhesive used for fixing the substrate without inner electrode are removed to make the wiring electrode and the wiring electrode for examination appear in a protruding shape rising above a surface of the surface insulating layer.

The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be described with reference to the drawings. Note that the same components will be referred to with the same numerals or letters, while omitting their overlapping descriptions.

First Embodiment

Structures of Semiconductor Wafer1

To begin with, the structure of a semiconductor wafer1will be described with reference toFIG. 1toFIG. 3. The semiconductor wafer1is used for manufacturing a laminated chip package100according to an embodiment of the present invention. The laminated chip package100is manufactured using later-described semiconductor wafers51and52in addition to the semiconductor wafer1. The semiconductor wafer1does not have later-described inner electrodes for test27,28and thus has a configuration as a substrate without inner electrode.

FIG. 1is a perspective view illustrating the whole semiconductor wafer1.FIG. 2is a plan view illustrating a device region10and a testing region18and a region surrounding them formed in the semiconductor wafer1, andFIG. 3is a sectional view taken along the line3-3inFIG. 2.

The semiconductor wafer1is composed using a silicon wafer2. The semiconductor wafer1has, as illustrated inFIG. 1, scribe lines3A and3B formed on a first surface1aof the silicon wafer2(the rear surface side of the first surface1ais a second surface1b). A plurality of each of the scribe lines3A and3B are formed on the first surface1aand formed on straight lines at predetermined intervals along certain directions, respectively. The scribe lines3A are orthogonal to the scribe lines3B. The later-described device region10and testing region18(which will also be referred to as “examining region”) are formed within a region surrounded by the adjacent scribe lines3A,3A and3B,3B.

The semiconductor wafer1further has groove portions20and21formed in the first surface1a. The groove portions20and21are formed along the scribe lines3A and3B, respectively, and each of them has a depth of about 20 to 60 μm and a width of about 50 to 120 μm.

The semiconductor wafer1has a surface insulating layer22as illustrated in detail inFIG. 3. The surface insulting layer22is formed to cover the device region10and testing region18, and thus the surface insulting layer22covers almost the whole first surface1aof the semiconductor wafer1to constitute a surface layer of the semiconductor wafer1. The surface insulating layer22has a larger thickness than that of a later-described protecting insulating layer31and has a surface22cformed flat, and is disposed at the outermost position of the semiconductor wafer1except for portions where later-described wiring electrodes15, wiring electrodes16and wiring electrodes for test25,26(which will also be referred to as “wiring electrodes for examination”) are formed.

Further, the surface insulating layer22is structured integrally with in-groove insulating portions22aformed inside the groove portions20and21, and is thus formed in one body without joints between the in-groove insulating portions22aand other portions. The surface insulating layer22is formed with a plurality of contact holes22b, and one wiring electrode15or one wiring electrode16or one wiring electrode for test25or one wiring electrode for test26is formed in each of the contact holes22b.

The surface insulating layer22can be formed using a resin such as an epoxy resin or a polyimide resin, or an insulating material made of silicon silicate glass (SOG) or the like. In this embodiment, a case using a resin for the surface insulating layer22is discussed. It is especially preferable to form the surface insulating layer22using a resin having a low thermal expansion coefficient. This ensures that when the semiconductor wafer1is cut along the groove portions20and21by a dicing saw, the cutting can be easily performed.

The semiconductor wafer1has a silicon substrate30composed of the silicon wafer2, and upper portions thereof are the device regions10, the testing region18. A plurality of connecting pads32, connecting pads42are formed respectively on the surface of the device region10, the testing region18, and a portion other than the connecting pads32, connecting pads42is covered with the protecting insulating layer31.

The protecting insulating layer31is disposed under the surface insulating layer22and formed to cover the device region10and testing region18. The protecting insulating layer31is made of silicon dioxide (SiO2) or the like, and has connecting holes31aformed at positions where the connecting pads32,42are to be formed. The connecting holes31aare formed to expose the connecting pads32,42so as to connect the later-described wiring electrodes15,16, wiring electrodes for test25,26to the connecting pads32,42. The connecting pads32are connected to the semiconductor device in the device region10(seeFIG. 4for details).

The device region10and the testing region18adjoin each other. The whole of the device region10and the testing region18are a rectangular region surrounded by the adjacent groove portions20and20and the groove portions21and21as illustrated in detail inFIG. 2. A plurality of the device regions10and the testing region18are formed on the first surface1a, and each of them is a unit region divided from adjacent regions by the groove portions20and21.

Each of the device regions10has the memory portion formed on the first surface1aby performing wafer process, and a plurality of wiring electrodes15and16are formed. Wiring electrodes for test25and26are formed on the testing region18. Note that the wafer process means a manufacturing process of forming a semiconductor element and an integrated circuit on the wafer such as the silicon wafer2or the like.

In addition to the memory portion, an integrated circuit and a semiconductor element such as a CPU, a sensor, a drive circuit for the sensor may be formed as the semiconductor devices within the device region10. Further, a memory portion and an integrated circuit constituting a controller for controlling the memory portion may be formed in the device region10.

The wiring electrode15is made of a conductive material such as Cu or the like. The wiring electrode15has an extended terminal portion15aand a rectangular electrode pad15b, and the extended terminal portion15aand the rectangular electrode pad15bhave, as a whole, a protruding structure rising above the surface22cof the surface insulating layer22into a three-dimensional shape.

The wiring electrode15is illustrated in detail inFIG. 11andFIG. 18in addition toFIG. 3. An end face15gof the extended terminal portion15aof the wiring electrode15is a projecting end face projecting outward from the surface22cof the surface insulating layer22. Further, the wiring electrode15has a cross side surface15d, a top end face15e, and an embedded portion15f.

The cross side surface15dis a side surface portion projecting outward from the surface22cof the surface insulating layer22and crossing with the surface22cto rise up from (almost intersecting to) the surface22c. The top end face15eis connected to the cross side surface15dand projects outward from the surface22c, and further has a rectangular portion disposed in a direction along the surface22cand a band-shaped portion extending from the rectangular portion in a direction along the surface22ctoward the groove portion20. The embedded portion15fis a portion embedded inward from the surface22cto connect to the connecting pad32.

The electrode pad15bis composed of the cross side surface15d, the top end face15e, and the embedded portion15f, and the extended terminal portion15ais composed of the cross side surface15dand the top end face15e.

The electrode pad15bis connected to the connecting pad32via the contact hole22band the connecting hole31awhich are arranged to be stacked one on the other, and has a depth reaching the connecting pad32. More specifically, the electrode pad15bhas a height (an expanded height) h15expanded from the top end face15eouter than the surface22cto the connecting pad32via the contact hole22band the connecting hole31a. The expanded height h15is larger than a height h32of the connecting pad32(h15>h32). For example, h15is about 2 to 6 μm, and h32is about 0.5 to 1 μm.

The wiring electrode16is also made of a conductive material such as Cu or the like. The wiring electrode16has an extended terminal portion16aand a rectangular electrode pad16b, and the extended terminal portion16aand the electrode pad16bhave, as a whole, a protruding structure like the wiring electrode15. An end face16gof the extended terminal portion16aof the wiring electrode16is a projecting end face projecting outward from the surface22c.

Further, the wiring electrode16has a cross side surface16d, a top end face16e, and an embedded portion16f. The cross side surface16dis a side surface portion crossing with the surface22c, like the cross side surface15d. The top end face16ehas a rectangular portion disposed in a direction along the surface22cand a band-shaped portion extending from the rectangular portion in a direction along the surface22ctoward the groove portion20, like the top end face15e. The embedded portion16fis a portion embedded inward from the surface22cand connected to the connecting pad32, like the embedded portion15f. Further, the electrode pad16bis composed of the cross side surface16d, the top end face16e, and the embedded portion16f, and the extended terminal portion16ais composed of the cross side surface16dand the top end face16e. The electrode pad16balso has an expanded height like the electrode pad15b.

The extended terminal portions15aand the electrode pads15bof the wiring electrodes15are formed along a part of the outer periphery of the device region10and testing region18, whereas the extended terminal portions16aof the wiring electrodes16are formed across the device region10. Further, the electrode pads16bare disposed along a part of the outer periphery of the device region10and testing region18to be opposed to the electrode pads15b.

Respective portions of the extended terminal portions15aand the extended terminal portions16aextend from the device region10into the groove portion20. More specifically, the extended terminal portions15aand the extended terminal portions16aare formed such that their respective portions on their tip sides apart from the electrode pads15band16bbulge out from an edge portion of the groove portion20and stay inside the groove portion20in the width direction. Further, the extended terminal portions15aand the extended terminal portions16aare formed such that their respective portions extending out from the device region10are in a protruding shape rising above the surface22cof the in-groove insulating portions22a.

The wiring electrode for test25is made of a conductive material such as Cu or the like. The wiring electrode for test25has a structure in common with the wiring electrode15. The wiring electrode for test25has an extended terminal portion25aand an electrode pad25b, and the extended terminal portion25aand the electrode pad25bhave, as a whole, a protruding structure rising above the surface22cof the surface insulating layer22into a three-dimensional shape. The extended terminal portion25ahas a structure in common with the extended terminal portion15a. The electrode pad25bhas a structure in common with the electrode pad15b. The end face25gof the extended terminal portion25ais a projecting end face in common with the end face15g.

Besides, the wiring electrode for test26is made of a conductive material such as Cu or the like. The wiring electrode for test26has a structure in common with the wiring electrode16. The wiring electrode for test26has an extended terminal portion26aand an electrode pad26b, and the extended terminal portion26aand the electrode pad26bhave, as a whole, a protruding structure rising above the surface22cof the surface insulating layer22into a three-dimensional shape. The extended terminal portion26ahas a structure in common with the extended terminal portion16a. The electrode pad26bhas a structure in common with the electrode pad16b. The end face26gof the extended terminal portion26ais a projecting end face in common with the end face16g.

The semiconductor wafer1has the extended terminal portions15a, the extended terminal portions16aand the extended terminal portions25a, the extended terminal portions26aTherefore, in the cut surfaces when the semiconductor wafer1is cut along the groove portions20, the later-described end faces15c,16cand25c,26cappear projecting outward from the surface22c.

Further, a number of the wiring electrodes15and16are alternately arranged along the groove portion20. These wiring electrodes15and16are united together to form a wiring electrode group17. Further, in the wiring electrodes15and16, the extended terminal portions15aand16aare extended only to the groove portion20on the left side or the right side that is a part of the four groove portions which are all of the groove portions surrounding and contacting with the device region10and testing region18, that is, the adjacent two groove portions20and20and two groove portions21and21. The wiring electrode group17has an unevenly distributed structure by such an unevenly distributed arrangement of the extended terminal portions15aand16a.

In the memory portion of the device region10, a number of memory cells41as the semiconductor devices are formed. The memory cell41has a structure as illustrated inFIG. 4.FIG. 4is a sectional view mainly illustrating memory cells41of a later-described laminated chip package100using two semiconductor wafers1.

To the memory cell41, the wiring electrodes15and16are connected via the connecting pads32. The memory cell41is formed on the surface of an N-type substrate71constituting the semiconductor wafer1. InFIG. 4, two memory cells41are laminated one on the other via an adhesive layer33. The adhesive layer33is formed by an adhesive used when the semiconductor wafers1are bonded together.

Each of the memory tells41constitutes a flash memory and is formed on a P-type well72which is formed on the surface of the N-type substrate71. The memory cell41has a source73A and a drain73B, insulating layers77, an insulating film81, a floating gate82, an insulating film83and a control gate84. The memory cell41further has a source electrode74, a drain electrode76and a gate electrode75.

Both of the source73A and the drain73B are N-type regions and connected with the source electrode74and the drain electrode76, respectively. The insulating layers77are formed with contact holes for connecting the connecting pads32to the source electrode74and the drain electrode76, respectively. The source electrode74, the gate electrode75, and the drain electrode76are connected to the source73A, the control gate84and the drain73B via the corresponding contact holes, respectively.

Method of Manufacturing Semiconductor Wafer1

Subsequently, the method of manufacturing the semiconductor wafer1having the above-described structure will be described with reference toFIG. 5toFIG. 10. Here,FIG. 5is a plan view similar toFIG. 2, illustrating the partially manufactured semiconductor wafer, andFIG. 6is a sectional view taken along the line6-6inFIG. 5.FIG. 7is a plan view similar toFIG. 2, illustrating the semiconductor wafer subsequent to that inFIG. 5, andFIG. 8is a sectional view taken along the line8-8inFIG. 7.FIG. 9is a plan view similar toFIG. 2, illustrating the semiconductor wafer subsequent to that inFIG. 7, andFIG. 10is a sectional view taken along the line10-10inFIG. 9. Note that hatching is given to the surface insulating layer22inFIG. 7andFIG. 9for convenience of illustration.

For manufacturing the semiconductor wafer1, a wafer (unprocessed wafer) is prepared which has memory portions and a plurality of connecting pads32formed in the device regions10and a plurality of connecting pads42formed in the testing regions18by performing wafer process. Then, the protecting insulating layer31is formed on the first surface1afor the unprocessed wafer, and then the connecting holes31aare formed at the locations in the protecting insulating layer31where the connecting pads32,42are to be formed, as illustrated inFIG. 6. Then, the groove portions20and21are formed along the scribe lines3A and3B. The groove portions20and21can be formed by the dicing saw, and may be formed by etching such as the reactive ion etching or the like.

Subsequently, a resin, for example, an epoxy resin, a polyimide resin or the like is applied to the entire first surface1a. Then, the applied resin spreads over the entire surface of the unprocessed wafer and further flows into the groove portions20and21. Subsequently, the surface of the unprocessed wafer is polished to be planarized. Thus, the surface insulating layer22is formed to cover the entire surface of the unprocessed wafer. The portions flowed into the groove portions20and21form the in-groove insulating portions22a, so that the surface insulating layer22is formed integrally with the in-groove insulating portions22a.

Subsequently, as illustrated inFIG. 9andFIG. 10, the contact holes22bare formed in the surface insulating layer22to expose the connecting pads32,42. Thereafter, the wiring electrodes15,16and the wiring electrodes for test25,26are formed. The wiring electrodes15,16and the wiring electrodes for test25,26are formed in a shape having the above-described protruding structure and including the extended terminal portions15a,16aand the extended terminal portions25a,26arespectively. The wiring electrodes15,16and the wiring electrodes for test25,26can be formed, for example, in the procedure as follows.

First, a not-shown seed layer for plating is formed on the surface insulating layer22. Next, a frame (not shown) including groove portions is formed on the seed layer. The frame is formed, for example, by patterning a photoresist by the photolithography. Further, a plating layer which will be portions of the wiring electrodes15,16and the wiring electrodes for test25,26is formed within the groove portions of the formed frame and on the seed layer. Subsequently, the frame is removed, and a portion of the seed layer other than the portion which exists under the plating layer is removed by etching. By the above processing, the wiring electrodes15,16and the wiring electrodes for test25,26can be formed of the plating layer and the seed layer thereunder.

Because, the wiring electrodes15,16and the wiring electrodes for test25,26are formed after the formation of the surface insulating layer22, the extended terminal portions15a,16aand25a,26aare formed in a manner that they are wholly disposed on the surface22cof the surface insulating layer22. The electrode pads15b,16band25b,26bare formed such that their peripheral portions are disposed on the surface22cand their center portions are embedded inward from the surface22cto connect with the connecting pads32.

Structures of Semiconductor Wafer51

Next, the structure of a semiconductor wafer51will be described with reference toFIG. 12. The semiconductor wafer51is different from the above-described semiconductor wafer1in that two inner electrodes for test27are formed in place of the wiring electrodes for test25,26, in the testing region18, but has the same configuration in the other points. The semiconductor wafer51has the inner electrodes for test27formed thereon and thus has a configuration as a substrate with inner electrode.

The inner electrode for test27is an inner electrode for examination according to this embodiment made of a conductive material such as Cu or the like and has a turn structure in a substantially U-shape in which extended terminal portions27aare formed at both end portions thereof, respectively. The inner electrode for test27has, as a whole, a protruding structure rising above the surface22cinto a three-dimensional shape. The inner electrode for test27is formed under the conditions in common with the wiring electrodes15,16though it is different in shape from the wiring electrodes15,16.

The inner electrode for test27has the two extended terminal portions27a,27aand an intermediate portion27b. The inner electrode for test27is formed in one body to be continuous from one of the extended terminal portions27ato the other extended terminal portion27apassing through the intermediate portion27b. When current flows to the inner electrode for test27from the one extended terminal portion27a, the current passes through the intermediate portion27b, turns back, and flows out from the other extended terminal portion27a.

The two extended terminal portions27aare extended, similarly to the extended terminal portion15a, from the testing region18to the inside of the groove portion20. Therefore, the two extended terminal portions27aare partially cut afterward along the groove portion20, so that later-described respective end faces27cappear. On the end faces27c, later-described outer electrodes for test65,66are formed.

Note that though the illustrated inner electrode for test27is formed in a structure in which the two extended terminal portions27aare substantially orthogonal to the intermediate portion27b, it may be formed in a U-shape by connecting the two extended terminal portions27aby a curved intermediate portion27b.

Structure of Semiconductor Wafer52

The structure of a semiconductor wafer52will be described with reference toFIG. 13. The semiconductor wafer52is different from the above-described semiconductor wafer51in that an inner electrode for test28is formed in place of the two inner electrodes for test27, in the testing region18, but has the same configuration in the other points. The semiconductor wafer52has the inner electrode for test28formed thereon and thus has a configuration as a substrate with inner electrode.

The inner electrode for test28is different from the above-described inner electrode for test27in that two extended terminal portions28a,28aare formed with a large space therebetween, but has the common structure in the other points. The inner electrode for test28has the same turn structure in a substantially U-shape as that of the inner electrode for test27, and has a protruding structure. The inner electrode for test28is different in shape from the wiring electrodes15,16, but is formed under the conditions in common with the wiring electrodes15,16.

Further, the inner electrode for test28has two extended terminal portions28asimilar to the extended terminal portions27a, and has an intermediate portion28bsimilar to the intermediate portion27a. The two extended terminal portions28aare extended, similarly to the extended terminal portions15a, from the testing region18to the inside of the groove portion20. Therefore, the two extended terminal portions28aare also partially cut afterward along the groove portion20, so that later-described respective end faces28cappear. On the end faces28c, later-described outer electrodes for test65are formed.

Structure of Laminated Chip Package

By using the semiconductor wafer1and the semiconductor wafers51,52having the above-described structure, a laminated chip package100can be manufactured. The structure of the laminated chip package100will be described as follows.

The laminated chip package100has a structure in which one device plate60, six device plates61, and one device plate62are stacked so that eight device plates in total are laminated as shown inFIG. 20,FIG. 21, andFIG. 22.FIG. 20is a perspective view showing the laminated chip package100with a part thereof omitted,FIG. 21is a side view of the laminated chip package100, andFIG. 22is a perspective view showing the laminated chip package100with a part thereof omitted, illustrating all the device plates thereof disassembled. In the laminated chip package100, the device plate60as a surface layer plate is laminated at the uppermost position, the six device plates61are laminated under the device plate60, and the device plate62is laminated under the device plates61.

Further, in the laminated chip package100, wiring of the device plates60,61and62is realized by the connection electrodes63. In the laminated chip package100, all of the connection electrodes63are formed on the wiring side surface100A that is one of four side surfaces. This realizes the single-side wiring structure in the laminated chip package100.

The laminated chip package100can realize memories with various storage capacities such as 64 GB (gigabyte), 128 GB, and 256 GB by varying the memory portions in the semiconductor wafer1,51,52. Note that eight device plates are laminated in the laminated chip package100. However, it is only necessary that a plurality of device plates are laminated, and the number of the laminated device plates is not limited to eight.

In the laminated chip package100, a plurality of end faces15cand a plurality of end faces16care formed. Further, connection electrodes63are formed to connect all of the end faces15cor16cover the device plates60,61, and62.

Besides, outer electrodes for test65,66are formed on a wiring side surface100A. The outer electrodes for test65,66are shown inFIG. 29andFIG. 30as well as inFIG. 20,FIG. 21, andFIG. 22.

The outer electrodes for test65,66are outer electrodes for examination according to this embodiment, and a plurality of outer electrodes for test65and a plurality of outer electrodes for test66are formed (eight outer electrodes for test65and six outer electrodes for test66). The outer electrode for test65,66is formed only for two adjacent device plates among the eight device plates60,61, and62in total, namely, to electrically connect only two adjacent device plates with the other device plates excluded from the target for electrical connection so as not to connect the other device plates. The outer electrodes for test65,66are different from the connection electrode63in height and positions where they are formed, but are formed under the common conditions such as a material and a forming method.

Then, each of the outer electrodes for test65is formed in one of three connection patterns shown in 1), 2), and 3), that is, a connection pattern A, a connection pattern B, and a connection pattern C, and each of the outer electrodes for test66is formed in the connection pattern B shown in 2). Note that a lamination direction E shown in 1), 2), and 3) is a direction in which the device plates60,61, and62are laminated, meaning a direction of the thickness of the laminated chip package100.

1) A connection pattern A: A connection pattern in which the end faces25c,26cof the wiring electrodes for test25,26are connected to the end faces27c,27cof the inner electrodes for test27formed directly under them in the lamination direction E.

2) A connection pattern B: A connection pattern in which the end faces27c,27cof the inner electrodes for test27,27vertically arranged are connected in the lamination direction E.

3) A connection pattern C: A connection pattern in which the end faces27c,27cof the inner electrodes for test27are connected to the end faces28c,28cof the inner electrodes for test28formed directly under them in the lamination direction E.

The outer electrode for test65is formed in the connection pattern A when it is disposed at the uppermost position and formed in the connection pattern C when it is disposed at the lowermost position. In other cases, it is formed in the connection pattern B. All of the outer electrodes for test66are formed in the connection pattern B.

The outer electrodes for test65,66are intermittently arranged out of contact with each other along the lamination direction E so that they are formed to connect different target device plates among the device plates60,61, and62. Besides, in the arrangement of the outer electrodes for test65,66as seen from the device plate60toward the device plate62, the outer electrodes for test65,66alternately appear. Further, outer electrode columns65L,66L shown inFIG. 21are constituted of the plurality of outer electrodes for test65,66arranged along the lamination direction E. In the laminated chip package100, the outer electrode columns65L,66L are formed two each. The outer electrode columns65L,66L mean intermittent arrangements of the outer electrodes for test65,66respectively.

Further, the outer electrodes for test65,66will be described in detail with reference toFIG. 29andFIG. 30as follows. Note that the wiring electrode for test26from among the wiring electrodes for test25,26is shown, and the illustration of the wiring electrode for test25is omitted inFIG. 29andFIG. 30. Further, the end faces26c,27care dotted for convenience of illustration.

The laminated chip package100is manufactured by laminating the semiconductor wafers51under the above-described semiconductor wafer1(described later for detail). Therefore, the end faces27c,27care formed directly under the end faces25c,26c. As described above, the wiring electrodes for test25,26have the protruding structure, and therefore the end faces25c,26care formed as projecting end faces. Meanwhile, the inner electrodes for test27also have the protruding structure, and therefore the end faces27c,27care also formed as projecting end faces. Incidentally, when manufacturing the laminated chip package100, the semiconductor wafer51is boded to the semiconductor wafer1using an adhesive (described later for detail). Accordingly, the end faces27c,27care covered by the adhesive layer33made of the adhesive used in manufacture, and the end faces27c,27care located below the lower surface of the upper device plate. Similarly, the end faces28c,28care located below the lower surface of the upper device plate.

The outer electrodes for test65,66connect the plural end faces in such a positional relation in the above-described connection patterns, and are therefore formed to have heights along the lamination direction E larger than the thicknesses of the device plates60,61, and62.

On the other hand, inFIG. 22, the connection relation between the wiring electrodes for test25,26and the inner electrodes for test27, the inner electrode for test28, the outer electrodes for test65,66is shown.

As described above, the end face25cof the wiring electrode for test25is connected to the end face27cof the inner electrode for test27located directly under it by the outer electrode for test65. Further, the other end face27cof the same inner electrode for test27is connected to the end face27cof the inner electrode for test27located directly under it by the outer electrode for test66. Hereinafter, the connection in the connection pattern B of the outer electrodes for test65,66is repeated four times. Then, the connection in the connection pattern C is repeated twice for the lowermost device plate61and the device plate62. Furthermore, the connection in the connection pattern B of the outer electrodes for test65,66is repeated five times, and the connection in the connection pattern A of the outer electrodes for test65is finally performed once.

In addition, the inner electrodes for test27,28have the turn structure. Therefore, in the laminated chip package100, the connections between the end faces by the outer electrodes for test65,66as described above are performed to form a line for test100L. The line for test100L is a line for examination according to the embodiment of the present invention, and is constituted of a series of electrodes between the wiring electrode for test25and the wiring electrode for test26together with the outer electrodes for test65,66and the inner electrodes for test27,28all of which are continuous. In the laminated chip package100, when current flows from the wiring electrode for test25, the current reaches the wiring electrode for test26passing through the line for test100L. In other words, the current flows in a direction shown by arrows f and g, passing through all of the inner electrodes for test27,28and the outer electrodes for test65,66, and reaches the wiring electrode for test26.

This line for test100L can be used for a test to confirm the contact resistance between the wiring electrodes15,16and the connection electrodes63in the laminated chip package100(referred to also as a resistance confirmation test and will be described later for detail). In this case, the wiring electrode for test25has a function as a first wiring electrode for examination, and the wiring electrode for test26has a function as a second wiring electrode for examination.

Since the above-described line for test100L is formed in the laminated chip package100, the resistance confirmation test can be conducted by bringing a not-shown test device into contact with the wiring electrodes for test25,26and applying a voltage for examination between them. By the resistance confirmation test, the values of the contact resistance between the wiring electrodes for test25,26or the inner electrodes for test27,28and the outer electrodes for test65,66, which constitute the line for test100L, can be obtained. Thus, the wiring electrodes for test25,26have a structure in common with the wiring electrodes15,16and are formed under the conditions in common with the wiring electrodes15,16. The inner electrodes for test27,28are formed under the conditions in common with the wiring electrodes15,16though they are different in shape from the wiring electrodes15,16. Further, the outer electrodes for test65and66are formed under the conditions in common with the connection electrode63. Therefore, the values of the contact resistance between the wiring electrodes15,16and the connection electrodes63can be estimated from the obtained values of the contact resistance.

On the other hand, if the obtained value of the contact resistance is abnormal, it can be judged that there is a failure in the contact at some portion in the line for test100L. In this case, for example, it is possible to bring the test device into contact with the wiring electrode for test25and any of the outer electrodes for test66and conduct the resistance confirmation test again. Further, it is also possible to bring the test device into contact with the outer electrode for test65and the outer electrode for test66and conduct the resistance confirmation test.

Besides, both of the outer electrodes for test65,66are provided only for two adjacent device plates among the device plates60,61, and62. This also makes it possible to conduct the resistance confirmation test only on a part of the device plates60,61, and62even though the device plates60,61, and62are laminated at eight layers in the laminated chip package100. The resistance confirmation test only on a part of the laminated device plates is referred to also as an individual test.

The laminated chip package100has a structure in which the resistance confirmation test on all of the device plates60,61, and62and the individual test are easily conducted and a structure in which the contact resistance between the device plates is easily confirmed. Therefore, for the laminated chip package100, the process of the resistance confirmation test can be simplified, and the time required for the resistance confirmation test can be reduced. This makes it possible to reduce the manufacturing time of the laminated chip package100and increase the number of laminated chip packages100which can be manufactured in a unit time. Consequently, the unit manufacturing cost of the laminated chip packaged can be reduced.

Method of Manufacturing Laminated Chip Package

Subsequently, the method of manufacturing the laminated chip package100having the above-described structure will be described usingFIG. 14toFIG. 17as follows.

Here,FIG. 14is a sectional view similar toFIG. 3, illustrating the semiconductor wafer1in the process of manufacturing the laminated chip package100and a base34.FIG. 15is a sectional view similar toFIG. 3, illustrating the process subsequent to that inFIG. 14.FIG. 16is a sectional view similar toFIG. 3, illustrating the process subsequent to that inFIG. 15, andFIG. 17is a sectional view similar toFIG. 3, illustrating the semiconductor wafer1,51,52in the process subsequent to that inFIG. 16.

The laminated chip package100is manufactured as follows. First, a substrate manufacturing process is performed to manufacture the semiconductor wafer1being the substrate without inner electrode and the semiconductor wafers51and52being the substrates with inner electrode.

Then, a lamination process of manufacturing the laminated device wafer is performed. In this lamination process, an adhesive is applied first on the first surface1ato fix the semiconductor wafer1to the base34. InFIG. 14, the adhesive layer33made of the adhesive applied this time is shown. The semiconductor wafer1is used as the uppermost substrate to be located at the uppermost position of a later-described laminated device wafer98. The base34is a member for supporting the semiconductor wafer1and a glass plate is used inFIG. 14. Subsequently, polishing is performed on the second surface1bof the semiconductor wafer1until the groove portions20,21appear to reduce the thickness of the semiconductor wafer1as shown inFIG. 14.

Next, the semiconductor wafer51is bonded to the second surface1bside of the semiconductor wafer1as illustrated inFIG. 15using an adhesive. In this event, position adjustment of the semiconductor wafer1and the semiconductor wafer51is performed such that the positions of the groove portions20and21of both of them coincide with each other. Then, the second surface1bof the semiconductor wafer51is polished until the groove portions20and21appear. This polish decreases the thickness of the semiconductor wafer51to thereby obtain a laminated device wafer. In the laminated device wafer, the semiconductor wafer1and the semiconductor wafer51are laminated.

Further, as illustrated inFIG. 16, other semiconductor wafers51,51are prepared. Then, for each of the semiconductor wafers51and51, a process of bonding it to the second surface1bside of the laminated device wafer and polishing it (a bonding and polishing process) is performed.

Continuously, the bonding and polishing process is repeatedly performed for other semiconductor wafers51. As a result, the bonding and polishing process is performed for the six semiconductor wafers51in total. Then, the bonding and polishing process is performed for the semiconductor wafer52as shown inFIG. 17.

Thereafter, when the base34and the adhesive layer33are removed, the laminated device wafer98as shown inFIG. 17is manufactured. In the laminated device wafer98, the semiconductor wafer1is placed at the uppermost position, and the six semiconductor wafers51and the one semiconductor wafer52are stacked thereunder, so that the eight semiconductor wafers in total are laminated. In the laminated device wafer98, the wiring electrodes15,16and the wiring electrodes for test25,26of the semiconductor wafer1appear in the protruding shape because the base34and the adhesive layer33have been removed.

Subsequently, a block manufacturing process is performed. In this block manufacturing process, the laminated device wafer98is cut along the groove portions20and21. Thus, a device block99in a rectangular parallelepiped shape is obtained as illustrated inFIG. 19.FIG. 19is a perspective view illustrating the device block99. One of four side surfaces of the device block99is a wiring side surface99a. At the wiring side surface99a, later-described end faces15cand16cof the extended terminal portions15aand16aappear to project outward from the surface22cof the surface insulating layer22. Besides, later-described end faces25cand26cof the extended terminal portions25aand26aappear to project outward from the surface22c. Further, a plural pair of the end surface27c,27cof the extended terminal portions27aappear, one pair of the end surface28c,28cof the extended terminal portions28aappears. The end surface27c,27cand the end surface28c,28cappear to project outward from the surface22c.

Then, an outer electrode forming process is performed to form the outer electrodes for test65,66and the connection electrodes63under the common conditions on the wiring, side surface99aas shown inFIG. 20. As a result, the laminated chip package100is manufactured. The connection electrodes63are formed in a band shape on the wiring side surface100A to connect the vertically arranged plural end faces15cor the vertically arranged plural end faces16c. The outer electrodes for test65,66are formed to connect the end faces25c,26cof the wiring electrodes for test25,26or the end faces27c,28cof the inner electrodes for test27,28in the lamination direction E only for two adjacent device plates among the laminated device plates. In this event, two of the outer electrodes for test65are formed to connect the end faces25c,26cand the end faces27c,28calong the lamination direction E, and the other outer electrodes for test65are formed to connect the end faces27c,28cof the inner electrodes for test27,28along the lamination direction E.

The laminated chip package100is manufactured by forming the connection electrodes63on the wiring side surface99a. The end faces15cand16cconnected by the connection electrodes63are formed in a manner to project upward from the surface22c.

At the time of forming the connection electrodes63, the mask pattern for forming the connection electrodes63needs to be accurately placed, but the laminated chip package100can be manufactured even if the position adjustment of the mask pattern is roughly performed. Even with the rough position adjustment, the connection electrodes63connecting the vertically arranged plural end faces15cor the vertically arranged plural end faces16ccan be formed.

More specifically, in the laminated chip package100, the alignment does not need to be performed with high accuracy when forming the connection electrodes63. Therefore, the process after the device block99in the rectangular parallelepiped shape is obtained can be simplified, thereby simplifying the whole manufacturing process of the laminated chip package100. Accordingly, the manufacturing time of the laminated chip package100can be reduced. This can increase the number of laminated chip packages100manufacturable in a unit time, resulting in a reduced manufacturing cost of the laminated chip package100.

The reason why the alignment does not need to be performed with high accuracy when forming the connection electrodes63is given as follows.

First of all, the device block99has four side surfaces composed of cut surfaces when the laminated device wafer98is cut. In one of the cut surfaces, the end faces15cand16cappear as end faces projecting similarly to the end faces15gand16g(seeFIG. 11for details). This is because of the following reason. Note that the end face projecting is also referred to as a projecting end face in this embodiment.

The wiring electrodes15and16of each of the semiconductor wafers1(also the semiconductor wafer51,52) have the extended terminal portions15aand the extended terminal portions16arespectively. The extended terminal portions15aand the extended terminal portions16aare extended inside the groove portions20. For this reason, when the laminated device wafer98is cut along the groove portions20and21, the extended terminal portions15aand the extended terminal portions16aare also cut. Further, the end faces15cand16cformed when the extended terminal portions15aand the extended terminal portions16aare cut appear at one of the cut surfaces.

On the other hand, the extended terminal portions15aand16aare formed in the protruding shape similarly to the electrode pads15band16bhaving the expanded height h15. Therefore, the end faces15cand16cappear as projecting end faces projecting upward from the surface22c.

For the connecting pads32, a case where terminal portions extending to the inside of the groove portion20are formed is discussed here (the terminal portions are referred to as virtual terminal portions). In this case, end faces of the virtual terminal portions will appear at the side surface of the device block.

However, the extended terminal portions15aand16ahave top end faces15eand16ecommon with the electrode pads15band16bhaving the expanded height h15and are formed to be larger in thickness than the connecting pads32. For this reason, the end faces15cand16cwill appear having a larger size than the end faces of the above-described virtual terminal portions. In the device block99, the end faces15cand16chaving such a large size appear arranged in the vertical direction, so that the end faces15care easily connected to each other and the end faces16care also easily connected to each other. It is only necessary for the connection electrodes63to connect the end faces15cor the end faces16c. Therefore, the position adjustment of the mask pattern may be roughly performed at the time when the connection electrodes63are formed. For this reason, the alignment does not need to be performed with high accuracy when forming the connection electrodes63in the device block99.

Besides, the large size of the end faces15cand16cmeans that the sectional areas of the wiring electrodes15and16have been expanded. Accordingly, the resistance values of the wiring electrodes15and16can be decreased. This causes the current flowing through the wiring electrodes15and16to easily flow, so that the power consumption of the laminated chip package100can also be reduced.

Thus, the semiconductor wafer1has the wiring electrodes15and16as described above, whereby the manufacturing process of the laminated chip package100can be simplified to reduce the manufacturing time.

Further, the device block99has the electrode pads15band16brising above in the protruding shape appearing at its upper surface. When pad-like terminals rising above the surface of the insulating layer are required, the laminated chip package needs to be manufactured by stacking the terminal layer including such pad-like terminals (such a terminal layer is an interposer having no semiconductor device).

However, in the device block99, the device plate60having the electrode pads15band16brising above in the protruding shape is laminated at the uppermost position. Therefore, it is unnecessary to stack the interposer. Therefore, the terminal layer is not necessary, so that the laminated chip package100has a compact structure with an accordingly smaller height.

Further, because the semiconductor wafer1has the extended terminal portions15aand16aextending inside the groove portions20, the end faces15cand16ccan appear at the cut surfaces when the laminated device wafer is cut along the groove portions20. In other words, by cutting the laminated device wafer98, in which the semiconductor wafers1are laminated, along the groove portions20, the end faces15cand16ccan be obtained.

Therefore, it is unnecessary, when using the semiconductor wafer1, to expressly provide another process in order to make the wirings connecting to the device regions10appear at the cut surfaces. If the wiring electrodes15and16do not have the extended terminal portions15aand16a, the wiring electrodes15and16cannot be cut even by cutting the laminated device wafer along the groove portions20. Therefore, only by cutting the laminate device wafer along the groove portions, the wirings connecting to the device regions10cannot be made to appear at the cut surfaces. Thus, in order to make such wirings appear at the cut surfaces, another process needs to be performed.

In contrast, in the case of using the semiconductor wafer1, the end faces of the wiring electrodes15and16can be made to appear at the cut surfaces when the laminated device wafer is cut along the groove portions, and therefore it is unnecessary to expressly perform a process for making the wirings appear at the cut surfaces. Consequently, the manufacturing process of the laminated chip package can be further simplified by using the semiconductor wafer1.

Further, the wiring electrodes15and16are formed to rise above the surface insulating layer22. Therefore, when the end faces15cand16cappear at the cut surface, the end faces15clocated one above the other are arranged via the surface insulating layer22and the end faces16clocated one above the other are arranged via the surface insulating layer22. Accordingly, a situation that the device plates located one on the other short-circuit can be prevented.

Further, the wiring electrodes15and16in the semiconductor wafer1form the wiring electrode group17, and the wiring electrode group17has an unevenly distributed structure in which the wiring electrodes15and16are unevenly distributed at a part of the groove portions20and21which are in contact with the device region10. This ensures that when the laminated chip package100is manufactured using the semiconductor wafer1, the wiring connecting to the device region10can be placed closely to a single side surface to realize the single side surface wiring of the laminated chip package100.

Consequently, the semiconductor wafer1is suitable for manufacturing the laminated chip package100which can realize the single side surface wiring. Further, an inspection to examine presence or absence of a defective chip needs to be performed only on part of the cut surfaces of the semiconductor wafer1. Accordingly, the process of manufacturing the laminated chip package could be further simplified by using the semiconductor wafer1.

In addition, because the extended terminal portions15aand16ahave a narrow-width structure having narrower widths than those of the electrode pads15band16b, many wiring electrodes15and16can be arranged in the device region10. Accordingly, the wiring density of the wiring electrodes15and16can be increased in the semiconductor wafer1. Furthermore, the memory portions of each device region10are formed on the same plane in the semiconductor wafer1, so that the alignment error is 0 (zero).

Meanwhile, the device block99has a structure that the device plates61,62illustrated inFIG. 19are laminated under the device plate60illustrated inFIG. 18.

In the device block99, the end faces15cand16cappear at the side surface for wiring99abeing one of the side surfaces of the device block99. The side surface for wiring99ais a cut surface when the laminated device wafer98is cut along the groove portions20and21.

Structure of Device Plate

The device plate60is formed as a whole in a thin rectangular plate shape as illustrated inFIG. 18,FIG. 22, and its four side surfaces are covered by the insulating layer. This insulating layer is formed by cutting the semiconductor wafer1along the groove portions20and21, and therefore is made of the same resin as that of the in-groove insulating portions22a. The device plate60is disposed at the uppermost position. Therefore, the device plate60has a function of a surface layer plate constitutes a surface layer of the laminated chip package100.

Further, in the device plate60, the flat surface on one side is the surface22cof the surface insulating layer22, and the plural three-dimensional wiring electrodes15and three-dimensional wring electrodes16rising above the surface22care formed. Besides, wiring electrodes for test25,26are formed into a three-dimensional shape too. The end faces15c,16cof the wiring electrodes15,16and the end faces25c,26cof the wiring electrodes for test25,26appear as projecting end faces at a side surface60A being one of the four side surfaces. The end faces15cand16ccan be connected to the connection electrodes63. The end faces25cand26ccan be connected to the outer electrodes for test65,66. The surface insulating layer22of the device plate60constitutes its own surface layer, and constitutes the surface layer of the laminated chip package100.

The device plate61is different from the device plate60in that the device plate61has the adhesive layer33and inner electrodes for test27. Note that illustration of the adhesive layer33is omitted in theFIG. 22.

The device plate61is laminated under the device plate60via the adhesive layer33. In the device plate61, the end faces15cand16cof the wiring electrodes15and the wiring electrodes16are formed as projecting end faces projecting outward from the surface22cof the surface insulating layer22below the end faces15cand16cof the device plate60. Besides, the end faces27cand27cof the inner electrodes for test27are formed as projecting end faces below the end faces25cand26cof the device plate60.

The device plate62is different from the device plate61in that the device plate62has a inner electrode for test28in place of the inner electrodes for test27. Besides, in the device plate62, the end faces28cand28cof the testing inner electrode28are formed as projecting end faces below the end faces27cand27cof the device plate61.

Second Embodiment

Structures of Laminated Chip Package

Next, a laminated chip package101will be described with reference toFIG. 23andFIG. 24.FIG. 23is a perspective view showing the laminated chip package101with a part thereof omitted, illustrating all the device plates thereof disassembled.FIG. 24is a perspective view showing the laminated chip package101. The laminated chip package101is different from the laminated chip package100in the following points a, b, and c and is common with it in the other points:

a) the point that six device plates61A are laminated in place of the six device plates61;

b) the point that the outer electrode columns65L and66L are formed one each; and

c) the point that an outer electrode for test69is formed.

The device plate61A is different from the device plate61in that only one inner electrode for test27is formed, but has a common structure in other points. The outer electrode for test69is an outer electrode for examination according to this embodiment, and is formed only for two device plates disposed at the outermost positions among the eight device plates60,61A, and62in total. The outer electrode for test69is formed to electrically connect the device plates60and62which are disposed at the outermost positions but not connect the other device plates. The outer electrode for test69connects the end face26cformed on the device plate60to the end face28cformed on the device plate62.

In such a laminated chip package101, the connections similar to those of the laminated chip package100by the outer electrodes for test65,66are repeated, and then the connection by the outer electrode for test69is made. Thus, a line for test101L is formed in the laminated chip package101.

The line for test101L is a line for examination according to this embodiment, similar to the line for test100L, and is a line of series of electrodes between the wiring electrode for test25and the wiring electrode for test26together with the outer electrodes for test65,66,69all of which are continuous in one body. In the laminated chip package101, when current flows from the wiring electrode for test25, the current flows in a direction shown by arrows f and g, passing through all of the inner electrodes for test27,28and the outer electrodes for test65,66,69, and reaches the wiring electrode for test26. Therefore, the line for test101L can be used for the resistance confirmation test on the laminate chip package101, similarly to line for test100L. Accordingly, the resistance confirmation test similar on the laminated chip package100can be conducted also on the laminated chip package101. Consequently, the laminated chip package101has a structure in which the resistance confirmation test and the individual test are easily conducted as in the laminated chip package100, so that the contact resistance between the device plates can be easily confirmed and therefore the time required for the resistance confirmation test can be reduced.

Other Embodiments of Semiconductor Wafer

The laminated chip package100can be manufactured by using a semiconductor wafer91in place of the semiconductor wafer1. The structure of a semiconductor wafer91will be described with reference toFIG. 25

The semiconductor wafer91according to this embodiment is different in that it has a device region92, a testing region93in place of the device region10, the testing region18and that it has wiring electrodes86in place of the wiring electrodes16, and that it has wiring electrodes for test96in place of the wiring electrodes for test26as compared with the semiconductor wafer1.

The device region92is different from the device region10in that the wiring electrodes86are formed as well as the wiring electrodes15. The testing region93is different in that it has the wiring electrodes for test96as compared with the testing region18.

The wiring electrode86is made of a conductive material such as Cu or the like, and has an extended terminal portion86aand a rectangular electrode pad86b. The extended terminal portion86aand the electrode pad86bof the wiring electrode86are formed along a part of the outer periphery of the device region92and the testing region93, similarly to the wiring electrode15. Thus, in the device region92, the wiring electrodes15and86form the same wiring electrode group17as in the device region10, and additionally, all of their electrode pads15band86bare gathered to a single side of the device region92and the testing region93. In such a manner, the wiring electrodes15and86form a gathered pad group88in the device region92.

The wiring electrodes for test96are different from the wiring electrodes for test26in that the wiring electrodes for test96are formed along a part of the outer periphery of the device region92and the testing region93.

In the semiconductor wafer1according to the first embodiment, the extended terminal portion16aof the wiring electrode16and the extended terminal portion26aof the wiring electrode for test26are formed across the device region10. Therefore, a certain length of the extended terminal portion16a,26aneeds to be secured in the semiconductor wafer1.

On the other hand, in the semiconductor wafer91, the extended terminal portions86a,96aare formed along a part of the outer periphery of the device region92and testing region93, so that the length of the extended terminal portion86a,96acan be made smaller than that of the extended terminal portion16a,26a. In the semiconductor wafer91, the length of the extended terminal portion86a,96aare reduced to allow more quick access to the device region92. Further, the amount of plating or the like required for forming the wiring electrodes86, the wiring electrodes for test96can be reduced as compared to the case of forming the wiring electrodes16, the wiring electrodes for test26, resulting in a reduced cost.

In addition, the semiconductor wafer91can be used to simplify the manufacturing process of the laminated chip package which can realize the single side surface wiring, as with the semiconductor wafer1.

Other Embodiments

A semiconductor wafer111will be described with reference toFIG. 26andFIG. 27. In the semiconductor wafer1according to the first embodiment, the groove portions20and21are formed. The semiconductor wafer111is different from the semiconductor wafer1in that groove portions21are not formed but only groove portions20are formed. Accordingly, the semiconductor wafer111is formed such that a plurality of groove portions20are arranged at regular intervals and the groove portions are formed in the shape of stripes not intersecting with each other.

A semiconductor wafer112illustrated inFIG. 28is the same as the semiconductor wafer111in that only groove portions20are formed, but the groove portion20is formed along every other scribe line3A.

In the semiconductor wafer1, the device region10and the testing region18are in contact with the four groove portions20and21, so that the device region10and the testing region18are in contact with the groove portions20and21in the four directions, that is, upper, lower, right and left directions. Accordingly, as illustrated inFIG. 18, the device plate60manufactured from the semiconductor wafer1is covered by the same resin as that of the in-groove insulating portions22aat the four side surfaces.

In contrast, in the semiconductor wafer111, the device region10and the testing region18are in contact with the groove portions20only in the two, that is, right and left directions. Accordingly, a device plate using the semiconductor wafer in which the groove portions are formed in the shape of stripes as in the semiconductor wafer111is as follows. This device plate has two sets of opposite side surfaces, which are structured such that only the one set of opposite side surfaces is covered by resin but the other set of opposite side surfaces is not covered by any resin.

Note that though not illustrated, when this device plates are laminated, the laminated chip package can be obtained by forming connection electrodes on the opposite two side surfaces. This laminated chip package has a both-side wiring structure in which the connection electrodes are formed on both of the opposite faces.

In the semiconductor wafer112, the device region10and the testing region18are in contact with the groove portion20only in any one of right and left directions. Therefore, when the semiconductor wafer in which the groove portion is formed along every other scribe line as in the semiconductor wafer112is used, the end faces of the wiring electrodes appear only one of the side surfaces in the device plate. The other side surfaces are not covered by any resin.