Method of forming a circuit board

A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

FIELD

Embodiments of the invention are related generally to integrated circuit (IC) chip attachment to electronic device circuit boards, such as a motherboard. Other embodiments are also described.

BACKGROUND

Integrated circuit (IC) chips (e.g., “chips”, “dies”, “ICs” or “IC chips”), such as microprocessors, coprocessors, and other microelectronic devices often use package devices (“packages”) to physically and/or electronically attach the IC chip to a circuit board, such as a motherboard (or motherboard interface). The die is typically mounted within a package that, among other functions, enables electrical connections between the die and a socket, a motherboard, or another next-level component. As die sizes shrink and interconnect densities increase, such electrical connections require scaling so as to match both the smaller pitches typically found at the die and the larger pitches typically found at the next-level component.

An existing approach to interconnect scaling within microelectronic packages is to use a single high density interconnect (HDI) substrate to handle the space transformation from die bump pitch, where a typical pitch value may be 130-150 micrometers (microns or μm) to system board level (e.g., motherboard) pitch, where a typical pitch value may be 400 micrometers, i.e., 0.4 millimeter (mm). This approach results in very fine line, space, and via design rules to enable die routing and very large substrate body sizes in order to interface at the system board level pitch.

For certain devices, such as tablet computers, cell phones, smart phones, and value phone devices, it may be desirable to use a smaller die or IC chip footprints. For those devices it may also be desirable to use a low height IC chip packaging, such as a “low Z-height package”. However, current IC chip packages and motherboard mounting technologies suffer drawbacks, such as increased Z-height, increased cost, reduced manufacturing rate, and specialized equipment requirements, as compared to improved processes and devices described herein.

DETAILED DESCRIPTION

Several embodiments of the invention with reference to the appended drawings are now explained. Whenever the shapes, relative positions and other aspects of the parts described in the embodiments are not clearly defined, the scope of the invention is not limited only to the parts shown, which are meant merely for the purpose of illustration. Also, while numerous details are set forth, it is understood that some embodiments of the invention may be practiced without these details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

Embodiments described herein enable direct chip attach (DCA) of an integrated circuit chip to a circuit board, such as a motherboard, without using a packaging substrate or interposer (e.g., without using a package or packaging). According to some embodiments, the motherboard interconnect pitch is only changed in scale to a smaller pitch for a zone where the chip is mounted; and the chip interconnect pitch does not have to change. In some cases, the smaller pitch zone integrates aggressive design rule (DR) (e.g., DR comparable to that of where a substrate package interconnects to a chip) and then the interconnect pitch transitions to DR comparable to that of the motherboard (e.g., DR for where a motherboard interconnects to a package substrate). The embodiments can be adopted for smartphones, value phones or, tablet segments of products.

In some cases, the zone where the chip is mounted is formed by (i) transfer of finer or smaller pitch break-out patterns of interconnects for interconnect layers in this zone (e.g., onto a pre-preg based core) than for the surrounding zone or for the rest of the circuit board. In some other cases, the zone where the chip is mounted is formed by (ii) a laser scribing process such as laser projection and patterning (LPP) of ablated traces that are filled with copper before copper etching, and after copper etching. Embodiments can be adopted for smartphones, value phones or, tablet segments of products.

FIG. 1Ais a schematic top view of a circuit board upon which a substrate package for an integrated circuit chip is mounted, according to embodiments described herein.FIG. 1Ashows circuit board100including dielectric material101having top surface102. Substrate103is mounted on surface102at area109. Substrate103has substrate foot print104on or in motherboard100. Substrate103has substrate footprint104including interconnect package zone108at location107on surface102. Zone108has area109, length L1 and width W1 on or at surface102. Area109may be an area equal to L1×W1.

Substrate103, may be a substrate upon which an IC chip may be or is mounted. Substrate103may be a microelectronic package including or having a microelectronic die or IC chip mounted within the package, such as on one or more substrates of substrate103. Substrate103may have a height that is greater than a height of the IC chip. Footprint104includes package interconnect zone108of interconnects, such as a geographic area on surface102having a plurality of interconnects to which substrate103is attached. In some case, substrate103has package contacts electronically attached to package interconnects within zone108.

According to embodiments, instead of using substrate103, an IC chip may be directly mounted onto a circuit board. Such mounting may decrease Z-height, decrease cost, increase manufacturing rate and specialized equipment requirements. For example, direct chip attach (DCA) of an IC chip to a circuit board is an attractive proposition for reduction of bill-of-materials (BOM) cost for the tablet, smartphone, or value phone segments. However to enable this DCA the footprint, the interconnection pattern and the geometrical dimensions of the silicon and motherboard may not be compatible with each other.

FIG. 1Bis a schematic top view of a circuit board upon which an integrated circuit chip may be directly mounted, according to embodiments described herein.FIG. 1Bshows circuit board120including dielectric material101having top surface122. Board120may be a circuit board upon which to mount an integrated circuit chip. In some cases, board120is a board upon which chip123is DCA mounted. In some cases, board120is a single high density interconnect (HDI) substrate.

To enable DCA of chip123, a breakout area may be needed to make the silicon first level interconnect (FLI) design rule (DR) compatible with that of motherboard. A typical chip (e.g., tablet silicon) may be of order of 10 mm×10 mm (100 mm2) in footprint and the substrate package will be of order of 15 mm×15 mm to 17 mm×17 mm in footprint. The chip may have a first level interconnect of 130-150 micron pitch and the breakout area may have a second level interconnect of 400 micron pitch. So, to enable DCA one option for the board to scale aggressively in design rule (DR) capability, increasing the cost of the mother board many times higher. The other option could be increasing silicon size to match it to substrate foot print, definitely not a financially attractive option since a redesigned larger and slower chip is required. Some embodiments described herein try to bridge this gap using breakout area133(e.g., as shown inFIG. 1B), and/or by providing some new process flows that can be integrated into the circuit board manufacturing process.

FIG. 1Bshows chip123with chip footprint128including first interconnect zone124at location127on surface122. Zone128has area129, length L2 and width W2 on or at surface122. Zone124may include interconnects, contacts (e.g., contact pads) having a first pitch at surface122. Zone124includes first exposed contacts125having a first pitch126at or on surface122. Pitch126may be defined as the distance between center points of adjacent contacts125; as an average of the distances between center points of all contacts125; or a pitch determined by a design rule (DR) contacts125; or a pitch of contacts125as know in the art. The center points may be geographically calculated center location of the exposed area of a contact from above, or determined otherwise as know in the art.

Surrounding chip123or zone124is breakout area133including second interconnect zone134at location107on surface122. Area133may have inner length L2 and width W2 on or at surface122; and outer length L1 and width W1 on or at surface122. Area133may be an area equal to (L1×W1)−(L2×W2).

Area133may include interconnects, contacts (e.g., contact pads) having a second pitch at surface122. Area133includes second exposed contacts135having a second pitch136at or on surface122. Pitch136may be defined with respect to contacts135, similar to how pitch126is defined with respect to contacts125.

Area133may be defined as an area (or interconnect zone) between area129(or zone124) and area109(or zone108). Area133may includes zone134having contacts135which are electrically connected to contacts of chip123, or traces connected to chip123. In some cases, contacts135are conductive wires, routing or traces extending (e.g., along material of surface122, or another material or gap) from interconnects, contacts, or other electronic devices on or in the chip to contacts125on surface122. In some cases, contacts135do not include actual contacts that will be directly contacted to by contacts of chip123, but only include conductive wires, routing or traces extending (e.g., along material of surface122) from interconnects, contacts, or other electronic devices on or in the chip to contacts125.

In some cases, area133completely surrounds all sides of area129on surface122. In some cases, first pitch126is smaller than the second pitch136.

Chip123is directly mounted on surface122. Chip123occupies first interconnect zone124or area129of the surface122at location127. In some cases, location127is within or completely surrounded by location107. In some cases area129is within or completely surrounded by area133. In some cases, zone124is within or completely surrounded by zone134.

Mounting of chip123may include physically attaching or bonding a bottom surface of chip123to surface122. Such attaching may include epoxy, resin, other adhesive or attaching as know in the art. Mounting of chip123may include electrically connecting, physically attaching or bonding electrical contacts on a bottom surface of the chip to exposed contacts125on surface102. These electrical connections may include solder, ball grid array, conductive adhesive or other electrical connections as know in the art. Mounting of chip123may include electrically connecting contacts on a bottom surface, side surface, and/or top surface of chip123to exposed contacts125on surface102. Such electrical connecting may include solder on die formed on contacts of chip123, and attaching the solder on die to contacts125. Such attaching may use soldering or other methods know. These electrical connections may include solder, ball grid array, conductive adhesive or other electrical connections as know in the art. Such connecting may include using wires, routing or traces extending (e.g., along material of surface122, or another material or gap) from interconnects, contacts, or other electronic devices on or in the chip to contacts125on surface122. In some embodiments, contacts135include or are such wires, routing and traces.

Board120may include layers dielectric interconnects and contacts (e.g., contact pads) as known in the art. The interconnects and contacts of board120may be formed on or within one or more layers of dielectric101. The interconnects of zones124and134; and contacts of124and134may be formed on or within a top layer of dielectric101. Board120may be a circuit board, motherboard, or another board upon which an IC chip, or microprocessor, or CPU can be mounted. Dielectric material101, and other dielectric materials or layers of board120may include one or more layers of non-conductive material, pre-preg, base core, resin, and/or epoxy as known in the art. The interconnects, contacts, and conductor materials or layers of board120may be formed of a conductive material as known in the art. In some cases, appropriate conductive materials include copper, nickel, gold, gold, palladium, an alloy thereof, and the like as known in the industry. Circuit board120may include more (e.g., two or three) interconnect zones124and134than those shown.

As shown inFIG. 1B, embodiments may locally integrate some aggressive DR in zone124(DR comparable to that of the substrate package) and then transitions it to DR in zone134, comparable to that of the motherboard. In some cases, forming contacts125may include forming the contacts using processing (e.g., electronic device fabrication processing so that the contacts satisfy the DR) according to a design rule appropriate for direct chip attachment (DCA) of integrated circuit chip contacts to contacts of a substrate or interposer, such as a DR for chip attachment to a substrate package or interposer to be mounted onto a circuit board (e.g., motherboard). In some cases, forming contacts135may include forming the contacts using processing according to a design rule appropriate for direct attachment of substrate package or interposer contacts to contacts of a circuit board, such as a DR for substrate or interposer attachment to a motherboard.

Moreover, it can be appreciated that forming contacts125and/or135may include forming hundreds of contacts in zones124and125, such as formed on a wafer as known in the art. Also, it can be appreciated that forming layers222,232and242may include forming hundreds or thousands of interconnects in each layer, such as formed on a wafer as known in the art.

According to some embodiments, a motherboard will require one or two breakout layers for enabling the DCA, and the proposed circuit board device or process flow will have or create those two layers. According to some embodiments, two separate process flows have been proposed out of which either one can be employed. According to embodiments, two technology components that may enable forming board120include: (i) transfer of finer or smaller pitch break-out patterns of interconnects for interconnect layers, and (ii) laser scribing process such as laser projection and patterning (LPP) ablated traces. For example,FIGS. 2A-Emay describe devices and processes for transferring a pattern of contacts on pre-preg based core; andFIGS. 3A-Emay describe devices and processes for patterning traces created by a LLP and filled with copper before copper etching, and after copper etching.

FIGS. 2A-Emay include embodiments of a schematic depiction of a pattern transfer process or flow to enable shrink DR in breakout area of the motherboard for DCA of an IC chip. Embodiments of a process to form the fine patterned break-out on the sacrificial substrate are describe forFIG. 2C.

FIGS. 2A-Emay include embodiments of where the fine pattern of break-out (e.g., having contacts125) is manufactured in a separate sacrificial substrate (e.g., substrate320) and then the fine pattern is later transferred (e.g., flip bonded) to the motherboard (e.g., board120) at the location (X-Y) (e.g., location127or zone124or area129) where the fine pattern is desired. The transfer may happen before the Prepreg (e.g., dielectric layer256) is fully cured. In some cases, after transfer of the fine pattern, the rest of the layer manufacturing process (e.g.,FIG. 2E, an so on) remains the same.

FIG. 2Ashows a cross-sectional side view schematic of a circuit board having interconnect layers.FIG. 2Ashows a cross-sectional schematic of board120, having interconnect layer222, over interconnect layer232, which is over interconnect layer242.

In some cases, layer222has interconnects224formed through dielectric material of layer222and contacts228upon the surface of layer222. In some cases, layer222includes a layer of dielectric material, a plurality of interconnects224at a first (e.g., bottom in this case) surface of the layer of dielectric material and a plurality of contacts228at a second (e.g., top in this case) surface of the layer of dielectric material. In some cases, layer222has openings229through or between contacts228upon the surface of layer222. Openings229may extend to or expose dielectric of layer222.

In some cases, layer232has interconnects234formed through dielectric material of layer232and contacts238upon the surface of layer232. In some cases, layer232includes a layer of dielectric material, a plurality of interconnects234at a first (e.g., bottom in this case) surface of the layer of dielectric material and a plurality of contacts238at a second (e.g., top in this case) surface of the layer of dielectric material. In some cases, some or all of contacts238are attached to or electrically connected to interconnects224of layer222.

In some cases, layer242has interconnects244formed through dielectric material of layer242; and has contacts248and258upon opposing surfaces of layer242. In some cases, layer242includes a layer of dielectric material, a plurality of interconnects244within the layer of dielectric material, a plurality of contacts248at a first (e.g., top in this case) surface of the layer of dielectric material, and a plurality of contacts258at a second (e.g., bottom in this case) surface of the layer of dielectric material.

In some cases, some or all of contacts248are attached to or electrically connected to interconnects234of layer232. In some cases, layer242has openings249through or between contacts258upon the surface of layer242. Openings249may extend to or expose dielectric of layer242. Openings249may be formed by known processes.

FIG. 2Aalso shows zone124and134, dielectric101, and contacts258along the bottom surface of board120. Circuit board120may include more (e.g., two to a dozen more) or fewer (e.g., may only have two or three) interconnect layers than those shown. According to some embodiments,FIG. 2Amay show making of the board120to the (N−1) layer (e.g., layer222) for break-out routing (e.g., the copper layer, such as contacts228, just below break-out routing (e.g., contacts125).

FIG. 2Bshows a cross-sectional side view schematic of the circuit board ofFIG. 2Aafter forming a dielectric layer over; and dielectric and a conductive layer under the interconnect layers.FIG. 2Bshows dielectric layer256formed over or on openings229, contacts228, interconnects224, and dielectric of layer222.FIG. 2Balso shows dielectric layer266formed over or on openings249, contacts258, interconnects244, and dielectric of layer242. Conductor layer278is shown formed on a bottom surface274of dielectric layer266. According to some embodiments,FIG. 2Bmay show lamination of pre-preg (e.g., dielectric layer266) with copper foil (e.g., conductor278) onto the back side of motherboard (e.g., surface274, where no break-out routing is needed), and lamination of pre-preg (e.g., dielectric layer256) with no copper foil onto the front side of substrate (e.g., on layer222).

FIG. 2Cshows a cross-sectional side view schematic of a transfer substrate for transferring to a surface of the circuit board ofFIG. 2B.FIG. 2Cshows transfer substrate320, including dielectric328and contacts125, formed on dielectric328. Dielectric328may be silicon or glass material having a planar surface and an annular radius (e.g., an annular outer perimeter or annular shaped surface area). In some cases, contacts125are patterned copper traces and contacts formed onto the surface of dielectric328, or a material formed on dielectric328that allows dielectric328to be removed from board120and contacts125without damaging board120and contacts125. Contacts125may have pitch126and be within zone124.

According to some embodiments,FIG. 2Cmay show a pattern on a transferable substrate (e.g., substrate320) for transferring of the breakout routing (e.g., contacts125, such as patterned copper traces or contacts onto the surface) from the transferable substrate to the board (e.g., surface272). According to some embodiments,FIG. 2Cmay include manufacturing a fine pattern of break-out (e.g., having contacts125) in a separate sacrificial substrate (e.g., substrate320).

According to some embodiments, substrate320may be formed by processing or preparing a sacrificial substrate having dielectric328including the following. A surface of dielectric328may be lithographically patterned with the breakout pattern or pattern of contacts125. Then, the pattern of conductor (e.g., pattern of contacts125) may be plated onto the surface of dielectric328(e.g., upside down). Plating may include copper patterning or patterning of copper traces onto the surface. Then a dry file resist (DFR) strip may be performed (e.g., to remove the patterning). Then, the plated substrate may be singulated to produce a number of substrate320s.

FIG. 2Dshows a cross-sectional side view schematic of the circuit board ofFIG. 2Bafter transferring the patter of contacts from the substrate ofFIG. 2Cto a surface of the circuit board ofFIG. 2B.FIG. 2Dshows transfer substrate320flipped and bonded to dielectric256of board120. Contacts125of substrate320may be attached to or electrically connected to interconnects224or contacts228of interconnect layer222. Substrate320may be “flip chip bonded” to surface272of dielectric256. The transfer may happen before the Prepreg (e.g., dielectric layer256) is fully cured.

According to some embodiments, substrate320may be formed by processing or preparing a sacrificial substrate having dielectric328including the following. Forming a seed layer upon surface329of dielectric328. The seed layer (e.g., 1 micron thick) may include paladium, copper, and/or other know seed material upon which to form conductor material of contacts125. Next, a dry film (e.g., resist) patterning material may be formed on the seed layer. In some cases, this may be done as know in the art. Next, openings may be formed in the dry film patterning material in a pattern according to the first design rule, such as to form the pattern where contacts125will be formed. In some cases, this include lithograpical patterning and forming openings in the film according to the first design rule. This pattern may have pitch126. In some cases, this may be done as know in the art. Next, copper is plated in the pattern or openings between the surviving film, such as by electrolytic bath or plating. Later, the dry film may be dissolved, such as by dry file resist (DFR) removal. In some cases, this may be done as know in the art.

According to some embodiments, contacts125may be transferred to board120by processing using substrate320including the following. Contacts125of substrate320are bonded to dielectric256. In some cases, this bonding may optionally bond or electrically connected contacts125to traces, interconnects or routing in dielectric256. In come cases, if contacts135are already formed, this bonding may optionally bond or electrically connected contacts125to contacts135(e.g., traces, interconnects or routing of contacts135), before dielectric256is cured. In some cases, this bonding may include pressing substrate320into uncured surface272of dielectric256until the surface329of dielectric328and top surface272are coplanar. In some cases, this bonding may include embedding contacts125into uncured layer256so that the surface of contacts125attached to surface329become coplanar with surface272. In some cases, this bonding may include pressing substrate320into surface272of dielectric256with enough pressure to embed contacts125into a thickness of256equal to the thickness of contacts125.

Next, dielectric256is cured, such as by heating. Next, dielectric256may be cured, while surface329of dielectric328is coplanar with surface272. Curing may be by heating the structure shown inFIG. 2Duntil the dielectric256is cured. Next, dielectric328is removed, such as by etching. In some cases, this may be done as know in the art.

FIG. 2Dalso shows board120after removing substrate320, but not removing contacts125from surface272of dielectric256. Contacts125are shown exposed on top surface272of dielectric layer256. In some cases, some or all of contacts125are attached to or electrically connected to contacts135; interconnects or contacts of layers242,232and or222. In some cases, some or all of contacts125are attached to or electrically connected to contacts228of layer222. In some cases, some or all of contacts125are attached to or electrically connected to contacts135.

According to some embodiments,FIG. 2Dmay show a pattern of the breakout routing (e.g., contacts125) transferred (e.g., by substrate320) from the transferable substrate and released from the sacrificial substrate onto the circuit board (e.g., onto surface272). After transfer of the pattern, one or more next layers of finer break-out can be built onto surface272, if desired.

According to some embodiments,FIG. 2Dmay include transferring (e.g., flip bonding) a fine pattern of break-out (e.g., having contacts125) to the motherboard (e.g., board120) at the location (X-Y) (e.g., location127or zone124or area129) where the fine pattern is desired. In some cases, after transfer of the fine pattern, the rest of the layer manufacturing process (e.g.,FIG. 2E, an so on) remains the same for board120, as it was without the process ofFIGS. 2B-C. According to some embodiments,FIG. 2Dmay include transferring (e.g., flip bonding) a fine pattern of break-out (e.g., having contacts125) of interconnects onto a surface below the interconnect zone124prior to curing a dielectric material of the circuit board (e.g., dielectric256).

FIG. 2Eshows a cross-sectional side view schematic of the circuit board ofFIG. 2Dafter removing the transfer or sacrificial substrate to form contacts in the first interconnect zone having a pitch smaller than contacts on the rest of the circuit card.FIG. 2Eshows board120after removing substrate320, but not removing contacts125from surface272of dielectric256. Thus, contacts125are exposed on surface272prior to forming contacts135, and forming solder pattern450on surface272. Then, contacts135and solder pattern450are formed on surface272. In some cases, contacts135are conductive wires, routing or traces extending (e.g., along material of surface122, or another material or gap) from interconnects, contacts, or other electronic devices on or in the chip to contacts125on surface122.

Contacts428are shown below opening449and are exposed through pattern450. Forming contacts428may include forming interconnects414through dielectric256. Contacts428may include power and grounding contacts as known.

Opening449and contacts429may represent a number of openings. Opening449may also represent a number of contact125openings for electically connecting contacts of chip123to contacts125. Such contact125openings may have pitch126in zone124, and may have a size (e.g., area at surface122) appropriate for such electical connections. Opening449may be formed by lithographic patterning of pattern450as known in the art.

Contacts425and solder pattern451are also shown formed on a bottom surface of dielectric266. Forming contacts425and solder pattern451may include removing or patterning conductor278. Forming contacts425may include forming interconnects424through dielectric266.

In some cases, some or all of interconnects424are attached to or electrically connected to interconnects or contacts of layers242,232and or222. In some cases, some or all of interconnects424are attached to or electrically connected to contacts258of layer242.

In some cases, some or all of contacts425are attached to or electrically connected to interconnects or contacts of layers242,232,222and or interconnects424. In some cases, some or all of contacts425are attached to or electrically connected to interconnects424.

According to some embodiments,FIG. 2Emay show formation of plan of record (POR) via and pattern (e.g., contacts425and pattern451) and then solder radius (SR) layer patterning (e.g., pattern450) and BGA side solder resist opening (SRO) formation (e.g., opening449). According to some embodiments, POR may refer to processing, DR, vias, interconnects, interconnect layers, or pitch as described for the second pitch or forming contacts135.

According to some embodiments,FIGS. 2A-Emay show forming contacts125by transferring a transfer substrate having the contacts onto the surface of the circuit board, wherein transferring includes transferring the contacts (1) into a dielectric material of the circuit board below the surface of the circuit board prior to curing the dielectric material of the circuit board and (2) within the first interconnect zone (e.g., seeFIG. 2C-D). In some cases, transferring may include, after transferring and curing, removing the transfer substrate from the surface of the circuit board and leaving the contacts below the surface of the circuit board (e.g., seeFIG. 2E). In some cases, contacts135are formed in the second zone after forming contacts125, such as by patterning and etching conductor to form contacts135at locations within the second zone (e.g., seeFIG. 2E).

FIGS. 3A-Dmay include embodiments of a schematic depiction of a process or flow to enable a shrink DR in breakout area of the motherboard for DCA of an IC chip.FIGS. 3A-Dmay include embodiments of where the fine pattern of break-out (e.g., having contacts125) is formed by scribing the break-out DR contact vias (e.g., where contacts125will be formed) using a laser process (e.g., such as Laser Projection and Patterning (LPP)). The fine patter scribing can be performed on a surface of the motherboard (e.g., board120) at the location (X-Y) (e.g., location127or zone124or area129) where the fine pattern is desired. Then the scribed pattern trenches can be filled with copper via electro-less and electrolytic plated copper. The plated copper can then be patterned and etched to leave contacts125and135. In addition, the over-plated copper can be used in formation of the POR layer patterning (e.g., forming contacts135and/or425). In some cases, after forming the fine pattern (e.g., contacts125_, the rest of the layer manufacturing process (e.g.,FIG. 3D, an so on) remains the same.

FIG. 3Ashows a cross-sectional side view schematic of a circuit board having interconnect layers.FIG. 3Amay be equal toFIG. 2A.

FIG. 3Bshows a cross-sectional side view schematic of the circuit board ofFIG. 3Aafter forming a dielectric layer over interconnect layers, forming a dielectric layer under the interconnect layers, and laser drilling vias in at least the top dielectric layer.FIG. 3Bshows dielectric layer256formed over or on openings229, contacts228, interconnects224, and dielectric of layer222.FIG. 3Balso shows dielectric layer266formed over or on openings249, contacts258, interconnects244, and dielectric of layer242. Layer266has bottom surface274.

According to some embodiments,FIG. 3Bmay show pre-preg (e.g., dielectric layer256) laminated onto layer222with no copper foil on front side of substrate (e.g., on layer222), and pre-preg (e.g., dielectric layer266) laminated onto layer242with no copper foil (e.g., without conductor278) on the back side of motherboard. In some cases, there may be copper foil (e.g., conductor278) dielectric266.

According to some embodiments,FIG. 3Bmay show laser via drilling (e.g., using LPP or another appropriate laser drilling technology) laser vias529into a portion of the thickness of dielectric256. In some cases, laser vias529only extend into a portion of the thickness of dielectric256. In some cases, some of laser vias529only extend into a portion of the thickness of dielectric256, while others (or the rest) extend through the entire thickness of dielectric256.

According to some embodiments,FIG. 3Bmay include laser scribing a pattern of trenches of the first interconnects (e.g., contacts125) onto surface272of the interconnect zone124prior to forming first interconnect conductors (e.g., contacts125) in the pattern of trenches (e.g., prior toFIG. 3C). According to some embodiments,FIG. 3Bmay include laser projection and patterning (LPP) ablated traces of a pattern of trenches of the first interconnects (e.g., contacts125) into a surface of the interconnect zone124prior to plating a conductor onto the trenches (e.g., prior toFIG. 3C).

Vias529may be a pattern of the breakout routing (e.g., for contacts125, such as a patterned of vias to be filled with copper to form copper traces or contacts onto the surface272of dielectric256). According to some embodiments, laser scribing a pattern of trenches to form contacts125includes scribing a dielectric (e.g., dielectric256), solder resist, or dry resist. Later, a laser is used to burn or drill holes or a patterns in dielectric256at locations for contacts125. The laser may be a laser for such functions as know in the art.

The holes or a patterns in dielectric256may be formed in a pattern according to the first design rule, such as to form the pattern where contacts125will be formed. In some cases, this includes forming openings according to the first design rule. This pattern may have pitch126. In some cases, this may be done as know in the art.

In some cases, openings539are formed into or through dielectric256. Openings539may extend to or expose contacts228or interconnects of layer222. Openings539may be formed by known processes. In some cases, openings569are formed into or through dielectric266. Openings569may extend to or expose contacts258or interconnects of layer242. Openings569may be formed by known processes.

FIG. 3Cshows a cross-sectional side view schematic of the circuit board ofFIG. 3Bafter filling the vias and openings with conductor.FIG. 3Cshows laser vias529and openings539filled with conductor layer588, such as by filling the vias and openings during a single process or plating process. In some cases, copper may be built into the holes or pattern by copper plating. Filling via529may include forming interconnects414through dielectric256. Interconnects414may be attached to or electrically connected to interconnects224and/or contacts228of interconnect layer222.

In some cases, openings569are also filled with conductor layer578. In some cases, openings569are filled during the same process as openings539and vias529. Filling openings569may include forming interconnects424through dielectric266. Interconnects424may be attached to or electrically connected to interconnects244and/or contacts248of interconnect layer242. In some cases, some or all of interconnects424are attached to or electrically connected to interconnects or contacts of layers242,232and or222. In some cases, some or all of interconnects424are attached to or electrically connected to contacts258of layer242.

According to some embodiments,FIG. 3Cmay include filling trenches (e.g., vias529) with copper via electro-less and electrolytic plating of copper. In some cases, the conductor may be plated using copper plating techniques. According to some embodiments,FIG. 3Cmay include electroless and electrolytic copper plating to fill the laser vias in the breakout trench pattern. According to some embodiments,FIG. 3Cmay include semi subtractive patterning using a DFR laminated onto dielectric256and then patterned, before the electrolytic plating is applied

FIG. 3Dshows a cross-sectional side view schematic of the circuit board ofFIG. 3Cafter etching or removing portions of the conductor formed on the dielectric layers to form contacts, and forming solder patterns over the board surfaces.FIG. 3Dmay include etching or removing portions of conductor588formed on dielectric layer256to form contacts125in zone124. This etching may be done using known processes for forming contacts having a size and pitch of contacts125. Contacts125may be attached to or electrically connected to interconnects239, interconnects224or contacts228. In some cases, some or all of contacts135are attached to or electrically connected to interconnects or contacts of layers242,232and or222. In some cases, some or all of contacts135are attached to or electrically connected to contacts228of layer222.

FIG. 3Dmay also include etching or removing portions of conductor588formed on dielectric layer256to form contacts135in zone134. This etching may be done using known processes for forming contacts having a size and pitch of contacts135. Contacts135may be attached to or electrically connected to interconnects239, interconnects224or contacts228.

In some cases, removing portions of conductor588includes a process that forms contacts125as a pattern of copper traces or contacts onto the surface of dielectric256, without damaging board120, dielectric256, contacts125or contacts135. Contacts125may have pitch126and be within zone124; and Contacts135may have pitch136and be within zone134.

In some cases, removing portions of conductor588includes copper etching as known in art to form contacts125and135. In some cases, removing portions of conductor588includes removing a top layer of conductor588(e.g, by etching or planarizing) to leave conductor in vias529(e.g., to form contacts125. and539(e.g., to form contacts428). Then, surface272in zone134is patterned and etched according to the second design rule to form contacts135.

FIG. 3Dmay include etching or removing portions of conductor578formed on dielectric layer266to form contacts425on surface274. This etching may be done using known processes for forming contacts having a size and pitch of contacts425. Contacts425may be attached to or electrically connected to interconnects424, interconnects244or contacts248. In some cases, some or all of contacts425are attached to or electrically connected to interconnects or contacts of layers242,232,222and or interconnects424. In some cases, some or all of contacts425are attached to or electrically connected to interconnects424.

Contacts125and135are shown exposed on top surface272of dielectric layer256, prior to forming pattern450. In some cases, some or all of contacts125and135are attached to or electrically connected to interconnects or contacts of layers242,232and or222. After forming contacts125and135, one or more next layers of finer break-out can be built onto surface272, if desired.

In some cases, after forming contacts125and135, the rest of the layer manufacturing process (e.g., forming patterns450and451, an so on) remains the same for board120, as it was without the process ofFIGS. 3B-C. According to some embodiments,FIG. 3Dmay include forming a fine pattern of break-out (e.g., having contacts125) of interconnects onto a surface below the interconnect zone124after curing a dielectric material of the circuit board (e.g., dielectric256).

Contacts425and solder pattern451are also shown formed on a bottom surface of dielectric266. Forming contacts425and solder pattern451may include removing or patterning conductor278. Forming contacts425may include forming interconnects424through dielectric266.

According to some embodiments,FIG. 3Dmay include patterning of the copper (e.g., conductor588and578) on the outer most layer of board120and then solder radius (SR) layer patterning (e.g., pattern450) and BGA side solder resist opening (SRO) formation (e.g., opening449).

According to some embodiments,FIGS. 3A-Dmay describe forming contacts125by laser scribing a pattern of trenches, at locations for the first contacts, into a surface of the circuit board and within the first interconnect zone (e.g.,FIG. 3B); then forming conductive material in the patterned trenches to form the first contacts (e.g.,FIGS. 3C-D). In some cases, the laser scribing includes laser projection and patterning (LPP) ablated traces of a pattern of trenches of the first contacts into a surface of the first interconnect zone (e.g.,FIG. 3B); and forming conductive material includes filling the trenches with copper using electro-less or electrolytic plating of copper (e.g.,FIG. 3C). In some cases, contacts135are formed in the second zone during forming contacts125, such as during etching of the conductive material (e.g., seeFIG. 3C-D).

FIGS. 2E and 3Dshow pattern450and451such solder resists formed on the exterior surface of, and in between contacts on surfaces of dielectrics256and266. Such solder resists may be a solder resist protective coating on the exterior surface of the package. Such solder resists may cause the flux spray to form only where the constraints do not exist, thus directing the spray material onto the contacts to form BGAs on and touching the contacts (e.g., at openings449and569). The function of Solder resist (SR) may also be to prevent any electrical shortage, such as to prevent shortage between contacts on surfaces of dielectrics256and266. Forming patterns450and451may include forming panel constraints, after which paste printing for ball grid array (BGA) attachments is performed, as known in the art.

According to some embodiments, after forming board120as shown inFIG. 2E or 3D, chip123is mounted on zone124and/or electronically attached to contacts125(e.g., seeFIG. 1B). In some cases, chip123is mounted onto surface122in area129and electrically connected to contacts125. According to some embodiments, after forming board120as shown inFIG. 2E or 3D, board120is configured for direct chip attach (DCA) of an integrated circuit chip to contacts125.

According to some embodiments, electronically attaching the chip to contacts125includes routing 600 signal lines through two (contacts125and135) or three interconnect layers of the circuit board. In some cases, the circuit board is for mounting in one of a tablet computer, a smartphone, and a value phone.

According to some embodiments, the pitch for contacts125has a pitch distance (e.g., as noted above, or between midpoints of the contacts125) of between 120 and 160 microns. In some cases, the pitch for contacts125has a pitch distance of between 130 microns and 150 microns.

In either of these cases, according to some embodiments, the pitch for contacts135has a pitch distance (e.g., as noted above, or between midpoints of the contacts135) of between 390 microns and 410 microns. According to some embodiments, the pitch for contacts125is between 30 and 40 percent as large the pitch for contacts135. In some cases, contacts125have a spacing between them of between 1 and 10 microns. In some cases, contacts125have a spacing between them of between 50 and 100 microns.

In some cases, zone124has a square outer perimeter having side lengths (e.g., L2 equal to W2) of between 9 mm and 11 mm. In some cases, zone124has a rectangular outer perimeter having each side length (e.g., L2 not equal to W2) of between 9 mm and 11 mm. In some cases, zone124has a circular or oval outer perimeter having a diameter length (e.g., not shown) of between 9 mm and 11 mm.

In some cases, zone134has a square outer perimeter having side lengths (e.g., L1 equal to W1) of between 14 or 15 mm and 17 or 18 mm (and an inner perimeter equal to any of those described above for zone124). In some cases, zone134has a rectangular outer perimeter having each side length (e.g., L1 not equal to W1) of between 14 or 15 mm and 17 or 18 mm (and an inner perimeter equal to any of those described above for zone124). In some cases, zone134has a circular or oval outer perimeter having a diameter length (e.g., not shown) of 14 and 18 mm (and an inner perimeter equal to any of those described above for zone124). According to some embodiments, zone124has a square outer perimeter side lengths that are between 57 and 67 percent as large as the zone134square outer perimeter side lengths.

In some cases, the inner perimeter of zone134completely surrounds the outer perimeter of zone124on surface122of the circuit board. In some cases, the inner perimeter of area133completely surrounds the outer perimeter of area129on surface122of the circuit board.

Some embodiments described herein provide an approach to enable direct chip attach to motherboard, without using a substrate (e.g., without using a package or packaging). For this neither the motherboard technology does not need to scale entirely nor, the silicon has to accommodate relaxed bump pitch at the financial or performance expenses or both. This can be adopted for smartphones, value phones or, tablet segments of products. Some embodiments described herein provide a cost effective solution for DCA using the existing MB technology with minor additive technology, the cost of which will be significantly lower than the substrate BOM cost.

Also, embodiments described herein allow for the routing of up to 600 signals in two layers (e.g., zones124and134), whereas the current board design will take four layers of motherboard for the same I/O count (with more relaxed DR). In some cases, the embodiments allow for attaching the chip directly to the motherboard without significantly changing the platform or board design. Also this technology can provide better financial affordability than changing the platform or board design.

FIG. 4illustrates a computing device600in accordance with one implementation. The computing device600houses board602. Board602may include a number of components, including but not limited to processor604and at least one communication chip606. Processor604is physically and electrically connected to board602. In some implementations at least one communication chip606is also physically and electrically connected to board602. In further implementations, communication chip606is part of processor604.

Board602may be a circuit board upon which to mount an integrated circuit chip (e.g., processor604) and may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) processor604. The first contacts may be formed as noted inFIG. 2 or 3. Processor604may be a smaller footprint processor chip (e.g., then a processor or CPU for a desktop computer), such as a processor for devices, such as tablet computers, cell phones, smart phones, and value phone devices. In some cases, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip606also includes an integrated circuit die packaged within communication chip606. In accordance with another implementation, a package including a communication chip incorporates one or more fin devices having cladding device layers such as described above. In further implementations, another component housed within computing device600may contain a typical motherboard for a computing device (e.g., not having zone124).

In various implementations, computing device600may be a tablet computer, cell phone, smart phone, or value phone device. In various implementations, computing device600may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device600may be any other electronic device that processes data.

In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the embodiments of the invention but to illustrate it. The scope of the embodiments of invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.

It should also be appreciated that reference throughout this specification to “one embodiment”, “an embodiment”, “one or more embodiments”, or “different embodiments”, for example, means that a particular feature may be included in the practice of the embodiments. Similarly, it should be appreciated that in the description various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an embodiment that requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects of embodiments that may lie in less than all features of a single disclosed embodiment. For example, although the descriptions and figures above describe two pitches of contacts for two zones, the technology can be applied to form three or more zones with different pitches. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.