Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.

FIELD

Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method of manufacturing the same.

BACKGROUND

A NAND-type flash memory is widespread as a storage device for a large volume of data. At present, memory cells are miniaturized for cost reduction and capacity increase per bit. Further miniaturization in the future is demanded. However, further miniaturization of the flash memory involves many problems to be solved, such as the development of lithography technology, a short channel effect, inter-element interference, and the inhibition of inter-element variations. Therefore, there is a strong possibility that future continuous improvement of storage density only by the development of simple in-plane miniaturization technology is difficult.

Accordingly, in order to raise the degree of memory cell integration, there has recently been suggested a three-dimensional stacked layer type semiconductor memory in which memory cells are three-dimensionally arranged.

In the conventional flash memories, drain ends of active areas (semiconductor layers) that are stacked are isolated from each other by an insulating layer, and one drain-side select transistor is provided for the active areas. Drain electrodes (contact plugs) are independently connected to the active areas, respectively.

However, in this structure, the drain electrode is formed for each memory string (active area), and regions to form the drain electrodes are therefore needed. As a result, increasing the number of memory strings to be stacked is not a great contribution to the improvement in the degree of memory cell integration because the regions to form the drain electrodes increase proportionately.

Another problem is that one bit line is connected to one memory string via the drain electrode so that the number of bit lines arranged on a memory cell array increases and their layout is complicated.

In view of such circumstances, there has been suggested a technique to connect drain ends of stacked active areas by a common semiconductor layer and provide drain-side select transistors (layer select transistors) for the active areas (e.g., refer to FIG. 13 in PCT/JP2009/060803).

According to this technique, one common drain electrode (contact plug) has only to be connected to memory strings (active areas). Therefore, the degree of memory cell integration can be improved by increasing the number of memory strings to be stacked.

However, intensive studies by the present inventors have proved that sufficient cut-off characteristics for the drain-side select transistors (layer select transistors) cannot be obtained by the device structure disclosed in the prior application). That is, when a current is passed through one selected memory string, unnecessary currents are also passed through the remaining unselected memory strings. This prevents accurate reading/writing/erasing.

DETAILED DESCRIPTION

In general, according to one embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor substrate; a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of the semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate; first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively; a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction; a drain electrode connected to the common semiconductor layer; a source electrode connected to the first to n-th semiconductor layers at second ends of the first to n-th memory strings in the second direction; and first to n-th layer select transistors arranged in order from the drain electrode to the first to n-th memory strings between the first to n-th memory strings and the drain electrode, wherein the first to n-th layer select transistors comprise first to n-th select gate electrodes extending in the first direction respectively, a drain side edge of an i-th insulating layer (i is one of 2 to n) among the first to (n+1)-th insulating layers is located at the same position as a memory string side edge of an (i−1)-th select gate electrode or located closer to the drain electrode than the memory string side edge of the (i−1)-th select gate electrode, where the drain side edge is a edge which is near the drain electrode, and the memory string side edge is a edge which is near the first to n-th memory strings, and a j-th layer select transistor (j is one of 1 to n) among the first to n-th layer select transistors is normally-on in a j-th semiconductor layer.

1. BASIC CONCEPT

The embodiment is intended for a three-dimensional stacked layer type semiconductor memory comprising first to n-th layer select transistors (n is a natural number equal to or more than 2) at the drain-electrode-side ends of first to n-th semiconductor layers that constitute a fin-type stacked layer structure. According to this structure, one common drain electrode is provided for the first to n-th semiconductor layers, and a high degree of integration can be obtained.

Here, if the j-th layer select transistor (j is one of 1 to n) among the first to n-th layer select transistors is normally-on in a j-th semiconductor layer, the first to n-th semiconductor layers can be selected (layer selection), that is, first to n-th memory strings can be selected.

The embodiment is also intended for a structure in which the drain-electrode-side ends of first to n-th semiconductor layers that constitute a fin-type stacked layer structure are combined to one another by a common semiconductor layer. According to this structure, channels of first to n-th layer select transistors are thicker, and their on-resistance is lower, so that the selection of the first to n-th semiconductor layers can be faster.

This structure is shown, for example, in FIG. 13 of PCT/JP2009/060803 as a prior application.

According to the embodiment, in such a three-dimensional stacked layer type semiconductor memory, the drain-electrode-side edge of an i-th insulating layer (i is one of 2 to n) among first to (n+1)-th insulating layers that constitute a fin-type stacked layer structure is located at the same position as the edge of an (i−1)-th select gate electrode of the (i−1)-th layer select transistor on the side of the first to n-th memory strings or located closer to the side of the drain electrode, in order to improve the cut-off characteristics of the first to n-th layer select transistors.

Thus, the position of the edge of the i-th insulating layer on the side of the drain electrode is adjusted so that when a current is passed through one selected memory string, unnecessary currents do not run through the remaining unselected memory strings, and reading/writing/erasing can be accurately performed.

(1) First Embodiment

FIG. 1shows a structure according to the first embodiment.FIG. 2is a sectional view taken along the line II-II ofFIG. 1.FIG. 3is a sectional view taken along the line ofFIG. 1.

Semiconductor substrate1is, for example, a silicon substrate. Fin-type stacked layer structure9is formed on semiconductor substrate1.

In the present embodiment, fin-type stacked layer structure9is a stack in which first insulating layer2, first semiconductor layer3a, second insulating layer4a, second semiconductor layer3b, third insulating layer4b, third semiconductor layer3c, and fourth insulating layer5are stacked in order in a first direction perpendicular to the surface of semiconductor substrate1. This stack extends in a second direction parallel to the surface of semiconductor substrate1.

However, fin-type stacked layer structure9is not limited thereto, and can be generalized as a stack in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order.

First insulating layer2is made of, for example, silicon oxide (SiO2). First to third semiconductor layers3(3a,3b, and3c) are made of, for example, monocrystalline silicon (Si). First to third semiconductor layers3(3a,3b, and3c) are preferably monocrystalline, but may be amorphous or polycrystalline.

Second and third insulating layers4(4aand4b) are made of, for example, silicon oxide (SiO2). Fourth insulating layer5is made of, for example, silicon oxide (SiO2), silicon nitride (SiNx), or a structure having a stack of these materials.

First to third memory strings (NANDa, NANDb, and NANDc) use first to third semiconductor layers3(3a,3b, and3c) as channels. Here, one memory string uses one semiconductor layer as a channel. Therefore, it is preferable for higher integration to increase the number of semiconductor layers that constitute fin-type stacked layer structure9and increase the number of memory strings.

First to third memory strings (NANDa, NANDb, and NANDc) have stacked layer structures of charge storage layer6(1)band control gate electrode6(1)dextending in the first direction across first to third semiconductor layers3(3a,3b, and3c).

First gate insulating layer6(1)ais formed between first to third semiconductor layers3(3a,3b, and3c) and charge storage layer6(1)b. Second gate insulating layer6(1)cis formed between charge storage layer6(1)band control gate electrode6(1)d.

In this embodiment, first to third memory strings (NANDa, NANDb, and NANDc) have a silicon/oxide/nitride/oxide/silicon (SONOS) type. That is, charge storage layer6(1)bis made of an insulator such as silicon-rich SiN. Second gate insulating layer6(1)cserves to block a leakage current between charge storage layer6(1)band control gate electrode6(1)d, and is therefore called a block insulating layer.

In this embodiment, first to third memory strings (NANDa, NANDb, and NANDc) cover two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in a third direction. That is, first to third memory strings (NANDa, NANDb, and NANDc) have a double gate structure.

Common semiconductor layer14combines first to third semiconductor layers3(3a,3b, and3c) at the ends (ends on the side of drain electrode7) of first to third memory strings (NANDa, NANDb, and NANDc) in a second direction.

Common semiconductor layer14is made of, for example, monocrystalline silicon (Si), and is integrated with first to third semiconductor layers3(3a,3b, and3c). Common semiconductor layer14is preferably monocrystalline as are first to third semiconductor layers3(3a,3b, and3c), but may be amorphous or polycrystalline.

Drain electrode7is connected to common semiconductor layer14, and source electrode8is connected to first to third semiconductor layers3(3a,3b, and3c) at the ends of first to third memory strings (NANDa, NANDb, and NANDc) in the second direction. The bottoms of drain electrode7and source electrode8preferably reach first insulating layer2.

Bit line BL is connected to drain electrode7, and source line SL is connected to source electrode8.

First to third layer select transistors Ta, Tb, and Tc are arranged in order from the side of drain electrode7to first to third memory strings (NANDa, NANDb, and NANDc) between first to third memory strings (NANDa, NANDb, and NANDc) and drain electrode7. The number of layer select transistors is equal to the number of semiconductor layers that constitute fin-type stacked layer structure9.

First to third layer select transistors Ta, Tb, and Tc have first to third select gate electrodes10(10a,10b, and10c) extending in the first direction across first to third semiconductor layers3(3a,3b, and3c).

In this embodiment, first to third select gate electrodes10(10a,10b, and10c) cover two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction. That is, first to third layer select transistors Ta, Tb, and Tc have a double gate structure.

Source-side select transistor Ts is located between first to third memory strings (NANDa, NANDb, and NANDc) and source electrode8.

Source-side select transistor Ts has select gate electrode11extending in the first direction across first to third semiconductor layers3(3a,3b, and3c).

In this embodiment, source-side select gate electrode11covers two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction. That is, source-side select transistor Ts has a double gate structure.

First to third layer select transistors Ta, Tb, and Tc and source-side select transistor Ts are not limited in their structures as long as these transistors function as switch elements.

For example, first to third layer select transistors Ta, Tb, and Tc and source-side select transistor Ts may each have the same structure as that of each of the memory cells that constitute first to third memory strings (NANDa, NANDb, and NANDc), or may have a different structure.

The positions of the edges of second and third insulating layers4(4aand4b) on the side of drain electrode7are described.

The edge of second insulating layer4aon the side of drain electrode7is located at the same position as the edge of first select gate electrode10aon the side of first to third memory strings (NANDa, NANDb, and NANDc) or located closer to the side of drain electrode7.

For example, as shown inFIG. 4, the edge of second insulating layer4aon the side of drain electrode7is located at point a or located closer to the side of drain electrode7.

The edge of third insulating layer4bon the side of drain electrode7is located at the same position as the edge of second select gate electrode10bon the side of first to third memory strings (NANDa, NANDb, and NANDc) or located closer to the side of drain electrode7.

For example, as shown inFIG. 4, the edge of third insulating layer4bon the side of drain electrode7is located at point b or located closer to the side of drain electrode7.

The above is generalized. Fin-type stacked layer structure9is a stack in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order. In this case, the edge of an i-th insulating layer (i is one of 2 to n) among first to (n+1)-th insulating layers on the side of the drain electrode is located at the same position as the edge of an (i−1)-th select gate electrode on the side of the first to n-th memory strings or located closer to the side of the drain electrode.

The edge of the i-th insulating layer on the side of the drain electrode is preferably located closer to the side of the drain electrode than the edge of an (i+1)-th insulating layer on the side of the drain electrode. In this case, the edges of first to (n+1)-th insulating layers on the side of the drain electrode are stepped.

The edge of the (i+1)-th insulating layer among the first to (n+1)-th insulating layers on the side of the drain electrode is preferably located at the same position as the edge of an (i−1)-th select gate electrode on the side of the first to n-th memory strings or located closer to the side of the first to n-th memory strings. This is because, for example, impurity regions13a,13b, and13care formed by one ion implantation, which will be described later in detail in connection with a manufacturing method.

The position of the edge of the uppermost (n+1)-th insulating layer on the side of the drain electrode is not particularly limited. This is because no semiconductor layer (memory string) as an active area is formed on the (n+1)-th insulating layer, that is, fourth insulating layer5inFIG. 1toFIG. 3.

The threshold states of first to third layer select transistors Ta, Tb, and Tc are described.

First layer select transistor Ta which is farthest from first to third memory strings (NANDa, NANDb, and NANDc) is normally-on (uncontrollable) within the range of voltages applied to first select gate electrode10ain lowermost first semiconductor layer3a.

The normally-on state here is obtained by providing impurity region13ain first semiconductor layer3aas a channel of first layer select transistor Ta.

In other second and third semiconductor layers3band3c, the on/off of first layer select transistor Ta is controlled within the range of voltages applied to first select gate electrode10a.

Second layer select transistor Tb is normally-on (uncontrollable) within the range of voltages applied to second select gate electrode10bin interlayer second semiconductor layer3b.

The normally-on state here is obtained by providing impurity region13bin second semiconductor layer3bas a channel of second layer select transistor Tb.

In other first and third semiconductor layers3aand3c, the on/off of second layer select transistor Tb is controlled within the range of voltages applied to second select gate electrode10b.

Third layer select transistor Tc which is closest to first to third memory strings (NANDa, NANDb, and NANDc) is normally-on (uncontrollable) within the range of voltages applied to third select gate electrode10cin uppermost third semiconductor layer3c.

The normally-on state here is obtained by providing impurity region13cin third semiconductor layer3cas a channel of third layer select transistor Tc.

In other first and second semiconductor layers3aand3b, the on/off of third layer select transistor Tc is controlled within the range of voltages applied to third select gate electrode10c.

The above is generalized. Fin-type stacked layer structure9is a stack in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order. In this case, a j-th layer select transistor (j is one of 1 to n) among first to n-th layer select transistors is normally-on in a j-th semiconductor layer.

According to such a structure, for example, first layer select transistor Ta is switched off in second and third memory strings NANDb and NANDc, all of first to third layer select transistors Ta, Tb, and Tc are switched on in first memory string NANDa, and a current is passed through first memory string NANDa. In this case, a leak path from first memory string NANDa to second and third memory strings NANDb and NANDc is cut off by second insulating layer4a.

Similarly, for example, second layer select transistor Tb is switched off in first and third memory strings NANDa and NANDc, all of first to third layer select transistors Ta, Tb, and Tc are switched on in second memory string NANDb, and a current is passed through second memory string NANDb. In this case, a leak path from second memory string NANDb to third memory string NANDc is cut off by third insulating layer4b.

In this way, unnecessary currents do not run through the unselected memory strings, and cut-off characteristics can be improved.

B. Material Examples

Materials best suited to the generations of the semiconductor memories can be properly selected as the materials that constitute the elements of the device structure shown inFIG. 1toFIG. 3.

For example, first gate insulating layer6(1)acan be SiO2, charge storage layer6(1)bcan be Si3N4, second gate insulating layer6(1)ccan be Al2O3, and control gate electrode6(1)dcan be NiSi.

First gate insulating layer6(1)amay be silicon oxynitride, or a stacked layer structure of silicon oxide and silicon nitride. First gate insulating layer6(1)amay include silicon nanoparticles, metal ions, or the like.

Charge storage layer6(1)bmay be made of at least one of the materials selected from the group consisting of SixNyhaving any composition ratio x, y of silicon and nitrogen, silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum oxynitride (AlON), hafnia (HfO2), hafnium aluminate (HfAlO3), hafnia nitride (HfON), hafnium nitride-aluminate (HfAlON), hafnium silicate (HfSiO), hafnium nitride-silicate (HfSiON), lanthanum oxide (La2O3), and lanthanum aluminate (LaAlO3).

Charge storage layer6(1)bmay otherwise be made of impurity-added polysilicon or a conductor such as a metal.

As an impurity that constitutes impurity regions13a,13b, and13c, it is possible to use an impurity serving as an N-type semiconductor, for example, a pentad such as arsenic (As) or phosphorus (P), an impurity serving as a P-type semiconductor, for example, a triad such as boron (B) or indium (In), and a combination of these substances.

C. First Application

FIG. 5shows a first application of the first embodiment.

Here, the same elements as those in the first embodiment (FIG. 1toFIG. 3) are provided with the same reference marks and are thus not described in detail.

The first application is characterized in that diffusion layer17surrounding drain electrode7is formed in common semiconductor layer14.

Diffusion layer17can be made of an impurity serving as an n-type semiconductor, an impurity serving as a p-type semiconductor, or a combination of these substances, similarly to impurity regions13a,13b, and13c.

Diffusion layer17serves to reduce contact resistance between common semiconductor layer14and drain electrode7.

D. Second Application

FIG. 6shows a second application of the first embodiment.

Here, the same elements as those in the first embodiment (FIG. 1toFIG. 3) are provided with the same reference marks and are thus not described in detail.

The second application is characterized in that first to third select gate electrodes10a,10b, and10ccover one of two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction.

That is, first to third layer select transistors Ta, Tb, and Tc have a single gate structure.

In the present application, insulating layer19is located between two fin-type stacked layer structures9aand9b, and isolate the fin-type stacked layer structures9aand9b.

Insulating layer19can be replaced by an electrode.

In this case, a bias can be applied to the electrode during writing/erasing to improve writing/erasing characteristics.

E. Third Application

FIG. 7shows a third application of the first embodiment.

Here, the same elements as those in the first embodiment (FIG. 1toFIG. 3) are provided with the same reference marks and are thus not described in detail.

The third application is characterized in that fin-type stacked layer structures9a,9b, and9care arranged in the third direction to constitute a memory cell array. Each fin-type stacked layer structure has the same structure as fin-type stacked layer structure9disclosed inFIG. 1toFIG. 3.

Gate stacked layer structures6(1),6(2), . . .6(n) including control gate electrodes extend in the third direction across fin-type stacked layer structures9a,9b, and9c. Similarly, gate stacked layer structures10a,10b, and10cincluding select gate electrodes extend in the third direction across fin-type stacked layer structures9a,9b, and9c.

Such an array structure enables a three-dimensional stacked layer type semiconductor memory having a high memory capacity.

The operations of the three-dimensional stacked layer type semiconductor memories according to the first embodiment (FIG. 1toFIG. 3) and the first to third applications (FIG. 5toFIG. 7) are described.Write operation is as follows.

First, in writing in memory string NANDa that uses first semiconductor layer3aas a channel, a ground potential is applied to drain electrode7and source electrode8, and a first positive bias is applied to select gate electrodes10band10cand control gate electrodes6(1)d, . . .6(n)d. No bias is applied to select gate electrodes10aand11.

At the same time, for example, n-type impurity storage regions are formed in first to third semiconductor layers3(3a,3b, and3c) serving as channels of first to third layer select transistors Ta, Tb, and Tc and first to third memory strings NANDa, NANDb, and NANDc.

As no bias is applied to select gate electrode10a, first layer select transistor Ta is off in second and third semiconductor layers3band3c, and is on in first semiconductor layer3aowing to impurity region13a. Moreover, as no bias is applied to select gate electrode11, source-side select transistor Ts is off in first to third semiconductor layers3(3a,3b, and3c).

Subsequently, for example, a second positive bias higher than the first positive bias is applied to the control gate electrode of the selected memory cell targeted for writing, and program data “0”/“1” is transferred to drain electrode7from bit line BL.

In second and third semiconductor layers3band3cin which unselected memory strings NANDb and NANDc are formed, the channel potential is increased by capacitive coupling resulting from the application of the second positive bias. Therefore, a sufficiently high voltage is not applied across the control gate electrode (or charge storage layer) and the channel, and writing is inhibited accordingly.

In first semiconductor layer3ain which selected memory string NANDa is formed, first layer select transistor Ta is on. Thus, program data “0”/“1” is transferred to first semiconductor layer3aas a channel.

When the program data is “0”, first semiconductor layer3aas the channel, for example, has a positive potential. In this condition, if the second positive bias is applied to the control gate electrode of the selected memory cell and the channel potential is slightly increased by the capacitive coupling, first layer select transistor Ta is cut off.

Therefore, in first semiconductor layer3a, the channel potential is increased by the capacitive coupling resulting from the application of the second positive bias. That is, a sufficiently high voltage is not applied across the control gate electrode (or charge storage layer) and the channel, and electrons are not injected into the charge storage layer. Therefore, writing is inhibited (“0”-programming).

In contrast, when the program data is “1”, first semiconductor layer3aas the channel, for example, has a ground potential. In this condition, even if the second positive bias is applied to the control gate electrode of the selected memory cell, first layer select transistor Ta is not cut off.

Therefore, the ground potential is applied to first semiconductor layer3aas the channel, and the second positive bias is applied to the control gate electrode. That is, a sufficiently high voltage is generated across the control gate electrode (or charge storage layer) and the channel, and electrons are injected into the charge storage layer. Therefore, writing is performed (“1”-programming).

Next, in writing in memory string NANDb that uses second semiconductor layer3bas a channel, a ground potential is applied to drain electrode7and source electrode8, and a first positive bias is applied to select gate electrodes10aand10cand control gate electrodes6(1)d, . . .6(n)d. No bias is applied to select gate electrodes10band11.

At the same time, for example, n-type impurity storage regions are formed in first to third semiconductor layers3(3a,3b, and3c) serving as channels of first to third layer select transistors Ta, Tb, and Tc and first to third memory strings NANDa, NANDb, and NANDc.

As no bias is applied to select gate electrode10b, second layer select transistor Tb is off in first and third semiconductor layers3aand3c, and is on in second semiconductor layer3bowing to impurity region13b. Moreover, as no bias is applied to select gate electrode11, source-side select transistor Ts is off in first to third semiconductor layers3(3a,3b, and3c).

Subsequently, for example, a second positive bias higher than the first positive bias is applied to the control gate electrode of the selected memory cell targeted for writing, and program data “0”/“1” is transferred to drain electrode7from bit line BL.

In first and third semiconductor layers3aand3cin which unselected memory strings NANDa and NANDc are formed, the channel potential is increased by capacitive coupling resulting from the application of the second positive bias. Therefore, a sufficiently high voltage is not applied across the control gate electrode (or charge storage layer) and the channel, and writing is inhibited accordingly.

In second semiconductor layer3bin which selected memory string NANDb is formed, second layer select transistor Tb is on. Thus, program data “0”/“1” is transferred to second semiconductor layer3bas a channel.

When the program data is “0”, second semiconductor layer3bas the channel, for example, has a positive potential. In this condition, if the second positive bias is applied to the control gate electrode of the selected memory cell and the channel potential is slightly increased by the capacitive coupling, second layer select transistor Tb is cut off.

Therefore, in second semiconductor layer3b, the channel potential is increased by the capacitive coupling resulting from the application of the second positive bias. That is, a sufficiently high voltage is not applied across the control gate electrode (or charge storage layer) and the channel, and electrons are not injected into the charge storage layer. Therefore, writing is inhibited (“0”-programming).

In contrast, when the program data is “1”, second semiconductor layer3bas the channel, for example, has a ground potential. In this condition, even if the second positive bias is applied to the control gate electrode of the selected memory cell, second layer select transistor Tb remains on.

Therefore, the ground potential is applied to second semiconductor layer3bas the channel, and the second positive bias is applied to the control gate electrode. That is, a sufficiently high voltage is generated across the control gate electrode (or charge storage layer) and the channel, and electrons are injected into the charge storage layer. Therefore, writing is performed (“1”-programming).

Finally, in writing in memory string NANDc that uses third semiconductor layer3cas a channel, a ground potential is applied to drain electrode7and source electrode8, and a first positive bias is applied to select gate electrodes10aand10band control gate electrodes6(1)d, . . .6(n)d. No bias is applied to select gate electrodes10cand11.

At the same time, for example, n-type impurity storage regions are formed in first to third semiconductor layers3(3a,3b, and3c) serving as channels of first to third layer select transistors Ta, Tb, and Tc and first to third memory strings NANDa, NANDb, and NANDc.

As no bias is applied to select gate electrode10c, third layer select transistor Tc is off in first and second semiconductor layers3aand3b, and is on in third semiconductor layer3cowing to impurity region13c. Moreover, as no bias is applied to select gate electrode11, source-side select transistor Ts is off in first to third semiconductor layers3(3a,3b, and3c).

Subsequently, for example, a second positive bias higher than the first positive bias is applied to the control gate electrode of the selected memory cell targeted for writing, and program data “0”/“1” is transferred to drain electrode7from bit line BL.

In first and second semiconductor layers3aand3bin which unselected memory strings NANDa and NANDb are formed, the channel potential is increased by capacitive coupling resulting from the application of the third positive bias. Therefore, a sufficiently high voltage is not applied across the control gate electrode (or charge storage layer) and the channel, and writing is inhibited accordingly.

In third semiconductor layer3cin which selected memory string NANDc is formed, third layer select transistor Tc is on. Thus, program data “0”/“1” is transferred to third semiconductor layer3cas a channel.

When the program data is “0”, third semiconductor layer3cas the channel, for example, has a positive potential. In this condition, if the second positive bias is applied to the control gate electrode of the selected memory cell and the channel potential is slightly increased by the capacitive coupling, third layer select transistor Tc is cut off.

Therefore, in third semiconductor layer3c, the channel potential is increased by the capacitive coupling resulting from the application of the second positive bias. That is, a sufficiently high voltage is not applied across the control gate electrode (or charge storage layer) and the channel, and electrons are not injected into the charge storage layer. Therefore, writing is inhibited (“0”-programming).

In contrast, when the program data is “1”, third semiconductor layer3cas the channel, for example, has a ground potential. In this condition, even if the second positive bias is applied to the control gate electrode of the selected memory cell, third layer select transistor Tc remains on.

Therefore, the ground potential is applied to third semiconductor layer3cas the channel, and the second positive bias is applied to the control gate electrode. That is, a sufficiently high voltage is generated across the control gate electrode (or charge storage layer) and the channel, and electrons are injected into the charge storage layer. Therefore, writing is performed (“1”-programming).Erase operation is as follows.

First Example

Erase operation is collectively performed in, for example, first to third memory strings NANDa, NANDb, and NANDc in the fin type stacked layer structures (block erasing1).

First, a ground potential is applied to drain electrode7and source electrode8, and a first negative bias is applied to select gate electrodes10a,10b,10c, and11and control gate electrodes6(1)d, . . .6(n)d.

At the same time, for example, p-type impurity storage regions are formed in first to third semiconductor layers3(3a,3b, and3c) serving as channels of first to third layer select transistors Ta, Tb, and Tc and first to third memory strings NANDa, NANDb, and NANDc.

Furthermore, a second positive bias higher than the first positive bias is applied to control gate electrodes6(1)d, . . .6(n)d.

As a result, a sufficiently high voltage is generated across the control gate electrode (or charge storage layer) and the channel, and electrons in the charge storage layer are discharged to the channel.

Second Example

The erase operation can also be performed in, for example, one of first to third memory strings NANDa, NANDb, and NANDc in the fin type stacked layer structures (block erasing2).

For example, in order to erase first memory string NANDa, no bias is applied to select gate electrodes10aand11, as in writing. As a result, first layer select transistor Ta is off in second and third semiconductor layers3band3c. Thus, first memory string NANDa can be selectively erased.

In order to erase second memory string NANDb, no bias is applied to select gate electrodes10band11, as in writing. As a result, second layer select transistor Tb is off in first and third semiconductor layers3aand3c. Thus, second memory string NANDb can be selectively erased.

In order to erase third memory string NANDc, no bias is applied to select gate electrodes10cand11, as in writing. As a result, third layer select transistor Tc is off in first and second semiconductor layers3aand3b. Thus, third memory string NANDc can be selectively erased.

Third Example

The erase operation can be performed in, for example, the memory cell in one of memory cells in first to third memory strings NANDa, NANDb, and NANDc in the fin type stacked layer structures (page erasing/one cell erasing).

In this case, the following conditions are further added to the conditions in the above-mentioned first or second examples.

A second negative bias higher than the first negative bias is applied to the control gate electrode of the selected memory cell targeted for erasing. No second negative bias is applied to the control gate electrodes of the unselected memory cells which are not targeted for erasing.

As a result, a sufficiently high voltage is generated across the control gate electrode (or charge storage layer) and the channel in the selected memory cell alone, and electrons in the charge storage layer are discharged to the channel. Thus, erasing is performed.Read operation is as follows.

First, in order to read memory string NANDa that uses first semiconductor layer3aas a channel, drain electrode7is connected to a reading circuit, and a ground voltage is applied to source electrode8. A first positive bias is applied to select gate electrodes10b,10c, and11and control gate electrodes6(1)d, . . .6(n)d.

The first positive bias has, for example, a value that switches on the memory cell regardless of whether data is “0” or “1”. No bias is applied to select gate electrode10a.

At the same time, as no bias is applied to select gate electrode10a, first layer select transistor Ta is off in second and third semiconductor layers3band3c, and is on in first semiconductor layer3a.

Data is then sequentially read in memory string NANDa from the source-side memory cells to the drain-side memory cells.

In the selected memory cell targeted for reading, for example, a second positive bias for reading that is lower than the first positive bias is applied to the control gate electrode. The second positive bias has, for example, a value between the threshold of the data “0” and the threshold of the data “1”.

Therefore, whether to switch on or off the selected memory cell is determined by the value of the data stored in the selected memory cell, so that reading can be performed by using the reading circuit to detect potential changes in bit line BL and changes in currents running through bit line.

Next, in order to read memory string NANDb that uses second semiconductor layer3bas a channel, drain electrode7is connected to the reading circuit, and a ground voltage is applied to source electrode8. A first positive bias is applied to select gate electrodes10a,10c, and11and control gate electrodes6(1)d, . . .6(n)d.

The first positive bias has, for example, a value that switches on the memory cell regardless of whether data is “0” or “1”. No bias is applied to select gate electrode10b.

At the same time, as no bias is applied to select gate electrode10b, second layer select transistor Tb is off in first and third semiconductor layers3aand3c, and is on in second semiconductor layer3b.

Data is then sequentially read in memory string NANDb from the source-side memory cells to the drain-side memory cells.

In the selected memory cell targeted for reading, for example, a second positive bias for reading that is lower than the first positive bias is applied to the control gate electrode. The second positive bias has, for example, a value between the threshold of the data “0” and the threshold of the data “1”.

Therefore, whether to switch on or off the selected memory cell is determined by the value of the data stored in the selected memory cell, so that reading can be performed by using the reading circuit to detect potential changes in bit line BL and changes in currents running through bit line.

Finally, in order to read memory string NANDc that uses third semiconductor layer3cas a channel, drain electrode7is connected to the reading circuit, and a ground voltage is applied to source electrode8. A first positive bias is applied to select gate electrodes10a,10b, and11and control gate electrodes6(1)d, . . .6(n)d.

The first positive bias has, for example, a value that switches on the memory cell regardless of whether data is “0” or “1”. No bias is applied to select gate electrode10c.

At the same time, as no bias is applied to select gate electrode10c, third layer select transistor Tc is off in first and second semiconductor layers3aand3b, and is on in third semiconductor layer3c.

Data is then sequentially read in memory string NANDc from the source-side memory cells to the drain-side memory cells.

In the selected memory cell targeted for reading, for example, a second positive bias for reading that is lower than the first positive bias is applied to the control gate electrode. The second positive bias has, for example, a value between the threshold of the data “0” and the threshold of the data “1”.

Therefore, whether to switch on or off the selected memory cell is determined by the value of the data stored in the selected memory cell, so that reading can be performed by using the reading circuit to detect potential changes in bit line BL and changes in currents running through bit line.

G. First Example of Method of Manufacturing Structure in FIG.1

FIG. 8AtoFIG. 8Fshow a method of manufacturing the structure inFIG. 1.

First, as shown inFIG. 8A, first-conductivity-type (e.g., p-type) semiconductor substrate (e.g., silicon)1having, for example, a plane direction (100) and a specific resistance of 10 to 20 Ωcm is prepared. On this semiconductor substrate1, first insulating layer (e.g., silicon oxide)2is formed. First semiconductor layer (e.g., silicon)3ais then formed on first insulating layer2.

A resist pattern is then formed on first semiconductor layer3aby a photo etching process (PEP). This resist pattern is used as a mask to implant ions, and impurity-added region13ais formed in first semiconductor layer3a. The resist pattern is removed afterwards.

As shown inFIG. 8B, second insulating layer (e.g., silicon oxide)4ais then formed on first semiconductor layer3a. Moreover, a resist pattern is formed on second insulating layer4aby the PEP. This resist pattern is used as a mask for reactive ion etching (RIE) to pattern second insulating layer4a.

As a result, the position of the edge of second insulating layer4ain the second direction is determined. The position of the edge of second insulating layer4ain the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Second semiconductor layer (e.g., silicon)3bis then formed on first semiconductor layer3aand second insulating layer4a. Second semiconductor layer3bis combined at one end in the second direction to first semiconductor layer3a.

A resist pattern is formed on second semiconductor layer3bby the PEP. This resist pattern is used as a mask to implant ions, and impurity-added region13bis formed in second semiconductor layer3b. The resist pattern is removed afterwards.

As shown inFIG. 8C, third insulating layer (e.g., silicon oxide)4bis then formed on second semiconductor layer3b. Moreover, a resist pattern is formed on third insulating layer4bby the PEP. This resist pattern is used as a mask for RIE to pattern third insulating layer4b.

As a result, the position of the edge of third insulating layer4bin the second direction is determined. The position of the edge of third insulating layer4bin the second direction complies with the conditions described in the paragraphs for the structure.

The resist pattern is removed afterwards.

Third semiconductor layer (e.g., silicon)3cis then formed on second semiconductor layer3band third insulating layer4b. Third semiconductor layer3cis combined at one end in the second direction to second semiconductor layer3b.

A resist pattern is formed on third semiconductor layer3cby the PEP. This resist pattern is used as a mask to implant ions, and impurity-added region13cis formed in third semiconductor layer3c. The resist pattern is removed afterwards.

As shown inFIG. 8D, fourth insulating layer (e.g., silicon oxide)5is then formed on third semiconductor layer3c. Moreover, a resist pattern is formed on fourth insulating layer5by the PEP. This resist pattern is used as a mask for RIE to pattern fourth insulating layer5. As a result, the position of the edge of fourth insulating layer5in the second direction is determined.

However, the position of the edge of uppermost fourth insulating layer5in the second direction is not particularly limited as has been described in the paragraphs for the structure.

The resist pattern is removed afterwards.

Fourth semiconductor layer (e.g., silicon)3dis then formed on third semiconductor layer3c. Fourth semiconductor layer3dis combined at one end in the second direction to third semiconductor layer3c. However, fourth semiconductor layer3dmay be omitted.

As shown inFIG. 8E, a resist pattern is formed on fourth insulating layer5and common semiconductor layer14by the PEP. This resist pattern is used as a mask for RIE to sequentially pattern fourth insulating layer5, third semiconductor layer3c, third insulating layer4b, second semiconductor layer3b, second insulating layer4a, first semiconductor layer3a, first insulating layer2, and common semiconductor layer14. As a result, fin-type stacked layer structure9is formed.

Here, common semiconductor layer14means a structure at the ends of first to fourth semiconductor layers3(3a,3b,3c, and3d) in the second direction.

The resist pattern is removed afterwards.

As shown inFIG. 8F, gate stacked layer structures6(1),6(2), . . .6(n) and select gate electrodes10(10a,10b, and10c) extending in the third direction across fin-type stacked layer structure9are formed by a method such as CVD or sputtering and by an anisotropic etching method such as the RIE.

Here, gate stacked layer structures6(1),6(2), . . .6(n) extend in the first direction, for example, in two side surfaces of first to fourth semiconductor layers3(3a,3b,3c, and3d) that face in the third direction. Select gate electrodes10(10a,10b, and10c) also extend in the first direction, for example, in two side surfaces of first to fourth semiconductor layers3(3a,3b,3c, and3d) that face in the third direction.

The structure shown inFIG. 1is completed by the steps described above.

H. Second Example of Method of Manufacturing Structure in FIG.1

FIG. 9AtoFIG. 9Cshow a method of manufacturing the structure inFIG. 1.

First, as shown inFIG. 9A, first-conductivity-type (e.g., p-type) semiconductor substrate (e.g., silicon)1having, for example, a plane direction (100) and a specific resistance of 10 to 20 Ωcm is prepared. On this semiconductor substrate1, first insulating layer (e.g., silicon oxide)2is formed. First semiconductor layer (e.g., silicon)3ais then formed on first insulating layer2.

Second insulating layer (e.g., silicon oxide)4ais then formed on first semiconductor layer3a. Moreover, a resist pattern is formed on second insulating layer4aby the PEP. This resist pattern is used as a mask for RIE to pattern second insulating layer4a.

As a result, the position of the edge of second insulating layer4ain the second direction is determined. The position of the edge of second insulating layer4ain the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Second semiconductor layer (e.g., silicon)3bis then formed on first semiconductor layer3aand second insulating layer4a. Second semiconductor layer3bis combined at one end in the second direction to first semiconductor layer3a.

Third insulating layer (e.g., silicon oxide)4bis then formed on second semiconductor layer3b. A resist pattern is formed on third insulating layer4bby the PEP. This resist pattern is used as a mask for RIE to pattern third insulating layer4b.

As a result, the position of the edge of third insulating layer4bin the second direction is determined. The position of the edge of third insulating layer4bin the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Third semiconductor, layer (e.g., silicon)3cis then formed on second semiconductor layer3band third insulating layer4b. Third semiconductor layer3cis combined at one end in the second direction to second semiconductor layer3b.

Fourth insulating layer (e.g., silicon oxide)5is then formed on third semiconductor layer3c. A resist pattern is formed on fourth insulating layer5by the PEP. This resist pattern is used as a mask for RIE to pattern fourth insulating layer5.

As a result, the position of the edge of fourth insulating layer5in the second direction is determined. The position of the edge of uppermost fourth insulating layer5in the second direction is not particularly limited as has been described in the paragraphs for the structure.

The resist pattern is removed afterwards.

Fourth semiconductor layer (e.g., silicon)3dis then formed on third semiconductor layer3c. Fourth semiconductor layer3dis combined at one end in the second direction to third semiconductor layer3c.

As shown inFIG. 9B, a resist pattern is then formed on fourth insulating layer5and fourth semiconductor layer3dby the PEP. This resist pattern is used as a mask to implant ions, and impurity-added region13ais formed in first semiconductor layer3a. In this ion implantation, the acceleration energy and dose amount for the ion implantation are set to form impurity-added region13ain first semiconductor layer3a.

The resist pattern is removed afterwards.

As shown inFIG. 9C, a resist pattern is then again formed on fourth insulating layer5and fourth semiconductor layer3dby the PEP. This resist pattern is used as a mask to implant ions, and impurity-added region13bis formed in second semiconductor layer3b. In this ion implantation, the acceleration energy and dose amount for the ion implantation are set to form impurity-added region13bin second semiconductor layer3b.

The resist pattern is removed afterwards.

A resist pattern is then again formed on fourth insulating layer5and fourth semiconductor layer3dby the PEP. This resist pattern is used as a mask to implant ions, and impurity-added region13cis formed in third semiconductor layer3c. In this ion implantation, the acceleration energy and dose amount for the ion implantation are set to form impurity-added region13cin third semiconductor layer3c.

The resist pattern is removed afterwards.

The same structure as that shown inFIG. 8Din the first example of the manufacturing method is obtained by the steps described above. Therefore, this is followed by the same steps as those inFIG. 8EandFIG. 8Fin the first example to complete the structure shown inFIG. 1.

In the second example of the manufacturing method, the resist does not adhere to first to third semiconductor layers3(3a,3b, and3c) as the active areas where the memory strings are formed. This prevents the contamination of first to third semiconductor layers3(3a,3b, and3c), and improves the channel characteristics of the memory strings.

I. Third Example of Method of Manufacturing Structure in FIG.1

FIG. 10AtoFIG. 10Eshow a method of manufacturing the structure inFIG. 1.

First, as shown inFIG. 10A, first-conductivity-type (e.g., p-type) semiconductor substrate (e.g., silicon)1having, for example, a plane direction (100) and a specific resistance of 10 to 20 Ωcm is prepared. On this semiconductor substrate1, first insulating layer (e.g., silicon oxide)2is formed. First semiconductor layer (e.g., silicon)3aand second insulating layer (e.g., silicon oxide)4aare then sequentially formed on first insulating layer2.

A resist pattern is formed on second insulating layer4aby the PEP. This resist pattern is used as a mask for RIE to pattern second insulating layer4aand first semiconductor layer3a.

As a result, the position of the edge of second insulating layer4ain the second direction is determined. The position of the edge of second insulating layer4ain the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Second semiconductor layer (e.g., silicon)3band third insulating layer (e.g., silicon oxide)4bare then sequentially formed on second insulating layer4a.

A resist pattern is formed on third insulating layer4bby the PEP. This resist pattern is used as a mask for RIE to pattern third insulating layer4band second semiconductor layer3b.

As a result, the position of the edge of third insulating layer4bin the second direction is determined. The position of the edge of third insulating layer4bin the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Third semiconductor layer (e.g., silicon)3cand fourth insulating layer (e.g., silicon oxide)5are then sequentially formed on third insulating layer4b.

A resist pattern is formed on fourth insulating layer5by the PEP. This resist pattern is used as a mask for RIE to pattern fourth insulating layer5and third semiconductor layer3c.

As a result, the position of the edge of fourth insulating layer5in the second direction is determined. The position of the edge of uppermost fourth insulating layer5in the second direction is not particularly limited as has been described in the paragraphs for the structure.

The resist pattern is removed afterwards.

Here, in the present example, second to fourth insulating layers4a,4b, and5are preferably equal in thickness in the first direction if later-described ion implantation (collective implantation) is taken into consideration.

As shown inFIG. 10B, resist pattern15is then formed on fourth insulating layer5by the PEP. This resist pattern15is used as a mask to implant ions.

In this ion implantation, the acceleration energy and dose amount are controlled to simultaneously form impurity regions13a,13b, and13cin first to third semiconductor layers3(3a,3b, and3c) (collective implantation).

As second to fourth insulating layers4a,4b, and5function as masks, each of impurity regions13a,13b, and13cis only formed at one end of each of first to third semiconductor layers3(3a,3b, and3c) in a self-aligning manner.

The resist pattern15is removed afterwards.

As shown inFIG. 10C, common semiconductor layer (e.g., silicon)14is then formed, and the surface of common semiconductor layer14is planarized by chemical mechanical polishing (CMP). This planarization can also be conducted, for example, by dry etching.

Common semiconductor layer14combines first to third semiconductor layers3(3a,3b, and3c) at one end in the second direction.

As shown inFIG. 10D, a resist pattern is then formed on fourth insulating layer5and common semiconductor layer14by the PEP. This resist pattern is used as a mask for RIE to sequentially pattern fourth insulating layer5, third semiconductor layer3c, third insulating layer4b, second semiconductor layer3b, second insulating layer4a, first semiconductor layer3a, first insulating layer2, and common semiconductor layer14. As a result, fin-type stacked layer structure9is formed.

The resist pattern is removed afterwards.

As shown inFIG. 10E, gate stacked layer structures6(1),6(2), . . .6(n) and select gate electrodes10(10a,10b, and10c) extending in the third direction across fin-type stacked layer structure9are formed by a method such as the CVD or sputtering and by an anisotropic etching method such as the RIE.

Here, gate stacked layer structures6(1),6(2), . . .6(n) extend in the first direction, for example, in two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction. Select gate electrodes10(10a,10b, and10c) also extend in the first direction, for example, in two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction.

The structure shown inFIG. 1is completed by the steps described above.

According to the first embodiment, the positions of the edges of the second and third insulating layers on the side of the drain electrode are adjusted so that when a current is passed through one selected memory string, unnecessary currents do not run through the remaining unselected memory strings, and reading/writing/erasing can be accurately performed.

(2) Second Embodiment

FIG. 11shows a structure according to the second embodiment.FIG. 12is a sectional view taken along the line XII-XII ofFIG. 11.FIG. 13is a sectional view taken along the line XIII-XIII ofFIG. 11.

Here, the same elements as those in the first embodiment (FIG. 1toFIG. 3) are provided with the same reference marks and are thus not described in detail.

The second embodiment is characterized in that a third memory string (dummy) that uses, as a channel, uppermost third semiconductor layer3camong first to third semiconductor layers3a,3b, and3cconstituting fin-type stacked layer structure9comprises dummy cells as non-memory cells.

The uppermost layer is the dummy layer, for example, because impurity region13cis formed entirely in uppermost third semiconductor layer3cif the structure shown inFIG. 11toFIG. 13is formed by a later-described manufacturing method.

In the present embodiment, as uppermost third semiconductor layer3cis the dummy layer, third layer select transistor Tc located closest to first and second memory strings NANDa and NANDb is not indispensable. That is, third layer select transistor Tc can be omitted.

The configuration is the same as that according to the first embodiment in other respects.

Particularly, the positions of the edges of second and third insulating layers4(4aand4b) in the second direction are the same as those according to the first embodiment. Although third semiconductor layer3cis dummy, a leak path from first or second semiconductor layer3aor3bto third semiconductor layer3ccan be cut off by adjusting the position of the edge of third insulating layer4bas in the first embodiment.

B. Material Examples

In the second embodiment (FIG. 11toFIG. 13), the materials described in Material Examples in the first embodiment can be used to manufacture a three-dimensional stacked layer type semiconductor memory.

The second embodiment (FIG. 11toFIG. 13) can also be applied as in the first to third applications (FIG. 5toFIG. 7) in the first embodiment.

Not Omitting Third Layer Select Transistor Tc

In this case, writing/erasing/reading can be performed by the same operations as those described in the first embodiment.

However, the third memory string (dummy) that uses uppermost third semiconductor layer3cas a channel is dummy, and is therefore not selected.

That is, during writing/erasing/reading, a bias is applied to select gate electrode10c, and no bias is applied to one of select gate electrodes10aand10b.

Therefore, no current runs through third semiconductor layer3c.

Omitting Third Layer Select Transistor Tc

In this case, writing/erasing/reading can be performed by the same operations as those described in the first embodiment.

However, as third layer select transistor Tc is not present, parts of the operation described in the first embodiment that are associated with select gate electrode10care omitted.

G. Method of Manufacturing Structure in FIG.11

FIG. 14AtoFIG. 14Eshow a method of manufacturing the structure inFIG. 11.

First, as shown inFIG. 14A, first-conductivity-type (e.g., p-type) semiconductor substrate (e.g., silicon)1having, for example, a plane direction (100) and a specific resistance of 10 to 20 Ωcm is prepared. On this semiconductor substrate1, first insulating layer (e.g., silicon oxide)2is formed. First semiconductor layer (e.g., silicon)3aand second insulating layer (e.g., silicon oxide)4aare then sequentially formed on first insulating layer2.

A resist pattern is formed on second insulating layer4aby the PEP. This resist pattern is used as a mask for RIE to pattern second insulating layer4aand first semiconductor layer3a.

As a result, the position of the edge of second insulating layer4ain the second direction is determined. The position of the edge of second insulating layer4ain the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Second semiconductor layer (e.g., silicon)3band third insulating layer (e.g., silicon oxide)4bare then sequentially formed on second insulating layer4a.

A resist pattern is formed on third insulating layer4bby the PEP. This resist pattern is used as a mask for RIE to pattern third insulating layer4band second semiconductor layer3b.

As a result, the position of the edge of third insulating layer4bin the second direction is determined. The position of the edge of third insulating layer4bin the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Third semiconductor layer (e.g., silicon)3cand fourth insulating layer (e.g., silicon oxide)5are then sequentially formed on third insulating layer4b.

A resist pattern is formed on fourth insulating layer5by the PEP. This resist pattern is used as a mask for RIE to pattern fourth insulating layer5and third semiconductor layer3c.

As a result, the position of the edge of fourth insulating layer5in the second direction is determined. The position of the edge of uppermost fourth insulating layer5in the second direction is not particularly limited as has been described in the paragraphs for the structure.

The resist pattern is removed afterwards.

Here, in the present example, second and third insulating layers4aand4bare preferably equal in thickness in the first direction if later-described ion implantation (collective implantation) is taken into consideration.

The thickness of fourth insulating layer5in the first direction may be equal to the thickness of each of second and third insulating layers4aand4bin the first direction, or may be greater than the thickness of each of second and third insulating layers4aand4bin the first direction.

As shown inFIG. 14B, ions are implanted. In this ion implantation, the acceleration energy and dose amount are controlled to simultaneously form impurity regions13a,13b, and13cin first to third semiconductor layers3(3a,3b, and3c) (collective implantation).

Impurity region13cis formed substantially entirely in uppermost third semiconductor layer3c. In contrast, each of impurity regions13aand13bis only formed at one end of each of first and second semiconductor layers3aand3bin the second direction in a self-aligning manner. This is because second to fourth insulating layers4band5function as masks.

As shown inFIG. 14C, common semiconductor layer (e.g., silicon)14is then formed, and the surface of common semiconductor layer14is planarized by the CMP. This planarization can also be conducted, for example, by dry etching.

Common semiconductor layer14combines first to third semiconductor layers3(3a,3b, and3c) at one end in the second direction.

As shown inFIG. 14D, a resist pattern is then formed on fourth insulating layer5and common semiconductor layer14by the PEP. This resist pattern is used as a mask for RIE to sequentially pattern fourth insulating layer5, third semiconductor layer3c, third insulating layer4b, second semiconductor layer3b, second insulating layer4a, first semiconductor layer3a, first insulating layer2, and common semiconductor layer14. As a result, fin-type stacked layer structure9is formed.

The resist pattern is removed afterwards.

As shown inFIG. 14E, gate stacked layer structures6(1),6(2), . . .6(n) and select gate electrodes10(10a,10b, and10c) extending in the third direction across fin-type stacked layer structure9are formed by a method such as the CVD or sputtering and by an anisotropic etching method such as the RIE.

Here, gate stacked layer structures6(1),6(2), . . .6(n) extend in the first direction, for example, in two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction. Select gate electrodes10(10a,10b, and10c) also extend in the first direction, for example, in two side surfaces of first to third semiconductor layers3(3a,3b, and3c) that face in the third direction.

The structure shown inFIG. 11is completed by the steps described above.

According to the second embodiment, the positions of the edges of the second and third insulating layers on the side of the drain electrode are adjusted so that when a current is passed through one selected memory string, unnecessary currents do not run through the remaining unselected memory strings (including the dummy memory string), and reading/writing/erasing can be accurately performed.

FIG. 15shows a structure according to the third embodiment.FIG. 16is a sectional view taken along the line XVI-XVI ofFIG. 15.FIG. 17is a sectional view taken along the line XVII-XVII ofFIG. 15.FIG. 18is a partial view showing the structure of a charge storage layer.

Here, the same elements as those in the first embodiment (FIG. 1toFIG. 3) are provided with the same reference marks and are thus not described in detail.

The third embodiment is characterized in that charge storage layers6(1)b,6(2)b, and6(3)bof a memory cell constituting first to third memory strings NANDa, NANDb, and NANDc are independent of one another.

That charge storage layers6(1)b,6(2)b, and6(3)bare independent means that charge storage layers6(1)b,6(2)b, and6(3)bare physically separated by a material (e.g., insulating layers or air gaps) different from the material constituting these charge storage layers.

Charge storage layers6(1)b,6(2)b, and6(3)bare independent for the respective memory cells so that the writing/erasing characteristics and cycling resistance of the three-dimensional stacked layer type semiconductor memory can be improved.

In the present embodiment, the charge storage layers have independent structures for the respective memory cells. Thus, it is possible to apply the memory cells, for example, not only to a SONOS memory cell that uses silicon-rich SiN as a charge storage layer but also to a floating gate type memory cell that uses, as a charge storage layer, a conductor serving as an electrically floating gate.

The configuration is the same as that according to the first embodiment in other respects.

B. Material Examples

In the third embodiment (FIG. 15toFIG. 18), the materials described in Material Examples in the first embodiment can be used to manufacture a three-dimensional stacked layer type semiconductor memory.

The third embodiment (FIG. 15toFIG. 18) can also be applied as in the first to third applications (FIG. 5toFIG. 7) in the first embodiment.

In the third embodiment (FIG. 15toFIG. 18), writing/erasing/reading can also be performed by the same operations as those described in the first embodiment.

E. Method of Manufacturing Structure in FIG.15

FIG. 19AtoFIG. 19Lshow a method of manufacturing the structure inFIG. 15.

In each of these drawings, (a) is a plan view, (b) is a sectional view taken along the line b-b, and (c) is a sectional view taken along the line c-c.

First, as shown inFIG. 19A, first-conductivity-type (e.g., p-type) semiconductor substrate (e.g., silicon)1having, for example, a plane direction (100) and a specific resistance of 10 to 20 Ωcm is prepared. On this semiconductor substrate1, first insulating layer (e.g., silicon oxide)2is formed. First semiconductor layer (e.g., silicon)3aand second insulating layer (e.g., silicon oxide)4aare then sequentially formed on first insulating layer2.

A resist pattern is formed on second insulating layer4aby the PEP. This resist pattern is used as a mask for RIE to pattern second insulating layer4aand first semiconductor layer3a.

As a result, the position of the edge of second insulating layer4ain the second direction is determined. The position of the edge of second insulating layer4ain the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Second semiconductor layer (e.g., silicon)3band third insulating layer (e.g., silicon oxide)4bare then sequentially formed on second insulating layer4a.

A resist pattern is formed on third insulating layer4bby the PEP. This resist pattern is used as a mask for RIE to pattern third insulating layer4band second semiconductor layer3b.

As a result, the position of the edge of third insulating layer4bin the second direction is determined. The position of the edge of third insulating layer4bin the second direction complies with the conditions described in the paragraphs for the structure. The resist pattern is removed afterwards.

Third semiconductor layer (e.g., silicon)3cand fourth insulating layer (e.g., silicon oxide)5are then sequentially formed on third insulating layer4b.

A resist pattern is formed on fourth insulating layer5by the PEP. This resist pattern is used as a mask for RIE to pattern fourth insulating layer5and third semiconductor layer3c.

As a result, the position of the edge of fourth insulating layer5in the second direction is determined. The position of the edge of uppermost fourth insulating layer5in the second direction is not particularly limited as has been described in the paragraphs for the structure.

The resist pattern is removed afterwards.

Here, in the present example, second to fourth insulating layers4a,4b, and5are preferably equal in thickness in the first direction if later-described ion implantation (collective implantation) is taken into consideration.

A resist pattern15is then formed on fourth insulating layer5by the PEP. This resist pattern15is used as a mask to implant ions.

In this ion implantation, the acceleration energy and dose amount are controlled to simultaneously form impurity regions13a,13b, and13cin first to third semiconductor layers3(3a,3b, and3c) (collective implantation).

As second to fourth insulating layers4a,4b, and5function as masks, each of impurity regions13a,13b, and13cis only formed at one end of each of first to third semiconductor layers3(3a,3b, and3c) in a self-aligning manner.

The resist pattern15is removed afterwards.

Common semiconductor layer (e.g., silicon)14is then formed, and the surface of common semiconductor layer14is planarized by the CMP. This planarization can also be conducted, for example, by dry etching.

Common semiconductor layer14combines first to third semiconductor layers3(3a,3b, and3c) at one end in the second direction.

A resist pattern is then formed on fourth insulating layer5and common semiconductor layer14by the PEP. This resist pattern is used as a mask for RIE to sequentially pattern fourth insulating layer5, third semiconductor layer3c, third insulating layer4b, second semiconductor layer3b, second insulating layer4a, first semiconductor layer3a, first insulating layer2, and common semiconductor layer14. As a result, fin-type stacked layer structure9is formed.

The resist pattern is removed afterwards.

As shown inFIG. 19B, the side surfaces of first to third semiconductor layers3ato3cin the third direction are then selectively etched by isotropic dry etching. As a result, the side surfaces of first to third semiconductor layers3ato3cin the third direction are set back, and first to third recesses21ato21cextending in the second direction are formed.

As shown inFIG. 19C, the side surfaces of first to third semiconductor layers3ato3cin the third direction are then thermally oxidized, and first gate insulating layers (e.g., silicon oxide)6aare formed on the side surfaces of first to third semiconductor layers3ato3cin the third direction.

As shown inFIG. 19D, charge storage layer6bcovering fin-type stacked layer structure9is then formed. A material such as silicon nitride or conductive polysilicon can be used as charge storage layer6b.

As shown inFIG. 19E, charge storage layer6bis then selectively etched by anisotropic dry etching. As a result, charge storage layer6bonly remains in first to third recesses21ato21con the side surfaces of first to third semiconductor layers3ato3cin the third direction.

That is, fourth insulating layer5is exposed when uppermost charge storage layer6bis removed. Therefore, fourth insulating layer5is used as a mask to further etch charge storage layer6b, and first to third charge storage layers6bare then formed in first to third recesses21ato21c, respectively.

Here, as fourth insulating layer5functions as a mask for etching charge storage layer6b, the width of fourth insulating layer5in the first direction may be greater than the width of each of first to third insulating layers2,4a, and4bin the first direction.

If the function of fourth insulating layer5as the mask is regarded as important, fourth insulating layer5may be formed by a method and a material different from first to third insulating layers2,4a, and4b(e.g., a stacked layer structure of different insulating layers).

At this point, first to third charge storage layers6bare separated in the first direction.

As shown inFIG. 19F, second gate insulating layer6cand control gate electrode6dthat cover fin-type stacked layer structure (including first to third charge storage layers6b)9are then formed. A material such as aluminum oxide can be used as second gate insulating layer6c, and a material such as nickel silicide can be used as control gate electrode6d.

As shown inFIG. 19G, second gate insulating layer6cand control gate electrode6dare fabricated by the PEP and the anisotropic dry etching, and control gate electrodes (word lines)6d, . . . are formed. Control gate electrodes (word lines)6d, . . . extend in the third direction on the side of fourth insulating layer5in the third direction, and extend in the first direction on the side of first to third charge storage layers6bin the third direction.

In this way, while gate stacked layer structure6(1) is formed in the memory string, select gate electrodes10a,10b, and10cof layer select transistors Ta, Tb, and Tc are formed at one end of the memory string in the second direction.

As shown inFIG. 19H, fourth insulating layer5is then selectively etched by anisotropic dry etching. At the same time, control gate electrodes6d, . . . function as masks for the anisotropic dry etching. Therefore, in parts that are not covered by control gate electrodes6d, . . . , fourth insulating layer5is selectively removed, and the side surfaces of third semiconductor layer3c, third charge storage layer6b, and third gate insulating layer6ain the first direction are exposed.

As shown inFIG. 19I, third charge storage layer6bis then selectively etched by anisotropic dry etching. At the same time, control gate electrodes6d, . . . and third semiconductor layer3cfunction as masks for the anisotropic dry etching. In this etching, first gate insulating layer6acan be removed together.

Therefore, as the part of third charge storage layer6bthat is not covered by control gate electrodes6d, . . . is selectively removed, third charge storage layers6b, . . . separated in the second direction and third gate insulating layer6aare formed on the side of third semiconductor layer3cin the third direction.

As shown inFIG. 19J, third insulating layer4bis then selectively etched by anisotropic dry etching. At the same time, control gate electrodes6d, . . . and third semiconductor layer3cfunction as masks for the anisotropic dry etching.

Therefore, in parts that are not covered by control gate electrodes6d, . . . and third semiconductor layer3c, third insulating layer4bis selectively removed, and the side surfaces of second charge storage layer6band second gate insulating layer6ain the first direction are exposed.

As shown inFIG. 19K, second charge storage layer6bis then selectively etched by anisotropic dry etching. At the same time, control gate electrodes6d, . . . and third semiconductor layer3cfunction as masks for the anisotropic dry etching. In this etching, first gate insulating layer6acan be removed together.

Therefore, as the part of second charge storage layer6bthat is not covered by control gate electrodes6d, . . . is selectively removed, second charge storage layers6b, . . . separated in the second direction and second gate insulating layer6aare formed on the side of second semiconductor layer3bin the third direction.

Similarly, first charge storage layers6b, . . . separated in the second direction and first gate insulating layer6aare formed on the side of first semiconductor layer3ain the third direction.

As shown inFIG. 19L, charge storage layers6b, . . . physically separated for the respective memory cells are formed by the process described above. This prevents a situation where a charge in a charge storage layer moves to another charge storage layer in first to third charge storage layers6b, . . . , so that satisfactory data retention characteristics can be obtained.

According to the third embodiment, the positions of the edges of the second and third insulating layers on the side of the drain electrode are adjusted so that when a current is passed through one selected memory string, unnecessary currents do not run through the remaining unselected memory strings, and reading/writing/erasing can be accurately performed.

3. VERIFICATION OF CUT-OFF CHARACTERISTICS

The improvement of the cut-off characteristics according to the structure of the embodiment is described by comparison with that according to a conventional structure.

FIG. 20shows a simulation model according to the embodiment.

Conditions are as follows.

First to third semiconductor layers3a,3b, and3cand common semiconductor layer14are p-type semiconductor layers including a p-type impurity of 1×1017atoms/cm3, and impurity regions13a,13b, and13care n-type impurity regions including an n-type impurity of 1×1016atoms/cm3, here 5×1018atoms/cm3.

The width of each of first to third semiconductor layers3a,3b, and3cin the first direction is 32 nm, and the width of each of first to fourth insulating layers2,4a,4b, and5in the first direction is also 32 nm. The width of fin-type stacked layer structure in the third direction, that is, the width of each of first to third semiconductor layers3a,3b, and3cand each of first to fourth insulating layers2,4a,4b, and5in the third direction is 20 nm.

Width (line width) L of each of control gate electrodes CG1, CG2, and CG3and each of select gate electrodes SG1, SG2, and SG3in the second direction is 32 nm, and the space therebetween is also 32 nm. That is, the gate interval (pitch) is 32 nm.

Potential Vd of drain electrode7is 0.05 V, and the source ends of first to third semiconductor layers3a,3b, and3care connected to a ground point via ammeters16a,16b, and16c.

The potential of each of control gate electrodes CG1, CG2, and CG3and each of select gate electrodes SG2and SG3is 5 V.

Under such conditions, the cut-off characteristics of layer select transistors Ta, Tb, and Tc are verified by changing potential Vsg1of select gate electrode SG1from −5 V to 5 V.

Under the above-mentioned conditions, first memory string NANDa is selected, and second and third memory strings NANDb and NANDc are not selected. Therefore, when potential Vsg1of select gate electrode SG1is 0 V (first layer select transistors Ta in second and third semiconductor layers3band3care off), the cut-off characteristics are better if current values detected by ammeters16band16care lower.

FIG. 21shows the results of the simulation ofFIG. 20.

According to the results, when potential Vsg1of select gate electrode SG1is 0 V, a current of about 1×10−7A runs through first memory string NANDa, whereas almost no current runs through second and third memory strings NANDb and NANDc (less than 1×10−11A).

Thus, according to the structure of the embodiment, the cut-off characteristics of the layer select transistors can be improved.

FIG. 22shows a simulation model according to a conventional technique.

This conventional technique corresponds to a structure disclosed in FIG. 13 of PCT/JP2009/060803 as a prior application.

The conventional technique is different from the structure according to the embodiment in that the drain ends of second and third insulating layers4aand4bare shorter. That is, second and third insulating layers4aand4bare not present on impurity regions13aand13b.

Other conditions are the same as the structure according to the embodiment (FIG. 20).

Under such conditions, the cut-off characteristics of layer select transistors Ta, Tb, and Tc are verified by changing potential Vsg1of select gate electrode SG1from −5 V to 5 V.

Under the above-mentioned conditions, first memory string NANDa is selected, and second and third memory strings NANDb and NANDc are not selected. Therefore, when potential Vsg1of select gate electrode SG1is 0 V (first layer select transistors Ta in second and third semiconductor layers3band3care off), the cut-off characteristics are better if current values detected by ammeters16band16care lower.

FIG. 23shows the results of the simulation ofFIG. 22.

According to the results, when potential Vsg1of select gate electrode SG1is 0 V, a current of about 1×10−7A runs through first memory string NANDa, while a current of about 1×10−8A also runs through second and third memory strings NANDb and NANDc.

This is attributed to the presence of a current path indicated by a thick arrow inFIG. 22. In the structure according to the embodiment, no such current path is present.

Therefore, according to the conventional technique, the cut-off characteristics of the layer select transistors are inadequate.

As described above, according to the structure of the embodiment, a high degree of integration is maintained, and at the same time, the cut-off characteristics can be improved as compared with the conventional technique.

Regarding a series connection comprising memory cells and select transistors (layer select transistors and source-side select transistors) connected in series, a diffusion layer may be or may not be formed between the transistors.

When the gate interval (the pitch of the control gate electrodes) is 30 nm or less, a current path can be formed in the semiconductor layer (channel) without even a diffusion layer between the transistors (e.g., see Chang-Hyum Lee et al., VLSI Technology Digest of Technical Papers, pp. 118-119, 2008).

According to the embodiment, it is possible to provide a three-dimensional stacked layer type semiconductor memory that enables both a high degree of integration and satisfactory cut-off characteristics.

The embodiment is industrially enormously advantageous to, for example, a file memory capable of high-speed random writing, a mobile terminal capable of high-speed downloading, a mobile player capable of high-speed downloading, a semiconductor memory for broadcasting devices, a drive recorder, a home video, a high-capacity buffer memory for communication, and a semiconductor memory for a security camera.