Digitally controlled oscillator

A digitally controlled oscillator includes a ring oscillator, a parallel resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a serial resistor bank connected to a second terminal of the ring oscillator and having a resistance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the parallel resistor bank and the resistance of the serial resistor bank according to the digital code.

CROSS-REFERENCE TO RELATED APPLICATIONS

A claim of priority is made to Korean Patent Application No. 10-2008-0099348, filed Oct. 9, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The inventive concepts described herein generally relate to oscillators, and more particularly, the invention concepts relate to digitally controlled oscillators.

Generally, a digitally controlled oscillator (DCO) must have a relatively wide tuning range in order to execute digital automatic frequency calibration of a phase locked loop (PLL) or a voltage controlled oscillator (VCO) of a wide operating range.

In the meantime, when frequency is controlled in a ring oscillator type DCO using a digital-to-analog converter (DAC) and a current starved transistor, a transistor used for a current source has a size that is significantly larger than a transistor used for a ring oscillator, and it is difficult to obtain a wide tuning range of about 2 decades.

In an effort to obtain an oscillator of a wide tuning range, a resistor or a capacitor may be switched according to a digital code. In this case, a frequency output from the oscillator varies generally along a 1/x curve since the frequency is inversely proportional to the resistance and the capacitance. If the frequency varies nonlinearly, the resolution of the frequency, which varies with the digital code, is degraded.

SUMMARY

According to an aspect of the inventive concept, a digitally controlled oscillator includes a ring oscillator, a parallel resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a serial resistor bank connected to a second terminal of the ring oscillator and having a resistance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the parallel resistor bank and the resistance of the serial resistor bank according to the digital code.

According to another aspect of the inventive concept, a digitally controlled oscillator includes a ring oscillator, a resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a capacitor bank connected to a second terminal of the ring oscillator and having impedance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the resistor bank and the impedance of the capacitor bank according to the digital code.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals in the drawings denote like elements, and thus their description will not be repeated.

FIGS. 1A,1B and1C are circuit diagrams of a current based inverter, a C-based inverter, and an R-based inverter, respectively, each of which may be employed in an oscillator.

The current based inverter illustrated inFIG. 1Aincludes first and second serially connected transistors of different polarities each gated to an input IN, and an current source transistors receiving bias voltages Vbp and Vbn. The current based transistors of this type can obtain a wide tuning range relative to the output OUT only with sufficiently large current source transistors to which bias voltages Vbp and Vbn are respectively applied.

In the C-based inverter ofFIG. 1Bincludes first and second serially connected transistors of different polarities each gated to an input IN, and a capacitance C connected between the output terminal OUT and ground. On the other hand, the R-based inverter includes first and second serially connected transistors of different polarities each gated to an input IN, and resistive elements R connected in the paths of the power supply VDD and output OUT.

In the C-based inverter and the R-based inverter, when a resistance R or capacitance C linearly varies, a frequency varies in a non-linearly manner inversely to the resistance R or capacitance C, and thus it is difficult to obtain a wide tuning range. The frequency variation can maintain linearity if the resistance R or capacitance C varies only slightly, but nonlinearity of the frequency variation increases as a variation in the resistance R or capacitance C increases. In the case of utilizing digital codes in a digitally controlled oscillator (DCO), a control resolution of a digitally controlled oscillator (DCO) decreases when the frequency variations become nonlinear.

FIG. 2is a circuit diagram of a DCO according to an embodiment of one or more inventive concepts described herein. As shown, the DCO of the example ofFIG. 2includes a ring oscillator1, a parallel resistor bank2and a serial resistor bank3.

The ring oscillator1ofFIG. 2includes a current-based inverter such as that illustrated inFIG. 1A, where the current sources are respectively implemented by the parallel resistor bank2and the serial resistor bank3ofFIG. 2.

The parallel resistor bank2forms resistance Rp and, in this example, includes a plurality (n=N+1) of p-type metal-oxide semiconductor (PMOS) transistors connected in parallel and respectively driving by signal bits Cb<0> through Cb<N> of an input digital code C. Also, in the example of this embodiment, a channel width W of each of n-th PMOS transistor is half the size of each (n+1)-th PMOS transistor. For example, the channel width W of the PMOS transistor receiving signal bit Cb<1> is twice the channel width W of the PMOS transistor receiving signal bit Cb<0>. The resistance Rp of the parallel resistor bank2adjusts a total transconductance Gmp of a plurality of p-type metal-oxide semiconductor (PMOS) transistors MPs included in the inverters forming the ring oscillator1.

The serial resistor bank3forms resistance Rn and, in this example, includes a plurality (n=N+1) of resistive elements connected in series, with a plurality (n=N+1) of n-type metal-oxide semiconductor (NMOS) transistors connected across the respective resistors and respectively driving by signal bits Cb<0> through Cb<N> of the input digital code C. Also, in the example of this embodiment, a resistance of each n-th resistor transistor is half that of each (n+1)-th resistor. For example, the resistance of the resistor connect to the transistor receiving signal bit Cb<1> is twice the resistance of the resistor connected to the NMOS transistor receiving signal bit Cb<0>. The resistance Rn of the parallel resistor bank2adjusts a total transconductance Gmn of a plurality of n-type metal-oxide semiconductor (NMOS) transistors MNs included in the inverters forming the ring oscillator1.

The average of the transconductances Gmp of the MPs and the transconductances Gmn of the MNs corresponds to the total transconductance Gm. Gmp corresponds to gmp/(1+gmpRp) and Gmn corresponds to gmn/(1+gmnRs). Here, gmp is the transconductance of a single PMOS transistor MP and gmn is the transconductance of a single NMOS transistor MN included in each of the inverters. It is assumed that the sizes of the PMOS transistor MP and the NMOS transistor MN are determined such that gmp=gmn=gm, wherein gm denotes a value being identical with gmp and gmn. The DCO has a higher frequency as the parallel resistance Rp or the serial resistance Rs decreases, and thus the frequency increases as a control code increases if the DCO has a small resistance while a resistance control code is large. The parallel resistance Rp decreases along a 1/x curve and the serial resistance Rs decreases along a straight line having a gradient −x as the digital code increases. For example, if the digital code has 5 bits and unit resistance of a transistor is ΔR, the parallel resistance Rp becomes 32ΔR/x and the serial resistance becomes ΔR(33−x). When the parallel resistance Rp and the serial resistance Rs which vary with the digital code are applied to the parallel resistor bank2and the serial resistor bank3, Gmp and Gmn can be obtained as follows.

Here, the frequency is determined as follows.

The two frequencies of Equation 2 are summed up to determine the frequency of the DCO.

FIG. 3is a graph illustrating a relationship between a normalized frequency and a frequency according to equation 2 with respect to a frequency control code input to the DCO illustrated inFIG. 2. Reference numeral30represents the frequency normalized with respect to the frequency control code input to the DCO illustrated inFIG. 2, reference numeral31denotes a frequency corresponding to the parallel resistor bank illustrated inFIG. 2and reference numeral32represents a frequency corresponding to the serial resistor bank illustrated inFIG. 2.

Referring toFIG. 3, the curved lines31and32show that frequency variations considerably vary with respect to a frequency control code variation over ranges other than narrow range portions. In contrast, the curved line30shows that a frequency variation with respect to the frequency control code variation is uniform over a range other than both edges of the graph. Accordingly, the frequency corresponding to each frequency control code linearly varies, and thus a high resolution can be obtained.

Although the DCO illustrated inFIG. 2employs resistance banks, one or more capacitor banks can be also used for the DCO.FIG. 4illustrates an example in which a parallel capacitor bank and a parallel resistor bank are used for a DCO. The impedance of the parallel capacitor bank operates in the same manner as the resistance of the serial resistor bank illustrated inFIG. 2, and thus the same effect can be obtained.