Gate driving device and display device having the same

A display device includes a display panel, a voltage generator configured to generate a gate driving voltage, a timing controller configured to generate a clock control signal, a gate controller configured to generate gate clock signals, a gate driver configured to generate a gate signal, an over current protection circuit configured to generate a gate clock current corresponding to the gate clock signals and output a shutdown control signal, and an abnormal signal detector configured to determine whether the clock control signal is abnormal based on a difference of a set reference signal and the clock control signal, and output a delay control signal that delays an output timing of the shutdown control signal from the over current protection circuit for a set time when the clock control signal is abnormal.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0080477, filed on Jul. 11, 2018 in the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Technical Field

Example embodiments relate generally to a gate driving device and a display device having the same.

2. Description of the Related Art

Flat panel display (FPD) devices are widely used as displays for electronic devices because FPD devices are relatively lightweight and thin compared to cathode-ray tube (CRT) display devices. Non-limiting examples of FPD devices are liquid crystal display (LCD) devices, field emission display (FED) devices, plasma display panel (PDP) devices, and organic light emitting display (OLED) devices. A FPD device includes a display panel that displays an image and a driver that drives the display panel. For example, the LCD device may include a liquid crystal display panel in which a plurality of pixels is formed by a plurality of gate lines and a plurality of data lines, a gate driver that outputs a gate signal to the gate line, and a data driver that outputs a data signal to the data line.

An over current protection (OCP) circuit that shuts down the power of the display device may be used when an over current flows due to the defects such as an abnormal signal that outputs from the gate driver, a short between lines, etc. is used. A power unit of the display device that is shut down by the OCP circuit may not operate again. Therefore, the display device may not operate again, as the power unit is shut down due to a temporary electrostatic surge and/or an electric surge.

SUMMARY

This summary is provided to introduce a selection of features and concepts of embodiments of the present disclosure that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in limiting the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a workable device.

Aspects of example embodiments of the present disclosure relate to a gate driving device and a display device having the same.

Aspects of some example embodiments are directed toward a gate driving device capable of delaying an operation of an OCP circuit by an abnormal signal.

Aspects of some example embodiments are directed toward a display device capable of delaying an operation of an OCP circuit by an abnormal signal.

According to one or more example embodiments, a display device may include a display panel including a plurality of pixels, a voltage generator configured to generate a gate driving voltage, a timing controller configured to generate a clock control signal having a first level in a first period and a second level lower than the first level in a second period, a gate controller configured to generate gate clock signals based on the gate driving voltage and the clock control signal, a gate driver configured to generate a gate signal based on the gate clock signals and provide the gate signal to the pixels, an over current protection circuit configured to detect a gate clock current corresponding to the gate clock signals and output a shutdown control signal that shuts down the voltage generator when the gate clock current is greater than a set or predetermined reference current, and an abnormal signal detector configured to determine whether the clock control signal is abnormal based on a difference of a set or predetermined reference signal and the clock control signal, and output a delay control signal that delays an output timing of the shutdown control signal from the over current protection circuit for a set or predetermined time when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector is configured to compare the reference signal and the clock control signal having the first level in the first period and to compare the reference signal and an inversion signal of the clock control signal having the second level in the second period.

In one or more example embodiments, the abnormal signal detector may include a comparator including a first input terminal that is configured to receive the reference signal, a second input terminal that is configured to receive the clock control signal, and an output terminal that is configured to output a comparing result of the reference signal and the clock control signal, a first switch configured to receive the clock control signal and turn on during the first period, wherein the first switch is coupled to the second input terminal of the comparator, a second switch configured to receive the clock control signal and turn on during the second period, and an inverter coupled between the second switch and the second input terminal.

In one or more example embodiments, the abnormal signal detector may determine that the clock control signal is abnormal when the difference between the reference signal and the clock control signal is greater than a set or predetermined critical value.

In one or more example embodiments, the abnormal signal detector may determine that the clock control signal is abnormal when the reference signal and the clock control signal are different from each other.

In one or more example embodiments, the reference signal may have the same level as the first level of the clock control signal.

In one or more example embodiments, the abnormal signal detector may block the over current protection circuit from outputting the shutdown control signal during the set or predetermined time when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector may output the delay control signal that turns off power of the over current protection circuit when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector may output the delay control signal that turns off a third switch coupled between the over current protection circuit and the voltage generator when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector may output the delay control signal that turns off a fourth switch coupled between the gate controller and the over current protection circuit when the clock control signal is abnormal.

According to one or more example embodiments, a gate driving device may include a voltage generator configured to generate a gate driving voltage, a gate controller configured to generate gate clock signals based on the gate driving voltage and a clock control signal having a first level in a first period and a second level in a second period, a gate driver configured to generate a gate signal based on the gate clock signals, an over current protection circuit configured to detect a gate clock current corresponding to the gate clock signals and output a shutdown control signal that shuts down the voltage generator when the gate clock current is greater than a set or predetermined reference current, and an abnormal signal detector configured to determine whether the clock control signal is abnormal based on a difference between a set or predetermined reference signal and the clock control signal, and output a delay control signal that delays an output timing of the shutdown control signal provided from the over current protection circuit for a set or predetermined time when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector is configured to compare the reference signal and the clock control signal having the first level in the first period and to compare the reference signal and an inversion signal of the clock control signal having the second level in the second period.

In one or more example embodiments, the abnormal signal detector may include a comparator including a first input terminal that is configured to receive the reference signal, a second input terminal that is configured to receive the clock control signal and an output terminal that is configured to output a comparing result of the reference signal and the clock control signal, a first switch configured to receive the clock control signal and turn on during the first period, wherein the first switch is coupled to the second input terminal of the comparator, a second switch configured to receive the clock control signal and turn on during the second period, and an inverter coupled between the second switch and the second input terminal.

In one or more example embodiments, the abnormal signal detector may determine that the clock control signal is abnormal when a difference between the reference signal and the clock control signal is greater than a set or predetermined critical value.

In one or more example embodiments, the abnormal signal detector may determine the clock control signal is abnormal when the reference signal and the clock control signal are different from each other.

In one or more example embodiments, the reference signal may have the same level as the first level of the clock control signal.

In one or more example embodiments, the abnormal signal detector may block the over current protection circuit from outputting the shutdown control signal during the set or predetermined time when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector may output the delay control signal that turn off an operation power of the over current protection circuit when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector may output the delay control signal that turns off a third switch coupled between the over current protection circuit and the voltage generator when the clock control signal is abnormal.

In one or more example embodiments, the abnormal signal detector may output the delay control signal that turns off a fourth switch coupled between the gate controller and the over current protection circuit when the clock control signal is abnormal.

Therefore, according to one or more example embodiments, the gate driving device and the display device having the same may reduce or prevent the voltage generator from shutting down due to the abnormal signal by determining whether the clock control signal is abnormal and delaying an operation of the over current protection circuit when the clock control signal is abnormal. Thus, defect due to the shutdown of the voltage generator may be reduced or prevented.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of some example embodiments of a gate driving device and a display device having the same provided in accordance with the present invention and is not intended to represent the only forms in which the present invention may be constructed or utilized. The description sets forth the features of the present invention in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the scope of the invention. As denoted elsewhere herein, like element numbers are intended to indicate like elements or features.

Hereinafter, the present inventive concept will be explained in more detail with reference to the accompanying drawings.

FIG. 1is a block diagram illustrating a display device according to example embodiments.FIG. 2is a timing diagram illustrating an operation of a gate controller included in the display device ofFIG. 1.FIG. 3is a diagram illustrating an operation of an over current protection circuit included in the display device ofFIG. 1.

Referring toFIG. 1, a display device100may include a display panel110, a voltage generator120, a timing controller130, a gate controller140, a gate driver150, an over current protection circuit160, an abnormal signal detector170, and a data driver180.

The display panel110may include a plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels PX. The gate lines GL may extend in a first direction D1and be arranged in a second direction D2, crossing (e.g., perpendicular to) the first direction D1. The data lines DL may extend in the second direction D2and be arranged in the first direction D1. The first direction D1may be parallel with a long side of the display panel110, and the second direction D2may be parallel with a short side of the display panel110. Each of the pixels PX may be formed in crossing or intersection regions of the data lines DL and the gate lines GL. In some example embodiments, each of the pixels PX may include a thin film transistor electrically coupled to the data line DL and the gate line GL, a liquid crystal capacitor, and a storage capacitor coupled to the thin film transistor. Thus, the display panel110may be a liquid crystal display panel, and the display device100may be a liquid crystal display device. In other example embodiments, each of the pixels PX may include a thin film transistor electrically coupled to the data line DL and the gate line GL, a storage capacitor coupled to the thin film transistor, a driving transistor coupled to the storage capacitor, and an organic light emitting diode coupled to the driving transistor. Thus, the display panel110may be an organic light emitting display panel, and the display device100may be an organic light emitting display device. The display panel110may include a display area DA and a non-display area NDA. The pixels PX may be formed in the display area DA and an image may be displayed in the display area DA. The circuits and the lines that generate or provide a signal for driving the pixels PX may be formed in the non-display area NDA.

The voltage generator120may receive a direct power VDD from an external device and generate a plurality of voltages to drive the display panel110. The voltage generator120may generate a gate driving voltage DVG provided to the gate controller140, a data driving voltage DVD provided to the data driver180, and a panel driving voltage provided to the display panel110. For example, the voltage generator120may generate the gate driving voltage DVG that includes a gate on voltage and a gate off voltage, and provide the gate driving voltage DVG to the gate controller140. The gate on voltage and the gate off voltage may be a driving voltage to generate a gate signal applied to the gate line GL. The voltage generator120may generate the data driving voltage DVD that includes an analog power voltage, a digital power voltage, etc., and provide the data driving voltage DVD to the data driver180. The analog power voltage and the digital power voltage may be a driving voltage to generate a data signal DS applied to the data line DL. The voltage generator120may generate the panel driving voltage that includes a common voltage, a storage voltage, etc., and provide the panel driving voltage to the display panel110. The common voltage may be a driving voltage applied to the liquid crystal capacitor included in the pixel PX, and the storage voltage may be a driving voltage applied to the storage capacitor included in the pixel PX. The storage voltage may be the same as the common voltage.

The timing controller130may generate a clock control signal CPV that controls the gate controller140. The timing controller130may receive a control signal from the external device and generate a vertical start signal STV and the clock control signal CPV provided to the gate controller140. For example, the clock control signal CPV may have a first level in a first period and a second level lower than the first level in a second period. The timing controller130may provide the vertical start signal STV and the clock control signal CPV to the gate controller140. Further, the timing controller130may generate a horizontal start signal and a data clock signal that control the data driver180. The timing controller130may convert a first image data provided from the external device to a second image data. For example, the timing controller may convert the first image data to the second image data by applying an algorithm that compensates display quality. The timing controller130may provide the horizontal start signal, the data clock signal, and the second image data to the data driver180.

The gate controller140may generate gate clock signals CKG based on the gate driving voltage DVG and the clock control signal CPV. The gate controller140may receive the data driving voltage DVG that includes the gate on voltage and the gate off voltage from the voltage generator120. Further, the gate controller140may receive the vertical start signal STV and the clock control signal CPV from the timing controller130. The gate controller140may receive at least one clock control signal CPV from the timing controller130. For example, the gate controller140may receive a first clock control signal and a second clock control signal from the timing controller130. The gate controller140may generate the gate clock signals CKG that swing between the gate on voltage and the gate off voltage based on the clock control signal CPV. For example, the gate clock signals CKG may include a clock signal and a clock bar signal.

Referring toFIG. 2, the gate controller140may generate gate clock signal CKG (e.g., the clock signal CKV and the clock bar signal CKVB) using the gate on voltage Von and the gate off voltage Voff in response to the clock control signal CPV provided from the timing controller130. One frame may include an active period AP and a blank period BP. The clock control signal CPV may swing between a voltage of first level LV1and a voltage of second level LV2in the active period AP, and have the voltage of second level LV2in the blank period BP. The clock signal CKV and the clock bar signal CKVB may swing between the gate on voltage Von and the gate off voltage Voff in the active period AP and have the gate off voltage Voff during the blank period BP in response to the clock control signal CPV. The gate on voltage Von of the clock signal CKV and the clock bar signal CKVB is higher than the first level LV1of the clock control signal CPV. The gate off voltage Voff of the clock signal CKV and the clock bar signal CKVB is lower than the second level LV2of the clock control signal CPV. An abnormal clock control signal CPV may be provided to the gate controller140due to an electrostatic surge and/or an electric surge. An abnormal clock signal CKV and the abnormal clock bar signal CKVB may output when the abnormal clock control signal CPV is provided because the clock signal CKV and the clock bar signal CKVB are generated in response to the clock control signal CPV. The abnormal clock control signal CPV may be restored in the same frame or after the blank period BP. When the clock control signal CPV is outputted normally, the clock signal CKV and the clock bar signal CKVB may be normally outputted to swing between the gate on voltage Von and the gate off voltage Voff.

The gate driver150may generate the gate signal based on the gate clock signals CKG and provide the gate signal to the pixels PX through the gate lines GL. The gate driver150may be formed in the non-display area NDA of the display panel110. The gate driver150may sequentially output the gate signals synchronized with the gate clock signals CKG. The gate driver150may include a plurality of stages, for example,152,154, or the like. Each of the stages152,154, may receive the gate clock signals CKG (e.g., the clock signal CKV and the clock bar signal CKVB) form the gate controller140. Each of the stages152,154may be coupled to an end of the gate line GL that extends to the display area DA. For example, the first stage152may generate a first gate signal based on the gate clock signals CKG and provide the first gate signal through the gate line GL coupled to the pixels PX in a first column. Further, the second stage154may generate a second gate signal based on the gate clock signals CKG and provide the second gate signal through the gate line GL coupled to the pixels in a second column. Similarly, the stages of the gate driver150may sequentially provide the gate signal to the gate lines GL.

The gate driver150may be formed as a plurality of driving chips, mounted on a flexible printed circuit board, and coupled to the display panel110in a tape carrier package (TCP) method. Alternatively, the gate driver150may be formed as the plurality of driving chips mounted on the non-display area NDA of the display panel110in a chip on glass (COG) method. Alternatively, the gate driver150may be simultaneously or concurrently formed with the transistors of the pixels PX and mounted on the display panel110as amorphous silicon TFT gate driver circuit (ASG) or oxide silicon TFT gate driver circuit (OSG).

The over current protection circuit160may detect a gate clock current IG corresponding to the gate clock signals CKG and output a shutdown control signal CTL_SHUT that shuts down the voltage generator120when the gate clock current IG is greater than a set or predetermined reference current. The over current protection circuit160may detect the gate clock current IG of the gate clock signals CKG in every frame. Referring toFIG. 3, the over current protection circuit160may determine that the over current occurs in the gate controller140when the gate clock current IG is greater than the reference current IR. The over current protection circuit160may output the shutdown control signal CTL_SHUT that shuts down the voltage generator120when the over current occurs in the gate controller140. The voltage generator120may not output the gate driving voltage DVG in response to the shutdown control signal CTL_SHUT and deactivate an operation of the gate controller140. Thus, damages to elements of the display device100may be reduced or prevented. For example, the voltage generator120may include a switch that blocks or provides the direct power provided from the external device in response to the shutdown control signal CTL_SHUT. When the switch125turns off in response to the shutdown control signal CTL_SHUT, the gate driving voltage DVG and the data driving voltage DVD may not be generated.

The abnormal signal detector170may determine whether the clock control signal CPV is abnormal based on a difference between a set or predetermined reference signal and the clock control signal CPV, and output a delay control signal CTL_D that delays an output timing of the shutdown control signal CTL_SHUT as a set or predetermined time when the clock control signal CPV is abnormal. The over current may be detected in the gate controller140due to the electrostatic surge and/or a short between lines in the gate controller140. As described inFIG. 2, although the clock control signal CPV abnormally outputs due to the electrostatic surge, the electric surge, etc., the clock control signal CPV may be restored to normal as time passes. The abnormal signal detector170may delay the output timing of the shutdown control signal CTL_SHUT form the over current protection circuit160during the time in which the abnormal clock control signal CPV is restored to normal. Thus, the abnormal signal detector170may protect or prevent the voltage generator120from immediately shutting down. For example, the abnormal signal detector170may output the delay control signal CTL_D during one frame or two frames.

The abnormal signal detector170may determine whether the clock control signal CPV is abnormal by comparing the reference signal and the clock control signal CPV having the first level in the first period and comparing the reference signal and the clock signal CPV having the second level in the second period. In some example embodiments, the abnormal signal detector170may determine that the clock control signal CPV is abnormal when the difference between the reference signal and the clock control signal CPV is greater than a set or predetermined critical value. In other example embodiments, the abnormal signal detector170may determine that the clock control signal CPV is abnormal when the reference signal and the clock control signal CPV are different from each other. Here, the reference signal may have the same level as the first level of the clock control signal CPV. The abnormal signal detector170may block or prevent the over current protection circuit160from outputting the shutdown control signal CTL_SHUT in the set or predetermined time when the clock control signal CPV is abnormal. In some example embodiments, the abnormal signal detector170may output the delay control signal CTL_D that turns off the power of the over current protection circuit160when the clock control signal CPV is abnormal. In other example embodiments, the abnormal signal detector170may output the delay control signal CTL_D that turns off a switch coupled between the over current protection circuit160and the voltage generator120when the clock control signal CPV is abnormal. In other example embodiments, the abnormal signal detector170may output the delay control signal CTL_D that turns off a switch coupled between the gate controller140and the over current protection circuit160.

The over current protection circuit160may output the shutdown control signal CTL_SHUT after the set or predetermined time in response to the delay control signal CTL_D provided from the abnormal signal detector170, although the over current is detected. Thus, the voltage generator120may not shut down when the abnormal signal is temporarily provided. When the over current is detected and the delay control signal CTL_D is not provided, the over current protection circuit160may determine that the short between the lines has occurred and immediately output the shutdown control signal CTL_SHUT. Thus, the damage to the elements of the display device100may be reduced or prevented.

Although the display device100, that includes each of the voltage generator120that generates the gate driving voltage DVG, the gate controller140that generates the gate clock signals CKG, the gate driver150that generates the gate signal, the over current protection circuit160that detects the over current of the gate clock signals CKG and shuts down the voltage generator120, and the abnormal signal detector170that delays the operation of the over current protection circuit160when the abnormal signal is detected, is described as being arranged as inFIG. 1, the voltage generator120, the gate controller140, the gate driver150, the over current protection circuit160, and the abnormal signal detector170, may be more specifically arranged as a gate driving device of the display device100.

InFIG. 1, the data driver180may provide the data signal DS to the pixels PX through the data line DL. The data driver180may generate the data signal DS based on the data control signal and the second image data provided from the timing controller130. The data control signal may include the horizontal start signal and the data clock signal. The data driver180may output the data signal corresponding to the second image data to the data lines DL in the display panel110in response to the horizontal start signal and the data clock signal.

As described above, the display device100ofFIG. 1may determine whether the clock control signal CPV is abnormal and prevent or block the voltage generator120from shutting down in response to abnormal signal temporarily provided by delaying the operation of the over current protection circuit160when the abnormal clock control signal CPV is provided. Thus, defects that occur by the shutdown of the voltage generator120may be reduced or prevented.

FIG. 4is a block diagram illustrating an example of an abnormal signal detector170included in the display device ofFIG. 1.

Referring toFIG. 4, the abnormal signal detector170may include a comparator171, a first switch172, a second switch173, and an inverter174.

The comparator171may include a first input terminal IN1, a second input terminal IN2, and an output terminal OUT. The reference signal S_REF may be provided through the first input terminal IN1, the clock control signal CPV may be provided through the second input terminal IN2, and a comparing result of the reference signal S_REF and the clock control signal CPV may be outputted as the delay control signal CTL_D through the output terminal OUT.

The reference signal S_REF may have the same level as the first level of the clock control signal CPV and may be provided to the comparator171through the first input terminal IN1. The clock control signal CPV may include a first period and a second period. The clock control signal CPV having the first level may be outputted during the first period, and the clock control signal CPV having the second level may be outputted during the second period. The first switch172may receive the clock control signal CPV and turn on during the first period. The first switch172may be coupled to the second input terminal IN2of the comparator171. That is, the first switch172may turn on, and the clock control signal CPV having the first level may be provided to the second input terminal IN2through the first switch172, during the first period. The second switch173may receive the clock control signal CPV and turn on during the second period. Further, the inverter174may be coupled between the second switch173and the second input terminal IN2. That is, when the second switch173turns on, the clock control signal CPV having the second level may be provided to the inverter174through the second switch173, and an inversion signal of the clock control signal CPV may be provided to the second input terminal IN2during the second period. For example, when the second level of the clock control signal CPV is a negative number, the inversion signal having a positive number may be provided to the second input terminal IN2.

The comparator171may compare the reference signal S_REF and the clock control signal CPV having the first level during the first period and compare the reference signal S_REF and the clock control signal CPV having the second level during the second period. In some example embodiments, the comparator171may output the delay control signal CTL_D that delays the operation of the over current protection circuit160through the output terminal OUT when the difference between the reference signal S_REF and the clock control signal CPV is greater than the set or predetermined critical value. In other example embodiments, the comparator171may output the delay control signal CTL_D that delays the operation of the over current protection circuit160through the output terminal OUT when the reference signal S_REF and the clock control signal CPV are different from each other. Here, the reference signal S_REF may have the same level as the first level of the clock control signal CPV. The comparator171may output the delay control signal CTL_D during the set or predetermined time. For example, the delay control signal CTL_D may output during one frame or two frames.

FIGS. 5A-5Care diagrams illustrating an operation of an abnormal signal detector included in the display device ofFIG. 1.

Referring toFIG. 5A, the abnormal signal detector170may provide the delay control signal CTL_D to the over current protection circuit160. The abnormal signal detector170may provide the delay control signal CTL_D to a power unit in the over current protection circuit160. The abnormal signal detector170may output the delay control signal CTL_D that turns off the power unit162of the over current protection circuit160during the set or predetermined time when the clock control signal CPV is abnormal. Thus, the over current protection circuit160may provide the shutdown control signal CTL_SHUT after the set or predetermined time when the gate current IG corresponding to the gate clock signals CKG is greater than the reference current (e.g., when the over current is detected).

Referring toFIG. 5B, a third switch164may be coupled between the over current protection circuit160and the voltage generator. The abnormal signal detector170may output the delay control signal CTL_D that turns off the third switch164during the set or predetermined time when the clock control signal CPV is abnormal. Thus, the over current protection circuit160may provide the shutdown control signal CTL_SHUT after the set or predetermined time when the gate current IG corresponding to the gate clock signals CKG is greater than the reference current (e.g., when the over current is detected).

Referring toFIG. 5C, a fourth switch166may be coupled between the gate controller140and the over current protection circuit160. The abnormal signal detector170may output the delay control signal CTL_D that turns off the fourth switch166during the set or predetermined time when the clock control signal CPV is abnormal. Thus, the over current protection circuit160may provide the shutdown control signal CTL_SHUT after the set or predetermined time when the gate current IG corresponding to the gate clock signals CKG is greater than the reference current (e.g., when the over current is detected).

FIG. 6is a block diagram illustrating an electronic device that includes the display device ofFIG. 1andFIG. 7is a diagram illustrating an example embodiment in which the electronic device ofFIG. 6is implemented as a smart phone.

Referring toFIGS. 6 and 7, an electronic device200may include a processor210, a memory device220, a storage device230, an input/output (I/O) device240, a power device250, and a display device260. Here, the display device260may correspond to the display device100ofFIG. 1. In addition, the electronic device200may further include a plurality of ports for communicating a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. Although it is illustrated inFIG. 7that the electronic device200is implemented as a smart phone300, a kind of the electronic device200is not limited thereto.

The processor210may perform various computing functions. The processor210may be a micro-processor, a central processing unit (CPU), etc. The processor210may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, the processor210may be coupled to an extended bus such as peripheral component interconnect (PCI) bus. The memory device220may store data for operations of the electronic device200. For example, the memory device220may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc, and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device230may be a solid stage drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc.

The I/O device240may be an input device such as a keyboard, a keypad, a touchpad, a touch-screen, a mouse, etc, and an output device such as a printer, a speaker, etc. In some example embodiments, the display device260may be included in the I/O device240. The power device250may provide power for operations of the electronic device200. The display device260may communicate with other components via the buses or other communication links.

As described above, the display device260may include a display panel, a voltage generator, a timing controller, a gate controller, a gate driver, an over current protection circuit, an abnormal signal detector, and a data driver. The display panel may include a plurality of pixels. Each of the pixels may be coupled to gate lines and data lines. The voltage generator may receive a direct power from an external device and generate a plurality of voltages to drive the display panel. For example, the voltage generator may generate a gate driving voltage provided to the gate controller, a data driving voltage provided to the data driver, and a panel driving voltage provided to the display panel. The timing controller may receive a control signal from the external device and generate a clock control signal provided to the gate controller and a data clock signal provided to the data driver. Further, the timing controller may compensate a first image data provided from the external device to a second image data and provide the second image data to the data driver. The gate controller may generate gate clock signals based on the gate driving voltage and the clock control signal. The gate controller may receive the gate driving voltage that includes a gate on voltage and a gate off voltage from the gate generator. Further, the gate controller may receive the clock control signal from the timing controller. The gate controller may generate gate clock signals that swing between the gate on voltage and the gate off voltage based on the clock control signal. For example, the gate clock signals may include a clock signal and a clock bar signal. The gate driver may generate a gate signal based on the gate clock signals and provide the gate signal to the pixels through the gate line GL. The gate driver may include a plurality of stages. Each of the stages may sequentially output the gate signals synchronized with the gate clock signals. The over current protection circuit may detect a gate clock current corresponding to the gate clock signal and output a shutdown control signal that shuts down the voltage generator when the gate clock current is greater than a set or predetermined reference current. The abnormal signal detector may determine whether the clock control signal is abnormal based on a difference between a set or predetermined reference signal and the clock control signal, and output a delay control signal that delays an output timing of the shutdown control signal for a set or predetermined time when the clock control signal is abnormal. The clock control signal may be restored as time passes, although the clock control signal is temporarily abnormal due to an electrostatic surge, an electric surge, etc. The abnormal signal detector may delay the output timing of the shutdown control signal while the clock control signal is restored. Thus, the voltage generator may not be immediately shut down. The abnormal signal detector may determine whether the clock control signal is abnormal by comparing the reference signal to the clock control signal having a first level during a first period and comparing the reference signal to the clock control signal having a second level during a second period. The over current protection circuit may output the shutdown control signal after the set or predetermined time in response to the delay control signal provided from the abnormal signal detector, when the over current is detected. Thus, the voltage generator may not shut down when the abnormal signal is just temporarily provided.

As described above, the electronic device200ofFIG. 6may include the display device260that protects or prevents the voltage generator from immediately shutting down due to the temporary abnormal signal, by determining whether the clock control signal is abnormal and delaying the operation of the over current protection circuit when the clock control signal is abnormal. Thus, defects that occur due to the shutdown of the voltage generator may be reduced or prevented.

The present inventive concept may be applied to a display device and an electronic device having the display device. For example, the present inventive concept may be applied to a computer monitor, a laptop, a digital camera, a cellular phone, a smart phone, a smart pad, a television, a personal digital assistant (PDA), a portable multimedia player (PMP), a MP3 player, a navigation system, a game console, a video phone, etc.

Although exemplary embodiments of a gate driving device and a display device having the same have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it is to be understood that to a gate driving device and a display device having the same constructed according to principles of this invention may be embodied other than as specifically described herein. The invention is also defined in the following claims, and equivalents thereof.