Semiconductor package

A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based on and claims the benefit of priority to Korean Patent Application No. 10-2017-0174234 filed on Dec. 18, 2017 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package for a package-on-package (POP) structure.

BACKGROUND

Recently, a significant recent trend in the development of technologies related to semiconductor packaging is reducing in the overall size of a semiconductor package while maintaining performance of the semiconductor package. As an example, in fan-out semiconductor packaging, connection terminals may be redistributed outwardly of amounting region of a semiconductor chip, such that the connection terminals may be efficiently arranged and the fan-out semiconductor package may be maintained at a small size.

In a package-on-package (POP) structure that has been recently developed, many connection terminals (for example, I/Os) of an upper package and a lower package need to be connected to each other, and a second connection member such as an interposer is required in order to connect the connection terminals to each other.

SUMMARY

An aspect of the present disclosure may provide a semiconductor package of which an increase in a thickness due to introduction of a connection member such as an interposer may be suppressed.

According to an aspect of the present disclosure, a semiconductor package may be provided, in which a process and a structure are simplified by using a connection member manufactured in advance and a connection structure between redistribution layers of connection members disposed on and beneath a semiconductor chip is improved.

According to an aspect of the present disclosure, a semiconductor package may include: a first connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package, the first connection member including an insulating member and a first redistribution layer embedded in the insulating member and having exposed regions in the second surface; a semiconductor chip having an active surface having connection electrodes disposed thereon, and an inactive surface opposing the active surface in the stacking direction and disposed on the first connection member, the inactive surface facing the second surface of the first connection member; an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip; a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrode, through-vias penetrating through the second region of the encapsulant and connected to the exposed regions of the first redistribution layer, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias; and a second connection member having a first surface disposed on the encapsulant and a second surface opposing the first surface and including a third redistribution layer connected to the second redistribution layer.

According to another aspect of the present disclosure, a semiconductor package may include: a first connection member having a first surface and a second surface opposing each other, including an insulating member and a first redistribution layer embedded in the insulating member, and having holes formed in the second surface to be connected to portions of the first redistribution layer; a semiconductor chip having an active surface having connection electrodes disposed thereon and an inactive surface opposing the active surface and disposed on the first connection member so that the inactive surface faces the second surface of the first connection member; an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip; and a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the first redistribution layer through the holes of the first connection member, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection.

In addition, an ordinal number such as “first”, “second”, or the like, is used to distinguish one component from another component, and does not limit a sequence, importance, and the like, of the corresponding components. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

The term an “exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. For example, singular forms need to be interpreted as including plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the mainboard1010, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in oneself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not used in oneself, and is packaged and is used in an electronic device, or the like, in a package state.

The reason why semiconductor packaging is required is that there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the accompanying drawings.

Fan-In Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged, andFIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring toFIGS. 3 and 4, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection member2240may be formed depending on a size of the semiconductor chip2220on the semiconductor chip2220in order to redistribute the connection pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device, andFIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

Referring toFIG. 5, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, low melting point metal balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an outer side of the semiconductor chip2220may be covered with an encapsulant2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may be further formed on the connection member2140, and an underbump metal layer2160may be further formed in openings of the passivation layer2150. Low melting point metal balls2170may be further formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

In the present manufacturing process, the connection member2140may be formed after the encapsulant2130is formed outside the semiconductor chip2120. In this case, a process for the connection member2140is performed from the via connecting the redistribution layers and the connection pads2122of the semiconductor chip2120to each other and the redistribution layers, and the vias2143may thus have a width that decreases as they become to the semiconductor chip (see an enlarged region).

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in the case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through low melting point metal balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

A semiconductor package that uses an interposer manufactured in advance will hereinafter be described in detail with reference to the accompanying drawings.

FIG. 9is a side cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure.FIGS. 10A and 10Bare, respectively, a plan view (viewed from “T” ofFIG. 9) and a bottom view (viewed from “B” ofFIG. 9) illustrating the semiconductor package illustrated inFIG. 9.

Referring toFIG. 9, a semiconductor package100according to the present exemplary embodiment may include a first connection member130having a first surface130A and a second surface130B opposing each other and including a first redistribution layer135, a semiconductor chip120disposed on the second surface130B of the first connection member130, an encapsulant140disposed on the second surface130B of the first connection member130and covering the semiconductor chip120, and a second redistribution layer155disposed on the encapsulant140and connected to the first redistribution layer135. In addition, the semiconductor package100may further include a second connection member160having a first surface160A disposed on the encapsulant140and a second surface160B opposing the first surface160A and including a third redistribution layer165connected to the second redistribution layer155.

The first connection member130used in the present exemplary embodiment may include an insulating member (also referred to as an “insulating layer”) and the first redistribution layer135including a wiring pattern (also referred to as a “first wiring pattern”) embedded in the insulating member131and having exposed regions in the second surface130B. Portions of a region of the first redistribution layer135embedded in the insulating member131may be exposed in the second surface130B. This will be described in detail below with reference toFIG. 11.

The semiconductor chip120may have an active surface having a plurality of connection electrodes120P disposed thereon and an inactive surface opposing the active surface. The inactive surface of the semiconductor chip120and the second surface130B of the first connection member130may be bonded to each other using a bonding layer125.

The second redistribution layer155used in the present exemplary embodiment may be directly connected to the connection electrodes120P of the semiconductor chip120, and may connect the first redistribution layer135of the first connection member130and the third redistribution layer165of the second connection member160to each other. The encapsulant140may be divided into a first region140A covering the semiconductor chip120and a second region140B positioned in the vicinity of the semiconductor chip120.

The second redistribution layer155may include connection vias153penetrating through the first region140A of the encapsulant140and connected to the connection electrodes120P and through-vias154penetrating through the second region140B of the encapsulant140and connected to the exposed regions of the first redistribution layer135. In addition, the second redistribution layer155may include a second wiring pattern152disposed on the encapsulant140and connected to at least one of the connection vias153and the through-vias154. The third redistribution layer165may be connected to the connection vias153and the through-vias154through the second wiring pattern152.

The first passivation layer171may be formed on the first surface130A of the first connection member130. The first passivation layer171may have first openings O1defining regions of a plurality of pads P. The first openings O1may be formed to correspond to an array of connection terminals of another semiconductor chip and package to be disposed on the semiconductor package. The plurality of pads P may be formed using a metal such as Au, and be provided as pads fora connection to another package and chip.

Electrical connection structures185connected to the third redistribution layer165may be disposed on the second surface160B of the second connection member160. The electrical connection structure185may be connected to the third redistribution layer165through an underbump metallurgy (UBM) layer181. The second passivation layer172may be formed on the second surface160B of the second connection member160. The second passivation layer172may have second openings O2defining regions of the third redistribution layer165connected to the UBM layer181.

In the present exemplary embodiment, as illustrated inFIG. 10A, the plurality of pads P may have pads disposed in an array of 9×2 at each of both sides of the semiconductor package100. As illustrated inFIG. 10B, the electrical connection structures185is illustrated in an array of 10×10 except for a central region (4×4). The plurality of pads P and the electrical connection structures185may be divided into fan-in pads that overlap the semiconductor chip120and fan-out pads that do not overlap the semiconductor chip120.

The plurality of pads P may have an array corresponding to that of connection terminals of an upper semiconductor package mounted on the semiconductor package100, and the electrical connection structures185may be arrayed to correspond to connection terminals of a motherboard on which the semiconductor package100is to be disposed. The plurality of pads P and the electrical connection structures185may be formed to have various other numbers and be formed in various arrays depending on the upper semiconductor package and the motherboard.

As described above, the plurality of pads P and the electrical connection structures185may be connected to each other and may also be connected to the semiconductor chip120by the first and third redistribution layers135and165together with the second redistribution layer155.

In the present exemplary embodiment, vias and patterns constituting the first and third redistribution layers135and165and the second redistribution layer155may have characteristic structures by a unique process.FIG. 11is an enlarged view of part “A” of the semiconductor package illustrated inFIG. 9.

Referring toFIG. 11, the second wiring pattern152may have an integrated structure with the connection vias153and the through-vias154. In the present specification, a term “integrated structure” does not mean that two components are simply in contact with each other, but refers to a structure in which two components are formed integrally with each other using the same material by the same process. For example, the second wiring pattern152may be considered to have the “integrated structure” with the connection vias153and the through-vias154since they are formed simultaneously with the connection vias153and the through-vias154by the same plating process (see a process ofFIG. 13F). As described above, the connection vias153and the through-vias154may be formed of the same metal. In addition, the connection vias153and the through-vias154may have integrated structures with the second wiring pattern152.

The encapsulant140may be formed of the photosensitive material. As described above, the encapsulant140may cover the semiconductor chip120disposed on the second surface160B of the second connection member160, and desired first and second holes H1and H2may be formed by a precise drilling process (e.g. photolithography) using a photoresist in order to form the connection vias153and the through-vias154for the second redistribution layer155(seeFIG. 13E).

The first holes for the connection vias153may be formed from an upper surface of the encapsulant140toward the semiconductor chip120. Therefore, an area of a surface of the connection via153adjacent to the second connection member160may be greater than that of a surface of the connection via153adjacent to the first connection member130(or the semiconductor chip120). Likewise, since second holes H2for the through-vias154may be formed from the upper surface of the encapsulant140toward the second connection member160, an area of a surface of the through-via154adjacent to the second connection member160may be greater than that of a surface of the through-via154adjacent to the first connection member130.

The first redistribution layer135of the first connection member130may be embedded in the insulating member131, as described above. Openings h may be formed in the second surface130B of the insulating member131, and the first redistribution layer135may have the exposed regions through the holes h. The exposed regions of the first redistribution layer135may be connected to the through-vias154penetrating through the encapsulant140. The through-vias154used in the present exemplary embodiment may be formed through the openings h of the insulating member131as well as the second holes H2of the encapsulant140.

A case in which each of the insulating member131and the first redistribution layer135of the first connection member130used in the present exemplary embodiment includes a single layer is illustrated, but each of the insulating member131and the first redistribution layer135may include a plurality of layers (seeFIGS. 14 and 15).

In the second connection member160used in the present exemplary embodiment, the third redistribution layer165may include a plurality of third wiring patterns162and a plurality of vias163. In detail, the third redistribution layer165may include two third insulating layers161, third wiring patterns162each disposed on the two third insulating layers161, and vias163each connected to the third wiring patterns162. The vias163of the third redistribution layer165may include vias connecting the second redistribution layer155and the third wiring patterns162to each other and vias connecting third wiring patterns162disposed on different levels to each other. A case in which the third redistribution layer165includes two-layer redistribution structures is illustrated. However, the third redistribution layer165is not limited thereto, but may have single-layer or three-layer or more redistribution structures.

The third insulating layer161of the third redistribution layer165may be formed of a photosensitive insulating material such as a photoimagable dielectric (PID). An area of a surface of the via163of the third redistribution layer165adjacent to the first surface160A of the second connection member160may be smaller than that of a surface of the via163of the third redistribution layer165adjacent to the second surface160B of the second connection member160.

The respective components included in the semiconductor package100according to the present exemplary embodiment will hereinafter be described in more detail.

The first connection member130may be used as an interposer connecting upper and lower packages to each other (seeFIG. 12). As described above, the first connection member130used in the present exemplary embodiment may be manufactured in advance before the semiconductor chip120is mounted. The insulating layer131of the first connection member130may be formed of a photosensitive insulating material such as a PID. The material of the insulating layer131is not limited thereto, but may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin in which a reinforcement material such as a glass fiber and/or an inorganic filler is impregnated, for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. The first redistribution layer135may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), or alloys thereof, but is not limited thereto.

The semiconductor chip120may be bonded to the first connection member130through the bonding layer125such as an adhesive film, as described above, and be supported by the first connection member130. The first connection member130may include a heat dissipation structure HD disposed on the inactive surface of the semiconductor chip120. The heat dissipation structure HD may be provided by a metal pattern disposed on the same level as that of the wiring pattern of the first redistribution layer135, but is not limited thereto. In another example, the heat dissipation structure HD may be formed in a stack structure including a metal layer and vias.

The second connection member160may be configured to redistribute the connection electrodes120P of the semiconductor chip120. In the present exemplary embodiment, the second connection member160may redistribute several tens to several hundreds of connection electrodes120P of the semiconductor chip120having various functions together with the second redistribution layer155to physically and/or electrically connect the several tens to several hundreds of connection electrodes120P to an external apparatus through the electrical connection structures185. Particularly, in the connection electrodes120P to which the second redistribution layer155is connected, other metal connectors such as conductive bumps are not introduced, and the second redistribution layer155may be directly connected to pad electrodes of a bare chip. The second connection member160may be connected to the connection electrodes120P of the semiconductor chip120, and may support the semiconductor chip120together with the first connection member130.

The insulating layer161of the second connection member160may be formed of a photosensitive insulating material such as a PID resin. The third redistribution layer165may include a conductive material such as Cu, Al, Ag, Sn, Au, Ni, or alloys thereof.

As described above, the third redistribution layer165of the second connection member160may be electrically connected to the semiconductor chip120through the second wiring pattern152and the connection vias153, and the first redistribution layer135of the first connection member130may be electrically connected to the semiconductor chip120in a bypass manner through the through-vias154.

The encapsulant140may be configured to protect the semiconductor chip120. In the present exemplary embodiment, the encapsulant140may cover the semiconductor chip120, and may be formed in a region positioned in the vicinity of the semiconductor chip120between the first connection member130and the second connection member160. The encapsulant140used in the present exemplary embodiment may be formed of a photosensitive insulating material. As described above, the vias for the second redistribution layer155are formed by a lithography process using a photoresist, and may thus be precisely implemented.

The semiconductor package100according to the present exemplary embodiment may further include the first and second passivation layers171and172disposed, respectively, on the first connection member130and the second connection member160. The first and second passivation layers171and172may be configured to protect the first connection member130and the second connection member160, respectively, from external physical or chemical damage, or the like. A material of each of the first and second passivation layers171and172is not particularly limited. For example, a solder resist may be used as the material of each of the first and second passivation layers171and172.

The electrical connection structures185connected to the third redistribution layer165of the second connection member160may be configured to physically or electrically externally connect the semiconductor package100. For example, the semiconductor package100may be mounted on the motherboard of the electronic device through the electrical connection structures185, as described above.

For example, the electrical connection structures185may be formed of Cu, Al, Ag, Sn, Au, Ni, and one of combinations thereof or a low melting point alloy such as an Sn—Al—Cu alloy, but are not limited thereto, and the electrical connection structures185may have various structures such as lands, balls, pins, and the like.

At least one passive component190may be disposed on the second surface160B of the second connection member160, if necessary, and be connected to the third redistribution layer165. In the present exemplary embodiment, the passive component190may be disposed between the electrical connection structures185, but is not limited thereto.

As illustrated inFIG. 10B, some of the electrical connection structures185may be disposed in a fan-out region. A fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. An array (the number, an interval, or the like) of the electrical connection structures185is not particularly limited, but may be variously modified depending on a condition of an external apparatus on which the semiconductor package is to be mounted.

In the present exemplary embodiment, a case in which the electrical connection structures185are provided on only the second surface160B of the second connection member160is illustrated, but connection terminals similar to the electrical connection structures185may also be provided on the first connection member130, that is, the pads P, if necessary.

FIG. 12is a side cross-sectional view illustrating a semiconductor device300of a package-on-package (POP) structure including the semiconductor package100illustrated inFIG. 9.

Referring toFIG. 12, the semiconductor device300according to the present exemplary embodiment may include the semiconductor package100provided as a lower package and an upper package200disposed on the first surface130A of the first connection member130.

The upper package200may include a connection member210provided as a support substrate and having insulating layers211and redistribution layers215formed on the insulating layers211, a semiconductor chip220mounted on the connection member210, and an encapsulant240formed on the connection member210and encapsulating the semiconductor chip220.

The upper package200may be connected to the pads P of the lower package100using additional electrical connection structures285provided on the first surface130A of the first connection member130of the lower package100to constitute one module.

A package-on-package (POP) may reduce a thickness of the device, and significantly reduce signal paths. For example, in a case of a graphic processor (GPU), it is required to significantly reduce signal paths between the GPU and a memory such as a high bandwidth memory (HBM). To this end, the upper package200and the lower package100may be used as a POP structure by stacking the upper package200including the semiconductor chip220such as the HBM on the lower package100in which the semiconductor chip120such as the GPU is mounted.

FIGS. 13A through 13Gare cross-sectional views for describing main processes of a method of manufacturing the semiconductor package illustrated inFIG. 9.

Referring toFIG. 13A, the first connection member130including the first redistribution layer135may be formed on a carrier film110.

The carrier film110may be used as a support for forming the first connection member130and supporting the first connection member130in some processes. The carrier film110used in the present exemplary embodiment may be a copper clad laminate such as a DCF including an insulating layer101and a metal layer102. In another example, the carrier film110may be various types of known adhesive films. For example, the adhesive film may include a thermosetting adhesive tape of which adhesion is weakened by heat treatment, an ultraviolet-curable adhesive tape of which adhesion is weakened by ultraviolet ray irradiation, or the like.

The first connection member130may be obtained by forming the wiring pattern providing the first redistribution layer135on the carrier film110and forming the insulating member (131) (also referred to as the “insulating layer”) on the first redistribution layer135. In this case, the insulating layer131may be embedded in the first redistribution layer135. In addition, a portion of the wiring pattern corresponding to the semiconductor chip120may be provided as a heat dissipation pattern HD. In the present exemplary embodiment, the first passivation layer171may be formed on the carrier film110in advance before the first redistribution layer135is formed, and the first connection member130may be formed on the first passivation layer171.

The insulating layer131of the first connection member130may be formed of a photosensitive insulating material such as a PID. However, the insulating layer131is not limited thereto, but may include the other resins described above. A case in which first redistribution layer135of the first connection member130used in the present exemplary embodiment is formed in a single-layer wiring pattern structure is illustrated, but in another exemplary embodiment (seeFIGS. 14 and 15), the first redistribution layer135may be implemented in a two-layer or more wiring structure including a plurality of wiring patterns and a plurality of vias connected to the plurality of wiring patterns.

Then, referring toFIG. 13B, the openings h may be formed in the insulating layer131so that portions of a region of the first redistribution layer135are exposed.

The openings h formed in the present process may expose portions of the region of the first redistribution layer135toward the second surface130B of the first connection member130. The regions of the first redistribution layer135exposed by the openings h may be provided as regions that are to be connected to through-vias154(seeFIG. 13F). When the insulating layer131is formed of a photosensitive insulating resin, the present process may be performed by a photolithography process. In another exemplary embodiment, the present process of forming the openings h is not separately performed, and the insulating layer131may be opened in a process (seeFIG. 13E) of forming the second holes H2for the through-vias in the encapsulant140.

Then, referring toFIG. 13C, the semiconductor chip120may be mounted on the second surface130B of the first connection member130.

The semiconductor chip120used in the present exemplary embodiment may have the active surface having a plurality of connection electrodes120P disposed thereon and the inactive surface opposing the active surface. In the present process, the semiconductor chip120may be bonded to the first connection member130using the bonding layer125so that the inactive surface of the semiconductor chip120is in contact with the second surface130B of the first connection member130manufactured in advance.

Since the first connection member130includes the heat dissipation pattern HD disposed in a region corresponding to the inactive surface of the semiconductor chip120, heat generated from the semiconductor chip120may be easily dissipated outwardly through the heat dissipation pattern HD. Particularly, a portion of an underfill or the encapsulant140is not disposed between the first connection member130and the semiconductor chip120, which may contribute to reducing an entire thickness of the semiconductor package, and a distance between the semiconductor chip120and the heat dissipation pattern HD may be reduced to ensure effective heat dissipation.

Then, referring toFIG. 13D, the encapsulant140may be formed on the second surface130B of the first connection member130to encapsulate the semiconductor chip120.

The encapsulant140may be formed of the photosensitive insulating material. In the present exemplary embodiment, the encapsulant140may cover the semiconductor chip120, and may be formed in a region positioned in the vicinity of the semiconductor chip120on the first connection member130. The encapsulant140may be divided into the first region140A covering the semiconductor chip120and the second region140B positioned in the vicinity of the semiconductor chip120.

Then, referring toFIG. 13E, the first holes H1exposing the connection electrodes120P of the semiconductor chip120and the second holes H2exposing portions of the region of the first redistribution layer135may be formed in the encapsulant140.

In the present exemplary embodiment, the encapsulant140may be formed of the photosensitive insulating material, and a process of forming the holes may thus be precisely performed by a photolithography process. The first holes H1for the connection vias153and the second holes H2for the through-vias154may be simultaneously formed in the first region and the second region, respectively. The second holes H2for the through-vias154may be connected to portions of the region of the first redistribution layer135of the first connection member130through the openings h prepared in advance in the insulating layer131.

In the present process, the first holes H1and the second holes H2may be drilled from the upper surface of the encapsulant140, and side cross sections of the first and second holes H1and H2may thus tend to become narrow toward a downward direction. In the present exemplary embodiment, in the connection electrodes120P of the semiconductor chip120, other metal connectors such as conductive bumps are not introduced, and a separate planarization process for exposing the conductive bumps, or the like, may not be required.

Then, referring toFIG. 13F, the second redistribution layer155may be formed on the encapsulant140so that the first holes H1and the second holes H2are filled.

The second redistribution layer155may be formed by forming a photoresist layer on the encapsulant140, forming a photoresist pattern by a lithography process, performing a plating process, and then removing the photoresist pattern. The second redistribution layer155may include the connection vias153penetrating through the first region140A of the encapsulant140and connected to the connection electrodes120P and the through-vias154penetrating through the second region140B of the encapsulant140and connected to the first redistribution layer135.

In addition, the second redistribution layer155may include the second wiring pattern152disposed on the encapsulant140and connected to at least one of the connection vias (or the second vias)153and the through-vias154. The second wiring pattern152may be formed together with the connection vias153and the through-vias154. Resultantly, the second wiring pattern152may have the integrated structures with the connection vias153and the through-vias154. As described above, the connection vias153and the through-vias154may be formed of the same metal as that of the second wiring pattern152.

Then, referring toFIG. 13G, the second connection member160having the third redistribution layer165may be formed on the encapsulant140.

The third redistribution layer165may be connected to the second redistribution layer155. The third redistribution layer165may provide a backside redistribution structure together with the second redistribution layer155. Each of the insulating layers161may be formed of the photosensitive insulating material such as the PID, and the third redistribution layer165may be formed by the lithography process using the photoresist.

In detail, the third redistribution layer165may include the third wiring pattern162and the vias163formed using the two insulating layers161. Since the third wiring pattern162and the vias163related to the respective insulating layers161are formed by the same plating process, they may have an integrated structure. The third redistribution layer165may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), or alloys thereof.

The second passivation layer172may be formed on the second surface160B of the second connection member160using a material similar to that of the first passivation layer171, the second openings O2may be formed so that the third redistribution layer165is exposed, and the UBM layer181may then be formed. The carrier film may be removed, and the first openings O1may be formed in the first passivation layer171.

If necessary, the electrical connection structures185may be formed on the UMB layer181, and a required passive component190may be mounted to manufacture the semiconductor package100illustrated inFIG. 9.

The semiconductor package according to the present exemplary embodiment may be modified into various structures.

In the semiconductor package100according to an exemplary embodiment, a case in which the redistribution layer of the first connection member is formed of single wiring pattern is illustrated, but the redistribution layer of the first connection member may also be implemented by two more wiring patterns and vias (seeFIG. 14).

In addition, in the semiconductor package100according to an exemplary embodiment, the through-vias154disposed in the second region140B of the encapsulant140may be provided as vertical connection structures connecting the first and third redistribution layers135and165to each other. Alternatively, the vertical connection structures may be formed by introducing other structures such as a support member having a through-wiring structure (seeFIG. 15).

FIGS. 14 and 15are side cross-sectional views illustrating semiconductor packages according to various exemplary embodiments in the present disclosure.

Referring toFIG. 14, it may be understood that a semiconductor package100A according to an exemplary embodiment is similar to the semiconductor package100illustrated inFIGS. 9 through 11except that a first redistribution layer135′ of a first connection member130′ is formed in a multilayer structure. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package100illustrated inFIGS. 9 through 11unless explicitly described to the contrary.

The first redistribution layer135′ of the first connection member130′ used in the present exemplary embodiment may include a plurality of wiring patterns132aand132band a plurality of vias133connected to the plurality of wiring patterns132aand132b. The first redistribution layer135′ having such a multilayer structure may be implemented by a process similar to the process illustrated inFIG. 13A. That is, the first redistribution layer135′ may be manufactured by forming an additional wiring pattern on the insulating layer in the structure illustrated inFIG. 13Aand then forming an additional insulating layer on the wiring pattern. As described above, an insulating member of the first connection member may include two insulating layers. Since the first redistribution layer135′ is formed by such a process, a via133of the first redistribution layer135′ may have a specific shape depending on a direction thereof. That is, an area of a surface of the via133adjacent to a first surface130A of the first connection member130′ may be smaller than that of a surface of the via133adjacent to a second surface130B of the first connection member130′. In the present exemplary embodiment, the first connection member130′ is manufactured in advance before a semiconductor chip120is mounted, and a shape of the via may thus be reversed, if necessary.

The wiring pattern132aadjacent to the first surface130A of the first connection member may be embedded in an insulating layer131, portions of regions of the wiring pattern132amay be exposed by first openings O1of a first passivation layer171, and the exposed regions may provide regions for a plurality of pads P. The wiring pattern132badjacent to the second surface130B of the first connection member may also be embedded in the insulating layer131, but may be exposed toward the second surface130B of the first connection member, and exposed regions may be connected to through-vias154. A heat dissipation structure HD provided in the first connection member130may include two metal patterns provided on the same levels as those of two wiring patterns, and may include a plurality of vias connecting the two metal patterns to each other, if necessary.

Referring toFIG. 15, it may be understood that a semiconductor package100B according to an exemplary embodiment is similar to the semiconductor package100illustrated inFIGS. 9 through 11except that a vertical connection structure is implemented by a support member190having a through-wiring structure195. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package100illustrated inFIGS. 9 through 11unless explicitly described to the contrary.

A first connection member130″ used in the present exemplary embodiment may further include a connection pattern136disposed in a region of an encapsulant140′ positioned in the vicinity of a semiconductor chip120, connected to a first redistribution layer135, and protruding from a second surface of the first connection member130″. The connection pattern136may be formed in the process of manufacturing the first connection member illustrated inFIG. 13A.

In the present exemplary embodiment, the vertical connection structure may be provided by a support member190having a through-wiring structure195instead of being formed in a second region of the encapsulant140. The support member190may include an insulating support191, wiring patterns192aand192bdisposed on upper and lower surfaces of the insulating support191, respectively, and a via193connecting the wiring patterns192aand192bto each other. The insulating support190may be formed of the insulating material described above, and may be provided as a plurality of unit blocks or be a rectangular structure having a cavity formed in a mounting region of the semiconductor chip.

The support member190may be coupled to the semiconductor package100B in various manners. For example, in a process (seeFIG. 130) of attaching the semiconductor chip120to the first connection member130″, the support member190having the through-wiring structure may be disposed on the first connection member130″ in the vicinity of the semiconductor chip120, and the connection pattern136connected to the first redistribution layer135and the through-wiring structure195may be connected to each other. Then, the encapsulant140′ is formed, such that the support member190as well as the semiconductor chip120may be coupled to the first connection member130″. Particularly, the encapsulant140′ may be formed to cover the wiring pattern192bof the support member190, and holes exposing the wiring pattern192bof the support member190may be formed at the time of forming first holes H1opening the connection electrodes120P, as inFIG. 13E, and a third redistribution layer connected to the wiring pattern192bof the support member190may be formed in a subsequent process.

As set forth above, according to the exemplary embodiments in the present disclosure, a connection structure and a process may be simplified and a heat dissipation path for the semiconductor chip may be effectively improved, by utilizing the connection member manufactured in advance. In addition, the vertical connection structures of the redistribution layers may be manufactured together with a redistribution structure for the semiconductor chip by introducing the photosensitive material as a material of the encapsulant.