Offline converter with power factor correction at light loads and method therefor

In one form, a power factor correction (PFC) controller, comprising includes a regulation circuit, a dead-time detection circuit, and a pulse width modulator. The regulation circuit provides a control voltage in response to a feedback voltage received at a feedback input terminal, wherein the feedback voltage is proportional to an output voltage. The dead-time detection circuit has an input coupled to a zero current detection input terminal, and an output for providing a dead-time signal. The pulse width modulator is responsive to the control voltage and the dead-time signal to provide a drive signal that controls conduction of a switch to improve a power factor of an offline converter, wherein the pulse width modulator modulates both an on-time and a switching period of the drive signal using the dead-time signal in a discontinuous conduction mode.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to power conversion circuits, and more particularly to offline converters with power factor correction.

BACKGROUND

An off-line power converter can be implemented using an integrated circuit power factor correction (PFC) controller. The PFC controller helps to boost the efficiency of power transfer to the load by making the current and voltage waveforms in phase with each other. To reduce electromagnetic interference (EMI), a typical offline converter with a PFC controller operates in critical conduction mode (CrM) in which a new switching cycle begins when the current through an inductor of the PFC stage drops to zero. The instantaneous inductor current varies from zero to a value that is proportional to the line voltage, and the average inductor current follows the same wave-shape as the input voltage, thus providing no distortion or phase shift in the current waveform.

In PFC controllers, it is difficult to preserve efficiency and to simultaneously achieve near-unity power factor across the entire load range. One solution to this problem is known as frequency-clamped CrM. As the level of the load lightens, a CrM controller with frequency clamped CrM clamps the natural switching frequency to preserve high efficiency. Once the frequency is clamped, the PFC controller enters discontinuous conduction mode (DCM). The power factor drops as the frequency varies from the natural frequency due to the frequency clamping if no circuitry to compensate for the dead-times is implemented. With frequency-clamped CrM controllers that incorporate circuitry to compensate for the dead-times, the power factor remains high but some noise can be generated due hesitations between valleys, and some current bumps can be observed particularly at transitions between CrM and DCM operation.

Other PFC controllers use techniques such as valley-synchronized frequency foldback (VSFF) and current controlled frequency foldback (CCFF) that reduce the switching frequency at light loads by forcing some dead-time without providing a firm frequency clamp. These PFC controllers modulate on-time to compensate for dead times experienced in DCM. They achieve high power factor at light loads but do not firmly control the frequency range. They may also experience current bumps when switching between valleys or transitioning between CrM and DCM.

The use of the same reference symbols in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION

FIG. 1illustrates in partial block diagram and partial schematic form an off-line power converter100including an 8-pin integrated circuit power factor correction (PFC) controller160. Off-line power converter100generally includes a rectifier110, a transformer120, a drive transistor130labeled “Q1”, a sensing circuit140, an output circuit150, integrated circuit power factor controller160, a line sensing circuit170, a resistor180labeled “Rfb1”, a resistor182labeled “Rfb2”, a resistor184labeled “Rz”, a capacitor186labeled “Cz”, a capacitor188labeled “CP”, and a resistor190labeled “RFF”.

Rectifier110includes an electromagnetic interference (“EMI”) filter112, a diode114, a diode115, a diode116, a diode117, and a capacitor118labeled “Cin”. Rectifier110has an input terminal connected to a first “AC line” power supply terminal, an input terminal connected to a second AC line power supply terminal, an output terminal to provide a first power supply terminal, and an output terminal connected to ground, which serves as a reference voltage terminal for off-line power converter100. Diode114has an anode connected to the first power supply terminal provided by EMI filter112, and a cathode to provide a voltage labeled “Vin”. Diode115has an anode connected to ground, and a cathode connected to the anode of diode114. Diode116has an anode connected to the second power supply terminal provided by EMI filter112, and a cathode connected to the cathode of diode114. Diode117has an anode connected to ground, and a cathode connected to the anode of diode116. Capacitor118has a first terminal connected to the cathode of diode116, and a second terminal connected to ground. In an alternate configuration, the negative terminal of diode bridge110(the anodes of diodes115and117) can be connected to another node, for example to perform negative current sensing. In this case, a resistor is inserted in the current return path between the anodes of diodes115and117and the second terminal of capacitor118and ground. In this case, the common connection point of the anodes of diodes115and117is below zero when a current is flowing across the resistor. If ground is at zero volts, then the voltage at the negative terminal of diode bridge110is equal to negative the resistance of the resistor times the current through the primary winding of transformer120.

Transformer120includes a primary winding122labeled “L1”, a secondary winding124, and a transformer core126. Primary winding122has a first terminal to receive Vin, and a second terminal. Secondary winding124has a first terminal connected to ground, and a second terminal.

Drive transistor130has a gate electrode, a drain electrode connected to the second terminal of primary winding122, a source electrode, and a substrate electrode connected to the source electrode.

Sensing circuit140includes a diode142labeled “Dzcd”, a resistor144labeled “Rzcd”, a resistor146labeled “Rocp”, and a resistor148labeled “Rsense”. Diode142has an anode connected to the second terminal of secondary winding124, and a cathode. Resistor144has a first terminal connected to the cathode of diode142, and a second terminal. Resistor146has a first terminal connected to the second terminal of resistor144, and a second terminal connected to the source electrode of drive transistor130. Resistor148has a first terminal connected to the second terminal of resistor146, and a second terminal connected to ground.

Output circuit150includes a diode152labeled “Dl”, a bulk capacitor154labeled “Cbulk”, and a load156. Diode152has an anode connected to the drain electrode of drive transistor130, and a cathode to provide a voltage labeled “Vbulk”. Bulk capacitor154has a first terminal connected to the cathode of diode152, and a second terminal connected to ground. Load156has a first terminal connected to the first terminal of bulk capacitor154, and a second terminal connected to ground.

Integrated circuit power factor controller160has a first terminal, a second terminal, a third terminal, a fourth terminal connected to the first terminal of resistor146, a fifth terminal connected to ground, a sixth terminal connected to the gate electrode of drive transistor130, a seventh terminal to receive a power supply voltage labeled “VCC”, and an eighth terminal to receive a signal labeled “Feedback”.

Line sensing circuit170includes a resistor172labeled “RX1”, a resistor174labeled “RX2.”, a resistor176labeled “Rbo1”, and a resistor178labeled “Rbo2”. Resistor172has a first terminal connected to the first AC line power supply terminal, and a second terminal. Resistor174has a first terminal connected to the second AC line power supply terminal, and a second terminal connected to the second terminal of resistor172. Resistor176has a first terminal connected to the second terminal of resistor174, and a second terminal connected to the second terminal of integrated circuit power factor controller160. Resistor178has a first terminal connected to the second terminal of resistor176, and a second terminal connected to ground.

Resistor180has a first terminal to receive Vbulk, and a second terminal to provide the Feedback signal. Resistor182has a first terminal connected to the eighth terminal of integrated circuit power factor controller160, and a second terminal connected to ground. Resistor184has a first terminal connected to the first terminal of integrated circuit power factor controller160, and a second terminal. Capacitor186has a first terminal connected to the second terminal of resistor184, and a second terminal connected to ground. Capacitor188has a first terminal connected to the first terminal of resistor184, and a second terminal connected to ground. Resistor190has a first terminal connected to the third terminal of integrated circuit power factor controller160, and a second terminal connected to ground.

In operation, rectifier110provides a full-wave rectified voltage Vin with filtering between the power supply mains (AC line), and downstream circuitry of off-line power converter100. In particular, rectifier110manages the propagation of unwanted energy from the AC line to downstream circuits by passing the signals through EMI filter112. EMI filter112filters EMI interference so that downstream circuits are not disturbed during operation. EMI filter112receives the AC line signal and provides a filtered AC signal to its output terminals. Diodes114,115,116and117provide a rectified input voltage Vin, stored and filtered across capacitor118, to the downstream circuits of off-line power converter100.

For transformer120, a varying alternating current through primary winding122creates a varying magnetic flux in transformer core126of transformer120that results in a varying alternating voltage across primary winding122. By inductive coupling, the varying magnetic flux creates a varying magnetic field in the coils of secondary winding124. As is known, the voltage induced in secondary winding124is a mathematical function of the voltage across primary winding122and is defined by the ratio of the number of turns in secondary winding124to the number of turns in primary winding122.

During an on time (“TON”), integrated circuit power factor controller160pulls up terminal6to provide a positive drive voltage on the gate electrode of drive transistor130, which is an N-channel metal oxide semiconductor field effect transistor (“MOSFET”). Drive transistor130transitions to the “on state” and provides a low impedance current path to ground at the second terminal of primary winding122. Rectifier110provides IL, and ILflows through primary winding122, drive transistor130, and resistor148. Drive transistor130operates to lower the drain electrode voltage towards ground, and transformer120builds its magnetic field and stores energy as a function of IL.

Resistor148senses the current flowing through drive transistor130and provides a voltage level to terminal4of integrated circuit power factor controller160. Resistor148provides a positive voltage to terminal4as a function of the current flowing from the drain electrode to the source electrode of drive transistor130. If the voltage on terminal4exceeds a threshold, integrated circuit power factor controller160determines that drive transistor130is operating in an over current condition, and deactivates drive transistor130.

During an off (“TOFF”) time, integrated circuit power factor controller160pulls down terminal6to make drive transistor130nonconductive. Drive transistor130transitions to the “off state” and provides a high impedance current path at the second terminal of primary winding122. In response, primary winding122resists the changing IL, and operates to raise the voltage at the second terminal of primary winding122. Diode152turns on as a function of the voltage provided by primary winding122to provide ILto output circuit150and to increase Vbulk. Bulk capacitor154stores Vbulkacross load156as a function of IL, and filters high frequency voltage transitions across load156.

Also, secondary winding124operates to raise the voltage on the anode of diode142of sensing circuit140. Diode142turns on and enables current flow through resistors144,146, and148in response to the voltage induced in secondary winding124. Sensing circuit140provides a voltage to terminal4of integrated circuit power factor controller160to indicate when the magnetic field of secondary winding124is in a “demagnetization” phase by detecting when secondary winding124is providing zero current, known as zero current detection (“ZCD”). As a function of the voltage on terminal4, if integrated circuit power factor controller160detects ZCD, integrated circuit power factor controller160adjusts the operation of certain internal circuits. Secondary winding124and diode142operate to prevent interference between OCP detection, when drive transistor130is in the on state, and ZCD detection, when drive transistor130is in the off state.

Line sensing circuit170senses the instantaneous voltage of the AC line by dividing the AC line voltage as a function of the values of resistors172,174,176, and178. The second terminal of resistor176forms a voltage at terminal2of integrated circuit power factor controller160. If the voltage on terminal2is less than a threshold for a certain duration, such as a time longer than a half-line cycle, integrated circuit power factor controller160detects a brown-out condition and stops operation to prevent excessive stress.

Off-line power converter100provides Vbulkto the first terminal of resistor180to provide the Feedback signal as a function of the values of resistors180and182. The second terminal of resistor180forms a voltage at terminal8of integrated circuit power factor controller160. As a function of the voltage on terminal8, integrated circuit power factor controller160regulates the duty cycle of drive transistor130and disables it immediately if the output voltage is too high.

Integrated circuit power factor controller160provides a signal from the output of an internal error amplifier implemented as an operational transconductance amplifier used in the voltage regulation loop to terminal1. A circuit network formed by resistor184, capacitor186, and capacitor188and connected to terminal1adjusts the regulation loop bandwidth and phase margin.

Integrated circuit power factor controller160provides an output voltage at terminal3to resistor190to form a voltage as a function of the current provided by the AC line. As a function of the voltage on terminal3, integrated circuit power factor controller160adjusts the dead time and initiates cycle skipping. It is desirable for controller160to implement a control technique that maintains both high power factor and high efficiency across the entire load range, including light and very light loads.

FIG. 2illustrates in partial block diagram and partial schematic form a power factor correction (PFC) controller200known in the prior art that can be used in off-line power converter100ofFIG. 1. PFC controller200has a set of integrated circuit terminals including a feedback terminal201labeled “FB”, a current sense/zero current detection terminal202labeled “CS/ZCD”, and a drive terminal203labeled “DRV”. Connected to FB terminal201are resistors180and182as previously illustrated inFIG. 1.

PFC controller200includes generally a regulation block210, a capacitor212, a dead-time detection block220, an on-time processing block230, a comparator240, a latch250, and a driver260. Regulation block210has an input connected to feedback terminal201, and an output for providing a regulated control voltage labeled “VCONTROL”. Capacitor212has a first terminal connected to the output of regulation block210, and a second terminal connected to ground. Dead-time detection block220has an input connected to current sense terminal202, and an output for providing a dead-time detect signal labeled “DT”.

On-time processing block230has an input connected to the output of regulation block210, an input connected to the output of dead-time detection block220, and an output for providing an on-time voltage signal labeled “VTON”. On-time processing block230includes an amplifier231, a capacitor232, a resistor233, an inverter234, a switch235, and a switch236. Amplifier231has a non-inverting input connected to the output of regulation block210, an inverting input, and an output. Capacitor232has a first terminal connected to the output of amplifier231, and a second terminal connected to the inverting input of amplifier231. Resistor233has a first terminal, and a second terminal connected to the inverting input of amplifier231. Inverter234has an input connected to the output of dead-time detection block220, and an output. Switch235has a first terminal connected to the output of amplifier231, a second terminal connected to the first terminal of resistor233, and a control terminal connected to the output of inverter234. Switch236has a first terminal connected to the second terminal of switch235and to the first terminal of resistor233, a second terminal connected to ground, and a control terminal connected to the output of dead-time detection block220.

Comparator240has a negative input connected to the output of amplifier231, a positive input terminal for receiving a ramp signal, and an output. Latch250is an SR latch having a set input labeled “S” for receiving a clock signal labeled “CLK”, a reset input labeled “R” connected to the output of comparator240, and an output labeled “Q”. Driver260has an input connected to the output of latch250, and an output connected to terminal203.

In operation, PFC controller200provides the DRV output signal in response to its control algorithm. Regulation block210receives the feedback signal and provides VCONTROLin response to comparing the FB signal to a reference voltage and filtering the feedback signal for loop stability. Capacitor212can be an external capacitor connected to an integrated circuit terminal and whileFIG. 2shows it as a single capacitor for simplicity this capacitor is commonly formed as a capacitor in parallel with a series combination of a capacitor and a resistor. Moreover regulation block210can include circuitry to clamp VCONTROLto a particular value.

On-time processing block230modulates VCONTROLbased on the measured dead-time. Amplifier231and capacitor232form an integrator, and modulate VCONTROLbased on the ratio of the switching cycle period (on-time plus demagnetization time) over the total switching period including the dead-time, i.e. the duty cycle. When DT is inactive at a logic low, switch235is closed and switch236is open. For the period of time that DT is low, the first terminal of resistor233receives VTON. For the period of time that DT is active at a logic high, the first terminal of resistor233is connected to ground at zero volts. Thus the first terminal of resistor233receives on average a voltage equal to VTON*duty cycle. Comparator240compares the level of VTONto a fixed ramp voltage and the on-time of the DRV signal ends when the ramp signal exceeds VTON.

FIG. 3illustrates a timing diagram300of the input voltage and on-time of PFC controller200ofFIG. 2. In timing diagram300, the horizontal axis represents time in milliseconds (msec), the left vertical axis represents on-time in microseconds (μs), and the right vertical axis represents input voltage in volts. Timing diagram300shows two waveforms of interest, including a first waveform310showing input voltage VIN(t), and a second waveform320showing on time tON(t). As can be seen over a half line cycle of 10 ms in a system in which vIN(t) is a 50 hertz (Hz), 230 V RMS voltage, vIN(t) varies from 0.0 V at 0 ms to a peak of around 320 V at around 5 ms, back to 0 V at 10 ms. At the same time, tON(t) goes from about 3.40 μs at 0 ms down to about 1.50 μs at about 5 ms and up to about 3.40 μs at 10 ms. Thus on-time varies as the input power and AC line voltage vary within the haversine half cycle. This kind of tONvariation can result from clamping the switching frequency to a fixed value. In this case, the frequency clamp causes dead-times which are higher near the line zero crossing, thus causing higher tONbut substantially constant frequency.

In this way, PFC controller200modulates the on-time to compensate for the dead-time and tends to reduce the dead-time. This control technique achieves close to unity power factor in discontinuous conduction mode (DCM) and maintains light load efficiency, but also can significantly vary dead-time from one cycle to another when the valley at which the MOSFET turns on needs to be changed and suffers from a large variation in the averaged current and current bumps or “glitches”.

FIG. 4illustrates a timing diagram400showing three waveforms related to the switching of a PFC controller known in the prior art that can be used in off-line power converter100ofFIG. 1. InFIG. 4, the horizontal axis represents time in μs. Three waveforms are shown on the same time axis but with different vertical axes, including a waveform410showing the drain-to-source voltage (VDs) of transistor130in which the vertical axis represents amplitude in volts (V), a waveform420of the current through the primary winding of transformer120labeled “IL” in which the vertical axis represents current in amperes (A), and a waveform430showing an oscillator clock signal labeled “OSC CLOCK” in which the vertical axis represents amplitude in V.

Timing diagram400shows the operation of a PFC controller that uses a control technique known as valley synchronized frequency foldback (VSFF). Timing diagram400shows two switching cycles. The first switching cycle corresponds to a VDSwaveform segment412, an ILwaveform segment422, and an OSC CLOCK waveform segment432. As shown in timing diagram400, at about time t0, the OSC CLOCK waveform segment transitions to a logic low. The transition sets latch250, which activates the DRV signal. Transistor130becomes conductive, and its VDSdecreases to about 0 V. The de-activation of the OSC CLOCK signal initiates a cycle of the ramp signal (not shown inFIG. 4) and load current ILrises from t0to t1. At time t1, the ramp signal intersects VTON, which resets latch250and causes driver260to deactivate the DRV signal. Thus VDSrises after t1until boost diode152turns on. Load current ILfalls from t1to t2, transformer120becomes fully demagnetized at time t2, and the dead-time of this switching cycle begins. VDSand ILstart ringing, with a valley in the VDSwaveform occurring at times t3, t5, and t7. According to the level of VFB, PFC controller200detects the third valley and de-activates the OSC CLOCK signal at time t7, starting another switching cycle.

The second switching cycle corresponds to a VDSwaveform segment414, an ILwaveform segment424, and an OSC CLOCK waveform segment434. In the second switching cycle, the load is larger. As shown in timing diagram400, the OSC CLOCK waveform segment transitions to a logic low at about time t10. The transition sets latch250, which activates the DRV signal. Transistor130becomes conductive, and its VDSdecreases to about 0 V. The de-activation of the OSC CLOCK signal initiates a cycle of the ramp signal that rises in voltage from times t10to t12, passing time t11that corresponds to the level of VTONduring the first switching cycle. At time t12, the ramp signal intersects the increased value of VTON, which resets latch250and causes driver260to deactivate the DRV signal. VDSrises after t12until boost diode152turns on. When transformer120becomes fully demagnetized at time t14, IL=0 A and the dead-time of this switching cycle begins. Note that the time from t12to t13corresponds to the length of the demagnetization time in the first switching cycle. VDSand ILstart ringing, with a valley in the VDSwaveform occurring at times t15and t17. According to the level of VFB, PFC controller200detects the second valley instead of the third valley because the load has gotten heavier. It de-activates the OSC CLOCK signal at time t17, starting another switching cycle.

Between the first and second switching cycles, the cycle time (on-time plus demagnetization time) increases, while the switching period decreases somewhat and the dead-time decreases significantly. The OSC CLOCK is generated a fixed amount of time after the DRV pulse goes high. A small increase in the on-time causes the second valley to be the first valley detectable while the OSC CLOCK signal is high during the second switching cycle, while the third valley was the first valley detectable when the OSC CLOCK signal is high during the first switching cycle. Thus, the on-time is longer leading a higher peak and in addition, due to the synchronization to a valley, the dead-time is reduced. These two effects cause a large variation in averaged current, which will now be described.

FIG. 5illustrates a timing diagram500showing four signal waveforms caused by switching of PFC controller200ofFIG. 2. In timing diagram500, the horizontal axis represents time in μs and the vertical axis represents voltage or current as the case may be. Timing diagram500shows four signals of interest, including a waveform510showing voltage VBULK, a waveform520showing line current in A, a waveform530showing input voltage VIN, and a waveform540showing frequency foldback control pin voltage that appears on the third terminal of integrated circuit power factor controller160inFIG. 1.

VINis a full-wave rectified sinusoidal line voltage, i.e. a haversine. The minima of the haversine correspond to minima of the FFCONTROLvoltage and zero crossings of the input line voltage. Thus when the FFCONTROLsignal goes low, it corresponds to a low line voltage. Waveform520shows that as the FFCONTROLpin voltage rises as VINrises in each half cycle, PFC controller200enters CrM and these transitions cause undesirable current glitches550and560and similar glitches to occur.

FIG. 6illustrates in partial block diagram and partial schematic form a PFC controller600that can be used in off-line power converter100ofFIG. 1according to various embodiments. PFC controller600has a set of integrated circuit terminals including a feedback terminal601(FB), a current sense/zero current detection terminal602(CS/ZCD), and a drive terminal603(DRV). Connected to FB terminal are resistors180and182as previously illustrated inFIG. 1.

PFC controller600includes generally a regulation block610, a capacitor612, a dead-time detection block620, and a pulse width modulation (PWM) circuit640. Regulation block610has an input connected to feedback terminal201, and an output for providing regulated voltage VCONTROL. Capacitor612has a first terminal connected to the output of regulation block610, and a second terminal connected to ground. Dead-time detection block620has an input connected to current sense terminal602, and an output for providing dead-time detect signal DT.

Pulse width modulation (PWM) circuit640includes a ramp control circuit650, a comparator660, a latch670, and a driver680. Ramp control circuit650includes a ramp generator652, a valley detection circuit654, and a clock generator656. Ramp generator652has a first input connected to the output of dead-time detection block for receiving the DT signal, an input for receiving a clock signal labeled “CLK”, a second input for receiving an end-of-cycle signal labeled “tCYCLE”, and an output for providing a ramp signal labeled “VRAMP”. Valley detection circuit654has a first input connected to pin602for receiving a zero current detect signal labeled “ZCD”, a second input for receiving drive signal DRV, a first output connected to the second input of ramp generator652for providing the tCYCLEsignal, and a second output for providing a detected valley signal labeled “VALLEY”. Clock generator656has a first input for receiving the VRAMPsignal, a second input for receiving the VALLEY signal, and an output for providing the CLK signal.

Comparator640has a negative input for receiving the VCONTROLsignal, a positive input connected to the output of ramp generator652for receiving the VRAMPsignal, and an output. Latch670is an SR latch having a set input (S) for receiving the CLK signal, a reset input (R) connected to the output of comparator660, and an output (Q). Driver680has an input connected to the output of latch670, and an output connected to terminal603.

In operation, PFC controller600operates similarly to PFC controller200ofFIG. 2, except that it uses a different control technique. As the load lightens, the switching frequency rises. Like frequency-clamped controllers, PFC controller600prevents the switching frequency from exceeding the preset level. It modulates both the on-time and the switching period of the DRV signal using the DT signal in a discontinuous conduction mode without substantially changing the dead-time. In this way, unlike PFC controller200ofFIG. 2, PFC controller600provides a firm frequency clamp and avoids the possible noise and current glitches of PFC controllers operating in DCM, while maintaining near-unity power factor and high efficiency across widely varying load conditions.

FIG. 7illustrates a timing diagram700showing the ramp voltage and the primary current generated by PFC controller600ofFIG. 6when operating in DCM. InFIG. 7, the horizontal axes represent time in μsec, and the vertical axes represent different quantities. A top portion of timing diagram700shows a waveform710of a ramp signal vRAMP(t) and the vertical axis represents amplitude in V. A bottom portion of timing diagram700shows a waveform720of a current signal iL(t) and the vertical axis represents amplitude in A. Timing diagram700shows five times of interest including times t1-t5.

Timing diagram700shows two consecutive switching cycles. At time t1, a first switching cycle begins. Ramp generator652is reset and vRAMP(t) is initially 0 volts. vRAMP(t) increases at a first slope. iL(t) increases until vRAMP(t) equals VCONTROL, at which point the on-time ends and the demagnetization phase begins. The demagnetization phase continues until vRAMP(t) reaches VCYCLEand iL(t)=0 at time t2. The time period between t1and t2defines the cycle time tCYCLE. After t2, PFC controller600operates in a dead-time period. In the dead-time period, vRAMP(t) continues to increase but its slope is higher. Thus ramp generator652generates vRAMP(t) as a two-slope ramp and compensates the slope for the dead-time. iL(t) remains at 0 during the dead time. Eventually vRAMP(t)=VCLAMP, which ends the current switching cycle and starts a second switching cycle. At time t3, the second switching cycle begins. Waveform720exhibits the same on-time, demagnetization time, cycle time, and dead time during the second cycle.

The slope of waveform710during tCYCLEin DCM depends on the sensed dead-time. However the slope of waveform710during dead time is not affected by the modulation provided by the circuit compensating for dead-times. Thus, since VCLAMPdoes not change and since it will be seen that VCYCLEis not affected by the ramp slope, tDTis not changed by the modulation provided by the circuit compensating for dead-times.

At t3, ramp generator652is again reset and vRAMP(t) is also reset 0 volts. vRAMP(t) and iL(t) increase until vRAMP(t) equals VCONTROL, at which point the on-time ends and the demagnetization phase begins. The demagnetization phase continues until vRAMP(t) reaches VCYCLEand iL(t)=0 at time t4. The time period between t3and t4defines the cycle time tCYCLE. After t4, the converter operates in a dead time period. In the dead-time period, vRAMP(t) continues to increase but its slope increases to the same slope as in the first switching cycle. iL(t) remains at 0. Eventually vRAMP(t)=VCLAMP, at time t5which ends the new switching cycle and starts a third switching cycle.

If the load increased such that Vcycleexceeded Vclampand hence the PFC controller600operated in CrM, vRAMP(t) would have the shape shown by a first phantom waveform712with a single, increased slope. Phantom waveform712shows the on-time which would be obtained when vRAMP(t) crosses VCONTROLif the ramp slope was not reduced until vRAMP(t) reaches Vcycle, which highlights the change in the on-time labeled “ΔtON”. A second phantom waveform722shows iL(t) which would result from the shorter on-time if the ramp slope was not reduced until vRAMP(t) reaches Vcycle.

According to the disclosed embodiments, however, the charging current which determines the slope of vRAMP(t) during the cycle time is scaled according to the dead time, that is the proportion of dead-time as a percentage of the switching period. The on-time depends on the ramp current as follows:

tON=CRAMP*VCONTROLIRAMP[1]
in which tONis the on-time of transistor130, CRAMPis the capacitance of a ramp capacitor, VCONTROLis the control voltage that is based on the FB signal, and IRAMPis the ramp current that is driven onto the terminal of the ramp capacitor. The off-time is linked to the on-time as follows:

tOFF=tON*VIN⁡(t)VOUT-VIN⁡(t)[2]
Thus the cycle duration is:

tCYCLE=tON+tOFF=tON*VOUTVOUT-VIN⁡(t)=CRAMP*VCONTROLIRAMP*VOUTVOUT-VIN⁡(t)[3]
The ramp voltage VCYCLEwhen the current cycle ends is:

tDT=IRAMP⁢⁢0CRAMP*(VRAMP,PK-VCYCLE)=IRAMP⁢⁢0CRAMP*(VRAMP,PK-VCONTROL*VOUTVOUT-VIN⁡(t))[5]
in which VRAMP,PKis VCLAMPofFIG. 7. Thus according to equation [5], the dead time is constant at fixed input and output voltages.

FIG. 8illustrates a timing diagram800showing three signal waveforms related to the switching of PFC controller600ofFIG. 6. InFIG. 8, the horizontal axis represents time in μs. Three waveforms are shown on the same time axis but with different vertical axes, including a waveform810showing the VDSof transistor130in which the vertical axis represents amplitude in V, a waveform820of current ILthrough the primary winding of transformer120in which the vertical axis represents current in A, and a waveform830showing the OSC CLOCK signal in which the vertical axis represents amplitude in V.

Timing diagram800shows the operation of a PFC controller according to an embodiment that uses valley synchronized frequency foldback. Timing diagram800shows two switching cycles. The first switching cycle corresponds to a VDSwaveform segment812, an ILwaveform segment822, and an OSC CLOCK waveform segment832. As shown in timing diagram800, at about time t0, the OSC CLOCK waveform segment transitions to a logic low. The transition sets latch670, which activates the DRV signal. Transistor130becomes conductive, and its VDSdecreases to about 0 V. The de-activation of the OSC CLOCK signal initiates a cycle of a ramp signal and load current ILrises from t0to t1. At time t1, the ramp signal intersects VCONTROL, which resets latch670and causes driver680to deactivate the DRV signal. Thus VDSinitially rises after t1until the boost diode turns on. Load current ILfalls from t1to t2and transformer120becomes fully demagnetized at time t2and the dead-time of this switching cycle begins. VDSand ILstart ringing, with a valley in the VDSwaveform occurring at times t3, t5, and t7. According to the level of VFB, PFC controller600detects the third valley and de-activates the OSC CLOCK signal at time t7, starting another switching cycle.

The second switching cycle corresponds to a VDSwaveform segment814, an ILwaveform segment824, and an OSC CLOCK waveform segment834. In the second switching cycle, the load is smaller. As shown in timing diagram400, the OSC CLOCK waveform segment transitions to a logic low at about time t10. The transition sets latch670, which activates the DRV signal. Transistor130becomes conductive, and its VDSdecreases to about 0 V. The de-activation of the OSC CLOCK signal initiates a cycle of a ramp signal that rises in voltage from times t10to t13, passing time t11that corresponds to the level of VCONTOLduring the first switching cycle. At time t11, the ramp signal intersects VCONTOL, which resets latch670and causes driver680to deactivate the DRV signal. VDSinitially rises after t11. When transformer120becomes fully demagnetized at time t13, IL=0 A and the dead-time of this switching cycle begins. Note that the time from t12to t13corresponds to the additional length of the demagnetization time compared to the first switching cycle due to the lightening of the load. At time t13, VDSand ILstart ringing, with three valleys again occurring in the VDSwaveform. According to the level of VFB, PFC controller600again detects the third valley even though the on-time was made longer due to the modulation of the circuit to compensate for dead-times. PFC controller600de-activates the OSC CLOCK signal at time t19, starting another switching cycle.

Between the first and second switching cycles, the on-time, demagnetization time, and cycle time increase, but the dead-time remains constant or substantially constant and the switching stays at the third valley. The constant or substantially constant dead-time keeps the average current waveform smooth, avoiding the current glitches with known control methods.

FIG. 9illustrates a graph900showing charge current modulation according to a first embodiment of the ramp generator652ofFIG. 6. In graph900, the horizontal axis represents the ratio of VCYCLEto VCLAMPin percent (%), and the vertical axis represents charge current ICHnormalized with respect to the nominal charge current at full load ICH0. A first waveform910represents an ideal theoretical characteristic defined by the following equation:

To approximate waveform910, a second waveform920can be used and can be practically implemented. Waveform920is a 2-segment, piecewise linear approximation of waveform910.

In this case, as VCYCLE/VCLAMPapproaches 0%, ramp generator652maintains a small or “minimum” charge current of about 0.04*ICH0. As VCYCLE/VCLAMPvaries from slightly above 0% to about 25%, ICHvaries from the minimum charge current to about 0.5*ICH0. As VCYCLE/VCLAMPincreases from about 25% to 100%, ICHvaries from about 0.5*ICH0to ICH0. As can be seen inFIG. 9, by using waveform920the error is small across the entire load range. However if greater accuracy is desired, the number of segments can be increased.

FIG. 10illustrates in partial block diagram and partial schematic form a ramp generator circuit1000that can be used as ramp generator652ofFIG. 6according to the first embodiment. Ramp generator circuit1000includes a sample and hold circuit1010labeled “S/H”, a ramp current processing circuit1020, a transistor1030, a timing capacitor terminal1040, and a timing capacitor1050. Sample and hold circuit1010has a signal input for receiving VRAMP, a clock input for receiving tCYCLE, and an output for providing voltage VCYCLE. Ramp current processing circuit1020has a first input connected to the output of sample and hold circuit1010for receiving VCYCLE, a second input for receiving ICH0, a third input for receiving VCLAMP, and an output for providing current ICH. Transistor1030is an N-channel MOS transistor having a drain connected to the output terminal of ramp current processing circuit1020, a gate for receiving the CLK signal, and a source connected to ground. Timing capacitor terminal1040is connected to the output of ramp current processing circuit1020and to the drain of transistor1030. Capacitor1050has a first terminal connected to timing capacitor terminal1040, and a second terminal connected to ground.

In operation, sample and hold circuit1010captures the value of VRAMPwhen the current cycle ends to form VCYCLE. Ramp processing circuit1020then forms charge current ICHfor the next cycle according to VCYCLE. For example as shown inFIG. 9, the value of ICHcan be set according to the two-segment piecewise linear approximation of equation [6]. Alternatively, the approximation of

VCYCLEVCLAMP
can be formed with more than two segments to achieve a better approximation. ICH0and VCLAMPare constants. The second input to ramp current processing circuit1020could either be an actual current, or a voltage that represents the level of ICH0.

The inventors have discovered that using the relationship shown inFIG. 9and the circuit ofFIG. 10provides a firm frequency clamp and the current waveform does not exhibit significant current glitches like current glitches550and560ofFIG. 5when transitioning between CrM and DCM.

FIG. 11illustrates in partial block diagram and partial schematic form a ramp current generator1100circuit that can be used in ramp generator652ofFIG. 6according to a second embodiment. Ramp generator1100includes generally a current source1110, a resistor1120, a dead-time modulator1130, a resistor-capacitor (RC) filter1140, an amplifier1150, and a resistor1160. Current source1110has a first terminal connected to VCC, and a second terminal, and conducts a current labeled “IRAMP0”. Resistor1120has a first terminal connected to the second terminal of current source1110, and a second terminal connected to ground.

Dead-time modulator1130includes a switch1132, a switch1134, and a resistor1136. Switch1132has a first terminal connected to the second terminal of current source1110and the first terminal of resistor1120, a second terminal connected to ground, and a control terminal. Switch1134has a first terminal connected to the control terminal of switch1132, a second terminal connected to ground, and a control terminal for receiving a signal labeled “FAULT”. Resistor1136has a first terminal connected to the control terminal of switch1132and the first terminal of switch1134, and a second terminal for receiving the DT signal.

RC filter1140includes a resistor1142and a capacitor1144. Resistor1142has a first terminal connected to the second terminal of current source1110and the first terminal of resistor1120, and the first terminal of switch1132, and a second terminal. Capacitor1144has a first terminal connected to the second terminal of resistor1142, and a second terminal connected to ground.

Amplifier1150has a non-inverting input connected to the second terminal of resistor1142and the first terminal of capacitor1144, an inverting input, and an output connected to the inverting input thereof. Resistor1160has a first terminal connected to the output of amplifier1150, and a second terminal connected to ground, and conducts a current labeled “IR2”. If ramp generator uses a capacitor to generate VRAMPlike capacitor1050ofFIG. 10, it would further include a current mirror to mirror IR2or a multiple or fraction of IR2into the first terminal of the capacitor, but these elements are not shown inFIG. 11for ease of discussion.

In operation, current source1110generates IRAMP0as a current that is equal to or proportional to ICH0. Assuming there is no fault (FAULT=0), the voltage at the input of RC filter1140is IRAMP0*R1120when DT is low, and 0 otherwise, in which R1120is the resistance of resistor1120. RC filter1140operates as a lowpass filter that forms the time average of these two values and provides the time average to the non-inverting input of amplifier1150. Amplifier1150is configured as a voltage follower and thus provides the same time average on its output. Thus if resistor1160and resistor1120have the same value, IR2is the current through resistor1160that makes the voltage on the first terminal of resistor1160equal to IRAMP0modulated by the duty cycle.

Mathematically, the voltage at the non-inverting input of amplifier1150is equal to:

R1120*IRAMP⁢⁢0*TSW-tDTTSW=R1120*IRAMP⁢⁢0*dCYCLE[7]
in which TSWis the switching period, tDTis the dead-time, and dCYCLEis the duty cycle (where dCYCLEis the relative current cycle duration tON+tDEMAGor tCYCLEover the switching period TSWand dCYCLE=tCYCLE/TSW).

Current IR2is the modulated ramp current and can be expressed as:

Thus ramp current generator1100generates a ramp current modulated by the duty cycle using a ramp current generator circuit that is compact and easy to implement. It can be used by PFC controller600to continue to provide high efficiency during light load conditions by preventing the frequency from exceeding a preset level, compensating for the dead-times without substantially changing their duration, and without exhibiting significant current glitches.

Thus various embodiments of a PFC controller and an offline converter implementing PFC have been described. The PFC controller, such as PFC controller600ofFIG. 6, can be used in an offline controller with PFC like offline power converter100ofFIG. 1. Instead of varying dead-time to clamp or reduce the switching frequency during light-load conditions, the PFC controller uses a two-slope ramp which offers a firm frequency clamp. The slope of the first portion of the ramp is modulated to compensate for the dead-times resulting from the input voltage, output voltage, and control voltage conditions. The slope of the second portion that occurs during the dead-time is constant or substantially constant. The compensation for the dead-times thus results in no substantial variation of the dead-time. In one particular embodiment, a ramp current processing circuit determines the ramp current to define the first portion of the slope based on full load current and the value of the ramp signal at the end of the previous current cycle time. In another particular embodiment, the ramp current is modulated based on dead-time during the cycle time.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. For example, different techniques of compensating for the dead-times without changing substantially changing the dead-time duration during DCM are possible. In one technique, a ramp current that determines both the on-time and the cycle time of the power factor correction transistor is modulated based on the full-load current, the cycle time, and the clamp voltage. The modulation can performed by a two-segment approximation of a piecewise approximation of an ideal waveform, but in other embodiments more segments can be used to achieve an approximation closer to the ideal characteristic. In another embodiment, a dead-time signal directly modulates the ramp current during the cycle time. The light-light load control technique can be combined with other circuits in a single integrated circuit. For example, the integrated circuit can include any of a variety of well-known protection features. It can also be combined with a primary side flyback controller to achieve high integration and low cost offline converter.

Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.