Infrared detector array

An infrared detector array having a plurality of infrared detectors arranged in a matrix of rows and columns in a first semiconductor body; and, a plurality of integration/read circuits arranged in a matrix of rows and columns in a second semiconductor body, each one of the plurality of integration/read circuits being in vertical registration with, and electrically connected to, a corresponding one of the plurality of detectors. Each one of the integration/read circuits includes: a capacitor; a first transistor, electrically coupling the capacitor and the corresponding one of the detectors during an integration mode, for enabling current generated in the detector in response to impinging radiation to pass from the detector to the capacitor for integration; and a second transistor, electrically coupling the charge built-up on the capacitor during the integration mode to an output bus during a subsequent read mode. A reset circuit, laterally displaced from the integration/read circuitry, is coupled to the output bus, for discharging the charge built-up on the capacitor during the integration mode and for discharging charge generated in the detector during a subsequent reset mode.

BACKGROUND OF THE INVENTION 
This invention relates generally to infrared detector arrays and more 
particularly to infrared detector array structures wherein the array of 
infrared detectors and associated electronic detector integration/read 
circuits are formed as a hybrid integrated circuit. 
As is known in the art, infrared detectors are used in a wide range of 
applications. In one application, an array of the detectors are used as 
sensors to detect the infrared energy emitted by objects in a scene under 
observation. Each detector generates an electrical charge in response to 
the portion of the emitted energy it detects. Circuitry is provided for 
converting the generated charge into a corresponding electrical signal. 
The electrical signals are combined by a processor which produces a 
corresponding visual image of the observed scene. Thus, each detector 
provides the data for a corresponding pixel of the produced visual image. 
In one arrangement, an optical system focuses the emitted infrared energy 
into a corresponding image on the focal plane of the optical system. The 
infrared detectors are formed as an array of electrically isolated 
photo-diode detectors along one surface of a semiconductor chip, typically 
a chip of InSb or HgCdTe. The chip is disposed on the focal plane. Each 
photo-diode detector in the array generates an electrical current 
representative of the amount of infrared power focused onto it. The 
current is integrated by an integration circuit, typically a capacitor 
during an integration mode, to produce an electrical signal representative 
of the infrared energy impinging the photo-diode detector. The integrated 
signal is read out and passed to the processor during a subsequent read 
mode. Finally, any residual charge generated in the photo-diode detector, 
as well as the charge built-up on the capacitor, are removed before the 
next address cycle during a reset mode. 
In one arrangement, the integration/read circuit, as well as a reset 
circuit, is formed as an integrated circuit in a second semiconductor 
chip, typically Si. More particularly, an array of integration/read 
circuit, as well as the reset circuits, is arranged in a matrix of rows 
and columns formed in the second semiconductor chip. Each one of the 
circuits is disposed in vertical alignment, or registration with, and is 
electrically connected to, a corresponding one of the photo-diode 
detectors. Thus, the first and second semiconductor chips are disposed in 
overlaying parallel planes. This arrangement allows for the direct 
electrical connection between each photo-diode detector and its associated 
integration/read circuit, as well as its associated reset circuit. An 
exemplary one of the circuits is shown in FIG. 1 as circuit 10'. 
The exemplary circuit 10' is shown connected to a photo-diode detector 12'. 
The diode detector 12' is formed in a region 13' of the first 
semiconductor chip 14', and the circuit 10' is formed in a region 16' of 
the second semiconductor chip 18'. It is noted that the region 16' of 
second chip 18' where the circuit 10' is formed in vertical alignment with 
the region 13' where the diode detector 12' is formed in the first 
semiconductor chip 14'. The circuit 10' includes five field effect 
transistors, F.sub.1, F.sub.2, F.sub.3, F.sub.4, and F.sub.5, arranged as 
shown, and a capacitor C'.sub.int. During all three modes (i.e., the 
integration mode, the read mode, and the reset mode), a bias voltage, 
V.sub.bias, is applied to the gate electrode of transistor F.sub.4 to bias 
such transistor F.sub.4 into conduction, for reasons to be discussed. 
Further, the circuit 10' is supplied by a drain voltage supply V.sub.dd 
and a source voltage supply V.sub.ss, as indicated. During the integration 
mode, transistor F.sub.1 is switched "on" by a set voltage, V.sub.set, fed 
to the gate electrode thereof, while transistors F.sub.3 and F.sub.2 are 
switched "off" by V.sub.reset and V.sub.read logic signals fed to the gate 
electrodes of transistors F.sub.3 and F.sub.2, respectively. Thus, charge 
generated in the photo-diode detector 12' in response to impinging 
infrared radiation is fed, via transistors F.sub.1 and F.sub.4, to the 
capacitor C.sub.int for integration. Therefore, during this integration 
mode, transistors F.sub.1 and F.sub.4 are in conducting conditions, and 
transistors F.sub.2 and F.sub.3 are in non-conducting conditions. After a 
predetermined integration time, transistor F.sub.2 is switched "on". The 
voltage built-up by capacitor C.sub.int and the gate electrode capacitance 
of transistor F.sub.5 produces a corresponding voltage on the source 
electrode of such transistor. When transistor F.sub.2 is switched "on" 
during the read mode, the voltage on the source electrode of transistor 
F.sub.5 produces a corresponding voltage on the source electrode of the 
transistor F.sub.2 which is coupled to an output bus 19'. During the 
subsequent reset mode, a V.sub.reset logic signal is fed to the gate 
electrode of transistor F.sub.3 to place such transistor in an "on" 
condition while the logic signal V.sub.read on the gate electrode of 
transistor F.sub.2 turns such transistor F.sub.2 to an "off" condition. 
Therefore, during the reset mode, charge built-up on the capacitor 
C.sub.int discharges to V.sub.ss through the source and drain electrodes 
of transistor F.sub.3. Likewise, any charge generated in the photo-diode 
detector 12' is also discharged to V.sub.ss through the source and drain 
electrodes of transistors F.sub.1, F.sub.3, and F.sub.4. It is noted that 
because of the bias on transistor F.sub.4 switching transients coupled 
through any parasitic gate-drain capacitance of transistor F.sub.3 and 
remaining channel charge of transistor F.sub.3 (and appearing on the drain 
of such transistor F.sub.3) is attenuated prior to passing to the diode 
detector 12'. That is, transistor F.sub.4 acts as a buffer, or isolation 
device, and attenuates transients resulting from a change in the 
V.sub.reset logic state of the signal on the gate of transistor F.sub.3 
from passing to the diode detector 12'. The voltage on the gate electrode 
of transistor F.sub.1 is selected to not only place such transistor 
F.sub.1 in a conducting condition; but, as noted above, is also selected 
to apply an appropriate reverse bias voltage to the diode detector 12'. 
Since the circuit 10' is formed in the region 16' of the silicon chip 18' 
disposed in vertical alignment with the diode detector device 12' 
connected to it, in order to reduce the amount of spacing between adjacent 
photo-diode detectors (and thereby increase array resolution), or 
alternatively, in order to increase the size of the integration capacitor 
C.sub.int used in the circuit (and thereby increase detection 
sensitivity), it is desirable to reduce the number of active devices 
(i.e., transistors) required to implement the circuit 10'. 
SUMMARY OF THE INVENTION 
With this background of the invention in mind, it is therefore an object of 
this invention to provide an improved infrared detector array. 
It is another object of this invention to provide an improved infrared 
detector array of the type having a first semiconductor chip providing an 
array of infrared detectors and a second semiconductor chip having formed 
therein a plurality of integration/read circuits, each one thereof being 
directly connected to a corresponding one of the diode detectors to 
provide a hybrid integrated circuit. 
These and other objects of the invention are obtained generally by 
providing: an infrared detector array having a plurality of infrared 
detectors arranged in a matrix of rows and columns in a first 
semiconductor body; and, a plurality of integration/read circuits arranged 
in a matrix of rows and columns in a second semiconductor body, each one 
of the plurality of integration/read circuits being in vertical 
registration with, and electrically connected to, a corresponding one of 
the plurality of detectors. Each one of the integration/read circuits 
includes: a capacitor; a first transistor, electrically coupling the 
capacitor and the corresponding one of the detectors during an integration 
mode, for enabling electrical current generated in the detector in 
response to impinging radiation to pass from the detector to the capacitor 
for integration; and, a second transistor, electrically coupling the 
charge built-up on the capacitor during the integration mode to an output 
bus during a subsequent read mode. 
In accordance with another feature of the invention, a reset circuit is 
coupled to the output bus, for discharging the charge built-up on the 
capacitor during the integration mode and for discharging charge generated 
in the detector during a subsequent reset mode. 
In a preferred embodiment of the invention, the reset circuit is formed in 
a portion of the second semiconductor body laterally displaced from the 
portion of the second semiconductor body having formed therein the array 
of integration/reset circuits. The integration/read circuits are arranged 
in a matrix of rows and columns thereof. Each one of the columns of 
integration/read circuits is connected to a common output bus. A plurality 
of reset circuits is provided, each one thereof being coupled to a 
corresponding one of the column of output buses. Each one of the reset 
circuits includes a third field effect transistor having a gate electrode 
adapted for coupling to the reset signal and one of the source and drain 
electrodes thereof coupled to the corresponding one of the output buses. 
Also included is a buffer circuit disposed between the output bus and an 
output terminal which produces the electrical circuit for a processor. The 
buffer circuit, laterally displaced from the second portion of the 
semiconductor having the array of integration/read circuits, includes a 
fourth field effect transistor having a gate electrode connected to the 
output bus and one of the source and drain electrodes of the fourth 
transistor. 
With such arrangement, because the transistor in the reset circuit used to 
discharge the capacitor during the reset mode is displaced from the region 
where the address circuit is formed, it is coupled to the diode detector 
device through a relatively long, relatively large capacitive impedance 
provided by a common column output bus. Therefore, the buffer transistor 
F.sub.4 of the prior art circuit is able to be removed since switching 
transients produced when the reset transistor is switched to the "on" 
state will be buffered from the diode detector by the relatively large 
capacitive impedance of the column output bus. Further, the discharge of 
the charge stored on the integration capacitor and bus capacitance during 
the reset mode prior to subsequent read or integration modes, passes 
directly onto the column output bus through the reset circuit transistor 
F.sub.8. Still further, in the prior art, circuit (FIG. 1), the voltage on 
the capacitor generates a voltage on the gate of transistor F.sub.5, which 
in turn produces a voltage on the column output bus after the read current 
I.sub.m out out is switched into field effect transistor F.sub.5, by 
transistor F.sub.2. The removal of transistor F.sub.5 with the invention 
thus inherently produces less offset and gain non-uniformity than the 
prior art circuit because of the elimination of the variation in the array 
matrix of gate-to-source voltage variations. A column-to-column gain 
variation is introduced by the introduction of column buffer line 
capacitance variations, but these variations are common to each row of a 
given column and are less severe than the variations induced by transistor 
F.sub.5 variations. The column buffer offset variations of the present 
invention are tightly grouped from one column to the next because the 
physical location of the column buffer circuit is laterally displaced from 
the first portion of the array and the integration/reset circuits over the 
prior art circuit 10'. Because of this displacement, the buffer circuit in 
the present invention can be made large and minimize threshold variations 
attributable to both junction geometry and semiconductor material property 
variations. The extent of the non-uniformity is now dominated by the 
columns relative to the column buffer circuit quality. Whereas in the 
prior art circuit threshold variations in transistor F.sub.5, which is 
also dependent on junction geometry and material property variations cause 
a matrix of non-uniformity associated with each detector as distinguished 
from a tighter column distribution. For example, with a matrix of 128 rows 
and 128 columns of detectors geometry and material variation in transistor 
F.sub.5 of the prior art cause 128.times.128=16,384 circuit variations 
whereas in the present invention the variations in geometry and material 
effect only 128 circuit variations.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now to FIG. 2, an infrared detector array structure 10 is shown 
to include a first semiconductor body or chip 14, here HgCdTe or InSb. The 
chip 14 has formed therein a plurality of infrared photo-diode detectors 
12, an exemplary one thereof being shown in FIG. 3. The photo-diode 
detectors 12 are formed in a conventional manner and are arranged in a 
matrix of rows and columns thereof in the chip 14, as indicated in FIG. 2. 
Thus, as is known and referring also to FIG. 3, the chip 14 has formed on 
one surface thereof a passivation/anti-reflection coating or layer 24 onto 
which incident infrared radiation is subjected, such radiation being 
represented by arrows 26 in FIGS. 2 and 3. The substrate 28 of chip 14 is 
adapted for coupling to a suitable voltage supply, here a drain voltage 
supply, V.sub.dd (here about 0 volts), (not shown). The opposite surface 
of the chip 14 has formed in laterally isolated regions thereof the diode 
detectors 12. Each one of the active regions 15 of the photo-diode 
detectors 12 is isolated in a conventional manner by isolation grooves 30 
and a suitable passivation/insulation layer 32, as shown in FIG. 3. The 
cathode of the photo-diode detector 12 is provided with an electrical 
contact 34, as shown. 
A second semiconductor body, or chip 18, here silicon, has formed in a 
region thereof vertically disposed under the first chip 14, using 
conventional integrated circuit fabrication techniques, a plurality of 
integration/read circuits 10a arranged in a matrix of rows and columns 
thereof. Each one of the plurality of integration/read circuits 10a is in 
vertical alignment, or vertical registration with, and is electrically 
connected to, a corresponding one of the plurality of detectors 12, as 
shown in FIG. 3. Each detector 12 is electrically connected to its 
correspondingly, aligned integration/read circuit 10 by a vertical 
electrical connector 38, here indium. Also formed as an integrated circuit 
on the second chip 18 is a plurality of reset circuits 10b. It is first 
noted that the plurality of reset circuits 10b is formed in a different, 
laterally displaced region where the plurality, or matrix, of 
integration/read circuits 10a is formed. A plurality of columns of output 
buses 19 is formed on the surface of the second semiconductor chip 18. 
Each one of the columns of the output buses 19 connects a corresponding 
one of the reset circuits 10b to a column of integration/read circuits 
10a, as shown more clearly in FIG. 4. 
Referring now to FIG. 4, the integration/read circuits 10a are shown 
arranged in a rectangular matrix of n rows and m columns. As discussed 
briefly above, each column of reset/read circuits is connected, via a 
column output bus 19, to a corresponding one of m reset circuits 10b. An 
integration/read circuit 10a and the reset circuit 10b connected to it by 
column output bus 19. A buffer circuit 21 is connected between each one of 
the column buses 19 and a corresponding output terminal 23 to multiplexer 
circuit 25. The electrical signals produced by column buffer circuits 21 
on the output terminals 23 are fed to a multiplexer 25 to reduce the 
number of electrical leads to a conventional processor, not shown. (The 
multiplexer is controlled by the processor, not shown, in a conventional 
manner). Also formed on the surface of the second chip 18 is a plurality 
of, here n, V.sub.read row conductors 40, each one being connected to the 
integration/read circuits 10a in a corresponding one of the rows thereof, 
as shown in FIG. 4. The V.sub.read row conductors 40 feed the read logic 
signals described above in connection with FIG. 5, to the integration/read 
circuits 10a. A second plurality of n V.sub.set row conductors 42 is also 
formed on the surface of the second chip 18. Each one of the row 
conductors feed a set signal to the integration/read circuits 10 a in the 
row thereof connected to such V.sub.set conductors 42. A reset signal is 
fed to the reset circuits 10b via bus 44, as shown. (It should be noted 
that an exemplary one of the photo-diode detectors 12 is shown in phantom 
to indicate that it is formed on the first chip 14). 
Referring now to FIG. 5, an exemplary one of the interconnected photo-diode 
detectors 12, integration/read circuits 10a and reset circuits 10b are 
shown. It is first noted that the integration/read circuit 10a and 
connected reset circuit 10b together form an address circuit 11 for the 
connected detector 12. Thus, one of the integration/read circuits 10a 
includes: an integration circuit, here a capacitor C.sub.int ; a first 
transistor F.sub.6 having source and drain electrodes serially coupled 
between the detector device 12 and the capacitor C.sub.int, as shown, and 
a second field effect transistor F.sub.7 having source and drain 
electrodes serially coupled between the capacitor C.sub.int and the column 
output bus 19, as shown. The reset circuit 10b includes a third transistor 
F.sub.8 having source and drain electrodes serially coupled between the 
column output bus and a reference potential V.sub.zero (here about -7 
volts). The column output bus 19 is coupled to output terminal 23 through 
buffer circuit 21. Buffer circuit 21 includes a field effect transistor 
F.sub.9, as shown. The source and drain electrodes of transistor F.sub.9 
are connected between ground and the output terminal 23 that goes to the 
multiplexer 25. The buffer circuit 21 operates as a buffer amplifier 
between the column output bus 19 and the output terminal 23. A parasitic 
bus capacitance C.sub.bus from the column output bus 19 to ground, is 
shown. 
In operation, during the integration mode, transistor F.sub.6, is switched 
to an "on" condition by the logic signal V.sub.set fed to the gate 
electrode thereof via V.sub.set row conductor 42. (Here the signal 
V.sub.set swings between 0 and -1.5 volts). During this integration mode, 
transistor F.sub.7 is switched to an "off" condition by the logic signal 
V.sub.read fed to the gate electrode thereof via V.sub.read row conductor 
40. (Here the logic signal V.sub.read swings between about 0 volts and -10 
volts). Thus, in the integration mode, current generated in the diode 
detector 12 passes through the source-drain electrodes of transistor 
F.sub.6 to C.sub.int (previously charged to -7 volts) to charge capacitor 
C.sub.int. The conducting transistor F.sub.6 buffers the photo-diode 
detector 12 from the changing integration voltage being built-up on 
capacitor C.sub.int thus maintaining the detector 12 at a suitable bias, 
as determined by V.sub.set, while also presenting an essentially constant 
input impedance to the photo-diode detector 12. The photo-diode detector 
12 impedance should be larger than the impedance of transistor F.sub.6 and 
variations in detector currents, combined with bias voltage sensitivities 
should be small. 
After a predetermined integration time, transistor F.sub.6 is switched to 
an "off" condition to terminate the integration mode. The charge is 
maintained on the capacitor C.sub.int until the initiation of the read 
mode for the selected circuit 10a. The read mode is initiated by switching 
transistor F.sub.7 to an "on" condition. Transistor F.sub.8 is in the 
"off" condition by the logic signal V.sub.reset on the gate electrode of 
such transistor via the reset bus 44. (Here the swing in V.sub.reset is 
between about 0 volts and -10 volts). The circuit 10 is thus placed in the 
read mode. More particularly, a portion of the charge built-up on 
capacitor C.sub.int is passed to the column output bus 19 via the 
source-drain electrodes of "on" transistor F.sub.7, the remaining portion 
is maintained on the capacitor C.sub.int. The portion of the charge 
coupled to bus 19 is equal to the total charge initially stored on 
capacitor C.sub.int times the ratio of the capacitance of the integration 
capacitor C.sub.int to the sum of the capacitance of bus 19, C.sub.bus, 
and the capacitance of the integrating capacitor, C.sub.int. The signal on 
the column output bus 19 is then passed to the column buffer circuit 21 
and the multiplexer 25 to the processor, not shown. Next, transistor 
F.sub.8 is switched to the "on" condition (transistor F.sub.7 remaining in 
the "on" condition and transistor F.sub.6 being turned "on"), thereby 
placing the circuit 10 in the reset mode. In such reset mode, charge 
built-up on the capacitor C.sub.int is discharged to V.sub.zero, via the 
source-drain electrodes of transistors F.sub.7 and F.sub.8. It is also 
noted that the bus capacitance, C.sub.bus, is reset to V.sub.zero. The 
voltage V.sub.zero sets the starting voltage on the integration capacitor 
C.sub.int and the bus capacitance C.sub.bus. It is also noted that any 
charge generated in the diode detector is also discharged to V.sub.zero 
via the source-drain electrodes of "on" transistors F.sub.6, F.sub.7, and 
F.sub.8. If necessary, the discharge of the charge in the detector can be 
enhanced by turning transistor F.sub.6 "on" harder during the reset mode 
with a lower voltage V.sub.set than that applied during the integration 
mode. 
With such arrangement, because the transistor F.sub.8 in the reset circuit 
10b used to discharge the capacitor C.sub.int during the reset mode is 
displaced from the region where the integration/read circuit 10a is formed 
and is coupled to the diode detector 12 though a relatively long (i.e., 
about 0.25 inches (128.times.128 50 micrometers per device), or greater, 
compared with about 10 microns in the circuit 10 shown in FIG. 1), 
relatively large capacitive impedance of the common column output bus 19, 
switching transients produced when the transistor F.sub.8 is switched to 
the "on" state will therefore be buffered from the diode detector 12 by 
the relatively large capacitive impedance of the column output bus 19. 
Further, the charge stored on the capacitor C.sub.int passes directly onto 
the column output bus 19 without passing through an additional matrix 
buffer transistor such as transistor F.sub.5 of the prior art circuit in 
FIG. 1. Thus, there is inherently less non-uniformity than the prior art 
arrangement because of the elimination of the variation in gate-to-source 
voltage variations due to geometry and process variations of the 
relatively small transistor F.sub.5 of the prior art circuit 10'. 
Having described a preferred embodiment of the invention, it will now be 
apparent to one of skill in the art that other embodiments incorporating 
its concepts may be used. It is felt, therefore, that this invention 
should not be restricted to the disclosed embodiment but rather should be 
limited only by the spirit and scope of the appended claims.