Semiconductor device with air gap and boron nitride cap and method for forming the same

The present disclosure provides a semiconductor device with an air gap and a boron nitride cap for reducing capacitive coupling in a pattern-dense region and a method for preparing the semiconductor device. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a boron nitride layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the boron nitride layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device with an air gap and a boron nitride cap for reducing capacitive coupling in a pattern-dense region and a method for forming the same.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while providing greater functionality and including greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, various types and dimensions of semiconductor devices providing different functionalities are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices.

However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations. Integration in semiconductor devices becomes increasingly complicated. An increase in complexity of manufacturing and integration of the semiconductor device may cause deficiencies, such as increased parasitic capacitance between adjacent conductive elements, which results in increased power consumption and unwanted resistive-capacitive (RC) delay (i.e., signal delay), especially in a pattern-dense region. Accordingly, there is a continuous need to improve the manufacturing process of semiconductor devices so that the problems can be addressed.

SUMMARY

In one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a boron nitride layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the boron nitride layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

In an embodiment, the first metal plug is separated from the second metal plug by a first distance, the third metal plug is separated from the fourth metal plug by a second distance, and the second distance is greater than the first distance. In an embodiment, the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug are covered by the boron nitride layer, and a top surface of the first metal plug is higher than a bottom surface of the first portion of the boron nitride layer. In an embodiment, the semiconductor device further includes a first spacer surrounding the first metal plug, and a second spacer surrounding the second metal plug, wherein the air gap is enclosed by the first spacer, the second spacer, the first portion of the boron nitride layer, and the semiconductor substrate. In an embodiment, the semiconductor device further includes a third spacer surrounding the third metal plug, wherein the third spacer is enclosed by the third metal plug, the boron nitride layer, and the semiconductor substrate, and a fourth spacer surrounding the fourth metal plug, wherein the fourth spacer is enclosed by the fourth metal plug, the boron nitride layer, and the semiconductor substrate. In an embodiment, the semiconductor device further includes an energy removable structure disposed between the first metal plug and the second metal plug, wherein a portion of the energy removable structure is between the air gap and the semiconductor substrate. In an embodiment, the pattern-dense region is in a memory cell of a memory device, and the pattern-loose region is in a peripheral region outside of the memory cell of the memory device.

In another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The first metal plug and the second metal plug have an air gap therebetween. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. A distance between the first metal plug and the second metal plug is less than a distance between the third metal plug and the fourth metal plug. The semiconductor device further includes a boron nitride layer covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. The boron nitride layer has a first portion between the first metal plug and the second metal plug and a second portion between the third metal plug and the fourth metal plug, and a height of the second portion is greater than a height of the first portion.

In an embodiment, the height of the second portion is substantially the same as a height of the third metal plug. In an embodiment, a width of the second portion of the boron nitride layer is greater than a width of the first portion of the boron nitride layer. In an embodiment, the semiconductor device further includes a first spacer surrounding the first metal plug, a second spacer surrounding the second metal plug, a third spacer surrounding the third metal plug, and a fourth spacer surrounding the fourth metal plug, wherein the air gap is between the first spacer and the second spacer. In an embodiment, a contact area between the second portion of the boron nitride layer and the third spacer is greater than a contact area between the first portion of the boron nitride layer and the first spacer. In an embodiment, the semiconductor device further includes an energy removable structure disposed between the first spacer and the second spacer and covered by the first portion of the boron nitride layer, wherein the air gap is enclosed by the energy removable structure.

In yet another embodiment of the present disclosure, a method for forming a semiconductor device is provided. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate, wherein the first metal plug and the second metal plug are over a pattern-dense region of the semiconductor substrate, and the third metal plug and the fourth metal plug are over a pattern-loose region of the semiconductor substrate. The method also includes depositing a boron nitride layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the boron nitride layer extends between the first metal plug and the second metal plug such that the first portion of the boron nitride layer and the semiconductor substrate are separated by an air gap while a second portion of the boron nitride layer extends between the third metal plug and the fourth metal plug such that the second portion of the boron nitride layer is in direct contact with the semiconductor substrate.

In an embodiment, a bottommost width of the second portion of the boron nitride layer is greater than a bottommost width of the first portion of the boron nitride layer. In an embodiment, the method further includes forming a first spacer surrounding the first metal plug, a second spacer surrounding the second metal plug, a third spacer surrounding the third metal plug, and a fourth spacer surrounding the fourth metal plug before the boron nitride layer is deposited. In an embodiment, the method further includes before the boron nitride layer is deposited, performing a deposition process that selectively deposits an energy removable layer between the first spacer and the second spacer in the pattern-dense region without depositing the energy removable layer between the third spacer and the fourth spacer in the pattern-loose region. In an embodiment, the boron nitride layer is formed to cover the energy removable layer, and the method further includes performing a heat treatment process to remove the energy removable layer, such that the air gap is enclosed by the first spacer, the second spacer, the first portion of the boron nitride layer, and the semiconductor substrate. In an embodiment, the boron nitride layer is formed to cover the energy removable layer, and the method also further includes performing a heat treatment process to transform the energy removable layer into an energy removable structure, wherein the air gap is enclosed by the energy removable structure, and the energy removable structure is denser than the energy removable layer. In an embodiment, the formation of the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug includes forming a doped oxide layer over the semiconductor substrate, etching the doped oxide layer to form a plurality of openings exposing the semiconductor substrate, forming the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug in the openings, and removing the doped oxide layer before the boron nitride layer is deposited.

Embodiments of a semiconductor device are provided in the disclosure. The semiconductor device includes metal plugs and a boron nitride layer over a pattern-dense region and a pattern-loose region of a semiconductor substrate. The boron nitride layer has a first portion between the metal plugs in the pattern-dense region, and a second portion between the metal plugs in the pattern-loose region. The first portion of the boron nitride layer is separated from the semiconductor substrate by an air gap, and the second portion of the boron nitride layer is in direct contact with the semiconductor substrate. Therefore, the parasitic capacitance between the metal plugs of the pattern-dense region may be reduced. As a result, the overall device performance may be improved.

DETAILED DESCRIPTION

FIG. 1is a top view illustrating a semiconductor device100, andFIG. 2is a cross-sectional view illustrating the semiconductor device100along the sectional line I-I′ inFIG. 1, in accordance with some embodiments. In some embodiments, the semiconductor device100includes a semiconductor substrate101, conductive features125a,125b,127a,127b, spacers135a,135b,137a,137b, and a dielectric layer such as a boron nitride (BN) layer143, as shown inFIGS. 1 and 2in accordance with some embodiments. In some embodiments, the conductive features125a,125b,127a,127bare conductive wires such as interconnects or bit lines, configured to electrically connecting two conductive terminals laterally separated from each other. In some embodiments, the conductive features125a,125b,127a,127bare metal plugs, such as bit line plug or capacitor plug, configured to electrically connecting two conductive terminals vertically separated from each other. The conductive features125a,125b,127a,127bare elaborated in connection with following figures, using the metal plugs as examples.

In some embodiments, isolation structures (not shown) are disposed in the semiconductor substrate101, and active areas (not shown) are defined by the isolation structures in the semiconductor substrate101. Each of the active areas may include source/drain (S/D) regions. In some embodiments, the semiconductor substrate101has a pattern-dense region A and a pattern-loose region B, the metal plugs125aand127aare disposed over the pattern-dense region A, and the metal plugs125band127bare disposed over the pattern-loose region B. It should be noted that the distance D1between the metal plugs125aand127ais less than the distance D2between the metal plugs125band127b. No obvious interfaces exist between the pattern-dense region A and the pattern-loose region B. The dashed lines shown inFIGS. 1 and 2are used to clarify the disclosure.

The spacers135aand137aare disposed over the pattern-dense region A, and the spacers135band137bare disposed over the pattern-loose region B. In some embodiments, the metal plug125ais surrounded by the spacer135a, the metal plug127ais surrounded by the spacer137a, the metal plug125bis surrounded by the spacer135b, and the metal plug127bis surrounded by the spacer137b. The dielectric layer (boron nitride layer)143is disposed over the pattern-dense region A and the pattern-loose region B.

Specifically, the metal plugs125a,125b,127a,127band the spacers135a,135b,137a,137bover the pattern-dense region A and the pattern-loose region B are covered by the boron nitride layer143. In some embodiments, the boron nitride layer143has a first portion P1between the metal plugs125aand127a, and a second portion P2between the metal plugs125band127b. In other words, the first portion P1of the boron nitride layer143is over the pattern-dense region A of the semiconductor substrate101, and the second portion P2of the boron nitride layer143is over the pattern-loose region B of the semiconductor substrate101. In particular, the first portion P1of the boron nitride layer143is between and in direct contact with the spacers135aand137a, and the second portion P2of the boron nitride layer143is between and in direct contact with the spacers135band137b. In some embodiments, the contact area between the first portion P1of the boron nitride layer143and the spacer135a(or the spacer137a) is less than the contact area between the second portion P2of the boron nitride layer143and the spacer135b(or the spacer137b).

It should be noted that the first portion P1of the boron nitride layer143is separated from the semiconductor substrate101by an air gap G while the second portion P2of the boron nitride layer143is in direct contact with the semiconductor substrate101. In other words, there is no air gap in the pattern-loose region B. As shown inFIG. 2, the second portion P2of the boron nitride layer143extends to cover the bottommost parts of the spacers135band137b, such that the spacer135bis enclosed by the metal plug125b, the second portion P2of the boron nitride layer143, and the semiconductor substrate101, and the spacer137bis enclosed by the metal plug127b, the second portion P2of the boron nitride layer143, and the semiconductor substrate101. In some embodiments, the air gap G is between the spacers135aand137aof the pattern-dense region A, and a top surface TS of the metal plug125ais higher than a bottom surface BS of the first portion P1of the boron nitride layer143(i.e., the interface between the first portion P1of the boron nitride layer143and the air gap (G).

In some embodiments, the first portion P1of the boron nitride layer143has a width W1, the second portion P2of the boron nitride layer143has a width W2, and the width W2is greater than the width W1. Moreover, the first portion P1of the boron nitride layer143has a height H1, the second portion P2of the boron nitride layer143has a height H2, and the height H2is greater than the height H1. It should be noted that the height H2of the second portion P2of the boron nitride layer143is substantially the same as the height of the metal plug125bor the height of the metal plug127b. Within the context of this disclosure, the word “substantially” means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

Furthermore, bit lines (not shown) and storage nodes (not shown) may be formed over the structure ofFIGS. 1 and 2in the subsequent processes. In some embodiments, the bit lines and the storage nodes are electrically connected to the S/D regions in the semiconductor substrate101. In some embodiments, the semiconductor device100is a dynamic random access memory (DRAM).

FIG. 3is a flow diagram illustrating a method10of forming the semiconductor device100, and the method10includes steps S11, S13, S15-1, S15-2, S15-3, S17, and S19, in accordance with some embodiments.FIG. 4is a flow diagram illustrating another method20of forming the semiconductor device100, and the method20includes steps S21, S23, S25, S27, S29-1, S29-2, S29-3, S31, and S33, in accordance with some embodiments. The steps S11to S19ofFIG. 3and the steps S21to S33ofFIG. 4are elaborated in connection with following figures.

FIGS. 5 and 7are top views illustrating intermediate stages in the formation of the semiconductor device100, andFIGS. 6 and 8are cross-sectional views illustrating intermediate stages in the formation of the semiconductor device100, in accordance with some embodiments. It should be noted thatFIGS. 6 and 8are cross-sectional views along the sectional line I-I′ ofFIGS. 5 and 7, respectively.

As shown inFIGS. 5 and 6, the semiconductor substrate101is provided. The semiconductor substrate101may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the semiconductor substrate101may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, the semiconductor substrate101includes an epitaxial layer. For example, the semiconductor substrate101has an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate101is a semiconductor-on-insulator substrate which may include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other applicable methods.

As mentioned above, the semiconductor substrate101has a pattern-dense region A and a pattern-loose region B, and isolation structures and S/D regions may be formed in the semiconductor substrate101. In these cases, the metal plugs125a,125b,127a, and127bare formed over the S/D regions. In some embodiments, the metal plugs125aand127aare formed over the pattern-dense region A, and the metal plugs125band127bare formed over the pattern-loose region B. The respective step is illustrated as the step S11in the method10shown inFIG. 3. It should be noted that the number of metal plugs over the pattern-dense region A is not limited to two, and may be more than two. Similarly, the number of metal plugs over the pattern-loose region B is not limited to two, and may be more than two, either.

In some embodiments, the metal plugs125a,125b,127a, and127bare made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, another applicable conductive material, or a combination thereof. In some embodiments, the metal plugs125a,125b,127a, and127bare formed by electroplating. In some other embodiments, the metal plugs125a,125b,127a, and127bare formed by a chemical vapor deposition (CVD) process, a metal organic CVD (MOCVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a sputtering process, or another applicable process.

Next, as shown inFIGS. 7 and 8, the spacers135a,135b,137a, and137bare formed surrounding the metal plugs125a,125b,127a, and127b, in accordance with some embodiments. The respective step is illustrated as the step S13in the method10shown inFIG. 3. In some embodiments, the spacers135a,135b,137a, and137bare formed on sidewalls of the metal plugs125a,125b,127a, and127b, respectively.

In some embodiments, the spacers135a,135b,137a, and137bare made of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, another applicable dielectric material, or a combination thereof. In some embodiments, the formation of the spacers135a,135b,137a, and137bincludes conformally depositing a spacer material (not shown) over the top surfaces and the sidewalls of the metal plugs125a,125b,127a, and127band the top surface of the semiconductor substrate101, and etching the spacer material to form the spacers135a,135b,137a, and137bon sidewalls of the metal plugs125a,125b,127a, and127b.

The deposition process for forming the spacers135a,135b,137a, and137bmay include a CVD process, a PVD process, an ALD process, a spin-coating process, or another applicable process. In addition, the etching process for forming the spacers135a,135b,137a, and137bmay be an anisotropic etching process, which removes the same amount of the spacer material vertically in all places, leaving the spacers135a,135b,137a, and137bon the sidewalls of the metal plugs125a,125b,127a, and127b. In some embodiments, the etching process is a dry etching process. As a result, an opening140ais obtained between the spacers135aand137a, and another opening140bis obtained between the spacers135band137b.

Referring toFIG. 2, after the spacers135a,135b,137a, and137bare formed, the boron nitride layer143is deposited over the structure ofFIGS. 7 and 8, such that the air gap G is formed in the pattern-dense region A, in accordance with some embodiments. The respective step is illustrated as the step S15-1in the method10shown inFIG. 3. In some embodiments, the boron nitride layer143has a hexagonal textured structure

In some embodiments, the boron nitride layer143is formed, using ALD and/or PEALD techniques. In this exemplary embodiment, the device is placed in a reaction chamber and is preferably heated to a temperature between 100 degrees Celsius and 500 degrees Celsius at a chamber pressure between 0.5 Torr and 10 Torr. More preferably, the temperature is between 300 degrees Celsius and 400 degrees Celsius, and the chamber pressure is between 0.5 Torr and 3 Torr.

In some embodiments, a boron precursor gas, such as one or more of boron trichloride (BCl3), trimethylboron (B(CH3)3), diborane (B2H6), boron tribromide (BBr3), or a precursor gas diluted with an inert gas such as helium (He) or argon (Ar), is then pulsed into the chamber where it is allowed to form a monolayer, or less than a monolayer, on the exposed surfaces of the device (i.e., surfaces of the gate stack, hardmask, semiconductor body, and, if present, the liner layer). In some embodiments, the boron precursor is pulsed for a time period between 2 seconds to 30 seconds at a flow rate ranging from 50 standard cubic centimeters (sccm) per minute to 1,000 sccm per minute. In some embodiments, the flow rate at which the boron precursor is pulsed into the chamber is between 100 sccm per minute and 500 sccm per minute.

In some embodiments, after the boron precursor is pulsed into the chamber, the chamber is purged with an inert gas, such as nitrogen (N2), argon (Ar), or helium (He), for an amount of time (e.g., 30 seconds) necessary to remove byproducts and all unreacted species from the chamber.

In some embodiments, a nitrogen-containing reactant gas, such as nitrogen, ammonia (NH3), or a mixture of nitrogen and hydrogen (H2), is then pulsed into the deposition chamber to react with the first layer and form a monolayer of boron-nitrogen. In some embodiments, the nitrogen-containing gas is pulsed into the chamber for a time period between 1 second and 10 seconds at a flow rate between 50 sccm per minute and 1,000 sccm per minute. In some embodiments, the flow rate at which the nitrogen-containing gas is pulsed is between 100 sccm per minute and 300 sccm per minute.

In some embodiments, PEALD techniques may also be used when providing the nitrogen-containing reactant gas to the chamber, whereby the boron-nitrogen bond forming reactions are assisted by dissociating the reactant gases using a plasma. In some embodiments, where PEALD is used, the plasma condition is created at a power between 50 W to 500 W and, more preferably, at a power between 100 W and 200 W.

In some embodiments, after pulsing the nitrogen-containing reactant gas, the chamber is again purged for an appropriate amount of time, and the cycle is repeated until deposition of the boron nitride layer has occurred to the desired thickness.

Since the width W2of the opening140bis greater than the width W1of the opening140a(seeFIG. 8), the opening140bis entirely filled by the boron nitride layer143while the opening140ais only partially filled by the boron nitride layer143due to the loading effect. As a result, the air gap G is sealed by the first portion P1of the boron nitride layer143. In some embodiments, the air gap G is enclosed by the first portion P1of the boron nitride layer143, the spacers135a,137a, and the semiconductor substrate101. In addition, the width W2is also the width of the second portion P2of the boron nitride layer143between the spacers135band137b, and the width W1is also the width W1of the first portion P1of the boron nitride layer143between the spacers135aand137a, as shown inFIG. 2in accordance with some embodiments.

After the boron nitride layer143is deposited, the semiconductor device100is obtained. By forming the air gap G between the metal plugs125aand127a(or between the spacers135aand137asurrounding the metal plugs125aand127a), the parasitic capacitance between the metal plugs125aand127amay be reduced, especially in the pattern-dense region A. As a result, the overall device performance may be improved (e.g., the decreased power consumption and signal delay).

FIGS. 9 to 15are cross-sectional views illustrating intermediate stages in the formation of the semiconductor device100, in accordance with some embodiments. The forming method shown inFIGS. 9-15is different from the forming method shown inFIGS. 1, 2, and 5 to 8.

A doped oxide layer103is formed over the pattern-dense region A and the pattern-loose region B of the semiconductor substrate101, as shown inFIG. 9in accordance with some embodiments. The respective step is illustrated as the step S21in the method20shown inFIG. 4. In some embodiments, the doped oxide layer103is made of silicon oxide, and P-type dopants, such as boron (B), gallium (Ga), or indium (In), or N-type dopants, such as phosphorous (P) or arsenic (As), can be implanted therein. In some embodiments, the doped oxide layer103is formed by a deposition process and is doped in-situ during the deposition process. In some other embodiments, the doped oxide layer103is formed by a deposition process and a subsequent ion implantation process.

Next, a patterned mask105is formed over the doped oxide layer103, as shown inFIG. 10in accordance with some embodiments. In some embodiments, the patterned mask105has openings106a,106b,108a, and108b, and portions of the doped oxide layer103are exposed by the openings106a,106b,108a, and108bof the patterned mask105.

The patterned mask105may be formed by a deposition process and a patterning process. The deposition process for forming the patterned mask105may be a CVD process, a high-density plasma CVD (HDPCVD) process, a spin-coating process, or another applicable process. The patterning process for forming the patterned mask105may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin-coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

Subsequently, an etching process is performed on the doped oxide layer103using the patterned mask105as a mask, as shown inFIG. 11in accordance with some embodiments. After the etching process, openings116a,116b,118a, and118bare formed in the doped oxide layer103. In some embodiments, portions of the semiconductor substrate101are exposed by the openings116a,116b,118a, and118bof the doped oxide layer103. In particular, the openings116aand118aare located on the pattern-dense region A of the semiconductor substrate101, and the openings116band118bare located on the pattern-loose region B of the semiconductor substrate101, in accordance with some embodiments. After the openings116a,116b,118a, and118bare formed, the patterned mask105may be removed.

Then, metal plugs125a,125b,127a, and127bare formed in the openings116a,116b,118a, and118b, as shown inFIG. 12in accordance with some embodiments. The respective step is illustrated as the step S23in the method20shown inFIG. 4. In some embodiments, the metal plugs125aand127aare formed over the pattern-dense region A of the semiconductor substrate101, and the metal plugs125band127bare formed over the pattern-loose region B of the semiconductor substrate101.

Some materials used to form the metal plugs125a,125b,127a, and127bofFIG. 12are similar to, or the same as, those used to form the metal plugs125a,125b,127a, and127bofFIG. 6, and details thereof are not repeated herein. In addition, the formation of the metal plugs125a,125b,127a, and127bofFIG. 12may include depositing a conductive material (not shown) in the openings116a,116b,118a, and118band over the doped oxide layer103, and performing a planarization process to remove the excess portions of the conductive material, such that the doped oxide layer103is exposed. In some embodiments, the patterned mask105(seeFIG. 10) is not removed after the openings116a,116b,118a, and118bare formed, and the conductive layer is deposited in the openings116a,116b,118a, and118band over the patterned mask105. In these cases, the patterned mask105may be removed during the planarization process. The planarization process may be a chemical mechanical polishing (CMP) process.

After the metal plugs125a,125b,127a, and127bare formed, the doped oxide layer103is removed, as shown inFIG. 13in accordance with some embodiments. The respective step is illustrated as the step S25in the method20shown inFIG. 4. In some embodiments, the doped oxide layer103is removed by an ashing process or stripping process. In some other embodiments, an etching process is used to remove the doped oxide layer103. The etching process may include a wet etching process, a dry etching process, or a combination thereof.

Next, as shown inFIG. 14, the spacers135a,135b,137a, and137bare formed surrounding the metal plugs125a,125b,127a, and127b, in accordance with some embodiments. The respective step is illustrated as the step S27in the method20shown inFIG. 4. Some materials and processes used to form the spacers135a,135b,137a, and137bofFIG. 14are similar to, or the same as, those used to form the spacers135a,135b,137a, and137bofFIG. 8, and details thereof are not repeated herein.

After the spacers135a,135b,137a, and137bare formed, opening140abetween the spacers135aand137aand opening140bbetween the spacers135band137bare obtained. It should be noted that the width W1of the opening140ain the pattern-dense region A is less than the width W2of the opening140bin the pattern-loose region B, in accordance with some embodiments.

After the spacers135a,135b,137a, and137bare formed, the boron nitride layer143is deposited over the structure ofFIG. 14, such that the air gap G is formed in the opening140ain the pattern-dense region A, as shown inFIG. 15in accordance with some embodiments. The respective step is illustrated as the step S29-1in the method20shown inFIG. 4. Some materials and processes used to form the boron nitride layer143ofFIG. 15are similar to, or the same as, those used to form the boron nitride layer143ofFIG. 2, and details thereof are not repeated herein.

As mentioned above, the width W2of the opening140bis greater than the width W1of the opening140a(seeFIG. 14). Therefore, the opening140bis entirely filled by the boron nitride layer143while the opening140ais only partially filled by the boron nitride layer143due to the loading effect. As a result, the air gap G is sealed by the first portion P1of the boron nitride layer143, and the second portion P2of the boron nitride layer143is in direct contact with the semiconductor substrate101.

FIGS. 16 to 18are cross-sectional views illustrating intermediate stages in the formation of the semiconductor device100, in accordance with some embodiments. The forming method shown inFIGS. 16 to 18is different from the forming method shown inFIGS. 1, 2, and 5 to 8and the forming method shown inFIGS. 9 to 15.

Continuing withFIG. 8 or 14, an energy removable layer151is selectively deposited between the spacers135aand137ain the pattern-dense region A, as shown inFIG. 16in accordance with some embodiments. The respective step is illustrated as the step S15-2in the method10shown inFIG. 3and the step S29-2in the method20shown inFIG. 4. It should be noted that the energy removable layer151is formed by performing a deposition process that selectively deposits the energy removable layer151between the spacers135aand137ain the pattern-dense region A without depositing the energy removable layer151between the spacers135band137bin the pattern-loose region B, in accordance with some embodiments.

In some embodiments, the materials of the energy removable layer151include a thermal decomposable material. In some other embodiments, the materials of the energy removable layer151include a photonic decomposable material, an e-beam decomposable material, or another applicable energy decomposable material. Specifically, in some embodiments, the materials of the energy removable layer151include a base material and a decomposable porogen material that is substantially removed once being exposed to an energy source (e.g., heat).

In some embodiments, the base material includes hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO2), and the decomposable porogen material includes a porogen organic compound, which can provide porosity to the space originally occupied by the energy removable layer151in the subsequent processes. In addition, the deposition process for forming the dielectric layer151may include a CVD process, a PVD process, an ALD process, a spin-coating process, or another applicable process. After the energy removable layer151is formed, a reduced opening140a′ may be obtained over the energy removable layer151.

Then, the boron nitride layer143is formed covering the structure ofFIG. 16, as shown inFIG. 17in accordance with some embodiments. The respective step is illustrated as the step S17in the method10shown inFIG. 3and the step S31in the method20shown inFIG. 4. Some materials and processes used to form the boron nitride layer143ofFIG. 17are similar to, or the same as, those used to form the boron nitride layer143ofFIG. 2, and details thereof are not repeated herein. It should be noted that the structure has no air gaps in this stage.

After the boron nitride layer143is deposited, a heat treatment process is performed, as shown inFIG. 18in accordance with some embodiments. In some embodiments, during the heat treatment process, the energy removable layer151is removed, such that the air gap G is formed between the spacers135aand137ain the pattern-dense region A. The respective step is illustrated as the step S19in the method10shown inFIG. 3and the step S33in the method20shown inFIG. 4.

More specifically, the heat treatment process is used to remove the decomposable porogen materials of the energy removable layer151to generate pores, and the pores are filled by air after the decomposable porogen materials are removed, such that the air gap G is obtained, in accordance with some embodiments. In some other embodiments, the heat treatment process can be replaced by a light treatment process, an e-beam treatment process, a combination thereof, or another applicable energy treatment process. For example, an ultra-violet (UV) light or laser light may be used to remove the decomposable porogen materials of the energy removable layer151, such that the air gap G is obtained.

FIG. 19is a cross-sectional view illustrating an intermediate stage of forming an energy removable structure151′ during the formation of a modified semiconductor device100′, in accordance with some embodiments.

Continuing withFIG. 17, a heat treatment process is performed to remove a portion of the energy removable layer151, as shown inFIG. 19in accordance with some embodiments. In some embodiments, during the heat treatment process, the energy removable layer151is transformed into an energy removable structure151′, such that the air gap G is enclosed by the energy removable structure151′. The respective step is illustrated as the step S19in the method10shown inFIG. 3and the step S33in the method20shown inFIG. 4.

More specifically, in some embodiments, the heat treatment process is used to remove the decomposable porogen materials of the energy removable layer151to generate pores, and the base materials of the energy removable layer151are accumulated at the edges of the energy removable layer151. The pores are filled by air after the decomposable porogen materials are removed, such that the air gap G is obtained inside the remaining portions of the energy removable layer151(i.e., the energy removable structure151′), in accordance with some embodiments. In some other embodiments, the air gap G is not fully surrounded by the energy removable structure151′ due to gravity, and a portion of the energy removable structure151′ is between the air gap G and the semiconductor substrate101. After the energy removable structure151′ is formed, the modified semiconductor device100′ is obtained.

FIG. 20is a partial schematic illustration of an exemplary integrated circuit, such as a memory device1000, including an array of memory cells30in accordance with some embodiments. In some embodiments, the memory device1000includes a dynamic random access memory (DRAM). In some embodiments, the memory device1000includes a number of memory cells30arranged in a grid pattern and including a number of rows and columns. The number of memory cells30may vary depending on system requirements and fabrication technology.

In some embodiments, each of the memory cells30includes an access device and a storage device. The access device is configured to provide controlled access to the storage device. In particular, the access device is a field effect transistor (FET)31and the storage device is a capacitor33, in accordance with some embodiments. In each of the memory cells30, the FET31includes a drain35, a source37and a gate39. One terminal of the capacitor33is electrically connected to the source37of the FET31, and the other terminal of the capacitor33may be electrically connected to the ground. In addition, in each of the memory cells30, the gate39of the FET31is electrically connected to a word line WL, and the drain35of the FET31is electrically connected to a bit line BL.

The above description mentions the terminal of the FET31electrically connected to the capacitor33is the source37, and the terminal of the FET31electrically connected to the bit line BL is the drain35. However, during read and write operations, the terminal of the FET31electrically connected to the capacitor33may be the drain, and the terminal of the FET31electrically connected to the bit line BL may be the source. That is, either terminal of the FET31could be a source or a drain depending on the manner in which the FET31is being controlled by the voltages applied to the source, the drain and the gate.

By controlling the voltage at the gate39via the word line WL, a voltage potential may be created across the FET30such that the electrical charge can flow from the drain35to the capacitor33. Therefore, the electrical charge stored in the capacitor33may be interpreted as a binary data value in the memory cell30. For example, a positive charge above a threshold voltage stored in the capacitor33may be interpreted as binary “1.” If the charge in the capacitor33is below the threshold value, a binary value of “0” is said to be stored in the memory cell30.

The bit lines BL are configured to read and write data to and from the memory cells30. The word lines WL are configured to activate the field effect transistors (FET)31to access a particular row of the memory cells30. Accordingly, the memory device1000also includes a periphery region which may include an address buffer, a row decoder and a column decoder. The row decoder and the column decoder selectively access the memory cells30in response to address signals that are provided to the address buffer during read, write and refresh operations. The address signals are typically provided by an external controller such as a microprocessor or another type of memory controller.

Referring back toFIGS. 2 and 19, the air gap G is formed in the pattern-dense region A of the semiconductor device100or100′, while no air gap is formed in the pattern-loose region B of the semiconductor device100or100′. The pattern-dense region A may be any of the regions of the memory cells30in the memory device1000, and the pattern-loose region B may be any of the regions of the address buffer, the row decoder, or the column decoder in the memory device1000.

Embodiments of the semiconductor devices100and100′ are provided in the disclosure. The semiconductor devices100and100′ include a plurality of metal plugs125a,125b,127a,127bover the pattern-dense region A and the pattern-loose region B of the semiconductor substrate101, spacers135a,135b,137a,137bsurrounding the metal plugs125a,125b,127a,127b, respectively, and the boron nitride layer143covering the metal plugs125a,125b,127a,127band the spacers135a,135b,137a,137b. Particularly, the boron nitride layer143has a first portion P1between the spacers135aand137ain the pattern-dense region A and a second portion P2between the spacers135band137bin the pattern-loose region B, the first portion P1of the boron nitride layer143is separated from the semiconductor substrate101by an air gap G while the second portion P2of the dielectric layer is in direct contact with the semiconductor substrate101. Therefore, the parasitic capacitance between the metal plugs125aand127aover the pattern-dense region A may be reduced. As a result, the overall device performance may be improved (i.e., the decreased power consumption and resistive-capacitive (RC) delay).

In one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

In another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The first metal plug and the second metal plug have an air gap therebetween. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. A distance between the first metal plug and the second metal plug is less than a distance between the third metal plug and the fourth metal plug. The semiconductor device further includes a dielectric layer covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. The dielectric layer has a first portion between the first metal plug and the second metal plug and a second portion between the third metal plug and the fourth metal plug, and a height of the second portion is greater than a height of the first portion.

In yet another embodiment of the present disclosure, a method for forming a semiconductor device is provided. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate, wherein the first metal plug and the second metal plug are over a pattern-dense region of the semiconductor substrate, and the third metal plug and the fourth metal plug are over a pattern-loose region of the semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an air gap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.

The embodiments of the present disclosure have some advantageous features. By forming an air gap between the adjacent metal plugs in the pattern-dense region, the parasitic capacitance between the metal plugs in the pattern-dense region may be reduced. This significantly improves the overall device performance.