Structure and formation method of semiconductor device with magnetic element covered by polymer material

A structure and a formation method of a semiconductor device are provided. The method includes forming a passivation layer over a semiconductor substrate. The method also includes forming a magnetic element over the passivation layer. The method further includes forming an isolation layer over the magnetic element and the passivation layer. The isolation layer includes a polymer material. In addition, the method includes forming a conductive line over the isolation layer, and the conductive line extends across the magnetic element.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

FIGS. 1A-1Jare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG. 1A, a semiconductor substrate100is received or provided. The semiconductor substrate100may include a semiconductor wafer with multiple device elements formed therein. For example, the semiconductor substrate100is a silicon wafer with transistors formed therein.

In some embodiments, an interconnection structure102is formed over the semiconductor substrate100. The interconnection structure102may include multiple dielectric layers and multiple conductive features. These conductive features form electrical connections between the device elements and other elements to be formed later. For example, the interconnection structure102includes a conductive layer802and a conductive pad804, as shown inFIG. 1A. In some embodiments, the topmost dielectric layer of the interconnection structure102is made of or includes a passivation layer. In some embodiments, the passivation layer is made of or includes a polymer material. For example, the polymer material is polyimide or one or more other suitable polymers.

As shown inFIG. 1A, a protective layer104is deposited over the interconnection structure102, in accordance with some embodiments. The protective layer104may be used to protect the interconnection structure102(including the passivation layer of the interconnection structure102) during a subsequent etching process for improving the quality of magnetic elements. In some embodiments, the protective layer104is in direct contact with the interconnection structure102. In some other embodiments, one or more other material layers are formed between the protective layer104and the interconnection structure102.

In some embodiments, the protective layer104is a single layer. In some other embodiments, the protective layer104includes multiple sub-layers. The sub-layers may be made of the same material. Alternatively, some of the sub-layers are made of different materials.

The protective layer104may be made of or include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof. The protective layer104may be deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a spin coating process, one or more other applicable processes, or a combination thereof.

The protective layer104may have a thickness that is in a range from 0.1 μm to about 3 μm. In some cases, if the protective layer104is thinner than about 0.1 μm, the protective layer104may be too thin to protect the interconnection structure102underneath. In some other cases, if the protective layer104is thicker than about 3 μm, the stress of the protective layer104may be too high. The protective layer104may become broken or delaminated due to the high stress, which may negatively affect the quality and reliability of the semiconductor device structure.

However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the protective layer104has a different thickness range. In some other embodiments, the protective layer104is not formed.

As shown inFIG. 1A, an etch stop layer106is deposited over the protective layer104, in accordance with some embodiments. The etch stop layer106may protect the protective layer104and the interconnection structure102thereunder from being damaged during a subsequent etching process for forming magnetic elements. In some embodiments, the etch stop layer106is a single layer. In some other embodiments, the etch stop layer106includes multiple sub-layers. The sub-layers may be made of the same material. Alternatively, some of the sub-layers are made of different materials.

In some embodiments, the etch stop layer106and the protective layer104are made of different materials. The etch stop layer106may be made of or include tantalum oxide, zirconium oxide, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the etch stop layer106is deposited using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. In some other embodiments, a metal layer is deposited over the interconnection structure102. Afterwards, an oxidation process and/or a nitridation process are used to transform the metal layer into the etch stop layer106.

As shown inFIG. 1A, two or more magnetic layers (such as magnetic layers108a-108e) are sequentially deposited over the etch stop layer106, in accordance with some embodiments. These magnetic layers108a-108ewill be patterned later to form one or more magnetic elements. In some embodiments, the magnetic layers108a-108eare made of the same material. In some other embodiments, some of the magnetic layers108a-108eare made of different materials. In some embodiments, each of the magnetic layers108a-108ehas the same thickness. In some other embodiments, some of the magnetic layers108a-108ehave different thicknesses.

In some embodiments, the magnetic layers108a-108econtain cobalt, zirconium, tantalum, iron, nickel, one or more other elements, or a combination thereof. The magnetic layers108a-108emay be made of or include an alloy containing cobalt, zirconium, and tantalum (CZT), an alloy containing cobalt and zirconium, an alloy containing iron and nickel, one or more other suitable materials, or a combination thereof. The magnetic layers108a-108emay be deposited using a PVD process, a CVD process, an ALD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1B, a patterned mask layer110is formed over the magnetic layer108e, in accordance with some embodiments. The patterned mask layer110is used to assist in a subsequent patterning process of the magnetic layers108a-108e. In some embodiments, the patterned mask layer110is a patterned photoresist layer. A photolithography process may be used to form the patterned mask layer110with the desired pattern. For example, the top view of the patterned mask layer110may have a square shape, a rectangular shape, or another suitable shape.

Afterwards, the magnetic layers108a-108eare partially removed, as shown inFIG. 1Bin accordance with some embodiments. As a result, the remaining portions of the magnetic layers108a-108etogether form a magnetic element109. In some embodiments, with the patterned mask layer110as an etching mask, an etching process is used to partially remove the magnetic layers108a-108e. In some embodiments, the etching process is a wet etching process. The etchant used in the wet etching process may include nitric acid, hydrochloric acid, hydrofluoric acid, one or more other suitable etchants, or a combination thereof. For example, a mixture of nitric acid, hydrochloric acid, and hydrofluoric acid is used as the etchant in the wet etching process. The etch stop layer106and the protective layer104may protect the interconnection structure102from being damaged during the wet etching process for patterning the magnetic layers108a-108e.

In some cases, due to the characteristics of the magnetic layers108a-108eand the wet etching process, hollow structures112may be formed at sidewall surfaces of the magnetic element109, as shown inFIG. 1B. The hollow structures112may include voids inside, which might negatively affect the quality and reliability of the formed magnetic element109.

As shown inFIG. 1C, the patterned mask layer110is removed, and a new mask element114is then formed to partially cover the top surface of the magnetic element109, in accordance with some embodiments. The material and formation method of the mask element114may be the same as or similar to those of the patterned mask layer110. In some embodiments, the magnetic element109includes a stack of multiple magnetic layers108a-108e. In some embodiments, the topmost magnetic layer (i.e., the magnetic layer108e) is wider than the mask element114.

In some embodiments, the mask element114covers a center region R1of the topmost magnetic layer108e, as shown inFIG. 1C. The topmost magnetic layer108ehas a periphery region R2that is not covered by the mask element114. The periphery region R2of the topmost magnetic layer108esurrounds the center region R1of the topmost magnetic layer108e.

Afterwards, an etching process is performed to partially remove the magnetic element109, as shown inFIG. 1Cin accordance with some embodiments. In some embodiments, the etching process is a dry etching process that is capable of removing the hollow structures112(including voids) at the sidewall surfaces of the magnetic element109. The etchant used in the dry etching process may include CF4, another suitable etchant, or a combination thereof. In some embodiments, due to the protection of the protective layer104, the dry etching process is allowed to be performed for a longer period of time to ensure a complete removal of the hollow structures112. Since the hollow structures112are removed, the quality and reliability of the magnetic element109are improved.

In some embodiments, the etching process used for removing the hollow structures112also partially remove the etch stop layer106and the protective layer104. Alternatively, in some other embodiments, another etching process is used to remove the protective layer104or the etch stop layer106. As a result, a portion of the interconnection structure102is exposed, as shown inFIG. 1Cin accordance with some embodiments. For example, the passivation layer of the interconnection structure102is exposed. In some embodiments, one or more conductive pads (such as the conductive pad804) formed in or on the interconnection structure102are exposed. Other conductive features such as redistribution layers may be formed later to connect the exposed conductive pads.

Afterwards, the mask element114is removed to expose the top surface109T of the magnetic element109, as shown inFIG. 1Din accordance with some embodiments. As shown inFIG. 1D, sidewall surfaces109S of the magnetic element109have stair-like profiles. The magnetic element109includes multiple sub-layers (108a-108e), and each sub-layer is larger or wider than the sub-layer above it, as shown inFIG. 1Din accordance with some embodiments.

FIG. 4is a top layout view of an intermediate stage of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG. 4is a top layout view of a portion of the structure shown inFIG. 1D. In some embodiments, a portion of the structure shown inFIG. 1D(without including the conductive pad804) is taken along line I-I inFIG. 4.

In some embodiments, the magnetic element109has multiple sub-layers such as the magnetic layers108a-108e. In some embodiments, each of the sub-layers is larger than the sub-layer above it, as shown inFIGS. 1D and 4. For example, the magnetic layer108ais larger than the magnetic layer108b. Similarly, the magnetic layer108dis larger than the magnetic layer108e.

As shown inFIG. 1E, an isolation layer806is formed over the interconnection structure102, the conductive pad804, and the magnetic element109, in accordance with some embodiments. In some embodiments, the isolation layer806covers an entirety of a top surface of the magnetic element109. In some embodiments, the isolation layer806is in direct contact with the interconnection structure102. For example, the isolation layer806is in direct contact with the passivation layer of the interconnection structure102. In some embodiments, the isolation layer806is in direct contact with the conductive pad804and the magnetic element109.

The isolation layer806may be made of or include a polymer material. Therefore, the isolation layer806may have a lower stress than other material layer that is made of silicon nitride. The polymer material may include polyimide, one or more other suitable polymers, or a combination thereof. The isolation layer806may be deposited using a spin coating process, a spray coating process, a lamination process, one or more other applicable processes, or a combination thereof. In some embodiments, the isolation layer806is formed directly on the magnetic element109using a spin coating process.

In some embodiments, the isolation layer806includes a first polymer material, and the passivation layer of the interconnection structure102includes a second polymer material. In some embodiments, since both the isolation layer806and the passivation layer of the interconnection structure102are made of polymer materials, the adhesion between the isolation layer806and the passivation layer of the interconnection structure102is high. In some embodiments, both the isolation layer806and the passivation layer of the interconnection structure102include or are made of the same polymer material such as polyimide. The adhesion between the isolation layer806and the passivation layer of the interconnection structure102is further improved. The isolation layer806may also function as a stress buffer layer. A cracking of the isolation layer806near the corner of the magnetic element109may be prevented.

In some other cases where the isolation layer is made of silicon nitride or silicon oxynitride having no polymer material, a delamination or a cracking may occur between the isolation layer and the passivation layer of the interconnection structure102. For example, delamination may occur at the position that is between the isolation layer806and the interconnection structure102and near the magnetic element109. Alternatively, the conductive pad formed in or over the interconnection structure102may be damaged due to the high stress of the isolation layer. For example, the isolation layer may shrink and cause delamination between the isolation layer and a passivation layer (such as a polyimide layer) of the interconnection structure102. The isolation layer may also be broken.

In some embodiments, the adhesion between the isolation layer806and the magnetic element109is also improved due to the material characteristics of the isolation layer806. The good adhesion may help to ensure that no or substantially no delamination would occur between the isolation layer806and the magnetic element109. The isolation layer806has a low stress and may also function as a stress buffer layer. Therefore, the isolation layer806may also help to prevent delamination between the magnetic layers108a-108e. The performance and reliability of the semiconductor device structure are improved.

As shown inFIG. 1F, the isolation layer806is patterned to form an opening that exposes the conductive pad804originally below the isolation layer806, in accordance with some embodiments. The isolation layer806may be patterned using a photolithography process, an energy beam drilling process, one or more other applicable processes, or a combination thereof. The energy beam drilling process may involve partially drilling the isolation layer806using an ion beam, an electron beam, a plasma beam, one or more other suitable beams, or a combination thereof. In some embodiments, after the patterning of the isolation layer806, the remaining isolation layer806still covers an entirety of the top surface of the magnetic element109, as shown inFIG. 1F.

As shown inFIG. 1G, the isolation layer806is cured to form a cured isolation layer806′, in accordance with some embodiments. The isolation layer806may be cured using a thermal operation to form the cured isolation layer806′. The thermal operation may be carried out at a temperature that is in a range from about 250 degrees C. to about 350 degrees C. for one or more hours. For example, the isolation layer806is cured at about 310 degrees C. for about four hours.

In some other embodiments, the isolation layer806is cured to form a cured isolation layer806′ using an illumination process. The illumination process may involve irradiate the isolation layer806using an ultraviolet light, a laser, one or more other suitable light sources, or a combination thereof. As a result, the cured isolation layer806′ is formed. In some other embodiments, both the thermal curing process and the illumination process are used for curing the isolation layer806.

However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the isolation layer806is not cured.

In some embodiments, due to the material characteristics of the isolation layer806, the cured isolation layer806′ also has inclined side surfaces. The inclined profile of the cured isolation layer806′ may facilitate to subsequent formation processes. The reliability and performance of the semiconductor device structure are improved.

As shown inFIG. 1G, the thickness of the cured isolation layer806′ becomes greater along a direction from an upper portion towards a lower portion of the cured isolation layer806′, in accordance with some embodiments. As shown inFIG. 1G, the cured isolation layer806′ has a first thickness H1and a second thickness H2. The first thickness H1is measured from one of the inclined side surfaces of the cured isolation layer806′ to an upper edge corner of the magnetic element109. The second thickness H2is measured from the inclined side surface of the cured isolation layer806′ to a lower edge corner of the magnetic element109. In some embodiments, the first thickness H1is greater than the second thickness H2.

As shown inFIG. 1G, there are a first imaginary line L1passing through the inclined side surface of the cured isolation layer806′ and a second imaginary line L2passing through the topmost edge corner of the magnetic element109. The first imaginary line L1and the second imaginary line L2together define an angle θ. In some embodiments, the angle θ is in a range from about 5 degrees to about 25 degrees. In some other embodiments, the angle θ is in a range from about 10 degrees to about 20 degrees.

As shown inFIG. 1H, a seed layer808is deposited over the cured isolation layer806′ and the conductive pad804, in accordance with some embodiments. The seed layer808may be used to assist in a subsequent plating process, such as an electroplating process. The seed layer808covers an entirety of the top surface of the magnetic element109.

The seed layer808may be made of or include copper, aluminum, titanium, gold, cobalt, platinum, nickel, one or more other suitable materials, or a combination thereof. The seed layer808may be deposited using a PVD process, a CVD process, an ALD process, a lamination process, one or more other applicable processes, or a combination thereof.

Afterwards, a patterned mask layer810is formed over the seed layer808, as shown inFIG. 1Hin accordance with some embodiments. The patterned mask layer810has an opening812that exposes a portion of the seed layer808directly above the conductive pad804. The patterned mask layer810includes one or more openings (including the opening812) that expose portions of the seed layer808where one or more conductive lines will be formed later. The patterned mask layer810may be a patterned photoresist layer. The formation of the patterned mask layer810may involve a photolithography process.

As shown inFIG. 1I, a conductive line814is formed over the exposed portions of the seed layer808, in accordance with some embodiments. The conductive line814may be made of or include copper, gold, cobalt, one or more other suitable materials, or a combination thereof. The conductive line814may be formed using an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1J, the patterned mask layer810is removed, in accordance with some embodiments. Afterwards, exposed portions of the seed layer808not covered by the conductive lines (such as the conductive line814) are removed, as shown inFIG. 1Jin accordance with some embodiments. An etching process may be used to remove the exposed portions of the seed layer808.

In some embodiments, due to the protection of the cured isolation layer806′, the magnetic element109is protected from damage during the etching process for removing the exposed portions of the seed layer808. The surface condition of the magnetic element109may be maintained in good condition. The quality and reliability of the magnetic element109are ensured.

FIG. 3is a top layout view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG. 3is the top layout view of the structure shown inFIG. 1J. In some embodiments, the cross-sectional view of the structure shown inFIG. 1Jis taken along the line1J-1J ofFIG. 3.

FIG. 2is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG. 3is the top layout view of the structure shown inFIG. 2. In some embodiments, the cross-sectional view of the structure shown inFIG. 2is taken along the line2-2ofFIG. 3.

As shown inFIG. 2, the conductive line814extends across the magnetic element109, in accordance with some embodiments. As shown inFIG. 3, multiple conductive lines814are formed over the cured isolation layer806′, in accordance with some embodiments. In some embodiments, each of the conductive lines814extends across the magnetic element109(that is under the cured isolation layer806′ and illustrated using dotted lines). The cured isolation layer806′ physically and/or electrically separate the magnetic element109from the conductive lines814.

In some embodiments, these conductive lines814are electrically connected to each other. In some embodiments, each of the conductive lines814is electrically connected to other conductive lines formed above and below the magnetic element109. These conductive lines (including the conductive lines814) together surround the magnetic element109. The conductive lines and the magnetic element109may together function as an inductor.

In some embodiments mentioned above, the formation of the conductive lines814involves using an electroplating process. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, a metal layer is deposited using a PVD process, a CVD process, one or more other applicable processes, or a combination thereof. Afterwards, a photolithography process and an etching process are used to pattern the metal layer into the conductive lines814.

Afterwards, multiple material layers and device elements may be formed over the structure as illustrated inFIGS. 1J, 2, and 3. Then, a dicing process may be performed to separate the structure into multiple semiconductor dies or die packages that are separate from each other.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG. 5is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG. 5is an enlarged cross-sectional view showing a portion of the structure illustrated inFIG. 1C. In some embodiments, after the etching process for removing the hollow structures112, portions of the top surface of the topmost magnetic layer108eare recessed. As shown inFIG. 5, the magnetic layer108ehas a first portion500A covered by the mask element114and a second portion500B not covered by the mask element114. After the etching process, the second portion500B is recessed to a lower height level than the first portion500A. In some embodiments, a recess502is thus formed. The recess502surrounds the first portion500A. In some embodiments, the recess502is positioned at the region R2illustrated inFIG. 4. Therefore, the recess502surrounds the region R1.

In some embodiments, the recess502has a width that is measured from a sidewall of the recess502to an edge of the magnetic layer108e. The width may be in a range from about 5 μm to about 10 μm. In some cases, if the width is less than about 5 μm, the etching process for removing the hollow structures112may be negatively affected. Once an overlay shift occurs during the formation of the mask element114, some of the hollow structures112may be covered by the mask element114. As a result, the hollow structures112may not be removed completely, which may result in a performance degradation of the semiconductor device structure. In some other cases, if the width is greater than about 10 μm, not only the hollow structures112but also a greater portions of the magnetic element109may be removed, which may also result in a performance degradation of the semiconductor device structure.

FIG. 6is a top view of an isolation layer of a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG. 6is a top view of a portion or an entirety of the isolation layer806′ illustrated inFIG. 1G, 1J, 2, or3. In some embodiments, due to the characteristics of the isolation layer806′, from the top view of the cured isolation layer806′, the cured isolation layer806′ includes one or more color rings902when the cured isolation layer806′ is observed under illumination of a visible light. The color rings902may include orange color, green color, yellow color, red color, another color, or a combination thereof.

In some embodiments, the cured isolation layer806′ has a thickness measured between the top surfaces of the cured isolation layer806′ and the magnetic element109. The thickness may be in a range from about 1.5 μm to about 2.5 μm. In some embodiments, the thickness of the cured isolation layer806′ is not uniform. The thickness non-uniform characteristics of the cured isolation layer806′ may result in the color rings902.

In some cases, if the thickness of the cured isolation layer806′ is smaller than about 1.5 μm, some portions of the magnetic element109may not be covered well and may be exposed. As a result, the magnetic element109may be in direct contact with a subsequently formed conductive line, which may result in function failure of the semiconductor device structure. In some other cases, if the thickness of the cured isolation layer806′ is greater than about 2.5 μm, the distance between the magnetic element109and a subsequently formed conductive line may be too large, which may result in a poor performance of the semiconductor device structure.

In some embodiments, some of the color rings902are continuous rings. In some embodiments, some of the color rings902are discontinuous rings. In some embodiments, the portion of the isolation layer806′ directly above the magnetic element109have about four to about six color rings. In some embodiments, widths of some of the color rings902are different from each other. In some embodiments, one of the color rings902that has a thinner width W1surrounds one of the color rings902that has a wider width W2, as shown inFIG. 6. In some embodiments, the inner color ring902has a lighter color than the outer color ring902. In some other embodiments, each of the color rings902is substantially as wide as each other. One of the color rings902surrounds one or more other color rings902. In some embodiments, the most inner color ring902surrounds an oval-like area R3, as shown inFIG. 6.

Embodiments of the disclosure form a semiconductor device structure with a magnetic element. An isolation layer made of or including a polymer material is formed to cover the magnetic element. Due to the low stress and good adhesion characteristics of the isolation layer, the magnetic element is protected. Delamination, cracking, and/or damage of the magnetic element and/or other nearby material layers are significantly reduced. The quality, performance, and reliability of the semiconductor device structure are significantly improved.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a passivation layer over a semiconductor substrate. The method also includes forming a magnetic element over the passivation layer. The method further includes forming an isolation layer over the magnetic element and the passivation layer. The isolation layer includes a polymer material. In addition, the method includes forming a conductive line over the isolation layer, and the conductive line extends across the magnetic element.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first polymer layer over a semiconductor substrate and forming a magnetic element over the first polymer layer. The method also includes forming a second polymer layer over the first polymer layer to cover the magnetic element. The method further includes forming a conductive line over the second polymer layer. The conductive line extends across the magnetic element.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes a passivation layer between the semiconductor substrate and the magnetic element. The semiconductor device structure further includes an isolation layer over the magnetic element and the passivation layer, and the isolation layer comprises a polymer material. In addition, the semiconductor device structure includes a conductive line over the isolation layer and extending across the magnetic element.