DISPLAY DEVICE

According to one embodiment, a display device includes a substrate, an insulating layer disposed above the substrate, a lower electrode disposed above the insulating layer, a rib formed of an inorganic material, including a pixel aperture overlapping the lower electrode and covering a peripheral edge of the lower electrode, a partition disposed above the rib, an upper electrode opposing the lower electrode, and an organic layer disposed between the lower electrode and the upper electrode, which emits light in response to a potential difference between the lower electrode and the upper electrode. The peripheral edge of the lower electrode is located between the insulating layer and the partition in a thickness direction of the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-062834, filed Apr. 7, 2023, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

In recent years, display devices in which organic light-emitting diodes (OLEDs) are applied as display elements have been put to practical use. Such a display device comprises a lower electrode, an organic layer which covers the lower electrode, and an upper electrode which covers the organic layer.

Generally, organic layers have low resistance to moisture. Therefore, if moisture reaches an organic layer for some reason, it can be a contributing factor to a decrease in display quality, such as a decrease in luminance of the display element when emitting light.

DETAILED DESCRIPTION

In general, according to one embodiment, a display device includes a substrate, an insulating layer disposed above the substrate, a lower electrode disposed above the insulating layer, a rib formed of an inorganic material, including a pixel aperture overlapping the lower electrode and covering a peripheral edge of the lower electrode, a partition disposed above the rib, an upper electrode opposing the lower electrode, and an organic layer disposed between the lower electrode and the upper electrode, which emits light in response to a potential difference between the lower electrode and the upper electrode. The peripheral edge of the lower electrode is located between the insulating layer and the partition in a thickness direction of the insulating layer.

Note that the disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the sizes, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. Besides, in the drawings, the corresponding elements are denoted by like reference numerals, and a detailed description thereof is omitted unless otherwise necessary.

Note that, in order to make the descriptions more easily understandable, some of the drawings illustrate an X axis, a Y axis and a Z axis orthogonal to each other. A direction along the X axis is referred to as a first direction, a direction along the Y axis is referred to as a second direction, and a direction along the Z axis is referred to as a third direction. The third direction Z is a normal direction to a plane containing the first direction X and the second direction Y. Further, viewing the elements parallel to the third direction Z is referred to as plan view.

The display device according to this embodiment is an organic electroluminescent display device comprising an organic light emitting diode (OLED) as a display element, and can be mounted on various types of electronic devices such as television devices, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile telephone terminals, wearable terminals and the like.

FIG.1is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP comprises a display panel PNL including an insulating substrate10. The display panel PNL includes a display area DA on which images are displayed and a peripheral area SA around the display area DA. The substrate10may be of glass or a flexible resin film.

In this embodiment, the shape of the substrate10in plan view is rectangular. However, the shape of the substrate10in plan view is not limited to rectangular, but may as well be some other shape such as a square, circle, oval or the like.

The display area DA comprises a plurality of pixels PX arranged in a matrix along the first direction X and the second direction Y. The pixels PX each include a plurality of subpixels SP. For example, each pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. Note that the pixel PX may as well include a subpixel SP of some other color, such as white, in addition to the subpixels SP1, SP2and SP3, or in place of any of the subpixels SP1, SP2and SP3.

The subpixels SP each comprises a pixel circuit1and a display element DE driven by the pixel circuit1. The pixel circuit1comprises a pixel switch2, a drive transistor3, and a capacitor4. The pixel switch2and the drive transistor3are switching elements each constituted by a thin-film transistor, for example.

A gate electrode of the pixel switch2is connected to a respective scanning line GL. One of source and drain electrodes of the pixel switch2is connected to a respective signal line SL, and the other is connected to the gate electrode of the drive transistor3and the capacitor4. In the drive transistor3, one of the source electrode and the drain electrode is connected to the power line PL and capacitor4, and the other is connected to the display element DE.

Note that the configuration of the pixel circuit1is not limited to that of the example illustrated in the figure. For example, the pixel circuit1may comprise more thin-film transistors and capacitors.

FIG.2is a plan view schematically showing an example layout of the subpixels SP1, SP2and SP3. In the example illustrated inFIG.2, the subpixels SP2and SP3are each aligned with the subpixel SP1along the first direction X. Further, the subpixel SP2and the subpixel SP3are aligned along the second direction Y.

When the subpixels SP1, SP2and SP3are laid out as such, rows in each of which subpixels SP2and SP3are arranged alternately along the second direction Y and rows in each of which a plurality of subpixels SP1are repeatedly arranged along the second direction Y are formed in the display area DA. These rows are alternately arranged along the first direction X. Note that the layout of the subpixels SP1, SP2and SP3is not limited to that of the example illustrated inFIG.2.

In the display area DA, a rib5and a partition6are disposed. The rib5includes pixel apertures AP1, AP2and AP3in the subpixels SP1, SP2and SP3, respectively, and has a grid-like shape in plan view. In the example illustrated inFIG.2, the pixel aperture AP1is larger than the pixel aperture AP2, and the pixel aperture AP2is larger than the pixel aperture AP3.

The subpixels SP1each comprise a lower electrode LE1, an upper electrode UE1and an organic layer OR1, which overlap the respective pixel aperture AP1. The subpixels SP2each comprise a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap the respective pixel aperture AP2. The subpixel SP3has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap the respective pixel aperture AP3.

Parts of the lower electrode LE1, the upper electrode UE1and the organic layer OR1, which overlap the pixel aperture AP1constitute a display element DE1of the subpixel SP1. Parts of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2, which overlap the pixel aperture AP2constitute a display element DE2of the subpixel SP2. Parts of the lower electrode LE3, the upper electrode UE3and the organic layer OR3, which overlap the pixel aperture AP3constitute a display element DE3of the subpixel SP3. The display elements DE1, DE2and DE3may as well further include a cap layer as described below. The rib5surrounds each of these display elements DE1, DE2and DE3.

The lower electrode LE1is connected to the pixel circuit1of the subpixel SP1(seeFIG.1) via a contact hole CH1. The lower electrode LE2is connected to the pixel circuit1of the subpixel SP2via a contact hole CH2. The lower electrode LE3is connected to the pixel circuit1of the subpixel SP3via a contact hole CH3.

On the rib5, a partition6is disposed. The partition6includes a plurality of first partitions6xextending along the first direction X and a plurality of second partitions6yextending along the second direction Y. Further, the partition6includes apertures AP61, AP62and AP63in the subpixels SP1, SP2and SP3, respectively. That is, the partition6, as in the case of the rib5, has a grid-like shape in plan view, and both the rib5and the partition6are disposed between the display elements DE1, DE2and DE3.

In the example ofFIG.2, the lower electrodes LE2and LE3include projecting portions PR21and PR31, respectively. The projecting portion PR21protrudes from the main body of the lower electrode LE2(, which is the part overlapping the pixel aperture AP2) toward the contact hole CH2. The projecting portion PR31protrudes from the main body of the lower electrode LE2(, which is the part overlapping the pixel aperture AP3) toward the contact hole CH3. The contact holes CH2and CH3overlap the projecting portions PR21and PR31, respectively.

FIG.3is a cross-sectional view schematically showing the display device DSP taken along line III-III inFIG.2. On the substrate10described above, a circuit layer11is placed. The circuit layer11includes various circuits and wiring lines, such as the pixel circuit1, the scanning lines GL, the signal lines SL, the power line PL and the like, shown inFIG.1.

The circuit layer11is covered by an insulating layer12. The insulating layer12functions as a planarization film that planarizes the unevenness caused by the circuit layer11. Although not illustrated in the cross section shown inFIG.3, the contact holes CH1, CH2and CH3described above are formed in the insulating layer12.

The lower electrodes LE1, LE2and LE3are disposed on the insulating layer12. The rib5is disposed on the insulating layer12and the lower electrodes LE1, LE2and LE3. End portions of the lower electrodes LE1, LE2and LE3are covered by the rib5.

The partition6(the second partitions6y) comprises a conductive lower portion61disposed on the rib5, and a upper portion62disposed on the lower portion61. The upper portion62has a width greater than that of the lower portion61. With this configuration, both ends of the upper portion62protrude from side surfaces of the lower portion61. The shape of the partition6having such a configuration is referred to as an overhang shape.

The organic layer ORI covers the lower electrode LE1through the pixel aperture AP1. The upper electrode UE1covers the organic layer OR1and opposes the lower electrode LE1. The organic layer OR2covers the lower electrode LE2through the pixel aperture AP2. The upper electrode UE2covers the organic layer OR2and opposes the lower electrode LE2. The organic layer OR3covers the lower electrode LE3through the pixel aperture AP3. The upper electrode UE3covers the organic layer OR3and opposes the lower electrode LE3. The upper electrodes UE1, UE2and UE3are in contact with a side surface of the lower portion61of the partition6.

In the example inFIG.3, a cap layer CP1is placed on the upper electrode UE1, a cap layer CP2is placed on the upper electrode UE2, and a cap layer CP3is placed on the upper electrode UE3. The cap layers CP1, CP2and CP3have a function as optical adjustment layers that improve the efficiency of extraction of light emitted by the organic layers OR1, OR2and OR3, respectively.

In the following descriptions, a stacked body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1is referred to as a stacked layer film FL1, a stacked body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2is referred to as a stacked layer film FL2, and a stacked body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3is referred to as a stacked layer film FL3.

A part of the stacked layer film FL1is located above the upper portion62. This part of the thin film FL1is separated from the portion of the stacked layer film FL1that is located under the partition6(the portion constituting the display element DE1). Similarly, a part of the stacked layer film FL2is located above the upper portion62, and this part of the stacked layer film FL2is separated from the portion of the stacked layer film FL2that is located under the partition6(the part constituting the display element DE2). Further, a part of the stacked layer film FL3is located above the upper portion62and this part is separated from the portion of the stacked layer film FL3that is located under the partition6(the portion constituting the display element DE3).

In the subpixels SP1, SP2and SP3, sealing layers SE1, SE2and SE3are disposed, respectively. The sealing layer SE1continuously covers the partition6around the stacked layer film FL1and the subpixel SP1. The sealing layer SE2continuously covers the partition6around the stacked layer film FL2and the subpixel SP2. The sealing layer SE3continuously covers the partition6around the thin film FL3and the subpixel SP3.

In the example illustrated inFIG.3, the stacked layer film FL1and the sealing layer SE1located on the portion of the partition6between the subpixels SP1and SP2are separated from the stacked layer film FL2and the sealing layer SE2on the partition6. Further, the stacked layer film FL1and the sealing layer SE1located on the portion of the partition6between the subpixels SP1and SP3are separated from the stacked layer film FL3and the sealing layer SE3on the partition6.

The sealing layers SE1, SE2and SE3are covered by a resin layer13. The resin layer13is covered by a sealing layer14. The sealing layer14is covered by a resin layer15. The resin layers13and15and the sealing layer14are continuously provided at least over the entire display area DA, and a part of the resin layers extend to the peripheral area SA.

A cover member such as a polarizer, a touch panel, a protective film or a cover glass may be further disposed above the resin layer15. Such a cover member may be adhered to the resin layer15via an adhesive layer such as optical clear adhesive (OCA), for example.

The organic insulating layer12is formed of an organic insulating material. The rib5, the sealing layers14, SE1, SE2and SE3each can be formed of an inorganic insulating material such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), aluminum oxide (Al2O3) or the like. For example, the rib5is formed of silicon oxynitride, whereas the sealing layers14, SE1, SE2and SE3are formed of silicon nitride. The resin layers13and15are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

The lower electrodes LE1, LE2and LE3each include a reflective layer formed of silver (Ag), for example, and a pair of conductive oxide layers which respectively cover the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be formed of a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO).

The upper electrodes UE1, UE2and UE3are formed, for example, of a metallic material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2and LE3correspond to anodes, and the upper electrodes UE1, UE2and UE3correspond to cathodes.

The organic layers OR1, OR2and OR3each have a stacked layer structure of, for example, a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer. The organic layers OR1, OR2and OR3may have a so-called tandem structure including a plurality of light emitting layers.

The cap layers CP1, CP2and CP3each have, for example, a stacked layer structure in which a plurality of transparent thin films are stacked one on another. These thin films may include thin films formed of inorganic materials and thin films formed of organic materials. Further, these plurality of thin films have refractive indices different from each other. The materials of the thin films are different from the materials of the upper electrodes UE1, UE2and UE3, and also different from the materials of the sealing layers SE1, SE2and SE3. Note that at least one of the cap layers CP1, CP2and CP3may be omitted.

The lower portion61of the partition is formed of, for example, aluminum (Al). The lower portion61may as well be formed of an aluminum alloy such as an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi), or may have a stacked layer structure of an aluminum layer and an aluminum alloy layer. Further, the lower portion61may as well include a bottom layer formed of a metallic material different from aluminum or the aluminum alloy, under the aluminum layer or the aluminum alloy layer. Usable examples of the metallic material which forms the bottom layer include molybdenum (Mo), titanium nitride (TiN), molybdenum-tungsten alloy (MoW) and molybdenum-niobium alloy (MoNb).

For example, the upper portion62of the partition6has a stacked layer structure of a bottom layer formed of a metallic material and a top layer formed of a conductive oxide. Usable examples of the metallic material which forms the bottom layer include titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, and molybdenum-niobium alloy. Usable examples of the conductive oxide which forms the top layer include ITO and IZO. Note that the upper portion62may have a single-layer structure of any of these materials.

To the partition6, a common voltage is supplied. This common voltage is supplied to each of the upper electrodes UE1, UE2and UE3, which are in contact with a side surface of the lower portion61. To the lower electrodes LE1, LE2and LE3, pixel voltages are respectively supplied through the respective pixel circuits1of the subpixels SP1, SP2and SP3.

The organic layers OR1, OR2and OR3emit light in response to the voltage applied. More specifically, when a potential difference is created between the lower electrode LE1and the upper electrode UE1, the light emitting layer of the organic layer OR1emits light of the blue wavelength range. When a potential difference is created between the lower electrode LE2and the upper electrode UE2, the light emitting layer of the organic layer OR2emits light of the green wavelength range. When a potential difference is created between the lower electrode LE3and the upper electrode UE3, the light emitting layer of the organic layer OR3emits light of the red wavelength range.

As another example, the light emitting layers of the organic layers OR1, OR2and OR3may emit light of the same color (for example, white). In this case, the display device DSP may comprise color filters that converts the light emitted by the light emitting layers into light of a color corresponding to each respective one of the subpixels SP1, SP2and SP3. Further, the display device DSP may as well comprise a layer containing quantum dots that are excited by the light emitted by the light emitting layers to generate light of colors corresponding to the subpixels SP1, SP2and SP3, respectively.

FIG.4is an enlarged plan view schematically showing the vicinity of the subpixel SP2inFIG.2.

The peripheral edge (outline) of the lower electrode LE2has a first side S11, a second side S12, a third side S13and a fourth side S14. The first side S11extends along the first direction X. The second side S12is located on a side opposite to the first side S11in the second direction Y and extends along the first direction X. The third side S13extends along the second direction Y. The fourth side S14is located on a side opposite to the third side S13in the first direction X and extends along the second direction Y.

The first side S11, the second side S12, the third side S13, and the fourth side S14are each located on an outer side of the aperture AP62and surrounds the aperture AP62. The first side S11, the second side S12, the third side S13, and the fourth side S14each overlap the partition6. For example, the first side S11overlaps the first partition6xillustrated in the upper part of the figure. The second side S12overlaps the first partition6xshown in the lower part in the figure. The third side S13overlaps the second partition6yshown on the left part in the figure. The fourth side S14overlaps the second partition6yshown on the right part of the figure. Note that the projecting portion PR21protrudes from the first side S11upwardly in the figure and overlaps the contact hole CH2.

Although not represented inFIG.4, similarly, the peripheral edges of the lower electrodes LE1and LE3are located on outer sides of the apertures AP61and AP63so as to surround the apertures AP61and AP63, respectively, and overlap the partition6(the first partition6xand second partition6y, respectively).

FIG.5is a cross-sectional view schematically showing the display device DSP taken along line V-V inFIG.4.FIG.6is a cross-sectional view schematically showing the display device DSP taken along line VI-VI inFIG.4. InFIGS.5and6, the substrate10, the circuit layer11, the resin layers13and15, and the sealing layer14are omitted.

In the example ofFIG.5, the lower portion61of the partition6on the left side in the figure (the second partition6y) includes a side surface F1and the lower portion61of the partition6on the right side in the figure (the second partition6y) includes a side surface F2. The peripheral edges of the upper electrode UE2are in contact with the side surfaces F1and F2, respectively.

Similarly, in the example ofFIG.6, the lower portion61of the partition6on the left side of the figure (the first partition6x) includes a side surface F3and the lower portion61of the partition6on the right side in the figure (the first partition6x) includes a side surface F4. One of the peripheral edges of the upper electrode UE2is in contact with the side surface F3and the other is not in contact with the side surface F4.

FIGS.5and6respectively show cases where one of the peripheral edges of the upper electrode UE2is not contact with the side surface F4only. However, it suffices if the peripheral edge of the upper electrode UE2is brought into contact with at least the side surface F3, and does not necessarily be in contact with the side surfaces F1and F2. More precisely, it suffices if at least the one of the peripheral edges of the upper electrode UE2, which is close to the contact hole CH2is in contact with the side surface of the lower portion61, and the other edges need not be in contact with the side surface of the lower portion61.

Although not represented inFIGS.5and6, similarly, it suffices if at least those of the peripheral edges of the upper electrodes UE1and UE3, which are close to the contact holes CH1and CH3are in contact with the respective side surfaces of the lower portion61, and the other edges need not be in contact with the side surfaces of the lower portion61.

Since the rib5is thin in this embodiment, a step is formed in the upper surface of the rib5due to the lower electrodes LE1, LE2and LE3. For example, in the example ofFIG.5, a step5ais formed in the rib5in the vicinity of the third side S13of the lower electrode LE2. Similarly, a step5bis formed in the rib5in the vicinity of the fourth side S14of the lower electrode LE2.

Further, in the example ofFIG.6, for example, a step5cis formed in the rib5in the vicinity of the first side S11of the lower electrode LE2. Similarly, a step5dis formed in the rib5in the vicinity of the second side S12of the lower electrode LE2.

In this embodiment, as shown inFIGS.5and6, the peripheral edges of the lower electrode LE2overlap the lower portion61of the partition6.

More particularly, the third side S13and the fourth side S14of the peripheral edges of the lower electrode LE2overlap the lower portion61of the second partition6y, which constitutes the partition6. That is, as shown inFIG.5, the third side S13and the fourth side S14are located between the organic insulating layer12and the lower portion61of the second partition6yin the third direction Z (the thickness direction of the rib5and the organic insulating layer12). With this configuration, the step5acreated by the third side S13and the step5bcreated by the fourth side S14are covered by the lower portion61of the second partition6y.

Note that the overlapping width between the lower electrode LE2and the lower portion61of the second partition6y(more specifically, a width W1from the third side S13to the side surface F1and a width W2from the fourth side S14to the side surface F2) should preferably be 1.5 μm or more. With this configuration, even if some variation in the size of the second partition6yoccurs during the process of forming the partition6, the peripheral edges of the lower electrode LE2can be reliably positioned between the organic insulating layer12and the lower portion61of the second partition6yin the third direction Z.

Similarly, the first side S11and the second side S12of the lower electrode LE2overlap the lower portion61of the first partition6x, which constitutes the partition6. That is, as shown inFIG.6, the first side S11and the second side S12are located between the organic insulating layer12and the lower portion61of the first partition6xin the third direction Z. With this configuration, the step5ccreated by the first side S11and the step5dcreated by the second side S12are covered by the lower portion61of the first partition6x.

Note that the overlapping width between the lower electrode LE2and the lower portion61of the second partition6x(more specifically, a width W3from the first side S11to the side surface F3and a width W4from the second side S12to the side surface F4) should preferably be 1.5 μm or more. With this configuration, even if some variation in the size of the first partition6xoccurs during the process of forming the partition6, the peripheral edges of the lower electrode LE2can be reliably positioned between the organic insulating layer12and the lower portion61of the first partition6xin the third direction Z.

Although not represented inFIGS.5and6, similarly, the peripheral edges of the lower electrodes LE1and LE3overlap the lower portion61of the partition6, and the peripheral edges of the lower electrodes LE1and LE3are located between the organic insulating layer12and the lower portion61of the partition6in the third direction Z. Therefore, the step of the rib5caused by the lower electrodes LE1and LE3can as well be covered by the lower portion61of the partition6.

According to the display device DSP of this embodiment, it is possible to improve resistance to moisture. This advantageous effect will now be explained usingFIG.7.

FIG.7is a cross-sectional view schematically showing a display device DSP1according to a comparative example. The display device DSP1according to the comparative example differs from the display device DSP of the present embodiment in that the peripheral edges of the lower electrode LE are not located between the organic insulating layer12and the lower portion61of the partition6in the third direction Z.

As described above, the rib5is thin, and therefore a step5zis formed in the upper surface of the rib5due to the lower electrode LE. In the vicinity of the step5zwith such configuration, defects such as cracks, for example, are likely to occur in the rib5. In the display device DSP1according to the comparative example, when some defect occurs in the rib5in the area near the step5zsurrounded by the chain line frame VII as shown inFIG.7, moisture that has penetrated through the organic insulating layer12to the area near the step5zmay enter the organic layer OR through the defect created in the rib5(see arrow AR inFIG.7).

By contrast, in the display device DSP of this embodiment, the peripheral edges of the lower electrodes LE (more specifically, the lower electrodes LE1, LE2and LE3) are located between the organic insulating layer12and the partition6(lower portion61), and steps (more specifically, steps5a,5b,5cand5d) of the rib5caused by the lower electrodes LE are covered by the partition6. With this configuration, even if some defects occurs in the vicinity of the steps of the rib5caused by the lower electrodes LE, such defects are covered by the partition6. Therefore, moisture that has penetrated through the organic insulating layer12to the vicinity of the steps of the rib5can be prevented from entering the organic layer OR from the defects made in the rib5. That is, the resistance of the display device DSP to moisture is improved.

As explained above, according to this embodiment, it is possible to provide a display device DSP with improved resistance to moisture.