Semiconductor devices having dual spacers and methods of fabricating the same

Semiconductor devices and methods of making the same are disclosed. According to one example, a semiconductor device having dual spacer may include a semiconductor substrate, a gate oxide film and a gate poly provided in a device region of the semiconductor substrate, a halo/pocket implant region formed in a region of the semiconductor substrate by which the gate poly is defined, and an inner spacer formed at a side wall of the gate poly for defining the width of a lower portion of the gate poly. The semiconductor device may also include an outer spacer formed at the side wall of the gate poly for defining the width of an upper portion of the gate poly, source/drain regions provided on the semiconductor substrate under the gate oxide film, and a salicide film provided on surfaces of the gate poly and the source/drain region.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices and, more particularly, semiconductor device having dual spacers and methods of fabricating the same.

BACKGROUND

With increased integration and operation speed of semiconductor devices, new semiconductor device fabrication technologies are actively being studied. For high operation speed of semiconductor devices, it is required to minimize the length of a path along which electrons move when a transistor is turned on. To this end, studies of a short channel transistor whose channel length, which is the distance between a source and a drain of the transistor, is reduced are being carried out. In addition, studies regarding the use of salicide for minimizing contact resistance between the gate of the transistor and subsequent wires are being progressed.

FIG. 1is a schematic diagram illustrating a configuration of a conventional semiconductor device. As shown inFIG. 1, a gate oxide film102and a gate poly104are formed in a device region of a semiconductor substrate100, and a spacer106made of an insulation film is formed on a side wall of the gate poly104. In addition, a Lightly Doped Drain (LDD)108, in which impurities of a conductivity type opposite to a conductivity type of the semiconductor substrate100are lightly doped, is formed on the semiconductor substrate100under the gate oxide film102. Source/drain regions110in which impurities of the same conductivity type as the LDD108are heavily doped are formed at a junction region of the semiconductor substrate100contacting with the LDD108. In addition, a salicide film112for lowering contact resistance is formed on the gate poly104and the source/drain regions110.

With the semiconductor device as configured above, for high operation speed of the transistor, the channel length between a source electrode and a drain electrode of the transistor should be reduced, as described above, and consequently, the width of the gate poly should be reduced. However, when the width of the gate poly is reduced, a serious narrow line effect may occur. Due to this effect, it is not easy to form the salicide on the gate poly. Accordingly, the conventional short channel transistor has a problem in that a characteristic of the transistor is deteriorated due to increased gate resistance.

As conventional solutions to overcome this problem, U.S. Pat. No. 6,100,561 discloses a method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation and U.S. Pat. No. 6,214,677 discloses a method of fabricating a self-aligned ultra short channel.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As disclosed herein, a semiconductor device constructed in accordance with the disclosed methods includes a short channel transistor having a gate area in which salicide is formed.

Referring toFIG. 2, a gate oxide film12and a gate poly14are formed in a device region of a semiconductor substrate10, and an inner spacer16made of a nitride film and an outer spacer18are formed on a side wall of the gate poly14.

Herein, the outer spacer18defines the width of an upper portion of the gate poly14and the inner spacer16defines the width of a lower portion of the gate poly14. To this end, the inner space16is provided inside the outer spacer18and is formed to be lower than the outer spacer18. Accordingly, the upper portion of the gate poly14is formed to be wider than the lower portion of the gate poly14. This prevents the area where a salicide20is to be formed from being reduced.

In addition, an LDD22in which impurities of a conductivity type opposite to a conductivity type of the semiconductor substrate10are lightly doped is formed on the semiconductor substrate10under the gate oxide film12, and source/drain regions24in which impurities of the same conductivity type as the LDD22are heavily doped are formed at a junction region of the semiconductor substrate10contacting with the LDD22. A halo/pocket implant region26is formed between the source/drain regions24. A final profile of the source/drain regions24after performing a thermal treatment process is shown inFIG. 2. The halo/pocket implant region26serves to prevent impurities doped into the source/drain regions from being diffused into a channel region under a gate electrode. Accordingly, it can be prevented that an electrical characteristic of the semiconductor device is deteriorated due to the diffusion of the impurities into the channel region.

In other words, as disclosed herein, because the impurities can be prevented from being diffused into the channel region, a conventional problem can be solved that it is difficult to distinguish between turn-on operation and turn-off operation of the semiconductor device as a threshold voltage is varied due to the diffusion of the impurities into the channel region, and consequently, malfunction of the semiconductor device may occur and leakage current may be increased.

In addition, a salicide film20made of cobalt, titanium, nickel, etc. for lowering contact resistance is formed on the gate poly14and the source/drain regions24. At this time, because the upper portion of the gate poly14is formed to be wider than the lower portion of the gate poly14, the salicide film20can be easily formed on the gate poly14. Accordingly, the problem of deterioration of the characteristic of the device due to the increase of gate resistance can be solved.

Hereinafter, an example method of fabricating the semiconductor device as constructed above will be described with reference toFIGS. 3ato3f. As shown inFIG. 3a, a first insulation film12′ and a second insulation film28are first deposited at a certain thickness on the semiconductor substrate, and a photoresist is applied on the second insulation film28and then is exposed and developed to form a damascene mask pattern30. The second insulation film28may be made of one selected from a group consisting of TEOS, MTO, USG and SiH4-rich oxide.

Subsequently, as shown inFIG. 3b, an opening32is formed by dry-etching the second insulation film28using the damascene mask pattern30as a mask, and then the damascene mask pattern30is removed.

Successively, as shown inFIG. 3c, the inner spacer16is formed on an inner wall of the opening32. More specifically, the inner spacer16can be formed by depositing a nitride film on the inner wall of the opening32and then etching the entire surface of the nitride film. In this entire surface etching process, a portion of the first insulation film12′ at the bottom of the opening32is removed.

Although according to one example the portion of the first insulation film12′ disposed under an inside space of the inner spacer16is removed when the inner spacer16is formed using the entire surface etching process, this is not essential.

After forming the inner spacer16as described above, the halo/pocket implant region26is formed in the semiconductor substrate10under the opening32using an implantation method.

Subsequently, as shown inFIG. 3d, the first insulation film12′ is again deposited in a portion where the first insulation film has been removed, and a polysilicon film is deposited thereon using a chemical vapor deposition (CVD) method and then is planarized until the second insulation film28is exposed using a chemical mechanical polishing (CMP) method. As a result, the gate poly14whose upper portion is wider than its lower portion is formed.

Next, as shown inFIG. 3e, the second insulation film28is removed by performing a wet etching process using solution containing HF (49%):H2O or NH4F:HF and then the LDD22is formed on the semiconductor substrate10using the inner spacer16and the gate poly14as a mask.

Subsequently, as shown inFIG. 3f, the outer spacer18is formed on side walls of the inner spacer16and the gate poly14. In this case, the outer spacer18can be formed by depositing a nitride film or an oxide film on the side walls of the inner spacer16and the gate poly14and patterning the nitride film or the oxide film using an entire surface etching process.

The first insulation film12′ surrounding the outer spacer18is removed when the entire surface etching process is performed, thereby forming the gate oxide12. After forming the gate oxide12as described above, the source/drain regions24are formed using the inner and outer spacers16and18and the gate poly as a mask, and then the salicide film20is formed on surfaces of the gate poly14and the source/drain regions24, as shown inFIG. 2.

Herein, the salicide film20is formed by forming a metal film such as cobalt, titanium or nickel on the entire surface of the semiconductor including the gate poly14and the spacers16and18using a sputtering process, performing a rapid thermal annealing (RTA) process for the semiconductor substrate10, and selectively removing a portion of the metal film, which does not react with silicon of the semiconductor substrate, using wet etchant.

Although not shown, after the salicide film20is formed, a PMD is deposited and planarized on the entire surface of the semiconductor substrate10and the PDM is selectively etched to form a contact hole. After that, a tungsten plug is formed in the contact hole to thereby form a contact for electrically connecting device electrodes to metal wire layers. Finally, for completing the semiconductor device, a metal film is deposited and patterned on the PMD to thereby form a metal wire layer consisting of the patterned metal film connected to the tungsten plug.

As is apparent from the above description, because the width of the gate poly can be sufficiently secured in order to form the salicide film, the short channel transistor can be fabricated using a damascene process without purchasing additional equipments, and the narrow line effect, which may occur due to the reduction of the width of the gate poly in the short channel transistor, can be suppressed. Accordingly, since the salicide film is easily formed on the gate poly, the problem can be solved that the device characteristic is deteriorated due to the increase of the gate resistance.

This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application entitled “Semiconductor Device with Dual Space and Method for Manufacturing the Same” filed in the Korean Industrial Property Office on Oct. 23, 2003, and there duly assigned Ser. No. 10-2003-0074451.

Disclosed herein are short channel transistors that are capable of sufficiently securing a gate area in which salicide is formed. Methods for fabricating the same are also disclosed.

An example semiconductor device constructed in accordance with the foregoing may include a semiconductor substrate, a gate oxide film and a gate poly provided in a device region of the semiconductor substrate, a halo/pocket implant region formed in a region of the semiconductor substrate by which the gate poly is defined, and an inner spacer formed at a side wall of the gate poly and defining the width of a lower portion of the gate poly. The example device may also include an outer spacer formed at the side wall of the gate poly and defining the width of an upper portion of the gate poly, source/drain regions provided on the semiconductor substrate under the gate oxide film, and a salicide film provided on surfaces of the gate poly and the source/drain region.

In one particular example, the inner spacer is formed to be lower than the outer spacer such that the width of the upper portion of the gate poly is wider than the width of the lower portion of the gate poly. Additionally, the halo/pocket implant region serves to prevent impurities, for example, boron (B) or phosphor (P), doped into the source/drain regions from being diffused into a channel region under a gate electrode when the impurities are heat-treated. Accordingly, it can be prevented that an electrical characteristic of the semiconductor device is deteriorated due to the diffusion of the impurities into the channel region. In other words, a problem can be solved that it is difficult to distinguish between turn-on operation and turn-off operation of the semiconductor device as a threshold voltage is varied due to the diffused impurities, and consequently, malfunction of the semiconductor device may occur and leakage current may be increased.

An example method of fabricating such a device includes depositing first and second insulation films on a semiconductor substrate sequentially and patterning the second insulation film to form an opening, forming an inner spacer on an inner wall of the opening, depositing a polysilicon on the opening and forming a gate poly by planarizing the polysilicon, and removing the second insulation film and forming an LDD using the gate poly and the inner spacer as a mask. The method may also include forming an outer spacer on side walls of the gate poly and the inner spacer, forming source/drain regions using the gate poly and the outer spacer as a mask, and forming a salicide film on the gate poly and the source/drain regions.

According to one arrangement, the inner spacer is formed to be lower than the outer spacer such that the width of an upper portion of the gate poly is wider than the width of a lower portion of the gate poly. The example method may also include, between forming the inner spacer and forming the gate poly, forming a halo/pocket implant region on the semiconductor substrate under the opening using an implantation method. In one example, the inner spacer is formed by depositing a spacer film made of a nitride film and patterning the spacer film using an entire surface etching process, and the outer spacer is formed by depositing a spacer film made of an oxide film or a nitride film and patterning the spacer film using an entire surface etching process.

When the inner spacer is formed using the entire surface etching process, the first insulation film disposed under an inside space of the inner spacer may be removed using the entire surface etching process. In this case, when the gate poly is formed, the first insulation film may again be deposited in a portion where the first insulation film has been removed. Alternatively, when the inner spacer is formed using the entire surface etching process, the first insulation film disposed under an inner space of the inner spacer may not be removed.

The second insulation film may be one selected from a group consisting of TEOS (Tetra Ethyl Ortho Silicate), MTO (Middle Temperature Oxide), USG (Undoped Silica Glass) and SiH4-rich oxide, and is removed by a wet etching process using solution containing HF (49%):H2O or NH4F:HF. In one example, the salicide film is made of titanium (Ti), cobalt (Co), or nickel (Ni).

Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.