Non-volatile memory apparatus and erasing method thereof

The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.

BACKGROUND

1. Field of the Invention

The invention relates to a non-volatile memory apparatus and an erasing method thereof. Particularly, the invention relates to a non-volatile memory apparatus capable of erasing at least one of memory sectors which disposed in a same well.

2. Description of Related Art

In prior art, when an erasing operation is operated on a flash memory apparatus, all the memory sectors disposed in a same well must be erased simultaneously. Referring toFIG. 1A, a flash memory apparatus110includes memory sector0MS0and a memory sector1MS1, a sector0selector SSD0and a sector1selector SSD1. The sector0selector SSD0corresponds to the memory sector0MS0, and the sector1selector SSD1corresponds to the memory sector1MS1. The memory sector0MS0and the memory sector1MS1are respectively disposed in different wells. The sector0selector SSD0is disposed between the memory sector0MS0and the memory sector1MS1for separating the memory sector0MS0and the memory sector1MS1. When an erasing operation is operated on the flash memory apparatus110, at least one of the memory sector0MS0and the memory sector1MS1is selected for erasing, and all of the memory cells in the selected memory sector are erased simultaneously. That is, in prior art, it is impossible to erase a part of memory cells of the memory sector0MS0or the memory sector1MS1, and a small size memory sector erasing capability can not be achieved in the flash memory apparatus100.

On the other hand, for the small size memory sector erasing purpose, another prior art flash memory apparatus120is shown asFIG. 1B. The memory sector0MS0inFIG. 1Acan be divided into a memory sector01MS01and a memory sector02MS02inFIG. 1B, and the memory sector1MS1inFIG. 1Acan be divided into a memory sector11MS11and a memory sector12MS12inFIG. 1B. Furthermore, the memory sectors MS01˜MS12can be respectively disposed in four different wells, and two sector selectors SSD01and SSD02and two sector selectors SSD11and SSD12are necessary. The sector01selector SSD01corresponds to the memory sector01MS01, the sector02selector SSD02corresponds to the memory sector02MS02, the sector11selector SSD11corresponds to the memory sector11MS11, and the sector12selector SSD12corresponds to the memory sector12MS12. That is, the number of wells and the sector selecting devices are increased in the flash memory apparatus120, and the chip size of the flash memory apparatus120is increased.

SUMMARY OF THE INVENTION

The invention is directed to a non-volatile memory apparatus and an erasing method thereof, which can erase one of a plurality of memory sectors disposed in the same well.

The invention provides a non-volatile memory apparatus. The non-volatile memory apparatus includes a plurality of first memory sectors and a control voltage provider. The first memory sectors disposed in a first well, wherein, each of the first memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider is coupled to the first memory sectors for providing the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the first memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.

The invention also provides an erasing method for a non-volatile memory apparatus. The step of the erasing method includes: providing a plurality of control line signals to a plurality of memory cells of each of a plurality of first memory sectors in the non-volatile memory apparatus, wherein the first memory sectors are disposed in a first well; when an erasing operation is operated, selecting one of the first memory sectors for erasing; providing the control line signals of the selected memory sector with an erase control voltage; and providing the control line signals of the un-selected memory sectors with a un-erase control voltage, wherein voltage levels of the erase control voltage and the un-erase control voltage are different.

According to the above descriptions, in the invention, the erasing operation may be operated on one or some of a plurality of memory sectors which are disposed in a same well. In consideration for a small size memory sector erasing capability, large amount of cells for disposing memory sectors is not necessary. Corresponding, isolated transistors are not necessary for the non-volatile memory apparatus according to the presented application. Such as that, chip size of the non-volatile memory apparatus can be reduced.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

Referring toFIG. 2,FIG. 2is a block diagram of a non-volatile memory apparatus200according to an embodiment of the invention. The non-volatile memory apparatus200includes a plurality of memory sectors MS1-MSN and a control voltage provider210. The memory sectors MS1-MSN are disposed in a well201. The well201may be a N-type well. When an erasing operation is operated on the non-volatile memory apparatus200, and at least one of the memory sectors MS1˜MSN is selected for erasing, the control voltage provider210provides control line signals to the selected memory sector with an erase control voltage and provides control line signals to the un-selected memory sector with a un-erase control voltage. For example, if the memory sector MS1is selected for erasing and the memory sector MSN is not selected for erasing, the control line signals CLS1and CSL2are provided by the control voltage provider210, wherein, a voltage level of the control line signals CLS1equals to the erase control voltage, and a voltage level of the control line signals CLS2equals to the un-erase control voltage. In this embodiment, the erase control voltage may equal to −6.5V and the un-erase control voltage may equal to 6.5V.

On the other hand, when the erasing operation is operated, a voltage applied on the well210may equal to 6.5V, and a voltage level on the word line signals WLS1-WLS2may equal to 3.0V. That is, the voltage levels of the voltage applied on the well210and the un-erase control voltage are the same. The voltage level of the un-erase control voltage is additive inverse of the voltage level of the erase control voltage.

Referring toFIG. 3A,FIG. 3Ais a block diagram of a non-volatile memory apparatus300according to another embodiment of the invention. The non-volatile memory apparatus300includes memory sectors310and320and a control voltage provider350. The memory sectors310and320are disposed in a same well, and a voltage is applied on the well which is coupled to a source line SL of all of memory cells in the memory sectors310and320. In this embodiment, the well may be a N-type well. Each of the memory cells (ex. memory cell311and memory cell321) includes two P-type transistors. A plurality of word line signals ZWL0_0-ZWL63_0and ZWL0_1-ZWL63_1are respectively transported to memory cells of memory sectors310and320. A plurality of control line signals ZCL0_0-ZCL63_0and ZCL0_1-ZCL63_1are respectively transported to memory cells of memory sectors310and320, too. When an erasing operation is operated, one of the memory sectors310and320is selected for erasing and the control voltage provider350provides the control line signals ZCL0_0-ZCL63_0and ZCL0_1-ZCL63_1of the selected memory sector with an erase control voltage and provides the control line signals ZCL0_0-ZWL63_0and ZCL0_1-ZCL63_1of the un-selected memory sectors with a un-erase control voltage.

For example, when the erasing operation is operated, the memory sector310is selected to be the selected memory sector, and the memory sector320may be selected to be the un-selected memory sector. The control voltage provider350may provide the control line signals ZCL0_0-ZCL63_0with the erase control voltage, and provide the control line signals ZCL0_1-ZCL63_1with the un-erase control voltage. Wherein, a voltage level of the un-erase control voltage may be equaled to a voltage level on the source line SL, and a voltage level of the erase control voltage may be smaller than the voltage level of the un-erase control voltage. In this embodiment, the voltage levels of the erase control voltage and the un-erase control voltage may be −6.5V and 6.5V respectively, and the voltage level of the source line may be 6.5V.

On the other hand, when the erasing operation is operated, voltage levels of the word line signals ZWL0_0-ZWL63_0and ZWL0_1-ZWL63_1may be the same. In this embodiment, the voltage level of the word line signals ZWL0_0-ZWL63_0and ZWL0_1-ZWL63_1may be 3.0V.

In such manner, the memory cells in the memory sector310are erased, and the memory cells in the memory sector320are not erased. That is, only one or some of all of the memory sectors disposed in same well may be selected to be erased, and a small size memory sector erasing capability is achieved.

Please noted here, the memory cells311and321formed by two transistors are only for reference and do not use to limit scope of present application. Any memory cell for flash memory can be used in the memory apparatus300.

On the other hand, a sector selecting device340is also disposed in the non-volatile memory apparatus300, and the sector selecting device340is coupled to the bit lines of the memory cells in the memory sectors310and320. Further, the sector selecting device340is also coupled to another memory sector390.

Please note here, the sector selecting device340is used to isolate the memory sector320from the memory sector390when the erasing operation is operated on at least one of the memory sectors310and320. On the other hand, the sector selecting device340is used for memory cell selection when a program or read operation in operated on the non-volatile memory apparatus300.

Referring toFIG. 3B,FIG. 3Bis a block diagram of the sector selecting device according to the embodiment inFIG. 3Aof the invention. InFIG. 3B, the sector selecting device340includes a plurality of transistors MI1˜MI8. First ends of the transistors MI1and MI2are respectively coupled to bit lines BL0_0_0and BL0_0_1, and second ends of the transistors MI1and MI2are coupled to a main bit line MBL0. First ends of the transistors MI5and MI6are coupled to the main bit line MBL0, and second ends of the transistors MI5and MI6are respectively coupled to bit lines BL1_0_0and BL1_0_1. The bit lines BL0_0_0and BL0_0_1are bit lines from the memory sectors310and320, and the bit lines BL1_0_0and BL1_0_1are bit lines from another memory sector. Moreover, first ends of the transistors MI3and MI4are respectively coupled to bit lines BL0_127_0and BL0_127_1, and second ends of the transistors MI3and MI4are coupled to a main bit line MBL127. First ends of the transistors MI7and MI8are coupled to the main bit line MBL127, and second ends of the transistors MI7and MI8are respectively coupled to bit lines BL1_127_0and BL1_127_1. The bit lines BL0_127_0and BL0_127_1are bit lines from the memory sectors310and320, and the bit lines BL1_127_0and BL_1_127_1are bit lines from another memory sector.

Referring toFIG. 4,FIG. 4is a circuit diagram of a control voltage provider according to an embodiment of the invention. The control voltage provider400includes voltage selectors410and420. The voltage selector410is coupled to a first vertical control signal line ZCLV0and a first voltage line VBCS0. The voltage selector410selects a voltage on one of the first vertical control signal line ZCLV0and the first voltage line VBCS0according to an operation control signal PU0for generating the control line signals ZCL0_0and ZCL1_0. The voltage selector420is coupled to a second vertical control signal line ZCLV1and a second voltage line VBCS1. The voltage selector420selects a voltage on one of the second vertical control signal line ZCLV1and the second voltage line VBCS1according to an operation control signal PU1for generating the control line signals ZCL0_1and ZCL1_1. It should be noted here, the control line signals ZCL0_0and ZCL1_0are provided to the memory cells in a first memory sector and the control line signals ZCL0—1and ZCL1_1are provided to the memory cells in a second memory sector, wherein, the first and second memory sectors are disposed in the same well.

InFIG. 4, the voltage selector410includes transistors T1-T4respectively form four switches. The transistor T1is coupled between the first vertical control signal line ZCLV0and an output end of the voltage selector410, and is controlled by the operation control signal PU0. The transistor T2is coupled between the first voltage line VBCS0and the output end of the voltage selector410, and is controlled by the operation control signal PU0. The transistor T3is coupled between the first vertical control signal line ZCLV0and another output end of the voltage selector410, and is controlled by the operation control signal PU0. The transistor T4is coupled between the first voltage line VBCS0and the output end (which the transistor T3coupled to) of the voltage selector410, and is controlled by the operation control signal PU0. The control line signals ZCL0_0and ZCL1_0are provided to the first memory sector.

On the other hand, the voltage selector420includes transistors T5-T8respectively form four switches. The transistor T5is coupled between the second vertical control signal line ZCLV1and an output end of the voltage selector420, and is controlled by the operation control signal PU0. The transistor T6is coupled between the second voltage line VBCS1and the output end of the voltage selector420, and is controlled by the operation control signal PU0. The transistor T7is coupled between the second vertical control signal line ZCLV1and another output end of the voltage selector420, and is controlled by the operation control signal PU1. The transistor T8is coupled between the second voltage line VBCS1and the output end (which the transistor T7coupled to) of the voltage selector420, and is controlled by the operation control signal PU1. The control line signals ZCL0_1and ZCL1_1are provided to the second memory sector.

When an erasing operation is operated, the first memory sector is selected to be erased, and the second memory sector is not selected to be erased, the voltage selector410provides the control line signals ZCL0_0and ZCL1_0with an erase control voltage (ex. −6.5V) and the control line signals ZCL0_1and ZCL1_1with an un-erase control voltage (ex. 6.5V).

That is, when the erasing operation is operated, the erase control voltage is provided to the first voltage line VBCS0and the un-erase control voltage is provided to the second vertical control signal line ZCLV1. Voltage levels of the first vertical control signal line ZCLV0and the second voltage line VBCS1are 0V. Furthermore, voltage levels of the operation control signals PU0and PU1are 0V.

Referring toFIG. 5,FIG. 5is another circuit diagram of a control voltage provider according to an embodiment of the invention. The control voltage provider400includes voltage selectors510and520. The voltage selector510is coupled to the first vertical control signal line ZCLV0, the second vertical control signal line ZCLV1and a first voltage line VBS0. The voltage selector510selects a voltage on one of the first and second vertical control signal lines ZCLV0, ZCLV1and the first voltage line VBCS0according to the operation control signal PU0for generating the control line signals ZCL0_0and ZCL1_0. The voltage selector520is coupled to the first and second vertical control signal lines ZCLV0, ZCLV1and a second voltage line VBCS1. The voltage selector520selects a voltage on one of the first and second vertical control signal line ZCLV0, ZCLV1and the second voltage line VBCS1according to the operation control signal PU1for generating the control line signals ZCL0_1and ZCL1_1.

InFIG. 5, the voltage selector510includes transistors T9-T12respectively form four switches. The transistor T9is coupled between the first vertical control signal line ZCLV0and an output end of the voltage selector510, and is controlled by the operation control signal PU0. The transistor T10is coupled between the first voltage line VBCS0and the output end of the voltage selector510, and is controlled by the operation control signal PU0. The transistor T11is coupled between the second vertical control signal line ZCLV1and another output end of the voltage selector510, and is controlled by the operation control signal PU0. The transistor T12is coupled between the first voltage line VBCS0and the output end (which the transistor T11coupled to) of the voltage selector510, and is controlled by the operation control signal PU0. The control line signals ZCL0_0and ZCL1_0are provided to the first memory sector.

On the other hand, the voltage selector520includes transistors T13-T16respectively form four switches. The transistor T13is coupled between the first vertical control signal line ZCLV0and an output end of the voltage selector520, and is controlled by the operation control signal PU1. The transistor T14is coupled between the second voltage line VBCS1and the output end of the voltage selector520, and is controlled by the operation control signal PU1. The transistor T15is coupled between the second vertical control signal line ZCLV1and another output end of the voltage selector520, and is controlled by the operation control signal PU1. The transistor T16is coupled between the second voltage line VBCS1and the output end (which the transistor T15coupled to) of the voltage selector520, and is controlled by the operation control signal PU1. The control line signals ZCL0_1and ZCL1_1are provided to the second memory sector.

When an erasing operation is operated, the first memory sector is selected to be erased, and the second memory sector is not selected to be erased, the voltage selector510provides the control line signals ZCL0_0and ZCL1_0with the erase control voltage (ex. −6.5V) and the control line signals ZCL0_1and ZCL1_1with the un-erase control voltage subtracted by a threshold voltage (ex. 6.5V−Vt). The threshold voltage Vt is a turned on voltage of the transistor of transistors T14and T16.

That is, when the erasing operation is operated, the erase control voltage is provided to the first voltage line VBCS0and the un-erase control voltage is provided to the second voltage line VBCS1. Voltage levels of the first and second vertical control signal lines ZCLV0and ZCLV1are 0V. Furthermore, voltage levels of the operation control signals PU0and PU1are respectively 0V and 6.5V.

Referring toFIG. 6,FIG. 6is a block diagram of a non-volatile memory apparatus600according to another embodiment of the invention. The non-volatile memory apparatus600may be a flash memory apparatus. The non-volatile memory apparatus600includes memory sectors610-640and a control voltage provider650. The memory sectors610and620disposed in a first well601, and the memory sectors630and640are disposed in a second well602. The wells601and602are different wells, and in this embodiment, types of well601and602are the same.

The well601is coupled to a source line SL1of memory cells in memory sectors610and620. The well602is coupled to a source line SL2of memory cells in memory sectors630and640. The word line signals WLS1-WLS are respectively provided to memory cells of the memory sectors610-640.

The control voltage provider650is coupled to the memory sectors610-640, and respectively provides a plurality of control line signals CLS1-CLS4to the memory sectors610-640. When one of the memory sectors610and620is erased, the control voltage provider650may provide one of the control line signals CLS1-CLS2(ex. CLS1) with an erase control voltage for erasing one of the memory sectors610-620(ex.610), and provide the control line signal CLS2with an un-erase control voltage to prevent the memory sector620from erasing. For the memory sectors630and640which are not selected for erasing, the control voltage provider650may provide the control line signal CSL3-CLS4with 0V which is between the un-erase control voltage and the erase control voltage.

On the other hand, the control voltage provider650may support a programming operation of the non-volatile memory apparatus600. In the programming operation, memory cells on one of the control lines are selected and the corresponding control line signal can be set to a programming control voltage (ex. 6.5V). The source line corresponding to the selected memory cells may be coupled to a high voltage (ex. 5V), and another source line may be coupled to a low voltage (ex. 3V). Furthermore, voltage levels of the control line signals of the unselected control lines may be set to the low voltage, and the programming operation can be achieved.

Referring toFIG. 7,FIG. 7is a flow chart of an erasing method for a non-volatile memory apparatus according to an embodiment of the invention. The method includes: in step S710, providing a plurality of control line signals to a plurality of memory cells of each of a plurality of first memory sectors in the non-volatile memory apparatus, wherein the first memory sectors are disposed in a first well; in step S720, when an erasing operation is operated, selecting one of the first memory sectors for erasing; in step S730, providing the control line signals of the selected memory sector with an erase control voltage; and in step S740, providing the control line signals of the un-selected memory sectors with an un-erase control voltage.

Operation details of the method for erasing the non-volatile memory apparatus of the present embodiment have been described in detail in the aforementioned embodiment with reference of the non-volatile memory apparatus, so that detailed descriptions thereof are not repeated.

In summary, each of the memory sectors in a same well is controlled by voltage levels of the control lines signals. That is, one or some memory sectors in a same well can be erased through the control line signal provided by the control voltage provider. A small size memory sector erasing capability is achieved without increasing chip size of the non-volatile memory apparatus.