Current sensing amplifier and sensing method thereof

A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage.

FIELD OF THE INVENTION

The present invention relates to a current sensing amplifier and a sensing method thereof, and more particularly to a current sensing amplifier of a non-volatile memory device and a sensing method thereof.

BACKGROUND OF THE INVENTION

As is well known, a non-volatile memory device such as a SD card is widely used in a variety of electronic devices. Generally, the non-volatile memory device comprises a memory array, and the memory array comprises plural cells. Each cell comprises a floating gate transistor. The floating gate transistor of each cell has a floating gate to store hot carriers. The storing state of the floating gate transistor may be determined according to the amount of the stored hot carriers.

Generally, after the hot carriers are injected into the floating gate transistor, a threshold voltage (VTH) of the floating gate transistor is changed according to the amount of the injected hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.

During a program cycle of the non-volatile memory device, the threshold voltage of the floating gate transistor may be changed by controlling the amount of hot carriers to be injected into the floating gate. During a read cycle of the non-volatile memory device, a read voltage is provided to the floating gate transistor, and thus a cell current (also referred as a read current) is generated. According to the magnitude of the cell current, the storing state (e.g. an on state or an off state) of the floating gate transistor may be realized.

For example, if the read voltage is provided to the floating gate transistor with the lower threshold voltage, the floating gate transistor is in the on state to generate a higher cell current. Whereas, if the read voltage is provided to the floating gate transistor with the higher threshold voltage, the floating gate transistor is in the off state to generate a nearly-zero cell current. That is, during the read cycle, the on-state cell may generate a higher cell current, but the off-state cell may generate a lower cell current.

Moreover, the non-volatile memory device further comprises a current sensing amplifier for receiving the cell current from the cell, thereby determining the storing state of the cell.

FIG. 1is a schematic circuit diagram illustrating a conventional current sensing amplifier. As shown inFIG. 1, the current sensing amplifier comprises three transistors M1, M2, M3, an operational amplifier OP, and a comparator CMP. The transistor M1and the operational amplifier OP are collaboratively defined as a clamp circuit. The drain terminal of the transistor M1is connected with a data line DL in order to receive a cell current Icell from the cell. The gate terminal of the transistor M1is connected with the output terminal of the operational amplifier OP. The source terminal of the transistor M1is connected with a low voltage source Vss. Moreover, a first input terminal of the operational amplifier OP receives an input voltage Vdl, and a second input terminal of the operational amplifier OP is connected with the drain terminal of the transistor M1. Consequently, in a normal working condition, the magnitude of the drain voltage V1of the transistor M1of the clamp circuit is equal to the magnitude of the input voltage Vdl.

Moreover, a bias voltage Vbias is received by the gate terminal of the transistor M3, and thus the transistor M3is served as a current source to generate a reference current Iref. The reference current Iref is received by the drain terminal of the transistor M2. The gate terminal of the transistor M2is connected with the gate terminal of the transistor M1. The source terminal of the transistor M2is connected with the low voltage source Vss. A first input terminal of the comparator CMP is connected with the drain terminal of the transistor M2for receiving the drain voltage V2of the transistor M2. A second input terminal of the comparator CMP receives the input voltage Vdl. An output data is outputted from the output terminal of the comparator CMP.

During the read cycle, the data line DL is connected with the cell to receive the cell current. When the cell is in the on state, the magnitude of the cell current Icell is higher than the magnitude of the reference current Iref, and the drain voltage V2of the transistor M2is lower than the input voltage Vdl. Consequently, the comparator CMP issues a first logic level (e.g. a low level). On the other hand, when the cell is in the off state, the magnitude of the cell current Icell is lower than the magnitude of the reference current Iref, and the drain voltage V2of the transistor M2is higher than the input voltage Vdl. Consequently, the comparator CMP issues a second logic level (e.g. a high level).

From the above discussions, the conventional current sensing amplifier can determine the storing state of the cell according to the cell current Icell generated by the cell. However, since the conventional current sensing amplifier needs the operational amplifier OP, some drawbacks occur. For example, since a DC bias current should be provided to the operational amplifier OP during normally operating of the operational amplifier OP, the power consumption of the conventional current sensing amplifier is high.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a sensing method of a current sensing amplifier for determining a storing state of a cell of a non-volatile memory device during a read cycle. The sensing method includes the following steps. First of all, after a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage. If the sensing voltage of the sensing node is lower than the preset voltage, the cell is in a first storing state. Whereas, if the sensing voltage of the sensing node is higher than the preset voltage, the cell is in a second storing state.

Another embodiment of the present invention provides a current sensing amplifier for determining a storing state of a first cell of a non-volatile memory device during a read cycle. The current sensing amplifier includes a reference unit and a first sensing unit. Basically, the circuit structures of the reference unit and the first sensing unit are identical. The reference unit includes a constant voltage providing circuit and a comparing circuit. The constant voltage providing circuit and the comparing circuit are connected with a reference node. After the reference node is adjusted to a constant voltage by the constant voltage providing circuit according to an activating signal, the reference node is connected with a reference current source to receive a reference current from the reference current source. The first sensing unit includes a constant voltage providing circuit and a latching circuit. The constant voltage providing circuit and the latching circuit are connected with a first sensing node. After the first sensing node is adjusted to the constant voltage by the constant voltage providing circuit according to the activating signal, the first sensing node is connected with a first data line to receive a first cell current from the first cell. When the comparing circuit detects that a reference voltage of the reference node reaches a preset voltage, the comparing circuit issues a latching signal to the latching circuit, so that the latching circuit determines whether the first cell is in a first storing state or a second storing state according to a relationship between a first sensing voltage of the first sensing node and the preset voltage.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

According to the properties of the non-volatile memory device, during the read cycle, different magnitudes of the cell current (also referred as a read current) are generated according to the storing state of the cell. If the cell of the non-volatile memory device has an n-type floating gate transistor (storage transistor), the cell may generate a cell current I1in the on state but generate a cell current I2in the off state. In accordance with the present invention, a reference current source may provide a reference current Iref. The magnitude of the reference current Iref is in the range between I1and I2. That is, I1>Iref>I2.

The present invention provides a sensing method of a current sensing amplifier.FIG. 2is a schematic flowchart illustrating a sensing method of a current sensing amplifier according to an embodiment of the present invention. Firstly, during a read cycle, a sensing node and a reference node are pre-charged to a constant voltage simultaneously (Step S201).

Then, the sensing node is connected with a data line to receive a cell current, and the reference node is connected with the reference current source to receive a reference current (Step S203). Consequently, the reference voltage of the reference node varies from the constant voltage.

Then, a reference voltage of the reference node is compared with a preset voltage, and a step S205is performed to determine whether the reference voltage reaches the preset voltage.

When the reference voltage of the reference node reaches the preset voltage, the storing state of the cell is determined according to the relationship between the sensing voltage of the sensing node and the preset voltage (Step S207). That is, if the sensing voltage of the sensing node is lower than the preset voltage, the cell is in a first storing state such as an on state (Step S208). Whereas, if the sensing voltage of the sensing node is higher than the preset voltage, the cell is in a second storing state such as an off state (Step S209).

The current sensing amplifier for implementing the above sensing method will be illustrated in more details as follows.

FIG. 3is a schematic circuit block diagram illustrating the concepts of a current sensing amplifier of the present invention. As shown inFIG. 3, the current sensing amplifier comprises a reference unit300, a first sensing unit310, and a second sensing unit320. The structures of the first sensing unit310and the second sensing unit320are substantially identical.

The reference unit300comprises a constant voltage providing circuit302and a comparing circuit304. The constant voltage providing circuit302and the comparing circuit304are connected with a reference node Nref. During the read cycle, the reference node Nref is adjusted to a constant voltage by the constant voltage providing circuit302. Then, the reference node Nref is connected with the reference current source to receive a reference current Iref. Meanwhile, the comparing circuit304starts to compare a reference voltage Vref of the reference node Nref with a preset voltage Vset. When the reference voltage Vref reaches the preset voltage Vset, the comparing circuit304issues a latching signal Lat to the first sensing unit310and the second sensing unit320.

The first sensing unit310comprises a constant voltage providing circuit312and a latching circuit314. The constant voltage providing circuit312and the latching circuit314are connected with a first sensing node Nsen1. During the read cycle, the first sensing node Nsen1is adjusted to the constant voltage by the constant voltage providing circuit312. Then, the first sensing node Nsen1is connected with a first data line DL1to receive a first cell current Icell1. When the latching signal Lat is received by the latching circuit314, the latching circuit314generates a first output signal Dout1according to the relationship between a first sensing voltage Vsen1of the first sensing node Nsen1and the preset voltage Vset. The first output signal Dout1may denote the storing state of a first cell.

Similarly, the second sensing unit320comprises a constant voltage providing circuit322and a latching circuit324. The constant voltage providing circuit322and the latching circuit324are connected with a second sensing node Nsen2. During the read cycle, the second sensing node Nsen2is adjusted to the constant voltage by the constant voltage providing circuit322. Then, the second sensing node Nsen2is connected with a second data line DL2to receive a second cell current Icell2. When the latching signal Lat is received by the latching circuit324, the latching circuit324generates a second output signal Dout2according to the relationship between a second sensing voltage Vsen2of the second sensing node Nsen2and the preset voltage Vset. The second output signal Dout2may denote the storing state of a second cell.

For clarification and brevity, one reference unit300and two sensing units310and320are shown inFIG. 3. It is noted that the number of the sensing units may be varied according to the practical requirements. For example, in some other embodiments, the current sensing amplifier comprises a reference unit300and one sensing unit. Alternatively, in some other embodiments, the current sensing amplifier comprises a reference unit300and more than two sensing units.

FIG. 4Ais a schematic circuit diagram illustrating a current sensing amplifier according to a first embodiment of the present invention.FIGS. 4B and 4Care schematic timing waveform diagrams illustrating associated signals processed by the current sensing amplifier according to the first embodiment of the present invention.

InFIG. 4A, only a reference unit400and a first sensing unit410are shown. It is noted that the current sensing amplifier may comprise a reference unit and plural sensing units with identical structures.

In this embodiment, the current sensing amplifier comprises the reference unit400, the first sensing unit410, and two switch elements SW0and SW1. The reference unit400comprises a constant voltage providing circuit402and a comparing circuit404. The constant voltage providing circuit402and the comparing circuit404are connected with a reference node Nref. The constant voltage providing circuit402comprises a transistor Mc. The source terminal of the transistor Mc is connected with a power supply voltage Vdd. The gate terminal of the transistor Mc receives an activating signal Vpre. The drain terminal of the transistor Mc is connected with the reference node Nref. Moreover, the comparing circuit404comprises two transistors Ma, Mb, and two inverters406,408. The source terminal of the transistor Ma is connected with the power supply voltage Vdd. The gate terminal of the transistor Ma is connected with the reference node Nref. The drain terminal of the transistor Mb is connected with the drain terminal of the transistor Ma. The source terminal of the transistor Mb is connected with a ground voltage Vss. The gate terminal of the transistor Mb is connected with the reference node Nref. The input terminal of the inverter406is connected with the drain terminal of the transistor Mb. The output terminal of the inverter406is connected with the reference node Nref. The input terminal of the inverter408is connected with the input terminal of the inverter406. A latching signal Lat is outputted from the output terminal of the inverter408. Moreover, the inverter406is controlled by the latching signal Lat. When the latching signal Lat is in a high-level state, the inverter406is disabled. When the latching signal Lat is in a low-level state, the inverter406is enabled.

The switch element SW0is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW0is in a closed state. Consequently, the reference node Nref is connected with the reference current source to receive a reference current Iref. When the latching signal Lat is in the low-level state, the switch element SW0is in an open state. Consequently, the connection between the reference node Nref and the reference current source is interrupted.

The first sensing unit410comprises a constant voltage providing circuit412and a latching circuit414. The constant voltage providing circuit412and the latching circuit414are connected with a first sensing node Nsen1. The constant voltage providing circuit412comprises a transistor M3. The source terminal of the transistor M3is connected with the power supply voltage Vdd. The gate terminal of the transistor M3receives the activating signal Vpre. The drain terminal of the transistor M3is connected with the first sensing node Nsen1. Moreover, the latching circuit414comprises two transistors M1, M2, and two inverters416,418. The source terminal of the transistor M1is connected with the power supply voltage Vdd. The gate terminal of the transistor M1is connected with the first sensing node Nsen1. The drain terminal of the transistor M2is connected with the drain terminal of the transistor M1. The source terminal of the transistor M2is connected with the ground voltage Vss. The gate terminal of the transistor M2is connected with the first sensing node Nsen1. The input terminal of the inverter416is connected with the drain terminal of the transistor M2. The output terminal of the inverter416is connected with the first sensing node Nsen1. The input terminal of the inverter418is connected with the input terminal of the inverter416. A first output signal Dout1is outputted from the output terminal of the inverter418. Moreover, the inverter416is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the inverter416is disabled. When the latching signal Lat is in the low-level state, the inverter416is enabled, and thus the latching circuit414is normally operated.

The switch element SW1is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW1is in a closed state. Consequently, the first sensing node Nsen1is connected with a first data line DL1to receive a first cell current Icell1. When the latching signal Lat is in the low-level state, the switch element SW1is in an open state. Consequently, the connection between the first sensing node Nsen1and the first data line DL1is interrupted.

In this embodiment, the transistors Ma and Mb are collaboratively defined as an inverter. A transition voltage of this inverter is the preset voltage Vset. That is, if the reference voltage Vref is lower than the preset voltage Vset, this inverter issues a high voltage level. Whereas, if the reference voltage Vref is higher than the preset voltage Vset, this inverter issues a low voltage level. Moreover, the structure of the transistor M1is identical to the structure of the transistor Ma, and the structure of the transistor M2is identical to the structure of the transistor Mb. Moreover, the transistors M1and M2are collaboratively defined as an inverter. A transition voltage of this inverter is the preset voltage Vset. As known, by adjusting the sizes of the transistors Ma and Mb, the transition voltage is adjusted, and thus the preset voltage Vset is correspondingly adjusted. Hereinafter, the operations of the current sensing amplifier will be illustrated with reference toFIGS. 4B and 4C, wherein Vset=Vdd/2.

FIG. 4Bis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 4Aduring the read cycle, in which the storing state of the cell is the off state.

From the time point t0to the time point t2, the transistor Mc of the constant voltage providing circuit402of the reference unit400and the transistor M3of the constant voltage providing circuit412of the first sensing unit410are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are pre-charged to the power supply voltage Vdd. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the power supply voltage Vdd. Moreover, at the time point t1, the reference node Nref and the first sensing node Nsen1are charged to the preset voltage Vset, the latching signal Lat and the first data line DL1are changed to a high-level state, and at the time point t2, the transistor Mc and the transistor M3are turned off according to the activating signal Vpre.

Moreover, at the time point t1, the latching signal Lat from the comparing circuit404is in the high-level state. Consequently, the latching circuit414is disabled, and the switch elements SW0and SW1are both in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Mc and the transistor M3are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1drop drown.

Since the storing state of the cell is the off state, the first cell current Icell1is equal to the cell current I2. That is, the reference current Iref is higher than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref drops down at a faster rate, while the first sensing voltage Vsen1of the first sensing node Nsen1drops down at a slower rate.

At the time point t3, the reference voltage Vref of the reference node Nref drops down to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit404is in the low-level state. Since the latching signal Lat is in the low-level state, the switch elements SW0and SW1are both in the open state, and the latching circuit414of the first sensing unit410is enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1drops down at the slower rate, the first sensing voltage Vsen1of the first sensing node Nsen1is still higher than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit414is in the high-level state. Under this circumstance, the storing state of the cell connected with the first data line DL1is the off state.

Since the latching signal Lat is in the low-level state at the time point t3, the inverter406and the inverter416are both enabled. Correspondingly, the magnitude of the reference voltage Vref is changed to be equal to the low voltage level outputted from the inverter406, and the magnitude of the first sensing voltage Vsen1is changed to be equal to the high voltage level outputted from the inverter416.

FIG. 4Cis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 4Aduring the read cycle, in which the storing state of the cell is the on state.

From the time point t0to the time point t2, the transistor Mc of the constant voltage providing circuit402of the reference unit400and the transistor M3of the constant voltage providing circuit412of the first sensing unit410are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are pre-charged to the power supply voltage Vdd. That is, at the time point t2, both the voltage of the reference node Nref and the voltage of the first sensing node Nsen1are equal to the power supply voltage Vdd. Moreover, at the time point t1, the reference node Nref and the first sensing node Nsen1are charged to the preset voltage Vset, the latching signal Lat and the first data line DL1are changed to a high-level state, and at the time point t2, the transistor Mc and the transistor M3are turned off according to the activating signal Vpre.

Moreover, at the time point t1, the latching signal Lat from the comparing circuit404is in the high-level state. Consequently, the latching circuit414is disabled, and the switch elements SW0and SW1are both in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Mc and the transistor M3are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1drop drown.

Since the storing state of the cell is the on state, the first cell current Icell1is equal to the cell current I1. That is, the reference current Iref is lower than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref drops down at a slower rate, while the first sensing voltage Vsen1of the first sensing node Nsen1drops down at a faster rate.

The first sensing voltage Vsen1of the first sensing node Nsen1drops down to the preset voltage Vset at the time point t3, and continuously drops down. At the time point t4, the reference voltage Vref of the reference node Nref drops down to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit404is in the low-level state. Since the latching signal Lat is in the low-level state, the switch elements SW0and SW1are both in the open state, and the latching circuit414of the first sensing unit410is enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1drops down at the faster rate, the first sensing voltage Vsen1of the first sensing node Nsen1is lower than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit414is in the low-level state. Under this circumstance, the storing state of the cell connected with the first data line DL1is the on state.

Since the latching signal Lat is in the low-level state at the time point t4, the inverter406and the inverter416are both enabled. Correspondingly, the magnitude of the reference voltage Vref is changed to be equal to the low voltage level outputted from the inverter406, and the magnitude of the first sensing voltage Vsen1is changed to be equal to the low voltage level outputted from the inverter416.

From the above discussions, a reference current source is provided to generate a reference current Iref. The magnitude of the reference current Iref is in the range between the on-state cell current I1and the off-state cell current I2. After the sensing node and the reference node are pre-charged to the constant voltage, the sensing node and the reference node are connected with the data line and the reference current source, respectively. Then, the storing state of the cell is determined according to the decreasing speed of the sensing voltage of the sensing node and the decreasing speed of the reference voltage of the reference node.

FIG. 5Ais a schematic circuit diagram illustrating a current sensing amplifier according to a second embodiment of the present invention.FIGS. 5B and 5Care schematic timing waveform diagrams illustrating associated signals processed by the current sensing amplifier according to the second embodiment of the present invention.

InFIG. 5A, only a reference unit500and a first sensing unit510are shown. It is noted that the current sensing amplifier may comprise a reference unit and plural sensing units.

In this embodiment, the current sensing amplifier comprises the reference unit500, the first sensing unit510, and two switch elements SW0and SW1. The reference unit500comprises a constant voltage providing circuit502and a comparing circuit504. The constant voltage providing circuit502and the comparing circuit504are connected with a reference node Nref. The constant voltage providing circuit502comprises a transistor Md. The source terminal of the transistor Md is connected with a power supply voltage Vdd. The gate terminal of the transistor Md receives an activating signal Vpre. The drain terminal of the transistor Md is connected with the reference node Nref. Moreover, the comparing circuit504comprises a preset voltage generator506, a comparator505, a switch element SW2, a NAND gate503and four inverters507,508,509,501. The positive input terminal of the comparator505is connected with the reference node Nref for receiving a reference voltage Vref. The negative terminal of the comparator505is connected with the preset voltage generator506for receiving a preset voltage Vset from the preset voltage generator506. The switch element SW2is connected between the output terminal of the comparator505and the input terminal of the inverter507. The input terminal of the inverter508is connected with the output terminal of the inverter507and the input terminal of the inverter507is connected with the output terminal of the inverter508. The input terminal of the inverter509is connected with the output terminal of the inverter507, and input terminal of the inverter501is connected with the output terminal of the inverter509. The first input terminal of the NAND gate503is connected with the output terminal of the inverter501, the second input terminal of the NAND gate503receives the activating signal Vpre, and a latching signal Lat is outputted from the output terminal of the NAND gate503. Moreover, the inverter508and the switch element SW2are controlled by the latching signal Lat. When the latching signal Lat is in a high-level state, the inverter508is disabled. When the latching signal Lat is in a low-level state, the inverter508is enabled. When the latching signal Lat is in the high-level state, the switch element SW2is in a closed state. When the latching signal Lat is in the low-level state, the switch element SW2is in an open state.

The switch element SW0is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW0is in a closed state. Consequently, the reference node Nref is connected with the reference current source to receive a reference current Iref. When the latching signal Lat is in the low-level state, the switch element SW0is in an open state. Consequently, the connection between the reference node Nref and the reference current source is interrupted.

The first sensing unit510comprises a constant voltage providing circuit512and a latching circuit514. The constant voltage providing circuit512and the latching circuit514are connected with a first sensing node Nsen1. The constant voltage providing circuit512comprises a transistor M4. The source terminal of the transistor M4is connected with the power supply voltage Vdd. The gate terminal of the transistor M4receives the activating signal Vpre. The drain terminal of the transistor M4is connected with the first sensing node Nsen1for receiving a first sensing voltage Vsen1. Moreover, the latching circuit514comprises a preset voltage generator516, a comparator515, a switch element SW3, and three inverters517,518,519. The positive input terminal of the comparator515is connected with the first sensing node Nsen1for receiving a first sensing voltage Vsen1. The negative terminal of the comparator515is connected with the preset voltage generator516for receiving the preset voltage Vset from the preset voltage generator516. The switch element SW3is connected between the output terminal of the comparator515and the input terminal of the inverter517. The input terminal of the inverter518is connected with the output terminal of the inverter517and the input terminal of the inverter517is connected with the output terminal of the inverter518. The input terminal of the inverter519is connected with the output terminal of the inverter517. A first output signal Dout1is outputted from the output terminal of the inverter519. Moreover, the inverter518and the switch element SW3are controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the inverter518is disabled. When the latching signal Lat is in the low-level state, the inverter518is enabled, and thus the latching circuit514is normally operated. Furthermore, the switch element SW3is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW3is in a closed state. When the latching signal Lat is in the low-level state, the switch element SW3is in an open state.

The switch element SW1is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW1is in a closed state. Consequently, the first sensing node Nsen1is connected with a first data line DL1to receive a first cell current Icell1. When the latching signal Lat is in the low-level state, the switch element SW1is in an open state. Consequently, the connection between the first sensing node Nsen1and the first data line DL1is interrupted.

In this embodiment, the preset voltage generator506of the reference unit500and the preset voltage generator516of the first sensing unit510are identical, and are used for providing the preset voltage Vset. Moreover, the preset voltage Vset may be adjusted by the preset voltage generators506and516. Hereinafter, the operations of the current sensing amplifier will be illustrated with reference toFIGS. 5B and 5C, wherein Vset=0.75×Vdd.

FIG. 5Bis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 5Aduring the read cycle, in which the storing state of the cell is the off state.

From the time point t0to the time point t2, the transistor Md of the constant voltage providing circuit502of the reference unit500and the transistor M4of the constant voltage providing circuit512of the first sensing unit510are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are pre-charged to the power supply voltage Vdd. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the power supply voltage Vdd. Moreover, at the time point t2, the transistor Md and the transistor M4are turned off according to the activating signal Vpre. Also, at the time point t0, the latching signal Lat outputted by the NAND gate503is changed to a high-level state. At the time point t1, the first sensing node Nsen1is charged to the preset voltage Vset, the first data line DL1are changed to the high-level state.

Moreover, at the time point t0, the latching signal Lat from the comparing circuit504is in the high-level state. Consequently, the latching circuit514and the inverter508are disabled, and the switch elements SW0, SW1, SW2and SW3are in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Md and the transistor M4are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1drop drown.

Since the storing state of the cell is the off state, the first cell current Icell1is equal to the cell current I2. That is, the reference current Iref is higher than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref drops down at a faster rate, while the first sensing voltage Vsen1of the first sensing node Nsen1drops down at a slower rate.

At the time point t3, the reference voltage Vref of the reference node Nref drops down to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit504is in the low-level state. Since the latching signal Lat is in the low-level state, the switch elements SW0, SW1, SW2and SW3are in the open state, and the latching circuit514of the first sensing unit510and the inverter508are enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1drops down at the slower rate, the first sensing voltage Vsen1of the first sensing node Nsen1is still higher than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit514is in the high-level state. Under this circumstance, the storing state of the cell connected with the first data line DL1is the off state.

FIG. 5Cis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 5Aduring the read cycle, in which the storing state of the cell is the on state.

From the time point t0to the time point t2, the transistor Md of the constant voltage providing circuit502of the reference unit500and the transistor M4of the constant voltage providing circuit512of the first sensing unit510are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are pre-charged to the power supply voltage Vdd. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the power supply voltage Vdd. Moreover, at the time point t2, the transistor Md and the transistor M4are turned off according to the activating signal Vpre. Also, at the time point t0, the latching signal Lat outputted by the NAND gate503is changed to a high-level state. At the time point t1, the first sensing node Nsen1is charged to the preset voltage Vset, the first data line DL1are changed to the high-level state.

Moreover, at the time point t0, the latching signal Lat from the comparing circuit504is in the high-level state. Consequently, the latching circuit514and the inverter508are disabled, and the switch elements SW0, SW1, SW2and SW3are in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Md and the transistor M4are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1drop drown.

Since the storing state of the cell is the on state, the first cell current Icell1is equal to the cell current I1. That is, the reference current Iref is lower than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref drops down at a slower rate, while the first sensing voltage Vsen1of the first sensing node Nsen1drops down at a faster rate.

The first sensing voltage Vsen1of the first sensing node Nsen1drops down to the preset voltage Vset at the time point t3, and continuously drops down. At the time point t4, the reference voltage Vref of the reference node Nref drops down to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit504is in the low-level state. Since the latching signal Lat is in the low-level state, the switch elements SW0, SW1, SW2and SW3are in the open state, and the latching circuit514of the first sensing unit510and the inverter508are enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1drops down at the faster rate, the first sensing voltage Vsen1of the first sensing node Nsen1is lower than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit514is in the low-level state. Under this circumstance, the storing state of the cell connected with the first data line DL1is the on state.

FIG. 6Ais a schematic circuit diagram illustrating a current sensing amplifier according to a third embodiment of the present invention.FIGS. 6B and 6Care schematic timing waveform diagrams illustrating associated signals processed by the current sensing amplifier according to the third embodiment of the present invention.

InFIG. 6A, only a reference unit600and a first sensing unit510are shown. It is noted that the current sensing amplifier may comprise a reference unit and plural sensing units. Also, the first sensing unit510inFIG. 5Ais the same with the first sensing unit510inFIG. 6A, and is not redundantly described.

In this embodiment, the current sensing amplifier comprises the reference unit600, the first sensing unit510, and two switch elements SW0and SW1. The reference unit600comprises a constant voltage providing circuit602and a comparing circuit604. The constant voltage providing circuit602and the comparing circuit604are connected with a reference node Nref. The constant voltage providing circuit602comprises a transistor Md. The source terminal of the transistor Md is connected with a power supply voltage Vdd. The gate terminal of the transistor Md receives an activating signal Vpre. The drain terminal of the transistor Md is connected with the reference node Nref. Moreover, the comparing circuit604comprises a preset voltage generator606, a comparator605and two inverters607,609. The positive input terminal of the comparator605is connected with the reference node Nref for receiving a reference voltage Vref. The negative terminal of the comparator605is connected with the preset voltage generator606for receiving a preset voltage Vset from the preset voltage generator606. The input terminal of the inverter607is connected with the output terminal of the comparator605, and input terminal of the inverter609is connected with the output terminal of the inverter607. A latching signal Lat is outputted from the output terminal of the inverter609.

The switch element SW0is in an closed state once the reference unit600is enabled by the activating signal Vpre. Consequently, the reference node Nref is connected with the reference current source to receive a reference current Iref. When the reference unit600is disabled, the switch element SW0is in an open state. Consequently, the connection between the reference node Nref and the reference current source is interrupted.

The switch element SW1is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW1is in a closed state. Consequently, the first sensing node Nsen1is connected with a first data line DL1to receive a first cell current Icell1. When the latching signal Lat is in the low-level state, the switch element SW1is in an open state. Consequently, the connection between the first sensing node Nsen1and the first data line DL1is interrupted.

In this embodiment, the preset voltage generator606of the reference unit600and the preset voltage generator516of the first sensing unit510are identical, and are used for providing the preset voltage Vset. Moreover, the preset voltage Vset may be adjusted by the preset voltage generators606and516. Hereinafter, the operations of the current sensing amplifier will be illustrated with reference toFIGS. 6B and 6C, wherein Vset=0.75×Vdd.

FIG. 6Bis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 6Aduring the read cycle, in which the storing state of the cell is the off state.

At the time point t0, the switch element SW0is in a closed state when the reference unit600is enabled by the activating signal Vpre. Moreover, from the time point t0to the time point t2, the transistor Md of the constant voltage providing circuit602of the reference unit600and the transistor M4of the constant voltage providing circuit512of the first sensing unit510are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are pre-charged to the power supply voltage Vdd. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the power supply voltage Vdd. Moreover, at the time point t1, the reference node Nref and the first sensing node Nsen1are charged to the preset voltage Vset, the latching signal Lat and the first data line DL1are changed to a high-level state, and at the time point t2, the transistor Md and the transistor M4are turned off according to the activating signal Vpre.

Moreover, at the time point t1, the latching signal Lat from the comparing circuit604is in the high-level state. Consequently, the latching circuit514is disabled, and the switch elements SW1and SW3are in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Md and the transistor M4are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1drop drown.

Since the storing state of the cell is the off state, the first cell current Icell1is equal to the cell current I2. That is, the reference current Iref is higher than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref drops down at a faster rate, while the first sensing voltage Vsen1of the first sensing node Nsen1drops down at a slower rate.

At the time point t3, the reference voltage Vref of the reference node Nref drops down to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit604is in the low-level state. Since the latching signal Lat is in the low-level state, the switch elements SW1and SW3are in the open state, and the latching circuit514of the first sensing unit510is enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1drops down at the slower rate, the first sensing voltage Vsen1of the first sensing node Nsen1is still higher than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit514is in the high-level state. Under this circumstance, the storing state of the cell connected with the first data line DL1is the off state.

FIG. 6Cis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 6Aduring the read cycle, in which the storing state of the cell is the on state.

At the time point t0, the switch element SW0is in a closed state when the reference unit600is enabled by the activating signal Vpre. Moreover, from the time point t0to the time point t2, the transistor Md of the constant voltage providing circuit602of the reference unit600and the transistor M4of the constant voltage providing circuit512of the first sensing unit510are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are pre-charged to the power supply voltage Vdd. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the power supply voltage Vdd. Moreover, at the time point t1, the reference node Nref and the first sensing node Nsen1are charged to the preset voltage Vset, the latching signal Lat and the first data line DL1are changed to a high-level state, and at the time point t2, the transistor Md and the transistor M4are turned off according to the activating signal Vpre.

Moreover, at the time point t1, the latching signal Lat from the comparing circuit604is in the high-level state. Consequently, the latching circuit514is disabled, and the switch elements SW1and SW3are in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Md and the transistor Md are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1drop drown.

Since the storing state of the cell is the on state, the first cell current Icell1is equal to the cell current I1. That is, the reference current Iref is lower than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref drops down at a slower rate, while the first sensing voltage Vsen1of the first sensing node Nsen1drops down at a faster rate.

The first sensing voltage Vsen1of the first sensing node Nsen1drops down to the preset voltage Vset at the time point t3, and continuously drops down. At the time point t4, the reference voltage Vref of the reference node Nref drops down to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit504is in the low-level state. Since the latching signal Lat is in the low-level state, the switch elements SW1and SW3are in the open state, and the latching circuit514of the first sensing unit510is enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1drops down at the faster rate, the first sensing voltage Vsen1of the first sensing node Nsen1is lower than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit514is in the low-level state. Under this circumstance, the storing state of the cell connected with the first data line DL1is the on state.

From the above discussions, the preset voltage Vset of the current sensing amplifier of the second embodiment can be adjusted to a higher value. Consequently, the sensing time of the current sensing amplifier can be shortened.

In the above embodiments, the storing state of the cell with the n-type floating gate transistor is sensed by the current sensing amplifier. Alternatively, the concept of the present invention may be applied to the current sensing amplifier for sensing the storing state of the cell with a p-type floating gate transistor, which will be described later.

If the cell of the non-volatile memory device has a p-type floating gate transistor, the cell may generate a cell current I3in the on state but generate a cell current I4in the off state. In accordance with the present invention, a reference current source may provide a reference current Iref. The magnitude of the reference current Iref is in the range between I3and I4. That is, I3>Iref>I4.

FIG. 7Ais a schematic circuit diagram illustrating a current sensing amplifier according to a fourth embodiment of the present invention.FIGS. 7B and 7Care schematic timing waveform diagrams illustrating associated signals processed by the current sensing amplifier according to the third embodiment of the present invention.

InFIG. 7A, only a reference unit700and a first sensing unit710are shown. It is noted that the current sensing amplifier may comprise a reference unit and plural sensing units.

In this embodiment, the current sensing amplifier comprises the reference unit700, the first sensing unit710, and two switch elements SW0and SW1. The reference unit700comprises a constant voltage providing circuit702and a comparing circuit704. The constant voltage providing circuit702and the comparing circuit704are connected with a reference node Nref. The constant voltage providing circuit702comprises a transistor Me. The source terminal of the transistor Me is connected with a ground voltage Vss. The gate terminal of the transistor Me receives an activating signal Vpre. The drain terminal of the transistor Me is connected with the reference node Nref. Moreover, the comparing circuit704may compare a reference voltage Vref of the reference node Nref with a preset voltage Vset. If the reference voltage Vref is lower than the preset voltage Vset, the latching signal Lat outputted from the comparing circuit704has a first voltage level (e.g. a high voltage level). Whereas, if the reference voltage Vref is higher than the preset voltage Vset, the latching signal Lat outputted from the comparing circuit604has a second voltage level (e.g. a low voltage level).

The switch element SW0is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state (i.e. with the first voltage level), the switch element SW0is in a closed state. Consequently, the reference node Nref is connected with the reference current source to receive a reference current Iref. When the latching signal Lat is in the low-level state (i.e. with the second voltage level), the switch element SW0is in an open state. Consequently, the connection between the reference node Nref and the reference current source is interrupted

The first sensing unit710comprises a constant voltage providing circuit712and a latching circuit714. The constant voltage providing circuit712and the latching circuit714are connected with a first sensing node Nsen1. The constant voltage providing circuit712comprises a transistor M5. The source terminal of the transistor M5is connected with the ground voltage Vss. The gate terminal of the transistor M5receives the activating signal Vpre. The drain terminal of the transistor M5is connected with the first sensing node Nsen1for receiving the first sensing voltage Vsen1. Moreover, the latching circuit714is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state (i.e. with the first voltage level), the latching circuit714is disabled. When the latching signal Lat is in the low-level state (i.e. with the second voltage level), the latching circuit714is enabled. Moreover, when the latching circuit714is enabled, if the magnitude of the first sensing voltage Vsen1is lower than the preset voltage Vset, the first output signal Dout1outputted from the latching circuit714is in the high-level state (i.e. with the first voltage level), which indicates an off state of the cell. On the other hand, if the magnitude of the first sensing voltage Vsen1is high than the preset voltage Vset, the first output signal Dout1outputted from the latching circuit714is in the low-level state (i.e. with the second voltage level), which indicates an on state of the cell.

The switch element SW1is controlled by the latching signal Lat. When the latching signal Lat is in the high-level state, the switch element SW1is in a closed state. Consequently, the first sensing node Nsen1is connected with a first data line DL1to receive a first cell current Icell1. When the latching signal Lat is in the low-level state, the switch element SW1is in an open state. Consequently, the connection between the first sensing node Nsen1and the first data line DL1is interrupted. Hereinafter, the operations of the current sensing amplifier will be illustrated with reference toFIGS. 6B and 6C, wherein Vset=Vdd/2.

FIG. 7Bis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 7Aduring the read cycle, in which the storing state of the cell is the off state.

From the time point t0to the time point t2, the transistor Me of the constant voltage providing circuit702of the reference unit700and the transistor M5of the constant voltage providing circuit712of the first sensing unit710are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are discharged to the ground voltage Vss. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the ground voltage Vss. Moreover, at the time point t1, the reference node Nref and the first sensing node Nsen1are discharged to the preset voltage Vset, the latching signal Lat and the first data line DL1are changed to a high-level state, and at the time point t2, the transistor Me and the transistor M5are turned off according to the activating signal Vpre.

Moreover, at the time point t1, the latching signal Lat from the comparing circuit704is in the high-level state (i.e. with the first voltage level). Consequently, the latching circuit714is disabled, and the switch elements SW0and SW1are both in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Me and the transistor M5are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1rise up.

Since the storing state of the cell is the off state, the first cell current Icell1is equal to the cell current I4. That is, the reference current Iref is higher than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref rises up at a faster rate, while the first sensing voltage Vsen1of the first sensing node Nsen1rises up at a slower rate.

At the time point t3, the reference voltage Vref of the reference node Nref rises up to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit704is in the low-level state (i.e. with the second voltage level). Since the latching signal Lat is in the low-level state, the switch elements SW0and SW1are both in the open state, and the latching circuit714of the first sensing unit710is enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1rises up at the slower rate, the first sensing voltage Vsen1of the first sensing node Nsen1is still lower than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit714is in the high-level state (i.e. with the first voltage level). Under this circumstance, the storing state of the cell connected with the first data line DL1is the off state.

FIG. 7Cis a schematic timing waveform diagram illustrating associated signals processed by the current sensing amplifier ofFIG. 7Aduring the read cycle, in which the storing state of the cell is the on state.

From the time point t0to the time point t2, the transistor Me of the constant voltage providing circuit702of the reference unit700and the transistor M5of the constant voltage providing circuit712of the first sensing unit710are shortly turned on according to the activating signal Vpre. Consequently, the reference node Nref and the first sensing node Nsen1are discharged to the ground voltage Vss. That is, at the time point t2, both the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1are equal to the ground voltage Vss. Moreover, at the time point t1, the reference node Nref and the first sensing node Nsen1are discharged to the preset voltage Vset, the latching signal Lat and the first data line DL1are changed to a high-level state, and at the time point t2, the transistor Me and the transistor M5are turned off according to the activating signal Vpre.

Moreover, at the time point t1, the latching signal Lat from the comparing circuit704is in the high-level state (i.e. with the first voltage level). Consequently, the latching circuit714is disabled, and the switch elements SW0and SW1are both in the closed state. Under this circumstance, the reference node Nref is connected with the reference current source to receive the reference current Iref, and the first sensing node Nsen1is connected with the first data line DL1to receive the first cell current Icell1. When the transistor Me and the transistor M5are turned off at the time point t2, the reference voltage Vref of the reference node Nref and the first sensing voltage Vsen1of the first sensing node Nsen1rise up.

Since the storing state of the cell is the on state, the first cell current Icell1is equal to the cell current I3. That is, the reference current Iref is lower than the first cell current Icell1. Consequently, after the time point t2, the reference voltage Vref of the reference node Nref rises up at a slower rate, while the first sensing voltage Vsen1of the first sensing node Nsen1rises up at a faster rate.

The first sensing voltage Vsen1of the first sensing node Nsen1rises up to the preset voltage Vset at the time point t3, and continuously rises up. At the time point t4, the reference voltage Vref of the reference node Nref rises up to the preset voltage Vset. Correspondingly, the latching signal Lat from the comparing circuit704is in the low-level state (i.e. with the second voltage level). Since the latching signal Lat is in the low-level state, the switch elements SW0and SW1are both in the open state, and the latching circuit714of the first sensing unit710is enabled. Since the first sensing voltage Vsen1of the first sensing node Nsen1rises up at the faster rate, the first sensing voltage Vsen1of the first sensing node Nsen1is higher than the preset voltage Vset. Correspondingly, the first output signal Dout1from the latching circuit714is in the low-level state (i.e. with the second voltage level). Under this circumstance, the storing state of the cell connected with the first data line DL1is the on state.

From the above discussions, the current sensing amplifier of the present invention is capable of quickly detecting the storing state of the cell. Moreover, since no operational amplifier OP is included in the current sensing amplifier, the power consumption of the current sensing amplifier can be effectively reduced.

Moreover, during the program cycle, if less hot carriers are injected into the cell, the storing state of the cell is in the on state. That is, the cell has a lower threshold voltage (e.g. Vth_l). Whereas, if more hot carriers are injected into the cell, the storing state of the cell is in the off state. That is, the cell has a higher threshold voltage (e.g. Vth_h).

In accordance with the present invention, the reference current source may be implemented by a reference cell. That is, during the program cycle, the threshold voltage of the reference cell may be adjusted to be in the range between Vth_l and Vth-h by controlling the amount of hot carriers to be injected into the floating gate. Consequently, during the read cycle, the cell current of the reference cell is equal to the reference current Iref. The magnitude of the reference current Iref is in the range between I1and I2, wherein I1is the magnitude of the cell current when the cell is in the on state, and I2is the magnitude of the cell current when the cell is in the off state.