Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first electrode layer disposed on the substrate, a gate electrode layer disposed on the first electrode layer, a second electrode layer disposed on the gate electrode layer, an oxide semiconductor layer penetrating through the gate electrode layer, a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer, a first insulating layer disposed between the gate electrode layer and the first electrode layer, and a second insulating layer disposed between the gate electrode layer and the second electrode layer. The oxide semiconductor layer is in direct contact with the first electrode layer and the second electrode layer, respectively.

BACKGROUND

Technical Field

The invention relates to a semiconductor manufacture technique, and particularly relates to a semiconductor device and a method of manufacturing the same.

Description of Related Art

The semiconductor device such as transistor has been developed for a long time. The transistor includes plane device and vertical device. The plane device is, for example, a thin film transistor, wherein a source electrode and a drain electrode are over a gate electrode, and the channel length (Lg) is defined by the spacing between the source electrode and the drain electrode. However, the channel length is desired to be smaller with the miniaturization of the device size, and thus the Lg of the plane device can not meet the requirement due to the resolution limitation of photolithography.

The vertical device is, for example, a 3D transistor, wherein a vertical channel formed on the substrate, a source electrode and a drain electrode are disposed at two ends of the vertical channel, and the Lg of the vertical device is defined by the thickness of a gate electrode. Therefore, the Lg of vertical device can be made smaller. However, the process of the vertical device is more complicated than the plane device, and it is difficult in the formation and the contact for drain/source/body.

SUMMARY

The invention provides a semiconductor device having fine channel length without complicated process.

The invention further provides a method of manufacturing a semiconductor device to obtain the semiconductor device having fine channel length.

The semiconductor device of one embodiment of the invention includes a substrate, a first electrode layer, a gate electrode layer, a second electrode layer, an oxide semiconductor layer, a gate dielectric layer, a first insulating layer, and a second insulating layer. The first electrode layer is disposed on the substrate, the gate electrode layer is disposed on the first electrode layer, and the second electrode layer is disposed on the gate electrode layer, wherein the first electrode layer and the second electrode layer are as a drain and a source of the semiconductor device. The oxide semiconductor layer penetrates through the gate electrode layer and is in direct contact with the first electrode layer and the second electrode layer, respectively. The gate dielectric layer is disposed between the gate electrode layer and the oxide semiconductor layer, the first insulating layer is disposed between the gate electrode layer and the first electrode layer, and the second insulating layer is disposed between the gate electrode layer and the second electrode layer.

In an embodiment of the invention, the semiconductor device further comprises electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer, respectively.

In an embodiment of the invention, a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide (IGZO).

In an embodiment of the invention, the substrate comprises a silicon-on-insulator (SOI) substrate.

The method of manufacturing a semiconductor device of another embodiment of the invention includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.

In another embodiment of the invention, after the step of forming the second electrode layer, the method further comprises patterning the second insulating layer and the gate electrode layer.

In another embodiment of the invention, after the step of forming the second electrode layer, the method further comprises respectively forming electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer.

In another embodiment of the invention, the step of forming the gate dielectric layer comprises conformally depositing a dielectric material layer on the stack structure and in the opening, and then etching back the dielectric material layer until the first electrode layer is exposed.

In another embodiment of the invention, the step of forming the stack structure comprises depositing the first insulating layer on the first electrode layer, depositing the gate electrode layer on the first insulating layer, and depositing the second insulating layer on the gate electrode layer.

In another embodiment of the invention, the step of forming the oxide semiconductor layer in the opening comprises blanket depositing an oxide semiconductor material to fill the opening, and then etching back the oxide semiconductor material until the stack structure is exposed.

In another embodiment of the invention, a method of forming the oxide semiconductor layer in the opening comprises a selective deposition process.

In another embodiment of the invention, a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide.

In another embodiment of the invention, the substrate comprises a silicon-on-insulator (SOI) substrate.

Based on the above, since the invention provides a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor penetrating through the gate electrode layer, it can realize fine channel length in the semiconductor device by simple process.

DESCRIPTION OF THE EMBODIMENTS

Referring to the embodiments below and the accompanied drawings for a sufficient understanding of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. However, the invention may be implemented in many other different forms and should not be limited to the embodiments described hereinafter. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the drawings, for clarity, the elements and relative dimensions thereof may not be scaled. For easy understanding, the same elements in the following embodiments will be denoted by the same reference numerals.

FIG.1is a schematic plan view of a semiconductor device according to a first embodiment of the invention.FIG.2is a cross-sectional view along line II-II′ ofFIG.1.

Referring toFIG.1andFIG.2, the semiconductor device of the first embodiment includes a substrate100, a first electrode layer102, a gate electrode layer104, a second electrode layer106, an oxide semiconductor layer108, a gate dielectric layer110, a first insulating layer112, and a second insulating layer114. The first electrode layer102is disposed on the substrate100, the gate electrode layer104is disposed on the first electrode layer102, and the second electrode layer106is disposed on the gate electrode layer104. In one embodiment, the substrate100may be a silicon-on-insulator (SOI) substrate or other semiconductor substrate. The gate electrode layer104may be made of conductive material such as indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide, zinc oxide, or other suitable material. The first electrode layer102and the second electrode layer106are as a drain and a source of the semiconductor device. For example, the first electrode layer102is a drain electrode and the second electrode layer106is a source electrode; alternatively, the first electrode layer102is a source electrode and the second electrode layer106is a drain electrode. In one embodiment, the first electrode layer102and the second electrode layer106may be a metal film or a metal nitride film, wherein the material of the metal film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W; the material of the metal nitride film is nitride of foregoing metal such as a titanium nitride film, a molybdenum nitride film, a tungsten nitride film), or the like. The oxide semiconductor layer108penetrates through the gate electrode layer104and is in direct contact with the first electrode layer102and the second electrode layer106, respectively. A material of the oxide semiconductor layer108includes, for example, indium-gallium-zinc oxide (IGZO) or other suitable oxide semiconductor material. The gate dielectric layer110is disposed between the gate electrode layer104and the oxide semiconductor layer108, the first insulating layer112is disposed between the gate electrode layer104and the first electrode layer102, and the second insulating layer114is disposed between the gate electrode layer104and the second electrode layer106.

In the first embodiment, the profile of the cross section of the semiconductor device is step-shaped, and thus it is beneficial to interconnection of the semiconductor device. For example, an electrode contact116connects to the first electrode layer102, an electrode contact118connects to the gate electrode layer104, and an electrode contact120connects to the second electrode layer106. Those electrode contacts116,118and120can be formed together using the same steps. However, the invention is not limited thereto.

FIG.3is a schematic plan view of a semiconductor device according to a second embodiment of the invention, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar components.FIG.4is a cross-sectional view along line IV-IV′ ofFIG.3. The description of the same components can be derived from the first embodiment, and will not be repeated here.

Referring toFIG.3andFIG.4, the semiconductor device of the second embodiment also includes a substrate100, a first electrode layer102, a gate electrode layer104, a second electrode layer106, an oxide semiconductor layer108, a gate dielectric layer110, a first insulating layer112, and a second insulating layer114. The difference between the second and the first embodiments is that the shapes of the oxide semiconductor layer108and the second electrode layer106are circular. In another embodiment, the shapes of the oxide semiconductor layer108and the second electrode layer106in theFIG.3may be rectangle, and so on.

FIG.5AtoFIG.5Iare schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention.

Referring toFIG.5A, a first electrode layer502is formed on a substrate500. The substrate500may be a SOI substrate or other semiconductor substrate.

Then, referring toFIG.5B, a stack structure504is formed on the first electrode layer502, wherein the stack structure504, for example, includes a first insulating layer506, a gate electrode layer508, and a second insulating layer510. In the embodiment, the step of forming the stack structure504, for example, includes depositing the first insulating layer506on the first electrode layer502, depositing the gate electrode layer508on the first insulating layer506, and depositing the second insulating layer510on the gate electrode layer508.

Thereafter, referring toFIG.5C, an opening512is formed in the stack structure504. The opening512may be, for example, a rectangle groove or a circular hole. To form a gate dielectric layer on a sidewall512aof the opening512, it may conformally depositing a dielectric material layer514on the stack structure504and in the opening512first.

After that, referring toFIG.5D, the dielectric material layer514inFIG.5Cis etched back until the first electrode layer502is exposed so as to form the gate dielectric layer514a. However, the invention is not limited thereto.

Then, referring toFIG.5E, an oxide semiconductor layer516is formed in the opening512, wherein the gate dielectric layer514ais sandwiched between the oxide semiconductor layer516and the gate electrode layer508. In one embodiment, the step of forming the oxide semiconductor layer516in the opening512includes blanket depositing an oxide semiconductor material (not shown) to fill the opening516, and then etching back the oxide semiconductor material until the stack structure504is exposed. In another embodiment, a method of forming the oxide semiconductor layer516in the opening512includes a selective deposition process. A material of the oxide semiconductor layer516includes, for example, IGZO or other suitable oxide semiconductor material.

Thereafter, referring toFIG.5F, a second electrode layer518is formed on the stack structure504to be in direct contact with the oxide semiconductor layer516, wherein the method of forming the second electrode layer518, for example, includes a deposition process. A semiconductor device of the third embodiment has been manufactured in this step.

After the step shown inFIG.5F, there are some optional steps as follows.

Please referring toFIG.5G, the second electrode layer518is patterned to expose a portion of the stack structure504.

Then, referring toFIG.5H, the second insulating layer510and the gate electrode layer508are patterned, and thus the profile of the cross section of the structure inFIG.5His step-shaped for the interconnection. In another embodiment, the first insulating layer506and the first electrode layer502can be further patterned to expose a portion of the substrate500(e.g. the semiconductor device as shown inFIG.4).

Thereafter, referring toFIG.5I, electrode contacts520a,520band520care formed to connecting to the first electrode layer502, the gate electrode layer508, and the second electrode layer518, respectively.

In summary, the semiconductor device according to the invention comprises a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor perpendicularly penetrating through the gate electrode layer, and thus the channel length (Lg) can be defined by the thickness of the gate electrode layer. In other words, according to the invention, fine channel length of the semiconductor device can be accomplished by simple process.