Pixel driving circuit, driving method thereof, and display apparatus

A pixel driving circuit is disclosed. A first electrode, a second electrode, and a third electrode of a driving sub-circuit respectively receives a first voltage signal, is coupled to the light-emission control sub-circuit, and to a first electrode of a second storage sub-circuit. A first electrode and second electrode of a first storage sub-circuit is coupled to a first node and receives a second voltage signal respectively. A second electrode of the second storage sub-circuit is coupled to a second node. A writing-compensation control sub-circuit is coupled to the first node and the second node, and receives a data signal, a gate signal, and a third voltage signal. A light-emission control sub-circuit is coupled to the first node, the second node, a second electrode of the driving sub-circuit, and the light-emission sub-circuit, and receives a light-emission control signal.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Chinese Patent Application No. CN 201711295429.8 filed on Dec. 8, 2017, the disclosures of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to the field of display technologies, and more specifically to a pixel driving circuit, its driving method, and a display apparatus containing the pixel driving circuit.

BACKGROUND

With the rapid development of technologies, there have emerged increasingly more types of display technologies, including traditional liquid crystal display (LCD) technologies, and organic light-emitting diode (OLED) display technologies, etc.

Currently, the OLED-based display technologies include active-matrix organic light-emitting diode (AMOLED) display technologies, and electrophoresis display technologies, and so on. Compared with other types of display panels, an OLED display panel has advantages including a self-luminescent display, a fast response, a high brightness, and a wide angle of view, etc., and therefore the organic electroluminescent diode display technologies have a wide application prospect.

Despite the above mentioned advantages, most current OLED display panels employ transistors as switches. Transistors are typically formed from low-temperature polysilicon produced by excimer laser annealing and/or ion implantation. During the manufacturing process of the transistors, there exist certain differences between different transistors. Such a lack of uniformity causes voltage deviations between these different transistors, resulting in an uneven brightness among different pixels, and in turn leading to the appearance of alternate light and shade in the display panel.

SUMMARY

In order to address the above mentioned issues associated with existing display technologies, the present disclosure provides a pixel driving circuit, its driving method, and a display apparatus containing the pixel driving circuit.

In a first aspect, a pixel driving circuit is disclosed.

The pixel driving circuit includes a writing-compensation control sub-circuit, a light-emission control sub-circuit, a first storage sub-circuit, a second storage sub-circuit, a driving sub-circuit, and a light-emission sub-circuit.

A first electrode of the driving sub-circuit is configured to receive a first voltage signal; a second electrode of the driving sub-circuit is electrically coupled to the light-emission control sub-circuit; and a third electrode of the driving sub-circuit is electrically coupled to a first electrode of the second storage sub-circuit.

A first electrode of the first storage sub-circuit is electrically coupled to a first node; and a second electrode of the first storage sub-circuit is configured to receive a second voltage signal. A second electrode of the second storage sub-circuit is electrically coupled to a second node.

The writing-compensation control sub-circuit is electrically coupled to the first node and the second node, and the writing-compensation control sub-circuit is configured to receive a data signal, a gate signal, and a third voltage signal, and is configured, under control of the gate signal, to control whether the first node receives the data signal, whether the second node receives the third voltage signal, and whether the third electrode of the driving sub-circuit is electrically connected with the second electrode of the driving sub-circuit.

The light-emission control sub-circuit is electrically coupled to the first node, the second node, a second electrode of the driving sub-circuit, and the light-emission sub-circuit, and the light-emission control sub-circuit is configured to receive a light-emission control signal, and is further configured, under control of the light-emission control signal, to control whether the first node is electrically connected with the second node, and whether the second electrode of the driving sub-circuit is electrically connected with the light-emission sub-circuit.

According to some embodiments of the pixel driving circuit, the driving sub-circuit comprises a P-type driving transistor, and a source electrode, a drain electrode, and a gate electrode of the driving transistor are respectively the first electrode, the second electrode, and the third electrode of the driving sub-circuit.

According to some embodiments of the pixel driving circuit, the writing-compensation control sub-circuit comprises a first transistor, a second transistor, and a third transistor.

With regard to the first transistor, a source electrode thereof is configured to receive the data signal, a drain electrode thereof is electrically coupled to the first node, and a gate electrode thereof is configured to receive the gate signal.

With regard to the second transistor, a source electrode thereof is configured to receive the third voltage signal, a drain electrode thereof is electrically coupled to the second node, and a gate electrode thereof is configured to receive the gate signal.

With regard to the third transistor, a source electrode thereof is electrically coupled to the second electrode of driving sub-circuit, a drain electrode thereof is electrically coupled to the third electrode of the driving sub-circuit, and a gate electrode thereof is configured to receive the gate signal.

According to some embodiments of the pixel driving circuit, the light-emission control sub-circuit comprises a fourth transistor and a fifth transistor.

With regard to the fourth transistor, a source electrode thereof is electrically coupled to the first node, a drain electrode thereof is electrically coupled to the second node, and a gate electrode thereof is configured to receive the light-emission control signal.

With regard to the fifth transistor, a source electrode thereof is electrically coupled to the second electrode of the driving sub-circuit, a drain electrode thereof is electrically coupled to the light-emission sub-circuit, and a gate electrode thereof is configured to receive the light-emission control signal.

According to some embodiments of the pixel driving circuit, the first storage sub-circuit comprises a first storage capacitor, wherein a first electrode thereof is electrically coupled to the first node, and a second electrode thereof is configured to receive the second voltage signal.

According to some embodiments of the pixel driving circuit, the second storage sub-circuit comprises a second storage capacitor, wherein a first electrode thereof is electrically coupled to the third electrode of the driving sub-circuit, and a second electrode thereof is electrically coupled to the second node.

According to some embodiments, the pixel driving circuit further comprises a first initiating sub-circuit, wherein the first initiating sub-circuit is electrically coupled with the light-emission sub-circuit, and is configured to receive a first initiating signal and a first initiating control signal, and the first initiating sub-circuit is configured, under control of the first initiating control signal, to control whether the light-emission sub-circuit receives the first initiating signal.

Herein, the first initiating sub-circuit can include a first initiating transistor. A source electrode thereof is configured to receive the first initiating signal, a drain electrode thereof is electrically coupled to the light-emission sub-circuit, and a gate electrode thereof is configured to receive the first initiating control signal.

According to some embodiments, the pixel driving circuit further comprises a second initiating sub-circuit, wherein the second initiating sub-circuit is electrically coupled with the first node, and is configured to receive a second initiating signal and a second initiating control signal, and the second initiating sub-circuit is configured, under control of the second initiating control signal, to control whether the first node receives the second initiating signal.

Herein, the second initiating sub-circuit can include a second initiating transistor. A source electrode thereof is configured to receive the second initiating signal, a drain electrode thereof is electrically coupled to the first node, and a gate electrode thereof is configured to receive the second initiating control signal.

According to some embodiments of the pixel driving circuit, the first voltage signal and the second voltage signal are same. Furthermore, in these embodiments of the pixel driving circuit, the first voltage signal and the third voltage signal can also be same or can be different.

In a second aspect, the present disclosure further provides a method for driving a pixel driving circuit.

The method comprises at least one display cycle, and each of the at least one display cycle comprises a writing-compensation control stage and a light-emission control stage.

The writing-compensation control stage comprises: manipulating a light-emission control signal and a gate signal, such that a first node is electrically disconnected from a second node, and a second electrode of a driving sub-circuit is electrically disconnected from a light-emission sub-circuit; and that a data signal is written to a first storage sub-circuit, the second node receives a third voltage signal; and the second electrode of the driving sub-circuit is electrically coupled with a third electrode of the driving sub-circuit.

The light-emission control stage comprises: manipulating the light-emission control signal and the gate signal, such that the first node does not receive the data signal, the second node does not receive the third voltage signal, and the second electrode of the driving sub-circuit is electrically disconnected with the third electrode of the driving sub-circuit; and that the first node is electrically connected with the second node, and the second electrode of the driving sub-circuit is electrically connected with a light-emission sub-circuit to thereby allow the light-emission sub-circuit to emit lights.

According to some embodiments of the method, the driving sub-circuit comprises a P-type driving transistor, and a source electrode, a drain electrode, and a gate electrode of the driving transistor are respectively the first electrode, the second electrode, and the third electrode of the driving sub-circuit. The pixel driving circuit further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor.

Herein, with regard to the first transistor, a source electrode thereof is configured to receive the data signal, a drain electrode thereof is electrically coupled to the first node, and a gate electrode thereof is configured to receive the gate signal. With regard to the second transistor, a source electrode thereof is configured to receive the third voltage signal, a drain electrode thereof is electrically coupled to the second node, and a gate electrode thereof is configured to receive the gate signal. With regard to the third transistor, a source electrode thereof is electrically coupled to the second electrode of the driving sub-circuit, a drain electrode thereof is electrically coupled to the third electrode of the driving sub-circuit, and a gate electrode thereof is configured to receive the gate signal. With regard to the fourth transistor, a source electrode thereof is electrically coupled to the first node, a drain electrode thereof is electrically coupled to the second node, and a gate electrode thereof is configured to receive the light-emission control signal. With regard to the fifth transistor, a source electrode thereof is electrically coupled to the second electrode of the driving sub-circuit, a drain electrode thereof is electrically coupled to the light-emission sub-circuit, and a gate electrode thereof is configured to receive the light-emission control signal.

As such, the manipulating the light-emission control signal and the gate signal in the writing-compensation control stage comprises: applying a turn-off signal as the light-emission control signal and applying a turn-on signal as the gate signal; and the manipulating the light-emission control signal and the gate signal in the light-emission control stage comprises: applying a turn-on signal as the light-emission control signal and applying a turn-off signal as the gate signal;

In the above embodiments of the method, each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor can be a P-type transistor. As such, the applying a turn-off signal as the light-emission control signal and applying a turn-on signal as the gate signal comprises: applying a high-level signal as the light-emission control signal and applying a low-level signal as the gate signal; and the applying a turn-on signal as the light-emission control signal and applying a turn-off signal as the gate signal comprises: applying a low-level signal as the light-emission control signal and applying a high-level signal as the gate signal.

According to some embodiments of the method, each of the at least one display cycle further comprises, prior to the writing-compensation control stage, an initiation stage. The initiation stage comprises: manipulating the light-emission control signal and the gate signal, such that the first node does not receive the data signal, the second node does not receive the third voltage signal, and the second electrode of the driving sub-circuit is electrically disconnected from the third electrode of the driving sub-circuit; and that the first node is electrically disconnected from the second node, and the second electrode of the driving sub-circuit is electrically disconnected from the light-emission sub-circuit.

In the above embodiments of the method, the pixel driving circuit can further comprise a first initiating sub-circuit, which is electrically coupled with the light-emission sub-circuit. The first initiating sub-circuit is configured to receive a first initiating signal and a first initiating control signal, and is further configured, under control of the first initiating control signal, to control whether the light-emission sub-circuit receives the first initiating signal. As such, the initiation stage further comprises: manipulating the first initiating control signal such that the first initiating signal is written to the first electrode of the light-emission sub-circuit to realize an initiation of the light-emission sub-circuit.

In the above embodiments of the method, the pixel driving circuit can alternatively further comprise a second initiating sub-circuit, which is electrically coupled with the first node. The second initiating sub-circuit is configured to receive a second initiating signal and a second initiating control signal, and is further configured, under control of the second initiating control signal, to control whether the first node receives the second initiating signal. As such, the initiation stage further comprises: manipulating the second initiating control signal such that the second initiating signal is written to the first node to realize an initiation of the light-emission sub-circuit.

In a third aspect, the present disclosure further provides a display apparatus. The display apparatus comprises a pixel driving circuit according to any one of the embodiments as described above.

DETAILED DESCRIPTION

Various embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure can be easily understood by those skilled in the field of technology from the contents disclosed in this specification.

Apparently, the described embodiments are only a part of embodiments in the present disclosure, rather than all of them. The present disclosure can also be implemented or applied through different specific embodiments, and various details of the specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure.

Based on the embodiments in the present disclosure, all the other embodiments acquired by those skilled in the art on the premise of not paying creative labor are in the protection scope of the present disclosure. It should be noted that, on the premise that there is no conflict, the following embodiments and the features in the embodiments can be combined together.

In a first aspect, the present disclosure provides a pixel driving circuit.

FIG. 1illustrates a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. As shown inFIG. 1, the pixel driving circuit100includes a writing-compensation control sub-circuit110, a light-emission control sub-circuit120, a first storage sub-circuit130, a second storage sub-circuit140, a driving sub-circuit150, and a light-emission sub-circuit160.

A first electrode of the driving sub-circuit150is electrically coupled or electrically connected to a first voltage input terminal VDD1, and is configured to receive a first voltage signal Vdd1from the first voltage input terminal VDD1. A second electrode of the driving sub-circuit150is electrically coupled/connected to the light-emission control sub-circuit120, and is further coupled to the light-emission sub-circuit160via the light-emission control sub-circuit120, and is thereby configured to control the light-emission sub-circuit160to emit lights. A third electrode of the driving sub-circuit150is electrically coupled/connected to a first electrode of the second storage sub-circuit140.

A first electrode of the first storage sub-circuit130is electrically coupled/connected to a first node N1. A second electrode of the first storage sub-circuit130is electrically coupled/connected to a second voltage input terminal VDD2, and is configured to receive a second voltage signal Vdd2from the second voltage input terminal VDD2.

The first electrode of the second storage sub-circuit140is electrically coupled to the third electrode of the driving sub-circuit150, and a second electrode of the second storage sub-circuit140is electrically coupled to a second node N2.

The writing-compensation control sub-circuit110is electrically coupled to a data line DL, a gate line Gate, a third voltage input terminal VDD3, the first node N1, and the second node N2, respectively. The writing-compensation control sub-circuit110is configured to receive a data signal Vdata from the data line DL, a gate signal Vgate from the gate line Gate, and a third voltage signal Vdd3from the third voltage input terminal VDD3.

Herein, the third voltage input terminal VDD3and the first voltage input terminal VDD1are configured to be a same voltage input terminal, and thus the signal from the third voltage input terminal VDD3(i.e. Vdd3) and the signal from the first voltage input terminal VDD1(i.e. Vdd1) are same, i.e. Vdd1=Vdd3.

In addition, the second voltage input terminal VDD2and the first voltage input terminal VDD1are configured to be a same voltage input terminal, and thus the signal from the second voltage input terminal VDD2(i.e. Vdd2) and the signal from the first voltage input terminal VDD1(i.e. Vdd1) are same, i.e. Vdd1=Vdd2.

As such, the signal form the first voltage input terminal VDD1(i.e. Vdd1), the signal from the second voltage input terminal VDD2(i.e. Vdd2), and the third voltage input terminal VDD3(i.e. Vdd3) are same, i.e. i.e. Vdd1=Vdd2=Vdd3=Vdd.

The writing-compensation control sub-circuit110is configured to control an electrical conductance between the first node N1and the data line DL under control of the gate signal Vgate, and is thus able to control whether the first node N1can receive the data signal Vdata from the data line DL.

The writing-compensation control sub-circuit110is further configured to control an electrical conductance between the second node N2and the third voltage input terminal VDD3under control of the gate signal Vgate, and is thus able to control whether the second node N2can receive the third voltage signal Vdd3from the third voltage input terminal VDD3.

The writing-compensation control sub-circuit110is further configured to control an electrical conductance between the third electrode of the driving sub-circuit150and the second electrode of the driving sub-circuit150under control of the gate signal Vgate.

The light-emission control sub-circuit120is electrically coupled to a light-emission control signal line EM, the first node N1, the second node N2, the second electrode of the driving sub-circuit150, and the light-emission sub-circuit160.

The light-emission control sub-circuit120is configured to receive a light-emission control signal Vem from the light-emission control signal line EM. The light-emission control sub-circuit120is further configured to control an electrical conductance between the first node N1and the second node N2under control of the light-emission control signal Vem, and the light-emission control sub-circuit120is also configured to control an electrical conductance between the second electrode of the driving sub-circuit150and the light-emission sub-circuit160under control of the light-emission control signal Vem.

Specifically, the driving sub-circuit150can include a driving transistor151. The driving transistor151can be a P-type transistor. A source electrode, a drain electrode, and a gate electrode of the driving transistor151can respectively be the first electrode, the second electrode, and the third electrode of the driving sub-circuit150.

The aforementioned embodiments of the pixel driving circuit are herein described with a driving transistor151as the driving sub-circuit150. It is noted that it serves only as an illustrating example, and other embodiments are possible. For example, the driving sub-circuit150can also include other components that can be combined with a driving transistor, such as resistors or inductors. These components together constitute the driver circuit150to realize the purported function of the driver circuit150.

Specifically, the light-emission sub-circuit160can include a light-emitting component161, which is electrically coupled to the drain electrode of the driving transistor151, and is configured to emit lights under driving of the driving transistor151.

Specifically, the writing-compensation control sub-circuit110can include a first transistor111, a second transistor112, and a third transistor113. A source electrode of the first transistor111is electrically coupled to the data line DL, and is configured to receive the data signal Vdata from the data line DL. A drain electrode of the first transistor111is electrically coupled to the first node N1. A gate electrode of the first transistor111is electrically coupled to the gate line Gate, and is configured to receive the gate signal Vgate from the gate line Gate.

A source electrode of the second transistor112is electrically coupled to the third voltage input terminal VDD3, and is configured to receive the third voltage signal from the third voltage input terminal VDD3. A drain electrode of the second transistor112is electrically coupled to the second node N2. A gate electrode of the second transistor112is electrically coupled to the gate line Gate, and is configured to receive the gate signal Vgate from the gate line Gate.

A source electrode of the third transistor113is electrically coupled to the second electrode of driving sub-circuit150, i.e., the source electrode of the third transistor113is electrically coupled to the drain electrode of the driving transistor151. A drain electrode of the third transistor113is electrically coupled to the third electrode of the driving sub-circuit150, i.e., the drain electrode of the third transistor113is electrically coupled to the gate electrode of the driving transistor151. A gate electrode of the third transistor113is electrically coupled to the gate line Gate, and is configured to receive the gate signal Vgate from the gate line Gate.

Further specifically, the light-emission control sub-circuit120can include a fourth transistor121and a fifth transistor122. A source electrode of the fourth transistor121is electrically coupled to the first node N1. A drain electrode of the fourth transistor121is electrically coupled to the second node N2. A gate electrode of the fourth transistor121is electrically coupled to the light-emission control signal line EM, and is thus configured to receive the light-emission control signal Vem from the light-emission control signal line EM.

A source electrode of the fifth transistor122is electrically coupled to the second electrode of the driving sub-circuit150, i.e. the source electrode of the fifth transistor122is electrically coupled to the drain electrode of the driving transistor151. A drain electrode of the fifth transistor122is electrically coupled to the light-emitting component161. A gate electrode of the fifth transistor122is electrically coupled to the light-emission control signal line EM, and is thus configured to receive the light-emission control signal Vem from the light-emission control signal line EM.

In the embodiments of the pixel driving circuits as described above, all transistors besides the driving transistor151(i.e. the first transistor111, the second transistor112, the third transistor113, the fourth transistor121, and the fifth transistor122) can each be a P-type transistor.

It is noted that these above embodiments shall be interpreted as illustrating examples only, and other embodiments are also possible. For example, each of these other transistors except the driving transistor151(i.e. the first transistor111, the second transistor112, the third transistor113, the fourth transistor121, and the fifth transistor122) can each be a N-type transistor, whose time sequence of the control signal can be altered accordingly when a control is needed. There are no limitations herein regarding the type of transistors, yet in the following, detailed description is given with each of the transistors, including the driving transistor151, the first transistor111, the second transistor112, the third transistor113, the fourth transistor121, and the fifth transistor122, being a P-type transistor.

Further specifically, the first storage sub-circuit130can include a first storage capacitor131. A first electrode of the first storage capacitor131is electrically coupled to the first node N1. A second electrode of the first storage capacitor131is electrically coupled to the second voltage input terminal VDD2, and is configured to receive the second voltage signal Vdd2from the second voltage input terminal VDD2.

It is noted herein that the first storage sub-circuit130is illustratively described with it being a first storage capacitor131. Other embodiments are possible. For example, the first storage sub-circuit130can also include other components that can be combined with the first storage capacitor131, such as resistors or capacitors. These components together can realize the purported function of the first storage sub-circuit130. In one specific example, the first storage sub-circuit130can include at least two first storage capacitors.

Further specifically, the second storage sub-circuit140can include a second storage capacitor141. A first electrode of the second storage capacitor141is electrically coupled to the third electrode of the driving sub-circuit150, i.e. the first electrode of the second storage capacitor141is electrically coupled to the gate electrode of the driving transistor151. A second electrode of the second storage capacitor141is electrically coupled to the drain electrode of the second transistor112, and is further electrically coupled to the third voltage input terminal VDD3via the second transistor112. As such, the second electrode of the second storage capacitor141is configured to receive the third voltage signal Vdd3from the third voltage input terminal VDD3.

It is noted herein that the second storage sub-circuit140is illustratively described with it being a second storage capacitor141. Other embodiments are possible. For example, the second storage sub-circuit140can also include other components that can be combined with the second storage capacitor141, such as resistors or capacitors. These components together can realize the purported function of the second storage sub-circuit140. In one specific example, the second storage sub-circuit140can include at least two second storage capacitors.

In a second aspect, the present disclosure further provides a method for driving a pixel driving circuit. The pixel driving circuit can be the embodiments as illustrated inFIG. 1.

Specifically,FIG. 2illustrates a time sequence diagram of the pixel driving circuit100as shown inFIG. 1. As shown inFIG. 2, the method for driving the pixel driving circuit100substantially comprises a display cycle which alternately includes a writing-compensation control stage T1and a light-emission control stage T2.

Specifically, the method includes a writing-compensation control stage T1, when the light-emission control signal Vem from the light-emission control signal line EM is a high-level signal, and the gate signal Vgate from the gate line Gate is a low-level signal. As such, under control of the light-emission control signal Vem, the light-emission control sub-circuit120can control the electrical disconnection between the first node N1and the second node N2, and the light-emission control sub-circuit120can further control the electrical disconnection between the second electrode of the driving sub-circuit150and the light-emission sub-circuit160.

Specifically, during the writing-compensation control stage T1of each display cycle, the light-emission control signal line EM can send the light-emission control signal Vem to both the fourth transistor121and the fifth transistor122. Under the light-emission control signal Vem, the source electrode and the drain electrode of the fourth transistor121are not electrically connected, thus the first node N1and the second node N2are electrically disconnected. Additionally, under the light-emission control signal Vem, the source electrode and the drain electrode of the fifth transistor122are not electrically connected, thus the drain electrode of the driving transistor151and the light-emission sub-circuit160are electrically disconnected.

Further under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls an electrical connection between the data line DL and the first node N1, and in turn the data line DL is electrically connected with the first electrode of the first storage sub-circuit130. As such, the writing-compensation control sub-circuit110controls that the data signal Vdata can be inputted or written to the first storage sub-circuit130and that the first node N1has a potential of Vdata.

Additionally, under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls an electrical connection between the second node N2and the third voltage input terminal VDD3, and in turn the second node N2can receive the third voltage signal Vdd3from the third voltage input terminal VDD3, and the second node N2has a potential of Vdd3.

Additionally, under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls an electrical connection between the second electrode of the driving sub-circuit150and the third electrode of the driving sub-circuit150, which in turn causes that the level at the third electrode of the driving sub-circuit150is
Vdd+Vth;(1)
where Vdd is the first voltage signal Vdd1that the first electrode of the driving sub-circuit150revives from the first voltage input terminal VDD1(because Vdd1=Vdd), and Vth is a threshold voltage of the driving sub-circuit150.

Specifically, during the writing-compensation control stage T1of each display cycle, the gate line Gate sends the gate signal Vgate to the first transistor111, the second transistor112, and the third transistor113.

Under control of the gate signal Vgate, the source electrode and the drain electrode of the first transistor111are electrically connected, causing the data line DL to be electrically connected to the first electrode of the first storage capacitor131. As such, the data signal Vdata is inputted or written to the first storage capacitor131, and the first node has a potential of Vdata.

Further under control of the gate signal Vgate, the source electrode and the drain electrode of the second transistor112are electrically connected, causing the second node N2to be electrically connected to the third voltage input terminal VDD3. As such, when the third voltage signal Vdd3is applied to the third voltage input terminal VDD3, the second node N2has a potential of Vdd (because Vdd3=Vdd).

Further under control of the gate signal Vgate, the source electrode and the drain electrode of the third transistor113are electrically connected, causing the second electrode of the driving sub-circuit150to be electrically connected with the third electrode of the driving sub-circuit150. As such, when the first voltage signal Vdd1is applied to the first voltage input terminal VDD1, the source electrode and the drain electrode of the driving transistor151are electrically connected, and the first voltage signal Vdd1is transmitted from the source electrode to the drain electrode, and the first voltage signal Vdd1is further transmitted to the gate electrode of the driving transistor151via the third transistor113. Then after electrical disconnection between the source electrode and the drain electrode of the driving transistor151, the gate electrode of the driving transistor151has a potential of Vdd+Vth after stabilization.

During the light-emission control stage T2of each display cycle, the light-emission control signal Vem inputted from the light-emission control signal line EM is a low-level signal, and the gate signal Vgate inputted from the gate line Gate is a high-level signal.

Under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the first node N1is electrically disconnected with the data line DL, causing that the first node N1does not receive the data signal Vdata. Because in the above writing-compensation control stage T1, the first node N1has a potential of Vdata, at the light-emission control stage T2, the first node N1still has a potential of Vdata.

Further under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the second node N2is electrically disconnected with the third voltage input terminal VDD3, causing that the second node N2does not receive the third voltage signal Vdd3from the third voltage input terminal VDD3.

Additionally, under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the second electrode of the driving sub-circuit150is electrically disconnected with the third electrode of the driving sub-circuit150.

Specifically, under control of the gate signal Vgate, the source electrode and the drain electrode of the first transistor111are electrically disconnected, the first node N1is electrically disconnected with the data line DL, and the first node N1still has a potential of Vdata. Additionally, under control of the gate signal Vgate, the source electrode and the drain electrode of the second transistor112are electrically disconnected, the second node N2is electrically disconnected with the third voltage input terminal VDD3. Furthermore, under control of the gate signal Vgate, the source electrode and the drain electrode of the third transistor113are electrically disconnected, the drain electrode and the gate electrode of the second transistor112are electrically disconnected.

Under control of the light-emission control signal Vem, the light-emission control sub-circuit120controls that the first node N1is electrically connected with the second node N2, causing that the second node N2has a potential of Vdata. Further under control of the light-emission control signal Vem, the light-emission control sub-circuit120controls that the second electrode of the driving sub-circuit150is electrically connected with the light-emission sub-circuit160, in turn causing the light-emission sub-circuit160to emit lights.

Specifically, under control of the light-emission control signal Vem, the source electrode and the drain electrode of the fourth transistor121are electrically connected, thus the first node N1is electrically connected with the second node N2, causing that each of the first node N1and the second node N2has a potential of Vdata. Additionally, under the light-emission control signal Vem, the source electrode and the drain electrode of the fifth transistor122are electrically connected, thus the drain electrode of the driving transistor151is electrically connected with the light-emitting component161in the light-emission sub-circuit160, causing that the first voltage signal Vdd1from the first voltage input terminal VDD1is able to pass through the driving transistor151to thereby drive the light-emitting component161to emit lights.

During the writing-compensation control stage T1, because each of the first transistor111, the second transistor112, the third transistor113is electrically turned on under control of the gate signal Vgate, whereas each of the fourth transistor121and the fifth transistor122is electrically turned off under control of the light-emission control signal Vem, the first node N1has a potential of Vdata, the first electrode of the first storage capacitor131has a same potential as the first node N1and thus also has a potential of Vdata.

Because the second electrode of the first storage capacitor131is connected to the second voltage input terminal VDD2, the second electrode of the first storage capacitor131has a potential of Vdd (because Vdd2=Vdd). Because of the second node N2is electrically connected to the third voltage input terminal VDD3via the second transistor112, the second node N2has a potential of Vdd (because Vdd3=Vdd).

Because the second electrode of the second storage capacitor141is electrically connected to the second node N2, the second electrode of the second storage capacitor141has a potential of Vdd. Because the first electrode of the second storage capacitor141is connected to the gate electrode of the driving transistor151, and also because the third transistor113is equivalent to a turned-on diode, which allows only one-direction conduction, therefore the first electrode of the second storage capacitor141has a potential of Vdd+Vth.

During the light-emission control stage T2, each of the fourth transistor121and the fifth transistor122is electrically turned on under control of the light-emission control signal Vem, whereas each of the first transistor111, the second transistor112, the third transistor113is electrically turned off under control of the gate signal Vgate. As such, the first node N1still has a potential of Vdata, the first electrode of the first storage capacitor131still has a potential of Vdata, and the second electrode of the first storage capacitor131still has a potential of Vdd.

As to the second node N2, because the second node N2is electrically connected to the first node N1, and the second node N2is electrically disconnected to the third voltage input terminal VDD3, as such, the second node N2has a potential of Vdata. Furthermore, because the second electrode of the second storage capacitor141is electrically connected to the second node N2, the second electrode of the second storage capacitor141also has a potential of Vdata.

Regardless of the writing-compensation control stage T1or the light-emission control stage T2, the total electrical charge in the first storage capacitor131and in the second storage capacitor141remains unchanged, which can be respectively calculated by the formula (2):
C2×U21+C1×U11=C2×U22+C1×U12;  (2)
where C1 is the capacitance of the first storage capacitor131, C2 is the capacitance of the second storage capacitor141, U11 is the voltage between the first electrode and the second electrode of the first storage capacitor131during the writing-compensation control stage T1, U21 is the voltage between the first electrode and the second electrode of the second storage capacitor141during the writing-compensation control stage T1, U12 is the voltage between the first electrode and the second electrode of the first storage capacitor131during the light-emission control stage T2, U22 is the voltage between the first electrode and the second electrode of the second storage capacitor141during the light-emission control stage T2.

After substituting each parameter in the formula (2), the following formula (3) is further obtained:
C2×(Vdd+Vth−Vdd+C1×(Vdd−Vdata)=C2×(Vg−Vdata)+C1×(Vdd−Vdata);  (3)

After reduction of the above formula (3), the formula (4) is obtained.
Vg=Vdata+Vth;(4)
where Vg is the potential at the first electrode of the second storage capacitor141. Because the first electrode of the second storage capacitor141is electrically connected to the gate electrode of the driving transistor151, the gate electrode of the driving transistor151also has a potential of Vg. In other words, during the light-emission control stage T2, the potential at the gate electrode of the driving transistor151is Vdata+Vth.

Furthermore, if the current characteristics of the driving transistor151is considered, i.e., in the calculation of the current, if the driving transistor151has a characteristics of a constant current, the formula (5) is satisfied:
Vds=Vgs−Vth;(5)
After the substitution of formula (5), the formula (6) is obtained:
Vgs−Vth=Vdata+Vth−Vth−Vdd=Vdata−Vdd;(6)

As illustrated by the formula (6), during the light-emission control stage T2, when the driving transistor151has a characteristics of a constant current, Vds=Vdata−Vdd. In other words, the current that runs through the driving transistor151and drives the light-emission component161is related to Vdata−Vdd, but is not related to the threshold voltage Vth of the driving transistor151.

As such, when emitting lights, the light-emission component161is not influenced by deviation or drifting of the threshold voltage Vth of the driving transistor151. Thereby, thought the pixel driving circuit disclosed herein, the threshold voltage Vth of the driving transistor151is compensated for the deviation or drifting thereof, and the voltage writing is also combined with the threshold voltage compensation.

Compared with the traditional OLED display technologies, which typically have four stages including a reset stage, threshold voltage compensation stage, a data signal writing stage, and a light emission stage, the pixel driving circuit disclosed herein allows a reduction to only two stages. As such, the non-light-emission time period is effectively reduced, the response speed of the pixel circuit is increased, in turn realizing a consistent and even brightness among different pixels, leading to an even brightness of the display apparatus.

It is noted that the above embodiments of the pixel driving circuit and its driving method are illustrated with the third voltage input terminal VDD3and the first voltage input terminal VDD1being a same voltage input terminal, yet other embodiments are also possible.

FIG. 3illustrates a circuit diagram of a pixel driving circuit according to some other embodiments of the present disclosure. As shown inFIG. 3, the third voltage input terminal VREF and the first voltage input terminal VDD1are different voltage input terminals. In other words, the third voltage signal from the third voltage input terminal VREF is substantially different from the first voltage signal from the first voltage input terminal VDD1.

Correspondingly, during the writing-compensation control stage T1, because each of the first transistor111, the second transistor112, the third transistor113is electrically turned on under control of the gate signal Vgate, whereas each of the fourth transistor121and the fifth transistor122is electrically turned off under control of the light-emission control signal Vem, the first node N1has a potential of Vdata, the first electrode of the first storage capacitor131has a same potential as the first node N1and thus also has a potential of Vdata.

Because the second electrode of the first storage capacitor131is connected to the second voltage input terminal VDD2, the second electrode of the first storage capacitor131has a potential of Vdd (because Vdd2=Vdd). Because the second node N2is electrically connected to the third voltage input terminal VREF via the second transistor112, the second node N2has a potential of Vref.

Because the second electrode of the second storage capacitor141is electrically connected to the second node N2, the second electrode of the second storage capacitor141has a potential of Vref. Because the first electrode of the second storage capacitor141is connected to the gate electrode of the driving transistor151, and also because the third transistor113is equivalent to a turned-on diode, which allows only one-direction conduction, therefore the first electrode of the second storage capacitor141has a potential of Vref+Vth.

During the light-emission control stage T2, each of the fourth transistor121and the fifth transistor122is electrically turned on under control of the light-emission control signal Vem, whereas each of the first transistor111, the second transistor112, and the third transistor113is electrically turned off under control of the gate signal Vgate. As such, the first node N1still has a potential of Vdata, the first electrode of the first storage capacitor131still has a potential of Vdata, and the second electrode of the first storage capacitor131still has a potential of Vdd.

As to the second node N2, because the second node N2is electrically connected to the first node N1, and the second node N2is electrically disconnected to the third voltage input terminal VREF, as such, the second node N2has a potential of Vdata. Furthermore, because the second electrode of the second storage capacitor141is electrically connected to the second node N2, the second electrode of the second storage capacitor141also has a potential of Vdata.

Regardless of the writing-compensation control stage T1or the light-emission control stage T2, the total electrical charge in the first storage capacitor131and in the second storage capacitor141remains unchanged, which can be respectively calculated by the formula (2):
C2×U21+C1×U11=C2×U12+C1×U12;  (2)
where C1 is the capacitance of the first storage capacitor131, C2 is the capacitance of the second storage capacitor141, U11 is the voltage between the first electrode and the second electrode of the first storage capacitor131during the writing-compensation control stage T1, U21 is the voltage between the first electrode and the second electrode of the second storage capacitor141during the writing-compensation control stage T1, U12 is the voltage between the first electrode and the second electrode of the first storage capacitor131during the light-emission control stage T2, U22 is the voltage between the first electrode and the second electrode of the second storage capacitor141during the light-emission control stage T2.

After substituting each parameter in the formula (2), the following formula (7) is further obtained:
C2×(Vdd+Vth−Vref)+C1×(Vdd−Vdata)=C2×(Vg−Vdata)+C1×(Vdd−Vdata);  (7)

After reduction of the above formula (7), the formula (8) is obtained.
Vg=Vdd+Vth+Vdata−Vref;  (8)
where Vg is the potential at the first electrode of the second storage capacitor141. Because the first electrode of the second storage capacitor141is electrically connected to the gate electrode of the driving transistor151, the gate electrode of the driving transistor151also has a potential of Vg. In other words, during the light-emission control stage T2, the potential at the gate electrode of the driving transistor151is Vdd+Vth+Vdata−Vref.

Furthermore, if the current characteristics of the driving transistor151is considered, i.e., in the calculation of the current, if the driving transistor151has a characteristics of a constant current, the formula (5) is satisfied:
Vds=Vgs−Vth;(5)
After the substitution of formula (5) in formula (8), the formula (9) is obtained:
Vgs−Vth=Vdd+Vth+Vdata−Vref−Vth−Vdd=Vdata−Vref;  (9)

As illustrated by the formula (9), during the light-emission control stage T2, when the driving transistor151has a characteristics of a constant current, Vds=Vdata−Vref. In other words, the current that runs through the driving transistor151and drives the light-emission component161is related to Vdata−Vref, but is not related to the threshold voltage Vth of the driving transistor151.

As such, when emitting lights, the light-emission component161is not influenced by deviation or drifting of the threshold voltage Vth of the driving transistor151. Thereby, thought the pixel driving circuit disclosed herein, the threshold voltage Vth of the driving transistor151is compensated for the deviation or drifting thereof, and the voltage writing is also combined with the threshold voltage compensation.

Compared with the traditional OLED display technologies, which typically have four stages including a reset stage, threshold voltage compensation stage, a data signal writing stage, and a light emission stage, the pixel driving circuit disclosed herein allows a reduction to only two stages. As such, the non-light-emission time period is effectively reduced, the response speed of the pixel circuit is increased, in turn realizing a consistent and even brightness among different pixels, leading to an even brightness of the display apparatus.

Furthermore, the light-emission control stage of the pixel driving circuit is related to Vref, but is not related to Vdd. As such, the influence of the voltage drop (i.e. IR drop) of Vdd on the driving circuit can be effectively avoided, leading to a further improved display effect.

FIG. 4illustrates a circuit diagram of a pixel driving circuit according to yet some other embodiments of the present disclosure. Compared with the embodiments illustrated inFIG. 1, the embodiments of the pixel driving circuit illustrated inFIG. 4further comprises a first initiating sub-circuit170.

The first initiating sub-circuit170is electrically coupled with the light-emission sub-circuit160, and is specifically between the first initiating signal line Init1and the light-emission sub-circuit160. Additionally, the first initiating sub-circuit170is electrically connected to a first initiating control signal line Gk1.

The first initiating sub-circuit170is configured to receive a first initiating control signal Vgk1from the first initiating control signal line Gk1, and is further configured, under control of the first initiating control signal Vgk1, to control whether the light-emission sub-circuit160is electrically connected with the first initiating signal line Init1, to thereby control whether the light-emission sub-circuit160can receive a first initiating signal Vinit1from the first initiating signal line Init1.

Specifically, the first initiating sub-circuit170comprises a first initiating transistor171. A source electrode of the first initiating transistor171is electrically coupled to the first initiating signal line Init1, and is configured to receive the first initiating signal Vinit1from the first initiating signal line Init1. A drain electrode of the first initiating transistor171is electrically coupled to the light-emission component161of the light-emission sub-circuit160. A gate electrode of the first initiating transistor171is electrically coupled to the first initiating control signal line Gk1, and is configured to receive first initiating control signal Vgk1from the first initiating control signal line Gk1.

The first initiating transistor171is configured, under control of the first initiating control signal Vgk1, to control whether the source electrode and the drain electrode of the first initiating transistor171are electrically connected, in turn controlling whether the light-emission component161of the light-emission sub-circuit160is electrically connected with the first initiating signal line Init1, to thereby control whether the light-emission component161can receive the first initiating signal Vinit1from the first initiating signal line Init1.

FIG. 5illustrates a time sequence diagram of the pixel driving circuit as shown inFIG. 4. As shown inFIG. 5, each display cycle of the pixel driving circuit as illustrated inFIG. 4further includes an initiation stage T3prior to the writing-compensation control stage T1.

Correspondingly, the method for driving a pixel driving circuit100according to the above mentioned embodiments illustrated inFIG. 4is further provided. Specifically, during the initiation stage T3, the first initiating control signal Vgk1from the first initiating control signal line Gk1is a low-level signal, the light-emission control signal Vem inputted from the light-emission control signal line EM is a high-level signal, and the gate signal Vgate inputted from the gate line Gate is a high-level signal.

Under control of the first initiating control signal Vgk1, the first initiating sub-circuit170controls that the light-emission sub-circuit160is electrically connected to the first initiating signal line Init1, and further controls that the light-emission sub-circuit160receives the first initiating signal Vinit1from the first initiating signal line Init1, such that the first initiating signal Vinit1is written or inputted to the first electrode of the light-emission sub-circuit160to realize an initiation of the light-emission sub-circuit160. As such, the first electrode of the light-emission sub-circuit160is set at a low level prior to the writing-compensation control stage T1and the light-emission control stage T2, ensuring that no light is emitting from any pixels, to in turn increase the contrast of the display panel.

Specifically, during the initiation stage T3, under control of the first initiating control signal Vgk1, the source electrode and the drain electrode of the first initiating transistor171are electrically connected, causing the light-emission sub-circuit160to be electrically connected to the first initiating signal line Init1. Thereby, the light-emission sub-circuit160can receive the first initiating signal Vinit1from the first initiating signal line Init1to thereby realize the initiation process.

Furthermore, during the initiation stage T3, under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the first node N1is electrically disconnected from the data line DL, and thus the first node N1does not receive the data signal Vdata.

Additionally under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the second node N2is electrically disconnected from the third voltage input terminal VDD3, and thus the second node N2does not receive the third voltage signal Vdd3.

Further under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the second electrode of the driving sub-circuit150is electrically disconnected from the third electrode of the driving sub-circuit150.

Furthermore, during the initiation stage T3, under control of the light-emission control signal Vem, the light-emission control sub-circuit120controls that the first node N1is electrically disconnected from the second node N2, and that the second electrode of the driving sub-circuit150is electrically disconnected from the light-emission sub-circuit160.

FIG. 6illustrates a circuit diagram of a pixel driving circuit according to yet some other embodiments of the present disclosure. Compared with the embodiments of the pixel driving circuit illustrated inFIG. 1, the embodiments of the pixel driving circuit illustrated inFIG. 6further comprises a second initiating sub-circuit180.

The second initiating sub-circuit180is electrically coupled with the first node N1, and is specifically between a second initiating signal line Init2and the first node N1. Additionally, the second initiating sub-circuit180is electrically connected to a second initiating control signal line Gk2.

The second initiating sub-circuit180is configured to receive a second initiating control signal Vgk2from the second initiating control signal line Gk2, and is further configured, under control of the second initiating control signal Vgk2, to control whether the first node N1is electrically connected with the second initiating signal line Init2, to thereby control whether the first node N1can receive a second initiating signal Vinit2from the second initiating signal line Init2.

Specifically, the second initiating sub-circuit180comprises a second initiating transistor181. A source electrode of the second initiating transistor181is electrically coupled to the second initiating signal line Init2, and is configured to receive the second initiating signal Vinit2from the second initiating signal line Init2. A drain electrode of the second initiating transistor181is electrically coupled to the first node N1. A gate electrode of the second initiating transistor181is electrically coupled to the second initiating control signal line Gk2, and is configured to receive the second initiating control signal Vgk2from the second initiating control signal line Gk2.

The second initiating transistor181is configured, under control of the second initiating control signal Vgk2, to control whether the source electrode and the drain electrode of the second initiating transistor181are electrically connected, in turn controlling whether the first node N1is electrically connected with the second initiating signal line Init2, to thereby control whether the first node N1can receive the second initiating signal Vinit2from the second initiating signal line Init2.

FIG. 7illustrates a time sequence diagram of the pixel driving circuit as shown inFIG. 6. As shown inFIG. 7, each display cycle of the pixel driving circuit as illustrated inFIG. 6further includes an initiation stage T3prior to the writing-compensation control stage T1.

Correspondingly, the method for driving a pixel driving circuit100according to the above mentioned embodiments illustrated inFIG. 6is further provided. Specifically, during the initiation stage T3, the second initiating control signal Vgk2from the second initiating control signal line Gk2is a low-level signal, the light-emission control signal Vem inputted from the light-emission control signal line EM is a high-level signal, and the gate signal Vgate inputted from the gate line Gate is a high-level signal.

Under control of the second initiating control signal Vgk2, the second initiating sub-circuit180controls that the first node N1is electrically connected to the second initiating signal line Init2, and further controls that the first node N1receives the second initiating signal Vinit2from the second initiating signal line Init2, such that the second initiating signal Vinit2is written or inputted to the first node N1, and is further written or inputted to the first electrode of the first storage capacitor131to realize an initiation of the first storage capacitor131. As such, the first electrode of the first storage capacitor131is set at a low level prior to the writing-compensation control stage T1and the light-emission control stage T2, allowing an improved writing effect of the data signal Vdata.

Specifically, during the initiation stage T3, under control of the second initiating control signal Vgk2, the source electrode and the drain electrode of the second initiating transistor181are electrically connected, causing the first node N1to be electrically connected to the second initiating signal line Init2. Thereby, the first node N1can receive the second initiating signal Vinit2from the second initiating signal line Init2to thereby realize the initiation process.

Furthermore, during the initiation stage T3, under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the first node N1is electrically disconnected from the data line DL, and thus the first node N1does not receive the data signal Vdata.

Additionally under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the second node N2is electrically disconnected from the third voltage input terminal VDD3, and thus the second node N2does not receive the third voltage signal Vdd3.

Further under control of the gate signal Vgate, the writing-compensation control sub-circuit110controls that the second electrode of the driving sub-circuit150is electrically disconnected from the third electrode of the driving sub-circuit150.

Furthermore, during the initiation stage T3, under control of the light-emission control signal Vem, the light-emission control sub-circuit120controls that the first node N1is electrically disconnected from the second node N2, and that the second electrode of the driving sub-circuit150is electrically disconnected from the light-emission sub-circuit160.

In the above mentioned embodiments of the pixel driving circuit as illustrated inFIG. 4andFIG. 6, the first initiating sub-circuit170and the second initiating sub-circuit180are separately added in the pixel driving circuit100shown inFIG. 1, respectively. It is noted that other embodiments are possible.

For example, according to some other embodiments shown inFIG. 8, both the first initiating sub-circuit170and the second initiating sub-circuit180are added in the pixel driving circuit100shown inFIG. 1.

The circuit diagram and the time sequence diagram of the pixel driving circuit shown inFIG. 8can reference to the embodiments shown inFIG. 4,FIG. 5,FIG. 6, andFIG. 7, which are skipped herein.

In a third aspect, the present disclosure further provides a display apparatus, which includes a pixel driving circuit according to any one of the embodiments as described above.

Although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise.