Increasing output amplitude of a voltage-mode driver in a low supply voltage technology

An apparatus for driving a load using a low supply voltage includes a voltage-mode driver and a current source arrangement. The voltage-mode driver provides a desired termination impedance and a first portion of a desired output current to the load. The current source arrangement provides a second portion of the desired output current. The desired output current generates a predetermined voltage swing across the load, while the voltage-mode driver and the current source arrangement are powered by the low supply voltage.

TECHNICAL FIELD

The present description relates generally to line drivers, and more particularly, but not exclusively, to methods and apparatus for increasing output amplitude of a voltage-mode driver in a low supply-voltage technology.

BACKGROUND

Line drivers including voltage-mode drivers are used in a number of applications such as mobile serializer-deserializer (SerDes) circuits, network switches and data center applications, and high speed PHY circuits. The main function of a line driver is to transmit a signal reliably across a medium (e.g., a line such as a conductor), in the presence of attenuation and distortion.

The required transmitted output swing specified by current standards (e.g., the IEEE standards) is technology independent. With technology nodes moving to smaller feature sizes, however, nominal supply voltage is also scaled down. For example, the 802.3ap standard for backplane Ethernet interface (e.g., IEEE KR) requires a minimum differential peak-to-peak voltage of 800 mV, which is greater than a nominal supply voltage that technologies below 28 nm can support. In a 16 nm technology, for instance, the supply voltage is approximately 800 mV. Some of the existing solutions increase the driver power supply and use a level shifter from the voltage-driver core to the power supply, which increases power consumption, or use two power supplies or a low drop-out (LDO) circuit. Other solutions use lower on-chip resistors, which sacrifices an important transmitter specification such as a return loss.

DETAILED DESCRIPTION

The subject technology provides methods and implementations for increasing output amplitude of a voltage-mode driver in a low supply-voltage technology. The disclosed technology merges a voltage-mode driver with a current driver (e.g., an H-driver) to provide a minimum differential peak-to-peak voltage across the load, as required by the current standards. The subject technology includes a number of advantageous features, for example, reduced power consumption and chip area without sacrificing the return loss, as compared to existing solutions that, for instance, rely on voltage mode drivers with increased power supply or decreased on-chip resistors or other solutions based on H-drivers or current-mode logic (CML) drivers. Further, the disclosed solution is the lowest power solution that is compliant with current standards (e.g., IEEE standards) and future process technologies.

FIG. 1illustrates an example of a voltage-mode driver circuit100for driving a load impedance. The voltage-mode driver circuit100includes resistors R1-R4and switches S1-S4and is used to drive the load resistor RL, which can be an input impedance of a device such as a serializer/deserializer (SerDes). The voltage-mode driver circuit100is implemented in a technology node (e.g., 16 nm) that allows a limited supply voltage (e.g., VDD=0.8V). On the other hand, the current standard (e.g., an IEEE standard, such as IEEE KR) requires a nominal voltage swing (e.g., differential peak-to-peak voltage) of ˜1V across the load impedance such as a resistor RL(e.g., 100Ω), and the voltage-mode driver circuit100has to provide an impedance match to the load resistor RL. The voltage-mode driver circuit100operates by providing current I1to the load resistor RL, through termination resistors R1and R4, in a positive bit of data when switches S1and S4are closed and switches S2and S3are open, and providing current I2to the load resistor RL, through termination resistors R3and R2, in a negative bit of the data when switches S3and S2are closed and switches S1and S4are open.

With an example value of 100Ω for the load resistor RL, each of the termination resistors R1-R4has to be ˜50Ω. It is understood that for this example, with VDD=0.8V, the value of currents I1and I2cannot exceed ˜4 mA. In other words, the voltage swing (e.g., differential peak-to-peak amplitude) across the 100Ω load resistor RLcannot exceed ˜800 mV, which is less than the nominal value of 1V required by the standard. Existing solutions for mitigating this problem face a number of drawbacks including increased power consumption and chip area and may sacrifice an important specification such as return loss. The subject technology, as disclosed herein, solves this problem without the above-mentions drawbacks.

FIGS. 2A through 2Eillustrate examples of an apparatus for driving a load using a low supply voltage in accordance with one or more implementations of the subject technology. An apparatus200A ofFIG. 2A, for example, includes a first circuit210and a second circuit220. The first circuit210can be a voltage-mode driver circuit such as the voltage-mode driver circuit100ofFIG. 1. The second circuit220includes a current source arrangement. The first circuit210can provide the desired termination impedance and a first portion of a desired output current to the load resistor (e.g., RLofFIG. 1). The first circuit210and the second circuit220are powered by a low supply voltage VDD(e.g., 0.8 V) that is a nominal supply voltage associated with an employed technology node (e.g., 16 nm). With this nominal supply voltage, the first circuit210would be incapable of independently providing a minimum current (e.g., 10 mA) to the resistor RL(e.g., 100Ω) ofFIG. 1that can establish the nominal voltage swing (e.g., 1V) across the load resistor RL, particularly in the presence of variations, for example, of the resistance values.

The current source arrangement220provides a second portion of the desired output current that can generate the predetermined voltage swing (e.g., the nominal voltage of 1V) across the 100Ω load resistor RLofFIG. 1. In one or more implementations, the current source arrangement220includes current sources I1-I4and switches S1-S4that are configurable to provide the second portion (e.g., 2 mA) of the desired output current (e.g., 5 mA) flowing in two opposing directions indicated by the curved arrows D1and D2into the load (not shown for simplicity). For example, in a positive bit of data when switches S1and S4are closed and switches S2and S3are open, current sources I1and I4(e.g., identical current sources) are active and are responsible for providing the second portion of the desired output current. In a negative bit of the data when switches S3and S2are closed and switches S1and S4are open, current sources I3and I2(e.g., identical current sources) are active and provide the second portion of the desired output current. In one or more aspects, the switches S1-S4are configurable to dynamically control an amount of current provided to the load.

In one or more implementations, the first circuit210is implemented as the voltage-mode driver circuit212ofFIG. 2B. The voltage-mode driver circuit212is similar to the voltage-mode driver circuit100ofFIG. 1, and can be implemented to provide the desired termination impedance (e.g., through R1and R4or R3and R2) that matches resistance of the load resistor RL (e.g., 100Ω) and a fixed output voltage. The deficiency of the voltage-mode driver circuit212in providing the desired current through the load resistor RLis alleviated by the current source arrangement222, which is similar to the current source arrangement220ofFIG. 2Adescribed above.

In some implementations, the first circuit210is realized as a constant-impedance voltage-mode driver circuit214ofFIG. 2C. The constant-impedance voltage-mode driver circuit214includes variable resistors Rv1and Rv2that can be controlled independently to provide constant-impedance values (e.g., as viewed by a signal) between nodes Out1and Out2and the ground node, while allowing variation of the voltage amplitude (e.g., based on pre-emphasis) across the load resistor RL. The constant-impedance voltage-mode driver circuit214can be implemented to provide the desired termination impedance, while the current source arrangement224, which is similar to the current source arrangement220ofFIG. 2Adescribed above, provides the additional current through the load resistor RLthat can establish the desired voltage swing across the load resistor RL(e.g., 100Ω).

In some aspects, the first circuit210is implemented as a variable-impedance voltage-mode driver circuit216ofFIG. 2D. The variable-impedance voltage-mode driver circuit216includes variable resistors Rv1and provides variable impedance and voltage amplitude values between nodes Out1and Out2and the ground node. The current source arrangement226is similar to the current source arrangement220ofFIG. 2Adescribed above.

In one or more implementations, the first circuit210is realized as a constant-impedance voltage-mode driver circuit218with shunt elements, as shown inFIG. 2E. The shunt elements include the variable resistors Rv1and Rv2provide a constant impedance values at nodes Out1and Out2, while allowing variation of the voltage amplitude (e.g., based on pre-emphasis) across the load resistor RL. The constant-impedance voltage-mode driver circuit218is a lower power consumption implementation of the constant-impedance voltage-mode driver circuit214ofFIG. 2C. The current source arrangement228is similar to the current source arrangement220ofFIG. 2Adescribed above.

Each of the above-described voltage-mode driver circuits (e.g.,210,212,214,216, and218) or the current source arrangement220are configurable to provide a desired termination impedance and output voltage amplitude control and/or equalization control, while maintaining a predetermined range of voltage swing (e.g., based on a standard) across the load resistor RL. The desired termination impedance is determined based on a desired return loss and is typically within the range of 80-120Ω.

FIGS. 3A-3Billustrate examples of configurable current sources I1and I2of an apparatus for driving a load using a low supply voltage in accordance with one or more implementations of the subject technology. As shown inFIG. 3A, a branch310(e.g., an upper portion of the current source arrangement220ofFIG. 2A) including the current source I1and the switch S1can be implemented by a parallel combination312of a number of branches including current sources I11through I1N and switches S11through S1N. The switches S11through S1N can be dynamically controlled to drive desired current values to the load resistor (e.g., RLofFIG. 2B).

FIG. 3Bshows a, a branch314(e.g., a lower portion of the current source arrangement220ofFIG. 2A) including a switch S2and the current source I2can be realized by a parallel combination316of a number of branches including switches S21through S2N and current sources I21through I2N. The switches S21through S2N can be dynamically controlled to drive desired current values to the load resistor (e.g., RLofFIG. 2B). For example, the configurable arrangements312and316allows for current sources I1and I2of any of the above-described current source arrangements (e.g.,220ofFIG. 2A) to have equal or different current values that can be dynamically controlled.

FIG. 4illustrates an example of a method400for driving a load using a low supply voltage in accordance with one or more implementations of the subject technology. For explanatory purposes, the blocks of the example method400are described herein as occurring in serial, or linearly. However, multiple blocks of the example method400can occur in parallel. In addition, the blocks of the example method400need not be performed in the order shown and/or one or more of the blocks of the example method400need not be performed.

The method400includes providing, by using a first circuit (e.g.,210ofFIG. 2A), a desired termination impedance (e.g., R1+R4or R3+R2ofFIG. 2B) and a first portion of a desired output current to the load (e.g., RLofFIG. 2A) (410). A second portion of the desired output current is provided, by using a second circuit (e.g.,220ofFIG. 2A), such that the desired output current generates a predetermined voltage swing across the load, while the first circuit and the second circuit are powered by the low supply voltage (e.g., VDDofFIG. 2A) (420).

FIG. 5illustrates an example of a communication device500employing features of the subject technology for driving one more loads using a low supply voltage in accordance with one or more implementations. Examples of the communication device500includes an Ethernet switch of an Ethernet network such as a private network including a data-center network, an enterprise network, or other private networks. The communication device500includes a number of ingress (input) ports IP1-IPn and multiple egress (output) ports EP1-EPm. In one or more implementations, one or more of the ingress ports IP1-IPn can receive a data packet from another switch or and endpoint device of the network. The communication device500further includes a hardware component such as an application specific integrated circuit (ASIC)510(which in some embodiments can be implemented as a field-programmable logic array (FPGA)), a buffer520, a processor530, memory540, and a software module550.

In some implementations, the ASIC510can include suitable logic, circuitry, interfaces and/or code that can be operable to perform functionalities of a PHY circuit. The buffer520includes suitable logic, circuitry, code and/or interfaces that are operable to receive and store and/or delay a block of data for communication through one or more of the egress ports EP1-EPm. The processor530includes suitable logic, circuitry, and/or code that can enable processing data and/or controlling operations of the communication device500. In this regard, the processor530can be enabled to provide control signals to various other portions of the communication device500. The processor530also controls transfers of data between various portions of the communication device500. Additionally, the processor530can enable implementation of an operating system or otherwise execute code to manage operations of the communication device500.

The memory540includes suitable logic, circuitry, and/or code that can enable storage of various types of information such as received data, generated data, code, and/or configuration information. The memory540includes, for example, RAM, ROM, flash, and/or magnetic storage. In various embodiment of the subject technology, the memory540may include a RAM, DRAM, SRAM, T-RAM, Z-RAM, TTRAM, or any other storage media. The memory540can include software modules550that when executed by a processor (e.g., processor530) can perform some or all of the functionalities of the ASIC510. In some implementations, the software modules550include codes that when executed by a processor can perform functionalities such as configuration of the communication device500.

In some implementations the communication device500may be implemented in a 28 nm or smaller technology node and be powered by a low voltage supply (e.g., 0.8V). In these implementations, various chips (e.g., the ASIC510, the processor530, and the memory540) of the communication device500may be coupled to one another via lines that are driven by voltage-mode drivers of the subject technology such as the apparatuses shown in any ofFIGS. 2A through 2Eto provide acceptable voltage swings across input nodes of the chips. In some aspects, the communication device500includes one or more universal serial bus (USB) interfaces that can also be driven by the disclosed voltage-mode drivers and benefit from the advantages features of the subject technology such as low power consumption, reduced chip area, and without return loss.

A phrase such as “an aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect can apply to all configurations, or one or more configurations. An aspect can provide one or more examples of the disclosure. A phrase such as an “aspect” refers to one or more aspects and vice versa. A phrase such as an “embodiment” does not imply that such embodiment is essential to the subject technology or that such embodiment applies to all configurations of the subject technology. A disclosure relating to an embodiment can apply to all embodiments, or one or more embodiments. An embodiment can provide one or more examples of the disclosure. A phrase such an “embodiment” can refer to one or more embodiments and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. A disclosure relating to a configuration can apply to all configurations, or one or more configurations. A configuration can provide one or more examples of the disclosure. A phrase such as a “configuration” can refer to one or more configurations and vice versa.