Fabrication of ultra-shallow junctions

A method of forming an ultra-shallow junction in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate by performing a pre-amorphization implant step and implanting one or more dopants in the amorphous region by performing a monolayer doping step. The semiconductor substrate is then thermally treated to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The thermal treatment can be performed without any oxide cap overlying the implanted amorphous region.

BACKGROUND

Integrated circuits (ICs) having a plurality of semiconductor devices including field effect transistors (FETs) are a cornerstone of modern microelectronic systems. Conventionally, the various regions of FETs (e.g., source/drain and source/drain extensions) are formed by introducing dopant atoms into a semiconductor substrate using methods such as ion implantation, etc. After the dopants have been introduced, they are electrically activated by subjecting the semiconductor substrate to one or more annealing processes such as low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing.

Dopants, however, have a tendency to diffuse or expand both laterally and vertically away from the profile during annealing thereby increasing the dimensions of the various device regions. This diffusion of dopants is undesirable particularly as semiconductor devices are scaled down in size. Scaling device dimensions down to the molecular regime thus presents a fundamental and technological challenge for fabricating well defined structures with controlled atomic composition.

One proposed route for achieving fine control of structural composition is the integration of self-limiting and self-assembly processes where surface and chemical phenomena guide the synthesis and fabrication of the desired nanostructures. There is a need for technology to demonstrate reliable nanoscale doping of silicon structures, e.g., for well-defined and uniformly doped ultra-shallow junctions at the source and drain extension regions. Conventional ion implantation processes which rely on bombardment of semiconductors with energetic ions suffer from an inability to achieve an implantation range and abruptness down to the nanometer range, a stochastic spatial distribution of the implanted ions, an incompatibility with nanostructured materials, and crystal damage. Solid-source diffusion processes lack the desired uniformity and control over the areal dose of the dopants to be used for miniaturized device fabrication. Monolayer doping (MLD), however, can attain a controlled doping of semiconductor materials with atomic accuracy. Generally, MLD utilizes the crystalline nature of semiconductors to form highly uniform, self-assembled, covalently bonded dopant-containing monolayers followed by a subsequent annealing step for the incorporation and diffusion of dopants.

Exemplary monolayer formation reactions are self-limiting and result in a deterministic coverage of dopant atoms on the semiconductor surface. MLD differs from other conventional doping techniques by method of dopant dose control. For example, as compared to ion-implantation, MLD does not involve a highly energetic introduction of dopant species into the semiconductor lattice where crystal damages are induced. To prevent dopant loss, however, conventional MLD techniques require an oxide cap layer to protect respective dopants during subsequent thermal processes. Thus, there is a need to provide or fabricate ultra-shallow junctions without depositing and/or removing such an oxide cap.

DETAILED DESCRIPTION

Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. The terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy. Moreover, space orientation terms such as “under”, “on”, “up”, “down”, etc. are used to describe a relationship between a device or a characteristic and another device or another characteristic in the drawing. It should be noted that the space orientation term can cover different orientations of the device besides the orientation of the device illustrated in the drawing. For example, if the device in the drawing is turned over, the device located “under” or “below” the other devices or characteristics is reoriented to be located “above” the other devices or characteristics. Therefore, the space orientation term “under” may include two orientations of “above” and “below”.

FIG. 1is a diagram of one technique of fabricating an ultra-shallow junction using monolayer doping (MLD). With reference toFIG. 1, an exemplary ultra-shallow junction fabrication technique100using MLD is illustrated where a monolayer of dopants112is assembled on the surface of a silicon structure when the substrate is exposed to a dopant-containing precursor in step110. While not shown, a native silicon oxide layer is generally first removed by hydrofluoric (HF) etching prior to the reaction of the substrate with the dopant-containing precursor. Exemplary dopants can include, but are not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, phosphorous, arsenic, antimony, and bismuth, to name a few. In step120, an oxide cap122comprising silicon dioxide (SiO2), silicon oxynitride (SiON) or another barrier material is deposited on the monolayer to prevent dopant loss during subsequent thermal treatments, e.g., from outgassing of the dopant during annealing. This oxide cap or layer122can be deposited by chemical vapor deposition, electron beam evaporation or another suitable deposition technique and then selectively etched. In step130, the structure undergoes thermal treatment to break down the dopant molecules resulting in a thermal diffusion of dopant atoms112into the substrate132to form an ultra-shallow junction. Exemplary thermal treatments include, but are not limited to, low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing. In step140, the oxide cap is removed by conventional methods such as HF etching.

FIGS. 2A and 2Bare diagrams of additional techniques of fabricating an ultra-shallow junction using monolayer doping according to some embodiments of the present disclosure. With reference toFIG. 2A, an exemplary ultra-shallow junction fabrication technique200using MLD is illustrated where a pre-amorphization implant (PAI) step210is performed on an epitaxial germanium layer202overlying a silicon substrate204. InFIG. 2B, the PAI step210is performed on the silicon substrate204. The PAI step can be performed using any desired dopant, dose and/or energy. Dose and energy can be selected according to requirements for the structure to be formed, in particular to the depth of the desired amorphous layer. Non-limiting examples of dopants that can be used for PAI are germanium, nitrogen, indium, arsenic, boron, carbon, xenon, antimony, and argon, to name a few. Further, the choice of dopants can be dependent upon the semiconductor material used for the respective substrate. Thus, an exemplary PAI step210can assist in the activation of subsequent introduced dopants due to the amorphous nature of the structure surface and its respective affinity for subsequent doping. For example, PAI can be used to form implantation regions which are amorphous silicon provided below a top surface of the respective structure. In the case depicted inFIG. 2A, an amorphous region203is formed in the epitaxial germanium layer202. In the case depicted inFIG. 2B, an amorphous region205is formed in the silicon substrate204. The depth of such an amorphization region or layer is dependent upon dose and energy as noted above and can be between 10-15 nm below the top surface of the structure. In some embodiments, the depth of such an amorphization region or layer should be deeper than the peak concentration of activated dopants to ensure that any activated dopants are covered inside the PAI region.

At step220, an exemplary MLD technique is used where a monolayer of dopants222is assembled on the surface of a respective structure when exposed to a dopant-containing precursor. Exemplary MLD techniques are applicable for both p- and n-doping of various nanostructured materials that are fabricated by either ‘bottom-up’ or ‘top-down’ approaches, making it highly versatile for various applications. An important characteristic of an MLD technique is that it employs self-limiting reactions to form a highly uniform monolayer on a crystalline germanium or silicon surface, resulting in a well-defined layer of chemically attached dopant-containing molecules with molecular accuracy. This is important for a well-controlled and uniform formation of the nanoscale doping profiles in subsequent thermal processes. The areal dopant dose can also be tuned by the molecular footprint of the respective precursor, with smaller molecules enabling a higher dose. The thermal process time and temperature can also be used to govern the precise nature of the junction depth. As a result, the combination of subsequent thermal process conditions and the molecular design of the precursor can provide a wide spectrum of doping profiles to meet the specific needs of the desired application or resulting structure. Exemplary dopants can include, but are not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, carbon, fluorine, phosphorous, arsenic, antimony, and bismuth, to name a few. In the case depicted inFIG. 2A, due to performance of the foregoing PAI step, a greater amount of dopant can be captured in the amorphous region203provided in the epitaxial germanium layer202in comparison to the method depicted inFIG. 1. In the case depicted inFIG. 2B, due to performance of the foregoing PAI step, a greater amount of dopant can be captured in the amorphous region205provided in the silicon substrate204in comparison to the method depicted inFIG. 1. While an MLD technique is depicted inFIGS. 2A and 2B, the claims appended herewith should not be so limited as any exemplary ion implantation step can be used in embodiments of the present disclosure. Further, the illustration of a single MLD step should not limit the scope of the claims appended herewith as multiple MLD processes or steps are envisioned to provide additional dopant implantations in exemplary structures. In step230, the respective structure then undergoes a thermal treatment to break down the dopant molecules resulting in a thermal diffusion of dopant atoms into the structure to form an ultra-shallow junction. Exemplary thermal treatments include, but are not limited to, low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing. During the thermal treatment step230, solid-phase epitaxial re-growth of the amorphous region can occur as illustrated.

FIG. 3is a diagram of an exemplary technique of fabricating an ultra-shallow junction according to some embodiments of the present disclosure. With reference toFIG. 3, an exemplary ultra-shallow junction fabrication technique300is illustrated where a PAI step310is performed on an epitaxial germanium layer302overlying a silicon substrate304to form an amorphous region303in the epitaxial germanium layer302. While an epitaxial germanium layer is illustrated, the PAI step310can be performed on any device or layer including a silicon substrate (not shown). The PAI step can be performed with a desired dopant, dose and/or energy. Dose and energy can be selected according to requirements for the structure to be formed, in particular to the depth thereof. Non-limiting examples of dopants that can be used for PAI are germanium, boron, carbon, nitrogen, indium, arsenic, xenon, antimony, and argon, to name a few. Further, the choice of dopants can be dependent upon the semiconductor material used for the respective substrate. An exemplary PAI step310can assist in the activation of subsequent introduced dopants. For example, PAI can be used to form implantation regions which are amorphous silicon provided below a top surface of the respective structure. The depth of such an amorphization is dependent upon dose and energy as noted above and can be between 10-15 nm below the top surface of the structure. In some embodiments, the depth of such an amorphization region or layer should be deeper than the peak concentration of activated dopants to ensure that any activated dopants are covered inside the PAI region.

At step320, an exemplary ion implantation technique is used to assemble a layer of dopant on the surface of the structure. In the depicted example, a nitrogen implantation step can be performed using an implantation energy of 6 KeV resulting in a nitrogen implantation layer321having a depth of approximately 125 Angstroms. These values are exemplary only and should not limit the scope of the claims appended herewith as any suitable implantation energy can be employed to achieve a desirable implantation depth for a respective dopant. In some embodiments, an exemplary MLD technique is used where a monolayer of dopants is assembled on the surface of a respective structure when exposed to a dopant-containing precursor. Exemplary dopants can include, but are not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, carbon, fluorine, phosphorous, arsenic, antimony, and bismuth, to name a few. In other embodiments, conventional ion implantation methods can be used in the place of MLD. At step330, a second ion implantation technique is used to assemble a second layer of dopant on the surface of the structure. In the depicted example, a phosphorous implantation step is performed using an energy of 2 KeV resulting in a phosphorous implantation layer331having a shallower depth than the nitrogen implantation layer321. Of course, this energy value is exemplary only and should not limit the scope of the claims appended herewith as any suitable implantation energy can be employed to achieve a desirable implantation depth for a respective dopant. It should be noted that due to performance of the foregoing PAI step310, a greater amount of dopants (whether multiple or single dopants) can be captured in the amorphous region303formed in the epitaxial germanium layer302. Generally, phosphorous diffuses in a germanium substrate. Thus, in some embodiments of the present disclosure, to suppress phosphorous diffusion in the structure a nitrogen co-implant can be introduced to achieve a high activation phosphorous source/drain extension (SDE) junction. Of course, other co-implants can be employed to suppress phosphorous diffusion, such as, but not limited to carbon co-implants, fluorine co-implants, and the like. In step340, the respective structure then undergoes thermal treatment to break down the dopant molecules resulting in a thermal diffusion of dopant atoms into the structure to form an ultra-shallow junction. Exemplary thermal treatments include, but are not limited to, low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing. During the thermal treatment step340, solid-phase epitaxial re-growth of the amorphous region can occur.

FIG. 4is a graphical illustration of co-implantation methods according to embodiments of the present disclosure. With reference toFIG. 4, four traces are provided representing the concentration of phosphorous versus depth for a germanium substrate having a carbon co-implant followed by a phosphorous implant410with a sheet resistance of 639 ohm/sq, a germanium substrate having a fluorine co-implant followed by a phosphorous implant420with a sheet resistance of 233 ohm/sq, a germanium substrate having a nitrogen co-implant followed by a phosphorous implant430with a sheet resistance of 341 ohm/sq, and phosphorous440with a sheet resistance of 209 ohm/sq. As illustrated inFIG. 4, phosphorous concentration of the carbon and fluorine co-implants are maintained over depth better than the phosphorous sheet, the nitrogen co-implant provides a superior maintenance of phosphorous concentration over depth in comparison to the carbon and fluorine co-implants.

Thus, with reference to the aforementioned figures, various embodiments of the present disclosure can provide a method of forming an ultra-shallow junction in a semiconductor substrate. The method can include forming an amorphous region in a semiconductor substrate by performing a PAI step, implanting a dopant in the amorphous region by performing an MLD step, and thermally treating the semiconductor substrate to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The dopant used for the PAI step can be, but is not limited to, germanium, boron, nitrogen, indium, arsenic, carbon, xenon, antimony, and argon. The implanted dopant used for the MLD step can be, but is not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, carbon, fluorine, phosphorous, arsenic, antimony, and bismuth. Exemplary thermal treatments include low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing step. In some embodiments of the present disclosure, the step of thermally treating is performed without any oxide cap overlying the implanted amorphous region.

Additional embodiments of the present disclosure provide a method of forming an ultra-shallow junction in a semiconductor substrate. The method can include forming an amorphous region in a semiconductor substrate by performing a PAI step, implanting a first dopant in the amorphous region by performing a first MLD step, implanting a second dopant in the amorphous region by performing a second MLD step, and thermally treating the semiconductor substrate to activate the implanted dopants in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The dopant used for the PAI step can be, but is not limited to, germanium, boron, carbon, nitrogen, indium, arsenic, xenon, antimony, and argon. The implanted dopant used for the first MLD step can be, but is not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, carbon, fluorine, phosphorous, arsenic, antimony, and bismuth. Exemplary thermal treatments include low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing step. In some embodiments, the second implanted dopant is phosphorous and the first implanted dopant is nitrogen, fluorine or carbon. In other embodiments of the present disclosure, the step of thermally treating is performed without any oxide cap overlying the implanted amorphous region.

Further embodiments of the present disclosure provide a method of providing an ultra-shallow junction having activated dopants in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate, implanting a first dopant in the amorphous region by performing an MLD step, and activating the first dopant where the activating comprises recrystallizing the amorphous region and is performed without any oxide cap overlying the implanted amorphous region. In some embodiments, the step of forming an amorphous region comprises performing a PAI step. The dopant used for the PAI step can be, but is not limited to, germanium, nitrogen, indium, arsenic, boron, carbon, xenon, antimony, and argon. The implanted first dopant can be, but is not limited to, boron, aluminum, gallium, indium, thallium, nitrogen, carbon, fluorine, phosphorous, arsenic, antimony, and bismuth. Exemplary thermal treatments include low temperature thermal annealing, rapid thermal annealing, spike annealing, flash annealing or laser annealing step. In other embodiments, the method includes the step of implanting a second dopant in the amorphous region by performing a second MLD step, the second dopant being shallower than the first dopant, where the step of activating further comprises activating the first and second dopants. In various embodiments, the second dopant is phosphorous and the first dopant can be nitrogen, fluorine or carbon.

It can be emphasized that the above-described embodiments, particularly any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications can be made to the above-described embodiments of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present disclosure and protected by the following claims.

As shown by the various configurations and embodiments illustrated inFIGS. 1-4, various methods for fabrication of ultra-shallow junctions have been described.