Implementing enhanced LBIST testing of paths including arrays

A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a method and circuit for implementing testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides.

DESCRIPTION OF THE RELATED ART

When testing integrated circuits, known techniques such as Array Built In Self Test (ABIST) and Logic Built in Self Test (LBIST) diagnostics are used to test memory arrays and logic.

It is very important to be able test the full latch-to-latch paths that are used in the chip function at the same frequency that will be used in the system application.

If the circuits are tested at a slower frequency or part of the functional path is bypassed then there could be AC defects that would not be caught by test but result in a failing chip when exercised in the system. This is a very expensive point to identify failing parts. Also at speed AC test of the full functional path can be used to perform sorting of chips into different frequency bins, which is very desirable to optimize yield of useable chips.

FIG. 1Aillustrates a prior art circuit path for implementing known Array Built In Self Test (ABIST) testing techniques with a latch-bounded array. Sometimes arrays are designed to be latch bounded. There are latches at all the address and data input pins and latches at the data output pins. The array typically has 1 clock cycle to perform a read access and have the data captured in the output latch. The data outputs would be launched out of the array on the subsequent cycle.

ABIST testing of the arrays is very straightforward when testing latch-bounded arrays. ABIST will test the entire path and if ABIST is run at system speed, AC defects will be caught.

FIGS. 1B and 1Cillustrate other circuit paths100,120with arrays102and logic104where the paths are not just a latch-bounded array as shown inFIG. 1A. In such circuit paths100,120, logic104may be placed after or in front of the array102as shown inFIGS. 1B and 1Cand testing the full latch-to-latch paths is more complex. For arrays that are not output latch bounded, typically observation latches, such as latches110,112are provided so that ABIST test is straightforward for partial AC paths as shown inFIGS. 1B and 1Cbut ABIST is not testing the full AC paths since the logic in front of the array or downstream logic is not tested along with the array path.

For LBIST, typically random patterns are scanned into banks of latches surrounding random logic and then the logic is functionally clocked and the capture latches are scanned out and the data is compressed and the results are compared with a signature to tell if there are any AC or DC defects. LBIST in this manner is a very well understood and inexpensive way to AC and DC test integrated circuits.

Known tools used for generating patterns and expects for paths that contain memory arrays mixed with logic currently require very long, onerous execution times when solving this type of problem since the tool must keep track of sequential changing of the memory arrays.

In a known level sensitive scan design (LSSD) test process, a pseudo-random pattern generator (PRPG) and a multiple input signature register (MISR) are provided with a test control module (TCM) used to operate in the LSSD scan mode. A prior art LSSD testing arrangement is STUMPS (Self-Test Using a MISR and a Parallel Shift register sequence generator). Fault simulation in LBIST is virtually intractable because of the need to retain the memory state across STUMPS loads.

A need exists to test the full AC latch-to-latch path that includes a memory array and logic.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method and circuit for implementing testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Other important aspects of the present invention are to provide such method and circuit substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a method and circuit for implementing testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

In accordance with features of the invention, the initialization pattern is deterministic and is based upon the logic included with the memory array in the circuit path. The deterministic initialization pattern is programmed into the memory, enabling an update with special patterns based on manufacturing or lab test results.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with features of the invention, a method is provided that tests a full AC latch-to-latch path that includes a memory array and logic. The method of the invention includes initializing the memory array into a deterministic pattern. Then when entering LBIST mode the memory array is forced into a read-only state. Then run LBIST as normal with the memory array treated as a Read Only Memory (ROM). The LBIST pattern generator and expect tool now does not have to keep track of sequential changing of the memory and the access of the memory exactly matches the read timing which will accurately catch AC defects. ROMs are handled easily by test pattern generation and fault simulation tools. In such tools, ROMs look like MUX trees with constant inputs.

FIGS. 1B, and1C illustrate respective circuit paths100,120to be tested using the method of the invention. Circuit path100includes a memory array102and downstream logic104shown inFIG. 1B. Circuit path120includes a memory array102and upstream logic104shown inFIG. 1C. Logic Built in Self Test (LBIST) diagnostics for the respective full AC path100,120are implemented with the requirement to include exact access time of memory array102in accordance with the preferred embodiment. Input latches110and output latches112are provided with the memory array102for implementing known testing techniques of Array Built In Self Test (ABIST) tests for a partial AC path. Circuit path100includes output latches114at the output of downstream logic104used with the array input latches110for LBIST testing the full AC latch-to-latch path100. Circuit path120includes input latches122at the input of upstream logic104used with the array output latches112for LBIST testing the full AC latch-to-latch path120.

Having reference now to the drawings, inFIG. 2, there is shown an exemplary computer test system for implementing testing of circuit paths including arrays including Logic Built in Self Test (LBIST) diagnostics generally designated by the reference character200in accordance with the preferred embodiment. Computer system200includes a main processor202or central processor unit (CPU)202coupled by a system bus206to a memory management unit (MMU)208and system memory including a dynamic random access memory (DRAM)210, a nonvolatile random access memory (NVRAM)212, and a flash memory214. A mass storage interface216coupled to the system bus206and MMU208connects a direct access storage device (DASD)218and a CD-ROM drive210to the main processor202. Computer system200includes a display interface222connected to a display224, and a test interface226coupled to the system bus206. An AC latch-to-latch path under test228including memory array and logic is coupled to the test interface226. The AC latch-to-latch path under test228includes, for example, a test path as illustrated inFIGS. 1B and 1C. Computer system200includes an operating system230, a test control program232, and a memory array initializing deterministic test pattern234of the preferred embodiment resident in a memory236.

Computer test system200is shown in simplified form sufficient for understanding the present invention. The illustrated computer test system200is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices, for example, multiple main processors.

Referring now toFIG. 3, an article of manufacture or a computer program product300of the invention is illustrated. The computer program product300includes a recording medium302, such as, a floppy disk, a high capacity read only memory in the form of an optically read compact disk or CD-ROM, a tape, or another similar computer program product. Recording medium302stores program means304,306,308,310on the medium302for carrying out the methods for implementing testing of circuit paths including arrays including Logic Built in Self Test (LBIST) diagnostics of the preferred embodiment in the system200ofFIG. 2.

A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means304,306,308,310, direct the computer system200for implementing testing of circuit paths including arrays including Logic Built in Self Test (LBIST) diagnostics of the preferred embodiment.

FIG. 4is a flow chart illustrating exemplary steps for implementing testing of circuit paths including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics in accordance with the preferred embodiment starting at a block400. First an initialization pattern of memory is provided as indicated at a block402. Test coverage of the logic in the circuit path is analyzed with the provided initialization pattern of memory as indicated at a block404. It is determined whether adequate test coverage of the logic is provided as indicated at a decision block406.

Depending upon the downstream logic, there could be a test coverage issue if the patterns driving the logic are too simple. A memory that contained blanket data, checkerboards and stripes of data could result in inadequate test coverage of the downstream logic. During LBIST random or pseudo-random data is needed on the array outputs to be able to adequately test the downstream logic.

If inadequate test coverage is identified at decision block406, then the initialization pattern is updated as indicated at a block408and the sequential steps are repeated. When adequate test coverage is identified at decision block406, then the final test data is provided as indicated at a block410. Sequential steps are completed as indicated at a block412.

FIG. 5is a diagram illustrating an exemplary initialization pattern generally designated by the reference character500for implementing testing of circuit paths including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics in accordance with the preferred embodiment. Initialization pattern500is deterministic and depends upon the logic in the circuit path under test. Initialization pattern500includes a plurality of entries 0-N, each entry including data 0-N. As shown, the initialization pattern500includes an entry 0of all data values of 0s, and an entry 1 of all data values of 1s, and entries 2-N including a combination of data values of 0s and 1s.

In accordance with features of the invention, the initialization pattern500illustrates one possible initialization pattern that is deterministic and depends upon the downstream logic of the memory array. For instance if there are many AND books in the logic then the entries would favor a high number of 1s to be able to sensitize the logic for fault detection. Since any deterministic initialization can be programmed into the memory, this allows for update of special patterns based on manufacturing or lab test results. This invention allows for loading different new data than standard ABIST pattern data where the new data is effective for unique downstream logic.

FIG. 6is a diagram illustrating an exemplary memory array system generally designated by the reference character600including a memory array602and exemplary gating logic604,606,608for implementing testing of circuit paths including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics in accordance with the preferred embodiment. The memory array system600includes gating logic604,606,608added to the memory array to force the memory into a Read-Only during LBIST. As shown, memory array system600includes an OR gate604receiving a pair of inputs of a Read enable606and an LBIST enable608. The output of the OR gate604is applied to a read enable input of memory array602with other inputs610applied to other inputs of memory array602. Memory array602includes data outs applied to data outs612for testing and other data outputs applied to data outputs614.

FIG. 7is a flow chart illustrating exemplary steps for implementing testing of circuit paths including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics in accordance with the preferred embodiment starting at a block700. First an initialization of memory, such as memory array602, is provided as indicated at a block702. Then testing switches to the LBIST mode as indicated at a block704. The memory602is forced to a read only, or ROM equivalent as indicated at a block706. Thus, the test model is created by replacing a read/write memory model with a read only memory model. Then LBIST diagnostics are run including AC and DC testing of the circuit path in accordance with the preferred embodiment as indicated at a block708.

In accordance with features of the invention, the LBIST testing includes scanning random patterns into the circuit path including the memory array and logic and then the logic is functionally clocked and the capture latches are scanned out and the data is compressed and the results are compared with a signature to tell if there are any AC or DC defects. With the memory array in the read only mode, an LBIST pattern generator and expect tool does not have to keep track of sequential changing of the memory and the access of the memory exactly matches the read timing which will accurately catch AC defects. Sequential steps are completed as indicated at a block710.

FIG. 8shows a block diagram of an example design flow800. Design flow800may vary depending on the type of IC being designed. For example, a design flow800for building an application specific IC (ASIC) may differ from a design flow800for designing a standard component. Design structure802is preferably an input to a design process804and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure802comprises circuits200,600in the form of schematics or HDL, a hardware-description language, for example, Verilog, VHDL, C, and the like. Design structure802may be contained on one or more machine readable medium. For example, design structure802may be a text file or a graphical representation of circuits200,600. Design process804preferably synthesizes, or translates, circuits200,600into a netlist806, where netlist806is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist806is resynthesized one or more times depending on design specifications and parameters for the circuits.

Design process804may include using a variety of inputs; for example, inputs from library elements808which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology, such as different technology nodes, 32 nm, 45 nm, 90 nm, and the like, design specifications810, characterization data812, verification data814, design rules816, and test data files818, which may include test patterns and other testing information. Design process804may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, and the like. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process804without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process804preferably translates an embodiment of the invention as shown inFIGS. 1B,1C,2, and6along with any additional integrated circuit design or data (if applicable), into a second design structure820. Design structure820resides on a storage medium in a data format used for the exchange of layout data of integrated circuits, for example, information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures. Design structure820may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown inFIGS. 1B,1C,2, and6. Design structure820may then proceed to a stage822where, for example, design structure820proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, and the like.