Method and system for insertion and extraction of overhead in SONET/SDH

An overhead insertion interface unit connected to a high-speed line via a frame processing unit includes a TOH FIFO, a POH FIFO, and a common gate for transmitting a TOH input request and a POH input request to an external device. Each of the FIFOs receives a TOHAV signal together with TOH data and POH data sequentially, and the frame processing unit performs insertion processing. Overhead extraction processing is performed by the reverse of the operations for insertion processing, using the frame processing unit and the overhead extraction interface unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a communication scheme and system equipped with an LSI device that provides an interface between a high-speed transmission line and a lower-speed device, and more particularly to a method and system for insertion and extraction of overhead in SONET/SDH (Synchronous Digital Hierarchy). The overhead is used on data transfer via a network as information for operation and administration of the network.

2. Description of the Prior Art

A conventional method and system for insertion and extraction of overhead in SONET or SDH have an LSI device in which every port has a frame-processing unit for interfacing to a high-speed line and an interface unit for interfacing to a lower-speed external device to perform insertion and extraction of the overhead present in a SONET/SDH frame; providing the LSI device with multiple ports has come to be an important issue. In particular, recent LSI devices have come to be highly functional, by performing numerous functions or having numerous channels, and communication capabilities are being implemented in a single IC.

Such an LSI device will now be described below; insertion and extraction of overhead will be described separately with reference toFIGS. 11 to 13andFIGS. 14 to 16, respectively.

First, as shown inFIG. 11, for the STS-12c system, for example, an interface system that performs insertion of overhead has a frame processing unit70for processing frames in SONET/SDH. The frame processing unit70interfaces to a high-speed line. The interface system also has an overhead insertion interface unit73that interfaces to a lower-speed external device. The SONET/SDH frame processing unit70has a transport overhead (TOH) processor71for inserting overhead into a frame transmitted to the line and a path overhead (POH) processor72; and the overhead insertion interface unit73has a TOH timing generator74that includes a function for generating timing for transmitting TOH data to the line, a function for generating timing for the external device to input TOH data, and a buffer function used in transmitting TOH data from the external device to the line; the overhead insertion interface unit73also has a POH timing generator75that generates timing for POH data in a way similar to the TOH timing generator74.

The basic STS-1 SONET frame structure, transport overhead (TOH), and path overhead (POH) have been disclosed in JP-A-101009/1993 (FIGS. 3, 4, and 6) and other documents. The STS-3c system is a combination of three STS-1 systems, and STS-12c represents a frame size of a combination (concatenation) of four STS-3c systems; a detailed description will be omitted herein. The concatenation is well known, being disclosed in JP-A-278235/2000 and other documents.

Next, the operations of the interface system will be described. As shown inFIG. 11, when an A1-byte request pulse (a pulse for requesting the A1 byte allocated in the first row of overhead) is input as a frame timing pulse for establishing synchronization of frames from the frame processing unit70to the TOH timing generator74in the overhead insertion interface unit73, the TOH timing generator outputs a TOH clock (TTOHCK) and a TOH framing pulse (TTOHFP) to the external device to request it to input 4-bit parallel TOH data (TTOH[3:0]), as shown inFIGS. 11 and 12. InFIG. 12, b1in the TOH data (TTOH[3:0]) represents the first bit of each byte from A1 to Z0 in the first row of TOH in the frame; representations of the second to eighth bits are omitted. Since a TOH clock (5.184 MHz) is a frequency for inputting the 36 TOH bytes over a whole one-row span of overhead, the external device outputs a TOH enable signal (TTOHEN), plus 4-bit parallel TOH data, to the TOH timing generator74in synchronization with the TOH clock. As a result, the TOH timing generator74outputs TOH data to the frame processing unit70, which inserts the TOH into the frame.

Similarly, as shown inFIG. 11, when a J1-byte request pulse, which is a pulse requesting the J1 byte that is a part of the path overhead (POH) and is allocated to the first byte of the payload, is input as a frame timing pulse from the frame processing unit70to the POH timing generator75in the overhead insertion interface unit73, the POH timing generator75outputs a POH clock (TPOHCK) and a POH framing pulse (TPOHFP) to the external device to request it to input POH data (TPOH), as shown inFIGS. 11 and 13. InFIG. 13, b1in the POH data represents the first bit of each byte from J1 to Z5 in the first column of POH in the frame; representations of the second to eighth bits are omitted. Since a POH clock (576 KHz) is a frequency for inputting the 1 POH byte over a whole one-byte span of overhead, the external device outputs the POH data in synchronization with the POH clock, together with a POH enable signal (TPOHEN), to the POH timing generator75. As a result, the POH timing generator75outputs the POH data to the frame processing part70, whereby the POH is inserted into the frame.

Next, as shown inFIG. 14, an interface system performing extraction of overhead is configured with circuits similar to those of the interface system shown inFIG. 11. More specifically, the interface system has a SONET/SDH frame processing part80that includes a transport overhead (TOH) processor81for interfacing to the high-speed line side to extract overhead from a frame received from the line and a path overhead (POH) processor82, and an overhead extraction interface unit83for interfacing to a lower-speed external device. The overhead extraction interface unit83has a TOH timing generator84that includes a function for generating timing for receiving TOH data input from a line, a function for generating timing for outputting TOH data to the external device, and a buffer function used in receiving TOH data output from the line to the external device; and a POH timing generator85that generates timing for POH data in a way similar to the TOH timing generator84.

Next, the operations of the interface unit will be described. As shown inFIG. 14, when an A1-byte pulse, which is a pulse requesting the A1 byte allocated to the first row of overhead, is input as a frame timing pulse for establishing synchronization of the frame from the SONET/SDH frame processing part80to the TOH timing generator84in the overhead extraction interface unit83, the TOH timing generator84outputs a TOH clock (RTOHCK) and a TOH framing pulse (RTOHFP) to the external device, and receives TOH data from the frame processing unit80, as shown inFIGS. 14 and 15. Since the TOH data is input and appears with fixed timing in every row, the TOH timing generator84receives it with the fixed timing in subsequent rows. In this example, two rows of TOH data can be stored and switched at every row. The TOH data is output as RTOH[3:0] from the TOH generator84to the external device. InFIG. 15, b1in RTOH data [3:0] also represents a first bit of each byte from A1 to Z0 in the first row of TOH in the frame; representations of the second to eighth bits are omitted. TOH clock (5.184 MHz) is a frequency for outputting the 36 TOH bytes over a whole one-row span of overhead, so the TOH timing generator84outputs 4-bit parallel TOH data to the external device in synchronization with the TOH clock.

As a result, TOH data is output from the frame processing unit80to the TOH timing generator84, whereby the overhead is extracted from the frame.

Similarly, as shown inFIG. 14, when a J1-byte pulse, which is a pulse requesting the J1 byte that is a part of the path overhead (POH) and is allocated to the first byte of the payload, is input as a frame timing pulse from the frame processing unit80to the POH timing generator85in the overhead extraction interface unit83, the POH timing generator85outputs a POH clock (RPOHCK) and a POH framing pulse (RPOHFP) to the external device, together with POH data (RPOH), as shown inFIGS. 14 and 16. InFIG. 16, b1in the POH data (RPOH) represents the first bit of each byte from J1 to Z5 in the first column of POH; representations of the second to eighth bits are omitted.

As a result, POH data is output from the frame processing unit80to the POH timing generator85, whereby the POH is extracted from the frame.

In the TOH clock and POH clock transmitted from the overhead insertion interface unit73and the overhead extraction interface unit83to the external device, a blank span (shown inFIGS. 1,2,13,15, and16) indicates an idle span. That is, request data or valid data is indicated only by the clock.

The aforementioned conventional SONET/SDH overhead insertion and extraction method and system place TOH overhead data (each byte) at a fixed location in a frame, thereby enabling periodic insertion and extraction of TOH. In contrast to TOH overhead data, however, POH overhead data (each byte) is not placed at a fixed location. This is because byte J1 in the POH, which indicates the location where the Synchronous Payload Envelope (SPE) begins, is dynamically designated by a pointer contained in the TOH. Therefore, a phase difference arises between overhead data in TOH and overhead data in POH, so the TOH and POH must be inserted into and extracted from a frame with different timing. Accordingly, the overhead insertion and extraction interface units must handle TOH and POH separately. That is, these interface units must be provided separately.

As described above, the conventional overhead insertion and extraction method and system must provide separate terminals for TOH and POH, so each port, including the ports of an interface system, must have more terminals, a drawback that prevents the number of ports per LSI device from being increased.

In addition, the conventional overhead insertion and extraction method and system perform processing of transport overhead and path overhead separately, thus present a drawback that it cannot adjust frequencies on the overhead transmitting side, or the insertion interface unit.

Furthermore, the conventional overhead insertion and extraction method and system must provide a number of POH interface units equal to the number of channels supported to realize multi-channel frame, increasing the number of terminals, raising the unwelcome problem of whether to increase the size of the LSI device to accommodate the plurality of ports or decrease the number of ports that can be accommodated in an LSI device.

BRIEF SUMMARY OF THE INVENTION

Objects of the Invention

The major object of the present invention is to provide a SONET/SDH overhead insertion and extraction method and system that can reduce the number of terminals per port of the LSI device used, and accordingly can provide more ports.

Another object of the present invention is to provide a SONET/SDH overhead insertion and extraction method and system that can adjust frequencies of the overhead transmitting side interface unit.

Another object of the present invention is to provide a SONET/SDH overhead insertion and extraction method and system that can also reduce the number of terminals of POH interface of each channel in a multi-channel frame and achieve small size and multiple ports of LSI devices.

SUMMARY OF THE INVENTION

According to the invented SONET/SDH overhead insertion and extraction method and system, in the TC sublayer (transmission convergence sublayer) that forms a SONET/SDH-based physical layer and adjusts speed of cells, in other words, in the LSI device that interfaces between a high-speed transmission line and a lower-speed external device, insertion and extraction of transport overhead (TOH) and path overhead (POH) in a SONET/SDH frame transmitted to and from the external device is performed by sharing an interface to the external device, thereby reducing the number of the terminals and making it easier to increase the number of ports. In short, the present invention can limit the increase in the number of terminals when increasing the number of ports of the LSI device.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment of the present invention will now be described with reference to the attached drawings. The present invention will be briefly described with reference toFIG. 1; a frame structure will be described with reference toFIG. 2; a first embodiment will be described with reference toFIGS. 3 to 6; and a second embodiment will be described with reference toFIGS. 7 to 10.

FIG. 1is a block diagram of a switching system for briefly describing the present invention. As shown inFIG. 1, the switching system is connected to an ATM device via high-speed transmission lines such as 622-Mbps optical fiber cables, and includes an LSI device1that interfaces to a lower-speed external device and an ATM device4that performs ATM processing via a plurality of ports2A to2C provided in the LSI device1, one port per line, to transmit and receive data to and from personal computers and other terminals. The LSI device1has an interface unit (IF)3in each port that interfaces between the line side and an external device side, and provides functions of inserting overhead information to SONET/SDH frames transmitted to the line and extracting overhead information from SONET/SDH frames received from the line. The external devices include devices with lower-speed processing capabilities unlike the LSI device1, while the LSI device1requires at least as many terminals as there are ports. The interface unit (IF)3provided in the LSI device1makes it possible to interface between the high-speed line side and lower-speed external device and input and output data in accordance with the timing of both.

FIG. 2is a diagram of the structure of a data frame transmitted by the system shown inFIG. 1. As shown inFIG. 2, the format of the data frame transmitted to the line is that of an STS-12c transmitting frame10, but it can also apply to STS-12c receiving frames, and STS-1, STS-3c, and other frames.

The frame10is mainly composed of a transport overhead (TOH)11, a path overhead (POH)14, and a Synchronous Payload Envelope (SPE)15; the TOH11includes section overhead (SOH)12and line overhead (LOH)13; and a pointer is placed on the first line of the LOH13. The STS-12c frame10is composed of 1080 bytes wide by 9 rows as a whole, and transmission and reception of the frame are performed from the most significant bit (MSB) of A1 byte in the first row, in the row direction, and repeated times the number of rows, or nine times (622 Mbps).

The TOH11is composed of overhead indicating information of the frame10, and is depicted as a rectangle of 9 rows, each 36 bytes. A pointer placed on the first row of the LOH13in the TOH11points to the location of the POH14(the location of the first J1 byte), thereby enabling multiplexing of the SPE15.

The SPE15is composed of 1043 bytes by 9 rows of payload data, into which ATM cells or POS packets are packed. An ATM cell is 53 bytes long (fixed length), so a maximum of 170-cells of information can be packed in the SPE15. The POH14is composed of overhead indicating payload information of the SPE15, and contains one byte in a row, thus 9 bytes in total.

The basic structures of the transport overhead (TOH)11and the path overhead (POH)14in the STS-12c system are the same as those of the TOH and POH shown inFIGS. 4 and 6in the document (JP-A-101009/1993) concerning an STS-1 system that has been described in relation to the prior art (FIG. 11).

The interface unit (IF)3shown inFIG. 1extracts the TOH11and POH14to the external device on reception of a frame with said structure, and inserts these overheads from the external device for transmitting the frame. Therefore, the POH14requires an interface performing insertion and extraction of 36 bytes per row for the TOH11and 9 bytes per frame.

FIG. 3is a block diagram of an interface unit for mainly describing insertion of overhead of a frame according to the first embodiment of the present invention. As shown inFIG. 3, an interface unit (IF)3A of the first embodiment has a frame processing unit20that performs frame processing to insert overhead into a high-speed line; an overhead insertion interface unit23that requests overhead data for inserting overhead to a lower-speed external device; a frame processing unit30for extracting overhead to a frame from the high-speed line; and an overhead extraction interface unit33that requests overhead data for extracting overhead to the lower-speed external device. The extraction of overhead will be described later with reference toFIG. 5, so the insertion of overhead will now be described.

The overhead insertion interface unit23in the interface system3A includes a basic timing generator24that generates basic timing in response to an A1-byte request pulse as a frame timing pulse; a TOH input request generator25that generates and outputs a TOH framing pulse (TTOHFP) to the external device in response to a timing signal output from the basic timing generator24; a POH input request generator27that generates an input request to the external device in response to a timing output from the basic timing generator24; a POH framing pulse generator29that generates a POH framing pulse (TPOHFP) to the external device in response to a J1-byte request pulse as a frame timing pulse and a timing signal output from the basic timing generator24; an OR gate (OR1) that outputs an overhead request signal (TOHREQ) to the external device in response to a request output of either the TOH input request generator25or the POH input request generator27; TOHFIFO26that receives an overhead valid signal (TOHAV) and overhead data (TOHD[1:0]) sequentially from the external device in response to a TOH request signal from the frame processing unit20and a TOH request from the TOH input request generator25, and transfers the TOH valid signal and the TOH data to the frame processing unit20; and POHFIFO28that receives an overhead valid signal (TOHAV) and overhead data (TOHD [1:0]) sequentially from the external device in response to a POH request signal from the frame processing unit20and a POH request from the POH input request generator27, and transfers the POH valid signal and the POH data to the frame processing unit20. In short, the overhead insertion interface unit23provides a common insertion control terminal and a common insertion data terminal for transferring TOH and POH insertion control signals and insertion data to and from the external device.

The overhead insertion interface unit23transmits an internal operating clock (CLK) 19.44 MHz that is generated by dividing the line transmission rate 622 MHz by a factor of 32 as an overhead clock (TOHCK) to the external device.

As described above, this embodiment transmits a TOH input request and a POH input request signal to the external device via OR1, thereby enabling sharing of the overhead request signal terminal, and provides TOHFIFO26and POHFIFO28, thereby sharing the overhead valid signal (TOHAV) terminal and the overhead data (TOHD [1:0]) terminal from the external device.

FIG. 4is a timing diagram of various signals and data for describing overhead insertion operations in the system shown inFIG. 3. As shown inFIG. 4, one STS12c frame is transmitted every 125 μs (=1080 bytes×8 bits×9 rows/622 MHz). As stated above, assuming that the internal operating clock (TOHCK) is 19.44 MHz, one row of the frame has to be processed in 270 clocks (=19.44 MHz×125 μs/9 rows).

Since the overhead inserted into one frame includes 36 TOH bytes and 0 to 2 POH bytes per row, the overhead is input from the external device at a 2-bit terminal. This makes the input timing last 152 clocks at the maximum (144 clocks for TOH +0 to 8 clocks for POH), which is within the number of processing clocks per row (270 clocks). The duration of the remaining 118 clocks is an idle span.

Overhead insertion operations will now be described more specifically with reference toFIGS. 3 and 4. First, a TOH request begins in response to an A1 byte pulse used as a frame timing pulse requesting the first byte of the frame, and subsequently, TOH is requested with fixed timing in a row. Therefore, the basic timing generator24generates basic timing by receiving the A1-byte frame timing pulse.

When the basic timing comes to be generated with fixed timing, the TOH input request generator25outputs an overhead (OH) request signal (TOHREQ) to the external device via the OR1gate over a 144-clock span (36 bytes×8 bits/2), and simultaneously outputs an OH request signal (TOHREQ) as a data input signal to TOHFIFO26. The TOHFIFO26writes the OH data (TOHD[1:0]) that has been input over an OH valid signal (TOHAV) span therein. If a basic timing is the input timing of A1 byte that is the first byte of the frame, the TOH input request generator25outputs a TOH framing pulse (TTOHFP). After that, when a TOH request signal is input to TOHFIFO26from the frame processing unit20, TOHFIFO26sequentially outputs the written OH data as TOH data to the frame processing unit20. The input from the external device and output to the frame processing unit20are completed within a row.

The TOH is requested with fixed timing in a row, whereas the timing for requesting POH is not fixed. This is because, as described with reference toFIG. 2, the POH J1 byte that indicates the start of the SPE15is designated by the pointer contained in TOH11, and does not lie in a fixed location. This means that there is a phase difference between TOH11and POH14. Therefore, the frame processing unit20inputs a pulse for requesting J1 byte of POH14to the POH framing pulse generator29, from which a POH framing pulse (TPOHFP) is output to the external device, thereby absorbing the phase difference.

Although a POH request generated by the POH input request generator27to the external device via the OR1gate is typically one byte long, when frequency is adjusted, it becomes zero to one byte long (on positive frequency justification) and one to two bytes long (on negative frequency justification). Therefore, in order for the POH data in POHFIFO28to be constantly two bytes (the maximum number of POH requests), the POH input request generator27reads the number of pieces of data in the FIFO from POHFIFO28and requests the external device to input the required number of POH bytes via the OR1gate. This enables frequency justification. As a result, POHFIFO28outputs POH data after frequency justification to the frame processing unit20, as in the case with TOHFIFO26.

FIG. 5is a block diagram of an interface system for mainly describing extraction of frame overhead according to the first embodiment of the present invention. As shown inFIG. 5, an interface system3A of this embodiment has, in addition to the frame processing unit20and the overhead insertion interface unit23that have been described with reference toFIG. 3, a frame processing unit30including a TOH processor31that performs frame processing for extracting overhead of a frame from a high-speed line and a POH processor32; and an overhead extraction interface unit33that outputs extracted overhead data to a lower-speed external device.

The overhead extraction interface unit33in the interface system3A includes a basic timing generator34that generates basic timing in response to an A1-byte pulse used as a frame timing pulse; a TOH output timing generator35that generates and outputs a TOH framing pulse (RTOHFP) to the external device in response to a timing signal output from the basic timing generator34; a POH output timing generator37that generates output timing in response to a timing signal output from the basic timing generator34; TOHFIFO36that writes TOH data received from the frame processing unit30in response to a timing signal output of the TOH output timing generator35; POHFIFO38that receives POH data in response to a timing signal output from the POH output timing generator37and a J1-byte pulse used as a frame timing pulse and outputs a POH framing pulse (RPOHFP); and two OR gates (OR2and OR3) that output a overhead valid signal (ROHAV) and overhead data (ROHD[1:0]) to the external device in response to the output of TOHFIFO36and POHFIFO38. In short, for extracting overhead, the overhead extraction interface unit33provides a common extraction control terminal and a common extraction data terminal for transferring TOH and POH extraction control signals and extraction data to and from the external device.

The overhead extraction interface unit33transmits an internal operating clock (CLK) 19.44 MHz that is generated by dividing the line transmission rate 622 MHz by a factor of 32 as an overhead clock (TOHCK) to the external device.

As described above, this embodiment transmits overhead valid signals and TOH and POH data to the external device via OR2and OR3, thereby enabling sharing of the overhead valid signal (ROHAV) terminal and the overhead data (ROHD[1:0]) terminal.

FIG. 6is a timing diagram of various signals and data for describing overhead extraction operations in the system shown inFIG. 5. As shown inFIG. 6, an STS12c frame is transmitted at a rate of 125 μs, as in the insertion operations. As described above, assuming that the internal operating clock (TOHCK) is 19.44 MHz, one STS12c frame has to be processed in 270 clocks.

Since the overhead extracted from one frame includes 36 TOH bytes and 0 to 2 POH bytes per row, so the overhead is output from a 2-bit terminal to the external device. This makes the output timing last 152 clocks at the maximum, which is within the number of processing clocks per row (270 clocks). The duration of the remaining 118 clocks is an idle (blank) span.

Next, overhead extraction operations will be described more specifically with reference toFIGS. 5 and 6. First, the frame processing unit30inputs the frame timing pulse (A1-byte pulse) indicating the first byte of the frame, plus TOH data. The 36 bytes of the input TOH data are written into TOHFIFO36sequentially. At the same time, the basic timing generator34receives the frame timing pulse (A1-byte pulse) to generate basic timing.

Similarly, POH data input from the frame processing unit30is written into POHFIFO38sequentially. TOH data is input with fixed timing in a row, whereas POH data is input with unfixed timing. This is because, as described with reference toFIG. 2, J1 byte of the POH14that indicates the first byte of SPE15is designated by a pointer contained in the TOH11, thus is not located in a fixed location. This means that there is a phase difference between TOH and POH. Therefore, writing the J1 byte pulse of the POH14into POHFIFO38and reading out the J1 byte pulse and the POH data and outputting them together to the external device make it possible to indicate that the input POH data is the J1 byte without requiring special recognition thereof, enabling the phase difference to be absorbed.

Although normally one byte of POH data is input, if frequency is adjusted, zero to one byte (on positive frequency justification) or one to two bytes of the POH data (on negative frequency justification) are input.

After the TOH data is input, when basic timing generated by the basic timing generator34becomes fixed timing, the TOH output timing generator35outputs an output timing signal over a 144-clock span (36 bytes×8 bits/2) to OHFIFO36. This causes an OH valid signal (ROHAV) and OH data (ROHD[1:0]) to be read from TOHFIFO36and output to the external device via the OR gates OR2and OR3. If basic timing output from the basic timing generator34is output timing of A1 byte that is the first byte of the frame, the TOH output timing generator35outputs a TOH framing pulse (RTOHFP) to the external device.

Furthermore, although the reading out of POH data, or POH extraction, is also performed with basic timing generated by the basic timing generator34, the number of bytes (either of 0, 1, or 2 bytes) of POH data written in POHFIFO38is not obvious because the frequency is adjusted. Therefore, the POH output timing generator37outputs a 2-byte output timing signal to POHFIFO38, and, if a data valid signal (ROHAV) is active (POH is available), it continues to output the output timing signal to output a data valid signal (ROHAV) and a POH framing pulse (ROHFP) to the external device. If the data valid signal (ROHAV) is not active (POH is unavailable), the POH output timing generator37stops outputting the output timing signal and cancels output to the external device. This enables frequency justification.

As a result, overhead read from TOHFIFO36and POHFIFO38can be output as OH data (ROHD[1:0]) to the external device. Input from the frame processing unit30and output to the external device are completed within one row.

The first embodiment described above has the advantage that although providing TOHFIFO and OR gates to share TOH and POH hardware adds an OH request signal terminal for adjusting the frequency in the overhead insertion interface unit, the POH clock terminal and POH data terminal can be eliminated in the overhead insertion interface unit and also in the overhead extraction interface unit.

FIG. 7is a block diagram of an interface system for mainly describing insertion of multi-channel frame overhead according to a second embodiment of the present invention As shown inFIG. 7, an interface system3B is an example of an interface that performs insertion of multi-channel overhead, which has a frame processing unit40that includes a TOH processor41for processing a frame to insert overhead for a high-speed line and a plurality of POH processors (#1to #12)42; an overhead insertion interface unit43that requests overhead data for insertion of the overhead for a lower-speed external device; a frame processing unit60that performs processing of a frame from the high-speed line to extract overhead; and an overhead extraction interface unit63that requests overhead data for extracting overhead to the lower-speed external device. A description of overhead extraction will be given later with reference toFIG. 9, so overhead insertion will now be described.

The overhead insertion interface unit43in the interface system3B includes a basic timing generator44that generates basic timing in response to an A1-byte request pulse used as a frame timing pulse; a TOH input request generator45that generates and outputs a TOH framing pulse to the external device with timing output from the basic timing generator44; a POH input request generator47that generates an input request to the external device with timing output from the basic timing generator44; a POH framing pulse generator51that generates a POH framing pulse for the external device in response to a J1 (#1to #12) byte request pulse as a frame timing pulse and with timing output from the basic timing generator44; an OR gate (OR4) that outputs an overhead request signal (TOHREQ) for the external device in response to an request output from either the TOH input request generator45or the POH input request generator47; TOHFIFO46that sequentially receives an overhead valid signal (TOHAV) and overhead data (TOHD[1:0]) from the external device in response to a TOH request signal from the frame processing unit40and a TOH request from the TOH input request generator45, and transfers the TOH valid signal and TOH data to the frame processing unit40; and a plurality of POHFIFOs48to50that sequentially receive overhead valid signals (TOHAVs) and overhead data (TOHD[1:0]) from the external device in response to TOH request signals (#1to #12) from the frame processing unit40and a POH request from the POH input request generator47, and transfer the POH valid signals (#1to #12) and POH data (#1to #12) to the POH processing unit (#1to #12)42of the frame processing unit40, respectively.

The overhead insertion interface unit43transmits an internal operating clock (CLK) 19.44 MHz generated by dividing the line transmission rate 622 MHz by a factor of 32 as an overhead clock (TOHCK) for the external device.

As described above, this embodiment provides the overhead insertion interface unit43that provides the same basic operations as those of the overhead insertion interface23shown inFIG. 3. More specifically, this embodiment transmits a TOH input request and a POH input request signal to the external device via OR4, thereby enabling sharing of the overhead request signal terminal, and more, provides TOHFIFO46and a plurality of POHFIFOs48to50to share the overhead valid signal terminal (TOHAV) and the overhead data terminal (TOHD[1:0]).

The insertion of multi-channel overhead differs from that by the overhead insertion interface23shown inFIG. 3in that the processing of the POH of an STS-1 frame allocated by a time slot is performed only when the POH is inserted.

FIG. 8is a timing diagram of various signals and data for describing multi-channel overhead insertion operations in the system shown inFIG. 7. As shown inFIG. 8, STS12c multi-channel processing is capable of multiplexing a maximum of 12 STS-1 frame Synchronous Payload Envelopes (SPEs) (corresponding to the SPE15shown inFIG. 2). More specifically, POH is a sequence of maximum 12 bytes per row of the frame, and if frequency justification is taken into account, POH becomes zero to 24 bytes. Therefore, this embodiment divides 96 clocks after output of the POH into time slots #1to #12of 8 clocks each, and allocates POH insertion processing of multiplexed STS-1 SPE to each time slot, thereby enabling insertion of overhead in a multi-channel system. Positive and negative frequency justification in the overhead insertion interface unit43is performed by increasing and decreasing the number of bytes of a POH request signal in a way similar to the justification described with reference toFIG. 4.

FIG. 9is a block diagram of an interface system for mainly describing multi-channel overhead extraction according to the second embodiment of the present invention. As shown inFIG. 9, an interface system3B according to this embodiment has the frame processing unit40and the overhead insertion interface43described with reference toFIG. 7, plus a frame processing unit60that includes a TOH processor61that performs frame processing for extracting overhead for a frame from a high-speed line and a plurality of POH processors (#1to #12)62; and an overhead extraction interface unit63that requests overhead data for extracting overhead to a lower-speed external device.

The overhead extraction interface unit63in the interface system3B has a basic timing generator64that generates basic timing in response to an A1-byte pulse used as a frame timing pulse; a TOH output timing generator65that generates and outputs a TOH framing pulse (PTOHFP) to the external device with timing output from the basic timing generator64; a POH output timing generator67that generates output timing with timing output from the basic timing generator64; TOHFIFO66that writes TOH data received from the frame processing unit60with timing output from the TOH output timing generator65; a plurality of POHFIFOs68to70that receive POH data (#1to #12) with timing output from the POH output timing generator67and in response to the J1 (#1to #12) byte pulses used as frame timing pulses and output POH framing pulses (RPOHFP); and three OR gates (OR5to OR7) that output overhead valid signals (ROHAVS) and overhead data (ROHD[1:0]) in response to output of TOHFIFO66and POHFIFOs68to70and POH framing pulses (RPOHFPs) in response to the output of POHFIFOs68to70to the external device.

The overhead extraction interface63transmits an internal operating clock (CLK) 19.44 MHz by dividing the line transmission rate 622 MHz by a factor of 32 as an overhead clock (ROHCK) to the external device.

As described above, this embodiment also transmits an overhead valid signal and TOH and POH data to the external device via the OR gates OR5to OR7, thereby enabling sharing of an overhead valid terminal (ROHAV), an overhead data terminal (ROHD[1:0]), and a POH framing pulse terminal (RPOHFP).

The extraction of multi-channel overhead differs from that by the overhead extraction interface unit33shown inFIG. 5in that processing of POH of an STS-1 frame allocated by the time slot is performed only when the POH is extracted.

FIG. 10is a timing diagram of various signals and data for describing extraction of multi-channel overhead in the system shown inFIG. 9. As shown inFIG. 10, multi-channel processing with an STS-1 frame enables multiplexing of a maximum of 12 STS-1 Synchronous Payload Envelopes (SPEs) (corresponding to SPE15shown inFIG. 2). More specifically, POH is a sequence of 12 bytes per row of the frame, and if frequency justification is taken into account, POH becomes zero to 24 bytes. Therefore, this embodiment divides 96 clocks after output of POH into time slots #1to #12of 8 clocks, and allocates POH insertion processing of multiplexed STS-1 SPE to each time slot, thereby enabling insertion of overhead in a multi-channel system. Positive and negative frequency justification in the overhead extraction interface unit63is performed by increasing and decreasing the number of bytes of a POH request signal in a way similar to the justification described with reference toFIG. 5.

The second embodiment described above, needless to say, requires a number of POH interfaces equal to the number of channels supported, but in addition to the advantage of the first embodiment, it has an advantage of being capable of sharing a POH interface terminal of each channel of multi-channel frames.

As described above, the SONET/SDH overhead insertion and extraction method and system of the present invention provide TOHFIFO, POHFIFO, and OR gates in the overhead insertion and extraction interface units to share TOH and POH hardware, thereby making it possible to eliminate the POH clock terminal and POH data terminal from the overhead insertion and extraction interface units, providing an effect of enabling the number of terminals per port of the LSI device to be reduced and the number of ports to be increased. In short, the present invention provides FIFO buffers for absorbing phase differences in each of the interface units, thereby enabling TOH and POH processing to be performed with the same basic timing, whereby hardware can be shared.

In addition, the present invention includes TOHFIFOs in the overhead insertion and extraction interface units, thereby providing an effect of absorbing phase differences between TOH and POH and enabling frequency justification of the overhead insertion interface unit.

Moreover, the present invention provides an effect of enabling the number of POH interface terminals per channel also to be reduced for multi-channel frames, so that the size of the LSI device can be reduced, or the number of ports increased.