Digital AV signal processing apparatus

A digital AV signal processing apparatus includes a buffer for storing digital data input to the digital AV signal processing apparatus, and outputting the digital data as output digital data, a D/A converter for converting the output digital data to analog data, a voltage-controlled oscillator for generating a clock signal to control a conversion rate of the D/A converter, and a voltage-controlled oscillator controller for detecting a data amount of the digital data stored in the buffer, and controlling a frequency of the clock signal based on a deviation in the detected data amount from a first predetermined value and a time integral of the deviation value.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital AV signal processing apparatus. More particularly, the present invention relates to a digital AV signal processing apparatus capable of controlling a rate of digital-to-analog (hereinafter referred to as D/A) conversion of digital data stored in a buffer.

2. Description of the Related Art

Recently, as computer networks have become widespread, digital audio and video (hereinafter referred to as AV) signals representing AV content are increasingly distributed via computer networks, and the digital AV signals are received by receiver apparatuses while the signals are reproduced (by D/A conversion). Such a form of audience of AV content is becoming popular.

In computer networks, a data transmission rate may fluctuate, causing short-cycle fluctuations (e.g., jitter) in transmitted data. Further, clocks are not synchronized with each other between transmitter apparatuses (e.g., a server and a personal computer) and receiver apparatuses (e.g., a digital AV signal processing apparatus), so that differences in clock between transmitter apparatuses and receiver apparatuses are present.

When typical data to be processed by computers are transmitted, such a jitter or a clock difference does not cause a problem. However, when a digital AV signal is transmitted, a jitter or a clock difference does cause problems. A jitter or a clock difference leads to uncomfortable disruptions in audio or video signals (e.g., sound skip).

Therefore, a D/A conversion rate of digital data stored in a buffer needs to be controlled in order to eliminate uncomfortable disruptions in audio or video signals. To this end, techniques for controlling the D/A conversion rate of digital data stored in a buffer have been developed.

FIG. 12is a diagram showing a configuration of a conventional digital AV signal processing apparatus300. The digital AV signal processing apparatus300includes a buffer31, a D/A converter32, a voltage-controlled oscillator (hereinafter referred to as “VCO”)33, and a voltage-controlled oscillator controller (hereinafter referred to as “VCO controller”)34.

The buffer31stores digital data which has been input via a transmission system (e.g., a computer network) into the digital AV signal processing apparatus300, and outputs the digital data as output digital data. The D/A converter32converts the output digital data to analog data. A conversion rate of the D/A converter32is determined by a clock signal generated by the VCO33.

When the conversion rate of the D/A converter32is greater than an input rate of digital data input to the buffer31, a data amount of the buffer31decreases. When the conversion rate of the D/A converter32is smaller than the input rate of digital data input to the buffer31, the data amount of the buffer31increases.

The VCO controller34detects the data amount of the buffer31, and controls the frequency of a clock signal generated by the VCO33in such a manner as to cause the conversion rate of the D/A converter32to be an appropriate value.

The VCO33receives output data DA3output from the VCO controller34. The greater the value of the output data DA3output from the VCO controller34, the greater the frequency of a clock signal which is controlled by the VCO33. The smaller the value of the output data DA3output from the adder36, the smaller the frequency of a clock signal which is controlled by the VCO33.

The VCO controller34includes a comparator35, an adder36, a reference data amount memory37, and a reference voltage memory38.

The reference data amount memory37stores the amount BHLF of data corresponding to a half of the total capacity of the buffer31. The reference voltage memory38outputs output data DA2which is used to generate a reference clock frequency. The adder36adds the value of output data DA1with the value of the output data DA2to output output data DA3.

FIG. 13is a graph showing an operating characteristic of the comparator35. The horizontal axis represents the amount BDAT of data in the buffer31, while the vertical axis represents the output data DA1output from the comparator35. BMAX represents the amount of data corresponding to the total capacity of the buffer31, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer31.

As the data amount BDAT increases, the value of the output data DA1output from the comparator35increases. As the value of the output data DA1increases, the value of the output data DA3increases. In this case, the frequency of a clock signal generated by the VCO33is raised so as to suppress the increase in the data amount BDAT. Conversely, as the data amount BDAT decreases, the value of the output data DA1output from the comparator35decreases. As the value of the output data DA1decreases, the value of the output data DA3decreases. In this case, the frequency of a clock signal generated by the VCO33is reduced so as to suppress the decrease in the data amount BDAT.

With the above-described operations, the D/A conversion rate of digital data stored in a buffer is controlled.

FIG. 14is a graph showing a change with time in an input rate of digital data input to the digital AV signal processing apparatus300. The horizontal axis represents time. The vertical axis represents the input rate of digital data. Short-cycle fluctuations (jitter) in the input rate occur during time periods t1to t2, t4to t5, and t7to t8. During time period t3to t6, a long-cycle fluctuation occurs due to the unstable clock frequency of a server or a personal computer.

FIG. 15is a graph showing the data amount of the buffer31in the case where digital data is input to the digital AV signal processing apparatus300at the input rate shown inFIG. 14. The horizontal axis represents time, while the vertical axis represents the data amount BDAT of the buffer31. Times t1, t2, t3, t4, t5, t6, t7and t8correspond to times t1, t2, t3, t4, t5, t6, t7and t8ofFIG. 14.

FIG. 16is a graph showing a frequency of a reproduced clock signal generated by the VCO33in the case where digital data is input to the digital AV signal processing apparatus300at the input rate shown inFIG. 14. The horizontal axis represents time, while the vertical axis represents a frequency of a reproduced clock signal generated by the VCO33. Times t1, t2, t3, t4, t5, t6, t7and t8respectively correspond to times t1, t2, t3, t4, t5, t6, t7and t8ofFIG. 14.

Short-cycle fluctuations in the input rate shown inFIG. 14(see times t1to t2, t4to t5, and t7to t8inFIG. 14), do not have much influence on the frequency of a reproduced clock signal. In other words, fluctuations (pitch fluctuations) in the frequency of a reproduced clock signal shown inFIG. 16are suppressed (see times t1to t2, t4to t5, and t7to t8inFIG. 16), whereby the quality of reproduced sound is improved.

In the conventional digital AV signal processing apparatus300, however, the frequency of a clock signal is controlled based on a deviation in the data amount of digital data stored in the buffer31from a predetermined value (e.g., BHLF, i.e., half the capacity of the buffer31), whereby even when the data amount BDAT of the digital data stored in the buffer31remains constant while being deviated from the predetermined value (time t3to t6inFIG. 15), the frequency of a clock signal also remains constant (time t3to t6inFIG. 16). Therefore, when the input rate of digital data has long-cycle fluctuations, the data amount of digital data stored in the buffer31may remain deviated from the predetermined value. In this situation, overflow or underflow is likely to occur in the buffer.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a digital AV signal processing apparatus includes: a buffer for storing digital data input to the digital AV signal processing apparatus, and outputting the digital data as output digital data; a D/A converter for converting the output digital data to analog data; a voltage-controlled oscillator for generating a clock signal to control a conversion rate of the D/A converter; and a voltage-controlled oscillator controller for detecting a data amount of the digital data stored in the buffer, and controlling a frequency of the clock signal based on a deviation in the detected data amount from a first predetermined value and a time integral of the deviation value.

In one embodiment of this invention, the voltage-controlled oscillator controller may control the frequency of the clock signal in such a manner that a ratio of the amount of a change in the frequency of the clock signal with respect to the amount of a change in the deviation in the data amount of the buffer when the deviation exceeds a predetermined range, is set to be greater than when the deviation is below the predetermined range.

In one embodiment of this invention, the buffer may be a ring buffer. The digital data input may be input to the ring buffer from a writing position of the ring buffer. The ring buffer may output the digital data to a reading position of the ring buffer. The voltage-controlled oscillator controller may calculate the data amount of the digital data stored in the ring buffer based on the reading position and the writing position. The voltage-controlled oscillator controller may change at least one of the reading position and the writing position when the data amount exceeds a predetermined second value greater than the first predetermined value or when the data amount is below a third value less than the first predetermined value.

In one embodiment of this invention, the voltage-controlled oscillator controller may change at least one of the reading position and the writing position in such a manner that the data amount is substantially a half of a capacity of the ring buffer.

In one embodiment of this invention, the digital data may be input to the digital AV signal processing apparatus in the form of a plurality of packets, and the voltage-controlled oscillator controller may detect the data amount of the buffer in synchronization with a timing of the input of the plurality of packets.

In one embodiment of this invention, the digital data may be input to the digital AV signal processing apparatus in a form of a plurality of packet groups, each of the plurality of packet groups including a predetermined number of first packets having a first data amount and a predetermined number of second packets having a second data amount arranged in a predetermined sequence. The voltage-controlled oscillator controller may detect the data amount of the buffer in synchronization with a timing of the input of the plurality of packet groups.

Thus, the invention described herein makes possible the advantages of providing a digital AV signal processing apparatus capable of controlling a D/A conversion rate of digital data stored in a buffer in order to eliminate a deviation in the data amount of the buffer due to long-cycle fluctuations in an input rate of digital data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a diagram showing a configuration of a digital AV signal processing apparatus100according to an embodiment of the present invention. The digital AV signal processing apparatus100includes a buffer1, a D/A converter2, a VCO3, and a VCO controller4.

The buffer1stores digital data input via a transmission system to the digital AV signal processing apparatus100, and outputs digital data as output digital data. The D/A converter2converts the output digital data to analog data. The conversion rate of the D/A converter2is determined based on a clock signal generated by the VCO3.

When the conversion rate of the D/A converter2is greater than the input rate of digital data input to the buffer1, the data amount of the buffer1decreases. When the conversion rate of the D/A converter2is smaller than the input rate of digital data input to the buffer1, the data amount of the buffer Increases. The VCO controller4detects the data amount of the digital data stored in the buffer1, and controls the frequency of a clock signal generated by the VCO3based on a deviation in the detected data amount from a predetermined value and the time integral of the deviation.

The VCO controller4includes a first control section5, a second control section7, a reference data amount memory13storing the amount of data corresponding to a half of the total capacity of the buffer1, an adder11, and a second holding section12.

The first control section5includes a first comparator6which compares the data amount BDAT of the buffer1with the data amount BHLF corresponding to a half of the total capacity of the buffer1(K1represents gain). The first comparator6detects a deviation between the data amount BDAT and the data amount BHLF, and outputs output data DA1based on the deviation and the gain K1to the adder11.

FIG. 2is a graph showing an operating characteristic of the first comparator6. The horizontal axis represents the data amount BDAT of the buffer1, while the vertical axis represents the output data DA1output from the first comparator6. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer1. The operating characteristic of the first comparator6is set to pass through a point (BHLF,0) when the gradient is K1. An operating cycle of the first control section5is set to be about 10 msec. A time constant of the first control section5is determined based on the operating characteristic (gradient K1) of the first comparator6and the operating cycle of the first control section5.

The second control section7includes a second comparator8which compares the data amount BDAT of the buffer1with the amount BHLF (K2represents gain), an integrator9which calculates a time integral of output data DA0output from the second comparator8, and a first holding section10which holds an output of the integrator9.

FIG. 3is a graph showing an operating characteristic of the second comparator8ofFIG. 1. The horizontal axis represents the data amount BDAT of the buffer1, while the vertical axis represents the output data DA0output from the second comparator8. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer1. The operating characteristic of the second comparator8is set to pass through a point (BHLF,0) when the gradient is K2. An operating cycle of the second control section7is set to be100msec. A time constant of the second control section7is determined based on the operating characteristic (gradient K2) of the second comparator8and the operating cycle of the second control section7.

The gradient K2is set to be much less than the gradient K1. The operating cycle of the first control section5is set to be 10 msec. The operating cycle of the second control section7is set to be 100 msec. In this case, 1/time constant=gradient/operating cycle. Therefore, the time constant of the first control section5is much less than the time constant of the second control section7.

The second comparator8detects a deviation between the data amount BDAT and the data amount BHLF, and outputs the output data DA0based on the deviation and the gain K2to the integrator9.

The integrator9calculates a time integral of the output data DA0output from the second comparator8. The time integral calculated by the integrator9is held by the first holding section10.

The first holding section10outputs the held value as output data DA2to the adder11. The first holding section10updates the held value in a cycle of 100 msec. The first holding section10is required when a control cycle of the second control section7is set to be greater than a control cycle of the first control section5.

The adder11adds the output data DA1with the output data DA2to calculate the output data DA3of the VCO controller4.

The second holding section12outputs the output data DA3of the adder11to the VCO3. The second holding section12updates the held value in a cycle of 10 msec.

As described above, the first control section5, the second control section7, the adder11, the second holding section12, and the reference data amount memory13collectively serve as the VCO controller4which detects the data amount of the digital data stored in the buffer1, and controls the frequency of a clock signal based on a deviation in the detected data amount from a predetermined value and the time integral of the deviation.

FIG. 4is a graph showing an operating characteristic of the VCO controller4. The horizontal axis represents the data amount BDAT of the buffer1, while the vertical axis represents the output data DA3output from the VCO controller4. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer1.

An operating point P0represents a state at which the input rate of data is constant and the data amount of the buffer1is in a state of equilibrium, where the data amount of the buffer1corresponds to a half of the total capacity of the buffer1(BHLF−BDAT=0). At this time, the output data DA3of the VCO controller4is DA30.

Referring toFIG. 4, it is assumed that digital data having fluctuations of a short cycle and a long cycle in the input rate are input to the digital AV signal processing apparatus100including the buffer1.

When the short-cycle fluctuations in the input rate triggers an increase in the data amount of the buffer1, the first control section5having a small time constant responds. As the value of the output data DA1of the first control section5is increased, the operating point is shifted from P0to P1. The VCO controller4generates output data DA31so as to increase a clock frequency, so that the data amount is temporarily in a state of equilibrium at BDAT1.

Subsequently, as the value of the output data DA2of the second control section7having a large time constant gradually increases from output data DA20, a deviation (BHLF−BDAT) in the data amount is shifted toward a smaller value than P1, i.e., P2. As deviation (BHLF−BDAT) in the data amount decreases, the absolute value of the output data DA1of the first control section5decreases. The value of the output data DA1and the value of the output data DA2are cancelled with each other. As a result, P1is translated to P2, i.e., the value of the output data DA3is not changed from DA31.

FIG. 5is a graph showing fluctuations in the data amount of the buffer1when digital data having a characteristic shown inFIG. 14is input to the digital AV signal processing apparatus100including the buffer1. The horizontal axis represents time. The vertical axis represents the data amount BDAT of the buffer1. Times t1, t2, t3, t4, t5, t6, t7, and t8ofFIG. 5respectively correspond to times t1, t2, t3, t4, t5, t6, t7, and t8ofFIG. 14.

FIG. 6is a graph showing fluctuations in the frequency of a reproduced clock signal generated by the VCO3when digital data having a characteristic shown inFIG. 14is input to the digital AV signal processing apparatus100including the buffer1. The horizontal axis represents time, while the vertical axis represents the frequency of a reproduced clock signal generated by the VCO3. Times t1, t2, t3, t4, t5, t6, t7, and t8ofFIG. 6respectively correspond to times t1, t2, t3, t4, t5, t6, t7, and t8ofFIG. 5.

ComparingFIG. 5withFIG. 15, andFIG. 6withFIG. 16, the digital AV signal processing apparatus100suppresses a deviation in the data amount of the buffer1due to long-cycle fluctuations in the input rate of digital data, while securing as much stability of a reproduction clock as is conventional, as compared to the conventional digital AV signal processing apparatus300.

In this example of the present invention, all of the components of the VCO controller4are implemented by software on a microcomputer. The processing load of the VCO controller4is considerably small and therefore, the microcomputer used is not necessarily a special purpose microcomputer. The VCO controller4may be achieved by using a part of the processing capability of a system microcomputer for controlling the entire system.

Note that the digital AV signal processing apparatus100does not necessarily include the D/A converter2. The digital AV signal processing apparatus100may output the output digital data to a loudspeaker system including a D/A converter, for example.

The data amount of the buffer1is preferably maintained to correspond to about a half of the total capacity of the buffer1in order to efficiently prevent overflow and underflow of the buffer1. Therefore, the reference data amount memory13is set to store the amount of data corresponding to a half of the total capacity of the buffer1. However, the data amount stored by the reference data amount memory13may correspond to substantially a half of the total capacity of the buffer1. This is because in this case, overflow and underflow of the buffer1can be efficiently prevented.

According to the digital AV signal processing apparatus100according to the above-described example of the present invention, the frequency of a clock signal is controlled based on a deviation in the data amount of digital data stored in a buffer from a predetermined value and the time integral of the deviation.

When the deviation in the data amount of digital data stored in the buffer1from the predetermined value is steeply increased, a voltage-controlled oscillator controller can rapidly control the frequency of a clock signal based on the deviation in the data amount of digital data stored in the buffer1from the predetermined value. Therefore, when the input rate of digital data has short-cycle fluctuations, the data amount of digital data stored in a buffer can be controlled to match a predetermined value.

When the data amount of digital data stored in the buffer1remains constant while being deviated from the predetermined value, the time integral of the deviation is increased over time and therefore, the frequency of a clock signal is not maintained constant. Therefore, when the input rate of digital data has long-cycle fluctuations, the data amount of digital data stored in the buffer1can be controlled to match the predetermined value.

(Utilization of a Comparator having a Non-linear Operating Characteristic)

In the present invention, the first comparator6and the second comparator8do not need to have a linear operating characteristic.

When a deviation between the data amount BDAT of the buffer1and the amount BHLF of data corresponding to the total capacity of the buffer1exceeds a predetermined value, at least one of the first comparator6and the second comparator8may be set to have a steep operating characteristic. Further, at least one of the first comparator6and the second comparator8may be set to have a curved operating characteristic.

FIG. 7is a graph showing another operating characteristic of the first comparator6. The horizontal axis represents the data amount BDAT of the buffer1, while the vertical axis represents the output data DA1output from the first comparator6. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents a half of the total capacity of the buffer1. The operating characteristic of the first comparator6is set to be a line passing through a point (BHLF,0) where the gradient is equal to K10, when the data amount BDAT is in the range from BDAT1to BDAT2. The operating characteristic of the first comparator6is set to be a line having a gradient K11when the data amount BDAT is in the range from BDAT2to BMAX. The operating characteristic of the first comparator6is set to be a line having a gradient K12when the data amount BDAT is in the range from 0 to BDAT1.

The gradient K11is greater than the gradient K10, and the gradient K12is also greater than the gradient K10.

When the first comparator6is set to have an operating characteristic as shown inFIG. 7, underflow and overflow of the buffer1can be effectively prevented even if short-cycle fluctuations occur in the input rate of digital data.

For example, even if the data amount BDAT is decreased due to extraordinary jitter or the like, and therefore, the data amount BDAT is shifted to an operating point below the data amount BDAT1, underflow and overflow of the buffer1can be prevented.

FIG. 8is a graph showing another operating characteristic of the second comparator8. The horizontal axis represents the data amount BDAT of the buffer1, while the vertical axis represents the output data DA0output from the second comparator8. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer1. The operating characteristic of the second comparator8is set to be a line passing through a point (BHLF,0) where the gradient is K20, when the data amount BDAT is in the range from BDAT1to BDAT2. The operating characteristic of the second comparator8is set to be a line having a gradient K21when the data amount BDAT is in the range from BDAT2to BMAX. The operating characteristic of the second comparator8is set to be a line having a gradient K22when the data amount BDAT is in the range from 0 to BDAT1.

The gradient K21is greater than the gradient K20, and the gradient K22is also greater than the gradient K20.

When the second comparator8is set to have an operating characteristic as shown inFIG. 8, underflow and overflow of the buffer1can be effectively prevented even if long-cycle fluctuations occur in the input rate of digital data.

Further, when the data amount BDAT of the buffer1is largely deviated from the amount BHLF of data corresponding to a half of the total capacity of the buffer1, the control cycle of the second control section7may be changed so as to shorten the time constant of the second control section7.

As described above, according to the digital AV signal processing apparatus of this example of the present invention, a ratio of the amount of a change in the frequency of a clock signal with respect to the amount of a change in a deviation in the data amount of a buffer when the deviation exceeds a predetermined range, is set to be greater than when the deviation is below the predetermined range. Therefore, overflow and underflow of the buffer can be prevented.

(Utilization of a Ring Buffer)

Note that in a configuration of the digital AV signal processing apparatus100, the buffer1may be a ring buffer21. Hereinafter, the digital AV signal processing apparatus100including the ring buffer21will be described.

FIG. 9is a diagram showing a concept of the ring buffer21. Data from a reading position RP to a writing position WP along a direction indicated by arrow A is stored in the ring buffer21, which have yet to be read. Data from the writing position WP to the reading position RP along a direction indicated by arrow B has already been output to the D/A converter2. Data from the writing position WP to the reading position RP along the direction indicated by arrow B will be replaced with digital data which is newly received in the future.

Digital data received by the digital AV signal processing apparatus100is input to the ring buffer21from the writing position WP. The ring buffer21outputs digital data from the reading position RP.

The VCO controller4calculates the data amount of the digital data stored in the ring buffer21based on the reading and writing positions RP and WP. The VCO controller4changes at least one of the reading and writing positions RP and WP when the data amount exceeds a predetermined value which is greater than the data amount BHLF or when the data amount is below a predetermined value which is smaller than the data amount BHLF.

When data to be input to the ring buffer21is greatly delayed, the reading position RP catches up with the writing position WP, whereby underflow occurs. If a large amount of accumulated data due to the input delay is input to the ring buffer21, the writing position WP catches up with the reading position RP, whereby overflow occurs.

However, the VCO controller4changes at least one of the reading and writing positions RP and WP so that the writing position WP does not catch up with the reading position RP, and the reading position RP does not catch up with the writing position WP. Therefore, overflow and underflow of the ring buffer21can be prevented. Further, in the case of underflow, since previous data stored in the ring buffer21is automatically output, substantially no sound skip occurs, for example. Further, since sound to be reproduced is data immediately before current data, the sound has a high level of correlation with the current data, whereby satisfactory sound can be advantageously reproduced.

Preferably, when the VCO controller4changes at least one of the reading and writing positions RP and WP, at least one of the reading and writing positions RP and WP is changed so that the data amount of the buffer1is substantially a half of the total capacity.

(When Digital Data is in the Form of a Packet)

Hereinafter, description will be given of the case where digital data to be input to the digital AV signal processing apparatus100is in the form of a plurality of packets.

FIG. 10is a graph showing fluctuations with time in the data amount of the buffer1where digital data to be input to the digital AV signal processing apparatus100is in the form of a plurality of packets. The horizontal axis represents time, while the vertical axis represents the data amount BDAT of the buffer1. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer1.

Every time a packet is received, new data in the packet is stored in the buffer1. Subsequently, the data amount of the buffer1is constantly decreased until a subsequent packet is received. Thus, when digital data to be input to the digital AV signal processing apparatus100is in the form of packets, the data amount BDAT of the buffer1fluctuates in a sawtooth-like manner even if there is substantially no jitter. Therefore, the VCO controller4is set to detect the data amount of the buffer1in synchronization with the timing of the input of the packets. Further, the total capacity BMAX of the buffer1is preferably much greater than (e.g., two times or more greater than) the size of a packet.

As shown inFIG. 10, data amounts are read out at times t1, t2, t3. . . in synchronization with the timing of the input of the packets, whereby the VCO controller4can detect correct data amounts.

As described below, even when digital data to be input to the digital AV signal processing apparatus100is divided into packets having different sizes, data amounts are read out in synchronization with the timing of the input of the packets, whereby the VCO controller4can detect the correct data amount in the buffer1.

FIG. 11is a graph showing fluctuations with time in the data amount of the buffer1where digital data to be input to the digital AV signal processing apparatus100is in the form of packets having different packet sizes. The horizontal axis represents time, while the vertical axis represents the data amount BDAT of the buffer1. BMAX represents the amount of data corresponding to the total capacity of the buffer1, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer1.

It is assumed that an audio signal in the IEC958 format (having a sampling frequency of 48 kHz and a transfer rate of 1.536 Mbps) is packet-transmitted on a universal serial bus (hereinafter referred to as a “USB”). Since a USB transmits packets having a length of 1 msec, a packet of 192 bytes is transmitted every one millisecond.

Alternatively, it is assumed that another audio signal in the IEC958 format (having a sampling frequency of 44.1 kHz and a transfer rate of 1.4112 Mbps) is packet-transmitted on a USB. Since a USB transmits packets having a length of 1 msec, a unit of data having a fixed length of 1764 bytes corresponding to 10 msec needs to be divided into 10 packets, for example, nine packets of 176 bytes and one packet of 180 bytes.

FIG. 11shows fluctuations in the data amount of the buffer1with time where such an audio signal is transmitted (having a sampling frequency of 44.1 kHz and a transfer rate of 1.4112 Mbps).

In this transmission format, if the data amount of the buffer1is read out every time an element packet is input to the buffer1. Since packets are irregular in size, the data amount of the buffer1cannot be correctly detected.

In order to easily detect a correct data amount, the data amount is detected in synchronization with the timing of the input of each packet group (a group of ten element packets including nine packets of 176 bytes and one packet of 180 bytes).

As described above, digital data is input to the digital AV signal processing apparatus100in the form of a plurality of packet groups. Each packet group includes nine first packets having a first data amount (176 bytes) and one second packet having a second data amount (180 bytes), which are arranged in a predetermined sequence. The VCO controller4detects the data amount of the buffer1in synchronization with the timing of the input of each packet group.

Thus, when digital data to be input to the digital AV signal processing apparatus100is in the form of packets, the data amount BDAT of the buffer1fluctuates in a sawtooth-like manner even if there is no jitter. Therefore, the VCO controller4included in the digital AV signal processing apparatus100can detect the data amount of the buffer1by reading out the data amount in synchronization with the timing of the input of the packets.

According to the digital AV signal processing apparatus of the present invention, the frequency of a clock signal is controlled based on a deviation in the data amount of digital data stored in a buffer from a predetermined value and the time integral of the deviation.

When the deviation in the data amount of digital data stored in a buffer from a predetermined value is steeply increased, a voltage-controlled oscillator controller rapidly controls the frequency of a clock signal based on the deviation in the data amount of digital data stored in a buffer from a predetermined value. Therefore, when there are short-cycle fluctuations in the input rate of digital data, the data amount of digital data stored in a buffer can be controlled to match a predetermined value.

When the data amount of digital data stored in a buffer is maintained constant while being deviated from a predetermined value, the time integral of the deviation is increased over time, so that the frequency of a clock signal is not maintained constant. Therefore, when there are long-cycle fluctuations in the input rate of digital data, the data amount of digital data stored in a buffer can be controlled to match a predetermined value.

Further, according to the digital AV signal processing apparatus of the present invention, the ratio of the amount of change in the frequency of a clock signal with respect to the amount of a change in the deviation of the data amount of a buffer when the deviation exceeds a predetermined range, is set to be greater than when the deviation is below the predetermined range. Therefore, overflow and underflow of the buffer can be prevented.

Still further, according to the digital AV signal processing apparatus of the present invention, a ring buffer can be used as a buffer and at least one of a writing position and a reading position of the ring buffer can be changed. Therefore, overflow and underflow of the ring buffer can be prevented.

Furthermore, according to the digital AV signal processing apparatus of the present invention, even when digital data input to the digital AV signal processing apparatus is in the form of packets, the data amount of a buffer is detected in synchronization with the timing of the input of the packets. Therefore, the correct data amount of the buffer can be detected.