Fabrication of FinFETs with multiple fin heights

A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

TECHNICAL FIELD

This invention relates generally to semiconductor devices, and more particularly to Fin field effect transistors (FinFET), and even more particularly to the structure and formation methods of FinFETs with different fin heights.

BACKGROUND

Transistors are key components of modem integrated circuits. To satisfy the requirements of increasingly faster speed, the drive currents of transistors need to be increasingly greater. Since the drive currents of transistors are proportional to gate widths of the transistors, transistors with greater widths are preferred.

The increase in gate widths, however, conflicts with the requirements of reducing sizes of semiconductor devices. Fin field effect transistors (FinFET) are thus formed.FIG. 1illustrates a perspective view of a conventional FinFET. Fin4is formed as a vertical silicon fin extending above substrate2, and is used to form source and drain regions6and a channel region therebetween (not shown). A vertical gate8intersects the channel region of fin4. While not shown inFIG. 1, a gate dielectric separates the channel region from vertical gate8.FIG. 1also illustrates oxide layer18, and insulating sidewall spacers12and14formed on source and drain regions6and vertical gate8, respectively. The ends of fin4receive source and drain doping implants that make these portions of fin4conductive. The channel region of fin4is also doped.

In the FinFET as shown inFIG. 1, the channel width is close to W+2H, wherein W is the width of fin4, and H is the height of fin4. The drive currents of FinFETs are thus increased without incurring the penalty of chip area. However, in conventional schemes for forming FinFETs, all FinFETs on a given chip have the same fin height, limiting the capability for customizing the performance of FinFETs. A solution is thus needed.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, a semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

In accordance with another aspect of the present invention, a semiconductor structure includes a first trench in a semiconductor substrate, wherein the first trench encircles a first semiconductor fin, and a first oxide region underlying the first trench. A second trench is formed in the semiconductor substrate, wherein the second trench encircles a second semiconductor fin, and wherein a bottom surface of the second trench is lower than a bottom surface of the first trench. A second oxide region is formed underlying the second trench.

In accordance with yet another aspect of the present invention, a semiconductor chip includes a semiconductor substrate having a top surface, and a first and a second semiconductor strip in the semiconductor substrate. Top surfaces of the first and the second semiconductor strips are level with the top surface of the semiconductor substrate. A first insulating region encircles a bottom portion of the first semiconductor strip, wherein the first insulating region is recessed from the top surface of the semiconductor substrate by a first distance. A second insulating region encircles a bottom portion of the second semiconductor strip, wherein the second insulating region is recessed from the top surface of the semiconductor substrate by a second distance greater than the first distance.

In accordance with yet another aspect of the present invention, a method for forming a semiconductor structure includes providing a semiconductor substrate and forming a first trench in the semiconductor substrate, wherein the first trench encircles a first semiconductor fin. A first oxide region is formed underlying and substantially aligned to the first trench. A second trench is formed in the semiconductor substrate, wherein the second trench encircles a second semiconductor fin, and wherein a bottom of the second trench is lower than a bottom of the first trench. The method further includes forming a second oxide region underlying and substantially aligned to the second trench.

In accordance with yet another aspect of the present invention, a method for forming a semiconductor structure includes providing a semiconductor substrate and forming a mask layer over the semiconductor substrate. The method further includes forming and patterning a first photoresist; and etching the mask layer and the semiconductor substrate to form a first trench, wherein the first trench encircles a first semiconductor fin. The first photoresist is then removed. A second photoresist is formed and patterned. The mask layer and the semiconductor substrate are etched to form a second trench, wherein the second trench encircles a second semiconductor fin, and wherein a bottom surface of the second trench is lower than a bottom surface of the first trench. The second photoresist is then removed. The method further includes implanting oxygen ions into semiconductor substrate regions in the first and second trenches. An annealing is then performed to convert oxygen implanted regions of the semiconductor substrate into a first and a second oxide region. The mask layer is then removed.

The advantageous features of the present invention include customized fin heights of semiconductor fins, so that the FinFETs may have customized performance.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A novel method for forming semiconductor fins with different heights on a same semiconductor chip is provided. The intermediate stages of manufacturing a preferred embodiment of the present invention are illustrated. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

Referring toFIG. 2, semiconductor substrate20is provided. In the preferred embodiment, semiconductor substrate20includes silicon. Other commonly used materials, such as carbon, germanium, gallium, arsenic, nitrogen, aluminum, indium, and/or phosphorus, and the like, and combinations thereof, may also be included in semiconductor substrate20. Semiconductor substrate20may be in the form of a single crystal or compound materials.

An optional pad layer22and mask layer24are formed on semiconductor substrate20. Pad layer22is preferably a thin film formed through a thermal process, and thus comprising silicon oxide. It is used to buffer semiconductor substrate20and mask layer24so that less stress is generated. Pad layer22may also act as an etch stop layer for etching the subsequently formed mask layer24. In the preferred embodiment, mask layer24is formed of silicon nitride using low-pressure chemical vapor deposition (LPCVD). In other embodiments, mask layer24is formed by thermal nitridation of silicon, plasma enhanced chemical vapor deposition (PECVD) or plasma anodic nitridation using nitrogen-hydrogen.

Photoresist26is formed on mask layer24, and is then patterned, forming openings28in photoresist26. The patterned photoresist26includes a photoresist strip30. If viewed from the top of the structure shown inFIG. 2, photoresist strip30may be a rectangular-shaped strip isolated from other portions of photoresist26by openings28. Width W1of photoresist strip30preferably equals to the desired width of a fin of a FinFET. In an exemplary embodiment, width W1is between about 15 nm and about 60 nm.

InFIG. 3, mask layer24and pad layer22are etched through openings28, exposing underlying semiconductor substrate20. The exposed semiconductor substrate20is then etched, forming trenches32in semiconductor substrate20. In an exemplary embodiment, depth D1of trenches32is substantially close to the desired height of the fin of the desired FinFET. Trenches32encircle fin48therebetween. Photoresist26is then removed.

FIG. 4illustrates the formation and patterning of photoresist34, which defines the pattern for forming another fin. Openings36are formed in photoresist34and define photoresist strip38, which is surrounded by openings36. Mask layer24, pad layer22and semiconductor substrate20exposed through openings36are then etched sequentially, forming trenches40in semiconductor substrate20, as is shown inFIG. 5. Preferably, trenches40have depth D2different from depth D1of trenches32. In an exemplary embodiment, trench depth D2is greater than about 130 percent of trench depth D1, and may even be greater than about 150 percent of trench depth D1. Trenches40define fin50therebetween.

A separation by implantation of oxygen (SIMOX) is then performed to form insulating regions, as is illustrated inFIGS. 6 and 7A. Referring toFIG. 6, oxygen ions are implanted into regions43and45, which are portions of semiconductor substrate20directly under trenches32and40, respectively. In an exemplary embodiment, the oxygen implantation is performed using an energy of between about 25 keV and about 75 keV. The top surfaces of semiconductor substrate20are protected by mask layer24, and thus no oxygen ions are implanted. The recessed surface of semiconductor substrate20in trenches32and40are exposed, and thus oxygen ions are implanted into substrate regions43and45. Preferably, oxygen ions are implanted vertically, so that the resulting implanted regions43and45have substantially vertical edges. Alternatively, other dielectric forming ions, such as nitrogen ions, carbon ions may be implanted to form silicon nitride, silicon carbide, silicon carbonitride, and even silicon oxynitride, silicon oxycarbide if combined with oxygen ions.

InFIG. 7A, mask layer24and pad layer22are removed. An annealing is preformed to react oxygen ions with silicon in semiconductor substrate20, and hence converting implanted regions43and45into silicon oxide regions44and46, respectively. Although the annealing may cause silicon oxide regions44and46to be slightly extended outwards than the respective regions43and45due to diffusion, the edges of silicon oxide regions44and46are still substantially aligned to edges of fins48and50, respectively. In an exemplary embodiment, the annealing is performed in an oxygen-free environment, with a preferred temperature of between about 1100° C. and about 1200° C., and for a duration of between about 60 minutes and about 120 minutes. It is noted that silicon oxide regions44and46have a same depth D3, which may be between about 2000 Å and about 2500 Å. In the resulting structure, fins48and50stand above the respective silicon oxides44and46.

A top view of the structure shown inFIG. 7Ais illustrated inFIG. 7B, which illustrates fins48and50surrounded by insulating regions44and46, respectively. FinFETs can thus be formed on fins48and50.

The embodiments discussed in preceding paragraphs are formed on bulk semiconductor substrate. It is appreciated that the embodiments of the present invention may also be formed on silicon-on-insulator (SOI) structure. An exemplary embodiment is illustrated inFIG. 8. The SOI structure includes substrate80, buried oxide layer82on substrate80, and semiconductor substrate84on buried oxide layer82, wherein semiconductor substrate84is preferably formed of essentially the same materials as semiconductor substrate20(refer toFIGS. 7A and 7B). In an embodiment, insulating regions46preferably contact buried oxide layer82. In other embodiments, at least one of insulating regions44and46, preferably both, extend into buried oxide layer82, although in this case, since buried oxide layer82has already been an oxide, no silicon-implanted oxide will be formed in buried oxide layer82. The top surfaces of insulating regions46may be as low as to level with the top surface of buried oxide layer82without undesirably reducing the desired depth D2of fin50.

FIG. 9illustrates a perspective view of FinFETs52and54formed on the structure shown inFIGS. 7A and 7B. FinFET52includes gate electrode56, source and drain regions62, and gate dielectric66between gate electrode56and fin48. FinFET54includes gate electrode58, source and drain regions64, and gate dielectric68between gate electrode58and fin50.

It is appreciated that by using the teaching provided by the embodiments of the present invention, a semiconductor chip may have additional heights with depths different from depths D1and D2. The fins may be spaced far from each other, so that each fin may be used for forming a FinFET. Alternatively, more than one fin may be formed close to each other, and may be used for forming a same FinFET. An exemplary embodiment is shown inFIG. 10, wherein gate electrode90extends over two fins48. The source regions of the two fins48are connected to each other, and two drain regions of the two fins48are connect to each other. Accordingly, the gate width is further increased.