Switch circuit for FET devices having negative threshold voltages which utilize a positive voltage only

A switch circuit is disclosed including a first FET device coupled in series with an input terminal and an output terminal. A second FET device coupled to the first device in a shunt configuration. The FET devices operative in a first mode to enable electronic signal transmission between the input and output terminals, and further operative in a second mode to prevent the electronic signal transmission. A biasing network for enabling a single control signal to operate the FET devices in both the first and second modes.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates generally to switch and attenuator circuits 
and more particularly, to a switch circuit utilizing semiconductor devices 
having negative threshold voltages which are controlled by a positive 
voltage only. 
2. Description of the Prior Art 
A Field Effect Transistor (FET) is a type of semiconductor device which is 
utilized in a wide variety of electronic circuit applications. An example 
of a FET device is shown in FIG. 1, which typically includes a drain 
terminal 12, a source terminal 14 and a gate terminal 16. Disposed between 
the drain 12 and source 14 is a channel, which is the portion of the FET 
10 that actually conducts current when the device 10 is turned on. The 
channel is fabricated from either n-type or p-type material, which 
determines whether the device 10 is n-type or p-type. The gate 16 is the 
control input of the device 10, which is utilized to control the current 
flow in the channel. 
In order to turn on the FET device 10, the gate 16 must be charged to some 
potential with respect to the source. The minimal potential required to 
turn on an FET device is known as the "Threshold Voltage", which typically 
has a magnitude of less than a volt. Depending on the type of device, the 
threshold voltage is either positive or negative. For example, a n-type 
enhancement mode FET device has a positive threshold voltage, while for a 
n-type depletion mode FET it is negative. 
N-type FET devices are inherently quicker than P-type devices due to the 
appreciably greater mobility of electrons in silicon as compared to holes. 
Thus, n-type FET devices are especially well suited to be utilized in 
circuit applications which require these devices to be switched on and off 
at a high frequency. Such circuit applications include switches, variable 
attenuators, digital attenuators and other circuits which utilize FETs as 
control devices. Also, in many GaAs circuit applications n-type FETs are 
utilized in order to implement the primary circuit function. 
An example of a switch circuit that utilizes enhancement mode FETs is shown 
in FIG. 2. The use of enhancement mode FETs enables this circuit 18 to 
incorporate a positive control voltage. The circuit 18 includes a series 
pass element 28 which is an enhancement mode FET device coupled between an 
input terminal 22 and an output terminal 34. Coupled between each terminal 
22,34 and the series pass element 28 are coupling capacitors 24,32 which 
are utilized to block DC voltages. The drain terminal and source terminal 
of the series pass element 28 are both coupled to ground by a pair of 
biasing resistors 26,30 which also have large resistive values. A first 
control voltage V.sub.1 is coupled to the gate of the series pass element 
28 by a first gate resistor 36, which also has a large value. 
Further coupled to the source of the series pass element 28 is the drain of 
a shunt element 38 which is also an enhancement mode FET device. The 
source of this device 38 is coupled to ground, while a second control 
voltage V.sub.2 is coupled to the gate of the device 38 by a second gate 
resistor 40. The second gate resistor also has a large resistive value. 
The enhancement mode devices 28,38 included in the circuit 18 are turned 
on by a positive gate-source voltage and turned off when the gate-source 
voltage drops to zero volts. 
During operation, V.sub.1 rises from 0 to a positive voltage while V.sub.2 
drops from a positive voltage to 0. This causes the series pass element 28 
to be turned on and the shunt element 38 to be turned off. The series pass 
element 28 being turned on corresponds to the "on" state of the circuit, 
which enables a signal to be transmitted from the input terminal 22 to the 
output terminal 34. After the signal is transmitted through the circuit 
18, V.sub.2 rises from 0 to a positive voltage while V.sub.1 drops from a 
positive voltage to 0. This causes the series pass element 28 to be turned 
off and the shunt element 38 to be turned on corresponding to the "off" 
state of the circuit 18. In the "off" state the series pass element 28 
blocks any signal from being transmitted between the terminals 22,34, 
while the shunt element 38 shorts any noise or other type of residual 
signal to ground. 
Another example of a switch circuit is shown in FIG. 3. This circuit 40 is 
similar to the previously described circuit except that it utilizes 
depletion mode FETs as the series pass element 29 and the shunt element 
39. As previously discussed, depletion mode FETs have a negative threshold 
voltage, which means these type of devices are turned on with a 
gate-source voltage of zero volts or higher. 
In order for this circuit 40 to utilize a positive control voltage, the 
drain and source terminals of the depletion mode devices 29,39 must be 
biased high enough so that 0 volts at the gate turns these devices off. 
This is accomplished by coupling the drain and source of the series pass 
element 29 to a positive voltage V.sub.+ through the bias resistors 
26,28, and coupling the source of the shunt element 39 to the positive 
voltage V.sub.+ through an additional bias resistor 42. Resistors 26,28 
and 42 have large resistive values. An additional coupling capacitor 44 is 
also coupled to the source of the shunt element 39. This capacitor 44 is 
also of a large value for blocking DC signals from other interfacing 
circuits. 
During operation, this circuit 40 operates similarly as the circuit of FIG. 
2. Still Referring to FIG. 3, when V.sub.1 rises from 0 to a positive 
voltage while V.sub.2 drops from a positive voltage to 0, the circuit 40 
enters the "on" state, where the series pass element 29 allows a signal to 
be transmitted from the input terminal 22 to the output terminal 34. When 
V.sub.2 rises from 0 to a positive voltage while V.sub.1 drops from a 
positive voltage to 0, the circuit enters the "off" state where the series 
pass element 29 blocks any signal from being transmitted between the 
terminals 22,34, while the shunt element 39 shorts any noise or other type 
of residual signal to ground. 
The circuits of FIGS. 2 & 3 both enable the use of positive control 
voltages as previously described. However, these circuits also require two 
different control voltages V.sub.1 & V.sub.2. In order to produce the two 
control voltages, an inverter circuit is required as shown in FIG. 4. The 
inverter circuit 46 includes an enhancement mode FET 50 which is utilized 
because the first control voltage V.sub.1 is positive. The gate of the 
device 50 is coupled to V.sub.1 through a gate resistor 52 having a large 
value. The resistors 48,54 coupled to the drain and source of the device 
50 are chosen to shape the transfer curve of the output voltage V.sub.2 
with respect to control voltage V.sub.1. 
This circuit 46 operates in conjunction with the previously described 
switch circuits, wherein V.sub.1 & V.sub.2 of this circuit 46 serve as the 
control voltages for the switch circuits. During operation, V.sub.1 rises 
from 0 to some positive voltage, which turns on the FET device 50. This 
causes the output voltage V.sub.2 to be driven from a positive voltage to 
0 volts. When V.sub.1 falls to 0 volts again, the FET device 50 turns off, 
again driving V.sub.2 to a positive voltage which is the supply voltage 
V.sub.+. 
The switch circuits of FIGS. 2 & 3 both require the use of enhancement mode 
FET devices due to the use of the voltage inverter. The use of such 
devices is a significant disadvantage since many GaAs circuits use 
depletion mode devices for the primary functions. Adding enhancement mode 
devices causes an increase in fabrication cost and decrease in the circuit 
yield. These considerations have required the use of negative control 
voltages or two control voltages in many previous circuits. 
It is therefore, an object of the present invention to provide a biasing 
scheme that enables a depletion mode FET device which has a negative 
threshold voltage to be utilized in a switch circuit having a single 
positive control voltage only. 
SUMMARY OF THE INVENTION 
A switch circuit including a first FET device coupled in series with an 
input terminal and an output terminal. A second FET device is coupled to 
the first device in a shunt configuration. The FET devices operative in a 
first mode to enable electronic signal transmission between the input and 
output terminals, and further operative in a second mode to prevent the 
electronic signal transmission. A biasing means for enabling a single 
control signal to operate the FET devices in both the first and second 
modes. 
The first mode includes simultaneously turning on the first device and 
turning off the second device, while the second mode includes 
simultaneously turning off the first device and turning on the second 
device.

DETAILED DESCRIPTION OF THE DRAWING 
The present invention is directed to a biasing scheme that enables 
semiconductor devices which have negative threshold voltages, such as 
depletion mode FETs, to be controlled in a switch circuit by a single 
positive control voltage. Utilizing a single control voltage is desirable 
because it eliminates the use of inverter circuits which require 
enhancement mode FETs as described in the prior art. By not utilizing 
enhancement mode devices, the circuit according to the present invention 
decreases fabrication costs and increases yields. 
Referring to FIG. 5, there is shown a schematic diagram of the switch 
circuit according to the present invention. This circuit 56 utilizes 
depletion mode FET devices 64,80 as both the series pass element and shunt 
element. The biasing scheme of the present invention enables a single 
positive control voltage V.sub.1 to simultaneously control both depletion 
mode devices 64,80. The biasing scheme includes biasing both the drain 64A 
and source 64B of the series pass element 64 to a predetermined positive 
potential, and further biasing the gate 80C of the shunt element 80 to a 
zero or ground potential. 
The circuit 56 includes a first depletion mode FET device 64 which is 
coupled between an input terminal 58 and an output terminal 70. The first 
device is utilized to allow signals to be transferred between the 
terminals 58,70 when turned on and block such transmission when turned 
off. Coupled between each terminal 58,70 and the first device 64 are 
coupling capacitors 60,68 which block DC voltages, yet have a sufficiently 
large capacitance to pass AC signals without attenuation. The drain 64A 
and source terminal of the first device 64B are both coupled to a 
predetermined positive potential V.sub.+ by a first pair of biasing 
resistors 62,66. The gate terminal of the first device 64C is coupled to 
the control voltage V.sub.1 by a gate resistor 72. Biasing the first 
device 64 in this manner enables it be turned off when V.sub.1 is at a 
zero potential. 
The circuit 56 further includes a second depletion mode FET device 80 which 
is coupled to the first device 64 in a shunt configuration. In particular, 
the drain of the second device 80A is coupled to the source of the first 
device 64B through a third coupling capacitor 74 which is also utilized to 
block DC signals. The source terminal of the second device 80B is coupled 
to ground by a fourth coupling capacitor 84. The gate of the second device 
80C is also coupled to ground by a second gate resistor 82. 
The drain 80A and source of the second device 80B are further coupled to 
the control voltage V.sub.1 by a second pair of biasing resistors 76,78. 
Biasing the second device 80 in this manner enables it to be turned on 
when V.sub.1 is at a zero voltage and turned off when V.sub.+ is at a 
significant positive voltage. The resistors 62,66,72,76,78,82 included in 
the circuit 56 each have a large resistance value of at least 50 Kilohms. 
During operation, the circuit 56 operates in two different states or modes. 
In the first mode, the control voltage V.sub.1 is at zero potential which 
causes the first device 64 to be turned off, while simultaneously turning 
on the second device 80. The first device 64 being turned off blocks any 
signal from being transmitted between the terminals 58,70, while the 
second device 80 being turned on shorts any noise or residual signals to 
ground. 
In the second state, the control voltage V.sub.1 transitions from a zero to 
a positive potential. This causes the first device 64 to be turned on, 
while simultaneously turning off the second device 80. The first device 64 
being turned on and the second device 80 being turned off enables a signal 
to be transmitted between the input and output terminals 58,70. The 
biasing scheme of the present invention enables the depletion mode devices 
64,80 in both states to be alternately turned on and off by a single 
control voltage V.sub.1. This eliminates the need to provide two control 
voltages, which as described in the prior art can be generated by an 
additional inverter circuit. As previously discussed, including such an 
inverter circuit is undesirable in GaAs circuit applications. Fabrication 
costs and yields of these type of circuits are adversely affected when an 
inverter is included. Without an inverter circuit, the switch circuit 
requires two control voltages, thus further complicating use of the 
circuit. 
The circuit configuration of the present invention is capable of being 
utilized to achieve positive control voltages with any depletion mode 
device such as a MESFET or JFET device. This configuration is applicable 
to other types of circuits such as switches, variable attenuators, digital 
attenuators and any other circuit utilizing depletion mode devices as 
control elements. 
While the invention has been particularly shown and described with 
reference to preferred embodiments thereof, it will be understood by those 
skilled in the art that changes in form and details may be made therein 
without departing from the spirit and scope of the present invention.