Solid-state imaging device including driver circuits comprising multi-stage buffer elements

A solid-state imaging device includes: pixels disposed in a matrix of pixel rows and pixel columns; control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; drive circuits that are provided for the control wires, each include buffer elements in at least two stages, and each output a control signal to one of the control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.

FIELD

The present disclosure relates to a solid-state imaging device typified by a charge coupled device (CCD) or complementary metal oxide semiconductor (CMOS) image sensor, and an imaging apparatus.

BACKGROUND

The time of flight (TOF) technique has been known which is for measurement using a flight time taken for light to travel and reach a measurement target object (a subject) to come back, among a plurality of techniques for detecting objects. In the distance measurement calculation using the TOF technique, at least two exposure signals are obtained from reflected light from a target object, and a time difference or a phase difference (time taken for light to travel and reach an object and come back) between light emission and light reception is calculated from the amount of the exposure signals obtained, thus calculating distance measurement.

A solid-state imaging device that measures a distance simultaneously exposes all the pixels so that a global shutter solid-state imaging device is used therefor, and simultaneously closes the shutter for all the pixels. Differences in shutter timings for the pixels appear as differences in distances for the pixels, and thus it is necessary to reduce temporal differences of the shutter to enhance accuracy of the distance measurement.

In order to address this, Patent Literature (PTL) 1 discloses technology for reducing temporal differences, in which a column skew correction circuit that adjusts, for each column, a delay time of a drive signal for controlling a shutter is provided.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

However, PTL 1 requires adjustment of a delay time of a drive signal for each column, and thus requires calibration for each solid-state imaging device. For calibration, it is necessary to actually calculate a distance and feed back the result to a delay adjuster, which requires more time and more steps. In addition, the circuit scale increases. If the temperature or the voltage changes, a delay time also changes, which requires calibration each time such changes are made. If calibration is not performed, a delay time differs for each column, and accuracy in measurement decreases.

The present disclosure has been conceived in view of the above problem, and is to provide a solid-state imaging device and an imaging apparatus that achieve high measurement accuracy by reducing a difference in delay of a drive signal for each column while calibration for adjusting a delay time of a drive signal for each column is unnecessary.

Solution to Problem

In order to address the above problem, a solid-state imaging device according to an aspect of the present disclosure includes: a plurality of pixels disposed in a matrix of pixel rows and pixel columns; a plurality of control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the plurality of pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; a plurality of drive circuits that are provided for the plurality of control wires, each include buffer elements in at least two stages, and each output a control signal to one of the plurality of control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.

An imaging apparatus according to an aspect of the present disclosure includes: the solid-state imaging device; and a signal processing circuit that generates a depth image or a brightness image based on a signal received by the solid-state imaging device.

Advantageous Effects

According to the present disclosure, high measurement accuracy can be achieved by reducing a difference in delay of a drive signal for each column without calibration.

DESCRIPTION OF EMBODIMENTS

The following describes embodiments with reference to the drawings. Note that the embodiments below are essentially preferable examples, and are not intended to limit the scope of the present disclosure, products to which the present disclosure is applied, or the applications of the present disclosure. Note that elements having the same numerals perform equivalent operations, and thus a redundant description is omitted.

[1. Configuration of Imaging Apparatus1000]

FIG.1is a block diagram illustrating an example of a configuration of imaging apparatus1000according to Embodiment 1.FIG.1also illustrates object190that is a distance measurement target.

Light source driver150supplies light source160with a drive signal, according to a signal that gives an instruction for light emission from timing generation circuit120.

Light source160generates pulsed light for distance measurement according to the drive signal from light source driver150.

Lens170is for collecting reflected pulsed light from object190, which corresponds to pulsed light from light source160.

Signal processing circuit180obtains a distance to object190by calculation, based on a signal received from solid-state imaging device200.

Pixel array100includes a plurality of pixels disposed in a matrix on a semiconductor substrate. In the following, pixels aligned in a row direction are referred to as a pixel row, out of the plurality of pixels. In addition, pixels aligned in a column direction are referred to as a pixel column.

Drive circuit array110includes aligned drive circuits provided for pixel columns, and supplies pixel array100with control signals for controlling signal charge generated in the pixels.

Timing generation circuit120generates an emission signal that gives an instruction for light emission to object190(here, an example of emission of near infrared light is shown). An emission signal drives light source160via light source driver150. At this time, timing generation circuit120generates an exposure signal that gives an instruction for pixel array100to be exposed to reflected light from object190. For example, timing generation circuit120generates an exposure signal for multiple times within one frame period, to cause each pixel to store a pixel signal corresponding to a total amount of exposure for the multiple times.

AD converter130converts an analog pixel signal output from each pixel row of pixel array100into a digital pixel signal.

Vertical scanning circuit140sequentially scans pixel rows of pixel array100, to cause each pixel row to output a pixel signal to AD converter130.

Solid-state imaging device200causes light source160to emit near infrared light to object190in background light, as illustrated inFIG.1. Reflected light from object190enters pixel array100through optical lens170. The reflected light that enters pixel array100forms an optical image, and the optical image is converted into pixel signals. Output from solid-state imaging device200is converted into distance data by signal processing circuit180, and is converted into a visible depth image or brightness image according to its application.

Note that signal processing circuit180is not necessarily provided outside solid-state imaging device200, and some or all the functions for calculating a distance, for instance, may be provided in solid-state imaging device200.

Examples of solid-state imaging device200include a so-called CMOS image sensor.

FIG.2is a block diagram illustrating an example of a detailed configuration of solid-state imaging device200according to Embodiment 1. Solid-state imaging device200includes pixel array100, drive circuit array110, timing generation circuit120, and AD converter130.

Pixel array100includes pixels101disposed in a matrix. Here, pixels101are unit elements each provided with, as necessary, a device structure for reading a signal generated through photoelectric conversion such as: a light-sensitive element such as a photodiode or a photogate; a photoelectric conversion film that includes amorphous silicon; or an organic photoelectric conversion film, and a structure that allows an initial operation to be performed. Such pixels are examples of sensitive pixels, and pixel array100is an example of a sensitive element array.

Drive circuit array110includes one or more drive circuits111provided for the pixel columns, and first wire113. Drive circuit array110controls storage and discharge of charge in and from pixels101.

Drive circuits111output control signals having the same phase in order to implement a global shutter. Each drive circuit111applies a drive pulse as a control signal to each electrode of pixels101through electrode drive wire114as a control wire for controlling pixels. Electrode drive wire114includes one or more control wires. More specifically, each drive circuit111supplies pixel array100with control signals for controlling resetting and reading signal charge generated in pixels101in a pixel column for which the drive circuit is provided. The control signals control simultaneous operation of all pixels101in order to implement a global shutter. In the following, a wire for conveying control signals and signals indicating drive pulses output from drive circuit array110is referred to as electrode drive wire114. Note that at least one drive circuit111is provided for each pixel column. The number of drive circuits111for one pixel column depends on the configuration of pixels101. In addition, the above “reading” in response to a control signal stated above means transfer of signal charge in pixel101, and means, for example, transfer (or reading) of signal charge from a photodiode to a floating diffusion layer.

First wire113short-circuits signal wires through which control signals having the same phase are conveyed, in two or more drive circuits111out of plural drive circuits111. The signal wires short-circuited by first wire113have averaged delayed times, as compared to the case when the signal wires are not short-circuited. Thus, a difference in delay time between short-circuited drive circuits111can be reduced while calibration described in relation to a conventional technology is unnecessary. In addition, a circuit for calibration is unnecessary, and thus a circuit scale can be reduced.

Note that examples of two or more drive circuits111may include a group of drive circuits111for even-numbered pixel columns, a group of drive circuits111for odd-numbered pixel columns, and a group of drive circuits111that operate in a pixel-thinned operation mode.

Timing generation circuit120generates an emission signal and an exposure signal already described, based on an instruction from signal processing circuit180.

AD converter130includes column analog-digital converters (ADCs)131provided for the pixel columns, memory array132, and output circuit133.

Each column ADC131is provided for one column or plural columns of pixels101, and converts analog pixel signals output from pixels101through vertical signal wire102into digital pixel signals.FIG.2illustrates an example in which each column ADC131is provided for one column. The digital pixel signals are transferred to memory array132, and sequentially output to signal processing circuit180as pixel signals through output circuit133.

Vertical scanning circuit140sequentially scans pixel columns of pixel array100as units, and reads and initializes pixel signals. The read pixel signals are transmitted to column ADCs131through vertical signal wires102provided for the columns, and converted into digital signals.

[1.2 Configuration of Pixel101]

FIG.3illustrates an example of a configuration of pixel101and an example of a configuration of electrode drive wire114.

Pixel101includes photoelectric converter300, reset electrode310, first read electrode330, second read electrode350, first charge storage340, second charge storage360, first selection transistor370, second selection transistor380, floating diffusion layer390, reset transistor400, and source follower410.

Photoelectric converter300converts light into charge, and stores the charge.

Reset electrode310is a gate electrode of a reset transistor that connects charge discharger320and photoelectric converter300.

First read electrode330is a gate electrode of a first transfer transistor that reads charge from photoelectric converter300to first charge storage340.

Second read electrode350is a gate electrode of a second transfer transistor that reads charge from photoelectric converter300to second charge storage360.

First charge storage340is a capacitor or a diffusion layer that holds charge read from photoelectric converter300.

Second charge storage360is a capacitor or a diffusion layer that holds charge read from photoelectric converter300.

First selection transistor370connects first charge storage340and the gate electrode of source follower410, according to control by a first selection signal. A first selection signal is supplied from vertical scanning circuit140to the gate electrode of first selection transistor370.

Second selection transistor380connects second charge storage360and the gate electrode of source follower410, according to control by a second selection signal. A second selection signal is supplied from vertical scanning circuit140to the gate electrode of second selection transistor380.

Floating diffusion layer390holds charge transferred from first charge storage340through first selection transistor370, and holds charge transferred from second charge storage360through second selection transistor380.

Reset transistor400resets floating diffusion layer390according to a reset signal. A reset signal is supplied from vertical scanning circuit140to the gate electrode of reset transistor400.

Source follower410converts charge held in floating diffusion layer390into voltage, and outputs the voltage to vertical signal wire102.

Electrode drive wire114includes reset control wire114A, first read control wire114B, and second read control wire114C.

When a drive pulse is applied to reset electrode310through reset control wire114A, charge stored in photoelectric converter300is discharged to charge discharger320.

When a drive pulse is applied to first read electrode330through first read control wire114B, charge stored in photoelectric converter300is transferred to first charge storage340.

When a drive pulse is applied to second read electrode350through second read control wire114C, charge stored in photoelectric converter300is transferred to second charge storage360.

[1.3 Configuration of Drive Circuit Array110]

FIG.4Aillustrates an example of a detailed configuration of drive circuit array110.

Pixel101inFIG.4Ahas the same configuration as the example illustrated inFIG.3. It is assumed that as electrode drive wire114from drive circuit array110, reset control wire114A, first read control wire114B, and second read control wire114C are connected to each pixel101.

Drive circuit array110includes three drive circuits111A to111C for each pixel column. Three drive circuits111A to111C are for reset control wire114A, first read control wire114B, and second read control wire114C, respectively. Note that when it is not necessary to particularly distinguish between drive circuits111A to111C, drive circuits111A to111C are each simply referred to as drive circuit111.

A reset control signal having drive pulse ΦODG is input from timing generation circuit120to drive circuit111A for each pixel column. Each drive circuit111A outputs a reset control signal to reset electrode310in each pixel101in a corresponding pixel column through reset control wire114A.

A first read control signal having drive pulse ΦTG1is input from timing generation circuit120to drive circuit111B for each pixel column. Each drive circuit111B outputs a first read control signal to first read electrode330in each pixel101in a corresponding pixel column through first read control wire114B.

A second read control signal having drive pulse ΦTG2is input from timing generation circuit120to drive circuit111C for each pixel column. Each drive circuit111C outputs a second read control signal to second read electrode350in each pixel101in a corresponding pixel column through second read control wire114C.

Each drive circuit111includes at least two stages of buffer elements112. Drive circuit111inFIG.4Aincludes three stages of buffer elements112ato112c. Buffer elements112ato112care configured to have drive capability such that buffer element112ahas the highest drive capability, buffer element112bhas the second highest drive capability, and buffer element112chas the third highest drive capability. Note that the drive capability of buffer element112can be increased by increasing the size of a transistor for output in buffer element112. The drive capability of buffer element112can be increased by including transistors for output that are disposed in parallel in buffer element112.

Note that when buffer elements112ato112care not distinguished in particular, buffer elements112ato112care each simply referred to as buffer element112. Here, buffer element112may be an inverter circuit whose polarity can be inverted or a buffer circuit whose polarity does not change.

First wire113includes at least one wire that short-circuits signal wires in two or more drive circuits111, through which signals having the same phase are conveyed. InFIG.4A, first wire113includes three types of first wires113A,113B, and113C corresponding to reset control wire114A, first read control wire114B, and second read control wire114C. Furthermore, first wire113includes three types of first wires113D,113E, and113F corresponding to reset control wire114A, first read control wire114B, and second read control wire114C.

Each of drive circuits111A drives a reset control signal having the same phase as that of a reset control signal driven by drive circuit111A in another column, if a difference in delay time is disregarded. Similarly, each of drive circuits111B in the columns drives a first read control signal having the same phase as that of a first read control signal driven by drive circuit111B in another column. The same also applies to drive circuit111C.

First wire113A short-circuits wires in two or more drive circuits111A, through which signals having the same phase are conveyed. InFIG.4A, first wire113A short-circuits output wires of buffer elements112bin the second stage in drive circuits111A. Accordingly, a difference in delay time between the output wires of buffer elements112bin drive circuits111A can be averaged.

First wire113B short-circuits output wires of buffer elements112bin the second stage in drive circuits111B. Similarly, first wire113C short-circuits output wires of buffer elements112bin the second stage in drive circuits111C.

First wire113D short-circuits output wires of buffer elements112ain the first stage in drive circuits111A. Accordingly, a difference in delay time between the output wires of buffer elements112ain drive circuits111A can be averaged.

First wire113E short-circuits output wires of buffer elements112ain the first stage in drive circuits111B. Similarly, first wire113F short-circuits output wires of buffer elements112ain the first stage in drive circuits111C. The first wires are configured such that the impedance of first wires113A to113C is lower than the impedance of first wires113D to113F. For example, the width of first wires113A to113C may be greater than the width of first wires113D to113F. Alternatively, first wires113D to113F may each include a single wire, and first wires113A to113C may each include parallel lines.

Loads driven by each drive circuit111are wire loads and gate loads the number of which is the same as the number of pixels that are driven, and thus are heavy. Thus, buffer elements112cin the last stage of drive circuits111need to have high drive capability. If buffer elements112cin the last stage are driven directly using drive pulses generated by timing generation circuit120, loads are too heavy and a long voltage rise time and a long voltage fall time are necessary, which results in a time lag in drive pulse between the columns. Accordingly, in drive circuits111, buffer elements112connected in multiple stages need to have gradually increasing drive capability from the first stage to the last stage. For example, the size of transistors included in buffer elements112is gradually increasing from buffer element112ain the first stage to buffer element112cin the last stage.

First wire113short-circuits output wires of buffer elements112that drive signals having the same phase, and reduces a time lag in drive pulse between the columns. Stated differently, first wire113is a wire for averaging a delay. A time delay between columns is generated due to manufacturing variations in transistors included in drive circuits111, a difference in wire resistance and capacity caused by a layout difference, and a difference in power source drop. First wire113short-circuits nodes in the drive circuits at low impedance, to change the potentials at the nodes to the same potential. Accordingly, this works to decrease a time lag through first wire113even when a time delay occurs between columns of drive circuits111. In addition, first wire113is provided in a horizontal direction of drive circuit array110, and thus a time lag is decreased in the entire drive circuit array.

Note that if a time lag occurs between columns, a potential difference between the columns is generated, and flow-through current flows through first wire113. In particular, the longer the time lag is, the greater the potential difference is, resulting in an increase in flow-through current. If a high current flows due to flow-through current, this may lead to melting of a wire and damage of a transistor. In drive circuits111, there is a longer time lag between columns in buffer element112in a downstream stage, thus a time lag is shorter in buffer element112in an upstream stage in drive circuits111. Accordingly, if first wire113short-circuits output wires of buffer elements in an upstream stage in drive circuits111in columns, a time lag is short, and thus flow-through current through first wire113can be decreased.

Plural first wires113may be provided, rather than single first wire113. Single first wire113yields an advantageous effect of reducing a time lag, yet there is a longer time lag in buffer element112in a downstream stage as mentioned above. Thus, a time lag can be decreased if output wires of buffer elements112are short-circuited for each stage. The drive capability of buffer elements112in a downstream stage in drive circuits111is higher, and thus the impedance of first wire113for a downstream stage is lower. The impedance is decreased by, for instance, providing thicker first wire113for a downstream stage, through which more flow-through current flows, and thus a wire can be prevented from being melted or cut.

Buffer electrodes112cin the last stage connected to electrode drive wires114have high drive capability, and if they are short-circuited between columns, great flow-through current flows, and thus a wire may be melted and cut and a transistor may be damaged. Accordingly, electrode drive wires114are not short-circuited between columns, and are made independent column by column.

Next, another example of a configuration of drive circuit array110is to be described.

FIG.4Billustrates another example of a configuration of drive circuit array110according to Embodiment 1. The configuration inFIG.4Bis different from that of drive circuit array110inFIG.4Ain that drive circuits111A to111C each include M drive circuit groups resulting from being divided into M (M is an integer greater than or equal to 2), first wires113A to113C are provided for each of the M drive circuit groups, and short-circuit output wires of buffer elements belonging to the drive circuit group. The following gives a description, focusing on different points.

Plural drive circuits111A to111C each include two drive circuit groups resulting from the drive circuits being divided into two. InFIG.4B, M=2. Specifically, drive circuits111A are divided into a drive circuit group that includes drive circuits111in odd-numbered columns, and a drive circuit group that includes drive circuits111in even-numbered columns. Drive circuits111B are divided into a drive circuit group in odd-numbered columns, and a drive circuit group in even-numbered columns. The same also applies to drive circuits111C.

First wire113A inFIG.4Acorresponds to two first wires113Ao and113Ae inFIG.4B. First wire113Ao short-circuits output wires of buffer elements112bin the drive circuit group in odd-numbered columns. First wire113Ae short-circuits output wires of buffer elements112bin the drive circuit group in even-numbered columns.

First wire113B corresponds to first wire113Bo for odd-numbered columns and first wire113Be for even-numbered columns.

Similarly, first wire113C corresponds to first wire113Co and first wire113Ce.

First wire113D inFIG.4Acorresponds to two first wires113Do and113De inFIG.4B. First wire113Do short-circuits output wires of buffer elements112ain the drive circuit group in odd-numbered columns. First wire113De short-circuits output wires of buffer elements112ain the drive circuit group in even-numbered columns.

First wire113E corresponds to first wire113Eo for odd-numbered columns and first wire113Ee for even-numbered columns.

Similarly, first wire113F corresponds to first wire113Fo and first wire113Fe.

FIG.4Billustrates an example in which pixel columns are divided equally into two. In this case, loads of first wires113on drive circuit array110can be decreased in a pixel-thinned operation mode for generating an image based on pixels, the number of which in the row direction is halved.

Note that dividing into M may not mean dividing equally into M, and M may be three or more. For example, when an image based on pixels, the number of which in the row direction is quartered, is generated, all the pixel columns may be divided into two at 1:3 or may be divided into three at 1:2:1.

Next, operation of solid-state imaging device200during an exposure period is to be described with reference toFIGS.5and6.

FIG.5is a flowchart illustrating exposure operation in Embodiment 1.FIG.6is a timing chart illustrating drive pulses during exposure operation in Embodiment 1.

First, reset step ST00is performed as an initial operation immediately before time t1. Drive pulse ΦODG applied to reset electrode310is in the high state, and photoelectric converter300is in the reset state. Drive pulse ΦTG1applied to first read electrode330and drive pulse ΦTG2applied to second read electrode350are in the low state, and photoelectric converter300, first charge storage340, and second charge storage360are electrically isolated. In this state, signal charge generated in photoelectric converter300is discharged to charge discharger320through reset electrode310, and is not stored in photoelectric converter300.

Next, the processing proceeds to light storage start step ST01at time t1. When reset electrode310is placed in the low state, and discharge of charge from photoelectric converter300to charge discharger320is stopped. Photoelectric converter300is placed in a state for storing generated signal charge. At the same time, timing generation circuit120applies a light-emission trigger signal to light source driver150, and light source160emits infrared pulsed light (emission pulsed light). After emitting infrared pulsed light, reflected light enters pixel array100with a time difference according to a distance to object190.

Next, the processing proceeds to first read step ST02at time t2. First read electrode330is placed in the high state, and photoelectric converter300and first charge storage340are electrically connected. The signal charge stored in photoelectric converter300is transferred to first charge storage340.

Next, first read electrode330is placed in the low state at time t3, photoelectric converter300and first charge storage340are electrically isolated, and reading signal charge S0is completed. At the same time, timing generation circuit120applies a trigger signal to light source driver150, and light source160stops emitting infrared pulsed light. Signal charge S0is an amount of charge in proportion to time (Tp−Tf) obtained by subtracting reach time Tf taken by reflected light to reach pixel array100after infrared pulsed light is emitted from emission time Tp of infrared pulsed light.

Next, the processing proceeds to second read step ST03at time t4. Second read electrode350is placed in the high state, and photoelectric converter300and second charge storage360are electrically connected. The signal charge stored in photoelectric converter300is transferred to second charge storage360.

Next, second read electrode350is placed in the low state at time t5, photoelectric converter300and second charge storage360are electrically isolated, and reading signal charge S1is completed. Signal charge S1is an amount of charge in proportion to reach time Tf.

Next, the processing proceeds to reset step ST04at time t6. Reset electrode310is placed in the high state, photoelectric converter300and charge discharger320are electrically connected, and photoelectric converter300is placed in the reset state, thus achieving a state in which charge is not stored in photoelectric converter300.

When exposure is repeated, the processing proceeds to emission accumulation start step ST01again, and operation from emission accumulation start step ST01to reset step ST04is repeated. Operation from emission accumulation start step ST01to reset step ST04is performed multiple times within a single frame period, and signal charge S0and signal charge S1according to a total amount of exposure for the multiple times are stored in first charge storage340and second charge storage360, respectively. After repetition of exposure ends, exposure is completed.

After the exposure period ends, first select transistor370is placed in the high state, and reading signal charge S0starts. Signal charge S0is transferred to floating diffusion layer390, and is converted into a voltage in source follower410. Signal charge S0converted into a voltage is converted into a digital signal in column ADC131through vertical signal wire102. When reading signal charge S0is completed, reset transistor400is placed in the high state, and floating diffusion layer390is reset to the initial state. Pixel array100is sequentially scanned in the vertical direction, and signal charges S0of all pixels101are converted into digital signals.

Next, after first select transistor370is placed back into the low state, second select transistor380is placed in the high state, and reading signal charge S1starts. Signal charge S1is transferred to floating diffusion layer390similarly to signal charge S0, and is converted into a voltage in source follower410. Signal charge S1converted into a voltage is converted into a digital signal in column ADC131through vertical signal wire102. When reading signal charge S1is completed, reset transistor400is placed in the high state, and floating diffusion layer390is reset to the initial state. Pixel array100is sequentially scanned in the vertical direction, and signal charges S1of all pixels101are converted into digital signals.

Here, distance Z from imaging apparatus1000to object190can be obtained from reach time Tf by using Expression (1) below, where the speed of light is c.

Signal charge S0is an amount of charge in proportion to Tp−Tf resulting from subtracting reach time Tf from emission time Tp, and signal charge S1is an amount of charge in proportion to reach time Tf, and thus ratio S1/S0of signal charges is equal to ratio Tf/(Tp−Tf) of the reach time and the emission time. Reach time Tf is obtained as follows by Expressions (2a) and (2b) below, based on emission time Tp and signal charges S1and S0.

Thus, distance Z to object190is obtained by Expression (3) below, based on signal charges S0and S1and emission time Tp.

If first wire113is not provided, a time lag occurs between columns. If there is time lag Δt, signal charge S1is proportional to Tf−Δt resulting from subtracting time lag Δt from reach time Tf, whereas signal charge S0is proportional to Tp−Tf+Δt resulting from adding time lag Δt to the result of Tp−Tf resulting from subtracting reach time Tf from emission time Tp. Thus, ratio S1/S0of signal charges is obtained by Expressions (4a) and (4b) below.

Since time lag Δt is added to actual reach time Tf, measurement distance difference ΔZ is generated in distance Z to object190, as shown by Expression (5) below.

As an example, measurement distance difference ΔZ generated is about 15 mm when the speed of light is c=299,792,458 m/s and a time lag is Δt=100 ps. By using first wire113, time lag Δt between columns can be reduced, and measurement distance difference ΔZ can be reduced. As a result, high measurement accuracy can be achieved without calibration or increasing circuit scale.

Next, a variation of solid-state imaging device200is to be described.

FIG.4Cillustrates a variation of the pixel array and a variation of the drive circuit array according to Embodiment 1. Drive circuit array110inFIG.4Cis different from the drive circuit array inFIG.4Ain that reset control wires14A for pixel rows are provided instead of reset control wires114A for pixel columns, drive circuits11A for pixel rows are provided instead of drive circuits111A for pixel columns, first wire13A is provided instead of first wire113A, and first wire13D is provided instead of first wire113D. In the following, a redundant description for the same point is avoided, and different points are mainly described.

Reset control wires14A are provided for pixel rows, and each transfer a reset control signal having drive pulse ΦODG output from vertical scanning circuit140through drive circuit11A to pixels101in the pixel row for which reset control wire14A is provided.

Drive circuit11A is provided for each pixel row and in the last stage in vertical scanning circuit140. Each drive circuit11A outputs a reset control signal to reset electrode310in each pixel101in a corresponding pixel row through reset control wire14A. Note that drive circuit11A may be provided between vertical scanning circuit140and pixel array100.

Each drive circuit11A includes at least two stages of buffer elements11. Drive circuit11A inFIG.4Cincludes buffer elements11ato11cin three stages. Buffer elements11ato11care configured to have drive capability such that buffer element11ahas the highest drive capability, buffer element11bhas the second highest drive capability, and buffer element11chas the third highest drive capability. Note that when buffer elements11ato11care not distinguished in particular, buffer elements11ato11care each simply referred to as buffer element11. Here, buffer element11may be an inverter circuit whose polarity can be inverted or a buffer circuit whose polarity is not changed.

First wire13A is a type of the first wire, and includes at least one wire that short-circuits signal wires in two or more drive circuits11, through which signals having the same phase are conveyed.

First wire13D is a type of the first wire, and includes at least one wire that short-circuits signal wires in two or more drive circuits11, through which signals having the same phase are conveyed. When first wire13A and first wire13D are not distinguished in particular, first wire13A and first wire13D are each simply referred to as first wire13.

Each of drive circuits11A drives a reset control signal having the same phase as that of drive circuit11A in another column, if a difference in delay time is disregarded.

First wire13A short-circuits wires in two or more drive circuits11A, through which signals having the same phase are conveyed. InFIG.4C, first wire13A short-circuits output wires of buffer elements11bin the second stage in drive circuits11A. Accordingly, a difference in delay time between the output wires of buffer elements11bin drive circuits11A can be averaged.

First wire13D short-circuits output wires of buffer elements11ain the first stage in drive circuits11A. Accordingly, a difference in delay time between the output wires of buffer elements11ain drive circuits11A can be averaged.

The first wires are configured such that the impedance of first wire13A is lower than the impedance of first wire13D. For example, the width of first wire13A may be greater than the width of first wire13D. Alternatively, first wire13D may include a single wire, and first wire13A may include parallel lines.

Loads driven by each drive circuit11A are wire loads and gate loads the number of which is the same as the number of pixels that are driven, and thus are heavy. Thus, buffer elements11cin the last stage of drive circuits11A need to have high drive capability. If buffer elements11cin the last stage are driven directly using drive pulses generated by timing generation circuit120, loads are too heavy and a long voltage rise time and a long voltage fall time are necessary, which results in a time lag in drive pulse between columns. Accordingly, in drive circuits11A, connected buffer elements11in multiple stages need to have gradually increasing drive capability from the first stage to the last stage. For example, the size of transistors included in buffer elements11gradually increases from buffer element11ain the first stage to buffer element11cin the last stage.

First wire13short-circuits output wires of buffer elements11that drive signals having the same phase, and reduces a time lag in drive pulse between columns. Stated differently, first wire13is a wire for averaging a delay. A time delay between columns is generated due to manufacturing variations in transistors included in drive circuits11, a difference in wire resistance and capacity caused by a layout difference, and a difference in power source drop. First wire13short-circuits nodes in the drive circuits at low impedance, to change the potentials at the nodes to the same potential. Accordingly, this works to decrease a time lag with use of first wire13A even when a time delay occurs between columns of drive circuits11A. In addition, first wire13is provided in a vertical direction of drive circuit array110, and thus a time lag is decreased in entire drive circuit array110.

As described above, solid-state imaging device200according to the present embodiment includes: plural pixels101disposed in a matrix of pixel rows and pixel columns; plural control wires114provided for the pixel rows or the pixel columns, and each connected to at least two pixels101out of plural pixels101, at least two pixels101being included in one of the pixel rows or the pixel columns for which control wire114is provided; plural drive circuits111that are provided for plural control wires114, each include buffer elements112ato112cin at least two stages, and each output a control signal to one of plural control wires114for which drive circuit111is provided, the buffer elements in the at least two stages being connected in series; and first wire113that short-circuits output wires of buffer elements112in one of the at least two stages in at least two of plural drive circuits111.

According to this, a difference in delay that is a time lag of control signals for each control wire114, by first wire113causing a short-circuit. Thus, high measurement accuracy can be achieved by reducing a difference in delay of a control signal for each column without calibration.

Here, first wire113averages delays of at least two of plural control wires114that occur in at least two of the pixel rows or at least two of the pixel columns.

Here plural pixels101may include optical black pixels and normal pixels that are not the optical black pixels, and first wire113has a length longer than a side out of four sides that define an effective region constituted by the normal pixels, the side extending parallel to first wire113.

According to this, the first wire can be connected to output wires of buffer elements112in arbitrary pixel columns out of all the pixel columns.

Here, plural drive circuits111may include M drive circuit groups into which plural drive circuits111are divided, M being an integer greater than or equal to 2. First wire113may be provided for each of the M drive circuit groups, and short-circuit output wires of buffer elements112in the M drive circuit group.

This is suitable to generate an image having fewer pixels than all the pixels, using pixel columns for which the drive circuit group is provided, for example.

Here, one of the M drive circuit groups may consist of one or more drive circuits111that operate in a pixel-thinned operation mode.

According to this, for example, when, for instance, a low-resolution image is generated, in a pixel-thinned operation mode in which one mth of all the pixel columns (m is an integer greater than or equal to 2) are used and pixel columns other than those pixel columns are not used, necessary drive circuits111only can be short-circuited by the first wire. Accordingly, parasitic capacitance of the first wire can be reduced, and the pixel-thinned operation mode can be executed at higher speed.

Here, first wire113may be provided for each of the at least two stages of buffer elements112, excluding a most upstream stage.

Here, first wire113provided for buffer elements112in one stage out of buffer elements112in the at least two stages may have impedance lower than impedance of first wire113provided for buffer elements in a stage upstream from the one stage out of buffer elements112in the at least two stages.

According to this, the occurrence of the above difference in delay time can be further reduced.

Here, first wire113provided for buffer elements112in one stage out of buffer elements112in the at least two stages may have a width greater than a width of first wire113provided for buffer elements112in a stage upstream from the one stage out of buffer elements112in the at least two stages.

According to this, the occurrence of the above difference in delay time can be further reduced.

Here, buffer elements112in one stage out of buffer elements112in the at least two stages may have drive capability higher than drive capability of buffer elements112in a stage upstream from the one stage out of buffer elements112in the at least two stages.

According to this, the occurrence of the above difference in delay time can be further reduced.

Here, plural pixels101may each include photoelectric converter300that converts light into charge, and read electrode330/350for reading the charge from photoelectric converter300, and plural control wires114may be each connected to read electrode330/350in each of at least two pixels101.

Here, plural pixels101may each include reset electrode310for resetting charge in pixel101, and plural control wires114may each be connected to reset electrode310in each of at least two pixels101.

Here, plural pixels101may each include photoelectric converter300that converts light into charge, first read electrode330for reading the charge from photoelectric converter300, and reset electrode310for resetting the charge in pixel101. Plural control wires114provided for the pixel columns may each include first read control wire114B connected to first read electrode330in each of at least two pixels101, and reset control wire114A connected to reset electrode310in each of at least two pixels101. Solid-state imaging device200may include, for each of the pixel columns, drive circuit111B connected to first read control wire114B, and drive circuit111A connected to reset control wire114A, drive circuit111B and drive circuit111A being included in plural drive circuits111.

Here, plural pixels101may each further include second read electrode350for reading the charge from photoelectric converter300. Plurality control wires114provided for the pixel columns may each further include second read control wire114C connected to second read electrode350in each of at least two pixels101. Solid-state imaging device200may further include, for each of the pixel columns, drive circuit111C connected to second read control wire114C, drive circuit111C being included in plural drive circuits111.

The imaging apparatus according to Embodiment 1 includes solid-state imaging device200described above, and signal processing circuit180that generates a depth image or a brightness image based on a signal received by solid-state imaging device200.

Note that the first wire that short-circuits output wires of corresponding buffer elements112in any of the stages may include not only a single wire, but also two or more wires connected in parallel. Two or more first wires113connected in parallel may be formed in a single wiring layer, or may be formed in a plurality of wiring layers.

[2. Configuration of Drive Circuit Array110]

FIG.7illustrates a configuration of drive circuit array110according to Embodiment 2. As illustrated inFIG.7, drive circuit array110in Embodiment 2 is different from drive circuit array110inFIG.4Ain that wire swappers510ato510care additionally included. The following description focuses on different points. Note that when wire swappers510ato510care not distinguished in particular, wire swappers510ato510care each simply referred to as wire swapper510.

Wire swappers510ato510ceach connect an output wire of buffer element112in drive circuit111to buffer element112that is not in the same column but in the same stage, and thus swap wires in drive circuit111in different columns. In other words, wire swappers510ato510ceach cause wires in plural drive circuits111to cross, to substantially swap between buffer elements112in a same stage in plural drive circuits111, out of buffer elements112in the at least two stages in each of plural drive circuits111.

AlthoughFIG.7illustrates an example in which wire swappers510ato510care provided at three locations, wire swappers may be provided at two locations or four or more locations. In addition,FIG.7illustrates an example in which wires are swapped between adjacent drive circuits111provided for the same pixel column, yet wires may be swapped between drive circuits111that are not adjacent to each other.

The exposure operation in Embodiment 2 is performed following the steps inFIG.5, similarly to Embodiment 1.

As described above, in the solid-state imaging device according to the present embodiment, with regard to a difference between columns of drive circuits111due to a difference in layout and manufacturing variations, by swapping paths through which drive signals pass, delay times of drive signals that differ for the columns can be averaged so that a difference in delay time between columns can be reduced. In particular, it is effective in reducing a difference in delay time between columns when drive signals have different phases and first wire113cannot short-circuits the columns. As a result, a delay difference in drive signals having different phases can be reduced, and measurement accuracy can be enhanced.

As described above, solid-state imaging device200according to Embodiment 2 may further include: wire swapper510that causes wires in plural drive circuits111to cross, to substantially swap between buffer elements112in a same stage in plural drive circuits111, out of buffer elements112in the at least two stages in each of plural drive circuits111.

Here, two or more wire swappers510may be provided, two or more wire swappers510each being wire swapper510. Each of two or more wire swappers510may be provided at input wires or output wires of buffer elements112in the at least two stages in plural drive circuits111.

[3. Configuration of Drive Circuit Array110]

FIG.8illustrates a configuration of drive circuit array110according to Embodiment 3. As illustrated inFIG.8, wire swappers510in Embodiment 3 are different from the wire swappers inFIG.7in that wire swappers510dand510eare provided instead of wire swappers510ato510c. The following description focuses on different points. Note that when wire swappers510dand510eare not distinguished in particular, wire swappers510dand510eare each simply referred to as wire swapper510.

Wire swapper510dincludes three selection circuits530for each pixel column. Selection circuits530each include one input terminal and three output terminals, select one of the output terminals, and connect the input terminal to the selected output terminal. Three selection circuits530for one pixel column each swap an input wire of buffer element112ain a corresponding one of three drive circuits111.

Selection circuit530to which drive pulse ΦODG is input selects one of input wires of buffer elements112ain three drive circuits111for a pixel column, and conveys drive pulse ΦODG to the selected input wire.

Selection circuit530to which drive pulse ΦTG1is input selects one of input wires of buffer elements112ain three drive circuits111for a pixel column, and conveys drive pulse ΦTG1to the selected input wire.

Similarly, selection circuit530to which drive pulse ΦTG2is input selects one of input wires of buffer elements112ain three drive circuits111for a pixel column, and conveys drive pulse ΦTG3to the selected input wire.

Three selection circuits530for one pixel column each exclusively select buffer element112ato which a drive pulse is conveyed.

Wire swapper510eincludes three selection circuits531for each pixel column. Selection circuits531each include three input terminals and one output terminal, select one of the input terminals, and connect the selected input terminal to the output terminal. Three selection circuits531for one pixel column swap output wires of buffer elements112cin three drive circuits111connected thereto. In the example of a configuration inFIG.8, selection circuits531each perform select operation to place swapped wires by corresponding selection circuit530into its original state.

Accordingly, three selection circuits530and531for pixel columns function to swap drive circuit111in one column to drive circuit111in a different column according to select switch signal540.

For example, when select switch signal540indicates “0”, drive circuit111is connected to control wire114in the same column. In this case, drive circuit111A is connected to reset control wire114A, drive circuit111B is connected to first read control wire114B, and drive circuit111C is connected to second read control wire114C.

When select switch signal540indicates “1”, drive circuit111is connected to another control wire not in the same column. In this case, drive circuit111B is connected to reset control wire114A, drive circuit111C is connected to first read control wire114B, and drive circuit111A is connected to second read control wire114C.

When select switch signal540indicates “2”, drive circuit111is connected to yet another control wire not in the same column. In this case, drive circuit111C is connected to reset control wire114A, drive circuit111A is connected to first read control wire114B, and drive circuit111B is connected to second read control wire114C.

An example in which select switch signal540has three values is shown, yet select switch signal540may have two values or four or more values.

Next, exposure operation in Embodiment 3 is to be described with reference to the flowchart inFIG.9. The flowchart inFIG.9additionally includes drive circuit swap step ST05as compared to the flowchart inFIG.5, and the other steps are the same as those in Embodiment 1. Normally, exposure is performed multiple times within a single frame when a distance to object190is to be measured. In Embodiment 3, when exposure is repeated after reset step ST04, the processing proceeds to drive circuit swap step ST05. In drive circuit swap step ST05, select switch signal540is switched, thus switching buffer element112through which a drive signal passes to another buffer element112. When drive circuit swap step ST05is completed, the processing proceeds to light storage start step ST01again. Each time exposure is repeated, drive circuit111through which a drive signal passes is switched to another drive circuit111.

Here, electrode drive wire114includes three types of control wires, namely reset control wire114A, first read control wire114B, and second read control wire114C.

It is assumed that wire swapper510swaps between three types of control wires each time exposure is performed. It is assumed that exposure is performed for a total of (l+m+n) times within one frame, and a drive signal applied to reset control wire114A passes through drive circuit111A in the lth exposure, passes through drive circuit111B in the mth exposure, and passes through drive circuit111C in the nth exposure. It is assumed that a drive signal applied to first read control wire114B passes through drive circuit111B in the lth exposure, passes through drive circuit111C in the mth exposure, and passes through drive circuit111A in the nth exposure. It is assumed that a drive signal applied to second read control wire114C passes through drive circuit111C in the lth exposure, passes through drive circuit111A in the mth exposure, and passes through drive circuit111B in the nth exposure. When Ata denotes a time lag of drive circuit111A, Δtb denotes a time lag of drive circuit111B, and Δtc denotes a time lag of drive circuit111C, measurement distance difference ΔZ1of a pixel that reset control wire114A drives, measurement distance difference ΔZ2of a pixel that first read control wire114B drives, and measurement distance difference ΔZ3of a pixel that second read control wire114C drives are obtained by Expressions (6) to (8) below.

When the number of times exposure is performed in which a drive signal passes through drive circuit111A, the number of times exposure is performed in which a drive signal passes through drive circuit111B, the number of times exposure is performed in which a drive signal passes through drive circuit111C, the number of reset control wires114A, the number of first read control wires114B, and the number of second read control wires114C are all the same, l=m=n, and measurement distance differences ΔZ1, ΔZ2, and ΔZ3are obtained by Expression (9) below.

Thus, measurement distance difference ΔZ1of pixels101that reset control wire114A drives, measurement distance difference ΔZ2of pixels101that first read control wire114B drives, and measurement distance difference ΔZ3of pixels101that second read control wire114C drives are all proportional to (Δta+Δtb+Δtc)/3 resulting from averaging time lag Δta of drive circuit111A, time lag Δtb of drive circuit111B, and time lag Δtc of drive circuit111C. As a result, time lags of reset control wire114A, first read control wire114B, and second read control wire114C are cancelled out, thus achieving high measurement accuracy.

Note thatFIG.8illustrates an example in which wire swapper510dand wire swapper510eare provided on the input side and the output side of drive circuit array110, respectively, and all drive circuits111can be swapped with all drive circuits111. The configuration is not limited thereto, and may be a configuration in which one or more buffer elements112or wires in drive circuit111are swapped. For example, wire swapper510dinFIG.8may be provided in output wires of buffer elements112b, instead of being provided in input wires of buffer elements112a.

InFIG.8, the same circuit as wire swapper510emay be provided instead of wire swapper510d. The same circuit as wire swapper510dmay be provided instead of wire swapper510e.

FIG.7andFIG.8each illustrate an example in which three electrode drive wires114for each column are swapped, but nevertheless the same advantageous effects can be achieved even when two or even four or more electrode drive wires114are swapped.

As described above, in solid-state imaging device200according to Embodiment 3, wire swapper510may include selection circuit530or531that selects a drive circuit that is a swap target, according to a select switch signal.

Summary

As described above with reference to the drawings, solid-state imaging device200according to the embodiment includes photoelectric converter300that converts received light into charge, read electrodes (first read electrode330and second read electrode350) that control reading of charge generated in photoelectric converter300, reset electrode310that controls discharge of charge generated in photoelectric converter300, pixel array100in which photoelectric converters300, the above read electrodes, and reset electrodes310are disposed, read control wires (first read control wire114B and second read control wire114C) that drive the above read electrodes, reset control wire114A that drives reset electrodes310, drive circuits111in each of which buffer elements112in at least two stages are cascaded, and which apply drive pulses to the above read control wires and reset control wire114A and are aligned in columns, and first wire113that short-circuits output wires of buffer elements112in at least two different columns.

With this configuration, drive pulses are applied from drive circuits111through the read control wires and reset control wire114A to electrodes of pixels101disposed in a matrix, and transfer of charge stored in photoelectric converter300is controlled. In drive circuits111, buffer elements112are cascaded, and output wires of buffer elements112in columns are electrically connected by first wire113at low impedance. As a result, potentials at the columns change so as to match, and thus a difference in delay is reduced.

Further, first wire113has a length longer than a side extending parallel to the first wire out of four sides that define an effective region constituted by pixels101, and the more downstream first wire113is provided, the lower impedance of first wire113is. Furthermore, the more downstream stage buffer element112is in, the higher drive capability the buffer element has, and electrode drive wires114are independent from column-to-column.

By first wires113short-circuiting output wires of buffer elements in two or more stages, even if a difference in delay occurs in columns and a potential difference is generated, a period in which a potential difference is generated is short since a difference in delay is small, and buffer element112in a more upstream stage has lower drive capability, and thus less through-current flows. Accordingly, risk of melting a wire and damaging buffer element112can be lowered. In addition, the impedance of first wire113that short-circuits output wires of buffer element112in a more downstream stage is decreased, so that risk of melting a wire can be lowered. As a result, first wire113can reduce a difference in delay of a drive signal for each column caused due to a difference in characteristics of a drive buffer and a difference in parasitic component caused by the layout can be reduced without the need of calibration.

Drive circuit array110includes one or more wire swappers510that swap a wire in drive circuit111with a wire in drive circuit111in a different column, and one or more wire swappers510each include selection circuits530and531that each select columns for which wires are swapped according to a selection switch signal.

Since buffer elements112in two or more stages in different columns are cascaded, the phases of drive signals can be made different, and even if buffer elements cannot be short-circuited in columns, a difference in delay can be reduced. With regard to a difference in delay in columns due to a difference in layout and manufacturing variations of drive circuits111, by swapping paths through which drive signals flow, delay times of different drive signals can be averaged. Utilizing multiple exposure in which TOF is used, selection circuit530can average delay times by changing paths of drive signals during an exposure period, and reduce a difference in delay of drive signals passing through different columns and having different phases.

INDUSTRIAL APPLICABILITY

As described above, the imaging apparatus according to the present disclosure is useful as an imaging apparatus that can reduce a difference in delay of drive signals between columns without the need of calibration, and can achieve high measurement accuracy while an increase in the circuit scale is reduced.