Semiconductor device and formation method

A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

BACKGROUND

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” may generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated.

As scales of the fin width in fin field effect transistors (FinFET) decreases, channel width variations might cause mobility loss. Nano-FETs (e.g., nanosheet FETs, nanowire FETs, or the like) are being studied as an alternative to fin field effect transistors. In a nano-FET, the gate of the transistor is made all around the channel (e.g., a nanosheet channel or a nanowire channel) such that the channel is surrounded or encapsulated by the gate. Such a transistor has the advantage of improving the electrostatic control of the channel by the gate, which also mitigates leakage currents.

FIG.1illustrates an example of nano-FETs (e.g., nanosheet FETs or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures104(e.g., nanosheets, nanowires, nanorings, nanoslabs, or other structures having nano-scale size (e.g., a few nanometers)) over fins102on a substrate100(e.g., a semiconductor substrate), wherein the nanostructures104act as channel regions for the GAA-FETs. The nanostructure104may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions106are disposed between adjacent fins102, which may protrude above and from between neighboring isolation regions106. Although the isolation regions106are described/illustrated as being separate from the substrate100, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins102are illustrated as being single, continuous materials with the substrate100, the bottom portion of the fins102and/or the substrate100may comprise a single material or a plurality of materials. In this context, the fins102refer to the portion extending between the neighboring isolation regions106. Gate dielectrics110are over top surfaces of the fins102and along top surfaces, sidewalls, and bottom surfaces of the nanostructures104. Gate electrodes112are over the gate dielectrics110. Epitaxial source/drain regions108are disposed on the fins102on opposing sides of the gate dielectric layers110and the gate electrodes112.

In various embodiments of the present disclosure, interbridge channels (interchangeably referred to as bridging channels, bridging portions or bridging structures in some embodiments of the present disclosure) are added between neighboring nanostructure channels, so as to improve on-current of nano-FETs. Moreover, in various embodiments of the present disclosure, the interbridge channels are localized to a periphery region or off-center region of the nanostructure channels, which can provide an improved on-current enhancement than forming the interbridge channels localized to a center region of the nanostructure channels.

FIG.2illustrates an example of a nano-FET having off-center interbridge channels in a three-dimensional view, in accordance with some embodiments. The nano-FET comprises a channel structure203including alternating nanostructure channels204A-C (collectively referred to as nanostructure channels204) and interbridge channels205A-205B (collectively referred to as interbridge channels205) on a substrate200. The substrate200may include fins and isolation regions disposed between the adjacent fins, as illustrated inFIG.1. Epitaxial source/drain regions208are disposed on the substrate200on opposing sides of the channel structure203. A gate structure210surrounds the channel structure203, and is separated from the epitaxial source/drain regions208by gate spacers218. The gate structure210includes, for example, a gate dielectric212over the channel structure203, a work function metal layer214over the gate dielectric212, and a fill metal216over the work function metal layer214.

In the channel structure203the nanostructure channels204each have a width W204in a direction perpendicular to a current flow between the epitaxial source/drain regions208(referred to as a current flow direction), and the interbridge channels205each have a width W205in the current flow direction and smaller than the width W204of the nanostructure channels204. The interbridge channels205are localized to a periphery region of the nanostructure channels204, rather than a center region of the nanostructure channels204. In such a configuration, an interbridge channel205forms only a single concave corner C203with a corresponding one of nanostructure channels204. In contrast, if the interbridge channels205are localized to a center region of the nanostructure channels204, an interbridge channel205would form two concave corners with a corresponding one of the nanostructure channels204, as exemplarily illustrated in Condition #2 inFIG.3. It is observed that concave corners in a channel structure may result in a weaker gate electric field (i.e., weaker gate control), which in turn may lead to less conducting charge carriers. Therefore, by localizing the interbridge channels205to the periphery region of the nanostructure channels204, a number of concave corners in the channel structure203can be reduced by half, which in turn results in a stronger gate control and hence more conducting charge carriers, which in turn allows for further increasing in the on-current enhancement, as discussed in greater detail below.

FIG.3illustrate simulation results showing channel charge density in different nano-FETs according to some embodiments of the present disclosure, wherein the channel charge density is shown on the vertical axis inFIG.3, and the gate voltage is shown on the horizontal axis inFIG.3. In Condition #1, the channel structure of the nano-FET includes two separated nanostructure channels NS without an interbridge channel therebetween. In Condition #2, the channel structure of the nano-FET includes two nano structure channels NS and an interbridge channel IB extending from a center region of a lower nanostructure channel to a center region of an upper nanostructure channel. In Condition #3, the channel structure of the nano-FET includes two nanostructure channels NS and an interbridge channel IB extending from a periphery region of a lower nanostructure channel to a periphery region of an upper nanostructure channel. In Conditions #1-3, the channel structures are surrounded by a gate structure including, for example, a gate dielectric GD, a work function metal WFM over the gate dielectric GD, and a fill metal FM over the work function metal WFM. Comparing the channel charge density curve of Condition #2 with the channel charge density curve of Condition #1, it can be observed that, at a same given non-zero gate voltage, the channel charge density of the nano-FET having an interbridge channel IB is greater than the channel charge density of the nano-FET without an interbridge channel. This simulation result shows that the interbridge channel provides on-current enhancement to nano-FETs. Comparing the channel charge density of Condition #3 with that of Condition #2, it can be observed that, at a same given non-zero gate voltage, the channel charge density of the nano-FET having the interbridge channel IB localized to the periphery regions of nanosheet channels NS is greater than the channel charge density of the nano-FET having the interbridge channel IB localized to the center regions of the nanosheet channels NS. This simulation result shows that the on-current enhancement can be further increased by forming the interbridge channel IB at peripheral regions of nanosheet channels NS.

FIG.4illustrates simulation results showing electron density along a width direction WNSof nanostructure channels NS in different nano-FETs according to some embodiments of the present disclosure, wherein the electron density is shown on the vertical axis inFIG.4, and the position along the width direction WNSof nanostructure channels NS is shown on the horizontal axis inFIG.4. In Condition #1, the channel structure of the nano-FET includes two separated nanostructure channels NS without an interbridge channel therebetween. In Condition #2, the channel structure of the nano-FET includes two nanostructure channels NS and an interbridge channel IB localized to center regions of the nanostructure channels NS. In Condition #3, the channel structure of the nano-FET includes two nanostructure channels NS and an interbridge channel IB localized to periphery regions of the nanostructure channels NS. Comparing the electron density curve of Conditions #1-#3, it can be observed that the interbridge channel IB causes electron density reduction, however, the interbridge channel IB localized to periphery regions of nanostructure channels NS results in a smaller electron density reduction than that localized to center regions of nanostructure channels NS.

FIG.5illustrates simulation results showing electron density along a height direction HIB+NSof interbridge channels IB and nanostructure channels NS in different nano-FETs according to some embodiments of the present disclosure, wherein the electron density is shown on the vertical axis inFIG.5, and the position along the height direction HIB+NSis shown on the horizontal axis inFIG.5. Comparing the electron density curve of Condition #3 with that of Condition #2 inFIG.5, it can be observed that the interbridge channel IB localized to periphery regions of nanostructure channels NS results in a higher electron density at opposite ends of the interbridge channel IB than that localized to center regions of nanostructure channels NS.

FIGS.6A-6Dare simulation results showing electron density improvement ratio of a nano-FET in Condition #3 to a nano-FET in Condition #2 according to some embodiments of the present disclosure, wherein WIBis a width of interbridge channels IB, WNSis a width of nanostructure channels NS, tNSis a thickness of nanostructure channels NS, and HIBis a height of interbridge channels IB. In some embodiments, W1is in a range from about 14 nm to about 16 nm, e.g., about 15 nm; H1is in a range from about 19 nm to about 21 nm, e.g., about 20 nm; W2is in a range from about 24 nm to about 26 nm, e.g., about 25 nm; H2is in a range from about 29 nm to about 31 nm, e.g., about 30 nm. In some embodiments, A nm is less than B nm, and B nm is less than C nm. By way of example and not limitation, A nm is in a range from about 4 nm to about 6 nm, e.g., about 5 nm; B nm is in a range from about 6 nm to about 8 nm, e.g., about 7 nm; and C nm is in a range from about 9 nm to about 11 nm, e.g., about 10 nm.

In Condition #2 the channel structure of the nano-FET includes two nanostructure channels NS and one interbridge channel IB localized to center regions of the nanostructure channels NS, and in Condition #3 the channel structure of the nano-FET includes two nanostructure channels NS and one interbridge channel IB localized to periphery regions of the nanostructure channels NS. Simulation results inFIGS.6A-6Dshow that the narrower the interbridge channel width WIB, the more carriers are generated in the nano-FETs. Simulation results inFIGS.6A-6Dfurther show that the interbridge channel IB localized to periphery regions of nanostructure channels NS results in higher electron density in the channel structure than that localized to center regions of nanostructure channels NS. Simulation results inFIGS.6A-6Dalso show that the thicker the nanostructure channel thickness tNS, the more carriers are generated in the nano-FETs, due to an increased effective transistor gate width (Weff) resulting from the thickened nanostructure channels.

FIGS.7A-7Dare simulation results showing electron density improvement ratio of a nano-FET in Condition #5 to a nano-FET in Condition #4 according to some embodiments of the present disclosure, wherein WIBis a width of interbridge channels, WNSis a width of nanostructure channels, tNSis a thickness of nanostructure channels, and HIBis a height of interbridge channels. In some embodiments, W1is in a range from about 14 nm to about 16 nm, e.g., about 15 nm; H1is in a range from about 19 nm to about 21 nm, e.g., about 20 nm; W2is in a range from about 24 nm to about 26 nm, e.g., about 25 nm; H2is in a range from about 29 nm to about 31 nm, e.g., about 30 nm. In some embodiments, A nm is less than B nm, and B nm is less than C nm. By way of example and not limitation, A nm is in a range from about 4 nm to about 6 nm, e.g., about 5 nm; B nm is in a range from about 6 nm to about 8 nm, e.g., about 7 nm; and C nm is in a range from about 9 nm to about 11 nm, e.g., about 10 nm.

In Condition #4 the channel structure of the nano-FET includes alternating three nanostructure channels NS and two interbridge channel IB localized to center regions of the nanostructure channels NS, and in Condition #5 the channel structure of the nano-FET includes alternating three nanostructure channels NS and two interbridge channel IB localized to periphery regions of the nanostructure channels NS. Simulation results inFIGS.7A-7Dshow that the interbridge channels IB localized to periphery regions of nanostructure channels NS result in an improvement in channel electron density by about 5% to about 12%, as compared to that localized to center regions of nanostructure channels NS.

In some embodiments, the interbridge channel width WIBof the interbridge channels IB is in a range from about 2 nm to about 10 nm. If the interbridge channel width WIBis excessively large (e.g., larger than about 10 nm), a longer transistor gate length may be employed for avoiding short channel effects, which in turn may cause a negative impact on device down-scaling. If the interbridge channel width WIBis excessively small (e.g., smaller than about 2 nm), surface roughness on sidewalls of the interbridge channels may be increased, which in turn may cause mobility degradation and reduce the on-current provided by the interbridge channels. In some embodiments, the interbridge channel height HIBof the interbridge channels IB in a range from about 10 nm to about 200 nm. If the interbridge channel height HIBis excessively small (e.g., smaller than about 10 nm), the interbridge channels may provide insufficient on-current enhancement. If the interbridge channel height HIBis excessively large (e.g., larger than about 200 nm), the increased device vertical footprint may increase the gate parasitic capacitance and thus degrade the device performance. Moreover, if the interbridge channel height HIBis excessively large (e.g., larger than about 200 nm), it may be challenging to form the overly high interbridge channels by etching process, which will be described in greater detail below.

Although the interbridge channels in the channel structure in Conditions #4-5 are illustrated as having substantially the same width, the interbridge channels may have different widths in some other embodiments.FIG.8Aillustrates a cross-sectional view of a channel structure having interbridge channels with different widths. InFIG.8A, the channel structure includes alternating nanostructure channels NS1-NS3and interbridge channels IB1and IB2surrounded by a gate structure. The interbridge channel IB2is disposed above the interbridge channel IB1and has a width W1IB2smaller than a width WIB1of the interbridge channel IB1. Width difference between interbridge channels may affect the electron density in the channel structure, as illustrated inFIG.8B, which shows simulation results of electron density in nano-FETs having various interbridge channel width differences, in accordance with some embodiments of the present disclosure. InFIG.8B, WNSis a width of nanostructure channels NS1-NS3, tNSis a thickness of nanostructure channels NS1-NS3, and HIBis a height of interbridge channels IB1and IB2. In some embodiments, W1is in a range from about 14 nm to about 16 nm, e.g., about 15 nm; H1is in a range from about 19 nm to about 21 nm, e.g., about 20 nm. In some embodiments, A nm is less than B nm, and B nm is less than C nm. By way of example and not limitation, A nm is in a range from about 4 nm to about 6 nm, e.g., about 5 nm; B nm is in a range from about 6 nm to about 8 nm, e.g., about 7 nm; and C nm is in a range from about 9 nm to about 11 nm, e.g., about 10 nm.

As illustrated inFIG.8B, when the lower interbridge channel width WIB1is C nm (e.g., about 10 nm), the less the upper interbridge channel width WIB2, the higher the electron density. On the other hand, when the upper interbridge channel width WIB2is A nm (e.g., about 5 nm), the less the lower interbridge channel width WIB1, the higher the electron density.

FIG.9Ashows simulation results showing on-current improvement ratio, sub-threshold swing (SS) improvement ratio, and an improvement in on-current/off-current ratio of a nano-FET in Condition #6 to a nano-FET in Condition #7. In Condition #6, as illustrated inFIG.9B, the channel structure of the nano-FET includes alternating five nanostructure channels NS1-NS5and four interbridge channels IB1-IB4localized to periphery regions of the nanostructure channels NS1-NS5. In Condition #7, as illustrated inFIG.9B, the channel structure of the nano-FET includes alternating five nanostructure channels NS1-NS5and four interbridge channels IB1-IB4localized to center regions of the nanostructure channels NS1-NS5. The interbridge channels IB1-IB4have widths WIB1, WIB2, WIB3, and WIB4, respectively. InFIG.9A, ΔIB can be expressed as: ΔWIB=WIBn-1−WIBn, e.g., WIB1−WIB2, WIB2−WIB3, or WIB3−WIB4. In some embodiments, W2is in a range from about 24 nm to about 26 nm, e.g., about 25 nm; H1is in a range from about 19 nm to about 21 nm, e.g., about 20 nm; A nm is in a range from about 4 nm to about 6 nm, e.g., about 5 nm; D nm is in a range from about 0.5 nm to about 1.5 nm, e.g., about 1 nm; and E nm is in a range from about 1.5 nm to about 2.5 nm, e.g., about 2 nm.

On-current simulation results inFIG.9Ashow that increasing in interbridge channel width difference (ΔWIB) results in increased on-current (Ion) in both Conditions #6 and #7.FIG.9Afurther shows that the interbridge channels IB1-IB4localized to periphery regions of nanostructure channels NS1-NS5(i.e., Condition #6) can provide a higher on-current than that localized to center regions of nanostructure channels NS1-NS5(i.e., Condition #7), regardless of the interbridge channel width difference.

Sub-threshold swing simulation results inFIG.9Ashow that increasing in interbridge channel width difference results in increased sub-threshold swing (SS) in both Conditions #6 and #7.FIG.9Afurther shows that the interbridge channels IB1-IB4localized to periphery regions of nanostructure channels NS1-NS5(i.e., Condition #6) can provide a higher SS than that localized to center regions of nanostructure channels NS1-NS5(i.e., Condition #7), regardless of the interbridge channel width difference.

Ion/Ioffratio simulation results inFIG.9Ashow that the interbridge channels IB1-IB4localized to periphery regions of nanostructure channels NS1-NS5(i.e., Condition #6) can provide a higher Ion/Ioffratio than that localized to center regions of nanostructure channels NS1-NS5(i.e., Condition #7), regardless of the interbridge channel width difference.FIG.9Afurther shows that increasing in interbridge channel width difference results in a degraded Ion/Ioffratio in both Conditions #6 and #7. This may be attributed to an unduly large width in the bottom interbridge channel IB1. The unduly wide interbridge channel IB1may be attributed to under-etching during SiGe selective etching for forming the interbridge channels. By localizing the interbridge channels to periphery regions of the nanostructure channels, interbridge channel width difference can be reduced by half, as compared to localizing the interbridge channels to center regions of the nanostructure channels, because only single side of the interbridge channels is etched, which will be discussed in greater detail below. As a result, it is easier to control the interbridge channel width difference by localizing the interbridge channels to periphery regions of nanostructure channels, which in turn aids in prevent an unduly large width in the bottom interbridge channel IB1. In some embodiments, the interbridge channel width difference (ΔWIB) is less than about 10 nm. Excessively large interbridge channel width (e.g., greater than about 10 nm) may result in increased short channel effects.

FIGS.10A-22Bare top views and cross-sectional views of intermediate stages in the manufacturing of a nano-FET, in accordance with some embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.10A-22B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.10Ais a top view of an intermediate stage in manufacturing of a nano-FET, andFIG.10Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.10A. InFIGS.10A and10B, a semiconductor substrate300is illustrated. In some embodiments, the substrate300may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layered or gradient substrate, or the like. The substrate300may include a semiconductor material, such as an elemental semiconductor including Si and Ge; a compound or alloy semiconductor including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; a combination thereof, or the like. The substrate100may be doped or substantially un-doped. In a specific example, the substrate100is a bulk silicon substrate, which may be a wafer.

The substrate300may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

Impurity ions (interchangeably referred to as dopants) are implanted into the silicon substrate300to form a well region (not shown). The ion implantation is performed to prevent a punch-through effect. The substrate300may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants are, for example, boron (BF2) for an n-type nano-FET and phosphorus for a p-type nano-FET.

FIGS.10A and10Balso illustrate a layer stack is formed over the substrate300. A first semiconductor layer (first interbridge layer)302A is formed over the substrate300. A second semiconductor layer (first nanostructure layer)304A is formed over the first semiconductor layer302A. Another first semiconductor layer (second interbridge layer)302B is formed over the second semiconductor layer304A. Another second semiconductor layer (second nanostructure layer)304B is formed over the another first semiconductor layer302B. Another first semiconductor layer (third interbridge layer)302C is formed over the second semiconductor layer304B. Another second semiconductor layer (third nanostructure layer)304C is formed over the first semiconductor layer302C.

In some embodiments, the first and second semiconductor layers are alternately stacked such that there are more than two layers each of the first and second semiconductor layers. In some embodiments, each of the second semiconductor layers, which become nanosheets, nanowires, nanoslabs or nanorings, can be formed of different materials. In some embodiments, the lattice constant of the second semiconductor layers is greater than the lattice constant of the first semiconductor layers. In other embodiments, the lattice constant of the second semiconductor layers is smaller than the lattice constant of the first semiconductor layers.

In some embodiments, the first and second semiconductor layers are made of different materials selected from the group consisting of Si, Ge, SiGe, GeSn, Si/SiGe/Ge/GeSn, SiGeSn, and combinations thereof. In some embodiments, the first and second semiconductor layers are formed by epitaxy. In some embodiments, the SiGe is Si1-xGex, where 0.1≤x≤0.9.

In some embodiments, the first semiconductor layers302A-302C (collectively referred to as first semiconductor layers302) are formed of a first semiconductor material. In some embodiments, the first semiconductor material includes a first Group IV element and a second Group IV element. The Group IV elements are selected from the group consisting of C, Si, Ge, Sn, and Pb. In some embodiments, the first Group IV element is Si and the second Group IV element is Ge. In certain embodiments, the first semiconductor material is Si1-xGex, wherein 0.1≤x≤0.9. In some embodiments, the first semiconductor layers302have different germanium atomic concentrations. For example, the bottommost first semiconductor layer302A may have a higher germanium concentration than upper first semiconductor layers302B and302C, which in turn allows for removing the bottommost first semiconductor layer302A while leaving portions of upper first semiconductor layers302B and302C to serve as interbridge channels in a following SiGe selective etching process. In some embodiments, the topmost first semiconductor layer302C has a higher germanium concentration than the middle first semiconductor layer302B, which in turn allows for forming a wider interbridge channel between nanostructure layers302B and302C, and a narrower interbridge channel above the nanostructure layer302C in the following SiGe selective etching process.

In some embodiments, the second semiconductor layers304A-304C (collectively referred to as second semiconductor layers304) are formed of a second semiconductor material. In some embodiments, the second semiconductor material is silicon. Stated another way, the second semiconductor material is substantially free of germanium in some embodiments. In some embodiments, the second semiconductor material includes a first Group IV element and a second Group IV element. In some embodiments, the first Group IV element is Si and the second Group IV element is Ge. In some embodiments, the amounts of the first Group IV element and second Group IV element are different in the second semiconductor material than in the first semiconductor material. In some embodiments, the amount of Ge in the first semiconductor material is greater than the amount of Ge in the second semiconductor material. In some other embodiments, the second semiconductor material includes a Group III element and a Group V element.

The first semiconductor layers302and second semiconductor layers304may be formed by one or more epitaxy or epitaxial (epi) processes. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and/or other suitable processes. Thickness of the first semiconductor layers302depends on a target interbridge channel height. For example, the thickness of first semiconductor layers302is in a range from about 10 nm to about 200 nm. If the thickness of first semiconductor layers302is excessively small (e.g., smaller than about 10 nm), the resulting interbridge channels may provide insufficient on-current enhancement. If the thickness of first semiconductor layers302is excessively large (e.g., larger than about 200 nm), the increased device vertical footprint may increase the gate parasitic capacitance and thus degrade the device performance. Moreover, if the thickness of first semiconductor layers302is excessively large (e.g., larger than about 200 nm), it may be challenging to form the overly high interbridge channels by a following SiGe selective etching process.

In some embodiments, the thickness of the second semiconductor layers304is less than the thickness of the first semiconductor layers302. For example, the thickness t1 of the first semiconductor layers302and the thickness t2 of the second semiconductor layers304are related as t1/t2=2 to 20.

After the epitaxial growth process of the layer stack is complete, a patterned mask306is formed over the topmost second semiconductor layer304C. The second semiconductor layer304C, followed by patterning the mask layer into the patterned mask306using suitable photolithography and etching techniques. The patterned mask306includes silicon nitride (Si3N4), silicon oxide, the like, or combinations thereof.

After forming the patterned mask306, a patterning process is performed on the layer stack to form a fin structure FS, as illustrated inFIGS.10A and10B. In some embodiments, the patterning process comprises one or more etching processes, where the patterned mask layer306is used as an etch mask. The one or more etching processes may include wet etching processes, anisotropic dry etching processes, or combinations thereof, and may use one or more etchants that etch the first and second semiconductor layers302,304at a faster etch rate than it etches the patterned mask layer306. Although the fin structure FS illustrated inFIG.10Bhas vertical sidewalls, the etching process may lead to tapered sidewalls in some other embodiments.

Once the fin structure FS has been formed, shallow trench isolation (STI) regions308(interchangeably referred to as isolation insulation layer) are formed around a lower portion of the fin structure FS are illustrated inFIGS.10A and10B. STI regions308may be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fin structures FS and then recessing the top surface of the dielectric materials. The dielectric materials of the STI regions308may be deposited using a high density plasma chemical vapor deposition (HDP-CVD), a low-pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), a flowable CVD (FCVD), spin-on coating, and/or the like, or a combination thereof. After the deposition, an anneal process or a curing process may be performed. In some cases, the STI regions308may include a liner such as, for example, a thermal oxide liner grown by oxidizing the silicon surface or silicon germanium surface of the fin structure FS and the substrate100. The recess process may use, for example, a planarization process (e.g., a chemical mechanical polish (CMP)) followed by a selective etch process (e.g., a wet etch, or dry etch, or a combination thereof) that may recess the top surface of the dielectric materials in the STI regions308such that an upper portion of the fin structure FS protrudes from surrounding insulating STI regions308.

FIG.11Ais a top view of an intermediate stage in manufacturing of a nano-FET, andFIG.11Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.11A. InFIGS.11A and11B, a dielectric wall310is formed on a first longitudinal side LS1of the fin structure FS but not on a second longitudinal side LS2of the fin structure FS opposing the first longitudinal side LS1. The dielectric wall310can be formed by, for example, depositing a dielectric layer over the substrate300, followed by patterning the dielectric layer into the dielectric wall310using suitable photolithography and etching techniques. For example, a photoresist material is first spin-coated on the dielectric layer, and then irradiated (exposed) and developed to remove portions of the photoresist material. Then, the dielectric layer is etched using the patterned photoresist as an etch mask. The etching step may be dry etching, wet etching, or combinations thereof. In an example photolithography step, a photomask or reticle (not shown) may be placed above the photoresist material, which may then be exposed to a radiation beam which may be ultraviolet (UV) or an excimer laser such as a Krypton Fluoride (KrF) excimer laser, or an Argon Fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and decrease the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove either the exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used. In some embodiments, the dielectric wall310includes silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable dielectric materials.

FIG.12Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.12Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.12A, andFIG.12Cis a cross-sectional view corresponding to the line C-C′ illustrated inFIG.12A. InFIGS.12A-12C, once the dielectric wall310has been formed, a dummy gate structure312is formed over the fin structure FS. The dummy gate structure312has a lengthwise direction perpendicular to the lengthwise direction of the fin structure FS. The dummy gate structure312includes a dummy gate dielectric layer and a dummy gate electrode layer over the dummy gate dielectric layer. The dummy gate dielectric layer may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode layer can be deposited over the dummy dielectric layer and then planarized, such as by a CMP process. The dummy gate electrode layer may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (poly silicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate electrode layer may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or the like. The dummy gate dielectric layer and the dummy gate electrode layer are patterned to form the dummy gate structure312. In some embodiments, the fin mask306is removed from the topmost second semiconductor layer304C before forming the dummy gate structure312.

FIGS.12A-12Calso illustrate formation of gate spacers314on sidewalls of the dummy gate structure312. In some embodiments of the spacer formation step, a spacer material layer is deposited on the substrate300. The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, a spacer material layer314is disposed conformally on top and sidewalls of the dummy gate structure312. The spacer material layer314may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. The spacer material layer314may be formed by depositing a dielectric material over the gate structure312using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. An anisotropic etching process is then performed on the deposited spacer material layer314to expose portions of the fin structure FS not covered by the dummy gate structure312(e.g., in source/drain regions of the fin structure FS). Portions of the spacer material layer directly above the dummy gate structure312may be completely removed by this anisotropic etching process. Portions of the spacer material layer on sidewalls of the dummy gate structure312may remain, forming gate sidewall spacers, which is denoted as the gate spacers314, for the sake of simplicity.

FIG.13Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.13Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.13A,FIG.13Cis a cross-sectional view corresponding to the line C-C′ illustrated inFIG.13A, andFIG.13Dis a cross-sectional view corresponding to the line D-D′ illustrated inFIG.13A. InFIGS.13A-13D, exposed portions of the fin structure FS that extend laterally beyond the gate spacers314(e.g., in source/drain regions of the fin structure FS) are recessed by using, for example, an anisotropic etching process that uses the dummy gate structure312and the gate spacers314as an etch mask. In some embodiments, the anisotropic etching may be performed by a dry chemical etch with a plasma source and a reaction gas. The plasma source may be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source or the like, and the reaction gas may be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), the like, or combinations thereof.

FIG.14Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.14Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.14A,FIG.14Cis a cross-sectional view corresponding to the line C-C′ illustrated inFIG.14A, andFIG.14Dis a cross-sectional view corresponding to the line D-D′ illustrated inFIG.14A. InFIGS.14A-14D, an interbridge mask316is formed on a sidewall of the dielectric wall310and over the recessed portion of the fin structure (e.g., in source/drain regions of the fin structure). The interbridge mask316can be formed by, for example, depositing a dielectric layer over the structure as illustrated inFIGS.13A-13D, followed by an anisotropic etching process to remove horizontal portions of the dielectric layer while leaving a vertical portion on the sidewall of the dielectric wall310to serve as the interbridge mask316.

FIG.15Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.15Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.15A,FIG.15Cis a cross-sectional view corresponding to the line C-C′ illustrated inFIG.15A, andFIG.15Dis a cross-sectional view corresponding to the line D-D′ illustrated inFIG.15A. InFIGS.15A-15D, a selective etching process is performed to selectively etch the first semiconductor layers302exposed at outer sidewalls of the gate spacers314. This etching step forms a sidewall recess319A below the second semiconductor layer304A, a sidewall recess319B between the second semiconductor layers304A and304B, and a sidewall recess319C between the second semiconductor layers304B and304C. In some embodiments, the etching step selectively etches the first semiconductor layers302at a faster etch rate than it etches the second semiconductor layers304. Therefore, the second semiconductor layers304may remain substantially intact after the selective etching step is complete.

In embodiments in which the first semiconductor layers302include, e.g., SiGe, and the second semiconductor layers304include, e.g., Si or SiC, fluorine-based etchant that can form fluorine radicals (e.g., NF*, NF2*, and F*) may be used to selectively etch the SiGe layers302. For example, this SiGe selective etching step may be an isotropic dry etching process using a fluorine-containing gas (e.g., NF3or CF4) as a main precursor gas and performed at a flow rate of the fluorine-containing gas in a range from about 1 standard cubic centimeters per minute (sccm) to about 200 sccm (e.g., 7 ccmm), at a chamber temperature in a range from about 0 degrees Centigrade to about 200 degrees Centigrade (e.g., 14 degrees Centigrade), and at a pressure in a range from about 1 torr to about 100 torr (e.g., 7 torr). The SiGe selective etching step performed using the foregoing conditions can result in a SiGe etch rate in a range from about 10 nm/min to about 20 nm/min (e.g., 15 nm/min), and an etch rate ratio of SiGe to Si in a range from about 40:1 to about 100:1. Etching process conditions out of the above selected ranges may result in unduly high SiGe etch rate, unduly low etching selectivity of SiGe over Si, and/or non-negligible surface roughness on sidewalls of the first semiconductor layers302.

In some embodiments, the etching step also etches the first semiconductor layer302A at a faster etch rate than it etches the first semiconductor layers302B and302C, which in turn allows for leaving end portions318B and318C of the first semiconductor layers302B and302C below the gate spacers314, while not leaving an end portion of the first semiconductor layer302A below the gate spacers314. These end portions318B and318C can act as parts of interbridge channels connecting subsequently formed source/drain epitaxial structures. In some embodiments, the interbridge mask316serves to protect the end portions318B and318C of the first semiconductor layers302B and302C from being etched in a direction perpendicular to the outer sidewalls of the gate spacers314.

In some embodiments where the first semiconductor layer302A has a higher germanium atomic concentration than the first semiconductor layers302B and302C, the fluorine-based etchant can etch the first semiconductor layer302A at a faster etch rate, because in the etching step using the fluorine-based etchant, the SiGe etch rate increases as the germanium atomic percentage increases. In some embodiments where the first semiconductor layers302B and302C have substantially the same germanium concentration, the end portions318B and318C below the gate spacers314have substantially the same width as illustrated inFIG.15C. In some embodiments where the first semiconductor layer302C has a higher germanium atomic concentration than the first semiconductor layer302B, the end portion318C of the first semiconductor layer302C has a smaller width than the end portion318B of the first semiconductor layer302B because of the etch rate difference resulting from the fluorine-based etchant, which in turn allows for a width difference in the interbridge layers as illustrated inFIG.8A.

FIG.16Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.16Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.16A,FIG.16Cis a cross-sectional view corresponding to the line C-C′ illustrated inFIG.16A, andFIG.16Dis a cross-sectional view corresponding to the line D-D′ illustrated inFIG.16A. InFIGS.16A-16D, the interbridge mask316is removed, for example, by using a selective etching process that etches the dielectric material of the interbridge mask316at a faster etch rate than it etches other materials on the substrate300. Once the interbridge mask316has been removed, end portions318B and318C of the first semiconductor layers302B and302C get exposed at outer sidewalls of the gate spacers314.

FIG.17Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.17Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.17A,FIG.17Cis a cross-sectional view corresponding to the line C-C′ illustrated inFIG.17A, andFIG.17Dis a cross-sectional view corresponding to the line D-D′ illustrated inFIG.17A. InFIGS.17A-17D, inner spacers320A,320B, and320C (collectively referred to as inner spacers320) are formed in the sidewall recesses319A,319B, and319C, respectively. The inner spacers320may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated inFIGS.16A-16D. The inner spacers320act as isolation features between subsequently formed source/drain epitaxial structures and gate structure. The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the inner spacers320.

FIG.18Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.18Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.18A. InFIGS.18A-18B, epitaxial source/drain structures322are formed on the recessed portions of the fin structure. In some embodiments, the source/drain regions322may exert stress on the nanostructure layers304and end portions318B and318C of the interbridge layers, thereby improving device performance. As illustrated inFIG.18A, the epitaxial source/drain structures322are formed such that each dummy gate structure312is disposed between respective neighboring pairs of the epitaxial source/drain structures322. In some embodiments, the gate spacers314are used to separate the epitaxial source/drain structures322from the dummy gate structure312, and the inner spacers320are used to separate the epitaxial source/drain structures322from portions of the interbridge layers302B and302C by an appropriate lateral distance, so that the epitaxial source/drain structures322do not short out with a subsequently formed gate of the resulting nano-FET that will take the place of the portions of the interbridge layers302B and302C.

In some embodiments, the epitaxial source/drain structures322may include any acceptable material appropriate for n-type nano-FETs. For example, if the nanostructure layers304are silicon, the epitaxial source/drain structures322may include materials exerting a tensile strain on the nanostructure layers304, such as silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source/drain structures322may include any acceptable material appropriate for p-type nano-FETs. For example, if the nanostructure layers304are silicon, the epitaxial source/drain structures322may comprise materials exerting a compressive strain on the nanostructure layers304, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain structures322may have facets as illustrated inFIG.18B.

The epitaxial source/drain structures322may be implanted with dopants to form source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1017atoms/cm3and about 1×1022atoms/cm3in some embodiments of the present disclosure. The p-type impurity includes, for example, boron, boron fluoride, indium, or the like. The n-type impurity includes, for example, phosphorus, arsenic, antimony, or the like. In some embodiments, the epitaxial source/drain structures322may be in situ doped during growth.

FIG.19Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.19Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.19A. InFIGS.19A-19B, the dummy gate structure312is removed in one or more etching steps, so that a gate trench GT is formed between corresponding gate spacers314. In some embodiments, an interlayer dielectric (ILD) layer is formed over the epitaxial source/drain structures322before removing the dummy gate structure312. In some embodiments, the dummy gate structure312is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate structure312at a faster rate than the gate spacers314and the ILD layer. The gate trench GT exposes and/or overlies the nanostructure layers304and the interbridge layers302.

FIG.20Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.20Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.20A. InFIGS.20A-20B, a selective etching process is performed to selectively etch the interbridge layers302exposed in the gate trench GT between the gate spacers314. This etching step forms an opening325A below the nanostructure layer304A, an opening325B between the nanostructure layers304A and304B, and an opening325C between the nanostructure layers304B and304C. In some embodiments, the etching step selectively etches the interbridge layers302at a faster etch rate than it etches the nanostructure layers304. Therefore, the nanostructure layers304may remain substantially intact after the selective etching step is complete.

In embodiments in which the interbridge layers302include, e.g., SiGe, and the nanostructure layers304include, e.g., Si or SiC, fluorine-based etchant that can form fluorine radicals (e.g., NF*, NF2*, and F*) may be used to selectively etch the SiGe layers302. For example, this SiGe selective etching step may be an isotropic dry etching process using a fluorine-containing gas (e.g., NF3or CF4) as a main precursor gas and performed at a flow rate of the fluorine-containing gas in a range from about 1 standard cubic centimeters per minute (sccm) to about 200 sccm (e.g., 7 ccmm), at a chamber temperature in a range from about 0 degrees Centigrade to about 200 degrees Centigrade (e.g., 14 degrees Centigrade), and at a pressure in a range from about 1 torr to about 100 torr (e.g., 7 torr). The SiGe selective etching step performed using the foregoing conditions can result in a SiGe etch rate in a range from about 10 nm/min to about 20 nm/min (e.g., 15 nm/min), and an etch rate ratio of SiGe to Si in a range from about 40:1 to about 100:1. Etching process conditions out of the above selected ranges may result in unduly high SiGe etch rate, unduly low etching selectivity of SiGe over Si, and/or non-negligible surface roughness on sidewalls of the interbridge layers302.

In some embodiments, the etching step also etches the interbridge layer302A at a faster etch rate than it etches the interbridge layers302B and302C, which in turn allows for leaving portions324B and324C of the interbridge layers302B and302C between the gate spacers314, while not leaving a portion of the interbridge layer302A between the gate spacers314. These remaining portions324B and324C bridge the nanostructure layers304A-304C and thus collectively form an E-shaped semiconductor channel structure that allows a current flow between the epitaxial source/drain structures322. The remaining portions324B and324C can thus be referred to as interbridge channels324B and324C (collectively referred to as324), and the nanostructure layers304A-304C can be referred to as nanostructure channels304A-304C (collectively referred to as304).

InFIG.20B, the E-shaped semiconductor channel structure includes alternately stacking nanostructure channels (i.e., first semiconductor layers)304and interbridge channels (i.e., second semiconductor layers)324. Central axes CA2of the interbridge channels324are laterally offset from central axes CA1of the nano structure channels304. In some embodiments, the interbridge channels324non-overlap with the central axes CA1of the nanostructure channels304. The interbridge channels324have a smaller width than the nanostructure channels304. In some embodiments, the width of the interbridge channels324is less than half a width of the nanostructure channels304. In some embodiments, the nanostructure channels304have opposite first and second side surfaces3041and3042, the interbridge channels324have opposite third and fourth side surfaces3241and3242. The first side surfaces3041of the nanostructure channels304are aligned with the third side surfaces3241of the interbridge channels324. The fourth side surfaces3242of the interbridge channels324are laterally set back from the second side surfaces3042of the nanostructure channels304. The interbridge channels324are made of a different material than the nanostructure channels304. For example, the interbridge channels324are germanium-containing semiconductor layers (e.g., SiGe layers), and the nanostructure channels304are germanium-free semiconductor layers (e.g., Si layers). Therefore, the interbridge channels324have a greater germanium atomic percentage than the nanostructure channels304.

In some embodiments where the interbridge layer302A has a higher germanium atomic concentration than the interbridge layers302B and302C, the fluorine-based etchant can etch the interbridge layer302A at a faster etch rate, because in the etching step using the fluorine-based etchant, the SiGe etch rate increases as the germanium atomic percentage increases. In some embodiments where the interbridge layers302B and302C have substantially the same germanium concentration, the resultant interbridge channels324B and324C between the gate spacers314have substantially the same width as illustrated inFIG.20B. In some embodiments where the interbridge layer302C has a higher germanium atomic concentration than the interbridge layer302B, the resultant interbridge channel324C has a smaller width than the resultant interbridge channel324B because of the etch rate difference resulting from the fluorine-based etchant, which in turn allows for a width difference in the interbridge channels as illustrated inFIG.8A. In that case, the interbridge channels324B and324C have misaligned side surfaces3242. In some embodiments where the nanostructure channels304have substantially the same width, a width difference between the interbridge channels324is greater than a width difference between the nanostructure channels304.

In some embodiments, both the channel formation step as illustrated inFIGS.20A-20Band the previous sidewall recessing step as illustrated inFIGS.15A-15Duse a selective etching process that etches the interbridge layers302(e.g., SiGe) at a faster etch rate than etching the nanostructure layers304(e.g., Si), and therefore these two steps may use the same etchant chemistry (e.g., fluorine-based etchant) in some embodiments. In this case, the etching time/duration of the channel formation step as illustrated inFIGS.20A-20Bmay be longer than the etching time/duration of the previous sidewall recessing step as illustrated inFIGS.15A-15D.

FIG.21Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.21Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.21A. InFIGS.21A-21B, the dielectric wall310is removed, for example, by using a selective etching process that etches the dielectric material of the dielectric wall310at a faster etch rate than it etches the semiconductor materials of the nanostructure channels304and interbridge channels324.

In some embodiments where the dielectric wall310is made of silicon oxide (SiO2), the silicon oxide wall310can be removed using a cyclic process including one or more repetitions of a plasma treatment step and an annealing step. For example, it may perform a plasma treatment step followed by an annealing step, and then repeats the plasma treatment step and the annealing step. The plasma treatment step serves to selectively etch silicon oxide, and the annealing step serves to remove solid byproducts resulting from the plasma treatment step. In the plasma treatment step the substrate300having the structure as illustrated inFIGS.20A-20Bis loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a gaseous mixture of a NF3gas and a NH3gas, at a flow rate ratio of NF3gas to NH3gas in a range from about 2 to about 100, at a temperature in a range from about 0 degrees Centigrade to about 50 degrees Centigrade (e.g., 35 degrees Centigrade), and at a pressure in a range from about 1 torr to about 100 torr. The annealing temperature of the annealing step is in a range from about 100 degrees Centigrade to about 200 degrees Centigrade (e.g., greater than 100 degrees Centigrade). The SiO2selective etching process using the foregoing conditions has a high selectivity against semiconductor materials (e.g., Si and SiGe), which in turn results in no or negligible loss in the nanostructure channels304and the interbridge channels324. In some embodiments where the STI regions308are made of silicon oxide, the etching time/duration of the SiO2selective etching process is controlled to prevent over-etching the STI regions308, which in turn results in a no or negligible loss in the STI regions308. In some embodiments, before the SiO2selective etching process, a patterned mask may be formed over portions of the STI regions308not covered by the dielectric wall310, so as to protect these portions of STI regions308from being damaged by the SiO2selective etching process.

FIG.22Ais a top view of an intermediate stage in manufacturing of a nano-FET,FIG.22Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.22A. InFIGS.22A-22B, replacement gate structure326is formed in the gate trench GT between the gate spacers314to surround the nanostructure channels304and interbridge channels324suspended between the gate spacers314. The gate structure326may be the final gate of a nano-FET. The final gate structure may be a high-k/metal gate stack, however other compositions are possible. In some embodiments, each of the gate structures326forms the gate associated with the multi-channels provided by the nanostructure channels304and interbridge channels324. For example, the high-k/metal gate structure326is formed within the openings325(as illustrated inFIG.21B) provided by etching the interbridge layers. In various embodiments, the high-k/metal gate structure326includes a gate dielectric layer328formed around the nanostructure channels304and interbridge channels324, and a gate metal330formed around the gate dielectric layer328. The gate metal330may include one or more work function metal layers formed around the gate dielectric layer328, and a fill metal formed around the one or more work function metal layers and filling a remainder of gate trench GT.

In some embodiments, the gate dielectric layer328includes an interfacial layer (e.g., silicon oxide layer) and a high-k gate dielectric layer over the interfacial layer. High-k gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The work function metal layer and/or fill metal layer used within the gate metal330may include a metal, metal alloy, or metal silicide. Formation of the high-k/metal gate (HKMG) structure326may include depositions to form various gate materials, and one or more CMP processes to remove excessive gate materials.

In some embodiments, the interfacial layer of the gate dielectric layer328may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer of the gate dielectric layer328may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer328may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof.

The work function metal layer in the gate metal330may include work function metals to provide a suitable work function for the high-k/metal gate structures326. For an n-type nano-FET, the work function metal layer may include one or more n-type work function metals (N-metal), which has a work function lower than a mid-gap wok function (about 4.5 eV) that is in the middle of the valance band and the conduction band of silicon. The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. On the other hand, for a p-type nano-FET, the work function metal layer may include one or more p-type work function metals (P-metal) having a work function higher than the mid-gap work function of silicon. The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal in the gate metal330may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

FIGS.23A-31Bare top views and cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments of the present disclosure. In general, the nano-FETs fabricated using the steps as illustrated inFIGS.23A-31Bhave separate and symmetric E-shaped channel structures but a shared gate structure surrounding both the E-shaped channel structures. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.23A-31B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.23Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.23Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.23A. InFIGS.23A and23B, a fin structure FS of alternating stacked first semiconductor layers (interbridge layers)402A-402C and second semiconductor layers (nanostructure layers)404A-404C are formed over a substrate400, and STI regions408are formed around a lower portion of the fin structure FS. Material and process details about the substrate400, interbridge layers402A-402C (collectively referred to402), nanostructure layers404A-404C (collectively referred to as404), and the SIT regions408are similar to that of the substrate300, interbridge layers302, nanostructure layers304, and the SIT regions308as discussed previously, and thus they are not repeated for the sake of brevity.

FIG.24Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.24Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.24A. InFIGS.24A and24B, a patterned mask layer409is formed over the substrate400, and then the fin structure is anisotropically etched by using the patterned mask layer409as an etch mask to form a trench409S that breaks the fin structure into two separate fin structures FS1and FS2, wherein the fin structure FS1includes alternating interbridge layers401A-401C and nanostructure layers405A-405C, and the fin structure FS2includes alternating interbridge layers403A-403C and nanostructure layers407A-407C.

The separate interbridge layers401A and403A have the same material because they are both formed from the interbridge layer402A as illustrated inFIG.23B. The separate interbridge layers401B and403B have the same material because they are both formed from the interbridge layer402B. The separate interbridge layers401C and403C have the same material because they are both formed from the interbridge layer402C. In some embodiments, the interbridge layers401A and403A may have a higher germanium atomic concentration than the upper interbridge layers401B-401C and403B-403C, which in turn allows for removing the bottom interbridge layers401A and403A while leaving portions of upper interbridge layers401B-401C and403B-403C to serve as interbridge channels in a following SiGe selective etching process.

The separate nanostructure layers405A and407A have the same material because they are both formed from the nanostructure layer404A. The separate nanostructure layers405B and407B have the same material because they are both formed from the nanostructure layer404B. The separate nanostructure layers405C and407C have the same material because they are both formed from the nanostructure layer404C. In some embodiments, the nanostructure layers405A-405C and407A-407C is silicon and substantially free of germanium.

FIG.25Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.25Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.25A. InFIGS.25A and25B, a dielectric wall410is formed in the trench409S to electrically isolate the fin structures FS1and FS2. The dielectric wall410may be formed by depositing a dielectric material in the trench409S until the trench409S is overfilled, followed by performing a CMP process to remove excessive dielectric material outside the trench409S. In some embodiments, the dielectric wall410includes silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable dielectric materials, and is deposited using, for example, CVD, ALD, PVD, or other suitable deposition techniques.

FIG.26Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.26Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.26A. InFIGS.26A and26B, a dummy gate structure412is formed across both the fin structures FS1and FS2. The dummy gate structure412has a lengthwise direction perpendicular to the lengthwise direction of the fin structures FS1and FS2. Next, gate spacers414are formed on sidewalls of the dummy gate structure412. Material and process details about the dummy gate structure412and gate spacers414are similar to that of the dummy gate structure312and gate spacers314as discussed previously, and thus they are not repeated for the sake of brevity.

FIG.27Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.27Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.27A. InFIGS.27A and27B, portions of the fin structures FS1and FS2extending beyond the gate structure412and gate spacers414are recessed, and then epitaxial source/drain structures416S,416D are formed on the recessed portions of the fin structure FS1, and epitaxial source/drain structures418S,418D are formed on the recessed portions of the fin structure FS2. Epitaxial growth time/duration is controlled such that topmost positions of the epitaxial source/drain structures416S,416D,418S,418D are lower than a topmost position of the dielectric wall410, and thus the epitaxial source structure416S is entirely spaced apart from the epitaxial source structure418S by the dielectric wall410, and the epitaxial drain structure416D is entirely spaced apart from the epitaxial drain structure418D by the dielectric wall410. Material and process details about the epitaxial source/drain structures416S,416D,418S,418D are similar to that of the epitaxial source/drain structures322as discussed previously, and thus they are not repeated for the sake of brevity.

FIG.28Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.28Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.28A. InFIGS.28A and28B, the dummy gate structure412is removed in one or more etching steps, so that a gate trench is formed between corresponding gate spacers414. In some embodiments, an ILD layer is formed over the epitaxial source/drain structures416S,416D,418S,418D before removing the dummy gate structure412. In some embodiments, the dummy gate structure412is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate structure412at a faster rate than the gate spacers414and the ILD layer. The gate trench exposes the nanostructure layers405and interbridge layers401on the left side of the dielectric wall410, and the nanostructure layers407and interbridge layers403on the right side of the dielectric wall410. The gate trench also exposes a portion of the dielectric wall410between the gate spacers414.

FIG.29Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.29Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.29A. InFIGS.29A and29B, a selective etching process is performed to selectively etch the interbridge layers401and403exposed in the gate trench between the gate spacers414. On the left side of the dielectric wall410, this selective etching step forms an opening421A below the nanostructure layer405A, an opening421B between the nanostructure layers405A and405B, and an opening421C between the nanostructure layers405B and405C. On the right side of the dielectric wall410, this selective etching step forms an opening423A below the nanostructure layer407A, an opening423B between the nanostructure layers407A and407B, and an opening423C between the nanostructure layers407B and407C. In some embodiments where the interbridge layers are SiGe, this etching step uses a SiGe selective etchant. Process details about the SiGe selective etching step is similar to that discussed previously with respect toFIGS.20A-20B, and thus they are not repeated of the sake of brevity.

In some embodiments, the etching step selectively etches the interbridge layers401and403at a faster etch rate than it etches the nanostructure layers405and407. Therefore, the nanostructure layers405and407may remain substantially intact after the selective etching step is complete. In some embodiments, the etching step also etches the interbridge layers401A and403A at a faster etch rate than it etches the interbridge layers401B-C and403B-C, which in turn leaves portions420B and420C of the interbridge layers401B and401C on the left side of the dielectric wall410, and also leaves portions422B and422C of the interbridge layers403B and403C on the right side of the dielectric wall410, while leaving no portion of the interbridge layer401A on the left side of the dielectric wall410and no portion of the interbridge layer403A on the right side of the dielectric wall410.

The remaining portions420B-420C bridge the nanostructure layers405A-405C and thus collectively form a reversed E-shaped semiconductor channel structure that allows a current flow between the epitaxial source/drain structures416S and416D. The remaining portions420B-420C can thus be referred to as interbridge channels on the left side of the dielectric wall410, and the nanostructure layers405A-405C can be referred to as nanostructure channels on the left side of the dielectric wall410. The remaining portions422B-422C bridge the nanostructure layers407A-407C and thus collectively form an E-shaped semiconductor channel structure that allows a current flow between the epitaxial source/drain structures418S and418D. The remaining portions422B-422C can thus be referred to as interbridge channels on the right side of the dielectric wall410, and the nanostructure layers407A-407C can be referred to as nanostructure channels on the right side of the dielectric wall410. The reversed E-shaped channel structure is symmetric with the E-shaped channel structure about the dielectric wall410, as illustrated in the cross-sectional view ofFIG.29B.

In some embodiments where the interbridge layer401A and403A have a higher germanium atomic concentration than the interbridge layers401B-401C and403B-403C, the fluorine-based etchant can etch the interbridge layer401A and403A at a faster etch rate, because in the etching step using the fluorine-based etchant, the SiGe etch rate increases as the germanium atomic percentage increases. In some embodiments where the interbridge layers401B and401C have substantially the same germanium concentration, the resultant interbridge channels420B and420C have substantially the same width as illustrated inFIG.29B. In some embodiments where the interbridge layer401C has a higher germanium atomic concentration than the interbridge layer401B, the resultant interbridge channel420C has a smaller width than the resultant interbridge channel420B because of the etch rate difference resulting from the fluorine-based etchant, which in turn allows for a width difference in the interbridge channels as illustrated inFIG.8A. Similarly, in some embodiments where the interbridge layers403B and403C have substantially the same germanium concentration, the resultant interbridge channels422B and422C have substantially the same width as illustrated inFIG.29B. In some embodiments where the interbridge layer403C has a higher germanium atomic concentration than the interbridge layer403B, the resultant interbridge channel422C has a smaller width than the resultant interbridge channel422B because of the etch rate difference resulting from the fluorine-based etchant, which in turn allows for a width difference in the interbridge channels as illustrated inFIG.8A.

FIG.30Ais a top view of an intermediate stage in manufacturing of nano-FETs,FIG.30Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.30A. InFIGS.30A-30B, the dielectric wall410is removed, for example, by using a selective etching process that etches the dielectric material of the dielectric wall410at a faster etch rate than it etches the semiconductor materials of the nanostructure channels405,407and interbridge channels420,422, and thus the nanostructure channels405,407and interbridge channels420,422remain substantially intact after the selective etching process is complete. In some embodiments where the dielectric wall410is made of silicon oxide (SiO2), the silicon oxide wall410can be removed using a cyclic process including one or more repetitions of a plasma treatment step and an annealing step. Process details about the SiO2selective etching process is discussed previously with respect toFIGS.21A-21B, and thus they are not repeated for the sake of brevity.

FIG.31Ais a top view of an intermediate stage in manufacturing of nano-FETs,FIG.31Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.31A. InFIGS.31A-31B, replacement gate structure424is formed in the gate trench between the gate spacers414to surround the nanostructure channels405,407and interbridge channels420,422suspended between the gate spacers314. As a result, the reversed E-shaped channel structure of alternating nanostructure channels405and interbridge channels420shares a same gate structure424with the E-shaped channel structure of alternating nanostructure channels407and interbridge channels422. The gate structure424may be a high-k/metal gate structure that includes a gate dielectric layer426formed around the nanostructure channels405,407and interbridge channels420,422, and a gate metal428formed around the gate dielectric layer426. The gate metal428may include one or more work function metal layers formed around the gate dielectric layer426, and a fill metal formed around the one or more work function metal layers and filling a remainder of gate trench. Materials and process details about the gate structure424is similar to that of the gate structure326, and thus they are not repeated for the sake of brevity.

FIGS.32A-40Bare top views and cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments of the present disclosure. In general, the nano-FETs fabricated using the steps as illustrated inFIGS.32A-40Bhave separate E-shaped channel structures surrounded by separate gate structures. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.32A-40B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.32Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.32Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.32A. InFIGS.32A and32B, a fin structure FS of alternating stacked first semiconductor layers (interbridge layers)502A-502C and second semiconductor layers (nanostructure layers)504A-504C are formed over a substrate500, and STI regions508are formed around a lower portion of the fin structure FS. Material and process details about the substrate500, interbridge layers502A-502C (collectively referred to502), nanostructure layers504A-504C (collectively referred to as504), and the SIT regions508are similar to that of the substrate300, interbridge layers302, nanostructure layers304, and the SIT regions308as discussed previously, and thus they are not repeated for the sake of brevity.

FIG.33Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.33Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.33A. InFIGS.33A and33B, a patterned mask layer509is formed over the substrate500, and then the fin structure is anisotropically etched by using the patterned mask layer509as an etch mask to form a trench509S that breaks the fin structure into two separate fin structures FS1and FS2, wherein the fin structure FS1includes alternating interbridge layers501A-501C and nanostructure layers505A-505C, and the fin structure FS2includes alternating interbridge layers503A-503C and nanostructure layers507A-507C.

The separate interbridge layers501A and503A have the same material because they are both formed from the interbridge layer502A as illustrated inFIG.32B. The separate interbridge layers501B and503B have the same material because they are both formed from the interbridge layer502B. The separate interbridge layers501C and503C have the same material because they are both formed from the interbridge layer502C. In some embodiments, the interbridge layers501A and503A may have a higher germanium atomic concentration than the upper interbridge layers501B-501C and503B-503C, which in turn allows for removing the bottom interbridge layers501A and503A while leaving portions of upper interbridge layers501B-501C and503B-503C to serve as interbridge channels in a following SiGe selective etching process.

The separate nanostructure layers505A and507A have the same material because they are both formed from the nanostructure layer504A. The separate nanostructure layers505B and507B have the same material because they are both formed from the nanostructure layer504B. The separate nanostructure layers505C and507C have the same material because they are both formed from the nanostructure layer504C. In some embodiments, the nanostructure layers505A-505C and507A-507C is silicon and substantially free of germanium.

FIG.34Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.34Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.34A. InFIGS.34A and34B, an outer dielectric wall510is formed in the trench509S to electrically isolate the fin structures FS1and FS2, and an inner dielectric wall511is formed over the outer dielectric wall. The outer and inner dielectric walls510and511may be formed by, for example, depositing in sequence a first dielectric layer and a second dielectric layer in the trench509S until the trench509S is overfilled, followed by performing a CMP process to remove excessive dielectric materials outside the trench509S, while leaving a portion of the first dielectric layer in the trench509S to serve as the outer dielectric wall510and leaving a portion of the second dielectric layer in the trench509S to serve as the inner dielectric wall511.

In some embodiments, the dielectric walls510and511include silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable dielectric materials, and are deposited using, for example, CVD, ALD, PVD, or other suitable deposition techniques. In some embodiments, the outer dielectric wall510has a different material and hence a different etching selectivity than the inner dielectric wall511. For example, the outer dielectric wall510includes silicon oxide, and the inner dielectric wall511includes silicon nitride (Si3N4) or other dielectric materials except for silicon oxide.

FIG.35Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.35Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.35A. InFIGS.35A and35B, a dummy gate structure512is formed over both the fin structures FS1and FS2. The dummy gate structure512has a lengthwise direction perpendicular to the lengthwise direction of the fin structures FS1and FS2. Next, gate spacers514are formed on sidewalls of the dummy gate structure512. Material and process details about the dummy gate structure512and gate spacers514are similar to that of the dummy gate structure312and gate spacers314as discussed previously, and thus they are not repeated for the sake of brevity.

FIG.36Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.36Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.36A. InFIGS.36A and36B, portions of the fin structures FS1and FS2extending beyond the gate structure512and gate spacers514are recessed, and then epitaxial source/drain structures516S,516D are formed on the recessed portions of the fin structure FS1, and epitaxial source/drain structures518S,518D are formed on the recessed portions of the fin structure FS2. Epitaxial growth time/duration is controlled such that topmost positions of the epitaxial source/drain structures516S,516D,518S,518D are lower than a topmost position of the dielectric walls510,511, and thus the epitaxial source structure516S is entirely spaced apart from the epitaxial source structure518S by the dielectric walls510,511, and the epitaxial drain structure516D is entirely spaced apart from the epitaxial drain structure518D by the dielectric walls510,511. Material and process details about the epitaxial source/drain structures516S,516D,518S,518D are similar to that of the epitaxial source/drain structures322as discussed previously, and thus they are not repeated for the sake of brevity.

FIG.37Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.37Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.37A. InFIGS.37A and37B, the dummy gate structure512is removed in one or more etching steps, so that a gate trench is formed between corresponding gate spacers514. In some embodiments, an ILD layer is formed over the epitaxial source/drain structures516S,516D,518S,518D before removing the dummy gate structure512. In some embodiments, the dummy gate structure512is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate structure512at a faster rate than the gate spacers514and the ILD layer. The gate trench exposes the nanostructure layers505and interbridge layers501on the left side of the dielectric walls510,511, and the nanostructure layers507and interbridge layers503on the right side of the dielectric walls510,511. The gate trench also exposes portions of the dielectric walls510,511between the gate spacers514.

FIG.38Ais a top view of an intermediate stage in manufacturing of nano-FETs, andFIG.38Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.38A. InFIGS.38A and38B, a selective etching process is performed to selectively etch the interbridge layers501and503exposed in the gate trench between the gate spacers514. On the left side of the dielectric walls510,511, this selective etching step forms an opening521A below the nanostructure layer505A, an opening521B between the nanostructure layers505A and505B, and an opening521C between the nanostructure layers505B and505C. On the right side of the dielectric wall510, this selective etching step forms an opening523A below the nanostructure layer507A, an opening523B between the nanostructure layers507A and507B, and an opening523C between the nanostructure layers507B and507C. In some embodiments where the interbridge layers are SiGe, this etching step uses a SiGe selective etchant. Process details about the SiGe selective etching step is similar to that discussed previously with respect toFIGS.20A-20B, and thus they are not repeated of the sake of brevity.

In some embodiments, the etching step selectively etches the interbridge layers501and503at a faster etch rate than it etches the nanostructure layers505and507. Therefore, the nanostructure layers505and507may remain substantially intact after the selective etching step is complete. In some embodiments, the etching step also etches the interbridge layers501A and503A at a faster etch rate than it etches the interbridge layers501B-C and503B-C, which in turn leaves portions520B and520C of the interbridge layers501B and501C on the left side of the dielectric walls510,511, and also leaves portions522B and522C of the interbridge layers503B and503C on the right side of the dielectric walls510,511, while leaving no portion of the interbridge layer501A on the left side of the dielectric walls510,511and no portion of the interbridge layer503A on the right side of the dielectric walls510,511.

The remaining portions520B-520C bridge the nanostructure layers505A-505C and thus collectively form a reversed E-shaped semiconductor channel structure that allows a current flow between the epitaxial source/drain structures516S and516D. The remaining portions520B-520C can thus be referred to as interbridge channels on the left side of the dielectric walls510,511, and the nanostructure layers505A-505C can be referred to as nanostructure channels on the left side of the dielectric walls510,511. The remaining portions522B-522C bridge the nanostructure layers507A-507C and thus collectively form an E-shaped semiconductor channel structure that allows a current flow between the epitaxial source/drain structures518S and518D. The remaining portions522B-522C can thus be referred to as interbridge channels on the right side of the dielectric walls510,511, and the nanostructure layers507A-507C can be referred to as nanostructure channels on the right side of the dielectric walls510,511. The reversed E-shaped channel structure is symmetric with the E-shaped channel structure about the dielectric walls510,511, as illustrated in the cross-sectional view ofFIG.38B.

In some embodiments where the interbridge layer501A and503A have a higher germanium atomic concentration than the interbridge layers501B-501C and503B-503C, the fluorine-based etchant can etch the interbridge layer501A and503A at a faster etch rate, because in the etching step using the fluorine-based etchant, the SiGe etch rate increases as the germanium atomic percentage increases. In some embodiments where the interbridge layers501B and501C have substantially the same germanium concentration, the resultant interbridge channels520B and520C have substantially the same width as illustrated inFIG.38B. In some embodiments where the interbridge layer501C has a higher germanium atomic concentration than the interbridge layer501B, the resultant interbridge channel520C has a smaller width than the resultant interbridge channel520B because of the etch rate difference resulting from the fluorine-based etchant, which in turn allows for a width difference in the interbridge channels as illustrated inFIG.8A. Similarly, in some embodiments where the interbridge layers503B and503C have substantially the same germanium concentration, the resultant interbridge channels522B and522C have substantially the same width as illustrated inFIG.38B. In some embodiments where the interbridge layer503C has a higher germanium atomic concentration than the interbridge layer503B, the resultant interbridge channel522C has a smaller width than the resultant interbridge channel522B because of the etch rate difference resulting from the fluorine-based etchant, which in turn allows for a width difference in the interbridge channels as illustrated inFIG.8A.

FIG.39Ais a top view of an intermediate stage in manufacturing of nano-FETs,FIG.39Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.39A. InFIGS.39A-39B, the outer dielectric wall510is recessed, for example, by using a selective etching process that etches the dielectric material of the outer dielectric wall510at a faster etch rate than it etches the dielectric material of the inner dielectric wall511and the semiconductor materials of the nanostructure channels505,507and interbridge channels520,522, and thus the inner dielectric wall511, the nanostructure channels505,507and interbridge channels520,522remain substantially intact after the selective etching process is complete. In some embodiments where the outer dielectric wall510is made of silicon oxide (SiO2), the silicon oxide wall510can be selectively etched using a cyclic process including one or more repetitions of a plasma treatment step and an annealing step. Process details about the SiO2selective etching process is discussed previously with respect toFIGS.21A-21B, and thus they are not repeated for the sake of brevity. In some embodiments in the SiO2selective etching process, an etch rate ratio of the outer dielectric wall510(SiO2) to the inner dielectric wall511(Si3O4) is in a range from about 3:1 to about 8:1 (e.g., about 4:1). After the SiO2selective etching process is complete, a portion524of the outer dielectric wall510remains in the substrate500, and the remaining portion524may have a topmost position higher than the STI regions508.

FIG.40Ais a top view of an intermediate stage in manufacturing of nano-FETs,FIG.40Bis a cross-sectional view corresponding to the line B-B′ illustrated inFIG.40A. InFIGS.40A-40B, two separate replacement gate structures526A and526B are formed in the gate trench between the gate spacers514. The gate structure526A is formed on the left side of the inner dielectric wall511to surround the nanostructure channels505and interbridge channels520. The gate structure526B is formed on the right side of the inner dielectric wall511to surround the nanostructure channels507and interbridge channels522. As a result, the left side channel structure of alternating nanostructure channels505and interbridge channels520and the right side channel structure of alternating nanostructure channels507and interbridge channels522are controlled by different gate structures526A,526B. The gate structures526A,526B are high-k/metal gate structures each including a gate dielectric layer528, and a gate metal530formed around the gate dielectric layer528. The gate metal530may include one or more work function metal layers formed around the gate dielectric layer528, and a fill metal formed around the one or more work function metal layers and filling a remainder of gate trench. Materials about the gate structures526A,526B are similar to that of the gate structure326, and thus they are not repeated for the sake of brevity.

In some embodiments, formation of the gate structures526A,526B may include depositing one or more layers of dielectric materials and one or more layers of metal materials, and performing a CMP process on the one or more layers of dielectric materials and one or more layers of metal materials until the inner dielectric wall511is exposed, thus leaving a first portion of the one or more layers of dielectric materials and one or more layers of metal materials on the left side of the inner dielectric wall511to serve as the gate structure526A, and leaving a second portion of the one or more layers of dielectric materials and one or more layers of metal materials on the right side of the inner dielectric wall511to serve as the gate structure526B. In such embodiments, the gate structures526A and526B may include the same materials.

FIG.41is a cross-sectional view of a nano-FET in accordance with some embodiments of the present disclosure. InFIG.41, the nano-FET is formed on a substrate600and includes a channel structure CH6and a gate structure610extending over the channel structure CH6and STI regions608. The channel structure CH6includes alternating nanostructure channels NS1-NS3and interbridge channels IB1and IB2, and further includes a foot channel FT extending from the bottommost nanostructure channel NS1to a fin of the substrate600. The foot channel FT may be a remaining portion of a bottommost interbridge layer302A as illustrated inFIG.19B.

In some embodiments, the foot channel FT has substantially the same germanium atomic concentration and width as the interbridge channels IB1and IB2. In some embodiments, the foot channel FT has a higher germanium atomic concentration and a smaller width than the interbridge channels IB1and IB2. In some other embodiments, the foot channel FT has a lower germanium atomic concentration and a larger width than the interbridge channels IB1and IB2. The gate structure610includes a gate dielectric layer612over the channel structure CH6and a gate metal614over the gate dielectric layer612.

FIG.42is a cross-sectional view of a nano-FET in accordance with some embodiments of the present disclosure. InFIG.42, the nano-FET is formed on a substrate700and includes a channel structure CH7and a gate structure710extending over the channel structure CH7and STI regions708. The channel structure CH7includes alternating nanostructure channels NS1-NS3and interbridge channels IB1and IB2, and further includes a foot channel FT extending from the bottommost nanostructure channel NS1to a fin of the substrate700, and a hair channel HR extending upwardly from the topmmost nanostructure channel NS3. The hair channel HR may be formed by, for example, forming an additional interbridge layer over the nanostructure layer304C as illustrated inFIG.10B, and then selectively etching the additional interbridge layer at the step as illustrated inFIG.20Bto form the hair channel HR.

In some embodiments, the hair channel HR has substantially the same germanium atomic concentration and width as the interbridge channels IB1and IB2and the foot channel FT. In some embodiments, the hair channel HR has a higher germanium atomic concentration and a smaller width than the interbridge channels IB1and IB2and the foot channel FT. In some other embodiments, the hair channel HR has a lower germanium atomic concentration and a larger width than the interbridge channels IB1and IB2and the foot channel FT. The gate structure710includes a gate dielectric layer712over the channel structure CH7and a gate metal714over the gate dielectric layer712.

FIG.43is a cross-sectional view of a nano-FET in accordance with some embodiments of the present disclosure. InFIG.43, the nano-FET is formed on a substrate800and includes a channel structure CH8and a gate structure810extending over the channel structure CH8and STI regions808. The gate structure810includes a gate dielectric layer812over the channel structure CH8and a gate metal814over the gate dielectric layer812. The channel structure CH8includes alternating nanostructure channels NS1-NS3and interbridge channels IB1and IB2, and further includes a hair channel HR extending upwardly from the topmmost nanostructure channel NS3, and a foot channel FT extending downwardly from the bottommost nanostructure NS1to a fin of the substrate800. The foot channel FT may be a remaining portion of a bottommost interbridge layer302A as illustrated inFIG.19B. The hair channel HR may be formed by, for example, forming an additional interbridge layer over the nanostructure layer304C as illustrated inFIG.10B, and then selectively etching the additional interbridge layer at the step as illustrated inFIG.20Bto form the hair channel HR.

InFIG.43, the left side surfaces of the interbridge channels IB1, IB2, foot channel FT, and hair channel HR are laterally set back from the left side surfaces of the nanostructure structures NS1-NS3. Such lateral offset profile may be formed by, for example, selectively etching the interbridge channels IB1, IB2, foot channel FT, and hair channel HR after the dielectric wall310is removed from left side surfaces of the interbridge channels IB1, IB2, foot channel FT, and hair channel HR, as illustrated in the step ofFIG.21B.

FIG.44is a cross-sectional view of a nano-FET in accordance with some embodiments of the present disclosure. InFIG.44, the nano-FET is formed on a substrate900and includes a channel structure CH9and a gate structure910extending over the channel structure CH9and STI regions908. The gate structure910includes a gate dielectric layer912over the channel structure CH9and a gate metal914over the gate dielectric layer912. The channel structure CH9includes alternating nanostructure channels NS1-NS3and interbridge channels IB11-IB32, and further includes hair channels HR1-HR3extending upwardly from the topmmost nanostructure channel NS3, and foot channels FT1-FT3extending downwardly from the bottommost nanostructure channel NS1to a fin of the substrate900. The foot channel FT1, interbridge channels IB11, IB12, and hair channels HR1are localized to a first region R1of the nanostructure channels NS1-NS3; the foot channel FT2, interbridge channels IB21, IB22, and hair channels HR2are localized to a second region R2of the nanostructure channels NS1-NS3spaced apart from the first region R1; and the foot channel FT3, interbridge channels IB31, IB32, and hair channels HR3are localized to a third region R3of the nanostructure channels NS1-NS3spaced apart from both the first and second regions R1and R2. The channel structure CH9may be formed by, for example, forming a layer stack of alternating first and second semiconductor layers, forming a patterned mask covering the regions R1-R3, selectively etching portions of the second semiconductor layers exposed by the patterned mask, and then removing the patterned mask from the regions R1-R3.

Based on the above discussions, it can be seen that the present disclosure in various embodiments offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the on-current of a transistor can be enhanced by adding interbridge channels between neighboring nanostructure channels. Another advantage is that the on-current enhancement can be further increased by forming interbridge channels localized to a periphery region or off-center region of the nanostructure channels.

In some embodiments, a device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers. In some embodiments, the second semiconductor layers have a smaller width than the first semiconductor layers. In some embodiments, the second semiconductor layers are made of a different material than the first semiconductor layers. In some embodiments, the second semiconductor layers have a greater germanium atomic percentage than the first semiconductor layers. In some embodiments, the second semiconductor layers have substantially a same width. In some embodiments, an upper one of the second semiconductor layers has a smaller width than a lower one of the second semiconductor layers. In some embodiments, a width difference between the second semiconductor layers is greater than a width difference between the first semiconductor layers. In some embodiments, the second semiconductor layers have different germanium atomic percentages. In some embodiments, an upper one of the second semiconductor layers has a greater germanium atomic percentage than a lower one of the second semiconductor layers. In some embodiments, the device further comprises a second channel structure surrounded by the first gate structure, and the second channel structure is symmetric with the first channel structure when viewed in the cross section taken along the second direction. In some embodiments, the device further comprises a second channel structure symmetric with the first channel structure when viewed in the cross section taken along the second direction; a second gate structure surrounding the second channel structure; and a dielectric wall separating the first gate structure from the second gate structure.

In some embodiments, a device comprises a source region, a drain region separated from the source region along a first direction, and a channel structure interposing the source region and the drain region. The channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, the first semiconductor layers have opposite first and second side surfaces, the second semiconductor layers have opposite third and fourth side surfaces, the third side surfaces of the second semiconductor layers are aligned with the first side surfaces of the first semiconductor layers, and the fourth side surfaces of the second semiconductor layers are laterally set back from the second side surfaces of the first semiconductor layers. In some embodiments, the second semiconductor layers non-overlap with central axes of the first semiconductor layers. In some embodiments, a width of the second semiconductor layers is less than half a width of the first semiconductor layers. In some embodiments, the fourth side surfaces of the second semiconductor layers are misaligned with each other. In some embodiments, the first semiconductor layers are germanium-free semiconductor layers, and the second semiconductor layers are germanium-containing semiconductor layers.

In some embodiments, a method comprises forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dielectric wall on a first longitudinal side of the fin structure but not on a second longitudinal side of the fin structure; performing a first etching process that etches the second semiconductor layers at a faster etch rate than etching the first semiconductor layers; after performing the first etching process, performing a second etching process to remove the dielectric wall; and after removing the dielectric wall, forming a gate structure over the first semiconductor layers and the second semiconductor layers. In some embodiments, the first etching process etches a bottommost one of the second semiconductor layers at a faster etch rate than etching upper ones of the semiconductor layers. In some embodiments, the second etching process etches the dielectric wall at a faster etch rate than etching the first semiconductor layers and the second semiconductor layers. In some embodiments, the method further comprises recessing a portion of the fin structure after forming the dielectric wall; and forming an epitaxial source/drain structure on the recessed portion of the fin structure and contacting a side surface of the dielectric wall.