Semiconductor die package using leadframe and clip and method of manufacturing

A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).

CROSS-REFERENCES TO RELATED APPLICATIONS

BACKGROUND OF THE INVENTION

Many semiconductor die packages use clips instead of wires to form external connections to external terminals. Such semiconductor die packages are sometimes referred to as “wireless” packages. A typical wireless package includes a clip that is attached to a semiconductor die. Wireless packages generally have better electrical and thermal performance than packages that use wire-based electrical connections.

Typically, conventional wireless packages need to be designed into a customers' circuit boards, because the circuit boards have unique footprints and pin assignments. It would be desirable to provide for a semiconductor die package that has a footprint and pin assignment that can correspond to conventional package footprints and pin assignments, while still having good electrical and thermal performance.

Also, when producing wireless packages, it is often difficult to create a clip (e.g., a source clip) that has a deep downset. The “downset” of a clip may correspond to the vertical distance between a major portion of the clip to the lead portion of the clip. It would also be desirable to provide for a clip that has a deeper downset than conventional clips so that different types of packages can be produced.

Another problem that exists is the problem of applying inconsistent or uneven amounts of solder between the clip and the semiconductor die. When inconsistent or uneven amounts of solder are used between a die and a clip, the resulting packages may exhibit poor performance.

In addition to the above-noted problems, it will be advantageous to provide for a method that can be used to create a semiconductor die package quickly and reliably. The method is also preferably compatible with Pb-free processing.

Embodiments of the invention address the above problems and other problems.

SUMMARY OF THE INVENTION

Embodiments of the invention are directed to clip structures, semiconductor die packages including the clip structures, and methods for making semiconductor die packages including clip structures.

One embodiment of the invention is directed to a clip structure for a semiconductor package, the clip structure comprising: a major portion; at least one pedestal extending from the major portion; a downset portion; and a lead portion, wherein the downset portion is between the lead portion and the major portion.

Another embodiment of the invention is directed to a clip structure for a semiconductor package, the clip structure comprising: a major portion; a downset portion having a stepped configuration; and a lead portion, wherein the downset portion is between the lead portion and the major portion.

Other embodiments of the invention are directed to semiconductor die packages including the above-described clip structures, as well as methods for making the semiconductor die packages using the clip structures.

Another embodiment of the invention is directed to a semiconductor die package comprising: a clip structure comprising a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion, wherein the downset portion is between the lead portion and the major portion, and has a stepped configuration; a leadframe structure; and a semiconductor die, wherein the semiconductor die is between the leadframe structure and the clip structure.

Another embodiment of the invention is directed to method of manufacturing a semiconductor die package, the method comprising: obtaining a clip assembly; obtaining a leadframe structure comprising at least one alignment structure, wherein the alignment structure aligns the clip assembly to the leadframe structure during the assembly of a semiconductor die package; attaching a second surface of a semiconductor die to the leadframe structure; and attaching a first surface of the semiconductor die to the clip assembly.

DETAILED DESCRIPTION

Embodiments of the invention can include wireless packages. A wireless package according to an embodiment of the invention does not use wires to connect to input and/or output terminals of an electrical device in a semiconductor die. In other embodiments, the semiconductor die packages need not be wireless. For example, as illustrated below, embodiments of the invention include unique source clip structures with specific configurations. Such source clip structures could be used in a semiconductor die package with a gate wire bond. However, wireless semiconductor die packages are preferred as they generally have better thermal and electrical properties than semiconductor die packages that use wires for terminal connections.

In one semiconductor die package embodiment, the semiconductor die package comprises a clip structure comprising a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion, and can have a stepped configuration. A semiconductor die is sandwiched between and is attached to the clip structure and a leadframe structure.

In embodiments of the invention, a first solder material can be used to mechanically and electrically couple the semiconductor die to the leadframe structure. A second solder material can be used to mechanically and electrically couple the semiconductor die to the clip structure. The first and second solder materials may be the same or different. They are preferably the same material and can comprise lead-free solder materials.

FIG. 1shows a side cross-sectional view of a semiconductor die package according to an embodiment of the invention. The semiconductor die package100includes a semiconductor die16, which is disposed between a source clip structure14and a leadframe structure18. A molding material20at least partially covers the semiconductor die16, the clip structure14, and the leadframe structure18. The molding material20may be an epoxy molding material or any other suitable commercially available molding material.

As shown inFIG. 1, the semiconductor die package100also includes a first lateral surface100(a) and a second lateral surface100(b), as well as a top surface100(c) and a bottom surface100(d).

Even though the resulting semiconductor die package100has embedded leads, the semiconductor die package100can be referred to as a “leadless” package in the sense that leads do not extend past the side surfaces of the molding material20. It can also be in the form of a block, and the semiconductor die package100may also be referred to as a MLP (micro-leadframe package) type package in some embodiments. Although a leadless die package is described in detail in this application, it is understood that the clip structure14could alternatively be used in a leaded die package.

Solder24is between a first surface16(a) of the semiconductor die16and the clip structure14. Solder90is also present between a second surface16(b) of the semiconductor die16and the leadframe structure18.

Any suitable solder material may be used for solder24and solder90. For example lead-tin solder could be used for solder24and solder90. Preferably, the solder24and the solder90comprises a lead-free solder material such as indium-tin based solder. Alternatively, a conductive polymer adhesive (e.g., a conductive epoxy adhesive) could be used instead of solder.

The semiconductor die16may include any suitable semiconductor device. Suitable semiconductor devices may comprise a semiconductor material such as silicon, and may include vertical or horizontal devices. Vertical devices have at least an input at one side of the die and an output at the other side of the die so that current can flow vertically through the die. Horizontal devices include at least one input at one side of the die and at least one output at the same side of the die so that current flows horizontally through the die. The semiconductor device in the semiconductor die16is preferably a vertical power transistor.

Vertical power transistors include VDMOS transistors and vertical bipolar transistors. A VDMOS transistor is a MOSFET that has two or more semiconductor regions formed by diffusion. It has a source region, a drain region, and a gate. The device is vertical in that the source region and the drain region are at opposite surfaces of the semiconductor die. The gate may be a trenched gate structure or a planar gate structure, and is formed at the same surface as the source region. Trenched gate structures are preferred, since trenched gate structures are narrower and occupy less space than planar gate structures. During operation, the current flow from the source region to the drain region in a VDMOS device is substantially perpendicular to the die surfaces.

In this example, the semiconductor die16comprises a vertical MOSFET. The vertical MOSFET includes a source region and a gate region at the first surface16(a), and a drain region at the second surface16(b) of the semiconductor die16. The source region may have a source metal (e.g., a solderable top metal or solder bumps), and may be electrically coupled to the clip structure14(which may be a source clip structure). The gate region may be electrically coupled to a corresponding gate clip structure (not shown), while the drain region at the second surface16(b) may be electrically coupled to the leadframe18.

The leadframe structure18includes a first surface18(a), and a second surface18(b). The leadframe structure18also includes a portion18(c) that is formed by an etching process, as well as a pad portion18(e) and a lead portion18(d). The pad portion18(e) may form the DAP (die attach pad) of the leadframe structure18.

As shown inFIG. 1, the lead portion18(d) does not extend past the molding material20, and is substantially coplanar with a bottom exterior surface20(a) of the molding material20. The first lateral surface100(a) of the semiconductor die package100coincides with a side surface of the molding material20and a side surface of the lead portion18(d). The bottom surface100(d) of the semiconductor die package100coincides with a bottom surface of the leadframe structure18and a bottom exterior surface of the molding material20.

The bottom of the leadframe structure18is exposed through the molding material20. The exposed bottom surface of the leadframe structure18provides for an additional drain connection as well as an additional cooling path for the semiconductor die package100.

The leadframe structure18may comprise any suitable material. For example, the leadframe structure34may comprise copper, copper alloys, or any other suitable conductive material. It may also be plated with a solderable metal if desired.

The clip structure14may have any suitable configuration. In this example, the clip structure14includes a major portion14(a), a lead portion14(c), and a downset portion14(b). The downset portion14(b) is disposed between the major portion14(a) and the lead portion14(c). It includes a stepped or zigzag structure. Although one “step” is shown inFIG. 1, in other embodiments, the clip structure14may include multiple steps.

The clip structure14may comprise any suitable material. For example, conductive materials such as copper, aluminum, and noble metals (and alloys thereof) may be used in the clip structure14. The clip structure14may also be plated with solderable layers if desired.

The stepped downset portion14(b) of the clip structure14provides for a number of advantages. For example, the stepped structure allows for a better alignment tolerance between a bottom surface of the lead portion14(c) and a bottom surface of the leadframe structure18. Since the downset portion14(b) is bent, it can “flex” more than a non-stepped downset portion. This allows the lead portion14(c) to be more easily aligned with the bottom surface of the leadframe structure18. Also, the stepped downset portion14(b) also allows the clip structure14to have a deeper downset than conventional clip structures.

In the clip structure14, a number of discrete pedestals14(a)-1extend downward and perpendicular to the horizontal surface of the main portion14(a) of the clip structure14. A pedestal14(a)-1is more clearly shown inFIG. 2. As shown, the end of the pedestal14(a)-1can contact the first surface16(a) of the semiconductor die16, and solder24surrounds the pedestal. The surface of the clip structure14opposite the pedestal14(a)-1is somewhat concave. This concave structure and the corresponding pedestal14(a)-1can be formed by a process such as stamping. Although a stamping process is described, the pedestals according to embodiments of the invention can be formed by any other suitable method known to those of ordinary skill in the art. For example, pedestals could be formed on a planar clip structure by etching the clip structure so that the appropriate protrusions are formed. Alternatively, protrusions can be formed by plating or placing conductive columns on a flat surface of a clip structure.

The pedestals14(a)-1in the clip structure14provide for a number of advantages. For example, they provide for consistent spacing between the bottom surface of the major portion14(a) of the source clip structure14and the first surface16(a) of the semiconductor die16. Because there is a consistent spacing between the major portion14(a) of the clip structure14and the first surface16(a) of the semiconductor die, a consistent amount of solder is always present between them. Excess solder, if any, can squeeze out from between the clip structure14and the semiconductor die16. In addition to providing for the more consistent solder deposition, the pedestals14(a)-1also provide for a larger attachment surface area for the clip structure14, thereby providing for a better bond and better electrical connection between the source clip structure14and the semiconductor die16. The pedestals14(a)-1also prevent the clip structure14from undesired “tilting”. If the pedestals14(a)-1were not present, the clip could “tilt”, thereby resulting in the uneven application of solder to the top surface of the semiconductor die16.

FIG. 3shows a perspective view of a semiconductor die package according to an embodiment of the invention. In this illustration, the molding material is not shown. As shown inFIG. 3, the semiconductor die package may include a source clip structure14and a gate clip structure28. The gate clip structure28and the source clip structure14are electrically uncoupled from each other. As will be explained in greater detail below, the source clip structure14and the gate clip structure28may be derived from a clip assembly. InFIG. 3, as inFIG. 1, the semiconductor die16is sandwiched between the source clip structure14and the leadframe structure18. Also, as shown inFIG. 3, the semiconductor die16is also sandwiched between the gate clip structure28and the leadframe structure18. Like the source clip structure14, the gate clip structure28may also include one or more pedestals (not shown) to provide for consistent solder deposition.

FIG. 4shows a top view of a semiconductor die package in a package assembly. The dotted line indicated by reference number40shows where the assembly will be cut with a saw or the like. Prior to being cut, the gate clip structure18and the source clip structure14are joined by a bridge structure52. The bridge structure52electrically and mechanically connects the leads of the gate clip structure18and the source clip structure14. In addition, prior to being cut, the leadframe structure18is part of a leadframe assembly that includes an alignment rail structure70. The alignment rail structure70includes two alignment end structures70(a). In this example, the alignment end structures70(a) are in the form of metal squares, but could have other shapes in other embodiments of the invention. The alignment end structures70(a) confine the bridge structure52so that the clip assembly102is properly aligned with the terminals of the semiconductor die16. Specifically, the source clip structure14and the source clip structure pedestals14(a)-1are automatically aligned so that they are electrically coupled to the source terminals in the MOSFET in the semiconductor die16. At the same time, the gate clip structure18and the gate pedestal18(a)-1are automatically aligned so that they are electrically coupled to the gate terminal in the MOSFET in the semiconductor die16. This alignment process takes one step, thereby saving processing time and cost.

Once the clip assembly102and the leadframe structure18are attached to the semiconductor die16using solder, the resulting assembly can be subjected to a reflow process to reflow all of the solder in the package simultaneously. A molding material can then be formed around the die in an encapsulation process. Then, the assembly can be cut along the dotted line shown by reference number40. This separates the bridge structure52from the formed package and electrically uncouples the gate lead structure18and the source lead structure16. Since only one reflow process is needed to form the resulting package, the package can be formed quickly and efficiently. Also, performing only one reflow process decreases the chances of forming intermetallic compounds in the solder. Intermetallic compounds are more likely to be formed with repeated heating. Intermetallic compounds can also lead to brittle solderjoints and an increase the likelihood of defective solder joints.

FIG. 5shows the assembly inFIG. 4from a side view. As shown inFIG. 5, the leadframe structure18and the lead portion14(c) are coplanar with each other and are disposed on a temporary substrate34. The temporary substrate34, can be made of any suitable material. For example, the temporary substrate34could be made of tape. After the package is formed, the temporary substrate34may be removed.

FIG. 6shows a bottom view of a leadframe assembly according to an embodiment of the invention. The leadframe assembly includes a leadframe structure18, which includes a number of the drain leads18(a), and an etched portion18(c). The etched portion18(c) may form a drain pad18(b) for the semiconductor die package and may be eventually soldered to a circuit board (not shown). Connection rails20may connect the leadframe structure18to a frame74. The frame74may include the previously described rail structure70and alignment end structures70(a), and may define a hole60. The leads of the source clip structure (not shown) may be present in the hole60during package assembly.

FIG. 7shows a clip assembly102before it is cut. As showed inFIG. 7, a bridge structure52couples the leads of the source clip structure14and the lead of the gate clip structure18. As explained above, the bridge structure52is separated from the gate clip structure18and the source clip structure14, and they are electrically uncoupled from each other in the formed semiconductor die package. The other elements inFIG. 7have been previously described.

FIG. 8shows a side view of a clip structure14according to an embodiment of the invention. As shown inFIG. 8, the pedestal14(a)-1resembles a mesa structure. However, in other embodiments, the pedestals may be cone-shaped, cylinder-shaped, or may have any other protruding shape. Also, the downset height between a bottom surface of the major portion14(a) and the bottom surface of the lead portion14(c) may be designated by the height D. In preferred embodiments, the downset height may be about 2 times the thickness (or more) of the leadframe structure18or the thickness of the clip structure14. The thickness of the leadframe structure18and/or the clip structure14can be greater than about100microns in some embodiments.

As shown inFIG. 9, the height of the pedestal14(a)-1may be about 50 microns, while the width of the pedestal may be approximately 150 microns. Of course, the dimensions of other pedestal may be different in other embodiments of the invention.

FIG. 10shows a semiconductor die package202that includes a MOSFET die82and a Schottky diode die84. A clip assembly102may include terminal connections to source and gate connections in the MOSFET die82and an input and/or output to the Schottky diode die84. As in prior embodiments, the clip assembly102may include a bridge structure52, which is aligned between alignment structures70(a).

FIG. 11shows a semiconductor die package204that includes two MOSFET dies82. A clip assembly102may include terminal connections to source and gate connections in the MOSFET dies82. As in prior embodiments, the clip assembly102may include a bridge structure52, which is aligned between alignment structures70(a).

FIG. 12shows a semiconductor die package according to another embodiment of the invention. This embodiment is similar to the embodiment shown inFIG. 1, except that the molding material20at the top portion of the package exposes the upper surface of the clip structure14. If desired, a heat sink (not shown) may be attached to the top surface14(f) of the clip structure14. The exposed clip structure surface14(f) is substantially coplanar with an exterior surface20(b) of the molding material20. The exposed clip surface14(f) allows for better heat dissipation and also results in a thinner semiconductor die package. The exposed clip surface14(f) can be formed by covering the surface with tape or a molding die, or any other suitable method known to one skilled in the art, and then molding the molding material20around the semiconductor die16. The other features inFIG. 12have been previously described.

FIGS. 13(a)-13(d) show how semiconductor die packages according to embodiments of the invention can be assembled.

FIG. 13(a) shows semiconductor dies16being mounted on leadframe structures34. The leadframe structure34may be in array or “gang” of leadframe structures. The gang may be a 2 or 1-dimensional array of leadframe structures connected together by rails or the like. As previously described, solder (e.g., lead-free solder) may be used to attach the semiconductor dies16to the leadframe structures18. At this point in the process, the leadframe structures18may be disposed on a temporary substrate34such as tape. This is done to cover the bottom surface of the leadframe structure18so that it is not covered with a molding material. At this point, the solder that is used to attach the leadframe structures18to the semiconductor dies16has not yet been reflowed.

FIG. 13(b) shows clip structures14being placed on the semiconductor dies16. The downset portions of the clip structures14are not shown as being stepped. However, it is understood that, in other embodiments, clip structures14with stepped downset portions may be used. As in other embodiments, the clip structures14may have pedestals14(a)-1that space major portions of the clip structures14from the top surfaces of the semiconductor dies16.

In some embodiments, solder may be deposited on the top surfaces of the semiconductor dies16and the clip structures14may be mounted thereon. Alternatively or additionally, solder may be deposited on the clip structures14and the solder-coated clip structures may be attached to the top surfaces of the semiconductor dies16.

As noted above, the solder material that is used to attach the semiconductor dies16to the leadframe structures18may be the same or different than the solder material that is used to attach the clip structures14to the semiconductor dies16. After the clip structures14are attached to the semiconductor dies16, the solder materials that are used to attach these components together are simultaneously reflowed. Suitable reflow processing conditions are known to those of ordinary skill in the art.

FIG. 13(c) shows the assembly after a molding process is performed. Commercially available molding tools may be used to perform the molding process. Molding materials such as epoxy molding materials may be used.

FIG. 13(d) shows the process of singulation. In a singulation process, semiconductor die packages100that are joined together are separated from each other. Any suitable cutting tool may be used for this purpose. For example, a water jet, laser, saw, etc. may be used to separate the semiconductor die packages from each other.

Embodiments of the invention provide for a number of advantages. For example, embodiments of the invention can have the same footprint and pin assignment as other types of conventional packages, while also exhibiting good electrical and thermal performance. In addition, the methods according to embodiments of the invention may use alignment structures to align clip structures on top of a semiconductor die with a leadframe structure at the bottom of the semiconductor die. This results in more efficient processing, and flip chip attachment processes need not be performed in embodiments of the invention. Also, embodiments of the invention are robust. In some embodiments, the semiconductor dies are not exposed to the environment.

Also, in embodiments of the invention, the same type of solder paste or conductive adhesive can be used to attach the leadframe structure to the bottom surface of the semiconductor die, and one or more clip structures to the top surface of the semiconductor die. A one-time solder-paste reflow process may be performed for both die attach and clip attach. Because only one reflow process is needed in this example, the formation of excessive amounts of intermetallic compounds in the solder joints is minimized or prevented. Also, because only one reflow process needs to be performed in this example, two types of Pb-free solder with different melting points are not needed.

In conventional processing, the die is attached to a leadframe structure using solder and that solder is reflowed. Then, a clip structure is attached to the semiconductor die and is also reflowed. The solder between the die and the leadframe structure is subjected to two heating processes. This increase in heating increases the chances that intermetallic compounds may form.

The above description is illustrative and is not restrictive. Many variations of the invention will become apparent to those skilled in the art upon review of the disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the pending claims along with their full scope or equivalents. Moreover, any one or more features of one or more embodiments may be combined with one or more features of any other embodiment without departing from the scope of the invention. For example, the features in the embodiments inFIGS. 10 and 11can be combined with the features of any other embodiment in any other figure without departing from the scope of the invention.

Any reference to positions such as “top”, “bottom”, “upper”, “lower”, etc. refer to the Figures and are used for convenience. They are not intended to refer to absolute positions. For example, althoughFIG. 1shows a “bottom” surface of a semiconductor die package, it is understood that the semiconductor die package could be mounted sideways, upside-down, or right side up and would still be within the scope of the claims.