Semiconductor process for forming stress absorbent shallow trench isolation structures

A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

FIELD OF THE INVENTION

The present invention is in the field of semiconductor fabrication processes and, more particularly, isolation structures for semiconductor fabrication processes.

RELATED ART

In the field of semiconductor fabrication processes, carrier mobility enhancement techniques involving the intentional introduction of compressive or tensile stress (or both) within the active transistor areas have been proposed. The use of compressively stressed silicon germanium, for example, has been proposed to enhance hole mobility for PMOS transistors. Because these techniques are typically being proposed for use in advanced semiconductor fabrication processes in which adjacent devices are closely spaced, it is possible that region of the wafer exhibiting a first type of stress characteristic will be in close proximity to a region of the wafer exhibiting a second type of stress characteristic such as when a compressively stressed PMOS transistor and a tensily stressed NMOS transistor are separated by an isolation trench having a minimum dimension. In such cases, it is possible that the stress characteristics of the first region may transfer, through the isolation structure, to the second region of the wafer where the stress characteristics may have a negative impact on device performance. It would be desirable, therefore, to implement a fabrication processes that uses stressed active regions to enhance carrier mobility of a first type of transistor while ensuring that the stressed regions do not adversely affect adjacent transistors.

DETAILED DESCRIPTION OF THE DRAWINGS

Generally speaking, the invention is directed at a semiconductor fabrication process that employs trench isolation structures designed to reduce or eliminate stress created at one transistor from being undesirably transmitted to an adjacent transistor through the isolation structure. Isolation trenches according to the present invention are primarily filled with a flowable type of oxide that acts as a damping structure that prevents compressive or tensile stress in one transistor being transmitted to an adjacent transistor. The isolation trenches are preferably capped with a second dielectric. The second dielectric has better mechanical stability and density than the first dielectric. The isolation trenches may incorporate trench liners to prevent unwanted diffusion of impurities in the trench to the active device areas.

Referring now to the drawings,FIG. 1is a partial cross sectional view of a semiconductor wafer101suitable for use in the fabrication of integrated circuits. In the depicted embodiment wafer101is a silicon on insulator (SOI) wafer. In this embodiment, wafer101includes a bulk102that is typically made of lightly doped, single crystal silicon. In other implementations, bulk102may be another semiconductor material such as gallium arsenide or another III-V compound.

An oxide layer, referred to as buried oxide (BOX) layer104overlies that wafer bulk102. A semiconductor layer, referred to herein as active layer106overlies BOX layer104. Active layer106may include various semiconductor materials including n-doped or p-doped silicon, silicon germanium, or silicon carbon. In other implementations, the starting material for wafer101is a conventional or “bulk” wafer that does not have a BOX layer.

Referring now toFIG. 2, a patterned mask108is formed over active layer106of wafer101. Mask108is patterned to expose an isolation region denoted by reference numeral110in wafer101. Isolation regions110represent regions of wafer101that provide physical and electrical separation and isolation between adjacent transistors. In one implementation, mask108is a hard mask (as opposed to a photoresist mask) made of a material such as silicon nitride. In this implementation, a pad oxide (not shown) may be formed on an upper surface of wafer101prior to depositing the silicon nitride for mask108. Patterning of mask108is achieved using conventional photoresist and photolithographic processes.

Referring now toFIG. 3, an isolation trench112is formed in wafer101by removing portions of active layer104within isolation regions110defined by patterned mask108. The trench isolation etch used to form isolation trench may be a conventional silicon plasma etch process that is selective to silicon nitride. In an embodiment suitable for implementations that use an SOI starting material (such as the wafer101depicted inFIG. 1), the isolation trench112extends entirely through the active layer106and partially into the BOX layer106. Other implementations may form an isolation trench that extends entirely through both active layer106and BOX layer104.

Turning now toFIG. 4, one or more dielectric liners are formed on sidewalls and the bottom or floor of isolation trench112. In the depicted embodiment, a silicon oxide liner120is formed adjacent the sidewalls of isolation trench112and a silicon nitride liner122is formed adjacent to silicon oxide liner120. The use of silicon nitride liner122beneficially provides a barrier to mobile contaminants or impurities that may be present in a subsequent formed isolation trench structure.

Turning now toFIG. 5, a first dielectric film130is deposited over wafer101and second dielectric film135is deposited over the first dielectric film. The first dielectric film130is referred to herein as flowable dielectric film130. A flowable dielectric film, for purposes of this disclosure, is a dielectric film that flows at a temperature of less than approximately 900 C. Flowable dielectric130may be implemented in various different embodiments. In one embodiment, flowable dielectric130is a commercially distributed, flowable oxide available from Dupont. In this embodiment, flowable oxide130is a spin on, low dielectric constant material that is flowable at a temperature of less than approximately 300 C.

In other embodiments, flowable dielectric130is doped glass such as borophosphosilicate glass (BPSG) preferably having a boron and phosphorous content of approximately 4% by weight or more. In this embodiment, the BPSG film will flow at a temperature of approximately 900 C. or less. In other doped glass embodiments, flowable dielectric130may be implemented as a phosphosilicate glass (PSG) or a borosilicate glass (BSG). In any of these doped glass embodiments, flowable silicon oxide130may be formed using widely known doped glass deposition techniques. In still other embodiments, flowable oxide130may be formed by depositing a conventional TEOS or other suitable silicon oxide material and introducing the desired level of impurities such as boron and/or phosphorous through ion implantation.

Flowable dielectric130as shown inFIG. 5only partially fills dielectric trench112. This embodiment is desirable for implementations that incorporate a capping layer overlying the flowable dielectric. Although flowable dielectric112has desirable flow properties, it may have undesirably high porosity or other characteristics that would counsel in favor of capping the flowable dielectric with a material that is more moisture impervious. To facilitate the partial filling of isolation trench112with flowable dielectric130, the process parameters for the deposition of flowable dielectric130may be controlled to produce a deposition that exhibits intentionally poor step coverage as suggested by the flowable dielectric depicted inFIG. 5. In this embodiment, little dielectric is formed on the sidewalls of dielectric trench112and, by controlling the thickness of the dielectric film deposited, flowable dielectric130only partially fills dielectric trench112.

The capping dielectric135is preferably a dielectric that exhibits excellent thermal and mechanical stability and is highly impervious to moisture. In the preferred embodiment, capping dielectric135is a high density plasma (HDP) silicon oxide. An HDP silicon oxide, as suggested by its name, is chemically vapor deposited using a low pressure, high density plasma. For purposes of this disclosure, a high density plasma is a plasma having an ion density of greater than approximately 1010ions/cm3. The high density plasma produces a silicon oxide having the desired mechanical and barrier properties at a temperature of approximately 400 C. or lower. The thickness of capping dielectric135is sufficient to fill and, preferably, overfill the isolation trench so that the upper surface of capping dielectric135is above the upper surface of active layer106of wafer101.

Turning now toFIG. 6, portions of capping dielectric135and flowable dielectric130that are exterior to the isolation trench are removed. In one embodiment, a chemical mechanical polish (CMP) process is used to remove dielectric layers130and135with mask108being used as a polish stop. The CMP process may also remove portions of patterned mask108, but preferably leaves at least a portion of patterned mask108intact.

As shown inFIG. 7, remaining portions of patterned mask108are removed. In the preferred embodiment, patterned mask108is removed with a wet or dry etch process that is preferential to patterned mask108and selective to capping dielectric135. Embodiments that use a silicon nitride mask108and a silicon oxide capping dielectric135, for example, may use a hot phosphoric acid wet etch process or various dry etch processes including NF3. An additional polish may be performed as well to obtain a smooth upper surface.

In addition to the removal of patterned mask108,FIG. 7depicts a region105where a first portion of semiconductor layer106was shown inFIG. 6and a region107where a second portion of semiconductor layer106was shown inFIG. 6. Depending upon the implementation, region105may be comprised of the same material as active layer106ofFIG. 6or, alternatively, region105may be comprised of a different material than the material of active layer106. Similarly, region107may be comprised of the same material as semiconductor layer106or a different material. Moreover, the material in region105and region107may also differ.

One example of a process that produces a region105having a material that differs from active layer106is a source/drain refill process. In a source/drain refill process, a significant portion of at least some regions (e.g., PMOS regions) of active layer106are etched or otherwise removed. The resulting void is then filled, usually with an epitaxial process, with a semiconductor material having a different lattice constant that the lattice constant of active layer106. If active layer106is silicon, for example, region105may be comprised of silicon germanium or silicon carbide. When the material in region105and/or107has a lattice constant that is different than the material of active layer106, compressive or tensile stress results.

Another example of a stress producing process includes the deposition of a material on the active layer106where the deposited material has a different lattice constant than active layer106. For example, region107might represent a film such as silicon nitride deposited overlying active layer106. Silicon nitride can create either compressive or tensile stress depending upon the deposition parameters and the impurities introduced in the silicon nitride film.

Stress, when properly restricted to appropriate regions of the wafer, advantageously enhances carrier mobility resulting in better performing transistors. Isolation structure100beneficially prevents transmission of stress from one region of the wafer to another region. The isolation structure100depicted inFIG. 7includes a first and relatively flowable dielectric130within an isolation trench formed in the substrate and a capping dielectric135overlying the flowable dielectric. The depicted embodiment of dielectric structure100further includes an oxide liner120and a silicon nitride liner122formed on sidewalls of the trench. Trench isolation structure100as depicted inFIG. 7extends through an active semiconductor layer106of an SOI wafer and partially into the underlying BOX layer104.

The use of flowable dielectric130within isolation structure100creates a stress absorbing structure that is able to prevent the transfer of stress from first region105of wafer101, which is adjacent to a first side of trench isolation structure100, to second region107of wafer101, which is adjacent to a second side of trench isolation structure100. This stress absorbing characteristic is most beneficial when the stress within first region105differs from the stress within second region107. Although the depicted implementation shows region107as a relatively thin film deposited overlying the existing active layer106and region105as a relatively thick film that replaces a substantial portion of active layer106, other embodiments are possible. For example, regions105and107may both be relatively thick films that replace substantial portions of active layer106. Similarly regions105and107may both be relatively thin films deposited overlying the existing active layer. Finally, other embodiments may omit either region105or107so that, on one side of trench100, the original active layer106remains intact.

As indicated above, various mobility enhancing applications use materials designed to create compressive or tensile stress within the active layer106of wafer101. A hole mobility application might use silicon germanium in first region105of substrate106where first region105represents a PMOS region of wafer101(a region where PMOS transistors are formed). If the separation between adjacent devices of different conductivity types is below a threshold value, the stress created within a PMOS region of wafer101might transfer through the isolation structure to an adjacent NMOS region, where the stress would have a negative impact on NMOS carrier mobility, unless the isolation structure exhibits the stress absorbing characteristics of trench isolation structure100.

Referring now toFIG. 8throughFIG. 12, a processing sequence in which a stress absorbing isolation trench formation process, such as the process described above with respect toFIG. 1throughFIG. 7, is integrated into a process that also employs more conventional trench isolation structures. Referring toFIG. 8, first and second isolation trenches201and202have been formed in wafer101. The first isolation trench201is a relatively wide trench while second isolation trench202is relatively narrow. Generally speaking, the stress absorbing characteristics of isolation trench structure100described above are needed for narrow isolation trenches (i.e., trenches having a lateral dimension of less than 1000 nm) while conventional trench isolation structures may be preferable for wider isolation structures. It is known that conventional shallow trench isolation exerts a compressive stress on the enclosed active area. The compressive stress in the longitudinal direction is advantageous to PMOS transistor but detrimental to NMOS. Therefore, it might be desirable to isolate the NMOS active area with shallow trench isolation exhibiting the reflowable oxide fill and thus provide relief to the longitudinal compressive stress component.

InFIG. 9, first isolation trench201and second isolation trench202ofFIG. 8have been filled with a conventional trench isolation dielectric (e.g., TEOS) and polished or otherwise planarized to form first and second isolation structures204and206respectively. InFIG. 10, a patterned mask208is formed to expose the second isolation trench206. In one embodiment, the patterned mask208is a hard mask analogous to mask108described above while, in other embodiments, patterned mask208is a photoresist mask. In the latter case, the dimensions and registration of the mask are not critical. InFIG. 11, the second isolation trench structure206ofFIG. 10is removed with an oxide etch that is selective to mask108. Following removal of the second isolation structure206, processing analogous to the processing described above with respect toFIG. 1throughFIG. 7is performed to produce a stress absorbing trench isolation structure100in the relative narrow isolation trench and a conventional trench isolation structure204in the relatively wide isolation trench.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and modifications of various materials and processing steps are intended to be included within the scope of present invention.