SEMICONDUCTOR DEVICE

A semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures each include a pillar portion in contact with the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2021-0181313 filed on Dec. 17, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Embodiments relate to a semiconductor device.

2. Description of the Related Art

As highly integrated and miniaturized semiconductor devices are in demand, capacitors of the semiconductor devices also have been miniaturized.

SUMMARY

The embodiments may be realized by providing a semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on at least a portion of an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein each of the lower electrode structures includes a pillar portion in contact with each of the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

The embodiments may be realized by providing a semiconductor device including a lower electrode structure including a pillar portion and a cylinder portion on the pillar portion and extending from the pillar portion; a dielectric layer on the lower electrode structure; and an upper electrode structure on the dielectric layer, wherein the pillar portion includes a first lower electrode layer and a second lower electrode layer on the first lower electrode layer.

The embodiments may be realized by providing a semiconductor device including a substrate; storage node contacts on the substrate; and capacitors respectively on the storage node contacts, wherein each of the capacitors includes lower electrode structures including a pillar portion and a cylinder portion on the pillar portion; a dielectric layer on the lower electrode structures; and an upper electrode structure on the dielectric layer, and the pillar portion includes a first lower electrode layer and a second lower electrode layer on the first lower electrode layer.

DETAILED DESCRIPTION

In addition, terms, such as “upper”, “middle”, “lower” and the like, are used to distinguish between relative positions of components, but example embodiments are not limited by these terms. Accordingly, the terms, such as “upper”, “middle”, “lower” and the like, could be termed “first”, “second”, “third” and the like, and used to describe components of the specification. However, the components are not limited by the terms, and “first component” may be referred to as “second component.” For example, as used herein, the terms “first,” “second,” and the like are merely for identification and differentiation, and are not intended to imply or require sequential inclusion (e.g., a third element and a fourth element may be described without implying or requiring the presence of a first element or second element).

Hereinafter, a semiconductor device according to example embodiments will be described with reference toFIGS.1and2.

FIG.1is a schematic layout diagram of a semiconductor device100according to example embodiments, andFIG.2is a schematic cross-sectional view of the semiconductor device100according to example embodiments.FIG.2is a cross-sectional view taken along line I-I′ ofFIG.1.

Referring toFIGS.1and2, the semiconductor device100may include a substrate110, a storage node contact150on the substrate110, and a capacitor CP in contact with the storage node contact150. The semiconductor device100may further include a landing pad155between the storage node contact150and the capacitor CP.

The substrate110may include a semiconductor material, e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In an implementation, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate110may further include impurities. The substrate110may include, e.g., a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

The substrate110may include a device isolation region120and active regions125defined by the device isolation region120.

The active regions125may have a bar shape, and may be disposed in an island shape extending in one direction within the substrate110. In an implementation, the active regions125may be inclined at a predetermined angle with respect to an X-direction and a Y-direction, and may include a plurality of active regions repeatedly arranged at regular intervals. Due to the inclined arrangement of the active regions125, cell density per unit area of the substrate110may be increased while securing a separation distance between neighboring active regions125.

The active regions125may have first and second impurity regions having a predetermined depth from an upper surface of the substrate110. The first and second impurity regions may be spaced apart from each other. The first and second impurity regions may be provided as source/drain regions of a transistor formed by a wordline (a gate electrode layer133). In an implementation, depths of the first and second impurity regions in a source region and a drain region may be different from each other.

The device isolation region120may be formed by a shallow trench isolation (STI) process. The device isolation region120may electrically isolate the active regions from each other while surrounding the active regions125. The device isolation region120may be formed of an insulating material, e.g., a silicon oxide, a silicon nitride, or a combination thereof. The device isolation region120may include a plurality of regions having bottom depths, different depending on a width of a trench in which the substrate110has been etched. The device isolation region120may define active regions125.

The substrate110may further include a buried gate structure130buried in the substrate110to extend in a first direction (a Y-direction).

The buried gate structure130may include a gate electrode layer133, a gate dielectric layer136, and a gate capping layer139. The gate electrode layer133may be provided in a line shape extending in the first direction (the Y-direction) to constitute a wordline. The wordline may cross the active region125and extend (e.g., lengthwise) in the first direction (the Y-direction). In an implementation, a pair of adjacent wordlines may cross one active region125.

An upper surface of the gate electrode layer133may be on a level that is lower than a level of an upper surface of the substrate110. High and low of the term “level” used herein may be defined based on a substantially planar upper surface. In an implementation, the gate electrode layer133may constitute a gate of a buried channel array transistor (BCAT). In an implementation, the gate electrode layer133may have a shape on the substrate110.

The gate electrode layer133may include a conductive material, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or aluminum (Al). In an implementation, the gate electrode layer133may have a double-layer structure in which two layers are formed of different materials.

The gate dielectric layer136may conformally cover a side surface and a bottom surface of the gate electrode layer133. The gate dielectric layer136may include, e.g., a silicon oxide, a silicon nitride, or a silicon oxynitride.

The gate capping layer139may be on the gate electrode layer133. The gate capping layer139may include an insulating material, e.g., a silicon nitride.

The semiconductor device100may further include an interlayer insulating layer140on the substrate110. The interlayer insulating layer140may include a plurality of interlayer insulating layers. The interlayer insulating layer140may include, e.g., first to third interlayer insulating layers143,146, and149. Each of the first to third interlayer insulating layers143,146, and149may include an insulating material. In an implementation, the first to third interlayer insulating layers143,146, and149may include, e.g., a silicon oxide, a silicon nitride, or a silicon oxynitride.

The storage node contact150may be on the substrate110. The storage node contact150may be formed through at least a portion of the interlayer insulating layer140. In an implementation, the storage node contact150may extend through the first and second interlayer insulating layers143and146.

The storage node contact150may be connected to one region of the active region125. The storage node contact150may be between wordlines (gate electrode layers133). A lower surface of the storage node contact150may be on or at a level that is lower than a level of an upper surface of the substrate110. The storage node contact150may include a conductive material. In an implementation, the storage node contact150may be formed of, e.g., doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

The semiconductor device100may further include a landing pad155between the storage node contact150and the capacitor CP. The landing pad155may electrically connect the storage node contact150and the lower electrode structure170of the capacitor CP to each other. The landing pad155may be on the storage node contact150and may penetrate through at least a portion of the interlayer insulating layer140. In an implementation, the landing pad155may penetrate through the third interlayer insulating layer149. The landing pad155may include a conductive material, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN).

The semiconductor device100may further include an etch-stop layer160on the interlayer insulating layer140. The lower electrode structure170of the capacitor CP may penetrate through the etch-stop layer160to be in contact with the landing pad155. The etch-stop layer160may include an insulating material having etch selectivity with respect to molding layers (ML1, ML2, and ML3ofFIG.6A) under a specific etching condition. In an implementation, when the molding layers (ML1, ML2, ML3ofFIG.6A) include a silicon oxide, the etch-stop layer160may include, e.g., a silicon nitride (SiN) or a silicon carbonitride (SiCN).

The capacitor CP may include a lower electrode structure170, a dielectric layer180, and an upper electrode structure190. A supporter structure SS may be on a side surface of the lower electrode structure170of the capacitor CP.

The lower electrode structure170may be in contact with the landing pad155through the etch-stop layer160.

The lower electrode structure170may include a first lower electrode layer171and a second lower electrode layer173on the first lower electrode layer171. In an implementation, the first and second lower electrode layers171and173may each include, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or aluminum (Al).

The first lower electrode layer171may have a cylindrical shape having a lower surface and side surfaces. The second lower electrode layer173may include a first portion173L, covering at least an internal wall of the first lower electrode layer171, and a second portion extending from the first portion173L and covering an upper end of the first lower electrode layer171. The second portion may include a first sidewall portion173F and a second sidewall portion173S. The first portion173L may fill a portion or an entirety of an empty space defined by the cylindrical shape of the first lower electrode layer171. The first sidewall portion173F and the second sidewall portion173S may extend from the first portion173L to cover the upper end of the first lower electrode layer171. The second portion may include a side surface aligned with at least a portion of the side surface of the first lower electrode layer171.

The lower electrode structure170may include a pillar portion170P and a cylinder portion170C on the pillar portion170P. The first lower electrode layer171and the first portion173L of the second lower electrode layer173may constitute a pillar portion170P. The first and second sidewall portions173F and173S of the second lower electrode layer173may constitute a cylinder portion170C.

In an implementation, the pillar portion170P may extend to a level between the first supporter layer SS1and the second supporter layer SS2. The first sidewall portion173F may extend from the first portion173L, e.g., to a level of an upper surface of the third supporter layer SS3. The second sidewall portion173S may extend from the first portion173L to a level that is lower than a level of the first sidewall portion173F. In an implementation, the second sidewall portion173S may extend to a level that is lower than or equal to a level of a lower surface of the third supporter layer SS3.

In an implementation, the first lower electrode structure170may include projections P1, P2, and P3protruding (e.g., outwardly) toward the supporter structure SS. The first projection P1may protrude from the first lower electrode layer171toward the first supporter layer SS1. The second projection P2may protrude from the first sidewall portion173F toward the second supporter layer SS2. The third projection P3may protrude from the first sidewall portion173F toward the third supporter layer SS3.

In an implementation, the second sidewall portion173S may have a shape of which width is decreased in a direction toward an upper portion. In an implementation, one side surface of the second sidewall portion173S may be perpendicular to the substrate110, and the other side surface thereof may have a shape inclined toward the one side surface. A ratio of the pillar portion170P to the cylinder portion170C, the shape of the cylinder portion170C, the shape of the supporter structure SS, and the like, may vary according to example embodiments.

As described above, the capacitor CP according to example embodiments may include the pillar portion170P, at a lower portion thereof, and the cylinder portion170C at an upper portion thereof. The capacitor CP may include the pillar portion170P to help uniformly adsorb the dielectric layer180, and may include the cylinder portion170C to help secure capacitance for a semiconductor device. Electrical characteristics of the capacitor CP according to example embodiments may be improved.

The semiconductor device100may include a plurality of capacitors CP. Each of the capacitors CP may include first and second lower electrode layers171and173having the same height. Also, each of the capacitors CP may include a pillar portion170P and a cylinder portion170C having the same height. Accordingly, each of the capacitors CP may have constant capacitance.

The supporter structure SS may be on a side surface of the lower electrode structure170. In an implementation, the supporter structure SS may include a plurality of supporter layers, e.g., first to third supporter layers SS1, SS2, and SS3. The first to third supporter layers SS1, SS2, and SS3may be spaced apart from each other in a Z direction, perpendicular to the upper surface of the substrate110, and may extend in a horizontal direction, perpendicular to the Z direction.

The first to third supporter layers SS1, SS2, and SS3may be in contact with the plurality of lower electrode structures170, and may connect a plurality of adjacent lower electrode structures170to each other. In an implementation, the first supporter layer SS1may be in contact with an external surface of the pillar portion170P, and the second and third supporter layers SS2and SS3may be in contact with an external surface of the cylinder portion170C. In an implementation, the first supporter layer SS1may be in contact with the first lower electrode layer171of the pillar portion170P, and the second supporter layer SS2may be in contact with the first sidewall portion173F of the cylinder portion170C.

The first to third supporter layers SS1, SS2, and SS3may be a structure supporting a plurality of lower electrode structures170having a high aspect ratio. The first to third supporter layers SS1, SS2, and SS3may include, e.g., a silicon oxide, a silicon nitride, or a silicon oxynitride.

In an implementation, the first and second supporter layers SS1and SS2may have a thickness (e.g., in the vertical Z direction) that is smaller than a thickness of the third supporter layer SS3. A distance (in the Z direction) between an upper surface of the interlayer insulating layer140and a lower surface of the first supporter layer SS1may be greater than a distance (in the Z direction) between an upper surface of the first supporter layer SS1and a lower surface of the second supporter layer SS2. The distance (in the Z direction) between the upper surface of the first supporter layer SS1and the lower surface of the second supporter layer SS2may be greater than a distance (in the Z direction) between an upper surface of the second supporter layer SS2and a lower surface of the third supporter layer SS3.

The dielectric layer180may be on the etch-stop layer160and may cover the lower electrode structure170and the supporter structure SS. The dielectric layer180may conformally cover upper surfaces and side surfaces of the plurality of lower electrode structures170, an upper surface of the etch-stop layer160, and exposed surfaces of the supporter structure SS. In an implementation, the dielectric layer180may include a portion extending inwardly or in the pillar portion170P of the lower electrode structure170.

The dielectric layer180may include, e.g., a high-k dielectric material, a silicon oxide, a silicon nitride, or combinations thereof. In an implementation, the dielectric layer180may include, e.g., an oxide, a nitride, a silicide, an oxynitride, or a silicic acid including hafnium (Hf), aluminum (Al), zirconium (Zr), or lanthanum (La).

The upper electrode structure190may be a structure covering the plurality of lower electrode structures170, the supporter structure SS, and the dielectric layer180. The upper electrode structure190may be a structure filling a space between the plurality of lower electrode structures170and a space between the supporter structures SS.

The upper electrode structure190may include a single upper electrode layer or a plurality of upper electrode layers. In an implementation, the upper electrode structure190may include a first upper electrode layer191and a second upper electrode layer192sequentially on the lower electrode structure170.

The first upper electrode layer191may be a conductive layer conformally covering the dielectric layer180. The first upper electrode layer191may include a metal-containing material, e.g., a titanium nitride (TiN).

The second upper electrode layer192may fill the space between the plurality of lower electrode structures170and the space between the supporter structures SS while covering the first upper electrode layer191. The second upper electrode layer192may include a semiconductor material, e.g., polycrystalline silicon (Si) containing impurities.

FIGS.3to5are schematic cross-sectional views of semiconductor devices according to example embodiments.

The example embodiments ofFIGS.3to5are different from the previous embodiments ofFIGS.1and2in shape, structure, or the like, of a capacitor. In the example embodiments ofFIGS.3to5, the same reference numerals as those ofFIGS.1and2but different alphabets are used to describe example embodiments, different from the example embodiment ofFIGS.1and2. Features described with the same reference numerals described above may be the same or similar.

The semiconductor device100aofFIG.3is different from the semiconductor device100according to the example embodiment ofFIGS.1and2, in a (e.g., height) ratio of a pillar portion170Pa and a cylinder portion170Ca of a capacitor CPa.

Referring toFIG.3, the pillar portion170Pa may extend only to a level between an etch-stop layer160and a first supporter layer SS1. The cylinder portion170Ca may be on the pillar portion170Pa. The cylinder portion170Ca may extend from the level between the etch-stop layer160and the first supporter layer SS1to a level of an upper surface of a third supporter layer SS3. The cylinder portion170Ca may have a height in the Z direction that is greater than a height of the pillar portion170Pa.

In the cylinder portion170Ca, a dielectric layer180may be on internal surfaces and external surfaces of the first and second sidewall portions173Fa and173Sa. The dielectric layer180may be on an external surface of the pillar portion170Pa. As a ratio of the height of the cylinder portion170Ca to a total height of the capacitor CPa is increased, capacitance of the capacitor CPa may be increased. The capacitor CPa illustrated inFIG.3may have capacitance that is higher than the capacitance of the capacitor CP illustrated inFIGS.1and2.

In an implementation, the ratio of the height of the cylinder portion170Ca to the total height of the capacitor CPa may vary depending on capacitance of a product, a size and a shape of a capacitor, a thickness of a dielectric layer, or the like.

The semiconductor device100bofFIG.4is different from the semiconductor device100according to the example embodiment ofFIGS.1and2, in shapes of a pillar portion170Pb and a dielectric layer180b.

Referring toFIG.4, the pillar portion170Pb may not include a seam therein.

The dielectric layer180bmay be conformally on an upper surface and side surfaces of a lower electrode structure170b.The dielectric layer180bmay be on an upper surface of the pillar portion170Pb of the lower electrode structure170b,and may not extend inwardly or inside of the pillar portion170Pb. The shape of the pillar portion170Pb and the dielectric layer180bmay vary depending on sizes of the capacitors CPb and a gap therebetween, thicknesses and materials of the first and second lower electrode layers171and173b,and the like.

The semiconductor device100cofFIG.5is different from the semiconductor device100according to the example embodiment ofFIGS.1and2, in a shape of a cylinder portion170Cc.

Referring toFIG.5, first and second sidewalls173Fc and173Sc of the cylinder portion170Cc may have the same shape. The first and second sidewalls173Fc and173Sc may extend to a level of an upper surface of the third supporter layer SS3. In an implementation, the first and second sidewalls173Fc and173Sc may have a uniform width throughout an entire height thereof. In an implementation, the shapes of the first and second sidewalls173Fc and173Sc may vary depending on a method of etching molding layers (ML1, ML2, ML3ofFIG.6A, and the like) and preliminary supporter layers (SL1, SL2, SL3ofFIG.6A, and the like) during a fabrication process.

FIGS.6A to6Nare schematic cross-sectional views of stages in a method of fabricating a semiconductor device according to example embodiments.FIGS.6A to6Nillustrate cross-sections corresponding to the cross-section ofFIG.2.

Referring toFIG.6A, a lower structure including the substrate110may be formed, and molding layers ML1, ML2, and ML3and preliminary supporter layers SL1, SL2, and SL3may be alternately stacked on the lower structure. Holes H may be formed to penetrate through the molding layers ML1, ML2, and ML3and the preliminary supporter layers SL1, SL2, and SL3.

Active regions125and device isolation regions120(defining the active regions125) may be formed on the substrate110. A portion of the substrate110may be removed to form trenches extending (e.g., lengthwise) in a first direction (a Y-direction), and buried gate structures130may be formed in the trenches. Impurity regions may be formed on opposite sides adjacent to the buried gate structures130, and bitline structures may be formed in a second direction (an X-direction) intersecting the first direction (the Y-direction).

First and second interlayer insulating layers143and146may be formed to cover the substrate110. An opening may be formed through the first and second interlayer insulating layers143and146to expose a portion of the active region125. The opening may be filled with a conductive material to form storage node contacts150. In an implementation, the storage node contacts150may include, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or aluminum (Al).

A third interlayer insulating layer149may be formed to cover the second interlayer insulating layer146and the storage node contacts150. An opening may be formed through the third interlayer insulating layer149to expose at least a portion of the storage node contacts150. The opening may be filled with a conductive material to form landing pads155. In an implementation, the landing pads155may include, e.g., doped polycrystalline silicon (Si).

An etch-stop layer160may be formed to cover the third interlayer insulating layer149and the landing pads155. The etch-stop layer160may include an insulating material having etching selectivity with respect to the molding layers ML1, ML2, and ML3under a specific etching condition. In an implementation, when the molding layers ML1, ML2, and ML3include a silicon oxide, the etch-stop layer160may include, e.g., a silicon nitride (SiN) or a silicon carbonitride (SiCN).

The molding layers ML1, ML2, and ML3and the preliminary supporter layers

SL1, SL2, and SL3may be alternately stacked on the etch-stop layer160to form a stack structure D. In an implementation, each of the molding layers ML1, ML2, ML3and the preliminary supporter layers SL1, SL2, and SL3may include three layers. The molding layers ML1, ML2, ML3and the preliminary supporter layers SL1, SL2, and SL3may have the same thickness or different thicknesses. In an implementation, the first molding layer ML1may have a thickness (e.g., in the Z direction) that is greater than a thickness of the second molding layer ML2, and the second molding layer ML2may have a thickness that is greater than a thickness of the third molding layer ML3. The third preliminary supporter layer SL3may have a thickness that is greater than a thickness of each of the first and second preliminary supporter layers SL1and SL2.

The holes H may be formed to penetrate through the stack structure D. The holes H may penetrate through the etch-stop layer160to expose the landing pad155.

Referring toFIG.6B, a first preliminary lower electrode layer171′ may be conformally formed in the holes H and on an upper surface of the stack structure D. The first preliminary lower electrode layer171′ may be formed to have a thickness that is smaller than a diameter of each of the holes H.

The first preliminary lower electrode layer171′ may be formed by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The first preliminary lower electrode layer171′ may include a conductive material. In an implementation, the first preliminary lower electrode layer171′ may include, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN), or aluminum (Al).

Referring toFIG.6C, a sacrificial layer OM may be formed on the upper surface of the first preliminary lower electrode layer171′. The first preliminary lower electrode layer171′ may be formed to fill the holes H and to cover the stacked structure D.

The sacrificial layer OM may include an organic material. The organic material included in the sacrificial layer OM, may have a low viscosity and may be easily removed in a process to be described below. In an implementation, the sacrificial layer OM may include a bottom anti-reflection coating (BARC). In an implementation, the sacrificial layer OM may include a heat eliminable polymer (HELP). The HELP may be adsorbed in a device in a solid form at a temperature of 170 degrees Celsius or less, and may be removed by thermal decomposition in a gaseous form at a temperature of 170 degrees Celsius or more. When the sacrificial layer OM includes a HELP, a process of forming the sacrificial layer OM may be performed at a temperature of 170 degrees or less.

The sacrificial layer OM including an organic material may be formed on the first preliminary lower electrode layer171′ in the process ofFIG.6Cto coat the inside of the hole H without a seam. If the hole H were to be filled with a conductive material such as a titanium nitride (TiN), a morphology of the conductive material may not be uniform, so that a seam could be formed in the hole H. If the conductive material were to be etched in such a state, a non-uniform distribution of recesses could occur. Therefore, a length of a single cylinder stack could vary for each of a plurality of capacitors, resulting in non-uniform capacitance.

In the process ofFIG.6C, the first preliminary lower electrode layer171′ may be conformally formed in the holes H, and the holes H may then be filled with a sacrificial layer OM including an organic material. Thus, the holes H may be filled without the seam.

Referring toFIG.6D, portions of the sacrificial layer OM on the stack structure

D may be removed. In an implementation, the sacrificial layer OM may be removed by a (e.g., wet) etching process using hydrogen gas (H2) and nitrogen gas (N2). In an implementation, the etching process may vary depending on the type of an organic material included in the sacrificial layer OM.

Referring toFIG.6E, at least a portion of the sacrificial layer OM in the holes H may be removed. As a method of removing the sacrificial layer OM, the etching described above with reference toFIG.6Dmay be applied.

A seam may not be formed in the sacrificial layer OM in the holes H, and the sacrificial layer OM may be etched to the same depth in each of the holes H. The sacrificial layers OM, respectively remaining in the plurality of holes H, may have the same height. In an implementation, the sacrificial layer OM may be etched to a depth between the first preliminary supporter layer SL1and the second preliminary supporter layer SL2. In an implementation, when the sacrificial layer OM is etched to a depth between the etch-stop layer160and the first preliminary supporter layer SL1, the capacitor CPa illustrated inFIG.3may be formed.

Referring toFIG.6F, at least a portion of the first preliminary lower electrode layer171′, on an upper surface of the stack structure D and in the holes H, may be etched.

The first preliminary lower electrode layer171′ may be etched to the same height as the sacrificial layer OM remaining in the holes H. The sacrificial layers OM, respectively remaining in the plurality of holes H, may have the same height, and the first preliminary lower electrode layers171′ in the plurality of holes H may also be etched to have the same height.

Referring toFIG.6G, all (e.g., remaining portions) of the sacrificial layers OM in the holes H may be removed. In an implementation, a method of removing the sacrificial layer OM may include the etching described above with reference toFIG.6D. In an implementation, when the sacrificial layer OM includes a HELP, the sacrificial layer OM may be removed by thermal decomposition at a temperature of 170 degrees Celsius or more.

A first preliminary lower electrode layer171′ having a cylindrical shape having a lower surface may be formed in each of the holes H. The first preliminary lower electrode layers171′, respectively formed in the holes H, may have the same height.

Referring toFIG.6H, a second preliminary lower electrode layer173′ may be formed in each of the holes H and on the upper surface of the stack structure D.

A first portion173L′ of the second preliminary lower electrode layer173′ may be formed to cover the first preliminary lower electrode layer171′ in each of the holes H. The first portion173L′ may fill a portion or an entirety of a space defined by or within the first preliminary lower electrode layer171′. The first preliminary lower electrode layer171′ and the first portion173L′ may form a pillar shape.

In an implementation, a seam may be formed between the first portions173L′. In an implementation, an entire internal space of the first preliminary lower electrode layer171′ may be filled without a seam, depending on a size of the holes H, a thickness and a material of the second preliminary lower electrode layer173′, or the like. In this case, the capacitor CPb illustrated inFIG.4may be formed.

A second portion173U′ of the second preliminary lower electrode layer173′ may cover a side surface of the holes H on which the first preliminary lower electrode layer171′ is not formed (e.g., has been removed). The second portion173U′ may have a cylindrical shape.

The third portion173T′ of the second preliminary lower electrode layer173′ may be formed to cover the upper surface of the stack structure D.

The second preliminary lower electrode layer173′ may include a conductive material. In an implementation, the second preliminary lower electrode layer173′ may include, e.g., polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or aluminum (Al).

Referring toFIG.6I, the second preliminary lower electrode layer173′ may be etched to remove a third portion173T′. In the holes H, the first preliminary lower electrode layer171′ and the first portion173L′ of and the second lower electrode layer173′ may have a pillar shape, and the second portion173U′ of the second lower electrode layer173′ may have a cylindrical shape.

Referring toFIG.6J, a mask M may be formed on the stacked structure D. The mask M may serve as an etching mask used to etch the first to third molding layers ML1, ML2, and ML3. The mask M may define a region in which the lower electrode structure170ofFIG.2is disposed. The mask M may have a structure including a hole-shaped openings.

Referring toFIG.6K, by using the mask M as an etching mask, the molding layers ML1, ML2, and ML3may be removed and portions of the preliminary supporter layers SL1, SL2, and SL3may be removed.

An etching process may be performed on portions of the molding layers ML1, ML2, and ML3and the preliminary supporter layers SL1, SL2, and SL3which do not overlap the mask M in the Z direction. In an implementation, the third preliminary supporter layer SL3may be etched by an anisotropic etching process, and the third molding layer ML3may be removed by an isotropic etching process before the second preliminary supporter layer SL2is etched. Similarly, the second preliminary supporter layer SL2may be etched by an anisotropic etching process, and the second molding layer ML2may be removed by an isotropic etching process before the first preliminary supporter layer SL1is etched. After the first preliminary supporter layer SL1is etched by an anisotropic etching process, the first molding layer ML1may be removed by an isotropic etching process. The mask M may be removed after etching the molding layers ML1, ML2, and ML3or while etching the molding layers ML1, ML2, and ML3.

Referring toFIG.6L, an etching process may be performed to reduce the thickness of the preliminary lower electrode structure170′ to form a lower electrode structure170.

An etching process ofFIG.6Lmay be performed to increase a gap between the adjacent lower electrode structures170. Accordingly, occurrence of a short-circuit between the lower electrode structures170may be prevented. The lower electrode structure170may have a shape, similar to the shape of the preliminary lower electrode structure170′, except that a thickness thereof is decreased.

Portions of the preliminary lower electrode structures, adjacent to the preliminary supporter layers SL1, SL2, and SL3ofFIG.6K, may remain without being etched. The remaining portions of the preliminary supporter layers (SL1, SL2, and SL3ofFIG.6K) may be defined as first to third supporter layers SS1, SS3, and SS3. The first to third supporter layers SS1, SS2, and SS3may be on side surfaces of the lower electrode structures170to connect lower electrode structures adjacent to each other, among the lower electrode structures170.

The portions of the lower electrode structure170, adjacent to the first to third supporter layers SS1, SS2, and SS3, may remain without being etched. As a result, projections P1, P2, and P3may be formed to protrude (e.g., outwardly) from the lower electrode structure170toward the first to third supporter layers SS1, SS2, and SS3. In an implementation, the first projection P1may protrude from the first lower electrode layer171to be in contact (e.g., direct contact) with the first supporter layer SS1. The second projection P2may protrude from the first sidewall portion173F of the second lower electrode layer173to be in contact (e.g., direct contact) with the second supporter layer SS2. The third projection P3may protrude from the first sidewall portion173F of the second lower electrode layer173to be in contact (e.g., direct contact) with the third supporter layer SS3.

Referring toFIG.6M, a dielectric layer180may be formed to cover the plurality of lower electrode structures170and the first to third supporter layers SS1, SS2, and SS3connected to the plurality of lower electrode structures170.

The dielectric layer180may conformally cover upper surfaces and side surfaces of the plurality of lower electrode structures170, an upper surface of the etch-stop layer160, and exposed surfaces of the first to third supporter layers SS1, SS2, and SS3. When a seam is formed in the first portion173L of the second lower electrode layer173, the dielectric layer180may extend to also fill the seam. The dielectric layer180may include, e.g., a high-k dielectric material, a silicon oxide, a silicon nitride, a silicon oxynitride, or combinations thereof.

Referring toFIG.6N, a first upper electrode layer191may be formed on the dielectric layer180. The first upper electrode layer191may conformally cover the dielectric layer180. The first upper electrode layer191may include, e.g., a titanium nitride (TiN).

Returning toFIG.2, a second upper electrode layer192may be formed on the first upper electrode layer191.

The second upper electrode layer192may fill a space between the plurality of lower electrode structures170, and may cover the plurality of lower electrode structures170and the first to third supporter layers SS1, SS2, and SS3.

The second upper electrode layer192may include a semiconductor material, e.g., polycrystalline silicon (Si) containing impurities. The second upper electrode layer192may constitute the upper electrode structure190together with the first upper electrode layer191.

The lower electrode structure170of the capacitor CP according to example embodiments may be formed by adsorbing or depositing lower electrode layers twice (e.g., two separate deposition or formation processes). When the lower electrode structure170of the capacitor CP is analyzed using a transmission electron microscopy (TEM), the first and second lower electrode layers171and173may be identified.

In an implementation, in the pillar portion170P of the lower electrode structure170, a first lower electrode layer171having a cylindrical shape having a lower surface and a side surface and a first portion173L of a second lower electrode layer173filling an internal space of the first lower electrode layer171may be provided. The first portion173L of the lower electrode layer173may be identified. Sidewall portions173F and173S, extending from the first portion173L of the second lower electrode layer173, may be identified in the cylinder portion170C of the lower electrode structure170.

FIGS.7and8illustrate a semiconductor device200according to example embodiments.

FIG.7is a layout diagram of the semiconductor device200according to example embodiments.FIG.8is a cross-sectional view of a semiconductor device according to example embodiments.FIG.8is a cross-sectional view taken along lines II-II′ and III-III′ ofFIG.7.

Referring toFIGS.7and8, the semiconductor device200may include a substrate210, a plurality of first conductive lines220, a channel layer230, a gate electrode layer240, a gate insulating layer250, and a capacitor CP. The semiconductor device200may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which a channel length of the channel layer230is increased from the substrate210in a vertical direction.

A lower insulating layer212may be on the substrate210, and a plurality of first conductive lines220may be spaced apart from each other in the X-direction and may extend (e.g., lengthwise) in the Y-direction on the lower insulating layer212. A plurality of first insulating patterns222may be on the lower insulating layer212to fill a space between the plurality of first conductive lines220. The plurality of first insulating patterns222may extend in the Y-direction, and upper surfaces of the plurality of first insulating patterns222may be at the same level as upper surfaces of the plurality of first conductive lines220. The plurality of first conductive lines220may function as bitlines of the semiconductor device200.

In an implementation, the plurality of first conductive lines220may include doped polycrystalline silicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. In an implementation, the plurality of first conductive lines220may be formed of, e.g., doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof. The plurality of first conductive lines220may include a single layer or multiple layers of the above-mentioned materials. In an implementation, the plurality of first conductive lines220may include a two-dimensional semiconductor material. In an implementation, the two-dimensional semiconductor material may include, e.g., graphene, carbon nanotubes, or a combination thereof.

The channel layer230may be arranged in a matrix form spaced apart in the X-direction and the Y-directions on the plurality of first conductive lines220. The channel layer230may have a first width in the X-direction and a first height in the Z-direction, and the first height may be greater than the first width. In an implementation, the first height may be, e.g., about 2 to 10 times the first width. A bottom portion of the channel layer230may serve as a first source/drain region, an upper portion of the channel layer230may serve as a second source/drain region, and a portion of the channel layer230between the first and second source/drain regions may serve as a channel region.

In an implementation, the channel layer230may include an oxide semiconductor. In an implementation, the oxide semiconductor may include, e.g., InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInzO, HfxInn, AlxZnySnzO, YbxGayZnzO, InxGayO, or combinations thereof. The channel layer230may include a single layer or multiple layers of an oxide semiconductor. In an implementation, the channel layer230may have bandgap energy, greater than bandgap energy of silicon. In an implementation, the channel layer230may have bandgap energy of about 1.5 eV to about 5.6 eV. In an implementation, the channel layer230may have optimal channel performance when having bandgap energy of about 2.0 eV to 4.0 eV. In an implementation, the channel layer230may be polycrystalline or amorphous. In an implementation, the channel layer230may include a two-dimensional semiconductor material. In an implementation, the two-dimensional semiconductor material may include, e.g., graphene, carbon nanotubes, or a combination thereof

The gate electrode layer240may extend in the X-direction on opposite sidewalls of the channel layer230. The gate electrode layer240may include a first sub-gate electrode240P1, facing a first sidewall of the channel layer230, and a second sub-gate electrode240P2facing a second sidewall opposing the first sidewall of the channel layer230. A single channel layer230may be between the first sub-gate electrode240P1and the second sub-gate electrode240P2, and the semiconductor device200may have a dual-gate transistor structure. In an implementation, a single-gate transistor structure may be implemented by omitting the second sub-gate electrode240P2and forming only the first sub-gate electrode240P1facing the first sidewall of the channel layer230.

The gate insulating layer250may surround a sidewall of the channel layer230, and may be between the channel layer230and the gate electrode layer240. In an implementation, an entire sidewall of the channel layer230may be surrounded by the gate insulating layer250and a portion of the sidewall of the gate electrode layer240may be in contact with the gate insulating layer250, as illustrated inFIG.7. In an implementation, the gate insulating layer250may extend in a direction in which the gate electrode layer240extends (e.g., the first or X direction), and among sidewalls of the channel layer230, only two sidewalls facing the gate electrode layer240may be in contact with the gate insulating layer250.

In an implementation, the gate insulating layer250may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant higher than a dielectric constant of the silicon oxide layer, or combinations thereof. The high-k dielectric layer may be formed of a metal oxide or a metal oxynitride. In an implementation, a high-k dielectric layer, available as the gate insulating layer250, may be formed of, e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof.

A plurality of second insulating patterns232may extend in the second or Y direction on a plurality of first insulating patterns222, and a channel layer230may be between two adjacent second insulating patterns232, among the plurality of second insulating patterns232. In an implementation, a first buried layer234and a second buried layer236may be in a space between two adjacent channel layers230, between two adjacent second insulating patterns232. The first buried layer234may be in a bottom portion of the space between the two adjacent channel layers230, and the second buried layer236may be formed to fill the other portion of the space between the two adjacent channel layers230on the first buried layer234. An upper surface of the second buried layer236may be on the same level as an upper surface of the channel layer230, and the second buried layer236may cover the upper surface of the gate electrode layer240. In an implementation, the plurality of second insulating patterns232may be formed of a material layer, continuous to the plurality of first insulating patterns222, or the second buried layer236may be formed of a material, continuous to the first buried layer234.

A storage node contact260may be on the channel layer230. The storage node contacts260may vertically overlap the channel layer230and may be in a matrix form spaced apart in the X-direction and the Y-direction. In an implementation, the storage node contact260may be formed of, e.g., doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof. The upper insulating layer262may surround sidewalls of the storage node contact260on the plurality of second insulating patterns232and the second buried layer236.

An etch-stop layer261may be on the upper insulating layer262, and a capacitor CP may be on the etch-stop layer261. The capacitor CP may include a lower electrode structure170, a dielectric layer280, and an upper electrode structure290. In an implementation, the capacitor CP may have a structure the same as or similar to the structures described with reference toFIGS.1to5.

By way of summation and review, research into various structures has been considered to increase an effective surface area of a lower electrode of a capacitor which may store information in a dynamic random-access memory (DRAM).

As described above, a conductive material for a lower electrode structure of a capacitor may be deposited twice (e.g., in two separate processes) to allow lengths of a lower pillar stack and an upper single cylinder stack to be constant for each capacitor. Accordingly, a semiconductor device having constant capacitance for each capacitor may be provided.

One or more embodiments may provide a highly integrated semiconductor device having improved electrical characteristics.