Resistance change memory

According to one embodiment, a resistance change memory includes a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2, and a first to a n-th drivers which drives the first to the (n+1)-th conductive lines. The odd-numbered conductive lines are extends in a first direction along a surface of the semiconductor substrate. The even-numbered conductive lines are extends in a second direction along the surface of the semiconductor substrate. Sizes of the first to (n+1)-th drivers become large gradually from the first driver to the (n+1)-th driver.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-001500, filed Jan. 6, 2010; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a peripheral circuit of a resistance change memory.

BACKGROUND

A resistance change memory is a semiconductor memory using a variable resistance element as a recording medium. The variable resistance element is an element made of a material that changes its resistance value in accordance with, e.g., a voltage, electric current, or heat, and includes a phase change element. For example, a ReRAM (Resistance Random Access Memory) using a metal oxide as a variable resistance element is expected as a next-generation semiconductor memory having a large capacity and capable of a high-speed operation.

The capacity can be increased by, e.g., giving a three-dimensional structure to a memory cell array, or storing multi-level data in the variable resistance element. A resistance change memory adopts a cross-point type memory cell array, and hence is suited to construction of a three-dimensional structure by stacking memory cell arrays (see, e.g., patent reference 1).

Presently, however, it is difficult to give a three-dimensional structure to a peripheral circuit even when a three-dimensional memory cell array is possible. Accordingly, the number of stackable memory cell arrays is limited by the size of the formation region of drivers for driving conductive lines in these memory cell arrays. That is, the number of drivers is proportional to the number of memory cell arrays, whereas it is impossible to unlimitedly enlarge the driver formation region on a semiconductor substrate.

Also, when stacking memory cell arrays, the time constant of a via plug for connecting a conductive line in a memory cell array and a driver for driving the conductive line changes from one memory cell array to another. On the other hand, the size (channel width) of an FET (Field Effect Transistor) as a driver is constant. Therefore, based on the time constant (maximum value) of a via plug for connecting a conductive line (uppermost conductive line) in an uppermost memory cell array and a driver for driving the conductive line, the size of all drivers is set to a size enough to drive the uppermost conductive line.

From the foregoing, it is conventionally necessary to form drivers having a large uniform size in a limited region. This makes it impossible to sufficiently obtain the benefit of a large capacity of a three-dimensional memory cell array.

DETAILED DESCRIPTION

In general, according to one embodiment, a resistance change memory comprising: a semiconductor substrate; a stacked layer structure stacked on the semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2; and a first to a n-th drivers which drives the first to the (n+1)-th conductive lines, wherein the odd-numbered conductive lines from the semiconductor substrate among the first to (n+1)-th conductive lines are extends in a first direction along a surface of the semiconductor substrate, the even-numbered conductive lines from the semiconductor substrate among the first to (n+1)-th conductive lines are extends in a second direction along the surface of the semiconductor substrate, and the first direction intersects with the second direction, wherein the g-th variable resistance element among the first to the n-th variable resistance elements is provided between the g-th conductive line and the (g+1)-th conductive line, where g is one of 1, 2, . . . and n, wherein sizes of the first to (n+1)-th drivers become large gradually from the first driver to the (n+1)-th driver.

1. Basic Concept

Embodiments propose a technique of minimizing the enlargement of a driver formation region with respect to the increase in number of memory cell arrays to be stacked, in a resistance change memory adopting cross-point type memory cell arrays.

This technique changes the driver size, i.e., the size (channel width) of an FET as a driver in accordance with the position (layer) of a corresponding memory cell array, thereby minimizing the enlargement of a driver formation region with respect to the increase in number of memory cell arrays to be stacked.

More specifically, the driver size is increased as the position of a conductive line in a corresponding memory cell array is spaced apart from a semiconductor substrate. This is so because when stacking memory cell arrays, the time constant of a via plug for connecting a conductive line in a memory cell array and a driver for driving the conductive line gradually increases from the lowermost memory cell array toward the uppermost memory cell array.

This can make the size of a driver formation region smaller than that of a conventional memory using a uniform driver size. Accordingly, it is possible to sufficiently obtain the benefit of a large capacity of a three-dimensional memory cell array.

2. Resistance Change Memory

First, a resistance change memory to which the embodiments are applied will be explained.

(1) Overall View

FIG. 1shows the main parts of a resistance change memory.

Resistance change memory (e.g., chip)1includes cross-point type memory cell array2. Cross-point type memory cell array2has a stacked structure including memory cell arrays.

First control circuit3is placed at one end in a first direction of cross-point type memory cell array2, and second control circuit4is placed at one end in a second direction perpendicular to the first direction.

First and second control circuits3and4select one of the stacked memory cell arrays based on, e.g., a memory cell array selection signal.

First control circuit3selects, e.g., a row of cross-point type memory cell array2based on a row address signal. Second control circuit4selects, e.g., a column of cross-point type memory cell array2based on a column address signal.

First and second control circuits3and4control data writing/erasing/reading for memory elements in cross-point type memory cell array2.

First and second control circuits3and4can perform data writing/erasing/reading for one of the stacked memory cell arrays, and can also perform data writing/erasing/reading for two or more or all of the stacked memory cell arrays at the same time.

In resistance change memory1, writing is called, e.g., set, and erasing is called, e.g., reset. A resistance value in the set state need only be different from that in the reset state: it is not important whether the former is higher or lower than the latter.

Also, when one of resistance values can selectively be written in a set operation, it is possible to implement a multi-level resistance change memory in which each memory element stores multi-level data.

Controller5supplies a control signal and data to resistance change memory1. The control signal is input to command interface circuit6, and the data is input to data input/output buffer7. Controller5can be placed in chip1, and can also be placed in a host (computer) different form chip1.

Based on the control signal, command interface circuit6determines whether the data from host5is command data. If the data is command data, command interface circuit6transfers the command data from data input/output buffer7to state machine8.

Based on the command data, state machine8manages the operation of resistance change memory1. For example, based on the command data from host5, state machine8manages set/reset operations and a read operation.

Controller5can also receive status information managed by state machine8, and determine the result of the operation of resistance change memory1.

In the set/reset operations and read operation, controller5supplies an address signal to resistance change memory1. The address signal includes, e.g., a memory cell array selection signal, row address signal, and column address signal.

The address signal is input to first and second control circuits3and4via address buffer9.

Based on an instruction from state machine8, pulse generator10outputs, at a predetermined timing, a voltage pulse or current pulse required for, e.g., the set/reset operations and read operation.

(2) Memory Cell Array

Cross-point type memory cell array2is formed on semiconductor substrate (e.g., silicon substrate)11. Note that circuit elements such as MOS transistors and an insulating film may be sandwiched between cross-point type memory cell array2and semiconductor substrate11.

As an example,FIG. 2shows cross-point type memory cell array2including four memory cell arrays M1, M2, M3, and M4stacked in a third direction (a direction perpendicular to the major surface of semiconductor substrate11). However, the number of memory cell arrays to be stacked need only be two or more.

Memory cell array M1includes cell units CU1arranged into an array in the first and second directions.

Similarly, memory cell array M2includes cell units CU2arranged into an array, memory cell array M3includes cell units CU3arranged into an array, and memory cell array M4includes cell units CU4arranged into an array.

Cell units CU1, CU2, CU3, and CU4each include a memory element (variable resistance element) and rectifying element connected in series.

On semiconductor substrate11, conductive lines L1(j−1), L1(j), and L1(j+1), conductive lines L2(i−1), L2(i), and L2(i+1), conductive lines L3(j−1), L3(j), and L3(j+1), conductive lines L4(i−1), L4(i), and L4(i+1), and conductive lines L5(j−1), L5(j), and L5(j+1) are arranged in order from semiconductor substrate11.

Conductive lines given odd numbers when counted from semiconductor substrate11, i.e., conductive lines L1(j−1), L1(j), and L1(j+1), conductive lines L3(j−1), L3(j), and L3(j+1), and conductive lines L5(j−1), L5(j), and L5(j+1) run in the second direction.

Conductive lines given even numbers when counted from semiconductor substrate11, i.e., conductive lines L2(i−1), L2(i), and L2(i+1), and conductive lines L4(i−1), L4(i), and L4(i+1) run in the first direction.

These conductive lines each function as a word line or bit line.

First memory cell array M1as the lowermost array is placed between first conductive lines L1(j−1), L1(j), and L1(j+1) and second conductive lines L2(i−1), L2(i), and L2(i+1). In set/reset operations and a read operation for memory cell array M1, conductive lines L1(j−1), L1(j), and L1(j+1) and conductive lines L2(i−1), L2(i), and L2(i+1) respectively function as word lines and bit lines or vice versa.

Second memory cell array M2is placed between second conductive lines L2(i−1), L2(i), and L2(i+1) and third conductive lines L3(j−1), L3(j), and L3(j+1). In set/reset operations and a read operation for memory cell array M2, conductive lines L2(i−1), L2(i), and L2(i+1) and third conductive lines L3(j−1), L3(j), and L3(j+1) respectively function as word lines and bit lines or vice versa.

Third memory cell array M3is placed between third conductive lines L3(j−1), L3(j), and L3(j+1) and fourth conductive lines L4(i−1), L4(i), and L4(i+1). In set/reset operations and a read operation for memory cell array M3, conductive lines L3(j−1), L3(j), and L3(j+1) and conductive lines L4(i−1), L4(i), and L4(i+1) respectively function as word lines and bit lines or vice versa.

Fourth memory cell array M4is placed between fourth conductive lines L4(i−1), L4(i), and L4(i+1) and fifth conductive lines L5(j−1), L5(j), and L5(j+1). In set/reset operations and a read operation for memory cell array M4, conductive lines L4(i−1), L4(i), and L4(i+1) and conductive lines L5(j−1), L5(j), and L5(j+1) respectively function as word lines and bit lines or vice versa.

(3) Cell Unit

FIG. 3shows cell units in two memory cell arrays.

For example,FIG. 3shows cell units CU1and CU2in two memory cell arrays M1and M2shown inFIG. 2. The configuration of the cell units in two memory cell arrays M3and M4shown inFIG. 2is the same as that of the cell units in two memory cell arrays M1and M2shown inFIG. 2.

Cell units CU1and CU2each include a memory element (variable resistance element) and rectifying element connected in series.

The connection relationship between the memory element and rectifying element has various patterns.

All cell units in one memory cell array, however, must have the same connection relationship between the memory element and rectifying element.

The operations of the above-described resistance change memory will be explained below with reference toFIG. 3.

Memory cell array M1is equivalent to memory cell array M1shown inFIG. 2, and memory cell array M2is equivalent to memory cell array M2shown inFIG. 2.

A. Set Operation

First, a write (set) operation performed for selected cell unit CU1-sel in memory cell array M1and selected cell unit CU2-sel in memory cell array M2will be explained.

The initial state of selected cell units CU1-sel and CU2-sel is an erased (reset) state. Also, the reset state is a high-resistance state (100 kΩ to 1 MΩ), and the set state is a low-resistance state (1 to 10 kΩ).

Selected conductive line L2(i) is connected to power supply potential Vdd on a high-potential side, and selected conductive lines L1(j) and L3(j) are connected to power supply potential Vss on a low-potential side.

Also, among the first conductive lines from the semiconductor substrate, unselected conductive lines L1(j−1) and L1(j+1) except for selected conductive line L1(j) are connected to power supply potential Vdd.

Among the second conductive lines from the semiconductor substrate, unselected conductive line L2(i+1) except for selected conductive line L2(i) is connected to power supply potential Vss.

Furthermore, among the unselected third conductive lines from the semiconductor substrate, unselected conductive lines L3(j−1) and L3(j+1) except for selected conductive line L3(j) are connected to power supply potential Vdd.

In this state, a forward bias is applied to the rectifying elements (diodes) in selected cell units CU1-sel and CU2-sel, a set current I-set from a constant current source flows through selected cell units CU1-sel and CU2-sel, and the resistance value of the memory elements in selected cell units CU1-sel and CU2-sel changes from the high-resistance state to the low-resistance state.

In the set operation, a voltage of 1 to 2 V is applied to the memory elements in selected cell units CU1-sel and CU2-sel, and the current density of the set current I-set to be supplied to these memory cells (the high-resistance state) is set within the range of 1×105to 1×107A/cm2.

On the other hand, among unselected cell units CU1-unsel in memory cell array M1, a reverse bias is applied to the rectifying elements (diodes) in cell units connected between unselected conductive line L2(i+1) and unselected conductive lines L1(j−1) and L1(j+1).

Likewise, among unselected cell units CU2-unsel in memory cell array M2, the reverse bias is applied to the rectifying elements (diodes) in cell units connected between unselected conductive line L2(i+1) and unselected conductive lines L3(j−1) and L3(j+1).

Also, among unselected cell units CU1-unsel in memory cell array M1, no bias is applied to the rectifying elements (diodes) in cell units connected between selected conductive line L2(i) and unselected conductive lines L1(j−1) and L1(j+1), and to the rectifying element (diode) in a cell unit connected between unselected conductive line L2(i+1) and selected conductive line L1(j).

Similarly, among unselected cell units CU2-unsel in memory cell array M2, no bias is applied to the rectifying elements (diodes) in cell units connected between selected conductive line L2(i) and unselected conductive lines L3(j−1) and L3(j+1), and to the rectifying element (diode) in a cell unit connected between unselected conductive line L2(i+1) and selected conductive line L3(j).

Accordingly, no set operation is performed for the memory elements in unselected cell units CU1-unsel and CU2-unsel.

B. Reset Operation

An erase (reset) operation performed for selected cell unit CU1-sel in memory cell array M1and selected cell unit CU2-sel in memory cell array M2will be explained.

Selected conductive line L2(i) is connected to power supply potential Vdd on the high-potential side, and selected conductive lines L1(j) and L3(j) are connected to power supply potential Vss on the low-potential side.

Also, among the first conductive lines from the semiconductor substrate, unselected conductive lines L1(j−1) and L1(j+1) except for selected conductive line L1(j) are connected to power supply potential Vdd.

Among the second conductive lines from the semiconductor substrate, unselected conductive line L2(i+1) except for selected conductive line L2(i) is connected to power supply potential Vss.

Furthermore, among the unselected third conductive lines from the semiconductor substrate, unselected conductive lines L3(j−1) and L3(j+1) except for selected conductive line L3(j) are connected to power supply potential Vdd.

In this state, the forward bias is applied to the rectifying elements (diodes) in selected cell units CU1-sel and CU2-sel, a reset current I-reset from the constant current source flows through selected cell units CU1-sel and CU2-sel, and the resistance value of the memory elements in selected cell units CU1-sel and CU2-sel changes from the low-resistance state to the high-resistance state.

In the reset operation, a voltage of 1 to 3 V is applied to the memory elements in selected cell units CU1-sel and CU2-sel, and the current density of the reset current I-reset to be supplied to these memory cells (the low-resistance state) is set within the range of 1×103to 1×106A/cm2.

On the other hand, among unselected cell units CU1-unsel in memory cell array M1, the reverse bias is applied to the rectifying elements (diodes) in cell units connected between unselected conductive line L2(i+1) and unselected conductive lines L1(j−1) and L1(j+1).

Likewise, among unselected cell units CU2-unsel in memory cell array M2, the reverse bias is applied to the rectifying elements (diodes) in cell units connected between unselected conductive line L2(i+1) and unselected conductive lines L3(j−1) and L3(j+1).

Also, among unselected cell units CU1-unsel in memory cell array M1, no bias is applied to the rectifying elements (diodes) in cell units connected between selected conductive line L2(i) and unselected conductive lines L1(j−1) and L1(j+1), and to the rectifying element (diode) in a cell unit connected between unselected conductive line L2(i+1) and selected conductive line L1(j).

Similarly, among unselected cell units CU2-unsel in memory cell array M2, no bias is applied to the rectifying elements (diodes) in cell units connected between selected conductive line L2(i) and unselected conductive lines L3(j−1) and L3(j+1), and to the rectifying element (diode) in a cell unit connected between unselected conductive line L2(i+1) and selected conductive line L3(j).

Accordingly, no reset operation is performed for the memory elements in unselected cell units CU1-unsel and CU2-unsel.

Note that set currents I-set and reset current I-reset are different. Note also that the values of voltages to be applied to the memory elements in selected cell units CU1-sel and CU2-sel in order to generate these electric currents depend on the material forming the memory elements.

C. Read Operation

A read operation performed for selected cell unit CU1-sel in memory cell array M1and selected cell unit CU2-sel in memory cell array M2will be explained below.

Selected conductive line L2(i) is connected to power supply potential Vdd on the high-potential side, and selected conductive lines L1(j) and L3(j) are connected to power supply potential Vss on the low-potential side.

Also, among the first conductive lines from the semiconductor substrate, unselected conductive lines L1(j−1) and L1(j+1) except for selected conductive line L1(j) are connected to power supply potential Vdd.

Among the second conductive lines from the semiconductor substrate, unselected conductive line L2(i+1) except for selected conductive line L2(i) is connected to power supply potential Vss.

Furthermore, among the unselected third conductive lines from the semiconductor substrate, unselected conductive lines L3(j−1) and L3(j+1) except for selected conductive line L3(j) are connected to power supply potential Vdd.

In this state, the forward bias is applied to the rectifying elements (diodes) in selected cell units CU1-sel and CU2-sel. Therefore, a read current I-read from the constant current source flows through the memory elements (the high- or low-resistance state) in selected cell units CU1-sel and CU2-sel.

Accordingly, data (the resistance value) of a memory element can be read by detecting the potential change of a sense node when read current I-read flows through the memory element.

Note that the value of read current I-read must be much smaller than those of set current I-set and reset current I-reset, so that the resistance value of the memory element does not change during the read operation.

In the read operation, as in the set/reset operations, among unselected cell units CU1-unsel in memory cell array M1, the reverse bias is applied to the rectifying elements (diodes) in cell units connected between unselected conductive line L2(i+1) and unselected conductive lines L1(j−1) and L1(j+1).

Likewise, among unselected cell units CU2-unsel in memory cell array M2, the reverse bias is applied to the rectifying elements (diodes) in cell units connected between unselected conductive line L2(i+1) and unselected conductive lines L3(j−1) and L3(j+1).

Also, among unselected cell units CU1-unsel in memory cell array M1, no bias is applied to the rectifying element (diode) in cell units connected between selected conductive line L2(i) and unselected conductive lines L1(j−1) and L1(j+1), and to the rectifying element (diode) in a cell unit connected between unselected conductive line L2(i+1) and selected conductive line L1(j).

Similarly, among unselected cell units CU2-unsel in memory cell array M2, no bias is applied to the rectifying elements (diodes) in cell units connected between selected conductive line L2(i) and unselected conductive lines L3(j−1) and L3(j+1), and to the rectifying element (diode) in a cell unit connected between unselected conductive line L2(i+1) and selected conductive line L3(j).

Accordingly, no read operation is performed for the memory elements in unselected cell units CU1-unsel and CU2-unsel.

Methods of changing the resistance value of a memory element include a method of reversibly changing the resistance value of a memory element between at least first and second values by changing the polarity of a voltage to be applied to the memory element, and a method of reversibly changing the resistance value of a memory element between at least first and second values by controlling the magnitude and application time of a voltage to be applied to the memory element without changing the polarity of the voltage.

The former is called a bipolar operation, and the latter is called a unipolar operation.

The embodiments are directed to a driver as a peripheral circuit of a memory cell array, and hence applicable to both the bipolar and unipolar operations.

3. Relationship Between Memory Cell Array and Peripheral Circuit (Driver)

FIG. 4shows the first example of a memory cell array and peripheral circuit.

On semiconductor substrate11, n (n is a natural number of 2 or more) memory cell arrays2are stacked. Note that in this example, n is an even number of 4 or more in order to simplify the explanation.

Odd-numbered conductive lines L1(j), . . . , L(n−1)(j), and L(n+1)(j) run in the second direction, and each have one end connected to a driver (FET) Dr1(j) in first control circuit3via hookup area14. Drivers (FETs) Dr1(j) are two-dimensionally formed in a limited region on semiconductor substrate11.

Even-numbered conductive lines L2(i), . . . , and Ln(i) run in the first direction, and each have one end connected to driver (FET) Dr2(i) in second control circuit4via hookup area15. Drivers (FETs) Dr2(i) are also two-dimensionally formed in a limited region on semiconductor substrate11.

State machine8manages the operations of first and second control circuits3and4based on command data.

FIG. 5shows the second example of a memory cell array and peripheral circuit.

Compared to the first example, the second example includes, as a feature, common driver (FET) Dr2(i) for even-numbered conductive lines L2(i), . . . , and Ln(i).

That is, even-numbered conductive lines L2(i), . . . , and Ln(i) run in the first direction, and each have one end connected to common driver (FET) Dr2(i) in second control circuit4. Drivers (FETs) Dr2(i) are two-dimensionally formed in a limited region on semiconductor substrate11.

The rest of the arrangement is the same as that of the first example, and a repetitive explanation will be omitted by using the same reference numerals as shown inFIG. 4.

(2) Device Structure

FIGS. 6,7, and8illustrate an example of the device structure.FIG. 6is a plan view,FIG. 7is a sectional view taken along line VII-VII inFIG. 6, andFIG. 8is a sectional view taken along line VIII-VIII inFIG. 6.

Dummy cell array13surrounds memory cell array2. Dummy cell array13has the same structure as that of memory cell array2, and is formed to planarize the upper surface of an insulating layer on memory cell array2.

Fifth conductive line L5from semiconductor substrate11runs in the second direction, and functions as an upper conductive line of memory cell array M4. One end of conductive line L5is connected to via plug ZIA5in hookup area14. Via plug ZIA5connects conductive lines22A and L5. Conductive line22A is connected to one terminal of driver Dr1via conductive line21A. The other terminal of driver Dr1is connected to conductive line23A via conductive lines21B and22B.

Third conductive line L3from semiconductor substrate11runs in the second direction, and functions as an upper conductive line of memory cell array M2and a lower conductive line of memory cell array M3. One end of conductive line L3is connected to via plug ZIA3. First conductive line L1from semiconductor substrate11runs in the second direction, and functions as a lower conductive line of memory cell array M1. One end of conductive line L1is connected to via plug ZIA1.

Fourth conductive line L4from semiconductor substrate11runs in the first direction, and functions as an upper conductive line of memory cell array M3and a lower conductive line of memory cell array M4. One end of conductive line L4is connected to via plug ZIA4in hookup area15. Via plug ZIA4connects conductive lines22C and L4. Conductive line22C is connected to one terminal of driver Dr2via conductive line21C. The other terminal of driver Dr2is connected to conductive line23B via conductive lines21D and22D.

Second conductive line L2from semiconductor substrate11runs in the first direction, and functions as an upper conductive line of memory cell array M1and a lower conductive line of memory cell array M2. One end of conductive line L2is connected to via plug ZIA2.

Conductive lines21A to21D and22A to22D are generally made of a metal material such as aluminum or copper, and desirably made of a refractory metal such as tungsten so as to withstand high-temperature processes.

Conductive lines23A and23B on memory cell array2can be made of a metal material such as aluminum or copper, and can also be made of a refractory metal such as tungsten.

(3) Structures of Memory Cell Array and Via Plug

FIGS. 9 and 10illustrate details of the structure of the memory cell array.FIG. 9is a sectional view of the memory cell array in the second direction, andFIG. 10is a sectional view of the memory cell array in the first direction.

InFIGS. 9 and 10, the same reference numerals as inFIGS. 6,7, and8denote the same elements.

The positions (reference points) of the bottom surfaces of all via plugs ZIA1, ZIA2, ZIA3, ZIA4, ZIA5, . . . are the same. Also, the lengths of via plugs ZIA1, ZIA2, ZIA3, ZIA4, ZIA5, . . . in the third direction gradually increase from via plug ZIA1connected to conductive line L1toward the via plug connected to the uppermost conductive line.

Accordingly, assuming that via plugs ZIA1, ZIA2, ZIA3, ZIA4, ZIA5, . . . have the same structure, time constants τ (=resistance values R×capacitance values C) of these via plugs gradually increase from via plug ZIA1toward the via plug connected to the uppermost conductive line.

As shown inFIG. 11, therefore, the sizes of the first to (n+1)-th drivers for driving conductive lines L1, L2, . . . , and L(n+1) gradually increase from the first driver toward the (n+1)-th driver in accordance with the increase in time constants τ of via plugs ZIA1, ZIA2, . . . , and ZIA(n+1).

Also, in a cross-point type memory cell array, the direction in which odd-numbered conductive lines L1, L3, L5, . . . run differs from the direction in which even-numbered conductive lines L2, L4, . . . run. That is, the drivers for driving odd-numbered conductive lines L1, L3, L5, . . . are collectively arranged at, e.g., one end of memory cell array2in the second direction, and the drivers for driving even-numbered conductive lines L2, L4, . . . are collectively arranged at, e.g., one end of memory cell array2in the first direction.

As shown inFIG. 12, therefore, the sizes of only the drivers for driving odd-numbered conductive lines L1, L3, L5, . . . may gradually be increased in accordance with the increase in time constants τ of via plugs ZIA1, ZIA3, ZIA5, . . . .

Likewise, as shown inFIG. 13, the sizes of the drivers for driving even-numbered conductive lines L2, L4, . . . may gradually be increased in accordance with the increase in time constants τ of via plugs ZIA2, ZIA4, . . . .

By thus changing the driver sizes, it is possible to minimize the enlargement of the driver formation region with respect to the increase in number of memory cell arrays to be stacked. This makes it possible to sufficiently obtain the benefit of a large capacity of a three-dimensional memory cell array.

Conductive lines L1, L2, L3, L4, L5, . . . in memory cell array2are stacked at a constant pitch in the third direction. Therefore, the lengths of via plugs ZIA1, ZIA2, ZIA3, ZIA4, ZIA5, . . . in the third direction increase at a constant rate from via plug ZIA1connected to conductive line L1toward the via plug connected to the uppermost conductive line.

Accordingly, the sizes of the drivers for driving conductive lines L1, L2, L3, L4, L5, . . . are desirably increased at a constant rate from the driver corresponding to via plug ZIA1toward the driver corresponding to the via plug connected to the uppermost conductive line.

Accordingly, the sizes of the first to (n+1)-th drivers for driving conductive lines L1, L2, . . . , and L(n+1) are respectively set to, e.g., 1, 2, 3, 4, . . . , and (n+1) from the first driver toward the (n+1)-th driver in accordance with the increase in time constants τ of via plugs ZIA1, ZIA2, ZIA3, ZIA4, . . . , and ZIA(n+1). Note that the size of the first driver connected to via plug ZIA1is defined as 1 (a reference value).

Also, as shown inFIG. 15, the sizes of only the drivers for driving odd-numbered conductive lines L1, L3, L5, . . . may be gradually increased like, e.g., 1, 3, 5, . . . in accordance with the increase in time constants τ of via plugs ZIA1, ZIA3, ZIA5, . . . . Note that the size of the first driver connected to via plug ZIA1is defined as 1 (a reference value).

Similarly, as shown inFIG. 16, the sizes of only the drivers for driving even-numbered conductive lines L2, L4, . . . may be gradually increased like, e.g., 2, 4, . . . in accordance with the increase in time constants τ of via plugs ZIA2, ZIA4, . . . . Note that the size of the first driver connected to via plug ZIA1is defined as 1 (a reference value).

Embodiments using different driver sizes will be explained below.

First, as a comparative example,FIG. 17shows an example in which the sizes of all drivers are the same. First control circuit3is placed at one end of memory cell array2in the second direction, and second control circuit4is placed at one end of memory cell array2in the first direction.

(1) First Embodiment

InFIG. 18, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of first to (n+1)-th drivers for driving the first to (n+1)-th conductive lines are as follows.

In this case, k is the number of odd-numbered conductive lines arranged in the first direction, and m is the number of even-numbered conductive lines arranged in the second direction. Each of k and m is a natural number of 2 or more, and k and m can be the same number or different numbers.

(2) Second Embodiment

InFIG. 19, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of drivers for driving odd-numbered conductive lines are as follows from first drivers toward drivers for driving uppermost conductive lines among the odd-numbered conductive lines.

In this case, k is the number of odd-numbered conductive lines arranged in the first direction, and is a natural number of 2 or more.

InFIG. 20, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of drivers for driving even-numbered conductive lines are as follows from second drivers toward drivers for driving uppermost conductive lines among the even-numbered conductive lines.

In this case, m is the number of even-numbered conductive lines arranged in the second direction, and is a natural number of 2 or more.

InFIG. 21, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of first to (n+1)-th drivers for driving the first to (n+1)-th conductive lines are as follows.

In this embodiment, the driver size increases at a constant rate whenever the number of conductive line layers increases by one. Therefore, FETs having a uniform size (channel width) are prepared, and the size of a driver is changed by changing the number of FETs forming the driver. That is, the number of FETs forming a driver is increased by one whenever the number of conductive line layers increases by one.

The size (channel width) of one FET is defined as 1 (a reference value).

In this case, k is the number of odd-numbered conductive lines arranged in the first direction, and m is the number of even-numbered conductive lines arranged in the second direction. Each of k and m is a natural number of 2 or more, and k and m can be the same number or different numbers.

InFIG. 22, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of first to (n+1)-th drivers for driving the first to (n+1)-th conductive lines are as follows.

In this embodiment, on the side of first control circuit3, the driver size increases at a constant rate whenever the number of conductive line layers increases by two. That is, the number of FETs forming a driver is increased by one whenever the number of conductive line layers increases by two.

Likewise, on the side of second control circuit4, the driver size increases at a constant rate whenever the number of conductive line layers increases by two. That is, the number of FETs forming a driver is increased by one whenever the number of conductive line layers increases by two.

In this embodiment, the size (reference value=1) of one FET on the side of first control circuit3and the size (reference value=1) of one FET on the side of second control circuit4can be the same or different.

In this case, k is the number of odd-numbered conductive lines arranged in the first direction, and m is the number of even-numbered conductive lines arranged in the second direction. Each of k and m is a natural number of 2 or more, and k and m can be the same number or different numbers.

InFIG. 23, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of drivers for driving odd-numbered conductive lines are as follows from first drivers toward drivers for driving uppermost conductive lines among the odd-numbered conductive lines.

In this embodiment, on the side of first control circuit3, the driver size increases at a constant rate whenever the number of conductive line layers increases by two. That is, the number of FETs forming a driver is increased by one whenever the number of conductive line layers increases by two.

On the side of first control circuit3, the size (channel width) of one FET is defined as 1 (a reference value), and k is the number of odd-numbered conductive lines arranged in the first direction, and is a natural number of 2 or more.

InFIG. 24, the same reference numerals as inFIG. 17denote the same elements.

According to the feature of this embodiment, when a memory cell array has a stacked layer structure including first conductive lines, first variable resistance elements, second conductive lines, second variable resistance elements, . . . , n-th conductive lines, n-th variable resistance elements, and (n+1)-th conductive lines (n is a natural number of 2 or more), the sizes of drivers for driving even-numbered conductive lines are as follows from second drivers toward drivers for driving uppermost conductive lines among the even-numbered conductive lines.

In this embodiment, on the side of second control circuit4, the driver size increases at a constant rate whenever the number of conductive line layers increases by two. That is, the number of FETs forming a driver is increased by one whenever the number of conductive line layers increases by two.

On the side of second control circuit4, the size (channel width) of one FET is defined as 1 (a reference value), and m is the number of even-numbered conductive lines arranged in the first direction, and is a natural number of 2 or more.

In the embodiments, it is possible to sufficiently obtain the benefit of a large capacity of a three-dimensional memory cell array by minimizing the enlargement of the driver formation region with respect to the increase in number of memory cell arrays to be stacked.

The embodiments have great industrial merits for, e.g., a file memory capable of high-speed random writing, a portable terminal capable of high-speed downloading, a portable player capable of high-speed downloading, a semiconductor memory for a broadcasting device, a drive recorder, a home video recorder, a large-capacity buffer memory for communication, and a semiconductor memory for a surveillance camera.