Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof

The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, which accounts for both rounding and cancellation errors, has two parts, the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the real value represented are determined from the truncated floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). The true, real value is absolutely contained by the first and second bounds. The allowed loss (optionally programmable) of significant bits provides a fail-safe, real-time notification of loss of significant bits.

FIELD OF INVENTION

This invention relates generally to logic circuits that perform certain floating point arithmetic operations in a floating point processing device and, more particularly, methods or arrangements for processing data by operating upon the order or content of the data to calculate and retain a bound on error introduced through alignment and normalization.

BACKGROUND OF THE INVENTION

In the design of floating point arithmetic systems for use in a floating point processing device, it is desirable that results are consistent to achieve conformity in the calculations and solutions to problems even though the problems are solved using different computer systems.

An American national standard has been developed in order to provide a uniform system of rules for governing the implementation of floating point arithmetic systems. This standard is identified as IEEE Standard No. 754-2008 and international standard ISO/IEC/IEEE 60599:2011, which are both incorporated by reference herein. The standard specifies basic and extended floating point number formats, arithmetic operations, conversions between integer and floating point formats, conversions between different floating point formats, conversions between basic format floating point numbers and decimal strings, and the handling of certain floating point exceptions.

The typical floating point arithmetic operation may be accomplished using formats of various (usually standard) widths (for example, 32-bit, 64-bit, etc.). Each of these formats utilizes a sign, exponent and fraction field (or significand), where the respective fields occupy predefined portions of the floating point number. For example, in the case of a 32-bit single precision number the sign field is a single bit occupying the most significant bit position; the exponent field is an 8-bit quantity occupying the next-most significant bit positions; the fraction field occupies the least significant 23-bit positions. Similarly, in the case of a 64-bit double precision number the sign field is a single bit, the exponent field is 11 bits, and the fraction field is 52 bits. Additional formats provide the same information, but with varied field widths, with larger field widths providing the potential for greater accuracy and value range.

After each floating point result is developed, it must be normalized and then rounded. When the result is normalized, the number of leading zeros in the fraction field is counted. This number is then subtracted from the exponent, and the fraction is shifted left until a “1” resides in the most significant bit position of the fraction field. Certain floating point answers cannot be normalized because the exponent is already at its lowest possible value and the most significant bit of the fraction field is not a “1.” This is a “subnormal number” with fewer significant digits than a normalized number.

In designing the hardware and logic for performing floating point arithmetic operations in conformance with this standard, it is necessary and desirable to incorporate certain additional indicator bits into the floating point hardware operations. These indicator bits are injected into the fraction field of the floating point number, and are used by the arithmetic control logic to indicate when certain conditions exist in the floating point operation. In non-subnormal (normalized) numbers, for example, an “implicit” bit (generally referred to as the “hidden bit”) is created by the arithmetic control logic when the exponent of the floating point number has a nonzero value. This “hidden bit” is not represented in the storage format, but is assumed. It is inserted at the time a floating point number is loaded into the arithmetic registers and occupies the most significant bit position of the fraction field of the number. During addition, a single “guard” bit is set by the floating point control logic during certain arithmetic operations, as an indicator of the loss of significant bits of the floating point number being processed. The guard bit is set when a right shift, required for normalization, shifts a bit from the right side of the fraction field capacity. The guard bit occupies a portion of the fraction field. Finally, a “sticky” bit is set in certain floating point arithmetic operations as an indicator that the floating point number has lost some significant bits.

These extra bits in the fraction field are used exclusively for rounding operations, after the result has been normalized. The guard bit is treated as if it is a part of the fraction and is shifted with the rest of the fraction during normalization and exponent alignment and is utilized by the arithmetic. The sticky bit is not shifted with the fraction, but is utilized by the arithmetic. It acts as a “catcher” for bits shifted off the right of the fraction; when a 1 is shifted off the right side of the fraction, the sticky bit will remain a 1 until normalization and rounding are finished.

There are typically four modes of rounding, as follows: (1.) round to nearest; (2.) round to positive infinity; (3.) round to negative infinity; and (4.) round to zero. Each of these may introduce error into the calculation.

Though this standard is widely used and is useful for many operations, this standard defines “precision” as the maximum number of digits available for the significand of the real number representation and does not define precision as the number of correct digits in a real number representation. Neither does this standard provide for the calculation and storage of error information and therefore permits propagation of error including the potential loss of all significant bits. These problems in the current standard can lead to substantial accumulated rounding error and catastrophic cancellation error. Cancellation occurs when closely similar values are subtracted, and it injects significant error without a corresponding indication of this error in the result.

Various authors have contributed to the standard or noted these significant problems, but the problem persists.

U.S. Pat. No. 3,037,701 to Sierra issued in 1962 establishes the basis for hardware to perform fixed word length floating point arithmetic including normalization, rounding, and zero conversion. The Sierra patent describes the potential for introducing error in floating point operations including total loss of useful information. No method is described for calculating or retaining error information of any type.

In 2010, in his bookHandbook of Floating-Point Arithmetic, Muller et al. describe the state-of-the-art of the application of floating point including the ISO/IEC/IEEE 60599:2011 and describe error problems. They state, “Sometimes, even with a correctly implemented floating-point arithmetic, the result of a computation is far from what could be expected.”

In 1991, David Goldberg, in “What Every Computer Scientist Should Know About Floating-Point Arithmetic,” provides a detailed description and mathematical analysis of floating point error. This paper describes rounding error (p. 6), relative error and error units in the last place (Ulps) (p. 8), the use of guard digits (p. 9), and cancellation error types, both catastrophic and benign (p. 10). Recommended error mitigation is limited to extending precision (again defined as digits available for real number representation) requiring additional storage space for computational results (p. 17) and numerical error analysis of a given problem to determine the method of computation to minimize and limit the error introduced by the computation.

Thus, many authors have acknowledged the existence of these types of errors in the current standard for floating point operations. In response, numerous attempts to address these significant problems have been made.

In 2012 in the article “Floating-Point Numbers with Error Estimates,” Glauco Masotti describes adding a data structure to standard floating point format to contain statistical estimates of the accumulated floating point error. This technique increases required storage space, adds computation time, and does not provide bounds for the error.

In 2008 in “The Pitfalls of Verifying Floating-Point Computations,” David Monniaux presents the limitations on static program analysis to determine the expected error generated by code to perform a sequence of floating point operations. However, static error analysis is prone to error and relies on and assumes a lengthy and expensive algorithm error analysis to ensure that the algorithm will provide sufficiently accurate results.

In summary, the current state-of-the-art does not retain error information within the associated floating point data structure. At present, any retention of bounds on floating point error requires significantly more memory space and computation time (or correspondingly more hardware) to perform error interval computations.

Further, in the current standard, when two values are compared by subtraction in which cancellation occurs, program flow decisions based on this erroneous comparison can result in an incorrect decision. No validity of the resulting comparison is provided by the standard conventions.

Importantly, the standard provides no indication when the result of a computation no longer provides a sufficient number of significant digits.

Additionally, conversion from external to internal format or conversion between floating point formats may inject an error in the initial representation of a real number without recording that error.

Further, floating point values are converted to external representation without indication of loss of significant bits even if no significant bits remain in the output data.

Notably, current technology does not permit allowing programmers to specify the number of required retained significant digits.

Thus, the various methods provided by the current art for floating point error mitigation have unresolved problems. Accordingly, there is a need for an apparatus and method for calculating and retaining a bound on error during floating point operations.

SUMMARY OF THE INVENTION

The present invention is directed to a floating point processing device and associated methods for calculating and retaining a bound on error during floating point operations by the insertion of an additional bounding field into the ANSI/IEEE 754-2008 standard floating-point arithmetic format. This bound B Field has two major parts, the lost bits field (D Field) and the accumulated rounding error field (N Field). The N Field is subsequently divided into the rounding bits field (R Field) and the rounding error count field (C Field), representing the sum of the carries from the sum of the R Fields. The lost bits D Field is the number of bits in the floating point representation that are no longer significant. The bounds on the real value represented are determined from the truncated (round to zero) floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). This lost bits D Field is compared to the (optionally programmable) unacceptable loss of significant bits to provide a fail-safe, real-time notification of the loss of significant bits.

The C Field of the floating point format of the present invention, which is the sum of the carries from the sum of the R Fields. (The term “field” refers to either a portion of a data structure or the value of that portion of the data structure, unless otherwise contextually defined.) When the extension count exceeds the current lost bits, one is added to the lost bits and the C Field is set to one. The R Field is the sum of the rounded most significant bits of the rounding error, lost during truncation.

The apparatus and method of the current invention can be used in conjunction with the apparatus and method implementing the current floating point standard. Conversion between the inventive format and the current format can be accomplished when needed; therefore, existing software that is dependent upon the current floating point standard need not be discarded. The new bounding field is added to the conventional floating point standard to provide accumulated information for the bound of the error that delimits the real number represented.

Current standards for floating point have no means of measuring and/or recording floating point rounding and cancelation error. The present invention provides an apparatus and method that classifies (as acceptable or as not acceptable) the accumulated loss of significant bits resulting from a floating point operation. This is done by comparing the loss of significant bits of the current operation against the unacceptable limit of the loss of significant bits. The unacceptable limits for different widths of floating point numbers can be provided in two ways, hardware or programmable. The hardware provides a default value. For example, in single precision (32-bit), the default value could require 3 significant decimal digits, which necessitates that the significand retains 10 significant bits. In a 64-bit double precision example, the default value could require 6 significant decimal digits, which necessitates that the significand retains 20 significant bits. The second way to provide the unacceptable limit is by a special floating point instruction that sets the limit on the error bound for the specified precision. The current invention provides a means of measuring, accumulating, recording, and reporting these errors, as well as optionally allowing the programmer to designate an unacceptable amount of error.

This is an advantage over the current technology that does not permit any control on the allowable error. The current invention not only permits the detection of loss of significant bits, but optionally allows the number of required retained significant digits to be specified.

When the loss of significant bits is greater than or equal to the unacceptable limit, an inventive signaling NaN that signals insufficient significant bits, termed “sNaN(isb),” is generated indicating that the result no longer has the required number of significant bits. This is in contrast to the current technology, which does not provide an indication when the result of a computation no longer provides a sufficient number of significant bits.

In contrast to the conventional floating point standard, which does not retain error information within the associated floating point data structure, the present invention provides error information in the lost bits D Field within the floating point data structure. Two bounds are provided. The first bound is the real number represented by the exponent and the truncated significand, and the second bound is determined by adding to the first bound a maximum error value represented by the lost bits D Field.

Using current technology error can be reduced by increasing computation time and/or memory space. The present invention provides this error information within the inventive data structure with little impact on space and performance.

In the standard floating point implementation cancellation injects significant error without a corresponding indication in the result. In contrast, the present invention accounts for cancellation error in the lost bits D Field.

The instant invention provides a method of recording the error injected by the conversion of an external representation to the inventive internal representation (or of recording the error in conversion between internal representations).

Currently floating point values are converted to external representation without indication of loss of significant digits even when no significant bits exist. In contrast, the current invention provides the inventive signaling Not-a-Number, sNaN(isb) when insufficient significant bits remain.

In the current art, static error analysis requires significant mathematical analysis and cannot determine actual error in real time. This work must be done by highly skilled mathematician programmers. Therefore, error analysis is only used for critical projects because of the greatly increased cost and time required. In contrast, the present invention provides error computation in real time with, at most, a small increase in computation time and a small decrease in the maximum number of bits available for the significand.

The dynamic error analysis by means of error injection, used in the current technology, has similar problems requiring multiple execution of algorithms that require floating point. Such techniques would be of little use when using adaptive algorithms or when error information is required in real time. The present invention eliminates the need for multiple execution and provides error information in real time.

Adding additional storage to retain statistical information on error, which is a commonly proposed solution, significantly increases computation time and required storage. The present invention makes a slight decrease in the maximum number of bits available for the significand for real number representation in order to accommodate space for error information. The storage space required by the present invention is the same as standard floating point.

Though interval arithmetic provides a means of computing bounds for floating point computations, it requires greatly increased computation time and at least twice as much storage. In contrast, the present apparatus for calculating and retaining a bound computes both the first and second bounds on the real number represented and does this within the execution of a single instruction. Additional memory is not required. The computed bounds are fail safe.

An object of the present invention is to bound floating point error when performing certain floating point arithmetic operations in a floating point processing device.

These and other objects, features, and advantages of the present invention will become more readily apparent from the attached drawings and from the detailed description of the preferred embodiments which follow.

DETAILED DESCRIPTION OF THE INVENTION

Shown throughout the figures, the present invention is directed toward a bounded floating point system900including a bounded floating point processing unit (BFPU)950and method for calculating and retaining a bound on error during floating point operations, an example of which is shown generally as reference number200(FIGS. 2A-2B). In contrast to the standard floating point implementation that introduces error without notification or warning, the present bounded floating point format100provides a new error bound B Field52(FIG. 1) that identifies and records a bound on the error and enables notification of loss of significant bits via replacement of the result with an inventive sNaN(isb)262, when insufficient significant bits remain.

Using the current floating point standard, error can be introduced during alignment or normalization. In the inventive apparatus and method, normalization during subtract and other floating point operations can still result in the loss of significant bits, such as through cancelation. When this loss is significant in the current computation, this loss is recorded in the bound on the number of lost significant bits, which is termed the “result bound lost bits D”54F (FIG. 8) stored in the lost bits field, the D Field54.

When the outcome of a calculation results in insufficient significant bits, the bounded floating point value, the “calculated result”260, is replaced with a special representation for an invalid bounded floating point value that is not a number (NaN), but is an inventive signaling NaN that signals insufficient significant bits, termed the “sNaN(isb)”262(FIG. 2B), which indicates excessive loss of significant bits. Memory in the hardware is provided for comparison to the recorded accumulated error to determine whether sufficient significant bits remain or whether sNaN(isb)262should be generated. As with other NaNs, the sNaN(isb)262is propagated into future computations. The sNaN(isb)262can be signaling to generate a hardware floating point exception.

The circuitry for determining loss of significant bits may contain an optionally programmable bound limit memory802to allow user determination of the number of significant bits required by the user resulting from a floating point calculation. The bound limit memory802contains a default value for each precision floating point width and can be programmable by the user.

When the inventive bounded floating point format100is implemented, it can be used concurrently with implementations of the current floating point standard. Therefore, existing software that is dependent upon the current floating point standard need not be discarded.

The new bound B Field52is inserted in the conventional floating point standard to provide accumulated information on the bound of error that delimits the real number represented.

FIG. 1provides a virtual bitwise layout of the bounded floating point format100for word width of width k101showing the inventive bound B Field52(having a width b103), which is composed of two parts, the lost bits D Field54(having a width d105) and the N Field55(having a width n106), as well as the standard floating point format fields. The N Field55is further composed of two fields, the C Field56(having a width c107) and the R Field57(having a width r108). The standard fields include the sign bit field, which is the S Field50, the exponent E Field51(having a width e102), and the significand field, which is the T Field53(having a width t104).

This bound B Field52is a new field inserted within the floating point standard format to provide accumulated information on the bound of the represented real number. The bound B Field52accounts for both rounding and cancellation errors. This bound B Field52keeps track of the loss of significant bits resulting from all previous operations and the current operation. Recording this loss of significant bits then allows a determination to be made as to whether insufficient significant bits have been retained. When a sufficient loss of significant bits occurs, this is signaled to the main processing unit910by the sNaN selection control811(FIG. 8). When insufficient significant bits have been retained, the BFPU selects the sNaN(isb)262for the bounded floating point result280(selected from among a calculated result260value, a representation of sNaN(isb)262, and a bounded floating point representation of BFP zero261).

The lost bits D Field54(FIG. 1) contains the representation of the number of bits in the floating point representation that are no longer significant.

The N Field55is the accumulation of the rounding errors that occur from alignment and normalization.

The C Field56contains the representation of the sum of the carries out of the R Field57R (FIG. 5), which like the R Field57has a width r108, where the “R” designates the result after normalization. The logical OR of the bits of the extended rounding error X Field60R, of width x502, which is used instead of the conventional carry and guard bits. When the value of the C Field56exceeds the value of the lost bits D Field54, one is added to the value of the lost bits D Field54and the C Field56is set to one (FIG. 6).

The R Field57contains the sum of the current R57and the resulting rounding bits R57R (FIG. 5), which is the most significant r108bits lost due to truncation of the normalized result720. The apparatus and method for calculating and retaining a bound on error during floating point operations is shown in the exemplary bounded floating point addition/subtraction diagram200shown onFIG. 2Aand continuing ontoFIG. 2B. This diagram provides the logic and control for an exemplary floating point addition or subtraction operation showing the inventive bounding of the floating point error (normally caused by alignment and normalization) of the present invention.

The bounded floating point system includes a processing device with a plurality of registers990(FIG. 9), a main processing unit910, and a bounded floating point unit (BFPU)950that is communicably coupled to the main processing unit910. The main processing unit910executes internal instructions and outputs at least two types of BFPU instructions930,830to the BFPU950. The first type is a bounded floating point operation instruction930, which instructs the BFPU950on the type of arithmetic operation to be performed and provides the two input operands201,202. The second type is a bound limit instruction830, which is an instruction to set a default bound limit833or to set a programmed bound limit831.

The arithmetic operation is performed on two input operands201,202, which in the example ofFIGS. 2A, 2B, are stored in the first operand register210and the second operand register220, respectively. Then the BFPU950generates a result value, the bounded floating point result280, from executing the FPU instructions on the bounded floating point number inputs201,202. This bounded floating point result280includes an error bound value obtained from the accumulated cancellation error and the accumulated rounding error. When there are insufficient significant bits in the bounded floating point result280, the BFPU950generates an sNaN selection control811signaling insufficient significant bits. The BFPU950also writes the bounded floating point result280to a main processing unit910solution register of the plurality of registers990, thereby storing the results from the operation of the bounded floating point unit950.

The first operand register operand210ofFIG. 2Ais the register (where a register may be a hardware register, a location in a register file, or a memory location) that contains the first operand201in the bounded floating point format100.

The first operand201ofFIG. 2Ais the bounded floating point first addend for an addition operation or is the minuend for a subtraction operation. The first operand201includes a first operand S value50A, a first operand exponent E value51A, a first operand bound B value52A, and the first operand significand T value53A.

The first operand register operand220ofFIG. 2Ais the register (where a register may be a hardware register, a location in a register file, or a memory location) that contains the first operand202in the bounded floating point format100.

The second operand202is the bounded floating point second addend for an addition operation or is the subtrahend for a subtraction operation. The second operand202includes a second operand sign bit S50B, a second operand exponent E51B, a second operand bound B52B, and the second operand significand T53B.

Many steps within this bounded floating point addition/subtraction diagram200ofFIGS. 2A-2Bare conventional steps (which are generally denoted by dashed lines), but some results from these conventional steps are utilized in the inventive apparatus and method.

Turning to the exponent logic steps300ofFIGS. 2A, 3, the first operand exponent E51A (coming from the first operand201ofFIG. 2A) and the second operand exponent E51B (coming from the second operand202ofFIG. 2A) are compared in the exponent comparator301to determine the largest exponent control302. The largest exponent control302is the control signal that controls the first and second significand swap multiplexers230,231(FIG. 2A), controls the largest and smallest exponent selection multiplexers310,311, and controls the first and second bound swap multiplexers401,402(FIG. 4).

Additionally, as seen onFIG. 3, the largest exponent control302is the control signal identifying the larger of the first operand exponent E51A or the second operand exponent E51B and controls the largest exponent selection multiplexer310. The largest exponent selection multiplexer310selects the largest exponent E51D from the first operand exponent E51A and the second operand exponent E51B controlled by the largest exponent control302. The smallest exponent selection multiplexer311is also controlled by the largest exponent control302and selects the smallest exponent E51E from the first operand exponent E51A and the second operand exponent E51B. The exponent difference321is calculated by the exponent subtractor320that subtracts the smallest exponent E51E from the largest exponent E51D. The exponent difference321controls the alignment shifter240(FIG. 2A) and is used by the lost bits subtractor410(FIG. 4).

Additionally, as seen onFIG. 2A, the largest exponent control302provides control for the first and second significand swap multiplexers230,231(FIG. 2A). The first significand swap multiplexer230selects from either the first operand significand T53A or the second operand significand T53B and produces the significand T of the operand with the smallest exponent E53D. Similarly, the second significand swap multiplexer231selects the significand T of the operand with the largest exponent E53E from either the first or second operand significands T53A,53B.

The alignment shifter240(FIG. 2A) shifts the significand T of the operand with the smallest exponent E53D to the right by the number of bits determined by the exponent difference321(coming from the exponent logic300,FIG. 3) to produce the aligned significand T of the operand with the smallest exponent E241. Only one bits (not zero bits) shifted out of the alignment shifter240causing alignment shift loss242are inserted into the least significant bit of the aligned significand T of the operand with the smallest exponent E241ensuring that a significand excess741will be detected.

The significand adder250(FIG. 2A) calculates the sum or difference251of the aligned significand T of the operand with the smallest exponent E241and the significand T of the operand with the largest exponent E53E. The virtual width v501(FIG. 5) of the significand adder is the width of the resulting sum or difference taking into account possible need for multiple additions necessary to accommodate extended bounded floating point formats.

FIG. 5provides a detail of the format500of the post normalization result, which is the format of the bounded floating point significand adder result720after normalization. This format includes: (1.) the standard hidden bit H Field510, the left justified hidden bit H Field510after normalization; (2.) the resulting normalized significand T53R (t104bits in width), the resulting significand after normalization; (3.) the resulting rounding bits R Field57R of width r108holding the most significant bits of the resulting significand that are lost due to truncation; and (4.) the extended rounding error X Field60R of width x502containing the bits of the result lost due to truncation, which is to the right of the R Field57R in the format.

The calculated sum or difference251(FIG. 2A) is utilized in the normalization logic700ofFIG. 2B, which is expanded onFIG. 7. Turning to the details of the normalization logic700ofFIG. 7, the sum or difference251is used by the right shifter703or left shifter712to arrive at the normalized result720. The first control for this determination is the right shift control702controlling the right shifter703, which is determined by the carry detection701. The right shifter703, when indicated by the right shift control702, shifts the sum or difference251right one bit producing the right shift result704. The right shift loss705is a one bit shifted out of the right shift result704. When this occurs, a one bit is inserted into the least significant bit of the right shift result704ensuring that a significand excess741will be detected. This right shift result704is utilized in the left shifter712. When the right shift control702is not asserted, the right shift result704is equal to the sum or difference251.

Also inFIG. 7, the sum or difference251is used in the most significant zeros counter710, which is another control. The zeros counter710counts the most significant zeros of the sum or difference251, which produces the number of leading zeros711necessary to normalize the result. The number of leading zeros711controls the left shifter712by shifting the right shift result704left producing the normalized result720comprised of the truncated resulting significand T53C, the normalized rounding R57A, and the normalized extension X60A. If the most significant zeros counter710determines that there are no leading zeros, the normalized result720is equal to the right shift result704. If there is no right or left shift, the value is merely passed through (which occurs if there is no carry and if there are no significant zeros). The number of leading zeros711is also used in the exponent normalization adder730and is further used in the inventive main bound logic600ofFIG. 2B, which is expanded onFIG. 6.

Still onFIG. 7, the largest exponent E51D (fromFIG. 3) is adjusted for normalization by the exponent normalization adder730using the right shift control702and the number of leading zeros711.

The normalized extension X60A is derived from the X Field60R of the post normalization result format500(FIG. 5) of the normalized result720.

The excess significand detector740produces the logical OR of all bits of the normalized extension X60A producing the significand excess741. The significand excess741is utilized by the count adder640(FIG. 6B) of the inventive main bound logic600(FIGS. 2B, 6A-6B).

The exponent normalization adder730(FIG. 7) adds the right shift control702, or subtracts the number of leading zeros711, to or from the largest exponent E51D to produce the result exponent E51C, which is the exponent in the inventive calculated result260ofFIG. 2B.

The sign logic290ofFIG. 2Boperates in the conventional manner, determining the result sign bit S50C from the operand sign bit S50A, the second operand sign bit S50B, and the right shift control702.

Turning to the exemplary diagram200of the logic and control of the inventive apparatus and method ofFIG. 2B, the calculated result260is created from the concatenation of the result sign bit S50C, the result exponent E51C ofFIG. 7, the result bound B52C ofFIG. 6A, and the truncated resulting significand T53C ofFIG. 7.

Turning to the exemplary diagram200of the logic and control of the inventive apparatus and method ofFIG. 2A, the first operand bound B52A ofFIG. 2A, the second operand bound B52B ofFIG. 2A, the largest exponent control302ofFIG. 3, and the exponent difference321ofFIG. 3are used in the dominant bound logic400ofFIG. 2A, which is expanded inFIG. 4.

In an arithmetic operation, the operand with the least number of significant digits determines (“dominates”) the number of significant digits of the result. When, after being aligned, the number of significant bits in one operand is less than the significant bits in the other operand, the significant bits of the operand with fewer significant bits governs or dominates the base significant bits of the result. The dominant bound logic400selects the bound from the initial operands, first operand bound B52A and the second operand bound B52B, to determine the bound with the most influence on the bound of the result prior to accounting for cancellation and rounding.

As seen in the dominant bound logic400ofFIG. 4, the bounds of both operands (first and second operand bounds B52A,52B ofFIG. 2A) are compared—with one bound adjusted before comparison. The dominant bound logic400determines the dominant bound B52H. The dominant bound B52H is the larger of (1.) the clamped bound B52G and (2.) the bound of the operand with the largest exponent (largest exponent operand bound B52E). This dominant bound B52H is the best-case bound of the operand when there is no rounding or cancellation. In an arithmetic operation, the adjusted operand with the least number of significant bits dominates this determination of the bound of the result, because the dominant bound B52H (from the bounds B52G or52E, where clamped bound B52G is derived from the adjusted bound of the operand with the smallest exponent B52F) with the largest number of lost bits is this best-case bound.

Turning to the details ofFIG. 4, the first bound swap multiplexer401, controlled by the largest exponent control302(fromFIG. 3), selects from either the first operand bound B52A or the second operand bound B52B (both fromFIG. 2A), resulting in the smallest exponent operand bound B52D. The second bound swap multiplexer402, which is also controlled by the largest exponent control302, selects from either the second operand bound B52B or the first operand bound B52A, which results in the largest exponent operand bound B52E.

The lost bits subtractor410is a circuit that subtracts the exponent difference321(FIG. 3) from the smallest exponent operand bound lost bits D54A, the lost bits portion of the smallest exponent operand bound B52D, producing the adjusted smallest exponent operand bound lost bits D54B. The adjusted smallest exponent operand bound lost bits D54B is concatenated with the smallest exponent operand bound accumulated rounding error N55A to form the adjusted bound of the operand with smallest exponent B52F. The subtraction may produce a negative adjusted smallest exponent operand bound lost bits D54B indicating that there are no significant digits lost during alignment at the alignment shifter240(FIG. 2A); this case is dealt with via the bound clamp420. The bound clamp420prohibits the adjusted bound of the operand with the smallest exponent B52F from underflowing to less than zero. This limits the clamped bound B52G to zero or greater. Zero indicates that all the bits of this adjusted operand are significant.

The bound comparator430compares the largest exponent operand bound B52E to the clamped bound B52G to determine the dominant bound control431. This dominant bound control431is asserted when the largest exponent operand bound B52E is greater than the clamped bound B52G. The dominant bound control431is used by the dominant bound multiplexer440that selects the dominant bound B52H from either the largest exponent operand bound B52E or the clamped bound B52G and is utilized in the main bound logic600ofFIG. 6A.

Turning now toFIG. 6A, the main bound logic600determines the result bound B52C of the calculated result260(FIG. 2B) of the current operation. The inputs for this are (1.) the dominant bound B52H ofFIG. 4, (2.) the number of leading zeros711(the number of most significant zeros, fromFIG. 7), and (3.) the carry adjusted bound B52M ofFIG. 6B. The result bound B52C is utilized by the calculated result260ofFIG. 2Band the determination of the result bound lost bits D54F ofFIG. 8.

In this cancellation path, when shifting right, significant bits are lost. These lost significant bits must be added to the dominant bound lost bits D54C. The dominant bound lost bits D54C is the lost bits54of the dominant bound B52H. This dominant bound lost bits D54C is used in the lost bits adder610, which adds the number of leading zeros711(fromFIG. 7) to the dominant bound lost bits D54C, resulting in the adjusted lost bits D54D. The adjusted lost bits D54D is concatenated with the dominant bound accumulated rounding error N55B to create the cancellation adjusted bound B52J. The dominant bound accumulated rounding error N55B is the accumulated rounding error of the dominant bound B52H.

Turning toFIG. 6B, the count adder640adds the accumulated rounding error N55B, the normalized rounding R57A (FIG. 7), and significand excess741(FIG. 7) producing the updated accumulated rounding error N55C.

The count comparator650asserts the count overflow651when the updated accumulated rounding error extension count C56A is greater than the dominant bound lost bits D54C ofFIG. 6A. The updated accumulated rounding error extension count C56A is the extension count56portion of the updated accumulated rounding error N55C. The dominant bound lost bits D54C and the count overflow651are utilized by the lost bits incrementer660and the adjusted bound multiplexer670.

The lost bits incrementer660adds one to the dominant bound lost bits D54C when the count overflow651is asserted producing the incremented lost bits D54E. The lost bits adjusted bound B52L is the bound comprised of the concatenation of the incremented lost bits D54E, an extension count having a value of one in the C Field56, and normalized rounding R57A.

The count adjusted bound B52K is the concatenation of the dominant bound lost bits D54C with the updated accumulated rounding error N55C.

The adjusted bound multiplexer670selects either the lost bits adjusted bound B52L when the count overflow651is asserted, or selects the count adjusted bound B52K to produce the carry adjusted bound B52M utilized by the count comparator650ofFIG. 6B.

The cancellation detector620(FIG. 6A) asserts cancellation control621when there is cancellation by determining that the number of leading zeros711is greater than one. This condition would be false, for instance, during an add operation with like signs. This condition is true when cancelation has occurred during a subtract or other operation in which cancellation may occur.

The result bound multiplexer630(FIG. 6A) selects either the cancellation adjusted bound B52J or the carry adjusted bound B52M ofFIG. 6Bdepending on the cancellation control621. The result is the result bound B52C to be included in the final result of the current operation (the calculated result260ofFIG. 2B).

Referring now to the exception logic800ofFIG. 8, the exception logic800provides controls (821and811) for the exceptions requiring specialized representation, zero and NaN. Considering the specialized representation of zero, the result of a subtract instruction yields a representation of zero when the significant bits of the result are zero. This is determined by comparing the resulting lost bits to the number of bits available in the operands of the current operation. Considering the specialized representation of the sNaN(isb)262(ofFIG. 2B)], if it is determined that the results lost bits D54F is greater than the unacceptable limit804, then the bounded floating point result280,FIG. 2B, is the specialized representation “sNaN(isb).”

Turning to the details ofFIG. 8, the significand capacity memory803is a static memory that provides the size of the T Field53plus one for the hidden bit H Field510(t+1, where width t104is the width of the significand T, as seen onFIG. 1) for the width of the current operation. Memory is addressed by the operation width control801. The operation width control801is a signal provided by the processor indicating the width of the current bounded floating point operation in the form of an address. The significand capacity memory803produces the significand capacity805, which is the total number of bits of the significand of the result (including the hidden bit H510).

The results lost bits D54F is the lost bits of the result bound B52C (FIGS. 2B, 6A). The zero detection comparator820asserts the zero selection control821(FIG. 2B) when the results lost bits D54F is greater than or equal to the significand capacity805.

The bound limit memory802is a memory (static or optionally dynamic) containing the unacceptable limit804on the result lost bits D54F for the current operation format width. This bound limit memory802, also addressed by the operation width control801, provides the unacceptable bound limit804.

The sNaN detection comparator810asserts the sNaN selection control811when the result lost bits D54F is greater than or equal to the unacceptable bound limit804. The sNaN selection control811is the signal provided to the exception and result multiplexer270(FIG. 2B) to select the sNaN(isb)262as the bounded floating point result280(FIG. 2B).

In the inventive apparatus and method, initially the bound limit memory802contains the default bound limit833values, which can be static (default) or dynamic (programmed bound limit831).

In the optional dynamic case shown on the right inFIG. 8, the bound limit can be changed from the default bound limit833value(s). The programmed bound limit831is a value provided by an optional bounded floating point instruction. This bounded floating point instruction stores an unacceptable bound limit804value in the bound limit memory802in a location determined by the operation width control801and occurs when the memory receives the limit write instruction830. The optional bounded floating point limit write instruction830provides an elective write control. This instruction stores a programmed bound limit831into the bound limit memory802into an address determined by the operation width control801.

The bound limit memory default reset control832is an elective control signal from an optional special bounded floating point instruction that resets all bound limit memory802locations to a default bound limit833specific for each of the bound limit memory802locations, which may be based on the precision. Optionally, the bound limit memory default reset control832can designate a particular bound limit memory802location that is to be reset to a default bound limit833, which is determined by the operation width control801.

In a first example, for single precision (32-bit, width k101=32) bounded floating point operation, if the T Field53is 16 bits in width (t104=16) providing 17 significant bits including the hidden bit H510(5 significant decimal digits), then the width of the lost bits D Field54(d105) and C Field56(c107), would need to be 3 bits each. This accommodates the standard 8-bit exponent, E Field51(width e102) and allows 1 bit for the R Field57making the N Field554 bits (n106=4). If the desired default significance is 3 decimal digits, then 10 binary bits including the hidden bit H510are required. This would mean that the allowable number of results lost bits D Field54F (width d105) could not exceed 7, the required value of the acceptable bound limit804for the bound limit memory802selected by the operation width control801for a single precision bounded floating point operation.

As an additional example, for a double precision (64-bit, width k101=64) bounded floating point operation, if the T Field53is 36 bits in width (width t104=36), providing 37 significant bits (11+ significant decimal digits) including the hidden bit H510, as specified in the significand capacity memory803location corresponding to a double precision operation, then the width of the lost bits D Field54(d105) and the C Field54(c107) would need to be 6 bits each allowing 4 bits for the R Field57(width r108=4) thereby making the N Field5510 bits (width n106=10). If the desired default decimal significance is 6 decimal digits, then 20 binary bits, including the hidden bit H510, are required. This would mean that the allowable number of results lost bits D54F could not exceed 17, the required value of the acceptable bound limit804for the bound limit memory802selected by the operation width control801for a double precision bounded floating point operation.

Turning back toFIG. 2B, the exception and result multiplexer270selects the bounded floating point result280from either the calculated result260, BFP zero261, or sNaN(isb)262based on the zero selection control821or the sNaN selection control811. The zero selection control821takes precedence over the sNaN selection control811. If neither the zero selection control821nor the sNaN selection control811is asserted, then the bounded floating point result280is the calculated floating point result260.

Where O is the exponent offset, t is the width of the significand, T is the value of the significand, S is the sign 0 or 1, E is the exponent, D is the lost bits, and 2tis the hidden bit H510:

the real value represented by a non-zero, non-NaN, and normalized bounded floating point value lies between the following:
−1S×((T+2t)/2t-1)E-Oand −1S×((T+2t+2D)/2t-1)E-O

and for denormalized values (where the value of the E Field is zero and there are no hidden bits), the first and second bounds are the following:
−1S×T/2t-1and −1S×(T+2D)/2t-1

and the expected value is the average of the first and second bounds.

Error that is introduced into floating point values when converted from an external decimal representation can be recorded in this inventive floating point representation. Conversion to external representation of a real number in decimal can be confined to only significant bits or can be expressed as a bounded real number of the form v+/−e where v is the expected real value expressed as a real number (in the format x×10p), where x is a decimal value and p is an integer power of 10) and e is the first and second bound of the error expressed as a similarly formatted real number.

In the present inventive apparatus and methods when two values are compared by subtraction in which cancellation occurs two considerations are made, as follows.

In considering equality, when the two operands are equal in their significant bits, the result will truly be zero. As noted above, when the number of lost bits exceeds the number of bits available for the significand (or exceeds the significand capacity805), the result of the equality comparison operation is set to the representation for zero. However, when the result is significantly zero in a subtraction operation, and that result is used in additional mathematical operations, it may be desirable to retain the bound field for that zero. This may require separate bounded floating point operations for comparison and subtraction.

In considering non-equality, in which there are typically four instances, which are greater-than, less-than, greater-than-or-equal-to, and less-than-or-equal-to, there are only two instances that need to be considered, because equal-to is handled as noted above. In considering greater-than, if the maximum value of the first operand is greater than the maximum value of the second operand, then the first operand is greater than the second operand. Similarly, if the minimum value of the second operand is less than the minimum value of the first operand, then the first operand is greater than the second operand.

In some instances, the sign of the result of the operation does not necessarily reflect the greater-than or less-than condition. This occurs when the minimum value of the first operand is less than the maximum value of the second operand and the maximum value of the second operand is greater than the minimum value of the first operand. In this instance, conventional methods may be relied upon to determine the result. These instances may also require special bounded floating point instructions.

In the present inventive apparatus and method, conversion of one bounded floating point width to a larger bounded floating point width (e.g., 32-bit to 64-bit, etc.) requires conversion of the loss of significant bits D Field54from the narrow width to the wider width. This requires that the number of retained significant bits be calculated for the first width and then converted to loss of significant bits for the second width. This may result in the generation of the sNaN(isb)262when converting, for instance, from 32-bit to 64-bit bounded floating point representations, when the newly computed loss of significant bits exceeds the limit value (unacceptable bound limit804) for the new width. Similarly, when converting from wider to narrower bounded floating point widths, all of the bits may be significant but bits lost from the X Field60R (FIG. 5) obtained from the wider representation must be accumulated as the initial loss of significant bits.

The exemplary embodiment depicted herein, describes a bounded floating point circuit with real-time error bound tracking within or in association with a processor, computer system, or other processing apparatus. In this description, numerous specific details such as processing logic, processor types, micro-architectural conditions, events, enablement mechanisms, and the like are set forth in order to provide a more thorough understanding of embodiments of the present invention. It will be appreciated, however, by one skilled in the art, that the invention may be practiced without such specific details. Additionally, some well-known structures, circuits, and the like have not been shown in detail to avoid unnecessarily obscuring embodiments of the present invention.

One embodiment of the present invention may provide a single core or multi-core bounded floating point processor or may be included in other floating point or general purpose processors. The processor may comprise a register file and a permutation (multiplexer) unit coupled to the register file. The register file may have a plurality of register banks and an input to receive a selection signal. The selection signal may select one or more unit widths of a register bank as a data element boundary for read or write operations.

Although the herein described embodiments are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments of the present invention can be applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. The teachings of embodiments of the present invention are applicable to any processor or machine that performs data manipulations. However, the present invention is not limited to processors or machines that perform specific data width operations and can be applied to any processor and machine in which manipulation or management of data is performed whether such operations are conducted with binary, decimal, or binary encoded decimal data representations.

In addition, though the embodiment presented herein represents an apparatus and associated method for bounded floating point addition and subtraction, it is presented as an example of bounded floating point operations. By extension, the same inventive apparatus for calculating and retaining a bound on error during floating point operations can be used in other floating point operations such as multiplication, division, square root, multiply-add, and other floating point functions. Other embodiments may contain ancillary bounded floating point operations such as conversion between floating point formats including, but not limited to, external representations of real numbers, standard floating point, bounded floating point, and includes formats of varying width.

Although the examples provided herein describe instruction handling and distribution in the context of execution units and logic circuits, other embodiments of the present invention can be accomplished by way of data or instructions stored on a machine-readable, tangible medium, which, when performed by a machine, cause the machine to perform functions consistent with at least one embodiment of the invention. In one embodiment, functions associated with embodiments of the present invention are embodied in machine-executable instructions. The instructions can be used to cause a general-purpose or special-purpose processor that is programmed with the instructions to perform the steps of the present invention. Embodiments of the present invention may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform one or more operations according to embodiments of the present invention. Alternatively, steps of embodiments of the present invention might be performed by specific hardware components that contain fixed-function logic for performing the steps, or by any combination of programmed computer components and fixed-function hardware components.

In modern processors, a number of different execution units are used to process and execute a variety of code and instructions. Not all instructions are created equal as some are quicker to complete while others can take a number of clock cycles to complete. The faster the throughput of instructions, the better the overall performance of the processor. Thus, it would be advantageous to have as many instructions execute as fast as possible. However, there are certain instructions that have greater complexity and require more in terms of execution time and processor resources. For example, there are floating point instructions, load/store operations, data moves, etc.

As more computer systems are used in Internet, text, and multimedia applications, additional processor support has been introduced over time. In one embodiment, an instruction set may be associated with one or more computer architectures, including data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O).

In one embodiment, the instruction set architecture (ISA) may be implemented by one or more micro-architectures, with associated micro-code, which includes processor logic and circuits used to implement one or more instruction sets. Accordingly, processors with different micro-architectures can share at least a portion of a common instruction set. For example, Intel® processors, Intel® Core™ processors, and processors from Advanced Micro Devices implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. Similarly, processors designed by other processor development companies, such as ARM Holdings, Ltd., MIPS, or their licensees or adopters, may share at least a portion a common instruction set, but may include different processor designs. For example, the same register architecture of the ISA may be implemented in different ways in different micro-architectures using new or well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file). In one embodiment, registers may include one or more registers, register architectures, register files, or other register sets that may or may not be addressable by a software programmer.

In one embodiment, a floating point format may include additional fields or formats indicating various fields (number of bits, location of bits, etc.). Some floating point formats may be further broken down into or defined by data templates (or sub formats). For example, the data templates of a given data format may be defined to have different subsets of the data format's fields and/or defined to have a given field interpreted differently.

Scientific, financial, auto-vectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation) may require the same operation to be performed on a large number of data items. In one embodiment, Single Instruction Multiple Data (SIMD) refers to a type of instruction that causes a processor to perform an operation on multiple data elements. SIMD technology may be used in processors that can logically divide the bits in a register into a number of fixed-sized or variable-sized data elements, each of which represents a separate value. For example, in one embodiment, the bits in a 64-bit register may be organized as a source operand containing four separate 16-bit data elements, each of which represents a separate 16-bit value. This type of data may be referred to as ‘packed’ data type or ‘vector’ data type, and operands of this data type are referred to as packed data operands or vector operands. In one embodiment, a packed data item or vector may be a sequence of packed data elements stored within a single register, and a packed data operand or a vector operand may a source or destination operand of a SIMD instruction (or ‘packed data instruction’ or a ‘vector instruction’). In one embodiment, a SIMD instruction specifies a single vector operation to be performed on two or more source vector operands to generate a destination vector operand (also referred to as a result vector operand) of the same or different size, with the same or different number of data elements, and in the same or different data element order.

In one embodiment, destination and source registers/data are generic terms to represent the source and destination of the corresponding data or operation. In some embodiments, they may be implemented by registers, memory, or other storage areas having other names or functions other than those depicted. For example, in one embodiment, the calculated result260may be a temporary storage register or other storage area, whereas the first operand201and the second operand202may be a first and second source storage register or other storage area, and so forth. In other embodiments, two or more of the operand and result storage areas may correspond to different data storage elements within the same storage area (e.g., a SIMD register). In one embodiment, one of the source registers may also act as a destination register by, for example, writing back the result of an operation performed on the first and second source data to one of the two source registers serving as a destination registers.

In one embodiment, a non-transitory machine-readable storage medium comprising all computer-readable media except for a transitory, propagating signal, may contain all or part of the invention described herein.

GLOSSARYNo.NameDescriptionFIG. 1fieldrefers to either a portion of a data structure or the value of thatportion of the data structure100bounded floatingprovides a virtual bitwise layout of the new floating point format.point format50sign bit field (Sis the standard floating point sign bit. (Information Technology -Field)Microprocessor Systems - Floating-Point Arithmetic, InternationalStandard, ISO/IEC/IEEE 60569: 2011. Geneva: ISO, 2011, p. 9)51exponent field (Eis the biased floating point exponent. (Information Technology -Field)Microprocessor Systems - Floating-Point Arithmetic, InternationalStandard, ISO/IEC/IEEE 60569: 2011. Geneva: ISO, 2011, p. 9)52bound field (Bis a new field added to the floating point standard to provideField)accumulated information on the bound of the represented realnumber.53significand field (Tis the floating point significand. It is the fraction of the floating pointField)value less the hidden bit H 510 of the current art. (InformationTechnology - Microprocessor Systems - Floating-PointArithmetic, International Standard, ISO/IEC/IEEE 60569: 2011.Geneva: ISO, 2011, p. 9) The width t of the bounded floating pointformat 100 is smaller than the corresponding standard format widthto accommodate the bound B Field 52.54lost bits field (Dis the number of bits in the floating point representation that are noField)longer significant. This is a subfield of the bound B Field 52 of thebounded floating point format 100.55accumulatedis the accumulation of the rounding errors that occur from alignmentrounding error fieldand normalization. This is a subfield of the bound B Field 52 of the(N Field)bounded floating point format 100. It is composed of the C Field 56and the R Field 57.56rounding erroris the sum of the carries from the sum of the R Field 57R fromcount field (C Field)successive operations. This is a subfield of the N Field 55 of thebounded floating point format 100.57rounding bits fieldis the sum of the rounded most significant bits of the rounding error,(R Field)lost during truncation. This is a subfield of the N Field 55 of thebounded floating point format 100.101bounded floatingis the width of a bounded floating point number. (Informationpoint widthTechnology - Microprocessor Systems - Floating-PointArithmetic, International Standard, ISO/IEC/IEEE 60569: 2011.Geneva: ISO, 2011, pp. 13-14)102width eis the width, e, of the exponent E Field 51.103width bis the width, b, of the bound B Field 52.104width tis the width, t, of the T Fields 53 (FIG. 1), 53R (FIG. 5)105width dis the width, d, of the lost bits D Field 54.106width nis the width, n, of the N Field 55.107width cis the width, c, of the C Field 56.108width ris the width, r, of the R Fields 57 (FIG. 1), 57R (FIG. 5).FIGS. 2A & 2B200bounded floatingis the data and control flow diagram of the apparatus and method forpointcomputing the exemplary bounded floating point addition andaddition/subtractionsubtraction operations, which can also be applied to otherdiagrammathematical operations.201first operanddata from the first operand register 210 of the registers 990 (where aregister may be a hardware register, a location in a register file, or amemory location) conforming to the bounded floating point format100 for an addition operation and the minuend for a subtractoperation.202second operanddata from the second operand register 220 of the registers 990 (wherea register may be a hardware register, a location in a register file, or amemory location) conforming to the bounded floating point format100 for an addition operation and the subtrahend for a subtractoperation.210first operandis the register (where a register may be a hardware register, a locationregisterin a register file, or a memory location) that contains the first operand201 in the bounded floating point format 100.220second operandis the register (where a register may be a hardware register, a locationregisterin a register file, or a memory location) that contains the first operand202 in the bounded floating point format 100.50Afirst operand signis the S Field of the first operand 201.bit S Field51Afirst operandis the E Field of the first operand 201.exponent E52Afirst operand boundprovides the inventive bound B Field 52 for the first operand 201.B53Afirst operandis the T Field of the first operand 201.significand T50Bsecond operand signis the S Field of the second operand 202.bit S Field51Bsecond operandis the E Field of the second operand 202.exponent E52Bsecond operandProvides the inventive error bound for the second operand.bound B53Bsecond operandis the T Field of the second operand 202.significand T230first significandselects the significand of the operand with the smallest exponent 53Dswap multiplexerfrom either the first operand significand T 53A or the second operandsignificand T 53B controlled by the largest exponent control 302.231second significandselects the significand T of the operand with the largest exponent Eswap multiplexer53E from either the first operand significand T 53A or the secondoperand significand T 53B controlled by the largest exponent control302.53Dsignificand T of theis the significand T of the operand with the smallest exponent E thatoperand with theis modified by the insertion of the hidden bit H 510 with thesmallest exponent Emodified significand left justified.53Esignificand T of theis the significand T of the operand with the largest exponent E that isoperand with themodified by the insertion of the hidden bit H 510 with the modifiedlargest exponent Esignificand left justified.240alignment shiftershifts the significand T of the operand with the smallest exponent E53D to the right by the number of bits determined by the exponentdifference 321. In this invention, this shift may shift off lost bits andthe associated bound must be adjusted (see FIG. 4, Dominant BoundLogic). Bits shifted out of the end of the alignment shifter areinserted into the least significant bit of the result of the alignmentshifter.241aligned significandis the aligned significand T of the operand with the smallest exponentT of the operandE.with the smallestexponent E242alignment shift lossis a one bit shifted out of the alignment shifter 240. When thisoccurs, a one bit is inserted into the aligned significand T of theoperand with the smallest exponent E 241 ensuring that a significandexcess 741 will be detected.250significand addercalculates the sum or difference 251 of the aligned significand T ofthe operand with the smallest exponent E 241 and the significand Tof the operand with the largest exponent E 53E.251sum or differenceis the sum or difference of the aligned significand T of the operandwith the smallest exponent E 241 and the significand T of theoperand with the largest exponent E 53E.51Cresult exponent Eis the final value of the exponent after normalization adjustment.52Cresult bound Bis the bound to be included in the final result.53Ctruncated resultingis the significand of the result of the operation rounded to zero.significand T260calculated resultis the final calculated result as the concatenation of the result sign bitS 50C, the result exponent E 51C, the result bound B 52C, and thetruncated resulting significand T 53C.261BFP zerois zero in the bounded floating point representation.262sNaN(isb)is the bounded floating point representation of NaN (Not a Number,insufficient significant bits).270exception and resultselects the bounded floating point result 280 from either themultiplexercalculated result 260, BFP zero 261, or sNaN(isb)262 based on thezero selection control 821 or sNaN selection control 811.280bounded floatingis the final bounded floating point value stored in the final resultpoint resultregister 285 of the registers 990 (where register may be a hardwareregister, a location in a register file, or a memory location) of theoperation, a bounded floating point value, zero, or NaN.285final result registeris a register of the registers 990 (where register may be a hardwareregister, a location in a register file, or a memory location) containingthe bounded floating point result 280.290sign logicdetermines the result sign bit S 50C from the first operand sign bit S50A and the second operand sign bit S 50B and the right shift control702 (the effect on the sign after subtraction).50Cresult sign bit Sis the sign of the calculated result 260.FIG. 3300exponent logiccalculates the exponent difference 321 and identifies the largestexponent control 302.301exponentcompares the first operand exponent E 51A with the second operandcomparatorexponent E 51B to determine the largest exponent control 302.302largest exponentis the control signal identifying the largest of the first operandcontrolexponent E 51A or the second operand exponent E 51B and controlsthe first and second significand swap multiplexers 230, 231, thelargest and smallest exponent selection multiplexers 310, 311, andthe first and second bound swap multiplexers 401, 402.310largest exponentselects either the largest exponent E 51D from first operand exponentselectionE 51A or the second operand exponent 51B controlled by the largestmultiplexerexponent control 302.311smallest exponentselects either the smallest exponent E 51E from the first operandselectionexponent E 51A or the second operand exponent E 51B controlled bymultiplexerthe largest exponent control 302.51Dlargest exponent Eis the largest of the first operand exponent E 51A and the secondoperand exponent E 51B determined by largest exponent control 302.51Esmallest exponent Eis the smallest of the first operand exponent E 51A and the secondoperand exponent E 51B determined by largest exponent control 302.320exponent subtractorcalculates the exponent difference 321 between the largest exponentE 51D and the smallest exponent E 51E.321exponent differenceis the magnitude of the difference between the first operand exponentE 51A and the second operand exponent E 51B and controls thealignment shifter 240. In this invention the lost bits subtractor 410also subtracts the exponent difference 321 from the count portion ofthe smallest exponent operand bound B 52D to produce the adjustedbound of the operand with smallest exponent B 52F.FIG. 4400dominant bounduses the first operand bound B 52A, the second operand bound Blogic52B, the largest exponent control 302, and the exponent difference321 to determine the dominant bound B 52H. In an arithmeticoperation, the operand with the least number of significant digitsdetermines (“dominates”) the number of significant digits of theresult.401first bound swapselects either the smallest exponent operand bound B 52D from firstmultiplexeroperand bound B 52A or the second operand bound B 52B controlledby the largest exponent control 302.402second bound swapselects either the largest exponent operand bound B 52E from themultiplexerfirst operand bound B 52A or the second operand bound B 52Bcontrolled by the largest exponent control 302.52Dsmallest exponentis the bound of the operand with the smallest exponent.operand bound B52Elargest exponentis the bound of the operand with the largest exponent.operand bound B54Asmallest exponentis the lost bits D portion of the smallest exponent operand bound Boperand bound lost52D.bits D55Asmallest exponentis the accumulated rounding error portion of the smallest exponentoperand bound Boperand bound B 52D.accumulatedrounding error N410lost bits subtractorsubtracts the exponent difference 321 from the smallest exponentoperand bound lost bits D 54A producing adjusted smallest exponentoperand bound lost bits D 54B.54Badjusted smallestis the smallest exponent operand bound lost bits D 54A adjusted byexponent operandthe exponent difference 321 to account for the increase in thebound lost bits Dsignificant bits of the operand with the smallest exponent operandbound B 52D due to alignment.52Fadjusted bound ofis the concatenation of the adjusted smallest exponent operand boundthe operand withlost bits D 54B and the smallest exponent operand boundsmallest exponent Baccumulated rounding error N 55A.420bound clampprohibits the adjusted bound of the operand with smallest exponent B52F from underflowing to less than zero when the lost bits subtractor410 produces a negative value for the adjusted smallest exponentoperand bound lost bits D 54B. This limits the clamped bound B 52Gto zero or greater.52Gclamped bound Bis the adjusted bound of the operand with smallest exponent B 52Flimited to zero or greater.430bound comparatorcompares largest exponent operand bound B 52E to the clampedbound B 52G to determine the dominant bound control 431.431dominant boundcontrols the dominant bound multiplexer 440 to select the dominantcontrolbound B 52H.440dominant boundselects either the largest of the largest exponent operand bound Bmultiplexer52E or the clamped bound B 52G to determine the dominant boundB 52H.52Hdominant bound Bis the largest of the largest exponent operand bound B 52E and theclamped bound B 52G. This is the bound of the operand with theleast number of significant bits after alignment.FIG. 5500post normalizationis the format of the bounded floating point significand adder resultresult format720 after normalization.501virtual width ofis the width of the resulting sum or difference taking into accountsignificand adderpossible need for multiple additions necessary to accommodateextended bounded floating point formats.510hidden bit His the left justified hidden bit H Field 510 after normalization.53Rresultingis the resulting significand after normalization. This result isnormalizedtruncated (round to zero) to form the final result significand T. Thissignificand Tfield is t bits in width.57Rresulting roundingis a field (of width r 108) holding the most significant bits of thebits R Fieldresulting significand that are lost due to truncation. These bits areused to accumulate rounding error.60Rextended roundingis a field (of width x 502) holding the bits of the result lost due toerror X Fieldtruncation, which is to the right of the R Field 57R in the format.These bits will provide something similar to a “sticky bit.”502extended roundingis the virtual width, x, of the X Field 60R.error width xFIGS. 6A and 6B600main bound logiccalculates the result bound B 52C from the dominant bound B 52H,the carry adjusted bound B 52M, and the number of leading zeros711.54Cdominant boundis the data in the lost bits D Field 54 of the dominant bound B 52H.lost bits D55Bdominant boundis the accumulated rounding error N Field 55 of the dominant boundaccumulatedB 52H.rounding error N610lost bits adderadds the number of leading zeros 711 to the dominant bound lost bitsD 54C to obtain the adjusted lost bits D 54D. When a significand isshifted left to normalize (cancellation), insignificant bits are shiftedin from the right increasing the number of lost bits in the result.54Dadjusted lost bits Dis the dominant bound lost bits D 54C adjusted by the number ofleading zeros 711.52Jcancellationis the concatenation of the adjusted lost bits D 54D and the dominantadjusted bound Bbound accumulated rounding error N 55B.620cancellationasserts cancelation control 621 when there is cancellation bydetectordetermining that the number of leading zeros 711 is greater than one.An add operation with like signs may require a one bit right shift.621cancellation controlis the control signal indicating that cancellation has occurred asdetermined by the cancellation detector 620 controlling the result ofthe result bound multiplexer 630.630result boundselects either the incremented adjusted bound B 52J or the carrymultiplexeradjusted bound B 52M depending on whether cancellation occurred(cancellation control 621). This determines the result bound B 52C.640count adderadds the significand excess 741 to the dominant bound accumulatedrounding error N 55B and the normalized rounding R 57A yieldingthe updated accumulated rounding error N 55C.55Cupdatedis the dominant bound accumulated rounding error N 55B adjustedaccumulatedby the significand excess 741.rounding error N56Aupdatedis the extension count 56 portion of the updated accumulatedaccumulatedrounding error N 55C.rounding errorextension count C650count comparatorcompares the updated accumulated rounding error extension count C56A to the dominant bound lost bits D 54C to produce the countoverflow 651.651count overflowis asserted when the updated accumulated rounding error extensioncount C 56A is greater than or equal to the dominant bound lost bitsD 54C indicating that a single bit of significance is lost due torounding. When updated accumulated rounding error extension countC 56A and the dominant bound lost bits D 54C are both zero, thecount overflow 651 is not asserted.660lost bitsadds one to the dominant bound lost bits D 54C when the countincrementeroverflow 651 is asserted.54Eincremented lostis the dominant bound lost bits D 54C adjusted by the countbits Doverflow 651.52Kcount adjustedis the bound comprised of the concatenation of the dominant boundbound Blost bits D 54C with the updated accumulated rounding error N 55C.52Llost bits adjustedis the bound comprised of the concatenation of the incremented lostbound Bbits D 54E, a one for the value of the C Field 56, and the normalizedrounding R 57A.670adjusted boundselects either the lost bits adjusted bound B 52L when countmultiplexeroverflow 651 is asserted or the count adjusted bound B 52Kproducing the carry adjusted bound B 52M.52Mcarry adjustedis the bound adjusted for potential rounding error selected betweenbound Bthe count adjusted bound B 52K and the lost bits adjusted bound B52L.FIG. 7700normalization logicproduces the truncated resulting significand T 53C, the resultexponent E 51C, the number of leading zeros 711, the significandexcess 741, and the carry detection 701 from the sum or difference251 and the largest exponent E 51D.701carry detectiondetermines whether the sum or difference 251 had a carry outrequiring a right shift to normalize, right shift control 702.702right shift controlcontrols whether the sum or difference 251 must be shifted right tonormalize. Controls the right shifter 703.703right shifterwhen indicated by the right shift control 702, shifts the sum ordifference 251 right one bit producing the right shift result 704. Theresult is modified by the right shift loss 705.704right shift resultis the result after normalizing the sum or difference 251 determinedby the right shift control 702. When the right shift control 702 is notasserted the right shift result 704 is equal to the sum or difference251.705right shift lossis a one bit (a true bit) shifted out of the right shift result 704. Whenthis occurs, a one bit is inserted into the right shift result 704ensuring that a significand excess 741 will be detected.710most significantcounts most significant zeros of the sum or difference 251 necessaryzeros counterto normalize by shifting left. Produces the number of leading zeros711 to control the left shifter 712 and to contribute to thecomputation of the result exponent E 51C.711number of leadingis the number of most significant leading zeros. Controls the leftzerosshifter 712 and the cancellation detector 620.712left shiftershifts the right shift result 704 left the number of bits specified bynumber of leading zeros 711 required to normalize the right shiftresult 704 to produce the normalized result 720. If the mostsignificant zeros counter 710 results in no leading zeros, thenormalized result 720 is equal to the right shift result 704.720normalized resultis the result of normalizing the sum or difference 251.730exponentadjusts the largest exponent E 51D for normalization. When the rightnormalization addershift control 702 is asserted one is added to the largest exponent E51D; otherwise the number of leading zeros 711 is subtracted fromthe largest exponent E 51D. Either case produces the result exponentE 51C.57Anormalizedis the most significant r bits 108 of the normalized result 720 that arerounding Rlost due to truncation.60Anormalizedis the x 502 inventive bits of the normalized result 720 to the right ofextension Xthe normalized rounding R 57A created by alignment ornormalization but lost due to truncation.740excess significandcreates the logical OR of all bits of the normalized extension X 60Adetectorproducing the significand excess 741.741significand excessis the logical OR of all bits of the normalized extension X 60A.FIG. 8800exception logicdetermines zero control 821 and sNaN selection control 811 from theresult bound B 52C, the unacceptable bound limit 804, and thesignificand capacity 805.801operation widthis a signal provided by the processor indicating the width of thecontrolcurrent bounded floating point operation in the form of an address.802bound limitis an optionally dynamic memory containing the unacceptable limitmemoryfor the result lost bits D 54F. Initialized to default values or by anoptional special command to reset to default values. A specialoptional processor command may set the contents of the bound limitmemory 802 to custom limits for lost significant bits. Memory isaddressed by the operation width control 801.803significand capacityis a static memory that provides the size of the significand (t + 1) formemorythe width of the current operation. Memory is addressed by theoperation width control 801.804unacceptable boundis the unacceptable limit (from the bound limit memory 802) for thelimitresult lost bits D 54F selected by the current operation width control801.54Fresult bound lostis the data in the lost bits D Field 54 portion of the result bound Bbits D52C.805significand capacityis the number of bits representing the significand, including thehidden bit H 510, in the operands of the current bounded floatingpoint operation.810sNaN detectionasserts the sNaN selection control 811 when the result lost bits Dcomparator54F is greater than or equal to the unacceptable bound limit 804.811sNaN selectionis the signal provided to the exception and result multiplexer 270 tocontrolselect sNaN(isb) 262 as the bounded floating point result 280.820zero detectionasserts the zero selection control 821 when the results lost bits D 54Fcomparatoris greater than or equal to the significand capacity 805.821zero selectionis the signal provided to the exception and result multiplexer 270 tocontrolselect zero as the bounded floating point result 280.830limit writeis optional bounded floating point instruction providing an electiveinstructionwrite control. This instruction stores a programmed bound limit 831into the bound limit memory 802 into an address determined by theoperation width control 801.831programmed boundis a value provided by an optional bounded floating point instruction.limitThis bounded floating point instruction stores an unacceptable boundlimit 804 value in the bound limit memory 802 in a locationdetermined by the operation width control 801.832bound limitis an optional control signal from an optional special boundedmemory defaultfloating point instruction that resets all bound limit memory 802reset controllocations to the default bound limit 833.833default bound limitis a default value (having a pre-determined value for each precision)stored in the bound limit memory 802 in a location determined by theoperation width control 801.FIG. 9900bounded floatingis a system for computing numbers in bounded floating point formatpoint systemconsisting of a main processing unit 910 with associated registers990 and communicating with a bounded floating point unit (BFPU)950.910main processingexecutes internal instructions accessing data 201, 202, 831, 280 from,unitand to, a plurality of registers 990 (where a register may be ahardware register, a location in a register file, or a memory location)and outputs commands and data 201, 202, 831.930bounded floatinga bounded floating point arithmetic instruction such as multiply,point operationsubtract, or the exemplar bounded floating point add operation.instruction940sNaN(isb)a bounded floating point signaling NaN processor exceptionexceptiongenerated based on sNaN selection control 811.950boundedis the portion of the bounded floating point system 900 that executesfloating point unitbounded floating point operation instructions 930 on the first operand(BFPU)201 and the second operand 202 producing the bounded floatingpoint result 280 and the sNaN(isb) exception 940, when insufficientsignificant bits remain in the result or executes the limit writeinstruction 830 establishing the unacceptable bound limit 804.990registersis a plurality of registers (where a register may be a hardwareregister, a location in a register file, or a memory location). Providesstorage for the bounded floating point first input operand 201, thebounded floating point second input operand 202, bounded floatingpoint result (280), and the programmed bound limit 831.

The invention illustratively disclosed herein suitably may be practiced in the absence of any element which is not specifically disclosed herein.