Display device

According to one embodiment, a display device includes a display portion, a non-display portion around the display portion, a scanning line located in the display portion, a feed line at a common potential located in the non-display portion, a scanning line drive circuit located in the non-display portion and supplying a scanning signal to the scanning line, a first wiring line group located between the feed line and the scanning line drive circuit and connected to the scanning line drive circuit, and a transparent conductive film electrically connected to the feed line and covering the feed line, the first wiring line group and the scanning line drive circuit. The transparent conductive film has an opening overlapping the first wiring line group.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-236407, filed Dec. 18, 2018, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

Recently, in display devices, various technologies for suppressing reduction in reliability have been considered. In one example, from the perspective of securing desired adhesive strength, the following technology has been disclosed. That is, a transparent conductive film is provided between an alignment film which is in contact with a sealant and an inorganic insulating film which serves as a base for the alignment film.

In another example, in a liquid crystal display device comprising a touch sensor, from the perspective of suppressing noise caused by a high-frequency pulse for touch sensing, the following technology has been disclosed. That is, a mesh-patterned shield formed of a metal material is provided on sensor feed lines.

DETAILED DESCRIPTION

In general, according to one embodiment, a display device includes a display portion in which a plurality of pixels are arranged in a matrix in a first direction and a second direction, a non-display portion around the display portion, a scanning line located in the display portion and extending in the first direction, a feed line at a common potential located in the non-display portion and extending in the second direction, a scanning line drive circuit located in the non-display portion and supplying a scanning signal to the scanning line, a first wiring line group located between the feed line and the scanning line drive circuit and connected to the scanning line drive circuit, and a transparent conductive film electrically connected to the feed line and covering the feed line, the first wiring line group and the scanning line drive circuit. The transparent conductive film has an opening overlapping the first wiring line group.

In the present embodiment, a liquid crystal display device will be described as an example of a display device DSP. Note that the main configurations disclosed in the present embodiment are also applicable to self-luminous display devices including organic electroluminescent display elements, μLEDs, etc., electronic paper type display devices including electrophoretic elements, display devices employing micro-electromechanical systems (MEMS), and display devices employing electrochromism.

FIG. 1is a plan view showing a configuration example of the display device DSP of the present embodiment. In one example, a first direction X, a second direction Y and a third direction Z are orthogonal to one another but may cross one another at an angle other than 90 degrees. The first direction X and the second direction Y correspond to directions parallel to the surface of a substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP.

The display device DSP includes a display panel PNL, an IC chip1and a flexible printed circuit2. The display panel PNL includes a display portion DA in which an image is displayed, and a frame-shaped non-display portion NDA which surrounds the display portion DA. The display portion DA includes a plurality of pixels PX arranged in a matrix in the first direction (row direction) X and the second direction (column direction) Y.

The display panel PNL is, for example, a liquid crystal display panel, and includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC and a sealant SE. The second substrate SUB2faces the first substrate SUB1. The sealant SE is located in the non-display portion NDA, and bonds the first substrate SUB1and the second substrate SUB2together and seals in the liquid crystal layer LC. The first substrate SUB1includes a mounting portion MA which extends more in the second direction Y than the second substrate SUB2does.

The IC chip1and the flexible printed circuit2are mounted on the mounting portion MA. Note that the IC chip1may be mounted on the flexible printed circuit2.

FIG. 2is a plan view showing a configuration example of the first substrate SUB1shown inFIG. 1. The first substrate SUB1includes the above-described display portion DA and non-display portion NDA. The first substrate SUB1has substrate end portions E1to E4. The substrate end portions E1and E2extend in the second direction Y and correspond to, for example, long sides. The substrate end portions E3and E4extend in the first direction X and correspond to, for example, short sides.

The first substrate SUB1includes a touch sensor TS in the display portion DA and includes the IC chip1in the non-display portion NDA.

A display driver DD and a touch controller TC are incorporated in the IC chip1. The display driver DD outputs a signal necessary for image display such as a video signal to the display panel PNL in an image display mode of displaying an image. The touch controller TC controls the touch sensor TS in a touch sensing mode of detecting approach of an object to or contact of an object with the display device DSP. Note that the touch controller TC may be incorporated in an IC chip other than the display driver DD.

Although the touch sensor TS will be described as a self-capacitance type touch sensor, the touch sensor TS may be a mutual capacitance type touch sensor. The touch sensor TS includes a plurality of sensor electrodes Rx and a plurality of sensor lines L. The sensor electrodes Rx are located in the display portion DA and are arranged in a matrix in the first direction X and the second direction Y. In the display portion DA, the sensor lines L extend in the second direction Y and are arranged in the first direction X. Each sensor line L is provided at, for example, a position overlapping a signal line S which will be described later. In addition, each sensor line L is drawn to the non-display portion NDA, is electrically connected to the IC chip1, and is electrically connected to the touch controller TC inside the IC chip1.

Here, attention will be focused on the relationship between sensor lines L1to L3arranged in the first direction X and sensor electrodes Rx1to Rx3arranged in the second direction Y. The sensor line L1overlaps the sensor electrodes Rx1to Rx3and is electrically connected to the sensor electrode Rx1.

The sensor line L2overlaps the sensor electrodes Rx2and Rx3and is electrically connected to the sensor electrode Rx2. A dummy line D21is spaced apart from the sensor line L2. The dummy line D21overlaps the sensor electrode Rx1and is electrically connected to the sensor electrode Rx1. The sensor line L2and the dummy line D21are located on the same signal line as will be described later.

The sensor line L3overlaps the sensor electrode Rx3and is electrically connected to the sensor electrode Rx3. A dummy line D31overlaps the sensor electrode Rx1and is electrically connected to the sensor electrode Rx1. A dummy line D32is spaced apart from the dummy line D31and the sensor line L3. The dummy line D32overlaps the sensor electrode Rx2and is electrically connected to the sensor electrode Rx2. The sensor line L3and the dummy lines D31and D32are located on the same signal line.

In the touch sensing mode, the touch controller TC applies a sensor drive voltage to the sensor lines L. Consequently, the sensor drive voltage is applied to the sensor electrodes Rx, and touch sensing in the sensor electrodes Rx is performed. Sensor signals corresponding to the results of sensing in the sensor electrodes Rx are output to the touch controller TC via the sensor lines L. Based on the sensor signals, the touch controller TC or an external host detects the presence or absence of approach of an object to or contact of an object with the display device DSP and the position coordinates of the object.

In the image display mode, a common voltage (Vcom) different from the sensor drive voltage is applied to the sensor electrodes Rx. The common voltage is applied from, for example, a voltage supply portion included in the display driver DD via the sensor lines L.

The first substrate SUB1includes scanning line drive circuits GD1and GD2, a feed line F, and wiring lines W1and W2in the non-display portion NDA. The scanning line drive circuit GD1is provided between the substrate end portion E1and the display portion DA. The scanning line drive circuit GD2is provided between the substrate end portion E2and the display portion DA.

The feed line F is provided along the substrate end portions E1to E3. In the example illustrated, the feed line F is provided between the substrate end portion E1and the scanning line drive circuit GD1, and is provided between the substrate end portion E2and the scanning line drive circuit GD2. The feed line F is electrically connected to, for example, the IC chip1, and the IC chip1supplies the common voltage to the feed line F. Furthermore, the common voltage supplied to the feed line F in the image display mode and the common voltage supplied to the feed line F in the touch sensing mode may have the same potential or may have different potentials.

Each of the wiring lines W1and W2is in the form of a frame surrounding the display portion DA. The wiring line W1is provided between the feed line F and the wiring line W2. The wiring line W2is provided between the wiring line W1and the display portion DA. The potential of the wiring line W1is different from the potential of the feed line F and the wiring line W2and is, for example, a fixed potential. In addition, the potential of the wiring line W2is the same as the potential of the feed line F. The potential of the wiring line W1may be relatively lower or may be relatively higher than the potential of the wiring line W2. If the potential of the wiring line W1is lower than the potential of the wiring line W2, the wiring line W1functions as an ion trap line which traps impurity ions having positive polarity. Alternatively, if the potential of the wiring line W1is higher than the potential of the wiring line W2, the wiring line W1functions an ion trap line which traps impurity ions having negative polarity. In one example, the potential of the wiring line W2is the same as the potential of a low-potential power supply VGL.

FIG. 3is an enlarged plan view of a region including sensor electrodes Rx1and Rx11shown inFIG. 2. Scanning lines G1to G3extend in the first direction X, and are arranged and spaced apart from one another in the second direction Y. The scanning lines G1to G3are electrically connected to the scanning line drive circuits GD1and GD2. Signal lines S1to S5extend in the second direction Y, and are arranged and spaced apart from one another in the first direction X. The signal lines S1to S5are electrically connected to the display driver DD. Note that the signal lines S1to S5are still assumed to extend in the second direction Y even if parts of the signal lines S1to S5are bent.

Common electrodes CE1and CE2are arranged and spaced apart from each other in the first direction X. The common electrode CE1corresponds to the sensor electrode Rx1shown inFIG. 2, and the common electrode CE2corresponds to the sensor electrode Rx11shown inFIG. 2.

A plurality of pixel electrodes PE overlap each of the common electrodes CE1and CE2. Each pixel electrode PE is electrically connected to one of the signal lines S1to S5via a switching element SW. For example, a switching element SW1shown in the drawing is electrically connected to the scanning line G2and the signal line S3. A pixel electrode PE1overlaps the common electrode CE1and is electrically connected to the signal line S3via the switching element SW1. In addition, a pixel electrode PE2overlaps the common electrode CE2and is electrically connected to the signal line S4via a switching element SW2.

Metal lines M1to M5extend in the second direction Y and are arranged in the first direction X. The metal lines M1to M5overlap the signal lines S1to S5, respectively. For example, the metal lines M1and M2correspond to the dummy line D31shown inFIG. 2, and the metal line M4corresponds to the sensor line L4shown inFIG. 2.

The common electrode CE1overlaps the metal lines M1and M2, and is electrically connected to the metal lines M1and M2in connection portions P11and P12, respectively.

The common electrode CE2overlaps the metal lines M4and M5, and is electrically connected to the metal line M5in a connection portion P15. In the example illustrated, the common electrode CE2and the metal line M4are not electrically connected to each other. The metal line M4is electrically connected to the touch controller TC.

FIG. 4is a cross-sectional view of the display panel PNL taken along line A-B shown inFIG. 3. The example illustrated corresponds to a case where a display mode using a lateral electric field is applied.

The first substrate SUB1includes an insulating substrate10, insulating films11to16, the signal lines S2to S4, the metal lines M2to M4, the common electrodes CE1and CE2, the pixel electrodes PE1and PE2, an alignment film AL1, and the like. The insulating substrate10is a light transmissive substrate such as a glass substrate or a flexible resin substrate. The insulating films11to13are arranged in the third direction Z in this order on the insulating substrate10. Although not shown in the drawing, a semiconductor layer provided in the switching element SW is located between the insulating films11and12, and the scanning line G is located between the insulating films12and13. The signal lines S2to S4are located between the insulating films13and14. In one example, the signal lines S2to S4are formed of a layered product of titanium (Ti), aluminum (Al) and titanium (Ti) which are stacked one on top of another, but the signal lines S2to S4may be formed of other metal materials. The metal lines M2to M4are located between the insulating films14and15. The metal lines M2to M4are located directly above the signal lines S2to S4, respectively. In one example, the metal lines M2to M4are formed of a layered product of titanium (Ti), aluminum (Al) and titanium (Ti) which are stacked one on top of another or a layered product of molybdenum (Mo), aluminum (Al) and molybdenum (Mo) which are stacked one on top of another, but the metal lines M2to M4may be formed of other metal materials.

The common electrodes CE1and CE2are located between the insulating films15and16. The insulating film15has a through hole CH12corresponding to the connection portion P12. The common electrode CE1is connected to the metal line M2in the through hole CH12.

The pixel electrodes PE1and PE2are located on the insulating film16and are covered with the alignment film AL1. The pixel electrode PE1is located directly above the common electrode CE1, and the pixel electrode PE2is located directly above the common electrode CE2. Each of the common electrodes CE1and CE2and the pixel electrodes PE1and PE2is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Each of the insulating films11to13and the insulating film16is an inorganic insulating film of silicon oxide, silicon nitride, silicon oxynitride or the like, and may have a single layer structure or a multilayer structure. Each of the insulating films14and15is, for example, an organic insulating film such as acrylic resin. Note that the insulating film15may be an inorganic insulating film.

The second substrate SUB2includes an insulating substrate20, a light-shielding layer BM, a color filter layer CF, an overcoat layer OC, an alignment film AL2, and the like. The insulating substrate20is a light transmissive substrate such as a glass substrate or a resin substrate similarly to the insulating substrate10. The light-shielding layer BM and the color filter layer CF are located on a side of the insulating substrate20which faces the first substrate SUB1. The color filter layer CF includes a red color filter CFR, a green color filter CFG and a blue color filter CFB. In the example illustrated, the color filter CFB is located directly above the pixel electrode PE1, and the color filter CFR is located directly above the pixel electrode PE2. The overcoat layer OC covers the color filter layer CF. The alignment film AL2covers the overcoat layer OC. The alignment film AL1and the alignment film AL2are formed of, for example, a material exhibiting horizontal alignment properties.

The liquid crystal layer LC is located between the first substrate SUB1and the second substrate SUB2and is held between the alignment film AL1and the alignment film AL2.

An optical element OD1including a polarizer PL1is bonded to the insulating substrate10. An optical element OD2including a polarizer PL2is bonded to the insulating substrate20.

FIG. 5is a plan view showing a configuration example of the non-display portion NDA including the scanning line drive circuit GD1. Note that the non-display portion NDA including the scanning line drive circuit GD2is configured similarly to the configuration example shown inFIG. 5.

As indicated by a dash-dot line inFIG. 5, the scanning line drive circuit GD1includes scan direction switching circuits SS1and SS2, shift registers SR1and SR2, gate switches GS1to GS8, and wiring line groups WG1and WG2. The scan direction switching circuits SS1and SS2and the wiring line group WG1are located between the feed line F and the shift registers SR1and SR2in the first direction X. The wiring line group WG2is located between the shift registers SR1and SR2and the gate switches GS1to GS8in the first direction X. The gate switches GS1to GS8are located between the wiring line group WG2and the wiring line W1in the first direction X.

Although the configuration examples of the respective parts will be described later, an example of wiring lines W11to W19constituting the wiring line group WG1will be briefly described below. The wiring line W11is a wiring line for an output monitor (OUTV), and the wiring line W12is a wiring line for supplying a vertical start pulse (STV). The wiring line W13is a wiring line for supplying a clock which sets a scan direction to a forward direction (UP). The wiring lines W14and W15are wiring lines corresponding to internal nodes. The wiring line W16is a wiring line for supplying a clock which sets a scan direction to a backward direction (xUP). The wiring line W17is a wiring line for supplying a transfer clock (CKV). The wiring line W18corresponds to a high-potential power supply line (VGH). The wiring line W19corresponds to a low-potential power supply line (VGL).

Each of the wiring lines W13and W16is electrically connected to the scan direction switching circuits SS1an SS2. The wiring lines W14and W15electrically connect the scan direction switching circuits SS1and SS2which are adjacent to each other in the second direction Y. Each of the wiring lines W17to W19is electrically connected to the shift registers SR1and SR2. The shift register SR1operates based on an output signal from the scan direction switching circuit SS1and controls the gate switches GS1to GS4. The gate switches GS1to GS4are electrically connected to the scanning lines G1to G4and supply scanning signals to the scanning lines G1to G4, respectively. The shift register SR2is configured similarly to the shift register SR1.

The wiring lines constituting the wiring line group WG2include wiring lines connected to the gate switches GS and power supply lines. The gate switches GS1to GS4are provided with corresponding wiring lines of the wiring line group WG2, and these wiring lines supply gate voltages to the scanning lines G1to G4, respectively.

A transparent conductive film TF is arranged so as to cover the feed line F and the scanning line drive circuit GD1. The transparent conductive film TF is electrically connected to the feed line F in a connection portion CN. That is, the potential of the transparent conductive film TF is a common potential similarly to the feed line F. In the present embodiment, the transparent conductive film TF does not cover the entire scanning line drive circuit GD1and has a plurality of openings OP overlapping the scanning line drive circuit GD1. The openings OP are arranged in the second direction Y.

In the region overlapping the scanning line drive circuit GD1, the openings OP are formed in a region close to the feed line F or a region close to the substrate end portion E1than the display portion DA. More specifically, the openings OP overlap the wiring line group WG1. In the present embodiment, the transparent conductive film TF covers the scan direction switching circuits SS1and SS2, and in the region overlapping the wiring line group WG1, the opening OP is formed in a region between the scan direction switching circuits SS1and SS2which are adjacent to each other. Note that the transparent conductive film TF may not cover the scan direction switching circuits SS1and SS2. In that case, openings OP will be formed also in portions overlapping the scan direction switching circuits SS1and SS2, respectively, in the transparent conductive film TF located between the openings OP.

An end portion Ell on the display portion DA side of the transparent conductive film TF overlaps the gate switches GS1to GS8. That is, the transparent conductive film TF covers parts of the gate switches GS1to GS8between the wiring line group WG2and the wiring line W1. On the other hand, the end portion Ell of the transparent conductive film TF does not overlap the wiring lines W1and W2. Note that, although not shown in the drawing, a transparent conductive film in a layer different from the transparent conductive film TF may overlap each of the wiring lines W1and W2.

As indicated by a dash-dot-dot line inFIG. 5, the sealant SE overlaps the feed line F and a part of the transparent conductive film TF in a planar view. In addition, the sealant SE overlaps the openings OP in its central portion, and the end portions of the sealant SE do not overlap the openings OP. Furthermore, the sealant SE overlaps a part of the scanning line drive circuit GD1, that is, the wiring line group WG1, the scan direction switching circuits SS1and SS2and the shift registers SR1and SR2. An end portion E21on the display portion DA side of the sealant SE overlaps the wiring line group WG2. That is, the sealant SE covers a part of the wiring line group WG2between the shift registers SR1and SR2and the wiring line W1. In addition, the end portion Ell of the transparent conductive film TF is located between the end portion E21of the sealant SE and the display portion DA.

FIG. 6is a circuit configuration example of a part of the scanning line drive circuit GD1shown inFIG. 5. The scan direction switching circuit SS1includes switches SW11and SW12. Each of the switches SW11and SW12is formed of a P-type transistor and an N-type transistor which are connected in parallel. The scan direction switching circuit SS2is configured similarly to the scan direction switching circuit SS1.

The shift register SR1includes a NOR circuit NR and switches SW13to SW16. One end of the NOR circuit NR is connected to the wiring line W18which is the high-potential power supply line (VGH), and the other end of the NOR circuit NR is connected to the wiring line W19which is the low-potential power supply line (VGL). The switch SW13which is a P-type transistor is connected in series to the switch SW14which is an N-type transistor. The switch SW13side is connected to the wiring line W17, and the switch SW14side is connected to the wiring line W19. The switch SW15which is a P-type transistor is connected in series to the switch SW16which is an N-type transistor. The switch SW15side is connected to the wiring line W18, and the switch SW16side is connected to the wiring line W19.

The shift register SR2includes a NAND circuit ND and switches SW17to SW20. The switch SW17is formed of two P-type transistors which are connected in parallel. The switch SW17is connected in series to the switch SW18which is an N-type transistor. The switch SW17side is connected to the wiring line W18, and the switch SW18side is connected to the wiring line W17. The switch SW19which is a P-type transistor is connected in series to the switch SW20which is an N-type transistor. The switch SW19side is connected to the wiring line W18, and the switch SW20side is connected to the wiring line W19.

Note that the circuit configuration of the scanning line drive circuit GD1is not limited to the example illustrated.

FIG. 7is a cross-sectional view of the display panel PNL taken along line C-D including the connection portion CN shown inFIG. 5. Note that the optical elements OD1and OD2shown inFIG. 4are not illustrated. In In the first substrate SUB1, the feed line F is located between the insulating films13and14. The insulating film14has a through hole CH11penetrating to the feed line F. A connection electrode CN1is located between the insulating films14and15and is in contact with the feed line F in the through hole CH11. The insulating film15has the through hole CH12penetrating to the connection electrode CN1. A connection electrode CN2is located between the insulating films15and16and is in contact with the connection electrode CN1in the through hole CH12. The insulating film16has a through hole CH13penetrating to the connection electrode CN2. The transparent conductive film TF is located between the insulating film16and the alignment film AL1and is in contact with the connection electrode CN2in the through hole CH13.

In the example illustrated, the through holes CH11to CH13are deviated from one another in the second direction Y such that the through holes CH11to CH13will not overlap one another. That is, the insulating film15is arranged in the through hole CH11, and the insulating film16is arranged in the through hole CH12. Note that the through holes CH11to CH13may be arranged such that at least two of the through holes CH11to CH13will overlap each other.

The feed line F is a metal line located in the same layer as the signal line S2, etc., shown inFIG. 4and formed of the same material as the signal line S2. The connection electrode CN1is a metal electrode located in the same layer as the metal line M2, etc., and formed of the same material as the metal line M2. The connection electrode CN2is a transparent electrode located in the same layer as the common electrode CE1, etc., and formed of the same material as the common electrode CE1. The transparent conductive film TF is located in the same layer as the pixel electrode PE1, etc., and is formed of the same material as the pixel electrode PE1.

The sealant SE is provided between the alignment films AL1and AL2and overlaps the connection portion CN. An upper surface ALA of the alignment film AL1is in contact with the sealant SE. An upper surface TFA of the transparent conductive film TF is in contact with the alignment film AL1. A lower surface TFB of the transparent conductive film TF is in contact with the insulating film16.

FIG. 8is a cross-sectional view of the display panel PNL taken along line E-F including the opening OP shown inFIG. 5. Note that the optical elements OD1and OD2shown inFIG. 4are not illustrated. In the example illustrated, the feed line F and the wiring lines W11to W19are located in the same layer and are located between the insulating films13and14. The transparent conductive film TF is located directly above the feed line F and the wiring lines W18and W19. The opening OP is formed directly above the wiring lines W11to W17. In the opening OP, the alignment film AL1is in contact with the insulating film16.

Meanwhile, suppose that a voltage corresponding to a minimum grayscale value and a voltage corresponding to a maximum grayscale value are alternately applied to the signal lines S when a specific pattern such as a checker pattern is displayed in the display portion DA. At this time, the metal line M (and the common electrode CE electrically connected to the metal line M) overlapping the signal line S is capacitively coupled to the signal line S. Therefore, when the fluctuation of the potential of the signal line S is large, the fluctuation of the potential of the common electrode CE is large. The potential fluctuation of the common electrode CE is transferred to the feed line F via the IC chip1which is the supply source of the common potential, and may cause malfunction of the scanning line drive circuits GD1and GD2which the feed line F overlaps. In particular, the wiring line which supplies the clock or start pulse of the wiring line group WG1is more vulnerable to the influence of malfunction than the power supply line of the wiring line group WG1and the wiring line group GW2.

According to the present embodiment, the transparent conductive film TF electrically connected to the feed line F has the openings OP overlapping the scanning line drive circuits GD1and GD2. Therefore, even if the potential fluctuation of the common electrode CE is transferred to the feed line F, the influence can be reduced. Consequently, malfunction of the scanning line drive circuits GD1and GD2can be suppressed, and reduction in reliability can be suppressed.

In addition, the openings OP overlap the wiring line group WG1, and parasitic capacitance can be reduced. Furthermore, the transparent conductive film TF overlaps the circuit portions (the scan direction switching circuits SS1and SS2and the shift registers SR1and SR2) of the scanning line drive circuit GD1and the high-potential power supply line W18, and blocks an electric field from the circuit portions to the liquid crystal layer LC.

Furthermore, in the region overlapping the sealant SE, the transparent conductive film TF is firmly bonded to the alignment film AL1and the insulating film16on both the substrate end portion E1side and the display portion DA side across the opening OP. For this reason, interlayer peeling in the region overlapping the sealant SE can be suppressed.

In the present embodiment, the shift register SR1corresponds to the first shift register, and the shift register SR2corresponds to the second shift register. The scan direction switching circuit SS1corresponds to the first scan direction switching circuit, and the scan direction switching circuit S22corresponds to the second scan direction switching circuit. The wiring line group WG1corresponds to the first wiring line group, and the wiring line group WG2corresponds to the second wiring line group.

The end portion Ell of the transparent conductive film TF corresponds to the first end portion, and the end portion E21of the sealant SE corresponds to the second end portion. The insulating film14corresponds to the first insulating film, and the through hole CH11corresponds to the first through hole. The insulating film15corresponds to the second insulating film, and the through hole CH12corresponds to the second through hole. The insulating film16corresponds to the third insulating film, and the through hole CH13corresponds to the third through hole. The connection electrode CN1corresponds to the first connection electrode, and the connection electrode CN2corresponds to the second connection electrode.

As described above, according to the present embodiment, a display device which can suppress reduction in reliability can be provided.