Body bias control circuit

A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to circuits and more specifically to transistor body bias control circuits.

2. Description of the Related Art

Transistors are used to implement circuitry in an integrated circuit. For some transistors, such as some types of Field Effect Transistors, carriers (e.g. holes or electrons) move in a channel region between a source and a drain of the transistor when a voltage above a threshold voltage is applied to the gate of the transistor. Typically, the channel region is located in a doped semiconductor well.

With some transistors, both the switching speed of the transistor and the sub threshold leakage current are determined by the threshold voltage. For FETs, a higher threshold voltage corresponds to a slower switching speed and lower leakage current. A lower threshold voltage corresponds to a faster switching speed but with higher leakage current. The amount of leakage current affects the power consumption of the transistor where a higher leakage current corresponds to higher power consumption.

The threshold voltage of a transistor (and correspondingly the leakage current, power, and switching speed) can be adjusted by biasing the body of the transistor (typically the well were the channel region is located) at a voltage different than the voltage applied to the source of the transistor (source voltage). Reverse body biasing can be used to raise the threshold voltage of a transistor. With an NFET, reverse body biasing is performed by applying a voltage to the body that is less than the voltage applied to the source (typically system ground (VSS) in some examples). For a PFET, reverse body biasing is performed by applying a voltage to the body that is greater than the voltage applied to the source (typically VDD in some examples).

Forward body biasing can be used to lower the threshold voltage of a transistor. For an NFET, forward body biasing is performed by applying a voltage to the body that is higher than the voltage applied to the source. For a PFET, forward body biasing is performed by applying a voltage to the body that is less than the voltage applied to the source.

In some examples, a rise in ambient temperature causes more leakage current during operation. Hence a transistor operating in a hotter environment may generate a greater amount of leakage current than one operating in a cooler environment.

DETAILED DESCRIPTION

It has been discovered that providing a body bias control circuit that varies the effective rate of change of the body bias over time during a transition of the body bias, may provide for a system whose voltage regulation can be more desirably controlled during the transition.

As stated above, a transistor's leakage current can be changed by changing the body bias to change the threshold voltage of a transistor. It may be desirable to selectively adjust the leakage current of transistors of a circuit to control power usage or to adjust operating speed. Also, body bias may be changed during a start up or reset period.

With some circuits, a change in the amount of leakage current causes a change in current usage and power consumption of a circuit. If the leakage current changes too quickly, the voltage provided by a voltage regulator powering the circuit may be pulled outside of desired tolerances. For example, a sudden change in the power draw of a circuit may lead to an overshoot or undershoot of a supply voltage from a voltage regulator powering the circuit. Out of tolerance supply voltages may cause operational problems with a circuit (e.g. erroneous data generation, erroneous resetting, and transistor damage). Hence, with some systems, there is a desirability to limit the amount of change in leakage current during a transition of the body bias applied to transistors of a circuit.

However, in addition to the requirement to limit the amount of change in leakage current, systems may also have timing requirements limiting the time to change modes where a change in body bias is required. Such requirements include a time permitted for a change in power modes or for startup. With some systems, a faster startup time or a faster time to change power modes is preferred.

To enable fast start up or mode switching times, it may be desirable for the change in leakage current to be linear at a rate that is just below a rate that would cause a regulator output voltage to be pulled out of tolerance. Changing the leakage current at a slower rate during any part of the transition would increase startup or power mode switching times. A higher rate of change in leakage current at any point in the transition would cause the regulated voltage to be out of tolerance.

However, with some types of transistors, an amount of change in the leakage current due to a change in body bias is not proportional with the amount of change in body bias across a range of body bias voltages. With some transistors, a small change in the body bias at bias voltages near the source voltage can cause a greater amount of change in leakage current. In one example, applying an initial 100 mV change in the body bias from the source voltage provides for an approximately 23% reduction in leakage current. The second 100 mV change in body bias from the source voltage provides for an approximately 12% reduction in leakage current. The third 100 mV change in bias body bias from the source voltage provides for an approximately 9% reduction in leakage current. The last 100 mV change in body bias from the source voltage provides for only a 5% reduction in leakage current. Thus, while changing the body bias from the source voltage to a voltage value that is 400 mV from the source voltage causes an approximate 49% reduction in leakage current, almost half of that reduction occurs in the first 100 mV of change. These specific results were provided for a fast corner NFET from typical 90 nm technology, 55 nm technology or beyond, operating in an environment of 165 C, where the body bias was reduced from 0 volts to −400 mV.

In one example, the dependence of leakage current (Isubthreshold) to threshold voltage (Vth) is set forth as follows (where Vgsis the gate to source voltage, VTis the temperature voltage (see enclosed image below), and Vdsis the drain to source voltage, n is the sub-threshold correction parameter:

Isubthreshold=I0⁢ⅇVgs-VthnVT[1-ⅇ-VdsVT]
where VTis the temperature voltage derived from VT=(k*T)/q with k being the Boltzmann constant, T the absolute temperature, and q the electron charge.

Accordingly, controlling the change in body bias such that smaller changes over time occur at voltages closer to the source voltage may reduce the change in leakage current during these transition periods such that the power supply voltage will not be pulled at of tolerance.

Furthermore as shown above, the further the body bias is changed from the source voltage, the effect of a change in body bias on threshold voltage and leakage current (and therefore power consumption) is less. Thus, larger changes in body bias voltages can be tolerated at these voltages. Accordingly, at these voltages, the body bias can be changed more quickly to reduce the transition time without causing the supply voltage to be out of tolerance.

Accordingly, in some embodiments described herein, the body bias control circuit changes the body bias voltage in a manner such that the change in leakage current will not cause the power supply voltage to be operating out of tolerance during the transition and yet reduces the time needed for the transition. In one embodiment, the body bias control circuit changes the body bias such that the leakage current changes at a linear at a rate during the transmission where the linear rate is below a rate that would cause the power supply voltage to become out of tolerance. In some embodiments, the rate of change of the body bias during a transition would be dependent on the operating temperature or designed for the intended operating temperature.

In some embodiments, the body bias control circuit changes the body bias voltage from the source voltage to the desired body bias in a quadratic manner over time with smaller changes in body bias over time occurring at voltages closer to the source voltage and larger changes in body bias over time occurring at farther voltages from the source voltage. In some embodiments, this quadratic manner provides for a linear change in leakage current during the transition. The phrase “changing in a quadratic manner” does not necessarily require that the body bias voltage follows an exact quadratic curve during every moment in the transition, but instead means that the moving average of the body bias moves in a manner that is generally characterized as being quadratic, although it does not necessarily require that it be exactly quadratic. For embodiments that include a number of intermediate target levels of body bias, the moving average is calculated over multiple target level transition periods.

FIG. 1is a portion of a circuit according to one embodiment of the present invention. In the embodiment shown, circuit101includes an inverter including an NFET105and a PFET103. The gate terminals of the NFET105and PFET103are connected together at node Vin. The drain terminals of NFET105and PFET103are connected together at node Vout. The source terminal of PFET103is connected to voltage regulator output terminal106of voltage regulator104that provides a power supply voltage VDD. The source terminal of NFET105is connected to a system ground terminal.

In the embodiment shown, the body terminal of PFET103is connected to an Nwell bias voltage control circuit107. The body terminal of NFET105is connected to a Pwell bias control circuit109via node113. Circuit107controls the body bias of PFET103and circuit109controls the body bias of NFET105.

In one embodiment, control circuit109controls the body bias of transistor105such that the body bias transitions from a first bias voltage (e.g. the source voltage) to a second bias voltage over a period of time in which an effective rate of change of the body bias varies over the period. During the transition, for body bias voltages between the first bias voltage and second bias voltage closer to the source voltage, the effective rate of change of the body bias is smaller in magnitude than for body bias voltages further from the source voltage. For example, during a transition to a low power mode when it is desirable to reduce power consumption, control circuit109will perform reverse body biasing to reduce the bias voltage from ground to a negative voltage (e.g. −400 mV) to raise the voltage threshold of NFET105to reduce leakage current. During the transition, the effective rate of change of the body bias is lower in magnitude at voltages closer to ground than at voltages closer to −400 mV.

In one embodiment, control circuit107controls the body bias of PFET103to reverse bias PFET103at voltages greater than VDD during at least some low power modes. In some embodiments during a transition, the magnitude of the effective rate of change of the body bias by circuit107also increases as the body bias goes higher than VDD. However, in other embodiments, control circuit107is a connector that ties the body of PFET103to the VDD terminal.

In some embodiments, control circuits109and107may also be used to forward bias transistors NFET105and PFET103, respectively. In one embodiment, control circuits109and107control the body bias voltage during the transition to the forward bias voltages by changing the body bias voltages more slowly at body bias voltages closer to the source voltage (e.g. VDD, ground) than when the body bias voltages are farther away from the source voltage.

AlthoughFIG. 1shows that circuit101has an inverter, circuit101may include other types of circuitry including circuitry with multiple transistors arranged in various circuit configurations. In some embodiments, the other circuitry includes NFETs whose body terminals are connected to control circuit109and PFETs whose body terminals are connected to control circuit107.

FIG. 2is a block diagram of an integrated circuit201that includes a number of Pwell bias control circuits109for controlling the bias voltages of multiple NFETs (not shown) of integrated circuit201. In one embodiment, integrated circuit201includes multiple independent Pwells with each Pwell including multiple NFETs. The NFETs may be configured to implement a number of different types of circuits. Each independent Pwell has an associated bias control circuit109connected to provide a bias voltage to the Pwell to control the body bias of the NFET transistors of the independent Pwell. Accordingly, the body bias of the NFETs of a Pwell can be independently controlled from the body bias of the NFETs of the other Pwells. With such a configuration, different portions of the integrated circuit201can be placed in different power modes at different times. In other embodiments, each Pwell would be connected to multiple body bias control circuits109. Not shown inFIG. 2are the Nwell bias control circuits107or other circuitry of integrated circuit201.

FIG. 3is a circuit diagram of one embodiment of a Pwell bias control circuit109. Circuit109includes a negative charge pump301, a pump clock303, a comparator305, multiplexer (mux)307, resistor ladder311, current source309, controller313, and power switch333. Controller313includes a register315for programming parameters of the control circuit's operation. Negative charge pump301provides charge to pull node312below system ground during a transition or during a low power mode. During a transition (e.g. from a normal to low power mode) or during a low power mode, switch333couples node312to node113. In one embodiment, charge pump301is an alternate phase type of charge pump capable of providing a negative voltage (e.g. −1 volts), but may be of another type of charge pump in other embodiments. Pump clock303provides a clock signal which causes pump301to pull charge from node312. When clock303does not provide a clock signal, pump301does not pull charge from node312.

When the voltage of the non inverting input of comparator305is greater than the voltage of the inverting input (which is tied to ground), comparator305asserts a high signal to pump clock303which causes pump clock303to provide a clock signal to charge pump301. In response to the clock signal, negative charge pump301becomes operational to pull node312towards a negative voltage. Pulling node312to a negative voltage pulls lower the voltages of the tap nodes (321,323,325, and327) of resister ladder311. These nodes are connected to the inputs of mux307. Mux307is used to select one of the tap nodes (referred to as the selected node) to couple to the non inverting input of comparator305. When the selected node of ladder311reaches ground, comparator305pulls its output low, which causes clock303to cease providing the clock signal to charge pump301. At this point, node312is at the target voltage (a negative voltage) and pump301stops pulling charge from node113. As the voltage of node312drifts higher above the target voltage, pump301turns back on when the voltage of the selected node of resistive ladder311goes above ground. At which time, comparator305turns on pump clock303wherein charge pump301starts pulling charge from node312to lower the voltage of node312to the target voltage. Once it reaches the target voltage, comparator305stops negative charge pump301from pulling charge.

The resistive values between the tap nodes (321,323,325, and327) are set to provide (based on the current of current source309) different target voltages when coupled to the non inverting input of comparator305. In the embodiment shown, the individual resistive values are each of a different value. In the embodiment shown, having different resistive values provides for target voltages that are separated by different increments. In one embodiment, current source309is designed to provide 0.5 micro amps of current, but may provide other current values in other embodiments.

In the embodiment shown, the resistive values between each set of tap nodes increase quadratically from the restive value between the preceding lower set of nodes. For example, the resistive value between node327and node312is X ohms and the resistive value between nodes327and325is 2N*X where N is 0.5. Accordingly, the target voltages associated with each node decrease in a quadratic manner from bottom node327to top node321. The resistive value of X depends upon the amperage of current source309and the desired target voltages.

During a normal power mode, circuit109provides a ground voltage at node113. During a normal power mode, power switch333couples node113to the input of switch333that is coupled to ground. In the embodiment shown, switch333is controlled by controller313, but may be controlled by other circuitry in other embodiments. During a normal power mode, controller313turns off negative charge pump301by disabling pump clock303from providing the clock signal. During a low power mode or transition, controller313controls switch333to couple node113to node312. Also, during a low power mode or transition, controller313does not disable pump clock303so that pump clock is controlled by comparator305.

To control the rate of change of the body bias at node113during a transition, controller313selects a different mux input at each interval (as based on a clock signal) to set a different negative target voltage to which charge pump301pulls the voltage of node113. In the embodiment shown, at an initial period of a transition, switch333is changed to couple node312to node113and tap node327is selected. In response, charge pump301is activated until the voltage of node113matches the first negative voltage level (e.g. −10 mV).

At a second period of the transition, tap node325is selected. Because there is a greater amount of resistance between node325and node312than between node327and node312, charge pump301will pull node312(and node113) lower because node325is at a higher voltage than node327(and therefore requires a lower voltage at node312for node325to reach ground). With each successive period, a higher tap node of ladder311is selected. With each higher tap node, charge pump301pulls node312(and node113) to a lower negative voltage until the selected tap node matches system ground. In the embodiment shown, node321is associated with the lowest target voltage.

In some embodiments, controller313includes a counter (not shown) whose output is coupled to mux307to control which input is selected. Where the counter is an up counter, node327corresponds to the lowest counter position.

Controller313includes a register for programming controller313. In the embodiment shown, controller313can be programmed (e.g. by a processor during operation or by other circuitry during manufacture) to stop at a particular target voltage as the final body bias voltage of the transition. In one embodiment, the counter of controller313that controls which input of mux307is selected stops counting when the count of the counter matches the programmed value in register315. Also in some embodiments, the rate at which controller313changes taps can be changed as well. If a circuit is operating in a high temperature environment, the controller can be programmed to increase the time between voltage transitions. In other embodiments, the mux could have multiple inputs connected to the resistor ladder that could be selectively used when a slower change in body bias is desired. When a faster change in body bias is desired, some of the intermediate mux inputs would not be used. In one embodiment, circuit109is placed in a normal power mode to provide a ground voltage at node113by programming register315with a particular value (e.g. “00”). However, in other embodiments, controller313may receive other signals for switching the power mode of circuit109.

In one embodiment, the counter counts both in the up and down direction. When it's desired to go back to the higher body bias voltage to increase transistor speed, the counter would down count from selecting tap node321to selecting tap node327. However, controller313may be configured differently in other embodiments.

FIG. 4shows a graph of the voltage of node113during a transition from providing a body bias of ground to a body bias of −300 mV as per the operation of the body bias control circuit109ofFIG. 3.

InFIG. 4, the body bias is initially at 0 Volts which may represent the body bias during a normal operating mode or the body bias initially at startup. This voltage corresponds to node113being tied to ground by switch333. At the first time period (1), controller313enables pump clock303, controls switch333to couple node113to node312, and selects tap node327which corresponds to target voltage −10 mV. Because the initial voltage was 0V, enabling pump clock303and selecting tap node327causes charge pump301to turn on (as determined by the output of comparator305) and pull the voltage of node113to −10 mV. Once node113reaches −10 mV, charge pump301turns off. As shown inFIG. 4, between time1and time2, the voltage of node113ripples around the target voltage of −10 mV. At this time, when the voltage goes above −10 mV, charge pump301is turned on to pull node113below −10 mV where charge pump301is turned off.

At time2, controller313changes the tap selected by mux307to tap node325which corresponds to a target of −75 mV. At which time pump301turns on to pull the voltage of node113to −75 mV. Subsequently, pump301is turned on and off to keep the voltage of node113at −75 mV. In subsequent cycles, different taps of ladder311are selected to pull the voltage of node113to even lower target levels (−134 mV, −209 mV) until the voltage is pulled to −300 mV at time6. As noted inFIG. 4, there are 6 target voltage levels which would correspond to mux307having 6 taps. However, for simplicity, only four taps are shown inFIG. 3. In other embodiments, circuit109may have additional taps that would allow the voltage of node113to be pulled even lower (e.g. −400 mV). In one embodiment, the time intervals are about 5 μs, but may be of other intervals in other embodiments.

Line401represents a moving average of the body bias during the transition from 0 V to −300 mV. Note that the magnitude of effective rate of change (the rate of change of the moving average) is lower (a flatter tangent line) at body bias values closer to the source voltage (ground) than at voltage values farther from the source voltage (e.g. at −209 mV, −300 mV). For example, the body bias voltage decreases faster as the bias voltage moves away from the source voltage. Line401shows that the magnitude of the effective rate of change of the body bias continuously increases during the transition away from the source voltage. In one embodiment, line401is characterized as generally a quadratic function.

Providing a body bias control circuit that provides a lower magnitude of an effective rate of change of the body bias at voltages closer to the source voltage provides for a circuit that does not generate a change in leakage current that would cause the supply voltage (VDD) to be out of tolerance. Providing a body bias control circuit that has a higher magnitude of an effective rate of the change of body bias at voltages further from the source voltage allows for the change in body bias to occur at a faster rate.

In other embodiments, control circuit109may having a different number of intermediate levels, have different target voltage values of those levels, and/or change to different final voltage values. In some embodiments, the magnitude of the rate of change of the body bias may be increasing as the voltage moves away from the source voltage, but the movement of the moving average of the body bias is not characterized as being in a quadratic manner.

FIG. 4shows the progression of node113during a transition that decreases the body bias from 0 volts to −300 mV to reverse bias an NFET transistor to decrease the leakage current. If the body bias is at −300 mV and it is desired that the circuit be in a mode where the transistors switch faster, circuit109can increase the body bias incrementally such that the leakage current will not change at a rate that will cause the supply voltage to go out of tolerance.

In one embodiment, circuit109increases the body bias by sequentially selecting the tap nodes in the opposite order from the reverse biasing order. If the top node321is selected for steady state reverse biasing, controller313sequentially selects the nodes in reverse order (323,325, and then 327) to increase the voltage to 0 Volts from −300 mV. To reach 0 volts, controller313controls switch333to couple node113to ground. Controller313also disables pump clock303at this time.

At first, the voltage increases relatively quickly (from −300 mV to −134 mV in two periods). However, as the body bias approaches the source voltage (e.g. ground), the increase in body bias slows down so that the change in leakage current due to the changing body bias is maintained below a threshold that would cause supply voltage issues. Referring toFIG. 4, a curve of the moving average of the increase in voltage to ground would be a mirror image of line401about a vertical axis at time6.

FIG. 5shows another embodiment of a body bias control circuit109. Control circuit109ofFIG. 5includes a pump clock501, negative charge pump503, op amp505, resister ladder509, multiplexer507, controller511, current source524, and power switch518. During a low power mode or a transition, pump clock501continuously provides a clock signal to negative charge pump503which causes negative charge pump503to provide a voltage at a minimum value (e.g. −1 V). The output of negative charge pump503is provided to current source524and to the negative supply rail of op amp505. The resistance values of the elements of resistive ladder509decrease in a quadratic manner from 5N*X to X ohms where N is about 2. Multiplexer507includes a number of inputs that are each coupled to a tap node of resister ladder509. The output of mux507is connected to the non inverting input of amplifier505. Unlike the embodiment ofFIG. 3, the voltages of nodes521,523,525and527do not change voltage values due to negative charge pump503continuously running during a low power mode or transition. Op amp505is configured in a unity gain configuration with the output of op amp505(node520) connected to the inverting input of op amp505. Power switch518is controlled by controller511to couple node113to node520or to couple node113to ground. In other embodiments, switch518is implemented using the output driver of op amp505.

During a normal power mode, switch518provides a ground voltage to node113. Also during a normal power mode, controller511disables pump clock501such that negative charge pump503is off. During a low power mode or transition, controller511controls switch518to couple node520to node113. During this time, controller511determines the output voltage of node113by selecting the appropriate tap node of ladder509that is at that the target voltage. The op amp505being configured in the unity gain configuration provides the voltage of the selected tap node at its output node520. Accordingly, to transition the body bias from a first value to a second value, the controller sequentially selects the nodes of ladder509that are at values between the first voltage value and the second voltage value at regular intervals during the transition. Because, during a low power mode or transition, circuit109ofFIG. 5is implemented with a continuously running charge pump where the voltage values of the resistor ladder nodes are held constant, the output node113voltage appears more “smooth” or steady at the target levels than the output node113voltage of the circuit ofFIG. 3. In other embodiments, one of the taps of mux507may be connected to ground where controller511would select that tap during a normal power mode. Such an embodiment may not use switch518.

In other embodiments, the intervals at which the back bias is changed may occur at non periodic intervals during the transition. For example, in one embodiment, for body bias voltages near the source voltage, the voltage of node113would change voltage target levels more slowly. As the voltage moves away from the source voltage, the body bias would change voltage target levels more quickly. In one such example, the amount that the body bias changes during a transition step would be the same for each transition. However, each change in body bias would occur at a decreasing time interval as compared to the previous change in body bias. In one embodiment, the time interval would decrease in a quadratic manner. With such an embodiment, the magnitude of the effective rate of change of the bias voltage would increase over time.

FIG. 6shows a graph of the voltage of an output of an Nwell bias control circuit107during a transition from providing a body bias of VDD to a body bias of 300 mV above VDD for a reverse biasing of a PFET (e.g. PFET103). The different target voltages for the body bias are of the same magnitude as that ofFIG. 4for the reverse biasing of an NFET. As withFIG. 4, the magnitude of the effective rate of change of the body bias is increasing as the body bias moves away from the source voltage (e.g. VDD) towards 300 mV above VDD.

In one example, an Nwell bias control circuit for controlling the body bias of a PFET may be similar to the Pwell bias control circuits inFIGS. 3 and 5, except that the Nwell bias control circuits include a positive charge pump instead of a negative charge pump. However, in other embodiments, other configurations of an Nwell bias control circuit may be used.

To transition from a mode where the PFET is in a reverse biased condition to a mode where the body bias of the PFET is at VDD, the body bias is reduced in the opposite direction as shown inFIG. 6where the body bias goes from 300 mV above VDD to VDD in the 6 intervals shown inFIG. 6. Thus, as the body bias gets closer to VDD, the rate of change of the body bias decreases.

AlthoughFIG. 4shows a graph for reverse biasing an NFET andFIG. 6shows a graph for reverse biasing a PFET, a PFET can be forward biased as per the graph ofFIG. 4and an NFET can be forward biased as per the graph ofFIG. 6. With the case of forward biasing a PFET according toFIG. 4, the Y axis would represent the voltage below the source voltage (e.g. VDD). In the case of forward biasing an NFET according toFIG. 6, the Y axis would represent the voltage above the source voltage (e.g. ground).

The embodiments ofFIGS. 3 and 5implement a control circuit that change the body bias by stepping through a series of target level increments. In other embodiments, the body bias may be changed by ramping the body bias voltage at different rates during the transition.

As set forth above, body bias control circuits can be implemented that provide an increasing magnitude of the effective rate of change of the body bias during a transition of the body bias away from the source voltage. In some embodiments, the moving average of the body bias may change in a quadratic manner. In some embodiments, this change may provide for a change in leakage current that is linear at a rate that is just less than what would produce an out of tolerance power supply voltage.

Providing a body bias control circuit with an increasing magnitude of the effective rate of change of the body bias during a transition may provide for a circuit where the leakage current does not change so rapidly that the supply voltages go out of tolerance. Furthermore, increasing the magnitude of the effective rate of change in the body bias as the voltage moves away from the source voltage enables the transition to occur more quickly.

In one embodiment, a circuit includes a transistor including a body terminal coupled to receive a bias voltage, and a source terminal coupled to receive a source voltage. The circuit includes a body bias control circuit including an output coupled to provide the bias voltage to the body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to the source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

In another embodiment, a method for controlling a body bias voltage includes providing a bias voltage to a body terminal of a transistor and a source voltage to a source terminal of the transistor. The method includes changing the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to the source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

In another embodiment, a circuit includes a transistor including a body terminal coupled to receive a bias voltage and a source terminal coupled to receive a source voltage. The circuit includes a body bias control circuit including an output coupled to provide the bias voltage to the body terminal, wherein the body bias control circuit is configured to sequentially step at different target levels, the bias voltage from a starting bias voltage to an ending bias voltage over a period of time in which voltage step sizes between the different target levels vary over the period of time. A voltage step size between target levels closer to the source voltage is smaller than a voltage step size between target levels further from the source voltage.