Modulator module in an integrated circuit device

An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.

TECHNICAL FIELD

The present disclosure relates to integrated circuit devices, and, more particularly, to integrated circuit devices having a modulation module integral therein.

BACKGROUND

Electronic systems, such as wireless systems, may communicate by some form of electromagnetic signals, e.g., radio frequency, infrared, etc. Also there are many types of modulation that may be used for the electromagnetic signals, e.g., amplitude modulation (AM), frequency modulation (FM), phase shift keying (PSK), frequency shift keying (FSK), etc. Present technology only offers an application specific communications modulator peripheral that must be added to the other electronic logic of the wireless electronic systems. This requires additional printed circuit board real estate and a separate integrated circuit device package for a communications modulator peripheral.

In addition, there are other electronic devices that may be wired or wireless, and require modulated signals for communications and/or control of an application, e.g., motor speed and fluorescent lamp dimming control, that use a plurality of different frequencies that may be modulated between the plurality of different frequencies and/or on and off keying of any one or more of the plurality of different frequencies.

SUMMARY

What is needed is an integrated circuit device that includes a communications modulator peripheral, and provides an interface to manipulate and automate the circuitry of that communications modulator peripheral with digital logic that also is included in the integrated circuit device. The communications modulator peripheral is capable of generating substantially any form of modulation using binary data, and may generate a data modulated signal from data supplied by the digital logic of the integrated circuit device, without requiring external connections or external peripheral devices.

For example, data transmissions may use audio modems, ultrasonic, infrared (IR) and radio frequency signal devices that use an appropriate modulated carrier to send the data. Operating frequencies of the modulated carrier may be, for example but are not limited to, as low as 40 Hz and as high as 32 Mhz. Heretofore, modulating a carrier signal has typically required external circuitry apart from the integrated circuit device, e.g., microcontroller.

Different types of modulation formats may be supported, according to the teachings of this disclosure. Some of these modulation formats supported may be, for example but are not limited to, on-off keying (OOK), frequency shift keying (FSK), phase shift keying (PSK) pulse width modulation (PWM), pulse position modulation (PPM), pulse density modulation (PDM), etc.

Modulation logic is integral with the integrated circuit device and may use internal frequency sources for the carrier(s) and modulation data from the integrated circuit device internal hardware logic, modulation data that is software generated, or modulation data from an external data source(s). Modulation between ones and zeros of the data modulation transitions of the selected carrier may be synchronized automatically so as to substantially reduce “glitches” and/or other unwanted frequency content, e.g., spurious noise, in the modulated signal output. For example when synchronization is enabled, when the modulator signal switches from logic low to high or high to low (e.g., logic transitions) will the carrier sources be switched. Synchronization ensures that the current carrier signal goes to a logic low or high before switching to the logic low or high, respectively, of a different carrier signal. This feature prevents shortened carrier pulses from appearing at bit boundaries in the output signal.

Carrier sources may be, for example but are not limited to, 1) a system clock of the integrated circuit device having an independent frequency divider, 2) a plurality of pulse width modulation (PWM) and/or Pulse Position Modulation (PPM) channels capable of operating at multiple frequencies and having offset timers with a common period that enables multiple phases, 3) an external clock source(s) and 4) a plurality of pulse density modulation (PDM) channels having a fixed duty cycle and capable of operating at different numbers of pulses per time period.

Modulation sources may be, for example but are not limited to, 1) Master Synchronous Serial Port/Synchronous Serial Port (MSSP/SSP), e.g., Serial Peripheral Interface Bus (SPI) and Inter-Integrated Circuit (I2C) communications peripherals; 2) Universal Asynchronous Receiver Transmitter (UART), including Universal Synchronous Asynchronous Receiver Transmitter (USART) and Enhanced Asynchronous Receiver Transmitter (EUART) that may be used for non-return to zero (NRZ) data streams; 3) software bit for software program controlled modulation peripherals, 4) PWM module for pulse width and pulse position modulation, 5) voltage comparators for process control applications, and 6) External signals.

It is contemplated and within the scope of this disclosure that two or more carrier sources, selectable by the modulation source(s) may be at the same frequency but in different phase relationships, e.g., shifted in phase by 120 electrical degrees to drive and control three phase brushless direct current motors.

According to a specific example embodiment of this disclosure, an integrated circuit device having a modulation module comprising: a modulation mixer; a modulator multiplexer having inputs that receive a plurality of modulator signals and an output connected to a modulator input of the modulation mixer, wherein the modulator multiplexer selects a one of the plurality of modulator signals for coupling to the modulator input; a high carrier multiplexer having inputs adapted for coupling to a plurality of carrier signals and an output coupled to a high carrier input of the modulation mixer, wherein the modulator multiplexer selects which one of the plurality of carrier signals is coupled to the high carrier input; a low carrier multiplexer having inputs adapted for coupling to the plurality of carrier signals and an output coupled to a low carrier input of the modulation mixer, wherein the modulator multiplexer selects which one of the plurality of carrier signals is coupled to the low carrier input; and wherein the modulation mixer outputs a modulated signal derived from the high carrier input when the modulator input is at a first logic level and from the low carrier input when the modulator input is at a second logic level.

DETAILED DESCRIPTION

Referring now to the drawing, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

Referring toFIG. 1, depicted is a schematic block diagram of an integrated circuit device comprising a modulator module, according to a specific example embodiment of this disclosure. An integrated circuit device, generally represented by the numeral100, comprises a modulator module having modulation control logic106, a signal modulation mixer108, an XOR gate110, a modulator multiplexer112, a high carrier multiplexer114, a low carrier multiplexer116, and input receivers and output drivers (I/O)118. The integrated circuit device100may further comprise a digital processor102and a memory104. The integrated circuit device100may be, for example but is not limited to, a microcontroller, a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic array (PLA), a field-programmable gate array (FPGA), etc. Generally, the digital processor102is controlled with a software/firmware program stored in the memory104. The memory104may be volatile and/or nonvolatile random access memory (RAM), and the like.

The function of the modulation control logic106may be performed by the digital processor102controlled by a software program (not shown), and/or dedicated hardware/firmware logic specifically designed to operate the multiplexers112,114and116, according to the teachings of this disclosure. The modulation control logic106may be may be, for example but is not limited to, a state machine. The XOR gate110may be used to invert the polarity of the modulated signal128coming from the signal modulation mixer108. The modulation control logic106may have a shutdown control input for shutting down the modulator module when not used or when the integrated circuit device is in a standby or sleep mode. When the modulation control logic106is shutdown its output may also be put into a high impedance state, e.g., tri-state output.

Any one of a plurality of modulation signals may be selected at any time through the modulator multiplexer112. Any two of a plurality of carrier signals may be selected at any time through the high carrier multiplexer114and low carrier multiplexer116, respectively. This feature enables having a plurality of different frequency pulses in a pulse stream, e.g., for fluorescent lamp drive and dimming applications, light emitting diode (LED) brightness control applications, brushless direct current motor drive and control applications, etc.

The modulator module provides the capability of generating a modulated signal128and sending this signal128through the I/O118of the integrated circuit device100without requiring external modulator and driver circuits.

Referring toFIG. 2, depicted is a schematic diagram of a mixer in the modulator module of the integrated circuit device shown inFIG. 1, according to a specific example embodiment of this disclosure. The high and/or low carriers may be from internal clocks, clocks and frequency dividers, timers, external, etc. The signal modulation mixer108takes the incoming modulator signal from the output122of the modulator multiplexer112which is ANDed with a carrier signal from either the high carrier124from the high carrier multiplexer114or the low carrier126from the low carrier multiplexer116to create the modulated signal128.

Modulator sources may be from internal data signal sources and/or external data signal sources (not shown). Any one of a plurality of modulator sources may be selected through the modulator multiplexer112. The selected modulator source is a data stream that will modulate one or two carriers, i.e., high carrier124or low carrier126(sequentially in time). In addition, the high carrier multiplexer114and/or the low carrier multiplexer116may be used to select more then one high carrier output124, and/or low carrier output126, respectively, so that a plurality of high and/or low carriers may be in the data stream sequentially. This feature is most advantageous for brightness control of fluorescent lamps having heated filaments, and speed control of brushless direct current motors.

A unique feature of the signal modulation mixer108is carrier synchronization which insures that substantially no glitches occur in the modulated signal128. Glitches or shortened carrier pulses are caused by the modulator switching from one carrier frequency to another. When carrier switching synchronization is enabled and the modulator data switches logic levels, e.g., from a logic high to a logic low or visa versa, the modulation mixer108first waits for the current carrier to go to a logic low. That carrier output is then latched low enabling the output of the data low carrier. Once a falling edge is detected on the data low carrier, output is enabled for that carrier source.

The carrier switching synchronization may be accomplished when a logic high is applied to the high carrier synchronization control port of the multiplexer236, and/or the low carrier synchronization control port of the multiplexer238. The D-flip-flops240and242retain the logic levels of the high carrier124and the low carrier126, respectively. So that whenever there is a logic level change in the modulator signal122and one or both of the carrier synchronization control ports is at a logic high, switching between the high carrier and the low carrier, or visa versa, will occur as more fully described hereinafter. The high and low carrier logic levels may be reversed through the XOR gates250and252, respectively. It is contemplated and within the scope of this disclosure that other logic circuit designs may be utilized for the functions of the circuit shown inFIG. 1, and would be readily apparent to one having ordinary skill in digital logic design and having the knowledge of the teachings of this disclosure.

Referring toFIG. 3, depicted is a schematic timing diagram of an on and off keying (OOK) modulated signal, according to the teachings of this disclosure. The modulator signal122causes the signal modulation mixer108to switch between the high carrier signal124and the low carrier signal126. In the example shown inFIG. 3the low carrier signal126is at a logic low continuously, i.e., off. Whenever the modulator signal122is at a logic high, the signal modulation mixer108will use the high carrier signal124, and whenever the modulator signal122is at a logic low, the signal modulation mixer108will use the low carrier signal126. How enabling and/or disabling synchronization for the high and low carriers affects the modulated signal128are illustrated in the four lower waveform graphs (a)-(d).

Referring now to waveform graph (a), high carrier synchronization is enabled and low carrier synchronization is disabled. Whenever the modulator signal122goes to logic low and the high carrier signal124goes to logic low, the modulated signal128will go to logic low. Thus, the transition from the high carrier signal124to the low carrier signal126will be synchronized with the logic level change (from high to low) of the high carrier signal124.

Referring now to waveform graph (b), both high carrier and low carrier synchronizations are enabled. Whenever the modulator signal122goes to logic low and the high carrier signal124goes to logic low, the modulated signal128will go to logic low. Thus, the transitions between the high carrier signal124and the low carrier signal126will be synchronized with a logic level change from high to low. In this example, the low carrier signal126is always at a logic low so the modulated signal128is the same as in waveform graph (a).

Referring now to waveform graph (c), both high carrier and low carrier synchronizations are disabled. Whenever the modulator signal122goes to logic low the modulated signal128will go to logic low. The transition from the high carrier signal124to the low carrier signal126may be truncated as illustrated at time points (1), (2) and (3).

Referring now to waveform graph (d), high carrier synchronization is disabled and low carrier synchronization is enabled. Whenever the modulator signal122goes to logic low the modulated signal128will go to logic low. The transition from the high carrier signal124to the low carrier signal126may be truncated as illustrated at time points (1), (2) and (3). In this example, the low carrier signal126is always at a logic low so the modulated signal128is the same as in waveform graph (c).

Referring toFIG. 4, depicted is a schematic timing diagram of a modulated signal without carrier synchronization when switching between the high and low carriers, according to the teachings of this disclosure. When the modulator signal122is at a logic high the modulated signal128follows the logic states of the high carrier signal124, and when the modulator signal122is at a logic low the modulated signal128follows the logic states of the low carrier signal126. The modulated signal128is representative of a FSK or PSK modulated carrier. In the example shown inFIG. 4, the logic state changes of the modulated signal128follow the carrier signal selection between the high carrier signal124and low carrier signal126according to the logic state changes of the modulator signal122without regard to the logic states of the high carrier signal124and low carrier signal126. As can be seen at time points (1), (2) and (3), the waveforms of the modulated signal128are truncated and are prone to producing “glitches” and frequency spurs.

Referring toFIG. 5, depicted is a schematic timing diagram of a modulated signal with only high carrier synchronization when switching between the high and low carriers, according to the teachings of this disclosure. The modulated signal128follows the logic states of the high carrier signal124so long as the modulator signal122is at a logic high. However when the modulator signal122goes to a logic low, switching to the low carrier signal126to be used as the modulated signal128is delayed until the high carrier signal124is at a logic low. This prevents some of the glitch problems encountered as shown inFIG. 4. However when the modulator signal122goes back to a logic high, the modulated signal128will switch back to the high carrier signal124irrespective of the logic state of the low carrier signal126. This still may introduce some undesirable waveforms, e.g., shortening of pulse widths.

Referring toFIG. 6, depicted is a schematic timing diagram of a modulated signal with only low carrier synchronization when switching between the high and low carriers, according to the teachings of this disclosure. The modulated signal128follows the logic states of the low carrier signal126so long as the modulator signal122is at a logic low. However when the modulator signal122goes to a logic high, switching to the high carrier signal124to be used as the modulated signal128is delayed until the low carrier signal126is at a logic low. This prevents some of the glitch problems encountered as shown inFIG. 4. However when the modulator signal122goes back to a logic low, the modulated signal128will switch back to the low carrier signal126irrespective of the logic state of the high carrier signal124. This still may introduce some undesirable waveforms, e.g., shortening of pulse widths.

Referring toFIG. 7, depicted is a schematic timing diagram of a modulated signal with high and low carrier synchronization when switching between the high and low carriers, according to the teachings of this disclosure. The modulated signal128follows the logic states of the high carrier signal124when the modulator signal122is at a logic high and the low carrier signal126when as the modulator signal122is at a logic low unless the modulator signal122is transitioning between logic states, i.e., logic high to logic low or visa versa. The modulated signal128will only switch from the high carrier signal124to the low carrier signal126when the modulator signal122is at a logic low and the high carrier signal124is at a logic low. Likewise, the modulated signal128will only switch from the low carrier signal126to the high carrier signal124when the modulator signal122is at a logic high and the low carrier signal126is at a logic low. Synchronizing the modulator signal122with both the high carrier signal124and the low carrier signal126maintains the proper respective waveforms of the modulated signal128and substantially reduces glitches therein.

Referring toFIG. 8, depicted is a schematic block diagram of a fluorescent lamp driver circuit that utilizes the integrated circuit device ofFIG. 1. The fluorescent lamp circuit ofFIG. 8may be used for both fixed brightness and dimming applications. The fluorescent lamp circuit, generally represented by the numeral800, comprises an integrated circuit device100a, high and low side metal oxide semiconductor field effect transistor (MOSFET) drivers804, a high-side power MOSFET806, a low-side power MOSFET808, an inductor810, a fluorescent lamp812, a filament capacitor816, and a DC blocking capacitor814. The MOSFET drivers804are used to translate the low output voltages of the integrated circuit device100ato the high voltage levels required to operate the high side power MOSFET806and the low side power MOSFET808. The integrated circuit device100amay be used to switch the high-side driver ON or OFF, and the low-side drive OFF or On, respectively, through the MOSFET drivers804. When the high-side drive is ON the high-side power MOSFET806allows current to flow through the resonant RLC fluorescent lamp circuit (inductor810and DC blocking capacitor814) in one direction, and when the low-side drive is ON the low-side power MOSFET808allows current to flow through the resonant RLC fluorescent lamp circuit (inductor810, fluorescent lamp812and DC blocking capacitor814) in the other direction. The high-side power MOSFET806and the low-side power MOSFET808cannot be both ON at the same time. Also a dead band is desirable, e.g., the high-side power MOSFET806and the low-side power MOSFET808are both OFF. This may be easily accomplished with software instructions running in a processor digital of the integrated circuit device100a. The integrated circuit device100amay synthesize an alternating current (AC) signal by alternatively turning on the high-side and low-side outputs of the MOSFET drivers804. For fluorescent lamp dimming applications, careful control of the time duration of the high-side and low-side outputs of the MOSFET drivers804will produce an AC drive signal having specific frequencies that may be synthesized as more fully described for the embodiments shown inFIGS. 1 and 2hereinabove.

The modulator, according to the teachings of this disclosure, may be used in a variety of fluorescent lamp driver systems. For example, but not limited to, multiple frequency pulse density modulation may be effectively used in fluorescent lamp brightness control (dimming) applications. A more detailed description of brightness control using different frequencies temporally for electronic dimming of fluorescent lamps is presented in commonly owned U.S. patent application Ser. No. 11/470,052; filed Sep. 5, 2006; now U.S. Pat. No. 7,642,735, issued Jan. 5, 2010; entitled “Using Pulse Density Modulation for Controlling Dimmable Electronic Lighting Ballasts,” by John K. Gulsen and Stephen Bowling; and U.S. patent application Ser. No. 12/631,118; filed Dec. 4, 2009; entitled “Using Pulse Density Modulation for Controlling Dimmable Electronic Lighting Ballasts,” by John K. Gulsen and Stephen Bowling; wherein both are hereby incorporated by reference herein for all purposes.