Method of and arrangement for addressing a switch memory in a transit exchange for synchronous data signals

A method of and an apparatus is disclosed for economically addressing memory positions in a switch memory of a transit exchange for the transfer of synchronous data signals between incoming and outgoing TDM links comprising data channels of several data rates, each constituting a multiple of a basic rate derived from the number of time slots in a TDM frame. The data signals are stored in a switch memory having a memory position for each of the data channels in the incoming links and are then transferred to a buffer memory having a memory position for each time slot of the data channels in the outgoing links before they are sent out on these links. The memory writing as well as the reading occurring at a repetition rate determined by the data rate of the respective data channel. The data signals are written into the switch memory by the aid of an address calculator including a structure memory for the storage of information indicating the allocation of time slots to the various data channels of each link, which information is common to all links of the same type, and a type memory for the storage of type designations where the relevant type designation is addressed by means of the identity number of the link.

The present invention relates to a method of and an arrangement for 
economically addressing memory positions in a switch memory in a transit 
exchange for the transfer of synchronous data signals from incoming TDM 
links to outgoing TDM links. When the links transfer data channels of 
several data rates which constitute multiples of a basic rate derived from 
the number of time slots in a TDM frame, the transit exchange includes a 
switch memory for storage of incoming data signals in memory positions, 
each of which is assigned to one of the incoming data channels in the 
incoming links, and a buffer memory to which the data signals are 
transferred and are stored in memory positions assigned to the time slots 
belonging to the respective channel in the outgoing links before they are 
sent out via these links, the writing as well as the reading occurring at 
a repetition rate determined by the data rate of the respective channel. 
The traffic in large public data networks is likely to have a high call 
intensity and short occupation times for a very great part of the traffic. 
In order to reduce the load on the common control functions, therefore, it 
is expedient to design the transit exchange in such a way that each data 
channel has its own signal sending and signal receiving units at its 
disposal which are directly connected to the channel. Thereby searching 
for free signalling units as well as connection and disconnection of the 
calling and the called channel to and from the signalling units can be 
avoided. 
In the case when all the data channels have the same data rate, a switching 
network using signal units working according to the time division 
multiplex principle can be obtained in such a way that the incoming 
transmission direction from all the connected channels is multiplexed onto 
a common data bus. The switching network is then furnished with a switch 
memory, where each channel is represented by a word. The word which 
corresponds to a certain channel is read from the memory at the same time 
as the incoming data from the channel is put onto the common bus system. 
At that moment a common logic unit can treat the incoming data in 
dependence of information about the channel and previously received data 
signals which are stored in the channel word. 
A connection network based on this principle is described, for example, in 
the Swedish patent application 7310969-6 and in IEEE, Transactions on 
Communications, Nov. 1974, in an article titled "A Time-Division Data 
Switch." 
Switching networks for synchronous data intended for time division 
multiplexed trunk lines and comprising channels of several rates quite 
seldomly appear in available literature. The report pulished by The 
Central National Administration of the Swedish Board of Telecommunications 
"Separate Common Data Networks, System Research," however, comprises a 
basic proposal for such a switching network. 
The above mentioned proposal describes a switching network which includes a 
control memory comprising a word for each time slot in every incoming 
multiplex and a buffer memory comprising a position for each time slot in 
every outgoing multiplex. The incoming multiplex connections are "frame 
adjusted" in an equipment tied to each connection, whereby time slots with 
the same order number in all multiplex frames are simultaneously available 
on the input to the switching network. Therefore the interrelation of the 
time slots in each multiplex to the words in the control memory can be 
simply identified. The words in the control memory comprise address 
information for addressing, on the one hand, the positions in the buffer 
memory and, on the other hand, special signal devices for line signalling 
and centralized signalling. Signal emitting devices are connected, in 
principle, in the same way as incoming channels, i.e. they are represented 
in the control memory by one word for each time slot being utilized. 
The described principle thus presumes individual treatment of each time 
slot for channels with higher rates than the basic rate and hence utilize 
more than one time slot. Moreover, connection of special signal devices is 
assumed during the setting-up procedures and also buffering in connection 
with each multiplex connection for frame adjustment. 
It is desirable to reduce the load on the common equipment by connecting to 
each incoming data channel a facility for signal treatment in the form of 
a word in a switch memory which also can execute the addressing function 
which was executed by the control memory according to the proposal of the 
Data Network Committee and to eliminate the need for a separate treatment 
of each time slot in the channels with higher data rates by limiting the 
number of words in the switch memory to the smallest possible, i.e. one 
word per data channel for each connected multiplex. 
The condition for being able to arrange the switch memory in the desired 
manner is the possibility to address the assigned memory word in the 
switch memory with the aid of identity information concerning a multiplex 
connection and a time slot. The multiplex identity is obtained directly 
from the equipment which controls the scanning of the incoming 
connections. The time slot identity, on the other hand, must be derived 
from the present phase position of the multiplex frames on each 
connection. The phase position information can be transferred from each 
connection, either in parallel with the data signals on a separate bus 
line, or together with the data signals in the form of synchronizing 
information on the same bus line. An evident solution for achieving the 
required addressing is to establish a table listing all time slots for 
each of the multiplex connections which are connected to the transit 
exchange and giving the address to the assigned memory word in the switch 
memory. The drawback of this solution is, for large transit exchanges 
however, that this table requires a very huge memory. An exchange can 
comprise several hundred connections, each transferring some hundred time 
slots. The above mentioned memory would then have to comprise tens of 
thousands of positions which must be read with a very short access time. 
It is an object of the invention to considerably reduce this memory 
requirement. The characteristics of the invention appear from the claims.

FIG. 1 shows a transit exchange to which each one of 4 .times. 16 = 64 
two-way connections ME 101 - MF 416 is connected via a line equipment LU 
101 - LU 416. Each of the connections is arranged for the transfer in time 
division multiplex of a number of data channels with several rates, 
constituting multiples of a basic rate. This basic rate is determined in a 
known manner by the number of time slots in a time division multiplex 
frame. According to the embodiment the TDM frames are assumed to be 
character oriented and, besides the synchronization information, to 
comprise 80 time slots for data signals, each representing the basic rate 
of 75 characters per second. In FIG. 2 the positioning of three different 
data channels in a TDM connection is schematically shown. Line a shows a 
number of frames in which the time slots which are utilized have been 
marked with different symbols and on the lines b, c and d a series of data 
elements are illustrated, e.g. characters, corresponding to each of the 
channels with the data rates 1, 2 and 4 times the basic rate for the 
connection. The line equipments are arranged in 16-groups, for example 
equipments LU 101 - LU 116, each of which is connected to a multiplexor, 
e.g. multiplexor MX1, and to a demultiplexor, e.g. demultiplexor DX1, 
having the task to switch through the connections in selected time slots 
to an incoming common multiplexor bus line MB and to individual outgoing 
demultiplexor bus lines, e.g. DB1. The multiplexors MX1 - 4 together 
constitute a sampling arrangement for the signal values of the incoming 
data channels and the demultiplexors DX1 - 4 together constitute a reading 
arrangement for the transfer of indication values representing the signal 
values of the outgoing data channels to a regeneration arrangement 
included in each line equipment as will be described later. Each line 
equipment also includes circuits for the mutual synchronization of on the 
one hand the transit exchange and on the other hand the frame structures 
of the multiplex connections. All these circuits are assumed to be known 
per se. 
The sampling and the reading functions operate synchronously and they are 
controlled by an address counter AR by means of address information which 
is transferred to all multiplexors and demultiplexors through the bus line 
AB according to a cyclic pattern where each time slot in every multiplex 
connection is addressed at a repetition rate of 75 times per second. At 
each addressing occasion, a series of sampling values carrying the 
information in a time slot are transferred to a read-in buffer IB, at the 
same time as the indication value referring to the corresponding time slot 
in the outgoing direction is transferred from a read-out buffer, e.g. UB1. 
The switching-through of the information from the read-in buffer to the 
read-out buffers takes place in a central switching equipment CK. 
The equipment CK comprises a switch memory KM to which the incoming time 
slot information is brought via a data bus DB by means of address 
information KO from an address calculating unit AD1. The data signals 
stored in the switch memory are processed by the switch logic KL which is 
supported by the control computer SD. The signal processing concerns, for 
example, decoding and storing in the switch memory the outgoing address 
during the course of a setting-up procedure. From the switch memory the 
data signals are transferred via the switch logic KL to a buffer memory BM 
where they are stored in the memory words belonging to the outgoing time 
slots. In this connection the address stored in the switch memory is 
utilized, after convertion in an address calculating unit AD2. 
The multiplex connections are addressed cyclically, whereby every cycle 
comprises 16 sequences of five steps each. During the first address step 
in each sequence, information relating to a time slot belonging to one 
multiplex connection in each of the four demultiplexors DX1 - DX4 is 
transferred from the buffer memory BM to the four read-out buffers UB1 - 
UB4. During the following four address steps the four read-out buffers are 
read out in turn to the respective time slots at the same time as the 
information from the corresponding incoming time slots are transferred in 
turn via the multiplexors MX1 - MX4 to the read-in buffer IB. At the same 
time as the information in a time slot is written into the corresponding 
memory word in the switch memory KM, information is read from the previous 
time slot into a position in the buffer memory being at the same time 
indicated by the address calculating unit AD2 which executes a simple 
conversion of the address information obtained from memory KM into a time 
slot address. The writing into the buffer memory is made in consecutive 
time slots belonging to the same data channel. 
The addressing procedure is illustrated in the timing diagram, FIG. 3, 
where the relative timing conditions for 4 different TDM connections are 
shown on the lines a, b, c and d, each comprising 80 time slots per 
multiplex frame. Within the duration of a time slot (according to the 
example the time slots 36, 71, 30 and 18 respectively for the frames 
shown), all the multiplexes are scanned in a cycle comprising, according 
to the example, 64 steps in accordance with the timing pulses on line e. 
As previously described, the cycle comprises 16 sequences, each having 
five steps. The five steps relating to sequence number 1 of the cycle are 
shown on the lines f - j. During step 001, according to line f, the above 
information transfer from the buffer memory BM to the reading buffers UB1 
- UB4 is made for the outgoing multiplex connections MF 101, 201, 301 and 
401. During the following step (101) a time slot is read in from the 
incoming multiplex connection MF 101 and the corresponding time slot is 
read-out to the outgoing multiplex connection MF 101 in synchronism with 
new write-in operations in the switch memory and the buffer memory. During 
the next step (201) the multiplex connection MF 201 is treated in the 
corresponding way and so on until the cycle is completed by the treatment 
of the multiplex connection MF 416. 
The switch memory KM, as shown in FIG. 4, has a memory area for each of the 
64 multiplex connections MF 101 - 416. In each area there is a memory word 
for each of the data channels in the respective multiplex connections, the 
number of channels depending on the allocation of the time slots to 
different rates. The greatest number of channels (80) is obtained if all 
the channels have the data rate 75 characters per second. The other 
extreme case is that all of the time slots in a multiplex connection, for 
example connection MF 415, are utilized for one data channel only with the 
rate 6000 characters per second. Between these extreme cases there are 
multiplexes with a varying number of channels of different rates within 
the range 75 - 1200 characters per second. Thus, according to the figure 
connection MF 101 has five data channels K1 - K5, all with the data rate 
1200 ch/s, while for example connection MF 416 has 10 data channels, of 
which two are for 1200 ch/s and the other are equally divided between 300 
and 600 ch/s. The writing of information into the respective memory words 
occurs at a repetition rate determined by the data rate of the data 
channels and in accordance with the address information obtained from the 
address calculating unit AD1. As previously mentioned, an analysis of the 
incoming information occurs in connection with the setting-up phase, 
whereby the address to the outgoing direction is determined. This address 
is stored in the word segment marked ADDR in FIG. 4. In the word segment