PWM control of analog front end

In an embodiment, a wireless power transmitter is disclosed that includes a first field-effect transistor, a second field-effect transistor a coil and an analog front end. The wireless power transmitter is configured to drive the coil based at least in part on activations of the first and second field-effect transistors. The analog front end includes a first driver corresponding to the first field-effect transistor and being configured to control activation of the first field-effect transistor based at least in part on a pulse-width modulation signal and a second driver corresponding to the second field-effect transistor and being configured to control activation of the second field-effect transistor based at least in part on the pulse-width modulation signal.

BACKGROUND OF THE SPECIFICATION

The present disclosure relates in general to apparatuses and methods for communication between wireless power transmitters and wireless power receivers.

Wireless power systems often include a transmitter and a receiver having a receiver coil. When a transmission coil of the transmitter and the receiver coil of the receiver are positioned close to one another they form a transformer that facilitates inductive transmission of an alternating current (AC) power between the transmitter and the receiver. The receiver often includes a rectifier circuit that converts the AC power into a direct current (DC) power that may be utilized for various loads or components that require DC power to operate. The transmitter and the receiver also utilize the transformer to exchange information or messages using various modulation schemes. For example, the receiver may include a resonant circuit having one or more capacitors and may switch in or switch out a different number of capacitors of the resonant circuit to generate amplitude shift key (ASK) signals and encode messages in the ASK signals. The receiver can transmit the ASK signals to the transmitter to communicate with the transmitter via the transformer. The transmitter decodes the messages from the ASK signals received from the receiver and encodes response messages in frequency shift key (FSK) signals that may be transmitted back to the receiver via the transformer.

SUMMARY

In an embodiment, a wireless power transmitter is disclosed that comprises a first field-effect transistor, a second field-effect transistor a coil and an analog front end. The wireless power transmitter is configured to drive the coil based at least in part on activations of the first and second field-effect transistors. The analog front end comprises a first driver corresponding to the first field-effect transistor and being configured to control activation of the first field-effect transistor based at least in part on a pulse-width modulation signal and a second driver corresponding to the second field-effect transistor and being configured to control activation of the second field-effect transistor based at least in part on the pulse-width modulation signal.

In another embodiment, a wireless power transmitter is disclosed that comprises a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a coil and an analog front end. The wireless power transmitter is configured to drive the coil based at least in part on activations of the first, second, third and fourth field-effect transistors. The analog front end comprises a first driver corresponding to the first field-effect transistor and being configured to control activation of the first field-effect transistor and a second driver corresponding to the second field-effect transistor and being configured to control activation of the second field-effect transistor. The analog front end further comprises a third driver corresponding to the third field-effect transistor and being configured to control activation of the third field-effect transistor and a fourth driver corresponding to the fourth field-effect transistor and being configured to control activation of the fourth field-effect transistor. The activation of at least one of the first field-effect transistor and the fourth field-effect transistor is controlled based at least in part on a first pulse-width modulation signal. The activation of at least one of the second field-effect transistor and the third field-effect transistor is controlled based at least in part on a second pulse-width modulation signal.

In another embodiment, a wireless power transmitter is disclosed that comprises a coil, a plurality of field-effect transistors that are configured to drive the coil, an analog front end that is configured to control activations of the plurality of field-effect transistors and a controller that is configured to provide an unencoded pulse-width modulation signal to the analog front end. The analog front end is configured to control the activation of at least one of the field-effect transistors based at least in part on the unencoded pulse-width modulation signal.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. In the drawings, like reference numbers indicate identical or functionally similar elements.

DETAILED DESCRIPTION

FIG.1is a diagram showing an example system100that implements wireless power transfer and communication according to an illustrative embodiment. System100comprises a transmitter110and a receiver120that are configured to wirelessly transfer power and data therebetween via inductive coupling. While described herein as transmitter110and receiver120, each of transmitter110and receiver120may be configured to both transmit and receive power or data therebetween via inductive coupling.

Transmitter110is configured to receive power from one or more power supplies116(FIG.2) and to transmit AC power to receiver120wirelessly. For example, transmitter110may be configured for connection to a power supply116such as, e.g., an AC power supply or a DC power supply. Transmitter110comprises a controller112and a power driver114.

Controller112is configured to control and operate power driver114. Controller112comprises, for example, a processor, central processing unit (CPU), field-programmable gate array (FPGA) or any other circuitry that is configured to control and operate power driver114. While described as a CPU in illustrative embodiments, controller112is not limited to a CPU in these embodiments and may comprise any other circuitry that is configured to control and operate power driver114. In an example embodiment, controller112is configured to control power driver114to drive a coil TX of the power driver114to produce a magnetic field. Power driver114is configured to drive coil TX at a range of frequencies and configurations defined by wireless power standards, such as, e.g., the Wireless Power Consortium (Qi) standard, the Power Matters Alliance (PMA) standard, the Alliance for Wireless Power (A for WP, or Rezence) standard or any other wireless power standards.

Receiver120is configured to receive AC power transmitted from transmitter110and to supply the power to one or more loads126or other components of a destination device140. Destination device140may comprise, for example, a computing device, mobile device, mobile telephone, smart device, tablet, wearable device or any other electronic device that is configured to receive power wirelessly. In an illustrative embodiment, destination device140comprises receiver120. In other embodiments, receiver120may be separate from destination device140and connected to destination device140via a wire or other component that is configured to provide power to destination device140.

Receiver120comprises a controller122and a power rectifier124. Controller122comprises, for example, a processor, central processing unit (CPU), field-programmable gate array (FPGA) or any other circuitry that may be configured to control and operate power rectifier124. Power rectifier124includes a coil RX and is configured to rectify power received via coil RX into a power type as needed for load126. Power rectifier124is configured to rectify AC power received from coil RX into DC power which may then be supplied to load126.

As an example, when receiver120is placed in proximity to transmitter110, the magnetic field produced by coil TX of power driver114induces a current in coil RX of power rectifier124. The induced current causes AC power130to be inductively transmitted from power driver114to power rectifier124. Power rectifier124receives AC power130and converts AC power130into DC power132. DC power132is then provided by power rectifier124to load126. Load126may comprise, for example, a battery charger that is configured to charge a battery of the destination device140, a DC-DC converter that is configured to supply power to a processor, a display, or other electronic components of the destination device140, or any other load of the destination device140.

Transmitter110and receiver120are also configured to exchange information or data, e.g., messages, via the inductive coupling of power driver114and power rectifier124. For example, before transmitter110begins transferring power to receiver120, a power contract may be agreed upon and created between receiver120and transmitter110. For example, receiver120may send communication packets or other data to transmitter110that indicate power transfer information such as, e.g., an amount of power to be transferred to receiver120, commands to increase, decrease, or maintain a power level of AC power130, commands to stop a power transfer, or other power transfer information. In another example, in response to receiver120being brought in proximity to transmitter110, e.g., close enough such that a transformer may be formed by coil TX and coil RX to facilitate power transfer, receiver120may be configured to initiate communication by sending a signal to transmitter110that requests a power transfer. In such a case, transmitter110may respond to the request by receiver120by establishing the power contract or beginning power transfer to receiver120, e.g., if the power contract is already in place.

Transmitter110and receiver120may transmit and receive communication packets, data or other information via the inductive coupling of coil TX and coil RX. As an example, communication packet sent from transmitter110to receiver120may comprise frequency shift key (FSK) signals134. FSK signals134are frequency modulated signals that represent digital data using variations in the frequency of a carrier wave. Communication packets sent from receiver120to transmitter110may comprise amplitude shift key (ASK) signals136. ASK signals136are amplitude modulated signals that represent digital data using variations in the amplitude of a carrier wave. While transmitter110is described as sending FSK signals134and receiver120is described as sending ASK signals136, in other embodiments, receiver120may alternatively send FSK signals and transmitter110may alternatively send ASK signals. Any other manner of transmitting communication packets, data or other information between transmitter110and receiver120may alternatively be used.

Referring now toFIG.2, transmitter110according to an illustrative embodiment will be described in more detail. As seen inFIG.2, controller112, e.g., a CPU, of the transmitter110communicates with an analog front-end (AFE)150of the power driver114using one or more signals such as, e.g., pulse-width modulation (PWM) signals or other signals, to control and operate power driver114to provide power or data using coil TX. As an example, controller112may be configured to supply one, two, three, four or any other number of PWM signals to AFE150for controlling and operating power driver114. For example, controller112may be configured to supply one or more of PWM signals PWM_0, PWM_1, PWM_2and PWM_3or other PWM signals to AFE150. In some embodiments, controller112may also be configured to provide a half bridge enable signal, EN_½_BRG, to AFE150that is configured to enable or disable half-bridge operation. In an illustrative embodiment, the PWM signals are not encoded by the controller112and decoded by the AFE150but instead are provided as-is to the AFE150. In other embodiments, the PWM signals may alternatively be encoded by the controller112and decoded by the AFE150.

AFE150is configured to receive the one or more of the PWM signals, e.g., PWM_0, PWM_1, PWM_2and PWM_3, other signals such as, e.g., EN_½_BRG, and power supplies116and to generate outputs signals UG_0, BST_0, LG_0, UG_1, BST_1and LG_1. Outputs signals UG_0, BST_0, and LG_0correspond to a top half-bridge of the power driver114and outputs signals UG_1, BST_1, and LG_1correspond to a bottom half-bridge of the power driver114. UG_0is connected to the gate of a metal-oxide-semiconductor field-effect transistor (MOSFET)152of power driver114and controls the activation of MOSFET152. When MOSFET152is activated, the source/drain of MOSFET152connects a bridge power supply, VBRIDGE, to an output SW_0which is connected to a first side of coil TX.

LG_0is connected to the gate of a MOSFET154of power driver114and controls the activation of MOSFET154. When MOSFET154is activated, the source/drain of MOSFET154connects SW_0to ground.

BST_0, which is connected through AFE150to one of power supplies116via a diode, for example, as shown inFIG.3, is connected to one side of a capacitor156. The other side of capacitor156is connected to SW_0such that the capacitor is charged and discharged according to the activations of UG_0and LG_0. In some embodiments, BST_0acts as a floating power supply to provide VBRIDGE+5V to power the UG_0signal.

UG_1is connected to the MOSFET158of power driver114and controls the activation of MOSFET158. When MOSFET158is activated, the source/drain of MOSFET158connects VBRIDGEto an output SW_1which is connected to a second side of coil TX via a capacitor160.

LG_1is connected to the gate of a MOSFET162of power driver114and controls the activation of MOSFET162. When MOSFET162is activated, the source/drain of MOSFET162connects SW_1to ground.

BST_1, which is connected through AFE150to one of power supplies116via a diode, for example, as shown inFIG.3, is connected to one side of a capacitor164. The other side of capacitor164is connected to SW_1such that the capacitor is charged and discharged according to the activations of UG_1and LG_1. In some embodiments, BST_1acts as a floating power supply to provide VBRIDGE+5V to power the UG_1signal.

Power driver114also comprises a capacitor166disposed between VBRIDGE and ground in parallel with the drain of MOSFET154and a capacitor168disposed between VBRIDGE and ground in parallel with the drain of MOSFET162.

AFE150also has connections to ground (GND) for each half-bridge and has connections to SW_0and SW_1for monitoring and feedback.

MOSFETS152,154,158and162and capacitors156,160,164,166and168are together configured to control outputs SW_0and SW_1to drive coil TX to generate a magnetic field according one or more of the PWM signals, e.g., PWM_0, PWM_1, PWM_2and PWM_3, received by AFE150for providing power or data inductively to another device such as, e.g., receiver120(FIG.1). While an example configuration of MOSFETs and capacitors is shown inFIG.2and the following figures, any other configuration of MOSFETs and capacitors may alternatively be utilized to drive coil TX.

Example embodiments of AFE150will now be described with reference toFIGS.3-21.

Referring now toFIG.3, an example AFE200according to an embodiment of AFE150will now be described. AFE200receives power supplies116, e.g., 5V power supplies or other voltages, and a single PWM signal PWM_0as inputs. PWM_0is fed to a dead time circuit202of the top half bridge of the AFE200. PWM_0is also inverted by an inverter204and the inverted signal PWM_0B is fed to a dead time circuit206of a bottom half bridge of the AFE200.

Dead time circuit202receives PWM_0as an input signal and is configured to delay the rising edges of corresponding output signals PWM_0_UG and PWM_0_LG according to a signal received from an automatic zero-voltage switching (ZVS) circuit208. PWM_0_LG is inverted relative to PWM_0by dead time circuit202with a delayed rising edge. PWM_0_UG feeds into a MOSFET driver210which outputs to UG_0to control the activation of MOSFET152. PWM_0_LG feeds into a MOSFET driver212which outputs to LG_0to control the activation of MOSFET154.

For example, as shown inFIG.4, the rising edge of PWM_0_UG is delayed relative to PWM_0to coincide with the end of the dead time of SW_0during the transition from low to high such that the rising edge of PWM_0_UG occurs when SW_0is high and no longer transitioning. Similarly, the rising edge of PWM_0_LG is delayed relative to the inversion of PWM_0to coincide with the end of the dead time of SW_0during the transition from high to low such that the rising edge of PWM_0_LG occurs when SW_0is low and no longer transitioning.

Dead time circuit206receives PWM_0B as an input signal and is configured to delay the rising edges of corresponding output signals PWM_0B_UG and PWM_0B_LG according to a signal received from ZVS circuit208. PWM_0B_LG is inverted relative to PWM_0B by dead time circuit206with a delayed rising edge. PWM_0B_UG feeds into a MOSFET driver214which outputs to UG_1to control the activation of MOSFET152. PWM_0B_LG feeds into a MOSFET driver216which outputs to LG_1to control the activation of MOSFET154.

For example, as shown inFIG.4, the rising edge of PWM_0B_UG is delayed relative to PWM_0B to coincide with the end of the dead time of SW_1during the transition from low to high such that the rising edge of PWM_0B_UG occurs when SW_1is high and no longer transitioning. Similarly, the rising edge of PWM_0B_LG is delayed relative to the inversion of PWM_0B to coincide with the end of the dead time of SW_1during the transition from high to low such that the rising edge of PWM_0B_LG occurs when SW_1is low and no longer transitioning.

ZVS circuit208is configured to monitor feedback from SW_0and SW_1and to indicate to dead time circuits202and206when the corresponding output, SW_0or SW_1, is high, low or transitioning. In some embodiments, controller112may alternatively control the dead time circuits202and206instead of ZVS circuit208or based on feedback from ZVS circuit208. ZVS circuit208is configured to cause dead time circuits202and206to delay the rising edges of the output signals based on a servo feed-back loop that detects specific voltages of SW_0and SW_1which fall in a region between the final voltage and the voltage clamped by the body diodes of the MOSFETs. The function of ZVS circuit208will be described in more detail below with reference toFIGS.16-21.

As shown inFIG.4, for example, PWM_0_UG and PWM_0_LG alternate between low and high with their respective rising and falling edges being spaced apart to optimize the dead times of SW_0. Similarly, PWM_0B_UG and PWM_0B_LG alternate between low and high with their respective rising and falling edges being spaced apart to optimize the dead times of SW_1.FIG.4shows a 50% duty cycle with 180-degree phase shift between SW_0and SW_1, e.g., due to the inversion of PWM_0. Any other duty cycle may alternatively be used.

While dead time circuits202and206are described as delaying the rising edges of the corresponding signals, in some embodiments, one or both of dead time circuits202and206may alternatively be utilized to delay the falling edges of the corresponding signals in some embodiments.

In some embodiments AFE200also receives EN_½_BRG from controller112. EN_½_BRG feeds into an OR gate218located prior to inverter204along with PWM_0such that, when EN_½_BRG is enabled, the bottom half-bridge of AFE200is disabled, e.g., because the output of inverter204will always be low, and SW_1will always be low as shown, for example inFIG.5. When EN_½_BRG is disabled, the bottom half-bridge of AFE200is enabled with PWM_0being inverted to PWM_0B by inverter204to drive SW_1, e.g., as shown inFIG.4.

The configuration of AFE200allows controller112to control and operate power driver114using a single PWM signal, e.g., PWM_0, for both full-bridge and half-bridge operations. The single PWM signal may be provided to AFE200from controller112using a single pin of the controller112. The single PWM signal also allows controller112to control the frequency of the power output from coil TX for FSK messaging. Full-bridge operation of power driver114is enabled by inverting the PWM signal to provide a 180-degree phase shift between SW_0and SW_1and dead time circuits202and206and ZVS208are utilized to automatically control the dead time optimization of SW_0and SW_1. The use of the EN_½_BRG signal allows controller112to enable and disable the half-bridge mode of operation independently of the single PWM signal.

Referring now toFIG.6, an example AFE300according to an embodiment of AFE150will now be described. AFE300includes similar components to AFE200where like components have similar reference numbers and are configured to operate in a similar manner. In this embodiment, AFE300receives two PWM signals, PWM_0and PWM_1, as inputs instead of a single PWM signal. PWM_0is fed to dead time circuit302of the top half bridge of the AFE300in a similar manner to AFE200. PWM_1is fed to a dead time circuit306of a bottom half bridge of the AFE300in this embodiment.

Dead time circuit302receives PWM_0as an input signal and is configured to delay the rising edges of corresponding output signals PWM_0_UG and PWM_0_LG according to a signal received from a ZVS circuit308in a similar manner to that described above for AFE200to control MOSFETs152and154of power driver114. PWM_0_LG is inverted relative to PWM_0by dead time circuit302with a delayed rising edge. PWM_0_UG feeds into a MOSFET driver310which outputs to UG_0to control the activation of MOSFET152. PWM_0_LG feeds into a MOSFET driver312which outputs to LG_0to control the activation of MOSFET154.

For example, as shown inFIG.7, the rising edge of PWM_0_UG is delayed relative to PWM_0to coincide with the end of the dead time of SW_0during the transition from low to high such that the rising edge of PWM_0_UG occurs when SW_0is high and no longer transitioning. Similarly, the rising edge of PWM_0_LG is delayed relative to the inversion of PWM_0to coincide with the end of the dead time of SW_0during the transition from high to low such that the rising edge of PWM_0_LG occurs when SW_0is low and no longer transitioning.

Dead time circuit306receives PWM_1as an input signal and is configured to delay the rising edges of corresponding output signals PWM_1_UG and PWM_1_LG according to a signal received from ZVS circuit308. PWM_1_LG is inverted relative to PWM_1by dead time circuit306with a delayed rising edge. PWM_1_UG feeds into a MOSFET driver314which outputs to UG_1to control the activation of MOSFET152. PWM_1_LG feeds into a MOSFET driver316which outputs to LG_1to control the activation of MOSFET154.

For example, as shown inFIG.7, the rising edge of PWM_1_UG is delayed relative to PWM_1to coincide with the end of the dead time of SW_1during the transition from low to high such that the rising edge of PWM_1_UG occurs when SW_1is high and no longer transitioning. Similarly, the rising edge of PWM_1_LG is delayed relative to the inversion of PWM_1to coincide with the end of the dead time of SW_1during the transition from high to low such that the rising edge of PWM_1_LG occurs when SW_1is low and no longer transitioning.

As shown inFIG.7, for example, PWM_0_UG and PWM_0_LG alternate between low and high with their respective rising and falling edges being spaced apart to optimize the dead times of SW_0. Similarly, PWM_1_UG and PWM_1_LG alternate between low and high with their respective rising and falling edges being spaced apart to optimize the dead times of SW_1.FIG.7shows a 50% duty cycle with a phase shift between SW_0and SW_1that is not limited to only 180 degrees. Any other duty cycle or phase shift may alternatively be used, e.g., by adjusting PWM_0and PWM_1respectively.

In this embodiment, controller112is configured to enable or disable each half-bridge of AFE300using PWM_0and PWM_1respectively. For example, to disable one of the top and bottom half-bridges, the corresponding PWM signal is set to low by controller112which results in the corresponding output SW_0or SW_1also being set to low with no transitioning between low and high states. For example, as shown inFIG.8, PWM_1is set to low which results in PWM_1_UG being set to low and PWM_1_UG being set to high, e.g., 5V and the corresponding output SW_1being set to low.

The configuration of AFE300allows controller112to control and operate power driver114using two PWM signals, e.g., PWM_0and PWM_1, with each PWM signal controlling one half-bridge of AFE300and both PWM signals together controlling the full-bridge operation. The two PWM signals allow controller112to control not only the frequency of the power output from coil TX for FSK messaging but to also to control the duty cycle and phase shift of the power output. Full-bridge operation of power driver114is enabled for AFE300by using both PWM signals together and dead time circuits202and206and ZVS208are utilized to automatically control the dead time optimization of SW_0and SW_1. The controller112is configured to transition between half-bridge and full-bridge operation by disabling or setting one of the PWM signals to a low value such as, e.g., 0V.

Referring now toFIG.9, an example AFE400according to an embodiment of AFE150will now be described. AFE400receives power supplies116, e.g., 5V power supplies or other voltages, and two PWM signal, PWM_0and PWM_1, as inputs. In this embodiment, PWM_0is fed to MOSFET drivers410and416to control outputs UG_0and LG_1and PWM_1is fed to MOSFET drivers412and414to control outputs UG_1and LG_0. PWM_0and PWM_1are utilized together by controller112to control each half-bridge of AFE400during full-bridge or half-bridge modes of operation. For example, in this embodiment, PWM_0is used by controller112to control the operation and activation of MOSFETs152and162while PWM_1is used by controller112to control the operation and activation of MOSFETs154and158. In this embodiment, controller112is configured to control the dead time of SW_0and SW_1via PWM_0and PWM_1.

As shown inFIG.10, for example, PWM_0and PWM_1alternate between low and high with their respective rising and falling edges being spaced apart by controller112to optimize the dead times of SW_0and SW_1.FIG.10shows a 50% duty cycle with a 180-degree phase shift between SW_0and SW_1. Any other duty cycle may alternatively be used.

In some embodiments AFE400also receives EN_½_BRG from controller112. EN_½_BRG feeds into an OR gate418disposed between PWM_0and MOSFET driver416and an OR gate420disposed between PWM_1and MOSFET driver414. In this embodiment, PWM_0is inverted before entering OR gate418and the output of OR gate418is also inverted. Similarly, PWM_1is inverted before entering OR gate420and the output of OR gate418is also inverted. When EN_½_BRG is enabled, the bottom half-bridge of AFE400is disabled, e.g., because the output of each OR gate418and420is high but gets inverted to a low signal such that both MOSFET driver414and MOSFET driver416will output low signals, for example inFIG.11. When EN_½_BRG is disabled, the bottom half-bridge of AFE400is enabled with PWM_0and PWM_1simply passing through the OR gates418and420, e.g., as shown inFIG.10.

In some embodiments, AFE400may also comprise a ZVS circuit that outputs its feedback signal to controller112instead of a dead time circuit, for example, as shown inFIG.12.

The configuration of AFE400allows controller112to control and operate power driver114using two PWM signals, e.g., PWM_0and PWM_1, for both full-bridge and half-bridge operations. The two PWM signals allow controller112to control the frequency of the power output from coil TX for FSK messaging and to control the dead times of SW_0and SW_1. The use of the EN_½_BRG signal allows controller112to enable and disable the half-bridge mode of operation independently of the PWM signals. In this embodiment, when operating in the half-bridge mode of operation, controller112is also configured to control the duty cycle of the power output by coil TX. For example, since each PWM signal independently controls one MOSFET of the active half-bridge, e.g., MOSFETs152and154of the top half-bridge, but are not needed to control the opposite MOSFETs of the other half-bridge, e.g., MOSFETS158and162of the bottom half-bridge, the PWM signals may be manipulated to control the duty cycle by controller112. It is important to note that dead time, i.e., the period of time when both PWM_0and PWM_1are low, may be controlled in a case where the duty cycles of PWM_0and PWM_1are 50% or less.

Referring now toFIG.12, an example AFE500according to an embodiment of AFE150will now be described. AFE500receives power supplies116, e.g., 5V power supplies or other voltages, and four PWM signal, PWM_0, PWM_1, PWM_2and PWM_3, as inputs. In this embodiment, PWM_0is fed to MOSFET driver510to control output UG_0, PWM_1is fed to MOSFET driver512to control output UG_1, PWM_2is fed to MOSFET driver514to control output UG_1and PWM_4is fed to MOSFET driver516to control output LG_1. PWM_0, PWM_1, PWM_2and PWM_3are utilized together by controller112to control AFE500during full-bridge or half-bridge modes of operation. For example, in this embodiment, PWM_0is used by controller112to control the operation and activation of MOSFET152, PWM_1is used by controller112to control the operation and activation of MOSFET154, PWM_2is used by controller112to control the operation and activation of MOSFET158and PWM_3is used by controller112to control the operation and activation of MOSFET162. In this embodiment, controller112is configured to control the dead time of SW_0and SW_1via PWM_0, PWM_1, PWM_2and PWM_3, e.g., using feedback from a ZVS circuit508. In other embodiments, dead time circuits such as, e.g., dead time circuits202and206(FIG.3), may alternatively be utilized to control the dead time where, for example, each PWM signal may have a corresponding dead time circuit that outputs only one of the delayed outputs.

As shown inFIG.13, PWM_0and PWM_1alternate between low and high with their respective rising and falling edges being spaced apart by controller112to optimize the dead times of SW_0. Similarly, PWM_2and PWM_3alternate between low and high with their respective rising and falling edges being spaced apart by controller112to optimize the dead times of SW_1.FIG.13shows a 50% duty cycle with a phase shift between SW_0and SW_1that is not limited to only 180 degrees. Any other duty cycle or phase shift may alternatively be used, e.g., by adjusting PWM_0, PWM_1, PWM_2and PWM_3.

In this embodiment, controller112is configured to enable or disable each half-bridge of AFE500using a combination of PWM_0and PWM_1or a combination of PWM_2and PWM_3respectively. For example, to disable one of the top and bottom half-bridges, the corresponding PWM signals are set to low and high, respectively, by controller112which results in the corresponding output SW_0or SW_1also being set to low with no transitioning between low and high states. For example, as shown inFIG.14, PWM_2is set to low and PWM_3is set to high which results in the corresponding output SW_1being set to low.

In some embodiments, AFE500also comprises a ZVS circuit508that outputs a feedback signal to controller112. ZVS circuit508operates in a similar manner to ZVS circuit208except that the output signal, e.g., ZVS FEEDBACK, is provided to controller112instead of a dead time circuit. Controller112is configured to delay the rising edges of one or more of PWM_0, PWM_1, PWM_2and PWM_3based on ZVS FEEDBACK in a similar manner to dead time circuits202and206.

The configuration of AFE500allows controller112to control and operate power driver114using four PWM signals, e.g., PWM_0, PWM_1, PWM_2and PWM_3for both full-bridge and half-bridge operations. The use of four PWM signals allows controller112to control the frequency of the power output from coil TX for FSK messaging. The use of four PWM signals also allows controller112to control the dead time of SW_0and SW_1directly, e.g., by delaying the rising edges of one or more of the PWM signals according to the ZVS FEEDBACK signal received from ZVS circuit508. Because separate PWM signals are used for each half-bridge, controller112is also configured to shift the phase of SW_1relative to SW_0when operating in full-bridge mode, e.g., by adjusting one or both of the corresponding PWM signals. In addition, the duty cycle of the power output from coil TX may be adjusted directly by controller112by adjusting the duty cycles of one or more of the four PWM signals.

Referring now toFIG.15, an example AFE600according to an embodiment of AFE150will now be described. AFE600receives power supplies116, e.g., 5V power supplies or other voltages, and one or more of PWM signals PWM_0, PWM_1, PWM_2and PWM_3as inputs.

In this embodiment, PWM_0is fed to a multiplexer (MUX)622that feeds into MOSFET driver610to control output UG_0. PWM_0also feeds into a dead time circuit602which outputs a signal such as, e.g., PWM_0_UG (FIG.3), to MUX622. Dead time circuit602also outputs a signal such as, e.g., PWM_0_LG (FIG.3), to a MUX624that feeds into MOSFET driver612to control output LG_0.

PWM_0also is fed into an inverter604and the inverted signal is fed into a MUX626that feeds into a dead time circuit606which outputs a signal, e.g., PWM_1_UG (FIG.3), to a MUX628that feeds into MOSFET driver614to control output UG_1. Dead time circuit606also outputs a signal such as, e.g., PWM_1_LG (FIG.3), to a MUX630that feeds into MOSFET driver616to control output LG_1.

PWM_1is fed into MUX624to control output LG_0, into MUX628to control output UG_1, and into dead time circuit606to control both outputs UG_1and LG_1.

AFE600is configured to control and operate coil TX in a single PWM mode, e.g., similar to AFE200, in a first dual PWM mode, e.g., similar to AFE300, in a second dual PWM mode, e.g., similar to AFE400, and in a quad PWM mode, e.g., similar to AFE500. For example, MUXs622,624,626,628and630may be configured or controllable to select a particular input according to the mode of operation for AFE600. In some embodiments, AFE600may be configured to determine which PWM signals are active and to configured MUXs622,624,626,628and630accordingly for the corresponding PWM mode of operation.

As an example, if only PWM_0is active or if AFE600is set to the single PWM mode, MUX622may be configured to use the signal output from dead time circuit602, MUX624may be configured to use the signal output from dead time circuit602, MUX626may be configured to use the signal output from inverter604, MUX628may be configured to use the signal output from dead time circuit606and MUX630may be configured to use the signal output from dead time circuit606. In the single PWM mode, AFE600functions in a similar manner to AFE200(FIG.3). In addition, half-bridge mode may be enabled setting MUX628to use an “off” signal, e.g., a low signal or 0V signal, and setting MUX630to use an “on” signal, e.g., a high signal or 5V signal.

If only PWM_0and PWM_1are active or if AFE600is set to the first dual PWM mode, MUX622may be configured to use the signal output from dead time circuit602, MUX624may be configured to use the signal output from dead time circuit602, MUX626may be configured to use the signal from PWM_1, MUX628may be configured to use the signal output from dead time circuit606and MUX630may be configured to use the signal output from dead time circuit606. In the first dual PWM mode, AFE600functions in a similar manner to AFE300(FIG.6). In addition, half-bridge mode may be enabled setting MUX628to use an “off” signal, e.g., a low signal or 0V signal, and setting MUX630to use an “on” signal, e.g., a high signal or 5V signal. Alternatively, in the first dual PWM mode, PWM_1may be set to low, e.g., 0V, to enable half-bridge mode in a similar manner to that described above for AFE300.

If only PWM_0and PWM_1are active or if AFE600is set to the second dual PWM mode, MUX622may be configured to use the signal from PWM_0, MUX624may be configured to use the signal from PWM_1, MUX628may be configured to use the signal from PWM_1and MUX630may be configured to use the signal from PWM_0. In the second dual PWM mode, AFE600functions in a similar manner to AFE400(FIG.9). In addition, half-bridge mode may be enabled setting MUX628to use an “off” signal, e.g., a low signal or 0V signal, and setting MUX630to use an “on” signal, e.g., a high signal or 5V signal.

If all four of PWM_0, PWM_1, PWM_2and PWM_3are active or if AFE600is set to the quad PWM mode, MUX622may be configured to use the signal from PWM_0, MUX624may be configured to use the signal from PWM_1, MUX628may be configured to use the signal from PWM_2and MUX630may be configured to use the signal from PWM_3. In the quad PWM mode, AFE600functions in a similar manner to AFE500(FIG.12). In addition, half-bridge mode may be enabled setting MUX628to use an “off” signal, e.g., a low signal or 0V signal, and setting MUX630to use an “on” signal, e.g., a high signal or 5V signal. Alternatively, half-bridge mode may be enabled by setting PWM_2to a low signal, e.g., 0V, and seeing PWM_3to a high signal, e.g., 5V.

When dead time circuits602and606are active, a ZVS circuit608may be utilized to optimize the dead time and set the rising edges of the outputs signals in a similar manner to ZVS circuit208. In some embodiments, ZVS circuit608may alternatively provide feedback to controller112.

The configuration of AFE600allows controller112to control and operate power driver114using any of the PWM modes mentioned above, e.g., the single PWM mode, the first dual PWM mode, the second dual PWM mode, and the quad PWM mode. For example, in some embodiments, the particular PWM mode that is used may be dependent on how many pins of controller112are available for use in controlling and operating power driver114. In some embodiments, the particular PWM mode that is used may be dependent on what functionality is needed for a specific application, e.g., frequency control, duty cycle control, phase shift control, dead time control, full-bridge and half-bridge operation, etc.

With reference now toFIGS.16-21, the function of ZVS circuits208,308,508and608will now be described.FIG.16shows three waveforms702,704and706that illustrate an example use of dead time optimization on the SW_0and SW_1signals. Waveform702illustrates an example signal without dead time optimization showing the clamping effect from the MOSFETs. As dead time is optimized, the clamping effect is reduced, e.g., as shown in waveform704, with clamping effect eventually being mitigated as seen in waveform706.

With reference now toFIG.17, the ZVS circuit is configured to activate the UG and LG MOSFETs such that the final VDS is equal to 0V. If the dead time is too short and the MOSFETs are activated too early hard switching occurs. If the dead time is too long the body diodes of the MOSFETs will conduct, causing power loss, and hard switching will also occur. In the latter case the hard switching is limited to the body diode voltage while in the former case the hard switching could be as large as the input voltage.

In some embodiments, the ZVS circuit comprises a comparator threshold that is monitored for the SW output on each rising edge. When the rising edge of the SW output exceeds the comparator threshold, the dead time delay is reduced for the next rising edge. If the rising edge of the SW output does not exceed the comparator threshold, the dead time delay is increased for the next rising edge. The magnitude of the decrease or increase may be predetermined or may be varied depending on an amount that the comparator threshold is exceeded or not exceeded. In this embodiment, the falling edge is aligned with the clock. This ZVS circuit continuously corrects the dead time delay based on feedback such that over time the dead time delay may be optimized.

In some embodiments, the dead time delay may be static and the comparator threshold may alternatively be increased when the rising edge of the SW output exceeds the comparator threshold and decreased when the rising edge of the SW output does not exceed the comparator threshold. For example, the comparator may be adjusted during a calibration process of the dead time of the SW output signals. In some embodiments, multiple comparator thresholds may be utilized to provide a range within which the dead time delay is acceptable, e.g., a minimum comparator threshold and a maximum comparator threshold. For example, if the rising edge of the SW output does not exceed the minimum comparator threshold, the dead time delay may be increased, if the rising edge of the SW output exceeds the minimum comparator threshold but does not exceed the maximum comparator threshold the dead time delay remains the same, and if the rising edge of the SW output exceeds the maximum comparator threshold the dead time delay is reduced.

By using a servo feedback loop from the SW outputs and comparing the feedback to the comparator thresholds, the ZVS circuit is able to identify where the peak of the SW outputs are located and to adjust and optimize the amount of dead time before activation of the next MOSFET accordingly.

To mitigate the effect of jitter or noise, the ZVS circuits are configured to utilize a digital delay for the dead time instead of an analog delay which is prone to having jitter. However instead of using an internal oscillator of the AFE150which may be prone to jitter or noise due to the power electronics in the integrated circuit, a digital clock of the AFE150that is frequency locked, phase locked, or both frequency and phase locked to an external clock signal provided by the controller112may instead be used by the ZVS circuits. Using such a digital clock mitigates jitter in a manner that satisfies the requirements of the QI standard FSK operations.

FIG.18shows an example scenario of a 50% duty cycle at 100% power having a 180-degree phase shift for a dual PWM mode using PWM_0and PWM_1as input signals. As seen inFIG.18, the PWM signals are latched to the clock signal and the ZVS circuit selects the dead time in internal clock ticks for activating the complementary UG and LG gate drive signals to drive the outputs LX_0and LX_1.

FIG.19shows an example scenario of a 25% duty cycle at 50% power having a 180-degree phase shift with a duty cycle operation for a dual PWM mode using PWM_0and PWM_1. As seen inFIG.19, the PWM signals are latched to the clock signal and the ZVS circuit selects the dead times in internal clock ticks for activating the complementary UG and LG gate drive signals to drive the outputs LX_0and LX_1.

FIG.20shows an example scenario of a 25% duty cycle at 25% power having a 45-degree phase shift with duty cycle and phase shift operations in a dual PWM mode using PWM_0and PWM_1. As seen inFIG.20, the PWM signals are offset in phase but latched to the clock signal and the ZVS circuit selects the dead times in internal clock ticks for activating the complementary gate drive signals UG and LG to drive the outputs LX_0and LX_1.

FIG.21shows an example scenario of a 50% duty cycle at 100% power having a 180-degree phase shift in a single PWM mode using PWM_0. As seen inFIG.21, the PWM signal is latched to the clock signal and the ZVS circuit selects the dead times in internal clock ticks for activating the complementary gate drive signals UG and LG to drive the outputs LX_0and LX_1.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The disclosed embodiments of the present invention have been presented for purposes of illustration and description but are not intended to be exhaustive or limited to the invention in the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.