Methods for fabricating semiconductor devices

Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.

FIELD OF THE INVENTION

The present invention generally relates to methods for fabricating semiconductor devices, and more particularly relates to methods for fabricating semiconductor devices using a double patterning lithography technique and to photomasks for such a technique

BACKGROUND OF THE INVENTION

There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.

High numerical aperture (NA) 193 nanometer (nm) optical projection stepper/scanner systems in combination with advanced photoresist processes now are capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include double patterning techniques (DPT) in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch. One such DPT is referred to as litho/etch/litho/etch (LELE), and involves two separate lithographic exposures each followed by an etch process. These exposures are performed using different photomask reticles, each designed to image a portion of the total pattern. However, this scheme includes an additional etch step between lithography steps which increases fabrication cost and adds complexity to process logistics as wafers are transported between lithography and etch areas of a typical fab line. Other DPT processing options include spacer lithography processing often used, for example, in the fabrication of FinFet devices. However, these processes typically introduce several additional steps into a fabrication sequence adding yet further cost and complexity to the overall device fabrication process.

DPT processes which utilize a single etch step known as litho/freeze/litho/etch (LFLE) have also been developed. In LFLE, a first pattern is imaged into a first layer of photoresist, and the resist layer then is “frozen” rendering it unaffected by a second, subsequent photoresist process. A second pattern, complementary to the first pattern, then is formed into the second resist layer. However, the resolution conventionally attainable, for example, for isolated and dense trenches using existing LFLE processes is still limited to that of the lithography process.

Accordingly, it is desirable to provide methods for fabricating semiconductor devices using DPT processes which provide improved resolution over existing DPT processes. Further, it is also desirable to provide methods for designing photomask patterns for such DPT processes. Furthermore, it is also desirable to provide photomasks for such DPT processes. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

BRIEF SUMMARY OF THE INVENTION

Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment of the invention, one method comprises the steps of providing a first pattern design having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality. The method also comprises forming a second pattern design by reversing the tonality of the first pattern design, and wherein the first polygon is converted from the first tonality to the second tonality, and wherein the second and third polygons are both converted to the first tonality. The method further comprises forming a third pattern design from the second pattern design by converting the second polygon from the first tonality to the second tonality forming a fourth pattern design from the second pattern design by converting the third polygon from the first tonality to the second tonality forming a fifth pattern design by reversing the tonality of the third pattern design, and forming a sixth pattern design by reversing the tonality of the fourth pattern design.

A method is provided for fabricating a semiconductor device in accordance with another exemplary embodiment of the invention. The method comprises providing a semiconductor substrate forming a first photoresist layer overlying the semiconductor substrate, and forming a first opening in the first photoresist layer, the first opening having a first side surface and a second side surface substantially parallel each other. The method also comprises freezing the first photoresist layer, forming a second photoresist layer on the first photoresist layer and in the first opening, and forming a second opening in the second photoresist layer, the second opening having a third side surface substantially parallel to the first and second side surfaces and positioned overlying the substrate between the first and second side surfaces, and a fourth side surface substantially parallel to the third side surface and positioned overlying the first photoresist layer.

A photomask set suitable for a double patterning lithography technique is provided. The set comprises a first photomask comprising a first surface, a first substantially opaque layer on the first surface, and a first substantially transparent polygon etched into the first substantially opaque layer, the first substantially transparent polygon having a first side and a second side substantially parallel each other. The set also comprises a second photomask comprising a second surface, a second substantially opaque layer on the second surface, and a second substantially transparent polygon etched into the second substantially opaque layer, the second substantially transparent polygon having a third side and a fourth side substantially parallel to the first and second sides, and wherein the first and second substantially transparent polygons overlap when the first and second photomasks are aligned to each other.

DETAILED DESCRIPTION OF THE INVENTION

Manufacturing of modern semiconductor devices requires high resolution DPT lithography processing methods. In accordance with one embodiment, one such method includes fabricating semiconductor devices using a DPT process which provides improved resolution over existing DPT processes, and designing pattern layouts for such a DPT process. This method involves decomposing a master pattern layout for a semiconductor device layer into two separate and complementary sub patterns for use in a DPT process. The layout of the master pattern contains isolated and/or dense features having CDs and pitches, respectively, that are difficult or impossible to resolve with an existing lithography process and tool set, while each of the sub patterns contains only resolvable isolated and/or dense features. The two sub patterns are sequentially imaged into separate layers of photoresist such that the resulting photoresist mask is open in intersecting or common regions between the two sub patterns. Accordingly, the previously unresolvable isolated and/or dense photoresist mask features are formed by the separate patterning of a combination of two sub patterns having larger, more resolvable features. Further, photomasks suitable for use with these methods are also provided.

FIGS. 1-7illustrate schematically, methods for fabricating semiconductor devices using a master pattern layout for a semiconductor device layer which has been decomposed into a pair of sub patterns, in accordance with exemplary embodiments of the invention. The sub patterns will be used in conjunction with a DPT, described more fully below, to fabricate a photoresist mask on a semiconductor substrate that will be used in the fabrication of a semiconductor device. The photoresist mask has isolated and dense features having improved resolution and smaller pitch than otherwise attainable by directly patterning the master layout using a single lithography step. While the decomposition of a master pattern layout having a particular geometry and configuration of features is illustrated, it will be appreciated that the methods depicted inFIGS. 1-7can be used to decompose other master pattern layouts having features of other geometries in any number of different configurations.

Referring toFIG. 1, in accordance with an exemplary embodiment, these methods begin by providing an original master pattern layout100. Master pattern layout100represents a two-dimensional design layout containing features pertaining to a particular layer of a semiconductor device, and is not limited with respect to dimension or to the number or shape of features contained therein. While pattern layout100may contain any number of features as required for implementing the device, for the sake of simplicity and clarity, this invention will be described in the context of a T-shaped feature104surrounded by a field108. In this example, feature104is composed of three individual rectangular polygons110,112, and114. However, those of skill in the art will appreciate that feature104may include any number of overlapping or non-overlapping polygon shapes including rectangles, trapezoids, and the like, that when composed, form the desired feature. Further, no distinction is made regarding the manner by which a designed feature is formed, such as whether the feature is drawn directly, or whether the feature is formed indirectly as a central region bounded by a plurality of other drawn features.

The design contained within pattern layout100will be ultimately transferred onto a photomask as either substantially opaque or substantially transparent features. Accordingly, the polygons used to compose features and field regions may be designated in accordance with the resultant photomask tonality. For example, design features that result in a substantially transparent mask region may be designated as “clear” or “brightfield” tone features, and are illustrated without cross-hatching inFIGS. 1-7. Conversely, design features that result in a substantially opaque mask region may be designated as “dark” or “darkfield” tone features, and are illustrated with cross-hatching inFIGS. 1-7. Accordingly, polygons110,112, and114are designated as clear or brightfield features while surrounding regions of field108are designated as dark or darkfield. The invention addresses the situation in which any or all of polygons110,112, and114has a CD that is below the resolution limit of an existing photoresist process and exposure toolset with acceptable processing latitude. For example, any or all of sides109,111, and113of polygons110,112, and114, respectively, has a dimension (as represented by double-headed arrows117,118, and119, respectively) below the threshold CD resolution limit. Accordingly, as will be described more fully below, master pattern layout100will be decomposed and divided into two separate sub patterns to be used in conjunction with a double patterning technique as a means of resolving such features.

Next, the tonality of master pattern layout100is globally reversed to form inverse master pattern120, as illustrated inFIG. 2. That is, regions formerly brightfield in master pattern layout100are transformed into darkfield, and those originally darkfield are converted to brightfield. For example, polygons110,112, and114now appear as darkfield features on a brightfield background of field108.

Inverse master pattern120then is converted into two separate complementary inverse sub patterns124and126, as illustrated inFIGS. 3-4, respectively. Referring toFIG. 3, inverse sub pattern124contains each of the elements of inverse master pattern120, and also includes polygons128and140added as darkfield polygons to supplement the CD of polygons110,112, and114. That is, a polygon128is added adjacent to a side132of polygon112, and adjacent to a side136of polygon114, and a polygon140is added adjacent to a side144of polygon110. As used herein, polygons described as adjacent each other, share a common side. Further, polygons sharing a common side are substantially parallel to each other along this side. Referring toFIG. 4, inverse sub pattern126also includes each of the elements of inverse master pattern120, and also includes additional darkfield polygons148and152to supplement the CD of polygons110,112, and114. That is, polygon148is added adjacent a side156of polygon112, and is thus substantially parallel to polygon112along side156. Polygon152is added adjacent sides160and164of polygons110and114, respectively, and is thereby substantially parallel to these sides.

Next, the tonality of inverse sub patterns124(FIG. 3) and 126(FIG. 4) are reversed to form normal sub patterns170and174, respectively, as illustrated inFIGS. 5-6. Referring toFIG. 5, normal sub pattern170includes polygons110,112,114,128, and140converted to brightfield features, while field108is converted to a darkfield region. When represented on a photomask, the combination of brightfield polygons110and140will form a clear substantially rectangular feature having a CD (as represented by double-headed arrow178) which is resolvable with an acceptable amount of processing latitude. Similarly, polygon114in combination with polygon128, and polygon112in combination with polygon128have CDs (as represented by double-headed arrows182and186, respectively) each acceptably resolvable.

Referring toFIG. 6, normal sub pattern174includes polygons110,112,114,148, and152converted to brightfield features, while field108is converted to a darkfield region. When these polygons are fabricated onto a photomask, the combination of brightfield polygons110and152will form a clear feature having a CD (as represented by double-headed arrow190) which is resolvable with acceptable processing latitude. Similarly, polygon114in combination with polygon152, and polygon112in combination with polygon148(as represented by double-headed arrows194and198, respectively) form clear features having CDs that are also acceptably resolvable. When aligned to and overlaid on each other, the intersection between normal sub patterns170and174comprises polygons110,112, and114, as polygons common to both sub patterns. The remaining polygons128,140,144, and152are contained within only one of the sub patterns. Accordingly, the intersecting polygon set, illustrated inFIG. 7as double cross-hatched regions, comprises the same polygons having the same tonality as contained within master pattern layout100.

FIGS. 8-9schematically illustrate, in cross-section, photomasks200and204fabricated using normal sub patterns170and174, respectively, in accordance with an exemplary embodiment. Photomasks200and204form an exemplary set of photomasks configured for use with a DPT lithography process, and comprise photomask blanks205and206, respectively, each made from a material substantially transparent to radiation of the exposing source wavelength such as, for example, quartz. Photomasks200and204contain normal sub patterns170and174, respectively, reproduced in any magnification such as, for example, 1×, 4×, 5×, and the like, suited for the optical lithography system to be used. Photomask200has opaque and clear features representative of normal sub pattern170, and includes polygons110and140merged together as a single clear feature208having sides209and211, and having opaque regions212representative of field108(FIG. 5) on either side thereof. In one embodiment, sides209and211are substantially parallel. Similarly, photomask204includes polygons110and152(FIG. 6) merged together as a clear feature216between opaque regions220, and having sides217and219. In another embodiment, sides217and219are substantially parallel. In a further embodiment, when photomasks200and204are in alignment with each other, sides209and211on photomask200are substantially parallel sides217and219on photomask204. Opaque regions212and220comprise a layer of a material such as, for example, chromium or chromium oxide, that is substantially opaque to radiation of the wavelength to be used for exposure.

FIGS. 10-14schematically illustrate, in cross-section, methods for fabricating a semiconductor device400including the steps of patterning a substrate224in and upon which the semiconductor device is fabricated, using photomasks200and204, in accordance with another exemplary embodiment. Referring toFIG. 10, substrate224may be any of the types commonly used in the fabrication of semiconductor devices such as silicon, germanium, a III-V material such as gallium arsenide, or another semiconductor material. Substrate224may be a bulk wafer or may be of a layered configuration such as, for example, a semiconductor-on-insulator (SOI) configuration comprising a thin layer of monocrystalline semiconductor material on an insulating layer supported by a semiconductor carrier wafer. Substrate224may optionally include without limitation one or more layers of additional materials having a surface228. These layers may also include any of the materials commonly used in semiconductor device fabrication such as, for example, semiconductor materials, dielectrics, conductive metal layers, and the like, and may include an organic or inorganic anti-reflective coating (ARC) or layer as a means of enhancing subsequent photoresist processing. While for ease of description the method described herein is illustrated by its application to the formation of semiconductor devices having isolated trenches, those of skill in the art will appreciate that the method is applicable to the fabrication of a myriad of semiconductor devices.

A photoresist layer232is applied overlying surface228. Photoresist layer232is an organic photoresist or “resist” layer sensitized to exposure from radiation of a particular wavelength or range of wavelengths. Such exposure wavelengths include, but are not limited to, 365 nanometer (nm), 248 nm, 193 nm, 157 nm, 126 nm, or 13.4 nm. Photoresist layer232may be either a positive acting or “positive tone” resist designed to be removed by a developer in regions exposed to actinic radiation, or a negative acting or “negative tone” resist designed to be removed by a developer in unexposed regions. Because this invention is directed to the formation of features on a semiconductor device of either positive or negative tone, the photoresist tonality is selected so as to complement the mask design and result in the formation of features having the desired tone in the resist film. Accordingly, to fabricate a trench using the exemplary clear features208and216of photomasks200and204, respectively, a positive tone resist is selected and herein described. However, those of skill in the art will appreciate that these methods may be applied with equal result in the formation of a trench in a photoresist layer using a negative tone resist in conjunction with photomasks having a reversed tonality. Layout patterns for such photomasks can be prepared using methods previously described and illustrated inFIGS. 1-7by globally reversing the tone of the pattern at each step. Photoresist layer232is applied using a suitable technique, such as, most commonly, by using a spin-coating and post application bake (PAB) process sequence.

Next, photomask200is used to selectively expose layer232, as illustrated inFIG. 11. Photomask200is used in conjunction with an optical exposure system, such as, for example, a step-and-scan lithography system having a lens assembly configured to project and focus normal sub pattern170onto layer232. Exposing radiation (as represented by arrows236) passes through clear feature208, and is substantially blocked from reaching photoresist layer232by opaque regions212. Following exposure, layer232is developed to form an opening240having side surfaces242and246. In one embodiment, side surfaces242and246are substantially parallel to each other. Resist development typically includes immersion of photoresist layer232in a suitable developing solution and, depending upon the type of resist used, also commonly includes a post exposure bake (PEB) step performed prior to developer immersion.

Photoresist layer232is stabilized or “frozen” (as represented by dash lines244) using a suitable freezing process, as illustrated inFIG. 12. The term “freezing” as used herein in the context of a photoresist, means that the resist layer has been chemically and structurally stabilized for use in conjunction with a subsequent photoresist patterning process. Accordingly, a frozen resist layer substantially maintains pattern fidelity for use as an etch mask when subjected to the coating, baking, exposure, and development steps associated with the second resist layer. The freezing of layer232may be performed using a suitable process including but not limited to exposure to heat and/or ultraviolet (UV) radiation (as represented by lines243), ion bombardment, electron bombardment, and the like, in a manner that cross-links polymers within the resist. Alternatively, freezing may be done through a chemical treatment which stabilizes the resist to the above processes. Next, a photoresist layer248is applied as a blanket coating overlying photoresist layer232and within opening240. Layer248may be applied as previously described with reference to layer232, and illustrated with respect toFIG. 11.

Photoresist layer248is selectively exposed to radiation (as represented by arrows252) through photomask204, as illustrated inFIG. 13. Exposing radiation passes through a clear feature216to expose layer248, but is blocked from reaching layer248by opaque features220. Layer248optionally is subjected to a post-exposure bake, and is developed following exposure as previously described with reference to layer232, and illustrated with respect toFIG. 11. The exposure and developing processes result in an opening256in photoresist layer248having a side surface260positioned overlying substrate surface228and a side surface264positioned overlying photoresist layer232. In one embodiment, side surfaces260and264are substantially parallel each other and to side surfaces242and246. Because photoresist layer232was frozen as described above, side surface242remains substantially unaltered during the patterning of photoresist layer248and, in conjunction with side surface260, form an opening268which provides access to surface228. Accordingly, because opening268constitutes the intersection of openings240and256, it has a CD (as represented by double headed arrows272) less than that of either opening, and substantially identical to the original desired opening as represented by polygon110illustrated inFIG. 1. A trench280then may be etched into surface228through opening268using the composite of patterned layers232and248as an etch mask via a suitable wet or dry etch process, as illustrated inFIG. 14.

FIGS. 15-16schematically illustrate, in cross-section, methods for forming a photoresist mask overlying surface228comprising a dense trench pattern, in accordance with another exemplary embodiment. This method begins with steps that are illustrated inFIGS. 10-12, and previously described. Following a blanket application, photoresist layer248is patterned using a photomask284, as illustrated inFIG. 15. Photomask284contains a dense line/space pattern which includes substantially opaque features288adjacent substantially transparent features292and296. Layer248is exposed (as represented by arrows300) through photomask284, and is subsequently developed as previously described to form openings304and308. Opening304has a side surface312positioned overlying layer232and a side surface316positioned overlying substrate surface228. In one embodiment, side surfaces312and316are substantially parallel. In another embodiment, side surfaces312and316are substantially parallel to each other and to side surfaces242and246. Opening308has a side surface320positioned overlying layer232and a side surface324positioned overlying substrate surface228. As described above, side surface242is frozen and as such is substantially unaffected by the processing of photoresist layer248and, in conjunction with side surface316, forms a photoresist mask opening328that exposes surface228. Similarly, a photoresist mask opening332that exposes surface228is bounded by side surface246of photoresist layer232in conjunction with side surface324of photoresist layer248. Photoresist mask openings328and332are separated by resist line336formed overlying surface228comprising photoresist layer248. Accordingly, because each of photoresist mask openings328and332is formed by the intersection of two larger resist openings, the resulting pitch (as represented by double headed arrows340) of photoresist mask openings328and332is less than the pitch (measured at 1×, and as represented by double headed arrows344) of features used to form them in photomask284. Next, substrate224may be suitably etched through photoresist mask openings328and332to form trenches348and350, respectively, as illustrated inFIG. 16.

Accordingly, methods have been provided for fabricating a semiconductor device including the steps of forming a photoresist mask pattern having enhanced resolution and pitch of isolated and dense features, respectively. These methods include a process for decomposing a single master pattern layout that contains potentially unresolvable isolated or dense features into a pair of sub patterns containing only larger, more resolvable features. The sub patterns are imaged onto two separate photomasks and used with an LFLE-type DPT process to form the final photoresist mask. In addition to isolated features, these methods may be used to enhance the resolution of features having other shapes composed of isolated segments such as L-shaped, T-shaped, or U-shaped designs, and the like. Methodologies related to both pattern generation and photoresist processing are compatible with either a positive or negative tone photoresist process by adjusting the tone of pattern layouts and photomasks appropriately. Accordingly, these methods may be used to further extend the resolution limits of the lithography tool set and photoresist processes with which they are used.