Trench poly ESD formation for trench MOS and SGT

A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P-N-P or N-P-N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.

FIELD OF THE INVENTION

This invention relates generally to the cell structure and device configuration of semiconductor devices. More particularly, this invention relates to an improved configuration for manufacturing an electrostatic discharge (ESD) protection circuit integrated with a semiconductor power device with reduced number of masks for Trench metal-oxide-semiconductor filed effect transistor (MOSFET) and Shield Gate Trench (SGT) MOSFET.

BACKGROUND OF THE INVENTION

Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. ESD is a serious issue in solid state electronics, such as integrated circuits (IC) and power transistors made from semiconductor materials such as silicon and insulating materials such as silicon dioxide. Either of these materials can suffer permanent damage when subjected to high voltages; as a result, there are now a number of antistatic devices that help prevent static build up.

On-chip ESD protection circuits with various diode structures have also been developed. With the shallower junction, much thinner gate oxide, salicide (self-aligned silicided) diffusion, Cu inter-connection and LLD (Light-Doped Drain) structure used on the MOSFET devices, ESD issue has become a main reliability concern of CMOS integrated circuits in sub-quarter-micron CMOS technology. To sustain a reasonable ESD stress for safe mass production, on-chip ESD protection circuits have to be added into the IC products.

Conventional power MOSFET devices with ESD protection circuits have also been developed. The ESD protection circuit diverts the ESD safely away from the rest of the MOSFET device. Conventional power MOSFET devices with ESD protection circuits generally have a layout and layer structures that require application of seven masks in typical manufacturing processes. These seven masks include a trench mask, an ESD mask, a body mask, a source mask, a contact mask, a metal mask and a passivation mask. With the seven masks required in the manufacturing processes, the processing steps are more complicated and time consuming In addition, the conventional method involves forming an additional poly layer above the silicon surface. Therefore, it may require additional poly deposition and two additional masks to pattern and form P-N junctions for the ESD structure. This adds cost and time in terms of extra masks and extra layers and extra steps. In addition, lithography machines and photoresists are expensive. The ESD protection circuit diverts the ESD safely away from the rest of the MOSFET device.

It is within this context that embodiments of the present invention arise.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Embodiments of the present invention use the existing process flow for trench MOS and form electrostatic discharge (ESD) protection circuits inside the trench polysilicon (poly). Therefore, the ESD circuits are able to form without adding any extra mask layers. Such ESD can be formed for both SGT and normal trench MOSFET (i.e. a trench MOSFET without a shield electrode).

A fabrication process of the SGT trench MOSFET with integrated ESD circuit using only four masks is depicted inFIGS. 1A to 1L, and FIGS.1A′ to1L′. By way of example, and not by way of limitation, as shown inFIG. 1A, semiconductor substrate102(e.g., an N type silicon bottom substrate layer with a less heavily doped N-type epitaxial (epi) layer grown on it) can be used to provide a drain of the device (e.g., for an N-channel MOSFET). It is noted that in alternative implementations, the substrate102could be a P type substrate with a less heavily doped P-type epitaxial layer grown on it (e.g., for a P-channel MOSFET). A hard mask layer105can be formed on top of the substrate102. The hard mask layer105can be formed, for example, by forming a thin oxide layer104on the substrate102by deposition or thermal oxidation following by a nitride layer106on top of the thin oxide layer104. FIG.1A′ shows the same structure asFIG. 1A, but is in a different portion of the semiconductor die. A photo resist (PR) layer108is then applied on top of the nitride layer106and patterned using a first mask, which is a trench mask. The residual PR layer108define ESD trench mask openings110in the ESD region and active gate trench mask openings112in the active region as shown inFIGS. 1B, and1B′ respectively.

Next, a hard mask (HM) etch is performed to etch away exposed portions of the hard mask105(e.g., nitride layer106and oxide layer104) to expose the semiconductor substrate102surface at the mask openings at110and112. The remaining PR layer108is then removed, as shown inFIGS. 1C,1C′. The remaining portions of oxide layer104and nitride layer106act as a hard mask for subsequent steps.

InFIGS. 1D,1D′, a layer of etch-resistant material (e.g., oxide or nitride) is deposited and anisotropically etched back along the horizontal surface. The term “etch-resistant” is used here to indicate that this material can be etched differentially, or more slowly, with respect to other materials like substrate102. In some embodiments, the thickness of the insulating layer can be approximately 2200 Å. Etch-resistant insulating spacers114(sometimes referred to herein as hard mask spacers) are thus formed along the walls of the hard mask openings110,112after blanket anisotropic etch back. The etch-resistant material that forms the spacers114is resistant to a process that etches the material of the substrate102.

Next, a blanket etch step is performed on the substrate102to form the ESD trench116and active trenches118with the ESD trenches116wider than the active trenches118as shown inFIGS. 1E,1E′. Typically, the width of the ESD trenches is approximately two times larger than the width of the active trenches. The etch-resistant spacers114allow for a self-aligned etching step that does not require additional mask. As will be shown later in the process, the spacers114preserve a spacing from the original hard mask layers104and106so that a self-aligned source/body contact trench can be formed. A wider trench opening results in a deeper trench than a narrower trench opening would have due to the nature of the silicon etch loading factor. For example, since the ESD trench opening110is wider than active gate trench opening112, the resulting ESD trench116is etched deeper than the active gate trench118during the blanket etch step, as shown inFIGS. 1E,1E′.

InFIGS. 1F,1F′, an insulator liner120(e.g., an oxide) is deposited or thermally grown on the sidewalls and the bottom of the trenches116,118. If deposited, the insulator liner120may also be formed on top of the nitride layer106. The liner120is thicker than a gate insulator that will be formed later in the process. In some embodiments, a sacrificial oxide layer of approximately 500 Å may optionally be grown and removed to improve the silicon surface.

By way of example, a layer of oxide of approximately 250 Å is grown, followed by forming a layer of high temperature oxide (HTO) of approximately 900 Å. For a higher voltage device, the oxide liner120may be thicker e.g. 1000 to 5000 Å.

Semiconducting material122, such as un-doped polysilicon, can be deposited, as shown inFIGS. 1G,1G′. In some embodiments, the thickness of the conductive material is less than half the trench width of the ESD trenches116, e.g., approximately 4000 Å to 10000 Å. The thickness of the material122may be selected to be less than half the width of the ESD trenches, but more than half the width of the active device trenches. The semiconducting material122completely fills the active device trenches118but only partially fills (i.e., lines) the ESD trenches116. This layer of material is sometimes referred to as source poly, shield poly, or poly1.

An ESD vertical dopant implant is performed to form a first part of the P-N-P (or N-P-N) junction for the ESD protection circuit. The doping is light and of a first conductivity type. The type of doping depends on whether the device is a P-channel or N-channel. A typical N-channel device can be doped, e.g., with Boron. A typical P-channel device can be doped, e.g., with Phosphorous. As shown inFIGS. 1G,1G′, because of the gap in the poly122in the ESD trenches116, there is doping124at the bottom in the center of the trenches. Doping of portions125of the semiconductor122at the bottom of the trench is a unique structural feature. Because the conductive material122completely fills the active trenches118, the doping only implants dopants124in the poly at the top of the active devices trenches118. Then an annealing process is carried out to drive in and diffuse the dopants.

As shown inFIGS. 1H,1H′, a dielectric material126, such as oxide, is deposited into the gaps in the ESD trenches116and active trenches118and then etched back. The dielectric material at least partially fills the gap between the polysilicon122lining the sides of the ESD trenches116and protects the doped portion125underneath the dielectric material126. The dielectric material is etched away elsewhere on the die. The dielectric material can be oxide, nitride, or combination.

The semiconductive material122containing the dopants124at the top of the substrate102is then subject to a blanket etch. Such that only the lower portions of the conductive material/poly122within the trenches remain. The only doped portions125of the poly layer122to remain are located underneath the dielectric126in the ESD trenches116. The semiconductive material122is etched back to a predetermined depth in both ESD trenches116and active trenches118, as shown inFIGS. 1I,1I′. The material122is etched all the way down to the level of the typical trench MOS bottom poly, i.e., down to the top of a shield electrode. In this embodiment, poly1may be etched down to about 1.4 micron below the top surface of the substrate.

After the conductive material122has been etched down to the predetermined depth, a second ESD vertical implant of dopants128(source like implant) is then performed. The dopants128are of a second conductivity type, which is opposite to the first conductivity type dopants124, with higher dose and lower energy than the first conductivity type dopants124implant. Then an annealing process can be carried out to drive in the dopants as shown inFIGS. 1J,1J′. The dopants128make the semiconductive material in the active device trenches conductive so that it forms a shield. The same dopants also provide the other type of doping needed to form a P-N-P (or N-P-N) junction.

An insulating material130(e.g., an oxide) may then be deposited into the ESD trenches116and the active device trenches118with a predetermined thickness using high-density-plasma (HDP) deposition. The oxide layer130is etched or polished back until the top surface of the oxide130is even with the nitride106surface, which serves as an etch stop.

At this point, a layer of photo resist134is then spun on the surface of the structure and a second mask is applied (not shown). The second mask, referred to herein as a P-cover mask, covers the ESD region to protect the ESD region during subsequent processing to finish the active devices as shown inFIG. 1K. A portion of the oxide130not protected by the second mask will be removed by HDP wet etching. Mask overlap and wet etch undercut together help determine the final profile if forming an asymmetric oxide trench like that described in U.S. application Ser. No. 12/583,192 filed on Aug. 14, 2009. Thus, the distance of the photoresist cover extending into the active region in part determines in part how much oxide will be removed by wet etching undercut. Other factors include etch time and the thickness of the oxide layers.

An anisotropic etch (e.g., a wet etch) of the insulating material130may then be performed. If an asymmetric oxide trench is not required a dry etch may be used instead. Some insulating material130in areas unmasked by the photoresist is removed, such that the remaining insulating material130is held at a desired height. Some insulating material130near the edges of the photoresist is also removed. The amount of insulating material130that is etched can be controlled by adjusting the position of edge of the photoresist layer and the etch time. Extending the edge further into the active region would result in less insulating material130being etched, and pulling the edge away from the active region would have the opposite effect. The amount of insulating material etched away can vary in different embodiments. The insulating material130remaining above the doped material128in the active trenches, e.g., oxide layer132, is referred to as the inter-electrode dielectric (IED) or inter-poly dielectric (IPD). The inter-electrode dielectric can range from about one hundred angstroms to about ten thousand angstroms in thickness.

The PR is then removed, and a layer of gate insulator136(e.g., gate oxide) is deposited or thermally grown. In some embodiments, the added gate insulator136can be an oxide layer approximately 450 Å thick. Thus, in FIG.1K′, gate insulators136are formed on the exposed trench walls of the active device trenches.

Another conductive material (e.g., polysilicon) deposition and etch back can then be performed, as seen in FIG.1K′. By way of example, and not by way of limitation, approximately 8000 Å to 12000 Å of polysilicon can be deposited in various trenches. The deposited poly can then be etched back, forming gate electrode/poly structures, as indicated at138. In the example shown, the gate poly surface can be recessed approximately 500-1000 Å below the top of the semiconductor substrate.

As shown inFIGS. 1L,1L′, exposed nitride spacers in the active gate trenches as well as other exposed nitride material can be removed through a wet etch process. A body implant can then take place, e.g., by bombarding the partially completed device with dopant ions. The ions may be implanted at an angle. In active areas unprotected by nitride, the implant forms body regions. In some embodiments, Boron ions with a dosage level of approximately 1.8×1013ions/cm2at 60 KeV˜180 KeV are used for an N-channel device. Other types of ions can be used. For example, Phosphorous or Arsenic ions can be used to form the body regions for P-channel devices. Then, source implant takes place (e.g. with a zero tilt angle (i.e., at normal incidence)). The device is again bombarded with dopant ions. In some embodiments, Arsenic ions (e.g. for N-channel device) with a dosage level of 4×1015ions/cm2at 40 KeV˜80 KeV are used to form the source. Source regions are formed within body regions. By way of example, a body diffusion step may be performed before the source implant and a source diffusion may then be performed after the source implant. No additional mask is required to implant the body and the source of the device. The body and source implants can be performed as self-aligned blanket implants.

Insulating material (e.g., oxide) may then be deposited to fill in the trench openings over the gate poly regions. In some embodiments, a chemical vapor deposition (CVD) process is used to deposit Low Temperature Oxide (LTO) and Borophosphosilicate Glass (BPSG) to a thickness of approximately 5000 Å. Next, the insulating material may be etched back through a dry etch process where the oxide is etched down and stopped by endpoint etch to surface of the substrate's surface.

Source/body contact trenches are then formed in the active regions for contact to the source and body regions. Exposed silicon areas are etched, while areas protected by oxide and/or nitride are not etched. Since the etching process does not require an additional mask, it is referred to as a self-aligned contact process. The self-aligned nature of the active cell contact trenches is made possible because the nitride spacers formed near the beginning of the process preserved the hard mask spacing.

An implant with dopants of opposite conductivity type to the substrate102may optionally be performed at the bottom of the source/body contact trenches for a better body contact. Barrier metal such as Ti and TiN can be deposited, followed, e.g., by rapid thermal processing (RTP) to form Ti silicide near the contact region. The thicknesses of Ti and TiN used in some embodiments can be 300 Å and 1000 Å, respectively. A metal, such as Tungsten (W), can then be blanket deposited to fill the contact trenches. In some embodiments about 4000 Å to 6000 Å of W may be deposited. The deposited metal can be etched back up to the oxide surface to form individual conductive plugs140.

A poly pick up mask, the third PR mask, is applied at the ESD region to form the contact trenches for contact to the P-N-P (or N-P-N) junction. The exposed oxide is etched and the mask is then removed. During this step, contact trenches to contact the shield electrode, and the gate electrode may also be formed in other regions of the device (not shown).

A fourth PR mask can be used to form a source metal region and a gate metal region. Specifically, as shown inFIGS. 1L,1L′, a metal layer142such as Aluminum-Copper (AlCu) can be deposited over the partially completed device. By way of example, and not by way of limitation, the metal layer can be about 3 μm to about 6 μm thick. A photoresist may be formed on the metal layer142and patterned to form a metal mask. After the resist is developed, the metal layer142may be etched through openings in the metal mask to separate the metal layer142into source and gate metal regions. After residual photoresist is removed, the metal142can be annealed. In some embodiments, the metal may be annealed at 450° C. for 30 minutes.FIGS. 1L,1L′ are cross sectional diagrams illustrating an example of a completed SGT MOSFET with an integrated ESD structure. The metal mask not only separates source and gate metals but can also perform a function to link to the ESD structure. For example, the metal layer portion above one end of the ESD protection structure may be connected to the source metal, and the metal layer portion above the other end of the ESD protection structure may be connected to the gate metal. Thus the ESD trench provides a P-N-P (or N-P-N) junction protection structure between the source and the gate of the device. In case of an ESD event, the excess current and voltage may be diverted between source and gate metal through the ESD protection structure, thus safely bypassing the active area of the device.

Embodiments of the present can be implemented with other types of trench MOSFETs. For example,FIG. 2AtoFIG. 2J, and FIG.2A′ to FIG.2J′ illustrate a process for fabricating a normal trench MOSFET with an integrated ESD using four masks. As shown inFIG. 2A, a semiconductor substrate102(e.g., an N type silicon bottom substrate layer with a less heavily doped N-type epi layer grown on it (for N-channel devices)) is used as the drain of the device. FIG.2A′ shows the same structure asFIG. 2A, but is in a different portion of the semiconductor die. A hard mask can optionally be formed on top of the substrate202to help etch the trenches in the following step. A photo resist (PR) layer204is then applied on top of the substrate202and patterned using a first mask, which is a trench mask.

Next, a semiconductor etch is performed to etch away exposed portions of the semiconductor substrate202surface to form the ESD trench206and active trenches208with the ESD trenches206wider than the active trenches208as shown inFIGS. 2B,2B′ respectively. (If a hard mask was employed a hard mask (HM) etch would first be performed to form openings in the hard mask layer). A wider trench opening results in a deeper trench than a narrower trench opening due to the nature of the silicon etch loading factor. For example, since ESD trench206is wider than active gate trench208, the resulting ESD trench206is deeper than active gate trench208during the etch step, as shown inFIGS. 2B,2B′.

InFIGS. 2C,2C′, gate insulator210is deposited or thermally grown on the sidewalls and the bottom of the trenches206,208. Conductive or semiconductor material212, such as undoped polysilicon, can be deposited, as shown inFIGS. 2D,2D′. The thickness of the conductive material212is less than half the trench width of the ESD trenches206, but greater than half the width of the active trenches208, e.g., approximately 4000 Å to 10,000 Å, which completely fills the active device trenches208but only partial fills the ESD trenches206. Since the material212only lines the sidewalls and bottom of ESD trench206, a gap215remains in the center of the trench, between portions of the conductive material212.

ESD vertical implant is performed to form a first part of the P-N-P (or N-P-N) junction. The doping is light and of a first conductivity type. The type of doping depends on whether the device is a P-channel or N-channel. At this step, an N-channel device is doped with Boron. A P-channel device is doped with Phosphorous. As shown inFIGS. 2D,2D′, because of the gap in the poly in the ESD trenches206, there is a doped portion214formed at the bottom of the trenches. The doping of the material212at bottom of the trench with dopants to form the doped portion214is believed to be a unique structural feature. Because the conductive or semiconductor material212completely fills the active trenches208, the dopants214are only implanted at the top portions of the poly above the active device trenches208.

As shown inFIGS. 2E,2E′, insulating material216(e.g., oxide) is deposited and then etched back. This leaves insulating material216at least partially filling the gaps215in ESD trenches206.

The conductive material212at the top of the substrate, including doped poly214at the top of the substrate is etched as shown inFIGS. 2F,2F′. The conductive material212may be etched (or planarized) with an endpoint above the top surface of the substrate. Then an annealing process is carried out to drive in the dopants of the doped poly214resulting in extended doped portions215at the bottom of the ESD trenches206as shown inFIG. 2G,2G′.

A second ESD vertical implant (same conductivity type as source) is performed to dope upper portions220of the material212in the ESD trenches. The doped portions220are doped with dopants of a second conductivity type, which is opposite to the first conductivity type of first implanted dopants214, and the implantation is performed with high dose and low energy as shown inFIGS. 2H,2H′. Then an annealing process is carried out to drive in the dopants resulting in extended doped portions222as shown inFIGS. 2I,2I′. In this embodiment the annealing process for doping the portions220may be longer than for the first implanted dopants214at the top of the poly. The resulting extended doped portions222provides the other type of doping needed to form the P-N-P (or N-P-N) junction with the doped portion214at the bottom the ESD trench.

A body implant can then take place, e.g., by bombarding the partially completed device with dopant ions. The ions may be implanted at an angle. In some embodiments, Boron ions with a dosage level of approximately 1.8×1013ions/cm2at 60 KeV˜180 KeV are used for an N-channel device. Other types of ions can be used. For example, Phosphorous or Arsenic ions can be used to form the body regions for P-channel devices. Then, source implant takes place (e.g. with a zero tilt angle (i.e., at normal incidence)). The device is again bombarded with dopant ions. In some embodiments, Arsenic ions with a dosage level of 4×1015ions/cm2at 40 KeV˜80 KeV are used (e.g. for an N-channel device). Source regions are formed within body regions. By way of example, a body diffusion step may be performed before the source implant and a source diffusion may then be performed after the source implant.

Source/body contact trenches (optional) may be then formed in the active regions for contact to the source and body regions. A dopant implant of a type opposite the doping of the substrate202may optionally be performed at the bottom of the contact trenches for a better body contact. Barrier metal such as Ti and TiN can be deposited, followed, e.g., by rapid thermal processing (RTP) to form Ti silicide near the contact region. The thicknesses of Ti and TiN used in some embodiments can be 300 Å and 1000 Å, respectively. Metal, such as Tungsten (W), can then be blanket deposited. The metal can be blanket deposited into the contact trenches. In some embodiments about 4000 Å to 6000 Å of W may be deposited. The deposited W can be etched back up to the oxide surface to form individual W plugs226.

Insulating material224(e.g., oxide) is deposited to cover the gate poly regions, the ESD poly regions and the substrate. In some embodiments, a chemical vapor deposition (CVD) process is used to deposit Low Temperature Oxide (LTO) and Borophosphosilicate Glass (BPSG) to a thickness of approximately 5000 Å. Next, the insulating material224is etched back through a dry etch process where the oxide is etched down and stopped by endpoint etch to surface of the substrate's surface.

Contact trenches for contact to the P-N-P (or N-P-N) junction are formed in the ESD region. A PR contact mask is applied to define gate pickups for active devices and contact trenches for the ESD structure. The exposed oxide and the silicon are etched and the mask is then removed.

A metal mask can be used to form a source metal region and a gate metal region. Specifically, as shown inFIGS. 2J,2J′, a metal layer228such as Aluminum-Copper (AlCu) can be deposited and etched through a metal mask, formed, e.g., by a patterned photoresist. By way of example, and not by way of limitation, the metal layer can be about 3 μm to about 6 μm thick. After residual photoresist is removed, the metal can be annealed. In some embodiments, the metal may be annealed at 450° C. for 30 minutes.FIGS. 2J,2J′ are cross sectional diagrams illustrating an example of a completed MOSFET with an integrated ESD structure.

For example, a metal layer portion above one end of the ESD protection structure may be connected to the source metal, and the metal layer portion above the other end of the ESD protection structure may be connected to the gate metal. Thus the ESD trench provides a P-N-P (or N-P-N) junction protection structure between the source and the gate of the device. In case of an ESD event, the excess current and voltage may be diverted between source and gate metal through the ESD protection structure, thus safely bypassing the active area of the device.

In the methods of the invention, under a given artificial thermal budget the right width for the trench can be determined to form the right ESD structure with high leakage protection. However, the depletion zone has to be wide enough for the P-N-P structure to work.

The unique feature of the PNP (or NPN) ESD structure formed by the above methods is that the PNP (or NPN) structure in the trench is formed horizontally with differently doped regions side by side across a width of the trench.

Though the paragraphs above describe an ESD structure with a trench MOSFET, the structure used to form the ESD structure can also be applied to other devices, such as an IGBT, or a non-trench MOSFET.