Thin film transistor array panel and method for manufacturing the same

A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application No. 10-2009-0088848, filed Sep. 21, 2009, the contents of which are herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

(a) Technical Field

The present description relates to a thin film transistor (TFT), and more particularly, to a TFT array panel and a manufacturing method of the same.

(b) Discussion of the Related Art

Liquid crystal displays (LCDs) are one of the most widely used flat panel displays. An LCD includes a liquid crystal (LC) layer interposed between two panels provided with field-generating electrodes. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer, which determines orientations of LC molecules in the LC layer to adjust polarization of incident light.

Commonly, LCDs include two panels respectively provided with field-generating electrodes, wherein one panel has a plurality of pixel electrodes in a matrix and the other has a common electrode covering the surface of the panel.

The LCD can display images by applying a different voltage to each pixel electrode. For this purpose, thin film transistors (TFTs), having three terminals to switch voltages applied to pixel electrodes, are connected to the pixel electrodes and gate lines. This configuration allows for the transmission of signals for controlling thin film transistors and allows for the data lines to transmit voltages applied to pixel electrodes formed on a thin film transistor (TFT) array panel.

The gate lines and data lines of the TFT array panel may include a conductive material having low resistivity such as, for example, aluminum (Al), an Al alloy, copper (Cu), a Cu alloy, silver (Ag) or a Ag alloy to reduce signal delay. However, the above low resistivity materials may have weak chemical or physical properties when they are used in a transistor so that the transistor may be ruined or an “on” current of the TFTs may be decreased, thereby degrading the image quality of an LCD.

SUMMARY

Exemplary embodiments of the present invention may provide a TFT array panel having enhanced image quality of a display.

Exemplary embodiments of the present invention provide a thin film transistor array panel including an insulating substrate, a gate line formed on the insulating substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode, a first ohmic contact layer formed on the semiconductor layer, a diffusion barrier layer containing nitrogen formed on the first ohmic contact layer, a second ohmic contact layer formed on the diffusion barrier layer, a data line crossing the gate line and including a source electrode and a drain electrode on the diffusion barrier layer, a passivation layer on the data line and a pixel electrode formed on the passivation layer and electrically connected to the drain electrode.

The semiconductor layer may have substantially the same planar pattern as the data line except a portion between the source and drain electrodes. The gate line may include copper or a copper alloy. Red, green, and blue color filters may be under the pixel electrode on the substrate. The data line may include a Cu—Mn (copper-manganese) alloy. A surface of the data line may include a Mn oxide.

Exemplary embodiments of the present invention provide a method for manufacturing a thin film transistor array panel including forming a gate line having a gate electrode on an insulating substrate. A gate insulating layer and an a-Si layer are formed. A first ohmic contact layer doped with a conductive impurity is formed. A diffusion barrier layer and a second ohmic contact layer are formed. A data line, source and drain electrodes overlapping with the second ohmic contact layer are formed. A passivation layer is formed on the data line and a pixel electrode electrically connected to the drain electrode is formed.

In the above method, the data line may include a Cu—Mn alloy and the diffusion barrier layer may include the same material as the first ohmic contact layer and nitrogen. The diffusion barrier layer may be formed through the plasma treatment. The semiconductor layer, the first ohmic contact layer, the diffusion barrier layer, the second ohmic contact layer and the data line having the source and drain electrode may be formed through a single photo exposure process.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, and regions may be exaggerated for clarity. Like numerals may refer to like elements throughout. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

A TFT array panel for an LCD according to an embodiment of the present invention will be described in detail below with reference toFIGS. 1 and 2.

FIG. 1is a layout view of a TFT array panel for an LCD according to an exemplary embodiment of the present invention andFIG. 2is a cross sectional view of the TFT array panel shown inFIG. 1taken along the line II-II′.

Referring toFIG. 1, a TFT array panel for an LCD includes a plurality of gate lines121for transmitting gate signals. The gate lines121are primarily formed in the horizontal direction. Portions of the gate lines121form a plurality of gate electrodes124. Different portions of the gate lines121, which extend in the lower direction toward a pixel electrode190, form a plurality of expansions127.

Data lines171for transmitting data voltages extend substantially in the longitudinal direction and intersect the gate lines121in a matrix arrangement. A plurality of branches of each data line171, which projects toward the drain electrodes175, forms a plurality of source electrodes173. A pair of the source electrode173and the drain electrode175is separated from each other and overlaps with a gate electrode124. A gate electrode124, a source electrode173, and a drain electrode175, along with a semiconductor layer154, form a TFT having a channel in the semiconductor layer154disposed between the source electrode173and the drain electrode175. A storage capacitor conductor177overlaps with the expansion127of the gate line121.

A pixel electrode190receiving a voltage from the TFT is connected to the drain electrode175of the TFT through a contact hole185.

A storage capacitor conductor177which is connected through a contact hole187forms a storage capacitor with the expansion127of the gate line and preserves the received voltage after the TFT is turned off. The storage capacitor conductor177may be formed with the same material as the data line171and may overlap with expansion127of the gate line.

In some exemplary embodiments of the present invention, the pixel electrode190may overlap the adjacent gate line121and the adjacent data line171to increase the aperture ratio when a passivation layer180(FIG. 2) is made from an organic material.

Referring toFIG. 2, a gate line121for transmitting gate signal and a gate electrode124are formed on an insulating substrate110.

The gate line121may comprise a conductive metal such as, for example, Al, an Al alloy, Cu, a Cu alloy, Ag, an Ag alloy, Au and an Au alloy. A gate line121may include a multi-layered film structure that may comprise a material such as Cr, Mo, Ta, Ti, and/or alloys thereof which have good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). Examples of suitable combinations of the multi-layered film structure include a Mo/Al—Nd alloy, Al—Nd alloy/Mo, Al/Ti, Ti/Cu and/or Mo/Cu.

A gate insulating layer140comprising silicon nitride (SiNx) is formed on the gate line121.

A semiconductor layer154comprising hydrogenated amorphous silicon (abbreviated as “a-Si”) is formed on the gate insulating layer140. The semiconductor layer154overlaps with the gate electrodes124.

First ohmic contact layers161and165comprising silicide or hydrogenated a-Si heavily doped with an impurity are formed on the semiconductor layer154. The first ohmic contact layers161and165are located in pairs on the semiconductor layer154. For example, the first ohmic contact layers161and165may be an a-Si doped with an n+ type impurity.

Diffusion barrier layers643and645are formed on the first ohmic contact layers161and165. The diffusion barrier layers643and645may include silicide and/or n+ hydrogenated a-Si and may further include nitrogen (N) or oxygen (O). Accordingly, the diffusion barrier layers643and645may have the same material as the first ohmic contact layers161and165and nitrogen (N) or may have the same material as the first ohmic contact layers161and165and oxygen (O). The diffusion barrier layers643and645have substantially the same planar pattern as the first ohmic contact layers161and165.

The diffusion barrier layers643and645prevent a metal particle of the source electrode173and drain electrode175from diffusing into the semiconductor layer154. The diffusion barrier layer643and645together with the ohmic contact layer may lower a contact resistance between the semiconductor layer and the source and drain electrode.

Second ohmic contact layers162and166are formed on the diffusion barrier layers643and645. The second ohmic contact layers162and166may have the same composition as the first ohmic contact layers161and165.

Edges of the semiconductor layer154, the first ohmic contact layers161and165, the diffusion barrier layers643and645, and the second ohmic contact layers162and166may be tapered to increase adhesion with an upper layer.

A data line171, a source electrode173, a drain electrode175, and a storage capacitor conductor177are formed on the second ohmic contact layers643and645and the gate insulating layer140.

The source electrode173and the drain electrode175are separated and overlap with the gate electrode124.

The gate electrode124, the source electrode173and the drain electrode175make a TFT and a channel of the TFT is formed between the source electrode173and the drain electrode175. The storage capacitor conductor177overlaps with the expansion127of the gate line121.

The data line171, a source electrode173, a drain electrode175, and a storage capacitor conductor177may comprise a copper-manganese alloy (Cu—Mn alloy), a main component of which is copper. The Cu—Mn alloy is deposited in a single layer, but after a heat, for example, an annealing process, Mn moves to a surface of the film so that the Cu—Mn alloy layer can have a stronger adhesion property and the resistivity of the Cu—Mn alloy layer is lowered. The Mn in the surface may prevent the copper from diffusing into the semiconductor layer and ohmic contact layer. The Mn in the surface may be an Mn oxide.

Center layers171b,173b,175band177bof the data line171, the source electrode173, the drain electrode175, and the storage capacitor conductor177mainly comprise copper and surface layers171a,173a,175aand177amay surround the center layers. The surface layers mainly comprise a manganese oxide layer.

The semiconductor layer154has an exposed portion between the source electrode and the drain electrode.

On the data line171, the drain electrode175and the storage capacitor conductor177, a passivation layer180is provided. The passivation layer180comprises an organic material having photosensitive properties or an inorganic material. The passivation layer180can be structured in a multiple layered way that comprising various combinations of the organic material and the inorganic material. To prevent the organic material of the passivation layer180from contacting the exposed portion of the semiconductor layer154between the source electrode173and the drain electrode175, the passivation layer180can be structured such that an insulating layer comprising SiNxor SiO2is additionally formed under the organic material layer.

In the passivation layer180, contact holes185,187, and182are formed and expose the drain electrode175, the storage capacitor conductor177, and an end portion of the data line171, respectively. The end portion of the data line171may be wider than the other portions of the data line171.

A pixel electrode190and contact assistants81and82, which may comprise IZO or ITO, are formed on the passivation layer180.

Since the pixel electrode190is physically and electrically connected with the drain electrode175and the storage capacitor conductor177through the contact holes185and187, respectively, the pixel electrode190receives the data voltage from the drain electrode175.

The contact assistants81and82are connected to the gate line121and the data line171through the contact holes181and182. The contact assistants81and82supplement adhesion between the end portion of the data line171and the gate line121and external devices, such as the driving integrated circuit, and protects them. The contact assistants81and82are formed with the same material as the pixel electrode.

The pixel electrode190, to which the data voltage is applied, generates an electric field with a common electrode (not illustrated) of the opposite substrate (not illustrated) to which a common voltage is applied, so that the liquid crystal molecules in the liquid crystal layer are rearranged.

A method of manufacturing a TFT array panel according to an exemplary embodiment of the present invention is described in detail below with reference toFIGS. 3A to 6Bas well asFIGS. 1 and 2.

FIGS. 3A,4A,5A, and6A are layout views sequentially illustrating the intermediate steps of a method of manufacturing a TFT array panel for an LCD according to an exemplary embodiment of the present invention.FIG. 3Bis a cross sectional view of the TFT array panel shown inFIG. 3Ataken along the lineFIG. 4Bis a cross sectional view of the TFT array panel shown inFIG. 4Ataken along the line IVb-IVb′ in a step following the step shown inFIG. 3B.FIG. 5Bis a cross sectional view of the TFT array panel shown inFIG. 5Ataken along the line Vb-Vb′ in a step following the step shown inFIG. 4B.FIG. 6Bis a sectional view of the TFT array panel shown inFIG. 6Ataken along the line VIb-VIb′ in a step following the step shown inFIG. 5B.

As shown inFIG. 3B, a metal layer is formed on an insulating substrate110using a method such as sputtering and is photo-etched (including photolithography and etching) to form gate line121having gate electrode124.

A gate insulating layer140, an a-Si layer150, a first impurity silicon layer160, impurity nitrogen silicon layer600and a second impurity silicon layer160-1are sequentially deposited on the gate line121. The a-Si layer150comprises intrinsic amorphous silicon. The first and second impurity silicon layer160and160-1comprise extrinsic amorphous silicon which is doped with a conductive impurity ion. The impurity nitrogen silicon layer600comprises extrinsic amorphous silicon containing nitrogen.

The gate insulating layer140comprises silicon nitride with a thickness of about 2,000 Å to about 5,000 Å.

The four layers comprising silicon layers150,160,600and160-1may be deposited in a chamber by an in-situ method. After forming the a-Si layer150, the first impurity layer160is formed by deposition while adding n-type impurities. Then, the impurity nitrogen silicon layer600is formed by introducing one or both of NH3and N2gas. And then, the second impurity layer160-1is formed by deposition while adding n-type impurities.

The impurity nitrogen silicon layer600can be formed by an ion implantation method or nitrogen plasma treatment after forming the first impurity silicon layer160. The impurity nitrogen silicon layer600can have a thickness of between 10 Å to 100 Å.

The a-Si layer150forms a channel of a TFT and the first and second impurity silicon layers160and160-1lower the contact resistance between the upper conductive layer and the lower a-Si layer. The impurity nitrogen silicon layer600prevents the conductive layer from diffusing into the a-Si layer.

Referring toFIGS. 4A and 4B, the impurity nitrogen silicon layer600, the first and second impurity silicon layers160and160-1and the a-Si layer are photo-etched to form a diffusion barrier pattern640, a impurity semiconductor patterns164and164-1, and a semiconductor layer154.

Next, as shown inFIGS. 5A and 5B, a data conductor layer is deposited on the impurity semiconductor patterns164-1by a method such as sputtering. The data conductor layer may include a Cu—Mn alloy.

A photoresist is formed on the data conductor layer and then the layer is patterned using an etch mask to form data line171, source electrode173, drain electrode175, and storage conductor177(for example, by photo-etching).

Next, portions of the diffusion barrier pattern640and the impurity semiconductor patterns164and164-1, which are not covered with the source electrode173and the drain electrode175, are removed by etching to complete the diffusion barriers643and645and first and second ohmic contact layers161and165and162and166and to expose a portion of the intrinsic semiconductor layer154.

By forming diffusion barrier layers643and645, diffusion of metal into the semiconductor layer154may be prevented. Accordingly, current leakage is minimized.

Nitrogen of the diffusion barrier layers643and islands645serve as an n-type impurity by reducing contact resistance between the data line171and the semiconductor layer154.

Referring toFIGS. 6A and 6B, a passivation layer180is deposited and covers the exposed portion of semiconductor layer154. The passivation layer may be one of an inorganic material, an organic material having a photosensitivity, or a low dielectric insulation material such as a-Si:C:O or a-Si:O:F which is formed by chemical vapor deposition method. Mn can move toward a surface of the Cu—Mn alloy layer and the Mn may form a Mn oxide (171a,173a,175aand177a) due to a heat temperature of the passivation formation process. The Mn oxide surrounds the inner (center) copper layer (171b,173b,175band177b).

The passivation layer180is then etched by photolithography to form contact holes181,182,185and187. The gate insulating layer140and the passivation layer180are etched under an etch condition having substantially the same etch ratio for both the gate insulating layer140and the passivation layer180.

When the passivation layer comprises a photosensitive material, the contact holes can be formed using photolithography.

As shown inFIGS. 1 and 2, a pixel electrode190and contact assistants81and82are formed by sputtering and photo-etching an IZO layer or an ITO layer.

A heat treatment may be applied to the substrate having the pixel electrode. By this heat treatment the Mn can move to the surface of the Cu—Mn alloy layer and the Mn can form a Mn oxide.

FIG. 7is a layout view of a TFT array panel for an LCD according to an exemplary embodiment of the present invention.FIG. 8is a cross sectional view of the TFT array panel shown inFIG. 7taken along the line VIII-VIII′.

The layer structure ofFIG. 7may be similar to that of the TFT array panel shown inFIGS. 1 and 2.

Referring toFIG. 7, the TFT array panel according to an exemplary embodiment of the present invention includes a storage electrode line131which are separated from the gate lines121and are overlapped by the drain electrode175to form a storage capacitor. The storage electrode line131is formed at the same layer as the gate line121.

The storage capacitor is implemented by overlapping the storage line131with the pixel electrode190. The storage electrode line131is supplied with a predetermined voltage such as the common voltage. The storage electrode line131may be omitted if the storage capacitance generated by the overlapping of the gate line121and the pixel electrode190is sufficient. The storage electrode line131may be formed along a boundary of the pixel to increase an aperture ratio.

Referring toFIG. 8, a gate line121having a gate electrode124is formed on an insulating substrate110. A gate insulating layer140, a semiconductor layer154, and first ohmic contact layers161and165are sequentially formed on the gate line121and gate electrode124. Diffusion barrier layers643and645are formed on the first ohmic contact layers161and165. Second ohmic contact layers162and166are sequentially formed on the diffusion barrier layers643and645.

A data line171, source electrode173and a drain electrode175are formed on the second ohmic contact layers162and166and on the gate insulating layer140. A passivation layer180is formed on the data line171, the source electrode173, and the drain electrode175. The passivation layer180has contact holes182and185. A pixel electrode190and contact assistants81and82are formed on the passivation layer180.

The data line171, the source electrode173and the drain electrode175have substantially the same planar pattern as the diffusion barrier layers643and645and the first and second ohmic contact layers161,162,165and166. The semiconductor layer154has substantially the same planar pattern as the first ohmic contact layers161and165, except for a portion between the source electrode173and the drain electrode175. The portion is exposed and not covered by the source electrode173and the drain electrode175, whereas inFIG. 7, the semiconductor layer154, the first and second ohmic contact layers, and the diffusion barrier layers are disposed under the data line171, the source electrode173and the drain electrode175.

The data line171has an end portion exposed through the contact hole182for contact with an external driving circuit. The exposed end portion of the data line171is coupled with the contact assistant82through the contact hole182. The gate line121may have such an end portion when the gate line121is coupled with external circuits.

A method of manufacturing the TFT array panel illustrated inFIGS. 7 and 8is described in detail below with reference toFIGS. 9A to 13A, as well asFIGS. 7 and 8.

FIGS. 9A,12A, and13A are layout views of the TFT array panel shown inFIGS. 7 and 8in intermediate steps of a manufacturing method according to an exemplary embodiment of the present invention.FIG. 9Bis a cross sectional view of the TFT array panel shown inFIG. 9Ataken along the line IXb-IXb′.FIG. 10is a cross sectional view of the TFT array panel in a step following the step shown inFIG. 9B.FIG. 11is a cross sectional view of the TFT array panel in a step following the step shown inFIG. 10.FIG. 12Bis a cross sectional view of the TFT array panel shown inFIG. 12Ataken along the line XIIb-XIIb′.FIG. 13Bis a cross sectional view of the TFT array panel shown inFIG. 13Ataken along the line XIIIb-XIIIb′.

As shown inFIGS. 9A and 9B, a metal layer is formed on an insulating substrate110by a method such as, for example, sputtering, and is photo-etched to form a gate line121having a gate electrode124and a storage line131. The metal layer may be formed with the same material and through the same method as described above.

As shown inFIG. 10, a gate insulating layer140and a-Si layer150, a first impurity silicon layer160, impurity nitrogen silicon layer600, second impurity silicon layer160-1are sequentially deposited on the gate line121. The a-Si layer150comprises intrinsic amorphous silicon. The first and second impurity silicon layers160and160-1comprise extrinsic amorphous silicon which is doped with conductive impurity ions. The impurity nitrogen silicon layer600comprises extrinsic amorphous silicon containing nitrogen.

The gate insulating layer140may comprise silicon nitride or silicon oxide with a thickness of about 2,000 Å to about 5,000 Å.

The four Si layers (a-Si layer150, a first impurity silicon layer160, impurity nitrogen silicon layer600and second impurity silicon layer160-1) may be deposited in a chamber by an in-situ method. After forming the a-Si layer150, the first impurity silicon layer160is formed by deposition while adding n-type impurities. Then, the impurity nitrogen layer600is formed by adding one or both of NH3and N2gas. The second impurity silicon layer160-1is formed in a manner similar to the way in which the first impurity silicon layer is formed.

The impurity nitrogen silicon layer600can be formed, for example, by an ion implantation method or nitrogen plasma treatment after forming the first impurity silicon layer160. The impurity nitrogen silicon layer600can have a thickness between 10 Å to 100 Å.

A data conductor layer is deposited on the impurity semiconductor patterns164-1by a method such as, for example, sputtering. The data conductor layer may include a Cu—Mn alloy.

A photoresist film is coated on the data conductor layer170. The photoresist film is exposed to light through an exposure mask (not shown) and is developed such that the developed photoresist has a position-dependent thickness as shown inFIG. 10. The developed photoresist includes a plurality of first to third portions. The first portion54is located on channel areas B and the second portions52are located on the data line areas A. No reference numeral is assigned to the third portions located on the remaining areas C since they have substantially zero thickness. Here, the thickness ratio of the first portion54to the second portions52is adjusted depending upon the process conditions in the subsequent process steps. The thickness of the first portion54may be equal to or less than half of the thickness of the second portions52.

The position-dependent thickness of the photoresist may be obtained by several techniques, for example, by providing translucent areas on the exposure mask as well as transparent areas and light blocking opaque areas. The translucent areas may have a slit pattern, a lattice pattern, or include one or more thin film(s) with intermediate transmittance or intermediate thickness. When using a slit pattern, the width of the slits or the distance between the slits may be smaller than the resolution of a light exposure used for the photolithography. Another example is to use reflowable photoresist. For example, once a photoresist pattern comprising a reflowable material is formed by using a normal exposure mask with transparent areas and opaque areas, it is subjected to a reflow process to flow onto areas without the photoresist, thereby forming thin portions.

Next, the photoresist film52and54and the underlying layers are etched such that the data lines171, drain electrodes175, and the underlying layers are left on the data areas A, only the intrinsic semiconductor layer is left on the channel areas B, and the gate insulating layer140is exposed on the remaining areas C (InFIGS. 12A and 12B).

A method to form such a structure will now be described. First, the exposed portions of the data conductor layer170, the first and second impurity silicon layers160and160-1, the impurity nitrogen silicon layer600and the a-Si layer150on the areas C are removed. Next, the photoresist film54on the channel portion (B) is removed. Then, the data conductor layer170, the first and second impurity silicon layers160and160-1and the impurity nitrogen silicon layer600on the area B are removed. Then, the photoresist film52on the area A is removed.

The structure may also be formed by first removing the data conductor layer170on the area C. Then, the photoresist film on the channel area B is removed. Next, the first and second impurity silicon layer160and160-1, the impurity nitrogen silicon layer600and the a-Si layer on the area C are removed. Then, the data conductor layer170on the area B is removed. Next, the photoresist film52on the area A is removed. Thereafter, the first and second impurity silicon layer160,160-1and the impurity nitrogen silicon layer600are removed.

The above two approaches for forming the structure are described below in additional detail. Referring toFIG. 11, an exposed portion of the data conductor layer170on the area C is removed. The source and drain electrode is not separated until now. Then, the exposed portions of the first and second impurity silicon layers160and160-1, the impurity nitrogen silicon layer600and the a-Si layer150on the areas C as well as the photoresist pattern54on the area B are removed. The data conductor layer170on the B is exposed. The removing of the photoresist film54on the channel portion (B) is performed at substantially the same time as the etching of the exposed portions of the first and second impurity silicon layers160and160-1, the impurity nitrogen silicon layer600and the a-Si layer150on the areas C. Alternatively, removal of the photoresist film54may be performed independently of the etching of the exposed portions of the first and second impurity silicon layers160and160-1, the impurity nitrogen silicon layer600and the a-Si layer150on the areas C. A remainder of the photoresist film54may be removed by ashing. At this time, the exposed portions of the semiconductor154may be etched to have a reduced thickness and the second portion52of the photoresist film may also be partially removed. The semiconductor layer154is then completed.

Referring toFIGS. 12A and 12B, the data conductor layer170, the first and second impurity silicon layers164and164-1and the impurity nitrogen silicon layer640on the area B are removed. Then, the photoresist film52on the area A is removed.

Accordingly, the source electrodes173and the drain electrodes175are separated from each other, and, simultaneously, the diffusion barrier layers643and645and the first and second ohmic contact layers161,162,165and166thereunder are completed.

The semiconductor layer, the first ohmic contact layer, the diffusion barrier layer, the second ohmic contact layer and the data line having the source and drain electrode are formed through a single photo exposure process.

Thereafter, as shown inFIGS. 13A and 13B, a passivation layer180is formed to cover the data line171, the drain electrode175, and the exposed portions of the semiconductor layer154, which are not covered by the source electrode173and the drain electrode175. The passivation layer180may comprise a photosensitive organic material having a good flatness characteristic, a dielectric insulating material having a low dielectric constant such as a-Si:C:O and a-Si:O:F formed by plasma enhanced chemical vapor deposition (PECVD), or an inorganic material such as silicon nitride and silicon oxide.

Mn can move toward a surface of the Cu—Mn alloy layer and the Mn may form a Mn oxide (171a,173a,175aand177a) due to the high temperature of the passivation formation process. The Mn oxide surrounds the inner (center) copper layer (171b,173b,175band177b).

Next, the passivation layer180is photo-etched to form contact holes185and182. When the passivation layer180comprises a photosensitive material, the contact holes185and182may be formed using photolithography.

Finally, as shown inFIGS. 7 and 8, a pixel electrode190and contact assistants82are formed by sputtering and photo-etching an IZO layer or an ITO layer. The pixel electrodes190and the contact assistants82are respectively connected to the drain electrodes175and an end of the data lines171through the contact holes185and182.

The substrate having the pixel electrode may undergo a heat treatment. By this heat treatment the Mn can move to the surface of the Cu—Mn alloy layer and the Mn can form a Mn oxide.

Exemplary embodiments of the present invention may provide for a thin film transistor array panel having color filters.

FIG. 14is a layout view of a TFT array panel for an LCD according to an exemplary embodiment of the present invention.FIG. 15is a sectional view of the TFT array panel shown inFIG. 14taken along the line XV-XV′. The TFT array panel for an LCD according to an exemplary embodiment of the present invention may have a similar planar view to that described in detail above. However, color filters230R,230G, and230B are formed on the passivation layer (not shown inFIG. 15, the passivation layer is under the color filter layer). The color filters230R,230G, and230B are formed on the data line171, the drain electrode175and the storage capacitor conductor177. The color filters230R,230G, and230B are formed along pixel columns which are partitioned by data lines171. The red, green, and blue color filters230R,230G, and230B are shown in turn.

The color filters230R,230G, and230B are not formed on the end portions of the gate lines121and the data lines171, which are coupled to external circuits. Two adjacent color filters230R,230G, and230B overlap each other on the data lines171. Accordingly, light leakage that may otherwise arise around a pixel area is prevented by the overlapping color filters230R,230G, and230B. All of red, green, and blue color filters230R,230G, and230B may be disposed on the data line171to overlap each other.

An interlayer insulating layer180is formed under the color filters230R,230G, and230B to prevent pigments of the color filters230R,230G, and230B from permeating into the pixel electrode190.

As described above, when the color filters230R,230G, and230B are formed on the thin film transistor array panel the opposite panel may have only a common electrode. Accordingly, the aperture ratio increases.

A method of manufacturing a TFT array panel according to an exemplary embodiment of the present invention is described in detail below with reference toFIGS. 16A to 17Bas well asFIGS. 14 and 15.

FIGS. 16A and 17Aare layout views of the TFT array panel in intermediate steps of a manufacturing method according to an exemplary embodiment of the present invention.FIG. 16Bis a cross sectional view of the TFT array panel shown inFIG. 16Ataken along the line XVIb-XVIb′.FIG. 17Bis a cross sectional view of the TFT array panel shown inFIG. 17Ataken along the line XVIIb-XVIIv′.

Referring toFIGS. 3A and 5B, a gate electrode124, a gate insulating layer140, a plurality of semiconductor layer154, first and second ohmic contact layers161,162,165and166, diffusion barrier layers643and645, and a data line171and drain electrode175are sequentially formed on the substrate110.

Next, inFIGS. 16A to 16B, organic photo-resist materials respectively containing pigments of red, green, and blue are coated and are patterned by a photo process to form color filters230R,230G, and230B. Here, a passivation layer (not shown) comprising an organic material or an inorganic material may be formed in a single or multiple layered structures under the color filters. The passivation layer comprising an inorganic insulating material such as SiNxor SiO2is formed on the data line171and drain electrode175before forming the color filters230R,230G, and230B. Openings235and237exposing the drain electrode175and the storage capacitor conductor177may be formed.

Referring toFIGS. 17A and 17B, an interlayer insulating layer180is formed by the coating of an organic insulating film having a low dielectric constant and a good flatness characteristic or by the PECVD of a low dielectric insulating material such as a-Si:C:O and a-Si:O:F having a dielectric constant.

Thereafter, the interlayer insulating layer180is photo-etched to form contact holes182,185, and187. Here, the contact holes185and187exposing the drain electrodes175and the storage capacitor conductor177are formed in the openings235and237of the color filters230R,230G, and230B.

Finally, as shown inFIGS. 14 and 15, a pixel electrode190and a contact assistant82are formed by sputtering and photo-etching an IZO layer or an ITO layer. The pixel electrode190is connected to the drain electrode175and the storage capacitor conductor177through the contact holes185and187.

While exemplary embodiments of the present invention have been described in detail with reference to the figures, various modifications and substitutions can be made thereto without departing from the spirit and scope of the present invention.