INDUCTIVE DEVICE STRUCTURE AND PROCESS METHOD

A device is described. The device includes a substrate having a first cavity. The device also includes a first redistribution layer (RDL) on sidewalls and a base of the first cavity in the substrate and on a first surface of the substrate. The device further includes a fill material in the first cavity.

BACKGROUND

Field

Aspects of the present disclosure relate to semiconductor devices and, more particularly, to a high-quality (Q) and high-density inductive device structure and process method.

Background

Wireless communications devices incorporate radio frequency (RF) modules that facilitate the communication and features users expect. As wireless systems become more prevalent and include more capabilities, the chips become more complex. Fifth generation (5G) new radio (NR) and sixth generation (6G) wireless communications devices incorporate the latest generation of electronic dies that are packed into smaller modules with smaller interconnections. Design challenges include integrating passive devices and active devices to implement RF front-end (RFFE) modules.

An RFFE module may be implemented by integrating RF filters, active devices, and surface-mount technology (SMT) devices on a laminate substrate. These RF filters, active devices, and SMT devices are conventionally arranged in a side-by-side package configuration supported by a laminate substrate. Unfortunately, these conventional side-by-side on package laminate configurations may not work well in a reduced form factor of future applications. An RFFE implementation that meets the reduced form factor of future RFFE module applications is desired.

SUMMARY

A device is described. The device includes a substrate having a first cavity. The device also includes a first redistribution layer (RDL) on sidewalls and a base of the first cavity in the substrate and on a first surface of the substrate. The device further includes a fill material in the first cavity.

A method for fabricating a device is described. The method includes forming a first cavity in a substrate. The method also includes depositing a first seed layer on sidewalls and a base of the first cavity and on a first surface of the substrate. The method further includes depositing a photoresist material on the first surface and in the first cavity in the substrate. The method also includes exposing the photoresist material on the first surface and in the first cavity in the substrate to form a first redistribution layer (RDL) mask. The method further includes depositing a first conductive material according to the first RDL mask to form a first redistribution layer (RDL) on the sidewalls and the base of the first cavity in the substrate and on the first surface of the substrate. The method also includes filling the first cavity in the substrate with a fill material.

DETAILED DESCRIPTION

As described herein, the use of the term “and/or” is intended to represent an “inclusive OR,” and the use of the term “or” is intended to represent an “exclusive OR.” As described herein, the term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” used throughout this description means “connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term “proximate” used throughout this description means “adjacent, very near, next to, or close to.” As described herein, the term “on” used throughout this description means “directly on” in some configurations, and “indirectly on” in other configurations.

Wireless communications devices incorporate radio frequency (RF) modules that facilitate the communication and features users expect. As wireless systems become more prevalent and include more capabilities, the chips become more complex. For example, mobile RF chips (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. Designing mobile RF transceivers is complicated by added circuit functions for supporting communications enhancements, such as fifth generation (5G) new radio (NR) communications systems. In particular, 5G NR wireless communications devices incorporate the latest generation of electronic dies that are packed into smaller modules with smaller interconnections. Design challenges include integrating passive devices and active devices to implement RF front-end modules (FEMs).

RF filters in mobile RF transceivers may include high performance capacitor and inductor components. For example, RF filters use various types of passive devices, such as integrated capacitors and integrated inductors. Integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. Capacitors are generally passive elements used in integrated circuits for storing an electrical charge. For example, parallel plate capacitors are often made using plates or structures that are conductive with an insulating material between the plates.

An inductor is an example of an electrical device used to temporarily store energy in a magnetic field within a wire coil according to an inductance value. This inductance value provides a measure of the ratio of voltage to the rate of change of current passing through the inductor. When the current flowing through an inductor changes, energy is temporarily stored in a magnetic field in the coil. In addition to their magnetic field storing capability, inductors are often used in alternating current (AC) electronic equipment, such as radio equipment. For example, the design of mobile RF transceivers includes the use of inductors with improved inductance density while reducing magnetic loss at millimeter wave (mmW) frequencies (e.g., frequency range two (FR2)).

A radio frequency (RF) front-end (RFFE) module may include a high performance RF filter including inductors and transformers. In practice, an RFFE module may be implemented by integrating RF filters, active devices, and surface-mount technology (SMT) devices on a laminate substrate. These RF filters, active devices, and SMT devices are conventionally arranged in a side-by-side package configuration supported by a laminate substrate. Unfortunately, this conventional side-by-side on package laminate configuration may not fit within a reduced form factor of future RF applications. That is, the conventional side-by-side on package laminate configurations may exceed the form factor of future RFFE module applications. An RFFE implementation that meets the reduced form factor specified by future RFFE module applications is desired.

In particular, a high performance RF filter is desirable for 5G/6G RFFE applications. In addition, a high-quality (Q) inductor is favorable for high performance filters. A high-density inductor is also desirable for compact filter chip design. These high-Q/compact inductors are specified for a transmit (TX) filter with high power handling capability. All above-mentioned favorable features are desirable to achieve a two-dimensional (2D) integrated passive device (IPD). A three-dimensional (3D) through glass via (TGV) process can offer a higher Q-factor and higher density inductors than the conventional 2D process. Nevertheless, the 3D TGV process involves a double-sided redistribution layer (RDL) and polyimide (PI) interlayer dielectric (ILD) processes, which are more expensive, and involve bonding/de-bonding temporary carriers and related processes when a thin TGV substrate is specified.

Various aspects of the present disclosure provide a high-quality (Q) and high-density inductive device structure. The process flow for fabrication of the inductive device structure may include wafer-level processes, such as front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term “layer” includes film and is not construed as indicating a vertical or horizontal thickness unless otherwise stated. As described, the term “substrate” may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably.

As described, the back-end-of-line (BEOL) interconnect layers may refer to the conductive interconnect layers (e.g., a first interconnect layer (MI) or metal one M1, metal two (M2), metal three (M3), metal four (M4), etc.) for electrically coupling to front-end-of-line (FEOL) active devices of an integrated circuit. The various BEOL interconnect layers are formed at corresponding BEOL interconnect layers, in which lower BEOL interconnect layers use thinner metal layers relative to upper BEOL interconnect levels. The BEOL interconnect layers may electrically couple to middle-of-line (MOL) interconnect layers, for example, to connect M1 to an oxide diffusion (OD) layer of an integrated circuit. The MOL interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of an integrated circuit. A BEOL first via (V2) may connect M2 to M3 or others of the BEOL interconnect layers. The BEOL vias may also provide a via pad (VP) to support package (or device) interconnects, such as package balls.

Some aspects of the present disclosure are directed to inductive device structures, including a redistribution layer (RDL) on a surface and in a cavity of a substrate. In some aspects of the present disclosure, the substrate is composed of a blind cavity alumina (BCA) substrate, supporting an RDL formed by depositing a thick copper layer directly built on the BCA substrate with high thermal conductivity. In these aspects of the present disclosure, the inductive device structure enables formation of an inductor having both a higher Q-factor and inductance density to support a higher power handling capability when implemented in integrated passive device (IPD) filters. According to aspects of the present disclosure, an RFFE module includes an IPD filter implemented using the inductive device structure.

In some aspects of the present disclosure, the inductive device structure supports formation of a transformer built on both sides of the cavity and having a higher coupling factor and a higher coupling efficiency. Some aspects of the present disclosure enhance the inductive device structure performance by applying a magnetic paste material and filling the cavity to increase inductance, Q-factor, and density. A single-sided process of fabricating the inductive device structure may combine a thick photoresist with a two-step photolithography scheme that offers a lower cost advantage than the conventional TGV process.

FIG.1is a schematic diagram of a radio frequency front-end (RFFE) module100employing an inductive device structure, according to aspects of the present disclosure. The RFFE module100includes power amplifiers102, duplexer/filters104, and a radio frequency (RF) switch module106. The power amplifiers102amplify signal(s) to a certain power level for transmission. The duplexer/filters104filter the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other like parameters. In addition, the RF switch module106may select certain portions of the input signals to pass on to the rest of the RFFE module100.

The radio frequency front-end (RFFE) module100also includes tuner circuitry112(e.g., first tuner circuitry112A and second tuner circuitry112B), the diplexer190, a capacitor116, an inductor118, a ground terminal115, and an antenna114. The tuner circuitry112(e.g., the first tuner circuitry112A and the second tuner circuitry112B) includes components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuitry112may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna114. The RFFE module100also includes a passive combiner108coupled to a wireless transceiver (WTR)120. The passive combiner108combines the detected power from the first tuner circuitry112A and the second tuner circuitry112B. The wireless transceiver120processes the information from the passive combiner108and provides this information to a modem130(e.g., a mobile station modem (MSM)). The modem130provides a digital signal to an application processor (AP)140.

As shown inFIG.1, the diplexer190is between the tuner component of the tuner circuitry112and the capacitor116, the inductor118, and the antenna114. The diplexer190may be placed between the antenna114and the tuner circuitry112to provide high system performance from the radio frequency front-end (RFFE) module100to a chipset including the wireless transceiver120, the modem130, and the application processor110. The diplexer190also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer190performs its frequency multiplexing functions on the input signals, the output of the diplexer190is fed to an optional inductor/capacitor (LC) network including the capacitor116and the inductor118. The LC network may provide extra impedance matching components for the antenna114, when desired. Then, a signal with the particular frequency is transmitted or received by the antenna114. Although a single capacitor and inductor are shown, multiple components are also contemplated.

FIG.2is a schematic diagram of a radio frequency integrated circuit (RFIC) chip200, having a wireless local area network (WLAN) (e.g., Wi-Fi) module150and a radio frequency front-end (RFFE) module170for a chipset210. The Wi-Fi module150includes a first diplexer162communicably coupling an antenna164to a WLAN module152. A first RF switch160communicably couples the first diplexer162to the WLAN module152. The RFFE module170includes a second diplexer190communicably coupling an antenna192to a wireless transceiver (WTR)120through a duplexer172. A second RF switch180communicably couples the second diplexer190to the duplexer172.

The WTR120and the WLAN module152of the Wi-Fi module150are coupled to a modem (mobile station modem (MSM), e.g., baseband modem)130that is powered by a power supply202through a power management integrated circuit (PMIC)140. The chipset210also includes capacitors144and148, as well as an inductor(s)146to provide signal integrity. The PMIC140, the modem130, the WTR120, and the WLAN module152each include capacitors (e.g.,142,132,122, and154) and operate according to a clock204. In addition, the inductor146couples the modem130to the PMIC140. The geometry and arrangement of the various inductor and capacitor components in the RFIC) chip200may reduce the electromagnetic coupling between the components.

The WTR120of the wireless device generally includes a mobile RF transceiver to transmit and receive data for two-way communications. The WTR120and the RFFE module170may be implemented using high performance complementary metal oxide semiconductor (CMOS) RF switch technologies to implement switch transistors of the first RF switch160and the second RF switch180. The RFFE module170may rely on these high performance CMOS RF switch technologies to implement an active die for successful operation. In practice, the active die used to implement the CMOS RF switch technology may involve integration with a passive RF filter to implement an antenna module, for example, as shown inFIG.3.

FIG.3is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module300including a semiconductor die and an integrated passive device (IPD) filter die, in accordance with aspects of the present disclosure. In this example, the RFFE module300includes a semiconductor die350and an IPD filter die320supported by a package substrate310(e.g., a laminate substrate). The semiconductor die350may be an active die having a semiconductor substrate360(e.g., an active silicon substrate) coupled to package balls302through back-end-of-line (BEOL) layers370. The BEOL layers370include multiple BEOL metallization layers (M1, M2, M3, Mn) on the semiconductor substrate360(e.g., a diced silicon wafer). A redistribution layer312is coupled to the package balls302.

The IPD filter die320includes a substrate330(e.g., a passive substrate) coupled to the package balls302through BEOL layers340. The redistribution layer312is coupled to the IPD filter die320through the package balls302. In some aspects of the present disclosure, the substrate330is composed of glass, and the IPD filter die320is a glass-substrate integrated passive device (GIPD) filter die. In practice, the RFFE module300integrates the IPD filter die320, the semiconductor die350, and surface-mount technology (SMT) devices on the package substrate310(e.g., laminate). The IPD filter die320, the semiconductor die350, and the SMT devices (not shown) are arranged in a side-by-side package configuration supported by the package substrate310. Unfortunately, this side-by-side on package substrate configuration may not fit within the reduced form factor of future RF applications. That is, the conventional side-by-side on package laminate configurations may exceed the form factor of future RFFE module applications. An RFFE implementation that meets the reduced form factor of future RFFE module applications is shown, for example, inFIGS.4A and4B.

FIGS.4A and4Bare block diagrams illustrating integrated passive devices (IPDs) formed from inductive device structures, according to aspects of the present disclosure. As shown inFIG.4A, an integrated passive device (IPD)400includes a substrate402having blind cavity and can be composed of alumina, glass, high resistivity (HR) silicon, a laminate material, or preferably substrate with high thermal conductivity (TC). In some aspects of the present disclosure, the substrate402includes a cavity410, in which an inductor420is formed on opposing sidewalls412,414and a base411of the cavity410, as well as a surface404of the substrate402. In some aspects of the present disclosure, the substrate402is composed of a blind cavity alumina (BCA) substrate, supporting a first redistribution layer (RDL) formed by depositing a thick copper (Cu) layer directly built on the BCA substrate of the substrate402and the cavity410.

As shown inFIG.4B, an IPD450includes the substrate402having the cavity410, in which an inductor460is formed, according to aspects of the present disclosure. In this example, the inductor460is also formed on the opposing sidewalls412,414and the base411of the cavity410, as well as the surface404of the substrate402. In this aspect of the present disclosure, the inductor460is also formed on opposing sidewalls416,418and extends between diagonal corners along the base411of the cavity410. In this example, the inductor460is composed of an RDL formed by depositing a copper (Cu) layer directly on the substrate402and the cavity410. This configuration of the inductor460provides a higher inductance and a higher Q-factor relative to the inductor420ofFIG.4A, which outperforms a conventional 2D inductor. The cavity410may be filled with a fill material to further improve a performance of the inductor420and the inductor460.

FIGS.5A and5Bare block diagrams further illustrating the integrated passive device (IPD)400, including the inductive device structure ofFIG.4A, according to aspects of the present disclosure.FIG.5Aillustrates the dimensions of the IPD400, including the substrate402, the cavity410in the substrate402, and the inductor420. In this example, the substrate402is shown with a thickness of approximately four-hundred (400) micrometers (microns) in which the cavity410is formed as a square, having a depth, a length, and a width of three-hundred (300) microns. In addition, the inductor420is shown having a redistribution layer (RDL) thickness of fifteen (15) microns and an RDL width of twenty (20) microns.

FIG.5Billustrates a perspective view of an IPD500including the substrate402, having the cavity410, in which the inductor420is formed. As described, the cavity410may be referred to as a blind cavity, in which a portion of the inductor420within the cavity410is occluded by the substrate402. In this example, the inductor420is a wire inductor formed by depositing an RDL of copper (Cu) within the cavity410and the surface404of the substrate402. In these aspects of the present disclosure, the inductive device structure of the IPD500enables formation of the inductor420having both a higher Q-factor and inductance density to support a higher power handling capability when implemented in a radio frequency (RF) filter. The inductive device structure of the IPD400provides a significant size reduction (e.g., 20%-30%) as well as a lower cost (e.g., 30%) relative to a conventional 2D passive on glass (POG) wire inductor.

FIGS.6A-6Dare block diagrams illustrating integrated passive devices (IPDs) formed from inductive device structures, according to aspects of the present disclosure. As shown inFIG.6A, an IPD600also includes the substrate402ofFIG.4Ahaving a first cavity410-1in which a first inductor420-1is formed, as well as a surface404of the substrate402. In addition, the substrate402includes a second cavity410-2, in which a second inductor420-2is formed. In some aspects of the present disclosure, the first inductor420-1and the second inductor420-2are also composed of a redistribution layer (RDL) (e.g., copper (Cu)) built on the surface404of the substrate402, the first cavity410-1, and the second cavity410-2. In this example, the substrate402is composed of a blind cavity alumina (BCA) substrate.

As shown inFIG.6B, an IPD650also includes the substrate402having the first cavity410-1, in which the first inductor420-1is formed, and the second cavity410-2, in which the second inductor420-2is formed, as well as the surface404of the substrate402. In this example, the first cavity410-1is filled with a first magnetic paste430-1, and the second cavity410-2is filled with a second magnetic paste430-2. In some aspects of the present disclosure, the first magnetic paste430-1and the second magnetic paste430-2are composed of magnetic paste material. The first inductor420-1and the second inductor420-2are also composed of an RDL formed by depositing a copper (Cu) layer directly built on the surface404of the substrate402as well as the first cavity410-1and the second cavity410-2.

As shown inFIG.6C, an IPD680also includes the substrate402; however, the substrate402includes a first cavity610-1and a second cavity610-2having tapered sidewalls612,614. In this example, a first inductor620-1is formed on the tapered sidewalls612,614of the first cavity610-1as well as the surface404of the substrate402. In addition, a second inductor620-2is formed on the tapered sidewalls612,614of the second cavity610-2as well as the surface404of the substrate402. In this example, the first inductor620-1and the second inductor620-2are also composed of an RDL formed by depositing a copper (Cu) layer directly on the surface404of the substrate402, the first cavity610-1, and the second cavity610-2.

As shown inFIG.6D, an IPD690also includes the substrate402, including the first cavity610-1and the second cavity610-2having tapered sidewalls612,614. In this example, the first inductor620-1is formed on the tapered sidewalls612,614of the first cavity610-1as well as the surface404of the substrate402. In addition, the second inductor620-2is formed on the tapered sidewalls612,614of the second cavity610-2as well as the surface404of the substrate402. In this example, the first cavity610-1is filled with a first magnetic paste640-1, and the second cavity610-2is filled with a second magnetic paste640-2. In some aspects of the present disclosure, the first magnetic paste640-1and the second magnetic paste640-2are composed of magnetic paste material. The first inductor620-1and the second inductor620-2are also composed of an RDL built on the surface404of the substrate402as well as the first cavity610-1and the second cavity610-2.

FIGS.7A and7Bare block diagrams illustrating integrated passive devices (IPDs) formed from inductive device structures including a transformer formed from inductors, according to aspects of the present disclosure. As shown inFIG.7A, an IPD700includes a double-sided substrate702having a first cavity710-1, in which a first inductor720-1is formed, as well as a first surface704of the double-sided substrate702. In addition, the double-sided substrate702includes a second cavity710-2, in which a second inductor720-2is formed. In some aspects of the present disclosure, the first inductor720-1and the second inductor720-2are also composed of a redistribution layer (RDL) built on the first surface704of the double-sided substrate702, the first cavity710-1, and the second cavity710-2.

As shown inFIG.7A, a second surface706of the double-sided substrate702includes a third cavity710-3, in which a third inductor720-3is formed. In addition, the double-sided substrate702includes a fourth cavity710-4, in which a fourth inductor720-4is formed. In some aspects of the present disclosure, the third inductor720-3and the fourth inductor720-4are also composed of an RDL built on the second surface706of the double-sided substrate702, the third cavity710-3, and the fourth cavity710-4.

In some aspects of the present disclosure, the double-sided substrate702includes a first via760-1(e.g., a first through alumina via (TAV)) and a second via760-2(e.g., a second TAV). In this aspect of the present disclosure, the first via760-1is coupled to the third inductor720-3to form a first portion (e.g.,770-1) of a transformer770. In addition, the second via760-2is coupled to the fourth inductor720-4to form a second portion (770-2) of the transformer770. In this example, the double-sided substrate702is composed of a double-sided, blind cavity alumina (BCA) substrate.

As shown inFIG.7B, an IPD750also includes the double-sided substrate702having the first cavity710-1, in which the first inductor720-1is formed, and the second cavity710-2, in which the second inductor720-2is formed, as well as the first surface704of the double-sided substrate702. In addition, the double-sided substrate702includes the third cavity710-3, in which the third inductor720-3is formed, and the fourth cavity710-4, in which the fourth inductor720-4is formed, as well as the second surface706of the double-sided substrate702. In this example, the first cavity710-1is filled with a first magnetic paste730-1, and the second cavity710-2is filled with a second magnetic paste730-2. The third cavity710-3is filled with a third magnetic paste730-3, and the fourth cavity710-4is filled with a fourth magnetic paste730-4. The first magnetic paste730-1, the second magnetic paste730-2, the third magnetic paste730-3, and the fourth magnetic paste730-4may be composed of magnetic paste material. The double-sided substrate702also includes the first via760-1and the second via760-2. The first via760-1is coupled to the third inductor720-3to form the first portion770-1of the transformer770. In addition, the second via760-2is also coupled to the fourth inductor720-4to form the second portion770-2of the transformer770.

FIGS.8A-8Nare block diagrams illustrating a process of fabricating the integrated passive devices (IPDs) ofFIGS.6A and6B, according to aspects of the present disclosure. As shown inFIG.8A, at step801, the substrate402is prepared for fabrication of the IPDs ofFIGS.6A and6B. In this example, the substrate402is shown as a high thermal conductivity (TC) alumina substrate.

As shown inFIG.8B, at step802, the first cavity410-1and the second cavity410-2are formed in the substrate402using, for example, an ablation laser, or other like cavity formation process. In this example, the first cavity410-1and the second cavity410-2are shown as having a rectangular shape, as opposed to the square shape of the cavity410shown inFIGS.4A and4B.

As shown inFIG.8C, at step803, a seed layer422is deposited on the surface404of the substrate402, as well as the sidewalls412,414and the base411of the first cavity410-1and the second cavity410-2. In this example, the seed layer422is deposited through a physical vapor deposition process, although other deposition processes are possible for formation of the seed layer422.

As shown inFIG.8D, at step804, a photoresist800is deposited on the seed layer422on the surface404of the substrate402, as well as the seed layer422on the sidewalls412,414and the base411of the first cavity410-1and the second cavity410-2. In some aspects of the present disclosure, the photoresist800is composed of an epoxy-based negative photoresist material, such as an SU-8 photoresist material, deposited through a spin-coating process, similar to the SU-8 photoresist that is widely used in micro-electro-mechanical system (MEMS) process.

As shown inFIG.8E, at step805A, a first step of a two-step photolithography technique is applied to the photoresist800using a first mask820. In this example, the first mask820is shown as an opaque, chromium (Cr) mask, having openings822through which the photoresist800is exposed to ultraviolet (UV) light.

As shown inFIG.8F, at step806A, cross links830are formed from exposure of the photoresist800to the UV light through the openings822of the first mask820. As shown inFIG.8H, at step807A, a post exposure and bake (PEB) process is performed and developed to strip the photoresist800. Once the photoresist800is stripped, a pattern of the cross links830is formed on the seed layer422on the surface404of the substrate402. The examples inFIG.8A-8Hare shown from the perspective of an X-X′ view shown in the integrated passive device (IPD)400ofFIG.8G. The examples inFIGS.8I-8Lare shown from the perspective of a Y-Y′ view shown in the IPD400ofFIG.8G.

As shown inFIG.8I, at step805B, a second step of the two-step photolithography technique is applied to the photoresist800using a second mask840, in which the photoresist800includes the pattern of cross links830, as shown inFIG.8F. In this example, the second mask840is also shown as an opaque, Cr mask, having openings842through which the photoresist800is exposed to UV light.

As shown inFIG.8J, at step806B, cross links850are formed from exposure of the photoresist800to the UV light through the openings842of the second mask840. As shown inFIG.8K, at step807B, the PEB process is performed and developed to strip the photoresist800. Once the photoresist800is stripped, a pattern of the cross links850is formed on the seed layer422on the surface404of the substrate402to expose a pattern of the seed layer422.

As shown inFIG.8L, at step808, a copper (Cu) redistribution layer (RDL) plating is performed on the portions of the seed layer422exposed by the patterns of the cross links830and850, shown as portions of the inductor420. As shown in FIG.8M, at step809, the patterns of the cross links830and850are removed to expose portions of the seed layer422. As shown inFIG.8N, at step810, the seed layer422is removed to expose portions of the surface404of the substrate402. The examples shown inFIGS.9A-9Jcontinue illustration of the formation process of the IPDs ofFIGS.6A and6B, as shown from the perspective of the X-X′ view shown in the IPD400ofFIG.8G.

FIGS.9A-9Jare block diagrams further illustrating the process of fabricating the integrated passive devices (IPDs) ofFIGS.6A and6B, according to aspects of the present disclosure. As shown inFIG.9A, at step907, a post exposure and bake (PEB) process is performed to strip the photoresist800ofFIG.8D. Once the photoresist800is stripped, the pattern of the cross links830is formed on the seed layer422on the surface404of the substrate402.

As shown inFIG.9B, at step908, a copper (Cu) redistribution layer (RDL) plating is performed on the portions of the seed layer422exposed by the pattern of the cross links830, shown as portions of the inductor420. As shown inFIG.9C, at step909, the pattern of the cross links830is removed to expose portions of the seed layer422. As shown inFIG.9D, at step910, the seed layer422is removed to expose portions of the surface404of the substrate402.

As shown inFIG.9E, at step911A, a first dry film fill440-1and a second dry film fill440-2are deposited in the first cavity410-1and the second cavity410-2of the substrate402. The first dry film fill440-1and second dry film fill440-2are also deposited on the first inductor420-1and the second inductor420-2, respectively, and the exposed portions of the surface404of the substrate402. In some aspects of the present disclosure, the first dry film fill440(e.g.,440-1and440-2) is composed of a polyimide (PI) with high thermal conductivity (TC) fillers (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3) nano-particle powder, etc.). In addition, via pad (VP) openings are formed in the first dry film fill440-1and second dry film fill440-2to expose a portion of the first inductor420-1and a portion of the second inductor420-2.

As shown inFIG.9F, at step912A, conductive interconnects470are formed on the exposed portions of the surface404of the substrate402. In some aspects of the present disclosure, the conductive interconnects470are composed of conductive bumps, copper pillars, C4 bumps, or other like conductive interconnects. As shown inFIG.9G, a second redistribution layer (RDL)480is deposited on the surface of the first dry film fill440(e.g.,440-1and440-2). In addition, an interlayer dielectric (ILD) layer442is deposited on the second RDL480(e.g., RDL-2).FIGS.9H-9Jfurther illustrate formation of the IPD650ofFIG.6B.

As shown inFIG.9H, at step911B, the first magnetic paste430-1and the second magnetic paste430-2are deposited in the first cavity410-1and the second cavity410-2of the substrate402. In addition, the first dry film fill440-1and second dry film fill440-2are deposited on exposed portions of the first inductor420-1, the second inductor420-2, and the exposed portions of the surface404of the substrate402. In some aspects of the present disclosure, the first magnetic paste430-1and the second magnetic paste430-2are composed of Ajinomoto magnetic paste (AMP) or other like magnetic paste material. In addition, via pad (VP) openings are formed in the first dry film fill440-1and the second dry film fill440-2to expose a portion of the first inductor420-1and a portion of the second inductor420-2.

As shown inFIG.9I, at step912B, conductive interconnects470are formed on the exposed portions of the surface404of the substrate402. In some aspects of the present disclosure, the conductive interconnects470are composed of conductive bumps, copper pillar bumps, C4 bumps, solder balls, or other like conductive interconnects. As shown inFIG.9J, a copper (Cu) redistribution layer (RDL-2)480is deposited on the surface of the first dry film fill440-1and the second dry film fill440-2. In addition, the interlayer dielectric (ILD) layer442is deposited on the RDL-2480. A process for fabricating an integrated passive device having an inductive device structure is shown inFIG.10.

FIG.10is a process flow diagram illustrating a method for fabricating an integrated passive device having an inductive device structure, according to aspects of the present disclosure. A method1000begins in block1002, in which a first cavity is formed in a substrate. For example, as shown inFIG.8B, at step802, the first cavity410-1and the second cavity410-2are formed in the substrate402using, for example, an ablation laser, or other like cavity formation process. In this example, the first cavity410-1and the second cavity410-2are shown as having a rectangular shape, as opposed to the square shape of the cavity410shown inFIGS.4A and4B.

In block1004, a first seed layer is deposited on sidewalls and a base of the first cavity and on a first surface of the substrate. For example, as shown inFIG.8C, at step803, a seed layer422is deposited on the surface404of the substrate402, as well as the sidewalls412,414and the base411of the first cavity410-1and the second cavity410-2. In this example, the seed layer422is deposited through a physical vapor deposition process, although other deposition processes are possible for formation of the seed layer422. As shown inFIG.7A, a second seed layer may be deposited on the sidewalls and the base of a second cavity (e.g.,710-3/710-4) on the second surface706of the double-sided substrate702.

Referring again toFIG.10, at block1006, a photoresist material is deposited on the first surface and in the first cavity in the substrate. For example, as shown inFIG.8D, at step804, a photoresist800is deposited on the seed layer422on the surface404of the substrate402, as well as the seed layer422on the sidewalls412,414and the base411of the first cavity410-1and the second cavity410-2. In some aspects of the present disclosure, the photoresist800is composed of an epoxy-based negative photoresist material, such as an SU-8 photoresist material, deposited through a spin-coating process, similar to the SU-8 photoresist that is widely used in micro-electro-mechanical system (MEMS) process.

At block1008, the photoresist material on the first surface and in the first cavity in the substrate is exposed to form a first redistribution layer (RDL) mask. For example, as shown inFIG.8E, at step805A, a two-step photolithography technique is applied to the photoresist800using the first mask820. As shown inFIG.8F, at step806A, the cross links830are formed from exposure of the photoresist800to the UV light through the openings822of the first mask820. As shown inFIG.8H, at step807A, the post exposure and bake (PEB) process is performed to strip the photoresist800. Once the photoresist800is stripped, a pattern of the cross links830is formed on the seed layer422on the surface404of the substrate402, which may be referred to as an RDL pattern.

At block1010, a first conductive material is deposited according to the first RDL mask to form a first RDL on the sidewalls and the base of the first cavity in the substrate and on the first surface of the substrate. For example, as shown inFIG.9B, at step908, a copper (Cu) RDL plating is performed on the portions of the seed layer422exposed by the pattern of the cross links830. As shown inFIG.9C, at step909, the pattern of the cross links830is removed to expose portions of the seed layer422. As shown inFIG.9D, at step910, the seed layer422is removed to expose portions of the surface404of the substrate402. As shown inFIG.7A, a second conductive material is deposited according to a second RDL mask for form a second RDL (e.g.,720-3/720-4) on the sidewalls and the base of a second cavity (e.g.,710-3/710-4) on the second surface706of the double-sided substrate702.

At block1012, the first cavity in the substrate is filled. For example, as shown inFIG.9E, at step911A, a first dry film fill440-1and a second dry film fill440- are deposited in the first cavity410-1and the second cavity410-2, respectively, of the substrate402. The first dry film fill440-1and the second dry film fill440-2are also deposited on the first inductor420-1, the second inductor420-2, and the exposed portions of the surface404of the substrate402. In some aspects of the present disclosure, the first dry film fill440-1and the second dry film fill440-2are composed of a polyimide (PI) with high thermal conductivity (TC) fillers (e.g., AlN, Al2O3 nano-particle powder, etc.). In addition, via pad (VP) openings are formed in the first dry film fill440-1and the second dry film fill440-2to expose a portion of the first inductor420-1and a portion of the second inductor420-2.

Some aspects of the present disclosure are directed to inductive device structures, including a redistribution layer (RDL) on a surface and in the cavity of a substrate. In some aspects of the present disclosure, the substrate is composed of a blind cavity alumina (BCA) substrate, supporting an RDL formed by depositing a thick copper layer directly built on the BCA substrate with high thermal conductivity. In these aspects of the present disclosure, the inductive device structure enables formation of an inductor having both a higher Q-factor and inductance density to support a higher power handling capability when implemented in integrated passive device (IPD) filters. According to aspects of the present disclosure, an RFFE module includes an IPD filter implemented using the inductive device structure.

According to a further aspect of the present disclosure, a device includes a means conducting on sidewalls and a base of a first cavity in a substrate and on a first surface of the substrate. In one configuration, the conducting means may be the inductor420, as shown inFIGS.4A and4B. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions recited by the aforementioned means. (Completed after claim language approval).

FIG.11is a block diagram showing an exemplary wireless communications system1100in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration,FIG.11shows three remote units1120,1130, and1150and two base stations1140. It will be recognized that wireless communications systems may have many more remote units and base stations. Remote units1120,1130, and1150include integrated circuit (IC) devices1125A,1125C, and1125B that include the disclosed inductive device structure. It will be recognized that other devices may also include the disclosed inductive device structure, such as the base stations, switching devices, and network equipment.FIG.11shows forward link signals1180from the base station1140to the remote units1120,1130, and1150, and reverse link signals1190from the remote units1120,1130, and1150to base stations1140.

InFIG.11, remote unit1120is shown as a mobile telephone, remote unit1130is shown as a portable computer, and remote unit1150is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as meter reading equipment, or other device that stores or retrieves data or computer instructions, or combinations thereof. AlthoughFIG.11illustrates remote units according to the aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the disclosed inductive device structure.

FIG.12is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the inductive device structure disclosed above. A design workstation1200includes a hard disk1201containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation1200also includes a display1202to facilitate design of a circuit1210or a radio frequency (RF) component1212such as an RDL substrate. A storage medium1204is provided for tangibly storing the design of the circuit1210or the RF component1312(e.g., the inductive device structure). The design of the circuit1210or the RF component1212may be stored on the storage medium1204in a file format such as GDSII or GERBER. The storage medium1204may be a compact disc read-only memory (CD-ROM), digital versatile disc (DVD), hard disk, flash memory, or other appropriate device. Furthermore, the design workstation1200includes a drive apparatus1203for accepting input from or writing output to the storage medium1204.

Data recorded on the storage medium1204may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium1204facilitates the design of the circuit1210or the RF component1212by decreasing the number of processes for designing semiconductor wafers.

Implementation examples are described in the following numbered clauses:1. A device, comprising:a substrate;a first redistribution layer (RDL) on sidewalls and a base of a first cavity in the substrate and on a first surface of the substrate; anda fill material in the first cavity.2. The device of clause 1, further comprising:a second redistribution layer (RDL) on sidewalls and a base of a second cavity in the substrate and on a second surface opposite the first surface of the substrate;the fill material in the second cavity; anda through via extending from the first surface to the second surface of the substrate and coupled to the second RDL.3. The device of any of clauses 1 or 2, in which the first RDL is on opposing sidewalls of the first cavity and a width of the first RDL is less than a width of the first cavity.4. The device of any of clauses 1-3, in which a portion of the first RDL on the base of the first cavity is diagonally disposed on the base of the first cavity.5. The device of any of clauses 1-4, further comprising conductive interconnects coupled to a portion of the first RDL on the first surface of the substrate.6. The device of any of clauses 1-5, in which the fill material comprises a magnetic paste or a dry film.7. The device of any of clauses 1-6, in which the substrate comprises alumina, glass, gallium arsenide, high resistivity silicon, and/or a laminate material.8. The device of any of clauses 1-7, in which the device is integrated in an integrated passive device (IPD).9. The device of clause 8, in which the IPD is integrated in a radio frequency (RF) filter.10. The device of clause 8, in which the IPD is integrated in a radio frequency (RF) front-end (RFFE) module.11. A method for fabricating a device, comprising:forming a first cavity in a substrate;depositing a first seed layer on sidewalls and a base of the first cavity and on a first surface of the substrate;depositing a photoresist material on the first surface and in the first cavity in the substrate;exposing the photoresist material on the first surface and in the first cavity in the substrate to form a first redistribution layer (RDL) mask;depositing a first conductive material according to the first RDL mask to form a first redistribution layer (RDL) on the sidewalls and the base of the first cavity in the substrate and on the first surface of the substrate; andfilling the first cavity in the substrate with a fill material.12. The method of clause 11, further comprising:forming a second cavity in the substrate, opposite the first cavity;depositing a second seed layer on sidewalls and a base of the second cavity and on a second surface opposite the first surface of the substrate;depositing the photoresist material on the second surface and in the second cavity in the substrate;exposing the photoresist material on the second surface and in the second cavity in the substrate to form a second redistribution layer (RDL) mask;depositing a second conductive material according to the second RDL mask to form a second redistribution layer (RDL) on the sidewalls and the base of the second cavity in the substrate and on the second surface of the substrate;filing the second cavity in the substrate with the fill material; andform a through via extending from the first surface to the second surface of the substrate and coupled to the second RDL.13. The method of any of clauses 11 or 12, in which the first RDL is on opposing sidewalls of the first cavity and a width of the first RDL is less than a width of the first cavity.14. The method of any of clauses 11-13, in which a portion of the first RDL on the base of the first cavity is diagonally disposed on the base of the first cavity.15. The method of any of clauses 11-14, further comprising coupling conductive interconnects to a portion of the first RDL on the first surface of the substrate.16. The method of any of clauses 11-15, in which the fill material comprises a magnetic paste or a dry film.17. The method of any of clauses 11-16, in which the substrate comprises alumina, glass, gallium arsenide, high resistivity silicon, and/or a laminate material.18. The method of any of clauses 11-17, further comprising integrating the device in an integrated passive device (IPD).19. The method of clause 18, further comprising integrating the IPD in a radio frequency (RF) filter.20. The method of clause 18, further comprising integrating the IPD in a radio frequency (RF) front-end (RFFE) module.

The previous description of the present disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.