Adaptive diode sizing techniques for reducing memory power leakage

Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply voltage for a memory array which tracks the data retention voltage of the memory array. In one embodiment, multiple diodes are implemented in parallel between a supply voltage and the memory array. The diodes have different sizes and different voltage drops, and the diode which will cause the voltage to drop closest to without going below the data retention voltage is selected for routing the supply voltage to the memory array. Since the data retention voltage for the memory array varies over temperature, the temperature of the system is monitored. Based on changes in the temperature, the system changes which diode is in the circuit path for supplying power to the memory array so as to reduce leakage current for the memory array.

BACKGROUND

Technical Field

Embodiments described herein relate to the field of integrated circuits and more particularly, to implementing adaptive diode sizing techniques for reducing power leakage in memories.

Description of the Related Art

In power-efficient silicon memories, it is desirable to power a static random-access memory (SRAM) at the lowest voltage possible to minimize standby power. The SRAM bitcell is a bi-stable circuit made up of cross-coupled CMOS inverters. For an SRAM, the data retention voltage (DRV) defines the minimum supply voltage at which data in the SRAM is still preserved. When portions of the SRAM are not being accessed, these portions may be placed in retention mode to conserve power. In retention mode, if the voltage supplied to the SRAM cells falls below the DRV, the SRAM cells will fail (i.e., data stored in the SRAM cells will be lost). Therefore, it is important to provide a supply voltage which stays above the DRV. Unfortunately, the DRV is a difficult voltage to track as it varies with temperature and process. For example, as temperature decreases, the DRV increases. However, overcompensating and providing a supply voltage to the SRAM for a worst case scenario results in increased power consumption.

SUMMARY

Systems, apparatuses, and methods for implementing adaptive diode sizing techniques to reduce leakage power for memory arrays are contemplated.

In one embodiment, a system includes multiple diodes implemented in parallel and memory array. The system is configured to determine which diode to utilize for generating a supply voltage for one or more portions of the memory array based at least in part on a temperature of the system. The system is configured to utilize a selected diode of the plurality of diodes to generate a supply voltage which tracks a data retention voltage for the memory array as the data retention voltage varies based on temperature, process variations during fabrication, and/or one or more other factors.

In one embodiment, the system also includes a control unit and multiple transistors. The control unit is configured to generate a control signal to activate a corresponding transistor to cause the selected diode to be switched into a circuit path for supplying power for the one or more portions of the memory array. In one embodiment, the control unit includes a lookup table, and the control unit utilizes the temperature as an input to the lookup table to choose the selected diode of the plurality of diodes to activate via the corresponding transistor.

In one embodiment, the system is configured to pass a supply voltage for one or more portions of the memory array through a first diode at a given point of time. The system is configured to prevent the supply voltage from passing through the other diodes at the given point in time. The first diode may be selected based on the current temperature and/or one or more additional factors. Then, at a later point in time, a first condition may be detected. In one embodiment, the first condition may be a change in temperature greater than a threshold. In response to detecting the first condition, the system passes the supply voltage for one or more portions of the memory array through a second diode and switches the first diode out of the circuit path for powering the one or more portions of the memory array. It may be assumed for the purposes of this discussion that the second diode is different from the first diode.

These and other features and advantages will become apparent to those of ordinary skill in the art in view of the following detailed descriptions of the approaches presented herein.

DETAILED DESCRIPTION OF EMBODIMENTS

This specification includes references to “one embodiment”. The appearance of the phrase “in one embodiment” in different contexts does not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. Furthermore, as used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to.

“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps. Consider a claim that recites: “A system comprising a circuit . . . .” Such a claim does not foreclose the system from including additional components (e.g., a processor, a memory controller).

Referring now toFIG. 1, a block diagram of one embodiment of an adaptive memory system100is shown. System100includes memory megacell102. Megacell102includes any number of static random-access memory (SRAM) cells which are powered by an adjustable supply voltage. In one embodiment, the adjustable supply voltage is controlled by the extra margin adjustment (EMA) bits generated by control unit104. Accordingly, the output of control unit104may control and adjust the voltage level of the power supplied to any number of memory cells. While discussion in this disclosure is directed to SRAM memory cells, embodiments described herein may be applicable to other types of memory cells.

In one embodiment, control unit104includes a lookup table for determining how to adjust the voltage level supplied to megacell102based on the inputs from temperature sensor106, process data108, and dynamic voltage frequency management (DVFM) unit110. Temperature sensor106provides temperature readings for the on-chip temperature associated with megacell102. Process data108provides an indication of the process variability used to fabricate the system100. DVFM unit110provides an indication of the current voltage and/or frequency settings of the power supply used for powering megacell102and/or other circuitry. It is noted that system100may also be referred to as a system on chip (SoC) or integrated circuit (IC).

Turning now toFIG. 2, a diagram of one embodiment of an adaptive diode sizing circuit200is shown. Circuit200includes memory cell215, and circuit200is configured to select one of diodes210A-N to provide the optimal supply voltage for memory cell215when memory cell215is in retention mode. The outputs of diodes210A-N are coupled together at connection220, with connection220providing power at an adjustable supply voltage to memory cell215. Diodes210A-N are representative of any number and type of diodes which may be located in parallel between the supply voltage and connection220. It is noted that any number of memory cells can be coupled to the supply voltage provided by the connection220. It is noted that the term “coupled” as used herein is defined as electrically connected.

Diodes205A-N include multiple diodes of different or same sizes. The voltage drop across the different diodes205A-N may vary according to the size of the diode. By having multiple different sizes of diodes205A-N in parallel between the supply voltage and connection220, a control unit (not shown) is able to select the diode which will provide a voltage closest to the data retention voltage of memory cell215while also being greater than the data retention voltage. This will allow circuit200to reduce the amount of leakage power lost by memory cell215.

Control signals0-N (Cnt[0-N]) are coupled to transistors205A-N, respectively. Transistors205A-N are representative of any type of transistors. In one embodiment, transistors205A-N are p-channel transistors. In other embodiments, transistors205A-N may be other types of transistors. In one embodiment, the control signals0-N are active low signals. A control unit is configured to select one of diodes205A-N for coupling the supply voltage to memory bitcell215based on one or more of a temperature sensor, process variations during fabrication, voltage/frequency settings, and/or other factors. In one embodiment, the control unit selects the diode from diodes205A-N which will provide a supply voltage to memory bitcell215which is nearest to the data retention voltage while also being greater than the data retention voltage. The control unit is configured to generate control signals0-N to route the supply current through the chosen path which includes the selected diode.

In one embodiment, the control unit is configured to drive one of the control signals low to select the chosen diode210A-N. The other control signals are driven high to prevent current from flowing through the corresponding transistors205A-N. In another embodiment, the control unit may drive one of the control signals high to pass the supply voltage through the chosen diode210A-N. In this embodiment, transistors205A-N may be n-channel transistors.

Referring now toFIG. 3, a block diagram of one embodiment of a circuit300to generate control bits for selecting a size of a diode is shown. In one embodiment, circuit300can generate the control bits that are utilized to select one of the diode sizes from the diodes210A-N of circuit200(ofFIG. 2). In one embodiment, temperature sensor306, process data308, and DVFM unit310generate inputs to control unit304. In other embodiments, a subset of these inputs and/or other inputs may be coupled to control unit304. Control unit304is configured to generate control bits based on the values of these inputs. In one embodiment, control unit304includes a lookup table to generate the control bits from the various inputs. In other embodiments, control unit304may include other mechanisms for generating control bits.

Turning now toFIG. 4, one embodiment of a lookup table400for selecting a diode for generating an optimal supply voltage to minimize leakage current is shown. In one embodiment, a control unit (e.g., control unit304ofFIG. 3) utilizes lookup table400for selecting the diode which will generate the optimal supply voltage for reducing leakage of SRAM bitcells. In one embodiment, lookup table400stores entries for different temperature ranges, with each temperature range associated with a corresponding diode which will generate the optimal retention voltage for the respective temperature range. In other embodiments, lookup table400can also include entries which utilize process variations and the voltage/frequency settings to determine which diode to select. The diodes have different sizes with different voltage drops from the input supply voltage at the input of the diode to the voltage level at the output of the diode. The diode which will provide a voltage drop which generates a supply voltage closest to the data retention voltage while not falling below the data retention voltage may be chosen by the control unit. As shown in table400, there are eight diodes to choose from. However, in other embodiments, other numbers of diodes may be implemented in parallel with a single diode or multiple diodes being selected for generating the supply voltage for the SRAM array.

Referring now toFIG. 5, a graph500illustrating the variation in the data retention voltage over temperature for an SRAM array is shown. Diagram500illustrates plots of the data retention voltage (DRV) versus temperature in Celsius for three different processes502,504, and506. For the plot for process502, there is an 84 millivolt (mV) difference between the DRV at −40° C. and room temperature of 25° C.

In the prior art, a diode providing the supply voltage for a SRAM array would be sized to provide a supply voltage greater than the DRV for the worst case scenario of −40° C. For these circuits, the typical scenario of operating the circuit at room temperature (approximately 25° C.) would cause the supply voltage to be about 84 mV higher than required to retain data, resulting in power being wasted due to an increase in the leakage current. However, by using circuit200shown inFIG. 2and adaptively changing the diode size based on temperature, substantial reductions in leakage power may be achieved.

Turning now toFIG. 6, a block diagram of one embodiment of a circuit600for implementing a temperature sensor is shown. In one embodiment, the elements of circuit600may be implemented as temperature sensor106(ofFIG. 1). Circuit600includes startup circuit604, cascode voltage generator606, proportional to absolute temperature (PTAT) current generator610, constant voltage generator612, timers620A-B, and ping-pong logic618. In other embodiments, circuit600can include other units and/or be arranged in different configurations.

Startup circuit604is configured to generate a start signal which is conveyed to cascode voltage generator606. Cascode voltage generator606is configured to generate voltage reference signals, P_CAS and N_CAS, to provide as inputs to PTAT current generator610. One example of a cascode voltage generator is illustrated and described in more detail below inFIG. 7. PTAT current generator610is configured to generate the P_BIAS signal which is provided to constant voltage generator612and timers620A-B. One example of a PTAT current generator is illustrated and described in more detail below inFIG. 7.

Constant voltage generator612is configured to generate a voltage reference signal (V_REF) which is coupled to the negative inputs of comparators624and630of timers620A and620B, respectively. The extra margin adjustment (EMA) bits are coupled to tuner614which is configured to tune constant voltage generator612based on temperature, process variation, and/or voltage/frequency settings. The signal P_BIAS is coupled from PTAT current generator610to current sources I_PTAT_A622and I_PTAT_B628of timers620A and620B, respectively. Current source622and628are configured to generate current sources to charge capacitors626and632, respectively. The voltage of capacitor626is compared to the V_REF signal by comparator624, with the output of comparator624coupled to ping-pong logic618. Similarly, the voltage of capacitor632is compared to the V_REF signal by comparator630, with the output of comparator630coupled to ping-pong logic618. Ping-pong logic618utilizes the inputs from comparator624and comparator630to generate a temperature value.

Referring now toFIG. 7, a diagram of one embodiment of a circuit700for implementing a cascode voltage generator and a PTAT current generator is shown. In one embodiment, the elements of circuit700may be implemented as part of blocks606and610of circuit600(ofFIG. 6). Circuit700includes p-channel transistors702,704,712,714, and716, n-channel transistors706,708,718,720, and722, and resistors710and724. The types of transistors that are used for the transistors in circuit700and in the other circuits shown throughout this disclosure can vary from embodiment to embodiment. It is noted that, in various embodiments, a “transistor” may correspond to one or more transconductance elements such as a metal oxide semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar transistor, or others. For example, in one embodiment, each p-channel transistor may be a p-channel metal-oxide semiconductor (PMOS) transistor and each n-channel transistor may be an n-channel metal-oxide-semiconductor (NMOS) transistor. In other embodiments, the p-channel transistors and n-channel transistors shown inFIG. 7and in other figures may be implemented using other types of transistors.

The source of p-channel transistor702is coupled to the supply voltage (VDD). The gate of p-channel transistor702is coupled to the gate of n-channel transistor704. The supply voltage is coupled to the source of p-channel transistor704, the source of p-channel transistor712, and the source of p-channel transistor714. The gates of p-channel transistors702and704are coupled to the drain of p-channel transistor702and to the gate of p-channel transistor716, with this connection labeled as P_CAS. The drain of p-channel transistor702is coupled to the drain of n-channel transistor706. The drain of p-channel transistor704is coupled to the drain of n-channel transistor708and the gate of n-channel transistor718, with this connection labeled N_CAS. The source of n-channel transistor706is coupled to one end of resistor710. The other end of resistor710coupled to ground (or VSS). In one embodiment, resistor710is a 20 kiloohm resistor.

In other embodiments, resistor710may be other sizes of resistors. The source of n-channel transistor708is coupled to ground. The gate of n-channel transistor706is coupled to the gate and drain of n-channel transistor708. With transistors706and708biased in the sub-threshold region of operation, the voltage across resistor710is independent of process and the power supply voltage.

The drain of p-channel transistor712is coupled to the gate of p-channel transistor712and to the gate of p-channel transistor714, with this connection labeled as P_BIAS. The drain of p-channel transistor712is also coupled to the drain of n-channel transistor718. The drain of p-channel transistor714is coupled to the source of p-channel transistor716. The source of n-channel transistor718is coupled to the drain of n-channel transistor720. The gate of n-channel transistor720is coupled to the gate of n-channel transistor722and to the drain of n-channel transistor722, with this connection labeled as N_BIAS. The drain of n-channel transistor722is also coupled to the drain of p-channel transistor716. The source of n-channel transistor720is coupled to one end of resistor724. The other end of resistor724is coupled to ground. In one embodiment, resistor724is a 20 kiloohm resistor. In other embodiments, resistor724may be other sizes of resistors, with the size of resistor724matching the size of resistor710. The source of n-channel transistor722is coupled to ground.

Turning now toFIG. 8, a diagram of one embodiment of a circuit800for implementing a constant voltage generator is shown. In one embodiment, the circuit elements of circuit800may be implemented as part of constant voltage generator612(ofFIG. 6). The source of p-channel transistor802is coupled to the supply voltage (VDD). The P_BIAS signal generated by a current generator (e.g., current generator610ofFIG. 6) is coupled to the gate of p-channel transistor802. The current flowing through p-channel transistor802is proportional to absolute temperature and is labeled as I_PTAT. The drain of p-channel transistor802is the output voltage reference signal from circuit800and is labeled as V_REF. The drain of p-channel transistor802is coupled to one end of resistor804. The other end of resistor804is coupled to the drain of n-channel transistor806. The voltage across resistor804is proportional to absolute temperature and is labeled as V_PTAT.

The drain of n-channel transistor806is coupled to the gate of n-channel transistor806. The source of n-channel transistor806is coupled to ground. The voltage across n-channel transistor806is complementary to absolute temperature and is labeled as V_CTAT. Accordingly, since V_REF is the sum of V_PTAT and V_CTAT, V_REF is virtually independent of temperature.

Referring now toFIG. 9, a diagram of another embodiment of a circuit900for implementing a constant voltage generator is shown. In one embodiment, the circuit elements of circuit900may be implemented as part of constant voltage generator612(ofFIG. 6). The source of p-channel transistor902is coupled to the supply voltage. The P_BIAS signal generated by a current generator (e.g., current generator610ofFIG. 6) is coupled to the gate of p-channel transistor902. The current flowing through p-channel transistor902is proportional to absolute temperature and is labeled as I_PTAT. The drain of p-channel transistor902is coupled to one end of resistor904and to one end of resistor908. The other end of resistor904is coupled to the drain of n-channel transistor906. The voltage across resistor904is proportional to absolute temperature and is labeled as V_PTAT. The drain of n-channel transistor906is coupled to the gate of n-channel transistor906. The source of n-channel transistor906is coupled to ground. The voltage across n-channel transistor906is complementary to absolute temperature and is labeled as V_CTAT.

The other end of resistor908is coupled to one end of resistor910. The other end of resistor910is coupled to ground. The connection between resistor908and resistor910is the output voltage reference signal from circuit1000and is labeled as V_REF. Since V_REF is proportional to the sum of V_PTAT and V_CTAT, V_REF is virtually temperature independent. The ratio of V_REF to the sum of V_PTAT and V_CTAT depends on the values of resistors908and910, which may be selected to choose a value of V_REF which is appropriate for a given embodiment.

Turning now toFIG. 10, one embodiment of a method1000for implementing an adaptive diode sizing mechanism is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various systems, apparatuses, and/or circuits described herein may be configured to implement method1000.

A system is configured to monitor temperature (block1005). The temperature of the system may also be referred to as the on-chip temperature. In some cases, the temperature may be associated with a memory array of the system. The system then selects a diode of a plurality of diodes based at least on the temperature of the system (block1010). The system couples a first supply voltage to an input of the selected diode (block1015).

The system couples an output of the selected diode as a second supply voltage to one or more portions of a memory array (block1020). In one embodiment, the memory array is a SRAM array. In other embodiments, the memory array may be array of other types of memories, such as NAND or NOR Flash, or DRAM memory arrays. In one embodiment, the outputs of the plurality of diodes are connected together, and the voltage level of this connection is the second supply voltage. The second supply voltage is equal to the first supply voltage minus the voltage drop across the selected diode. The system utilizes the second supply voltage to track a data retention voltage of the memory array as the data retention voltage varies based on temperature (block1025). After block1025, method1000may end.

Referring now toFIG. 11, another embodiment of a method1100for implementing an adaptive diode sizing mechanism is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various systems, apparatuses, and/or circuits described herein may be configured to implement method1100.

A system is configured to monitor temperature (block1105). Based on the temperature, the system selects a first diode of a plurality of diodes and routes a supply voltage through the first diode for supplying power to one or more portions of a memory array (block1110). In one embodiment, the memory array is a SRAM array.

At a later point in time, the system detects a change in temperature that will cause a different diode to be selected for supplying power to the one or more portions of a memory array (block1115). In response to detecting this change in temperature, the system switches a second diode into the circuit path for supplying power to the one or more portions of the memory array (block1120). Also, the system switches the first diode out of the circuit path for supplying power for one or more portions of the memory array (block1125). After block1125, method1100may end.

Referring now toFIG. 12, a graph1200of a retention voltage for an SRAM bitcell as it varies over temperature is shown. Line1202represents the retention voltage for an SRAM array fabricated using a first process. Line1204represents the retention voltage for an SRAM array fabricated using a second process. A typical circuit in the prior art would set the voltage supplied to an SRAM array in retention mode to be greater than or equal to the retention voltage at −25 Celsius (C). However, for a circuit at room temperature (25° C.), this circuit would be providing a supply voltage that is substantially higher than the retention voltage, resulting in wasted power. As will be described in further detail in the description associated with subsequent figures, a circuit that can track the change in the retention voltage due to temperature can achieve power savings for systems and apparatuses which include SRAM arrays. Additionally, circuits that can generate a supply voltage to automatically track changes in the retention voltage due to process variations during fabrication of the SRAM arrays and due to supply voltage fluctuations can also achieve power savings.

In one embodiment, a voltage threshold reference that is proportional to absolute temperature is generated using SRAM transistors biased in the sub-threshold region of operation. The current is mirrored between two branches, with a diode-connected n-channel transistor being run at a different current density than the mirror transistor. A resistor provides feedback that makes the circuit output voltage independent of the supply voltage. The voltage across the resistor is linear as a function of temperature, and therefore, so is the output current. The current also tracks linearly as a function of the SRAM leakage. The current from the voltage threshold reference is then mirrored into a circuit tracking the threshold voltages of a p-channel transistor and an n-channel transistor. Whichever threshold voltage is greater between these transistors is used as a set point for a voltage regulator to generate a supply voltage for an SRAM array which tracks the retention voltage.

Turning now toFIG. 13, a block diagram of one embodiment of a system1300is shown. In various embodiments, system1300may be a system on chip (SoC), an integrated circuit (IC), or other types of systems. System1300includes at least circuit1305, circuit1310, voltage regulator1315, and memory1320. In one embodiment, memory1320is an SRAM array. In other embodiments, memory1320may be other types of memory units. In one embodiment, circuit1305and1310and voltage regulator1315may be considered part of the same circuit but are shown separately inFIG. 13for the purposes of discussion.

Circuit1305is configured to track a leakage current indicative of the bitcells of the memory1320as the leakage current varies over temperature. For example, in one embodiment, circuit1305tracks a voltage threshold reference that is proportional to absolute temperature (PTAT) using SRAM transistors biased in the sub-threshold region of operation.

Circuit1305may provide a gate voltage to a pull-up transistor of circuit1310. In one embodiment, circuit1310is configured to mirror the leakage current of circuit1305and track the higher threshold voltage of a p-channel transistor or an n-channel transistor, with the p-channel and n-channel transistors being matching transistors to the transistors in the bitcells of the memory1320. In one embodiment, circuit1310includes a diode-connected p-channel tracking transistor which is wrapped inside a diode-connected n-channel tracking transistor. The voltage reference output generated by circuit1310is the logical OR of whichever of the p-channel and n-channel thresholds is higher. The higher of these thresholds is coupled as a voltage reference to voltage regulator1315.

Voltage regulator1315supplies retention mode power to memory1320at a supply voltage proportional to the voltage reference generated by circuit1310. The power supplied to memory1320by voltage regulator1315is at a voltage which tracks the retention voltage. In one embodiment, an optional margin may be added to the supply voltage by voltage regulator1315so that the supply voltage is at a level slightly higher than the retention voltage. This optional margin may be adjusted via one or more programmable circuit elements in circuit1305and/or circuit1310. It is noted that system1300may also be referred to as an apparatus. It is also noted that system1300may include other components in addition to those shown inFIG. 13.

Referring now toFIG. 14, a diagram of one embodiment of a retention voltage tracking reference circuit1400is shown. In one embodiment, retention voltage tracking reference circuit1400is coupled to a voltage regulator (not shown). Retention voltage tracking reference circuit1400is configured to supply a reference voltage (VREF1416) to the voltage regulator, with VREF1416tracking the retention voltage of a static random-access memory (SRAM) array (e.g., SRAM array1320ofFIG. 13). The voltage regulator may utilize VREF1416to generate a supply voltage for supplying power to the SRAM array. The reference voltage (VREF1416) generated by circuit1400is able to track the retention voltage as it changes due to temperature, supply voltage, and process variations.

Retention tracking reference circuit1400includes p-channel transistors1402,1404,1406, and1412, n-channel transistors1408,1410, and1414, and resistor1418. In one embodiment, p-channel transistors1404and1406may be programmable to add a margin to VREF1416. The gate of p-channel transistor1402is coupled to the gates of p-channel transistors1404and1406. The gate of p-channel transistor1402is also coupled to the drain of p-channel transistor1402. It is noted that p-channel transistor1402may also be referred to as a pull-up transistor. The source of p-channel transistor1402is coupled to the supply voltage for circuit1400. The drain of p-channel transistor1402is coupled to the drain of n-channel transistor1408. The source of n-channel transistor1408is coupled to one end of resistor1418with the other end of resistor1418coupled to ground. The resistance of resistor1418may vary from embodiment to embodiment, with the higher the resistance, the lower the amount of power which is lost through resistor1418.

The gate of n-channel transistor1408is coupled to the gate of n-channel transistor1410, with the gate of n-channel transistor1410also coupled to the drain of n-channel of transistor1410. The drain of n-channel transistor1410is also coupled to the drain of p-channel transistor1404. The source of n-channel transistor1410is coupled to ground. It is noted that n-channel transistor1410may also be referred to as a pull-down transistor.

The sources of p-channel transistors1404and1406are coupled to the supply voltage, and the drain of p-channel transistor1406is coupled to the source of p-channel transistor1412. P-channel transistor1412is connected such that it functions similar to a diode. The drain of p-channel transistor1412is coupled to the gate of p-channel transistor1412and to the drain of n-channel transistor1414. The source of n-channel transistor1414is coupled to ground. The gate of n-channel transistor1414is coupled to the drain of p-channel transistor1406and is the voltage reference (or VREF) signal1416. The connections of transistor1412and1414serve as a logical OR of two analog voltages, with VREF signal1416generated as the higher of the threshold voltages of p-channel transistor1412and n-channel transistor1414. In one embodiment, p-channel transistor1412and n-channel transistor1414match the p-channel and n-channel transistors used in the SRAM array. Accordingly, these circuit elements are able to track changes in the threshold voltages due to process variations during fabrication.

The types of transistors that are used for the transistors in circuit1400can vary from embodiment to embodiment. It is noted that, in various embodiments, a “transistor” may correspond to one or more transconductance elements such as a metal oxide semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar transistor, or others. For example, in one embodiment, each p-channel transistor may be a p-channel metal-oxide semiconductor (PMOS) transistor and each n-channel transistor may be an n-channel metal-oxide-semiconductor (NMOS) transistor. In one embodiment, the circuit elements of1400may be used to construct circuits1305and1310(ofFIG. 13).

Turning now toFIG. 15, a diagram of one embodiment of a circuit1500is shown. Circuit1500includes retention tracking reference circuit1505and voltage regulator circuit1510. It is noted that retention tracking reference circuit1505is equivalent to circuit1400(ofFIG. 14). The gates of the p-channel transistors at the top of retention tracking reference circuit1505are coupled together and these gates are also coupled to the gate of p-channel transistor1520of voltage regulator circuit1510. The source of p-channel transistor1520is coupled to the supply voltage, and the drain of p-channel transistor1520is coupled to the drain of n-channel transistor1525. The gate of n-channel transistor1525is coupled to the drain of n-channel transistor1525and to the gate of n-channel transistor1540. The sources of n-channel transistor1525and n-channel transistor1540are coupled to ground.

The gate of p-channel transistor1530is coupled to the gate of p-channel transistor1545and to the drain of p-channel transistor1530. The sources of p-channel transistor1530and p-channel transistor1545are coupled to the supply voltage. The drain of p-channel transistor1530is coupled to the drain of n-channel transistor1535. The drain of p-channel transistor1545is coupled to the drain of n-channel transistor1550and to the gate of p-channel transistor1555. The source of p-channel transistor1555is coupled to the supply voltage. The source of n-channel transistor1535is coupled to the source of n-channel transistor1550and to the drain of n-channel transistor1540. The voltage reference signal generated by circuit1505and labeled as VREF is coupled to the gate of n-channel transistor1550. The gate of n-channel transistor1535is coupled to the drain of p-channel transistor1555, with this voltage tracking VREF. The drain of p-channel transistor1555is also coupled as an input to SRAM array1515and is used as the retention voltage of SRAM array1515.

Referring now toFIG. 16, one embodiment of a method1600for supplying a standby voltage of a memory array is shown. In some embodiments, method1600may be used for supplying a standby voltage to an SRAM array but in other embodiments, method1600may be used for supplying a standby voltage to other types of memory arrays. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various systems, apparatuses, and/or circuits described herein may be configured to implement method1600.

A circuit is configured to generate a voltage that is proportional to leakage current of a static random-access memory (SRAM) bitcell (block1605). In one embodiment, generating a current that is proportional to the leakage current of an SRAM bitcell comprises biasing an n-channel transistor so that the n-channel is in a sub-threshold region of operation to track the leakage current of an SRAM bitcell as the leakage current varies over temperature. The circuit utilizes the voltage to bias a voltage regulator (block1610). The circuit utilizes the voltage regulator to supply power to an SRAM array at a voltage which is proportional to the leakage current of the SRAM bitcell (block1615). After block1615, method1600may end.

Referring now toFIG. 17, another embodiment of a method1700for supplying a standby voltage of a memory array is shown. In some embodiments, method1700may be used for supplying a standby voltage to an SRAM array but in other embodiments, method1700may be used for supplying a standby voltage to other types of memory arrays. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various systems, apparatuses, and/or circuits described herein may be configured to implement method1700.

A circuit tracks which threshold voltage is greater between a p-channel transistor threshold voltage and an n-channel transistor threshold voltage (block1705). In one embodiment, the circuit tracks which threshold voltage is greater by connecting a p-channel transistor in series with an n-channel transistor, connecting a gate of the p-channel transistor to a drain of the p-channel transistor, and connecting a gate of the n-channel transistor to a source of the p-channel transistor. The circuit mirrors leakage current of an SRAM bitcell through the p-channel transistor and the n-channel transistor connected in series.

The circuit generates a supply voltage proportional to whichever threshold voltage is greater between the p-channel transistor threshold voltage and the n-channel transistor threshold voltage (block1710). In one embodiment, the supply voltage may be set equal to whichever threshold voltage is greater. In another embodiment, a margin may be added to whichever threshold voltage is greater, and then the supply voltage may be generated so that it is equal to the sum of the margin and the threshold voltage. The circuit supplies power to an SRAM array at the supply voltage (block1715). In one embodiment, a device type of the n-channel transistor is a same device type as n-channel transistors of the bitcells of the SRAM array, and a device type of the p-channel transistor is a same device type as p-channel transistors of the bitcells of the SRAM array. After block1715, method1700may end.

Referring now toFIG. 18, one embodiment of a method1800for fabricating a circuit for generating a standby voltage for a memory array is shown. In some embodiments, method1800may be used for fabricating a circuit for an SRAM array but in other embodiments, method1800may be used for fabricating a circuit for other types of memory arrays. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various systems, apparatuses, and/or circuits described herein may be configured to implement method1800.

A first p-channel transistor is connected in series with a first n-channel transistor and a resistor in between a supply voltage and ground (block1805). A second p-channel transistor is connected in series with a second n-channel transistor in between the supply voltage and ground (block1810). A third p-channel transistor is connected in series with a fourth p-channel transistor and a third n-channel transistor in between the supply voltage and ground (block1815). In one embodiment, the fourth p-channel transistor is a same type of p-channel transistor used in bitcells of the SRAM array, and the first, second, and third n-channel transistors are a same type of n-channel transistor used in bitcells of the SRAM array.

A drain of the first p-channel transistor is connected to a drain of the first n-channel transistor, a source of the first n-channel transistor is connected to a first end of the resistor, and a second end of the resistor is connected to ground (block1820). A gate of the first p-channel transistor is connected to a drain of the first p-channel transistor, to a gate of the second p-channel transistor, and to a gate of the third p-channel transistor (block1825). A gate and a drain of the second n-channel transistor are connected to a gate of the first n-channel transistor, a gate and drain of the fourth p-channel transistor are connected together, and a gate of the third n-channel transistor is connected to a source of the fourth p-channel transistor (block1830). Additionally, a voltage at a source of the fourth p-channel transistor is utilized by a voltage regulator to set a standby voltage of an SRAM array (block1835). After block1835, method1800may end.

Turning now toFIG. 19, one embodiment of a method1900for generating a voltage reference is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various systems, apparatuses, and/or circuits described herein may be configured to implement method1900.

A first portion of a circuit tracks the leakage current of an n-channel transistor as the leakage current varies over temperature (block1905). In one embodiment, circuit1305of (FIG. 13) may be used to track the leakage current as it varies over temperature. Then, the leakage current is mirrored into a second portion of the circuit (block1910). In one embodiment, the leakage current may be mirrored from circuit1305into circuit1310. The second portion of the circuit tracks the threshold voltages of a p-channel transistor and an n-channel transistor (block1915). The second portion of the circuit tracks for process variations during fabrication of the SRAM bitcells. The p-channel transistor and n-channel transistor in the second portion of the circuit match the p-channel transistor and n-channel transistor, respectively, used in the bitcells of the SRAM array.

If the threshold voltage (Vt) of the p-channel transistor is greater than the threshold voltage of the n-channel transistor as tracked by the second portion of the circuit (conditional block1920, “yes” leg), then the threshold voltage of the p-channel transistor is used as the retention voltage of the SRAM array (block1925). Otherwise, if the threshold voltage of the n-channel transistor is greater than the threshold voltage of the p-channel transistor (conditional block1920, “no” leg), then the threshold voltage of the n-channel transistor is used as the voltage reference (block1930). Then, after blocks1925and1930, the voltage reference is connected to a voltage regulator and used to generate a standby voltage for an SRAM array (block1935). After block1935, method1900may end.

Turning now toFIG. 20, a block diagram illustrating an exemplary non-transitory computer-readable storage medium that stores circuit design information is shown. In the illustrated embodiment, semiconductor fabrication system2020is configured to process the design information2015stored on non-transitory computer-readable medium2010and fabricate integrated circuit2030based on the design information2015.

Non-transitory computer-readable medium2010may comprise any of various appropriate types of memory devices or storage devices. Medium2010may be an installation medium, (e.g., a CD-ROM, floppy disks, or tape device) a computer system memory or random access memory (e.g., DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM), a non-volatile memory (e.g., a Flash, magnetic media, a hard drive, optical storage), registers, or other types of memory elements. Medium2010may include other types of non-transitory memory as well or combinations thereof. Medium2010may include two or more memory mediums which may reside in different locations (e.g., in different computer systems that are connected over a network).

Design information2015may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information2015may be usable by semiconductor fabrication system2020to fabricate at least a portion of integrated circuit2030. The format of design information2015may be recognized by at least one semiconductor fabrication system2020. In some embodiments, design information2015may also include one or more cell libraries which specify the synthesis and/or layout of integrated circuit2030.

In various embodiments, integrated circuit2030is configured to operate according to a circuit design specified by design information2015, which may include performing any of the functionality described herein. For example, integrated circuit2030may include any of various elements shown inFIGS. 1-3, 6-9, and 13-15. Furthermore, integrated circuit2030may be configured to perform various functions described herein in conjunction with other components. For example, integrated circuit2030may be coupled to voltage supply circuitry that is configured to provide a supply voltage (e.g., as opposed to including a voltage supply itself). Further, the functionality described herein may be performed by multiple connected integrated circuits.

Referring next toFIG. 21, a block diagram of one embodiment of a system2100is shown. As shown, system2100may represent chip, circuitry, components, etc., of a desktop computer2110, laptop computer2120, tablet computer2130, cell phone2140, television2150(or set top box configured to be coupled to a television), wrist watch or other wearable item2160, or otherwise. Other devices are possible and are contemplated. In the illustrated embodiment, the system2100includes at least one instance of SoC100(ofFIG. 1) coupled to an external memory2102. Alternatively, in another embodiment, the system2100includes at least one instance of SoC1300(ofFIG. 13) coupled to an external memory2102.

SoC100is coupled to one or more peripherals2104and the external memory2102. A power supply2106is also provided which supplies the supply voltages to SoC100as well as one or more supply voltages to the memory2102and/or the peripherals2104. In various embodiments, power supply2106may represent a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer). In some embodiments, more than one instance of SoC100may be included (and more than one external memory2102may be included as well).

The peripherals2104may include any desired circuitry, depending on the type of system2100. For example, in one embodiment, peripherals2104may include devices for various types of wireless communication, such as wifi, Bluetooth, cellular, global positioning system, etc. The peripherals2104may also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals2104may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc.

In various embodiments, program instructions of a software application may be used to implement the methods and/or mechanisms previously described. The program instructions may describe the behavior of hardware in a high-level programming language, such as C. Alternatively, a hardware design language (HDL) may be used, such as Verilog. The program instructions may be stored on a non-transitory computer readable storage medium. Numerous types of storage media are available. The storage medium may be accessible by a computer during use to provide the program instructions and accompanying data to the computer for program execution. In some embodiments, a synthesis tool reads the program instructions in order to produce a netlist comprising a list of gates from a synthesis library.