Self-reference sensing for memory cells

Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

BACKGROUND

The following relates generally to memory devices and more specifically to a self-reference sensing scheme for memory cells.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic “1” or a logic “0.” In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored state in the memory device. To store information, the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor. A charged capacitor may, however, become discharged over time through leakage currents, resulting in the loss of the stored information. Certain features of volatile memory may offer performance advantages, such as faster read or write speeds, while features of non-volatile memory, such as the ability to store data without periodic refreshing, may be advantageous.

FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices. Some FeRAM sensing schemes, however, do not account for a variations within a memory cell. This may reduce the reliability of sensing operations of the memory cell.

DETAILED DESCRIPTION

Increased sensing reliability for memory cells may be realized with a sensing scheme that provides a voltage reference that is cell-specific or based on the memory cell selected. By first reading a particular memory cell and generating a reference value based on the read operation, a wider read margin can be attained. As described below, a cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a number of voltages may be applied across a first access line and second access line. The voltages may result in a specific voltage value across both access lines. These voltage values may be used in determining the stored logic state of the memory cell.

By way of example, a capacitor of a memory cell may store a charge representative of a particular logic state—for example, logic “1” or logic “0.” In generating a read signal of the memory cell, a read voltage may be provided to the first of two access lines. The voltage of a second access line may be dependent upon the parasitic capacitance of the second access line. The value across the second access line may then be then provided to a sense amplifier to be used in determining the logic state of the particular ferroelectric memory cell, and potentially for subsequent writing operations.

Subsequently, in generating a voltage reference value, a read voltage may be provided to the second access line. The voltage across the first access line and second access line may be equivalent. This voltage value may then be provided to the sense amplifier. Upon receiving both the read signal and voltage reference value, the sense amplifier is able to better-account for variations within the ferroelectric memory cell. Further, the provided voltage values allow the sense amplifier to more-reliably determine the logic value of the ferroelectric memory cell.

Features of the disclosure introduced above are further described below in the context of a memory array. Circuits and cell characteristics for memory cells and arrays that support a self-referencing sensing scheme are then described. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to a self-referencing sensing scheme.

FIG. 1illustrates examples memory array100that supports a self-referencing sensing scheme in accordance with various embodiments of the present disclosure. Memory array100may also be referred to as an electronic memory apparatus. Memory array100includes memory cells105that are programmable to store different states. Each memory cell105may be programmable to store two states, denoted as a logic “0” and a logic “1.” In some cases, memory cell105may be configured to store more than two logic states. A memory cell105may include a capacitor to store a charge representative of the programmable states; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may commonly use such a design, and the capacitor employed may include a dielectric material with linear electric polarization properties. By contrast, a ferroelectric memory cell may include a capacitor that has a ferroelectric as the dielectric material. Different levels of charge of a ferroelectric capacitor may represent different logic states. Ferroelectric materials have non-linear polarization properties; some details and advantages of a ferroelectric memory cell105are discussed below.

Operations such as reading and writing may be performed on memory cells105by activating or selecting the appropriate word line110and digit line115. Word lines110may also be referred to as access lines, and digit lines115may also be referred to as bit lines. In some examples, an additional line, such as a plate line, may be present. Both word lines110and digit lines115may be referred to as access lines. Activating or selecting a word line110or a digit line115may include applying a voltage to the respective line. Word lines110and digit lines115are made of conductive materials. For example, word lines110and digit lines115may be made of metals (such as copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, or the like.

According to the example ofFIG. 1, each row of memory cells105is connected to a single word line110, and each column of memory cells105is connected to two digit lines115. By activating one word line110and one digit line115(e.g., applying a voltage to the word line110or digit line115), a single memory cell105may be accessed at their intersection. Accessing the memory cell105may include reading or writing the memory cell105. The intersection of a word line110and digit line115may be referred to as an address of a memory cell.

In some architectures, the logic storing device of a cell, e.g., a capacitor, may be electrically isolated from the digit lines by a selection component. The connection to each digit line115may be via a separate switching component (e.g., transistor). The word line110may be connected to and may control the selection components. For example, the first selection component (e.g., selection component220described with reference toFIG. 2) may be a first transistor, the second selection component (e.g., selection component222described with reference toFIG. 2) may be a second transistor, and the word line110may be connected to the gate of each transistor. Thus, cells105may be referred to as two-transistor, one-capacitor cells. Activating the word line110results in an electrical connection or closed circuit between the capacitor of a memory cell105and its corresponding digit line115. The digit line may then be accessed to either read or write the memory cell105.

Accessing memory cells105may be controlled through a row decoder120and a column decoder130. In some examples, a row decoder120receives a row address from the memory controller140and activates the appropriate word line110based on the received row address. Similarly, a column decoder130receives a column address from the memory controller140and activates the appropriate digit line115.

Upon accessing memory cell105, memory cell105may be read, or sensed, by sense component125to determine the stored state of the memory cell105. For example, after accessing the memory cell105, the ferroelectric capacitor of memory cell105may discharge onto its corresponding digit line115. Discharging the ferroelectric capacitor may be based on biasing, or applying a voltage, to the ferroelectric capacitor. The discharging may cause a change in the voltage of the digit line115, which sense component125may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell105. For example, if digit line115has a higher voltage than the reference voltage, then sense component125may determine that the stored state in memory cell105was a logic “1” and vice versa. As described herein, the reference voltage may be generated from the cell105being sensed.

Sense component125may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of memory cell105may then be output through column decoder130as output135. Sense component125may compare a value obtained by applying a first voltage to a first access line with a second value obtained by applying a second voltage to a second access line. This comparison may determine a logic value for a cell105that is based on a reference value that is specific to that cell105. Sense component125may, as described below with reference toFIG. 4, compare a read signal (e.g., read signal330-adescribed with reference toFIG. 3) and a reference value (e.g., reference value335-adescribed with reference toFIG. 3) to determine the logic state of the cell105. The difference between the read signal and the reference value may be related to the difference between the first read voltage and the second read voltage.

Sense component125may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. Sense component125may also include one or more nodes, for example a first node (e.g., node425) and a second node (e.g., node430) as described with reference toFIG. 4. The detected logic state of memory cell105may then be output through column decoder130as output135.

A memory cell105may be set, or written, by activating the relevant word line110and digit line115. As discussed above, activating a word line110electrically connects the corresponding row of memory cells105to their respective digit lines115. By controlling the relevant digit line115while the word line110is activated, a memory cell105may be written—i.e., a logic value may be stored in the memory cell105. Column decoder130may accept data, for example input135, to be written to the memory cells105. A ferroelectric memory cell105may be written by applying a voltage across the ferroelectric capacitor. This process is discussed in more detail below.

As described herein, a memory cell105may be sensed several times. This type of scheme may involve applying a number of voltages across at least a first access line and a second access line. A first read voltage may be applied to a first access line, and a second read voltage may be applied across a second access line. The read voltage applied to the first access line may result in a first voltage across the second access line (e.g., VBlt(0) with reference toFIG. 3) and the read voltage applied to the second access line may result in a second voltage across the first access line (e.g., VBlc(0) with reference toFIG. 3). The read voltages applied across the first access line and the second access line may be representative of a read signal (e.g., read signal330-adescribed with reference toFIG. 3) and a reference value (e.g., reference value335-adescribed with reference toFIG. 3), respectively. The read signal and the reference value may be provided to sense component125for use in determining the logic state of the cell105. This process is discussed in more detail below.

In some memory architectures, accessing the memory cell105may degrade or destroy the stored logic state and re-write or refresh operations may be performed to return the original logic state to memory cell105. In DRAM, for example, the capacitor may be partially or completely discharged during a sense operation, corrupting the stored logic state. So the logic state may be re-written after a sense operation. Additionally, activating a single word line110may result in the discharge of all memory cells in the row; thus, several or all memory cells105in the row may need to be re-written.

Some memory architectures, including DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. With increasingly larger memory arrays, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supplies, heat generation, material limits, etc.), especially for mobile devices that rely on a finite power source, such as a battery. As discussed below, ferroelectric memory cells105may have beneficial properties that may result in improved performance relative to other memory architectures.

As discussed below, ferroelectric memory cells105may have beneficial properties that may result in improved performance relative to other memory architectures. For example, because ferroelectric memory cells tend to be less susceptible to degradation of stored charge, a memory array100that employs ferroelectric memory cells105may require fewer or no refresh operations, and may thus require less power to operate. Additionally, employing sensing schemes described herein in which a number of voltages are applied to a number of access lines to generate a read signal and a reference value may allow for a wider read margin to be attained.

The memory controller140may control the operation (e.g., read, write, re-write, refresh, etc.) of memory cells105through the various components, such as row decoder120, column decoder130, and sense component125. Memory controller140may generate row and column address signals in order to activate the desired word line110and digit line115. Memory controller140may also generate and control various voltage potentials used during the operation of memory array100. In general, the amplitude, shape, or duration of an applied voltage discussed herein may be adjusted or varied and may be different for the various operations for operating memory array100. Furthermore, one, multiple, or all memory cells105within memory array100may be accessed simultaneously; for example, multiple or all cells of memory array100may be accessed simultaneously during a reset operation in which all memory cells105, or a group of memory cells105, are set to a single logic state.

FIG. 2illustrates examples circuit200that supports a self-referencing sensing scheme in accordance with various embodiments of the present disclosure. Circuit200includes a memory cell105-a, word lines110, digit lines115, and sense component125-a, which may be examples of a memory cell105, word line110, digit line115, and sense component125, respectively, described with reference toFIG. 1. Memory cell105-amay include a logic storage component, such as capacitor205that has a first plate, cell plate230, and a second plate, cell bottom215. Cell plate230and cell bottom215may be capacitively coupled through a ferroelectric material positioned between them. The orientation of cell plate230and cell bottom215may be flipped without changing the operation of memory cell105-a. Circuit200also includes first selection component220, second selection component222. In some instances, only one of first selection component220and selection component222may be present. Cell plate230and cell bottom215may be accessed via digit lines115-band115-a, respectively, and sense component125-amay compare, for example, the read signal (e.g., read signal330-adescribed with reference toFIG. 3) and reference value (e.g., reference value335-adescribed with reference toFIG. 3). As described above, various states may be stored by charging or discharging capacitor205.

The stored state of capacitor205may be read or sensed by operating various elements represented in circuit200. Capacitor205may be in electronic communication with digit lines115. For example, capacitor205can be isolated from digit line115-awhen first selection component220is deactivated, and capacitor205can be connected to digit line115-awhen first selection component220is activated. Activating first selection component220and second selection component222may be referred to as selecting memory cell105-a. In some cases, first selection component220and second selection component222are transistors and their operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. Word line110-amay activate first selection component220or second selection component222, or both; for example, a voltage applied to word line110-ais applied to the transistor gate, connecting capacitor205with digit line115-b.

Due to the ferroelectric material between the plates of capacitor205, and as discussed in more detail below, capacitor205may not discharge upon connection to digit line115-a. In one scheme, to sense the logic state stored by ferroelectric capacitor205, word line110-amay be biased to select memory cell105-aand a voltage may be applied to digit line115-b. In some cases, digit line115-ais virtually grounded and then isolated from the virtual ground, which may be referred to as “floating,” prior to biasing digit line115-band word line110-a. Biasing digit line115-bmay result in a voltage difference (e.g., digit line115-bvoltage minus digit line115-avoltage) across capacitor205. The voltage difference may yield a change in the stored charge on capacitor205, where the magnitude of the change in stored charge may depend on the initial state of capacitor205—e.g., whether the initial state stored a logic “1” or a logic “0.” This may cause a change in the voltage of digit line115-abased on the charge stored on capacitor205. The operations of digit lines115-aand115-bmay be reversed to chase capacitor205to discharge onto digit line115-b. As described herein, accessing a cell105-avia digit line115-aand115-bin alternating fashion may be employed in a self-reference sensing scheme.

The change in voltage of digit line115-amay depend on its intrinsic capacitance. That is, as charge flows through digit line115-a, some finite charge may be stored in digit line115-aand the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical characteristics, including the dimensions, of digit line115-a. Digit line115-amay connect many memory cells105so digit line115-amay have a length that results in a non-negligible capacitance (e.g., on the order of picofarads (pF)). The resulting voltage of digit line115-amay then be compared to a reference value by sense component125-ain order to determine the stored logic state in memory cell105-a. For example, the reference value may be obtained from digit line115-bby accessing the memory cell105via digit line115-a. Other sensing processes may be used.

Sense component125-amay include various transistors or amplifiers to detect and amplify a difference in signals, which may be referred to as latching. Sense component125-amay include a plurality of inverters. Sense component125-amay also include a sense amplifier that receives and compares the voltage of digit line115-aand a reference voltage, which may be referred to as a reference value.

Additionally or alternatively, sense component125-amay compare, for example, the read signal (e.g., read signal330-adescribed with reference toFIG. 3) and reference value (e.g., reference value335-adescribed with reference toFIG. 3). The sense amplifier output may be driven to the higher (e.g., a positive) or lower (e.g., negative or ground (GND)) read voltage based on the comparison. Stated alternatively, the read voltage may be representative of the upper and lower-most values of a sense amplifier swing (e.g., Vccor GND). For instance, if digit line115-ahas a higher voltage than the reference voltage, then the sense amplifier output may be driven to a positive read voltage. In some cases, the sense amplifier may additionally drive digit line115-ato the read voltage. Sense component125-amay then latch the output of the sense amplifier and/or the voltage of digit line115-a, which may be used to determine the stored state in memory cell105-a, e.g., logic “1.” Alternatively, if digit line115-ahas a lower voltage than reference voltage, the sense amplifier output may be driven to a negative or ground voltage. Sense component125-amay similarly latch the sense amplifier output to determine the stored state in memory cell105-a, e.g., logic “0.” The latched logic state of memory cell105-amay then be output, for example, through column decoder130as output135with reference toFIG. 1.

To write memory cell105-a, a voltage may be applied across capacitor205. Various methods may be used. In one example, first selection component220may be activated through word line110-bin order to electrically connect capacitor205to digit line115-a. A voltage may be applied across capacitor205by controlling the voltage of cell plate230(through digit line115-b) and cell bottom215(through digit line115-a). To write a logic “0,” cell plate230may be taken high, that is, a positive voltage may be applied to digit line115-b, and cell bottom215may be taken low, e.g., virtually grounding or applying a negative voltage to digit line115-a. The opposite process is performed to write a logic “1,” where cell plate230is taken low and cell bottom215is taken high.

FIG. 3illustrates examples of non-linear electrical properties with hysteresis curves300-aand300-bfor a ferroelectric memory cell that is operated in accordance with various embodiments of the present disclosure. Hysteresis curves300-aand300-billustrate writing and reading processes, respectively. Hysteresis curves300-aand300-bdepict the charge, Q, stored on a ferroelectric capacitor (e.g., capacitor205ofFIG. 2) as a function of a voltage difference, V.

A ferroelectric material is characterized by a spontaneous electric polarization, i.e., it maintains a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electric polarization within a ferroelectric capacitor results in a net charge at the ferroelectric material's surface and attracts opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization may be maintained in the absence of an externally applied electric field for relatively long times, even indefinitely, charge leakage may be significantly decreased as compared with, for example, capacitors employed in DRAM arrays. This may reduce the need to perform refresh operations as described above for some DRAM architectures.

Hysteresis curves300-aand300-bmay be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Likewise, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. Additionally, it should be understood that the voltages in hysteresis curves300represent a voltage difference across the capacitor and are directional. For example, a positive voltage may be realized by applying a positive voltage to the terminal in question (e.g., a cell plate230, as shown inFIG. 2) and maintaining the second terminal (e.g., a cell bottom215, as shown inFIG. 2) at ground (or approximately zero volts (0V)). A negative voltage may be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal—i.e., positive voltages may be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage difference shown in hysteresis curves300.

As depicted in hysteresis curve300-a, the ferroelectric material may maintain a positive polarization with a zero voltage difference, resulting in possible charge state305-a. According to the example ofFIG. 3, charge state305-arepresents a logic “0.” In some examples, the logic values of the respective charge states may be reversed to accommodate other schemes for operating a memory cell.

As depicted in hysteresis curve300-b, the ferroelectric material may maintain a negative polarization with a zero voltage difference, resulting in possible charge state305-b. According to the example ofFIG. 3, charge state305-brepresents a logic “1.” In some examples, the logic values of the respective charge states may be reversed to accommodate other schemes for operating a memory cell.

A logic “0” or “1” may be written to the memory cell by controlling the electric polarization of the ferroelectric material, and thus the charge on the capacitor terminals, by applying voltage. For example, applying a net positive voltage across the capacitor results in charge accumulation until charge state310-ais reached. Upon removing the voltage, charge state310-afollows the path depicted by hysteresis curve300-auntil it reaches charge state315-aat zero voltage potential. Similarly, charge state320-ais written by applying a net negative voltage to a capacitor. After removing the net negative voltage, a positive voltage is again applied, and charge state320-afollows a path until it reaches charge state325-a. Charge states305-aand305-bmay also be referred to as the remnant polarization (Pr) values, i.e., the polarization (or charge) that remains upon removing the external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero.

To read, or sense, the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge, Q, changes, and the degree of the change depends on the initial charge state—i.e., the final stored charge (Q) depends on whether charge state305-aor305-bwas initially stored. Voltage may be applied across the capacitor as discussed with reference toFIG. 2. For example, in response to voltage, charge state305-amay follow a specific path. Additionally, for example, if charge state305-bwas initially stored, then it follows a specific path. The final position of charge state depends on a number of factors, including the specific sensing scheme and circuitry.

As depicted in hysteresis curve300-a, a voltage (e.g.,VBlt(0)) may be applied to a first access line, resulting in charge state310-a). This step may represent generating a read signal330-a, wherein the voltage depends on the logic state of the cell. Subsequently, the cell may be reset to zero (0V) and the charge state passes from310-ato315-a. Upon reaching charge state315-a, a net negative voltage (e.g.,VBlc(0) may be applied to a second access line, resulting in charge state320-a). This step may represent generating a reference value335-aof the particular memory cell. A voltage may then be re-applied to the memory cell, resulting in charge state325-a. This step may represent writing a logic value to the cell. After the operation is completed (e.g., at charge state325-a), the charge state of the cell may return to charge state305-a.

Similarly, as depicted in hysteresis curve300-b, a voltage (e.g.,VBlt(1)) may be applied to a first access line, resulting in charge state310-b). This step may represent generating a read signal330-b, wherein the voltage depends on the logic state of the cell. Subsequently, the cell may be reset to zero (0V) and the charge state passes from310-bto315-b. Upon reaching charge state315-b, a net negative voltage (e.g.,VBlc(1)) may be applied to a second access line, resulting in charge state320-b). This step may represent generating a reference value335-bof the particular memory cell. A net negative voltage may be again-applied to the memory cell, resulting in charge state325-b. This step may represent writing a logic value to the cell. After the operation is completed (e.g., at charge state325-b), the charge state of the cell may return to charge state305-b.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if the capacitor is electrically connected to the digit line and voltage is applied, the voltage of the digit line may rise due to its intrinsic capacitance. So a voltage measured at a sense component may not equal the voltage and instead may depend on the voltage of the digit line. The position of final charge states on hysteresis curves300-aand300-bmay thus depend on the capacitance of the digit line and may be determined through a load-line analysis. As a result, the voltage of the capacitor may be different and may depend on the initial state of the capacitor. For example, a voltage (e.g., VBlt(0) or VBlt(1)) may develop across capacitor205when a same voltage is applied to a first access line. Similarly, for example, a voltage (e.g., VBlc(0) or VBlc(1)) may develop across capacitor205when applying a same voltage to a second access line.

By comparing the read signal to the reference value, the initial state of the capacitor may be determined. Upon comparison by the sense component, the read signal may be determined to be higher or lower than the reference value, and the stored logic value of the ferroelectric memory cell (i.e., a logic “0” or “1”) may be determined.

As discussed above, reading a memory cell that does not use a ferroelectric capacitor may degrade or destroy the stored logic state. A ferroelectric memory cell, however, may maintain the initial logic state after a read operation. For example, if charge state305-bis stored, the charge state may follow a specific path during a read operation and, after removing voltage, the charge state may return to initial charge state305-bby following a path in the opposite direction.

FIG. 4illustrates examples circuit400that supports a self-referencing sensing scheme in accordance with examples of the present disclosure. Circuit400includes first voltage source415and second voltage source420, and virtual ground435and440, which may each include switching components. Additionally, circuit400includes switching components445,450,455, and460and nodes425and430. In some examples, switching components445,450,455, and460may be transistors. Additionally, circuit400may include first selection component220-a, second selection component222-a, memory cell105-b, word line110-c, digit lines115-cand115-d, cell plate230-a, cell bottom215-b, and capacitor205-b, which may be examples of corresponding components described with reference toFIG. 2. Ferroelectric memory cell105-bmay be selected using selection component220-aand selection component222-athat are in electronic communication with ferroelectric capacitor205-a. For example, selection component220-aand selection component222-amay be a transistor (e.g., a FET) and may be activated by a voltage applied to a gate of a transistor using word line110-c.

As depicted inFIG. 4, read voltage415may be applied to a first access line, such as digit line115-c, based on selecting ferroelectric memory cell105-a. Upon applying read voltage415, a voltage (e.g., VBlt(0)) may develop across a second access line, e.g., digit line115-d. This voltage may depend on the charge state with respect to read voltage415. In some examples, this voltage may result from a capacitive sharing between ferroelectric memory cell105-aand the second access line. The voltage value across the second access line (e.g., read signal330-awith reference toFIG. 3) may be sampled to a latch (e.g., sense component125-b) at node425. After sampling the voltage value to the latch at node425, node425may be isolated. Similarly, read voltage420may be applied to the second access line, e.g., digit line115-d, based on selecting ferroelectric memory cell105-a. In some examples, read voltage415and read voltage420may be a same read voltage. Before applying read voltage420, the first access line and second access line (e.g., digit lines115) may be reset to zero (0V)—i.e., grounded—by connecting virtual ground435and/or virtual ground440. When grounded, the memory cell105-amay have a residual polarization due to applying read voltage415. After grounding the access lines, read voltage420may be applied to second access line. Upon applying read voltage420, a voltage (e.g., VBlc(0)) may develop across the first access line, e.g., digit line115-c. This voltage may depend on the charge state with respect to read voltage420. In some examples, this voltage may result from a capacitive sharing between ferroelectric memory cell105-aand the first access line. Read voltage420may, for example, result in the voltage across the first access line being correlated to the residual polarization of memory cell105-a. Upon applying read voltage420, the voltage across first access line may be equivalent to the voltage across the second access line. This voltage value (e.g., reference value335-aofFIG. 3) may be sampled to a latch at node430. After sampling the voltage value to the latch at node430, node430may be isolated. A logic value may then be written to the ferroelectric memory cell.

Additionally, for example, the first voltage across the second access line (e.g., VBlt(0)) and the second voltage across the first access line may be equivalent (e.g., VBlc(0)). A value of read voltage415and read voltage420may be selected based upon this determination. The value of read voltage415and read voltage420may be selected to create an offset in a comparison of the first voltage across the second access line (e.g., VBlt(0)) and the second voltage across the first access line (e.g., VBlc(0)).

Additionally or alternatively, for example, a first read voltage source and a second read voltage source may supply read voltage415read voltage420. In some examples, read voltage415and read voltage420may be a same voltage. In such examples, read voltage420may be the same as read voltage415and the first and second read voltage sources may be the same voltage source. In other examples, the first read voltage source and the second read voltage source may supply different voltages. In such cases, read voltage420may be a higher voltage or a lower voltage than the read voltage415. Thus the position on a hysteresis curve of the memory cell's states during the first portion of the access operation (e.g.,310-aor310-b) and during the second portion of the access operation (e.g.,320-aor320-b) may vary. For example, voltage VBlt(0) and VBlc(0) may be offset. Reading performances may be obtained in case of an equivalent or substantially equivalent difference between a sensed value (e.g., VBlt(0) or VBlt(1)) and corresponding reference value (e.g., VBlc(0) or VBlc(1)). In some examples, the value of read voltage415and read voltage420may be selected to create an offset in a comparison of the first voltage across the second access line (e.g., VBlt(0) or VBlt(1)) and the second voltage across the first access line (e.g., VBlc(0) or VBlc(1)).

Additionally,FIG. 4depicts switching components445,450,455, and460, which may be opened or closed to facilitate access to nodes425or430, first access line, and second access line. For example, when applying first read voltage415to first access line, switching component460may be open, while switching component455may be closed. Further, for example, when applying a voltage value to node425, node425may be isolated by closing switching component450and opening switching component460. Additionally or alternatively, for example, node425may be isolated by opening switching component450, only. Similarly when applying a voltage value to node430, node430may be isolated by closing switching component460and opening switching component450. Additionally or alternatively, for example, node430may be isolated by opening switching component460, only. Upon supplying voltage values to nodes425and430, sense component125-bmay be operated to latch a logic value stored in memory cell105-b. This operation may, for example, increase the voltage values applied to nodes425and430and may facilitate writing the logic value back to memory cell105-b.

FIG. 5shows a block diagram500of a memory array100-athat supports self-referencing for ferroelectric memory in accordance with examples of the present disclosure. Memory array100-amay be referred to as an electronic memory apparatus, and may be an example of a component of a memory controller140-aas described with reference toFIG. 1.

Memory array100-amay include one or more memory cells105-c, a memory controller140-a, a word line110-d, a reference component520, a sense component125-c, digit lines115-eand115-f, and a latch525. These components may be in electronic communication with each other and may perform one or more of the functions described herein. In some cases, memory controller140-amay include biasing component510and timing component515. Memory controller140-amay be in electronic communication with word line110-d, digit lines115, and sense component125-c, which may be examples of word line110, digit line115, and sense component125, described with reference toFIGS. 1 and 2. In some cases, reference component520, sense component125-c, and latch525may be components of memory controller140-a.

In some examples, digit lines115-eand115-fare in electronic communication with sense component125-cand a ferroelectric capacitor (e.g., capacitor205-aofFIG. 4) of ferroelectric memory cell105-c. Ferroelectric memory cell105-cmay be writable with a logic state (e.g., a first or second logic state). Word line110-dmay be in electronic communication with memory controller140-aand a selection component of ferroelectric memory cell105-c. Sense component125-cmay be in electronic communication with memory controller140-a, digit lines115, latch525. Reference component520may be in electronic communication with digit lines115. These components may also be in electronic communication with other components, both inside and outside of memory array100-a, in addition to components not listed above, via other components, connections, or busses.

Memory controller140-amay be configured to activate word line110-dor digit lines115by applying voltages to those various nodes. For example, biasing component510may be configured to apply a voltage to operate memory cell105-cto read or write memory cell105-cas described above. In some cases, memory controller140-amay include a row decoder, column decoder, or both, as described with reference toFIG. 1. This may enable memory controller140-ato access memory cell105-c. Biasing component510may also provide voltages to reference component520in order to generate a self-reference signal for sense component125-c. For example, biasing component510may provide different read voltages to sense component125-cvia reference component520. Additionally, biasing component510may provide voltages for the operation of sense component125-c.

In some cases, memory controller140-amay perform its operations using timing component515. For example, timing component515may control the timing of the various word line selections or plate biasing, including timing for switching and voltage application to perform the memory functions, such as reading and writing, discussed herein. In some cases, timing component515may control the operations of biasing component510.

Reference component520may include various components to generate a self-reference signal for sense component125-c. Reference component520may include circuitry, including various switching components to apply voltages to or to ground digit lines115. In some examples, reference component520may be in electronic communication with sense component125-c. Sense component125-cmay compare a signal from memory cell105-c(through digit line115-c) with a reference signal from reference component520.

Upon determining the logic state, the sense component may then store the output in latch525, where it may be used in accordance with the operations of an electronic device that memory array100-ais a part. Sense component125-cmay include a sense amplifier in electronic communication with the latch525and the ferroelectric memory cell. For example, latch525may be in electronic communication with the first access line and second access line via a plurality of switching components (as shown inFIG. 4, for example).

The latch525may be in electronic communication with the first access line (e.g., digit line115-e) via a first switching component and also in electronic communication with the second access line (e.g., digit line115-f) via a second switching component. Further, a first voltage source may be in electronic communication with both the first access line and the latch via a third switching component. A second voltage source may be in electronic communication with both the second access line and the latch via a fourth switching component. Additionally, the first access line may be in electronic communication with a virtual ground via a fifth switching component and the second access line may be in electronic communication with a virtual ground via a sixth switching component. Latch525may be in further electronic communication with the first access line at a first node and be in electronic communication with the second access line at a second node. The first node and the second node may be in electronic communication via a seventh switching component. The various switching components described with reference toFIG. 5may be within sense component125-c; though not shown, such switching components may perform similar functions as those describe with reference toFIG. 4

Memory controller140-aand/or at least some of its various sub-components may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of the memory controller140-aand/or at least some of its various sub-components may be executed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. The memory controller140-aand/or at least some of its various sub-components may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical devices. In some examples, memory controller140-aand/or at least some of its various sub-components may be a separate and distinct component in accordance with examples of the present disclosure. In other examples, memory controller140-aand/or at least some of its various sub-components may be combined with one or more other hardware components, including but not limited to a receiver, a transmitter, a transceiver, one or more other components described in the present disclosure, or a combination thereof in accordance with examples of the present disclosure.

Memory controller140-amay be in electronic communication with the first access line (e.g., digit line115-e), second access line (digit line115-d), and sense component125—to control a first switching component, second switching component, third switching component, fourth switching component, fifth switching component, sixth switching component, and seventh switching component. For example, memory controller140-amay apply a first read voltage to the first access line during a first portion of an access operation. After applying the first read voltage, memory controller140-amay then apply a second read voltage to the second access line during a second portion of the access operation. Subsequently, memory controller140-amay compare a first voltage of the first access line to a second voltage of the second access line during a third portion of the access operation, wherein the first voltage is based at least in part on the first read voltage and the second voltage is based at least in part on the second read voltage. Memory controller140-amay determine a logic value associated with the ferroelectric memory cell based at least in part on comparing the first voltage of the first access line and the second voltage of the second access line.

FIG. 6shows a diagram of a system600including a device605that supports self-referencing for ferroelectric memory in accordance with examples of the present disclosure. Device605may include memory controller140-b, which may be an example of memory controller140as described above with reference toFIG. 1. Device605may include components for bi-directional voice and data communications including components for transmitting and receiving communications, memory array100-bthat includes memory controller140-band memory cells105-d, basic input/output system (BIOS) component615, processor610, I/O controller625, and peripheral components620. These components may be in electronic communication via one or more busses (e.g., bus630). Memory cells105-dmay store information (i.e., in the form of a logical state) as described herein.

BIOS component615may be a software component that includes BIOS operated as firmware, which may initialize and run various hardware components. BIOS component615may also manage data flow between a processor and various other components, e.g., peripheral components, input/output control component, etc. BIOS component615may include a program or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

I/O controller625may manage input and output signals for device605. I/O controller625may also manage peripherals not integrated into device605. In some cases, I/O controller625may represent a physical connection or port to an external peripheral. In some cases, I/O controller625may utilize an operating system such as iOS®, ANDROID®, MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, or another known operating system.

Peripheral components620may include any input or output device, or an interface for such devices. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

Input635may represent a device or signal external to device605that provides input to device605or its components. This may include a user interface or an interface with or between other devices. In some cases, input635may be managed by I/O controller625, and may interact with device605via a peripheral component620.

Output640may also represent a device or signal external to device605configured to receive output from device605or any of its components. Examples of output640may include a display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, output640may be a peripheral element that interfaces with device605via peripheral component(s)620. In some cases, output640may be managed by I/O controller625

The components of device605may include circuitry designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry out the functions described herein. Device605may be a computer, a server, a laptop computer, a notebook computer, a tablet computer, a mobile phone, a wearable electronic device, a personal electronic device, or the like. Or device605may be a portion or component of such a device.

FIG. 7shows a flowchart illustrating a method700for a self-referencing sensing scheme in accordance with examples of the present disclosure. The operations of method700may be implemented by memory controller140-adescribed with reference toFIG. 5or its components as described herein. In some examples, a memory controller may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller may perform some or all of the functions described below using special-purpose hardware.

At block705, method700may include applying a first read voltage to a first access line of a ferroelectric memory cell during a first portion of an access operation. The operations of block705may be implemented by memory controller140-aor biasing component510described with reference toFIG. 5.

At block710, method700may include applying a second read voltage to a second access line of the ferroelectric memory cell during a second portion of the access operation. The operations of block710may be implemented by memory controller140-aor biasing component510described with reference toFIG. 5.

In some examples, the method may also include grounding or virtually grounding the first access line and the second access line after applying the first read voltage, wherein the second read voltage is applied after the grounding or virtual grounding. In some examples, a third voltage of the second access line during the first portion of the access operation is based at least in part on a polarization of the ferroelectric memory cell. In some examples, a fourth voltage of the first access line during the second portion of the access operation is based at least in part on a polarization of the ferroelectric memory cell. In some examples, a fourth voltage of the first access line during the second portion of the access operation is less than the third voltage of the second access line. In other examples, a fourth voltage of the first access line during the second portion of the access operation may be greater than the third voltage of the second access line.

At block715, method700may include comparing a first voltage of the second access line to a second voltage of the first access line, during a third portion of the access operation, wherein the first voltage is based at least in part on the application of the first read voltage and the second—read voltage is based at least in part on the application of the second read voltage. The operations of block715may be implemented by memory controller140-aor biasing component510described with reference toFIG. 5.

At block720, method700may include determining a logic value associated with the ferroelectric memory cell based at least in part on comparing the first voltage of the second access line and the second voltage of the first access line. The operations of block720may be implemented by memory controller140-aor biasing component510described with reference toFIG. 5. The method may also include writing the logic value to the ferroelectric memory cell during a fourth portion of the access operation. In some examples, the method may include a write back operation in which a cell is returned to a pre-sensing charge representative of the stored state.

FIG. 8shows a flowchart illustrating a method800for a self-referencing scheme in accordance with examples of the present disclosure. The operations of method800may be implemented by memory controller140-adescribed with reference toFIG. 5or its components as described herein. In some examples, a memory controller may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller may perform some or all of the functions described below using special-purpose hardware.

At block805, method800may include activating a first switching component that is coupled between a first read voltage and a first access line. The operations of block805may be implemented by memory controller140-aor biasing component510described with reference toFIG. 5.

At block810, method800may include sensing a value representative of a first state associated with a ferroelectric memory cell at a second access line after activating the first switching component. The operations of block810may be implemented by memory controller140-aor sense component125-cdescribed with reference toFIG. 5.

At block815, method800may include activating a second switching component that is coupled between a second read voltage and the second access line after sensing the first state. In some examples, the first read voltage source and the second read voltage source may be a same voltage source. Additionally or alternatively, for example, the second read voltage source may be a different voltage source than the first read voltage source. The operations of block815may be implemented by memory controller140-aor biasing component510described with reference toFIG. 5.

At block820, method800may include generating a reference value based at least in part on activating the second switching component. The operations of block820may be implemented by memory controller140-aor reference component520described with reference toFIG. 5.

At block825, method800may include determining a logic value stored at the ferroelectric memory cell, wherein the logic value is based at least in part on comparing the value representative of the first state of the ferroelectric memory cell and the reference value. The operations of block825may be implemented by memory controller140-aor sense component125-cdescribed with reference toFIG. 5.

It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, some or all of the steps from two or more of the methods may be combined.

As used herein, the term “virtual ground” refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly connected with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. “Virtual grounding” or “virtually grounded” means connected to approximately 0V.

The terms “electronic communication” and “coupled” refer to a relationship between components that supports electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication or coupled to one another may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

The term “isolated” refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

As used herein, the term “shorting” refers to a relationship between components in which a conductive path is established between the components via the activation of a single intermediary component between the two components in question. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables the flow of charge between components (or lines) that are in electronic communication.