Ceramic electronic component and method of manufacturing the same

A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first ceramic dielectric layers having a first width in a first direction in which side faces of the multilayer chip are opposite to each other, the second multilayer structure including second internal electrode layers having a second width less than the first width in the first direction, and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein main components of the first and second internal electrode layers differ from a main component of the external electrodes.

FIELD

A certain aspect of the present disclosure relates to a ceramic electronic component and a method of manufacturing the same.

BACKGROUND

The capacitance of multilayer ceramic capacitors is increasing, and the replacement of electrolytic capacitors with the multilayer ceramic capacitors is progressing. Therefore, the demand for large, high-capacitance multilayer ceramic capacitors is increasing as disclosed in, for example, Japanese Patent Application Publication Nos. 2019-110158 and 2014-241453.

RELATED ART DOCUMENTS

Patent Documents

Japanese Patent Application Publication No. 2019-110158

Japanese Patent Application Publication No. 2014-241453

SUMMARY OF THE INVENTION

The multilayer ceramic capacitor has a capacitance section where internal electrode layers are stacked with dielectric layers interposed therebetween, and side margin sections protecting respective lateral ends of the internal electrode layers. The large, high-capacitance multilayer ceramic capacitor has a large number of the internal electrode layers that are stacked, and therefore, is heavy. Thus, even when the multilayer ceramic capacitor is dropped from a slight height during manufacturing or mounting, the impact may cause cracks in the multilayer ceramic capacitor, resulting in deterioration in the moisture resistance.

In addition, as the internal electrode layers become thinner and more stacked to achieve high capacitance, the difference between the shrinkage of the capacitance section and the shrinkage of the side margin section during firing becomes larger, and cracks are more likely to occur. In addition, thicker cover layers, which protect the capacitance section, have a lower capability to follow the shrinkage, and increase a risk of occurrence of cracks in the cover layers.

Furthermore, during baking of the external electrodes, the main component metal of the external electrode and the main component metal of the internal electrode layer interdiffuse, causing the internal electrode layer to expand. This may result in occurrence of cracks. To ensure the reliability, the temperature at which the external electrodes are baked (hereinafter, referred to as baking temperature) is preferably high. However, as the baking temperature of the external electrodes increases, the diffusion length of the main component metal of the external electrode increases, resulting in increase in possibility of occurrence of cracks. Since these cracks occur in the locations further in than the external electrode, they are not observed from the outside, resulting in reduced reliability.

The present disclosure has an objective of providing a ceramic electronic component and a method of manufacturing the same capable of reducing occurrence of cracks.

In one aspect of the present disclosure, there is provided a ceramic electronic component including: a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first dielectric layers and first internal electrode layers that are alternately stacked, the second multilayer structure including second dielectric layers and second internal electrode layers that are alternately stacked, the first and second dielectric layers being mainly composed of ceramic, the first internal electrode layers being formed so as to be alternately exposed to two edge faces opposite to each other of the multilayer chip, the second internal electrode layers being formed so as to be alternately exposed to the two edge faces; and a pair of external electrodes formed from the respective two edge faces to at least one of side faces of the multilayer chip, wherein a main component of the first internal electrode layer and a main component of the second internal electrode layer differ from a main component of the external electrode, wherein a width of the first internal electrode layer in a first direction orthogonal to a second direction and a third direction is greater than a width of the second internal electrode layer in the first direction, the second direction being a direction in which the first dielectric layers and the first internal electrode layers are stacked, the third direction being a direction in which the two edge faces are opposite to each other, wherein in a first capacitance section where adjacent first internal electrode layers connected to different external electrodes are opposite to each other, the number of the first internal electrode layers per 1 mm of height in the second direction is 500 or greater, wherein in a second capacitance section where adjacent second internal electrode layers connected to different external electrodes are opposite to each other, the number of the second internal electrode layers per 1 mm of height in the second direction is 500 or greater.

In the above ceramic electronic component, a ratio of the width of the second internal electrode layer in the first direction to the width of the first internal electrode layer in the first direction may be 0.5 to 0.75.

In the above ceramic electronic component, a ratio of the width of the second internal electrode layer in the first direction to the width of the first internal electrode layer in the first direction may be 0.55 to 0.70.

In the above ceramic electronic component, a ratio of the width of the second internal electrode layer in the first direction to the width of the first internal electrode layer in the first direction may be 0.60 to 0.65.

In the above ceramic electronic component, in a cross-section orthogonal to the third direction, in each of ridge portions, a shortest distance among distances between the ridge portion and the first internal electrode layers and distances between the ridge portion and the second internal electrode layers may be 10 μm or greater, the ridge portions including first ridge portions each connecting the top face of the multilayer chip and a corresponding one of two side faces of the multilayer chip and second ridge portions each connecting the bottom face of the multilayer chip and a corresponding one of the two side faces of the multilayer chip.

In the above ceramic electronic component, 300 to 950 of the first internal electrodes may be included in the first multilayer structure, and 50 to 500 of the second internal electrodes may be included in the second multilayer structure.

In the above ceramic electronic component, the multilayer chip has a length of 1.6 mm or greater, a width of 0.8 mm or greater, and a height of 0.8 mm or greater.

In the above ceramic electronic component, a main component of the first internal electrode layer and a main component of the second internal electrode layer may be nickel, and a main component of the external electrode may be copper.

In the above ceramic electronic component, a thickness of the dielectric layer is 1 μm or less.

In another aspect of the present disclosure, there is provided a method of manufacturing a ceramic electronic component, including: preparing a ceramic multilayer structure including a first multilayer portion and a second multilayer portion disposed on each of top and bottom faces of the first multilayer portion, the first multilayer portion including first ceramic dielectric green sheets and first patterns of metal conductive pastes that are alternately stacked so that the first patterns are exposed to two edge faces opposite to each other of the first multilayer portion, the second multilayer portion including second ceramic dielectric green sheets and second patterns of metal conductive pastes that are alternately stacked so that the second patterns are exposed to two edge faces opposite to each other of the second multilayer portion; obtaining a multilayer chip by firing the ceramic multilayer structure, the multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a second multilayer structure disposed on each of top and bottom faces of the first multilayer structure, the first multilayer structure including first dielectric layers and first internal electrode layers that are alternately stacked, the second multilayer structure including second dielectric layers and second internal electrode layers that are alternately stacked, the first internal electrode layers being formed so as to be alternately exposed to two edge faces opposite to each other of the multilayer chip, the second internal electrode layers being formed so as to be alternately exposed to the two edge faces; applying a metal paste from each of the two edge faces of the multilayer chip to at least one of side faces of the multilayer chip; and baking the metal pastes to form external electrodes, wherein a width of the first internal electrode layer in a first direction orthogonal to a second direction and a third direction is greater than a width of the second internal electrode layer in the first direction, the second direction being a direction in which the first dielectric layers and the first internal electrode layers are stacked, the third direction being a direction in which the two edge faces are opposite to each other, wherein in a first capacitance section where adjacent first internal electrode layers connected to different external electrodes are opposite to each other, the number of the first internal electrode layers per 1 mm of height in the second direction is 500 or greater, wherein in a second capacitance section where adjacent second internal electrode layers connected to different external electrodes are opposite to each other, the number of the second internal electrode layers per 1 mm of height in the second direction is 500 or greater.

DETAILED DESCRIPTION

Hereinafter, a description will be given of an embodiment with reference to the accompanying drawings.

Embodiment

FIG.1is a partial cross-sectional perspective view of a multilayer ceramic capacitor100in accordance with an embodiment.FIG.2is a cross-sectional view taken along line A-A inFIG.1.FIG.3AandFIG.3Bare cross-sectional views taken along line B-B inFIG.1. As illustrated inFIG.1toFIG.3B, the multilayer ceramic capacitor100includes a multilayer chip10having a substantially rectangular parallelepiped shape, and external electrodes20aand20bdisposed on respective edge faces opposite to each other of the multilayer chip10. Among four faces other than the two edge faces of the multilayer chip10, the faces other than the top face and the bottom face in the stack direction (a second direction) are referred to as side faces. The stack direction is a direction in which dielectric layers11and internal electrode layers12, which are described later, are alternately stacked. Each of the external electrodes20aand20bextends from the corresponding edge face to the top and bottom faces in the stack direction and the two side faces of the multilayer chip10. However, the external electrodes20aand20bare spaced from each other.

The multilayer chip10has a multilayer structure designed to have the dielectric layers11and the internal electrode layers12alternately stacked. The dielectric layer11contains a ceramic material functioning as a dielectric substance. End edges of the internal electrode layers12are alternately exposed to a first edge face of the multilayer chip10and a second edge face of the multilayer chip10. The external electrode20ais disposed on the first edge face, while the external electrode20bis disposed on the second edge face. Therefore, the internal electrode layers12are alternately electrically connected to the external electrode20aand the external electrode20b. The outermost layers of the multilayer chip10in the stack direction are cover layers13. The cover layer13is mainly composed of a ceramic material. For example, the main component material of the cover layer13is identical to the main component material of the dielectric layer11.

As illustrated inFIG.3AandFIG.3B, in the multilayer ceramic capacitor100, the widths of the internal electrode layers12are changed with two stepped levels in a direction (a first direction) orthogonal to the stack direction and a direction (a third direction) in which the two edge faces are opposite to each other. Hereinafter, the direction in which the two edge faces are opposite to each other is referred to as the facing direction of the two edge faces, and the direction orthogonal to the stack direction and the facing direction of the two edge faces is referred to as an orthogonal direction. As illustrated inFIG.3A, the internal electrode layers12include first internal electrode layers12aand second internal electrode layers12b. As illustrated inFIG.3B, the width W2of the second internal electrode layer12bis less than the width of W1of the internal electrode layer12ain the orthogonal direction.

The first internal electrode layers12aare included in a first multilayer structure in which the first internal electrode layers12aand the dielectric layers11are alternately stacked, while the second internal electrode layers12bare included in a second multilayer structure in which the second internal electrode layer12band the dielectric layers11are alternately stacked. Therefore, in the multilayer ceramic capacitor100, the multilayer structure in which the dielectric layers11and the internal electrode layers12are alternately stacked has a structure designed to have the second multilayer structure, the first multilayer structure, and the second multilayer structure stacked in this order from the bottom in the stack direction. That is, the second multilayer structures are disposed on the top and bottom faces of the first multilayer structure in the stack direction.

The multilayer ceramic capacitor100may have a length of 1.6 mm, a width of 0.8 mm, and a height of 0.8 mm. The multilayer ceramic capacitor100may have a length of 2.0 mm, a width of 1.2 mm, and a height of 1.2 mm. The multilayer ceramic capacitor100may have a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm. The multilayer ceramic capacitor100may have a length of 3.2 mm, a width of 2.5 mm, and a height of 2.5 mm. The multilayer ceramic capacitor100may have a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm. The dimensions of the multilayer ceramic capacitor100are not limited to the above dimensions.

The main component of the internal electrode layer12is a base metal such as nickel (Ni), copper (Cu), tin (Sn), or the like. The internal electrode layer12may be made of a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or an alloy thereof. The average thickness of each of the internal electrode layers12is, for example, 1 μm or less. The dielectric layers11are mainly composed of a ceramic material having a perovskite structure expressed by a general expression ABO3. The perovskite structure includes ABO3, having an off-stoichiometric composition. For example, employed as the ceramic material is barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), or Ba1-x-yCaxSryTi1-zZrzO3(0≤x≤1, 0≤y≤1, 0≤z≤1) having a perovskite structure. The average thickness of each of the dielectric layers11is, for example, 1 μm or less.

The main component of the external electrodes20aand20bis a metal such as Cu, Ni, aluminum (Al), zinc (Zn), Ag, Au, Pd, or Pt, or an alloy of at least two of them (for example, an alloy of Cu and Ni). In the present embodiment, the main component metal of the external electrodes20aand20bdiffers from the main component metal of the internal electrode layer12. For example, the diffusion coefficient of the main component metal of the external electrodes20aand20bto the main component metal of the internal electrode layer12is greater than the diffusion coefficient of the main component metal of the internal electrode layer12to the main component metal of the external electrodes20aand20b. For example, the main component metal of the internal electrode layer12is Ni, and the main component metal of the external electrodes20aand20bis Cu.

As illustrated inFIG.2andFIG.3A, the section where the internal electrode layer12connected to the external electrode20ais opposite to the internal electrode layer12connected to the external electrode20bis a section where electric capacitance is generated in the multilayer ceramic capacitor100. Thus, the section where electric capacitance is generated is referred to as a capacitance section14. That is, the capacitance section14is a section where two adjacent internal electrode layers12connected to different external electrodes are opposite to each other.

In the present embodiment, the capacitance section14includes a first capacitance section14aand second capacitance sections14b. The first capacitance section14ais a section where the first internal electrode layer12aconnected to the external electrode20ais opposite to the first internal electrode layer12aconnected to the external electrode20b. That is, the first capacitance section14ais a section where adjacent first internal electrode layers12aconnected to different external electrodes are opposite to each other.

In addition, the second capacitance section14bis a section where the second internal electrode layer12bconnected to the external electrode20ais opposite to the second internal electrode layer12bconnected to the external electrode20b. That is, the second capacitance section14bis a section where adjacent second internal electrode layers12bconnected to different external electrodes are opposite to each other.

As illustrated inFIG.2, the section where the internal electrode layers12connected to the external electrode20aare opposite to each other with no internal electrode layer12connected to the external electrode20binterposed therebetween is referred to as an end margin section15. The section where the internal electrode layers12connected to the external electrode20bare opposite to each other with no internal electrode layer12connected to the external electrode20ainterposed therebetween is also the end margin section15. That is, the end margin section15is a section where the internal electrode layers12connected to one of the external electrodes are opposite to each other with no internal electrode layer12connected to the other of the external electrodes interposed therebetween. The end margin section15is a section where no electric capacitance is generated.

As illustrated inFIG.3A, in the multilayer chip10, the section from each of the two side faces of the multilayer chip10to the internal electrode layers12is referred to as a side margin section16. That is, the side margin section16is a section that covers the end edges, extending toward the corresponding side face of the multilayer structure, of the stacked internal electrode layers12. The side margin section16is also a section where no electric capacitance is generated.

As illustrated inFIG.3A, the section surrounded by the cover layer13, the side margin section16, and the capacitance section14is referred to as a margin section17. The margin section17is also a section where no electric capacitance is generated.

In the present embodiment, in the cross-section orthogonal to the facing direction of the two edge faces of the multilayer chip10, a portion connecting the side face and the top face of the multilayer chip10and a portion connecting the side face and the bottom face of the multilayer chip10are defined as ridge portions P1. In each of the ridge portions P1, the shortest distance D1among the distances between the ridge portion P1and the internal electrode layers12is 10 μm or greater. In the example ofFIG.3B, the distance between the ridge portion P1and the end edge of the outermost second internal electrode layer12bis the shortest distance D1. This structure inhibits cracks from reaching the internal electrode layer12even when cracks occur.

In addition, in the multilayer ceramic capacitor100in accordance with the present embodiment, the number of the stacked internal electrode layers12per 1 mm of the height of the capacitance section14in the stack direction is 500 or greater, and this achieves a high capacitance. More specifically, the number of the stacked first internal electrode layers12aper 1 mm of height in the stack direction is 500 or greater in the first capacitance section14a. The number of the stacked second internal electrode layers12bper 1 mm of height in the stack direction is 500 or greater also in the second capacitance section14b.

Such multilayer ceramic capacitors100having a large number of stacked layers have high specific gravity. Thus, the impact due to drop or the like may cause cracks in the multilayer ceramic capacitors100. However, as described above, the multilayer ceramic capacitor100of the present embodiment includes the first multilayer structure and the second multilayer structure disposed on each of the top and bottom faces of the first multilayer structure in the stack direction. The first multilayer structure includes the dielectric layers11and the first internal electrode layers12athat are alternately stacked. The dielectric layers11are manly composed of ceramic. The second multilayer structure includes the dielectric layers11and the second internal electrode layers12bthat are alternately stacked. The width W2of the second internal electrode layer12bis less than the width W1of the first internal electrode layer12ain the direction orthogonal to the stack direction and the facing direction of the two edge faces. This structure reduces occurrence of cracks. A detailed description will be given of this advantageous effect.

First, a description will be given of a multilayer ceramic capacitor200in which the internal electrode layers12have the same width unlike the multilayer ceramic capacitor100of the present embodiment.FIG.4Ais a partial cross-sectional perspective view of the multilayer ceramic capacitor200in which the internal electrode layers12have the same width,FIG.4Bis a cross-sectional view taken along line A-A inFIG.4A, andFIG.4Cis a cross-sectional view taken along line B-B inFIG.4A. As illustrated inFIG.4C, the multilayer ceramic capacitor200has a structure identical to the structure of the multilayer ceramic capacitor100except that the internal electrode layers12have the same width.

FIG.5presents results of the drop test of the multilayer ceramic capacitor200with a length of 1.6 mm, a width of 0.8 mm, and a height of 0.8 mm. InFIG.5, the horizontal axis represents the number of the stacked internal electrode layers12per 1 mm of the height of the capacitance section14in the stack direction, and the vertical axis represents the height from which the multilayer ceramic capacitor200was dropped. As presented inFIG.5, when the number of the stacked internal electrode layers becomes 500 layers/mm or greater, the multilayer ceramic capacitor200itself becomes heavy, and thus, cracks occur even when the multilayer ceramic capacitor200is dropped from a relatively low height such as 0.03 meters. Cracks caused by such drops deteriorate the moisture resistance of the multilayer ceramic capacitor.

FIG.6Ais a graph of a crack occurrence rate in the manufacturing process of the multilayer ceramic capacitor200versus the radius R (seeFIG.4C) of the ridge portion P1of the multilayer ceramic capacitor200, andFIG.6Bis a diagram for describing the radius R.

As illustrated inFIG.6B, the length of a line L1, which connects the starting point of the ridge portion P1on the top face and the starting point of the ridge portion P1on the side face in the cross-section orthogonal to the facing direction of the two edge faces of the multilayer ceramic capacitor200, is represented by W, and the length of the longest line L2among the lines extending from the line L1to the ridge portion P1in the direction orthogonal to the line L1is represented by h. In this case, the radius R is expressed by the following equation.
R=((W/2)2+h2)/2h

InFIG.6A, the multilayer ceramic capacitor200has a length of 1.6 mm, a width of 0.8 mm, and a height of 0.8 mm.FIG.6Areveals that occurrence of cracks in the manufacturing process is reduced by adjusting the radius R to be 105 μm or greater when the multilayer ceramic capacitor200has a length of 1.6 mm, a width of 0.8 mm, and a height of 0.8 mm.

However, when the internal electrode layers12have the same width as in the multilayer ceramic capacitor200, as the radius R of the ridge portion P1increases, the shortest distance D1between the ridge portion P1and the end edge of the internal electrode layer12decreases. Thus, cracks are more likely to reach the internal electrode layer12. Therefore, it is difficult to make the radius R of the ridge portion P1large. On the other hand, in the multilayer ceramic capacitor100of the present embodiment, the second internal electrode layers12bhaving a smaller width are provided near each of the cover layers13. Thus, the radius R of the ridge portion P1can be made to be larger than when the internal electrode layers12have the same width.

FIG.7presents results of the moisture resistance load test conducted after the multilayer ceramic capacitors200with different shortest distances D1were dropped from different heights. In the moisture resistance load test, a voltage of 10 V was applied to the multilayer ceramic capacitor200at a temperature of 45° C. and a relative humidity of 95% for 500 hours after the multilayer ceramic capacitor200was dropped. Thereafter, the direct current resistance was measured by the insulation resistance meter. The multilayer ceramic capacitor200having a measured direct current resistance of 1 MΩ or less was determined to be rejectable.

InFIG.7, open circles indicate the case where the shortest distance D1is 10 μm or greater, and cross marks indicate the case where the shortest distance D1is less than 10 μm. As presented inFIG.7, when the shortest distance D1is 10 μm or greater, there is no rejectable capacitor.

When the radius R of the ridge portion P1is to be 105 μm and the shortest distance D1is to be 10 μm or greater in the multilayer ceramic capacitor200having a length of 1.6 mm, a width of 0.8 mm, and a height of 0.8 mm, the thickness of each of the cover layers13is required to be 160 μm or greater.

FIG.8presents whether cracks occurred during firing in the multilayer ceramic capacitors200having different shortest distances D1and different thicknesses of the cover layer13. As presented inFIG.8, when the shortest distance D1is 10 μm or greater and the thickness of the cover layer13is 160 μm or greater, cracks occur in the cover layer13during firing. A supposable reason is described with reference toFIG.9AandFIG.9B.FIG.9Ais a cross-sectional view illustrating the states before and after firing of the multilayer ceramic capacitor200, andFIG.9Bis a cross-sectional view illustrating the states before and after firing of the multilayer ceramic capacitor100in accordance with the embodiment. In the multilayer ceramic capacitor200, a section P11in which the internal electrode layers12are stacked (indicated by hatching inFIG.9A) shrinks largely due to firing, while a section P12corresponding to the side margin section16shrinks less. The cover layer13cannot follow the difference in shrinkage, and thereby cracks occur in the cover layer13during firing.

In contrast, in the multilayer ceramic capacitor100of the present embodiment, the widths of the internal electrode layers12are changed with two stepped levels. Thus, as illustrated inFIG.9B, a section P22where only the first internal electrode layers12aare stacked shrinks less than a section P21where the first internal electrode layers12aand the second internal electrode layers12bare stacked. Accordingly, since the section P22of which the shrinkage is moderate is interposed between the section P21and a section P23, the following capability of the cover layer13is improved, and occurrence of cracks during firing is reduced. InFIG.9AandFIG.9B, dotted lines indicate the position of the cover layer before firing, and long dashed double-dotted lines indicate a section where the internal electrode layers12are stacked.

FIG.10is a graph presenting results of the reliability test and a crack occurrence rate after baking of the external electrodes20aand20bwith respect to the baking temperature of the external electrodes20aand20b. InFIG.10, open circles indicate the ratio of the samples that were determined to be rejectable in the reliability test to all samples, and black circles indicate a crack occurrence rate. As presented inFIG.10, as the baking temperature increases, the reliability increases, but the crack occurrence rate increases. In the reliability test, a direct current voltage of 10 V was applied to samples under the environment of 105° C., and the sample in which breakdown occurred in less than 1000 hours was determined to be rejectable.

The reason of the above results is considered as follows. As illustrated inFIG.11AandFIG.11B, the internal electrode layers12and the external electrodes20aand20breact with each other during baking, and Cu, which is the metal component of the external electrodes20aand20b, diffuses into the internal electrode layers12, resulting in expansion of the internal electrode layers12. Therefore, as indicated by arrows inFIG.11AandFIG.11B, the outward stresses are generated in the side margin sections16and the end margin sections15, and thereby, cracks30occur in the locations where the cover layer13, the side margin section16, and the end margin section15overlap.

In the multilayer ceramic capacitor200, cracks are more likely to occur from the end edge of the internal electrode layer12, but the multilayer ceramic capacitor200does not have the margin section17unlike the multilayer ceramic capacitor100of the present embodiment. Therefore, it is considered that cracks occur because the cover layer13has insufficient strength with respect to the stress. In contrast, in the multilayer ceramic capacitor100, it is considered that cracks are more likely to occur from the part where the widths of the internal electrode layers12change (indicated by P30inFIG.11C). However, since the multilayer ceramic capacitor100has the margin section17, sufficient strength with respect to the outward stress generated during baking is obtained, and occurrence of cracks is reduced.

As described above, the multilayer ceramic capacitor100in accordance with the present embodiment can reduce occurrence of cracks.

As the width W2of the second internal electrode layer12bdecreases, the capacitance of the multilayer ceramic capacitor100decreases. Thus, the ratio of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12ais preferably 0.5 or greater, more preferably 0.55 or greater, further preferably 0.60 or greater. On the other hand, as the ratio of the width W2of the second internal electrode layer12bincreases, the area of the margin section17decreases, resulting in decrease in resistance to the stress during baking of the external electrodes20aand20b, which may cause cracks. Therefore, the ratio of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12ais preferably 0.75 or less, more preferably 0.7 or less, further preferably 0.65 or less.

The widths W1of the first internal electrode layers12amay differ from each other within a range of ±4%, and the widths W2of the second internal electrode layers12bmay differ from each other within a range of ±4%. Therefore, the ratio of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12amay be the ratio of the average value of the widths W2of the second internal electrode layers12bto the average value of the widths W1of the first internal electrode layers12a.

A description will next be given of a method of manufacturing the multilayer ceramic capacitor100in accordance with the present embodiment.FIG.12is a flowchart of the method of manufacturing the multilayer ceramic capacitor100in the embodiment.

[Making of Raw Material Powder (S1)]

A dielectric material for forming the dielectric layer11is prepared. The dielectric material contains the main component ceramic of the dielectric layer11. The A site element and the B site element contained in the dielectric layer11are contained in the dielectric layer11typically in the form of a sintered compact of ABO3particles. For example, BaTiO3is a tetragonal compound having a perovskite structure, and exhibits high permittivity. This BaTiO3can be obtained typically by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods have been known as a synthesizing method of the main component ceramic of the dielectric layer11. For example, the solid phase method, the sol-gel method, the hydrothermal method, and the like are known. Any one of the above methods can be employed in the present embodiment.

Additive compound is added to the resulting ceramic powder in accordance with purposes. The additive compound may be an oxide of zirconium (Zr), calcium (Ca), strontium (Sr), magnesium (Mg), manganese (Mn), vanadium (V), chrome (Cr), or a rare-earth element, an oxide of cobalt (Co), Ni, lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass.

Next, a margin material for forming the end margin section15and the side margin section16is prepared. The margin material contains the main component ceramic of the end margin section15and the side margin section16. For example, BaTiO3powder is prepared as the main component ceramic. The BaTiO3powder can be obtained through the same process of the making process of the dielectric material. Additive compound is added to the resulting BaTiO3powder in accordance with purposes. The additive compound may be an oxide of Zr, Ca, Sr, Mg, Mn, V, Cr, or a rare-earth element, an oxide of Co, Ni, Li, B, Na, K, or Si, or glass.

Next, a cover material for forming the cover layer13is prepared. The cover material contains the main component ceramic of the cover layer13. For example, BaTiO3powder is prepared as the main component ceramic. The BaTiO3powder can be obtained through the same process as the making process of the dielectric material. Additive compound is added to the resulting BaTiO3powder in accordance with purposes. The additive compound may be an oxide of Zr, Ca, Sr, Mg, Mn, V, Cr, or a rare-earth element, an oxide of Co, Ni, Li, B, Na, K, or Si, or glass. The margin material described above may be used as the cover material.

Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the resulting dielectric material and wet-blended. With use of the resulting slurry, a strip-shaped dielectric green sheet51with a thickness of, for example, 0.8 μm or less is coated on a base material using, for example, a die coater method or a doctor blade method, and then dried.

Then, as illustrated inFIG.13A, a first pattern52a(a first pattern) of the first internal electrode layer is formed on the surface of the dielectric green sheet51(afirst ceramic dielectric green sheet) by printing a metal conductive paste for forming the internal electrode with use of screen printing or gravure printing. The metal conductive paste for forming the internal electrode contains an organic binder. Ceramic particles are added as a co-material to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer11.

Then, a binder such as an ethylcellulose-based binder and an organic solvent such as a terpineol-based solvent are added to the resulting margin material and kneaded by a roll mill to obtain a margin paste for a reverse pattern layer. As illustrated inFIG.13A, a second pattern53ais formed by printing the margin paste in the region where no first pattern52ais printed on the dielectric green sheet51to cause the second pattern53aand the first pattern52ato form a flat surface.

Thereafter, as illustrated inFIG.13B, the dielectric green sheets51, the first patterns52a, and the second patterns53aare stacked so that the first internal electrode layers12aand the dielectric layers11are alternated with each other and the end edges of the first internal electrode layer12aare alternately exposed to both edge faces in the length direction of the dielectric layer11so as to be alternately led out to a pair of external electrodes20aand20bof different polarizations. Through this process, a first multilayer portion is obtained. For example, 300 to 950 dielectric green sheets51are stacked.

Then, as illustrated inFIG.13C, a third pattern52b(a second pattern) of the second internal electrode layer is formed on the surface of the dielectric green sheet51(a second ceramic dielectric green sheet) by printing the metal conductive paste for forming the internal electrode layer with use of screen printing or gravure printing. The width W4of the third pattern52bof the second internal electrode layer in the facing direction of the two side faces is less than the width W3of the first pattern52aof the first internal electrode layer.

As illustrated inFIG.13C, a fourth pattern53bis formed by printing the margin paste in the region where no third pattern52bis printed on the dielectric green sheet51to cause the fourth pattern53band the third pattern52bto form a flat surface.

Thereafter, as illustrated inFIG.13D, the dielectric green sheets51, the third patterns52b, and the fourth patterns53bare stacked so that the second internal electrode layers12band the dielectric layers11are alternated with each other and the end edges of the second internal electrode layers12bare exposed to both edge faces in the length direction of the dielectric layer11so as to be alternately led out to a pair of the external electrodes20aand20bof different polarizations. Through this process, a second multilayer portion is obtained. For example, 25 to 250 dielectric green sheets51are stacked.

Then, as illustrated inFIG.14AandFIG.14B, the second multilayer portion, the first multilayer portion, and the second multilayer portion are stacked in this order from the bottom to obtain a ceramic multilayer structure. Note thatFIG.14Ais a cross-sectional view corresponding to the cross-section taken along line A-A inFIG.1, andFIG.14Bis a cross-sectional view corresponding to the cross-section taken along line B-B inFIG.1.

Then, a binder such as a polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the resulting cover material and wet-blended. With use of the resulting slurry, a strip-shaped cover sheet54with a thickness of, for example, 10 μm or less is coated on a base material using, for example, a die coater method or a doctor blade method, and is then dried. As illustrated inFIG.14AandFIG.14B, a predetermined number (for example, 2 to 10) of the cover sheets54are stacked on and under the ceramic multilayer structure, and then heated and compressed. The resulting multilayer structure is cut into a predetermined chip size (for example, 1.6 mm×0.8 mm). Instead of the above step, a predetermined number of the cover sheets54may be stacked and compressed, and then attached to each of the top and bottom faces of the ceramic multilayer body.

A part of the side margin section may be formed by attaching a margin sheet or applying a margin paste to the side faces of the first and second multilayer portions. More specifically, a predetermined number (for example, 25 to 250) of the dielectric green sheets51, the predetermined number of the third patterns52b, and the predetermined number of the fourth patterns53bare stacked so that the second internal electrode layers12band the dielectric layers11are alternated with each other and the end edges of the second internal electrode layer12bare alternately exposed to both edge faces in the length direction of the dielectric layer11so as to be alternately led out to a pair of the external electrodes20aand20bof different polarizations. Then, a predetermined number (for example, 300 to 950) of the dielectric green sheets51, the predetermined number of the first patterns52a, and the predetermined number of the second patterns53aare stacked so that the first internal electrode layers12aand the dielectric layers11are alternated with each other and the end edges of the first internal electrode layers12aare alternately exposed to both edge faces in the length direction of the dielectric layer11so as to be alternately led out to a pair of the external electrodes20aand20bof different polarizations. Furthermore, a predetermined number (for example, 25 to 250) of the dielectric green sheets51, the predetermined number of the third patterns52b, and the predetermined number of the fourth patterns53bare stacked so that the second internal electrode layers12band the dielectric layers11are alternated with each other and the end edges of the second internal electrode layers12bare alternately exposed to both edge faces in the length direction of the dielectric layer11so as to be alternately led out to a pair of the external electrodes20aand20bof different polarizations.

Then, the cover sheets54, which are to be the cover layers13, are stacked on and under the ceramic multilayer structure, and compressed. Thereafter, the resulting multilayer structure is cut into a predetermined size to obtain a multilayer structure having two edge faces to which the patterns of the first and second internal electrode layers12aand12bare alternately exposed and two side faces to which the patterns of the internal electrode layers12aare all exposed. Then, as illustrated inFIG.15, a sheet55formed of a side margin paste is attached to each of the side faces of the multilayer structure or the side margin paste is applied to each of the side faces of the multilayer structure to form the side margin sections. The margin paste may be used as the side margin paste.

The resulting ceramic multilayer structure is fired in a reductive atmosphere with approximately 1.0 volume percent of H2in a temperature range of 1100° C. to 1400° C. for approximately 2 hours. Through the firing, obtained is the multilayer chip10in which the dielectric layers11and the internal electrode layers12, which are made of the sintered compact, are alternately stacked and the outermost layers are the cover layers13. To reduce deterioration in temperature characteristics due to excessive sintering, the firing temperature is preferably within a temperature range of 1100° C. to 1200° C.

Thereafter, the re-oxidizing process may be performed in a N2gas atmosphere in a temperature range of 600° C. to 1000° C.

[Forming of External Electrode (S5)]

Then, conductive pastes for forming the external electrode are applied to respective edge faces, to which the internal electrode layer patterns are exposed, of the multilayer chip10after firing. The conductive paste for forming the external electrode contains powder of the main component metal (Cu in this embodiment) of the external electrodes20aand20b, a glass component, a binder, a solvent, and other auxiliary agents as needed. The binder and the solvent may be the same as those of the ceramic paste described above.

Then, the multilayer chip10to which the conductive paste for forming the external electrode is applied is baked in a nitrogen atmosphere at a temperature of approximately 770° C. or less. Through this process, the external electrodes20aand20bare baked.

Thereafter, the external electrodes20aand20bmay be coated with a metal such as Cu, Ni, or Sn by plating.

In the manufacturing method in the present embodiment, the widths of the internal electrode layers12are changed with two stepped levels. Thus, in the section next to the side margin section16, the number of the stacked internal electrode layers12is less than that of the multilayer ceramic capacitor200. Therefore, the difference in shrinkage during firing is reduced. Thus, occurrence of cracks in the cover layer13during firing is reduced.

Furthermore, since the margin section is present in the part where the internal electrode layers12form a step, sufficient strength with respect to the outward stress generated during baking of the external electrode is obtained. Thus, occurrence of cracks is reduced.

EXAMPLES

The multilayer ceramic capacitor of the embodiment was fabricated, and the reliability thereof was examined.

Additives were added to barium titanate powder and were sufficiently wet-blended and crushed in a ball mill to obtain a dielectric material. Additives were added to barium titanate powder and were sufficiently wet-blended and crushed in a ball mill to obtain a margin material. Additives were added to barium titanate powder and were sufficiently wet-blended and crushed in a ball mill to obtain a cover material.

An organic binder and solvents were added to the dielectric material, and the dielectric green sheets51were made using a doctor blade method. The organic binder was a butyral-based binder. The solvents were toluene and ethyl alcohol. The third pattern52bof the metal conductive paste was printed on the resulting dielectric green sheet51. The first pattern52aof the metal conductive paste was printed on the dielectric green sheet51. Then, 30 dielectric green sheets51on which the respective third patterns52bwere printed were stacked so that the positions of the third patterns52bwere alternately shifted. Then, 840 dielectric green sheets51on which the respective first patterns52awere printed were stacked so that the positions of the first patterns52awere alternately shifted. Then, 30 dielectric green sheets51on which the respective third patterns52bwere printed were stacked so that the positions of the third patterns52bwere alternately shifted.

An organic binder and solvents were added to the cover material, and the cover sheets54were made using a doctor blade method. The organic binder was a butyral-based binder. The solvents were toluene and ethyl alcohol. Thereafter, the cover sheets54were stacked on and under the stacked dielectric green sheets51, and heated and compressed to obtain a multilayer structure.

Thereafter, the resulting multilayer structure was cut into a predetermined size, and the resulting multilayer structure was fired to make a multilayer chip.

Thereafter, a conductive paste for forming the external electrode was applied to the multilayer chip, and baked to obtain a multilayer ceramic capacitor. The conductive paste for forming the external electrode contained a Cu filler, a glass component, a binder, and solvents

A crack occurrence rate in the multilayer chip after firing was examined with respect to different ratios of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12a

Examples 1 and 2

In the example 1, the ratio of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12awas 0.5. In the example, 2, the ratio of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12awas 0.75.

Comparative Examples 1 to 3

The ratio of the width W2of the second internal electrode layer12bto the width W1of the first internal electrode layer12awas 0.4 in the comparative example 1, 0.9 in the comparative example 2, and 1 in the comparative example 3.

Results are presented inFIG.16. As presented inFIG.16, cracks occurred in the samples of the comparative examples 1 to 3, but no cracks occurred in the samples of the examples 1 and 2.

Next, the effect of the margin-section ratio on the occurrence rate of cracks under the external electrode after baking of the external electrode was examined. The margin-section ratio is the ratio of the total area of regions R2to the area of a region R1in the cross-section orthogonal to the facing direction of the two edge faces. The region R2is a region where no internal electrode layer12exists within the region R1. The region R1is defined by the line obtained by extending the lines connecting the respective end edges of the first internal electrode layers12a, which extend toward two side faces of the multilayer chip10, the outermost internal electrode layer12of the capacitance section14, and the outermost first internal electrode layer12ain the cross-section orthogonal to the facing direction of the two edge faces as illustrated inFIG.17A.

Examples 3 and 4

In the examples 3 and 4, as illustrated inFIG.17A, the widths of the internal electrode layers12were changed with two stepped levels. The margin-section ratio was 0.502 in the example 3, and 0.525 in the example 4.

Comparative Examples 5 to 7

In the comparative examples 5 and 6, as illustrated inFIG.17B, the widths of the internal electrode layers12were changed with three stepped levels. The margin-section ratio was 0.475 in the comparative example 5, and 0.495 in the comparative example 6. In the comparative example 7, as illustrated inFIG.17C, the widths of the internal electrode layers12were changed with four stepped levels, and the margin-section ratio was 0.465.

FIG.18presents results. As presented inFIG.18, cracks occurred in the comparative examples 5 and 6, in which the widths of the internal electrode layers12were changed with three stepped levels, and the comparative example 7, in which the widths of the internal electrode layers12were changed with four stepped levels. By contrast, no cracks occurred in the examples 3 and 4, in which the widths of the internal electrode layers12were changed with two stepped levels. This reveals that the sufficient strength with respect to the stress due to the expansion of the internal electrode layer during baking of the external electrodes is obtained when the widths of the internal electrode layers12are changed with two stepped levels.