Lanthanide dielectric with controlled interfaces

Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices and device fabrication, and particularly to dielectric layers and their method of fabrication.

BACKGROUND

Scaling dielectric layers, including silicon dioxide (SiO2) beyond 2 nm gives rise to large leakage current due to direct tunneling. Thus, alternative high-k dielectrics have been proposed. Generally, “high-K” refers to dielectric constants greater than that of SiO2 (K˜3.9). As used herein, “high-K” will refer to dielectric constants greater than 15, while “medium-K” will refer to dielectric constants between approximately 4-15.

The common approach has involved amorphous materials with higher dielectric constants, such as hafnium or zirconium oxides (K˜20-25) and their silicates (K˜10-14). The former group (oxides) show poor thermal stability and undergo reinsulatorlization at modest temperature (>800 C). The later (silicates) achieve higher thermal stability at the expense of lower dielectric constants. Both groups, in general, when used as a gate dielectric directly on a silicon substrate, exhibit high interface state density and consequently severe mobility degradation for a field effect transistor (FET) device. Additionally, oxygen-vacancy induced defects create a high density of shallow traps introducing threshold instability and reliability concerns.

DETAILED DESCRIPTION

Methods and devices for a high k dielectric with controlled interfaces are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

FIG. 1Aillustrates, at100, a high-k dielectric including a lanthanide insulator film106with controlled interfaces103and107in accordance with one or more embodiments of the present disclosure. A passivation layer104is shown formed over a semiconductor substrate102wafer, e.g., silicon. A lanthanide dielectric film106is shown formed over the passivation layer104. An encapsulation layer107is shown formed over the lanthanide dielectric layer106. Interface103is illustrated as the interface between the passivation layer104and the substrate102. The means by which passivation layer104controls interface103will be described below. Interface107is shown as the interface between lanthanide dielectric layer106and any additional layer which may be used above the dielectric, e.g., a gate electrode such as214inFIG. 2, as controlled by encapsulation layer108. The means by which encapsulation layer108controls interface107will be described below.

In one or more embodiments, semiconductor substrate102may be a silicon wafer, as understood by one of ordinary skill in the art. Passivation layer104will be described in more detail in connection withFIG. 1Bbelow. One or more embodiments could be applicable to other high k insulators including reactive metal oxides, silicates, aluminates, oxynitrides, composites, and laminates, which may react readily with silicon and metals. As used herein, the term “lanthanide” refers to the element lanthanum and other rare-earth metals, e.g., praseodymium, neodymium, samarium, gadolinium, dysprosium, and erbium. Embodiments are not limited to the given examples of lanthanides. As used herein, the term “lanthanide dielectric” refers to the combination of a member of the lanthanide family of metals with additional elements, e.g., lanthanide oxides, lanthanide silicates, and lanthanide aluminates. Embodiments are not limited to the given examples of lanthanide dielectrics enumerated above.

In one or more embodiments, lanthanide dielectric film106can serve as a dielectric for a semiconductor. In some prior approaches, silicon dioxide was used as a dielectric layer. However, scaling SiO2 beyond 2 nm can give rise to large leakage currents due to direct tunneling between the dielectric and the substrate. In some prior approaches, amorphous materials with higher dielectric constants have been suggested as replacements for SiO2, such as hafnium or zirconium oxides and their silicates. The aforementioned oxides have dielectric constants between approximately 20˜25, but can show poor thermal stability and undergo recrystallization at temperatures less than 800 C. The aforementioned silicates have lower dielectric constants (10˜14). Furthermore, both of the oxides and silicates, when used as dielectrics directly on silicon substrates, e.g.,102, can exhibit high interface state density and fixed charges, consequently creating severe mobility degradation and threshold shift for field effect transistor (FET) devices. Additionally, oxygen-vacancy induced defects can create a high density of shallow traps introducing threshold instability and reliability concerns.

Lanthanide insulator film106can be a lanthanide oxide, e.g., La2O3, Pr2O3, Nd2O3, Sm2O3, Gd2O3, Dy2O3, and Er2O3, which can exhibit a large band gap, typically greater than 5 ev, with conduction band offset with silicon greater than 2 ev. Such oxides can also exhibit greater thermal stability on silicon substrates, e.g.,102, compared to ZrO2 or HfO2. Lanthanide oxides can also have higher effective dielectric constants when normalized for a given leakage current density, and can have lattice parameter matching with silicon, which is conducive to epi-oxide growth deriving still higher dielectric constant values. Additionally, lanthanide oxides exhibit superior leakage characteristics. Lanthanide dielectric film106can also be formed as stable lanthanide silicates and aluminates.

Some prior processing schemes for lanthanide dielectrics can result in uncontrollable formation of unwanted SiO2, silicates (SixMyOz), and aluminates (AlxMyOz) at the substrate interface103, which can lower the effective dielectric constant of the films, and can create an unwanted higher fixed charge density. Furthermore, some prior processing schemes can result in interface densities greater than 1E12/cm2and negative fixed charge density resulting in poor FET device characteristics due to reduced carrier mobility. According to one or more embodiments of the present disclosure, tools including at least: liquid injection metalorganic chemical vapor deposition (MOCVD), hot-wall reduced pressure liquid-injection atomic layer deposition (ALD), ultra-high-vacuum molecular-beam epitaxy (MBE) using e-beam evaporation, and high vacuum sputtering can be used to form lanthanide dielectric film106as described below in connection withFIGS. 6 and 7.

The “equivalent oxide thickness” (EOT) measurement, sometimes simply called “oxide equivalent,” is a convenient measure of the relative capacitance of any dielectric layer of a given thickness relative to the thickness that might be required if an SiO2 dielectric layer is employed in any given application. The EOT of a dielectric layer is calculated by dividing the physical thickness of the layer by its dielectric constant over that of the silicon dioxide. The dielectric constant of silicon dioxide is about 4. In one or more embodiments of the present disclosure, lanthanide dielectric film106can be formed to a thickness of approximately 5 nm˜10 nm with an EOT of approximately 1 nm˜2 nm.

Lanthanide oxides can readily absorb moisture. Oxygen and unwanted contaminates can readily diffuse through such films at modest temperature. To ensure integrity of post formation processing and to control the interface107between the dielectric and an additional layer such as a gate electrode, encapsulation layer108can be formed on top of the lanthanide dielectric film106. In one or more embodiments, encapsulation layer108can help control interface107by forming a stable compound such as silicate, oxynitride, or aluminate at the interface107and by preventing reactivity with water for the lanthanide dielectric film106. Encapsulation layer108can be formed to a thickness, e.g., 0.5 nm˜2.0 nm over the dielectric. In one ore more embodiments, encapsulation layer108can be silicon nitride (SiN), undoped polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or PrTixOy, for example. Encapsulation layer108can be formed using tools including rapid thermal anneal (RTA) or in-situ deposition from a composite source by e-beam, sputtering, ALD, or MOCVD.

FIG. 1Billustrates an expanded view of a portion ofFIG. 1A.FIG. 1Billustrates an expanded view of passivation layer104. Lanthanide dielectric films, e.g.,106, can react with oxygen, —OH ions, and hydrogen. Such films can also form silicate layers at room temperature even under ultra-high vacuum conditions. Furthermore, both oxygen and silicon can inter-diffuse in lanthanide dielectric films, e.g.,106. While a high density of interface states can be due to unsaturated bonds at the interface103, high density of fixed charge and traps can be associated with non-stoichiometric silicate or silicide formation and associated defects. By incorporating passivation layer104, the interface103is stabilized and defect formation, as described above, is minimized.

An appropriate oxygen concentration and Si—O bond formation at the interface103is required to overcome the abovementioned defects, without forming weaker Si—H bonds to quench interface states while improving interface103stability. Simultaneously, sufficient Si—N bonds established at or near the interface103can substantially passivate reactivity with oxygen, —OH, and hydrogen.

As shown in the embodiment illustrated inFIG. 1B, passivation layer104can include a nitride112formed above a composition of silicon, oxygen, and nitrogen “SiON”110. In one or more embodiments, SiON layer110can include a mixture of approximately 40 atomic percent of oxygen, 20 atomic percent of nitrogen, and 40 atomic percent of silicon. SiON layer110can be formed to a thickness of 0.5 nm˜2.0 nm using tools such as liquid injection MOCVD, liquid injection ALD, or hot-wall reduced pressure liquid injection ALD. Formation methods will be described in more detail below in connection withFIGS. 6 and 7.

In one or more embodiments, passivation layer104can be formed as two layers, e.g., a bottom layer110formed on the substrate102and a top layer112formed on the bottom layer110. In one or more embodiments, top layer112can be formed as a nitride or a nitrogen rich oxy-nitride. Embodiments are not limited to a two layer passivation layer104. In embodiments including only a one-layer passivation layer104, it can be formed substantially as described for bottom layer110, e.g., SiON. Embodiments having a two-layered encapsulation layer108can include a bottom layer formed to approximately 1.0 nm˜1.5 nm, and a top layer formed to approximately 0.5 nm˜1.0 nm.

FIG. 2illustrates a transistor200having a lanthanide dielectric film206with controlled interfaces203and207in accordance with one or more embodiments of the present disclosure. In one or more embodiments, transistor200can be a field effect transistor (FET). As will be appreciated by one of ordinary skill in the art, the transistor200can be used as a basic high performance device for logic circuits such as microprocessors as well as in a semiconductor memory cell, for example, in a DRAM as described in connection withFIGS. 4A and 4B, or a non-volatile memory cell as described in connection withFIGS. 5A and 5B.

Diffusion regions216, e.g., a source region and a drain region, can be formed in substrate, e.g., silicon semiconductor substrate wafer,202. A passivation layer204may be formed on the substrate202. A lanthanide dielectric film dielectric206may be formed on the passivation layer204. An encapsulation layer208may be formed on the lanthanide dielectric film206. A gate electrode214may be formed on the encapsulation layer208.

The passivation layer204, lanthanide dielectric film206, and encapsulation layer208may be formed and may function substantially as described in connection withFIGS. 1A,1B,6, and7. Furthermore, controlled interfaces203and207are substantially similar to controlled interfaces103and107as described in connection withFIG. 1A. Gate electrode214can be used to apply a voltage to the transistor200in order to create a conductive channel in the substrate202between the diffusion regions216. Transistor200can be a metal oxide semiconductor (MOS) transistor.

In one or more embodiments, the lanthanide dielectric film206may be formed as a lanthanide silicate, lanthanide aluminate, stable polycrystal lanthanide oxide, amorphous lanthanide oxide, stable mono-crystalline oxide, or an amorphous or stable mono-crystalline aluminate, for example. The dielectric constant for the lanthanide dielectric layer206may be greater than 20. The EOT for the transistor200may be approximately 1.0 nm˜1.5 nm. According to one or more embodiments of the present disclosure, the effective electron mobility for the transistor may be greater than 500 cm2/V-sec. In one or more embodiments, the transistor may have a sub-Vt slope of approximately 80 mV/dec and a Vth of approximately 0.5V, as described in more detail in connection withFIG. 9. The transistor200provides the building block for high performance future generation logic circuits such as can be employed in high performance microprocessors.

FIG. 3illustrates a capacitor300having a lanthanide dielectric film306with controlled interfaces305in accordance with one or more embodiments of the present disclosure. In one or more embodiments, capacitor300can be formed on substrate302. As will be appreciated by one of ordinary skill in the art, the capacitor300can be used in a semiconductor memory cell, for example, in a DRAM as described in connection withFIGS. 4A and 4B. Alternatively, the capacitor300can also be used as a discrete capacitor element in logic and RF circuits. The capacitor300includes conductive electrode layers318, which can be formed from conductive materials such as metals, polysilicon, or doped polysilicon.

As shown in the embodiment illustrated inFIG. 3, capacitor300includes passivating layers309between and adjacent to the conductive layers318. In one or more embodiments, passivating layers can be formed as TiN, TaN, or WN. As is also shown in the embodiment illustrated inFIG. 3, capacitor300includes a lanthanide dielectric film306between the encapsulating layers. Lanthanide dielectric film306also can be formed as materials described above in connection withFIG. 1A. In one or more embodiments, lanthanide dielectric film306can be formed as a two-layer dielectric including a layer of PrTiOx and a layer of PrSiOx. The relative position of the layers of PrTiOx and PrSiOx can be reversed in one or more embodiments. The order of placement of the layers depends on the particular fabrication process for the device and relative position of the layers with respect to the electrode material selections and integration requirements.

Capacitors300formed according to one or more embodiments of the present disclosure can provide as much as double capacitor storage capacity compared to capacitors formed using Al2O3, HfO2, or ZrO2 dielectric layers. Capacitors300can achieve dielectric constants of 22 or greater for structures including passivating layer-lanthanide dielectric film-passivating layer (309-306-309). Such as structures including TiN—PrSiOx—TiN, TiN—PrTiOx—TiN, TiN—PrTiOx/PrSiOx—TiN, TaN—PrTiOx/PrSiOx—TaN, and WN—PrTiOx/PrSiOx—WN, and other similar combinations of lanthanum family dielectrics. Capacitors300formed according to one or more embodiments of the present disclosure can achieve dielectric constants of 30 for structures including single dielectric Pr2O3 as the lanthanide dielectric film306.

FIG. 4Aillustrates a buried capacitor-type DRAM memory cell400-A having a lanthanide dielectric film406with controlled interfaces403,405, and407in accordance with one or more embodiments of the present disclosure.FIG. 4Billustrates a trenched capacitor-type DRAM memory cell400-B having a lanthanide dielectric film406with controlled interfaces403and407in accordance with one or more embodiments of the present disclosure. The details of controlled interfaces403and407are substantially the same as described above in connection withFIG. 1Afor interfaces103and107. The one or more embodiments illustrated inFIGS. 4A and 4Bcan be used in DRAM memory cells.

FIGS. 4A and 4Binclude capacitors430including storage electrodes432and plate electrodes434. Storage electrodes432and plate electrodes434can be made of any conductive or semiconductive material as represented by conductive layer318inFIG. 3. In one or more embodiments, storage electrodes432and plate electrodes434are made of polycrystalline or crystalline silicon, a refractory metal such as W, Mo, Ta, Ti or Cr, or combinations thereof such as WSi2, MoSi2, TaSi2 or TiSi2. It will be appreciated that the electrodes432and434may be made from other materials without departing from the scope of the present disclosure. In one or more embodiments, storage electrodes432and plate electrodes434are separated by passivating layers409, e.g.,309inFIG. 3, with controlled interfaces405, e.g.,305inFIG. 3, and a lanthanide dielectric film406, e.g.,306inFIG. 3.

The capacitors430are used to store charge representing data. Access to the capacitors430is made via a select line, e.g., word line,422and sense line, e.g., bit line,424. The select lines422are the gate electrodes, e.g.,214inFIG. 2, of the transistors420that are used to form a conductive channel between diffusion regions, e.g., source/drain regions,416, e.g.,216inFIG. 2, when sufficient voltage is applied to the select line422. In one or more embodiments of the present disclosure, the select line422is located above encapsulation layers408. As described above in connection withFIG. 1A, encapsulation layers408, e.g.,108inFIG. 1A, can be formed as silicon nitride (SiN), undoped polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or PrTixOy.

In the one or more embodiments illustrated inFIGS. 4A and 4B, encapsulation layers408are located above lanthanide dielectric films406. As described above in connection withFIG. 1A, lanthanide dielectric films406, e.g.,106inFIG. 1A, can be formed as lanthanide silicates, lanthanide aluminates, stable polycrystal lanthanide oxides, amorphous lanthanide oxides, stable mono-dielectricline oxides, and stable amorphous or mono-crystalline aluminates. The lanthanide dielectric films used as dielectrics for the transistors420and capacitors430can be made from the same, or different, materials for a particular DRAM device.

As is also illustrated in the one or more embodiments illustrated inFIGS. 4A and 4B, lanthanide dielectric films406are located above passivation layers404, which are located above substrate402. As described above in connection withFIG. 1, passivation layers404, e.g.,104inFIG. 1A, can be formed as a composition of silicon, oxygen, and nitrogen. In one or more embodiments the composition can include 40 atomic percent of oxygen, 20 atomic percent of nitrogen, and 40 atomic percent of silicon. As is also described above in connection withFIG. 1B, in one or more embodiments, passivation layer404can be formed as a layer of SiON and a layer of nitride or nitrogen rich oxy-nitride, e.g., layers110and112respectively inFIG. 1B. Formation processes for the various layers illustrated inFIGS. 4A and 4Bare described in more detail below in connection withFIGS. 6 and 7.

FIG. 5Aillustrates a floating gate-type memory cell500having a lanthanide dielectric film with controlled interfaces in accordance with one or more embodiments of the present disclosure. Transistor500includes a substrate502, e.g., a silicon based substrate, with diffusion regions516, e.g., a source and a drain. In one ore more embodiments, the substrate502can be a p-type silicon substrate implanted with n-type diffusion regions516. In one or more embodiments, the substrate502can be an n-type silicon substrate implanted with p-type diffusion regions516.

Located above substrate502is a stack including a tunnel dielectric548, a floating gate (FG)544, a charge blocking dielectric546, a control gate (CG)542, and a select line, e.g., word line, contact540. Floating gate544can be used to store charge representing data. Although not shown inFIG. 5A, the select line connected to select line contact540continues to connect each of the control gates of other memory cells, e.g., transistors on the select line running in and/or out of the page, as illustrated inFIG. 5A. Both dielectric layers548and546can be high k lanthanide dielectric films as illustrated inFIG. 5B.

FIG. 5Billustrates an expanded view548of the high k dielectric illustrated inFIG. 5A.FIG. 5Bincludes a passivation layer504, a lanthanide dielectric film506, an encapsulation layer508, and controlled interfaces503and507. Passivation layer504is formed on substrate502, as illustrated inFIG. 5A. Floating gate544inFIG. 5Ais formed over encapsulation layer508, illustrated inFIG. 5B. Elements ofFIG. 5Bcan be formed substantially as described above in connection withFIGS. 1A and 1Band as described below in connection withFIGS. 6 and 7.

As one of ordinary skill in the art will appreciate, charge blocking dielectric546inFIG. 5Acould also include a passivation layer, e.g.,504inFIG. 5B, and/or an encapsulation layer, e.g.,508inFIG. 5B. Transistor500, illustrated inFIGS. 5A and 5B, can be a non-volatile memory cell, such as is commonly used in a NAND or NOR flash array.

FIG. 6illustrates a MOCVD/ALD reactor600that can be used in accordance with one or more embodiments of the present disclosure. The elements depicted permit discussion of the present disclosure such that those skilled in the art may practice the present invention without undue experimentation. InFIG. 6, a target656, e.g., substrate, can be located inside a reaction chamber684of MOCVD/ALD reactor600. Also located within the reaction chamber684can be a heated rotary stage654, which can be thermally coupled to target656to control the target temperature. A vaporizer658can introduce precursors to the target656. Each precursor can originate from sources660, including sources662,664, and666, whose flow can be controlled by mass-flow controllers680. Sources660can provide precursors by providing a liquid material to form the selected precursor gas in vaporizer658.

Also included in the MOCVD/ALD reactor600can be purging gas sources670including672and674. Furthermore, additional purging gas sources can be constructed in MOCVD/ALD reactor600, one purging gas source for each precursor gas, for example. For a process that uses the same purging gas for multiple precursor gases less purging gas sources are required for MOCVD/ALD system600. The MOCVD/ALD reactor600also can include gas sources676,678, and679for introduction to reaction chamber684without needing to be vaporized at658for ALD mode operation. Reaction chamber684also can be coupled to vacuum pump, or exhaust pump,652, after thermocouple650, to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from the reaction chamber684.

For convenience, control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections as are known to those skilled in the art are not shown inFIG. 6. Though MOCVD/ALD reactor600is well suited for practicing the present invention, other MOCVD/ALD systems commercially available can be used.

The use, construction and fundamental operation of reaction chambers for deposition of films are understood by those of ordinary skill in the art of semiconductor fabrication. The present invention may be practiced on a variety of such reaction chambers without undue experimentation. Furthermore, one of ordinary skill in the art will comprehend the necessary detection, measurement, and control techniques in the art of semiconductor fabrication upon reading the present disclosure.

The elements of MOCVD/ALD reactor600can be controlled by a computer. To focus on the use of MOCVD/ALD reactor600in the various embodiments of the present invention, the computer is not shown. Those skilled in the art can appreciate that the individual elements such as pressure control, temperature control, and gas flow within MOCVD/ALD system600can be under computer control.

MOCVD/ALD reactor600can be used to form a passivation layer, e.g.,104as described above in connection withFIGS. 1A and 1B. A passivation layer, e.g., passivation layer104, including 40 atomic percent of oxygen, 20 atomic percent of nitrogen, and 40 atomic percent of silicon, with a refractive index of approximately 1.6, could be deposited to a thickness of approximately 1 nm˜2 nm over a silicon substrate, e.g., target656. In one or more embodiments, formation could be performed after some preliminary steps. For example, appropriate high temperature degassing of the reaction chamber684, e.g., pre-baking at 450 C in an ultra-pure nitrogen environment to help provide complete desorption of hydrogen and moisture from silicon surface and a contamination free silicon surface prior to SiON deposition. Furthermore, pre-cleaning of substrate, e.g., target656, interface oxidation, e.g., interface103inFIG. 1A, and in-situ vapor-phase removal of native oxide from the surface of the silicon substrate, e.g., target656can be performed prior to formation.

An SiON passivation layer, e.g.,104inFIGS. 1A and 1B, can be deposited in MOCVD mode using reactants SiCl4, NH3, N2O, or ozone appropriately diluted in a nitrogen carrier at approximately 650 C˜750 C. Such a layer could also be formed in ALD mode with cycles of SiCl4 at approximately 400 C˜450 C and NH3-N20-N2 or NH3-O3-N2 at approximately 650 C˜700 C while maintaining appropriate gas pressures of SiCl4, NH3, and N2O to achieve desired film composition at a slow deposition rate less than 0.1 nm/sec.

As described above in connection withFIG. 1B, the passivation layer could also be formed of a bottom layer of SiON, e.g.,110inFIG. 1B, and a top layer of nitride or nitrogen-rich SiON, e.g.,112inFIG. 1B. In one or more embodiments utilizing a two-layer passivation layer, as described in connection withFIG. 1B, the layer of nitride could be formed to a thickness of approximately 0.5 nm˜1.0 nm. A layer of nitrogen-rich SiON, having a refractive index of approximately 1.8, could be formed by appropriately controlling the N2O content. A layer of nitride, having a refractive index of approximately 2.0, could be formed by eliminating N2O altogether during deposition of the nitride layer.

Crystallography, film composition and quality, and electrical characteristics of lanthanide dielectrics are very sensitive to substrate, e.g.,102inFIG. 1A, preparation and interface, e.g.,103inFIG. 1A, passivation. Formation of lanthanide dielectrics is also very dependent on source material composition and preparation, temperature of deposition, and ambient conditions. Generally, oxide films grown by ALD or MOCVD at substrate temperatures below 650 C are polydielectricline, e.g., hexagonal and oxygen-rich, with or without an amorphous silicate interlayer when tetramethylheptanedionate [(tmhd)3] and methoxymethlypropanolate [(mmp)3] precursor family of source materials are used. These films are characteristically textured and exhibit poorer electrical characteristics and undergo structural changes when annealed above 800 C. Films grown at higher temperatures are relatively more stable on annealing in inert ambient, e.g., Ar or N2, and the silicate interlayer may undergo dielectriclization in an oxygen environment. In contrast, silicates are more stable and remain amorphous even when deposited by ALD or MOCVD means at substrate, e.g., target656, at temperatures between approximately 250 C˜550 C when silylamide precursor sources are used.

After the passivation layer, e.g.,104inFIG. 1A, is formed as described above, a lanthanide dielectric film, e.g.,106inFIG. 1A, can be formed using MOCVD/ALD reactor600. Lanthanide silicates can be formed in MOCVD mode using a source material of [Ln{n(SiMe3)2}3] (lanthanide trialkyl silylamide) in toluene with tetraglyme added for stabilization, and held at approximately 170 C with carrier gas consisting of either argon+N2O or nitrogen+N2O. The substrate temperature can be held around 400 C˜600 C and the reactor pressure can be held at approximately 1 mbar. Incorporation of N2O can help ensure removal of carbon from the film by forming volatile CO2 while keeping the partial pressure of oxygen appropriate for the silicate film formed. The growth rate can be approximately 5 nm˜7 nm/min. Lanthanide silicate can be deposited in the range of approximately 5 nm˜10 nm with an EOT of approximately 1 nm˜2 nm. The particular lanthanides formed can include La, Pr, or Gd, using the above conditions.

Lanthanide silicates can be formed in ALD mode by keeping reactor600and above mentioned sources the same except for the following changes. The carrier gas can be argon+O3 or nitrogen+O3. The substrate temperature can be held around 200 C˜400 C while the precursor pulse length can be approximately 0.5˜1.0 sec. In one or more embodiments a mixture of water vapor and ozone can be employed to control the deposition rate along with nitrogen or argon. A precursor volume of approximately 20 μL-40 μL per cycle can be employed.

Lanthanide aluminates can be formed in MOCVD or ALD mode substantially as described above, but by using precursors including lanthanide amidinates [Ln(R—NCHN—R)3] in combination with Me3Al.

In order to help reduce the poorer structural stability and electrical characteristics of lanthanide-oxide polycrystalline structures resulting from MOCVD/ALD reactions using Ln(mmp)3 and Ln(mthd)3 families of precursors, excess silicon can be incorporated during deposition to drive the surface reaction towards silicate formation around the grain boundaries. This can be achieved by substantially simultaneously incorporating SiCl4 and {Ln(mmp)3 or Ln(mthd)3 or sylilamide} precursors at the substrate. This can result in a mixed oxide/silicate amorphous film that can enhance thermal stability and electrical properties. Using a Gd(mmp)3 precursor deposited over a silicon substrate at a temperature greater than 450 C in the absence of oxygen can result in single-crystal stable Gd2O3 film. At lower temperatures and in the presence of oxygen, the film can be amorphous.

An encapsulation layer, e.g.,108inFIG. 1A, can be formed on the lanthanide dielectric layer, e.g.,106inFIG. 1A. An encapsulation layer can help passivate the film at the interface, e.g.,107inFIG. 1A, and protect against post-processing contaminants throughout an integration process. An in-situ deposition of approximately 0.5˜2.0 nm thick SiN film can help encapsulate the dielectric layer with only a slight reduction in the effective dielectric constant. Other options for an encapsulation layer include undoped polysilicon, TiN, TaN, or WN. Such a layer could be deposited by standard in-situ CVD and other techniques. Optimum encapsulation layers for a given dielectric layer may be selected by one of ordinary skill in the art. For example, TiN can be an effective interface layer in preventing silicate formation and reactivity with water for Pr2O3 as a dielectric film.

FIG. 7illustrates an e-beam evaporation vessel700that can be used in accordance with one or more embodiments of the present disclosure. The e-beam evaporation vessel700can be located on top of a base plate781. The substrate, e.g., target756, can include a previously deposited passivation layer of SiON and/or (nitrogen-rich) nitride. The substrate, e.g., target756, can be held in a substrate support device788with the target surface facing a shutter786that controls exposure of the substrate surface to the beam of evaporated lanthanide source706. The beam can be emitted by bombardment from an electron gun790situated in the lower part of the chamber below the shutter786.

The temperature of the substrate, e.g., target756, and chamber environment can be controlled by a heater787assembly that may include an optional reflector789in proximity to the substrate, e.g., target756. An oxygen distribution ring783can be located below the shutter786. The oxygen distribution ring can be a manifold that distributes oxygen around the surface of the substrate, e.g., target756, at a pressure of about 1E-7 Torr. The electron beam evaporation vessel700can be configured with a vacuum pump752for evacuating the chamber to a pressure of about 10E-6 Torr or less. Oxygen pressure in the chamber can be regulated by oxygen control regulator780. A small amount of oxygen is needed in the chamber to ensure that the deposited layer of lanthanide film is completely oxidized because the process of e-beam evaporation tends to degrade the oxidation stoichiometry of the lanthanide material706. Optional detectors or monitors may be included on the interior or exterior of the vessel700, such as an interiorly situated detector791for detecting the thickness of the layer and the exteriorly situated monitor792for displaying the thickness of the layer. The lanthanide dielectric layer can be formed to a suitable thickness of approximately 5 nm˜10 nm with an EOT of approximately 1 nm˜2 nm by controlling the duration of electron beam evaporation.

Using the process scheme described above, an approximately 2 nm thick stable silicate interface layer may be formed under ultra-high vacuum conditions for Pr2O3 single-dielectric formation on a silicon substrate at approximately 600 C. Optionally, stable Pr-silicate (PrSixOy) amorphous films can also be deposited at lower substrate temperatures, which can achieve dielectric constants of approximately 22.

Stable mono-crystalline Pr2O3 can be deposited over silicon substrate, e.g., target756, using e-beam evaporation from solid single crystal pallets of Pr6O11 crystals at706. Following the formation of a passivation layer, e.g.,104inFIG. 1A, as described above, single-crystal Pr2O3 films could be deposited without a silicate interface layer. An undoped polysilicon layer of approximately 100 nm thickness can be deposited in-situ to eliminate moisture absorption prior to subsequent processing. For other lanthanide oxide dielectric films, a similar approach could be employed using other LnOx material as a source, as will be understood by one of ordinary skill in the art. Alternatively, for single-crystal aluminate films, single-crystal LnAlO3 could be used as targets and laser sputter deposition techniques could be employed at around 1E-7 Torr at a substrate temperature of approximately 650 C˜700 C.

FIG. 8illustrates a flow diagram800of elements for an embodiment of a method to form a semiconductor device including a lanthanide dielectric film with controlled interfaces by liquid-injection metal organic chemical vapor deposition according to one or more embodiments of the present disclosure. Elements810,820,830,840,850, and860indicate general elements of a method to form a semiconductor device. Elements reflect sub-elements of the general element from which they flow. For example,811,813,815, and817provide more detail about general element810.

At810, a silicon substrate, e.g.,102inFIG. 1A, can be pre-cleaned, the surface can be oxidized, and annealed. Element810includes an RCA clean and 5% HF dip to remove hydrated oxide from the substrate at811. At813, a low temperature ozone oxidation can be used to form a protective oxide at 600 C. At815, an in-situ HF-vapor clean can be performed to achieve a clean silicon surface free from oxide. At817, the substrate can be UV-baked to help ensure a clean silicon substrate surface and remove hydrogen from the interface, e.g., interface103inFIG. 1A.

At820, a SiON passivation layer can be deposited to a thickness of approximately 0.5 nm˜1.0 nm as described in more detail with respect toFIGS. 1A,1B, and6. Element820can include the use of precursors SiCl4, NH3, N2O, and N2 at 700 C at821. At823, a programmed reduction of N2O flow can be used to convert a top layer of the overall passivation layer into a nitride or a nitrogen-rich nitride, e.g.,812inFIG. 1B. As described in connection withFIGS. 1A and 1B, passivation layer104can include either a single layer of SiON, or two layers including a bottom layer110of SiON and a top layer112of nitride or nitrogen-rich nitride.

At830a lanthanide dielectric film, e.g.,106inFIG. 1A, e.g., Ln-silicate, can be in-situ deposited to a thickness of approximately 4 nm˜5 nm. Element830can include the use of precursors SiCl3, Pr-trialkyl silylamide, ozone, and (N2 or Ar) at a temperature of approximately 500 C˜550 C with a growth rate of approximately 5 nm/min at a pressure of 1 mbar at831. Formation of this layer is described in more detail with respect toFIGS. 6 and 7.

At840, an encapsulation layer, e.g.,108inFIG. 1A, e.g., SiN, is in-situ deposited to a thickness of approximately 0.5 nm˜1.0 nm. Element840can include the use of precursors SiCl4, NH3, and N2 at approximately 700 C at841. Formation of this layer is described in more detail with respect toFIGS. 6 and 7.

At850, an ex-situ RTA anneal in N2 at 900 C can be performed on the substrate, e.g.,102inFIG. 1A. At this point, the substrate can include a passivation layer, a lanthanide dielectric film, and an encapsulation layer. As one of ordinary skill in the art will appreciate, elements815through850could be performed in one controlled environment, without removing the substrate between processes, for ease of processing. At860, standard post processing can occur, as will be understood by one of ordinary skill in the art.

FIG. 9illustrates transfer characteristics of a transistor formed according to one or more embodiments of the present disclosure. The x-axis is a linear representation of gate voltage, measured in volts. The y-axis is a logarithmic representation of drain current over channel width measured in amps/μm. In the embodiment illustrated inFIG. 9, the transistor can be formed including a lanthanide dielectric film, e.g.,106inFIG. 1A, including Pr2O3 as the lanthanide dielectric, for example. The channel width can be approximately 100 μm for the example illustrated inFIG. 9.

Element900-1represents the transfer characteristics for a device formed according to some prior approaches, e.g., without interface control. Element900-1illustrates a sub-threshold Vt shift of 145 mV/decade. Element900-2represents the transfer characteristics for a device formed according to one or more embodiments of the present disclosure using interface control. Element900-2illustrates a sub-threshold Vt shift of 80 mV/decade. The significantly higher sub-threshold Vt shift illustrated at900-1, without interface control, can indicate that the device turns on, e.g., conducts slowly in response to an applied gate potential due to poor interface characteristics. Nearly ideal device characteristics with superior speed and leakage are achieved with interface control as illustrated at900-2.

CONCLUSION

Methods and devices for a dielectric with controlled interfaces are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.