Multilevel inverters and their components

A multilevel inverter includes a first half bridge in series with a second half bridge, each comprising a switch having a channel. The switch is configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation. During the third mode of operation, a gate of the switch is biased relative to a source of the switch at a voltage that is less than a threshold voltage of the switch. The inverter may also include a third half bridge. The inverter can be configured such that in operation, switches of the third half bridge are switched at a substantially lower frequency than the switches of the first and second half bridges.

TECHNICAL FIELD

This invention relates to multilevel power inverter circuits and the components of which they are comprised.

BACKGROUND

Compared to a simple two-level inverter, multilevel inverters can provide higher operating voltage for a given device rating, lower voltage distortion because of smaller voltage steps, and reduced interference signals. A typical prior art three-level inverter circuit is shown inFIG. 1. The inverter circuit includes four switches101-104, each switch being formed of an insulated gate bipolar transistor or IGBT (111-114) and a diode (121-124). Diodes121-124, which carry freewheeling currents through the switches101-104during times that the switches conduct in the reverse direction (i.e., when current flows from source to drain), are included to prevent conduction through the intrinsic parasitic diodes that are inherent in IGBT devices and are anti-parallel to the channels of the IGBT devices.

The inverter topology shown inFIG. 1is referred to as a neutral-point clamped (NPC) inverter, because diodes125and126serve to clamp their respective switched nodes to the neutral point, here represented as the midpoint of voltage supply130, which supplies a voltage Vs1. There are three possible output voltages at output node140: +(Vs1)/2 (when IGBT transistors111and112are ON and IGBT transistors113and114are OFF), 0 (when IGBT transistors112and113are ON and IGBT transistors111and114are OFF), and −(Vs1)/2 (when IGBT transistors113and114are ON, and IGBT transistors111and112are OFF). To permit current flow in either direction, the 0 level is normally achieved by turning on both IGBT transistors112and113. During operation of this circuit, none of the four transistors (111-114) or six diodes (121-126) ever blocks a voltage in excess of about (Vs1)/2, even though the output voltage at node140swings across the entire range of Vs1[i.e., the minimum output voltage is −(Vs1)/2, and the maximum output voltage is +Vs1)/2].

As shown inFIG. 1and previously described, the transistors111-114are insulated gate bipolar transistors (IGBTs). These IGBTs could be devices rated to operate at voltages up to 600V, for example, and Vs1could be as high as 1200V, which is two times the rated voltage of each of the IGBTs. Although 1200V rated devices exist, the cost and performance of 600V devices is often superior. In the simplest mode of operation, the output voltage at node140is switched between the three possible output voltage levels in sequence which repeats at the desired fundamental frequency of the output, such as 60 Hz, for example. In the case where a sinusoidal output is desired, lower distortion can be achieved if a pulse-width modulation (PWM) technique is employed to apply the switching voltages to the gates of each of the transistors111-114. During the half cycle where the output voltage at node140should be positive, the gate of transistor111is pulsed ON and OFF at some switching frequency which is appreciably higher than that of the desired output. A PWM switching frequency of 10 kHz, for example, could be used to generate a 60 Hz output.

SUMMARY

A DC-AC inverter circuit comprising at least two half-bridges capable of efficient high-frequency switching without freewheeling diodes, which are connected to a common output with switching transistors switched at the low, fundamental frequency, is described. The circuit enables increased power density through reduced component count, higher efficiency, and smaller-sized passive filter components.

A DC-AC inverter circuit, as in the previous paragraph, is described for which the filter function can be moved to intermediate nodes, such that the output transistors are decoupled from the high-frequency switching.

In one aspect, a multilevel inverter comprises a first half bridge connected in series with a second half bridge, where each half bridge comprises a semiconductor-based switch having a channel. Each switch is configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation. During the third mode of operation, a gate of the switch is biased relative to a source of the switch at a voltage that is less than a threshold voltage of the switch.

In a second aspect, a multilevel inverter comprises a first half bridge connected in series with a second half bridge, where each half bridge comprises a plurality of switches, and a third half bridge comprising a high-side switch coupled to a low-side switch. The high-side switch includes a first gate and a first power terminal and the low-side switch includes a second gate and a second power terminal. The inverter is configured such that in operation, the high-side switch and low-side switch are switched at a substantially lower frequency of switching than the plurality of switches of the first and second half bridges.

In a third aspect, a multilevel inverter comprises a first half bridge connected in series with a second half bridge, where each half bridge comprises a plurality of switches. The inverter further includes a third half bridge comprising a high-side switch coupled to a low-side switch, where the high-side switch includes a first gate and a first power terminal and the low-side switch includes a second gate and a second power terminal, and two low-pass filters. The first low-pass filter is coupled between an output node of the first half bridge and the first power terminal of the high-side switch, and the second low-pass filter is coupled between an output node of the second half bridge and the second power terminal of the low-side switch.

Devices described herein can each include one or more of the following features. A multilevel inverter may include a third half bridge that has a low-side switch coupled to a high-side switch, wherein an output node of the first half bridge is coupled to a power terminal of the high-side switch, and an output node of the second half bridge is coupled to a power terminal of the low-side switch. Additionally, the low-side switch and the high-side switch of the third half bridge may each be configured to switch at a substantially lower frequency than a switching frequency of the semiconductor-based switch. Furthermore, the multilevel inverter may include one filter, which is connected to the output node of the third half bridge, or two filters, where the first filter is coupled between the output node of the first half bridge and the power terminal of the high-side switch, and the second filter is coupled between the output node of the second half bridge and the second power terminal of the low-side switch. The semiconductor-based switch of the inverter can comprise a III-Nitride transistor, or can comprise an enhancement-mode transistor coupled to a III-Nitride depletion-mode transistor.

The multilevel inverter may be constructed such that an output node of the first half bridge is electrically coupled to the first power terminal of the high-side switch, and an output node of the second half bridge is electrically coupled to the second power terminal of the low-side switch. The multilevel inverter can be configured such that in operation, the switching frequency of the plurality of switches of the first and second half bridges may be at least five times greater than the switching frequency of the high-side and the low-side switch. The multilevel inverter can be configured such that in operation, the switching frequency of the plurality of switches of the first and second half bridges is at least 50 kHz and the switching frequency of the high-side switch and the low-side switch is 1 kHz or less. The multilevel inverter may include a III-Nitride transistor or an enhancement-mode transistor coupled to a III-Nitride depletion-mode transistor for at least one of the plurality of switches. The first low-pass filter and the second low-pass filter may each include an inductor and a capacitor.

DETAILED DESCRIPTION

Described herein are multi-level inverter circuits which can be designed to have low loss and/or high efficiency. A first example is shown inFIG. 2. The inverter ofFIG. 2is similar to that ofFIG. 1but further includes an L-C output filter which includes inductor251and capacitor252. The output filter substantially attenuates the switching frequency at the output node240. The inductive load current continues in freewheeling fashion during the inactive portions of the switching cycle. During the positive half cycle, diode225provides the path for the freewheeling current when the gate of transistor212is biased OFF (i.e., when the gate electrode of transistor212is biased below the threshold voltage of transistor212relative to the source electrode of transistor212). During the negative half cycle, diode226carries the current when the gate of transistor214is biased OFF.

For the circuit ofFIG. 2, because IGBT transistors211-214have high switching losses, in particular when operated at high switching frequencies, energy loss during each switching cycle is high enough that the switching frequency must be limited in order to minimize power loss. With switching frequencies of about 15 kHz or less, which are typically the highest frequencies that can be employed with IGBT switches during operation without incurring substantially high power loss, passive components251and252required for filtering of inputs and outputs are large, heavy, and expensive. Much of the switching loss is associated with charge injected across a p-n or p-i-n junction (of one of the diodes221-226or within the IGBTs211-214) during conduction. The forward voltage drop associated with a forward biased p-n or p-i-n junction also contributes to conduction loss. In a high voltage circuit, this contributes to the total power loss, generating heat which must be handled by the thermal management portion (e.g., heat sinks) of the system. These limitations can be addressed by utilizing high voltage transistors which lack intrinsic parasitic diodes anti-parallel to their channels and which can be switched at high frequencies (e.g., greater than 50 kHz or greater than 80 kHz) without incurring such high switching losses.

FIG. 3illustrates a three-level inverter built with switches305-310, where each switch is formed of a single transistor315-320, respectively, without the need for any diodes. Switches305-310are each capable of blocking a voltage which is at least equal to 0.5 times the voltage Vs2of the high-voltage supply330. That is, for each switch305-310, when the switch is biased OFF, it can block any voltage which is less than or equal to 0.5 times the voltage Vs2of the high-voltage supply330. In some implementations, the maximum voltage that the switches are each rated to block is between 0.5 times the voltage Vs2of the high-voltage supply330and 1 times the voltage Vs2of the high-voltage supply330. As used herein, the term “blocking a voltage” refers to the ability of a switch, transistor, device, or component to prevent substantial current, such as current that is greater than 0.001 times the average on-state operating current during regular conduction, from flowing through the switch, transistor, device, or component when a voltage is applied across the switch, transistor, device, or component. In other words, while a switch, transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the switch, transistor, device, or component will not be greater than 0.001 times the average on-state operating current during regular conduction.

Transistors315-320each include a conductive channel extending from the source to the drain, the conductivity of a portion of the channel being controlled by the gate. The transistors315-320also each lack an intrinsic parasitic diode anti-parallel to the channel, which allows switches305-310to be formed without anti-parallel diodes (such as diodes221-224ofFIG. 2) while still allowing for low switching losses and low loss during reverse conduction mode.

During operation of the circuit ofFIG. 3, each of transistors315-320operates as follows. In a first mode of operation, when voltage at the drain of the transistor is higher than voltage at the source of the transistor, and the gate of the transistor is biased relative to its source at a voltage below the transistor threshold voltage (i.e., the gate is biased OFF), the transistor blocks the drain-source voltage that is across the transistor. In this mode of operation, the drain source voltage may be as high as (Vs2)/2, and can be even higher immediately after switching due to ringing. In a second mode of operation, when voltage at the drain is higher than voltage at the source and the gate is biased relative to the source at a voltage above the transistor threshold voltage (i.e., the gate is biased ON), the transistor conducts substantial current from the drain to the source (i.e., in a first direction) through the channel of the transistor. In a third mode of operation, when voltage at the drain is lower than voltage at the source and the gate is biased relative to the source at a voltage below the transistor threshold voltage (i.e., the gate is biased OFF), the transistor conducts substantial current from the source to the drain (i.e., in a second direction) through the channel of the transistor. Because this third mode of operation can result in conduction losses being too high, a fourth mode of operation can be achieved as follows. While the transistor is operated in the third mode of operation described above, the gate of the transistor is switched ON (i.e., to a voltage that is greater than the transistor threshold voltage relative to the voltage at the source). In this fourth mode of operation, current continues to flow through the channel of the transistor in the second direction, but conduction losses are reduced relative to the third mode of operation.

Transistors that can be operated as described above include metal-semiconductor field-effect transistors (MESFETs) which are configured such that they lack intrinsic anti-parallel diodes, and high electron mobility transistors (HEMTs) which are configured such that they lack intrinsic anti-parallel diodes. While MESFETs and HEMTs of any material system which include the above characteristics can be used, in high voltage switching applications, III-Nitride transistors such as III-Nitride HEMTs are capable of blocking the required high voltages while having low switching losses and low ON-state conduction losses. A typical III-Nitride HEMT, which is illustrated inFIG. 4, includes a substrate400(e.g., a silicon substrate), a III-N buffer layer402formed of a III-N semiconductor material such as AlN or AlGaN, a III-N channel layer406formed of a III-N semiconductor material such as GaN, a III-N barrier layer408formed of a III-N semiconductor material (e.g., AlGaN or AlN) having a larger bandgap than that of the III-N channel layer406, and a two-dimensional electron gas (2DEG) channel416formed in the III-N channel layer406adjacent to the III-N barrier layer408, the 2DEG channel416serving as the conductive channel of the transistor. The III-N HEMT further includes source and drain contacts410and412, respectively, which contact the 2DEG channel416. A gate electrode414, which is deposited between the source and drain contacts410and412, is used to modulate the conductivity of the channel in the region directly below the gate electrode414. Optionally, a gate insulator420is included between the gate electrode414and the underlying III-N semiconductor materials.

As used herein, the terms III-Nitride or III-N materials, layers, devices, structures, etc., refer to a material, device, or structure comprised of a compound semiconductor material according to the stoichiometric formula AlxInyGazN, where x+y+z is about 1. In a III-Nitride or III-N device, the conductive channel can be partially or entirely contained within a III-N material layer.

Referring again toFIG. 3, switches305-310(and transistors315-320) can also be capable of being switched at frequencies of at least 50 kHz, at least 80 kHz, or at least 100 kHz without sustaining substantial switching losses. Traditional high power switching devices which are capable of blocking high voltages, such as IGBT's and power MOSFETs, which are typically silicon-based devices, experience switching losses at these frequencies that are greater than can be tolerated, and also inherently include parasitic diodes anti-parallel to their channels. On the other hand, III-Nitride or III-N field effect transistors, such as the III-N HEMT shown inFIG. 4, are capable of blocking the required high voltages while inherently being capable of higher switching speeds than a traditional IGBT or power MOS device. High voltage III-N devices, for example III-N HEMTs, have lower reverse recovery charge in their semiconductor portions, as well as lower junction capacitances as compared to traditional IGBTs or power MOSFETs. They have been demonstrated to be capable of switching at frequencies which are in some cases at least as high as 1 MHz (1000 kHz), but typically greater than 80 kHz, greater than 100 kHz, greater than 300 kHz, or greater than 500 kHz, depending on the specific design.

Still referring toFIG. 3, transistors315and316form a first diode-free bridge circuit capable of efficient high-frequency switching. Transistors317and318form a second bridge circuit of the same type, and transistors319and320form a third bridge circuit of the same type. The high-side switching function which was performed by transistor211, diode221, and diode225of the circuit ofFIG. 2is performed by transistors315and316in the circuit ofFIG. 3, without the need for any diodes. Transistor316performs the neutral-point clamping function whether its gate is biased, relative to its source, at a voltage above or below the threshold voltage of the transistor. Likewise, transistors317and318perform the low-side switching function which was performed by transistor214, diode224, and diode226of the circuit ofFIG. 2. These two pairs of transistors each function as two-level half-bridge circuits, operating from a voltage supply of magnitude (Vs2)/2.

The output transistors319and320act as a power multiplexer, selecting which half bridge drives the output and protecting the inactive half bridge from voltages in excess of (Vs2)/2. These transistors are not switched at the high PWM frequency used to switch transistors315-318, but rather at the fundamental frequency of the output. Because the III-N transistors can conduct in both directions, the 0 state does not require both transistors319and320to be ON simultaneously. Rather, for the positive half cycle, the 0 state corresponds to transistors316and319being biased ON, with all other transistors biased OFF. For the negative half cycle, the 0 state corresponds to transistors317and320biased ON, with all other transistors biased OFF.FIG. 5shows gate-drive waveforms provided by the various gate-drive circuits (Vg5, Vg6, etc.) of the circuit ofFIG. 3in producing one cycle of a sinusoidal output voltage with amplitude approaching (Vs2)/2.

The primary advantage of the circuit ofFIG. 3is that switching frequencies above 100 kHz may be used without excessive power loss, and with subsequent reduction in size of the passive components. For inverter circuits which must provide a smoothly varying, nearly sinusoidal output, a filter of the type shown inFIG. 3may be required, and a reduction in the size, cost, and weight of this filter is a desirable. Switching of the transistors at these high frequencies allows for such a reduction in the size, cost, and weight of the filter. A second advantage is that the number of components required for the circuit is reduced, since no freewheeling diodes are required.

Although in the circuit ofFIG. 3the gates of transistors319and320are not switched at high frequencies (the frequencies at which the gates of switches305-308are switched are typically at least five times the frequencies at which the gates of switches309-310are switched, and can more commonly be at least 20 times the frequencies at which the gates of switches309-310are switched), they experience rapidly changing voltages at the switching frequency. In the positive half cycle, for example, when transistor319is ON and transistor320is OFF, all three terminals of transistor319slew between ground potential and +Vs/2 at the same slew rate and frequency as transistors315and316. If transistor319is mounted to an insulated heat sink, then any capacitance between transistor319and the heat sink will be charged and discharged at this rate, with large instantaneous currents, potentially creating interference. At the same time the drain-to-source voltage of transistor320is charged to Vs/2 and discharged at the switching frequency and its output capacitance adds to the switching loss. For these reasons, it may be desirable to decouple transistors319and320from the switching nodes.

Because a very high switching frequency can be used for the switches305-308in the circuit ofFIG. 3, it is a practical possibility to divide the output filter, formed by inductor351and capacitor352, into two filters and move them to the intermediate nodes.FIG. 6shows this topology. In the circuit ofFIG. 6, an output filter is not included at the output node of the circuit (i.e., the filter formed by inductor351and capacitor352at the output node340ofFIG. 3is omitted from the circuit ofFIG. 6). Instead, the circuit ofFIG. 6includes two separate L-C filters, the first filter constituting inductor651and capacitor652, and the second constituting inductor653and capacitor654. The first filter is at one end connected to the output node641of the half bridge formed by switches305and306, and is at the opposite end connected to the high-side power terminal (e.g., the drain terminal) of switch309. The second filter is at one end connected to the output node642of the half bridge formed by switches307and308, and is at the opposite end connected to the low-side power terminal (e.g., the source terminal) of switch310.

In this topology, the high-frequency components of the voltage and current signals that are output at nodes641and642(which result from the high-frequency PWM switching of switches305-308) are filtered prior to the signals being received by output switches309and310, which are switched at much lower frequencies. Consequently, output transistors319and320only experience voltage and current signals at the fundamental output frequency, which might be 60 Hz, for example. This can lead to lower losses and interference in the circuit. In some implementations, switches305-308are switched at frequencies of at least 20 kHz, at least 50 kHz, or at least 80 kHz, while switches309-310are switches at frequencies of 2 kHz or less, 1 kHz or less, 100 Hz or less, or 60 Hz or less.

FIG. 7shows a representative plot of the frequency response of each of the L-C filters used in the circuits ofFIGS. 3 and 6. As shown, the filters can be low-pass filters, the 3 dB roll-off frequency (the frequency corresponding to point51) is about 30 kHz, and the cut-off frequency (the frequency corresponding to point52) is about 300 kHz. The 3 dB roll-off frequency is defined as the frequency at which the output voltage signal is attenuated by 3 dB relative to the input signal. Attenuation by the filter increases monotonically with frequency. As such, signals of higher frequency than the 3 dB roll-off frequency are attenuated by more than 3 dB, and signals of lower frequency than the 3 dB roll-off frequency are attenuated by less than 3 dB. For the L-C filters inFIGS. 2-3 and 6, the 3 dB roll-off frequency f3 dBis given by the equation:
f3 dB=(4π2LC)−1/2

The cut-off frequency of the filter is the frequency above which the fractional admittance (i.e., the ratio of a voltage signal applied at the input to that at the output) of the filter is low enough to prevent substantial output ripple at the switching frequency. The cut-off frequency is typically about 10 times the 3 dB roll-off frequency, but in applications where only very small output ripple can be tolerated, or for filters with a frequency roll-off that is smaller than 40 dB per decade, the cut-off frequency may be higher, for example about 20 times the 3 dB roll-off frequency.

For a filter with a higher 3 dB roll-off frequency, and therefore a higher cut-off frequency, the size of the inductor and/or capacitor can be reduced. When the switches201-204or305-308are switched at a frequency of about 80 kHz or greater, the cut-off frequency of the filter can be at least as high as 50 kHz, and the 3 dB roll-off frequency can be at least as high as 5 kHz or 10 kHz. When the switches201-204or305-308are switched at higher frequencies, for example at least 100 kHz, at least 200 kHz, at least 350 kHz, at least 500 kHz, or at least 1 MHz (1000 kHz), the cut-off frequency of the filter can be higher, for example at least 80 kHz, at least 150 kHz, at least 300 kHz, at least 450 kHz, or at least 900 kHz. The 3 dB roll-off frequency can be at least 12 kHz, at least 20 kHz, at least 30 kHz, at least 50 kHz, or at least 100 kHz.

Referring again toFIGS. 3, 6, and 7, because of the high 3 dB roll-off and cut-off frequencies that the L-C filter can be designed to have when combined with a switches that are switched at these higher frequencies, the frequency of the voltage and/or current signal applied to electrical load can be high. For example, a sinusoidal waveform of at least 1 kHz, at least 2 kHz, at least 5 kHz, at least 10 kHz, at least 50 kHz, or at least 100 kHz can be applied. An additional benefit of enabling a very high switching frequency, combined with a filter with high 3 dB and cut-off frequencies, is that the output waveform is not limited to a single-frequency sine wave. With adequate spacing between the fundamental excitation frequency and the switching frequency, multiple higher harmonics of the fundamental can also be faithfully included in the output waveform. Use of a 3rdharmonic is sometimes employed with three phase motors as a way of utilizing the full available voltage. With the configurations ofFIGS. 3 and 6, even higher harmonics could be introduced, such as a 5thharmonic or a 7thharmonic. For example, harmonic pre-distortion could be applied to the waveform to compensate for nonlinearity of the motor's magnetizing inductance. This could be particularly useful in designs where the magnetic circuit is operated at or near saturation of the magnetic material.

Another advantage to having a filter with such high 3 dB and cut-off frequencies, and correspondingly small inductive and capacitive elements, respectively, is that the filter and/or the entire circuit can be made extremely compact. For a conventional inverter circuit designed to deliver about 1 kW of power to an electrical load, the total volume of the filter alone can be around 104cm3or higher. Furthermore, the total volume of the filter scales approximately linearly with output power. Hence, higher output power requires even larger filter components, leading to excessively high costs for the filter, and preventing use of the inverter circuit in applications that require a more compact design.

While the switches305-310inFIGS. 3 and 6are each shown to be formed of single transistors, other devices which can inherently be switched at high frequencies could be used instead. For example, a hybrid device807, shown inFIGS. 8A and 8B, could be used for any of switches305-310. Although the switches305-310could be depletion-mode (D-mode) devices, it is often preferable that switches305-310be enhancement-mode or E-mode devices. That is, the switch is in the OFF state when the control terminal is held at the same voltage as the low-side terminal, and is turned ON by switching the voltage at the control terminal to a sufficiently high positive voltage relative to the low-side terminal. Since single high-voltage enhancement-mode transistors can be difficult to fabricate reliably, one alternative to a single high-voltage E-mode transistor is to combine a high-voltage depletion-mode transistor808with a low-voltage E-mode transistor809in the configuration ofFIGS. 8A and 8Bto form a hybrid device807. Hybrid device807can be operated in the same way as a single high-voltage E-mode transistor, and in many cases achieves the same or similar output characteristics as a single high-voltage E-mode transistor.FIG. 8Ashows a plan view schematic diagram of hybrid device807, andFIG. 8Bshows a circuit schematic of hybrid device807. Hybrid device807includes a high-voltage D-mode transistor808and a low-voltage E-mode transistor809. In the configuration illustrated inFIGS. 8A and 8B, E-mode transistor809is a vertical transistor, having its drain electrode813on the opposite side of the device from its source electrode811and gate electrode812, and D-mode transistor808is a lateral transistor, having its source electrode814, gate electrode815, and drain electrode816all on the same side of the device. However, other configurations for each of transistors808and809are possible as well.

The source electrode811of the low-voltage E-mode transistor809and the gate electrode815of the high-voltage D-mode transistor808are both electrically connected together, for example with wire bonds869, and together form the source821of the hybrid device807. The gate electrode812of the low-voltage E-mode transistor809forms the gate822of the hybrid device807. The drain electrode816of the high-voltage D-mode transistor808forms the drain823of the hybrid device807. The source electrode814of the high-voltage D-mode transistor808is electrically connected to the drain electrode813of the low-voltage E-mode transistor809. As seen inFIG. 8A, drain electrode813, which is on the opposite side of the E-mode transistor809from the source and drain electrodes811and812, respectively, can be electrically connected to source electrode814by mounting the low-voltage E-mode transistor809directly on top of the source electrode814with the drain electrode813directly contacting the source electrode814, for example by using a conductive solder or resin. As such, the footprint (and therefore the cross-sectional area) of the low-voltage E-mode transistor809can be smaller than that of the high-voltage D-mode transistor808, and in particular the footprint of the low-voltage E-mode transistor809can be smaller than that of the source electrode814of high-voltage D-mode transistor808.

As used herein, a “hybrid enhancement-mode electronic device or component”, or simply a “hybrid device or component”, is an electronic device or component formed of a depletion-mode transistor and an enhancement-mode transistor, where the depletion-mode transistor is capable of a higher operating and/or breakdown voltage as compared to the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor with a breakdown and/or operating voltage about as high as that of the depletion-mode transistor. That is, a hybrid enhancement-mode device or component includes at least 3 nodes having the following properties. When the first node (source node) and second node (gate node) are held at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage (i.e., a voltage larger than the maximum voltage that the enhancement-mode transistor is capable of blocking) applied to the third node (drain node) relative to the source node. When the gate node is held at a sufficiently positive voltage (i.e., greater than the threshold voltage of the enhancement-mode transistor) relative to the source node, current passes from the source node to the drain node or from the drain node to the source node when a sufficiently positive voltage is applied to the drain node relative to the source node. When the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The depletion-mode transistor can have a breakdown and/or maximum operating voltage that is at least two times, at least three times, at least five times, at least ten times, or at least twenty times that of the enhancement-mode transistor.

As used herein, a “high-voltage device”, such as a high-voltage transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, about 1200V or higher, or about 1700V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block any voltage between 0V and at least Vmax, where Vmaxis the maximum voltage that could be supplied by the circuit or power supply. In some implementations, a high-voltage device can block any voltage between 0V and at least 2*Vmax. As used herein, a “low-voltage device”, such as a low-voltage transistor, is an electronic device which is capable of blocking low voltages, such as between 0V and Vlow(where Vlowis less than Vmax), but is not capable of blocking voltages higher than Vlow. In some implementations, Vlowis equal to about |Vth|, greater than |Vth|, about 2*|Vth|, about 3*|Vth|, or between about |Vth| and 3*|Vth|, where |Vth| is the absolute value of the threshold voltage of a high-voltage transistor, such as a high-voltage-depletion mode transistor, contained within the hybrid component in which a low-voltage transistor is used. In other implementations, Vlowis about 10V, about 20V, about 30V, about 40V, or between about 5V and 50V, such as between about 10V and 40V. In yet other implementations, Vlowis less than about 0.5*Vmax, less than about 0.3*Vmax, less than about 0.1*Vmax, less than about 0.05*Vmax, or less than about 0.02*Vmax.

In the hybrid device ofFIGS. 8A and 8B, while the high-voltage D-mode transistor808typically lacks a parasitic diode anti-parallel to the channel, the low-voltage E-mode transistor809may include an intrinsic parasitic anti-parallel diode. Or, an external diode can be connected anti-parallel to the channel. In the case where transistor809includes an intrinsic parasitic anti-parallel diode but without an external diode connected in parallel to the parasitic diode, hybrid device807operates as follows. In a first mode of operation, when voltage at the drain of the hybrid device (i.e., the drain of D-mode transistor808) is higher than voltage at the source of the hybrid device (i.e., the source of E-mode transistor809) and the gate of the hybrid device (i.e., the gate of E-mode transistor809) is biased relative to the source at a voltage below the threshold voltage of E-mode transistor809(i.e., the gate is biased OFF), the hybrid device807blocks the drain-source voltage that is across the device. In this mode of operation, the drain source voltage may be as high as (Vs2)/2, and can be even higher immediately after switching due to ringing. In a second mode of operation, when voltage at the drain of the hybrid device is higher than voltage at the source of the hybrid device, and the gate of the hybrid device is biased relative to the source at a voltage above the threshold voltage of E-mode transistor809(i.e., the gate is biased ON), the hybrid device conducts substantial current from the drain of the hybrid device to the source of the hybrid device (i.e., in a first direction) through the channels of both transistors808and809. In a third mode of operation, when voltage at the drain of the hybrid device is lower than voltage at the source of the hybrid device, and the gate is biased relative to the source at a voltage below the transistor threshold voltage (i.e., the gate is biased OFF), the hybrid device conducts substantial current from the source of the hybrid device to the drain of the hybrid device (i.e., in a second direction). In this mode of operation, the current conducts through the channel of D-mode transistor808and through the parasitic diode of E-mode transistor809. Since E-mode transistor809is a low voltage device, conduction and switching losses incurred due to switching on of the parasitic diode are not as high as those incurred for conduction through a parasitic diode of a high voltage transistor. However, this third mode of operation can still result in conduction losses being too high, and so a fourth mode of operation can be achieved as follows. While the hybrid device is operated in the third mode of operation described above, the gate of the hybrid device is switched ON (i.e., to a voltage that is greater than the hybrid device threshold voltage relative to the voltage at its source). In this fourth mode of operation, current continues to flow through the channel of the D-mode transistor808in the second direction, but current in the E-mode transistor809flows through the transistor channel rather than through the parasitic diode. Hence, conduction losses are reduced relative to the third mode of operation.

In a hybrid device in which an external diode is connected anti-parallel to the channel, the external diode performs the same function as the parasitic diode in the four modes of operation described above.

InFIGS. 8A and 8B, D-mode transistor808can be a III-Nitride transistor, such as a III-N HEMT, and E-mode transistor809can be a Silicon-based device, such as a Si MOSFET. Alternatively, E-mode transistor809can be a III-N transistor as well. Because E-mode transistor809is a low-voltage device, and therefore does not need to be capable of blocking the entire circuit high voltage, it can be made to switch much faster than a high-voltage device formed of the same material. Hybrid device807can therefore be capable of operating at the higher switching frequencies for which the filter is designed.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, additional half-bridge circuits may be included to create any number of output voltage levels. It is also understood that the topology is not limited to production of pure sinusoidal waveforms. Although the circuit is referred to as an inverter, consistent with a common application, it could be applied to any switch-mode amplifier function. Accordingly, other embodiments are within the scope of the following claims.