Feedback compensation for multistage amplifiers

Feedback compensation for multistage amplifiers. In some embodiments, an amplifier can include a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier can further include a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier can further include a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback pack can include a transconductance element and a second capacitance arranged in series. In some embodiments, such an amplifier can be configured as an operational-amplifier.

BACKGROUND

Field

The present disclosure relates to feedback compensation for multistage amplifiers.

Description of the Related Art

In many electronic applications, processing of signals can include use of an amplifier. Such an amplifier can include, for example, an operational-amplifier.

SUMMARY

In accordance with some implementations, the present disclosure relates to an amplifier that includes a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier further includes a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier further includes a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback path includes a transconductance element and a second capacitance arranged in series.

In some embodiments, the amplifier can further include a cascode transistor implemented between an output of the first stage and an input of the second stage. The first feedback path can include the cascode transistor such that the first feedback path couples the output of the third stage with the input of the second stage. The cascode transistor can include a source connected to the output of the first stage, and a drain connected to the input of the second stage.

In some embodiments, the amplifier can further include a feed-forward element implemented between the input of the second stage and the output of the third stage. The feed-forward element can include a field-effect transistor having a gate connected to the input of the second stage and a drain connected to the output of the third stage.

In some embodiments, the third stage can include a field-effect transistor having a drain connected to the output of the third stage and a gage connected to an input of the third stage. In some embodiments, the input of the third stage can be directly connected to the output of the second stage. In some embodiments, the second feedback path can be configured such that a first terminal of the second capacitance is connected to the drain of the field-effect transistor of the third stage, and a second terminal of the second capacitance is connected to the transconductance element of the second feedback path. In some embodiments, the transconductance element of the second feedback path can include a field-effect transistor having a source connected to the second terminal of the second capacitance, and a drain connected to the output of the second stage.

In some embodiments, each of the first stage, the second stage, and the third stage can include one or more field-effect transistors. In some embodiments, substantially all of the field-effect transistors can be implemented as CMOS devices.

In some embodiments, the amplifier can be configured as an operational-amplifier. The operational-amplifier can be configured to process a signal having a frequency within a radio-frequency (RF) range.

In a number of implementations, the present disclosure relates to a semiconductor die having a semiconductor substrate and an amplifier circuit implemented on the semiconductor substrate. The amplifier circuit includes a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier circuit further includes a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier circuit further includes a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback path includes a transconductance element and a second capacitance arranged in series.

In some embodiments, each of the first stage, the second stage, and the third stage can include one or more field-effect transistors. The semiconductor substrate can be configured to allow formation of the field-effect transistors as CMOS devices.

In some embodiments, the amplifier circuit can be configured as an operational-amplifier. In some embodiments, the semiconductor die can further include an integrated circuit configured to process one or more signals, and the integrated circuit can be coupled to and configured to utilize the operational-amplifier.

In some teachings, the present disclosure relates to a packaged electronic module having a packaging substrate configured to receive a plurality of components, and a semiconductor die mounted on the packaging substrate. The semiconductor die includes an amplifier circuit having a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier circuit further includes a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier circuit further includes a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback path includes a transconductance element and a second capacitance arranged in series.

In some implementations, the present disclosure relates to a packaged electronic module having a packaging substrate configured to receive a plurality of components, and an amplifier circuit implemented on the packaging substrate. The amplifier circuit includes a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier circuit further includes a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier circuit further includes a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback path includes a transconductance element and a second capacitance arranged in series.

In some embodiments, some or all of the amplifier circuit can be implemented on a semiconductor die, and such a die can be mounted on the packaging substrate.

In some implementations, the present disclosure relates to an electronic device having one or more amplifier circuits. Each of the one or more amplifier circuits includes a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier circuit further includes a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier circuit further includes a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback path includes a transconductance element and a second capacitance arranged in series.

In some embodiments, the electronic device can be, for example, a wireless device.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Disclosed herein are various examples related to circuits, devices and methods involving feedback compensation for multistage amplifiers. For the purpose of description, it will be understood that a multistage amplifier can include two or more amplification stages.

In some embodiments, a feedback compensation circuit can be configured as cascode and transconductance with capacitances feedback compensation (also referred to herein as CTCFC) for multistage amplifiers. By adding a transconductance with capacitor feedback across, for example, an output stage of an amplifier, a shorting effect of the capacitor can be eliminated or reduced, which can enlarge the gain at a higher frequency region. Such a capacitor can also help stabilize a no load configuration. Another compensation capacitor implemented through cascode from an output to a first stage of the amplifier can simplify the compensation circuit and provide one or more zeros to further increase the bandwidth. Various examples related to the foregoing are described herein.

When configured as described herein, an example amplifier implemented in a 0.6 μm CMOS process has demonstrated a number of performance features. For example, a gain-bandwidth product (GBW) has been shown to be approximately 3.6 MHz under a capacitive load of 1 nF. A slew rate of approximately 2.6V/μs and a current consumption of approximately 88 μA have also been demonstrated as yielding an improvement in, for example, a figure of merit performance parameter IFOML.

Operational amplifiers are important building blocks in modern integrated systems. With high-gain and high-bandwidth characteristics, they are widely used in various circuits such as buffers, filters and data converters. Due the shrinking voltage headroom, conventional methods of cascoding transistors to increase the gain are generally not practical. Instead, cascading stages horizontally is a popular method of gain boosting. However, an increase of pole number due to multiple stages typically generates closed-loop stability problems for the amplifiers.

In some applications, frequency-compensation methods can be utilized to address some or all of the foregoing challenges. For example, nested-Miller compensation (NMC) is a known technique that can be utilized. However, a disadvantage of large compensation capacitors and low gain-bandwidth product typically limits the applicability of such a technique.

In some applications, transconductance with capacitances feedback compensation (TCFC) uses a transconductance stage between a compensation capacitor and the feedback node to avoid self-biasing of an output stage in order to improve the frequency response. However, such a configuration can be affected by another compensation capacitor, similar to foregoing NMC example.

In some applications, active-feedback frequency-compensation (AFFC) technique utilizes a similar method to deal with another compensation capacitance by an extra circuit. However, if implemented without a transconductance with capacitance feedback, such a configuration can suffer from a stability problem for small load conditions.

Described herein are examples related to a cascode and transconductance with capacitances feedback compensation (also referred to herein as CTCFC) technique for an example three-stage amplifier. It will be understood that such an amplifier can be an operational amplifier, an amplifier configured to amplify a radio-frequency (RF) signal, and the like.

With such a CTCFC topology, small compensation capacitors can be implemented to thereby help stabilize the multi-pole system which gives rise to a higher gain-bandwidth product, as well as an ability of driving a no load or large capacitive load with a reasonable slew rate. Various examples of an analysis of the foregoing CTCFC technique are described herein in greater detail. Although the example CTCFC configuration is described in the context of a three-stage amplifier, it will be understood that one or more features of the present disclosure can also be implemented in amplifiers having other numbers of stages.

It is noted that in some implementations, nested Miller compensation (NMC) can include an extension of two-stage Miller compensation. By assuming that gain of each stage is much larger than 1 and CL, Cm1,2>>Ci, where Ciis the parasitic capacitance at the output of the i-th stage, CLis the load capacitance and Cm1,2are compensation capacitors, a condition yielding stability can be expressed as gm3/(4CL)>2πGBW, where gm3is the transconductance of the last stage, and GBW is the gain bandwidth.

Then, a large transconductance for the last stage is typically required, which is typically not suited for low-power applications. Accordingly, the foregoing stability condition limits the maximum achievable GBW. With gm1,2being transconductances for the first and second stages, design constraints can be expressed as Cm1=4gm1/(gm3CL) and Cm2=2gm2/(gm3CL). With such design constraints, an example phase margin of 60° can be realized. However, the compensation capacitors are typically large and proportional to the load capacitor. Accordingly, use of such compensation capacitors will typically need an increased area, and degradation of slew rate can occur.

It can be seen that the first to output stage compensation capacitor Cm1generates one right hand plan (RHP) zero which is typically harmful to phase margin. The second to output compensation Cm2typically shorts the connection at high frequency and typically causes an unnecessary gain reduction. If Cm2is removed, such limitation can be eliminated or reduced; however, the first non-dominant pole would typically be determined by the parasitic capacitance at the output node of the second stage which is typically very process-sensitive. Accordingly, stability with small CLis also affected.

Disclosed herein are examples related to a cascode and transconductance with capacitances feedback compensation (CTCFC) circuit.FIG. 1shows an example amplification system having multiple stages, and also having a CTCFC circuit having one more features as described herein. In some embodiments, by adding a transconductance with capacitance feedback across the last stage (gmt-Cm2loop inFIG. 1), a shorting effect caused by sole Cm2compensation can be prevented. Also, GBW can be increased, and stability can be achieved for no-external-load applications. By introducing a Cm1capacitance through a cascode transistor, two left-hand plane (LHP) zeros can be generated to improve the stability performance. In addition, an area needed for such compensation can be small, and the slew rate can be improved due to the small compensation capacitors.

Referring to the example compensation configuration ofFIG. 1, gmi, Riand Cirepresent transconductance, resistance and capacitance, respectively, of each stage. A ratio gmc/Rcis the transconductance/input-resistance of the cascode transistor, and gmt/Rtis the transconductance/input-resistance for the second compensation feed-back (gmt-Cm2) loop. The two example compensation capacitors are represented by Cm1and Cm2. CLis the load capacitance.

In some embodiments, a feed-forward stage gmfcan be utilized to improve the slew-rate. In the compensation configuration ofFIG. 1, the feedback of Cm1can be implemented through cascode gmcwhich can also include an indirect compensation functionality. Some or all of the foregoing features can facilitate simplification of the amplification and/or the compensation circuit and also yield an improved frequency response.

Referring to the example compensation configuration ofFIG. 1, a small signal open-loop transfer function can be expressed as follows. For simplification, assumptions can be made where
gm1R1,gm2R2,gm3R3>>1, and  (1a)
CL>>Cm1,Cm2; andCm1,Cm2>C1,C2.  (1b)

In addition, Cm1can be set to be equal to Cm2to simplify computations. One can also assume that Rt=1/gmt, and Rc=1/gmc. Then, the transfer function can be expressed as

In some embodiments, stability with large load capacitance can be addressed based on a unity-gain closed-loop configuration. Since the denominator's order is higher than that of the numerator, the stability will typically depend on the denominator of the closed-loop transfer function. By neglecting the zeros, the closed-loop transfer function can be expressed as

With Routh-Hurwitz stability criterion, the stability conditions can be obtained as

{gmt<gm⁢⁢cGBW=gm⁢⁢1Cm⁢⁢1<A2⁢Cm⁢⁢1C1⁢(gm⁢⁢c-gmt)gm⁢⁢c⁢gm⁢⁢3CL(4)
In Equation 4, A2is representative of the gain of the second stage. The first condition can be easy to meet since gmtand gmcare both under control. As for the second condition, the achievable GBW can be scaled by A2Cm1(gmc−gmt)/(C1gmc) which can increase the limitation to a large amount. However, because of process uncertainty in some implementations, a conservative value can be more preferable in some designs.

In some embodiments, no-load stability with and without gmt-Cm2loop can be characterized as follows. For the no-load situation, assumptions similar to those described above can be made, except that CL, which mainly comes from the parasitic capacitance, is typically only several times larger than C2. Accordingly, stable conditions by Routh-Hurwitz stability criterion can be expressed as in Equations 5 and 6 for configurations with and without the gmt-Cm2loop, respectively. In some situations, the condition associated with Equation 6 (without the gmt-Cm2loop) can be more difficult to be met because of the relatively small C2and gmccompared with CLand gm2. Further, the stability can depend highly on parasitic parameters, and designs depending on such stability are typically not robust designs. If the gmt-Cm2loop is present, the stability can be improved by Cm2which can be set to be the same as Cm1for simple calculations.

It will be understood that the foregoing example analysis in reference to Equations 5 and 6 is applicable for smaller CLcompared with Cm1. For a load capacitance in between (e.g., a medium load capacitance), appropriate transfer functions can be obtained.

It is noted that with the some or all of the foregoing conditions described herein, stability can be achieved. Additional information such as phase margin can be obtained by including more small terms in the open-loop transfer function. With a large load capacitance, such a transfer function can be re-written as

It is noted that p−3 dBis a dominant pole. With a very conservative estimation, one can have

zc⁢⁢1,⁢2≈Cm⁢⁢1⁢R1⁢gmf±2⁢Cm⁢⁢1⁢R1⁢gmf2⁢C1⁢Cm⁢⁢1⁢R1=3⁢gmf2⁢C1⁢⁢or⁢⁢-gmf2⁢C1(8)
which can be set far away without affecting phase margin. In addition, as long as ωol1and ωol4are far from each other which is realizable, the two LHP zeros can cancel the real poles to thereby expand the GBW. Then the complex poles can eventually determine the phase margin. In such a situation, a design constraint can include

From the foregoing, one can obtain

To avoid gain peaking, damping factor can be set or estimated as

FIG. 2shows a more detailed schematic of the example amplification system100ofFIG. 1. InFIG. 2, such an amplification system is depicted as a three stage amplification system110. The three stages can generally include dashed portions indicated as gm1, gm2, and gm3. In the example ofFIG. 2, Cm1compensation and gmt-Cm2loop as described herein can include dashed portions indicated as114and122, respectively.

In some embodiments, the three stage amplifier ofFIG. 2can be implemented in, for example, a 0.6 μm CMOS process. Each of the capacitances Cm1and Cm2can have a value of, for example, approximately 1 pF.

In some embodiments, the first stage can be implemented with a differential input single-ended folded cascode. The second stage can include a common source with a current mirror. The third stage can be implemented as a class-AB stage to, for example, improve slew-rate performance.

Examples of DC gains and phase margins at different corners for the example configuration ofFIG. 1are shown in Table 1.

TABLE 1CornerTSSFFFSSF−40°DCGain (dB)105.5105.1105.6105.1106.6PM (°)70.2578.6750.3569.8670.8527°DCGain (dB)102.7102.4102.6102.3103.1PM (°)67.4676.3751.6467.0368.09105°DCGain (dB)100.7100.5100.4100.4101.1PM (°)65.3574.6650.2564.8765.99
Referring to Table 1, it is noted that the phase margin (PM) can be kept above 50° at all of the corners.

FIG. 3shows examples of responses of transfer functions for the worst case example of Table 1 (phase margin at the FF corner (50.25) at 105°), relative to a unity gain frequency (UGF). The three sets of curves correspond to different load capacitances (e.g., CL=1,000 nF, 850 nF, 700 nF). It is noted that the phase margin becomes better with smaller load, consistent with the example of Equation 9.

Examples of parameters of the amplifier at the foregoing FF corner are shown in Table 2, and examples of specifications are shown in Table 3.

An example configuration without an external load was also simulated, and the corresponding closed-loop pole locations are shown in Table 4.

TABLE 4CaseP1 (MHz)P2 (MHz)P3 (MHz)P4 (MHz)With Loop−3.0−15.8−41.8−51.8 ± 210.3iNo Loop−3.0−18.155.8 ± 150.8i−226.4
In Table 4, the example pole locations are shows for configurations with and without the gmt-Cm2loop as described herein. One can see that in the configuration without the gmt-Cm2loop, the RHP poles degrade or destroy the stability performance.

FIG. 4shows an example of large signal performance for the example amplifier ofFIG. 2. As shown, the slew rate can be as high as 2.6V/μs, and such a slew rate can allow the amplifier design to drive larger load capacitance with more slew rate and improving the IFOMLperformance.

As described herein, one or more features of a frequency compensation technique can provide effective compensation of amplification topology for both large capacitive load and no-load configurations. As also described herein, two example LHP zeros can help cancel or reduce the effect of two real poles, and with such complex poles' expression, designs for multistage amplifiers can be improved. Further, and as described herein, such a technique can stabilize and enlarge bandwidth associated with a multistage amplifier. In the example where the output stage is a class-AB amplification stage, one or more features of the present disclosure can allow driving of the output with relatively large slew rate in a multistage amplifier implemented in, for example, 0.6 μm CMOS technology.

FIG. 5shows that in some embodiments, a multistage amplifier204having one or more features as described herein can be implemented in a semiconductor die200. Such a die can include a substrate202configured to allow, for example, CMOS processes for formation of the multistage amplifier204.

In the example ofFIG. 5, the multistage amplifier204can be implemented as, for example, an operational amplifier having one or more features as described herein. It will be understood that one or more features of the present disclosure can also be implemented in other types of amplifiers. The die202can also include some or all of a compensation circuit206having one or more features as described herein.

In some implementations, one or more features described herein can be included in a module.FIG. 6depicts an example radio-frequency (RF) module300having a packaging substrate302that is configured to receive a plurality of components. In some embodiments, such components can include a die200having one or more features as described herein. For example, the die200can include a semiconductor die202such as the example ofFIG. 5. A plurality of connection pads304can facilitate electrical connections such as wirebonds308to connection pads310on the packaging substrate302to facilitate passing of various power and signals to and from the die200.

In some embodiments, other components can be mounted on or formed on the packaging substrate302. For example, one or more surface mount devices (SMDs) (314) can be implemented. In some embodiments, the packaging substrate302can include a laminate substrate.

In some embodiments, the module300can also include one or more packaging structures to, for example, provide protection and facilitate easier handling of the module300. Such a packaging structure can include an overmold formed over the packaging substrate302and dimensioned to substantially encapsulate the various circuits and components thereon.

It will be understood that although the module300is described in the context of wirebond-based electrical connections, one or more features of the present disclosure can also be implemented in other packaging configurations, including flip-chip configurations.

In some embodiments, the RF module300ofFIG. 6can be, for example, a power amplifier module, a front-end module, a low-noise amplifier module, a transceiver module, a power management module, or any module configured to provide amplification functionality such as op-amp functionality. It will be understood that one or more features of the present disclosure can also be implemented in other types of modules.

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc.

FIG. 7shows that one or more compensated amplifiers100(e.g., compensated operational amplifier(s)) having one or more features as described herein can be included in a wireless device400. In some embodiments, such compensated amplifier(s) can include one or more compensation circuits as described herein. Such compensated amplifier(s) can be utilized in various parts of the wireless device400, including some or all of the various components described herein.

In the example ofFIG. 7, the wireless device400can also include a transceiver410for generating an RF signal to be amplified by one or more power amplifiers430and transmitted through an antenna416, and for processing a received RF signal received through the antenna520and amplified by an LNA440.

In the example ofFIG. 7, the amplifiers430can receive their respective RF signal(s) from the transceiver410. The transceiver410is shown to interact with a baseband sub-system408that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver410. The transceiver410is also shown to be connected to a power management component406that is configured to manage power for the operation of the wireless device400.

The baseband sub-system408is shown to be connected to a user interface402to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system408can also be connected to a memory404that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example wireless device400, outputs of the amplifiers430are shown to be matched and routed to an antenna416via their respective duplexers412a-412dand a band-selection switch414. The band-selection switch414can be configured to allow selection of, for example, an operating band or an operating mode. In some embodiments, each duplexer412can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,416). InFIG. 7, received signals are shown to be routed to “Rx” paths that can include, for example, the LNA440.