Diode and transistor design for high speed I/O

An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to integrated circuit devices and more particularly to layout techniques for such devices.

2. Description of Related Art

One area where parasitic capacitance is noted is in input/output (I/O) buffer circuits. For high speed I/O circuits, the parasitic capacitance is one limiter to the fast transitioning edges of the circuit. The larger the capacitance, the slower the charging or discharging, resulting in degraded bus performance. Thus, many efforts have been put forth to reduce the capacitive load and create faster transitions which in turn leads to faster I/O circuits.

The input signals to an integrated circuit, for example, a metal oxide semiconductor (MOS) integrated circuit, are generally fed to transistors. If the voltage applied to the transistor becomes excessive, the gate oxide can break down, the junctions can be destroyed, and the metal to the transistor can be destroyed. Excessive voltages are voltages in excess of the normal operating voltages of the circuit. For example, voltages far in excess of the nominal operating voltage of an integrated circuit, may be impressed upon the inputs to the circuit during either human-operator or mechanical handling operations.

The main source of excessive high voltages to integrated circuits is triboelectricity. Triboelectricity is caused when two materials are rubbed together. A common situation is a person developing very high static voltage (i.e., a few hundred to a few thousand volts) simply by walking across a room or by removing an integrated circuit from its plastic package, even when careful handling procedures are followed. If such a high voltage is applied to the pins of an integrated circuit package, its discharge, referred to as ElectroStatic Discharge (ESD), can cause breakdown of the devices to which the voltage is applied. The breakdown event may cause sufficient damage to produce immediate destruction of the integrated circuit, or it may weaken the device enough that it will fail early in the operating life of the integrated circuit.

In general, all inputs (e.g., pins) of MOS integrated circuits are provided with protection circuits to prevent excessive voltages from damaging the MOS transistors. These protection circuits are normally placed at the input and output pads on a chip and the transistor gates to which the pads are connected. The protection circuits are designed to begin conducting or to undergo breakdown, thereby providing an electrical path to ground (or to the power-supply rail), in the presence of excessive voltages, generally ESD. Since the breakdown mechanism is designed to be non-destructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.

Typically, two types of protection circuits are used to provide protection against ESD damage: Diode breakdown and diode conduction. Diode protection is obtained by using the diode-breakdown or diode-conduction phenomenon to provide an electrical path in the semiconductor, e.g., silicon, substrate that consists of a diffused diode region of a doping type opposite to that of the substrate (for example, p-type and n-type doping, respectively). This diffused region is connected between the input pad and substrate. If a reverse-bias voltage greater than the breakdown voltage of the resultant pn junction is applied, the diffusion region (which otherwise works as a diode) undergoes breakdown. Furthermore, the diffused region will also clamp a negative-going ESD transition at the chip input to one diode drop below the substrate voltage. In CMOS technologies, an additional protection diode can be added by utilizing the pn junction that exists between a p-type region and the body region of the PMOS device (an n-type region that is connected to VCC). This diode is utilized as a protection device when a connection is made between the pad and a p-type region. This diode will generally clamp positive-going transitions to one diode drop above VCC(VCCis generally OV during ESD).

FIG. 2shows a prior art layout of a portion of I/O buffer circuit10ofFIG. 1, specifically illustrating the layout of PMOS device20and ESD protection diode D2.FIG. 2shows PMOS field effect transistor (MOSFET) device20made up of polysilicon gate60separating source region65and drain region70with individual contacts72and75to source and drain regions65and70, respectively. In this embodiment, PMOS device20is in an n-well with p-type (p+doped) source and drain regions65and70, respectively.FIG. 2also shows conventional PMOS diode D2adjacent drain70of PMOS device20. InFIG. 2, p-type area70acts as both a MOSFET drain70and the D2diode anode. Adjacent drain/anode70is an n-type (n+-doped) cathode region80in the n-well.

The critical size of a protection circuit and of a performance circuit are independent of one another. For example, protection diodes D1and D2are sized (i.e., a specific volume of semiconductor material allocated) in accordance with the amount of charge that is contemplated to be dissipated. If the power is dissipated into too small a volume of silicon, the silicon can be heated beyond its melting point and the device destroyed. Transistor devices20and30are likewise sized, for example, in accordance with the voltage drive capabilities of the output driver.

In typical prior art structures, such as the I/O scheme illustrated inFIGS. 1 and 2, the size of PMOS protection D2diode corresponds to the size of the PMOS device because they share a common junction (drain or anode). To accommodate layout concerns and processing conveniences, D2diode is integrated with PMOS device20. In other words, the critical size of either D2diode or PMOS device20determines the size of the corresponding device. If D2diode size is critical and controls, PMOS device20size is enlarged to accommodate the large diode. If, on the other hand, PMOS device20is critical and controls, D2diode size is enlarged beyond what is necessary for an ESD protection circuit. It is to be appreciated that techniques for determining a critical diode size for addressing ESD concerns are well known and, so as not to obscure the invention, will not be discussed herein. For purposes of the invention, it is necessary to understand only that there is a critical, scaleable minimum size, for example, a minimum sized D2diode, that will protect a performance circuit, such as a PMOS device or NMOS device, from ESD damage. Similarly, it is well known in the art how to size performance circuits, such as PMOS drivers. Accordingly, techniques for sizing performance circuits will not be presented herein.

I/O circuit10pad capacitance has several elements, including the NMOS device, the PMOS device, the wire bond or C4pad, the pad to VCCPdiode (D2) and the VSSto pad diode (D1). The diffusion capacitance is high because it is a p+-type diffusion in an n-type well. As noted above, the typical PMOS device20of an I/O circuit includes a D2diode, where one edge of the p-type drain serves as the drain and the other as the diode anode or edge. This sharing makes the diode scale up or down with PMOS device20size. For example, in a mixed voltage environment, when a high voltage technology wants to drive a low voltage I/O, PMOS device20size can be very large. Therefore, D2diode size is much larger than required resulting in extra capacitive loading.

On the other hand, there are also performance circuits that do not need a large PMOS pull-up device. One example is an open drain buffer. To meet the minimum diode size requirement, however, the PMOS size is increased (and generally tied off).

Increasing the size of either the MOSFET device or the ESD protection circuit, e.g., diode, directly leads to increased capacitance. In general, the size of a device (e.g., area, volume, etc.) is directly related to its parasitic capacitance. Thus, what is needed is a layout, particularly an I/O layout, that minimizes parasitic capacitance contributed by the performance and protection circuits without sacrificing the required actions of either circuit.

SUMMARY OF THE INVENTION

An integrated circuit is disclosed. The integrated circuit includes a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit commensurate with dissipating an amount of predetermined charge incident on the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area.

Additional features and benefits of the invention will become apparent from the detailed description, figures, and claims set forth below.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to an integrated circuit and a method of forming an integrated circuit having a performance circuit occupying a first area of an integrated circuit substrate, and a protection circuit coupled to the performance circuit and occupying a second area of the integrated circuit substrate separate from the first area. The partitioning of the performance circuit and protection circuit is scaleable to different device circuit requirements and may be utilized wherever a protection circuit is used to prevent ESD from causing breakdown of integrated circuit devices. The partitioned performance circuit and protection circuit can be utilized in I/O circuits with the objective of maximizing the protection circuit current capability and minimizing the total capacitance at the I/O circuit pad.

The following detailed description describes an improved circuit and a method of forming an improved circuit such as an I/O unit similar to the circuits described with reference toFIGS. 2,1(a), and1(b) and the accompanying text. More particularly, the following description relates to a PMOS device and the D2ESD diode protection circuit for the PMOS device. It is to be appreciated, however, that the invention is not to be limited to I/O circuits or more specifically to PMOS/ESD circuits or CMOS performance circuits and diode protection circuits. Instead, the invention will apply anywhere ESD protection circuits are implemented and the objective is to increase the current capability of the protection circuit and decrease the capacitance of the performance circuit.

FIG. 3illustrates an embodiment of the invention where the ESD protection circuit is partitioned from the performance circuit. In this example, the performance circuit is, for example, PMOS device110of a CMOS I/O circuit in an n-well. ESD protection circuit is, for example, D2diode115.

As illustrated inFIG. 3, the invention contemplates that the protection circuit, such as for example, ESD diode115, is separate from the performance circuit, in this case PMOS device110in terms of area or volume utilization of a semiconductor substrate. In the case of D2diode115, D2diode115is partitioned from PMOS device110. The drain region of PMOS device110and the anode of D2diode115are not formed of a common doped area of the substrate, such as was described inFIG. 2and the accompanying text.

The partitioning of D2diode115from PMOS device110ensures the best utilization of integrated circuit space. The partitioning allows PMOS device110to be scaled up or down while maintaining D2diode115at, for example, the ESD critical size. The partitioning reduces the capacitance (due to the reduction in excess area of either D2diode115or PMOS device110) while retaining the ESD current handling capability over a standard PMOS driver and ESD protection D2diode115. The reduction in capacitance leads to faster transition times, enhancing bus speed. In addition, correctly sized and improved protection circuits (e.g., ESD diodes) and performance circuits (e.g., PMOS drivers) result in an on-chip area reduction when compared to prior art devices.

Comparisons have been made between the partitioned performance/protection circuits and prior art coupled circuits. In one embodiment, a partitioned bimodal driver having a large PMOS device yields an estimated 22% gain in capacitance reduction over a prior art driver coupled bimodal driver. In that same embodiment, the partitioned driver decreases the area for both the performance circuit and protection circuit by an estimated 22%. If a D2diode size equal to that of an input buffer (e.g., input D2diode) is used in the output (PMOS) section, the capacitance will see an estimated 36% capacitance reduction gain, and a 37%=area reduction.

The above discussion illustrates how the capacitance and required area of an I/O driver with protection circuits are reduced by de-coupling or partitioning the protection circuit from the performance circuit. In addition to this reduction, the invention also contemplates that, in the case of a D2diode, in particular, the current discharge capability of a diode can be enhanced. This allows a smaller diode to be used while maintaining the critical current discharging requirements necessary for an ESD protection circuit.

FIG. 4illustrates a layout of partitioned D2diode115. Partitioned D2diode115is formed, for example, in an n-type well120with n-type doped area regions125and145serving as cathodes adjacent a p-type doped region135anode. Contacts130are made to n-type area regions125and145to, for example, dissipate any charge to a suitable power supply. Similarly, contacts140are made to p-type region135to, for example, link the diode to the performance circuit.FIG. 4shows p-type area135illustratively represented as a plurality of unit cells, each unit cell represented by a contact130to the p-type area135. A unit cell is the minimum area necessary to place a contact in a minimum area, e.g., a minimum p-type area.FIG. 5shows a cross-sectional side view taken through line A—A ofFIG. 4. This formation of unit cells of lateral stripes125and145adjacent lateral stripe135is referred to herein as a “striped” design.

As illustrated by the arrows inFIG. 4, when ESD diode115discharges an ESD current, the current travels laterally (as indicated by the arrows) toward two edges of each p-type unit cell of an area135. In diode conduction, the periphery or edges of the unit cell contribute more to current dissipation than the area. Thus, the periphery to area ratio as a measurement of p-type each unit cell of area135to dissipate charge toward the cathode is limited to two edges of each unit, i.e., 2/4 or1/2of the periphery of each unit cell is available.

The invention contemplates, that in addition to the structure shown inFIGS. 4 and 5, the p-type unit cells of the diode may be made as islands.FIG. 6shows one such island configuration. InFIG. 6, unit cells122of p-type doped area region135are formed in n-well120and are located adjacent stripes of n-type regions125and145. Each unit cell122contains a contact130. This formation of unit cell122adjacent lateral stripes135is referred to herein as an “island” design.FIG. 7illustrates a top view of a single unit cell122taken from the diode layout ofFIG. 6. Unit cell122sits in n-well region120separated from stripes of n-type regions125and145adjacent to the opposing sides of unit cell122. In this manner, current paths forming along unit cell122sides substantially parallel to n-type stripes125and145have a direct path toward the n-type stripes, much like the prior art diode structures. In addition, since the edges of unit cell122that are orthogonal or substantially perpendicular to stripes125and145are adjacent n-well120, current150can travel through these edges toward stripes125and145improving the discharge capability of unit cell122over the unit cells described with reference toFIGS. 4 and 5. As can be seen inFIG. 7, by creating unit cell122as an island, the p-type area region can dissipate charge in four directions.

In the condition where the p-type/n-well diode is strongly forward biased, on the order of 0.8V, a conductivity modulation occurs in n-well120. During conductivity modulation, there is sufficient hole injection into n-well120that even the electrons in n-well120exceed the doping density (electrons increase to maintain charge neutrality). Thus, the resistivity of n-well120falls dramatically at high conduction, thereby allowing all sides of unit cell122to conduct almost uniformly. In such cases, from a geometrical consideration, each unit cell122has at least four times the advantage over a diode shared as a drain as in prior art structures (FIG. 2and the accompanying text), or twice the advantage over a striped diode using both edges as described with reference to the embodiment of the invention described inFIGS. 4 and 5and the accompanying text.

If higher current uniformity is desired,FIGS. 8 and 9illustrate a third embodiment of the partitioned protection circuit of the invention. InFIG. 8, unit cells133of p-type doped regions133are formed in n-well120. p-type regions160are formed adjacent each edge of p-type units133. In this manner, each unit cell133becomes an island in n-well120surrounded by n-type region160. This surrounding of unit cell133with n-type region160is referred to herein as a “waffle” design.

FIG. 9shows the current paths165from an edge of one unit cell133ofFIG. 8. The current spreading improves the diode resistance over prior art diode structures. Resistance can be estimated and compared based on the length of the current path. Current path165has a trapezoidal shape, and the effective width of the path can be estimated as the average of the widths of the current source and sink. InFIG. 9, the current source has width “3S” and sink width “5S.” The diode resistance is reduced by current spreading, spreading a distance “4S.” Therefore, the resistive improvement with respect to a linear diode stripe implementation is about “1S/3S”, or 33%.

A comparison between a prior art coupled bimodal driver and an embodiment of a decoupled bimodal driver with improved unit cell diode design of the invention has been made. The de-coupling and improved unit cell diode reduces the capacitance of the bimodal driver by an estimated 34% and reduces the area by an estimated 27% for the waffle diode configuration of the invention compared to the integrated diode of the prior art.

Comparing the island diode presented inFIGS. 6 and 7to the waffle diode presented inFIGS. 8 and 9, one estimate is that the waffle diode occupies approximately half the area of the striped diode with other factors remaining the same. The capacitance savings is calculated at about 34%.

The prior art has reported enhanced conduction at the corners of a unit cell of, for example, an anode area stripe such as described with reference toFIG. 2and the accompanying text. In S. H. Voldman, V. P. Gross, M. J. Hargrove, J. M. Never, J. A. Slinkman, M. P. O'Boyle, T. S. Scott, J. D. Deleckl, “Shallow Trench Isolation Double Diode Electrostatic Discharge Circuit and Interaction With DRAM Output Circuits,” Proc. EOS/ESD Symp. 1992, at page 277, and S. H. Voldman, “ESD Protection In A Mixed Voltage Interface and Multirail Disconnected Power Grid Environment in 0.5 μm and 0.25 μm Channel Length CMOS Technology,” Proc. EOS/ESD Simp., 1994 at 253, the authors report up to 56% higher currents were observed at the ends or corners compared to a length edge of a diode. In those cases, the enhanced conduction at the corner led to diode destruction, because of uneven current sharing between the length edge and the corners leading to higher temperature at the corners. This enhanced conduction was explained as a three-dimensional implant effect where the junction at the corner becomes cylindrical, as opposed to planar over a straight edge for a trench isolated technology. For a Local Oxidation of Silicon (LOCOS) technology, the junction shapes are spherical at the corner and cylindrical at the straight edge).

The solution to the problem proposed by the prior art was to eliminate the unit cell at or near the corners, thus reducing the current conduction at the corners. This could be done, for example, by removing the contacts near the ends of, for example, an anode area stripe, as shown inFIG. 10(a).FIG. 10(a) shows anode stripe190having unit cells1902,1903, and1904. In areas1901and1905, contacts are not placed and viable areas for unit cells are not utilized and a capacitance penalty is paid.

In contrast to the prior art teachings, particularly the teachings of Voldman, et al. noted above, the invention contemplates that the diode consists entirely of corners, with very short straight segments. This is shown inFIG. 10(b) in the contrasting structure of anode area195in accordance with an embodiment of the invention. InFIG. 10(b), each unit cell1951–1955is a diode made up of a multitude (4) of only corners. Therefore, uneven current distribution will not occur. The overall diode performance will be biased toward the enhanced conduction mode and the “problem” recognized by the prior art of enhanced conduction is turned into a beneficial gain.

The p-type to n-well diode is a common ESD protection device employed in many input and input/output pads, including CMOS, mixed voltage, etc. By partitioning the diode and the I/O circuit, and also enhancing the current capability of the diode itself, the area of the semiconductor substrate is significantly reduced and the capacitive load on an I/O pad and on a bus is significantly reduced. The reduction in the capacitive load enhances speed and, to a smaller degree, saves system power. The enhanced current capability of the island and waffle unit cell diodes also reduce the resistance which helps to protect the I/O circuit during an ESD occurrence. Similar area, capacitance, and resistance improvements can be achieved by applying similar principles to other performance/protection circuit, including, in this case, the VSSto pad D1diode. With regard to the D1diode, for example, the partitioning and unit cell designs apply equally as well. In the case of implementing the D1diode in a p-type epitaxial substrate, the D1diode need not be in a well, but can be made simply by placing an n-type tap or region in the substrate and forming a contact to the tap. It is also to be appreciated that, although logic families conventionally use p-type epitaxial substrates, if another type of substrate, e.g., an n-type substrate, is used, the construction of the D1and D2diodes can be suitably adjusted.

Much of the above discussion has focused on optimizing the partitioned diode portion of an I/O circuit. In much the same way, the performance portion of the I/O circuit can similarly be enhanced. As shown inFIG. 2, a prior art PMOS driver20utilizes one edge of drain70of a MOSFET for transistor action and the other for creating an ESD diode. Each contact75to drain region70to define a unit cell has a width W and a capacitance C.

FIG. 11shows a top view of a portion of the partitioned performance circuit in accordance with one embodiment of the invention.FIG. 11shows a PMOS device250in an n-well220. PMOS device250includes polysilicon gate260between source region235and drain region225. Adjacent drain region225opposite the edge adjacent source region235is second source region260. Similarly, polysilicon gate270overlies a semiconductor substrate having p-type doped source region235and drain region245. Adjacent the edge of drain region245opposite source region235is a second source region255. Drain regions225and245are each divided into a plurality of unit cells, each unit cell having a contact230to drain region225and245, respectively.

In the structure shown inFIG. 11, the absence of an integrated protection allows the transistor devices to be scaled independent of the protection circuits, e.g., independent of the ESD protection diode. The absence of an integrated protection circuit such as a diode also allows both sides of drains225and245of respective PMOS transistor devices to be exploited. Thus, for each contact230to a unit cell of drain region225and245, respectively, there is twice the width (2W) for a given capacitance C. Thus, a doubling of the width to capacitance ratio is obtained over the prior art structure shown inFIG. 2.

FIG. 12shows a layout of a second embodiment of the performance portion of the partitioned integrated circuit of the invention. InFIG. 12, individual unit cells280include a p-type doped region285and contact290in n-well220. Here again, a unit cell is that minimum amount of p-typed doped area that will support a contact. Overlying and surrounding the periphery of unit cell280is polysilicon gate295. In this case, p-type doped regions285of unit cells280serve as drain regions for the PMOS FET device. Surrounding drain region285of unit cells280is p-type source region310. Summarizing the unit cell280structure as a waffle structure, one drain contact290serves four sides. Accordingly, the width to capacitance ratio is 4W/C, a gain of four times the width to capacitance ratio over prior art structures such as described inFIG. 2and the accompanying text.

The waffle transistors described above can be analytically or empirically modeled similar to prior art “Ladder” transistors such as shown inFIG. 2and the accompanying text. For a right angle edged waffle MOSFET, the width is four times the inner width (assuming small gate lengths). If the corners are not sharp and a right triangle is placed at each corner, the effective width of the corners is diminished, such that the effective width is estimated by the known relationship:Δ⁢⁢Weff=4⁢Lπ⁢ln⁢LWsL
where Wsis the length of the triangle's side. Straight gate edges should be added to this number.

Another advantage of the waffle design of transistors is that asymmetries arising in I/O circuits due to chip layout are avoided. This occurs generally on the corners of a chip where ladder type devices of the prior art that were laid out in one direction changed direction at the corner, for example, going from vertical to horizontal.FIG. 13shows the example of a ladder type transistor layout in the corner showing horizontal ladder I/O device310and vertical ladder I/O device320. The changing of direction can lead to small asymmetries in the device that in turn lead to skews in timing.FIG. 14shows the waffle transistor design of the invention wherein symmetric I/O devices are used in I/O circuits eliminating asymmetries in corners of the chip and therefore benefiting the timing margin.

By improving the drain width to capacitance ratio in accordance with the embodiments described above, the capacitance on, for example, an I/O pad is reduced for the same current drive capability. This reduction in capacitance leads to faster transition times and enhances bus performance (e.g., bus speed). Further, the four-fold symmetry of the waffle FET design, in particular, reduces effects due to orientation, leading to less skew in the timing of the circuit performance.