Power semiconductor device

A power semiconductor device is such that a notch provided, along a longitudinal end face of an inner lead, in a region of a lead frame to which the inner lead is bonded. A resistor is disposed, adjacent to the inner lead, on the same side as the notch with respect to the inner lead, and a distance between the inner lead and the notch is set to be smaller than a distance between the inner lead and the resistor, and thereby the inner lead, even when shifted in position, comes into no contact with the resistor. Because of this, it is no more necessary that a space be provided around the inner lead taking into consideration a positional shift of the inner lead, and it is possible to secure the heat release area of power semiconductor chips accordingly, and thus to obtain the small-sized and high-powered power semiconductor device.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a power semiconductor device on which switchable power semiconductor chips are mounted.

Description of the Related Art

A power semiconductor device is such that switchable power semiconductor chips are mounted on a lead frame formed in a wiring pattern and are sealed with a molding resin. A power conversion circuit is configured by a single such power semiconductor device or by combining a plurality thereof.

As the power semiconductor chips generate heat by being supplied with a current, causing a rise in the temperature thereof, it is necessary to control the current to be supplied to the power semiconductor chips so as not to exceed a predetermined allowable temperature. In other words, the rise in the temperature of the power semiconductor chips when supplied with the current is controlled, and thereby it is possible to increase the value of the current to be supplied, thus enabling an operation at the maximum power in the range where the temperature of the power semiconductor chips when supplied with the current is at or below the allowable temperature. As a result of this, the performance of the power conversion circuit improves, and the power of a power converter can be brought out to the maximum.

Examples of a method of improving the maximum power in the range where the temperature of the power semiconductor chips is at or below the allowable temperature include: to reduce heat loss caused in the power semiconductor chips, to reduce the amount of heat which the power semiconductor chips receive from the outside, to make it easy to release the amount of heat generated in the power semiconductor chips, and to allow power to be inputted to the brisk at which the temperature of the power semiconductor chips, while being monitored, reaches the allowable temperature.

Also, as the power semiconductor device is supplied with a current via a diversity of members, such as bus bars, a lead frame, and power semiconductor chips, and via the connecting portions of these members, it is required to secure connection resistance reduction and connection reliability. For example, in Patent Literature 1, with the aim of securing the resistance reduction and connection reliability of the power semiconductor device, the semiconductor chips and respective plate-like inner leads are bonded in advance using a conductive bonding material, and the semiconductor chips are mounted on a lead frame at a temperature lower than the temperature at which the conductive bonding material starts to remelt.

The heretofore known power semiconductor device has a problem in that, when connecting the top electrode of a power semiconductor chip and the lead frame with a metal inner lead, solder melted due to heat treatment using a reflow unit, or the like, wets and spreads on the lead frame, causing a positional shift of the inner lead. When the inner lead which is shifted in position interferes with the power semiconductor chip, there is fear of a short circuit failure.

In the heretofore known power semiconductor device, a space of, for example, 5 mm or more is provided around the inner lead in order thereby to avoid contact of the inner lead with an adjacent electronic part due to a positional shift of the inner lead, but this prevents the power semiconductor device from being made smaller in size. Also, there is a problem in that the area of the lead frame in which to mount the inner lead is secured, thus narrowing the area of the lead frame in which to mount the power semiconductor chip, and reducing the heat release area of the power semiconductor chip. As a result of this, there is a problem in that it is not possible to sufficiently suppress a rise in the temperature of the power semiconductor chip, and thus not possible to obtain the high-powered power semiconductor device.

As it is not possible to prevent the solder from wetting and spreading on the lead frame with the method proposed in Patent Literature 1, it is necessary to secure the area in which to mount the inner lead, as well as to provide a space around the inner lead. Also, there is a problem in that the process of bonding the semiconductor chip and inner lead in advance is needed, and the bonding by batch heat treatment using a reflow unit or the like cannot be carried out, leading to a decrease in productivity.

SUMMARY OF THE INVENTION

The invention, having been contrived order to solve the heretofore described kinds of problems, has for its object to obtain a power semiconductor device which suppresses a positional shift of an inner lead when bonding the inner lead to a lead frame and which is small in size and high in power.

The power semiconductor device according to the invention includes a lead frame having a plurality of electrically independent regions; switchable power semiconductor chips mounted on the lead frame; metal inner leads which electrically connect the top electrodes of the respective power semiconductor chips and the lead frame; a conductive bonding member which bonds at least the lead frame and the inner leads; and a resin which covers the lead frame, the power semiconductor chips, and the inner leads, wherein a notch is provided, along the inner lead, in a region of the lead frame to which the inner lead is bonded.

According to the invention, the notch is provided, along the inner lead, in the region of the lead frame to which the inner lead is bonded, whereby the conductive bonding member, which is melted in a region where the lead frame and the inner lead are bonded, only wets and spreads to the notch, and thus it is possible to suppress a positional shift of the inner lead. As it is hereby possible to make the distance between the inner lead and an electronic part adjacent to the inner lead smaller than heretofore known, and thus possible to secure the heat release area of the power semiconductor chip, it is possible to obtain the small-sized and high-powered power semiconductor device.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent form the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereafter, a description will be given, based on the drawings, of a power semiconductor device according to Embodiment 1 of the invention.FIG. 1is a plan view schematically showing the power semiconductor device according to Embodiment 1,FIG. 2is a sectional view of the portion shown by A-A inFIG. 1, andFIG. 3is a sectional view of the portion shown by B-B inFIG. 1. In the individual drawings, identical signs are given to identical and equivalent portions.

A power semiconductor device1according to Embodiment 1 includes a metal lead frame2, switchable power semiconductor chips3a,3b,3c, and3d(collectively described as power semiconductor chips3), current detection resistors4, solder5which is a conductive bonding member, inner leads6which are metal wiring members, and a molding resin8which covers these parts.

The lead frame2configuring the power semiconductor device1has a plurality of electrically independent regions21,22, and23. InFIG. 1, the region21is a P potential lead, the regions22are AC potential leads, and the region23is an N potential lead. The power semiconductor chips3aand3b, which are two upper power semiconductor chips of a three-phase AC circuit, are mounted in the region21, and the power semiconductor chips3cand3d, which are lower power semiconductor chips of the three-phase AC circuit, are mounted one in each of two regions22.

Also, the two regions22in which the respective power semiconductor chips3cand3dare mounted are electrically connected one to each of two regions22, in which no power semiconductor chip3is mounted, by the respective resistors4which are shunt resistors or the like. The regions22in each of which no power semiconductor chip3is mounted are connected one to each external electrode.

Each of the power semiconductor chips3is, for example, a metal-oxide semiconductor field-effect transistor (MOSFET) but, not being limited to this, may be an insulated gate bipolar transistor (IGBT). Silicon (Si), silicon carbide (SiC), silicon nitride (SiN), gallium nitride (GaN), gallium arsenide (GaAs), or the like, is used as the base material of the power semiconductor chip3.

The power semiconductor chip3includes on the chip top a gate portion and a gate electrode in addition to a source electrode which is a chip top electrode, and has a chip bottom electrode on the chip bottom (the gate portion and the electrodes are not shown). The chip top electrode of the power semiconductor chip3is electrically connected by the inner lead6to a region of the lead frame2different from the region thereof in which the power semiconductor chip3is mounted. The gate electrode is connected, by wire bonding, to a gate terminal configured of one portion of the lead frame2. When bonding the chip top electrode and inner lead6with the solder5, the chip top electrode is plated with nickel (Ni), thus meeting soldering specifications.

The lead frame2is one which is formed in a wiring pattern by etching or pressing an alloy plate with copper (Cu), aluminum (Al), or the like, as a base material. The front surface of the lead frame2may be either such that the base metal is exposed therefrom or such that at least one portion thereof is plated.

As shown inFIG. 2, one of the opposing main surfaces of the lead frame2is referred to as a mounting surface2a, while the other is referred to as a heat release surface2b, and after the power semiconductor chips3, the inner leads6, the resistors4, and the like, are mounted on the mounting surface2aand sealed with the molding resin8, a portion unnecessary for electrical wiring is removed. As a result of this, the lead frame2is separated, forming the electrically independent regions21,22, and23. Also, a heatsink10is bonded to the heat release surfaces2bvia an insulating adhesive9high in thermal conductivity.

As shown inFIG. 3, the chip top electrode of the power semiconductor chip3dand the inner lead6are bonded by the solder5, the chip bottom electrode of the power semiconductor chip3dand the region22of the lead frame2are bonded by the solder5, and the inner lead6and the region23of the lead frame2are bonded by the solder5. Also, each of the resistors4and the regions22placed one on either side thereof are also bonded by the solder5.

The inner lead6is one wherein a metal plate is processed in a wiring member shape, and a portion of the inner lead6other than the portion thereof connected to the power semiconductor chip3or lead frame2is in contact with the molding resin8. Also, the inner lead6is disposed so as to be encompassed inside the molding resin8, and when being manufactured, has no portion that supports the inner lead6from the outside. The body of the inner lead6is formed in a direction further away from the lead frame2than the connecting portion, thus preventing a short circuit with the lead frame2.

Also, the sectional area of the body of the inner lead6is determined by the amount of current to be supplied. The power semiconductor device1according to Embodiment 1 is assumed to be supplied with a current of on the order of several amperes to several hundred amperes including even an instantaneously applied current. A through hole and/or a constricted portion is provided in the body of the inner lead6, and thereby it is possible to increase the longitudinal thermal resistance of the inner lead6and thus to reduce the conduction of heat between the power semiconductor chips3.

The power semiconductor device1is such that, as shown inFIG. 4, a notch7is provided, along at least one longitudinal end face6aof the inner lead6, in the region23of the lead frame2to which the inner lead6is bonded. The notch7is provided to narrow the area in which solder which is melted in a portion where the inner lead6and the region23of the lead frame2are bonded, due to heat treatment using a reflow unit or the like, wets and spreads. That is, the melted solder5can only wet and spread to a lead frame end7aof the notch7.

Also, an electronic part (in Embodiment 1, the resistor4) is disposed, adjacent to the inner lead6, on the same side as the notch7with respect to the inner lead6, and the distance between the inner lead6and the notch7is set to be smaller than the distance between the inner lead6and the electronic part. Also, the longitudinal end face6aof the inner lead6and the lead frame end7aof the notch7are set to have an interval of 0.5 mm or more therebetween taking into consideration the positional accuracy of the solder5. As shown inFIG. 4, when the distance between the longitudinal end face6aof the inner lead6and the notch7is represented by L1, and the distance between the longitudinal end face6aof the inner lead6and the electronic part adjacent to the longitudinal end face6ais represented by L2, L1and L2meet 0.5 mm≤L1<L2.

By providing this kind of notch7, the longitudinal end face6aof the inner lead6only moves to the notch7even though a positional shift of the inner lead6occurs when mounting, and thus the inner lead6comes into no contact with the adjacent resistor4. In a heretofore known power semiconductor device, a space of 5 mm or more is provided around the inner lead in order thus to avoid contact of the inner lead with the adjacent electronic part due to a positional shift of the inner lead, but this prevents a reduction in the size of the power semiconductor device. In Embodiment 1, by providing the notch7, it is possible to make the interval between the inner lead6and the resistor1narrower than heretofore known, thus enabling L2to meet L2≤5 mm.

In the example shown inFIG. 4, the notch7is formed in a right triangle, and the lead frame end7awhich is the hypotenuse of the right triangle is disposed parallel to the longitudinal end face6aof the inner lead6. However, any shape of the notch7is acceptable as long as the notch7is shaped along the inner lead6, and the notch7can be formed in a diversity of shapes, such as a quadrangle or an elongated slit. Also, inFIG. 4, the notch7is provided along the one longitudinal end face6aof the inner lead6, but when electronic parts are disposed one adjacent to each of the longitudinal end faces on both sides of the inner lead6, the notches7may be provided one along each of the longitudinal end faces on both sides of the inner lead6.

In Embodiment 1, the two power semiconductor chips3aand3bare mounted in the region21which is the P potential lead, and the power semiconductor chips3cand3dare mounted one in each of the two regions22which are the AC potential leads, but the number and disposition of the power semiconductor chips3are not limited to these. Two or more power semiconductor chips3may be mounted on the P potential lead.

Also, in Embodiment 1, the solder5is used as the conductive bonding member, but when strain occurs due to a change in temperature, or the like, when using a power converter, and a difference in durability occurs in a plurality of bonding portions, solders different in composition may be used from one bonding portion to another. Also, the conductive bonding member is not limited to the solder5, and a conductive resin paste, a sintering paste, or the like, can also be used as the conductive bonding member.

As above, according to Embodiment 1, the notch7is provided, along the inner lead6, in the region23of the lead frame2to which the inner lead6is bonded, whereby the solder5, which is melted in the portion where the lead frame2and the inner lead6are bonded, only wets and spreads to the lead frame end7aof the notch7, and thus it is possible to suppress a positional shift of the inner lead6.

Also, the distance L1between the inner lead6and the notch7is made smaller than the distance L2between the inner lead6and the electronic part which is disposed, adjacent to the inner lead6, on the same side as the notch7with respect to the inner lead6, and thereby the inner lead6comes into no contact with the electronic part even when the inner lead6is shifted in position. Because of this, it is possible to make the distance between the inner lead6and the electronic part smaller than heretofore known.

Also, as it is no more necessary that a space be provided between the inner lead6and the adjacent electronic part, taking into consideration a positional shift of the inner lead6, and the heat release area of the power semiconductor chip3can be secured accordingly, it is possible to obtain the small-sized and high-powered power semiconductor device1. Furthermore, as it is possible to carry out the same bonding by batch heat treatment using a reflow unit or the like, as heretofore known, without adding a new step, as well as to prevent a defect caused by contact of the inner lead6with the adjacent electronic part, it is possible to achieve an improvement in productivity.

FIG. 5is a plan view schematically showing a power semiconductor device according to Embodiment 2 of the invention. A lead frame2configuring a power semiconductor device1A according to Embodiment 2 has a plurality of electrically independent regions21,22,24, and25. InFIG. 5, the region21is a P potential lead, the regions22and the regions25are AC potential leads, and the region24is an N potential lead.

The chip top electrodes of semiconductor chips3cand3dmounted one in each of the regions22are electrically connected to the region24by respective inner leads6. Furthermore, power semiconductor chips3eand3fare mounted, adjacent to the respective inner leads6, in the region24to which the inner leads6are bonded. The chip top electrodes of the power semiconductor chips3eand3fare further electrically connected one to each of the regions25different from the region24by respective inner leads6.

In the case of the power semiconductor device1A according to Embodiment 2, as there is fear of a short circuit failure caused by the interference between the inner leads6bonded to the region24and the respective power semiconductor chips3eand3f, a notch7is provided between each inner lead6and each respective power semiconductor chip3eand3f. As this causes the inner lead6only to move to a lead frame end7aof the notch7even though a positional shift of the inner lead6occurs, the inner lead6comes into no contact with each adjacent power semiconductor chip3eand3f.

Also, the regions22of the lead frame2, in which the respective power semiconductor chips3cand3dare mounted, each have an extended portion12which opposes the notch7and protrudes into the inside of the notch7. A lead frame end12aof the extended portion12is provided parallel to the lead frame end7aof the notch7. As the area of the regions22in which the respective power semiconductor chips3cand3dare mounted increases by providing these kinds of extended portions12, the heat release area of the power semiconductor chips3cand3dincreases, thus suppressing a rise in the temperature of the power semiconductor chips3cand3d. As other configurations of the power semiconductor device1A are the same as in Embodiment 1, a description thereof is omitted.

In the example shown inFIG. 5, the notch7is formed in a triangle, and the lead frame end7awhich forms one side of the triangle is disposed parallel to a longitudinal end face6aof the inner lead6. However, any shape of the notch7is acceptable as long as the notch7is shaped along the inner lead6, and the notch7can be formed in a diversity of shapes, such as a quadrangle or an elongated slit.

According to Embodiment 2, the notch7is provided between each inner lead6and each respective power semiconductor chip3eand3f, which are mounted in the same region24, whereby solder5, which is melted in the portion where the lead frame2and the inner lead6are bonded, only wets and spreads to the lead frame end7aof the notch7, and thus it is possible to suppress a positional shift of the inner lead6. Because of this, it is possible to make the distance between each inner lead6and each respective power semiconductor chip3eand3fsmaller than heretofore known.

Also, as the inner lead6, even when shifted in position, comes into no contact with each respective power semiconductor chip3eand3f, it is possible to prevent a short circuit failure caused by the interference between the inner lead6and each respective power semiconductor chip3eand3f. Furthermore, the extended portion12opposite to the notch7is provided in each of the regions22where the respective power semiconductor chips3cand3dare mounted, whereby the heat release area of the power semiconductor chips3cand3dincreases, and thus it is possible to suppress a rise in the temperature of the power semiconductor chips3cand3d.

For these reasons, according to Embodiment 2, the small-sized and high-powered power semiconductor device1A can be obtained. The invention is such that the individual embodiments can be freely combined, or any of the individual embodiments can be appropriately modified or omitted, within the scope of the invention.