METHODS AND APPARATUS TO SUPPORT POST-MANUFACTURING FIRMWARE EXTENSIONS ON COMPUTING PLATFORMS

Methods, apparatus, systems, and articles of manufacture are disclosed to support post-manufacturing firmware extensions on computing platforms. An example non-transitory computer readable storage medium comprising instructions that, when executed, cause one or more processors to at least: based on a soft strap status indicator stored in a serial peripheral interface (SPI) memory, extract a silicon initialization code profile from the SPI memory and initialize the processor based on the silicon initialization code extension profile.

FIELD OF THE DISCLOSURE

This disclosure relates generally to computing devices and, more particularly, to methods and apparatus to support post-manufacturing firmware extensions on computing platforms.

BACKGROUND

Most computing devices utilize, low-level computing device software (e.g., basic input/output systems (BIOS) and/or unified extensible firmware interface (UEFI)) to boot up and perform low-level operation in a computer system (e.g., prior to booting of an operating system and/or user application). Boot operations managed by the low-level software perform multiple configuration actions such as configuring platform hardware such as the components of a personal computer (PC).

The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other.

Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events. As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmed with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmed microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of the processing circuitry is/are best suited to execute the computing task(s).

DETAILED DESCRIPTION

Developers of processor-based devices expect such devices to boot in a manner consistent with specifications outlined by a manufacturer of the type of processor selected by the developers. In examples related to personal computer (PCs), boot operations may be managed by basic input/output systems (BIOS), unified extensible firmware interface (UEFI), or other firmware interface. As used herein, references to “BIOS” refer to the process and/or mechanism by which a platform is booted from a previously powered-off state and any such reference may apply equally to traditional BIOS, UEFI, or any other type of firmware interface. In other words, while UEFI and other firmware interfaces are not noted throughout for simplicity, it is understood that the references to BIOS may be substituted with references to UEFI and/or any other type of firmware interface. Generally speaking, boot operations occur immediately after power is applied to a platform, but prior to an operational point where an operating system (OS) has control of that platform. The boot operations initialize platform hardware (e.g., memory, buses, drives, keyboards, displays, etc.) so that such hardware is in a state to be handed-off to the OS.

While the PC industry has a mature market for BIOS vendors, in some examples, customizing the BIOS involves engaging BIOS vendors for development expertise and/or licensing to use one or more BIOS solution(s). Even in circumstances where a BIOS vendor agrees to license one or more solutions to facilitate platform booting, such solutions may remain proprietary, thereby leaving the platform developer with a degree of dependence upon outside expertise rather than a controlled and/or otherwise fully owned platform solution.

The platform developer is typically knowledgeable of key aspects of the platform being developed, particularly with regard to on-board sensors and/or devices. However, many platform developers still rely on third party vendors for processing resources (e.g., processors, microprocessors, microcontrollers and/or, more generally, processing silicon). While the platform developers may have expertise in most aspects of their platform, gaining similar expertise and/or knowledge regarding the processing resources and/or processing resource initialization requirements may require adherence to voluminous and/or complicated processing vendor specifications and manuals.

To relinquish valuable developer development time, silicon initialization code (SIC) components (e.g., binaries, application programming interfaces (APIs)) facilitate a focused configuration effort of processing resources of a platform. In some examples, the SIC components are associated with the Intel® Firmware Support Package (FSP). Rather than require the developer to become an expert in third party processing resources, the SIC components allow the processing resources to be properly initialized during a booting phase of the platform through a bootloader (e.g., coreboot or EDK II). Upon completion of processing resource initialization via the SIC components, developer-specific boot instructions may be implemented to continue with initialization of one or more other portions of the platform for which the developer likely has expertise.

The boot operations for a PC configure hardware of the PC including: controlling settings such as clock speed and ring speed, enabling or disabling hardware component ports such as those containing video cards or graphics cards, enabling or disabling hyperthreading, etc. Typically, these BIOS (or other low level operation) settings can only be modified via a setup screen which allows a user to enable or disable a feature. The setup screen may only contain a subset of the features and settings controlled by the BIOS, thus limiting the user's ability to customize their platform for their usage needs. Furthermore, some platforms do not contain a BIOS setup infrastructure making platform configuration even more challenging. While it would be possible for an OEM to distribute an updated BIOS for end-user usage needs, such process is expensive and, therefore, BIOS updates by an OEM are typically limited during the life of a platform.

Because early initialization software can have a tightly coupled binding to underlying processor hardware, the silicon manufacturer may provide early initialization software (e.g., SIC), rather than it being implemented by the OEM BIOS. The SIC may be used in an environment to load code, guarantee its provenance, and after execution of the SIC, hand control off to OEM BIOS in a seamless fashion. The SIC may be used to perform low level aspects of memory initialization (e.g., training and diagnostics), key initialization code for memory controllers and interconnect links, as well as potentially provide runtime support for various processor and system features.

Examples disclosed herein facilitate firmware updates and/or configuration to allow for customization of a platform according to user needs (e.g., after a computing device has left a manufacturer). In some examples, silicon reference policies within an SIC can be dynamically controlled. In some examples, the serial peripheral interface (SPI) flash image can be modified to control hardware configuration policies. In examples disclosed herein, platform configuration can occur without altering the BIOS portion of the SPI flash (e.g., without the need for deploying a new version of the BIOS, UEFI, and/or firmware interface). In some examples, a cloud service (e.g., an applet store) can facilitate distribution of applets, applications, modules, etc. that may be retrieved to a computing platform and may operate to configure the platform without modifying BIOS code after the platform leaves a manufacturer.

FIG. 1illustrates an example system100constructed in accordance with the teachings of this disclosure and including a user device102. The user device102is communicatively coupled to a software repository105via a network107. The example software repository105ofFIG. 1provides means for hosting SIC applets106. The SIC applets106can be provided to the software repository105by one or more of a silicon manufacturer, an operating system (OS) vendor, and/or a third-party SIC applet developer.

The example user device102can be a personal computing (PC) device (e.g., laptop, desktop, electronic tablet, a hybrid or convertible PC, etc.), a server computing device, or any other type of computing device. In some examples, the user device102includes a mobile device such as a smartphone.

In the illustrated example ofFIG. 1, the user device102includes a processor104. The processor104of the example user device102ofFIG. 1includes a software portion108. The example software portion108includes storage devices (not shown) storing user applications. One example user application is SIC app management instructions110. The SIC app management instructions110provide means for managing SIC applets106. For example, the SIC app management instructions110can download an SIC applet106from the software repository105. The SIC app management instructions110can download an SIC applet106in response to a request (e.g., from a user116or a cloud administrator118). In some examples, the SIC app management instructions110provide a graphical user interface (GUI) with which a user116can interact. In other examples, the user116and/or the cloud administrator118can interact with the SIC app manager via command line instructions. In some examples, the SIC app management instructions110download one SIC applet106. In other examples, the SIC app management instructions110download a plurality of SIC applets106. The SIC app management instructions110can store the downloaded SIC applet(s)106in the user device102. The storage location of the SIC applet(s) can be inside and/or outside the processor104.

The example SIC app management instructions110ofFIG. 1send a notification to other components of the user device102indicating that the SIC applet106is available. For example, the notification may include a status of the SIC applet106and a storage location of the SIC applet106in the user device102. In some examples, the notification is sent in response to an initial download of the SIC applet106. In other examples, the notification may be sent in response to input (e.g., due to a request from a user116or from a cloud administrator118).

The example user device102ofFIG. 1includes a hardware portion120. The example hardware portion120includes one or more processors, memories, input/output devices, etc. The example hardware portion120contains one or more serial peripheral interface (SPI) flash device(s)114. In some examples, the SPI flash device(s)114are non-volatile memory such as an electrically erasable and programmable read only memory (EEPROM). A layout of the example SPI flash device114is described below in conjunction withFIG. 4. Contents of the SPI flash device114can be based on an image file (e.g., the IFWI). The example SPI flash device114ofFIG. 1is used to perform boot operations of the user device102. In the example ofFIG. 1, the SPI flash device114includes a BIOS122.

The example SPI flash device114includes an SIC extension profile119. The example SIC extension profile119is one byte of memory containing bits corresponding to SIC extension profile status, debug profile mode, boot mode, low power mode profile status, gaming mode profile status, performance mode profile status, etc.

The example hardware includes a chipset124. The chipset124is in communication with the SPI flash device(s)114and a processor126(e.g., a central processing unit (CPU)). Interface circuitry (not shown) may provide access to the SPI flash device(s)114from the chipset124or any other hardware or software component of the user device102. In some examples, the chipset124is a Platform Controller Hub (PCH). The example chipset124includes a trusted execution environment128. In some examples, the trusted execution environment128is an Intel® Management Engine (ME). The trusted execution environment128includes silicon initialization code (SIC)130. In other examples, the SIC130can be located on a SPI flash device (e.g., SPI flash device114ofFIG. 1) and/or anywhere else in the hardware120of the user device102. The example SIC130is platform independent code (e.g., can be executed on any given platform regardless of the specific of the machine) whereas the example BIOS122which is platform dependent. During boot operations, the example SIC130initializes memory and/or silicon components (e.g., processors, etc.) of the user device102. In some examples, the SIC130is a Firmware Support Package (FSP). Components of the example SIC130are described in further detail below in conjunction withFIG. 2.

The trusted execution environment128includes an out of band manager (OOBM)132. The OOBM132allows remote hardware and firmware management of the user device102. For example, a cloud administrator118can perform management activity (e.g., power up, power down, block network traffic, etc.) on the user device102remotely via the OOBM132. In some examples, the OOBM132is Active Management Technology (AMT). The trusted execution environment128ofFIG. 1includes a secure storage134. The example secure storage134stores one or more SIC applet(s)106such as SIC applet106a and SIC applet106b.

Returning to the software portion108, the user device102ofFIG. 1includes flash image tool instructions112. The flash image tool instructions112configure and creates a firmware image. For example, the flash image tool instructions112can create an integrated firmware image (IFWI) which can be used for configuring the SPI flash device114. The flash image tool instructions112configure settings of the firmware image (e.g., IFWI). In some examples, the SIC applet106downloaded by the SIC app management instructions110has provision to override one or more of the settings of the firmware image within the flash image tool instructions112. In some examples, the SIC applet106overrides the settings during runtime operation (e.g., after boot operations) of the user device102. In other examples, the example flash image tool instructions112can configure the settings of the firmware image based on input (e.g., by a user116and/or a cloud administrator118).

The example software portion108of the user device102includes firmware update instructions138. The example firmware update instructions138flash an image (e.g., IFWI) to the SPI flash device114. The example software portion108of the user device102includes operating system (OS) load instructions140. In some examples, the firmware update instructions138flash the image (e.g., IFWI) onto the SPI flash device114in response to instructions from the OS load instructions140.

The example hardware ofFIG. 1includes platform intellectual property (IP) blocks136(e.g., NVM store142, configuration logic circuitry144, user logic circuitry146, update logic circuitry148, etc.). The example platform IP blocks136provide a reusable unit of logic, cell, or integrated circuit layout. For example, the BIOS122and/or the SIC130can initialize the platform IP blocks136during boot operations to initialize silicon components (e.g., CPU, companion chips, etc.).

In some examples, the platform IP blocks136are located within the processor104. In other examples, the platform IP blocks136are located outside of the processor104. In some examples, the platform IP blocks136are provided by the silicon manufacturer. In other examples, the platform IP blocks136are provided by a third-party.

FIG. 2is a block diagram of an example implementation of the SIC130to operate in the system ofFIG. 1. The example SIC130ofFIG. 2includes example memory initialization instructions202, example extension profile handler instructions204, and example silicon initialization instructions206.

The example memory initialization instructions202initialize temporary and/or permanent memory and/or performs early silicon initialization. For example, during boot operations, a bootloader may pass control to the SIC as per standard flow. The example memory initialization instructions202then perform memory initialization steps (e.g., setting up memory addressing).

The example extension profile handler instructions204retrieve an SIC extension profile119. For example, during boot operations after the SIC130has received platform control, the extension profile handler instructions204read the SPI flash114to obtain the SIC extension profile119. The example extension profile handler instructions204update hardware configuration based on the SIC extension profile119as discussed below in conjunction withFIG. 6. The example extension profile handler instructions204read the SIC extension profile119to determine the status of hardware and/or boot modes as set by the SIC extension profile119. For example, the extension profile handler instructions204can determine a bit in the SIC extension profile119corresponding to an SIC extension profile status is set to 1 (e.g., enable). In some of these examples, the extension profile handler instructions204can determine a bit in the SIC extension profile119corresponding to a profile status (e.g., lower power mode profile status, gaming mode profile status, performance mode profile status, etc.) is set to 1 (e.g., enable). Based on the hardware and/or boot modes set in the SIC extension profile, the example extension profile handler instructions204set hardware configuration settings within the SIC130.

The example silicon initialization instructions206initialize silicon components (e.g., processor126, graphics processing units (GPUs), etc.) of the user device102. In some examples, the silicon initialization instructions206initialize the silicon components (e.g., processor126, GPUs, etc.) based on the SIC extension profile119. For example, if the profile reader determines that the SIC extension profile status is set to enable and the low power mode profile status is set to enable, the silicon initializer uses the hardware settings configured by the extension profile handler instructions204to initialize the silicon components (e.g., processor126, GPUs, etc.) of the user device102.

FIG. 3is a block diagram of an example layout of the SPI flash device114ofFIG. 1. The example SPI flash device114includes a flash descriptor region302. The example flash descriptor region302includes a description of the layout of the SPI flash device114and/or configuration parameters for the user device102. The example SPI flash114device includes a BIOS region304. In other examples, the BIOS is located on a separate flash device from SPI flash device114. In some examples, the BIOS region304includes the SIC130. The example SPI flash device114includes a trusted execution environment firmware region306. The example SPI flash device114includes additional regions such as a gigabit ethernet (GbE) region308, an embedded controller region310, and/or any other regions. In some examples, one or more of the above regions is omitted from the SPI flash device114.

FIG. 4is a block diagram of an example layout of the flash descriptor region320ofFIG. 3. The example flash descriptor region320as illustrated inFIG. 4includes one or more reserved regions402and416, a signature region404, a descriptor map region406, a component region408, a region410, a master region412, a chipset soft strap region414, a trusted execution environment vendor-specific component capabilities (TEE VSCC) table418, a descriptor upper map region420, and an OEM section422. In some examples, the flash descriptor region320includes regions not displayed inFIG. 4. In some examples, not all the regions displayed inFIG. 4are included in the flash descriptor region320. The example chipset soft strap region414includes configurable option selections that are loaded into the chipset124during boot operations.

FIG. 5is a block diagram of an example layout of the chipset soft strap region414ofFIG. 4. The chipset soft strap region414illustrated inFIG. 5includes a first region502including chipset strap records (CHSTRP)0-17. The example chipset soft strap region414ofFIG. 5also includes the SIC extension profile119as discussed above in conjunction withFIG. 2. As explained above, the example extension profile handler instructions204find, read, and extract one or more SIC extensions from the SIC extension profile119during boot operations.

FIG. 6is a block diagram of an example layout of the SIC extension profile119ofFIG. 5. In the example ofFIG. 6, the SIC extension profile119is 1 byte in width. In other examples, the SIC extension profile119may be larger or smaller than one 1 byte. The example SIC extension profile119includes an example SIC extension profile status region602, an example debug profile mode604, an example BIOS boot mode606, an example lower power mode profile status608, an example gaming mode profile status610, and an example performance mode profile status612.

The SIC extension profile status region602ofFIG. 6includes 1 bit wherein a setting of0corresponds to disable and a setting of1corresponds to enable. For example, if the SIC extension profile status region602is set to0(e.g., disable), hardware configuration based on the SIC extension119is disabled. Alternatively, if the SIC extension profile status region602is set to1(e.g., enable), hardware configuration based on the SIC extension119is enabled. In one example, a default value of the SIC extension profile status region602is0(e.g., disable).

The example debug profile mode region604illustrated inFIG. 6includes 3 bits corresponding to debug settings (e.g., CPU, memory, chipset, TBT/USB4, etc.). For example, if the debug profile mode region604is set to000, CPU is selected for debug. In another example, if the debug region is set to001, memory is set for debug.

The example BIOS boot mode region606ofFIG. 1includes 1 bit wherein a setting of0corresponds to release and a setting of1corresponds to debug. For example, if the BIOS boot mode region606is set to1(e.g., debug), the BIOS122boots into debug mode corresponding to the component indicated by the debug profile mode604(e.g., CPU). In another example, the BIOS boot mode region606is set to0(e.g., release). In this example, the BIOS122does not boot into debug mode. In one example, a default value of the BIOS boot mode region606is0(e.g., release).

In the example ofFIG. 6, the SIC extension profile119includes multiple profile status indicates for selecting to enable various customizable configurations: the lower power mode profile status region608, the gaming mode profile status region610, and the performance mode profile status region612. In other examples, profile status regions corresponding to alternative modes can be included alternatively and/or additionally to the ones included inFIG. 6. For example, the example SIC extension profile119can contain regions corresponding to profile status for modes that are different than those represented inFIG. 6(e.g., video conferencing mode, low temperature mode, quiet mode, dark mode, bright mode, etc.).

The profile status regions of the SIC extension profile119(e.g., the lower power mode profile status region608, the gaming mode profile status region610, and the performance mode profile status region612) include 1 bit wherein a setting of0corresponds to disable and a setting of1corresponds to enable. For example, if the gaming mode profile status region610is set to0(e.g., disable), hardware configuration based on the gaming mode profile is disabled. Alternatively, if the gaming mode profile status region610is set to1(e.g., enable) and the SIC extension profile status region602is set to1(e.g., enable), the SIC configures the hardware based on a gaming mode profile (e.g., setting parameters that correspond to increasing performance related to gaming). In one example, a default value of the profile status regions608,610, and612is0(e.g., disable).

As explained above in conjunction withFIG. 1, the example SIC applet106downloaded by the SIC app management instructions110has provision to override one or more of the settings (e.g., factory settings) of the firmware image via the flash image tool instructions112. In the illustrated example, the SIC applet106has provision to override one or more of the settings of the SIC extension profile119. For example, the SIC applet106can modify the gaming mode profile status region610to1(e.g., enable) and the SIC extension profile status region602to1(e.g., enable) within the flash image tool instructions112. Once the updated flash image is loaded onto the SPI flash device114, the hardware of the user device102is configured based on the updated SIC extension profile119.

While the illustrated examples utilize a value of 1 for enable and0for disable, any other arrangement or values may be utilized to indicate enable or disable.

While an example manner of implementing the user device102ofFIG. 1is illustrated inFIG. 1, one or more of the elements, processes, and/or devices illustrated inFIG. 1may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example processor104, the example SIC app management instructions110, the example flash image tool instructions112, the example firmware update instructions138, the example OS load instructions140, the example SIC130, and/or, more generally, the example user device102ofFIG. 1, may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the example processor104, the example SIC app management instructions110, the example flash image tool instructions112, the example firmware update instructions138, the example OS load instructions140, the example SIC130, and/or, more generally, the example user device102, could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the example processor104, the example SIC app management instructions110, the example flash image tool instructions112, the example firmware update instructions138, the example OS load instructions140, and/or the example SIC130is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including the software and/or firmware. Further still, the example user device102ofFIG. 1may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated in FIG.1, and/or may include more than one of any or all of the illustrated elements, processes and devices.

While an example manner of implementing the SIC130ofFIG. 1is illustrated inFIG. 2, one or more of the elements, processes, and/or devices illustrated inFIG. 2may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example memory initialization instructions202, the example extension profile handler instructions204, the example silicon initialization instructions206and/or, more generally, the example SIC130ofFIG. 1, may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the example memory initialization instructions202, the example extension profile handler instructions204, the example silicon initialization instructions206, and/or, more generally, the example SIC130, could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the example memory initialization instructions202, the example extension profile handler instructions204, and/or the example silicon initialization instructions206is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including the software and/or firmware. Further still, the example SIC130ofFIG. 1may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated inFIG. 2, and/or may include more than one of any or all of the illustrated elements, processes and devices.

FIG. 7is a flowchart representative of example machine readable instructions and/or example operations700that may be executed and/or instantiated by processor circuitry to configure platform hardware without modifying the BIOS. The machine readable instructions and/or operations700ofFIG. 7begin at block702, at which the SIC app management instructions110download an SIC applet106from the software repository105. For example, the SIC app management instructions110download an SIC applet106corresponding to hardware settings to configure the device platform into a lower power mode. At block704, in response to the applet download, the flash image tool instructions112updates the flash descriptor region302setting of a flash image and creates a flash image based on the updated descriptor portion. For example, in response to the download of the lower power mode applet, the flash image tool instructions112can set a profile status region (e.g., lower power mode profile status region608) of the chipset soft strap region414in the flash descriptor region302to1(e.g., enable). Further, the flash image tool instructions112create an IFWI including the updated flash descriptor region302. In the updated IFWI, only the flash descriptor region302is modified. The additional regions (e.g., the BIOS region304) of the IFWI remain unchanged. In some examples, the IFWI is included in a UEFI capsule.

At block706, the firmware update instructions138flash the updated flash image including the updated flash descriptor region302onto the SPI flash device114as described in more detail below in conjunction withFIG. 8. At block708, the SIC130initializes the platform hardware based on SIC applet106configuration settings as described in more detail below in conjunction withFIGS. 9, 10 and 11.

FIG. 8is a flowchart representative of example machine readable instructions and/or example operations706that may be executed and/or instantiated by processor circuitry to update the flash image on the SPI flash device114. The illustrated example ofFIG. 8represents a firmware image update mechanism based on UEFI capsules. In other examples, another firmware update mechanism can be implemented to flash the SPI flash device114.

At block802, the firmware update instructions138are invoked by the processor104. In some examples, the firmware update instructions138are invoked in response to the creation of the updated IFWI by the flash image tool instructions112. In some examples, the firmware update instructions138are a UEFI service (e.g., UpdateCapsule). In some examples, the firmware update instructions138are invoked during runtime (e.g., after boot operations). In the illustrated example, the system is reset after the firmware update instructions138are invoked. At block804, the OS load instructions140locate the firmware image (e.g., IFWI and/or UEFI capsule) and puts the firmware image (e.g., IFWI and/or UEFI capsule) on memory. In some examples, the system is reset after the OS load instructions140put the firmware image on the memory. At block806, the OS load instructions140find the firmware image (e.g., IFWI and/or UEFI capsule) and invokes an update call. For example, the OS load instructions140locate the IFWI including the updated flash descriptor region302and invoke the firmware update instructions138based on the location of the IFWI. The firmware update instructions138flash the updated IFWI onto the SPI flash device114, thus updating the flash descriptor region302of the SPI flash device114. At block808, the system performs a reset and the flow passes back to block708ofFIG. 7.

FIG. 9is a flowchart representative of example machine readable instructions and/or example operations708that may be executed and/or instantiated by processor circuitry to initialize the platform based on the SIC applet106. At block902, power is applied to the user device102and the user device102comes out of reset. At block904, the SIC130receives control of the platform. For example, after the user device102comes out of reset, core microcode or other logic in the processor104may locate the SIC103and transfer platform control to the SIC103to continue boot operations. In some examples, the example memory initialization instructions202perform temporary and/or non-temporary memory initialization. At block906, the example extension profile handler instructions204locate the SIC extension profile119as discussed below in further detail in conjunction withFIG. 10. At block908, the silicon initialization instructions206of the SIC130initialize platform silicon components based on the policies set in the SIC extension profile119as discussed below in further detail in conjunction withFIG. 11.

FIG. 10is a flowchart representative of example machine readable instructions and/or example operations908that may be executed and/or instantiated by processor circuitry to locate the SIC extension profile119. At block1002, the SIC130accesses the SPI flash device114. For example, the SIC130uses a structure such as a pre-EFI initialization module (PEIM)-to-PEIM interface (PPI) to communicate with the SPI flash device114. At block1004, the extension profile handler instructions204read the flash descriptor region302of the SPI flash device114to determine the location of the chipset soft strap region414on the SPI flash device114. For example, the extension profile handler instructions204read the descriptor map portion406of the flash descriptor region302. The example descriptor map portion406contains the location of the chipset soft strap region414. In some examples, the chipset soft strap region414is stored in a different location within the flash descriptor region302. At block1006, the extension profile handler instructions204determine the location of the SIC extension profile119within the flash descriptor region302. For example, the extension profile handler instructions204add a known offset corresponding to the SIC extension profile119to the location indicating the start of the chipset soft strap region414.

FIG. 11is a flowchart representative of example machine readable instructions and/or example operations908that may be executed and/or instantiated by processor circuitry to initialize the user device102based on the SIC applet106. At block1102, the extension profile handler instructions204check the SIC extension profile status region602of the SIC extension profile119. If the SIC extension profile status region602is set to0(e.g., disable), configuration of the hardware based on the SIC extension profile119is disabled (block1104). If the SIC extension profile status region602is set to1(e.g., enable), the extension profile handler instructions204continue reading the SIC extension profile119to determine hardware configuration settings. At block1106, the extension profile handler instructions204read the debug profile mode region604to determine a selected component for debug. For example, if the debug profile mode region604is set to000, CPU is selected for debug. At block1108, the extension profile handler instructions204read the BIOS boot mode region606. If the BIOS boot mode region606is set to1(e.g., debug), the platform is booted into debug mode using the selected component of the debug profile mode604(block1110). If the BIOS boot mode region606is set to0(e.g., release), the extension profile handler instructions204continue checking the SIC extension profile119to determine a custom boot mode which is set to enable (block1112). For example, the extension profile handler instructions204can determine that the gaming mode profile status region610is set to1(e.g., enable). At block1114, the extension profile handler instructions204set hardware configuration policies based on the enabled custom boot mode. For example, the extension profile handler instructions204use the below pseudocode to set hardware settings.

At block1116, the silicon initialization instructions206initialize the silicon components (e.g., processor126, GPUs, etc.) of the user device102based on the hardware configuration of block1114. For example, the silicon initialization instructions206use the platform IP block136logic to initialize the processor104and/or other silicon components of the user device102.

In some examples, the apparatus includes means for extracting the SIC extension profile119from the SPI flash device114. For example, the means for extracting may be implemented by the extension profile handler instructions204. In some examples, the extension profile handler instructions204may be implemented by machine executable instructions such as that implemented by at least blocks708ofFIG. 7, 906ofFIG. 9, 1002, 1004, 1006ofFIG. 10, 1102, 1104, 1106, 1108, 1110, 1112, 1114ofFIG. 11, executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the extension profile handler instructions204are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the extension profile handler instructions204may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In some examples, the apparatus includes means for initializing a processor based on the SIC extension profile119. For example, the means for initializing may be implemented by the silicon initialization instructions206. In some examples, the silicon initialization instructions206may be implemented by machine executable instructions such as that implemented by at least blocks708ofFIG. 7, 908ofFIG. 9, 1114, 1116ofFIG. 11, executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the silicon initialization instructions206are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the silicon initialization instructions206may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In some examples, the apparatus includes means for modifying the SIC extension profile119during runtime based on the SIC applet106retrieved from the software repository105. For example, the means for modifying may be implemented by the flash image tool instructions112and/or the SIC applet106. In some examples, the flash image tool instructions112and/or the SIC applet106may be implemented by machine executable instructions such as that implemented by at least blocks702,704,706ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the flash image tool instructions112and/or the SIC applet106are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the flash image tool instructions112and/or the SIC applet106may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In some examples, the apparatus includes means for generating a flash image based on the SIC applet106. For example, the means for generating may be implemented by the flash image tool instructions112. In some examples, the flash image tool instructions112may be implemented by machine executable instructions such as that implemented by at least blocks702,704,706ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the flash image tool instructions112are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the flash image tool instructions112may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In some examples, the apparatus includes means for flashing the flash image onto the SPI flash device114. For example, the means for flashing may be implemented by the firmware update instructions138. In some examples, the firmware update instructions138may be implemented by machine executable instructions such as that implemented by at least blocks706ofFIG. 7, 802, 804, 806ofFIG. 8executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the firmware update instructions138are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the firmware update instructions138may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In some examples, the apparatus includes means for enabling initialization of the processor based on the SIC extension profile119. For example, the means for enabling may be implemented by the flash image tool instructions112and/or the SIC applet106. In some examples, the flash image tool instructions112and/or the SIC applet106may be implemented by machine executable instructions such as that implemented by at least blocks702,704,706ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the flash image tool instructions112and/or the SIC applet106are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the flash image tool instructions112and/or the SIC applet106may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In some examples, the apparatus includes means for associating the SIC extension profile119with a performance setting for the processor. For example, the means for enabling may be implemented by the flash image tool instructions112and/or the SIC applet106. In some examples, the flash image tool instructions112and/or the SIC applet106may be implemented by machine executable instructions such as that implemented by at least blocks702,704,706ofFIG. 7executed by processor circuitry, which may be implemented by the example processor circuitry1212ofFIG. 12, the example processor circuitry1300ofFIG. 13, and/or the example Field Programmable Gate Array (FPGA) circuitry1400ofFIG. 14. In other examples, the flash image tool instructions112and/or the SIC applet106are implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the flash image tool instructions112and/or the SIC applet106may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

FIG. 12is a block diagram of an example processor platform1200structured to execute and/or instantiate the machine readable instructions and/or operations ofFIGS. 7, 8, 9, 10, and 122to implement the user device102ofFIG. 1. The processor platform1200can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device.

The processor platform1200of the illustrated example includes processor circuitry1212. The processor circuitry1212of the illustrated example is hardware. For example, the processor circuitry1212can be implemented by one or more integrated circuits, logic circuits, FPGAs microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry1212may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry1212implements the example SIC app manager, the example flash image tool, the example capsule updater, the example profile reader, and the example silicon initializer.

The processor circuitry1212of the illustrated example includes a local memory1213(e.g., a cache, registers, etc.). The processor circuitry1212of the illustrated example is in communication with a main memory including a volatile memory1214and a non-volatile memory1216by a bus1218. The volatile memory1214may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory1216may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory1214,1216of the illustrated example is controlled by a memory controller1217.

The processor platform1200of the illustrated example also includes interface circuitry1220. The interface circuitry1220may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a PCI interface, and/or a PCIe interface.

In the illustrated example, one or more input devices1222are connected to the interface circuitry1220. The input device(s)1222permit(s) a user to enter data and/or commands into the processor circuitry1212. The input device(s)1222can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

One or more output devices1224are also connected to the interface circuitry1220of the illustrated example. The output devices1224can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry1220of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.

The processor platform1200of the illustrated example also includes one or more mass storage devices1228to store software and/or data. Examples of such mass storage devices1228include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices, and DVD drives.

The machine executable instructions1232, which may be implemented by the machine readable instructions ofFIGS. 7, 8, 9, 10, and 11may be stored in the mass storage device1228, in the volatile memory1214, in the non-volatile memory1216, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG. 13is a block diagram of an example implementation of the processor circuitry1212ofFIG. 12. In this example, the processor circuitry1212ofFIG. 12is implemented by a microprocessor1300. For example, the microprocessor1300may implement multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores1302(e.g., 1 core), the microprocessor1300of this example is a multi-core semiconductor device including N cores. The cores1302of the microprocessor1300may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores1302or may be executed by multiple ones of the cores1302at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores1302. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowchart ofFIG. 7.

The cores1302may communicate by an example bus1304. In some examples, the bus_04may implement a communication bus to effectuate communication associated with one(s) of the cores_02. For example, the bus1304may implement at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the bus1304may implement any other type of computing or electrical bus. The cores1302may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry1306. The cores1302may output data, instructions, and/or signals to the one or more external devices by the interface circuitry1306. Although the cores1302of this example include example local memory1320(e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor1300also includes example shared memory1310that may be shared by the cores (e.g., Level 2 (L2_cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory1310. The local memory1320of each of the cores1302and the shared memory1310may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory1214,1216ofFIG. 12). Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core1302may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core1302includes control unit circuitry1314, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU)1316, a plurality of registers1318, the L1 cache1320, and an example bus1322. Other structures may be present. For example, each core1302may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry1314includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core1302. The AL circuitry1316includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core1302. The AL circuitry1316of some examples performs integer based operations. In other examples, the AL circuitry1316also performs floating point operations. In yet other examples, the AL circuitry1316may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry1316may be referred to as an Arithmetic Logic Unit (ALU). The registers1318are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry1316of the corresponding core1302. For example, the registers1318may include vector register(s), SIMD register(s), general purpose register(s), flag register(s), segment register(s), machine specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers1318may be arranged in a bank as shown inFIG. 13. Alternatively, the registers1318may be organized in any other arrangement, format, or structure including distributed throughout the core1302to shorten access time. The bus1322may implement at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus

FIG. 14is a block diagram of another example implementation of the processor circuitry1212ofFIG. 12. In this example, the processor circuitry1212is implemented by FPGA circuitry1400. The FPGA circuitry1400can be used, for example, to perform operations that could otherwise be performed by the example microprocessor1300ofFIG. 13executing corresponding machine readable instructions. However, once configured, the FPGA circuitry1400instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

In the example ofFIG. 14, the FPGA circuitry1400is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry1400ofFIG. 14, includes example input/output (I/O) circuitry1402to obtain and/or output data to/from example configuration circuitry1404and/or external hardware (e.g., external hardware circuitry)1406. For example, the configuration circuitry1404may implement interface circuitry that may obtain machine readable instructions to configure the FPGA circuitry1400, or portion(s) thereof. In some such examples, the configuration circuitry1404may obtain the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the instructions), etc. In some examples, the external hardware1406may implement the microprocessor1300ofFIG. 13. The FPGA circuitry1400also includes an array of example logic gate circuitry1408, a plurality of example configurable interconnections1410, and example storage circuitry1412. The logic gate circuitry1408and interconnections1410are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions ofFIGS. 7-10and/or other desired operations. The logic gate circuitryl408shown inFIG. 14is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry1408to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry1408may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

The storage circuitry1412of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry1412may be implemented by registers or the like. In the illustrated example, the storage circuitry1412is distributed amongst the logic gate circuitry1408to facilitate access and increase execution speed.

The example FPGA circuitry1400ofFIG. 14also includes example Dedicated Operations Circuitry1414. In this example, the Dedicated Operations Circuitry1414includes special purpose circuitry1416that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry1416include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry1400may also include example general purpose programmable circuitry1418such as an example CPU1420and/or an example DSP1422. Other general purpose programmable circuitry1418may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

AlthoughFIGS. 13 and 14illustrate two example implementations of the processor circuitry1212ofFIG. 12, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU1420ofFIG. 14. Therefore, the processor circuitry1212ofFIG. 12may additionally be implemented by combining the example microprocessor1300ofFIG. 13and the example FPGA circuitry1400ofFIG. 14. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts ofFIGS. 7-10may be executed by one or more of the cores1302ofFIG. 13and a second portion of the machine readable instructions represented by the flowchart ofFIG. 7may be executed by the FPGA circuitry1400ofFIG. 14.

In some examples, the processor circuitry1212ofFIG. 12may be in one or more packages. For example, the processor circuitry1300ofFIG. 13and/or the FPGA circuitry1400ofFIG. 14may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry1212ofFIG. 12, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

A block diagram illustrating an example software distribution platform1505to distribute software such as the example machine readable instructions1232ofFIG. 12to hardware devices owned and/or operated by third parties is illustrated inFIG. 15. The example software distribution platform1505may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other computing devices. The third parties may be customers of the entity owning and/or operating the software distribution platform1505. For example, the entity that owns and/or operates the software distribution platform1505may be a developer, a seller, and/or a licensor of software such as the example machine readable instructions1232ofFIG. 12. The third parties may be consumers, users, retailers, OEMs, etc., who purchase and/or license the software for use and/or re-sale and/or sub-licensing. In the illustrated example, the software distribution platform1505includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions1232, which may correspond to the example machine readable instructions700ofFIGS. 7, 8, 9, 10, and 11, as described above. The one or more servers of the example software distribution platform1505are in communication with a network1510, which may correspond to any one or more of the Internet and/or any of the example networks107described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and/or license of the software may be handled by the one or more servers of the software distribution platform and/or by a third party payment entity. The servers enable purchasers and/or licensors to download the machine readable instructions1232from the software distribution platform1505. For example, the software, which may correspond to the example machine readable instructions700ofFIG. 7, may be downloaded to the example processor platform1200, which is to execute the machine readable instructions1232to implement the SIC 1XX. In some example, one or more servers of the software distribution platform1505periodically offer, transmit, and/or force updates to the software (e.g., the example machine readable instructions1232ofFIG. 12) to ensure improvements, patches, updates, etc., are distributed and applied to the software at the end user devices.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that facilitate firmware update and/or configuration of a platform according to user needs without the need for a firmware and/or BIOS update from an OEM. The disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by allowing for dynamic updates to hardware configurations based on end-user need. These updates can be made without modifying the BIOS of the user device. Additionally, the updates are performed via a trusted execution method so as not to introduce security risk to the user device. The disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device.

Example apparatus, systems, and methods for initializing a processor are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes At least one non-transitory computer readable storage medium comprising instructions that, when executed, cause one or more processors to at least based on a soft strap status indicator stored in a serial peripheral interface (SPI) memory, extract a silicon initialization code profile from the SPI memory, and initialize the processor based on the silicon initialization code extension profile.

Example 2 includes the at least one non-transitory computer readable storage medium of example1, wherein the instructions, when executed, cause the one or more processors to modify the silicon initialization code extension profile during runtime based on an applet retrieved from a remote location.

Example 3 includes the at least one non-transitory computer readable storage medium of example 1, wherein the instructions, when executed, cause the one or more processors to generate a flash image based on the applet.

Example 4 includes the at least one non-transitory computer readable storage medium of example 3, wherein the instructions, when executed, cause the one or more processors to flash the flash image into the SPI memory.

Example 5 includes the at least one non-transitory computer readable storage medium of example 2, wherein initialization of the processor based on the silicon initialization code extension profile is enabled by the applet.

Example 6 includes the at least one non-transitory computer readable storage medium of example1, wherein the silicon initialization code extension profile includes custom hardware settings.

Example 7 includes the at least one non-transitory computer readable storage medium of example 1, wherein the silicon initialization code extension profile is associated with a performance setting for the processor.

Example 8 includes the at least one non-transitory computer readable storage medium of example 1, wherein the silicon initialization code extension profile includes a setting to indicate whether silicon initialization code extension profiles are enabled.

Example 9 includes an electronic device comprising interface circuitry to access SPI memory, extension profile handler instructions, and silicon initialization instructions, and processor circuitry including one or more of at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the processor circuitry to execute the extension profile handler instructions and the silicon initialization instructions to based on a soft strap status indicator stored in the SPI memory, extract a silicon initialization code extension profile from the SPI memory, and initialize the processor circuitry based on the silicon initialization code extension profile.

Example 10 includes the electronic device of example 9, wherein the silicon initialization code extension profile is modified during runtime based on an applet retrieved from a remote location.

Example 11 includes the electronic device of example 10, wherein the processor circuitry is to generate a flash image based on the applet.

Example 12 includes the electronic device of example 11, wherein the processor circuitry is to flash the flash image into the SPI memory.

Example 13 includes the electronic device of one of examples 10-12, wherein initialization of the processor circuitry based on the silicon initialization code extension profile is enabled by the applet.

Example 14 includes the electronic device of example 9, wherein the silicon initialization code extension profile includes custom hardware settings.

Example 15 includes the electronic device of example 9, wherein the silicon initialization code extension profile is associated with a performance setting for the processor circuitry.

Example 16 includes the electronic device of example 9, wherein the silicon initialization code extension profile includes a setting to indicate whether silicon initialization code extension profiles are enabled.

Example 17 includes a method comprising extracting a silicon initialization code extension profile from a SPI memory based on a soft strap status indicator stored in the SPI memory, and initializing a processor based on the silicon initialization code extension profile.

Example 18 includes the method of example 17, further including modifying the silicon initialization code during runtime based on an applet retrieved from a remote location.

Example 19 includes the method of example 18, further including generating a flash image based on the applet.

Example 20 includes the method of example 19, further including flashing the flash image into the SPI memory.

Example 21 includes the method of example 18, further including enabling initialization of the processor based on the silicon initialization code extension profile by the applet.

Example 22 includes the method of example 17, wherein the silicon initialization code extension profile includes custom hardware settings.

Example 23 includes the method of example 17, further including associating the silicon initialization code extension profile with a performance setting for the processor.

Example 24 includes the method of example 17, wherein the silicon initialization code extension profile includes a setting to indicate whether silicon initialization code extension profiles are enabled.

Example 25 includes an apparatus comprising means for extracting a silicon initialization code extension profile from a SPI memory based on a soft strap indicator stored in the SPI memory, and means for initializing a processor based on the silicon initialization code extension profile.

Example 26 includes the apparatus of example 25, further including means for modifying the silicon initialization code extension profile during runtime based on an applet retrieved from a remote location.

Example 27 includes the apparatus of example 26, further including means for generating a flash image based on the applet.

Example 28 includes the apparatus of example 27, further including means for flashing the flash image into the SPI memory.

Example 29 includes the apparatus of example 26, further including means for enabling initialization of the processor based on the silicon initialization code extension profile.

Example 30 includes the apparatus of example 25, wherein the silicon initialization code extension profile includes custom hardware settings.

Example 31 includes the apparatus of example 25, further including means for associating the silicon initialization code extension profile with a performance setting for the processor.

Example 32 includes the apparatus of example 25, wherein the silicon initialization code extension profile includes a setting to indicate whether silicon initialization code extension profiles are enabled.

It is noted that this patent claims priority from Indian Patent Application Number 202141028575 which was filed on Jun. 25, 2021, and is hereby incorporated by reference in its entirety.