Analog delay line implemented with a digital delay line technique

An analog delay line uses an analog-to-digital (A/D) converter which converts an analog signal into a plurality of digital signals. Digital delay lines, each including a series of digital delay elements, delay the respective digital signals. A digital-to-analog (D/A) converter converts the digital signals back into a delayed analog signal.

TECHNICAL FIELD
 The present invention relates to signal processing and, more particularly,
 to a circuit and methodology for delaying an analog signal.
 BACKGROUND ART
 There are many situations in which it is desirable to delay an analog
 electrical signal for a prespecified period of time. For example, delaying
 analog signals is common in processing audio signals, such as music.
 Conventional techniques of delaying analog signals, however, have a number
 of drawbacks.
 Some conventional analog delay lines involve large-lumped components, such
 as large capacitors, resistors, and inductors, that are difficult to
 manufacture on a monolithic semiconductor substrate. Moreover, some
 conventional analog delay lines may not be able to accurately achieve
 small delay periods, e.g. around 1 ns. A related difficulty with
 conventional analog delay lines is in obtaining fine resolution within the
 delay periods, for example, about 200 ps.
 DISCLOSURE OF THE INVENTION
 There exists a need for an analog delay line that can readily be
 implemented on a monolithic semiconductor substrate. There is also a need
 for an analog delay line which can accurately achieve small delay periods
 and fine resolution within the delay periods.
 These and other needs are met by the present invention, in which an
 analog-to-digital (A/D) converter converts an analog signal into a
 plurality of digital signals. The digital signals are delayed by digital
 delay lines and reconverted into a delayed analog signal. By converting
 the analog signal into a digital signal, the analog delay line can delay
 the analog signal by digital delay techniques, and the analog delay line
 can readily be implemented on a monolithic semiconductor substrate and
 achieve small delay periods with fine resolution.
 According to one aspect of the invention, an analog delay line comprises an
 analog-to-digital converter, having an analog signal input and a plurality
 of digital signal outputs. A plurality of digital delay lines are coupled
 respectively to the digital signal outputs, in which each digital delay
 line includes a plurality of digital delay elements coupled in series. A
 digital-to-analog converter, having an analog signal output, has a
 plurality of digital signal inputs coupled respectively to outputs of the
 digital delay lines. Preferably, the digital delay lines and digital delay
 elements include an input for receiving a calibration signal for adjusting
 the delay period, for example, to be about 140 ps.
 According to another aspect of the invention, a method of delaying an
 analog signal includes the step of converting the analog signal into a
 plurality of digital signals. The method includes repeatedly delaying by a
 common delay period the plurality of digital signals and converting the
 plurality of repeatedly delayed digital signals into a delay analog
 signal. The method may include the step of calibrating the common delay
 period to be about 140 ps.
 Additional objects, advantages, and novel features of the present invention
 will be set forth in part in the detailed description which follows, and
 in part will become apparent upon examination or may be learned by
 practice of the invention. The objects and advantages of the invention may
 be realized and obtained by means of the instrumentalities and
 combinations particularly pointed out in the appended claims.

BEST MODE FOR CARRYING OUT THE INVENTION
 A circuit and method for delaying an analog signal, are described. In the
 following description, for purposes of explanation, numerous specific
 details are set forth in order to provide a thorough understanding of the
 present invention. It will be apparent, however, that the present
 invention may be practiced without these specific details. In other
 instances, well-known structures and devices are shown in block diagram
 form in order to avoid unnecessarily obscuring the present invention.
 HIGH-SPEED DIGITAL DELAY LINE
 FIG. 1 is a block diagram of an exemplary high-speed, digital delay line
 100 with which the present invention can be implemented. The exemplary
 high-speed digital delay line 100 receives a serial bit stream comprising
 a plurality of bits spaced at regular intervals, termed "bit stream clock
 periods." Digital delay line 100 delays the serial bit stream so that an
 identical serial bit stream is output but with a phase delay of an
 integral number of bit stream clock periods.
 Specifically, digital delay line 100 comprises a plurality of digital delay
 elements 102-1 to 102-n, coupled in series. Each of the digital delay
 elements 102-1 to 102-n delays a digital signal for a specified amount of
 time. Digital delay line 100 may comprise an arbitrary number n of digital
 delay elements, depending upon any constraints inherent in the
 semiconductor implementation utilized or other practical considerations.
 For example, digital delay line 100 can comprise tens of thousands of
 digital delay elements. Since each of the digital delay elements 102-1 to
 102-n of digital delay line 100 is constructed during the same
 manufacturing process on the same semiconductor substrate, it is likely
 that the operating characteristics, and hence the delay period, of each
 digital delay element are nearly identical.
 When the common delay period equals the bit stream clock period, each
 individual bit of the serial bit stream input into digital delay line 100
 is delayed by a respective digital delay element. Thus, outputs of a
 plurality of digital delay elements may be tapped to simultaneously
 monitor a plurality of bits of the serial bit stream. Accordingly, digital
 delay line 100 comprises a plurality of taps 104-1 to 104-n coupled to the
 outputs of the respective digital delay elements 102-1 to 102-n for
 monitoring portions of the serial bit stream in parallel.
 Delay characteristics of any digital circuit will vary from chip to chip
 and over time because of unavoidable variations in manufacturing and
 operating conditions. Thus, there is a need to calibrate the delay period
 of each of the digital delay elements 102-1 to 102-n to match the bit
 stream clock period. According to one approach, both the delay period and
 the bit stream clock period are synchronized to a reliable, precise
 reference clock, such as a crystal oscillator.
 The delay period of each of the digital delay elements 102-1 to 102-n is
 preferably adjustable by a digital command code as a calibration signal.
 This calibration signal is produced with reference to a reliable, precise
 clock signal, preferably by an on-chip digital servo circuit (not shown)
 such as described in the commonly assigned U.S. Pat. No. 5,457,719, issued
 to Guo et al. on Oct. 10, 1995. Briefly, the on-chip digital servo circuit
 comprises an adjustable digital delay line of its own, which it monitors
 and continually adjusts with a calibration signal in a feedback loop. The
 calibration signal is shared with other systems on the chip.
 Referring to FIG. 1(b), each adjustable digital delay element 102 comprises
 two adjustable inverters 106-1 and 106-2, coupled in series, each
 receiving the aforementioned calibration signal. Thus, the delay period of
 each of the two adjustable inverters 106-1 and 106-2 is one-half of the
 bit stream clock period and is controlled by the calibration signal.
 Referring to FIG. 1(c), each adjustable inverter 106 in a preferred
 embodiment comprises a plurality of switchable inverters 108-1 to 108-m
 coupled in parallel. Each of the switchable inverters 108-1 to 108-m is
 switched on or off by one of bits 109-1 to 109-m of the calibration
 signal. Thus, two of the parameters that determine the propagation delay
 of an inverter, the P-channel size to N-channel size ratio and the driving
 power, may be determined for precise control over the delay period.
 Switchable inverters are described in further detail in the commonly
 assigned U.S. Pat. No. 5,220,216, issued to Woo on Jun. 15, 1993, and the
 commonly assigned U.S. Pat. No. 5,227,679, issued to Woo on Jul. 13, 1993.
 Accordingly, digital delay line 100 comprises a series of adjustable
 digital delay elements 102-1 to 102-n, each of which provides a uniform
 delay period synchronized to a reference clock period according to a
 calibration signal. Moreover, each adjustable inverter 106 can have a
 consistent delay period of as little as 70 ps. Thus, each adjustable
 digital delay element 102 can have a consistent delay period of as little
 of 140 ps. Therefore, digital delay line 100 is high-speed, capable of
 processing a serial bit stream at data rates up to about 7 GHz.
 Furthermore, digital delay line 100 provides parallel taps 104-1 to 104-n
 for simultaneously viewing in parallel any portion of a high-speed serial
 bit stream.
 ANALOG DELAY LINE
 Referring to FIG. 2, depicted is an analog delay line 200 according to one
 embodiment of the invention. Analog delay line 200 receives an analog
 signal through an "analog in" input, delays the analog signal, and outputs
 the delayed signal through an "analog out" output.
 The analog signal received through the "analog in" input is converted into
 digital form in bit-parallel format, that is `N` bits wide, by
 analog-to-digital (A/D) converter 202. The present invention may be
 implemented with a variety of A/D converters known in the art, but does
 not require any specific A/D converter. Preferably a fast A/D converter,
 such as a flash A/D converter, may be employed.
 The `N` bits of the digital signal are fed into `N` digital delay lines 100
 to 170. Although FIG. 2 depicts an analog delay line 200 with eight
 digital delay lines 100 to 170 (for an eight-bit output of A/D converter
 202), the present invention may be implemented with any number of digital
 delay lines for each bit of output from A/D converter 202. Generally, more
 bits of digital output from A/D converter 202 allow delay of analog
 signals with greater range and precision. Preferably, at least eight bits
 of digital output is desirable, even up to 32 and 64 bits. The number of
 digital delay lines matches the number of output bits from A/D converter
 202 in order to use pre-existing designs for A/D converter 202. For
 example, typical A/D converters output 8 bits, 9 bits, 10 bits, 12 bits,
 and 16 bits of data. Thus, the number of digital delay lines for such A/D
 converters would be 8, 9, 10, 12, and 16, respectively.
 The digital delay lines 100 to 170 are implemented with enough adjustable
 digital delay elements of a particular delays period so that the total
 delay period is the desired period for the analog delay line 200, taking
 into account the delays of the A/D converter 202 and D/A converter 204.
 For example, if the desired delay period is 30 ns in excess of the digital
 conversion periods, then a minimum of 215 (30 ns/140 ps=214.3 rounded up)
 adjustable delay elements 102 having a 140 ps delay period is required.
 The resolution of the total delay period would be delay period of a single
 digital delay element, i.e. 140 ps.
 The number of adjustable, delay elements 102 can be reduced by using
 adjustable delay elements 102 with a larger period. In fact, adjustable
 delay elements 102 having different periods may be used, for example
 twenty with a delay period of 1.4 ns and fifteen with a delay period of
 140 ps.
 The digital delay lines 100 to 170 delay each bit of the digital form of
 the analog signal for the desired period of time and pass the digital
 signals to digital-to-analog (D/A) converter 204. D/A converters are well
 known in the art, and a variety of D/A converters may each be employed to
 practice the invention. Preferably, D/A converters with short delay times
 are used.
 D/A converter 204 reconverts the digital signals into an analog signal,
 which is a delayed form of the input analog signal. The delayed analog
 signal is output from the D/A converter 204, and hence the analog delay
 line 200.
 Use of digital delay lines comprising a series of calibratable digital
 delay elements allows smaller delay periods to be accurately achieved.
 Furthermore, since each digital delay element can consistently have a
 delay period as short as 140 ps, the resolution of the analog delay period
 can be within 200 ps. Since the delay lines are all-digital, the delay
 lines can be fabricated on a monolithic semiconductor substrate.
 While this invention has been described in connection with what is
 presently considered to be the most practical and preferred embodiment, it
 is to be understood that the invention is not limited to the disclosed
 embodiments, but, on the contrary, is intended to cover various
 modifications and equivalent arrangements included within the spirit and
 scope of the appended claims.