Method and apparatus of automatically tuning output line rate and display controller provided with the same

A method and apparatus for automatically tuning the output line rate thereof and a display controller provided with the same. The display controller of the present invention provides a display controller having a line buffer, an input means, an output means, a status detector, and an auto-tune control means. The input means is employed to write line data into the line buffer at an input line rate, and the output means is employed to read the written line data from the line buffer at an output line rate. The status detector is coupled to the input means and the output means for generating a status signal indicating whether the input line rate and the output line rate are unbalanced. The auto-tune control means is used to adjust the output line rate in response to the status signal so as to balance the input line rate and the output line rate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a display system for processing source image data by means of scaling technology. More particularly, the present invention relates to a method and apparatus for automatically tuning output line rate of a display controller.

2. Description of Related Arts

Display systems are employed to process source image data into output image data to be displayed on a display screen thereof. The source image data is usually provided by a graphics controller such as a graphics card, video decoder, digital camera, etc., and the resolution of the source image data is predetermined. Therefore, the source image data needs to be resized or scaled into an appropriate resolution such that the display screen can correctly display the output image data. Accordingly, a device used to process the source image data into the associated output image data is so-called a “display controller.”

The display controller usually utilizes a line buffer with n blocks for read/write operations, which are subject to underrun or overrun due to undesirable read/write racing. Although firmware adjustment approach has been conventionally utilized to solve the buffer underrun or overrun issues, the user is required to realize the detailed operations of the image controller and manually adjust the associated parameters via firmware.

Thus, there is a need for a simple hardware-implemented display controller for tuning an image that has good image quality, fast tuning result, and a user-friendly interface.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a method and apparatus for automatically tuning the output line rate of a display controller such that no buffer underrun or overrun occurs.

It is another object of the present invention to provide a method and apparatus for automatically tuning the output line rate of a display controller such that the associated output device parameters can be correspondingly adjusted.

It is yet another object of the present of the present invention to provide a method and apparatus for automatically tuning the output line rate of a display controller without manual firmware intervention.

For fulfilling the aforementioned objects, the present invention provides a display controller having a line buffer with n blocks, an input means, an output means, a status detector, and an auto-tune control means. The input means is employed to write the line data into the line buffer at an input line rate, and the output means is employed to read the written line data from the line buffer at an output line rate. The status detector is coupled to the input means and the output means for generating a status signal indicating whether the input line rate and the output line rate are unbalanced. The auto-tune control means is used to adjust the output line rate in response to the status signal so as to balance the input line rate and the output line rate.

Moreover, the present invention provided an auto-tune method, comprising the following steps of:

(a) writing the line data into a line buffer at an input line rate;

(b) reading the written line data from the line buffer at an output line rate;

(c) detecting the input line rate and the output line rate;

(d) generating a status signal indicating whether the detected input line rate and the output line rate are unbalanced; and

(e) adjusting the output line rate by updating an output horizontal total number ohtot thereof responsive to the status signal until the input line rate and the output line rate are balanced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a block diagram of the display controller in accordance with one preferred embodiment of the present invention. As shown inFIG. 1, the display controller of the present invention comprises an input sampler and horizontal down-scaler102, a write line buffer control104, a line buffer106with n blocks, an output counter and up-scaler108, a read line buffer control110, an auto-tune control112, a line buffer timing control114, a line buffer status detector116, a phase-locked loop (PLL)118, and an oscillator120. Source image data, such as scan line image data, are sampled by the input sampler102and, if necessary, down-scaled by the horizontal down-scaler thereof. The processed image data is thereafter stored in the line buffer106line by line and then outputted to the output counter and up-scaler108in response to timing control from the line buffer timing control114. The line buffer106can be any type or combination of storage memory, which store the scan line image data. In this embodiment, the line buffer106is provided with n (n being an integer) blocks which can at the utmost store n lines of the image data. The up-scaler108receives the output from the line buffer106and generates the output image data to a display device (not shown in the drawings) according to an output pixel clock opclk from an output clock generator of the PLL118and the oscillator120. As is described in further detail hereinafter, the output clock opclk is predetermined and fixed based upon the display panel specification. The block108further comprises the output counter for generating output timing by following output pixel count.

For example, if the line buffer106is a SRAM device, the write line buffer control104will generate SRAM addresses, data, and write-enable (WE) signals. Upon reception of the source image data, the write line buffer control104in response to an enable signal from the input sampler102together with an input pixel clock ipclk generates the WE signal to facilitate the write operation in the line buffer106. Similarly, the read line buffer control110will generate SRAM addresses, data, and read-enable (RE) signals which may be provided with polarity opposite to that of the WE signals. The read line buffer control110in response to the output timing from the output counter and up-scaler108together with the output pixel clock opclk generates the RE signals for facilitating the read operation upon the line buffer106. The line buffer timing control114is the line buffer read/write arbiter to switch read/write timing in the line buffer106. In other words, the line buffer timing control114receives the WE signals from write line buffer control104and the RE signals from read line buffer control110to control the write and read operations of the line buffer106respectively.

Moreover, the line buffer status detector116is connected to the blocks102and108for detecting whether any buffer underrun or overrun for each image frame occurs by comparing the difference between an input line rate and an output line rate. The auto-tune control112in response to the detected result generated by the status detector116balances the read and write timing by means of auto-tune mechanism (to be described in the following), the auto-tune control112.

FIG. 2depicts an input/output frame diagram for explaining how a source image202is scaled to an output image204. Usually, the frame period includes a display enable (DE) period and a blank period. The DE period represents the actual time while the source image data is scaled and the blank period designates the horizontal/vertical retrace time called horizontal synchronization (HS) and vertical synchronization (VS). The HS and VS are utilized by CRT monitors for polarized scan line retracing, but both are treated as reference signals in the application to LCD monitors. During the blank period, there are invalid image pixels. Therefore, an entire horizontal line is divided into two parts: one part contains valid image pixels in the display (DE) period and the other part contains invalid image pixels in the blank period. Thus,
horizontal total pixel period=valid image pixel period+blank image pixel period, and
vertical total scan lines=valid image scan lines+blank image scan lines.
Furthermore, some acronyms inFIG. 2are described as below:ipclk: input pixel clock;ihtot: input horizontal total number;ihde: input horizontal display enable number (valid image pixel period in ihtot), which is the pixel number to be written to the line buffer106;iblank: input horizontal blank number (invalid image pixel in ihtot);ivde: input vertical display enable number (valid pixel scan lines);ivs: input vertical synchronization scan lines;opclk: output pixel clock to be generated by the oscillator-based PLL118;ohtot: output horizontal total number;ohde: output horizontal display enable number (valid image pixel in ohtot), which is the pixel number to be scaled up after reading pixel from the line buffer106;oblank: output horizontal blank number (invalid image pixel in ohtot);ovde: output vertical display enable number; andovs: output vertical synchronization scan lines.

The equation (1) that states the relationship of the input pixels:
ihtot=ihde+iblank(1)

The equation (2) that states the relationship of the output pixels:
ohtot=ohde+oblank(2)

Therefore, the display controller of the present invention receives the source image data according to the equation (3) and writes it into the line buffer106. After waiting for a certain period, the display controller generates the output image data for the display device by means of reading and scaling the image data stored in the line buffer106in response to the output pixel clock opclk according to the equation (4).

Referring toFIG. 3, a diagram showing the line buffer106ofFIG. 1provided with n blocks (preferably, n=2˜5) to be connected in the form of a ring in accordance with the present invention is schematically illustrated. By selecting a proper number of the blocks, the line buffer106configured with the ring buffer can eliminate the impact of write/read racing while maintaining the whole circuit workable. However, although the ring buffer inFIG. 3can provide buffer function to balance the write speed and read speed, the input and output line rates should be adjusted to reach a balanced condition, which will be described in details as follows.

The equation (5) that defines the input line rate:
Input line rate=ipclk×ihtot(5)

The equation (6) that defines the output line rate
Output line rate=opclk×ohtot(6)

FIG. 4is a timing diagram of the input write and output read sequences used for explanation. Input timing is shown: T1=ipclk×ihde is the time period for writing valid pixels, T2=ipclk×iblank is the blank time period, and T1+T2=ipclk×ihtot is the total period of an input scan line. The display controller sequentially writes each input pixel line during each T1period into the line buffer106by the sequence of the blocks0,1,2,3, . . . , n−2, n−1, in the line buffer and then back to the blocks0,1,2,3, . . . , n−2, n−1, in the line buffer and again and again as depicted inFIG. 3until the last input valid scan line. Output timing is shown: T5is the wait time during the write operation before the read operation starts. T3=opclk×ohde is the time period for reading valid pixels, T4=opclk×oblank is the blank time period, and T3+T4=opclk×ohtot is the total period of an output scan line. The display controller reads each pixel line during each T3period from the line buffer106by the sequence of the blocks0,1,2,3, . . . , n−2, n−1, in the line buffer and then back to blocks0,1,2,3, . . . n−2, n−1 in the line buffer over and over again until the last output scan line. However, the following input scan line must be written into the next adjacent block for the write operation, but read operation may not jump to the next adjacent block after reading the output scan line from the preceding block. The following read operation may stay on the same block or not follow consecutively but jumping several blocks based upon the vertical scaling ratio.

Ideally, no buffer overrun or underrun will occur during read/write operations as long as the input line rate and the output line rate reach a balanced condition. However, underrun will occur if the output line rate is too fast, and overrun will occur if the output line rate is too slow. According to the present invention, the output line rate is automatically tuned by means of updating the number ohtot by the auto-tune control112. Using iteration for several frames until no buffer overrun or underrun condition exists. Though the frequency of the output clock opclk can be changed to tune the output line rate, the output clock opclk of the present invention is predetermined and fixed upon display panel specification. However, for easy and precision, adjustment of the ohtot value is a better choice than opclk due to less parameter involved and a more precise tuning is achieved.

Referring toFIG. 6, a block diagram of the line buffer status detector116ofFIG. 1in accordance with the present invention is schematically illustrated. InFIG. 6, the line buffer status detector116comprises a write line counter602, a write pixel counter and blank checker604, a read line counter606, a read pixel counter and blank checker608, a line difference counter610, a pixel difference counter612, and a judgment circuit614. The write line counter602generates a write line count for the line difference counter610in response to the write pixel count and write blank data provided by the write pixel counter and blank checker604. The read pixel counter and blank checker608receives h-blank indicator and generates read pixel count and read blank data for the read line counter606. The read line counter606receives a vertical scaling factor and jump_to_next_line indicator, which decides whether the read operation stays in the same line or jump to the next line, wherein the next line does not necessarily mean the next consecutive line and can be the next2line. In addition, the read line counter606also generates a read line count to the line difference counter610in response to the read pixel count and read blank data provided by the read pixel counter and blank checker608. The line difference counter610receives the write line count and the read line count from the write line counter602and the read line counter606, respectively, so as to measure the line difference between the corresponding write/read operations. Alternatively, the pixel difference counter612receives the write pixel count and read pixel count from the write pixel counter604and the read pixel counter608, respectively, so as to measure the pixel difference between the corresponding write/read operations. The judgment circuit614is utilized to derive the status of overrun or underrun indicators in response to the line difference and the pixel difference provided by the line difference counter610and the pixel difference counter612respectively.

Referring toFIG. 7, a block diagram of the auto-tune control112inFIG. 1in accordance with the present invention is schematically illustrated. InFIG. 7, the auto-tune control112comprises a coarse tune control702, a fine tune control704, a fractional tune control706, and a selector708. According to the present invention, the initial value of ohtot can be either the output horizontal display enable number ohde or a user-programmed number ohtotuserin response to whether an coarse-tune bit is set or not. If the coarse-tune bit is found to be set, ohde is sent to the coarse tune control702as the initial value of ohtot; however, if the coarse-tune bit is found to be unset, ohtotuseris sent to the fine tune control704as the initial value of ohtot. Note that coarse tune control702is not involved when ohtotuseris chosen. According to the present invention, the coarse tune control702, fine tune control704and fractional tune control706are employed to perform coarse tune, fine tune and fractional tune, respectively. The terms “coarse tune,” “fine tune” and “fractional tune” are defined as follows:(1) Coarse tune: ohtot is changed by an integer greater than one;(2) Fine tune: ohtot is exactly changed by one; and(3) Fractional tune: ohtot is changed by a fraction smaller than one.
The three-phased auto-tune method is hardware-based and therefore does not require any software or firmware for operation. According to the present invention, the line buffer status detector116monitors the read and write operations made to the line buffer106, and thus generates overrun/underrun indication at the end of each frame. The overrun and underrun indicators are provided for the auto-tune control112so as to update ohtot according to the three-phased auto-tune method and thus tune the output line rate, accordingly. The updated ohtot is generated by one of the coarse tune control702, the fine tune control704, and the fractional tune control706. The selector708is used to select the updated ohtot according to a tune-type signal, which designates one output of the coarse tune control702, the fine tune control704and the fractional tune control706as the updated ohtot. The updated ohtot is thereafter processed by the output counter and up-scaler108which generates the corresponding output timing for the next frame. The ohtot-updated cycle continues until no underrun or overrun occurs.

The detailed operations of the coarse tune control702, fine tune control704and fractional tune control706will be described inFIGS. 8,9, and10, respectively.FIG. 8is a flow chart diagram of the coarse tune method according to the present invention. As shown inFIG. 8, the coarse-tune bit is set in Step802when the auto-tune method is required and thus enabled, and then an initial jump step p (p>1) is chosen in Step804. The initial jump step p can be selected within the range of 2˜512; preferably, p=512 or 256 in the application of XGA display mode. Next, the initial value of ohtot is set to ohde in Step806. By proceeding to Step808, the coarse-tune bit is checked again as to whether the display system is reset and/or input frame mode (e.g., input resolution, polarity, . . . , etc.) is changed again even though the auto-tune method has not been finalized yet; if yes, the flow goes back to Step804, and, if no, the flow goes to Step810to check the statuses of the overrun and underrun indicators generated by the line buffer status detector116. Note that the statuses of the underrun and overrun indicators are checked at the end of each image frame. If no buffer underrun or overrun occurs, that is, underrun=0 and overrun=0, the flow goes back to Step808by iterating Steps808and810as well. If p≠1 and buffer underrun or overrun occurs, that is, overrun=1 or underrun=1, the flow goes to Step812to check either overrun=1 or underrun=1; if p=1 and buffer underrun or overrun occurs, that is, overrun=1 or underrun=1, the flow goes to Step906to be processed upon the fine tune method. If underrun=1 is found in Step812which means the output line rate is too fast, the jump step p is updated by p(old)/2 and ohtot is updated by [ohtot(old)+p(old)/2] as depicted in Step813; if overrun=1 is found in Step812which means the output line rate is too slow, the jump step p is updated byp(old)/2 and ohtot is updated by [ohtot(old)−p(old)/2] as depicted in Step814. The updated jump step p and the updated ohtot obtained in Steps813and814are thereafter applied to the next frame and the flow goes back to Step808as shown inFIG. 8.

FIG. 9is a flow chart diagram of the fine tune method according to the present invention. InFIG. 9, the fine tune method retains the option of being independent of the coarse tune method if the coarse-tune bit is not set so the fine tune method can be initialized on its own by choosing ohtotuserto be the initial value of ohtot. As shown inFIG. 9, the hardware will pick a user-programmed ohtotuseras the initial value of ohtot in Step904if the coarse-tune bit is found unset in Step902. Next, in Step906, the coarse-tune bit is checked again as to whether the display system is reset and/or input frame mode (e.g., input resolution, polarity, . . . , etc.) is changed; if yes, the flow goes back to Step804. According to the present invention, when the input frame mode (e.g. input resolution, polarity, . . . , etc.) is found to be changed, it means that the previous condition has been reset and the auto-tune mechanism is reset by setting the coarse-tune bit for the new input frame mode. If the coarse-tune bit is checked in Step906and not set at all, the flow proceeds to Step908to compare the statuses of the current frame and the previous frame.

If the current status of overrun=1 and underrun=0 and the previous status of overrun=0 and underrun=1, it means that the fractional tune is required and thus the flow should proceed to Step1004. For the same reason, if the current status of overrun=0 and underrun=1 and the previous status of overrun=1 and underrun=0, it also means that the fractional tune is required and thus the flow should proceed to Step1004. Otherwise, the fine tune flow goes to Step910to check the current status of either overrun=1 or underrun=1. If underrun=1 is found in Step910which means the output line rate is too fast, the value of ohtot is updated by [ohtot(old)+1] as depicted in Step911. If overrun=1 is found in Step910which means the output line rate is too slow, ohtot is updated by [ohtot(old)−1] as depicted in Step913. The updated ohtot obtained in Steps911and913is thereafter applied to the next frame and the fine tune flow goes back to Step906as shown. Note that if overrun=0 and underrun=0 are found in Step910which means no overrun and underrun occurs, the flow then goes back to Step906for iterating Steps906,908,910as depicted inFIG. 9.

Referring toFIG. 10, a flow chart diagram of the fractional tune method according to the present invention is schematically illustrated. In Step1004, the fraction number m is set by the user program and a count number cnt is reset to 0. The operation then proceeds to Step1006to check the coarse-tune bit again as to whether the display system has been reset and/or the input frame mode (e.g., input resolution, polarity, . . . , etc.) has been changed; if yes, the flow goes back to Step804as depicted inFIG. 8. According to the present invention, when the input frame mode (e.g. input resolution, polarity, . . . etc) is found to be changed, it means that the previous condition has been reset and the auto-tune mechanism is required by setting the coarse-tune bit for the new input frame mode. If the coarse-tune bit is checked in Step1006and not set at all, the flow proceeds to Step1008to determine if the count number cnt is equal to the fraction number m. If cnt=m is found in Step1008and thus no solution for the fractional tune in the range from cnt=0 to cnt=m can be concluded, the fractional tune flow proceeds to Step906to issue a failure flag to inform the user to try another value of m. If cnt is not equal to m, the fractional tune flow proceeds to Step1010to check the statuses of buffer underrun and overrun indicators.

If underrun=1 is found in Step1010which means the output line rate is too fast, the count number cnt is updated by [cnt(old)+1] as depicted in Step1013. Therefore, among m scan lines, there are cnt lines with output horizontal total number (ohtot+1) and (m−cnt) scan lines with the output horizontal total number ohtot. This arrangement can slow down the output line rate. To the contrary, if overrun=1 is found in Step1010which means the output line rate is too slow, the count number cnt is updated by [cnt(old)+1] as depicted in Step1011. Accordingly, among m scan lines, there are cnt lines with output horizontal total number (ohtot−1) and (m−cnt) scan lines with output horizontal total number ohtot. After Steps1011and1013are completed, the flow goes back to Step1006. In addition, if underrun=0 and overrun=0 are found in Step1010, the flow proceeds to Step1012to keep the count number cnt and then goes back to Step1006.

Furthermore, according to the auto-tune method of the present invention, the output horizontal total number ohtot can not be an integer but containing a fraction. For example, the fraction number m=8 and the count number cnt=1 are obtained eventually; therefore, ohtot=(1000+1/8) or (999+7/8). As shown inFIG. 5, by taking ohtot=(1000+1/8) as an example, it is implemented by means of every 8 scan lines provided with seven scan lines of ohtot=1000 and one scan line of ohtot=1001.