Multi-level cell (MLC) techniques and circuits for cross-point memory

Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a third read voltage with a greater magnitude is applied across the memory cell. In one example, the thresholding of the memory cell triggers the application of a write current to write back the state of the bit due to read disturb from the read.

FIELD

The descriptions are generally related to memory, and more particularly, to techniques for multi-level cell (MLC) nonvolatile memory, such as cross-point memory.

BACKGROUND

Memory resources have innumerable applications in electronic devices and other computing environments. There is demand for memory technologies that can scale smaller than traditional memory devices. However, continued drive to smaller and more energy efficient devices has resulted in scaling issues with traditional memory devices. Three-dimensional memory devices emerged as a solution to the scaling limitations of traditional memory devices.

Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.

DETAILED DESCRIPTION

Techniques for accessing multi-level cell (MLC) crosspoint memory are described herein.

Conventional crosspoint memories include memory cells that are programmable to one of two states to store one bit. In contrast to conventional crosspoint memory, an MLC crosspoint memory includes cells that are programmable to more than two states, and therefore can store multiple bits. For example, an MLC crosspoint memory can include a storage material that can be in one of four states (to store 2 bits) or more.

Prior attempts at developing a MLC crosspoint memory have been generally unsuccessful due to the challenges faced. Techniques for writing to and reading from MLC crosspoint memory have resulted in high error rates. One prior technique for attempting to read a MLC crosspoint cell involves applying a single sub-threshold voltage across the cell. A sub-threshold voltage is a voltage that is lower than any threshold voltage of the cell. Thus, the read operation does not cause the storage material of the cell to experience a threshold event and is therefore unlikely to cause read disturb. In one such scheme, after applying a sub-threshold voltage, the resistance of the cell can then be determined by detecting the current flowing through the cell. However, the difference between the expected current flowing through the cell in response to the sub-threshold voltage for different resistive states is very small. Therefore, correctly determining the resistive state is difficult and the error rate is high.

In contrast, reading an MLC crosspoint cell with multiple voltage pulses that are above threshold voltages of the cell enable faster and more accurate results. For example, a 2-bit memory cell with four states can be read by applying three read voltages. After application of each read voltage, it is determined whether the cell thresholds. If the cell thresholds after a read voltage, the value stored by the cell can be determined and the operation can end. If the cell does not threshold after a read voltage, then the next read voltage with a higher magnitude is applied to the cell. Thus, one of multiple read voltage are applied depending on the output of the cell in response to the previous read voltage. After a read voltage causes a cell to threshold, a program current can be applied to bring the cell back to the previous state. Thus, each read operation for a two-bit memory cell includes up to 3 consecutive sub-reads, done at 3 different read biases. Each sub-read may also enable a write-back operation to ensure read-disturb immunity. Accordingly, the read technique enables crosspoint memory to be used for higher density applications (e.g., 2x higher density for a 2-bit cell) without high read error rates. A similar or same technique can be applied for memory cells storing more than two bits (e.g., 3 bits, 4 bits, or more).

FIG. 1Ais circuit diagram of an example of a two-terminal crosspoint memory cell. The crosspoint memory cell is one of many memory cells in a crosspoint memory device. The crosspoint memory cell106is coupled with access circuitry via a bitline102and a wordline104. The crosspoint memory cell106includes a material to store one or more bits. The memory element of the crosspoint memory cell106can include any memory element with a tunable threshold voltage. In one example, the cell106can be in one of multiple (e.g., 2, 4 or more) resistive states. In one such example, each different resistive state is associated with a different threshold voltage (VT). A threshold voltage is a voltage at which the cell106undergoes a change (e.g., a physical change) that causes the cell to be in a higher conductive state. In one example, a memory cell can be said to “threshold” or undergo a “threshold event.” In one example, when a memory cell thresholds (e.g., in response to an applied voltage with a magnitude greater than the threshold voltage at the current state), the memory cell undergoes a physical change that causes the memory cell to exhibit a certain electrical characteristics, such as high conductivity. Once a cell thresholds, a program current of a particular amplitude, polarity, and duration can be applied to the cell to cause the cell to be in the desired resistive state. The value stored by the crosspoint memory cell106can therefore be determined by detecting the resistive state of the cell, which can be determined by detecting the current that flows through the cell in response to an applied voltage.

The memory cell106is coupled with circuitry108to enable access to and operation of the memory cell106. The circuitry includes electronic components that are electrically coupled to perform one or more of: supplying voltages to the memory cell, sensing electrical responses of the memory cell, performing analog or logic operations on received or stored information, outputting information, and storing information. In one example, the access circuitry108includes circuitry to select memory cells, write to memory cells, and read from memory cells.

FIG. 1Billustrates an example of threshold voltage distributions for the memory cell106ofFIG. 1A.FIG. 1Bshows in an example in which the memory cell can be in one of four states or programming levels (e.g., L1, L2, L3, and L4). Although different states are referred to herein as L1, L2, L3, and L4, other labels may be used to identify different states or programming levels. Each of the states) has a different threshold voltage distribution. The read voltages are selected to be between adjacent threshold voltage distributions. For example, READ_BIAS_1is between the threshold voltage distributions for states L1and L2. READ_BIAS_2is between the threshold voltage distributions for states L2and L3. READ_BIAS_3is between the threshold voltage distributions for states L3and L4. By applying the voltage READ_BIAS_1across the memory cell, cells in state L1would threshold, but cells in states L2, L3, and L4would not threshold. Applying the voltage READ_BIAS_2would cause cells in states L1and L2to threshold, but not cells in states L3and L4. Applying the voltage READ_BIAS_3would cause cells in states L1, L2, and L3to threshold, but not cause cells in state L4to threshold. Thus, the second read voltage has a larger magnitude than the first read voltage, and the third read voltage has a larger magnitude than the second read voltage. In one example, one or more of the read voltages have magnitudes that cause the memory cell to threshold. In one such example, all the read voltages have magnitudes sufficient to cause the memory cell to threshold. In this example, all the read voltages have magnitudes less than the write bias magnitude.

Consider an example in which the memory cell106includes a phase change storage material. In one such example, the distributions L1-L4may represent varying levels of crystallinity or amorphousness. For example, the storage material may include a phase change material to be in one of four states having varying degrees of amorphousness or crystallinity. For example, the distribution L1may represent the VT distribution for a storage element that is fully crystalline. Distributions L2, L3and L4may represent increasing amorphous fractions inside the storage element, achieved by applying different programming currents.

In one example, the memory cell106includes both a phase change storage material and a non-phase change selector material. In one such example, the selector material is capable of being in two or more states. For example, states L1and L2can represent two states of the selector material and states L3and L4can represent two state of the phase change storage material. In another example with a selector device, the selector device does not store data and states L1-L4represent different states of the phase change material. In an example in which the memory cell106does not include a phase change storage material, the distributions for L1-L4may represent different resistive or conductive states. Note that the example ofFIG. 1Billustrates four states, however, the techniques described herein can be extended to more than four states (e.g., eight states, etc.).

FIG. 1Cis a graph illustrating an example of I-V curves (current-voltage characteristic curves) for a crosspoint memory cell in different states. Specifically, the graph ofFIG. 1Cshows I-V curves A, B, C, and D for the memory cell106in states L1, L2, L3, and L4, respectively. Given the programming I-VT characteristic of each cell, MLC capability can be achieved by programming the cell into four different states. In this example, each I-V curve is approximately linear up until the threshold voltage. Once the threshold voltage is reached, there is a “snapback” or threshold event in which the cell enters a higher conductive state. To program a memory cell, typically a voltage (shown as Write_Bias inFIG. 1C) that is higher than the threshold voltages in all states is applied to ensure the cell thresholds. Once the cell thresholds in response to the application of Write_Bias, a program current is applied to program the cell to the desired state.

To read the cell, unlike prior MLC read techniques involving sub-threshold voltages (e.g., voltages at or below Sub_Vt_Bias), one or more read voltages (READ_BIAS_1, READ_BIAS_2, and READ_BIAS_3) with magnitudes greater than threshold voltages are applied across the cell.

FIG. 2illustrates an example of a technique for reading an MLC crosspoint memory cell.

The technique begins with a read at a first read voltage, READ_BIAS_1. In this example, if the cell thresholds (“1”) during the first read at READ_BIAS_1, the read-operation ends because the status of the cell is determined to be L1. In some examples, the threshold event potentially causes read-disturb. Therefore, a write-back repair current (I-1) is applied with the first read operation if the cell thresholds (e.g., “1” is detected). Note that the program current I-1is indicated as optional. In some crosspoint memory architectures, the application of READ_BIAS_1may not disturb the value stored in the memory cell, and therefore not require a write back current. In one such example, the voltage READ_BIAS_1can be selected to be below the threshold voltages of the memory element (for example, if the states A and B are states of an amorphous selector element, then READ_BIAS_1may not be disruptive).

If during the first read at READ_BIAS_1, no threshold is detected (“0”), then state “L1” can be excluded and a second read at a higher bias READ_BIAS_2is applied. In this example, if a threshold event is detected at READ_BIAS_2(“1”), the state of the cell is determined to be L2. In one example, the threshold event at READ_BIAS_2is likely to cause read-disturb, potentially moving the VT of the cell into the L1, L3, or L4distributions. Thus, a program current I-2is also applied with the second read operation if the cell thresholds to bring back the cell in state L2. However, the current I-2is also indicated to be optional because some crosspoint memory architectures may not experience disturbance from the application of READ_BIAS_2. If no threshold event is detected during the second read at READ_BIAS_2read (“0”) the bit will be in state L3or L4. To determine which state of the two (L3or L4) the memory cell is in, a final third read at READ_BIAS_3is applied. If during this third read at READ_BIAS_3a threshold event is detected (“1”) the read operation ends, and the cell is determined to be in state L3. Also, the I-3current may or may not be applied to avoid any residual read-disturb problem, as previously described. If during this third read at READ_BIAS_3, no threshold is detected (“0”), the read ends and the cell is determined to be in state L4. In this last case, there is no need to apply any repair current since no threshold event occurred.

FIG. 3illustrates an example of a circuit topology with a MLC crosspoint memory cell. The circuit300includes a single memory cell302. The memory cell302is an MLC crosspoint memory cell that can be the same as, or similar to, the cell106described above with respect toFIG. 1. In the illustrated example, the memory cell302has one terminal that is coupled with the supply voltage VPP and another terminal that is coupled with the supply voltage VNN. In this example, VPP is on the bitline side and VNN is on the wordline side, so the supply voltages could alternatively be referred to as bitline supply voltage and the wordline supply voltage, respectively. In one example, VPP is the maximum positive supply voltage and VNN is the maximum negative supply voltage. However, the supply voltages may be different than illustrated inFIG. 3(e.g., the bitline supply voltage may be negative and the wordline supply voltage may be positive, or both supply voltages can have the same polarity).

The circuit300also includes selection transistors (which can also be referred to as decoding transistors) between the memory cells and the supply voltages. For example, the circuit includes a global bit line selection transistor (GBL_SEL), a local bit line selection (LBL_SEL) transistor, a local word line selection transistor (LWL_SEL), and a global word line selection transistor (GWL_SEL). Turning on the selection transistors (e.g., by applying a pre-determined voltage to the gate of the transistors) selects the cell for reading or writing. In the illustrated example, the transistors GBL_SEL and LBL_SEL are connected to VPP and transistors LWL_SEL and GWL_SEL are connected to VNN. Thus, in the illustrated example, GBL_SEL and LBL_SEL are shown as PMOS transistors and LWL_SEL and GWL_SEL are shown as NMOS transistors.

Typical crosspoint memory circuit architectures include circuitry to apply a single read voltage across the cell and a single current mirror for write back after read operations. In contrast to conventional architectures, multiple read circuits enable the cell to be read at multiple read voltages to enable accurate reading of MLC crosspoint memory cells.

The circuit300includes transistors306and308-1-308-3to enable application of multiple read voltages across the memory cell302. In one example, the transistors306and308-1-308-3are cascode transistors. For example, the transistor206on the bitline side can include a cascode transistor that passes a bias applied to the gate to its source. In this way, the voltage (e.g., BL_Read_Bias) applied to the gate of the transistor306can be applied to the node307at the source of transistor307. Similarly, the transistors308-1-308-3on the wordline side can include cascode transistors to pass the voltage applied to the gate to the bulk (given that the transistors308-1-308-3in the illustrated example are PMOS transistors). In this way, the voltage applied to the gate of the transistors308-1-308-3(e.g., WL_Read_Bias_1, WL_Read_Bias_2, or WL_Read_Bias_3) can be applied to the node309at the drain of transistors308-1-308-3. Regardless of the circuitry used, multiple different read voltages are to be applied across the memory cell in accordance with the techniques described herein.

For each of the different read voltages, one technique for generating the bias across the memory cell is to apply a portion of the read voltage on the bitline side and a portion of the read voltage is applied on the wordline side. For example, to cause a voltage difference of X across the memory cell302, X/2 can be applied on the bitline side and −X/2 can be applied on the wordline side. Alternative biasing schemes can also be used. In the example illustrated inFIG. 3, the three different voltage levels (e.g., READ_BIAS_1, READ_BIAS_2, or READ_BIAS_3) are applied across the memory cell by applying a positive voltage (BL_Read_Bias) on the bitline side and a negative voltage (e.g., one of WL_Read_Bias_1, WL_Read_Bias_2, or WL_Read_Bias_3) on the wordline side via the gate of the appropriate transistor on the wordline side (e.g.,308-1for READ_BIAS_1,308-2for READ_BIAS_2, and308-3for READ_BIAS_3). In the example illustrated inFIG. 3, the voltage generated on the bitline side can be the same for READ_BIAS_1, READ_BIAS_2, and READ_BIAS_3, and the voltage generated on the wordline side is varied depending on whether the cell is to be biased at READ_BIAS_1, READ_BIAS_2, or READ_BIAS_3. In the illustrated example, READ_BIAS_1is equal to BL_Read_Bias+|WL_Read_Bias_1|. READ_BIAS_2is equal to BL_Read_Bias+|WL_Read_Bias_2|. READ_BIAS_3is equal to BL_Read_Bias+|WL_Read_Bias_3|. Thus, the three different read biases are delivered using three different transistors (transistors308-1,308-2, and308-3) to deliver three different Word-Line biases. In this example, the bitline bias is kept constant in all the three read cases. Applying a voltage to the gate of one of the transistors involves bringing the gate to the desired voltage relative to another baseline level (e.g., ground or other baseline level). Applying a voltage can involve applying a pulse or pulses or otherwise bringing the node in the circuit to the desired voltage. A current pulse is typically a rapid and transient change (e.g., increase or decrease) in voltage or current. For example, a voltage pulse may be defined as a rapid change from a first voltage level to a second voltage level, followed by a rapid return to the first voltage level. Pulses can have a variety of shapes, such as rectangular, triangular, or other shapes.

The circuit300also includes current mirrors304-1,304-2, and304-3for generating program current after one or more read voltages are applied across the cell. In the illustrated example, each cascode leg of the circuit is connected to a specific current mirror. Specifically, the transistor308-1is coupled with the current mirror304-1, the transistor308-2is coupled with the current mirror304-2, and the transistor308-3is coupled with the current mirror304-3.

In one example, a current mirror will only turn on when the memory cell302thresholds in response to the application of the associated read voltage across the memory cell302. For example, once the specific read bias is applied (e.g., READ_BIAS_1and thus when WL_Read_Bias_1is applied to the gate of the transistor308-1), only if the memory cell302thresholds will there be enough bias across the current mirror304-1to effectively turn-on the current mirror304-1and then deliver the I-1current. Similarly, when applying READ_BIAS_2(and thus when applying WL_read_Bias_2to the gate of the transistor308-2), the current mirror304-2turns on only if the memory cell302thresholds in response to READ_BIAS_2. In the same way, the current mirror304-3turns on if the memory cell302thresholds in response to application of READ_BIAS_3across the memory cell (and thus when applying WL_Read_Bias_3to the gate of the transistor308-3). Therefore, after the memory cell thresholds, the current path is opened and the program current (e.g., one of I-1, I-2, or I-3) is applied to the cell to bring the cell back into the prior state. Accordingly, if a read voltage causes the value stored by the cell to change (due to thresholding of the cell), a program current is automatically generated to immediately restore the state of the memory cell.

Thus,FIG. 3illustrates one exemplary circuit in which the three sub-reads and subsequent writes are accomplished through three different cascode architectures in parallel. The circuit ofFIG. 3could be expanded to more than three cascode branches in parallel to support more than four states.

FIG. 4illustrates an example of programming current to be used during reads. The graph ofFIG. 4shows current versus time for reads at READ_BIAS_1, READ_BIAS_2, and READ_BIAS_3. The current I-1is generated by the current mirror304-1ofFIG. 3. The current I-2is generated by the current mirror304-2ofFIG. 3. The current I-3is generated by the current mirror304-3ofFIG. 3. In one example, the currents I-1, I-2, and I-3are currents that are generated by the respective current mirrors in response to the thresholding of a cell after application of a read voltage. Note that the current waveforms illustrated inFIG. 4are examples; other current magnitudes and current pulse shapes are possible.

Turning first to the example of the read at READ_BIAS_1, the first read voltage READ_BIAS_1is applied across the memory cell. After application of READ_BIAS_1, the cell may or may not threshold depending on the state of the cell. If the cell is in states L2, L3, or L4, then the cell does not threshold in response to the voltage READ_BIAS_1. If the cell does not threshold, the current mirror304-1does not turn on. If the cell is in state L1, the cell thresholds. The current mirror204-1is then turned on and the current I-1ramps up from zero to a first level to program the memory cell to the value L1. The current I-1is then ramped down to zero as the first read completes.

If the cell did not threshold in response to READ_BIAS_1, then a second read at READ_BIAS_2is performed. If the cell is in states L3or L4, then the cell does not threshold in response to the voltage READ_BIAS_2. If the cell does not threshold, the current mirror304-2does not turn on. If the cell is in state L2, the cell thresholds. The current mirror304-2is then turned on and the current I-2ramps up from zero. In the illustrated example, the memory cell is first programmed to state L1. After the cell is in state L1, the magnitude of the current is further increased to a second level to program the cell to state L2. The current I-2is then ramped down to zero as the second read completes.

If the cell did not threshold in response to READ_BIAS_2, then a third read at READ_BIAS_3is performed. If the cell is in state L4, then the cell does not threshold in response to the voltage READ_BIAS_3. If the cell does not threshold, the current mirror304-3does not turn on. If the cell is in state L3, the cell thresholds in response to READ_BIAS_3. The current mirror304-3is then turned on and the current I-3ramps up from zero. In the illustrated example, the memory cell is first programmed to L1. After the cell is in state L1, the magnitude of the current is further increased to a third level to program the cell to state L3. The current I-3is then ramped down to zero as the third read completes.

Consider an example in which the crosspoint memory cell includes a phase change storage element. If the cell is in state L1(e.g., the cell thresholds in response to READ_BIAS_1), the I-1programming current from the current mirror304-1provides current to crystallize back (set) the storage element, due to the read-disturb (e.g., a read disturb caused by the storage element transitioning to a partially amorphous state). If the memory cell is in state L2(e.g., the cell thresholds in response to READ_BIAS_2), the I-2programming current from the current mirror204-1provides the current to crystallize back (set) the storage element to state L1, and the current above the melting value to bring the cell back in state L2. If cell is in state L3(e.g., the cell thresholds in response to READ_BIAS_3), the I-3programming current from the current mirror304-3provides the current to crystallize back (set) the storage element to state L1, and the current above the melting value, (larger in magnitude than for state L2), to bring the cell back in state L3.

FIG. 5is a flow diagram of an example of a method of accessing a MLC crosspoint memory cell. The method500can be performed by hardware, firmware, or a combination of hardware and firmware.

The method500begins with application of a first read voltage across a crosspoint memory cell, at502. For example, referring toFIG. 3, the voltage READ_BIAS_1is applied across the memory cell302. The voltage READ_BIAS_1can be generated across the memory cell302by applying voltages to the gates of transistor306on the bitline side and308-1on the wordline side. The voltages can be generated by one or more voltage generation circuits coupled with the gates of the transistors306and308-1. After applying the first read voltage, the method involves detecting whether the memory cell thresholded in response to the first read voltage. Detection of whether the memory cell thresholds can involve, for example, detecting whether there is current flowing through the cell (e.g., detecting whether the current through the cell has a magnitude that is greater than a threshold). For example, referring toFIG. 3, the current flowing through the memory cell302in response to the first read voltage can be sensed with a sense amplifier or other sense circuit.

If the memory cell did threshold in response to the first read voltage,504YES branch, then the state of the memory cell can be determined to be L1without additional reads, at505. If the memory cell did not threshold in response to the first read voltage (504NO branch), then further reads are needed to determine the state of the memory cell. Therefore, if the memory cell did not threshold in response to the first read voltage, the method involves applying a second read voltage across the memory cell, at506. For example, referring toFIG. 3, the voltage READ_BIAS_2is applied across the memory cell302. The method then involves detecting whether the memory cell thresholded in response to the second read voltage. If the memory cell thresholded in response to the second read voltage, then the state of the memory cell can be determined to be L2, at509. If the memory cell did not threshold in response to the second read voltage (508NO branch), the method can then continue with the application of a third read voltage, at510. For memory cells with more than four states, the method can continue to apply additional read voltages (e.g., more than three read voltages) until the state of the memory cell can be determined. As mentioned above with respect toFIG. 2, optional write currents can be applied after one or more of the read voltages to correct any read disturb errors caused by the reads. Thus, each read operation consists of one or more consecutive sub-reads, done at different read biases. Each sub-read can also deliver a write-back current to ensure read-disturb immunity.

FIG. 6illustrates an example of a crosspoint memory cell that can be accessed using techniques described herein.

FIG. 6illustrates a memory cell600. The memory cell600includes one or more layers of material602to store data and aid in selection of the memory cell100. For example, the memory cell600can include a storage material602, a selector material, or both, between access lines604and606. In one example, the memory cell includes a layer of storage material and a separate layer of selector material. In one example, the selector is a device with a threshold voltage and the storage element is a device with a tunable threshold voltage. In one example, the memory cell600includes a self-selecting material that exhibits both memory and selection effects. A self-selecting material is a storage material that enables selection of a memory cell in an array without requiring a separate layer of material for selection of the cell. In one example, a self-selecting memory cell includes a single layer of material that acts as both a selector element to select the memory cell and a memory element to store a logic state. A material exhibits memory effects if the material can be put in one of multiple stable states (e.g., via a write operation), and subsequently read back (e.g., via a read operation).

The techniques described herein apply generally to crosspoint memory and are not dependent on or specific to a particular storage material. However, some non-limiting examples of storage material follow.

In some examples, the storage material is a phase change material. In other examples, the storage material can be in one or multiple stable states without a change in phase. In one example, the memory element, switching element, or both are amorphous semiconductor threshold switches (e.g., ovonic threshold switches) using an amorphous material such as an amorphous chalcogenide material or other amorphous material. An ovonic threshold switch remains in an amorphous state which distinguishes it from an ovonic memory, which generally changes between amorphous and crystalline states. In one example, an ovonic memory is used in series with an ovonic threshold switch. In such case, the ovonic threshold switch operates as the select device for the ovonic memory. Whether the memory material of the memory cell changes phase or not, in one example, the memory could be referred to as a resistance-based memory. In a resistance-based memory, the bit stored by a memory cell is based on the resistive state of the memory cell.

As mentioned above, some memory cells include a separate layer of selector material to form a selector device. The selector material may include a chalcogenide material (e.g., a chalcogenide glass) or other material capable of operating as a selection element. In one example, the selector material includes one or more of: silicon (Si), germanium (Ge), selenium (Se), arsenic, tellurium (Te), or other materials. In one example, the selector material includes Si—Ge—As—Se, As—Ge—Te—Si, or other selector material. The selector material may also include dopants such as: aluminum (Al), oxygen (O), nitrogen (N), silicon (Si), carbon (C), boron (B), zirconium (Zr), hafnium (Hf), or a combination thereof. The selector material may include other materials or dopants not explicitly listed.

The access lines604,606electrically couple the memory cell100with circuitry that provides power to and enables access to the memory cell100. The term “coupled” can refer to elements that are physically, electrically, and/or communicatively connected either directly or indirectly, and may be used interchangeably with the term “connected” herein. Physical coupling can include direct contact. Electrical coupling includes an interface or interconnection that allows electrical flow and/or signaling between components. Communicative coupling includes connections, including wired and wireless connections, that enable components to exchange data. The access lines604,606can be referred to as a bit line and word line, respectively. The word line is for accessing a particular word in a memory array and the bit line is for accessing a particular bit in the word. The access lines604,606can be composed of one or more metals including: Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicide nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN, or any other suitable electrically conductive material.

In one example, electrodes608are disposed between storage material602and access lines604,606. Electrodes608electrically couple access lines604,606with storage material602. A memory cell with separate layers of storage and selector material may also include an electrode between the layers of storage and selector material. Electrodes608can be composed of one or more conductive and/or semiconductive materials such as, for example: carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; conductive metal oxides including RuO2, or other suitable conductive materials.

FIG. 7illustrates a portion of a memory cell array700, which can include a memory cell such as the memory cell106ofFIG. 1or memory cell600ofFIG. 6. The memory cell array700is an example of a cross-point memory array. The memory cell array700includes a plurality of access lines704,706, which can be the same or similar as the access lines604,606described with respect toFIG. 6. Access lines704,706can be referred to as bit lines and word lines. In the example illustrated inFIG. 7, the bit lines (e.g., access lines704) are orthogonal to the word lines (e.g., access lines706). A storage material702is disposed between the access lines704,706. In one example, a “cross-point” is formed at an intersection between a bit line, a word line. A memory cell is created from the storage material702between the bit line and word line where the bit line and word line intersect. The storage material702can be a chalcogenide material, phase change material, both a chalcogenide material and phase change material, or other storage material. In one example, the access lines704,706are composed of one or more conductive materials such as the access lines604,606described above with respect toFIG. 6.

Although a single level or tier of memory cells is shown inFIG. 7for the sake of clarity, memory cell array700typically includes multiple levels or tiers of non-volatile memory cells (e.g., in the z-direction). Nonvolatile memory devices including multiple tiers of cross-point memory cells may be referred to as three-dimensional (3D), multi-level, or multi-tiered cross-point memory devices. TheFIGS. 6 and 7illustrate an example of a memory cell and array in which the multi-level cell (MLC) techniques described herein may be implemented. However, the programming techniques described herein can be implemented in memory cell structures and arrays having different materials or structures than the examples described inFIGS. 6 and 7.

FIG. 8is a block diagram of a system that can include a non-volatile memory device in accordance with examples described herein.

System800includes components of a memory subsystem having random access memory (RAM)820to store and provide data in response to operations of processor810. The system800receives memory access requests from a host or a processor810, which is processing logic that executes operations based on data stored in RAM820or generates data to store in RAM820. The processor810can be or include a host processor, central processing unit (CPU), microcontroller or microprocessor, graphics processor, peripheral processor, application specific processor, or other processor, and can be single core or multicore.

The system800includes a memory controller830, which represents logic to interface with RAM820and manage access to data stored in the memory. In one example, the memory controller830is integrated into the hardware of processor810. In one example, the memory controller830is standalone hardware, separate from the processor810. The memory controller830can be a separate circuit on a substrate that includes the processor. The memory controller830can be a separate die or chip integrated on a common substrate with a processor die (e.g., as a system on a chip (SoC)). In one example, the memory controller830is an integrated memory controller (iMC) integrated as a circuit on the processor die. In one example, at least some of RAM820can be included on an SoC with the memory controller830and/or the processor810.

In the illustrated example, the memory controller830includes read/write logic834, which includes hardware to interface with the RAM820. The logic834enables the memory controller830to generate read and write commands to service requests for data access generated by the execution of instructions by processor810.

The memory resources or cachelines in the RAM820are represented by a memory cell array826, which can include a cross-point array. The RAM820includes an interface824(e.g., interface logic) to control the access to the memory device array826. The interface824can include decode logic, including logic to address specific rows or columns, bit lines or word lines, or otherwise address specific bits of data. The controller822represents an on-die controller on RAM820to control its internal operations to execute commands received from memory controller830. For example, the controller822can control any of timing, voltage levels, addressing, I/O (input/output) margining, scheduling, and error correction for RAM820.

In one example, the controller822is configured to read and write to the memory device array826(e.g., via set and reset operations) in accordance with any example described herein. A power source840is connected to the RAM820to provide one or more voltage rails for operation of the RAM820.

FIG. 9provides an exemplary depiction of a computing system900(e.g., a smartphone, a tablet computer, a laptop computer, a desktop computer, a server computer, etc.). As observed inFIG. 9, the system900may include one or more processors or processing units901. The processor(s)901may include one or more central processing units (CPUs), each of which may include, e.g., a plurality of general-purpose processing cores. The processor(s)901may also or alternatively include one or more graphics processing units (GPUs) or other processing units. The processor(s)901may include memory management logic (e.g., a memory controller) and I/O control logic. The processor(s)901can be similar to, or the same as, the processor810ofFIG. 8.

The system900also includes memory902(e.g., system memory), non-volatile storage904, communications interfaces906, and other components908. The other components may include, for example, a display (e.g., touchscreen, flat-panel), a power supply (e.g., a battery or/or other power supply), sensors, power management logic, or other components. The communications interfaces906may include logic and/or features to support a communication interface. For these examples, communications interface906may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links or channels. Direct communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCIe specification. Network communications may occur via use of communication protocols or standards such those described in one or more Ethernet standards promulgated by IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may also occur according to one or more OpenFlow specifications such as the OpenFlow Switch Specification. Other examples of communications interfaces include, for example, a local wired point-to-point link (e.g., USB) interface, a wireless local area network (e.g., WiFi) interface, a wireless point-to-point link (e.g., Bluetooth) interface, a Global Positioning System interface, and/or other interfaces.

The computing system also includes non-volatile storage904, which may be the mass storage component of the system. The non-volatile storage904can be similar to, or the same as, the RAM820ofFIG. 8, described above. Non-volatile storage904may include byte or block addressable types of non-volatile memory having a cross-point memory structure. Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory (e.g., 3D NAND flash memory), NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) that incorporates memristor technology, spin transfer torque MRAM (STT-MRAM), or a combination of any of the above. In one example, the non-volatile storage904may include mass storage that is composed of one or more SSDs (solid state drives), DIMMs (dual in line memory modules), or other module or drive. The non-volatile storage904may include MLC memory cells and implement techniques for accessing the MLC memory cells in accordance with examples described herein.

Besides what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.