FPGA functionality mode switch-over

In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA. In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

FIELD

Embodiments of the invention relate generally the field of field programmable field arrays (FPGAs), and relate particularly to the use of a FPGA device in the environment that requires FPGA re-configuration.

DESCRIPTION OF RELATED ART

The background description provided herein is for the purpose of generally presenting the context of the disclosure of the invention. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against this present disclosure of the invention.

FPGA re-configuration is performed by various methods. However, there is a continuing need to overcome the constraints and/or disadvantages of conventional approaches.

SUMMARY

Embodiments of the invention relate generally the field of field programmable field arrays (FPGAs), and relate particularly to the use of a FPGA device in the environment that requires FPGA re-configuration.

In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image.

In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. For example, the foregoing general description presents a simplified summary in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the claimed subject matter. This summary is intended to neither identify key or critical elements of the claimed subject matter nor delineate the scope thereof. The sole purpose of the summary is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one (several) embodiment(s) of the invention and together with the description, serve to explain the principles of the invention.

DETAILED DESCRIPTION

In the following detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments of the present invention. Those of ordinary skill in the art will realize that these various embodiments of the present invention are illustrative only and are not intended to be limiting in any way. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure.

In addition, for clarity purposes, not all of the routine features of the embodiments described herein are shown or described. One of ordinary skill in the art would readily appreciate that in the development of any such actual implementation, numerous implementation-specific decisions may be required to achieve specific design objectives. These design objectives will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine engineering undertaking for those of ordinary skill in the art having the benefit of this disclosure. The various embodiments disclosed herein are not intended to limit the scope and spirit of the herein disclosure.

Exemplary embodiments for carrying out the principles of the present invention are described herein with reference to the drawings. However, the present invention is not limited to the specifically described and illustrated embodiments. A person skilled in the art will appreciate that many other embodiments are possible without deviating from the basic concept of the invention. Therefore, the principles of the present invention extend to any work that falls within the scope of the appended claims.

In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” (or “coupled”) is intended to mean either an indirect or direct electrical connection (or an indirect or direct optical connection). Accordingly, if one device is coupled to another device, then that connection may be through a direct electrical (or optical) connection, or through an indirect electrical (or optical) connection via other devices and/or other connections.

An embodiment of this invention presents a mechanism that can be used in a system with a FPGA (field programmable gate array) device, a CPLD (or any equivalent device used for the same purpose), and a flash device (i.e., flash memory device or any device used for the same purpose or any suitable non-volatile memory device). Multiple FPGA images are stored in the flash device. The CPLD (complex programmable logic device) is used to store and select which FPGA image to load into the FPGA. An embodiment of this invention presents a mechanism where the system can select which FPGA image can be loaded into the FPGA device. The following are the example scenarios where the invention is used.

(1) Scenario A: Host-controlled manual selection of which FPGA image to load,

(2) Scenario B: FPGA auto-configuration when a current FPGA image is corrupted, and/or

(3) Scenario C: FPGA auto-configuration when a current FPGA image is partially working, but a connection to the host is gone or has failed.

As known to those skilled in the art, a given FPGA image as discussed herein (e.g., RA version1, RA version2, RS version1, RS version2, current FPGA image, or default FPGA image) permits an FPGA (e.g., FPGA120, FPGA220, or FPGA320) to perform a given FPGA functionality (or given FPGA functionality mode) or given FPGA functionalities (or given FPGA functionality modes).

FIG. 1is a block diagram100of a first scenario (Scenario A) before an FPGA functionality mode switch-over of an apparatus105, in accordance with an embodiment of the invention.FIG. 1also shows a block diagram108of the first scenario (scenario A) after an FPGA functionality mode switch-over of the apparatus105, in accordance with an embodiment of the invention. Scenario A involves a host-controlled manual selection (as performed by a host) of which FPGA image to load into an FPGA device.

In an embodiment of the invention, the apparatus105comprises a flash device110, a CPLD115, a FPGA120, and a host125. The flash device110is communicatively coupled to and/or electrically coupled to the CPLD115. The CPLD115is communicatively coupled to and/or electrically coupled to the FPGA120. The host125is communicatively coupled to and/or electrically coupled to the FPGA120.

The flash device110stores FPGA images130. For example, the FPGA images130comprises RA version1(135a) which is the current image in the FPGA120and RA version2(135b) which is another version of the current image in the FPGA120. The number of versions of the current image in the FPGA120may vary as symbolically shown by the dot symbols140.

The FPGA images130also comprises RS version1(145a) which is the target new image for the FPGA120and RS version2(145b) which is another version of the target new image for the FPGA120. The number of versions of the target new image for the FPGA120may vary as symbolically shown by the dot symbols150.

The CPLD115selects and loads an FPGA image into the FPGA device120. The CPLD115stores FPGA images into the flash device110.

The FPGA120currently stores RA version1(135a) which is the current FPGA image in diagram100. The CPLD115previously selected (152) and previously loaded (152) the current image135ainto the FPGA120.

The host125can be, for example, a central processing unit (CPU), a server or another type of computer, or another type of host device. The host125provides a software-control mode switch-over for providing a FPGA functionality mode switch-over so that the host125provides a host-controlled manual selection of which FPGA image to load into the FPGA120from the flash device110. The host125controls the switching from the current image135ain the FPGA120to a target new image145ain the FPGA120.

The FPGA120comprises a switch-over control logic155that switches the current image135ain the FPGA120to a target new image145ain the FPGA120.

The scenario A steps are as follows.

In step1(160), the host125triggers a switch from the current image (RA)135ato a target new image (RS)145a.

In step2(165), the switch-over control logic155inside the FPGA120tells the CPLD155to load a new target image145a.

In step3(170), the CPLD115selects and loads the target new image145ainto the FPGA120.

The switch-over control logic155is communicatively coupled to and/or electrically coupled to the CPLD115by the switch-over interface175. The CPLD115is communicatively coupled to and/or electrically coupled to the FPGA120by the FPGA configuration interface176. The FPGA configuration interface176is also shown inFIGS. 2 and 3.

The scenario A after the FPGA functionality mode switch-over is shown in diagram108. In diagram108, the target image145ahas been loaded into the FPGA120.

FIG. 2is a block diagram200of a second scenario (Scenario B) before an FPGA auto-configuration when the current FPGA image is corrupted in an apparatus205, in accordance with an embodiment of the invention.FIG. 2also shows a block diagram208of the second scenario (Scenario B) after the FPGA auto-reconfiguration of the apparatus205, in accordance with an embodiment of the invention. Scenario B involves an FPGA auto-reconfiguration when the current FPGA image in an FPGA (e.g., FPGA220) is corrupted.

In an embodiment of the invention, the apparatus205comprises a flash device110, a CPLD215, a FPGA220, and a host225. Features and/or functions of the flash device110, CPLD215, FPGA220, and host225have been similarly discussed with reference to the flash device110, CPLD115, FPGA120, and host125, respectively, inFIG. 1. Additional features and/or functions of the flash device110, CPLD215, FPGA220, and host225are also discussed below.

The flash device110is communicatively coupled to and/or electrically coupled to the CPLD215. The CPLD215is communicatively coupled to and/or electrically coupled to the FPGA220. The host225is communicatively coupled to and/or electrically coupled to the FPGA220.

The flash device110stores FPGA images130. For example, the FPGA images130comprises RA version1(135c) which is the default FPGA image in the FPGA220and RA version2(135d) which is the current FPGA image in the FPGA220. The number of versions of the current FPGA image in the FPGA120may vary as symbolically shown by the dot symbols140.

The FPGA images130also comprises RS version1(145a) which is the target new image for the FPGA120and RS version2(145b) which is another version of the target new image for the FPGA120. The number of versions of the target new image for the FPGA120may vary as symbolically shown by the dot symbols150.

The FPGA220currently stores RA version2(current FPGA image)135din diagram200. The CPLD215previously selected (252) and previously loaded (252) the current FPGA image135dinto the FPGA220.

The host225controls the switching from the current FPGA image135din the FPGA220to a target new image145ain the FPGA220.

The CPLD215loads a default FPGA image135cwhen a heartbeat signal265from the heartbeat generator262is gone.

The scenario B steps are as follows.

In step1(260), a heartbeat generator262(in FPGA220) continuously generates a heartbeat signal265, with the heartbeat generator262sending the heartbeat signals265to the CPLD215.

In step2(267), the heartbeat monitor268(in CPLD215) monitors the heartbeat signal265from the FPGA device220. When the current FPGA image135dis corrupted, the heartbeat generator262stops the generation of the heartbeat signal265.

In step3(270), the heartbeat monitor268detects that the heartbeat signal265from the FPGA220is gone. In step3(270), the CPLD215loads (272) the default image135cinto the FPGA220.

In step4(285), the CPLD215sends a default image switch signal286to a logic287in the new FPGA image135c. The signal286indicates that a switch to the default FPGA image135chas happened in the FPGA220.

In step5(290), a report292is sent by the logic287to the Host125. The report292indicates to the host225that a switch to the default FPGA image135chas happened in the FPGA220. The host125can then initiate the switch to the new target FPGA image145ainto the FPGA220.

FIG. 3is a block diagram300of a third scenario (Scenario C) before an FPGA auto-reconfiguration of an apparatus305, in accordance with an embodiment of the invention.FIG. 3also shows a block diagram308of the third scenario (Scenario C) after the FPGA auto-reconfiguration of the apparatus305, in accordance with an embodiment of the invention. Scenario C involves a FPGA auto-configuration when the current FPGA image in the FPGA is partially working, but a connection to the host is gone or has failed.

In an embodiment of the invention, the apparatus305comprises a flash device110, a CPLD315, a FPGA320, and a host325. Features and/or functions of the flash device110, CPLD315, FPGA320, and host325have been similarly discussed with reference to the flash device110, CPLD115, FPGA120, and host125, respectively, inFIG. 1. The flash device110is communicatively coupled to and/or electrically coupled to the CPLD315. The CPLD315is communicatively coupled to and/or electrically coupled to the FPGA320. The host325is communicatively coupled to and/or electrically coupled to the FPGA320.

The flash device110stores FPGA images130. For example, the FPGA images130comprises RA version1(135c) which is the default FPGA image in the FPGA320and RA version2(135d) which is the current FPGA image in the FPGA320. The number of versions of the current FPGA image in the FPGA320may vary as symbolically shown by the dot symbols140.

The FPGA images130also comprises RS version1(145a) which is the target new image for the FPGA320and RS version2(145b) which is another version of the target new image for the FPGA320. The number of versions of the target new image for the FPGA320may vary as symbolically shown by the dot symbols150.

The CPLD315loads a default FPGA image135cinto the FPGA320with the heartbeat signal from the heartbeat generator in the host325is gone.

The FPGA320currently stores RA version2(current FPGA image)135din diagram300. The CPLD115previously selected (352) and previously loaded (352) the current image135ainto the FPGA320.

The host325controls the switching from the default image in the FPGA320to a target image145ain the FPGA320.

The Scenario C steps are as follows.

In step1(360), a heartbeat generator362in the host side (i.e., host325) continuously generates heartbeat signal365, and the heartbeat generator362sends the heartbeat signals365to the FPGA device320.

In step2(367), the FPGA device320passes the heartbeat signal365to the CPLD315. The FPGA device320comprises a heartbeat pass-through logic368that passes the heartbeat signal365from the host325to the CPLD315.

In step3(369), the heartbeat monitor370(in CPLD315) monitors the heartbeat signal365from the FPGA device320. When the current FPGA image135dis partially working, but a host connection372(e.g., PCIe link or Peripheral Component Interconnect Express link) is gone or becomes defective, the heartbeat signal365from the host325is not received by the FPGA320.

In step4(375), the heartbeat monitor370detects that the heartbeat signal365from the FPGA320is gone. The CPLD315loads (377) the default image135cinto the FPGA320.

In step5(380), the CPLD315sends a default image switch signal382to a logic384in the new FPGA image135c. The signal382indicates that a switch to the default FPGA image135chas happened in the FPGA320.

In step6(385), a report386is sent form the logic384to the Host325that a switch to the default FPGA image135chas happened in the FPGA320. The Host325can then initiate the switch to the new target FPGA image145ain the FPGA320.

FIG. 4is a flow diagram of a method400, in accordance with an embodiment of the invention.

At405, an FPGA stores a current FPGA image.

At410, an event occurs that triggers a switch of an FPGA image in the FPGA to another FPGA image.

The event410may be a host-controlled manual selection. At415, a host-controlled manual selection is performed to switch an FPGA image (in the FPGA) to another FPGA image.

The event410may be a current FPGA image (in the FPGA) become corrupted. At420, an FPGA auto-configuration is performed when the current FPGA image (in the FPGA) is corrupted.

The event410may be a connection to a host as subject to failure. At425, an FPGA auto-configuration is performed when the current FPGA image (in the FPGA) is partially working, but a connection to the host has failed, wherein the host is communicatively coupled to and/or electrically coupled to the FPGA.

Embodiments of the invention relate generally the field of field programmable field arrays (FPGAs), and relate particularly to the use of a FPGA device in the environment that requires FPGA re-configuration.

In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image.

In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

The word “exemplary” (or “example”) is used herein to mean serving as an example, instance, or illustration. Any aspect or embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other aspects or embodiments or designs. Similarly, examples are provided herein solely for purposes of clarity and understanding and are not meant to limit the subject innovation or portion thereof in any manner. It is to be appreciated that a myriad of additional or alternate examples could have been presented, but have been omitted for purposes of brevity and/or for purposes of focusing on the details of the subject innovation.

As used in herein, the terms “component”, “system”, “module”, “element”, and/or the like are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution. For example, a component or element may be, but is not limited to being, a process running on a processor, a processor, an object, an instance, an executable, a thread of execution, a program, and/or a computer. By way of example, both an application running on a computer and the computer can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers.

Foregoing described embodiments of the invention are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, it is contemplated that functional implementation of invention described herein may be implemented equivalently in hardware, software, firmware, and/or other available functional components or building blocks, and that networks may be wired, wireless, or a combination of wired and wireless.

It is also within the scope of the present invention to implement a program or code that can be stored in a non-transient machine-readable medium (or non-transitory machine-readable medium or non-transient computer-readable medium or non-transitory computer-readable medium) having stored thereon instructions that permit a method (or that permit a computer) to perform any of the inventive techniques described above, or a program or code that can be stored in an article of manufacture that includes a non-transient computer readable medium (non-transitory computer readable medium) on which computer-readable instructions for carrying out embodiments of the inventive techniques are stored. Other variations and modifications of the above-described embodiments and methods are possible in light of the teaching discussed herein.