Computer architecture and system for efficient management of bi-directional bus

An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.

BACKGROUND

Computer systems typically incorporate one or more buses to facilitate communication between devices or components in the system. As used herein, a bus is a plurality of wires or conductors to which multiple agents or devices are coupled in order to transport data or signals among and between the agents or devices. A bi-directional bus provides for reads and writes (i.e., communications in both directions) to occur on common wires or conductors. Typically, a bus has a certain protocol which is to be followed by all of the agents coupled to the bus. Having a consistent protocol ensures all agents use the same rules of communication on the bus.

Since a bus is essentially a group of shared conductors or wires, it is important that the agents share the bus in the manner prescribed by the bus protocol. Moreover, it is important that only one agent drive the bus (i.e., issue or place signals on the shared wires of the bus) at a time. When multiple agents attempt to drive the bus at the same time, it is called a bus conflict or bus contention. Bus contention will often result in the signals or data on the bus being corrupted or unreliable and may also result in damage to the agents on the bus.

To avoid bus contention, dead time or “bubbles” may be introduced on the bus between bus transactions. Bubbles ensure the last transaction is complete before the next transaction is attempted. The use and necessity of bubbles is dictated by the bus protocol which may in turn be dictated by the agents or devices connected to the bus. In some bi-directional buses, for example the RAMbus® a standard memory bus, a bubble is only required for transitions from reads to writes or vice versa. In computer systems employing such bi-directional buses, then, the system must incorporate some mechanism to insert bubbles between read/write transitions to ensure that multiple agents connected to the bus do not attempt to simultaneously drive the bus, i.e., and to ensure there is no bus contention. This bubble or delay time between read/write transitions ensures that the previous transaction, either a read or a write, has ended before the next transaction is attempted. Note that for buses of this type, when the same kind of transaction occurs consecutively on the bus (i.e., consecutive reads or consecutive writes), a delay is not required to ensure there will be no bus contention and thus no bubble is added. Bubbles are only introduced when the bus transactions switch from a read to a write or vice versa.

Although bubbles may be necessary to ensure no bus contention, their occurrence should be minimized because the bubbles result in unused bandwidth that would otherwise be useful to the system for enhanced performance. Specifically, the more bubbles that are introduced, the more wait or delay time that is introduced into the system. Accordingly, a system designers desire to maximize bandwidth and system performance is often at odds with the need to ensure avoidance of bus conflicts by adding bubbles.

One method of reducing the number of bubbles, and the associated delays, would be to stream or group reads and writes together whenever possible. Streaming reads and writes consecutively reduces the number of transitions from reads to writes or vice versa, thereby reducing the number of bubbles required. The system used to group like transactions, however, must also ensure that reads and writes are not indefinitely stalled or starved while a stream of the opposite transaction is being performed on the bus. In particular, the system must ensure read/write fairness and avoid starvation for either.

The present invention is directed at an efficient system and architecture to maximize bandwidth and optimize system performance while avoiding bus contention and read/write starvation.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a novel system and architecture for intelligently managing reads and writes on a bi-directional bus to optimize bus performance, avoid starvation, and introduce bubbles only when needed to avoid bus contention. This is accomplished by separately queuing reads and writes and then using a simple 2 to 1 multiplexer (“mux”) to control the issuance of transactions and bubbles to the bus. The mux is controlled by bus streaming control logic which uses counters, comparators and certain threshold parameters to optimize the system performance by selectively streaming reads and writes together.

The inventive system for managing bi-directional bus usage, comprises: a bi-directional bus; a read queue for pending read bus transactions; a write queue for pending write bus transactions; a mux having a first input coupled to the read queue and a second input coupled to the write queue and an output coupled to the bus; bus streaming control logic coupled to the read queue and the write queue having a first and second control signal coupled to the mux; wherein the bus streaming control logic selectively controls the mux to issue or stream either read transactions from the read queue or write transactions from the write queue to the bus.

In an alternate embodiment of the present invention, the bus streaming control logic of the inventive system further comprises: a first counter to track the number of pending writes in the write queue; a second counter to track the number of consecutive reads issued to the bus; a third counter to track the number of pending reads in the read queue; and a fourth counter to track the number of consecutive writes issued to the bus; as well as a first threshold for pending writes in the write queue; a second threshold for consecutive reads issued to the bus; a third threshold for pending reads in the read queue; and a fourth threshold for consecutive writes issued to the bus.

In an additional alternate embodiment of the present invention, the bus streaming control logic of the inventive system further comprises a plurality of counters to track the number of clock cycles that pending read transactions and write transactions have been waiting in the read queue and the write queue respectively and wherein the bus streaming control logic forces a transition to issue pending transactions which have been waiting for a predetermined amount of time in the queues.

The inventive computer system incorporating the present invention, comprises: a power supply; architecture for managing bi-directional bus usage, comprising: a read queue for pending read bus transactions; a write queue for pending write bus transactions; a mux having a first input coupled to the read queue and a second input coupled to the write queue; bus streaming control logic coupled to the read queue and the write queue having a control signal coupled to the mux; wherein the bus streaming control logic selectively controls the mux to output or stream read transactions from the read queue or write transactions from the write queue.

NOTATION AND NOMENCLATURE

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now to the drawings, wherein like reference characters denote corresponding components or parts:

FIG. 1shows a functional block diagram of the system and architecture10for efficiently managing bus traffic as contemplated by the present invention. Reads and writes set for issuance to the bus are queued in a separate read queue12and write queue14. These queues are collectively referred to herein as pending transaction queues12,14. Each queue12,14is coupled to a multiplexer16or any other switch (collectively referred to herein as a “mux”). The output of the mux16is issued to the bus.

Bus streaming control logic18is coupled to the pending transaction queues12,14to track or monitor the state of the read queue12and write queue14. The bus streaming control logic18is coupled to the mux16via control signals Kill_Rd and Kill_Wr as shown. When the bus streaming control logic18asserts the Kill_Rd signal to the mux16, all reads are blocked by the mux16and the mux16will only issue writes from the write queue14to the bus. When the bus streaming control logic18asserts the Kill_Wr signal, all writes are blocked by the mux16and the mux16will only issue reads from the read queue12to the bus. When both control signals are asserted, neither reads nor writes will be issued to the bus causing a bubble or delay on the bus. Of course if there are no pending transactions in queue, the bus will also be inactive. For example, if Kill_Rd is asserted and Kill_Wr is not asserted, there may still be a delay or bubble if there are no writes pending in the write queue14. Similarly, if Kill_Wr is asserted and Kill_Rd is not asserted, there may still be a delay or bubble if there are no reads pending in the read queue12. The bus streaming control logic18utilizes counters, comparators and threshold parameters to selectively control the streaming of the reads, writes and bubbles to the bus. In various embodiments of the computer system incorporating the present invention, the bus streaming control logic18is in the Middle Mapper/Slotter of the Zbox as described in the applications incorporated herein by reference only.

The system and architecture10as contemplated by the present invention may be more fully understood by discussing an example of its operation. Reads and writes arrive at the pending transaction queues12,14ready for issuance to the bus. Bus streaming control logic18uses a counter to track the number of pending reads in the read queue12(a “pending read counter”) and a counter to track the number of pending writes in the write queue14(a “pending write counter”). When a stream of reads is being performed on the bus, the bus streaming control logic18compares the number of pending writes to a first threshold parameter. When the number of pending writes in the write queue14reaches the threshold number, the system is said to become “hungry” for writes and a transition from reads to writes is desired. Although the transition could be effectuated immediately by the bus streaming control logic18, in various embodiments of the invention an additional criteria must be met before a transition is instituted. In particular, when the system becomes hungry for writes, the bus streaming control logic18starts another counter to track the number of consecutive reads issued (an “issued reads counter”). The bus streaming control logic18then compares the number of issued reads to a second threshold parameter. This second threshold parameter ensures that a sufficient stream of reads has been issued before a transition occurs. When the number of issued reads reaches the second threshold number, the system is said to be “starved” for writes and a transition from reads to writes is executed.

The control signals Kill_Rd and Kill_Wr are used to execute a transition from reads to writes. Since only reads are currently being issued to the bus, the Kill_Wr signal is already asserted to the mux16. The bus streaming control logic18then asserts the Kill_Rd signal to stop all reads and writes from issuance to the bus. With both control signals asserted, the mux16prevents any reads or writes from issuance to the bus and a bubble is implemented on the bus (i.e., no reads or writes are issued). After a predetermined amount of time elapses, based on the necessary delay time required by the bus protocol, the bus streaming control logic18unasserts the Kill_Wr signal. With only the Kill_Rd signal asserted, the mux16begins to issue writes from the write queue14to the bus and the transition from reads to writes is complete.

Transitions from writes to reads are similarly handled. When a stream of writes is being performed on the bus, the bus streaming control logic18compares the number of pending reads to a third threshold parameter. When the number of pending reads in the read queue14reaches the threshold number, the system is said to become “hungry” for reads and a transition from writes to reads is desired. Although the transition could be effectuated immediately by the bus streaming control logic18, in various embodiments of the invention an additional criteria must be met before a transition is instituted. In particular, when the system becomes hungry for reads, the bus streaming control logic18starts another counter to track the number of consecutive writes issued (an “issued writes counter”). The bus streaming control logic18then compares the number of issued writes to a fourth threshold parameter. This fourth threshold parameter ensures that a sufficient stream of writes has been issued before a transition occurs. When the number of issued writes reaches the fourth threshold number, the system is said to be “starved” for reads and transition from writes to reads is executed.

The control signals Kill_Rd and Kill_Wr are also used to execute a transition from reads to writes. Since only writes are being issued to the bus, the Kill_Rd signal is already asserted to the mux16. The bus streaming control logic18then asserts the Kill_Wr signal to stop all writes and reads from issuance to the bus. With both control signals asserted, the mux16prevents any reads or writes from issuance to the bus and a bubble is implemented on the bus (i.e., no reads or writes are issued). After a predetermined amount of time elapses, based on the necessary delay time required by the bus protocol, the bus streaming control logic18unasserts the Kill_Rd signal. With only the Kill_Wr signal asserted, the mux16begins to issue reads from the read queue12to the bus and the transition from writes to reads is complete.

In order to accomplish this control of the bus usage, 4 counters and 4 threshold parameters have been used as follows:

CountersExemplary Thresholds1. number of pending writes1. threshold for pending writes (4)2. number of consecutive reads2. threshold for consecutive reads (8)3. number of pending reads3. threshold for pending reads (1)4. number of consecutive writes4. threshold for consecutive writes (8)
As discussed above, counters1and3continuously track and monitor the number of writes and reads pending in the write queue14and read queue12, respectively. When counter1reaches the threshold1for pending writes, the system becomes hungry for writes and counter2is started to track the number of consecutive reads executed. When counter2reaches threshold2for consecutive reads issued, the system is starved for writes and a transition from reads to writes occurs. Similarly, when counter3reaches the threshold3for pending reads, the system becomes hungry for reads and counter4is started to track the number of consecutive writes executed. When counter4reaches threshold4for consecutive writes issued, the system is starved for reads and transition from writes to reads occurs.

It should be noted that in the discussion of the present invention to this point, there is the potential for a problem. In particular, when thresholds1or3are set to a number greater than 1, there is the potential for a read or write to become stranded in the pending transaction queues12,14(i.e., real or complete starvation of a read or write). For instance, if a stream of reads is being executed in various embodiments (where threshold1for pending writes is set to 4), when a write arrives at the write queue14, it must wait until4writes have accumulated in the queue before the system will become hungry and begin counting the consecutive reads issued. If no other writes are forthcoming, the write could remain stranded in the write queue14indefinitely.

Obviously, indefinitely delaying a pending transaction could introduce additional and indefinite latency in the system as a whole. To avoid this possibility, an additional counter can be used to track the number of clock cycles a transaction has been waiting in the pending transaction queues12,14and to ensure the transactions do not wait indefinitely for a transition. Specifically, in the various embodiments a counter is started when the first write enters the write queue14. The counter is incremented each clock cycle to track the amount of time the write has been waiting. If a transition has not been completed in a predetermined amount of time, i.e., before the counter reaches a predetermined value, then the system is forced to become hungry for writes (as if 4 writes had accumulated in the write queue14). Accordingly, the counter2for consecutive reads is started and a transition occurs when it reaches the threshold2for consecutive reads. This assures that the write will not remain in the queue indefinitely waiting for 4 writes to accumulate. Such a counter is not required for reads in various embodiments because the threshold for reads is set to 1, meaning the system becomes hungry for reads as soon as a read enters the read queue12. Similar counters should be used if the thresholds1or3are set greater than 1 in order to ensure there is not indefinite starvation of reads or writes.

FIG.2andFIG. 3attempt to illustrate the increased performance realized by the present invention.FIG. 2illustrates reads and writes indiscriminately issued on a bus as would often occur prior to the present invention. InFIG. 2, reads are represented by an R on the bus and writes are represented by a W. Between each transition from read to write or vice versa, a bubble or delay is inserted to ensure there is no bus contention. Bubbles are represented by an X. In the example illustrated inFIG. 2, there are three reads and three writes being issued on the bus. Because the reads and writes are interspersed, however, several bubbles are required between the read/write transitions. Assuming each read, write and bubble takes a clock cycle, 11 cycles are required to issue the three reads and three writes as illustrated in FIG.2.

FIG. 3illustrates reads and writes issued on a bus as contemplated by the present invention. In particular, three reads and three writes are also depicted on the bus in FIG.3. The reads and writes inFIG. 3, however, are streamed or grouped together as opposed to intermingled as shown in FIG.2. The result is that only one bubble is required since there is only one transition between reads and writes. Accordingly, only 7 cycles are required to issue three reads and three writes (again assuming each read, write and bubble takes one clock cycle). Thus, by grouping or streaming the reads and writes, 4 cycles were saved from the example in FIG.2. The invention streams the reads and writes to allow more transactions to occur on the bus with less bubbles or latency. The result is increased system performance.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. While the invention has been particularly shown and described with respect to specific embodiments thereof, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.