Selectable device options for characterizing semiconductor devices

A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

FIELD OF THE INVENTION

This disclosure relates generally to characterizing devices to be offered for a semiconductor technology, and more particularly to a system and method of implementing a testsite for characterizing semiconductor devices, which allows a Back End Of Line (BEOL) mask change to be used to select different device options.

BACKGROUND OF THE INVENTION

Each time a new semiconductor technology is introduced, various challenges are presented. A semiconductor technology generally includes substrates and material specification, device specifics, ground rules, critical steps, levels of wiring, and other optional features. Each new technology generation incorporates both evolutionary and revolutionary improvements over the prior generation. Illustrative technologies include the use of deep and shallow trenches, planarization, copper wiring, and silicon-on-insulator (SOI) substrates.

The development of a semiconductor technology requires detailed characterization and optimization of the devices to be offered with the technology. For example, devices such as transistors, capacitors, resistors, diodes, etc., will have different electrical characteristics and properties depending on how they are implemented. For instance, layout differences such as spacing between devices, length of lines, size, etc., will impact device characteristics.

One method for characterizing devices involves the creation of “testsites”, which are essentially chips designed in the technology that include a large number of discrete instances of devices connected to pads in metallization which can be probed. A “macro” refers to a set of chip pads having a subset of related devices. For example, a macro may include 25 pads having six versions of transistor, with each transistor having a slight layout variation. The testsite will typically contain as many macros as possible to cover as many devices and device layout options as possible. Once a testsite chip is fabricated, probes can be used to send and receive electrical signals to and from the pads to characterize the discrete devices.

One of the limitations with using testsites is the fact that testsites often do not have enough space (e.g., total number of pads) to contain an inclusive set of all test macro configurations covering all possible device layout options. Accordingly, it is often the case that the testsite does not include all the particular device layout options that may be implemented in the given technology. This can be particularly problematic early in the technology development phase since the final design to be used is not always known.

Rebuilding a completely new testsite, including a complete set of masks, to change a device layout style being used in the current macros can be unacceptable due to cost and schedule. Accordingly, a need exists for a technique that would allow for the ability to cover more layout options in a testsite without significantly impacting cost and schedule.

SUMMARY OF THE INVENTION

The present disclosure addresses the above mentioned problems, as well as others, by providing a system and method that allows for multiple devices to be placed such that a Back End Of Line (BEOL) mask change can be used to select particular device layouts.

In one embodiment, there is a system for implementing a testsite for characterizing devices in an integrated circuit technology, comprising: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

In a second embodiment, there is a computer program product stored on a computer readable medium for designing a testsite for characterizing devices in an integrated circuit technology, which when executed by a computer system comprises: program code for designing a plurality of device options for a set of chip pads; program code for designing a pseudo wiring layout for each of the plurality of device options; program code for selecting one of the device options; program code for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and program code for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

In a third embodiment, there is a method for implementing a testsite for characterizing devices in an integrated circuit technology, comprising: designing a plurality of device options for a set of chip pads; designing a pseudo wiring layout for each of the plurality of device options; selecting one of the device options; mapping the pseudo wiring layout for a selected device option to a predetermined design level; and outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

In a fourth embodiment, there is a system for generating an integrated circuit, comprising: a system for generating a design layout that includes a plurality of device options for a set of chip pads; a system for selecting one of the device options; a system for instantiating a wiring layout for a selected device option within a Back End Of Line (BEOL) design level; and a system for outputting a configured mask design at the BEOL design level that includes the wiring layout for connecting the selected device option to the set of chip pads.

In a fifth embodiment, there is a design structure embodied in a machine readable medium used in a design flow process, the design structure comprising a testsite, the testsite comprising: a plurality of device options for a set of chip pads; and a pseudo wiring layout for each of the plurality of device options.

The illustrative aspects of the present invention are designed to solve the problems herein described and other problems not discussed. Benefits include the ability to cover primary and backup layout options in a testsite without additional macro area; complete coverage of primary and backup layout options being made available on all wafers with different BEOL masks, rather than minimal coverage of each with a single BEOL mask; and the ability to allow macro “overlap” when a testsite is used to cover multiple technology options and device options or layout styles that are different in the multiple technologies.

The drawings are merely schematic representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict only typical embodiments of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbers represent like elements.

DETAILED DESCRIPTION OF THE INVENTION

As noted above, a testsite is essentially a semiconductor design that includes sets of device layouts, which, when fabricated, can be probed to characterize the device layouts contained within the testsite. A testsite is implemented with a set of masks, which are designed using software tools. Once designed, the masks can be printed, and then be used in a fabrication process to produce a physical testsite chip. The embodiments described herein allow for multiple devices to be placed between pads of a testsite chip such that a Back End Of Line (BEOL) mask change can be used to select different device options.

Note that while in one illustrative embodiment, the BEOL mask change involves instantiating different wiring designs on the metal one (M1) layer, it is understood that the techniques and processes described herein could be applied on any layer (e.g., M2, vias, etc.). Moreover, it is understood that the teachings are not limited to implementing any particular device options, i.e., device options may include any type of device (e.g., transistors, resistors, capacitors, etc.) and any type of layout (e.g., line size, configuration, widths, number of fingers, position, density, etc.).

FIG. 1depicts a flow diagram of an illustrative process for providing selectable device layouts in a testsite design. First at S1, a testsite is designed with n different device options for a given set of pads (e.g., a “macro”). In a simple case, e.g., involving the testing of a resistor design in which only two pads are required, there may be three different layout options (i.e., n=3). In this case, three different device options would be designed between the two pads.

In a more complex arrangement, a macro containing 25 pads may be utilized to accommodate six transistor devices (i.e., four pads per device, with one unused pad resulting in six pad sets). Again, n different device options would be designed between each of the six pad sets. For instance, there may be four different device options (i.e., n=4) that potentially need to be tested for each of the six transistor devices in the macro, resulting in a total of 24 different devices.

At S2, a wiring layout is designed for each device option on a “pseudo” Back End Of Line (BEOL) level. In an illustrative embodiment, the wiring for each design option may be designed on different pseudo metal one (M1) layers. For instance, in an application having four design options, wiring can be designed on levels M1_A, M1_B, M1_C and M1_D.

At S3, one of the n device options is selected for implementation. This may, for example, be via a software interface by an end user. At S4, the wiring for the selected device (e.g., on level M1_A) is mapped to the actual BEOL level (e.g., the M1 level). At S5, a BEOL mask is generated having the wiring for the selected device option. Finally, at step S6, the masks are printed and a testsite chip is fabricated. Thus, although the physical chip will actually contain multiple device options, only one of the options will actually be wired. In the event that a different device option is needed, S3-S6can be repeated with a different device option being selected. Only the BEOL mask needs to be updated to effectuate the desired changes. Accordingly, only a single design level needs to be changed to implement a different device structure.

FIG. 2depicts an illustrative portion of a testsite design having pads12,14and16at the M1 level. In this example, four device options18(d1, d2, d3, d4) have been designed between the pads12,14, and16. In addition, four associated wiring layouts20,22,24and26have been designed on four pseudo levels. For example, wiring layout20has been designed for device option d1on a first pseudo level shown with horizontal line shading, wiring layout22has been designed for device option d2on a second pseudo level shown with dot shading, wiring layout24has been designed for device option d3on a third pseudo level shown with diagonal line shading, and wiring layout26has been designed for device option d4on a fourth pseudo level shown with cross hatching.

FIG. 3depicts the design result after device option d1was selected for implementation. In this case, wiring layout20is mapped to the M1 level, where it will be included in the actual M1 mask.

FIG. 4depicts an alternative embodiment in which three device options28,29, and30are provided between source and drain pads32and34, and gate line40. In this case, vias42(shown with X's) are utilized to wire the selected device option28to associated regions36,38and40, to ultimately provide connection to pads32and34, and line40. In this case, device28has been selected for wiring.

FIG. 5depicts a computer system50having a testsite design system58implemented as a software program product in memory56for generating a set of fixed mask designs74and a configured BEOL mask design70. Once created, the fixed mask designs74and configured BEOL mask design70can be printed into physical masks82,84by mask printing system76, and then used by fabrication process78to fabricate a testsite chip78. Fixed mask designs74are utilized to generate a set of fixed masks84to implement all of the layout features for fabricating testsite chip80, with the exception of one BEOL level that is implemented by a BEOL mask84printed from configurable BEOL mask design70.

Fixed mask designs74may be created based on layout parameters68using known design techniques and tools within testsite design system58. Configured BEOL mask design70is generated using an additional set of software tools, shown in this illustrative embodiment as: device option design system60, pseudo wiring design system62, device option selection system64and mapping system66. Device option design system60provides a process for providing a set of device options in a given region between a set of pads (e.g., devices d1, d2, d3and d4ofFIG. 2). Pseudo wiring design system62provides a process for designing a pseudo wiring design for each of the device options. Device option selection system64provides a process for selecting a device option72from the set of device options. Mapping system66maps the pseudo wiring associated with the selected device option72to the BEOL layer, e.g., the M1 layer. Once the wiring for the selected device option72is mapped, configured BEOL mask design70can be used to create BEOL mask82, which is then used in a BEOL fabrication step in building testsite chip80. Once fabricated, probing system86can be used to probe chip pads to characterize the selected device options.

In the event that device options provided in the configurable BEOL mask design70need to be changed, an alternative device option72can be inputted into device option selection system64and cause mapping system66to instantiate a different device option selected from the layout created by device option design system60. A new configured BEOL mask design70can then be used to generate a different BEOL mask82for fabrication process78. Thus, no changes need to be made to each of the fixed masks84to instantiate different device options.

It is understood that computer system50may be implemented as any type of computing infrastructure. Computer system50generally includes a processor52, input/output (I/O)54, memory56, and bus57. The processor52may comprise a single processing unit, or be distributed across one or more processing units in one or more locations, e.g., on a client and server. Memory56may comprise any known type of data storage and/or transmission media, including magnetic media, optical media, random access memory (RAM), read-only memory (ROM), a data cache, a data object, etc. Moreover, memory56may reside at a single physical location, comprising one or more types of data storage, or be distributed across a plurality of physical systems in various forms.

I/O54may comprise any system for exchanging information to/from an external resource. External devices/resources may comprise any known type of external device, including a monitor/display, speakers, storage, another computer system, a hand-held device, keyboard, mouse, voice recognition system, speech output system, printer, facsimile, pager, etc. Bus57provides a communication link between each of the components in the computer system50and likewise may comprise any known type of transmission link, including electrical, optical, wireless, etc. Although not shown, additional components, such as cache memory, communication systems, system software, etc., may be incorporated into computer system50.

Access to computer system50may be provided over a network such as the Internet, a local area network (LAN), a wide area network (WAN), a virtual private network (VPN), etc. Communication could occur via a direct hardwired connection (e.g., serial port), or via an addressable connection that may utilize any combination of wireline and/or wireless transmission methods. Moreover, conventional network connectivity, such as Token Ring, Ethernet, WiFi or other conventional communications standards could be used. Still yet, connectivity could be provided by conventional TCP/IP sockets-based protocol. In this instance, an Internet service provider could be used to establish interconnectivity. Further, as indicated above, communication could occur in a client-server or server-server environment.

It should be appreciated that the teachings of the present invention could be offered as a business method on a subscription or fee basis. For example, a computer system50comprising a testsite design system58could be created, maintained and/or deployed by a service provider that offers the functions described herein for customers. That is, a service provider could offer to deploy or provide the ability to generate configurable BEOL mask designs70as described above.

It is understood that in addition to being implemented as a system and method, the features may be provided as a program product stored on a computer-readable medium, which when executed, enables computer system50to provide a testsite design system58. To this extent, the computer-readable medium may include program code, which implements the processes and systems described herein. It is understood that the term “computer-readable medium” comprises one or more of any type of physical embodiment of the program code. In particular, the computer-readable medium can comprise program code embodied on one or more portable storage articles of manufacture (e.g., a compact disc, a magnetic disk, a tape, etc.), on one or more data storage portions of a computing device, such as memory56and/or a storage system, and/or as a data signal traveling over a network (e.g., during a wired/wireless electronic distribution of the program product).

FIG. 6shows a block diagram of an example design flow1000. Design flow1000may vary depending on the type of IC being designed. For example, a design flow1000for building an application specific IC (ASIC) will differ from a design flow1000for designing a standard component. Design structure1020is an input to a design process1010and may come from an IP provider, a core developer, or other design company. Design structure1020comprises a circuit, such as that shown inFIGS. 2-4, in the form of schematics or HDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.). Design structure1020may be on one or more of a machine readable medium such as that described herein. For example, design structure1020may be a text file or a graphical representation of a circuit. Design process1010synthesizes (or translates) the circuit into a netlist1080, where netlist1080is, for example, a list of fat wires, transistors, logic gates, control circuits, I/O, models, etc. and describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of a machine readable medium.

Design process1010includes using a variety of inputs; for example, inputs from library elements1030which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g. different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1040, characterization data1050, verification data1060, design rules1070, and test data files1085, which may include test patterns and other testing information. Design process1010further includes, for example, standard circuit design processes such as timing analysis, verification tools, design rule checkers, place and route tools, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process1010without deviating from the scope and spirit of the invention.

Ultimately, design process1010translates a circuit, along with the rest of the integrated circuit design (if applicable), into a final design structure1090(e.g., information stored in a GDS storage medium). Final design structure1090may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test data, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce a circuit such as that shown inFIGS. 2-4. Final design structure1090may then proceed to a stage1095of design flow1000; where stage1095is, for example, where final design structure1090: proceeds to tape-out, is released to manufacturing, is sent to another design house or is sent back to the customer.