Method of fabricating FLASH memory devices

A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked, are formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Along each of the first active regions, the hard mask pattern is removed at regular intervals to expose a top of the conductive pattern. An oxide pattern is formed on the exposed top of the conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns arranged over each of the first active regions at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate patterns. A plurality of control gate electrodes are formed to cross over the first active regions. The control gate electrodes are disposed on the floating gate patterns.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a FLASH memory device, and more particularly to a method of fabricating a FLASH memory device including a split gate.

2. Discussion of Related Art

FLASH memory devices can electrically write or erase data. FLASH memory devices maintain data without a power supply. Therefore, the FLASH memory devices have been widely used in various technologies. FLASH memory devices can be classified into NAND type and NOR type devices according to a structure of a memory cell array. Comparatively, NAND type FLASH memory devices can be highly integrated within a unit area of a circuit and NOR type FLASH memory devices have a fast response speed.

In NOR type FLASH memory devices, memory cells are arranged along rows and columns, a plurality of bit lines are disposed parallel to the rows and a plurality of word lines are disposed with parallel to columns. The memory cells in each of the rows are connected to a bit line in parallel and the memory cells in each of the columns are connected to a word line in parallel.

A memory cell of a NOR type FLASH memory device is selected by selecting a word line and a bit line. Accordingly, the memory cells of NOR type FLASH memory devices can be accessed randomly, so that the response speed thereof is faster than that of the NAND type FLASH memory device. In the NOR type FLASH memory device, a plurality of memory cells are connected to a bit line in parallel, so that if a memory cell transistor connected to the bit line is erased, current passes through the bit line regardless of a state of a selected memory cell. Therefore, each memory cell that is connected to the bit line is read as if the memory cells are in a turned-on state.

A split gate type FLASH memory device is another type of FLASH memory device. Word lines of the split gate type FLASH memory device act as a selection gate and a control gate, overlap a portion of a floating gate.

FIG. 1Ais a top plane view of a conventional split gate type FLASH memory device.

Referring toFIG. 1A, device isolation layers8are disposed to defined first and second active regions12aand12b, which intersect each other. A pair of floating gate patterns14are disposed on each first active region12abetween adjacent second active regions12b. Word lines18crossing over the first active regions12aare disposed on the floating gate patterns14. The word lines18lie on top of the floating gate patterns14and on the first active regions12abeside a sidewall of the floating gate patterns14. Drain regions are formed in the first active regions12abetween adjacent word lines18and a bit line plug20is connected to each drain region.

Referring toFIG. 1B, after active regions12aand12bare defined in a substrate, a conductive layer is formed. The conductive layer is patterned to form a floating gate14of the conventional split gate type nonvolatile memory device. Edges of a pattern formed by a photolithographic process are rounded due to a proximity effect even though the pattern is designed to be rectangular in layout. As illustrated in theFIG. 1B, a width of the elliptical floating gate pattern may reduced at the edges, so that when the floating gate pattern is misaligned, a channel under the floating gate decreases in width and influences characteristics of the memory cell. Thus, variations in cell characteristics in a cell array may be widened. Referring toFIG. 1C, if a width of the active region becomes narrow due to a high integration of the semiconductor device, a misalignment of the floating gate causes a direct contact of a word line18and a substrate10between a device isolation layer8and the floating gate pattern14. In addition, the floating gates of the adjoining memory cells connected to adjoining bit lines needs to be separated from each other on the device isolation layer by a predetermined distance, so that the distance between the adjoining floating gates should be defined wider than a minimum line width. Therefore, the width of the device isolation pattern8may not be reduced to a minimum line width.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a split gate type FLASH memory device is formed comprising floating gate patterns thereof without harmful influence of a misalignment or a proximity effect during a photolithographic process.

According to an embodiment of the present invention, a method of forming a split gate type FLASH memory device minimizes variations in cell characteristics in a cell array.

According to an embodiment of the present invention, there are provided methods of fabricating a split gate type FLASH memory device including floating gates with sidewalls aligned to sidewalls of a trench device isolation layer. The methods comprise forming trench device isolation layers to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked and include sidewalls aligned to sidewalls of the trench device isolation layer, are formed on the first active region. The hard mask pattern is removed at regular intervals along each first active region so as to expose a top of the conductive pattern. An oxide pattern is formed on the exposed conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns disposed on each first active region at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate pattern and a plurality of control gate electrodes are formed, crossing over the first active regions. The control gate electrodes are disposed on the floating gate patterns.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2is a plane view of a NOR type split gate FLASH memory device in accordance with an exemplary embodiment of the present invention.

Referring toFIG. 2, a spilt gate type FLASH memory device includes device isolation layers58disposed in a substrate to define a plurality of first active regions62athat are parallel to each other. Floating gate patterns64are disposed on the first active regions62aat regular intervals. A plurality of parallel word lines68crossing over the first active regions62aare disposed on the floating gate patterns64. The word lines68lie on a plurality of floating gate patterns64and the first active regions62abeside a sidewall of each of the plurality of floating gate patterns64.

The device isolation layer58defines a plurality of second active regions62bthat are parallel to each other and cross the first active regions62a. is A pair of floating gate patterns64are disposed on each of the first active regions62abetween intersections of the first and second active regions62aand62b. Drain regions are formed in each first active region62abetween the word lines68lying on the first active regions62a. Source regions are formed in each second active region62bbetween the word lines lying on the first active regions62a. A bit line plug70is disposed on each drain region. Therefore, the source region comprises a shared source region where memory cells at both sides of the source region are connected in parallel. A shared source pattern connected to the first active regions62amay be disposed in the position of the second active regions62b, replacing the second active regions62b. In exemplary embodiment of the present invention, the device isolation layer58is formed with a trench structure and the floating gate pattern64includes sidewalls aligned to sidewalls of the device isolation layer58.

FIGS. 3A-9Aare top plane views illustrating a method of fabricating a split gate type FLASH memory device in accordance with the exemplary embodiment of the present invention.

Referring toFIGS. 3A,3B and3C, a gate insulation layer52, a conductive layer54and a hard mask layer56are stacked on a substrate50. The gate insulation layer52may be formed of silicon oxide, silicon oxynitride or the like, the conductive layer54may be formed of polysilicon and the hard mask layer56may be formed of silicon nitride.

Referring toFIGS. 4A,4B and4C, the hard mask layer56, the conductive layer54and the gate insulation layer52are patterned to form a plurality of parallel patterns comprising a gate insulation pattern52a, a conductive pattern54aand a hard mask pattern56a, which are sequentially stacked on the substrate50. Using the hard mask pattern56aas an etch mask, the substrate50is etched to form a trench so as to define a plurality of parallel first active regions60a. An insulation layer is filled within regions between the stacked patterns and the trench, thereby forming a trench isolation layer58. The patterns comprising the gate insulation pattern52a, the conductive pattern54aand the hard mask pattern56a, which are sequentially stacked, are arranged on the first active regions60a. The conductive pattern54aincludes sidewalls55aligned to the sidewalls of the trench isolation layer58. A portion of top of the trench device isolation layer58is recessed to reduce step differences between a substrate where a peripheral circuit and a logic circuit will be formed and device isolation layers. However, the recess needs to be controlled with respect to depth so that a top of the trench isolation layer58is higher than a top of the conductive pattern54a. If the top of the trench isolation layer58is lower than that of the conductive pattern54a, sidewalls of conductive pattern54aare oxidized by a thermal oxidation process for forming an oxide pattern on a floating gate pattern. If the sidewalls of conductive pattern54aare oxidized, it is difficult to form a tip of the floating gate pattern for Fowler-Nordheim tunneling.

As illustrated above, the gate insulation pattern52a, the conductive pattern54aand the hard mask pattern56a, which are stacked on the substrate, may be formed with a mesh. Using the hard mask pattern56aas an etch mask, the substrate50may be etched to form an active region with a mesh. The mesh shaped active region comprises a plurality of parallel first active regions60aand a plurality of second active regions60b, which cross the first active regions60a. Shared source regions of the NOR type FLASH memory device are formed in the second active regions60b.

Referring toFIGS. 5A,5B and5C, a photoresist pattern61is formed over the substrate50. The photoresist pattern61includes a plurality of openings62parallel to the second active regions60b. The hard mask pattern56aand the device isolation pattern58are alternately exposed in the openings62. A pair of openings62are disposed between the second active regions60b. Using the photoresist pattern61as an etch mask, the hard mask pattern56ais etched. Therefore, a top of the conductive pattern54ais exposed in each of the openings62at regular intervals. Two parts of the top of the conductive pattern54aare exposed on each of the first active region60abetween the second active regions60b.

Referring toFIGS. 6A,6B and6C, the photoresist pattern61is removed. As a result, the top of the conductive pattern54a, which is defined by the device isolation layers58and the hard mask patterns56a, is exposed over the substrate50like islands arranged along rows and columns. An oxide pattern64is formed on the exposed conductive pattern54a. The oxide pattern64may be formed by performing an oxidation, oxidizing the exposed conductive pattern54a. The oxide pattern64is formed having an elliptical cross-section due to a three dimensional-effect.

Referring toFIGS. 7A,7B and7C, the hard mask pattern56ais removed. As a result, the conductive pattern54ais exposed over the first active region60aand the second active region60b. The oxide patterns64are disposed on the conductive patterns54aat regular intervals.

Referring toFIGS. 8A,8B and8C, using the oxide patterns64as an etch mask, the conductive pattern54ais etched. Thus, floating gate patterns54bare formed on the first active region60aat regular intervals. The floating gate pattern54bincludes sidewalls55aaligned to sidewalls of the trench device isolation layer58. The oxide pattern64is disposed on the top of the floating gate pattern54b. The oxide pattern64has an elliptical cross-section, so that tips may be formed at top edges of the floating gate pattern54b. In the mesh shaped active region comprising the first and second active regions60aand60b, intersections of the first and second active regions60aand60bare disposed on a substrate and a pair of floating gate pattern54bmay be disposed on the first active region60abetween the intersections.

Referring toFIGS. 9A,9B and9C, a conductive layer is formed on an entire surface of a substrate with the floating gate patterns54band patterned to form a plurality of parallel word lines68crossing over the first active regions60a. The word lines68lie on a portion of a top of the floating gate pattern54band on the first active region60aadjacent to the floating gate pattern54b. In addition, adjacent word lines68are disposed symmetrically. A pair of word lines68are disposed between the second active regions60bforming a mesh shaped active region. A drain region is formed in the first active region60abetween the word lines68and a source region is formed in the second active region60bbetween the word lines68.

As a result, a split gate type FLASH memory device of theFIG. 2can be formed.

According to an embodiment of the present invention, a floating gate pattern may not be influenced by a proximity effect or a misalignment occurring during a photolithographic process because a trench device isolation layer is formed first. Further, the floating gate pattern is formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Therefore, a split gate type FLASH memory device can be formed to have substantially uniform cell characteristics in a cell array. In addition, floating gates of the memory cells connected to adjoining bit lines are isolated by the device isolation layer, so that a width of the device isolation layer can be reduced to improve integration of circuits.