Load isolation for pad signal monitoring

A driver circuit includes an output driver including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster.

BACKGROUND

The present disclosure relates generally to signal monitoring and adjustment, and more particularly, to load isolation for pad signal monitoring.

An input/output (IO) driver receives data from a memory controller, level shifts and conditions the data, and outputs the conditioned data to a load, such as, for example, a dynamic random access memory (DRAM). A duty cycle of the data may be adjusted by the IO driver and/or the memory controller. There is currently a need to improve the adjustment of the duty cycle to thereby improve the duty cycle of the data outputted by the IO driver.

SUMMARY

In an aspect of the disclosure, a driver circuit includes an output driver including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster.

In an aspect of the disclosure, a method of adjusting a data signal is provided. The method may be performed by a driver circuit. The driver circuit electrically isolates at least one output driver leg of an output driver from remaining output driver legs of the output driver. The driver circuit monitors an output of the at least one output driver leg when the at least one output driver leg is electrically isolated from the remaining output driver legs. The driver circuit adjusts a duty cycle of a signal based on the monitoring.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Apparatuses and methods will be described in the following detailed description and may be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc.

FIG. 1is a diagram illustrating a standard IO configuration100. Referring toFIG. 1, a standard IO configuration100includes a memory controller/core logic102. The core logic102includes a data module103that is configured to provide data110to an IO driver such as a double data rate (DDR) IO105. The core logic102and the DDR IO105may be part of one integrated circuit (IC) located on a single printed circuit board (PCB). In the configuration100, the data module103is configured to send a data signal110to a level shifter104of the DDR IO105. The level shifter104shifts (e.g., amplifies) a voltage level of the incoming data signal110. The level shifter104outputs the level-shifted data signal to the pre-driver106, which may include one or more inverters or buffers, and which is configured to condition the level-shifted data signal. The pre-driver106outputs the conditioned data signal to an output driver108. The output driver108is configured to receive the conditioned, level-shifted data signal from the pre-driver106, to output the data signal to a pad (also referred to as pad bump, or pad landing) at node118, and to drive the data signal across the transmission line/channel111to the DRAM112. The output driver108may include a plurality of output driver legs connected in parallel. Each of the output driver legs may have approximately the same output impedance (e.g., 240 ohms at a particular frequency). One or more of the output driver legs may be activated to obtain a smaller output impedance. For example, if at a particular frequency each of the output driver legs has an output impedance of 240 ohms, two output driver legs may be activated to obtain an output impedance of 120 ohms, three output driver legs may be activated to obtain an output impedance of 80 ohms, and four output driver legs may be activated to obtain an output impedance of 60 ohms.

FIG. 2is a diagram illustrating an IO configuration200including a duty cycle monitor214and a duty cycle adjuster216. Referring toFIG. 2, an IO configuration200includes a memory controller/core logic202. The core logic202includes a data module203and a duty cycle adjuster216. The data module203is configured to provide a data signal to the duty cycle adjuster216. The duty cycle adjuster216is configured to adjust a duty cycle of the data signal, and to output the data signal210to an IO driver such as a DDR IO205. In the configuration200, the duty cycle adjuster216is configured to send the data signal210to a level shifter204of the DDR IO205. The level shifter204shifts (e.g., amplifies) a voltage level of the incoming data signal210. The level shifter204outputs the level-shifted data signal to the pre-driver206, which may include one or more inverters or buffers, and which is configured to condition the level-shifted data signal. The pre-driver206outputs the conditioned data signal at node219to a duty cycle monitor214and to an output driver208. The duty cycle monitor214monitors the duty cycle of the output of the pre-driver206at node219, and outputs a duty cycle monitoring signal to the duty cycle adjuster216. The duty cycle adjuster216adjusts a duty cycle of the data signal from the data module203based on the duty cycle monitoring signal. The output driver208may have a plurality of legs, such as, for example, four legs208a,208b,208c,208d. The output driver208is configured to receive the conditioned, level-shifted data signal from the pre-driver206, to output the data signal233to a pad (also referred to as pad bump, or pad landing) at node218, and to drive the data signal233across the transmission line/channel211to the DRAM212.

As shown inFIG. 2, the duty cycle monitor214monitors the duty cycle at the node219. However, monitoring the duty cycle at the node219is less than ideal due to duty cycle distortion introduced by the output driver208at node218. Further, monitoring at node218is also less than ideal due to distortion as a result of reflections from the transmission line/channel211and/or the DRAM212. Accordingly, an exemplary driver circuit is provided infra in which the duty cycle monitor214monitors at the output of an output driver.

FIG. 3is a diagram illustrating an exemplary IO configuration300including a duty cycle monitor314and a duty cycle adjuster316according to a configuration. Referring toFIG. 3, an IO configuration300includes a memory controller/core logic302. The core logic302includes a data module303and a duty cycle adjuster316. The data module303is configured to provide a data signal to the duty cycle adjuster316. The duty cycle adjuster316is configured to adjust a duty cycle of the data signal, and to output the data signal310to an IO driver such as a DDR IO305. In the IO configuration300, the duty cycle adjuster316is configured to send the data signal310to a level shifter304of the DDR IO305. The level shifter304shifts (e.g., amplifies) a voltage level of the incoming data signal310. The level shifter304outputs the level-shifted data signal to the pre-driver306, which may include one or more inverters or buffers, and which is configured to condition the level-shifted data signal. The pre-driver306outputs the conditioned data signal at node319to output driver leg308dof the output driver308and to output driver legs308a,308b,308cof the output driver308. As shown, the output driver308includes four legs. However, the output driver308may include x legs (e.g., 4 legs, 8 legs, etc.), with y legs between node319and node330, and x−y legs (e.g., if y=1, then x−y equals 3 legs, 7 legs, etc.) between node319and node318. The output driver leg308dis located within a duty cycle feedback loop that includes the duty cycle monitor314, the duty cycle adjuster316, the level shifter304, and the pre-driver306.

Unlike the IO configuration200shown inFIG. 2, in which the data signal from the core logic202is measured at a node219at an input of the output driver208(i.e., a node219between the pre-driver206and the output driver208), the duty cycle monitor314of the present configuration is connected to a node330to monitor the duty cycle at an output of the output driver leg308dof the output driver308. In the present configuration, the output driver308is shown to include four output driver legs308a-d, although the output driver308of other configurations may include more or fewer output driver legs. The duty cycle monitor314outputs a duty cycle monitoring signal to the duty cycle adjuster316. The duty cycle adjuster316adjusts a duty cycle of the data signal from the data module303based on the duty cycle monitoring signal. The output driver308is configured to receive the conditioned, level-shifted data signal from the pre-driver306, to output the data signal333to a pad at node318, and to drive the data signal333across the transmission line/channel311to the DRAM312.

To improve the effectiveness of the duty cycle monitor314(as compared to the duty cycle monitor214of the IO configuration200shown inFIG. 2), the output of the output driver leg308d, as well as the duty cycle monitor314, are switchably isolated from the node318coupled to the outputs of the remaining output driver legs308a-cand from the load (e.g., transmission line/channel311and DRAM312), while the remaining output driver legs308a-cremain in electrical connection with the load. The isolation module320is configured to be in a closed/conductive state when both the duty cycle monitor314is not monitoring the signal334at the output of the output driver leg308dand the output driver leg308dis enabled, and is configured to be in an open/nonconductive state otherwise. When the output driver leg308dis enabled, drv_308d_en is enabled, and when the duty cycle monitor314is enabled, the pad_mon_en is enabled. The isolation module320is configured to be in a closed/conductive state (en is at a high voltage and en_b is at a low voltage) when both the drv_308d_en is enabled and the pad_mon_en is disabled, and is configured to be in an open/nonconductive state otherwise (en is at a low voltage and en_b is at a high voltage). Accordingly, the isolation module320is in an open/nonconductive state when the drv_308d_en is disabled (e.g., not being utilized as part of the output driver308, such as when the output driver leg308dis not needed to reduce the output impedance of the output driver308), and when both the drv_308d_en and pad_mon_en are enabled.

When the duty cycle monitor314is disabled and the output driver leg308dis enabled for operation with the output driver legs308a-c, the isolation module320electrically connects the output driver leg308dto be in parallel with the output driver legs308a-c. When the duty cycle monitor314is enabled while the output driver leg308dis enabled, the isolation module320isolates the output driver leg308dfrom the node318so that signal reflections (e.g., shown within the signal333) that are reflected from the transmission line/channel311and the DRAM312(due to a mismatch in the impedances) are isolated from the duty cycle monitor314. By isolating the signal reflections from the duty cycle monitor314, the duty cycle adjuster316is able to provide improved adjustment of the duty cycle of the data signal310.

In the present configuration300, the output driver leg308dthat is isolated from the transmission line/channel311and the DRAM312during monitoring by the duty cycle monitor314is the least significant leg of the output driver308(i.e., of the output driver legs308a-d, the isolated output driver leg308dproduces the smallest percentage of power of the output signal, and therefore produces less power than each of the other output driver legs308a-c). By choosing the least significant leg308dto be isolated from the load311,312during monitoring by the duty cycle monitor314, accuracy of the measurements by the duty cycle monitor314is improved, and the signal delivered to the DRAM312during the monitoring is affected less than if a more significant leg were used.

Referring again toFIG. 2, when the duty cycle monitor214is active, the output driver leg208dmay or may not be enabled depending on whether the output driver leg208dis needed to drive the signal233across the transmission line/channel211. However, inFIG. 3, when the duty cycle monitor314is active, the output driver leg308dis enabled to provide an output signal at the node330for the duty cycle monitor314. When the duty cycle monitor314is active, the output from the output driver leg308dis not used to drive the signal333across the transmission line/channel311, as the switch/isolation module320isolates the output from the output driver leg308d.

As shown inFIG. 3, the isolation module320includes a transmission gate, which includes an n-type metal oxide semiconductor (nMOS) transistor321and p-type metal oxide semiconductor (pMOS) transistor323connected in parallel. The isolation module320further includes a NOR gate322as a part of a transmission gate control module, which receives inputs of the pad_mon_en signal and an inverted drv_308d_en signal. The NOR gate322outputs the en signal, which is input to the gate of the nMOS transistor321. The en signal is inverted to provide the en_b signal, which is input to the gate of the pMOS transistor323.

Referring again toFIG. 3, capacitance module340may be coupled to node330in order to improve the results of the duty cycle adjustment. The capacitance module340adds capacitance into the circuit for the duty cycle monitor314in order to account for the isolation of the output capacitance at node318by the isolation module320. The capacitance module340may be a separate module, or may be part of the isolation module320or the duty cycle monitor314. The capacitance module340includes a capacitor341and a transistor342. The transistor342operates as a switch to connect and to disconnect the capacitor341to and from the node330as a function of en_b. The capacitor341may have a capacitance C equal to 1/nthof the output capacitance of the output driver308, where “n” is the number of output driver legs of the output driver308. In other configurations, for improved accuracy of the duty cycle adjustment, the capacitance C may be chosen to be 1/nthof the output capacitance of the output driver308less the capacitance associated with the transmission gate321,323of the isolation module320.

Referring again toFIG. 3, a driver circuit300includes an output driver308, a duty cycle adjuster316, an isolation module320, and a duty cycle monitor314. The output driver308includes a plurality of output driver legs308a-d. The duty cycle adjuster316is configured to adjust a duty cycle of a signal provided to the output driver308. The isolation module320is configured to isolate at least one output driver leg308dof the output driver legs308a-dfrom remaining output driver legs308a-cof the output driver legs308a-d. The duty cycle monitor314is configured to monitor an output of the at least one output driver leg308dwhen the at least one output driver leg308dis isolated from the remaining output driver legs308a-c. The duty cycle monitor314is also configured to provide the monitored output (e.g., signal334) to the duty cycle adjuster316.

The isolation module320may include a transmission gate321,323and a transmission gate control module322. The transmission gate321,323may be coupled between the output of the at least one output driver leg308dand outputs of the remaining output driver legs308a-c. The transmission gate control module322may be configured to close the transmission gate321,323when the at least one output driver leg308dis outputting a signal and the duty cycle monitor314is not monitoring the output (e.g., signal334) of the at least one output driver leg308d. The transmission gate control module322may further be configured to open the transmission gate321,323when the at least one output driver leg308dis not outputting a signal or when the duty cycle monitor314is monitoring the output of the at least one output driver leg308d. The driver circuit300may further include a load capacitance module340configured to introduce a load capacitance341to the output of the at least one output driver leg308dwhen the duty cycle monitor314is monitoring the output of the at least one output driver leg308d. The load capacitance module340may include a transistor342and a capacitor341. The driver circuit300may further include a level shifter304configured to receive a signal from the duty cycle adjuster316to output a level-shifted signal, and may also further include a pre-driver306configured to receive the level-shifted signal from the level shifter304and to provide a conditioned signal to the output driver308. The output driver308may be configured to be coupled to a load312that is configured to receive an output driver signal333from the output driver308. The load312may be DRAM312. The driver circuit300may be a memory controller300.

FIG. 4is a flow chart400of a method of adjusting a data signal. The method may be performed by an apparatus, such as the IO configuration/driver circuit300including the duty cycle adjuster316, the duty cycle monitor314, and the isolation module320shown inFIG. 3. At402, at least one output driver leg of an output driver is isolated from remaining output driver legs of the output driver. The at least one output driver leg may be isolated from the remaining output driver legs by operation of a transmission gate control module to open a transmission gate coupled between the output of the at least one output driver leg and outputs of the remaining output driver legs when the at least one output driver leg is outputting a signal and the output of the at least one driver leg is being monitored. The transmission gate control module may isolate the at least one output driver leg by opening the transmission gate further when the at least one output driver leg is not outputting a signal. For example, referring toFIG. 3, the driver circuit300may electrically isolate at least one output driver leg308dof an output driver308from remaining output driver legs308a-cof the output driver308by operating a transmission gate control module320to open a transmission gate321,323coupled between the output of the at least one output driver leg308dand outputs of the remaining output driver legs308a-cwhen the at least one output driver leg308dis outputting a signal (drv_308d_en is enabled) and the output of the at least one driver leg is being monitored (pad_mon_en is enabled), and the transmission gate control module320may isolate the at least one output driver leg308dby opening the transmission gate321,323when the at least one output driver leg308dis not outputting a signal (drv_308d_en is disabled). At404, an output of the at least one output driver leg is monitored when the at least one output driver leg is electrically isolated from the remaining output driver legs. For example, referring toFIG. 3, the duty cycle monitor314of the driver circuit300may monitor an output of the at least one output driver leg308dwhen the at least one output driver leg308dis electrically isolated from the remaining output driver legs308a-c. At406, a duty cycle of a signal is adjusted based on the monitoring. For example, referring toFIG. 3, the duty cycle adjuster316of the driver circuit300may adjust a duty cycle of a signal produced by the data module303stored in the core logic302based on the monitoring.

At408, the at least one output driver leg of the output driver is electrically connected to the remaining output driver legs of the output driver after performing the monitoring. The transmission gate control module may be operated to electrically connect the at least one output driver leg to the remaining output driver legs by closing a transmission gate when the at least one output driver leg is outputting a signal and the output of the at least one driver leg is not being monitored. For example, referring toFIG. 3, the at least one output driver leg308dof the output driver308may be electrically connected to the remaining output driver legs308a-cof the output driver308after performing the monitoring by operating the transmission gate control module320to electrically connect the at least one output driver leg308dto the remaining output driver legs308a-cby closing a transmission gate321,323when the at least one output driver leg308dis outputting a signal and the output of the at least one driver leg308dis not being monitored (when both pad_mon_en is disabled and drv_308d_en is enabled).

At410, the adjusted signal is level-shifted, the level-shifted signal is conditioned, and the conditioned, level-shifted signal is driven with the at least one output driver leg when an output of the at least one output driver leg is being monitored. For example, referring toFIG. 3, the level shifter304may level-shift the adjusted signal310, the pre-driver306may condition the level-shifted signal, and the output driver leg308dmay drive the conditioned, level-shifted signal when an output of the at least one output driver leg308dis being monitored by the duty cycle monitor314.

In one configuration, an apparatus is configured to adjust a data signal. The apparatus includes means for electrically isolating at least one output driver leg of an output driver from remaining output driver legs of the output driver. The means for electrically isolating is the isolation module320. The apparatus further includes means for monitoring an output of the at least one output driver leg when the at least one output driver leg is electrically isolated from the remaining output driver legs. The means for monitoring is the duty cycle monitor314. The apparatus further includes means for adjusting a duty cycle of a signal based on the monitoring. The means for adjusting a duty cycle is the duty cycle adjuster316. The apparatus may further include means for electrically connecting the at least one output driver leg of the output driver to the remaining output driver legs of the output driver after the means for monitoring perform the monitoring. The means for electrically connecting is the isolation module320. The means for electrically connecting may include a transmission gate control module configured to electrically connect the at least one output driver leg to the remaining output driver legs by closing a transmission gate when the at least one output driver leg is outputting a signal and the output of the at least one driver leg is not being monitored. The means for electrically isolating may include a transmission gate control module configured to be operated to open a transmission gate coupled between the output of the at least one output driver leg and outputs of the remaining output driver legs when the at least one output driver leg is outputting a signal and the output of the at least one driver leg is being monitored. The transmission gate control module may be configured to isolate the at least one output driver leg by opening the transmission gate further when the at least one output driver leg is not outputting a signal. The apparatus may further include means for level-shifting the adjusted signal. The apparatus may further include means for conditioning the level-shifted signal. The apparatus may further include means for driving the conditioned, level-shifted signal with the at least one output driver leg when an output of the at least one output driver leg is being monitored.

As described supra, a driver circuit includes an output driver, a duty cycle adjuster, an isolation module, and a duty cycle monitor. The duty cycle monitor monitors the output of a leg of an output driver when the leg of the output driver is electrically isolated from the remaining legs of the output driver by the isolation module. Information of the signal detected by the duty cycle monitor is delivered to a duty cycle adjuster, which adjusts a duty cycle of a signal received from a data module. Monitoring an output of the leg while the output is isolated from the output of the remaining legs improves the duty cycle adjustment.