Gallium nitride high electron mobility transistor having high breakdown voltage and formation method therefor

A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.

TECHNICAL FIELD

The present disclosure relates to the technical field of semiconductors, and in particular, relates to a gallium nitride high electron mobility transistor having a high breakdown voltage and a formation method therefor.

BACKGROUND

Gallium nitride (GaN) is greatly concerned because gallium nitride may accommodate such high performance requirements as high temperature, high frequency, high voltage, high power, anti-irradiation and the like in the modern electronics technology. A GaN-based high electron mobility transistor (HEMT), used as a power device, is a frontline hotspot technology which is in energetic development in the worldwide, and is also a core technique in the key power electronic technology that needs to be urgently developed in China energy development field.

Although the GaN-based HEMT has a high theoretic breakdown voltage, the GaN-based HEMT used as a power switch device has a high voltage resistance which is far less than a theoretically calculated breakdown voltage. This greatly restricts application of the GaN-based HEMT in the field of high voltage and high power field. Studies reveal that the GaN-based HEMT has a low breakdown voltage mainly because a gate electric field concentration effect and current leakage of a buffer layer, especially the gate electric field concentration effect. To be specific, in an off state, when a device suffers a high voltage between a source and a drain, the end of the gate proximal to the drain may generate an electric field peak which causes non-uniform electric field distribution. As a result, the device is broken down ahead of time.

At present, various metal layer field plate structures are fabricated in the source region, the gate region or the drain region to smoothen the surface electric field distribution to improve the breakdown voltage. This approach of the field plate structure may improve the breakdown voltage to some extents. However, due to lattice mismatch and thermal stress mismatch between the metal and gallium nitride, defects and interface charge traps may be additionally introduced. As a result, quality of the device is degraded, and reliability and stability of the device are adversely affected.

Therefore, finding a specific solution to improving the breakdown voltage of a GaN-based HEMT power device and sufficiently taking advantages of the high voltage and high power of the GaN-based electronic power device are significant.

SUMMARY

A technical problem to be solved by the present disclosure is to provide a gallium nitride high electron mobility transistor having a high breakdown voltage and a formation method therefor, to improve the breakdown voltage of the high electron mobility transistor.

In view of the above problem, the present disclosure provides a gallium nitride high electron mobility transistor having a high breakdown voltage. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas.

The present disclosure further provides a formation method for a gallium nitride high electron mobility transistor. The method includes: providing a substrate; forming a gallium channel layer and a first barrier layer disposed on the gallium channel layer in sequence on the substrate; forming a second barrier layer on a surface of the first barrier layer, the second barrier layer being configured to generate two-dimensional hole gas; etching the second barrier layer to expose a part of the surface of the first barrier layer; and forming a source, a drain and a gate on the surface of the first barrier layer respectively, the gate being positioned between the source and the second barrier layer, and a side wall on one side of the gate being connected to a side wall of the second barrier layer.

DETAILED DESCRIPTION

Specific embodiments illustrating a gallium nitride high electron mobility transistor having a high breakdown voltage and a formation method therefor according to the present disclosure are described hereinafter in detail with reference to the accompanying drawings.

Referring toFIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one or more embodiments of the present disclosure is given.

The formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage includes: step S101: providing a substrate; step S102: forming a gallium channel layer and a first barrier layer disposed on the gallium channel layer in sequence on the substrate; step S103: forming a second barrier layer on a surface of the first barrier layer, the second barrier layer being configured to generate two-dimensional hole gas; step S104: etching the second barrier layer to expose a part of the surface of the first barrier layer; and step S105: forming a source, a drain and a gate on the surface of the first barrier layer respectively, the gate being positioned between the source and the second barrier layer, and a side wall on one side of the gate being connected to a side wall of the second barrier layer.

Referring toFIG. 2toFIG. 6, schematic sectional structural diagrams of a formation process of the gallium nitride high electron mobility transistor having a high breakdown voltage according to one or more embodiments are given.

The substrate200may be made of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, gallium nitride, or the like.

Referring toFIG. 3, a channel layer303and a first barrier layer305disposed on a surface of the channel layer303are formed on the substrate200in sequence.

The channel layer303, as a transmission channel of two-dimensional electron gas, needs to have a higher crystal quality to reduce a background concentration in the channel, such that diffraction and mobility of the two-dimensional electron gas are reduced. The channel303may also be made of a non-doped group III metal nitride, for example, a non-doped GaN layer.

The first barrier layer305and the channel layer303form a heterojunction, wherein non-contiguous energy band levels, and piezo polarization and spontaneous polarization on an interface of the heterojunction may generate the two-dimensional electron gas having a high concentration. The first barrier layer305may be made of materials including aluminum gallium nitride and indium aluminum nitride, and may have a single layer or a multi-layer structure.

In one or more embodiments of the present disclosure, the process further includes: forming a nucleation layer301and a buffer layer302disposed on a surface of the nucleation layer301between the substrate200and the channel layer303.

The nucleation layer301is mainly intended to provide an effective nucleation center for growth of a subsequent epitaxial layer, and meanwhile release a mismatch stress between the nucleation layer and the substrate by virtue of formation of a large number of dislocations and defects. This may remarkably improve quality of a group III metal nitride layer epitaxially grown on the nucleation layer301. The nucleation layer301may be made of materials including GaN, AlN and AlGaN.

The buffer layer302has a higher resistivity to prevent electrons in the channel layer303from leaking to the buffer layer302. It is generally required that the buffer layer302has a resistivity over 106ohms cm. The buffer layer302may be made of gallium nitride, and deep level defects are generated in the buffer layer to form a high resistance by virtue of ion injection, or a high resistance is obtained by introduction of P-type impurity doping and compensation for an N-type background concentration. In other embodiments of the present disclosure, the buffer layer302having a high resistivity may also be obtained in other ways.

In one or more embodiments of the present disclosure, the process further includes: forming an insert layer304between the channel layer303and the first barrier layer305. The insert layer304is configured to improve crystal quality of the first barrier layer305, and the insert layer304may be made of aluminum nitride.

The nucleation layer301, the buffer layer302, the channel layer303, the insert layer304and the first barrier layer305may be formed by an atomic layer deposition process, a metal-organic chemical vapor deposition process, a molecular beam epitaxy process or a hydride vapor phase epitaxy process.

In other embodiments of the present disclosure, a part of the structures of the nucleation layer301, the buffer layer302or the insert layer304may be only formed.

Referring toFIG. 4, a second barrier layer400is formed on a surface of the first barrier layer305, wherein the second barrier layer400is configured to generate two-dimensional hole gas.

The second barrier layer400may be made of materials including group III metal nitrides for generating the two-dimensional hole gas, for example, P-doped group III metal nitride or a heterojunction capable of generating the two-dimensional hole gas.

In one or more embodiments of the present disclosure, the second barrier layer400includes: a first sub-layer401disposed on the surface of the first barrier layer305, a second sub-layer402disposed on a surface of the second sub-layer401and a third sub-layer403disposed on a surface of the second sub-layer402, wherein the first sub-layer401and the second sub-layer402form a heterojunction, and the third sub-layer403is P-doped.

In one or more embodiments of the present disclosure, the first sub-layer401is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer402is made of gallium nitride, aluminum nitride or aluminum gallium nitride; and the third sub-layer403is made of P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride. The first sub-layer401and the second sub-layer402form a heterojunction, and a ratio of the aluminum element and/or the gallium element in the first sub-layer401and the second sub-layer402is adjusted such that the two-dimensional hole gas is generated on the interface of the first sub-layer401and the second sub-layer402.

The first sub-layer401may have a thickness of 1 nm to 100 nm; the second sub-layer402may have a thickness of 1 nm to 100 nm; and the third sub-layer403may have a thickness of 1 nm to 100 nm.

In other specific embodiments of the present disclosure, other suitable materials may be used to form the second barrier layer400having a single-layer or a multi-layer structure, such that the second barrier layer400generates the two-dimensional hole gas under the condition of spontaneous polarization or external electrode polarization.

The second barrier layer400may also be formed by the atomic layer deposition process, the metal-organic chemical vapor deposition process, the molecular beam epitaxy process or the hydride vapor phase epitaxy process.

Referring toFIG. 5, the second barrier layer400is etched to expose a part of the surface of the first barrier layer305.

The second barrier layer400is pattern-like etched to reserve a partial second barrier layer400apositioned above the channel region between the gate and the drain of an HEMT to be formed. In one or more embodiments of the present disclosure, the second barrier layer400aincludes: a first sub-layer401adisposed on the surface of the first barrier layer305, a second sub-layer402adisposed on a surface of the first sub-layer401aand a third sub-layer403adisposed on a surface of the second sub-layer402a.

The second barrier layer400may be etched by a dry etch process. Further, the second barrier layer400may be etched by a low-damage dry etch process to prevent great damages to the second barrier layer400and avoid impacts to quality of the interface between the second barrier layer400and the subsequently formed gate. In one or more embodiments of the present disclosure, the second barrier layer400may also be etched by a reactive ion etch process or an inductively coupled plasma etch process, with an etching gas including Cl2and BCl3.

Referring toFIG. 6, a source601, a drain602and a gate603are formed on the surface of the first barrier layer305respectively, wherein the gate603is positioned between the source601and a second barrier layer600, and a side wall on one side of the gate603is connected to a side wall of the second barrier layer400.

A method for forming the source601, the drain602and the gate603includes: forming a metal layer covering the first barrier layer305and the second barrier layer400a, for example, Ti, Al, Cu, Au, Ag, or the like; and pattern-like etching the metal layer such that the source601, the drain602and the gate603disposed on the surface of the first barrier layer305are formed, and the gate603is positioned between the source601and the second barrier layer400aand a side wall of the gate603is connected to a side wall of the second barrier layer400a, to generate two-dimensional hole gas by polarizing the gate603and the second barrier layer400a.

By polarization, the second barrier layer400agenerates the two-dimensional hole gas, and improves the breakdown voltage of the high electron mobility transistor. In one or more embodiments of the present disclosure, by using impurity ionization of the P-doped third sub-layer403aand the two-dimensional hole gas generated by charge polarization on the interface between the second sub-layer402aand the first sub-layer401a, the second barrier layer400aexhausts two-dimensional electron gas in a channel in a drift region between the gate and the drain, smoothens electric field distribution of the channel, and thus improves the breakdown voltage of the high electron mobility transistor.

In an embodiment of the present disclosure, 8-inch silicon with orientation <111> is used as the substrate, and afterwards, the nucleation layer of aluminum nitride, the buffer layer of gallium nitride, the channel layer of gallium nitride, the insert layer of aluminum nitride, the barrier layer of aluminum gallium nitride, the first sub-layer of aluminum nitride, the second sub-layer of gallium nitride and the third sub-layer of P-type gallium nitride are epitaxially grown by metal-organic chemical vapor deposition (MOCVD). The MOCVD system is a planetary reaction chamber G5+ manufactured by Aixtron in Germany, which may accommodate five 8-inch silicon substrates. A growing temperature is 1100 to 1150° C., trimethylaluminum (TMAI) has a flow rate of 50 μmol/min to 180 μmol/min, and trimethylgallium (TMGa) has a flow rate of 80 μmol/min to 220 μmol/min. Ammonia is supplied by group V raw materials, which has a flow rate of 5 slm to 50 slm. Hydrogen and nitrogen are carrier gases, which have a flow rate of 10 slm to 80 slm. The first sub-layer of aluminum nitride has a thickness of 20 nm, the second sub-layer of gallium nitride has a thickness of 50 nm, and the third sub-layer of P-type gallium nitride has a thickness of 100 nm.

Afterwards, the first sub-layer of aluminum nitride, the second sub-layer of gallium nitride and the third sub-layer of P-type gallium nitride are etched by an inductively coupled plasma (ICP) process, but a part of the region between the gate and the drain is reserved. An etching gas used in the ICP process is boron trichloride (BCl3) and Cl2, wherein BCl3has a flow rate of 100 sccm, Cl2has a flow rate of 5 sccm, and an etching power is 50 W. Subsequently, the source, the gate and the drain are respectively fabricated. A composite layer of a Ti layer and an Al layer formed by virtue of electron beam deposition is used as an electrode metal, wherein the Ti layer has a thickness of 20 nm, the Al layer has a thickness of 200 nm, and annealing is carried out at an atmosphere of nitrogen at an annealing temperature of 850° C. and a duration of 30 s.

In another aspect, the present disclosure further provides a high electron mobility transistor having a breakdown voltage.

Referring toFIG. 6, the high electron mobility transistor includes: a substrate200; a channel layer303disposed on the substrate200; a first barrier layer305disposed on the channel layer303; and a gate603, a source601and a drain602disposed on the first barrier layer305, wherein the source601and the drain602are disposed on two sides of the gate603respectively; and a second barrier layer400adisposed on a surface of the first barrier layer305positioned between the gate603and the drain602, wherein a side wall of the second barrier layer400ais connected to a side wall on one side of the gate603and is configured to generate two-dimensional hole air.

The substrate200may be made of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, gallium nitride or the like.

The channel layer303, as a transmission channel of two-dimensional electron gas, needs to have a higher crystal quality to reduce a background concentration in the channel, such that diffraction and mobility of the two-dimensional electron gas are reduced. The channel303may also be made of a non-doped group III metal nitride, for example, a non-doped GaN layer.

The first barrier layer305may be made of materials including aluminum gallium nitride and indium aluminum nitride, and may have a single layer or a multi-layer structure. The first barrier layer305and the channel layer303form a heterojunction to generate two-dimensional electron gas.

In one or more embodiments of the present disclosure, the high electron mobility transistor further includes: a nucleation layer301positioned between the substrate200and the channel layer303, and a buffer layer302disposed on a surface of the nucleation layer301. The nucleation layer301may remarkably improve quality of a group III metal nitride layer epitaxially grown on the nucleation layer301. The nucleation layer301may be made of materials including GaN, AlN and AlGaN. The buffer layer302has a higher resistivity, and the buffer layer302may be made of gallium nitride.

In one or more embodiments of the present disclosure, the high electron mobility transistor further includes an insert layer304positioned between the channel layer303and the first barrier layer305, wherein the insert layer304is configured to improve crystal quality of the first barrier layer305, and the insert layer304may be made of aluminum nitride.

In other specific embodiments of the present disclosure, the high electron mobility transistor may also have a part of the structures of the nucleation layer301, the buffer layer302and the insert layer304.

The second barrier layer400amay be made of materials including group III metal nitrides for generating the two-dimensional hole gas, for example, P-doped group III metal nitride or a heterojunction capable of generating the two-dimensional hole gas. In one or more embodiments of the present disclosure, the second barrier layer400aincludes: a first sub-layer401adisposed on the surface of the first barrier layer305, a second sub-layer402adisposed on a surface of the second sub-layer401aand a third sub-layer403adisposed on a surface of the second sub-layer402a, wherein the first sub-layer401aand the second sub-layer402aform a heterojunction, and the third sub-layer403ais P-doped. In one or more embodiments of the present disclosure, the first sub-layer401ais made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer402ais made of gallium nitride, aluminum nitride or aluminum gallium nitride; and the third sub-layer403ais made of P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride. The first sub-layer401aand the second sub-layer402aform a heterojunction, and a ratio of the aluminum element and/or the gallium element in the first sub-layer401aand the second sub-layer402ais adjusted such that the two-dimensional hole gas is generated on the interface of the first sub-layer401aand the second sub-layer402a.

The first sub-layer401amay have a thickness of 1 nm to 100 nm; the second sub-layer402amay have a thickness of 1 nm to 100 nm; and the third sub-layer403amay have a thickness of 1 nm to 100 nm. In other specific embodiments of the present disclosure, other suitable materials may be used to form the second barrier layer400ahaving a single-layer or a multi-layer structure, such that the second barrier layer400agenerates the two-dimensional hole gas under the condition of spontaneous polarization or external electrode polarization.

The source601, the drain602and the gate603are all a metal, for example, Ti, Al, Cu, Au, Ag or the like. The gate603is positioned between the source601and the second barrier layer600, and a side wall on a side of the gate603is connected to a side wall of the second barrier layer400, such that the two-dimensional hole gas is generated by polarizing the gate603and the second barrier layer400a.

The second barrier layer400ais capable of generating the two-dimensional hole gas, and thus improving the breakdown voltage for the high electron mobility transistor. In one or more embodiments of the present disclosure, by using impurity ionization of the P-doped third sub-layer403aand the two-dimensional hole gas generated by charge polarization on the interface between the second sub-layer402aand the first sub-layer401a, the second barrier layer400aexhausts two-dimensional electron gas in a channel in a drift region between the gate and the drain, smoothens electric field distribution of the channel, and thus improves the breakdown voltage of the high electron mobility transistor.

Optionally, the second barrier layer includes: a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sub-layer disposed on a surface of the second sub-layer, wherein the first sub-layer and the second sub-layer form a heterojunction, and the third sub-layer is P-doped.

Optionally, a nucleation layer and a buffer layer disposed on the nucleation layer are defined between the substrate and the gallium channel layer.

Optionally, an insert layer is further defined between the gallium channel layer and the first barrier layer.

Optionally, the first sub-layer is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer is made of gallium nitride, aluminum nitride or aluminum gallium nitride; the third sub-layer is made from P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride; the nucleation layer is made of a gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer layer is made of gallium nitride; the insert layer is made of aluminum nitride; and the first barrier layer is made of aluminum gallium nitride or indium aluminum nitride.

Optionally, the second barrier layer includes: a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sub-layer disposed on a surface of the second sub-layer, wherein the first sub-layer and the second sub-layer form a heterojunction, and the third sub-layer is P-doped.

Optionally, the second barrier layer is etched by a reactive ion etch process or an inductively coupled plasma etch process.

Optionally, the method further includes: forming a nucleation layer and a buffer layer disposed on a surface of the nucleation layer between the substrate and the gallium nitride channel layer; and forming an insert layer between the gallium nitride channel layer and the first barrier layer.

Optionally, the first sub-layer is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer is made of gallium nitride, aluminum nitride or aluminum gallium nitride; the third sub-layer is made from P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride; the nucleation layer is made of a gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer layer is made of gallium nitride; the insert layer is made of aluminum nitride; and the first barrier layer is made of aluminum gallium nitride or indium aluminum nitride.

In the high electron mobility transistor according to the present disclosure, a second barrier layer is defined between a gate and a drain, wherein the second barrier layer is capable of generating two-dimensional hole gas to exhaust two-dimensional electron gas in a channel in a drift region between the gate and the drain, smoothen electric field distribution of the channel, and thus improve the breakdown voltage of the high electron mobility transistor.

Described above are preferred examples of the present disclosure. It should be noted that persons of ordinary skill in the art may derive other improvements or polishments without departing from the principles of the present disclosure. Such improvements and polishments shall be deemed as falling within the protection scope of the present disclosure.