DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

A display apparatus includes: an overcoat layer; a first color filter layer, a second color filter layer, and a third color filter layer arranged on the overcoat layer; a first planarization layer arranged on the first color filter layer, the second color filter layer, and the third color filter layer; a second planarization layer arranged on the first planarization layer and defining a first through-hole, a second through-hole, and a third through-hole therein; a first quantum dot layer in the first through-hole; and a second quantum dot layer in the second through-hole.

This application claims priority to Korean Patent Application No. 10-2021-0111872, filed on Aug. 24, 2021, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

BACKGROUND

One or more embodiments relate to a display apparatus and a method of manufacturing the same.

2. Description of the Related Art

A display apparatus may include a plurality of pixels. For a full-color display apparatus, each of the plurality of pixels may emit light of a different color. To this end, at least some pixels of the display apparatus may include a color conversion unit. Accordingly, the light generated by a light-emitting unit of some pixels may be converted into light of a different color while passing through the color conversion unit to be extracted to the outside.

SUMMARY

However, in the conventional display apparatus, misalignment may occur in a process of bonding a light-emitting unit on which a transistor and a light-emitting element are arranged and a color conversion unit on which a color conversion material is arranged, thereby reducing light efficiency.

One or more embodiments include a display apparatus capable of preventing or minimizing misalignment caused in a process of bonding a light-emitting unit and a color conversion unit to each other, and at the same time improving light efficiency of the display apparatus by forming a color filter layer and a quantum dot layer on a substrate on which a transistor is arranged, and a method of manufacturing the display apparatus.

According to one or more embodiments, a display apparatus includes: an overcoat layer; a first color filter layer, a second color filter layer, and a third color filter layer arranged on the overcoat layer; a first planarization layer arranged on the first color filter layer, the second color filter layer, and the third color filter layer; a second planarization layer arranged on the first planarization layer and defining a first through-hole, a second through-hole, and a third through-hole, a first quantum dot layer in the first through-hole therein; and a second quantum dot layer in the second through-hole.

In the present embodiment, the display apparatus may further include a light-transmitting layer located in the third through-hole.

In the present embodiment, the first quantum dot layer may at least partially overlap the first color filter layer, the second quantum dot layer may at least partially overlap the second color filter layer, and the light-transmitting layer may at least partially overlap the third color filter layer in a plan view.

In the present embodiment, the display apparatus may further include a light-emitting device arranged on the second planarization layer and including a light-emitting layer.

In the present embodiment, the light-emitting device may further include a pixel electrode and an opposite electrode corresponding to the pixel electrode, and the light-emitting layer may be arranged on the pixel electrode to be interposed between the pixel electrode and the opposite electrode.

In the present embodiment, the pixel electrode may be directly arranged on the first quantum dot layer.

In the present embodiment, the display apparatus may further include a protective layer arranged between the pixel electrode and the first quantum dot layer.

In the present embodiment, the first quantum dot layer may be interposed between the first color filter layer and the light-emitting device.

In the present embodiment, the display apparatus may further include a transistor interposed between the first color filter layer and the first quantum dot layer.

In the present embodiment, the transistor may not overlap the first color filter layer in the plan view.

In the present embodiment, the display apparatus may further include a connection electrode arranged on the transistor, and the connection electrode may electrically connect the transistor to the light-emitting device.

In the present embodiment, the display apparatus may further include a light-shielding electrode arranged on the transistor.

In the present embodiment, the second planarization layer may have a maximum thickness of about 10 micrometers (μm) to about 15 μm.

In the present embodiment, the first planarization layer may have a maximum thickness of about 8 μm to about 13 μm.

In the present embodiment, a bottom surface of each of the first through-hole, the second through-hole, and the third through-hole may be convex in a direction approaching the overcoat layer.

According to one or more embodiments, a method of manufacturing a display apparatus includes: forming a transistor on a first carrier substrate; forming a first color filter layer, a second color filter layer, and a third color filter layer on the transistor; forming a second carrier substrate on the first color filter layer, the second color filter layer, and the third color filter layer, and then inverting the first carrier substrate; removing the first carrier substrate; forming a first quantum dot layer, a second quantum dot layer, and a light-transmitting layer on the transistor; and forming a light-emitting device on the first quantum dot layer, the second quantum dot layer, and the light-transmitting layer.

In the present embodiment, the method may further include, before forming the transistor on the first carrier substrate, forming a first planarization layer on the first carrier substrate, and forming a connection electrode on the first planarization layer.

In the present embodiment, the connection electrode may electrically connect the transistor to the light-emitting device.

In the present embodiment, the forming of the transistor on the first carrier substrate may include: forming a semiconductor layer on the first carrier substrate; forming a gate insulating layer on the semiconductor layer; and forming a gate electrode on the gate insulating layer.

In the present embodiment, the method may further include, after forming the first color filter layer, the second color filter layer, and the third color filter layer, forming an overcoat layer on the first color filter layer, the second color filter layer, and the third color filter layer.

In the present embodiment, the overcoat layer may have a thickness of about 50 μm to about 70 μm.

In the present embodiment, the method may further include, after removing the first carrier substrate, forming a second planarization layer defining a first through-hole, a second through-hole, and a third through-hole therein, on the first planarization layer.

In the present embodiment, the second planarization layer may have a maximum thickness of about 10 μm to about 15 μm.

In the present embodiment, the first quantum dot layer may be formed in the first through-hole, the second quantum dot layer may be formed in the second through-hole, and the light-transmitting layer may be formed in the third through-hole.

In the present embodiment, the first planarization layer may have a maximum thickness of about 8 μm to about 13 μm.

In the present embodiment, the first quantum dot layer may at least partially overlap the first color filter layer, the second quantum dot layer may at least partially overlap the second color filter layer, and the light-transmitting layer may at least partially overlap the third color filter layer in a plan view.

In the present embodiment, the light-emitting device may include a pixel electrode, an opposite electrode arranged to face the pixel electrode, and a light-emitting layer between the pixel electrode and the opposite electrode.

In the present embodiment, in the light-emitting device, the pixel electrode may be directly formed on the first quantum dot layer.

In the present embodiment, the first quantum dot layer may be interposed between the first color filter layer and the light-emitting device.

In the present embodiment, the method may further include, after forming the light-emitting device, forming an encapsulation member on the light-emitting device, and removing the second carrier substrate.

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

Since the disclosure may have diverse modified embodiments, certain embodiments are illustrated in the drawings and are described in the detailed description. Advantages and features of the disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms.

It will be understood that when a layer, region, or element is referred to as being “formed/disposed on” another layer, area, or element, it can be directly or indirectly formed/disposed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of description, the following embodiments are not limited thereto.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. In the specification, the term “A and/or B” refers to the case of A or B, or A and B. In the specification, the term “at least one of A and B” refers to the case of A or B, or A and B.

In the following embodiments, the term “extension of a conductive line in a first direction or a second direction” means not only linear extension but also zigzag or curved extension in the first direction or the second direction.

In the following embodiments, the term “in a plan view” means that an object is viewed from above (i.e., from a Z direction. Here, the Z direction corresponds to a thickness direction of a display apparatus), and the term “in a cross-sectional view” means that a vertical section of an object is viewed from the side. In the following embodiments, “overlap” includes overlap “planar” overlap and “cross-sectional” overlap.

FIG.1is a plan view of a portion of a display apparatus1according to an embodiment.

Referring toFIG.1, the display apparatus1may include a display area DA and a peripheral area PA around the display area DA. The peripheral area PA may be a kind of non-display area in which light-emitting devices are not arranged. In an embodiment, the peripheral area PA may at least partially surround the display area DA.

In an embodiment, the display area DA may have a rectangular shape as shown inFIG.1. In an embodiment, the display area DA may be provided in various shapes such as a polygonal shape such as a triangle, a pentagon, or a hexagon, or an irregular shape such as a round shape, an oval shape, or an irregular shape.

The display apparatus1may include a plurality of pixels P arranged in the display area DA. The pixels P may be arranged in various forms, such as a stripe arrangement and a pentile arrangement, to implement an image.

In the peripheral area PA of the display apparatus1, various wires for transmitting an electrical signal to be applied to the display area DA, and pad units PAD to which a printed circuit board or a driver IC chip is attached may be located.

FIG.2is a cross-sectional view schematically illustrating a portion of the display apparatus1according to an embodiment. As shown inFIG.2, the display apparatus1according to an embodiment may include a first pixel P1, a second pixel P2, and a third pixel P3. However, this is only an example, and the display apparatus1may include more pixels than the three pixels. In addition, although the first pixel P1 to the third pixel P3 are illustrated as being adjacent to each other inFIG.2, the disclosure is not limited thereto. That is, components such as other wires may be interposed between the first pixel P1 to the third pixel P3. Accordingly, the first pixel P1 to the third pixel P3 may not be pixels located adjacent to each other.

In an embodiment, the display apparatus1may include an overcoat layer100. In an embodiment, the overcoat layer100may include glass, metal, or polymer resin. In another embodiment, the overcoat layer100may include, for example, a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate such that the overcoat layer100is flexible or bendable. In another embodiment, the overcoat layer100may have a multi-layer structure including two layers each containing such a polymer resin and a barrier layer containing an inorganic material interposed between the two layers, and various modifications for the structure of the overcoat layer100are possible.

In an embodiment, the overcoat layer100may have a thickness of 50 micrometers (μm) to 70 μm (e.g., a second thickness t2). if the thickness of the overcoat layer100is less than 50 μm, as will be described later below, in a process of removing a second carrier substrate70(ofFIG.23) formed on the overcoat layer100, curling may occur in the overcoat layer100. On the other hand, if the thickness of the overcoat layer100exceeds 70 μm, the flexibility of the overcoat layer100may be reduced, and thus, flexible or bendable characteristics of the display apparatus including the overcoat layer100may be deteriorated. Accordingly, when the overcoat layer100is provided with a thickness of 50 μm to 70 μm, it is possible to effectively prevent or minimize the occurrence of curling in the overcoat layer100, and to secure the flexibility of the overcoat layer100, thereby improving the flexible or bendable characteristics of the display apparatus including the overcoat layer100.

A second insulating layer101may be arranged on the overcoat layer100. The second insulating layer101may be formed as a single layer or multiple layers constituting a film including an organic material or an inorganic material. In an embodiment, the second insulating layer101may include a general polymer such as benzocyclobutene (“BCB”), polyimide (“PI”), hexamethyldisiloxane (“HMDSO”), polymethylmethacrylate (“PMMA”), and polystyrene (“PS”), a polymer derivative including a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, or a blend thereof. In an embodiment, the second insulating layer101may include SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO.

A first insulating layer103may be on the second insulating layer101. In an embodiment, the first insulating layer103may include the same material as the material of the second insulating layer101. In another embodiment, the first insulating layer103may include a material different from the material of the second insulating layer101.

A first color filter layer411, a second color filter layer421, and a third color filter layer431may be interposed between the second insulating layer101and the first insulating layer103. In an embodiment, the first color filter layer411may pass only light having a wavelength in the range of 630 nanometers (nm) to 780 nm, the second color filter layer421may pass only light having a wavelength in the range of 495 nm to 570 nm, and the third color filter layer431may pass only light having a wavelength in the range of 450 nm to 495 nm. However, the disclosure is not limited thereto.

In an embodiment, the first color filter layer411to the third color filter layer431may reduce reflection of external light in the display apparatus1.

In an embodiment, a transistor TFT may be on the first insulating layer103. In an embodiment, the transistor TFT may include a gate electrode131, a source electrode133, a drain electrode135, and a semiconductor layer137.

In an embodiment, the gate electrode131, the source electrode133, and the drain electrode135may be arranged on the first insulating layer103. In an embodiment, the gate electrode131, the source electrode133, and the drain electrode135may be formed in the same layer. However, the disclosure is not limited thereto. For example, the gate electrode131and the source electrode133may be arranged in different layers from each other, and the source electrode133and the drain electrode135may be arranged in the same layer.

In an embodiment, the gate electrode131, the source electrode133, and the drain electrode135may be a single layer or multiple layers of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu.

A gate insulating layer105may be arranged on the gate electrode131, the source electrode133, and the drain electrode135. In an embodiment, the gate insulating layer105may include at least one inorganic insulating material selected from the group containing SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. In an embodiment, the gate insulating layer105may be provided as a single layer or multiple layers including the above-described inorganic insulating material.

The semiconductor layer137may be arranged on the gate insulating layer105. In an embodiment, the semiconductor layer137may include a channel area overlapping the gate electrode131, and a source area and a drain area arranged on opposite sides of the channel area and including impurities having a higher concentration than impurity of the channel area. The source area and the drain area may be electrically connected to the source electrode133and the drain electrode135through contact holes105aand105cdefined in the gate insulating layer105, respectively.

The semiconductor layer137may include an oxide semiconductor and/or a silicon semiconductor. In an embodiment, when the semiconductor layer137is formed of an oxide semiconductor, the semiconductor layer137may include an oxide of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), Ti, and zinc (Zn). For example, the semiconductor layer137may be made of ITZO (InSnZnO), IGZO (InGaZnO), or the like. In an embodiment, when the semiconductor layer137is formed of a silicon semiconductor, the semiconductor layer137may include amorphous silicon (a-Si) or low temperature poly-silicon (“LTPS”) crystallized from amorphous silicon (a-Si).

A buffer layer107may be arranged on the semiconductor layer137. The buffer layer107may include at least one inorganic insulating material selected from the group containing SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. In an embodiment, the buffer layer107may be provided as a single layer or multiple layers including the above-described inorganic insulating material.

A connection electrode141and a light-shielding electrode143may be arranged on the buffer layer107. In an embodiment, the connection electrode141and the light-shielding electrode143may be arranged in the same layer. However, the disclosure is not limited thereto. For example, the connection electrode141and the light-shielding electrode143may be arranged in different layers from each other.

In an embodiment, the connection electrode141and the light-shielding electrode143each may be a single layer or multiple layers of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. Alternatively, the connection electrode141and the light-shielding electrode143each may include at least one of indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”).

In an embodiment, as will be described later inFIG.6, the connection electrode141may include a second conductive layer141b(ofFIG.6) and a first conductive layer141a(ofFIG.6) sequentially stacked on the buffer layer107. In this case, the second conductive layer141bmay include a metal having good conductivity, and the first conductive layer141amay include a metal having good strength, rigidity, and corrosion resistance. For example, the second conductive layer141bmay be made of Cu, and the first conductive layer141amay be made of Ti or ITO.

A first planarization layer109may be arranged on the connection electrode141and the light-shielding electrode143. In an embodiment, the first planarization layer109may be formed of or include a polymer resin. For example, the first planarization layer109may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

In an embodiment, the first planarization layer109may have a maximum thickness of 3 μm to 4 μm (e.g., a first thickness t1). If the thickness of the first planarization layer109is less than 3 μm, the flatness of the first planarization layer109may be reduced. On the other hand, if the thickness of the first planarization layer109is greater than 4 μm, it may be difficult to form a contact hole through which the connection electrode141is electrically connected to a pixel electrode to be described later below. For example, as the thickness of the first planarization layer109increases, the area of the contact hole through which the connection electrode141is electrically connected to the pixel electrode increases, which may make it difficult to realize high resolution.

Accordingly, because the first planarization layer109is provided with a maximum thickness of 3 μm to 4 μm, the flatness of the first planarization layer109may be secured, and a contact hole may be easily formed in the first planarization layer109.

In an embodiment, the first planarization layer109may define contact holes109a,109b, and109ctherein. In an embodiment, the connection electrode141may be electrically connected to a pixel electrode to be described later below through the contact hole109a. In addition, the connection electrode141may be arranged in the contact hole109bdefined in the first planarization layer109, and the light-shielding electrode143may be arranged in the contact hole109cdefined in the first planarization layer109.

In an embodiment, the source electrode133may be electrically connected to the light-shielding electrode143through a contact hole105bdefined in the gate insulating layer105and the buffer layer107. In an embodiment, the drain electrode135may be electrically connected to the connection electrode141through a contact hole105ddefined in the gate insulating layer105and the buffer layer107.

In an embodiment, the contact holes105band105ddefined in the gate insulating layer105and the buffer layer107and the contact holes109band109cdefined in the first planarization layer109may surround at least a portion of each of the pixels P1, P2 and P3.

In an embodiment, metals may be arranged in the contact holes105band105ddefined in the gate insulating layer105and the buffer layer107and the contact holes109band109cdefined in the first planarization layer109. In more detail, the source electrode133and/or a drain electrode135may be arranged in the contact holes105band105ddefined in the gate insulating layer105and the buffer layer107, and the connection electrode141and/or the light-shielding electrode143may be arranged in the contact holes109band109cdefined in the first planarization layer109.

In an embodiment, by disposing metals in the contact holes105band105ddefined in the gate insulating layer105and the buffer layer107and the contact holes109band109cdefined in the first planarization layer109, it is possible to effectively prevent or minimize color mixing of lights emitted from light-emitting devices to be described later below. For example, by disposing metals in the contact holes105band105ddefined in the gate insulating layer105and the buffer layer107and the contact holes109band109cdefined in the first planarization layer109, it is possible to effectively prevent lights emitted from adjacent light-emitting devices200and respectively passing through a first quantum dot layer413, a second quantum dot layer423, and a light-transmitting layer433from mixing with each other.

In addition, in an embodiment, the source electrode133and the drain electrode135are electrically connected to the light-shielding electrode143and the connection electrode141through the contact holes105cand105d, respectively, defined in the gate insulating layer105and the buffer layer107, so that the transistor TFT may be stabilized. However, the disclosure is not limited thereto.

A second planarization layer400may be arranged directly on the first planarization layer109. In an embodiment, the second planarization layer400may be formed of or include a polymer resin. For example, the second planarization layer400may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

In an embodiment, the second planarization layer400may define a first through-hole410to a third through-hole430therein corresponding to the first color filter layers411to431, respectively. For example, the first through-hole410may at least partially overlap the first color filter layer411in the plan view, the second through-hole420may at least partially overlap the second color filter layer421in the plan view, and the third through-hole430may at least partially overlap the third color filter layer431in the plan view.

In an embodiment, the first quantum dot layer413may be located in the first through-hole410, the second quantum dot layer423may be positioned in the second through-hole420, and the light-transmitting layer433may be positioned in the third through-hole430.

In an embodiment, the first quantum dot layer413may at least partially overlap the first color filter layer411, the second quantum dot layer423may at least partially overlap the second color filter layer421, and the light-transmitting layer433may at least partially overlap the third color filter layer431.

In an embodiment, the second planarization layer400may be provided with a maximum thickness of 10 μm to 15 μm (e.g., a third thickness t3) from an upper surface (or one side) of the first planarization layer109. If a maximum thickness of the second planarization layer400is less than 10 μm, the amount of the quantum dot layers413and423arranged in the through-holes410,420, and430provided in the second planarization layer400decreases, so that the luminous efficiency may be reduced, or when the area is increased to secure the amount of the quantum dot layers413and423arranged in the through-holes410,420, and430, it may be difficult to realize high resolution. On the other hand, if the thickness of the second planarization layer400is greater than 15 μm, it may be difficult to form a contact hole through which the connection electrode141is electrically connected to a pixel electrode210to be described later below. For example, as the thickness of the second planarization layer400increases, the area of the contact hole through which the connection electrode141is electrically connected to the pixel electrode210, and thus it may be difficult to realize high resolution. In addition, if the thickness of the second planarization layer400is greater than 15 μm, the amount of material for forming the quantum dot layers413and423arranged in the through-holes410,420, and430provided in the second planarization layer400may increase. Accordingly, because the second planarization layer400is provided with a maximum thickness of 10 μm to 15 μm, luminous efficiency may be effectively improved, a high-resolution display apparatus may be realized, and the amount of material forming the quantum dot layers413and423may be reduced.

In an embodiment, the first quantum dot layer413may be provided with a maximum thickness of 8 μm to 13 μm (e.g., a fourth thickness t4) from the upper surface (or one side) of the first planarization layer109. If a maximum thickness of the first quantum dot layer413is less than 8 μm, luminous efficiency may be reduced. On the other hand, if the thickness of the first quantum dot layer413exceeds 13 μm, there is a case where the first quantum dot layer413is formed outside the first through-hole410defined in the second planarization layer400, so that luminous efficiency may be reduced. Accordingly, because the first quantum dot layer413has a maximum thickness of 8 μm to 13 μm, the luminous efficiency of the display apparatus may be improved.

In addition, each of the second quantum dot layer423and the light-transmitting layer433may also be provided with a maximum thickness of 8 μm to 13 μm (e.g., the fourth thickness t4) from the upper surface (or one side) of the first planarization layer109.

In an embodiment, the light-emitting device200may be disposed on the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433. In an embodiment, the light-emitting device200may include the pixel electrode210, an intermediate layer220, and an opposite electrode230sequentially stacked. In an embodiment, the pixel electrode210may be patterned to correspond to each of the pixels P1, P2, and P3, and the intermediate layer220and the opposite electrode230may be integrally provided.

In an embodiment, the light-emitting device200may be an organic light-emitting diode (“OLED”) or an inorganic light-emitting diode (“ILED”), and various modifications are possible.

The pixel electrode210may be arranged on the second planarization layer400. As described above, the pixel electrode210may be patterned to correspond to each of the pixels P1, P2, and P3. In an embodiment, the pixel electrode210may be directly arranged on the first quantum dot layer413, the pixel electrode210may be directly arranged on the second quantum dot layer423, and the pixel electrode210may be arranged directly on the light-transmitting layer433.

In an embodiment, in the pixel electrode210, a transparent or semi-transparent electrode layer may include at least one selected from the group consisting of ITO, IZO, ZnO, In2O3, IGO, or AZO.

In an embodiment, the pixel electrode210may be electrically connected to the transistor TFT through a contact hole400adefined in the second planarization layer400. In more detail, the pixel electrode210and the connection electrode141are electrically connected to each other through the contact hole400adefined in the second planarization layer400and the contact hole109adefined in the first planarization layer109, and the source electrode133and/or the drain electrode135of the transistor TFT are electrically connected to each other through the contact hole105ddefined in the gate insulating layer105and the buffer layer107, so that the pixel electrode210may be electrically connected to the transistor TFT.

The intermediate layer220including a light-emitting layer may be arranged on the pixel electrode210. In an embodiment, the intermediate layer220including the light-emitting layer may be integrally provided on the pixel electrode210patterned to correspond to each of the pixels P1, P2, and P3. However, the disclosure is not limited thereto.

FIG.3is a cross-sectional view of a light-emitting device200that may be employed in a display apparatus according to an embodiment.

Referring toFIG.3, the pixel electrode210of the light-emitting device200may be patterned for each of the first pixels P1 to the third pixels P3. In an embodiment, the intermediate layer220and the opposite electrode230of the light-emitting device200may be integrally provided. However, the disclosure is not limited thereto.

The light-emitting device200may include the intermediate layer220, and the intermediate layer220may include a light-emitting layer EML and a hole transport layer HTL. In addition, the intermediate layer220may further include a hole injection layer HIL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL may be arranged between the pixel electrode210and the hole transport layer HTL. The electron transport layer ETL may be arranged on the light-emitting layer EML to transport electrons from the opposite electrode230to the light-emitting layer EML. The electron injection layer EIL may be arranged between the electron transport layer ETL and the opposite electrode230.

In an embodiment, the light-emitting layer EML may include an organic light-emitting material such as a high molecular weight organic material or a low molecular weight organic material that emits light of a certain color. For example, the light-emitting layer EML may be formed of or include an organic material emitting blue light. However, the disclosure is not limited thereto. In an embodiment, the light-emitting layer EML may be formed of or include an organic material emitting red or green light, or may be formed of or include an inorganic light-emitting material or quantum dots.

FIG.4is a cross-sectional view of the light-emitting device200that may be employed in a display apparatus according to another embodiment. InFIG.4, the same reference numerals inFIG.3denote the same elements, and a duplicate description will be omitted for simplicity.

Referring toFIG.4, the intermediate layer220of the light-emitting device may be provided by stacking a plurality of light-emitting layers.

In an embodiment, the intermediate layer220may include a first light-emitting layer EMLa and a second light-emitting layer EMLb. The first light-emitting layer EMLa and the second light-emitting layer EMLb may be formed of or include the same material. For example, the first light-emitting layer EMLa and the second light-emitting layer EMLb may be formed of or include an organic material emitting blue light. However, the disclosure is not limited thereto. The first light-emitting layer EMLa and the second light-emitting layer EMLb may be formed of or include an organic material emitting red or green light, or may be formed of or include an inorganic light-emitting material or quantum dots.

In an embodiment, the intermediate layer220may include a first stack220aincluding the first light-emitting layer EMLa, a second stack220cincluding the second light-emitting layer EMLb, and a charge generation layer220bbetween the first stack220aand the second stack220c.

In an embodiment, the first stack220amay have a structure in which the hole injection layer HIL, a first hole transport layer HTLa, the first light-emitting layer EMLa, and a first electron transport layer ETLa are sequentially stacked. In an embodiment, the second stack220cmay have a structure in which a second hole transport layer HTLb, a second light-emitting layer EMLb, a second electron transport layer ETLb, and the electron injection layer EIL are sequentially stacked.

In an embodiment, the charge generation layer220bmay supply charges to the first stack220aand the second stack220c. In an embodiment, the charge generation layer220bmay include an n-type charge generation layer n-CGL for supplying charges to the first stack220a, and a p-type charge generation layer p-CGL for supplying holes to the second stack220c. In this case, the n-type charge generation layer n-CGL may be provided by including a metal material as a dopant.

FIG.4shows that the intermediate layer220of a light-emitting device is provided by stacking two light-emitting layers, but the disclosure is not limited thereto. Three, four, or more light-emitting layers may be stacked.

Referring back toFIG.2, the intermediate layer220may include at least one light-emitting layer, and the light-emitting layer may emit light of a first wavelength band. For example, the light-emitting layer may emit light having a wavelength in the range of 450 nm to 495 nm. However, the disclosure is not limited thereto.

In an embodiment, the opposite electrode230may be arranged on the intermediate layer220. In an embodiment, the opposite electrode230may be integrally formed in light-emitting devices. In an embodiment, the opposite electrode230may be a reflective electrode. For example, the opposite electrode230may include a reflective film formed of or include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, or a compound thereof.

In an embodiment, the opposite electrode230may have a maximum thickness of 1000 angstroms (Å) or more (e.g., a fifth thickness t5). If the thickness of the opposing electrode230is less than 1000 angstroms (Å), the resistance of the opposing electrode230may increase, thereby reducing light-emitting efficiency.

In an embodiment, because the pixel electrode210arranged under the intermediate layer220including a light-emitting layer is formed as a transparent or translucent electrode, and the opposite electrode230arranged on the intermediate layer220is formed as a reflective electrode, the display apparatus1may be a bottom emission type in which light emitted from the light-emitting layer of the light-emitting device200is emitted toward the overcoat layer100.

An encapsulation member500may be on the light-emitting device200. In more detail, the encapsulation member500may be on the opposite electrode230of the light-emitting device200. In an embodiment, the encapsulation member500may be made of metal. For example, the encapsulation member500may be formed of or include an iron (Fe)-nickel (Ni) alloy. In an embodiment, the encapsulation member500may be attached on the opposite electrode230. Because the encapsulation member500on the light-emitting device200is made of metal, light emitted from the light-emitting device200may be partially reflected toward the overcoat layer100by the encapsulation member500.

In an embodiment, the encapsulation member500may have a thickness of 50 μm to 150 μm (e.g., a sixth thickness t6). In more detail, the encapsulation member500may be provided with a thickness of 50 μm to 150 μm (e.g., the sixth thickness t6) from an upper surface (or one side) of the opposite electrode230. If the encapsulation member500is provided with a thickness of less than 50 μm, sealing characteristics of the encapsulation member500may be deteriorated and the light-emitting device200may be contaminated by external foreign matter. On the other hand, if the encapsulation member500is provided with a thickness of more than 150 μm, flexible or bendable characteristics of the display apparatus1may be deteriorated. Accordingly, because the encapsulation member500is provided with a thickness of 50 μm to 150 μm (e.g., the sixth thickness t6), it is possible to effectively prevent or minimize contamination of the light-emitting device200from external foreign matter, and at the same time to implement a flexible or bendable display apparatus.

In an embodiment, because the display apparatus1has a bottom emission type structure, it is not necessary to form a thin film encapsulation layer TFE on the light-emitting device200. Accordingly, because a process of forming the thin film encapsulation layer TFE on the light-emitting device200may be omitted, the process may be simplified compared to the conventional one.

In an embodiment, the first quantum dot layer413may be interposed between the light-emitting device200and the first color filter layer411, the second quantum dot layer423may be interposed between the light-emitting device200and the second color filter layer421, and the light-transmitting layer433may be interposed between the light-emitting device200and the third color filter layer431.

The first quantum dot layer413may convert light of the first wavelength band generated by the intermediate layer220including the light-emitting layer into light of a second wavelength band. For example, when light having a wavelength in the range of 450 nm to 495 nm is generated in the intermediate layer220including the light-emitting layer, the first quantum dot layer413may convert the light into light having a wavelength in the range of 630 nm to 780 nm. Accordingly, in the first pixel P1, the light having a wavelength in the range of 630 nm to 780 nm may be emitted to the outside through the overcoat layer100. For example, red light may be emitted from the first pixel P1.

The second quantum dot layer423may convert light of the first wavelength band generated by the intermediate layer220including the light-emitting layer into light of a third wavelength band. For example, when light having a wavelength in the range of 450 nm to 495 nm is generated in the intermediate layer220including the light-emitting layer, the second quantum dot layer423may convert the light into light having a wavelength in the range of 495 nm to 570 nm. Accordingly, in the second pixel P2, the light having a wavelength in the range of 495 nm to 570 nm may be emitted to the outside through the overcoat layer100. For example, green light may be emitted from the second pixel P2.

Each of the first quantum dot layer413and the second quantum dot layer423may be provided in a form in which quantum dots are dispersed in a resin. A quantum dot includes semiconductor materials such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or indium phosphide (InP). The size of the quantum dot may be several nanometers, and a wavelength of light after conversion varies according to the size of the quantum dot. The resin included in the first quantum dot layer413and the second quantum dot layer423may be any light-transmitting material. For example, a polymer resin such as acryl, BCB, or HMDSO may be used as a material for forming the first quantum dot layer413and the second quantum dot layer423.

The third pixel P3 may emit light of the first wavelength band generated by the intermediate layer220including the light-emitting layer to the outside without wavelength conversion. Accordingly, the third pixel P3 may not have a quantum dot layer. As such, because a quantum dot layer is not required in the third through-hole430, the light-transmitting layer433formed of or include a transmissive resin is positioned in the third through-hole430. However, the disclosure is not limited thereto.

In an embodiment, the first color filter layer411, the second color filter layer421, and the third color filter layer431may be arranged on the overcoat layer100. The first color filter layer411may pass only light having a wavelength in the range of 630 nm to 780 nm, the second color filter layer421may pass only light having a wavelength in the range of 495 nm to 570 nm, and the third color filter layer431may pass only light having a wavelength in the range of 450 nm to 495 nm. However, the disclosure is not limited thereto.

In an embodiment, the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433may be arranged on the first color filter layer411, the second color filter layer421, and the third color filter layer431, respectively. In an embodiment, the first color filter layer411may at least partially overlap the first quantum dot layer413, the second color filter layer421may at least partially overlap the second quantum dot layer423, and the third color filter layer431may at least partially overlap the light-transmitting layer433. In this case, the first quantum dot layer413may convert incident light into light having a wavelength in the range of 630 nm to 780 nm, the second quantum dot layer423may convert incident light into light having a wavelength in the range of 495 nm to 570 nm, and the light-transmitting layer433may emit incident light to the outside without wavelength conversion.

In an embodiment, the light-emitting device200may be arranged on the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433. In an embodiment, the light-emitting device200may include the pixel electrode210, the intermediate layer220, and the opposite electrode230sequentially stacked. In this case, light having a wavelength in the range of 450 nm to 495 nm may be generated in the intermediate layer220including the light-emitting layer.

Because the display apparatus1is provided as a bottom emission type, the light generated in the intermediate layer220including the light-emitting layer may be emitted toward the overcoat layer100. Accordingly, the light generated in the intermediate layer220including the light-emitting layer may sequentially pass through the first quantum dot layer413and the first color filter layer411, may sequentially pass through the second quantum dot layer423and the second color filter layer421, or may sequentially pass through the layer433and the third color filter layer431.

In an embodiment, the first quantum dot layer413may convert incident light into light of a wavelength in the range of 630 nm to 780 nm, and because the first color filter layer411may pass only light having a wavelength in the range of 630 nm to 780 nm, light generated in the intermediate layer220including the light-emitting layer may be converted into light having a wavelength in the range of 630 nm to 780 nm by the first quantum dot layer413, and the converted light may pass through the first color filter layer411and be emitted to the outside through the overcoat layer100. Accordingly, in the first pixel P1, the light having a wavelength in the range of 630 nm to 780 nm may be emitted to the outside through the overcoat layer100.

In an embodiment, because the second quantum dot layer423may convert incident light into light of a wavelength in the range of 495 nm to 570 nm and the second color filter layer421may pass only light having a wavelength in the range of 495 nm to 570 nm, light generated in the intermediate layer220including the light-emitting layer may be converted into light having a wavelength in the range of 495 nm to 570 nm by the second quantum dot layer423, and the converted light may pass through the second color filter layer421and be emitted to the outside through the overcoat layer100. Accordingly, in the second pixel P2, the light having a wavelength in the range of 495 nm to 570 nm may be emitted to the outside through the overcoat layer100.

In an embodiment, because the light-transmitting layer433may emit incident light to the outside without wavelength conversion and the third color filter layer431may pass only light having a wavelength in the range of 450 nm to 495 nm, light generated in the intermediate layer220including the light-emitting layer may pass through the light-transmitting layer433without wavelength conversion, and the passed light may pass through the third color filter layer431and be emitted to the outside through the overcoat layer100. Accordingly, in the third pixel P3, the light having a wavelength in the range of 450 nm to 495 nm may be emitted to the outside through the overcoat layer100.

In the display apparatus1according to an embodiment, light in the range of 630 nm to 780 nm (e.g., the second wavelength band) may be emitted to the outside in the first pixel P1, light in the range of 495 nm to 570 nm (e.g., the third wavelength band) may be emitted to the outside in the second pixel P2, and light in the range of 450 nm to 495 nm (e.g., the first wavelength band) may be emitted to the outside in the third pixel P3. Accordingly, the display apparatus1may display a full color image.

In an embodiment, because a light path is formed between the first quantum dot layer413and the first color filter layer411, the transistor TFT may not overlap the first quantum dot layer413and/or the first color filter layer411.

In an embodiment, because a light path is formed between the second quantum dot layer423and the second color filter layer421, the transistor TFT may not overlap the second quantum dot layer423and/or the second color filter layer421.

In an embodiment, because a light path is formed between the light-transmitting layer433and the third color filter layer431, the transistor TFT may not overlap the light-transmitting layer433and/or the third color filter layer431.

FIGS.5to24are cross-sectional views illustrating a process of manufacturing a portion of a display apparatus according to an embodiment. In more detail,FIGS.5to24are cross-sectional views schematically illustrating a manufacturing process of the display apparatus1ofFIG.2.

Referring toFIGS.5to24, the method of manufacturing the display apparatus1according to an embodiment may include forming the transistor TFT on a first carrier substrate50, forming the first color filter layer411, the second color filter layer421, and the third color filter layer431on the transistor TFT, inverting the first carrier substrate50after forming a second carrier substrate70on the first color filter layer411, the second color filter layer421, and the third color filter layer431, removing the first carrier substrate50, forming the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433on the transistor TFT, and forming the light-emitting device200on the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433.

In an embodiment, before the forming of the transistor TFT on the first carrier substrate50, forming the first planarization layer109on the first carrier substrate50and forming the connection electrode141on the first planarization layer109may be performed.

Referring toFIG.5, the first planarization layer109may be formed on the first carrier substrate50. In an embodiment, the first carrier substrate50may be formed of or include glass, and the first planarization layer109may be formed of or include a polymer resin. For example, the first planarization layer109may be made of polyimide.

In an embodiment, the first planarization layer109may include the contact holes109a,109b, and109c. That is, the contact holes109a,109b, and109cmay be defined in the first planarization layer109. The contact holes109a,109b, and109cdefined in the first planarization layer109may be formed by a photomask or laser drilling.

In an embodiment, the first planarization layer109may have a maximum thickness of about 3 μm to about 4 μm (e.g., the first thickness t1). Because the first planarization layer109is provided with a maximum thickness of about 3 μm to about 4 μm, the flatness of the first planarization layer109may be secured, and the contact holes109a,109b, and109cmay be easily formed in the first planarization layer109.

Thereafter, referring toFIG.6, the connection electrode141and the light-shielding electrode143may be formed on the first planarization layer109. In an embodiment, the connection electrode141and the light-shielding electrode143may be formed on the same layer.

In an embodiment, the connection electrode141may be arranged in the contact holes109aand109bdefined in the first planarization layer109, and the light-shielding electrode143may be arranged in the contact hole109cdefined in the first planarization layer109.

In an embodiment, the connection electrode141and the light-shielding electrode143may be a single layer or multiple layers of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. Alternatively, the connection electrode141and the light-shielding electrode143may include at least one of ITO, IZO, ZnO, In2O3, IGO, or AZO.

In an embodiment, the connection electrode141may include the first conductive layer141aand the second conductive layer141b. In an embodiment, after the first conductive layer141ais formed on the first planarization layer109, the second conductive layer141bmay be formed on the first conductive layer141a.

In an embodiment, the first conductive layer141aand the second conductive layer141bmay be formed of or include different materials. For example, the first conductive layer141amay be made of Ti or ITO, and the second conductive layer141bmay be made of Cu. In an embodiment, the first conductive layer145amay be provided to protect the second conductive layer145b.

When Cu is directly formed on the first planarization layer109, the copper may be oxidized to reduce electrical conductivity of the connection electrode141. In addition, when the connection electrode141has a structure in which Ti, Cu, and ITO are sequentially stacked, in a process of etching the ITO, a tip may be generated in the ITO, and cracks may occur in inorganic layers arranged on the connection electrode141. In addition, in order to effectively prevent this, when the connection electrode141has a structure in which Ti, Cu, Ti, and ITO are sequentially stacked, a process for etching Ti and ITO may be added.

In an embodiment, by forming the first conductive layer141amade of Ti on the first planarization layer109and forming the second conductive layer141bmade of Cu on the first conductive layer141a, oxidation of Cu may be prevented.

In addition, as will be described later below, after sequentially stacking the first conductive layer141aand the second conductive layer141bon the first planarization layer109, by inverting the first carrier substrate50on which the first conductive layer141aand the second conductive layer141bare arranged, the first conductive layer141amay be above the second conductive layer141b. For example, there may be a structure in which the second conductive layer141b, the first conductive layer141a, and the first planarization layer109are sequentially stacked. Because the first conductive layer141amade of Ti is on the second conductive layer141bmade of Cu, damage to the second conductive layer141bin a subsequent process may be effectively prevented or minimized.

In an embodiment, the light-shielding electrode143may also have the same structure as the connection electrode141.

Thereafter, referring toFIG.7, the buffer layer107may be formed on the connection electrode141and the light-shielding electrode143. In an embodiment, the buffer layer107may include at least one inorganic insulating material selected from the group containing SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. In an embodiment, the buffer layer107may be provided as a single layer or multiple layers including the above-described inorganic insulating material.

Thereafter, in an embodiment, the transistor TFT may be formed on the first carrier substrate50. In an embodiment, the forming of the transistor TFT on the first carrier substrate50may include forming the semiconductor layer137on the first carrier substrate50, forming the gate insulating layer105on the semiconductor layer137, and forming the gate electrode131on the gate insulating layer105.

Referring toFIG.8, the semiconductor layer137may be formed on the buffer layer107. In an embodiment, the semiconductor layer137may include an oxide semiconductor and/or a silicon semiconductor.

Thereafter, referring toFIG.9, the gate insulating layer105may be formed on the semiconductor layer137. In an embodiment, the gate insulating layer105may include at least one inorganic insulating material selected from the group containing SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. In an embodiment, the gate insulating layer105may be provided as a single layer or multiple layers including the above-described inorganic insulating material.

In an embodiment, the gate insulating layer105may include the contact holes105a,105b,105c, and105d. That is, the contact holes105a,105b,105c, and105dmay be defined in the gate insulating layer105. In an embodiment, the contact holes105band105dmay be defined in the gate insulating layer105and the buffer layer107.

Thereafter, referring toFIG.10, the gate electrode131, the source electrode133, and the drain electrode135may be formed on the gate insulating layer105. In an embodiment, the gate electrode131, the source electrode133, and the drain electrode135may be formed on the same layer. However, the disclosure is not limited thereto.

InFIG.10, the source electrode133is formed on the left side of the gate electrode131and the drain electrode135is formed on the right side of the gate electrode131, but the disclosure is not limited thereto. In an embodiment, the drain electrode135may be formed on the left side of the gate electrode131, and the source electrode133may be formed on the right side of the gate electrode131.

In an embodiment, the gate electrode131, the source electrode133, and the drain electrode135may be a single layer or multiple layers of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu.

In an embodiment, the gate electrode131may at least partially overlap the semiconductor layer137formed thereunder. In an embodiment, the source electrode133may be electrically connected to the semiconductor layer137through the contact hole105adefined in the gate insulating layer105. In addition, in an embodiment, the drain electrode135may be electrically connected to the semiconductor layer137through the contact hole105cdefined in the gate insulating layer105. However, the disclosure is not limited thereto.

In addition, the source electrode133may be electrically connected to the light-shielding electrode143through the contact hole105bdefined in the buffer layer107and/or the gate insulating layer105, and the drain electrode135may be electrically connected to the connection electrode141through the contact hole105ddefined in the buffer layer107and/or the gate insulating layer105. However, the disclosure is not limited thereto.

In an embodiment, the contact hole109bdefined in the first planarization layer109and the contact hole105ddefined in the buffer layer107and/or the gate insulating layer105in a direction perpendicular to the first carrier substrate50may overlap at least partially. In addition, in an embodiment, the contact hole109cdefined in the first planarization layer109and the contact hole105bdefined in the buffer layer107and/or the gate insulating layer105in the direction perpendicular to the first carrier substrate50may overlap at least partially.

In an embodiment, metals arranged in the contact holes105band105ddefined the gate insulating layer105and/or the buffer layer107and the contact holes109band109cdefined in the first planarization layer109reflect incident light, thereby effectively preventing or minimizing color mixing between adjacent pixels.

In an embodiment, by electrically connecting the source electrode133and/or the drain electrode135to the connection electrode141through the contact hole105ddefined in the gate insulating layer105and the buffer layer107, the transistor TFT may be stabilized.

Thereafter, referring toFIG.11, the first insulating layer103may be formed on the gate electrode131, the source electrode133, and the drain electrode135.

In an embodiment, the first insulating layer103may be formed as a single layer or multiple layers constituting a film including an organic material or an inorganic material. In an embodiment, the first insulating layer103may include a general polymer such as BCB, PI, HMDSO, PMMA, and PS, a polymer derivative including a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, or a blend thereof. In an embodiment, the first insulating layer103may include SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO.

Thereafter, referring toFIG.12, the first color filter layer411, the second color filter layer421, and the third color filter layer431may be formed on the first insulating layer103. In an embodiment, the first color filter layer411, the second color filter layer421, and the third color filter layer431may be formed on the first insulating layer103by an inkjet printing method. However, the disclosure is not limited thereto.

In an embodiment, each of the first color filter layer411, the second color filter layer421, and the third color filter layer431may not overlap the transistor TFT. Because each of the first color filter layer411, the second color filter layer421, and the third color filter layer431does not overlap the transistor TFT, luminous efficiency of the display apparatus may be improved.

In an embodiment, the first color filter layer411may pass only light having a wavelength in the range of 630 nm to 780 nm, the second color filter layer421may pass only light having a wavelength in the range of 495 nm to 570 nm, and the third color filter layer431may pass only light having a wavelength in the range of 450 nm to 495 nm. However, the disclosure is not limited thereto.

In a case of a structure in which a transistor is formed on a first substrate and a color filter layer is formed on a second substrate, and then the first substrate and the second substrate are bonded to each other, misalignment may occur when the first substrate and the second substrate are bonded to each other, thereby reducing optical efficiency.

In the display apparatus according to the disclosure, by sequentially forming the transistor TFT and the color filter layer (e.g., the first color filter layer411to the third color filter layer431) on the first carrier substrate50, it is possible to effectively prevent or minimize misalignment in the process of bonding the first substrate and the second substrate to each other, thereby improving the optical efficiency of the display apparatus.

Thereafter, referring toFIG.13, the second insulating layer101may be formed on the first color filter layer411, the second color filter layer421, and the third color filter layer431.

In an embodiment, the second insulating layer101may include the same material as that of the first insulating layer103. In an embodiment, the second insulating layer101may include a material different from that of the first insulating layer103.

Then, referring toFIG.14, the overcoat layer100may be formed on the second insulating layer101. In an embodiment, the overcoat layer100may be formed of or include a polymer resin. For example, the overcoat layer100may be formed of or include polyarylate, polyimide, or the like.

In an embodiment, the overcoat layer100may have a thickness of 50 μm to 70 μm (e.g., the second thickness t2). In more detail, the overcoat layer100may be provided with a thickness of 50 μm to 150 μm (e.g., the second thickness t2) from an upper surface (or one side) of the second insulating layer101. When the overcoat layer100is provided with a thickness of 50 μm to 70 μm, it is possible to effectively prevent or minimize the occurrence of curling in the overcoat layer100, and to secure the flexibility of the overcoat layer100, thereby improving the flexible or bendable characteristics of the display apparatus including the overcoat layer100.

Thereafter, referring toFIG.15, the second carrier substrate70may be formed on the overcoat layer100. In an embodiment, the second carrier substrate70may be formed of or include glass.

In an embodiment, by applying a material forming the overcoat layer100on the second insulating layer101and curing the material forming the overcoat layer100after forming the second carrier substrate70, the second carrier substrate70may be formed (or attached) on the overcoat layer100.

Thereafter, referring toFIG.16, after the second carrier substrate70is formed on the overcoat layer100, the first carrier substrate50may be inverted. In more detail, after the second carrier substrate70is formed on the first carrier substrate50, the first carrier substrate50on which the second carrier substrate70is formed may be inverted (turned over). For example, a display apparatus in which the first carrier substrate50, the first planarization layer109, the buffer layer107, the gate insulating layer105, the first insulating layer103, the second insulating layer101, the overcoat layer100, and the second carrier substrate70are sequentially stacked may be turned over so that the first carrier substrate50is arranged on the top.

Thereafter, referring toFIG.17, the first carrier substrate50may be detached (removed). In more detail, after inverting (turning over) the first carrier substrate50, the first carrier substrate50positioned on the first planarization layer109may be detached (removed).

In an embodiment, the first carrier substrate50may be detached (removed) using a laser beam. However, the disclosure is not limited thereto.

Thereafter, referring toFIG.18, the second planarization layer400may be formed on the first planarization layer109. In an embodiment, the second planarization layer400may be formed of or include a polymer resin. For example, the second planarization layer400may be formed of or include polyarylate, polyimide, or the like.

In an embodiment, the second planarization layer400may have a maximum thickness of about 10 μm to about 15 μm (e.g., the third thickness t3). In an embodiment, the second planarization layer400may be provided with a maximum thickness of about 10 μm to about 15 μm (e.g., the third thickness t3) from the upper surface (or one side) of the first planarization layer109. Because the second planarization layer400is provided with a maximum thickness of about 10 μm to about 15 μm, luminous efficiency may be effectively improved, a high-resolution display apparatus may be realized, and the amount of material forming the quantum dot layers413and423may be effectively reduced.

In an embodiment, the second planarization layer400may define the first through-hole410, the second through-hole420, and the third through-hole430therein. In addition, the second planarization layer400may include the contact hole400a. That is, the contact hole400amay be defined in the second planarization layer400.

Thereafter, referring toFIG.19, the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433may be formed on the transistor TFT. In more detail, the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433may be formed in the first through-hole410, the second through-hole420, and the third through-hole430provided in the second planarization layer400, respectively.

In an embodiment, each of the first quantum dot layer413and the second quantum dot layer423may include quantum dots. In the specification, quantum dots refer to crystals of a semiconductor compound, and may include any material capable of emitting light in various wavelength bands according to the size of the crystals.

The quantum dots exhibit unique excitation and emission characteristics according to their material and size, and thus may convert incident light into certain color light. Various materials may be employed as the quantum dots. For example, the quantum dots may include a Group II-VI compound, a Group III-V compound, a Group III-VI compound, a Group semiconductor compound, a Group IV-VI semiconductor compound, a Group IV element or compound, or any combination thereof.

The Group III-V compound may be selected from the group consisting of a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AIP, AlAs, AlSb, InN, InP, InAs, InSb, and a mixture thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AINP, AINAs, AINSb, AIPAs, AIPSb, InGaP, InNP, InAIP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and a mixture thereof; and a quaternary compound selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and a mixture thereof. However, a Group III-V semiconductor compound may further include a Group II element. Examples of the Group III-V semiconductor compound further including a Group II element may include InZnP, InGaZnP, InAlZnP, or the like.

Examples of a Group III-VI semiconductor compound may include a binary compound such as GaS, GaSe, Ga2Se3, GaTe, InS, InSe, In2S3, In2Se3, InTe, and the like; a ternary compound such as InGaS3, InGaSe3, and the like; or any combination thereof.

Examples of the Group semiconductor compound may include a ternary compound such as AgInS, AgInS2, CuInS, CuInS2, CuGaO2, AgGaO2, AgAlO2, and the like, or any combination thereof.

The Group IV-VI compound may be selected from the group consisting of a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and a mixture thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and a mixture thereof; and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and a mixture thereof.

The Group IV element may be selected from the group consisting of Si, Ge, and a mixture thereof. The Group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and a mixture thereof.

In this case, the binary compound, the ternary compound, or the quaternary compound may exist in a particle with a uniform concentration, or may be in partially different concentration distributions in the same particle.

The quantum dots may be formed in a core-shell structure having a core and a shell. An interface between the core and the shell may have a concentration gradient in which the concentration of an element present in the shell decreases toward the center.

The shell of the quantum dots may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core and/or as a charging layer for imparting electrophoretic properties to the quantum dots. The shell may be a single layer or multiple layers. An interface between the core and the shell may have a concentration gradient in which the concentration of an element present in the shell decreases toward the center.

Examples of the shell of the quantum dots may include a metal, a metalloid or non-metal oxide, a semiconductor compound, or a combination thereof. Examples of the metal or non-metal oxide may include a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, and the like, a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, and the like, or any combination thereof. Examples of the semiconductor compound may include, as described herein, the Group III-VI semiconductor compound, the Group II-VI semiconductor compounds, the Group III-V semiconductor compound, the Group III-VI semiconductor compound, the Group I-III-VI semiconductor compound, the Group IV-VI semiconductor compound, or any combination thereof. For example, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AIP, AlSb, or any combination thereof.

The quantum dots may have a size of about 45 nm or less, preferably about 40 nm or less, more preferably about 30 nm or less, and color purity or color reproducibility may be improved in this range. In addition, because light emitted through the quantum dots is emitted in all directions, a wide viewing angle may be improved.

In addition, the form of the quantum dots is not particularly limited as those generally used in the art, but more specifically spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanoplatelets, etc. may be used.

The core of the quantum dots may be 2 nm to 10 nm in diameter, and the quantum dots may emit light of a specific frequency depending on the size of particles and the type of material when exposed to light, so that the average size of the quantum dots included in the first quantum dot layer413and the average size of the quantum dots included in the second quantum dot layer423may be different from each other. For example, the larger the quantum dot size, the longer-wavelength color may be emitted.

The first quantum dot layer413and the second quantum dot layer423may further include, in addition to quantum dots, various materials for mixing and properly dispersing them. For example, the first quantum dot layer413and the second quantum dot layer423may further include scattering particles, a solvent, a photoinitiator, a binder polymer, a dispersant, and the like.

In an embodiment, the light-transmitting layer433may be formed of or include an organic material capable of emitting incident light to the outside without wavelength conversion. For example, the light-transmitting layer433may include scattering particles for uniform color spread. In this case, the scattering particles may have a diameter in the range of about 200 nm to 400 nm. However, the disclosure is not limited thereto.

In an embodiment, because an inkjet printing method is used, the amount of wasted material for forming a quantum dot layer may be minimized.

In an embodiment, the first quantum dot layer413may at least partially overlap the first color filter layer411, the second quantum dot layer423may at least partially overlap the second color filter layer421, and the light-transmitting layer433may at least partially overlap the third color filter layer431.

In an embodiment, each of the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433may be provided with a maximum thickness of 8 μm to 13 μm (e.g., the fourth thickness t4). In more detail, each of the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433may be provided with a maximum thickness of 8 μm to 13 μm (e.g., the fourth thickness t4) from the upper surface (or one side) of the first planarization layer109. Because each of the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433is provided to have a maximum thickness of 8 μm to 13 μm (e.g., fourth thickness t4), luminous efficiency of the display apparatus may be improved, and a material forming a quantum dot layer may be effectively prevented from being wasted.

In an embodiment, after respectively forming the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433in the first through-hole410, the second through-hole420, and the third through-hole430, the light-emitting device may be formed on the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433. In an embodiment, the light-emitting device may include the pixel electrode210, the intermediate layer220, and the opposite electrode230sequentially stacked, and the intermediate layer220may include a light-emitting layer.

Referring toFIG.20, the pixel electrode210may be formed on the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433. In an embodiment, the pixel electrode210may be patterned to correspond to each of the pixels P1, P2, and P3 (seeFIG.2). In an embodiment, the pixel electrode210may be directly arranged on the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433.

In an embodiment, in the pixel electrode210, a transparent or semi-transparent electrode layer may include at least one selected from the group consisting of ITO, IZO, ZnO, In2O3, IGO, or AZO.

In an embodiment, the pixel electrode210may be electrically connected to the connection electrode141through the contact hole400adefined in the second planarization layer400. Accordingly, the light-emitting device may be electrically connected to the transistor TFT.

Thereafter, referring toFIG.21, the intermediate layer220may be formed on the pixel electrode210. In an embodiment, the intermediate layer220including at least one light-emitting layer may be formed on the pixel electrode210.

In an embodiment, the light-emitting layer may include an organic light-emitting material such as a high molecular weight organic material or a low molecular weight organic material that emits light of a certain color. For example, the light-emitting layer may be formed of or include an organic material emitting blue light. However, the disclosure is not limited thereto. In an embodiment, the light-emitting layer may be formed of or include an organic material emitting red or green light, or may be formed of or include an inorganic light-emitting material or quantum dots.

In an embodiment, the intermediate layer220including at least one light-emitting layer may be provided integrally in light-emitting devices. However, the disclosure is not limited thereto.

Thereafter, referring toFIG.22, the opposite electrode230may be formed. In an embodiment, the opposite electrode230may be formed on the intermediate layer220. In an embodiment, the opposite electrode230may be integrally formed in light-emitting devices. In an embodiment, the opposite electrode230may be a reflective electrode. For example, the opposite electrode230may include a reflective film formed of or include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu, or a compound thereof.

In an embodiment, the opposite electrode230may have a maximum thickness of 1000 angstroms (Å) or more (e.g., a fifth thickness t5). If the thickness of the opposing electrode230is less than 1000 angstroms (Å), the resistance of the opposing electrode230may increase, thereby reducing light-emitting efficiency.

In an embodiment, because the pixel electrode210arranged under the intermediate layer220including a light-emitting layer is formed as a transparent or translucent electrode, and the opposite electrode230arranged on the intermediate layer220is formed as a reflective electrode, a display apparatus including the same may be a bottom emission type in which light emitted from the light-emitting layer of the light-emitting device200is emitted toward the overcoat layer100.

Thereafter, referring toFIG.23, the encapsulation member500may be formed on the light-emitting device200. In an embodiment, the encapsulation member500may be formed of or include a Fe—Ni alloy. In an embodiment, the encapsulation member500may be attached on the opposite electrode230.

In an embodiment, the encapsulation member500may have a thickness of 50 μm to 150 μm (e.g., the sixth thickness t6). Because the encapsulation member500is provided with a thickness of 50 μm to 150 μm (e.g., the sixth thickness t6), it is possible to effectively prevent or minimize contamination of the light-emitting device200from external foreign matter, and at the same time to implement a flexible or bendable display apparatus.

Thereafter, referring toFIG.24, the second carrier substrate70may be detached (removed). In an embodiment, after the second planarization layer400, the light-emitting device200, and the encapsulation member500are sequentially formed on the first planarization layer109, the second carrier substrate70under the overcoat layer100may be detached (removed). In an embodiment, the second carrier substrate70may be detached (removed) using a laser beam. However, the disclosure is not limited thereto.

The first carrier substrate50and the second carrier substrate70may be formed of or include glass. The first carrier substrate50and the second carrier substrate70are used to support components arranged thereon, and when the display apparatus includes the first carrier substrate50and/or the second carrier substrate70made of glass, bendability of the display apparatus may be reduced. For example, flexible or bendable characteristics of the display apparatus may be deteriorated.

In the disclosure, the bendability of the display apparatus may be improved by using the first carrier substrate50and/or the second carrier substrate70made of glass during a manufacturing process of the display apparatus, but later detaching (removing) the first carrier substrate50and the second carrier substrate70from the display apparatus. For example, the flexible or bendable characteristics of the display apparatus may be deteriorated.

FIG.25is a cross-sectional view schematically illustrating a portion of a display apparatus according to an embodiment.FIG.25is a cross-sectional view illustrating a cross-section of a pad unit PAD provided on the peripheral area PA.

Referring toFIG.25, the second insulating layer101, the first insulating layer103, the gate insulating layer105, and the buffer layer107may be sequentially arranged on the overcoat layer100. In an embodiment, the pad electrode145may be arranged on the buffer layer107. In an embodiment, the pad electrode145may be arranged on the same layer as that of the connection electrode141and the light-shielding electrode143described above inFIG.2.

In an embodiment, the pad electrode145may be a single layer or multiple layers of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. Alternatively, the pad electrode145may include at least one selected from the group consisting of ITO, IZO, ZnO, In2O3, IGO, or AZO.

In an embodiment, the pad electrode145may include a first conductive layer145aand a second conductive layer145b. In an embodiment, the first conductive layer145amay be arranged on the second conductive layer145b. In an embodiment, the first conductive layer145amay be made of Ti or ITO, and the second conductive layer145bmay be made of Cu.

The pad electrode145will be described in more detail with reference toFIGS.26to32.

FIGS.26to32are cross-sectional views schematically illustrating a process of manufacturing a portion of the display apparatus1according to an embodiment. In more detail,FIGS.26to32are cross-sectional views schematically illustrating a manufacturing process of the display apparatus1ofFIG.25.

Referring toFIG.26, the pad electrode145may be formed on the first carrier substrate50. In an embodiment, the pad electrode145may include the first conductive layer145aand the second conductive layer145b. In an embodiment, after the first conductive layer145ais formed on the first carrier substrate50, the second conductive layer145bmay be formed on the first conductive layer145a.

In an embodiment, the first conductive layer145aand the second conductive layer145bmay be formed of or include different materials. For example, the first conductive layer145amay be made of Ti or ITO, and the second conductive layer145bmay be made of Cu. In an embodiment, the first conductive layer145amay be provided to protect the second conductive layer145b. In more detail, the first conductive layer145amay effectively prevent the second conductive layer145bfrom being damaged in a subsequent process, and may effectively prevent the second conductive layer145bfrom being combined with a component arranged thereunder to form an oxide.

The first conductive layer145aof the pad electrode145may have a thickness of 200 angstroms (Å) to 300 angstroms (Å). If the thickness of the first conductive layer145ais less than 200 angstroms (Å), the thickness of the first conductive layer145ais too thin to protect the second conductive layer145bthrough the first conductive layer145a, so that the second conductive layer145bmay be damaged in a subsequent process or may combine with the surrounding components to form an oxide. On the other hand, if the thickness of the second conductive layer145bexceeds 300 angstroms (Å), it may be difficult to pattern the second conductive layer145b. For example, although the second conductive layer145bis etched by a wet etching process, when the first conductive layer145aexceeds 300 angstroms (Å), the second conductive layer145bmay not be well etched. Accordingly, when the first conductive layer145ahas a thickness of 200 angstroms (Å) to 300 angstroms (Å), the second conductive layer145bmay be protected by the first conductive layer145aand may be easily formed on the first conductive layer145a.

The second conductive layer145bof the pad electrode145may have a thickness of 5000 angstroms (Å) to 6000 angstroms (Å). If the thickness of the second conductive layer145bis less than 5000 angstroms (Å), the total thickness of the pad electrode145may decrease, and thus the total resistance of the pad electrode145may increase. On the other hand, if the thickness of the second conductive layer145bis greater than 6000 angstroms (Å), cracks may occur in the surrounding inorganic layer, and stress due to the thickness may increase. Accordingly, when the second conductive layer145bis provided with a thickness of 5000 angstroms (Å) to 6000 angstroms (Å), it is possible to increase the total thickness of the pad electrode145and reduce the total resistance of the pad electrode145, to effectively prevent or minimize the occurrence of cracks in the surrounding inorganic layer, and to effectively prevent or minimize an increase in stress due to the thickness.

Thereafter, referring toFIG.27, the buffer layer107may be formed on the pad electrode145. In an embodiment, the buffer layer107may include at least one inorganic insulating material selected from the group containing SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. In an embodiment, the buffer layer107may be provided as a single layer or multiple layers including the above-described inorganic insulating material.

Referring toFIG.28, the gate insulating layer105may be formed on the buffer layer107. In an embodiment, the gate insulating layer105may include at least one inorganic insulating material selected from the group containing SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. In an embodiment, the gate insulating layer105may be provided as a single layer or multiple layers including the above-described inorganic insulating material.

Thereafter, referring toFIG.29, the first insulating layer103, the second insulating layer101, and the overcoat layer100may be sequentially formed on the gate insulating layer105. In an embodiment, the first insulating layer103and the second insulating layer101may be formed of or include a polymer resin. In an embodiment, the overcoat layer100may be formed of or include a polymer resin. For example, the overcoat layer100may be formed of or include polyarylate, polyimide, or the like.

Thereafter, referring toFIG.30, the second carrier substrate70may be formed on the overcoat layer100. In an embodiment, the second carrier substrate70may be formed of or include glass.

In an embodiment, by applying a material forming the overcoat layer100on the second insulating layer101and curing the material forming the overcoat layer100after forming the second carrier substrate70, the second carrier substrate70may be formed on the overcoat layer100.

Thereafter, referring toFIG.31, after the second carrier substrate70is formed on the overcoat layer100, the first carrier substrate50may be inverted. In more detail, after the second carrier substrate70is formed on the first carrier substrate50, inverting the first carrier substrate50on which the second carrier substrate70is formed may be performed. For example, a display apparatus in which the first carrier substrate50, the buffer layer107, the gate insulating layer105, the first insulating layer103, the second insulating layer101, the overcoat layer100, and the second carrier substrate70are sequentially stacked may be turned over so that the first carrier substrate50is arranged on the top.

Thereafter, referring toFIG.32, detaching (removing) the second carrier substrate70may be performed. In more detail, after inverting (turning over) the first carrier substrate50, detaching (removing) the first carrier substrate50positioned on the first planarization layer109may be performed.

In an embodiment, the first carrier substrate50may be detached (removed) using a laser beam. However, the disclosure is not limited thereto.

In an embodiment, because the first carrier substrate50is detached (removed), the pad electrode145may be exposed to the outside. In more detail, because the first carrier substrate50is detached (removed), the first conductive layer145aof the pad electrode145may be exposed to the outside.

When Cu is directly formed on an inorganic layer, Cu and the inorganic layer are combined to form an oxide, which may deteriorate insulating properties of the inorganic layer. In addition, when Cu is directly formed on the inorganic layer, a deposition rate may be lower than when Cu is formed on Ti. Accordingly, when an electrode is manufactured by forming Ti on the inorganic film and then forming Cu on Ti, it is possible to effectively prevent or minimize the formation of oxides by combining Cu with the inorganic layer, and it is possible to improve a deposition rate of a Cu electrode.

However, when the pad electrode145has a structure in which Ti and Cu are sequentially stacked, in a subsequent wet etching process, the outermost exposed Cu may be damaged. To effectively prevent this, when the pad electrode145has a structure in which Ti, Cu, and ITO are sequentially stacked, in the process of etching the ITO, a tip may be generated in the ITO, thereby causing cracks in inorganic layers arranged on the pad electrode145. In addition, in order to effectively prevent this, when the pad electrode145has a structure in which Ti, Cu, Ti, and ITO are sequentially stacked, a process for etching Ti and ITO may be added.

In the display apparatus according to an embodiment, the first conductive layer145amade of Ti is first formed on the first carrier substrate50, and the second conductive layer145bmade of Cu is formed on the first conductive layer145a, so that the bonding of Cu and the inorganic layer to form an oxide may be effectively prevented or minimized, and the deposition rate of the Cu electrode may be improved.

In addition, by sequentially stacking the first conductive layer145aand the second conductive layer145bon the first carrier substrate50and then inverting the first carrier substrate50on which the first conductive layer145aand the second conductive layer145bare arranged, the first conductive layer145amay be above the second conductive layer145b. For example, the display apparatus may have a structure in which the second conductive layer145b, the first conductive layer145a, and the first carrier substrate50are sequentially stacked.

Thereafter, when the first carrier substrate50on the first conductive layer145ais removed, an upper surface of the first conductive layer145amay be exposed to the outside. Accordingly, because the upper surface of the first conductive layer145amade of Ti is exposed to the outside, and the second conductive layer145bmade of Cu is not exposed to the outside, damage to the second conductive layer145bmade of Cu in a subsequent process may be effectively prevented or minimized.

In an embodiment, the pad electrode145may include the first conductive layer145aincluding Ti and the second conductive layer145bincluding Cu. For example, even when the pad electrode145is provided with the first conductive layer145aincluding Ti and the second conductive layer145bincluding Cu, by inverting the first carrier substrate50on which the first conductive layer145aand the second conductive layer145bis formed after sequentially forming the first conductive layer145aincluding Ti and the second conductive layer145bincluding Cu on the first carrier substrate50, the first conductive layer145aincluding Ti is positioned on the second conductive layer145bincluding Cu, and thus oxidation or corrosion of the second conductive layer145bmade of Cu in a subsequent wet etching process may be effectively prevented or minimized.

FIG.33is a cross-sectional view of a portion of a display apparatus according to another embodiment. The embodiment ofFIG.33is different from the embodiment ofFIG.2in that bottom surfaces of the first through-holes410to430are convex downward in a −Z direction. InFIG.33, the same reference numerals as inFIG.2refer to the same members, and redundant descriptions thereof will be omitted.

Referring toFIG.33, in an embodiment, the second planarization layer400may include the first through-hole410, the second through-hole420, and the third through-hole430. In an embodiment, the bottom surfaces of the first through-hole410, the second through-hole420, and the third through-hole430provided in the second planarization layer400may have a convex shape in a direction approaching the overcoat layer100. In more detail, the bottom surfaces of the first through-hole410, the second through-hole420, and the third through-hole430provided in the second planarization layer400may have a convex shape downward in the −Z direction. For example, the bottom surfaces of the first through-hole410, the second through-hole420, and the third through-hole430may be provided in a convex lens shape.

Because light generated from the light-emitting device is extracted through the overcoat layer100due to the convex lens-shaped structure, a light efficiency in a −Z direction may be improved by a condensing effect of the convex lens-shaped structure.

In an embodiment, the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433may be provided in the first through-hole410, the second through-hole420, and the third through-hole430provided in the convex shape downward in the −Z direction, respectively.

FIG.34is a cross-sectional view of a portion of a display apparatus according to still another embodiment. The embodiment ofFIG.34is different from the embodiment ofFIG.2in that a protective layer250is arranged between the first quantum dot layer413and the pixel electrode210, between the second quantum dot layer423and the pixel electrode210, and between the light-transmitting layer433and the pixel electrode210. InFIG.34, the same reference numerals as inFIG.2refer to the same members, and redundant descriptions thereof will be omitted.

Referring toFIG.34, in an embodiment, a protective layer250is respectively arranged between the first quantum dot layer413and the pixel electrode210, between the second quantum dot layer423and the pixel electrode210, and between the light-transmitting layer433and the pixel electrode210. In an embodiment, the protective layers250respectively arranged between the first quantum dot layer413and the pixel electrode210, between the second quantum dot layer423and the pixel electrode210, and between the light-transmitting layer433and the pixel electrode210may serve to protect the first quantum dot layer413, the second quantum dot layer423, and the light-transmitting layer433.

In an embodiment, the protective layer250may be formed as a single layer or multiple layers constituting a film including an organic material or an inorganic material. In an embodiment, the protective layer250may include a general polymer such as BCB, PI, HMDSO, PMMA, and PS, a polymer derivative including a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, or a blend thereof. In an embodiment, the protective layer250may include SiOX, SiNX, SiOXNY, Al2O3, TiO2, Ta2O5, HfO2, or ZnO.

In an embodiment, the protective layer250may not be arranged in the contact hole400adefined in the second planarization layer400. However, the disclosure is not limited thereto. For example, at least a portion of the protective layer250may also be arranged in the contact hole400adefined in the second planarization layer400. In this case, in order to facilitate contact between the connection electrode141and the pixel electrode210, a width (or area) of the contact hole400adefined in the second planarization layer400may be greater.

As described above, according to an embodiment, by forming a color filter layer and a quantum dot layer on a substrate on which a transistor is arranged, a display apparatus with improved light efficiency and a method of manufacturing the same may be realized. However, the scope of the disclosure is not limited by these effects.