Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS

A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to nonvolatile memory array structure and operation. More particularly, this invention relates to flash based EEPROM nonvolatile memory device structures, peripheral circuits for operating flash based EEPROM nonvolatile memory devices and methods for operation of flash based EEPROM nonvolatile memory devices.

2. Description of Related Art

Nonvolatile memory is well known in the art. The different types of nonvolatile memory include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the Flash Memory has become one of the more popular types of Nonvolatile Memory. All EEPROM, NOR and NAND flash are Electrically Erasable and Programmable Memory using a single low-voltage power supply VDD but only EEPROM offers an erase size in unit of bytes and page with1M program/erase cycles.

The Flash Memory structures known in the art employ a charge retaining mechanism such as a charge storage phenomena and a charge trapping phenomena. The charge storage mechanism, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell determine that digital data stored. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiNx).

NOR flash provides a fast random-access, asynchronous read, but NAND flash offers a slow serial-access, synchronous read. NOR flash is the high pin-count memory chip with multiple external address and data pins, and control signal pins. One disadvantage of NOR flash is as the density being doubled, the number of its required external pin count would increase by one due to the adding of one more external address pin. In contrast, NAND has advantage of less pin-count than NOR with no address input pins. As density increases, NAND's pin count is always kept constant. Both today's NAND and NOR flash provide the advantage of in-system program and erase capabilities with 100K endurance cycles spec. NOR flash is used to store fast program code but NAND is used to store huge slow serial audio and video data storage. The size of the memory units that are erased in a NOR and NAND flash is presently around 1M bits in a giga-bit density memory device. Alternately, an EEPROM provides a unit of erase that is capable of storing a byte and a page, to permit alteration of small quantities of data or parameters.

Up until 2008, the EEPROM designs were based on a semiconductor manufacturing process where the transistor devices had a drain-to-source breakdown voltage (BVDS) of approximately ±16V. In 2008, the semiconductor manufacturing processing moved to having feature sizes less than 0.13 μm. The current EEPROM design employ program and erase voltage levels of approximately +15.0V. The current EEPROM memory cell is designed having a polycrystalline silicon floating-gate placed over a tunneling oxide. A polycrystalline control gate is formed over an inter-polycrystalline silicon oxide layer above the floating gate. Low current Fowler-Nordheim channel erase operation is used to increase the threshold voltage Vt of the memory cell above the desired value of +2.0V to store a digital datum of a logical “1”. A low-current Fowler-Nordheim channel program operation is used to decrease threshold voltage Vt of the memory cell to a voltage level of approximately −2.0V to store digital datum of a logical “0”.

The advantage of an EEPROM memory device is its high 1M program/erase cycles and its ability to be programmed in units of byte and page. However, a disadvantage of an EEPROM memory device is that the physical size of a memory cell is very large and not scalable. The averaged cell size is more than 80 λ2and because of the inability to be scaled the manufacturing technology is employing feature sizes of approximately 0.18μ. And as noted above, the EEPROM designs were based on a drain-to-source breakdown voltage (BVDS) of approximately ±16V.

SUMMARY OF THE INVENTION

An object of this invention is to provide a method for operating an array of EEPROM connected flash nonvolatile memory cells at increments of a page and block while minimizing operational disturbances and providing bias operating conditions to prevent drain to source breakdown drain to source breakdown in peripheral devices.

Another object of this invention is to provide a row decoder circuit for selecting nonvolatile memory cells of an array of EEPROM connected nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells of the array of the EEPROM connected nonvolatile memory cells while minimizing operational disturbances and preventing drain to source breakdown in peripheral devices.

Further, another object of this invention is to provide a select gate decoder circuit for selecting and providing biasing conditions to selected nonvolatile memory cells of an array of EEPROM connected nonvolatile memory cells for reading, programming, verifying, and erasing the selected nonvolatile memory cells of the array of the EEPROM connected nonvolatile memory cells while minimizing operational disturbances and preventing drain to source breakdown of peripheral devices.

To accomplish at least one of these objects, a nonvolatile memory device includes an array of nonvolatile memory cells arranged in rows and columns. The nonvolatile memory cells are connected into an EEPROM configuration where the nonvolatile memory cells located on each column are connected such that the drains of each of the nonvolatile memory cells are commonly connected to a bit line associated with each column. The nonvolatile memory cells on each row are commonly connected to a word line. The nonvolatile memory cells on two adjacent rows are commonly connected to a select gate control line. The array of nonvolatile memory cells is placed in an isolation well of a first impurity type. The array of the nonvolatile memory cells is divided into blocks and each block is divided into pages. Each page includes one row of the nonvolatile memory cells within each block of each sector connected to a word line.

The EEPROM configured nonvolatile memory cells each have a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The drain of the floating gate memory transistor is connected to the source of the floating gate select transistor and the drain of the floating gate select transistor is connected to the bit line that is commonly connected with one column of the EEPROM configured nonvolatile memory cells. The source of the floating gate memory transistor is connected to a source line that is commonly connected with the one row of the EEPROM configured nonvolatile memory cells. A gate of the floating gate select transistor is connected to the connected to a select gate control line associated with one row of the EEPROM configured memory cells for receiving a select gate control biasing voltages for selectively activating the floating gate select transistor to connect the floating gate memory transistor to the bit line for reading, programming, and erasing the floating gate memory cell. The gate of the floating gate memory cell is connected to the word line for receiving operational biasing voltages for reading, programming, and erasing the floating gate memory transistor.

The nonvolatile memory device has a row decoder that has a first block selector that sets a block signal when a block address indicates that a block is selected. The row decoder further includes a word line selector circuit, which based on a row address provides the word lines with word line operational biasing voltage levels necessary for biasing the control gates of the EEPROM configured nonvolatile memory cells for reading, programming, verifying, and erasing. The row decoder has a voltage level shifter for shifting a voltage level of a block select signal to activate pass gates to transfer the operational biasing voltage levels to the word lines of the selected block for biasing the control gates of the EEPROM configured nonvolatile memory cells of the block for reading, programming, verifying, and erasing the selected nonvolatile memory cells.

The nonvolatile memory device has a select gate decoder circuit is connected to each select gate control line within each block to transfer a necessary gate select biasing voltage for reading, programming, verifying, and erasing selected EEPROM configured nonvolatile memory cells to selected select gate control lines. The select gate decoder circuit has a second block selector circuit which activates for the selection of the block being addressed. The block selector circuit is connected to a select gate voltage level shifter that shifts the voltage level of the block selector signals for activating pass transistors to transfer select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor of each of the EEPROM configured nonvolatile memory cells of the selected block for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells.

The nonvolatile memory device has a column decoder in communication with bit lines for providing biasing voltages for reading, programming, verifying, and erasing selected EEPROM configured nonvolatile memory cells. The row decoder, select gate decoder, and column decoder provide inhibit biasing voltage levels to all the non-selected nonvolatile EEPROM configured nonvolatile memory cells to minimize disturbances resulting from the reading, programming, verifying, and erasing selected EEPROM configured nonvolatile memory cells. Further the row decoder, select gate decoder, and column decoder generate the word line biasing voltages, the select gate biasing voltage, bit line biasing voltages, and the inhibit biasing voltages such that an amplitude of the word line biasing voltages, the select gate biasing voltage, bit line biasing voltages, and the inhibit biasing voltages does not exceed a drain-to-source break down voltage of transistors forming the row decoder, select gate decoder, and column decoder.

For reading a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a read reference biasing voltage level to the word line of the selected EEPROM configured nonvolatile memory cells. The row decoder further transfers read reference biasing voltage level to the word lines of the unselected EEPROM configured nonvolatile memory cells in the selected and unselected blocks. The column decoder transfers a first read biasing voltage to the drains of the selected EEPROM configured nonvolatile memory cells and the voltage level of the ground reference voltage source to the drains of the unselected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The first read biasing voltage has a voltage level of approximately +1.0V. The read reference biasing voltage level is approximately the voltage level of the power supply voltage source VDD, where voltage level of the power supply voltage source is either 1.8V or 3.0V. The bit lines are is pre-charged to the voltage level of the first read voltage of approximately the 1.0V. The pre-charged level of the first read voltage is discharged to approximately 0.0V when the memory cell has been programmed and has a threshold voltage level less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the first read level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary erased threshold voltage level of approximately +4.0V. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

For erasing a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high positive erase voltage to the word line of the selected EEPROM configured nonvolatile memory cells and transfers the ground reference voltage level to the word lines of the unselected EEPROM configured nonvolatile memory cells of the selected block. The row decoders of the unselected blocks of EEPROM configured nonvolatile memory cells disconnect the word lines of the unselected EEPROM configured nonvolatile memory cells so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The select gate decoder transfers the very high negative erase voltage to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to an isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the select gate decoder. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −10.0V to approximately −8.0V.

For verifying a page erase, a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the second read biasing voltage is pre-charged to approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage level is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the second biasing read voltage level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

For erasing a selected block of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high positive erase voltage to all the word lines of the EEPROM configured nonvolatile memory cells of the selected block. The row decoders of the unselected blocks of EEPROM configured nonvolatile memory cells disconnect the word lines of the unselected EEPROM configured nonvolatile memory cells so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The select gate decoder transfers the very high negative erase voltage to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the very high negative erase voltage. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the select gate decoder. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V.

For verifying a block erase, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read voltage to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the second read biasing voltage is pre-charged to approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the second read biasing voltage will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

For erasing an entire chip containing the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high positive erase voltage to all the word lines of the EEPROM configured nonvolatile memory cells of the entire chip. The select gate decoder transfers the very high negative erase voltage to the selected and unselected select gate control lines. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the select gate decoder. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V.

For verifying erasing an entire chip, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the second biasing read voltage is pre-charged to approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V.

For programming a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a very high negative program voltage to the word line of the selected EEPROM configured nonvolatile memory cells. The row decoder transfers the voltage level of the ground reference voltage source to the unselected word lines of the selected block and disconnects the words lines to float the unselected blocks of the array of EEPROM configured nonvolatile memory cells. The column decoder transfers a high program select voltage level to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are to be programmed. The column decoder transfers a low program deselect voltage level to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are not to be programmed. The select gate decoder transfers a high positive activate control signal to the select gate control lines connected to the selected nonvolatile voltage cells and transfers a low deactivate select gate signal to the select gate control lines connected to the selected nonvolatile voltage cells to allow them to float. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The voltage level of the very high negative program voltage and the high positive program select voltage are less than the breakdown voltage level of transistors forming the row decoder. The voltage level of the high negative program voltage is from approximately −8.0V to approximately −10.0V. The high program select voltage is from approximately +8.0V to approximately +10.0V and the low program deselect voltage level is from approximately −2.0V to the voltage level of the ground reference voltage source (0.0V) to avoid programming of the unselected EEPROM configured nonvolatile memory cells.

For verifying a page program, a selected page of the array of EEPROM configured nonvolatile memory cells, the row decoder transfers a voltage level of an upper boundary of programmed threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. The column decoder transfers a second read biasing voltage to the drains of the selected EEPROM configured nonvolatile memory cells. The select gate decoder transfers an activate select gate signal to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The upper boundary of an programmed threshold voltage level is approximately +1.0V for the single level cell program. The bit line is pre-charged to the voltage level of the second read biasing voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has been successfully programmed and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are not successfully programmed, the pre-charged level will be maintained when the threshold voltage of the programmed EEPROM configured nonvolatile memory cells is greater than the upper boundary of the programmed threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

In other embodiments, a method for operating an array includes steps for providing the operating conditions for reading, page erasing, block erasing, chip erasing, page erase verifying, block erase verifying, chip erase verifying, page programming, and page program verifying of selected EEPROM configured nonvolatile memory cells of the array of EEPROM configured nonvolatile memory cells. For the step of reading a selected page of the array of EEPROM configured nonvolatile memory cells, a read reference biasing voltage level is transferred to the word line of the selected EEPROM configured nonvolatile memory cells. A read reference biasing voltage level is transferred to the word lines of the word lines of the unselected EEPROM configured nonvolatile memory cells in the selected and unselected blocks. A first read biasing voltage is transferred to the drains of the selected EEPROM configured nonvolatile memory cells and the voltage level of the ground reference voltage source is transferred to the drains of the unselected EEPROM configured nonvolatile memory cells. An activate select gate signal is transferred to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and transfers a deactivate select gate signal to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The first read biasing voltage has a voltage level of approximately +1.0V. The read reference biasing voltage level is approximately the voltage level of the power supply voltage source VDD, where power supply voltage source is either 1.8V or 3.0V. The voltage level of the bit lines is pre-charged to the first read voltage level. The pre-charged level of the first read voltage is discharged to approximately 0.0V when the memory cell has been successfully programmed and has a threshold voltage level is less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells are not successfully programmed, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the upper boundary of the programmed threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

For the step of erasing a selected page of the array of EEPROM configured nonvolatile memory cells, a very high positive erase voltage is transferred to the word line of the selected EEPROM configured nonvolatile memory cells and the word lines of the unselected EEPROM configured nonvolatile memory cells of the selected block are set to the ground reference voltage level. A very high negative erase voltage is applied to the selected and unselected select gate control lines. The word lines of the unselected EEPROM configured nonvolatile memory cells are disconnected and allowed to float so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The very high negative erase voltage is applied to an isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage are less than approximately the breakdown voltage level of transistors. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −10.0V to approximately −8.0V.

For the step of verifying a page erase, a selected page of the array of EEPROM configured nonvolatile memory cells, a voltage level of a lower boundary of an erased threshold voltage level is transferred to the word lines of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is applied to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and a deactivate select gate signal is applied to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the bit lines is pre-charged to second read biasing voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor wherein the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

For the step of erasing a selected block of the array of EEPROM configured nonvolatile memory cells, a very high positive erase voltage is applied to all the word lines of the EEPROM configured nonvolatile memory cells of the selected block. A very high negative erase voltage is applied to the selected and unselected selected gate control lines. The word lines of the unselected EEPROM configured nonvolatile memory cells of the unselected blocks are disconnected so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected EEPROM configured nonvolatile memory cells in unselected blocks. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the very high negative erase voltage. The very high negative erase voltage is applied to the isolation well of the first impurity type. The voltage levels of the very high positive erase voltage and the very high negative erase voltage is approximately the breakdown voltage level of transistors. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V.

For the step of verifying a block erase, a voltage level of a lower boundary of an erased threshold voltage level is applied to the word lines of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is applied to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the bit lines are pre-charged to the second read biasing voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

For the step of erasing an entire chip containing the array of EEPROM configured nonvolatile memory cells, a very high positive erase voltage is applied to all the word lines of the EEPROM configured nonvolatile memory cells of the entire chip. A very high negative erase voltage is applied to the isolation well of the first impurity type. The very high negative erase voltage is applied to the all the select gate control lines of the EEPROM configured nonvolatile memory cells of the entire chip. The source lines of the EEPROM configured nonvolatile memory cells are set to the very high negative erase voltage level. The voltage levels of the very high positive erase voltage and the very high negative erase voltage is less than approximately the breakdown voltage level of transistors. The voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −8.0V to approximately −10.0V.

For the step verifying erasing an entire chip, the row decoder transfers a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is transferred to the select gate control lines of the selected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The lower boundary of an erased threshold voltage level is approximately +4.0V for the single level cell program. The voltage level of the bit lines is pre-charged to the second read biasing voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V.

For the step of programming a selected page of the array of EEPROM configured nonvolatile memory cells, a very high negative program voltage is applied to the word line of the selected EEPROM configured nonvolatile memory cells. A second negative program inhibit voltage is applied to the word lines of the unselected word lines is the selected block and the unselected blocks of the array of EEPROM configured nonvolatile memory cells. A high program select voltage level is applied to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are to be programmed. A low program deselect voltage level is applied to the bit lines and thus to the drains of the selected EEPROM configured nonvolatile memory cells that are not to be programmed. A high positive activate control signal is transferred to the select gate control lines connected to the selected nonvolatile voltage cells and a low deactivate select gate signal is transferred to the select gate control lines connected to the unselected nonvolatile voltage cells to allow them to float. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The voltage level of the very high negative program voltage is less than the breakdown voltage level of transistors forming the row decoder. The voltage level of the high negative program voltage is from approximately −8.0V to approximately −10.0V. The high program select voltage is from approximately +8.0V to approximately +10.0V and the low program deselect voltage level is from approximately −2.0V to the voltage level of the ground reference voltage source (0.0V) to avoid programming of the unselected EEPROM configured nonvolatile memory cells.

For the step of verifying a page program, a selected page of the array of EEPROM configured nonvolatile memory cells, a voltage level of an upper boundary of an programmed threshold voltage level is applied to the word line of the selected and unselected EEPROM configured nonvolatile memory cells. A second read biasing voltage is applied to the drains of the selected EEPROM configured nonvolatile memory cells. An activate select gate signal is transferred to the select gate control lines of the selected EEPROM configured nonvolatile memory cells and a deactivate select gate signal is transferred to the select gate control lines of the unselected EEPROM configured nonvolatile memory cells. The source lines of the EEPROM configured nonvolatile memory cells are set to the voltage level of the ground reference voltage source. The upper boundary of an programmed threshold voltage level is approximately +1.0V for the single level cell program. The voltage level of the bit lines is pre-charged to the second read biasing voltage that is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor, where the voltage level of the power supply voltage source is either +1.8V or +3.0V. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has been successfully programmed and has a threshold voltage level is less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells are not programmed, the pre-charged level will be maintained when the threshold voltage of the programmed EEPROM configured nonvolatile memory cells is greater than the upper boundary of the threshold voltage level. The activate select gate signal has a voltage level of approximately +5.0V and the deactivate select gate signal has a voltage level of the voltage level of the ground reference voltage source.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1ais schematic diagram of an embodiment of a two floating-gate transistor EEPROM configured memory cell5.FIG. 1bis a top plan view of an embodiment of two floating-gate transistor EEPROM configured memory cell5.FIG. 1cis a cross sectional cross sectional view of an embodiment of two floating-gate transistor EEPROM configured memory cell5. The two floating-gate transistor EEPROM configured memory cell5is formed in the top surface of a P-type substrate10. An N-type material is diffused into the surface of the P-type substrate10to form a deep N-well15. A P-type material is then diffused into the surface of the deep N-well15to form a P-well20(commonly referred to as a triple P-well—TPW). The N-type material is then diffused into the surface of a P-type well TPW20to form the drain region (D)31of the NMOS floating-gate select transistor30, the source region of the floating gate select transistor30and the source/drain regions (S/D)55. The source/drain region55is the source region of the floating gate select transistor30and the drain region for the floating gate memory transistor25. A first polycrystalline silicon layer is formed above the bulk region of the P-type well20between the drain region31and the source/drain region55of the NMOS floating-gate select transistor30to form the floating gate32. The first polycrystalline layer is also formed above the bulk region between the source/drain region55and the source region29to form the floating gate27of the floating gate memory transistor25. A second polycrystalline silicon layer is formed over the floating gates27and32to create the control gates28and33of the floating gate memory transistor25and the floating-gate select transistor30. The source/drain regions55is formed between the adjacent second polycrystalline silicon layers of control gates28and33of the floating gate memory transistor25and the floating-gate select transistor30. The source region29of the floating gate memory transistor25is shown as a half source region in that the whole source region29is shared with the source region of an adjacent two floating-gate transistor EEPROM configured memory cell5in an array. The self-aligned source/drain regions29are commonly used in the floating gate memory transistor25to reduce the source line pitch.

In an array, multiple two floating-gate transistor EEPROM configured memory cells5are arranged in a matrix of rows and columns. The control gate28of the floating gate memory transistors25is extended to form a word line35that connects to each of the floating gate memory transistor25on a row of the array. The control gate33of the NMOS floating-gate select transistor30is connected to receive the select gating signal40at the drain31. A P+-contact21connects a P-well TPW20to the P-well voltage source70, the N+-contact16is connected to the deep N-well voltage source65, and the P+-contact11is connected to the P-substrate voltage source60. In most embodiments P-substrate voltage source60is actually the ground reference voltage source.

FIGS. 2aand2bare graphs of threshold voltage levels of various embodiments of a two floating-gate transistor EEPROM configured memory cell with a floating gate memory transistor25and a floating-gate select transistor30ofFIG. 1a.FIG. 2aillustrates the voltage thresholds levels the NMOS floating-gate select transistor30. The floating-gate select transistor30has a positive threshold voltage that is nominally approximately +2.0V. The voltage level applied to the select gating signal40must be greater than the select gating voltage VSG (boosted) to insure that the floating-gate select transistor30will turn on. The select gating voltage VSG (boosted) is set to a voltage level that is approximately +2.0V greater than the positive threshold voltage Vt1of the floating-gate select transistor30. The select gating voltage VSG (boosted) will be discussed in more detail hereinafter for the read operation, the program operation, the program verify operation, the erase operation (page, block, and chip), and the erase verify operation.

FIG. 2billustrates the voltage thresholds levels for programming and erasing of the floating gate memory transistor25. There is a positive programmed threshold voltage level (Vt1) representing a logical “0” datum and one positive erased threshold voltage level (Vt0) representing a logical “1” datum. The programmed threshold voltage level (Vt1) is established through a Fowler-Nordheim edge tunneling effect and the erased threshold voltage level (Vt0) is established through a Fowler-Nordheim channel tunneling effect. An upper boundary of the threshold voltage Vt0H for programming of the floating gate memory transistor25with an voltage level of approximately +1.0 V to activate the Fowler-Nordheim edge tunneling effect. A lower boundary of the threshold voltage Vt1L for erasing the floating gate memory transistor is approximately +4.0V to activate the Fowler-Nordheim channel tunneling effect.

FIGS. 3a-3dare simplified schematic diagrams of an array of a two floating-gate transistor EEPROM configured memory cells110a, . . . ,110millustrating the bias conditions for reading, programming, page erasing and chip erasing of two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention. The EEPROM configured memory cells110a, . . . ,110mare arranged in rows and columns to form an array. The schematic diagrams ofFIGS. 3a-3dare simplified to show a single column of the array of EEPROM configured memory cells110a, . . . ,110m. Each of the EEPROM configured memory cells110a, . . . ,110mhas a floating gate select transistor115a, . . . ,115mand a floating-gate memory transistor120a, . . . ,120m. The drains of the floating gate memory transistors120a, . . . ,120mand the source of floating-gate select transistors115a, . . . ,115mare connected together. The drains of the floating gate select transistors115a, . . . ,115mon each column are commonly connected to the bit line140. The control gates of each of the floating gate memory transistors120a, . . . ,120mon each row are commonly connected to one of a word lines125a, . . . ,125mThe sources of the floating-gate memory transistors120a, . . . ,120mon each row of the array are commonly connected to the source lines135a, . . . ,135m. The gates of the floating-gate select transistors115a, . . . ,115mare connected to the select gate lines130a, . . . ,130m. The array100of the EEPROM configured memory cells110a, . . . ,110mare formed in a single P-type well TPW105.

The word lines125a, . . . ,125mare connected to a row decoder that decodes a block and row address and applies the appropriate voltages to the word lines125a, . . . ,125mfor reading, programming, and erasing selected EEPROM configured memory cells110a, . . . ,110mof the array100. The select gate lines130a, . . . ,130mare connected to a select gate decoder that decodes a block and row address and applies to the appropriate voltage levels to the source lines select gate lines130a, . . . ,130mfor reading, programming, and erasing selected EEPROM configured memory cells110a, . . . ,110mof the array100. The bit line140is connected to a pass gate and sense amplifier that decodes a column address and applies the appropriate biasing voltages for reading, programming, and erasing selected EEPROM configured memory cells110a, . . . ,110mof the array100. The bit line140is representative of multiple bit lines in a much larger array of EEPROM configured memory cells110a, . . . ,110m. The P-type well TPW105and the source lines135a, . . . ,135mare connected to be appropriately biased for reading, programming, and erasing selected EEPROM configured memory cells110a, . . . ,110mof the array100.

FIG. 3aillustrates the biasing voltages for reading data from selected EEPROM configured memory cells110a, . . . ,110mof the array100. The word line125a, which is connected to the selected page having the selected EEPROM configured memory cell110acontaining the selected floating gate memory transistor120a, is set to the voltage level of the read voltage threshold VR or approximately the level of the power supply voltage source VDD. The power supply voltage source VDD is either 1.8V or 3.0V. The unselected word line125m, which is connected to the unselected page having the selected EEPROM configured memory cell110mcontaining the unselected floating gate memory transistor120m, is set to the voltage level of the read voltage threshold VR. The select gate line130aconnected to the selected floating-gate select transistor115ais set to the voltage level select gating voltage VSG that is approximately +4.0V. The select gate line130m, which is connected to the unselected page having the selected EEPROM configured memory cell110mcontaining the unselected floating gate memory transistor115m, is set to a first select gate inhibit biasing voltage that is approximately the voltage level of the ground reference voltage source. The bit line BL[0]140is set to the first read voltage VRB of approximately +1.0V. The P-type well TPW105and the source lines135a, . . . ,135mare set to the voltage level of the ground reference voltage source (0.0). The bit line BL[0]140is pre-charged to the voltage level of the first read voltage VRB of approximately the 1.0V. The pre-charged level of the first read voltage VRB is discharged to approximately 0.0V when the selected EEPROM configured memory cell110ahas been programmed and has a threshold voltage level less than the upper boundary of the programmed threshold voltage level. If the selected EEPROM configured memory cell110ais erased, the pre-charged level will be maintained when the threshold voltage of the selected EEPROM configured memory cell110ais greater than the lower boundary erased threshold voltage level of approximately +4.0V. If the selected floating gate memory transistor120ais erased as a logical “1”, the selected NMOS floating gate memory transistor120awill not turn on and a sense amplifier will detect the programmed level of the logical “1”. Alternately, if the selected floating gate memory transistor120ais programmed with a logical “0”, the selected floating gate memory transistor120awill turn on and a sense amplifier will detect the programmed level of the logical “0”.

FIG. 3billustrates the biasing voltages for programming data to selected EEPROM configured memory cells110a, . . . ,110mof the array100. The word line125a, which is connected to the selected page having the selected EEPROM configured memory cell110acontaining the selected floating gate memory transistor115a, is set to the voltage level of a very high negative programming voltage level of from approximately −10.0V to approximately −8.0V. The unselected word line125m, which is connected to the unselected page containing the unselected floating gate memory transistor120m, is disconnected to be floating. The select gate line130aconnected to the selected floating gate memory transistor120ais set to a voltage level of a very high positive voltage that is from approximately +8.0V to approximately +10.0V. The select gate line130m, which is connected to the unselected page having the unselected floating-gate select transistor115m, is set to a program inhibit voltage level VPLthat is approximately either a voltage level of approximate +2.0v or the voltage level of the ground reference voltage source (0.0V). The P-type well TPW105and the source lines135a, . . . ,135mare set to the voltage level of the ground reference voltage source (0.0). If the selected floating gate memory transistor120ais to remain erased as a logical “1”, the bit line BL[0]140connected to the selected NMOS floating gate memory transistor120awill be set to a program biasing drain voltage VPBof approximately the ground reference voltage. Alternately, if the selected floating gate memory transistor120ais to be programmed with a logical “0”, the bit line BL[0]140connected to the selected floating gate memory transistor120ais set to the program biasing drain voltage VPBof approximately +5.0V.

FIG. 3cillustrates the biasing voltages for erasing a page of data from selected EEPROM configured memory cells110a, . . . ,110mof the array100. The word line125a, which is connected to the selected page having the selected EEPROM configured memory cell110acontaining the selected floating gate memory transistor120a, is set to the voltage level of a very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V. The unselected word line125m, which is connected to unselected pages of the selected block containing an unselected floating gate memory transistor120m, is set to the voltage level of approximately the ground reference voltage source. The unselected word line125m, which is connected to unselected pages of an unselected block containing an unselected floating gate memory transistor120m, is set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. The select gate lines130a, . . . ,130mare set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. The bit line BL[0]140, the P-type well TPW105, and the source lines135a, . . . ,135mare set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V.

The approximately 16.0 V to 20.0 V voltage difference between the very high positive erasing voltage level at the control gate of the selected floating gate memory transistor120aand very high negative erasing voltage level at the P-type well TPW105induces the Fowler-Nordheim channel tunneling phenomena that attracts electrons into the floating-gate of the selected floating gate memory transistor120ain the selected page. As a consequence, the threshold voltage of the selected floating gate memory transistor is increased. After about 500 μS, the threshold voltage would be increased to be greater than lower boundary of the erased threshold voltage level Vt1L of approximately 4.0V. The bias conditions as shown, prevent the floating gate memory transistors120min the unselected pages from being effected during the erase operation. After a page erase operation, an erase verification operation is executed to insure that the desired erased threshold voltage level Vt1L of approximately 4.0V is achieved.

FIG. 3dillustrates the biasing voltages for erasing an entire chip of data from selected EEPROM configured memory cells110a, . . . ,110mof the array100. All the word lines125a, . . . ,125mof the chip containing the all the floating gate memory transistor120a, . . . ,120mare selected and set to the voltage level of a very high positive erasing voltage level of from approximately +8.0V to approximately +10.0V. The select gate lines130a, . . . ,130mare connected are set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V. The bit line140, the P-type well TPW105, and the source lines135a, . . . ,135mare set to the very high negative erasing voltage level of from approximately −10.0V to approximately −8.0V.

As described, the approximately 16.0 V to 20.0 V voltage difference between the very high positive erasing voltage level at the control gate of all the floating gate memory transistors120a, . . . ,120mand very high negative erasing voltage level at the P-type well TPW105induces the Fowler-Nordheim channel tunneling phenomena that attracts electrons into the floating-gate of the selected floating gate memory transistors120a, . . . ,120min the chip. As a consequence, the threshold voltage of the floating gate memory transistors120a, . . . ,120mis increased. After about 500 μS, the threshold voltage would be increased to be greater than lower boundary of the erased threshold voltage level Vt1L of approximately +4.0V.

FIG. 4is a block diagram of a nonvolatile memory device200embodying the principles of the present invention incorporating the various embodiments of EEPROM configured memory cells of the present invention. The EEPROM nonvolatile memory device200includes an array205of EEPROM configured memory cells arranged in a matrix of rows and columns. The array205is partitioned into a uniform number of blocks210a, . . . ,210mand each block is divided into a uniform number of pages215a,215b, . . . ,215n, and216a,216b, . . . ,216n, For instance, a 1 Mb memory array device may be divided into 128 blocks. Each block then becomes 8 KB and may be divided into a number of pages such as 8 pages of 1 KB each. Further, the block is divided into pages. In this example, the page may have a size of 4 Kb such that one page is equivalent to one word line or row of the block or sub-array215a,215b, . . . ,215n, and216a,216b, . . . ,216n. Thus, each block215a,215b, . . . ,215n, and216a,216b, . . . ,216nhas 8 pages or word lines.

The column address decoder265receives a column address290, decodes the column address290, and from the decoded column address290selects which columns of the array are being accessed. The data register and sense amplifier260activates the appropriate bit lines270a, . . . ,270kfor operating a selected block210a, . . . ,210m. The appropriate bit lines270a, . . . ,270kare further connected to the column address decoder265. The data register and sense amplifier260receives the data signals through the bit lines270a, . . . ,270kfrom the selected block210a, . . . ,210mand senses and holds the data from the data signal for a read operation. In a program operation, the data is transferred from the data register and sense amplifier260through the bit lines270a, . . . ,270kto the selected block210a, . . . ,210m. The data being read from or written (program and erase) to the array205of EEPROM configured memory cells is transferred to and from the data register and sense amplifier260through the column address decoder265from and to the data input/output bus295.

Each block215a,215b, . . . ,215n, and216a,216b, . . . ,216nof the array205of EEPROM configured memory cells is connected to a row decoder220through the word lines275a,275b, . . . ,275n,276a,276b, . . . ,276n. Each block210a, . . . ,210mis connected to a block row decoder230a, . . . ,230mwithin the row decoder220for providing the appropriate voltage levels to a selected page or word line for reading and programming selected EEPROM configured memory cells. The row address285is transferred to each of the block row decoders230a,230b, . . . ,230nto select the page or word line and to provide the appropriate voltage levels for reading and programming the selected EEPROM configured memory cells.

Each block215a,215b, . . . ,215n, and216a,216b, . . . ,216nof the array205of EEPROM configured memory cells is connected to a select gate decoder240through the select gate lines280a,280b, . . . ,280nand281a,281b, . . . ,281n. The select gate decoder240is formed of multiple blocks of select gate decoders245a, . . . ,245m. Each block215a,215b, . . . ,215n, and216a,216b, . . . ,216nis connected with its own select gate line decoder245a, . . . ,245mfor providing the appropriate voltage levels to selected gate lines of a selected page for reading and programming selected EEPROM configured memory cells. The row address285is transferred to each of the block select gate line decoders245a,245b, . . . ,245mto select the select gate line of the selected page to provide the appropriate voltage levels for reading, programming, and erasing the selected EEPROM configured memory cells.

Refer now toFIG. 5for a discussion of the structure of a block210of the array205ofFIG. 4. The block210is exemplary of the all the blocks210a, . . . ,210mof array205. The block210is placed in a common P-type well TPW212and contains all the EEPROM configured memory cells5of the block210. The EEPROM configured memory cells5are arranged in rows and columns to form the sub-array of the block210. Each of the EEPROM configured memory cells5are formed of a floating-gate memory transistor MC and a floating-gate select transistor MS. The floating-gate select transistor MS of the EEPROM configured memory cells5have their drains commonly connected to a bit line270a, . . . ,270kassociated with a column on which the EEPROM configured memory cells5are placed. The source of the floating-gate select transistor MS is commonly connected to the drain of the floating-gate memory transistor MC. The sources of the floating-gate memory transistors MC of adjacent pairs of rows of the EEPROM configured memory cells5are connected to one source line135a, . . . ,135m. The source lines135a, . . . ,135mare connected externally to the array to receive the appropriate source biasing voltages for reading, programming, and erasing selected EEPROM configured memory cells5. The control gates of the floating-gate memory transistors MC are connected to the word lines275a, . . . ,275m. The word lines275a, . . . ,275mare connected to the row decoder220ofFIG. 4. The block210divided into pages215a, . . . ,215m. The page215a, . . . ,215mbeing groupings of the EEPROM configured memory cells5having their control gates connected commonly to a word line (WL0) of the word lines275a, . . . ,275m. The control gates of the floating-gate select transistors MS are connected to the select gate lines280a, . . . ,280m. The select gate lines280a, . . . ,280mare commonly connected to the select gate decoder240ofFIG. 4to received the activation signals to turn on the selected floating-gate select transistors MS for reading, programming, erasing and verifying selected floating-gate memory transistors MC.

FIG. 6ais a schematic diagram of a representative row decoder220of the nonvolatile memory device ofFIG. 4. Each row decoder220is partitioned into block decoders230a, . . . ,230m. The number of block decoders230a, . . . ,230min each row decoder220is equal to the number of blocks210a, . . . ,210mofFIG. 4. the logic gate310a, . . . ,310m(an AND gate in this embodiment) receives the block address320of the row address285ofFIG. 4, decodes the block address320to select which of the block row decoders230a, . . . ,230mis to be activated for reading, programming, or erasing. The output of the logic gate310a, . . . ,310mis the block select signal RXD [0]312a, . . . , RXD [m]312mthat is the input to an input to the level shift circuit315a, . . . ,315m. The level shift circuit315a, . . . ,315mreceives the power supply voltage levels325that are used to shift the lower voltage logic level of the block select signal RXD [0]312a, . . . , RXD [m]312mto the levels required for reading, programming, and erasing. The outputs of the level shift circuit315a, . . . ,315mare the high voltage block select signals XD330a, . . . ,330mand XDB332a, . . . ,332mthat are applied to the row decode circuit340a, . . . ,340m.

The row decode circuits340a, . . . ,340mprovide the appropriate voltage levels for transfer to the rows of the word lines275a, . . . ,275mof the selected block210a, . . . ,210mofFIG. 4. The voltage levels applied to row decode circuit340a, . . . ,340mare provided by the high voltage power supply voltage lines335. Each high voltage power supply voltage lines XT[0:1]335is associated with one of the word lines275a, . . . ,275mand is set according to the operation (read, program, erase, or verify) to be executed and are discussed hereinafter. The row decode circuits340a, . . . ,340mhave the row pass devices formed of the high voltage PMOS transistors341a, . . . ,341mand the high voltage NMOS transistors342a, . . . ,342mconnected pair-wise in parallel. The gates of the PMOS transistors341a, . . . ,341mare each connected to one of the high voltage out of phase block select signals XDB332a, . . . ,332m. The gates of the NMOS transistors342a, . . . ,342mare each connected to one of the in-phase block select signals XD330a, . . . ,330m. The sources of the PMOS transistors341a, . . . ,341mand the drains of the NMOS transistors342a, . . . ,342mare connected to the high voltage power supply voltage lines XT[0:1]335associated with one of the word lines275a, . . . ,275m. The drains of the PMOS transistors341a, . . . ,341mand the sources of the NMOS transistors342a, . . . ,342mare connected to the drain high voltage pass transistors343a, . . . ,343massociated with one of the word lines275a, . . . ,275m. The drains of the PMOS transistors341a, . . . ,341mand the sources of the NMOS transistors342a, . . . ,342mare further connected to the drain of the NMOS transistors343a, . . . ,343m. The gate of the NMOS transistors343a, . . . ,343mis connected to the out of phase block select signals XDB332a, . . . ,332mand the sources of the NMOS transistors343a, . . . ,343mare connected to the ground reference voltage source (0.0). For the row decoders230a, . . . ,230mof the unselected block210a, . . . ,210m, the level shift circuit315a, . . . ,315mare deactivated and the out of phase block select signals XDB332a, . . . ,332mare set to turn on the NMOS transistors343a, . . . ,343mto set the drains of the NMOS transistors343a, . . . ,343mto the voltage level of the ground reference voltage source (0.0).

FIG. 6bis a schematic diagram of select gate decoder240of the nonvolatile memory device ofFIG. 4. Each select gate decoder240is partitioned into a block select gate decoders245a,245b, . . . ,245m. The number of block select gate decoders245a,245b, . . . ,245min each select gate decoder425is equal to the number blocks210a, . . . ,210min the array205ofFIG. 4. The logic gate410a, . . . ,410m(an AND gate in this embodiment) receives the block address420of the row address285ofFIG. 4, decodes the block address420to select which of the block select gate decoders245a, . . . ,245mis to be activated for reading, programming, or erasing. The output of the logic gate410a, . . . ,410mis the block select signal RXD [0]412a, . . . , RXD [m]412mthat is the input to an input to the level shift circuit415a, . . . ,415m. The level shift circuit415a, . . . ,415mreceives the power supply voltage levels425that are used to shift the lower voltage logic level of the block select signal RXD [0]412a, . . . , RXD [m]412mto the levels required for reading, programming, and erasing. The outputs of the level shift circuit415a, . . . ,415mare the high voltage block select signals XD330a, . . . ,330mand XDB432a, . . . ,432mthat are applied to the row decode circuit440a, . . . ,440m.

The row decode circuits440a, . . . ,440mprovide the appropriate voltage levels for transfer to the rows of the select gate lines280a, . . . ,280mof the selected block210a, . . . ,210mofFIG. 4. The voltage levels applied to row decode circuit440a, . . . ,440mare provided by the high voltage power supply voltage lines435. Each high voltage power supply voltage lines435is associated with one of the select gate lines280a, . . . ,280mand is set according to the operation (read, program, erase, or verify) to be executed and are discussed hereinafter. Each of the row decode circuits440a, . . . ,440mhave the row pass devices formed of the high voltage PMOS transistors441a, . . . ,441mand the high voltage NMOS transistors442a, . . . ,442mconnected pair-wise in parallel. The gates of the PMOS transistors441a, . . . ,441mare each connected to one of the high voltage out of phase block select signals XDB432a, . . . ,432m. The gates of the NMOS transistors442a, . . . ,442mare each connected to one of the in-phase block select signals XD330a, . . . ,330m. The sources of the PMOS transistors441a, . . . ,441mand the drains of the NMOS transistors442a, . . . ,442mare connected to the high voltage power supply voltage line435associated with one of the select gate lines280a, . . . ,280m. The drains of the PMOS transistors441a, . . . ,441mand the sources of the NMOS transistors442a, . . . ,442mare connected to the drain high voltage pass transistors443a, . . . ,443massociated with one of the select gate lines280a, . . . ,280m. The drains of the PMOS transistors441a, . . . ,441mand the sources of the NMOS transistors442a, . . . ,442mare further connected to the drain of the NMOS transistors443a, . . . ,443m. The gate of the NMOS transistors443a, . . . ,443mis connected to the out of phase block select signals XDB432a, . . . ,432mand the sources of the NMOS transistors443a, . . . ,443mare connected to the ground reference voltage source (0.0). For the select gate decoders245a, . . . ,245mof the unselected block210a, . . . ,210m, the level shift circuit415a, . . . ,415mare deactivated and the out of phase block select signals XDB432a, . . . ,432mare set to turn on the NMOS transistors443a, . . . ,443mto set the drains of the NMOS transistors443a, . . . ,443mto the voltage level of the ground reference voltage source (0.0).

FIG. 7is a schematic diagram of the level shifter circuits315a, . . . ,315mand415a, . . . ,415mrespectively of the row decoder ofFIG. 6aand the select gate decoder ofFIG. 6b. Referring now toFIG. 7, the level shifter circuit515has two sub-level-shifter circuits570and580to translate the low voltage level of the block select signal RXD512to a voltage level of a positive high voltage power source VPX527. The voltage translation maintains the drain to source breakdown voltage BVDSS that is less than ±10V such that special high voltage devices are not required for the circuitry of the nonvolatile memory device200ofFIG. 4. The first level shift circuit570has pair of cross connected PMOS transistors571and572that have their sources and bulk regions connected to the positive high voltage power source VPX527. The drain of the PMOS transistor571is connected to the gate of the PMOS transistor572and the drain of the PMOS transistor572is connected to the gate of the PMOS transistor571. The drain of the PMOS transistors571is connected to the drain of the NMOS transistor575and the drain of the PMOS transistors572is connected to the drain of the NMOS transistor577. The gate of the NMOS transistor575is connected to receive the block select signal RXD512. The block select signal RXD512is connected to the input of the inverter576. The output of the inverter576is connected to the gate of the NMOS transistor577. The sources of the NMOS transistors575and577are connected to the ground reference voltage source (0.0).

The output nodes573and574of the first level shift circuit570are the input nodes of the second level shift circuit580. The second level shift circuit580has a pair of PMOS transistors581and582that have their sources and bulk regions connected to the high voltage power supply VPX527. The drain of the PMOS transistor581is connected to the drain of the NMOS transistor585and the source of the PMOS transistor583. The drain of the PMOS transistor582is connected to the drain of the NMOS transistor586and the source of the PMOS transistor584. The output node573of the first level shift circuit570is connected to the gate of the PMOS transistor581and the output node574of the first level shift circuit570is connected to the gate of the PMOS transistor582. The sources of the NMOS transistors585and586are connected to the negative high voltage source VNX526. The drains of the PMOS transistors583and584are connected to the drain of the NMOS transistor587. The source of the NMOS transistor587is connected to the ground reference voltage source. The gate of the NMOS transistor587is connected to the negative power supply enable signal ENVNX528. The out-of-phase block select signal XDB533is at the junction of the connection of the drains of the PMOS transistors581and583and the NMOS transistor585. The in-phase block select signal XD532is at the junction of the connection of the drains of the PMOS transistor582and584and the NMOS transistor586.

The first sub-level shifter circuit570receives the low voltage logic signal of the block select signal RXD512and generates the high voltage block select signal XD532and XDB533. The two sub-level-shifter circuits570and580, as designed, provide the positive and negative very high voltages and yet not exceed the drain-to-source breakdown voltage of the transistors of the two sub-level-shifter circuits570and580. The negative power supply enable signal ENVNX528selectively activates the NMOS transistor587to provide the appropriate ground reference voltage level to allow the in-phase block select signal XD532and the out-of-phase block select signal XDB533to be set to the voltage level of the negative high voltage source VNX526during a program and erase.

FIG. 8is flow chart for the method for operating the nonvolatile memory device200ofFIG. 4.FIG. 9is flow chart of the method for erasing and erase verifying a page, block, or chip of the nonvolatile memory device200ofFIG. 4.FIG. 10is flow chart of the method for programming and program verifying a page of the nonvolatile memory device200ofFIG. 4. Refer now toFIGS. 4-11,12a, and12bfor a discussion of the operating voltage levels required for the reading, programming, erasing, and verification of the nonvolatile memory device200. The method begins by determining (Box600) if the operation is an erase. If the operation is an erase operation, the erase is determined (Box605) to be a page, block, or chip erase. If the operation is to be a page erase, the page to be erased is selected (Box610) and the page is erased (Box620). The voltage levels for erasing a page of the array205of EEPROM configured memory cells5are shown inFIG. 11The word lines275U of the unselected blocks410U of the selected chips are set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V as coupled from the P-type well TPW212. The P-type well TPW212of the selected chip set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. The selected word line275S of the selected block is set to a very high positive erase voltage is from approximately +8.0V to approximately +10.0V. The unselected word line275SU in the selected block410S is set to the approximately the voltage level of the ground reference voltage source (0.0V). The selected bit line270S is set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V. The selected and unselected select gate line280S are set to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V.

To establish the page erase values as just described the row decoders230a,230b, . . . ,230mhave voltage levels described inFIG. 12aand the select gate decoders245a,245b, . . . ,245mhave voltage levels described inFIG. 12b. The selected word line275S must be set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the unselected word lines275SU of the selected block are set to the approximately the voltage level of the ground reference voltage source (0.0V). The unselected word lines275U of the unselected blocks are coupled to the very high negative erase voltage is from approximately −8.0V to approximately −10.0V coupled from the P-type well TPW212. The selected select gate line280S, unselected select gate lines280SU of the selected block, and unselected select gate lines280U of the unselected blocks must be set to the very high negative erase voltage is from approximately −10.0V to approximately −8.0V. To accomplish these levels as shown inFIGS. 12aand12b, the row decoders275a,275b, . . . ,275nof the selected blocks410S have their selected high voltage power supply voltage line XT335S associated with the selected word line275S set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V to be fed through the row decode circuit340a, . . . ,340nand the PMOS high voltage isolators350a, . . . ,350nto the selected word line275. The unselected high voltage power supply voltage line335U associated with the selected word line275SU set to the voltage level of the ground reference voltage level to be fed through the row decode circuit340a, . . . ,340nand the PMOS high voltage isolators350a, . . . ,350nto the unselected word line275SU. The voltage level of the selected in-phase block select signals XD330S, indicating that a block210S is selected, is set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the out-of-phase block select signals XD330U, indicating that the unselected blocks410U are unselected, is set to approximately the voltage level of the ground reference voltage source (0.0V) to be coupled from the row decode circuit340a, . . . ,340nthrough the PMOS high voltage isolators350a, . . . ,350msuch that the unselected word lines275U are coupled to the very high negative erase voltage that is from approximately −8.0V to approximately −10.0V from the P-type well TPW212. The N-type wells352S of the selected block410S is connected to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V to avoid voltage breakdown in the PMOS high voltage isolators350a, . . . ,350mand the N-type well switch355a, . . . ,355m. The N-type wells352U of the selected block410U is connected to the voltage level of the ground reference voltage source (0.0V).

To transfer the very high positive erase voltage present on the selected high voltage power supply voltage line XT335S to the selected word line275S, the PMOS high voltage isolators350a, . . . ,350mare activated with the isolation signal ISOB366is set to the voltage level of the ground reference voltage source (0.0V). The out of phase read signal RDB364, positive high voltage power source VPX327, and the positive N-well biasing voltage source VP1362are set to the very high positive erase voltage is from approximately +8.0V to approximately +10.0V to set the selected word line275S to the voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V. The high negative voltage source VNX326, negative power supply enable signal ENVNX328are set to the voltage level of the ground reference voltage source (0.0V) to set the unselected word lines275SU of the selected block410S to approximately the voltage level of the ground reference voltage source (0.0V).

The select gate decoders280a,280b, . . . ,280mof the selected blocks410S have their selected high voltage power supply voltage line XT435S associated with the selected select gate line280S, the unselected high voltage power supply voltage line XT435U associated with the unselected select gate lines280SU of the selected block, and unselected select gate lines280U of the unselected blocks are set to the voltage level of the very high negative erase voltage to be fed through the row decode circuit440a, . . . ,440mand the PMOS high voltage isolators450a, . . . ,450mto the selected select gate line280S and unselected select gate lines280SU and280U. The voltage level of the selected in-phase block select signals XD430S and the voltage level of the out-of-phase block select signals XD430U are set to the very high negative erase voltage to be coupled from the row decode circuit440a, . . . ,440mthrough the PMOS high voltage isolators450a, . . . ,450msuch that the selected select gate line280S and the unselected select gate lines280SU and280U are set to the very high negative erase voltage that is from approximately −8.0V to approximately −10.0V. The N-type wells452S of the selected block410S and the N-type wells452U of the selected blocks410U are connected to the voltage level of the ground reference voltage source (0.0V).

To transfer the very high negative erase voltage present on the selected high voltage power supply voltage lines XT435S,435SU, and435U to the selected select gate line280S, the PMOS high voltage isolators450a, . . . ,450mare activated with the isolation signal ISOB466is set to a very high negative select level of approximately −12V. The out of phase read signal RDB464is set to the very high positive erase voltage. The positive high voltage power source VPX427is set to the voltage level of the ground reference voltage source (0.0V) and the high negative voltage source VNX426is set to the very high negative erase voltage level. The negative power supply enable signal ENVNX428is set to the voltage level of the power supply voltage source VDD and set the selected gate lines280S and the unselected select gate lines280SU and280U of the selected and unselected blocks to very high negative erase voltage.

Returning now toFIG. 9, after the completion of the page erase operation (Box620), the page erase verify operation is executed (Box625) to determine if the erase has been successfully accomplished. The voltage levels for the page erase verification for the array205of the EEPROM configured memory cells5are shown inFIG. 11. Referring toFIG. 11, the selected word line275S and the unselected word lines275SU of the selected blocks410S and the unselected word lines275U of the unselected blocks410U are set to the lower boundary of the threshold voltage Vt1L that is approximately +4.0V. The selected bit line270S is pre-charged to the second read biasing voltage that is approximately the voltage level of the power supply voltage source VDD less a threshold voltage Vt of an NMOS transistor. The pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully erased and has a threshold voltage level is less than the lower boundary of the erased threshold voltage level Vt1L. If the EEPROM configured nonvolatile memory cells are erased, the pre-charged level of the second read biasing voltage will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells is greater than the lower boundary of the erased threshold voltage level Vt1L. The selected select gate line280S is set to the high read select voltage HV″ that is approximately +5.0V and the unselected select gate lines are set a voltage level of the voltage level of the ground reference voltage source (0.0V).

Referring toFIG. 12ato discuss the voltage levels of the row decoders230a,230b, . . . ,230m, the selected word line275S and the unselected word lines275SU and275U are set to the lower boundary of the erase threshold voltage level Vt1L by setting selected high voltage power supply voltage line XT335S and the unselected high voltage power supply voltage line XT335SU and335U to the voltage level of the lower boundary of the erase threshold voltage level Vt1L. The voltage level of the selected and unselected in-phase block select signals XD330S and330U, the positive high voltage power source VPX327, and the selected and unselected negative N-well biasing voltage lines NW352aand NW352U are set to lower boundary of the erase threshold voltage Vt1L to pass the lower boundary of the erase threshold voltage level Vt1L to the selected word line275S. The out of phase read signal RDB364, the first high negative voltage source VNX326, and the negative power supply enable signal ENVNX328are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB366is set to a first negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the lower boundary of the erase threshold voltage level Vt1L from the selected and unselected high voltage power supply voltage line XT335S and XT335U to the selected word line275S and the unselected word lines275SU and275U.

Returning toFIG. 11, the selected bit lines BL270S for the selected columns are pre-charged to the pre-charge voltage level of the power supply voltage source VDD less the threshold voltage Vt (VDD−Vt) for sensing the status of the selected floating-gate memory transistor MC of the EEPROM configured memory cells5on the activated columns. The pre-charge voltage level (VDD−Vt) will be discharged to 0V when any of the floating-gate memory transistors MC have not been successfully erased to the lower boundary of the threshold voltage level Vt1L of the floating-gate memory transistor MC is lower than the lower boundary of the erased threshold voltage level. If the floating-gate memory transistors MC are erased, the pre-charged level will be maintained when the threshold voltage of the floating-gate memory transistor MC is greater than the erased threshold voltage level Vt1L. The select gate lines280S for the selected block is set to the voltage level of the high read select voltage HV″ of approximately +5.0V to fully couple the pre-charged voltage level of second read biasing voltage that is the power supply voltage source VDD less the threshold voltage Vt (VDD−Vt) from the bit lines270a, . . . ,270kto the drains of the selected floating-gate memory transistors MC.

Referring toFIG. 12bto discuss the voltage levels of the select gate decoders245a,245b, . . . ,245m, the selected select gate line280S is set to the high read select voltage HV″ by setting selected high voltage power supply voltage line XT435S to the high read select voltage HV″. The unselected select gate lines280SU and280U are set to the voltage level of the ground reference voltage source (0.0V) by setting the unselected high voltage power supply voltage line XT435SU and435U to the voltage level of the ground reference voltage source (0.0V). The voltage level of the selected in-phase block select signals XD430S, selected and unselected negative N-well biasing voltage lines NW452S and NW452U, and the positive high voltage power source VPX427are set to the high read select voltage HV″. The unselected in-phase block select signals430U, negative high voltage power source VNX426, the out of phase read signal RDB464, and the negative power supply enable signal ENVNX428are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB466is set to a second negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the high read select voltage HV″ from the selected high voltage power supply voltage line XT435S to the selected select gate line280S. Further, the voltage levels, as described, fully pass voltage level of the ground reference voltage source (0.0V) from the unselected high voltage power supply voltage line XT435U to the unselected select gate lines280U.

Returning toFIG. 9, if the page erase verify (Box625) indicates the page erase (Box620) is not successful, a loop counter is tested (Box630) to assess that the maximum number of erasure trials is not exceeded. If the maximum number of erasure trials is not exceeded, the loop counter is incremented (Box635) and the page erase operation (Box620) is executed repetitively until the maximum number of erasure trials is exceeded and the nonvolatile memory device is declared as having failed (Box640) or the erasure is a success and the nonvolatile memory device is declared as having successfully been erased (Box645).

Return now toFIG. 9. If the operation is not a page erase but is determined (Box605) to be a block erase, the block to be erased is selected (Box615) and the block is erased (Box615). Referring now toFIGS. 11,12aand12b, the voltage levels for the block erase are identical to that of the page erase described above except that there are no unselected word lines275SU in the selected block410S. All the word lines275S are now selected for erasure and placed at the very high positive erase voltage level of from approximately +8.0V to approximately +10.0V to accomplish the block erase.

Returning now toFIG. 9, after the completion of the block erase operation (Box620), the block erase verify operation is executed (Box625) to determine if the block erase has been successfully accomplished. The block erase verify operation (Box625) is identical to the page erase verify. The selected and unselected word lines275S,275SU, and275U are set to a voltage level of the lower boundary of the erase threshold voltage Vt1L or approximately +4.0V for the single level cell program as shown inFIG. 12a.

Returning toFIG. 9, if the block erase verify (Box625) indicates that the block erase (Box620) was not successful, a loop counter is tested (Box630) to assess that the maximum number of erasure trials is not exceeded. If the maximum number of erasure trials is not exceeded, the loop counter is incremented (Box635) and the block erase operation (Box620) is executed repetitively until the maximum number of erasure trials is exceeded and the nonvolatile memory device is declared as having failed (Box640) or the erasure is a success and the nonvolatile memory device is declared as having successfully been erased (Box645).

If the operation is to be a chip erase, the chip is erased (Box625). Referring now toFIGS. 11,12aand12b, the voltage levels for the chip erase are identical to that of the page erase and block erase described above except that there are no unselected word lines275SU or275U. All the word lines275S are now selected for erasure and placed at the very high positive erase voltage level of from approximately +8.0V to approximately +10.0V to accomplish the chip erase.

Returning now toFIG. 9, after the completion of the chip erase operation (Box625), the chip erase verify operation is executed (Box630) to determine if the block erase has been successfully accomplished. The chip erase verify (Box625) is identical to the page erase verify. All the selected and unselected word lines275S,275SU, and275U are set to a voltage level of the lower boundary of the erase threshold voltage Vt1L.

If the chip erase verify (Box625) indicates that the block erase (Box620) was not successful, a loop counter is tested (Box630) to assess that the maximum number of erasure trials is not exceeded. If the maximum number of erasure trials is not exceeded, the loop counter is incremented (Box635) and the chip erase (Box620) operation is executed repetitively until the maximum number of erasure trials is exceeded and the nonvolatile memory device is declared as having failed (Box640) or the erasure is a success and the nonvolatile memory device is declared as having successfully been erased (Box645).

Returning now toFIG. 8, if the operation is determined (Box600) not to be an erase operation, the operation is determined (Box650) if it is a program operation. If the operation is determined (Box650) to be a page program operation (referring to FIG.10), data is loaded (Box655) to the data register and sense amplifier260and the page to be programmed is selected (Box660) to be transferred to the bit line270a, . . . ,270kthrough the activation of the data register and sense amplifier260. The floating-gate memory transistors MC of the selected page are then programmed with the voltage levels applied as shown inFIG. 11,12a, and12b. Referring toFIG. 11, the unselected word lines275U of the unselected blocks410U because the unselected row decode circuits340a, . . . ,340mare turned off and the unselected word lines275SU of the selected block410S are set to the voltage level of the ground level voltage source (0.0V). The selected word line275S is set to the high negative program voltage level that is from approximately −8.0V to approximately −10, which is somewhat less than the drain to source breakdown voltage BVDSS of the transistors of the row decoder220ofFIG. 4. The selected bit lines BL270S for the columns that are to be programmed are set to the high program voltage is approximately +5.0V. The unselected bit lines BL270U (the program inhibited) for the columns that are to remain erased are set to a voltage level of approximately the ground reference voltage source (0.0V) or alternately disconnected and allowed to float. The selected select gate line280S connected to the selected page is set to the high program select voltage of approximately 10.0V. The unselected select gate lines280U are set to the voltage level of the ground reference voltage source (0.0V). The source lines of the array205of EEPROM configured memory cells5, and the P-type well TPW212in which the array205of EEPROM configured memory cells5are formed is set to the voltage level of the ground reference voltage source (0.0V).

To establish the voltage levels as described for the programming inFIG. 11, the row decoder220has the voltage levels shown inFIGS. 12aand the select gate decoder has the voltage levels shown inFIG. 12b. Referring toFIG. 12a, to have the selected word line275S set to a high negative program voltage level that is from approximately −8.0V to approximately −10.0V, the selected high voltage power supply voltage line XT335S associated with the selected word line275S set to the very high negative program voltage level. To have the unselected word lines275SU set to the voltage level of the ground reference voltage source (0.0V), the unselected high voltage power supply voltage line XT335SU associated with the unselected word lines275SU set to the voltage level of the ground reference voltage source (0.0V). To have the unselected word lines275U of the unselected blocks disconnected and floating the selected row decode circuit340a, . . . ,340mare deactivated to disconnect the unselected word lines275U to be floating. The voltage level of the selected in-phase block select signals XD330S, indicating that a block410S is selected is set to approximately the voltage level of the ground reference voltage source (0.0V) such that the very high negative program voltage is coupled from the selected row decode circuit340a, . . . ,340nthrough the PMOS high voltage isolator350a, . . . ,350mto the selected word line275S. The voltage level of the out-of-phase block select signals XD330U, indicating that a block is unselected, is set to the very high negative program voltage to turn off all the voltages from the unselected high voltage power supply voltage line XT335U and XT335SU to the force unselected word line275SU and275U to be disconnected and allowed to float. The selected N-type well NW352S of the selected block and the N-type wells352U of the unselected blocks410U are connected to the voltage level of approximately the ground reference voltage source (0.0V). The isolation signal ISOB366is set to a very large program activation voltage level of approximately −12.0V to activate the PMOS high voltage isolators350a, . . . ,350mto transfer the very high negative program voltage to the selected word lines275S and the voltage level of the ground reference voltage source (0.0V) to the unselected word lines275SU and disconnecting the unselected word lines275U such that they are floating. The out of phase read signal RDB364is set to the very high negative program voltage. The positive high voltage power source VPX327is set to the voltage level of the ground reference voltage source (0.0V) and the negative high voltage power source VNX326is set to the very high negative program voltage. To enable the passage of the very high negative program voltage from the negative high voltage power source VNX326, the negative power supply enable signal ENVNX328is set to the voltage level of the power supply voltage source VDD.

Referring now toFIG. 12b, the selected select gate line280S is set to the very high positive program voltage that is from approximately +8.0V to approximately +10.0V. The unselected select gate lines280SU and280U are voltage level of the ground reference voltage source (0.0V). Further, the selected select gate lines280S is to be set to the voltage level of very high program voltage level of from approximately +8.0V to approximately +10.0V and the unselected select gate lines280S is to be set to the voltage level of approximately the ground reference voltage source (0.0V). To have the selected select gate line280S set to the very high program voltage level, the selected high voltage power supply voltage line XT435S associated with the selected select gate lines280S set to very high program voltage level. To have the unselected select gate lines280SU and280U set to the voltage level of the ground reference voltage source (0.0V), the unselected high voltage power supply voltage line XT435U associated with the unselected select gate lines280U set to the voltage level of the ground reference voltage source (0.0V). The voltage level of the selected in-phase block select signal XD430S, indicating that a block is selected is set to approximately the high program select voltage of approximately +10.0V. The voltage level of the unselected in-phase block select signals XD430S, indicating that a block is selected, are set to the voltage level of the ground reference voltage source (0.0V). The selected N-type well NS452S of the selected block and the N-type wells452U of the unselected blocks is set to the high program select voltage of approximately +10.0V. The isolation signal ISOB466is set to the voltage level of a negative pass gate activation voltage level of approximately −2.0V to activate the PMOS high voltage isolators450a, . . . ,450mto transfer the very high positive program voltage to the selected select gate lines280S and the voltage level of the ground reference voltage source (0.0V) to the unselected select gate lines280SU and280U. The out of phase read signal RDB464is set to the voltage level of the ground reference voltage source and the positive high voltage power source VPX427is set to the very high positive program voltage that is from approximately +8.0V to approximately +10.0V. The negative high voltage power source VNX426is set to the very high negative program voltage. To enable the passage of the very high negative program voltage from the negative high voltage power source VNX426, the negative power supply enable signal ENVNX428is set to the voltage level of the ground reference voltage source.

Returning now toFIG. 10, after the completion of the program operation (Box665), the page program verify operation is executed (Box670) to determine if the program has been successfully accomplished. If the program operation (Box665) is not successful, a loop counter is tested (Box675) to assess that the maximum number of program trials is not exceeded. If the maximum number of program trials is not exceeded, the loop counter is incremented (Box680) and the page program operation (Box665) is executed repetitively until the maximum number of program trials is exceeded and the nonvolatile memory device is declared as having failed (Box685) or the programming is a success and the nonvolatile memory device is declared as having successfully been erased (Box690).

Referring toFIG. 11, the program verify operation (Box670) is essentially the same as the erase verify (Box630) ofFIG. 9except the selected word line275S is set to the upper boundary of the threshold voltage level Vt0H to evaluate the programmed threshold voltage of the selected NMOS floating gate transistors Mc.

FIG. 13is a plot of threshold voltage for the floating gate memory transistor in the two floating-gate transistor EEPROM configured memory cell embodying the principles of the present invention vs. program time for hot hole injection. In the example illustrated the selected bit lines BL270S for the columns that are to be programmed are increased from the high program voltage that is approximately +5.0V to a voltage of approximately +6.0V to activate a Fowler-Nordheim hot-hole injection phenomena. It can be seen that the threshold voltage Vt of the floating-gate memory transistor MC of the EEPROM configured memory cells5are able to be programmed to a lower voltage level700of approximately +1.0V in approximately 300 μs. The setting of the selected bit lines BL270S for the columns that are to be programmed to the higher program voltage is approximately +6.0V allows the Fowler-Nordheim hot-hole injection phenomena or maintaining the high program voltage of approximately +5.0V allows a slower Fowler-Nordheim drain edge injection. The program current for each cell in these examples is approximately 1.0 nA. This permits a page program that is similar to that of a NAND flash nonvolatile memory page program operation.

Returning now toFIG. 8, if the operation is determined (Box650) not to be a program operation, the operation is a read operation and the read operation is executed (Box695). The selected page is then read with the voltage levels applied as shown inFIG. 11,12a, and12b. Referring toFIG. 11, the selected word line275S and the unselected word lines275SU of the selected blocks and the unselected word lines275U of the unselected blocks are set to the read voltage threshold VR that is approximately the level of the power supply voltage source VDD. The selected bit line270S is set to the first read voltage level of approximately +1.0V. The selected select gate line280S is set to the high read select voltage HV″ that is approximately +5.0V and the unselected select gate lines280S and280SU are set a voltage level of the voltage level of the ground reference voltage source (0.0V).

Referring toFIG. 12ato discuss the voltage levels of the row decoders230a,230b, . . . ,230n, . . . ,245n, the selected word line275S and the unselected word lines275SU and275U are set to the read voltage threshold VR by setting selected high voltage power supply voltage line XT335S and the unselected high voltage power supply voltage line XT335SU and335U to the voltage level of the read voltage threshold VR. The voltage level of the selected and unselected in-phase block select signals XD330S and330U, the positive high voltage power source VPX327, and the selected and unselected negative N-well biasing voltage lines NW352S and NW352U are set to the voltage level of the power supply voltage source VDD to pass the read voltage threshold VR to the selected word line275S. The out of phase read signal RDB364, the first high negative voltage source VNX326, and the negative power supply enable signal ENVNX328are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB366is set to a first negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the read voltage threshold VR from the selected and unselected high voltage power supply voltage line XT335S and XT335U to the selected word line275S and the unselected word lines275SU and275U.

Returning toFIG. 11, the selected bit lines BL270S for the selected columns are pre-charged to the first read voltage level of approximately +1.0V for sensing the status of the selected floating-gate memory transistor MC of the EEPROM configured memory cells5on the activated columns. The selected select gate lines280S for the selected block is set to the voltage level of the high read select voltage HV″ of approximately +5.0V to fully couple the read voltage threshold VR from the bit lines270a, . . . ,270kto the selected floating-gate memory transistors MC.

Referring toFIG. 12bto discuss the voltage levels of the select gate decoders245a,245b, . . . ,245m, the selected select gate line280S is set to the high read select voltage HV″ by setting selected high voltage power supply voltage line XT435S to the high read select voltage HV″. The unselected select gate lines280SU and280U are set to the voltage level of the ground reference voltage source (0.0V) by setting the unselected high voltage power supply voltage line XT435SU and435U to the voltage level of the ground reference voltage source (0.0V). The voltage level of the selected in-phase block select signals XD430S, selected and unselected negative N-well biasing voltage lines NW452n and NW452U, and the positive high voltage power source VPX427are set to the high read select voltage HV″. The unselected in-phase block select signals430U, negative high voltage power source VNX426, the out of phase read signal RDB464, and the negative power supply enable signal ENVNX428are set to the voltage level of the ground reference voltage source (0.0V). The isolation signal ISOB466is set to a second negative read activation voltage level of approximately −5.0V. These voltage levels, as described, fully pass the lower boundary of the high read select voltage HV″ from the selected high voltage power supply voltage line XT435S to the selected select gate line280S. Further, the voltage levels, as described, fully pass voltage level of the ground reference voltage source (0.0V) from the unselected high voltage power supply voltage line XT435U to the unselected select gate lines280U and280SU.

Refer toFIGS. 14 and 15for a summary of the erase and program operations of the floating-gate memory transistor MC of the EEPROM configured memory cells5ofFIG. 5within the EEPROM memory array205ofFIG. 4.FIG. 14is a timing diagram for erasing and erase verification of a block of the nonvolatile memory device ofFIG. 5. During the erase operation620between the time τ0and the time τ1. The voltage levels are as described above forFIGS. 11,12a, and12bto initiate an Fowler-Nordheim channel tunneling phenomena to inject more electrons to the floating-gate to increase the threshold voltage Vt of the floating-gate memory transistor MC of the EEPROM configured memory cells5to greater than the lower boundary of the threshold voltage Vt1L that is approximately +4.0V.

The erase verify operation625has two segments a pre-charge period626and the verification period627. The pre-charge period626is between the time τ1and the time τ2. At this time, the selected bit line270S is pre-charged to the second read biasing voltage that is approximately the voltage level of the power supply voltage source VDD less a threshold voltage Vt of an NMOS transistor. In the verification time between the time τ2and the time τ3, the pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cells have not been successfully erased and has a threshold voltage level that is less than the lower boundary of the erased threshold voltage level Vt1L. If the EEPROM configured nonvolatile memory cells5are erased, the second read biasing voltage will be maintained when the threshold voltage of the erased EEPROM configured nonvolatile memory cells5is greater than the lower boundary of the erased threshold voltage level Vt1L. The Y-pass gate and sense amplifier260bofFIG. 4determines if the floating-gate memory transistor MC of the EEPROM configured memory cells5are erased and has achieved the threshold voltage level representing the datum of a logical “1”. If the floating-gate memory transistor MC of the EEPROM configured memory cells5is not erased, the data register and sense amplifier260ofFIG. 4determines that the floating-gate memory transistor MC of the EEPROM configured memory cells5has not achieved the threshold voltage level representing a datum of logical “1”. The voltage levels as shown are established as described above forFIGS. 11,12a, and12b.

FIG. 15is a timing diagram for programming and program verification of a block of the nonvolatile memory device ofFIG. 5. During the program operation665between the time τ0and the time τ1. The voltage levels are as described above forFIGS. 11,12a, and12bto initiate an Fowler-Nordheim drain edge tunneling phenomena to extract electrons to the floating-gate to decrease the threshold voltage Vt of the floating-gate memory transistor MC of the selected EEPROM configured memory cells5on the selected bit lines270S to less than the upper boundary of the threshold voltage Vt0H that is approximately +1.0V. For the floating-gate memory transistor MC of the unselected EEPROM configured memory cells5on the unselected bit lines270U, the program inhibit voltage level that is the ground reference voltage source is applied to the unselected bit lines270U.

The program verify operation670has two segments a pre-charge period671and the verification period672. The pre-charge period671is between the time τ1and the time τ2. At this time, the selected bit lines270S are pre-charged to approximately the voltage level of the power supply voltage source VDD less a threshold voltage Vt of an NMOS transistor. In the verification time between the time τ2and the time τ3, the pre-charged level of the second read biasing voltage is discharged to approximately 0.0V when the memory cell has not been successfully programmed and has a threshold voltage level that is less than the upper boundary of the programmed threshold voltage level. If the EEPROM configured nonvolatile memory cells5are not programmed, the pre-charged level will be maintained when the threshold voltage of the programmed EEPROM configured nonvolatile memory cells5is greater than the upper boundary of the programmed threshold voltage level. The data register and sense amplifier260ofFIG. 4determines if the floating-gate memory transistor MC of the EEPROM configured memory cells5are programmed and has achieved the threshold voltage level representing the datum of a logical “0”. If the floating-gate memory transistor MC of the EEPROM configured memory cells5is not programmed, the data register and sense amplifier260ofFIG. 4determines that the floating-gate memory transistor MC of the EEPROM configured memory cells5has not achieved the threshold voltage level representing a datum of logical “0”. The voltage levels as shown are established as described above forFIGS. 11,12a, and12b.

The description of the nonvolatile memory device200ofFIG. 4incorporating EEPROM configured memory cells having a floating-gate memory transistor and a floating gate select transistor. In other embodiments, the EEPROM configured memory cells include charge trapping transistor formed with a layers of silicon, a first layer of silicon dioxide, silicon nitride, a second layer of silicon oxide and a layer of polycrystalline silicon commonly referred to as a SONOS charge trapping transistor to form a charge trapping memory transistor and a charge trapping select transistor within the EEPROM configured memory cells to embody the principles of this invention. Further, as shown inFIG. 14, other voltage levels may be used for reading, programming, erasing and verifying the EEPROM configured memory cells in other embodiments and still be in keeping with the principles of this invention. One key aspect of the principles of this invention is that the structure of the row decoder220, the select gate decoder240, and the data register and Sense Amplifier260ofFIG. 4provide the operating voltages voltage levels that do not exceed the drain-to-source breakdown voltage of the transistors used to construct the row decoder220, the select gate decoder240, and the data register and Sense Amplifier260ofFIG. 4.