Semiconductor package structure and method for manufacturing the same

A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

This application claims the benefit of People's Republic of China application Serial No. 201410341647.0, filed Jul. 17, 2014, the subject matter of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

The disclosure relates to a semiconductor package structure and a method for manufacturing the same. More particularly, the disclosure relates to a thinned semiconductor package structure and a method for manufacturing the same.

2. Description of the Related Art

During the development of the consumer electronics such as mobile phones and the like, higher performance, higher power efficiency, larger density and lower thickness have been pursued all the time. Among these goals, the thickness decreasing issue has been limited by the thickness of the electronic components in the consumer electronics. For example, for an application processor or a DRAM having a package-on-package structure, the lowest thickness may be the sum of the thickness of the two stacked packages, wherein the thickness of each package typically equals to the sum of the thickness of the substrate and the thickness of the die/dies formed thereon.

SUMMARY

In this disclosure, a thinned semiconductor package structure and a method for manufacturing the same are provided.

According to some embodiment, the semiconductor package structure comprises a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

According to some embodiment, the method for manufacturing a semiconductor package structure comprises the following steps. First, a substrate is attached to a carrier. The substrate has a first side, a second side and an opening extending from the first side to the second side. Then, a die stack of n die(s) is attached to the carrier through the opening, wherein n≧1. The thickness of the substrate is substantially the same as the thickness of the die stack.

DETAILED DESCRIPTION

Now the description is directed to said semiconductor package structure and a method for manufacturing the same.FIG. 1A-FIG. 9schematically illustrate a method for manufacturing said semiconductor package structure according to one embodiment. For clarity, parts of the elements may be removed from the drawings.

Referring toFIGS. 1A and 1B, a substrate102is provided.FIG. 1Ashow the top view of the substrate102, andFIG. 1Bshows a cross-sectional view of the substrate102taken from the line B-B′ shown inFIG. 1A. The substrate102has a first side102a, a second side102band an opening102oextending from the first side102ato the second side102b. The substrate102may be a wafer or a panel. In some example, the substrate102comprises Si, glass or the like. The substrate102may comprise redistribution layers104and via106connecting the redistribution layers104. The redistribution layers104may be formed of Cu, Al, W or composition thereof.

Referring toFIG. 2, a die stack108of n die(s) is provided, wherein n≧1. In the example ofFIG. 2, two dies are shown to compose a die stack108. All or part of the dies of the die stack108may be the same, or all of the dies of the die stack108may be different. In other examples, only one die or more than two dies may be comprised in the die stack108. In some examples, one or more dies in the die stack108comprise through silicon vias (TSVs).

Here, the thickness of the substrate102or the thickness of the die(s) of the die stack108may be adjusted such that the thickness of the substrate102is substantially the same as the thickness of the die stack108. For example, the thickness of the die(s) may be adjusted by being thinned from the back surface (i.e. the surface opposite to the surface having the integrated circuits and interconnects).

Referring toFIG. 3, first, the substrate102is attached to a carrier110. Then, the die stack108is attached to the carrier110through the opening102oof the substrate102. In some examples, an alignment step may be optionally carried out. The substrate102and the die stack108may be temporarily mounted on the carrier110by an adhesive layer112. Here, the thickness of the substrate102is substantially the same as the thickness of the die stack108.

Referring toFIG. 4, a first adhesive insulating layer114may be formed on the first side102aof the substrate102and between the substrate102and the die stack108. The first adhesive insulating layer114may comprise a light-sensitive adhesive, such as benzocyclobutene (BCB), polybenzoxazole (PBO) or the like. The first adhesive insulating layer114may provide electrical insulation to the circuit layer(s) (such as first circuit layers118and122) formed in the following steps. The first adhesive insulating layer114may be patterned.

Referring toFIG. 5, the carrier110is removed. Then, a second adhesive insulating layer116may be formed on the second side102bof the substrate102. The second adhesive insulating layer116may comprise the same material as the first adhesive insulating layer114, such as a light-sensitive adhesive. The second adhesive insulating layer116may provide electrical insulation to the circuit layer(s) (such as second circuit layers120and124) formed in the following steps. The second adhesive insulating layer116may be patterned.

Referring toFIG. 6, a first circuit layer118may be formed on the first side102aof the substrate102, and a second circuit layer120may be formed on the second side102bof the substrate102. The first circuit layer118and the second circuit layer120may be formed by semi-additive metallization process. The semi-additive metallization process may exemplarily comprise: forming openings in an insulating layer, such as the first adhesive insulating layer114or the second adhesive insulating layer116, (see the description with respect toFIG. 5); forming a thin conformal metal layer on the surface of the insulating layer and on the sidewalls and bottoms of the openings such as by electroless plating process; forming a patterned photo resist on the insulating layer, wherein the exposed region is the region where metal lines to be formed; plating the exposed region to form the metal lines and filling the openings in the insulating layer; removing the patterned photo resist; and removing the thin conformal metal layer that had been covered by the patterned photo resist.

Referring toFIG. 7, another first circuit layer122may be formed on the first circuit layer118, and another second circuit layer124may be formed on the second circuit layer120. The first circuit layer122and the second circuit layer124may be formed by semi-additive metallization process. The first circuit layer122comprises pads126. The second circuit layer124comprises pads128.

Referring toFIG. 8, a first passivation layer130may be formed on the first circuit layer122, and a second passivation layer132may be formed on the second circuit layer124. The first passivation layer130exposes the pads126of the first circuit layer122. The second passivation layer132exposes the pads128of the second circuit layer124.

Referring toFIG. 9, a die134may be provided on the first passivation layer130. In the example ofFIG. 9, three dies134are exemplarily provided. The die134is electrically connected to the pads126of the first circuit layer122. The die134may be electrically connected to the pads126of the first circuit layer122by wire bonding, ball grid array (BGA) bonding, flip chip bonding or the like. In the example ofFIG. 9, the die134and the pads126are connected by wire bonding. In the example ofFIG. 9, solder balls is formed on the pads128of the second circuit layer124for electrical connection. However, other connecting method, such as flip chip bonding, may be used.

Then, a step of cutting the substrate102may be carried out for singulation. It is to be noted that the cutting step may be incorporated into any steps after the formation of the first adhesive insulating layer114.

Through the method described above, the die stack108is disposed in the opening102oof the substrate102. In addition, the thickness of the substrate102is adjusted to be substantially the same as the die stack108. As such, the thickness may be further decreased. The decreased thickness equals to at least the thickness of a substrate. Compared to a conventional package on package structure, a package on package structure formed by the above method may be about 200 um thinner.

A semiconductor package structure100formed by the above method comprises a substrate102and a die stack108of n die(s), wherein n≧1. The substrate102has a first side102a, a second side102band an opening102oextending from the first side102ato the second side102b. The substrate102may be a wafer or a panel. In some example, the substrate102comprises Si, glass or the like. In some example, one of the n dies is different from another one of the n dies. The die stack108is disposed in the opening102o. The thickness of the substrate102is substantially the same as the thickness of the die stack108.

The semiconductor package structure100may further comprise a first adhesive insulating layer114and a second adhesive insulating layer116. The first adhesive insulating layer114is disposed on the first side102aof the substrate102and between the substrate102and the die stack108. The second adhesive insulating layer116is disposed on the second side102bof the substrate102. The first adhesive insulating layer114and the second adhesive insulating layer116may comprise a light-sensitive adhesive, such as BCB, PBO or the like.

The semiconductor package structure100may further comprise at least one first circuit layer118/122and at least one second circuit layer120/124. The at least one first circuit layer118/122is disposed on the first side102aof the substrate102. The at least one first circuit layer118/122comprises pads126. The at least one second circuit layer120/124is disposed on the second side102bof the substrate102. The at least one second circuit layer120/124comprises pads128.

The semiconductor package structure100may further comprise a first passivation layer130and a second passivation layer132. The first passivation layer130is disposed on the at least one first circuit layer118/122. The first passivation layer130exposes the pads126of the at least one first circuit layer118/122. The second passivation layer132is disposed on the at least one second circuit layer120/124. The second passivation layer132exposes the pads128of the at least one second circuit layer120/124.

The semiconductor package structure100may further comprise a die134. The die134is disposed on the first passivation layer130and electrically connected to the pads126of the at least one first circuit layer118/122. The die134may be electrically connected to the pads126by wire bonding, ball grid array bonding, flip chip bonding or the like. In some examples, solder balls may be formed on the pads128for electrical connection. In other examples, other connecting method, such as flip chip bonding, may be used.

In this embodiment, since the die stack108is disposed in the opening102oof the substrate102and the thickness of the substrate102is adjusted to be substantially the same as the die stack108, the thickness may be further decreased. As described above, compared to a conventional package on package, the semiconductor package structure100may be about 200 um thinner.