SENSOR ARRANGEMENT AND METHOD FOR PROVIDING A SENSOR SIGNAL

A sensor arrangement comprises a first capacitive sensor with a first and a second terminal, a second capacitive sensor with a first and a second terminal, a charge pump arrangement coupled to the first terminal of the first capacitive sensor and to the first terminal of the second capacitive sensor, and a differential output. The differential output comprises a first terminal coupled to the second terminal of the first capacitive sensor and a second terminal coupled to the second terminal of the second capacitive sensor. The first and the second capacitive sensor having opposite geometric orientation.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of and priority to European Patent Application No. 19155823.8, filed Feb. 6, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure is related to a sensor arrangement, to an apparatus comprising a sensor arrangement and a method for providing a sensor signal.

BACKGROUND

In some embodiments, a sensor arrangement may have a capacitive sensor which detects a parameter. The parameter to be detected by the capacitive sensor changes a capacitance value of the capacitive sensor. The parameter to be detected may be, for example, sound, noise, vibration and/or acceleration. The capacitive sensor may be realized as a microphone, for example as a micro-electro-mechanical-system microphone, abbreviated to MEMS microphone, or as an electret microphone.

SUMMARY

It is an object to provide a sensor arrangement, an apparatus with a sensor arrangement and a method for providing a sensor signal which increase the sensitivity for the detection of a parameter. These objects are achieved with the subject-matter of the independent claims. At least some further developments and embodiments are disclosed in the dependent claims.

In one implementation, a sensor arrangement comprises a first capacitive sensor with a first and a second terminal, a second capacitive sensor with a first and a second terminal, a charge pump arrangement coupled to the first terminal of the first capacitive sensor and to the first terminal of the second capacitive sensor, and a differential output having a first terminal coupled to the second terminal of the first capacitive sensor and having a second terminal coupled to the second terminal of the second capacitive sensor.

Advantageously, by the use of two capacitive sensors, a sensor signal at the differential output can be increased. The charge pump arrangement may be operable to provide a high bias voltage to the first and the second capacitive sensor. The high bias voltage also increases the sensor sensitivity.

In an embodiment, the first and the second capacitive sensor have an opposite geometric orientation.

In an embodiment, the first and the second capacitive sensor provide a first and a second sensor signal. Due to this opposite geometric orientation, the first and the second sensor signal are different. Advantageously, the sensor signal obtains a high value. In an embodiment, the first and the second capacitive sensor are configured to detect the same parameter.

In an embodiment, a first capacitance value of the first capacitive sensor and a second capacitance value of the second capacitive sensor change in opposite directions. Thus, the first capacitance value of the first capacitive sensor increases, when the second capacitance value of the second capacitive sensor decreases and vice versa. The first and the second sensor signal are a function of the first and the second capacitance value.

In an embodiment, one of the first and the second capacitive sensor is configured to operate in-phase with the parameter to be detected and the other of the first and the second capacitive sensor is configured to operate out-of-phase with the parameter to be detected. The parameter to be detected may be an alternating signal. Thus, the first and the second sensor signal are also alternating signals. The first sensor signal has a phase difference of 180 degree or approximately 180 degree to the second sensor signal. Only one of the first and the second sensor signal is in-phase with the parameter to be detected; the other of the first and the second sensor signal is out-of-phase.

In an embodiment, the sensor arrangement comprises a first circuit block. The first circuit block comprises at least one out of a group comprising a first bias diode, an anti-parallel circuit of diodes, a resistor and a first bias capacitor. The first circuit block is coupled to an output side of the charge pump arrangement and to the first terminal of the first capacitive sensor. Advantageously, the first circuit block realizes a coupling with a high impedance value between the charge pump arrangement and the first capacitive sensor. The first circuit block forms a resistive-capacitive network (RC network), e.g. to filter noise, a clock signal and other disturbing signals. The resistive component of the first circuit block may be realized by the anti-parallel circuit of diodes. The capacitive component of the first circuit block may be realized by the first bias capacitor. The first bias capacitor may be a discrete integrated capacitor.

In an embodiment, the first circuit block is also coupled to the first terminal of the second capacitive sensor. Thus, a bias voltage is generated for the second capacitive sensor in an efficient manner.

In some embodiments, the first circuit block and the amplifier arrangement may be realized e.g. as one integrated circuit. Thus, a size of the sensor arrangement is reduced. In an alternative embodiment, the sensor arrangement comprises a second circuit block that is coupled to the output side of the charge pump arrangement and to the first terminal of the second capacitive sensor. In some embodiments, the first circuit block, the amplifier arrangement and the second circuit block may be realized e.g. as one integrated circuit.

In an embodiment, the charge pump arrangement comprises a first pump output coupled to the first terminal of the first capacitive sensor and a second pump output coupled to the first terminal of the second capacitive sensor. Advantageously, the first and the second capacitive sensor can separately be provided with a first and a second bias voltage which optionally may be different. Thus, the influence of different characteristics of the two sensors may be reduced by different bias voltages.

In some embodiments, the charge pump arrangement comprises a first pump output coupled to the first terminal of the first capacitive sensor and to the first terminal of the second capacitive sensor. In an embodiment, the charge pump arrangement comprises a first charge pump coupled to the first pump output. In a further development, the charge pump arrangement comprises a second charge pump coupled to the second pump output.

In some embodiments, the charge pump arrangement comprises a first charge pump with a first number of stages. The first pump output is coupled to an output of one of the first number of stages. The second pump output is coupled to an output of another of the first number of stages. Advantageously, the first charge pump is operable to generate a first and a second pump voltage which optionally may be different.

In some embodiments, the sensor arrangement comprises an amplifier arrangement having a first input coupled to the second terminal of the first capacitive sensor and a second input coupled to the second terminal of the second capacitive sensor. The amplifier arrangement comprises a first output coupled to the first terminal of the differential output and a second output coupled to the second terminal of the differential output. Thus, the sensor signal tapped at the differential output is buffered by the amplifier arrangement.

In some embodiments, the amplifier arrangement comprises a first amplifier having an input coupled to the first input of the amplifier arrangement and a second amplifier having an input coupled to the second input of the amplifier arrangement. Since the first and the second amplifier are integrated on one integrated circuit, their characteristics correlate.

In some embodiments, the amplifier arrangement comprises a current source coupled to the first and the second amplifier, for example by a current mirror. The current source may provide a bias current to the first and the second amplifier. Advantageously, the current source may e.g. control a supply of the first and the second amplifier.

In some embodiments, the amplifier arrangement comprises a differential amplifier having a first and a second input coupled to the first and the second input of the amplifier arrangement. Advantageously, the amplification of the first and the second sensor signal is synchronized.

The first and the second capacitive sensor may both be implemented as mechanical sensors. The first and the second capacitive sensor may be fabricated as micro electro mechanical system sensors, abbreviated to MEMS sensors, or as MEMS capacitors. In some embodiments, the first and the second capacitive sensor are both implemented as one of a group comprising a microphone and an accelerometer. In some embodiments, the sensor arrangement is configured as microphone arrangement or accelerometer arrangement.

In some embodiments, the first capacitive sensor is implemented as a first microphone having a first backplate and a first diaphragm. The second capacitive sensor is implemented as a second microphone having a second backplate and a second diaphragm. The first and the second capacitive sensor are fabricated such that the first backplate moves towards the first diaphragm when the second backplate moves away from the second diaphragm. Vice versa, the first backplate moves away from the first diaphragm when the second backplate moves towards the second diaphragm.

In some embodiments, an apparatus comprises the sensor arrangement. The apparatus is realized as one of group comprising a mobile device, a smart speaker, a headset and a studio device.

In an embodiment, a method for providing a sensor signal comprises providing a first pump voltage to a first terminal of a first capacitive sensor, providing a second pump voltage to a first terminal of a second capacitive sensor, providing a first output signal at a first terminal of a differential output, providing a second output signal at a second terminal of the differential output, and providing the sensor signal derived from the first output signal and from the second output signal. The first terminal of the differential output is coupled to a second terminal of the first capacitive sensor. The second terminal of the differential output is coupled to a second terminal of the second capacitive sensor. In an embodiment, the first and the second capacitive sensor have an opposite geometric orientation.

The first and the second pump voltage may be equal or may be different. The first and the second capacitive sensor may detect the same parameter which may be an acoustic signal. The first and the second capacitive sensor may operate in an out-of-phase manner due to the different geometric construction of the first and the second capacitive sensor. The first and the second capacitive sensor may realize a 180 degrees out of phase operation.

A method for providing a sensor signal may be implemented e.g. by the sensor arrangement and the apparatus according to one of the embodiments defined above. In some embodiments, the sensor arrangement is configured as a dual MEMS differential microphone.

In some embodiments, the sensor arrangement realizes the integration of a fully differential microphone consisting of two MEMS capacitive sensors generating two sensor signals, which are out of phase. The sensor signals are being sensed by a single integrated circuit. The integrated circuit is realized as an ASIC. This allows for higher integration level of the microphone and thus enables smaller package size construction. With such a construction also the common noise sources inside the amplifier circuit can be correlated and suppressed by the differential nature of the microphone construction allowing the SNR of the integrated circuit to be increased.

The sensor arrangement allows for higher integration level for microphones using a multiple MEMS construction. By eliminating common noise sources of the amplifier such a construction allows for higher SNR of the ASIC.

In the following detailed description, various embodiments are described with reference to the appended drawings. The skilled person will understand that the accompanying drawings are schematic and simplified for clarity and therefore merely show details which are essential to the understanding of the disclosure, while other details have been left out. Like reference numerals refer to like elements or components throughout. Like elements or components will therefore not necessarily be described in detail with respect to each figure.

DETAILED DESCRIPTION

In a MEMS microphone arrangement, the MEMS microphone is used as the capacitive sensor where its capacitive profile is changed by moving its membrane with respect to its backplate. The membrane may be named diaphragm. The membrane and the backplate form the two plates of the capacitive sensor. If the charge Q at the plates remain constant, the change in voltage ΔV across the membrane and the backplate is proportional to the change Δd of a distance d between the plates given by:

where A is an area of the plates, co is the absolute dielectric constant and εris the relative dielectric constant of the medium between the plates which typically is air. The sensor arrangement which may be implemented as MEMS microphone arrangement comprises the microphone. The signal-to-noise ratio, shorted SNR, of the sensor arrangement is thereby defined by the signal-to-noise ratio for a 94 dB sound pressure level signal, shorted SPL signal, as expressed by:

where Vin_94dBSPL represents a root-mean-square voltage level (shorted rms voltage level) at an output of an amplifier, when a sound pressure of 94dBSPL=1 Pascal is applied to the sensor arrangement; Vn_mems represents the (usually) A-weighted integrated voltage noise of the MEMS microphone at the output of the amplifier across the band of interest (usually 20 Hz to 20 kHz); and Vn_asic represents the (usually) A-weighted integrated voltage noise of an application specific integrated circuit (shorted ASIC) at the output of the amplifier across the band of interest (usually 20 Hz to 20 kHz). vn_mems and vn_asic are meant to be summed in an rms sense. That is, the SNR of the sensor arrangement is increased when the signal swing at the input of the amplifier is maximized to reduce the impact of noise contribution of the ASIC. This can be e.g. achieved by a larger sensitivity of the MEMS microphone or alternatively by a reduced parasitic capacitance of the amplifier of the ASIC to reduce signal attenuation as much as possible. Thus, a voltage across the capacitive sensor should be detected with high sensitivity.

FIG. 1Ashows an example of a sensor arrangement10. The sensor arrangement10comprises a first capacitive sensor11with a first and a second terminal12,13. The first capacitive sensor11comprises a first electrode14that is coupled to the first terminal12of the first capacitive sensor11. The first electrode14of the first capacitive sensor11may be directly and permanently connected to the first terminal12of the first capacitive sensor11. Moreover, the first capacitive sensor11comprises a second electrode15coupled to the second terminal13of the first capacitive sensor11. The second electrode15may be directly and permanently connected to the second terminal13of the first capacitive sensor11.

Additionally, the sensor arrangement10comprises a second capacitive sensor21having a first and a second terminal22,23. The second capacitive sensor21comprises a first and a second electrode24,25. The first electrode24of the second capacitive sensor21is coupled to the first terminal22of the second capacitive sensor21. The first electrode24of the second capacitive sensor21may be directly and permanently connected to the first terminal22of the second capacitive sensor21. The second electrode25of the second capacitive sensor21is coupled to the second terminal23of the second capacitive sensor21. The second electrode25of the second capacitive sensor21may be directly and permanently connected to the second terminal23of the second capacitive sensor21.

The first and the second capacitive sensor11,21are sensitive for the same parameter. The parameter may be e.g. sound, noise, acceleration and/or vibration. The first and the second capacitive sensor11,21may have the same sensitivity towards the parameter to be measured. The first and the second capacitive sensor11,21have a first and a second capacitance value CMEMS1, CMEMS2. However, the first and the second capacitive sensor11,21have an opposite geometric orientation which is explained below withFIG. 4.

The first and the second capacitive sensor11,21may be realized as microphone sensors. Thus, the first electrode14of the first capacitive sensor11is implemented as a first diaphragm and the second electrode15of the first capacitive sensor11is implemented as a first backplate. The first electrode14of the first capacitive sensor11may be a bottom-plate and the second electrode15may be a top-plate.

The first electrode24of the second capacitive sensor21is realized as a second backplate and the second electrode25of the second capacitive sensor21is implemented as a second diaphragm. The first electrode24of the second capacitive sensor21may be realized as a bottom-plate and the second electrode25may be implemented as a top-plate.

Moreover, the sensor arrangement10comprises a charge pump arrangement30coupled to the first terminal12of the first capacitive sensor11and to the first terminal22of the second capacitive sensor21. Thus, the charge pump arrangement30comprises a first pump output31coupled to the first terminal12of the first capacitive sensor11. Moreover, the first pump output31is coupled to the first terminal22of the second capacitive sensor21. The charge pump arrangement30comprises a first charge pump32. The first charge pump32is connected on its output side to the first pump output31.

Additionally, the sensor arrangement10comprises a first circuit block33. The first pump output31couples to an input of the first circuit block33. The first circuit block33couples the first pump output31to the first terminal12of the first capacitive sensor11. The first circuit block33also couples the first pump output31to the first terminal22of the second capacitive sensor21. The first circuit block33comprises a first bias diode34. An anode of the first bias diode34is connected to the first pump output31and a cathode of the first bias diode34is connected to the first terminal12of the first capacitive sensor11. Moreover, the first circuit block33comprises a first bias capacitor35coupling the first bias diode34to a reference potential terminal36. The first bias capacitor35couples the first terminal12of the first capacitive sensor11to the reference potential terminal36. The first bias capacitor35may be realized as a discrete capacitor. For example, the first bias capacitor35may be realized as an off-chip capacitor or an on-chip capacitor, for example as a metal-isolator-metal capacitor. Alternatively, the first bias capacitor35is not realized as a discrete capacitor, instead the first bias capacitor35symbolizes a parasitic capacitance of the connection lines between the charge pump arrangement30and the first and the second capacitive sensor11,21.

A first sensor capacitor16of the sensor arrangement10couples the first terminal12of the first sensor11to the reference potential terminal36. A second sensor capacitor26of the sensor arrangement10couples the first terminal22of the second capacitive sensor21to the reference potential terminal36. The first and the second sensor capacitor16,26may be realized as discrete capacitors, for example as on-chip capacitors. Alternatively, the first and the second sensor capacitor16,26represent parasitic capacitances of connection lines, for example the connection lines of the first terminal12to the first electrode14,24of the first and the second capacitive sensor11,21.

Additionally, the sensor arrangement10comprises a differential output40having a first and a second terminal41,42. The first terminal41of the differential output40is coupled to the second terminal13of the first capacitive sensor11. The second terminal42of the differential output40is coupled to the second terminal23of the second capacitive sensor21.

Furthermore, the sensor arrangement10comprises an amplifier arrangement43. The differential output40forms the output of the amplifier arrangement43. Thus, the amplifier arrangement43has a first input44coupled to the second terminal13of the first capacitive sensor11. Moreover, the amplifier arrangement43has a second input45coupled to the second terminal23of the second capacitive sensor21. A first and a second output of the amplifier arrangement43is directly and permanently connected to the first and second terminal41,42of the differential output40. The amplifier arrangement43comprises a differential amplifier46having a first and a second input47,48coupled to the first and second input44,45of the amplifier arrangement43and thus to the second terminals13,23of the first and the second capacitive sensor11,21. A first and a second output of the differential amplifier46are coupled to the first and the second terminal41,42of the differential output40.

The amplifier arrangement43comprises a first amplifier capacitor49coupling the first input44of the amplifier arrangement43to the reference potential terminal36. Moreover, a second amplifier capacitor50of the amplifier arrangement43couples the second input45of the amplifier arrangement43to the reference potential terminal36. The first and the second amplifier capacitor49,50may be realized as discrete capacitors such as, for example, on-chip capacitors. Alternatively, the first and the second amplifier capacitor49,50represent parasitic capacitances resulting from connection lines.

The sensor arrangement10comprises an integrated circuit51. The integrated circuit51may be realized as an application specific integrated circuit, abbreviated ASIC. The integrated circuit51comprises the charge pump arrangement30, the first circuit block33and the amplifier arrangement43. The integrated circuit51is realized by a single semiconductor body. Additionally, the integrated circuit51may also comprise the first and the second capacitive sensor11,21. Thus, the first and the second capacitive sensor11,21are additionally realized together with the charge pump arrangement30and the amplifier arrangement43on the single semiconductor body. Alternatively, the first and the second capacitive sensor11,21are fabricated using one or two additional semiconductor bodies.

The first charge pump32generates a first pump voltage VOUT1. Thus, at the output31of the charge pump arrangement30, the first pump voltage VOUT1is tapped. On the output side of the first circuit block33a first bias voltage VBIAS1is provided. The first bias voltage VBIAS1is applied to the first terminal12,22of the first and second capacitive sensor11,21. The first bias voltage VBIAS1is generated by the first circuit block33. The first bias voltage VBIAS1is mainly a DC voltage.

The parameter to be detected changes the first and the second capacitance value CMEMS1, CMEMS2of the first and of the second capacitor11,21. Thus, a first sensor signal VSIGP is provided by the first capacitive sensor11at the second terminal13of the first capacitive sensor11. Correspondingly, a second sensor signal VSIGN is generated by the second capacitive sensor21at the second terminal23of the second capacitive sensor21. Since the first and the second capacitive sensor11,21have an opposite geometric orientation, the first sensor signal VSIGP rises at a point-of-time at which the second sensor signal VSIGN decreases and vice versa. The first and the second sensor signal VSIGP, VSIGN are provided by the first and the second capacitive sensor11,21to the first and the second input44,45of the amplifier arrangement43. Thus, these two signals VSIGP, VSIGN are provided to the first and the second input47,48of the differential amplifier46. The first and the second sensor signal VSIGP, VSIGN may have the same amount, but a different sign. The first and the second sensor signal VSIGP, VSIG may also obtain different amount values depending on how well the two signal paths are matched.

A first output signal OUTP is generated at the first terminal41of the differential output40and a second output signal OUTN is generated at the second terminal42of the differential output40. The amplifier arrangement43generates the first and the second output signal OUTP, OUTN as a function of the first and the second sensor signal VSIGP, VSIGN. A sensor signal SE is tapped between the first terminal41and the second terminal42of the differential output40. The sensor signal SE is equal to a difference between the first and the second output signal OUTP, OUTN. In the case that the amplifier arrangement43has an amplification factor of 1, the sensor signal SE can be calculated according to the following equation:

Advantageously, by the use of two capacitive sensors11,21the sensor signal SE is increased in comparison to a sensor arrangement comprising a single capacitive sensor. By the differential construction of the sensor arrangement10, the influence of disturbances or of parasitic capacitors can be reduced.

A differential configuration is employed to sense the voltage across the two MEMS capacitors11,21. The benefit of a differential sensing approach (over a single-ended approach) is that the signal swing at the input side of the amplifier arrangement43can be doubled. Under assumption of un-correlated noise sources of an amplifier input stage the noise of the integrated circuit51is increased by:

vn_asic=√{square root over (vn12+vn22)}∝√{square root over (2)},

whereas Vn1 represents the (usually) A-weighted integrated voltage noise of the positive input44of the amplifier arrangement43at the output of the amplifier46across the band of interest (usually 20 Hz to 20 kHz); Vn2 represents the (usually) A-weighted integrated voltage noise of the negative input45of the amplifier arrangement43at the output of the amplifier46across the band of interest (usually 20 Hz to 20 kHz); and vn_asic represents the total (usually) A-weighted integrated voltage noise of the full differential amplifier46. Thus, the signal amplitude is doubled. Ideally, with a differential sensing method the signal-to-noise ratio (shorted SNR) of the integrated circuit51can be increased by 3 dB.

Another advantage of a differential sensing method compared to a single ended approach is that disturbing signals injected at the differential input of the amplifier arrangement43are suppressed by the common mode rejection of the amplifier arrangement43. Thereby it is important that the disturbance is coupled into amplifier inputs44,45as symmetrically as possible.

The fully differential amplifier46can be used to sense the signal VSIGP, VSIGN of the MEMS capacitors11,21in a differential manner.

The sensor arrangement10comprise two separate MEMS capacitors11,21. In such a configuration, the first capacitive sensor11generates a positive signal whereas the second capacitive sensor21generates a negated version of the same acoustic signal P. A dual MEMS configuration allows to increase signal amplitude at the input side of the differential amplifier46by factor of two. If the two MEMS capacitors11,21are acoustically isolated the noise of the MEMS capacitors11,21will be only increasing by 3 dB resulting in a gain in SNR of (ideally) 3 dB.

Both MEMS capacitors11,21have the top-plate connected to the inputs44,45of the amplifier arrangement43, whereas the bottom plate is connected to the high-voltage charge pump output31(acting as a virtual ground). The parasitic capacitance of the first and the second sensor capacitor16,26is not loading the input of the amplifier arrangement43and the capacitive loading on the positive and negative input44,45are more symmetric. This allows disturbing signals to be better rejected by the differential nature of the sensor arrangement10helping to improve (among other parameters) power supply rejection ratio (shorted PSRR) and electromagnetic compatibility (EMC).

The sensor arrangement10is implemented as a differential configuration of a MEMS microphone. The first and the second sensor signal VSIGP, VSIGN is sensed differential by a fully differential input-output amplifier46. In contrast to a two chip solution or a two amplifier solution the advantage of such a configuration is that the noise sources inside the amplifier46are correlated and can be suppressed by the differential nature of the amplifier46. Moreover, a higher integration level can be achieved by using a single chip solution to interface to both MEMS capacitors11,21. This advantage is realized by the examples of the sensor arrangement10shown inFIGS. 1A to 1F.

In an alternative embodiment, the first electrode14of the first capacitive sensor11is realized as the first backplate that forms a top-plate. The second electrode15of the first capacitive sensor11is implemented as the first diaphragm that forms a bottom-plate.

In an alternative embodiment, the first electrode24of the second capacitive sensor21is realized as the second diaphragm that forms a top-plate. The second electrode25of the second capacitive sensor21is implemented as the second backplate that forms a bottom-plate.

In some embodiments, the first capacitive sensor11is inserted in the circuit shown inFIG. 1Ain place of the second capacitive sensor21and the second capacitive sensor21is inserted in place of the first capacitive sensor11. Thus, one diaphragm of the first and the second capacitive sensor11,21is a top-plate and the other diaphragm is a bottom-plate. Consequently, one backplate of the first and the second capacitive sensor11,21is a top-plate and the other backplate is a bottom-plate. Alternatively or additionally, the first and the second capacitive sensor11,21may be fabricated as electret microphones or accelerometers.

FIG. 1Bshows a further example of the sensor arrangement10which is a further development of the example shown inFIG. 1A. InFIG. 1B, the first electrode14of the first capacitive sensor11is realized as the first backplate which forms a bottom-plate. The second electrode15of the first capacitive sensor11is formed as the first diaphragm that is realized as a top-plate. The first electrode24of the second capacitive sensor21is realized as the second diaphragm which forms a bottom-plate. The second electrode25of the second capacitive sensor21is formed as the second backplate that is realized as a top-plate.

The amplifier arrangement43comprises a first and a second amplifier60,61. The first amplifier60couples the first input44of the amplifier arrangement43to the first terminal41of the differential output40. Correspondingly, the second amplifier61couples the second input45of the amplifier arrangement43to the second terminal42of the differential output40. Optionally, a current source62of the amplifier arrangement43is coupled to the first and the second amplifier60,61. The first and the second amplifier60,61may have an equal amplification factor, e.g. the amplification factor may be 1 or different from 1. The amplification factor can be named gain factor.

The amplifier arrangement43is constructed out of two single-ended amplifiers60,61. In such an implementation bias currents of the amplifiers60,61are uncorrelated and would increase the input referred noise of the amplifier arrangement43. Optionally, the noise of common building blocks can be correlated by an additional connection between the first amplifier60and the second amplifier61resulting in a reduced input referred noise characteristic of the amplifier arrangement43.

FIG. 1Cshows a further example of the sensor arrangement10which is a further development of the examples shown inFIGS. 1A and 1B. The amplifier arrangement43comprises a first anti-parallel circuit of diodes52connected to the first input44of the amplifier arrangement43and a second anti-parallel circuit of diodes53connected to the second input45of the amplifier arrangement43. The anti-parallel circuit of diodes52,53both comprises two diodes: An anode of a first diode is connected to a cathode of a second diode and a cathode of the first diode is connected to an anode of the second diode. The diodes of the anti-parallel circuits of diodes52,53can be discrete components or parasitic diodes due to CMOS switches, well diodes etc. CMOS is the abbreviation for complementary metal-oxide-semiconductor.

The amplifier arrangement43comprises a first feedback block54coupling the differential output40to the first anti-parallel circuit of diodes52and a second feedback block55coupling the differential output40to the second anti-parallel circuit of diodes53. The first and the second feedback block54,55have a low-pass characteristic, e.g. resulting in a closed loop high pass characteristic. The first and the second feedback block54,55regulate the DC level of the inputs47,48of the amplifier46.

The amplifier arrangement43comprises a common mode sensing circuit56arranged between the first and the second output41,42of the differential output40. A tap of the common mode sensing circuit56is coupled via the first feedback block54and the first anti-parallel circuit of diodes52to the first input44of the amplifier arrangement43. The tap of the common mode sensing circuit56is coupled via the second feedback block55and the second anti-parallel circuit of diodes53to the second input45of the amplifier arrangement43. The common mode sensing circuit56may be realized as a voltage divider. The voltage divider comprises two resistors. The tap of the common mode sensing circuit56may be arranged between the two resistors. Alternately, the common mode sensing circuit56can be replaced by other circuit blocks to realize the operation of common mode sensing e.g. source follower structures or MOSFETs operated in triode-region.

Advantageously, feedback currents are provided via the feedback blocks54,55and the anti-parallel circuits of diodes52,53to the input side of the amplifier arrangement43. Thus, the input signals at the differential amplifier46are kept in a voltage range appropriate for amplification. Large DC offsets are avoided at the inputs47,48of the differential amplifier46.

FIG. 1Dshows a further example of the sensor arrangement10which is a further development of the examples shown inFIGS. 1A to 1C. The first output41of the differential output40is coupled via the first feedback block54and the first anti-parallel circuit of diodes52to the first input44of the amplifier arrangement43. The second output42of the differential output40is coupled via the second feedback block55and the second anti-parallel circuit of diodes53to the second input45of the amplifier arrangement43.

Advantageously, feedback currents are provided to the first and the second amplifier60,61keeping the input signals of the first and the second amplifier60,61in a controlled voltage range appropriate for amplification.

FIG. 1Eshows a further example of the sensor arrangement10which is a further development of the examples shown inFIGS. 1A to 1D. The amplifier arrangement43comprises the first and the second amplifier60,61as shown inFIGS. 1B and 1D. The charge pump arrangement30comprises a second pump output65. The second pump output65is coupled to the first terminal22of the second capacitive sensor21.

Moreover, the sensor arrangement10comprises a second circuit block66coupled to an output side of the charge pump arrangement30and to the first terminal22of the second capacitive sensor21. The second pump output65of the charge pump arrangement30couples to an input of the second circuit block66. The second pump output65is coupled via the second circuit block66to the first terminal22of the second capacitive sensor21. The second circuit block66may be realized such as the first circuit block33. Thus, the second circuit block66comprises a second bias diode68coupling the second pump output65to the first terminal22of the second capacitive sensor21. The second circuit block66comprises a second bias capacitor69coupling the first terminal22of the second capacitive sensor21to the reference potential terminal36. The second bias capacitor69is realized such as discussed above regarding the first bias capacitor35. The second bias circuit66generates a second bias voltage VBIAS2.

The charge pump arrangement30comprises a second charge pump67that is coupled to the second pump output65. At the second pump output65, a second pump voltage VOUT2is generated. The second pump voltage VOUT2is provided by the second charge pump67. The second pump voltage VOUT2may be equal to the first pump voltage VOUT1. Alternatively, the first and the second pump voltage VOUT1, VOUT2may be different. The first and the second pump voltage VOUT1and VOUT2may have the same sign, for example may both be positive with respect to a reference potential GND tapped at the reference potential terminal36. The first and the second amplifier60,61may be realized as non-inverting amplifiers. The gain factor of the first and the second amplifier60,61may be different from 1.

The charge pump arrangement30, the first and the second circuit block33,66and the amplifier arrangement43are realized as one integrated circuit51and thus are fabricated using a single semiconductor body.

FIG. 1Fshows a further example of the sensor arrangement10that is a further development of the above-shown examples. The amplifier arrangement43comprises the differential amplifier46as shown inFIGS. 1A and 1C. The charge pump arrangement30comprises the first and the second charge pump32,67as shown inFIG. 1E. Moreover, the sensor arrangement10comprises the first and the second circuit block33,66as shown inFIG. 1E. The first and the second pump voltage VOUT1, VOUT2may be different. The first and the second pump voltage VOUT1, VOUT2may have the same sign. The first and the second pump voltage VOUT1, VOUT2may have the same amount. Alternatively, the first and the second pump voltage VOUT1, VOUT2may have a different amount. The first and the second capacitive sensor11,21may be realized such as shown in Figures above.

The sensor arrangement10comprises a codec37that is coupled to the differential output40. Codec is an abbreviation for encoder/decoder. The codec37comprises an analog-to-digital converter connected to the input side of the codec37. The analog-to-digital converter may be a sigma/delta converter. The codec37may comprises a filter coupled to the analog-to-digital converter and an interface coupled to the filter. The examples of the sensor arrangement10ofFIGS. 1A to 1Emay optionally comprise the codec37coupled to the differential output40.

Additionally, the sensor arrangement10may comprise a filter38coupling the differential output40to the codec37. The filter38is realized as a radio frequency filter. The filter38may be a digital filter. The filter38may be implemented as a low pass filter or a band pass filter. The filter38comprises two inputs coupled to the first and the second terminal41,42of the differential output40. The filter38may comprise one output connected to the codec37. Alternatively, the filter38may comprise two outputs coupled to two inputs of the codec37. The examples of the sensor arrangement10ofFIGS. 1A to 1Emay also optionally comprise the filter38connected to the differential output40. Alternatively or additionally, the filter38may be omitted.

The codec37may e.g. include a digital filter. The codec37and the filter38are realized on a separate integrated circuit. Alternatively, the codec37and/or the filter38may be part of the integrated circuit51.

The sensor signal SE is provided to the filter38. The filter38generates a filtered sensor signal SF out of the sensor signal SE. The filtered sensor signal SF is digitized by the codec37into a digital sensor signal SD that can be tapped at the output side of the codec75. The sensor arrangement10generates the digitized sensor signal SD as a function of the sensor signal SE. The sensor signal SE and the digitized sensor signal SD depend on the acoustic signal P.

The sensor arrangement10may include a not-shown circuit performing a differential-to-single ended conversion, e.g. between the differential output40and the filter38, between the filter38and the codec37or inside the codec37.

The sensor arrangement10uses two independent charge pumps32,67to generate the bias voltages VBIAS1, VBIAS2of the MEMS capacitors11,21independent of each other. This allows setting different bias voltages for the two different MEMS capacitors11,21to accommodate for performance differences in terms of sensitivity due to the different construction of the MEMS capacitors11,21. The different pump voltages VOUT1, VOUT2can also be generated of one single charge pump, e.g. the first charge pump32, tapping off from different outputs of the charge pump32.

The embodiments shown inFIGS. 1E and 1Fare also applicable to a sensor arrangement10with two identical MEMS capacitors11,21but with one MEMS capacitor supplied by a positive bias voltage and one being supplied by a negative bias voltage. The first and the second pump voltage VOUT1and VOUT2may have different signs. For example, one voltage of the first pump voltage VOUT1and the second pump voltage VOUT2may be negative and the other may be positive with respect to the ground potential GND at the reference potential terminal36.

In a not shown embodiment that is a further development of the embodiments shown inFIGS. 1E and 1F, the second circuit block66couples the first pump output31to the first terminal22of the second capacitive sensor21. The second charge pump67may be omitted. Thus, the two capacitive sensors11,21are decoupled on the bias side.

FIG. 2Ashows an example of the first circuit block33that is a further development of the examples shown inFIG. 1A to 1F. The first circuit block33comprises an anti-parallel circuit of diodes57that couples the input of the first circuit block33to the output of the first circuit block33. Thus, the anti-parallel circuit of diodes57couples the first pump output31to the first terminal12of the first capacitive sensor11. The anti-parallel circuit of diodes57comprises the first bias diode34and a further bias diode58. An anode of the further bias diode58is connected to a cathode of the first bias diode34and a cathode of the further bias diode58is connected to an anode of the first bias diode34.

Advantageously, the anti-parallel circuit of diodes57is configured to keep a value of the first bias voltage VBIAS1nearly constant. Thus, the first bias voltage VBIAS1can be calculated according to the following equation:

wherein VOUT1is a value of the first pump voltage and VT is a forward threshold voltage of the first bias diode34and of the further bias diode58. Advantageously, the anti-parallel circuit of diodes57implements a high resistance value between the first pump output31and the first terminal12of the first capacitive sensor11. In an alternative embodiment, the first bias capacitor35is omitted.

FIG. 2Bshows a further example of the first circuit block33as a further development of examples shown inFIGS. 1A to 1F and 2A. The first circuit block33comprises a resistor59coupled to the input of the first circuit block33and to the output of the first circuit block33. Thus, the resistor59connects the first pump output31to the first terminal12of the first capacitive sensor11. The resistor59may obtain a high resistance value that may be higher than 10 mega Ohm, 1 giga Ohm, 1 tera Ohm or 100 tera Ohm. Similarly, in some embodiments, the second bias circuit66may be realized such as shown inFIGS. 2A and 2B.

FIG. 2Cshows an example of details of the sensor arrangement10shown inFIGS. 1C and 1D. The first feedback block54comprises a feedback amplifier63. The feedback amplifier63may be configured as operational transconductance amplifier, shorted OTA. The first feedback block54may comprise a feedback capacitor64coupled to an output of the feedback amplifier63. The differential output40may be coupled to an inverting input of the feedback amplifier63(in case the first amplifier60has a positive amplification factor). The second feedback block55may be realized such as shown inFIG. 2C.

FIG. 2Dshows an example of details of the sensor arrangement10shown inFIGS. 1B, 1D and 1E. The amplifier arrangement43comprises the first and the second amplifier60,61and the current source62. A terminal of the current source62is coupled to the first and the second amplifier60,61. A further terminal of the current source62is connected to the reference potential terminal36. The amplifier arrangement43includes a current mirror150that couples the terminal of the current source62to the first and the second amplifier60,61. The first and the second amplifier60,61are operated in a common biasing scheme.

The first amplifier60comprises a first current mirror transistor151, a first input transistor152and a first current source153that are arranged in a series connection between a supply terminal154and the reference potential terminal36. The first current mirror transistor151couples the supply terminal154to the first input transistor152. The first current source153couples the first input transistor152to the reference potential terminal36. A control terminal of the first input transistor152is connected to the first input44of the amplifier arrangement43. A node between the first current mirror transistor151and the first input transistor152is coupled to the first terminal41of the differential output40; said node may be directly connected to the first terminal41or may be coupled via a not-shown stage of the first amplifier60to the first terminal41.

The second amplifier61comprises a second current mirror transistor161, a second input transistor162and a second current source163that are arranged in a series connection between the supply terminal154and the reference potential terminal36. The second current mirror transistor161couples the supply terminal154to the second input transistor162. The second current source163couples the second input transistor162to the reference potential terminal36. A control terminal of the second input transistor162is connected to the second input45of the amplifier arrangement43. A node between the second current mirror transistor161and the second input transistor162is coupled to the second terminal42of the differential output40; said node may be directly connected to the second terminal42or may be coupled via a not-shown stage of the second amplifier61to the second terminal42.

The current mirror150comprises the first and the second current mirror transistor151,161and a further current mirror transistor165. The further current mirror transistor165couples the supply terminal154to the current source62. A control terminal of the further current mirror transistor165is connected to control terminals of the first and the second current mirror transistor151,161and to a node between the further current mirror transistor165and the current source62.

The first and the second sensor signal VSIGP, VSIGN are provided to the control terminals of the first and the second input transistor152,162. A supply voltage VDD is tapped at the supply terminal154. The supply voltage VDD may e.g. be provided to the integrated circuit51from an external voltage source. The current source62provides a bias current IBIAS that is mirrored to the first and the second amplifier60,61. Thus, the first and the second amplifier60,61are coupled to the common current source62by the current mirror150. Advantageously, disturbances such as noise in the two amplifiers60,61only have a small influence on the sensor signal SE due to said coupling.

FIG. 3shows an example of the charge pump arrangement30that is a further development of the above-shown embodiments. The charge pump arrangement30comprises the first charge pump32. The first charge pump32has an output71and an input72. The first charge pump32may be implemented as a positive charge pump. The first charge pump32generates the first pump voltage VOUT1at the output71of the first charge pump32. The first pump voltage VOUT1is positive with respect to the reference potential GND tapped at the reference potential terminal36. The output71of the first charge pump32is coupled via a not-shown circuit part (such as e.g. a switch or filter) or directly connected to the first pump output31of the charge pump arrangement30. Thus, the first pump voltage VOUT1may be provided at the first pump output31of the charge pump arrangement30. InFIG. 3, a simplified block diagram of the first charge pump32is illustrated.

The first charge pump32comprises a first number N of stages74to76. In the example shown inFIG. 3A, the first number N is 3. Alternatively, the first number N may be 1, 2, 4 or a higher number. Therefore, the first number N of stages74to76may be higher than 0, higher than 1, higher than 2, higher than 3 and/or higher than 4. The first number N of stages74to76may be lower than 10, lower than 5 and/or lower than 3. The first number N of stages74to76couple the input72of the first charge pump32to the output71of the first charge pump32. The first number N of stages74to76are connected in series between the input72of the first charge pump32and the output71of the first charge pump32.

Each of the first number N of stages74to76may be realized identically. The first stage74comprises a first capacitor81, a second capacitor87and at least two switches or diodes not shown. An input85of the first stage74is connected to the input72of the first charge pump32. An output86of the first stage74is coupled via the N−1 stages75,76to the output71of the first charge pump32.

The second stage75is implemented such as the first stage74. The output86of the first stage74is connected to a further input85′ of the second stage75. The second stage75comprises a further first capacitor81′, a further second capacitor87′, at least two switches or diodes, not shown, and a further output86′.

Also the third stage76is implemented such as the first stage74. The third stage76comprises an additional first capacitor81″, an additional second capacitor87″, at least two switches or diodes, not shown, an additional input85″ and an additional output86″.

An input voltage VIN is provided to the input72of the first charge pump32. The input voltage VIN is realized as a reference voltage. The input voltage VIN may be an internally derived reference voltage. The integrated circuit51may comprise a reference voltage generator, not shown, that generates the input voltage VIN. For example, the input voltage VIN may obtain a value of 1.31 V. Alternatively, the input voltage VIN may be supplied to the integrated circuit51via the supply terminal154and may be equal to the supply voltage VDD. A first clock signal CLK is provided to the first capacitor81,81′,81″ of the different stages74to76. A second clock signal is provided to the second capacitor87,87′,87″ of the different stages74to76.

Optionally, as indicated by a dotted connection line, the first pump circuit32may comprise a further output71′ coupled or connected to the second pump output65. One of the outputs of the first number N of outputs86,86′,86″ of the first charge pump32may be coupled or connected via the further output71′ to the second pump output65, optionally with the exception of the output86″ of the last stage of the first number N of stages74to76. This pump arrangement30may be used e.g. in the sensor arrangements10ofFIGS. 1E and 1F. Thus, a third number S of stages74to76of the first charge pump32couple the input72of the first charge pump32via the further output71′ of the first charge pump32to the second pump output65, with S<N or S≤N. The second pump voltage VOUT2has the same sign as the first pump voltage VOUT1but may have a smaller amount in comparison to the first pump voltage VOUT1. Alternatively or additionally, the first and the second pump output31,65may be interchanged.

Charge is pumped by the first stage74to the output86of the first stage74. A voltage can be tapped at the output86of the first stage74that is higher than the input voltage VIN. The second stage75generates an even higher output voltage at the further output86′ of the second stage75using the voltage that is provided at the output86of the first stage74. Thus, the first charge pump32generates the first pump voltage VOUT1with a value being higher than a value of the input voltage VIN. The first pump voltage VOUT1may be in a range between 5V and 100V, more specific between 10V and 50V.

FIG. 4shows an example of the sensor arrangement10which is a further development of the embodiments shown above. A cross section of the first and the second capacitive sensor11,21is shown. The first and the second capacitive sensor11,21are both realized as microphones. The first and the second capacitive sensor11,21may be realized as external capacitive sensors. The first and the second capacitive sensor11,21may be realized on two semiconductor bodies. Alternatively, the first and the second capacitive sensor11,21are fabricated on a single semiconductor body.

The MEMS arrangement10is constructed by two separate MEMS capacitive sensors11,21with opposite geometric orientation. The first and the second capacitive sensor11,21are attached to one side of a carrier140of the sensor arrangement10. The integrated circuit51, not shown, may also be attached to the carrier140and is connected to the first and the second capacitive sensor11,21. The first and the second capacitive sensor11,21both have a diaphragm and a backplate. The diaphragms move as a function of the acoustic signal P and the back plates have a position independent of the acoustic signal P. A first diaphragm of the first capacitive sensor11is between a first backplate of the first capacitive sensor11and the carrier140. The first electrode14of the first capacitive sensor11may be realized by the first diaphragm and the second electrode15of the first capacitive sensor11may be realized by the first backplate (or vice versa).

A second backplate of the second capacitive sensor21is between a second diaphragm of the second capacitive sensor21and the carrier140. The first electrode24of the second capacitive sensor21may be realized by the second backplate and the second electrode25of the second capacitive sensor21may be realized by the second diaphragm (or vice versa). The first and the second capacitive sensor11,21are flipped with respect to the direction of the acoustic signal P.

In such a configuration, the first capacitive sensor11generates the first sensor signal VSIGP, whereas the second capacitive sensor21generates the second sensor signal VSIGN. The first sensor signal VSIGP and the second sensor signal VSIGN both depend on the same acoustic signal P. The acoustic signal P reaches the first and the second capacitive sensor11,21through openings141,141′ of the carrier140. The openings141,141′ are acoustic port holes. The first sensor signal VSIGP has a positive value and the second sensor signal VSIGN has a negative value at a point of time. At a following point of time, the first sensor signal VSIGP has a negative value and the second sensor signal VSIGN has a positive value. The second sensor signal VSIGN is a negated version of the first sensor signal VSIGP. The values of the first sensor signal VSIGP and the second sensor signal VSIGN have a different sign. On an acoustic stimulus, the displacement of the first diaphragm of the first capacitive sensor11is in opposite direction in comparison to the displacement of the second diaphragm of the second capacitive sensor21. Advantageously, this leads to a positive and negative change in the voltage on the first and the second input44,45of the amplifier arrangement43. Alternatively or additionally, the first and the second capacitive sensor11,21are attached to the side of the carrier140at which the source of the acoustic signal P is located.

FIG. 5Ashows an example of an apparatus200comprising the sensor arrangement10according to one of the embodiments and Figures described above. The apparatus200comprises the sensor arrangement10. InFIGS. 5A to 5D, the sensor arrangement10is realized as a microphone arrangement. The apparatus200is realized as a mobile device201. The mobile device201may be configured for mobile communication. The mobile device201comprises an opening202in a casing203. Thus, sound can be detected by the sensor arrangement10through the opening202.

FIG. 5Bshows a further example of the apparatus200which is a further development of the embodiments shown in the figures above. The apparatus200is realized as a smart speaker205. The smart speaker205comprises the sensor arrangement10. Additionally, the smart speaker205comprises a loudspeaker206. The smart speaker205may comprise an energy-storing device207such as, for example, a battery. The smart speaker205may comprise a communication device208for communication, for example with a wireless local area network, abbreviated as WLAN.

FIG. 5Cshows a further example of the apparatus200which is a further development of the embodiments shown in the figures above. The apparatus200is implemented as a headset210. The headset210comprises the sensor arrangement10encapsulated in a housing215and a loudspeaker211. Additionally, the headset210may comprise a further loudspeaker212. A cable213of the headset210couples the loudspeaker211, the optional further loudspeaker212and the sensor arrangement10to a plug214.

FIG. 5Dshows a further example of the apparatus200which is a further development of the embodiments shown in the figures above. The apparatus200is realized as a studio device230. The studio device230comprises the sensor arrangement10that is realized as a microphone and a holder231.

The embodiments shown in theFIGS. 1A to 5Das stated represent example embodiments of the improved sensor arrangement, therefore they do not constitute a complete list of all embodiments according to the improved sensor arrangement. Actual sensor arrangement configurations may vary from the embodiments shown in terms of circuit parts, shape, size and materials, for example.