Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0122378, filed on Sep. 23, 2016, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Inventive concepts relate to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a memory device having excellent electrical characteristics.

As electronic devices have become more multifunctional, semiconductor devices including memory devices may have high capacity and high integration. As the size of a memory cell for high capacity and high integration has been reduced, operation circuits included in a memory device and an interconnection structure for operation of the memory device and electrical connection have become complicated. Accordingly, a semiconductor device including a memory device having enhanced integration and excellent electrical characteristics is desired.

SUMMARY

Inventive concepts relate to a method of manufacturing a semiconductor device including a non-volatile vertical memory device having excellent electrical characteristics and high integration.

According to some example embodiments of inventive concepts, a method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate; conformally forming a first conductive layer on the insulating pattern layer, the first conductive layer having a first thickness; wet etching the first conductive layer, the wet etching the first conductive layer including reducing a thickness of the first conductive layer from the first thickness to a second thickness that is less than the first thickness; and forming a second conductive layer on the first conductive layer after the wet etching the first conductive layer, the second conductive layer including a material that is different from a material included in the first conductive layer.

According to some example embodiments of inventive concepts, a method of manufacturing a semiconductor device includes forming a semiconductor structure on a substrate, the semiconductor structure extending vertically from an upper surface of a first area of the substrate; conformally forming a gate dielectric layer along a side wall of the semiconductor structure; conformally forming a gate electrode layer on the gate dielectric layer, the gate electrode layer having a first thickness; wet etching the gate electrode layer, the wet etching the gate electrode layer including reducing a thickness of the gate electrode layer to a second thickness that is less than half of the first thickness; forming a gate conductive layer on the gate electrode layer after the wet etching the gate electrode layer, the gate conductive layer including a material different from a material included in the gate electrode layer; and forming a contact electrode on an upper surface of a second area of the substrate, the contact electrode extending vertically from the upper surface of the second area of the substrate.

According to some example embodiments of inventive concepts, a method of manufacturing a semiconductor device includes forming a first conductive layer on a preliminary structure, wet etching the first conductive layer, and forming second conductive layer on the first conductive layer after the wet etching the first conductive layer. The forming the first conductive layer includes conformally forming the first conductive layer in an opening defined by the preliminary structure on a substrate. The first conductive layer has a first thickness. The wet etching the first conductive layer includes reducing a thickness of the first conductive layer from the first thickness to a second thickness that is less than the first thickness. The second conductive layer includes a material that is different from a material included in the first conductive layer.

DETAILED DESCRIPTION

FIGS. 1 through 6are cross-sectional views for sequentially describing a method of manufacturing a semiconductor device, according to some example embodiments of inventive concepts.

Referring toFIG. 1, after an insulating layer is formed on an upper surface of a substrate10, a part of the upper surface of the substrate10is exposed. A photolithography process and an etching process may be performed by using a mask (not shown). Thus, an insulating pattern layer20including a hole pattern30may be formed.

The substrate10may include a semiconductor or semiconductor-on-insulator. For example, the substrate may include silicon (Si), for example, crystalline silicon (Si), polycrystalline silicon (Si), or amorphous silicon (Si). In some example embodiments, the substrate10may include a semiconductor material such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some example embodiments, the substrate10may include a conductive area, for example, an impurity-doped well or an impurity-doped structure.

The insulating pattern layer20may include one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide/nitride/oxide (ONO) layer, and a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof.

The hole pattern30may have a high aspect ratio (e.g., an aspect ratio greater than 5). As the semiconductor device has high capacity and high integration, an area of a unit memory device of the semiconductor device may be reduced and/or minimized. To this end, the hole pattern30may have a high aspect ratio, for example, an aspect ratio higher than 1:50. The insulating pattern layer20and the hole pattern30may also be referred to as a preliminary structure and an opening defined by the preliminary structure, respectively.

Referring toFIG. 2, a first conductive layer40A may be conformally formed with a first thickness T1on an upper surface of the insulating pattern layer20, an inner surface of the hole pattern30(seeFIG. 1), and an exposed surface of the substrate10.

The first conductive layer40A may include one of TiN, TiON, WN, TaN, AlN, and MoON, or a combination thereof. The first conductive layer40A may include different materials according to the purpose of use. For example, the first conductive layer40A may be used as a gate electrode layer, a barrier metal layer, or an anti-diffusion layer and may include different materials in each case.

The first conductive layer40A may be formed by a chemical vapor deposition (CVD) process, an MOCVD metal organic CVD process, an atomic layer deposition (ALD) process, an MOALD metal organic ALD (MOALD) process, an electroplating process, or a combination thereof, but is not limited thereto. These processes may generally have an excellent step coverage, compared to a physical vapor deposition (PVD) process.

Thus, as described above, to conformally form the first conductive layer40A substantially having the first thickness T1along a space limited by the hole pattern30having a high aspect ratio, a process having an excellent step coverage may be used.

The first thickness T1may range from about 40 Å to about 80 Å but is not limited thereto. The first thickness T1of the first conductive layer40A may be different according to the purpose of use. However, since the first thickness T1of the first conductive layer40A is a middle process for finally obtaining a desired (and/or alternatively predetermined) second thickness T2(seeFIG. 4), the first thickness T1of the first conductive layer40A may be determined in consideration of this. That is, the first thickness T1of the first conductive layer40A may be a thick enough to totally cover upper and side surfaces of the insulating pattern layer20and an exposed surface of the substrate10in consideration of a thickness that is to be removed during a subsequent wet etching process.

Referring toFIG. 3, a wet etching process may be performed by immersing the substrate10including the first conductive layer40A having the first thickness T1into a chemical bath containing an etchant EC. The etchant EC may include one of SC1, sulfuric acid, phosphoric acid, acetic acid, and nitric acid, or a combination thereof. SC1 is a generally used solution in which ammonia (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O) are mixed with a mixture ratio of about 1:4:20.

Unlike a dry etching process that is an anisotropic etching process, when the first conductive layer40A is etched by the wet etching process that is an isotropic etching process, the first conductive layer40A may be etched with the same etching rate in all areas contacting the etchant EC.

The etchant EC may be prepared to etch the first conductive layer40A with an etching rate ranging from about 1 Å to about 10 Å per minute. The etchant EC may be selected in consideration of various variables for adjusting the etching rate, for example, concentration of the etchant EC, temperature, an etching time, and a relationship with an etch target layer. When the etchant EC has an etching rate that is greater than about 10 Å per minute, it may be difficult to control a target etching amount of the first conductive layer40A. When the etchant EC has an etching rate that is less than about 1 Å per minute, the wet etching process may take longer than desired.

Referring toFIG. 4, the first conductive layer40A (seeFIG. 3) may be etched with the same etching rate in all areas contacting the etchant EC, and thus a first conductive layer40B having a desired (and/or alternatively predetermined) second thickness T2may be formed.

The second thickness T2of the first conductive layer40B may be formed to be less than half of the first thickness T1(seeFIG. 3) of the first conductive layer40A. For example, the first conductive layer40A may be wet etched so that the second thickness T2of the first conductive layer40B may range from about 5 Å to about 20 Å, but is not limited thereto.

When the first thickness T1of the first conductive layer40A initially ranges from about 5 Å to about 20 Å, according to a geometrical structure of the hole pattern30(seeFIG. 1), a method of forming the first conductive layer40A, and a type of a material of the first conductive layer40A, a thickness of a part of the first conductive layer40A and a thickness of another part thereof may be different. In some cases, a disconnection may occur in a part of the first conductive layer40A.

In some example embodiments of inventive concepts, a wet etching process may be used, and thus, all areas of the first conductive layer40A may be etched by the same amount. That is, the second thickness T2of the first conductive layer40B resulting from wet etching may be substantially the same in all areas of the first conductive layer40B.

Although not shown, after the wet etching process, a cleaning operation of the substrate10on which the first conductive layer40B is formed may be performed using deionized water.

Referring toFIG. 5, a second conductive layer50A may be formed on the wet etched first conductive layer40B, and thus a spaced limited by the hole pattern30(seeFIG. 1) may be completely filled.

The second conductive layer50A may include a material different from that of the first conductive layer40B. For example, the second conductive layer50A may include one of W, Ti, Al, Co, Cu, Ta, WSi, TiSi, TaSi, and CoSi, or a combination thereof. The second conductive layer50A may include different materials according to the purpose of use. For example, the second conductive layer50A, along with the first conductive layer40B, may be used as a contact plug, a via, or a metal interconnection layer and may include different materials in each case.

Similarly to forming the first conductive layer40A (seeFIG. 2), the second conductive layer50A may be formed by a CVD process, an MOCVD process, an ALD process, an MOALD process, or an electroplating process but is not limited thereto.

A first thin film layer45A may be formed between the first conductive layer40B and the second conductive layer50A. The first thin film layer45A may be an amorphous layer. The first thin film layer45A may be an intermetallic compound formed by a chemical reaction of a chemical element constituting (and/or included in) the wet etched first conductive layer40B and a chemical element constituting (and/or included in) the second conductive layer50A. In some example embodiments, the first thin film layer45A may not be formed or may be formed as a crystalline layer.

Referring toFIG. 6, each of the second conductive layer50A, the first thin film layer45A, and the first conductive layer40B may be partially removed in order to expose an upper surface of the insulating pattern layer20.

For example, a chemical mechanical polishing (CMP) method or an etch-back method may be used to sequentially polish the second conductive layer50A, the first thin film layer45A, and the first conductive layer40B.

The polished second conductive layer50A, first thin film layer45A, and first conductive layer40B may fill the hole pattern30(seeFIG. 1). A level of an upper surface of the polished second conductive layer50A, first thin film layer45A, and first conductive layer40B may be substantially the same as a level of the upper surface of the insulating pattern layer20.

According to some example embodiments of inventive concepts, a first conductive layer40may be formed as an ultra-thin film having substantially a uniform thickness along a side wall of the hole pattern30having a high aspect ratio. Accordingly, a gap-fill margin of a second conductive layer50may be increased, and electrical characteristics of the semiconductor device may be enhanced.

As electronic devices have become more multifunctional, semiconductor devices including memory devices are used to have high capacity and high integration. As the size of a memory cell for high capacity and high integration has been reduced, operation circuits included in a memory device and an interconnection structure for operation of the memory device and electrical connection have become complicated. Accordingly, a semiconductor device including a memory device having enhanced integration and excellent electrical characteristics is desired. One of the memory structures capable of implementing such high capacity and high integration may be a non-volatile vertical memory device.

According to some example embodiments of inventive concepts, in a structure including an ultra-thin film like a gate electrode layer of a non-volatile vertical memory device, the semiconductor device may be manufactured where the gate electrode layer is continuously formed with a uniform thickness.

Because of a characteristic of a geometrical structure of the gate electrode layer of the non-volatile vertical memory device, if a WF-based process gas may be used to form a gate conductive layer including, for example, tungsten (W) on the gate electrode layer, a fluorine (F) gas that is a reaction by-product of the process gas may remain in an inner opening of the gate electrode layer. The fluorine (F) gas may damage a silicon oxide layer in an insulating spacer and a mold layer around the gate electrode layer.

To limit and/or prevent damaging the silicon oxide layer, a first conductive layer40according to some example embodiments of inventive concepts may be formed. A thickness of the gate electrode layer may be continuously reduced in order to achieve the gap-fill margin of the gate conductive layer. Since the gate electrode layer may be formed as the ultra-thin film due to the reduced thickness thereof, it may be difficult to continuously form the gate electrode layer with a uniform thickness, which may deteriorate the electrical characteristics of the memory device.

According to some example embodiments of inventive concepts, a gate electrode layer having a great thickness may be formed and a wet etching process may be performed. Thus, the gate electrode layer may be finally formed as an ultra-thin film and may have a uniform thickness. Thus, a thickness of the gate electrode layer may be reduced without deteriorating electrical characteristics of a memory device, a gap-fill margin of a subsequent gate conductive layer may be achieved, thereby limiting and/or preventing damage to a silicon oxide layer, and the gate electrode layer and the gate conductive layer may be stably formed.

A non-volatile vertical memory device according to some example embodiments of inventive concepts will be described below.

FIG. 7is an equivalent circuit diagram of a memory cell array1000of a non-volatile vertical memory device manufactured by using a method of manufacturing a semiconductor device, according to some example embodiments of inventive concepts.

Referring toFIG. 7, the memory cell array1000may include a plurality of memory cell strings MS. The memory cell array1000may include a plurality of bit lines BL (e.g., BL: BL1, BL2, . . . , BLm), a plurality of word lines WL (e.g., WL1, WL2, . . . , WLn−1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The plurality of memory cell strings MS may be formed between the plurality of bit lines BL and the plurality of word lines WL.

Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn. A drain area of the string selection transistor SST may be connected to the bit lines BL: BL1, BL2, . . . , BLm. A source area of the ground selection transistor GST may be connected to the common source line CSL. The common source line CSL may be an area that is commonly connected to source areas of the plurality of ground selection transistors GST.

The string selection transistor SST may be connected to the string selection line SSL. The ground selection transistor GST may be connected to the ground selection line GSL. The plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn may be respectively connected to the word lines WL: WL1, WL2, . . . , WLn−1.

The memory cell array1000may be aligned in a 3-dimension (3D) structure. The plurality of memory cell transistors MC1, MC2, . . . , MCn−1 constituting (and/or included in) the memory cell array1000may have a serially connected structure along a vertical direction with respect to an upper surface of a substrate100(seeFIGS. 8A through 8L). Accordingly, the string selection transistor SST, the ground selection transistor GST, and the plurality of memory cell transistors MC1, MC2, . . . , MCn−1, and MCn may be formed such that each channel area may extend in a substantially vertical direction with respect to the upper surface of the substrate100. InFIG. 7, a structure of the string selection transistor SST and/or ground selection transistor GST may be different than a structure of the memory cell transistors MCn. For example, the charge trap layer may be omitted in the string selection transistor SST and/or ground selection transistor GST. Alternatively, the structure of the string selection transistor SST and/or ground selection transistor GST may be the same as a structure of the memory cell transistors MCn.

FIGS. 8A through 8Lare cross-sectional views for sequentially describing a method of manufacturing a non-volatile vertical memory device by using a method of manufacturing a semiconductor device, according to some example embodiments of inventive concepts.

The substrate100may be the same as described with reference toFIG. 1, and thus a detailed description thereof is omitted. The substrate100may be, for example, a silicon wafer. In some example embodiments, a lower structure (not shown) including at least one transistor may be between the substrate100, the sacrificial layers180, and the interlayer insulating layers160.

However, for ease of understanding inventive concepts, an example in which the sacrificial layers180and the interlayer insulating layers160are directly formed on the substrate100will be described. However, inventive concepts are not limited thereto.

The interlayer insulating layers160may include a plurality of insulating layers161through166. The sacrificial layers180may include a plurality of sacrificial layers181through186. The plurality of insulating layers161through166and the plurality of sacrificial layers181through186may be alternately stacked on the substrate100by starting with the sacrificial layer181that is the lowermost layer, as shown inFIG. 8A. The sacrificial layers180may include a material that may be etched with etch selectivity with respect to the interlayer insulating layers160. That is, during a process of etching the sacrificial layers180by using a desired (and/or alternatively predetermined) etching recipe, the sacrificial layers180may include a material that may be etched while minimizing etching of the interlayer insulating layers160. The etch selectivity may quantitatively be a ratio of etching rates of the sacrificial layers180with respect to etching rates of the interlayer insulating layers160.

In some example embodiments, the sacrificial layers180may include one of materials having etch selectivity ranging from about 1:10 to about 1:200 or from about 1:30 to about 1:100 with respect to the interlayer insulating layers160. For example, the interlayer insulating layers160may be one of silicon oxide and silicon nitride, or a combination thereof, and the sacrificial layers180may include one of a silicon layer, a silicon oxide layer, a silicon carbide layer, and a silicon nitride layer, or a combination thereof and may include a material different from a material of the interlayer insulating layers160. However, for ease of understanding inventive concepts, an example in which the interlayer insulating layers160include a silicon oxide layer and the sacrificial layers180include a silicon nitride layer directly formed on the substrate100will be described.

In some example embodiments, a first sacrificial layer181and a sixth sacrificial layer186may have thicknesses greater than those of second through fifth sacrificial layers182through185. Thicknesses of the first sacrificial layer181and the sixth sacrificial layer186may determine thicknesses of gates of the string selection transistor SST and the ground selection transistor GST and may be greater than thicknesses of gates of memory cell transistors. MC1through MC4that are determined according to thicknesses of the second through fifth sacrificial layers182through185so that a sufficient current may be supplied to memory cell strings MS.

Thicknesses of a first interlayer insulating layer161and the fifth interlayer insulating layer165may be greater than those of the second through fourth interlayer insulating layers162through164.

However, the thicknesses of the interlayer insulating layers160and the sacrificial layers180may be modified in various ways. The number of layers constituting (and/or included in) the interlayer insulating layers160and the sacrificial layers180may also be modified in various ways.

Referring toFIG. 8B, first openings H1that penetrate the interlayer insulating layers160and the sacrificial layers180that are alternately stacked may be formed. The first openings H1may limit an area in which semiconductor structures120(seeFIG. 8C) and insulating layers (not shown) are to be formed. The first openings H1may be trenches having a depth in a Z direction and extending in a Y direction. The first openings H1may be separated from each other by a desired (and/or alternatively predetermined) distance in an X direction and may be repeatedly formed.

An operation of forming the first openings H1may include an operation of forming a desired (and/or alternatively predetermined) mask pattern defining locations of the first openings H1on the interlayer insulating layers160and the sacrificial layers180that are alternately stacked and an operation of anisotropic etching the interlayer insulating layers160and the sacrificial layers180alternately by using the mask pattern as an etching mask.

In some example embodiments, when the interlayer insulating layers160and the sacrificial layers180are directly formed on the substrate100, the first openings H1may be formed to partially expose an upper surface of the substrate100as shown inFIG. 8B. In addition, as a result of over-etching in the anisotropic etching operation, the substrate100below the first openings H1may be recessed with a desired (and/or alternatively predetermined) depth, as shown inFIG. 8B.

Referring toFIG. 8C, a semiconductor layer122may be formed to conformally cover side walls and lower surfaces of the first openings H1(seeFIG. 8B). The semiconductor layer122may include silicon. For example, the semiconductor layer122may include a silicon epitaxial layer having a polycrystalline or single crystalline structure. The semiconductor layer122may be formed by one of CVD and ALD processes. The semiconductor layer122may have a certain thickness, for example, a thickness ranging from about 1/50 to about ⅕ of widths of the first openings H1. Accordingly, an inner opening may be formed in the semiconductor layer122.

The inner opening may be filled by an insulating pillar124. The insulating pillar124may include an oxide layer such as Undoped Silica Glass (USG), Spin On Glass (SOG), or Tonen SilaZene (TOSZ). In some example embodiments, before the insulating pillar124fills the inner opening, an annealing operation of thermally treating a structure in which the semiconductor layer122is formed in a gas atmosphere including hydrogen or heavy hydrogen may be performed. Many crystalline defects in the semiconductor layer122may be cured by the annealing operation.

To remove unnecessary semiconductor material and insulating material covering the sixth interlayer insulating layer166that is the uppermost layer, a planarization process, for example, a CMP or etch-back process, may be performed so that the sixth interlayer insulating layer166is exposed. Thus, the semiconductor layer122and the insulating layer124may be formed inside the first openings H1.

An upper portion of the insulating layer124may be removed by using an etching process. A conductive layer126may be formed in a location from which the upper portion of the insulating layer124is removed. The conductive layer126may include doped polysilicon. The planarization process that is performed so that the sixth interlayer insulating layer166that is the uppermost layer is exposed may be performed again, and thus the conductive layer126may be arranged on the insulating pillar124and connected to the semiconductor layer122.

In some example embodiments, the semiconductor layer122may be formed inside the whole first openings H1. In this case, an operation of forming the insulating pillar124may be omitted. To form the conductive layer126in an upper portion of the semiconductor layer122, impurities may be injected into the upper portion of the semiconductor layer122that totally fills the inside of the first openings H1and thus an area corresponding to the conductive layer126may be formed therein.

In some example embodiments, to form a gate dielectric layer, before the semiconductor layer122is formed in the first openings H1, for example, a tunneling insulating layer131(seeFIG. 9) may be formed on side walls of the first openings H1.

Referring toFIG. 8D, second openings H2that expose another part of the upper surface of the substrate100may be formed in the structure ofFIG. 8C. The second openings H2may have a width that is slightly greater than a width of an area in which a contact electrode170(seeFIG. 8K) and insulating spacers110(seeFIG. 8K) arranged in both sides of the contact electrode170are to be formed. For example, the second openings H2may be at least twice a thickness of a gate dielectric layer130(seeFIG. 8K). The second openings H2may be vertically formed in the substrate100between the first openings H1(seeFIG. 8B).

An operation of forming the second openings H2may include an operation of forming an etching mask defining the second openings H2on the structure ofFIG. 8Cand an operation of alternately anisotropy etching the interlayer insulating layers160and the sacrificial layers180below the etching mask so that the other part of the upper surface of the substrate100is exposed.

In some example embodiments, as shown inFIG. 8D, the second openings H2and the first openings H1may be alternately formed in the X direction. That is, the number of first openings H1and second openings H2at the same X coordinates in the X direction may be substantially the same. However, inventive concepts are not limited thereto. Relative locations of the first openings H1and the second openings H2may be different.

Referring toFIG. 8E, the sacrificial layers180(seeFIG. 8D) exposed through the second openings H2may be selectively removed, and thus recess areas may be formed between the interlayer insulating layers160. The recess areas may be gap areas horizontally extending from the second openings H2and exposing some side walls of the semiconductor structures120.

An operation of forming the recess areas may include an operation of horizontally etching the sacrificial layers180by using an etching recipe having etch selectivity with respect to the interlayer insulating layers160. For example, when the sacrificial layers180are silicon nitride layers and the interlayer insulating layers160are silicon oxide layers, the operation of horizontally etching the sacrificial layers180may be performed by using an etchant containing phosphoric acid.

Referring toFIG. 8F, the gate dielectric layer130may be formed to conformally cover the semiconductor structures120, the interlayer insulating layers160, and the substrate100that are exposed by the second openings H2and the recess areas. The gate dielectric layer130may include a tunneling insulating layer131(seeFIG. 9), a charge storing layer132(seeFIG. 9), and a barrier insulating layer133(seeFIG. 9). Thus, the gate dielectric layer130may be formed to cover the semiconductor structures120, the interlayer insulating layers160, and the substrate100in the order of the tunneling insulating layer131, the charge storing layer132, and the barrier insulating layer133. The tunneling insulating layer131, the charge storing layer132, and the barrier insulating layer133may have the same thickness through a CVD process or an ALD process. The gate dielectric layer130may also be formed on an upper surface of the sixth interlayer insulating layer166that is the uppermost layer and an upper surface of the conductive layer126, and thus function as an anti-etching layer that limits and/or prevents etching of the upper surface of the sixth interlayer insulating layer166that is the uppermost layer.

The gate dielectric layer130may be conformally formed with a desired (and/or alternatively predetermined) thickness, and thus inner openings may be formed in the second openings H2and the recess areas. A gate electrode layer140A may be included in the inner openings surrounded by the gate dielectric layer130and may be conformally formed on the gate dielectric layer130with the first thickness T1. The interlayer insulating layers160and semiconductor structures120may also be referred to as a preliminary structure. The second openings H2may be also be referred to as openings defined by the preliminary structure.

The gate electrode layer140A may include a material similar to that of the first conductive layer40A described with reference toFIG. 2above. For example, the gate electrode layer140A may include tantalum (TaN). The gate electrode layer140A may be formed by using a similar process to that of the first conductive layer40A. For example, the gate electrode layer140A may be formed by using a CVD process or an ALD process.

The gate electrode layer140A may be conformally formed on the gate dielectric layer130with the first thickness T1, and thus inner openings may be formed in the second openings H2and the recess areas. That is, the gate electrode layer140A may be formed with the first thickness T1by which the inner openings are formed. For example, the first thickness T1may range from about 40 Å to about 80 Å, but is not limited thereto.

The gate electrode layer140A may also be formed on the upper surface of the sixth interlayer insulating layer166that is the uppermost layer and the upper surface of the conductive layer126, and thus function as an anti-etching layer that limits and/or prevents etching of the upper surface of the sixth interlayer insulating layer166that is the uppermost layer.

Referring toFIG. 8G, a gate electrode layer140B having the desired (and/or alternatively predetermined) second thickness T2may be formed by performing a wet etching operation of removing a part of the gate electrode layer140A (seeFIG. 8F).

The second thickness T2of the wet etched gate electrode layer140B may be formed to be less than half of the first thickness T1of the gate electrode layer140A (seeFIG. 8F). For example, the wet etched gate electrode layer140B may be formed by wet etching so that the second thickness T2may range from about 5 Å to about 20 Å. A method and a process of performing wet etching to form the wet etched gate electrode layer140B are similar to those of wet etching the first conductive layer40A described with reference toFIG. 3above, and thus detailed descriptions thereof are omitted.

When the first thickness T1of the gate electrode layer140A initially ranges from about 5 Å to about 20 Å, according to a geometrical structure of the non-volatile vertical memory device, a method of forming the gate electrode layer140A, and a type of a material of the gate electrode layer140A, a thickness of a part of the gate electrode layer140A and a thickness of another part thereof may be different. In some cases, a disconnection may occur in a part of the gate electrode layer140A.

In inventive concepts, a wet etching process may be used, and thus, all areas of the gate electrode layer140A may be etched by the same amount. That is, the second thickness T2of the wet etched gate electrode layer140B may be substantially the same in all areas. A disconnection in a part of the gate electrode layer140A may be reduced.

Referring toFIG. 8H, a gate conductive layer150A may be formed on the wet etched gate electrode layer140B, and thus entirely filling inner openings surrounded by the gate electrode layer140B.

The gate conductive layer150A may include a material different from that of the wet etched gate electrode layer140B. The gate conductive layer150A may include a material similar to that of the second conductive layer50A described with reference toFIG. 5above. For example, the gate conductive layer150A may include tungsten (W).

Similarly to a process of forming the second conductive layer50A, a process of forming the gate conductive layer150A may include a CVD process, an MOCVD process, an ALD process, an MOALD process, or an electroplating process but is not limited thereto.

An interface thin film layer145A may be formed between the wet etched gate electrode layer140B and the gate conductive layer150A. The interface thin film layer145A may be an amorphous layer. The interface thin film layer145A may be an intermetallic compound formed by a chemical reaction of a chemical element constituting (and/or included in) the wet etched gate electrode layer140B and a chemical element constituting (and/or included in) the gate conductive layer150A. In some example embodiments, the interface thin film layer145A may not be formed or may be formed as a crystalline layer.

The wet etched gate electrode layer140B, the interface thin film layer145A, and the gate conductive layer150A may be flattened so that the gate dielectric layer130formed on an upper portion of the interlayer insulating layer166that is the uppermost layer is exposed.

Referring toFIG. 8I, third openings H3may be formed by partially removing the gate conductive layer150A (seeFIG. 8H), the interface thin film layer145A (seeFIG. 8H), and the wet etched gate electrode layer140B (seeFIG. 8H) so that a part of an upper surface of the substrate100is exposed. The gate conductive layer150A, the interface thin film layer145A, and the wet etched gate electrode layer140B may be partially removed through anisotropic etching. Thus, gate electrodes150filling a recess area may be formed.

A part of the gate dielectric layer130formed on the upper surface of the substrate100may be removed through anisotropic etching. In some example embodiments, the gate dielectric layer130formed on sidewalls of the interlayer insulating layers160may be removed. During a process of etching the gate conductive layer150A, the interface thin film layer145A, and the wet etched gate electrode layer140B, the gate electrodes150filling the recess area may be partially recessed toward the semiconductor structures120.

Impurities may be injected into the substrate100through the third openings H3, and thus an impurity area105may be formed extending in a Y direction adjacent to the upper surface of the substrate100. The impurity area105may have the same conductivity as or an opposite conductivity to that of the substrate100. When the impurity area105has an opposite conductivity to that of the substrate100, the impurity area105and the substrate100may constitute a P-N junction. In some example embodiments, each of the impurity areas105may be connected to each other in an equipotential state.

Referring toFIG. 8J, insulating spacers110may be formed in sidewalls of the third openings H3. The insulating spacers110may include an insulating material having etch selectivity with respect to a material of the gate electrodes150and a material of the gate dielectric layer130, in particular, a barrier insulating layer133(seeFIG. 9). The insulating spacers110may be formed by filling the third openings H3with the insulating material and partially removing the insulating material through isotropic etching. Fourth openings H4having a desired (and/or alternatively predetermined) thickness, defined by the insulating spacers110and having a width that is less than the third openings H3, may be formed in the insulating spacers110formed by isotropic etching. Isotropic etching may be over etching, and thus an upper surface of the impurity area105may be recessed.

Referring toFIG. 8k, the fourth openings H4may be filled with a conductive material, and thus a contact electrode170including a barrier metal layer172and a contact electrode layer174that are in ohmic contact with the impurity area105may be formed. To reduce a contact resistance of the impurity area105and limit and/or prevent diffusion of a material constituting (and/or included in) the contact electrode layer174, the barrier metal layer172may be formed before the contact electrode layer714is formed.

The barrier metal layer172may be formed with a third thickness and then wet etched in order to have a desired (and/or alternatively predetermined) fourth thickness that is less than the third thickness, and the contact electrode layer174including a material different from that of the barrier metal layer172may be formed on the barrier metal layer172, thereby forming the contact electrode170.

A material of the barrier metal layer172and a method of forming the barrier metal layer172may be similar to those of the first conductive layer40described with reference toFIGS. 2 through 6above, and a material of the contact electrode layer174and a method of forming the contact electrode layer174may be similar to those of the second conductive layer50described with reference toFIGS. 2 through 6above, and thus detailed descriptions thereof are omitted.

Although not shown, an interlayer thin film layer may be formed between the barrier metal layer172and the contact electrode layer174. The interface thin film layer may be an amorphous layer. The interface thin film layer may be an intermetallic compound formed by a chemical reaction of a chemical element constituting (and/or included in) the barrier metal layer172and a chemical element constituting (and/or included in) the contact electrode layer174. In some example embodiments, the interface thin film layer may not be formed or may be formed as a crystalline layer.

Referring toFIG. 8L, a capping layer191may be formed on the structure ofFIG. 8K. A bit line contact plug195may be formed on the conductive layer126of the semiconductor structures120to penetrate the capping layer191. The bit line contact plug195may be formed by using a photolithography process and an etching process. A bit line193connecting the bit line contact plugs195arranged in an X direction may be formed on the capping layer191. The bit line193may be formed in a line shape by using the photolithography process and the etching process. In some example embodiments, the bit line contact plug195may have a multilayer structure.

In some example embodiments, a plurality of 3D memory cell strings may be formed vertically from an upper surface of the substrate100by using the semiconductor structure120as an active area.

Accordingly, a non-volatile vertical memory device1100may be formed. According to some example embodiments of inventive concepts, if the gate electrode layer140having a great thickness is formed and then formed as an ultra-thin film electrode by using a wet etching process, the gate electrode layer140may have a uniform thickness while being as the ultra-thin film electrode. Thus, a thickness of the gate electrode layer140may be reduced without deteriorating electrical characteristics of a memory device, a gap-fill margin of the gate conductive layer150B may be achieved, thereby limiting and/or preventing damage to a silicon oxide layer, and the gate electrode150may be stably formed.

FIG. 9is a partial enlarged view of a portion AA ofFIG. 8Lfor describing the gate dielectric layer130and the gate electrode150.

FIG. 9illustrates the semiconductor layer122that may be used as a channel by transistors of memory cell strings. The insulating pillar124may be arranged on a left surface of the semiconductor layer122. The gate electrode150may be arranged on a right surface of the semiconductor layer122. The interlayer insulating layers160may contact the right surface of the semiconductor layer122and may be arranged in upper and lower portions of the gate electrode150. The gate dielectric layer130may be arranged so one surface contacts two surfaces of the upper interlayer insulating layer160, contacts three surfaces of the gate electrode150, and contacts two surfaces of the lower interlayer insulating layer160.

The gate dielectric layer130may have a structure in which the tunneling insulating layer131, the charge storing layer132, and the barrier insulating layer133are sequentially joined from the right surface of the semiconductor layer122.

The tunneling insulating layer131may include one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) or a combination thereof in a single layer structure or a multilayer structure.

The charge storing layer132may be a charge trap layer or a floating gate. When the charge storing layer132is a floating gate, the charge storing layer132may be formed by depositing polysilicon by using, for example, a low pressure CVD (LPCVD) process. When the charge storing layer132is a charge trap layer, the charge storing layer132may include one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O3), titanium oxide (TiO2), hafnium aluminum oxide (HfAlxOy), hafnium tantalum oxide (HfTaxOy), hafnium silicon oxide (HfSixOy), aluminum nitride (AlxNy), and aluminum gallium nitride (AlGaxNy), or a combination thereof in a single layer structure or a multilayer structure.

The barrier insulating layer133may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric layer, or a combination thereof in a single layer structure or a multilayer structure. The barrier insulating layer133may include a material having a dielectric constant that is higher than that of the tunneling insulating layer131. The high-k dielectric layer may include one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3), or a combination thereof.

The insulating spacer110may be arranged in the gate electrode150and a right side of the barrier insulating layer133.

FIG. 10is a block diagram of a semiconductor device1200manufactured by using a method of manufacturing a semiconductor device, according to some example embodiments of inventive concepts.

Referring toFIG. 10, a NAND cell array1230may be coupled to a core circuit unit1210in the semiconductor device1200. For example, the NAND cell array1230may include the semiconductor device1100manufactured by using a method of manufacturing a semiconductor device ofFIGS. 8A through 8L. The core circuit unit1210may include a control logic1211, a row decoder1212, a column decoder1213, a sense amplifier1214, and a page buffer1215.

The control logic1211may communicate with the row decoder1212, the column decoder1213, and the page buffer1215. The row decoder1212may communicate with the NAND cell array1230through the plurality of string selection lines SSL, the plurality of word lines WL, and the plurality of ground selection lines GSL. The column decoder1213may communicate with the NAND cell array1230through the plurality of bit lines BL. The sense amplifier1214may be connected to the column decoder1213when a signal is output by the NAND cell array1230and may not be connected to the column decoder1213when the signal is transferred to the NAND cell array1230.

For example, the control logic1211may transfer a row address signal to the row decoder1212, the row decoder1212may decode the row address signal and may transfer the decoded row address signal to the NAND cell array1230through the plurality of string selection lines SSL, the plurality of word lines WL, and the plurality of ground selection lines GSL. The control logic1211may transfer a column address signal to the column decoder1213or the page buffer1215, and the column decoder1213may decode the column address signal and may transfer the decoded column address signal to the NAND cell array1230through the plurality of bit lines BL. The signal of the NAND cell array1230may be transferred to the sense amplifier1214through the column decoder1213. The sense amplifier1214may amplify the signal and may transfer the amplified signal to the control logic1212through the page buffer1215.

The NAND cell array1230may be a three-dimensional (3D) memory array that includes three-dimensionally arranged memory cells, a plurality of word lines electrically connected to the memory cells, and a plurality of bit lines electrically connected to the memory cells. The 3D memory array may be monolithically formed on a substrate (e.g., semiconductor substrate such as silicon, or semiconductor-on-insulator substrate). The 3D memory array may include vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may comprise a charge trap layer. The following patent documents, which are hereby incorporated by reference in their entirety, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

While some example embodiments of inventive concepts have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.