Dynamic tuning in wireless energy transfer systems

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a variable capacitance device. The device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch.

BACKGROUND

Electronic devices may require the use of tunable circuit components. In some applications, an electronic device may need to adjust the values of one or more circuit components to match impedances between different portions of a circuit, such as in a dynamic impedance matching network. Existing tunable circuit components may have a limited dynamic range of values, imprecise tuning capabilities, or high power losses. In some cases, existing tunable circuit components may be unusable in high power circuits such as a wireless power transfer system having large voltage swings.

SUMMARY

In general, the disclosure features dynamically tunable circuit elements and related tuning circuits. In a first aspect, the disclosure features a variable capacitance device including a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The first capacitor includes a first-capacitor first terminal and a first-capacitor second terminal, where the first-capacitor first terminal is electrically connected to a ground. The first switch includes a first-switch first terminal, a first-switch second terminal, and a first-switch control terminal. The first-switch first terminal is electrically connected to the first-capacitor first terminal, and the first-switch second terminal is electrically connected to the first-capacitor second terminal. The second capacitor includes a second-capacitor first terminal and a second-capacitor second terminal, where the second-capacitor first terminal is electrically connected to the ground. The second switch includes a second-switch first terminal, a second-switch second terminal, and a second-switch a control terminal. The second-switch first terminal is electrically connected to the second-capacitor first terminal, and the second-switch second terminal is electrically connected to the second-capacitor second terminal. The control circuitry is coupled with the first-switch control terminal and the second-switch control terminal. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch. The first and second control signals cause the respective first and second switch to close.

This and other implementations can each optionally include one or more of the following features.

A capacitance of the variable capacitance device can depend upon the duration of time for which the first and second control signals are applied to the respective first-switch control terminal and second-switch control terminal. The first switch can be a first transistor and the second switch can be a second transistor. The control circuitry can be configured to receive an input signal and, in response to receiving the input signal, change the duration of time for which the first and second control signals are applied to the respective first-switch control terminal and second-switch control terminal.

In some implementations, the variable capacitance device can include a first comparator and a second comparator. The first comparator can include a first-comparator first input terminal electrically connected to the first-capacitor second terminal. The second comparator can include a second-comparator first input terminal electrically connected to the second-capacitor second terminal. The control circuitry can be coupled with a first-comparator output terminal of the first comparator and a second-comparator output terminal of the second comparator, where the control circuitry configured to detect the zero voltage condition across the first switch based on an output signal of the first comparator, and, in response, cause the first control signal to be applied to the first-switch control terminal for the duration of time; and to detect the zero voltage condition across the second switch based on an output signal of the second comparator, and, in response, cause the second control signal to be applied to the second-switch control terminal for the duration of time.

In some implementations, the variable capacitance device can include a third comparator and a fourth comparator. The third comparator can include a third-comparator first input terminal electrically connected to a first reference voltage and a third-comparator second input terminal electrically connected to the first-switch control terminal. The fourth comparator can include a fourth-comparator first input terminal electrically connected to a second reference voltage and a fourth-comparator second input terminal electrically connected to the second-switch control terminal. The control circuitry can be coupled with a third-comparator output terminal of the third comparator and a fourth-comparator output terminal of the fourth comparator. The control circuitry can be configured to: detect a first ON condition at the first-switch control terminal based on an output signal of the third comparator. Determine a first time difference, where the first time difference being a difference in time from detecting the zero voltage condition across the first switch and detecting the first ON condition at the first-switch control terminal. Adjust a first timing of when the first control signal is applied to the first-switch control terminal so as to reduce the first time difference. Detect a second ON condition at the second-switch control terminal based on an output signal of the fourth comparator. Determine a second time difference, where the second time difference being a difference in time from detecting the zero voltage condition across the second switch and detecting the second ON condition at the second-switch control terminal. And, adjust a second timing of when the second control signal is applied to the second-switch control terminal so as to reduce the second time difference.

In some implementations, the control circuitry can include a pulse width modulation (PWM) generator. The PWM generator can include a first output terminal electrically connected to the first-switch control terminal and a second output terminal electrically connected to the second-switch control terminal, where the first control signal is a first pulse width modulated signal and the second control signal is a second pulse width modulated signal, and the control circuitry is configured to control characteristics of the first and second pulse width modulated signals.

Adjusting the timing of when the first and second control signals are applied to the respective first-switch control terminal and the second-switch control terminal can include adjusting phases of the first and second pulse width modulated signals. The control circuitry can be configured to receive an input signal and, in response to receiving the input signal, change the duration of time for which the first and second control signals are applied to the respective control terminals of the first switch and the second switch by adjusting respective duty cycles of the first and second pulse width modulated signals.

In some implementations, the variable capacitance device can include a third comparator and a fourth comparator. The third comparator can include a third-comparator first input terminal electrically connected to a first reference voltage and a third-comparator second input terminal electrically connected to the first-switch control terminal. The fourth comparator can include a fourth-comparator first input terminal electrically connected to a second reference voltage and a fourth-comparator second input terminal electrically connected to the second-switch control terminal. And, the control circuitry can include a controller, a first counter, and a second counter. The first counter can be coupled with the first-comparator output terminal, the third-comparator output terminal, and the controller. In addition, the first counter can be configured to start a first timer in response to receiving a zero voltage signal from the first comparator, stop the first timer in response to receiving a first ON condition signal from the third comparator, and send a signal indicating an elapsed time of the first timer to the controller. The second counter can be coupled with the second-comparator output terminal, the fourth-comparator output terminal, and the controller. In addition, the second counter can be configured to start a second timer in response to receiving a zero voltage signal from the second comparator, stop the second timer in response to receiving a second ON condition signal from the fourth comparator, and send a signal indicating an elapsed time of the second timer to the controller. And, the controller can be configured to adjust a first timing of when the first control signal is applied to the first-switch control terminal, based on the first-time-difference signal, so as to reduce the first time difference, and adjust a second timing of when the second control signal is applied to the second-switch control terminal, based on the second-time-difference signal, so as to reduce the second time difference.

In some implementations, the control circuitry can include a PWM generator coupled with the controller. The PWM generator can include a first output terminal electrically connected to the first-switch control terminal and a second output terminal electrically connected to the second-switch control terminal, where the first control signal is a first pulse width modulated signal and the second control signal is a second pulse width modulated signal. The controller can be configured to control characteristics of the first and second pulse width modulated signals.

The controller can be one of: a microcontroller, a computer processor, a field programmable logic array (FPGA), or an application specific integrated circuit (ASIC).

In some implementations, detecting the zero voltage condition across the first switch based on an output signal of the first comparator, and, in response, causing the first control signal to be applied to the first-switch control terminal can include: determining a first phase difference between a first-comparator output signal and a third-comparator output signal, generating a third reference voltage based the first phase difference, and causing the first control signal to be applied to the first-switch control terminal upon detecting that a voltage signal at the first-switch second terminal has crossed a voltage value equal to the third reference voltage. Detecting the zero voltage condition across the second switch based on an output signal of the second comparator, and, in response, cause the second control signal to be applied to the second-switch control terminal can include: determining a second phase difference between a second-comparator output signal and a fourth-comparator output signal, generating a fourth reference voltage based the second phase difference, and causing the second control signal to be applied to the second-switch control terminal upon detecting that a voltage signal at the second-switch second terminal has crossed a voltage value equal to the fourth reference voltage.

In some implementations, the control circuitry includes a first phase detection circuit, a first integrator circuit, a fifth comparator, a first flip-flop, a second phase detection circuit, a second integrator circuit, a sixth comparator, a second flip-flop, and a controller. The first phase detection circuit is coupled with the first-comparator output terminal and a third-comparator output terminal of the third comparator. The first integrator circuit is coupled with the first phase detection circuit. The fifth comparator includes a fifth-comparator output terminal, a fifth-comparator first input terminal electrically connected to the first-capacitor second terminal, and a fifth-comparator second input terminal coupled with the first integrator circuit. The first flip-flop includes a first-flip-flop reset terminal, a first-flip-flop clock terminal electrically connected to the fifth-comparator output terminal, and a first-flip-flop output terminal electrically connected to the first-switch control terminal. The second phase detection circuit is coupled with the second-comparator output terminal and a fourth-comparator output terminal of the fourth comparator. The second integrator circuit is coupled with the second phase detection circuit. The sixth comparator includes a sixth-comparator output terminal, a sixth-comparator first input terminal electrically connected to the second-capacitor second terminal, and a sixth-comparator second input terminal coupled with the second integrator circuit. The second flip-flop includes a second-flip-flop reset terminal, a second-flip-flop clock terminal electrically connected to the sixth-comparator output terminal, and a second-flip-flop output terminal electrically connected to the second-switch control terminal. The controller is coupled with the first flip-flop and the second flip-flop and is configured to provide a first reset signal to the first flip-flop after the duration of time and to provide a second reset signal to the second flip-flop after the duration of time. The controller can be a PWM generator, where the first reset signal is a first pulse width modulated signal, and the second reset signal is a second pulse width modulated signal.

In a second aspect, the disclosure features a wireless energy transfer system includes a split coil resonator and a variable capacitance device. The split coil resonator includes a first winding magnetically coupled with a second winding. The variable capacitance device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The first capacitor includes a first-capacitor first terminal and a first-capacitor second terminal, the first-capacitor first terminal electrically connected to a ground, and the first-capacitor second terminal electrically connected to a first-winding terminal of the first winding of the split coil resonator. The first switch includes a first-switch first terminal, a first-switch second terminal, and a first-switch control terminal, the first-switch first terminal electrically connected to the first-capacitor first terminal, and the first-switch second terminal electrically connected to the first-capacitor second terminal. The second capacitor includes a second-capacitor first terminal and a second-capacitor second terminal, the second-capacitor first terminal electrically connected to the ground, and the second-capacitor second terminal electrically connected to a second-winding terminal of the second winding of the split coil resonator. The second switch comprising a second-switch first terminal, a second-switch second terminal, and a second-switch a control terminal, the second-switch first terminal electrically connected to the second-capacitor first terminal, and the second-switch second terminal electrically connected to the second-capacitor second terminal. The control circuitry is coupled with the first-switch control terminal and with the second-switch control terminal. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch. The first and second control signals cause the respective first and second switch to close.

This and other implementations can each optionally include one or more of the following features. In addition, the variable capacitance device can include any of the features described above.

In some implementations, the wireless energy transfer system can include a third capacitor and a fourth capacitor. The third capacitor can include a third-capacitor first terminal and a third-capacitor second terminal, the third-capacitor first terminal electrically connected to the first-winding terminal, and the third-capacitor second terminal electrically connected to the first-capacitor second terminal. And, the fourth capacitor can include a fourth-capacitor first terminal and a fourth-capacitor second terminal, the fourth-capacitor first terminal electrically connected to the second-winding terminal, and the fourth-capacitor second terminal electrically connected to the second-capacitor second terminal. The wireless energy transfer system can include a fixed impedance matching network coupled with a first-winding second terminal of the first winding and a second-winding second terminal of the second winding.

In some implementations, the wireless energy transfer system can include a third capacitor comprising a third-capacitor first terminal and a third-capacitor second terminal, the third-capacitor first terminal electrically connected to the first-winding terminal, and the third-capacitor second terminal electrically connected to the second-winding terminal.

In a third aspect, the disclosure features a zero voltage switching device including a switch, a first comparator, a second comparator and a controller. The switch includes a first terminal, a second terminal, and a control terminal. The first comparator includes a first input terminal electrically connected to the second terminal of the switch and a second input terminal electrically connected to the first terminal of the switch. The second comparator includes a first input terminal electrically connected to a reference voltage and a second input terminal electrically connected to the control terminal of the switch. The controller is coupled to respective output terminals of the first and second comparators. And, the controller is configured to: detect a zero voltage condition across the switch based on an output of the first comparator, and, in response, cause a control signal to be applied to the control terminal of the switch, wherein the control signal causes the switch to close. Detect an ON condition at the control terminal of the first switch based on an output of the second comparator. Determine a time difference, the time difference being a difference in time from detecting the zero voltage condition across the switch and detecting the ON condition at the control terminal of the switch. And, adjusting a timing of when the control signal is applied to the control terminal of the switch so as to reduce the time difference.

This and other implementations can each optionally include one or more of the following features.

The reference voltage can be selected based on characteristics of the switch. The switch can be a field effect transistor, where the control terminal is a gate of the transistor, the first terminal is one of a source or a drain of the transistor, and the second terminal is the other of the source or the drain of the transistor. The reference voltage can be selected based on the threshold voltage of the transistor. The controller can be one of: a microcontroller, a computer processor, a field programmable logic array (FPGA), or an application specific integrated circuit (ASIC).

In some implementations, the zero voltage switching device includes a PWM generator coupled with the controller, where the PWM generator includes an output terminal electrically connected to the control terminal of the switch. The control signal can be a pulse width modulated signal, and the controller can be configured to control characteristics of the pulse width modulated signal. Adjusting the timing of when the control signal is applied to the control terminal of the switch can include adjusting a phase of the pulse width modulated signal.

In a fourth aspect, the disclosure features a zero voltage switching device including a switch, a first comparator, a second comparator, and control circuitry. The switch includes a first terminal, a second terminal, and a control terminal. The first comparator includes a first-comparator output terminal and a first-comparator first input terminal electrically connected to the first terminal of the switch. The second comparator includes a second-comparator output terminal, a second-comparator first input terminal electrically connected to a first reference voltage, and a second-comparator second input terminal electrically connected to the control terminal of the switch. The control circuitry is coupled with the first-comparator output terminal and the second-comparator output terminal. In addition, the control circuitry is configured to: determine a phase difference between a first-comparator output signal and a second-comparator output signal, generate a second reference voltage based the phase difference, and cause a control signal to be applied to the switch control terminal upon detecting that a voltage signal at one of the first terminal or second terminal of the switch has crossed a voltage value equal to the second reference voltage.

In some implementations, the control circuitry includes, a phase detection circuit, an integrator circuit, a third comparator, a flip-flop, and a controller. The phase detection circuit can be coupled with the first-comparator output terminal and the second-comparator output terminal. The integrator circuit can be coupled with the phase detection circuit. The third comparator can include a third-comparator output terminal, a third-comparator first input terminal electrically connected to the first terminal of the switch, and a third-comparator second input terminal coupled with the integrator circuit. The flip-flop can include a reset terminal, a clock terminal electrically connected to the third-comparator output terminal, and an output terminal electrically connected to the control terminal of the switch. And, the controller can be coupled with the reset terminal of the flip-flop, and configured to provide a reset signal to the flip-flop.

The controller can be configured to provide the reset signal to turn the switch OFF after a switch ON duration. The switch can be a field effect transistor, where the control terminal is a gate of the transistor, the first terminal is one of a source or a drain of the transistor, and the second terminal is the other of the source or the drain of the transistor.

The first reference voltage can be selected based on the threshold voltage of the transistor. The phase detection circuit can be to determine a phase difference between an output signal from the first comparator and an output signal from the second comparator. The controller can be a PWM generator and the reset signal is a PWM signal.

Particular implementations of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. Implementations may permit the use of lower operating voltages for tuning circuit components. Some implementations may reduce voltage and current stresses on tunable circuit components. Some implementations may permit dynamic balancing of resonator coils. Some implementations may improve the accuracy of zero voltage switching (ZVS) controls.

Embodiments of the devices, circuits, and systems disclosed can also include any of the other features disclosed herein, including features disclosed in combination with different embodiments, and in any combination as appropriate.

DETAILED DESCRIPTION

Wireless energy transfer systems described herein can be implemented using a wide variety of resonators and resonant objects. As those skilled in the art will recognize, important considerations for resonator-based power transfer include resonator quality factor and resonator coupling. Extensive discussion of such issues, e.g., coupled mode theory (CMT), coupling coefficients and factors, quality factors (also referred to as Q-factors), and impedance matching is provided, for example, in U.S. patent application Ser. No. 13/428,142, published on Jul. 19, 2012 as US 2012/0184338, in U.S. patent application Ser. No. 13/567,893, published on Feb. 7, 2013 as US 2013/0033118, and in U.S. patent application Ser. No. 14/059,094, published on Apr. 24, 2014 as US 2014/0111019. The entire contents of each of these applications are incorporated by reference herein.

Power transfer systems may rely on electronic circuits such as rectifiers, AC (Alternating Current) to DC (Direct Current) converters, impedance matching circuits, and other power electronics to condition, monitor, maintain, and/or modify the characteristics of the voltage and/or current used to provide power to electronic devices. Power electronics can provide power to a load with dynamic input impedance characteristics. In some cases, in order to enable efficient power transfer, a dynamic impedance matching network is provided to match varying load impedances to that of the power source.

In some applications such as wireless power transfer, load impedances for a wireless power supply device may vary dynamically. In such applications, impedance matching between a load, such as a resonator coil, and a power supply of the device may be required to prevent unnecessary energy losses and excess heat. For example, the impedance associated with a resonator coil may be dynamic, in which case, a dynamic impedance matching network can be provided to match the varying power supply impedance (e.g., a device resonator) to that of the device. In the case of a wirelessly powered device, power supply impedances (e.g., a device resonator coil) may be highly variable. Therefore, an impedance matching network can be supplied between the device resonator coil and the power source of the device (e.g., battery or battery charging circuitry) to promote efficient transfer of power. Accordingly, power transfer systems transferring and/or receiving power via highly resonant wireless energy transfer, for example, may be required to configure or modify impedance matching networks to maintain efficient power transfer. The power electronics used in existing devices may not be capable of accurately detecting or measuring impedance mismatches or of rapidly accounting for impedance variations.

While the impedance matching circuits, methods, and systems disclosed herein are discussed in the context of a wireless power transfer system, it should be appreciated that they may be useful with other electronic devices as well. In some cases, the disclosed control circuitry and ZVS techniques may be used in other applications such as, for example, high power amplifiers and power supplies.

FIG. 1shows a block diagram of an example of a wireless power transfer system100. The system100includes a wireless power source102and a wirelessly powered or wirelessly charged device104. Wirelessly powered or wirelessly charged devices104can include, for example, electronic devices such as laptops, smartphones, tablets, and other mobile electronic devices that are commonly placed on desktops, tabletops, bar tops, and other types of surfaces. The device104includes a device resonator108D, device power and control circuitry110, and a wirelessly powered or wirelessly charged electronic device112, to which either DC or AC or both AC and DC power is transferred. The wireless power source102includes source power and control circuitry106and a source resonator108S. The electronic device112or devices that receive power from the device resonator108D and device power and control circuitry110can be, for example, an electronic device such as a laptop, smartphone, and other mobile electronic devices. The device resonator108D and device circuitry110delivers power to the device/devices112that can be used to recharge the battery of the device/devices, power the device/devices directly, or both when in the vicinity of the source resonator108S.

The power source102can be powered from a number of DC or AC voltage, current or power sources including, for example, a USB (Universal Serial Bus) port of a computer. In addition, the source102can be powered from the electric grid, from a wall plug, from a battery, from a power supply, from an engine, from a solar cell, from a generator, or from another source resonator. The source power and control circuitry106can include circuits and components to isolate the source electronics from the power supply, so that any reflected power or signals are not coupled out through the source input terminals.

The source power and control circuitry106can drive the source resonator108S with alternating current, such as with a frequency greater than 10 kHz and less than 100 MHz (e.g., 6.78 MHz). The source power and control circuitry106can include, for example, impedance matching circuitry, a DC-to-DC converter, an AC-to-DC converter, or both an AC-to-DC converter and a DC-to-DC converter, an oscillator, and a power amplifier.

The device power and control circuitry110can be designed to transform alternating current power from the device resonator108D to stable direct current power suitable for powering or charging one or more devices112. The device power and control circuitry110can be designed to transform an alternating current power at one frequency (e.g., 6.78 MHz) from the device resonator to alternating current power at a different frequency suitable for powering or charging one or more devices112. The power and control circuitry can include, for example, impedance matching circuitry, rectification circuitry, voltage limiting circuitry, current limiting circuitry, AC-to-DC converter circuitry, DC-to-DC converter circuitry, DC-to-AC converter circuitry, AC-to-AC converter circuitry, and battery charge control circuitry.

The power source102and the device104can have tuning capabilities, for example, dynamic impedance matching circuits, that allow adjustment of operating points to compensate for changing environmental conditions, perturbations, and loading conditions that can affect the operation of the source and device resonators and the efficiency of the energy transfer. The tuning capability can also be used to multiplex power delivery to multiple devices, from multiple sources, to multiple systems, to multiple repeaters or relays, and the like. The tuning capability can be controlled automatically, and may be performed continuously, periodically, intermittently or at scheduled times or intervals. In some implementations, manual input can be used to configure a control algorithm for tuning the impedance matching circuits.

The power source102and the device104resonators may be separated by many meters or they may be very close to each other or they may be separated by any distance in between. The source and device resonators108S,108D may be offset from each other laterally or axially. The source and device resonators108S,108D may be directly aligned (no lateral offset). The source and device resonators108S,108D may be oriented so that the surface areas enclosed by their inductive elements are approximately parallel to each other. The source and device resonators108S,108D may be oriented so that the surface areas enclosed by their inductive elements are approximately perpendicular to each other, or they may be oriented for any relative angle (0 to 360 degrees) between them. Such variations in the physical arrangement between the source and device resonators108S,108D may affect power coupling between the resonators108S,108D, and thereby, alter impedances exhibited by the resonators108S,108D to the source power and control circuitry106or device power and control circuitry110, respectively.

FIG. 2shows a block diagram of an example wireless power transfer system200including an impedance matching network (IMN)204and IMN control circuitry208. The system200can, for example, be implemented as part of either the wireless power source102or the wirelessly powered or charged device104ofFIG. 1. The system200includes a power supply202, an IMN204, a load206, and IMN control circuitry208. The load206can be, for example, the source resonator108S of the wireless power source102. In another example, the power supply202can be the source power and control circuitry106of the wireless power source102. The power supply202can be the device resonator108D of the device104. The load206can be the electronic device112powered by or a battery of the electronic device112charged by the device resonator108D. The impedance exhibited by either the load206or the power supply202may be dynamic and vary based on, for example, a physical position of a device104(e.g., a device resonator108D) in relation to a wireless power source102(e.g., a source resonator108S).

The impedance-matching network204can be designed to maximize the power delivered between power supply202and the load206at a desired frequency (e.g., 6.78 MHz). The impedance matching components in the IMN204can be chosen and connected so as to preserve a high-Q value of the resonator. Depending on the operating conditions, the components in the IMN204can be automatically tuned to control the power delivered from the power supply202to the load206, for example, to maximize efficient transfer of power from a power supply202to a source resonator (e.g., load206of a wireless power source102).

The IMN204components can include, for example, a capacitor or networks of capacitors, an inductor or networks of inductors, or various combinations of capacitors, inductors, diodes, switches, and resistors. The components of the impedance matching network can be adjustable and variable and can be controlled to affect the efficiency and operating point of the system. The impedance matching can be performed by controlling the connection point of the resonator, adjusting the permeability of a magnetic material, controlling a bias field, adjusting the frequency of excitation, and the like. The impedance matching can use or include any number or combination of varactors, varactor arrays, switched elements, capacitor banks, switched and tunable elements, reverse bias diodes, air gap capacitors, compression capacitors, barium zirconium titanate (BZT) electrically tuned capacitors, microelectromechanical systems (MEMS)-tunable capacitors, voltage variable dielectrics, transformer coupled tuning circuits, and the like. The variable components can be mechanically tuned, thermally tuned, electrically tuned, piezo-electrically tuned, and the like. Elements of the impedance matching can be silicon devices, gallium nitride devices, silicon carbide devices, and the like. The elements can be chosen to withstand high currents, high voltages, high powers, or any combination of current, voltage and power. The elements can be chosen to be high-Q elements.

The IMN control circuitry208monitors impedance differences between the source202and the load206and provides control signals to the IMN204to tune the IMN204or components thereof. In some instances, the IMN control circuitry208can include ZVS circuitry to reduce power losses and increase the overall efficiency of the circuit. For example, ZVS circuitry can control switching operations within the IMN204to occur when a voltage (e.g., a voltage across one or more components) is near or at zero. In so doing, the IMN control circuitry208may minimize transients and power losses.

In some implementations, the IMN204can include a fixed IMN and a dynamic IMN. For example, a fixed IMN may provide impedance matching between portions of the system with static impedances or to grossly tune a circuit to a known dynamic impedance range. In some implementations, a dynamic IMN can be further composed of a coarsely adjustable IMN and a finely adjustable IMN. For example, the coarsely adjustable IMN can permit coarse impedance adjustments within a dynamic impedance range and the finely adjustable IMN can be used to fine tune the overall impedance of the IMN204. In another example, the coarsely adjustable IMN can attain impedance matching within a desirable impedance range and the finely adjustable IMN can achieve a more precise impedance around a target within the desirable impedance range.

FIG. 3depicts an example of a dynamically tunable capacitor circuit300. The tunable capacitor circuit300includes two capacitors302a,302bof equal capacitance (C) electrically connected in series with a ground connection310between them. Each capacitor302a,302bhas an associated shorting switch304a,304belectrically connected in parallel with the respective capacitor302a,302b. The shorting switches304a,304bcan be transistors such as, for example, metal-oxide-semiconductor field-effect transistors (MOSFET), junction gate field-effect transistors (JFET), or bipolar junction (BJT) transistors. Both the capacitors302a,302band switches304a,304bcan be ground referenced, for example, for use in high voltage circuits such as circuits including wireless power transmission coils. For example, connecting one terminal each of the capacitors302a,302band each switch304a,304bto ground may permit the use of lower switch control voltages (e.g., less than 5 V) and eliminate a need for level shifting or other special control or isolation circuitry.

The effective capacitance of the combined capacitors302a,302bcan be controlled by varying the period of time that the capacitors302a,302bare shorted during portions of a cycle of an AC input signal (IAC) applied to the capacitors302a,302b. In other words, effective capacitance can be controlled by varying the period of time that the switches304a,304bare closed (or “ON” in the case of transistor switches (TON)). Together, the capacitors302a,302band switches304a,304bare controlled so as to function as a single capacitor with an effective capacitance

(Ceff)⁢⁢equal⁢⁢to⁢⁢Ceff=C2⁢(1/(1-TON*f)),
where f is the frequency (e.g., 6.78 MHz) of the AC signal (IAC) applied to the capacitors302a,302b. The tunable capacitor circuit300, thus, has a range of effective capacitance (Ceff) from 0 to C/2. The tuning resolution, or precision, of the tunable capacitor circuit300is determined by the number of possible values for TONin some implementations. Thus, the tuning resolution of the tunable capacitor circuit300need be limited only by the timing resolution of TON.

FIGS. 4A-4Cdepict examples of AC voltage signals applied to the tunable capacitor circuit300. Referring toFIGS. 3, 4A, and 4B,FIGS. 4A and 4Bdepict graphs400and420of voltage signals at Va and Vb in the tunable capacitor circuit300. The voltage signal at Va represents the voltage across capacitor302a, and the voltage signal at Vb represents the voltage across capacitor302b. The voltage signals are shown with a frequency of 6.78 MHz.

InFIG. 4A, for example, the switches304a,304bare closed (i.e., capacitors302a,302bare shorted) for 15 ns during each cycle of the voltage signals Va and Vb. In other words, TONis equal to 15 ns inFIG. 4Aresulting in a peak amplitude of approximately 50V. InFIG. 4B, for example, the switches304a,304bare closed (i.e., capacitors302a,302bare shorted) for 60 ns during each cycle of the voltage signals Va and Vb. In other words, TONis equal to 60 ns inFIG. 4Bresulting in a peak amplitude of approximately 33V. As seen by the difference in amplitude between signals Va and Vb inFIG. 4Acompared to signals Va and Vb inFIG. 4Ba longer TONtime, as shown inFIG. 4B, results in a lower effective capacitance (or effective impedance) of the tunable capacitor circuit300as indicated by the lower voltage drop across the respective capacitors302a,302b. A graph440of the overall voltage across the tunable capacitor circuit300is shown inFIG. 4C. The voltage signal inFIG. 4Crepresents Va-Vb, the voltage across both capacitors302a,302b, with a 60 ns TONvalue.

In addition, the switches304a,304bcan be timed to close (turn ON) when the voltage across the associated capacitor302a,302b(Va or Vb) crosses zero. This timing is illustrated by the zero crossings402and404ofFIGS. 4A and 4Brespectively and is referred to as zero voltage switching (ZVS). Precisely time switching of the switches304a,304bmay ensure that the voltage across the tunable capacitor circuit300is continuous, and also prevent both large current transients and needless power losses.

Referring again toFIG. 3, the switches304a,304b, are controlled by control circuitry306coupled with respective control terminals (e.g., transistor gate terminals) of switches304a,304b. The control circuitry306controls the effective capacitance of the capacitors by controlling TONof the switches304a,304bin accordance with a tuning input. In addition, the control circuitry306controls the ZVS timing of the switches304a,304bby monitoring the voltage or current of a signal applied to the capacitors302a,302b. The control circuitry306can include, for example, a microcontroller, a computer processor, a field programmable logic array (FPGA), or an application specific integrated circuit (ASIC). The control circuitry306can include or be coupled to a computer readable storage device such as, for example, random access memory, flash memory, or other appropriate memory device.

Comparators308a,308bcan be used to detect when the voltage across the respective capacitor302a,302bcrosses zero. For example, the input terminals of comparator308aare electrically connected across capacitor302a, and the input terminals of comparator308bare electrically connected across capacitor302b. The respective output terminals of the comparators308a,308bare coupled with the control circuitry306.

The control circuitry306can detect the zero crossings based on the output signals of comparators308a,308band, upon detecting a zero crossing, close the switches304a,304bfor a duration of TON. For example, the control circuitry306can detect the zero crossing of the voltage across the capacitor302abased on the rising or falling edge of the comparator's308aoutput signal. In response, the control circuitry306can apply a control signals to the control terminal switch304ato close the switch (e.g., turn the transistor ON) and begin shorting the capacitor302a. After the duration TONexpires, the control circuitry306re-opens the switch304a(e.g., turns the transistor OFF).

The TONduration can be controlled by, for example, a counter that is part of the control circuitry306. The duration of the counter (TON) can be set based on a tuning input signal to the control circuitry306. For example, an IMN control circuitry208(shown inFIG. 2) can transmit one or more tuning control signals to the control circuitry306. The control circuitry306can vary a duration of the counter (TON) based on the received tuning control signal(s).

The comparators308a,308bcan produce a two-level output signal that alternates when the voltage across the respective capacitor302a,302bcrosses zero. Moreover, the value of the comparator output signal can indicate the polarity of the voltage signals. For example, as shown inFIG. 3, the non-inverting (“+”) input terminal of each comparator308a,308bis electrically connected to the grounded terminal of its respective capacitor302a,302b. The inverting (“−”) input terminal of each comparator308a,308bis electrically connected to the other (non-grounded) terminal of its respective capacitor302a,302b. In this configuration, each comparator308a,308bwill output a high signal value when the voltage across its respective capacitor302a,302bis negative and a low signal when the voltage across its respective capacitor302a,302bis positive.

In some implementations, the comparators308a,308bcan be connected with the input terminals swapped. That is, the inverting (“−”) input terminal of each comparator308a,308bcan be electrically connected to the grounded terminal of its respective capacitor302a,302b. The non-inverting (“+”) input terminal of each comparator308a,308bcan be electrically connected to the other (non-grounded) terminal of its respective capacitor302a,302b. In such a configuration, each comparator308a,308bwill output a high signal value when the voltage across its respective capacitor302a,302bis positive and a low signal when the voltage across its respective capacitor302a,302bis negative.

In some implementations, the effective capacitances of capacitor302aand capacitor302bcan be tuned independently by, for example, shorting each capacitor302a,302bfor a different duration. For example, the TONassociated with each capacitor302a,302bmay be different, thereby, producing a different effective capacitance for each capacitor. Hence, the effective capacitance of capacitor302acan be represented by Ceff_a=Ca/(1−TON_a*f), the effective capacitance of capacitor302bcan be represented by Ceff_b=Cb/(1−TON_b*f), and the overall effective capacitance can be represented by the series combination of Ceff_aand Ceff_b.

In some implementations, the comparators308a,308bcan be replaced by phase detection devices. For example, a voltage or current sensor (e.g., a Rogowski coils) can be used to monitor the voltage across or current through a circuit component (e.g., capacitors302a,302b). A phase detection device or circuitry can detect and track the phase of the voltage or current and the control circuitry306(e.g., a microcontroller or processor) can time the ZVS of the switches304a,304bbased on the phase of the monitored voltage or current. For example, the control circuitry306can determine the zero crossings of the monitored voltage or current based on the detected phase, and control the switches304a,304baccordingly.

In some examples, the tunable capacitor circuit300can be implemented without a ground reference between the capacitors302a,302b. For example, the tunable capacitor circuit300can be isolated from high voltages using isolation circuitry, such as opto-couplers, isolation transformers, and the like, for example.

FIG. 5depicts an example of a wireless energy transfer system500including a dynamically tunable capacitor circuit300. The wireless energy transfer system500includes the tunable capacitor circuit300ofFIG. 3, a split-coil502, an optional fixed IMN508, and power source or device510that either provides power to the split-coil502(e.g., power source102) or receives power from the split-coil502(e.g., a wirelessly powered/charged electronic device112).

The tunable capacitor circuit300is coupled with the split-coil502and can be tuned to adapt the impedance of the wireless energy transfer system500to a varying impedance of the split-coil502. As described in reference toFIG. 1above, the split-coil502can be used to wirelessly transfer energy to or receive energy from another resonator coil (e.g., a corresponding device or source resonator coil, respectively). The effective impedance of the split-coil502may vary dynamically based on, for example, environmental factors (e.g., interfering objects), orientation between resonator coils, distance between resonator coils, etc. The tunable capacitor circuit300can be adjusted to compensate for such variations in the effective impedance of the split-coil502.

The split-coil502includes two windings504and506that are coupled so as to function as one resonator coil. In embodiments, the two windings504and506are magnetically coupled. In some implementations, the split-coil502can be two separate coils coupled by a capacitor. Each winding504,506has two input terminals507. The tunable capacitor circuit300is connected in series between the windings504,506to one input terminal507of each winding504,506. The split-coil design allows for a ground-reference point to be established between the windings504,506of the split-coil502. As a result, impedance matching circuitry such as the tunable capacitor circuit300and capacitors C1, C2, and C3can be connected to the resonator502and operated at lower voltages without the need of isolation circuits such as galvanic isolation circuits.

The wireless energy transfer system500also can include capacitors C1, C2, and/or C3. These capacitors can be either fixed or variable capacitors. Each of capacitors C1, C2, and C3can represent, for example, a number or combination of varactors, varactor arrays, capacitor banks, air gap capacitors, compression capacitors, barium zirconium titanate (BZT) electrically tunable capacitors, or microelectromechanical systems (MEMS)-tunable capacitors. For example, capacitors C1, C2, and/or C3can represent a coarsely adjustable impedance matching network used in combination with the tunable capacitor circuit300. For instance, capacitors C1, C2, and/or C3can be used to grossly tune a circuit to a known dynamic impedance range or can provide coarse impedance adjustments while the tunable capacitor circuit300provides fine impedance adjustments. For example, the capacitors C1, C2, and/or C3can permit coarse impedance adjustments within a dynamic impedance range and the tunable capacitor circuit300can be used to perform fine impedance adjustments.

Although circuit elements C1, C2, and/or C3are represented and described as capacitors, in some implementations, they can be replaced by or used in combination with other impedance matching components. For example, capacitors C1, C2, and/or C3can be replaced by or used in combination with inductors, diodes, and resistors.

As noted above, in some implementations, the effective capacitances of capacitor302aand capacitor302bcan be tuned independently by, for example, shorting each capacitor302a,302bfor a different duration. For example, when combined with a split-coil502, independent tuning of capacitors302a,302bmay be used to correct for imbalances in the respective windings504,506of the split-coil502. For example, a second resonator coil (e.g., a resonator coil to which power is being transferred) may be placed next to the split-coil502, but misaligned slightly so as to create an impedance imbalance between the windings504,506. For example, the impedance of winding504may become more inductive than that of winding506. The wireless energy transfer system500can correct for such imbalance by, for example, adjusting TON_ato increase the effective capacitance of capacitor302a, adjusting TON_bto decrease the effective capacitance of capacitor302b, or adjusting TON_aand TON_bin combination to re-balance the windings504,506.

The fixed IMN508can include, for example, a capacitor or networks of capacitors, an inductor or networks of inductors, or various combinations of capacitors, inductors, diodes, and resistors. For example, the fixed IMN508may provide impedance matching between portions of the system500with static impedances or to grossly tune the system500to a known dynamic impedance range (e.g., a dynamic impedance range of the split-coil502).

FIG. 6depicts the dynamically tunable capacitor circuit600with an example of a first implementation of the control circuitry606. The control circuitry606includes a flip-flop602a,602band a TONcounter604a,604bassociated with each capacitor302a,302b. The flip-flops602a,602bare illustrated as D flip-flops, however, they may be implemented using other types of flip-flops or gated latch circuits. As illustrated inFIG. 6, the control circuitry606is symmetric, so, for simplicity, the control circuitry will be described in the context of one capacitor (capacitor302a).

The comparator308aand the flip-flop602ain combination control the ZVS of the switch304a. The comparator308achanges the state of its output signal when the voltage across the capacitor302a(Va) crosses zero, as described above in reference toFIG. 3. The comparator308aoutput signal is applied to an edge triggered gating (clock) input of the flip-flop602a. The input (D) of the flip-flop602ais tied to a high (e.g., 5V) input signal VDD (e.g., 5V). The output terminal (Q) of the flip-flop602ais electrically connected to the control terminal of the switch304a(e.g., transistor gate) and a counter-start terminal of the TONcounter504a. When the flip-flop602adetects an appropriate edge (rising or falling) in the comparator308aoutput signal, the flip-flop turns switch304aON to short capacitor302aand triggers the TONcounter604ato begin timing the duration TON.

An output terminal of the TONcounter604ais electrically connected to the CLR input terminal of the flip-flop602a. Upon expiration of the duration TON, the TONcounter604agenerates a CLR signal to clear the output of the flip-flop602a(e.g., reset to low or “0”), thereby, turning the switch304aOFF. In addition, the TONcounter604acan receive a tuning input signal to set the duration of TONand control the effective capacitance of the capacitor302a. Furthermore, the resolution of the effective capacitance for capacitor302ais determined by the count increment of the TONcounter604a. For example, a TONcounter604ahaving a smaller count increment will allow for more precise control of the effective capacitance of the capacitor302a.

FIG. 7depicts the dynamically tunable capacitor circuit700with an example of a second implementation of the control circuitry706. The control circuitry706includes a controller702, counters704a,704b, a pulse width modulation (PWM) generator707and gate drivers708a,708b. The tunable capacitor circuit700is similar to that described in reference toFIG. 3, and includes an additional set of comparators710a,710b.

The controller702can be, for example, a microcontroller, a computer processor, an FPGA, or an ASIC. The controller702can include or be coupled to a computer readable storage device such as, for example, random access memory, flash memory, or other appropriate memory device. In some examples, the counters704a,704bcan be internal counters in the controller702. The controller702receives one or more input tuning signals and controls the PWM generator707to adjust the effective capacitance of the capacitors302a,302bbased on the input tuning signal(s).

The PWM generator707generates PWM signals used to control the switches304a,304b. The ON timing, or ZVS timing, of the switches304a,304bis controlled by the phase of the PWM signals and the OFF timing, or TON, is controlled by the duty cycle of the PWM signals. For example, the duty cycle is increased to increase the TONduration and reduced to decrease the TONduration. The period of the PWM signals is configured to match that of the signal applied to the capacitors302a,302b(Va, Vb). Thus, for example, for a 6.78 MHz signal applied to the capacitors302a,302b, the period of the PWM signals would be approximately 147.5 ns. The gate drivers708a,708bamplify the PWM signals as applicable to operate the switches304a,304b.

As described in reference to control circuitry306ofFIG. 3, the control circuitry706controls the ZVS of the switches304a,304band the effective capacitance of the capacitors302a,302bby controlling the shorting duration TON. In addition, the control circuitry706adjusts the ZVS timing for turning the switches304a,304bON to account for switching control delays. For example, electronic circuitry has some inherent signal processing and propagation delays, which become more readily apparent when circuits are operated at higher frequencies because delay times represent greater portions of operating signal periods. The control circuitry706can monitor such delays and adjust the ZVS timing for the switches304a,304baccordingly.

The comparators710a,710bare used to monitor the control signals applied to the switches304a,304b. More specifically, when transistors (e.g., MOSFETs) are used for the switches304a,304b, the comparators710a,710bcan be configured to monitor for a voltage slightly below the threshold voltage, for example, the threshold voltage less a voltage offset (δ) (Vth—δ). The magnitude of the voltage offset (δ) is less than the magnitude of the threshold voltage (Vth) of the associated transistor.

For example, as shown inFIG. 7, the non-inverting (“+”) input terminal of each comparator710a,710bis electrically connected to the control terminal (e.g., gate) of its respective switch304a,304b. The inverting (“−”) input terminal of each comparator710a,710bis electrically connected to a reference voltage V1or V2for the respective switch304a,304b. The reference voltages, V1and V2, can be set at the threshold voltage (Vth) of the associated switch304a,304bor the threshold voltage less a voltage offset (Vth−δ). In this configuration, each comparator710a,710bwill output a high signal value when the voltage of the gate drive signal for its respective switch304a,304bexceeds the applicable reference voltage V1or V2, thereby, indicating that the respective switch304a,304bis ON.

As illustrated inFIG. 7, the control circuitry706is symmetric, so, for simplicity, the control circuitry will be described in the context of controlling only one of the switch/capacitor pairs (switch304/capacitor302a). The counter704aand controller702control the ZVS timing for the switch304a. The counter704areceives timing input signals from both comparator308aand comparator710a. As described above, the output signal of comparator308aindicates when the voltage across the capacitor302a(Va) crosses zero, and the output signal of comparator710aindicates when the switch304aturns ON. The counter704ameasures the delay in turning the switch304aON (“switching delay”) by measuring the timing difference between the output signals of comparator308aand comparator704a. For example, the counter704acan initiate a timer when an appropriate edge (rising or falling) of the output signal from comparator308ais received, and stop the timer when the output signal of comparator710aindicates that sufficient drive voltage is being applied to switch304ato turn switch304aON.

The measured switching delay is provided to the controller702. The controller702provides control signals to the PWM generator707to shift the phase of the PWM signal sent to gate driver708ain order to decrease the switching delay for switch304a. For example, the phase of the PWM signal sent to gate driver708acan be advanced by an amount equivalent to the measured switching delay. In some examples, the controller702can monitor the switching delay each time the switch304ais turned ON, and make adjustments to the PWM signal as appropriate. In some examples, the controller702can adjust the PWM signal until the switching delay is minimized. That is, the controller702can adjust the PWM signal until the switching delay is zero or approximately zero within the limitations of the circuit components (e.g., within the precision of the counters704a,704b).

FIG. 8depicts the dynamically tunable capacitor circuit800with an example of a third implementation of the control circuitry806. The control circuitry806includes a controller802, phase detection circuits804a,804b, integrator circuits805a,805b, comparators807a,807b, flip-flops809a,809b, and gate drivers808a,808b. The tunable capacitor circuit800is similar to that described in reference toFIG. 3, and includes voltage divider circuits812a,812band an additional set of comparators810a,810b.

The controller802can be, for example, a microcontroller, a computer processor, an FPGA, or an ASIC. The controller802can include or be coupled to a computer readable storage device such as, for example, random access memory, flash memory, or other appropriate memory device. In some examples, the controller802can be a PWM generator.

As described in reference to control circuitry306ofFIG. 3, the control circuitry806controls the ZVS of the switches304a,304band the effective capacitance of the capacitors302a,302bby controlling the shorting duration TON. In addition, the control circuitry806adjusts the ZVS timing for turning the switches304a,304bON to account for switching control delays. For example, electronic circuitry typically has at least some inherent signal processing and propagation delays, which become more readily apparent when circuits are operated at higher frequencies because delay times represent greater portions of operating signal periods. The control circuitry806can monitor such delays and adjust the ZVS timing for the switches304a,304baccordingly.

The comparators810a,810bmonitor the control signals applied to the switches304a,304b. More specifically, when transistors (e.g., MOSFETs) are used for the switches304a,304b, the comparators810a,810bdetect when the gate drive signals meet the threshold voltage (Vth) of the associated transistor. In some examples, the comparators810a,810bmonitor for a voltage slightly below the threshold voltage, for example, the threshold voltage less a voltage offset (δth) Vth−δth. The voltage offset (δth) can be positive if soft switching is desired, or negative if hard switching is desired. The magnitude of the voltage offset (δth) is less than the magnitude of the threshold voltage (Vth) of the associated transistor.

For example, as shown inFIG. 8, the non-inverting (“+”) input terminal of each comparator810a,810bis electrically connected to the control terminal (e.g., gate) of its respective switch304a,304b. The inverting (“−”) input terminal of each comparator810a,810bis electrically connected to a reference voltage V1or V2for the respective switch304a,304b. The reference voltages, V1and V2, can be set at the threshold voltage (Vth) of the associated switch304a,304bor the threshold voltage less a voltage offset (Vth−δth). In this configuration, each comparator810a,810bwill output a high signal value when the voltage of the gate drive signal (Vg) for its respective switch304a,304bexceeds the applicable reference voltage V1or V2, thereby, indicating that the respective switch304a,304bis ON. In some implementations, the reference voltages V1or V2are equal. Further, in some implementations, the inverting input terminals of both comparator810aand810bcan be electrically connected to a common reference voltage (e.g., V1or V2). Alternatively, reference voltages V1and V2can be different and can be provided as independent reference voltages.

The voltage divider circuits812a,812bare optionally used in tunable capacitor circuits800that operate at high voltages that would otherwise damage comparators308a,308b,807a, and807b, and possible other portions of the control circuitry806. The voltage divider circuits821a,812bstep the operating voltages of the tunable capacitors circuits800(e.g., Va and Vb) down to voltage levels that the control circuitry806can manage without incurring damage. Each voltage divider circuit812a,812bincludes a network of resistive elements816and impedance elements814(e.g., capacitors and/or inductors) of appropriate values to step down the voltage from the tunable capacitor circuit for control circuitry806. Although the voltage divider circuits812a,812bare illustrated expressly inFIG. 8, they can be included in any of the preceding implementations as well.

As illustrated inFIG. 8, the control circuitry806is symmetric, so, for simplicity, the control circuitry will be described in the context of controlling only one of the switch/capacitor pairs (switch304a/capacitor302a). However, it should be understood that the following discussion applies equally to the control of other switch capacitor pairs (e.g., switch304b/capacitor302b). The phase detection circuit804ais coupled with the output terminals of comparator308aand810aand receives the output signals of comparator308aand810aas the phase detection circuit804ainput signals. The output of the phase detection circuit804ais coupled with the input to the integrator circuit805a. Together, the phase detection circuit804aand the integrator circuit805agenerate a reference voltage (Vint) input to comparator807a.

The comparator807amonitors the voltage across the switch304aand capacitor302a(Va) with respect to the reference voltage (Vint) generated by the phase detection circuit804aand integrator circuit805a. The non-inverting (“+”) input terminal of comparator807ais coupled with the integrator circuit805a. The inverting (“−”) input terminal of comparator807ais electrically connected to the non-grounded terminals of the switch304aand the capacitor302a. Consequently, the comparator807ainverts its output signal when the signal at the inverting input terminal (e.g., voltage Va or Va divided by the optional voltage divider circuit812a) falls below the reference voltage (Vint).

The flip-flop809areceives the output signal of comparator807aat an edge triggered clock terminal. The rising edge of the comparator807aoutput signal causes the flip-flop809ato output the voltage signal (VDD) applied to the input terminal (D) of the flip-flop809a, thereby, turning on the switch304a. The output terminal (Q) of the flip-flop809ais electrically connected to the control terminal of the switch304a(e.g., transistor gate) through the optional gate driver808a. The controller802is coupled with the reset terminal (CLR) of the flip-flop809aand sends a reset signal to the flip-flop809ato open (or turn OFF) the switch304aafter the capacitor shorting duration TON.

In operation, the phase detection circuit804a, integrator circuit805a, and comparator807acontrol when the switch304acloses (e.g., a transistor turns ON). In other words, the phase detection circuit804a, integrator circuit805a, and comparator807acontrol the ZVS timing for the switch304a. The phase detection circuit804aand integrator circuit805aadaptively generate a reference voltage (Vint) for the comparator807athat accounts for the control circuitry's806switching delay. The reference voltage (Vint) is established so as to cause the comparator807ato begin the switching process (the process of turning switch304aON) an appropriate amount of time before the voltage across the switch304aand capacitor302a(Va) crosses zero such that the switch304awill begin conducting (turn ON) at the zero crossing instead of, for example, several nanoseconds afterwards. The comparator807amonitors the voltage across the switch304aand capacitor302a(Va) and inverts its output signal when Va (or Va divided by the optional voltage divider circuit812a) falls below the output voltage of the of the integrator circuit805a(Vint), thereby, causing the flip-flop809ato turn on the switch304a.

More specifically, as noted above, comparator308amonitors the voltage across the capacitor302a. When the voltage (Va) across capacitor302a(and switch304a) is at (or near) zero, the output signal of comparator308aswitches states. Thus, the output signal of comparator308ais timed to the zero crossings of the voltage across the capacitor302aand switch304a. Also, as noted above, comparator810amonitors the control signal applied to switch304a. When the voltage at the control terminal of switch (Vg) is at or exceeds the threshold voltage (V1), the output signal of comparator810aswitches states. The threshold voltage (V1) is set at or just below the voltage required to turn switch304aON, thus, the output signal of comparator810ais timed to indicate when the switch304aturns ON.

The phase detection circuit804adetermines a phase difference between output signals from comparator308aand comparator810a, which represents the time delay between when the comparator308adetects the voltage Va crossing zero and when the switch304aactually turns ON to short out the capacitor302a. The phase detection circuity804aoutputs a voltage signal proportional to this phase difference each time the switch304ais turned ON. The integrator circuit805asums the phase detection circuity804aoutput signals, the result of which is provided as a reference voltage (Vint) for the non-inverting input terminal of comparator807a. Because the reference voltage (Vint) applied to comparator807ais slightly above zero, the comparator807awill begin the switching process for switch304abefore the voltage Va actually crosses zero. This provides sufficient time for the voltage at the control terminal of switch304ato build up to a value sufficient to turn the switch304aON when the voltage Va does cross zero.

FIGS. 9A-9Ddepict graphs of exemplary control signals in the control circuitry806.FIG. 9Adepicts a graph900of the voltage across the switch304aand capacitor302a(Va) and the voltage applied to the control terminal of switch304a(Vg) at 1 μs after applying a voltage signal to the tunable capacitor circuit800. The voltage signal Va is a 6.78 MHz sinusoidal signal. The graph900shows the signals Va and Vg before the control circuitry806has had time to adjust for the switching delay902. At point904Va crosses zero volts and the control circuitry806begins applying the gate voltage (Vg) to the control terminal of the switch304a. However, the gate voltage (Vg) does not reach the threshold voltage (e.g., 1.5 V) of the switch304auntil point906. Therefore, due to the switching delay902, the voltage across the switch304aand capacitor302a(Va) is allowed to drop significantly below zero volts before the switch304aturns on at point906. The total switching delay902is approximately 3.63 ns and represents approximately 2.5% of the period of the voltage signal Va.

However, over a short period of time the phase detection circuit804aand integrator circuit805aadjust the reference voltage (Vint) of comparator807ato account for the switching delay902to shift point904and begin applying the gate voltage (Vg) to the switch304aearlier in time. For example,FIG. 9Bdepicts a graph925showing an example of the integrator circuit805aoutput signal (Vint) (also the reference voltage for comparator807a) varying over time. At 1 μs after applying a voltage signal to the tunable capacitor circuit800(point926), the voltage signal Vintis relatively small. Thus, comparator807ais not triggering the flip-flop809ato turn on the switch until the voltage across the switch304aand capacitor302a(Va) is already too close to zero to account for the switching delay. The voltage signal Vintbegins to plateau at approximately 18 μs and ZVS is fairly achieved at approximately 34 μs after applying a voltage signal (point928). Note that continuous reduction in the slope of the voltage signal Vintillustrates the decreasing phase difference between the output signals of comparators308aand810aas the switch timing approaches ZVS.

FIG. 9Cdepicts a graph950of the voltage across the switch304aand capacitor302a(Va) and the voltage applied to the control terminal of switch304a(Vg) at approximately 34 μs after applying a voltage signal to the tunable capacitor circuit800. Here, the control circuitry806begins applying the gate voltage (Vg) to the control terminal at point952of the switch304awhen the voltage Va is approximately 5.5 V. Thus, the gate voltage Vg reaches the threshold voltage (e.g., 1.5 V) of the switch304aat point906within approximately 20 ps of when the voltage signal Va crosses zero (point904). The voltage signal Va still drops slightly below zero, however, more due to ringing than switching delay.

Referring again toFIG. 8, the controller802controls the capacitor shorting duration (TON) (e.g., the time that the switch304ais maintained ON). For example, the controller802can include a timer that is triggered to start when the switch304is turned ON. At the expiration of the timer the controller802sends a reset signal to the flip-flop809acausing the flip-flop809ato turn the switch304aOFF by, for example, ceasing to apply the required voltage to the control terminal of the switch304a. The controller802can vary the value of TONbased on an input signal received by the controller802. For example, the controller802may receive the input signal from an impedance matching network control circuit.

FIG. 9Ddepicts a graph975of the current (IAC) flowing into capacitor302aand the switch304a, the voltage across the switch304aand capacitor302a(Va), and the voltage applied to the control terminal of switch304a(Vg). Graph975illustrates the full operation of control circuitry806. At point952the control circuitry806begins to apply a gate voltage signal (Vg) to the control terminal of the switch304a, slightly before the voltage signal Va crosses zero at point904. At point906the value of the gate voltage signal Vg is sufficient to turn the switch304aON. The controller802resets the flip-flop809aat point976after the shorting duration (TON)980expires. At point978the gate voltage signal decays sufficiently to turn the switch304aOFF and the capacitor302abegins to charge. The controller802turns switch304aOFF during the positive half982of the current IACso that the voltage signal Va is rising.

Referring back toFIG. 8, in some implementations the controller802can be a PWM generator. In such implementations, the PWM generator can output a PWM signal to the reset terminal of the flip-flop809a. The shorting duration (TON) can be controlled by the PWM signal. For example, the frequency of the PWM signal can be matched to that of the voltage signal Va applied to the capacitor302aand the switch304a. The shorting duration (TON) can be controlled by the phase of the PWM signal pulse relative to the phase of the voltage signal Va. For example, the amount of phase delay between the rising edge of the PWM pulse and the zero crossing on the negative slope of the voltage signal Va can be set to achieve a desired shorting duration (TON).

In some implementations, the voltage offset (δth) of reference voltages V1and V2can be adjustable. For example, the voltage offset (δth) can be the output of a digital to analog converter (DAC). The input to the DAC can be a digital output signal from the controller802. For example, an adjustable voltage offset (δth) may permit fine tuning of the ZVS points. For instance, decreasing the magnitude of the voltage offset (δth) biases the control circuitry806towards switching closer to the actual zero crossing point of the applied voltage signal. Furthermore, decreasing the voltage offset (δth) to zero or a negative value can place the control circuitry806into a hard switching mode.

In some implementations, the comparators308a,308bare referenced to ground. That is, the non-inverting inputs of comparators308a,308bare connected to ground, for example, as inFIG. 3. In some implementations, the comparators308a,308bcan be referenced to a slightly positive voltage (VGND+δ). That is, the non-inverting inputs of comparators308a,308bcan be connected to a slightly positive voltage (VGND+δ). In some examples, the δ voltage can be set to reduce the initial switching delay (e.g., that shown inFIG. 9A) and reduce the time required for the control circuitry806to generate an optimal reference voltage (Vint) for comparator805a. In some examples, the δ voltage can be set to bias the control circuitry806more towards hard switching versus soft switching. Furthermore, the δ voltage can be either a preset value or adjustable.

The examples and implementations discussed above are described in reference to performing ZVS on the positive half of a voltage waveform. It should be understood that the implementations discussed can also perform ZVS on the negative half of a voltage waveform. To do so, the polarity of reference signals can be reversed and the connections to the input terminals of appropriate comparators can be switched. In addition, the connections to the input terminals of the comparators shown in the depicted circuits can be switched for use with falling edge triggered devices (e.g., flip-flops) instead of rising edge triggered devices.

In some examples, the control circuitry of each of the above described tunable capacitor circuits can be implemented as ZVS circuitry in other applications. For example, the control circuitry of any of the above described implementations can be used as ZVS control circuitry for various amplifiers or power supplies (e.g., class D or class E switching amplifiers). For example, the ZVS devices and methods described herein can be used to control the switch timing of amplifiers or power supplies to minimize power losses in the amplifier or power supply. Zero voltage amplifier switching may also reduce hard switching effects and electromagnetic interference effects in amplifiers.

For illustrative purposes, the foregoing description focuses on the use of devices, components, and methods in desktop wireless power transfer applications, e.g., power transfer to electronic devices such as laptops, smartphones, and other mobile electronic devices that are commonly placed on desktops, tabletops, and other user work surfaces.

More generally, however, it should be understood that devices that can receive power using the devices, components, and methods disclosed herein can include a wide range of electrical devices, and are not limited to those devices described for illustrative purposes herein. In general, any portable electronic device, such as a cell phone, keyboard, mouse, radio, camera, mobile handset, headset, watch, headphones, dongles, multifunction cards, food and drink accessories, and the like, and any workspace electronic devices such as printers, clocks, lamps, headphones, external drives, projectors, digital photo frames, additional displays, and the like, can receive power wirelessly using the devices, components, and methods disclosed herein. Furthermore, any electrical device, such as electric or hybrid vehicles, motorized wheel chairs, scooters, power tools, and the like, can receive power wirelessly using the devices, components, and methods disclosed herein. In addition the devices, components, and methods disclosed herein may be used for applications outside of wireless power transfer, for example, power factor correction devices, handheld signal analyzers, and the like.

In this disclosure, certain circuit or system components such as capacitors, inductors, resistors, diodes, and switches, are referred to as circuit “components” or “elements.” The disclosure also refers to series and parallel combinations of these components or elements as elements, networks, topologies, circuits, and the like. Further, combinations of capacitors, diodes, transistors, and/or switches are described. More generally, however, where a single component or a specific network of components is described herein, it should be understood that alternative embodiments may include networks for elements, alternative networks, and/or the like.

As used herein, the term “coupled” when referring to circuit or system components is used to describe an appropriate, wired or wireless, direct or indirect, connection between one or more components through which information or signals can be passed from one component to another.

As used herein, the term “direct connection” or “directly connected,” refers to a direct connection between two elements where the elements are connected with no intervening active elements between them. The term “electrically connected” or “electrical connection,” refers to an electrical connection between two elements where the elements are connected such that the elements have a common potential. In addition, a connection between a first component and a terminal of a second component means that there is a path between the first component and the terminal that does not pass through the second component.

The embodiments described herein merely serve to illustrate, but not limit, the features of the disclosure. Other embodiments are also within the scope of the disclosure.