Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly to a semiconductor device package with good shielding and heat dissipation capabilities and a method of manufacturing the same.

2. Description of the Related Art

A semiconductor device package may include an electronic device operating at a particular frequency, such as a radio frequency integrated circuit (RFIC), which may generate electromagnetic interference (EMI). The EMI can become particularly problematic when a layout density of components of the semiconductor device package increases and when the semiconductor device package becomes miniaturized. In addition, heat dissipation of a semiconductor device package is another issue of concern.

SUMMARY

In some embodiments, according to one aspect, a semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first surface, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer. An upper surface of the molding layer and an upper surface of the shielding layer are substantially coplanar.

In some embodiments, according to another aspect, a semiconductor device package includes a circuit layer having a first surface and a second surface opposite the first surface, a first electronic component, a second electronic component, a shielding element, a molding layer and a shielding layer. The first electronic component is disposed over the first surface of the circuit layer. The first electronic component includes a plurality of first conductive pillars extending toward the first surface and electrically connected to the circuit layer. The second electronic component is disposed over the first surface of the circuit layer and the first electronic component. The second electronic component includes a plurality of second conductive pillars extending toward the first surface and electrically connected to the circuit layer, the second electronic component partially overlapping the first electronic component, a length of at least one of the second conductive pillars being larger than a length of at least one of the first conductive pillars. The shielding element is disposed over the first surface and is electrically connected to the circuit layer, and the shielding element is disposed adjacent to at least one side of the first electronic component and to at least one side of the second electronic component. The molding layer encapsulates the first electronic component, the second electronic component and the shielding element. The shielding layer is disposed over the molding layer and is electrically connected to the shielding element. The carrier is disposed over the shielding layer.

In some embodiments, according to another aspect, a method of manufacturing a semiconductor device package includes forming a shielding layer over a carrier; forming a shielding element over the shielding layer; disposing a first electronic component over the shielding layer; disposing a molding layer to encapsulate the shielding layer, the shielding element and the first electronic component; and forming a first circuit layer over the molding layer, the shielding element and the first electronic component.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters to refer to components of the various examples. This repetition is for the purpose of simplicity and clarity and does necessarily imply that components referred to by a same reference numeral and/or letter are identical. For example, some such components may be similar in some respects, but may differ in other respects.

The following description is directed to a semiconductor device package. In some embodiments, the semiconductor device package includes a shielding element disposed over a circuit layer and disposed adjacent to at least one side of an electronic component, and a shielding layer disposed over the electronic component and electrically connected to the shielding element. The shielding layer and the shielding element are configured to function as an EMI shield and a heat sink for the electronic component, and provide a ground path. The following description is also directed to a method of manufacturing a semiconductor device package, as discussed below.

FIG. 1is a cross-sectional view of a semiconductor device package1in accordance with some embodiments of the present disclosure. As shown inFIG. 1, the semiconductor device package1includes a first circuit layer28, a first electronic component20, a shielding element16, a shielding layer14and a molding layer24. The first circuit layer28includes a first surface281facing the first electronic component20, and a second surface282opposite to the first surface281. In some embodiments, the first circuit layer28includes a redistribution layer (RDL) configured to reroute input/output paths corresponding to input/output (I/O) contacts of the first electronic component20. In some embodiments, the first circuit layer28includes one or more conductive wiring layers and one or more dielectric layers, which may be stacked adjacent to or on each other. In some embodiments, a conductive wiring layer proximal to the second surface282may function as or may include bonding pads such as under bump metallurgies (UBMs).

The first electronic component20is disposed over a first surface281of the first circuit layer28, and is electrically connected to the first circuit layer28. In some embodiments, the first electronic component20includes a semiconductor die having an integrated circuit (IC) formed therein. In some embodiments, the first electronic component20includes, but is not limited to, an active component such as an application specific IC (ASIC), a memory component such as a high bandwidth memory (HBM) component or another active component, and/or a passive component such as a capacitor, an inductor, a resistor or the like. In some embodiments, conductive pillars22such as metal pillars are disposed under a bottom surface20B of the first electronic component20, and the first electronic component20is electrically connected to the first circuit layer28through the conductive pillars22. By way of example, the conductive pillars22include, but are not limited to, copper pillars.

The shielding element16is disposed over the first surface281of the first circuit layer28, and is electrically connected to the first circuit layer28. The shielding element16is disposed adjacent to at least one side20S of the first electronic component20. By way of example, the shielding element16may be disposed adjacent to one side20S, two sides20S, three sides20S or more sides20S of the first electronic component20. In some embodiments, the shielding element16surrounds the sides20S of the first electronic component20to shield the first electronic component20from EMI. In some embodiments, the shielding element16is configured to function as a part of a grounding path. In some embodiments, the shielding element16is formed of conductive material such as metal or metal alloy. By way of example, the conductive material may include, but is not limited to, copper, copper alloy, or the like.

The shielding layer14is disposed over the first electronic component20and the shielding element16. In some embodiments, the shielding layer14is formed of conductive material such as metal or alloy. By way of example, the conductive material may include, but is not limited to, copper, copper alloy, or the like. In some embodiments, the shielding layer14is a conformal shielding, covering an upper surface20U of the first electronic component20to provide an EMI shielding effect. In some embodiments, the shielding layer14is configured to function as another part of a grounding path. In some embodiments, the shielding layer14is electrically connected to the shielding element16, forming an EMI shielding cap enclosing the upper surface20U and the sides20S of the first electronic component20. In some embodiments, the shielding layer14is in contact with the first electronic component20, and configured to provide a heat dissipation path for the first electronic component20. In some embodiments, a width W (e.g. a horizontal extension, as shown inFIG. 1) of the shielding element16is larger than a thickness T (e.g. a vertical extension, as shown inFIG. 1) of the shielding layer14. The width W of the shielding element16and the thickness T of the shielding layer14may be modified as appropriate based on desired shielding effect, heat dissipation effect or other considerations.

The molding layer24encapsulates the first electronic component20, the shielding element16and a portion of the shielding layer14. In some embodiments, an upper surface24U of the molding layer24and an upper surface14U of the shielding layer14are substantially coplanar. In some embodiments, the material of the molding layer24includes, but is not limited to, a molding compound such as an epoxy resin or the like, and fillers24F such as silicon oxide fillers in the molding compound. In some embodiments, the fillers24F disposed adjacent to the first circuit layer28have at least one cutting plane. In some embodiments, a first interface S1between the shielding layer14and the shielding element16and a second interface S2between the shielding layer14and the first electronic component20are substantially coplanar.

In some embodiments, the semiconductor device package1further includes first conductors30disposed over the second surface282of the first circuit layer28, and electrically connected to the first circuit layer28. In some embodiments, the first conductors30include conductive bumps such as solder bumps, solder balls, solder pastes or the like. In some embodiments, at least some of the first conductors30are electrically connected to the first electronic component20through the first circuit layer28, and are configured to provide an electrical connection path to another electronic device such as a circuit board or the like. In some embodiments, some other first conductors30are electrically connected to the shielding element16through the first circuit layer28, and are configured to connect to a grounding circuit.

FIG. 2A,FIG. 2B,FIG. 2C,FIG. 2D,FIG. 2E,FIG. 2FandFIG. 2Gillustrate an example of a manufacturing method of the semiconductor device package1in accordance with some embodiments of the present disclosure. As depicted inFIG. 2A, a shielding layer14is formed over a carrier10. In some embodiments, a conductive film12configured to function as a seed layer is formed over the carrier10prior to formation of the shielding layer14. In some embodiments, the conductive film12is a metal film such as a copper film or an alloy film such as a titanium/copper (Ti/Cu) film, which can be formed by pasting, sputtering or any other suitable technique. In some embodiments, the shielding layer14may, but need not, be formed by plating.

As shown inFIG. 2B, a shielding element16is formed over the shielding layer14. In some embodiments, the shielding element16may, but need not, be formed by plating. As shown inFIG. 2C, a first electronic component20is bonded to the carrier10(e.g. via the shielding layer14and/or the conductive film12), and is disposed adjacent to the shielding element16. In some embodiments, the first electronic component20includes conductive pillars22such as conductive posts extending upward.

As shown inFIG. 2D, a molding layer24is disposed over the carrier10to encapsulate the shielding layer14, the shielding element16and the first electronic component20. As shown inFIG. 2E, a portion of the molding layer24is removed to expose the shielding element16. In some embodiments, the portion of the molding layer24is removed by grinding. In some embodiments, the conductive pillars22of the first electronic component20are exposed after grinding.

As shown inFIG. 2F, a first circuit layer28is formed over the molding layer24, the shielding element16, the conductive pillars22and the first electronic component20. In some embodiments, the first circuit layer28is an RDL implemented by alternately forming several conductive wiring layers and several dielectric layers. The first circuit layer28includes a first surface281facing the first electronic component20, and a second surface282opposite to the first surface281. In some embodiments, a conductive wiring layer proximal to the second surface282may function as or may include bonding pads such as under bump metallurgies (UBMs). As shown inFIG. 2G, first conductors30are formed over the second surface282of the first circuit layer28. The carrier10and the conductive film12are removed from the shielding layer14, and a singulation process is performed to form a semiconductor device package1as illustrated inFIG. 1.

The semiconductor device package and manufacturing method of the present disclosure are not limited to the above-mentioned embodiments, and may be implemented according to other embodiments. To streamline the description and for the convenience of comparison between various embodiments of the present disclosure, similar components in each of the following embodiments are marked with same numerals, and are not redundantly described.

FIG. 3is a cross-sectional view of a semiconductor device package2in accordance with some embodiments of the present disclosure. As shown inFIG. 3, different from the semiconductor device package1, the semiconductor device package2further includes a thermal conductive element15between the first electronic component20and the shielding layer14. The thermal conductive element15is formed from a thermal conductive material, and is configured to function as a heat sink for enhancing heat dissipation of the first electronic component20. In some embodiments, a first interface S1between the shielding layer14and the shielding element16and a third interface S3between the shielding layer14and the thermal conductive element15are substantially coplanar.

FIG. 4is a cross-sectional view of a semiconductor device package3in accordance with some embodiments of the present disclosure. As shown inFIG. 4, different from the semiconductor device package1, the semiconductor device package3further includes a second electronic component32and a shielding compartment34(which may be, for example, a conductive post or pillar, such as a metallic conductive post or pillar). The second electronic component32is disposed over the first surface281of the first circuit layer28, and is electrically connected to the first circuit layer28. In some embodiments, the second electronic component32is disposed adjacent to the first electronic component20. The shielding compartment34is disposed over the first surface281of the first circuit layer28and between the first electronic component20and the second electronic component32. In some embodiments, the shielding compartment34is electrically connected to the first circuit layer28and the shielding layer14. The shielding compartment34is configured to block EMI transmission between the first electronic component20and the second electronic component32. In some embodiments, the shielding layer14is in contact with the first electronic component20and the second electronic component32. In some alternative embodiments, conductive elements15may be disposed between the first electronic component20and the shielding layer14, and/or between the second electronic component32and the shielding layer14.

FIG. 5is a cross-sectional view of a semiconductor device package4in accordance with some embodiments of the present disclosure. As shown inFIG. 5, different from the semiconductor device package3, the semiconductor device package4further includes at least one conductive post36and a second circuit layer38. The at least one conductive post36penetrates through the molding layer24and is electrically connected to the first circuit layer28. In some embodiments, the at least one conductive post36is configured to electrically connect the first circuit layer28and the second circuit layer38. In some embodiments, the at least one conductive post36may be, but is not limited to, a metal post such as a copper post. The second circuit layer38is disposed over the molding layer24, the shielding layer14and the at least one conductive post36, and is electrically connected to the shielding layer14and the at least one conductive post36. The second circuit layer38includes a third surface383facing the first circuit layer28, and a fourth surface384opposite to the third surface383. In some embodiments, the second circuit layer38is a redistribution layer (RDL) configured to reroute input/output paths corresponding to input/output (I/O) contacts of the first electronic component20and/or the second electronic component32. In some embodiments, the second circuit layer38includes one or more conductive wiring layers and one or more dielectric layers stacked on each other. In some embodiments, a conductive wiring layer proximal to the fourth surface384may function as or may include bonding pads such as under bump metallurgies (UBMs).

FIG. 6A,FIG. 6B,FIG. 6C,FIG. 6D,FIG. 6E,FIG. 6F,FIG. 6GandFIG. 6Hillustrate an example of a manufacturing method of the semiconductor device package4in accordance with some embodiments of the present disclosure. As depicted inFIG. 6A, a shielding layer14is formed over a carrier10. In some embodiments, a conductive film12configured to function as a seed layer is formed over the carrier10prior to formation of the shielding layer14. In some embodiments, the conductive film12is a metal film such as a copper film or an alloy film such as a titanium/copper (Ti/Cu) film, which can be formed by pasting, sputtering or any other suitable technique. In some embodiments, the shielding layer14may, but need not, be formed by plating.

As shown inFIG. 6B, a shielding element16is formed over the shielding layer14. In some embodiments, the shielding element16may, but need not, be formed by plating. At least one conductive post36is formed over the carrier10(e.g. over the conductive film12). In some embodiments, the at least one conductive post36and the shielding element16are formed concurrently by the same process such as plating. In some embodiments, a shielding compartment34may be formed over the shielding layer14at this stage. As shown inFIG. 6C, a first electronic component20and a second electronic component32are bonded to the carrier10(e.g. via the conductive film12and the shielding layer14). In some embodiments, the first electronic component20and the second electronic component32include conductive pillars22such as conductive posts extending upward. In some embodiments, a thermal conductive element15is formed between at least one of: (i) the first electronic component20and the shielding layer14, and (ii) the second electronic component32and the shielding layer14.

As shown inFIG. 6D, a molding layer24is disposed over the carrier10to encapsulate the shielding layer14, the shielding element16, the conductive post36, the shielding compartment34, the first electronic component20and the second electronic component32. As shown inFIG. 6E, a portion of the molding layer24is removed to expose the shielding element16, the shielding compartment34and the conductive post36. In some embodiments, the portion of the molding layer24is removed by grinding. In some embodiments, the conductive pillars22of the first electronic component20and of the second electronic component32are exposed after grinding.

As shown inFIG. 6F, a first circuit layer28is formed over the molding layer24, the shielding element16, the conductive post36, the shielding compartment34, the first electronic component20and the second electronic component32. In some embodiments, the first circuit layer28is an RDL implemented by alternately forming several conductive wiring layers and several dielectric layers. The first circuit layer28includes a first surface281facing the first electronic component20, and a second surface282opposite to the first surface281. In some embodiments, the conductive wiring layer proximal to the second surface282may function as or may include bonding pads such as under bump metallurgies (UBMs). Then, first conductors30are formed over the second surface282of the first circuit layer28.

As shown inFIG. 6G, the first conductors30are mounted on a supporter11, the semiconductor package may be flipped, and the carrier10and the conductive film12are removed from the shielding layer14. In some embodiments, the supporter11is a tape attached to the second surface of the first circuit layer28and enclosing the first conductors30. In some embodiments, residual conductive film12is removed from the shielding layer14, the molding layer24and the at least one conductive post36by, for example, grinding or etching.

As shown inFIG. 6H, the second circuit layer38is formed over the shielding layer14, the molding layer24and the at least one conductive post36. The second circuit layer38includes a third surface383facing the first circuit layer28, and a fourth surface384opposite to the third surface383. The supporter11is then removed from the first conductors30, and a singulation process is performed to form a semiconductor device package4as illustrated inFIG. 5.

FIG. 7is a cross-sectional view of a semiconductor device package5in accordance with some embodiments of the present disclosure. As shown inFIG. 7, different from the semiconductor device package4, the semiconductor device package5further includes an electronic device50disposed over and electrically connected to the second circuit layer38. In some embodiments, the electronic device50may, but need not, be another semiconductor device package having similar structure as the semiconductor device packages3or4. In some embodiments, the semiconductor device package5further includes second conductors48disposed between and electrically connected to both the second circuit layer38and the electronic device50. In some embodiments, the second conductors48include conductive bumps such as solder bumps, solder balls, solder pastes or the like. In some embodiments, at least some of the second conductors48are electrically connected to the first electronic component20and the second electronic component32through the second circuit layer38, and are electrically connected to the electronic device50. In some embodiments, at least some of the second conductors48and a portion of first conductors30are configured to connect to a grounding circuit.

FIG. 8is a cross-sectional view of a semiconductor device package6in accordance with some embodiments of the present disclosure. As shown inFIG. 8, the semiconductor device package6includes a circuit layer82, a first electronic component70, a second electronic component76, a shielding element66, a molding layer80, a shielding layer62and a carrier60. The first electronic component70is disposed over a first surface821of the circuit layer82. In some embodiments, the circuit layer82is a redistribution layer (RDL) configured to reroute input/output paths corresponding to input/output (I/O) contacts of the first electronic component70and/or the second electronic component76. The first electronic component70includes first conductive pillars72extending toward the first surface821and electrically connected to the circuit layer82. The second electronic component76is disposed over the first surface821of the circuit layer82and at least a portion of the first electronic component70. The second electronic component76includes second conductive pillars78extending toward the first surface821and electrically connected to the circuit layer82. The second electronic component76partially overlaps the first electronic component70(e.g. a portion of the second electronic component76is disposed over the first electronic component70, and another portion of the second electronic component76is not disposed over the first electronic component70), and a length L2of at least one of the second conductive pillars78is larger than a length L1of at least one of the first conductive pillars72. In some embodiments, the first electronic component70and the second electronic component76are semiconductor dies having an integrated circuit formed therein. In some embodiments, each of the first electronic component70and the second electronic component76may, but need not, include any of an active component such as an application specific IC (ASIC), a memory component such as a high bandwidth memory (HBM) component or another active component, and/or a passive component such as a capacitor, an inductor, a resistor or the like.

The shielding element66is disposed over the first surface821and is electrically connected to the circuit layer82. The shielding element66is adjacent to at least one side of the first electronic component70and the second electronic component76. By way of example, the shielding element66may be disposed adjacent one side, two sides, three sides or more sides of the first electronic component70and the second electronic component76. In some embodiments, the shielding element66surrounds the sides of the first electronic component70and the second electronic component76and helps to reduce EMI. In some embodiments, the shielding element66is configured to function as a part of a grounding path. In some embodiments, the shielding element66is formed of conductive material such as metal or alloy. By way of example, the conductive material may include, but is not limited to, copper, copper alloy, or the like.

The molding layer80encapsulates the first electronic component70, the second electronic component76and the shielding element66. The shielding layer62is disposed over the molding layer80and is electrically connected to the shielding element66. In some embodiments, the material of the molding layer80includes, but is not limited to, a molding compound such as an epoxy resin or the like, and fillers such as silicon oxide fillers in the molding compound. The carrier60is disposed over the shielding layer62. In some embodiments, the carrier60is a semiconductor carrier such as a silicon carrier. In some embodiments, the carrier60is configured to enhance robustness and heat dissipation for the semiconductor device package6.

In some embodiments, the semiconductor device package6further includes an insulating layer64disposed between the molding layer80and the shielding layer62. The insulating layer64defines an opening64H, and the shielding layer62and the shielding element66are electrically connected through the opening64H of the insulating layer64.

In some embodiments, the semiconductor device package6further includes conductors86disposed over a second surface822of the circuit layer82and electrically connected to the circuit layer82. In some embodiments, the conductors86include conductive bumps such as solder bumps, solder balls, solder pastes or the like. In some embodiments, at least some of the conductors86are electrically connected to the first electronic component70and/or the second electronic component76through the circuit layer82, and are configured to create an electrical connection path to another electronic device such as a circuit board or the like. In some embodiments, some other conductors86are electrically connected to the shielding element66through the circuit layer82, and are configured to connect to a grounding circuit.

FIG. 9A,FIG. 9B,FIG. 9C,FIG. 9D,FIG. 9EandFIG. 9Fillustrate an example of a manufacturing method of the semiconductor device package6in accordance with some embodiments of the present disclosure. As depicted inFIG. 9A, a shielding layer62is formed over a carrier60. In some embodiments, an insulating layer64is formed over the shielding layer62. The insulating layer64defines one or more openings64H exposing the shielding layer62.

As shown inFIG. 9B, a shielding element66is formed over the shielding layer64. In some embodiments, the shielding element66is electrically connected to the shielding layer64through the opening64H of the insulating layer64. As shown inFIG. 9C, a second electronic component76is bonded to the carrier60(e.g. via the insulating layer64and the shielding layer62), adjacent to the shielding element16. In some embodiments, the second electronic component76includes conductive pillars78such as conductive posts extending upward.

As shown inFIG. 9D, a first electronic component70is formed over at least a portion of the second electronic component76. The first electronic component70includes a plurality of second conductive pillars72extending upward. The second electronic component76partially overlaps the first electronic component70, and a length L2of at least one of the second conductive pillars78is larger than a length L1of at least one of the first conductive pillars72.

As shown inFIG. 9E, a molding layer80is disposed over the carrier10to encapsulate the shielding layer64, the shielding element66, the first electronic component72and the second electronic component76. A portion of the molding layer80is removed to expose the shielding element66. In some embodiments, the portion of the molding layer80is removed by grinding. In some embodiments, the conductive pillars72of the first electronic component70and the conductive pillars78of the second electronic component76are exposed after grinding.

As shown inFIG. 9F, a circuit layer82is formed over the molding layer80, the shielding element66, the first electronic component70and the second electronic component76. In some embodiments, the circuit layer82is an RDL implemented by alternately forming several conductive wiring layers and several dielectric layers. The circuit layer82includes a first surface821facing the first electronic component70and the second electronic component76, and a second surface822opposite to the first surface821. In some embodiments, the conductive wiring layer proximal to the second surface822may function as or may include bonding pads such as under bump metallurgies (UBMs). Conductors86are formed over the second surface822of the circuit layer82to form a semiconductor device package6as illustrated inFIG. 8.

A semiconductor device package of various embodiments of the present disclosure is compatible with wafer level chip scale packaging (WLCSP). The semiconductor device package is compatible with package on package structure, and 2.5 D/3D packaging. The shielding layer and the shielding element can form a conformal EMI shielding for the electronic component(s), and the conformal EMI shielding makes it possible to further reduce the size of the semiconductor device package. The shielding layer may also be configured to function as a heat sink for enhancing heat dissipation for the electronic component(s). The electronic components can partially overlap, and can be electrically connected to a circuit layer. Thus, the size of the semiconductor device package is reduced, and electrical communication is implemented in a shorter path, which increases bandwidth and speed and reduces power consumption.