Power conversion system and voltage sampling device thereof

A voltage sampling system is provided. The voltage sampling system includes a first and a second input paths and a signal-processing module. The first input path includes a first input voltage-dividing resistor unit, a second input voltage-dividing resistor unit and a first DC voltage-dividing resistor unit to generate a first input divided voltage and a first DC bias voltage to further generate a first sampled voltage signal according to a first input voltage and a DC voltage source. The second input path includes a third input voltage-dividing resistor unit, a fourth input voltage-dividing resistor unit and a second DC voltage-dividing resistor unit to generate a second input divided voltage and a second DC bias voltage to further generate a second sampled voltage signal according to a second input voltage and the DC voltage source. The signal-processing module receives the first and the second sampled voltage signals to perform signal processing.

RELATED APPLICATIONS

This application claims priority to Chinese Application Serial Number 201410258433.7, filed Jun. 11, 2014, which is herein incorporated by reference.

BACKGROUND

Field of Invention

The present invention relates to a voltage-sampling technology. More particularly, the present invention relates to a power conversion system and a voltage sampling device.

Description of Related Art

In a power system, a power conversion system has higher requirements of a current/voltage sensor as the grid voltage increases. Conventionally, an electromagnetic transformer is utilized to perform voltage sampling. However, the electromagnetic transformer has shortcomings such as possessing a complex insulation structure, being bulky and being expensive, etc. The electromagnetic transformer may also induce ferromagnetic resonance, which damages the equipments.

Developments of electronic transformers in recent years have improved a number of the shortcomings of an electromagnetic transformer, but certain theoretical and technical issues still remain in practical applications. It is very common for an electronic transformer to be interfered by common mode noise. When a sampled voltage possesses the common mode noise, an accuracy of the sampled voltage is dropped significantly. Consequently, a control circuit of the power conversion system cannot control an operation mode of the power conversion system accurately according to the sampled voltage, due to the interference caused by the common mode noise.

Therefore, an appropriate solution of a power conversion system and a voltage sampling device thereof has yet been developed, in order to address the above problems.

SUMMARY

The present disclosure provides a voltage sampling device. The voltage sampling device includes a first input path, a second input path and a signal processing module. The first input path includes a first input voltage-dividing resistor unit, a second input voltage-dividing resistor unit and a first DC (direct current) voltage-dividing resistor unit. The first input voltage-dividing resistor unit is electrically coupled between a first voltage input terminal and a first node. The first input voltage-dividing resistor unit receives a first input voltage from the first voltage input terminal. The second input voltage-dividing resistor unit is electrically coupled between the first node and a ground terminal, wherein the first input voltage-dividing resistor unit and the second input voltage-dividing resistor unit generate a first input divided voltage at the first node according to the first input voltage. The first DC voltage-dividing resistor unit is electrically coupled between the first node and a DC voltage source, wherein the DC voltage source generates a first DC bias voltage via the first DC voltage-dividing resistor unit at the first node, and the first DC bias voltage combines with the first input divided voltage to generate a first sampled voltage signal. The second input path includes a third input voltage-dividing resistor unit, a fourth input voltage-dividing resistor unit and a second DC voltage-dividing resistor unit. The third input voltage-dividing resistor unit is electrically coupled between a second voltage input terminal and a second node. The third input voltage-dividing resistor unit receives a second input voltage from the second voltage input terminal. The fourth input voltage-dividing resistor unit is electrically coupled between the second node and the ground terminal, wherein the third input voltage-dividing resistor unit and the fourth input voltage-dividing resistor unit generate a second input divided voltage at the second node according to the second input voltage. The second DC voltage-dividing resistor unit is electrically coupled between the second node and the DC voltage source, wherein the DC voltage source generates a second DC bias voltage via the second DC voltage-dividing resistor unit at the second node, and the second DC bias voltage combines with the second input divided voltage to generate a second sampled voltage signal. Resistances of the third input voltage-dividing resistor unit, the fourth input voltage-dividing resistor unit and the second DC voltage-dividing resistor unit are substantially the same as the first input voltage-dividing resistor unit, the second input voltage-dividing resistor unit and the first DC voltage-dividing resistor unit. The signal processing module receives the first sampled voltage signal and the second sampled voltage signal to perform signal processing.

An aspect of the present disclosure provides a power conversion system. The power conversion system includes a grid-side converter, a DC bus module, a motor-side converter and at least one voltage sampling device. The grid-side converter is electrically coupled to a power grid. The grid-side converter converts grid-side three-phase AC voltages to a plurality of DC bus voltages. The DC bus module includes a plurality of DC buses and at least one bus capacitor, wherein the bus capacitor is electrically coupled to two neighboring DC buses of the plurality of DC buses. The motor-side converter is electrically coupled to the grid-side converter via the DC bus module. The motor-side converter generates motor-side three-phase AC voltages according to the plurality of DC bus voltages transmitted by the DC bus module. The at least one voltage sampling device includes a first input path, a second input path and a signal processing module. The first input path includes a first input voltage-dividing resistor unit, a second input voltage-dividing resistor unit and a first DC voltage-dividing resistor unit. The first input voltage-dividing resistor unit is electrically coupled between a first voltage input terminal and a first node. The first input voltage-dividing resistor unit receives a first input voltage from the first voltage input terminal. The second input voltage-dividing resistor unit is electrically coupled between the first node and a ground terminal, wherein the first input voltage-dividing resistor unit and the second input voltage-dividing resistor unit generate a first input divided voltage at the first node according to the first input voltage. The first DC voltage-dividing resistor unit is electrically coupled between the first node and a DC voltage source, wherein the DC voltage source generates a first DC bias voltage via the first DC voltage-dividing resistor unit at the first node, and the first DC bias voltage combines with the first input divided voltage to generate a first sampled voltage signal. The second input path includes a third input voltage-dividing resistor unit, a fourth input voltage-dividing resistor unit and a second DC voltage-dividing resistor unit. The third input voltage-dividing resistor unit is electrically coupled between a second voltage input terminal and a second node. The third input voltage-dividing resistor unit receives a second input voltage from the second voltage input terminal. The fourth input voltage-dividing resistor unit is electrically coupled between the second node and the ground terminal, wherein the third input voltage-dividing resistor unit and the fourth input voltage-dividing resistor unit generate a second input divided voltage at the second node according to the second input voltage. The second DC voltage-dividing resistor unit is electrically coupled between the second node and the DC voltage source, wherein the DC voltage source generates a second DC bias voltage via the second DC voltage-dividing resistor unit at the second node, and the second DC bias voltage combines with the second input divided voltage to generate a second sampled voltage signal. Resistances of the third input voltage-dividing resistor unit, the fourth input voltage-dividing resistor unit and the second DC voltage-dividing resistor unit are substantially the same as the first input voltage-dividing resistor unit, the second input voltage-dividing resistor unit and the first DC voltage-dividing resistor unit. The signal processing module receives the first sampled voltage signal and the second sampled voltage signal to perform signal processing.

An advantage of the present disclosure is that by utilizing resistor units having a same structure in different input paths in the voltage sampling device, common mode noise can be effectively eliminated.

DESCRIPTION OF THE EMBODIMENTS

Reference is now made toFIG. 1.FIG. 1is a schematic diagram illustrating a voltage sampling device1according to an embodiment of the present disclosure. The voltage sampling device1includes a first input path10, a second input path12and a signal processing module14.

The first input path10includes a first input voltage-dividing resistor unit R1a, a second input voltage-dividing resistor unit R1band a first DC voltage-dividing resistor unit R1c.

The first input voltage-dividing resistor unit R1ais electrically coupled between a first voltage input terminal In1and a first node P1, so as to receive a first input voltage U1from the first voltage input terminal In1. The first input voltage U1can be a DC (direct current) power source or an AC (alternating current) power source.

The second input voltage-dividing resistor unit R1bis electrically coupled between the first node P1and a ground terminal GND. The first input voltage-dividing resistor unit R1aand the second input voltage-dividing resistor unit R1bgenerate a first input divided voltage (not illustrated) at the first node P1according to the first input voltage U1.

The first DC voltage-dividing resistor unit R1cis electrically coupled between the first node P1and a DC voltage source Vcc. The DC voltage source Vccgenerates a first DC bias voltage (not illustrated) at the first node P1via the first DC voltage-dividing resistor unit R1c. The first DC bias voltage and the first input divided voltage are combined to generate a first sampled voltage signal Usam1.

The second input path12includes a third input voltage-dividing resistor unit R2a, a fourth input voltage-dividing resistor unit R2band a second DC voltage-dividing resistor unit R2c.

The third input voltage-dividing resistor unit R2ais electrically coupled between a second voltage input terminal In2and a second node P2, so as to receive a second input voltage U2from the second voltage input terminal In2. The second input voltage U2can be a DC (direct current) power source or an AC (alternating current) power source.

The fourth input voltage-dividing resistor unit R2bis electrically coupled between the second node P2and a ground terminal GND. The third input voltage-dividing resistor unit R2aand the fourth input voltage-dividing resistor unit R2bgenerate a second input divided voltage (not illustrated) at the second node P2according to the second input voltage U2.

The second DC voltage-dividing resistor unit R2cis electrically coupled between the second node P2and the DC voltage source Vcc. The DC voltage source Vccgenerates a second DC bias voltage (not illustrated) at the second node P2via the second DC voltage-dividing resistor unit R2c. The second DC bias voltage and the second input divided voltage are combined to generate a second sampled voltage signal Usam2.

Resistances of the third input voltage-dividing resistor unit R2a, the fourth input voltage-dividing resistor unit R2band the second DC voltage-dividing resistor unit R2care substantially the same as those of the first input voltage-dividing resistor unit R1a, the second input voltage-dividing resistor unit R1band the first DC voltage-dividing resistor unit R1crespectively. “Substantially the same” means that the resistances between the corresponding resistor units are not necessarily identical, but may be differed by a reasonable range, such as 5% and is not limited thereto.

The signal processing module14receives the first sampled voltage signal Usam1and the second sampled voltage signal Usam2, so as to perform signal processing. In an embodiment, the signal processing module14includes an analog-to-digital converter (ADC)140and a signal processing unit142. The ADC140firstly converts the first sampled voltage signal Usam1and the second sampled voltage signal Usam2from an analog format to a digital format, so that the signal processing unit142can perform subsequent signal processing. In an embodiment, the signal processing unit142can be implemented by, for instance, a CPLD (complex programmable logic device) or a FPGA (field programmable gate array), but is not limited thereto.

In an embodiment, the DC voltage source Vccmentioned above is a positive DC voltage source, and by utilizing the first DC bias voltage and the second DC bias voltage generated, the first input divided voltage and the second input divided voltage can be biased to a range acceptable by the signal processing module14. For instance, when the signal processing module14can only process positive signals, and the first input divided voltage or the second input divided voltage is negative, the DC voltage source Vcccan bias the negative divided voltage to a positive range, in order for the signal processing module14to process.

Therefore, the voltage sampling device1of the present embodiment can sample the first input voltage U1and the second input voltage U2via the voltage-dividing resistor units of the same resistance on the first input path10and the second input path12, so as to suppress the common mode noise of the sampled voltage signal.

Reference is now made toFIG. 2.FIG. 2is a schematic diagram illustrating a voltage sampling device2according to another embodiment of the present disclosure. The voltage sampling device2includes a first input path20, a second input path22and a signal processing module24.

In the present embodiment, the first input path20, which is similar to the first input path10shown inFIG. 1, includes a first input voltage-dividing resistor unit R1a, a second input voltage-dividing resistor unit R1band a first DC voltage-dividing resistor unit R1c. The second input path22, which is similar to the second input path12shown inFIG. 1, includes a third input voltage-dividing resistor unit R2a, a fourth input voltage-dividing resistor unit R2band a second DC voltage-dividing resistor unit R2c. The signal processing module24, which is similar to the signal processing module14shown inFIG. 1, includes an ADC (analog-to-digital converter)240and a signal processing unit242. Operation mechanisms and connecting relations of the above components are similar to those shown inFIG. 1, so detailed descriptions are omitted hereinafter.

In the present embodiment however, the first input path20further includes a first voltage follower unit200and a first matching resistor unit R1d.

The first voltage follower unit200is electrically coupled to the first node P1, so as to transmit the first sampled voltage signal Usam1to the signal processing module24via the first voltage follower unit200. The first matching resistor unit R1dis electrically coupled between the first voltage follower unit200and the signal processing module24, so as to provide impedance matching.

In an embodiment, the first voltage follower unit200is implemented by an operational amplifier, where a non-inverting input terminal (shown as “+” inFIG. 2) is electrically coupled to the first node P1and an inverting input terminal (shown as “−” inFIG. 2) is electrically coupled to an output (shown as “o” inFIG. 2) of the voltage follower unit200. The first voltage follower unit200is a circuit possessing a high input impedance and a low output impedance, so as to isolate the non-inverting input terminal and the output terminal. Therefore, a value of the first sampled voltage signal Usam1does not change with a magnitude of the first matching resistor unit R1d. The first voltage follower unit200can therefore act like a buffer, for instance.

Similarly, the second input path22further includes a second voltage follower unit220and a second matching resistor unit R2d. The second voltage follower unit220is electrically coupled to the second node P2, so the second sampled voltage signal Usam2can be transmitted to the signal processing module24via the second voltage follower unit220. The second matching resistor unit R2dis electrically coupled between the second voltage follower unit220and the signal processing module24, so as to provide impedance matching. Structures and effects of the second voltage follower unit220are similar to those of the first voltage follower unit200, so detailed descriptions are omitted hereinafter.

Therefore, in addition to sample the first input voltage U1and the second input voltage U2via the voltage-divided resistor units of the same resistance on the first input path10and the second input path12, the voltage sampling device1of the present embodiment can further utilize implementations of the first voltage follower unit200and the second voltage follower unit220to suppress common mode noise and interference of the sampled voltage signals.

InFIG. 1andFIG. 2, each resistor unit is represented by a single resistor. In different embodiments however, each resistor unit may include a plurality of resistors coupled in series and/or in parallel.

Reference is now made toFIG. 3,FIG. 4AandFIG. 4B.FIG. 3is a schematic diagram illustrating a voltage sampling device3according to another embodiment of the present disclosure.FIG. 4Ais a schematic diagram illustrating a voltage sampling device4according to another embodiment of the present disclosure.FIG. 4Bis a schematic diagram illustrating a voltage sampling device4′ according to another embodiment of the present disclosure. Each of the voltage sampling devices3,4and4′ includes a first input path20, a second input path22, a signal processing module24and a common mode choke module30.

In the embodiments shown inFIG. 3,FIG. 4AadFIG. 4B, structures of the first input path20, the second input path22and the signal processing module24are similar to those ofFIG. 2, so detailed descriptions are omitted hereinafter.

In the present embodiment, the common mode choke module30can be implemented by a common mode choke. The common mode choke is a closed magnetic ring having wirings with a same number of turns, wound in symmetrically opposite directions. The common mode noise currents generated by the noise have a same direction when flowing pass the two windings, so the magnetic flux generated (i.e. the magnetic flux is of a same phase) is accumulated, and a high amount of impedance is produced at the choke coil, achieving common mode noise suppression. In an embodiment, the common mode choke module30is electrically coupled to the first input path20and the second input path22, in order to eliminate the common mode noise of the voltage signals of these two input paths.

TakingFIG. 3as an example. The common mode choke module30is electrically coupled between the first voltage input terminal In1and the first input voltage-dividing resistor unit R1aof the first input path20, as well as between the second voltage input terminal In2and the second input voltage-dividing resistor unit R2aof the second input path22.

TakingFIG. 4Aas an example. The common mode choke module30is electrically coupled between the first input voltage-dividing resistor unit R1aand the first node P1of the first input path20, as well as between the second input voltage-dividing resistor unit R2aand the second node P2of the second input path22.

TakingFIG. 4Bas an example. The common mode choke module30is electrically coupled between the first node P1of the first input path20, the second node P2of the second input path22and the signal processing module24. More specifically, the common mode choke module30is electrically coupled between the first node P1and the non-inverting input terminal of the first voltage follower unit200of the first input path20, as well as between the second node P2and the non-inverting input terminal of the second voltage follower unit220of the second input path22.

Reference is now made toFIG. 5.FIG. 5is a schematic diagram illustrating a voltage sampling device5according to another embodiment of the present disclosure. The voltage sampling device5includes a first input path20, a second input path22, a signal processing module24and a third input path26.

In the present embodiment, structures of the first input path20, the second input path22, and the signal processing module24are similar to those shown inFIG. 2, and relative descriptions are omitted hereinafter.

The third input path26includes a fifth input voltage-dividing resistor unit R3a, a sixth input voltage-dividing resistor unit R3b, a third DC voltage-dividing resistor unit R3c, a third voltage follower unit260and a third matching resistor unit R3d.

The fifth input voltage-dividing resistor unit R3ais electrically coupled between the third voltage input terminal In3and the third node P3, so as to receive a third input voltage U3from the third voltage input terminal In3. The third input voltage U3can be a DC (direct current) power source or an AC (alternating current) power source.

The sixth input voltage-dividing resistor unit R3bis electrically coupled between the third node P3and a ground terminal GND. The fifth input voltage-dividing resistor unit R3aand the sixth input voltage-dividing resistor unit R3bgenerate a third input divided voltage (not illustrated) at the third node P3according to the third input voltage U3.

The third DC voltage-dividing resistor unit R3cis electrically coupled between the third node P3and a DC voltage source Vcc. The DC voltage source Vccgenerates a third DC bias voltage (not illustrated) at the third node P3via the third DC voltage-dividing resistor unit R3c. The third DC bias voltage and the third input divided voltage are combined to generate a third sampled voltage signal Usam3.

Resistances of the fifth input voltage-dividing resistor unit R3a, the sixth input voltage-dividing resistor unit R3band the third DC voltage-dividing resistor unit R3care substantially the same as those of the first input voltage-dividing resistor unit R1a, the second input voltage-dividing resistor unit R1band the first DC voltage-dividing resistor unit R1crespectively.

The third voltage follower unit260is electrically coupled to the third node P3, so the third sampled voltage signal Usam3is transmitted to the signal processing module24via the third voltage follower unit260. The third matching resistor unit R3dis electrically coupled between the third voltage follower unit260and the signal processing module24, so as to provide impedance matching.

Therefore, the voltage sampling device5of the present embodiment can sample three voltage input terminals, and can perform sampling the first input voltage U1, the second input voltage U2and the third input voltage U3via the voltage-divided resistor units of the same resistance on the first input path20, the second input path22and the third input path26respectively.

Reference is now made toFIG. 6,FIG. 7AandFIG. 7B.FIG. 6is a schematic diagram illustrating a voltage sampling device6according to an embodiment of the present disclosure.FIG. 7Ais a schematic diagram illustrating a voltage sampling device7according to another embodiment of the present disclosure.FIG. 7Bis a schematic diagram illustrating a voltage sampling device7′ according to another embodiment of the present disclosure. Each of the voltage sampling devices6,7and7′ includes a first input path20, a second input path22, a signal processing module24, a third input path26and a common mode choke module60.

In the present embodiment, structures of the first input path20, the second input path22, the signal processing module24and the third input path26shown inFIG. 6,FIG. 7AandFIG. 7Bare similar to those ofFIG. 5, so relative descriptions are omitted hereinafter.

In an embodiment, the common mode choke module60can be implemented by two common mode chokes, whereas one is electrically coupled to the first input path20and the second input path22, while the other is electrically coupled to the second input path22and the third input path26, so as to eliminate the common mode noise of the voltage signals of these three input paths. The common mode choke module60can be electrically coupled between the voltage input terminals and the input voltage-dividing resistor units of each input path. For instance, as shown inFIG. 6, the common mode choke module60is electrically coupled between the first voltage input terminal In1, the first input voltage-dividing resistor unit R1a, the second voltage input terminal In2, the third input voltage-dividing resistor unit R2a, the third voltage input terminal In3and the fifth input voltage-dividing resistor unit R3a.

In another embodiment, the common mode choke module60is electrically coupled to the first input voltage-dividing resistor unit R1a, the first node P1the third input voltage-dividing resistor unit R2a, the second node P2, the fifth input voltage-dividing resistor unit R3aand the third node P3, as shown inFIG. 7A.

In yet another embodiment, the common mode choke module60, as shown inFIG. 7B, is electrically coupled to the first node P1, the second node P2, the third node P3and the signal processing module24. More specifically, the common mode choke module60can be electrically coupled to the first node P1, the non-inverting input terminal of the first voltage follower unit200, the second node P2, the non-inverting input terminal of the second voltage follower unit220, the third node P3and the non-inverting input terminal of the third voltage follower unit260.

Reference is now made toFIG. 8A.FIG. 8Ais a block diagram illustrating a power conversion system8according to an embodiment of the present disclosure. The power conversion system8includes a rectifier80, a DC bus module82and an inverter84.

The rectifier80is electrically coupled to a power grid81. In an embodiment, the rectifier80includes a plurality of switches (not illustrated), such as but not limited to, IGBTs (Insulated Gate Bipolar Transistor). By turning the switches on and off, the three-phase AC voltages Vea, Veband Vecof the power grid81can be converted to DC bus voltages.

In an embodiment, the power conversion system8can further include a filter83. The rectifier80can receive the three-phase AC voltages Vea, Veband Vecvia the filter83. The filter83can restrain a harmonic current flowing into the power grid81.

The DC bus module82can transmit DC voltages. In the present embodiment, the DC bus module82includes DC buses821,823and825, and bus capacitors820A and820B. The bus capacitor820A or820B can be a single capacitor, or a plurality of capacitors connected in series or a plurality of capacitors connected in parallel. The bus capacitor820A is electrically coupled to the DC buses821and823. The bus capacitor820B is electrically coupled to the DC buses823and825. The bus capacitors820A and820B act as supports and filters for voltages of the DC buses821,823and825. In another embodiment, the DC bus module can include two DC buses and a bus capacitor. The Bus capacitor is electrically coupled between the two DC buses and acts as the support and the filter for the two DC buses.

The invertor84is electrically coupled to the rectifier80via the DC bus module82, so as to generate loading three-phase AC voltages Vea′, Veb′ and Vec′ according to a DC bus voltage transmitted by the DC bus module82. In an embodiment, the inverter84can further be electrically connected to a motor85, and the motor85can be driven by the loading three-phase AC voltages Vea′, Veb′ and Vec′.

Reference is now made toFIG. 8B.FIG. 8Bis a block diagram illustrating a power conversion system8′ according to an embodiment of the present disclosure. The power conversion system8′ includes a grid-side converter80′, a DC bus module82and a motor-side converter84′.

The grid-side converter80′ is electrically coupled to a power grid81. In an embodiment, the grid-side converter80′ includes a plurality of switches (not illustrated), such as but not limited to, IGBTs (Insulated Gate Bipolar Transistor). Grid-side three-phase AC voltages Vea, Veband Vecof the power grid81can be converted to DC bus voltages, according to on/off operations of the switches.

The DC bus module82can transmit DC bus voltages. In the present embodiment, the DC bus module82includes DC buses821,823and825, and bus capacitors820A and820B. The bus capacitor820A is electrically coupled to the DC buses821and823. The bus capacitor820B is electrically coupled to the DC buses823and825. The bus capacitors820A and820B act as supports and filters for the voltages of the DC buses821,823and825.

The motor-side converter84′ is electrically coupled to the grid-side converter80′ via the DC bus module82, so as to generate the motor-side three-phase AC voltages Vea′, Veb′ and Vec′ according to the DC bus voltages transmitted by the DC bus module82. In an embodiment, the motor-side converter84′ can further be electrically coupled to the motor85, so as to drive the motor85according to the motor-side three-phase AC voltages Vea′, Veb′ and Vec′.

The voltage sampling device of the present disclosure, such as the voltage sampling devices1-7′ shown inFIG. 1toFIG. 7B, can be disposed in the power conversion system8ofFIG. 8Aor the power conversion system8′ ofFIG. 8B, in order to sample voltage signals of the power conversion system8or the power conversion system8′.

Reference is now made toFIG. 9.FIG. 9is a schematic diagram illustrating a DC bus module82and two voltage sampling devices2and2′ according to an embodiment of the present disclosure. In the present embodiment, the voltage sampling device2includes a first input path20, a second input path22and a signal processing module24, and the voltage sampling device2′ includes a first input path20′, a second input path22′ and a signal processing module24′. The first input paths20and20′ and the second input paths22and22′ are represented by functional blocks, and components and operations thereof are similar to the voltage sampling device2shown inFIG. 2, so relative descriptions are omitted hereinafter.

In the present embodiment, the first voltage input terminal In1and the second voltage input terminal In2of the voltage sampling device2correspond to the DC bus821and the DC bus823of the DC bus module82(i.e. the two terminals of the bus capacitor820A) respectively. The first input voltage U1and the second input voltage U2received by the voltage sampling device2correspond to the line voltages of the DC buses821and823respectively.

On the other hand, the first voltage input terminal In1′ and the second voltage input terminal In2′ of the voltage sampling device2′ correspond to the DC buses823and825of the DC bus module82respectively (i.e. the two terminals of the bus capacitor820B). Therefore, the first input voltage U1′ and the second input voltage U2′ received by the voltage sampling device2′ correspond to the line voltages of the DC buses823and825respectively.

Hence, each DC bus voltages of the DC bus module82of the power conversion system8or8′ can be sampled via the voltage sampling devices2and2′. In an embodiment, a voltage signal generated from sampling can be transmitted to other control modules (not illustrated), so as to adjust an operation mode of the power conversion system8according to the sampled voltage signals.

The voltage sampling devices2and2′ inFIG. 9are described by using the voltage sampling device2in the embodiment shown inFIG. 2as an example. In other embodiments, the voltage sampling devices1,3,4and4′ shown in the respectiveFIG. 1,FIG. 3,FIG. 4AandFIG. 4Bcan also be utilized to sample voltages.

Reference is now made toFIG. 10.FIG. 10is a schematic diagram illustrating a DC bus module82and a voltage sampling device5according to an embodiment of the present disclosure. In the present embodiment, the voltage sampling device5includes a first input path20, a second input path22, a signal processing module24and a third input path26. The first input path20, the second input path22and the third input path26are represented by functional blocks, and components and operations thereof are similar to the voltage sampling device5shown inFIG. 5, so relative descriptions are omitted hereinafter.

In the present embodiment, a first voltage input terminal In1, a second voltage input terminal In2and a third voltage input terminal In3correspond to a DC bus821, a DC bus823and a DC bus825of the DC bus module82(i.e. a terminal of the bus capacitor820A, a terminal of the bus capacitor820B and a terminal between the bus capacitors820A and820B) respectively. Therefore, a first input voltage U1, a second input voltage U2and a third input voltage U3received by the voltage sampling device2correspond to the line voltages of the DC buses821,823and825respectively.

Compare to the embodiment shown inFIG. 9, which utilizes two signal processing modules24and24′ and four input paths, the voltage sampling device5of the present embodiment achieves sampling by utilizing only one signal processing module24and three input paths, so the hardware cost can be lowered.

The voltage sampling devices5inFIG. 10is described by using the voltage sampling device5in the embodiment shown inFIG. 5as an example. In other embodiments, the voltage sampling devices6,7and7′ shown in the respectiveFIG. 6,FIG. 7AandFIG. 7Bcan also be utilized to sample voltages.

Reference is now made toFIG. 11.FIG. 11is a schematic diagram illustrating a power grid81and two voltage sampling devices2and2′ according to an embodiment of the present disclosure. In the present embodiment, the voltage sampling device2includes a first input path20, a second input path22and a signal processing module24. The voltage sampling device2′ includes a first input path20′, a second input path22′ and a signal processing module24′. The first input paths20and20′ and the second input paths22and22′ are represented by functional blocks, and components and operations thereof are similar to the voltage sampling device2shown inFIG. 2, so relative descriptions are omitted hereinafter.

In the present embodiment, the first voltage input terminal In1and the second voltage input terminal In2of the voltage sampling device2correspond to two phases of a three-phase power grid81. Therefore, the first input voltage U1and the second input voltage U2received by the voltage sampling device2correspond to AC voltages Veaand Vebof two phases of the three-phase power grid81.

On the other hand, the first voltage input terminal In1′ and the second voltage input terminal In2′ of the voltage sampling device2′ correspond to two phases of the three-phase power grid81. Therefore, the first input voltage U1′ and the second input voltage U2′ received by the voltage sampling device2′ correspond to AC voltages Veband Vecof two phases of the three-phase power grid81.

Hence, the (grid-side) three-phase AC voltages Vea, Veband Vecof the power grid81received by the DC bus module82of the power conversion system8or8′ can be sampled via the voltage sampling devices2and2′. In an embodiment, a voltage signal generated from sampling can be transmitted to other control modules (not illustrated), so as to adjust an operation mode of the power conversion system8according to the sampled voltage signal.

The voltage sampling devices2and2′ shown inFIG. 11are described by using the voltage sampling device2in the embodiment shown inFIG. 2as an example. In other embodiments, the voltage sampling devices1,3,4and4′ shown in the respectiveFIG. 1,FIG. 3,FIG. 4AandFIG. 4Bcan also be utilized to sample voltages.

Reference is now made toFIG. 12.FIG. 12is a schematic diagram illustrating a power grid81and a voltage sampling device5according to an embodiment of the present disclosure. In the present embodiment, the voltage sampling device5includes a first input path20, a second input path22, a signal processing module24and a third input path26. The first input path20, the second input path22and the third input path26are represented by functional blocks, and components and operations thereof are similar to those of the voltage sampling device5shown inFIG. 5, so relative descriptions are omitted hereinafter.

In the present embodiment, a first voltage input terminal In1, a second voltage input terminal In2and a third voltage input terminal In3correspond to a power grid81of three phases. Therefore, the first voltage input terminal In1, the second voltage input terminal In2and the third voltage input terminal In3correspond to three-phase AC voltages Vea, Veband Vecof the power grid81received by the DC bus module12, respectively.

Compare to the embodiment shown inFIG. 11, which utilizes two signal processing modules24and24′ and four input paths, the voltage sampling device5of the present embodiment achieves sampling by utilizing only one signal processing module24and three input paths, so the hardware cost can be lowered.

In an embodiment, structures shown inFIG. 11andFIG. 12can also be applied to three-phase AC signals Vea′, Veb′ and Vec′ generated by the sampling inverter84ofFIG. 8A, or the motor-side three-phase AC signals Vea′, Veb′ and Vec′ generated by the motor-side converter84′ ofFIG. 8B, so a relative control module can adjust operation modes of the power conversion system8or8′ according to the sampled voltage signal.

The voltage sampling device5shown inFIG. 12is described by using the voltage sampling device5in the embodiment shown inFIG. 5as an example. In other embodiments, the voltage sampling devices6,7and7′ shown in the respectiveFIG. 6,FIG. 7andFIG. 7Acan also be utilized to sample voltages.