Contact structure for semiconductor device having trench shield electrode and method

In one embodiment, a contact structure for a semiconductor device having a trench shield electrode includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or inside of the trench structure. A thick passivating layer surrounds the shield electrode in the contact portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to an application entitled “SEMICONDUCTOR DEVICE HAVING TRENCH SHIELD ELECTRODE STRUCTURE” having an application Ser. No. 12/271,041, having a common assignee, and a common inventor, which is filed concurrently herewith.

This application is related to an application entitled “TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD” having an application Ser. No. 12/271,068, having a common assignee, and having a common inventor, which is filed concurrently herewith.

FIELD OF THE INVENTION

This document relates generally to semiconductor devices, and more specifically to insulated gate structures and methods of formation.

BACKGROUND OF THE INVENTION

Metal oxide field effect transistor (MOSFET) devices are used in many power switching applications such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. By way of example, in an n-type enhancement mode MOSFET, turn-on occurs when a conductive n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to the application of a positive gate voltage, which exceeds an inherent threshold voltage. The inversion layer connects n-type source regions to n-type drain regions and allows for majority carrier conduction between these regions.

There is a class of MOSFET devices where the gate electrode is formed in a trench that extends downward from a major surface of a semiconductor material such as silicon. Current flow in this class of devices is primarily vertical and, as a result, device cells can be more densely packed. All else being equal, this increases the current carrying capability and reduces on-resistance of the device.

In certain applications, high frequency switching characteristics are important and certain design techniques have been used to reduce capacitive effects thereby improving switching performance. By way of example, it is previously known to incorporate an additional electrode below the gate electrode in trench MOSFET devices and to connect this additional electrode to the source electrode or another bias source. This additional electrode is often referred to as a “shield electrode” and functions, among other things, to reduce gate-to-drain capacitance. Shield electrodes have been previously used as well in planar MOSFET devices.

Although shield electrodes improve device performance, challenges still exist to more effectively integrate them with other device structures. These challenges include avoiding additional masking steps, addressing non-planar topographies, and avoiding excessive consumption of die area. These challenges impact, among other things, cost and manufacturability. Additionally, opportunities exist to provide devices having shield electrodes with more optimum and reliable performance.

Accordingly, structures and methods of manufacture are needed to effectively integrate shield electrode structures with other device structures and to provide more optimum and reliable performance.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein current-carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel devices, a person of ordinary skill in the art will appreciate that P-channel devices and complementary devices are also possible in accordance with the present description. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight-line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions are generally not straight lines and the corners are not precise angles.

In addition, structures of the present description may embody either a cellular base design (where the body regions are a plurality of distinct and separate cellular or stripe regions) or a single base design (where the body region is a single region formed in an elongated pattern, typically in a serpentine pattern or a central portion with connected appendages). However, one embodiment of the present description will be described as a cellular base design throughout the description for ease of understanding. It should be understood that it is intended that the present disclosure encompass both a cellular base design and a single base design.

DETAILED DESCRIPTION OF THE DRAWINGS

In general, the present description pertains to a semiconductor device formed on a region of semiconductor material having a major surface. The semiconductor device includes a trench structure with a control electrode layer and a shield electrode layer. The semiconductor device further includes a contact structure where the control electrode layer and the shield electrode layer terminate. In one embodiment, the control electrode layer and the shield electrode layer are recessed below the major surface. In one embodiment, contact is made to both the control electrode layer and the shield electrode layer inside of the trench structure. In another embodiment, the shield electrode layer is surrounded by a thick insulator layer adjacent the major surface in the contact structure.

FIG. 1shows a partial cross-sectional view of a semiconductor device or cell10having a shield electrode or electrodes21. The cross-section is taken, for example, along reference line I-I from active area204of device20shown inFIG. 2. In this embodiment, device10comprises a MOSFET structure, but it is understood that this description applies as well to insulated gate bipolar transistors (IGBT), MOS-gated thyristors, and the like.

Device10includes a region of semiconductor material, semiconductor material, or semiconductor region11, which comprises for example, an n-type silicon substrate12having a resistivity in a range from about 0.001 ohm-cm to about 0.005 ohm-cm. Substrate12can be doped with phosphorous or arsenic. In the embodiment shown, substrate12provides a drain contact or a first current carrying contact for device10. A semiconductor layer, drift region, or extended drain region14is formed in, on, or overlying substrate12. In one embodiment, semiconductor layer14is formed using conventional epitaxial growth techniques. Alternatively, semiconductor layer14is formed using conventional doping and diffusion techniques. In an embodiment suitable for a 50 volt device, semiconductor layer14is n-type with a dopant concentration of about 1.0×1016atoms/cm3and has a thickness from about 3 microns to about 5 microns. The thickness and dopant concentration of semiconductor layer14is increased or decreased depending on the desired drain-to-source breakdown voltage (BVDSS) rating of device10. It is understood that other materials may be used for semiconductor material11or portions thereof including silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, silicon carbide, or the like. Additionally, in an alternate embodiment, the conductivity type of substrate12is switched to be opposite the conductivity type of semiconductor layer14to form, for example, an IGBT embodiment.

Device10also includes a body, base, PHV, or doped region or regions31extending from a major surface18of semiconductor material11. Body regions31have a conductivity type that is opposite to the conductivity type of semiconductor layer14. In this example, body regions31are p-type conductivity. Body regions31have a dopant concentration suitable for forming inversion layers that operate as conduction channels or channel regions45of device10. Body regions31extend from major surface18to a depth, for example, from about 0.5 microns to about 2.0 microns. N-type source regions, current conducting regions, or current carrying regions33are formed within, in, or overlying body regions31and extend from major surface18to a depth, for example, from about 0.1 microns to about 0.5 microns. A p-type body contact or contact region36can be formed in body regions31, and is configured to provide a lower contact resistance to body regions31.

Device10further includes trench control, trench gate, or trench structures19, which extend in a substantially vertical direction from major surface18. Alternatively, trench control structures19or portions thereof have a tapered shape. Trench structures19include trenches22, which are formed in semiconductor layer14. For example, trenches22have a depth from about 1.5 microns to about 2.5 microns or deeper. In one embodiment, trenches22extend all the way through semiconductor layer14into substrate12. In another embodiment, trenches22terminate within semiconductor layer14.

Passivating layers, insulator layers, field insulator layers or regions24are formed on lower portions of trenches22and comprise, for example, an oxide, a nitride, combinations thereof, or the like. In one embodiment, insulator layers24are silicon oxide and have a thickness from about 0.1 microns to about 0.2 microns. Insulator layers24can be uniform in thickness or variable thickness. Additionally, the thickness of layer24may be varied, depending on the desired drain-to-source breakdown voltage (BVDSS). Shield electrodes21are formed overlying insulator layers24in substantially centrally located lower portions of trenches22. In one embodiment, shield electrodes21comprise polycrystalline semiconductor material that can be doped. In another embodiment, shield electrodes21can comprise other conductive materials. In contact structure embodiments described below, portions of trenches22in the contact structure areas have insulator layers24along upper sidewall portions as well.

Passivating, dielectric, or insulator layers26are formed along upper sidewall portions of trenches22and are configured as gate dielectric regions or layers. By way of example, insulator layers26comprise oxide, nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, combinations thereof, or the like. In one embodiment, insulator layers26are silicon oxide and have a thickness from about 0.01 microns to about 0.1 microns. In one embodiment, insulator layers24are thicker than insulator layers26. Passivating, dielectric, or insulator layers27are formed overlying shield electrodes21, and in one embodiment insulator layers27have a thickness between the thickness of insulator layers24and insulator layers26. In one embodiment, insulator layers27have a thickness greater than the thickness of insulator layer26, which improves oxide breakdown voltage performance.

Trench structures19further include control electrodes or gate electrodes28, which are formed overlying insulator layers26and27. In one embodiment, gate electrodes28comprise doped polycrystalline semiconductor material such as polysilicon doped with an n-type dopant. In one embodiment, trench structures19further include a metal or silicide layer29formed adjoining gate electrode28or upper surfaces thereof. Layer29is configured to reduce gate resistance.

An interlayer dielectric (ILD), dielectric, insulator, or passivating layer41is formed overlying major surface18and above trench structures19. In one embodiment, dielectric layer41comprises a silicon oxide and has a thickness from about 0.4 microns to about 1.0 micron. In one embodiment, dielectric layer41comprises a deposited silicon oxide doped with phosphorous or boron and phosphorous. In one embodiment, dielectric layer41is planarized to provide a more uniform surface topography, which improves manufacturability.

Conductive regions or plugs43are formed through openings or vias in dielectric layer41and portions of semiconductor layer14to provide for electrical contact to source regions33and body regions31through contact regions36. In one embodiment, conductive regions43are conductive plugs or plug structures. In one embodiment, conductive regions43comprise a conductive barrier structure or liner plus a conductive fill material. In one embodiment, the barrier structure includes a metal/metal-nitride configuration such as titanium/titanium-nitride or the like. In another embodiment, the barrier structure further includes a metal-silicide structure. In one embodiment, the conductive fill material includes tungsten. In one embodiment, conductive regions43are planarized to provide a more uniform surface topography.

A conductive layer44is formed overlying major surface18and a conductive layer46is formed overlying a surface of semiconductor material11opposite major surface18. Conductive layers44and46are configured to provide electrical connection between the individual device components of device10and a next level of assembly. In one embodiment, conductive layer44is titanium/titanium-nitride/aluminum-copper or the like and is configured as a source electrode or terminal. In one embodiment, conductive layer46is a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like and is configured as a drain electrode or terminal. In one embodiment, a further passivation layer (not shown) is formed overlying conductive layer44. In one embodiment, shield electrodes21are connected (in another plane) to conductive layer44so that shield electrodes21are configured to be at the same potential as source regions33when device10is in use. In another embodiment, shield electrodes21are configured to be independently biased.

In one embodiment, the operation of device10proceeds as follows. Assume that source electrode (or input terminal)44and shield electrodes21are operating at a potential VSof zero volts, gate electrodes28receive a control voltage VGof 2.5 volts, which is greater than the conduction threshold of device10, and drain electrode (or output terminal)46operates at a drain potential VDof 5.0 volts. The values of VGand VScause body region31to invert adjacent gate electrodes28to form channels45, which electrically connect source regions33to semiconductor layer14. A device current IDSflows from drain electrode46and is routed through source regions33, channels45, and semiconductor layer14to source electrode44. In one embodiment, IDSis on the order of 1.0 amperes. To switch device10to the off state, a control voltage VGof less than the conduction threshold of device10is applied to gate electrodes28(e.g., VG<2.5 volts). This removes channels45and IDSno longer flows through device10.

Shield electrodes21are configured to control the width of the depletion layer between body region31and semiconductor layer14, which enhances source-to-drain breakdown voltage. Also, shield electrodes21help reduce gate-to-drain charge of device10. Additionally, because there is less overlap of gate electrode28with semiconductor layer14compared to other structures, the gate-to-drain capacitance of device10is reduced. These features enhance the switching characteristics of device10.

FIG. 2shows a top plan view of a semiconductor device, die or chip20that includes device10ofFIG. 1. For perspective,FIG. 2is generally looking down at major surface18of semiconductor material11shown inFIG. 1. In this embodiment, device20is bounded by a die edge51, which can be the center of a scribe line used to separate chip20from other devices when in wafer form. Device20includes a control pad, gate metal pad or gate pad52, which is configured to electrically contact gate electrodes28(shown inFIG. 1) through gate metal runners or gate runners or feeds53,54, and56. In this embodiment, gate metal pad52is placed in a corner portion238of device20. In one embodiment, gate runner54is adjacent to an edge202of device20, and gate runner56is adjacent another edge201of device20, which is opposite to edge202. In one embodiment, trenches22extend in a direction from edge201to edge202. In one embodiment, central portion203of device20is absent any gate runner(s). That is, in one embodiment the gate runners are placed in only peripheral or edge portions of device20.

Conductive layer44, which is configured in this embodiment as a source metal layer, is formed over active portions204and206of device20. In one embodiment, portion444of conductive layer44wraps around end portion541of gate runner54. A portion446of conductive layer44wraps around end portion561of gate runner56and is designated as structure239. Structure239is further shown in more detail inFIG. 24. Conductive layer44is further configured to form shield electrode contacts, runners, or feeds64and66, which in this embodiment provide contact to shield electrodes21. In this configuration, conductive layer44is connected to shield electrodes21. In the wrap around configuration described above, conductive layer44, portions444and446, shield electrode runners64and66and gate runners54and56are in the same plane and do not overlap each other. This configuration provides for the use of a single metal layer, which simplifies manufacturing.

In one embodiment, shield electrode runner66is placed between edge201of device20and gate runner56, and shield electrode runner64is placed between edge202of device20and gate runner54. In one embodiment, additional contact is made to shield electrodes21in shield contact region, contact region or stripe67, which separates the active area of device20into portions204and206. Contact region67is another location on device20where contact between conductive layer44and shield electrodes21is made. Contact region67is configured to divide gate electrodes28into two portions within device20. The two portions include one portion that feeds from gate runner54and another portion that feeds from gate runner56. In this configuration, gate electrode material28is absent from contact region67. That is, gate electrodes28do not pass through contact region67.

In embodiments that place gate pads52in a corner (e.g., corner23) of device20, the effects of gate resistance can be more optimally distributed through a selected or predetermined placement of contact region67within device20. This predetermined placement provides more uniform switching characteristics. In one embodiment, contact region67is offset from center203so that contact region67is closer to edge202than edge201with gate pad52in corner portion238adjacent to edge201. That is, contact region67is placed closer to the edge opposite to the corner and edge where gate pad52is placed. This configuration decreases the length of gate electrodes28in active area206and increases the length of gate electrodes28in active area204, which provides for a more efficient distribution of the gate resistance load.

In one embodiment, contact region67is placed in an offset location on device20to reduce gate resistance in active area206by about one half the resistance of gate runner53, and to increase gate resistance in active area204by about one half the resistance of gate runner53. In this embodiment, the gate resistance of active area206is given by:
2RgFET206+R53−(R53/2)
where RgFET206is the resistance of gate electrodes28in active area206when contact region67is placed in the center of device20, and R53is the resistance of metal runner53. The gate resistance of active area204is given by:
2RgFET204+R53/2
where RgFET204is the resistance of gate electrodes28in active area204when contact region67is placed in the center of device20. This is an example of a predetermined placement of contact region67that optimizes the distribution of gate resistance.

In another embodiment, shield contact region67is the only shield contact used to make contact to shield electrodes21and is placed in an interior portion of device20. That is, in this embodiment shield electrode runners64and66are not used. This embodiment is appropriate, for example, when switching speeds are not as critical, but where the resurf effect of the shield electrode is desired. In one embodiment, shield contact region67is placed in the center of device20. In another embodiment, shield contact region67is placed offset from center of device20. In these embodiments, shield contact region67provides contact to shield electrodes21within or inside of trenches22while control electrode runners54and56make contact to control electrodes28within or inside trenches22near edges201and202. This embodiment further saves on space within device20. In another embodiment, control electrodes28extend and overlap onto major surface18and control electrode runners54and56make contact to control electrodes outside of trenches22.

FIG. 3is a top view of another embodiment of a semiconductor device, die or chip30. In this embodiment, gate pad52is placed in corner portion238of device30similar to device20. Device30is similar to device20except that gate runners54and56are configured to decrease the left-to-right non-uniformity of gate resistance. In one embodiment, gate runner56feeds, connects, or links into an additional gate runner560at a substantially central location562. Gate runner560then connects to gate electrodes28(shown inFIG. 1) in active area204. In another embodiment, gate runner54feeds, connects, or links into gate runner540at a substantially central location542. Gate runner540then connects to gate electrodes28(shown inFIG. 1) in active area206. It is understood that one or both of gate runners54and56can be configured this way. Also, if used shield contact region67can be offset in device30as shown inFIG. 2. In one embodiment, shield electrode runner66is placed between gate runners56and560and edge201, and shield electrode runner64is placed between gate runners54and540and edge202. The gate runner configuration ofFIG. 3can be used as well in devices that do not include shield electrodes to reduce left-to-right non-uniformity of gate resistance.

FIG. 4shows an enlarged cross-sectional view of a gate/shield electrode contact structure, connective structure, or contact structure or region40, which is taken along reference line IV-IV inFIG. 2. In general, structure40is a contact area where contact is made between gate electrodes28and gate runners54and56, and where contact is made between shield electrodes21and shield electrode runners64and66. In previously known gate/shield electrode contact structures, a double stack of polysilicon or other conductive material is placed on top of the major surface of a substrate in peripheral or field regions of the device to enable contact to be made. Such double stacks of material can add in excess of 1.2 microns to surface topography. The double stacks of material on the major surface create several problems that include a surface topography that is non-planar, which affects subsequent photolithography steps and manufacturability. These previously known structures also increase die size.

Structure40is configured to address, among other things, the double polysilicon stack problem with previously known devices. Specifically, upper surface210of shield electrode21and upper surface280of gate electrode28are both recessed below major surface18of semiconductor material11so that contact is made to shield electrodes21and gate electrodes28within or directly inside of trenches22. That is, in one embodiment gate electrodes28and shield electrodes21do not overlap or extend on to major surface18. A conductive structure431connects gate runner56to gate electrode28, and a conductive structure432connects shield electrode runner66to shield electrode21. Conductive structures431and432are similar to conductive structures43as described in conjunction withFIG. 1. Structure40uses planarized dielectric layer41and planarized conductive structures431and432to provide a more planar topography. This structure enables deep submicron lithography and global planarization in power device technology. In addition, this configuration enables portion444of conductive layer44to wrap around end portion541of gate runner54(as shown inFIG. 2), and portion446to wrap around end portion561of gate runner56(as shown inFIG. 2) and to do so without consuming too much die area.

In another embodiment, shield electrode21overlaps onto major surface18and contact to shield electrode21is made there while gate electrode28remains within trenches22without overlapping upper surface210of shield layer21or major surface18and contact to gate electrode28is made within or above trenches22. This embodiment is shown inFIG. 25, which is cross-sectional view of a structure401, which is similar to structure40except shield electrode21overlaps major surface18as described above. In this embodiment, shield electrodes21and conductive layer44wrap-around end portions541and561(shown inFIG. 2) and source metal44makes contact to shield electrodes21through openings in dielectric layer41.

Another feature of structure40is that insulator layers24and27, which are thicker than insulator layer26(shown inFIG. 1), surround and overlie shield electrode21even where shield electrode21approaches major surface18. In previously known structures, a thinner gate oxide separates the gate electrode from the shield electrode in the field or peripheral regions. In previously known structures oxide is also thinner at the top surface-to-trench interface where both gate shield routing is made. However, such structures, where gate or shield oxides are thinned, are susceptible to oxide breakdown and device failure. Structure40reduces this susceptibility by using thicker insulator layers24and27. This feature is further shown inFIGS. 17-18.

Turning now toFIGS. 5-16, which are partial cross-sectional views, a method of manufacturing structure40ofFIG. 4is described. It is understood that the process steps used to form structure40can be the same steps used to form device10ofFIG. 1as well as the shielding structures described inFIGS. 20-23.FIG. 5shows structure40at an early step of fabrication. A dielectric layer71is formed over major surface18of semiconductor material11. In one embodiment, dielectric layer71is an oxide layer such as a low temperature deposited silicon oxide, and has a thickness from about 0.25 microns to about 0.4 microns. Next, a masking layer such as a patterned photoresist layer72is formed over dielectric layer71and then dielectric layer71is patterned to provide an opening73. In this embodiment, opening73corresponds to one of many trench openings for forming trenches22. The unmasked portion of dielectric layer71is then removed using conventional techniques and layer72is then removed.

FIG. 6shows structure40after one of trenches22has been etched into semiconductor layer14. For perspective, this view is parallel to the direction that trenches22run on devices20and30. That is, inFIG. 6trench22runs left to right. By way of example, trenches22are etched using plasma etching techniques with a fluorocarbon chemistry. In one embodiment, trenches22have a depth of about 2.5 microns, and a portion of dielectric layer71is removed during the process used to form trenches22. In one embodiment, trenches22have a width of about 0.4 microns and can taper or flare out to 0.6 microns where, for example, conductive structures431and432are formed to electrically connect gate electrodes28and shield electrodes21to gate runners54or56and shield electrode runners56or66respectively. Surfaces of trenches22can be cleaned using conventional techniques after they are formed.

FIG. 7shows structure40after additional processing. A sacrificial oxide layer having a thickness of about 0.1 microns is formed overlying surfaces of trenches22. This process is configured to provide a thicker oxide towards the top of trenches22compared to lower portions of trenches22, which places a slope in the trench. This process also removes damage and forms curves along lower surfaces of trenches22. Next, the sacrificial oxide layer and dielectric layer71are removed. Insulator layer24is then formed over surfaces of trenches22. By way of example, insulator layer24is a silicon oxide and has a thickness from about 0.1 microns to about 0.2 microns. A layer of polycrystalline semiconductor material is then deposited overlying major surface18and within trenches22. In one embodiment, the polycrystalline semiconductor material comprises polysilicon and is doped with phosphorous. In one embodiment, the polysilicon has a thickness from about 0.45 microns to about 0.5 microns. In one embodiment, the polysilicon is annealed at an elevated temperature to reduce or eliminate any voids. The polysilicon is then planarized to form region215. In one embodiment, the polysilicon is planarized using a chemical mechanical planarization process that is preferentially selective to polysilicon. Region215is planarized to portion245of insulator layer24, which is configured as a stop layer.

FIG. 8shows structure40after subsequent processing. A masking layer (not shown) is formed overlying structure40and patterned to protect those portions of region215that will not be etched such as portion217. Exposed portions of region215are then etched so that the etched portions are recessed below major surface18to form shield electrodes21. In one embodiment, region215is etched to about 0.8 microns below major surface18. In one embodiment, a selective isotropic etch is used for this step. The isotropic etch further provides a rounded portion216where shield electrode21transitions into portion217, which extends upward towards major surface18. This step further clears polycrystalline semiconductor material from exposed portions of the upper surfaces of trenches22. Any remaining masking materials can then be removed. In one embodiment, portion245of insulator layer24is exposed to an etchant to reduce its thickness. In one embodiment, about 0.05 microns are removed. Next, additional polycrystalline material is removed from shield electrode21so that upper surface210of shield electrode21including portion217is recessed below major surface18as shown inFIG. 9. In one embodiment, about 0.15 microns of material is removed.

FIG. 10shows structure40after still further processing. A portion of insulator layer24is removed where portion217of shield electrode21has been recessed. This forms an oxide stub structure247, which is configured to reduce stress effects during subsequent processing steps. After oxide stub structure247is formed, an oxide layer (not shown) is formed overlying shield electrode21and upper surfaces of trenches22. In one embodiment, a thermal silicon oxide growth process is used, which grows a thicker oxide overlying shield electrode21because shield electrode21is a polycrystalline material and a thinner oxide along exposed sidewalls of trenches22because these sidewalls are substantially monocrystalline semiconductor material. In one embodiment silicon oxide is grown and has a thickness of about 0.05 microns on sidewalls of trenches22. This oxide helps to smooth the upper surfaces of shield electrodes21. This oxide is then removed from the sidewalls of trenches22while leaving a portion of the oxide overlying shield electrode21. Next, insulator layer26is formed overlying the upper sidewalls of trenches22, which also increases the thickness of the dielectric material already overlying or formed on shield electrode21to form insulator layer27thereon. In one embodiment, a silicon oxide is grown to form insulator layers26and27. In one embodiment, insulator layer26has a thickness of about 0.05 microns, and insulator layer27has a thickness greater than about 0.1 microns.

FIG. 11shows structure40after polycrystalline semiconductor material has been formed overlying major surface18. In one embodiment, doped polysilicon is used with phosphorous being a suitable dopant. In one embodiment about 0.5 microns of polysilicon is deposited overlying major surface18. In one embodiment, the polysilicon is then annealed at an elevated temperature to remove any voids. Any surface oxide is then removed using conventional techniques, and the polysilicon is then planarized to form gate electrodes28. In one embodiment, chemical mechanical planarization is used with the oxide overlying major surface18providing a stop layer.

Next, gate electrodes28are subjected to an etch process to recess upper surface280below major surface18as shown inFIG. 12. In one embodiment, dry etching is used to recess upper surface280with a chemistry that is selective with respect to polysilicon and silicon oxide. In one embodiment, a chlorine chemistry, a bromine chemistry, or a mixture of the two chemistries is used for this step. It is convenient to use this etch step to remove polycrystalline semiconductor from the oxide layer above surface210of portion217so that when a silicide layer is used with gate electrode28, it does not form above surface210, which would complicate the contacting of shield electrode21in subsequent process steps.

FIG. 13shows structure40after silicide layer29has been formed overlying surface280. In one embodiment, silicide layer29is titanium. In another embodiment, silicide layer29is cobalt. In a further embodiment, a self-aligned silicide (salicide) process is used to form layer29. For example, in a first step, any residual oxide is removed from major surface280. Then, titanium or cobalt is deposited overlying structure40. Next, a lower temperature rapid thermal step (about 650 degrees Celsius) is used to react the metal and exposed polycrystalline semiconductor material. Structure40is then etched in a selective etchant to remove only unreacted titanium or cobalt. A second rapid thermal step at a higher temperature (greater than about 750 degrees Celsius) is then used to stabilize the film and lower its resistivity to form layer29.

In a next sequence of steps, ILD41is formed overlying structure40as shown inFIG. 14. In one embodiment, about 0.5 microns of phosphorous doped silicon oxide is deposited using atmospheric pressure chemical vapor deposition. Next, about 0.5 microns of silane based plasma-enhanced chemical vapor deposited oxide is formed on or over the phosphorous doped oxide. The oxide layers are then planarized back to a final thickness of about 0.7 microns using, for example, chemical mechanical planarization to form ILD41. InFIG. 14, insulator layer27and stub247are no longer shown within ILD41because they all comprise oxide in this embodiment, but it is understood that they can be present in the final structure.

FIG. 15shows structure40after trench openings151and152have been formed in ILD41to expose a portion of silicide layer29and shield electrode21. Conventional photolithography and etch steps are used to form openings151and152. Next, exposed portions of shield electrode21are further etched to recess part of portion217below surface210.

Next, conductive structures or plugs431and432are formed within openings151and152respectively as shown inFIG. 16. In one embodiment, conductive structures431and432are titanium/titanium-nitride/tungsten plug structures, and are formed using conventional techniques. In one embodiment, conductive structures431and432are planarized using, for example, chemical mechanical planarization so the upper surfaces of ILD41and conductive structures431and432are more uniform. Thereafter, a conductive layer is formed overlying structure40and patterned to form conductive gate runner56, shield electrode runner66and source metal layer44as shown inFIG. 4. In one embodiment, conductive layer44is titanium/titanium-nitride/aluminum-copper or the like. A feature of this embodiment is that the same conductive layer is used to form source electrode44, gate runners54and56, and shield electrodes56and66as shown inFIG. 2. Additionally, conductive layer46is formed adjacent substrate12as shown inFIG. 4. In one embodiment, conductive layer46is a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like.

FIG. 17is a partial top plan view of a contact or connective structure170according to a first embodiment that is configured to provide a contact structure for making contact to gate electrodes28and shield electrodes21within or inside of trenches22. That is, structure170is configured so that conductive contact to gate electrode28and shield electrode21can be made inside of or within trenches22. For perspective, connective structure170is one embodiment of a top view of structure40without conductive gate runner56, shield electrode runner66, conductive structures431and432, and ILD41. This view also shows insulator layer26adjacent gate electrode28as shown inFIG. 1. Additionally, this view shows one advantage of this embodiment. In particular, shield electrode21in connective structure170is surrounded by insulator layers24and27, which are thicker than insulator layers26. This feature reduces the oxide breakdown problem with previously known structures, which provides a more reliable device. In this embodiment, structure170is striped shape and contact to both gate electrodes28and shield electrodes21is made within a wider or flared portion171. Structure170then tapers down to a narrower portion172as it approaches, for example, the active area of the device. As shown inFIG. 17, gate electrode28has a width174within flared portion171that is wider than width176of shield electrode21within flared portion171. In this embodiment, end portion173of trench22terminates with a shield electrode21, which is surrounded by insulator layers24and27, which are thicker than insulator layer or gate dielectric layer26. In one embodiment, end portion173is adjacent to or in proximity to edge201or edge202of device20or device30shown inFIGS. 2 and 3.

FIG. 18is a partial top plan view of a contact connective structure180according to a second embodiment that is configured to provide a contact structure for making contact to gate electrodes28and shield electrodes21formed within or inside of trenches22. That is, structure180is configured so that conductive contact to gate electrode28and shield electrode21can be made inside of or within trenches22. In this embodiment, structure180includes a thin stripe portion221and a flared portion222that is wider than stripe portion221. In this embodiment, flared portion222provides a wider contact portion for making contact to shield electrode21. Structure180further includes another separate flared portion223that is wider than stripe portion221for making contact to gate electrode28. Like structure170, shield electrode21is surrounded by insulator layers24and27, which are thicker than insulator layers26. In one embodiment, shield electrode21includes a narrow portion211within stripe portion221and a wider portion212within flared portion222. In this embodiment, insulator layer24is within flared portion222and further extends into thin stripe portion221. In this embodiment insulator layer26is only within thin stripe portion221and flared portion223. In this embodiment, end portion183of trench22terminates with a shield electrode21, which is surrounded by thicker insulator layers24and27. In one embodiment, end portion183is adjacent to or in proximity to edge201or edge202of device20or device30shown inFIGS. 2 and 3.

FIG. 19is a partial top plan view of a contact or connective structure190according to a third embodiment that is configured to provide a contact structure for making contact to gate electrode28and shield electrode21within or inside of trench22. That is, structure90is configured so that conductive contact to gate electrode28and shield electrode21is made inside of or within trenches22. In this embodiment, trench22includes a thin stripe portion224and a flared portion226that is wider than stripe portion224. In this embodiment, flared portion226provides a wider contact portion for making contact to both gate electrode28and shield electrode21. Shield electrode21is surrounded by thicker insulator layers24and27, which is thicker than insulator layers26. In one embodiment, gate electrode28includes a narrow portion286within thin stripe portion224and a wider portion287within flared portion226. In this embodiment, insulator layer26is within thin stripe portion224and further extends into flared portion226. In this embodiment, thicker insulator layers24and27are only within flared portion224. In one embodiment, shield electrode21is within flared portion226only. It is understood that combinations of structures170,180and190or individual structures170,180, and190can be used in structure40with devices20and30. In this embodiment, end portion193of trench22terminates with a shield electrode21, which is surrounded by with thicker insulator layers24and27. In one embodiment, end portion193is adjacent to or in proximity to edge201or edge202of device20or device30shown inFIGS. 2 and 3.

Turning now toFIGS. 20-23, various shielding structure embodiments are described.FIG. 20shows a partial top plan view of a trench shielding structure261according to a first embodiment. Shielding structure261is suitable for use with, for example, devices20and30, and is conveniently formed using the processing steps used to form device or cell10and structure40described previously. Shielding structure261is an embodiment of a shielding structure that runs at least partially below or underneath gate pad52to better isolate or insulate gate pad52from semiconductor layer14. Structure261includes a plurality of trenches229, which are formed at least in part underneath gate pad52. Trenches229are conveniently formed at the same time as trenches22. Portions of trenches229are shown in phantom to illustrate that they are underneath gate pad52and shield electrode runner66.

As further shown inFIG. 21, which is a partial cross-sectional view of structure261taken along reference line XXI-XXI ofFIG. 20, in structure261trenches229are each lined with insulator layer24and include a shield electrode21. However, in one embodiment of structure261trenches229do not contain any gate electrode material28. That is, in this embodiment structure261does not include any gate or control electrodes. As shown inFIG. 20, shield electrodes21are connected to shield electrode runner66, and in one embodiment are electrically connected to source metal44. In another feature of the present embodiment, ILD41separates shield electrodes21from gate pad52and there are no other intervening polycrystalline or other conductive layers overlying major surface18between gate pad52and structure261. That is, structure261is configured to better isolate gate pad52from semiconductor region11without adding more shielding layers overlying the major surface as used in previously known devices. This configuration helps to reduce gate-to-drain capacitance and does so without extra masking and/or processing steps. In one embodiment, spacing88between adjacent trenches229in structure261is less than about 0.3 microns. In another embodiment spacing88is less than one half the depth89(shown inFIG. 21) of trenches22to provide a more optimum shielding. In one embodiment it was found that a spacing88of about 0.3 microns provides about a 15% reduction in gate-to-drain capacitance compared to a spacing88of 1.5 microns. In one embodiment of structure261, trenches229and shield electrodes21do not pass all of the way below gate pad52. In another embodiment, structure261and shield electrodes21pass all of the way the past gate pad52. In a still further embodiment, gate pad52contacts gate electrode28at an edge portion521of gate pad52as shown inFIG. 20.

FIG. 22shows a partial top plan view of a trench shielding structure262according to a second embodiment. Structure262is similar to structure261accept that structure262is placed to pass a plurality of trenches229and shield electrodes21below or underneath gate pad52and gate runner53to further isolate gate pad52and gate runner53from semiconductor layer14. In one embodiment of structure262, contact is made to shield electrodes21at both shield electrode runners64and66as shown inFIG. 22, which are further connected to source metal44. Structure262is configured to better isolate gate pad52and gate runner53from semiconductor region11. In structure262, a portion of trenches229pass all the way past or underneath at least a portion of gate pad52. That is, in one embodiment at least one trench229extends from at least one edge or side of gate pad52to another opposing edge of gate pad52.

FIG. 23shows a partial top plan view of a trench shielding structure263according to a third embodiment. Structure263is similar to structure261accept that structure263is placed to pass a plurality of trenches229and shield electrodes21below or underneath gate pad52and at least a portion of gate runner56. In one embodiment, a portion of trenches229and shield electrodes21below gate runner56pass all the way below or past gate runner56. In another embodiment, a portion of trenches229and shield electrodes21below gate runner56only pass a part of the way below gate runner56. In another embodiment, a portion of gate runner56makes contact to gate electrodes28at an edge portion568as shown inFIG. 23. Structure263is configured to better isolate gate pad52and at least a portion of gate runner56from semiconductor layer14. It is understood that all, one or combinations of structures261,262, and263can be used with, for example, devices20and30.

FIG. 24shows a partial top plan view of structure239from device20shown inFIG. 2. As shown inFIG. 24, conductive layer44includes portion446, which wraps around end561of gate runner56and connects to shield electrode runner66where contact is made to shield electrodes21.FIG. 24further shows an example of the location of trenches22and gate electrodes28where contact is made between gate runner56and gate electrode28. Additionally,FIG. 24shows trenches22having a striped shape and extending in a direction from the active area where conductive layer44is to the contact area where gate runner56and shield runner66are located. It is understood that the connective structures ofFIGS. 17,18and19can be used with structure239either individually or in combination. Structure239further illustrates an embodiment that provides for the use of one metal layer to connect the various structures.

In summary, a contact structure for a semiconductor device having a trench shield electrode has been described including a method of manufacture. The contact structure includes a gate electrode contact portion and a shield electrode contact portion within a trench structure. Contact is made to the gate electrode and the shield electrode within or in side the trench structure. The shield electrode contact portion is surrounded by a passivating layer that is thicker that the passivating layer used to form a gate dielectric layer. Additionally, several contact structure embodiments have been described that included flared portions for making contact to the gate and shield electrodes. The structures and method described herein improve the integration of shield electrodes with power devices and further improves reliability.

Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.