Semiconductor device with air-spacer

A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.

BACKGROUND

For example, it is generally desired to reduce stray capacitance among features of field effect transistors, such as capacitance between a gate structure and source/drain contacts, in order to increase switching speed, decrease switching power consumption, and/or decrease coupling noise of the transistors. Certain low-k materials, with a dielectric constant lower than that of silicon oxide, have been suggested as insulator materials providing lower relative permittivity to reduce stray capacitance. However, as semiconductor technology progresses to smaller geometries, the distances between the gate structure and source/drain contacts are further reduced, resulting in still large stray capacitance. Therefore, although existing approaches in transistor formation have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

The present disclosure is generally related to semiconductor devices and methods of forming the same. More particularly, the present disclosure is related to providing methods and structures for lowering stray capacitance between a gate structure and source/drain contacts of field effect transistors (FETs) in semiconductor manufacturing. In the forming of FETs, it is desired to increase switching speed, decrease switching power consumption, and decrease coupling noise. Stray capacitance generally has a negative impact on these parameters, especially from stray capacitance between a gate structure and source/drain contacts. As semiconductor technology progresses to smaller geometries, the distances between the gate and source/drain contacts shrink, resulting in larger stray capacitance. Consequently, stray capacitance in FETs has become more problematic. The present disclosure provides solutions in forming air-spacers surrounding gate structures instead of spacers conventionally made of a solid dielectric material, lowering the relative permittivity (or dielectric constant) between the gate and source/drain contacts and thereby lowering stray capacitance.

FIG. 1illustrates a flow chart of a method100for forming semiconductor devices according to the present disclosure. The method100is an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method100, and some operations described can be replaced, eliminated, or relocated for additional embodiments of the method. The method100is described below in conjunction withFIGS. 2-9, which illustrate cross-sectional views of a semiconductor device200during various fabrication steps according to an embodiment of the method100. The device200may be an intermediate device fabricated during processing of an integrated circuit (IC), or a portion thereof, that may comprise static random access memory (SRAM) and/or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (pFETs), n-type FETs (nFETs), FinFETs, metal-oxide semiconductor field effect transistors (MOSFET), and complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. Furthermore, the various features including transistors, gate stacks, active regions, isolation structures, and other features in various embodiments of the present disclosure are provided for simplification and ease of understanding and do not necessarily limit the embodiments to any types of devices, any number of devices, any number of regions, or any configuration of structures or regions.

At operation102, the method100(FIG. 1) provides a precursor of the device200(FIG. 2A). For the convenience of discussion, the precursor of the device200is also referred to as the device200. The device200may include a substrate202and various features formed therein or thereon. The substrate202is a silicon substrate in the present embodiment. Alternatively, the substrate202may comprise another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the substrate202is a semiconductor on insulator (SOI).

In some embodiments, the substrate202includes an insulator (or an isolation structure) that may be formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating material. The insulator may be shallow trench isolation (STI) features. In an embodiment, the insulator is formed by etching trenches in the substrate202, filling the trenches with an insulating material, and performing a chemical mechanical planarization (CMP) process to the substrate202including the insulating material. The substrate202may include other isolation structure(s) such as field oxide and LOCal Oxidation of Silicon (LOCOS). The substrate202may include a multi-layer isolation structure.

At operation104, the method100(FIG. 1) forms one or more FETs204(e.g., FETs204aand204b) on the substrate202(FIG. 2A). The FETs204may include n-type FETs, p-type FETs, or a combination thereof. In some embodiments, FETs204aand204bare both n-type FETs or are both p-type FETs. In alternative embodiments, FET204ais an n-type FET and FET204bis a p-type FET.

Each FET204includes a gate stack208. The gate stack208is disposed over the substrate202. In various embodiments, the gate stack208is a multi-layer structure. The gate stack208may include a gate dielectric layer210and a gate electrode layer212. In some embodiments, the gate dielectric layer210further includes a high-k dielectric layer and an interfacial layer interposed between the substrate202and the high-k dielectric layer. In various embodiments, the interfacial layer may include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. The high-k dielectric layer is formed by a suitable process such as an atomic layer deposition (ALD). Other methods to form the high-k dielectric layer include metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), UV-Ozone Oxidation and molecular beam epitaxy (MBE). In one embodiment, the high-k dielectric material includes hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal-oxides, or combinations thereof. Alternatively, the high-k dielectric layer includes metal nitrides or metal silicates.

In some embodiments, the gate electrode layer212may be a poly-silicon layer or a metal gate electrode layer. The metal gate electrode layer may further include multiple layers, such as a work function metal layer and a metal fill layer. The work function metal layer may include a p-type work function metal layer or an n-type work function metal layer. The p-type work function metal layer comprises a metal selected from, but not limited to, the group of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The n-type work function metal layer comprises a metal selected from, but not limited to, the group of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The p-type or n-type work function metal layer may further include a plurality of layers and may be deposited by CVD, PVD, and/or other suitable process. The one or more metal layers may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and/or other suitable materials, and may be formed by CVD, PVD, plating, and/or other suitable processes. The metal fill layer may include aluminum (Al), tungsten (W), or copper (Cu) and/or other suitable materials. The metal fill layer may be formed by CVD, PVD, plating, and/or other suitable processes.

A gate spacer is formed on sidewalls of each gate stack208. Referring toFIG. 2A, in various embodiments, the gate spacer may include multiple layers such as a seal spacer214and a dummy spacer216. The seal spacer214includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), other dielectric material, or combination thereof. The seal spacer214protects the four approximately vertical sides of the gate stack208. The dummy spacer216may compose of silicon oxide (SiO2), aluminum oxide (AlO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON). Generally, the composition of the seal spacer214and the dummy spacer216are selected such that the seal spacer214has a high etch selectivity as compared to the dummy spacer216. The dummy spacer216will be removed in subsequent operations of the method100to form a void as an air-spacer, while the seal spacer214is substantially remained. Therefore, the dummy spacer216is also referred to as the sacrificial spacer216. The forming of the air-spacer will be further described in details later. In an example, the seal spacer214is formed by blanket depositing a dielectric layer (e.g., a silicon nitride layer having a substantially uniform thickness) over the device200by a CVD process and then anisotropically etching to remove portions of the dielectric layer to form the seal spacer214. The sacrificial spacer216may be formed with a similar process. In some embodiments, the sacrificial spacer216has a thickness in a range from about 2 nm to about 4 nm.

The source/drain (S/D) regions218are also formed in the substrate202. The S/D regions218may be n-type doped regions and/or p-type doped regions for forming active devices. The S/D regions218may include heavily doped S/D (HDD), lightly doped S/D (LDD), raised regions, strained regions, epitaxially grown regions, and/or other suitable features. The S/D regions218may be formed by etching and epitaxial growth, S/D implantation, S/D activation, and/or other suitable processes. In an embodiment, the S/D regions218further include silicidation or germanosilicidation. For example, silicidation may be formed by a process that includes depositing a metal layer, annealing the metal layer such that the metal layer is able to react with silicon to form silicide, and then removing the non-reacted metal layer. In an embodiment, the device200includes fin-like active regions for forming multi-gate FETs such as FinFETs. To further this embodiment, the S/D regions218and the channel region224may be formed in or on the fins. The channel region224is under the gate stack208and interposed between a pair of S/D regions218. The channel region224conducts currents between the respective S/D regions218when the semiconductor device200turns on, such as by biasing the gate electrode layer212.

Still referring toFIG. 2A, in the present embodiment, the S/D regions218are formed by first etching S/D recesses in the substrate202followed by epitaxially growing S/D regions218in the respective recesses. Based on the profile of the S/D recesses, the S/D regions218may have a substantially u-shaped profile and a sidewall of each of the S/D regions218is substantially aligned with the edge (or outer boundary) of the sacrificial spacer216. The respective sidewall is spaced from the gate stack208by a distance260. In some embodiments, the distance260is in a range from about 2 nm to about 10 nm. In some embodiment where the spacers214/216are thicker than desired which enlarges the distance260and it is desired that the distance260falls nonetheless into a shorter range, the S/D regions218can be formed to have a substantially diamond-shaped profile, such as S/D regions218ainFIG. 2B. Referring toFIG. 2B, some sidewalls of the S/D regions218aare extended towards the gate stack208underneath the spacers214/216. In one example, the S/D recesses are formed with an etching process that includes both a dry etching and a wet etching process where etching parameters thereof are tuned (such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, and other suitable parameters) to achieve the desired recesses profile. For the convenience of discussion, the device200with the S/D regions in a shape as shown inFIG. 2Ais used as an example for subsequent operations. Persons having ordinary skill in the art should recognize that the device200with the S/D regions in a shape as shown inFIG. 2Bcan also be used for the subsequent operations.

Referring back toFIG. 2A, in the present embodiment, the device200includes a contact etch stop (CES) layer220over the substrate202and on sidewalls of the sacrificial spacer216, and further includes an inter-layer dielectric (ILD) layer222over the CES layer220. The CES layer220may include a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), other dielectric materials, or combination thereof. The CES layer220may be formed by a plasma-enhanced CVD (PECVD) process and/or other suitable deposition or oxidation processes. The ILD layer222may include materials such as or silicon oxide, doped silicon oxide such as borophosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, and/or other suitable dielectric materials. The ILD layer222may be deposited by a PECVD process, a flowable CVD (FCVD) process, or other suitable deposition technique. The composition of the CES layer220and the ILD layer222are selected such that the CES layer220has some etch selectivity as compared to the ILD layer222. In an embodiment, the CES layer220is deposited as a blanket layer over the substrate202covering various structures thereon, and the ILD layer222is deposited over the CES layer220. Subsequently, the method100(FIG. 1) proceeds to operation106by performing a chemical mechanical planarization (CMP) process to polish the ILD layer222and expose the gate stack208(FIG. 2A). As a result, portions of the CES layer220remain over the substrate202between adjacent sacrificial spacers216.

At operation108, the method100(FIG. 1) forms another ILD layer228over the device200(FIG. 3). The ILD layer228may include silicon oxide, low-k dielectric material, or other suitable dielectric material, formed by CVD or other suitable method. For example, the ILD layer228may be formed by a PECVD process, a FCVD process, or other suitable deposition processes. In some embodiments, the ILD layer228may include different or same material as the ILD layer222. A CMP process may follow operation108to remove excessive dielectric materials.

At operation110, the method100(FIG. 1) patterns the ILD layer228to form the S/D via holes230over the S/D regions218(FIG. 4). In an embodiment, operation110includes a photolithography process and etching processes. The photolithography process may include forming a photoresist (or resist) over the ILD layer228, exposing the resist to a pattern that defines various geometrical shapes for the S/D via holes230, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. The masking element, or a derivative thereof, is then used for etching recesses into the ILD layer228. The masking element (e.g., a patterned resist) is subsequently removed. The etching processes may include one or more dry etching processes, wet etching processes, and other suitable etching techniques. For example, the etching processes may include a two-step etching. The first etching step removes portions of the ILD layers228and222to expose a bottom portion of the CES layer220, and the second etching step removes the bottom portion of the CES layer220, thereby exposing a portion of the S/D regions218. In some embodiments, the ILD layer222is substantially completely removed in the operation11.

At operation112, the method100(FIG. 1) form one or more S/D contacts232in the S/D via holes230(FIG. 5). In an embodiment, the S/D contacts232include a metal such as tungsten (W), aluminum (Al), copper (Cu), combinations thereof, or other suitable conductive material. In an embodiment, the contact metal is deposited using a suitable process, such as CVD, PVD, plating, and/or other suitable processes. A CMP process may follow operation112to remove excessive metals.

At operation114, the ILD layer228is removed, forming openings240that expose layers214,216,220, and the gate stack208, as shown inFIG. 6. In an embodiment, the operation114includes an etching process that is tuned to etch the ILD layer228while the other layers,214,216,220, and the gate stack208, remain substantially unchanged in the etching process. In embodiments, the operation114may use a dry etching, a wet etching, or other suitable etching processes.

The method100(FIG. 1) proceeds to operation116where trench250for creating the air-spacer structure is formed (FIG. 7). Specifically the trench250is formed by etching the sacrificial spacer216. In an embodiment, the trench250is filled with air, forming an air gap between the seal spacer214and the CES layer220. The sidewalls of the seal spacer214and the CES layer220are exposed in the trench250.

Generally, the composition of the seal spacer214and the CES layer220are selected such that the seal spacer214and the CES layer220has a high etch selectivity as compared to the sacrificial spacer216. As a result, the etching process may remove the sacrificial spacer216while the seal spacer214and the CES layer220remain relatively and/or substantially unchanged in thickness. In some embodiments, the seal spacer214and the CES layer220contains nitride (or nitride rich) and the sacrificial spacer contains oxide (or oxide rich). For example, each of the seal spacer214and the CES layer220may contain a composition selected from a group of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride (tuned to be nitride rich), and a combination thereof, while the sacrificial spacer216may contain a composition selected from a group of silicon oxide, aluminum oxide, silicon carbon oxynitride (tuned to be oxide rich), and a combination thereof. The seal spacer214and the CES layer220may contain the same or different materials. In one specific embodiment, the seal spacer214contains silicon nitride, the CES layer220contains silicon carbonitride, and the sacrificial spacer216contains aluminum oxide. In another specific embodiment, the seal spacer214contains silicon carbonitride, the CES layer220contains silicon carbon oxynitride, and the sacrificial spacer216contains aluminum oxide. In alternative embodiments, the seal spacer214and the CES layer220contains oxide (or oxide rich) and the sacrificial spacer216contains nitride (or nitride rich). For example, each of the seal spacer214and the CES layer220may contain a composition selected from a group of silicon oxide, aluminum oxide, silicon carbon oxynitride (tuned to be oxide rich), and a combination thereof, while the sacrificial spacer216may contain a composition selected from a group of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride (tuned to be nitride rich), and a combination thereof. In yet another specific embodiment, the seal spacer214contains silicon oxide, the CES layer220contains silicon carbon oxynitride, and the sacrificial spacer216contains silicon nitride.

In embodiments, the operation116uses an etching process with an etchant to selectively remove the sacrificial spacer216. The operation116may use a dry etching, a wet etching, or other suitable etching processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and/or acetic acid (CH3COOH); or other suitable wet etchant. In one example, the sacrificial spacer216contains silicon oxide and the wet etching process includes applying DHF. In another example, the sacrificial spacer216contains aluminum oxide and the wet etching process includes applying an ammonia and hydrogen peroxide mixture (APM) such as an SC1 solution (NH4OH:H2O2:H2O). In yet another example, the sacrificial spacer216contains silicon nitride and the wet etching process includes applying an acid containing H3PO4.

The method100(FIG. 1) proceeds to operation118where a cap structure for the air gap (void) is formed above the trench250. Specifically, an ILD layer252is deposited above the device200, as shown inFIG. 8A. The ILD layer252also forms a cap or upper wall for the air gap in the trench250. In an embodiment, the ILD layer252is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), coating process, and/or other suitable process. In an embodiment, the ILD layer252is deposited by a CVD process. The formation of the ILD layer252is tuned to effectively close up the trench250, resulting in the air gap. The parameters in the CVD process (e.g., pressure, temperature, and gas viscosity) are tuned in a way such that the gap fill behavior of depositing dielectric materials maintains the air gap without filling up the trench250. In the present embodiment, the CVD process employs a setting with pressure less than about 0.75 torr and temperature higher than about 75 degree Celsius. Hence, the dielectric material of the ILD layer252may be deposited at the upper portion of the trench250to enclose the opening of the trench250without a significant amount being deposited in a lower portion of the trench250. Respective air gap can therefore be formed below the dielectric material of the ILD layer252and between the seal spacer214and the CES layer220. The sidewalls of the seal spacer214and the CES layer220are exposed in the air gap. A gas, such as a gas(es) used during the deposition of the dielectric material of the ILD layer252or any other species that can diffuse into the air gap, may be in the air gap. The ILD layer252extends laterally from the air gap to top surfaces of the seal spacer214and the gate stack208. The ILd layer252also covers the CES layer220and the S/D contacts232. In some embodiments, the ILD layer252may include silicon nitride, silicon oxynitride, silicon carbonitride. In some embodiments, the ILD layer252may include an oxide, such as TEOS, BPSG, FSG, PSG, and BSG. The ILD layer252may include different or same material as the ILD layer228. In the present embodiment, the ILD layer252is a silicon oxide layer.

Still referring toFIG. 8A, in some embodiments, substrate202is exposed in the trench250after the etching of the sacrificial layer216. Therefore, the air gap defined in the trench250spans horizontally from a sidewall of the spacer layer214to a sidewall of the CES layer220, and spans vertically from a top surface of the substrate202to a bottom surface of the ILD layer252. In alternative embodiments, the sacrificially layer216may not be completely removed from the trench250in the etching process (e.g., by controlling the etching time) and have some residue216aremained in the bottom of the trench250, which still covers the substrate202, as shown inFIG. 8B. In this case, the air gap spans vertically from a bottom portion of the sacrificial layer216to a bottom surface of the ILD layer252, instead. In the present embodiment, the air gap has a width in a range from about 2 nm to about 4 nm. The air gap forms air-spacer structures surrounding the gate stack208, which helps reducing the effective dielectric constant of material layers between the gate stack208and the S/D contacts232and thereby reducing respective stray capacitance.

At operation120, the method100(FIG. 1) performs another CMP process to polish the ILD layer252and expose the S/D contacts232(FIG. 9). Although not shown inFIG. 1, the method100may proceed to further processes in order to complete the fabrication of the device200. For example, the method100may form multi-layer interconnect structure that connects the gate stacks208and the S/D contacts232with other parts of the device200to form a complete IC.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. Spacers used in forming fins of FinFETs can be processed according to the above disclosure. For example, embodiments of the present disclosure provide a method of forming air-spacers surrounding the gate stack. The relative permittivity (or dielectric constant) between the gate stack and source/drain contacts is lower, which reduces interference, noise, and parasitic coupling capacitance between interconnects. Further, the disclosed methods can be easily integrated into existing semiconductor manufacturing processes.

In one exemplary aspect, the present disclosure is directed to a method. The method includes forming a gate structure on a substrate; forming a seal spacer covering a sidewall of the gate structure; forming a sacrificial spacer covering a sidewall of the seal spacer; forming source/drain (S/D) regions sandwiching a channel region that is under the gate structure; depositing a contact etch stop (CES) layer covering a sidewall of the sacrificial spacer; removing the sacrificial spacer to form a trench, wherein the trench spans between a sidewall of the CES layer and the sidewall of the seal spacer; and depositing an inter-layer dielectric (ILD) layer, wherein the ILD layer caps the trench, thereby defining an air gap inside the trench.

In another exemplary aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes forming a gate stack on a semiconductor substrate; forming a seal spacer covering a sidewall of the gate stack; forming a sacrificial spacer covering a sidewall of the seal spacer; forming source/drain (S/D) regions sandwiching a channel region that is under the gate stack; forming a contact etch stop (CES) layer covering a sidewall of the sacrificial spacer; depositing a first inter-layer dielectric (ILD) layer over the gate stack; patterning the first ILD layer, thereby forming an opening exposing one of the S/D regions; forming an S/D contact in the opening; after the forming of the S/D contact, removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the CES layer and the sidewall of the seal spacer; and depositing a second ILD layer over the S/D contact, the seal spacer, and the gate stack, wherein the second ILD layer seals the trench, thereby defining a void inside the trench.

In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate having source/drain (S/D) regions with a channel region interposed therebetween; a gate stack over the channel region; a spacer layer covering sidewalls of the gate stack; an S/D contact over one of the S/D regions; a contact etch stop (CES) layer covering sidewalls of the S/D contact; and an inter-layer dielectric (ILD) layer covering the CES layer, the spacer layer, and the gate stack, wherein the CES layer and the spacer layer are spaced from each other, defining a gap therebetween, the gap being capped by the ILD layer.