Memory-Module with an increased density for mounting semiconductor chips

The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

FIELD OF THE INVENTION

The present invention relates to technology for manufacturing a semiconductor and, particularly, to technology that can be effectively applied to highly densely mounting the semiconductor chips on a memory-module.

BACKGROUND OF THE INVENTION

The technology described below is the one discussed by the present inventors in studying and accomplishing the present invention, and is roughly as described below.

A memory-module is one of the module products mounting a plurality of semiconductor devices.

The memory-module includes a plurality of semiconductor devices having memory chips that are mounted on one surface or on both the front and back surfaces of a module board. In mounting the memory on a personal computer or a work station, the memory-module mounts the memory by being mounted on a mother board provided in the personal computer or the work station with each module as a unit.

As the semiconductor device mounted on the memory-module, there has been used the one of the surface mount type called SMD (surface mount device) having a semiconductor chip sealed with a resin and having lead terminals (external terminals) for drawing the electrodes to the outside of the resin-sealed portion, as represented by TSOP (thin small outline package) and TCP (tape carrier package).

Module products of various structures have been disclosed in, for example, Japanese Patent Laid-Open Nos. 209368/1998, 258466/1989 and 86492/1995.

Japanese Patent Laid-Open No. 209368/1998 discloses a CPU (central processing unit) module, and Japanese Patent Laid-Open No. 258466/1989 discloses a memory-module mounting SMD parts having a DRAM (dynamic random access memory) chip. Japanese Patent Laid-Open No. 86492/1995 discloses technology for applying an underfiller resin in the MCM (multi-chip module).

SUMMARY OF THE INVENTION

The SMD parts to be mounted on the above-mentioned conventional memory-module have a large package size compared with the chip size due to the package body (semiconductor device body) that is sealed and the outer leads.

As a result, limitation is imposed on the number of the semiconductor chips that can be mounted on the module board.

There further arouses a problem in that due to the inductance added as a result of the sealing, it becomes difficult to design a memory-module having a high-speed interface to meet a high-speed CPU.

The object of the present invention is to provide a memory-module that offers an increased module capacity as a result of enhancing the density for mounting the semiconductor chips and is capable of coping with a high-speed bus, and a method of manufacturing the same.

The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the attached drawings.

Briefly described below are representative examples of the inventions disclosed in this application.

That is, the memory-module of the present invention comprises protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips; lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.

Further, the memory-module of the invention comprises protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with rewirings which are wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes in the areas of semiconductor chips; lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.

In mounting the protruded terminal semiconductor devices together with the lead terminal semiconductor devices in a mixed manner, therefore, the mounting is accomplished requiring mounting areas nearly equal to those of the semiconductor chips.

Therefore, the semiconductor chips can be mounted requiring the least areas, making it possible to increase the density for mounting the semiconductor chips.

This makes it possible to increase the module capacity of the memory-module.

The method of manufacturing a memory-module according to the present invention comprises a step for preparing protruded terminal semiconductor devices having protruded terminals as external terminals, and wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes of semiconductor chips; a step for preparing lead terminal semiconductor devices having outer leads which are the external terminals electrically connected to the bonding electrodes of the semiconductor chips; a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices; are mounted in a mixed manner on the module board.

Further, the method of manufacturing a memory-module of the present invention comprises a step for preparing protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, and rewirings which are wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes in the areas of semiconductor chips; a step for preparing lead terminal semiconductor devices having outer leads which are external terminals electrically connected to the bonding electrodes of the semiconductor chips; a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a diagram illustrating the structure of a memory-module according to an embodiment 1 of the present invention, whereinFIG. 1Ais a plan view,FIG. 1Bis a side view andFIG. 1Cis a sectional view along the A—A section ofFIG. 1A,FIG. 2is an enlarged partial sectional view illustrating, on an enlarged scale, a portion B in the sectional view ofFIG. 1C,FIG. 3is a view of block circuits of the memory-module shown inFIG. 1,FIG. 4is a perspective view illustrating the appearance of the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown inFIG. 1,FIG. 5is a diagram illustrating an SMD (surface mount-type semiconductor device having lead terminals, which is hereinafter referred to as lead terminal semiconductor device) mounted on the memory-module shown inFIG. 1and the structure of a wafer process package, whereinFIG. 5Ais a plan view of the SMD andFIG. 5Bis a plan view of the wafer process package,FIG. 6is a process flow illustrating the steps for manufacturing the wafer process package mounted on the memory-module shown inFIG. 1,FIGS. 7A,7B,7C,7D,7E and7F are enlarged partial sectional views illustrating the structure of the semiconductor wafer corresponding to the major steps in the process flow shown inFIG. 6,FIG. 8is a basic mounting flow illustrating the procedure for mounting the wafer process package and the SMD on the module board so as to be mounted on the memory-module shown inFIG. 1,FIG. 9is a mounting flow illustrating the procedure for mounting the wafer process package on the module board so as to be mounted on the memory-module shown inFIG. 1,FIG. 10is an enlarged partial perspective view illustrating a method of applying an underfiller resin onto the wafer process package mounted on the memory-module shown inFIG. 1,FIGS. 11A,11C,11E and11G are perspective views illustrating the permeation of the underfiller resin that is applied as shown inFIG. 10andFIGS. 11B,11D,11F and11H are plan views showing the semiconductor chip in a see-through manner,FIGS. 12 and 13are plan views illustrating the modified structures of the memory-module of the embodiment 1 of the present invention,FIGS. 14A,14C,14E and14G are perspective views illustrating the permeation of the underfiller resin that is applied according to modified examples of the embodiment 1 of the invention andFIGS. 14B,14D,14F and14H are plan views illustrating a semiconductor chip in a see-through manner,FIG. 15is a view illustrating a modified structure of the memory-module according to the embodiment 1 of the present invention, whereinFIG. 15Ais a plan view andFIG. 15Bis a side view,FIG. 16is a side view illustrating the memory-module ofFIG. 15in a warped state,FIG. 17is a plan view illustrating a modified structure of the memory-module according to the embodiment 1 of the present invention, andFIG. 18is a side view illustrating the memory-module ofFIG. 17in a warped state.

A memory-module100of the embodiment 1 shown inFIG. 1comprises protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals and having wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes1aof the semiconductor chips1; TSOPs (thin small outline packages) which are lead terminal semiconductor devices20having semiconductor chips, outer leads21as the external terminals and are mounted via the outer leads21which are electrically connected to the bonding electrodes1aof the semiconductor chips1; and a module board2for supporting the protruded terminal semiconductor devices and TSOPs20; wherein the protruded terminal semiconductor devices and the TSOPs20are mounted in a mixed manner on the module board2by the simultaneous reflowing.

Here, the protruded terminal semiconductor device has a plurality of bump electrodes11(protruded terminals) that serve as the external terminals arranged in an area of a package body13(semiconductor device body), and wiring portions for expanding the pitch among the bump electrodes11to be wider than the pitch among the bonding electrodes1aof the semiconductor chip1.

The lead terminal semiconductor device has a plurality of outer leads21serving as the external terminals that are arranged protruding from the package body22(semiconductor device body).

In the protruded terminal semiconductor device and the lead terminal semiconductor device, the bonding electrodes1aof the semiconductor chip1are formed by using, for example, aluminum or the like, and are electrically connected to the bonding wires when the wires are to be bonded.

The external terminals of the protruded terminal semiconductor device and of the lead terminal semiconductor device are electrically connected to the connection electrodes on the side of the module board2when the semiconductor devices are mounted on the mounting board such as the module board2.

The embodiment 1 deals with the case where the protruded terminal semiconductor device is a wafer process package (hereinafter abbreviated as WPP)10which is a small semiconductor device of a chip size.

Therefore, the memory-module100of the embodiment 1 includes WPPs10which are the protruded terminal semiconductor devices of a chip size, TSOPs20which are SMD (surface mount type package) parts and are lead terminal semiconductor devices, and an EEPROM (electrically erasable programmable read-only memory)5which is a nonvolatile read-only memory as an example of another lead terminal semiconductor device, that are mounted in a mixed manner on the module board2.

Here, as shown inFIG. 4, the WPP10is a protruded terminal semiconductor device having bump electrodes11which are the protruded terminals serving as the external terminals, and is mounted on the module board2via bump electrodes11, and is provided with rewirings12which are wiring portions for expanding the pitch among the bump electrodes11to be wider than the pitch among the bonding electrodes1ain an area of the semiconductor chip1.

The bump electrodes11used for the WPP10have little dispersion in the height, decreasing percent defective when it is mounted on the board and, hence, improve the mounting yield. Besides, the bump electrodes11have a mounting height of about 0.13 mm, which makes it possible to decrease the mounting height.

Referring toFIG. 1, on the memory-module100are further mounted capacitors3, small surface-attached resistors4and other electronic parts in addition to the WPPs10, TSOPs20and EEPROM5.

That is, the memory-module100of the embodiment 1 includes 18 WPPs10, two TSOPs20,18capacitors3, 36 small surface-attached resistors4and one EEPROM5that are mounted on either the front surface or the back surface thereof, and 18 WPPs10that are mounted on the surface on the opposite side thereof.

In the memory-module100of the embodiment 1, there are arranged the WPPs10in a total number of 18 in a sequence on both sides of the two TSOPs20(ten on one side and eight on the other side with the TSOPs20being sandwiched therebetween) on one surface of the module board2.

Between the two TSOPs20, the one (TSOP20arranged on the upper side inFIG. 1) is a PLL (phase-locked loop)6which is a frequency control means and the other one (TSOP20arranged on the lower side inFIG. 1) is a register8having a register function.

That is, in the memory-module100of the embodiment 1, both the PLL6and the register8are the lead terminal semiconductor devices.

Each capacitor3is arranged to correspond to each WPP10close thereto.

Further, a total of 36 small surface-attached resistors4are arranged in sequence; i.e., two for each WPP10. The small surface-attached resistors4are provided to correspond to the I/Os of the memory-module100. In the memory-module100of the embodiment 1, there are provided 36 I/Os on one surface and, hence, the surface-attached resistors4are mounted in a number of 36. The small surface-attached resistors4of the number of 36 are arranged in a sequence nearly along and near the connection terminals2awhich are the external terminals of the module board2.

Referring toFIG. 1A, the module board2of the memory-module100measures, for example, L=133.35 mm and M=38.1 mm, and the mounting height (max) is N=4 mm as shown inFIG. 1B.

In the memory-module100of the embodiment 1, further, the TSOPs20and the WPPs10are mounted by the simultaneous reflowing. As shown inFIG. 2, however, the WPP10is sealed with the underfiller resin after the reflow, so that a sealing portion14is formed.

That is, the surrounding of the bump electrodes11between the package body13of WPP10and the module board2is sealed with a resin thereby to form the sealed portion14.

The memory-module100shown inFIG. 1uses the WPPs10as DRAMs and further uses the module board2of a bus of a width of 72 bits with error code correction.

Therefore, the memory-module100mounts a total of 36 DRAMs (WPPs10) on both the front and back surfaces of the module board2. When the DRAM has, for example, 64 megabits (16 M×4), the DRAM module has a constitution of 16 words×72 bits×2 banks.

FIG. 3is a diagram of block circuits of the memory-module100shown inFIG. 1, i.e., the diagram of block circuits of the DRAM module of the constitution of 16 words×72 bits×2 banks.

In the structure ofFIG. 3, the RS0system and the RS2system of the bank1operate simultaneously, and the RS1system and the RS3system of the bank2operate simultaneously. The bank1or the bank2is selected by a register8. When the bank1is read out, the bank2is not read out. Similarly, when the bank2is read out, the bank1is not read out.

A terminal A (S0to S3) of the register8is connected to a chip select (CS) terminal of the DRAM (WPP10) of either the bank1or the bank2. The bank that is selected by the register8forms an input to the CS terminal of the selected semiconductor chip1.

D0to D35of each chip represent the WPPs10of the number of 36, and the [I (input)/O (output)0to I/O3] terminals of each chip are connected to the connection terminals2aof the module board2as independent terminals.

In all DRAMs, the I/Os used as data consist of 64 bits of from DQ0to DQ63, and the I/Os used as check consist of 8 bits of from CB0to CB7. The sum of the two constitutes a two-bank constitution of 72 bits.

Symbols attached to the terminals shown inFIG. 3are described below. [A0to A11] are address inputs, [DQ0to DQ63] are data inputs/outputs, [CB0to CB7] are check bits (data inputs/outputs), [S0to S3] are chip select inputs, [RE] is a row enable (RAS) input, [CE] is a column enable (CAS) input, [W] is a write enable input, [DQMB0to DQMB7] are bite data masks, [CK0to CK3] are clock inputs, [CKE0] is a clock enable input, [WP] is a write protection for serial PD, [REGE] is a register enable, [SDA] is a data input/output for serial PD, [SCL] is a clock input for serial PD, [SA0to SA2] are serial address inputs, [Vcc] is a power source of the high-potential side, [Vss] is a ground, and [NC] is a non-connection.

Next, the structure of the WPP10will be described in detail. Referring toFIG. 4, the bonding electrodes1aof the semiconductor chip1in the WPP10are electrically connected to the solder bump electrodes11which are the external terminals through rewirings12.

That is, the bonding electrodes1aarranged at a narrow pitch are expanded by the rewirings12to a pitch of the bump electrodes11that are electrically connected thereto.

This is to form a package of a chip size by forming functional portions of the elements in a unit of the wafer and, then, effecting the dicing to divide into individual semiconductor chips1.

Therefore, the device is efficiently produced at a low cost compared with the small packages assembled by a method of production similar to that of manufacturing packages of the SMD (surface mount type) parts.

FIG. 5illustrates the TSOP20which is an SMD part and the WPP10which is the protruded terminal semiconductor device of the chip size, from which a difference in the size can be comprehended.

FIG. 5Ais a plan view of the TSOP20mounted on the memory-module100shown inFIG. 1, andFIG. 5Bis a plan view of the WPP10mounted on the memory-module100shown inFIG. 1.

As shown inFIG. 5, compared to the DRAM of the SMD (surface mount) type package such as TSOP20, the WPP10can be realized in a small size since it has neither the inner leads nor the outer leads21.

By mounting the DRAMs in the form of WPPs10on the module board2as in the memory-module100of the embodiment 1, therefore, the mounting area can be greatly reduced as compared to when the TSOPs20that are formed by being individually treated are mounted.

That is, by mounting the WPPs10, the mounting area can be minimized so far as the semiconductor chips1are mounted and, hence, the module capacity can be greatly increased.

The same capacity can be realized even by mounting the flip chips which is the mounting of bare chips. In mounting the flip chips, however, there is formed no rewiring12. Accordingly, the pitch is small among the external terminals, and it is not allowed to accomplish the mounting by reflow simultaneously with the SMD type parts. Therefore, the parts mounting the bare chips must be mounted one by one by using a flip chip bonder, which is inferior in efficiency to mounting the WPPs10.

In other words, the WPPs10are mounted without using any special mounting device such as the flip chip bonder, and makes it possible to decrease the number of the steps for mounting.

Further, the WPPs10can be mounted permitting the pitch among the bump electrodes11that are the external terminals to be expanded to be broader than the pitch of when the flip chips are mounted, enabling the wiring rule to be broadened on the module board2. This does not drive up the cost of the module board2, and makes it possible to realize the memory-module100of a highly dense mounted form suppressing the cost.

In the WPP10, further, the wiring lengths from the bonding electrodes1aof the semiconductor chip1to the bump electrodes11which are the external terminals become shorter than the wiring lengths from the bonding electrodes1ato the ends of the outer leads21of the SMD part such as TSOP20, making it possible to transfer signals at a high speed.

This enables the memory-module100to operate at high speeds and, hence, to cope with a high-speed bus.

Described below is the reason why the semiconductor devices (packages) mounted on the memory-module100of the embodiment 1 are not all in the form of WPPs10, i.e., why the WPPs10which are the protruded terminal semiconductor devices of the chip size and the SMD parts (TSOPs20in the embodiment 1) are mounted in a mixed manner.

The WPPs10are formed by treating the wafers in the preceding steps. In the subsequent steps, therefore, they are all treated in a unit of the wafer even in a step of forming the devices one by one.

When the number of non-defective products is small in a piece of wafer, the defective products must be worked, driving up the cost.

As a result, for some kinds of products for which the yields of the semiconductor wafers are not so high, no cost merit is obtained.

Further, a reticle for exposure to light must be prepared for every kind of products. For the products that are not produced in large quantity, therefore, a material having general applicability is used for the semiconductor devices (packages) that are incorporated in the lead frames. Therefore, the products that are not produced in large quantity are better not in the form of the WPPs10.

Besides, physical conditions play important roles. From a relationship between the number of the terminals to be drawn out and the chip size, the logical devices in the form of small chips but having many terminals to be drawn out, are better not in the form of the WPP10. This is because the electrode pads (diffusion-preventing adhesion layers7cshown inFIG. 7) and the bump electrodes11cannot be formed after the rewirings12are formed from the bonding electrodes1a.

Therefore, the devices that are better formed as WPPs10are those chips produced maintaining a high yield and obtained in a large number per a wafer and, particularly, are those small memory devices.

On the other hand, the devices that are not better in the form of WPPs10are those chips produced maintaining a low yield and obtained in a small number per a wafer and, particularly, are those large chips, end devices or devices produced in small quantity. Further, when an ASIC (application specific integrated circuit) having many external terminals compared to the chip area, is obtained in the form of the WPP10, a sufficiently large pitch is not often maintained among the bump electrodes11. In this case, too, the package should be in a conventional form for easy mounting.

Next, described below is a method of manufacturing the WPP10with reference to a process flow of WPP10(seeFIG. 1) shown inFIG. 6and sectional views of the wafer shown inFIG. 7corresponding to the principal steps in the process flow.

First, the wafer is subjected to a pre-treatment at step S1shown inFIG. 6. The bonding electrode1ais exposed on the main surface of the silicon board7shown inFIG. 7Athereby to form an inorganic insulating protection film7a.

Then, a WPP first insulating layer is formed at step S2. That is, as shown inFIG. 7B, the first insulating layer7bof polyimide or fluorine-contained resin is formed on the inorganic insulating protection film7aof the silicon board7.

Then, at step S3, a WPP rewiring layer is formed. That is, as shown inFIG. 7C, a rewiring12is formed on the first insulating layer7bbeing electrically connected to the bonding electrode1a.

Then, at step S4, a WPP second insulating layer is formed. That is, as shown inFIG. 7D, a second insulating layer7dcomprising polyimide or epoxy is formed on the rewiring12.

Then, at step S5, a WPP-UBM (underbump metal) is formed. That is, as shown inFIG. 7E, a diffusion-preventing adhesion layer7cwhich is a UBM is formed being electrically connected to the rewiring12.

Then, at step S6, the wafer is inspected (W-test). This is to inspect whether the wafer has been treated as contemplated relying on the electric characteristics by bringing a probe needle into contact with the electrode pad formed on a scribe area of the semiconductor wafer (silicon board7).

Then, at step S7, the silicon board7is inspected by using the probe (P-test1). This is to detect defective portions by inspecting whether the semiconductor chip1electrically works properly by bringing the probe needle into contact with the bonding electrode1aof the silicon board7.

Then, at step S8, the defective portions are relieved; i.e., laser blown fuses is executed. This is to relieve defective portions by cutting the fuse in a redundancy circuit by laser beam.

Then, at step S9, test is effected by using probe (P-test2). This is to make sure whether the defective portion relieved by the P-test1has been corrected.

Then, at step S10, marking is effected on the back surface of the wafer to attach a predetermined mark to the back surface of the silicon board7.

Then, a bump is formed at step S11. That is, as shown inFIG. 7F, a bump electrode11(protruded terminal) which is an external terminal of the WPP10is formed on the diffusion-preventing adhesion layer7cwhich is the UBM provided at an end drawn out from the bonding electrode1aon the rewiring12.

Here, the bump electrode11is formed by, for example, a printing method. A metal mask corresponding to the bump-forming position is disposed on the wafer (silicon board7), a solder paste is applied, the metal mask is removed, followed by reflowing at one time to form the bump electrodes11at one time on the wafer.

Then, at step S12, the semiconductor wafer, i.e., the silicon board7is cut by dicing, thereby to form the WPP10as shown inFIG. 4.

Then, at step S13, the WPP10is subjected to the aging, i.e., to the burn-in (BI) testing.

At step S14, the single products are sorted out to select non-defective WPPs10.

Thus, the fabrication of the WPP10is completed.

In the procedure of production shown inFIG. 6, no back grinding step (hereinafter abbreviated as BG) for grinding the back surface of the silicon board7was executed after the test by using the probe (P-test2) at step S9. However, the BG step may be executed after step S9of test by using the probe (P-test2) but before step S10of marking the back surface of the wafer.

Here, the BG step is to decrease the height of the WPP10by decreasing the thickness of the silicon board7by grinding the back surface of the silicon board7.

In other words, this is to decrease the thickness of the semiconductor chip1in order to decrease the thickness of the WPP10.

Upon executing the BG step, it is allowed to decrease the height of mounting the WPP10(e.g., to decrease to 1 mm or less).

Through the BG step, further, the thickness of the silicon board7can be decreased. Even when the scribing width on the silicon board7is decreased at the time of dicing to obtain an increased number of the chips, the dicing is effected without hindering the infiltration of the cooling water at the time of dicing into the scribe grooves.

This prevents damage to the silicon board7at the time of dicing, and enhances the yield of the silicon boards7. This is particularly effective at the time of dicing the silicon board7having a diameter of 300 mm.

Further, steps S6to S9(test of wafer (W-test), test using probe (P-test1), relief by laser, test using probe (P-test2)) in the procedure of production shown inFIG. 6may be executed between step S1of putting the wafer to the pre-treatment and step S2of forming the WPP first insulating layer.

That is, steps S6to S9are executed after the step S1of putting the wafer to the pre-treatment.

This makes it possible to execute a series of tests using the probe prior to forming the insulating film on the silicon board7and to assemble the WPP10without leaving damage even in case the bonding electrode1ais damaged.

Next, described below with reference toFIGS. 8 and 9is a method of manufacturing the memory-module100shown inFIG. 1of the embodiment 1.

The memory-module100shown inFIG. 1is obtained by mounting the WPPs10on both the front and back surfaces of the module board2and mounting the TSOPs20on one surface thereof.

First, the WPPs10are produced in compliance with the process flow shown inFIG. 6.

That is, the WPPs10(protruded terminal semiconductor devices) of the chip size shown inFIG. 4are prepared through the pre-treatment of the wafer (prepared in a number of 18×2=36), the WPPs10having bump electrodes11(protruded terminals) serving as external terminals, and rewirings12(wiring portions) in the areas of the semiconductor chips1for expanding the pitch among the bump electrodes11to be wider than the pitch among the bonding electrodes1a.

In the embodiment 1, the semiconductor chip1possessed by the WPP10is a DRAM.

In addition to the WPPs10, there are assembled the lead terminal semiconductor devices which are SMD parts to be mounted on the module board2.

There are prepared two TSOPs20(one being a PLL6and the other being a register8) which are lead terminal semiconductor devices having outer leads21that are external terminals electrically connected to the bonding electrodes1aof the semiconductor chips1, an EEPROM5(lead terminal semiconductor device), and small surface-attached resistors4of a number of 36×2=72.

The mounting procedure will be roughly described in compliance with the basic flow for mounting the parts shown inFIG. 8.

At step S15, first, the solder is printed on the module board2to form terminals (land pads) for electric connection to the ends of the outer leads21of the lead terminal semiconductor devices and to the bump electrodes11of the WPPs10.

Thereafter, SMDs are mounted at step S16and WPPs10are mounted at step S17.

Then, at step S18, reflowing is effected at one time in order to electrically connect the outer leads21of the lead terminal semiconductor devices to the land pads, and the bump electrodes11of the WPPs10to the land pads.

Then, washing is effected at step S19. The washing, however, may not be effected.

Further, at step S20, a resin is underfilled to effect the sealing.

Next, the method of manufacturing the memory-module100will be described in detail by using the mounting flow closely illustrated inFIG. 9.

At step S21shown inFIG. 9, first, the solder is printed on predetermined portions on the module board2.

Then, at step S22, the parts are mounted on the surfaces of the module. Here, predetermined numbers of WPPs10(of a number of 18), TSOPs20(of a number of 2), small surface-attached resistors4(of a number of 36) and EEPROM5(of a number of 1) are arranged on the front surface of the module board2using a mounting machine.

Then, at step S23, all of the above-mentioned parts on the front surface of the module board2are mounted by the batchwise (simultaneous) solder reflowing.

Then, at step S24, the parts are mounted on the back surface of the module. Here, the parts are arranged on the back surface of the module board2by using the mounting machine in the same manner as on the front surface.

Then, at step S25, all of the above-mentioned parts on the back surface of the module board2are mounted by the batchwise (simultaneous) solder reflowing.

Thus, the memory-module100is fabricated mounting (in a mixed manner) predetermined numbers of WPPs10(of a number of 18×2), TSOPs20(of a number of 2), small surface-attached resistors4and EEPROM5on both the front and back surfaces of the module board2.

Then, washing is effected at step S26.

Washing, however, may not be effected.

Then, at step S27, the module is tested. That is, the memory-module100is inspected in a predetermined manner to detect defective chips.

Then, at step S28, the defective chips are repaired and are exchanged. In this case, the solder is melted by being heated again, the defective chip (defective semiconductor device) is removed and is replaced by a non-defective chip (non-defective semiconductor device).

Then, at step S29, all parts are mounted by effecting the reflowing again.

Thereafter, washing is effected at step S30.

Washing, however, may not be effected.

Then, at step S31, the WPPs10are sealed by being underfilled with the resin. The underfilling is that when the WPP10has a relatively large chip size like DRAM and fails to exhibit a sufficient function for buffering stress to the bump electrodes11, the resin9is applied between the package body13of the WPP10and the module body2to decrease the stress exerted on the bump electrodes11.

That is, the underfilling is a sealing with resin between the package body13of the WPP10and the module board2, in order to solidify and protect the surrounding of the bump electrode11with the resin9.

To effect the underfilling, the liquid resin9is applied onto the module board2one surface by one surface from a nozzle60aof a dispenser60shown inFIG. 10. That is, the resin9is applied onto the WPPs10on the front and back surfaces of the module board2one surface by one surface.

After the application has been finished on both surfaces, the front and back surfaces of the module board2are heated at one time to simultaneously cure the resin9on the front and back surfaces. That is, after the application of the resin9on both surfaces has been finished, the two surfaces are simultaneously cured (hardened) by baking by heating the atmosphere or by the like means.

Then, at step S32as shown inFIG. 9, casing is effected, and the module is finally tested at step S33.

Predetermined data are written into the EEPROM5by using a special writer.

Here, mounting the bare chip that requires the same area as when the WPP10is mounted will be described for the purpose of comparing the two.

First, in mounting the bare chip, the bonding electrodes1aare mounted on the mounting board without being rearranged by rewirings12. Therefore, the pitch is narrow among the external terminals, the wiring rule becomes strict on the mounting board, and the cost of the mounting board is driven up. In assembling the module, further, it becomes necessary to add a mounting step by using a flip chip bonder of a relatively slow processing speed in addition to the step of mounting the SMD parts by reflowing the solder.

Accordingly, the WPPs10on the memory-module100of the embodiment 1 exhibit much effect in their mounting (decreases the number of the mounting steps since no special mounting device such as flip-chip bonder is used) than mounting the bare chips.

Next, described below is the underfilling method in the method of manufacturing the memory-module100of the embodiment 1.

FIG. 10is a view illustrating a method of applying the resin for underfilling the WPPs10mounted on the memory-module100ofFIG. 1, andFIG. 11is a view illustrating the permeation of the resin9that is applied by the method of application shown inFIG. 10.

InFIG. 10, arrows indicate the direction in which the nozzle60atravels. The dispenser60and the nozzle60amove on the short sides of the WPPs10along the arrows.

According to the method of applying the resin of the embodiment 1, the dispenser60is moved intermittently and nearly linearly along the direction of short sides of the WPPs10having a rectangular shape on a plane, and the resin9is successively dripped on the short sides of the WPPs10from the upper side of the WPPs10through the nozzle60a.That is, when the application on one WPP10has finished, the nozzle60ais moved to an end on the front side of the short side of a next WPP10, and the nozzle60ais once stopped at this position.

Thereafter, the resin9is dripped while moving the nozzle60afrom the end of the front side of the short side of the WPP10toward the end of the rear side thereof and, at this position, motion of the nozzle60aand dripping of the resin9are once halted.

Then, in a state where the resin9is no longer dripped, the nozzle60ais moved to an end on the front side of the short side of the neighboring WPP10, and the resin9is similarly dripped and, thus, the WPPs10are successively underfilled.

FIG. 11illustrates the spreading of wet resin9that is applied by the method shown inFIG. 10to the WPPs10of DRAMs in which the bump electrodes11are arranged in 15 rows×4 columns, whereinFIGS. 11A and 11Billustrate a state right after the resin is applied onto the short side,FIGS. 11C and 11Dillustrate a state when a predetermined period of time (short time) has passed after the application,FIGS. 11E and 11Fillustrate a state when a predetermined period of time (long time) has passed after the application, andFIGS. 11G and 11Hillustrate a state where the resin9is applied by moving the nozzle60aone turn to form a fillet9aalong the periphery after the predetermined period of time (long time) has passed after the application.

Referring toFIGS. 11E and 11F, it is also allowable to move again the dispenser60and the nozzle60aabout the package body13of the WPP10after the wet resin9has spread throughout between the WPP10and the module board2to reliably form the fillet9ashown inFIG. 11G, so that the WPP10is secured to the module board2more strongly.

FIG. 12illustrates the structure of a memory-module200which is modified from the memory-module100of the embodiment 1 of the invention.

The memory-module200includes 18 WPPs10(protruded terminal semiconductor devices) that are mounted being arranged in a sequence maintaining an equal pitch on one surface of the module board2, and one TSOP20(lead terminal semiconductor device) mounted near the WPPs10, the TSOP20(lead terminal semiconductor device) being arranged near the center of the WPPs10that are arranged in a sequence.

That is, a plurality of (10 and 8) WPPs10are arranged in a sequence on both sides of one TSOP20.

Further, nine SOPs (small outline packages)61(registers8) which are the lead terminal semiconductor devices are mounted on the module board2on the side of the connection terminals2awhich are the external terminals, and 18 WPPs10are mounted on the side opposite to the connection terminals2a(on the side remote from the connection terminals2a), the individual WPPs10being underfilled.

In the memory-module200of this type of mounting, the resin9for underfilling the WPPs10is applied nearly linearly onto the short sides of 18 WPPs10arranged in a sequence.

This makes it possible to efficiently apply the resin9.

FIG. 13illustrates the structure of a memory-module300which is modified from the memory-module100of the embodiment 1 of the invention.

In the memory-module300shown inFIG. 13, 18 WPPs10are mounted on the module board2in the form of groups (masses) each consisting of two or four in a two rows×two columns matrix arrangement.

Further, the individual WPPs10are mounted with their lengthwise direction in parallel with the direction of the short sides of the module board2of the memory-module300.

Described here is a method of efficiently applying the resin9for underfilling the WPPs10in a state where the WPPs10are mounted.

When the temperature for applying the resin9is low, the resin9is applied to the package body13of the WPP10on the side of the long side, since the resin9may be infiltrated into between the package body13and the module board2over a short distance. This makes it possible to shorten the time for application.

It is therefore desired to maintain space for moving the nozzle60aalong the long sides of at least one side of the package bodies13, and to arrange the long sides thereof of the side where no nozzle60amoves as close to other parts as possible from the standpoint of highly densely mounting the parts.

When the semiconductor chip1has many bits and many DRAMs are connected to the same I/Os of the memory-module300, a great advantage is obtained by applying the resin onto the DRAMs which are arranged as close as possible to each other in a 2×2 arrangement on the same plane.

With the WPPs10being arranged as shown inFIG. 13, therefore, it is desired to apply the resin9to the outer peripheries of the long sides of the outer side along the outer long sides of the WPPs10. When the resin9is applied along the outer long sides of 2×2 DRAMs (WPPs10) according to this method of application, the resin9does not flow onto the package bodies13to which the resin is not to be applied on the side opposite to the package bodies13to which the resin is to be applied. Or, the resin9does not leak or spread, either.

In the memory-module300, it is desired that the WPPs10having I/O of (×4) constitution are collected in a number of four to obtain a 16-bit constitution, and are mounted as a group. In mounting the WPPs10as shown inFIG. 13, therefore, it is desired to apply the resin9along the locus as indicated by arrows.

FIG. 14is a diagram illustrating the permeation of the resin9when it is applied according to a modified embodiment.

That is, in mounting the WPPs10on a memory-module400as shown inFIG. 15, the underfiller resin9is applied to the outer peripheries along the two opposing sides of the package bodies13as shown inFIG. 14. Here, the resin9is applied to both short sides of the WPPs10from the ends on one side to the ends on the opposite side.

Arrows shown inFIGS. 14A and 14Bindicate the loci of motion of the dispenser60.FIGS. 14C and 14Dillustrate a state right after the application on both short sides (two sides),FIGS. 14E and 14Fillustrate a state when a predetermined period of time (intermediate time) has passed after the application, andFIGS. 14G and 14Hillustrate a state of infiltration of the resin9of when a predetermined period of time (long time) has passed after the application.

In the embodiment 1, the resin9permeated starting from both short sides is still in a separated state leaving an intermediate region where no resin9exists even in the final stage of infiltration of the resin9. The difference in the thermal expansion between the package body13and the module board2, and stress acting on the bump electrodes11due to the warping of the module board2, increase with an increase in the distance from the center of the package body13and become a maximum at the bump electrodes11at the corners. Therefore, if the resin9is permeating near both short sides of the package body13of a rectangular shape, the stress acting on the bump electrodes11can be decreased to some extent even if there exists an intermediate region where the resin9is not existing.

Thus, the effect close to that of when the resin is applied to the whole surface of the package body13is obtained requiring a decreased amount of the resin9and a shortened operation time.

In other words, it is made possible to shorten the time for application and to decrease the amount of application.

Further, the resin9may simply be applied to the four corners of the package body13. In this case, a decreased stress acts on the bump electrodes11arranged along the outermost circumference and, hence, the bump electrodes11feature extended life for connection.

FIGS. 15A and 15Billustrate the structure of a memory-module400modified from the memory-module100, and in which 16 WPPs10are mounted in a sequence maintaining an equal pitch on one surface of the module board2. In this memory-module400, the underfiller resin9is linearly applied to 16 WPPs10arranged in a sequence. Arrows shown inFIG. 15Aindicate the locus of motion of the dispenser60(seeFIG. 10).

FIG. 16illustrates a state where the memory-module400shown inFIG. 15is deflected. This happens when the ends of the module board2are held at the time of inserting the socket for inspecting the memory-module400.

That is, as shown inFIG. 16, when the memory-module400shown inFIG. 15is deflected in the lengthwise direction thereof, the stress is nearly uniformly dispersed over the whole memory-module400since the memory-module400as a whole is deflected unless the sealing portions14of the neighboring WPPs10are integrally fabricated without coming into contact with each other.

This structure withstands the load from the outer side and, hence, improves the reliability of the memory-module400.

In a memory-module500shown inFIGS. 17 and 18, the WPPs10of a number of16are mounted being divided into four regions each including four of them along the direction in which the plurality of connection terminals2aare arranged on the module board2, the sealing portion14continuing over the four WPPs10in each region.

That is, the WPPs10are mounted being divided into groups (masses), and are sealed by being underfilled as designated at the sealing portion14in a continuing manner with the group as a unit. Therefore, the portions of the groups (masses) of the memory-module500exhibit increased rigidity apparently including the WPPs10.

Therefore, the bending stress of the module board2concentrates at the gaps among the groups of WPPs10.

That is, the neighboring sealing portions14may often become continuous due to some factors affecting the application of the underfiller resin9, such as gaps among the WPPs10. Even in such a case, the memory-module500that includes the non-mounting portions2bthat are not partly continuous as shown inFIGS. 17 and 18, deflects at the non-mounting portions2bwhen an external force is exerted, preventing the stress from being applied to the connection portions of bump electrodes11of the WPPs10or to the semiconductor chips1.

Since the stress is dispersed, the WPPs10on the memory-module500feature improved reliability in the connection.

In the memory-modules100,200,300,400and500of the embodiment 1, the WPPs10are sealed by underfilling, and the whole surfaces of the chips or the major portions are secured more strongly. As a result, shock resistance is improved and moisture resistance is improved, too.

In the module product, a TCP (tape carrier package) may be laminated as another means for highly densely mounting the parts. According to this technology, however, the chips are often cracked as their thickness is decreased. In the memory-modules100,200,300,400and500according to the embodiment 1, on the other hand, shock resistance is improved by securing the chips relying on the underfilling, preventing the chips from being cracked.

Further, the WPPs10are sealed by underfilling and are mounted on the module board2with the main surfaces of the semiconductor chips1and the surfaces (back surfaces) of the opposite side being exposed. Moreover, the whole main surfaces or the main portions of the semiconductor chips1are secured to the module board2by being underfill-sealed, making it possible to decrease the heat resistance.

This helps improve the heat-radiating performance of the memory-modules100,200,300,400and500and lengthen the life.

FIG. 19is a plan view illustrating the structure of the memory-module according to an embodiment 2 of the present invention.

The memory-module600of the embodiment 2 includes 72 WPPs10(protruded terminal semiconductor devices) which are DRAMs mounted in a matrix arrangement. Connection of input/output signals to the WPPs10is accomplished in a manner that a group (mass) includes a total of 9 WPPs10consisting of one for ECC and eight of two rows (in the memory-module600ofFIG. 19, the direction in parallel with the short sides of the module board2is referred to as row and the direction at right angles therewith is referred to as column, which, however, may be reversed to the above), and nine FET (field-effect transistor)—bus switches15(lead terminal semiconductor devices) which are memory selection means are mounted for the WPPs10of each of the groups to switch each of the groups.

That is, in the memory-module600, the connection of input/output signals to nine WPPs10of two rows is switched within the group (8 WPPs) by a corresponding FET-bus switch15, making it possible to increase the number of the WPPs10without increasing the number of the connection terminals2aof the module board2.

Therefore, the memory-module600mounts the WPPs10of a number four times as great as that of the memory-module100of the embodiment 1.

That is, the memory-module600separately switches the I/Os using the FET-bus switches15, so that an increased number of DRAMs can be mounted.

In appearance, the FET-bus switches15of the memory-module600are, for example, those of the SOP type, which are lead terminal semiconductor devices.

The structure of the memory-module600of the embodiment 2 in other respects and the method of manufacturing the memory-module600are the same as those of the memory-module100of the embodiment 1, and are not described here again.

FIG. 20is a view illustrating the structure of a memory-module according to an embodiment 3 of the present invention, whereinFIG. 20Ais a plan view andFIG. 20Bis a side view,FIG. 21is a diagram of block circuits of the memory-module shown inFIG. 20,FIG. 22is a bottom view illustrating the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown inFIG. 20,FIG. 23is a diagram of wirings on the side of the board illustrating an example of wirings on the module board at a portion C in the memory-module shown inFIG. 20A,FIGS. 24,25and26are diagrams of wirings illustrating modified examples of the bump arrangement on the wafer process package in the memory-module according to the embodiment 3 of the invention and modified examples of the wirings on the side of the board corresponding thereto, andFIG. 27is a diagram of bump arrangement and wirings illustrating a further modified example of the bump arrangement on the wafer process package and of the wirings on the side of the board shown inFIG. 25.

The memory-module700of the embodiment 3 shown inFIGS. 20A and 20Bis an unbuffered SDRAM (static DRAM)—DIMM (dual in-line memory-module) of 8 bytes having 168 pins, and includes 8 WPPs10(protruded terminal semiconductor devices), small surface-attached resistors4, capacitors3and an EEPROM5that are mounted in a mixed manner on one surface thereof.

The memory-module700, however, does not mount the registers8that are mounted on the memory-module100ofFIG. 1.

FIG. 21is a diagram of block circuits of the memory-module700shown inFIG. 20, constituting two banks.

Symbols attached to the terminals shown inFIG. 21are the same as those described with reference to the block circuit diagram of the memory-module100of the embodiment 1, and are not described here again.

In the memory-module700shown inFIG. 21, whether the S0system of the bank1or the S1system of the bank2be read out, is directly determined by a signal since no register8has been mounted. That is, since the memory-module is of the unbuffered type, a signal directly enters either bank to select a semiconductor chip1of either bank.

The chips D0to D15represent WPPs10of a number of 16 on both surfaces, and [I/O0to I/O3] terminals of each chip are connected as independent terminals to the connection terminals2aof the module board2.

The DRAMs as a whole have I/Os of 64 bits from DQ0to DQ63that are used as data, constituting two banks.

The module board2of the memory-module700has a size of, for example, P=133.35 mm and Q=33.02 mm, and the mounting height (max) is R=4 mm as shown inFIG. 20B.

Referring toFIG. 20A, the memory-module700includes 8 WPPs10(protruded terminal semiconductor devices) which are DRAMs arranged in a sequence on one surface thereof, as well as capacitors3at portions among the neighboring WPPs10or by the WPPs10nearly at the centers in the lengthwise direction.

This is to minimize the wiring length between the WPPs10and the capacitors3.

Here,FIG. 22illustrates the structure of the WPP10used for the memory-module700.

In the semiconductor chip1of WPP10shown inFIG. 22, a free space1bwithout bump electrode11is formed near the center in the lengthwise direction thereof.

This is done by partly changing the pitch among the bump electrodes11by rewirings12so as to form the free space1b,i.e., to form the free space1bwithout bump electrode11near the center of the WPP10in the lengthwise direction thereof.

FIG. 23illustrates the wirings on the side of the module board2at the portion C inFIG. 20A.

Referring toFIGS. 22 and 23, the capacitor3(lead terminal semiconductor device) is mounted neighboring the free space1bof the semiconductor chip1, and power source wirings2cof the capacitor3are formed as surface-layer wirings2hon the surface layer opposing the free space1bof the semiconductor chip1on the module board2(they, however, may be formed as inner-layer wirings2gin the inner layer).

That is, as shown inFIG. 22, the free space1bwithout bump electrode11is formed near the center of the semiconductor chip1in the lengthwise direction thereof. Therefore, the connection can be accomplished without drawing the signal lines of the WPP10to the portions corresponding to the center of the chip on the module board2and, hence, the capacitor3can be mounted at a portion closest to the WPP10.

Accordingly, the wirings become the shortest between the WPPs10and the capacitors3to improve the operation characteristics.

Referring toFIG. 23, the module board2is formed by a total of six metal layers including two core layers Vcc, a GND layer, and two signal line layers on each surface. Common wirings2eof the address/functional system connect the lands2don the surface layer to which the bump electrodes11of the WPP10are connected, to the layer which is just thereunder through via-holes2f,and are connected to the inner-layer wirings2gthat extend in the lengthwise direction of the module board2.

The I/O wirings are connected to the connection terminals2adisposed nearby through the surface-layer wirings2hof the module board2. This suppresses an increase in the inductance that results when the via-holes2fare passed through.

In the wirings shown inFIG. 23, the Vss (GND) and Vdd are extending sideways from the capacitor3, which, however, may be readily connected to the core layers through via-holes2f.

FIGS. 24,25and26are diagrams illustrating modified examples of the bump arrangement of the WPP10in the memory-module700of the embodiment 3 and modified examples of the wirings on the side of the board corresponding thereto, andFIG. 27illustrates a further modified example of the bump arrangement of the wafer process package shown inFIG. 25and of the wirings on the side of the board.

In the WPPs10inFIGS. 24,25,26and27, there are separately provided a group of common bump electrodes (group of common protruded terminals)1cwhich is a group of common electrodes such as of addresses, functions, power source and GND that can be connected in common among the WPPs10, and a group of independent bump electrodes (group of independent protruded terminals)1dthat is a group of independent electrodes such as of I/Os independently connected for each of the WPPs10.

In the WPP10, further, the group of independent bump electrodes1dis arranged at an end on one side which is the short side of the package body13. On one surface of the memory-module700, eight WPPs10are mounted with their groups of independent bump electrodes1dbeing directed to the side of the connection terminals2aof the module board2.

On the module board2are therefore formed surface-layer wirings2hwhich are common wirings2efor connecting the groups of common bump electrodes1cof eight WPPs10.

Here, the pitch is broadened among the group of common bump electrodes1c,i.e., among the bump electrodes11of the address system and functional system. In particular, the pitch is expanded in the lengthwise direction of the chip so that many wirings can be formed in the direction at right angles with the lengthwise direction of the package body13passing among the bump electrodes.

Further, the pitch is decreased among the group of independent bump electrodes1d,i.e., among the bump electrodes11of the I/O system, and the bump electrodes are arranged in the outer periphery on one side of the package body13.

This makes it possible to form common wirings2erelying on the surface-layer wirings2honly and, hence, to decrease the number of the wiring layers in the module board2.

In the WPPs10shown inFIG. 24, the groups of common bump electrodes1care regularly arranged by rewirings12being inclined with respect to the package bodies13.

This makes it possible to form the plurality of common wirings2ein parallel in the lengthwise direction of the package bodies13to connect common electrodes such as of addresses, functions, power source and GND.

As a result, the wiring density of the module board2can be maximized and the lengths of the common wirings2ecan be minimized.

When the number of the bump electrodes11of the WPP10is relatively small compared to its chip size or when the module board2involves fine wiring rules like an additive board, the GND and Vcc layers of the surface layer and of the inner layer are partly used as signal layers to produce the module board2of four layers and, hence, to assemble the memory-module700by using this module board2.

In this case, the independent wirings2iof the I/O system are connected from the bump electrodes11provided on the side of the connection terminals2a,and the plurality of common wirings2econnecting the common electrodes such as of addresses, functions, power source and GND are so formed as to pass among the chips.

In the WPPs10as shown inFIG. 25, further, the groups of common bump electrodes1care arranged like a grid using rewirings12(seeFIG. 22). In this case, as shown inFIG. 22, the rewirings12are used for distributing the power source and GND wirings in the chip, and one bump electrode11is electrically connected to a plurality of bonding electrodes1athrough the rewirings12to decrease the number of the bump electrodes11(to decrease the number of the external terminals).

In the wirings on the side of the board shown inFIG. 25, the connection is made using the surface layer only of the module board2, and the bump electrodes11are arranged without being inclined. Therefore, the wirings are accomplished by utilizing the bending and inclination of the wirings on the side of the board.

In the WPPs10shown inFIG. 26, the pitch among the bump electrodes11is slightly expanded to be larger than that of the bump arrangement of the WPPs10shown inFIG. 25, and the bump electrodes are arranged on the module board2being inclined in the lengthwise direction or in the direction of the short side.

Therefore, the common wirings2eon the side of the module board2are inclined relative to the lengthwise direction of the package bodies13. As a result, the common wirings2eare formed straight like the common wirings2eshown inFIG. 24.

FIG. 27illustrates a further modified example in which the pitch among the bump electrodes11is slightly expanded to be larger than that of the bump arrangement of the WPPs10shown inFIG. 25. In this modified example, independent pins other than those of the I/O system are drawn out from the lower side. This is an example in which the bits are specially constituted to decrease the number of pins to thereby increase the gap among the common wirings2e,the I/O pins and other independent pins having a narrow pitch (d1>d2inFIG. 27).

The modified example shown inFIG. 27exhibits such an effect that an increased number of wirings can be drawn among the pins since the gap is broadened among the common wirings. Therefore, the wirings on the module board2can be used in common using the surface-layer wirings2honly, without using the inner-layer wirings2g(seeFIG. 23) of the module board2. The I/O pins and independent pins such as of the power source have a narrow pitch. These pins may have a narrow pitch since the wirings are drawn downward, i.e., drawn to the connection terminals2awithout passing among the pins.

InFIG. 27, three surface-layer wirings2hrun between the pins when the wiring layout D is employed, and four surface-layer wirings2hrun between the pins when the wiring layout E is employed.

InFIGS. 24,25,26and27, the mounting lands are not particularly indicated on the module board2and the slit-like openings in the resist at right angles with the common wirings2eare regarded to be false lands for connection by soldering, in order to increase the wiring density on the module board2up to its limit.

The structure of the memory-module700of the embodiment 3 in other respects and the method of manufacturing the memory-module700are the same as those of the memory-module100of the embodiment 1, and are not described here again.

In the foregoing was concretely described the invention accomplished by the present inventors by way of embodiments. However, the present invention is in no way limited to the above-mentioned embodiments only but can be modified in a variety of ways without departing from the spirit and scope of the invention.

In the memory-modules100to700of the above-mentioned embodiments 1, 2 and 3, for example, the EEPROM5was the lead terminal semiconductor device having outer leads21. However, the EEPROM5which is a nonvolatile read-only memory may be formed in the same structure as the protruded terminal semiconductor device, i.e., as the WPP10, and may be mounted.

In this case, however, the EEPROM5of the WPP structure is not sealed by underfilling but the WPPs10which are the DRAMs only are underfilled.

That is, the EEPROM5of the WPP structure is detachably mounted on the module board2.

This is because the EEPROM5is produced maintaining a low yield and when it is detected to be defective upon electrically writing data therein, the EEPROM5is better replaced by a non-defective one. The EEPROM5has a small chip size compared to the DRAM, causes small stress to exert on the bump electrodes11, and maintains reliability to a sufficient degree even without being underfilled. Upon mounting the EEPROM5of the WPP structure, the mounting area can be decreased compared to when the SOP type device is mounted and the cost can be decreased to be lower than that of the SOP type device.

The above-mentioned embodiments 1, 2 and 3 have dealt with the memory-modules of the type mounting the WPPs10on both the front and back surfaces of the module board2. However, the memory-module may be the one of the type mounting the WPPs10on one surface only.

The lead terminal semiconductor device mounted together with the WPPs10(protruded terminal semiconductor devices) is not limited to TSOP20but may be such a semiconductor device as QFP (quad flat package) or TCP (tape carrier package) in addition to TSOP20.

The above-mentioned embodiments 1, 2 and 3 have dealt with the case where the protruded terminal semiconductor devices are the WPPs10. However, the protruded terminal semiconductor devices may be any other semiconductor devices provided their external terminals are bump electrodes11and are equipped with wiring portions for expanding the pitch among the bonding electrodes1aof the semiconductor chips1to be wider than the pitch among the bump electrodes11.

FIGS. 28,29and30illustrate modified examples of the protruded terminal semiconductor device other than the WPP10.

FIGS. 28A,28B and28C illustrate a CSP (chip scale package)30as a modified example of the protruded terminal semiconductor device.

The CSP30has a chip size nearly equal to, or slightly larger than, the semiconductor chip1, and is of the fan in structure that supports the semiconductor chip1by a tape board32by interposing an elastomer31.

Further, a plurality of bump electrodes34(protruded terminals) of solder or the like are formed as external terminals within an area of the semiconductor chip1, the connection leads32aprovided on the tape board32are electrically connected to the bonding electrodes1aof the semiconductor chip1, and terminal pitch-expanding wirings32bare formed on the tape board32to expand the pitch among the bump electrodes34to be wider than the pitch among the bonding electrodes1aof the semiconductor chip1.

A sealing portion33is formed on the bonding electrodes1aof the semiconductor chip1.

FIGS. 29A and 29Billustrate a BGA (ball grid array)40of the chip face-up mounting system as a modified example of the protruded terminal semiconductor device.

The BGA40is the one in which the semiconductor chip1is secured to a BGA board42in a face-up manner through a die-bonding material45, and the bonding electrodes1aof the semiconductor chip1are electrically connected to the board electrodes42fof the BGA board42through bonding wires41of gold or the like material.

Further, a plurality of bump electrodes44(protruded terminals) of solder or the like material are arranged as external terminals like a grid on the back surface of the BGA board42, and terminal pitch-expanding wirings42aare formed on the BGA board42to expand the pitch among the bump electrodes44to be wider than the pitch among the bonding electrodes1aof the semiconductor chip1.

Further, a molded portion43is formed for sealing the semiconductor chip1and the bonding wires41with a resin.

FIGS. 30A,30B and30C illustrate a BGA (ball grid array)50of the chip face-down mounting system as a modified example of the protruded terminal semiconductor device.

The BGA50is of the flip-chip structure in which the semiconductor chip1is mounted on the BGA board52in a face-down manner via small bumps51, and the bonding electrodes1aof the semiconductor chip1are electrically connected to the electrodes of the BGA board52through the small bumps51.

Further, the bump electrodes54(protruded terminals) of solder or the like material are arranged as external terminals like a grid on the back surface of the BGA board52, and terminal pitch-expanding wirings52a(seeFIG. 30C) are formed on the BGA board52to expand the pitch among the bump electrodes54to be wider than the pitch among the bonding electrodes1a(seeFIG. 29) of the semiconductor chip1.

A gap between the semiconductor chip1and the BGA board52, i.e., the periphery of the small bumps51, is underfilled with a resin to form a sealed portion53.

In the CSP30shown inFIG. 28, BGA40shown inFIG. 29and BGA50shown inFIG. 30, too, the terminal pitch-expanding wirings32b,42aand52aare provided, respectively, to expand the pitch among the bump electrodes34,44,54to be wider than the pitch among the bonding electrodes1aof the semiconductor chip1, which, therefore, can be mounted by reflowing on the module board2or the like.

Briefly described below are the advantages obtained by the representative examples of the inventions disclosed in this application.(1) Upon mounting the protruded terminal semiconductor devices on the module board of the memory-module, it becomes possible to greatly decrease the mounting areas compared to mounting the lead terminal semiconductor devices having semiconductor chips that are individually treated. This makes it possible to effect the mounting requiring the least areas so far as the semiconductor chips are mounted and, hence, to greatly increase the module capacity.(2) The WPPs are mounted as the protruded terminal semiconductor devices while expanding the pitch among the bump electrodes which are the external terminals to be wider than the pitch among those of the flip chips, making it possible to expand the wiring rules on the module board and, hence, to realize a highly densely mounted memory-module suppressing the cost.(3) The bonding electrodes of the semiconductor chip can be connected to the bump electrodes which are the external terminals of the WPPs through wirings of lengths shorter than those of the SMD parts such as TSOPs. This enables the memory-module to cope with high-speed operations and, hence, to cope with high-speed buses.(4) Since the WPPs in the memory-module are sealed by underfilling, the whole chip surfaces are strongly secured to exhibit improved shock resistance. Therefore, the chips are prevented from being cracked.(5) The WPPs are sealed by underfilling and are mounted on the module board in a state where the back surfaces of the semiconductor chips are exposed and, besides, the whole main surfaces of the semiconductor chips are secured to the module board by underfill-sealing, enabling the heat resistance of the memory-module to be decreased. As a result, the memory-module exhibits improved heat-radiating performance and extended life.