Memory management system with backup system and method of operation thereof

An memory management system with backup system, and a method of operation of a memory management system with backup system thereof, including: a memory module controller for detecting a power failure condition, the memory module controller including a nonvolatile memory controller; a compression controller integrated within the nonvolatile memory controller for receiving a data block from volatile memory; a compression engine within the compression controller for compressing the data block to form a compressed data block; and a sequencer for writing the compressed data block to nonvolatile memory.

TECHNICAL FIELD

The present invention relates generally to a memory management system, and more particularly to a system for backing up data.

BACKGROUND ART

There is a continual need in the area of electronics and electronic computing systems toward smaller systems and/or systems with greater computing performance for a given space and within a given power profile. Within these systems, the integrated circuit and memory modules are the building block used in high performance electronic systems to provide applications for usage in products such as automotive vehicles, computers, cell phone, intelligent portable military devices, aeronautical spacecraft payloads, and a vast line of other similar products that require small compact electronics supporting many complex functions.

Products must compete in world markets and attract many consumers or buyers in order to be successful. It is very important for products to continue to improve in features, performance, and reliability while reducing product costs, product size, and to be available quickly for purchase by the consumers or buyers. Manufacturing improvements may increase reliability of a product itself, but there are situations out of the manufacturer's control which also may impact the user experience, such as extreme temperatures and pressures, simple user error, and unreliable power supply.

Thus, a need still remains for a system to reliably and safely backup user data even when there is a loss of system power. In view of the growing importance of data and data structures, it is increasingly critical that answers be found to these problems in order to ensure that user data is not lost. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides a method of operation of a memory management system with backup system that includes detecting a power failure condition with a memory module controller, the memory module controller including a nonvolatile memory controller; receiving a data block from volatile memory at a compression controller integrated within the nonvolatile memory controller; compressing the data block to form a compressed data block; and writing the compressed data block to nonvolatile memory.

The present invention provides a memory management system with backup system that includes a memory module controller for detecting a power failure condition, the memory module controller including a nonvolatile memory controller; a compression controller integrated within the nonvolatile memory controller for receiving a data block from volatile memory; a compression engine within the compression controller for compressing the data block to form a compressed data block; and a sequencer for writing the compressed data block to nonvolatile memory.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now toFIG. 1, therein is shown a functional block diagram of a memory management system100with backup system in an embodiment of the present invention. The memory management system100can include a memory module102having both volatile memory104and nonvolatile memory106, for example. As another example, the memory management system100can include a memory module having DRAM and NAND flash memory as an example of the volatile memory104and the nonvolatile memory106, respectively. The memory module102can include a memory module controller108, a volatile memory controller109, and a nonvolatile memory controller110. The memory module102can also include a super capacitor112. The memory module102is ordinarily connected to some type of a power source114. The super capacitor112is shown as just one super capacitor, but it is understood that more than one super capacitor may be used depending on the power requirements of the nonvolatile memory106.

The memory module102and the power source114can be part of a larger host device (not shown for clarity). A host device volatile memory controller111can interface with the volatile memory104when the host device is operating normally and the power source114is properly connected and operating.

The nonvolatile memory106can function as part of the backup system of the memory management system100. The volatile memory104requires that the power source114be present. If there is a loss of connection between the power source114in the volatile memory104or any kind of power failure whatsoever, without any backup system, data within the volatile memory104would then be lost. However, in the memory management system100with the nonvolatile memory106as part of the backup system, data can be backed up from the volatile memory104to the nonvolatile memory106in the event of a power failure.

For example, the memory module controller108can remain in standby mode during normal operation of the memory module102. Normal operation of the memory module requires connection to the power source114, and in this mode the host device volatile memory controller111will perform normal operations reading and writing to the volatile memory104.

The memory module102and its various components are powered by either the power source114or the super capacitor112, but never both at the same time. Circuitry can be included to ensure this separation. In this example, a power source diode113and a super capacitor diode115can ensure that only one power source operates at one time. However, it is understood that these two diodes are used for example only, and any circuitry can be used so long as it allows the super capacitor112to be used upon loss of connection to the power source114. In the event of a power failure, the memory module controller108containing the nonvolatile memory controller110and the volatile memory controller109can assert control and use the power available from the super capacitor112to transfer data from the volatile memory104to the nonvolatile memory106.

As a more specific example, the memory module102can be a nonvolatile dual in-line memory module type N (NVDIMM-N), which includes both volatile and nonvolatile memory. For example, the volatile memory104can be some type of DDR SDRAM (Double Data Rate Synchronous Random Access Memory; for example: DDR3 SDRAM, DDR4 SDRAM, etc.), and the nonvolatile memory106can be NAND flash memory. In the event of a power failure, the memory module controller108can assert control of the DRAM (the volatile memory104in this example) and can backup the data in the DRAM to the flash memory (the nonvolatile memory106in this example) utilizing the power stored within the super capacitor112. The nonvolatile memory controller110and the volatile memory controller109can be integrated within the memory module controller108, for example.

Referring now toFIG. 2, therein is shown a detailed block diagram of the nonvolatile memory controller110ofFIG. 1. The nonvolatile memory controller110includes a DMA buffer220, a compression controller222, a page buffer224, an ECC controller226, and a sequencer228. Other components are included or omitted for clarity. The nonvolatile memory controller110is connected between the volatile memory104ofFIG. 1and the nonvolatile memory106, which could be DRAM and NAND flash memory, respectively, as an example. Only the nonvolatile memory controller110is shown in detail for clarity. Also for clarity, the DMA buffer220is shown connected to a DMA interface221and the sequencer228is connected to the nonvolatile memory106.

Upon detection of a power failure, a DMA transfer from the volatile memory104can be initiated. The nonvolatile memory controller110can utilize the compression controller222to compress data from the volatile memory104before backing up such data to the nonvolatile memory106. The compression controller222is integrated into the nonvolatile memory controller110, which in turn can be integrated into the memory module controller108ofFIG. 1.

It has been discovered that on data which has a high compression or compressibility ratio, integrating the compression controller222within the nonvolatile memory controller110can improve the speed of data transfer and can lower necessary backup power requirements. For example, although compressing data with the compression controller222can add some latency to a data transfer process, the latency is outweighed because in this example application, the access to memory is sequential and the delay at the beginning of data transfer is not considerable. In turn, an increase in data transfer speed can allow for faster backup time, which can improve the reliability of the memory module102. For example, for a given application with no compression controller integrated into the memory controller, four or more super capacitors may be required; however, with the compression controller222, the backup power requirements may decrease and perhaps fewer super capacitors may then be required. In this example, this would reduce the amount of physical space taken up by the super capacitors and would also lower the cost of the final package. Manufacturing may also be simplified.

It has also been discovered that integrating the compression controller222within the nonvolatile memory controller110can improve reliability. Due to the above discussed lower back up power requirements, fewer super capacitors may be required. Not only does this lower manufacturing complexity and material costs, it also decreases the chance that any given super capacitor may fail. As the number of super capacitors goes up, the likelihood that any one of them will fail and require replacement also increases. This improvement in reliability can greatly decrease maintenance or replacement costs.

Additionally, it has been discovered that integrating the compression controller222within the nonvolatile memory controller110can improve reliability of the nonvolatile memory106. As is understood within the art, nonvolatile or flash memory degrades in proportion to the amount of writes or reads which it is subjected to. Because data is compressed before being written to the nonvolatile memory106, less wear and tear is placed on the nonvolatile memory106and this leads directly to greater reliability for the nonvolatile memory106and a longer life.

A more detailed example of how the compression controller222is utilized follows. Once a power failure or loss of power is detected, a DMA transfer from the volatile memory104can be initiated. Data is first transferred from the volatile memory104to the DMA buffer220through the DMA interface221. In this example, the DMA buffer220can be 64 kB in size, but it is understood that other sizes are possible as technology improves. The compression controller222can include a compression engine230, a decompression engine232, a compression buffer234, and a decompression buffer236.

The compression controller222can read, for example, one kB of data from the DMA buffer220and temporarily store the data in the compression buffer234. The compression engine230can be utilized to compress this chunk or block of data within the compression buffer234. The compression controller222can then transfer the compressed data to the page buffer224until the page buffer224is full. If the last compressed chunk of data is not aligned with the page size of the nonvolatile memory106ofFIG. 1, for example, the compression controller222can pad the last chunk of data to properly align with the page size.

Once the page buffer224is full, the sequencer228can cause the data to be transferred to the ECC controller226. The ECC controller226can add error correction information to the data and the sequencer228can send the compressed data and the error correction information to the nonvolatile memory106.

Also for example, the host device (not shown) can modify the operation of the compression controller222. For example, some types of data are more compressible than others; already compressed image and video formats may not be good candidates for compression. On the other hand, memory opcode (operation code) may be highly compressible (have a high compressibility ratio) and can be a good candidate for compression by the compression controller222. Further, if it is determined that a data block has a compressibility ratio below a given threshold, compression of that data block can be disabled to avoid wasting time and power on compressing a data block which is not very compressible.

The use of the compression controller222can be enabled or disabled dynamically by the host depending on the type of data or compressibility of each data block stored within the volatile memory104such as DRAM. As a further example, the exact algorithm used by the compression controller222may also be modified or changed depending on the type of data being compressed. For example, while a Lempel-Ziv (LZ77 or LC78) algorithm may be a useful algorithm for general compression, if the host device, the compression controller222, or the nonvolatile memory controller110determines that the data may be compressed better by more specialized algorithm, that specialized algorithm may be used instead. The variation in compressibility does not affect the overall benefits of the compression controller222integrated into the nonvolatile memory controller110.

Upon restoration of power to the host device after a power failure, a read command can be issued to the nonvolatile memory106to recover the data which was backed up from the volatile memory104upon detection of the power failure. The read process is basically the reverse of the write process as indicated by the double headed arrows in the figure.

For example, the ECC controller226in conjunction with the sequencer228can extract error correction information from the backed up data and write the rest of the data to the page buffer224. The compression controller222can utilize the decompression engine232with the decompression buffer236to decompress the data and the compression controller222can then write the uncompressed data to the DMA buffer220. The uncompressed data can then be written to the volatile memory104; after all the backup data is decompressed and written to the volatile memory104, the state of the volatile memory104immediately prior to the loss of power should be restored.

Referring now toFIG. 3, therein is shown a flow chart of a method300of operation of a memory management system with backup system in a further embodiment of the present invention. The method300includes: detecting a power failure condition with a memory module controller, the memory module controller including a nonvolatile memory controller in a block302; receiving a data block from volatile memory at a compression controller integrated within the nonvolatile memory controller in a block304; compressing the data block to form a compressed data block in a block306; and writing the compressed data block to nonvolatile memory in a block308.

The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.