SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

The present disclosure includes a first substrate including a first wiring layer having a first connection electrode projecting by a predetermined quantity from a first interlayer insulation film and a second wiring layer having a second connection electrode projecting by a predetermined quantity from a second interlayer insulation film. On a bonded surface between the first and second substrates, the first and second connection electrodes are joined with each other, and at the same time, at least a part of the first interlayer insulation film and a part of the second interlayer insulation film which face to each other in a lamination direction are joined with each other.

TECHNICAL FIELD

The present disclosure relates to a three-dimensional structure semiconductor device produced by bonding substrates together and a manufacturing method therefor. The present disclosure also relates to an electronic device having the semiconductor device.

BACKGROUND ART

In a method for producing a three-dimensional structure large scale integration (LSI) by bonding devices (substrates) with each other, there is a method to directly join metal electrodes with each other which are exposed on a surface of the device. In the method to directly join the metal electrodes with each other, a method has been proposed in which the metal electrode and an interlayer insulation film (ILD) on the surface of the device are planarized so as to be the same surface and the metal electrodes and the interlayer insulation films are respectively joined with each other between the devices.

Generally, when the metal electrodes are joined by the above method, a method is employed in which a Cu electrode and the interlayer insulation film on the surface of the device are planarized and the devices are bonded with each other. However, actually, a dishing occurs at the time of chemical mechanical polishing (CMP) according to an area ratio between the Cu electrode and the interlayer insulation film on the surface of the device. Therefore, it is extremely difficult to obtain the flatness of joint surface to ensure an electrical connection by directly contacting the Cu electrodes with each other. There is a method to planarize the joint surface so that the surface of the Cu electrode and the surface of the interlayer insulation film become the same surface by selecting a preferable condition at the time of the CMP. However, it is difficult to stably and continuously arrange the CMP condition.

In recent years, a method has been proposed in which the Cu electrodes project from the interlayer insulation film and the projecting Cu electrodes are connected with each other (Patent Documents 1 and 2). However, in this method, although the Cu electrodes contact with each other, the interlayer insulation films do not contact with each other in the connection between the devices. Therefore, since the Cu electrode is exposed in the external space of the device, there is a possibility that Cu is diffused on the surface of the interlayer insulation film and the reliability is deteriorated.

Further, when the metal such as Cu is not coated, there is a possibility in many cases that Cu is corroded or causes metal contamination in a process for thinning the substrate, a chemical treatment, a plasma dry etching treatment, and the like performed after the connection. According to the above, it is not preferable that the joint surfaces other than the metal do not contact with each other in the joint between the metal electrodes with each other and between the interlayer insulation films with each other.

On the other hand, a method has been proposed in which an adhesive layer is formed on a bonding surface between the devices and the surfaces of the device except for the metal electrode are contacted with each other (Patent Document 3). However, in this case, there is a problem in heat resistance of an adhesive and non-proliferation ability of Cu. There is a possibility to have an influence on the reliability of the device.

CITATION LIST

Patent Document

Patent Document 1: JP 01-205465 A

Patent Document 2: JP 2006-191081 A

Patent Document 3: JP 2006-522461 W

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In consideration of the above-mentioned point, a purpose of the present disclosure is to improve the heat resistance, diffusion resistance, and the reliability of a semiconductor device such as a solid imaging apparatus having a three-dimensional structure in which a plurality of substrates is laminated. Also, a manufacturing method for the semiconductor device and an electronic device having the semiconductor device are provided in the present disclosure.

Solutions to Problems

A semiconductor device of the present disclosure includes a first substrate and a second substrate. The first substrate includes a first wiring layer having a first connection electrode which projects by a predetermined quantity from a first interlayer insulation film. Also, the second substrate includes a second wiring layer having a second connection electrode which projects by a predetermined quantity from a second interlayer insulation film. The second substrate is bonded and provided on the first substrate so as to join the second connection electrode with the first connection electrode. At this time, on a bonded surface between the first and second substrates, the first and second connection electrodes are joined, and at the same time, at least a part of the first interlayer insulation film and a part of the second interlayer insulation film which face to each other in a lamination direction are joined with each other.

In the semiconductor device of the present disclosure, on the bonded surface between the first and second substrates, the first and second connection electrodes are sealed by the first and second interlayer insulation films which are joined with each other.

A manufacturing method for the semiconductor device of the present disclosure includes a process for preparing the first substrate including the first wiring layer having the first connection electrode which projects by the predetermined quantity from the first interlayer insulation film. Also, the manufacturing method includes a process for preparing the second substrate including the second wiring layer having the second connection electrode which projects by the predetermined quantity from the second interlayer insulation film. Next, the manufacturing method includes a process for bonding the first connection electrode of the first substrate and the second connection electrode of the second substrate so that the first and second connection electrodes face to each other. On the bonded surface between the first and second substrates, the first and second substrates are bonded so that the first and second connection electrodes are joined with each other and at the same time at least a part of the first interlayer insulation film and a part of the second interlayer insulation film which face to each other in the lamination direction are joined with each other.

In the manufacturing method for the semiconductor device of the present disclosure, on the bonded surface between the first and second substrates bonded together, the first and second connection electrodes are sealed by the first and second interlayer insulation films which are joined with each other.

An electronic device of the present disclosure includes a solid imaging apparatus and a signal processing circuit. The solid imaging apparatus includes a sensor substrate and a circuit substrate. The sensor substrate includes a sensor-side semiconductor layer having a pixel region having a photoelectric converter provided therein and a sensor-side wiring layer. The sensor-side wiring layer is provided on a surface opposite to a light-receiving surface of the sensor-side semiconductor layer and has a wiring provided via a sensor-side interlayer insulation film and a sensor-side connection electrode which projects by the predetermined quantity from a surface of the sensor-side interlayer insulation film. Also, the circuit substrate includes a circuit-side semiconductor layer and a circuit-side wiring layer. The circuit-side wiring layer includes a wiring provided on a side of the sensor-side wiring layer of the sensor substrate and provided via a circuit-side interlayer insulation film and a circuit-side connection electrode which projects by the predetermined quantity from a surface of the circuit-side interlayer insulation film. The circuit substrate is bonded and provided on the sensor substrate. Also, on a bonded surface between the sensor substrate and the circuit substrate, the sensor-side connection electrode is joined with the circuit-side connection electrode, and at the same time, at least a part of the sensor-side interlayer insulation film and a part of the circuit-side interlayer insulation film which face to each other in the lamination direction are joined. The signal processing circuit performs processing on an output signal output from the solid imaging apparatus.

Effects of the Invention

According to the present disclosure, a semiconductor device and an electronic device excellent in heat resistance and diffusion resistance and with high reliability can be obtained.

MODE FOR CARRYING OUT THE INVENTION

Non-patent Literature “Semiconductor Wafer Bonding”, Q. Y. Tong, U. Gosele; JOHN WILEY & SONS, Inc., 1999 discloses a technology regarding a Si substrate bonding. As a result of keen examination, the proposers of the technique of the present disclosure have found to apply the search result regarding an influence of a particle of the substrate on bonding to a technique for bonding electrodes together of the present disclosure.

An example of the semiconductor device, the manufacturing method therefor, and the electronic device according to the embodiments of the present disclosure will be described below with reference to the drawings.

The embodiments of present disclosure will be described in the following order. The technique of the present disclosure is not limited to the example below.

1. First embodiment: Solid imaging apparatus of two-layered structure

1-2. Manufacturing method

2. Second embodiment: Semiconductor device of three-layered structure

2-2. Manufacturing method

3. Third embodiment: Electronic device

1. First Embodiment

Solid Imaging Apparatus of Two-Layered Structure

First, as an example of a semiconductor device according to a first embodiment of the present disclosure, a solid imaging apparatus will be described.FIG. 1is a cross-section diagram of a principal part of a solid imaging apparatus1according to the first embodiment of the present disclosure. As illustrated inFIG. 1, the solid imaging apparatus1of the present embodiment is a solid imaging apparatus of a rear-surface irradiation type having a three-dimensional structure.

As illustrated inFIG. 1, the solid imaging apparatus1of the present embodiment includes a sensor substrate2and a circuit substrate3bonded on a surface opposite to a light-receiving surface of the sensor substrate2. Also, the solid imaging apparatus1of the present embodiment includes a color filter10and an on-chip lens11provided on the light-receiving surface of the sensor substrate2.

The sensor substrate2includes a sensor-side semiconductor layer12and a sensor-side wiring layer13.

The sensor-side semiconductor layer12is a semiconductor substrate, for example, configured of single-crystal silicon. In a pixel region of the sensor-side semiconductor layer12, a plurality of photoelectric converters17is arranged and formed in a two-dimensional array along the light-receiving surface (rear-surface in the present embodiment). Each photoelectric converter17has a lamination structure of an n-type diffusion layer and a p-type diffusion layer, for example. The photoelectric converter17is provided for each pixel, and a cross-sectional surface for three pixels is illustrated inFIG. 1.

Also, an impurity region including a read unit to read a signal charge accumulated in the photoelectric converter17and an impurity region including an element isolation unit are formed in the sensor-side semiconductor layer12. The impurity regions are not shown inFIG. 1.

The sensor-side wiring layer13is provided on a surface opposite to the light-receiving surface of the sensor-side semiconductor layer12and includes a plurality of (two layers inFIG. 1) wirings15laminated via a sensor-side interlayer insulation film14. The wiring15is formed of, for example, copper (Cu), and the sensor-side interlayer insulation film14is formed of, for example, SiO2. Also, a read electrode, which is not shown, including the read unit to read the signal charge generated by the photoelectric converter17is provided on a side of the sensor-side semiconductor layer12in the sensor-side wiring layer13. In the sensor-side wiring layer13, the two wirings15adjacent to each other in a lamination direction and the wiring15and the read unit are connected with each other through a via18provided in the sensor-side interlayer insulation film14as necessary. A pixel circuit to read the signal charge of each pixel is configured by the plurality of wirings15provided in the sensor-side wiring layer13and the read electrode not shown.

Also, in the sensor-side wiring layer13, the wiring15in the top layer (wiring15positioned on the most circuit substrate3side) is a sensor-side connection electrode16to ensure the electrical connection with the circuit substrate3and is provided so as to project from the surface of the sensor-side interlayer insulation film14and be exposed. In the present embodiment, a surface of the sensor-side connection electrode16and a surface of the sensor-side interlayer insulation film14become a bonded surface between the sensor substrate2and the circuit substrate3.

The circuit substrate3includes a circuit-side semiconductor layer4and a circuit-side wiring layer5.

The circuit-side semiconductor layer4is a semiconductor substrate, for example, configured of single-crystal silicon. In a surface layer for facing a side of the sensor substrate2of the circuit-side semiconductor layer4, a source/drain region of a transistor which configures a part of the pixel circuit and an impurity layer such as the element isolation unit are provided. The source/drain region and the impurity layer are not shown.

The circuit-side wiring layer5is provided on a surface-side of the circuit-side semiconductor layer4and includes a wiring7having a plurality of layers (three layers inFIG. 1) laminated via the circuit-side interlayer insulation film6. Also, a gate electrode of the transistor, which is not shown, for configuring a part of the pixel circuit is provided on a side of the circuit-side semiconductor layer4in the circuit-side wiring layer5. The wiring7is formed of, for example, copper (Cu), and the circuit-side interlayer insulation film6is formed of, for example, SiO2. Also, the two wirings7adjacent to each other in the lamination direction, and the wiring7and each transistor are connected with each other through a via8provided in the circuit-side interlayer insulation film6as necessary. A part of the pixel circuit and a drive circuit for driving the pixel circuit are configured by the transistor and the plurality of wirings7provided in the circuit-side wiring layer5.

Also, in the circuit-side wiring layer5, the wiring7in the top layer (wiring7positioned on the most sensor substrate2side) is a circuit-side connection electrode9to ensure the electrical connection with the sensor substrate2and is provided so as to project from the surface of the circuit-side interlayer insulation film6and be exposed. A surface of the circuit-side connection electrode9and a surface of the circuit-side interlayer insulation film6become the bonded surface between the sensor substrate2and the circuit substrate3.

The color filters10are provided on the light-receiving surface of the sensor substrate2via a planarization film not shown and provided corresponding to the respective photoelectric converters17. In the color filter10, filter layers which selectively transmit light of, for example, red (R), green (G), and blue (B) are arranged for the respective pixels. Also, these filter layers are arranged for each pixel, for example, in a Bayer array.

The color filter10transmits the light with a desired wavelength, and the light having passed through the color filter10enters the photoelectric converter17in the sensor-side semiconductor layer12. In the present embodiment, each pixel transmits the light of any one of R, G, and B. However, the color of the light is not limited to these. As a material for forming the color filter10, an organic material which transmits the light of cyan, yellow, magenta, and the like may be used. The material can be variously selected according to a specification.

The on-chip lens11is formed above the color filter10and formed for each pixel. The incident light is concentrated in the on-chip lens11, and the concentrated light efficiently enters the corresponding photoelectric converter17via the color filter10. In the present embodiment, the on-chip lens11concentrates the incident light at the center position of the photoelectric converter17.

In the present embodiment, the sensor substrate2and the circuit substrate3are bonded and laminated with each other and the sensor-side connection electrode16provided in the sensor-side wiring layer13and the circuit-side connection electrode9provided in the circuit-side wiring layer5are electrically connected with each other on the bonded surface. Accordingly, for example, the drive circuit for driving the pixel and the signal processing circuit for processing the signal obtained by the pixel can be provided in the circuit substrate3. Therefore, a larger pixel area can be ensured in the sensor substrate2.

Also, as will be described below, on the bonded surface between the sensor substrate2and the circuit substrate3, the sensor-side connection electrode16is connected with the circuit-side connection electrode9, and at the same time, the sensor-side interlayer insulation film14of an outermost surface of the sensor substrate2and the circuit-side interlayer insulation film6of an outermost surface of the circuit substrate3are joined with each other. Accordingly, surrounding areas of the sensor-side connection electrode16and the circuit-side connection electrode9are sealed by the interlayer insulation film. Therefore, the sensor-side connection electrode16and the circuit-side connection electrode9are not exposed in external space of the solid imaging apparatus1.

1-2 Manufacturing Method

FIGS. 2A to 2Care process diagrams of a manufacturing method for the solid imaging apparatus1of the present embodiment. The manufacturing method for the solid imaging apparatus1of the present embodiment will be described with reference toFIGS. 2A to 2C.

First, as illustrated inFIG. 2A, the plurality of photoelectric converters17is formed in the pixel region in the sensor-side semiconductor layer12, and at the same time, the desired impurity region which is not shown is formed. After that, the sensor substrate2is produced by forming the sensor-side wiring layer13on the surface of the sensor-side semiconductor layer12. The photoelectric converter17and the desired impurity region not shown can be formed by ion implantation of a desired impurity on the surface of the sensor-side semiconductor layer12.

Also, the sensor-side wiring layer13is formed by alternately repeating the formation of the sensor-side interlayer insulation film14and the formation of the wiring. At this time, a vertical hole is formed in the sensor-side interlayer insulation film14as necessary. Then, a via which connects the wiring15with the read unit and a via18which connects two wirings15adjacent to each other in the lamination direction are formed by embedding an electrically conductive material in the vertical hole. Also, the wiring15has been formed by using a so-called damascene method. In the damascene method, the electrically conductive material is embedded so as to coat a wiring groove and the sensor-side interlayer insulation film14and an electrically conductive material layer is polished by using the CMP method until the sensor-side interlayer insulation film14is exposed after the wiring groove has been formed in the sensor-side interlayer insulation film14.

At this time, in the present embodiment, the sensor-side wiring layer13has been formed so that the wiring15which is the sensor-side connection electrode16in the top layer (the wiring15which is farthest from the sensor-side semiconductor layer12) projects by a predetermined projection quantity h1 from the surface of the sensor-side interlayer insulation film14as illustrated inFIG. 2A. The projection quantity h1 of the sensor-side connection electrode16can be controlled by adjusting slurry when the electrically conductive material layer which is the sensor-side connection electrode16is polished by using the CMP method. The projection quantity h1 will be described below. Also, it is assumed that a distance between the sensor-side connection electrodes16adjacent to each other be R1.

Next, as illustrated inFIG. 2B, the circuit substrate3is produced by forming the circuit-side wiring layer5on the surface of the circuit-side semiconductor layer4after the impurity region which is not shown has been formed in the circuit-side semiconductor layer4. The impurity region not shown can be formed by the ion implantation of the desired impurity on the surface of the circuit-side semiconductor layer4.

Also, the circuit-side wiring layer5is formed by alternately repeating the formation of the circuit-side interlayer insulation film6and the formation of the wiring7. At this time, a vertical hole is formed in the circuit-side interlayer insulation film6as necessary.

Then, a via which connects the wiring7with the transistor and a via8which connects two wirings7adjacent to each other in the lamination direction are formed by embedding the electrically conductive material in the vertical hole. Also, in the circuit substrate3, the wiring7has been formed by using the damascene method. The circuit-side wiring layer5has been formed so that the wiring7which is the circuit-side connection electrode9in the top layer (the wiring7which is farthest from the circuit-side semiconductor layer4) projects by a predetermined projection quantity h2 from the surface of the circuit-side interlayer insulation film6. Also, it is assumed that a distance between the circuit-side connection electrodes9adjacent to each other be R2 (=R1).

The projection quantity h1 of the sensor-side connection electrode16and the projection quantity h2 of the circuit-side connection electrode9are controlled to satisfy the conditions indicated by following formulas (1) and (2).

Here, E1′ is E1/(1−ν12) (E1: Young's modulus of the sensor-side semiconductor layer12, ν1: Poisson's ratio of the sensor-side semiconductor layer12). E2′ is E2/(1−ν22) (E2: Young's modulus of the circuit-side semiconductor layer4, ν2: Poisson's ratio of the circuit-side semiconductor layer4). Also, γ is a joint strength (surface energy) between the sensor-side interlayer insulation film14and the circuit-side interlayer insulation film6. Also, R1 is the distance between the sensor-side connection electrodes16adjacent to each other, and R2 is the distance between the circuit-side connection electrodes9adjacent to each other. Also, tw1is the thickness of the sensor-side semiconductor layer12, and tw2is the thickness of the circuit-side semiconductor layer4.

The condition of the formula (1) is applied when R1>2tw1and tw1>>h1. The condition of the formula (2) is applied when R2>2tw2and tw2>>h2. Additionally, when the formulas (1) and (2) respectively satisfy 2tw1=R1 and 2tw2=R2 or when the formulas (1) and (2) respectively satisfy 2tw1>R1 and 2tw2>R2, the formulas (1) and (2) can be approximate to formulas (3) and (4) below.

Furthermore, in a case where the sensor substrate2and the circuit substrate3are joined by receiving power from outside at the time of joint indicated in the process below, the projection quantities h1 and h2 are respectively set so as to satisfy formulas (5) and (6).

In the present embodiment, it is assumed that each projection quantities h1 and h2 be 10 nm and each R1 and R2 be 50 μm as values for satisfying the above condition. In this case, the projection quantities h1 and h2 are set so as to satisfy the condition of Expression 2.

Next, as illustrated inFIG. 2C, the sensor substrate2is contacted with and bonded with the circuit substrate3after a surface on a side of the sensor-side connection electrode16of the sensor substrate2has been aligned with and faced to a surface on a side of the circuit-side connection electrode9of the circuit substrate3so that the connection electrodes thereof are faced to each other. The bonding process has been performed by depressing a center position of a wafer (for example, the sensor substrate2) with a pin immediately after the polishing process according to the CMP method in the previous stage. In the present embodiment, it is assumed that a depression load be 12 N, and the wafer is depressed with a pin having a spherical front end.

In the present embodiment, the projection quantity h1 of the sensor-side connection electrode16in the sensor substrate2and the projection quantity h2 of the circuit-side connection electrode9in the circuit substrate3are set so as to satisfy the conditions indicated by the above-mentioned formulas (3) and (4). Therefore, since the both insulation films attract each other depending on the joint strength, the substrate itself is deformed (bent). Accordingly, on the bonded surface between the sensor substrate2and the circuit substrate3, the sensor-side connection electrode16and the circuit-side connection electrode9, which face to each other, are joined, and at the same time, the sensor-side interlayer insulation film14and the circuit-side interlayer insulation film6, which face to each other, are joined with each other.

Next, although the process is not shown, the sensor-side semiconductor layer12of the sensor substrate2has been polished from a side of the rear-surface, and the sensor-side semiconductor layer12has been thinned. After that, the solid imaging apparatus1shown inFIG. 1has been completed by forming the planarization film which is not shown, the color filter10, and the on-chip lens11similarly to a normal manufacturing method for a solid imaging apparatus.

In the present embodiment, the sensor-side interlayer insulation film14and the circuit-side interlayer insulation film6, which face to each other, are joined on the bonded surface between the sensor substrate2and the circuit substrate3. Therefore, surrounding areas of the sensor-side connection electrode16and the circuit-side connection electrode9are respectively sealed by the sensor-side interlayer insulation film14and the circuit-side interlayer insulation film6. Accordingly, on the bonded surface, the sensor-side connection electrode16and the circuit-side connection electrode9are not exposed to external environment of the solid imaging apparatus1. Therefore, the sensor-side connection electrode16and the circuit-side connection electrode9are not exposed in chemical solution at the time of chemical treatment performed after bonding. Also, the two substrates can be bonded without using a material such as a resin with low heat resistance and low diffusion resistance on the bonded surface. Therefore, high-temperature processing can be performed without worrying about the heat resistance temperature after the bonding, and the reliability can be improved.

Also, in the present embodiment, the sensor-side connection electrode16and the circuit-side connection electrode9have projected by the predetermined projection quantity from the respective surfaces of the sensor-side interlayer insulation film14and the circuit-side interlayer insulation film6before the bonding. Therefore, in the present embodiment, since the acceptable range of a variation generated at the time of the planarization processing becomes bigger than that of the traditional bonding technique in which the surface of the interlayer insulation film and the surface of the connection electrode are planarized so as to be the same surface, mass producibility can be improved.

In the bonding process between the sensor substrate2and the circuit substrate3, a position of the sensor-side connection electrode16may be deviated from a position of the circuit-side connection electrode9.FIG. 3is a schematic diagram of a case where the position of the sensor-side connection electrode16is deviated from the position of the circuit-side connection electrode9by x along the bonded surface. As illustrated inFIG. 3, even when the bonding position is deviated by x along the bonded surface between the sensor substrate2and the circuit substrate3, the sensor-side interlayer insulation film14and the circuit-side interlayer insulation film6can be joined by setting the projection quantities h1 and h2 by displacing R1 with R1−x under the condition indicated by the formula 1.

As has been described above, the projection quantities h1 and h2 are set so as to satisfy a formula in which R1 is displaced with R1−x under the condition indicated by the formula 1 when the gap x is considered at the time of bonding the sensor substrate2with the circuit substrate3. Accordingly, the CMP process can be performed with a margin, and the mass producibility can be improved.

2. Second Embodiment

Semiconductor Device of Three-Layered Structure

Next, a semiconductor device according to a second embodiment of the present disclosure will be described.FIG. 4is a cross-section diagram of a semiconductor device20of the present embodiment. A structure of the semiconductor device20of the present embodiment is a three-layered structure in which three layers of semiconductor substrates are laminated.

As illustrated inFIG. 4, the semiconductor device20of the present embodiment includes a first substrate21, a second substrate22, and a third substrate23. The semiconductor device20also includes a lamination structure having the first substrate21, the second substrate22, and the third substrate23laminated in this order.

The first substrate21includes a first semiconductor layer24and a first wiring layer25. The first semiconductor layer24is a semiconductor substrate, for example, configured of single-crystal silicon. In a surface layer on a side of the second substrate22in the first semiconductor layer24, a source/drain region of a transistor which configures a predetermined circuit and an impurity layer such as an element isolation unit are provided as necessary. The source/drain region and the impurity layer are not shown.

The first wiring layer25is provided on a surface of the first semiconductor layer24and includes a plurality of wirings26(three layers inFIG. 4) laminated via a first interlayer insulation film27. Also, a gate electrode of the transistor, which is not shown, for configuring the predetermined circuit is provided on a side of the first semiconductor layer24in the first wiring layer25as necessary. The wiring26is formed of, for example, copper (Cu), and the first interlayer insulation film27is formed of, for example, SiO2. Also, the two wirings26adjacent to each other in a lamination direction, and the wiring26and each transistor are connected with each other through a via29provided in the first interlayer insulation film27as necessary. A first circuit includes the transistor and the plurality of wirings26provided in the first wiring layer25.

Also, in the first wiring layer25, the wiring26in the top layer (the wiring26positioned on the most second substrate22side) is a first connection electrode28to ensure an electrical connection with the second substrate22and is provided so as to project from a surface of the first interlayer insulation film27. In the present embodiment, a surface of the first connection electrode28and a surface of the first interlayer insulation film27become a bonded surface between the first substrate21and the second substrate22.

The second substrate22includes a second wiring layer33. The second wiring layer33includes a plurality of wirings32(three layers inFIG. 4) laminated via a second interlayer insulation film31. The wiring32is formed of, for example, copper (Cu), and the second interlayer insulation film31is formed of, for example, SiO2. Also, as necessary, the two wirings32adjacent to each other in the lamination direction are connected with each other through a via34provided in the second interlayer insulation film31. A second circuit includes the wirings32provided in the second wiring layer33.

Also, in the second wiring layer33, the wiring32in the top layer (the wiring32positioned on the most first substrate21side) is a lower-side connection electrode35to ensure the electrical connection with the first substrate21and is provided so as to project from a under surface of the second interlayer insulation film31. Also, in the second wiring layer33, the wiring32in the top layer (the wiring32positioned on the most third substrate23side) is an upper-side connection electrode36to ensure the electrical connection with the third substrate23and is provided so as to project from the upper surface of the second interlayer insulation film31. In the present embodiment, the surface of the lower-side connection electrode35and the lower surface of the second interlayer insulation film31become the bonded surface between the first substrate21and the second substrate22. The surface of the upper-side connection electrode36and the upper surface of the second interlayer insulation film31become the bonded surface between the second substrate22and the third substrate23.

The third substrate23includes a third semiconductor layer37and a third wiring layer38. The third semiconductor layer37is a semiconductor substrate, for example, configured of single-crystal silicon. In a surface layer on a side of the second substrate22in the third semiconductor layer37, a source/drain region of a transistor which configures a predetermined circuit and an impurity layer such as the element isolation unit are provided as necessary. The source/drain region and the impurity layer are not shown.

The third wiring layer38is provided on a surface of the third semiconductor layer37and includes a plurality of layers of wirings39(three layers inFIG. 4) laminated via a third interlayer insulation film40. Also, as necessary, a gate electrode of a transistor, which is not shown, for configuring a predetermined circuit is provided on the surface of the side of the third semiconductor layer37of the third wiring layer38. The wiring39is formed of, for example, copper (Cu), and the third interlayer insulation film is formed of, for example, SiO2. Also, as necessary, the two wirings39adjacent to each other in the lamination direction, and the wiring39and each transistor are connected with each other through a via41provided in the third interlayer insulation film40. A third circuit includes the transistor and the plurality of wirings39provided in the third wiring layer38.

Also, in the third wiring layer38, the wiring39in the top layer (the wiring39positioned on the most second substrate22side) is a third connection electrode42to ensure the electrical connection with the second substrate22and is provided so as to project from a surface of the third interlayer insulation film40. In the present embodiment, a surface of the third connection electrode42and a surface of the third interlayer insulation film40become the bonded surface between the third substrate23and the second substrate22.

2-2 Manufacturing Method

FIGS. 5A to 7Gare process diagrams of a manufacturing method for the semiconductor device20of the present embodiment. The manufacturing method for the semiconductor device20of the present embodiment will be described with reference toFIGS. 5A to 7G.

First, as illustrated inFIG. 5A, the first substrate21is produced by forming the first wiring layer25on the surface of the first semiconductor layer24after an impurity region which is not shown has been formed in the first semiconductor layer24. A desired impurity region not shown can be formed by ion implantation of desired impurity on the surface of the first semiconductor layer24. Also, the first wiring layer25is formed by alternately repeating the formation of the first interlayer insulation film27and the formation of the wiring26. At this time, a vertical hole is formed in the first interlayer insulation film27as necessary. Then, a via which connects the wiring26with the transistor and a via29which connects two wirings26adjacent to each other in the lamination direction are formed by embedding an electrically conductive material in the vertical hole. Also, the wiring26is formed by using the damascene method in the first substrate21similarly to the first embodiment. The first wiring layer25has been formed so that the wiring26in the top layer which is the first connection electrode28(the wiring26which is farthest from the first semiconductor layer24) projects by the predetermined projection quantity h from the surface of the first interlayer insulation film27. Also, it is assumed that a distance between the first connection electrodes28adjacent to each other be R.

Next, as illustrated inFIG. 5B, the second substrate22is produced by preparing a second semiconductor layer30and forming the second wiring layer33on the surface of the second semiconductor layer30. Here, an upper-side connection electrode36in the second wiring layer33has not been formed yet. The second wiring layer33is formed by alternately repeating the formation of the second interlayer insulation film31and the formation of the wiring32. At this time, a vertical hole is formed in the second interlayer insulation film31as necessary. Then, a via34which connects two wirings32adjacent to each other in the lamination direction is formed by embedding the electrically conductive material in the vertical hole. Also, in the second substrate22, the wiring32has been formed by using the damascene method. The second wiring layer33has been formed so that the wiring32which is the lower-side connection electrode35in the bottom layer (the wiring32which is farthest from the second semiconductor layer30) projects by a predetermined projection quantity h from the surface of the second interlayer insulation film31. Also, it is assumed that a distance between the lower-side connection electrodes35adjacent to each other be R. The second semiconductor layer30is removed in the following process.

Next, as illustrated inFIG. 5C, the third substrate23is produced by forming the third wiring layer38on the surface of the third semiconductor layer37after an impurity region which is not shown has been formed in the third semiconductor layer37. The impurity region not shown can be formed by the ion implantation of the desired impurity on the surface of the third semiconductor layer37. Also, the third wiring layer38is formed by alternately repeating the formation of the third interlayer insulation film40and the formation of the wiring39. At this time, a vertical hole is formed in the third interlayer insulation film40as necessary. Then, a via which connects the wiring39with the transistor and a via41which connects two wirings39adjacent to each other in the lamination direction are formed by embedding the electrically conductive material in the vertical hole. Also, in the third substrate23, the wiring has been formed by using the damascene method. The third wiring layer38has been formed so that the wiring39which is the third connection electrode42in the top layer (the wiring39which is farthest from the third semiconductor layer37) projects by the predetermined projection quantity h from the surface of the third interlayer insulation film40. Also, it is assumed that a distance between the third connection electrodes42adjacent to each other, which are not shown, be R.

In the present embodiment, the projection quantities h of the first connection electrode28, the lower-side connection electrode35, and the third connection electrode42respectively in the first substrate21, the second substrate22, and the third substrate23can be set by using a conditional expression in which the projection quantity h1 in the formulas (1), (3), and (5) is replaced with the projection quantity h. When the projection quantity h of the first connection electrode28is obtained, it is assumed that E1 be the Young's modulus of the first semiconductor layer24, ν1 be the Poisson's ratio of the first semiconductor layer24, and γ be the joint strength (surface energy) between the first interlayer insulation film27and the second interlayer insulation film31. Also, it is assumed that R1 be the distance R between the first connection electrodes28adjacent to each other and tw1be the thickness of the first semiconductor layer24.

Also, when the projection quantity h of the lower-side connection electrode35is obtained, it is assumed that E1 be the Young's modulus of the second semiconductor layer30, ν1 be the Poisson's ratio of the second semiconductor layer30, and γ be the joint strength (surface energy) between the second interlayer insulation film31and the first interlayer insulation film27. Also, it is assumed that R1 be the distance R between the lower-side connection electrodes35adjacent to each other and tw1be the thickness of the second semiconductor layer30.

Also, when the projection quantity h of the third connection electrode42is obtained, it is assumed that E1 be the Young's modulus of the third semiconductor layer37, ν1 be the Poisson's ratio of the third semiconductor layer37, and γ be the joint strength (surface energy) between the third interlayer insulation film40and the second interlayer insulation film31. Also, it is assumed that R1 be the distance R between the third connection electrodes42adjacent to each other and tw1be the thickness of the third semiconductor layer37.

In the present embodiment, as values for satisfying the above conditional expression, it is assumed that the projection quantities h of the first connection electrode28, the lower-side connection electrode35, and the third connection electrode42be 10 nm and the distance R between the respective connection electrodes be 50 nm.

Next, as illustrated inFIG. 6D, the first substrate21is contacted with and bonded with the second substrate22after a surface on a side of the first connection electrode28of the first substrate21has been aligned with and faced to a surface on a side of the lower-side connection electrode35of the second substrate22so that the connection electrodes thereof are faced to each other. The bonding process has been performed by depressing a center position of a wafer (for example, the second substrate22) with a pin immediately after the polishing process according to the CMP method in the previous stage. In the present embodiment, it is assumed that a depression load be 12 N, and the wafer is depressed with a pin having a spherical front end.

In the present embodiment, the projection quantity h of the first connection electrode28in the first substrate21and the projection quantity h of the lower-side connection electrode35in the second substrate22are set so as to satisfy the above conditional expression. Therefore, on the bonded surface between the first substrate21and the second substrate22, the first connection electrode28and the lower-side connection electrode35, which face to each other, are joined, and at the same time, the first interlayer insulation film27and the second interlayer insulation film31, which face to each other, are joined.

Next, as illustrated inFIG. 6E, the second semiconductor layer30of the second substrate22is polished from the side of the rear-surface. After the second semiconductor layer30has been thinned until a film thickness of the second semiconductor layer30becomes 100 μm, the remaining second semiconductor layer30is separated from the second wiring layer33by the chemical solution. In the present embodiment, most regions of the first interlayer insulation film27and the second interlayer insulation film31, which face to each other, are joined with each other on the bonded surface between the first substrate21and the second substrate22. Therefore, in a separation process of the second semiconductor layer30, the chemical solution does not penetrate into the bonded surface, and also, the first connection electrode28and the lower-side connection electrode35are not exposed in the chemical solution. As a result, the second semiconductor layer30can be removed without damaging the bonded surface between the first substrate21and the second substrate22.

Next, as illustrated inFIG. 7F, the second circuit is completed by further forming the second interlayer insulation film31, the wiring32, and the via34on the second wiring layer33exposed by removing the second semiconductor layer30. In the completed second wiring layer33, the wiring32in the top layer (the wiring32provided on the opposite surface to the lower-side connection electrode35) is the upper-side connection electrode36to ensure the electrical connection with the third substrate23and formed to project from the upper surface of the second interlayer insulation film31. Also, in this case, the wiring32is formed by the damascene method and the amount of the polish is adjusted by using the CMP method so as to adjust the projection quantity h of the upper-side connection electrode36from the upper surface of the second interlayer insulation film31. In the present embodiment, the projection quantity h of the upper-side connection electrode36is set to be the same as that of the lower-side connection electrode35.

Next, as illustrated inFIG. 7G, the second substrate22is contacted with and bonded with the third substrate23after a surface of a side of the upper-side connection electrode36of the second substrate22has been aligned with and faced to a surface on a side of the third connection electrode42of the third substrate23so that the connection electrodes thereof are faced to each other. The bonding process has been performed by depressing the center position of the wafer (for example, the third substrate23) with the pin immediately after the polishing process according to the CMP method at the time of forming the upper-side connection electrode36. In the present embodiment, it is assumed that a depression load be 12 N, and the wafer is depressed with a pin having a spherical front end.

In the present embodiment, the projection quantity h of the upper-side connection electrode36in the second substrate22and the projection quantity h of the third connection electrode42in the third substrate23are set so as to satisfy the above conditional expression. Therefore, on the bonded surface between the second substrate22and the third substrate23, the upper-side connection electrode36and the third connection electrode42, which face to each other, are joined, and at the same time, the second interlayer insulation film31and the third interlayer insulation film40, which face to each other, are joined with each other. After that, the third semiconductor layer37has been polished until it becomes a predetermined film thickness as necessary, and the semiconductor device20of the present embodiment illustrated inFIG. 4has been completed.

In the semiconductor device20of the present embodiment, the second interlayer insulation film31and the third interlayer insulation film40are joined with each other on the bonded surface between the second substrate22and the third substrate23. Therefore, also in a case where the third semiconductor layer37is polished after the bonding process in theFIG. 7G, the third semiconductor layer37can be polished without damaging the bonded surface between the second substrate22and the third substrate23.

In the present embodiment, the effect similar to that of the first embodiment can be obtained. Also, the configuration of the semiconductor device20in this way can be applied to, for example, a semiconductor memory, and a semiconductor laser other than the solid imaging apparatus.

Also, in the example of the present embodiment, the first, second, and third circuits are electrically connected with one another on the bonded surface. However, the first, second, and third circuits are not limited to this example and may be respectively independent. In this case, each connection electrode on the bonded surface are used to connect the substrates.

Electronic Device

Next, an electronic device according to a third embodiment of the present disclosure will be described.FIG. 8is a schematic block diagram of an electronic device200according to the third embodiment of the present disclosure.

The electronic device200according to the present embodiment includes a solid imaging apparatus1, an optical lens210, a shutter device211, a drive circuit212, and a signal processing circuit213. In the present embodiment, am embodiment of a case will be described where the solid imaging apparatus1in the first embodiment of the present disclosure mentioned as the solid imaging apparatus1is used in an electronic device (digital still camera).

The optical lens210images imaging light (incident light) from a subject on an imaging surface of the solid imaging apparatus1. Accordingly, a signal charge is accumulated in the solid imaging apparatus1for a certain period of time. The shutter device211controls a light irradiation period and a light blocking period relative to the solid imaging apparatus1. The drive circuit212supplies a driving signal for controlling a signal transfer operation of the solid imaging apparatus1and a shutter operation of the shutter device211. The solid imaging apparatus1transfers the signal according to the driving signal (timing signal) supplied from the drive circuit212. The signal processing circuit213performs various signal processing relative to the signal output from the solid imaging apparatus1. A video signal to which the signal processing has been performed is stored in a storage media such as a memory or output to a monitor.

In the electronic device200of the present embodiment, since the solid imaging apparatus1having a lamination structure is produced by a manufacturing method with high mass producibility and high reliability, the cost can be reduced.

Also, the present disclosure can have a configuration below.

A semiconductor device including:

a first substrate configured to include a first interlayer insulation film and a first wiring layer having a first connection electrode projecting by a predetermined quantity from the first interlayer insulation film; and

a second substrate configured to include a second interlayer insulation film and a second wiring layer having a second connection electrode projecting by a predetermined quantity from the second interlayer insulation film, wherein

the second connection electrode is bonded on the first substrate so as to join with the first connection electrode, and the second connection electrode is joined with the first connection electrode and at the same time at least a part of the first interlayer insulation film and a part of the second interlayer insulation film are joined with each other on the bonded surface.

The semiconductor device according to (1), wherein

the first substrate includes a first semiconductor layer, the first wiring layer is provided above the first semiconductor layer, the second substrate includes a second semiconductor layer, the second wiring layer is provided above the second semiconductor layer, and

a projection quantity h1 of the first connection electrode from the first interlayer insulation film and a projection quantity h2 of the second connection electrode from the second interlayer insulation film satisfy conditions of the following formulas (1) and (2) in a case where it is assumed that E1/(1−ν12) be E1′ when it is assumed that E1 be Young's modulus of the first semiconductor layer and ν1 be Poisson's ratio of the first semiconductor layer, E2/(1−ν22) be E2′ when it is assumed that E2 be the Young's modulus of the second semiconductor layer and ν2 be the Poisson's ratio of the second semiconductor layer, a joint strength between the first interlayer insulation film and the second interlayer insulation film be γ, a distance between the first connection electrodes adjacent to each other be R1, a thickness of the first semiconductor layer be tw1, a distance between the second connection electrodes adjacent to each other be R2, and a thickness of the second semiconductor layer be tw2.

The semiconductor device according to (1), wherein

the first substrate includes a first semiconductor layer, the first wiring layer is provided above the first semiconductor layer, the second substrate includes a second semiconductor layer, the second wiring layer is provided above the second semiconductor layer, and

a projection quantity h1 of the first connection electrode from the first interlayer insulation film and a projection quantity h2 of the second connection electrode from the second interlayer insulation film satisfy conditions of the following formulas (3) and (4) in a case where it is assumed that E1/(1−ν12) be E1′ when it is assumed that E1 be Young's modulus of the first semiconductor layer and ν1 be Poisson's ratio of the first semiconductor layer, E2/(1−ν22) be E2′ when it is assumed that E2 be the Young's modulus of the second semiconductor layer and ν2 be the Poisson's ratio of the second semiconductor layer, a joint strength between the first interlayer insulation film and the second interlayer insulation film be γ, a thickness of the first semiconductor layer be tw1, and a thickness of the second semiconductor layer be tw2.

The semiconductor device according to (1), wherein

the first substrate includes a first semiconductor layer, the first wiring layer is provided above the first semiconductor layer, the second substrate includes a second semiconductor layer, the second wiring layer is provided above the second semiconductor layer, and

a projection quantity h1 of the first connection electrode from the first interlayer insulation film and a projection quantity h2 of the second connection electrode from the second interlayer insulation film satisfy conditions of the following formulas (5) and (6) in a case where it is assumed that E1/(1−ν12) be E1′ when it is assumed that E1 be Young's modulus of the first semiconductor layer and ν1 be Poisson's ratio of the first semiconductor layer, E2/(1−ν22) be E2′ when it is assumed that E2 be the Young's modulus of the second semiconductor layer and ν2 be the Poisson's ratio of the second semiconductor layer, a joint strength between the first interlayer insulation film and the second interlayer insulation film be γ, a distance between the first connection electrodes adjacent to each other be R1, and a distance between the second connection electrodes adjacent to each other be R2.

A manufacturing method for a semiconductor device, including:

a step of preparing a first substrate including a first wiring layer having a first connection electrode projecting by a predetermined quantity from a first interlayer insulation film;

a step of preparing a second substrate including a second wiring layer having a second connection electrode projecting by a predetermined quantity from a second interlayer insulation film; and

a step of bonding the first connection electrode of the first substrate with the second connection electrode of the second substrate while facing them to each other and bonding the first substrate with the second substrate so that the first connection electrode and the second connection electrode are joined and at the same time at least a part of the first interlayer insulation film and a part of the second interlayer insulation film, which face to each other in a lamination direction, are joined with each other on the bonded surface.

The manufacturing method for a semiconductor device according to (5), wherein

the first substrate includes a first semiconductor layer, the first wiring layer is provided above the first semiconductor layer, the second substrate includes a second semiconductor layer, the second wiring layer is provided above the second semiconductor layer, and

the first substrate and the second substrate are formed so that a projection quantity h1 of the first connection electrode from the first interlayer insulation film and a projection quantity h2 of the second connection electrode from the second interlayer insulation film satisfy conditions of the following formulas (1) and (2) in a case where it is assumed that E1/(1−ν12) be E1′ when it is assumed that E1 be Young's modulus of the first semiconductor layer and ν1 be Poisson's ratio of the first semiconductor layer, E2/(1−ν22) be E2′ when it is assumed that E2 be the Young's modulus of the second semiconductor layer and ν2 be the Poisson's ratio of the second semiconductor layer, a joint strength between the first interlayer insulation film and the second interlayer insulation film be γ, a distance between the first connection electrodes adjacent to each other be R1, a thickness of the first semiconductor layer be tw1, a distance between the second connection electrodes adjacent to each other be R2, and a thickness of the second semiconductor layer be tw2.

The manufacturing method for a semiconductor device according to (5), wherein

the first substrate includes a first semiconductor layer, the first wiring layer is provided above the first semiconductor layer, the second substrate includes a second semiconductor layer, the second wiring layer is provided above the second semiconductor layer, and

the first substrate and the second substrate are formed so that a projection quantity h1 of the first connection electrode from the first interlayer insulation film and a projection quantity h2 of the second connection electrode from the second interlayer insulation film satisfy conditions of the following formulas (3) and (4) in a case where it is assumed that E1/(1−ν12) be E1′ when it is assumed that E1 be Young's modulus of the first semiconductor layer and ν1 be Poisson's ratio of the first semiconductor layer, E2/(1−ν22) be E2′ when it is assumed that E2 be the Young's modulus of the second semiconductor layer and ν2 be the Poisson's ratio of the second semiconductor layer, a joint strength between the first interlayer insulation film and the second interlayer insulation film be γ, a thickness of the first semiconductor layer be tw1, and a thickness of the second semiconductor layer be tw2.

The manufacturing method for a semiconductor device according to (5), wherein

the first substrate includes a first semiconductor layer, the first wiring layer is provided above the first semiconductor layer, the second substrate includes a second semiconductor layer, the second wiring layer is provided above the second semiconductor layer, and

the first substrate and the second substrate are formed so that a projection quantity h1 of the first connection electrode from the first interlayer insulation film and a projection quantity h2 of the second connection electrode from the second interlayer insulation film satisfy conditions of the following formulas (5) and (6) in a case where it is assumed that E1/(1−ν12) be E1′ when it is assumed that E1 be Young's modulus of the first semiconductor layer and ν1 be Poisson's ratio of the first semiconductor layer, E2/(1−ν22) be E2′ when it is assumed that E2 be the Young's modulus of the second semiconductor layer and ν2 be the Poisson's ratio of the second semiconductor layer, a joint strength between the first interlayer insulation film and the second interlayer insulation film be γ, a distance between the first connection electrodes adjacent to each other be R1, and a distance between the second connection electrodes adjacent to each other be R2.

An electronic device including:

a solid imaging apparatus configured to include a sensor substrate including a sensor-side semiconductor layer including a pixel region having a photoelectric converter provided therein and a sensor-side wiring layer having a wiring provided on a side of a surface opposite to a light-receiving surface of the sensor-side semiconductor layer and provided via a sensor-side interlayer insulation film and a sensor-side connection electrode projecting by a predetermined quantity from a surface of the sensor-side interlayer insulation film and a circuit substrate, which is bonded and provided on the sensor substrate, including a circuit-side semiconductor layer and a circuit-side wiring layer having a wiring provided on a side of the sensor-side wiring layer of the sensor substrate and provided via a circuit-side interlayer insulation film and a circuit-side connection electrode projecting by a predetermined quantity from a surface of the circuit-side interlayer insulation film; and

a signal processing circuit configured to perform processing on an output signal output from the solid imaging apparatus, wherein

the solid imaging apparatus includes the sensor-side connection electrode and the circuit-side connection electrode joined with each other and at least a part of a sensor-side interlayer insulation film and a part of a circuit-side interlayer insulation film, which face to each other in a lamination direction, are joined with each other on a bonded surface between the sensor substrate and the circuit substrate.

REFERENCE SIGNS LIST