Structure for measurement of capacitance of ultra-thin dielectrics

Disclosed is an on-chip test device for testing the thickness of gate oxides in transistors. A ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide and the inverter receives different voltages as power supplies. The difference between the voltages provides a measurement of capacitance of the gate oxide. The difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator. The capacitance of the gate oxide comprises the inverse of the frequency of the ring oscillator output multiplied by the difference between the voltages, less a capacitance constant for the test device. This capacitance constant is for the test device alone, and does not include any part of the capacitance of the gate oxide. The measurement of capacitance of the gate oxide is used to determine the thickness of the gate oxide.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention generally relates to an on-chip test circuit for testing the gate oxide capacitance and more particularly to a circuit that includes a ring oscillator to allow high frequency testing.

2. Description of the Related Art

As integrated circuit transistors are reduced in size (e.g., scaled), gate dielectrics continue to get thinner. Gate dielectrics that have been scaled to very small values are experiencing an exponential increase in the incidence of undesirable tunneling currents, in which the gate dielectric fails to insulate the gate from the underlying substrate. In addition, the increased use of larger dielectric DC currents requires the use of higher frequency test devices when measuring capacitance in order for the displacement current to significantly exceed the DC leakage current.

For example, in 90 nm technology, the DC leakage has reached current densities on the order of 400 A/cm2, requiring frequencies on the order of 100 Mhz for the displacement current to significantly exceed the DC leakage current. Ordinary test structures and test equipment are unable to perform such high-frequency measurements, making the characterization of gate oxide thickness a very difficult test, which is unable to be repeated in a manufacturing environment.

SUMMARY OF INVENTION

The invention provides an on-chip test device for testing the thickness of gate oxides in transistors. With the invention, a ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide capacitor and the inverter receives different voltages as power supplies. The current drawn by the inverter provides a measurement of capacitance of the gate oxide. In a different embodiment, the invention comprises a plurality of inverters receiving the ring oscillator output to allow one of the terminals of a multi-terminal device to be tested. Current drawn by the inverters provides a measurement of capacitance of each of the devices under test.

The difference between the voltages supplied to the inverter is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator. Also, the difference between the voltages supplied to the inverter is less than the sum of the absolute values of the threshold voltages of the n-type and p-type FETs that make up the inverter.

The capacitance of the gate oxide is calculated by multiplying the frequency of the ring oscillator output by the difference between the voltages supplied to the inverter. The current drawn by the inverter is then divided by the result of this multiplication process. A capacitance constant for the test device is then subtracted from the result of this division process. This capacitance constant is for the test device alone, and does not include any part of the capacitance of the gate oxide capacitor. The measurement of capacitance of the gate oxide capacitor is used to determine the electrical thickness of the gate oxide through the well known relationship Tinv=A×∈ox/C, where A is the area of the gate oxide capacitor, C is the measured capacitance, and ∈oxis the dielectric constant of the gate oxide.

In method form, the invention provides a method of testing the capacitance of a device under test in an integrated circuit chip. More specifically, this method supplies the output of the ring oscillator to the inverter to produce an inverted ring oscillator output. Again, the inverter receives different voltages as power supplies. The method also inputs the inverted ring oscillator output to the device under test. The current drawn by the inverter provides a measurement of capacitance of the device under test. Again, the difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator and is also less than the sum of the absolute values of the threshold voltages of the n-type and p-type FETs that make up the inverter. The capacitance of the device under test is calculated by multiplying the frequency of the ring oscillator output by the difference between the voltages supplied to the inverter. The current drawn by the inverter is then divided by the result of this multiplication process. The capacitance constant for the test device is then subtracted from the result of this division process.

Thus, the invention uses an on-chip ring oscillator to provide a high-frequency signal together with a circuit which will allow measurement of the capacitance at very high frequencies using ordinary test probes and equipment. This circuit allows full C-V (capacitance-voltage) characterization, avoiding the weaknesses associated with the use of simple ring-oscillators as a means of capacitance extractions.

DETAILED DESCRIPTION

As mentioned above, the increased use of larger dielectric DC currents requires the use of higher frequency test devices when measuring capacitance in order for the displacement current to significantly exceed the DC leakage current. The invention uses an on-chip ring oscillator to provide a high-frequency signal together with a circuit which will allow measurement of the capacitance at very high frequencies using ordinary test probes and equipment. This circuit allows full C-V characterization, avoiding the weaknesses associated with the use of simple ring-oscillators as a means of capacitance extractions.

FIG. 1is a schematic diagram of one example of the invention embodied in the circuit used for on-chip high-frequency capacitance characterization. While the following embodiment is designed to find the capacitance of a device (such as an ultra-thin gate oxide), the invention can also be used to measure gate length, channel width, flat-band voltage, interconnect capacitance, etc.

The circuit shown in the example inFIG. 1includes a ring oscillator10and an inverter14comprising an P-type transistor11, and a N-type transistor12. The oscillator10is connected to a different power supply (VRO) than the inverter VDD. The ring oscillator10is capable of producing a signal of very high frequency, f, above 100 Mhz (shown in the waveform inFIG. 1) with period “t”. The device under test “DUT” (e.g., the capacitance of the gate oxide in this example) is shown as capacitor40. Transistor11is connected to VDD, while transistor12is connected to VSSand, VSSand VDDcan be chosen (VDD>VSS) to limit the voltage range across the DUT40and thus, make the capacitance measurements at a specific DC bias voltage, which is usually required for complete characterization of the DUT. Furthermore VDDVSSshould be less than the sum of the absolute values of the threshold voltages of the n-type and p-type FETs that make up the inverter.

FIG. 2illustrates waveforms of the ring oscillator “RO”10(at VIN) and to the DUT14(VOUT). To measure the capacitance of the DUT14, knowing that the current drawn in VDD(or VSS) is
I=(VDD−VSS)×f×(Cckt+C),
which is inverted to yield:
C=I/(f×(VDD−VSS))−Ccktwhere I is measured current at VDDusing ammeter16, VDDand VSSare the applied voltages to the circuit inFIG. 1, f is the frequency supplied to VIN(by the ring oscillator), and Cckt represents the incidental capacitance that the test circuit itself adds to the DUT node. To separate Cckt from C, the invention uses a second copy (e.g., a sample, non-testing, standards circuit) of the circuit that is not connected to a DUT to develop a constant for the capacitance of the test circuit Cckt alone. Then, as shown above, the invention simply substitutes this constant for Cckt in the above equation.

This is shown graphically in the waveform diagram inFIG. 2. More specifically,FIG. 2shows that, at each pulse from the ring oscillator from 0 V to VROat VIN, the voltage at VOUTdecreases from VDDto VSS. The capacitance of the DUI is detected from the current drawn by the inverter, I, as shown by the above equation (e.g., I/(VDD−VSS)).

Thus, as shown above, the invention provides an on-chip test device for testing the thickness of gate oxides in transistors. With the invention, a ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide and the inverter receives different voltages as power supplies. The current drawn by the inverter together with the frequency of the signal and the difference between the voltages provides a measurement of capacitance of the gate oxide through the relationship above. The difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator in order to represent a good approximation to the differential capacitance, dQ/dV, of the DUT. Furthermore, the difference between the voltages VDDand VSSshould also be less than the sum of the absolute values of the threshold voltages of the n-type and p-type FETs which make up the inverter in order to ensure that no short-circuit current contributes to the inverter current.

The capacitance of the gate oxide capacitor (or other device being measured) comprises the current drawn by the inverter divided by a multiplication result of the frequency of the ring oscillator output multiplied by the difference between the voltages supplied to the inverter (less the capacitance constant for the testing structure). In other words, the capacitance of the device under test is calculated by multiplying the frequency of the ring oscillator output by the difference between the voltages supplied to the inverter. The current drawn by the inverter is then divided by the result of this multiplication process. The capacitance constant for the test device is then subtracted from the result of this division process. This capacitance constant is for the testing device alone, and does not include any part of the capacitance of the gate oxide capacitor. The measurement of capacitance of the gate oxide capacitor is used to determine the electrical thickness of the gate oxide.

FIG. 3illustrates the inventive method of testing the capacitance of a device under test in an integrated circuit chip. More specifically, this method supplies the output of the ring oscillator300to the inverter302to produce an inverted ring oscillator output304. Again, the inverter receives different voltages as power supplies. The method also inputs the inverted ring oscillator output to the device under test306. The current drawn by the inverter provides a measurement of capacitance of the device under test. Again, the difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator and furthermore is less than the sum of the absolute values of the threshold voltages of the n-type and p-type FETs which make up the inverter. The capacitance of the device under test314is calculated by multiplying the frequency of the ring oscillator output by the difference between the voltages supplied to the inverter (item308). The current drawn by the inverter is then divided by the result of this multiplication process (item310). The capacitance constant for the test device is then subtracted from the result of this division process (item312) to produce the desired capacitance314.

Another embodiment of this invention (shown inFIGS. 4 and 5) provides for similar three-terminal measurement of capacitances. In many three terminal devices40, a capacitance network41–43exists among all three nodes44–46(A–C), represented by the schematic diagram inFIG. 4. For example, it may be desirable to measure only the capacitance CAB, directly between terminals A and B ofFIG. 4. The invention as previously described, if applied to terminals A and B, will measure the combined capacitance of CABadded to the series capacitance combination of CBCand CAB.

To provide for this case, a second inverter50is added to the measurement structure ofFIG. 1, as shown inFIG. 5. This second inverter50receives the same power supply voltages as the first inverter14, however the signal from the second inverter is applied to the “third” terminal, terminal C in this example while terminal B is tied to ground. This allows the capacitance of CAB(capacitor41) to be easily determined because neither capacitor42(CAC) nor capacitor43(CCB) will draw power from the first inverter14by operation of the connections to ground and the second inverter50. Again the average (DC) current drawn by the first inverter14,1, is measured using ammeter16with VDDand VSSapplied to the upper and lower inverter power supply terminals, respectively, and the output of the first inverter14applied to terminal A. As a result, the same signal voltage appears on terminals A and C, ensuring that neither capacitor42(CAC) nor capacitor43(CCB) will draw power from the first inverter14. Thus, the current drawn by the first inverter14is used to determine the capacitance of capacitor42. Because of this arrangement, the current drawn by one inverter provides a measurement of capacitance of one of the terminals while the remaining inverter(s) isolate the current drawn by the first inverter to only that associated with its terminal.

As in the first embodiment of this invention (shown inFIG. 1), the capacitance of the device under test, CAB41, is given by CAB=(I/[f×(VDD−VSS)]) CCKT, where f is the frequency of the ring oscillator, and CCKTis the capacitance of the test structure alone, measured with an identical structure to that ofFIG. 5except with no device under test, and CCKTis calculated by CCKT=IZERO/[f×(VDD−VSS)]. IZEROis the current measured in the inverter of the test structure with no device under test.

As mentioned above, the invention can be used for a number of purposes, such as determining gate length, LGATE. More specifically, gate length may be measured in the same manner, by having a few copies of the inventive circuit, each with a MOSFET of fixed channel width and varying gate length. Then, the invention compares the gate capacitance vs LDESIGN(the design length of the gate of each MOSFET), which can be used to extract Lgate (gate length) in a well known manner. In particular, a linear relationship of LDESIGNversus measured gate capacitance is established through the preceding measurements, and the correlation used to extrapolate to a value of LDESIGN=ΔL, where the gate capacitance is equal to just the edge (or outer fringe) capacitance of the gate. This value ΔL, gives the difference between the design length, LDESIGN, and the physical gate length, LGATE.

Therefore, as shown above, the invention uses an on-chip ring oscillator to provide a high-frequency signal together with a circuit which will allow measurement of the capacitance at very high frequencies using ordinary test probes and equipment. This circuit allows full C-V characterization, avoiding the weaknesses associated with the use of simple ring-oscillators as a means of capacitance extractions.

Advantages of this invention include the ability to perform in-line manufacturing measurements of capacitances with standard equipment. This results in low test costs, short test-time, and regular monitoring of critical manufacturing processes. As a result, improved manufacturing control ultra-thin oxide processes used to fabricate ICs is possible. Thinner dielectrics with high leakage values can be reliably characterized in line, allowing for fabrication of more-advanced structures.