Clock gater with independently programmable delay

An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Provisional App. 61/765,574, filed on Feb. 15, 2013 and U.S. Pat. No. 8,339,166, issued on Dec. 25, 2012, the entire disclosure and contents of which are hereby incorporated by reference.

BACKGROUND

The embodiments described herein relate generally to circuit manufacturing and, more particularly, to clock gaters with a programmable delay.

Integrated circuit devices are typically designed using a combination of computer-automated design techniques and manual design techniques. The portions of the design layout generated by computer-automated tools are commonly referred to as tiles, and the portions of the design layout manually generated by circuit designers are commonly referred to as macros.

In a synchronous digital system, the clock signal is used to define a time reference for the switching of data throughout the system. The clock distribution network (or clock tree, when this network forms a tree) distributes the clock signal(s) from a source point to all the elements that use the same clock. The clock signal is distributed to tiles as well as macros.

For a macro, the clock tree logic is placed and routed by custom design. On the other hand, within a tile it is common for the clock tree to be at least partially designed by computer-automated tools. An automated synthesis tool can generate a tree that starts with the core clock signal (CCLK) and branches to all of the state elements in the tile. As the circuit design progresses, the number of stages in the clock tree generated by the automated synthesis may change. The number of stages in a clock tree is an important parameter in circuit design, because it determines the delay of the clock signal. For example, a clock signal measured at a certain point in the circuit can be delayed in proportion to the number of stages it has to pass through.

The automated generation of clock trees may create complications during the design process. The design of computer generated tiles and the custom macros generally proceed at different rates and in different order. For example, it is common for some tile synthesis operations to occur after the macro designs have been completed. One of these synthesis operations may yield a change in the number of stages in the clock tree. This change in turn may require the manual redesign of the macros to accommodate this change in clock signal delays.

In order to simulate the integrated circuit device operation during the design process, the clock trees in the macros need to be consistent with those in the tiles. Also, consistency is required for the final design. Adjustments to maintain clock delay consistency require significant time and effort, and may need to be repeated several times during the design phase.

BRIEF SUMMARY

Integrated circuits, a method and a computer-readable medium are provided. An embodiment comprises an integrated circuit device comprising first circuitry comprising first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. Each of the first and second clock gaters comprises a programmable delay circuit including a plurality of delay elements, each element imposing a different amount of delay. Each of the first and second clock gaters is operable to receive the clock signal and configurable to distribute the clock signal to the second logic devices through one of the plurality of delay elements. The first clock gater is operable to distribute the clock signal to a first subset of the second logic devices and the second clock gater is operable to distribute the clock signal to a second subset of the second logic devices.

DETAILED DESCRIPTION

The term “embodiments” does not require that all embodiments include the discussed feature, advantage or mode of operation. Alternate embodiments may be devised without departing from the scope of the disclosure, and well-known elements of the disclosure may not be described in detail or may be omitted so as not to obscure the relevant details. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof

Referring toFIG. 1, the embodiments shall be described in the context of an integrated circuit device100. The integrated circuit device100includes tile portions110and macros120. The number of tile portions110and the number of macros120illustrated is for exemplary purposes and may vary. The integrated circuit device100may be a microprocessor, graphics processing unit (GPU), memory device, etc. Exemplary macros120may include, for example, synchronous random access memory (SRAM) array macros, such as instruction caches, data caches, predictor tables, etc. Multiple instances of some of the macros120may be present. The tile portions110are typically designed using an automated circuit synthesis tool, and the macros120are typically designed manually by circuit designers using, for example, computer-aided design (CAD) tools. As part of the automated design process for the tile portions110, a clock tree130is typically generated. In one embodiment, each tile110may have its own clock tree130. Interfaces may be defined between different tiles110or between a macro120in one tile110and another tile110or a macro120in a different tile110.

FIG. 2depicts a model of an exemplary clock tree130. Clock tree130has a number of stages140that start from the core clock signal (CCLK) and branch to the logic elements150in the tile110. Every stage adds an amount of delay to the clock signal as received at the logic elements150. As the design progresses, the number of stages140may change. Hence, the amount of delay imposed by the clock tree130may change throughout the design process.

Returning toFIG. 1, the macros120includes clock gaters160and170. The clock gaters can be configured to introduce a delay that matches the delay provided by clock tree130. In this way, the clock signal received by tile110can be synchronized with clock signals received by macro120. In an embodiment, clock gaters160and170provide a programmable delay that can be changed if the characteristics of the clock tree130change during the design process. Also, once the integrated circuit device100has been manufactured, the individual timings of the macros120may be measured and the delays tuned to optimize performance.

FIG. 3is a simplified diagram of a tile310including macro320. The clock tree330for the tile is represented by a delay element imposing a delay D4. The logic devices380and382(depicted as flip flops, by way of example) of the tile310receive the clock from the clock tree330, and the logic devices390and392of the macro320receive the clock from the clock gater360. In the illustrated embodiment, the clock gater360includes a multiplexer362and a plurality of delay elements364-367. The delay elements364-367each impose a different amount of delay on the clock signal. The delay elements364-367may be implemented using various logic elements, such as shown in the clock tree330ofFIG. 2.

In the example illustrated inFIG. 3, the clock signal received by tile310is delayed by the delay D4of clock tree330. In one embodiment, this may represent4stages in the clock tree330. To synchronize the clock for the macro320with that of the tile310, the multiplexer362is configured to select the delay element367, also corresponding to a delay of D4. For example, the delay element367may have four drivers or inverters in series to create the same delay as the clock tree130. The multiplexer362can be configured, for example, by using a control register of the device or by blowing fuses. During the design phase the blowing of fuses can be simulated. In an actual design, various tests and characterizations can be performed to select the appropriate fuse pattern for the multiplexer362.

The situation illustrated inFIG. 3may represent the configuration of the tile310and the clock tree330at a particular point in the design of a device300. At a later stage in the design cycle, the design of the tile310may have been changed by the automated synthesis tool, such that the delay imposed by the clock tree330changes to, for example, D1. To synchronize the clock for the macro320with that of the tile310, the multiplexer362can be configured to select the delay element364, which corresponds to a delay of D1.

In this manner, changes in the design of the tile310that affect the timing may be addressed simply by reconfiguring the multiplexer362, thereby avoiding a redesign of the macro320. This results in increased efficiency and decreased design costs. The programmable clock gater360obviates need to redesign macro320prior to allowing the simulation testing of device300to proceed after a change in clock tree330. Furthermore, the need for designer input is also obviated, resulting in decreased engineering costs. Further design iterations can be accounted for simply by reconfiguring the multiplexer362to select the delay element364-367corresponding to the delay imposed by the clock tree330. The number of delay elements364-367provided in the clock gater360may vary depending on the degree of granularity desired for timing changes.

FIG. 4depicts a device400including a tile410with two instances of the same macro420a,420b, according to an embodiment. In the example shown, macros420aand420binclude an input logic device490(a flip flop, by way of example) and an output logic device492(also a flip flop, by way of example). Both the input and the output logic devices receive the clock signal from clock gater460.

During the design phase, timing testing may be implemented for the design using simulation tools. Assume the clock tree430of the tile410has a delay of D3. Initially, the multiplexers462for the macros420a,420bwould both be configured to select the delay element466(i.e., D3) to synchronize the tile410and the macros420aand420b.

However, during the timing simulation for the device400, it may be determined that the input signals to the macro420aare on the critical timing path, while the outputs are not. Signals in the critical timing path may be delayed more than other signals, and may arrive towards the end of a clock cycle. In order to prevent a switch of flip flop490before the input signal arrives, the programmable delay of the clock gater460of macro420acan be increased by configuring the multiplexer462to select a longer delay element467(i.e., D4). The longer delay allows more time for input signals to set up.

In contrast, consider that the timing simulation also revealed that the output signals of macro420bare on the critical timing path. In order to prevent a switch of the logic device480that reads these output signals, the programmable delay of the clock gater460for the macro420bcan be decreased by configuring the multiplexer462to select a shorter delay element465(i.e., D2). The shorter delay allows the output signals to be generated slightly earlier, and allows them to be correctly read by logic device482before its clock edge.

The previous example ofFIG. 4shows the tuning of macro clock signal delay, while running timing simulation on the tile410. However, the longest timing paths in timing analysis may not correspond to the longest timing paths when the device400is actually fabricated. Hence, once the design of the integrated circuit device is completed, and the device400has been fabricated, the clock gaters460for one or more macros420may be tuned to increase the actual performance of the device by further adjusting the macro interface timing.

There may be instances in which tuning the clock signal delay may be difficult, particularly when both the input and the output of a macro are part of the critical timing path. In such a scenario, increasing the clock signal delay may allow the input signal more time to set up correctly before the clock edge, but may result in the output signal not being generated with enough time to be correctly read before the next clock edge. Conversely, decreasing the clock signal delay may allow the output signal to be timely generated, but the input signal may not be properly set before being read. An approach to prevent this issue from affecting performance is to multiple clock gaters within a macro to allow for more precise tuning of the clock delays.

FIG. 5depicts a device500including a macro with multiple clock gaters, according to an embodiment. In the example shown, device500inFIG. 5includes a tile510and a macro520. Macro520comprises clock gaters560and570, which provide clock signals to input logic device590and output logic device592, respectively. Input logic device580reads the input signal to the macro from logic device580, while output logic device582outputs the output signal from the macro to logic device582.

If the timing simulation reveals that the input received at input logic device590is part of the critical timing path, the control signals to clock gater multiplexer562can be configured apply a longer delay to the clock signal, for example, delay D4. If the timing simulation also reveals that the output generated by output logic device582is part of the critical timing path, the control signals to multiplexer572can be configured to apply a shorter delay to the clock signal, for example, delay D1. This avoids the complication of having to find a single intermediate delay that will avoid untimely clock edges at both the input and output.

As previously mentioned, the longest timing paths in timing analysis may not correspond to the longest timing paths when the device is actually fabricated. Once the design of the integrated circuit device is completed, and the device500has been fabricated, the clock gaters560and570for one or more macros520may be tuned to increase the actual performance of the device by further adjusting the macro interface timing.

FIG. 6depicts a device600including a macro with multiple clock gaters in a scenario where the internal logic of the macro is part of the critical timing path, according to an embodiment. In the example shown, device600inFIG. 6includes a tile610and a macro620. Macro620comprises internal logic640that can include state logic. Although discussion of the macros' internal logic has been omitted from the devices in the previous figures, it should be understood the macros can contain internal logic including state elements.

In the example shown, macro620further includes clock gaters660and670, which provide clock signals to input logic device690and output logic device692, respectively. Input logic device680reads the input signal to the macro from logic device680, while output logic device682outputs the output signal from the macro to logic device682.

In the example depicted inFIG. 6, the timing simulation reveals the internal logic640is part of the critical timing path, while the input and output paths are not. In this scenario, clock gater multiplexer662can be configured to apply a shorter delay, for example delay D1, while clock gater multiplexer672can be configured to apply a longer delay, for example delay D4. This provides the input signal to internal logic640earlier and allows more time for the output signal to the internal logic640to be properly set.

As previously mentioned, the longest timing paths in timing analysis may not correspond to the longest timing paths when the device is actually fabricated. Once the design of the integrated circuit device is completed, and the device600has been fabricated, the clock gaters660and670for one or more macros620may be tuned to increase the actual performance of the device by further adjusting the macro's internal timing.

Although the examples ofFIGS. 3-6illustrate timing interfaces between a macro and the tile in which it is formed, it is contemplated that the timing interface may be defined between the macro and a different tile in the case where multiple tiles are present in the integrated circuit device.

FIG. 7illustrates a simplified diagram of selected portions of the hardware and software architecture of a computing apparatus700such as may be employed in some aspects of the present subject matter. The computing apparatus700includes a processor705communicating with storage710over a bus system715. The storage710may include a hard disk and/or random access memory (“RAM”) and/or removable storage, such as a magnetic disk720or an optical disk725. The storage710is also encoded with an operating system730, user interface software735, and an application765. The user interface software735, in conjunction with a display740, implements a user interface745. The user interface745may include peripheral I/O devices such as a keypad or keyboard750, mouse755, etc. The processor705runs under the control of the operating system730, which may be practically any operating system known in the art. The application765is invoked by the operating system730upon power up, reset, user interaction, etc., depending on the implementation of the operating system730. The application765, when invoked, performs a method of the present subject matter. The user may invoke the application765in conventional fashion through the user interface745. Note that although a stand-alone system is illustrated, there is no need for the data to reside on the same, computing apparatus700as the application765by which it is processed. Some embodiments of the present subject matter may therefore be implemented on a distributed computing system with distributed storage and/or processing capabilities.

It is contemplated that, in some embodiments, different kinds of hardware descriptive languages (HDL) may be used in the process of designing and manufacturing very large scale integration circuits (VLSI circuits), such as semiconductor products and devices and/or other types semiconductor devices. Some examples of HDL are VHDL and Verilog/Verilog-XL, but other HDL formats not listed may be used. In one embodiment, the HDL code (e.g., register transfer level (RTL) code/data) may be used to generate GDS data, GDSII data and the like. GDSII data, for example, is a descriptive file format and may be used in different embodiments to represent a three-dimensional model of a semiconductor product or device. Such models may be used by semiconductor manufacturing facilities to create semiconductor products and/or devices. The GDSII data may be stored as a database or other program storage structure. This data may also be stored on a computer readable storage device (e.g., storage710, disks720,725, solid state storage, and the like). In one embodiment, the GDSII data (or other similar data) may be adapted to configure a manufacturing facility (e.g., through the use of mask works) to create devices capable of embodying various aspects of the instant invention. In other words, in various embodiments, this GDSII data (or other similar data) may be programmed into the computing apparatus700, and executed by the processor705using the application765, which may then control, in whole or part, the operation of a semiconductor manufacturing facility (or fab) to create semiconductor products and devices. For example, in one embodiment, silicon wafers containing the tiles, macros, clock gaters disclosed herein may be created using the GDSII data (or other similar data).

It is also contemplated that the computing apparatus700and the application765may be used to perform performance modeling of an integrated circuit device according to an embodiment. For example, a timing analysis of the tiles and macros may be performed as described above to identify critical timing paths and adjust the clock gaters accordingly.