INTEGRATED CIRCUIT DEVICE

An integrated circuit device includes a conductive region disposed on a substrate, an insulating structure including a contact hole disposed in the conductive region and extending from the conductive region in a vertical direction, a local capping pattern having an outer sidewall in contact with an upper portion of an inner wall of the contact hole and an inner sidewall facing an inside of the contact hole and having a width gradually increasing in a horizontal direction away from the substrate, and a conductive plug passing through the insulating structure through the contact hole in the vertical direction, having a lower sidewall in contact with the insulating structure and an upper sidewall in contact with the local capping pattern, and including a first metal.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0175211, filed on Dec. 8, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to an integrated circuit (IC) device.

2. Description of the Related Art

Due to the development of electronics technology, IC devices have been rapidly downscaled, and accordingly, line widths and pitches of metal wiring layers included in IC devices have also been reduced.

SUMMARY

An embodiment is directed to an integrated circuit device including a conductive region disposed on a substrate, an insulating structure including a contact hole disposed on the conductive region and extending from the conductive region in a vertical direction, a local capping pattern having an outer sidewall in contact with an upper portion of an inner wall of the contact hole and an inner sidewall facing an inside of the contact hole and having a width gradually increasing in a horizontal direction, away from the substrate, and a conductive plug passing through the insulating structure through the contact hole in the vertical direction, having a lower sidewall in contact with the insulating structure and an upper sidewall in contact with the local capping pattern, and including a first metal.

An embodiment is directed to an integrated circuit device including a source/drain region disposed on a substrate and a recess surface on an upper surface thereof, a metal silicide layer disposed on the recess surface of the source/drain region and including a first metal, an insulating structure including a contact hole disposed on the metal silicide layer and extending from the metal silicide layer in a vertical direction, a local capping pattern having an outer sidewall in contact with an upper portion of an inner wall of the contact hole away from the substrate and an inner sidewall facing an inside of the contact hole, and having a width gradually increasing in a horizontal direction, away from the substrate, and a conductive plug passing through the insulating structure through the contact hole in the vertical direction, having a lower sidewall in contact with the insulating structure and an upper sidewall in contact with the local capping pattern, and including a second metal that is different from the first metal.

An embodiment is directed to an integrated circuit device including a fin-type active region protruding from a substrate, a source/drain region disposed in the fin-type active region, a metal silicide layer in contact with an upper surface of the source/drain region, a gate line extending from the fin-type active region in a direction intersecting the fin-type active region, an insulating structure disposed in the source/drain region, the metal silicide layer, and the gate line, a source/drain contact structure passing through a first portion of the insulating structure and connected to the source/drain region through the metal silicide layer, and a gate contact structure passing through a second portion of the insulating structure in a vertical direction and configured to be connected to the gate line, wherein at least one of the source/drain contact structure and the gate contact structure includes a local capping pattern having an outer sidewall in contact with an upper portion of an inner wall of a contact hole formed in the insulating structure and an inner sidewall facing an inside of the contact hole and having a width gradually increasing in a horizontal direction, away from the substrate and a conductive plug passing through the insulating structure through the contact hole in a vertical direction, having a lower sidewall in contact with the insulating structure and an upper sidewall in contact the local capping pattern, and including a first metal.

DETAILED DESCRIPTION

FIG.1is a plan layout diagram illustrating an integrated circuit (IC) device100according to example embodiments.FIG.2Ais a cross-sectional view showing a partial configuration of a cross-section taken along line X1-X1′ and a cross-section taken along line X2-X2′ ofFIG.1,FIG.2Bis a cross-sectional view showing a partial configuration of a cross-section taken along line Y1-Y1′ ofFIG.1,FIG.2Cis an enlarged cross-sectional view of a portion EX1inFIG.2A, andFIG.2Dis an enlarged cross-sectional view of a portion EX2inFIG.2B.

Referring toFIGS.1and2A to2D, the IC device100may constitute a logic cell including a fin field effect transistor (FinFET) device. The IC device100may include a logic cell LC formed in a region defined by a cell boundary BN on a substrate110.

The substrate110may have a main surface110M extending in a horizontal direction (X-Y plane direction). The substrate110may include an elemental semiconductor, such as Si or Ge, or a compound semiconductor, such as SiGe, SiC, GaAs, InAs, or InP. The substrate110may include a conductive region, e.g., a well that is doped with an impurity or a structure that is doped with an impurity.

The logic cell LC may include a first device region RX1and a second device region RX2. Fin-type active regions FA protruding from the substrate110may be disposed in the first device region RX1and the second device region RX2, respectively. The fin-type active regions FA may extend parallel to each other in a width direction of the logic cell LC, that is, in a first horizontal direction (an X direction).

Referring toFIG.2B, a device separation layer112may be disposed in the first device region RX1and the second device region RX2on the substrate110. The device separation layer112may be disposed between each of the fin-type active regions FA, and may cover a lower sidewall of the fin-type active region FA. In the first device region RX1and the second device region RX2, the fin-type active regions FA may protrude in a fin shape over the device separation layer112. An inter-device separation region DTA may be disposed between the first device region RX1and the second device region RX2. A deep trench DT defining the first device region RX1and the second device region RX2may be formed in the device separation region DTA, and the deep trench DT may be filled with an inter-device separation insulating layer114. The device separation layer112and the inter-device separation insulating layer114may each include an oxide layer.

On the substrate110, a plurality of gate insulating layers132and a plurality of gate lines GL may extend in a height direction of the logic cell LC inFIG.1, i.e., in a second horizontal direction (a Y direction), intersecting with the fin-type active regions FA. The gate insulating layers132and the gate lines GL may cover a top surface and both sidewalls of each of the fin-type active regions FA, an upper surface of the device separation layer112, and a top surface of the inter-device separation insulating layer114.

A plurality of MOS transistors may be formed along the gate lines GL in the first device region RX1and the second device region RX2. Each of the MOS transistors may be a MOS transistor having a three-dimensional (3D) structure in which channels are formed on the top surface and both sidewalls of the fin-type active regions FA. In example embodiments, the first device region RX1may be an NMOS transistor region, and a plurality of NMOS transistors may be formed in portions in which the fin-type active region FA and the gate line GL intersect each other in the first device region RX1. The second device region RX2may be a PMOS transistor region, and a plurality of PMOS transistors may be formed in portions in which the fin-type active region FA intersects with the gate line GL in the second device region RX2.

Referring toFIG.1, a dummy gate line DGL may extend along a portion of the cell boundary BN extending in the second horizontal direction (the Y direction). The dummy gate line DGL may be formed of the same material as that of the gate lines GL. The dummy gate line DGL may maintain an electrically floating state during the operation of the IC device100, thereby functioning as an electrical separation region between the logic cell LC and other logic cells surrounding the logic cell LC. The gate lines GL and the dummy gate lines DGL may each have the same width in the first horizontal direction (the X direction) and may be arranged at a constant pitch in the first horizontal direction (the X direction).

The gate insulating layers132may include a silicon oxide layer, a high-k layer, or a combination thereof. The high-k layer may be formed of a material having a higher dielectric constant than that of the silicon oxide layer. The high-k layer may be formed of a metal oxide or a metal oxynitride. An interface layer (not shown) may be interposed between the fin-type active region FA and the gate insulating layer132. The interface layer may include an oxide layer, a nitride layer, or an oxynitride layer.

Each of the gate lines GL and the dummy gate lines DGL may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are sequentially stacked. The metal nitride layer and the metal layer may include at least selected from titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), and hafnium (Hf). The gap-fill metal layer may include a W layer or an Al layer. Each of the gate lines GL and the dummy gate lines DGL may include a work function metal-containing layer. The work function metal-containing layer may include at least one metal selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). In example embodiments, the gate lines GL and the dummy gate lines DGL may each include a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/W, for example.

A plurality of insulating spacers120may cover both sidewalls of the gate lines GL and the dummy gate lines DGL. The gate lines GL, the dummy gate lines DGL, the gate insulating layers132, and the insulating spacers120may be covered with a plurality of insulating capping lines140. The insulating capping lines140and the insulating spacers120may each extend in a line shape in the second horizontal direction (the Y direction).

Each of the insulating spacers120may be formed of silicon nitride (SiN), SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, for example. The insulating capping lines140may be formed of SiN. As used herein, the terms “SiN”, “SiCN”, “SiBN”, “SiON”, “SiOCN”, and “SiBCN” refer to a material including elements included in each term, and is not a chemical formula that indicates a stoichiometric relationship.

A plurality of recess regions RR may be formed in top surfaces of the fin-type active regions FA. The gate lines GL may include a pair of gate lines GL disposed adjacent to one recess region RR and apart from each other with the one recess region RR therebetween. A plurality of source/drain regions130may be disposed in the recess regions RR. The source/drain regions130may include a source/drain region130interposed between a pair of gate lines GL. The gate line GL and the source/drain region130may be apart from each other with the gate insulating layer132and the insulating spacer120therebetween.

The source/drain regions130may include epitaxial semiconductor layers that are epitaxially grown from the recess regions RR. For example, the source/drain regions130may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the first device region RX1is an NMOS transistor region and the second device region RX2is a PMOS transistor region, the source/drain regions130in the first device region RX1may be formed of an n-type dopant or include a SiC layer doped with an n-type dopant, and the source/drain regions130in the second device region RX2may include a SiGe layer doped with a p-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). The p-type dopant may be selected from boron (B) and gallium (Ga).

In example embodiments, the source/drain regions130in the first device region RX1and the source/drain regions130in the second device region RX2may have different shapes and sizes. The shape of each of the source/drain regions130may be varied from those illustrated inFIGS.2A and2C, and source/drain regions130having various shapes and sizes may be formed in the first device region RX1and the second device region RX2.

Referring toFIG.2C, each of the source/drain regions130may have a recess surface130R on a top surface thereof. A plurality of metal silicide layers152may be disposed on the recess surface130R of each of the source/drain regions130. The metal silicide layers152may cover top surfaces of the source/drain regions130, respectively. The source/drain regions130and the metal silicide layers152may constitute conductive regions, respectively.

Each of the metal silicide layers152may include a first metal. In example embodiments, the first metal may be Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide layer152may be formed of titanium silicide.

An insulating liner146and an inter-gate insulating layer148may be sequentially disposed on the source/drain regions130and the metal silicide layers152. The insulating liner146and the inter-gate insulating layer148may constitute a lower insulating structure. In example embodiments, the insulating liner146may be formed of, e.g., silicon nitride (SiN), SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof. The inter-gate insulating layer148may include a silicon oxide layer, for example.

The IC device100may include a plurality of the insulating capping lines140, the insulating liner146, and an insulating layer149covering a top surface of each of the inter-gate insulating layers148. In example embodiments, the insulating layer149may include a silicon oxide layer, for example.

The insulating capping lines140, the insulating liner146, and the inter-gate insulating layer148may constitute an insulating structure. A plurality of source/drain contact holes CAH may be formed in the metal silicide layer152and extending from the metal silicide layer152in a vertical direction (a Z direction). The source/drain contact holes CAH may pass through the insulating layer149, the inter-gate insulating layer148, and the insulating liner146of the insulating structure in the vertical direction (the Z direction).

The source/drain contact holes CAH may be filled with a plurality of source/drain contact structures CA. Each of the source/drain contact structures CA may be configured to pass through the insulating layer149, the inter-gate insulating layer148, and the insulating liner146in the vertical direction (the Z direction) to be connected to the source/drain region130through the metal silicide layer152. Each of the source/drain contact structures CA may be apart from the gate line GL in the first horizontal direction (the X direction) with at least a portion of the insulating spacer120and the inter-gate insulating layer148therebetween. Each of the source/drain regions130may be connected to an upper conductive line through the metal silicide layer152and the source/drain contact structure CA.

Each of the source/drain contact structures CA may include a local capping pattern154and a conductive plug156in the source/drain contact hole CAH.

The local capping pattern154may be disposed concentrically with the conductive plug156, and may have a ring shape surrounding an upper end of the conductive plug156when viewed in a plan view (e.g., an X-Y plane). An outer sidewall of the local capping pattern154may contact an upper portion of the inner wall of the source/drain contact hole CAH, which is relatively far from the substrate110. An inner sidewall of the local capping pattern154may face the inside of the source/drain contact hole CAH, and may contact the upper end of the conductive plug156. The local capping pattern154may have a width gradually increasing in a horizontal direction (e.g., the X-direction and the Y-direction) away from the substrate110.

Referring toFIGS.2A and2C, the conductive plug156may pass through the insulating layer149, the inter-gate insulating layer148, and the insulating liner146through the source/drain contact hole CAH in the vertical direction (the Z direction). A lower sidewall SW1of the conductive plug156that is relatively close to the substrate110may contact at least a portion of the insulating layer149, the inter-gate insulating layer148, and the insulating liner146. An upper sidewall SW2of the conductive plug156that is relatively far from the substrate110may contact the local capping pattern154. A top surface of the local capping pattern154, a top surface of the conductive plug156, and a top surface of the insulating layer149may extend in a horizontal direction on the same plane.

The upper sidewall SW2of the conductive plug156may include an inclined surface that is inclined horizontally away from the insulating structure including the insulating layer149, the inter-gate insulating layer148, and the insulating liner146in a direction away from the substrate110. Accordingly, a width of an upper portion of the conductive plug156, defined by the upper sidewall SW2of the conductive plug156, may gradually decrease in the horizontal direction (e.g., the X and Y directions) in a direction away from the substrate110.

The local capping pattern154may include a silicon-containing insulating layer, a metal nitride layer, a metal oxynitride layer, an insulating layer doped with a metal or metal-doped insulating layer, or a combination thereof. In example embodiments, the local capping pattern154may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiCN) layer, a silicon oxycarbonitride (SiOCN) layer, a boron-containing silicon nitride (SiBN) layer, a titanium oxynitride (TiON) layer, TiN, TaN, a Ti-doped silicon oxide layer, a Ti-doped silicon nitride layer, or a combination thereof. However, a constituent material of the local capping pattern154may be varied.

In example embodiments, the local capping pattern154may be formed of the same material as that of at least a portion of the insulating structure that includes the insulating layer149, the inter-gate insulating layer148, and the insulating liner146. For example, the local capping pattern154, the inter-gate insulating layer148, and the insulating layer149may each include a silicon oxide layer, and the local capping pattern154may include a portion in contact with at least one of the inter-gate insulating layer148and the insulating layer149.

Referring toFIG.2C, in the vertical direction (the Z direction), a first length L11of the local capping pattern154may be about 30% to about 50% of a second length L12of the source/drain contact hole CAH. In example embodiments, the first length L11may be less than about 50% of the second length L12. For example, in the vertical direction (the Z direction), the first length L11may be greater than about 30% and less than about 50% of the second length L12.

In forming the conductive plug156, as a length (i.e., a length obtained by subtracting the first length L11from the second length L12) of a portion of the inner sidewall of the source/drain contact hole CAH that is not covered with the local capping pattern154in a vertical direction (the Z direction) increases, a nucleation delay effect may increase at the exposed surfaces of the insulating layers that are exposed from inner sidewalls of the source/drain contact hole CAH (for example, the exposed surfaces of the insulating liner146and the inter-gate insulating layer148), which may be advantageous for forming the conductive plug156in a bottom-up filling manner. When the local capping pattern154includes a metal, adhesion between the local capping pattern154and the conductive plug156may be improved.

In example embodiments, the local capping pattern154and the conductive plug156may each include a metal, and the metal included in the local capping pattern154may be different from the metal included in the conductive plug156. For example, the metal included in the local capping pattern154may be formed of titanium (Ti), tantalum (Ta), or a combination thereof, and the metal included in the conductive plug156may be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), or a combination thereof.

The conductive plug156may have a surface in contact with the metal silicide layer152, a surface in contact with the insulating liner146and the inter-gate insulating layer148, and a surface in contact with the local capping pattern154.

In example embodiments, the conductive plug156, the metal silicide layer152, and the local capping pattern154may each include different metals. In other example embodiments, at least some of the conductive plug156, the metal silicide layer152, and the local capping pattern154may include the same metal. For example, each of the metal silicide layer152and the local capping pattern154may include a first metal, and the conductive plug156may not include the first metal.

Referring toFIGS.2A and2B, the top surface of each of the insulating layer149and the source/drain contact structures CA may be covered with an upper insulating structure180. The upper insulating structure180may include an etch stop layer182and an interlayer insulating layer184sequentially stacked on the source/drain contact structures CA and the insulating layer149. The etch stop layer182may be formed of silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating layer184may include an oxide layer, a nitride layer, an ultra low-k (ULK) layer having an ultra low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating layer184may include a tetraethylorthosilicate (TEOS) film, a high density plasma (HDP) oxide layer, a boro-phospho-silicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, an SiON layer, a SiN layer, a SiCOH layer, or a combination thereof.

A plurality of upper contact holes CAVH extending in the vertical direction (the Z direction) through the upper insulating structure180may be formed in the upper insulating structure180. A plurality of via contacts CAV may be respectively disposed in the plurality of upper contact holes CAVH. Each of the via contacts CAV may contact the conductive plug156of the source/drain contact structure CA. The via contacts CAV may constitute an upper wiring structure.

The via contacts CAV may include a metal. In example embodiments, the via contacts CAV may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, etc. For example, the via contacts CAV may be formed of Mo.

The metal included in the via contacts CAV may be formed of the same metal element as the metal included in the conductive plug156. For example, each of the plurality of conductive plugs156and the via contacts CAV may include Mo. In other example embodiments, a metal included in the via contacts CAV and a metal included in the conductive plug156may be formed of different metal elements.

In example embodiments, a bottom surface of each of the via contacts CAV may contact a top surface of the conductive plug156. Each of the via contacts CAV may be formed of an upper conductive plug directly in contact with the conductive plug156without passing through a separate conductive barrier layer. When the via contact CAV and the conductive plug156are formed of the same metal, an intermixing phenomenon (which may occur between metal elements thereof) may not affect electrical characteristics of the IC device100. Therefore, a separate conductive barrier layer for blocking the intermixing may not be provided between the conductive plug156and the via contact CAV.

Referring toFIGS.1and2B, a plurality of gate contact structures CB may be disposed on the gate lines GL. The gate contact structures CB may each be disposed in the gate contact hole CBH passing through the upper insulating structure180, the insulating layer149, and the insulating capping line140. The gate contact structures CB may be disposed on the gate line GL, and may contact a top surface of at least one metal layer constituting the gate line GL. The gate lines GL may be connected to an upper conductive line through the gate contact structure CB.

Referring toFIGS.2B and2D, each of the gate contact structures CB may include a local capping pattern194and a conductive plug196in the gate contact hole CBH. The local capping pattern194may have an outer sidewall contacting an upper portion of an inner wall of the gate contact hole CBH and an inner sidewall facing the inside of the gate contact hole CBH, and may have a width gradually increasing in a horizontal direction, away from the substrate110. The conductive plug196may pass through the insulating structure including the upper insulating structure180, the insulating layer149, and the insulating capping line140in a vertical direction (the Z direction) through the gate contact hole CBH. A lower sidewall of the conductive plug196may contact at least a portion of the insulating structure, e.g., the upper insulating structure180and the insulating layer149. An upper sidewall of the conductive plug196may contact the local capping pattern194. A top surface of the local capping pattern194, a top surface of the conductive plug196, and a top surface of the upper insulating structure180may extend in a horizontal direction on the same plane.

Referring toFIG.2D, in the vertical direction (the Z direction), a first length L21of the local capping pattern194may be about 30% to about 50% of a second length L22of the gate contact hole CBH. In example embodiments, the first length L21may be less than about 50% of the second length L22. For example, in the vertical direction (the Z direction), the first length L21may be greater than about 30% and less than about 50% of the second length L22.

A more detailed configuration of the local capping pattern194and the conductive plug196is substantially the same as that described above for the local capping pattern154and the conductive plug156included in the source/drain contact structure CA.

Referring toFIG.1, in the logic cell LC, a ground line VSS may be connected to the fin-type active region FA of the first device region RX1through the source/drain contact structure CA in the first device region RX1, among the source/drain contact structures CA. A power line VDD may be connected to the fin-type active region FA of the second device region RX2through the source/drain contact structure CA in the second device region RX2, among the source/drain contact structures CA. The ground line VSS and the power line VDD may be formed at a level higher than the top surface of each of the source/drain contact structures CA and the gate contact structures CB.

In example embodiments, the ground line VSS and the power line VDD may be formed of a local capping pattern for wiring and a conductive plug for wiring, respectively. The local capping pattern for wiring and the conductive plug for wiring respectively included in the ground line VSS and the power line VDD may have substantially the same configuration as that described above with respect to the local capping pattern154and the conductive plug156included in the source/drain contact structure CA.

In the IC device100illustrated inFIGS.1and2A to2D, the source/drain contact structures CA include the local capping pattern154and the conductive plug156, and the gate contact structure CB includes the local capping pattern194and the conductive plug196. The local capping patterns154and194surround outer sidewalls of the upper ends of the conductive plugs156and196and have a shape having a width gradually increasing in a horizontal direction away from the substrate110, and thus, the local capping patterns154and194physically fix the conductive plugs156and196so that at least a portion of the conductive plugs156and196may not escape from a contact hole (e.g., the source/drain contact hole CAH or the gate contact hole CBH) during a manufacturing process of the IC device100.

In particular, when the local capping patterns154and194include a metal, adhesion between the local capping patterns154and194and the conductive plugs156and196may be improved at a contact portion thereof, so that the effect of physically fixing the conductive plugs156and196by the local capping patterns154and194may be further improved. Also, when formed of an insulating material or a dielectric material, the local capping patterns154and194may provide a structure advantageous for securing an insulating distance between the conductive plugs156and196and a conductive region adjacent thereto, e.g., between the conductive plug156of the source/drain contact structure CA and the gate line GL adjacent thereto, compared to a case in which the local capping patterns154and194are formed of a conductive material.

In addition, without a separate barrier layer having a resistance, which is greater than that of the conductive plugs156and196, between an insulating structure adjacent to the conductive plugs156and196, i.e., an insulating structure including the insulating capping line140, the insulating liner146, the inter-gate insulating layer148, and the insulating layer149, and the conductive plugs156and196, a lower sidewall of each of the conductive plugs156and196is in contact with the insulating structure. Accordingly, even when the IC device100has a device region having a reduced area due to down-scaling, the electrical characteristics and reliability of the IC device100may be improved, while contact resistance in each of the source/drain contact structure CA and the gate contact structure CB is reduced.

FIG.2Eis a cross-sectional view illustrating an IC device100A according to other example embodiments.FIG.2Eillustrates a cross-sectional configuration of a region corresponding to the portion EX2inFIG.2B.

Referring toFIG.2E, the IC device100A may have substantially the same configuration as that of the IC device100described above with reference toFIGS.1and2A to2D. However, the IC device100A may include an upper insulating structure180A, instead of the upper insulating structure180, and may include a gate contact structure CB2, instead of the gate contact structure CB.

The upper insulating structure180A may include an etch stop layer182and an interlayer insulating layer184A sequentially stacked on the insulating layer149. The gate contact structure CB2may be disposed in a gate contact hole CBHA passing through the upper insulating structure180A, the insulating layer149, and the insulating capping line140.

The gate contact structure CB2may include a local capping pattern194A and a conductive plug196in the gate contact hole CBHA. The local capping pattern194A may have an outer sidewall in contact with an upper portion of an inner wall of the gate contact hole CBHA and an inner sidewall facing the inside of the gate contact hole CBHA, and may have a width gradually increasing in a horizontal direction, away from the gate line GL.

The interlayer insulating layer184A of the upper insulating structure180A may include a round corner portion defining an upper portion of an entrance side of the gate contact hole CBHA. The local capping pattern194A may have substantially the same configuration as that of the local capping pattern194described above with reference toFIGS.2B and2C. However, the local capping pattern194A may be in contact with the round corner portion of the interlayer insulating layer184A and may have an upper edge portion AR protruding in a radial direction away from the conductive plug196in a horizontal direction to correspond to a shape of the round corner portion.

In the IC device100A, the round corner portion of the interlayer insulating layer184A may be formed during a process of forming the gate contact hole CBHA. As the local capping pattern194A is formed to be in contact with the round corner portion of the interlayer insulating layer184A, the local capping pattern194A may include the upper edge portion AR protruding in a radial direction away from the conductive plug196in a horizontal direction, as shown inFIG.2E.

FIG.3is a cross-sectional view illustrating an IC device200according to still other example embodiments.FIG.3illustrates a cross-sectional configuration of the IC device200showing regions corresponding to a cross-section taken along line X1-X1′ and a cross-section taken along line X2-X2′ ofFIG.1. InFIG.3, the same reference numerals as those ofFIGS.2A to2Cdenote the same members, and redundant descriptions thereof are omitted herein.

Referring toFIG.3, the IC device200may have substantially the same configuration as that of the IC device100described above with reference toFIGS.1and2A to2D. However, the IC device200includes a plurality of via contacts CAV2, instead of the via contacts CAV.

The via contacts CAV2may each pass through the upper insulating structure180, and may contact the conductive plug156of the source/drain contact structure CA. The via contacts CAV2may constitute an upper wiring structure.

The via contacts CAV2may include a local capping pattern274and a conductive plug276in the upper contact hole CAVH. In an example embodiment, the local capping pattern274may be referred to as an upper local capping pattern, and the conductive plug276may be referred to as an upper conductive plug.

The local capping pattern274may have an outer sidewall contacting an upper portion of an inner wall of the upper contact hole CAVH and an inner sidewall facing the inside of the upper contact hole CAVH, and may have a width gradually increasing in a horizontal direction, away from the substrate110. The conductive plug276may pass through the insulating structure including the upper insulating structure180in a vertical direction (the Z direction) through the upper contact hole CAVH. A lower sidewall of the conductive plug276may contact at least a portion of the insulating structure, e.g., the etch stop layer182and the interlayer insulating layer184. An upper sidewall of the conductive plug276may contact the local capping pattern274. A top surface of the local capping pattern274, a top surface of the conductive plug276, and a top surface of the upper insulating structure180may extend in a horizontal direction on the same plane. Detailed configurations and effects of the local capping pattern274and the conductive plug276are substantially the same as those described above for the local capping pattern154and the conductive plug156with reference toFIGS.2A and2C.

FIG.4is a cross-sectional view illustrating main components of an IC device300A according to still other example embodiments.

Referring toFIG.4, the IC device300A may include a lower structure310. The lower structure310may include a semiconductor substrate formed of an elemental semiconductor, such as Si or Ge, or a compound semiconductor, such as SiGe, SiC, GaAs, InAs, or InP. The lower structure310may include a conductive region (not shown). The conductive region may include a well that is doped with impurities, a structure that is doped with impurities, or a conductive layer. In example embodiments, the lower structure310may include circuit elements (not shown), such as a gate structure, an impurity region, and a contact plug. For example, the lower structure310may include the structures described for the IC device100with reference toFIGS.2A to2Cor the structures described for the IC device200with reference toFIG.3.

A lower wiring structure320may be disposed on the lower structure310. The lower wiring structure320may contact the lower structure310through the first etch stop layer312and the lower insulating layer314sequentially stacked on the lower structure310.

The first etch stop layer312may be formed of a material having an etch selectivity different from that of the lower insulating layer314. In example embodiments, the first etch stop layer312may include a silicon nitride layer, a carbon-doped silicon nitride layer, or a carbon-doped silicon oxynitride layer. In other example embodiments, the first etch stop layer312may include a metal nitride layer, e.g., an AlN layer.

In example embodiments, the lower insulating layer314may include a silicon oxide layer. For example, the lower insulating layer314may be formed of a silicon oxide-based material such as plasma enhanced oxide (PEOX), tetraethyl orthosilicate (TEOS), boro TEOS (BTEOS), phosphorous TEOS (PTEOS), boro phospho TEOS (BPTEOS), boro silicate glass (BSG), phospho silicate glass (PSG), boro phospho silicate glass (BPSG), etc. In other example embodiments, the lower insulating layer314may include a low dielectric film having a low dielectric constant K of about 2.2 to about 3.0, e.g., a SiOC film or a SiCOH film.

The lower wiring structure320may include a metal layer and a conductive barrier layer surrounding the metal layer. The metal layer may be formed of Mo, Cu, W, Al, or Co. The conductive barrier layer may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof. In example embodiments, the lower wiring structure320may be electrically connected to a conductive region formed in the lower structure310. In other example embodiments, the lower wiring structure320may be connected to a source/drain region (not shown) or a gate electrode (not shown) of a transistor formed in the lower structure310.

A second etch stop layer322and a first insulating layer324may be sequentially disposed on the lower insulating layer314. A first metal wiring structure ML1may extend to the lower wiring structure320through an insulating structure including the first insulating layer324and the second etch stop layer322.

The first metal wiring structure ML1may include a local capping pattern334and a lower conductive line336in the lower contact hole CH1. The lower conductive line336of the first metal wiring structure ML1may include a plug shape portion adjacent to the lower wiring structure320, and a line shape portion integrally connected to plug shape portion and spaced apart from the lower local capping pattern334with the plug shape portion therebetween.

The local capping pattern334of the first metal wiring structure ML1may have an outer sidewall contacting an upper portion of an inner wall of the lower contact hole CH1and an inner sidewall facing the inside of the lower contact hole CH1, and may have a width gradually increasing in a horizontal direction, away from the lower wiring structure320. The lower conductive line336may pass through an insulating structure including the second etch stop layer322and the first insulating layer324in a vertical direction (the Z direction) through the lower contact hole CH1. A lower surface of the lower conductive line336may contact at least a portion of the insulating structure, e.g., the upper insulating structure180and the insulating layer149. A top surface of the lower conductive line336may contact the local capping pattern334. A top surface of the local capping pattern334, a top surface of the lower conductive line336, and a top surface of the first insulating layer324may extend in a horizontal direction on the same plane. A more detailed configuration and effect of the local capping pattern334and the lower conductive line336are substantially the same as those of the local capping pattern154and the conductive plug156described above with reference toFIGS.2A and2C.

The IC device300A may include an insulating capping layer350covering a top surface of each of the first metal wiring structure ML1and the first insulating layer324. In example embodiments, the insulating capping layer350may have a multi-layer structure including a first insulating capping layer352including metal and a second insulating capping layer354including no metal. In example embodiments, the first insulating capping layer352may be formed of AN, AlON, AlO, or AlOC, and the second insulating capping layer354may be formed of silicon carbide (SiC), silicon nitride (SiN), or nitrogen-doped silicon carbide (SiC:N), or SiOC, for example. In example embodiments, in the insulating capping layer350, any one of the first insulating capping layer352and the second insulating capping layer354may be omitted.

The insulating capping layer350may be covered with a second insulating layer356. A second metal wiring structure ML2may be disposed in an upper contact hole CH2passing through the insulating structure including the insulating capping layer350and the second insulating layer356. The second metal wiring structure ML2may be connected to the first metal wiring structure ML1. Constituent materials of the first insulating layer324and the second insulating layer356may be substantially the same as those of the lower insulating layer314described above.

The second metal wiring structure ML2may contact a top surface of the lower conductive line336. The second metal wiring structure ML2may include an upper wiring366directly contacting the lower conductive line336of the first metal wiring structure ML1without passing through a separate barrier layer. In example embodiments, the upper wiring366may be formed of a metal including an element selected from molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), and aluminum (Al) alone, or a metal including a combination thereof. In example embodiments, the lower conductive line336of the first metal wiring structure ML1and the upper wiring366of the second metal wiring structure ML2may include the same metal. For example, each of the lower conductive line336of the first metal wiring structure ML1and the upper wiring366of the second metal wiring structure ML2may be formed of Mo.

FIG.5is a cross-sectional view illustrating an IC device300B according to still other example embodiments. InFIG.5, the same reference numerals as those ofFIG.4denote the same members, and a redundant description thereof is omitted herein.

Referring toFIG.5, the IC device300B may have substantially the same configuration as that of the IC device300A described above with reference toFIG.4. However, the IC device300B includes a second metal wiring structure ML2A instead of the second metal wiring structure ML2.

The second metal wiring structure ML2A may be connected to the first metal wiring structure ML1through the insulating structure including the insulating capping layer350and the second insulating layer356. The second metal wiring structure ML2A may constitute an upper wiring structure.

The second metal wiring structure ML2A may include a local capping pattern374and an upper conductive line376in the upper contact hole CH2. A bottom surface of the upper conductive line376of the second metal wiring structure ML2A may contact a top surface of the lower conductive line336.

The local capping pattern374of the second metal wiring structure ML2A may have an outer sidewall contacting an upper portion of the inner wall of the upper contact hole CH2, may have an inner sidewall facing the inside of the upper contact hole CH2, and may have a width gradually increasing in a horizontal direction, away from the lower wiring structure320. The upper conductive line376may pass through the insulating structure including the insulating capping layer350and the second insulating layer356in a vertical direction (the Z direction) through the upper contact hole CH2. A lower surface of the upper conductive line376may contact at least a portion of the insulating structure, e.g., the insulating capping layer350and the second insulating layer356. A top surface of the upper conductive line376may contact the local capping pattern374. A top surface of the local capping pattern374, a top surface of the upper conductive line376, and a top surface of the second insulating layer356may extend in a horizontal direction on the same plane. A more detailed configuration and effect of the local capping pattern374and the upper conductive line376are substantially the same as those of the local capping pattern154and the conductive plug156included in the source/drain contact structure CA described above with reference toFIGS.2A and2C.

FIG.6is a plan layout diagram of some components of an IC device400according to still other example embodiments,FIG.7Ais a cross-sectional view taken along line X4-X4′ ofFIG.6, andFIG.7Bis a cross-sectional view taken along line Y4-Y4′ ofFIG.6. An example configuration of the IC device400including a multi-bridge channel field effect transistor (MBCFET) or a gate-all-around FET (GAAFET) device is described with reference toFIGS.6,7A, and7B.

Referring toFIGS.6,7A, and7B, the IC device400may include a plurality of fin-type active regions F4protruding from a substrate402and elongated in a first horizontal direction (the X direction), and a plurality of nanosheet stacks NSS facing a top surface FT4of the fin-type active regions F4at a position apart upward from the fin-type active regions F4in a vertical direction (the Z direction). As used herein, the term “nanosheet” refers to a conductive structure having a cross-section substantially perpendicular to a direction in which current flows. It should be understood that the nanosheet may include nanowires.

A trench T4defining fin-type active regions F4may be formed in the substrate402, and the trench T4may be filled with a device separation layer412. The substrate402, the fin-type active regions F4, and the device separation layer412may have substantially the same configuration as those of the substrate110, the fin-type active region FA, and the device separation layer112described above with reference toFIGS.2A to2C.

A plurality of gate lines460may extend in a second horizontal direction (the X direction) on the fin-type active regions F4. The nanosheet stacks NSS may be disposed on the top surface FT4of each of the fin-type active regions F4in regions in which the fin-type active regions F4intersect the gate lines460, and may face the top surface FT4of the fin-type active region F4at a position apart from the active region F4. A plurality of nanosheet transistors may be formed in portions in which the fin-type active regions F4intersect the gate lines460on the substrate402.

The nanosheet stacks NSS may each include a plurality of nanosheets N1, N2, and N3overlapping each other in a vertical direction (the Z direction) on the top surface FT4of the fin-type active region F4. The nanosheets N1, N2, and N3may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3having different vertical distances from the top surface FT4of the fin-type active region F4.

FIG.6illustrates a case in which a planar shape of the nanosheet stack NSS has a substantially quadrangular shape, as an example, but the nanosheet stack NSS may have various planar shapes depending on a planar shape of each of the fin-type active region F4and the gate line460. In the present example, a configuration in which the nanosheet stacks NSS and the gate lines460are formed on one fin-type active region F4and the nanosheet stacks NSS are formed in a row in a first horizontal direction (the X direction) on one fin-type active region F4is illustrated, but the number of nanosheet stacks NSS disposed on one fin-type active region F4may be varied. For example, one nanosheet stack NSS may be formed on one fin-type active region F4. In this example, a case in which the nanosheet stacks NSS each include three nanosheets is illustrated, but the nanosheet stack NSS may include one or more nanosheets, and the number of nanosheets constituting the nanosheet stack NSS may be varied.

Each of the nanosheets N1, N2, and N3may have a channel region. In example embodiments, each of the nanosheets N1, N2, and N3may be formed of a Si layer, a SiGe layer, or a combination thereof.

A plurality of recess regions R4may be formed at an upper portion of the fin-type active region F4, and a plurality of source/drain regions430may be disposed on the recess regions R4. The source/drain regions430may be formed of an epitaxial semiconductor layer. Referring toFIG.7A, among the source/drain regions430, the source/drain region430adjacent to the device separation layer412may have a smaller volume, compared with the source/drain region430relatively far from the device separation layer412. A more detailed configuration of the source/drain regions430is substantially the same as that of the source/drain regions130described above with reference toFIGS.2A and2C.

The gate line460may surround each of the nanosheets N1, N2, and N3, while covering the nanosheet stack NSS on the fin-type active region F4. The gate lines460may each include a main gate portion460M covering an upper surface of each of the nanosheet stacks NSS and elongated in a second horizontal direction (the Y direction), and a plurality of sub-gate portions460S integrally connected to the main gate portion460M and disposed between each of the nanosheets N1, N2, and N3and between the fin-type active region F4and the first nanosheet N1one by one. The nanosheets N1, N2, and N3may have a gate-all-around (GAA) structure surrounded by the gate line460. The gate line460may be formed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. A gate insulating layer432may be between the nanosheet stack NSS and the gate line460. The gate insulating layer432may have substantially the same configuration as that of the gate insulating layer132described above with reference toFIGS.2A to2C.

A metal silicide layer452may be formed on a top surface of each of the source/drain regions430. The metal silicide layer452may have substantially the same configuration as that of the metal silicide layer152described above with reference toFIGS.2A and2C.

Both sidewalls of each of the gate lines460may be covered with a plurality of outer insulating spacers418. The outer insulating spacers418may cover both sidewalls of the main gate portion460M on the nanosheet stacks NSS. The outer insulating spacers418and the source/drain regions430may be covered with an insulating liner442. The outer insulating spacer418and the insulating liner442may each be formed of SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or a combination thereof. The insulating liner442may be omitted.

A plurality of inner insulating spacers428may be interposed between each of the nanosheets N1, N2, and N3and between the fin-type active region F4and the first nanosheet N1. Both sidewalls of each of the sub-gate portions460S may be covered with an inner insulating spacer428with the gate insulating layer432therebetween. The inner insulating spacers428may be between the sub-gate portions460S and the source/drain regions430. In example embodiments, the outer insulating spacer418and the inner insulating spacer428may be formed of the same insulating material. In other example embodiments, the outer insulating spacer418and the inner insulating spacer428may be formed of different insulating materials. The inner insulating spacer428may be formed of SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or a combination thereof. The inner insulating spacer428may further include an air gap. In example embodiments, the inner insulating spacers428may be omitted. In this case, each of the source/drain regions430may contact the gate insulating layer432between the source/drain region430and the sub-gate portion460S.

The insulating liner442may be covered with an inter-gate insulating layer444. The inter-gate insulating layer444may include a silicon oxide layer. A plurality of source/drain contact structures CA4may be disposed in source/drain contact holes CAH4passing through the inter-gate insulating layer444and the insulating liner442. Each of the source/drain contact structures CA4may be configured to be connected to the source/drain region430through the metal silicide layer452. Each of the source/drain contact structures CA4may include a local capping pattern454and a conductive plug456.

The conductive plug456may be elongated in a vertical direction (the Z direction) through the inter-gate insulating layer444and the insulating liner442. The local capping pattern454may be disposed concentrically with the conductive plug456, and may have a width gradually increasing in a horizontal direction away from the substrate402. The conductive plug456may pass through the insulating structure including the inter-gate insulating layer444and the insulating liner442in a vertical direction (the Z direction). A lower sidewall of the conductive plug456may contact at least a portion of the insulating structure, e.g., the inter-gate insulating layer444and the insulating liner442. An upper sidewall of the conductive plug456may contact the local capping pattern454. A top surface of the local capping pattern454, a top surface of the conductive plug456, and a top surface of the inter-gate insulating layer444may extend in a horizontal direction on the same plane. A more detailed configuration and effect of the local capping pattern454and the conductive plug456are the same as those of the local capping pattern154and the conductive plug156included in the source/drain contact structure CA described above with reference toFIGS.2A and2C.

Each of the gate lines460may be covered with an insulating capping line440. The insulating capping line440may have substantially the same configuration as that of the insulating capping line140described above with reference toFIGS.2A to2C.

The IC device400may include an upper insulating structure480covering a top surface of each of a plurality of source/drain contact structures CA4, a plurality of insulating capping lines440, and the inter-gate insulating layer444. The upper insulating structure480may include an etch stop layer482and an interlayer insulating layer484sequentially stacked on the source/drain contact structure CA4and the insulating capping line440. The etch stop layer482and the interlayer insulating layer484may have substantially the same configuration as those of the etch stop layer182and the interlayer insulating layer184described above with reference toFIGS.2A and2B.

Referring toFIG.6, a plurality of via contacts CAV4may be disposed on the source/drain contact structures CA4. The via contacts CAV4may each pass through the upper insulating structure480to contact a top surface of the source/drain contact structure CA4. In example embodiments, each of the via contacts CAV4may have the same configuration as that of the via contacts CAV described above with reference toFIG.2A. In other example embodiments, each of the via contacts CAV4may have the same configuration as that of the via contacts CAV2described above with reference toFIG.3.

Referring toFIGS.6,7A, and7B, a gate contact structure CB4may be disposed on the gate line460. The gate contact structure CB4may be configured to be disposed in a gate contact hole CBH4passing through the upper insulating structure480and the insulating capping line440in a vertical direction (the Z direction) and connected to a top surface of the gate line460.

The gate contact structure CB4may be disposed on the gate line460, and may be in contact with a top surface of at least one metal layer constituting the gate line460. The gate lines460may be connected to an upper conductive line through a gate contact structure CB4.

The gate contact structure CB4may include a local capping pattern494and a conductive plug496in the gate contact hole CBH4. The local capping pattern494may have an outer sidewall in contact with an upper portion of an inner wall of the gate contact hole CBH4, may have an inner sidewall facing the inside of the gate contact hole CBH4, and may have a width gradually increasing in a horizontal direction, away from the substrate402. The conductive plug496may pass through the insulating structure including the insulating capping line440and the upper insulating structure480in a vertical direction (the Z direction) through the gate contact hole CBH4. A lower sidewall of the conductive plug496may contact at least a portion of the insulating structure, e.g., the insulating capping line440. An upper sidewall of the conductive plug496may contact the local capping pattern494. A top surface of the local capping pattern494, a top surface of the conductive plug496, and a top surface of the upper insulating structure480may extend in a horizontal direction on the same plane. A more detailed configuration and effect of the local capping pattern494and the conductive plug496are substantially the same as those of the local capping pattern154and the conductive plug156included in the source/drain contact structure CA described above with reference toFIGS.2A and2B.

In the IC device400described above with reference toFIGS.6,7A, and7B, the source/drain contact structure CA4includes the local capping pattern454and the conductive plug456, and the gate contact structure CB4includes the local capping pattern494and the conductive plug496.

The local capping patterns454and494surround the outer sidewalls of the upper ends of the conductive plugs456and496, and have a width gradually increasing in a horizontal direction, away from the substrate402. Thus, the local capping patterns454and494may physically fix the conductive plugs456and496so that at least a portion of the conductive plugs456and496may not escape from the contact hole (e.g., the source/drain contact hole CAH4or the gate contact hole CBH4).

In particular, when the local capping patterns454and494include a metal, adhesion between the local capping patterns454and494and the conductive plugs456and496may be improved at a contact portion thereof, so that the effect of physically fixing the conductive plugs456and496by the local capping patterns454and494may be further improved. In addition, when formed of an insulating material or a dielectric material, the local capping patterns454and494may provide a structure advantageous for securing an insulating distance between the conductive plugs456and496and a conductive region adjacent thereto, e.g., between the conductive plug456of the source/drain contact structure CA4and the gate line460and/or the conductive plug496adjacent thereto, compared to a case in which the local capping patterns454and494are formed of a conductive material.

In addition, without a separate barrier layer having resistance, which is greater than that of the conductive plugs456and496, between an insulating structure adjacent to the conductive plugs456and496, i.e., an insulating structure including the insulating capping line440, the insulating liner442, the inter-gate insulating layer444, and the upper insulating structure480, and the conductive plugs456and496, a lower sidewall of each of the conductive plugs456and496is in contact with the insulating structure. Accordingly, even when the IC device400has a device region having a reduced area due to down-scaling, the electrical characteristics and reliability of the IC device400may be improved, while contact resistance in each of the source/drain contact structure CA4and the gate contact structure CB4is reduced.

Hereinafter, a method of manufacturing an IC device, according to example embodiments, is described in detail.

FIGS.8A to8Iare cross-sectional views illustrating a process sequence of a method of manufacturing an IC device, according to example embodiments, and are cross-sectional views according to a process sequence of a partial region of portions corresponding to a cross-section taken along line X2-X2′ ofFIG.1. A method of manufacturing the IC device100illustrated inFIGS.1and2A to2Dis described with reference toFIGS.8A to8I.FIGS.8A to8Iillustrate a process sequence in a partial region of the second device region RX2, but the same or similar processes as described below may also be performed on the first device region RX1. InFIGS.8A to8I, the same reference numerals as those inFIGS.1and2A to2Ddenote the same members, and redundant descriptions thereof are omitted herein.

Referring toFIG.8A, a partial region of the substrate110may be etched in the first device region RX1and the second device region RX2(seeFIGS.1and2A) to form fin-type active regions FA protruding from the main surface110M of the substrate110upward in a vertical direction (the Z direction) and extending in parallel to each other in the first horizontal direction (the X direction). A device separation layer112(seeFIG.2B) covering both lower sidewalls of each of the fin-type active regions FA may be formed. Thereafter, a portion of the device separation layer112and a portion of the substrate110may be etched to form a deep trench DT (seeFIG.2B) defining the first device region RX1and the second device region RX2. The deep trench DT may be filled with the inter-device separation insulating layer114. Referring toFIG.2B, after the deep trench DT in the device separation region DTA is filled with the inter-device separation insulating layer114, a structure in which the fin-type active regions FA protrude above the top surface of the device separation layer112in the first device region RX1and the second device region RX2may be obtained.

Referring toFIG.8B, a plurality of dummy gate structures DGS extending across the fin-type active regions FA may be formed on the device separation layer112and the inter-device separation insulating layer114(seeFIG.2B). The dummy gate structures DGS may include a dummy gate insulating layer D12, a dummy gate line D14, and a dummy insulating capping layer D16sequentially stacked on the fin top surface FT of the fin-type active regions FA, and on each of the device separation layer112and the inter-device separation insulating layer114(seeFIG.2B). The dummy gate insulating layer D12may include a silicon oxide layer. The dummy gate line D14may include a polysilicon layer. The dummy insulating capping layer D16may include a silicon nitride layer.

Insulating spacers120may be formed on both sidewalls of the dummy gate structure DGS. Portions of the fin-type active regions FA exposed between each of the dummy gate structures DGS may be etched to form the recess region RR in the fin-type active regions.

Thereafter, the source/drain region130may be formed to fill the recess regions RR in the first device region RX1and the second device region RX2. In example embodiments, a low-pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed using source materials including an elemental semiconductor precursor to form the source/drain region130. In example embodiments, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), etc., may be used as a Si source to form the source/drain region130formed of a Si layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). In other example embodiments, a Si source and a Ge source may be used to form the source/drain region130including a SiGe layer doped with a p-type dopant. As the Si source, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), or the like may be used. As the Ge source, germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H10), dichlorogermane (GeH2Cl2), etc., may be used. The p-type dopant may be selected from boron (B) and gallium (Ga).

The process of forming the source/drain region130in the first device region RX1and the process of forming the source/drain region130in the second device region RX2may be sequentially performed. For example, after the source/drain region130is formed in the first device region RX1, the source/drain region130may be formed in the second device region RX2, or after the source/drain region130is formed in the second device region RX2, the source/drain region130may be formed in the first device region RX1.

The insulating liner146and the inter-gate insulating layer148sequentially covering a resultant structure, in which the source/drain region130is formed in the first device region RX1and the second device region RX2, may be formed. The inter-gate insulating layer148may be formed to have a planarized top surface. After the inter-gate insulating layer148is formed, a top surface of the dummy insulating capping layer D16may be exposed.

Referring toFIG.8C, in the result ofFIG.8B, the dummy insulating capping layer D16and surrounding insulating layers may be removed from the result structure ofFIG.8Bby a chemical mechanical polishing (CMP) process to expose a top surface of the dummy gate line D14. As a result, heights of the insulating liner146, the inter-gate insulating layer148, and the insulating spacers120may be lowered.

Referring toFIG.8D, the gate spaces GA may be prepared by removing the dummy gate lines D14and the dummy gate insulating layers D12from a resultant structure ofFIG.8C. The insulating spacer120, the fin-type active regions FA, the device separation layer112, and the inter-device separation insulating layer114(seeFIG.2B) may be exposed through the gate spaces GA.

Referring toFIG.8E, in the result ant structure ofFIG.8D, a gate insulating layer132, a gate line GL, and an insulating capping line140may be formed in the gate spaces GA.

In order to form the gate insulating layer132, the gate line GL, and the insulating capping line140, first, the gate insulating layers132and gate lines GL filling the gate spaces GA may be formed and then etched back so that the gate insulating layers132and the gate lines GL may fill only a lower portion of each of the gate spaces GA. During the etch-back, an upper portion of the insulating spacer120may also be removed to lower the height of the insulating spacer120.

Thereafter, the insulating capping line140covering the top surface of each of the gate line GL, the gate insulating layer132, and the insulating spacer120in the gate spaces GA and filling an upper portion of the gate space GA may be formed. The insulating capping line140may be formed to have a planarized top surface. During the planarization of the top surface of the insulating capping line140, an upper portion of each of the insulating liner146and the inter-gate insulating layer148may also be removed so that the heights thereof may be lowered. Thereafter, the insulating layer149covering the top surface of each of the insulating capping line140, the insulating liner146, and the inter-gate insulating layer148may be formed.

In example embodiments, before forming the gate insulating layer132, an interface layer (not shown) may be formed to cover the surface of each of the fin-type active regions FA exposed through the gate spaces GA. A portion of the fin-type active regions FA exposed in the gate spaces GA may be oxidized to form the interface layer.

Referring toFIG.8F, the source/drain contact hole CAH passing through the insulating layer149and the inter-gate insulating layer148to expose the source/drain regions130may be formed in a resultant structure ofFIG.8E. After the source/drain regions130are exposed through the source/drain contact holes CAH, a partial region of the source/drain region130may be removed through the source/drain contact holes CAH so that the source/drain contact hole CAH may be further elongated toward the substrate110. In example embodiments, an anisotropic etching process for forming the source/drain contact hole CAH may be performed using plasma.

After the source/drain contact hole CAH is formed, a metal silicide layer152may be formed on the source/drain region130exposed from a bottom side of the source/drain contact hole CAH. In example embodiments, in order to form the metal silicide layer152, a metal liner (not shown) conformally covering an inner wall of the source/drain contact hole CAH may be formed and heat treated to induce a reaction between the source/drain region130and a metal constituting the metal liner. After the metal silicide layer152is formed, a remaining portion of the metal liner may be removed. A portion of the source/drain region130may be consumed during the process of forming the metal silicide layer152. In example embodiments, when the metal silicide layer152is formed of a titanium silicide layer, the metal liner may be formed of a Ti layer.

Referring toFIG.8G, in a resultant structure ofFIG.8F, a local capping layer154L covering an upper portion of the inner sidewall of each of the source/drain contact hole CAH and a top surface of the insulating layer149may be formed.

In forming the local capping layer154L, the local capping layer154L may be formed with a degraded step coverage, rather than being conformally formed on the insulating layers defining the inner wall of the source/drain contact hole CAH, e.g., on the inter-gate insulating layer148and the insulating layer149.

In example embodiments, a physical vapor deposition (PVD) process may be used to form the local capping layer154L. Here, the local capping layer154L may be controlled to include an overhang portion (OH) covering only an upper portion, which is adjacent to an entrance, of the inner wall of the source/drain contact hole CAH by controlling a deposition atmosphere for forming the local capping layer154L, e.g., a bias applied to the substrate, temperature, pressure, plasma formation conditions, etc., or by controlling a flow rate of source gases considering a sticking coefficient of each of atoms to constitute the local capping layer154L. The local capping layer154L may be formed to cover only an upper portion of the insulating layers defining the source/drain contact hole CAH in the source/drain contact hole CAH. For example, the local capping layer154L may be formed to cover a portion of the sidewall of the insulating layer149exposed in the source/drain contact hole CAH and a portion of the sidewall of the inter-gate insulating layer148.

The local capping layer154L in the source/drain contact hole CAH may cover the insulating structure including the insulating layer149and the inter-gate insulating layer148with a greater thickness in a direction away from the substrate110. A horizontal width of a portion defined by the local capping layer154L in the source/drain contact hole CAH may gradually decrease in a direction away from the substrate110.

The local capping layer154L may include a silicon-containing insulating layer, a metal nitride layer, a metal oxynitride layer, an insulating layer doped with a metal, or a combination thereof In example embodiments, the local capping layer154L may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiCN) layer, a silicon oxycarbonitride (SiOCN) layer, a boron-containing silicon nitride (SiBN) layer, a titanium oxynitride (TiON) layer, TiN, TaN, a Ti-doped silicon oxide layer, a Ti-doped silicon nitride layer, or a combination thereof. However, the constituent material of the local capping layer154L may be varied.

Referring toFIG.8H, in the resultant structure ofFIG.8G, a metal-containing layer156L may be formed to fill the source/drain contact hole CAH. The metal-containing layer156L may have a surface in contact with the local capping layer154L inside the source/drain contact hole CAH.

The metal-containing layer156L may include a metal selected from molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), and a combination thereof.

In example embodiments, the metal-containing layer156L may be formed of a Mo layer. In this case, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process using a Mo precursor may be performed to form the metal-containing layer156L. When the metal-containing layer156L is formed of a Mo layer, the Mo precursor may be selected from MoCl3, MoCl5, MoOCl4, MoCl6, Mo(CO)6, MoO2Cl2, MoOCl4, MoF6, an organic Mo compound, and a combination thereof. In example embodiments, the organic Mo compound may be selected from molybdenum acetylacetonate, biscyclopentadienyl molybdenum dihydride, bisethylcyclopentadienyl molybdenum dihydride, bisisopropylcyclopentadienyl molybdenum dihydride, biscyclopentadienylimide molybdenum, and a combination thereof. However, the types of Mo precursors that may be used to form the metal-containing layer156L may be varied from those described above.

In example embodiments, the metal-containing layer156L may be formed of a Mo layer. The Mo layer may include a Mo nucleation layer formed on the metal silicide layer152, and a bulk Mo layer filling the source/drain contact hole (CAH) on the Mo nucleation layer. The Mo nucleation layer may be formed by a PVD process. The bulk Mo layer may be formed by a bottom-up filling method using an ALD process. In forming the bulk Mo layer by the bottom-up filling method, a process temperature, a process pressure, a flow rate of the Mo precursor, a partial pressure of a reducing gas (e.g., H2gas) may be adjusted so that there is a nucleation delay on the exposed surfaces of the insulating layers exposed from an inner sidewall of the source/drain contact hole CAH, e.g., the insulating liner146, the inter-gate insulating layer148, and the insulating layer149.

In other example embodiments, the metal-containing layer156L may include a growth initiation layer formed on the metal silicide layer152and including tungsten (W) or a W-containing material, and a bulk Mo layer formed on the growth initiation layer by the bottom-up charging method described above to fill the source/drain contact hole CAH.

In example embodiments, the metal-containing layer156L may also be formed in a relatively large opening or trench formed in a scribe lane region or a peripheral circuit region of the substrate110, as well as in the source/drain contact hole CAH. Also, althoughFIG.8Hillustrates that the source/drain contact hole CAH is completely filled with the metal-containing layer156L up to the entrance thereof, an empty space may remain on the metal-containing layer156L in the relatively large opening or trench after the metal-containing layer156L is formed. In this case, an overburden Mo layer (not shown) covering the metal-containing layer156L may be further formed on the substrate110in order to completely fill the relatively large opening or trench. The overburden Mo layer may be formed by a PVD process, for example.

In example embodiments, the first length L11of a portion covering the inner sidewall of the source/drain contact hole CAH in the overhang portion OH of the local capping layer154L in a vertical direction (the Z direction) may be about 30% to 50% of the second length L12from the entrance of the source/drain contact hole CAH to the lowermost surface of the source/drain contact hole CAH defined on the metal silicide layer152in the vertical direction (the Z direction). In example embodiments, the first length L11may be less than about 50% of the second length L12. For example, in the vertical direction (the Z direction), the first length L11may be greater than about 30% and less than about 50% of the second length L12.

When the local capping layer154L includes a metal, adhesion between the overhang portion OH of the local capping layer154L and the metal-containing layer156L may be improved. As a length of a portion not covered with the overhang portion OH of the local capping layer154L in the inner sidewall of the source/drain contact hole CAH in a vertical direction (the Z direction) (i.e., a length obtained by subtracting the first length L11from the second length L12) increases, a nucleation delay effect at the exposed surfaces of the insulating layers exposed from inner sidewalls of the source/drain contact hole CAH, e.g., the exposed surfaces of the insulating liner146and the inter-gate insulating layer148, may increase, which may be advantageous for forming the metal-containing layer156L in a bottom-up filling manner.

Referring toFIG.8I, in a resultant structure ofFIG.8I, portions outside the source/drain contact hole CAH in the local capping layer154L and the metal-containing layer156L may be removed using a CMP process to expose an upper surface of the insulating layer149. As a result, the conductive plug156filling the source/drain contact hole CAH may be obtained from the metal-containing layer156L, and a ring-shaped local capping pattern154formed of portions remaining in the source/drain contact hole CAH in the overhang portion OH of the local capping layer154L may be obtained. The local capping pattern154and the conductive plug156may constitute the source/drain contact structure CA.

Because the local capping pattern154has a ring shape surrounding the outer sidewall of the upper end of the conductive plug156, the local capping pattern154may physically fix the conductive plug156so that at least a portion of the conductive plug156may not escape from the source/drain contact hole CAH during removal of portions of the local capping layer154L and the metal-containing layer156L outside the source/drain contact hole CAH using a CMP process or a follow-up process. In addition, when the local capping layer154L includes a metal, adhesion between the overhang portion OH of the local capping layer154L and the metal-containing layer156L may be improved, so that the physical fixing effect of the conductive plug156by the local capping pattern154may be further improved.

Thereafter, referring again toFIGS.2A and2B, the etch stop layer182and the interlayer insulating layer184may be sequentially formed on a resultant structure ofFIG.8Ito form the upper insulating structure180, and form the via contacts CAV connected to the source/drain contact structure CA and the gate contact structures CB connected to the gate lines GL, thereby manufacturing the IC device100described above with reference toFIGS.1and2A to2D.

In example embodiments, in order to form the gate contact structures CB, after the gate contact hole CBH exposing the gate line GL through the upper insulating structure180, the insulating layer149, and the insulating capping line140, a process similar to the process of forming the source/drain contact structure CA described above with reference toFIGS.8G to8Imay be performed on a resultant structure.

FIGS.9A to15are cross-sectional views illustrating a process sequence of a method of manufacturing an IC device, according to other example embodiments, in whichFIGS.9A,10A,11A,12A,13A,14A, and15are cross-sectional views according to a process sequence of portions corresponding to the cross-section X4-X4′ ofFIG.6, andFIGS.9B,10B,11B,12B,13B, and14Bare cross-sectional views illustrating a process sequence of a portion corresponding to the cross-section Y4-Y4′ ofFIG.6. A method of manufacturing the IC device400illustrated inFIGS.6,7A, and7Bis described with reference toFIGS.9A to15. InFIGS.9A to15, the same reference numerals as those inFIGS.6,7A, and7Bdenote the same members, and detailed descriptions thereof are omitted herein.

Referring toFIGS.9A and9B, a plurality of sacrificial semiconductor layers404and a plurality of nanosheet semiconductor layers NS may be alternately stacked one by one on a substrate402. The sacrificial semiconductor layers404and the nanosheet semiconductor layers NS may be formed of different semiconductor materials. In example embodiments, the sacrificial semiconductor layers404may be formed of SiGe, and the nanosheet semiconductor layers NS may be formed of Si.

Referring toFIGS.10A and10B, portions of the sacrificial semiconductor layers404, the nanosheet semiconductor layers NS, and the substrate402may be etched to form a trench T4. A device separation layer412may be formed in the trench T4. As a result, the fin-type active region F4defined by the trench T4may be formed. A stacked structure of the sacrificial semiconductor layers404and the nanosheet semiconductor layers NS remains on a top surface FT4of the fin-type active region F4.

Referring toFIGS.11A and11B, a plurality of dummy gate structures DGS4may be formed on the stacked structure of the sacrificial semiconductor layers404and the nanosheet semiconductor layers NS in a resultant structure ofFIGS.10A and10B. A plurality of outer insulating spacers418may be formed to cover both sidewalls of each of the dummy gate structures DGS4. Thereafter, a portion of each of the sacrificial semiconductor layers404and the nanosheet semiconductor layers NS may be etched using the dummy gate structures DGS4and the outer insulating spacers418as etch masks to divide the nanosheet semiconductor layers NS into a plurality of nanosheet stacks NSS including a plurality of nanosheets N1, N2, and N3. Thereafter, the fin-type active region F4exposed between each of the nanosheet stacks NSS may be etched to form a plurality of recess regions R4on the fin-type active region F4.

Each of the dummy gate structures DGS4may be elongated in a second horizontal direction (the X direction). Each of the dummy gate structures DGS4may have a structure in which an insulating layer D462, a dummy gate layer D464, and a capping layer D466are sequentially stacked. In example embodiments, the insulating layer D462may be formed of silicon oxide, the dummy gate layer D464may be formed of polysilicon, and the capping layer D466may be formed of silicon nitride.

Referring toFIGS.12A and12B, in a resultant structure ofFIGS.11A and11B, a portion of each of the sacrificial semiconductor layers404exposed near the recess regions R4may be removed to form a plurality of indent regions between each of the nanosheets N1, N2, and N3and between the first nanosheet N1and the top surface FT4. Thereafter, a plurality of inner insulating spacers428may be formed to fill the indent regions.

Referring toFIGS.13A and13B, in a resultant structure ofFIGS.12A and12B, a semiconductor material may be epitaxially grown from an exposed surface of each of the recess regions R4and an exposed surface of each of the nanosheets N1, N2, and N3to form a plurality of source/drain regions430. Here, at least one facet430F may be formed on a surface of the source/drain region430adjacent to the device separation layer412and facing the device separation layer412, among the source/drain regions430. Accordingly, the source/drain region430adjacent to the device separation layer412may be formed to have a volume less than the source/drain region430relatively away from the device separation layer412. Thereafter, an insulating liner442may be formed to cover a resultant structure in which the source/drain regions430are formed, an inter-gate insulating layer444may be formed on the insulating liner442, and then a top surface of each of the insulating liner442and the inter-gate insulating layer444may be planarized to expose a top surface of the capping layer D466(seeFIGS.12A and12B).

Thereafter, the dummy gate structures DGS4illustrated inFIGS.12A and12Bmay be removed to prepare a gate space GS. The sacrificial semiconductor layers404may be removed through the gate space GS to expand the gate space GS to a space between each of the nanosheets N1, N2, and N3and a space between the first nanosheet N1and the top surface FT4.

Referring toFIGS.14A and14B, a gate insulating layer432covering the exposed surfaces of the nanosheets N1, N2, and N3and the fin-type active region F4may be formed, a plurality of gate lines460filling the gate space GS on the gate insulating layer432may be formed, and thereafter, an upper portion of the gate lines460and an upper portion of each of the gate insulating layer432and the outer insulating spacers418adjacent thereto may be removed so that an upper space of each of the gate spaces GS is empty. Thereafter, an upper space of each of the gate spaces GS may be filled with an insulating capping line440. A planarization process may be performed, while the gate lines460and the insulating capping line440are formed, so that a height of each of the insulating liner442and the inter-gate insulating layer444may be lowered.

Referring toFIG.15, the inter-gate insulating layer444and the insulating liner442may be partially etched to form a plurality of source/drain contact holes CAH4exposing the source/drain regions430. Thereafter, a portion of the source/drain region430may be removed by an anisotropic etching process through the source/drain contact hole CAH4so that the source/drain contact hole CAH4may be elongated toward the substrate402.

Thereafter, in a similar manner to that of the process of forming the metal silicide layer152described above with reference toFIG.8F, a metal silicide layer452may be formed on the source/drain region430exposed from a bottom side of the source/drain contact hole CAH4, and in a similar manner to that of the process of forming the source/drain contact structure CA described above with reference toFIGS.8G to8I, a local capping pattern454and a conductive plug456may be sequentially formed in the source/drain contact hole CAH4to form a source/drain contact structure CA4.

Thereafter, referring toFIGS.7A and7B, an etch stop layer482and an interlayer insulating layer484sequentially covering a resultant structure ofFIG.15may be formed to form an upper insulating structure480, and a gate contact structure CB4connected to the gate line460may be formed. In order to form the gate contact structure CB4, processes similar to the process of forming the source/drain contact structure CA described above with reference toFIGS.8G to8Imay be performed.

Also, referring toFIG.6, a plurality of source/drain via contacts CAV4connected to the source/drain contact structures CA4may be formed. In example embodiments, the source/drain via contacts CAV4and the gate contact structures CB4may be simultaneously formed. In other example embodiments, the source/drain via contacts CAV4and the gate contact structures CB4may be sequentially formed through separate processes. In this case, the source/drain via contacts CAV4may be first formed, and then the gate contact structures CB4may be formed, or the gate contact structures CB4may be first formed, and then the source/drain via contacts CAV4may be formed.

The method of manufacturing the IC device100illustrated inFIGS.1and2A to2Dand the method of manufacturing the IC device400illustrated inFIGS.6and7A and7Bare described as an example with reference toFIGS.8A to15, but various IC devices having various structures modified or changed from the IC device200illustrated inFIG.3, the IC device300A illustrated inFIG.4, and the IC device300B illustrated inFIG.5may be formed by applying various modifications with reference to the above descriptions.

By way of summation and review, as line widths and pitches of metal wiring layers included in an IC device are reduced, it may become increasingly important to suppress an increase in resistance of metal wiring layers, to improve electrical characteristics and reliability.

As described above, embodiments relate to an integrated circuit (IC) device including a metal wiring layer.