Memory cells with vertically integrated tunnel access device and programmable impedance element

A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and more particularly to memory devices having storage elements that are programmed between different impedance states.

BACKGROUND

There is a need to store information for long periods of time without the use of power. For example, in many electronic devices and systems, data can be stored in a nonvolatile memory, or quasi-nonvolatile memory. A quasi-nonvolatile memory can be a memory with a ‘refresh’ interval orders of magnitude longer than a dynamic random access memory (DRAM).

One type of memory is a conductive bridging random access memory (CBRAM). A CBRAM can have memory elements that store information in terms of the resistance level of two-terminal structure. Changes in resistance can come about by a reduction-oxidation reaction of one or more memory layers caused by the application of bias voltages.

Conventionally, nonvolatile memory cells utilize access devices formed in a substrate. For example, “flash” electrically erasable and programmable read only memory (EEPROM) cells can include one or more transistors formed in a substrate that store data by the presence of charge on a floating gate. Thus, substrate area must be dedicated to such memory cells. Flash EEPROMs can also require specialized fabrication processes. While conventional CBRAM based memories can form storage elements over a substrate, such elements are accessed by access devices formed in a substrate (e.g., silicon based transistors, diodes, thyristors, etc.).

DETAILED DESCRIPTION

According to embodiments, a memory device can include memory cells that include a vertically integrated tunnel access device and storage element, all formed over a substrate. In some embodiments, a storage element can be a two terminal element having a memory layer programmable between different impedance states by way of a reduction-oxidation (redox) reaction. In particular embodiments, a tunnel access device can be a tunnel diode or tunnel transistor and a storage element can be a conductive bridging random access memory (CBRAM) type element.

According to embodiments, a tunnel access device can be advantageously formed on top of a contact structure (e.g., contact or via) by a number of vertically stacked layers. The corresponding storage element can be formed, or completed by additional vertically stacked layers. In this way, memory cells with both access devices and storage elements can be formed on top of contact structures, for a compact memory array that requires no additional substrate area.

In the embodiments disclosed herein, like sections are referred to by the same reference character but with the leading digit(s) corresponding to the figure number.

FIG. 1is a side cross sectional representation of a memory device100according to an embodiment. A memory device100can include a number of bottom electrodes102-0/1, top conductive plates104-0/1, and memory cells106-0/1. Memory cells106-0/1can be formed between each bottom electrode102-0/1and a corresponding plate104-0/1. It is understood that bottom electrodes102-0/1, memory cells106-0/1and plates104-0/1can be formed above a substrate108. In some embodiments, a substrate108can be the substrate of an integrated circuit device that includes various circuit elements, such as transistors, for example.

Referring still toFIG. 1, as shown by memory cell106-0, each memory cell106-0/1can include a tunnel access device110and a storage element112. A tunnel access device110can be enabled to pass current, predominantly by tunneling, through storage element112in at least one direction. As will be described in other embodiments below, a tunnel access device110can be, but is not limited to, a tunnel diode or tunnel transistor. Storage element112can be programmed between different impedance states via a redox reaction. This can include, but is not limited to, the ion conduction within a memory material. In particular embodiments, a storage element112can be a CBRAM type element.

According to embodiments, tunnel access device110and storage element112can be vertically stacked with one another. In some embodiments, storage element112can be formed over tunnel access device110, however, in alternate embodiments, such vertical positions can be switched.

Memory cells106-0/1can be formed by a number of vertically stacked layers114-0to114-n. Such layers (114-0to114-n) can include insulating layers, conductive (or semiconductive) layers, and one or more memory layers. Memory layer(s) can be layers which, alone or in combination, can be programmed between different impedance states by application of a voltage and/or current that induces a redox reaction within one of the memory layers. In particular embodiments, a tunnel access device110and storage element112can share structures. For example, one or more of layers (114-0to114-n) can be a conductive layer that functions as a common electrode (or terminal) for both the tunnel access device110and the storage element112.

According to embodiments, bottom electrodes102-0/1can each correspond to a different memory cell (i.e., bottom electrode102-0corresponds to memory cell106-0, bottom electrode102-1corresponds to memory cell106-1). A bottom electrode102-0/1can be formed, in part or in whole, by a vertical interconnect structure of an integrated circuit, including but not limited to a contact or via. In particular embodiments, bottom electrodes102-0/1can be “plugs” that can form a conductive path between interconnect layers at different vertical levels.

However, other structures can be layers common to multiple memory cells (106-0/1). For example, any of layers (114-0to114-n) can be common to multiple cells (i.e., extend horizontally over multiple bottom contacts102-0/1). Similarly, plates104-0/1can be common to multiple memory cells (i.e., plate104-0and104-1can be the same structure).

In this way, memory cells having a tunnel access device and storage element can be formed on individual bottom electrodes.

FIGS. 2A to 2Cshow examples of tunnel access devices that can be included in embodiments.FIGS. 2A to 2Cshow the use of diodes as tunnel access devices. InFIGS. 2A to 2Cit is understood that a top terminal can be connected to a storage element (e.g.,112). Accordingly,FIG. 2Ashows a tunnel diode210-A with an anode216-0and cathode216-1, with the cathode216-1connected to a storage element.FIG. 2Bshows a tunnel diode210-B with an anode216-0connected to a storage element. InFIGS. 2A and 2B, it is understood that once a reverse bias (anode at a lower potential than cathode) voltage exceeds a threshold voltage, a current can start to flow through the tunnel diode210-A/B that is predominantly due to tunneling. In contrast, in some arrangements, once a forward bias (anode higher potential than cathode) reaches a turn-on voltage (typically less than the threshold voltage), a current can start to flow through the tunnel diode210-A/B in the other direction. However, between the turn-on and threshold voltages, current can be prevented from flowing through the memory element. Turn-on and threshold voltages can be set according to dielectric properties (e.g., material, thickness, etc.).

In particular embodiments, a threshold voltage can be greater than a programming voltage of the corresponding memory storage element.

FIG. 2Cshows a tunnel diode configuration210-C having tunnel diodes217-0/1with commonly connected cathodes. Anode216-0can be connected to a memory element, while anode216-0′ can form an opposing terminal. When a voltage from anode216-0to anode216-0′ exceeds a threshold voltage of tunnel diode217-1, a predominantly tunneling current can flow. Conversely, when a voltage from anode216-0′ to anode216-0exceeds a threshold voltage of tunnel diode217-0, a predominantly tunneling current can flow. It is noted that the materials of tunnel diodes217-0/1can be selected to arrive at desired threshold voltages and current responses. Accordingly, an asymmetric voltage response can be achieved so that it takes a greater bias to induce a current in one direction as opposed to the other direction.

FIGS. 3A to 3Dshow additional examples of tunnel access devices that can be included in embodiments.FIGS. 3A to 3Dshow tunnel transistors that can be used as access devices. InFIGS. 3A to 3Dit is understood that a top terminal can be connected to a storage element (e.g.,112). Accordingly, inFIG. 3Aterminal316-1of tunnel transistor310-A can be connected to a storage element, inFIG. 3Bterminal316-0of tunnel transistor310-B, etc. Each tunnel transistor (310-A to310-D) can have a first terminal316-0, second terminal316-1, and control terminal318. A current flow, which can be a predominantly tunneling current, between a first terminal316-0and a second terminal316-1can be controlled according to a state of the control terminal318. It is understood that a state of a control terminal318can include a high impedance state, as well as an applied voltage.

FIGS. 4A and 4Bshow examples of storage elements that can be included in embodiments.FIGS. 4A and 4Bshow CBRAM type elements412-A/B. InFIGS. 4A and 4Bit is understood that a bottom terminal can be connected to a tunnel access device (e.g.,110). Accordingly,FIG. 4Ashows a CBRAM type element412-A with an anode418-0and cathode418-1, with the anode418-0being connected to a tunnel access device. Conversely,FIG. 4Bshows a CBRAM type element412-B with a cathode418-1connected to a tunnel access device.

CBRAM type elements412-A/B can include one or more memory layers that are programmable between different impedance states due to a redox type reaction. In particular embodiments, an anode418-1can be formed of one or more elements which, under bias, can ionize and ion conduct into a “switching” layer, to thereby alter a switching layer impedance. However, alternate embodiments could include storage elements of different types that are programmable via a current flow and/or application of voltage by operation of the corresponding tunnel access device.

FIG. 5Ashows a memory cell506-A according an embodiment. A memory cell506-A can include a bottom electrode502, a conductive plate504, and a number of layers514-0to514-2formed between. Layers (514-0to514-2) can be vertically stacked with respect to one another. In combination with bottom electrode502and conductive plate504, layers (514-0to514-2) can form a tunnel access device and a storage element. It is understood that memory cell506-A can be formed over a substrate.

A bottom electrode502can be formed in an insulating layer520, and as described for other embodiments herein, can be a contact or via type structure, including a plug. In very particular embodiments, a bottom electrode502can be formed of titanium (Ti), titanium nitride (TiN) tungsten (W), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), gold (Au) or aluminum (Al), as but a few examples.

According to embodiments, layers514-0and514-1can be different insulating layers. In some embodiments, layers514-0/1can be different metal oxide layers. A first metal oxide layer514-0can be an oxide formed by oxidizing bottom electrode502. First metal oxide layer514-0can have a substantially uniform composition, or one that varies over the thickness. Second metal oxide layer514-1can be a deposited layer formed over, and in contact with, the first oxide layer514-0. In a very particular embodiment, a first metal oxide layer514-0can include tantalum oxide (TaOx) formed by oxidizing a tantalum bottom electrode502, and a second metal oxide514-1can be aluminum oxide (AlOx). In another embodiment, a first metal oxide layer514-0can include zirconium oxide (ZrOx) and a bottom electrode502can be zirconium. In a particular embodiment, the ZrOx layer can be formed by oxidizing a bottom electrode of Zr.

InFIG. 5A, layer514-2can include one or more memory layers. Accordingly, layer514-2can be programmable between two or more impedance states. In particular embodiments, a memory layer514-2can be programmed between different resistance values by application of an electric field. In particular embodiments, a memory layer can include a metal and chalcogen. In one very particular embodiment, a memory layer514-2can be a zirconium tellurium combination (ZrTe). As noted above, a layer514-2can include multiple layers, one or more of which can be programmed between different impedance values via a redox reaction. For example, in other embodiments, layer514-2can include metal oxide layers in which ions can conduct to vary an impedance. Further, layer514-2can also include a conductive electrode layer.

A conductive plate504can be formed over layers514-0to514-2. It is understood that a conductive plate504can include more than one layer. In one very particular embodiment, a conductive plate504can include a layer of Ti covered with a layer TiN.

FIG. 5Bshows a memory cell506-B according another embodiment. A memory cell506-B can include items like those ofFIG. 5A. Such items can be formed of the same materials and subject to the same variation as shown inFIG. 5A. However, unlikeFIG. 5Ain the memory cell506-B, layer514-0′ can be a deposited layer, not a layer formed by oxidizing a bottom electrode502.

FIG. 5Cshows a memory cell506-C according another embodiment. A memory cell506-C can include items like those ofFIG. 5A. Such items can be formed of the same materials and subject to the same variation as shown inFIG. 5A. However, unlikeFIG. 5Ain the memory cell506-B, both layers514-0and514-1′ can be formed by oxidizing bottom electrode502. In particular embodiments, first oxidizing conditions can be applied to form layer514-0then second oxidizing conditions can be applied to form layer514-1′.

As noted above, according to embodiments herein, an access device can be used to access a vertically integrated storage element, to enable current to flow through the storage element and/or a voltage to be applied to the storage element to detect its impedance (i.e., read operation). Alternatively, such a current can be a greater magnitude (and direction) to set the impedance of the storage element to a particular value (e.g., program to a low resistance, erase to a high resistance).

FIG. 6is a graph showing responses of various access devices for a memory cell.FIG. 6shows a current versus voltage response. A voltage can be the voltage applied across terminals of an access device, and a current can be a current flowing through the access device.FIG. 6shows an ideal response622, an ideal diode response624, a bi-directional response626, and a resistor response628. As shown, if a diode response624had a threshold voltage response (i.e., increase in current in the negative voltage direction) it could closely follow an ideal access device response. Accordingly, a tunnel diode type access device can serve as an access device. It is understood that a tunnel diode response can be varied according to selection of material type and thickness, in a vertically integrated case.

FIG. 7is a band diagram showing one example of a tunnel diode that can be included in embodiments. The tunnel diode can include metal oxide layers Ta2O5and Al2O3formed between Ta and tantalum nitride (TaN) electrodes. In the particular example shown, the layer of Ta2O5can have a thickness of 50 angstroms (Å) and the layer of Al2O3can have a thickness of 10 Å. Of course, layer thicknesses can be varied to arrive at different threshold responses. In one embodiment, Ta can be a bottom electrode and TaN can be an overlying conductive plate, with layers of Ta2O5and Al2O3vertically stacked in between.

FIGS. 8A and 8Bare diagrams showing read operation simulation results for a memory cell having a tunnel diode access device and CBRAM type element.FIG. 8Ashows the memory cell806of the simulation that includes a tunnel diode selector810and CBRAM element812. In the example shown, tunnel diode selector810was formed by a layer of gadolinium oxide (GdOx) of 20 Å and a layer of tantalum oxide (TaOx) of 50 Å formed between two electrodes.

FIG. 8Bis a graph showing responses of memory cell806in a read operation.FIG. 8Bshows a current resulting from an applied voltage for a CBRAM in a low resistance state (LRS)834-0(Ion) and a high resistance state (HRS)834-1(Ioff).

As shown, at a sense voltage of 1.0V, an Ion/Ioff ratio of 100 can be achieved, for a high sensing margin.

According to some embodiments, memory cells with tunnel access devices and storage elements can form arrays for compactly storing large numbers of data values. One such embodiment is shown inFIGS. 9A and 9B.FIG. 9Ais an isometric view of a memory device900.FIG. 9Bis a transmission electron microscope (TEM) micrograph cross section of a memory cell that can be included in an embodiment like that ofFIG. 9A.

Referring toFIG. 9A, a memory device900can include a number of bottom electrodes902, lower interconnect structures932, and plate stacks930. Lower interconnect structures932can be disposed in a first direction, while plate stacks930can be disposed in a second direction, which in some embodiments, can be generally perpendicular to the first direction. Bottom electrodes902can be formed at the intersection of each plate stack930and lower interconnect structure932(when viewed from the top).

Memory cells (one shown as906) can be formed by each bottom electrode902and a number of overlying layers (914-0to914-3) and a conductive plate904included within each plate stack930. In the embodiment shown, layer914-0can be formed only on a top surface of the corresponding bottom electrode902, however, in other embodiments, such a layer could be part of a plate stack. Further, whileFIG. 9Ashows each plate stack930with layers914-1to914-3, in other embodiments, any or all of such layers may not follow the shape of the conductive plate904. For example, any of layers914-1to914-3can be separate structures, formed over only one bottom electrodes902or a smaller number of bottom electrodes than a conductive plate904. Conversely, any of layers914-1to914-3can be formed over a greater number of bottom electrodes than a conductive plate904.

In one embodiment, layer914-0can be an insulating layer, layer914-1can be an electrode layer, layer914-2can be a switching layer, and layer914-3can be an anode layer. Insulating layer914-0can include one or more insulating layers disposed between bottom electrode902and electrode layer914-1to form a tunnel diode as described herein. Insulating layer914-0can be formed on a top surface of bottom electrode902according to any of the embodiments described herein, or equivalents.

Anode layer914-3and switching layer914-2can form a memory layer. In particular embodiments, anode layer914-3can include one or more metals that can ion conduct within the anode layer914-3and/or the switching layer914-2. Switching layer914-2can be programmed between different impedance states by one or more redox reactions. In some embodiments, this can include the ion conduction of species from the anode layer914-3into the switching layer914-2. In addition or alternatively, other redox reactions within the switching layer914-2can result in a reversible changed in impedance. In very particular embodiments, anode layer914-3can include a chalcogen and metal, while a switching layer can be metal oxide.

Conductive plates904can be a conductive layers that are oriented a different directions than interconnect structures932. In such an arrangement, each memory cell906can be formed between a different plate layer904/interconnect structure932.

By situating memory cells906between different plate layer904/interconnect structure932pairs, selection of individual memory cells906for reading and programming operations can be possible. In such operations a potential can be developed between the plate layer904(or corresponding plate stack930) and interconnect structure932of a memory cell906that is sufficient to enable current to flow through the tunnel diode. This can include exceeding the threshold voltage(s) of the tunnel diode. For read operations, a resulting current or voltage is not sufficient to program the device. However, in program operations, the voltage/current will be sufficient to program the device. In very particular embodiments, a switching layer914-2can be programmed to a low resistance via a current/voltage in one direction, and erased to a high resistance via a current/voltage in the opposite direction. At the same time one memory cell906is selected for reading or programming, other memory cells can be de-selected by ensuring that the voltage between their corresponding plate layer904/interconnect structure932is not sufficient to enable current to flow through the tunnel diode. As noted previously, desired threshold voltages and currents can be established by selection of tunnel diode materials and thicknesses.

FIG. 9Bshows one example of a memory cell like that ofFIG. 9Ain a side cross sectional view.FIG. 9Bshows a memory cell having a tantalum bottom electrode902, a metal oxide layer914-0, an electrode layer914-1, a switching layer914-2, an anode layer914-3, and a TaN conductive plate904.

While embodiments can include tunnel diodes as vertically integrated access devices, other embodiments can include tunnel transistors. Examples of such embodiments are shown inFIGS. 10A and 10B.FIG. 10Ais a schematic diagram of a memory cell1006according to an embodiment. Memory cell1006can include a tunnel transistor1010integrated with a storage element1012. Memory cell1006can be conceptualized as having a first terminal1016-0, second terminal1016-1and control terminal1018. Such terminals are referred to as an emitter (e), collector (c) and base (b), respectively. In operation, according to a state of control terminal1018, a current can be enabled to flow between first terminal1016-0and second terminal1016-1. In some embodiments, a current flow in one direction, can result in a programming of storage element1016-1to one state (e.g., high resistance), while a current flow in the other direction can result in a programming of storage element1016-1to another state (e.g., low resistance). A smaller current in one of the directions can be used to sense the impedance state of storage element1012.

FIG. 10Bis a side cross sectional view of one implementation of a memory cell1006′ such as that shown inFIG. 10A. A memory cell1006′ can include a bottom electrode1002a conductive plate1004, and a number of layers1014-0to1014-3vertically stacked in between. Bottom electrode1002can serve as a first terminal (emitter). Layer1014-0can be an insulating layer, such as one or more metal oxides, for example, which can serve as a tunneling layer (e.g., layer that creates the tunneling current threshold voltage). Layer1014-1can be an electrode layer, which can serve as a control terminal (base). Layer1014-2can be a switching layer as described for embodiments herein, and equivalents. Layer1014-3can be an anode layer as described for embodiments herein, and equivalents. Conductive plate1004can serve as a second terminal (collector).

In the particular embodiment shown, memory cell1006′ can include an electrode tap1036which enables an electrical connection to electrode layer1014-1(base). Electrode tap1036can include a conductive portion1038and insulating sidewall portions1040. Accordingly, a state (i.e., potential or high impedance state) of the control electrode (base)1014-1can be established via electrode tap1036.

It is understood thatFIGS. 10A and 10Bshow particular memory cell configurations, and alternate embodiments can include various other configurations, including those described with reference toFIGS. 2A to 4B.

Memory cells like those shown inFIGS. 10A and 10Bcan be arranged into arrays, which can be formed over a substrate of an integrated circuit. This can enable dense, nonvolatile memory arrays to be created at a “back end” of an integrated circuit fabrication process. Such memory arrays can require substantially no substrate area apart from circuits for driving conductive lines that control access to the memory cells of the array.

An integrated circuit device1100according to one embodiment is shown inFIGS. 11A to 11C.FIG. 11Ais a top plan view.FIG. 11Bis a side cross sectional view taken along the plane B-B ofFIG. 11A.FIG. 11Cis a side cross sectional view taken along the plane C-C ofFIG. 11A.

Referring toFIG. 11A, a memory device1100can include a number of lower interconnect structures (one shown as1132) arranged in one direction (horizontal inFIG. 11A). Interconnect structures1132can be conductively connected to bottom electrodes (one shown as1102), which serve as first terminals (e.g., emitters) for memory cells of a row. Accordingly, the interconnect structures1132can be conceptualized as being emitter lines E0, E1, E2and E3, common to memory cells of a same column.

Control electrodes (one shown as1114-1) can be formed over, and arranged in a different direction than interconnect structures1132. InFIG. 11A, control electrodes1114-1can extend in a vertical direction. A state of each control electrode1014-1can be established by a corresponding control electrode tap (one shown as1136). Control electrodes1114-1can be conceptualized as being base lines B0, B1and B2common to memory cells of a same row.

A conductive plate (one shown as1104) can be formed over each control electrode1114-1. A state of each conductive plate1104can be established by a corresponding control electrode tap (one shown as1142). Conductive plates1104can be conceptualized as being collector lines C0, C1and C2common to memory cells of a same row.

Bottom electrodes (one shown as1102) can be formed at the intersection of each lower interconnect structure1132and conductive plate1104. Consequently, a memory cell can be formed at each such intersection by the vertical layers formed over the corresponding bottom electrode1102.

Referring toFIG. 11B, lower interconnect structures1132can be formed on an insulating layer1144. It is understood that insulating layer1144can be formed over a substrate (not shown). Bottom electrodes1102can be formed in an insulating layer1120. Further, a layer1114-0can be formed between each bottom electrode1102and the corresponding control electrode1114-1. A layer1114-0can include one or more insulating layers as described herein, which can create a tunneling barrier for the tunnel transistor. In alternate embodiments, all or a portion of layer1114-0can be formed by oxidizing a bottom electrode1102. A memory layer1114-2can be formed between each control electrode1114-1and conductive plate1104. All or a portion of memory layer1114-2can be programmable between different impedance state. Memory layer1114-2can include multiple layers, as described herein, or equivalents.

Referring toFIG. 11C, in the memory device1100shown, control electrodes1114-1can extend in a lateral direction beyond memory layer1114-2and conductive plate1104, to provide a landing area for control electrode tap1136. However, in alternate embodiments, such a tap could extend through various layers, as shown inFIG. 10B.

As will be described in following embodiments, by establishing the states of emitter lines (E0to E3), collector lines (C0to C2), and base lines (B0to B2), memory cells can be selected for read operations (which sense the impedance state of a storage element) and program operations (which establish the impedance state of the storage element).

FIGS. 12A and 12Bare diagrams showing a memory device like that shown inFIGS. 11A to 11C.FIG. 12Ais a schematic diagram showing memory device1200with memory cells (four shown as1206-00, -02, -20, -21) like those ofFIG. 10A(i.e., include a tunnel transistor and storage element, such as a CBRAM like element). Memory cells of same row (shown in a horizontal direction) can have commonly connected base lines (B0to B2) and collector lines (C0to C2). Memory cells of a same column (shown in a vertical direction) can have commonly connected emitter lines (E0to E3). In a particular embodiment, base lines (B0to B2), collector lines (C0to C2) and emitter lines (E0to E3) can be formed by structures like those shown inFIGS. 11A to 11C. InFIG. 12A, memory cell1206-00is assumed to store a data value “Bit00”.

FIG. 12Bis table showing the states of base lines (B0to B2), collector lines (C0to C2) and emitter lines (E0to E2) for operations of the memory device1200. In particular,FIG. 12Bshows states for selecting memory cell1206-00(i.e., Bit00) for program, erase, and read operations, while the other memory cells are de-selected.

Referring toFIGS. 12A and 12B, in a programming operation, collector lines (C0to C2) can be driven to a high voltage (H), a base line of the selected row (B0in this example), can be placed into a high impedance state, while base lines of unselected rows (B1, B2) can be driven to the high voltage (H). An emitter line of the selected column (E0in this example), can be driven to a low voltage (L), while emitter lines of unselected columns (E1to E3) can be driven to the high voltage (H).

In the program operation, in the selected memory cell1206-00, a potential will be sufficient to cause a tunnel transistor current to flow, programming the corresponding storage element. In one embodiment, such an operation can program a CBRAM type element to a low resistance state. In a memory cell1206-02of the same column, but a different row, while its emitter line can be low (E0=L), the corresponding base line (B2) and collector line (C2) can both be high. As a result, there will be no potential difference across the storage element, so the storage element will not be programmed. In a memory cell1206-20of the same row, but different column, while the base line (B0) can be in a high impedance state, the emitter and collector lines can both be high (C0=E2=H), thus no current will flow through the memory cell, and the storage element will not be programmed. In a memory cell1206-21of a different column and row, all terminals will be at the same voltage (H), thus no current will flow in the memory cell, and the storage element will not be programmed.

As shown byFIG. 12B, read operations can occur in the same fashion as program operations. However, high voltage (H′) is at a level sufficient to enable a tunnel transistor current, but not high enough to program the storage element (i.e., H′<<H).

Referring still toFIGS. 12A and 12B, in an erase operation, collector lines (C0to C2) can be driven to a low voltage (L), a base line of the selected row (B0in this example), can be placed into a high impedance state, while base lines of unselected rows (B1, B2) can be driven to the low voltage (L). An emitter line of the selected column (E0in this example), can be driven to a high voltage (H), while emitter lines of unselected columns (E1to E3) can be driven to the low voltage (L). Within the selected memory cell1206-00, a potential will be sufficient to cause a tunnel transistor current to flow in a direction opposite to that of the programming operation, resulting in the impedance of the corresponding storage element being changed. In one embodiment, such an operation can erase a CBRAM type element to a high resistance state. In a memory cell1206-02of the same column, but a different row, while an emitter line can be high (E0=H), the base (B2) and collector (C2) can both be low, so no potential difference will develop across the storage element. In a memory cell1206-20of the same row, but different column, while the base (B0) can be in a high impedance state, the emitter and collector can both be low (C0=E2=H), and no current will flow through the memory cell. In a memory cell1206-21of a different column and row, all terminals will be at the same voltage (L), thus no current will flow in the memory cell.

In this way, an array of memory cells having tunnel transistors and storage elements can individually access individual memory cells for read, program and erase operations.

Having described various memory devices, memory cells and methods of operations, methods of manufacturing memory cells according to particular embodiments will now be described.

FIGS. 13A to 13Eare a sequence of side cross views showing one method of fabricating a memory cell like that shown inFIG. 5A.

FIG. 13Ashows the formation of an opening1350in insulating layer520. In some embodiments, such an opening1350can be formed by etching through the insulating layer to a conductive structure below (e.g., a lower interconnect structure). In particular embodiments, opening1350can be minimal achievable contact size, for a very compact memory cell footprint.

FIG. 13Bshows the formation of bottom electrode502′ within opening1350. In a particular embodiment, this can include forming a “plug”. In some embodiments, electrode material(s) can be deposited into the opening1350and then a planarization step can planarize the structure. Bottom electrode502′ can formed with any suitable fabrication technique, including but not limited to sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD). Bottom electrode502′ can be formed of any suitable conductive material, or combination of conductive materials. In one very particular embodiment, bottom electrode502′ can be Ta.

FIG. 13Cshows the oxidation of bottom electrode to form bottom electrode502covered with a native oxide layer514-0. Such a step can include a direct in situ oxidation of the bottom electrode502′. That is, bottom electrode502′ can be exposed to an oxidizing atmosphere to grow an oxide layer of desired thickness and property. However, as will be described with reference toFIG. 13D, oxide layer514-0can be formed indirectly while a second insulating layer is being formed. In one very particular embodiment, bottom electrode502can be Ta and oxide layer514-0can be TaOx.

FIG. 13Dshows the formation of a second insulating layer514-1over oxide layer514-0. In some embodiments, second insulating layer514-1can be formed by depositing a layer after oxide layer514-0has been formed. However, in other embodiments, oxide layer514-0can be formed as second insulating layer514-1is deposited. In one particular embodiment, a second insulating layer514-1can be AlOx formed by reactive pulsed DC PVD technique, which can indirectly oxidize a Ta bottom electrode to create a TaOx layer514-0. The degree to which the bottom electrode502′ is oxidized can be controlled by variables used to form the AlOx, including but not limited to: when and how much oxygen is introduced into the reaction chamber and the interval between plasma ignition and the introduction of oxygen. In one very particular embodiment, a layer of TaOx514-0can be formed by the deposition of a layer of AlOx by a DC pulsed PVD deposition with a power of 1000 W, duty cycle of 30%, and pressure of about 5.2 mT at room temperature (RT).

FIG. 13Eshows the formation of a memory layer514-2over second insulating layer514-1. A memory layer can have the form of any of those described for embodiments herein, or equivalents, including being composed of multiple layers. In one very particular embodiment, memory layer514-2can be a Zr—Te combination (ZrTe) formed by co-sputtering a Zr target and Te target with DC and RF PVD, respectively. The sputtering of the Zr target can be at a power of 13 W, while the sputtering of the Te target can be at a power of 17 W. A pressure can be about 2 mT at RT.

Referring back toFIG. 5A, following the operations ofFIG. 13E, a conductive plate504can be formed over memory layer514-2. A conductive plate504can be formed of any conductive material(s) suitable for the memory cell structure, materials, and fabrication process used. In one very particular embodiment, a conductive plate504can include a100A layer of Ta covered with a500A layer of TaN. Ta can be deposited with DC PVD at a power of 50 W at a pressure of 2 mT at RT. TaN can be deposited with a nitrogen (N2) and argon (Ar) gas mixture, with an N2flow of 6 standard cubic centimeters per minute (sccm) and an Ar flow of 19 sccm. Such a TaN layer can be deposited at 150 W with a pressure of about 2 mT at RT.

FIGS. 14A to 14Eare a sequence of side cross views showing one method of fabricating a memory cell like that shown inFIG. 5B.FIGS. 14A to 14Einclude steps like those ofFIGS. 13A to 13E, and such steps can be the same, except as noted below.

Referring toFIG. 14C, unlike the embodiment ofFIGS. 13A to 13E, a first insulating layer514-0′ can be a deposited layer, rather than an oxide layer created by oxidizing a surface of bottom electrode.

FIGS. 15A to 15Eare a sequence of side cross views showing one method of fabricating a memory cell like that shown inFIG. 5C.FIGS. 15A to 15Einclude steps like those ofFIGS. 13A to 13E, and such steps can be the same, except as noted below.

Referring toFIGS. 15C and 15D, unlike the embodiment ofFIGS. 13A to 13E, a first insulating layer514-0and second insulating layer514-1′ can be formed by oxidizing bottom electrode502′. In particular embodiments, a bi-layer of a same metal oxide can be created, where the different layers have different stoichiometry. An oxidation process can be varied to create such a bi-layer structure. Process variations can include, but are not limited to: varying an amount of oxygen introduced into the reaction chamber, varying a gas chemistry or conditions during a deposition (e.g., CVD, ALD) process.

Referring toFIG. 15C, first oxidation conditions can form an initial oxide layer514-x.

Referring toFIG. 15D, second oxidation conditions following the first oxidation conditions can create a bi-layer metal oxide, composed of a metal oxide514-0of a first stoichiometry or composition and a metal oxide514-1′ of a second, different stoichiometry or composition.

It is understood that any of the various process actions shown inFIGS. 13A to 15Ecan be combined or varied. Further, alternate embodiments can include the inclusion of additional layers to arrive at a desired vertically integrated memory cell. That is, the fabrication methods shown are intended as examples, and should not be construed as limiting.

It is also understood that other embodiments of this invention may be practiced in the absence of an element/step not specifically disclosed herein.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.