ERROR CORRECTION VIA ARTIFICIAL INTELLIGENCE

Apparatuses and methods related to error correction via artificial intelligence (AI) are described. An augmented reality (AR) display can be coupled to a memory device. AI circuitry coupled to the memory device can receive an error correction model. Prior to receipt of the error correction model by the AI circuitry, the error correction model can be trained, externally to the memory device and AI circuitry, to correct random errors introduced to execution of the AR AI workload in hazardous conditions. The AI circuitry can execute the model to perform error correction in association with execution of the AR AI workload.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and more particularly, to devices and methods related to error correction via artificial intelligence (AI).

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to error correction via artificial intelligence (AI). An AI workload (e.g., executing a model on AI circuitry) and/or overclocked memory (e.g., memory operating in an overclocked mode) can be particularly susceptible to random errors (e.g., random bit flips) because an AI workload or overclocked memory can push AI circuitry and memory to the edge of reliability. Hardware-based error correction (e.g., execution of error correction code (ECC)) may only correct a few errors (e.g., 1-2 flipped bits) per codeword. Execution of an AI workload can be affected environmental conditions, such as hazardous conditions, in which circuitry executing the AI workload operates. A non-limiting example of a hazardous condition can be radioactivity. Radiation can cause random errors (e.g., random bit flips) that ECC, for example, may not be able to account for and/or correct.

Some previous approaches to utilizing hardware-based error correction (e.g., via execution of ECC in the form of hardware circuitry) in hazardous and/or overclocking conditions may include memory sub-systems having additional (e.g., redundant) and/or specialized circuitry to compensate for effects associated with memory sub-system in hazardous conditions and/or at overclocking conditions. Although a robust memory output may be ensured by making use of memory redundancy and/or specialized error correction mechanisms, for example, such previous approaches lead to increases in hardware overheads and/or resource consumption such as increased size (e.g., die size), power, and energy. Such hardware overheads and/or resource consumption may be contrary to operation of a memory sub-system of a smart device that utilizes resources for processing and/or increasing processing capabilities of a memory sub-system of a smart device, for example.

Embodiments of the present disclosure address the above deficiencies and other deficiencies of previous approaches by utilizing software-based error correction, in addition to and/or instead of hardware-based error correction, to compensate for effects associated with operation of a memory sub-system, or a component thereof, in hazardous conditions and/or at overclocking. Embodiments of the present disclosure utilize AI circuitry to provide software-based error correction. For example, a neural network, implemented on AI circuitry of a memory sub-system, can execute a model (e.g., an error correction model) trained to provide error correction when the memory sub-system, or a component thereof, is in hazardous conditions and/or at overclocking. Some embodiments provide error correction capabilities similar to, or even improved relative to, that of memory redundancy and/or specialized error correction mechanisms of previous approaches. For example, software-based error correction described herein can correct multiple (e.g., more than two) bits in a set of data on which the software-based error correction is performed in contrast to hardware-based error correction that can only correct up to one or two bits with a single codeword.

As used herein, the singular forms “a,” “an,” and “the” include singular and plural referents unless the content clearly dictates otherwise. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, mean “including, but not limited to.” The term “coupled” means directly or indirectly connected.

FIG.1illustrates an example computing system100for error correction via AI in accordance with some embodiments of the present disclosure. The computing system100can include a host system120and a memory sub-system110can include media, such as one or more volatile memory devices (e.g., memory device140), one or more non-volatile memory devices (e.g., memory device130), or a combination of such.

The memory sub-system110can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM). In some embodiments, the memory sub-system110is an augmented reality (AR) device, such as an AR display.

The host system120can include a processor122and a software stack (not shown) executed by the processing sub-system. The processor122can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system120can include a memory124, in which an error correction model126can be stored. The host system120can be communicatively coupled (e.g., via a wireless interface) to the memory sub-system110. The host system120can be distinct from the memory sub-system110. In some embodiments, the host system120can be a cloud server, or a component thereof.

The host system120can be coupled to the memory sub-system110via an interface (e.g., a physical interface and/or a wireless interface). Examples of a physical interface can include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Universal Serial Bus (USB), or any other physical interface. Examples of a wireless interface can include, but are not limited to, a cellular interface, a Wi-Fi interface, a Bluetooth interface, or any other wireless interface. The interface can be used to transmit data between the host system120and the memory sub-system110. The host system120can further utilize an NVM Express (NVMe) interface to access the memory components (e.g., memory devices130) when the memory sub-system110is coupled with the host system120by the PCIe interface. The interface can provide a way for passing control, address, data, and other signals between the memory sub-system110and the host system120.FIG.1illustrates a memory sub-system110as an example. In general, the host system120can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

Some examples of non-volatile memory devices (e.g., the memory device130) include negative-and (NAND) type flash memory and write-in-place memory. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

In some embodiments, the local memory119can include memory registers storing memory pointers, fetched data, etc. The local memory119can also include read-only memory (ROM) for storing micro-code. While the memory sub-system110described in association withFIG.1includes the memory sub-system controller115, in at least one embodiment of the present disclosure, the memory sub-system110does not include the memory sub-system controller115and can rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system110).

In general, the memory sub-system controller115can receive commands or operations from the host system120and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device130and/or the memory device140. The memory sub-system controller115can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices130. The memory sub-system controller115can further include host interface (not shown) circuitry to communicate with the host system120via a physical host interface (not pictured). The host interface circuitry can convert the commands received from the host system into command instructions to access the memory device130and/or the memory device140as well as convert responses associated with the memory device130and/or the memory device140into information for the host system120.

From the perspective of a deep-learning execution pipeline, an error correction model (e.g., the model126) can be stacked on to a topmost (input) layer of a vision-based deep learning model. For instance, a deep neural network (DNN) model, can be trained to emulate (e.g., act as) error correction circuitry of the memory sub-system110via input of weights of a vision-based model with errors (e.g., random bit flips). As a result, the trained DNN model can output a bit stream with the errors corrected.

In some embodiments, the host system120can train a model (e.g., the error correction model126) to emulate execution of ECC to correct random errors from operating the memory sub-system110in hazardous conditions. The hazardous conditions can include a radioactive environment, such as subjecting the memory sub-system110, or one or more components thereof, to at least one hundred gray (Gy). The host system120can train a model126(e.g., an error correction model) to emulate execution of ECC to correct random errors from operating the memory sub-system110in an overclocked mode. During training of the model126, losses can be determined for backpropagation. The losses can be based on, for the same input data, the output of the model126and the output of executing ECC by the host system120. The host system120can include AI circuitry125to train the model126. The AI circuitry125can implement a DNN model. The memory sub-system110can be distinct from the host system120.

In some embodiments, the host system120can include an error generator (not shown). The error generator can provide, in association with training the model126, errors associated with one or more operating conditions associated with operating the memory device140in an overclocked mode and a type of the memory device140(e.g., DRAM). For instance, a DRAM-specific error generator can generate errors (e.g., random bitflips) and capture one or more characteristics and/or behaviors of the DRAM (e.g., the memory device140) when operating under a heavy workload, such as high temperatures and/or overclocking. Such training of an error correction model using deep learning can be for one or more particular types of DRAM. Knowledge of the type of DRAM with which an error correction model is to be used can be beneficial in choosing and/or training the error correction model.

The operating conditions can include, but are not limited to, one or more temperatures and/or clock frequencies of the memory device140associated with operating the memory device140in an overclocked mode. In some embodiments, the memory sub-system110can be a component of a gaming system (e.g., a mobile gaming system) or an AR system. A gaming system or AR system, among others, may frequently operate memory devices, such as the memory device140, in an overclocked mode to increase performance and data throughput.

The memory sub-system110includes AI circuitry113. Although the AI circuitry113is illustrated as a component of the memory device140, in some embodiments the AI circuitry113can be a different component of the memory sub-system110, such as a component of the memory sub-system controller115and/or the memory device130. AI circuitry can be configured to combine data using iterative processing and algorithms such that the AI circuitry learns from patterns and/or features in the data. A non-limiting example of AI circuitry can be a neural network. As used herein, “neural network” refers to software, hardware, or combinations thereof configured to process data in a manner similar to neurons of a human brain. Artificial neural networks can include various technologies such as deep learning and machine learning. As used herein, “machine learning” refers to an ability software, hardware, or combinations thereof to learn and improve from experience without improvements being explicitly programmed. As used herein, “deep learning” refers to machine learning methods based on artificial neural networks with representation learning (also referred to herein as DNNs), which can be supervised, semi-supervised or unsupervised. Deep learning can be a subset of AI. The low power, inexpensive design of deep learning accelerators (DLAs) can be implemented in internet-of-things (IoT) devices. The DLAs can process and make intelligent decisions at run-time. Memory devices including the edge DLAs can also be deployed in remote locations without cloud or offloading capability.

In some embodiments, the AI circuitry113can receive a model132(e.g., an error correction model) from the host system120. The model132can be the model125or based on the model125. The model132is trained, by the host system120, to emulate execution of ECC of the memory sub-system110. The AI circuitry113can be on-chip with a memory array (not shown) of the memory device140such that the memory device140comprises a system-on-chip (SoC). In some embodiments, the AI circuitry113can execute the trained model to perform software-based error correction instead of and/or in addition to hardware-based error correction of the memory sub-system110.

Random errors can occur on the memory device140in response to operating the memory sub-system110in one or more hazardous conditions. In some embodiments, the AI circuitry113can execute the model132in response the memory sub-system110, or one or more components thereof, operating in hazardous conditions. Execution of the model132provides software-based error correction. In some embodiments, execution of the trained model can provide software-based error correction in addition to hardware-based error correction of the memory sub-system110. The software-based error correction via execution of the model132can be distinct from other error correction capabilities (e.g., execution of ECC) of the memory sub-system110.

As described herein, random errors can occur on the memory device140in response to operating the memory device140in an overclocked mode. In some embodiments, the AI circuitry113can receive the model132(e.g., an error correction model) from the host system120. The model132can be trained, by the host120, to emulate execution of ECC of the memory sub-system110. The AI circuitry113can execute the model132to perform software-based error correction instead of and/or in addition to hardware-based error correction of the memory sub-system110in response to the memory device140operating in an overclocked mode. The software-based error correction via execution of the model132can be distinct from other error correction capabilities (e.g., execution of ECC) of the memory sub-system110.

Although not specifically illustrated byFIG.1, in some embodiments, the memory sub-system110can be a component of an AR device, such as an AR display. In some embodiments, the AR display is a component of personal protection equipment (PPE), which can be worn in hazardous conditions. The AI circuitry113can execute an AI workload associated with an AR device (e.g., an AR display) coupled to the memory sub-system110or of which the memory sub-system110is a component. Such an AI workload can be referred to herein as an AR AI workload. Execution of an AR AI workload by the AI circuitry113, for example, can include, but is not limited to, executing a model associated with AR functions, such as overlaying information on images where the information is based on those images. Data corresponding to the images and/or the information can be stored on the memory device140. Some embodiments include the AI circuitry113on-chip with the memory device140to facilitate communication of data from the memory device140to the AI circuitry113, ands vice versa, via increased throughput and more direct access to the data as compared to the AI circuitry113being not on-chip with the memory device140. In some embodiments, an error correction model can be trained such that inputting weights with random errors to an AR AI workload and executing the error correction model causes the AR AI workload to yield a same output as the AR AI workload would without the random errors.

FIG.2illustrates an example of a method250for error correction in hazardous conditions via AI in accordance with a number of embodiments of the present disclosure. The method250can be performed by AI circuitry, such as the AI circuitry125and/or the AI circuitry113and/or the host system120described in association withFIG.1. The method250can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or combinations thereof. One or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At252, the method250can include training, by a host system (e.g., the host system120), an error correction model (e.g., the model126) to emulate execution of ECC to correct random errors from operating a memory sub-system (e.g., the memory sub-system110) of an AR device (e.g., an AR display) in hazardous conditions. At254, the method250can include, subsequent to training the error correction model, communicating the error correction model from the host system to the AR device.

At256, the method250can include executing an AR AI workload on a DNN implemented on AI circuitry of the AR device. At258, the method250can include performing software-based error correction associated with executing the AR AI workload via executing the error correction model (e.g., the model132) on the DNN. Executing the AR AI workload can include executing a vision-based AI model to perform an AR function. Performing the software-based error correction can include executing the error correction model to emulate execution of the ECC to correct random errors introduced to execution of the vision-based AI model by the hazardous conditions.

Although not specifically illustrated, the method250can include, responsive to operating the AR device in non-hazardous conditions, performing hardware-based error correction via associated with the memory device via error correction circuitry of the AR device. The method250can include, responsive to operating the AR device in the hazardous conditions subsequent to operating the AR device in the non-hazardous conditions, switching from performing hardware-based error correction to performing software-based error correction. The method250can include, responsive to operating the AR device in the non-hazardous conditions subsequent to operating the AR device in the hazardous conditions, switching from performing software-based error correction to performing hardware-based error correction.

FIG.3illustrates an example of a method360for error correction for overclocking via AI in accordance with a number of embodiments of the present disclosure. The method360can be performed by AI circuitry, such as the AI circuitry125and/or the AI circuitry113and/or the host system120described in association withFIG.1. The method360can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or combinations thereof. One or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At362, the method360can include training, by a host system (e.g., the host system120), an error correction model (e.g., the model126) to emulate execution of ECC to correct random errors from operating a memory device (e.g., the memory device140) of a gaming device in an overclocked mode. At364, the method360can include subsequent to training the error correction model, communicating the error correction model from the host system to the gaming device. At366, the method360can include performing software-based error correction associated with operating the memory device in the overclocked mode via executing the error correction model (e.g., the model132) on a DNN implemented on AI circuitry of the memory device.

Although not specifically illustrated, the method360can include, responsive to operating the memory sub-system in a non-overclocked mode, performing hardware-based error correction associated with the memory device via error correction circuitry of the gaming device. The method360can include, responsive to operating the memory device in the overclocked mode subsequent to operating the memory device in the non-overclocked mode, switching from performing the hardware-based error correction to performing the software-based error correction. The method360can include, responsive to operating the memory device in the non-overclocked mode subsequent to operating the memory device in the overclocked mode, switching from performing the software-based error correction to performing the hardware-based error correction.

FIG.4illustrates an example machine of a computer system480within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system480can correspond to a host system (e.g., the host system120described in association withFIG.1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system110) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the AI circuitry125and/or the AI circuitry113). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The example computer system480includes a processing device482, a main memory484(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory486(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system488, which communicate with each other via a bus490.

The data storage system488can include a machine-readable storage medium498(also known as a computer-readable medium) on which is stored one or more sets of instructions492or software embodying any one or more of the methodologies or functions described herein. The instructions492can also reside, completely or at least partially, within the main memory484and/or within the processing device482during execution thereof by the computer system480, the main memory484and the processing device482also constituting machine-readable storage media. The machine-readable storage medium498, data storage system488, and/or main memory484can correspond to the memory sub-system110.

In some embodiments, the instructions492can include instructions to implement functionality corresponding to AI circuitry (e.g., the AI circuitry125, the AI circuitry113) executable by a processing device (e.g., the processing device482). In some embodiments, the instructions492can include instructions to, responsive to an AR device including a memory device and a DLA coupled thereto operating in hazardous conditions, perform software-based error correction via execution of a model on the DLA. The hazardous conditions causes random errors to occur in the memory device. The hazardous conditions can include subjecting to the AR device to at least one hundred Gy of radiation and/or at least 100 degrees Celsius (° C.), for example.

In some embodiments, the instructions492can include instructions to, responsive to a memory device operating in an overclocked mode, perform software-based error correction via execution of a model on a DLA coupled to the memory device. The model emulates execution of ECC by the memory device and/or error correction circuitry coupled thereto. The instructions492can include instructions to train the model prior to operating the memory device in the overclocked mode. The instructions492can include instructions to execute the model to correct random errors associated with a temperature and/or a clock frequency associated with operating the memory device in the overclocked mode. The instructions492can include instructions to execute the model to correct errors associated with operating the memory device in the non-overclocked mode.