PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

At least some embodiments of the present disclosure relate to an electronic structure. The package structure includes a lead frame, an electronic component, and a conductive wire physically and electrically connecting the electronic component to the lead frame. An elevation of a first end of the conductive wire is substantially equal to an elevation of a second end of the conductive wire.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a package structure and a method of manufacturing the same. More particularly, the present disclosure relates to a package structure including a lead frame and a method of manufacturing the same.

2. Description of the Related Art

In Flat No leads packaging, such as Quad Flat No leads (QFN), a height of a wire loop and thickness of a molding compound may cause thickening of the package. However, current trends in the industry prefer packages to be as thin as possible.

SUMMARY

In some embodiments, according to one aspect, a package structure includes a lead frame, an electronic component, and a conductive wire physically and electrically connecting the electronic component to the lead frame. An elevation of a first end of the conductive wire is substantially equal to an elevation of a second end of the conductive wire.

In some embodiments, according to another aspect, a package structure includes an electronic component and at least one pin disposed around the electronic component. The at least one pin has a top surface, a bottom surface opposite to the top surface, a first lateral surface extending between the top surface and the bottom surface, and a second lateral surface opposite to the first lateral surface. The first lateral surface faces the electronic component. A roughness of the first lateral surface of the at least one pin is greater than a roughness of the second lateral surface of the at least one pin.

In some embodiments, according to another aspect, a method is disclosed for manufacturing a package structure. The method includes: providing a lead frame, the lead frame defining a space extending through the lead frame; disposing the lead frame on a temporary carrier; attaching an electronic component to the temporary carrier; forming at least one bonding wire to electrically connect the electronic component to the lead frame; encapsulating the lead frame, the at least one bonding wire, and the electronic component with an encapsulant; removing the temporary carrier; and back-etching the lead frame to form a plurality of pins

DETAILED DESCRIPTION

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom.” “vertical,” “horizontal.” “side,” “higher,” “lower,” “upper.” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of the embodiments of this disclosure are not deviated from by such arrangement.

FIG.1Ais a top view of a package structure1according to some embodiments of the present disclosure.FIG.1Bis a cross-sectional view of the package structure1taken along line A-A′ ofFIG.1A. The package structure1may be an electronic device, a semiconductor device package or a semiconductor package device.

The package structure1may include a lead frame10, an electronic component11, a plurality of conductive wires121,122,123and an encapsulant13.

The lead frame10may include at least one pin101, at least one conductive pad102, and at least one conductive pad103. For example, the lead frame10may include a plurality of pins101, a plurality of conductive pads102, and a plurality of conductive pads103. The pins101may be physically separated from each other and/or electrically insulated from each other. The conductive pad102is disposed on a top surface101tof the pin101, and may be also referred to as a first conductive pad, a top conductive pad or an upper conductive pad. The conductive pad102has a top surface102t. The top surface102tof the conductive pad102and a second top surface11t2of the electronic component11may be substantially coplanar with each other. That is, the top surface102tof the conductive pad102may be substantially aligned with the second top surface11t2of the electronic component11. An elevation of the top surface102tof the conductive pad102is substantially equal to an elevation of the second top surface11t2of the electronic component11. In addition, the conductive pad103is disposed on a bottom surface101bof the pin101, and may be also referred to as a second conductive pad, a bottom conductive pad or a lower conductive pad. The conductive pad103has a bottom surface103b. The bottom surface103bof the conductive pad103and a bottom surface113bof an adhesive layer113may be substantially coplanar with each other. That is, the bottom surface103bof the conductive pad103may be substantially aligned with the bottom surface113bof the adhesive layer113. In some embodiments, a vertical distance between the top surface102tof the conductive pad102and the bottom surface103bof the conductive pad103may be substantially equal to a vertical distance between the second top surface11t2of the electronic component11and the bottom surface113bof the adhesive layer113.

The pin101closest to the left side/right side of the electronic component11has a top surface101t, a bottom surface101bopposite to the top surface101t, a first lateral surface101s1connected to the top surface101t, a second lateral surface101s2connected to the first lateral surface101s1, a third lateral surface101s3connected to the first lateral surface101s1, and a fourth lateral surface101s4opposite to the third lateral surface101s3and connected to the second lateral surface101s2. The first lateral surface101s1of the pin101may be a vertical surface, and may be located above the third lateral surface101s3. The second lateral surface101s2, third lateral surface101s3, and the fourth lateral surface101s4of the pin101may be curved. The second lateral surface101s2may be located above the fourth lateral surface101s4so that a lower portion of the second lateral surface101s2and an upper portion of the fourth lateral surface101s4may collectly define a protrusion101a. As shown inFIG.1B, the pin101closest to the left side/right side of the electronic component11has one protrusion101afacing away the electronic component11. The conductive pad102may partially cover the top surface101tof the pin101closest to the left side/right side of the electronic component11. The conductive pad103may completely cover the bottom surface101bof the pin101closest to the left side/right side of the electronic component11.

In some embodiments, the protrusion101amay be a curve portion101aof the pin101. The curve portion101ahas an apex point intersected by the second lateral surface101s2and the fourth lateral surface101s4. A shape of the curve portion101amay be a bird's beak. An elevation of a horizontal imaginary line104between two apexes of two adjacent curve portions101ais between the second top surface11t2of the electronic component11and a bottom surface11bof the electronic component11. An elevation of the curve portion101ais between the second top surface11t2and the bottom surface11bof the electronic component11.

In some embodiments, the conductive pad102on the pin101closest to the left side/right side of the electronic component11has a width D1, and that the conductive pad102on the pin101far away from the electronic component11has a width D2which is greater than the width D1. In some embodiments, the widths D1, D2may be the same.

The first lateral surface101s1and the third lateral surface101s3face the electronic component11. A surface roughness (Ra) of the first lateral surface101s1of the pin101may be greater than a surface roughness of the second lateral surface101s2of the pin101since the first lateral surface101s1of the pin101may be formed by punching, and the second lateral surface101s2of the pin101may be formed by etching. Further, the surface roughness of the first lateral surface101s1of the pin101may be greater than a surface roughness of the third lateral surface101s3of the pin101and a surface roughness of the fourth lateral surface101s4of the pin101since the first lateral surface101s1of the pin101may be formed by punching, and the third lateral surface101s3of the pin101and the fourth lateral surface101s4of the pin101may be formed by etching.

A projection of the electronic component11may be free from overlapping a projection of the lead frame10in a top view. That is, the electronic component11may be not disposed on the lead frame10. There may be no portion of the lead frame10located right under the electronic component11. The electronic component11may include a cap111, a membrane112, and the adhesive layer113. The adhesive layer113is disposed on the bottom surface11bof the electronic component11and exposed to air. In some embodiments, the adhesive layer113is a die attach film. The adhesive layer113may include a thermosetting resin or a thermoplastic resin. A material of the adhesive layer113may be different from a material of the encapsulant13. The adhesive layer113may protect the bottom surface11bof the electronic component11. In some embodiments, the adhesive layer113may be omitted, such that the bottom surface11bof the electronic component11is exposed by the encapsulant13. The cap111may have a first top surface11t1and may define a cavity11c. The cap111is disposed over the second top surface11t2of the electronic component11and electrically connected to the second top surface11t2of the electronic component11. The membrane112is disposed over the second top surface11t2of the electronic component11and in the cavity11c.

In some embodiments, the electronic component11may include, e.g., a MEMS package, a MEMS microphone, or a MEMS gas sensor.

The package structure1may include a die attach region11A (or a die security region). The die attach region11A may be arranged at a central portion of the package structure1, and the pin(s)101may be disposed around the die attach region11A. In some embodiments, the first lateral surface101s1of the pin101may be a portion of an edge of the die attach region11A. The electronic component11may be disposed in the die attach region11A. Thus, the electronic component11may be disposed between two first lateral surfaces101s1of the pins101. The die attach region11A may be large enough to accommodate the electronic component11. The pins101of the lead frame10may be disposed around the electronic component11. The die attach region11A has a width W1. In some embodiments, the width W1may be equal to a distance between two first lateral surfaces101s1of the pins101. A distance W2is defined as a distance between the left side of the die attach region11A and the left side of the package structure1. A distance W3is defined as a distance between the right side of the die attach region11A and the right side of the package structure1. The width W1may be greater than the distance W2. The width W1may be greater than the distance W3. The distance W2may be equal to or different from the distance W3.

The conductive wires121,122,123(or bonding wires) physically and electrically connect the electronic component11to the lead frame10. The conductive wire121electrically connects the second top surface11t2of the electronic component11to the top surface102tof conductive pad102. The conductive wire122electrically connects the second top surface11t2of the electronic component11to the top surface102tof the conductive pad102closest to the left side/right side of the electronic component11. An elevation of a first end of the conductive wire121at the top surface102tof the conductive pad102on the most left side pin101is substantially equal to an elevation of a second end of the conductive wire121at the second top surface11t2of the electronic component11. An elevation of a first end of the conductive wire122at the top surface102tof the conductive pad102on the pin101closest to the left side/right side of the electronic component11is substantially equal to an elevation of a second end of the conductive wire122at the second top surface11t2of the electronic component11. An apex point of the conductive wire121is higher than an apex point of the conductive wire122. A height of a loop of each conductive wires121,122may be decreased. The conductive wire123electrically connects the first top surface11t1of the electronic component11to the top surface102tof the most right side pin101. An apex point of the conductive wire123is higher than the apex point of the conductive wire121. The conductive wire123is electrically connected to ground.

The encapsulant13encapsulates the lead frame10and the electronic component11. The encapsulant13encapsulates the conductive wires121,122,123. The encapsulant13is in contact with the first lateral surface101s1of the pin101and spaced apart from the third lateral surface101s3of the pin101. A bottom portion of the encapsulant13is spaced apart from the pin101closest to the electronic component11. The bottom portion of the encapsulant13may include a first lateral surface13s1, a second lateral surface13s2connected to the first lateral surface13s1, and a first bottom surface13b1connected to the second lateral surface13s2. The first lateral surface13s1of the encapsulant13may be substantially aligned with the first lateral surface101s1of the pin101. The first bottom surface13b1of the encapsulant13may be substantially aligned with the bottom surface103bof the conductive pad103. The first bottom surface13b1of the encapsulant13may be substantially aligned with the bottom surface113bof the adhesive layer113.

The third lateral surface101s3of the pin101and the first lateral surface13s1of the encapsulant13collectively define a pin recess105recessed from the first lateral surface101s1of the pin101. The second lateral surface13s2of the encapsulant13defines a molding recess133recessed from the first lateral surface13s1of the encapsulant13and the first bottom surface13b1of the encapsulant13. The pin recess105faces the molding recess133. The pin recess105is in communication with the molding recess133. A size of the pin recess105may be greater than a size of the molding recess133. Alternatively, a capacity volume of the pin recess105may be greater than a capacity volume of the molding recess133. A highest end of the pin recess105may be higher than a highest end of the molding recess133. In some embodiments, the second lateral surface13s2of the encapsulant13and the molding recess133may be omitted, and the first lateral surface13s1of the encapsulant13may be perpendicular to the first bottom surface13b1of the encapsulant13.

The encapsulant13may include a protruding portion134having a second bottom surface13b2. The protruding portion134of the encapsulant13protrudes beyond the horizontal imaginary line104between two adjacent curve portions101a. The protruding portion134of the encapsulant13extends beyond the curve portion101aof the pin101. An elevation of the second bottom surface13b2of the protruding portion of the encapsulant13is higher than an elevation of the first bottom surface13b1of the encapsulant13. The elevation of the second bottom surface13b2of the encapsulant13is between the second top surface11t2of the electronic component11and the bottom surface11bof the electronic component11. A profile of the protruding portion134of the encapsulant13filled between adjacent pins101is conformal to the pins101. The shape of the second bottom surface13b2of the protruding portion134of the encapsulant13is curved. In some embodiments, a thickness of the encapsulant13may be defined as a vertical distance between a top surface of the encapsulant13and the first bottom surface13b1of the encapsulant. Such thickness of the encapsulant13may define a total thickness of the package structure1.

Since the electronic component11is disposed between the pins101of the lead frame10rather than arranged above/on the lead frame10, a thickness of the encapsulant13can be minimized. Accordingly, a size (e.g., the total thickness) of the package structure1is minimized.

FIG.1Cis a cross-sectional view of a package structure1′ in accordance with some embodiments of the present disclosure. The package structure1′ is similar to the package structure1inFIG.1Bexcept that an electronic component15is disposed above the electronic component11.

The electronic component15is disposed above the electronic component11through an adhesive layer151. A material of the adhesive layer151is the same as that of the adhesive layer131. In some embodiments, the electronic component15may include one or more of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a controller, a processor, or other electronic components or semiconductor devices. The electronic component15(e.g., an ASIC device) may be used, for example, to collect the information obtained by the electronic component11(e.g., a MEMS device), and transmit or process the information in an analog or digital form.

FIG.1Dis a top view of a package structure1″ in accordance with some embodiments of the present disclosure.FIG.1Eis a cross-sectional view of the package structure1″ taken along line C-C′ ofFIG.1D. The package structure1″ is similar to the package structure1inFIG.1AandFIG.1B, except that the pin101closest to the left side/right side of the electronic component11includes a curve portion101a. The pin101closest to the left side/right side of the electronic component11has a top surface101t, a bottom surface101bopposite to the top surface101t, a first lateral surface101s5connected to the top surface101t, a second lateral surface101s2connected to the top surface101t, a third lateral surface101s3connected to the first lateral surface101s5, and a fourth lateral surface101s4opposite to the third lateral surface101s3and connected to the second lateral surface101s2. The first lateral surface101s5, the second lateral surface101s2, the third lateral surface101s3, and the fourth lateral surface101s4of the pin101may be curved. A lower portion of the first lateral surface101s5and an upper portion of the third lateral surface101s3may collectly define the curve portion101a. In addition, and the first lateral surface13s1of the encapsulant13may be perpendicular to and connected to the first bottom surface13b1of the encapsulant13.

FIG.1Fis a cross-sectional view of a package structure1′″ according to some embodiments of the present disclosure. The package structure1′″ ofFIG.1Fis similar to the package structure1″ ofFIG.1E, except that the adhesive layer113of FIG E is omitted and the bottom surface103bof the conductive pad103, the bottom surface11bof the electronic component11and the first bottom surface13b1of the encapsulant13are substantially aligned with each other.

FIG.2Ais a top view of a semiconductor device package2according to some embodiments of the present disclosure.FIG.2Bis a cross-sectional view of the package structure2taken along line B-B′ ofFIG.2A. The package structure2may be an electronic device, a semiconductor device package or a semiconductor package device.

The package structure2includes a lead frame20, an electronic component21, a plurality of conductive wires221,222,223, and an encapsulant23. The configurations of the conductive wires221,222,223are similar to those of the conductive wires121,122,123ofFIG.1B. The encapsulant23covers a plurality of conductive pads202of the lead frame20, a plurality of curve portions201aof the lead frame20, and a plurality of extension portions201′eof the lead frame20.

The structure of the lead frame20is similar to the structure of the lead frame10. The lead frame20includes at least one pin201, at least one pin201′, at least one conductive pad202, and at least one conductive pad203. The pin201is closest to the left side/right side of the electronic component21. The pin201′ is adjacent to a periphery of the lead frame20.

The conductive pad202is disposed on a top surface201tof the pin201. The conductive pad202has a top surface202t. The top surface202tof the conductive pad202and the second top surface21t2of the electronic component21are substantially coplanar with each other or aligned with each other. The conductive pad203is disposed on a bottom surface201bof the pin201. The conductive pad203has a bottom surface203b. The bottom surface203bof the conductive pad203and the bottom surface21bof the electronic component21are substantially coplanar with each other or aligned with each other.

The pin201includes a curve portion201a. The pin201has the top surface201t, the bottom surface201bopposite to the top surface201t, a first lateral surface201s1extending between the top surface201tand the bottom surface201b, a second lateral surface201s2opposite to the first lateral surface201s1, and a third lateral surface201s3opposite to the first lateral surface201s1and extending from the second lateral surface201s2. The first lateral surface201s1of the pin201is a vertical surface. The second lateral surface201s2and the third lateral surface201s3are curved. The pin201has a curve portion201afacing away the electronic component21. The conductive pad202partially covers the top surface201tof the pin201. The conductive pad203partially covers the bottom surface201bof the pin201.

The first lateral surface201s1faces the electronic component21. A surface roughness (Ra) of the first lateral surface201s1of the pin201is greater than a roughness of the second lateral surface201s2of the pin201. The surface roughness of the first lateral surface201s1of the pin201is greater than a roughness of the third lateral surface201s3of the pin201.

Similarly, the pin201′ includes a curve portion201′a. The pin201′ includes an extension portion201′eextending to a periphery of the encapsulant23or a lateral surface of the package structure2. A position of the extension portion201′eis relatively higher than that of the curve portion201′a. The pin201′ has a top surface201′t, a bottom surface201′bopposite to the top surface201′t, a first lateral surface201′s1connected to the top surface201′t, a second lateral surface201′s2opposite to the first lateral surface201′s1, a third lateral surface201′s3connected to the first lateral surface201′s1, and a fourth lateral surface201′s4connected to the second lateral surface201′s2. The second lateral surface201′s2of the pin201(or the extension portion201′e) is a vertical surface and may be aligned with a lateral surface of the encapsulant23. The first lateral surface201′s1, the third lateral surface201′s3, and the fourth lateral surface201′s4are curved. The pin201′ has a curve portion201′afacing the electronic component21.

The package structure2has a die attach region21A (or a die security region). The die attach region21A may be arranged at a central portion of the package structure2, and the pin(s)201,201′ may be disposed around the die attach region21A. The die attach region21A has a width W1′. In some embodiments, the width W1′ may be equal to a distance between two first lateral surfaces201s1of the pins201. A distance W2′ is defined as a distance between the left side of the die attach region21A and the left side of the package structure2. A distance W3′ is defined as a distance between the right side of the die attach region21A and the right side of the package structure2. The width W1′ may be greater than the distance W2′. The width W1′ may be greater than the distance W3′. The distance W2′ may be equal to or different from the distance W3′.

The electronic component21includes a cap211and a membrane212. The cap211has a first top surface21t1and defines a cavity21c. The electronic component21has a second top surface21t2and a bottom surface21bopposite to the second top surface21t2. The configurations of the electronic component21are similar to those of the electronic component11ofFIG.1B, except that there is no adhesive layer under the electronic component21.

The encapsulant23completely encapsulates the lead frame20, the electronic component21and the conductive wires221,222,223. The encapsulant23completely encapsulates the pins201,201′. The encapsulant23encapsulates the first lateral surface201s1, the second lateral surface201s2, and the third lateral surface201s3of the pin201. The encapsulant23encapsulates the exposed top surface201tand the exposed bottom surface201bof the pin201. The encapsulant23encapsulates the first lateral surface201′s1, the third lateral surface201′s3, and the fourth lateral surface201′s4of the pin201′. The encapsulant23encapsulates the exposed top surface201′tof the pin201′.

Since the electronic component21is disposed between the pins201of the lead frame20rather than arranged above/on the lead frame20, a thickness of the encapsulant23can be minimized. Accordingly, a size (e.g., the total thickness) of the package structure2is minimized.

FIG.2Cis a cross-sectional view of a package structure2′ in accordance with some embodiments of the present disclosure. The package structure2′ is similar to the package structure2inFIG.2Bexcept that a position of an extension portion201′fof the pin201′ is relatively lower than that of a curve portion201′aof the pin201′.

FIG.2Dis a cross-sectional view of a package structure2″ in accordance with some embodiments of the present disclosure. The package structure2″ is similar to the package structure2inFIG.2Bexcept that a conductive pad203′ is exposed rather than encapsulated by the encapsulant23.

Accordingly, the bottom surface21bof the electronic component21, the bottom surface201bof the pin201, the bottom surface201′bof the pin201′, and the bottom surface23bof the encapsulant23are substantially coplanar with each other or aligned with other. A bottom surface203′bof the conductive pad203′ is lower than the bottom surface23bof the encapsulant23.

In some embodiments, the conductive pad203′ may include a solder material, such as tin (Sn). The conductive pad203′ may facilitate following soldering operations for connecting the package structure2″ to other elements, such as a main board.

FIG.2Eis a cross-sectional view of a package structure2′″ in accordance with some embodiments of the present disclosure. The package structure2′ is similar to the package structure2″ inFIG.2Dexcept that there is an encapsulant boundary23b2connected between the curve portion201′aof the pin201′ and the curve portions201aof the pin201.

FIGS.3A through3Hillustrate some embodiments of a method of manufacturing the package structure1ofFIG.1Baccording to some embodiments of the present disclosure.

Referring toFIG.3AandFIG.3B, whereinFIG.3Ashows a cross-sectional view of a structure taken along line D-D′ ofFIG.3B, a lead frame10is provided. The lead frame10includes a base material106, at least one pin101, at least one conductive pad102, and at least one conductive pad103and a die attach region11A (or a die security region). The pin101protrudes from the base material106. The pin101has a lateral surface101s2. The patterned conductive pad102is formed or disposed on a top surface101tof the pin101. The patterned conductive pad102has a top surface102t. The patterned conductive pad103is formed or disposed on a bottom surface101bof the lead frame10. The patterned conductive pad103has a bottom surface103b. The patterned conductive pad103may be used for the following soldering operation. In some embodiments, the patterned conductive pads102,103may include copper (Cu), a copper (Cu) alloy or other suitable materials.

The die attach region11A (or a die security region) is located at a central portion of the lead frame10or a portion adjacent to the central portion of the lead frame10. The die attach region may be predetermined or predefined. The lead frame10has an etching region33A. The predefined die attach region and the region extending between the patterned conductive pad102and the die attach region are unetched. An elevation of a top surface of the die attach region is higher than an elevation of the etching region33A. The die attach region is large enough to facilitate die-attaching process during the following operation. In some embodiments, the die attach region may be square or rectangular.

The lead frame10defines an empty space301formed by an etching operation. The space301extends through the lead frame10. That is, a portion of an upper portion of the lead frame10is etched, and the base material106, the pin101and the die attach region11A remain. The etching region33A and the space301are both formed by etching operations.

Referring toFIG.3C, an accommodation space303is formed by a punch operation. The accommodation space303extends through the lead frame10for accommodating an electronic component11(FIG.3E). A position of the accommodation space303may correspond to the die attach region11A ofFIG.3AandFIG.3B. A central portion of the lead frame10(corresponding to the die attach region11A) is removed by the punch operation one time for saving costs. The lead frame10has a lateral surface101s1after the punch operation. That is, the lateral surface101s1is formed due to the punch operation. Thus, the accommodation space303is defined by the lateral surface101s1of the lead frame10. A surface roughness of the lateral surface101s1of the lead frame10is greater than a surface roughness of the lateral surface101s2of the pin10of the lead frame10due to a process difference between the punch operation and the etching operation.

The lead frame10has a first portion corresponding to a distance W2as shown inFIG.3Band a second portion corresponding to a distance W3as shown inFIG.3Bafter the punching operation. A width of the space303is greater than a width of the first portion of the lead frame10.

Referring toFIG.3D, the lead frame10is disposed on a temporary carrier30. In some embodiments, the temporary carrier30may be a tape. The conductive pads103of the lead frame10are pressed into the temporary carrier30. An adhesive of the temporary carrier completely covers the conductive pads103. The adhesive of the temporary carrier30may be in contact with the bottom surface101bof the lead frame10. A portion of the adhesive may be a protruding portion305. The protruding portion305of the temporary carrier30protrudes into a vertical projection of the accommodation space303. That is, the protruding portion305of the temporary carrier30may be located between two opposite lateral surface101s1of the lead frame10.

Referring toFIG.3E, an electronic component11is disposed on the temporary carrier30in the accommodation space303. In some embodiments, an adhesive layer113is applied on a bottom surface11bof the electronic component11. Thus, the electronic component11is attached to the temporary carrier30through the adhesive layer113. A bottom surface113bof the adhesive layer113and the bottom surface103bof the conductive pad103are substantially coplanar with each other or aligned with each other. The electronic component11has a cap111and a membrane112. The cap111defines a cavity11cto accommodate the membrane112. The electronic component11includes a first top surface11t1, a second top surface11t2, and a bottom surface11bopposite to the second top surface11t2, wherein the second top surface11t2is between the first top surface11t1and the bottom surface11b. The second top surface11t2of the electronic component11and the top surface102tof the conductive pad102are substantially coplanar with each other or aligned with each other. In some embodiments, the electronic component11may include, e.g., a MEMS package, a MEMS microphone, or a MEMS gas sensor.

Referring toFIG.3F, conductive wires121,122,123are formed or provided to electrically connect the electronic component11to the lead frame10. An elevation of a first end of the conductive wire121at the top surface102tof the conductive pad102is substantially equal to an elevation of a second end of the conductive wire121at the second top surface11t2of the electronic component11. An elevation of a first end of the conductive wire122at the top surface102tof the conductive pad102is substantially equal to an elevation of a second end of the conductive wire122at the second top surface11t2of the electronic component11. A height of a loop of each conductive wires121,122may be decreased.

The conductive wires121,122,123may be provided by a reverse bonding operation. For example, the first end of the conductive wire121may be first provided at the top surface102tof the conductive pad102, and then the second end of the conductive wire121is provided to the second top surface11t2of the electronic component11. That is, the first end of the conductive wire121is a first bond, and the second end of the conductive wire121is a second bond. Apex points of the conductive wires121,122,123may be as low as possible by using the reverse bonding operation.

In some embodiments, a forward bonding operation may be performed based on needs. For example, a first end of the conductive wire123may be first provided at the first top surface11t1of the electronic component11, and then a second end of the conductive wire123is provided to the top surface102tof the conductive pad102.

Referring toFIG.3G, an encapsulant13is provided by a molding operation. The encapsulant13encapsulates the lead frame10, the electronic component11, and the conductive wires121,122,123. The encapsulant13has a bottom surface13b1, a first lateral surface13s1, and a second lateral surface13s2. The first lateral surface13s1of the encapsulant13is vertical and the second lateral surface13s2of the encapsulant13is curved. The first lateral surface13s1of the encapsulant13contacts the lateral surface101s1of the lead frame10. The second lateral surface13s2of the encapsulant13is conformal to the protruding portion305of the temporary carrier30. The bottom surface13b1of the encapsulant13and the bottom surface113bof the adhesive layer113are substantially coplanar with each other or aligned with each other.

Referring toFIG.3H, the temporary carrier30is removed. The second lateral surface13s2of the encapsulant13and the bottom surface113bof the adhesive layer113are exposed after removal of the temporary carrier30. Meanwhile, a molding recess133of the encapsulant13is formed.

Subsequently, a back-etching operation is performed to the base material106of the lead frame10. The package structure1ofFIG.1Bis formed. A total thickness t of the package structure1depends on a thickness of the electronic component11and a thickness of encapsulant13. For example, the total thickness of the package structure1is determined by the maximum thickness of the encapsulant13(e.g., a distance between a top surface of the encapsulant13and a bottom surface13b1of the encapsulant13.

A plurality of pins101with respective curve portions101are formed through the back-etching operation. A protruding portion of the encapsulant13including a second bottom surface13b2is formed. The protruding portion of the encapsulant13extends beyond the curve portion101aof the pin101. Meanwhile, a third lateral surface101s3of the pin101and a pin recess105are formed. As shown inFIG.1B, the third lateral surface101s3of the pin101and the first lateral surface13s1of the encapsulant13collectively define a pin recess105. The pin recess105is in communication with the molding recess133.

In some embodiments, the package structures1′,2,2′, and2″ may be formed by operations similar to those ofFIGS.3A through3H.

FIGS.4A through4Fillustrate some embodiments of a method of manufacturing the package structure1″ ofFIG.1Eaccording to some embodiments of the present disclosure.

Referring toFIG.4A, a method of manufacturing the package structure1″ includes providing a lead frame10. The structure of the lead frame10ofFIG.4Ais similar to the structure of the lead frame10ofFIG.3A, except that a central portion of the lead frame10ofFIG.4Ais partially etched to form a lateral surface101s5. The central portion of the lead frame10remains a portion of the base material106. Similar to empty space301ofFIG.3A, an empty space401is formed by an etching operation.

Referring toFIG.4B, similar to the structure ofFIG.3C, a punch operation is performed to form an accommodation space403.

Referring toFIGS.4C through4E, the operations ofFIGS.4C through4Eare similar to those ofFIGS.3D through3H, except that a patterned conductive pad103of the lead frame10ofFIGS.4C through4Eis disposed over a carrier40. For example,FIG.4Cshows an attaching operation.FIG.4Dshows a die attaching operation.FIG.4Eshows a molding operation.

Referring toFIG.4F, de-carrier operation is performed. Subsequently, a back etching operation is performed to form a plurality of pins101and expose a back surface of an encapsulant13. After performing the back etching operation, the package structure1″ is formed.

FIGS.5A through5Eillustrate some embodiments of a method of manufacturing the package structure2according to some embodiments of the present disclosure.

Referring toFIG.5A, a method of manufacturing the package structure2includes providing a lead frame20. The lead frame20includes a pin201, a patterned conductive pad202, and a patterned conductive pad203. The patterned conductive pad202is formed on a top surface201tof the lead frame20. The patterned conductive pad202has a top surface202t. The patterned conductive pad203is formed on a bottom surface201bof the lead frame20. The patterned conductive pad203has a bottom surface203b. The patterned conductive pad203may be used for the following soldering operation. The lead frame20includes a plurality of openings401formed by an etching operation. The opening401has a lateral surface201s2. In some embodiments, the patterned conductive pad202and the patterned conductive pad203may be conductive pads.

Referring toFIG.5B, a space403is formed by a punch operation or an etching operation. The space403is defined by the lead frame20. A central portion of the lead frame20is removed by the punch operation one time for saving costs. A back etching operation is performed to form at least one pin201closest to the space403and at least one pin201′ adjacent to the at least one pin201.

The pin201has the lateral surface201s1, a lateral surface201s2, and a lateral surface201s3. The pin201′ has the lateral surface201′s1, a lateral surface201′s2, a lateral surface201′s3, and a lateral surface201′s4. The pin201includes a lateral surface201s1after the punch operation. The pin201includes a lateral surface201s3after the back etching operation. The pin201′ includes lateral surfaces201′s3,201′s4after the back etching operation.

The pin201has a curve portion201adefined by the lateral surface201s2and the lateral surface201s3. The pin201′ has a curve portion201′adefined by the lateral surface201′s1and the lateral surface201′s3.

A roughness of the lateral surface201s1of the lead frame20is greater than a roughness of the lateral surface201s2of the lead frame20due to an operation difference between the punch operation and the etching operation.

Referring toFIG.5C, the lead frame20is disposed above a temporary carrier40. In some embodiments, the temporary carrier40may be a tape. The conductive pads203of the lead frame20are over the temporary carrier40.

Referring toFIG.5D, an electronic component21is attached to the temporary carrier40. A bottom surface21bof the electronic component21and the bottom surface203bof the conductive pad203are substantially coplanar. The electronic component21has a cap211and a membrane212. The cap211defines a cavity21cto accommodate the membrane212. The electronic component21includes a first top surface21t1, a second top surface21t2, and a bottom surface21bopposite to the second top surface21t2, wherein the second top surface21t2is between the first top surface21t1and the bottom surface21b. The second top surface21t2of the electronic component21and the top surface202tof the conductive pad202are substantially coplanar. In some embodiments, the electronic component21may include, e.g., a MEMS package, a MEMS microphone, or a MEMS gas sensor.

Referring toFIG.5E, bonding operations and molding operations ofFIG.5Eare similar to those ofFIG.3G. After the bonding operations and molding operations are completed, the carrier40is removed to form the package structure2.

FIGS.6A through6Eillustrate some embodiments of a method of manufacturing the package structure2″ according to some embodiments of the present disclosure. The operations ofFIGS.6A through6Eare similar to those ofFIGS.5A through5E, except that the lead frame20ofFIGS.6A through6Ehas no patterned conductive pad203. For example.FIG.6Ashows providing a lead frame20.FIG.6Bshows a back-etching operation.FIG.6Cshows an attaching operation.FIG.6Dshows a die attaching operation.

Referring toFIG.6E, a respective conductive pad203′ is correspondingly formed on a back surface201bof a pin201or a back surface201′bof a pin201′ by a soldering operation. A bottom surface203′bof the conductive pad203′ is lower than a bottom surface23bof an encapsulant23. In some embodiments, the conductive pad203′ may include a solder material, such as tin (Sn). After the formation of the conductive pad203′, the package structure2″ is formed.