System and a method for a line encoded data stream

A system that receives a line encoded data stream from a source. The system has a de-serializer for de-serializing a line encoded data stream to generate a raw parallel data stream. The system has a serializer for serializing the raw parallel data stream. The system has a parallel data generator configured to generate another raw parallel data stream. The system has reconfigurable circuitry for communicating the raw parallel data stream to the serializer in a configuration and communicating the other parallel data stream in another configuration.

The present application is a National Phase entry of PCT Application No. PCT/AU2016/050750, filed Aug. 12, 2016, which claims the benefit of Australian Provisional Patent Application No. 2015903229, filed Aug. 12, 2015, which are incorporated herein by reference.

TECHNICAL FIELD

The disclosure herein generally relates to a system and a method, and particularly but not exclusively to a system and a method for modifying a line encoded data stream.

BACKGROUND

Information may be carried in a computer network by a line encoded data stream. The information may be arranged into Ethernet packets transporting Ethernet frames. Each Ethernet frame is generally proceeded by a preamble and start frame delimiter, for example, which are generally both part of the Ethernet packet. The line encoded data stream may be transmitted along a network cable in the form of an optical fibre network cable or an electrical network cable (“copper network cable”), or wirelessly transmitted.

In some circumstances, it may be desirable to modify a line encoded data stream. An example of modifying a line encoded data stream is filtering the line encoded data stream.

Some technologies may simply not function unless communications latency is sufficiently small. In other applications, the latency of a communication may be, in some circumstances, an important factor in securing a favourable outcome. For example, being the first to have a complete electronic trade order received by a stock exchange may establish trade priority. Advantage can then be taken of favourable prices for financial instruments, examples of which include but are not limited to shares, derivatives and futures. Being the first to receive market information may enable a trader to take advantage of favourable market conditions before others. In another example, a favourable outcome for an individual playing a networked electronic game may be determinant on the latency of a gaming command received by a gaming system. Being able to send a low latency instruction to place a wager or a bid at an auction, for example, may increase the probability of securing good odds, a good price, or a successful purchase. Furthermore, it may be desirable, in at least some circumstances, to keep communications confidential.

SUMMARY

Disclosed herein is a system. The system comprises a deserialiser for de-serialising a line encoded data stream to generate a raw parallel data stream and a serialiser for serialising the raw parallel data stream. The system comprises a parallel data generator configured to generate another raw parallel data stream. The system comprises reconfigurable circuitry for communicating the raw parallel data stream to the serialiser in a configuration and communicating the other raw parallel data stream to the serialiser in another configuration. The system comprises a controller configured to confirm satisfaction of a trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry between the configuration and the other configuration. The parallel data generator is configured for the other raw parallel data stream to be synchronised to the raw parallel data stream.

In an embodiment, the parallel data generator is configured for the other raw parallel data stream to be synchronised to the raw parallel data stream at the serialiser.

In an embodiment, the system is for modifying a line encoded data stream.

The system may introduce a relatively small amount of delay by communicating the raw parallel data stream from the deserialiser to the serialiser. Payload decoding logic, for example packet decoding logic, may not be required in the raw parallel data stream's path within the system. Inline packet decoding logic generally introduces latency. Gearboxes, scrambling, descrambling, block alignment, clock domain crossing, rate-matching FIFOs buffers etc. can be avoided in favour of simply transmitting what is received. Synchronisation of the data stream and the line encoded data stream may prevent a communication error resulting from the reconfiguration of the reconfigurable circuitry.

In an embodiment, the controller is configured to confirm satisfaction of the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry for communicating the other parallel data stream to the serialiser.

In an embodiment, the controller is configured to confirm that the raw parallel data stream satisfies the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry for communicating the other raw parallel data to the serialiser.

In an embodiment, the controller is configured to retrieve information, for example a payload, from the raw parallel data stream and confirm that the information satisfies the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry for communicating the other raw parallel data to the serialiser.

In an embodiment, the trigger condition comprises at least one of: the payload comprises an Ethernet frame; the payload comprises a broadcast packet; the payload comprises a multicast packet; the payload comprises an Internet protocol packet; the payload comprises a UDP packet; the payload comprises a TCP packet; the payload comprises a HTTP request; the payload comprises a HTTP response; the payload comprises a proscribed source address; the payload comprises a proscribed destination address; the payload comprises a proscribed MAC source address; the payload comprises a proscribed MAC destination address; the payload comprises a proscribed Internet Protocol (IP) source address; the payload comprises a proscribed IP destination address; the payload comprises a Peripheral Component Interconnect Express (PCIe) packet; and the payload comprises an Infiniband message.

In an embodiment, the controller is configured to confirm satisfaction of another trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry for communication of the raw parallel-data stream to the serialiser. The controller may be configures to trigger reconfiguration for filtering out a sequence of payloads terminated by the other payload.

In an embodiment, the controller is configured to detect the end of the payload and subsequently trigger reconfiguration of the reconfigurable circuitry for communicating the raw parallel-data stream to the serialiser.

In an embodiment, the controller is configured to detect one of an end-of-payload control code and an idle control code and subsequently trigger reconfiguration of the reconfiguration circuitry for communication of the raw parallel-data stream to the serialiser.

In an embodiment, in one of the configurations the reconfigurable circuitry is configured for communicating to the serialiser one of the raw parallel data stream and the other raw parallel data stream, and in the other configuration the reconfigurable circuitry is configured for communicating to the serialiser the other one of the raw parallel data stream and the other raw parallel data stream.

In an embodiment, in the configuration the reconfigurable circuitry has a raw parallel data stream path that connects the serialiser and deserialiser for communicating the raw parallel data stream to the serialiser, and in the other configuration the parallel data generator is in communication with the serialiser for communicating the other parallel data stream to the serialiser. The raw parallel data stream path may comprise a delay line. The delay line may comprise at least one register.

The confirmation by the controller may be made before the end of a payload is sent. If there are no privacy concerns, then the decision can simply be made by the end of receipt of the payload. If there are privacy concerns, then the decision may be made by the time the part of the payload that is sensitive is sent to the output. If the latency of the controller is relatively high, then the delay line may be necessary. Since a payload can be generally aborted right up until the end of the packet, this generally means that the latency of the controller is preferably, but not necessarily, less than the time taken for a packet to traverse the device.

In an embodiment, the raw parallel data stream path has a latency of less than at least one of: 1 clock cycle of the line encoded data stream; substantially the number of clock cycles of the line encoded data stream it takes to determine the trigger condition; substantially the number of clock cycles of the line encoded data stream in a payload; and the number of clock cycles of the line encoded data stream required to synchronise the other parallel data stream.

In an embodiment, the parallel data generator comprises a block aligner configured to give at least one block of the other raw parallel data stream the same block alignment as a plurality of blocks of the raw parallel data stream.

In an embodiment, the parallel data generator comprises a block scrambling synchroniser configured for synchronising the scrambling of the other raw parallel data stream and the raw parallel data stream. The block scrambling synchroniser may be configured for synchronising the scrambling of the other raw parallel data stream and the raw parallel data stream at the serialiser.

In an embodiment, the parallel data generator comprises a block generator configured to generate at least one block.

In an embodiment, the other raw parallel data stream is configured to cause a machine receiving the at least one block to reject a payload.

In an embodiment, the other raw parallel data stream is configured to erase or replace information in the payload.

An embodiment comprises at least one logic device having at least one of the serialiser, the deserialiser, the parallel data generator, the reconfigurable circuitry and the controller.

In an embodiment, the at least one logic device comprises at least one of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a complex programmable logic device (CPLD). The at least one logic device may comprise, for example, a plurality of field programmable arrays, a plurality of ASICs and a plurality of CPLDs.

In an embodiment, the parallel data generator is configured to be controlled by a clock recovered from the line encoded data stream by the deserialiser.

In an embodiment, the parallel data generator is configured to generate the other raw parallel data stream such that a protocol rule is not violated when the reconfigurable circuitry is reconfigured between the configuration and the other configuration.

Disclosed herein is a method. The method comprises the step of de-serialising a line encoded data stream to generate a raw parallel data stream. The method comprises the step of generating another raw parallel data stream. The method comprises the step of serialising one of the raw parallel data stream and other raw parallel data stream and transmitting the so serialised one of the raw parallel data stream and the other raw parallel data stream. The method comprises the step of confirming satisfaction of a trigger condition and subsequently cease serialising the one of the raw parallel data stream and the other raw parallel data stream and transmitting the so serialised one of the raw parallel data stream and the other raw parallel data stream, and commence serialising the other one of the raw parallel data stream and the other raw parallel data stream and transmitting the so serialised other one of the raw parallel data stream and the other raw parallel data stream. The other raw parallel data stream so serialised is synchronised to the raw parallel data stream so serialised.

In an embodiment, the method is for modifying a line encoded data stream.

An embodiment comprises the step of confirming satisfaction of the trigger condition and subsequently cease serialising and transmitting the raw parallel data stream and commence serialising and transmitting the other parallel data stream for transmission.

An embodiment comprises the step of retrieving information, for example a payload, from the raw parallel data stream and confirming that the information satisfies the trigger condition. The trigger condition may comprise at least one of: the payload comprises an Ethernet frame; the payload comprises a broadcast packet; the payload comprises a multicast packet; the payload comprises an Internet protocol packet; the payload comprises a UDP packet; the payload comprises a TCP packet; the payload comprises a HTTP request; the payload comprises a HTTP response; the payload comprises a proscribed source address; the payload comprises a proscribed destination address; the payload comprises a proscribed MAC source address; the payload comprises a proscribed MAC destination address; the payload comprises a proscribed Internet Protocol (IP) source address; the payload comprises a proscribed IP destination address; the payload comprises a Peripheral Component Interconnect Express (PCIe) packet; and the payload comprises an Infiniband message.

An embodiment comprises the step of confirming satisfaction of another trigger condition and subsequently cease serialising and transmitting the other raw parallel data stream and commence serialising and transmitting the raw parallel-data stream.

An embodiment comprises the step of detecting the end of the payload and subsequently cease serialising and transmitting the other raw parallel data stream and commence serialising and transmitting the raw parallel-data stream.

An embodiment comprises the step of detecting one of an end-of-payload control code and an idle control code and subsequently cease serialising and transmitting the other raw parallel data stream and commence serialising and transmitting the raw parallel-data stream.

An embodiment comprises the step of delaying the raw parallel data stream. The raw parallel data stream may be delayed with at least one register.

In an embodiment, the raw parallel data stream is delayed for a period selected from a group comprising: 1 clock cycle of the line encoded data stream; substantially the number of clock cycles of the line encoded data stream it takes to determine the trigger condition; substantially the number of clock cycles of the line encoded data stream in a payload; and the number of clock cycles of the line encoded data stream required to synchronise the other parallel data stream.

An embodiment comprises the step of generating a plurality of blocks of the other raw parallel data stream, the other plurality of blocks having the same block alignment as a plurality of blocks of the raw parallel data stream.

An embodiment comprises the step of synchronising the scrambling of the other raw parallel data stream and the raw parallel data stream. The scrambling of the other raw parallel data stream and the raw data stream may be synchronised at the serialiser.

An embodiment comprises generating the plurality of blocks of the other raw parallel data stream.

In an embodiment, the other raw parallel data stream is configured to cause a machine receiving the plurality of blocks to reject a payload. The other raw parallel data stream may be configured to cause a machine receiving the plurality of blocks to reject a sequence of payloads terminated by the payload.

In an embodiment, the other raw parallel data stream is configured to erase or replace information in the payload.

In an embodiment, at least one of the steps of serialising, de-serialising, generating and confirming is performed within at least one logic device. The at least one logic device may comprise at least one of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a complex programmable logic device (CPLD). The at least one logic device may comprise, for example, a plurality of field programmable arrays, a plurality of ASICs and a plurality of CPLDs.

In an embodiment, the other raw parallel data has the same clock as the line encoded data stream.

In an embodiment, the other raw parallel data stream is synchronised such that a protocol is not violated by commencing serialising and transmission of the other one of the raw parallel data stream and the other raw parallel data stream.

Disclosed herein is a system. The system comprises an input for receiving a line encoded data stream and an output for transmitting the line encoded data stream. The system comprises a data generator configured to generate another data stream. The system comprises reconfigurable circuitry configured to communicate the line encoded data stream to the output in a configuration and communicate the other data stream to the output in another configuration. The system comprises a controller configured to confirm satisfaction of a trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry between the configuration and the other configuration. The data generator is configured for the other data stream and the line encoded data stream to be synchronised.

In an embodiment, the data generator is configured for the other data stream and the line encoded data stream to be synchronised at the output. In an embodiment, the system is for modifying the line encoded data stream. Modifying the line encoded data stream may comprise, for example, at least one of filtering information in the line encoded data stream, and replacing at least one payload in the line encoded data stream with at least one other payload. The at least one other payload may not comprise useful information.

The system may introduce a relatively small amount of delay by communicating the line encoded data stream to the output. Payload decoding logic, for example packet decoding logic, may not be required in the line encoded data stream's path within the system. Inline packet decoding logic generally introduces latency. Gearboxes, scrambling, descrambling, block alignment, clock domain crossing, rate-matching first-in first-out (FIFIO) buffers etc. can be avoided in favour of simply transmitting what is received. Synchronisation of the data stream and the line encoded data stream may prevent a communication error resulting from the reconfiguration of the reconfigurable circuitry.

In an embodiment, the controller is configured to confirm satisfaction of the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry from the configuration to the other configuration for communication of the other data stream to the output. This may be to filter the line encoded data stream or replace the line encoded data stream, for example. The controller may be configured to confirm that the line encoded data stream satisfies the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry from the configuration to the other configuration for communication of the other data stream to the output. The controller may be configured to retrieve information, for example a payload, from the line encoded data stream and confirm that the information satisfies the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry from the configuration to the other configuration for communication of the other data stream to the output. For example, if a payload having a particular address (e.g. IP or MAC address) is detected, then it may be blocked or filtered out. The trigger condition may comprise at least one of: the payload comprises an Ethernet frame; the payload comprises a broadcast packet; the payload comprises a multicast packet; the payload comprises an Internet protocol packet; the payload comprises a UDP packet; the payload comprises a TCP packet; the payload comprises a HTTP request; the payload comprises a HTTP response; the payload comprises a proscribed source address; the payload comprises a proscribed destination address; the payload comprises a proscribed MAC source address; the payload comprises a proscribed MAC destination address; the payload comprises a proscribed Internet Protocol (IP) source address; the payload comprises a proscribed IP destination address; the payload comprises a Peripheral Component Interconnect Express (PCIe) packet; and the payload comprises an Infiniband message.

In an embodiment, the controller is configured to confirm satisfaction of another trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry from the other configuration to the configuration for communication of the line encoded data stream to the output. The controller may be configured to confirm that the line encoded data stream satisfies the other trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry from the other configuration to the configuration for communication of the line encoded data stream to the output.

The controller may be configured to retrieve other information, for example another payload, from the line encoded data stream and confirm that the other information, for example another payload, satisfies the other trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry from the other configuration to the configuration for communication of the line encoded data stream to the output.

In an embodiment, the controller may be configured to detect the end of the payload and subsequently trigger the reconfiguration of the reconfigurable circuitry from the other configuration to the configuration for communication of the line encoded data stream to the output. The controller may be configured to trigger reconfiguration for filtering out a sequence of payloads terminated by the other payload.

In an embodiment, the controller is configured to detect one of an end-of-payload control code and an idle control code and subsequently trigger the reconfigurable circuitry to reconfigure for communication of the line encoded data stream to the output. The end-of-payload control code and/or the idle control code may be associated with the payload.

In an embodiment the reconfigurable circuitry may have a configuration in which a line encoded data stream path connects the input and the output for communicating the line encoded data stream to the output, and has another configuration in which the output is in communication with the data generator for communicating the other data stream to the output.

In an embodiment, the line encoded data stream path comprises a delay line. The delay line may comprise at least one of a capacitive delay, a plurality of logic gates, a time-of-flight delay comprising, for example, a wire or an optical communications mechanism, a printed circuit board trace, and/or a plurality of IODELAY elements in an FPGA. Generally, any suitable method to delay the signal may be used.

The controller may be configured to confirm that the trigger condition is satisfied before the end of a payload is sent. If there are no privacy concerns, then the decision may simply be made by the end of receipt of the payload. If there are privacy concerns, then the decision may be made before the part of the payload that is sensitive is sent to the output. If the latency of the controller is relatively high, then the delay line may be necessary. Since a payload may be generally aborted right up until the end of the packet, this generally means that the latency of the controller is preferably, but not necessarily, less than the time taken for a packet to traverse the device.

In an embodiment, the line encoded data stream path has a latency of less than at least one of: 1 clock cycle; substantially the number of clock cycles it takes to determine the trigger condition; substantially the number of clock cycles in a payload; and the number of clock cycles required to synchronise the other parallel data stream. A latency of less than 1 clock cycle may be used if the data generator does not require any prior knowledge of the data stream. A latency of less than substantially the number of clock cycles it takes to determine the trigger condition may be used if knowledge of the trigger condition is required before the first part of the encoded data stream is output. A latency of substantially the number of clock cycles in a payload may be used if knowledge of the entire payload is required before the trigger condition can be determined. A latency of the number of clock cycles required to synchronise the other parallel data stream may be used if some information is required from the data stream to synchronise the parallel data stream, or if some processing time is required to synchronise the parallel data stream.

In an embodiment, the data generator comprises a block generator. The block generator may be configured to generate at least one block for replacing at least one block of the line encoded data stream.

In an embodiment, the data generator comprises a block aligner configured to give the at least one block for replacing the at least one block of the line encoded data stream the same block alignment as a plurality of blocks of other data stream. Consequently, the block alignment of the line encoded data stream and the other data stream are synchronised.

An embodiment comprises a block scrambling synchroniser configured for synchronising the scrambling of the other data stream. The block scrambling synchroniser is configured for synchronising the scrambling of the other data stream and the line encoded data stream at the output.

In an embodiment, the other data stream is configured to cause a machine receiving a plurality of blocks of the other data stream to reject a payload. The rejected payload may be at least part of the payload of the line encoded data stream by the controller.

In an embodiment, the other data stream is arranged to replace or erase information in the payload. This may ensure, for example, that sensitive information is not transmitted. Alternatively, the other data stream comprises information in the line encoded data stream. This may provide, for example, integrity of a data connection between network nodes.

An embodiment comprises at least one logic device having at least one of the data generator and the controller. The at least one logic device may comprise at least one of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a complex programmable logic device (CPLD). The at least one logic device may comprise, for example, a plurality of field programmable arrays, a plurality of ASICs and a plurality of CPLDs.

An embodiment comprises a clock recovery system configured to recover a clock from the line encoded data stream and generate the other data stream using the clock. The data generator may comprise the clock recovery system configured to recover the clock from the line encoded data stream and generate the other data stream using the clock. In an embodiment, the reconfigurable circuitry comprises a switch. The reconfigurable circuitry may comprise a crosspoint switch.

In an embodiment, the data generator is configured to generate the other data stream such that a protocol rule is not violated when the reconfigurable circuitry is reconfigured between the configuration and the other configuration. The protocol rule may include a timing jitter rule, a clock tolerance rule, a block encoding format rule, a bit error rate rule, and a scrambling format rule.

Disclosed herein is a method. The method comprises receiving a line encoded data stream. The method comprises generating another data stream. The method comprises transmitting the line encoded data stream. The method comprises confirming satisfaction of a trigger condition and subsequently cease transmitting the line encoded data stream and commence transmitting the other data stream. The other data stream is synchronised to the line encoded data stream.

In an embodiment, the method is for modifying the line encoded data stream.

An embodiment comprises the step of confirming that the line encoded data stream satisfies the trigger condition and subsequently cease transmission of the line encoded data stream and commence transmission of the other data stream.

An embodiment comprised retrieving information, for example a payload, from the line encoded data stream and confirming that the information satisfies the trigger condition and subsequently cease transmission of the line encoded data stream and commence transmission of the other data stream.

In an embodiment, the trigger condition comprises at least one of: the payload comprises an Ethernet frame; the payload comprises a broadcast packet; the payload comprises a multicast packet; the payload comprises an Internet protocol packet; the payload comprises a UDP packet; the payload comprises a TCP packet; the payload comprises a HTTP request; the payload comprises a HTTP response; the payload comprises a proscribed source address; the payload comprises a proscribed destination address; the payload comprises a proscribed MAC source address; the payload comprises a proscribed MAC destination address; the payload comprises a proscribed Internet Protocol (IP) source address; the payload comprises a proscribed IP destination address; the payload comprises a Peripheral Component Interconnect Express (PCIe) packet; and the payload comprises an Infiniband message.

An embodiment comprises confirming satisfaction of another trigger condition and subsequently cease transmission of the other data stream and commence transmission of the line encoded data stream.

An embodiment comprises retrieving another payload from the line encoded data stream and confirming that the other payload satisfies another trigger condition and subsequently cease transmission of the other data stream and commence transmission of the line encoded data stream.

An embodiment comprises the step of detecting the end of the payload and subsequently triggering transmission of the line encoded data stream.

An embodiment comprises detecting one of an end-of-payload control code and an idle control code and subsequently transmitting the line encoded data stream.

An embodiment comprises the step of delaying the line encoded data stream.

An embodiment comprises the step of delaying the line encoded data stream with at least one of, for example, a capacitive delay, a plurality of logic gates, a time-of-flight delay comprising, for example, a wire or an optical communications mechanism, or a printed circuit board trace, a plurality of IODELAY elements in an FPGA. Generally, any suitable method to delay the signal by a consistent amount may be used.

In an embodiment, the line encoded data stream is delayed for no longer than a period selected from a group comprising: 1 clock cycle; substantially the number of clock cycles it takes to determine the trigger condition; substantially the number of clock cycles in a payload; and the number of clock cycles required to synchronise the other parallel data stream.

An embodiment comprises the step of generating a plurality of blocks of the other data stream, the plurality of blocks of the other data stream having the same block alignment as a plurality of blocks of the line encoded data stream.

An embodiment comprises the step of synchronising scrambling of the other data stream and the line encoded data stream.

In an embodiment, the other data stream is configured to cause a machine receiving the plurality of blocks of the other stream to reject a payload.

In an embodiment, the other data stream is configured to erase or replace information in the payload.

In an embodiment, at least one of generating the other data stream and confirming satisfaction of the trigger condition is performed within at least one logic device. The at least one logic device may comprise at least one of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a complex programmable logic device (CPLD). The at least one logic device may comprise, for example, a plurality of field programmable gate arrays, a plurality of ASICs and a plurality of CPLDs.

In an embodiment, the data stream has the same clock rate as the line encoded data stream.

In an embodiment, the other data stream is synchronised to the line encoded data stream such that a protocol rule is not violated when transmission of one of the line encoded data stream and the other data stream ceases and the transmission of the other one of the line encoded data stream and the other data stream commences. The protocol rule may include a timing jitter rule, a clock rule, a clock encoding format rule, a bit error rate rule, and a scrambling format rule.

An embodiment comprises the step of reconfiguring a crosspoint switch to cease transmitting the line encoded data stream and commence transmitting the other one of the line encoded data stream and the other data stream. The crosspoint switch may be implemented in an FPGA or may be implemented in a crosspoint switch package.

Any of the various features of each of the above disclosures, and of the various features of the embodiments described below, can be combined as suitable and desired.

DESCRIPTION OF EMBODIMENTS

FIG. 1shows an embodiment of a system generally indicated by the numeral10. The system10has an input11for receiving a line encoded data stream12. The system has an output81for transmitting the line encoded data stream12. The system10has a de-serialiser16for de-serialising the line encoded data stream12to generate a raw parallel data stream18. The system10has a serialiser28for serialising the raw parallel data stream18. The system10has a parallel data generator20configured to generate another raw parallel data stream22. The system10has reconfigurable circuitry24for communicating raw parallel data stream18to the serialiser28in a configuration and communicating the other parallel data stream22in another configuration.

The system10is, in this but not necessarily in all embodiments, a system for modifying a line encoded data stream.

In system10, but not all embodiments, the reconfigurable circuitry24is configured to communicate one of the raw parallel data stream18and the parallel data stream22to the serialiser28in the configuration and the other one of the raw parallel data stream18and the other parallel data stream22in the other configuration.

The system10, but not all embodiments, comprise at least one logic device102in the form of at least one field programmable gate array (FPGA), for example a VIRTEX 7, ARRIA 10, ULTRASCALE etc. The embodiment ofFIG. 1comprises a single FPGA102, however others may have more than one FPGA. In alternative embodiments, the logic device102may take the form of an application-specific integrated circuit (ASIC) or a complex programmable logic device (CPLD), or generally any suitable of logic device. In system10, the serialiser16, the reconfigurable circuitry24, the deserialiser28, the data generator20, and the controller42are each integral to the logic device102. In other embodiments, however, only some of the components are integral to the logic device, or may be in separate packages.

The input11is in the form of an input port11for receiving the line encoded data stream. The port11is configured for interfacing with a line encoded data stream conduit external of the logic device102. In this particular embodiment, but not all, the port11is in the form of an electrically conductive pad that is solderable to a circuit board in the form of a printed circuit board104. The port11may additionally or alternatively take the form of a pin. The line encoded data stream source14is in this but not necessarily all embodiments a part of the circuit board104. The source14may be external of the circuit board104or device hosting the circuit board104.

In an alternative embodiment, the system10is one of a plurality of systems10that are integral to logic device102. The reconfigurable circuitry24comprises a switch26in the form of a cross point switch. The output30of the parallel data generator20is connected via a bus32to an input34of the reconfigurable circuitry24.

An output36of the deserialiser16is connected via bus38to another input40of the reconfigurable circuitry24.

The system10has a controller42configured to confirm satisfaction of a trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry24. The controller42comprises a trigger circuit68configured to confirm satisfaction of the trigger condition and subsequently trigger reconfiguration of the reconfigurable circuitry24. The parallel data generator20is configured for the other raw parallel data stream22to be synchronised to the raw parallel data stream18. The other raw parallel data stream22may be synchronized to the raw parallel data stream18at the serialiser28. That is, at least one of the following properties of the line encoded data stream12input to the serialiser28are preserved by reconfiguration of the reconfigurable circuitry: The block alignment, the block scrambling sequence, and the line encoded data stream clock.

In the embodiment ofFIG. 1, the controller42, but not in all embodiments, the trigger circuit68, is configured to confirm satisfaction of the trigger condition and subsequently trigger the reconfigurable circuitry24to reconfigure for communicating the other parallel data stream22to the serialiser28. For example, the controller42may be configured to confirm that the raw parallel data stream18satisfies the trigger condition and subsequently trigger the reconfigurable circuitry24to reconfigure for communicating the other raw parallel data22to the serialiser. A tap44communicates the raw parallel data stream18to an input46of the controller42. The controller42interrogates the raw parallel data stream18received at input46. In one specific example, the controller42is configured to retrieve information in the form of a payload, for example, from the raw parallel data stream18and confirm that the information satisfies the trigger condition. The raw parallel data stream18received at input46is communicated within the controller42via a conduit to a block synchronisation module48that determines the block offset of the raw parallel data stream18and generates a sequence of words50that each correspond to a respective block of the line encoded data stream. The sequence of words50is communicated via a conduit to a descrambling module52that descrambles the sequence of words. The descrambled sequence of words54are communicated via a conduit to a decoding module56in the form of a 64b66b decoding module which decodes the descrambled sequence of words54. The decoded sequence58is communicated via a bus to a media access control (MAC) module60. The media access control module60retrieves a payload62that is communicated via a bus to a payload parsing module64to extract information66from the payload62. The information66is communicated via a bus to the trigger circuit68in the form of a filter logic module68which determines if the information satisfies the trigger condition. If the filter logic model68determines that the information does indeed satisfy the trigger condition then the controller42generates a trigger signal70that is communicated via trigger signal conduit72to the reconfigurable circuitry24and in particular input74of switch26. The switch26receives the trigger signal70, which causes the switch to reconfigure such that the output76of the switch26is placed in communication with the input34of the switch26, input34being in communication with the output30of the parallel data generator20. The trigger circuit68may not be triggered for only a filtering function.

The trigger condition could comprise any number of payload conditions, for example at least one of:The payload comprises an Ethernet frame;the payload comprises a broadcast packet;the payload comprises a multicast packet;the payload comprises an Internet protocol packet;the payload comprises a UDP packet;the payload comprises a TCP packet;the payload comprises a HTTP request;the payload comprises a HTTP response;the payload comprises a proscribed source address;the payload comprises a proscribed destination address;the payload comprises a proscribed MAC source address;the payload comprises a proscribed MAC destination address;the payload comprises a proscribed Internet Protocol (IP) source address;the payload comprises a proscribed IP destination address;the payload comprises a Peripheral Component Interconnect Express (PCIe) packet; andthe payload comprises an Infiniband message.

The controller42is, and at least in this embodiment specifically the trigger circuit68, configured to confirm satisfaction of another trigger condition and subsequently trigger the reconfigurable circuitry24to reconfigure for communication of the raw parallel data stream18to the serialiser28. For example, the controller42or trigger circuit68may be configured to detect the end of the payload (or the another payload) and subsequently trigger the reconfigurable circuitry to reconfigure for communicating the raw parallel data stream to the serialiser28. In this and/or another embodiment, the controller42or trigger circuit68is configured to detect one of an end-of-payload control code and an idle control code, and subsequently trigger the reconfiguration circuitry24to reconfigure the communication of the raw parallel data stream18to the serialiser28. A sequence of payloads terminated by the payload may be filtered or replaced.

Within the signal generator20, for example, a layer 1 and/or layer 2 encoding is generated which matches the signal required to validly abort a payload, for example a packet. This is generated in a format such that only a minimal amount of processing has to occur. As a payload arrives it is decoded and the upstream logic decides whether the packet will be delivered or not. If it will not be delivered, then the output is switched to an “abort” signal, which validly aborts the signal (for example, in 10 Gb Ethernet may insert an error symbol).

In the configuration in which the raw parallel data stream18is communicated to the serialiser28, the reconfigurable circuitry24has a raw parallel data stream path78in the form of a bus that connects the output36of the deserialiser16and the input80of the serialiser28, via the input40of switch26, and the output76of switch26. The raw parallel data stream path includes the switch26. In the other configuration, however, the parallel data generator20is in communication with the serialiser28for communicating the other parallel data stream22to the serialiser28. In the other configuration, the other raw parallel data stream22generated by the data generator20is communicated via bus22to input34of switch26, through the switch26to the switch output76, and then communicated along bus82to the input80of the serialiser28.

In this but not all embodiments, the raw parallel data stream path78comprises a delay line84electrically disposed between the deserialiser16and the switch26. The delay line comprises at least one register for temporally delaying the raw parallel data stream18. The delay introduced by the delay line84may be such that the latency of the raw parallel data stream path78is substantially the number of clock cycles of the line encoded data stream18it takes to determine the trigger condition, substantially the number of clock cycles of the line encoded data stream in a payload of the raw parallel data stream18, and the number of clock cycles in the line encoded data stream18required to synchronise the other parallel data stream22. In embodiments without a delay line84, the latency of the raw parallel data stream path may be no more than one clock cycle of the line encoded data stream18.

A latency of less than 1 clock cycle may be used if the data generator does not require any prior knowledge of the data stream. A latency of less than substantially the number of clock cycles it takes to determine the trigger condition may be used if knowledge of the trigger condition is required before the first part of the encoded data stream is output. A latency of substantially the number of clock cycles in a payload may be used if knowledge of the entire payload is required before the trigger condition can be determined. A latency of the number of clock cycles required to synchronise the other parallel data stream may be used if some information is required from the data stream to synchronise the parallel data stream, or if some processing time is required to synchronise the parallel data stream.

The data generator20is configured for the other data stream22to be synchronised to the line encoded data stream18at the serialiser28. That is, the synchronisation of the signal measured at the serialiser input80immediately after the reconfigurable circuitry is reconfigured is the same as that before the reconfigurable circuitry is reconfigured. The same synchronisation is observed at the output76of the switch and at the output81of the serialiser28. The other raw parallel data stream22is configured such that a protocol is not violated when the reconfigurable circuitry is reconfigured between the configuration and the other configuration. The parallel data generator20has another block synchronisation module82that generates block synchronisation information indicative of the alignment of a plurality of blocks of the raw parallel data stream18and generates a sequence of words84communicated via a conduit to a scrambling synchronisation module86. The scrambling synchronisation module generates scrambling information94indicative of the scrambling sequence of the plurality of blocks of the raw parallel data stream18. The data generator20has a block generator88that generates at least one block90that, in this but not all embodiments, is to replace a block within the raw parallel data stream18. The at least one block may be, for example, configured to cause a machine receiving the at least one block to reject a payload. In some applications it may be desirable to conceal information within the raw parallel data stream18, in which case the at least one block when used to modify the raw parallel data stream18may erase information therein. The at least one block may replace blocks within the raw parallel data stream18. The at least one block may be scrambled in a scrambling module92. The scrambling synchronisation module86is in communication with the scrambling module92for communicating the scrambling information94via a conduit to the scrambling module92. The scrambling module92uses the scrambling information94to synchronise the scrambling of the at least one block90to the raw parallel data stream18at the scrambler92. The scrambled at least one block96is communicated from the scrambling module92to the block alignment module98, which is in communication with the block synchronisation module82via a conduit and receives therefrom block synchronisation information100. The block alignment module98gives the at least one block the same alignment as a plurality of blocks of the raw parallel data stream18. The deserialiser16recovers from the line encoded data stream12a line encoded data stream clock. The system10has a clock conduit89for communicating the line encoded data stream clock from the deserialiser16to the parallel data stream generator20which is internally clocked by the line encoded data stream clock. Consequently, the parallel data generator20is controlled by the line encoded data stream clock.

The line encoded data stream in the embodiment ofFIG. 1is a 10G Ethernet line encoded data stream with a 64b/66b Ethernet block code structure defined by the standard IEEE 802.3. It will be appreciated however, that the line encoded data stream may be of any suitable protocols examples of which include but are not limited to 1G and 10G Ethernet, FireWire, InfiniBand, USB, PCIe, and FiberChannel. Some forms of block encoding, including 10G Ethernet and Hamming codes, include error detection and error correction. Other suitable protocols may have, for example, 8b/10b encoded blocks, 128b/132b encoded blocks, and 128b/132b encoded blocks.

The system may be inserted into a network in the form of, for example, a PAN, LAN, MAN, WAN or generally any suitable form of network.

FIG. 4discloses an embodiment of a method500that may be performed using the system10. The method comprises the step502of de-serialising a line encoded data stream to generate a raw parallel data stream. The method comprises the step504of generating another raw parallel data stream. The method comprises the step506of serialising one of the raw parallel data stream and other raw parallel data stream and transmitting the so serialised one of the raw parallel data stream and the other raw parallel data stream. The method comprises the step508of confirming satisfaction of a trigger condition and subsequently cease serialising the one of the raw parallel data stream and the other raw parallel data stream and transmitting the so serialised one of the raw parallel data stream and the other raw parallel data stream, and commence serialising the other one of the raw parallel data stream and the other raw parallel data stream and transmitting the so serialised other one of the raw parallel data stream and the other raw parallel data stream. The other raw parallel data stream so serialised is synchronised to the raw parallel data stream so serialised.

FIG. 5shows another embodiment of a system600. The system600comprises at least one logic device602in the form of at least one field programmable gate array (FPGA), for example a VIRTEX 7, ARRIA 10, ULTRASCALE etc. System600comprises a single FPGA602, however others may have more FPGAs. In alternative embodiments, the logic device602may take the form of an application-specific integrated circuit (ASIC) or a complex programmable logic device (CPLD), or generally any suitable form of logic device. The system600comprises a plurality of systems604that are each integral to the logic device602. Each system604has a port607for receiving a line encoded data stream from a source606. Each system604has a de-serialiser608for de-serialising the line encoded data stream12to generate a raw parallel data stream. Each system604has a serialiser610for serialising the raw parallel data stream. Each system604has a parallel data generator612configured to generate another raw parallel data stream. The system10has reconfigurable circuitry614for communicating raw parallel data stream to the serialiser610in a configuration and communicating the other parallel data stream in another configuration.

The systems604are generally of similar form and/or function as system10, except where necessarily not in view of the differences between the architectures of systems10,604.

Some embodiments may broadcast the line encoded data stream to a plurality of outputs and filter the line encoded data stream at each of the plurality of outputs. Filtering the line encoded data stream by the present embodiments may introduce relatively little time delay, which is beneficial for applications that require low latency.

FIG. 2shows another embodiment of a system generally indicated by the numeral200. The system200has an input202for receiving a line encoded data stream208. The system200also has an output204for transmitting the line encoded data stream. The system has a data generator206, which is configured to generate another data stream210. The system200has reconfigurable circuitry212that in a configuration is configured to communicate the line encoded data stream208to the output204. In another configuration, the reconfigurable circuitry212is configured to communicate the other data stream to the output204. The system200has a controller214that is configured to confirm satisfaction of a trigger condition, and subsequently trigger reconfiguration of the reconfigurable circuitry212between the configuration and the other configuration. The data generator206is configured for the other data stream210and the line encoded data stream208to be sychronised, for example at the output204. That is, the synchronisation of the signal measured at the output204immediately after the reconfigurable circuitry is reconfigured is the same as that before the reconfigurable circuitry is reconfigured. The same synchronisation may be observed at232,228,227, and236for example.

At least one of following properties of the data stream at the output are preserved by reconfiguration of the reconfigurable circuitry because of the syncronisation of the other data stream210and the line encoded data stream208: The block alignment, the block scrambling sequence, and the data stream input's clock. The other data stream210and the line encoded data stream208may be syncronised at the output.

The embodiment200is for modifying a line encoded data stream.

The controller214is configured to confirm satisfaction of the trigger condition and subsequently trigger the reconfigurable circuitry212to reconfigure for communication of the other data stream210to the output204. In this embodiment, the controller214is configured to confirm that the line encoded data stream208satisfies the trigger condition and subsequently trigger the reconfigurable circuitry206to reconfigure communication of the other data stream to the output204. The controller214is configured to retrieve information, for example a payload from the line encoded data stream208. The controller is configured to confirm that the information satisfies the trigger condition and subsequently trigger the reconfigurable circuitry212to reconfigure for communication of the other data stream210to the output204. The information may comprise a payload or the information may be from any layer of the Open Systems Interconnection Model (OSI model), and may comprise an Ethernet packet or other information.

The trigger condition may comprise any number of payload or other conditions, for example at least one of:The payload comprises an Ethernet frame;the payload comprises a broadcast packet;the payload comprises a multicast packet;the payload comprises an Internet protocol packet;the payload comprises a UDP packet;the payload comprises a TCP packet;the payload comprises a HTTP request;the payload comprises a HTTP response;the payload comprises a proscribed source address;the payload comprises a proscribed destination address;the payload comprises a proscribed MAC source address;the payload comprises a proscribed MAC destination address;the payload comprises a proscribed Internet Protocol (IP) source address;the payload comprises a proscribed IP destination address;the payload comprises a Peripheral Component Interconnect Express (PCIe) packet; andthe payload comprises an Infiniband message.

The controller214is configured to confirm satisfaction of another trigger condition and subsequently trigger the reconfigurable circuitry214to reconfigure for communication of the line encoded data stream208to the output204. For example, the controller214is in one embodiment configured to retrieve other information, for example another payload, from the line encoded data stream208and confirm that the other information satisfies another trigger condition and subsequently trigger the reconfigurable circuitry212to reconfigure for communication of the line encoded data stream208to the output204. In another embodiment, the controller214is configured to detect the end of the payload and subsequently trigger the reconfigurable circuitry214to reconfigure for communication of the line encoded data stream208to the output204. The controller is configured to detect at least one of an end-of-payload control code and an idle control code, either of which may signal the end of the payload, and subsequently trigger the reconfigurable circuitry212to reconfigure for communication of the line encoded data stream208to the output204.

The reconfigurable circuitry212comprises a switch216that facilitates the reconfiguration of the reconfigurable circuitry212. In the configuration, the switch216is configured such that a line encoded data stream path is established between input202and the output204, via input218of optional delay line220, the output222of optional delay line220, input224of switch216, output226of switch216, the output of the reconfigurable circuitry212, input228of optional clock and data recovery unit230, and the output232of optional clock and optional recovery unit230. Without the optional delay line220the input202is in communication with the input224of the switch216. Without the optional clock and data recovery module230, the output227of the reconfigurable circuitry212is in direct communication with the output204. In the other configuration, the switch216is configured such that the output204is in communication with the data generator206for communicating the other data stream210to the output204. Another data stream path is established between other input234of the reconfigurable circuitry212, the other input236of the switch216, the output226of the switch216, the outputs227of the reconfigurable circuitry, the input228of the optional clock and data recovery unit230, the output232of the optional clock and data recovery unit230, and the output204. Without the optional clock and data recovery unit230, the output227of the reconfigurable circuitry212is in direct communication with the output204.

In this embodiment, the system200has the delay line220electrically disposed between the input202of the reconfigurable circuitry212and the input224of the switch216. The delay line220comprises at least one of a capacitive delay, a plurality of logic gates, a time-of-flight delay comprising for example a copper trace or optical communications mechanism, or a printed circuit board trace, and a plurality of IODELAY elements in an FPGA. Generally, any suitable method to delay the signal by a consistent amount may be used.

The line encoded data stream path through switch216may have a latency of less than at least one of one clock cycle, substantially the number of clock cycles it takes to determine the trigger condition, substantially the number of clock cycles in a payload, and the number of clock cycles required to synchronise the other parallel data stream.

The data generator206has a block generator240. The block generator240is configured to generate blocks that are to replace blocks within the line encoded data stream208. The blocks242may be synchronised to the line encoded data stream at the output204. The blocks242generated by the block generator240are to be synchronised to the line encoded data stream208at the output204. Scrambling information244generated by a descrambling module246(“scramble sync and descramble”) of the controller214is communicated via conduit248to a scrambling module250(scramble, 64/66 encode, MAC, etc.) of the data generator206. The scrambling module250receives the blocks242via a conduit and synchronises the scrambling of the blocks242generated by the block generator240with the blocks of the line encoded data stream208at the output204. The block generator240receives via conduit256protocol synchronisation and MAC information254from a protocol synchroniser and MAC module252. The block generator240uses the protocol sync and MAC information254to emit blocks242which, when passed through the other encoding stages, will form a line encoded data stream which is protocol compliant with the line encoded data stream281. The data generator206has block alignment circuitry258, which comprises a block aligner260. The block aligner260receives from the scrambling module250the scrambled blocks262via a conduit. The block aligner260receives via a conduit block offset information264generated by the block alignment circuitry258. The block offset information is indicative of the block offset of the other data stream210relative to the line encoded data stream. The block aligner260of the block alignment circuitry258generates using the block offset information264a sequence of words266that each correspond to a respective block of the line encoded data stream208. The sequence of words266are communicated via a conduit from the block aligner260to a serialiser270. The output272of the serialiser270is in communication with the output274of the data generator206which is in turn in communication with the input234of the reconfigurable circuitry212.

The block alignment circuitry258has a first input276and a second input278. The first input276receives the data stream210via tap280in the reconfigurable circuitry212, which comprises a crosspoint switch. The second input278receives the line encoded data stream208in the reconfigurable circuitry212. The block alignment circuitry258compares the data stream210and line encoded data stream208to generate the block offset information264. Comparator282performs the comparison. The comparator282deserialises the data stream210and the line encoded data stream208in respective deserialisers284and286. The outputs288and290of the deserialisers284,286are received by block synchronisation modules292and294that determine the alignment of the blocks of the data stream210and the line encoded data stream208. The output from the block synchronisation modules292,294, being block alignment information295,297is received by an offset difference adjustment module296which generates offset adjustment information that is communicated via a conduit to integration unit298in the form of a proportional-integral-derivative controller, for example an I-type controller, that generates the block offset information264communicated to the block aligner260. A phase offset detector322determines the phase offset between the signals input at input276and input278via taps330and332. An integrator326in receives phase offset information from the phase offset controller326and sends integrator information to a phase aligner328. The phase aligner sends phase alignment information to the signal generator240. A clock recovery unit324receives a copy of the line encoded data stream at input278to recover a clock from the line encoded data stream208. A recovered clock signal is sent by the cloak recovery unit324to the phase aligner.

The line encoded data stream208is communicated to the controller214. A tap300within the reconfigurable circuitry212communicates the line encoded data stream208to an output302of the reconfigurable circuitry212in communication with input304of the controller214. The controller214then interrogates the line encoded data stream208received at304. The line encoded data stream208received at input304is communicated via a conduit within the controller214to a deserialiser306, the output307of which is communicated to a block synchronisation module308that determines the block offset of the line encoded data stream208and generates a sequence of words310that each correspond to a respective block of the line encoded data stream308. The sequence of words310are communicated to a module246that has a 64b64b decoding module that descrambles the sequence of words. The descrambled sequence of words312is communicated via a conduit to the protocol synchronisation and MAC module252to retrieve the payload from the descrambled sequence of words312. The payload314is communicated via a conduit to a trigger circuit in the form of a filter logic module316, which determines if the information in the payload satisfies the trigger condition. If the filter logic module316determines that the information does indeed satisfied the trigger condition, then a trigger signal318generated by the filter decision logic causes the reconfigurable circuitry212to reconfigure. The trigger signal318is communicated via a conduit to a switch controller320that reconfigures the reconfigurable circuitry, and in particular the switch216. The trigger circuit68may not be triggered for only a filtering function.

FIG. 3discloses an embodiment of a method400that may be performed using the system200. The method comprises a step402of receiving a line encoded data stream. The method comprises a step404of generating another data stream. The method comprises a step406of transmitting the line encoded data stream. The method comprises a step408of confirming satisfaction of a trigger condition and subsequently cease transmitting the line encoded data stream and commence transmitting the other data stream. The other data stream is synchronised to the line encoded data stream.

All of the modifications to the line encoded data stream described with respect to the line encoded data stream processed with an embodiment of a system and/or an embodiment of a method described herein may, as suitable and desired, be performed by any other embodiment of a system and/or an embodiment of a method described herein.

Embodiments of the above described system and methods comply with a 10G Ethernet protocol, and other embodiments of the above described systems and methods comply with a 1G Ethernet protocol.

Encoding for the 10G Ethernet protocol includes:1. Block synchronisation and alignment. For example, when you put 66 bits on the line, it must align with the block boundaries already on the line.2. Scrambling in 10G Ethernet is based on previously received data, so if you're going to put different data on the line it needs to be encoded using information from the last data received.3. Data synchronisation. The data contained within the blocks needs to ‘make sense’ given the previously received/transmitted blocks.

Encoding for the 1G Ethernet protocol includes:1. Block synchronisation and alignment (which is 8b10b for the 1G Ethernet protocol).2. Running disparity synchronisation. The DC bias of the outgoing signal may be different to the incoming signal, and so an appropriate DC bias may be created to switch between the line encoded data stream and the other data stream.3. Data syncronisation. The data contained within the blocks needs to ‘make sense’ given the previously received/transmitted blocks.

In some other circumstances it may be desirable to switch from one source of data to another source of data. For example, when the source of data may have a lower latency than the other source of data, but is also less reliable. Switching from the one source of data to the other source of data when the source of data is interrupted may, however, cause a communications error, which may not be desirable.

In another embodiment, the source may be an external low latency transmission path over which the line encoded data stream is transmitted. A low latency transmission path may be for trading financial instruments, for example; a plurality of financial instrument trading orders received by a financial market may be processed in the order that they were received. In one example, the low latency transmission path comprises a microwave transmission path. The microwave transmission path, however, may be relatively unreliable because, for example, of the possibility of an inadvertent break of the microwave transmission path by an intersecting object. The data generator20,206may also receive the line encoded data stream via another transmission path that is more reliable but has more latency than the low latency link. For example, the other transmission path may be a wired link. The controller may be configured to detect a break in the low latency transmission path and trigger the reconfigurable circuitry24,212to reconfigure to the configuration in which the output of the data generator is transmitted from the output204,81of the system10,200. The controller42,214may be configured to detect the re-establishment of the low latency transmission path and subsequently trigger the reconfigurable circuitry24,212to reconfigure to the other configuration in which the line encoded data stream is transmitted from the output of the system10,200.

It will be appreciated that the systems10,200may be, for example, configured to be a firewall. Filtering may be based on, for example, MAC address, IP address, VLAN tag, port number, packet type etc.

The trigger condition for systems10,200may comprise a plurality of conditions. For example, the trigger condition may be that a payload has a proscribed source address AND a proscribed destination address. The trigger condition may by any suitable Boolean expression, for example, including any one of, for example, of a MAC address, and IP address, a VLAN tag, a port number, a packet type etc. The trigger condition may comprise a condition requiring information external of the payload, for example the contents of memory set by software.

The systems10,200may comprise or be integral to a multilayer printed circuit board (e.g.104) having components mounted thereto which generally, but not necessarily, are connected to each other by conduits in the form of conductive pathways, which may comprise, for example, tracks, signal traces, strip lines and/or micro strip lines, and wires, as appropriate. Generally, but not necessarily, the printed circuit board is housed by a rack mountable enclosure having dimensions of 1 rack unit, although any suitable enclosure may be used or not used as desired. The printed circuit board has various surface mounted and/or through hole components mounted thereto. A mains supply may be mounted to the printed circuit board, the main supply in use producing a relatively low voltage, such as 12, 24 or 48 volts as suitable, from a relatively high voltage source, for example, a 110V or 240V electricity grid. There may be a DC regulator in the form of a switched mode power supply module mounted to the printed circuit board that receives the low voltage output from the mains supply and powers two or more active conductive rails integral to the circuit board. Alternatively, the mains supply and DC regulator may be mounted within the enclosure separate from the printed circuit board.

At least one fan may be mounted to the circuit board or alternatively the enclosure. The at least one fan may provide airflow across the multilayer printed circuit board to extract waste heat.

Associated or integrated with the circuit board may optionally be a receiver in the form of a line encoded data stream receiver, which may comprise an optical-to-electrical (o/e) converter. Associated or integrated with the circuit board may optionally be, for example a transmitter in the form of a data stream transmitter, which may comprise an electrical-to-optical (o/e) converter. In alternative embodiments described further below, the receiver and transmitter provide an electrical-to-electrical interface, for example supporting BASE-T Ethernet or direct attach electrical network cables. In this embodiment, but not necessarily in all embodiments, the receiver and transmitter are each configured to accept a network cable in the form of an optical network cable for interfacing with a network in the form of, for example, a local area network (LAN). The receivers and transmitters may be part of an enhanced small form factor pluggable (SFP+) transceiver. Generally, however, any suitable transceiver may be used, for example any of gigabit interface converter (GBIC), small form factor pluggable (SFP), 10 gigabit small form factor pluggable (XFP), 10 Gigabit Media Independent Interface (XAUI), C form-factor pluggable (CFP), quad small form-factor pluggable (QSFP), CXP specified by the Infiniband Trade Association, and a Thunderbolt transceiver. The o/e and e/o converters may alternatively be configured to receive an electrical network cable in the form of, for example, an electrical network cable, for example a copper network cable. Alternatively, the source may be from within the logic device, for example the FPGA.

The o/e and e/o converters may be housed in enclosures in the form of SFP cages fixed to the printed circuit board. The cages provide an electrical connection between electrical contacts on the transceivers and the conductive tracks. The cages may also act as Faraday cages to reduce electromagnetic interference, and extract heat from the transceiver. In alternative embodiments, the transceivers may be mounted directly to the printed circuit board.

The FPGA described herein (including but not limited to FPGA102) may have any suitable architecture. In one embodiment, the FPGA architecture comprises an array of configurable logic blocks, I/O leads or pins, and routing channels. Generally, but not necessarily, the logic blocks comprise of logical cells that may comprise of, for example, a look up table, a full adder, and a D-type flip flop. Clock signals may be routed through special purpose dedicated clock networks within the FPGA in communication with a CDR module. The FPGA24may also include higher-level functionality including embedded multipliers, generic digital signal processing blocks, embedded processors, high-speed I/O logic for communication with components external of the FPGA (for example), and embedded memories that may be used by buffers.

The internal structure of the FPGAs described herein (including but not limited to FPGA102) is configured to form a plurality of modules. The modules are initially specified, for example, using a hardware description language, examples of which include VHDL and VERILOG. The functionality to be implemented on the FPGA is described in a hardware description language. The description is compiled, synthesized and mapped to the FPGA using appropriate EDA tools to a configuration file that, when loaded or programmed into the FPGA, causes the FPGA to implement the functionality described.

Now that embodiments have been described, it will be appreciated that some embodiments may have some of the following advantages:Modification of a line encoded data stream, for example filtering, may be performed with relatively low latency, which may be advantageous for trading applications, for example.Packet decoding logic may not be required in the line encoded data stream's path within the system, which would introduce latency.Reconfiguring the reconfigurable circuitry may not cause a protocol error.

Variations and/or modifications may be made to the embodiments described without departing from the spirit or ambit of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

Prior art, if any, described herein is not to be taken as an admission that the prior art forms part of the common general knowledge in any jurisdiction.