Trench silicide contacts with high selectivity process

A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

BACKGROUND

Technical Field

The present invention relates to semiconductor processing, and more particularly to methods and devices having a selective self-aligned contact etching process to minimize spacer erosion when forming source and drain contacts in devices with highly scaled gate pitches.

Description of the Related Art

One commonly employed technique for forming gate structures involves forming a line-type gate electrode structure above a layer of insulating material that is formed above an active region defined in a semiconductor substrate. Typically, the line-type gate electrode structures are formed by defining long parallel line-type structures, i.e., gate electrode structures that extend across multiple spaced-apart active regions and the isolation regions formed in the substrate between such spaced-apart active regions. At some point later in the process flow, these long, line-type gate electrode structures are subsequently “cut” by performing an etching process to define the gate electrodes having the desired length in the “gate-width” direction of the transistor device. This results in substantially rectangular shaped gate structures (when viewed from above) having the desired dimensions in the gate-length and gate width directions.

After the gate electrodes are patterned, a sidewall spacer is typically formed around the perimeter of the substantially rectangular shaped gate structure, i.e., the spacer is formed adjacent on all four side sidewalls (two sidewalls and two end surfaces) of each of the patterned gate electrodes. In some cases, a thin liner layer may be formed on the gate structure prior to forming the sidewall spacer. The sidewall spacer, in combination with the gate cap layer, function to protect the gate electrode structure in subsequent processing operations.

Unfortunately, as device dimensions have decreased and packing densities have increased, it is more likely that, when epi semiconductor material is formed in the source/drain regions, some of the epi material may undesirably form on the end surfaces of the polysilicon/amorphous silicon gate electrode. This may occur for several reasons. As noted above, after the gate structures are patterned, a sidewall spacer is formed around all four sides of the gate structure so as to, along with the gate cap layer, encapsulate and protect the gate electrode during subsequent processing operations. As packing densities have increased, the end-to-end spacing between two different gate electrode structures formed above two different active regions has decreased, thereby limiting the physical size, i.e., the width, of the protective sidewall spacers. Additionally, as the pitch between adjacent gate structures has decreased, the width of the protective sidewall spacers must also be decreased.

With respect to forming a sidewall spacer on a device, the duration of the etching process performed to form the spacer is typically increased to ensure that the layer of spacer material is completely cleared from the surfaces of the source/drain regions of the device. This over-etching also tends to reduce the width of the protective spacer. All of these factors and others tend to result in an undesirable thinning of the spacer, particularly at the corner of the gate electrode (the intersection between the side surfaces and the end surfaces of the gate electrode). It is not uncommon that, due to these factors and others, some portion of the polysilicon or amorphous silicon gate electrode material will be exposed at the time epi semiconductor material is formed in the source/drain regions of a planar or FinFET device. As a result, epi semiconductor material will undesirably form on the exposed portions of the gate electrode layer.

The extent and amount of undesirable epi semiconductor material formation will vary depending upon the particular application and the quality of the manufacturing processes used to manufacture the device. As a result of such undesirable and unpredictable epi formation, the resulting semiconductor devices and the integrated circuits including such devices may completely fail or operate at less than acceptable performance levels. Even after gate formation additional processing can still expose sidewall spacers to damage.

For example, current self-aligned contact (SAC) etches employ an oxide plasma dry etch which is selective to SiN to open source/drain (S/D) contact regions. Process margin for this type of process becomes smaller for small nodes (e.g., 7 nm), given the fact that SAC cap thickness may be reduced to only 25 nm, and spacer thickness may be only about 6 nm. This means even a 2 nm spacer thin down during the SAC etch will fail the minimum insulator rule of greater than >5 nm. Scaling of spacers and thinning due to scaling and erosion may result in increased risk of shorts between S/D regions and gate contacts.

SUMMARY

A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device; etching a cut region through a first dielectric layer between the fin regions down to a substrate; filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer; isotropic etching the first dielectric layer to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible, the isotropic etching being super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions; and depositing metal in the trenches to form silicide contacts to the source and drain regions.

Another method for forming self-aligned contacts include etching a cut region through a first dielectric layer between fin regions of a semiconductor device down to a substrate; filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer; planarizing the first material and stopping on the first dielectric layer to form a planar surface; forming and patterning a second dielectric layer on the planar surface to expose portions of the first dielectric layer; isotropic etching the first dielectric layer to expose source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible, the isotropic etching being super selective to remove the first dielectric layer relative to the first material, the second dielectric layer and gate structures, the gate structures being disposed between the source and drain regions; depositing metal in the trenches to form contacts to the source and drain regions; and replacing the second dielectric layer with a second dielectric material.

A device having self-aligned contacts includes a cut region formed between fin regions down to a substrate of a semiconductor device, the cut region including a nitride material. Source and drain regions are disposed in the fin regions, and gate structures are disposed between the source and drain regions. Silicide contacts are connected to the source and drain regions, wherein the silicide contacts have a width that is larger in contact with the source and drain regions and reduced with height to a level of the gate structures.

DETAILED DESCRIPTION

In accordance with the present principles, devices and methods are provided for improvements in is self-aligned contact (SAC) etchings and processing. SACs or CA contacts are formed through at least one dielectric layer to land, self-aligned, on trench silicide (TS) contacts. The silicide contacts may an electrical connection with source/drain regions of field effect transistors (FETs). In the present example, the FETs will include finFETs although the present principles are applicable to other forms of devices (e.g., planar, etc.). In useful embodiments, structures are provided to assist in improving selectivity to preserve dielectric material during contact formation. In one example, SACs are formed through a dielectric material that is highly selectively etchable relative to other materials present which may otherwise experience losses due to inadequate etch selectivity.

Instead of a directional dry etch (e.g., with oxygen plasma to etch carbon based layers (e.g., OPL, resist), or F-based plasma to etch SiO2), an isotropic etch is employed to form SAC openings in the materials present. In one embodiment, the isotropic etch includes a buffered hydrofluoric (BHF) etch or a chemical oxide removal (COR) isotropic oxide removal etch, which gives a much better oxide etch selectivity than a dry etch. Isotropic oxide etches, while useful, have the potential to blow-up the contact critical dimensions (CD), and cause shorts, such as, silicided contact/region tip-to-tip shorts or CA/TS shorts to the gate electrode due to spacer thinning, since isotropic etching does not etch in a single direction, but rather etches in all directions (e.g., horizontally as well as vertically) in the material.

The present principles utilize a selective, isotropic etch of a dielectric layer, e.g., oxide, during a SAC etch (e.g., BHF or COR) to minimize damage to spacers and provide CD control to achieve target design rule (DR) specifications using special structures to achieve these goals in a controlled manner. In one embodiment, a nitride material, e.g., SiN, is employed between contacts as a bottom dielectric layer instead of a conventional SiO2material. Spacer thickness is maintained at substantially its original dimensions before the SAC etch. Spacer profiles versus unetched inactive regions over shallow trench isolation regions showed the same spacer thickness (within tolerance). A contact open angle is less than 90° for silicide contacts. This is in comparison to a greater than 90° open angle for conventional directional dry etching.

Referring now to the drawings in which like numerals represent the same or similar elements,FIGS. 1-8, 10-12each includes an illustrative top view8which includes a section line XX′ transversely through fins and a section line YY′ transversely through gate structures. Cross-sectional views at each of XX′ and YY′ are shown in each ofFIGS. 1-8, 10-12. It should be understood that fin regions10include S/D regions. Regions22include gate structures20, which may be active or dummy gate structures. The present principles are applicable to gate first and gate last processes.

Referring toFIG. 1, the cross-sections taken at section lines XX′ and YY′ are depicted after a gate conductor20(as well as a work function metal and high-k gate dielectric (not shown)) is deposited, planarized and recessed in gate structures22. The gate conductor20may include a metal, e.g., W or other suitable material. Fins14have been etched into a substrate12. The fins14and the substrate12may include a monocrystalline silicon, although other suitable substrate materials may be employed. In one embodiment, the fins14are buried in a dielectric material, which is recessed to expose a portion of the fins14. The portion of the fins14is subjected to an epitaxial growth process to form S/D regions16on the fins14. The S/D regions16and the fins14are buried in a dielectric layer18. The dielectric layer18may include a flowable oxide or other suitable dielectric material.

Gate structures22include completed gate structures (for gate-first or gate-last designs). For gate structures, the gate material includes a gate dielectric (e.g., high-k material (not shown)) and the gate conductor20(e.g., metal, such as W). The gate conductor20may also include a work function metal. The gate structures22have S/D regions16formed on opposite sides of the gate structure22, e.g., by epitaxial growth processing. The gate structures22include sidewall spacers24, which may include a nitride material. S/D regions16may be grown on the fins14between gates structures22by an epitaxial growth process.

Referring toFIG. 2, an organic planarizing (or patterning) layer (OPL)32(or organic dielectric layer (ODL)) is deposited over a top surface of the device on the layer18and over the gate structures22. The OPL32is patterned using a mask (silicide contact mask or TS mask) to form openings30in the OPL32. The OPL32may include a photo-sensitive organic polymer comprising a light-sensitive material that, when exposed to electromagnetic (EM) radiation, is chemically altered and thus configured by the mask (not shown) to be removed using a developing solvent. For example, the photo-sensitive organic polymer may be polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, poly(methyl methacrylate) or benzocyclobutene (BCB).

The patterning of regions32and30corresponds with the fin region10wherein S/D regions16are formed on the fins14. The OPL32fills the recessed regions on top of gate conductor20in the gate structures22.

Referring toFIG. 3, the OPL32is employed as an etch mask to extend recesses30in the dielectric layer18. The OPL32may be etched using a reactive ion etch (RIE) process.

Referring toFIG. 4, the OPL32is stripped off using, e.g., an ash process or wets removal. This exposes the gate conductors20, spacers24and the dielectric layer18. Within dielectric layer18, the S/D regions16and fins14remain protected. A dielectric layer34is deposited to fill in regions30, over the dielectric layer18and fill the gate structures22on the gate conductor20. The dielectric layer34overfills the regions30. The dielectric layer34is formed from a material that can be selectively etched relative to the dielectric layer18. In one embodiment, dielectric layer18may include an oxide, and dielectric layer34may include a nitride (e.g., SiN).

Referring toFIG. 5, the dielectric layer34is planarized down to the dielectric layer18by a planarization process, such as, e.g., a chemical mechanical polish (CMP). Then, a dielectric or amorphous carbon material36is deposited over the dielectric layer34(e.g., SiN) and dielectric layer18for forming local interconnects. The material36is patterned using lithographic processes to open up regions38to expose spacers24and dielectric layer18over the S/D regions16. The patterning of the material36exposes edges40of the dielectric layer34. The material36may include amorphous carbon or other material that withstands etching of the dielectric layer18as will be described. The dielectric layer34forms caps on the gate conductor20in the gate structures22.

Referring toFIG. 6, an isotropic etch is performed to remove the dielectric layer18and recess the dielectric layer18to expose the S/D regions16. The dielectric layer18may be overetched to reveal a portion of the fins14. A thin liner, e.g., SiN, (not shown) may be formed on the region16and fins14to provide an etch stop and protect the epi (16) and fin materials (14). the thin liner is removed prior to silicide formation. The etch process removes the dielectric layer18selectively to the dielectric layer34and to the dielectric material36to form trenches42. The S/D regions16are now accessible to form a silicide contact down to the S/D regions16and the etch stop/SiN liner is removed before silicide formation.

The isotropic etch may include a BHF wet or dry etch, or a chemical oxide removal (COR) process etch. The isotropic etch is preferably a dry selective etch. The isotropic etch is highly selective and removes/recesses dielectric layer18, e.g., an oxide, with respect to the dielectric layer34(e.g., SiN), and dielectric material36(e.g., amorphous C). The dielectric layer34and dielectric material36remain virtually intact. In one embodiment, The selectivity for removing SiO2to SiN for BHF>200:1, for COR˜100:1. The highly selective process protects gate structures and in particular spacers24, which prevents S/D region to gate shorting.

Referring toFIG. 7, the protective SiN liner is selectivity removed before silicide formation and contact formation. A metal silicide is formed on the regions16by depositing a metal and annealing. Then, self-aligned contacts44are formed in the trenches42(FIG. 6). The contacts44may include a liner (not shown). The liner may include, e.g., TiN, although other materials may be employed. Examples of other liner materials include, e.g., TaN, Al2O3, etc. The liner thickness need only be a few nanometers in thickness. The contacts44are formed from a metal, such as W, Al, Ti, etc. After formation of the contact material (metal and liner), a CMP process is performed to planarize a top surface. The contacts44land on and connect to the S/D regions16.

Referring toFIG. 8, another etch process is performed to remove material36(e.g., amorphous carbon, other organic layer or dielectric if etching selectivity is large enough with underlying dielectric34) selectively from dielectric layer18, layer34and spacers24. The etch process to remove material36may include an oxide plasma etch. After removing material36, the material36is replaced with a dielectric material46. Dielectric material46may include an oxide. Dielectric material46fills in spaces where material36was removed. Dielectric material46may be planarized by, e.g., a CMP process.

The contacts44form a single shared contact for all source regions on fins14in each region10and a single shared contact for all drain regions on fins14in each region10. Contacts44may include a silicide (TS) contact48and a self-aligned contact (CA)50. InFIG. 8the CA contacts50are separated. In another embodiment as depicted inFIG. 9the CA contacts50′ may be shared.

Referring toFIG. 10, beginning withFIG. 4, another embodiment is illustratively shown where a contact pattern includes contact openings62that run along the gate structures22. A material60is deposited and patterned using lithography. Material60may include an OPL material, amorphous carbon or a dielectric material.

Referring toFIG. 11, an isotropic etch is performed to remove the dielectric layer18and recess the dielectric layer18to expose the S/D regions16. The etch process removes the dielectric layer18selectively to the dielectric layer34and to the dielectric material60to form trenches64. The S/D regions16are now accessible to form a silicide contact (TS) down to the S/D regions16.

The isotropic etch may include a BHF wet or dry etch, or a COR process etch. The isotropic etch is highly selective and removes/recesses dielectric layer18, e.g., an oxide, with respect to the dielectric layer34(e.g., SiN), and material60(e.g., amorphous C). The dielectric layer34and material60remain virtually intact.

Referring toFIG. 12, the dielectric material60is stripped/removed. If the material60includes OPL an ash process may be performed. Self-aligned TS contacts66are formed in the trenches64(FIG. 11). The contacts66may include a liner (not shown). The liner may include, e.g., TiN, although other materials may be employed. Examples of other liner materials include, e.g., TaN, Al2O3, etc. The liner thickness need only be a few nanometers. The contacts66are formed from a metal, such as W, Al, Ti, etc. After formation of the contact material (metal and liner) a CMP process is performed to planarize a top surface. The contacts66land on and connect to the S/D regions16. As before TS contacts48(FIG. 8) and TS contacts66are formed in layer34, which may include SiN instead of an oxide material. Contacts48and66are formed having sidewalls with an angle less than 90 degrees, which means the contacts are larger at the bottom than the top of the contacts48and66.

In this embodiment, further processing is needed to form CA contacts or contacts connected to the TS contacts66. The CA contacts may be shared or separated as described above with respect toFIGS. 8 and 9. Separated portions of the CA contacts may be filled with SiN, filled with oxide or filled with a combination of materials. In one embodiment, regions34may include an oxide barrier formed therein. The oxide barrier may be formed to adjust dielectric properties of a barrier between TS contacts and/or CA contacts.

Referring toFIG. 13, an illustrative cross-section taken at section line XX′ ofFIG. 12shows an alternate structure with a dielectric material70formed in a TS cut region72between TS contacts66. The dielectric material70may include an oxide and may be deposited after the formation of the layer34. A trench may be etched into the materials of34that may be filled using dielectric material employed in other steps.

In block102, a mask is patterned between fin regions of a semiconductor device. The mask may be formed from an OPL material although other materials may be employed for lithographic patterning. In block104, a cut is etched through a first dielectric layer between the fin regions down to a substrate using the mask. The cut forms a cut region to separate fin regions for the later formation of silicide contacts (trench silicide or TS). The cut region may be referred to as a silicide cut region or a TS cut region. In block106, the cut region is filled with a first material, which is selectively etchable relative to the first dielectric layer (e.g., SiN). In a particularly useful embodiment, the first dielectric layer may include a silicon oxide and the first material may include a silicon nitride.

In block108, the first dielectric layer is isotropically etched to reveal source and drain regions in the active regions and to form trenches in the first material where the source and drain regions are exposed. The S/D regions may have a protective liner (e.g., SiN) formed thereon. The isotropic etch may include a buffered hydrofluoric (BHF) wet etch. The isotropic etch is super selective (e.g., etches oxide:nitride at a ratio of 200:1 or greater and 100:1 or greater for a COR process) to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. In this way, the spacers of the gate structures are preserved while the first dielectric layer is efficiently recessed without concern for damage to other structures.

In block110, metal is deposited in the trenches to form silicide contacts to the source and drain regions. The silicide contacts may extend over the gate structure and may also concurrently form self-aligned contacts or CA contacts in a single process. Alternately, the CA contacts may be formed by additional processing. In useful embodiments, the silicide contacts have a width that is larger in contact with the source and drain regions and reduced with height. In one embodiment, the contacts have a width that is larger in contact with the source and drain regions and reduced with height up to a surface of the first dielectric material or height of the gate structures. The silicide contacts may include lateral sides that form an angle of less than 90 degrees from vertical.

In block112, when trench silicide contacts are formed in a separate process from CA contacts, a dielectric pattern is applied over the first material and the silicide contacts for forming second contacts (CA contacts) on the silicide contacts. In block114, a metal deposition is performed to fill the dielectric pattern to form CA contacts. A planarization process may be performed to complete the contact formation. The second contacts (CA) may be separated or shared between two or more silicided (TS) contacts.

In block120, in another embodiment, the first material may be planarized, stopping on the first dielectric layer to form a planar surface. In block122, a second dielectric layer is formed and patterned on the planar surface to expose portions of the first dielectric layer. In block124, the first dielectric layer is isotropically etched to expose source and drain regions in the active regions to form trenches in the first material where the source and drain regions are exposed. The isotropic etching (e.g., BHF or COR etch) is super selective to remove the first dielectric layer relative to the first material. The second dielectric layer and gate structures are disposed between the source and drain regions.

In block126, metal is deposited in the trenches to form contacts to the source and drain regions. A planarization process may also be employed on the metal. The contacts include a first portion (e.g., TS contact) up to a height of the gate structures and an extended portion (CA contact) that extends above the gate structures. The contacts may have a width that is larger in contact with the source and drain regions and reduced with height up to a surface of the first dielectric material or gate structures. The contacts include lateral sides below a surface of the first dielectric material that forms an angle of less than 90 degrees from vertical.

In block128, the second dielectric layer is replaced with a second dielectric material. The second dielectric layer may include amorphous carbon, which is replaced by an oxide or other suitable dielectric. In accordance with the present principles, the extended portions or CA contacts may be separated by the second dielectric material or the extended portion may be shared between two or more first portions (TS contacts). Processing continues to complete the device.