Methods of forming buried bit line DRAM circuitry

A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.

TECHNICAL FIELD

This invention relates to methods of forming buried bit line DRAM circuitry.

BACKGROUND OF THE INVENTION

An exemplary prior art method of forming buried bit line DRAM circuitry, and issues associated therewith, is described with reference toFIGS. 1-3.FIGS. 1 and 2depict circuitry fabrication relative to a memory array, whereasFIG. 3depicts circuitry fabrication relative to peripheral circuitry which is not within the memory array. A wafer fragment10comprises an exemplary bulk monocrystalline substrate11, for example bulk monocrystalline silicon. Exemplary shallow trench isolation regions12are shown formed relative to substrate11. Within the memory array, exemplary n+ diffusion regions/storage node locations13and15are formed. An n+ diffusion region/bit line node14is also illustrated. A p+ peripheral node16is illustrated relative to the peripheral circuitry (FIG.3). Background doping within the substrate11region ofFIG. 1would typically be p−, while that ofFIG. 3would typically be n−.

Exemplary word line/gate line/conductive interconnects18are illustrated. Preferred constructions for the same include a gate dielectric layer20, a conductively doped polysilicon layer22, a conductive metal silicide layer24and an insulative cap26. Insulative sidewall spacers28are also illustrated as comprising a portion of gate constructions18.

A thin, undoped silicon dioxide layer30has been deposited over the substrate. An example material is silicon dioxide deposited by decomposition of tetraethylorthosilicate (TEOS). Another insulating layer31has been deposited thereover, with an example being doped silicon dioxide, such as borophosphosilicate glass (BPSG). Such has been planarized, as shown, for example by chemical mechanical polishing (CMP).

A photolithographic masking and etch step is then conducted to form storage node vias32and bit line via34in a common masking and in one or more common etching steps. A buried contact implant can then be provided, if desired, to within the typically previously formed diffusion regions13,14and15. Then, n+ polysilicon36is provided, typically by in situ doping during deposition, to overfill openings32and34. Such can then be dry etched or CMP'd back to provide the illustrated isolated plugs36within openings32and34.

Next, an exemplary illustrated peripheral circuit via38is etched within insulative mass31/30(FIG.3). Then, p+ polysilicon40is provided within opening38, typically by in situ doping during deposition. Such polysilicon is then CMP'd or otherwise planarized back to form an isolated plug within peripheral circuitry via38.

Thereafter, a thin undoped silicon dioxide layer42is deposited, preferably by the decomposition of TEOS. Then, photolithographic patterning and oxide etch are conducted to form opening44to the bit contact plugging material36within bit line via34. During this step, or more typically at a later step in the process, openings47(FIG. 3) are also formed within undoped silicon dioxide layer42relative to the peripheral p+ plugging material40received within peripheral vias38.

Metal materials46and48are blanketly deposited over the substrate. Preferably, material46comprises a composite of a physical vapor deposited titanium rich titanium nitride material followed by physical vapor deposition of stoichiometric tungsten nitride. Typically, layer48is then deposited by chemical vapor deposition to principally comprise elemental tungsten. An insulative capping layer51might also be provided. Metal materials46and48are subjected to a photolithographic masking and subtractive etching step to form the illustrated buried bit line52. Nitride spacers54can be provided by deposition and anisotropic etch.

Then, another BPSG layer56is deposited. Such can be by rapid thermal processing and reflow, or any other process. Nitride can also be etched from the backside of the substrate at this point. The BPSG can then be CMP'd or otherwise planarized back. Another photolithographic masking step and patterning can then be conducted to form the illustrated openings58and60within insulative materials56and42to the illustrated material36within openings32, and material40within opening38. Thereafter, conductive plugging material62(i.e., conductively doped polysilicon) is provided within openings58and60, and then etched or otherwise planarized back. Subsequent processing is then conducted to form capacitor constructions in electrical contact with material62within the array.

Full formation of the contacting plugs to conductive nodes13,14,15and16, including the fabrication of the buried bit line, in the above-described process uses five different masking steps, as well as a plethora of deposition steps and dry etch processing. It would be desirable to minimize this complexity and number of steps.

While the invention was motivated in addressing the above issues and improving upon the above-described drawbacks, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification, or the drawings), and in accordance with the doctrine of equivalents.

SUMMARY

The invention includes methods of forming buried bit line DRAM circuitry. In one implementation, a method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass.

In one implementation, a method of forming buried bit line DRAM circuitry includes forming an insulative mass over a substrate. A plurality of via openings are formed through the insulative mass to conductive node locations. At least one of the conductive node locations is a memory array bit line node. At least one of the conductive node locations is a memory array storage node. After forming the plurality of via openings, at least one bit line forming trench is formed within the insulative mass. The bit line forming trench overlies the one via to the memory array bit line node. Conductive material is deposited to within the buried bit line forming trench, the one via to the memory array bit line node, and the one via to the memory array storage node.

In one implementation, a method of forming buried bit line DRAM circuitry includes forming a conductively interconnected mass of conductive material which comprises a bit line, a contact to a memory array storage node, and a contact to a bit line node. The mass has an outer region. A quantity of the outer region of the conductively interconnected mass of conductive material is removed effective to form a bit line in electrical connection with the bit line contact which is electrically isolated from the contact to the memory array storage node.

Other aspects and implementations are contemplated.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Exemplary preferred methods of forming buried bit DRAM circuitry are described with reference toFIGS. 4-16. Referring initially to (FIGS. 4 and 5, a wafer fragment or substrate is indicated generally with reference numeral100. Like numerals from the prior art embodiment described above are utilized where appropriate, with differences or additional emphasis being indicated with different numerals. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated.

Diffusion regions13,14,15and16constitute exemplary conductive node locations. Node locations13and15comprise memory array storage nodes. Diffusion region14constitutes a memory array bit line node. Diffusion region16comprises a peripheral circuitry node. An insulative mass80is formed as part of the illustrated substrate. By way of example only, such preferably comprises an undoped silicon dioxide layer82deposited by the decomposition of TEOS, and an overlying BPSG layer84. An exemplary thickness for layer82is 200 to 300 Angstroms, while an exemplary thickness for layer84is 3000 Angstroms. Preferably, mass80is processed to have a planarized outer surface as shown, for example by chemical mechanical polishing or any other existing or yet-to-be developed techniques.

Referring toFIGS. 6-8, a masking layer86has been deposited and patterned. A preferred material for layer86is photoresist, although other materials, (including multiple materials) and with and without photosensitive materials, are also of course contemplated. A plurality of via openings has been formed through insulative mass80to the conductive node locations, typically and preferably by one or more conventional or yet-to-be-developed etching techniques. In the illustrated example as shown inFIG. 6, via openings88are etched to memory array storage node locations13and15, with via opening90being etched to memory array bit line node14. Also in the most preferred embodiment utilizing the illustrated masking layer86, and correspondingly in the same masking step, periphery circuitry vias are also formed, for example via92to exemplary peripheral circuitry node16.

Referring toFIGS. 9 and 10, using another masking step, a bit line trench96is formed within insulative mass80to overlie via90to memory array bit line node14. In the context of this document, a “bit line forming trench” constitutes a trench formed within a material to create at least a general global outline of a bit line being formed over the substrate. An example preferred technique for doing so is to utilize photolithographic masking and a timed etch, for example, to produce the illustratedFIGS. 9 and 10outline.

The above processing describes and depicts but one example of collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench and memory array storage node-vias within a dielectric mass using only two masking steps, and which, in the preferred embodiment, comprises photolithography and etch. Such also forms, in one preferred embodiment, peripheral circuitry vias within the dielectric mass.

The above also depicts and describes but one exemplary method of forming buried bit line DRAM circuitry which includes forming a plurality of via openings through an insulative mass to conductive node locations on a substrate, with at least one of the conductive node locations being a memory array bit line node and at least one of the conductive node locations being a memory array storage node. At least one bit line forming trench is formed within the insulative mass after forming the plurality of via openings, with the bit line forming trench overlying the one via to the memory array bit line node. In such exemplary aspect, the forming of the plurality of via openings and the forming of the bit line trench comprises photolithography and etch. In one implementation, such photolithography and etch uses different masking steps, and more preferably only two different masking steps.

Referring toFIGS. 11-13, conductive materials, for example depicted layers98and100, are deposited to within buried bit line forming trench96, vias88to memory array storage nodes13and15, via90to memory array bit line node14, and peripheral circuitry via92to peripheral circuitry node16. Preferably as shown, at least some, and preferably all, of the depicted depositing occurs simultaneously into the respective vias and trenches. In one preferred implementation, the deposited conductive material comprises conductive metal. In the context of this document, “metal” is defined as at least one of metal in elemental form, at least two elemental metals in alloy form, or a metal compound. In one preferred implementation, all conductive material provided within the buried bit line forming trench, the bit line vias extending from the bit line forming trench and the memory array storage node vias consists essentially of conductive metal, with the resulting effect being to form conductive plugs and the bit line to consist essentially of conductive metal, as will be apparent from the continuing discussion.

In one preferred implementation, the conductive metal which is deposited comprises a metal compound and an elemental metal. In one preferred implementation, the conductive metal deposited comprises at least two, and more preferably at least three, different metals. For example, and by way of example only, conductive material98can be deposited to comprise a composite of a conductive tungsten, an overlying nitrogen-containing material/compound, and an overlying elemental titanium or a titanium enriched titanium nitride material/compound. Further by way of preferred example only, layer100can be deposited to comprise or consist essentially of elemental tungsten.

In another considered aspect or implementation,FIGS. 11-13depict but one exemplary method of forming a conductively interconnected mass98/100which comprises a bit line, a contact to a memory array storage node and a contact to a bit line node. For purposes of the continuing discussion, conductively interconnected mass98/100can be considered as having an outer region, for example outer region102. Further considered, the collective depositing of materials98/100can be considered as overfilling buried bit line forming trench96, memory array storage node vias88and peripheral circuitry via92. Further in one considered aspect or implementation, the illustrated forming of a conductively interconnected mass of conductive material occurs in at least one deposition, more preferably in at least two depositions and most preferably in the exemplary preferred embodiment in at least three depositions, which is/are common to form the conductive material in all of the bit line, contact to the bit line node, contact to the memory array storage node and contact to the peripheral circuitry node.

Referring toFIGS. 14-16, some quantity of the outer region, for example all of the previously depicted outer region102, of the conductively interconnected mass is removed at least to the insulative mass80effective to electrically isolate the bit line from the contacts to the memory array storage nodes, and from the contacts to the peripheral circuitry. An exemplary preferred process for the removing comprises chemical mechanical polishing. Of course, other techniques, for example blanket etch back/resist etch back, or any other existing or yet-to-be-developed removing methods are also contemplated. In the illustrated preferred embodiment, the removing preferably forms discontinuous outer surfaces125of the deposited conductive material which, as shown, lies in a common plane, for example a plane “P”. Of course, subsequent insulative and/or barrier layers can be provided following theFIGS. 14-16processing to continue the processing or connection with higher layers to be formed on the substrate, for example to storage capacitors for the DRAM array.

The above-described preferredFIGS. 14-16embodiment is functionally equivalent to that depicted byFIGS. 1-3and can be a simplification thereof.