Low power flip-flop element with gated clock

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate generally to computer systems and, more specifically, to a low power flip-flop element with gated clock.

2. Description of the Related Art

In computer systems, there is widespread utilization of flip-flop elements. A flip-flop element, also known as a bi-stable multivibrator, is a circuit that has two stable states and may be used to store data. A periodic signal, known as a clock, is applied to one input of the flip-flop element in order to transfer the state of a second, data input signal to the output on the rising edge of the clock.

A typical flip-flop element is configured in a master-slave arrangement. An input latch, know as the master latch, couples the input data to a second latch, known as the slave latch, on the rising edge of the clock signal. The slave latch couples the data from the master latch to the output on the falling edge of the clock signal. The master latch and slave latch each generate multiple clock inversions to implement the data capture functionality.

A number of P-channel and N-channel metal-oxide-semiconductor (MOS) field effect transistors (FETs) are configured in a circuit arrangement to construct the flip-flop element. Within the circuit arrangement, some of the FETs are coupled in pairs, consisting of one PFET and one NFET, to form inverters. Inverters consume power during the switching intervals, and power consumption increases as the frequency of operation increases. Further, all FETs dissipate power due to charging and discharging of junction capacitances whenever a varying signal is applied.

During operation, in a conventional flip-flop element, clocking action is applied to a number of the FET junctions and inverters within the flip-flop element on each clock cycle. For example, if the data input is high, the flip-flop element clocks the high input level to the output. If, on the next cycle, the data input is low, the flip-flop element will clock the low input level to the output. Alternatively, if the data input has remained high, the flip-flop element will clock the high level input level to the output on the next cycle even though the output already had been set high on the prior cycle. Thus, all clocking action results in numerous junction transitions regardless of whether the input changes.

Each clocking action in each individual FET causes dissipation, and the sum of these dissipations equals the dissipation of each individual flip-flop element. The sum of the dissipations of all flip-flop elements represents a portion of the system usage that may exceed twenty percent of the total power consumption.

One drawback to the above approach is that clocking of flip-flop elements incurs power dissipation on each clock cycle regardless of the state of the input data. In a computer system, over a long period, the number of ones and zeroes may be expected to be generally equivalent. Computer data carries information, but a simple alternating sequence of ones and zeroes, such as a clock signal, carries no information. Consequently, consecutive bit sequences during which the logic state remains unchanged must occur in the data signal. In such sequences, it is necessary to capture the first bit only, as the output is unchanged for subsequent bits. Thus, the power consumption due to internal clocking of flip-flop elements is generally avoidable and represents excessive usage.

As the foregoing illustrates, what is needed in the art is a more effective technique for reducing the power dissipated by a flip-flop element.

SUMMARY OF THE INVENTION

One embodiment of the present invention sets forth a circuit element configured to perform a data capture operation, including a first latch element configured to receive a first data signal that has a first logic state, invert the first logic state to generate a first inverted logic state, receive a first clock signal, and invert the first clock signal to generate a first inverted clock signal. The circuit element further includes a first logic element coupled to the first latch element and configured to gate the first inverted clock signal with the first inverted logic state to generate a second clock signal, and output the second clock signal to the first latch element, where the first latch element, in response to the second clock signal, inverts the first data signal to generate a first inverted data signal.

One advantage of the disclosed approach is that gating the clock inversion according to the state of the input data substantially reduces the number of transitions that the constituent FETs and inverters undergo, which results in less overall power consumption. Further, combining functionality of constituent FETs reduces the number of constituent FETs and, hence, reduces the number of overall transitions in the circuit, which further reduces power consumption.

DETAILED DESCRIPTION

System Overview

FIG. 1is a block diagram illustrating a computer system100configured to implement one or more aspects of the present invention. As shown, computer system100includes, without limitation, a central processing unit (CPU)102and a system memory104coupled to a parallel processing subsystem112via a memory bridge105and a communication path113. Memory bridge105is further coupled to an I/O (input/output) bridge107via a communication path106, and I/O bridge107is, in turn, coupled to a switch116.

In operation, I/O bridge107is configured to receive user input information from input devices108, such as a keyboard or a mouse, and forward the input information to CPU102for processing via communication path106and memory bridge105. Switch116is configured to provide connections between I/O bridge107and other components of the computer system100, such as a network adapter118and various add-in cards120and121.

As also shown, I/O bridge107is coupled to a system disk114that may be configured to store content and applications and data for use by CPU102and parallel processing subsystem112. As a general matter, system disk114provides non-volatile storage for applications and data and may include fixed or removable hard disk drives, flash memory devices, and CD-ROM (compact disc read-only-memory), DVD-ROM (digital versatile disc-ROM), Blu-ray, HD-DVD (high definition DVD), or other magnetic, optical, or solid state storage devices. Finally, although not explicitly shown, other components, such as universal serial bus or other port connections, compact disc drives, digital versatile disc drives, film recording devices, and the like, may be connected to I/O bridge107as well.

In various embodiments, memory bridge105may be a Northbridge chip, and I/O bridge107may be a Southbridge chip. In addition, communication paths106and113, as well as other communication paths within computer system100, may be implemented using any technically suitable protocols, including, without limitation, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

In some embodiments, parallel processing subsystem112comprises a graphics subsystem that delivers pixels to a display device110that may be any conventional cathode ray tube, liquid crystal display, light-emitting diode display, or the like. In such embodiments, the parallel processing subsystem112incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry. As described in greater detail below inFIG. 2, such circuitry may be incorporated across one or more parallel processing units (PPUs) included within parallel processing subsystem112. In other embodiments, the parallel processing subsystem112incorporates circuitry optimized for general purpose and/or compute processing. Again, such circuitry may be incorporated across one or more PPUs included within parallel processing subsystem112that are configured to perform such general purpose and/or compute operations. In yet other embodiments, the one or more PPUs included within parallel processing subsystem112may be configured to perform graphics processing, general purpose processing, and compute processing operations. System memory104includes at least one device driver103configured to manage the processing operations of the one or more PPUs within parallel processing subsystem112.

In various embodiments, parallel processing subsystem112may be integrated with one or more of the other elements ofFIG. 1to form a single system. For example, parallel processing subsystem112may be integrated with CPU102and other connection circuitry on a single chip to form a system on chip (SoC).

It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs102, and the number of parallel processing subsystems112, may be modified as desired. For example, in some embodiments, system memory104could be connected to CPU102directly rather than through memory bridge105, and other devices would communicate with system memory104via memory bridge105and CPU102. In other alternative topologies, parallel processing subsystem112may be connected to I/O bridge107or directly to CPU102, rather than to memory bridge105. In still other embodiments, I/O bridge107and memory bridge105may be integrated into a single chip instead of existing as one or more discrete devices. Lastly, in certain embodiments, one or more components shown inFIG. 1may not be present. For example, switch116could be eliminated, and network adapter118and add-in cards120,121would connect directly to I/O bridge107.

FIG. 2is a block diagram of a parallel processing unit (PPU)202included in the parallel processing subsystem112ofFIG. 1, according to one embodiment of the present invention. AlthoughFIG. 2depicts one PPU202, as indicated above, parallel processing subsystem112may include any number of PPUs202. As shown, PPU202is coupled to a local parallel processing (PP) memory204. PPU202and PP memory204may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or memory devices, or in any other technically feasible fashion.

In some embodiments, PPU202comprises a graphics processing unit (GPU) that may be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data supplied by CPU102and/or system memory104. When processing graphics data, PP memory204can be used as graphics memory that stores one or more conventional frame buffers and, if needed, one or more other render targets as well. Among other things, PP memory204may be used to store and update pixel data and deliver final pixel data or display frames to display device110for display. In some embodiments, PPU202also may be configured for general-purpose processing and compute operations.

In operation, CPU102is the master processor of computer system100, controlling and coordinating operations of other system components. In particular, CPU102issues commands that control the operation of PPU202. In some embodiments, CPU102writes a stream of commands for PPU202to a data structure (not explicitly shown in eitherFIG. 1orFIG. 2) that may be located in system memory104, PP memory204, or another storage location accessible to both CPU102and PPU202. A pointer to the data structure is written to a pushbuffer to initiate processing of the stream of commands in the data structure. The PPU202reads command streams from the pushbuffer and then executes commands asynchronously relative to the operation of CPU102. In embodiments where multiple pushbuffers are generated, execution priorities may be specified for each pushbuffer by an application program via device driver103to control scheduling of the different pushbuffers.

As also shown, PPU202includes an I/O (input/output) unit205that communicates with the rest of computer system100via the communication path113and memory bridge105. I/O unit205generates packets (or other signals) for transmission on communication path113and also receives all incoming packets (or other signals) from communication path113, directing the incoming packets to appropriate components of PPU202. For example, commands related to processing tasks may be directed to a host interface206, while commands related to memory operations (e.g., reading from or writing to PP memory204) may be directed to a crossbar unit210. Host interface206reads each pushbuffer and transmits the command stream stored in the pushbuffer to a front end212.

As mentioned above in conjunction withFIG. 1, the connection of PPU202to the rest of computer system100may be varied. In some embodiments, parallel processing subsystem112, which includes at least one PPU202, is implemented as an add-in card that can be inserted into an expansion slot of computer system100. In other embodiments, PPU202can be integrated on a single chip with a bus bridge, such as memory bridge105or I/O bridge107. Again, in still other embodiments, some or all of the elements of PPU202may be included along with CPU102in a single integrated circuit or system on chip (SoC).

In operation, front end212transmits processing tasks received from host interface206to a work distribution unit (not shown) within task/work unit207. The work distribution unit receives pointers to processing tasks that are encoded as task metadata (TMD) and stored in memory. The pointers to TMDs are included in a command stream that is stored as a pushbuffer and received by the front end unit212from the host interface206. Processing tasks that may be encoded as TMDs include indices associated with the data to be processed as well as state parameters and commands that define how the data is to be processed. For example, the state parameters and commands could define the program to be executed on the data. The task/work unit207receives tasks from the front end212and ensures that GPCs208are configured to a valid state before the processing task specified by each one of the TMDs is initiated. A priority may be specified for each TMD that is used to schedule the execution of the processing task. Processing tasks also may be received from the processing cluster array230. Optionally, the TMD may include a parameter that controls whether the TMD is added to the head or the tail of a list of processing tasks (or to a list of pointers to the processing tasks), thereby providing another level of control over execution priority.

PPU202advantageously implements a highly parallel processing architecture based on a processing cluster array230that includes a set of C general processing clusters (GPCs)208, where C≥1. Each GPC208is capable of executing a large number (e.g., hundreds or thousands) of threads concurrently, where each thread is an instance of a program. In various applications, different GPCs208may be allocated for processing different types of programs or for performing different types of computations. The allocation of GPCs208may vary depending on the workload arising for each type of program or computation.

Memory interface214includes a set of D of partition units215, where D≥1. Each partition unit215is coupled to one or more dynamic random access memories (DRAMs)220residing within PPM memory204. In one embodiment, the number of partition units215equals the number of DRAMs220, and each partition unit215is coupled to a different DRAM220. In other embodiments, the number of partition units215may be different than the number of DRAMs220. Persons of ordinary skill in the art will appreciate that a DRAM220may be replaced with any other technically suitable storage device. In operation, various render targets, such as texture maps and frame buffers, may be stored across DRAMs220, allowing partition units215to write portions of each render target in parallel to efficiently use the available bandwidth of PP memory204.

A given GPC208may process data to be written to any of the DRAMs220within PP memory204. Crossbar unit210is configured to route the output of each GPC208to the input of any partition unit215or to any other GPC208for further processing. GPCs208communicate with memory interface214via crossbar unit210to read from or write to various DRAMs220. In one embodiment, crossbar unit210has a connection to I/O unit205, in addition to a connection to PP memory204via memory interface214, thereby enabling the processing cores within the different GPCs208to communicate with system memory104or other memory not local to PPU202. In the embodiment ofFIG. 2, crossbar unit210is directly connected with I/O unit205. In various embodiments, crossbar unit210may use virtual channels to separate traffic streams between the GPCs208and partition units215.

Again, GPCs208can be programmed to execute processing tasks relating to a wide variety of applications, including, without limitation, linear and nonlinear data transforms, filtering of video and/or audio data, modeling operations (e.g., applying laws of physics to determine position, velocity and other attributes of objects), image rendering operations (e.g., tessellation shader, vertex shader, geometry shader, and/or pixel/fragment shader programs), general compute operations, etc. In operation, PPU202is configured to transfer data from system memory104and/or PP memory204to one or more on-chip memory units, process the data, and write result data back to system memory104and/or PP memory204. The result data may then be accessed by other system components, including CPU102, another PPU202within parallel processing subsystem112, or another parallel processing subsystem112within computer system100.

As noted above, any number of PPUs202may be included in a parallel processing subsystem112. For example, multiple PPUs202may be provided on a single add-in card, or multiple add-in cards may be connected to communication path113, or one or more of PPUs202may be integrated into a bridge chip. PPUs202in a multi-PPU system may be identical to or different from one another. For example, different PPUs202might have different numbers of processing cores and/or different amounts of PP memory204. In implementations where multiple PPUs202are present, those PPUs may be operated in parallel to process data at a higher throughput than is possible with a single PPU202. Systems incorporating one or more PPUs202may be implemented in a variety of configurations and form factors, including, without limitation, desktops, laptops, handheld personal computers or other handheld devices, servers, workstations, game consoles, embedded systems, and the like.

Operation of GPC208is controlled via a pipeline manager305that distributes processing tasks received from a work distribution unit (not shown) within task/work unit207to one or more streaming multiprocessors (SMs)310. Pipeline manager305may also be configured to control a work distribution crossbar330by specifying destinations for processed data output by SMs310.

In one embodiment, GPC208includes a set of M of SMs310, where M≥1. Also, each SM310includes a set of functional execution units (not shown), such as execution units and load-store units. Processing operations specific to any of the functional execution units may be pipelined, which enables a new instruction to be issued for execution before a previous instruction has completed execution. Any combination of functional execution units within a given SM310may be provided. In various embodiments, the functional execution units may be configured to support a variety of different operations including integer and floating point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit-shifting, and computation of various algebraic functions (e.g., planar interpolation and trigonometric, exponential, and logarithmic functions, etc.). Advantageously, the same functional execution unit can be configured to perform different operations.

In operation, each SM310is configured to process one or more thread groups. As used herein, a “thread group” or “warp” refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different execution unit within an SM310. A thread group may include fewer threads than the number of execution units within the SM310, in which case some of the execution may be idle during cycles when that thread group is being processed. A thread group may also include more threads than the number of execution units within the SM310, in which case processing may occur over consecutive clock cycles. Since each SM310can support up to G thread groups concurrently, it follows that up to G*M thread groups can be executing in GPC208at any given time.

Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SM310. This collection of thread groups is referred to herein as a “cooperative thread array” (“CTA”) or “thread array.” The size of a particular CTA is equal to m*k, where k is the number of concurrently executing threads in a thread group, which is typically an integer multiple of the number of execution units within the SM310, and m is the number of thread groups simultaneously active within the SM310.

Although not shown inFIG. 3, each SM310contains a level one (L1) cache or uses space in a corresponding L1 cache outside of the SM310to support, among other things, load and store operations performed by the execution units. Each SM310also has access to level two (L2) caches (not shown) that are shared among all GPCs208in PPU202. The L2 caches may be used to transfer data between threads. Finally, SMs310also have access to off-chip “global” memory, which may include PP memory204and/or system memory104. It is to be understood that any memory external to PPU202may be used as global memory. Additionally, as shown inFIG. 3, a level one-point-five (L1.5) cache335may be included within GPC208and configured to receive and hold data requested from memory via memory interface214by SM310. Such data may include, without limitation, instructions, uniform data, and constant data. In embodiments having multiple SMs310within GPC208, the SMs310may beneficially share common instructions and data cached in L1.5 cache335.

Each GPC208may have an associated memory management unit (MMU)320that is configured to map virtual addresses into physical addresses. In various embodiments, MMU320may reside either within GPC208or within the memory interface214. The MMU320includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile or memory page and optionally a cache line index. The MMU320may include address translation lookaside buffers (TLB) or caches that may reside within SMs310, within one or more L1 caches, or within GPC208.

In graphics and compute applications, GPC208may be configured such that each SM310is coupled to a texture unit315for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data.

In operation, each SM310transmits a processed task to work distribution crossbar330in order to provide the processed task to another GPC208for further processing or to store the processed task in an L2 cache (not shown), parallel processing memory204, or system memory104via crossbar unit210. In addition, a pre-raster operations (preROP) unit325is configured to receive data from SM310, direct data to one or more raster operations (ROP) units within partition units215, perform optimizations for color blending, organize pixel color data, and perform address translations.

It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Among other things, any number of processing units, such as SMs310, texture units315, or preROP units325, may be included within GPC208. Further, as described above in conjunction withFIG. 2, PPU202may include any number of GPCs208that are configured to be functionally similar to one another so that execution behavior does not depend on which GPC208receives a particular processing task. Further, each GPC208operates independently of the other GPCs208in PPU202to execute tasks for one or more application programs. In view of the foregoing, persons of ordinary skill in the art will appreciate that the architecture described inFIGS. 1-3in no way limits the scope of the present invention.

Low Power Flip-Flop Element with Gated Clock

FIG. 4is a conceptual diagram of a flip-flop element402that includes a gated clock, according to one embodiment of the present invention. Flip-flop element402may be included within any portion of computer system100ofFIG. 1that is configured to capture data to perform operations. For example, CPU102ofFIG. 1or PPU202ofFIG. 2may include one or more instances of flip-flop element402. As a general matter, flip-flop element402may be incorporated into any type of computer device, including server machines, desktop machines, laptop computers, mobile devices, handheld devices, and so forth.

As shown, flip-flop element402includes master latch404, slave latch406, and NAND gate408. Flip-flop element402couples clock412to M-Clk420, the clock input of master latch404, to S-Clk430, the clock input of slave latch406, and to one input of NAND gate408.

Flip-flop element402, further, couples data in410to M-D418, the data input port of master latch404. Master latch404produces the state of data in410at the output port, M-Q426, on the rising edge of clock412. Master latch404couples the state of data in410to S-D428, the data input port of slave latch406. Master latch404, then, couples the inversion of the state of data in410, at M-Q-not424, to the second input of NAND gate408. When M-Q-not424is low, the output of NAND gate408is gated high.

NAND gate408produces an inversion of clock412only when m-q-not424is high. Thus, gated-clock-not414is an inversion of clock412that is gated according to the state of data in410. Gated-clock-not414is, then, coupled to M-Clk-not422, the inverted clock input of master latch404, and to S-Clk-not432, the inverted clock input of slave latch406. Slave latch406forwards the state of the S-D428input to the S-Q434output to produce latched data416.

In this manner, all clock inversion transitions within master latch404and slave latch406are controlled by gated-clock-not414. When gated-clock-not414is at a high logic level, the high input to NAND gate408enables NAND gate408to produce the inversion of clock412at the output as gated-clock-not414. All junctions coupled to gated-clock-not414, then, transition between the high and low level with each cycle of clock412. However, when gated-clock-not414is at a low logic level, the low input to NAND gate408forces the output of NAND gate408to a steady high state, and all transitions of gated-clock-not414cease. All junctions coupled to gated-clock-not414will, then, be in an idle state. Thus, the number of transitions and the consequent power penalty associated with the inverted clock may be reduced, as described above, by generally the proportionality of the two logic states. Consequently, a substantial reduction in system power usage may be realized.

FIG. 5is a more detailed illustration of flip-flop element402ofFIG. 4, according to one embodiment of the present invention. As shown, master latch404includes an input stack formed by PFETs506and508, and NFETs510and512. Master latch404further includes a keeper formed by PFETs514and516, NFETs518and520, and inverter522. NAND gate408includes PFETs524and530, and NFETs526and528. Slave latch406includes an input stack formed by PFET532and NFETs534and536, and a keeper formed by PFET538, NFETs540and542and inverters544and546.

Flip-flop element402couples data in410to the input stack of master latch404. PFET508and NFET510constitute an inverter that is gated by clock412, applied to PFET506, and by gated-clock-not414, applied to NFET512. The input stack of master latch404couples inverted data to the keeper of master latch404as M-Q-not424. Gated-clock-not414controls PFET514, which gates the common504connection to PFET516and NFET518. Similarly, clock412controls FET520, which gates the supply voltage502connection to PFET516and NFET518. Thus, master latch404retains the inversion of the state of data in410.

Master latch404couples captured data inversion, M-Q-not424, to one input of NAND gate408. Flip-flop element402couples clock412to the second input of NAND gate408. NAND gate408, then, produces gated-clock-not414which is the gated inversion of clock412.

Master latch404, further, couples captured data, M-Q-26to the data input of slave latch406, NFET534. Gated-clock-not414controls PFET532, which gates the supply voltage502connection to NFET534. Similarly, clock412controls NFET536, which gates the common504connection to NFET534.

The circuit topology of the input stack of slave latch406consists of a single FET in the inverter portion. The function of an upper FET of the inverter portion, analogous to PFET508in master latch404, would be redundant with the implementation of the inversion clock via gated-clock-not414. Further, in the keeper of slave latch406, PFET506, common to master latch404input stack, performs the functionality of the upper clocking FET, analogous to PFET514in master latch404. Thus, slave latch704eliminates two FETs compared to conventional designs.

Eliminating two FETs reduces power usage in the flip-flop element. Further, the gating of the clock inversion achieved by NAND gate408allow substantial reduction in the number of junction transitions occurring on each clock cycle. Thus, the staticized flip-flop element affords substantial reduction in the power consumption.

FIG. 6is a conceptual diagram of flip-flop element602that includes a simplified master latch604, according to one embodiment of the present invention. Flip-flop element602includes some of the same elements as flip-flop element402described above in conjunction withFIGS. 4-5. However, certain elements have been removed in flip-flop element602compared to flip-flop element402. In particular, master latch604does not include NFET520, as is shown. Instead, master latch604utilizes NFET528, within NAND gate408, to implement the functionality of NFET520. In this manner, flip-flop element602achieves further power reduction by reducing the number of constituent FETs.

FIG. 7is a conceptual diagram of a flip-flop element702that includes a simplified slave latch704, according to one embodiment of the present invention. Flip-flop element702includes some of the same elements as flip-flop element602described above in conjunction withFIG. 6. However, certain elements have been removed in flip-flop element702compared to flip-flop element602. In particular, slave latch704does not include NFET542, as is shown. Instead, slave latch704utilizes NFET512, within master latch404, to implement the functionality of NFET542. In this manner, flip-flop element702achieves further power reduction by further reducing the number of constituent FETs.

FIG. 8is a conceptual diagram of a flip-flop element802configured to implement clock inversion gating, according to one embodiment of the present invention. Flip-flop element802includes some of the same elements as flip-flop element702described above in conjunction withFIG. 7. However, certain additional elements have been included in flip-flop element802compared to flip-flop element702. In particular, logic gate804includes PFET806, as is shown. Further, flip-flop element802includes inverter808.

The inclusion of PFET806transforms the functionality of the logic gate804into a two-input and-or-invert, (AOI22). Data in410couples to inverter808, producing the inversion of data in410to drive PFET806. Consequently, PFET806enables toggling of gated-clock-not414by the switching action of PFET530only when data in410is high.

Thus, PFET806prevents a series of zeroes at data in410from repeatedly precharging gated-clock-not414. Reducing the number of transitions of gated-clock-not414further reduces the power usage of staticized master-slave flip-flop element802.

FIG. 9is a conceptual diagram of a flip-flop element902configured to minimize clocking transitions within a flip-flop element, according to one embodiment of the present invention. Flip-flop element902includes some of the same elements as flip-flop element802described above in conjunction withFIG. 8. However, the interconnections of certain elements have been altered in flip-flop element902compared to flip-flop element802. Specifically, slave latch904couples the gate drive of NFET534to gated-clock-not414, as is shown. Coupling the gate drive of NFET534to gated-clock-not414reduces the transitions of NFET534and provides further power reduction.

FIG. 10is a conceptual diagram of a flip-flop element1002configured to implement a clean input latch1004, according to one embodiment of the present invention. Flip-flop element1002includes some of the same elements as flip-flop element702described above in conjunction withFIG. 7. However, the connectivity of the input latch1004is configured to implement clean data capture that is significantly less susceptible to spurious transitions. Input latch1004receives four inputs. Specifically, the inputs to input latch1004are data in410, clock412, gated-clock-not414, and the master true storage node M-Q426in a configuration known in the industry as an AND-OR-INVERT gate. PFET1006gates clock-not1010, which is the inversion of the clock412. Further, gated-clock-not connects to PFET1008to reduce transitions at M-Q426.

FIG. 11is a conceptual diagram of a flip-flop element1102configured to implement a tristate logic element via a gated pull-up on the inverted clock414, according to one embodiment of the present invention. Flip-flop element1102includes some of the same elements as flip-flop element702described above in conjunction withFIG. 7. However, PFET1106and PFET1108are included in slave latch1104to provide a gated pull-up that reduces unnecessary toggling of gated-clock-not414. Further, the gate of PFET530is coupled to data in not1110to provide further immunity to spurious toggling.

In sum, a flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

One advantage of the flip-flop elements disclosed herein is that gating the clock inversion according to the state of the input data reduces the number of transitions that internal components incur. Combining elements with common functionality further reduces component count and transitions within the flip-flop element. Reducing the number of FETs and inverters within the flip-flop element and the number of internal transitions results in a substantial reduction in flip-flop element power usage.

The invention has been described above with reference to specific embodiments. Persons of ordinary skill in the art, however, will understand that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Therefore, the scope of embodiments of the present invention is set forth in the claims that follow.