Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same

A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0016341, filed on 26 Feb., 2009, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference as if set forth fully herein.

BACKGROUND

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and method for changing at least one characteristic thereof and a semiconductor system including the semiconductor device.

For non-volatile memory devices, there exist specifications on endurance (e.g., the number of times that erase and program operations can be performed) and retention (e.g., a period of time while data can be retained). Accordingly, when the quantities of the erase operations and/or program operations increase, fail data may occur in non-volatile memory devices. When the fail data cannot be recovered, data reliability may decrease.

SUMMARY

Some embodiments of the present invention provide semiconductor devices and methods for changing a parameter, which may affect at least one of endurance and retention, during operation and a semiconductor system including the semiconductor device.

Some embodiments of such methods include receiving and storing data in a storage region and changing at least one of a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage region. In some embodiments, the parameter is a program time, an erase time, a read time, a program voltage, an erase voltage, a read voltage, a reference cell voltage, a program current, an erase current, a read current, and/or a reference cell current. Some embodiments provide that the DC characteristic is a DC current or voltage level. In some embodiments, the AC timing characteristic is a parameter control signal time value.

Some embodiments provide that changing the at least one of the DC characteristic and the AC timing characteristic of the parameter includes generating multiple DC voltages according to a first portion of the data stored in the storage region and generating multiple AC timing signals according to a second portion of the data stored in the storage region. Embodiments may include generating a parameter control signal by mixing one of the DC voltages and one of the AC timing signals in response to selection signals, changing at least one of the DC characteristic and the AC timing characteristic of the parameter in response to the parameter control signal and accessing the non-volatile memory cell according to a changed parameter.

Some embodiments of the present invention include methods of changing a parameter in a semiconductor system that includes a semiconductor device and a controller controlling an operation of the semiconductor device. Such methods may include monitoring, using the controller, a characteristic of a memory cell of the semiconductor device, generating a data set including a command and data based on a monitoring result, and transmitting the data set to the semiconductor device. Methods may further include changing, using the semiconductor device, at least one of a DC characteristic and an AC timing characteristic of a parameter used to access the memory cell according to the data received from the controller.

In some embodiments, the characteristic of the memory cell is at least one of an endurance property of the memory cell and a retention property of the memory cell. Some embodiments provide that the DC characteristic is a DC voltage or current level and the AC timing characteristic is a parameter time.

Some embodiments of the present invention include a semiconductor device that includes a memory core including multiple non-volatile memory cells, an access block configured to access the non-volatile memory cells, and a control block configured to change, responsive to externally input data, at least one of a DC level and an AC timing characteristic of a parameter control signal that is provided to the access block to change at least one between a DC characteristic and an AC timing characteristic of a parameter used to access the non-volatile memory cells.

In some embodiments, the control block includes a voltage generation block configured to generate multiple DC voltages according to a first portion of the data, a timing generation block configured to generate multiple AC timing signals according to a second portion of the data, and a level/timing adjustment block configured to generate the parameter control signal by mixing one of the DC voltages and one of the AC timing signals in response to selection signals.

Some embodiments provide that when the access block includes a wordline driver block that drives wordlines connected with the non-volatile memory cells, the control block provides the parameter control signal to the wordline driver block.

In some embodiments, when the access block includes a program block that programs data to the non-volatile memory cells, the control block provides the parameter control signal to the program block in a program operation to change at least one of the DC characteristic and the AC timing characteristic of the parameter that defines a program time, a program voltage, or a program current.

Some embodiments provide that when the access block includes a read block that reads data from the non-volatile memory cells, the control block provides the parameter control signal to the read block in a read operation to change at least one of the DC characteristic and the AC timing characteristic of the parameter that defines a development time, a read voltage, or a read current.

In some embodiments, when the access block includes an erase block that erases the non-volatile memory cells, the control block provides the parameter control signal to the erase block in an erase operation to change at least one of the DC characteristic and the AC timing characteristic of the parameter that defines an erase time, an erase voltage, or an erase current.

Some embodiments provide that when the access block includes a reference memory cell, the control block provides the parameter control signal to the reference memory cell to change at least one of the DC characteristic and the AC timing characteristic of the parameter that defines a reference cell current or a reference cell voltage.

Some embodiments of the present invention are directed to a semiconductor system that includes a semiconductor device including a memory core that includes multiple non-volatile memory cells and a controller configured to control an operation of the semiconductor device. Some embodiments provide that the controller is configured to monitor a characteristic of the non-volatile memory cells, to generate a data set based on a monitoring result, and to transmit the data set to the semiconductor device. In some embodiments, the semiconductor device further includes a storage region configured to store data included in the data set, an access block configured to access the non-volatile memory cells, and a control block configured to change at least one between a DC level and an AC timing characteristic of a parameter control signal provided to the access block to change at least one of a DC characteristic and an AC timing characteristic of a parameter used to access the non-volatile memory cells according to the data stored in the storage region.

In some embodiments, the characteristic of the non-volatile memory cells includes at least one of endurance and retention of the non-volatile memory cells. Some embodiments provide that the controller generates the data set based on a result of comparing a monitored endurance with a reference endurance. In some embodiments, the controller generates the data set based on a result of comparing a monitored endurance with a reference endurance and based on a marginal distribution. Some embodiments provide that the controller informs a user of the monitoring result through an interface logic unit and generates the data set according to a parameter change signal input by the user through the interface logic unit.

In some embodiments, the control block includes a voltage generation block configured to generate multiple DC voltages according to a first portion of the data, a timing generation block configured to generate multiple AC timing signals according to a second portion of the data, and a level/timing adjustment block configured to generate the parameter control signal by mixing one of the DC voltages and one of the AC timing signals in response to selection signals.

Some embodiments provide that the parameter is a program time, an erase time, a read time, a program voltage, an erase voltage, a read voltage, a reference cell voltage, a program current, an erase current, a read current, and/or a reference cell current. In some embodiments, the DC characteristic is a DC level and the AC timing characteristic is a time.

It is noted that aspects of the invention described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present invention are explained in detail in the specification set forth below.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1illustrates a semiconductor system10including a controller20and a semiconductor device30and a data set generated by the controller20according to some embodiments of the present invention.FIG. 14is a flowchart of the operations of the semiconductor system10according to some embodiments of the present invention.

Referring toFIG. 1, the semiconductor system10includes the controller20and the semiconductor device (or memory device)30. The semiconductor system10may be a computer (PC, notebook, or net book), a handheld terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart card, a memory card, an image pickup (or capture) device, a digital camera, a camcorder, a mobile communication device, a data storage device such as a solid state drive (SSD), and/or consumer equipment (CE), among others.

The controller20may be any control device that can generally control the program, write, read, or erase operation of the semiconductor device (or memory device)30including non-volatile memory cells. The controller20may communicate data with an external device (not shown). Referring toFIGS. 1 and 14, the controller20may monitor the endurance and/or retention of a non-volatile memory cell included in the semiconductor device30(FIG. 14, block2).

According to the monitoring result, the controller20may generate a data set for changing at least one between a direct current (DC) characteristic and an alternating current (AC) timing characteristic of a parameter control signal for changing at least one between a DC characteristic and an AC timing characteristic of a parameter that defines an access operation, e.g., a program operation, a write operation, a read operation, or an erase operation, of the semiconductor device30. The controller20may be implemented in hardware and may include an electronic recording medium (e.g., a microprocessor) that can be equipped with firmware, which can generate the data set.

For instance, the controller20may periodically and/or non-periodically monitor the endurance and/or retention of a non-volatile memory cell included in the semiconductor device30(FIG. 14, block2) and, according to the monitoring result, the controller20may automatically generate a data set for changing at least one between the DC characteristic (e.g., a DC level) and the AC timing characteristic (e.g., a time or a period) of a parameter control signal and transmit the data set to the semiconductor device30(FIG. 14, block4). Thereafter, the semiconductor device30may decode a command CMD included in the received data set and change at least one between the predetermined DC characteristic of a parameter (referred to as a “DC parameter”) and the predetermined AC timing characteristic of the parameter (referred to as an “AC parameter”) according to data DATA included in the data set (FIG. 14, block6).

For instance, the controller20may generate a data set including a command CMD, an address ADD, and/or data DATA in response to a parameter change signal input by a user or according to a result of monitoring the operation characteristics (e.g., at least one between endurance and retention) of the semiconductor device30and transmit the data set to the semiconductor device30via a wired and/or wireless connection (FIG. 14, block4). The address ADD may be a signal indicating a storage region, e.g., a position in a register43(FIG. 2), in which the data DATA will be stored in the semiconductor device30. The data DATA is related with at least one between the DC characteristic and the AC timing characteristic of a parameter to be changed.

Parameters that can be changed according to a data set may be voltage levels and/or current levels for indicating the DC and operating characteristics defined in the specification of the semiconductor device30. For instance, a parameter that can be changed according to a data set output from the controller20may be a wordline voltage, a program voltage, an erase voltage, a read voltage, a reference cell voltage, a program current, an erase current, a read current, and/or a reference cell current, among others, of the semiconductor device30. Some embodiments provide that the parameters that can be changed according to the data set may be times, e.g., a development time T_RDEV (FIG. 12), an erase time T_RESET (FIG. 13), and/or a program time T_SET (FIG. 13), among others, indicating AC timing characteristics.

The semiconductor device30may receive the data set including the command CMD, the address ADD, and the data DATA, decode the command CMD, and store the data DATA in the register43indicated by the address ADD. The data DATA may be used for changing at least one between the DC characteristic and the AC timing characteristic of a parameter control signal. Accordingly, an access block may change at least one between the DC characteristic and the AC timing characteristic of a parameter according to the parameter control signal. In addition, some embodiments provide that the access block may access a memory core60(FIG. 2) according to a changed parameter.

The semiconductor device30may change at least one of the predetermined DC characteristic and the predetermined AC timing characteristic of the parameter according to the data DATA stored in the register43. For instance, the semiconductor device30may change at least one of the DC characteristics (e.g., a DC voltage level or a DC current level) and the AC timing characteristics (e.g., a time or a period) of the parameter control signal, which may be provided to the access block performing the program, write, read or erase operation, according to the received data DATA (FIG. 14, block6).

Consequently, the controller20may change parameters, which have been set by manufacturers of the controller20and the semiconductor30during manufacturing, during operation. Some embodiments provide that the controller may change any parameter at any time according to the use state of the semiconductor device30. As a result, when fail data occurs, the controller20and/or the semiconductor device30can recover the fail data according to the changed parameter. The controller20of the semiconductor system10may include an interface logic unit (not shown) to inform a user of the monitoring result. The user may input a parameter change signal through the interface logic unit.

Reference is made toFIG. 2, which is a block diagram of the semiconductor device30according to some embodiments of the present invention. The semiconductor device30includes a control/register block40, a control block50, an access block, and the memory core60. The control/register block40may access the memory core60under the control of a control logic unit41. The control/register block40may decode the command CMD output from the controller20and store the data DATA in a storage region of the register43indicated by the address ADD under the control of the control logic unit41. The control logic unit41of the control/register block40may control the operation of a state machine45. The control logic unit41may receive and decode a plurality of control signals /CS, /WE, /RE, and CMD output from the controller20and output decoded signals to at least one among the register43, the state machine45, the control block50, the access block, and/or the memory core60.

The plurality of control signals /CS, /WE, /RE, and CMD may include a chip selection signal /CS for enabling the semiconductor device30, a write enable signal /WE for instructing the start of a write operation, a read enable signal /RE for instructing the start of a read operation, and a data set including the command CMD and the data DATA according to some embodiments of the present invention. The control logic unit41may receive the command CMD of the data set and store the data DATA for changing at least one between the DC characteristic and the AC timing characteristic of a parameter in a region of the register43indicated by the address ADD according to a result of decoding the command CMD.

According to some embodiments of the present invention, the command CMD for instructing to change a parameter has a unique value and is distinguished from a command instructing an access operation (e.g., a program operation, a write operation, a read operation, or erase operation) of the semiconductor device30.

The state machine45may output control signals for controlling the access operation of the semiconductor device30to the control block50. For instance, in the read operation, the state machine45may output control signals necessary to perform bitline discharge, bitline precharge, development, sensing, and/or latch illustrated inFIG. 12to the control block50. The control block50may change at least one between the DC characteristic and the AC timing characteristic of a parameter control signal (e.g., WL, DIS/Vpp, REN/WEN, nPRG, LCH, Vref, Rcell, C_S/R, and/or WDE), which is provided to the access block to access a plurality of non-volatile memory cells included in the memory core60, according to the data DATA stored in the register43. Some embodiments provide that the control block50includes a voltage generation block51, a timing generation block53, and a level/timing adjustment block55.

In some embodiments, the voltage generation block51may generate a plurality of DC voltages Vout1through Voutn (where “n” is a natural number) respectively having different DC levels according to a first portion, e.g., first control bits, of the data DATA stored in the register43. The timing generation block53may generate a plurality of timing signals Tout_S1through Tout_Sm(where “m” is a natural number) respectively having different timings (e.g., times or periods) according to a second portion, e.g., second control bits, of the data DATA stored in the register43. The level/timing adjustment block55may receive the DC voltages Vout1through Voutn from the voltage generation block51and the timing signals Tout_S1through Tout_Smfrom the timing generation block53and mix the DC voltages Vout1through Voutn with the timing signals Tout_Smthrough Tout_Smin response to the control signals output from the state machine45, thereby generating at least one parameter control signal WL, DIS/Vpp, REN/WEN, nPRG, LCH, Vref, Rcell, C_S/R, and/or WDE.

Each parameter control signal WL, DIS/Vpp, REN/WEN, nPRG, LCH, Vref, Rcell, C_S/R, and/or WDE illustrated inFIG. 2may indicate a control signal for changing at least one of the DC characteristic and the AC timing characteristic of a parameter in some embodiments of the present invention. Some embodiments provide that each parameter control signal WL, DIS/Vpp, REN/WEN, nPRG, LCH, Vref, Rcell, C_S/R, and/or WDE illustrated inFIG. 2may indicate a parameter itself in some embodiments disclosed herein.

The structure and the operations of the control block50will be described in detail with reference toFIGS. 3 through 9. The access block is a block that may access the memory core60in the program, write, read and/or erase operation and may include a row decoder62, a column decoder64, a write/read buffer block66, an output buffer68, and/or an input buffer69, among others. In some embodiments of the present invention, when the access block includes a wordline driver block, e.g., the row decoder62, for driving a wordline connected to a plurality of non-volatile memory cells in the memory core60, the control block50may provide the parameter control signal WL for changing at least one between the DC characteristic (e.g., the DC level) and the AC timing characteristic (e.g., the time) of a parameter (e.g., a wordline driving voltage) to the wordline driver block.

In some embodiments, when the access block includes a program block, e.g., the write/read buffer block66, for programming data to non-volatile memory cells in the memory core60, the control block50may provide the parameter control signal (e.g., S/R inFIG. 13or C_S/R for controlling S/R) for changing at least one of the DC characteristic and the AC timing characteristic of a parameter (e.g., a program time T_SET, a program voltage VSET, or a program current I_SET inFIG. 13) to the program block in the program operation.

In some embodiments, when the access block includes a read block, e.g., the write/read buffer block66, for read data from non-volatile memory cells in the memory core60, the control block50may provide the parameter control signal REN and/or nPRG for changing at least one of the DC level and the AC timing characteristic of a parameter (e.g., a development time T_RDEV, a read voltage Vread, or a read current Iread inFIG. 12) to the read block in the read operation.

In some embodiments of the present invention, when the access block includes an erase block, e.g., the write/read buffer block66, for erasing non-volatile memory cells in the memory core60, the control block50may provide the parameter control signal (e.g., S/R inFIG. 13or C_S/R for controlling S/R) for changing at least one of the DC level and the AC timing characteristic of a parameter (e.g., an erase time T_RESET, an erase voltage VRESET, or an erase current I_RESET inFIG. 13) to the erase block in the erase operation.

In some embodiments, when the access block includes a reference memory cell (e.g., a transistor195inFIG. 10), the control block50may provide the reference memory cell with the parameter control signal Rcell for changing a reference cell voltage (Vref_cell inFIG. 12) or at least one of the DC level and the AC timing characteristic of the reference cell voltage (or a current flowing in the transistor195inFIG. 10due to the reference cell voltage Rcell).

The memory core60includes a plurality of wordlines, a plurality of bitlines, and a plurality of non-volatile memory cells. The non-volatile memory cells may be implemented by electrically erasable programmable read-only memory (EEPROM) cells, flash memory cells, resistive random access memory (ReRAM) cells, phase-change RAM (PRAM) cells, ferroelectric RAM (FeRAM) cells, and/or magnetoresistive RAM (MRAM) cells, among others.

Reference is now made toFIG. 3, which is a block diagram of the voltage generation block51illustrated inFIG. 2. The voltage generation block51includes a plurality of voltage generation circuits51-1through51-n. The first voltage generation circuit51-1may control the DC level of a first voltage Vout1in response to a control bit set CTL_L1corresponding to a portion of the data DATA stored in the register43and may output the first voltage Vout1to control the DC level thereof. The second voltage generation circuit51-2may control the DC level of a second voltage Vout2in response to a control bit set CTL_L2corresponding to another portion of the data DATA stored in the register43and may output the second voltage Vout2to control the DC level thereof. The n-th voltage generation circuit51-nmay control the DC level of an n-th voltage Voutn in response to a control bit set CTL_Lncorresponding to a further portion of the data DATA stored in the register43and may output the n-th voltage Voutn to control the DC level thereof. The voltages Vout1through Voutn may have different DC levels.

Reference is now made toFIG. 4, which is a circuit diagram of the first voltage generation circuit51-1illustrated inFIG. 3. For clarity of the description, the first voltage generation circuit51-1only is illustrated. The voltage generation circuits51-1through51-nreceive different control bit sets CTL_L1through CTL_Lnbut have substantially the same structure.

The first voltage generation circuit51-1includes a voltage regulator70, a comparator90, a controller91, and a voltage generator93. The voltage regulator70may regulate the level of the first voltage Vout1in response to the control bit set CTL_L1. The voltage regulator70may include a plurality of resistors71,73,75,77,79, and81connected in series between an output terminal N1and a ground Vss and a plurality of switching circuits83,85,87, and89.

The switching circuits83,85,87, and89are respectively connected in parallel with the resistors73,75,77, and79and perform a switching operation in response to control bits CTL_V1, CTL_V2, CTL_V3, and CTL_V4, respectively, composing the control bit set CTL_L1. Some embodiments provide that the voltage regulator70operates in response to the four control bits CTL_V1through CTL_V4inFIG. 4. The total resistance value of the resistors71through81connected in series between the output terminal N1and the ground Vss may vary with each of the control bits CTL_V1through CTL_V4.

The comparator90may compare a voltage at a node N2with a first reference voltage Vc1and output a comparison signal according to the comparison result. Some embodiments provide that the voltage at the second node N2is input to a negative (−) terminal of the comparator90and the first reference voltage Vc1is input to a positive (+) terminal of the comparator90, however, the terminations may be provided vice versa in some embodiments disclosed herein. The controller91may generate a plurality of control signals Φ and /Φ in response to the comparison signal. The control signals Φ and /Φ may be differential signals or complementary signals. In addition, the control signals Φ and /Φ may have a non-overlap portion. In some embodiments, the controller91may be implemented by an oscillator.

The voltage generator93may be enabled in response to an enable signal EN that is output from the state machine45and may generate the first voltage Vout1in response to the control signals Φ and /Φ. Some embodiments provide that the voltage generator93may be implemented by a charge pump. The first voltage generation circuit51-1may output the first voltage Vout1corresponding to a level that is controlled according to the control bits CTL_V1through CTL_V4.

Reference is now made toFIG. 5, which is a block diagram of the timing generation block53illustrated inFIG. 2. Some embodiments provide that the timing generation block53includes a plurality of timing generation circuits53-1through53-m. The first timing generation circuit53-1may generate a plurality of timing signals Tout_S1in response to a control bit set CTL_T1corresponding to a portion of the data DATA stored in the register43. The timing signals Tout_S1may have different timings, e.g., periods. The second timing generation circuit53-2may generate a plurality of timing signals Tout_S2in response to a control bit set CTL_T2corresponding to another portion of the data DATA stored in the register43. The timing signals Tout_S2may have different timings, e.g., periods. The m-th timing generation circuit53-mmay generate a plurality of timing signals Tout_Smin response to a control bit set CTL_Tm, corresponding to a further portion of the data DATA stored in the register43. The timing signals Tout_Smmay have different timings, e.g., periods. Accordingly, all timing signals Tout_S1through Tout_Smgenerated by the timing generation block53may have different periods. Some other embodiments provide that each of the timing generation circuits53-1through53-mmay generate a single timing signal.

Reference is now made toFIG. 6, which is a circuit diagram of the first timing generation circuit53-1illustrated inFIG. 5. For clarity of the description, the first timing generation circuit53-1only is illustrated. The timing generation circuits53-1through53-mmay receive different control bit sets CTL_T1through CTL_Tmbut may have substantially the same structure.

In some embodiments, the first timing generation circuit53-1includes an oscillation block100and one or more timing generators151,153, and155. The oscillation block100may generate a period-controlled oscillation signal OSC1in response to the control bit set CTL_T1. Each of the timing generators151,153, and155may generate one or more timing signals Tout_S1having different periods in response to a control signal CTL1, CTL2, or CTLp (where “p” is an integer), respectively, output from the state machine45.

For instance, the first timing generator151may generate a plurality of timing signals Tout_A1through Tout_Ak(where “k” is a natural number) having different periods in response to the oscillation signal OSC1and at least one control signal CTL1output from the state machine45. The second timing generator153may generate a plurality of timing signals Tout_B1through Tout_Bkhaving different periods in response to the oscillation signal OSC1and at least one control signal CTL2output from the state machine45. The p-th timing generator155may generate a plurality of timing signals Tout_C1through Tout_Ckhaving different periods in response to the oscillation signal OSC1and at least one control signal CTLp output from the state machine45. Some embodiments provide that ones of and/or each of the timing generators151,153, and155may generate a single timing signal.

Reference is now made toFIG. 7, which is a circuit diagram of the oscillation block100illustrated inFIG. 6. In some embodiments, the oscillation block100includes a bias voltage generator110and a ring oscillator140. The bias voltage generator110may include a switch111, a plurality of resistors113,115,117,119,121, and123, a plurality of switches125,127,129, and131, and a comparator133. Some embodiments provide that the resistors113through123and the switches125through131may form a voltage regulator.

The switch111may be connected between a power supply Vdd and an output terminal N3and perform a switching operation in response to an output signal of the comparator133. The switch111may be implemented by a metal-oxide semiconductor field effect transistor (MOSFET), among others. The resistors113through123may be connected in series between the output terminal N3and the ground Vss. The switches125through131may be connected in parallel with the resistors115through123, respectively, and perform a switching operation in response to control bits TCTL_V1through TCTL_V4, respectively, composing the control bit set CTL_T1.

The comparator133may compare a second reference voltage Vc2with a voltage at a node N4and generate a comparison signal for controlling the switching operation of the switch111according to the comparison result.

The bias voltage generator110may generate a level-controlled bias voltage Vbias in response to the second reference voltage Vc2and the control bits TCTL_V1through TCTL_V4. The ring oscillator140may include a plurality of stage cells141-1through141-3connected in a ring shape. Each of the stage cells141-1through141-3may include an inverter and a bias circuit. The period of the oscillation signal OSC1may be controlled by the level of the bias voltage Vbias applied to the bias circuit. Examples of the oscillation signal OSC1that can be generated are shown inFIG. 6.

Some embodiments provide that the last stage cell141-3outputs the oscillation signal OSC1inFIG. 7. In some embodiments, an output signal of any one of the stage cells141-1through141-3may be used as the oscillation signal OSC1.

Reference is now made toFIG. 8, which is a block diagram of the level/timing adjustment block55illustrated inFIG. 2. In some embodiments, the level/timing adjustment block55includes a wiring circuit160and a plurality of level/timing adjusters161through164. The wiring circuit160may provide the voltages Vout1through Voutn generated by the voltage generation block51and the timing signals Tout_S1through Tout_Smgenerated by the timing generation block53to the level/timing adjusters161through164. For instance, the wiring circuit160may control such that the level/timing adjusters161through164are provided with different or the same numbers of voltages Vout1through Voutn and timing signals Tout_S1through Tout_Sm. In other words, the numbers of voltages Vout1through Voutn and the timing signals Tout_S1through Tout_Smused by the first level/timing adjuster161may be different those used by the second, third, or fourth level/timing adjusters162,163, or164.

Reference is now made toFIG. 9, which is a block diagram of the first level/timing adjuster161illustrated inFIG. 8. For clarity of the description, the first level/timing adjuster161only is illustrated inFIG. 9. The level/timing adjusters161through164may have substantially the same structures and the numbers of voltages Vout1through Voutn and timing signals Tout_S1through Tout_S1, input to each of the level/timing adjusters161through164may be the same and/or different among the level/timing adjusters161through164.

In some embodiments, the first level/timing adjuster161includes a first selection circuit170, a second selection circuit172, and a buffer174. The first selection circuit170may output one of the timing signals Tout_S1through Tout_Smin response to at least one first selection signal SEL1. Some embodiments provide that the first selection circuit170may be implemented by a multiplexer (MUX). The second selection circuit172may output one of the voltages Vout1through Voutn in response to at least one second selection signal SEL2. In some embodiments, the second selection circuit172may implemented by a MUX. The at least one first selection signal SEL1and the at least one second selection signal SEL2may be output from the state machine45.

A timing signal (CTM) selected by the first selection circuit170may be applied to a gate of the buffer174and a voltage selected by the second selection circuit172may be applied to an operating voltage supply line CVL of the buffer174. The buffer174may be implemented by an inverter. As a result, the first level/timing adjuster161may generate the parameter control signal WL for adjusting at least one between the DC level and the AC timing of a parameter. In other words, each of the level/timing adjusters161through164may generate the parameter control signal WL, DIS, REN, nPRG, LCH, Vref, Rcell, C_S/R, and/or WDE for controlling at least one between the DC level and the AC timing of a different parameter.

Reference is now made toFIG. 10, which is a circuit diagram of the write/read buffer block66illustrated inFIG. 2. For clarity of the description,FIG. 10illustrates a unit write/read buffer connected to a single bitline BL. Some embodiments, however, provide that the write/read buffer block66may include a plurality of unit write/read buffers connected to a plurality of bitlines, respectively.

The parameter control signals DIS/Vpp, REN, nPRG, LCH, Vref, Rcell, C_S/R, and WDE generated by the level/timing adjustment block55may be applied to the unit write/read buffer, which performs the program, write, read and/or erase operation.

The unit write/read buffer may include a write buffer180, a read buffer190, and a data input/output (I/O) circuit200. In response to each of the parameter control signals Vpp, S/R, WEN, and WDE, illustrated inFIG. 2,10, or13, in the program, write and/or erase operation, the write buffer180may change and/or adjust the DC level and the AC timing (e.g., an erase time T_RESET or a program time T_SET) of a parameter (e.g., an erase voltage VRESET, an erase current I_RESET, a program voltage VSET, and/or a program current I_SET) used in the program, write, and/or erase operation.

In response to each of the parameter control signals DIS, REN, nPRG, LCH, Vref, and Rcell, illustrated inFIGS. 2,10, and/or12, in the read operation, the read buffer190may change the DC level and the AC timing (e.g., a development time T_RDEV) of a parameter (e.g., a read voltage Vread or a read current Iread) used in the read operation.

The data I/O circuit200may latch I/O data Din/Dout in each operation. Some embodiments provide that the write buffer180includes a MOSFET181, which may control the DC level of a parameter (e.g., the program or write current I_SET) in response to a parameter control signal (e.g., the reset/reset signal S/R) generated by a plurality of transistors in response to the parameter control signal C_S/R. Some embodiments provide that the write buffer180includes a MOSFET183, which is turned on or off in response to a data signal A output from a latch circuit210, and a MOSFET185, which provides data corresponding to the data signal A to the bitline BL in response to a parameter control signal (e.g., the write enable signal WEN.) The program or write voltage VSET may be directly applied to one end of the MOSFET185. A circuit for generating the parameter control signal, (e.g., the set/reset signal S/R) may be implemented within the level/timing adjustment block55.

In some embodiments, the read buffer190includes a plurality of transistors191,193,195, and197and a sense amplifier (S/A)199. The precharge transistor191may be turned on or off in response to a parameter control signal (e.g., the bitline precharge signal nPRG.) The precharge transistor191may be turned on or off in response to the bitline precharge signal nPRG, whose DC level and/or AC timing has been adjusted.

The discharge transistor193may be turned on or off in response to a parameter control signal (e.g., the discharge signal DIS) or may be turned on or off in response to the discharge signal DIS whose DC level and/or AC timing has been adjusted.

The reference transistor195may be turned on or off in response to a parameter control signal (e.g., the reference read voltage signal Rcell) or may be turned on or off in response to the reference read voltage signal Rcell, whose DC level and/or AC timing has been adjusted. The reference transistor195may generate a reference read current in response to the reference read voltage signal Rcell.

The read enable transistor197may be turned on or off in response to a parameter control signal (e.g., the read enable signal REN) or may be turned on or off in response to the read enable signal REN, whose DC level and/or AC timing has been adjusted. In the read operation, the S/A199may compare a reference signal Vref with a signal (e.g., the read voltage Vread) of the bitline BL input through the read enable transistor197and transmit a read data signal B to the data I/O circuit200. At least one of the DC level and the AC timing of the reference signal Vref may have been changed or adjusted by the level/timing adjustment block55. Also, at least one of the DC level and the AC timing of a high voltage Vpp applied to a source of the transistor181of the write buffer180may have been changed or adjusted by the level/timing adjustment block55.

The data I/O circuit200may latch the data signal B output from the S/A199in response to a parameter control signal (e.g., the latch enable signal LCH) and output the latched data signal B as the output data Dout. In the program, write and/or erase operation, the data I/O circuit200may transmit the input data Din as a write data signal to the bitline BL through the transistors183and185in response to a parameter control signal, e.g., the write data enable signal WDE.

Reference is now made toFIG. 11, which is a circuit diagram of the latch circuit210illustrated inFIG. 10. Some embodiments provide that the latch circuit210includes a plurality of switching transistors and a plurality of inverters. In the program, write and/or erase operation, the latch circuit210may write a data signal DI input through an input transistor to a memory cell through the bitline BL in response to the write data enable signal WDE. In the read operation, the latch circuit210may output the data signal B from the S/A199as the output data Dout in response to the latch signal LCH.

Reference is now made toFIG. 12, which is a timing chart of the read operation of the semiconductor device30illustrated inFIG. 2. Referring toFIGS. 1 through 12, when at least one of the DC level and the AC timing of each of the parameter control signals DIS, REN, nPRG, WL, LCH, Vref, and Rcell related with the read operation is changed, a phase, e.g., a bitline discharge time, a bitline precharge time, a development time, a sensing time, and/or a latch time, may be changed.

Referring toFIG. 12, the semiconductor device30may control the development time T_RDEV by adjusting the timing of the parameter control signal nPRG. The semiconductor device30may also control the read voltage Vread or the read current Iread generated by the transistor197by adjusting the DC level of the parameter control signal REN. In addition, the semiconductor device30may control a reference read current generated by the reference transistor195by adjusting the DC level of the parameter control signal Rcell.

Reference is now made toFIG. 13, which is a timing chart of the write operation of the semiconductor device30illustrated inFIG. 2. Referring toFIGS. 1 through 11andFIG. 13, when at least one between the DC level and the AC timing of each of the parameter control signals REN, WL, S/R, WDE, and WEN related with the program, write, and erase operations is changed, a phase, e.g., a latch/reset time, an erase time, a data loading time, a program time, and/or a recovery time, may be changed.

For instance, the semiconductor device30may control the erase voltage VRESET or the erase current I_RESET by adjusting the DC level of the parameter control signal S/R in the erase operation. The semiconductor device30may also control the program voltage VSET or the program current I_SET by adjusting the DC level of the parameter control signal S/R in the program operation.

FIG. 15is a flowchart of the operations of the semiconductor system10according to some embodiments of the present invention. Referring toFIGS. 1 through 13andFIG. 15, the controller20monitors a current endurance Ep of the semiconductor device30(block11). The controller20compares the current endurance Ep with a first reference endurance Eref1(block13). When the current endurance Ep does not exceed the first reference endurance Eref1, the operations end.

However, when the current endurance Ep exceeds the first reference endurance Eref1, the controller20generates a first data set CMD_1for changing at least one between the DC characteristic and the AC timing characteristic of a particular parameter to be changed, as described with reference toFIGS. 1 through 12, and transmits the first data set CMD_1to the semiconductor device30(block15).

The semiconductor device30generates a parameter control signal for changing at least one of the DC level of the particular parameter (or a DC parameter) and the AC timing of the particular parameter (or an AC parameter) according to a command and data included in the first data set CMD_1and performs an access operation according to the DC level and/or the AC timing changed in response to the parameter control signal (block17).

After the parameter of the semiconductor device30is changed according to the first data set CMD_1, the controller20monitors the current endurance Ep of the semiconductor device30(block19). The controller20compares the current endurance Ep with a second reference endurance Eref2(block21). The operations end when the current endurance Ep does not exceed the second reference endurance Eref2. However, when the current endurance Ep exceeds the second reference endurance Eref2, the controller20generates a second data set CMD_2for changing at least one between the DC characteristic and the AC timing characteristic of the particular parameter, as described with reference toFIGS. 1 through 12, and transmits the second data set CMD_2to the semiconductor device30(block23).

The semiconductor device30generates a parameter control signal for changing at least one between the DC level of the particular parameter (or the DC parameter) and the AC timing of the particular parameter (or the AC parameter) according to a command and data included in the second data set CMD_2and performs an access operation according to the DC level and/or the AC timing newly changed in response to the parameter control signal (block25).

The semiconductor system10may repeatedly perform operations corresponding to blocks19-25as illustrated inFIG. 15while increasing a reference endurance. Accordingly, the semiconductor system10may repeatedly change at least one of the DC characteristic and the AC timing characteristic of the particular parameter.

Reference is now made toFIG. 16, which is a flowchart of the operations of the semiconductor system10according to some embodiments of the present invention. Referring toFIGS. 1 through 12andFIG. 16, the controller20monitors a current endurance Ep of the semiconductor device30(block31). The controller20compares the current endurance Ep with a reference endurance Eref (block33). When the current endurance Ep does not exceeds the reference endurance Eref, the operations end.

However, when the current endurance Ep exceeds the reference endurance Eref, the controller20performs a verify read operation on non-volatile memory cells included in the memory core60at least one time (block35). The controller20checks whether a distribution Mp of the non-volatile memory cells subjected to the verify read operation is within a range of a marginal distribution Mtor defined in the specification of the semiconductor device30based on the result of the verify read operation (block37).

When the distribution Mp is less than the marginal distribution Mtor, the controller20finishes the operation. However, when the distribution Mp is greater than the marginal distribution Mtor, the controller20generates a data set for changing at least one between the DC characteristic and the AC timing characteristic of a particular parameter to be changed, as described with reference toFIGS. 1 through 12, and transmits the data set to the semiconductor device30(block39).

Thereafter, the semiconductor device30stores data set in the register43indicated by an address according to a command included in the data set and changes at least one between the DC characteristic of the particular parameter (i.e., the DC parameter) and the AC timing characteristic of the particular parameter (i.e., the AC parameter) according to the data set stored in the register43(block41).

According to some embodiments of the present invention, the controller20may generate at least one data set for changing at least one parameter (e.g., a program time, an erase time, a read time, a program voltage, an erase voltage, a read voltage, a reference cell voltage, a program current, an erase current, a read current, and/or a reference cell current) affecting endurance and/or retention and transmit the data set to the semiconductor device30. Accordingly, when fail data occurs during operation, the controller20recovers the fail data using at least one changed parameter and controls at least one parameter or at least one changed parameter according to the endurance and/or the retention, thereby increasing the reliability of the semiconductor device30.

According to some embodiments of the present invention, the semiconductor device30may change at least one of the DC characteristic (e.g., the program voltage, the erase voltage, the read voltage, the reference cell voltage, the program current, the erase current, the read current, and/or the reference cell current) and the AC timing characteristic (e.g., the program time, the erase time, and/or the read time) of a parameter requested to be changed by the controller20according to a data set output from the controller20.

In the above-described embodiments of the present invention, changing a parameter may not mean to change the parameter itself but may mean to change the DC characteristic and/or the AC timing characteristic of the parameter. In addition, changing the parameter may mean to change the DC characteristic and/or the AC timing characteristic of a parameter control signal.

As described above, according to some embodiments of the present invention, a semiconductor device can change the DC characteristic and/or the AC timing characteristic of a parameter according to externally input data. Accordingly, when fail data occurs, the semiconductor device can recover the fail data according to the externally input data, thereby increasing data reliability.