An integrated circuit (IC) system includes a substrate, a first doped well of a first polarity in the substrate, a first electrode in contact with the doped well, a buried oxide (BOX) in contact with the doped well in the substrate, a first IC device including a second electrode formed on the BOX, and fuse control circuitry coupled to the first electrode and the second electrode. The fuse control circuitry is configured to cause voltages to be applied to the first and second electrodes to change a resistance level of the BOX in the vicinity of the second electrode.

BACKGROUND

Field

This disclosure relates generally to antifuses, and more specifically, to antifuses integrated on SOI substrates.

Related Art

Antifuses are fuses that are blown to create a low resistance state and are commonly used in many integrated circuit applications as one-time programmable non-volatile storage. However, antifuses are large devices which take up valuable real estate in circuits. Therefore, a need exists for antifuses which take up less circuit real estate.

DETAILED DESCRIPTION

Fully depleted semiconductor-on-insulator (FDSOI) substrates include a carrier substrate with a buried oxide (BOX) layer over the carrier substrate. Over the BOX layer is a thin silicon layer in which active circuitry is formed. In one embodiment, the BOX layer itself is used as the dielectric of an antifuse. In this embodiment, part of the silicon layer on top of the BOX layer is used as a first electrode of an antifuse and wells in the carrier substrate under the BOX layer are used as a second electrode of the antifuse. The first electrode may correspond to active circuitry within the silicon layer, such as a source/drain electrode of a metal-oxide-semiconductor field-effect transistor (MOSFET) on top of the BOX layer or an electrode of a capacitor or diode formed on top of the BOX layer. Depending on the thickness of the BOX layer, a minimum programming voltage is needed across the antifuse dielectric (the BOX layer) in order to break down the dielectric and program it to a low resistance state. Currently, with BOX thickness being about 150-250 Angstroms, higher programming voltages are needed to blow the antifuse than achievable with conventional complementary metal-on-semiconductor (CMOS) devices, therefore, high voltage devices, such as laterally diffused MOSFET (LDMOS) devices, can be used as programming devices for the antifuses.

FIG. 1illustrates in partial cross-sectional form and partial block diagram form, an integrated circuit (IC)10having antifuses64,66,68, and70, fuse control circuitry80, and programming devices82, in accordance with one embodiment of the present invention. Note that IC10may also be referred to as an IC system. IC10includes a carrier substrate12, which, when part of a wafer, may be referred to as a carrier wafer. In a first portion11of IC10, a BOX layer14is located on carrier substrate12, and a thin active silicon layer46is located on BOX layer14. IC devices36,38,40, and42are formed in active silicon layer46and are located on BOX layer14. In a second portion13of IC10, a bank82of high voltage programming devices is formed on and in carrier substrate12. In second portion13, BOX layer14is removed prior to formation of bank82such that the programming devices are formed directly on and in substrate12.

A P-well region16and an N-well region18are formed in substrate12in first portion11. Isolation regions20,22,24,26,28,30, and32extend from BOX layer14into substrate12in P-well16or N-well18. A P+ contact region34is formed on P-well16on and in substrate12between isolation regions20and22and provides an electrical contact to P-well16. In between isolation regions20and22, BOX layer14is removed such that BOX layer14is not present between contact region34and P-well16. Similarly, an N+ contact region44is formed on N-well18on and in substrate12between isolation regions30and32and provides an electrical contact to N-well18. In between isolation regions30and32, BOX layer14is removed such that BOX layer14is not present between contact region44and N-well18. Each of contact regions34and44are formed on and in substrate12. Note that isolation regions20,22,24,26,28,30, and32extend into substrate12but do not extend through the bottoms of P-well16and N-well18.

Device36is formed directly on BOX layer14, over P-well16and between isolation regions22and24. Device36is a MOSFET device having source/drain electrodes labeled “P+”, such as highly doped P+ source/drain electrode50, and a channel region located between the source/drain electrodes. Each of the source/drain electrodes and channel region is formed from thin active silicon layer46. Note that the channel region has an opposite polarity to the source/drain electrodes. Device36includes a gate dielectric48over the channel region and over portions of the source/drain electrodes, and a gate electrode47over gate dielectric48. Further details of device36are not illustrated inFIG. 1, such as sidewall spacers, liners, raised source/drains, etc. These elements are known elements and known variations, and in alternate embodiments, device36may include more elements than those illustrated inFIG. 1. Also, thinner or thicker gate dielectrics may be used, or a gate dielectric including various different materials may be used. In one example, device36may correspond to an input/output device and in another example, device36may correspond to a core device, in which the gate dielectric would be of an appropriate material and thickness for each type of device.

Device38is a capacitor formed directly on BOX layer14, over P-well16and between isolation regions24and26. Device38is a capacitor having a bottom electrode56directly on BOX layer14, a capacitor dielectric54on bottom electrode56, and a top electrode52on capacitor dielectric54. In one embodiment, capacitor38can be used as an antifuse in which a high voltage can be placed across the top and bottom electrodes to break down capacitor dielectric54to program the antifuse to a low resistance state.

Device40is formed directly on BOX layer14, over N-well18and between isolation regions26and28. Device40is a MOSFET device having source/drain electrodes labeled “N+”, such as highly doped N+ source/drain electrode62, and a channel region located between the source/drain electrodes. Each of the source/drain electrodes and channel region is formed from thin active silicon layer46. Note that the channel region has an opposite polarity to the source/drain electrodes. Device40includes a gate dielectric60over the channel region and over portions of the source/drain electrodes, and a gate electrode58over gate dielectric60. Further details of device40are not illustrated inFIG. 1, such as sidewall spacers, liners, raised source/drains, etc. These elements are known elements and known variations, and in alternate embodiments, device40may include more elements than those illustrated inFIG. 1. Also, thinner or thicker gate dielectrics may be used, or a gate dielectric including various different materials may be used. In one example, device40may correspond to an input/output device and in another example, device40may correspond to a core device, in which the gate dielectric would be of an appropriate material and thickness for each type of device. Note that in the illustrated embodiment, gate dielectric60of device40is thinner than gate dielectric48of device36.

Device42is a highly doped N+ region formed from thin active layer46and is formed directly on BOX layer14, over N-well18, and between isolation regions28and30. In one embodiment, device42is a stand-alone N+ region. In an alternate embodiment, device42is a diode device in which a highly doped P+ region, also formed from thin active layer46, would be formed immediately adjacent the highly doped N+ region, such as behind the highly doped N+ region and thus not visible in the cross section ofFIG. 1. Note that the highly doped N+ region may also be referred to as an electrode.

As illustrated inFIG. 1, under each of electrode50of device36, electrode56of device38, electrode62of device40, and electrode42of device42, BOX layer14forms an antifuse64,66,68, and70, respectively. That is, each antifuse is formed from BOX layer14in the vicinity of a corresponding electrode of a corresponding device. Prior to programming these antifuses, BOX layer14provides a high resistive state between the corresponding electrode of the corresponding device and underlying well, P-well16or N-well18. Each antifuse can be programmed by applying a high voltage between the corresponding electrode on top of BOX layer14and the underlying P-well or N-well so as to change the resistance level of BOX layer14in the vicinity of the corresponding electrode to a low resistance state. When programmed, an antifuse provides a low resistance path from P-well16or N-well18to the corresponding electrode.

Note that each antifuse inFIG. 1is formed with a top electrode located directly on top of BOX layer14, a portion of BOX layer14as the antifuse dielectric, and a bottom electrode formed by the P or N well underlying BOX layer14. The top electrode may be formed from a corresponding electrode of an active or passive device formed with thin active silicon layer46directly on BOX layer14. In this manner, an electrode of a device formed on BOX layer14can be utilized as both an electrode of the device itself as well as a top electrode of an antifuse. For example, electrode50may be used as both a source/drain electrode of device36and the top electrode for antifuse64. In the case of a programmed (blown) antifuse, though, the voltage of the electrode of the device would be the same as the underlying P-well or N-well (the bottom electrode for the antifuse). This may limit how the device is used. For example, if antifuse64is programmed (or blown), the voltage of electrode50would be about the same as P-well16. Therefore, flexibility is reduced on how to set electrode50of device36. That is, if P-well16is grounded, then electrode50would also be set to ground. The use of an electrode of a device on top of BOX layer14as a top electrode of a BOX layer antifuse saves area but may reduce the flexibility of that device.

In the examples ofFIG. 1, antifuses are formed in BOX layer14under devices36,38,40, and42. By vertically integrating these antifuses with circuitry formed on BOX layer14, area savings can be achieved. Also, in one example, electrode56is used as a top electrode of antifuse66with P-well16being the bottom electrode. Note that in this case, if dielectric54of device38is also used as an antifuse, two antifuses are vertically stacked on each other, which saves area. Furthermore, each antifuse formed from BOX layer14is locally formed under its corresponding top electrode. In this manner, any number of antifuses can be formed in BOX layer14.

Fuse control circuitry80can apply appropriate voltages to the electrodes of each antifuse for programming. Due to the thickness of BOX layer14, a higher voltage may be required to change the resistance state of BOX layer14than can be applied by conventional CMOS devices. In this case, a bank of high voltage programming devices82may be located in portion13of IC10, on substrate12. In the illustrated embodiment, bank82includes high voltage device (HV dev)72which is connected to electrode50of device36and of antifuse64, HV dev74which is connected to electrode56of device38and of antifuse66, HV dev76which is connected to electrode62of device40and of antifuse68, and HV dev78which is connected to electrode42of antifuse70.

Fuse control circuitry80directs programming of one of antifuses64,66,68, or70by directing the corresponding HV dev to apply a high program voltage (i.e. write voltage) to the corresponding electrode while applying a well voltage to the corresponding well contact34or44. For example, to program antifuse64, fuse control circuitry may apply 0V to contact34(and thus P-well16, which is the bottom electrode of antifuse64) and directs HV device72to apply a high enough voltage to electrode50(the top electrode of antifuse64) such that the resistance of Box layer14under electrode50changes to a low resistance state. In one embodiment, fuse control circuitry80can direct a HV device to apply a programming voltage with a signal indicating that a programming voltage be applied to the corresponding electrode of an IC device. In one embodiment, this signal may also indicate the value of the programming voltage to be applied to the corresponding electrode of the IC device. Programmed data can be programmed into the antifuses by choosing to program or not program each antifuse to place each antifuse into a low or high resistance state, respectively. A high resistance state may correspond to a logic level high and a low resistance state to a logic level low, or vice versa.

In one embodiment, the HV devices in bank82are LDMOS devices which are formed directly on and in substrate12. In this case, BOX layer14is removed from portion13of substrate12to form the HV devices. Alternate embodiments may use different HV devices. However, as the thickness of BOX layer14becomes thinner as technology evolves, it may be possible to use other devices to apply the programming voltages, such as conventional CMOS devices or other non-high voltage devices.

Fuse control circuitry80also includes circuitry to read the state (i.e. the programmed data) of the antifuses. In one embodiment, fuse control circuitry80can apply read voltages, as needed, to the electrodes of each antifuse to determine a resistance state of the antifuse. For example, to read antifuse64, fuse control circuitry80may apply a voltage to electrode50and sense the resulting current from electrode50to contact34to determine if BOX layer14has a high or low resistance state, in which one resistance state corresponds to a logic level high and the other to a logic level low. Note that during a read of an antifuse, the antifuse is decoupled from its corresponding HV programming device.

In one embodiment, each electrode used as a top electrode of an antifuse has the same conductivity type (i.e. the same polarity) as the well which provides the bottom electrode of the antifuse. For example, electrodes50and56are both P-type, as is P-well16, and similarly, electrodes62and42are both N-type as is N-well18.

Therefore, by now it can be appreciated how a BOX layer can be used to vertically integrate antifuses, which results in area savings of an IC. The top electrode of an antifuse is located on the BOX layer with the bottom electrode of the antifuse being the underlying well region (or back gate). The resistance state of the BOX layer located under the top electrode of the antifuse can be changed by applying an appropriate programming voltage. Furthermore, this top electrode of the antifuse may also be an electrode of an active device which is formed on the BOX layer, such as a source/drain electrode of a MOSFET, electrode of a capacitor, or electrode of a diode. The dual use of the top electrode for an IC device and an antifuse allows for the vertical integration of an IC device directly over an antifuse.

Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans will appreciate that conductivity types and polarities of potentials may be reversed.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, different active devices on BOX layer14may be used to provide a top electrode for an antifuse which uses BOX layer14as the antifuse dielectric. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

In one embodiment, an integrated circuit (IC) system includes a substrate; a first doped well of a first polarity in the substrate; a first electrode in contact with the doped well; a buried oxide (BOX) in contact with the doped well in the substrate; a first IC device including a second electrode formed on the BOX; fuse control circuitry coupled to the first electrode and the second electrode, the fuse control circuitry is configured to cause voltages to be applied to the first and second electrodes to change a resistance level of the BOX in the vicinity of the second electrode. In one aspect, the first IC device is a capacitor further including a third electrode above the second electrode; a layer of oxide between the second electrode and the third electrode. In another aspect, the first IC device is a transistor further including a layer of conductive material on the BOX adjacent the second electrode, wherein the layer of conductive material has a different polarity than the second electrode; a third electrode on the BOX adjacent the layer of conductive material, wherein the second and third electrodes have the same polarity; a layer of gate oxide over the layer of conductive material; and a gate electrode over the layer of gate oxide. In yet another aspect, the IC system further includes a high voltage device formed directly on the substrate, the high voltage device being coupled to receive a signal indicating a voltage to be applied to the first IC device from the fuse control circuitry, and to provide a voltage signal to the first IC device. In a further aspect, the high voltage device is a laterally diffused metal oxide semiconductor (LDMOS) transistor. In another aspect of this embodiment, the voltages applied to the first and second electrodes create a low resistance path by causing the BOX to breakdown in the vicinity of the second electrode. In yet another aspect of this embodiment, the voltages are applied to the first and second electrodes to write a data value by changing the resistance level, and different voltages are applied to the first and second electrodes to read the resistance level. In a further aspect, the IC system further includes a connection between the gate electrode and a voltage source and between the third electrode and another component. In another further aspect, the IC system further includes a connection between the third electrode and another component.

In another embodiment, a method of programming data in a one-time programmable integrated circuit component, includes applying a first voltage to a first electrode contacting a doped well in a semiconductor substrate; and applying a write voltage to a second electrode on a buried oxide (BOX) layer, wherein the BOX layer overlies the doped well, the second electrode is part of an active IC component formed on the BOX layer, the write voltage changes a resistance level of the BOX layer under the second electrode to program the data; and the first and second electrodes and the doped well have a first polarity. In one aspect, the method further includes applying a read voltage to the second electrode to read the data programmed in the one-time programmable circuit component. In a further aspect, the method further includes applying the write voltage using a high-voltage device coupled to the second electrode. In yet a further aspect, the method further includes providing a signal to the high-voltage device to control the applying the write voltage. In yet an even further aspect, the method further includes operating the active IC component to perform a different circuit function than the one-time programmable IC component. In yet a further aspect, the active IC component is one of a transistor, a capacitor, or a diode.

In yet another embodiment, an integrated circuit system includes a semiconductor substrate; a buried oxide (BOX) layer over a portion of the substrate; a first doped well having a first polarity in the semiconductor substrate under the BOX layer; a second doped well having a second polarity opposite the first polarity in the semiconductor substrate under the BOX layer; a first electrode of the first polarity on the substrate and in direct contact with the first doped well; a second electrode of the second polarity on the substrate and in direct contact with the second doped well; a first active IC device including a third electrode of the first polarity over the BOX layer and the first doped well; a second active IC device including a fourth electrode of the second polarity over the BOX layer and the second doped well; a first voltage source coupled to the first electrode; a second voltage source coupled to the second electrode; a third voltage source coupled to the third electrode; a fourth voltage source coupled to the fourth electrode; control circuitry coupled to the third and fourth electrodes and configured to read a resistance level of the BOX layer between the third and fourth electrodes and the first and second doped wells. In one aspect of this yet another embodiment, the first active IC device is a transistor that includes a layer of conductive material on the BOX layer adjacent the third electrode, wherein the layer of conductive material has the second polarity; a fifth electrode on the BOX layer adjacent the layer of conductive material, wherein the fifth electrode has the first polarity; a layer of gate oxide over the layer of conductive material; and a gate electrode over the layer of gate oxide. In another aspect, the first active IC device is a capacitor that includes a fifth electrode of the first polarity above the third electrode; a layer of oxide between the third electrode and the fifth electrode. In another aspect, the IC system further includes a first high voltage device formed directly on the substrate, the first high voltage device being coupled to receive a signal indicating a voltage to be applied to the third electrode from the control circuitry, and to provide the third voltage source; and a second high voltage device formed directly on the substrate, the second high voltage device being coupled to receive a signal indicating a voltage to be applied to the fourth electrode from the fuse control circuitry, and to provide the fourth voltage source. In another aspect, the second active IC device is a transistor that includes a second layer of conductive material on the BOX layer adjacent the fourth electrode, wherein the second layer of conductive material has the first polarity; a sixth electrode on the BOX layer adjacent the second layer of conductive material, wherein the sixth electrode has the second polarity; a second layer of gate oxide over the second layer of conductive material; and a second gate electrode over the second layer of gate oxide.