INTEGRATED CIRCUITS HAVING SMOOTH METAL GATES AND METHODS FOR FABRICATING SAME

Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.

TECHNICAL FIELD

The technical field generally relates to integrated circuits and methods for fabricating integrated circuits, and more particularly relates to integrated circuits with metal gates and methods for fabricating such integrated circuits.

BACKGROUND

As the critical dimensions of integrated circuits continue to shrink, the fabrication of gate electrodes for both planar and non-planar complementary metal-oxide-semiconductor (CMOS) transistors has advanced to replace silicon dioxide and polysilicon with high-k dielectric material and metal. A replacement metal gate process is often used to form the gate electrode. A typical replacement metal gate process begins by forming a sacrificial gate oxide material and a sacrificial gate between a pair of spacers on a semiconductor substrate. After further processing steps, such as an annealing process, the sacrificial gate oxide material and sacrificial gate are removed and the resulting trench is filled with a high-k dielectric and one or more metal layers. The metal layers can include workfunction metals as well as gate metals.

Processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating (EP), and electroless plating (EL) may be used to deposit the one or more metal layers that form the metal gate electrode. Conventionally, such metal layers are planarized to uniform heights during the fabrication process. Under conventional processing, the metal layers are often formed with non-uniform, rough upper surfaces that increase resistance and harm device performance.

Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits having improved metal gates. Also, it is desirable to provide methods for fabricating integrated circuits with metal gates that avoid the formation of non-uniform and rough upper surfaces on the metal gates. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.

In accordance with another embodiment, a method for fabricating an integrated circuit includes forming trenches in a dielectric layer. The method deposits a liner overlying the dielectric layer. The method further includes filling the trenches with tungsten. A non-mechanical etching process is performed to remove tungsten outside of the trenches.

In another embodiment, an integrated circuit is provided. The integrated circuit includes a semiconductor substrate and a metal gate structure overlying the semiconductor substrate. The metal gate structure includes a gate liner and a tungsten gate electrode overlying the gate liner. The tungsten gate electrode has an upper surface with a root mean squared surface roughness of less than about 0.5 nanometers (nm).

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments of the integrated circuits or the methods for fabricating integrated circuits claimed herein. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description.

Integrated circuits having smooth metal gates and methods for fabricating such integrated circuits as described herein avoid issues faced in conventional processes. For example, the integrated circuits and methods for fabricating integrated circuits described herein provide metal gates with smooth upper surfaces. Exemplary metal gates have upper surfaces with a root mean squared surface roughness of less than about 0.5 nm. As a result of the reduced surface roughness, device performance is improved. Specifically, increased surface roughness leads to increased contact resistance and hinders device performance. Increased surface roughness also leads to greater variation between contacts, leading to non-uniform and unpredictable performance. As described herein, metal gates are provided with smooth upper surfaces by reducing the amount of metal planarized during fabrication. Specifically, after the metal is deposited in the gate trench, the overburden portion of the metal is removed by a chemical, non-mechanical etch rather than by planarization. Conventional removal of the overburden of metal is performed by chemical mechanical planarization (CMP) and results in the lifting and removal of metal grains. Such grain removal causes surface roughness. The chemical, non-mechanical removal of the overburden portion described herein does not cause grain removal and results in a metal gate with a smoother surface. Further processing of the gate metal substantially retains the smooth surface achieved by the chemical, non-mechanical etch.

FIGS. 1-13illustrate steps in accordance with various embodiments of methods for fabricating integrated circuits. Various steps in the design and composition of integrated circuits are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Further, it is noted that integrated circuits include a varying number of components and that single components shown in the illustrations may be representative of multiple components.

InFIG. 1, an integrated circuit10is partially fabricated for use in a typical replacement gate process. As shown, the partially fabricated integrated circuit10includes a semiconductor substrate12. The semiconductor substrate12for example is a silicon material as typically used in the semiconductor industry, e.g., relatively pure silicon as well as silicon admixed with other elements such as germanium, carbon, and the like. Alternatively, the semiconductor material can be germanium, gallium arsenide, or the like. The semiconductor material may be provided as a bulk semiconductor substrate, or it could be provided on a silicon-on-insulator (SOI) substrate, which includes a support substrate, an insulator layer on the support substrate, and a layer of silicon material on the insulator layer. Alternatively, the semiconductor substrate12may include a compound semiconductor such as, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the semiconductor substrate12may optionally include an epitaxial layer. Also, the semiconductor substrate12may be in the form of fin structures for use in a FinFET. As shown, the semiconductor substrate is provided with a substantially planar surface16.

As shown inFIG. 1, sacrificial gate structures18are formed overlying the surface16. As used herein, “overlying” means “on” and “over”. In this regard, the sacrificial gate structures18may lie directly on the semiconductor substrate12such that they make physical contact with the semiconductor substrate12or they may lie over the semiconductor substrate12such that another material layer is interposed between the semiconductor substrate12and the sacrificial gate structures18. Each exemplary sacrificial gate structure18includes a sacrificial gate20and a sacrificial cap22overlying the sacrificial gate20. The sacrificial gate structures18can be fabricated using conventional process steps such as material deposition, photolithography, and etching. In this regard, fabrication of the sacrificial gate structures18may begin by forming at least one layer of sacrificial gate material overlying the surface16. For this example, the material used for the sacrificial gates20is formed overlying the surface16, and then a hard mask material used for the sacrificial caps22is formed overlying the sacrificial gate material. The sacrificial gate material is typically a polycrystalline silicon material, and the hard mask material is typically a silicon nitride material or a silicon oxide material. In typical embodiments, the sacrificial gate materials are blanket deposited on the semiconductor device structure in a conformal manner (using, for example, chemical vapor deposition, physical vapor deposition (PVD) or another suitable deposition technique).

The hard mask layer is photolithographically patterned to form a sacrificial gate etch mask, and the underlying the sacrificial gate material is anisotropically etched into the desired topology that is defined by the sacrificial gate etch mask. The resulting sacrificial gate structures18including sacrificial gates20and sacrificial caps22are depicted inFIG. 1, and have sides24.

After the sacrificial gate structures18have been created, the process may continue by forming spacers26adjacent the sides24of the sacrificial gate structures18. In this regard,FIG. 2depicts the state of the partially fabricated integrated circuit10after the formation of the spacers26. The spacers26are formed adjacent to and on the sides24of the sacrificial gate structures18. In this regard, formation of the spacers26may begin by conformally depositing a spacer material overlying the sacrificial gate structures18and the surface16. The spacer material is an appropriate insulator, such as silicon nitride, and the spacer material can be deposited in a known manner by, for example, ALD, CVD, low pressure chemical vapor deposition (LPCVD), semi-atmospheric chemical vapor deposition (SACVD), or plasma enhanced chemical vapor deposition (PECVD). The spacer material is deposited to a thickness so that, after anisotropic etching, the spacers26have a thickness that is appropriate for the subsequent etching steps described below. Thereafter, the spacer material is anisotropically and selectively etched to define the spacers26. In practice, the spacer material can be etched by, for example, reactive ion etching (RIE) using a suitable etching chemistry.

After the spacers26have been created, other processing may be performed to form desired source/drain regions in the semiconductor substrate18, such as etching and epitaxial deposition, stressing techniques, and ion implantations using the sacrificial gate structures as ion implantation masks. The manufacturing process may proceed by forming regions of dielectric material surrounding the spacers26.FIG. 3depicts the state of the partially fabricated integrated circuit10after dielectric material28has been formed. At this point in the fabrication process, previously unoccupied space around the spacers26has been completely filled with the dielectric material28(for example, by blanket deposition), and the exposed surface30of the partially fabricated integrated circuit10has been polished or otherwise planarized.

In certain embodiments, the dielectric material28is an interlayer dielectric (ILD) material that is initially blanket deposited overlying the surface16, the sacrificial gate structures18, and the spacers26using a well-known material deposition technique such as CVD, LPCVD, or PECVD. The dielectric material28is deposited such that it fills the spaces adjacent to the spacers26and such that it covers the spacers26and the sacrificial caps22. Thereafter, the deposited dielectric material28is planarized using, for example, a chemical mechanical polishing tool and such that the sacrificial caps22serve as a polish stop indicator.

The exemplary fabrication process proceeds by removing the sacrificial gate structures18while leaving the spacers26intact or at least substantially intact.FIG. 4depicts the state of the partially fabricated integrated circuit10after removal of the sacrificial gate structures18. Removal of the sacrificial gate structures18results in the removal of the sacrificial caps22and the removal of the sacrificial gates20. Accordingly, removal of the sacrificial gate structures18exposes the surface16between the spacers26. Removal of the sacrificial gate structures18results in the formation of trenches32in the dielectric material28. As shown, the trenches32are bounded by trench surfaces34formed by the spacers26and the surface16.

In certain embodiments, the sacrificial gate structures18are removed by sequentially or concurrently etching the sacrificial caps22and the sacrificial gates20in a selective manner, stopping at the desired point. The etching chemistry and technology used for this etching step is chosen such that the spacers26and the dielectric material28are not etched (or only etched by an insignificant amount). Etching of the sacrificial gates20may be controlled to stop at the top of the semiconductor substrate12. The sacrificial gate structures18are removed by dry etching, wet etching, or a combination of dry and wet etching.

InFIG. 5, the exemplary fabrication process continues with the formation of an interlayer material36on the surface16in the trenches32. For example, silicon oxide may be formed as the interlayer material36. The exemplary interlayer material36is selectively formed on the surface16, and not on the trench surfaces34formed by spacers26. For example, the interlayer material36may be formed via a chemical oxide process that oxides the exposed surface16of the semiconductor substrate12. An exemplary interlayer material36has a thickness of from about 5 Angstroms (Å) to about 12 Å, such as about 9 Å.

As shown inFIG. 6, a high-k dielectric layer38is conformally deposited over the partially fabricated integrated circuit10. Specifically, the high-k dielectric layer38is formed over the interlayer material36and along the spacers26in the trenches32, and over the dielectric material28outside of the trenches32. An exemplary high-k dielectric layer38is formed from hafnium oxide (HfO2), hafnium silicate (HfSiOx) or lanthanum oxide (La2O3), although other high-k dielectric materials are also contemplated. In an exemplary embodiment, the high-k dielectric layer38is conformally deposited by ALD. The high-k dielectric layer38may have a thickness of about 14 Å to about 18 Å, such as about 15.6 Å.

After formation of the high-k dielectric layer38, the exemplary method includes forming a capping layer40. The exemplary capping layer40is conformally deposited over the high-k dielectric layer38, both within and outside of the trenches32. An exemplary capping layer40is titanium nitride, though other suitable materials may be used. An exemplary process for depositing the capping layer40is ALD. The capping layer40may be formed with a thickness of about 10 Å to about 20 Å.FIG. 6illustrates the structure of the partially fabricated integrated circuit10after deposition of the capping layer40.

The exemplary fabrication process proceeds by forming a work function metal or stack of work function metals to provide the gate structures to be formed with desired electrical characteristics. InFIG. 7, an optional work function layer42is formed overlying the capping layer40. The work function layer42may include a single work function metal, or a stack of work function metals. In an exemplary embodiment, the work function layer42is used in a P-type gate and is formed of a tantalum nitride/titanium nitride (TaN/TiN) stack, though other work function metals or metal stacks suitable for use in P-type gates may be used. The exemplary work function layer42is conformally deposited by ALD over the capping layer40within and outside of the trenches32. The work function layer42may be formed with a thickness of from about 10 Å to about 20 Å.

A work function layer44may be formed over the work function layer42, or over the capping layer40if the work function layer42is not present. The work function layer44may include a single work function metal, or a stack of work function metals. In an exemplary embodiment, the work function layer44is formed of titanium carbide (TiC) though other appropriate work function metals or work function metal stacks for use in N-type gates may be used. The exemplary work function layer44is conformally deposited by ALD over the work function layer42or capping layer40within and outside of the trenches32. The work function layer44may be formed with a thickness of from about 10 Å to about 20 Å.

InFIG. 8, the exemplary fabrication process proceeds by forming liner50overlying the partially fabricated integrated circuit10. Specifically, the exemplary liner50is conformally deposited over the work function layer44within and outside of the trenches32. An exemplary liner50is titanium nitride (TiN), though other materials suitable for serving as a chemical etch stop may be used. In an exemplary process, the liner50is conformally deposited by ALD. The liner50may have a thickness of from about 15 Å to about 30 Å.

A gate metal54is deposited overlying the liner50of the partially fabricated integrated circuit10inFIG. 9. The exemplary gate metal54fills the trenches32and forms an overburden portion58overlying the dielectric material28. An exemplary gate metal54is formed with a thickness of from about 2000 Å to about 4000 Å. Further, an exemplary gate metal54has an overburden portion58with a thickness of more than about 1000 Å. An exemplary gate metal54is tungsten. Further, in an exemplary process the tungsten gate metal54is low fluorine tungsten (LFW). An exemplary low fluorine tungsten is deposited by minimizing fluorine concentration at the interface. In another embodiment, the gate metal54is smooth tungsten deposited using a nitrogen assisted CVD process.

A selective etch is performed inFIG. 10to remove the overburden portion58of the gate metal54. Specifically, a chemical etch process is used with an etchant selective to the gate metal54relative to the liner50. For example, for a tungsten gate metal54and a titanium nitride liner50, a suitably selective dry etchant is nitrogen fluoride (NF3). An exemplary etch has a very high tungsten etch rate as a result of using a high plasma power, and the specific selectivity is controlled by maintaining this process at a low temperature. The selective etch process does not utilize any mechanical means, such as an abrasive polishing pad as used in CMP processes, to etch the gate metal54. Rather, the selective etch process is limited to non-mechanical forces, i.e., wet or dry chemical etchants. As a result, grains in the gate metal54are not mechanically lifted or pulled out during the etching process and the resulting upper surface60of the gate metal54is relatively smooth as compared to mechanically etched surfaces. For example, the upper surface60of the gate metal54has a root mean squared surface roughness of less than about 0.5 nm.

The etch process stops at the upper surface64of the liner50due to the selectivity of the chemical etchant. As a result, the upper surface60of the gate metal54is substantially aligned with the upper surface64of the liner50. In an exemplary embodiment, the etch process removes from about 1000 Å to about 2000 Å of the gate metal54.

A planarization process, such as CMP, is performed inFIG. 11to remove the portions of the high-k dielectric layer38, capping layer40, work function layer42, work function layer44, liner50, and gate metal54located outside of the trenches32and over the dielectric material28. The planarization process may remove a portion of the spacers26and the dielectric material28. In an exemplary embodiment, the planarization process removes a portion of the gate metal54having a thickness, indicated by double-headed arrow68, of less than about 25 nm, for example, less than about 20 nm, such as from about 5 nm to about 20 nm, or from about 15 nm to about 20 nm. By limiting the use of a mechanical etching means, i.e., the mechanical polishing pad used in CMP, the process herein avoids lifting, peeling or removal of grains within the gate metal54as the surface portion removed is substantially smaller than that removed by CMP in conventional processes. As a result of the planarization process, the upper surface60of the gate metal54, the upper surface70of the dielectric material28, and the upper edge72of the liner50and layers44,42,40,38and26are substantially co-planar. Further, because grains are not lifted or removed by the limited CMP process, the upper surface60of the gate metal54remains smooth.

InFIG. 12, the high-k dielectric layer38, capping layer40, work function layer42, work function layer44, liner50, and gate metal54are recessed within the trenches32. As a result, the high-k dielectric layer38, capping layer40, work function layer42, work function layer44, liner50, and gate metal54have a recessed surface80that is about 25 nm lower than the surface70of the dielectric material28. An exemplary process uses a reactive ion etch (RIE) selective to the high-k dielectric layer38, capping layer40, work function layer42, work function layer44, liner50, and gate metal54over the spacers26, or uses multiple RIE processes with an etchant selective to layer(s) to be removed over the spacers26. The etchant chemistry may include those discussed above or other suitable etchants that do not attack interfaces in the partially completed integrated circuit10or etch the spacers26. The chemical etch of the gate metal54does not lift or remove grains in the gate metal54, thus the recessed surface80of the gate metal54remains smooth, such as with a root mean squared surface roughness of less than about 0.5 nm.

After formation of the partially-fabricated integrated circuit10ofFIG. 12, the high-k dielectric layer38, capping layer40, work function layer42, work function layer44, liner50, and gate metal54are encapsulated with a capping material82, as shown inFIG. 13. For example, the capping material82is deposited on the recessed surface80. In an exemplary embodiment, the capping material82is silicon nitride. The capping material82may be deposited by a CVD process or other suitable process. If the capping material82is formed with an overburden above the upper surface70of the dielectric material28, the capping material82may be planarized to form a surface84substantially coplanar with the upper surface70of the dielectric material28. Alternatively, the capping material82may be deposited with its surface84substantially coplanar with the upper surface70of the dielectric material28, or at a lower level than the upper surface70of the dielectric material28.

As shown inFIG. 13, replacement metal gate structures90with gate metal54having smooth upper surfaces80are formed by the processes described herein. The smoothness of the surface of the gate metal54after the chemical etch of the overburden portion is retained through later processing by avoiding use of mechanical etching to remove large portions of the gate metal. After formation of the partially fabricated integrated circuit10ofFIG. 13, further processing may be performed to complete the integrated circuit10. For example, back-end-of-line processing may form contacts to the gate structures90and form interconnects between devices on the semiconductor substrate12.

As described above, fabrication processes are implemented to form integrated circuits with smooth metal gates. Further, metal gates are formed with greater uniformity. The processes described herein avoid use of conventional mechanical planarization techniques that remove large portions of metal gate material. Conventional use of such mechanical planarization techniques causes lifting and removal of grains within the metal gate material, resulting in gate metal surface roughness. The processes described herein avoid increased gate metal surface roughness and increased contact resistance, as well as non-uniformity in gate metal surfaces that leads to unpredictable performance.