Semiconductor device having a three-sided textured substrate

A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface. The device layer includes a second semiconductor element electrically connected to the first semiconductor element, and is provided on the first surface of the substrate. The film includes a first film including a first region, a second region, and a third region. The substrate is positioned between the first region and the device layer in a first direction. The substrate is positioned between the second region and the third region in a second direction crossing the first direction. The first film fills the unevenness of the second surface and the side surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-064974, filed on Mar. 29, 2017; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device and a method for manufacturing the same.

BACKGROUND

The thinning of semiconductor chips has been progressing. There are now increased occurrences of “warping” in thinned semiconductor chips. Suppression of this “warping” is desired.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface. The device layer includes a second semiconductor element electrically connected to the first semiconductor element, and is provided on the first surface of the substrate. The film includes a first film including a first region, a second region, and a third region. The substrate is positioned between the first region and the device layer in a first direction. The substrate is positioned between the second region and the third region in a second direction crossing the first direction. The first film fills the unevenness of the second surface and the side surface.

Embodiments of the invention will now be described in the following with reference to the drawings.

Note that the drawings are schematic or simplified illustrations and that relationships between thicknesses and widths of parts and proportions in size between parts may differ from actual parts. Also, even where identical parts are illustrated, mutual dimensions and proportions may be illustrated differently depending on the drawing.

Note that in the drawings and specification of this application, the same numerals are applied to elements that have already appeared in the drawings and been described, and repetitious detailed descriptions of such elements are omitted.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment.FIG. 2is a schematic cross-sectional view along the II-II line inFIG. 1.FIG. 3is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

The first direction, second direction, and third direction are shown inFIG. 1toFIG. 3. In the specification, the first direction is defined as a Z-axis direction. One direction crossing, for example, orthogonal to the Z-axis direction, is defined as the second direction. The second direction is the X-axis direction. One direction crossing, for example, orthogonal to both the Z-axis direction and the X-axis direction, is defined as the third direction. The third direction is the Y-axis direction.

As shown inFIG. 1toFIG. 3, the semiconductor device according to the first embodiment includes a substrate1, a device layer2, and a film3including a first film31. The semiconductor device according to the first embodiment is, for example, a first semiconductor chip100sliced from a semiconductor wafer.

The substrate1includes a first surface1a, a second surface1b, and a side surface1c. The second surface1bis separated from the first surface1ain the Z-axis direction. The side surface1cis between the first surface1aand second surface1b. The substrate1includes a first semiconductor element Tr1. The substrate1includes a semiconductor, for example, silicon (Si), and an n-type well region, a p-type well region, and a device isolation region are provided on a side of the first surface1a. For example, the first semiconductor element is provided on the n-type well region and the p-type well region. The first semiconductor element Tr1includes, for example, a transistor. InFIG. 1, an illustration of the n-type well region, p-type well region, and device isolation region is omitted.

The device layer2is provided on the first surface1a. The device layer2includes, for example, a second semiconductor device Tr2, an electric wire, an insulator, and a resin layer (for example, polyimide) from a side of the substrate1. For example, the second semiconductor element Tr2includes, for example, a transistor or a memory cell. For example, the second semiconductor element Tr2is electrically connected to the first semiconductor element Tr1through an electric wire (not illustrated). InFIG. 1, an illustration of the electric wire, insulator, and resin layer is omitted. An electric wire and a metal layer of aluminum (Al) or the like that functions as an electrode is provided on an upper surface2aof the device layer2. InFIG. 1, an illustration of the metal layer is omitted.

The film3including the first film31includes a first region3ra, a second region3rb, and a third region3rc. The substrate1is positioned between the first region3raand the device layer2in the Z-axis direction, and is positioned between the second region3rband the third region3rcin the X-axis direction. The first film31covers, for example, the second surface1bof substrate1, and the side surface1cof the substrate1. In the first embodiment, the film3is, for example, one film provided continuously from on the second surface1bof the substrate1to on the side surface1cof the substrate1. For example, the first film31is a film with an integral structure.

In the first embodiment, a gap G is provided between the side surface1cof the substrate1and the side surface2cof the device layer2. The film3is separated from the device layer2. The film3is provided on the side surface1cof the substrate1, however, for example, it is not provided on the first surface1ain the gap G and on the device layer2. In the gap G, a structure21is provided on the first surface1aof the substrate1. The structure21includes, for example, an insulator. The structure21may also include an insulator, and a metal layer of Al or the like. The structure21may also include an insulator, a metal layer, and a resin layer provided on the metal layer. One example of the width in the X-direction for the gap G is not less than 5 μm and not more than 100 μm. In particular, although not illustrated, the width in the Y-direction of the gap G is also, for example, not less than 5 μm and not more than 100 μm. The width in the X-axis direction and the width in the Y-axis direction of the gap G vary according to the design. The width in the X-axis direction and the width in the Y-axis direction of the gap G are not limited to not less than 5 μm and not more than 100 μm.

The substrate1is, for example, thinned. The second surface1bof the thinned substrate1has, for example, minute surface roughness. The minute surface roughness causes a minute unevenness4on the second surface1b. The minute surface unevenness4may also include, for example, a scratch (microscratch)4aas illustrated inFIG. 2. The scratch4ais, for example, a “grinding mark” formed in the Back Side Grinding (BSG) process. The BSG process is performed when the substrate1is thinned. For example, the substrate1having the scratch4aon the second surface1bis thinned. The minute unevenness4also occurs on the side surface1c. The minute unevenness4of the side surface1coccurs, for example, together with a chipping4bor the like in dicing.

In the first semiconductor chip100, the second surface1bof the substrate1and the side surface1cof the substrate1are covered by the film3including the first film31. The first film31suppresses deformations of the substrate1. The first film31mitigates the force of the device layer2that attempts to deform the substrate1, for example, on the second surface1bof the substrate1. The first film31is, for example, a stress load layer.

According to the first embodiment, for example, a thickness tb of the substrate1is thinned, and deformation of the substrate1can be suppressed, even in a case where transverse strength of the substrate1itself decreases. Thus, for example, “warping” of the first semiconductor chip100can be suppressed. The thickness tb of the substrate1is the thickness of the substrate1in the Z-axis direction.

In the first embodiment, the minute unevenness4of the second surface1band side surface1cis filled by the film3. The surface roughness of a back surface100aof the first semiconductor chip100can be reduced in comparison to when the back surface100aremains as the second surface1bof the substrate1. The surface roughness of a side surface100cof the first semiconductor chip100can also be reduced in comparison to when the side surface100cremains as the side surface1cof the substrate1. According to the first embodiment in which the surface roughness of the back surface100aof the first semiconductor chip100can be reduced, for example, it is also possible to omit a treatment that decreases the minute unevenness4(for example, dry polishing or the like), implemented after the BSG process.

Surface roughness of the back surface100aor side surface100cof the first semiconductor chip100affects the strength of the substrate1. For example, surface roughness of the back surface100aor side surface100creduces “transverse strength” of the substrate1, and also promotes, for example, “breakability” of the substrate1. Note that in the specification “substrate1breaks” includes “substrate1breaks” and “substrate1cracks”. In the case where transverse strength of the substrate1decreases, it becomes likely that substrate1will deform when it is made into individual pieces. In a case where the substrate1becomes breakable, substrate1will become more likely to be damaged in processes where a load such as bending stress or the like is applied to the substrate1, such as a pick-up process and mounting process or the like.

In the first embodiment, the film3is provided on the second surface1bof the substrate1, thus, for example, a decrease in strength of the substrate1caused by the minute unevenness4of the second surface1bcan be suppressed. The minute unevenness4of the second surface1b, for example, strongly affects transverse strength. According to the first embodiment, for example, “warping” of the first semiconductor chip100can be suppressed.

Furthermore, in the first embodiment, the film3is also provided on the side surface1cof the substrate1. The film3including the first film31mitigates the force of the device layer2that attempts to deform the substrate1, for example, even on the side surface1cof the substrate1. In addition to this advantage, for example, a decrease in strength of the substrate1caused by the minute unevenness4of the side surface1ccan be further suppressed. The minute unevenness4of the side surface1c, for example, affects the “breakability” of the substrate1. According to the first embodiment, for example, “breaking” of the first semiconductor chip100can be suppressed. In particular, the first semiconductor chip100becomes even less likely to be damaged in the pick-up process and mounting process or the like.

Additionally, in the first embodiment, the film3is provided as one film, continuous from on the second surface1bof the substrate1to on the side surface1cof the substrate1. According to this kind of film3including the first film31, for example, “peeling resistance” from the substrate1improves. “Peeling resistance” of the film3including the first film31improves, so the first film31is stable on the substrate1. The first film31is stable on the substrate1, so an effect can be further obtained where, for example, “warping” and “breaking” of the first semiconductor chip100can be suppressed.

There is also a case where, for example, chipping4bis generated on the second surface1bof the substrate1and the side surface1cof the substrate1. In this case, the minute unevenness4further includes the chipping4b. The chipping4b, for example, is a “dicing mark” formed in the dicing process. Also, the chipping4bis a “minute crack” in the substrate1, generated in the dicing process or BSG process. For example, the substrate1is diced, with the chipping4bon the second surface1band side surface is of the substrate1. There are occasions where the chipping4benlarges the surface roughness of the second surface1bof the substrate1and the surface roughness of the side surface1cof the substrate1.

In the first embodiment, the chipping4bis filled by the film3. The minute unevenness4including the chipping4bbecomes smaller. Accordingly, in the first embodiment, “warping” and “cracking” of the first semiconductor chip100can be suppressed, even in cases where there is minute unevenness4including chipping4bon the second surface1bof the substrate1and the side surface1cof the substrate1.

There is also a case where, for example, a crack4cis generated on the side surface1cof the substrate1. The crack4creaching the side surface1cof the substrate1, for example, can become an invasion route into the substrate1by impurities such as, for example, metal, moisture, and organic matter or the like, or ions. In a case where impurities or ions invade into the substrate1, for example, there is a possibility that operation, for example, of the first semiconductor chip100will become unstable. In addition, the crack4citself becomes a cause of decrease in strength of the substrate1.

In the first embodiment, the crack4cis sealed by the film3including the first film31. According to the first embodiment, infiltration of impurities into the substrate1can be suppressed, in comparison to when there is no film3on the side surface1c. Accordingly, operation of the first semiconductor chip100, for example, can also be stabilized over a long period of time. Even in the case where the crack4cis generated on the side surface1cof the substrate1, suppression of a decrease in strength of the first semiconductor chip100or an improvement in strength of the first semiconductor chip100can be sought. An effect can be further obtained where, for example, “warping” and “breaking” of the first semiconductor chip100can be suppressed.

As shown inFIG. 3, the effect wherein the minute unevenness4is filled, for example, increases as a thickness tx in the X-axis direction of the film3and a thickness tz in the Z-axis direction of the film3is made thicker. For example, it is also likely that the surface of the back surface100aof the first semiconductor chip100and the surface of the side surface100cof the first semiconductor chip100are brought exceedingly close to flat. The surface roughness of the back surface100aof the first semiconductor chip100and the surface roughness of the side surface100cof the first semiconductor chip100each become smaller. In a case where the surface roughness of the back surface100aof the first semiconductor chip100and the surface roughness of the side surface100cof the first semiconductor chip100can be made smaller, an effect can be further obtained where, for example, “warping” and “breaking” of the first semiconductor chip100can be suppressed.

FIG. 4AtoFIG. 4Care schematic cross-sectional views illustrating the semiconductor device according to the first embodiment. The relationship between the thickness tx in the X-axis direction of the film3and the thickness tz in the Z-axis direction of the film3is shown inFIG. 4AtoFIG. 4C. Note that illustrations for the minute unevenness4are omitted inFIG. 4AtoFIG. 4C.

As shown inFIG. 4AtoFIG. 4C, the relationship between the thickness tx in the X-axis direction of the film3and the thickness tz in the Z-axis direction of the film3is not particularly limited. For example, it may be “tx<tz (FIG. 4A)”, “tx=tz (FIG. 4B)”, or “tx>tz (FIG. 4C)”.

As shown inFIG. 4A, when “tx<tz”, of the advantage wherein “warping” can be suppressed and the advantage wherein “breaking” can be suppressed, for example, the former advantage can be more powerfully obtained.

As shown inFIG. 4B, when “tx=tz”, each advantage wherein “warping” and “breaking” can be suppressed, for example, can be sufficiently obtained.

As shown inFIG. 4C, when “tx>tz”, of the advantage wherein “warping” can be suppressed and the advantage wherein “breaking” can be suppressed, for example, the latter advantage can be more powerfully obtained. Furthermore, for example, an advantage can be obtained wherein the thickness in the Z-axis direction of the first semiconductor chip100can easily be made thin.

The thickness tx in the X-axis direction of the film3and the thickness tz in the Z-axis direction of the film3, for example, can be calculated from a cross-sectional observation image, enlarged using a measurement device such as SEM, TEM or the like. Magnification of the cross-sectional image, for example, is 5000 times. The “likelihood” of the measurement for the thickness tx and thickness tz is improved by increasing the magnification. The measurement location of the thickness tz in the Z-axis direction of the film3and the measurement location of the thickness tx in the X-axis direction of the film3, for example, should be the center cross-section of the substrate1. For the center cross-section, the center part in the X-axis direction of the substrate1or the Y-axis direction of the substrate1, for example, is almost the center part for the thickness tz, and the center part of the substrate1in the Z-axis direction of the substrate1is, for example, almost the center part for the thickness tx. For example, the thickness tz in the Z-axis direction of the film3and the thickness tx in the X-axis direction of the film3in the center cross-section of the substrate1are understood from the results of cross section SEM and TEM observation in the X-axis direction, and the results of cross section SEM and TEM observation in the Y-axis direction. The number of semiconductor devices to be measured is appropriately 1 or 3. In the case where there is a plurality of semiconductor devices to be measured, each of the thickness tz in the Z-axis direction of the film3and the thickness tx in the X-axis direction of the film3is understood, and, for example, an average is taken. Furthermore, when a plurality of semiconductor devices is selected to be measured, it is preferable that one where the first semiconductor chip100is positioned in the center of the wafer and one that includes the first semiconductor chip100adjacent to the first semiconductor chip100positioned in the center are selected.

A material where the force of the device layer2, for example, can be mitigated can be selected for the material of the first film31. The first film31may be either a metal or a non-metal. The first film31may be either conductive or have insulation properties.

Examples of metals that can be used as the material of the first film31are described below. Modulus of elasticity E (GPa) and coefficient of linear expansion α (ppm) are also described in the following. Modulus of elasticity E and coefficient of linear expansion α, for example, are measurement values taken at atmospheric pressure (between 100 kPa to 102 kPa, for example, standard atmospheric pressure of 101.325 kPa) and room temperature (approximately 25° C.).

The first film31includes at least one metal selected from the group consisting of, for example:

Thermal stress, intrinsic stress due to crystal structure or the like are included in film stress (for example, residual stress) of the first film31. A material having both a high modulus of elasticity E and coefficient of linear expansion α has high film stress. In a case where film stress is high, it is highly effective in mitigating the force of the device layer2that attempts to deform the substrate1. For example, Ni has both a high modulus of elasticity E and coefficient of linear expansion α. Ni is a material with great intrinsic stress. Ni has high film stress. Ni, for example, is used as a solder alloy barrier layer. Ni is unlikely to undergo a diffusion reaction with other materials. It can be fully expected that Ni also has an advantage in which infiltration of ions into the substrate1(for example, Si) and a mold material (for example, resin) can be suppressed. Ni is not as expensive as, for example, W or Ti. Ni is one preferable material as the material of the film3. For example, in the first embodiment, the first film31includes Ni.

The first film31may also be an alloy, or a metal alloy, including at least one of the metals (a) to (h). The metal compound, for example, includes an oxide including at least one of the metals (a) to (h) and a nitride including at least one of the metals (a) to (h), and an oxynitride including at least one of the metals (a) to (h), or the like.

When an alloy or a metal compound is used in the material for the first film31, for example, the first film31includes at least one alloy or metal compound selected from the group consisting of:

For example, a nickel alloy can adjust the size of intrinsic stress of Ni. It is possible for film stress of a nickel alloy to be increased, for example, by the film stress of Ni. A Ni alloy is one ideal material as the material of the first film3.

The first film31may also be an alloy including at least one of the metals (a) to (h), in addition to the alloys (i) to (m).

The first film31may also be a non-metal. A non-metal that can be practically used as a material of the first film31is described below. In the following, the examples of insulator are described as non-metals. Note that the insulator includes a metal compound, for example, aluminum oxide (alumina).

The first film31includes at least one non-metal selected from the group consisting of, for example:

The metals (a) to (h), alloys, or metal compounds (i) to (m), and non-metals (n) to (q) are merely examples. Metals, alloys, or metal compounds, and non-metals (insulators or the like) other than the foregoing may also be selected.

The materials of the first film31described in the first embodiment are also applied to variations of the first embodiment, the second embodiment, and variations of the second embodiment, to be described later.

FIG. 5AtoFIG. 5Care schematic cross-sectional views illustrating the semiconductor device according to a first variation of the first embodiment. Note that illustrations for the minute unevenness4are omitted inFIG. 5AtoFIG. 5C.

As shown inFIG. 5A, the first film31of a second semiconductor chip100B according to the first variation includes a first layer31a, and a second layer31b. The second layer31bis provided between the substrate1and the first layer31a. The first layer31aincludes a metal, for example, Ni. The second layer31bincludes, for example, any one of Ti, Cr, and W. The second layer31bis, for example, an adhesive layer for improving the adhesiveness of the substrate1and the first layer31a. The first layer31ais a stress load layer. In a case where adhesiveness of the substrate1and the first layer31aimproves, “peeling resistance” of the first layer31aimproves. The first layer31ais stable on the substrate1. According to the first variation, an effect can be further obtained where, for example, “warping” and “breaking” of the first semiconductor chip100can be suppressed.

In a case where the first film31includes two layers, the first film31includes at least one stacked structure selected from the group consisting of, for example:

(s) layer including any one of Ti, Cr, and W/layer including Ni

(t) layer including any one of Ti, Cr, and W/layer including Cu.

For the stacked structure (s), the second layer31bincludes any one of Ti, Cr, and W, and the first layer31aincludes Ni.

For the stacked structure (t), the second layer31bincludes any one of Ti, Cr, and W, and the first layer31aincludes Cu.

The first film31may also include three or more layers.

In the case shown inFIG. 5B, the first film31includes the first layer31a, the second layer31b, and a third layer31c. The second layer31bis provided between the substrate1and the first layer31a. The first layer31ais provided between the second layer31band the third layer31c.

In the case shown inFIG. 5C, the first film31includes the first layer31a, the second layer31b, the third layer31c, and a fourth layer31d. The second layer31bis provided between the substrate1and the first layer31a. The first layer31ais provided between the second layer31band the fourth layer31d. The fourth layer31dis provided between the first layer31aand the third layer31c.

In a case where the first film31includes three or more layers, the first film31includes at least one stacked structure selected from the group consisting of, for example:

(u) layer including Ti/layer including Ni/layer including Cu

(v) layer including Ti/layer including W/layer including Ti

For the stacked structure (u), the second layer31bincludes Ti, the first layer31aincludes Ni, and the third layer31cincludes Cu.

For the stacked structure (v), the second layer31bincludes Ti, the first layer31aincludes W, and the third layer31cincludes Ti.

For the stacked structure (w), the second layer31bincludes Ti, the first layer31aincludes Ni, the fourth layer31dincludes Cu, and the third layer31cincludes Ti.

For example, in the stacked structure (u) and the stacked structure (w), the first film31includes, for example, a layer including Ni, and a layer including Cu. Film stress of the layer including Ni is different to film stress of the layer including Cu. The first film31may also include a plurality of layers with different film stresses. In a case where the first film31includes a plurality of layers with different film stresses, for example, an advantage can be obtained where the degree of freedom in relation to adjustment of the film stress in the first film31increases.

The first film31in the stacked structures (s) to (w) includes a metal layer, but the first film31may also include an alloy layer, a metal compound layer (for example, metal oxide, metal nitride, and metal oxynitride or the like), and a non-metal layer (for example, silicon oxide, silicon nitride, and silicon oxynitride or the like). In particular, although not shown, the first film31may also include five or more layers.

Such a stacked structure for the first film31is applied to variations of the first embodiment, the second embodiment, and variations of the second embodiment, to be described later.

FIG. 6is a schematic perspective view illustrating the semiconductor device according to the first embodiment. Note that only the substrate1and the film3including the first film31are shown inFIG. 6.

As shown inFIG. 6, in the first semiconductor chip100, the first film31is not patterned on the second surface1bof the substrate1. The first film31is provided, for example, on the entire surface of the second surface1bof the substrate1. The first film31may also be patterned on the second surface1bof the substrate1. The first film31may be cracked in one part, and may have one part removed on the second surface1bof the substrate1. In the following, a representative example of the first film31that has been patterned on the second surface1bof the substrate1is illustrated as a second variation to a fourth variation.

FIG. 7is a schematic perspective view illustrating a semiconductor device according to a second variation of the first embodiment. Note that only the substrate1and the film3including the first film31are shown inFIG. 7.

As shown inFIG. 7, in a third semiconductor chip100C of the semiconductor device according to the second variation, the first film31has a hole pattern3H on the second surface1bof the substrate1. The hole pattern3H, for example, is an isolated opening reaching from the surface of the first film31to the second surface1bof the substrate1. The first film31of the second semiconductor chip100B is provided, for example, as one ring-shaped pattern on four edges1Ea to1Ed of the substrate1, on the second surface1bof the substrate1.

The first film31may also have, for example, a hole pattern3H on the second surface1bof the substrate1. The first film31may also have a plurality of hole patterns3H.

FIG. 8is a schematic perspective view illustrating a semiconductor device according to a third variation of the first embodiment. Note that only the substrate1and the film3including the first film31are illustrated inFIG. 8.

As shown inFIG. 8, in a fourth semiconductor chip100D of the semiconductor device according to the third variation, the first film31has a slit pattern3S on the second surface1bof the substrate1. The slit pattern3S is, for example, a line-shaped opening reaching from the surface of the first film31to the second surface1bof the substrate1. The slit pattern3S is provided, for example, along the Y-axis direction, from an edge to another edge of the substrate1. The first film31of the fourth semiconductor chip100D is provided, for example, as two line-shaped patterns on the edge1Eb of the substrate1and on the edge1Ed of the substrate1, on the second surface1bof the substrate1. The edge1Eb of the substrate1faces the edge1Ed of the substrate1, in the substrate1which is a square shape.

The first film31may also have, for example, the slit pattern3S on the second surface1bof the substrate1. The slit pattern3S does not need to be provided from an edge to another edge of the substrate1. For example, the slit pattern3S may also be provided from on the second surface1bof the substrate1to one edge of the substrate1. The first film31may have a plurality of the slit patterns3S. The first film31may also have the slit pattern3S and the hole pattern3H.

FIG. 9is a schematic perspective view illustrating a semiconductor device according to a fourth variation of the first embodiment. Note that only the substrate1and the film3including the first film31are illustrated inFIG. 9.

As shown inFIG. 9, in a fifth semiconductor chip100E of the semiconductor device according to the fourth variation, the first film31has a cross pattern3C on the second surface1bof the substrate1. The cross pattern3C is, for example, a cross-shaped opening reaching from the surface of the first film31to the second surface1bof the substrate1. The cross pattern3C has a part provided along the Y-axis direction from an edge to another edge of the substrate1, and has a part provided along the X-axis direction from an edge to another edge of the substrate1. The first film31of the fifth semiconductor chip100E is provided, for example, as four isolated patterns on four corners1Ca to1Cd of the substrate1, on the second surface1bof the substrate1.

The first film31may also have, for example, the cross pattern3C on the second surface1bof the substrate1. The cross pattern3C does not need to be provided from an edge to another edge of the substrate1. For example, the cross pattern3C may also be provided as an isolated cross-shaped opening on the second surface1bof the substrate1. The first film31is not limited to one cross pattern3C, but may also have a plurality of such. The first film31may also have the cross pattern3C and the hole pattern3H. The first film31may also have the cross pattern3C and the slit pattern3S. The first film31may also have the cross pattern3C, the hole pattern3H, and the slit pattern3S.

Additionally, the first film31may also have an “opening” with a different pattern to the hole pattern3H, the slit pattern3S, and the cross pattern3C, on the second surface1bof the substrate1.

FIG. 10is a schematic cross-sectional view illustrating a semiconductor device according to a fifth variation of the first embodiment.

As shown inFIG. 10, in a sixth semiconductor chip100F of the semiconductor device according to the fifth variation, the film3includes the first film31and a second film32. The second film32is provided between the substrate1and the first film31.

The first film31of the sixth semiconductor chip100F includes, for example, a metal. In the fifth variation, the first film31includes, for example, Ni. The first film31is, for example, a stress load layer. The second film32includes, for example, a metal different to the first film31, or a non-metal. In the fifth variation, the second film32includes, for example, silicon oxide.

In the fifth variation, the function of the second film32includes at least one of the following, for example:

suppressing diffusion of ions from the first film31to the substrate1(for example, a barrier layer)

improving adhesiveness of the first film31and the substrate1(for example, an adhesive layer)

insulating the first film31and the substrate1(for example, an insulating layer).

According to the fifth variation, at least one of the following advantages can be further obtained, for example:

diffusion of ions from the first film31to the substrate1can be suppressed

adhesiveness of the first film31and the substrate1can be improved

the first film31can be electrically insulated from the substrate1.

In a case where diffusion of ions from the first film31to the substrate1can be suppressed, for example, reliability of the semiconductor device improves.

In a case where adhesiveness of the first film31and the substrate1improves, for example, an effect can be further obtained where, for example, “warping” and “breaking” of the sixth semiconductor chip100F can be suppressed.

In a case where the first film31can be electrically insulated from the substrate1, for example, reliability of the semiconductor device improves.

For example, in the fifth variation, the second film32includes, for example, silicon oxide. In this case, the second film32functions as a barrier layer for suppressing diffusion of ions from the first film31including, for example, Ni to the substrate1.

FIG. 11is a schematic cross-sectional view illustrating a semiconductor device according to a sixth variation of the first embodiment. As shown inFIG. 11, in a seventh semiconductor chip100G of the semiconductor device according to the sixth variation, the film3includes the first film31and the second film32. The second film32is provided between the substrate1and the first film31. The first film31includes the first layer31aand the second layer31b. The second layer31bis provided between the first film31and the first layer31a.

The first layer31aof the seventh semiconductor chip100G includes, for example, a metal. In the sixth variation, the first layer31aincludes, for example, Ni. The first layer31ais, for example, a stress load layer. The second layer31bincludes, for example, a metal different to the first layer31a, or a non-metal. In the sixth variation, the second layer31bincludes, for example, Ti. The second film32includes, for example, a metal different to the first layer31aand the first layer31a, or a non-metal. In the sixth variation, the second film32includes, for example, silicon oxide.

In the sixth variation, the function of the second layer31bincludes at least one of the following, for example:

improving the adhesiveness of the first layer31aand the second film32(for example, an adhesive layer)

suppressing the diffusion of ions from the first layer31ato the second film32(for example, a barrier layer)

insulating the first layer31aand the second film32(for example, an insulating layer).

According to the sixth variation, at least one of the following advantages can be further obtained, for example:

adhesiveness of the first layer31aand the second film32improves

diffusion of ions from the first layer31ato the second film32can be suppressed

the first layer31acan be electrically insulated from the second film32. For example, in the sixth variation, the second layer31bincludes, for example, any one of Ti, Cri, and W. In this case, the second layer31bfunctions as an adhesive layer for improving adhesiveness of the first layer31aincluding, for example, Ni and the second film32.

As in the sixth variation, the fifth variation can also be combined with the first variation. A case where the first film31includes two layers is illustrated in the sixth variation, however, the first film31may also include three or more layers.

FIG. 12is a schematic cross-sectional view illustrating a semiconductor device according to a seventh variation of the first embodiment. As shown inFIG. 12, in an eighth semiconductor chip100H of the semiconductor device according to the seventh variation, the film3includes the first film31and a third film33. The first film31is provided between the substrate1and the third film33.

The first film31of the eighth semiconductor chip100H includes, for example, a metal. In the seventh variation, the first film31includes, for example, Ni. The first film31is, for example, a stress load layer. The third film33includes, for example, a metal different to the first film31, or a non-metal. In the seventh variation, the third film33includes, for example, silicon oxide.

FIG. 13is a schematic cross-sectional view illustrating a mold material. Note that an illustration for the minute unevenness4is omitted inFIG. 13.

The semiconductor device has, for example, a mold material. The mold material covers a semiconductor chip. For example, a state wherein the eighth semiconductor chip100H is covered by a mold material23is shown inFIG. 13. The mold material23includes, for example, a resin.

In the seventh variation, the function of the third film33includes at least one of the following, for example:

suppressing the diffusion of ions from the first film31to the mold material23(for example, a barrier layer)

insulating the first film31and the mold material23(for example, an insulating layer)

improving the adhesiveness of the first film31and the mold material23(for example, an adhesive layer).

According to the seventh variation, at least one of the following advantages can be further obtained, for example:

diffusion of ions from the first film31to the mold material23can be suppressed

the first film31can be electrically insulated from the mold material23

adhesiveness of the first film31and the mold material23improves.

In the case where diffusion of ions from the first film31to the mold material23can be suppressed, for example, reliability of the semiconductor device improves.

In the case where the first film31can be electrically insulated from the mold material23, for example, reliability of the semiconductor device improves.

In the case where adhesiveness of the first film31and the mold material23improves, for example, reliability of the semiconductor device improves.

For example, in the seventh variation, the third film33includes, for example, silicon oxide. In this case, the third film33functions as a barrier layer for suppressing diffusion of ions from the first film31including, for example, Ni to the mold material23.

In particular, although not shown, note that the seventh variation can also be combined with the first variation.

FIG. 14is a schematic cross-sectional view illustrating a semiconductor device according to an eighth variation of the first embodiment. As shown inFIG. 14, in a ninth semiconductor chip100I of the semiconductor device according to the eighth variation, the film3includes the first film31, the second film32, and the third film33. The second film32is provided between the substrate1and the first film31. The first film31is provided between the second film32and the third film33.

The first film31of the ninth semiconductor chip100I includes, for example, a metal. In the eighth variation, the first film31includes, for example, Ni. The first film31is, for example, a stress load layer. The second film32includes, for example, a metal different to the first film31, or a non-metal. In the eighth variation, the second film32includes, for example, silicon oxide. The third film33includes, for example, a metal different to the first film31, or a non-metal. In the eighth variation, the third film33includes, for example, silicon oxide.

As in the eighth variation, the fifth variation can also be combined with the seventh variation. According to the eighth variation, for example, the advantages obtained from the fifth variation and the seventh variation can both be obtained.

In particular, although not shown, note that the eighth variation can also be combined with the first variation.

In the fifth to the eighth variations, the second film32and third film33each include, for example, at least one selected from the group consisting of the aforementioned non-metals (n) to (q). The non-metals (n) to (q) are merely examples. Non-metals other than the foregoing may also be selected. Additionally, a metal compound with insulation properties, for example, alumina or the like, may also be selected for the second film32and third film33. The material of the second film32and the material of the third film33are applied to the variations of the first embodiment, the second embodiment, and the variations of the second embodiment, to be described later.

FIG. 15is a schematic cross-sectional view showing the thickness of the film3. Note that an illustration for the minute unevenness4is omitted inFIG. 15.

The function and one object of the first film31are, for example, to mitigate the force of the device layer2that attempts to deform the substrate1. The function and one object of the second film32are, for example, to suppress diffusion of ions from the first film31to the substrate1. The function and one object of the third film33are, for example, to suppress diffusion of ions from the first film31to the mold material23.

In order to achieve these functions and objects, a thickness tz31in the Z-axis direction of the first film31is set to, for example, from 0.5 to 5.0 μm, as shown inFIG. 15. By doing so, for example, “warping” and “breaking” of the substrate1can be suppressed. A thickness t32in the Z-axis direction of the second film32is set to, for example, from appropriately 0.1 to 0.5 μm. In doing so, for example, diffusion of ions from the first film31to the substrate1can be suppressed. A thickness t33in the Z-axis direction of the third film33is set to, for example, appropriately from 0.1 to 0.5 μm. By doing so, for example, diffusion of ions from the first film31to the mold material23can be suppressed.

In the film3, one relationship between the thickness tz31in the Z-axis direction of the first film31and the thickness tz32in the Z-axis direction of the second film32is, for example, set to: tz31>tz32. For example, the thickness tz32in the Z-axis direction of the second film32is set to approximately 1/50 to 1 (=(0.1/5.0) to (0.5/0.5)) of the thickness tz31in the Z-axis direction of the first film31.

In the film3, one relationship between the thickness tz31in the Z-axis direction of the first film31and the thickness tz32in the Z-axis direction of the third film33is, for example, set to: tz31>tz33. For example, the thickness tz33in the Z-axis direction of the third film33is set to approximately 1/50 to 1 (=(0.1/5.0) to (0.5/0.5)) of the thickness tz31in the Z-axis direction of the first film31.

By leveling the thickness tz32in the Z-axis direction of the second film32and the thickness tz33in the Z-axis direction of the third film33to a thinness wherein the functions can be exhibited, the semiconductor chip, for example, the thickness in the Z-axis direction of the ninth semiconductor chip100I shown inFIG. 15can be even slightly thinned. Being able to thin the thickness in the Z-axis direction of the ninth semiconductor chip100I is, for example, a valid advantage in the semiconductor device wherein the ninth semiconductor chip100I is stacked along the Z-axis direction.

The measurement location of the thickness tz31, thickness tz32, and thickness tz33should be, for example, the center cross-section of the substrate1, as aforementioned. The measurement method should be, for example, a calculation from a cross-sectional observation image by SEM or TEM, as aforementioned.

FIG. 16is a schematic cross-sectional view illustrating a semiconductor device according to a ninth variation of the first embodiment. An upper surface3aof the film3is shown inFIG. 16. Note that an illustration for the minute unevenness4is omitted inFIG. 16.

In a case where the first film31includes, for example, a metal, there is a possibility that ions will be diffused from the first film31to the mold material23on the upper surface3aof the film3. Such diffusion of ions can be suppressed by providing, for example, an insulation film22on the upper surface3aof the film3, as in a tenth semiconductor chip1003shown inFIG. 16. The insulation film22is provided, for example, on the upper surface3aof the film3, on an upper surface21aof the structure21, on the side surface21cof the structure21, on an upper surface2aof the device layer2, and on the side surface2cof the device layer2. The insulation film22includes, for example, a resin with insulation properties. The resin with insulation properties is, for example, polyimide or the like.

FIG. 17is a schematic cross-sectional view illustrating a semiconductor device according to a tenth variation of the first embodiment. Note that an illustration for the minute unevenness4is omitted inFIG. 17.

As shown inFIG. 17, in an eleventh semiconductor chip100K of the semiconductor device according to the tenth variation, the film3includes the first film31, the second film32, and the third film33. The first film3includes, for example, a metal, for example, Ni. The second film32and the third film33include, for example, silicon oxide. On the side surface1cof the substrate1, the thickness tx in the X-axis direction of the film3is made thinner toward the first surface1aof the substrate1. For example, the cross-sectional shape of the film3in the tenth variation has, for example, a “tapered shape” becoming thinner from the second surface1bof the substrate1toward the first surface1aof the substrate1, on the side surface1cof the substrate1. The thickness tx31in the X-axis direction of the first film31, the thickness tx32in the X-axis direction of the second film32, and the thickness tx33in the X-axis direction of the third film33are also each thinned toward the first surface1aof the substrate1. For example, on the side surface1cof the substrate1, the first film31is coated by the third film33. The thickness tz in the X-axis direction of the film3becomes, for example, “0”, on, for example, the first surface1aof the substrate1, or near the first surface1a.

In the eleventh semiconductor chip100K of the tenth variation, the third film33covers the first film31on the side surface1cof the substrate1. According to the tenth variation, diffusion of ions from the first film31to the mold material23can be suppressed.

FIG. 18is a schematic cross-sectional view illustrating a semiconductor device according to an eleventh variation of the first embodiment. Note that an illustration for the minute unevenness4is omitted inFIG. 18.

As shown inFIG. 18, in a twelfth semiconductor chip100L of the semiconductor device according to the eleventh variation, the film3includes the first film31, the second film32, and the third film33. Furthermore, the first film31includes the first layer31a, the second layer31b, and the third layer31c. The second layer31bis provided between the first layer31aand the second film32. The first layer31ais provided between the second layer31band the third layer31c. The third layer31cis provided between the first layer31aand the third film33.

The eleventh variation is a combination, for example, of when the first film31of the first variation of the first embodiment includes three or more layers and the eighth variation of the first embodiment.

According to the eleventh variation, at least one of the following advantages can be further obtained, for example:

adhesiveness of the first layer31aand the second film32can be improved

diffusion of ions from the first layer31ato the second film32can be suppressed

the first layer31acan be electrically insulated from the second film32

adhesiveness of the first layer31aand the third film33can be improved

diffusion of ions from the first layer31ato the third film33can be suppressed

the first layer31acan be electrically insulated from the third film33.

In the eleventh variation, the second film32includes, for example, silicon oxide. The second layer31bincludes, for example, any one of Ti, Cr, and W. The first layer31aincludes, for example, Ni. The third layer31cincludes, for example, any one of Ti, Cr, and W. The third film33includes, for example, silicon oxide. The second film32and the third film33including silicon oxide function as barrier layers. The second layer31band the third layer31cincluding Ti function as adhesive layers. The first layer31aincluding Ni functions as a stress load layer.

For example, according to the twelfth semiconductor chip100L, provided with the film3including a “barrier layer/adhesive layer/stress load layer/adhesive layer/barrier layer”, diffusion of ions from the first layer31ato the substrate1and the mold material23can be suppressed. Furthermore, adhesiveness of the first layer31aand the second film32and adhesiveness of the first layer31aand the third film33can both be improved. “Peeling resistance” of the first layer31afurther improves. According to the twelfth semiconductor chip100L wherein peeling resistance of the first layer31afurther improves, diffusion of ions is further suppressed, and reliability of the semiconductor device further improves. Moreover, the twelfth semiconductor chip100K is less likely to experience “warping”, and also less likely to experience “breaking”.

Second Embodiment

FIG. 19is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. The cross-section shown inFIG. 19, for example, corresponds to the cross section shown inFIG. 1.

As shown inFIG. 19, the second embodiment includes the substrate1, the device layer2, and the film3including the first film31, the same as the first embodiment. The second embodiment further includes a film30including a fourth film34.

In the second embodiment, the film3includes the first region3ra. The substrate1is positioned between the first region3raand the device layer2in the Z-axis direction. The film3is provided, for example, on the second surface1bof the substrate1.

The film30includes a fourth region30rd, a fifth region30re, and a sixth region30rf. The substrate1and the film3are positioned between the fourth region30rdand the device layer2in the Z-axis direction. The substrate1is positioned between the fifth region30reand the sixth region30rfin the X-axis direction. In the second embodiment, the film30covers, for example, the film3and the side surface1cof the substrate1. In the second embodiment, the film30is, for example, one film provided continuously from above the film3to above the side surface1cof the substrate1. The one film is, for example, a film with an integral structure.

The gap G is also provided between the side surface1cof the substrate1and the side surface2cof the device layer2in the second embodiment, the same as the first embodiment. The film30is separated from the device layer2. The film30is provided on the side surface1cof the substrate1, however, for example, it is not provided on the first surface1ain gap G and on the device layer2.

In a thirteenth semiconductor chip100M of the second embodiment, the film3and the side surface1cof the substrate1is covered by the film30. The first film31of film3of the thirteenth semiconductor chip100M includes, for example, a metal. In the second embodiment, the first film31includes, for example, Ni. The first film31is, for example, a stress load layer. In the second embodiment, the fourth film34of the film30includes, for example, silicon oxide.

In the second embodiment, the function of the fourth film34includes at least one of the following, for example:

suppressing infiltration of impurities or ions into the substrate1from the side surface1cof the substrate1

suppressing a decrease in strength of the substrate1, caused by a surface roughness4of the side surface is of the substrate1

improving peeling resistance from the substrate1of the film3

suppressing diffusion of ions from the film3to the mold material23.

According to the second embodiment, the film3including the first film31(stress load layer) is provided on the second surface1bof the substrate1. According to the second embodiment, for example, “warping” of the thirteenth semiconductor chip100M can be suppressed.

Furthermore, according to the second embodiment, the film30including the fourth film34is provided. According to the second embodiment, at least one of the following advantages can be further obtained, for example:

infiltration of impurities or ions from the side surface1cof the substrate1into the substrate1can be suppressed

strength of the substrate1further improves

peeling resistance from the substrate1of the film3improves

diffusion of ions from the film3to the mold material23can be suppressed.

In a case where infiltration of impurities or ions from the side surface1cof the substrate1into the substrate1can be suppressed, for example, reliability of the semiconductor device improves.

In a case where the strength of the substrate1further improves, for example, “breaking” of the thirteenth semiconductor chip100M can be further suppressed well. In particular, the thirteenth semiconductor chip100M becomes even less likely to be damaged in the pick-up process and mounting process or the like.

In a case where peeling resistance from the substrate1of the film3improves, for example, the film3is stable on the substrate1. By the film3being stable on the substrate1, the thirteenth semiconductor chip100M can further obtain an effect where, for example, “warping” and “breaking” can be suppressed.

In a case where diffusion of ions from the film3to the mold material can be suppressed, for example, reliability of the semiconductor device improves.

In the second embodiment, the materials described in the first embodiment can be used in the first film31of the film3. The material of the first film31is applied even to the variations of the second embodiment to be described later.

In the second embodiment, a material the same as the material of the second film32of the first embodiment, for example, can be selected for the film of the fourth film34of the film30. The material of the fourth film34is applied even to the variations of the second embodiment to be described later.

FIG. 20is a schematic cross-sectional view illustrating a semiconductor device according to a first variation of the second embodiment. Note that the minute unevenness4is shown inFIG. 20, omitting the unevenness.

As shown inFIG. 20, in a fourteenth semiconductor chip100N of the semiconductor device according to the first variation of the second embodiment, the film3includes the first film31and the second film32. The second film32is provided between the substrate1and the first film31.

As in the first variation of the second embodiment, the second embodiment can be combined with the fifth variation of the first embodiment. In particular, although not shown, note that the second embodiment can be combined with the sixth variation of the first embodiment, and also with the seventh variation of the first embodiment.

FIG. 21is a schematic cross-sectional view illustrating a semiconductor device according to a second variation of the second embodiment. Note that the minute unevenness4is shown in FIG.21, omitting the unevenness.

As shown inFIG. 21, in a fifteenth semiconductor chip100O of the semiconductor device according to the second variation of the second embodiment, the film3includes the first film31, the second film32, and the third film33. The second film32is provided between the substrate1and the first film31. The first film31is provided between the second film32and the third film33.

As in the first variation of the second embodiment, the second embodiment can be combined with the eighth variation of the first embodiment.

FIG. 22is a schematic cross-sectional view illustrating a semiconductor device according to a third variation of the second embodiment. Note that the minute unevenness4is shown inFIG. 22, omitting the unevenness.

As shown inFIG. 22, in a sixteenth semiconductor chip100P of the semiconductor device according to the third variation of the second embodiment, the film30includes the fourth film34and a fifth film35. The fifth film35is one film, for example, provided continuous from on the film3including the first film to on the side surface1cof the substrate1, the same as the fourth film34. The one film is, for example, a film with an integral structure. In the third variation of the second embodiment, the fourth film34is provided between the fifth film35and film3including the first film31, and between the fifth film35and the side surface1cof the substrate1.

In the third variation of the second embodiment, the function of the fifth film35includes, for example:

mitigating the force of the device layer2that attempts to deform the substrate1. The fifth film35, for example, as well as the first film31, suppresses deformation of the substrate1. The fifth film35is, for example, a stress load layer.

The first film31is provided on the second surface1bof the substrate1. The first film31suppresses deformation of the substrate1from on the second surface1bof the substrate1. The fifth film35is provided on the second surface1bof the substrate1, and on the side surface1cof the substrate1. The fifth film35suppresses deformation of the substrate1from both on the second surface1bof the substrate1and on the side surface1cof the substrate1. A material the same as the first film31of the first embodiment, for example, can be selected for the material of the fifth film35. A stacked structure for the fifth film35, for example, can be the same as that of the first film31of the first embodiment.

According to the third variation of the second embodiment, for example, an effect can be further obtained where, for example, “warping” and “breaking” of the sixteenth semiconductor chip100P can be suppressed.

Furthermore, the third variation of the second embodiment includes the film3including the first film31and the fifth film35as stress load layers. According to the third variation of the second embodiment, for example, an advantage can be further obtained where the degree of freedom in relation to adjustment of film stress of a stress load layer increases.

FIG. 23is a schematic cross-sectional view illustrating a semiconductor device according to a fourth variation of the second embodiment. Note that the minute unevenness4is shown inFIG. 23, omitting the unevenness.

As shown inFIG. 23, in a seventeenth semiconductor chip100Q of the semiconductor device according to the fourth variation of the second embodiment, the film30includes the fourth film34, the fifth film35, and a sixth film36. The sixth film36is one film, for example, provided continuous from on the film3to on the side surface1cof the substrate1, the same as the fourth film34and the fifth film35. The one film is, for example, a film with an integral structure. In the fourth variation of the second embodiment, the fifth film35is provided between the sixth film36and the fourth film34. A material the same as the material of the third film33of the first embodiment can be selected for the sixth film36.

In the fourth variation of the second embodiment, the function of the sixth film36includes at least one of the following, for example:

suppressing the diffusion of ions from the fifth film35to the mold material23(for example, a barrier layer)

insulating the fifth film35and the mold material23(for example, an insulating layer)

improving the adhesiveness of the fifth film35and the mold material23(for example, an adhesive layer).

According to the fourth variation of the second embodiment, at least one of the following advantages can be further obtained, for example:

diffusion of ions from the fifth film35to the mold material23can be suppressed

the fifth film35can be electrically insulated from the mold material23

adhesiveness of the fifth film35and the mold material23improves

In a case where diffusion of ions from the fifth film35to the mold material23can be suppressed, for example, reliability of the semiconductor device improves.

In a case where the fifth film35can be electrically insulated from the mold material23, for example, reliability of the semiconductor device improves.

In a case where adhesiveness of the fifth film35and the mold material23improves, for example, reliability of the semiconductor device improves.

Third Embodiment

FIG. 24AtoFIG. 24Gare procedural schematic views illustrating a method for manufacturing a semiconductor device according to a third embodiment.FIG. 25AtoFIG. 25Jare procedural schematic cross-sectional views illustrating a method for manufacturing the semiconductor device according to the third embodiment.

As shown inFIG. 24A,FIG. 25A, andFIG. 25B, a semiconductor wafer W is diced along the X-axis direction and Y-axis direction. The semiconductor wafer W includes the substrate1. The semiconductor wafer W has a surface provided with a plurality of device layers2. A first device layer2l, a second device layer2m, and a third device layer2nare three that are illustrated inFIG. 25AtoFIG. 25J. The surface provided with the first device layer2lto the third device layer2nis a main surface Wa. The semiconductor wafer W includes the main surface Wa in the Z-axis direction, and a back surface Wb separated from the main surface Wa in the first direction. A dicing line5is formed on the diced semiconductor wafer W. The dicing line5is a lattice-shaped groove formed on the semiconductor wafer W, along the X-axis direction and the Y-axis direction. Of the dicing lines5, the dicing lines5along the Y-axis direction are shown inFIG. 25B. In the part shown inFIG. 25B, the dicing lines5are provided between the first device layer2land the second device layer2m, and also between the second device layer2mand the third device layer2n. A width W5is the width of the dicing line5. A width W2is the width between the device layer2. InFIG. 25B, the width in the X-axis direction of the dicing line5is shown as the width W5, and the width in the X-axis direction between the first device layer2land the second device layer2mis shown as the width W2. The width W5of the dicing line5is narrower than the width W2between the device layer2. The gap G is formed between the side surface1cof the substrate1and the side surface2cof the device layer2. A dicing blade7is used, for example, for dicing of the semiconductor wafer W. Dicing is not limited to dicing with the dicing blade7. Dicing with plasma and dicing with a chemical liquid or the like can also be used for dicing.

As shown inFIG. 24BandFIG. 25C, a first support member61is provided on a first device layer2lto the third device layer2n. One example of the first support member61is, for example, surface protection tape.

As shown inFIG. 24C,FIG. 25D, andFIG. 25E, the semiconductor wafer W is, for example, turned over, and the back surface Wb of the semiconductor wafer W turns towards a grindstone8of a grinding machine. Subsequently, the back surface Wb of the semiconductor wafer W is ground, for example, using the grindstone8, and the back surface Wb is retracted. The back surface Wb is retracted to reach the dicing lines5. The semiconductor wafer W is isolated into a plurality of semiconductor chips100on the first support member61. For example, in the part shown inFIG. 25E, the semiconductor wafer W is isolated into the semiconductor chip100lincluding the first device layer2l, the semiconductor chip100mincluding the second device layer2m, and the semiconductor chip100nincluding the third device layer2n, on the first support member61. The dicing lines5become spaces generated between the semiconductor chip100land the semiconductor chip100m, and also between the semiconductor chip100mand the semiconductor chip100n. In the Z-axis direction, the side surface1cof the substrate1is separated from each side surface2cin the first device layer2lto the third device layer2n. The side surface1cof the substrate1is separated, from each side surface2cin the first device layer2lto the third device layer2n, for example, by the width in the X-axis direction of the gap G and the width in the Y-axis direction of the gap G. The width in the X-axis direction of the gap G and the width in the Y-axis direction of the gap G are, for example, not less than 5 μm and not greater than 100 μm. The thickness in the Z-axis direction of the first device layer2lto the third device layer2nis, for example, from 0.5 to 20 μm. The thickness in the Z-axis direction of the first device layer2lto the third device layer2nis modified in various ways according to the design. The first device layer2lto the third device layer2nincludes, for example, a semiconductor device, an electrical wire, an insulator, and a polyimide from a side of the substrate1. The thickness from 0.5 to 20 μm in the Z-axis direction of the first device layer2lto the third device layer2nis, for example, the thickness of the semiconductor device and the electrical wire.

As shown inFIG. 26A, the back surface Wb of the semiconductor wafer W is retracted, and the semiconductor wafer W is thinned.

As shown inFIG. 26B, a lattice-shaped crack5ais formed on the inner part of the semiconductor wafer W along the X-axis direction and the Y-axis direction. The lattice-shaped crack5adoes not, for example, reach the main surface Wa of the semiconductor wafer W and the back surface Wb of the semiconductor wafer W. When the lattice-shaped crack5ais formed on the inner part of the semiconductor wafer W, for example, a transmittable wavelength laser is used on the semiconductor wafer W. The laser is concentrated, for example, to focus on the inner part of the semiconductor wafer W.

As shown inFIG. 26C, for example, the first support member61is stretched. The semiconductor wafer W is isolated into the semiconductor chip100lincluding the first device layer2l, the semiconductor chip100mincluding the second device layer2m, and the semiconductor chip100nincluding the third device layer2n, on the first support member61, the same as the third embodiment. The part wherein the lattice-shaped crack5ais formed becomes the dicing line5.

When the semiconductor wafer W is diced, this kind of dicing method may be used.

As shown inFIG. 24DandFIG. 25F, on the first support member61, the film3is formed on the second surface1bof the substrate1in each semiconductor chip100lto100n, and on the side surface1cof the substrate1.

The film3includes, for example, the first film31, the second film32, and the third film33of the first embodiment. Illustrations of the first film31to the third film33are omitted inFIG. 25FtoFIG. 25J. The first film31to the third film33are formed, for example, using physical vapor deposition. The sputtering method can be given as an example of physical vapor deposition. According to physical vapor deposition, for example, the sputtering method, the first film31, the second film32, and the third film33can each be formed at a low temperature. For example, the first film31, the second film32, and the third film33can each be formed at the heat resistance temperature or less of the first support member61. Thus, when forming the first film31, the second film32, and the third film33, deformation or the like due to heat of, for example, the first support member61, can be suppressed. The heat resistant temperature of the first support member61is, for example, from 100 to not higher than 150° C.

In a case where the film3is formed using physical vapor deposition, for example, the sputtering method, the film3is formed on the second surface1bof the substrate1, on the side surface1cof the substrate1, and on the first support member61exposed to the bottom of the dicing lines5. In the gap G, the substrate1overhangs on the first support member61. The side surface2cof the first device layer2lto the third device layer2nexists in a space enclosed by the overhanging part of the substrate1and the first support member61. The length in the X-axis direction and the Y-axis direction of the space is, for example, from 5 μm to 100 μm. The material for forming the film3is unlikely to enter the space. The film3is not formed, for example, on the side surface2cof the first device layer2lto the third device layer2n. The film3is separated by a part formed on the side surface is of the substrate1, and a part formed on the first support member61.

The film3can also be formed with another physical vapor deposition, for example, chemical vapor deposition (CVD method). In a case where a resin is used, for example, in the film3, the film3can be formed with a coating method.

As shown inFIG. 24E,FIG. 25G, andFIG. 25H, for example, the semiconductor wafer W is turned over. Next, a second support member62is provided on the film3. The second support member62is, for example, dicing tape. The dicing tape may be an integrated dicing tape having, for example, die attach film DAF. The dicing tape may also be a dicing tape having an adhesive material without DAF.

As shown inFIG. 24FandFIG. 25I, the first support member61is peeled off from on the first device layer2lto the third device layer2n.

As shown inFIG. 24GandFIG. 25J, the second support member62is cut along the dicing lines5, to a part in the middle along the Z-axis direction. In the third embodiment, for example, a part of DAF of the second support member62is cut. The semiconductor chips100lto100neach become semiconductor chips100lto100nwith DAF attached. A laser9is used, for example, on the cut of the DAF and the second support member62. A dicing blade may also be used, for example, on the cut of the DAF and the second support member62. The DAF may, for example, extend and cleave the second support member62under cooling.

Following this, the second support member62is, for example, stretched. Subsequently, for example, a push-up pin that is not shown is used, and of the semiconductor chips100lto100n, for example, one is pushed out from on the second support member62. Following this, of the semiconductor chips100lto100n, for example, one is taken out from on the second support member62.

By doing so, the semiconductor chips100lto100nare formed. The semiconductor chips100lto100nare provided with the film3on the second surface1bof the substrate1, and on the side surface1cof the substrate1.

Fourth Embodiment

FIG. 27AtoFIG. 27Fare procedural schematic views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment.FIG. 28AtoFIG. 28JandFIG. 29AtoFIG. 29Dare procedural schematic cross-sectional views illustrating a method for manufacturing the semiconductor device according to the fourth embodiment.

As shown inFIG. 27A,FIG. 28A, andFIG. 28B, the first support member61is provided on the first device layer2lto the third device layer2n. One example of the first support member61is, for example, surface protection tape.

As shown inFIG. 27BandFIG. 28C, for example, the semiconductor wafer W is turned over. Subsequently, the back surface Wb is ground, for example, using the grindstone8, and retracted.

As shown inFIG. 27CandFIG. 28D, on the first support member61, the film3is formed on the back surface Wb of the retracted semiconductor wafer W.

The film3includes, for example, the first film31and the second film32of the second embodiment. Illustrations of the first film31and the second film32are omitted inFIG. 28DtoFIG. 28J. The first film31and the second film32are formed using, for example, physical vapor deposition. The sputtering method can be given as an example of physical vapor deposition.

As shown inFIG. 27DandFIG. 28E, for example, the semiconductor wafer W is turned over. Next, the second support member62is provided on the film3. One example of the second support member62is, for example, dicing tape.

As shown inFIG. 27EandFIG. 28F, the first support member61is peeled off from the main surface Wa of the semiconductor wafer W.

As shown inFIG. 27FandFIG. 28G, on the second support member62, for example, the semiconductor wafer W is diced along the X-axis direction and Y-axis direction using the dicing blade7. The semiconductor wafer W is isolated into a plurality of semiconductor chips100on the second support member62. In the part shown inFIG. 28G, the semiconductor wafer W is isolated into the semiconductor chip100lincluding the first device layer2l, the semiconductor chip100mincluding the second device layer2m, and the semiconductor chip100nincluding the third device layer2n, on the second support member62. The dicing line5is formed between the semiconductor chip100land the semiconductor chip100m, and also between the semiconductor chip100mand the semiconductor chip100n. The width W5of the dicing line5is narrower than the width W2between the device layer2. The gap G is formed between the side surface1cof the substrate1and the side surface2cof the device layer2. InFIG. 28G, the width in the X-axis direction of the dicing line5is shown as the width W5, and the width in the X-axis direction between the first device layer2land the second device layer2mis shown as the width W2. The side surface is of the substrate1is separated from each side surface2cin the first device layer2lto the third device layer2nby the width in the X-axis direction of the gap G and the Y-axis direction of the gap G.

As shown inFIG. 28H, a third support member63is provided on the first device layer2lto the third device layer2n. One example of the third support member63is, for example, dicing tape.

As shown inFIG. 28I, for example, the semiconductor wafer W is turned over. Next, the second support member62is peeled off from the film3.

As shown inFIG. 28J, on the third support member63, the film30is formed on the film3of each semiconductor chip100lto100n, and on the side surface1cof the substrate1.

The film30includes, for example, the fourth film34of the second embodiment. Illustrations of the reference numerals for the fourth film34are omitted inFIG. 28JandFIG. 29AtoFIG. 29D. The fourth film34is formed using, for example, physical vapor deposition. The sputtering method can be given as an example of physical vapor deposition. According to the sputtering method, the film30including the fourth film34can be formed at a low temperature. For example, the fourth film34can be formed at the heat resistance temperature or less of the third support member63.

In a case where the film30is formed using physical vapor deposition, for example, the sputtering method, the film30is formed on film3, on the side surface1cof the substrate1, and on the third support member63exposed to the bottom of the dicing line5. In the gap G, the substrate1overhangs on the third support member63. The side surface2cof the first device layer2lto the third device layer2nexists in a space enclosed by the overhanging part of the substrate1and the third support member63. The length in the X-axis direction and the Y-axis direction of the space is not less than 5 μm and not more than 100 μm, for example. The material for forming the film30is less likely to enter the space. The film30is not formed, for example, on the side surface2cof the first device layer2lto the third device layer2n. The film30is separated by a part formed on the side surface1cof the substrate1, and a part formed on the third support member63.

The film30can also be formed with another physical vapor deposition, for example, chemical vapor deposition (CVD method). If a resin is used, for example, in the film30, the film30can be formed with a coating method.

As shown inFIG. 29AandFIG. 29B, for example, the semiconductor wafer W is turned over. Next, a fourth support member64is provided on the film30. The fourth support member64is, for example, a tape having an adhesive material. The fourth support member64may also have, for example, an adhesive and DAF, as shown.

As shown inFIG. 29C, the third support member63is peeled off from on the first device layer2lto the third device layer2n.

As shown inFIG. 29D, the fourth support member64is cut along the dicing line5, to a part in the middle along the Z-axis direction. In the fourth embodiment, for example, the part of DAF of the fourth support member64is cut. The semiconductor chips100lto100neach become semiconductor chips100lto100nwith DAF attached. A laser or a dicing blade is used, for example, on the cut of the DAF and the second support member62. The DAF may also, for example, extend and cleave the second support member62under cooling.

Following this, the fourth support member64is, for example, stretched. Subsequently, for example, a push-up pin that is not shown is used, and of the semiconductor chips100lto100n, for example, one is pushed out from on the fourth support member64. Following this, of the semiconductor chips100lto100n, for example, one is taken out from on the fourth support member64.

By doing so, the semiconductor chips100lto100nare formed. The semiconductor chips100lto100nare provided with the film30on the film3, and on the side surface1cof the substrate1.

The embodiments described above can provide a semiconductor device that is able to suppress warping and a method for manufacturing the same.

Moreover, all semiconductor devices, and methods for manufacturing the same practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices, and the methods for manufacturing the same described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.