Structure of package on package and method for fabricating the same

A structure of a package on package and a method for fabricating the same are provided. The structure of the package on package includes a first package, a second package and a plurality of pins. The first package includes a first substrate and a first chip disposed thereon. The second package includes a second substrate and a second chip disposed thereon. The second package is disposed under the first package. The second package includes a plurality of holes. The pins are disposed on the first package and inserted to the holes so as to electrically connect the first package and the second package.

This application claims the benefit of Taiwan application Serial No. 095139858, filed Oct. 27, 2006, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a structure of a package on package and a method for fabricating the same, and more particularly to a structure of a package on package connected by pins and a method for fabricating the same.

2. Description of the Related Art

As portable multimedia devices become more and more popular, the trend toward new storage structures with higher digital signal processing, larger storage capacity and more flexibility grows accordingly. Therefore, the application of stacked package on package (PoP) extends rapidly.

The package on package is a new three-dimensional packaging technology with lowest cost for logic and memory Integration. The stacked package on package is used for developing devices with new appearance or higher integration. Also, the package on package has small volume due to stacked structure. Therefore, the size of the mother board is not increased or even reduced.

FIG. 1is a cross-sectional view of a conventional package on package. Please referring toFIG. 1, the structure of the conventional package on package10includes an upper package12and a lower package14connected together by solder balls20. A chip18, circuits and the solder balls20are disposed on a surface of a substrate16of the lower package14.

The available space for disposing the circuits is limited because the solder balls20and the circuits are both disposed on the lower substrate16. Therefore, it is difficult to dispose vias when the circuits have to be disposed on inner layers. It is even more difficult to disposes the circuits in the high-density area adjacent to the chip18. Therefore, multilayer technology is used or the size of the package is increased for solving the above problems.

SUMMARY OF THE INVENTION

The invention is directed to a structure of a package on package and a method for fabricating the same. Packages are connected by pins so as to increase the space for wiring layout.

According to the present invention, a structure of a package on package and a method for fabricating the same are provided. The package on package includes a first package, a second package and a plurality of pins. The first package includes a first substrate and a first chip disposed thereon. The second package includes a second substrate and a second chip disposed thereon. The second package is disposed under the first package and includes a plurality of holes. The pins are disposed on the first package and inserted in the holes so as to electrically connect the first package and the second package.

According to the present invention, another structure of a package on package including a first package, a second package, a plurality of first pins, a plurality of second pins and a connecting component is provided. The first package includes a first substrate and a first chip disposed thereon. The second package includes a second substrate and a second chip disposed thereon. The second package is dispose under the first package. The first pins are disposed on the first package, and the second pins are disposed on the second package. The connecting component is disposed between the first pins and the second pins so as the electrically connect the first package and the second package.

According to the present invention, a method of fabricating a package on package is provided. First, a first package is provided. A first chip is disposed on and electrically connected with a first substrate. Next, a second package is provided. A second chip is disposed on and electrically connected with a second substrate. Then, a plurality of first pins are disposed on the first substrate. Afterward, a plurality of second pins are disposed on the second substrate. Later, a connecting component is disposed between the second pins. Subsequently, the first pins of the first package are inserted in the connecting component correspondingly, so as to electrically connect the first package and the second package.

According to the present invention, another method of fabricating a package on package is provided. First, a first package is provided. A first chip is disposed on and electrically connected with a first substrate. Next, a second package is provided. A second chip is disposed on and electrically connected with a second package. Then, a plurality of pins are disposed on the first substrate. Afterward, a plurality of holes are formed in the second substrate. Later, a plurality of pins are inserted in the holes so as to electrically connect the first package and the second package.

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment

Please referring toFIG. 2, illustrating a structure of a package on package according to a first embodiment of the present invention. The package on package100of the present embodiment includes a first package120, a second package140and a plurality of pins160. The first package120includes a first substrate122and a first chip124disposed on the first substrate122. The first package120further includes a first inner circuit123and a first molding material126. The first inner circuit123is formed in the first substrate122. The first chip124and the first inner circuit123are electrically connected together. The first molding material126encapsulates at least a portion of the first substrate122and the first chip124.

The second package140includes a second substrate142and a second chip144disposed on the second substrate142. The second package140is disposed under the first package120. The second package140further includes a second inner circuit143, a second molding material146and several solder balls141. The second inner circuit143is formed in the second substrate142. The second chip144is electrically connected with the second inner circuit143. The second molding material146encapsulates at least a portion of the second substrate142and the second chip144. Several solder balls141are disposed on a lower surface of the second substrate142.

FIG. 3Ais an enlarged view of part of the second substrate inFIG. 2. What is worth mentioning is that a plurality of holes148are formed on the second substrate142. Preferably, the second package140further includes a plurality of conductive receptacles149disposed inside the holes148of the second substrate142.

A plurality of pins160are disposed on the first package120and inserted in the holes148for electrically connecting the first package120and the second package140. The pins160are disposed on a lower surface of the first substrate120and electrically connected with the first inner circuit123.

The pins replace the conventional solder balls to connect the two packages. The saved space can be used for wiring layout, disposing the chip, molding, etc. As a result, the space on the second substrate can be used more effectively and flexibly. For example, even when a complicated module, such as a multi-chip package, is used in the package on package, there is no need to increase the substrate area. The wiring layout space on the second substrate is increased and capable of containing more complicated circuits. Furthermore, a large-size chip can be disposed on the substrate of the package on package of the present invention. Moreover, the size of the second substrate can be decreased so that the size of the package on package is reduced.

The method for fabricating the package on package100includes following steps. First, the first package120is provided. The details are as follow. A first inner circuit123is formed in the first substrate122first. Next, the first chip124is disposed on the first substrate124, and electrically connected with the first substrate122. For example, the first chip124is wire-bonded with the first substrate122, as shown inFIG. 2. Then, the first molding material126over molds at least a portion of the first substrate122and the first chip124.

Next, the second package140is provided. Details of this step are as follow. First, the second inner circuit143is formed in the second substrate140. Next, the second chip144is disposed on the second substrate142, and electrically connected with the second substrate142. For example, the second chip144is wire-bonded with the second substrate142, as shown inFIG. 2. Then, the second molding material146over molds at least a portion of the second substrate142and the second chip144.

Then, the pins160are disposed on the first substrate122. The pins160are electrically connected with the first inner circuit123and disposed on the lower surface of the first substrate122.

FIGS. 3A˜3Cillustrate steps of connecting the pins and the holes. Please referring toFIG. 3A, a plurality of holes148are formed in the second substrate142. The holes148are formed on the upper surface of the second substrate142and expose the second inner circuit143. Please referring toFIG. 3B, a plurality of conductive receptacles129are formed in the holes148for protecting the holes148from collapse and guiding the pins160entering the holes148.

Afterwards, the pins160are inserted in the holes148and the conductive receptacles149, as shown inFIG. 3C. When the pins160are inserted in the conductive receptacles149, the pins160are electrically connected with the second inner circuit143for electrically connecting the first package120and the second package140.

Second Embodiment

The present embodiment and the above embodiment are only different in the connection of the first package and the second package. The same parts are not described redundantly. Please referring toFIG. 4, the structure of the package on package according to a second embodiment of the present invention is illustrated inFIG. 4. The package on package200of the present embodiment includes the first package120, the second package140, a plurality of first pins262, a plurality of second pins264and a connecting component270. The first pins262are disposed on the first package120. Preferably, the first pins262are disposed on the lower surface of the first substrate122and electrically connected with the first inner circuit123. The second pins264are disposed on the second package140. Preferably, the second pins264are disposed on the upper surface of the second substrate140and electrically connected with the second inner circuit143.

The connecting component270is disposed between the first pins262and the second pins264for electrically connecting the first package120and the second package140. Please referring toFIG. 5, a cross-sectional view of the connecting component inFIG. 4is illustrated inFIG. 5. The connecting component270includes a first clamp272, a second clamp274and a conductive part276. The first clamp272is for clamping the first pins262, and the second clamp274is for clamping the second pins264. The conductive part276is disposed between the first clamp272and the second clamp274for electrically connecting the second pins264clamped by the second clamp274and the first pins262clamped by the first clamp272. What is worth mentioning is that the connecting component270can be used for connecting only one first pin262and one second pin264(as shown inFIG. 5). Therefore, several connecting components are needed in the package on package200. However, the connecting component is not limited thereto. Only one connecting component can be used for connecting a plurality of first pins262and a plurality of second pins264.

There can be many different kinds of methods for fabricating the package on package. One method is illustrated as follow for example. The method for fabricating the package on package according to the present embodiment includes following steps. After the first package120and the second package140are provided, a plurality of first pins262are disposed on the first substrate122, and a plurality of second pins264are disposed on the second substrate142. The first pins262are disposed on the lower surface of the first substrate122and electrically connected with the first inner circuit123. The second pins264are formed on the upper surface of the second substrate142and electrically connected with the second inner circuit143. Then, the connecting component270is disposed on the first pins262to hold the first pins262. Afterwards, the second pins264of the second package140are inserted in the connecting component270correspondingly. As a result, the first package120is electrically connected with the second package140.

In the structure of the package on package and the method for fabricating the same of the above embodiments, several packages are connected by the pins. The saved space can be used for wiring layout, disposing chips, molding, etc. As a result, the space on the second substrate can be used more effectively and flexibly. For example, even a multi-chip package or another more complicated module is used in the structure of the package on package, there is no need to increase the substrate area. The wiring layout space on the second substrate is enlarged and capable of containing more complicated circuits.