System and method for converting an input signal

A video driver includes a current-to-voltage converter circuit that converts an analog input current to a corresponding analog voltage. Active termination circuitry is configured to synthesize an output impedance at an output thereof that substantially matches a load impedance to which the output is coupled, the active termination circuitry buffering the analog voltage to the output.

TECHNICAL FIELD

This invention relates to an analog video system.

BACKGROUND

One common type of video system architecture includes a video encoder that provides a corresponding digital video signal to a digital-to-analog converter (DAC). The DAC converts the digital input signal to a corresponding analog signal format. Existing and future performance demands, such as can enable studio quality video, can require that the DAC should be at least 10-bit DAC and have linearity that is at least 50 dB. Performance requirements can also necessitate that the DAC operate at a relatively high clock rate, such as of up to 60 MHz or higher.

One challenge in designing a video amplifier is to provide a large output swing for the high-bandwidth video signal while also maintaining adequate linearity. Another consideration for the output buffer is matching the output impedance of the buffer with the load impedance. For example, impedance matching to the load (e.g. about 75Ω) is required to avoid reflections from the load at high frequencies such as are typically utilized in video frequencies. One common approach to achieve impedance matching is either by having a 75Ω in series with the load or by having 75Ω in parallel to the load. Each of these approaches, however, is not power and area efficient. For instance, these approaches typically require more external components than may be desirable in many applications.

The increasing demands of manufacturers to minimize cost while maintaining or improving performance have prompted significant design efforts and new manufacturing techniques. For example, many integrated circuits for video systems are being manufactured using ultra deep submicron processes. Circuits produced by such processes impose additional design considerations due to the requirement of low power consumption as well as substrate and supply rejection. The associated complexity of design and manufacture of such components is compounded in circumstances when having to design such a system with substantially zero-cost passive components (e.g., resistors and capacitors) in a base line CMOS process.

SUMMARY

One embodiment of the present invention provides a video driver that includes a current-to-voltage converter circuit that converts an analog input current to a corresponding analog voltage. Active termination circuitry is configured to synthesize an output impedance at an output thereof that substantially matches a load impedance to which the output is coupled, the active termination circuitry buffering the analog voltage to the output.

Another embodiment of the present invention provides an integrated on-chip system that includes means for converting a digital input signal to a corresponding analog current. The system also includes means for converting the analog current to a corresponding analog voltage. The system also includes means for actively matching impedance at an output of the system with a load impedance and for providing an output voltage at the output corresponding to a buffered indication of the corresponding analog voltage. The means for converting and the means for actively matching share at least one component in the integrated on-chip system.

Another embodiment of the present invention provides a method for driving a video signal to an output. The method includes converting a digital input signal, by a first on-chip converter, to a corresponding analog current based on a reference current. The analog current is converted, by an on chip current-to-voltage converter, to a corresponding analog voltage at a feedback node based on a voltage across an on-chip resistor. Impedance at the output is actively matched, by on-chip circuitry, and providing an analog output voltage at the output by buffering the corresponding analog voltage at the feedback node to the output.

DETAILED DESCRIPTION

FIG. 1depicts a block diagram of a video system10according to an aspect of the present invention. The system10includes a digital-to-analog converter (DAC)12that converts a digital input signal14to a corresponding analog output signal16. For instance, the input signal14can be a multi-bit video signal having N bits, where N is a positive integer (e.g., N=10 or more bits), according to performance and specification requirements. The input signal14can be generated by a video encoder, which can be implemented within the same integrated circuit as the DAC12and an output circuit18. The DAC12can be implemented as a current steering DAC that provides the output signal as a corresponding analog current (IDAC).

The output circuit18can be implemented as a video driver that is configured to perform current-to-voltage conversion of the IDACsignal as well as to perform active impedance matching at an output20thereof. The output circuit18provides an analog output voltage (VOUT) to drive a load (not shown) that is coupled at an output thereof. The output signal VOUTcorresponds to the input current IDACthat is provided by the DAC12. As shown inFIG. 1, the output circuit18includes a current-to-voltage converter22. For example, the current-to-voltage converter22can be implemented as a loop that converts the analog current IDACto a corresponding voltage at an internal node thereof. Active termination circuitry24is configured to synthesize an output impedance at the output20that substantially matches a load impedance to which the output is coupled. For example, the active termination circuitry24can be a hybrid circuit configured to match the output impedance at20with a line impedance (e.g., about 75Ω).

As schematically indicated at26, part of the active termination circuitry24is shared by the current-to-voltage converter22, thereby achieving additional efficiencies in fabrication. For example, the current-to-voltage conversion can be implemented across an integrated resistor (e.g., an NWELL resistor in a CMOS process), which resistor also forms part of the active termination circuitry24. Advantageously, the active termination circuitry24can be designed so as not to consume power, but still provide an output impedance that is substantially equal to the load impedance. Such active impedance matching can avoid reflections from the load at high frequencies like the video frequencies.

The system10can be implemented as a system on chip (SOC), including the DAC12and at least a substantial portion of the output circuit18. The on-chip integration of the current-to-voltage conversion and active impedance matching affords advantages in terms of both area and power. The approach shown and described inFIG. 1can also provide large output swing for the high-bandwidth video signal while maintaining excellent linearity. Additional benefits associated with the approach shown and described inFIG. 1will be better appreciated with reference to other example embodiments shown inFIGS. 2 and 3.

FIG. 2depicts a video system50that can be implemented on an IC chip52according to an aspect of the present invention. The system includes a DAC54that provides an analog output current IDACthat varies as a function of a digital INPUT signal56and a predetermined DAC reference current IREF. The DAC reference current IREFcan be set by a resistor RSET. RSETcan be an internal resistance, an external resistance or a combination of internal and external resistances. The digital INPUT can be provided to the DAC54by a video encoder (not shown), such as a multi-bit (e.g., about 10 bits or greater) digital input code according to application requirements.

A current-to-voltage converter, indicated at60, converts IDACto a corresponding voltage VFB. The current-to-voltage converter60can be implemented as a loop includes an op-amp62, transistor M1and a resistor R1. A common mode voltage VCMof the DAC54is provided to the inverting input of the op-amp62and the non-inverting input of the op-amp is coupled to the output of the DAC. The transistor M1is coupled between a voltage rail64and a node66that provides a feedback voltage VFB. The op-amp62drives gates of transistors M1and M2. The transistor M1provides current I3to the node66based on the voltage provided by the op-amp62, which voltage varies as a function of IDAC. The resistor R1is coupled between the output of the DAC54and the node66. The resistor R1performs current-to-voltage conversion based on IDACto provide VFB. The resistor R1can be implemented as an on-chip resistor (e.g., an NWELL resistor in a CMOS process). Alternatively or additionally, the resistor R1could include an external resistance. DC current sources provide (e.g., sink) current I1and I2, respectively, away from the output of the DAC and from the node66.

The video driver system50also includes active termination circuitry70configured to synthesize an output impedance at an output72that substantially matches a load impedance RLto which the output is coupled. The load impedance RL, for instance, corresponds to the impedance of line for a video output (e.g., about 75Ω). The active termination circuitry72can be implemented as a hybrid circuit that includes the transistors M1and M2and resistors R1and R2. The areas of the transistors M1and M2are matched transistors according to a ratio 1:N. The transistors M1and M2of the active termination circuitry72thus can be controlled by the output of the op-amp62to maintain an output impedance that substantially matches the output impedance RL. Other types and configurations of active termination circuits could also be utilized. The performance of the driver system50will vary according to the parameters of the system50.

By way of further example, the current-to-voltage converter60and the active termination circuitry70can be configured to implement a video driver according to design specifications, such as voltage swing at the output72, VOPP, and the DAC peak current, IDAC—PP. The parameters of the other system components can be set based on such specifications, including the mirror ratio of N, DC voltage at VFBand VOand the DC currents of I1, I2. For instance, the video driver system50can be described by the following set of equations:

From the foregoing Eq. 1, the DC transfer function (VO) of the video driver system50can be expressed as follows:

The DC terms in Eqs. 1 and 2, which are dictated by the currents of I1and I2, define the DC operating points at nodes64and72, respectively. Accordingly, by adjusting I1and I2, flexibility in the DC condition can be achieved to optimize the linearity performance of the video driver system50. To provide proper output impedance matching and keep VOand VFBtracking each other, the nominal value for resistors R1and R2can be chosen as a function of N and the load resistance RL, such as follows:
R1=NRL, and   Eq. 3
R2=(N+1)RL.   Eq. 4
Therefore, by appropriate substitution, VFBfrom Eq. 1 and Eq. 2 can be re-written as follows:

Given the swing (peak-peak voltage) of the DAC output, IDACPP, and the desired output voltage swing, VOPP, we can define the value of N by:

N=VOPPIDACPP⁢RLEq.⁢7
It will be appreciated that the system50can be designed with VOand VFBbeing close so as to improve the linearity of the driver. Therefore, combining the DC terms in Eqs. 1 and 2, the values of the DC currents I1and I2can be provided as follows:

where VCMOis the desired DC voltage at the VOand VFBwhen the DAC output current equals 0.

Eqs. 7, 8 and 9 thus can be employed to define a set of design parameters for the video driver system50. It will be appreciated that, non-idealities should be considered in designing the system50since the foregoing derivation has assumed that the amplifier and the current mirror are ideal. The non-linearity of the video driver50can come from various sources, including from the amplifier, the current mirror output driver, the DC bias current source and the integrated NWELL resistors.

Additionally, in practice, current sources I1and I2have finite output impedance, which also introduces non-linearity to the video driver system. For instance, current source I1connect to a virtual ground node and its current output can be treated as constant. However, current source I2sees large signal swing at VFB. Although the I2variation, which is modulated by the signal at VFB, does not introduce non-linearity directly since that variation itself is just a replica of the signal. The DC unbalance due to the disproportion of I1and I2tends introduces non-linearity. Those skilled in the art will appreciate various techniques can be utilized to reduce the non-linearity generated by this and other effects. Other process variations can introduce errors and degrade performance, such as including gain error. In an embodiment where the resistor R1is an NWELL resistor, significant changes in resistor values can occur across temperature and process corners. As one example, in a 65 nm process, the NWELL resistor value can change over ±30% across temperature and processor corners.

To explain the effects of process variations due to variation in the NWELL resistor, the foregoing model of the driver system50is modified in the following discussion. Instead of using the nominal value R1=NRLand R2=(N+1)RLfor R1and R2, by describing R1=MRLand R2=(M+1)RL. Here M deviates from its nominal value N to account for the process and temperature variations. Assuming the current mirror has a fixed gain N, it can be shown that the change in the drain-to-source voltage (ΔVds) between M1and M2can be expressed as follows:

Δ⁢⁢Vds=VO-VFB=(N-M)⁢(M+1)M+N+2⁢RL⁢IDACEq.⁢10
It thus can be shown that the Vdsof the M1and M2are different. Furthermore, ΔVdsis a function of the input signal IDACfrom the DAC. In practice, the ΔVdsgenerates an input dependent current mirror gain variation, which can produce additional non-linearity. The AC input dependent current mirror gain can be represented as follows:

From the foregoing analysis, it can be shown that variation in the load resistance RLintroduces the same effect (e.g., nonlinearity) as does variation in the NWELL resistor R1mentioned above. That is, the variation in RLalso creates an input dependent ΔVds, and hence causes an input dependent current mirror gain. For example, the ΔVdsdue to variation in RLcan be represented as follows:
ΔVds=VO−VFB=ΔRLIDACEq. 12
and the resulting the current mirror gain can be expressed as:

N≈No(1+λ⁢⁢Δ⁢⁢RL⁢IDAC︸Non⁢-⁢linear⁢⁢Term)Eq.⁢13
As mentioned above, the term ΔRLis the variation in the load impedance. In the video driver system50, the signal dependent current mirror gain can also provide a significant source for the non-linearity. A fixed current mirror gain across the signal swing over all the process and temperature corners can be implemented to mitigate non-linearity due to current mirror gain.

As shown in the foregoing analysis, the non-linearity of the current mirror gain is created by the signal dependent ΔVds. In both Eqs. 11 and 13, it is shown that the current mirror gain variation is determined by two terms, ΔVdsand λ. Therefore, two methods can be employed to mitigate the gain variation. For instance, trimming can be utilized to track variation in the NWELL resistor or load resistance. In that way, ΔVdscan be forced to be negligible. A second approach is to reduce λ, such that the current mirror gain becomes insensitive to the ΔVds.

FIG. 3depicts another example embodiment of a video system100that can implement an analog video driver102according to an aspect of the present invention. The driver102is similarly configured to the approach ofFIG. 2, but also includes additional circuitry104to improve linearity. The circuitry104can be implemented as a regulated (e.g., a gate-boost) current mirror. Additionally, the system102includes circuitry106to mitigate gain error in the system. For sake of consistency of explanation, the circuitry104and106will be described in the context of various components that are represented by many reference characters previously introduced with respect toFIG. 2.

The system100thus includes a current DAC110that is configured to provide an analog output current IDACthat varies as a function of a digital INPUT signal112and a predetermined DAC reference current IREF. The DAC reference current IREFcan be set according to the configuration of the circuitry106.

In the illustrated example ofFIG. 3, the driver102includes an op-amp116that drives gates of transistors M1and M2based on the IDACcurrent. The areas of the transistors M1and M2are matched transistors according to a ratio 1:N. A common mode voltage VCMof the DAC110is provided to the inverting input of the op-amp116, and the non-inverting input is coupled to the output of the DAC. The regulated current mirror104is coupled between the transistors M1and M2and respective nodes120and122. In particular, transistor M1is coupled in series with transistor M3of the regulated current mirror104between a voltage rail118and the node120. A feedback voltage VFBis provided at120based on the voltage drop across the resistor R1and IDAC. Transistor M2is coupled in series with transistor M4of the regulated current mirror104between the voltage rail118and the node122, where node122defines an output of the driver that provides the output voltage VOUT. The regulated current mirror104also includes op-amps124and126that drive the gates of M3and M4, respectively, based on a reference voltage (from the DAC110) relative to the drain voltages provided respectively by M1and M2. The current mirror circuitry104thus provides regulated currents I3and I4to the nodes120and122.

A resistance R1is coupled between the output of the DAC110and the node120. A second resistance R2is coupled between nodes120and122. In the illustrated example, the resistor R1is depicted as an internal resistance (e.g., an NWELL resistor) and the resistor R2as an external resistor. It is to be understood that each of the resistors R1and R2could be implemented as internal resistances, external resistances or a combination of internal and external resistances. For purposes of consistency, the following discussion assumes that R1is implemented as an NWELL internal resistance. DC current sources130and132provide DC currents I1and I2.

Linearity in the system100can be improved due to the regulation of current by the gate-boost current mirror104. From the foregoing example, is can be shown that the λ of the gate-boosting current mirror104is AgmCASRCAStimes smaller than the one of the simple current mirror. Here “A” is the gain of the boost amplifier, gmCASand RCAScorrespond to the transconductance and output impedance of the cascode transistor, respectively. By using the gate-boosting current mirror, total harmonic distortion can be improved significantly (e.g., by about 22 dB). Since the current mirror gain is insensitive to the difference in VOUTand VFBin this structure, it is also substantially immune to the load impedance variation. Those skilled in the art will appreciate that when the gate-boost current mirror is employed in the driver system, R2should be external to ensure the output impedance matching. This is because the output impedance of the hybrid driver is given can be expressed as follows:

RO=R2N+1Eq.⁢14
The large variation in the NWELL resistor cannot provide accurate impedance matching that is required in most of the applications.

Another performance consideration relates to the gain variation caused by large variation in the on-chip NWELL resistor. For the gate-boosting current mirror structure, the AC transfer function VOcan be re-written as in Eq. 15, given that external resistor is used for R2, and an NWELL resistor is used for R1. Hence, R2(being external) has a fixed value (N+1)RLand R1=MRL, where M has a nominal value of N and varies with the process and temperature corners as mentioned above.

For the transistor trimming structure, all the resistors are integrated, which provides R1=MRLand R2=(M+1)RL. With trimming, the current mirror gain is also tuned to be M. Therefore, the AC transfer function in this case can be expressed as follows;

Assuming that the NWELL has over ±30% variation across process temperature corners, the value of M can vary significantly. From Eqs. 16 and 17, it is shown that the swing at VOchanges commensurate with the M variation, which results in over ±15% gain error for the gate-boosting current mirror video driver and ±30% gain error for the trimming video driver.

The only other variable in Eqs. 15, 16 and 17 is the input current IDACthat is provided by the DAC110. To mitigate this gain error issue, variation can be introduced into the IDACto compensate the M variation. Since IDACis the output from the DAC, it is a function of the reference current IREFused in the current steering the DAC. By way of example, the input current from the DAC (IDACinFIG. 3) can be expressed as follows:

iI⁢⁢N=Iref8⁢(63+1516)Eq.⁢18
Irefis obtained by applying a fixed voltage from bandgap reference on a reference resistor. Thus, the reference current can be represented as

Iref=VBGRref.
Combining Eqs. 15, 16, 17 and 18, it can be shown that gain error can be substantially cancelled by introducing the same variation factor to the reference resistance that is utilized to generate the reference current.

By way of example, referring back toFIG. 3, the circuitry106can be implemented as a resistance RSETthat includes an NWELL resistor R3in series with a switched-capacitor resistor network134. The switched-capacitor resistor network134provides a substantially constant resistor that exhibits little variation due to temperature and processor variations (as compared to the large variation in NWELL resistance). The circuitry106thus can be configured to compensate for the gain error in the gate-boosting current mirror video driver104. With the series resistance provided by the circuitry106, the reference current IREF becomes:

Iref=VBGRnwell+Rsw,Eq.⁢19
where Rnwellis the varying NWELL resistor and Rswis the constant switched-cap resistor. Both resistors are designed for the same nominal value.

Since all the on-chip NWELL resistors varies in the same direction across the process and temperature corners, Irefcan be re-written as:

Iref=VBG(M+N)⁢RL·K,Eq.⁢20where K is a scaling factor
Irefcan be substituted into Eq. 16 to provide the following transfer function:

Thus, it is shown that by employing an internal NWELL resistance to generate the reference current IREF for the DAC110, the gain error can be substantially cancelled. From simulation, it can be shown that the gain error can be reduced to approximately ±3%. The remaining gain error results form the variation of the switched capacitor, which can be further reduced by careful design and layout for the capacitor.