Low cost power converter for a computer

Method and apparatus for providing a regulated, direct current (DC) output voltage for use in computers. An unregulated voltage source is regulated by a power converter of the present invention that produces the regulated voltage reliably, inexpensively, and without requiring heat sinks or auxiliary fans. In a preferred embodiment, the power converter includes a buck regulator and a control circuit. The control circuit includes a resistor-divider feedback loop connected to the output of the buck regulator in order to provide a feedback voltage. The feedback voltage is supplied to an error amplifier which compares the feedback voltage to an internal reference voltage and produces an output that is the amplified difference between the two voltages. The amplified output is then provided to a frequency modulation (FM) port of a multipurpose timer. As a result, the timer can control and modulate the frequency and pulse width of the buck regulator.

TECHNICAL FIELD 
The invention relates generally to computers and more specifically, to a 
relatively low cost frequency modulating and pulse width modulating power 
converter for use with computers and the like. 
BACKGROUND OF THE INVENTION 
A power converter is simply a device that converts energy from an input 
source to produce a regulated output source of energy. Although there are 
many types and applications for power converters, one such type is a 
switching, direct current (DC) to DC, step-down power converter, or "buck" 
regulator, for use in computers and the like. 
FIG. 1 illustrates a conventional non-synchronous buck regulator, 
designated generally by the reference numeral 10. The buck regulator 10 
receives an input voltage V.sub.IN and drives an output voltage V.sub.OUT 
and an output current I.sub.OUT for use by a load Z, such that V.sub.OUT 
&lt;V.sub.IN. The buck regulator 10 comprises a switch S1, which is typically 
a field effect transistor ("FET"), a diode D1, an inductor L1 and a 
capacitor C1. A control circuit 12 turns the switch "off" and "on", i.e., 
non-conducting and conducting, respectively, as discussed in greater 
detail below. 
The buck regulator 10 operates on the principle of pulse width modulation 
to provide "point-of-load" voltage regulation. Point-of-load voltage is 
the voltage level directly at the load Z. A voltage V.sub.D1, across the 
diode D1 is manipulated in such a way that the output voltage V.sub.OUT 
maintains the point-of-load voltage at a regulated voltage level. 
The control circuit 12 modulates the switch S1 between "off" and "on" for 
specific periods, or pulses, of time, referred to as pulse width 
modulation ("PWM"). In this way, the control circuit 12 controls the duty 
cycle of the switch S1, and thereby controls the output voltage V.sub.OUT. 
Switching regulators such as the buck regulator 10 have conventionally 
used dedicated PWM chips for the control circuit 12. 
Conventional dedicated PWM chips have only moderate performance responses 
to sharp changes in the point-of-load voltage at the load Z. When the load 
Z has a sharp transient response, it increases the output current 
I.sub.OUT and thereby causes the output voltage V.sub.OUT to sharply fall. 
As a result, the PWM chip must increase the duty cycle so that it may 
rapidly pull the output voltage V.sub.OUT back to the desired 
point-of-load voltage level. 
The PWM chip increases the duty cycle by increasing the "on" time and 
decreasing the "off" time of the switch S1, thereby maintaining a fixed 
frequency. The changes in the duty cycle occur incrementally, i.e., the 
PWM chip can not make large and instantaneous changes in the duty cycle. 
The changes in the duty cycle are also restricted by the fixed frequency 
because the "on" time can not exceed the frequency period. Because of the 
small change in pulse width, the point-of-load voltage and output voltage 
V.sub.OUT will continue to drop until the regulator has sufficiently 
increased the duty cycle. As a result, hard and/or soft errors may occur 
in the load Z, depending on the sensitivity of the load to large swings in 
the point-of-load voltage. 
In addition, dedicated PWM chips are relatively expensive. As a result, one 
solution has been to use linear regulators. Linear regulators are often 
fairly inexpensive and very simple, by contrast, to the buck regulator 10. 
However, linear regulators require substantial heat sinking. Typically, 
for higher power levels, an extruded heat sink is required, even when used 
with an auxiliary fan. Thus while the regulators are low in cost and easy 
to manufacture, they have poor thermal performance. As a result, the cost 
savings from using a linear regulator are expended on thermal management 
using a heat sink and/or auxiliary fan. 
Therefore, what is needed is a power converter such as a buck regulator 
with a control circuit that is relatively inexpensive. 
Furthermore what is needed is a power converter which does not have the 
thermal penalties of a conventional linear regulator. 
Furthermore what is needed is a power converter such as a buck regulator, 
with relatively sharp responses to transients in the point-of-load 
voltage. 
SUMMARY OF THE INVENTION 
The foregoing problems are solved and a technical advance is achieved by a 
low cost method and apparatus for providing a regulated, direct current 
(DC) output voltage for use in computers and the like. An unregulated 
voltage source is regulated by a power converter of the present invention 
that produces the regulated voltage reliably, inexpensively, and without 
requiring heat sinks or auxiliary fans. 
In a preferred embodiment, the power converter includes a buck regulator 
comprising an n-type field effect transistor (FET) switch with the drain 
connected to the unregulated power source and the source connected to a 
diode's cathode. The anode of the diode is connected to a ground supply. 
An inductor is connected between the source of the switch and an output 
node of the power converter and a capacitor is connected between output 
node and ground. 
The power converter also includes a resistor-divider feedback loop 
connected to the output node to provide a feedback voltage. The feedback 
voltage is supplied to a shunt regulator, acting as an error amplifier, 
which compares the feedback voltage to an internal voltage and produces an 
output that is the amplified difference between the two voltages. The 
amplifier output is then provided to a frequency modulation (FM) port of a 
multipurpose timer. The output of the timer is connected to the gate of 
the switch, thereby allowing the timer to control and modulate the 
frequency and pulse width of the switch. 
A technical advantage achieved with the invention is that it provides a 
relatively inexpensive power converter. 
Another technical advantage achieved with the invention is that it provides 
a power converter with sharp responses to transients in the output 
voltage. 
Another technical advantage achieved with the invention is that it provides 
a power converter that does not have the thermal penalties of a 
conventional linear regulator.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
As mentioned above, FIG. 1 schematically represents a conventional, 
non-synchronous, direct current ("DC") to DC step down converter commonly 
referred to as a buck regulator. 
Referring to FIG. 2, the reference numeral 20 refers to a personal 
computer, though it may also refer to a laptop computer, a file server, a 
mainframe computer, or other electrical device. The computer 20 includes 
an alternating current ("AC") to DC power converter 22, a DC to DC power 
converter 24, a power distribution circuit 26, a processing device 28, a 
memory device 30 and a peripheral device 32. The processing device 28, 
memory device 30 and peripheral device 32 are representative of a 
plurality of electronic devices of the computer 20, and are collectively 
represented as a load Z1. 
The AC to DC power converter 22 receives AC power through a power plug 34. 
Although not shown, the power plug 34 connects to a conventional 
electrical outlet. However, the power plug 34, as well as the AC to DC 
power converter 22 may not exist in some applications, such as a laptop 
computer or other battery driven devices. The AC to DC power converter 22 
sources at least three separate DC voltages: a 12V supply, a 5V supply, 
and a 3.3V supply, as well as a 0V or ground supply GND. 
The DC to DC converter 24 and the power distribution circuit 26 receive the 
DC voltages from the AC to DC power converter 22. The DC to DC converter 
24 drives a first voltage V1, which in the present description also 
represents the point-of-load voltage for the load Z1. The power 
distribution circuit 26 drives a second voltage V2. The DC to DC converter 
24 and the power distribution circuit 26 also receive a dual-power signal 
V.sub.DET. The dual-power signal V.sub.DET is a conventional signal that 
allows the DC to DC converter 24 and the power distribution circuit 26 to 
support different voltage requirements of the computer 20. In the 
preferred embodiment, if the load Z1 requires two separate voltages V1, 
V2, such that V1.noteq.V2, then the level of the dual-power signal 
V.sub.DET is set "low." If, however, the load Z1 requires a single voltage 
V1, V2, such that V1=V2, then the dual-power signal V.sub.DET is set 
"high." 
Referring to FIG. 3, the DC to DC power converter 24 uses a multipurpose 
timer 40 to control a switch 42. In the preferred embodiment, the switch 
42 is a field effect transistor ("FET") and the multipurpose timer 40 is a 
conventional "555" timer, such as the LM555 timer manufactured by National 
Semiconductor Company of Santa Clara, Calif. The pin numbers 1-8 shown on 
the timer chip 40 also correspond to the LM555. Trigger, reset and 
threshold levels for the timer chip 40 are configured, as shown, by 
resistors 42, 44 and capacitors 46 connected between the 12V power supply 
and ground GND. Such a configuration of the timer 40 is well known by 
those of ordinary skill in the art and, for the sake of brevity, will not 
be further discussed. 
An output 50 of the timer chip 40 connects to the gate of the FET 42 
through an optional resistor 52. The drain of the FET 42 is tied to the 5V 
power supply, which is decoupled with a capacitor 54. The source of the 
FET 42 and a cathode of a diode 58 are commonly connected to a node A, 
wherein a voltage V.sub.A represents the voltage difference between the 
node A and ground GND. The anode of the diode 58 is connected to ground 
GND. An inductor 60 is connected between the node A and a node B, wherein 
the first voltage V1 represents the voltage difference between the node B 
and ground GND. An output capacitor 62 is also connected between the node 
B and ground GND. 
The first voltage V1 also supports a feedback loop comprising voltage 
divider resistors 64, 66 connected between the node B and ground GND, 
thereby producing a feedback voltage V.sub.FBK at a node C. The feedback 
voltage V.sub.FBK is also selectively responsive to the dual-power signal 
V.sub.DET and circuit 67. If the dual-power signal V.sub.DET is low, the 
circuit 67 has no effect on the feedback voltage V.sub.FBK. If the 
dual-power signal V.sub.DET is high, the circuit 67 places a resistor 68 
in parallel with the resistor 66, thereby reducing the feedback voltage 
V.sub.FBK. 
The feedback voltage V.sub.FBK is supplied to a voltage input 69 of a shunt 
regulator 70, which in the preferred embodiment is a TL431 shunt regulator 
manufactured by National Semiconductor Company of Santa Clara, Calif. The 
shunt regulator 70 serves as an error amplifier, in that it compares a 
voltage on the voltage input 69 with an internal voltage, and amplifies 
the difference accordingly. The shunt regulator 70 used in the present 
invention has an anode connected to ground GND, a cathode connected to a 
node D and an internal reference voltage of about 2.5V. The node D 
connects the shunt regulator cathode to the frequency modulation ("FM") 
port 72 of the timer 40 through a resistor 74. The node D is also pulled 
high by a resistor 76 and supports a control loop compensation network 
comprising a resistor 78 and a capacitor 80 going to the voltage input 69 
of the shunt regulator. 
Referring to FIG. 4, the power distribution circuit 26 receives the first 
voltage V1 and the dual-power signal V.sub.DET to produce the second 
voltage V2. If the dual-power signal V.sub.DET is low, a FET 80, which is 
connected between the 3.3V power supply and the second voltage V2, drives 
the second voltage V2 to about 3.3V. If the dual-power signal V.sub.DET is 
high, two FETs 82, 84 tie the second voltage V2 to the first voltage V1. 
Referring to FIGS. 2-4, in operation, the DC to DC power converter 24 
provides a relatively stable point-of-load voltage for the load Z1. The 
timer 40 drives the output 50 at an initial frequency and duty cycle, as 
determined by the resistors 42, 44 and the capacitor 46. However, if a 
change occurs in the point-of-load voltage, such as one caused by a sudden 
increase in current consumption by the load Z1, the level of the first 
voltage V1 will drop. 
The shunt regulator 70 works to compensate for the drop in the first 
voltage V1 by comparing the feedback voltage V.sub.FBK with an internal 
feedback voltage and amplifying the difference therebetween. Whenever the 
first voltage V1 drops, the feedback voltage V.sub.FBK also drops. 
Therefore, as the feedback voltage V.sub.FBK changes, the shunt regulator 
70 output at node D changes at an amplified rate. 
The shunt regulator 70 controls the FM port 72 of the timer 40. Because the 
shunt regulator 70 provides a fast and broad range of change in the 
voltage level of node D, both the frequency and the pulse width of the 
timer output 50 are modulated. In response, the "on" time, or pulse width, 
of the FET 42 can be increased past the original frequency period of the 
FET. By modulating both the pulse width and frequency, the combination of 
both the shunt regulator 70 and timer 40 cause the output voltage 
V.sub.OUT to quickly regain the original point-of-load voltage level. 
Referring also to FIGS. 1 and 5, the performance of the present invention 
is dramatically improved over that of the prior art buck regulator 10 of 
FIG. 1, as shown by three graphs 90, 92, and 94. For example, if at a time 
t1 the load Z1 begins to consume a great deal of current, the first 
voltage V1 of the present invention only drops to a voltage level 100. 
However, in the prior art buck regulator 10, the output voltage V.sub.OUT 
drops to a lower voltage level 102. In addition, at a time t2 when the 
point-of-load voltage reaches its desired voltage level, the output 
voltage V.sub.OUT overshoots the desired voltage level, as compared to the 
first voltage V1 of the present invention. The improved performance of the 
present invention is due to the responsiveness of the timer 40, with 
respect to the shunt regulator 70, over that of the conventional control 
circuit 12. 
The graph 92 illustrates the switching performance of the switch S1 of the 
prior art buck regulator 10. The control circuit 12 is limited to the 
fixed frequency .function. as well as small incremental changes in pulse 
width "on" time of the voltage V.sub.D1. As a result, at the time t1, the 
pulse width "on time" of the switch S1 is only slightly increased, and can 
never exceed the length of the frequency period. As a result, the output 
voltage V.sub.OUT drops to the voltage level 102. In addition, at the time 
t2, the pulse width "off time" of the switch S1 is only slightly 
decreased, so that the output voltage V.sub.OUT rises above the voltage 
level 102. 
The graph 94 illustrates the performance of the DC to DC power converter 24 
of the present invention. The timer 40 is not limited to a fixed 
frequency, but supports frequency modulation such as f1, f2, f3, f4, f5, 
f6 wherein f1.noteq.f2, f2.noteq.f3, f3.noteq.f4, f4.noteq.f5, and 
f5.noteq.f6. Not being bound to a fixed frequency, the "on time" of the 
voltage V.sub.A is capable of relatively large incremental changes. For 
example, an on-time t3 of the voltage V.sub.A immediately after the time 
t1 is greater than both the on-time t4 and off-time t5 immediately 
preceding the time t1. Likewise, an off-time t6 immediately after the time 
t2 is greater than both the off-time t7 and the on-time t8 immediately 
preceding the time t2. As a result, the present invention provides a 
voltage regulator that is more responsive to changes in the point-of-load 
voltage, thereby allowing the first voltage V1 to only drop to the voltage 
level 100 and to only rise slightly above the desired voltage level. 
In summary, the DC to DC power converter 24 of the present invention 
provides a more reliable point-of-load voltage for the load Z1 than that 
of the prior art. Furthermore, because the timer 40 and the shunt 
regulator 70 have a combined cost of about one-fifth that of the dedicated 
control chip of the prior art, the present invention is relatively 
inexpensive. Finally, the present invention does not have the thermal 
considerations of a linear regulator, and therefore does not require a 
heat sink and/or auxiliary fan. 
Although an illustrative embodiment of the invention has been shown and 
described, other modifications, changes, and substitutions are intended in 
the foregoing disclosure. In addition, portions of the preferred 
embodiment, such as circuits and components associated with the dual-power 
signal V.sub.DET and the second voltage V2, can be removed or modified, 
while still utilizing the present invention. Accordingly, it is 
appropriate that the appended claims be construed broadly and in a manner 
consistent with the scope of the invention.