Memory devices and methods of forming memory devices

A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

TECHNICAL FIELD

The present disclosure relates generally to memory devices, and methods of forming the memory devices.

BACKGROUND

Non-volatile memory devices are often used in consumer electronic products such as smart phones and tablets. One type of non-volatile memory device is the resistive random access memory (RRAM) device. A RRAM device typically uses a switching element such as a dielectric element sandwiched between two electrodes. The switching element is normally insulating. However, upon application of a sufficiently high potential difference (set voltage/switching voltage) between the electrodes, conducting filaments may be formed within the switching element. The switching element thus becomes conductive via the conducting filaments. The switching element can be made insulating again by applying a sufficiently low voltage difference (reset voltage) to the electrodes to break the conducting filaments. A typical RRAM can switch between states based on the resistance of the switching element. When the switching element is insulating, the switching element has a high resistance, and the RRAM may be referred to as being in a high resistance state (HRS). When the switching element is conductive, the switching element has a low resistance and the RRAM may be referred to as being in a low resistance state (LRS). To set the RRAM, the RRAM is switched from the HRS to the LRS. To reset the RRAM, the RRAM is switched from the LRS to the HRS.

The fabrication of a memory device, such as a RRAM device, typically involves several processes that may possibly damage parts of the electrodes and the switching element. This may adversely affect the formation of the conducting filaments, and in turn, the performance of the memory device. For example, due to the damage caused during the fabrication process, the resistance of a RRAM device may vary greatly over different switching cycles. Accordingly, it is desirable to provide an improved memory device having reduced damage from manufacturing processes.

SUMMARY

According to various non-limiting embodiments, there may be provided a memory device including: a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

According to various non-limiting embodiments, there may be provided a method of forming a memory device. The method may include providing a base layer; forming an insulating layer over the base layer, where the insulating layer may include a recess having opposing side walls; forming a first electrode along the opposing side walls of the recess; forming a switching element along the first electrode; forming a second electrode along the switching element; and forming a capping layer over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

DETAILED DESCRIPTION

The embodiments generally relate to semiconductor devices. More particularly, some embodiments relate to memory devices, for instance, non-volatile memory devices such as RRAM devices in a non-limiting example. The memory devices may be used in several applications, such as, but not limited to, neuromorphic computing applications and multi-bit applications.

Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “approximately”, “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Further, a direction is modified by a term or terms, such as “substantially” to mean that the direction is to be applied within normal tolerances of the semiconductor industry. For example, “substantially parallel” means largely extending in the same direction within normal tolerances of the semiconductor industry and “substantially perpendicular” means at an angle of ninety degrees plus or minus a normal tolerance of the semiconductor industry.

As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements.

FIG. 1shows a simplified cross-sectional view of a memory device100according to various non-limiting embodiments. The memory device100may include a RRAM device.

As shown inFIG. 1, the memory device100may include a base layer102. The base layer102may be an inter-layer dielectric (ILD) layer and may include insulating material, such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or combinations thereof.

The memory device100may further include an insulating layer104arranged over the base layer102. The insulating layer104may also be an inter-layer dielectric (ILD) layer and may include insulating material, such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride or combinations thereof. As shown inFIG. 1, the insulating layer104may include a top surface104tand a recess106. The recess106may have a bottom surface106band opposing side walls (including a first side wall106s1and a second side wall106s2). The side walls106s1,106s2may be vertical (in other words, may extend substantially perpendicular to the bottom surface106bof the recess106) or may alternatively be slanted at an angle relative to the bottom surface106bof the recess106.

A first blocking layer150may be arranged between the insulating layer104and the base layer102. The first blocking layer150may include blocking material, such as, but not limited to, Nblok (nitrogen-doped silicon carbide).

The memory device100may also include a first electrode108arranged within the recess106of the insulating layer104. The first electrode108may include a base surface108barranged along the bottom surface106bof the recess106and a top surface108tlaterally aligned with the top surface104tof the insulating layer104. Further, the first electrode108may be arranged along the opposing side walls106s1,106s2of the recess106. In particular, the first electrode108may include a first part1081arranged along the first side wall106s1and a second part1082arranged along the second side wall106s2. The first and second parts1081,1082of the first electrode108may be separated from each other. Accordingly, the base surface108band the top surface108tof the first electrode108may each include a gap. The first electrode108may be an inert electrode and may include inert electrode material, such as, but not limited to, tungsten (W), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), alloys thereof, or combinations thereof.

The memory device100may further include a switching element110arranged within the recess106of the insulating layer104and along the first electrode108. The switching element110may include a base surface110barranged along the bottom surface106bof the recess106and a top surface110tlaterally aligned with the top surface104tof the insulating layer104. In other words, the base surfaces108b,110bof the first electrode108and the switching element110may be laterally aligned. Similarly, the top surfaces108t,110tof the first electrode108and the switching element110may be laterally aligned. As shown inFIG. 1, the switching element110may include a first part1101nearer to the first side wall106s1of the recess106and a second part1102nearer to the second side wall106s2of the recess106. The first part1101of the switching element110may be arranged along the first part1081of the first electrode108and the second part1102of the switching element110may be arranged along the second part1082of the first electrode108. The first and second parts1101,1102of the switching element110may similarly be separated from each other. Accordingly, the base surface110band the top surface110tof the switching element110may each include a gap. The switching element110may include switching material, such as, but not limited to, magnesium oxide (MgO), tantalum oxide (TaOx), hafnium oxide (HfOx), titanium oxide (TiOx), aluminum oxide (AlOx), silicon dioxide (SiOx), strontium oxide (SrOx), lanthanide oxide or combinations thereof.

The memory device100may further include a second electrode112arranged within the recess106of the insulating layer104and along the switching element110. In particular, referring toFIG. 1, the second electrode112may include a liner arranged along the switching element110, where the ends112eof the liner may be laterally aligned with the top surfaces108t,110tof the first electrode108and the switching element110. The liner may also extend into and across the first blocking layer150between the first and second parts1101,1102of the switching element110. The liner may be thin with its thickness ranging from about 5 nm to about 15 nm. This may help to reduce the amount of electrode material used for fabricating the memory device100, and hence, the cost of this fabrication. The second electrode112may be an active electrode and may include active electrode material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), alloys thereof, or combinations thereof.

The memory device100may further include a conductive member114arranged at least partially within the recess106, where the conductive member114may adjoin the second electrode112. As shown inFIG. 1, the conductive member114may include a conductive layer116and a conductive region118. The conductive layer116may be arranged along an entire length of the second electrode112, and the conductive region118may be arranged over the conductive layer116to fill the remaining portion of the recess106. InFIG. 1, the conductive member114is depicted as being partially within the recess106with a portion of the conductive layer116extending into the first blocking layer150, but the conductive member114may alternatively be entirely within the recess106. The conductive layer116and the conductive region118may each include conductive material such as, but not limited to, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, cobalt, alloys thereof, or combinations thereof. For example, the conductive layer116may include tantalum, tantalum nitride or cobalt, and the conductive region118may include copper. Alternatively, the conductive layer116may include titanium or titanium nitride, and the conductive region118may include tungsten. InFIG. 1, the conductive layer116and the conductive region118are shown as including different materials, but in alternative non-limiting embodiments, the conductive layer116and the conductive region118may include a same material.

The memory device100may also include a capping layer120arranged over the recess106of the insulating layer104. As shown inFIG. 1, the capping layer120may extend continuously over the recess106. The capping layer120may at least partially overlap the first electrode108, the switching element110and the second electrode112. In particular, referring toFIG. 1, the capping layer120may extend laterally across an entire width W106of the recess106. Accordingly, the capping layer120may overlap the entire top surfaces108t,110tof the first electrode108and the switching element110and the ends112eof the second electrode112, and may also overlap the conductive member114. The capping layer120may include an oxide layer, where the oxide layer may include an oxide of a material of at least one of the first electrode108and the second electrode112. For example, if the first electrode108includes titanium nitride and the second electrode112includes tantalum, the oxide layer may include at least one of titanium oxy-nitride and tantalum oxide. The oxide layer may further include an oxide of a material of the switching element110, an oxide of a material of the conductive layer116, an oxide of a material of the conductive region118or a combination thereof. A thickness T120of the capping layer120may be greater than or equal to 1 nm. For example, the thickness T120of the capping layer120may range from about 1 nm to about 15 nm.

As shown inFIG. 1, the memory device100may also include a further insulating layer122arranged above the insulating layer104. The further insulating layer122may be an inter-layer dielectric (ILD) layer and may include insulating material, such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or combinations thereof. The further insulating layer122, the insulating layer104and the base layer102may include a same material, but alternatively, at least two of these layers102,104,122may include different materials.

The memory device100may further include an intermediate layer124arranged between the insulating layer104and the further insulating layer122. As shown inFIG. 1, a base124bof the intermediate layer124may be laterally aligned with the base120bof the capping layer120, and a thickness T124of the intermediate layer124may be approximately equal to the thickness T120of the capping layer120. However, the thickness T120of the capping layer120may alternatively be less than the thickness T124of the intermediate layer124. The intermediate layer124may include a second blocking layer152and a protective layer154arranged over the second blocking layer152. A thickness T154of the protective layer154may be greater than 5 nm. For example, the thickness T154of the protective layer154may range from about 5 nm to about 15 nm. A thickness T152of the second blocking layer152may be equal to or less than a thickness T150of the first blocking layer150. The second blocking layer152may include a blocking material, such as, but not limited to, Nblok (nitrogen-doped silicon carbide). The protective layer154may include an oxide layer. For example, the protective layer154may include an oxide of a protective material, such as, but not limited to, silicon dioxide (SiO2), silicon oxynitride (SiON), or combinations thereof.

The memory device100may also include a plurality of contacts including a first contact126, a second contact128, a third contact130, a fourth contact132, a fifth contact134and a sixth contact136. The memory device100may also include a plurality of connectors including a first connector138, a second connector140, a third connector142and a fourth connector144. As shown inFIG. 1, the first contact126and the second contact128may be arranged within the base layer102and may be electrically isolated from each other by part of the base layer102. The first contact126may contact the second electrode112; whereas, the second contact128may be electrically connected to the third contact130by the first connector138. In particular, the third contact130may be arranged within the insulating layer104and the first connector138may extend from the third contact130to the second contact128, through the insulating layer104and the first blocking layer150. The third contact130may in turn be connected to the fourth contact132by the second connector140, where the second connector140may extend between the third and fourth contacts130,132through the further insulating layer122, the protective layer154and the second blocking layer152. In addition, as shown inFIG. 1, the fifth contact134may be electrically connected to the first part1081of the first electrode108by the third connector142; whereas, the sixth contact136may be electrically connected to the second part1082of the first electrode108by the fourth connector144. The fifth and sixth contacts134,136may be arranged within the further insulating layer122and the third and fourth connectors142,144may extend through the further insulating layer122, the protective layer154and the second blocking layer152into the insulating layer104.

As mentioned above, a first blocking layer150may be arranged between the insulating layer104and the base layer102, and a second blocking layer152may be arranged between the further insulating layer122and the insulating layer104. The first blocking layer150may help to reduce the amount of diffusion of conductive material from the second contact128into the insulating layer104; whereas, the second blocking layer152may help to reduce the amount of diffusion of conductive material from the third contact130, the conductive layer116and the conductive region118into the further insulating layer122. The first and second blocking layers150,152may be optional. For example, the first blocking layer150may be omitted and the second electrode112may extend along the bottom surface106bof the recess106.

FIGS. 2A to 2Mshow simplified cross-sectional views that illustrate a method for fabricating the memory device100according to various non-limiting embodiments. For clarity of illustration, some reference numerals have been omitted fromFIGS. 2A to 2M.

Referring toFIG. 2A, the method may include providing the base layer102, and forming the first and second contacts126,128within the base layer102. For example, insulating material may first be deposited over a surface on which the memory device100is to be formed and then etched to form openings. The openings may subsequently be filled with conductive material to form the contacts126,128within the base layer102. The method may further include depositing first blocking material200over the base layer102.

Referring toFIGS. 2B, 2C and 2D, the method may further include forming the insulating layer104. As shown inFIG. 2B, insulating material may be deposited over the base layer102, in particular, over the first blocking material200. In particular, first insulating material202amay be deposited and may then be etched, together with the first blocking material200to form an opening. Thereafter, conductive material may be deposited into the opening to form the first connector138. Second insulating material202bmay then be deposited over the first insulating material202aand subsequently etched to form an opening. Conductive material may then be deposited into this opening to form the third contact130. As shown inFIG. 2C, the method may further include depositing second blocking material204and protective material206over the second insulating material202b, with the protective material206arranged over the second blocking material204. As shown inFIG. 2D, the method may further include etching the first and second insulating materials202a,202b, the second blocking material204and the protective material206. The insulating layer104having the recess106may thus be formed over the base layer102(in particular, over the first blocking material200), with the second blocking material204and the protective material206thereabove.

Referring toFIG. 2E, the method may further include depositing electrode material208over the insulating layer104(in particular, over the protective material206) and into the recess106, such that the electrode material208may line the side walls106s1,106s2and the bottom surface106bof the recess106.

Referring toFIG. 2F, the method may further include removing a part of the electrode material208over the protective material206and along the bottom surface106bof the recess106. This may be done using an etching process, such as, but not limited to, a spacer etch process.

Referring toFIG. 2G, the method may further include depositing switching material210over the protective material206and into the recess106, such that the switching material210may line the electrode material208and the bottom surface106bof the recess106.

Referring toFIG. 2H, the method may further include removing a part of the switching material210over the protective material206and along the bottom surface106bof the recess106. This may be done using an etching process, such as, but not limited to, a spacer etch process.

Referring toFIG. 2I, the method may further include etching the first blocking material200to form the first blocking layer150with a gap150gvertically aligned with the recess106. For clarity of illustration, the gap150gis not labelled in the other figures.

Referring toFIG. 2J, the method may further include depositing an electrode liner212over the protective material206and into the recess106such that the electrode liner212may line the switching material210. As shown inFIG. 2J, the electrode liner212may extend into and across the first blocking layer150(in particular, the gap150gof the first blocking layer150). The method may also include depositing a conductive liner214such that the conductive liner214may line the electrode liner212. In addition, the method may include depositing conductive material216over the conductive liner214and into the recess106, such that the conductive material216may fill the remaining part of the recess106.

Referring toFIG. 2K, the method may further include removing an upper portion of each of the conductive material216, the conductive liner214, the electrode liner212, the protective material206, the switching material210and the electrode material208. This may be done using a planarization process, such as, but not limited to, a chemical mechanical polishing (CMP) process. As shown inFIG. 2K, a portion of the protective material206above the second blocking material204may remain. A thickness T206of this remaining portion of the protective material206may be greater than 5 nm. For example, a thickness T206of this remaining portion of the protection material206may range from about 5 nm to about 15 nm.

Referring toFIG. 2L, the method may further include forming the capping layer120, the first electrode108, the switching element110, the second electrode112, the conductive layer116and the conductive region118with a single oxidisation process. In particular, the method may include forming the capping layer120over the recess106by oxidising a top part of each of the conductive material216, the conductive liner214, the electrode liner212, the switching material210and the electrode material208extending above the recess106. The oxidised parts of these materials208,210,212,214,216may form the capping layer120; whereas, the remaining parts of these materials208,210,212,214,216may form the first electrode108, the switching element110, the second electrode112, the conductive layer116and the conductive region118, respectively. The oxidising of the top part of each of the materials208,210,212,214,216may further oxidise the protective material206to form oxidised protective material218. A thickness T218of the oxidised protective material218may be equal to the thickness T206as mentioned above. Alternatively, the thickness T218may be greater than the thickness T206as the oxidisation process may convert a top portion of the second blocking material204to become a part of the oxidised protective material218. In this case, the resulting second blocking layer152may have a thickness T152less than a thickness T150of the first blocking layer150.

Referring toFIG. 2M, the method may further include depositing third insulating material over the oxidised protective material218. The method may also include etching the third insulating material, the oxidised protective material218, the second blocking material204and the insulating layer104to form openings. These openings may then be filled with conductive material to form the second, third and fourth connectors140,142,144. The remaining oxidised protective material218and the remaining second blocking material204may form the protective layer154and the second blocking layer152, respectively. The method may also include depositing fourth insulating material over the third insulating material, and etching the fourth insulating material to form openings. These openings may then be filled with conductive material to form the fourth, fifth and sixth contacts132,134,136. The remaining third and fourth insulating material may then form the further insulating layer122.

The above described order for the method is only intended to be illustrative, and the method is not limited to the above specifically described order unless otherwise specifically stated.

In use, when a sufficiently high potential difference is applied between the first part1081of the first electrode108and the second electrode112(e.g. using the first and fifth contacts126,134), conducting filaments may be formed therebetween within the first part1101of the switching element110. Similarly, when a sufficiently high potential difference is applied between the second part1082of the first electrode108and the second electrode112(e.g. using the first and sixth contacts126,136), conducting filaments may be formed therebetween within the second part1102of the switching element110. The formation of the conducting filaments between the first part1081of the first electrode108and the second electrode112may be independent from the formation of the conducting filaments between the second part1082of the first electrode108and the second electrode112. The memory device100may thus function as a two-bit memory device.

The process (for example, CMP process) for removing the upper portion of each of the materials208,210,212as described with reference toFIG. 2Kmay damage a top part of one or more of these materials208,210,212. Oxidising the top part of each of these materials208,210,212extending above the recess106may help to confine the formation of the conducting filaments to lower parts of the materials208,210,212which are less likely to be damaged. Accordingly, the performance of the memory device100may be improved. In addition, a portion of the protective material206may be retained over the second blocking material204prior to the oxidisation process. This retained portion of the protective material206may help to protect the second blocking material204and in turn, the contact130thereunder from damage during the oxidisation process.