Method of optimizing design for manufacturing (DFM)

The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

BACKGROUND

For example, as a critical dimension (CD) shrinks accompanying increasing IC complexities for more integrated functionality, it is ever more risky financially to manufacture semiconductor devices at advanced nodes. Thus, it is important that early warnings be enabled to detect hot spots of potential faults like openings or bridges in the printed patterns of geometric layouts on wafers. A design for manufacturability (DFM) simulation is design for a software tools for this early detection of potential faults during the design stage. Accuracy of the DFM simulation is critical to ensure the prediction results for early warnings to have meaningful impacts. Accordingly, what are needed are a method and a system to improve the DFM simulation.

DETAILED DESCRIPTION

Referring now toFIG. 1, a flow chart of a method100for calibrating a design for manufacture (DFM) engine is illustrated according to one or more embodiments of the present disclosure. The method100includes beginning with two operations, such as operation105and operation110. The method100begins at operation105by providing or receiving IC design layout data (or IC design layout pattern) from circuit files from a designer or a customer. The designer can be a separate design house or can be part of a semiconductor fabrication facility (fab) for making IC devices according to the IC design layout. In various embodiments, the semiconductor fab may be capable of making photomasks, semiconductor wafers, or both. The IC design layout includes various geometrical patterns designed for an IC product and based on a specification of the IC product.

The IC design layout is presented in one or more data files having the information of the geometrical patterns. In one example, the IC design layout is expressed in a “gds” format. The designer, based on the specification of the product to be manufactured, implements a proper design procedure to carry out the IC design layout. The design procedure may include logic design, physical design, and/or place and route. As an example, a portion of the IC design layout includes various IC features (also referred to as main features), such as active region, gate electrode, source and drain, metal lines and vias of an interlayer interconnection, and openings for bonding pads, to be formed in and on a semiconductor substrate (such as a silicon wafer) and various material layers disposed over the semiconductor substrate. The IC design layout may include certain assist features, such as for imaging effect, processing enhancement, and/or mask identification information.

As shown inFIG. 1, the method100also begins at operation110by receiving process data. The process data includes physical models of processes, process tool parameter settings, process recipes setup data, and other model parameters. The process data includes a plurality of parameters to be calibrated or recalibrated. In one embodiment, the process includes depositing a silicon oxide film on a substrate. The parameters of process data of depositing the silicon oxide film on the substrate include thickness of the silicon oxide, depositing rate, and deposition time, depositing temperature, and chemical composition. In another embodiment, the process includes a chemical mechanical polishing (CMP) process. The parameters of process data of the CMP includes the polishing rate, polishing pressure, polishing time, target thickness and associated step height. In other embodiment, the process includes forming a pattern on the substrate. The process of forming the pattern on the substrate includes coating a resist film on the substrate, exposing the resist film coated on the substrate, developing the exposed resist film to form a resist pattern on the substrate, and etching the resist pattern to form the pattern on the substrate. The parameters of process data of coating the resist film include thickness of the resist film, spin speed, and soft bake temperature. The parameters of process data of exposing the resist film include lens illumination aperture, lens focus offset, exposing dose, and alignment strategy. The parameters of process data of developing the exposed resist film include the post exposure bake temperature and time, and the developing puddle time. The parameters of process data of etching includes etching chemical composition, radio frequency (RF) power and voltage, bias voltage, and etching rate and time. In yet another embodiment, the process includes forming metal layers and vias as interconnects. The parameters of process data of the metal layers and vias include the numbers and types of the metal layers, vias and properties of the insulating layers separating the metal interconnect.

The method100proceeds to operation120for performing a DFM simulation on a DFM engine using the IC design layout data and the process data with a set of parameter settings. The DFM engine includes a computer and software operating the computer and running the DFM simulation. The method100proceeds to operation130for generating an output data. The output data includes all simulation results, for example, a calculated critical dimension (CD) of a feature or a calculated thickness of a film deposited on the wafer by the simulation, generated on the DFM engine for the given set of parameter settings, for example, the exposing dose, the etching rate and time, or a film depositing time.

The method100proceeds to operation140for optimizing the DFM simulation. At operation140, the method100also includes receiving measurement data obtained at operation150. The measurement data includes actual measurements from a processed wafer. The wafer is processed by a process and/or an operation unit on a tool. The measurement data may include an actual critical dimension (CD) of a feature on the wafer or an actual thickness of a film deposited on the wafer. In some embodiments, the output data at operation130and the measurement data at operation150may be converted to a common format, for example, ASCII format or CSV format, for general portability across computing platforms.

As shown inFIG. 1, the optimizing simulation at operation140executes by using an optimization engine. The optimization engine is constructed on a computing platform, for example, on MS-Windows or on Linux. The optimization engine may use another computing platform or share a common computing platform with the DFM engine. The optimizing simulation at operation140includes integrating three sub-operations, such as evaluating the simulation output data and the measurement data on the wafer, making a decision based on the evaluation, and adjusting the parameter settings for the DFM engine based on the decision. In some embodiments, an adjusted parameter setting is also referred to as a calibrated parameter setting. The calibrated parameter setting is sent to operation105again to set a new set of parameter settings for the process data. The process data with the new set of parameter settings is sent to operation120to perform the DFM simulation using the new parameter settings. A new output data is generated at operation130using the calibrated parameter settings. The new output data is sent to operation140for optimizing the simulation. The new set of parameter settings is re-calibrated. This cycle can be performed many times until the parameter settings are well tuned and optimized, and a satisfactory DFM simulation output data is generated. Additional operations can be provided before, during, and after the method100, and some the operations described can be replaced, eliminated, or moved around for additional embodiments of the method100.

In one embodiment, the DFM engine and the optimization engine can exist on the same computing platform, for example, LINUX. A supervisory architecture integrates the entire calibration process and takes control of the data flows with two engines serving as function providers. In another embodiment, the DFM engine and the optimization engine are constructed on different computing platforms, for example, the DFM engine on MS-WINDOW and the optimization engine on LINUX. A supervisory loop is constructed for managing distributing computing services and data across the different platform.

Referring now toFIG. 2, a sequence200of calibration procedure of the supervisory layer in the method100is illustrated according to one or more embodiments. The sequence200includes an outer loop220, a middle loop240, and an inner loop260. The outer loop220includes multiple parameters k, k={1 . . . n}, for each calibration. The middle loop240includes multiple steps m, m={m1, m2 . . . }, for each parameter k. The inner loop260includes multiple levels of resolution grid (minimum increment change in a parameter setting) n, n={n1, n2,}, for each step m. In some embodiments, each parameter k is divided into m steps for middle level calibration. Each step m is divided into n grids for fine calibration. System architecture of the optimization engine is built to enable three tiers of the outer loop220, middle loop240, and inner loop260to be calibrated in single parameter for sequential calibration or multiple parameters for parallel calibration. More nested loops may be added for other instantiations of the supervisory architecture concerning the exact numbers of recipe steps, resolution grids, and other factors of importance.

In the present embodiments, a performance index J(Φ;ω) of the DFM simulation is introduced. The performance index J(Φ;ω) of the DFM simulation is defined as
J(Φ;ω)=Σ∀(x,y){Σ∀kωk·[zk(x,y)−{circumflex over (z)}k(x,y)]2}  Eq. (1)
wherein the (x, y) are coordinates about areas of interests on the wafer, the {circumflex over (z)}(x, y) are output values from the DFM simulation at the point (x, y), z(x, y) are physical measurements from silicon wafer at the point (x, y), Φ is vector of model parameters to be calibrated, Φ0is vector of model parameters optimally calibrated, ω is vector of dynamic weighting of performance index, and J(Φ;ω) is performance index of DFM engine under calibration. The optimization objective is to find Φ0, so that
J(Φ0)≦J(Φ)∀Φ  Eq. (2)
The number of model parameter Φ to be calibrated may rank in thousands. The model parameter Φ may include polishing rate, removing rate, and target thickness in the CMP process; etching rate, etching time, RF power, RF frequency, and bias voltage in the etching process; and resist thickness, exposing dose, bake temperature and time in the lithography process. Some of the model parameters may depend on the individual design of a semiconductor device, process specifications or configuration, or settings of processing equipment.

In one embodiment, the performance index may be defined via mappings between simulation results and silicon data,
{circumflex over (z)}(x,y)=F[z(x,y);θ]  Eq. (3)
J(Φ;ω,θ)=Σ∀kωk·fk(θ)  Eq. (4)
wherein the F[z; θ] is mapping between simulation result and silicon data, the θ is vector of mapping parameters to be optimally tuned, and f(θ) is appropriate cost function for each mapping parameter. This embodiment simplifies the optimization process by summarizing the spatial mapping between the DFM simulation and the silicon data, for example, a linear mapping with coefficient of determination is presented by Eq. (5),
{circumflex over (z)}(x,y)=a·z(x,y)+br2Eq. (5)
in this particular case
θ={a,b,r}  Eq. (6)
Least-square fits may be used to obtain {a, b} and calculate {r} accordingly. Ideally the best fit would give slope a=1 and intercept b=0 with r=1.

In one embodiment, the optimization process may be illustrated by a density profile300. The density profile300is shown inFIG. 3. A performance index J1(ω) may take the form for unconstrained optimization,

J1⁡(ω)=ω·(z1-z^1)T·(z1-z^1)+(1-ω)·(z2-z^2)T·(z2-z^2)Eq.⁢(7)
wherein z1is measured dielectric thickness, z2is measured metal thickness, and {{circumflex over (z)}1, {circumflex over (z)}2} are simulated values of {z1, z2}. Or, a performance index J2(ω) may take the form for constrained optimization by Eq. (5),
J2(ω)=√{square root over (ω·(1−α)2+(1−ω)·(1−r2))}{square root over (ω·(1−α)2+(1−ω)·(1−r2))}{square root over (ω·(1−α)2+(1−ω)·(1−r2))}  Eq. (8)
wherein 0≦ω≦1, and the sample boundary constraints is
a∈1±0.08r2≧0.85

Referring now toFIG. 4, an example of optimizing a parameter p1using the sequence200is presented according to one or more embodiments. As shown inFIG. 4, the example includes optimizing the parameter p1using the performance index J1(ω) by the unconstrained optimization presented in Eq. (7) or using the performance index J2(ω) by the constrained optimization presented in Eq. (8). The example also includes using the sequence200shown inFIG. 2to optimize the parameter p1. First, curves272aand272bare calculated using the outer loop220of the sequence200. Both curves272aand272bgive a range of the parameter p1for the performance index J1(ω) and J2(ω) respectively. Then, curves274aand274bare calculated using the middle loop240of the sequence200based on the range of the parameter p1given by the outer loop220of the sequence200. The curves274aand274bnarrow the range of the parameter p1for the performance index J1(ω) and J2(ω) respectively. Finally, curves276aand276bare calculated using the inner loop260of the sequence200based on the range of the optimal setting of the parameter p1given by the middle loop240of the sequence200. The curves276aand276bfurther narrow the range of the parameter p1for the performance index J1(ω) and J2(ω) respectively.

As shown inFIG. 4, in one embodiment, the optimal performance index J1(ω) of the parameter p1is optimized by choosing a nadir of the curve276a. The performance index J1(ω) is optimized using Eq. (7) by an unconstraint approach. The optimal setting of the parameter p1is determined by locating the nadir of the performance index J1(ω). An optimal range of the parameter p1is also determined by the optimizing process. In another embodiment, the optimal performance index J2(ω) of the parameter p1is optimized by choosing a nadir of the curve276b. The performance index J2(ω) is optimized using Eq. (8) by a constraint approach. The optimal setting of the parameter p1is determined by locating the nadir of the performance index J2(ω). An optimal range of the parameter p1is also determined by the optimizing process. Different embodiments may have different advantages, and no particular advantage is necessarily required for any embodiment.

FIG. 5shows graphs of optimizing a parameter p3using the sequence200is presented according to one or more embodiments. As shown inFIG. 5, the example includes optimizing the parameter m using the performance index J1(ω) by the unconstrained optimization presented in Eq. (7) or using the performance index J2(ω) by the constrained optimization presented in Eq. (8). The example also includes using the sequence200shown inFIG. 2to optimize the parameter p3. First, curves282aand282bare calculated using the outer loop220of the sequence200. Both curves282aand282bgive a range of the parameter p3for the performance index J1(ω) and J2(ω) respectively. Then, curves284aand284bare calculated using the middle loop240of the sequence200based on the range of the parameter p3given by the outer loop220of the sequence200. The curves284aand284bnarrow the range of the parameter p3for the performance index J1(ω) and J2(ω) respectively. Finally, curves286aand286bare calculated using the inner loop260of the sequence200based on the range of the optimal setting of the parameter p3given by the middle loop240of the sequence200. The curves286aand286bfurther narrow the range of the parameter p3for the performance index J1(ω) and J2(ω) respectively. The optimal setting of the parameter p3is determined (or tuned) by either the performance index J1(ω) or by the performance index J2(ω).

As shown inFIG. 5, in one embodiment, the optimal performance index J1(ω) of the parameter p3is optimized by choosing a nadir of the curve286a. The performance index J1(ω) of the parameter p3is optimized using Eq. (7) by the unconstraint approach. The optimal setting of the parameter p3is determined by locating the nadir of the performance index J1(ω) of the parameter p3. An optimal range of the parameter p1is also determined by the optimizing process. In another embodiment, the optimal performance index J2(ω) of the parameter p3is optimized by choosing a nadir of the curve286b. The performance index J2(ω) of the parameter p3is optimized using Eq. (8) by the constraint approach. The optimal setting of the parameter p3is determined by locating the nadir of the performance index J2(ω) of the parameter p3. An optimal range of the parameter p3is also determined by the optimizing process. Different embodiments may have different advantages, and no particular advantage is necessarily required for any embodiment.

Referring now toFIG. 6, a block diagram of a system500for optimizing the DFM simulation is illustrated according to one or more embodiments. The system500includes a data storage system510, a network system540, and a computing system560. The data or file exchanges between the data storage system510and the computing system560through the network system540. The data storage system510includes a plurality of memory units. The data storage system510further includes the IC design data unit512for storing the IC design data, the process data unit514for storing the process data, the measurement data unit516for storing measurement data, and the output file unit518for storing the output file. The IC design data unit512, the process data unit514, the measurement data unit516, and the output file unit518are configured to connect to the network system540respectively. The computing system560includes a DFM engine562and an optimization engine564. The computing system560may include more than one DFM engine562or more than one optimization engine564. The DFM engine562is configured to connect to the network system540. The optimization engine564is configured to connect to the network system540. The DFM engine562may include a computer. The optimization engine may also include a computer. The DFM engine562and the optimization engine564may be constructed on the same common platform (e.g. both on MS-window or LINUX) or constructed on different platform (e.g. one on MS-WINDOW and another on LINUX). The DFM engine562or the optimization engine564may not in pair. The system architecture is very general and not necessarily limited to operating systems of MS-Windows or Linux or Unix)

As shown inFIG. 6, the system500is constructed for parallel computing for optimizing the DFM simulation. The DFM engine562gets input data, such as IC design data, process data including parameter settings, and measurement data, from the data storage system510through the network540. The DFM engine562performs the simulation to the input data and generates the output data. The output data stored in the output data unit518and the measurement data stored in the measurement data unit520are sent to optimization engine564through the network540for optimizing the parameter setting of the process data. The optimized parameter settings of the process data is sent to the DFM engine562again for another cycle optimization. The computation for the simulation and the optimization are performed parallelly using the DFM engine562and optimization engine564by exchanging the data or the file through the network560. The system500can reduce the optimization cycle time significantly. For example, the optimization time for optimizing a DFM engine is about several months using a traditional manual optimizing procedure. The cycle time is reduced to several days using the system500as shown inFIG. 6.

Thus, the present disclosure describes a method of optimizing the DFM simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The method further includes receiving a measurement data. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The generating the performance index of the parameter or the plurality of parameters includes finding the difference between the simulation output data and the measurement data. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters. The performing the DFM simulation includes performing the DFM simulation in sequential order, parallel order, or in combination of both order thereof. The optimizing the DFM simulation includes optimizing the DFM simulation in sequential order, parallel order, or in combination order thereof.

The present disclosure also describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, generating an output data by executing the DFM simulation using the IC design data and the process data, receiving a measurement data using a processed wafer, and optimizing the DFM simulation. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by comparing the output data and the measurement data. The parameter or the plurality of parameters includes steps, and furthermore the step includes levels. The optimizing the DFM simulation includes generating the performance index of the parameter or the plurality of parameters by adjusting the parameter or the plurality of parameters of the process data. The optimizing the DFM further includes locating a nadir of the performance index. The optimizing the DFM simulation includes optimizing in a sequential order, in a parallel order, or in a combination order thereof.

In another embodiment, a system for optimizing a design for manufacture (DFM) simulation is described. The system includes a network system, a data storage system configured to connect the network, and a computing system configured to connect the network. The data storage system includes an integrate circuit (IC) design data unit, a process data unit storing the process data including parameter settings, a measurement data unit, and an output data unit. The computing system includes at least one DFM engine and at least one optimization engine. The DFM engine is designed to perform the DFM simulation using the IC design data and the process data with a set of parameter settings and generating the output data. The optimization engine is designed for generating a performance index of the parameter or the plurality of parameters using the output data and the measurement data and locating a nadir of the performance index of the parameter or the plurality of parameters so that the parameter setting of the process data is optimized.