Systems and methods for DC to DC conversion with current mode control

In one embodiment the present invention includes a DC to DC converter device which includes an electronic circuit. The electronic circuit comprises a first comparator, a second comparator, a first switch, a first latch, and a current sensor. The inductor current includes a peak current value and a valley current value. The first comparator detects the peak current value and resets the first latch which opens the first switch. The second comparator detects the valley current value and sets the first latch which closes the first switch. The current sensor is coupled to sense an inductor current flowing through an output load, and is coupled to provide a sense voltage to the first and second comparators. In this manner, the electronic circuit provides DC to DC conversion with current control.

CROSS REFERENCE TO RELATED APPLICATIONS

Not Applicable

BACKGROUND

The present invention relates to power conversion, and more particularly, to systems and methods for DC to DC conversion with current control.

Power management is extremely important in portable electronic devices due to the limited energy available in a battery supply. Switching regulators have helped improve efficiency and have resulted in extended operating times between recharging of the battery. Switching regulator design and implementation has historically been problematic due to the application requirements for varying load currents and in the difficulty in selecting appropriate compensation to guarantee stability over a range of loads. For example, a switching regulator design may require a narrow range of inductor values in order to operate. Additionally, switching regulators using peak current control methods presently used in the art require additional slope compensation to prevent sub-harmonic oscillation.

The present invention solves these and other problems with systems and methods for DC to DC conversion with current control.

SUMMARY

Embodiments of the present invention improve systems and methods of DC to DC conversion with current control. In one embodiment the present invention includes a DC to DC converter device which includes an electronic circuit. The electronic circuit comprises a first comparator, a second comparator, a first switch, a first latch, and a current sensor. The first comparator has an inverting terminal coupled to receive a first reference signal, a non-inverting terminal, and an output terminal, The second comparator has an inverting terminal, a non-inverting terminal coupled to receive the first reference signal, and an output terminal. The first switch has a first terminal coupled to a first voltage source, a second terminal coupled to an output load, and a control terminal. The first latch has a set terminal coupled to the output of the second comparator, a reset terminal coupled to the output of the first comparator, and an output coupled to the control input of the first switch. The current sensor is coupled to sense an inductor current flowing through the output load, and is coupled to provide a sense voltage to the non-inverting terminal of the first comparator and the inverting terminal of the second comparator. The sense voltage corresponds to the inductor current. The inductor current includes a peak current value and a valley current value. The peak current value is higher than the valley current value. The first comparator detects the peak current value and provides a first component of a first comparator output signal which resets the first latch. The first latch provides a first component of the first latch output signal to open the first switch in response to the first component of the first comparator output signal. The second comparator detects the valley current value and provides a first component of a second comparator output signal which sets the first latch. The first latch provides a second component of the first latch output signal to close the first switch in response to the first component of the second comparator output signal.

In one embodiment, the first switch is a field effect transistor.

In one embodiment, the electronic circuit further comprises a first diode having a first terminal coupled to the output load, a second terminal coupled to a return reference voltage.

In one embodiment, the return reference voltage is ground.

In one embodiment, the electronic circuit further comprises a second switch and a second latch. The second switch has a first terminal coupled to the output load, a second terminal coupled to a return reference voltage, and a control terminal. The second latch has a set terminal coupled to the output of the first comparator, a reset terminal coupled to the output of the second comparator, and an output coupled to the control input of the second switch. The first component of the first comparator output signal sets the second latch. The second latch provides a first component of the second latch output signal to close the second switch in response to the first component of the first comparator output signal. The first component of the second comparator output signal resets the second latch. The second latch provides a second component of the second latch output signal to open the second switch in response to the first component of the second comparator output signal.

In one embodiment, the first switch and the second switch are field effect transistors.

In one embodiment, the electronic circuit further comprises a current limit circuit comprising a third comparator. The third comparator has a non-inverting terminal, an inverting terminal, and an output terminal. The non-inverting terminal is coupled to receive the sense voltage. The inverting terminal is coupled to a current limit reference voltage having a current limit reference voltage value. The output terminal is coupled to provide a third comparator output signal when the sense voltage exceeds the current limit reference voltage value. The third comparator output signal resets the first latch. The first latch provides the first component of the first latch output signal to open the first switch in response to the third comparator output signal. The third comparator output signal sets the second latch. The second latch provides the first component of the second latch output signal to open the first switch in response to the third comparator output signal.

In one embodiment, the electronic circuit further comprises a first voltage reference and a second voltage reference. The first voltage reference has a first terminal coupled to the inverting terminal of the first comparator and a second terminal coupled to receive a first reference signal. The first voltage reference provides a first reference voltage. The second voltage reference has a first terminal coupled to receive the first reference signal and a second terminal coupled to the non-inverting terminal of the second comparator. The second voltage reference provides a second reference voltage. A peak detect threshold comprises the first reference signal and the first reference voltage. A valley detect threshold comprises the first reference signal and the second reference voltage.

In one embodiment, the electronic circuit further comprises a divider circuit, a loop amplifier, and a loop voltage reference. The divider circuit is coupled to receive an output voltage and is coupled to provide a scaled output voltage. The loop amplifier has a non-inverting terminal, an inverting terminal and an output terminal. The inverting terminal is coupled to receive the scaled output voltage, and the output terminal is coupled to provide the first reference signal. The loop voltage reference has a first terminal and a second terminal. The first terminal is coupled to the non-inverting terminal of the loop amplifier and the second terminal is coupled to a return reference voltage. The loop voltage reference provides a loop reference voltage. The loop amplifier generates the first reference signal in which the scaled output voltage matches the loop reference voltage, in accordance therewith provides the output voltage corresponding to the loop reference voltage.

In one embodiment, the loop amplifier is a transconductance amplifier and the electronic circuit further comprises a first resister. The first resistor has a first terminal is coupled to the output of the loop amplifier and a second terminal is coupled a return reference voltage.

In one embodiment, the first reference voltage, the second reference voltage, and the third reference voltage are predetermined.

In one embodiment, the present invention includes a voltage regulator device including an electronic circuit, the electronic circuit comprising a first comparator, a second comparator, a first switch, a first latch, a sense resistor, and a differential amplifier. The first comparator has an inverting terminal coupled to receive a first reference signal, a non-inverting terminal, and an output terminal. The second comparator has an inverting terminal, a non-inverting terminal coupled to receive the first reference signal, and an output terminal. The first switch has a first terminal coupled to a first voltage source, a second terminal coupled to an output load, and a control terminal. The first latch has a set terminal coupled to the output of the second comparator, a reset terminal coupled to the output of the first comparator, and an output terminal coupled to the control input of the first switch. The sense resistor has a first tenninal coupled to the second terminal of the first switch and a second terminal coupled to the output load. The differential amplifier has a first terminal coupled to the first terminal of the sense resistor, a second terminal coupled to the second terminal of the sense resistor, and an output terminal coupled to provide a sense voltage to the non-inverting terminal of the first comparator and the inverting terminal of the second comparator. The sense voltage corresponds to the inductor current. The inductor current includes a peak current value and a valley current value. The peak current value is higher than the valley current value. The first comparator detects the peak current value and provides a first component of a first comparator output signal which resets the first latch. The first latch provides a first component of the first latch output signal to open the first switch in response to the first component of the first comparator output signal. The second comparator detects the valley current value and provides a first component of a second comparator output signal which sets the first latch. The first latch provides a second component of the first latch output signal to close the first switch in response to the first component of the second comparator output signal.

In one embodiment, the present invention includes a method for providing DC to DC conversion comprising the steps of sensing an inductor current, detecting the peak current value, latching a first switch open, detecting the valley current value, and latching the first switch closed. The output load has a peak current value and a valley current value. The peak current value is higher than the valley current value. The inductor current passes through a load. The step of latching a first switch open is in response to detecting the peak current value. The step of latching the first switch closed is in response to detecting the valley current value. The step of latching the first switch open allows the inductor current to decrease to the valley current value. The step of latching the first switch closed allows the inductor current to increase to the peak current value.

In one embodiment, the method further comprises latching a second switch closed in response to detecting the peak current value, and latching the second switch open in response to detecting the valley current value. The step of latching the first switch open and the step of latching the second switch closed allows the inductor current to decrease to the valley current value. The step of latching the first switch closed and the step of latching the second switch open allows the inductor current to increase to the peak current value.

In one embodiment, the method further comprises the steps of scaling an output voltage, amplifying, setting a peak detect level, setting a valley detect level. The step of scaling the output voltage results in a scaled output voltage. The step of amplifying includes amplifying a difference between the scaled output voltage and a first reference voltage. This results in a first reference signal. Setting a peak detect level is based on the first reference signal and a second reference voltage. Setting a valley detect level is based on the first reference signal and a third reference voltage. The first reference voltage, the second reference voltage, and the third reference voltage are predetermined. The step of amplifying generates the first reference signal in which the scaled output voltage matches the first reference voltage, and in accordance therewith providing the output voltage corresponding to the first reference voltage.

DETAILED DESCRIPTION

FIG. 1illustrates an electronic circuit100according to one embodiment of the present invention. The electronic circuit100is configured to act as a buck converter which has current mode control. The electronic circuit utilizes an inductor current peak value and an inductor current valley value to control a switch. Electronic circuit100includes a logic drive circuit123, a switch107, a diode108, a loop amplifier116, a loop voltage reference118, a current sensor120, an inductor110, and an output load121. The logic drive circuit123provides a drive signal which opens and closes switch107. The opening and closing of switch107generates a switching current at the switch node122. The diode108rectifies the switching current such that when the switch107is open, the diode may provide for a current path for an inductor current iLto flow through inductor110, sense resistor109, and the output load121. The logic drive circuit123provides a control input to the switch107. The logic drive circuit123receives a sense voltage from the current sensor120and a reference signal from the loop amplifier116. The loop amplifier116provides a logic drive reference signal such that a scaled output voltage from an intermediate node124of the output load121matches the voltage of the loop voltage reference118, and accordingly the logic drive circuit123provides a control signal which produces an output voltage VOUTacross the output load121which corresponds to the voltage of the loop voltage reference118.

The current sensor120is coupled to sense the inductor current and provide the sense voltage to the logic drive circuit123. The sense voltage corresponds to the inductor current iL. In this embodiment, current sensor120includes a sense resistor109and a differential amplifier119. The inductor current iLis sensed by converting iLinto a small voltage across the sense resistor109and amplifying the small voltage with the differential amplifier119. Amplifier119produces a sense voltage which corresponds to the inductor current iL. Other sense circuitry may be employed to sense the output current including diverting a proportional current of the inductor current iL. A current sensor may also extrapolate the inductor current iLfrom some intermediate current, for example. In one embodiment, the current sensor may be a sense transistor which diverts a proportional current from a switch transistor. The current sensor provides the sense voltage corresponding to the inductor current iL. The sense voltage provides peak current feedback which limits the peak current delivered from the power source VSto the output load121.

The logic drive circuit123includes a comparator101, a comparator102, a voltage reference103, a voltage reference104, and a latch105. The inductor current iLincludes a peak current value and a valley current value, the peak current value being higher than the valley current value. The comparator101detects the peak current value and provides a first component of a first comparator output signal which resets the latch105. The latch105provides a first component of the first latch output signal to open the switch107in response to the first component of the first comparator output signal. The comparator102detects the valley current value and provides a first component of a second comparator output signal which sets the latch105. The latch105provides a second component of the first latch output signal to close the switch107in response to the first component of the second comparator output signal. The logic drive reference signal at node117and the voltage reference103set a peak detect threshold at an inverting tenninal of the comparator101. The sense voltage is provided to a non-inverting terminal of the comparator101and an inverting terminal of the comparator102. The logic drive reference signal at node117and the voltage reference104set a valley detect threshold at an non-inverting terminal of the comparator102.

The inductor current iLflows through the output load and generates the output load voltage VOUT. The the inductor110, sense resistor109, and the output load121are coupled in series. The output load121includes a load resistor111, a load resistor112, a load resistor113, a load resistor115, and a capacitor114. The load resistor111and the load resistor112form a voltage divider and provide the scaled output voltage. The load resistor113, the load resistor115, and the capacitor114form a compensation network. Resistor113and capacitor114may form a electrolytic capacitor in which resistor113represents the effective series resistance (ESR) of the electrolytic capacitor. This may be important for compensation.

The switch107may be a field effect transistor (FET). The switch107may be an NMOS, a PMOS, or an IGBT device. The loop amplifier116may be a transconductance amplifier and an additional impedance network may be added to node117in order to convert the output current from the loop amplifier116to a voltage. The node117may also be coupled to a network to aid in compensation, startup, or both. The loop voltage reference118, the voltage reference103, the voltage reference104, or any combination thereof may be designed with a predetermined value. For example, the loop voltage reference118may be comprised of a band gap reference circuit.

In another embodiment the diode108may be replaced by a rectifying switch. Switch107may be driven by a driver such as an inverter, a buffer, a bootstrapped circuit, or any circuit which may provide the signal required to drive switch107closed and open. A similar driver may be used to drive the rectifying switch as well. Switch107will be closed when the rectifying switch is opened and switch107will be opened when the rectifying switch is closed. The rectifying switch may be a field effect transistor (FET). The rectifying switch may be an NMOS, a PMOS, or an IGBT device.

FIG. 2illustrates a timing diagram200associated with the embodiment ofFIG. 1. Timing diagram200includes an inductor current signal201, a first comparator output signal202, a second comparator output signal203, and a latch output signal204. At point216, the switch107(SeeFIG. 1) closes and the inductor current signal201begins to rise until it reaches the peak current value205at point208. The comparator101detects the peak current value205and provides the first component210of the first comparator output signal202which resets the latch105. The latch105provides a first component211of the latch output signal204to open the switch107in response to the first component210of the first comparator output signal202. The inductor current signal201falls until it reaches the valley current value207at point212. The comparator102detects the valley current value207and provides the first component214of the second comparator output signal203which sets the latch105. The latch105provides a second component215of the latch output signal204to close the switch107in response to the first component214of the second comparator output signal203. Once again the inductor current signal201begins to rise and the cycle repeats.

FIG. 3illustrates a method300according to one embodiment of the present invention.

At301, an inductor current is sensed. The inductor current has a peak current value and a valley current value. The peak current value is higher than the valley current value being a lower current. The inductor current passes through a load. As an example, in the embodiment shown inFIG. 1, current sensor132senses the inductor current iLthrough the output load121.

At302, the peak current value is detected. As an example, in the embodiment shown inFIG. 1, comparator101detects the peak current value. The logic drive reference signal at node117and the voltage reference103set a peak detect threshold at the inverting terminal of the comparator101. The sense voltage is provided to the non-inverting terminal of the comparator101. In this manner, the peak current value is detected.

At303, a first switch is latched open in response to detecting the peak current value. As an example, in the embodiment shown inFIG. 1, comparator101detects the peak current value and provides the first component of the first comparator output signal which resets the latch105, The latch105provides the first component of the first latch output signal to open the switch107in response to the first component of the first comparator output signal.

At304, a second switch is latched closed in response to detecting the peak current value. The latching the first switch open and the latching the second switch closed allows the inductor current to decrease to the valley current value.

At305, the valley current value is detected. As an example, in the embodiment shown inFIG. 1, comparator102detects the valley current value. The logic drive reference signal at node117and the voltage reference104set a valley detect threshold at the non-inverting terminal of the comparator102. The sense voltage is provided to the inverting terminal of the comparator102. In this manner, the valley current value is detected.

At306, the first switch is latched closed in response to detecting the valley current value. As an example, in the embodiment shown inFIG. 1, comparator102detects the valley current value and provides a first component of the second comparator output signal which sets the latch105. The latch105provides a first component of the first latch output signal to open the switch107in response to the first component of the first comparator output signal.

At307, the second switch is latched open in response to detecting the valley current value. The latching the first switch closed and the second switch open allows the inductor current to increase to the peak current value.

At308, an output voltage is scaled resulting in a scaled output voltage. As an example, in the embodiment shown inFIG. 1, the load resistor111and the load resistor112form a voltage divider and provide the scaled output voltage at node124.

At309, a difference between the scaled output voltage and a first reference voltage is amplified which results in a first reference signal. As an example, in the embodiment shown inFIG. 1, loop amplifier116provides the logic drive reference signal such that a scaled output voltage from an intermediate node124of the output load121matches the voltage of the loop voltage reference118, and accordingly the logic drive circuit123provides a control signal which produces an output voltage VOUTacross the output load121which corresponds to the voltage of the loop voltage reference118.

At310, a peak detect level is set based on the first reference signal and a second reference voltage. As an example, in the embodiment shown inFIG. 1, the logic drive reference signal at node117and the voltage reference103set a peak detect threshold at the non-inverting terminal of the comparator101.

At311, a valley detect level is set based on the first reference signal and a third reference voltage. As an example, in the embodiment shown inFIG. 1, the logic drive reference signal at node117and the voltage reference104set a valley detect threshold at the non-inverting terminal of the comparator102.

The first reference voltage, the second reference voltage, and the third reference voltage may be predetermined. The logic drive reference signal establishes an output voltage such that the scaled output voltage matches the first reference voltage. Accordingly, the first reference signal establishes the output voltage which corresponds to the first reference voltage.

FIG. 4illustrates an electronic circuit400according to another embodiment of the present invention. The electronic circuit400is configured to act as a buck converter. However, other types of converter configurations may be implemented as well. Electronic circuit400includes a logic drive circuit431, a switch407, a switch430, a loop amplifier416, a loop voltage reference418, an electrical network436, a current sensor432, an inductor410, and an output load433. The loop amplifier416, the loop voltage reference418, the current sensor432, the inductor410, and the output load433function in a similar manner to corresponding components116,118,132,110, and133in circuit110as described above.

The logic drive circuit431controls both switch407and switch430. Logic drive circuit431includes a comparator401, a comparator402, a voltage reference403, a voltage reference404, a latch405, and a latch429. The comparator4013the comparator402, the voltage reference403, the voltage reference404, the latch405, and the switch407function in a similar manner to corresponding components101,102,103,104,105, and107in circuit100as described above. The switch430operates as a rectifying switch. The switch430replaces the diode108for circuit100described above. The rectifying switch430allows for lower input voltages to be generated at the output. Switch430has a first terminal coupled to a switching node435, a second terminal coupled to a reference voltage, and a control terminal. The latch429has an output coupled to the control input of the switch430, a set terminal coupled to the output terminal of the comparator401, and a reset terminal coupled to the output terminal of the comparator402.

The inductor current iLincludes a peak current value and a valley current value. The peak current value is higher than the valley current value. The comparator401detects the peak current value and provides a first component of a first comparator output signal which resets latch405and sets latch429. Latch405provides a first component of the first latch output signal to open switch407in response to the first component of the first comparator output signal. Latch429provides a first component of the second latch output signal to close switch430in response to the first component of the first comparator output signal. This allows the inductor current iLto decrease.

The comparator402detects the valley current value and provides a first component of a first comparator output signal which sets latch405and resets latch429. Latch405provides a second component of the first latch output signal to close switch407in response to the first component of the second comparator output signal. Latch429provides a second component of the second latch output signal to open switch430in response to the first component of the first comparator output signal. This allows the inductor current iLto decrease. Once again the output current begins to rise and the cycle repeats.

Logic drive circuit431further comprises a current limit circuit comprising a third comparator424and OR gate425. The third comparator424has a non-inverting terminal, an inverting terminal, and an output terminal. The non-inverting terminal is coupled to receive the sense voltage. The inverting terminal is coupled to a current limit voltage reference424. The output terminal is coupled to a first input of the OR gate424. A second input of OR gate424is coupled to the output of comparator401. The output of OR gate424is coupled to the reset terminal of latch405and the set terminal of latch429. Comparator424provides a first component of a third comparator output signal when the sense voltage exceeds a current limit reference voltage value. The first component of the third comparator output signal resets latch405and sets latch429. This third comparator output signal propagates through the OR gate425. Latch405provides a first component of the first latch output signal to open switch407in response to the first component of the third comparator output signal. Latch429provides a first component of the second latch output signal to close switch430in response to the first component of the third comparator output signal. This allows the inductor current iLto decrease.

The electronic circuit400further comprises a pulse frequency modulation (PFM) mode circuit comprising a comparator427, a voltage reference426having a reference voltage V6, and a AND gate428. A non-inverting terminal of the comparator427is coupled to node417. An inverting terminal of the comparator427is coupled to receive the reference voltage V6from voltage reference426. The output of the comparator427is coupled to a first input of the AND gate428. A second input of AND gate428is coupled to the output of the comparator402. The output of the AND gate428is coupled to the set terminal of latch405. Comparator427detects the voltage at node417. Under light load conditions the voltage at node417may fall. When the voltage at node417falls below V6, both switch407and switch430will open. The switching may begin again when the voltage at node417rises in response to the voltage at node434. This pulse frequency modulating mode reduces the overall time the switches (407and430) are switching and therefore may reduce power consumption at light loads. This may also reduce the reverse current flowing through switch430.

The electrical network436includes resistor421, and capacitor422. Resistor421and capacitor422provide compensation to the feed back loop formed when the scaled output voltage is provided to the inverting terminal of loop amplifier416. The loop amplifier416is a transconductance amplifier and electrical network436may aid in converting the current output of the amplifier into a voltage.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims. The terms and expressions that have been employed here are used to describe the various embodiments and examples. These terms and expressions are not to be construed as excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the appended claims.