Screening for reference cells in a memory

Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory.

BACKGROUND

Advances in semiconductor manufacturing processes, digital system architecture, and wireless infrastructure, among other things, have resulted in a vast array of electronic products, particularly consumer products, that drive demand for ever-increasing performance and density in non-volatile memory. One way of increasing the performance and density of non-volatile memories such as, but not limited to, a flash memory, is to shrink the dimensions of transistors that are used in the form of memory cells in flash memories. It is well-recognized that shrinking the physical dimensions of transistors also reduces the size of the storage media itself and thus reduces the amount of charge that can be stored. One drawback of this approach, however, is such systems are more prone to manufacturing defects and larger cell to cell variations. These manufacturing defects and variations affect memory cells and reference memory cells, thereby reducing operation and reliability of the non-volatile memories.

Conventionally, the way in which a reference cell is selected for a given memory is hardware fixed, for example, by the manufacturer. Therefore, once fixed, the selection of a reference cell cannot be changed. Generally, reference cells are selected for a non-volatile memory based on the technology associated with the non-volatile memory. As such, when the conventionally fixed references are affected by manufacturing defects or cell to cell variation, etc., the entire nonvolatile memory fails because certain operations such as, for example, the read operation with respect to any memory cell in the non-volatile memory may not be carried out successfully.

One possible effect on the reference cell due to manufacturing defects is that the reference cell has high random telegraph noise (RTN). In this case, the reference threshold voltage and/or an active reference current level associated with the reference cell are rendered unstable, This leads to unreliable comparison of these levels with corresponding levels associated with a given memory cell of the memory. As a result, certain operations such as, for example, the read operation with respect to the given memory cell in the non-volatile memory may not be carried out successfully.

Another possible effect on the reference cell due to manufacturing defects or cell to cell variation is that the reference cell becomes less robust and less reliable. For example, assume the reference threshold voltage and/or the active reference current level associated with the reference cell may be programmable. In this case, the reference threshold voltage and/or the active reference current level associated with the reference cell may have to be calibrated to a desired level of, for example, 5V. Finally, the reference threshold voltage and/or the active reference current level should be stable so that certain operations such as, for example, the read operation may be carried out successfully. In this case, when the reference cell has been affected by manufacturing defects or cell to cell variation, an increasing number of over-programming and/or over-erasing operations are required to be performed on the reference cell to stabilize the reference threshold voltage at the desired level of 5V. The over-programming operation may be an operation that increases a measured reference threshold voltage when the measured reference threshold voltage is found to be less than the desired level of 5V, and the over-erasing operation may be an operation that reduces the measured reference threshold voltage when the measured reference threshold voltage is found to be greater than the desired level of 5V. However, performing this increased number of over-programming and/or over-erasing operations to stabilize the reference threshold voltage at the desired level of 5V reduces the integrity and stability of the reference cell, thereby making the reference cell less robust and less reliable.

SUMMARY

System, method, and computer program product embodiments for screening reference memory cells in a memory are described herein.

In an embodiment, a system includes a memory and a processor to enable selection of an array from among a plurality of arrays in the memory as a reference array, evaluation of memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repetition of the evaluating to select a second reference cell from within the reference array. The second reference cell is associated with a second operation of the memory, and so on for multiple references.

In another embodiment, a method for screening reference cells in a memory is described. The method operates by selecting an array from among a plurality of arrays in a memory as a reference array, evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating to select a second reference cell from within the reference array. The second reference cell is associated with a second operation of the memory, and so on for multiple references.

DETAILED DESCRIPTION

To address the above issues and others, an embodiment screens memory cells of a memory to select a reference cell, instead of the conventional fixing of the reference cell as discussed above. In an embodiment, the screening of memory cells is conducted after the manufacturing of the memory. The proposed screening may isolate the memory from the above-mentioned issues, and increases the reliability of the reference cells, thereby improving operation of the memory.

FIG. 1illustrates an exemplary memory100comprising memory cells, e.g., in the form of memory cells (e.g., non-volatile memory cells), according to an embodiment. The memory100includes a plurality of memory arrays A1. . . AJ, where J is an integer number. Each memory array includes Wordlines W1. . . WN, which may be connected to respective gates of M number of memory cells, where M is an integer number. For example, the Wordline W1is connected to the respective gates of memory cells W1-1, W1-2. . . W1-M, Wordline W2is connected to the respective gates of memory cells W2-1, W2-2. . . W2-M, and so on. Further, the memory100includes a plurality of Bitlines B0. . . BM, which are connected to respective sources and drains of N number of the memory cells. For example, Bitline B0is connected to respective drains of memory cells W1-1, W2-1. . . WN-1, and is connected to respective sources of memory cells W1-2, W2-2. . . WN-2, Bitline B1is connected to respective drains of memory cells W1-2, W2-2. . . WN-2, and is connected to respective sources of non-volatile memory cells W1-3, W2-3. . . WN-3, and so on. In this way, each of the plurality of memory arrays A1. . . AJ includes M×N number of memory cells. In an exemplary embodiment, a given memory array may have a different number of M memory cells and a different number of N Wordlines with respect to another memory array. In an embodiment, the non-volatile memory cells may include floating gate transistors.

The non-volatile memories include a reference memory cell (hereinafter, reference cell) among the memory cells. Certain operations such as, for example, a read operation related to a memory cell are performed by comparing a threshold voltage level and/or an active conducting current level associated with the memory cell against a corresponding known reference threshold voltage and/or an active reference current level associated with the reference cell under a technology determined electric field. For example, when data stored in a given memory cell is to be read, a threshold voltage (potential) level and/or an active reference current level associated with the given memory cell is compared with a corresponding known reference threshold voltage and/or an active reference current level associated with the reference cell. In an embodiment, when the threshold voltage level and/or the active reference current level associated with the given memory cell is greater than the corresponding known reference threshold voltage and/or the active reference current level associated with the reference cell, the system proceeds to read the data stored in the given memory cell.

The reference threshold voltage and/or current may be sourced from a smaller reference array structure which can be built from memory cells or fixed voltage and/or current sources. Each read operation can be defined with different electric fields across the memory cell and can have its own reference source for fine tuning purposes.

FIG. 2illustrates an exemplary method200for selecting a reference cell according to an embodiment. The method starts at step210. At step220, a reference array is selected from the plurality of memory arrays A1. . . AJ. The reference array is an array from which the reference cell is selected. In an embodiment, the reference array may be selected based on a convenient location of the reference array among the plurality of memory arrays A1. . . AJ in the memory and/or based on technological design preferences related to the memory. In another embodiment, the reference array may be selected randomly.

At step230, the memory cells included in the selected reference array are evaluated and/or screened to determine or select a reference cell. Step230is discussed in greater detail below with respect toFIG. 3.

At step240(which is optional), it is decided whether the selection or determination of a reference cell in step230is to be repeated. For example, in an embodiment, a plurality of reference cells may be selected from among the memory cells included in the reference array, where each of the plurality of reference cells is associated with a corresponding application and/or operation of the memory. In this embodiment, the reference cell determined at step230may be associated with, for example, a read operation of the memory, and the determination of reference cells may be repeated for a write operation, an erase operation, an error correction operation, etc. In another embodiment, even for a given application, the determination of a reference cell may be repeated to determine whether a plurality of memory cells meet the criteria of being selected as reference cells. When a plurality of memory cells meet the criteria of being selected as reference cells, the memory cell having the least deviation from the criteria is selected as the reference cell for the given application. The method ends at step250.

In an embodiment, a reference cell selected in step230is excluded from the evaluation and/or the screening process when step230is repeated by operation of step240. In another embodiment, previously selected reference cells are not so excluded. Further, in another embodiment, parameters associated with determining or selecting the reference cell in step230may be different from parameters associated with subsequently determining or selecting a number reference cell by operation of step240.

FIG. 3illustrates exemplary operation of step230according to an embodiment in greater detail. At step302, a target threshold voltage range and/or a target active current range is determined for a memory cell included in memory100. The target threshold voltage range and/or the target active current range may be based on operating parameters of the memory. For example, when the memory is configured to have an operating threshold voltage range of −1V to 8V, a first target threshold voltage and a second target threshold voltage may be chosen from the operating threshold voltage range of −1 V to 8V, where a difference between the first target threshold voltage and the second target threshold voltage may be the target threshold voltage range. The second target threshold voltage may be greater than the first target threshold voltage. Some non-limiting examples of the target threshold voltage range include −1V to 1V, 0V to 2V, 4V to 8V, −1V to 8V, etc.

Further at step302, first and second target RTN values may also be predetermined. In an embodiment, the RTN value of the memory cell may be a current (or a voltage) associated with, for example, an operation such as reading data from the memory cell. The first and second target RTN values may be a maximum value of RTN that may be acceptable for a reference cell. In an embodiment, the first RTN value may be different from the second RTN value. Some non-limiting examples of the RTN values include 1 μA, 0.5 μA, etc.

At step304, a memory cell is selected from the selected reference array (in step220), and a threshold voltage and/or an active current is measured for the selected memory cell. The measured threshold voltage may be the threshold voltage of a transistor that is used to implement the memory cell under consideration. The measured active current may be a current measured when an operation (e.g., reading, writing, etc.) is conducted on the memory cell under consideration.

At step306, it is determined whether the measured threshold voltage and/or the measured active current are within the target threshold voltage range and/or the predetermined target current range determined in step302, respectively. When the result of the determination at step306is a “Yes,” the method moves to step308. Otherwise, the method moves to step304, and another memory cell from among the memory cells included in the reference array is selected for evaluation. The memory cell under consideration may be excluded from being considered as a reference cell in the future. In another embodiment, the memory cell under consideration may be again evaluated, and also selected as a reference cell in the future.

At step308, the RTN associated with the memory cell under consideration is measured. In one embodiment, multiple measurements of the RTN value associated with the memory cell may be made, and a delta RTN value (ΔRTN) may be calculated. For example, the delta RTN value ΔRTN may be defined by taking a difference between two consecutively measured RTN values from among the multiple measurements. Alternatively, for example, the delta RTN value ΔRTN may be defined by taking a difference between a maximum measured RTN value and a minimum measured RTN value from among the multiple measurements.

At step310, the delta RTN value ΔRTN is compared to the predetermined first target RTN value, and it is determined whether the delta RTN value ΔRTN is less than the predetermined first target RTN value. If it is determined that the delta RTN value ΔRTN is less than the predetermined first target RTN value, then the process moves to step312. Otherwise, the method moves to step304and another memory cell from among the memory cells included in the reference array is selected for evaluation.

In an embodiment, steps308and310are performed to ensure that the calibration process discussed in step312is performed on a memory cell having acceptable RTN value. However, it is within the scope of the present disclosure to omit steps308and310.

At step312, the threshold voltage and/or an active current associated with the memory cell under consideration is calibrated to be closer to a desired threshold voltage and/or a desired active current, respectively. The desired threshold voltage and/or the desired active current may be within the predetermined target threshold voltage range and/or the predetermined target current range, respectively.

At step314, the RTN associated with the memory cell under consideration is re-measured in a similar way as discussed above with respect to step308. In an embodiment, multiple measurements of the RTN value associated with the memory cell may be made, and a re-measured delta RTN value may be calculated. For example, the re-measured delta RTN value may be defined by taking a difference between two consecutively re-measured RTN values from among the multiple re-measurements. Alternatively, for example, the re-measured delta RTN value may be defined by taking a difference between a maximum re-measured RTN value and a minimum re-measured RTN value from among the multiple re-measurements.

At step316, the re-measured delta RTN value is compared to the predetermined second target RTN value, and it is determined whether the re-measured delta RTN value is less than the predetermined second target RTN value. If it is determined that the re-measured delta RTN value is less than the predetermined second target RTN value, then the process moves to step318. Otherwise, the method moves to step302and another memory cell from among the memory cells included in the reference array is selected for evaluation.

In an embodiment, steps314and316are performed to verify that the calibration process conducted on the memory cell under consideration (in step312) has not affected the RTN value associated with the memory cell under consideration. In an embodiment, the predetermined second target RTN value is less than the predetermined first target RTN value

At step318, the memory cell under consideration is selected as a reference cell.

Various embodiments can be implemented, for example, using one or more well-known computer systems, such as computer system400shown inFIG. 4. Computer system400can be any well-known computer capable of performing the functions described herein, such as computers available from International Business Machines, Apple, Sun, HP, Dell, Sony, Toshiba, etc. One or more of the algorithms depicted in the methods illustrated inFIGS. 2 and 3(e.g., selecting a reference array220, selecting a reference array230, repeating determination of the reference cell240, etc.) and their corresponding steps can be executed on one or more distinct computer systems400, or a portion thereof. Furthermore, any functions performed by any of the above features can be implemented on one or more distinct computer systems400.

Computer system400includes one or more processors (also called central processing units, or CPUs), such as a processor404. Processor404is connected to a communication infrastructure or bus406.

One or more processors404may each be a graphics processing unit (GPU). In an embodiment, a GPU is a processor that is a specialized electronic circuit designed to rapidly process mathematically intensive applications on electronic devices. The GPU may have a highly parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data common to computer graphics applications, images and videos.

Computer system400also includes a main or primary memory408, such as random access memory (RAM). Main memory408may include one or more levels of cache. Main memory408has stored therein control logic (i.e., computer software) and/or data.

Computer system400may also include one or more secondary storage devices or memory410. Secondary memory410may include, for example, a hard disk drive412and/or a removable storage device or drive414. Removable storage drive414may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, tape backup device, and/or any other storage device/drive.

Removable storage drive414may interact with a removable storage unit418. Removable storage unit418includes a computer usable or readable storage device having stored thereon computer software (control logic) and/or data. Removable storage unit418may be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, and/any other computer data storage device. Removable storage drive xx14reads from and/or writes to removable storage unit418in a well-known manner.

According to an exemplary embodiment, secondary memory410may include other means, instrumentalities or other approaches for allowing computer programs and/or other instructions and/or data to be accessed by computer system400. Such means, instrumentalities or other approaches may include, for example, a removable storage unit422and an interface420. Examples of the removable storage unit422and the interface420may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card slot, and/or any other removable storage unit and associated interface.

Computer system400may further include a communication or network interface424. Communication interface424enables computer system400to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and collectively referenced by reference number428). For example, communication interface424may allow computer system400to communicate with remote devices428over communications path426, which may be wired and/or wireless, and which may include any combination of LANs, WANs, the Internet, etc. Control logic and/or data may be transmitted to and from computer system400via communication path426.

In an embodiment, a tangible apparatus or article of manufacture comprising a tangible computer useable or readable medium having control logic (software) stored thereon is also referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system400, main memory408, secondary memory410, and removable storage units418and422, as well as tangible articles of manufacture embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices (such as computer system400), causes such data processing devices to operate as described herein.

Therefore, the present disclosure enables screening of memory cells in a memory for designation of stable and reliable memory cells as reference cells and assists in avoiding over-programming and/or over-erasing of levels associated with reference cells. The present disclosure also assists in screening out cells that have, for example, undesirable random telegraph noise (RTN). In this way, the proposed screening improves operation and reliability of the memory.

Conclusion