Active power supply rejection using negative current generation loop feedback

A negative current generator for an amplifier circuit including a shunt transistor, first and second mirror transistors, a current bias device, and an amplifier. The amplifier circuit includes a current source transistor having current terminals coupled between a supply terminal and an input node and a control terminal receiving a bias voltage. The shunt transistor is coupled in a shunt configuration with the current source transistor. Each mirror transistor has a control terminal, a first current terminal coupled to the supply terminal and a second terminal coupled to a voltage node. The control terminal of the first mirror transistor receives another bias voltage. The current bias device draws a constant current from the voltage node. The amplifier has a first input receiving a reference voltage, a second input coupled to the voltage node, and an output coupled to the control terminals of the shunt and second mirror transistors.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power supply rejection, and more particularly to active power supply rejection using negative current generation loop feedback to reduce power supply noise injected into the signal path of amplifiers, filters, reference circuits and the like.

2. Description of the Related Art

The performance and function of many electronic circuits, including amplifiers (particularly open-loop amplifiers), filters, reference circuits, etc., are affected by the stability of the voltage of the power supply. The measure of performance is known as the power supply rejection (PSR). There is an increasing demand to have high rejection of power supply noise in analog and/or digital systems, particularly in communication applications.

Many analog and/or digital applications employ a P-channel metal-oxide semiconductor (PMOS) common gate (CG) amplifier for buffering or amplifying a signal. In this configuration, PMOS current source transistors provide the primary paths for coupling power supply noise to the signal. When biased using a diode-connected mirror transistor and a current source with adequate output resistance, the gate voltage of the PMOS current source transistor tracks the power supply noise. Hence, the power supply noise coupling occurs predominantly through source/bulk voltage fluctuations. The current follows the output conductance “gds” and the bulk-to-drain capacitance (Cbd) and gate-to-drain capacitance (Cgd) paths.

It is desired to counteract power supply noise to improve power supply rejection.

SUMMARY OF THE PRESENT INVENTION

A negative current generator for an amplifier circuit according to an embodiment of the present invention includes a shunt transistor, first and second mirror transistors, a current bias device, and an amplifier. The amplifier circuit includes a current source transistor having a first current terminal coupled to a first supply terminal, a control terminal receiving a first bias voltage and a second current terminal coupled to an input node. The shunt transistor has first and second current terminals for coupling to the first and second current terminals, respectively, of the current source transistor. Each of the first and second mirror transistors has a control terminal, a first current terminal coupled to the first supply terminal and a second terminal coupled to a voltage node. The control terminal of the first mirror transistor receives a second bias voltage. The current bias device is coupled between the voltage node and a second supply terminal and draws a constant current from the voltage node. The amplifier has a first input receiving a reference voltage, a second input coupled to the voltage node, and an output coupled to the control terminals of the shunt and second mirror transistors. The amplifier operates to drive the control terminal of the second mirror transistor to maintain the voltage node equal to the reference voltage.

The shunt transistor and the current source transistor may be equally sized, and the first and second mirror transistors may also be equally sized and scaled relative to the shunt transistor. In a more specific embodiment, the shunt transistor and the first and second mirror transistors may each be P-channel devices or PMOS transistors and the like. The first and second bias voltages may be equal to each other.

An amplifier circuit according to an embodiment of the present invention includes five P-channel devices, first and second bias current devices, and first and second amplifiers. The first P-channel device has first and second current electrodes coupled between a power supply voltage and a dummy node and has a control electrode receiving a first bias voltage. The second P-channel device has first and second current electrodes coupled between the power supply voltage and the dummy node and has a control electrode. The first bias current device is coupled between the dummy node and ground. The first amplifier has a first input receiving a reference voltage, a second input coupled to the dummy node, and an output coupled to the control electrode of the second P-channel device. The third P-channel device has first and second current electrodes coupled between the power supply voltage and an input node and has a control electrode coupled to the output of the first amplifier. The third P-channel device has a conductance that is N times that of the second P-channel device. The fourth P-channel device has first and second current electrodes coupled between the power supply voltage and the input node and has a control electrode receiving a second bias voltage. The fourth P-channel device has a conductance that is N times that of the first P-channel device. The fifth P-channel device has first and second current electrodes coupled between the input node and an output node and has a control electrode. The second bias current device is coupled between the output node and ground. The second amplifier has a first input coupled to the input node, a second input receiving the reference voltage, and an output coupled to the control electrode of the fifth P-channel device.

The P-channel devices may be PMOS transistors or the like. The first and second P-channel devices may be equal in size and the third and fourth P-channel devices may also be equal in size. The first and second P-channel devices may be scaled relative to the fourth and third P-channel devices, respectively. The first and second bias voltages may be equal to each other.

A method of rejecting power supply noise in an amplifier circuit according to an embodiment of the present invention, where the amplifier has a current source transistor with first and second current terminals coupled between a supply terminal and an input node, includes coupling first and second current terminals of a shunt transistor between the supply terminal and the input node, coupling first and second current terminals of a first mirror transistor between the supply terminal and a dummy node, coupling first and second current terminals of a second mirror transistor between the supply terminal and the dummy node, biasing the dummy node with a constant current device, and coupling an amplifier to drive control terminals of the second mirror transistor and the shunt transistor to maintain the dummy node at a predetermined reference voltage level.

The method may include coupling the control terminals of the current source and first mirror transistor to the same bias voltage level. The method may include scaling the first and second mirror transistors relative to the current source transistor and the shunt transistor, respectively, by the same scaling factor. The method may include coupling a source terminal of a PMOS transistor to the supply terminal and coupling a drain terminal of the PMOS transistor to the input node. The method may include coupling a source terminal of a PMOS transistor to the supply terminal and coupling a drain terminal of the PMOS transistor to the dummy node. The method may include coupling a source terminal of a PMOS transistor to the supply terminal and coupling a drain terminal of the PMOS transistor to the dummy node. The method may include coupling a constant current sink between the dummy node and a second supply terminal. The method may include coupling a first input of the amplifier to the predetermined reference voltage level, coupling a second input of the amplifier to the dummy node, and coupling an output of the amplifier to the control terminals of the second mirror transistor and the shunt transistor.

DETAILED DESCRIPTION

The inventor has recognized the need to reduce the power supply noise injected into the signal path in various electronic circuits, such as filters, amplifiers, reference circuits, etc. He has therefore developed a negative current generation loop that uses a shunt current source to inject negative current noise to minimize power supply noise in the signal path.

The sole FIGURE is a schematic diagram of a P-channel metal-oxide semiconductor (PMOS) common gate (CG) amplifier100employing a negative current generation loop implemented according to an exemplary embodiment of the present invention. A supply voltage VDD is provided to the sources of PMOS transistors M1, M2, M3and M4. The gate of M4receives a bias voltage VB2, and its drain is coupled to an input node INPUT. The input node INPUT is also coupled to the drain of M3, to a first input of a transconductance (gm) boosting amplifier A2, and to the source of another PMOS transistor M5. The drain of M5forms an OUTPUT node, which is coupled to an input of a bias current source I2having its output coupled to ground (GND). The current source I2generates a current12from the OUTPUT node to GND. The second input of the amplifier A2receives a reference voltage REFP.

An amplifier A1receives the REFP voltage at a first input and has its second input coupled to a node A, which develops a voltage VX. The output of A1is coupled to the gates of M2and M3. The drains of M1and M2are coupled to node A, which is coupled to the input of another bias current source I1having its output coupled to GND. The current source I1generates a current I1from node A to GND. The gate of M1receives a bias voltage VB1, where VB1is related to VB2in the illustrated embodiment. For example, VB2=VB1, or they are related by a suitable factor, or they may, in fact, be the same bias node. M1and M2are “mirror” transistors of M4and M3, respectively. In particular, M1is scaled relative to M4by a factor “N” and has its drain-source path coupled between VDD and node A similar to the drain-source path of transistor M4coupled between VDD and INPUT. M2is scaled relative to M3by the same factor N and has its drain-source path coupled in parallel with the drain-source path of M1similar to the drain-source path of M3coupled in parallel with the drain-source path of M4. Also, the gates of M2and M3are driven by the output of the amplifier A1. The transistors M3, M4and M5, the amplifier A2and the current source I2collectively form a signal branch101. The transistors M1and M2, the amplifier A1and the current source I1collectively form a “dummy” branch103providing a negative current generation loop that senses and compensates for power supply noise.

M3and M4are signal path current source transistors for M5. M4is biased from a diode-connected PMOS bias transistor (not shown) providing the bias voltage VB2. M3is a shunt current source driven by the output of the amplifier A1, where the amplifier A1is part of a negative current generation loop. The amplifier A1, having a sufficiently high gain to drive its inputs to be relatively equal, senses the voltage VX at node A and drives the gate of M2to maintain VX at REFP, while also driving the gate of M3. In this configuration, the PMOS current source transistors are the major source of power supply noise coupling path. When biased using a diode-connected mirror transistor and a current source with adequate output resistance, the gate voltage of the PMOS current source transistor M4tracks the noise of the power supply VDD. Hence, the power supply noise coupling occurs predominantly through source/bulk voltage fluctuations. The current follows an output conductance “gds” and the bulk-to-drain capacitance (Cbd) and gate-to-drain capacitance (Cgd) paths.

If vdd represents the small signal power supply perturbations of the source voltage VDD, then variations in VDD cause a noise component current N*vdd*gds to flow via the source-drain path of M4from VDD to INPUT (where the asterisk “*” denotes multiplication). It is noted that the output conductance “gds” in this case represents the combined conductance of the mirror components M1and M2, where the combined conductance of M3and M4is N*gds. It is desired to control the gate of M3such that it generates an equal and opposite compensation current N*vdd*gds through the drain-source path of M3from the INPUT node to VDD for compensation to minimize the effect of the power supply noise. In other words, the potential noise caused in the signal path by injecting the noise component current N*vdd*gds into the node INPUT is essentially canceled by pulling or drawing out the same level of current from node INPUT to VDD via M3to significantly reduce noise.

The same variation in VDD causing the noise component current N*vdd*gds flowing into the source of M4causes a similar noise component current vdd*gds into the source of M1. The noise component current vdd*gds effectively flows into node A causing a corresponding change of VX. The amplifier A1counteracts the change of VX by controlling the gate of M2to generate an equal and opposite compensation current vdd*gds flowing through the drain-source path of M2from node A to VDD. The amount of compensation applied to the gate of M2to generate the compensation current vdd*gds through M2is the same compensation applied to the gate of M3to generate the compensation current N*vdd*gds through M3. In summary, the dummy branch103controls M2to pull back the supply noise injected by the gds components of M1and M2, and, due to the mirroring effect of M1and M2relative to M3and M4, also controls M3to pull back the supply noise injected in the signal path by the gds components of M3and M4.

For low frequency analysis, let gds1, gds2, gds3and gds4be the output conductances of M1, M2, M3and M4, respectively, let gm2and gm3be the transconductance factors of M2and M3, respectively, and let A be the DC gain of the amplifier A1. Also, let “vx” be the small signal noise perturbations of VX at node A caused by vdd, which is the small signal supply perturbation of VDD. Supply noise injected into the signal path, without negative current compensation injection, is given by vdd*(gds3+gds4). The current components in the dummy branch103are as follows: a first current component (vdd−vx)*(gds1+gds2) due to the gds components of M1and M2; a second component gm2*A*vx due to the voltage controlled current source component of M2; and an output resistance component R0of the current source I1. It is shown that the gm2*A*vx current component is equal to and opposite of the gds components of M1and M2except for a leakage current due to the finite output resistance R0of the current source I1. The leakage current, however, is A*gm2*R0times smaller than the original gds components, and thus is very small. Neglecting the small leakage current (which sets the theoretical limit for PSR ratio enhancement), the gds current component is “pulled back” by the negative feedback loop formed by the amplifier A1and the M2transistor. Intuitively, the transistor M2serves to pull back the supply noise injected by the gds components of M1and M2, and, due to mirroring effect of M1/M2with M3/M4, the gm3current component of M3cancels the gds3+gds4current components of M3and M4.

The factor N may be any value including 1 for a 1:1 correspondence between M1and M2relative to M3and M4, respectively. A factor of N greater than one allows the use of significantly smaller transistors M1and M2in the dummy branch103to improve efficiency and to reduce overall size of the PMOS CG amplifier100. For example, the size of the transistors M1and M2can be made appreciably smaller and thus draw appreciably less current to achieve similar results.

In experimental results, cancellation of power supply noise was observed in a PMOS common gate amplifier with a negative current generation loop implemented according to an embodiment of the present invention used in a microphone amplifier. The PSR ratio (PSRR) at 217 Hertz (Hz) was improved from 30 decibels (dB) to 85 dB.

Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. For example, the same principles may be applied to differential pairs or other amplifiers using PMOS current source transistors. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.