Switched-mode power converter with split partitioning

A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.

TECHNICAL FIELD

This disclosure relates to power converters, and more particular, to techniques and circuits associated with switched-mode power converters.

BACKGROUND

Some circuits may use power converters that receive a power input from a power source and convert (e.g., step-up or step-down) the power input to a power output that has a different (e.g., regulated) voltage or current level than the voltage or current level of the power input. The converter outputs the power output to a filter for powering a component, a circuit, or other electrical device. Switch-based power converters may use half-bridge circuits and signal modulation techniques to regulate the current or voltage level of a power output. In some examples, power converters may use additional feedback control circuits and techniques (e.g., voltage sensing, current sensing, and the like) to improve the accuracy and control of the voltage or current level of the power output. These aforementioned techniques and circuits for improving the accuracy and control of the voltage or current of the power output may decrease overall efficiency of the power converter and/or increase the physical size, complexity, and/or cost of the power converter.

SUMMARY

In general, techniques and circuits are described for enabling a system in package (SiP) power converter to output power with a current level that can not only reach or exceed five amperes, but also can be contained within a narrow (e.g., accurate) current-level tolerance window, all without sacrificing the package size, cost, and/or efficiency of the SiP power converter. A SiP power converter, whether a step-down or step-up converter, may include one or more power switches, driver/control logic, and feedback control circuitry (e.g., current sensing circuitry) distributed across only two dies of the SiP power converter package. One die is a CMOS (Complementary Metal Oxide Semiconductor) type die and the other die is a FET (Field Effect Transistor) or SFET (Superconductor Field Effect Transistor) type die. The one or more power switches of the SiP power converter comprise a power stage (e.g., a single phase half-bridge, a multi-phase half-bridge, etc.). Some of the one or more power switches (e.g., either the low-side or the high-side the half-bridge of the half-bridge of the power stage) are located on the one FET or SFET type die, while the rest of the one or more power switches (e.g., the side of the half-bridge of the power stage that is not on the FET or SFET type die), are located on the other CMOS type die. The other CMOS type die further includes all the driver/control logic and the feedback control circuitry (e.g., current sensing circuitry).

By containing some of the one or more power switches to the one FET or SFET type die, the efficiency of the SiP power converter can be improved since at least a portion (e.g., the high-side) of the power stage of the SiP power converter can include high-efficiency FET or SFET type power switches. Additionally, by co-locating the driver/control logic, the feedback control circuitry (e.g., the current sensing circuitry), and the rest (e.g., the low-side) of the one or more power switches to the one CMOS type die, the accuracy of the power output of the SiP power converter can be improved since the power output can be controlled using highly accurate sense-FET current sensing circuitry without being susceptible to electromagnetic interference (EMI) and other noise caused by switching of the FET or SFET type switches. Furthermore by operating the current sensing circuitry on the same CMOS die as the rest of the power switched and driver/control logic, the current sensing circuitry can operate without using a charge pump.

In one example, the disclosure is directed to a power converter including a first die including one or more first switches coupled to a switching node of a power stage, and a second die. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.

In another example, the disclosure is directed to a method that includes detecting, by a feedback control unit at a second die of a power converter, a current level at one or more second switches at the second die of the power converter, the one or more second switches being coupled to one or more first switches at a first die of the power converter at a switching node of a power stage. The method further includes controlling, by a controller unit at the second die, the one or more first switches of the power stage at the first die based at least in part on a driver signal, wherein the driver signal is based at least in part on the current level detected at the one or more second switches at the second die. The method further includes controlling, by the controller unit at the second die, the one or more second switches of the power stage at the second die based at least in part on the driver signal.

In another example, the disclosure is directed to a power converter having means for means for detecting a current level at one or more second switches at a second die of a power converter, the one or more second switches being coupled to one or more first switches at a first die of the power converter at a switching node of a power stage. The power converter further includes means for controlling, from the second die, the one or more first switches of the power stage at the first die based at least in part on a driver signal, wherein the driver signal is based at least in part on the current level detected at the one or more second switches at the second die. The power converter further includes means for controlling, from the second die, the one or more second switches of the power stage at the second die based at least in part on the driver signal.

DETAILED DESCRIPTION

In some applications, a switch-based power converter (hereafter referred to as a “power converter” or simply a “converter”) may receive a power input and convert (e.g., by stepping-up or stepping-down) the power input to a power output that has a voltage or current level that is different (e.g., regulated) than the voltage or current level of the power input, for instance, to provide the power output to a filter for powering a load (e.g., a device). As described herein, the term “step-up” refers to a power converter configured to receive an input power signal with a first voltage level, and output a power signal with a second voltage level that is greater than the first voltage level. As also described herein, the term “step-down” converter refers to a power converter configured to receive an input power signal with a first voltage level, and output a power signal with a second voltage level that is less than the first voltage level.

In either case, a power converter may have one or more switches (e.g., MOS power switch transistors based switches, gallium nitride (GaN) based switches, or other types of switch devices) arranged in a power stage configuration (e.g., a single phase, or multi-phase half-bridge configuration, etc.) that the power converter controls, according to one or more modulation techniques, to change the current or voltage level of the power output. A single phase half-bridge may include a high-side switch coupled to a low-side switch at a switching node whereas a multi-phase half-bridge may include multiple high-side switches coupled to multiple low-side switches at a switching node.

A power converter may include one or more gate drivers and control logic to control (e.g., turn-on and turn-off) the one or more switches of the power stage using modulation techniques. Such modulation of the switches of a power stage may operate according to pulse-density-modulation (PDM), pulse-width-modulation (PWM), pulse-frequency-modulation (PFM), or another suitable modulation technique. By controlling the switches of a power stage using modulation techniques, a power converter can regulate the current or voltage level of the power being outputted by the power converter.

Some power converters may use feedback circuits and techniques for performing current sensing and/or voltage sensing to obtain information about a current or voltage level of a power output. The power converter may use the information received using feedback circuits and techniques to improve the accuracy of the power output. For example, the power converter may use the feedback information to contain the voltage or current level of a power output within a particular tolerance or threshold window for satisfying the power requirements of a load. Some power converters may use current sensing as one example of feedback circuits and techniques to determine the real-time current level of the power being outputted to a load. If the power converter determines that the current level does not satisfy the power requirements of the load, then the power converter may adjust or change how the power converter controls the power switches in order to adjust or change the current level of the power output until the current level of the power output is contained within the tolerance window and satisfies the current level associated with the power requirements of the load.

Some power converters have individual and discrete high-side and low-side power switches that are separate from the driver/control logic and/or feedback control circuitry of the power converter. A power converter that uses individual and discrete power switches may operate with less efficiency than some other types of power converters. For instance, a “System in Package” or “SiP” power converter may have a higher level of efficiency than a power converter that uses individual and discrete power switches.

Rather than rely on individual and discrete power switches, a SiP power converter includes power switches that are integrated with driver/control logic and feedback control circuitry into a single integrated circuit (IC) or chip package. While integrated packaging may cause SiP power converters to operate with greater efficiency than other types of power converters, the integrated packaging may increase complexity and/or cost associated with the design and manufacturing of the power converter. As a result of higher complexity and costs, a SiP power converter may be unsuitable (e.g., too complex and/or too costly) for certain low-cost and less complex power converter applications.

Although the components of the SiP are contained in a single package, the size of the SiP packaging may cause the SiP power converter to be too large for some applications. For example, a SiP power converter may have one or more dies (e.g., of CMOS type) that include all the driver/control logic and feedback control circuitry of the power converter as well as two or more other dies (e.g., of FET type, of SFET type, etc.) that each include one or more high-side and low-side high-efficiency (e.g., FET, SFET, etc.) power switches. As such, a SiP power converter may include a minimum of three separate and individual dies within the single integrated circuit or chip package. The resultant size, complexity, and cost to design and manufacture a SiP power converter may be proportionate to the quantity of dies included in the SiP. By including three, and often more than three, individual dies within a single integrated circuit or chip package, the complexity, cost, and/or size of the SiP converter may exceed the corresponding complexity, cost, and/or size requirements of the application of the SiP power converter.

Although some SiP power converters may include integrated feedback control circuitry for performing on-chip current and/or voltage sensing, in some instances, the integrated feedback control circuitry of a SiP power converter may obtain inaccurate information about a current or voltage level of a power output since. The inaccuracies of integrated feedback control (e.g., sensing) circuitry of a SiP power converter may be due to an increased susceptibility that sense lines of integrated feedback control (e.g., sensing) circuitry may have to operating noise (e.g., during a switching cycle when the power switches of the SiP power converter transitions between operating in an on-state and an off-state).

For example, a SiP power converter may co-locate the driver/control logic and the feedback control circuitry onto a single CMOS type die. The SiP power converter may further co-locate the high-side power switches onto a first FET or SFET type die and the low-side power switches onto a second FET or SFET type die. By separating the feedback control circuitry from the power switches, the SiP power converter may require additional sense lines (e.g., wires or traces) arranged in-between the CMOS type die and one or both of the two FET or SFET type dies for coupling the feedback control (e.g., sensing) circuitry to the power switches.

Sense lines that are located outside of the die that contains the feedback control circuitry, and that are arranged in-between two separate dies of an integrated circuit or chip package, may be susceptible to electromagnetic interference (EMI) or other type of electrical noise, especially when high-efficiency FET or SFET power switches are used and caused to transition between operating in an on-state and an off-state (e.g., turn-on or turn-off) during a switching cycle. In addition, when performing particular types of sensing or feedback control techniques (e.g., current sense-FET current sensing) at a one side of a half-bridge (e.g., the low-side), a large (e.g., high capacitance) charge pump may be required by the feedback control (e.g., sensing) circuitry to obtain accurate information associated with the current level of a power output.

In some examples, to minimize the effects that noise may have on the sensing circuitry of a power converter, a “System on Chip” or “SoC” power converter with monolithic integration may be used. The SoC power converter integrates the driver/control logic and feedback control circuitry of the power converter, with the power switches of the power converter, onto a single die within the same chip or package. By integrating all the power switches, the driver/control logic, and the feedback control circuitry onto a single die, the sense lines of the feedback control circuitry is also contained within the single die and may be less susceptible to EMI or other electrical noise and obtain more accurate information about the current and/or voltage level of a power output than the sensing circuitry used by some other power converters.

Although a SoC power converter with monolithic integration may have improved sensing circuitry, a SoC power converter may be less efficient that some other power converters because the power switches of a SoC power converter may dissipate a greater amount of power during each switching cycle (e.g., each transition between operating in an on-state and an off-state) than the amount of power lost to a switching cycle by the power switches of some other power converters. For example, rather than use more efficient FET or SFET power switch technology, a SoC power converter may use less efficient CMOS switching technology that can be co-located onto the same (e.g., CMOS) die as the driver/control logic and integrated current sensing.

The less efficient power switch technology of the SoC power converter may have a higher amount of RDS(ON)than the power switches of other power converters. As a result of a higher amount of RDS(ON), the power switches of a SoC power converter may dissipate a greater amount of power during each switching cycle than the amount of power lost during each switching cycle of the power switches power converters that have switches with a lower amount of RDS(ON)(e.g., FET or SFET type switches). In addition, the CMOS type switches of the SoC power converter may limit the current level of the SoC power output to less than five amperes.

In general, circuits and techniques of this disclosure may enable a system in package (SiP) power converter to output power with a current level that can not only reach or exceed five amperes, but also can be contained within a narrow (e.g., accurate) current-level tolerance window, all without sacrificing the package size, cost, and/or efficiency of the SiP power converter. A SiP power converter, whether a step-down or step-up converter, may include one or more power switches, driver/control logic, and feedback control circuitry (e.g., current sensing circuitry) distributed across only two dies of the SiP power converter package. One die is a CMOS type die and the other die is a FET or SFET type die. The one or more power switches of the SiP power converter comprise a power stage (e.g., a half-bridge). Some of the one or more power switches (e.g., either the low-side or the high-side a half-bridge of the power stage) are located on the one FET or SFET type die, while the rest of the one or more power switches (e.g., the side of the half-bridge of the power stage that is not on the FET or SFET type die), are located on the other CMOS type die. The other CMOS type die further includes all the driver/control logic and the feedback control circuitry (e.g., current sensing circuitry).

Throughout this disclosure the terms “CMOS type” and “FET or SFET type” are used to describe two different types or forms of semiconductor dies for use in implementing the circuits and techniques described herein. A CMOS type die as referred to herein describes a semiconductor die that includes primarily CMOS type transistors, or that the semiconductor die is primarily manufactured according to a CMOS type manufacturing process, or that the semiconductor die includes substantially more CMOS type transistors than other types of transistors. A FET or SFET type die as referred to herein describes a semiconductor die that includes primarily FET or SFET type transistors (e.g., rather than CMOS type transistors that may be primarily found in a CMOS type die), or that the semiconductor die is primarily formed by a FET or SFET type manufacturing process (e.g., rather than a CMOS type manufacturing process that may be used to form a CMOS type die), or that the semiconductor die includes substantially more FET or SFET type transistors than other types of transistors (e.g., CMOS type).

By containing some of the one or more power switches to the one FET or SFET type die, at least a portion (e.g., the high-side) of the power stage of the SiP power converter can include high-efficiency FET or SFET type power switches. Additionally, co-locating the driver/control logic, the current sensing circuitry, and the rest (e.g., the low-side) of the one or more power switches to the one CMOS type die allows the SiP power converter to be controlled using highly accurate sense-FET current sensing circuitry without further requiring a charge pump for the sense-FET current sensing circuitry. Furthermore, by co-locating the rest of the one or more power switches, the current sensing circuitry, and the driver/control logic to a single die, electromagnetic interference (EMI) or other noise disturbances (e.g., caused by switching of the FET or SFET type switches on the FET or SFET type die) at the sense lines of the current sensing circuitry may be reduced.

In this way, by using high efficient FET or SFET type power switches for at least some of the power switches of the SiP power converter, the SiP power converter according to the following circuits and techniques can operate more efficiently, and can output power at greater current levels, than some SoC and other SiP power converters. Furthermore, by containing current sensing circuitry to the same die as the driver/control logic and the rest of the power switches of the SiP power converter, the SiP power converter according to the following circuits and techniques can be controlled using highly accurate (e.g., sense-FET) current sensing technology, without requiring a charge pump, to provide a more accurate power output that has a current level contained to a narrow tolerance window. Additionally, because a charge pump is not necessary, and since only two dies are used, the SiP power converter can fit within a smaller, less complex, and cheaper package than some larger, more complex, and more expensive SoC and SiP power converters.

FIG. 1is a block diagram illustrating system1for converting power from power source2, in accordance with one or more aspects of the present disclosure.FIG. 1shows system1as having four separate and distinct components shown as power source2, power converter4, filter6, and load8, however system1may include additional or fewer components. For instance, power source2, power converter4, filter6, and load8may be four individual components or may represent a combination of one or more components that provide the functionality of system1as described herein.

System1includes power source2which provides electrical power to system1. Numerous examples of power source2exist and may include, but are not limited to, power grids, generators, transformers, batteries, solar panels, windmills, regenerative braking systems, hydro-electrical or wind-powered generators, or any other form of devices that are capable of providing electrical power to system1.

System1includes power converter4which operates as a switch-based power converter that converts one form of electrical power provided by power source2into a different, and usable form, of electrical power for powering load8. Power converter4may be a step-up converter that outputs power with a higher voltage level than the voltage level of input power received by the step-up converter. One example of such step-up converter may be referred to as a boost converter. Power converter4may instead comprise a step-down converter configured to output power with a lower voltage level than the voltage level of input power received by the step-down converter. One example of such a step-down converter may be referred to as a buck converter. In still other examples, power converter4may be a step-up and step-down converter (e.g., a buck-boost converter) that is capable of outputting power with a voltage level that is higher or lower level than the voltage level of the power input received by the step-up and step-down converter. Examples of power converter4may include battery chargers, microprocessor power supplies, and the like. Power converter4may operate as a DC-to-DC, DC-to-AC or AC-to-DC converter.

System1further includes filter6and load8. Load8receives the electrical power (e.g., voltage, current, etc.) converted by power converter4after the power passes through filter6. In some examples, load8uses the filtered electrical power from power converter4and filter6to perform a function. Numerous examples of filter6exist and may include, any suitable electronic filter for filtering power for a load. Examples of filter6include, but are not limited to, passive or active electronic filters, analog or digital filters, high-pass, low-pass, band pass, notch, or all-pass filters, resistor-capacitor filters, inductor-capacitor filters, resistor-inductor-capacitor filters, and the like. Likewise, numerous examples of load8exist and may include, but are not limited to, computing devices and related components, such as microprocessors, electrical components, circuits, laptop computers, desktop computers, tablet computers, mobile phones, batteries, speakers, lighting units, automotive/marine/aerospace/train related components, motors, transformers, or any other type of electrical device and/or circuitry that receives a voltage or a current from a power converter.

Power source2may provide electrical power with a first voltage or current level over link10. Load8may receive electrical power that has a second voltage or current level, converted by power converter4, and filtered through filter6, over link14. Links10,12, and14represent any medium capable of conducting electrical power from one location to another. Examples of links10,12, and14include, but are not limited to, physical and/or wireless electrical transmission mediums such as electrical wires, electrical traces, conductive gas tubes, twisted wire pairs, and the like. Each of links10and12provide electrical coupling between, respectively, power source2and power converter4, and power converter4and filter6. Link14provides electrical coupling between filter6and load8. In addition, link14provides a feedback loop or circuit for carrying information to power converter4associated with the characteristics of a filtered power output from filter6.

In the example of system1, electrical power delivered by power source2can be converted by converter4to power that has a regulated voltage and/or current level that meets the power requirements of load8. For instance, power source2may output, and power converter4may receive, power which has a first voltage level at link10. Power converter4may convert the power which has the first voltage level to power which has a second voltage level that is required by load8. Power converter4may output the power that has the second voltage level at link12. Filter6may receive the power from converter4and output the filtered power that has the second voltage level at link14.

Load8may receive the filtered power that has the second voltage level at link14. Load8may use the filtered power having the second voltage level to perform a function (e.g., power a microprocessor). Power converter4may receive information over link14associated with the filtered power that has the second voltage level. For instance, feedback control (e.g., current sensing) circuitry of power converter4may detect the voltage or current level of the filtered power output at link14and driver/control logic of converter4may adjust the power output at link12based on the detected voltage or current level to cause the filtered power output to have a different voltage or current level that fits within a voltage or current level tolerance window required by load8.

FIG. 2is a block diagram illustrating one example of power converter4of system1shown inFIG. 1. For instance,FIG. 2shows a more detailed exemplary view of power converter4of system1fromFIG. 1and the electrical connections to power source2, filter6, and load8, provided by links10,12, and14respectively.

Power converter4is shown as being a switch-based SiP power converter having various electrical components and traces (e.g., links or wires) that are co-located within a single, integrated circuit or chip package. The various electrical components and traces of power converter4are distributed across two separate dies of converter4, labeled as die20and die22. Power converter4may be a step-up converter (e.g., boost converter), a step-down converter (e.g., buck converter), or a step-up and step-down converter (e.g., a buck-boost converter).

An elliptical dashed line is drawn inFIG. 2to illustrate the various components of power stage34of power converter4including one or more switches30of die22which are coupled to one or more switches32of die22at switching node18. Switches30may be high-side or low-side switches of a half-bridge of power stage34, a full-bridge of power stage34, or any other type of power stage configuration that for outputting power from a switch based power converter. If switches30are high-side switches of power stage34, then switches32are low-side switches of power stage34. Conversely, if switches30are low-side switches of power stage34, then switches32are high-side switches of power stage34.

In the example ofFIG. 2, die20includes controller unit42, driver40, and driver42that represent the driver/control logic and feedback control circuitry of power converter4. Die20further includes one or more switches32which represent one half (e.g., the low-side or the high-side) of power stage34of converter4. Die22of converter4does not include any of the driver/control logic or feedback control circuitry of power converter4. Die22does include one or more switches30which represent the other half (e.g., the high-side or low-side) of power stage34of converter4that is omitted from die20.

In some examples, die20and die22may include additional or fewer components than the components shown inFIG. 2. For instance, die22may include over-current protection circuitry that may require placement at a FET or SFET type die (e.g., die22) and may not be compatible with placement at a CMOS type die (e.g., die20). In other words, FET or SFET type components that require placement at a FET or SFET type die can be co-located with switches32at die22.

Die22may be a FET or SFET type die and the various components contained within die22may be of FET or SFET type. For instance, switches30may be one or more FET or SFET type switches. Die22may include various other FET or SFET type electrical components not shown inFIG. 2. As FET or SFET type switches, switches30may be highly efficient switch devices that perform either the high-side or low-side switching operations of converter4. For instance, switches30may be a single GaN based switch arranged in a single phase half-bridge configuration of power stage34with switches32and switching node18. Switches30may also be multiple GaN based switches arranged in a multi-phase half-bridge configuration of power stage34with switches32and switching node18. In any event, switches30may have a lower RDS(ON)than some other types of switches and as a result dissipate less energy during a switching cycle (e.g., when transitioning from operating in an off-state and an on-state) than other, less efficient, type switches.

Die20may be a CMOS type die and the various electrical components contained within die20may be of CMOS type. For example, die20includes controller unit24, drivers40and42, and one or more switches32. Controller unit24includes modulation unit28(e.g., a driver/control logic block) and feedback control unit26(e.g., feedback control circuitry). Switches32of die20may perform the switching operations of converter4that are not performed by switches30of die22. Said differently, in cases where switches30of die22perform low-side switching operations for power stage34, switches32of die20may perform high-side switching operations for power stage34. Conversely, switches32of die20may perform low-side switching operations for power stage34when switches30of die22perform high-side switching operations.

Switches32of die20may be single or multiple CMOS type switch devices for performing the switching operations of power stage34that are not performed by switches30of die20. As CMOS type switch devices, switches32of die20may operate less efficiently than other types of switches. For example, switches32may have a higher RDS(ON)than some other types of switches (e.g., FET or SFET type switches30of die22) and as a result dissipate more energy during a switching cycle (e.g., when transitioning from operating in an off-state and an on-state) than other, more efficient, type switches.

Power converter4includes three terminals for connecting converter4to external devices using links10,12, and14. Power converter4includes input/output terminals50and52and feedback terminal54. Feedback terminal54may be coupled to link14ofFIG. 1for providing feedback information indicative of voltage or current level of the filtered power output being provided out of filter6, across link14, to load8.

Depending on the particular configuration of converter4, input/output terminal52couples switching node18to either link10or link12. For example, when power converter4operates as a step-down or buck converter, input/output terminal52acts as an output and couples switching node18to link12. Conversely, when power converter4operates as a step-up or boost converter, input/output terminal52acts as an input and couples switching node18to link10. When power converter4operates as a step-up and step-down converter, power converter4includes additional switching logic (not shown) for causing input/output terminals50and52to operate as either input or output terminals. In addition, depending on the particular configuration of converter4, input/output terminal50couples switches30, via link56A, to either link10or link12, or input/output terminal52couples switches32, via link56B, to either link10or link12.

For example, in one example, switches30are high-side switches of a half-bridge of power stage34and switches32are low-side switches of a half-bridge of power stage34. When power converter4operates as a step-down or buck converter, input/output terminal50acts as an input and couples link10to high-side switches30via link56A. Conversely, when power converter4operates as a step-up or boost converter, input/output terminal50acts as an output and couples link12to high-side switches30via link56A.

In an alternative example, switches32are high-side switches of a half-bridge of power stage34and switches30are low-side switches of a half-bridge of power stage34. When power converter4operates as a step-down or buck converter, input/output terminal50acts as an input and couples link10to high-side switches32via link56B. Conversely, when power converter4operates as a step-up or boost converter, input/output terminal50acts as an output and couples link12to high-side switches32via link56B.

In either example, when operating as a step-down converter, power converter4may receive a power input over link10from source2at input/output terminal50. Power converter4may control switches30and32according to modulation techniques to convert the power input to a power output that has a lower voltage level than the power input. Power converter4may output the power output to filter6across link12at input/output terminal52. Conversely, when operating as a step-up converter, power converter4may receive a power input over link10from source2at input/output terminal52. Power converter4may control switches30and32according to modulation techniques to convert the power input to a power output that has a higher voltage level than the power input. Power converter4may output the power output to filter6across link12at input/output terminal50. In either example, when power converter4operates as a step-up and step-down converter, power converter4includes additional switching logic (not shown) for causing input/output terminals50and52to operate as either input or output terminals.

Links16A-16E (collectively “links16”) represent various “internal” traces and/or vias of die20that electrically couple and interconnect the internal components24,26,28,40,42, and32contained within die20. For example, link16A provides a path for electrical information to pass between feedback control unit26and modulation unit28within controller unit24. Link16B represents a sense line between switches32and (e.g., current sense-FET current sensing circuitry of) feedback control unit26. Links16C and16D are driver control lines for transmitting driver control signals (e.g., based on pulse-density-modulation (PDM) signal, a pulse-width-modulation (PWM) signal, pulse-frequency-modulation (PFM) signal or other suitable modulation technique) from controller unit24to drivers40and42. Link16E represents a switch control line for transmitting switch control signals from driver42to one or more switches32.

Links17A-17D (collectively “links17”) represent “external” traces and/or vias that electrically couple or connect components from one die20or22to feedback terminal54, switching node18, and/or the internal components of another die20or22. For example, link17A couples feedback terminal54to feedback control unit26of controller unit24of die20for transmitting information associated with the characteristics of a filtered power output provided by filter6at link14. Link17B represents a switch control line for transmitting switch control signals from driver40of die22to one or more switches30of die20. Links17C and17D couple one or more switches32of die22to one or more switches30of die20at switching node18and input/output terminal52.

Many examples of one or more switches30exists and could be any type of switch devices that can be contained to a CMOS type die and further, when arranged in a power stage configuration, are suitable for stepping-down/bucking or stepping-up/boosting a voltage level of a power input. For instance, some examples of one or more switches30may include Silicon (Si), Gallium Nitride (GaN), and/or Silicon Carbide (SiC) based switching devices, normally-on or normally-off type switches, GaN high-electron-mobility transistors (HEMT), N-type MOSFET based switch devices, P-type MOSFET based switch devices, diodes, IGBT switch devices, drain extended MOS (deMOS) switch devices, or any other type of power switch transistors or switch device that can operate in a power stage configuration at a CMOS type die.

Likewise, many examples of one or more switches32exists and could be any type of switch devices that can be contained to a FET or SFET type die and further, when arranged in a power stage configuration are suitable for stepping-down/bucking or stepping-up/boosting a voltage level of a power input. For instance, some examples of one or more switches32may include Si, GaN, and/or Silicon Carbide SiC based switching devices, normally-on or normally-off type switches, HEMT (GaN), FET (GaN), diodes, JFETs (SiC, normally on or off), vertical or lateral type switch devices, metal-gate switch devices, poli-Si-gate switch devices, or any other type of power switch transistors or switch device that can operate in a power stage configuration at a FET or SFET type die.

Driver(s)40and driver(s)42represent one or more individual gate drivers for controlling each of the one or more individual switches30and32(respectively). For ease of description,FIG. 2is described as if each of driver(s)40and42are each single drivers for controlling each of the one or more individual switches30and32. However, in some examples, driver(s)40and42each represent an array of multiple drivers, with each driver of the array of drivers40being used to control a different respective one of the one or more switches30, and each driver of the array of drivers42being used to control a different respective one of the one or more switches32.

Driver40is coupled to the one or more switches30via link17B such that an output signal produced by driver40may cause the one or more switches30to transition from operating between an on-state and an off-state (e.g., turn-on or turn-off). Driver42is coupled to the one or more switches32via link16E such that an output signal produced by driver42may cause the one or more switches32to transition from operating between an on-state and an off-state. Driver40and42each receive driver control signals from modulation unit28of controller unit24via links16C and16D respectively. An output of driver40may be based on a driver control signal received via link16C and an output of driver42may be based on a driver control signal received via link16D.

Controller unit24of die20represents a combination of driver/control logic and feedback control circuitry of converter4for performing modulation and feedback techniques to control drivers40and42for causing switches30and32to modulate and to output power at link12. Controller unit24can comprise any suitable arrangement of hardware, software, firmware, or any combination thereof, to perform the techniques attributed to controller unit24herein. For example, controller unit24may include digital circuitry, analog circuitry, or any combination thereof to control and regulate a switch mode power converter. Controller unit24may include any one or more microprocessors, signal processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), comparators, operational amplifiers, full-custom and/or semi-custom digital logic, registers for storing control data (e.g., parameters), analog and/or digital filter stages, non-linear control blocks, or any other equivalent, integrated, digital or analog circuitry, as well as any combinations of such components.

When controller unit24includes software or firmware, controller unit24further includes hardware for storing and executing the software or firmware, such as one or more digital or analog processors or processing units. In general, a processing unit may include one or more microprocessors, signal processors, ASICs, FPGAs, comparators, operational amplifiers, or any other equivalent, integrated, digital or analog circuitry, as well as any combinations of such components. Although not shown inFIG. 2, controller unit24may include a memory configured to store data. The memory may include any volatile or non-volatile media, such as a random access memory (RAM), read only memory (ROM), non-volatile RAM (NVRAM), electrically erasable programmable ROM (EEPROM), flash memory, and the like. In some examples, the memory may be external to controller unit24and/or power converter4, e.g., may be external to a package in which controller unit24and/or power converter4is housed.

Controller unit24may rely on feedback control unit26to detect the voltage or current level of a power output at link14and to detect or “sense” the amount of current at power stage34. For example, feedback control unit26may include sense-FET current sensing circuitry, voltage sensing circuitry, or other types of current or voltage sensing circuitry for sensing a current or voltage level via link16B through switches32and power stage34. Because link16B is contained internally within die20, feedback control unit26can determine a highly accurate measurement of current at power stage34. In other words, because feedback control unit26does not rely on “external” sense lines that pass between two or more separate dies of converter4, the sense lines of feedback control unit26(e.g., link16B) are less susceptible to EMI or other noise interference. As a result, the state of the information that feedback control unit26receives over link16B arrives from switches32intact and unaltered as compared to state of the information when the information is first transmitted.

By co-locating feedback control unit26and switches32within the same CMOS die20, the sensing circuitry of feedback control unit26may perform current and/or voltage sensing without the need for a high-capacitance (e.g., large) charge pump required by some other sensing circuitry and techniques. In other words, feedback control unit26can perform current sensing, in particular, sense-FET current sensing, at CMOS type switches32to determine the level of current at power stage34without using a high-capacitance charge pump that may be required by other SoC or SiP power converters.

Controller unit24may rely on modulation unit28to generate driver control signals (e.g., based on pulse-density-modulation (PDM) signal, a pulse-width-modulation (PWM) signal, pulse-frequency-modulation (PFM) signal or other suitable modulation technique) for controlling the turn-on and/or turn-off signals to switches30and32of power stage34to cause converter4to provide a power output at link12. For example, modulation unit28may receive information from feedback control unit26adjusting a voltage or current level of a power output, and based on the adjustment information, modulation unit28may vary the properties or characteristics of the driver control signals that modulation unit28outputs to drivers40and42.

Modulation unit28may provide PWM-based driver control signals over links16C and16D that cause drivers40and42to cause switches30and32of power stage34to transition between operating in an on-state and an off state. In response to the voltage or current level of a power output detected at link14by feedback control unit26, and further responsive to the current level at power stage34detected by feedback control unit26, modulation unit28may vary the duty cycle of the PWM-based driver signals. For instance, modulation unit28and feedback control unit26may use current and/or voltage level thresholds to determine an adjustment to the duty cycle of the PWM-based driver signals that control switches30and32for modulating a particular power output within a particular current or voltage level tolerance window, at link12. By varying the duty cycle of the PWM-based driver signals based on information detected by feedback control unit26, modulation unit28may alter the level of voltage or current of the power output provided by converter4at link12.

Modulation unit28may provide PDM-based driver control signals over links16C and16D that cause drivers40and42to cause switches30and32of power stage34to transition between operating in an on-state and an off state. In response to the voltage or current level of a power output detected at link14by feedback control unit26, and further responsive to the current level at power stage34detected by feedback control unit26, modulation unit28may vary the average value of the PDM-based driver signals. For instance, modulation unit28and feedback control unit26may use current and/or voltage level thresholds to determine an adjustment to the duty cycle of the PDM-based driver signals that control switches30and32for modulating a particular power output within a particular current or voltage level tolerance window, at link12. By varying the average value of the PDM-based driver signals based on information detected by feedback control unit26, modulation unit28may alter the level of voltage or current of the power output provided by converter4at link12.

By containing switches30to die22, at least a portion (e.g., the high-side or low-side) of power stage34can operate using high-efficiency FET or SFET type power switches without interfering with current or voltage sensing techniques performed by feedback control unit26of controller unit24of die20. Additionally, by co-locating controller unit24, drivers40and42, and switches32to die20, controller unit24can control switches30and32using information obtained from highly accurate sense-FET current sensing circuitry of feedback control unit26without further requiring a charge pump for the sense-FET current sensing circuitry of feedback control unit26. Furthermore, co-locating switches32together with feedback control unit26, modulation unit28, and drivers40and42on a single die20, minimizes the amount of EMI and other noise disturbances, caused during the switching of switches30of die22, at the sense lines (e.g., link16B) of the current sensing circuitry of feedback control unit26.

By using high efficient FET or SFET type power switches for at least some of the power switches of a power stage (e.g., including a single phase half-bridge, a multi-phase half-bridge, etc.), the power converter according to these circuits and techniques may operate more efficiently, and can output power at greater current levels, than some SoC and other SiP power converters. Furthermore, by containing current feedback control circuitry to the same die as driver/control logic, and the rest of the power switches of the power stage, the power converter according to these circuits and techniques can be controlled using more accurate (e.g., sense-FET) current sensing technology, without requiring a charge pump, to provide a more accurate power output that has a current level contained to a narrow tolerance window. Additionally, because a charge pump is not necessary, and since only two dies are used, the power converter according to these circuits and techniques can fit within a smaller, less complex, and cheaper package than some larger, more complex, and more expensive SoC and SiP power converters.

In some examples, controller unit24does not include feedback control unit26and therefore does not perform voltage or current sensing at switches32. In addition, without feedback control unit26, controller unit24does not control switches30and switches32based on the voltage or current detected by feedback control unit26. In some examples, switches30may be a diode. For instance, where converter4acts as a boost converter, and switches30of power stage34represent the high-side switches of converter4, switches30may be a single or multiple diodes.

FIG. 3is a block diagram illustrating one other example of power converter4of system1shown inFIG. 1.FIG. 3is described below within the context power converter4ofFIG. 2and system1ofFIG. 1.

SFET type high-side switch90A is coupled to CMOS type low-side switch92A at switching node94A. SFET type High-side switch90B is coupled to CMOS type low-side switch92B at switching node94B. Filter96A is arranged between switching node94A and input/output terminal52and filter96B is arranged between switching node94B and input/output terminal52. In some examples, filters96A and96B are inductor-capacitor (LC) based filters. In some examples, filters96A and96B may be outside of the packaging of converter4, for instance, as part of filter6ofFIG. 1. In some examples, filters96A and96B may be co-located within die20or die22.

Sense-FET current sensing circuitry of feedback control unit26may receive information associated with a detected current level at CMOS type low-side switches92A and92B via sense lines98A and98B contained within die20. By containing sense lines98A and98B to the interior of die20, the information transmitted via sense lines98A and98B may be less susceptible to EMI or other noise caused during switching operations of SFET type high-side switches90A and90B. In addition, by co-locating CMOS type low-side switches92A and92B with feedback control unit26at die20, the sense-FET current sensing circuitry of feedback control unit26may perform current sensing without requiring a large (e.g., high-capacitance) charge pump. Converter4may obtain the benefit of operating more efficiently by using SFET type high-side switches90A and90B to die20, while also using highly accurate current sensing techniques to output power at link12that has a current level that fits within a narrow current level tolerance window required by load8.

In the example ofFIG. 3, high-side switches90A and90B are contained to SFET die22. The example ofFIG. 3further illustrates that an optional current sense circuitry (indicated by the 3-wires arranged between the CMOS die20and the SFET die22). Low-side switches92A and92B are integrated in CMOS die20along with feedback control unit26that performs current sensing using integrated sense-MosFets on CMOS die20.

FIG. 4is a flowchart illustrating example operations of an example power converter, in accordance with one or more aspects of the present disclosure.FIG. 5is described below within the context of power converter4ofFIG. 2and system1ofFIG. 1.

From die20, power converter4may detect a current level at one or more switches32of a half-bridge of power stage34that are located at die20. For example, feedback control unit26of controller unit24located at die20of power converter4may detect a current level switches32. The current level may be received by feedback control unit26via link16B (e.g., one or more sense lines connecting switches32to sense-FET current sensing circuitry of feedback control unit26). In some examples, the current level detected at the one or more switches32is detected based on a sense-FET current sensing signal received by feedback control unit26over one or more current sense lines contained to die20. The one or more current sense lines may be arranged between feedback control unit26at die20and the one or more switches32at die20.

From die20, power converter4may control one or more switches30of the half-bridge of power stage34that are located on die22of power converter4based at least in part on the current level detected at switches32at die20. For example, feedback control unit26may send information indicative of the current level at power stage34detected by sense-FET current sensing circuitry of feedback control unit26to modulation unit28. In addition, modulation unit28may receive information indicative of the current or voltage level of a filtered power output being transmitted at link14. Based on the information received from feedback control unit26, modulation unit28may generate a driver control signal (e.g., a PWM based signal, a PDM based signal, or a signal based on some other modulation technique) for causing driver40to control switches30at die22. Modulation unit28may output the drive control signal to driver40. The driver control signal may cause driver40to output a command that passes over link17B, from die20to die22, for causing switches30to transition between operating in an on-state and an off-state.

From die20, power converter4may control the one or more switches32of power stage34that are located on die20of power converter4based at least in part on the current level detected at switches32at die20. For example, based on the information received from feedback control unit26, modulation unit28may generate a driver control signal (e.g., a PWM based signal, a PDM based signal, or a signal based on some other modulation technique) for causing driver42to control switches32at die20. Modulation unit28may output the drive control signal to driver42. The driver control signal may cause driver42to output a command that passes over link16E (e.g., contained within die20) for causing switches32to transition between operating in an on-state and an off-state.

FIGS. 5A and 5Bare circuit diagram illustrating cross sections of power converter4ofFIG. 2. For example,FIG. 5Ashows a “face down” SiP configuration of power converter4ofFIG. 2, including cross sectional views of dies20and22.FIG. 5Bshows a “face up” SiP configuration of power converter4ofFIG. 2, also including cross sectional views of dies20and22.

With only having two dies, die20and die22, power converter4can fit into a smaller SiP package size than other SiP power converters. For instance, other SiP power converters may include the high-side switches of a power stage on one die, the low-side switches on another die, and driver/logic and feedback control circuitry on one or more additional dies. In any case, some converters may require a minimum package size of approximately forty-nine square millimeters (i.e., seven millimeters by seven millimeters) to contain more than two dies.

Conversely, by using only two dies, the components of converter4can fit within a smaller package size. In some examples, converter4can fit within a package size that is less than forty-nine square millimeters and is approximately thirty-six square millimeters (i.e., six millimeters by six millimeters). With a smaller package size than some other power converters, the manufacturing cost to produce converter4is also cheaper than some other converters. A SiP power converter according to these techniques and circuits can, not only fit within a smaller package size that costs less to produce than some other converters, but the SiP power converter according to these circuits and techniques can operate more efficiently and provide a more controlled and accurate power output than some converters by using FET or SFET type switches at one die while simultaneously using highly accurate sense-FET current sensing at the other die.

Clause 1. A power converter comprising: a first die including one or more first switches coupled to a switching node of a power stage; and a second die including: one or more second switches coupled to the switching node of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage to produce a power output at the switching node of the power stage.

Clause 2. The power converter of clause 1, wherein the one or more first switches comprise one or more high-side switches of a half-bridge of the power stage and the one or more second switches comprise one or more low-side switches of the half-bridge of the power stage.

Clause 3. The power converter of any of clauses 1-2, wherein the one or more second switches comprise one or more high-side switches of a half-bridge of the power stage and the one or more first switches comprise one or more low-side switches of the half-bridge of the power stage.

Clause 4. The power converter of any of clauses 1-3, wherein the second die further includes a feedback control unit configured to detect a current level at the one or more second switches of the power stage, wherein the controller unit is further configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.

Clause 5. The power converter of clause 4, wherein the feedback control unit is further configured to detect the current level at the one or more second switches based on a sense-FET current sensing signal.

Clause 6. The power converter of clause 5, wherein the second die further includes: one or more sense lines contained to the second die that couple the feedback control unit to the one or more second switches of the power stage, the one or more sense lines being configured to transmit information associated with a current or voltage level of the power stage to the feedback control unit.

Clause 7. The power converter of clause 6, wherein the one or more sense lines are further configured to transmit a sense-FET current sensing signal associated with a current level detected at the one or more second switches to the feedback control unit

Clause 8. The power converter of any of clauses 1-7, wherein the feedback control unit is further configured to detect a voltage or current level of a power output of the power converter, and wherein the controller unit is further configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the voltage or current level of the power output detected by the feedback control unit.

Clause 9. The power converter of any of clauses 1-8, wherein the first die is a FET or SFET type die.

Clause 10. The power converter of any of clauses 1-9, wherein the one or more first switches are SFET type switches.

Clause 11. The power converter of any of clauses 1-10, wherein the second die is a CMOS type die.

Clause 12. The power converter of any of clauses 1-11, wherein the one or more second switches are CMOS type switches.

Clause 13. The power converter of any of clauses 1-12, wherein the second die further includes at least one first driver configured to control the one or more first switches and at least one second driver further configured to control the one or more second switches.

Clause 14. The power converter of any of clauses 1-13, wherein the power converter comprises a step-down converter, wherein the power output comprises at a first voltage level that does not exceed a second voltage level of a power input received at the half bridge.

Clause 15. The power converter of any of clauses 1-14, wherein the power converter comprises a step-up converter, wherein the power output comprises a first voltage level that meets or exceeds a second voltage level of a power input received at the half bridge.

Clause 16. The power converter of any of clauses 1-15, wherein the controller unit is further configured to output at least one of a pulse-density-modulation signal, a pulse width modulation signal, and a pulse frequency modulation signal for controlling the one or more first switches and the one or more second switches of the power stage.

Clause 17. The power converter of any of clauses 1-16, wherein the power stage comprises a single phase half-bridge, wherein the one or more first switches comprise a single high-side switch of the single phase half-bridge and the one or more second switches comprise a single low-side switch of the single phase half-bridge.

Clause 18. The power converter of any of clauses 1-17, wherein the power stage comprises a multiple phase half-bridge, wherein the one or more first switches comprise two or more high-side switches of the multiple phase half-bridge and the one or more second switches comprise two or more low-side switches of the multiple phase half-bridge.

Clause 19. A method comprising: detecting, by a feedback control unit at a second die of a power converter, a current level at one or more second switches at the second die of the power converter, the one or more second switches being coupled to one or more first switches at a first die of the power converter at a switching node of a power stage; controlling, by a controller unit at the second die, the one or more first switches of the power stage at the first die based at least in part on a driver signal, wherein the driver signal is based at least in part on the current level detected at the one or more second switches at the second die; and controlling, by the controller unit at the second die, the one or more second switches of the power stage at the second die based at least in part on the driver signal.

Clause 20. A power converter comprising: means for detecting a current level at one or more second switches at a second die of a power converter, the one or more second switches being coupled to one or more first switches at a first die of the power converter at a switching node of a power stage; means for controlling, from the second die, the one or more first switches of the power stage at the first die based at least in part on a driver signal, wherein the driver signal is based at least in part on the current level detected at the one or more second switches at the second die; and means for controlling, from the second die, the one or more second switches of the power stage at the second die based at least in part on the driver signal.