Resistance variable memory structure and method of forming the same

A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. A portion of the resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode embedded in the dielectric layer. A resistance variable layer disposed over the first electrode and a portion of the dielectric layer. A second electrode disposed over the resistance variable layer.

TECHNICAL FIELD

This disclosure relates generally to a semiconductor structure and, more particularly, to a resistance variable memory structure and method for forming a resistance variable memory structure.

BACKGROUND

In integrated circuit (IC) devices, resistive random access memory (RRAM) is an emerging technology for next generation non-volatile memory devices. RRAM is a memory structure including an array of RRAM cells each of which stores a bit of data using resistance values, rather than electronic charge. Particularly, each RRAM cell includes a resistance variable layer, the resistance of which can be adjusted to represent logic “0” or logic “1”.

From an application point of view, RRAM has many advantages. RRAM has a simple cell structure and CMOS logic comparable processes which result in a reduction of the manufacturing complexity and cost in comparison with other non-volatile memory structures. Despite the attractive properties noted above, a number of challenges exist in connection with developing RRAM. Various techniques directed at configurations and materials of these RRAMs have been implemented to try and further improve device performance.

DETAILED DESCRIPTION

According to one or more embodiments of this disclosure, a semiconductor structure includes a resistance variable memory structure. The resistance variable memory structure includes a resistance variable layer formed between two electrodes. By applying a specific voltage to each of the two electrodes, an electric resistance of the resistance variable layer is altered. The low and high resistances are utilized to indicate a digital signal “1” or “0”, thereby allowing for data storage. The switching behavior does not depend only on the materials of the resistance variable layer but also depends on the choice of electrodes and interfacial properties of the electrodes.

According to one or more embodiments of this disclosure, the semiconductor structure having a resistance variable memory structure is formed within a chip region of a substrate. A plurality of semiconductor chip regions is marked on the substrate by scribe lines between the chip regions. The substrate will go through a variety of cleaning, layering, patterning, etching and doping steps to form the semiconductor structures. The term “substrate” herein generally refers to a bulk substrate on which various layers and device structures are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor, such as GaAs, InP, Si/Ge, or SiC. Examples of such layers include dielectric layers, doped layers, polysilicon layers or conductive layers. Examples of device structures include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additional integrated circuits.

FIG. 1is a flowchart of a method100of forming a semiconductor structure having a resistance variable memory structure according to one or more embodiments of this disclosure.FIGS. 2A to 2Iare cross-sectional views of semiconductor structures200A and200B each having a resistance variable memory structure at various stages of manufacture according to various embodiments of the method100ofFIG. 1. It should be noted that additional processes may be provided before, during, or after the method100ofFIG. 1. Various figures have been simplified for a better understanding of the inventive concepts of the present disclosure.

Referring now toFIG. 1, the flowchart of the method100begins with operation102. An opening is formed in a dielectric layer. The dielectric layer has a top surface. The dielectric layer is formed on a substrate having at least one conductive structure on a top portion of the substrate. In at least one embodiment, the opening is etched from the top surface of the dielectric layer to expose a portion of the at least one conductive structure.

Referring toFIG. 2A, which is an enlarged cross-sectional view of a portion of a semiconductor structure200A having a resistance variable memory structure after performing operation102. The semiconductor structure200A includes a substrate (not shown) such as a silicon carbide (SiC) substrate, GaAs, InP, Si/Ge or a silicon substrate. The substrate may include a plurality of layers formed on a top portion of the substrate. Examples of such layers include dielectric layers, doped layers, polysilicon layers or conductive layers. The substrate may further include a plurality of device structures formed within the plurality of layers. Examples of device structures include transistors, resistors, and/or capacitors.

In the illustrated examples ofFIGS. 2A-2I, the semiconductor structures200A and200B include a conductive structure202formed on the top portion of the substrate (not shown). The conductive structure202may include a conductive interconnect, a doped region or a silicide region. In some embodiments, the conductive structure202may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN or silicon. The conductive structure202is formed by a suitable process, including deposition, lithography patterning, doping, implanting, or etching processes.

A dielectric layer204is deposited over the conductive structure202. The dielectric layer204has a top surface204A. The dielectric layer204comprises silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, silicon nitride, silicon oxynitride, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, or combinations thereof. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD) or spinning on glass.

An opening206is etched in the dielectric layer204extending from the top surface204A to a top surface of the conductive structure202to expose a portion of the conductive structure202. The opening206has sidewalls and a width W1. The opening206is formed by suitable process, including lithography patterning, and etching processes.

FIG. 2Bis a cross-sectional view of the semiconductor structure200A after a barrier layer208is optionally formed in the opening206. The barrier layer208comprises at least one of TiN, Ti, Ta, TaN, W or WN. In at least one embodiment, a barrier material may overfill the opening206in the dielectric layer204. Possible formation methods include electroless plating, sputtering, electro plating, physical vapor deposition (PVD) or CVD. The excess barrier material outside the opening206is removed through a suitable process such as chemical mechanical polishing (CMP) or planarization etching back process.

FIG. 2Cis a cross-sectional view of the semiconductor structure200A after a top portion of the barrier layer208is removed from the opening206. An etching process is performed to remove the top portion of the barrier layer208and leave a remained portion of the barrier layer208filled in a bottom section of the opening206. The etching process may include a dry etching process, wet etching process, or a combination thereof.

Referring back toFIG. 1, the method100continues with operation104in which the opening is filled with a first electrode material substantially to the top surface of the dielectric layer.

FIG. 2Dis a cross-sectional view of the semiconductor structure200A after performing operation104. A first electrode210is filled in the opening206overlying the barrier layer208. The first electrode210includes a first electrode conductive material having a proper work function such that a high work function wall is built between the first electrode210and a resistance variable layer subsequently formed. The first electrode210may comprise Pt, AlCu, TiN, Au, Ti, Ta, TaN, TaN, W, WN or Cu. In at least one embodiment, a first electrode conductive material may overfill the opening206of the dielectric layer204inFIG. 2C. Possible formation methods include electroless plating, sputtering, electro plating, PVD or ALD. Then, the excess first electrode conductive material outside the opening206is removed through a suitable planarization process such as CMP or planarization etching back process. The first electrode210is formed in a top section of the opening206, and embedded in the dielectric layer204. The first electrode210has a top surface210A substantially coplanar to the top surface204A of the dielectric layer204. Since the barrier layer208and the first electrode210are formed in the same opening206, the barrier layer208and the first electrode210have a substantially same width W1as the opening206and aligned sidewalls. The conductive structure202is electrically connected to the first electrode210through the barrier layer208.

The barrier layer208deposited on the conductive structure202and under the first electrode210is designed to prevent inter-mixing of the materials in the conductive structure202and the first electrode210. The barrier layer208prevents diffusion between the conductive structure202and the first electrode210and any junction spiking. The electrical performances the semiconductor structure200A is thus improved.

Referring back toFIG. 1, method100continues with operations106and108. In operation106, a resistance variable layer is deposited over the first electrode material. In operation108, a second electrode material is deposited over the resistance variable layer.

FIG. 2Eis a cross-sectional view of the semiconductor structure200A after performing operations106and108. A resistance variable layer212is deposited over the first electrode210and the dielectric layer204. The resistance variable layer212has a resistivity capable of switching between a high resistance state and a low resistance state (or conductive), by application of an electrical voltage. In various embodiments, the resistance variable layer212includes dielectric materials comprising a high-k dielectric material, a binary metal oxide or a transition metal oxide. In some embodiments, the resistance variable layer212includes nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide or copper oxide. Possible formation methods include PVD or ALD, such as ALD with a precursor containing zirconium and oxygen. In one example, the resistance variable layer212has a thickness in a range from about 20 angstrom to about 200 angstrom.

A second electrode material214is deposited over the resistance variable layer212. The second electrode material214may include suitable conductive material to electrically connect a subsequently formed resistance variable memory structure to other portions of an interconnect structure for electrical routing. The second electrode material214may comprise Pt, AlCu, TiN, Au, Ti, Ta, TaN, TaN, W, WN or Cu. In some embodiments, the first electrode material210and the second electrode material214have a same composition. In some embodiments, the first electrode material210and the second electrode material214have different compositions. Possible formation methods include electroless plating, sputtering, electro plating, PVD or ALD.

In some examples, the semiconductor structure200A may further includes a cap layer213optionally formed on the resistance variable layer212and underlying the second electrode material214as shown inFIG. 2I. The cap layer includes a conductive material that is unstable, capable of depriving oxygen from the resistance variable layer212, and creates vacancy defects in the resistance variable layer212. The cap layer comprises titanium, tantalum or hafnium.

Referring back toFIG. 1, the method100continues with operation110in which the second electrode material and the resistance variable layer are etched to form a resistance variable memory structure.

FIGS. 2F and 2Gare cross-sectional views of the semiconductor structure200A after performing operation110. InFIG. 2F, a mask layer216having a feature with a width W2is formed over the second electrode material214. The feature is formed by suitable process, including deposition, lithography patterning, and/or etching processes. In at least one embodiment, the feature of the mask layer216overlies the first electrode210and covers a region having the width W2wider than the width W1of the first electrode210. An etching process is performed to remove the second electrode material214and the resistance variable layer212not underlying the mask layer216. Then, a second electrode214A is defined and a resistance variable memory structure250A is formed. Since the second electrode material214and the resistance variable layer212are covered and etched under the same mask layer216, the second electrode214A and the patterned resistance variable layer212have a substantially same width W2wider than the width W1of the first electrode210. Also, the second electrode214A and the patterned resistance variable layer212have substantially aligned sidewalls.

In certain embodiments, the feature of the mask layer216overlies the first electrode210and covers a region having the width W2less than the width W1of the first electrode210. The second electrode214A and the patterned resistance variable layer212have a substantially same width W2less than the width W1of the first electrode210.

FIG. 2Gillustrates a cross-sectional view of the semiconductor structure200A after the mask layer216is removed and a top surface of the second electrode214A of the resistance variable memory structure250A is exposed. The removing process may include a dry etching process, wet etching process, or combination thereof.

FIG. 2His a cross-sectional view of the semiconductor structure200B having another resistance variable memory structure250B according to various embodiments of the method100ofFIG. 1. The layer stacks and manufacture methods of the semiconductor structure200B are similar to the semiconductor structure200A. However, the resistance variable memory structure250B in the semiconductor structure200B does not include the barrier layer208of the semiconductor structure200A. The conductive structure202is electrically connected directly to the first electrode210.

FIG. 3is an enlarged cross-sectional view of the semiconductor structure200A having a resistance variable memory structure250A in various operations for data storage. In a “forming” operation, a “forming” voltage is applied to the first and second electrodes210and214A of the resistance variable memory structure. The “forming” voltage is high enough to generate a conductive portion in the resistance variable layer212. In one example, the conductive portion includes one or more conductive filaments300to provide a conductive path such that the resistance variable layer212shows an “on” or low resistance state. The conductive path may be related to the lineup of the defect (e.g. oxygen) vacancies in the resistance variable layer212. In some embodiments, the “forming” voltage is applied only one time. Once the conductive path is formed, the conductive path will remain present in the resistance variable layer212. Other operations may disconnect or reconnect the conductive path using smaller voltages or different voltages.

In a “set” operation, a “set” voltage high enough to reconnect the conductive path in the resistance variable layer212is applied to the resistance variable memory structure250A such that the resistance variable layer212shows the “on” or low resistance state. The “set” operation turns the resistance variable layer212to the low resistance state.

In a “reset” operation, a “reset” voltage high enough to break the conductive path in the resistance variable layer212is applied to the resistance variable memory structure250A such that the resistance variable layer212shows an “off” or high resistance state. By applying a specific voltage between two electrodes210and214A, an electric resistance of the resistance variable layer212is altered after applying the specific voltage. The low and high resistances are utilized to indicate a digital signal “1” or “0”, thereby allowing for data storage.

Various embodiments of the present disclosure may be used to improve the performance of a resistance variable memory structure. For example, the first electrode210is formed by a filling process in the opening206in operation104. The second electrode214A is formed by an etching process in operation110. The disclosed method includes a single etching process (in operation110) used to form both electrodes210and214A. This disclosure eliminates drawbacks in conventional methods such as etching damage to the resistance variable layer212due to multiple etching steps in patterning both the first and second electrodes210and214A which leads to long exposure times in plasma environments. Without etching damages in the resistance variable layer212, a possible leakage current in the resistance variable memory structures250A and250B is reduced.

In another example, an operation current of the resistance variable memory structure (250A or250B) is related to an area of the conductive paths (or conductive filaments300) in the resistance variable layer212. The area of the conductive paths (or conductive filaments300) is confined within the width W1of the first electrode210and the width W2of the second electrode214A after the “forming” operation. The smaller of either the width W1or the width W2dictates a width of the area of the conductive paths in the resistance variable layer212. As lithography patterning processes continue shrinking the width W1and the width W2, the operation current of the resistance variable memory structure (250A or250B) also is capable of being further reduced. In this disclosure, the width W1is decided by the lithography patterning and etching processes capability to from the opening206in operation102. Also, the width W1of the first electrode210is decided in the operation102. In a view of the lithography patterning and etching processes, reducing a size of the dimension of an opening (or etched portion) in a material layer is simpler than reducing the dimension of a feature (or remained portion) in a material layer. In this disclosure, the width W1of the first electrode210is decided in the opening206. This disclosure provides an effective technique to facilitate scaling down of the resistance variable memory structure (250A or250B), and also reduction of the operation current.

One aspect of the disclosure describes a semiconductor structure including a resistance variable memory structure. The semiconductor structure includes a dielectric layer. At least a portion of the resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode embedded in the dielectric layer. A resistance variable layer disposed over the first electrode and a portion of the dielectric layer. A second electrode disposed over the resistance variable layer.

A further aspect of the disclosure describes a semiconductor structure including a resistance variable memory structure. The semiconductor structure includes a conductive structure. A barrier layer disposed over the conductive structure. The resistance variable memory structure is over the barrier layer. The resistance variable memory structure includes a first electrode disposed over the barrier layer. The barrier layer and the first electrode have a substantially same width W1. A resistance variable layer disposed over the first electrode. A second electrode disposed over the resistance variable layer. The resistance variable layer and the second electrode have a substantially same width W2different from the width W1.

The present disclosure also describes an aspect of a method of forming a resistance variable memory structure. The method includes forming an opening in a dielectric layer. The dielectric layer has a top surface. The opening is filled with a first electrode material substantially to the top surface. A resistance variable layer is deposited over the first electrode material. A second electrode material is deposited over the resistance variable layer. The resistance variable layer and the second electrode material are etched to form a resistance variable memory structure.

Although the embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.