RRAM DEVICE AS PHYSICAL UNCLONABLE FUNCTION DEVICE AND MANUFACTURING METHOD

A resistive random access memory array includes a plurality of memory cells. Each memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element. The resistive random access memory array is used to generate physical unclonable function data.

BACKGROUND

Technical Field

The present disclosure relates to the field of integrated circuits. The present disclosure relates more particularly integrated circuits including memory arrays used for generating physically unclonable functions.

Description of the Related Art

An electronic device that includes an integrated circuit may use the integrated circuit to generate a physically unclonable function that can be used to authenticate the electronic device. Physically unclonable functions are based on physical and electrical characteristics of an integrated circuit that result from variations that occur during fabrication of the integrated circuit. These variations result in a unique electronic fingerprint for the device that can be used as a physically unclonable function.

DETAILED DESCRIPTION

In the following description, many thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example for various embodiments. Those of skill in the art will recognize, in light of the present disclosure, that other dimensions and materials can be used in many cases without departing from the scope of the present disclosure.

Embodiments of the present disclosure provide a resistive random access memory (RRAM) array including a plurality of RRAM cells. The RRAM array can be used to generate physically unclonable function (PUF) data for an electronic device. The manufacturing process of the RRAM array will result in the RRAM array having unique electrical and physical characteristics based on natural variations in the fabrication process. These unique electrical physical characteristics utilized to generate PUF data that is unique to the RRAM array. An electronic device that includes the RRAM array can utilize the PUF data for authentication purposes.

The RRAM array includes a plurality of RRAM cells. Each memory cell includes a gate all around nanosheet transistor and a resistor device. The resistor device includes similar structures to the gate all around transistor and can be formed in the same processing steps. The resistor device includes a dielectric layer that acts as an adjustable resistor and memory storage element of the memory cell. The fabrication of the memory cells results in resistor devices having selected different characteristics based on the natural structural variations that occur during the fabrication process. Embodiments of the present disclosure provide many benefits over traditional PUF devices. The transistor and the resistor device are formed with many of the same structures in overlapping process steps. This reduces the number of additional steps and provides a resistor device with feature sizes and area footprints approximately the same as very small nanosheet transistors.

FIG.1is a block diagram of a PUF authentication system100, according to one embodiment. The PUF authentication system100includes an electronic device101electronic device101includes an integrated circuit103. The integrated circuit103includes an RRAM memory array105and a memory controller107. The unique physical characteristics of the RRAM memory array104can be utilized to generate a PUF that can be used as a unique identifier to authenticate the electronic device104. Details regarding the fabrication process of the memory cells of the RRAM memory array105are provided in relation toFIGS.2A-2N.

In some embodiments, the electronic device101is a personal electronic device such as a mobile phone, a tablet, a laptop computer, or another type of personal electronic device. In various circumstances such electronic devices may need to be authenticated in order to receive services, to receive or make purchases, or for other reasons. The RRAM array105can be utilized to generate the PUF in order to facilitate secure authentication.

In some embodiments, the electronic device101takes part in the Internet of things. The electronic device101can include a medical device, a smart appliance, a vehicle, part of a security system, part of a vehicle identification system, part of an agricultural monitoring system, an energy management system, or any type of device for which authentication is utilized.

The RRAM array105includes memory cells arranged in rows and columns. Each memory cell can story a binary logic value such as a logical 0 or a logical 1. The memory controller107reads data from the memory cells, writes data to the memory cells, and erases the memory cells of the RRAM array105. Accordingly, the memory controller107manages the storage of data and the retrieval of data from the RRAM array105. In some embodiments, the memory controller107may not be part of the same integrated circuit103as the RRAM array105. Alternatively, the memory controller107may be part of a different integrated circuit of the electronic device101.

The PUF generator109is a device or system that is utilized specifically to generate and store a PUF associated with the electronic device101. After assembly of the electronic device101, including installation of the integrated circuit103, the PUF generator109is communicatively connected to the electronic device101. The PUF generator109can be connected to the electronic device101by wired connections or via wireless connections.

During the PUF generation process, the PUF generator109provides instructions to the memory controller107of the integrated circuit103. The instructions include challenges to apply to the RRAM array in order to generate initial PUF data for later authentication. The challenges are designed to detect unique electrical or physical characteristics of the RRAM array. In one example, the challenges can include recording the duration of read operations associated with each of a plurality of memory cells of the RRAM array. Slight variations in physical structure of the memory cells, as well as interconnection structures coupled to the memory cells, will result in slightly different read times for the various memory cells of the RRAM array105. The different read times for each of a plurality of memory cells can be utilized to generate a PUF for the electronic device. The PUF generator109controls or instructs the memory array108to read data from each of a plurality of memory cells of the RRAM array and to provide the read time associated with each of the memory cells.

In another example, the initial condition of the RRAM array105upon startup can be utilized to generate initial PUF data. Based on the natural variations that occur during fabrication of the RRAM array105, each memory cell of the RRAM array may resolve to a particular data value at startup. The PUF generator109can cause the memory controller107to read data values from each of the memory cells of the RRAM array105at startup prior to writing or erasing any data from the RRAM array105. Because the memory cells will result in the same data values upon each startup, the distribution of these values can be utilized to generate initial PUF data to authenticate the electronic device101. The PUF generator109can control the memory controller107to generate the initial PUF data on this basis.

In another example, writing or erasing procedures can be utilized to generate initial PUF data from the RRAM array105. In this case, the PUF generator109can cause the memory controller107to do a thorough erase operation of the entire RRAM array105. The PUF generator109can then cause the memory controller107to cycle through a portion of a write operation for each of the memory cells. As will be set forth in more detail below, writing data to an RRAM cell includes performing a DC sweep in which one electrode of the memory cell is held at a particular voltage while another electrode of the memory cell undergoes a DC sweep to a higher voltage or a lower voltage. The PUF generation procedure can include performing a DC sweep to a voltage with a magnitude that is somewhat lower than standard write operations. Based on the physical characteristics of each memory cell, this partial write procedure will succeed or fail in writing data to the memory cell. After the partial writing operation, the PUF generator109can control the memory controller107to read data from the memory cells. The distribution of data value stored in the memory cells corresponds to a unique electronic fingerprint of the RRAM array104and, correspondingly, the electronic device101.

The PUF generator109can generate the initial PUF data based on one or more of the techniques described above, or based on other techniques described herein. The higher the number of techniques utilized to generate the PUF, the stronger the security of the PUF authentication for the electronic device101.

The PUF generator109can store the initial PUF data associated with the RRAM array105in a database113. The database113can include a secure database utilized for authentication purposes for electronic devices. The PUF generator109can store the initial PUF data of the electronic device101in the database113via one or more networks111. The one or more networks111can include one or more of the Internet, wide area networks, local area networks, intranets, or other types of networks.

After the initial PUF authentication data has been stored in the database113, the electronic device101can utilize the initial PUF data for authentication. In particular, when the electronic device101undergoes an authentication process, an authentication system115can reproduce the interrogations that were utilized by the PUF generator109in initially generating the PUF data. The authentication system115causes the memory controller107to perform the same operations and provide the same data that is utilized to generate the initial PUF data. The authentication system115then compares the data to the PUF data stored in the database113. If the newly received data matches initial the PUF data stored in the database113, then the electronic device101is authenticated. Other types of PUF based authentication processes can be utilized in conjunction with the RRAM array105without departing from the scope of the present disclosure.

In some embodiments, after the initial PUF authentication data has been generated, the authentication system115provides an authentication request to the electronic device101. The authentication request may be responsive to an access request from the electronic device101. The electronic device101interrogates the RRAM array105responsive to the authentication request. The interrogation request the same types of data or signals that were utilized in generating the initial authentication data. The RRAM array105outputs signals responsive to the interrogation. The memory controller107, or another component of the electronic device101or the authentication system115generates PUF data from the signals provided by the RRAM array. The authentication system115then compares the PUF data provided by the electronic device101to the initial PUF data stored in the database113. If the PUF data matches the initial PUF data stored in the database113, then the authentication system115authenticates the electronic device101. The memory controller107or other components of the electronic device101can perform the interrogation of the RRAM array105.

FIGS.2A-2Nare cross-sectional views of an integrated circuit103at successive intermediate stages of processing, according to some embodiments. The integrated circuit103is one example of the integrated circuit103utilize an electronic device101ofFIG.1. More particularly,FIGS.2A-2Nillustrate an exemplary process for producing an RRAM memory cell of the RRAM array105ofFIG.1. The RRAM memory cell includes a gate all around transistor and a resistor device that includes the memory storage element of the memory cell.FIGS.2A-2Nillustrate how the memory cell can be formed in a simple and effective process in accordance with principles of the present disclosure. Other process steps and combinations of process steps can be utilized without departing from the scope of the present disclosure.

FIG.2Ais a cross-sectional diagram of an integrated circuit103at an intermediate stage of processing, according to some embodiments. The view ofFIG.2Aillustrates a transistor102and a resistor device104at an intermediate stage of processing. Accordingly, the transistor102and the resistor device104are not yet fully formed in the view ofFIG.2A. As will be set forth in more detail below, the resistor device104shares many of the same structures as the transistor102. Accordingly, the process for forming the transistor102and the resister104heavily overlap, thereby reducing the number of process steps utilized to form then resistor device. Additionally, the resistor device can be formed with a very small area footprint because the resistor device104is formed with a same or similar area footprint as the very small transistor102.

The transistors102is a gate all around transistor. The gate all around transistor structure may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.

InFIGS.2A-2G, the transistor102and the resistor device104have the same or substantially similar structures and undergo the same processing steps, in accordance with one embodiment. Accordingly, the description ofFIGS.2A-2Gwill refer primarily to the transistor102, however, it will be understood that the same structures may be present within the resistor device104as illustrated. In other embodiments, the transistor102and the resistor device104may have different structures and undergo different processing steps.

The integrated circuit103includes a semiconductor substrate106. In the example ofFIG.2A, the semiconductor substrate106includes a first semiconductor layer112, a second semiconductor layer114on the first semiconductor layer112, and a third semiconductor layer116on the second semiconductor layer114. In some embodiments, the first semiconductor layer112includes silicon; however, embodiments of the present disclosure are not limited thereto, and in various embodiments, the first semiconductor layer may include any suitable semiconductor material. The second semiconductor layer114can include silicon germanium. The third semiconductor layer116can include silicon. The first, second, and third semiconductor layers112,114, and116can collectively act as a semiconductor substrate106. The semiconductor substrate106can include different numbers of layers in different semiconductor materials than those shown inFIG.2Aand described above without departing from the scope of the present disclosure. The semiconductor substrate106can include various doped regions including N-type and P-type dopants. N-type dopants can include phosphorus. P-type dopants can include boron. Other types of dopants can be utilized without departing from the scope of the present disclosure.

The integrated circuit103includes a shallow trench isolation118. The shallow trench isolation118can be utilized to separate one or more semiconductor device structures, such as the transistor102and the resistor104, formed on or in conjunction with the semiconductor substrate106. The shallow trench isolation118can include a dielectric material. For example, in some embodiments, the shallow trench isolation118includes a trench that is formed extending into the semiconductor substrate106, and a dielectric material that fills or substantially fills the trench. The dielectric material for the shallow trench isolation118may include silicon oxide, silicon nitride, silicon oxynitride (SON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. Other materials and structures can be utilized for the shallow trench isolation118without departing from the scope of the present disclosure.

The integrated circuit103includes a plurality of semiconductor nanosheets120or nanowires. The semiconductor nanosheets120are layers of semiconductor material. The semiconductor nanosheets120correspond to the channel regions of the gate all around transistors that will result from the process described. The semiconductor nanosheets120are formed over the substrate106, and may be formed on the semiconductor substrate106. The semiconductor nanosheets120may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In at least one embodiment, the semiconductor nanosheets120are the same semiconductor material as the substrate102, Other semiconductor materials can be utilized for the semiconductor nanosheets120without departing from the scope of the present disclosure. In a non-limiting example described herein, the semiconductor nanosheets120and the substrate102are silicon.

The integrated circuit103includes a plurality of sacrificial semiconductor nanosheets122positioned between the semiconductor nanosheets120. The sacrificial semiconductor nanosheets122include a different semiconductor material than the semiconductor nanosheets120. In an example in which the semiconductor nanosheets120include silicon, the sacrificial semiconductor nanosheets122may include Site. In one example, the silicon germanium sacrificial semiconductor nanosheets122may include between 20% and 30% germanium, though other concentrations of germanium can be utilized without departing from the scope of the present disclosure.

In some embodiments, the semiconductor nanosheets120and the sacrificial semiconductor nanosheets122are formed by alternating epitaxial growth processes from the third semiconductor layer116. For example, a first epitaxial growth process may result in the formation of the lowest sacrificial semiconductor nanosheet122on the top surface of the third semiconductor layer116, A second epitaxial growth process may result in the formation of the lowest semiconductor nanosheet120on the top surface of the lowest sacrificial semiconductor nanosheet122. A third epitaxial growth process results in the formation of the second lowest sacrificial semiconductor nanosheet122on top of the lowest semiconductor nanosheet120. Alternating epitaxial growth processes are performed until a selected number of semiconductor nanosheets120and sacrificial semiconductor nanosheets122have been formed.

InFIG.2A, the transistor102has three semiconductor nanosheets120. However, in practice, the transistor102may have more semiconductor nanosheets120than three. For example, the transistor102may include between 8 and 20 semiconductor nanosheets120in some embodiments. Other numbers of semiconductor nanosheets120can be utilized without departing from the scope of the present disclosure.

The semiconductor nanosheets120can have thicknesses between 2 nm and 100 nm. In some embodiments, the semiconductor nanosheets120have thicknesses between 2 nm and 20 nm. This range provides suitable conductivity through the nanosheets while retaining a low thickness. In some embodiments, each nanosheet120is thicker than the nanosheet(s)120above ft. The semiconductor nanosheets120can have other thicknesses without departing from the scope of the present disclosure.

InFIG.2Aa dummy gate124has been deposited and patterned on the top semiconductor nanosheet120. The dummy gate124can include polysilicon. The dummy gate124can have a thickness between 20 nm and 100 nm. The polysilicon dummy gate can be deposited by an epitaxial growth, a CVD process, a physical vapor deposition (PVD) process, or an ALD process. Other thicknesses and deposition processes can be used for depositing the material of the dummy gate124without departing from the scope of the present disclosure.

The dummy gate124can be patterned by standard photolithography processes. For example, the dummy gate124can be patterned by etching the dummy gate124in the presence of the photoresist mask, a hard mask, or other types of masks.

InFIG.2A, a gate spacer126has been deposited on the sides of the dummy gate124. In one example, the gate spacer126includes SiCON. The gate spacer126can be deposited by CVD, PVD, or ALD. Other materials and deposition processes can be utilized for the gate spacer126without departing from the scope of the present disclosure.

InFIG.2B, the semiconductor nanosheets120and the sacrificial semiconductor nanosheets122have been etched. The dummy gate124and the gate spacer126have been used as a mask to pattern the semiconductor nanosheets120and the sacrificial semiconductor nanosheets122. In particular, an etching process has been performed in the presence of the dummy gate124and the gate spacer126to etch the semiconductor nanosheets120and the sacrificial semiconductor nanosheets122.

InFIG.2Cthe etching process has been performed to laterally recess the sacrificial semiconductor nanosheets122with respect to the semiconductor nanosheets120, The etching process can be performed by a chemical bath that selectively etches the sacrificial semiconductor nanosheets122with respect to the semiconductor nanosheets120. As described previously, in one example the sacrificial semiconductor nanosheets122are Site. This difference in composition from the semiconductor nanosheets120allows the sacrificial semiconductor nanosheets122to be selectively etched with respect to the semiconductor nanosheets120. Accordingly, the etching process ofFIG.2Crecesses the sacrificial semiconductor nanosheets122without significantly etching the semiconductor nanosheets120. The etching process is timed so that the sacrificial semiconductor nanosheets122are recessed but not entirely removed. The recessing process is utilized to enable the formation of an inner sheet spacer layer between the semiconductor nanosheets120at the locations where the sacrificial semiconductor nanosheets122have been removed.

InFIG.2Da sheet inner spacer layer128has been formed (e.g., by deposition) between the semiconductor nanosheets120. The sheet inner spacer layer128can be deposited by an ALD process, a CVD process, or other suitable processes. In one example, the sheet inner spacer layer128includes silicon nitride. After formation of the sheet inner spacer layer128, and etching processes may be performed utilizing the gate spacer126as a mask. The etching process removes the sheet inner spacer layer128except directly below the gate spacer126. Other processes and materials can be utilized for the sheet inner spacer layer128without departing from the scope of the present disclosure.

InFIG.2Dsource and drain regions130have been formed. The source and drain regions130includes semiconductor material. The source and drain regions130can be grown epitaxially from the semiconductor nanosheets120. The source and drain regions130can be epitaxially grown from the semiconductor nanosheets120or from the substrate102. The source and drain regions130can be doped with N-type dopants species in the case of N-type transistors. The source and drain regions130can be doped with P-type dopant species in the case of P-type transistors. The doping can be performed in-situ during the epitaxial growth. While the source and drain regions130are labeled with a common reference number and title, in practice, the transistor102will have a source region and the drain region. For example, the region130on the left of the transistor102may correspond to a source of the transistor102. The region on the right of the transistor102may correspond to a drain of the transistor102. Alternatively, the drain may be on the left and the source may be on the right.

InFIG.2Ean interlevel dielectric layer132has been deposited on the source and drain regions130and on the shallow trench isolation118. The interlevel dielectric layer132can include silicon oxide. The interlevel dielectric layer132can be deposited by CVD, ALD, or other suitable processes. After deposition of the interlevel dielectric layer132, a CMP process can be performed to planarize the top surface of the interlevel dielectric layer132and to make the top surface of the interlevel dielectric layer132at the same level as the top surface of the dummy gate124and the gate spacer126. Other materials and processes can be utilized for the interlevel dielectric layer132without departing from the scope of the present disclosure.

InFIG.2F, the dummy gate124and the sacrificial semiconductor nanosheets122have been removed. The dummy gate124can be removed in a first etching step. The sacrificial semiconductor nanosheets122can then be removed in a second etching step. Both the first and the second etching steps selectively etches the corresponding layer with respect to the material of the semiconductor nanosheets120. Alternatively, a single etching process can be utilized to remove both the sacrificial semiconductor cladding114and the sacrificial semiconductor nanosheets122.

The removal of the dummy gate124leaves a gate trench134. The gate trench134corresponds to the location at which the portion of the gate electrode of the transistor102will be formed. The removal of the sacrificial semiconductor nanosheets122leaves a gap136around the semiconductor nanosheets120. In practice, the gate trench134and the gap136are contiguous with each other such that the gate trench134and the gaps136are a single contiguous void at the stage shown inFIG.2F.

InFIG.2Gan interfacial dielectric layer138has been deposited on the exposed surfaces of the semiconductor nanosheets120. The interfacial dielectric layer138can include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial dielectric layer138can include a comparatively low-K dielectric with respect to high-K dielectrics such as hafnium oxide or other high-K dielectric materials that may be used in gate dielectrics of transistors. The interfacial dielectric layer138can be formed by a thermal oxidation process, a CVD process, or an ALD process. The interfacial dielectric layer138can have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses can be utilized for the interfacial dielectric layer without departing from the scope of the present disclosure.

The interfacial dielectric layer138surrounds the semiconductor nanosheets120. In particular, the semiconductor nanosheets120have a shape corresponding to a slat or wire extending between the source and drain regions130. The interfacial dielectric layer138wraps around each semiconductor nanosheet120. The interfacial dielectric layer138surrounds or partially surrounds the semiconductor nanosheets120.

InFIG.2G, a high-K gate dielectric layer140has been formed on the interfacial dielectric layer138, on the sidewalls of the gate spacers126, and on the sidewalls of the sheet inner spacers128. Together, the high-K gate dielectric layer140and the interfacial dielectric layer138correspond to a gate dielectric of the transistor102. The high-K dielectric layer140surrounds or partially surrounds the semiconductor nanosheets120in the same way as described in relation to the interfacial dielectric layer138, except that the interfacial dielectric layer is between the semiconductor nanosheets120and the high-K gate dielectric layer140.

The high-K gate dielectric layer140includes one or more layers of a dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The high-K gate dielectric layer140may be formed by CVD, ALD, or any suitable method. In some embodiments, the high-K gate dielectric layer140is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each semiconductor nanosheet104. In some embodiments, the thickness of the high-k dielectric layer140is in a range from about 1 nm to about 4 nm. Other thicknesses, deposition processes, and materials can be utilized for the high-K gate dielectric layer without departing from the scope of the present disclosure. The high-K gate dielectric layer140may include a first sub-layer that includes HfO2 with dipole doping including La and Mg, and a second sub-layer including a higher-K ZrO layer with crystallization. In particular, the first sub-layer may include a primarily amorphous structure while the second sub-layer may include a primarily crystalline structure. In some embodiments, the first layer is between 0.5 nm and 2 nm in thickness. In some embodiments, the second layer is between 0.5 nm and 2 nm in thickness.

In some embodiments, the high-K gate dielectric layer140of the resistor device104may include only the first or second sub-layer whereas the high-K dielectric layer140of the transistor102may include both the first and second sub-layers. In one example, after deposition of the first and second sub-layers of the high-K dielectric layer140, the second sub-layer may be removed from the resistor device104. This can be accomplished by masking the region of the transistor102and performing a controlled etching process at the exposed high-K gate dielectric layer140of the resistor device104. The controlled etching process removes the second sub-layer of the high-K dielectric layer140at the resistor device104without removing the first sub-layer of the high-K dielectric layer140of the resistor device104.

In some embodiments, because the sub-layers of the high-K dielectric layer140are very thin, a tightly controlled atomic layer etching (ALE) process is performed to remove the second sub-layer of the high-K dielectric layer140at the resistor device104. The ALE process is able to remove a single atomic or molecular layer of the second sub-layer in each ALE cycle. The number and duration of each cycle can be selected to remove the second sub-layer without removing the first sub-layer.

In some embodiments, the ALE process is controlled by an analysis mode trained with a machine learning process. Further details regarding the controlled ALE process are provided in relation toFIGS.6A and66.

InFIG.2H, a first metal layer142is deposited on the high-K gate dielectric140in the trench134and in the voids136between semiconductor nanosheets120. In some embodiments, the first metal layer142includes titanium nitride. The first metal layer142can be deposited using PVD, ALD, CVD, or other suitable deposition processes. The first metal layer142can have a thickness between 1 nm and 3 nm. Other materials, deposition processes, and thicknesses can be utilized for the first metal layer142without departing from the scope of the present disclosure.

InFIG.2H, a spacer layer143is deposited on the first metal layer142in the trench134and in the voids136between semiconductor nanosheets120. In some embodiments, the spacer layer includes one or more of silicon, polysilicon, or other conductive materials. The spacer layer143can be deposited using PVD, ALD, CVD, or other suitable deposition processes. The spacer layer143can have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses can be utilized for the first spacer layer143without departing from the scope of the present disclosure.

InFIG.2H, a second metal layer144has been deposited on the spacer layer143in the trench134and in the voids136between semiconductor nanosheets120. In one example, the second metal layer144includes titanium nitride. The second metal layer144can be deposited using PVD, ALD, CVD, or, or other suitable deposition processes. The second metal layer144can have a thickness between 1 nm and 3 nm. Other materials, deposition processes, and thicknesses can be utilized for the second metal layer144without departing from the scope of the present disclosure.

InFIG.2I, a third metal layer146has been deposited on the second metal layer144in the trench134and in the voids136between semiconductor nanosheets120. In one example, the third metal layer146includes tungsten. The third metal layer146can be deposited using PVD, ALD, CVD, or other suitable deposition processes. The third metal layer146fills the remaining space in the trench134and in the voids136between semiconductor nanosheets120. For this reason, the third metal layer146is a trench fill or gate fill material. The gate fill material is highly conductive. The first and second metal layers142and144are very thin so that as much of the trench134in the voids136is possible can be filled with the gate fill material. This ensures that the gate electrode148of the transistor102will be highly conductive. The gate electrode of the transistor102corresponds to the first, second, and third metal layers142,144, and146. Other materials, deposition processes, and thicknesses can be utilized for the second metal layer144without departing from the scope of the present disclosure. The first, second, and third metal layers142,144, and146correspond to the gate electrode148of the transistor102.

In some embodiments, a void147may be formed in the trench134during deposition of the third metal layer146. The void147may result from a process called key-holing. During deposition of the third metal layer146, it may be possible that the third metal layer146may accumulate or deposit at a higher rate on the corners of the trench134than in the middle of the trench134. Due to the increased rate of deposition or accumulation, the top of the trench134may become blocked off by the accumulation of material of the third metal layer146before the middle of the trench134is entirely filled. Accordingly, a void147remains in the trench134. As will be set forth in more detail below, the void can factor into the PUF that can be generated from the RRAM array105.

The first, second, and third metal layers142,144, and146surround or partially surround the semiconductor nanosheets120in the same way as described above in relation to the interfacial dielectric layer138and the high-K gate dielectric layer140, except that the interfacial dielectric layer and the high-K gate dielectric layer140are positioned between the semiconductor nanosheets120and the first, second, and third metal layers142,144, and146.FIG.2Hand subsequent figures may not show all of the layers which may be present in the voids136between nanosheets120. In practice, the first metal layer142, the spacer layer143, the second metal layer144, and the third metal layer146may each be present in the voids136between the semiconductor nanosheets120.

In the resistor device104, the high-K gate dielectric140is not utilized as a gate dielectric because the resistor device104will not be a transistor in the end. In the case of the resistor device104, the high-K gate dielectric140is a resistive element and a data storage element as described in more detail below. Additionally, in the case of the resistor device104, the first, second, and third metal layers142,144, and146do not act as a gate electrode because the resistor device104is not a transistor with a gate terminal. Instead, the first, second, and third metal layers142,144, and146may correspond to a top electrode162of the resistor device.

The first, second, and third metal layers142,144, and146surround the semiconductor nanosheets120. The semiconductor nanosheets120are physically separated from the first, second, and third metal layers142,144, and146by the gate dielectric made up of the interfacial dielectric layer138and the high-K gate dielectric layer140. For this reason, the transistor102is called a gate all around transistor, because the gate electrode148surrounds the semiconductor nanosheets120. The semiconductor nanosheets120correspond to the channel regions of the transistor102. When the transistor102is turned on by application of a voltage between the source and the gate electrode148, current flows between the source and drain regions130through the semiconductor nanosheets120in the transistor102.

The electrical characteristics of both the transistor102and the resistor device104are based, in part, on the materials of the gate electrode148and the top electrode162, During fabrication of the integrated circuit103, the transistors102may have slightly different dimensions and conductivities associated with the gate electrodes148. For example, the gate trenches134of some transistors102may be slightly wider than the gate trenches134of the other transistors. The various metal layers of the gate electrodes148may have slightly different thicknesses and conductivities. As mentioned above, the voids147may form in some of the transistors102but not in others of the transistors102. The dimensions of the voids147may be different than some of the transistors102. AH these factors can affect the threshold voltage, the conductivity, or other electrical aspects of the transistors102. When the PUF is generated for the integrated circuit103, each of the factors mentioned above can affect the various interrogations utilized to form the PUF.

The variations that can occur in the transistors102can also occur in the resistor devices104. Additionally, the high K dielectric layer140acts as a resistive storage element, as will be described in further detail below, in the resistor devices104. Variations that results during the fabrication process of the high K dielectric layer140can result in the resistor devices104having different electrical characteristics. All these factors can affect the electrical properties of the resistor devices104. When the PUF is generated for the integrated circuit103, each of the factors mentioned above can affect the various interrogations utilized to form the PUF.

InFIG.2I, the structure of the resistor device104begins to diverge from the structure of the transistor102. InFIG.2I, a trench150has been etched in the interlevel dielectric layer132. The trench150exposes the left source/drain region130of the resistor device104. The trench150can be formed by etching the interlevel dielectric layer132in the presence of a mask. The pattern of the mask150ensures that the etch will result in the trench150at the location shown inFIG.2I.

InFIG.2J, the trench150is extended at the resistor device104by removing the source/drain region130on the left side of the resistor device104. After the trench150has been opened in the interlevel dielectric layer132an etching process is performed to remove the source/drain region130on the left side of the resistor device104. The etching process selectively etches the semiconductor material of the source/drain region130with respect to the interlevel dielectric layer132, the third semiconductor layer116, the sheet inner spacer128, and the semiconductor nanosheets120.

InFIG.2J, an etching process has been performed to remove the third semiconductor layer116, the semiconductor nanosheets120, and the interfacial dielectric layer138from the resistor device104. In an example in which the semiconductor nanosheets120are silicon, the third semiconductor layer116is silicon, and the interfacial dielectric layer138is silicon dioxide, a single etching process can be performed to remove the semiconductor nanosheets120, the third semiconductor layer116, and the interfacial dielectric layer138at the resistor device104via the trench150.

The removal of the semiconductor nanosheets120results in a void154at the location of the removed semiconductor nanosheets120. The trench150and the void154are contiguous with each other and may be considered a single trench or void. The etching process exposes the high-K gate dielectric layer140.

InFIG.2K, a layer of conductive material156has been deposited in the trenches150,152, and the void154. In one example, the layer of conductive material156is titanium nitride deposited by an ALD process, though other materials and processes can be utilized without departing from the scope of the present disclosure. The layer of conductive material156lines the walls of the trench150, and fills the voids154where the semiconductor nanosheets120were previously positioned. The layer of conductive material156forms conductive nanosheets157where the semiconductor nanosheets120were previously positioned. The conductive nanosheets157correspond to a bottom electrode of the resistor device104, The conductive nanosheets157have a thickness corresponding to the thickness of the removed semiconductor nanosheets plus the thickness of the previously removed interfacial dielectric layer138. Accordingly, the conductive nanosheets157are slightly thicker than the semiconductor nanosheets120. In some embodiments the conductive nanosheets have a thickness between 2 nm and 7 nm. This range of thicknesses provides a thin profile and high conductivity. Other materials, deposition processes and thicknesses can be utilized for the conductive material156and conductive nanosheets157without departing from the scope of the present disclosure.

InFIG.2K, a conductive trench fill material158has been deposited on the layer of conductive material156. The conductive trench fill material158fills any remaining gap in the trench150. In one example, the conductive trench fill material158is tungsten deposited by a CVD process, though other materials and deposition processes can be utilized for the conductive trench fill material158without departing from the scope of the present disclosure. The layer of conductive material156, the conductive nanosheets157, and the conductive trench fill material158collectively form a bottom electrode160of the resistor device104.

InFIG.2K, the top electrode162includes the first metal layer142, the second metal layer144, and the third metal layer146. In other embodiments, the top electrode162can include a single metal or different combinations of metal layers other than the gate electrode148of the transistor102.

InFIG.2L, silicide layers164have been formed in the source and drain regions130of the transistor102. The silicide layers164can include titanium silicide, cobalt silicide, or other types of silicide. InFIG.2L, cobalt contact plugs168have been formed in the interlayer dielectric layer132in each of the transistors102,104, and108. The cobalt contact plugs168can be utilized to apply voltages to the source and drain regions130of the transistor102. The plugs168are surrounded by a titanium nitride glue layer168. The plugs168, the glue layer168, and the silicide layers164can include other materials without departing from the scope of the present disclosure.

InFIG.2M, an interlevel dielectric layer169has been deposited on the interlevel dielectric layer132. The interlevel dielectric layer169can include silicon oxide. The interlevel dielectric layer169can be deposited by CVD, ALD, or other suitable processes. Other materials and processes can be utilized for the interlevel dielectric layer169without departing from the scope of the present disclosure.

InFIG.2M, contact plugs170,172,174, and176have been formed in the interlevel dielectric layer169. The contact plugs170are electrical contact with the contact plugs168that contact the silicide164in the source and drain layers130of the transistor102. The contact plugs172contacts the gate electrode148of the transistor102. The contact plugs174contacts the conductive material158and is thus electrically connected to the bottom electrode,160of the resistor device104. The contact plugs176is in electrical contact with the top electrode162of the electrical device. Each of the contact plugs170,172,174, and176can include tungsten or another suitable conductive material. Each of the contact plugs170,172,174, and176can be surrounded by a respective conductive liner171,173,177, and179. The conductive liners171,173,177, and179can include titanium nitride or another suitable material.

InFIG.2N, an interlevel dielectric layer181has been deposited on the interlevel dielectric layer169. The interlevel dielectric layer181can include silicon oxide. The interlevel dielectric layer181can be deposited by CVD, ALD, or other suitable processes. Other materials and processes can be utilized for the interlevel dielectric layer181without departing from the scope of the present disclosure.

InFIG.2N, metal lines180,182,184, and186have been formed in the interlevel dielectric layer181. The metal lines180,182,184, and186are conductive lines that electrically connect to the various terminals of the transistor102and the resistor device104. The metal lines180,182,184, and186can include copper or another suitable conductive material. InFIG.2Nthe transistor102and the resistor device104are complete, although other subsequent dielectric and metal layers and structures may be subsequently formed in the integrated circuit as will be understood by those of skill in the art.

The transistor102and the resistor device104correspond to a RRAM memory cell190of a RRAM memory array. The transistor102corresponds to an access transistor of the memory cell190. The resistor device104includes the data storage element of the memory cell190. More particularly, the high-K gate dielectric layer140the resistive element in the resistor device104and corresponds to the data storage element of the memory cell190. The effective resistance of the high-K dielectric layer140can be selectively toggled between a high resistance state and a low resistance state. Accordingly, the resistance provided by the high-K dielectric layer140corresponds to the value of data stored in the memory cell190.

The high-K dielectric layer140can be placed in a high resistance state by performing a DC sweep operation by holding the voltage of the bottom electrode160and 0 V and sweeping the voltage of the top electrode162to −1.5 V, i.e., by performing a DC sweep that lowers the voltage of the top electrode162below the voltage of the bottom electrode160. The high-K dielectric140of the resistor device104can be placed in a low resistance state by holding the voltage of the bottom electrode160at 0 V and sweeping the voltage of the top electrode162to 1.5 V, i.e., by performing a DC sweep that raises the voltage of the top electrode162higher than the voltage of the bottom electrode160. Other voltage values can be applied for setting the resistor device104between the high resistance state and the low resistance state without departing from the scope of the present disclosure.

In one example, in the low resistance state the resistance of the resistor device104is between 1000 ohms and 10,000 ohms. In the high resistance state, the resistance of the resistor device104is between 10,000 ohms and 100,000 ohms. Thus, in one example, the resistance of the resistor device104changes by least an order of magnitude between the high resistance state and the low resistance state.

Data can be read from the memory cell190by measuring the resistance in the resistor device104. Typically, a read operation includes turning on the transistor102by applying a voltage between the gate terminal148and the source130. In the example ofFIG.2N, the source terminal of the transistor102is the left region130. The drain terminal is the right region130of the transistor102. With the transistor102in the conducting state, a voltage can be applied between the bottom electrode160and the top electrode162of the resistor device104. The resistance can be measured indirectly by measuring a voltage drop across the resistor device104or by measuring a current flowing through the resistor device104. Such measurements can be accomplished by current or voltage based sense amplifiers and other read circuitry coupled to the memory array of which the memory cell190is part.

In some embodiments, the metal interconnect180is a source line of the memory cell190. The metal interconnect180is electrically coupled to the source of the transistor102via the plugs170and168on the left side of the transistor102, In some embodiments, the metal interconnect182is a word line of the memory cell190. The word line182is electrically connected to the gate terminal148of the transistor102via the plugs172, In some embodiments, the metal interconnect184electrically connects the drain terminal of the transistor102to the bottom electrode160of the resistor device104via the right side plug170and the plug174. In some embodiments, the metal interconnect186is a bit line of the memory cell190.

FIG.3is a schematic diagram of a memory array105, according to some embodiments. The memory array105is one example of the memory array105ofFIG.1. The memory array105is a RRAM memory cell including a plurality of RRAM memory cells190. The view ofFIG.2Nillustrates a single RRAM memory cell190. Each RRAM memory cell190ofFIG.2has the structure shown inFIG.2N, in some embodiments. In particular, each RRAM memory cell190includes a transistor102and a resistor device104. The drain of the transistor102is coupled to the bottom electrode of the resistor device104. The top terminal of the resistor device104is coupled to a bit line (BL)186. The gate terminal of the transistor102is coupled to a word line (WL)182. The source terminal of the transistor102is coupled to a source line (SL)180.

In practice, the memory array105may include thousands or millions of memory cells190arranged in rows and columns. Each row of memory cells190is coupled to a respective word line182. Each column of memory cells190is coupled to a respective source line180and the bit line186. As described in relation toFIG.2, the resistor devices104are the data storage elements of the memory cells190. Though not shown inFIG.2, the memory array105may include or may be coupled to additional circuitry for writing data to the memory cells190and for reading data from the memory cells190. Such additional circuitry may include row decoders, column decoders, sense amplifiers, charge pumps, read voltage regulators, clock signal generators, timing signal generators, or other circuit components that may be utilized in writing data to or reading data from the memory cells190of the memory array105.

The integrated circuit103can include a memory controller107, as described in relation toFIG.1. The memory controller107can control the memory array105ofFIG.3. The memory controller107can control the operation of the memory array105during generation of a PUF for authentication of the integrated circuit103, or of an electronic device101in which the integrated circuit103is installed.

During the PUF generation process, the memory controller107receives PUF generation instructions for generating a PUF from the memory array105. The instructions include operations or challenges to apply to the RRAM array105in order to generate PUF data for later authentication. The challenges are designed to detect unique electrical or physical characteristics of the RRAM array. The PUF generation process can include recording or measuring parameters associated with each of a plurality of memory cells190of the memory array one of six. The operations can include measuring the data state upon startup of the memory array105. The operations can include measuring a read time of each of a plurality of memory cells190of the memory array105. The operations can include performing a partial write operation to a plurality of memory cells190and recording the data value stored in each memory cell190. These and other operations or challenges can be performed in relation to the memory array105in order to generate a PUF for authentication purposes.

The memory array105ofFIG.3illustrates memory cells190that include only a single transistor102and a single resistor device104. This is known as a 1T1R configuration. However, other configurations are possible for the memory cells190. For example, each memory cell190may include a single resistor device104and two or more transistors102. These configurations are known as nT1R, where n is a positive integer. In another example, each memory cell190may include a single transistor102and multiple resistor devices104. These configurations are known as 1TmR, where m is a positive integer.

In the example ofFIGS.2N and3, the memory array105is implemented in a single integrated circuit formed from a single semiconductor wafer. However, other arrangements are possible. For example, the memory array105may be implemented in an integrated circuit cut from two semiconductor wafers bonded together. One of the semiconductor wafers may include the transistors102of the memory cells190. The other semiconductor wafer may include the resistor devices104of the memory cells190. Various configurations for the memory cells190of the memory array105are possible without departing from the scope of the present disclosure.

FIG.4is a cross-sectional diagram of an integrated circuit103, according to some embodiments. The integrated circuit103includes a first integrated circuit die103A and a second integrated circuit die1036bonded together by wafer bonding techniques. In particular, the first integrated circuit die103A is formed in a first semiconductor wafer. The second integrated circuit die103B is formed in the second semiconductor wafer. Prior to dicing, the first semiconductor wafer is bonded to the second semiconductor wafer. After dicing, a plurality of integrated circuits100are formed from the bonded wafers. Each integrated circuit103includes a first integrated circuit die103A and a second integrated circuit die1036.

The integrated circuit die103, includes a plurality of transistors102. The transistors102can include the same structures and can be formed using the same or similar processes as those described for forming the transistor102ofFIGS.2A-2N. Some differences may include forming a silicide at the bottom of the drain regions130of the transistors102and forming conductive plugs194at the bottom of the integrated circuit die103A teaching contact with the drain terminal130of the respective transistor102. Prior to the wafer bonding process, the bottom surface of the conductive plugs194are exposed on the bottom surface of the integrated circuit die103A.

The integrated circuit die1036includes a plurality of resistor devices104, The resistor devices104can include the same structures and can be formed using the same or similar processes as those described for forming the resistor device104ofFIGS.2A-2N. Some differences may include forming contacts196on top of the interconnects184in the second integrated circuit die103B. The top surfaces of the contacts196are exposed at the top surface of the integrated circuit die103B prior to the wafer bonding process. The wafer bonding process brings each contact196into electrical contact with a respective conductive plug194. In this way, the drain terminal of each transistor102are coupled to the bottom electrode of a respective resistor device104.

In some embodiments, each RRAM memory cell190includes a transistor102from the first integrated circuit the103A and a resistor device104from the second integrated circuit die103B. While two memory cells190are illustrated inFIG.100, in practice, the integrated circuit103may include thousands or millions of memory cells190.

FIG.5is a cross-section of integrated circuit103, according to some embodiments. The integrated circuit103includes an RRAM memory cell190. The memory cell190includes a transistor102and a resistor device104. The transistor102ofFIG.4may be identical or substantially identical to the transistor102described in relation toFIGS.2A-2N. The resistor device104ofFIG.5is similar to the resistor device104ofFIGS.2A-2N, except that the left source region130and the semiconductor nanosheets120of the resistor device104are not replaced with the conductive materials156and158. Instead, the left source drain region130and the semiconductor nanosheets120of the resistor device104correspond to the bottom electrode160of the resistor device104.

The semiconductor nanosheets120of the resistor device104are highly doped compared to the semiconductor nanosheets120of the transistor102. This renders the semiconductor nanosheets120of the resistor device104highly conductive compared to the semiconductor nanosheets120of the transistor102. Accordingly, the semiconductor nanosheets120of the resistor device104are conductive nanosheets157. In one example, the semiconductor nanosheets120of the resistor device104are heavily doped with P-type dopants. The P-type dopants may include boron or other P-type dopants. In another example, the semiconductor nanosheets120of the resistor device104heavily doped with N-type dopants. The N-type dopants can include phosphorus or other N-type dopants. The doping of the semiconductor nanosheets120of the resistor device104can occur during formation of the semiconductor nanosheets120of the resistor device104.

In one example, aside from the different doping of the semiconductor nanosheets120of the resistor device104with respect to the semiconductor nanosheets120of the transistor102, the process for forming the resistor device104ofFIG.3differs from formation of the resistor device104ofFIGS.2A-2beginning at the stage of processing shown inFIGS.1G and2LIn particular, the steps shown inFIGS.2I-2Kdo not take place in the formation of the resistor device104ofFIG.5. Instead, silicide164is formed in the left source/drain region130of the resistor device104as described in relation to the silicide164formed in the transistor102. The formation of the silicides may occur in the same processing steps. Conductive plug198can be formed at the same time as conductive, plugs160may be formed in the same material. The processing steps for forming conductive plugs170,172,174, and176and interconnects180,182,184, and186may be substantially the same as described in relation toFIGS.2M and2N.

Another difference between the resistor device104ofFIG.5and the resistor device104ofFIG.2Nis that the interfacial dielectric layer138is still present in the resistor device104ofFIG.4. Another possible difference is that the top electrode162of the resistor device104ofFIG.5can include a single conductive layer rather than the various metal layer layers that are included in the gate electrode of the transistor device101.

FIG.6is a cross-sectional view of an integrated circuit103, according to some embodiments. The integrated circuit103includes a RRAM memory cell190. The memory Cell190includes a transistor102and a resistor device104. The transistor102and the resistor device104are substantially similar to the transistor102and the resistor device104ofFIG.3, except that the drain region130of the transistor102is shared with the resistor device104. Accordingly, when the current is passed through the memory cell190, a voltage is applied to the gate electrode of the transistor102in order to render the semiconductor nanosheets120of the transistor102conductive. A voltage is applied between the top electrode162of the resistor device104and the source region130(left region130) of the transistor102. Current flows from the top electrode162through the resistive element including the interfacial dielectric layer138and the high-K dielectric layer140of the resistor device104into the highly doped semiconductor nanosheets of the resistor device104through the shared drain region130, through the semiconductor nanosheets120of the transistor102to the source region130of the transistor102and through the source line180.

FIG.7Ais a block diagram of a control system700for controlling an atomic layer etching (ALE) process, according to some embodiments. The control system700ofFIG.7Ais configured to control operation of an ALE etching system in performing ALE processes to form aspects of the integrated circuits100ofFIGS.1-6, according to some embodiments. In some embodiments, controls system700is utilized to control and ALE process for forming the high-K dielectric layer140from either the resistor device104or the transistor102as described in relation toFIG.2G.

While the description ofFIGS.7A and7Bis directed primarily to controlled etching of the high-K dielectric layer140, the controlled etching can also be used to pattern other thin-films. For example, the controlled etching can be used to pattern the various metal layers of the gate electrode148of the transistor102and the top electrode162of the resistor device104.

The control system700utilizes machine learning to adjust parameters of the ALE system. The control system700can adjust parameters of the ALE system between ALE runs or even between ALE cycles in order to ensure that the high-K dielectric layer140of the resistor device104falls within selected specifications.

In some embodiments, the control system700includes an analysis model702and a training module704. The training module trains the analysis model702with a machine learning process. The machine learning process trains the analysis model702to select parameters for an ALE process that will result in the high-K dielectric layer140of the resistor device104having selected characteristics. Although the training module704is shown as being separate from the analysis model702, in practice, the training module704may be part of the analysis model702.

The control system700includes, or stores, training set data706. The training set data706includes historical high-K dielectric data708and historical process conditions data710. The historical high-K dielectric data708includes data related to high-K dielectric layers resulting from ALE processes. The historical process conditions data710includes data related to process conditions during the ALE processes that etched the high-K dielectric layers. As will be set forth in more detail below, the training module704utilizes the historical high-K dielectric data708and the historical process conditions data710to train the analysis model702with a machine learning process.

In some embodiments, the historical high-K dielectric data708includes data related to the remaining thickness of previously etched high-K dielectric layers. For example, during operation of a semiconductor fabrication facility, thousands or millions of semiconductor wafers may be processed over the course of several months or years. Each of the semiconductor wafers may include high-K dielectric layers etched by ALE processes. After each ALE process, the thicknesses of the thin-films are measured as part of a quality control process. The historical high-K dielectric data708includes the remaining thicknesses of each of the high-K dielectric layers etched by ALE processes. Accordingly, the historical high-K dielectric data708can include thickness data for a large number of thin-films etched by ALE processes.

In some embodiments, the historical high-K dielectric data708may also include data related to the thickness of high-K dielectric layers at intermediate stages of the thin-film etching processes. For example, an ALE process may include a large number of etching cycles during which individual layers of the high-K dielectric layer are etched. The historical high-K dielectric data708can include thickness data for high-K dielectric layers after individual etching cycles or groups of etching cycles. Thus, the historical high-K dielectric data708not only includes data related to the total thickness of a high-K dielectric layer after completion of an ALE process, but may also include data related to the thickness of the high-K dielectric layer at various stages of the ALE process.

In some embodiments, the historical high-K dielectric data708includes data related to the composition of the remaining high-K dielectric layers etched by ALE processes. After a high-K dielectric layer is etched, measurements can be made to determine the elemental or molecular composition of the high-K dielectric layers. Successful etching of the high-K dielectric layers results in a high-K dielectric layer that includes particular remaining thicknesses. Unsuccessful etching processes may result in a high-K dielectric layer that does not include the specified proportions of elements or compounds. The historical high-K dielectric data708can include data from measurements indicating the elements or compounds that make up the various high-K dielectric layers.

In some embodiments, the historical process conditions710include various process conditions or parameters during ALE processes that etch the high-K dielectric layers associated with the historical high-K dielectric data708. Accordingly, for each high-K dielectric layer having data in the historical high-K dielectric data708, the historical process conditions data710can include the process conditions or parameters that were present during etching of the high-K dielectric layer. For example, the historical process conditions data710can include data related to the pressure, temperature, and fluid flow rates within the process chamber during ALE processes.

The historical process conditions data710can include data related to remaining amounts of precursor material in the fluid sources during ALE processes. The historical process conditions data710can include data related to the age of the ALE etching chamber, the number of etching processes that have been performed in the ALE etching chamber, a number of etching processes that have been performed in the ALE etching chamber since the most recent cleaning cycle of the ALE etching chamber, or other data related to the ALE etching chamber. The historical process conditions data710can include data related to compounds or fluids introduced into the ALE etching chamber during the etching process. The data related to the compounds can include types of compounds, phases of compounds (solid, gas, or liquid), mixtures of compounds, or other aspects related to compounds or fluids introduced into the ALE etching chamber. The historical process conditions data710can include data related to the humidity within the ALE etching chamber during ALE processes. The historical process conditions data710can include data related to light absorption, light adsorption, and light reflection related to the ALE etching chamber. The historical process conditions data710can include data related to the length of pipes, tubes, or conduits that carry compounds or fluids into the ALE etching chamber during ALE processes. The historical process conditions data710can include data related to the condition of carrier gases that carry compounds or fluids into the ALE etching chamber during ALE processes.

In some embodiments, historical process conditions data710can include process conditions for each of a plurality of individual cycles of a single ALE process. Accordingly, the historical process conditions data710can include process conditions data for a very large number of ALE cycles.

In some embodiments, the training set data706links the historical high-K dielectric data708with the historical process conditions data710. In other words, the thin-film thickness, material composition, or crystal structure associated with a high-K dielectric layer in the historical high-K dielectric data708is linked to the process conditions data associated with that etching process. As will be set forth in more detail below, the labeled training set data can be utilized in a machine learning process to train the analysis model702to predict semiconductor process conditions that will result in properly formed high-K dielectric layers.

In some embodiments, the control system724includes processing resources712, memory resources714, and communication resources716. The processing resources712can include one or more controllers or processors. The processing resources712are configured to execute software instructions, process data, make thin-film etching control decisions, perform signal processing, read data from memory, write data to memory, and to perform other processing operations. The processing resources712can include physical processing resources712located at a site or facility of the ALE system. The processing resources can include virtual processing resources712remote from the site ALE system or a facility at which the ALE system is located. The processing resources712can include cloud-based processing resources including processors and servers accessed via one or more cloud computing platforms.

In some embodiments, the memory resources714can include one or more computer readable memories. The memory resources714are configured to store software instructions associated with the function of the control system and its components, including, but not limited to, the analysis model702. The memory resources714can store data associated with the function of the control system700and its components. The data can include the training set data706, current process conditions data, and any other data associated with the operation of the control system700or any of its components. The memory resources714can include physical memory resources located at the site or facility of the ALE system. The memory resources can include virtual memory resources located remotely from site or facility of the ALE system. The memory resources714can include cloud-based memory resources accessed via one or more cloud computing platforms.

In some embodiments, the communication resources can include resources that enable the control system700to communicate with equipment associated with the ALE system. For example, the communication resources716can include wired and wireless communication resources that enable the control system700to receive the sensor data associated with the ALE system and to control equipment of the ALE system. The communication resources716can enable the control system700to control the flow of fluids or other material from the fluid sources708and710and from the purge sources712and714. The communication resources716can enable the control system700to control heaters, voltage sources, valves, exhaust channels, wafer transfer equipment, and any other equipment associated with the ALE system. The communication resources716can enable the control system700to communicate with remote systems. The communication resources716can include, or can facilitate communication via, one or more networks such as wire networks, wireless networks, the Internet, or an intranet. The communication resources716can enable components of the control system700to communicate with each other.

In some embodiments, the analysis model702is implemented via the processing resources712, the memory resources714, and the communication resources716. The control system700can be a dispersed control system with components and resources and locations remote from each other and from the ALE system.

FIG.7Bis a block diagram illustrating operational aspects and training aspects of the analysis model702ofFIG.7A, according to some embodiments. The analysis model702can be used to select parameters for ALE processes performed by the ALE system to form aspects the integrated circuits100ofFIGS.1-6. In some embodiments, the analysis model702ofFIG.7Bis used to control an ALE process for forming the high-K dielectric layer140described in relation toFIG.2G.

While the description of the analysis model702is directed primarily to forming or patterning the high-K dielectric layer140, the analysis model702can be utilized to pattern other materials of the transistor102or the resistor device104. For example, the analysis model702can control an ALE process for forming or patterning the metal layers associated with the gate electrode148and the top electrode162.

As described previously, the training set data706includes data related to a plurality of previously performed high-K dielectric layer etching processes. Each previously performed high-K dielectric layer etching process took place with particular process conditions and resulted in a high-K dielectric layer having a particular characteristics. The process conditions for each previously performed high-K dielectric layer etching process are formatted into a respective process conditions vector752. The process conditions vector includes a plurality of data fields754. Each data field754corresponds to a particular process condition.

The example ofFIG.7Billustrates a single process conditions vector752that will be passed to the analysis model702during the training process. In the example ofFIG.7B, the process conditions vector752includes nine data fields754. A first data field754corresponds to the temperature during the previously performed high-K dielectric layer etching process. A second data field756corresponds to the pressure during the previously performed high-K dielectric layer etching process. A third data field754corresponds to the humidity during the previously performed high-K dielectric layer etching process. The fourth data field754corresponds to the flow rate of etching materials during the previously performed high-K dielectric layer etching process. The fifth data field754corresponds to the phase (liquid, solid, or gas) of etching materials during the previously performed high-K dielectric layer etching process. The sixth data field754corresponds to the age of the ampoule used in the previously performed high-K dielectric layer etching process. The seventh data field754corresponds to a size of an etching area on a wafer during the previously performed high-K dielectric layer etching process. The eighth data field754corresponds to the density of surface features of the wafer utilized during the previously performed high-K dielectric layer etching process. The ninth data field corresponds to the angle of sidewalls of surface features during the previously performed high-K dielectric layer etching process. In practice, each process conditions vector752can include more or fewer data fields than are shown inFIG.7Bwithout departing from the scope of the present disclosure. Each process conditions vector752can include different types of process conditions without departing from the scope of the present disclosure. The particular process conditions illustrated inFIG.7Bare given only by way of example. Each process condition is represented by a numerical value in the corresponding data field754. For condition types that are not naturally represented in numbers, such as material phase, a number can be assigned to each possible phase.

The analysis model702includes a plurality of neural layers756a-e. Each neural layer includes a plurality of nodes758. Each node758can also be called a neuron. Each node758from the first neural layer756areceives the data values for each data field from the process conditions vector752. Accordingly, in the example ofFIG.7B, each node758from the first neural layer756areceives nine data values because the process conditions vector752has nine data fields. Each neuron758includes a respective internal mathematical function labeled F(x) inFIG.7B. Each node758of the first neural layer756agenerates a scalar value by applying the internal mathematical function F(x) to the data values from the data fields754of the process conditions vector752. Further details regarding the internal mathematical functions F(x) are provided below.

Each node758of the second neural layer756breceives the scalar values generated by each node758of the first neural layer756a. Accordingly, in the example ofFIG.7Beach node of the second neural layer756breceives four scalar values because there are four nodes758in the first neural layer756a. Each node758of the second neural layer756bgenerates a scalar value by applying the respective internal mathematical function F(x) to the scalar values from the first neural layer756a.

Each node758of the third neural layer756creceives the scalar values generated by each node758of the second neural layer756b. Accordingly, in the example ofFIG.7Beach node of the third neural layer756creceives five scalar values because there are five nodes758in the second neural layer756b. Each node758of the third neural layer756cgenerates a scalar value by applying the respective internal mathematical function F(x) to the scalar values from the nodes758of the second neural layer756b.

Each node758of the neural layer756dreceives the scalar values generated by each node758of the previous neural layer (not shown). Each node758of the neural layer756dgenerates a scalar value by applying the respective internal mathematical function F(x) to the scalar values from the nodes758of the second neural layer756b.

The final neural layer includes only a single node758. The final neural layer receives the scalar values generated by each node758of the previous neural layer756d. The node758of the final neural layer756egenerates a data value768by applying a mathematical function F(x) to the scalar values received from the nodes758of the neural layer756d.

In the example ofFIG.7B, the data value768corresponds to the predicted remaining thickness of a high-K dielectric layer generated by process conditions data corresponding to values included in the process conditions vector752. In other embodiments, the final neural layer756emay generate multiple data values each corresponding to a particular high-K dielectric layer characteristic such as high-K dielectric layer crystal orientation, high-K dielectric layer uniformity, or other characteristics of a high-K dielectric layer. The final neural layer756ewill include a respective node758for each output data value to be generated. In the case of a predicted high-K dielectric layer thickness, engineers can provide constraints that specify that the predicted high-K dielectric layer thickness768must fall within a selected range, such as between 0 nm and 50 nm, in one example. The analysis model702will adjust internal functions F(x) to ensure that the data value768corresponding to the predicted high-K dielectric layer thickness will fall within the specified range.

During the machine learning process, the analysis model compares the predicted remaining thickness in the data value768to the actual remaining thickness of the high-K dielectric layer as indicated by the data value770. As set forth previously, the training set data706includes, for each set of historical process conditions data, high-K dielectric layer characteristics data indicating the characteristics of the high-K dielectric layer that resulted from the historical high-K dielectric layer etching process. Accordingly, the data field770includes the actual remaining thickness of the high-K dielectric layer that resulted from the etching process reflected in the process conditions vector752. The analysis model702compares the predicted remaining thickness from the data value768to the actual remaining thickness from the data value770. The analysis model702generates an error value772indicating the error or difference between the predicted remaining thickness from the data value768and the actual remaining thickness from the data value770. The error value772is utilized to train the analysis model702.

The training of the analysis model702can be more fully understood by discussing the internal mathematical functions F(x). While all of the nodes758are labeled with an internal mathematical function F(x), the mathematical function F(x) of each node is unique. In one example, each internal mathematical function has the following form:

In the equation above, each value x1-xncorresponds to a data value received from a node758in the previous neural layer, or, in the case of the first neural layer756a, each value x1-xncorresponds to a respective data value from the data fields754of the process conditions vector752. Accordingly, n for a given node is equal to the number of nodes in the previous neural layer. The values w1-wnare scalar weighting values associated with a corresponding node from the previous layer. The analysis model702selects the values of the weighting values w1-wn. The constant b is a scalar biasing value and may also be multiplied by a weighting value. The value generated by a node758is based on the weighting values w1-wn. Accordingly, each node758has n weighting values w1-wn. Though not shown above, each function F(x) may also include an activation function. The sum set forth in the equation above is multiplied by the activation function. Examples of activation functions can include rectified linear unit (ReLU) functions, sigmoid functions, hyperbolic tension functions, or other types of activation functions.

After the error value772has been calculated, the analysis model702adjusts the weighting values w1-wnfor the various nodes758of the various neural layers756a-356e. After the analysis model702adjusts the weighting values w1-wn, the analysis model702again provides the process conditions vector752to the input neural layer756a. Because the weighting values are different for the various nodes758of the analysis model702, the predicted remaining thickness768will be different than in the previous iteration. The analysis model702again generates an error value772by comparing the actual remaining thickness770to the predicted remaining thickness768.

The analysis model702again adjusts the weighting values w1-wnassociated with the various nodes758. The analysis model702again processes the process conditions vector752and generates a predicted remaining thickness768and associated error value772. The training process includes adjusting the weighting values w1-wnin iterations until the error value772is minimized.

FIG.7Billustrates a single process conditions vector752being passed to the analysis model702. In practice, the training process includes passing a large number of process conditions vectors752through the analysis model702, generating a predicted remaining thickness768for each process conditions vector752, and generating associated error value772for each predicted remaining thickness. The training process can also include generating an aggregated error value indicating the average error for all the predicted remaining thicknesses for a batch of process conditions vectors752. The analysis model702adjusts the weighting values w1-wnafter processing each batch of process conditions vectors752. The training process continues until the average error across all process conditions vectors752is less than a selected threshold tolerance. When the average error is less than the selected threshold tolerance, the analysis model702training is complete and the analysis model is trained to accurately predict the thickness of high-K dielectric layers based on the process conditions. The analysis model702can then be used to predict high-K dielectric layer thicknesses and to select process conditions that will result in a desired high-K dielectric layer thickness. During use of the trained model702, a process conditions vector, representing current process condition for a current high-K dielectric layer etching process to be performed, and having the same format at the process conditions vector752, is provided to the trained analysis model702. The trained analysis model702can then predict the thickness of a high-K dielectric layer that will result from those process conditions.

A particular example of a neural network based analysis model702has been described in relation toFIG.7B. However, other types of neural network based analysis models, or analysis models of types other than neural networks can be utilized without departing from the scope of the present disclosure. Furthermore, the neural network can have different numbers of neural layers having different numbers of nodes without departing from the scope of the present disclosure.

FIG.8is a flow diagram of a method800for operating an electronic device, according to one embodiment. The method800can be utilized in conjunction with devices, systems, components, and processes associated withFIGS.1-7B. At802, the method800includes receiving an authentication request with an electronic device including an integrated circuit. One example of an electronic device is the electronic device100ofFIG.1. One example of an integrated circuit is the integrated circuit103ofFIG.1. At804, the method includes interrogating a resistive random access memory array of the integrated circuit responsive to the authentication request. One example of a resistive random access memory array is the resistive random access memory array105ofFIG.1. At806, the method800includes providing, from the resistive random access memory array, a plurality of signals responsive to the interrogation. At808, the method800includes generating, based on the signals, physical unclonable function data. At810, the method800includes outputting, responsive to the authentication request, the physical unclonable function data.

In some embodiments, a method includes receiving, with an electronic device including an integrated circuit, an authentication request. The method includes interrogating a resistive random access memory array of the integrated circuit responsive to the authentication request, and providing, from the resistive random access memory array, a plurality of signals responsive to the interrogating. The method includes generating, based on the signals, physical unclonable function data and outputting, responsive to the authentication request, the physical unclonable function data.

In some embodiments, an electronic device includes a resistive random access memory array including a plurality of resistive random access memory cells. Each memory cell includes a gate all around transistor and a resistor device coupled to the gate all around transistor. The resistor device includes a first electrode including a plurality of conductive nanosheets, a resistive element at least partially surrounding the conductive nanosheets, and a second electrode separated from the conductive nanosheets by the resistive element. The electronic device includes a memory controller configured to interrogate the resistive random access memory array responsive to an authentication request, to receive signals from the resistive random access memory array responsive to the interrogation, and generate physical unclonable function data from the signals.

In some embodiments, a method includes forming a gate all around transistor of a resistive random access memory cell of an integrated circuit and forming a resistor device of the resistive random access memory cell. Forming the resistor device includes forming a bottom electrode of the resistor device including a plurality of conductive nanosheets, forming a resistive element of the resistive random access memory cell at least partially surrounding the conductive nanosheets, and forming a top electrode of the resistor device separated from the conductive nanosheets by the resistive element and including a void.