Metal schemes of trench MOSFET for copper bonding

A trench MOSFET with improved metal schemes is disclosed. The improved contact structure applies a buffer layer to minimize the bonding damage to semiconductor when bonding copper wire upon front source and gate metal without additional cost.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the cell structure and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and improved process for fabricating a trench MOSFET with improved metal schemes for copper bonding.

2. The Prior Arts

Please refer toFIG. 1for a Cu bonding compatible bond pad structure of prior art (U.S. Patent application publication No. 20080006951). The disclosed structure includes a buffering structure comprising exposed electrode metal regions118of electrode metal layer114formed over a TiNi barrier metal layer112and non-conductive passivation regions120having same material as passivation layer116. As illustrated, while bonding Cu bonding wire122, some of the passivation regions120were pushed into the electrode metal layer114to provide a buffer function to keep Cu bonding wire122away from barrier metal layer112and the semiconductor device whereunder.

By employing non-conductive passivation material as buffer layer, the structure of prior art shown inFIG. 1minimized bonding damage on semiconductor device, however, comparing to its advantage, the disadvantages brought by this passivation structure are more significant to a certain extent. First of all, more cost are needed due to the requirement of additional passivation layer deposition, masking and etching; Second, wire bonding resistance is increased because that some Cu bonding area is occupied by the non-conductive passivation layer; Third, bad wire bonding adhesion issue is introduced due to Cu wire contacting with passivation layer in some area. Therefore, it is necessary to provide an improved metal bonding structure with lower cost, lower power consumptions, as well as steady performance.

Please refer toFIGS. 2 to 4for MOSFETs structures of another prior art (U.S. Pat. No. 6,888,196). InFIG. 2, the trench MOSFET is formed on a heavily doped substrate200of a first semiconductor doping type, e.g., N+ dopant, on which an epitaxial layer202doped with the same first semiconductor doping type is grown. Inside epitaxial layer202, a plurality of trench gates210are formed over a gate oxide layer208. Between each trench, there is a body region212of a second semiconductor doping type, e.g., P dopant, introduced by Ion Implantation, and N+ source regions214near the top surface of P-body area. Said source regions and body regions are connected to source metal220via metal plug216in source-body contact trench through a layer of oxide interlayer218. Around the bottom of each metal plug216, an area of heavily P+ doped206is formed to reduce the resistance between source and body region. Metal layer220serving as source metal is deposited on the front surface of whole device while metal layer222serving as drain metal deposited on the rear side of substrate200.

As mentioned above, the metal plug216, e.g., W plug, filled in source-body contact trench connects directly with the front source metal through the contact trench open area in oxide interlayer film218, in other words, no buffer layer is available while bonding Cu wire upon source metal layer. Therefore, thick front source metal is required to minimize the bonding damage to semiconductor device, leading to extra cost and metal etching complication.

On the other hand, the P+ area206underneath trench source-body contact bottom is formed by BF2 Ion Implantation before source-body contact trench's filled with contact material. As the sidewalls of source-body contact trench is perpendicular to the front surface of epitaxial layer, said P+ area can be implanted only around the bottom of source-body contact trench no matter with or without oxide film BF2 Ion Implantation, resulting in a high resistance Rp underneath N+ source and between channel and P+ area. As is known to all, a parasitic N+/PIN will be turned on if Iav*Rp>0.7V where Iav is avalanche current originated from the trench bottom. Therefore, the conventional vertical source contact shown inFIG. 2also has a poor avalanche capability which significantly affects the performance of whole device.

Another MOSFETs structure with P+ region formed by BF2 Ion Implantation through an oxide film deposited on the contact trench was disclosed in that application, as shown inFIG. 3. The structure here is almost the same as structure inFIG. 2except for the slope source-body contact trench. However, even if the slope contact trench is helpful to enlarge the P+ area under trench source-body contact during BF2 Ion Implantation, it is still not enough to resolve the high Rp problem as the P+ area is also formed only around the bottom of source-body contact trench. Meanwhile, a similar structure with P+ region formed on both bottom and sidewall of source-body contact trench by BF2 Ion Implantation without through the oxide film of prior art is given inFIG. 4. As there is no oxide film, the P+ area is apparently enlarged to be formed on the sidewall of source-body contact trench besides the bottom, resolving the high Rp issue discussed above. However, anther problem is thus introduced, which is that the N+ concentration on contact trench sidewalls will be reduced as a result of compensation by BF2 Ion Implantation due to no oxide film as stopper, causing high source contact resistance.

At the same time, structures illustrated inFIG. 3andFIG. 4both required thick front metal to minimize the bonding damage to semiconductor device due to the lack of buffer layer.

Accordingly, it would be desirable to provide a trench MOSFET cell with improved metal schemes and improved source contact structure to avoid those problems mentioned above.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide new and improved trench MOSFET cell and manufacture process to minimize the Cu wire bonding damage to semiconductor device without additional cost.

One aspect of the present invention is that, a W layer with a resistance reduction layer composed of Ti or Ti/N whereon underneath a front metal of source and gate is provided as buffer layer for reducing Cu wire bonding damage. The difference between the prior art of U.S. Pat. No. 6,888,196 and the present invention is that, in the prior art the W layer is totally removed from surface of oxide interlayer film after W deposition to fill the source-body contact trench while in the present invention it is selectively removed, in other words, the W layer is only kept on the oxide interlayer surface of the areas underneath source and gate metal to serve as buffer layer when bonding Cu wire upon source and gate metal, therefore, no additional cost is needed. And, comparing to structure inFIG. 1, the high wire bonding resistance and wire bonding adhesion issue are both resolved due to Cu bonding wire directly bonded to front source and gate metal layer. Additionally, contact resistance between buffer layer and front metal of source and gate are further reduced by employing the resistance reduction layer composed of Ti or Ti/N sandwiched therebetween.

Another aspect of the present invention is that, in some preferred embodiment, an improved source-body contact structure is proposed, which has vertical contact trench sidewalls within oxide interlayer and N+ source regions, and has slope contact trench sidewalls within P-body region. To be detailed, the contact trench sidewalls are substantially vertical (90+/−5 degree) within oxide interlayer and N+ source regions, and the taper angle is less than 85 degree respect to top surface of epitaxial layer within P-body region. By employing this structure, the P+ area can be enlarged to wrap the bottom and the slope sidewalls of source-body contact trench in P-body region, which resolves the high Rp problem and enhances the avalanche capability. On the other hand, there will be no BF2 Ion Implantation into the sidewalls of N+ source regions because the sidewall are substantially vertical, avoiding the N+ concentration reduction issue occurs inFIG. 4, thus preventing the increasing of source contact resistance from happening.

Another aspect of the present invention is that, in some preferred embodiment, the conventional poly gate within gate trench is replaced by a terrace gate, which will provide additional poly over silicon mesa area to further reduce gate resistance Rg, and what is the most important is that, a self-aligned source contact is implemented by employing the terrace gate structure, therefore resolved avalanche current Iav and Rds non-uniform distribution issue resulted from misalignment between contact and trench.

Briefly, in a preferred embodiment, as shown inFIG. 5, the present invention disclosed a trench MOSFET cell comprising: a heavily doped substrate of a first semiconductor doping type, e.g., N dopant, with a layer of Ti/Ni/Ag on the rear side serving as drain metal; a lighter doped epitaxial layer of a first semiconductor doping type grown on said substrate; a plurality of trenches etched into said epitaxial layer as gate trenches; a gate oxide layer along the inner surface of said gate trenches; doped poly filled within said gate trenches to form trench gates; a thin oxide layer formed onto trench gate and the top surface of epitaxial layer; body regions of a second semiconductor doping type, e.g., P dopant, extending between every two trench gates; source regions above the top surface of P-body regions; an oxide interlayer film onto front surface of a thin oxide layer; a vertical source-body contact trench penetrating through said oxide interlayer, said source regions and into said body regions with vertical sidewalls; P+ area wrapping the bottom of source-body contact trench to reduce the resistance between source and body; W metal deposited over a layer of Ti/TiN or Co/TiN to serve as contact metal plug into source-body contact trench and also serve as buffer layer covering the surface of the oxide interlayer; metal Al alloys or Copper over Ti or Ti/TiN layer deposited onto a resistance reduction layer composed of Ti or Ti/N to serve as source and gate metal with Cu wires bonded whereon.

Briefly, in another preferred embodiment, as shown inFIG. 6, the present invention disclosed a trench MOSFET cell same asFIG. 5except the slope source-body contact trench.

Briefly, in another preferred embodiment, as shown inFIG. 7, the present invention disclosed a trench MOSFET cell same asFIG. 5except that the source-body contact trench is vertical in source region and slope in body region

Briefly, in another preferred embodiment, as shown inFIG. 9, the present invention disclosed a trench MOSFET cell comprising: a heavily doped substrate of a first semiconductor doping type, e.g., N dopant, with a layer of Ti/Ni/Ag on the rear side serving as drain metal; a lighter doped epitaxial layer of a first semiconductor doping type grown on said substrate; a plurality of trenches etched into said epitaxial layer as gate trenches and especially, trench for gate connection is wider than others; a gate oxide layer along the inner surface of said gate trenches; doped poly filled not within gate trenches but to form terrace gates above gate oxide layer; a thin oxide layer formed onto the top surface of said epitaxial layer; body regions of a second semiconductor doping type, e.g., P dopant, extending between every two terrace gates; source regions near the top surface of P-body regions; oxide interlayer layer deposited above the thin oxide layer and covering the sidewalls and surface of terrace gate to form self-aligned contact structure; source-body contact trench with a smaller width in Si portion than in oxide interlayer portion; gate contact trench opened through oxide interlayer and into terrace gate for gate connection; P+ area wrapping the source-body contact trench bottom and the sidewalls inside P-body portion; W metal deposited over a layer of Ti/TiN or Co/TiN to serve as contact metal plug into source-body contact and gate contact trench, and also serve as buffer layer covering the surface of oxide interlayer; metal Al alloys or copper over Ti or Ti/TiN deposited onto a resistance reduction layer composed of Ti or Ti/N to be patterned as source and gate metal with Cu wires bonded whereon.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Please refer toFIG. 5for a preferred embodiment of the present invention. The shown trench MOSFET cell is formed on an N+ substrate400coated with back metal Ti/Ni/Ag422on rear side as drain. Onto said substrate400, grown an N epitaxial layer402, and a plurality of trenches were etched wherein. To fill these trenches, doped poly was deposited into trenches above gate oxide layer408to form trench gates410. P-body regions412are extending between trenches gates410with a layer of source regions414above the top surface of P-body regions412. Source-body contact trench is etched through an oxide interlayer418, a thin oxide layer408′ and N+ source region414, and into P-body region412. Especially, the sidewalls of source-body contact trench are perpendicular to the front surface of epitaxial layer. To fill source-body contact trench, Ti/TiN/W or Co/TiN/W is deposited not only within contact trench as metal plug416but also cover the surface of oxide interlayer418to act as buffer layer417for Cu wire bonding. Underneath the metal plug416, a heavily P+ doped area406is formed wrapping its bottom to reduce the resistance between source and body. Above the buffer layer417, a source metal420either Al alloys or Copper is deposited over a resistance reduction layer419composed of a low resistance metal layer such as a Ti or Ti/TiN layer for reducing contact resistance between the source metal420and the buffer layer417, electrically connected to source region and body region with Cu bonding wire424bonded whereon while drain metal Ti/Ni/Ag422is deposited on the rear side of the substrate.

FIG. 6shows another preferred embodiment of the present invention. Comparing toFIG. 5, the structure inFIG. 6has a different source-body contact structure with slope sidewalls to partially enlarge the P+ area along source-body contact trenches.

FIG. 7shows another preferred embodiment of the present invention. Comparing toFIG. 5, the structure inFIG. 7has a different source-body contact structure. Especially, the sidewalls of source-body contact trenches are perpendicular to the front surface of epitaxial layer within the oxide interlayer and N+ source region while is oblique within P-body region with a taper angle less than 85 degree respective to top surface.

FIG. 8shows structure inFIG. 5with trench gate metal area. At least a wider trench gate410′ is formed inside epitaxial layer for gate connection wherein a gate contact trench is etched and filled with Ti/TiN/W or Co/TiN/W to connect trench gate to gate metal. Buffer layer and front metal are patterned to form source metal420with Cu bonding wire424over buffer layer417and gate metal420′ with Cu bonding wire424′ over buffer layer417′.

FIG. 9shows another preferred embodiment of the present invention with trench gate metal area. The disclosed trench MOSFET cell formed on an N+ substrate500coated with back metal Ti/Ni/Ag on rear side as drain. Onto said substrate500, grown an N epitaxial layer502, and a plurality of trenches were etched wherein, especially, a trench for gate connection is wider than trenches under source metal region. To fill these trenches, doped poly was deposited not within those trenches but to form terrace gate510and510′ above gate oxide layer508. P-body regions512are extending between said trenches with a layer of source regions514above the top surface of said P-body region between trenches510. Self-aligned source-body contact structure is implemented through oxide interlayer518, a thin oxide layer508′ and into epitaxial layer while gate contact trench is etched through the oxide interlayer518and into terrace gate510′. To be detailed, the width of source-body contact in upper oxide interlayer portion is bigger than that within epitaxial layer and underneath said source-body contact, P+ area506is implanted to reduce the resistance between source and body. Metal W is deposited over a layer of Ti/TiN or Co/TiN into source-body contact trench and gate contact trench to form source-body contact516and gate contact516′ while covering the surface of oxide interlayer518to serve as buffer layer517and517′ for Cu wire bonding. Source metal520bonded with Cu bonding wire524and gate metal520′ bonded with Cu bonding wire524′ are formed over resistance reduction layer519and519′ composed of a low resistance metal layer such as a Ti or Ti/TiN layer for reducing contact resistance between source metal520and buffer layer517, and gate metal520′ and buffer layer517′, respectively.

FIGS. 10A to 10Eshow a series of exemplary steps that are performed to form the inventive trench MOSFET of the present invention shown inFIG. 8. InFIG. 10A, an N-doped epitaxial layer402is grown on an N+ substrate400, then, a trench mask (not shown) is applied, which is then conventionally exposed and patterned to leave mask portions. The patterned mask portions define the gate trenches410aand at least a wider gate trench410a′ for gate connection, which are dry silicon etched through mask opening to a certain depth. InFIG. 10B, a sacrificial oxide (not shown) is grown and then removed to eliminate the plasma damage may introduced during trenches etching process. After the trench mask removal, a gate oxide408is formed on the front surface of epitaxial layer and the inner surface of gate trenches410aand410a′. Next, all gate trenches410aand410a′ are filled with doped poly to form trench gates410and at least a wider trench gate410′ for gate connection. Then, the filling-in conductive material such as doped poly is etched back or CMP (Chemical Mechanical Polishing) to expose the portion of gate oxide layer that extends over the surface of epitaxial layer. Next, by employing a P-body mask, an Ion Implantation is applied to form P-body regions412, followed by a P-body diffusion step for P-body region drive in. After removing the P-body mask, another Ion Implantation is applied to form N+ source regions414using a source mask followed by an n+ diffusion step for source regions drive in. Then, a thin oxide layer408′ is formed over whole top surface. InFIG. 10C, the process continues with the deposition of oxide interlayer418over thin oxide layer408′. Then, a contact mask (not shown) is applied to carry out the source-body contact etch to open the source-body contact trench416aand gate contact etch to open gate contact trench416a′ by successive dry oxide etching and dry silicon etching. Next, the BF2 Ion Implantation is applied over entire surface to form the P+ area wrapping the bottom of source-body contact trench within P-body region to further reduce resistance betweens source and body. InFIG. 10D, after the deposition of Ti/TiN or Co/TiN layer, source-body contact trench416aand gate contact trench416a′ are filled with W metal to form source-body contact416and gate contact416′. At the same time, the deposited W metal formed a buffer layer417for Cu wire bonding. After that, Al Alloys or copper metal layer is deposited over a resistance reduction layer419composed of a low resistance metal layer such as a Ti or Ti/TiN layer to serve as front metal420. Last, inFIG. 10E, metal mask is deposited to pattern the metal layer and buffer layer into source portion and gate portion by dry metal etching, as illustrated, after removing the metal material, front metal is patterned into source metal420and gate metal420′ while buffer layer is patterned into source portion417and gate portion417′. Drain metal422Ti/Ni/Ag422is then deposited on rear surface after backside grinding.