Semiconductor device and method of using

A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority to Chinese Application No. 202110096367.8, filed Jan. 25, 2021, the entirety of which is hereby incorporated by reference.

BACKGROUND

Applying a bias voltage to a substrate helps to control a threshold voltage of devices manufactured on that substrate. The threshold voltage is the voltage level of a signal used to activate a transistor to transition from a non-conductive state to a conductive state. The bias voltage is usable to reduce the threshold voltage in some instances in order to utilize signals having a lower voltage for operating the device.

In order to reliably manufacture the devices, conductive structures in the device are enlarged in order to help ensure the formation of a conductive path regardless of offset errors during the manufacturing process. In some instances, an extrinsic gate is added to a gate structure in order to help pick up a bias voltage. An extrinsic gate is a conductive structure that expands the gate in two dimensions, i.e., a length and a width of the gate structure is increased by the inclusion of an extrinsic gate. The inclusion of an extrinsic gate increases the size of the overall gate structure. In addition, the extrinsic gate also is designed to satisfy design spacing rules, which determine how close different components of the device are able to be reliably manufactured. In some instances, the inclusion of the extrinsic gate structure results in the overall gate structure having an L-shape or a T-shape.

DETAILED DESCRIPTION

As mentioned above, the inclusion of extrinsic gates in gate structures in order to help pick up bias voltages increases a size of a device. Not only does the extrinsic gate increase the size of the gate structure overall, but the design rule spacing for reliably manufacturing the extrinsic gate further increases the size of the device. In order to avoid the use of extrinsic gate structures in gate structures used to pick up the bias voltage, a silicide material is extended between adjacent pick up gate structures. In addition, a doped region also extends into the space between adjacent gate structures. By including the silicide region and the doped region between the adjacent gate structures, the bias voltage is reliably supplied to a bulk of the device and the overall size of the device is decreased. In some embodiments, the size reduction of the device ranges from about 13% to about 25% in comparison to devices that include extrinsic gate structures in the pick-up gate structures.

In addition, parasitic capacitance is reduced between the pick-up gate structures and other gate structures within the device. In some embodiments, parasitic capacitance is reduced by about 13% in comparison with devices that include extrinsic gate structures in the pick-up gate structures. Reducing the parasitic capacitance within the device helps the device to operate faster in comparison with devices having higher parasitic capacitance.

FIG.1is a top view of a semiconductor device100in accordance with some embodiments. The semiconductor device100is a metal-oxide-semiconductor (MOS) structure. The following description of semiconductor device100is based on a p-type MOS (PMOS) structure. However, one of ordinary skill in the art would recognize that the current disclosure is also applicable to an n-type MOS (NMOS) structure by changing dopant types in the following description.

The semiconductor device100includes an n-well102around a perimeter of the semiconductor device100. An n-doped region104is in a substrate and extends across the semiconductor device100in a first direction. A p-doped region106is in the substrate and is spaced from the n-doped region104. An isolation region108surrounds the p-doped region106. A first pick-up gate structure110aand a second pick-up gate structure110b, collectively referred to as pick-up gate structures110, extend in a second direction perpendicular to the first direction. The pick-up gate structures110extend over the p-doped region106and a portion of the n-doped region104. A first operating gate structure120aand a second operating gate structure120b, collectively referred to as operating gate structures120, are next to the pick-up gate structures110. The second operating gate structure120bincludes an intrinsic portion120b′ and an extrinsic portion120b″. The extrinsic portion120b″ is an example of an extrinsic gate structure. The operating gate structures120extends over the p-doped region106and a portion of the n-doped region104. The semiconductor device100further includes a silicide structure130. The silicide structure130is over the n-doped region104. The silicide structure130includes a main body133extending in the first direction over the n-doped region104away from the pick-up gate structures110and the operating gate structures120. The silicide structure130further includes a silicide extension135that extends from the main body133to a region between the pick-up gate structures110. The n-doped region104also extends into the region between the pick-up gate structures110.

The n-well102is formed by implanting n-type dopants into a substrate to form a region of the substrate having n-type conductivity. In some embodiments, the implanted dopants include phosphorous, arsenic or another suitable n-type dopant. In some embodiments, a dopant concentration in the n-well102ranges from about 1×1014atoms/cm3to about 1×1017atoms/cm3. If the dopant concentration is too high, then a risk of current leakage through the substrate increases, in some instances. If the dopant concentration is too high, then a bias voltage is unable to impact each of the devices formed on the substrate, in some instances.

The n-doped region104is also formed by implanting n-type dopants into the substrate. A concentration of n-type dopants in the n-doped region is higher than a concentration of n-type dopants in the n-well. The n-well102surrounds n-doped region104. In some embodiments, a dopant concentration in the n-doped region104ranges from about 1×1016atoms/cm3to about 1×1018atoms/cm3. If the dopant concentration is too high, then a risk of current leakage through the substrate increases, in some instances. If the dopant concentration is too high, then a bias voltage is unable to impact each of the devices formed on the substrate, in some instances. In some embodiments, a dopant in the n-well102is a same dopant as that in the n-doped region104. In some embodiments, the dopant in the n-well102is different from the dopant in the n-doped region104.

The n-doped region104extends between the pick-up gate structures110. A portion of the n-doped region is exposed between each of the pick-up gate structures110and the silicide extension135. In some embodiments, a spacing Ss between each of the pick-up gate structures110and the silicide extension135ranges from about 50 nanometers (nm) to about 100 nm. If the spacing Ss is too small, then a risk of the silicide extension135short circuiting to the pick-up gate structures110increases, in some instances. If the spacing Ss is too large, then the size of the semiconductor device100is increased without a noticeable increase in performance, in some instances.

The p-doped region106is formed by implanting p-type dopants into the substrate. The n-well102surrounds p-doped region106. In some embodiments, the p-type dopants include boron, boron difluoride or another suitable p-type dopant. In some embodiments, a dopant concentration in the p-doped region106ranges from about 1×1016atoms/cm3to about 1×1018atoms/cm3. If the dopant concentration is too high, then a risk of current leakage through the substrate increases, in some instances. If the dopant concentration is too high, then a bias voltage is unable to impact each of the devices formed on the substrate, in some instances.

In the top view, the p-doped region106is recessed in the second direction between the pick-up gate structures110to permit the n-doped region104and the silicide extension135to extend between the pick-up gate structures. The p-doped region106outside of the pick-up gate structures110is closer to the silicide main body133than the p-doped region between the pick-up gate structures110.

The isolation region108provides electrical separation between the n-doped region104and the p-doped region106near the silicide structure130. In some embodiments, the isolation region108is a shallow trench isolation (STI). In some embodiments, the isolation region108is formed by etching a portion of the substrate to form a recess and filling the recess with a dielectric material. In some embodiments, the isolation region108is formed by local oxidation of the substrate.

The pick-up gate structures110are configured to assist in coupling the bias voltage into the substrate. The pick-up gate structures110include only intrinsic gate structures without extrinsic gate structures. As a result, the pick-up gate structures110have an I-shape. A width W of the pick-up gate structures110remains constant along an entirety of the gate structures. In an upper region of pick-up gate structure110a, a first edge of the pick-up gate structure110ais aligned with the p-doped region106while a second edge, opposite the first edge, is aligned with the n-doped region104. Similarly, in an upper region of pick-up gate structure110b, a third edge of the pick-up gate structure110bis aligned with the n-doped region104and a fourth edge, opposite the third edge, is aligned with the p-doped region106. Both of the pick-up gate structures include an end region where both edges are aligned with the n-doped region104, and a lower region where both edges are aligned with the p-doped region106. In some embodiments, the pick-up gate structures110include polysilicon or metal. In some embodiments, the pick-up gate structures110include a gate dielectric material, for example, a high-k gate dielectric material.

The operating gate structures120are usable for implementing the functioning of the semiconductor device100. That is, each of the operating gate structures120is usable to selectively electrically connect a corresponding source to a corresponding drain. A threshold voltage for selectively electrically connecting the corresponding source to the corresponding drain is determined in part based on the bias voltage coupled to the substrate near the pick-up gate structures110. Each of the operating gate structures120includes both an intrinsic gate structure and an extrinsic gate structure. For example, operating gate structure120bincludes an intrinsic gate structure120b′ and an extrinsic gate structure120b″. The intrinsic gate structure120b′ helps with operation of the operating gate structure120b. The extrinsic gate structure120b″ helps to isolate the corresponding source and drain. Due to the extrinsic gate structure, the operating gate structures120have a variable width. In some embodiments, the operating gate structures120include polysilicon or metal. In some embodiments, the operating gate structures120include a same material as the pick-up gate structures110. In some embodiments, the operating gate structures120include a different material from the pick-up gate structures110. In some embodiments, the operating gate structures120include a gate dielectric material, for example, a high-k gate dielectric material. In some embodiments, a gate dielectric material of the operating gate structures120is a same material as a gate dielectric material of the pick-up gate structures. In some embodiments, the gate dielectric material of the operating gate structures120is different from the gate dielectric material of the pick-up gate structures110.

The silicide structure130extends over the n-doped region104to electrically connect to a bias voltage supply. The silicide structure130is formed by depositing a metal layer over the substrate and then annealing the semiconductor device100. During the annealing, the silicon of the substrate reacts with the metal layer to form the silicide structure. In some embodiments, the silicide structure130is electrically connected to the bias voltage supply by an interconnect structure (not shown). In some embodiments, the silicide structure130is electrically connected to the bias voltage supply by a through substrate via (TSV) (not shown).

The silicide structure130includes the main body133extending in the first direction, and the silicide extension135extending in the second direction away from the main body133. The main body133extends beyond the pick-up gate structures110and the operating gate structures120in the first direction.

The silicide extension135extends between the pick-up gate structures110. A first portion of the silicide extension135is spaced from each of the pick-up gate structures110by a silicide spacing distance Ss. The silicide spacing distance Ss ranges from about 50 nanometers (nm) to about 100 nm. If the silicide spacing distance Ss is too small, then a risk of shorting the silicide structure to a conductive portion of the pick-up gate structures110increases, in some instances. If the silicide spacing distance Ss is too great, then a size of the semiconductor device100is increased without an increase in performance, in some instances. A second portion of the silicide extension135contacts each of the pick-up gate structures110. The second portion of the silicide extension135is farther from the main body133than the first portion of the silicide extension135. An edge of the silicide extension135farthest from the main body133is aligned with the p-doped region106.

A distance D from a center of the silicide extension135to a closest edge of the operating gate structures120is reduced by about 30% in comparison to other structures which do not include the silicide extension135. Overall, a size of the semiconductor device100is reduced by about 13% to about 25% in comparison to other structures which do not include the silicide extension135. Further, each of the pick-up gate structures110has a parasitic capacitance reduction of about 13% in comparison with other structures where the pick-up gate structures include extrinsic gate structures.

FIG.2is a top view of a portion of the semiconductor device100in accordance with some embodiments.FIG.2is a top view of a zone140fromFIG.1in some embodiments. In comparison withFIG.1,FIG.2includes contacts210a,210b,210cand210d, collectively referred to as the contacts210. The contacts210provide electrical connection between the corresponding source and drain regions of the pick-up gate structures and an interconnect structure (not shown). An interface line220is used to indicate where the isolation region108meets the p-doped region106.

A width Sw of the silicide extension135between the pick-up gate structures110ranges from about 300 nm to about 400 nm. If the width Sw is too small, then an ability to reliably manufacture the semiconductor device decreases, in some instances. If the width Sw is too great, then the semiconductor device100is increased in size without significant improvement in performance, in some instances.

Positions a, b and c indicate a flow of a bias voltage through the silicide structure130and into the n-doped region104below the pick-up gate structures. This flow is also included inFIGS.4and6, discussed below.

FIG.3is a cross-sectional view of a portion of the semiconductor device100taken along line A-A ofFIG.2in accordance with some embodiments. The semiconductor device100includes a bulk substrate310. An insulating layer320is over the bulk substrate310. The isolation region108surrounds the n-doped region104and the p-doped region106of the substrate. As discussed above, the n-doped region104and the p-doped region106are formed in a semiconductor layer, such as silicon. In some embodiments, the semiconductor device100is call a silicon-on-insulator (SOI) device.

The silicide structure130is on the p-doped region106between the pick-up gate structures110. The contact210ais electrically connected to the p-doped region106on a first side of the pick-up gate structure110aopposite to the silicide structure130. The contact210bis electrically connected to the p-doped region106on a second side of the pick-up gate structure110bopposite to the silicide structure130.

Each of the pick-up gate structures110is over the n-doped region104. The pick-up gate structure110aincludes a gate dielectric material115aand a conductive layer117a. In some embodiments, the gate dielectric material115aincludes a high-k dielectric material. In some embodiments, the conductive layer117aincludes polysilicon or metal. The pick-up gate structure110bincludes a gate dielectric material115band a conductive layer117b. In some embodiments, the gate dielectric material115bincludes a high-k dielectric material. In some embodiments, the gate dielectric material115bincludes a same material as the gate dielectric material115a. In some embodiments, the gate dielectric material115bincludes a different material from the gate dielectric material115a. In some embodiments, the conductive layer117bincludes polysilicon or metal. In some embodiments, the conductive layer117bincludes a same material as the conductive layer117a. In some embodiments, the conductive layer117bincludes a different material from the conductive layer117b.

FIG.4is a cross-sectional view of a portion of the semiconductor device100taken along line B-B ofFIG.2in accordance with some embodiments. In comparison withFIG.3, the silicide structure130is over the n-doped region104between the pick-up gate structures110. The n-doped region104is continuous from under pick-up gate structure110ato under pick-up gate structure110b. The contact210cis electrically connected to the p-doped region106on the first side of the pick-up gate structure110aopposite to the silicide structure130. The contact210dis electrically connected to the p-doped region106on the second side of the pick-up gate structure110bopposite to the silicide structure130. The bias current flow from position b to position c will be discussed in detail below.

FIG.5is a cross-sectional view of a portion of the semiconductor device100taken along line C-C ofFIG.2in accordance with some embodiments. In comparison withFIG.3, the silicide structure130is over the n-doped region104between the pick-up gate structures110. Each of the pick-up gate structures110is over the isolation region108.

FIG.6is a cross-sectional view of a portion of the semiconductor device100taken along line D-D ofFIG.2in accordance with some embodiments. The silicide structure130extends over the n-doped region104and over the p-doped region106. The portion of the silicide structure130over the n-doped region104is either the main body133(FIG.1) or a portion of the silicide extension135near the main body133. The bias current flow from position a to position b will be discussed in detail below.

FIG.7is a cross-sectional view of a portion of the semiconductor device100taken along line E-E ofFIG.2in accordance with some embodiments. The silicide structure130is over the n-doped region104. The portion of the silicide structure130inFIG.7is the main body133. The silicide structure130is separated from the pick-up gate structure110a. A first portion of the pick-up gate structure110abeyond the interface line220is over the isolation region108. A second portion of the pick-up gate structure110aadjacent to the interface line220is over the n-doped region104. A third portion of the pick-up gate structure110afarther from the interface line220is over the p-doped region106.

Returning to the bias voltage flow ofFIGS.4and6, the silicide structure130is electrically connected to the bias voltage supply. The bias voltage flows through an interconnect structure or TSV (not shown) to the silicide structure. The bias voltage travels along the main body133(FIG.1) of the silicide structure to reach position a. As indicated inFIG.2, the position a is at a location where the silicide extension135connects to the main body133. The bias voltage then flows along the silicide extension135to position b, as indicated inFIG.6. As indicated inFIG.2, position b is a portion of the silicide extension135beyond the interface line220. From position b, the bias voltage then flow into the substrate by entering the n-doped region104below the pick-up gate structures110, as indicated inFIG.4. By controlling the voltage in the n-doped region104, the threshold voltage of the operating gate structures120(FIG.1) are able to be controlled.

FIG.8is a top view of a portion of the semiconductor device100in accordance with some embodiments.FIG.8is similar toFIG.1.FIG.8is provided separate fromFIG.1in order to provide information related to dimensions of the semiconductor device100. The various components of the semiconductor device100are not labeled inFIG.8for the sake of clarity of the drawing.

In some embodiments, a width a1of the main body133in the first direction ranges from about 200 nm to about 300 nm. If the width a1is too small, then resistance of the main body133increases and the bias voltage applied to the substrate is reduced, in some instances. If the width a1is too great, then a size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance a2of the pick-up gate structures110beyond the p-doped region106ranges from about 140 nm to about 450 nm. If the distance a2deviates too far from this range, then a length of the pick-up gate structures110in the first direction is significantly different from the length of the operating gate structures120and formation of the semiconductor device100becomes more complicated and a risk of error in manufacturing increases, in some instances.

In some embodiments, a distance a3between an edge of the pick-up gate structures110and the silicide extension135ranges about 50 nm to about 100 nm. If the distance a3is too small, then a risk of the silicide extension135short circuiting to the pick-up gate structures110increases, in some instances. If the distance a3is too large, then the size of the semiconductor device100is increased without a noticeable increase in performance, in some instances.

In some embodiments, a width a4of the silicide extension135that does not contact the pick-up gate structures110ranges from about 180 nm to about 240 nm. If the width a4is too small, then resistance of the silicide extension135increases and the bias voltage applied to the substrate is reduced, in some instances. If the width a4is too great, then a size of the semiconductor device100increase without appreciable improvement in performance, in some instances.

In some embodiments, a width a5of the p-doped region106in the second direction between the pick-up gate structures110ranges from about 200 nm to about 280 nm. If the width a5is too small, then the width a4is also reduced and the resistance of the silicide structure130increases to an unacceptable level, in some instances. If the width a5is too great, then the size of the semiconductor device100is increased without an appreciable improvement in performance, in some instances.

In some embodiments, a distance a6between the pick-up gate structure110band the extrinsic gate of the operating gate structure120ain the second direction ranges from about 140 nm to about 240 nm. If the distance a6is too small, then the pick-up gate structure110band the operating gate structure120acannot be manufactured reliably, in some instances. If the distance a6is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance a7in which the extrinsic gate extends beyond the p-doped region106in the second direction ranges from about 140 nm to about 240 nm. If the distance a7is too small, then extrinsic gate fails to provide sufficient isolation between the corresponding source and drain, in some instances. If the distance a7is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance a8in which the extrinsic gate extends overlaps the p-doped region106in the second direction ranges from about 75 nm to about 150 nm. If the distance a8is too small, an interface between the operating gate structures120and the silicide structure130is reduced, in some instances. If the distance a8is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a width a9of the extrinsic gate of the operating gate structures120in the first direction ranges from about 240 nm to about 300 nm. If the width a9is too small, then extrinsic gate fails to provide sufficient isolation between the corresponding source and drain, in some instances. If the width a9is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a width a10of the intrinsic gate of the operating gate structures120in the second direction ranges from about 180 nm to about 280 nm. If the width a10is too small, then intrinsic gate fails to provide sufficient isolation between the corresponding source and drain, in some instances. If the width a10is too great, then the operating speed of the semiconductor device100is reduced, in some instances.

In some embodiments, a distance a11between an outer portion of the extrinsic gate and the p-doped region106in the first direction ranges from about 50 nm to about 150 nm. If the distance a11is too small, then extrinsic gate fails to provide sufficient isolation between the corresponding source and drain, in some instances. If the distance a11is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance a12between an outer portion of the extrinsic gate and the main body133in the first direction ranges from about 50 nm to about 100 nm. If the distance a12is too small, then a risk of the extrinsic gate shorting to the silicide structure130increases, in some instances. If the distance a12is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance b1between an outer edge of the pick-up gate structure110aand an outer edge of the p-doped region106in the second direction ranges from about 280 nm to about 350 nm. If the distance b1is too small, then a size of a source or drain in the p-doped region106is reduced and resistance for a current through the contacts210increases, in some instances. If the distance b1is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance b2between an outer edge of the pick-up gate structure110band an intrinsic gate of the operating gate structure120ain the second direction ranges from about 350 nm to about 500 nm. If the distance b2is too small, then the pick-up gate structure110band the operating gate structure120acannot be manufactured reliably, in some instances. If the distance b2is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

In some embodiments, a distance b3between an intrinsic gate of the operating gate structure120band an intrinsic gate of the operating gate structure120ain the second direction ranges from about 600 nm to about 750 nm. If the distance b3is too small, then the operating gate structures120cannot be manufactured reliably, in some instances. If the distance b3is too great, then the size of the semiconductor device100is increased without appreciable improvement in performance, in some instances.

FIG.9is a top view of a portion of a semiconductor device900in accordance with some embodiments. The semiconductor device900is similar to the semiconductor device100(FIG.1). Description of components of the semiconductor device900that are similar to the semiconductor device100is omitted for the sake of brevity. Unless otherwise noted, dimensions of the semiconductor device900are similar to the dimension of the semiconductor device100, as described above with respect toFIG.8.FIG.9is a top view of a portion of the semiconductor device900similar to the zone140fromFIG.1in some embodiments. In comparison withFIG.2, the silicide structure930ofFIG.9includes a main body933and a silicide extension935which completely fills a space between the pick-up gate structures110. While the main body933remains separated from the pick-up gate structures110, the silicide extension935contacts an edge of the pick-up gate structures110adjacent to the main body933. A composition of n-doped region904is similar to the composition of the n-doped region104described above. A composition of the silicide structure930is similar to the composition of the silicide structure130described above.

FIG.10is a cross-sectional view of a portion of the semiconductor device900taken along line *C-*C ofFIG.9in accordance with some embodiments. In comparison withFIG.5, the n-doped region904extends below both of the pick-up gate structures110.

FIG.11is a cross-sectional view of a portion of the semiconductor device900taken along line *E-*E ofFIG.9in accordance with some embodiments. In comparison withFIG.7, the n-doped region904extends below the pick-up gate structure110aclosest to the main body933(FIG.9). In addition, the silicide extension935directly contacts the pick-up gate structure110a.

In comparison with the semiconductor device100, the semiconductor device900is able to provide faster transfer of the bias voltage from the bias voltage supply to the substrate. The increased size of the silicide structure930in comparison with the silicide structure130reduces resistance to the flow of the bias voltage. The increased size of the n-doped region904also helps to supply the bias voltage to different areas of the semiconductor device900with reduced isolation from the isolation region108(FIG.1).

FIG.12is a flow chart of a method1200of using a semiconductor device in accordance with some embodiments. In some embodiments, the method1200is implemented using the semiconductor device100or the semiconductor device900.

In operation1205, a bias voltage is transferred to a silicide structure form a bias voltage supply. In some embodiments, the bias voltage supply is a bus carrying a source voltage, e.g., VDD. In some embodiments, the bias voltage is transferred to the silicide structure using an interconnect structure. In some embodiments, the bias voltage is transferred to the silicide structure using a TSV. In some embodiments, transfer of the bias voltage to the silicide structure is controlled by at least one transistor in order to control the amount of bias voltage provided to the substrate in order to tune the threshold voltage of elements within the semiconductor device.

In operation1210, the bias voltage is conducted along the silicide structure to a silicide extension between pick-up gate structures. The silicide extension is integral with the silicide structure. The silicide structure extends between pick-up gate structures. In some embodiments, a first portion of the silicide extension between the pick-up gate structures is spaced from the pick-up gate structures; and a second portion of the silicide extension between the pick-up gate structures directly contacts the pick-up gate structures. In some embodiments, an entirety of the silicide extension between the pick-up gate structures directly contacts the pick-up gate structures. In some embodiments, the silicide extension directly contacts an edge of the pick-up gate structures closest to a main body of the silicide structure.

In operation1215, the bias voltage is transferred from the silicide extension into a doped region of a substrate below the pick-up gate structures. In some embodiments, the doped region includes an n-doped region. In some embodiments, the substrate is an SOI substrate. In some embodiments, the doped region is directly beneath the pick-up gate structures only in a location where the pick-up gate structures are in direct contact with the silicide extension. In some embodiments, the doped region is directly beneath the pick-up gate structures along an entirety of the pick-up gate structures.

An aspect of this description relates to a semiconductor device. The semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area. In some embodiments, each of the plurality of first gate structures has an I-shape. In some embodiments, the semiconductor device further includes a plurality of second gate structures, wherein each of the plurality of second gate structures has a T-shape. In some embodiments, the silicide extension includes a first portion in direct contact with the adjacent gate structures of the plurality of first gate structures. In some embodiments, the silicide extension includes a second portion spaced from each of the adjacent gate structures of the plurality of first gate structures. In some embodiments, the silicide extension directly contacts an edge of each of the plurality of first gate structures, and the edge is a closest edge of each of the plurality of first gate structures to the main body. In some embodiments, the semiconductor device further includes an isolation region in the substrate, wherein the isolation region directly contacts the second doped region at an interface. In some embodiments, a portion of each of the plurality of first gate structures extending beyond the interface is over the isolation region. In some embodiments, a portion of each of the plurality of first gate structures extending beyond the interface is over the first doped region.

An aspect of this description relates to a semiconductor device. The semiconductor device includes an n-doped region in a substrate. The semiconductor device further includes a p-doped doped region in the substrate. The semiconductor device further includes a silicide structure over the n-doped region, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein the n-doped region extends into a space of the substrate exposed by adjacent gate structures of the plurality of first gate structures, and the silicide extension extends between the adjacent gate structures of the plurality of first gate structures. In some embodiments, a width of the silicide extension between the adjacent gate structures of the plurality of first gate structures is constant. In some embodiments, a width of the silicide extension between the adjacent gate structures of the plurality of first gate structures is variable. In some embodiments, the silicide extension directly contacts each of the plurality of first gate structures along an entire edge adjacent to the space. In some embodiments, the silicide extension is spaced from a portion of an edge of each of the plurality of first gate structures adjacent to the space. In some embodiments, the semiconductor device further includes a plurality of second gate structures on the substrate. In some embodiments, each of the plurality of second gate structures has a T-shape, and each of the plurality of first gate structures has an I-shape.

An aspect of this description relates to a method of biasing a substrate. The method includes electrically connecting a silicide structure to a bias voltage supply. The method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. The method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures. In some embodiments, electrically connecting the silicide structure to the bias voltage supply includes electrically connecting the silicide structure to the bias voltage supply using an interconnect structure. In some embodiments, electrically connecting the silicide structure to the bias voltage supply includes electrically connecting the silicide structure to the bias voltage supply using a through silicon via (TSV). In some embodiments, transferring the bias voltage to into the doped region includes transferring the bias voltage to the doped region from a portion of the silicide extension in direct contact with each of the plurality of first gate structures.