Power chip set for a switching mode power supply having a device for providing a drive signal to a control unit upon startup

A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.

FIELD OF THE INVENTION
 The present invention relates to an integrated circuit (IC) of a switching
 mode power supply (SMPS), and more particularly to a power chip set for an
 SMPS.
 BACKGROUND OF THE INVENTION
 It is a principal concern of the cost to manufacture a power supply in
 selecting between power supply types to be used in particular application
 and the components selected to construct them. Since integrated circuit
 technology has advanced such that a majority of the complex switching mode
 circuits can be integrated on a single chip, switching mode power supplies
 have become cost competitive with much simpler linear power supplies.
 A prior art flyback power supply with a voltage regulator is schematically
 shown in FIG. 1. In a power supply circuit 10, a full-wave bridge
 rectifier 12 accepts an AC power from a set of power input terminals 14,
 and a DC power is therefore supplied to a transformer 18 in association
 with a filter capacitor 16. The transformer 18 comprises a primary winding
 20 and a pair of secondary windings 22 and 24. A capacitor 28 is charged
 through the winding 22 and a diode 26 such that a power supply output
 voltage is provided at a set of output terminals 30 of the power supply
 circuit 10. On the other hand, a capacitor 34 is charged through the
 winding 24 and a diode 32 to provide a feedback voltage, which is
 delivered to a pulse width modulator (PWM) 40 through a voltage divider
 consisting of resistors 52 and 54. An end of the winding 20 is connected
 to a high voltage switching transistor 38 in a regulator circuit 36, which
 is turned on/off under the control of a signal from the PWM 40. The
 control signal from the PWM 40 to a gate of the switching transistor 38
 oscillates at a frequency with a duty cycle such that a preset output
 voltage is maintained between the set of output terminals 30 of the power
 supply circuit 10.
 A high voltage power start up transistor 42 is used to start up the
 regulator circuit 36. When power is turned on, the transistor 42 is turned
 on and the capacitor 34 is charged to provide a line 50 with internal low
 voltage power. Once the voltage on the line 50 reaches a threshold
 voltage, the PWM 40 functions, and when the voltage on the line 50 reaches
 a specific threshold voltage, a transistor 46 is turned on. As a result,
 the threshold voltage from a voltage source 48 is connected to a gate of
 the transistor 42, and thus the transistor 42 is turned off. As shown in
 FIG. 1, a resistor 44 is connected to a drain of the transistor 42.
 To overcome the inconveniences caused by the high voltage pins of a chip
 and the high voltage itself, Balakrishnan disclosed in U.S. Pat. No.
 5,014,178 a high voltage power start up transistor directly connected to a
 drain of a high voltage switching transistor, while in U.S. Pat. No.
 5,313,381 a feedback control signal and a bias supply voltage combined at
 a single pin with a metal-oxide-semiconductor (MOS) transistor, such as
 that proposed in U.S. Pat. No. 4,811,075 to Eklund. However, complicated
 circuits and expensive manufacturing processes are presented in these
 prior arts. In addition, it is desired a further integration and excellent
 performance for an SMPS circuit.
 SUMMARY OF THE INVENTION
 Therefore, an object of the present invention is to provide a power chip
 set for an SMPS.
 Briefly, a chip set according to the present invention comprises a high
 voltage chip and a control unit chip, in which the high voltage chip
 contains a junction field effect transistor (JFET) connected to the
 control unit and served as its power start up element. The JFET has a
 negative threshold voltage and its absolute value is equal to the value of
 the voltage to start up the control unit.
 It is one aspect of the present invention that the JFET further contains a
 Zener diode for over voltage protection to the power start up terminals of
 the control unit.
 One advantage of the present invention resides in that the JFET is
 manufactured in a process compatible with the power MOS, and therefore the
 JFET and the high voltage switching power MOS transistor are integrated on
 a single chip.
 Another advantage of the present invention resides in that the chip set is
 constituted of the high voltage chip and the control unit chip, such that
 expensive IC manufacturing process is avoided and a smaller chip area is
 obtained. The chip set can be packaged into a module.

DETAILED DESCRIPTION OF THE INVENTION
 One embodiment according to the present invention is shown in FIG. 2, in
 which a power module 56 for a SMPS comprises a chip set composed of a
 control unit chip 58 and a high voltage chip 60. The high voltage chip 60
 contains high voltage circuit elements, while all control circuits
 contained in the control unit chip 58 being not applied with high voltage.
 Provided in the control unit circuit 58, a pulse width modulation
 comparator 62 receives and compares two signals, i.e., a feedback signal
 FB and an oscillation signal OSCI from an oscillator 64, through its two
 input terminals respectively. As a result, an output oscillation signal
 COMP with a selected oscillation frequency and duty cycle is generated by
 the pulse width modulation comparator 62. The feedback signal FB is also
 connected to an over voltage and under voltage detection and feedback
 detection unit 66 whose output signal together with an output signal of a
 shutdown/auto restart unit 68, an output signal of the oscillator 64 and
 the output oscillation signal COMP from the pulse width modulation
 comparator 62 are inputted into an AND gate 70, from which a resultant
 control signal CTRL by logic decision is transmitted to a gate driver 72
 to control ON/OFF state of a switching transistor 74. In addition to the
 switching transistor 74, the high voltage chip 60 further contains a power
 start up unit 76 and a current detection and protection unit 78 connected
 to the control unit circuit 58. The switching transistor 74 has a source
 connected to a system reference voltage, i.e., ground, and a drain
 connected to an output terminal OUT of the chip set 56, which is connected
 to the end of the primary winding 20 of the transformer 18 as shown in
 FIG. 1. When the SMPS of the present invention is turned on, a start up
 voltage power is provided through the power start up unit 76 to the
 control unit 58 for the initiation of the control unit 58. On the other
 hand, the current detection and protection unit 78 monitors the drain
 current of the switching transistor 74 and produces an output signal
 I.sub.sns which is also inputted into the AND gate 70 in the control unit
 58 to be one of the decision factors of the control single CTRL such that
 a protection for the chip set 56 is further provided.
 FIG. 3 shows a circuit diagram of the high voltage chip 60, in which a
 power MOS transistor 74 serves as the switching transistor being turned
 on/off under the control of the control signal outputted from the control
 unit 58. The source of the transistor 74 is grounded and the drain thereof
 is connected to the output terminal OUT of the chip set, which will be
 connected to the primary winding of the transformer 18 as shown in FIG. 1.
 A junction FET 80 is used as the start up element for the control unit 58,
 and is connected between the drain of the transistor 74 and the control
 unit 58 in order to provide the start up voltage power for driving the
 control unit 58 to be initiated. The threshold voltage of the junction FET
 80 has a negative value, and the absolute value thereof is equal to the
 value of the power voltage for driving the control unit 58. When the power
 of the SMPS is turned on, a start up voltage is applied to the control
 unit 58 from the junction FET 80 to initiate the control unit 58, and then
 the junction FET 80 is turned off. Another power MOS transistor 82 serves
 as a current sense transistor to detect the drain current of the
 transistor 74, which has a drain connected to the drain of the transistor
 74, a gate connected to the gate of the transistor 74 and a source
 connected to the control unit 58. Moreover, a Zener diode 84 for over
 voltage protection of the control unit 58 is coupled to the power terminal
 of the control unit 58.
 The structure of the high voltage chip 60 is shown in FIG. 4, in which the
 junction FET is manufactured in a process compatible with that of MOS. In
 the chip 60, an N.sup.- drift layer 88 is epitaxially grown on an N.sup.+
 substrate 86, and then three P- wells 90, 92 and 94 are formed. P- base
 91, N.sup.+ region 96 and P.sup.+ region 98 are formed on the well 90. P-
 base 93, N.sup.+ region 100 and P.sup.+ region 102 are formed on the well
 92. P.sup.+ region 114 and N.sup.+ region 116 are formed on the well 94. A
 planar gate 104 is formed between the N.sup.+ regions 96 and 100 above the
 drift layer 88, and a dielectric layer 106 is formed between the gate 104
 and the drift layer 88. A surface layer of the P- base 91 and 93 between
 the N.sup.+ regions 96 and 100 below the dielectric layer 106 is a channel
 controlled by the gate 104. Therefore, the substrate 86, the drift layer
 88, the wells 90 and 92, the regions 96-102, the gate 104, and the
 dielectric layer 106 constitute the switching power MOS transistor 74
 mentioned above. A surface portion of the drift layer 88 between the wells
 92 and 94 is formed with N.sup.+ region 108, and insulation layers 110 and
 112 are formed on the drift layer 88 between the N.sup.+ region 108 and
 P.sup.+ regions 102 and 114, respectively. Therefore, the substrate 86,
 the drift layer 88, the wells 92 and 94, the P.sup.+ regions 102 and 104,
 and the N.sup.+ region 108 constitute the junction FET 80 mentioned above,
 in which the structure is also known as static induction transistor (SIT).
 In the transistor 80, as shown in the figure, the Zener diode 84 comprises
 the drift layer 88, the N.sup.+ region 108 and the P.sup.- wells 92 and
 94. A planar gate 118 is produced on a surface among the P- base 95, the
 N.sup.+ regions 116 and the drift layer 88, and a dielectric layer 120 is
 formed between the gate 118 and the P- base 95. A surface of the P- base
 below the gate 118 is a gate channel. Therefore, the substrate 86, the
 drift layer 88, the P.sup.+ region 114, the N.sup.+ region 116, the well
 94, the P- base 95, the gate 118 and the dielectric layer 120 constitute
 the current-sense transistor 82 mentioned above.
 While the present invention has been described in conjunction with
 preferred embodiments thereof, it is evident that many alternatives,
 modifications and variations will be apparent to those skilled in the art.
 Accordingly, it is intended to embrace all such alternatives,
 modifications and variations that fall within the spirit and scope thereof
 as set forth in the appended claims.