A sigma-delta modulator including at least first and second sub-modulators, each including an analog integration circuit, the analog integration circuit of the first sub-modulator having an output node connected to an input node of the analog integration circuit of the second sub-modulator, the modulator further comprising a coupling capacitor having a first electrode connected to an output node of the analog integration circuit of the second sub-modulator, and a comparator having its input coupled to the first electrode of the coupling capacitor by a first switch and to a second electrode of the coupling capacitor by a second switch.

This application claims the priority benefit of French patent application number 16/57232, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

BACKGROUND

The present disclosure relates to the field of analog-to-digital converters, and more particularly, of sigma-delta converters.

DISCUSSION OF THE RELATED ART

A sigma-delta converter conventionally comprises a sigma-delta modulator and a digital filter. The analog signal to be digitized is applied at the modulator input and is sampled by the latter at a relatively high frequency (relative to the maximum frequency of the input signal), called oversampling frequency. The modulator generates, at the oversampling frequency, binary samples representative of the analog input signal. The output bit train of the sigma-delta modulator is processed by the digital filter which extracts therefrom a digital value over N bits (N being the quantization resolution of the sigma-delta converter), representative of the input signal. The number of binary samples, that is, the number of oversampling periods, necessary to generate a digital output value over N bits is designated with acronym OSR, for “Over Sampling Ratio”.

The function of the sigma-delta modulator is to shape, on the one hand, the useful signal by means of its signal transfer function STF and, on the other hand, the quantization noise by means of its noise transfer function NTF. The STF is the transfer function linking the analog input signal to be digitized to the output signal of the modulator, and the NTF is the transfer function linking the quantization noise introduced by modulator to the output signal of the modulator. The NTF enables to reject the quantization noise out of the band of interest (containing the signal). The sigma-delta modulator thus forms a quantization noise shaping stage. The digital filter is designed to extract the signal from frequency bands where the attenuation of the quantization noise by the NTF is high (that is, where the signal is located). The signal transfer function, STF, is generally equal to 1, and the noise transfer function, NTF, is for example expressed, for a modulator of order p, as NTF(z=(1−z−1)P.

FIG. 1is a simplified electric diagram illustrating, in the form of blocks, an example of a sigma-delta modulator of order1.

The modulator ofFIG. 1comprises an input terminal A1intended to receive analog input signal Vin to be digitized, and an output terminal A2intended to supply a series of binary samples BS representative of signal Vin. The modulator ofFIG. 1comprises an analog integration circuit101, a 1-bit analog-to-digital converter103and a feedback loop comprising a 1-bit digital-to-analog converter105. Analog integration circuit101comprises a first input terminal connected to terminal A1of application of signal Vin, and an output terminal A3connected to the input of 1-bit analog-to-digital conversion circuit103, for example, a comparator. The output of I-bit analog-to-digital converter103is connected to output A2of the modulator, and is further coupled, via the feedback loop, to a second input terminal A4of analog integration circuit101. In this example, analog integration circuit101comprises a subtractor107having its positive input coupled to terminal A1of application of signal Vin and having its negative input coupled to output terminal A4of the feedback loop, and an analog integrator Ia1having its input connected to the output of subtractor107and having its output connected to input terminal A3of 1-bit analog-to-digital converter103.

For each cycle k of duration TOSRof a phase of conversion of analog input signal Vin into a digital output value, where TOSRdesignates the oversampling period of the converter, k is an integer in the range from 1 to OSR, and OSR is the number of successive cycles of the conversion phase, integration circuit101takes an analog sample Vin(k) of the input signal, and the modulator supplies, at the output of 1-bit analog-to-digital converter103, a binary sample BS(k) of the output signal. More particularly, in the shown example, for each cycle k, integrator Ia1of circuit101receives on its input a signal equal to the difference between input signal Vin(k) and feedback signal BS(k−1) (converted to the analog field by 1-bit digital-to-analog converter105). Output value Ia1(k) of integrator Ia1is accordingly updated, that is, incremented by value Vin(k)−BS(k−1), and then quantized by analog-to-digital converter103to provide output sample BS(k).

As a variation, analog integration circuit101may comprise a plurality of cascaded analog integrators. It may also comprise one or a plurality of subtractors, one or a plurality of summing circuits, and/or one or a plurality of weighting coefficients. Number p of analog integrators generally defines the order of the sigma-delta modulator. The higher order p of the modulator, the more number OSR of samples necessary to obtain a digital output value over N bits can be decreased (for identical quantization noise levels). On the other hand, sigma-delta modulators are all the more complex to form as their order is high (difficult stabilization).

The digital filter (not shown) of a sigma-delta converter conventionally comprises, according to the modulator structure, one or a plurality of digital integrators (generally at least as many as there are analog integrators in the modulator), for example, counters, and carries out a filtering function intended to extract the useful information from the bit train generated by the sigma-delta modulator.

The forming of sigma-delta modulators having an order greater than 1 is here more particularly considered.

SUMMARY

Thus, an embodiment provides a sigma-delta modulator comprising at least first and second sub-modulators, each comprising an analog integration circuit, the analog integration circuit of the first sub-modulator having an output node connected to an input node of the analog integration circuit of the second sub-modulator, the modulator further comprising a coupling capacitor having a first electrode connected to an output node of the analog integration circuit of the second sub-modulator, and a comparator having its input coupled to the first electrode of the coupling capacitor by a first switch and to a second electrode of the coupling capacitor by a second switch.

According to an embodiment, the modulator is capable of implementing a phase of conversion of an analog input signal into an output bit train, the conversion phase comprising a plurality of operating cycles, wherein, for each cycle of the conversion phase, during a first part of the cycle, the first and second switches are respectively off and on, and a binary value Y1is read from the comparator output and, during a second part of the cycle, the first and second switches are respectively on and off, and a binary value Y2is read from the comparator output, values Y1and Y2being then combined into an output bit of the modulator.

According to an embodiment, for each cycle of the conversion phase, the analog integration circuit of the second sub-modulator integrates a signal representative of the difference between binary value Y1and an output signal of the analog integration circuit of the first sub-modulator.

According to an embodiment, for each cycle of the conversion phase, a feedback signal representative of binary value Y2is subtracted from the signal integrated by the analog integration circuit of the second sub-modulator.

According to an embodiment, for each cycle of the conversion phase, the analog integration circuit of the first sub-modulator integrates a signal representative of the analog input signal.

According to an embodiment, for each cycle of the conversion phase, a feedback signal representative of the binary output value of the modulator is subtracted from the signal integrated by the analog integration circuit of the first sub-modulator.

According to an embodiment, the analog integration circuit of the first sub-modulator comprises at least two cascaded analog integrators, and at least one circuit achieving a weighted sum of the output values of said integrators, the output of the summing circuit forming the output of said analog integration circuit.

According to an embodiment, the analog integration circuit of the second sub-modulator comprises a single analog integrator having its input and its output respectively connected to the input and to the output of said analog integration circuit.

The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of dedicated embodiments in connection with the accompanying drawings.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the details of the forming of the digital filters of the described sigma-delta converters have not been shown, the forming of such filters being within the abilities of those skilled in the art on reading of the present description. In the present description, term “connected” is used to designate a direct electric connection, with no intermediate electronic component, for example, by means of one or a plurality of conductive tracks or conductive wires, and term “coupled” or term “linked” is used to designate an electric connection which may be direct (then meaning “connected”) or indirect (that is, via one or a plurality of intermediate components).

FIG. 2schematically illustrates in the form of blocks an example of a sigma-delta modulator of order4.

The sigma-delta modulator ofFIG. 2differs from the sigma-delta modulator ofFIG. 1essentially by the architecture of its analog integration circuit101. In the example ofFIG. 2, analog integration circuit101comprises a subtractor107, four cascaded analog integrators Ia1, Ia2, Ia3and Ia4, and a summing circuit109(Σ). Each analog integrator comprises an input and an output, and for example has a z−1/(1−z−1) transfer function, that is, for each cycle, the integrated signal, or output signal of the integrator, is incremented by the value of the signal applied at the integrator input. In this example, subtractor107receives, on its positive input, input signal Vin(k) weighted by a coefficient b1and, on its negative input, feedback signal BS(k−1) weighted by a coefficient a1. Integrator Ia1receives on its input the output signal of subtractor107, that is, a signal equal to difference b1*Vin(k)−a1*BS(k−1). Integrator Ia2receives on its input a signal equal to the output signal of integrator Ia1weighted by a coefficient c1. Integrator Ia3receives on its input a signal equal to the output signal of integrator Ia2weighted by a coefficient c2. Integrator Ia4receives on its input a signal equal to the output signal of integrator Ia3weighted by a coefficient c3. Summing circuit109adds input signal Vin(k) weighted by a coefficient b5and the output signals of integrators Ia1, Ia2, Ia3, and Ia4, respectively weighted by coefficients c7, c6, c4, and c4. The output of summing circuit109is connected to output terminal A3of circuit101.

In this example, it is considered that input signal Vin and output signal BS of the modulator are normalized, that is, value 0 of binary signal BS corresponds to a voltage level equal to the smallest value that analog signal Vin can take, and value 1 of signal BS corresponds to a voltage level equal to the greater value that signal Vin can take. Thus, the feedback loop of the modulator is a simple conductive track coupling terminal A2to terminal A4, and the feedback signal directly is signal BS. In the case where binary output signal BS is not at the same scale as input signal Vin, the feedback loop may comprise, as in the example ofFIG. 1, a 1-bit digital-to-analog converter having its input coupled to terminal A2and having its output coupled to terminal A4, the feedback signal then being the output signal of the 1-bit digital-to-analog converter.

Many alternative architectures of analog integration circuit101can be envisaged. Generally, analog integration circuit101of a sigma-delta modulator of order p greater than or equal to 1 may comprise p analog integrators Iaj, j being an integer in the range from 1 to p, each analog integrator Iajreceiving on its input a signal equal to the difference between input signal Vin(k) weighted by a coefficient bjand feedback signal BS(k−1) weighted by a coefficient aj, to which is added, if rank j of integrator Iajis greater than 1, the output signal of the integrator Iaj−1of previous rank weighted by a coefficient cj−1. Summing circuit Σ adds input signal Vin(k) weighted by a coefficient bp+1, the output signal of integrator Iapof rank p weighted by a coefficient cpand, if p is greater than 1, the output signal(s) of the integrators of rank p−1, 1 being an integer in the range from 1 to p−1, respectively weighted by coefficients cp+1. Some of the above-mentioned coefficients may be zero. For example, in the modulator of order4ofFIG. 2, coefficients b2, b3, b4, a2, a3and a4are zero, and, in the modulator of order1ofFIG. 1, coefficients b1, a1, and c1are unit coefficients, and coefficient b2is zero. Further, in the sub-modulator of order2MOD1ofFIG. 3(which will be described hereafter), coefficients b1, a1, and c2are unit coefficients, and coefficients a2, b2, and b3are zero, and, in the sub-modulator of order1MOD1ofFIG. 3(which will be described hereafter), coefficients b1, a1, and c1are unit coefficients and coefficient b2is zero.

In certain architectures of order p greater than or equal to 1, summing circuit Σ may further receive as an input feedback signal BS(k−1) weighted by a specific weighting coefficient.

Further, the analog integration circuit101of a sigma-delta modulator of order p greater than 1 may further comprise one or a plurality of analog feedbacks from the output of an analog integrator to the input of an upstream analog integrator, through a specific weighting coefficient.

Further, in an architecture of order p greater than 1, the output of an integrator of rank i may be added, through a specific weighting coefficient, to the input of a downstream integrator having a rank greater than or equal to i+2.

Further, delays may be introduced between the different stages of circuit101, and/or between circuit101and converter103.

A limitation of the above-mentioned architectures with a single noise shaping stage, that is, comprising a single feedback loop from the output of quantization stage103to the input of analog integration circuit101, is that the forming of a modulator of high order is in practice complex to implement. In particular, a problem which is posed is that the modulator may have an unstable behavior for certain levels of the input signal.

To overcome this disadvantage, MASH-type (“Multi Stage Noise Shaping”) sigma-delta modulators, that is, modulators of order p greater than 1 formed by the series connection of a plurality of sigma-delta sub-modulators having an order smaller than p, have been provided, where each sub-modulator may have a conventional single-stage noise shaping architecture of the above-described type, that is, comprising an analog integration circuit, a 1-bit analog-to-digital converter, and a feedback loop capable of comprising a digital-to-analog converter. The operating principle of MASH-type sigma-delta modulators is for example described in article “Sturdy MASH Δ-Σ modulator” of Maghari et al. (ELECTRONICS LETTERS 26 Oct. 2006 Vol. 42 No. 22). As an example, a MASH-type sigma-delta modulator of order2comprises a first sub-modulator of order1, or upstream sub-modulator, for example, of the type described in relation withFIG. 1, receiving the analog signal to be digitized on its analog input, and a second sub-modulator of order1, or downstream sub-modulator, for example, of the type described in relation withFIG. 1, receiving on its analog input a signal representative of the quantization error of the upstream sub-modulator. During a phase of conversion of the analog input signal into a digital value, each of the sub-modulators of order1supplies a train of OSR bits at the output of its 1-bit analog-to-digital converter, the two bit trains being recombined in a single train of OSR bits by a logic recombination circuit. The recombined bit train is digitally integrated by a digital filtering circuit generating a digital output value of the sigma-delta converter. More generally, MASH topologies can be applied whatever the orders of the series-coupled sub-modulators, and whatever the number of series-coupled sub-modulators. The sub-modulators are then coupled so that each sub-modulator of the series association of sub-modulators, except for the first sub-modulator, receives an input signal representative of the quantization error of the previous sub-modulator. An advantage of MASH-type sigma-delta modulators is that they enable to obtain high modulation orders, while doing away with the problems usually encountered (particularly, instability problems) in the forming of conventional sigma-delta modulators (with a single noise shaping stage).

FIG. 3schematically shows in the form of functional blocks an example of a MASH-type sigma-delta modulator.

In this example, the modulator is of MASH 2-1 type, that is, it comprises a first sigma-delta sub-modulator of order2MOD1, or upstream sub-modulator, followed by a second sigma-delta sub-modulator of order1MOD2, of downstream sub-modulator.

Sub-modulator MOD1has a conventional topology of order2with a single noise shaping stage. It comprises, as in the above-described examples, an analog integration circuit101having a first input A1intended to receive an analog input signal U to be converted, a 1-bit analog-to-digital converter103having its input coupled to an output A3of analog integration circuit101, and a feedback loop coupling output A2of analog-to-digital converter103to a second input A4of analog integration circuit101. In this example, analog integration circuit101comprises a subtractor107, two analog integrators Ia1and Ia2, and a summing circuit109. The positive input of subtractor107is coupled to input A1of circuit101, and the negative input of subtractor107is coupled to input A4of circuit101. The output of subtractor107is coupled to the input of analog integrator Ia1, and the output of analog integrator Ia1is coupled to the input of analog integrator Ia2via a weighting coefficient c1. Summing circuit109adds output signal O1of integrator Ia1weighted by a coefficient c3to output signal O2of integrator Ia2, and subtracts from this sum feedback signal Y applied to input A4of circuit101, weighted by a coefficient d. The output of summing circuit109forms the output (terminal A3) of analog integration circuit101of sub-modulator MOD1, and is coupled to the input of analog-to-digital converter103of sub-modulator MOD1. In the example ofFIG. 3, 1-bit analog-to-digital converter103of sub-modulator MOD1is shown in the form of a summing circuit adding to output signal S1(terminal A3) of analog integration circuit101of sub-modulator MOD1a quantization noise E1introduced by converter103. In this example, each analog integrator Iaicomprises a summing circuit301, and a delay operator303with a unit gain noted Z−1. A first input of summing circuit301is coupled to the input of the analog integrator, the output of summing circuit301being coupled to the input of operator303, and the output of operator303being coupled, on the one hand, to the output of the analog integrator and, on the other hand, to a second input of summing circuit301by a unit-gain positive feedback loop. At each operating cycle k of the sigma-delta converter, summing circuit301adds the signal received at cycle k at the input of integrator Iaiand a signal internal to integrator Iaicorresponding to the output signal of operator301, that is, to the output value of integrator Iaiat the previous cycle.

Sub-modulator MOD2has a conventional topology of order1of the type described in relation withFIG. 1. It comprises an analog integration circuit101comprising a first input A1receiving an analog signal equal to the difference between output signal Y1of analog-to-digital converter103of sub-modulator MOD1and output signal S1of analog integration circuit101of sub-modulator MOD1, that is, equal to the quantization error E1introduced by analog-to-digital converter103of sub-modulator MOD1. To achieve this, the sigma-delta modulator ofFIG. 3comprises, between sub-modulators MOD1and MOD2, a subtractor305having its positive input coupled to output A2of sub-modulator MOD1, having its negative input coupled to output A3of analog integration circuit101of sub-modulator MOD1, and having its output coupled to input A1of analog integration circuit101of sub-modulator MOD2. Sub-modulator MOD2further comprises a 1-bit analog-to-digital converter103having its input connected to an output terminal A3of its analog integration circuit101, and a feedback loop coupling output A2of its analog-to-digital converter103to a second input A4of its analog integration circuit101. In this example, analog integration circuit101of sub-modulator MOD2comprises a subtractor107and an analog integrator Ia1. The positive input of subtractor107is coupled to input A1of circuit101, and the negative input of subtractor107is coupled to input A4of circuit101. The output of subtractor107is coupled to the input of analog integrator Ia1. The output of analog integrator Ia1forms output A3of analog integration circuit101, and is coupled to the input of analog-to-digital converter103. Analog integrator Ia1of sub-modulator MOD2is for example identical or similar to integrator Ia1of sub-modulator MOD1. In the example ofFIG. 3, 1-bit analog-to-digital converter103of sub-modulator MOD2is shown in the form of a summing circuit adding to output signal (terminal A3) of analog integration circuit101of sub-modulator MOD2a quantization noise E2.

In the example ofFIG. 3, the sigma-delta modulator further comprises a unit-gain delay operator307, noted Z−1, and a subtractor309. The input of operator307is coupled to output A2of sub-modulator MOD1. The positive input of subtractor309is coupled to the output of operator307. The negative input of subtractor309is coupled to output A2of sub-modulator MOD2. In this example, the output of subtractor309forms the output of the sigma-delta modulator. The circuit formed by delay operator307and subtractor309recombines output bit trains Y1of sub-modulator MOD2and Y2of sub-modulator MOD2into an output bit train Y of the sigma-delta modulator, applied to the input of the digital filter (not shown) of the sigma-delta converter.

In the shown example, the feedback loop of sub-modulator MOD2is a direct feedback loop, that is, directly coupling (or possibly via a 1-bit digital-to-analog converter) output A2of sub-modulator MOD2to input A4of analog integration circuit101of sub-modulator MOD2. Conversely, the feedback loop of sub-modulator MOD1is an indirect feedback loop, comprising the recombination circuit formed by elements307and309. In other words, the feedback loop of sub-modulator MOD1does not directly couple output A2of sub-modulator MOD1to input A4of analog integration circuit101of sub-modulator MOD1, but it couples the output of the sigma-delta modulator (that is, the output of subtractor309supplying signal Y) to input A4of analog integration circuit101of sub-modulator MOD1(possibly via an analog-to-digital converter, not shown).

The following equations describe the response of the sigma-delta modulator ofFIG. 3:
Y2=z−1E1+(1−z−1)E2

FIG. 4is a detailed electric diagram of an embodiment of the sigma-delta modulator ofFIG. 3.

In the example ofFIG. 4, each of integrators Ia1, respectively Ia2, of sub-modulator MOD1comprises an operational amplifier AO having its input coupled to the output by an integration capacitor Ci1, respectively Ci2. The input and the output of the operational amplifier respectively form the input and the output of the integrator. Similarly, integrator Ia1of sub-modulator MOD2comprises an operational amplifier AO having its input coupled to its output by an integration capacitor Ci3. Each integrator further comprises, in parallel with its integration capacitor, a reset switch controlled by a signal Φr. In the present description, for simplification, the switches of the modulator are designated with the same reference numerals as their respective control signals. Thus, although the switches switching the different capacitors of the modulator are different, same designations are used for simultaneously controlled switches.

In this example, each of sub-modulators MOD1and MOD2comprises an analog integration circuit101and a 1-bit analog-to-digital converter103formed by a comparator having its input connected to an output terminal A3of analog integration circuit101of the sub-modulator, and having its output connected to an output terminal A2of the sub-modulator. In operation, an internal signal of each comparator switches from a high state to a low state according to whether the input signal of the comparator is higher or lower than a threshold, for example, equal to a reference potential applied to a reference node R of the circuit. The internal signal of the comparator is copied on its output terminal A2at each rising or falling edge of a control signal Φcomp.

In sub-modulator MOD1, the analog integration circuit101is formed as follows. The output of integrator Ia1is coupled to a first electrode of a capacitor C2by a first switch Φ1d, and the output of integrator Ia2is coupled to a first electrode of a capacitor C3by a first switch Φ2d. The second electrode of capacitor C2is coupled to the input of integrator Ia2by a first switch Φ2, and the second electrode of capacitor C3is coupled to output terminal A3of circuit101by a second switch Φ2. The first and second electrodes of capacitor C2are further coupled to a node R of application of a reference potential, respectively via a second switch Φ2dand via a first switch Φ1. Further, the first and second electrodes of capacitor C3are coupled to node R respectively via a second switch Φ1dand via a second switch Φ1. Analog integration circuit101of sub-modulator MOD1further comprises a capacitor C1having a first electrode coupled to input terminal A1of the sub-modulator by a third switch Φ1dand having its second electrode coupled to the input of integrator Ia1by a third switch Φ2. The first and second electrodes of capacitor C1are further respectively coupled to a node N1receiving output signal Y of the modulator by a third switch Φ2dand to node R by a third switch Φ1. Analog integration circuit101of sub-modulator MOD1further comprises a capacitor C4having a first electrode coupled to the output of integrator Ia1by a fourth switch Φ2dand having its second electrode coupled to output terminal A3of circuit101by a fourth switch Φ2. The first and second electrodes of capacitor C4are further coupled to node R respectively by a fourth switch Φ1dand by a fourth switch Φ1. Analog integration circuit101of sub-modulator MOD1further comprises a capacitor C5having a first electrode coupled to node N2receiving output signal Y2of sub-modulator MOD2via a fifth switch Φ2dand having a second electrode coupled to output terminal A3of circuit101by a fifth switch Φ2. The first and second electrodes of capacitor C5are further respectively coupled to a node N3receiving output signal Y1of sub-modulator MOD1via a fifth switch Φ1dand to node R via a fifth switch Φ1.

The circuit formed by capacitors C4, C3, and C5and by the switches Φ2d, Φ1d, Φ1, Φ2associated with these capacitors is duplicated at the input of the analog integrator Ia1of sub-modulator MOD2. In other words, in addition to its analog integrator Ia1, analog integration circuit101of sub-modulator MOD2comprises: a capacitor C3′ substantially identical to capacitor C3(to within manufacturing dispersions) having a first electrode coupled to the output of integrator Ia2of sub-modulator MOD1by a sixth switch Φ2dand having its second electrode coupled to the input of integrator Ia1of sub-modulator MOD2by a sixth switch Φ2, the first and second electrodes of capacitor C3′ being further coupled to node R respectively by a sixth switch Φ1dand by a sixth switch Φ1; a capacitor C4′ substantially identical to capacitor C4(to within manufacturing dispersions) having a first electrode coupled to the output of integrator Ia1of sub-modulator MOD1by a seventh switch Φ2dand having its second electrode coupled to the input of integrator Ia1of sub-modulator MOD2by a seventh switch Φ2, the first and second electrodes of capacitor C4′ being further coupled to node R respectively by a seventh switch Φ1dand by a seventh switch Φ1; and a capacitor C5′ substantially identical to capacitor C5(to within manufacturing dispersions) having a first electrode coupled to node N2by an eighth switch Φ2dand having its second electrode coupled to the input of integrator Ia1of sub-modulator MOD2by an eighth switch Φ2, the first and second electrodes of capacitor C5′ being further respectively coupled to node N3by an eighth switch Φ1dand to node R by an eighth switch Φ1.

Analog integration circuit101of sub-modulator MOD2further comprises a capacitor C6having a first electrode coupled to a node N4receiving a signalY1complementary to output signal Y1of sub-modulator MOD1via a ninth switch Φ1d(node N4is for example coupled to node N3by an inverter) and having its second electrode coupled to the input of integrator Ia1of sub-modulator MOD2by a ninth switch Φ1. The first and second electrodes of capacitor C6are further respectively coupled to a node N5receiving a signalY2complementary to output signal Y2of sub-modulator MOD2via a ninth switch Φ2d(node N5is for example coupled to node N2by an inverter) and to node R by a ninth switch Φ2.

In this example, the output of integrator Ia1of sub-modulator MOD2is connected to output terminal A3of analog integration circuit101of sub-modulator MOD2.

The sigma-delta modulator ofFIG. 4further comprises a logic circuit401(LOGIC) comprising two binary inputs respectively coupled to output terminal A2of 1-bit analog-to-digital converter103of sub-modulator MOD1and to output terminal A2of 1-bit analog-to-digital converter103of sub-modulator MOD2, and three binary outputs respectively coupled to nodes N1, N2, and N3and supplying binary output signal Y1of sub-modulator MOD1, binary output signal Y2of sub-modulator MOD2, and the binary output signal Y of the modulator.

A timing diagram is shown inFIG. 4to show the chaining in a cycle of two successive switching phases P1and P2of the modulator switches. During phase P1, switches Φ2and Φ2dare turned on (made conductive), switches Φ1and Φ1dbeing kept off (non-conductive). At the end of phase P1, switches Φ2and Φ2dare turned off. During phase P2, switches Φ1and Φ1dare turned on (made conductive), switches Φ2and Φ2dbeing kept off (non-conductive). At the end of phase P2, switches Φ1and Φ1dare turned off. At the end of each of phases P1and P2, the internal signal of comparators103of sub-modulators MOD1and MOD2is sampled (rising edges of signal Φcomp) to generate signals Y1and Y2.

In the embodiment ofFIG. 4, the function of summing circuit109ofFIG. 3is implemented on the one hand by capacitors C4, C3, and C5and the switches connected to these capacitors, and on the other hand by capacitors C4′, C3′, and C5′ and the switches connected to these capacitors.

At each cycle k of a phase of conversion of analog input signal U into a digital value, during phase P1, a signal S1resulting from the weighted sum of output signal O1of integrator Ia1, of output signal O2of integrator Ia2, and of output signal Y of the sigma-delta modulator, is generated on input node A3of analog-to-digital converter103of sub-modulator MOD1, with S1=−(O2+c3*O1−d*Y), coefficients c3and d being respectively set by the ratio of capacitances C3and C4and the ratio of capacitances C5and C3. It should be noted that in this example, signal Y(k)=Y1(k−1)−Y2(k) is not directly applied to the input of the summing circuit, but is generated again by the latter in capacitor C5, based on signals Y1and Y2. At the end of phase P1, signal S1is quantized by comparator103of sub-modulator MOD1to generate signal Y1. In parallel, during phase P1, signal S1is further generated on the input node of integrator Ia1of sub-modulator MOD2by the duplicated summing circuit comprising capacitors C4′, C3′, and C5′ and the switches connected to these capacitors. The value of signal S1thus adds to the output value of integrator Ia1of sub-modulator MOD2.

During phase P2following phase P1, signalY1is applied to the input of integrator Ia1of sub-modulator MOD2. Thus, at the end of the cycle, the output value of integrator Ia1of sub-modulator MOD2has effectively been increased by a value corresponding to quantization noise E1of analog-to-digital converter103of sub-modulator MOD1(from which feedback signal Y2of sub-modulator MOD2due to the precharging of capacitor C6to potential −Y2during phase P1is subtracted).

In the example ofFIG. 4, the function of subtractor circuit107of sub-modulator MOD1ofFIG. 3is implemented by capacitor C1and the switches associated with this capacitor, and the function of subtractor circuit107of sub-modulator MOD2ofFIG. 3is implemented by capacitor C6and the switches associated with this capacitor.

A disadvantage of the architecture ofFIG. 4is the hardware cost due to the duplicating, at the input of sub-modulator MOD2, of the capacitors of the summing circuit used in sub-modulator MOD1to generate output signal S1of analog integration circuit101of sub-modulator MOD1. Another disadvantage is due to the matching, which is inevitably imperfect, of the duplicated capacitors, which results in introducing an additional component of quantization noise E1in the expression of output signal Y of the modulator.

FIG. 5is a detailed electric diagram illustrating an embodiment of a multistage noise shaping sigma-delta modulator.

Functionally, the sigma-delta modulator ofFIG. 5is a MASH 2-I-type modulator identical or similar to the modulator ofFIG. 3.

Structurally, the sigma-delta modulator ofFIG. 5comprises elements common with the sigma-delta modulator ofFIG. 4. Only the differences between the two embodiments will be detailed hereafter.

Analog integration circuit101of sub-modulator MOD2ofFIG. 5differs from analog integration circuit101of sub-modulator MOD2ofFIG. 4essentially in that it comprises no replication of the output summing circuit of analog integration circuit101of sub-modulator MOD1. In other words, analog integration circuit101of sub-modulator MOD2ofFIG. 5differs from analog integration circuit101of sub-modulator MOD2ofFIG. 4essentially in that it does not comprise capacitors C4′, C3′ and C5′ and the switches associated with these capacitors.

In the example ofFIG. 5, the analog integration circuits101of sub-modulators MOD1and MOD2are directly series-coupled, that is, output terminal A3of analog integration circuit101of sub-modulator MOD1is connected to input terminal A1of analog integration circuit101of sub-modulator MOD2(corresponding to the input node of integrator Ia1of sub-modulator MOD2).

In the embodiment ofFIG. 5, the sigma-delta modulator comprises a single 1-bit analog-to-digital converter103, for example, a comparator identical or similar to comparators103of sub-modulators MOD1and MOD2ofFIG. 4, shared by sub-modulators MOD1and MOD2. The input of converter103is coupled to the output of analog integration circuit101of sub-modulator MOD2. More particularly, in the shown example, the sigma-delta modulator comprises a capacitor Cc having a first electrode connected to output node A3of analog integration circuit101of sub-modulator MOD2(corresponding to the output node of integrator Ia1of sub-modulator MOD2), and having its second electrode coupled to the input of analog-to-digital converter103by a switch Φ2d. The first electrode of capacitor Cc is further coupled to the input of converter103by a switch Φ1d. Further, the second electrode of capacitor Cc is coupled to node R by a switch Φ1.

The sigma-delta modulator ofFIG. 5further comprises a logic circuit501(LOGIC) comprising a binary input coupled to the output terminal of 1-bit analog-to-digital converter103, and three binary outputs respectively coupled to nodes N1, N2, and N3and supplying binary output signal Y1of sub-modulator MOD1, binary output signal Y2of sub-modulator MOD2, and binary output signal Y of the modulator.

A timing diagram is shown inFIG. 5to show the chaining in a cycle of two successive switching phases P1and P2of the modulator switches. As in the example ofFIG. 4, during phase P1, switches Φ2and Φ2dare turned on, switches Φ1and Φ1dbeing kept off (non-conductive). At the end of phase P1, switches Φ2and Φ2dare turned off. During phase P2, switches Φ1and Φ1dare turned on (made conductive), switches Φ2and Φ2dbeing kept off (non-conductive). At the end of phase P2, switches Φ1and Φ1dare turned off. At the end of each of phases P1and P2, the internal signal of comparator103is sampled (rising edges of signal Φcomp) to generate signals Y1and Y2.

In the implementation ofFIG. 5, the function of summing circuit109ofFIG. 3is implemented by capacitors C4, C3, and C5and the switches connected to these capacitors. At each cycle k of a phase of conversion of analog input signal U into a digital value, during phase P1, a signal S1resulting from the weighted sum of output signal O1of integrator Ia1of sub-modulator MOD1, of output signal O2of integrator Ia2of sub-modulator MOD1, and of output signal Y of the sigma-delta modulator is generated on output node A3of analog integration circuit101of sub-modulator MOD1, with S1=−(O2+c3*O1−d*Y). Signal S1is applied to input node A1of analog integration circuit101of the downstream sub-modulator MOD2, that is, in the shown example, to the input of integrator Ia1of sub-modulator MOD2. Signal S1is thus integrated by integrator Ia1of sub-modulator MOD2, that is, during phase P1, the value of integrator Ia1is incremented by value S1. Prior thereto, during phase P2of the previous cycle during which switches Φ1are conductive, capacitor Cc is charged to the output value of integrator Ia1. Thus, during the next phase P1(Φ1off), output coupling capacitor Cc introduces at the input of comparator103a voltage shift with respect to the current output value of integrator Ia1equal to the output value of integrator Ia1at the end of the previous cycle. In other words, during phase P1, the voltage variation observed at the input of comparator103due to coupling capacitor Cc corresponds to quantity S1. At the end of phase P1, the value S1observed on the second electrode of capacitor Cc is quantized by comparator103to generate signal Y1.

During phase P2following phase P1, signalY1is applied to the input of integrator Ia1of sub-modulator MOD2(node N4). Thus, during phase P2, the output value of integrator Ia1of sub-modulator MOD2is incremented by a value corresponding to the quantization noise E1introduced by analog-to-digital converter103during the quantization of signal S1, from which feedback Y2is subtracted (node N5). At the end of phase P2, the output signal of integrator Ia1of sub-modulator MOD2is directly quantized by comparator103(without passing through coupling capacitor Cc) to obtain signal Y2.

Thus, functionally, the circuit ofFIG. 5behaves substantially in the same way as the circuit ofFIG. 3. However, in the implementation ofFIG. 5, rather than duplicating the circuit for generating signal S1at the input of sub-modulator MOD2as in the implementation ofFIG. 4, it is provided to reconstruct signal S1by diverting the output signal of integrator Ia1of downstream modulator MOD2through coupling capacitor Cc.

An advantage of the embodiment ofFIG. 5is that signal S1is not duplicated, which, in addition to the advantage in terms of hardware cost due to the suppressing of capacitors C4′, C3′, C5′ and of their switches, enables, during the generation of quantization error signal E1=Y1−S1, to avoid risks of lack of integrity of signal S1due to a mismatch of the duplicated capacitors.

Another advantage of the implementation ofFIG. 5is that it enables to spare a 1-bit analog-to-digital converter with respect to the implementation ofFIG. 4.

Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the described embodiments are not limited to the example of MASH 2-I-type sigma-delta modulator architecture described in relation withFIGS. 3 and 5. More generally, the provided solution, implementing an analog circuit for diverting the output signal of an analog integration circuit101of a downstream sub-modulator to reconstruct an output signal of an analog integration circuit101of an upstream sub-modulator may be used in any type of sigma-delta modulator, comprising at least two cascaded sub-modulators.