High-bandwidth magnetoresistive random access memory devices and methods of operation thereof

A method for accessing a memory cell of a magnetoresistive random access memory (MRAM) device, where the memory cell includes a plurality of memory units, includes writing the memory cell by identifying ones of the memory units having stored therein a datum different from a datum to be written thereto; and simultaneously writing all of the ones of the memory units. An MRAM device includes a plurality of write word lines, a plurality of write bit lines, and a plurality of memory cells. Each memory cell includes a plurality of memory units. Each memory unit includes a free magnetic region having one or more easy axes non-perpendicular to the write bit lines and non-perpendicular to the write word lines, a pinned magnetic region, and a tunneling barrier between the free magnetic region and the pinned magnetic region.

DESCRIPTION OF THE INVENTION

1. Field of the Invention

This invention relates in general to high-bandwidth magnetoresistive random access memory (MRAM) devices and methods for operating the same.

MRAM devices have been proposed as an alternative to conventional memory devices such as static random access memories (SRAM), dynamic random access memories (DRAM), and flash memories. MRAM devices store data using a magnetoresistance effect, which refers to a phenomenon wherein electrical resistance of a material changes with magnetic fields to which the material is subjected. As compared to these conventional memories, MRAM devices excel in speed, integration density, power consumption, radiation hardness, and endurance.

FIG. 1shows an exemplary MRAM device100including an array of memory cells. Only one of the memory cells, memory cell102, is shown. MRAM device100includes a plurality of write bit lines104and a plurality of write word lines106. Write bit lines104and write word lines106are substantially perpendicular to each other. Each memory cell corresponds to one write bit line104and one write word line106.

Memory cell102includes a pinned magnetic region108, a free magnetic region110, and a tunneling barrier112sandwiched between pinned magnetic region108and free magnetic region110. Tunneling barrier112may comprise, for example, aluminum oxide (Al2O3) or magnesium oxide (MgO).

Free magnetic region110may comprise a single free magnetic layer or an SAF structure.FIG. 1shows that free magnetic region110includes two ferromagnetic layers120and122sandwiching an anti-ferromagnetic coupling spacer layer124. Ferromagnetic layers120and122may comprise, for example, cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or nickel-iron (NiFe). Anti-ferromagnetic coupling spacer layer124may comprise, for example, ruthenium (Ru) or copper (Cu). A thickness of anti-ferromagnetic coupling spacer layer124is selected such that ferromagnetic layers120and122are anti-ferromagnetically coupled to each other. If the magnetic moments of ferromagnetic layers120and122are significantly different, then the SAF structure may be equivalent to a single free magnetic layer.

An anti-ferromagnetic pinning layer126, a buffer layer128, a bottom electrode130, and a dielectric layer132are sequentially provided between pinned magnetic region108and write word line106. Anti-ferromagnetic pinning layer126may comprise, for example, platinum manganese (PtMn) or manganese iridium (MnIr). Buffer layer128may comprise, for example, nickel-iron (NiFe), nickel-iron-chromium (NiFeCr), or nickel-iron-cobalt (NiFeCo). A top electrode134is provided on free magnetic region110and a dielectric layer136is provided between top electrode134and write bit line104.

Anti-ferromagnetic pinning layer126pins a magnetic moment of pinned magnetic region108, such that the magnetic moment of pinned magnetic region108does not rotate when a moderate magnetic field is applied. In contrast, a magnetic moment of free magnetic region110is free to rotate under an external magnetic field. Pinned magnetic region108has an easy axis along the direction of write word line106, and free magnetic region110has two easy axes anti-parallel to each other and also along the direction of write word line106. Easy axis as known in the art and used herein refers to an intrinsic orientation of magnetic dipole moments of an anisotropic material in the absence of an external magnetic or biasing field.

An electron tunneling barrier of tunneling barrier112and, therefore, a resistance of memory cell102, change with magnetic fields. For example, when the respective magnetic moment vectors of ferromagnetic layers116and120are parallel to each other, tunneling barrier112has a low electron tunneling barrier and memory cell102has a low resistance. When the respective magnetic moment vectors of ferromagnetic layers116and120are anti-parallel to each other, tunneling barrier112has a high electron tunneling barrier and memory cell102has a high resistance. Thus, memory cell102may store one bit of “1” or “0” defined by the value of the resistance thereof. For example, a high resistance of memory cell102may represent a bit of “1” and a low resistance of memory cell102may represent a bit of “0”, or the converse.

A bit of datum may be written into memory cell102by adjusting magnetic moment vectors of ferromagnetic layers120and122(so-called “spin flop”) to rotate the magnetic moment vectors of ferromagnetic layers120and122, such that the magnetic moment vector of ferromagnetic layer120is parallel or anti-parallel to the magnetic moment vector of ferromagnetic layer116. In particular, appropriate currents may be provided to write bit line104and write word line106to induce external magnetic fields, which change the magnetic moments of ferromagnetic layers120and122. A digit current IDthrough write bit line104induces a circular digit magnetic field HD, and a word current IWthrough write word line106induces a circular word magnetic field HW. The strength of magnetic fields HDand HWare respectively proportional to digit current IDand word current IW. It is assumed that write bit line104is above memory cell102and write word line106is below memory cell102. Thus, when digit current IDflows from left to right, HDis substantially in the direction from outside the paper into the paper in the plane of memory cell102, as indicated inFIG. 1. Conversely, when digit current IDflows from right to left, HDis substantially in the direction from inside the paper coming out of the paper in the plane of memory cell102. Similarly, when word current IWflows into the paper from outside the paper, HWis substantially in the direction from left to right in the plane of memory cell102, as indicated inFIG. 1. To write a bit of datum to memory cell102, a word current IWthrough write word line106is first provided to generate a word magnetic field HWin a direction perpendicular to the easy axes of free magnetic region110in the plane of memory cell102. As a result, the magnetic moment vector of ferromagnetic layer120is aligned in a direction approximately perpendicular to the easy axes of free magnetic region110. Then, a digit current IDthrough write bit line104is provided to generate a digit magnetic field HDin a direction of one of the easy axes of free magnetic region110. As a result, the magnetic moment of ferromagnetic layer120is aligned with the one of the easy axes of free magnetic region110. If digit magnetic field HDis in a direction parallel to the easy axis of pinned magnetic region108, a bit of “0” is written into memory cell102. If digit magnetic field HDis in a direction anti-parallel to the easy axis of pinned magnetic region108, a bit of “1” is written into memory cell102.

Memory cell102may be read by sensing the resistance thereof. MRAM device100includes a plurality of read word lines (not shown) and a plurality of read bit lines. Each memory cell corresponds to one read word line and one read bit line and includes a transistor coupled the corresponding read word line. MRAM device100also includes a plurality of sense amplifiers each coupled to one of the read bit lines to sense a current therethrough. AsFIG. 1shows, a transistor138is coupled to bottom electrode130of memory cell102, and a sense amplifier140is coupled to top electrode134of memory cell102. The corresponding read word line is coupled to the gate of transistor138. The corresponding read bit line is coupled to top electrode134. To read the datum stored in memory cell102, the corresponding read word line and read bit line are activated to select memory cell102. Transistor138is thus turned on, a voltage is applied between top electrode134and bottom electrode130, and a current through memory cell102is sensed by sense amplifier140. AsFIG. 1shows, sense amplifier140is also coupled to sense a reference current through a reference cell (not shown). Sense amplifier140compares the current through memory cell102with the reference current to determine a state of memory cell102.

In one aspect, top electrode134of memory cell102may be electrically connected to corresponding write bit line104through a metal plug (not shown) formed in dielectric layer136. Thus, one bit line serves as both the write bit line and the read bit line.

U.S. Pat. No. 6,757,189 to Hung et al. discloses a high-density MRAM device, in which each memory cell of the high-density MRAM device includes multiple magnetic memory units for storing multiple data bits.FIG. 2shows a high-density MRAM device200as disclosed in Hung et al.

AsFIG. 2shows, MRAM device200includes a plurality of memory cells202, of which2021,2022,2023,2024are shown. Each memory cell202corresponds to a bit line BL, a read word line RWL, and two write word lines WWL. Each memory cell202includes two memory units1021and1022connected in parallel. For example, memory cell2021includes two memory units1021and1022, and a transistor138. Each of memory units1021and1022has the same structure as memory cell102inFIG. 1. Each bit line BL acts as both a write bit line and a read bit line. Memory units1021and1022are connected in parallel between the drain of transistor138and the corresponding bit line BL. The source of transistor138is grounded. The gate of transistor138is connected to the corresponding read word line RWL. InFIG. 2, memory units1021of memory cells2021and2022correspond to a first write word line WWL1; memory units1022of memory cells2021and2022correspond to a second write word line WWL2; memory units1021of memory cells2023and2024correspond to a first write word line WWL3; memory units1022of memory cells2023and2024correspond to a second write word line WWL4. In addition, memory cells2021and2022correspond to a first read word line RWL1; memory cells2023and2024correspond to a second read word line RWL2; memory cells2021and2023correspond to a first bit line BL1; and memory cells2022and2024correspond to a second bit line BL2. Each of bit lines BL1and BL2is also coupled to sense amplifier140through a transistor204. Because each memory cell202includes two memory units1021and1022, MRAM200has a high density of data storage.

MRAM200is manufactured such that R1max//R2max, R1max//R2min, R1min//R2max, R1min//R2minall have different values, wherein R1maxis the high resistance of memory unit1021, R1minis the low resistance of memory unit1021, R2maxis the high resistance of memory unit1022, R2minis the low resistance of memory unit1022, and R1//R2represents two resistances R1and R2connected in parallel. One of memory cells202to be read is first selected by enabling the corresponding read word line RWL, and sense amplifier140detects the current through the corresponding bit line BL. Sense amplifier140compares the detected current with three intermediate reference currents, Ref1, Ref2, Ref3, where Ref1, Ref2, Ref3respectively correspond to three reference resistance values, R1, R2, R3, between R1max//R2max, R1max//R2min, R1min//R2max, and R1min//R2min. Assume, for example, R1max//R2max>R1>R1max//R2min>R2>R1min//R2max>R3>R1min//R2min. Thus, if the detected current is between Ref1and Ref2, then the resistance of the selected memory cell2021is R1max//R2min. Consequently, memory unit1021of the selected memory cell202has a bit of “1” stored therein, and memory unit1022of the selected memory cell202has a bit of “0” stored therein.

FIG. 3Ashows a clock signal CLK and a sequence of signals on first read word line RWL1and first bit line BL1for reading memory cell2021. On a rising edge of clock signal CLK, an enabling signal, e.g., a positive voltage, is provided on first read word line RWL1, and an enabling signal is provided to turn on transistor204coupled to first bit line BL1. Thus, transistor138of memory cell2021and transistor204coupled to first bit line BL1are turned on, and a voltage drop is applied across memory units1021and1022of memory cell2021. Sense amplifier140detects the current through first bit line BL1, i.e., the current through memory units1021and1022of memory cell2021and compares the detected current with the three reference values, Ref1, Ref2, Ref3. Based on the result of the comparison, sense amplifier outputs two bits of data, D0and D1, simultaneously. InFIG. 3A, the shaded areas of D0and D1are time periods during which data are transmitted, and the clear areas of D0and D1are time periods during which no data are transmitted or previous data are latched. Thus, each memory cell202is capable of outputting two bits of data during one clock cycle, and a bandwidth for reading MRAM device200, or a read bandwidth of MRAM device200, is doubled.

However, according to Hung et al., only one bit of datum may be written into each memory cell202in one clock cycle, and writing two bits of data into each memory cell202takes two clock cycles. As an example,FIG. 3Bshows a sequence of signals on write word lines WWL1and WWL2and first bit line BL1for writing data into memory cell2021. Particularly, a bit of datum is written into memory unit1021of memory cell2021in a first clock cycle, by first providing a current through first write word line WWL1and then providing a current in an appropriate direction through first bit line BL1. In a second clock cycle, a bit of datum is written into memory unit1022of memory cell2021by first providing a current through second write word line WWL2, and then providing a current in an appropriate direction through first bit line BL1. Because the current through first bit line BL1defines states of both memory unit1021and memory unit1022, the two bits of data must be separately written into memory units1021and1022. Similarly, inFIG. 3B, the shaded areas of BL1are time periods during which data are transmitted, and the clear areas of BL1are time periods during which no data are transmitted.

Therefore, although the read bandwidth of MRAM device200is doubled by including two memory units connected in parallel in each memory cell202, a bandwidth for writing MRAM device200, i.e., a write bandwidth of MRAM device200, is limited, because two clock cycles are required for writing each two-bit memory cell202.

SUMMARY OF THE INVENTION

Consistent with embodiments of the present invention, there is provided a method for accessing a memory cell of a magnetoresistive random access memory (MRAM) device. The memory cell includes a plurality of memory units each for storing a bit of datum. The method includes writing the memory cell, where writing the memory cell includes identifying ones of the memory units, each of the ones of the memory units having stored therein a datum different from a datum to be written thereto; and simultaneously writing all of the ones of the memory units.

Consistent with embodiments of the present invention, there is also provided a method for accessing a memory cell of a magnetoresistive random access memory device, where the memory cell comprising a plurality of memory units each for storing a bit of datum. The method includes writing the memory cell by reading data stored in the memory units; identifying first ones of the memory units and second ones of the memory units, wherein each of the first ones of the memory units has stored therein a datum different from a datum to be written thereto and each of the second ones of the memory units has stored therein a datum the same as a datum to be written thereto; subjecting the first and second ones of the memory units to a first magnetic field in a first direction between a first time point and a second time point; subjecting the first ones of the memory units to a second magnetic field in a second direction between a third time point and a fourth time point, the first and second directions being substantially perpendicular to each other; and subjecting the second ones of the memory units to a third magnetic field in the second direction between the third time point and a fifth time point, wherein the first and second magnetic fields change a state of each of the first ones of the memory units, and the first and third magnetic fields maintain a state of each of the second ones of the memory units.

Consistent with embodiments of the present invention, there is also provided a method for operating a magnetoresistive random access memory (MRAM) device. The MRAM device includes a plurality of memory cells, each memory cell including a plurality of memory units. The method includes selecting first ones of the memory cells; and writing the first ones of the memory cells. Writing the first ones of the memory cells further includes reading data stored in the memory units of the first ones of the memory cells, identifying first ones of the memory units of the first ones of the memory cells and second ones of the memory units of the first ones of the memory cells, wherein each of the first ones of the memory units has stored therein a datum different from a datum to be written thereto and each of the second ones of the memory units has stored therein a datum the same as a datum to be written thereto, and simultaneously writing the first ones of the memory units.

Consistent with embodiments of the present invention, a magnetoresistive random access memory device includes a plurality of read bit lines; a plurality of write bit lines; a plurality of read word lines; a plurality of write word lines substantially perpendicular to the write bit lines; and a plurality of memory cells. Each memory cell corresponds to one of the read bit lines, one of the read word lines, one of the write word lines, and several of the write bit lines. Each memory cell includes a plurality of memory units each corresponding to one of the corresponding several write bit lines. Each memory unit includes a free magnetic region having one or more easy axes non-perpendicular to the write bit lines and non-perpendicular to the write word lines, a pinned magnetic region, and a tunneling barrier between the free magnetic region and the pinned magnetic region.

Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be apparent from that description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

DESCRIPTION OF THE EMBODIMENTS

Consistent with embodiments of the present invention, there are provided high-bandwidth MRAM devices having not only a high read bandwidth but also a high write bandwidth, and methods for operating the high-bandwidth MRAM devices.

FIG. 4Ashows an MRAM device400consistent with a first embodiment of the present invention. MRAM device400includes an array of memory cells402, four of which,4021,4022,4023,4024are shown. Each memory cell402corresponds to a read bit line RBL, a read word line RWL, a write word line WWL, and several, particularly two inFIG. 4A, write bit lines WBL. Each memory cell402includes two memory units404as memory units4041and4042, connected in parallel between a transistor406and the corresponding read bit line RBL, where a gate of transistor406is connected to the corresponding read word line RWL. Each memory unit404corresponds to one of the write bit lines WBL. AsFIG. 4Ashows, memory cells4021and4022correspond to a first read bit line RBL0; memory units4041of memory cells4021and4022correspond to a first write bit line WBL0; and memory units4042of memory cells4021and4022correspond to a second write bit line WBL1. Memory cells4023and4024correspond to a second read bit line RBL1; memory units4041of memory cells4023and4024correspond to a third write bit line WBL2; and memory units4042of memory cells4023and4024correspond to a fourth write bit line WBL3. Memory cells4021and4023correspond to a first read word line RWL0and a first write word line WWL0; and memory cells4022and4024correspond to a second read word line RWL1and a second write word line WWL1. A sense amplifier408is coupled to each read bit line RBL through a select transistor410to detect a current through a selected memory cell402.

FIG. 4Bshows a cross-sectional view of one memory unit404. Memory unit404is formed between the corresponding write word line WWL and the corresponding write bit line WBL. It is assumed that write bit line WBL is above memory unit404, write word line WWL is below memory unit404, and write bit line WBL and write word line WWL are approximately perpendicular to each other. However, it is to be understood that the terms “above” and “below” are relative terms depending on an angle at which one views memory unit404. Memory unit404includes a pinned magnetic region420, a free magnetic region422, and a tunneling barrier424sandwiched between pinned magnetic region420and free magnetic region422. Tunneling barrier424may comprise, for example, aluminum oxide (AlOx) or magnesium oxide (MgO).

Free magnetic region422may comprise an SAF including two ferromagnetic layers432and434sandwiching an anti-ferromagnetic coupling spacer layer436. Ferromagnetic layers432and434may comprise, for example, cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or nickel-iron (NiFe). Anti-ferromagnetic coupling spacer layer436may comprise, for example, ruthenium (Ru) or copper (Cu). A thickness of anti-ferromagnetic coupling spacer layer436is selected such that ferromagnetic layers432and434are anti-ferromagnetically coupled to each other. AlthoughFIG. 4Bonly shows free magnetic region422to include three layers, a single free magnetic layer or a multi-layered SAF structure having more than three layers can also be used. For example, free magnetic region422may comprise three or more ferromagnetic layers separated by coupling spacer layers.

An anti-ferromagnetic pinning layer438, a buffer layer440, a bottom electrode442, and a dielectric layer444are sequentially provided between pinned magnetic region420and write word line WWL. Anti-ferromagnetic pinning layer438may comprise, for example, platinum manganese (PtMn) or manganese iridium (MnIr). Buffer layer440may comprise, for example, nickel-iron (NiFe), nickel-iron-chromium (NiFeCr) or nickel-iron-cobalt (NiFeCo). A top electrode446is provided on free magnetic region422and a dielectric layer448is provided between top electrode446and the corresponding write bit line WBL.

Anti-ferromagnetic pinning layer438pins a magnetic moment of pinned magnetic region420, such that the magnetic moment of pinned magnetic region420does not rotate when a moderate magnetic field is applied. In contrast, a magnetic moment of free magnetic region422is free to rotate under an external magnetic field.

Consistent with the first embodiment of the present invention, pinned magnetic region420has an easy axis EP, and free magnetic region422has a positive easy axis E+and a negative easy axis E−, where all of EP, E+, and E−are at an angle of about 45° with the corresponding write word line and write bit line, and E+and E−are anti-parallel with each other.FIG. 4Cis a plan view illustrating magnetic moments in memory unit404with respect to the directions of the corresponding write bit line WBL and write word line WWL when memory unit404is viewed from the top. InFIG. 4C, an x-axis is along the direction of the corresponding write bit line WBL and a y-axis is along the direction of the corresponding write word line WWL. The positive x-axis is in the direction along write bit line WBL shown inFIG. 4Bfrom left to right, and the positive y-axis is in the direction along write word line WWL shown inFIG. 4Bfrom outside the paper into the plane of the paper. In the absence of external magnetic fields, magnetic moment vectors of ferromagnetic layers426,428,432, and434align with one of the easy axes. InFIG. 4C, a magnetic moment vector A of ferromagnetic layer428is aligned with easy axis EP, a magnetic moment vector B of ferromagnetic layer426is anti-parallel with magnetic moment vector A, a magnetic moment vector C of ferromagnetic layer432is aligned with negative easy axis E−, and a magnetic moment vector D of ferromagnetic layer434is aligned with positive easy axis E+. The arrowed lines labeled as magnetic moment vectors A-D inFIGS. 4B and 4Cand in others figures herein only indicate the approximate directions of these magnetic moment vectors, and do not indicate the relative strengths thereof.

An electron tunneling barrier of tunneling barrier424and, therefore, a resistance of memory unit404, change with magnetic fields. For example, when magnetic moment vector A of ferromagnetic layer428and magnetic moment vector C of ferromagnetic layer432are parallel to each other, tunneling barrier424has a low electron tunneling barrier and memory unit404has a low resistance. When magnetic moment vector A of ferromagnetic layer428and magnetic moment vector C of ferromagnetic layer432are anti-parallel to each other, tunneling barrier424has a high electron tunneling barrier and memory unit404has a high resistance. Thus, memory unit404may store one bit of “1” or “0” defined by the value of the resistance thereof. For example, a high resistance of memory unit404may represent a bit of “1” and a low resistance of memory unit404may represent a bit of “0”, or the converse.

Consistent with the first embodiment of the present invention, MRAM device400is manufactured such that a resistance of each of memory cells402has a different value corresponding to a different state of the corresponding memory cell402. For example, memory cell4021has four possible states: 1) “00”, when memory unit4041has stored therein a bit of “0”, and memory unit4042has stored therein a bit of “0”; 2) “01”, when memory unit4041has stored therein a bit of “0”, and memory unit4042has stored therein a bit of “1”; 3) “10”, when memory unit4041has stored therein a bit of “1”, and memory unit4042has stored therein a bit of “0”; and 4) “11”, when memory unit4041has stored therein a bit of “1”, and memory unit4042has stored therein a bit of “1”. Then memory cell4021also has four possible resistance values respectively corresponding to the four possible states thereof. In other words, R1max//R2max, R1max//R2min, R1min//R2max, R1min//R2minall have different values, wherein R1maxis the high resistance of each memory unit4041, R1minis the low resistance of each memory unit4041, R2maxis the high resistance of each memory unit4042, R2minis the low resistance of each memory unit4042. Consequently, two bits of data may be read from a selected memory cell402in one clock cycle by determining the resistance of the selected memory cell402. Consider memory cell4021as an example.FIG. 5shows a clock signal CLK and a sequence of signals on read word line RWL0and read bit line RBL0for reading memory cell4021. On a rising edge of clock signal CLK, an enabling signal, e.g., a positive voltage, is provided on read word line RWL0, thereby turning on transistors406coupled to read word line RWL0, and an enabling signal (not shown) is provided to turn on select transistor410coupled to read bit line RBL0to activate read bit line RBL0. A voltage drop between read bit line RBL0and transistor406is therefore applied across memory units4041and4042of memory cell4021, and sense amplifier408detects a current through read bit line RBL0, i.e., the current through memory units4041and4042of memory cell4021. Sense amplifier408compares the detected current with three intermediate reference current values Ref1, Ref2, Ref3, which correspond to reference resistance values, R1, R2, R3, between R1max//R2max, R1max//R2min, R1min//R2max, R1min//R2min. Assume, for example, R1max//R2max>R1>R1max//R2min>R2>R1min//R2max>R3>R1min//R2min. Thus, if the detected current is between Ref1and Ref2, then the resistance of memory cell4021is R1max//R2min. Consequently, memory unit4041of memory cell4021has a bit of “1” stored therein, and memory unit4042of memory cell4021has a bit of “0” stored therein. Thus, two bits of data may be read out each memory cell402during one clock cycle. InFIG. 5and subsequent drawing figures showing sequence of signals, shaded areas indicate time periods during which data are transmitted, clear areas indicate time periods during which no data are transmitted or previous data are latched, and different types of shadings indicate separate bits of data that may or may not be different from one another.

MRAM device400consistent with the first embodiment of the present invention also has a high write bandwidth. Particularly, two bits of data may be written into a selected memory cell402during one clock cycle. Consistent with a second embodiment of the present invention, a so-called toggle writing method is applied to write two bits of data into a selected memory cell402of MRAM device400. According to the toggle writing method, a bit of datum to be written into a memory unit is first compared with the datum stored in the memory unit. If the datum to be written is the same as the datum stored in the memory unit, no writing operation is performed. Otherwise, the state of the memory unit is changed, or “toggled”. If necessary, both memory units4041and4042of a selected memory cell402may be toggled at the same time. The second embodiment is described with reference toFIGS. 6 and 7(a)-7(e). It is assumed that memory cell4021is selected for the writing operation.

To toggle write one of memory units404, write currents are provided to the corresponding write word line WWL and write bit line WBL to induce external magnetic fields, thereby changing the magnetic moment of ferromagnetic layer432thereof.FIGS. 4B and 4Cshow the relationship between currents provided to write bit line WBL and write word line WWL and the external magnetic fields induced thereby. A word current IWthrough write word line WWL induces a circular word magnetic field HW, and a digit current IDthrough write bit line WBL induces a circular digit magnetic field HD. The strength of magnetic fields HWand HDare respectively proportional to word current IWand digit current ID. Also, as shown inFIG. 4B, when word current IWis positive, i.e., in the positive y-axis direction, HWis substantially in the positive x-axis direction in the plane of memory unit404; when digit current IDis positive, i.e., in the positive x-axis direction, HDis substantially in the positive y-axis direction in the plane of memory unit404.

FIG. 6shows a sequence of signals on write word line WWL0, write bit line WBL0, and write bit line WBL1, provided by a peripheral circuit (not shown), hereinafter referred to as the writing circuit, for writing data into memory cell4021. AsFIG. 6shows, clock signal CLK rises at time t0. Between time t0and time t1, a logic circuit (not shown) reads memory cell4021, compares the data in memory cell4021with the data to be written into memory cell4021, and determines if one or both of memory units4041and4042should be toggled. It is assumed that memory unit4041has stored therein a bit of datum the same as the bit of datum to be written thereto, and that memory unit4042has stored therein a bit of datum different from the bit of datum to be written thereto. Therefore, memory unit4042should be toggled, while memory unit4041should not.

Then, the writing circuit sequentially provides a digit current and a word current to toggle memory unit4042. Particularly, at time t2, a positive digit current IDis provided through write bit line WBL1; at time t3, a positive word current IWis provided through write word line WWL0; at time t4, IDis turned off; and at time t5, IWis turned off. Clock signal CLK falls at time t6. Through the time period of to t6, no current is provided through write bit line WBL0.

As a result of the word current and bit current provided as shown inFIG. 6, memory unit4042is toggled, and the state of memory unit4041remains unchanged.FIGS. 7(a)-7(e) illustrate the process by which IDand IWshown inFIG. 6toggle write memory unit4042-Magnetic moment vectors C and D in the following descriptions ofFIGS. 7(a)-7(e) refer to magnetic moment vectors C and D of memory unit4042.

FIG. 7(a) shows magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434at times t0and t1, when no word current or digit current is provided. Magnetic moment vector C is in the direction of negative easy axis E−of free magnetic region422and magnetic moment vector D is in the direction of positive easy axis E+of free magnetic region422.

FIG. 7(b) shows magnetic moment vectors C and D at time t2, when IDis provided, inducing a digit magnetic field HDsubstantially in the positive y-axis direction. Under digit magnetic field HD, magnetic moment vectors C and D rotate clockwise. Magnetic moment vector C is in a direction between the negative x-axis and the positive y-axis. Magnetic moment vector D is in a direction between the positive x-axis and positive easy axis E+of free magnetic region422.

FIG. 7(c) shows magnetic moment vectors C and D at time t3, when IWis provided, inducing a word magnetic field HWsubstantially in the positive x-axis direction. As a result, magnetic moment vectors C and D further rotate clockwise. Magnetic moment vector C approaches the positive y-axis, and magnetic moment vector D may pass the positive x-axis.

FIG. 7(d) shows magnetic moment vectors C and D at time t4, when IDis turned off. As a result, magnetic moment vectors C and D further rotate clockwise. Magnetic moment vector C may pass the positive y-axis and approaches positive easy axis E+of free magnetic region422. Magnetic moment vector D approaches the negative x-axis.

FIG. 7(e) shows magnetic moment vectors C and D at time t5, when IWis also turned off. Because magnetic moment vector C is closer to positive easy axis E+than negative easy axis E−of free magnetic region422, magnetic moment vector C further rotates clockwise and aligns with positive easy axis E+of free magnetic region422. Because magnetic moment vector D is closer to negative easy axis E−than positive easy axis E+of free magnetic region422, magnetic moment vector D further rotates clockwise and aligns with negative easy axis E−of free magnetic region422.

Thus, after the sequence of IDand IWshown inFIG. 6, magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434have switched positions. Particularly, magnetic moment vector C of ferromagnetic layer432has rotated 180°. Thus, if memory unit4042previously had a bit of “0” stored therein, then the sequence of IDand IWshown inFIG. 6has written a bit of “1” into memory unit4042; if memory unit4042previously had a bit of “1” stored therein, then the sequence of IDand IWshown inFIG. 6has written a bit of “0” into memory unit4042.

Similarly, when both memory units4041and4042need to be toggled, digit currents are provided through write bit lines WBL of both memory units4041and4042simultaneously to write the memory units4041and4042at the same time.FIG. 8shows a sequence of signals on write word line WWL0, write bit line WBL0, and write bit line WBL1, for toggle writing both memory unit4041and memory unit4042. The process of toggle writing both memory units4041and4042should now be apparent to one of ordinary skill in the art and is therefore not described in detail herein.

Thus, consistent with embodiments of the present invention, two bits of data may be read from or written into a selected memory cell402of MRAM device400within one clock cycle. In other words, MRAM device400not only has a high read bandwidth but also has a high write bandwidth.

InFIG. 6, a digit current IDis only provided to memory unit4042, which is to be toggled. However, consistent with the second embodiment of the present invention, a digit current may also be provided to a memory unit404not to be toggled.FIG. 9shows a sequence of signals on write word line WWL0, write bit line WBL0, and write bit line WBL1, for toggle writing only memory unit4042. Particularly, at time t2, a positive digit current ID0and a positive digit current ID1are respectively provided through write bit lines WBL0and WBL1; at time t3, a positive word current IWis provided through write word line WWL0; at time t4, ID1is turned off; at time t5, IWis turned off; and at time t6, ID0is also turned off. Clock signal CLK falls at time t7.

As compared to the sequence of signals shown inFIG. 6, when the sequence of signals shown inFIG. 9are applied, memory unit4042is subjected to the same signals and will be toggled. However, memory unit4041is subjected to a different signal sequence and will not toggle.FIGS. 10(a)-10(e) illustrate the state of memory unit4041through the signal sequence shown inFIG. 9. Magnetic moment vectors C and D in the following descriptions ofFIGS. 10(a)-10(e) refer to magnetic moment vectors C and D of memory unit4041.

FIG. 10(a) shows magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434at times t0and t1, when no word current or digit current is provided. Magnetic moment vector C is in the direction of negative easy axis E−of free magnetic region422and magnetic moment vector D is in the direction of positive easy axis E+of free magnetic region422.

FIG. 10(b) shows magnetic moment vectors C and D at time t2, when ID0is provided, inducing a digit magnetic field HD0substantially in the positive y-axis direction. Under digit magnetic field HD0, magnetic moment vectors C and D rotate clockwise. Magnetic moment vector C is in a direction between the negative x-axis and the positive y-axis. Magnetic moment vector D is in a direction between the positive x-axis ad the positive easy axis E+of free magnetic region422.

FIG. 10(c) shows magnetic moment vectors C and D at time t3, when IWis provided, inducing a word magnetic field HWsubstantially in the positive x-axis direction. As a result, magnetic moment vectors C and D further rotate clockwise. Magnetic moment vector C approaches the positive y-axis, and magnetic moment vector D may pass the positive x-axis.

FIG. 10(d) shows magnetic moment vectors C and D at time t4, when IWis turned off. As a result, magnetic moment vectors C and D rotate counterclockwise and return to the same positions as shown inFIG. 10(b).

FIG. 10(e) shows magnetic moment vectors C and D at time t5, when ID0is also turned off. Magnetic moment vectors C and D further rotate counterclockwise and return to the same positions as shown inFIG. 10(a).

Thus, after the sequence of ID0and IWshown inFIG. 9, magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434of memory unit4041remain at the same positions, and a state of memory unit4041has not changed.

Consistent with embodiments of the present invention, magnetic moment vector A of ferromagnetic layer428and magnetic moment vector B of ferromagnetic layer426may be adjusted to generate a fringe (or stray) magnetic field as a bias magnetic field HBIASin free magnetic region422, such that only weak magnetic fields HWand HDare required to toggle write memory unit404.FIG. 11shows the requisite magnetic fields HWand HDfor toggle writing memory unit404when there is no bias magnetic field HBIASand the requisite magnetic fields H′Wand H′Dfor toggle writing memory unit404when there is bias magnetic field HBIASin the direction of positive easy axis E+of free magnetic region422. When weaker magnetic fields HWand HDare required for writing memory unit404, lower word current IWand lower digit current IDmay be applied. Thus, a bias magnetic field HBIASresults in a reduced power consumption.

Consistent with a third embodiment of the present invention, there is provided a method for operating MRAM device400when memory units404of MRAM device400are subjected to a bias magnetic field. The same sequence of signals as illustrated inFIG. 5may be applied to read MRAM device400. However, to write MRAM device400, a sequence of writing currents with two bidirectional current pulses, i.e., current pulses with both a negative part and a positive part, are applied to toggle write memory cells402when memory cells402are under a bias magnetic field. For example,FIG. 12shows a sequence of signals on write word line WWL0, write bit line WBL0, and write bit line WBL1, for writing data into memory cell4021, when memory units4041and4042of memory cell4021are under a bias magnetic field HBIASin the direction of positive easy axis E+of free magnetic region422. AsFIG. 12shows, clock signal CLK rises at time t0. Between time t0and time t1, the logic circuit (not shown) reads memory cell4021, compares the data in memory cell4021with the data to be written into memory cell4021, and determines if one or both of memory units4041and4042should be toggled. It is assumed that the bit of datum to be written into memory unit4041is the same as the bit of datum stored in memory unit4041, and that the bit of datum to be written into memory unit4042is different from the bit of datum stored in memory unit4042. Therefore, memory unit4042is toggled, while memory unit4041is not.

Then, at time t2, a negative word current IW1is provided through write word line WWL0; at time t3, a positive digit current ID1is provided through write bit line WBL1; at time t4, IW1is turned off, and a positive word current IW2is provided through write word line WWL0; at time t5, ID1is turned off, and a negative digit current ID2is provided through write bit line WBL1; at time t6, IW2is turned off; and at time t7, ID2is also turned off. Clock signal CLK falls at time t8. Through the time period of t0to t8, no current is provided through write bit line WBL0.

FIGS. 13(a)-13(g) illustrate the process by which IW1, ID1, IW2, and ID2shown inFIG. 12toggle write memory unit4042. Magnetic moment vectors C and D in the following descriptions ofFIGS. 13(a)-13(g) refer to magnetic moment vectors C and D of memory unit4042.

FIG. 13(a) shows magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434at times t0and t1, when no word current or digit current is provided. Because of HBIAS, magnetic moment vectors C and D, may rotate counterclockwise and respectively approach or pass the negative and positive y-axis.

AsFIG. 13(b) shows, at time t2, negative word current IW1is provided, generating a word magnetic field HW1substantially in the negative x-axis direction, i.e., at an angle of 135° with HBIAS. In other words, HW1partially offsets HBIAS. As a result, magnetic moment vectors C and D respectively approach easy axes E−and E+.

FIG. 13(c) shows magnetic moment vectors C and D at time t3, when ID1is provided, inducing a digit magnetic field HD1substantially in the positive y-axis direction. As a result, magnetic moment vectors C and D rotate clockwise. Magnetic moment vector C may pass the negative x-axis, and magnetic moment vector D approaches the positive x-axis.

FIG. 13(d) shows magnetic moment vectors C and D at time t4, when IW1is turned off and IW2is turned on, inducing a word magnetic field HW2substantially in the positive x-axis direction. As a result, magnetic moment vectors C and D further rotate clockwise. Magnetic moment vector C approaches the positive y-axis and magnetic moment vector D may pass the positive x-axis.

FIG. 13(e) shows magnetic moment vectors C and D at time t5, when ID1is turned off and ID2is turned on, inducing a digit magnetic field HD2in the negative y-axis. Magnetic moment vectors C and D further rotate clockwise. Magnetic moment vector C may pass the positive y-axis, and magnetic moment vector D approaches the negative y-axis.

FIG. 13(f) shows magnetic moment vectors C and D at time t6, when IW2is turned off. Magnetic moment vectors C and D further rotate clockwise. Now magnetic moment vector C approaches positive easy axis E+and magnetic moment vector D may pass the negative y-axis and approaches negative easy axis E−.

FIG. 13(g) shows magnetic moment vectors C and D at time t7, when ID2is turned off. Because magnetic moment vector C is closer to positive easy axis E+direction and magnetic moment vector D is closer to negative easy axis E−direction prior to time t7, magnetic moment vector C settles in a position close to positive easy axis E+direction and magnetic moment vector D settles in a position close to negative easy axis E−direction.

Thus, after the sequence of the word current and digit current shown inFIG. 12, magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434have changed positions. Particularly, magnetic moment vector C of ferromagnetic layer432has rotated from a position close to negative easy axis E−to a position close to positive easy axis E+. Thus, if memory unit4042previously had a bit of “0” stored therein, then the sequence of the word current and digit current shown inFIG. 12has written a bit of “1” into memory unit4042; if memory unit4042previously had a bit of “1” stored therein, then the sequence of the word current and digit current shown inFIG. 12has written a bit of “0” into memory unit4042.

Similarly, when both memory units4041and4042need to be toggled, digit currents are simultaneously provided through write bit lines WBL of both memory units4041and4042to write the memory units4041and4042at the same time.FIG. 14shows a sequence of signals on write word line WWL0, write bit line WBL0, and write bit line WBL1, for toggle writing both memory unit4041and memory unit4042. The process of toggle writing both memory units4041and4042should now be apparent to one of ordinary skill in the art and is therefore not described in detail herein.

InFIG. 12, digit currents ID1and ID2are only provided to memory unit4042, which is to be toggled. However, consistent with the third embodiment of the present invention, a digit current may also be provided to a memory unit404not to be toggled.FIG. 15shows a sequence of signals on write word line WWL0, write bit line WBL0, and write bit line WBL1, for toggle writing only memory unit4042. Particularly, at time t2, a negative word current IW1is provided through write word line WWL0; at time t3, a positive digit current ID0and a positive digit current ID1are respectively provided through write bit line WBL0and write bit line WBL1; at time t4, IW1is turned off, and a positive word current IW2is provided through write word line WWL0; at time t5, ID1is turned off, and a negative digit current ID2is provided through write bit line WBL1; at time t6, IW2is turned off; and at time t7, ID0and ID2are both also turned off. Clock signal CLK falls at time t8.

As compared to the sequence of signals shown inFIG. 13, when the sequence of signals shown inFIG. 15are applied, memory unit4042is subjected to the same signals and will toggle. However, memory unit4041is subjected to a different signal sequence and will not toggle.FIGS. 16(a)-16(e) illustrate the state of memory unit4041through the signal sequence shown inFIG. 15. Magnetic moment vectors C and D in the following descriptions ofFIGS. 16(a)-16(e) refer to magnetic moment vectors C and D of memory unit4041.

FIG. 16(a) shows magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434at times t0and t1, when no word current or digit current is provided. Because of HBIAS, magnetic moment vectors C and D, may rotate counterclockwise and respectively approach or pass the negative and positive x-axis.

AsFIG. 16(b) shows, at time t2, negative word current IW1is provided, generating a word magnetic field HW1substantially in the negative x-axis direction, i.e., at an angle of 135° with HBIAS. In other words, HW1partially offsets HBIAS. As a result, magnetic moment vectors C and D rotate clockwise and respectively approach or pass easy axes E−and E+.

FIG. 16(c) shows magnetic moment vectors C and D at time t3, when ID0is provided, inducing a digit magnetic field HD0substantially in the positive y-axis direction. As a result, magnetic moment vectors C and D rotate clockwise. Magnetic moment vector C may pass the negative x-axis, and magnetic moment vector D approaches the positive x-axis.

FIG. 16(d) shows magnetic moment vectors C and D at time t4, when IW1is turned off and IW2is turned on, inducing a word magnetic field HW2in the positive x-axis direction. As a result, magnetic moment vectors C and D further rotate clockwise. Magnetic moment vector C approaches the positive y-axis and magnetic moment vector D may pass the positive x-axis.

FIG. 16(e) shows magnetic moment vectors C and D at time t6, when IW2is turned off. Magnetic moment vectors C and D rotate counterclockwise. Magnetic moment vector C rotates back towards the negative x-axis and magnetic moment vector D rotates back towards and may pass the positive x-axis. As a result, magnetic moment vector C is closer to negative easy axis E−and magnetic moment vector D is closer to positive easy axis E+.

At time t7, ID0is turned off. Because magnetic moment vector C is closer to the negative easy axis E−direction and magnetic moment vector D is closer to the positive easy axis E+direction prior to time t7, magnetic moment vectors C and D return to their respective original positions as shown inFIG. 16(a).

Thus, after the sequence of IW1, ID0, and IW2as shown inFIG. 15, magnetic moment vector C of ferromagnetic layer432and magnetic moment vector D of ferromagnetic layer434of memory unit4041remain at the same positions and memory unit4041has not changed state.

Consistent with embodiments of the present invention, more than one of memory cells402may be selected at the same time. For example, more than one of memory cells402may be read by activating one read word line RWL and multiple read bit lines RBL; more than one of memory cells402may be written by activating one write word line WWL and multiple write bit lines WBL. To read the selected memory cells402, appropriate signals such as those shown inFIG. 5are simultaneously applied to all of the selected memory cells402. To write the selected memory cells402, appropriate signals, such as those shown inFIGS. 6,8,9,12,14, or15, are simultaneously applied to all of the selected memory cells402. Because two bits of data may be read from or written into each memory cell402in one clock cycle, the number of bits of data read from or written into memory cells402of MRAM device400within each clock cycle is twice the number of memory cells402simultaneously selected. Therefore, the methods of operating MRAM device400consistent with embodiments of the present invention provide not only a high read bandwidth but also a high write bandwidth of MRAM400.

Consistent with embodiments of the present invention, MRAM400also includes an appropriate interface for making the high read and write bandwidths available to external devices accessing MRAM400.

A memory device communicates with external devices through a data bus including a number of data lines and control signal lines. The number of data lines in the data bus is equal to a number of bits of data that the memory device may simultaneously provide or receive, which is also referred to as a word size. Because each memory cell of conventional memory devices stores only one bit of datum, the word size of the conventional memory devices is equal to the number of memory cells that may be simultaneously selected. For example, if a memory device has 8 memory cells simultaneously selected, the memory device is connected to a data bus including 8 data lines for sending and receiving 8 bits of data in parallel.

However, as discussed above, MRAM device400consistent with embodiments of the present invention has a high read bandwidth and a high write bandwidth. In one aspect, MRAM device400is connectable to a data bus including a number of data lines equal to twice the number of memory cells402simultaneously selected when MRAM400is being accessed. For example, if 8 memory cells402are selected at the same time, a data bus including 16 data lines is connected to MRAM device400for simultaneously transferring 16 bits of data. Therefore, the word size of MRAM device400is twice that of a conventional MRAM device having 8 memory cells simultaneously selected.

In another aspect, MRAM device400is connectable to a data bus including a number of data lines as many as a number of memory cells402simultaneously selected when MRAM400is being accessed. For example, if 8 memory cells402are selected at the same time, then the data bus includes only 8 lines. However, MRAM device400includes an I/O circuit for transferring two bits of data per clock cycle through each of the data lines. Particularly, the I/O circuit has an input portion and an output portion. The input portion receives in series two bits of data to be written into a selected memory cell402through one of the data lines and parallelizes the two bits for simultaneous transfer to the writing circuit, which then writes the two bits simultaneously into the selected memory cell402. The output portion receives two bits of data in parallel from sense amplifier408and queues the two bits for serial transfer onto one of the data lines within one clock cycle. For example, one bit may be transferred during the first half of a clock cycle and the other bit may be transferred during the second half of the clock cycle. Therefore, although the word size of MRAM400is the same as that of a conventional MRAM device having 8 memory cells simultaneously selected, the number of bits transferred through each data line within the same period of time, i.e., the per-line data transfer rate, is doubled.

The I/O circuit may comprise any suitable logic circuit.FIG. 17shows as an example an output portion450of an I/O circuit in MRAM device400for queuing data consistent with embodiments of the present invention. Output portion450includes two shift registers452and454and a multiplexer456. Shift registers452and454respectively receive data outputs D0and D1from sense amplifier408and respectively output the same data on a rising edge of a clock signal (CL). Particularly, referring toFIG. 17, when the CL signal of shift register452rises from “0” to “1”, an output of shift register452, Q0, is set to be D0; when the CL signal of shift register454rises from “0” to “1”, an output of shift register454, Q1, is set to be D1. The clock signal CLK is provided to shift register452as the CL signal thereof. An inverted clock signalCLK, which is the clock signal CLK inverted by an inverter458, is provided to shift register454as the CL signal thereof. Multiplexer456receives Q0and Q1as input, and outputs one of Q0and Q1in accordance with a select (SL) signal. For example, when SL is “1”, the output of multiplexer456, DOUT, is Q0; when SL is “0”, Q1is output as DOUT. The clock signal CLK is provided to multiplexer456as the SL signal thereof.

FIG. 18illustrates two exemplary clock cycles, a first cycle and a second cycle, of the process of queuing two bits of data by output portion450of the I/O circuit shown inFIG. 17. Consider the first cycle as an example. Shift register452shifts D0out as the output Q0when the clock signal CLK rises at the beginning of the first cycle. Thus, throughout the first cycle, Q0is the same as D0. Shift register454shifts D1out as the output Q1when the inverted clock signalCLKrises at the center point of the first cycle. Thus, Q1is the same as D1through the second half of the first cycle. Because the clock signal CLK, which is the SL signal of multiplexer456, is “1” during the first half of the first cycle and is “0” during the second half of the first cycle, Q0is output as DOUT during the first half of the first cycle, and Q1is output as DOUT during the second half of the first cycle. Thus, two bits of data, D0and D1, are output in series within one clock cycle. The same process is repeated in the second cycle and subsequent clock cycles.

As persons of ordinary skill will now appreciate, the input portion of the I/O circuit of MRAM400may be similarly constructed to enable parallelization of two bits of data serially transferred within one clock cycle. Therefore, such a construction is not shown in the drawing figures or described herein.

By queuing two bits of data for serial transmission in one clock cycle and rearranging two bits of data received within one clock cycle for parallel transmission, the I/O circuit of MRAM device400consistent with embodiments of the present invention enables a per-line data transfer rate that is twice the per-line data rate of a conventional MRAM device.

By either increasing the word size or increasing the per-line data transfer rate, the high read and write bandwidths of MRAM device400consistent with embodiments of the present invention may be fully utilized.

FIG. 4Ashows each memory cell402of MRAM device400to include two memory units404. However, consistent with embodiments of the present invention, each memory cell of an MRAM device may include more than two memory units.FIG. 19shows an MRAM device500consistent with a fourth embodiment of the present invention. MRAM device500includes an array of memory cells502, four of which,5021,5022,5023,5024are shown. Each memory cell502corresponds to a read bit line RBL, a read word line RWL, a write word line WWL, and three write bit lines WBL.FIG. 19shows that each memory cell502includes three memory units504, i.e., memory units5041,5042, and5043, connected in parallel between a transistor506and the corresponding read bit line RBL, where a gate of transistor506is connected to the corresponding read word line RWL. Each memory unit504corresponds to one of the three write bit lines WBL. AsFIG. 19shows, memory cells5021and5022correspond to a first read bit line RBL0, a first write bit line WBL0, a second write bit line WBL1, and a third write bit line WBL2; memory cells5023and5024correspond to a second read bit line RBL1, a fourth write bit line WBL3, a fifth write bit line WBL4, and a sixth write bit line WBL5; memory cells5021and5023correspond to a first read word line RWL0and a first write word line WWL0; and memory cells5022and5024correspond to a second read word line RWL1and a second write word line WWL1. A sense amplifier508is coupled to each read bit line RBL through a select transistor510to detect a current through a selected one of memory cells502.

Consistent with the fourth embodiment of the present invention, memory units5041,5042, and5043in each memory cell502of MRAM device500are fabricated such that a resistance of each of memory cells502has a different value corresponding to a different state of the corresponding memory cell502. In other words, eight parallel resistances, R1max//R2max//R3max, R1max//R2max//R3min, R1max//R2min//R3max, R1max//R2min//R3min, R1min//R2max//R3max, R1min//R2max//R3min, R1min//R2min//R3max, R1min//R2min//R3min, all have different values, where R1maxis the high resistance of memory unit5041, R1minis the low resistance of memory unit5041, R2maxis the high resistance of memory unit5042, R2minis the low resistance of memory unit5042, R3maxis the high resistance of memory unit5043, and R3minis the low resistance of memory unit5043. Therefore, three bits of data may be stored in each memory cell502and may be read out simultaneously. Particularly, sense amplifier508compares the detected current through the selected memory cell502with seven intermediate reference current values Ref1˜Ref7, which correspond to reference resistance values between the eight parallel resistances, and finds the one of the eight parallel resistances that is the closest to the resistance of the selected memory cell502. Once the corresponding parallel resistance is found, the states of memory units504of the selected memory cell502are determined and three bits of data D0, D1, and D2are output simultaneously.

To write a selected memory cell502, a logic circuit (not shown) first reads the data stored in memory units504of the selected memory cell502and compares the same with the data to be written into memory units504. If a memory unit504has stored therein a bit of datum the same as the datum to be written thereto, no writing operation is performed. Otherwise, the state of the memory unit is changed, or “toggled”. If more than one of memory units504of a selected memory cell502need to be toggled, writing currents may be simultaneously provided to the corresponding write word line and the write bit lines corresponding to the memory units to be toggled.

The processes of reading and writing a selected memory cell502should now be apparent to one skilled in the art and are not described in detail herein.

MRAM device500may be connectable to a data bus including a number of data lines three times a number of memory cells502simultaneously selected when MRAM500is being accessed. For example, if 8 memory cells502are selected at the same time, a data bus including 24 data lines may be connected to MRAM device500for receiving and sending 24 bits of data in parallel. Therefore, the word size of MRAM device500is three times that of a conventional MRAM device having 8 memory cells simultaneously selected.

Alternatively, MRAM device500may be connectable to a data bus including a number of data lines equal to a number of memory cells502simultaneously selected when MRAM500is being accessed. For example, if 8 memory cells502are selected at the same time, then the data bus includes only 8 data lines. However, MRAM device500further includes an I/O circuit for transferring three bits of data per clock cycle through each of the data lines. For example, the I/O circuit may have an output portion for queuing three bits of data read from a selected memory cell502, such that a first bit is transferred during the first quarter of a clock cycle, a second bit is transferred during the second quarter of a clock cycle, and a third bit is transferred during the third quarter of a clock cycle. The I/O circuit may also include an input portion for parallelizing three bits of data to be written into a selected memory cell502such that the three bits are transferred in parallel to the writing circuit for simultaneous writing into memory units504of the selected memory cell502. Thus, although the word size of MRAM500does not change, the per-line data transfer rate is tripled.

The I/O circuit consistent with the fourth embodiment of the present invention may comprise any suitable logic circuit for the purpose. For example,FIG. 20shows an exemplary output portion550of the I/O circuit of MRAM device500consistent with the fourth embodiment of the present invention. AsFIG. 20shows, output portion550includes three shift registers552,554, and556, and a multiplexer558. Shift registers552,554, and556respectively receive data outputs D0, D1, and D2from sense amplifier508, and respectively output the same data as Q0, Q1, and Q2on a rising edge of a clock signal (CL). Two external clock signals, CLK1and CLK2, are provided to generate clock signals for shift registers552,554, and556, where the frequency of CLK2is twice the frequency of CLK1. Particularly, the clock signal of shift register552is AND(CLK1, CLK2), the clock signal of shift register554is AND(CLK1,CLK2), and the clock signal of shift register556is AND(CLK1, CLK2), whereCLK1andCLK2are CLK1and CLK2respectively inverted by inverters560and562. Thus, when AND(CLK1, CLK2) rises, shift register552shifts D0out as Q0; when AND(CLK1,CLK2) rises, shift register554shifts D1out as Q1; and when AND(CLK1, CLK2) rises, shift register556shifts D2out as Q2.

FIG. 21illustrates two clock cycles, a first cycle and a second cycle, of the process of queuing D0, D1, D2, by output portion550. The process of queuing the three bits of data should now be understood by one skilled in the art and is therefore not described in detail herein.

The input portion of the I/O circuit of MRAM500may be similarly constructed and is also not shown in the drawing figures or described herein.

Thus, consistent with the fourth embodiment of the present invention, an MRAM device with three memory units in each memory cell thereof is capable of transferring a number of bits of data per clock cycle three times a number of memory cells that may be simultaneously selected, either with a tripled word size or with a tripled per-line data transfer rate.

Similarly, consistent with embodiments of the present invention, an MRAM device may have four or more memory units in each memory cell thereof to increase a bandwidth thereof, and may communicate with external devices through a data bus with an increased word size or an increased per-line data transfer rate.

The above descriptions of embodiments of the present invention assumed for convenience that the word currents or digit currents are provided in a manner such that moment vectors C and D rotate in a certain direction. However, it is to be understood that moment vectors C and D may rotate in both clockwise and counterclockwise directions. For example, in contrast to the sequence of signals shown inFIG. 6, and also consistent with the second embodiment of the present invention, to toggle write memory unit4042of memory cell4021, a positive word current IWmay be provided through write word line WWL0between time t2and time t4, and a positive digit current IDmay be provided through write bit line WBL1between time t3and time t5. As a result, moment vectors C and D will rotate counterclockwise, in contrast to the clockwise rotation shown inFIGS. 7(a)-7(e). For another example, in contrast to the sequence of signals shown inFIG. 12, and also consistent with the third embodiment of the present invention, to write memory unit4042of memory cell4021, a negative digit current may be provided between time t2and time t4, a positive digit current may be provided between time t4and time t6, a positive word current may be provided between time t3and time t5, and a negative word current may be provided between time t5and time t7. As a result, moment vectors C and D will rotate counterclockwise, in contrast to the clockwise rotation shown inFIGS. 13(a)-13(g).

In the above descriptions, it was assumed that the easy axes E+and E−are at an angle of about 45° with the x-axis and y-axis. However, it is to be understood that the easy axes do not have to be at a particular angle with the x-axis and y-axis, but rather may be at any angle with the x-axis or y-axis. Methods for writing memory units404or504may be modified accordingly. For example, consistent with the second embodiment of the present invention, when the easy axes of the free magnetic region are at random angles with the read word line and digit line, two sequential current pulses may be provided to write a memory unit404, where each of the two pulses is a combination of both a word current and a digit current, rather than a word current or a digit current alone. For another example, consistent with the third embodiment of the present invention, when the easy axes of the free magnetic region are at random angles with the read word line and digit line, four sequential current pulses may be provided to write a memory unit, where each of the four pulses is a combination of both a word current and a digit current.