Memory mapping management method for nonvolatile main memory system

A memory mapping management method for a system using nonvolatile memory (NVM) as main memory, including receiving a request to cancel a memory mapping, determining whether the memory mapping is a mapping of a file based on meta data relating to the memory mapping, separately storing the meta data when the memory mapping is the mapping of the file, and cancelling the memory mapping when the memory mapping is not the mapping of the file may be provided. Further, the memory mapping management method may include receiving a memory mapping request, searching for a memory mapping for a file in a memory mapping storage space when a requested memory mapping is a mapping of the file, and reusing a searched memory mapping found during the search when a region of the searched memory mapping includes a region required by the requested memory mapping in a virtual address space.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2015-0171500 filed on Dec. 3, 2015, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Example embodiments of the inventive concepts relate to memory mapping management methods for a nonvolatile main memory system, and more particularly, to memory mapping management methods for a nonvolatile main memory system which reuses a memory mapping generated during file input/output.

Research has been conducted to use nonvolatile memory as main memory of a computer system. As one example of such research, file input/output using a memory mapping has been introduced. File input/output using a memory mapping provides relatively high performance as compared to a general file input/output. In other words, file input/output using memory mapping enables a large file to be processed at a higher speed, uses relatively simple program codes, and facilitates maintenance.

However, the file input/output using memory mapping incurs great expense of time and labor to create a memory mapping between a frame of a file and a page of a process when a page fault occurs. Furthermore, the memory mapping is erased when the file input/output using the memory mapping ends. To overcome these problems, an approach for efficiently using a memory mapping that has been generated is desired.

SUMMARY

According to an example embodiment of the inventive concepts, a memory mapping management method for a nonvolatile main memory system includes receiving a request to cancel a memory mapping, determining whether the memory mapping is a mapping of a file based on meta data relating to the memory mapping, separately storing the meta data when the memory mapping is the mapping of the file, and cancelling the memory mapping when the memory mapping is not the mapping of the file.

According to an example embodiment of the inventive concepts, a memory mapping management method for a nonvolatile main memory system, which uses nonvolatile memory as main memory, includes receiving a memory mapping request, searching for a memory mapping for a file in a memory mapping storage space when a requested memory mapping is a mapping of the file, and reusing a searched memory mapping found during the search when a region of the searched memory mapping includes a region required by the requested memory mapping in a virtual address space.

According to an example embodiment of the inventive concepts, a memory mapping management method for a nonvolatile main memory system, which uses nonvolatile memory as main memory, includes a first management operation and a second management operation. The first management operation includes receiving a memory mapping request, accessing a memory mapping for a file in a memory mapping storage space when a requested memory mapping is a mapping of the file, and reusing the accessed memory mapping when a region of the accessed memory mapping includes a region required by the requested memory mapping in a virtual address space. The second management operation includes receiving a request to cancel a memory mapping, determining whether the memory mapping is a mapping of a file based on meta data relating to the memory mapping, separately storing the meta data to have a first data structure and a second data structure when the memory mapping is the mapping of the file, and cancelling the memory mapping when the memory mapping is not the mapping of the file.

DETAILED DESCRIPTION

With the recent development of manufacturing processes for producing semiconductor memory, functions of the semiconductor memory have been rapidly improved. For example, nonvolatile memory has reached a level of replacing existing volatile main memory or sub memory in terms of performance indices such as read latency, write latency, addressability, and/or endurance.

Hereinafter, the description will be made based on the premise that systems according to some example embodiments of the inventive concepts have the following technical features, which reflects technical developments in nonvolatile memory. Firstly, systems according to some example embodiments of the inventive concepts include a main memory formed of nonvolatile memory instead of volatile memory. Here, the nonvolatile memory may include persistent memory. Secondly, the nonvolatile main memory functions as sub memory and is thus able to store a file system therein.

FIG. 1is a block diagram of a nonvolatile main memory system10according to an example embodiment of the inventive concepts. The nonvolatile main memory system10may include a computing system100and a sub memory142.

The computing system100may include a central processing unit (CPU)110, a memory mapping manager120, a nonvolatile main memory130, a sub memory controller140, and a bus150. The CPU110may include at least one core111and a cache112. The nonvolatile main memory130may include a page table (PT)132.

The CPU110may control the overall operation of the nonvolatile main memory system10under the control of an operating system (OS). The CPU110may use the core111and the cache112to control the overall operation of the nonvolatile main memory system10.

The CPU110may control the overall operation of the nonvolatile main memory system10to generate a memory mapping between pages of virtual memory and frames of physical memory. Here, the pages may be blocks of certain size into which a storage space of the virtual memory is divided and the frames may be blocks of certain size into which a storage space of the physical memory is divided. The physical memory may be the nonvolatile main memory130.

The CPU110may store a result of the memory mapping between the pages and the frames in the PT132. The CPU110may input a new memory mapping result to the PT132or may erase the existing memory mapping result from the PT132.

The CPU110may also perform file input/output (I/O). In addition, the CPU110may perform memory mapped file I/O using the memory mapping. When the CPU110performs file I/O using memory mapping, memory copy overhead brought by general file I/O can be avoided and a file can be directly accessed without a help of other hardware and/or software component(s).

The nonvolatile main memory130may include electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic random access memory (MRAM), spin-transfer torque MRAM, ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM, nano floating gate memory (NFGM), holographic memory, molecular electronics memory device, or insulator resistance change memory. However, the inventive concepts are not restricted to these examples. The nonvolatile main memory130may include persistent memory which retains data even when power is off. The PT132included in the nonvolatile main memory130may store a result of memory mapping between virtual memory and physical memory.

The sub memory controller140may control a data access operation, e.g., a write operation or a read operation, of the sub memory142according to the control of the CPU110. The sub memory controller140may be implemented in a chip separated from the CPU110or may be implemented as a part of the CPU110. The sub memory142extends the functions of the nonvolatile main memory130to permanently preserve a large amount of data.

The computing system100may be implemented as a personal computer (PC) or a mobile device, such as a laptop computer, a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, an internet of everything (IoE) device, a drone, or an e-book, but the inventive concepts are not restricted to these examples.

The components110,111,112,120,130,132, and140of the computing system100may communicate data with one another through the bus150. The bus150may be implemented as advanced microcontroller bus architecture (AMBA), an advanced high-performance bus (AHB), an advanced system bus (ASB), advanced extensible interface (AXI) coherency extensions (ACE), or a combination thereof, but the inventive concept is not restricted to these examples. The structure and functions of the memory mapping manager120will be described in detail with reference toFIG. 5later.

FIG. 2is a block diagram of a nonvolatile main memory130-1formed of NAND flash memory according to an example embodiment of the inventive concepts.FIG. 3is a detailed diagram of a memory cell array1410illustrated inFIG. 2according to an example embodiment of the inventive concepts.FIG. 4is a detailed diagram of the memory cell array1410illustrated inFIG. 2according to an example embodiment of the inventive concepts.

Referring toFIG. 2, the nonvolatile main memory130-1may include the memory cell array1410and an access circuit1412. The memory cell array1410includes NAND memory cell strings respectively connected to bit lines. Each of the NAND memory cell strings includes a plurality of nonvolatile memory cells connected in series to one another.

Each NAND memory cell string may be laid out (or embodied) on one plane (or layer) in two dimensions as illustrated inFIG. 3. Alternatively, the memory cell array1410may be implemented in three dimensions, as illustrated inFIG. 4, using a wafer stack, a chip stack, or a cell stack.

Referring toFIGS. 3 and 4, the NAND memory cell string may include the nonvolatile memory cells connected in series between a string selection transistor ST1connected to one of the bit lines and a ground selection transistor ST2connected to a common source line (CSL). A gate of the string selection transistor ST1may be connected to a string selection line (SSL). Gates of the respective nonvolatile memory cells may be connected to a plurality of word lines, respectively. A gate of the ground selection transistor ST2may be connected to a ground selection line (GSL). The NAND memory cell strings may be connected to page buffers1421-1lthrough1421-1minFIG. 3 or 1421-1 through 1421-minFIG. 4, respectively. At this time, the number of word lines may vary depending on example embodiments.

The three-dimensional (3D) memory cell array may be monolithically formed at one or more physical levels in an array of memory cells having an active region disposed on or above a silicon substrate and may include a circuit related with the operation of the memory cells. The circuit may be formed in, on or above the silicon substrate. The term “monolithic” means that layers at each level in an array are directly deposited on layers at an underlying level in the array. The three-dimensional memory cell array may include a vertical NAND string which is vertically oriented so that at least one memory cell is placed on or above another memory cell. The at least one memory cell may include a charge trap layer. The following patent documents, which are hereby incorporated by reference, describe suitable 3D memory cell array configurations, in which the 3D memory cell array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

The access circuit1412may access the memory cell array1410to perform a data access operation, for example, a program operation, a read operation, or an erase operation, according to a command (or a set of commands) and an address received from an outside, the CPU110. The access circuit1412may include a voltage generator1440, a row decoder1450, a control logic1460, a column decoder1470, a page buffer and sense amplifier (S/A) block1420, a Y-gating circuit1430, and an I/O block1480.

The voltage generator1440may generate a voltage for a data access operation in response to a control code generated by the control logic1460. The voltage generator1440may generate a program voltage and a program-verify voltage to perform a program operation, read voltages to perform a read operation, and an erase voltage and an erase-verify voltage to perform an erase operation and may output the voltages for each of the operations to the row decoder1450.

The control logic1460may control the overall operation of the access circuit1412in response to a command CMD output from the CPU110. The control logic1460may control memory read state information to be sensed during a memory read operation and data that has been read to be output to the CPU110.

Under the control of the control logic1460, the column decoder1470may decode a column address YADD and output a plurality of select signals to the Y-gating circuit1430.

The page buffer and S/A block1420may include a plurality of page buffers PB. The page buffers PB may be connected to the bit lines, respectively.

The page buffers PB may operate as drivers that temporarily store data read from the memory cell array1410in the read operation according to the control of the control logic1460. Each of the page buffers PB may also operate as an S/A which senses and amplifies a voltage of each bit line during the read operation according to the control of the control logic1460.

The Y-gating circuit1430may control transmission of data between the page buffer and S/A block1420and the I/O block1480in response to the select signals received from the column decoder1470.

The I/O block1480may transmit data from an outside to the Y-gating circuit1430or transmit data from the Y-gating circuit1430to the CPU110through a plurality of I/O pins (or a data bus).

FIG. 5is a block diagram of the structure of components included in the memory mapping manager120illustrated inFIG. 1. Referring toFIGS. 1 and 5, the memory mapping manager120may include an interface (I/F)1000, a mapping controller1001, a search engine1002, a determinator1003, a memory mapping storage space1004, and a bus1005as the components. The memory mapping storage space1004may include a first data structure space1004aand a second data structure space1004b. The components1000,1001,1002,1003,1004,1004a,1004b, and1005may manage memory mapping of a nonvolatile main memory system according to some example embodiments of the inventive concepts.

The I/F1000may receive, for example, a memory mapping request or a memory mapping cancellation request from the CPU110. The memory mapping request or the memory mapping cancellation request may be a system call which enables a process to use the function of a kernel of an OS. The memory mapping request or the memory mapping cancellation request may include arguments. The arguments included in the memory mapping request may include address information of a virtual memory space to be allocated, information about the size, the right and the mode of a memory mapping, a descriptor of a target file of the memory mapping, and an offset value for starting the memory mapping in the descriptor. The arguments included in the memory mapping cancellation request may include information about a start address of a virtual memory space that has been subjected to a memory mapping and the size of the memory mapping.

The I/F1000may send a search request for meta data relating to a memory mapping to the CPU110and may receive the meta data from the CPU110under the control of the mapping controller1001. Some example embodiments relating to the memory mapping request, the memory mapping cancellation request, and the meta data will be described in detail with reference toFIGS. 6 and 10later.

The mapping controller1001may control each component included in the memory mapping manager120. The mapping controller1001may transmit arguments included in the memory mapping request and the memory mapping cancellation request, which are received through the I/F1000, to each component included in the memory mapping manager120. At this time, the mapping controller1001may send the CPU110a request to reserve the operation involved in the memory mapping request or the memory mapping cancellation request until execution of some example embodiments of the inventive concepts according to the requests is terminated.

The mapping controller1001may generate a memory mapping and store it in the memory mapping storage space1004or may cancel the memory mapping stored in the memory mapping storage space1004. Further, the mapping controller1001may update or revise the memory mapping stored in the memory mapping storage space1004.

The search engine1002may search a memory mapping stored in the memory mapping storage space1004under the control of the mapping controller1001. At this time, the search engine1002may use a first data structure. The search engine1002may cancel a memory mapping stored in the memory mapping storage space1004under the control of the mapping controller1001. At this time, the search engine1002may use a second data structure. The first data structure may be a hash table and the second data structure may be a free list. The first data structure and the second data structure will be described in detail with reference toFIGS. 8 and 9later.

The determinator1003may determine whether a memory mapping corresponding to a memory mapping request or a memory mapping cancellation request is a mapping of a file. The determinator1003may determine whether the memory mapping requested is the mapping of a file based on one of arguments included in the memory mapping request. The determinator1003may also determine whether the memory mapping to be cancelled is the mapping of a file based on meta data transmitted in response to the memory mapping cancellation request.

The determinator1003may also determine whether a region of a memory mapping in a virtual address space searched for in the memory mapping storage space1004by the search engine1002includes a region in the virtual address space requested by a memory mapping. The region of the searched memory mapping in the virtual address space may be determined using a structure member included in meta data relating to the searched memory mapping. The region required by the requested memory mapping in the virtual address space may be determined using arguments included in the memory mapping request.

The memory mapping storage space1004may store a memory mapping under the control of the mapping controller1001.

The components1000,1001,1002,1003,1004,1004a, and1004bof the memory mapping manager120may communicate data with one another through the bus1005. The operations and functions of the memory mapping manager120and its components1000,1001,1002,1003,1004,1004a, and1004bwill be described in detail with reference toFIGS. 6 through 11later.

The memory mapping manager120and its components1000,1001,1002,1003,1004,1004a, and1004bmay be implemented as hardware components. The I/F1000, the mapping controller1001, the search engine1002, the determinator1003, the memory mapping storage space1004, and the bus1005may be implemented inside the computing system100. For example, the components may be implemented as parts of the CPU110or may be implemented in a chip or chips separated from the CPU110. When the components are implemented in a chip or chips separated from the CPU110, the components may be implemented inside a memory management unit (MMU) (not shown). The first data structure space1004aand the second data structure space1004bmay be stored in the cache112.

In some example embodiments, the memory mapping manager120and its components1000,1001,1002,1003,1004,1004a, and1004bmay be implemented as software components. For example, the I/F1000, the mapping controller1001, the search engine1002, the determinator1003, the memory mapping storage space1004, and the bus1005may be stored in the nonvolatile main memory130and executed by an OS.

FIG. 6is a flowchart of a memory mapping management method for the nonvolatile main memory system10when there is a memory mapping cancellation request according to an example embodiment of the inventive concepts. Referring toFIGS. 1 through 6, the memory mapping cancellation request may be received in operation S100. The memory mapping cancellation request is a system call by a process and may be received by the I/F1000. The I/F1000may receive the memory mapping cancellation request from the CPU110. The memory mapping cancellation request may include arguments which may include information about a start address of a virtual memory space that has been subjected to a memory mapping and the size of the memory mapping.

Thereafter, meta data relating to the memory mapping whose cancellation has been requested may be searched for in operation S102. The search of the meta data may be performed by the CPU110at the request of the mapping controller1001. The request of the mapping controller1001may be transmitted to the CPU110through the I/F1000. The meta data will be described in detail with reference toFIG. 7.

FIG. 7is a diagram of the meta data relating to the memory mapping. The meta data may be a data structure provided by the OS for the management of virtual memory. The meta data may include a structure and structure members. The start address of the virtual memory space that has been subjected to a memory mapping may be included as a structure member. The search of the meta data relating to the memory mapping whose cancellation has been requested may be performed by comparing the argument included in the memory mapping cancellation request with the structure members included in the meta data relating to the memory mapping. The searched meta data may be a set of meta data having a structure member which coincides with the start address of the virtual memory space that has been subjected to a memory mapping and included in the argument.

Referring back toFIGS. 1 through 6, the CPU110may transmit the meta data that have been searched for in operation S102to the mapping controller1001through the I/F1000. The mapping controller1001may transmit the meta data to the determinator1003. Thereafter, whether the memory mapping whose cancellation has been requested is a mapping of a file may be determined in operation S104. The determination may be performed by the determinator1003. Referring toFIG. 7, the determinator1003may determine whether the memory mapping whose cancellation has been requested is the mapping of a file based on a structure member including information about the mapping of a file among structure members of the meta data transmitted by the mapping controller1001.

When it is determined that the memory mapping is the mapping of a file (i.e., in case of YES) in operation S104, an access right to the meta data relating to the memory mapping may be revised in operation S106aand the meta data relating to the memory mapping may be separately stored in the memory mapping storage space1004in operation S106b.

The revision of the access right may be performed by the mapping controller1001in operation S106a. Referring toFIG. 7, the mapping controller1001may revise a structure member representing the access right among the structure members of the meta data relating the memory mapping. The revised access right may be for read-only.

The storing of the meta data may be performed by the mapping controller1001in operation S106b. The mapping controller1001may separately store the meta data relating to the memory mapping in the memory mapping storage space1004. The meta data stored in the memory mapping storage space1004may be managed using a first data structure and a second data structure, which will be described in detail with reference toFIGS. 8 and 9.

FIG. 8is a diagram of the first data structure for managing the meta data.FIG. 9is a diagram of the second data structure for managing the meta data. The first data structure may be a data structure for searching for the meta data having a particular structure member among a plurality of random meta data at a relatively high speed. The second data structure may be a data structure for erasing meta data which is the oldest one among the plurality of random meta data. The first data structure may be a hash table and the second data structure may be a free list.

Referring toFIG. 8, the hash table may store meta data M(0) through M(j−1) and M(j) through M(k−1) in a bucket. A hash key of the hash table may be a file location. The hash table may use chaining in order to avoid hash collision(s). Referring toFIG. 9, the free list may store the meta data M(0) through M(j−1) and M(j) through M(k−1) in order in which they are stored according to operation S106b. The free list may add the meta data to its tail in operation S106b. Referring toFIGS. 7 through 9, the meta data stored in the hash table and the free list may include structure members indicating a position in the hash table and a position in the free list.

When it is determined that the memory mapping is not the mapping of a file (i.e., in case of NO) in operation S104, the memory mapping is canceled in operation S108. The cancellation of the memory mapping may be performed by the CPU110at the request of the mapping controller1001. The CPU110may cancel the memory mapping under the control of the OS. With the cancellation of the memory mapping, the memory mapping may be erased from the PT132in the nonvolatile main memory130.

Consequently, in the memory mapping management method for a nonvolatile main memory system according to some example embodiments of the inventive concepts, when a memory mapping cancellation request is received and a memory mapping whose cancellation is requested is the mapping of a file, meta data relating to the memory mapping is separately stored in the memory mapping storage space1004, so that the memory mapping whose cancellation is requested can be kept.

FIG. 10is a flowchart of a memory mapping management method for the nonvolatile main memory system10when there is a memory mapping request according to an example embodiment of the inventive concepts. Referring toFIGS. 1, 5, and 10, the memory mapping request is received in operation S200.

The memory mapping request is a system call by a process and may be received by the I/F1000. The I/F1000may receive the memory mapping request from the CPU110. The memory mapping request may include arguments which may include address information of a virtual memory to be allocated in response to the memory mapping request, information about the size, the right and the mode of a memory mapping, a file descriptor of a target file of the memory mapping, and an offset value for starting the memory mapping in the descriptor. The memory mapping request is transmitted from the I/F1000to the determinator1003under the control of the mapping controller1001.

Thereafter, whether the memory mapping is the mapping of a file may be determined in operation S202. The determination may be performed by the determinator1003. The determinator1003may determine whether the memory mapping is the mapping of a file based on one of the arguments included in the memory mapping request under the control of the mapping controller1001. For example, the determinator1003may determine whether the memory mapping is the mapping of the file based on information about the mode of the memory mapping among the arguments included in the memory mapping request.

When it is determined that the memory mapping is the mapping of a file (i.e., in case of YES) in operation S202, a memory mapping may be searched for a file, which is the same as the file determined in operation202, in the memory mapping storage space1004in operation S204. For example, the search of the memory mapping may be performed by the search engine1002under the control of the mapping controller1001. The search engine1002may search memory mappings in the memory mapping storage space1004to find the memory mapping of a file, which is the same as the file determined in operation S202.

As described above with reference toFIGS. 8 and 9, the memory mappings stored in the memory mapping storage space1004may be managed using the first data structure and the second data structure. The first data structure may be a hash table and the second data structure may be a free list. The search engine1002may use the first data structure to search for the memory mapping of the file in the memory mapping storage space1004.

After operation S204, whether a region of the searched memory mapping in a virtual address space includes a region in the virtual address space requested by the memory mapping may be determined in operation S206. The determination may be performed by the determinator1003in operation S206. The region required by the requested memory mapping in the virtual address space may be determined using arguments included in the memory mapping request. The arguments may include address information of virtual memory to be allocated according to the memory mapping request and information about the size of the memory mapping. The region of the searched memory mapping in the virtual address space may be determined using a structure member included in meta data relating to the searched memory mapping.

In operation S206, it is determined whether the region of the searched memory mapping in the virtual address space includes the region required by the requested memory mapping in the virtual address space.FIG. 11is a diagram for explaining the cases where the region of the searched memory mapping in the virtual address space includes the region required by the requested memory mapping in the virtual address space.

In the first case shown inFIG. 11, a region MRQT1required by the requested memory mapping in the virtual address space totally coincides with a region MSRH1of the searched memory mapping in the virtual address space. In the second case shown inFIG. 11, a region MRQT2required by the requested memory mapping in the virtual address space coincides with a part MSRH2of a region MSRH2+MSRH2′ of the searched memory mapping in the virtual address space. In the third case shown inFIG. 11, a region MRQT3required by the requested memory mapping in the virtual address space coincides with a part MSRH3of a region MSRH3′+MSRH3+MSRH3″ of the searched memory mapping in the virtual address space. In other words, cases where the region of the searched memory mapping in the virtual address space may include the region required by the requested memory mapping in the virtual address space may include the first through third cases illustrated inFIG. 11.

When it is determined that the region of the searched memory mapping in the virtual address space includes the region required by the requested memory mapping in the virtual address space (i.e., in case of YES) in operation S206, an access right of the searched memory mapping may be revised to be the same as an access right of the requested memory mapping in operation S208. The revision of the access right may be performed by the mapping controller1001in operation S208. The access right may be read-only, write-only, execute-only, or a combination thereof. The mapping controller1001may revise a structure member representing the access right among the structure members of the meta data relating to the searched memory mapping so that the access right of the searched memory mapping is the same as the access right of the requested memory mapping.

Thereafter, the searched memory mapping is reused in operation S210. The reuse of the searched memory mapping may be performed by the mapping controller1001. The mapping controller1001may transmit the meta data relating to the searched memory mapping to the CPU110through the I/F1000. The reuse of the searched memory mapping will be described in detail with reference toFIGS. 7 and 11.

In the first case shown inFIG. 11, the region MRQT1required by the requested memory mapping in the virtual address space entirely coincides with the region MSRH1of the searched memory mapping in the virtual address space. In the second and third cases shown inFIG. 11, the regions MRQT2and MRQT3required by the requested memory mapping in the virtual address space coincide with the parts MSRH2and MSRH3, respectively, of the regions MSRH2+MSRH2′ and MSRH3′+MSRH3+MSRH3″ of the searched memory mapping in the virtual address space. In such case, the searched memory mapping may be reused within a range in which the region of the searched memory mapping coincides with the region of the requested memory mapping in the virtual address space. For instance, the searched memory mappings MSRH1, MSRH2, and MSRH3which coincide with the region of the requested memory mapping in the first through third cases may be reused.

When the region required by the requested memory mapping at least partially coincides with the region of the searched memory mapping in the virtual address space, the meta data of the searched memory mapping may be revised to have the same range as the region of the requested memory mapping in the virtual address space. For example, the meta data of the searched memory mapping may be revised by changing a start address and an end address in the virtual memory space among the structure members included in the meta data.

The searched memory mapping may be stored in the memory mapping storage space1004within a range in which the region of the searched memory mapping does not coincide with the region of the requested memory mapping in the virtual address space. For instance, in the second and third cases, the searched memory mappings MSRH2′, MSRH3′, and MSRH3″ which do not coincide with the region of the requested memory mapping may be stored in the memory mapping storage space1004.

For this operation, meta data the same as the meta data of the searched memory mapping may be generated. The generated meta data may be revised to have a range except for the region of the requested memory mapping in the virtual address space. The meta data of the searched memory mapping may be revised by changing a start address and an end address in the virtual memory space among structure members included in the meta data, which is the same as the meta data of the searched memory mapping.

Consequently, in the memory mapping management method for a nonvolatile main memory system according to the current example embodiment of the inventive concepts, when a memory mapping request is received and a requested memory mapping is the mapping of a file, a memory mapping stored in a memory mapping storage space can be reused, so that time and cost for generating the requested memory mapping can be saved.

When it is determined that the region of the searched memory mapping in the virtual address space does not include the region required by the requested memory mapping in the virtual address space (i.e., in case of NO) in operation S206, whether the memory mapping storage space1004is insufficient may be determined in operation S212. The determination may be performed by the determinator1003in operation S212. The maximum value of the memory mapping storage space1004may be predetermined for the memory mapping management method.

When it is determined that the memory mapping storage space1004is insufficient (i.e., in case of YES) in operation S212, the memory mapping storage space1004may be canceled in operation S214. The cancellation of the memory mapping storage space1004may be performed by the mapping controller1001. The mapping controller1001may cancel meta data relating to a memory mapping stored in the memory mapping storage space1004to cancel the memory mapping storage space1004.

The meta data to be cancelled may be selected by the search engine1002under the control of the mapping controller1001. As described above with reference toFIGS. 8 and 9, the memory mapping stored in the memory mapping storage space1004may be managed using the first data structure and the second data structure. The first data structure may be a hash table and the second data structure may be a free list.

The search engine1002may use the second data structure to select the meta data to be cancelled. The meta data selected by the search engine1002may be the oldest one among the meta data relating to the memory mapping stored in the memory mapping storage space1004. The mapping controller1001may release the meta data selected by the search engine1002from the first data structure and the second data structure.

Consequently, in the memory mapping management method for a nonvolatile main memory system according to the current example embodiment of the inventive concepts, when a memory mapping storage space is insufficient, the oldest meta data relating to the memory mapping is cancelled so that maintenance of meta data relating to the memory mapping stored in the memory mapping storage space is possible.

After operation S214, the requested memory mapping may be generated in operation S216. When it is determined that the memory mapping storage space1004is not insufficient (i.e., in case of NO) in operation S212, the requested memory mapping may also be generated in operation S216. The generation of the requested memory mapping may be performed by the CPU110at the request of the mapping controller1001in operation S216. The mapping controller1001may generate meta data relating to the requested memory mapping and send the meta data to the CPU110. When a page fault occurs, the CPU110may generate the requested memory mapping using the meta data relating to the requested memory mapping under the control of the OS. The requested memory mapping may be stored in the PT132in the nonvolatile main memory130.

When it is determined that the memory mapping is not the mapping of a file (i.e., in case of NO) in operation S202, an anonymous memory mapping may be generated in operation S218. The generation of the anonymous memory mapping may be performed by the CPU110at the request of the mapping controller1001. The mapping controller1001may generate meta data relating to the anonymous memory mapping and send the meta data to the CPU110. When a page fault occurs, the CPU110may generate the anonymous memory mapping using the meta data relating to the anonymous memory mapping under the control of the OS. The anonymous memory mapping may be stored in the PT132in the nonvolatile main memory130.

FIG. 12is a block diagram of a system20including the CPU and the nonvolatile main memory illustrated inFIG. 1according to an example embodiment of the inventive concepts.

Referring toFIGS. 1 and 12, the system20may be implemented as a cellular phone, a smart phone, or a tablet personal computer (PC).

The system20includes a host210and a memory device200. The memory device200may be the memory device130illustrated inFIG. 1.

According to some example embodiments, the host210and the memory device200may be packaged in a single package. In this case, the package may be mounted on the system board (not shown).

The system20includes a memory controller220that can control, for example, the test operation of the memory device200and the data processing operation of the memory device200, for example, a write operation or a read operation.

The memory controller220may be controlled by the host210, which controls the overall operation of the system20. The memory controller220may be connected between the host210and the memory device200.

The data in the memory device200may be displayed through a display230according to the control of the host210.

A radio transceiver240transmits or receives radio signals through an antenna ANT. The radio transceiver240may convert radio signals received through the antenna ANT into signals that can be processed by the host210. Accordingly, the host210may process the signals output from the radio transceiver240and store the processed signals in the memory device200or display the processed signals through the display230.

The radio transceiver240may also convert signals output from the host210into radio signals and outputs the radio signals to an external device through the antenna ANT.

An input device250enables control signals for controlling the operation of the host210or data to be processed by the host210to be input to the system20. The input device250may be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The host210may control the operation of the display230to display data output from the memory device200, data output from the radio transceiver240, or data output from the input device250.

FIG. 13is a block diagram of a system30including the CPU and the nonvolatile main memory illustrated inFIG. 1according to an example embodiment of the inventive concepts. The system30may be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The system30includes a host310for controlling the overall operation of the system30and the memory device300. The memory device300may be the memory device130illustrated inFIG. 1.

According to some example embodiments, the host310and the memory device300may be packaged in a single package. In this case, the package may be mounted on the system board (not shown).

The system30may include a memory controller320for controlling the operation of the memory device300. The memory controller320may be the memory controller140illustrated inFIG. 1.

The host310may display data stored in the memory device300through the display330according to data input through the input device340. The input device340may be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

FIG. 14is a block diagram of a system40including the CPU and the nonvolatile main memory illustrated inFIG. 1according to an example embodiment of the inventive concepts. The system40may be implemented as an image processing device like a digital camera, a cellular phone equipped with a digital camera, or a smart phone equipped with a digital camera.

The system40includes a host410, the memory device400and a memory controller420controlling the data processing operations, such as a write operation or a read operation, of the memory device400. The system40further includes an image sensor430and a display440.

The image sensor430included in the system40converts optical images into digital signals and outputs the digital signals to the host410or the memory controller420. The digital signals may be controlled by the host410to be displayed through the display440or stored in the memory device400through the memory controller420.

Data stored in the memory device400may be displayed through the display440according to the control of the host410or the memory controller420. The memory controller420, which may control the operations of the memory device400, may be implemented as a part of the host410or as a separate chip.

FIG. 15is a block diagram of a system50including the CPU and the nonvolatile main memory illustrated inFIG. 1according to an example embodiment of the inventive concepts. The system50includes the memory device520and a host510controlling the operations of the memory device520. The memory device520may be implemented by nonvolatile memory such as a flash memory.

The system50may include a system memory500, a memory interface530, an error correction code (ECC) block540, and a host interface550.

The system memory500may be used an operation memory of the host510. The system memory500may be implemented by, for example, a non-volatile memory like read-only memory (ROM) or a volatile memory like static random access memory (SRAM).

The host510connected with the system50may perform data communication with the memory device520through the memory interface530and the host interface550.

The ECC block540may be controlled by the host510to detect an error bit included in data output from the memory device520through the memory interface530, correct the error bit, and transmit the error-corrected data to the host510through the host interface550. The host510may control data communication among the memory interface530, the ECC block540, the host interface550, and the memory device520through a bus570. The system50may be implemented as a flash memory drive, a USB memory drive, an IC-USB memory drive, or a memory stick.

As described above, in a memory mapping management method according to some example embodiments of the inventive concepts, meta data relating to a memory mapping may be separately stored in a memory mapping storage space when a memory mapping cancellation request is received and the memory mapping whose cancellation is requested is the mapping of a file so that the memory mapping whose cancellation is requested can be kept or maintained. In addition, when a memory mapping request is received and a memory mapping requested is the mapping of a file, the memory mapping stored in the memory mapping storage space may be reused so that time and cost for generating the requested memory mapping can be saved. Further, when the memory mapping storage space is insufficient, the oldest meta data among meta data relating to the memory mapping may be cancelled so that meta data relating to the memory mapping stored in the memory mapping storage space can be kept or maintained.