Mode selection circuit and switch control circuit including the mode selection circuit and multi functions pin

A mode selection circuit generates a mode voltage according to a clamping current flowing when a voltage of a multi-pin is clamped to a predetermined clamping voltage, and selects one of a plurality of mode signals according to the mode voltage. The mode voltage is controlled according to a passive element connected to the multi-pin.

BACKGROUND

(a) Field of the Invention

Exemplary embodiments relate to a mode selection circuit and a switch control circuit including the mode selection circuit and a multi-function pin.

(b) Description of the Related Art

Prior to operation of a converter, a mode may be selected. Mode selection implies determination of an operation mode of a control IC. Parameters are set or thorough functions of the control IC are determined through mode selection.

For such mode selection, a conventional control IC includes an additional structure and a mode is selected through an additional process through the additional structure. For example, prior to operation of a converter, an internal current source of the control IC is connected to a specific pin of the control IC and an operation mode is selected by a voltage of the specific pin. After that, start-up operation is performed. Thus, an additional current source is required and a start-up period is increased due to a connection period between the specific pin and the internal current source.

SUMMARY OF THE INVENTION

The invention has been made in an effort to provide a mode selection circuit that can select a mode without an additional structure and an additional process, and a switch control circuit including the mode selection circuit and a multi-functional pin.

A mode selection circuit according to an exemplary embodiment includes: a mode voltage generator configured to generate a mode voltage according to a clamping current that flows when a voltage of a multi-pin is clamped to a predetermined clamping voltage; and an operation mode distinction circuit configured to select one of a plurality of mode signals according to the mode voltage. The mode voltage is controlled according to a passive element connected to the multi-pin.

The mode voltage generator further includes a clamping circuit that clamps the voltage of the multi-pin to the clamping voltage when being connected to the multi-pin.

The mode voltage generator includes a comparator configured to compare the voltage of the multi-pin with a predetermined reference voltage and a clamping circuit configured to clamp the voltage of the multi-pin to the clamping voltage. Connection between the clamping circuit and the multi-pin may be controlled according to an output of the comparator and an enabled mode signal of among the plurality of mode signals.

The mode voltage generator includes a connection switch connected between the multi-pin and the clamping circuit, and turns on the connection switch according to the output of the comparator and turns off the connection switch according to the enabled mode signal.

The mode selection circuit may further include a logic operation unit that turns on the connection switch according to the output of the comparator when the voltage of the multi-pin reaches the predetermined reference voltage and turns off the connection switch according to the enabled mode signal.

The mode selection circuit further includes a current mirror circuit configured to generate a mirror current by mirroring the clamping current and a resistor to which the mirror current flows, wherein the mode voltage is a voltage generated in the resistor.

The operation mode distinction circuit includes: a plurality of first comparators configured to compare whether the mode voltage is lower than a corresponding threshold voltage among a plurality of first threshold voltages; a plurality of second comparators configured to compare whether the mode voltage is higher than a corresponding threshold voltage among a plurality of second threshold voltages; and a plurality of logic operation units configured to perform logic operation on an output of a third comparator among the plurality of first comparators and an output of a fourth comparator that corresponds to the third comparator among the plurality of second comparators. The plurality of mode selection signals include outputs of the plurality of logic operation units.

The plurality of mode selection signals include: an output of a comparator comparing a lowest first threshold voltage with the mode voltage among the plurality of first comparators; and an output of a comparator comparing a highest second threshold voltage with the mode voltage among the plurality of second comparators.

The mode voltage generator may further include a clamping circuit configured to clamp a voltage of the multi-pin to a predetermined clamping voltage when being connected to the multi-pin and a sampling/holder configured to sample the voltage of the multi-pin for a predetermined period and hold the sampled voltage. The mode selection circuit controls connection between the clamping circuit and the multi-pin according to a result of comparison between the held voltage and a predetermined reference voltage.

A switch control circuit according to an exemplary embodiment controls switching operation of a power switch. The switch control circuit includes a multi-pin connected to a passive element and a mode selection circuit configured to generate a mode voltage according to a clamping current flowing when a voltage of the multi-pin is clamped to a predetermined clamping voltage and select one of a plurality of mode signals according to the mode voltage.

The switch control circuit further includes a first connection switch connected between the multi-pin and an internal block of the switch control circuit, and the mode selection circuit includes a clamping circuit configured to clamp the voltage of the multi-pin to the clamping voltage; and a second connection switch connected between the multi-pin and the clamping voltage. The mode selection circuit controls switching operation of the first and second connection switches according to an enabled mode signal among the plurality of mode signals and a result of comparison between the voltage of the multi-pin and a predetermined reference voltage.

The mode selection circuit may further include a logic operation unit that turns off the first connection switch and turns on the second connection switch according to an output of the result of comparison when the voltage of the multi-pin reaches the reference voltage and turns on the first connection switch and turns off the second connection switch according to an enabled mode selection signal among the plurality of mode selection signals.

The mode selection circuit includes a current mirror circuit configured to generate a mirror current by mirroring the clamping current and a resistor to which the mirror current flows, and the mode voltage is a voltage generated in the resistor.

The mode selection circuit includes: a plurality of first comparators configured to compare whether the mode voltage is lower than a corresponding first threshold voltage among a plurality of first threshold voltages; a plurality of second comparators configured to compare whether the mode voltage is higher than a corresponding second threshold voltage among the plurality of second threshold voltages; and a plurality of logic operation units configured to perform logic operation on an output of a third comparator among the plurality of first comparators and an output of a fourth comparator that corresponds to the third comparator among the plurality of second comparators. The plurality of mode selection signals include outputs of the plurality of logic operation units.

The plurality of mode selection signals include an output of a comparator comparing a lowest first threshold voltage with the mode voltage among the plurality of first comparators and an output of a comparator comparing a highest second threshold voltage with the mode voltage among the plurality of second comparators.

The mode selection circuit includes a clamping circuit configured to clamp a voltage of the multi-pin to a predetermined clamping voltage when being connected to the multi-pin and a sampling/holder configured to sample the voltage of the multi-pin for every switching cycle of the power switch during a turn-off period of the power switch and hold the sampled voltage. The mode selection circuit controls connection between the clamping circuit and the multi-pin according to a result of comparison between the held voltage and a predetermined reference voltage.

The multi-pin may be connected to an auxiliary wire coupled to a primary side wire that is connected to the power switch. Alternatively, the multi-pin may be connected to an output voltage of a power supply that includes the power switch. Alternatively, the multi-pin may be connected to a line voltage.

The mode voltage may be controlled according to the passive element.

A switch control circuit according to an exemplary embodiment controls switching operation of a power switch. The switch control circuit includes: a gate-pin connected to a gate of the power switch and a first resistor; a voltage source connected to the gate pin through a switch; and a mode selection circuit configured to generate a mode voltage according to a first current flowing between the voltage source and the gate-pin when the power switch is turned on, and select one of a plurality of mode signals according to the mode voltage. The first current may be determined according to the voltage source and the first resistor.

A switch control circuit according to an exemplary embodiment controls switching operation of a power switch. The switch control circuit includes: a gate pin connected to a gate of the power switch and a first resistor; a current source connected to the gate pin; and a mode selection circuit configured to select one of a plurality of mode signals according to a gate voltage that turns on the power switch. The gate voltage may be determined according to the first resistor and a current of the current source.

According to the exemplary embodiments, a mode selection circuit that can select a mode without an additional structure and an additional process, and a switch control circuit including the mode selection circuit and a multi-functional pin can be provided.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A switch control circuit according to an exemplary embodiment includes a plurality of pins, and at least one of the plurality of pins performs multi-functions. Mode selection is performed through the multi-pin. Mode selection includes selection of one of at least two functions that can be performed by a constituent element included in the switch control circuit and operation for setting a plurality of parameters set in the switch control circuit.

For example, a protection structure of the switch control circuit may be selected to one of an over-voltage protection function and an over-current protection function through the mode selection. In addition, reference voltages corresponding to the plurality of parameters can be set through the mode selection.

First, exemplary embodiments in which mode selection is performed through a sense pin included in the switch control circuit will be described.

FIG. 1shows a switch control circuit according to a first exemplary embodiment.

A switch control circuit10includes an IC internal block300and a mode selection circuit400.

A sense pin SP shown inFIG. 1is a pin for sensing a voltage at a specific node ND. The sense pin SP is a multi-pin in the exemplary embodiment. A voltage sensed through the node ND may be one of various voltages such as a voltage corresponding to an input voltage, a voltage corresponding to an output voltage, and a voltage corresponding to an output current. Two resistors RS1and RS2are connected in series between the node ND and a ground, and a node to which the two resistors RS1and RS2are connected is connected to the sense pin SP.

The switch control circuit10includes a mode voltage generator100and an operation mode distinction circuit200, and other constituent elements except for the mode voltage generator100and the operation mode distinction circuit200are illustrated as the IC internal block300.

The mode selection circuit400selects an operation mode of the switch control circuit10using a sense voltage VS input through the sense pin SP, and includes a mode voltage generator100and an operation mode distinction circuit200.

The mode voltage generator100according to the exemplary embodiment clamps the sense voltage VS input through the sense pin SP to a predetermined clamping voltage VCLP, and mirrors a current generated by clamping the sense voltage VS to generate a mode voltage VRM.

The operation mode distinction circuit200selects an operation mode according to a level of the mode voltage VRM, and generates a mode selection signals MDS that indicates a selected operation mode. The mode selection signals MDS may include a plurality of mode selection signals respectively indicating a plurality of modes.

The mode voltage generator100includes a first connection switch S1, a second connection switch S2, a comparator101, an XNOR gate102, a current mirror circuit103, a clamping circuit105, a buffer107, an inverter108, and a resistor RM.

The current mirror circuit103includes a current sensing unit104and a current source106. A clamping current Iclp flowing through the current sensing unit104is mirrored and then transmitted to the current source106, and in this case, a mirroring ratio may be K. The current source106generates a mirrored current K*Iclp. Hereinafter, the mirrored current is referred to as a mirror current IM1.

The mirror current IM1flows to the resistor RM, and the mode voltage VRM is generated in the resistor RM. The voltage VRM can be represented as K*Iclp*RM. A voltage source VCC supplies a voltage required for generation of the mirror current IM1of the current source106.

When the sense voltage VS reaches a voltage α*Vclp acquired by multiplying a predetermined ratio α to the clamping voltage Vclp, the first connection switch S1is turned off and the second connection switch S2is turned on. The clamping voltage Vclp is a Zener voltage of the clamping circuit105. The predetermined ratio may be appropriately set according to a design. The voltage (α*Vclp) is an example of a reference voltage, and it is not restrictive.

When the sense voltage VS reaches the voltage (α*Vclp), the comparator101outputs a high level, and since inputs of the XNOR gate102have different logic levels, the XNOR gate102outputs a low level. The buffer107turns off the first connection switch S1according to the output of the XNOR gate102, and the inverter108turns on the second connection switch S1by inverting the output of the XNOR gate102.

When the two inputs are different from each other, the XNOR gate102outputs a low level, and when the two inputs are the same, the XNOR gate102outputs a high level. The XNOR gate102is described as an example of a logic operation unit for controlling switching operation of the second connection switch S2, and the exemplary embodiment of the invention is not limited thereto.

Then, the sense pin SP is connected to the clamping circuit105, and the sense voltage VS of the sense pin SP is clamped to the clamping voltage Vclp. In this case, the clamping current Iclp flows through the clamping circuit105.

Since current flowing to the resistor RS1flows to the resistor RS2right before the clamping current Iclp flows, a current flowing to the ground from the node ND is α*Vclp/RS2. When the clamping current Iclp flows, the current flowing to the resistor RS2is Vclp/RS2, and therefore the current flowing to the ground through the clamping circuit105from the sense pin SP becomes α*Vclp/RS2−Vclp/RS2as given in Equation 1.
Iclp=α−1*Vclp/RS2  [Equation 1]

The clamping circuit105can be implemented as a Zener diode, and, as a Zener voltage of a Zener diode, the clamping voltage Vclp is a fixed in the switch control circuit10. In addition, the ratio α is also fixed in the switch control circuit10. However, RS2, that is, a resistance value of the resistor RS2is adjustable as an external component of the switch control circuit10connected through the sense pin SP. Thus, the clamping current Iclp can be controlled by changing the resistance value of the resistor RS2, and the mirror current IM1is determined according to the clamping current Iclp such that the mode voltage VRM can be controlled as given in Equation 2.
VRM=K*Iclp*RM[Equation 2]

Here, RM implies resistance of the RM. K and RM are also fixed in the switch control circuit10. That is, the mode selection signals MDS can be controlled by changing resistance of the resistor RS2.

The operation mode distinction circuit200selects one of a plurality of operation modes according to a level of the mode voltage VRM and enables a mode selection signal MDS that instructs the selected operation mode. For example, an enable level of the mode selection signal MDS may be a high level.

Since an output of the comparator101is latched to high level and the mode selection signal MD is high level, all inputs of the XNOR gate102become high level and the XNOR gate102accordingly outputs a high level. Then, the first connection switch S1is turned on and the second connection switch S2is turned off.

As described, the mode voltage VRM is determined according to a clamping current Iclp generated when the sense voltage VS reaches the predetermined voltage α*Vclp and the clamping current Iclp is controlled according to the resistor RS2, and therefore a mode of the switch control circuit10can be simply selected according to a resistance value of the resistor RS.

Hereinafter, a second exemplary embodiment in which a sense pin SP senses an output voltage will be described.

FIG. 2shows a switch control circuit and a converter according to a second exemplary embodiment.

A switch control circuit11includes an error amplifier301and a mode selection circuit400.

As shown inFIG. 2, a sense pin SP1of the switch control circuit11is connected to a sense voltage VS1that corresponds to an output voltage Vo of the converter1. A resistor RS3and a resistor RS4are connected in series between the output voltage Vo and a ground. An output capacitor Co filters a ripple of the output voltage Vo of the converter1.

The same reference numerals and marks designate the same elements in the first exemplary embodiment, and a detailed description thereof will be omitted hereinafter.

When the sense voltage VS1reaches a voltage (α*Vclp), a comparator101outputs a high level. An XNOR gate102outputs a low level according to the output of the comparator101and a low-level mode signal which is in a disable state. Then, a first connection switch S1is turned off and a second connection switch S2is turned on.

Then, the sense pin SP1is connected to a clamping circuit105, and the sense voltage VS1of the sense pin SP1is clamped to a clamping voltage Vclp. A clamping current Iclp flows through the clamping circuit105and mirrored by a current mirror circuit103such that a mirror current IM1is generated. Then a mode voltage VRM is generated as given in Equation 2.

The operation mode distinction circuit200receives the mode voltage VRM, and generates a plurality of mode signals mode1to mode4which are examples of mode selection signals. The operation mode distinction circuit200transmits a mode signal enabled by the mode voltage VRM to an input terminal of the XNOR gate102.

The operation mode distinction circuit200includes a plurality of comparators201to206and two AND gates211and212. The comparators201to206output a high level when an input of a non-inversion terminal (+) is higher than an input of an inversion terminal (−), and outputs a low level in the opposite case. The AND gates211and212output a high level when both of the two inputs are high levels. Otherwise, the AND gates211and212output a low level.

The comparator201generates a mode signal mode1according to a result of comparison between the mode voltage VRM and a first threshold voltage VTH1. The mode voltage VRM is input to an inversion terminal (−) of the comparator201, and the first threshold voltage VTH1is input to a non-inversion terminal (+) of the comparator201. Thus, the comparator201generates a high-level mode signal mode1, which is an enable level, when the mode voltage VRM is lower than the first threshold voltage VTH1.

The comparator202outputs a result of comparison between the mode voltage VRM and a second threshold voltage VTH2, and the comparator203outputs a result of comparison between the mode voltage VRM and a third threshold voltage VTH3. The mode voltage VRM is input to a non-inversion terminal (+) of the comparator202and an inversion terminal (−) of the comparator203, the second threshold voltage VTH2is input to an inversion terminal (−) of the comparator202, and the third threshold voltage VTH3is input to a non-inversion terminal (+) of the comparator203

In this case, the third threshold voltage VTH3may be higher than the second threshold voltage VTH2.

Then, when the mode voltage VRM is higher than the second threshold voltage VTH2and lower than the third threshold voltage VTH3, the comparator202and the comparator203both output high levels. When the mode voltage VRM is lower than the second threshold voltage VTH2, the comparator202outputs a low level and the comparator203outputs a high level. When the mode voltage VRM is higher than the third threshold voltage VTH3, the comparator203outputs a low level and the comparator202outputs a high level.

The AND gate211generates a mode signal mode2according to the output of the comparator202and the output of the comparator203. When the mode voltage VRM is higher than the second threshold voltage VTH2and lower than the third threshold voltage VTH3, the comparator202and the comparator203both output high levels, and therefore the AND gate211generates a high-level, which is, an enable level mode signal mode2.

The comparator204outputs a result of comparison between the mode voltage VRM and a fourth threshold voltage VTH4, and the comparator205outputs a result of comparison between the mode voltage VRM and the fifth threshold voltage VTH5. The mode voltage VRM is input to a non-inversion terminal (+) of the comparator204and an inversion terminal (−) of the comparator205, the fourth threshold voltage VTH4is input to an inversion terminal (−) of the comparator204, and the fifth threshold voltage VTH5is input to a non-inversion terminal (+) of the comparator205. In this case, the fifth threshold voltage VTH5may be higher than the fourth threshold voltage VTH4.

Thus, when the mode voltage VRM is higher than the fourth threshold voltage VTH4and lower than the fifth threshold voltage VTH5, the comparator204and the comparator205both output high levels. When the mode voltage VRM is lower than the fourth threshold voltage VTH4, the comparator204outputs a low level and the comparator205outputs a high level. When the mode voltage VRM is higher than the fifth threshold voltage VTH5, the comparator205outputs a low level and the comparator204outputs a high level.

The AND gate212generates a mode signal mode3according to the output of the comparator204and the output of the comparator205. When the mode voltage VRM is higher than the fourth threshold voltage VTH4and lower than the fifth threshold voltage VTH5, the comparator204and the comparator205both output high levels, and therefore the AND gate121generates a high-level mode signal mode3, which is an enable-level mode signal mode3.

The comparator206generates a mode signal mode4according to a result of comparison between the mode voltage VRM and a sixth threshold voltage VTH6. The mode voltage VRM is input to a non-inversion terminal (+) of the comparator206and the sixth threshold voltage VTH1is input to an inversion terminal (−) of the comparator206. Thus, the comparator206generates a high-level mode signal mode4, which is an enable-level mode signal mode4when the mode voltage VRM is higher than the sixth threshold voltage VTH6.

As described, according to the second exemplary embodiment, mode selection can be performed using the sense pin SP1that senses the output voltage Vo.

When a mode is selected and one of the mode signals mode1to mode4is enabled, all inputs of the XNOR gate102become high levels so that the first connection switch S1is turned on and the second connection switch S2is turned off.

Then, the sense voltage VS1is input to the error amplifier301, and the error amplifier301may generate an error voltage by amplifying a difference between the sense voltage VS1and a predetermined reference voltage. The switch control circuit11can control switching operation of the power switch according to the error voltage.

A sense voltage transmitted through the sense pin may be a voltage corresponding to an input voltage or an output voltage according to the switching operation of the power switch. A sense voltage of a turn-on period and a sense voltage of a turn-off period may need to be selected.

In a third exemplary embodiment, a sense voltage is sampled and held during a turn-off period of a power switch, and a mode selection may be performed according to the held voltage.

FIG. 3shows a power supply according to a third exemplary embodiment.

A switch control circuit12includes an IC internal block302and a mode selection circuit410. The mode selection circuit410according to the third exemplary embodiment further includes a sampling/holder109compared to the first and second exemplary embodiments.

The same reference numerals and marks as those of the first and second exemplary embodiment will be used for the same elements and a detailed description thereof will not be repeated in the following description.

A power supply2is exemplarily implemented as a flyback converter, and the second exemplary embodiment is not limited thereto.

The power supply2generates an output voltage Vo using an input voltage Vin rectified from an AC input.

A power switch M1performs switching operation according to a gate voltage VG1output from a switch control circuit12. The power switch M1is an n-channel type, and therefore, an enable level of the gate voltage VG1is a high level and a disable level of the gate voltage VG1is a low level.

The input voltage Vin is supplied to one end of a primary side wire W1, and the other end of the primary side wire W1is connected to a drain of the power switch M1. A current flowing to the primary side wire S1is increased with an inclination that depends on the input voltage Vin during a turn-on period of the power switch M1. During the turn-on period of the power switch M1, energy is stored in the primary side wire W1. When the power switch M1is turned off, a diode is conductive and thus a current flows to the secondary side wire W2.

A sense resistor RCS1is connected between a source of the power switch M1and a primary side ground. A switch current Ids flowing to the power switch M1flows to the sense resistor RCS1. A voltage generated in the sense resistor RCS1is referred to as a sense voltage CS1.

The secondary side wire W2is coupled in an insulated manner with the primary side wire W1, and a turn ratio n between the primary side wire W1and the secondary side wire W2corresponds to NS/NP. NS is turns of the secondary side wire W2and NP is turns of the primary side wire W1. One end of the secondary side wire W2is connected to the diode D1and the other end of the secondary side wire W2is connected to a secondary side ground.

The diode D1is connected between the secondary side wire W2and an output terminal. A cathode of the diode D1is connected to the output terminal and an output capacitor Co1.

The output capacitor Co1is connected between the output terminal and the secondary side ground and reduces a ripple of an output voltage Vo. The output capacitor Co1is charged by a current passed through the diode D1.

An auxiliary wire W3is coupled with the primary side wire W1in the primary side ground, and is coupled in an insulated manner with the secondary side wire W2. A turn ratio n1between turns (NA) of the auxiliary wire W3and turns (NP) of the primary side wire W1is NA/NP.

The secondary side wire W2is connected to the output voltage Vo through the diode D1, and a turn ratio n2between turns (NS) of the secondary side wire W2and turns (NA) of the auxiliary wire W3is NA/NS.

Two resistors RS5and RS6are connected in series between the auxiliary wire W3and the primary side ground, and a voltage of a node to which the two resistors RS5and RS6are connected is referred to as a sense voltage VS2.

When the power switch M1is in the turn-on state, a voltage of the primary side wire W1becomes the input voltage Vin, and a negative voltage (−n1*Vin) acquired by multiplying a turn ratio n1to the input voltage Vin is generated as a voltage Vw (hereinafter, referred to as an auxiliary voltage) of the auxiliary wire W3.

When the power switch M1is in the turn-off state, a voltage of the secondary side wire W2becomes a voltage acquired by adding a forward voltage VF of the diode D1to the output voltage Vo. The auxiliary voltage VA becomes a positive voltage positive voltage (Vo+VF)*n2that is acquired by multiplying a turn ratio n2to a voltage of the secondary side wire W2. The forward voltage VF is a very low voltage compared to the output voltage Vo, and the auxiliary voltage VA is substantially Vo*n2. Thus, the sense voltage VS2is Vo*n2*RS6/(RS5+RS6).

The switch control circuit12generates the gate voltage VG1according to the sense voltage CS1and the sense voltage VS2. For example, when the sense voltage CS1reaches a feedback voltage, the switch control circuit12turns off the power switch M1and may generate the feedback voltage using the sense voltage VS2.

The mode voltage generator120according to the third exemplary embodiment further includes the sampling/holder109compared to the previous exemplary embodiments.

The sampling/holder109receives the sense voltage VS2through a sense pin SP2, and samples and holds the sense voltage VS2of the turn-off period of the power switch M1. For example, the sampling/holder109samples and holds the sense voltage VS2of the turn-off period of the power switch M1for every switching period. In detail, the sampling/holder109may sample the sense voltage VS2at an instant that no current flows to the diode D1during the turn-off period of the power switch M1, and may hold the sampled voltage.

When the held voltage reaches a voltage (α*Vclp), the comparator101outputs a high level. The XNOR gate102outputs a low level according to the output of the comparator101and a low-level mode signal, which is in a disable state. Then, the first connection switch S1is turned off and the second connection switch S2is turned on.

Then, the sense pin SP2is connected to the clamping circuit105, and the sense voltage VS2is clamped to a clamping voltage Vclp. A clamping current Iclp flows through the clamping circuit105and then mirrored by a current mirror circuit103such that a mirror current IM1is generated. Then, a mode voltage VRM is generated as given in Equation 2.

The operation mode distinction circuit200receives the mode voltage VRM, and generates a plurality of mode signals mode1to mode4, which are examples of the plurality of mode selection signals. The operation mode distinction circuit200transmits a mode signal enabled by the mode voltage VRM to an input terminal of the XNOR gate102. A detailed structure of the operation mode distinction circuit200is the same as that of second exemplary embodiment, and therefore no further description will be provided.

When mode selection is finished and thus one of the mode signals mode1to mode4is enabled, all input of the XNOR gate102become high levels so that the first connection switch S1is turned on and the second connection switch S2is turned off.

The power supply of the third exemplary embodiment is implemented as a flyback converter, but the third exemplary embodiment is not limited thereto. A different type of power supply is provided in a fourth exemplary embodiment.

FIG. 4shows a power supply according to a fourth exemplary embodiment.

As shown inFIG. 4, a power supply3includes a power switch M2, an inductor L1, an output capacitor Co2, and a diode D2. A switch control circuit13includes an IC internal block303and a mode selection circuit410.

A drain of the power switch M2is connected to an input voltage, and the power switch M2performs switching operation according to a gate voltage VG2. A source of the power switch M2is connected to a first end of a sense resistor RCS2and a second end of the sense resistor RCS2is connected to a ground. A first end of the inductor L1is connected to the second end of the sense resistor RCS2and a second end of the inductor L1is connected to a first electrode of an output capacitor Co2. An anode of the diode D2is connected to a second electrode of the output capacitor Co2. A cathode of the diode D2, the second end of the sense resistor RCS2, and the first end of the inductor L1are connected to the ground. A voltage between lateral ends of the output capacitor Co2is an output voltage Vo.

A sense pin SP3of the switch control circuit13is connected to a sense voltage VS3generated by resistance-dividing the output voltage Vo. A resistor RS7and a resistor RS8are connected in series between the output voltage Vo and the ground.

When the power switch M2is turned on, a switch current Ids1flows to the inductor L1and energy is stored in the inductor L1. The switch current Ids1passed through the inductor L1flows to the ground through the resistor RS7and the resistor RS8. When the power switch M2is turned off, the diode D2is conductive, and thus a current of the inductor L1is supplied to a load (not shown) or flows to the ground through the output capacitor Co2and the diode D2by the energy stored in the inductor L1.

During a turn-on period of the power switch M2, a switch current Ids1flows to the resistor RCS2, and a sense voltage VCS2which is a voltage at a first end of the resistor RCS2is supplied to the switch control circuit13. During a turn-off period of the power switch M2, a sense voltage VS3that depends on the output voltage Vo is input to the sense pin SP3.

The switch control circuit13generates a gate voltage VG2according to the sense voltage CS2and the sense voltage VS3. For example, when the sense voltage CS2reaches the feedback voltage, the switch control circuit13turns off the power switch M2and may generate the feedback voltage using the sense voltage VS2.

The sampling/holder109receives the sense voltage VS3through the sense pin SP3, and samples and holds the sense voltage VS3of the turn-off period of the power switch M2. For example, the sampling/holder109samples and holds the sense voltage VS3of the turn-off period of the power switch M2for every switching period. In detail, the sampling/holder109may sample the sense voltage VS3at an instant that no current flows to the diode D2during the turn-off period of the power switch M2, and may hold the sampled voltage.

When the held voltage reaches a voltage (α*Vclp), the comparator101outputs a high level. The XNOR gate102outputs a low level according to the output of a comparator101and a low-level mode signal, which is in a disable state. Then, the first connection switch S1is turned off and the second connection switch S2is turned on.

Then, the sense pin SP3is connected to the clamping circuit105, and the sense voltage VS3is clamped to a clamping voltage Vclp. A clamping current Iclp flows through the clamping circuit105and then mirrored by a current mirror circuit103such that a mirror current IM1is generated. Then, a mode voltage VRM is generated as given in Equation 2.

The operation mode distinction circuit200receives the mode voltage VRM, and generates a plurality of mode signals mode1to mode4, which are examples of the plurality of mode selection signals. The operation mode distinction circuit200transmits a mode signal enabled by the mode voltage VRM to an input terminal of the XNOR gate102. A detailed structure of the operation mode distinction circuit200is the same as that of second exemplary embodiment, and therefore no further description will be provided.

When mode selection is finished and thus one of the mode signals mode1to mode4is enabled, all input of the XNOR gate102become high levels so that the first connection switch S1is turned on and the second connection switch S2is turned off.

Then, the sense voltage VS3is input to an IC internal block303, and the IC internal block303generates a feedback voltage according to the sense voltage VS3, and when the sense voltage CS2reaches the feedback voltage, the power switch M2is turned off.

A voltage for mode selection is not limited to the sense voltages of first to fourth exemplary embodiments. A voltage different from the sense voltages of first to fourth exemplary embodiments may be used for mode selection. Any voltage higher than a predetermined level (e.g., α*Vclp) during a predetermined period may be used as a sense voltage for mode selection.

A mode selection circuit according to a fifth exemplary embodiment may uses a line voltage for mode selection. The line voltage is a voltage rectified from an AC input and follows on a sine wave. One cycle of the line voltage is very long compared to one power switching cycle, and therefore the line voltage is higher than a predetermined level (e.g., α*Vclp) during a predetermined period (e.g., several switching cycles of the power switch).

FIG. 5shows a switch control circuit according to the fifth exemplary embodiment.

A switch control circuit14includes an IC internal block305and a mode selection circuit400.

As shown inFIG. 5, two resistors RS9and RS10are connected in series between a line voltage Vline and a ground. A node where the two resistors RS9and RS10are connected is connected to a sense pin SP4, and a voltage at the node is a sense voltage VS4.

When the sense voltage VS4reaches a voltage (α*Vclp), a comparator101outputs a high level. An XNOR gate102outputs a low level according to the output of the comparator101and a low-level mode signal which is in a disable state. Then, a first connection switch S1is turned off and a second connection switch S2is turned on.

Then, the sense pin SP4is connected to a clamping circuit105, and the sense voltage VS4is clamped to a clamping voltage Vclp. A clamping current Iclp flows through the clamping circuit105and mirrored by a current mirror circuit103such that a mirror current IM1is generated. Then a mode voltage VRM is generated as given in Equation 2.

The operation mode distinction circuit200receives the mode voltage VRM, and generates a plurality of mode signals mode1to mode4which are examples of mode selection signals. The operation mode distinction circuit200transmits a mode signal enabled by the mode voltage VRM to an input terminal of the XNOR gate102. A detailed structure of the operation mode distinction circuit200is the same as that of the second exemplary embodiment, and therefore no further description will be provided.

When a mode is selected and one of the mode signals mode1to mode4is enabled, all inputs of the XNOR gate102become high levels so that the first connection switch S1is turned on and the second connection switch S2is turned off.

Then, the sense voltage VS4is input to the IC internal block305and the IC internal block305senses the line voltage Vline according to the sense voltage VS4.

In the first to fifth exemplary embodiments, mode selection is performed through the sense pin, but an exemplary embodiment is not limited thereto.

Instead of using the sense pin, a gate pin to which a gate voltage is supplied may be used for mode selection.

A power supply4includes a power switch M3, a primary side wire W11, a secondary side wire W21, a diode D3, an output capacitor Co3, a resistor Rg, and a switch control circuit15.

An input voltage Vin is connected to a first end of the primary side wire W11and a second end of the primary side wire W11is connected to a drain of the power switch M3. A first end of the secondary side wire W21is connected with an anode of the diode D3, and a cathode of the diode D3is connected to an output voltage Vo. An output capacitor Co is connected between the output voltage Vo and a secondary ground.

A source of the power switch M3is connected to a primary ground, a gate of the power switch M3is connected to a gate pin GP and performs switching operation by a gate voltage VG3supplied from the switch control circuit15. The resistor Rg is connected between the gate pin GP and the primary ground.

The switch control circuit15includes the gate pin GP and generates the gate voltage VG3.

FIG. 7shows a switch control circuit according to a sixth exemplary embodiment.

A switch control circuit15includes a mode selection circuit500, a transistor T1, and a transistor T2.

The transistor T1and the transistor T2has a push-pull structure, and operates according to a gate control signal VGC. A source of the transistor T1is connected to a voltage Vdd, a drain of the transistor T1and a drain of the transistor T2are connected with each other, and a source of the transistor T2is connected to the primary side ground. The gate control signal VGC is input to a gate of the transistor T1and a gate of the transistor T2.

When the transistor T2is turned on according to a high-level gate control signal VGC, the gate voltage VG3becomes low level so that the power switch M3is turned off, and when the transistor T1is turned on according to a low-level gate control signal VGC, the gate voltage VG3becomes high level so that the power switch M3is turned on.

The mode selection circuit500generates a mode voltage VRM3by mirroring a current supplied to the resistor Rg, and selects a mode according to the mode voltage VRM3. The mode selection circuit500includes a current mirror circuit133, a resistor RM3, and an operation mode distinction circuit200. The operation mode distinction circuit200has the same structure of the operation mode distinction circuit of the previous exemplary embodiments.

The current mirror circuit133includes a current sensing unit131and a current source132. A current Ig1flowing through the current sensing unit131is mirrored with a predetermined mirror ratio and then transmitted to the current source132, and the current source132generates a mirror current IM3. The mirror current IM3flows to the resistor RM3so that the mode voltage VRM3is generated.

The operation mode distinction circuit200selects a mode according to the mode voltage VRM3.

The current Ig1flows to the primary side ground through the resistor Rg when the gate pin GP is connected to the voltage Vdd as the transistor T1is turned on. That is, the current Ig1is Vdd/Rg. Thus, the current Ig1can be controlled by controlling the resistor Rg, and therefore the mode voltage VRM3can be controlled by controlling the resistor Rg. That is, a mode can be selected by controlling the resistor Rg.

FIG. 8shows a switch control circuit according to a seventh exemplary embodiment.

A switch control circuit16shown inFIG. 8may be applied to the power supply ofFIG. 6.

The switch control circuit16includes a current source141, a transistor T3, and an operation mode distinction circuit200.

The current source141generates a current Ig2using the voltage Vdd. The transistor T3is connected to the current source141and a primary side ground, and performs switching operation according to a gate control signal. A gate voltage VG3is determined according to the gate control signal VGC supplied to a gate of the transistor T3.

When the transistor T3is turned on by a high-level gate control signal VGC, the gate voltage VG3becomes low level and the power switch M3is turned off. When the transistor T3is turned off by a low-level gate control signal VGC, a current Ig2flows to the resistor Rg so that the gate voltage VG3becomes a level of Ig2*Rg and the power switch M3is turned off.

The operation mode distinction circuit200selects a mode according to the gate voltage VG3. Since a level of the gate voltage VG3is determined according to the resistor Rg, the mode can be selected by controlling the resistor Rg.

In the above-described exemplary embodiments, the element connected to the multi-pin and the element generating the mode voltage are described as resistors, but the exemplary embodiments are not limited thereto. Instead of using a resistor, an active element such as a capacitor may be used.

FIG. 9shows a switch control circuit according to an eighth exemplary embodiment.

Compared to the first exemplary embodiment shown inFIG. 1, capacitors C1, C2, and C3may be used instead of using resistors RS1, RS2, and RN.

A voltage at a node NC is divided through two capacitors C1and C2that are connected in series and a sense voltage VS5is connected to a sense pin SP5.

As shown inFIG. 9, the switch control circuit15includes a mode selection circuit and an IC internal block300. The mode selection circuit420includes a mode voltage generator140and an operation mode distinction circuit200.

The mode voltage generator140generates a mirror current IM2by mirroring a clamping current Iclp1generated when the sense voltage VR5supplied through the sense pin SP5is clamped. The capacitor C3is charged by the mirror current IM2so that a mode voltage VRM1is generated.

When the two serially-connected capacitors C1and C2respectively control their capacitances, the sense voltage VS5is changed. That is, the mode voltage VRM1can be controlled by controlling capacitance of each of the two serially-connected capacitors C1and C2.

Other descriptions are the same as the descriptions of the previous exemplary embodiments, and therefore no detailed description will be provided.

Instead of using the resistor Rg shown inFIG. 7andFIG. 8, a capacitor may be connected. Then, in the sixth exemplary embodiment shown inFIG. 7, a current charging the capacitor according to the voltage Vdd is mirrored so that the mode voltage VRM3can be generated. In addition, in the seventh exemplary embodiment shown inFIG. 8, the gate voltage VG3generated when the capacitor is charged by the current Ig2may be input as a mode voltage to the operation mode distinction circuit200.

DESCRIPTION OF SYMBOLS

10,11,12,13,14,15,16: switch control circuit400,410,420: mode selection circuit100,120,140: mode voltage generator200: operation mode distinction circuit300,302,303,305: IC internal block