Wrap-around contact plug and method manufacturing same

A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.

BACKGROUND

In the manufacturing of integrated circuits, contact plugs are used for connecting to the source and drain regions and the gates of transistors. The source/drain contact plugs are typically connected to source/drain silicide regions, which are formed by depositing a metal layer, and then performing an anneal to react the metal layer with the silicon of the source/drain regions. A wet etch is then performed to remove the un-reacted portion of the metal layer.

DETAILED DESCRIPTION

A transistor with contact structures and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages in the formation of the transistors are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS. 1 through 10Eillustrate the cross-sectional views of intermediate stages in the formation of transistors in accordance with some embodiments of the present disclosure. The steps shown inFIGS. 1 through 10Eare also reflected schematically in the process flow shown inFIG. 19.

FIG. 1illustrates a perspective view of an initial structure. The initial structure includes wafer10, which further includes substrate20. Substrate20may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. Substrate20may be doped with a p-type or an n-type impurity. Isolation regions22such as Shallow Trench Isolation (STI) regions are formed to extend from a top surface of substrate20into substrate20. The portions of substrate20between neighboring STI regions22are referred to as semiconductor strips24. In accordance with some embodiments of the present disclosure, semiconductor strips24are parts of the original substrate20, and hence the material of semiconductor strips24is the same as that of substrate20.

In accordance with alternative embodiments of the present disclosure, semiconductor strips24are replacement strips formed by etching the portions of substrate20between STI regions22to form recesses, and performing an epitaxy to regrow another semiconductor material in the recesses. Accordingly, semiconductor strips24are formed of a semiconductor material different from that of substrate20. In accordance with some exemplary embodiments, semiconductor strips24are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material. In accordance with some embodiments of the present disclosure, portions24A of semiconductor strips24are replaced with a semiconductor material different from the material of bottom portions24B. For example, portions24A may be formed of silicon germanium, silicon carbon, or the like. The bottom portions24B are portions of the original substrate20, and are formed of the same semiconductor material (such as silicon) as the underlying bulk portions of substrate20.

STI regions22may include a liner oxide (not shown), which may be a thermal oxide formed through thermal oxidation of a surface layer of substrate20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI regions22may also include a dielectric material over the liner oxide, and the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, or the like.

STI regions22are recessed, so that some top portions24′ of semiconductor strips24protrude higher than the top surfaces22A of the remaining portions of STI regions22. The respective step is illustrated as step202in the process flow200shown inFIG. 19. Throughout the description, the top portions24′ are alternatively referred to as semiconductor fins24′ or protruding fins24′. The etching may be performed using a dry etching process, wherein a mixture of HF3and NH3is used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of STI regions22is performed using a wet etch process. The etching chemical may include HF, for example.

Referring toFIG. 2, dummy gate stacks30are formed. The respective step is illustrated as step204in the process flow shown inFIG. 19. The formation of dummy gate stacks30includes forming dummy gate dielectric layer32, and a dummy gate electrode layer over dummy dielectric layer32. The dummy gate electrode layer is patterned to form dummy gate electrodes34. Throughout the description, dummy gate electrodes34and the underlying portions of dummy gate dielectric layer32are in combination referred to as dummy gate stacks30. Dummy gate electrodes34may be formed, for example, using polysilicon, and other materials may also be used. Dummy gate stacks30may include one or more mask layers (not shown), which may be formed of silicon nitride, silicon oxide, silicon carbo-nitride, or multi-layers thereof. Dummy gate stacks30may cross over a single one or a plurality of protruding fins24′ and/or STI regions22. Dummy gate stacks30also have lengthwise directions perpendicular to the lengthwise directions of protruding fins24′. After the patterning of the dummy gate electrode layer, dummy gate dielectric layer32is exposed, and covers the sidewalls and the top surfaces of protruding fins24′.

Next, an etch step is performed, and the exposed portions of dummy gate dielectric layer32are removed, as shown inFIG. 3. Gate spacers38are formed on the sidewalls of dummy gate stacks30. In accordance with some embodiments of the present disclosure, gate spacers38are formed of a dielectric material such as silicon nitride, silicon carbo-nitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

Next, source/drain regions are formed. In according with some embodiments of the present disclosure, the source/drain regions are formed as cladding source/drain regions, as shown inFIG. 4, in which epitaxy semiconductor regions42(including42A and42B) are epitaxially grown on the exposed protruding fins24′. The respective step is illustrated as step206in the process flow shown inFIG. 19. Epitaxy regions42A and42B represent the epitaxy regions for forming different types of FinFETs. Depending on whether the resulting FinFETs is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, epitaxy regions42A may include silicon germanium boron (SiGeB), and the resulting FinFET is a p-type FinFET. Epitaxy regions42B may include silicon phosphorous (SiP) or silicon carbon phosphorous (SiCP), and the respective resulting FinFET is an n-type FinFET. In accordance with alternative embodiments of the present disclosure, epitaxy regions42are formed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof. When epitaxy regions42A and42B are formed of different materials, they are formed in different epitaxy processes, and the corresponding masks (not shown) are used to allow the epitaxy occurs on one of epitaxy regions42A and42B, but not on the other.

In accordance with alternatively embodiments, instead of directly growing epitaxy regions on protruding fins24′, an etching step (referred to as source/drain recessing hereinafter) is performed to etch the portions of protruding fins24′ that are not covered by dummy gate stack30and gate spacers38, so that recesses are formed. Epitaxy regions42are then grown from recesses. Exemplary resulting epitaxy regions42are shown inFIG. 6E.

An implantation step(s) may be performed to implant the desirable p-type or n-type impurity such as boron or phosphorous into protruding fins24′ and epitaxy regions42A and42B. The protruding fins24′ and the corresponding epitaxy regions42A and42B in combination are referred to as source/drain regions44. In accordance with alternative embodiments of the present disclosure, the implantation step is skipped when epitaxy regions42are in-situ doped with the p-type or n-type impurity.

FIG. 5illustrates a perspective view of the structure after the formation of Contact Etch Stop Layer (CESL)46and Inter-Layer Dielectric (ILD)48. The respective step is illustrated as step208in the process flow shown inFIG. 19. CESL46may not be formed in accordance with some embodiments of the present disclosure, and when formed, may be formed of silicon nitride, silicon carbo-nitride, or the like. In accordance with some embodiments of the present disclosure, CESL46is free from oxygen therein. CESL46may be formed using a conformal deposition method such as ALD or CVD, for example. ILD48may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. ILD48may also be formed of an oxygen-containing dielectric material, which may be silicon-oxide based such as Tetra Ethyl Ortho Silicate (TEOS) oxide, Plasma-Enhanced CVD (PECVD) oxide (SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like. A planarization step such as Chemical Mechanical Polish (CMP) or mechanical grinding may be performed to level the top surfaces of ILD48, dummy gate stacks30(FIG. 4), and gate spacers38with each other.

After the formation of CESL46and ILD48, the dummy gate stacks30as shown inFIG. 4are replaced with replacement gate stacks50as shown inFIG. 5. The respective step is illustrated as step210in the process flow shown inFIG. 19. The formation of replacement gate stacks50includes performing etching steps to remove dummy gate stacks30(FIG. 4), forming one or more gate dielectric layer, depositing a plurality of conductive layers such as metal layers, and performing a planarization such as CMP or mechanical grinding to remove excess portions of the gate dielectric layer and the metal layers. The resulting replacement gate stack50includes gate dielectric52and gate electrode54, as shown inFIG. 5.

In accordance with some embodiments of the present disclosure, gate dielectric52includes an Interfacial Layer (IL, not shown separately) as its lower part. The IL is formed on the surfaces of protruding fins24′. The IL may include an oxide layer such as a silicon oxide layer, which is formed through the thermal oxidation of protruding fins24′, a chemical oxidation process, or a deposition process. Gate dielectric52may also include a high-k dielectric layer (not shown separately) over the IL. The high-k dielectric layer includes a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0. The high-k dielectric layer is formed as a conformal layer, and extends on the sidewalls of protruding fins24′ and the sidewalls of gate spacers38. In accordance with some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD or CVD.

Gate electrode54may include a diffusion barrier layer and one (or more) work-function layer over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work-function layer determines the work function of the gate, and includes at least one layer, or a plurality of layers formed of different materials. The material of the work-function layer is selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work-function layer may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work-function layer may include a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. After the deposition of the work-function layer(s), a barrier layer, which may be another TiN layer, is formed. Gate electrode54may also include a filling metal, which may be formed of aluminum, tungsten, or cobalt.

After the formation of replacement gate stacks50, gate stacks50are recessed, followed by filling hard masks56into the resulting recesses. Hard masks56are formed of a dielectric material such as silicon nitride. A planarization step is performed to level the top surface of hard masks56with ILD48.

After the formation of replacement gates50and hard masks56, CESL46and ILD48are removed, for example, through etching. The respective step is illustrated as step212in the process flow shown inFIG. 19. The resulting structure is shown inFIG. 6A. In accordance with some embodiments of the present disclosure, the etching is performed to remove all CESL46and ILD48throughout wafer10. Accordingly, in the etching, there is no mask formed to protect some portions of CESL46and ILD48. Epitaxy regions42are exposed as a result of the removal of CESL46and ILD48.

FIGS. 6B, 6C, 6D, and 6Eillustrate the cross-sectional views of some portions of the structure shown inFIG. 6A. ThroughoutFIGS. 6A through 10E, each of the figure numbers may include letter “A,” “B,” “C,” “D,” or “E.” Letter “A” indicates that the respective figure is a perspective view, and letters “B,” “C,” “D,” and “E” indicate that the corresponding figures illustrate the cross-sectional views of the structure shown in the respective perspective view. The cross-sectional views shown in Figures with letter “B” are obtained from the plane same as the vertical plane containing line A-A inFIG. 6A, which vertical plane cuts through semiconductor strips24and protruding fin24′. Also, letters “C,” “D,” and “E” indicate that the respective figures are obtained from the plane same as the vertical plane containing line B-B in the respective perspective view. Furthermore, letters “C,” “D,” and “E” indicate that the respective figures reflective different embodiments.

Referring toFIG. 6B, the top surface22A of STI regions22(not in the illustrated plane) is illustrated, and protruding fin24′ will be higher than top surface22A. The detailed structure of source/drain regions44may be found inFIGS. 6C, 6D, and6E, which illustrate the structures of source/drain regions44in accordance with various embodiments.

FIG. 6Cillustrates the cross-sectional view of cladding source/drain regions44, which include epitaxy semiconductor regions42grown on protruding fins24′. In accordance with some embodiments of the present disclosure, protruding fins24′ are the remaining portions of the original substrate, and hence the material of protruding fins24′ is the same as the material of the underlying bulk portion of substrate20.

FIG. 6Dillustrates the cross-sectional view of cladding source/drain regions44, which include epitaxy semiconductor regions42grown on protruding fins24′. In accordance with some embodiments of the present disclosure, protruding fins24′ are re-grown from the original substrate, and hence the material of protruding fins24′ is different from the material of the underlying bulk portion of substrate20. The re-grown semiconductor material, which are re-grown from the recesses formed between STI regions, are marked as semiconductor regions25.

FIG. 6Eillustrates the cross-sectional view of regrown source/drain regions44, which include epitaxy semiconductor regions42grown from the recesses formed after etching protruding fins. The resulting source/drain regions44may include facets. In accordance with some embodiments, replacement fins are formed, as shown as semiconductor regions25, and are recessed again. Accordingly, epitaxy regions42are grown from semiconductor regions25.

FIGS. 7A through 9Eillustrate the perspective views and cross-sectional views in the formation of source/drain silicide regions and metal nitrides in accordance with some embodiments. The steps shown inFIGS. 7A through 9Emay be performed in a same production tool such as a deposition tool, and may be performed in a same vacuum environment in the production tool. For example,FIG. 18schematically illustrates vacuum chamber60in deposition tool61. Vacuum chamber60can be vacuumed to provide a vacuum environment. Chuck62is located in vacuum chamber60. Wafer10is placed on chuck62in order to perform the steps shown inFIGS. 7A through 9E. The steps shown inFIGS. 7A through 9Emay be performed with no vacuum break occurring during the period of time starting at the time the step shown inFIG. 7Ais started and ending at the time the step shown inFIG. 9Ais ended. By maintaining the vacuum during these process steps, the exposed features such as semiconductor regions and metal regions do not suffer from oxidation. Accordingly, there is no need to remove the (non-existent) oxide.

After wafer10is placed into the production tool (FIG. 18), a vacuum environment is formed by vacuuming vacuum chamber60inFIG. 18(or a cluster system including a plurality of vacuum chambers sharing a common vacuum environment). A cleaning step is then performed, which is referred to as in-situ cleaning. The in-situ cleaning step removes the undesirable oxide formed on the surface of source/drain regions44, which are shown inFIGS. 6A, 6B, 6C, 6D, and 6E. The removed oxide may be silicon oxide, silicon-germanium oxide, or the like, depending on the material of sourced/drain regions44. In accordance with some embodiments of the present disclosure, the cleaning is performed using a mixture of process gases including NF3and NH3, or a mixture of HF and NH3.

After the cleaning step, an in-situ selective deposition is performed in the same vacuum environment as the cleaning step. The respective step is illustrated as step214in the process flow shown inFIG. 19. Accordingly, after the cleaning, no new oxide is generated on the surfaces of source/drain regions44. The resulting structure is shown inFIGS. 7A, 7B, 7C, 7D, and 7E. In accordance with some embodiments of the present disclosure, the in-situ selective deposition is performed using process gases including a metal halide (such as TiCl4) and hydrogen (H2). In accordance with some embodiments of the present disclosure, the flow rate of TiCl4is in the range between about 5 sccm and about 15 sccm, and the flow rate of hydrogen is in the range between about 30 sccm and about 70 sccm. The power may be in the range between about 200 Watts and about 500 Watts. The deposition temperature may be in the range between about 400° C. and about 500° C. The selective deposition may last between about 40 seconds and about 60 seconds, depending on the desirable thickness of the deposited layers. During the selective deposition, plasma is turned on.

The selective deposition is selective since on source/drain regions44, what are deposited is metal silicide layer64, which is formed as a result of the deposition of metal and the silicide reaction of the metal and surface layers of source/drain regions44. This is due to the appropriate process conditions including the elevated deposition temperature and appropriate deposition rate. On the other hand, on the surfaces of dielectric layers including gate spacers38, hard masks56, and STI regions22, a metal layer (such as titanium layer)66is formed, which is not silicided. The formation of metal silicide layer64and the formation of metal layer66are concurrent. In accordance with some embodiments of the present disclosure, metal silicide layer64has thickness T1in the range between about 2 nm and about 8 nm, and thickness T2of metal layer66is in the range between about 0.5 nm and about 5 nm. The formation method may include Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like.

FIGS. 7B, 7C, 7D, and 7Eillustrate the cross-sectional views of source/drain regions44and metal silicide layer64in accordance with various embodiments. Metal silicide layer64is formed on the top surface and the sidewalls of source/drain regions44. The shapes of metal silicide layer64depend on the shapes of the underlying source/drain regions44. On the top surface of STI regions22, there may be some small and thin portions of metal layer66formed. The thicknesses of these portions of titanium66are not uniform.

After the in-situ selective deposition, an in-situ selective etching step is performed in the same vacuum environment as the in-situ selective deposition. The respective step is illustrated as step216in the process flow shown inFIG. 19. The resulting structure is shown inFIGS. 8A, 8B, 8C, 8D, and 8E. In accordance with some embodiments of the present disclosure, the in-situ selective etching is performed using etching gases including a metal halide (such as TiCl4), hydrogen (H2), and argon. It is noted that the metal halide in the etching gas may be changed to different halides (or metal halides) if metal layer66is formed of other metals other than titanium. For example, HCl may be used in accordance with some embodiments. In accordance with some embodiments of the present disclosure, the flow rate of TiCl4is in the range between about 20 sccm and about 30 sccm, the flow rate of hydrogen is in the range between about 1,100 sccm and about 1,500 sccm, and the flow rate of argon is in the range between about 1,100 sccm and about 1,500 sccm. Wafer10is heated during the selective etching, and the temperature of the wafer may be in the range between about 400° C. and about 500° C. During the selective etching, plasma may be turned off.

During the selective etching, metal layer66as shown inFIGS. 7A and 7Bis etched. Metal silicide layer64, on the other hand, is not etched. As a result, gate spacers38and hard masks56are exposed again.

In accordance with some embodiments, the process gases for the selective deposition and the selective etching are common. For example, TiCl4and hydrogen may be used in both the selective deposition and the selective etching. In accordance with these embodiments, plasma may be turned on to result in the selective deposition, while the plasma may be turned off to result in the selective etching. Also, process conditions such as flow rates of the process gases are changed between the selective deposition and the selective etching.

FIGS. 8B, 8C, 8D, and 8Eillustrate the cross-sectional views of source/drain regions44and metal silicide layer64. In accordance with some embodiments of the present disclosure, all of the metal layer66on the top surfaces of STI regions22are removed. In accordance with alternative embodiments, the thicker portions (refer toFIGS. 7C, 7D, and 7E) of metal layer66may have some residue portions left the top surfaces of STI regions22. The residue portions, however, are discontinuous, and hence will not affect the electrical performance of the resulting FinFET.

After the selective etching, an in-situ nitridation is performed in the same vacuum environment as the selective etching step. The respective step is illustrated as step218in the process flow shown inFIG. 19. The resulting structure is shown inFIGS. 9A, 9B, 9C, 9D, and 9E. In accordance with some embodiments of the present disclosure, the in-situ nitridation is performed using a nitrogen-containing process gas such as ammonia (NH3). In accordance with some embodiments of the present disclosure, the flow rate of ammonia is in the range between about 3,000 sccm and about 5,000 sccm. The power may be in the range between about 400 Watts and about 600 Watts. The deposition temperature may be in the range between about 400° C. and about 500° C. The nitridation may last between about 15 seconds and about 25 seconds, depending on the desirable thickness of the nitride layer and the thickness of metal silicide layer64.

The selective nitridation results in a top surface layer of metal silicide layer64to be nitridated to form metal silicon nitride layer68, which may be a titanium silicon nitride (TiSiN) layer. The bottom layer of metal silicide layer64remains not nitridated, and is free from nitrogen. In accordance with some embodiments of the present disclosure, the remaining metal silicide layer64has thickness T1′ in the range between about 2 nm and about 7 nm, and thickness T3of titanium silicon nitride layer68is in the range between about 1 nm and about 3 nm. It is observed that since titanium silicon nitride layer68is formed by nitridating titanium silicide layer64, metal silicon nitride layer68is formed on metal silicide layer64, but not on dielectric materials such as STI regions22, gate spacers38, and hard masks56.

FIGS. 10A, 10B, 10C, 10D, 10D, and 10Eillustrate the formation of CESL70, ILD72, and contact plugs74. The respective step is illustrated as steps220and222in the process flow shown inFIG. 19. FinFET76is thus formed. The formation of CESL70and ILD72may include forming a blanket CESL layer throughout wafer10and extending into the gaps between gate spacers38, filling the remaining gaps with ILD72, and performing a planarization such as CMP or mechanical grinding. CESL70may be formed of a material selected from the same group of candidate materials for forming CESL46(FIG. 5), and ILD72may be formed of a material selected from the same group of candidate materials for forming ILD48(FIG. 5). CESL70is a conformal layer, which may be formed through, for example, ALD. Accordingly, CESL70wraps around all exposed surfaces in the gaps.

ILD72and CESL70are then etched to form contact openings (filled by contact plugs74as shown inFIGS. 10A, 10B, 10C, 10D, and 10E). Accordingly, metal silicon nitride layer68is exposed to the contact openings. Next, the contact openings are filled with a conductive material to form contact plugs74. In accordance with some embodiments of the present disclosure, the formation of contact plugs74includes blanket depositing a conformal barrier layer (not shown separately) extending into the contact openings, and depositing a metallic material over the barrier layer and filling the remaining contact openings. The barrier layer may be formed of titanium nitride or tantalum nitride. The metallic material may be formed of cobalt, tungsten, aluminum, or the like. A planarization is then performed to remove excess portions of the barrier layer and the metallic material. In accordance with alternative embodiments, contact plugs74include the metallic material such as cobalt, tungsten, aluminum, and do not include the barrier layer.

FIGS. 10B, 10C, 10D, and 10Eillustrate the cross-sectional views of CESL70, ILD72, and contact plugs74in accordance with some embodiments. As shown inFIGS. 10B, 10C, 10D, and 10E, metal silicide regions64and metal silicon nitride layer68wrap around the respective source/drain regions44, while contact plugs74are in contact with the top surfaces of some portions, but not all, of the corresponding metal silicon nitride layer68.

In the embodiments shown inFIGS. 1 through 10E, metal silicide regions64and metal silicon nitride layer68are formed before the formation of CESL70and ILD72. CESL46and ILD48(FIG. 5), on the other hand, are sacrificial features that are removed from the final structure. In accordance with alternative embodiments, metal silicide regions64and metal silicon nitride layer68may be formed after the formation of CESL46and ILD48, which are left in the final structure.FIGS. 11 through 16illustrate the perspective views and cross-sectional views of intermediate stages in the formation of a transistor in accordance with these embodiments of the present disclosure. Unless specified otherwise, the materials and the formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments shown inFIGS. 1 through 10E. The details regarding the formation process and the materials of the components shown inFIGS. 11 through 16may thus be found in the discussion of the embodiment shown inFIGS. 1 through 10E.

The initial steps of these embodiments are essentially the same as shown inFIGS. 1 through 5.FIG. 11illustrates a resulting structure (the same structure as inFIG. 5) as an example, wherein CESL46and ILD48are formed to cover source/drain regions44. It is appreciated that the source/drain regions44may have various structures such as what are shown inFIGS. 6C, 6D, and 6E. Next, referring toFIG. 12, contact openings78are formed by etching ILD48and CESL46. Source/drain regions44are thus exposed.

In accordance with alternative embodiments of the present disclosure, instead of growing source/drain regions44to a level higher than the top surface of protruding fins24′, a recess is performed to etch protruding fins24′. Lines27schematically illustrate the top surfaces of the recessed fins24′. An implantation is performed on the recessed fins24′ to form recessed source/drain regions44. In accordance with these embodiments, the epitaxy semiconductor regions42are not formed.

FIGS. 13 through 17illustrate the cross-sectional views of intermediate stages in the selective deposition, selective etching, and selective nitridation in accordance with some embodiments. In accordance with some embodiments of the present disclosure, the process steps shown inFIGS. 13 through 15(and possiblyFIG. 16) are in-situ performed in the same vacuum environment such as the vacuum chamber60as shown inFIG. 18, and there is no vacuum break throughout the entire period for performing these process steps. It is noted thatFIGS. 13 through 17illustrate the cross-sectional views in a vertical plane same as the vertical plane containing line A′-A′ inFIG. 12. The cross-sectional views in the vertical plane B′-B′ (FIG. 12) will be similar to the structures shown in the figures identified with numbers7C/7D/7E,8C/8D/8E, and9C/9D/9E, and hence are not repeated.

Referring toFIG. 13, an in-situ selective deposition is performed to simultaneously form metal silicide layer (which may be a titanium silicide layer)64on the exposed surfaces of source/drain regions44. In accordance with some embodiments, as shown inFIGS. 12 and 13, the epitaxy of semiconductor regions42results in the top surface of metal silicide layer64to be higher than the top surface of protruding fin24′.

In accordance with the embodiments in which epitaxy semiconductor regions42(FIG. 12) are not formed, and protruding fins24′ are recessed to levels27(FIG. 12), the shape of metal silicide layer64will be similar to the regions illustrated with dashed lines67, and metal layer66will further extend down to the bottom end of gate spacers38.

Next, the in-situ selective etching is performed, and hence metal layer66is etched. Metal silicide layer64is left. The resulting structure is shown inFIG. 14.FIG. 15illustrates the in-situ selective nitridation to form metal silicon nitride layer68. In accordance with some embodiments of the present disclosure, an anneal is performed to change the phase of the metal silicide so that the resistance of the resulting metal silicide layer64is reduced. The anneal may also be in-situ performed in the same vacuum chamber for the selective deposition, the selective etching, and the selective nitridation.

After the anneal, a metal nitride layer80, which may be a titanium nitride layer, is deposited, as shown inFIG. 16. In accordance with some embodiments of the present disclosure, the deposition is in-situ performed in the same process chamber (with no vacuum break therebetween) as the selective deposition, the selective etching, the selective nitridation, and the anneal. In accordance with other embodiments of the present disclosure, the deposition of metal nitride layer80is performed after a vacuum break and in a different process chamber. Metal nitride layer80is conformal, and extends into the gap between neighboring gate stacks. The bottom surface of metal nitride layer80contacts metal silicon nitride layer68.

FIG. 17illustrates the filling of the remaining gap with a filling metal82, and a planarization step for removing excess portions of the filling metal82and metal nitride layer80. The filling metal82and metal nitride layer80are in combination referred to as a contact plug, which have a similar shape as shown in10A,10B,10C,10D, and10E.

The embodiments of the present disclosure have some advantageous features. In conventional silicide formation processes, a metal layer is deposited first, followed by an anneal process to form silicide, wherein some portions of the metal layer react with the source/drain regions to form silicide. The unreacted portions of the metal layer are then removed, which may involve wet etching using peroxide. This causes some portions of the metal silicide to be oxidized, and the resulting oxide needs to be removed before forming a metal nitride layer. The removal of the oxide, however, results in the loss of metal silicide, particularly because the metal silicide is typically metal-rich, and hence the property of the metal silicide is close to the metal. In the embodiments of the present disclosure, however, by using the in-situ performed selective deposition, selective etching, and selective nitridation, no oxidation occurs on the metal silicide, and no oxide-removal is needed. The loss of the metal silicide cause by oxide removal is thus avoided.

In accordance with some embodiments of the present disclosure, a method includes forming a source/drain region, and in a vacuum chamber, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber. In an embodiment, the selective deposition and the selectively etching the metal layer are in-situ performed without vacuum break therebetween. In an embodiment, the selectively etching the metal layer and the selectively forming the metal nitride layer are in-situ performed without vacuum break therebetween. In an embodiment, the metal silicide layer and the metal layer are formed simultaneously using same process gases. In an embodiment, the selectively forming the metal nitride layer comprises nitridating a surface layer of the metal silicide layer. In an embodiment, the selective deposition is performed using process gases comprising a metal halide. In an embodiment, the selectively etching is performed using process gases comprising a metal halide. In an embodiment, the selective deposition is performed at an elevated temperature between about 400° C. and about 500° C.

In accordance with some embodiments of the present disclosure, a method includes forming a gate stack over a first portion of a semiconductor fin; epitaxially growing a semiconductor material on a second portion of the semiconductor fin; in a vacuum chamber, simultaneously forming a metal layer and a metal silicide layer, and the metal silicide layer is formed on the semiconductor material; without vacuum break, removing the metal layer; without vacuum break, forming a metal silicon nitride layer on the metal silicide layer; forming a first CESL covering the metal silicon nitride layer; and forming a first inter-layer dielectric over the first CESL. In an embodiment, the method further includes, before the simultaneously forming the metal layer and the metal silicide layer, forming a second CESL and a second inter-layer dielectric covering the semiconductor material; and removing a dummy gate stack over the first portion of the semiconductor fin, wherein the gate stack is formed in a recess left by the dummy gate stack. In an embodiment, the simultaneously forming the metal layer and the metal silicide layer is performed using process gases comprising TiCl4. In an embodiment, the removing the metal layer is performed using additional process gases comprising TiCl4. In an embodiment, the method further includes etching the first CESL and the first inter-layer dielectric to form a contact opening; and filling the contact opening with a contact plug. In an embodiment, the metal layer and the metal silicide layer comprise a titanium layer and a titanium silicide layer, respectively.

In accordance with some embodiments of the present disclosure, a method includes forming a gate stack over a first portion of a semiconductor fin; epitaxially growing a semiconductor material on a second portion of the semiconductor fin; simultaneously forming a metal layer and a metal silicide layer using a first process gas, and the metal silicide layer is formed on the semiconductor material; removing the metal layer using a second process gas, wherein both the first process gas and the second process gas comprise a halide; and forming a metal nitride layer on the metal silicide layer using a third process gas. In an embodiment, each of the first process gas and the second process gas comprises a metal halide. In an embodiment, the first process gas and the second process gas comprise a same metal halide. In an embodiment, the metal layer comprises titanium, and both the first process gas and the second process gas comprise TiCl4. In an embodiment, the forming the metal nitride layer comprises converting a surface layer of the metal silicide layer into a metal silicon nitride layer. In an embodiment, the simultaneously forming the metal layer and the metal silicide layer, the removing the metal layer, and the forming the metal nitride layer are performed in a same process chamber.

In accordance with some embodiments of the present disclosure, a method includes forming a dummy gate stack over a first portion of a semiconductor fin; forming a gate spacer on a sidewall of the dummy gate stack; epitaxially growing a semiconductor material on a second portion of the semiconductor fin; forming a first inter-layer dielectric to cover the semiconductor material; replacing the dummy gate stack with a replacement gate stack; removing the first inter-layer dielectric to re-expose the semiconductor material; in a vacuum chamber, cleaning the semiconductor material; in the vacuum chamber, selectively forming a metal silicide layer on the semiconductor material; and forming a metal silicon nitride layer over the metal silicide layer, and at a time the forming the metal silicon nitride layer is finished, a metal of the metal silicide layer does not extend on the gate spacer. In an embodiment, at a same time the metal silicide layer is formed, a metal layer is formed on the gate spacer. In an embodiment, the method further includes selectively etching the metal layer in the vacuum chamber.

In accordance with some embodiments of the present disclosure, a method includes forming a dummy gate stack over a first portion of a semiconductor fin; forming a gate spacer on a sidewall of the dummy gate stack; epitaxially growing a semiconductor material on a second portion of the semiconductor fin; forming a first inter-layer dielectric to cover the semiconductor material; replacing the dummy gate stack with a replacement gate stack; removing the first inter-layer dielectric to re-expose the semiconductor material; in a vacuum chamber, selectively forming a metal silicide layer on the semiconductor material; and in the vacuum chamber, forming a metal silicon nitride layer over the metal silicide layer, wherein no vacuum break occurs between the selectively forming the metal silicide layer and the forming the metal silicon nitride layer. In an embodiment, the selectively forming the metal silicide layer and the forming the metal silicon nitride layer are performed using a same halide as process gases. In an embodiment, the selectively forming the metal silicide layer and the forming the metal silicon nitride layer are performed using TiCl4as process gases.

In accordance with some embodiments of the present disclosure, a method includes epitaxially growing a semiconductor material on a portion of a semiconductor fin; forming an inter-layer dielectric to cover the semiconductor material; removing the inter-layer dielectric to re-expose the semiconductor material; in a vacuum chamber, selectively forming a metal silicide layer on the semiconductor material; and in the vacuum chamber, nitridating a surface layer of the metal silicide layer to form a metal silicon nitride layer. In an embodiment, the method further includes, between the forming the inter-layer dielectric and the removing the inter-layer dielectric, replacing a dummy gate stack on the portion of the semiconductor fin with a replacement gate stack. In an embodiment, no vacuum break occurs between the selectively forming the metal silicide layer and the nitridating the surface layer of the metal silicide layer. In an embodiment, when the metal silicide layer is formed, a metal layer is formed on dielectric material adjacent to the semiconductor material.