Transistor device with heterogeneous channel structure bodies and method of providing same

Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.

BACKGROUND

1. Technical Field

Embodiments of the present invention generally relate to microelectronic devices and their methods of fabrication, and more particularly, but not exclusively, to layered semiconductor structures of a transistor.

2. Background Art

Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals in the microelectronic industry for the fabrication of microelectronic devices. As these goals are achieved, the microelectronic devices scale down (i.e., become smaller), which increases the need for optimal performance from each integrated circuit component, including managing transistor drive currents while reducing short-channel effects, parasitic capacitance, and off-state leakage.

DETAILED DESCRIPTION

Embodiments discussed herein variously provide techniques and mechanisms for an integrated circuit transistor device to exhibit improved operational characteristics. In an embodiment, a transistor comprises source or drain structures and a channel structure which spans a region which extends between said source or drain structures. A first semiconductor body and a second semiconductor body of the channel structure may comprise different respective semiconductor materials. The first semiconductor body may include a high mobility material which adjoins a gate dielectric layer. In such an embodiment, the second semiconductor body may include a wide bandgap material, portions of which each adjoin a different respective one of the source or drain structures. For example, the first semiconductor body may be between the second semiconductor body and the gate dielectric—e.g., wherein a portion of the second semiconductor body is between the first semiconductor body and one of the source or drain structures. By providing a wide bandgap semiconductor body at a side of the high mobility semiconductor body, some embodiments enable improved gain, switching and/or other performance benefits which are associated with conventional high mobility transistor designs, while also mitigating current leakage which is typically result from such designs.

As used herein, “source or drain structure” (or “SD structure”) refers to a structure which is configured to function as one of a source of a device or a drain of the device. A SD structure may comprise at least a conductive surface which provides a contact electrode that adjoins a semiconductor material. “Channel structure” refers herein to a structure of a device which, during operation of the device, may be used to selectively provide a conductive channel between two SD structures of the device. A contiguous body of one or more semiconductor materials (or “semiconductor structure” herein) may include or function as a channel structure.

As used herein, “back-gate transistor” refers to a transistor which comprises a gate structure that, as compared to a SD structure of that same transistor, is relatively close to an underlying substrate. Such a gate structure may be disposed between the substrate and one or both of a source structure and a drain structure of the transistor. As used herein, “high mobility” refers to the property of a material having a mobility which is equal to or greater than 100 cm2/V·s. “Wide bandgap” refers to the property of a material having a bandgap which is equal to or greater than 2.0 eV.

Certain features of various embodiments are described herein with reference to a back-gate transistor, a channel structure of which comprises portions that each provide a different respective one of a high mobility and a wide bandgap. However, such description may be extended to additionally or alternatively apply to any of a variety of other types of transistors which include a first semiconductor body and second semiconductor body with different respective physical properties.

The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including one or more transistors of an integrated circuit.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Here, multiple non-silicon semiconductor material layers may be stacked within a single fin structure. The multiple non-silicon semiconductor material layers may include one or more “P-type” layers that are suitable (e.g., offer higher hole mobility than silicon) for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more “N-type” layers that are suitable (e.g., offer higher electron mobility than silicon) for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors. The multiple non-silicon semiconductor material layers may be fabricated, at least in part, with self-aligned techniques such that a stacked CMOS device may include both a high-mobility N-type and P-type transistor with a footprint of a single transistor.

FIG. 1shows a portion of an IC device100which includes transistor structures according to an embodiment.FIG. 1also shows a cross-sectional side view104of IC device100, wherein view104corresponds to a x-z plane102of the xyz coordinate system shown. IC device100is one example of an embodiment wherein a semiconductor structure (also referred to herein as a “channel structure”) provides a channel region of a transistor, wherein portions of the semiconductor structure have different mobility and/or bandgap characteristics.

As shown, IC device100includes a substrate110, a dielectric112on substrate110, and a gate structure120disposed in a recess which is formed at least in part by dielectric112. Although structures of IC device100are variously shown as having respective rectilinear geometries, some or all such structures may instead have curved, obliquely angled, tapered and/or otherwise non-rectilinear shapes. Substrate110may be formed of any of a variety of materials that are suitable for use as a substrate of a semiconductor device, and in particular as a substrate for a back-gate (or other) transistor. Non-limiting examples of suitable materials that may be used as substrate110therefore include silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-carbide (SiC), sapphire, a III-V semiconductor, a silicon on insulate (SOI) substrate, combinations thereof, and the like. Without limitation, in some embodiments substrate110is formed from or includes glass or single crystal silicon.

In some embodiments, one or more underlayers (not illustrated) may be deposited on substrate110, e.g., such that they are present between substrate110and one or more of dielectric112and the materials forming gate structure120. For example, one or more semiconductor base layers may be deposited on substrate110. When used, such base layers may be pseudomorphic, metamorphic, or substantially lattice matched buffer and/or transition layers, as understood in the art. In any case, substrate110may be understood to provide an epitaxial seeding surface (e.g., a crystalline surface having a (100) or other suitable orientation) for the subsequent deposition of the materials thereon.

Dielectric112may be formed from any material that is suitable for use as an electrical insulator of a semiconductor device. Non-limiting examples of such materials include oxides, nitrides and alloys, such as but not limited to silicon oxide (SiO2), silicon nitride (SiN), combinations thereof, and the like. Without limitation, in some embodiments dielectric112is SiO2.

Gate structure120may be formed of any of a variety of suitable gate electrode materials. For example, gate structure120may comprise any of a variety of suitable conductors including, but not limited to, one of titanium nitride, tungsten, platinum, iridium, gold, ruthenium, a p-type doped polysilicon, zinc, or gallium. It is to be appreciated that gate structure120need not include a single material and may (for example) be a composite stack of thin films—e.g., wherein the stack forms a polycrystalline silicon/metal electrode or a metal/polycrystalline silicon electrode.

A transistor of IC device100—e.g., a thin film transistor, or “TFT”—may comprise structures which are variously disposed over substrate110(e.g., including structures over dielectric112and/or over gate structure120). For example, as shown in view104, such a transistor may include—in addition to gate structure120—a channel structure130and two source or drain (“SD”) structures140,150each adjoining a respective portion of channel structure130. The transistor may further comprise a layer122which includes a dielectric material to provide at least some electrical insulation between gate structure120and a bottom side of channel structure130. To protect the transistor, an insulator material160(e.g., including silicon dioxide or any of a variety of other dielectric materials) may be variously disposed on or around some or all of SD structures140,150, channel structures130, dielectric112or the like. Connectivity to the transistor may be facilitated with one or more electrodes (e.g., including the illustrative electrodes142,152shown) which extend at least in part through insulator material160. In one example embodiment, electrodes142,152each include copper disposed on a respective layer of tantalum nitride, titanium nitride, pure tantalum, pure titanium, or other such suitable material.

SD structures140,150may include any of a variety of conductors which, for example, are adapted from conventional transistor designs. By way of illustration and not limitation, a conductor of SD structures140,150may include one of tungsten, tantalum nitride, titanium nitride, tantalum silicide, platinum, iridium, ruthenium, or cobalt. A conductive surface of SD structure140may be provided at an interface with channel structure130—e.g., wherein a conductive surface of SD structure150is provided at an interface with channel structure130. For example, channel130may comprise a body134of a semiconductor (or “semiconductor body” herein) which adjoins a silicide, germanide, arsenide, metal or otherwise conductive surface of SD structure140—e.g., wherein semiconductor body134also adjoins a conductive surface of SD structure150. Although some embodiments are not limited in this regard, SD structures140,150may each further comprise a respective semiconductor material—e.g., wherein one or each of SD structures140,150comprises layers having different conductivity properties.

SD structures140,150and channel structure130are configured to conduct current during operation of IC device100—e.g., the current controlled using gate structure120. For example, SD structures140,150may be separated from one another (e.g., along the x-axis shown) by a distance which, in some embodiments, is in a range of 5 nanometers (nm) to 80 nm. Semiconductor body134may extend under and/or along this separation distance to variously adjoin respective portions of SD structures140,150. In such an embodiment, another semiconductor body132of channel structure130may be disposed between semiconductor body134and each of layer122and gate structure120. Operation of IC device100may include an application of voltages at respective ones of SD structures140,150and gate structure120to create a conductive channel in channel structure130.

To mitigate current leakage or otherwise promote efficient transistor performance, some embodiments provide a channel structure which includes both a body of a high mobility semiconductor material and another body of a wide bandgap semiconductor material. For example, as illustrated in view104, the body134of a wide bandgap semiconductor may extend between (and variously adjoins) SD structures140,150. In such an embodiment, at least some of the body132of a high mobility semiconductor may be disposed between body134and layer122. Although some embodiments are not limited in this regard, a portion of body134may be disposed between body132and one of SD structures140,150. For example, each of SD structures140,150may be separated from body132by a respective portion of body134.

Body132may be formed of any of a variety of suitable semiconductor materials including, but not limited to, one of epitaxial (e.g., monocrystalline or polycrystalline) silicon, epi germanium, or epi silicon germanium (SiGe), InP, GaAs, GaN, InGaAs, InGaN, GaAlN, InAlN, or InAs. In some embodiments, body132comprises a Group III-V semiconductor. Alternatively, body132may comprise an oxide of indium—e.g., InGaO, InO or the like—which has an oxygen vacancy level (e.g., less than 1017per cm3) that contributes to a mobility which is equal to or greater than 100 square centimeters per Volt second (cm2/V·s).

Body134may be formed of any of a variety of suitable semiconductor materials including, but not limited to, one of InGaZO, zinc oxide, InO, GaO, TiO2, AZO, ITO, IZO, polysilicon, Ge, alloys thereof, etc. In some embodiment, an oxygen vacancy level—e.g., more than 1017per cm3—a level of doping (if any) and/or other such characteristics of body134may contribute to a bandgap which is equal to or greater than 2.0 electron Volts (eV).

A thickness (z-axis dimension) of channel structure130may, for example, be in a range of 2 nm to 40 nm—e.g., wherein one or both of a length (x-axis dimension) and a width (y-axis dimension) of channel structure130is/are in a range of 10 nm to 100 nm. In such an embodiment, respective thicknesses of SD structures140,150may be in a range of 2 nm to 50 nm—e.g., wherein respective lengths and/or respective widths of SD structures140,150are each in a range of 10 nm to 100 nm. In some embodiments, portion132may be self-aligned with SD structure140and/or portion134may be self-aligned to SD structure150. Such self-alignment may be width respect to a length dimension, a width dimension or a combination thereof.

In one embodiment, a thickness of layer122is in a range of 1 nm to 30 nm. It is to be appreciated that a length of gate structure120may be greater than, equal to or even smaller than a length of channel structure130. Similarly, a width of gate structure120may be greater than, equal to or even smaller than a width of channel structure130. The respective lengths of gate structure120and layer122may vary significantly in different embodiments based on implementation-specific details (e.g., including the presence, proximity and configuration of any other circuit elements on substrate110). It is to be appreciated that the above dimensions are merely illustrative, and may vary in different embodiments according to implementation-specific details.

FIG. 2shows features of a method200to provide functionality of an integrated circuit device according to an embodiment. Method200may fabricate some or all structures of IC device100, for example. To illustrate certain features of various embodiments, method200is described herein with reference to structures which are variously shown inFIGS. 3A, 3B. However, method200may additionally or alternatively fabricate any of a variety of other structures, in different embodiments.

As shown inFIG. 2, method200may comprise operations205to fabricate a transistor, a channel structure of which comprises both a high mobility semiconductor body and a wide bandgap semiconductor body. In an embodiment, operations205comprise (at210) forming a gate comprising a metal, and (at220) forming a layer adjacent to the gate, the layer comprising a dielectric material. The various forming at210and220may include masking, lithography, etching, deposition (e.g., chemical vapor deposition, atomic layer deposition or the like) and/or other operations which, for example, are adapted from conventional semiconductor fabrication techniques.

Referring now toFIGS. 3A, 3B, various respective cross-sectional views are shown for stages300through305of processing to fabricate transistor structures according to an embodiment. More particularly, for each of stages300through305, corresponding structures during that stage are shown in a respective x-z plane cross-sectional view. The processing represented by stages300through305may include operations of method200—e.g., wherein such processing is to fabricate a device having at least some features of IC device100.

As shown at stage300, a gate structure320may be disposed on a substrate310, the gate structure320located in a recess which is formed at least in part by a dielectric312. Substrate310, dielectric312and gate structure320may correspond functionally to substrate110, dielectric112and gate structure120(respectively), in one embodiment. Gate structure320may be located in a recess which is formed at least in part by a dielectric312. The forming at210may include a selective deposition of one or more metal materials into such a recess to form gate structure320. Such selective deposition may include one or more operations which, for example, are adapted from conventional techniques to fabricate structures of a back-end (or other) transistor device. In such an embodiment, the forming of the layer at220may include—at stage300—depositing at least on a surface of gate structure320a layer322of a dielectric material (such as that of layer122). For example, layer322may be formed by depositing one or more layers of dielectric material via chemical vapor deposition (CVD), plasma enhanced CVD, or another suitable deposition process. The extent of layer322may be limited or otherwise defined by use of a patterned mask (not shown) during such deposition.

Referring again toFIG. 2, method200may further comprise (at230) forming a first body of a first “high mobility” semiconductor adjacent to the layer—e.g., wherein a mobility of the first semiconductor is equal to or greater than 100 cm2/V·s. The first semiconductor may comprise any of a variety of high mobility materials that, for example, are adapted from conventional transistor designs. In an embodiment, the first semiconductor comprises one of gallium, nitrogen, silicon, indium, phosphorous, or arsenic (for example, one of GaN, Si, InP, or GaAs)—e.g., wherein the first semiconductor comprises gallium and one of nitrogen, or arsenic. The first body formed at230may correspond functionally to semiconductor body132.

For example, referring again toFIGS. 3A, 3B, a patterned mask314may be formed directly or indirectly over one or both of dielectric312and some of layer322(as shown at stage301). A hole315formed by mask314may expose at least a portion of layer322, the hole315enabling a first deposition of a high mobility semiconductor to form a semiconductor body330.

Referring again toFIG. 2, method200may further comprise (at240) forming a second body of a second semiconductor other than the first semiconductor, wherein a bandgap of the second semiconductor is equal to or greater than 2.0 eV. For example, as shown at stage302, a wide bandgap semiconductor may be deposited through hole315and onto an exposed surface of the previously formed semiconductor body330. Such deposition may result in the formation of another semiconductor bodies332. The second (wide bandgap) semiconductor may comprise one of titanium, indium, gallium, zinc, arsenic, tin, silicon, or germanium—e.g., wherein the second semiconductor comprises oxygen and one of titanium, indium, gallium, zinc, arsenic, or tin. Although some embodiments are not limited in this regard, the high mobility semiconductor and the wide bandgap semiconductor may have partially (i.e., only partially) similar chemical compositions—e.g., wherein such compositions vary from one another at least with respect to dopant levels, oxygen vacancy levels and/or the like.

In an embodiment, method200further comprises (at250) forming a source and a drain, wherein portions of the second body each adjoin a different respective one of the source or the drain, wherein the first body is between the second body and the layer which is formed at220. In some embodiments, a first portion of the second body is disposed between the first body and one of the source or the drain—e.g., wherein a second portion of the second body is disposed between the first body and another of the source or the drain. A portion of the second body is between the gate and an underlying substrate, wherein a thickness of the second body is in a range of 0.2 nanometers (nm) to 5.0 nm. Alternatively, the gate may be between the second body and a substrate, wherein a thickness of the second body is more than 5.0 nanometers (e.g., where the thickness of the second body is in a range of 6 nm to 20 nm).

Referring now to stage303, another patterned mask316may be formed directly or indirectly over at least some of semiconductor bodies330,332—e.g., wherein portions of patterned mask316further extend over one or both of dielectric312and some of layer322. Holes317formed by patterned mask316may leave portions of semiconductor body332exposed to a subsequent deposition processing. For example, as shown at stage304, the forming at250may comprise a conductive material being variously deposited into holes317to form SD structures340,350over respective portions of semiconductor body332.

Referring again toFIG. 2, method200may (in some embodiments) additionally or alternatively comprise one or more operations which provide connectivity with and/or operation of a transistor device such as one resulting from operations205. For example, method200may comprise (at260) coupling a circuit to one of the source or the drain, and/or (at270) communicating a signal with such a circuit and with the one of the source or the drain.

For example, stages300-304may result in the formation of a transistor comprising gate structure320, layer322, SD structures340,350and a semiconductor structure (comprising bodies330,332) which is to function as a channel structure for conducting a current between SD structures340,350. As shown at stage305, an insulator material360may be deposited over SD structures340,350, over the semiconductor structure and/or other such circuit structures. Connectivity with such a transistor may be provided at least in part with electrodes342,352which extend into insulator material360to couple to SD structures340,350(respectively).

FIG. 4shows features of an integrated circuit (IC)400comprising a transistor which includes an arrangement of semiconductor structures according to another embodiment. IC400is one example of an embodiment wherein a transistor comprises a first body of a high mobility semiconductor material and a second body of a wide bandgap semiconductor material, wherein the first body is disposed between a dielectric layer and the second body, and wherein both the first body and the second body extend between (and variously adjoin) two doped source or drain regions of the transistor. IC400may include features of IC device100, for example. In some embodiments, functionality of IC400is provided according to operations of method200.

As shown inFIG. 4, IC400may include one or more material layers410which are disposed, directly or indirectly, on an underlying substrate416. The one or more material layers410may include at least a body432of a wide bandgap semiconductor material. In some embodiments, one or more material layers410further comprise one or more other semiconductor layers and/or one or more insulation layers (e.g., including a buried oxide layer). Such one or more additional layers may variously provide a lattice gradient, a potential well and/or the like.

In such an embodiment, a transistor of IC400may comprise—in addition to body432—a gate420, a layer422of a dielectric material, a layer430of a high mobility semiconductor material, a SD structures each comprising a respective one of doped SD regions440,450, and a respective one of SD contacts442,452. Sidewall spacers424may facilitate electrical insulation between gate420and other structures (such as SD contacts442,452). Layer422may be disposed directly or indirectly on a side of the one or more material layers410—e.g., wherein layer422is between gate420and layer430, wherein layer430is between layer422and body432. Layer430and body432may each extend between the SD structures—e.g., wherein layer430and body432each variously adjoin doped SD regions440,450. Semiconductor bodies430,432, layer422and gate420may functionally correspond (respectively) to semiconductor bodies134,132, layer122and gate120.

The transistor of IC device400may be a planar transistor (e.g., wherein the transistor is a TFT), or alternatively, any of a variety of non-planar transistor such as a tri-gate transistor, a finFET transistor, or the like. For example,FIG. 5shows, in a perspective view, features of an integrated circuit (IC) device500including a high mobility semiconductor body and an adjoining wide bandwidth semiconductor body according to an embodiment.FIG. 5also shows a cross-sectional view502of IC device500in the y-z plane506of the xyz coordinate system shown.

In the example embodiment shown, IC device500includes a buffer layer510having a side512. Buffer layer510may comprise one or more epitaxial single crystalline semiconductor layers (e.g., silicon, germanium, silicon germanium, gallium arsenide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, etc.) which—for example—may be grown atop a different bulk semiconductor substrate (such as the illustrative silicon substrate516shown).

IC device500may further include on buffer layer510a first semiconductor body which forms a fin structure (such as the illustrative fin structure532shown). For example, the first semiconductor body may be formed in part from an epitaxially grown single crystalline semiconductor such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. Fin structure532may extend to side512, in some embodiments. In other embodiments, the first semiconductor body may further comprise an underlying sublayer portion from which fin structure532extends (e.g., where the underlying sublayer portion is disposed between, and adjoins each of, side512and fin structure532). At least partial electrical isolation of some or all of fin structure532may be provided with a dielectric514(such as a dielectric112, for example).

A source and a drain of a transistor may each include a different respective one of doped regions534,536of fin structure532. The transistor may be configured to selectively provide a conductive channel between doped regions534,536, wherein the channel is to be controlled using a gate structure520which extends over a portion of fin structure532. For example, a gate dielectric524may extend at least in part along, and adjoin, one or more sides of fin structure532. In the example embodiment shown, gate dielectric524comprises a layer of dielectric material which extends over a top side522of fin structure532. Such a layer of dielectric material may further extend along either or both of two opposing vertical sidewalls of fin structure532—e.g., wherein gate dielectric524extends to side512.

To mitigate current leakage and/or otherwise improve transistor performance, a layer530of a high mobility semiconductor may be disposed between gate dielectric524and a portion of fin structure532which is under gate dielectric524. In such an embodiment, some or all of the portion of fin structure532includes a body of a wide bandgap semiconductor material (the body adjoining layer530). In one such embodiment, another cross-section of IC device500—the cross-section in a x-z plane that extends along a midline of fin structure532—corresponds to the cross-sectional side view of IC device400inFIG. 4.

FIG. 6illustrates a computing device600in accordance with one embodiment. The computing device600houses a board602. The board602may include a number of components, including but not limited to a processor604and at least one communication chip606. The processor604is physically and electrically coupled to the board602. In some implementations the at least one communication chip606is also physically and electrically coupled to the board602. In further implementations, the communication chip606is part of the processor604.

The processor604of the computing device600includes an integrated circuit die packaged within the processor604. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip606also includes an integrated circuit die packaged within the communication chip606.

The computer system700may further include a network interface device708. The computer system700also may include a video display unit710(e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device712(e.g., a keyboard), a cursor control device714(e.g., a mouse), and a signal generation device716(e.g., a speaker).

The secondary memory718may include a machine-accessible storage medium (or more specifically a computer-readable storage medium)732on which is stored one or more sets of instructions (e.g., software722) embodying any one or more of the methodologies or functions described herein. The software722may also reside, completely or at least partially, within the main memory704and/or within the processor702during execution thereof by the computer system700, the main memory704and the processor702also constituting machine-readable storage media. The software722may further be transmitted or received over a network720via the network interface device708.

Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.