Temperature compensation circuit

A temperature compensation circuit may include a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal in negatively-proportional-to-absolute temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature.

TECHNICAL FIELD

The present disclosure relates generally to electronic circuits and, more particularly, to temperature compensation for electronic circuits.

BACKGROUND

Integrated circuits may be required to perform across a range of temperatures. Various devices in an integrated circuit, including, but not limited to, transistors, resistors, and capacitors may have performance parameters that vary across a range of temperatures. Accordingly, the performance of circuits that comprise such devices may also vary across a range of temperatures. To improve accuracy over a range of temperatures, a circuit may be designed to include temperature compensation that offsets the variation that the circuit would otherwise experience across a range of temperatures.

SUMMARY

In accordance with some embodiments of the present disclosure, a temperature compensation circuit may comprise a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal is negatively-proportional-to-absolute-temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature.

Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein.

DETAILED DESCRIPTION

FIG. 1depicts a block diagram of an example wireless communication system100, in accordance with certain embodiments of the present disclosure. For simplicity, only two terminals110and two base stations120are shown inFIG. 1. A terminal110may also be referred to as a remote station, a mobile station, an access terminal, user equipment (UE), a wireless communication device, a cellular phone, or some other terminology. A base station120may be a fixed station and may also be referred to as an access point, a Node B, or some other terminology. A mobile switching center (MSC)140may be coupled to the base stations120and may provide coordination and control for base stations120.

A terminal110may or may not be capable of receiving signals from satellites130. Satellites130may belong to a satellite positioning system such as the well-known Global Positioning System (GPS). Each GPS satellite may transmit a GPS signal encoded with information that allows GPS receivers on earth to measure the time of arrival of the GPS signal. Measurements for a sufficient number of GPS satellites may be used to accurately estimate a three-dimensional position of a GPS receiver. A terminal110may also be capable of receiving signals from other types of transmitting sources such as a Bluetooth transmitter, a Wireless Fidelity (Wi-Fi) transmitter, a wireless local area network (WLAN) transmitter, an IEEE 802.11 transmitter, and any other suitable transmitter.

InFIG. 1, each terminal110is shown as receiving signals from multiple transmitting sources simultaneously, where a transmitting source may be a base station120or a satellite130. In certain embodiments, a terminal110may also be a transmitting source. In general, a terminal110may receive signals from zero, one, or multiple transmitting sources at any given moment.

System100may be a Code Division Multiple Access (CDMA) system, a Time Division Multiple Access (TDMA) system, or some other wireless communication system. A CDMA system may implement one or more CDMA standards such as IS-95, IS-2000 (also commonly known as “1x”), IS-856 (also commonly known as “1xEV-DO”), Wideband-CDMA (W-CDMA), and so on. A TDMA system may implement one or more TDMA standards such as Global System for Mobile Communications (GSM). The W-CDMA standard is defined by a consortium known as 3GPP, and the IS-2000 and IS-856 standards are defined by a consortium known as 3GPP2.

FIG. 2depicts a block diagram of selected components of an example transmitting and/or receiving element200(e.g., a terminal110, a base station120, or a satellite130), in accordance with certain embodiments of the present disclosure. Element200may include a transmit path201and/or a receive path221. Depending on the functionality of element200, element200may be considered a transmitter, a receiver, or a transceiver.

As depicted inFIG. 2, element200may include digital circuitry202. Digital circuitry202may include any system, device, or apparatus configured to process digital signals and information received via receive path221, and/or configured to process signals and information for transmission via transmit path201. Such digital circuitry202may include one or more microprocessors, digital signal processors, and/or other suitable devices.

Transmit path201may include a digital-to-analog converter (DAC)204. DAC204may be configured to receive a digital signal from digital circuitry202and convert such digital signal into an analog signal. Such analog signal may then be passed to one or more other components of transmit path201, including upconverter208.

Upconverter208may be configured to frequency upconvert an analog signal received from DAC204to a wireless communication signal at a radio frequency based on an oscillator signal provided by oscillator210. Oscillator210may be any suitable device, system, or apparatus configured to produce an analog waveform of a particular frequency for modulation or upconversion of an analog signal to a wireless communication signal, or for demodulation or downconversion of a wireless communication signal to an analog signal. In some embodiments, oscillator210may be a digitally-controlled crystal oscillator.

As shown inFIG. 2, oscillator may include a phase-locked loop (PLL)212. PLL212may be a control system configured to generate a signal that has a fixed relation to the phase of a “reference” input signal by responding to both the frequency and the phase of the input signal, and automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. PLL212may be described in greater detail below with reference toFIG. 3.

Transmit path201may include a variable-gain amplifier (VGA)214to amplify an upconverted signal for transmission, and a bandpass filter216configured to receive an amplified signal VGA214and pass signal components in the band of interest and remove out-of-band noise and undesired signals. The bandpass filtered signal may be received by power amplifier220where it is amplified for transmission via antenna218. Antenna218may receive the amplified and transmit such signal (e.g., to one or more of a terminal110, a base station120, and/or a satellite130).

Receive path221may include a bandpass filter236configured to receive a wireless communication signal (e.g., from a terminal110, a base station120, and/or a satellite130) via antenna218. Bandpass filter236may pass signal components in the band of interest and remove out-of-band noise and undesired signals. In addition, receive path221may include a low-noise amplifier (LNA)234to amplify a signal received from bandpass filter236.

Receive path221may also include a downconverter228. Downconverter228may be configured to frequency downconvert a wireless communication signal received via antenna218and amplified by LNA234by an oscillator signal provided by oscillator210(e.g., downconvert to a baseband signal). Receive path221may further include a filter238, which may be configured to filter a downconverted wireless communication signal in order to pass the signal components within a radio-frequency channel of interest and/or to remove noise and undesired signals that may be generated by the downconversion process. In addition, receive path221may include an analog-to-digital converter (ADC)224configured to receive an analog signal from filter238and convert such analog signal into a digital signal. Such digital signal may then be passed to digital circuitry202for processing.

FIG. 3depicts a block diagram of PLL212, in accordance with certain embodiments of the present disclosure. PLL212may be a frequency-selective circuit designed to synchronize an incoming signal, vI(ωI, θI) and maintain synchronization in spite of noise or variations in the incoming signal frequency. As depicted inFIG. 3, PLL212may comprise a phase detector302, a loop filter304, a voltage-controlled oscillator (VCO)306, and a voltage regulator308.

Phase detector302may be configured to compare the phase θIof the incoming reference signal vIto the phase θOof the VCO306output vO, and produce a voltage vDproportional to the difference θI−θO. In some embodiments, phase detector302may include a frequency divider that may divide the frequency of the VCO306output before comparing the phase θIof the incoming reference signal vIto the phase θOof the VCO306output vO. Voltage vDmay be filtered by loop filter304to suppress high-frequency ripple and noise, and the result, called the error voltage vE, may be applied to a control input of VCO306to adjust its frequency ωvco. VCO306may be configured such that with vE=0 it is oscillating at some initial frequency ω0, known as the free-running frequency, so that the characteristic of VCO306is:
ωvco=ω0+KVvE(t)
where KVis the gain of VCO306in radians-per-second per volt. If a periodic input is applied to PLL212with frequency ωIsufficiently close to the free-running frequency ω0, an error voltage vEwill develop, which will adjust ωvcountil vObecomes synchronized, or locked, with vI. Should ωIchange, the phase shift between vOand vIwill start to increase, changing vDand vE. VCO306may be configured such that this change in vEadjusts θvcountil it is brought back the same value as ωI, allowing the PLL212, once locked, to track input frequency changes.

In some embodiments, VCO306may comprise an inductor-capacitor (“LC”) VCO. Factors that may contribute to the variation of the frequency of VCO306across a range of temperatures include the variation across temperature of parasitic capacitance in the VCO active stage, variation across temperature of a variable capacitance bank, and variation across temperature of a supply voltage that may be provided by voltage regulator308to power VCO306that may cause a variation in a supply-dependent parasitic capacitance in the VCO active stage and a supply-dependent variable capacitance bank in VCO306. The described factors may have a temperature dependency that may vary the effective tank capacitance of an LC VCO, and in turn, the factors may cause a frequency shift of VCO306across a range of temperatures.

While the closed loop operation of PLL212may compensate for some variation of VCO306over temperature, too much variation of VCO306can lead the PLL212to go out of lock. However, a temperature compensation scheme may be implemented to offset the variation of VCO306over temperature. For example, voltage regulator308may be configured to provide a supply voltage with a temperature coefficient that may offset the other factors that may impact the frequency variation of VCO306over a range of temperatures. In some embodiments, the temperature compensation scheme may not perfectly offset other factors impacting the frequency variation of VCO306over temperature, but the temperature compensation scheme may significantly reduce the overall variation of VCO306over temperature to the extent that the closed loop operation of PLL212may account for the remaining variation without PLL212going out of lock.

FIG. 4depicts a block diagram of voltage regulator308, in accordance with certain embodiments of the present disclosure. Voltage regulator308may include a temperature compensation circuit410, a resistor421, a capacitor422, and an N-type metal-oxide semiconductor field-effect transistor (NMOS)423. Temperature compensation circuit410may drive a voltage signal, VTC. Resistor421may have a first terminal coupled to the VTC output of temperature compensation circuit410and a second terminal coupled to a gate of NMOS423. Capacitor422may have a first terminal coupled to a gate of NMOS423and a second terminal coupled to a low potential power supply, which, for the purposes of the present disclosure, may be referred to as “GND.” Accordingly, resistor421and capacitor422may provide an RC-filter on the VTC signal. NMOS423may have a drain coupled to a high potential power supply, which for the purposes of the present disclosure, may be referred to as “VDD.” As described above, a gate of NMOS423may be driven by the VTC signal through an RC filter. NMOS423may have a source that may be coupled to the output of voltage regulator308used to supply power to VCO306. In the configuration described above, NMOS423may be described as operating in source-follower mode. Accordingly, the regulator output at the source of NMOS423may track the VTC signal that may drive the gate of NMOS423through an RC filter.

In some embodiments, VCO306may experience different amounts of temperature variation at different operating frequencies. Further, VCO306may experience different amounts of temperature variation across different ranges of temperatures. For example, VCO306may experience a larger amount of temperature variation at the higher end of its oscillator frequency range than at the lower end of its oscillator frequency range. Also, VCO306may, for example, experience one level of variation from a cold temperature to a median temperature and experience a second level of variation from a median temperature to a hot temperature. To compensate for the described variations, some embodiments of temperature compensation circuit410may provide different temperature coefficients at different temperature ranges. Further, in some embodiments of temperature compensation circuit410, different temperature coefficients at different temperature ranges may be independently programmable. The generation of multiple independently programmable temperature coefficients may be discussed below in greater detail with reference toFIG. 5andFIG. 6.

As described above, VCO306may have a range of frequencies in which it may operate. VCO306may be configured such that it may be tuned to a frequency corresponding to the desired PLL212frequency. For example, in some embodiments, VCO306may receive a five-bit course tune signal (Ctune <4:0>) that may tune VCO306to one of thirty-two potential coarse frequency ranges at, for example, 20 MHz steps. In some embodiments, VCO306may be finely tuned within the selected coarse-tune range after being coarsely tuned by the Ctune<4:0> signal. As described above, the temperature variation of VCO306may be different at different operating frequencies. Accordingly, the five-bit coarse tune signal may also be received by the temperature compensation circuit410, which may use the Ctune<4:0> signal to select a cold-to-median temperature coefficient and a median-to-hot temperature coefficient, both of which may correspond to the cold-to-median and median-to-hot temperature variations of VCO306at the frequency designated by the Ctune<4:0> signal.

FIG. 5depicts a functional block diagram500of a temperature compensation scheme, in accordance with certain embodiments of the present disclosure.

In the present disclosure, various temperatures may be referred to as “cold,” “room,” or “hot” temperatures. As used herein, “room” temperature may be used to describe the temperature of a device based on ambient air temperatures. Such temperatures may commonly be in the range of twenty-five to thirty degrees Celsius.

In the present disclosure, various temperatures may be referred to as a “median” temperature. A “median” temperature may refer to a selected temperature that may be less than, in the range of, or greater than “room” temperature. When referred to in conjunction with a median temperature, a “cold” temperature may mean any temperature less than a selected median temperature, and a “hot” temperature may mean any temperature greater than a selected median temperature. Accordingly, when discussed in terms of a range, “cold to median” may refer to a range of temperatures starting at less than the median temperature and going to the median temperature, and “median to hot” may refer to a range of temperatures starting at a median temperature and going to a temperature that may be greater than the median temperature.

Block510illustrates a current, Ineg_tc_prog, that may have a programmable negative temperature coefficient from cold to median, and zero temperature coefficient from median to hot. The generation of Ineg_tc_prog may be described in further detail below in reference toFIG. 6andFIG. 7E.

Block520illustrates a current proportional-to-absolute-temperate, Iptat, that may have a positive temperature coefficient from cold to hot. The generation of Iptat may be described in further detail below in reference toFIG. 6andFIG. 7A.

Block530illustrates the summation of Ineg_tc_prog and Iptat to generate a current, Ipre_tc, that may have a programmable temperature coefficient from cold to median and a positive temperature coefficient from median to hot. Block540illustrates the conversion of Ipre_tc into a voltage signal, Vpre_tc. The generation of Ipre_tc and its conversion into Vpre_tc may be described in further detail below in reference toFIG. 6.

Block550illustrates a current, Ipos_tc_prog, that may have zero temperature coefficient from cold to median, and a programmable positive temperature coefficient from median to hot. The generation of Ipos_tc_prog may be described in further detail below in reference toFIG. 6andFIG. 7C.

As shown inFIG. 5, Ipos_tc_prog may be injected into a feedback network of amplifier560, at for example, the negative input of amplifier560. The feedback network of amplifier560may include a resistor570coupled from the output of amplifier560to the negative input of amplifier560and a resistor580coupled from the negative input of amplifier560to GND.

Amplifier560may combine the Vpre_tc signal and the Ipos_tc_prog signal according to the feedback network. Amplifier may output a voltage signal, VTC, with a first programmable temperature coefficient from cold to median and a second programmable temperature coefficient from median to hot. The generation of the VTC signal and the characteristics of the VTC signal may be described in more detail below in reference toFIG. 6andFIG. 7F.

FIG. 6depicts a schematic diagram of temperature compensation circuit410, in accordance with certain embodiments of the present disclosure.FIGS. 7A-7Einclude graphs illustrating various currents that may be generated inside of temperature compensation circuit410, in accordance with certain embodiments of the present disclosure, and may be referenced to in conjunction withFIG. 6.FIG. 7Fdepicts a graph illustrating an output voltage of the temperature compensation circuit410, in accordance with certain embodiments of the present disclosure, and may be referenced to in conjunction withFIG. 6.

In the present disclosure, the term “equivalent” may be used to describe two or more currents that may be designed to be approximately equal to each other or to describe two or more voltage potentials that may be designed to be approximately equal to each other. Though they may be designed to be approximately equal to each other, “equivalent” voltages, “equivalent” currents, or other “equivalent” items may include some variation due to factors including, but not limited to, device matching imperfections, semiconductor processing imperfections, and/or imbalanced operating conditions.

The present disclosure may refer to the “size” of various types of transistors, including an N-type bipolar junction transistor (NPN), an N-type metal-oxide semiconductor field-effect transistor (NMOS), and a P-type metal-oxide semiconductor field-effect transistor (PMOS). Unless otherwise specified, the description of a transistor's size, as used herein, describes the size parameter that affects the transconductance of the transistor. For example, for NPN devices, “size” may refer to the area of the NPN's base-to-emitter junction. Also, for PMOS and NMOS devices, “size” may refer to the width-to-length ratio of the gate and/or conducting channel of the device. Accordingly, devices that are described as having a size at a ratio, or being sized at a ratio, as compared to another otherwise matching device, may have a transconductance that is larger or smaller at that ratio as compared to the transconductance of the other device.

Temperature compensation circuit410may include an Iptat generator601. Iptat generator601may include an NPN603, an NPN604, a resistor608, an NMOS605, an NMOS606, a PMOS610, and a PMOS611.

NPN603may have a collector and a base that may be coupled together and an emitter that may be coupled to GND. NPN604may have a collector and a base that may be coupled together and an emitter that may be coupled to GND. Resistor608may have a first terminal coupled to a source of NMOS605and a second terminal coupled to a base and a collector of NPN603. NMOS606may have a gate and a drain that are coupled together and a source that may be coupled to a base and a collector of NPN604. NMOS605may have a gate that may be coupled to a gate and a drain of NMOS606. PMOS610may have a source that may be coupled to VDD. PMOS610may have a gate and a drain that may be coupled together and further coupled to a drain of NMOS605. PMOS611may have a source coupled to VDD, a drain coupled to a gate and a drain of NMOS606, and a gate coupled to a gate and a drain of PMOS610.

NPN603may be sized at a ratio of N:1 as compared to NPN604, where “N” may be a number larger than one. As described above, the respective gates of PMOS610and PMOS611may be coupled to a drain of PMOS610. Accordingly, PMOS611may mirror the current of PMOS610, forcing the current through NMOS606and NPN604to be equivalent to the current through NMOS605and NPN603. Because the size of NPN603may be larger than the size of NPN604, the base-to-emitter voltage (Vbe) for NPN603may be less than the Vbe of NPN604. The difference between the Vbe of NPN604and the Vbe of NPN603may be referred to as a “delta Vbe” or a “ΔVbe.”

NMOS606may match NMOS605, and because the current through NMOS605may be equivalent to the current through606, the gate-to-source voltage of NMOS605may be equivalent to the gate-to-source voltage of NMOS606. Accordingly, the voltage at the source of NMOS605may be equivalent to the voltage at the source of NMOS606. Thus, the voltage across resistor608may be equivalent to the delta Vbe of NPN604and NPN603, and the current through resistor608may be described as ΔVbe divided by resistor608, or generically as a “ΔVbe/R” current. ΔVbe may have a positive temperature coefficient, i.e., the magnitude of ΔVbe may become larger at higher absolute temperatures. For example, in some embodiments, ΔVbe may increase approximately 0.087 mV per degree Celsius. Accordingly, the ΔVbe/R current through resistor608may have a positive temperature coefficient and may be described as a current proportional-to-absolute-temperature (“Iptat”).

As described above, PMOS610may have a gate and a drain that may be coupled to each other, and NMOS606may have a gate and a drain that may be coupled to each other. Accordingly, PMOS610and NMOS606may be described as being configured to be self-biased devices during normal operation. In some embodiments, the high potential power supply, VDD, may be at zero volts before the power is turned on. Once power is applied to VDD, during, for example, power-up of a device including an embodiment, the voltage potential of VDD may rise from zero volts to a high potential, e.g., 1.8 volts. During such a power-up event, start-up devices (not expressly shown), as known in the art, may be used to inject a start-up current or start-up currents into the paths of PMOS610and/or NMOS606in order for those devices to become self-biased. After power-up, PMOS610and NMOS606may be self-biased and fully operational, and accordingly, the start-up current or currents may be turned off.

Temperature compensation circuit410may include an Intat generator602. Intat generator602may include a resistor609, an NMOS607, and a PMOS620. Resistor609may have a first terminal coupled to GND and a second terminal coupled to the source of NMOS607. NMOS607may have a gate that may be coupled to the gate and drain of NMOS606. PMOS620may have a source coupled to VDD and a gate and a drain that may be coupled together and further coupled to the drain of NMOS607.

NMOS607may match NMOS606, and the current through NMOS607may be configured to be equivalent to the current through NMOS606. Accordingly, the gate-to-source voltage of NMOS607may be approximately the same as the gate-to-source voltage of NMOS606. Thus, the voltage potential at the source of NMOS607may be equivalent to the voltage potential at the source of NMOS606, causing the voltage potential across resistor609to be equivalent to the Vbe of NPN604. Accordingly, the current through resistor609may be described as a Vbe divided by resistor609, or generically as a “Vbe/R” current. The Vbe of NPN604may have a negative temperature coefficient, i.e., the magnitude of Vbe may become lower at higher temperatures. For example, in some embodiments, Vbe may decrease approximately −1.5 mV per degree Celsius. Accordingly, the Vbe/R current through resistor609may have a negative temperature coefficient and may be described as a current negative-to-absolute-temperature (“Intat”).

Graph700inFIG. 7Adepicts an Iptat current711and an Intat current710across a range of temperatures, in accordance with some embodiments of the present disclosure. As illustrated inFIG. 7A, Iptat current711may be lower than Intat current710from cold to room. Iptat711may increase with increased temperature and Intat710may decrease with increased temperature. Accordingly, Iptat711and Intat710may be equivalent at an intersection temperature712that may be equal to room temperature. In some alternative embodiments, the intersection temperature712may move to a temperature that may be greater or less than room temperature if Iptat is scaled up or down. For example, in some embodiments, Iptat current711may be scaled up, thus causing the intersection temperature712to be lower than room temperature. In some alternative embodiments, Iptat current711may be scaled down, thus causing the intersection temperature712to be higher than room temperature. Similarly, in some alternative embodiments, the intersection temperature712may move if Intat is scaled up or down. For example, in some embodiments, Intat current710may be scaled up, thus causing the intersection temperature712to be higher than room temperature. In some alternative embodiments, Intat current710may be scaled down, thus causing the intersection temperature712to be lower than room temperature. Accordingly, the intersection temperature may be described as a selected “median” temperature.

Referring back toFIG. 6, a current with a positive temperature coefficient from median to hot (“Ipos_tc”) may be generated at PMOS630by comparing mirrored versions of the Iptat current and the Intat current. Temperature compensation circuit410may include a PMOS612, an NMOS640, an NMOS642, a PMOS622, a PMOS630, and a programmable-PMOS631.

PMOS612may have a source that may be coupled to VDD and a gate that may be coupled to the gate and drain of PMOS610. Accordingly, PMOS612may mirror the Iptat current711flowing through PMOS610. NMOS640may have a source coupled to GND and have a gate and a drain that are coupled together and further coupled to the drain of PMOS612. Accordingly, NMOS640may sink the mirrored Iptat current from PMOS612. NMOS642may have a source coupled to GND and a gate coupled to the gate and drain of NMOS640. NMOS642may be sized at a ratio of A:1 as compared to NMOS640. Accordingly, NMOS642may mirror the Iptat current of NMOS640at a ratio of A:1 and sink a current740that may be equivalent to A*Iptat.

PMOS622may have source coupled to VDD and a gate coupled to the gate and drain of PMOS620. PMOS622may be sized at a ratio of B:1 as compared to PMOS620. Accordingly, when operating in saturation mode, PMOS622may mirror the Intat current of PMOS620at a ratio of B:1 and source a current741that may be equivalent to B*Intat.

Graph701inFIG. 7Bdepicts the subtraction of an Intat current from an Iptat current, in accordance with certain embodiments of the present disclosure. Referring back toFIG. 6, PMOS630may have a source that may be coupled to VDD, and a gate and drain that may be coupled to each other and may be further coupled to the respective drains of PMOS622and NMOS642. Accordingly, PMOS630may source a current742(Ipos_tc) that equals current740(A*Iptat) minus current741(B*Intat). At cold temperatures, Iptat may be lower than Intat. Accordingly, from cold to median, PMOS622may operate in linear mode and current741sourced by PMOS622may be limited by current740sunk by NMOS642, and current742sourced by PMOS630may equal zero. At hot temperatures, Iptat may be higher than Intat. Accordingly, the difference between current740sunk by NMOS642and current741sourced by PMOS622may increase from median to hot, and current742sourced by PMOS630may increase from median to hot.

As shown inFIG. 7B, current742sourced by PMOS630equals zero from cold to the median temperature of inflection point743where A*Iptat equals B*Intat. Current742then increases from the median temperature of inflection point743to hot temperatures where the difference between A*Iptat and B*Intat becomes larger at higher temperatures. In some alternative embodiments, the ratio of A:B may be increased, which may cause the inflection point743, at which the current sourced by PMOS630begins to rise, to be located at a lower temperature. In some alternative embodiments, the ratio of A:B may be decreased, which may cause the inflection point743, at which the current sourced by PMOS630begins to rise, to be located at a higher temperature.

Referring back toFIG. 6, programmable-PMOS631may have a source terminal coupled to VDD and a gate terminal coupled to the gate and drain of PMOS630. In some embodiments, programmable-PMOS631may include a plurality of individual PMOS devices that may be turned off when their gates are driven by VDD, but may be selected to add to the effective size of programmable-PMOS631when their gates are driven by the gate terminal of programmable-PMOS631. Accordingly, programmable-PMOS631may have a programmable effective size and may mirror the current of PMOS630at a programmable ratio. Thus, as shown in graph702ofFIG. 7C, programmable-PMOS631may source a current744(Ipos_tc_prog) that may be equal to zero from a cold temperature to the median temperature of inflection point743, and a positive programmable temperature coefficient from the median temperature of inflection point743to a hot temperature. When a larger number of PMOS devices inside of programmable-PMOS631are selected, Ipos_tc_prog may be larger as shown by current744a. On the other hand, when a smaller number of PMOS devices inside of programmable-PMOS631are selected, Ipos_tc_prog may be smaller as shown by current744c.

As described above, temperature compensation circuit410may receive a five-bit coarse tune signal (Ctune<4:0>) that may also be used to tune VCO306to one of thirty-two potential frequency ranges. In some embodiments, Ctune<4:0> may be translated and input into the control bits of programmable-PMOS631.

Programmable-PMOS631may be configured such that each setting of the Ctune<4:0> signal, and the corresponding setting of the control bit inputs, may select the proper number of individual PMOS devices inside of programmable-PMOS631to select the magnitude of current744required to generate a temperature coefficient from median to hot that may offset the temperature coefficient of VCO306at the frequency corresponding to the Ctune<4:0> setting.

In some alternative embodiments, the coarse tune signal may have a number of bits other than five. Further, though temperature compensation circuit410is described herein in conjunction with VCO306in PLL212, some embodiments of temperature compensation circuit410may be used in conjunction with other types of circuits that may have parameters that vary over temperature. Some embodiments may include any suitable number of control bits to provide a required range of potential values for Ipos_tc_prog from median to hot. In some embodiments the control bit or bits of programmable-PMOS631may be driven dynamically. In some embodiments, the control bit or bits of programmable-PMOS631may be driven by registers stored in memory, e.g., Electrically Erasable Programmable Read-Only Memory (EEPROM) or other types of memory. In some embodiments, the control bit or bits of programmable-PMOS631may be hard-coupled to GND or VDD, for example, by metal-layer connections in a semiconductor process.

Referring back toFIG. 6, a current with a negative temperature coefficient from cold to median (“Ineg_tc”) may be generated at NMOS635by comparing mirrored versions of the Iptat current and the Intat current. Temperature compensation circuit410may include a PMOS621, an NMOS641, an NMOS635, an NMOS636, a PMOS637, and a programmable-PMOS638.

PMOS621may have a source that may be coupled to VDD and gate that may be coupled to the gate and drain of PMOS620. PMOS621may be sized at a ratio of C:1 as compared to PMOS620. Accordingly, PMOS621may mirror the Intat current of PMOS620at a ratio of C:1 and source a current that may be equivalent to C*Intat.

NMOS641may have a source that may be coupled to GND and a gate that may be coupled to the gate and drain of NMOS640. NMOS641may be sized at a ratio of D:1 as compared to NMOS640. Accordingly, when operating in saturation mode, NMOS641may mirror the current of NMOS640at a ratio of D:1 and sink a current that may be equivalent to D*Iptat.

Graph703inFIG. 7Ddepicts the subtraction of an Iptat current from an Intat current, in accordance with certain embodiments of the present disclosure. Referring back toFIG. 6, NMOS635may have a source that may be coupled to GND, and a gate and drain that are coupled to each other and are further coupled to the respective drains of PMOS621and NMOS641. Accordingly, NMOS635may sink a current752(Ineg_tc) that equals current750(C*Intat) minus current751(D*Iptat). At cold temperatures, Iptat may be lower than Intat. Accordingly, the difference between current750sourced by PMOS621and current751sunk by NMOS641may decrease from cold to median, and current752sunk by NMOS635may decrease from cold to median. At hot temperatures, Iptat may be greater than Intat. Accordingly, from median to hot, NMOS641may operate in linear mode and current751sunk by NMOS641may be limited by current750sourced by PMOS621, and current752sunk by NMOS635may equal zero.

As shown inFIG. 7D, current752sunk by NMOS635may decrease from cold to median, equaling zero at the median temperature of inflection point753where D*Iptat equals C*Intat. In some alternative embodiments, the ratio of C:D may be increased, which may cause the inflection point753, at which the current sunk by NMOS635equals zero, to be located at a higher temperature. In some alternative embodiments, the ratio of C:D may be decreased, which may cause the inflection point753, at which the current sunk by NMOS635hits zero, to be located at a lower temperature.

Referring back toFIG. 6, NMOS636may have a source that may be coupled to GND and a gate that may be coupled to the gate and drain of NMOS635. Accordingly, NMOS636may mirror the current of NMOS635. PMOS637may have a source that may be coupled to VDD and a gate and a drain that are coupled to each other and are further coupled to the drain of NMOS636. Accordingly, PMOS637may source the mirrored current of Ineg_tc.

Programmable-PMOS638may have a source terminal coupled to VDD and a gate terminal coupled to the gate and drain of PMOS637. In some embodiments, programmable-PMOS638may include a plurality of individual PMOS devices that may be turned off when their gates are driven by VDD and may add to the effective size of programmable-PMOS638when their gates are driven by the gate terminal of programmable-PMOS638. Accordingly, programmable-PMOS638may have a programmable effective size and may mirror the current of PMOS637at a programmable ratio. Thus, as shown in graph704ofFIG. 7E, programmable-PMOS638may source a current754(Ineg_tc_prog) that may have a programmable negative temperature coefficient from a cold temperature to the median temperature of inflection point753, and may equal zero from the median temperature of inflection point753to a hot temperature. When a larger number of PMOS devices inside of programmable-PMOS638are selected, Ineg_tc_prog may be larger as shown by current754a. On the other hand, when a smaller number of PMOS devices inside of programmable-PMOS638are selected, Ineg_tc_prog may be smaller as shown by current754c.

As described above, temperature compensation circuit410may receive a five-bit course tune signal (Ctune<4:0>) that may also be used to tune VCO306to one of thirty-two potential frequency ranges. In some embodiments, Ctune<4:0> may be translated and input into the control bits of programmable-PMOS638. Programmable-PMOS638may be configured such that each setting of the Ctune<4:0> signal, and the corresponding setting of the control bit inputs, may select the proper number of individual PMOS devices inside of programmable-PMOS638to select the magnitude of current754required to generate a temperature coefficient from cold to median that may offset the temperature coefficient of VCO306at the frequency corresponding to the Ctune<4:0> setting.

In some alternative embodiments, the coarse tune signal may have a number of bits other than five. Further, though temperature compensation circuit410is described herein in conjunction with VCO306in PLL212, some embodiments of temperature compensation circuit410may be used in conjunction with other types of circuits that may have parameters that vary over temperature. Some embodiments may include any suitable number of control bits to provide a required range of potential values for Ineg_tc_prog current from cold to median. In some embodiments the control bit or bits of programmable-PMOS638may be driven dynamically. In some embodiments, the control bit or bits of programmable-PMOS638may be driven by registers stored in memory, e.g., electrically erasable programmable read-only memory (EEPROM) or other types of memory. In some embodiments, the control bit or bits of programmable-PMOS638may be hard-coupled to GND or VDD, for example, by metal-layer connections in a semiconductor process.

Referring back toFIG. 6, a current with a programmable temperature coefficient from cold to median and a positive temperature coefficient from median to hot (Ipre_tc) may be generated by adding Ineg_prog_tc to an Iptat current. Temperature compensation circuit410may include a PMOS613, an NMOS650, an NMOS651, a PMOS653, and a PMOS654. PMOS613may have a source coupled to VDD and a gate coupled to the gate and drain of PMOS610. Accordingly, PMOS613may mirror the Iptat current of PMOS610. NMOS650may have a source coupled to GND and a gate and a drain coupled to each other. The gate and drain of NMOS650may be further coupled to a drain of PMOS613and a drain terminal of programmable PMOS638. Accordingly, NMOS650may sink both the mirrored Iptat current from PMOS613and Ineg_tc_prog from programmable-PMOS638. NMOS651may have a source coupled to GND and a gate coupled to the gate and drain of NMOS650. Accordingly, NMOS651may mirror the sum of the Iptat current and Ineg_tc_prog. PMOS653may have a source coupled to VDD and gate and a drain coupled to each other and further coupled to the drain of NMOS651. Accordingly, PMOS653may source the sum of an Iptat current and Ineg_tc_prog. PMOS654may have a source coupled to VDD and a gate coupled to the gate and drain of PMOS653. Accordingly, PMOS654may mirror the sum of an Iptat current and Ineg_tc_prog and source a current Ipre_tc. As a sum of an Iptat current and Ineg_tc_prog, Ipre_tc may have a programmable temperature coefficient from cold to median and a positive temperature coefficient from median to hot.

Temperature compensation circuit410may include a resistor660. Resistor660may have a first terminal coupled to GND and a second terminal coupled to the drain of PMOS654. Accordingly, resistor660may convert Ipre_tc to a voltage potential Vpre_tc, which, similar to Ipre_tc, may have a programmable temperature coefficient from cold to median and a positive temperature coefficient from median to hot.

Temperature compensation circuit410may include amplifier560as well as a feedback-network resistor570and a feedback-network resistor580. Amplifier560may include a positive input terminal that may be driven by Vpre_tc. Feedback-network resistor570may have a first terminal coupled to an output of amplifier560and a second terminal coupled to a negative input terminal of amplifier560. Feedback-network resistor580may have a first terminal coupled to GND and a second terminal coupled to a negative input terminal of amplifier560. The negative input terminal of amplifier560may also be coupled to the drain terminal of programmable-PMOS631. Thus, Ipos_tc_prog may be injected into the feedback network of amplifier560.

At the positive input terminal of amplifier560, Vpre_tc may have, as described above, a programmable temperature coefficient from cold to median and a positive temperature coefficient from median to hot. At the negative input terminal of amplifier560, Ipos_tc_prog may be injected into the feedback network, as described above, with zero temperature coefficient from cold to median and with a programmable positive temperature coefficient from median to hot. Accordingly, the output terminal of amplifier560may drive a voltage signal VTC that, as shown in graph705ofFIG. 7F, may have a programmable temperature coefficient760from cold to median that may be programmed to be either positive or negative. Further, the positive temperature coefficient from median to hot of Vpre_tc at the positive input terminal of amplifier560may offset the positive slope to the positive programmable temperature coefficient of Ipos_tc_prog at the negative input terminal of amplifier560. Accordingly, as shown in graph705ofFIG. 7F, VTC may have a programmable temperature coefficient770from median to hot that may be programmed to be either a positive or a negative temperature coefficient.

Referring back toFIG. 5, diagram500depicts, as described above, various temperature coefficient signals that may be generated and combined within temperature compensation circuit410. For example, diagram500shows Ineg_tc_prog being combined with an Iptat current to generate an Ipre_tc signal which may be converted into an Vpre_tc signal having a programmable temperature coefficient from cold to median and a positive temperature coefficient from median to hot. The Vpre_tc signal may be input into the positive input terminal of amplifier560while the Ipos_tc signal, which may have a zero temperature coefficient from cold to median and a positive programmable temperature coefficient from median to hot, may be input into the feedback network at the negative input terminal of amplifier560. Accordingly, as shown inFIG. 7F, a VTC signal may be generated that may have a temperature coefficient from cold to median that may be programmed to be either positive or negative, and may have a temperature coefficient from median to hot that may be programmed to be either positive or negative.

Some alternative embodiments may use other combinations of signals to generate the VTC signal. For example, in some embodiments: (i) an Intat signal may be combined with an Ipos_tc_prog signal to create an Ipre_tc signal that may have a negative temperature coefficient from cold to median and a programmable temperature coefficient from median to hot; (ii) the Ipre_tc signal may be converted to a voltage signal, Vpre_tc, and input into the positive input terminal of amplifier560; and (iii) an Ineg_tc_prog signal with a negative programmable temperature coefficient from cold to median may be input into the feedback network at the negative input terminal of amplifier560. Accordingly, in such embodiments, a VTC signal may be generated that may have a temperature coefficient from cold to median that may be programmed to be either positive or negative, and may have a temperature coefficient from median to hot that may be programmed to be either positive or negative.

FIG. 8depicts a flow chart of a method for generating a temperature compensation signal, in accordance with certain embodiments of the present disclosure.

At step802, Iptat generator601may generate a current that is proportional to absolute temperature, i.e., has a positive temperature coefficient. In some embodiments, Iptat may be based on the ΔVbe between NPN604and NPN603divided by resistor608as shown inFIG. 6.

At step804, Intat generator602may generate a current that is negatively proportional to absolute temperature, i.e., has a negative temperature coefficient. In some embodiments, Intat may be based on the Vbe of NPN604divided by resistor609as shown inFIG. 6.

At step806, temperature compensation circuit410may subtract a first mirrored version of Iptat (D*Iptat) from a first mirrored version of Intat (C*Intat) to generate a first signal (Ineg_tc) having a negative temperature coefficient from a cold temperature to a median temperature.

At step808, temperature compensation circuit410may subtract a second mirrored version of Intat (B*Intat) from a second mirrored version of Iptat (A*Iptat) to generate a second signal (Ipos_tc) having a positive temperature coefficient from a median temperature to a hot temperature.

At step810, temperature compensation circuit410may multiply the first signal (Ineg_tc) by a first programmable ratio. In some embodiments, temperature compensation circuit410may perform the multiplication by mirroring a current equivalent to Ineg_tc with a programmable current mirror ratio implemented by programmable-PMOS638.

At step812, temperature compensation circuit410may multiply the second signal (Ipos_tc) by a second programmable ratio. In some embodiments, temperature compensation circuit410may perform the multiplication by mirroring Ipos_tc with a programmable current mirror ratio implemented by programmable-PMOS631.

At step814, temperature compensation circuit410may generate a temperature compensation output signal including a first programmable temperature coefficient from a cold temperature to a median temperature based at least on the first programmable ratio and a second programmable temperature coefficient from the median temperature to the hot temperature based at least on the second programmable ratio. In some embodiments, amplifier560may implement step814by combining the Vpre_tc signal at its positive input terminal with the Ipos_tc_prog signal injected into the negative feedback network at its negative input terminal.

AlthoughFIG. 8discloses a particular number of steps to be taken with respect to method800, method800may be executed with greater or lesser steps than those depicted inFIG. 8. In addition, althoughFIG. 8discloses a certain order of steps to be taken with respect to method800, the steps comprising method800may be completed in any suitable order.

Although the present disclosure has been described with several embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.