High density ROM cell

A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

BACKGROUND OF INVENTION

1. Field of the Invention

The invention relates to a high density read-only memory (ROM) cell, and more particularly, to a high density ROM cell having a structure similar to a metal oxide semiconductor (MOS) transistor.

2. Description of the Prior Art

As semiconductor technology progresses, circuits manufactured by semiconductor technology are widely used in electronic devices and computer systems. One example of these circuits is a ROM. The prior art combines MOS transistors with peripheral circuits to form ROMs. However, each of theses ROMs can only store one bit data. Since circuit area corresponds to the number of MOS transistors and peripheral circuits, a high capacity memory circuit will occupy a large area on a semiconductor chip. As a result, high capacity memory circuits cannot be satisfactorily integrated on a single wafer.

Please refer toFIG. 1showing a circuit diagram of a conventional ROM cell, wherein each MOS transistor is a ROM. As described above, each ROM cell can store only one bit of data; the data can be read under the control of word lines WL0, WL1, WL2, WL3. . . (four word lines are shown inFIG. 1) and bit lines BL0, BL1. . . (two bit lines are shown inFIG. 1).

As described above, in the conventional memory circuit, each ROM cell can store only one bit of data, and the circuit area corresponds to the number of these transistors and peripheral circuits. Thus, a high capacity memory circuit occupies a large area on a semiconductor chip, which means that high capacity memory circuits cannot be satisfactorily integrated on a single wafer. Accordingly, the cost of a high capacity memory circuit cannot be reduced, and the capacity of ROM is hardly improved. Thus, the prior art retains disadvantages which can be improved upon.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to provide a high density ROM cell to solve the problem mentioned above.

Briefly, a ROM cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

The present invention further provides a high density ROM cell installed on a silicon substrate for storing data. The ROM cell includes a plurality of first doped regions being of a second conductive type installed on the silicon substrate, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the plurality of first doped regions and the second doped region.

DETAILED DESCRIPTION

The present invention provides a high density ROM cell having a structure similar to a MOS transistor. The memory cell includes a plurality of drains, a common gate, and a common source. Since such kind of the structure composed of the common devices provides a manner for operating a plurality of drain signals, a single memory cell can store a plurality of bits of data, which is of higher density than that in the prior art. According to the first embodiment of the present invention, the plurality of drains are installed in a common drain doped region having a plurality of heavily doped regions, wherein each heavily doped region and the common doped drain region form a diode so that the plurality of drain signals passing through the plurality of heavily doped regions do not interfere with each other. In the second embodiment of the present invention, the plurality of drains are the plurality of drain doped regions separated by at least one extension structure of the common gate.

Please refer toFIG. 2showing a block diagram of the ROM cell, andFIG. 3showing a block diagram of an optimal variation of the ROM cell shown inFIG. 2, both of which are according to the first embodiment of the present invention. A gate230according to the first embodiment is made of polysilicon (POLY inFIG. 2and the following figures). A common drain doped region210and a common source doped region220are doped wells formed by a diffusion process (DIFF inFIG. 2and the following figures). In other related figures, such asFIG. 2,FIG. 3,FIG. 4,FIG. 7,FIG. 8, “P+” and “N+” represent respectively a P-type doped well having a higher relative doping density than that of a surrounding N-type well and a N-type doped well having a higher relative doping density than that of a surrounding P-type well. GND represents that the common source of the ROM cell is grounded.

The difference betweenFIG. 3andFIG. 2is the number of the heavily doped regions212a,212b,212c. . . The number of these heavily doped regions represents how many bits the ROM cell can store, which is equal to the number of drain signals employed. For instance, a ROM cell200having 5 heavily doped regions212a,212b,212c,212d,212e(212dand212eare not shown inFIG. 3) can store 5 bits. The following description is related to the first embodiment shown inFIG. 2, wherein the ROM cell200has 2 heavily doped regions212a,212bfor storing 2 bits.

According to the first embodiment shown inFIG. 2, the present invention provides a high density ROM cell200installed on a silicon substrate for storing data. The ROM cell200includes a first doped region210installed on the silicon substrate having a second conductive type (N-type in this embodiment; that is, the first doped region210is an N-type doped well), a plurality of first heavily doped regions212a,212b(two in this embodiment) installed in the first doped region210and having a first conductive type (P-type in this embodiment; that is, the first heavily doped regions212a,212bare P-type doped wells), a second doped region220installed on the silicon substrate having the second conductive type (N-type doped well), and a gate230installed on the surface of the silicon substrate and adjacent to the first doped region210and the second doped region220. The first doped region210is a drain doped region; the second doped region220is a source doped region. Each first heavily doped region of the plurality of heavily doped regions212a,212bforms a diode in cooperation with the first doped region210(described hereinafter) so that the plurality of drain signals (two in this embodiment, not shown inFIG. 2) respectively passing through the plurality of heavily doped regions212a,212bwill not interfere with each other.

Please refer toFIG. 2as well asFIG. 4showing a cross-section view of the ROM cell200. In this embodiment, the ROM cell200is installed in a doped well on the silicon substrate (P_SUB, P-Substrate inFIG. 4), and the doped well has the first conductive type (P-type in this embodiment; that is, the doped well is a P-type doped well). Such kind of structure is optional and does not limit the present invention. Moreover, the diode mentioned above is marked by a diode mark between the heavily doped region212(representing the heavily doped regions212a,212b) and the first doped region210inFIG. 4. When a first drain signal current (not shown) composed of the drain signals flows in sequence from a drain terminal215through the heavily doped region212(representing the heavily doped regions212a,212b) and the first doped region210, and even in the event it passes through the silicon substrate (in this embodiment, pass through the region adjacent to the gate230in the P-type doped well shown as P_SUB) and the second doped region220to the source terminal225under control of the gate230, the diode can prevent the first drain signals from flowing between the heavily doped regions212a,212b. Therefore, the plurality of drain signals (two in this embodiment, not shown inFIG. 2) respectively passing through the plurality of heavily doped regions212a,212bwill not interfere with each other.

Please refer toFIG. 5showing a circuit diagram of the ROM cell array, andFIG. 6showing a combination of the circuit inFIG. 5and a global bit line. The ROM cell200inFIG. 5andFIG. 6is an equivalent circuit to the ROM cell200inFIG. 2andFIG. 4, wherein a single ROM cell200can store a plurality of bits (2 bits in this embodiment) of data in order to provide a higher density on data storage. As shown inFIG. 5andFIG. 6, the plurality of bits of data can be read by a plurality of bit lines BL0, BL1(two in this embodiment). As shown inFIG. 5, the data read by the bit line BL0, BL1are transmitted to a bit line output SA. The global bit line GBL inFIG. 6controls a plurality of bit line switches610,611through a plurality of column selection lines C_SEL0, C_SEL1corresponding to the bit lines BL0, BL1, to multiplex data read by one of the bit lines BL0, BL1and transmit them to the bit line output SA. In other words, the circuit inFIG. 6is a combination of the circuit inFIG. 5and a Y-multiplexer (Y-MUX). Therefore, bothFIG. 5andFIG. 6show that the present invention provides higher storage density than the prior art. In addition, bit read values (BL0, BL1)=(0, 1), (1, 0), (0, 1), (1, 1) marked on the right side of word lines WL0, WL1, WL2, WL3inFIG. 5andFIG. 6correspond to the drain terminal215and the programmed (shown by a black dot) or unprogrammed (without black dot) status between the bit lines BL0, BL1of each ROM cell200.

In the present invention, the first conductive type is P-type and the second conductive type is N-type. However, it is optional and does not limit the present invention. In another possible embodiment of the present invention, the first conductive type can be N-type and the second conductive type can be P-type.

Please refer toFIG. 7showing a block diagram of a ROM cell, andFIG. 8showing a block diagram of an optimal variation of the ROM cell shown inFIG. 7, both of which are according to the second embodiment of the present invention. A gate730according to the second embodiment is also made of polysilicon. A plurality of drain doped regions710a,710b,710c. . . and a common source doped region720are doped wells formed by a conventional diffusion process.

The difference betweenFIG. 8andFIG. 7is in the number of plurality of drain doped regions710a,710b,710c. . . and corresponding gate extension structures732b,732c. . . The number of the plurality of drain doped regions represents how many bits the ROM cell can store, which is equal to the number of the plurality of drain signals. For instance, a ROM cell700having N drain doped regions710a,710b,710c. . .710n(representing respectively the first, the second, the third . . . the Nthdrain doped region) can store N bits. The following description is related to the second embodiment shown inFIG. 7, wherein the ROM cell700has 2 drain doped regions710a,710bfor storing 2 bits.

According to the second embodiment shown inFIG. 7, the present invention provides another high density ROM cell700installed on a silicon substrate for storing data. The ROM cell700includes a plurality of first doped regions710a,710binstalled on the silicon substrate and having a second conductive type (N-type in this embodiment; that is, the plurality of first doped regions710a,710bare N-type doped wells), a second doped region720installed on the silicon substrate having the second conductive type (N-type doped well), and a gate730installed on the surface of the silicon substrate and adjacent to the plurality of first doped regions710a,710band the second doped region720. The plurality of first doped regions710a,710bare drain doped regions, the second doped region720is a source doped region, and the gate730has at least one extension structure located respectively between one first doped region710aand the other first doped region710bso that a plurality of drain signals (two in this embodiment, not shown inFIG. 7) respectively passing the plurality of first doped regions710a,710bwill not interfere with each other.

In the present invention, the ROM cell700is installed in a doped well (not shown inFIG. 7) on the silicon substrate having the first conductive type (P-type in this embodiment; that is, the doped well is a P-type doped well). Such kind of structure is optional, and does not limit the present invention.

Please refer toFIG. 9showing a circuit diagram of the ROM cell array, andFIG. 10showing a combination of the circuit inFIG. 9and a global bit line. The ROM cell700inFIG. 9andFIG. 10is an equivalent circuit to the ROM cell700inFIG. 7, wherein a single ROM cell700can store a plurality of bits (2 bits in this embodiment) of data in order to provide a higher density on data storage. As shown inFIG. 9andFIG. 10, the plurality of bits of data can be read by a plurality of bit lines BL0, BL1(two in this embodiment). As shown inFIG. 9, the data read by the bit lines BL0, BL1are transmitted to a bit line output SA. The global bit line GBL inFIG. 6controls a plurality of bit line switches1010,1011, through a plurality of column selection lines C_SEL0, C_SEL1, to multiplex data read by one of the bit lines BL0, BL1and transmit them to the bit line output SA. In other words, the circuit inFIG. 10is a combination of the circuit inFIG. 9and a Y-MUX. Therefore, bothFIG. 9andFIG. 10show that the present invention provides higher storage density than the prior art. In addition, bit read values (BL0, BL1)=(0, 1), (1, 0), (0, 1), (1, 1) marked on the right side of word lines WL0, WL1, WL2, WL3inFIG. 9andFIG. 10correspond to drain terminals715a,715band the programmed (shown by a black dot) or unprogrammed (without black dot) status between the bit lines BL0, BL1of each ROM cell700.

In the present invention, the first conductive type is P-type and the second conductive type is N-type. However, it is optional and does not limit the present invention. In another possible embodiment of the present invention, the first conductive type can be N-type and the second conductive type can be P-type.

In contrast to the prior art, the high-density ROM cell according to the present invention has a plurality of drains, a common gate, and a common source. Since such kind of the structure composed of the common devices provides a manner for operating a plurality of drain signals, a single memory cell can store a plurality bits of data, which has a higher density than that of the prior art, and accordingly, the circuit area can be reduced.

In addition, the high-density ROM cell according to the present invention has a structure similar to a MOS transistor so that it can be applied in any of the related products, and designed or manufactured in a easy manner.