Liquid crystal display device

An LCD device, which is cost effective, is discussed. According to one embodiment, the LCD device includes a timing controller to generate an initial POL signal; a signal stabilizer to receive the initial POL signal from the timing controller and a constant voltage from a source, and to generate a stabilized POL signal using the received constant voltage and the received initial POL signal; and a common voltage generator to generate a common voltage signal using the stabilized POL signal and to supply the generated common voltage signal to an LCD panel.

This application claims the benefit of the Korean Patent Application No. 10-2005-0057575 filed on Jun. 30, 2005 in Republic of Korea, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device in which a POL signal from a timing controller is stabilized without using a regulator.

2. Discussion of the Related Art

Demands for various display devices have increased with development of an information society. Accordingly, efforts have been made to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some species of flat display devices have already been used as displays for different types of equipment.

Among the various flat display devices, liquid crystal display (LCD) devices have been widely used due to their advantageous characteristics of high picture quality, thin profile, lightness in weight, and low power consumption. As a result, the LCD devices are a substitute for Cathode Ray Tubes (CRTs). In addition to mobile type LCD devices such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.

Despite various technical developments in the LCD technology having applications in different fields, research in enhancing the picture quality of the LCD device has been, in some respects, lacking as compared to other features and advantages of the LCD device.

In order to use LCD devices in various fields as a general display, one of the keys to developing such LCD devices depends on whether the LCD device can implement a high quality picture such as high resolution and high luminance with a large-sized screen while maintaining lightness in weight, thin profile, and low power consumption.

A general LCD device includes an LCD panel for displaying images, and a driver for applying a driving signal to the LCD panel. The LCD panel generally includes first and second substrates bonded to each other with a certain space therebetween, and a liquid crystal layer formed between the first and second substrates by injection.

The first substrate (TFT array substrate) according to a related art includes a plurality of gate lines arranged along a first direction at fixed intervals, a plurality of data lines arranged along a second direction perpendicular to the first direction at fixed intervals, a plurality of pixel electrodes formed in a matrix arrangement at pixel regions where the gate lines cross the data lines, and a plurality of thin film transistors (TFTs) switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode.

The second substrate (color filter substrate) according to a related art includes a black matrix layer that shields light from certain portions except the pixel regions, R/G/B color filter layers for displaying various colors, and a common electrode for producing the image.

The common electrode is supplied with a common voltage signal generated from a common voltage generator. In case of a line inversion LCD device, the common voltage signal has an alternating current type inverted per horizontal period. At this time, the common voltage signal is generated by a POL signal from a timing controller. In more detail, a driver of a related art LCD device will be described below with reference toFIG. 1.

FIG. 1illustrates a driver of a related art LCD device. Referring toFIG. 1, a direct current (DC)-to-DC converter101is supplied with an input voltage VCC from a system100and boosts or decompresses the input voltage VCC to output a reference voltage VDD, a high gate voltage VGH, and a low gate voltage VGL. The reference voltage VDD is supplied to a regulator102. The regulator102stabilizes the reference voltage VDD and supplies the stabilized reference voltage VDD to a timing controller103as a power source. The timing controller103generates a POL signal using the stabilized reference voltage VDD and supplies the POL signal to a common voltage generator104. The common voltage generator104inverts and amplifies the received POL signal.

The regulator102supplies the power source (stabilized reference voltage VDD) to the timing controller103to operate the timing controller103. At this time, since the reference voltage output from the regulator102is a constant voltage, the POL signal is stably output from the timing controller103. If the input voltage VCC from the system100is supplied to the timing controller103without the regulator102, the POL signal output from the timing controller103is easily varied depending on the input voltage VCC from the system100. If the POL signal is varied, a common voltage signal VCOM generated by the POL signal is also varied, which is a problem.

To prevent the common voltage signal VCOM from being varied, the LCD device is provided with the regulator102. However, a problem arises in that the regulator102is expensive and increases the overall cost of the LCD device.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an LCD device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide an LCD device in which a constant voltage is supplied using a logic buffer or a transistor to stabilize a POL signal from a timing controller without using an expensive regulator.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an LCD device according to an embodiment of the present invention includes a timing controller supplied with an input voltage from a system to output a POL signal, a signal stabilizer supplied with an external constant voltage and the POL signal from the timing controller to stabilize the external constant voltage and the POL signal, and a common voltage generator supplied with the POL signal stabilized by the stabilizer to output a common voltage signal, supplying the common voltage signal to an LCD panel.

According to one aspect of the present invention, there is provided an LCD device comprising a timing controller to generate an initial POL signal; a signal stabilizer to receive the initial POL signal from the timing controller and a constant voltage from a source, and to generate a stabilized POL signal using the received constant voltage and the received initial POL signal; and a common voltage generator to generate a common voltage signal using the stabilized POL signal and to supply the generated common voltage signal to an LCD panel.

According to another aspect of the present invention, there is provided an LCD device comprising: a timing controller to generate an initial POL signal; a signal stabilizer connected between the timing controller and a common voltage generator, and generating a stabilized POL signal using the initial POL signal; and the common voltage generator to generate a common voltage signal using the stabilized POL signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2illustrates an LCD device according to an embodiment of the present invention. All the components of the LCD device are operatively coupled.

As shown inFIG. 2, the LCD device according to one embodiment of the present invention includes an LCD panel211, a data driver211a, a gate driver211b, a timing controller203, a DC-to-DC converter201, a signal stabilizer202, and a common voltage generator204. The display panel211is provided with m×n pixels arranged in a matrix arrangement, m data lines (D1to Dm) vertically crossing n gate lines (G1to Gn), and thin film transistors (TFTs) formed at regions where the data lines cross the gate lines.

The data driver211asupplies data to the data lines D1to Dm of the LCD panel211. The gate driver211bsupplies scan signals to the gate lines G1to Gn. The timing controller203outputs respectively gate control signals GCS and data control signals DCS to control the gate driver211band the data driver211ausing synchronizing signals from an interface circuit205, and outputs to the signal stabilizer202a POL signal required to generate a common voltage signal VCOM. The DC-to-DC converter201generates voltages supplied to the LCD panel211. The signal stabilizer202stabilizes the POL signal received from the timing controller203as a constant voltage, and outputs the stabilized POL signal to the common voltage generator204. The common voltage generator204receives the stabilized POL signal output from the signal stabilizer202and generates the common voltage signal VCOM using the stabilized POL signal to supply it to the LCD panel211.

A system200supplies appropriate signals such as vertical/horizontal synchronizing signals, clock signals and data (RGB) to the interface circuit205through a low voltage differential signaling transmitter of a graphic controller and supplies an input voltage VCC generated from its power source to the respective digital circuit devices203,211a,211band205, the common voltage generator204and the DC-to-DC converter201.

Meanwhile, in the LCD panel211, a liquid crystal is injected or otherwise provided between two glass substrates. Various structures of these two glass substrates are known and can be present in the LCD panel211. In this embodiment, the data lines D1to Dm and the gate lines G1to Gn formed on the lower glass substrate of the LCD panel211vertically cross each other. The TFTs formed at crossing points between the data lines D1to Dm and the gate lines G1to Gn supply data on the data lines D1to Dn to liquid crystal cells C1cin response to the scan signals from the gate lines G1to Gn. To this end, a gate electrode of each TFT is connected to a corresponding gate line and its source electrode is connected to a corresponding data line. A drain electrode of each TFT is connected to a pixel electrode of a corresponding liquid crystal cell C1c.

In one embodiment, a black matrix layer and color filter layers and a common electrode are formed on the upper glass substrate of the LCD panel211. Polarizing plates whose polarizing axes vertically cross each other are attached onto the upper and lower glass substrates of the LCD panel211. An alignment film is formed on an inner side adjoining the liquid crystal to set a pre-tilt angle of the liquid crystal. A storage capacitor Cst is formed in each liquid crystal cell C1cof the LCD panel211. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell C1cand a previous gate line or between the pixel electrode of the liquid crystal cell C1cand a common electrode line to uniformly maintain a voltage of the liquid crystal cell C1c.

The data driver211aconverts digital video data (RGB) to analog gamma voltages corresponding to a gray level in response to the data control signals DCS output from the timing controller203and supplies the analog gamma voltages to the data lines D1to Dm. The input voltage VCC from the power source of the system200is supplied to a data drive integrated circuit in which the data driver211ais integrated.

On the other hand, the gate driver211bsequentially supplies the scan pulses to the gate lines G1to Gn in response to the gate control signals GCS output from the timing controller203and selects a horizontal line of the LCD panel211supplied with the data. The input voltage VCC from the power source of the system200is supplied to a gate drive integrated circuit in which the gate driver211bis integrated.

The timing controller203generates the gate control signals GCS for controlling the gate driver211b, the data control signals DCS for controlling the data driver211a, and the POL signal required to generate the common voltage from the common voltage generator204using the vertical/horizontal synchronizing signals input from the graphic controller of the system200through the interface circuit205.

The timing controller203realigns the digital video data (RGB) input from the graphic controller of the system200through the interface circuit205and supplies the realigned digital video data to the data driver211a. The input voltage VCC from the power source of the system200is supplied to the timing controller203.

The interface circuit205lowers voltage levels of the signals input from the graphic controller of the system200and a low voltage differential signaling receiver and enhances frequencies of the signals, so as to reduce the number of signal lines required between the system200and the timing controller203. The input voltage VCC from the power source of the system200is supplied to the interface circuit205.

An electromagnetic interference (EMI) filter is provided between the interface circuit205and the timing controller203to reduce EMI generated due to high voltage and high frequency components of the signals supplied from the interface circuit205to the timing controller203.

Meanwhile, the DC-to-DC converter201boosts or decompresses the input voltage VCC from the power source of the system200through a connector to generate a voltage to be supplied to the LCD panel211. To this end, the DC-to-DC converter201includes an output switching device for switching output voltages at an output terminal, and a pulse width modulator (PWM) or a pulse frequency modulator (PFM) for boosting or decompressing the output voltages by controlling a duty ratio or frequency of a control signal of the output switching device. The pulse width modulator enhances the output voltages of the DC-to-DC converter201by enhancing the duty ratio of the control signal of the output switching device or lowers the output voltages of the DC-to-DC converter201by lowering the duty ratio of the control signal of the output switching device.

The pulse frequency demodulator enhances the output voltages of the DC-to-DC converter201by enhancing the frequency of the control signal of the output switching device or lowers the output voltages of the DC-to-DC converter201by lowering the frequency of the control signal of the output switching device. The output voltages of the DC-to-DC converter201are voltages/signals output from the DC-to-DC converter201.

The output voltages of the DC-to-DC converter201include a reference voltage VDD of, e.g., 5V or greater, gamma reference voltages GMA1˜GMA10less than ten stages, a high gate voltage VGH of, e.g., 15V or greater, and a low gate voltage VGL of, e.g., −4V or less. The gamma reference voltages GMA1˜GMA10are generated by partial pressure of the reference voltage VDD. The reference voltage VDD and the gamma reference voltages GMA1˜GMA10are supplied to the data driver211aas analog gamma voltages. The high gate voltage VGH is a high logic voltage of the scan pulses set at a threshold voltage of the TFT or greater and is supplied to the gate driver211b. The low gate voltage VGL is a low logic voltage of the scan pulses set at an off voltage of the TFT and is supplied to the gate driver211b.

The signal stabilizer202is supplied with the POL signal output from the timing controller203and with the reference voltage VDD output from the DC-to-CD converter201. In the LCD device according to the present invention, since the timing controller203is supplied with the input voltage VCC from the system200, which is not a constant voltage, the POL signal output from the timing controller203is not constant and varies depending on the input voltage VCC.

To prevent the POL signal from being varied, the signal stabilizer202is provided in the present invention. The signal stabilizer202processes the POL signal output from the timing controller203and generates a stabilized POL signal (a constant high/low voltage) using the reference voltage VDD. The signal stabilizer202thus supplies the POL signal having the constant high voltage to the common voltage generator204. A logic buffer, a plurality of transistors, or other similar elements may be used as the signal stabilizer20. However, a more detailed operation of the signal stabilizer202will be discussed later referring toFIG. 4.

The common voltage generator204generates the common voltage signal VCOM using the POL signal output from the signal stabilizer202. At this time, since the POL signal input to the common voltage generator204is a constant voltage, the common voltage signal VCOM is stably output from the common voltage generator204.

The common voltage generator204will now be described in more detail.

FIG. 3is a circuit diagram illustrating the common voltage generator204ofFIG. 2according to an embodiment of the present invention.

As shown inFIG. 3, the common voltage generator204includes an inversion amplifier301for inverting and amplifying a differential voltage between the POL signal input through an inversion terminal of the inversion amplifier301and an offset voltage (Voffset) input through a non-inversion terminal of the inversion amplifier301, and a buffer302for alternately switching and buffering first and second transistors Q1and Q2depending on a level of the voltage obtained from the inversion amplifier301, feeding the output values back to the inversion amplifier301through a resistor R3, and amplifying the feedback signals.

The voltage output from the buffer302is the common voltage VCOM.

The aforementioned common voltage generator204outputs inverted and amplified signals depending on a set gain, i.e., a resistance ratio (R1/R2), if the POL signal is input to the inversion amplifier301per one horizontal synchronization (1 Hsync).

The signals output from the inversion amplifier301are input to respective base terminals of the first and second transistors Q1and Q2. Thus, the first and second transistors Q1and Q2alternately switch the supplied power source to generate the common voltage signal VCOM of a constant globular wave. In other words, if the signals output from the inversion amplifier301are at high level, the first transistor Q1corresponding to an NPN transistor applied with the high potential voltage is turned on while the second transistor Q2corresponding to a PNP transistor is turned off, so that the common voltage signal VCOM of high level is output. If the signals output from the inversion amplifier301are at low level, the second transistor Q2corresponding to the PNP transistor applied with the low potential voltage is turned on while the first transistor Q1corresponding to the NPN transistor is turned off, so that the common voltage signal VCOM of low level is output.

The common voltage generator204further includes a noise attenuator303that attenuates the signal output from the inversion amplifier301. The noise attenuator303includes a capacitor C connected between an output terminal of the inversion amplifier301and the inversion terminal of the inversion amplifier301, and a resistor R2connected between the output terminal of the inversion amplifier301and an input terminal of the buffer302.

FIG. 4is a circuit diagram illustrating the signal stabilizer202ofFIG. 2according to an embodiment of the present invention.

As shown inFIG. 4, the signal stabilizer202includes first and second transistors Q3and Q4. The first transistor Q3includes a base terminal to which the POL signal from the timing controller203is input, a collector terminal to which the reference voltage VDD from the DC-to-DC converter201is input, and an emitter terminal connected to a ground terminal. The second transistor Q4includes a base terminal connected to the collector terminal of the first transistor Q3, a collector terminal to which the reference voltage VDD is input, and an emitter terminal connected to the ground terminal. The collector terminal of the second transistor Q2is connected to the inversion terminal of the inversion amplifier301provided in the common voltage generator204, through a resistor R1(FIG. 3), so as to supply the stabilized POL signal to the common voltage generator204. Resistors such as R10, R20, R30, R40, etc. are included in the signal stabilizer202.

The operation of the aforementioned signal stabilizer202will be now described in detail.

If the POL signal input to the signal stabilizer202is at high level, the first transistor Q3is turned on so that a ground voltage GND is supplied to the collector terminal of the first transistor Q3. As a result, the second transistor Q4whose base terminal is connected to the collector terminal of the first transistor Q3is turned off. Therefore, the reference voltage VDD is supplied to the collector terminal of the second transistor Q2. The reference voltage VDD supplied to the collector terminal of the second transistor Q2is then supplied to the inversion terminal of the inversion amplifier301(FIG. 3) provided in the common voltage generator204, as a stabilized POL signal.

On the other hand, if the POL signal input to the signal stabilizer202is at low level, the first transistor Q3is turned off so that the reference voltage VDD is supplied to the collector terminal of the first transistor Q3. As a result, the second transistor Q4whose base terminal is connected to the collector terminal of the first transistor Q3is turned on. Therefore, the ground voltage GND is supplied to the collector terminal of the second transistor Q2and to the inversion terminal of the inversion amplifier204.

As described above, the signal stabilizer202supplies the reference voltage VDD or the ground voltage GND to the inversion terminal of the inversion amplifier301through the first and second transistors Q3and Q4, so that the common voltage generator204generates the common voltage signal VCOM. At this time, since the reference voltage VDD output to the common voltage generator204by the signal stabilizer202is a constant voltage, the common voltage signal VCOM is stably generated and output from the common voltage generator204.

In the related art LCD device, to stably output a POL signal from a timing controller, a constant voltage is directly supplied to the timing controller using a regulator which has a high cost. However, in the LCD device according to the present invention, the input voltage VCC is supplied to a timing controller, and only the POL signal output from the timing controller is stabilized through a logic buffer or transistor(s). Therefore, in the present invention, the regulator for supplying the constant voltage to the timing controller is not required and eliminated.

Accordingly, the LCD device according to the present invention has advantages including, but not limited to, the following.

Since the constant voltage is supplied using the logic buffer or the transistor(s), it is possible to stabilize a POL signal output from the timing controller without using a regulator, which is expensive. As a result, a cost-effective driver for a display device can be provided in an effective manner.