Methods for fabricating memory cells having fin structures with smooth sidewalls and rounded top corners and edges

Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

FIELD OF THE INVENTION

The present invention relates to the fabrication of memory cells.

BACKGROUND

Consumer electronic products such as televisions, digital cameras, cellular telephones, media content players, etc., help to satisfy consumer demand for basic communications and entertainment services. Data storage components play an important role in the operation of these devices. Data storage devices include RAM, ROM, flash memory products, etc.

An important feature of data storage devices is memory cell density. There are many approaches to increasing the memory cell density of memory arrays. One approach involves reducing the channel length between the source and the drain of transistors associated with memory cells in a memory array. This allows the size of each memory cell to be reduced which in turn facilitates the provision of denser memory arrays. Another approach to increasing memory cell density is embodied in a commercially available flash memory product called MirrorBit™ Technology from Spansion, located in Sunnyvale, Calif.

In flash memory arrays that use MirrorBit technology, the use of MirrorBit memory cells effectively doubles their intrinsic density by storing two physically distinct bits on opposite sides of the memory cells. Each bit that is stored within a cell serves as a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.

An exemplary MirrorBit™ memory device includes a semiconductor substrate with spaced apart source and a drain regions (both typically having N-type conductivity) formed in a substrate. An oxide-nitride-oxide (ONO) layered stack is formed on the top surface of the substrate between the two bit lines. A gate electrode, which typically comprises an N or N+ polysilicon layer, is formed over the ONO stack. The ONO stack includes a first or bottom dielectric layer (often referred to as a bottom tunnel oxide), a charge storing nitride layer, and a second or top dielectric layer of oxide.

Some challenges associated MirrorBit™ devices are related to structural and functional features of the device. For example, it can be difficult to reduce the size or pitch of the cell because the storage element of the above-mentioned flash memory cell can be planar (the oxide, nitride and oxide layers are all horizontal layers formed one on top of the other on the silicon substrate). Moreover, as it regards operations such as the erasure of a Mirrorbit™ cell such as by hot hole injection, because hot holes bombard the interface between the substrate and the bottom tunnel oxide, the interface as well as the bottom tunnel oxide can be damaged causing undesirable interface states and degraded reliability over program/erase cycling.

In order to increase memory density, a FIN structure is desirable in more advanced non-volatile memory technology. However, conventional fabrication methodologies can provide results that can affect the operation of the fabricated MirrorBit™ devices. Problematic features of devices fabricated from conventional methodologies include rough FIN sidewall silicon surfaces, sharp corners and edges in the FIN structure between top surface and sidewalls, non-uniform coverage of the tunnel oxide and early breakdown at the corners and edges due to enhanced electric field.

It should be appreciated that rough sidewall silicon surfaces can result in interface traps. Because of mismatched surface orientations of the silicon FIN sidewalls and the tunnel oxide layer formed over them, interface stresses can result. Importantly, defects can be easily formed at points in the interface where the materials are imperfectly matched.FIG. 1shows how the formation of the FIN structure can result in damaged sidewall surfaces101that include terraces103in the sidewalls that are the root cause of high tunnel oxide-silicon interface trap density. Interface traps trap hot electrons that are intended to tunnel through the oxide layer.

In addition, sharp corners and edges of the FIN structure between its top surface and sidewalls can contribute to breakdown at the corners and edges. Referring again toFIG. 1, even though an electric field can be uniformly provided the electric field that results can be concentrated and more intense at the top edges105of the FIN structure. As a result, the likelihood of tunnel oxide breakdown at such points is greater. Tunnel oxide breakdown can cause a loss of charge from the charge storage cell structure. As a result, programmed data can be lost.

As can be seen from the above discussion, conventional approaches to fabricating memory cells are inadequate. These approaches can precipitate undesirable consequences that negatively affect device function.

SUMMARY OF THE INVENTION

Methods for fabricating memory cells having FIN structures with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures is annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

It should be noted that like reference numbers refer to like elements in the figures.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described in detail with reference to a various embodiments thereof as illustrated in the accompanying drawings. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without using some of the implementation details set forth herein. It should also be understood that well known operations have not been described in detail in order to not unnecessarily obscure the present invention.

Methods for Fabricating Memory Cells having FIN Structures with Smooth Sidewalls and Rounded Top Corners and Edges

FIG. 2Ashows a cross section of a memory cell200having a FIN structure with smooth sidewalls and rounded top corners and edges according to one embodiment of the invention. In this embodiment, memory cell200includes silicon FIN structure201, nitride charge storage layer205, oxide layer203and polycrystalline layer207.

Referring toFIG. 2A, memory cell200includes a FIN structure201that possesses smooth sidewall silicon surfaces201aand201band rounded top corners and edges201cand201dbetween the FIN structure top surface202and sidewall surfaces201aand201b. Moreover, conformal oxide layer203is formed over FIN structure201.FIG. 2Bshows a three-dimensional depiction of the FIN component of memory cell200that shows source and drain regions. As shown inFIG. 2B, as used herein the term “top corners” and “edges” is intended to refer to the top corners and edges201cand201dof FIN structure201in both source and drain regions (see encircled elements). In one embodiment, the rounded top corners and edges serve to provide a memory cell with improved data retention, improved data disturbance immunity and improved memory cell reliability.

In one embodiment, operations discussed in detail herein result in the aforementioned smooth sidewall surfaces201aand201band rounded top corners and edges201cand201dbetween top surface202and sidewall surfaces201aand201bof FIN structure201. In one embodiment, smooth sidewall surfaces201aand201bare achieved through oxygen radical oxidation, wet oxide deposition and annealing operations described in detail herein. In one embodiment, as is discussed in detail herein a sacrificial oxide is formed and then removed with a high selectivity oxide etchant. In one embodiment, a concentrated hydro-fluoride acid is used to remove the sacrificial oxide. Moreover, in one embodiment, the high selectivity oxide etchant prevents silicon surface roughening. Subsequently, the semiconductor FIN structure201is annealed to further smooth its surface. In one embodiment, semiconductor FIN structure201is annealed in a hydrogen environment. In one embodiment, the annealing of the surface of FIN structure201reduces the number of surface terraces in the FIN sidewall structure and other imperfections found therein. These operations are discussed in detail herein below.

In one embodiment, the above discussed rounded top corners201cand201dare achieved through the use of the aforementioned sacrificial oxide application process that causes a rounding of the top corners and edges of FIN structure201. Importantly, in one embodiment, the sacrificial oxide application process causes an elimination of the sharp edges that can be a problematic feature of conventional FIN structures. In one embodiment, the sacrificial oxide can be formed by thermal radical oxidation (e.g., steam oxidation) in a thermal furnace. In another embodiment, the sacrificial oxide can be formed by oxygen radical oxidation in a single wafer chamber. In one embodiment, higher temperature and pressure in the oxygen radical oxidation process are used to enhance top corner and edge rounding.

In one embodiment, scaling is facilitated because of reduced breakdown of oxide at the top corners and edges of the FIN structure and trapping of charge at points in the interface between the FIN structure and the tunnel oxide layer that can be aggravated as the size of FIN devices are made smaller.

FIG. 3shows an array architecture300that employs memory cells such as are described with reference toFIG. 2A. Array300includes a plurality of the word lines360running in one direction and a plurality of overlying metal interconnects302running in the perpendicular direction. The metal interconnects302deliver a voltage to the underlying source/drain regions358through metal interconnects304.FIG. 3also shows two adjacent cells354labeled “cell1” and “cell2” inFIG. 3. The two cells354share a common source/drain region358. Operations in the process by which the cells are fabricated are described below.

Process Flow for Forming Memory Cells Having FIN Structures with Smooth Sidewalls and Rounded Top Corners and Edges

FIGS. 4A-4Eshow a series of cross sections illustrating the process flow involved in forming memory cells having FIN structures401a-401cwith smooth sidewalls403aand403band rounded top corners and edges405aand405baccording to one embodiment of the invention is shown.

As shown inFIG. 4A, in an initial operation a plurality of FIN structures401a-401care formed in a substrate wafer.

As shown inFIG. 4B, subsequent to one or more operations that result in the plurality of FIN structures,401a-401c, shown inFIG. 4A, a sacrificial oxide402is formed on FIN structures401a-401c. In one embodiment, sacrificial oxide402can be formed by thermal radical oxidation (e.g., a type of oxygen radical oxidation) in a thermal furnace. In another embodiment, sacrificial oxide402can be formed by plasma radical oxidation (e.g., a type of oxygen radical oxidation) in a single wafer chamber. In one embodiment, higher temperature and pressure in the plasma process can be used to enhance top corner and edge rounding. In one embodiment, sacrificial oxide402is applied in a manner that causes a rounding of the top corners and edges of the FIN structure. In particular, in one embodiment, sacrificial oxide402is applied such that sacrificial oxide402that is formed over the corners of the FIN structure is tuned, such as through the adjustment of pressure and temperature, to etch more actively than that which is applied along the FIN sidewall surfaces, as is illustrated by the representation of the etched FIN structure401bshown at the upper right side ofFIG. 4B. Importantly, this process provides a first level of FIN surface smoothing that acts to eliminate the sharp corners edges that can promote oxide breakdown.

In one embodiment, the plasma process discussed herein can involve the use of both continuous and pulsed plasma. In one embodiment, the plasma process uses 1 W to 5000 W plasma power, at 1 mTorr to 760 Torr, with an oxygen flow rate of 1 sccm (standard cubic centimeter per minute) to 20 slm (standard cubic liter per minute), and N2 flow rate of 1 sccm (standard cubic centimeter per minute) to 20 slm (standard cubic liter per minute). In one embodiment, the thermal process uses 50-1300 C thermal temperature, at 1 Torr to 760 Torr with a hydrogen percent in N2 equal to 1 to 33 percent.

As shownFIG. 4C, subsequent to one or more operations that result in the cross section shown inFIG. 4B, the sacrificial oxide is removed with a high selectivity oxide etchant to expose FIN structures401a-401chaving rounded top corners and edges405aand405b. In one embodiment, a concentrated hydro-fluoride acid is used to remove the sacrificial oxide shown inFIG. 4B. In one embodiment, the high selectivity oxide etchant is designed to aggressively etch the sacrificial oxide and to forego the etching of the silicon material from which FIN structure401is formed so as to prevent the roughening of the silicon surfaces of FIN structure401. In one embodiment, a 49 percent solution of hydro-fluoride acid can be used as the oxide etchant. In other embodiments, other solutions may be used.

As shown inFIG. 4D, subsequent to the execution of one or more operations that result in the cross section shown inFIG. 4C, the semiconductor FIN structures401a-401care annealed to provide further smoothing of the surface of the FIN structures (in addition to the smoothing provided by the operations described with reference toFIG. 4B). In one embodiment, FIN structures401a-401care annealed in a hydrogen environment. In one embodiment, the annealing of the surfaces of FIN structures401a-401cprovides a fine tuned smoothing of the surfaces of FIN structures401a-401cwhich targets FIN sidewall surface imperfections404such as terraces as is shown at right inFIG. 4D(as contrasted with the general smoothing provided by the operations described with reference toFIG. 4B). 7. In one embodiment, a hydrogen anneal at a temperature of 600-1000 C at a pressure of 1 mTorr to 760 Torr using a hydrogen flow rate of 1 sccm to 10 slm for a period of time of 1 second to 1 hour is performed. In other embodiments, other temperatures, pressures, hydrogen flow rates and times can be used.

As shown inFIG. 4E, subsequent to the execution of one or more operations that result in the cross section shown inFIG. 4D, a tunnel oxide406is formed over FIN structures401a-401c, a nitride charge trapping layer408is formed over the tunnel oxide and a top oxide410is formed over the nitride layer (shown only over401binFIG. 4Efor clarity). Thereafter, typical SONOS steps can be performed.

EXEMPLARY ADVANTAGES

Low Interface Trap Density

In one embodiment, a FIN charge cell structure that possesses a low interface trap density is provided. In conventional FIN charge cell structures, interface traps can develop at the interface of the FIN structure (e.g.,201inFIG. 2A) and the tunnel oxide layer (e.g.,203inFIG. 2A) of the FIN charge cell structure that trap hot electrons that are intended to tunnel through the tunnel oxide layer. The charge bottleneck can cause the speed of the device to be slowed as a programming of the device requires the charge trap to be filled before the charge storage space is filled to effect programming. In contrast, to erase the charge from the charge cell structure, the charge trap must be emptied before the substrate is emptied to effect erasure. It is important to note that the reading of memory storage cells can involve the detection of a threshold voltage. For example, in one embodiment, a high threshold voltage reading can indicate that a memory cell is programmed and a low threshold voltage reading can indicate that the memory cell is erased. However, because charge that is trapped in interface traps can cause a threshold voltage Vth to remain until the trapped charge is emptied, even when the charge in a memory storage cell has been emptied during the erasure process, a “programmed” reading may continue to be indicated. In one embodiment, the herein described operations result in a smoothing of sidewall surfaces of FIN structures which enables the provision of FIN charge cell structures that possess low interface trap density (see discussion below).

Smooth FIN Sidewall Surfaces

In one embodiment, smooth sidewall silicon surfaces in FIN charge storage structures are provided. Because of the surface orientation (110) of the silicon FIN sidewalls (e.g.,201aand201binFIG. 2A), the silicon FIN sidewalls and the material used to form the tunnel oxide (e.g.,203inFIG. 2A) can be imperfectly matched at the atomic level and may not form perfect bonds. The resultant imperfections that form in the interface between the FIN sidewalls and the tunnel oxide can cause stress in the interface between the FIN sidewalls and the tunnel oxide. Importantly, defects can be easily formed at points in the interface where the materials are imperfectly matched. Consequently, interface traps can be formed that trap charge (e.g., hot electrons) that is intended to tunnel through the oxide layer.

In one embodiment, the operations discussed above with reference toFIGS. 4A-4Eresult in smooth FIN sidewall silicon surfaces. In one embodiment, the application of the sacrificial oxide (seeFIG. 4B) provides general smoothing and shaping of the FIN sidewall surfaces while the annealing step (seeFIG. 4D) provides fine tuned smoothing that smoothes microscopic sidewall surface imperfections that may be present in the FIN sidewalls. Accordingly, the processes embodied in exemplary embodiments provide multiple levels of smoothing that result in optimally smooth FIN sidewall surfaces. The smooth FIN sidewall surfaces promote a reduction in the formation of defects in the interface between the FIN sidewall surfaces (e.g.,201aand201binFIG. 2A) and the tunnel oxide (e.g.,203inFIG. 2A) that can lead to the formation of interface traps.

Rounded Top Corners and Edges in FIN Structure Between Top Surface and Sidewall

In one embodiment, a FIN charge storage cell structure that features rounded top corners and edges of the FIN structure (201cand201dinFIG. 2A) is provided. Even though an electric field may be uniformly provided to the FIN structure of a transistor formed conventionally during normal operation of the transistor, the electric field that results can be concentrated or more intense at sharp top corners and edges of the FIN structure. As a result the likelihood of breakdown at such points is greater. Breakdown can cause a loss of charge for the charge storage cell structure. As a result, programmed data stored therein can be lost.

In one embodiment, as discussed above with reference toFIG. 4B, the sacrificial oxide is applied in a manner that causes a rounding of the top corners and edges of the FIN structure. In one embodiment, the sacrificial oxide is applied such that the sacrificial oxide that is formed over the corners of the FIN structure is tuned, such as through adjustments to pressure and temperature, to etch more actively than that which is applied along the FIN sidewall surfaces. Importantly, this process eliminates the sharp top corners and edges that can promote breakdown.

In one embodiment, again as discussed above with reference toFIG. 4B, the sacrificial oxide can be formed with steam oxidation in a thermal furnace. In another embodiment, the sacrificial oxide can be formed by plasma radical oxidation in a single wafer chamber. In one embodiment, through tuning, the higher temperature and pressure in the plasma radical oxidation process can be used to enhance rounding of the top corners and edges of the FIN structure.

Resistant to Breakdown at Top Corners and Edges

In one embodiment, a FIN charge cell structure (e.g.,200inFIG. 2A) that is resistant to breakdown at the top corners and edges (e.g.,201cand201dinFIG. 2A) of the associated FIN structure is provided. Because early breakdown at such top corners and edges can be caused by the enhanced intensity and concentration of an applied electric field as discussed above, device operation can be degraded. In one embodiment, the above discussed rounding of the top corners and edges of the FIN structure can provide the device with a robust resistance to breakdown at top corners and edges of the FIN structure.

Uniform Tunnel Oxide Coverage

In one embodiment, because of the operations described herein that result in rounded FIN top corners and edges, uniform tunnel oxide coverage is facilitated. As a result the likelihood of breakdown at such points is further reduced.

Exemplary Operations for Fabricating Memory Cells Having Fin Structures with Smooth Sidewalls and Rounded Top Corners and Edges

FIG. 5shows a flowchart500of the steps performed in a method for fabricating memory cells having FIN structures with smooth sidewalls and rounded top corners and edges as is described herein according to one embodiment. In one embodiment, the fabrication of the memory cells can be a part of a larger process for fabricating a memory cell array. Although specific steps are disclosed in the flowcharts, such steps are exemplary. That is the present invention is well suited to performing various other steps or variations of the steps recited in the flowcharts.

Referring toFIG. 5, at501in an initial operation a plurality of FIN structures are formed in a substrate wafer.

At503, a sacrificial oxide is formed over the plurality of FIN structures. In one embodiment, the sacrificial oxide can be formed with thermal radical oxidation (e.g., steam oxidation) in a thermal furnace. In another embodiment, the sacrificial oxide can be formed by plasma radical oxidation in a single wafer chamber. In one embodiment, higher temperature and pressure in the plasma radical oxidation process can be used to enhance top corner and edge rounding.

At505, the sacrificial oxide is removed with a high selectivity oxide etchant. In one embodiment, a concentrated hydro-fluoride acid is used to remove the sacrificial oxide. In one embodiment, the high selectivity oxide etchant prevents silicon surface roughening.

At507, the semiconductor FIN structures are annealed to further smooth the surface of the FIN structures. In one embodiment, the semiconductor FIN structures are annealed in a hydrogen environment. In one embodiment, the annealing of the surfaces of the FIN structures reduces the number of surface terraces and other imperfections that are formed on the FIN (especially sidewall) surface.

At509, a tunnel oxide is formed over the FIN structures. In one embodiment, subsequent to step509typical SONOS steps can be performed.

With reference to exemplary embodiments thereof, methods for fabricating memory cells having FIN structures with smooth sidewalls and rounded top corner and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures is annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

Although many of the components and processes are described above in the singular for convenience, it will be appreciated by one of skill in the art that multiple components and repeated processes can also be used to practice the techniques of the present invention. Further, while the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, embodiments of the present invention may be employed with a variety of components and should not be restricted to the ones mentioned above. It is therefore intended that the invention be interpreted to include all variations and equivalents that fall within the true spirit and scope of the present invention.