Method and apparatus for improving efficiency in a power supply modulated system

A radio is presented that has a processor, memory, modulator and a power amplifier. An envelope of a signal to be transmitted is used by the processor to control modulation of the voltage of the power amplifier by the modulator between a desired minimum voltage and a desired maximum voltage. Using the memory, the desired minimum voltage is determined from the desired maximum voltage and these voltages are less than nominal minimum and maximum voltage, respectively. The desired minimum voltage is tailored for the radio and takes into account environmental conditions to optimize operating conditions for the radio. If the range of voltages would exceed the dynamic range of the radio, the modulation provided by the modulator is controlled by the processor in steps until the desired minimum and maximum voltages are achieved.

TECHNICAL FIELD

The present application relates to a power amplifier and in particular to a power amplifier whose minimum and maximum power supply is modulated.

BACKGROUND

With the ever-increasing demand for portable communication devices, reliability and efficiency of both user devices and devices in the supporting network has become of increasing importance. There are a number of different considerations, related to both individual elements as well as system elements, which affect these characteristics. For example, it is desirable to increase both bandwidth efficiency and power efficiency of a power amplifier in various communication devices. While bandwidth efficiency (the rate that data can be transmitted over a given bandwidth) is typically achieved using linear modulation, amplifier efficiency is a significant concern for achieving longer battery life and lower energy costs in transmitters as it usually dominates the power consumption in the system.

A transmitter of the portable communication device or of a communication device in the infrastructure (such as a base station) generally uses a radio frequency power amplifier (RFPA) as the final amplifying stage of a transmitter. The RFPA typically has a fixed power supply voltage. With a fixed supply voltage, however, the efficiency of the RFPA decreases as the output signal magnitude drops, leading to ineffectiveness and excessive peak power capability. To improve efficiency, it is desirable for the RFPA to continually operate near saturation, where the amplifier is close to or slightly gain compressed (about 0.5 dB below gain compression to 0.5 dB in gain compression). This can be achieved by modulating the power supply of the RFPA using the known technique of envelope tracking (i.e. the supply voltage of the RFPA tracks the output signal of the RFPA), which adjusts the power supply of the RFPA such that the power supply voltage of the RFPA follows the output signal thereby allowing the RFPA to continually operate near saturation.

While it is usually desirable in using power supply modulation for the RFPA to continually operate near saturation, a margin is provided to prevent “starvation” of the RFPA. The addition of margin to the power supply voltage is less than ideal because, it reduces average efficiency. Nevertheless, without providing some amount of margin, distortion in the amplified signal is often caused because of unexpected gain compression. Moreover, it is desirable for the RFPA to be adaptable to different forms of modulation, and thus the method of improving the efficiency of the RFPA to be able to operate for any given modulation. It is also desirable to be able to control the minimum voltage of the modulated supply, which improves efficiency especially when operating at low output power.

Therefore, a need exists for improved control of modulation of a power supply voltage to a power amplifier in order for the power amplifier to maintain high efficiency while operating linearly over a wide dynamic range. This control should also allow the power supply modulator implementation to be tolerant of design and component variations and to be backward compatible, thereby interfering minimally with core software used to implement a majority of the transmission functionality.

The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments shown so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Other elements, such as those known to one of skill in the art, may thus be present.

DETAILED DESCRIPTION

Before describing in detail the various embodiments, it should be observed that such embodiments reside primarily in an apparatus and method related to a power amplifier module in which control of the minimum level of the power amplifier power supply voltage is effected. A processor determines a desired minimum power supply voltage to the power amplifier based on the desired maximum power supply voltage to the power amplifier. The minimum-to-maximum power supply voltages are predetermined and stored internally in the radio for later retrieval. The minimum power supply voltage is adjusted to its desired level for various operating conditions, while the desired maximum output level is maintained.

FIG. 1illustrates a general network100that includes an infrastructure110. There are many distributed elements in the infrastructure110, some local to each other others disposed geographically distant from each other. Such elements include a base station120, which provides connectivity for a portable communication device130disposed within the coverage area serviced by the base station120to other devices either in the same coverage area or in a different coverage area through the infrastructure110. The portable communication device130can be, for example, a cellular telephone, personal digital assistant, or a communication device used by emergency personnel.

An embodiment of one such communication device, such as the base station120, is shown in the block diagram ofFIG. 2. The base station200may contain, among other components, a processor202, a transceiver204including transmitter circuitry206and receiver circuitry208, an antenna222, I/O devices212, a program memory214, a buffer memory216, one or more communication interfaces218, and removable storage220. The base station200is preferably an integrated unit and may contain at least all the elements depicted inFIG. 2as well as any other element necessary for the base station200to perform its electronic functions. The electronic elements are connected by a bus224.

The processor202includes one or more microprocessors, microcontrollers, DSPs, state machines, logic circuitry, or any other device or devices that process information based on operational or programming instructions. Such operational or programming instructions are stored in the program memory214and may include instructions such as estimation and correction of a received signal, encryption/decryption, and decisions about whether an alarm exists that are executed by the processor202as well as information related to the transmit signal such as modulation, transmission frequency or signal amplitude. The program memory214may be an IC memory chip containing any form of random access memory (RAM) and/or read only memory (ROM), a floppy disk, a compact disk (CD) ROM, a hard disk drive, a digital video disk (DVD), a flash memory card or any other medium for storing digital information. One of ordinary skill in the art will recognize that when the processor202has one or more of its functions performed by a state machine or logic circuitry, the memory214containing the corresponding operational instructions may be embedded within the state machine or logic circuitry. The operations performed by the processor202and the rest of the base station200are described in detail below.

The transmitter circuitry206and the receiver circuitry208enable the base station200to respectively transmit and receive communication signals. In this regard, the transmitter circuitry206and the receiver circuitry208include appropriate circuitry to enable wireless transmissions. The implementations of the transmitter circuitry206and the receiver circuitry208depend on the implementation of the base station200and the devices with which it is to communicate. For example, the transmitter and receiver circuitry206,208may be implemented as part of the communication device hardware and software architecture in accordance with known techniques. One of ordinary skill in the art will recognize that most, if not all, of the functions of the transmitter or receiver circuitry206,208may be implemented in a processor, such as the processor202. However, the processor202, the transmitter circuitry206, and the receiver circuitry208have been artificially partitioned herein to facilitate a better understanding. The buffer memory216may be any form of volatile memory, such as RAM, and is used for temporarily storing received or transmit information.

The base station200may also contain a variety of I/O devices such as a keyboard with alpha-numeric keys, a display (e.g., LED, OELD) that displays information about the base station or communications connected to the base station, soft and/or hard keys, touch screen, jog wheel, a microphone, and a speaker. Again, although the device discussed with relation to the figures is specifically referred to the base station, other communication devices that employ a power amplifier may be used.

As shown in the simplified block diagram ofFIG. 3, the transmitter portion of the base station300contains a transmitter module310and a power amplifier (PA) module320. The transmitter module310supplies signals to be power amplified (the final stage of amplification) to the PA module320. The PA module320also contains PA control circuitry322. The PA control circuitry322enables the transmitter module310and PA module320to exchange control signals including, if desired, alarm conditions from the PA module320to the transmitter module310, and alert instructions and envelope modulation signals from the transmitter module310to the PA module320.

The transmitter module and PA module are shown in more detail in the transceiver400ofFIG. 4. The transceiver400can employ any of a number of linear modulation techniques, such as Integrated Digital Enhanced Network (iDen), Terrestrial Trunked Radio (TETRA) and Transducer Electronic Data Sheet (TEDS) platforms. In each of the embodiments, the input RF signal is assumed to be a modulated signal. However, the input signal may also comprise of a multi-carrier signal or a slotted signal. The slotted signal can comprise at least one off slot or a lower power slot in addition to the slots carrying modulated data.

The transceiver400contains a transmitter module410and PA module440. The transmitter module410has a digital signal processor (DSP) or other microprocessor412. The DSP412includes a program for implementing power supply modulation. The DSP412provides a digital signal to be transmitted, which is then converted to an analog signal by a digital-to-analog (D/A) converter414. Although the DSP412may generate in-phase (I) and quadrature-phase (Q) baseband signals, as well known in the art, only one such signal is shown inFIG. 4for convenience. Although a transmitter configuration using Cartesian feedback is shown, other implementations such as polar feedback, pre-distortion, or feed-forward implementations may be used.

The I and Q signals from the DSP412are attenuated by an attenuator416, which may be passive or active. The attenuated signals are supplied to a summer418, which sums the attenuated signals with baseband signals from a feedback loop. The summed signals are amplified by an amplifier420and then upconverted to transmission frequency by a modulator422, which creates a low power RF signal according to a modulation scheme. The summed signals may be upconverted directly, as shown, or through an intermediate frequency. The modulator422is supplied with a carrier signal from an oscillator424. As above, as only one signal is shown, the 90° phase shifter used to provide signals to modulate the Q signal is not shown.

The low level RF signal from the modulator422is provided to an RFPA450in the PA module440. Other amplification and/or attenuation stages in the transmitter module410and/or PA module440have been omitted inFIG. 4for clarity.

The RFPA450in the PA module440provides power amplification of the low level RF signal for transmission. A coupler454couples the output from the RFPA450, which is then fed back to the transmitter module410. The analog signal from the coupler454is supplied to a demodulator428, where it is demodulated from the transmission frequency to baseband. The signal from the coupler454may be amplified and/or attenuated prior to being demodulated. One or more phase shifters426provide a predetermined phase shift of the carrier signal from the oscillator424. This phase shift is used to compensate the I and Q signals for the individual path delays in the Cartesian feedback loop as well as the overall loop delay. The baseband signal is then amplified by a feedback amplifier430before being supplied to the summer418, where it is used to linearize the signal to be transmitted.

The PA module440also contains a processor such as a floating-point gate array (FPGA), DSP, or complex programmable logic device (CPLD)444(hereinafter referred to as an FPGA for convenience), a power supply modulator446, and an input coupler448. The DSP412in the transmitter module410supplies envelope information to the FPGA444and the power supply modulator446. Specifically, the DSP412provides a modulated envelope signal with known minimum and maximum levels of the signal to be transmitted. The various digital signals from the DSP412are converted to analog signals either in the PA module440or in the Transmitter module410. Although the input coupler448is shown as coupling the signal supplied to the RFPA450, it can be placed anywhere along the forward path of the feedback loop (i.e., after the output of the summer418).

The power supply modulator446, which may be a fast acting DC to DC converter, modulates the power supply voltage of the RFPA450such that the modulated power supply voltage corresponds to the desired power supply voltage determined using the envelope signal of the signal to be transmitted by the RFPA450. Such converters are known in the art, and provide an output corresponding to a reference signal, which as shown inFIG. 4is the analog envelope signal provided by the DSP412. Alternatively, a digital signal corresponding to the analog envelope signal may be supplied to the power supply modulator446by the DSP412.

To control the power supply voltage, the FPGA444receives the envelope signal from the DSP412and the envelope signal from the input coupler448to determine the current power supply voltage modulation setting of the power supply modulator446and select the appropriate power supply voltage to ensure that compression does not occur within the RFPA450. Once this power supply voltage is selected, the FPGA444controls the power supply modulator446to limit the power supply voltage using multiple control signals sent to the power supply modulator446. The coupled signal from input coupler448is an RF signal that is fed to, for example, an envelope detector (not shown). The envelope detector produces a detected envelope of the input signal is fed to the FPGA444. In another embodiment, rather than the DSP412providing the envelope of the signal to be transmitted, another envelope detector may receive the signal to be transmitted from the DSP412(in addition to the D/A converter414) and provide the envelope to the FPGA444. Such envelope detectors are known in the art and thus will not be described in further detail herein.

In the embodiment shown inFIG. 4the transmitter module410and the PA module440are able to operate essentially independent of each other. This is to say that independent of whether or how the PA Module440is altering the power supply voltage, the transmitter module410receives the same signals from and sends the same signals to the PA module440. Thus, if adjustment of the power supply modulation level is not desired, the PA module440can be replaced by another PA module that does not contain the FPGA444(as well as other supporting circuitry)—i.e., one that does not require software changes in the DSP when operating in PSM mode—or contains a circuit that disengages the FPGA444from the power supply modulator446. This allows the transceiver400to be backwards compatible. As is apparent from the implementation shown inFIG. 4, the apparatus and method used to adjust the minimum power supply voltage only relies on information that is available within the PA module440.

As shown inFIG. 4, two control signals are provided from the FPGA444to the power supply modulator446: a minimum voltage control signal and a maximum voltage control signal. The minimum-to-maximum power supply voltage relationship of the RFPA450is predetermined, during factory calibration or bench testing, where the minimum power supply voltage is based on stability of the RFPA450. In general, while the minimum power supply voltage is about ½ the maximum power supply voltage, this varies in a nonlinear manner as the minimum power supply voltage is reduced such that, for example, as the maximum power supply voltage reaches single digit voltages, the minimum power supply voltage approaches zero volts. The results (Vmin=f(Vmax)) are stored in the FPGA444as a lookup table or as polynomial with corresponding coefficients. The FPGA444thus determines the minimum power supply voltage to provide to the RFPA450based on the maximum power supply voltage to the RFPA450. As the minimum power supply voltage to the RFPA450decreases, so does the maximum power supply voltage to the RFPA450. Thus, if the minimum voltage supply were adjusted independent of the maximum supply voltage, the RFPA450will begin to gain compress, become unstable, or fail device specifications or FCC regulations (e.g., adjacent channel power restrictions). In this case, as described in more detail below (with relation toFIG. 7), the maximum and minimum power supply voltages are adjusted in steps.

In general, the minimum power supply voltage is limited due to rapidly changing gain and phase, resulting in high amplitude and phase distortion to the amplified RF modulated signal at low power supply voltages. One solution would be to determine the minimum power supply voltage based only on the transmitted output power and then store this relationship in memory. Such a solution, however, does not take into account circuit, part-to-part, and operating temperatures of the implementation and instead limits the minimum power supply voltage to the worst case minimum power supply voltage. By relating the minimum power supply voltage to the maximum power supply voltage (which is optimal independent of output power and other variations, such as part-to part variations and temperature), a more optimal power amplifier efficiency can be achieved.

Consider, for example, the effects of ambient temperature on the minimum and maximum power supply voltages. The linearity of power amplifiers worsens with increasing temperature. Thus, a higher maximum power supply voltage is used to maintain linearity and output power requirements at a temperature extreme of 60° C. than at a temperature extreme of −30° C. If the minimum power supply voltage were to be based solely on the transmitted output power, the same minimum power supply voltage (based on the highest temperature level for which the power amplifier is to be employed) would be used at −30° C. as at 60° C. However, when the minimum power supply voltage is based on maintaining an allowable gain/phase change, the minimum power supply voltage is reduced at −30° C. since a lower maximum power supply voltage is employed, thereby improving efficiency.

One embodiment of the components associated with the FPGA444and the power supply modulator446ofFIG. 4is shown in the architecture500ofFIG. 5. Some or all of the components pictured may be present in the PA module shown inFIG. 4, but are not shown inFIG. 4for clarity. The signals from the Transmitter Module are differential signals, which are converted to single end signals in the architecture500. However, in other embodiments differential signals may be maintained throughout the architecture500or single end signals may be supplied by the Transmitter Module and retained throughout the architecture500.

In the embodiment shown, clock (CLK) and envelope (ENV) signals are provided from the Transmitter Module. The clock module502contains a CLK differential-to-single ended amplifier504(whose output is a square wave and whose gain may be variable) and a CLK divider506that reduces the clock rate of the clock signals from the CLK differential-to-single ended amplifier504. Although the CLK signal is shown inFIG. 5as being provided by the Transmitter Module, the CLK signal may instead originate in the PA Module using one or more oscillators and associated circuitry therein. The CLK signal may be single-ended or a single-ended clock converted to a differential clock. The signal from the CLK module is a square wave having a predetermined voltage range, for example 0 to 5V. The CLK signal is supplied to a Buffer (that may or may not invert the signal)508, which adjusts the voltage range of the signal using a maximum voltage control signal. The maximum voltage control signal is used as the power supply voltage VDD of the Buffer508so that the output signal from the Buffer508is a square wave that has a voltage range of 0 to VDD. The output signal of the Buffer508is supplied to one input of a ramp generator510. The gain may also be adjusted using a variable gain amplifier in the CLK path to the ramp generator510.

The ENV signal from the Transmitter Module is also shown inFIG. 5as being converted at an ENV differential-to-single ended converter512from a differential-to-single ended signal. The ENV differential-to-single ended converter512may also amplify or attenuate signals passing through it and will be referred to hereafter as ENV converter. The signal from the ENV converter512is supplied to an analog multiplexer (MUX)514along with a preset (in this embodiment constant) voltage Vbias. A control signal A is used to select either the ENV signal or the preset voltage. The signal selected from the multiplexer514as well as with the signal from the ramp generator510are supplied to a comparator516. The output from the comparator516is amplified by a gate driver circuit518and then switched through a transistor520(shown as a MOSFET, although other transistors such as a BJT may be used) or other gate circuit. The output from the transistor520is then filtered by an output filter522before being provided to the power supply of the RFPA450shown inFIG. 4.

The differential ENV signal is also supplied to separate multiplexers532,534, each of which are controlled by the same control signal A as multiplexer514. The other selectable input of one of the multiplexers532is grounded while the other input selectable input of the other of the multiplexers534is tied to the output of the output filter522through a voltage divider circuit (as shown formed by a pair of resistors). The outputs of the multiplexers532,534are supplied to a variable gain amplifier (VGA)536, whose analog differential output is supplied to an ADC538that produces a single ended digital output. In other embodiments, similar to the CLK signal, the ENV signal can be a single-ended only signal or a single ended signal converted to a differential signal. In these embodiments, the VGA536would be a single-ended input multiplexer or a single ended to differential multiplexer and multiplexer532would be eliminated.

Another multiplexer524, controlled by the same control signal as multiplexers514,532and534, selects between a buck control signal (fixed DC voltage) and the pre-distorted signal from the input coupler448inFIG. 4. Similar to the above, the output from multiplexer524is supplied to another VGA526, whose analog differential output is supplied to an ADC528that produces a single ended digital output. The gains of the VGAs526,536are individually controlled by different control signals B, C, which permits full usage of the output range of the ADCs528,538. The outputs of the ADCs528,538are supplied to the FPGA540, which employs the algorithm described herein to determine the minimum and maximum power supply voltages. The FPGA540also provides the control signals A, B, C to the multiplexers514,524,532,534and VGAs526,536. The digital minimum and maximum power supply voltages from the FPGA540are supplied to DACs542,544. The analog output from DAC542, which indicates the minimum power supply voltage, is supplied to the other input of the ramp generator510(e.g., the positive input of an op amp used in the ramp generator510). Similarly, the output from DAC544, which indicates the maximum power supply voltage, is supplied as the VDD signal to the Buffer408. The ADCs528,538, FPGA540, and DACs542,544are all clocked at the same rate. InFIG. 5, the FGPA clock is shown, which can be derived off of the clock module502or can be a new derived clock that may be the same or different.

The use of the multiplexers514,524,532,534permits the PA module to switch between envelope mode and buck emulation mode, the latter of which enables the PA module to be backwards compatible with older device architectures. In one embodiment, in the buck emulation mode the control signal A of the FPGA540is set to 1, thereby instructing the power supply modulator inFIG. 4to provide a constant power supply voltage to the RFPA. Control signals B and C are used for gain control and are set accordingly. In the buck emulation mode, either of the inputs to the ramp generator may stay fixed while the other input varies (i.e., Vbias supplied to multiplexer514or the control signals from the DACs542,544) to ensure that the optimal amount of compression is maintained. Thus, in the buck emulation mode either the power supply voltage of the RFPA is not modulated (i.e., pass-thru at the system voltage supply) or is modulated independent of the envelope signal with a constant voltage that is a function of output power.

In the envelope mode, the control signal A of the FPGA540, which is provided to the multiplexers514,524,532,534, is set to 0, allowing for the maximum and minimum power supply voltage of the modulated signal to be set to the desired levels. Similarly, control signals B and C control the gain of VGAs526,536. The FPGA540sets the control voltages to reduce the minimum power supply voltage and to maintain the maximum power supply voltage at the desired level. As the minimum control voltage signal (Vmin_control signal) increases, the minimum power supply voltage decreases. As Vmin_control signal decreases, the minimum power supply voltage increases. In one embodiment, Vmin_control signal is a signal to a positive input of an op amp (not shown) in the ramp generator510, thereby adjusting the offset of the ramp signal generated by the ramp generator510. The maximum control voltage signal (Vmax_control signal) adjusts the magnitude of the CLK signal being provided to the ramp generator510.

In one embodiment, Vmax_control signal may be varied over a predetermined range, e.g., from 2.8V to 5.5V. As Vmax_control signal decreases, the maximum power supply voltage increases. As Vmax_control signal increases, the maximum power supply voltage decreases. The ramp generator510generates a triangular waveform biased at a predetermined value, e.g., 1.8V (at the positive input of the op amp).

FIG. 6illustrates a slightly different architecture600than that ofFIG. 5. Unlike inFIG. 5, the FPGA640inFIG. 6employs a control signal to vary the amplitude of the envelope reference waveform at the ENV converter612. In this case, as the ENV control voltage increases, the maximum power supply voltage increases commensurately and as the ENV control voltage decreases, the maximum power supply voltage decreases commensurately. Although not expressly described below, variations similar to those inFIG. 5can also be employed in the architecture ofFIG. 6.

In the embodiment ofFIG. 6, clock (CLK) and envelope (ENV) signals are provided from the Transmitter Module. The clock module602contains a CLK differential-to-single ended amplifier604and a CLK divider606that reduces the clock rate of the clock signals from the CLK differential-to-single ended amplifier604. The CLK signal is supplied to a Buffer608whose power supply voltage is constant. The output signal of the Buffer608is supplied to one input of a ramp generator610.

The signal from the ENV converter612is supplied to an analog multiplexer (MUX)614along with a preset voltage Vbias. A control signal A is used to select either the ENV signal or the preset voltage. The signal selected from the multiplexer614as well as with the signal from the ramp generator610are supplied to a comparator616. The output from the comparator616is amplified by a gate driver circuit618and then switched through a transistor620. The output from the transistor620is then filtered by an output filter622before being provided to the power supply of the RFPA450shown inFIG. 4.

The differential ENV signal is also supplied to separate multiplexers632,634, each of which are controlled by the same control signal A as multiplexer614. The other selectable input of one of the multiplexers632is grounded while the other input selectable input of the other of the multiplexers634is tied to the output of the output filter622through a voltage divider circuit. The outputs of the multiplexers632,634are supplied to a VGA636, whose analog differential output is supplied to an ADC638that produces a single ended digital output.

Another multiplexer624, controlled by the same control signal as multiplexers614,632and634, selects between a buck control signal and the pre-distorted signal from the input coupler448inFIG. 4. Similar to the above, the output from multiplexer624is supplied to a VGA626, whose analog differential output is supplied to an ADC628that produces a single ended digital output. The gains of the VGAs626,636are individually controlled by different control signals B, C, which permits full usage of the output range of the ADCs628,638. The outputs of the ADCs628,638are supplied to the FPGA640, which employs the algorithm described herein to determine the minimum and maximum power supply voltages. The FPGA640also provides the control signals A, B, C to the multiplexers614,624,632,634and VGAs626,636. The digital minimum and maximum power supply voltages from the FPGA640are supplied to DACs642,644. The analog output from DAC642, which indicates the minimum power supply voltage, is supplied to the input of the ramp generator610(e.g., the positive input of an op amp used in the ramp generator610). Similarly, the output from DAC644, which indicates the maximum power supply voltage, is supplied to the ENV converter612to control its amplification.

As inFIG. 5, the use of the multiplexers614,624,632,634permits the PA module to switch between the envelope mode and buck emulation mode and control the gain of VGAs626,636.

In another embodiment, the power supply modulation may be provided using an interleaved approach. In this embodiment, the clock divider generates multiple out-of-phase (e.g., equally spaced) clock signals. Each of these clock signals is provided to a different Buffer, ramp generator, comparator circuit, gate drive, and transistor. The signals are then combined at the output filter. For example, the clock divider may generate four clock signals that are 90 degrees out-of-phase with each other, each of which is sent to a different one of four Buffers, four ramp generators, four comparator circuits, four gate drivers, and four transistors. The Vmax control voltage and Vmin Control voltage signals to the four ramp generator circuits and/or ENV signals to the ENV converter are identical. The use of interleaving reduces speed of the gate drive so that a slower clock can be used, thereby reducing the thermal load and power dissipation of the gate and transistor as well as permitting filtering of spurs at the switching frequency that may coincide with the signal frequency. The use of interleaving however, may increases the size and cost due to the use of multiple similar components.

In another embodiment (not shown), both the amplification provided by the ENV converter and the Buffer power supply can be varied.

A flowchart of one embodiment of the method of adjusting the minimum and maximum power supply voltage is shown inFIG. 7. Several terms are used herein and are defined as follows: Vmax_nomimal is the maximum allowable modulated power supply voltage (also referred to as the nominal maximum power supply voltage), Vmin_nomimal is the maximum allowable minimum modulated power supply voltage (also referred to as the nominal minimal power supply voltage), Vmax_desired is the desired maximum modulated power supply voltage (also referred to as the optimal maximum voltage of the modulated supply), Vmin_desired is the desired minimum modulated power supply voltage (also referred to as the optimal minimum voltage of the modulated supply), Vmax_offset is Vmax_nominal−Vmax_desired and Vmin_offset is a variable that depends on the state in the algorithm. The appropriate minimum and maximum power supply voltages are provided to the supply modulator after each iteration. Thus, it may take a short amount of time for the minimum and maximum power supply voltages to settle to their desired values. However, this settling time is relatively short compared to the changes in the envelope signal (a baseband signal with a bandwidth of less than about 100 KHz). For example, the envelope signal may be sampled at a rate of several MHz—10-20 times higher than that of the envelop signal itself.

As shown, the maximum power supply voltage is initially set to Vmax_desired (i.e., the optimal maximum modulated voltage for the RFPA to be maintained near saturation) at step702. Vmin_desired is then determined at step704based on Vmax_desired using the stored information in the FPGA (in the lookup table or polynomial). The amount of offset of the minimum power supply voltage from the nominal power supply voltage is then determined at step706such that Vmin_offset=Vmin_nomimal−Vmin_desired.

After determining the minimum offset at step706, it is then determined at step708whether Vmax_desired+Vmin_offset>Vmax_nomimal. This is used because the maximum power supply voltage correspondingly decreases with a decrease in the minimum power supply voltage. Accordingly, if the maximum desired power supply voltage is to be maintained, then the maximum power supply voltage is to be increased by the amount that the minimum power supply voltage is reduced. However, as the maximum power supply voltage cannot exceed the nominal maximum power supply voltage, the process determines whether further adjustments are to be made. Thus, if it is determined at step708that Vmax_desired+Vmin_offset≦Vmax_nomimal, the maximum power supply voltage is set to Vmax_desired+Vmin_offset at step710and the minimum power supply voltage is set to Vmin_desired at step712.

If, on the other hand, it is determined at step708that Vmax_desired+Vmin_offset>Vmax_nomimal, then at step714Vmax_offset is determined such that Vmax_offset=Vmax_nominal−Vmax_desired. At step716, the maximum power supply voltage is set to Vmax_nominal. At step718, the minimum power supply voltage is set to Vmin_nomimal−Vmax_offset. Then, at step720, Vmin_offset is reset to Vmin_offset−Vmax_offset before the process returns to step708to again determine whether Vmax_desired+Vmin_offset (from step720)>Vmax_nomimal.

In one example, Vmax_nominal=28V, Vmin_nomimal=14V, Vmax_desired=26V, and Vmin_desired=13V (predetermined based on Vmax_desired). Thus at step706, Vmin_offset=V_min_nominal−Vmin_desired=14V−13V=1V. At step708, Vmax_desired+Vmin_offset=26V+1V=27V and is compared to Vmax_nominal of 28V. In this case, since step708is false (27V is not>28V), the maximum power supply voltage is set to Vmax_desired+Vmin_offset (i.e., 27V) at step710and the minimum power supply voltage is set to Vmin_desired (i.e., 13V) at step712and the process terminates (i.e., Vmax_desired is 26V and Vmin_desired is 13V).

In another example, Vmax_nominal=28V, Vmin_nomimal=14V, Vmax_desired=25V, and Vmin_desired=10V (again predetermined based on Vmax_desired). Thus, at step706Vmin_offset=V_min_nominal−Vmin_desired=14V−10V=4V. At step708Vmax_desired+Vmin_offset=25V+4V=29V and is compared to Vmax_nominal of 28V. In this case, since step708is true (29V is >28V), this is unacceptable as the maximum power supply voltage cannot exceed the nominal maximum power supply voltage. In other words, the maximum power supply voltage cannot increase by the amount the minimum power supply voltage is supposed to be decreased.

As step708is true (Vmax_desired+Vmin_offset>Vmax_nominal), the adjustment to achieve Vmax_desired and Vmin_desired is performed in stages. The first step is to determine Vmax_offset=Vmax_nominal−Vmax_desired=28V−25V=3V at step714. The maximum voltage supply is then increased by 3V to Vmax_nomimal at step716and the minimum voltage supply is then decreased by 3V from 14V (Vmin_nominal) to 11V at step718(i.e., in setting the minimum voltage to 11V, the maximum voltage will thus be at 2 W as discussed above). Next it is determined how much more the minimum power supply voltage is to be shifted to get to Vmin_desired, while maintaining Vmax_desired. A new Vmin_offset is calculated as =the original Vmin_offset−Vmax_offset=4V−3V=1V at step720. This new Vmin_offset is now used to determine whether Vmax_desired+Vmin_offset>Vmax_nominal (i.e., whether 25V+1V >28V) at step708. In this case, now that this is no longer true, the maximum power supply voltage is now set to Vmax_desired+Vmin_offset=25V+1V=26V at step710while the minimum power supply voltage is set to Vmin_desired=10V at step712. Having reached the desired minimum and maximum power supply voltages, the process again terminates (i.e., Vmax_desired is 25V and Vmin_desired is 10V).

In the above embodiments, the minimum and maximum power supply voltages are set in series, with the maximum power supply voltage being set first and then the minimum power supply being set later. This is advantageous in embodiments in which only one DAC is present after the FPGA. In another embodiment, the minimum and maximum power supply voltages may be set simultaneously. In this case, multiple DACs are present and may thus provide both voltages at the same time from the FPGA. This is shown inFIG. 5.

A simulated graph of gain/phase change vs. modulated power supply voltage is shown inFIG. 8. The high and low power Vmax/Vmin ratio is determined by the maximum allowable gain/phase change, thus providing for maximum efficiency of the power amplifier. This is true, in one embodiment, as long as the Vmax/Vmin optimal ratio does not require Vmin to fall below a fixed value (such as a predetermined level of half the main supply voltage). In this case, the maximum possible efficiency is not maintained, since Vmin is fixed.

In a different embodiment, Vmin is allowed to decrease such that the Vmax/Vmin ratio is optimal. In this case, the maximum efficiency of the power amplifier is able to be maintained even for low output power levels. This approach also allows for the Vmax desired level to be below the aforementioned predetermined level (e.g., half the main supply voltage), since Vmin is a function of the Vmax/Vmin ratio and not simply a voltage level.

In various embodiments, the power supply voltage may be adjusted when compression occurs in the RFPA. For example, the peak-to-average power ratio of the input signal to the RFPA may be compared to an ideal peak-to-average power ratio. The PA module automatically compensates for compression by increasing the RF input signal peaks by predetermined step sizes (that can be dynamically adjusted so that the step size changes), and thus the input peak-to-average power ratio. However in any given architecture the amount of compensation in a closed loop system may be limited, thus the power supply voltage levels may be adjusted in addition to any loop compensation. In this case, if the power supply voltage is to be increased to avoid signal compression, the minimum voltage level is able to be adjusted accordingly (i.e., using the algorithm described above).

Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the spirit and scope of the invention and that such modifications, alterations, and combinations are to be viewed as being within the scope of the inventive concept. Thus, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims issuing from this application. The invention is defined solely by any claims issuing from this application and all equivalents of those issued claims.