Semiconductor device with air gap between wires and method for fabricating the same

A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0126063, filed on Sep. 30, 2016, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device and Method for Fabricating the Same,” is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor device and a method for fabricating the same.

2. Description of the Related Art

As downscaling of a semiconductor device is accelerated with the development of the electronic technology, high-integration and low-power of a semiconductor chip are demanded. In response to a demand for high-integration and low-power of a semiconductor device, feature size of a semiconductor device continuously decreases and a dielectric constant of an intermetal dielectric film continuously decreases at a back end-of-line (BEOL) process. Meanwhile, according to decrease of feature size, enhancement for resistance capacitance and reliability of a dielectric film between wires may be important.

SUMMARY

According to an aspect of embodiments, there is provided a semiconductor device including a substrate, a first interlayer dielectric film on the substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film and being adjacent to each other in a second direction different from the first direction, a hard mask pattern including an opening, on the first interlayer dielectric film, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion non-overlapping with the opening in the first direction.

According to another aspect of embodiments, there is provided a semiconductor device including a substrate, a first interlayer dielectric film on the substrate, first and second wires extending respectively in a first direction within the first interlayer dielectric film and being adjacent to each other in a second direction different from the first direction, a first recess includes a sidewall defined by the first and second wires within the first interlayer dielectric film between the first and second wires, and a first hard mask pattern on the first interlayer dielectric film, the first hard mask pattern including a first opening overlapping with a portion of the first recess, a portion of the first wire, and a portion of the second wire, wherein a width of the first recess in the first direction is greater than a width of the first opening in the first direction.

According to still another aspect of embodiments, there is provided a semiconductor device including an interlayer dielectric film on a substrate, a recess within the interlayer dielectric film, a wire of which at least a portion is disposed within the recess, an end portion of the wire being disposed within the recess, a hard mask pattern on the interlayer dielectric film and the wire, the hard mask pattern covering the end portion of the wire, and an air gap between the end portion of the wire and the first interlayer dielectric film.

According to yet another aspect of embodiments, there is provided a semiconductor device including a substrate, a first interlayer dielectric film on the substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and a recess within the first interlayer dielectric film, the recess including an air gap that overlaps vertically with the opening of the hard mask pattern and extends beyond the opening to overlap a portion of the hard mask pattern.

According to still another aspect of embodiments, there is provided a method for fabricating a semiconductor device including forming first and second wires extending respectively in a first direction within a first interlayer dielectric film and being adjacent to each other in a second direction different from the first direction, forming a hard mask pattern including an opening on the first interlayer dielectric film, the opening exposing at least a portion of the interlayer dielectric film between the first wire and the second wire, performing a plasma treatment process on the interlayer dielectric film exposed by the opening by using the hard mask pattern as a mask, forming a recess within the interlayer dielectric film by removing the plasma-treated interlayer dielectric film, a width of the recess in the first direction being greater than a width of the opening in the first direction, and forming an air gap within the recess.

DETAILED DESCRIPTION

FIG. 1is a layout view provided to explain a semiconductor device according to some example embodiments.FIG. 2is a top view illustrating the semiconductor device ofFIG. 1.FIG. 3is a cross sectional view along line A-A ofFIG. 1.FIG. 4is a view provided to explain relations between the interlayer dielectric film and the hard mask pattern ofFIG. 3.FIG. 5is a cross sectional view along line B-B ofFIG. 1.FIG. 6is an enlarged view of section P ofFIG. 5. For reference,FIG. 2is a top view illustrating the semiconductor device while excluding a second interlayer dielectric film170on a first hard mask pattern150.

Referring toFIGS. 1 to 6, a semiconductor device according to some example embodiments may include a first interlayer dielectric film160, the first hard mask pattern150, first to third wires110,120,130, the second interlayer dielectric film170, a first recess165, and a first air gap180. The first interlayer dielectric film160may be formed on a substrate100.

The substrate100may be a structure stacking a base substrate and an epitaxial layer. but not limited hereto. The substrate100may be, e.g., a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for display, or a semiconductor on insulator (SOI) substrate.

For example, when the substrate100includes a silicon substrate, the substrate100may be a structure including a dielectric film formed on the silicon substrate100. Further, the substrate100may include a conductive pattern. The conductive pattern may be a metal wire or a contact, a gate electrode of a transistor, a source/drain of a transistor, or a diode, but not limited hereto.

An etch stopping film may be additionally formed between the substrate100and the first interlayer dielectric film160. The etch stopping film may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN). The etch stopping film may be formed by using, e.g., chemical vapor deposition, atom layer deposition, and so on.

The first interlayer dielectric film160may include at least one of, e.g., silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material. For example, the first interlayer dielectric film160may include a low-k dielectric material to alleviate the coupling phenomenon between wires. A low-k dielectric material may be, e.g., silicon oxide having properly high carbon and hydrogen, or a material such as SiCOH.

A dielectric constant of a dielectric material may be lowered by including carbon in the dielectric material. However, in order to further lower a dielectric constant of the dielectric material, the dielectric material may include, within the dielectric material, a pore, i.e., a cavity, in which gases or airs are filled.

The first wire110, the second wire120, and the third wire130may be formed within the first interlayer dielectric film160. The first wire110, the second wire120, and the third wire130may be formed on the substrate100.

The first wire110, the second wire120, and the third wire130may respectively extend longitudinally in a first direction X1. Further, the first wire110, the second wire120, and the third wire130may be aligned in sequence in a second direction Y1. That is, the first wire110, the second wire120, and the third wire130may be adjacent to, e.g., and spaced apart from, each other in the second direction Y1.

As illustrated inFIG. 1, the first wire110may include a long side110aextending longitudinally in the first direction X1and a short side110bextending in the second direction Y1. The second wire120may include a long side120aextending longitudinally in the first direction X1and a short side120bextending in the second direction Y1. The third wire130may include a long side130aextending longitudinally in the first direction X1and a short side extending in the second direction Y1. The long side120aof the second wire may face the long side110aof the first wire and the long side130aof the third wire.

As illustrated inFIG. 5, the first wire110may include a first filling conductive film112and a first barrier conductive film111extending along a bottom surface and a sidewall of the first filling conductive film112. The second wire120may include a second filling conductive film122and a second barrier conductive film121extending along a bottom surface and a sidewall of the second filling conductive film121. The third wire130may include a third filling conductive film132and a third barrier conductive film131extending along a bottom surface and a sidewall of the third filling conductive film132. The first to third filling conductive films112,122,132may be respectively formed on the first to third barrier conductive films111,121,131.

Each of the first to third barrier conductive films111,121,131may include, e.g., at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr) zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir) and rhodium (Rh). For example, each of the first to third barrier conductive films111,121,131may, e.g., completely, separate the first interlayer dielectric film160from a corresponding one of the first to third filling conductive films112,122,132.

Each of the first to third filling conductive films112,122,132may include, e.g., at least one of aluminum (Al), copper (Cu), tungsten (W), and cobalt (Co). For example, when each of the first to third filling conductive films112,122,132includes copper, the copper included in the first to third filling conductive films112,122,132may include, e.g., at least one of carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chrome (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al) or zirconium (Zr).

FIG. 5illustrates an upper surface of each of the first to third filling conductive films112,122,132being planar, but this is provided only for convenience of explanation and the example embodiments are not limited hereto. For example, the upper surface of each of the first to third filling conductive films112,122,132may be convex upwardly or downwardly.

Referring toFIGS. 2, 3, and 5, the first recess165may be formed within the first interlayer dielectric film160. The first recess165may be formed between the first wire110and the second wire120, as illustrated inFIGS. 2 and 5.

As illustrated inFIG. 2, the first recess165may include a first sidewall165sadefined by the first wire110and the second wire120, and a second sidewall165sbdefined by the first interlayer dielectric film160. The first sidewall165saof the first recess may be defined by the long side110aof the first wire and the long side120aof the second wire. The second sidewall165sbof the first recess165, which connects the first sidewalls165saof the first recess165extending in the first direction X1, may include a curved surface. The first recess165will be explained below.

Referring toFIGS. 1-5, the first hard mask pattern150may be formed on the first interlayer dielectric film160. The first hard mask pattern150may be formed on the first to third wires110,120,130. For example, the first hard mask pattern150may be in contact with the first to third wires110,120,130and the first interlayer dielectric film160. As used herein, the expression “in contact with” indicates that an inserting film is not formed between the first hard mask pattern150and the first interlayer dielectric film160.

The first hard mask pattern150may include a first opening155. The first opening155may expose at least a portion of the first wire110and the second wire120. More specifically, the first opening155may vertically overlap, e.g., along a third direction Z1, with at least a portion of the first wire110and at least a portion of the second wire120. Each of the first wire110and the second wire120may include a portion overlapping the first opening155and a portion not overlapping the first opening155.

The first opening155may overlap with a portion of the first recess165. The first recess165may extend in the first direction X1longer than the first opening155, e.g., as illustrated inFIGS. 2-3.

The first interlayer dielectric film160between the first wire110and the second wire120may be undercut under the first hard mask pattern150. That is, as illustrated inFIGS. 3-4, the first hard mask pattern150may include a protruding portion150platerally protruding from an uppermost portion of the first recess165farther than the second sidewall165sbof the first recess, e.g., the protruding portion150pmay extend horizontally along the first direction X1to overhang a portion of the first recess165. The protruding portion150pof the first hard mask pattern150may not be in contact with the first interlayer dielectric film160. Relations between the first opening155of the first hard mask pattern150and the first recess165will be described below.

As illustrated inFIG. 2, the first opening155may be formed by the joining of a first sidewall155aextending in the first direction X1with a second sidewall155bextending in the second direction Y1. In the semiconductor device according to some example embodiments, the first sidewall155aof the first opening may be placed on upper surfaces of the first wire110and the second wire120extending longitudinally in the first direction X1. That is, among the first sidewalls155aof the first opening which are parallel to each other, one first sidewall155amay be placed on, e.g., above, the first wire110, and the other first sidewalls155aof the first opening parallel thereto may be placed on, e.g., above, the second wire120.

For example, the first hard mask pattern150may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN). In the semiconductor device according to some example embodiments, it is described that the first hard mask pattern150includes silicon carbonitride.

As illustrated inFIGS. 3 and 5, the second interlayer dielectric film170may be formed on the first hard mask pattern150. The second interlayer dielectric film170may block the first opening155. The second interlayer dielectric film170may include at least one of, e.g., silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material. The second interlayer dielectric film170may include, e.g., a low-k dielectric material, but not limited hereto.

As illustrated inFIGS. 3 and 5, the first air gap180may be formed within the first interlayer dielectric film160. The first air gap180may be formed between the first interlayer dielectric film160and the second interlayer dielectric film170as the first opening155is blocked with the second interlayer dielectric film170. At least a portion of the first air gap180may vertically overlap with the first opening155.

At least a portion of the first air gap180may be disposed within the first recess165, e.g., the first air gap180may fill the first recess165. That is, the first air gap180may be formed within the first interlayer dielectric film160between the first wire110and the second wire120.

The protruding portion150pof the first hard mask pattern150may include an upper surface facing the second interlayer dielectric film170, and a bottom surface facing the first interlayer dielectric film160, e.g., a portion of the first air gap180may be between the bottom surface of the protruding portion150pand the first interlayer dielectric film160. The second interlayer dielectric film170may be formed on an upper surface of the protruding portion150pof the first hard mask pattern150. In the semiconductor device according to some example embodiments, the second interlayer dielectric film170may not be formed between a bottom surface of the protruding portion150pof the first hard mask pattern150and the first air gap180.

Referring toFIGS. 2 to 4, a width W11of the first recess165in the first direction X1may be greater than a width W21of the first opening155in the first direction X1. The width difference between W11and W21may account for a width of the protruding portion150p.

The first recess165may include a first portion165avertically overlapping with the first opening155and a second portion165bnon-overlapping with the first opening155. The second portion165bof the first recess165may vertically overlap with the protruding portion150pof the first hard mask pattern150.

In the semiconductor device according to some example embodiments, the second portion165bof the first recess may be disposed on both sides of the first portion165aof the first recess based on the first portion165aof the first recess, when viewed in a cross-sectional view. The second portion165bof the first recess may be disposed on both sides of the first portion165aof the first recess in the first direction X1. As illustrated inFIG. 5, because the opposed first sidewalls155aof the first opening are respectively positioned on the first wire110and the second wire120, a width of the first recess165in the second direction Y1may be less than a width of the first opening155in the second direction Y1.

In the semiconductor device according to some example embodiments, a depth D1of the first recess165may be substantially equal to a depth D2of the second portion165bof the first recess in the first direction X1. The depth D2of the first interlayer dielectric film160undercut under the first hard mask pattern150may be substantially equal to the depth D1of the first recess165. On a border of the first interlayer dielectric film160with the first hard mask pattern150, the depth D2of the first hard mask pattern150protruding from the sidewall of the first recess165may be substantially equal to the depth D1of the first recess165.

Further, as illustrated inFIG. 5, in the semiconductor device according to some example embodiments, the depth D1of the first recess165may be equal to or less than a height h1of the first wire110, and equal to or less than a height h2of the second wire. In other words, a distance from a lower surface of the first interlayer dielectric film160to a bottom surface of the first recess165may be equal to or greater than a distance from a lower surface of the first interlayer dielectric film160to a bottom surface of the first wire110, and equal to or greater than a distance from a lower surface of the first interlayer dielectric film160to a bottom surface of the second wire120.

That is, even when the first recess165is formed between the first wire110and the second wire120, the bottom surface of the first wire110and the bottom surface of the second wire120may be adjoined with the first interlayer dielectric film160. When the depth D1of the first recess165is greater than the height h1of the first wire110and/or the height h2of the second wire, the first wire110and/or the second wire120may be inclined.

InFIGS. 3 and 4, a width W31of the first air gap180in the first direction X1may be greater than the width W21of the first opening155in the first direction X1. The first air gap180may include a first portion180avertically overlapping with the first opening155and a second portion180bnon-overlapping with the first opening155. The second portion180bof the first air gap may not overlap with the first opening155in the first direction X1. The second portion180bof the first air gap may vertically overlap with the protruding portion150pof the first hard mask pattern.

In the semiconductor device according to some example embodiments, the second portion180bof the first air gap may be disposed on both sides of the first portion180aof the first air gap based on the first portion180aof the first air gap. The second portion180bof the first air gap may be disposed on both sides of the first portion180aof the first air gap in the first direction X1. Only the first portion180aof the first air gap180may be positioned between the first wire110and the second wire120overlapping with the first opening155. It is further noted that the first and second portions180aand180bof the first air gap180may define a single air gap, and the first and second portions180aand180bare defined only for ease of description.

InFIG. 6, the first wire110may include a first portion110apoverlapping with the first opening155and a second portion110bpnon-overlapping with the first opening155. That is, referring toFIGS. 5-6, a top of the second portion110bpof the first wire110may be covered by the second interlayer dielectric film170, while the first portion110apof the first wire110may be exposed by the second interlayer dielectric film170to define the first opening155.

In the semiconductor device according to some example embodiments, a height h12of the first barrier conductive film111in the first portion110apof the first wire110may be substantially equal to a height h11of the first barrier conductive film111in the second portion110bpof the first wire110. In other words, the height h12from the bottom surface of the first wire110at the first portion110apof the first wire to an uppermost portion of the first barrier conductive film111may be substantially equal to the height h11from the bottom surface of the first wire110at the second portion110bpof the first wire to an uppermost portion of the first barrier conductive film111.

In the semiconductor device according to some example embodiments, at a location where the upper surface of the first filling conductive film112at the second portion110bpof the first wire meets the first barrier conductive film111, the first barrier conductive film111may not include a portion protruding upward higher than the upper surface of the first filling conductive film112. That is, upper most surfaces of the first filling conductive film112and the first barrier conductive film111may be substantially level with each other.

WhileFIGS. 1, 2, and 5illustrate that the first wire110, the second wire120, and the third wire130have same height and width, this is provided so only for convenience of explanation and the example embodiments are not limited hereto.

WhileFIGS. 1, 2, and 5illustrate the three wires110,120,130aligned in parallel in the second direction Y1, this is provided only for convenience of explanation and the example embodiments are not limited hereto. That is, the two wires aligned in parallel in the second direction Y1may be formed, or four or more wires may be formed.

WhileFIGS. 1, 2, and 5illustrate that the first to third wires110,120,130are spaced apart by equal intervals, this is provided only for convenience of explanation and example embodiments are not limited hereto.

WhileFIGS. 1, 2, and 5illustrate only the three wires110,120,130extending longitudinally in the first direction X1, this is provided only for convenience of explanation and the example embodiments are not limited hereto. Another wire extending in the second direction Y1may be formed between the first wire110and the second wire120and/or between the second wire120and the third wire130.

Further, whileFIGS. 1, 2, and 5illustrate that there are two wires being partially exposed by the first opening155, this is provided only for convenience of explanation and the example embodiments are not limited hereto. That is, there may be three or more wires exposed by the first opening155. In the above case, one or more wires may be additionally formed between the first wire110and the second wire120.

FIGS. 7A to 7Care example views provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 1 to 6will be mainly explained below. For reference, each ofFIGS. 7A to 7Cmay be a cross sectional view along the second direction Y1of the first wire110.

Referring toFIG. 7A, in the semiconductor device according to some example embodiments, the height h12of the first barrier conductive film111at the first portion110apof the first wire may be less than the height h11of the first barrier conductive film111at the second portion110bpof the first wire.

In detail, in a process of forming the first opening155, a portion of the first barrier conductive film111at the first portion110apof the first wire may be etched. However, because the second portion110bpof the first wire may be covered by the first hard mask pattern150, the first barrier conductive film111at the second portion110bpof the first wire may not be etched.FIG. 7Aillustrates that a portion of the first filling conductive film112may have an etched shape at the first portion110apof the first wire, although example embodiments are not limited hereto.

Referring toFIG. 7B, in the semiconductor device according to some example embodiments, at a location where an upper surface of the first filling conductive film112at the second portion110bpof the first wire meets the first barrier conductive film111, the first barrier conductive film111may include a portion111pprotruding upward higher than the upper surface of the first filling conductive film112. Because there is a difference in the etching degree between the first barrier conductive film111and the first filling conductive film112in a process of forming the first wire110, the first barrier conductive film111may include a portion111pprotruding upward higher than the upper surface of the first filling conductive film112.

Referring toFIG. 7C, in the semiconductor device according to some example embodiments, the height h12of the first barrier conductive film111at the first portion110apof the first wire may be less than the height h11of the first barrier conductive film111at the second portion110bpof the first wire. Further, at a location where the upper surface of the first filling conductive film112at the second portion110bpof the first wire meets the first barrier conductive film111, the first barrier conductive film111may include a portion111pprotruding upward higher than the upper surface of the first filling conductive film112.

In a process of forming the first opening155, a portion of the first barrier conductive film111at the first portion110apof the first wire may be etched. Further, in a process of forming the first wire110, the first barrier conductive film111may include the portion111pprotruding upward higher than the upper surface of the first filling conductive film112.

Unlike the illustration inFIG. 7C, at a location where the upper surface of the first filling conductive film112at the first portion110apof the first wire meets the first barrier conductive film111, a portion of the first barrier conductive film111may be protruding higher than the upper surface of the first filling conductive film112.

FIG. 8is a view provided to explain a semiconductor device according to some example embodiments.FIG. 9is an enlarged view of section Q ofFIG. 8. For convenience of explanation, differences that are not explained above with reference toFIGS. 1 to 6will be mainly explained below. For reference,FIG. 8corresponds to a cross sectional view along line B-B ofFIG. 1.

Referring toFIGS. 8 and 9, in the semiconductor device according to some example embodiments, each of the first to third wires110,120,130may further include first to third capping conductive films113,123,133. For example, the first capping conductive film113may be disposed on the upper surface of the first filling conductive film112. The first capping conductive film113may extend along the upper surface of the first filling conductive film112. Each of the first to third capping conductive films113,123,133may include, e.g., at least one of cobalt (Co), tungsten (W), aluminum (Al), tantalum (Ta), titanium (Ti), nickel (Ni), ruthenium (Ru), or aluminum nitride (AlN).

For example, as illustrated inFIG. 8, each of the first to third capping conductive films113,123,133may, e.g., completely, cover a top of first through third filling conductive film112,122,132, respectively. The first to third capping conductive films113,123,133may minimize loss of metal, e.g., Cu, first through third filling conductive film112,122,132, respectively, during subsequent processing.

For example, a thickness h14of the first capping conductive film113at the first portion110apof the first wire110may be less than a thickness h13of the first capping conductive film113at the second portion110bpof the first wire110, as illustrated inFIG. 9. In a process of forming the first opening155, a portion of the first capping conductive film113at the first portion110apof the first wire110may be etched, e.g., removed.

In another example, a thickness of the first capping conductive film113at the first portion110apof the first wire may be also equal to a thickness of the first capping conductive film113at the second portion110bpof the first wire. Further, whileFIGS. 8 and 9illustrate that the first capping conductive film113is not deposited on the uppermost surface of the first barrier conductive film111, this is provided only for convenience of explanation and the example embodiments are not limited hereto.

InFIG. 8, a portion of the second wire120overlapping with the first opening155may be similar to the first portion110apof the first wire.

FIG. 10is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 8 and 9will be mainly explained below. For reference,FIG. 10is an enlarged view of section Q ofFIG. 8.

Referring toFIG. 10, in the semiconductor device according to some example embodiments, the first capping conductive film113may not be disposed on the first filling conductive film112at the first portion110apof the first wire overlapping with the first opening155. That is, the first capping conductive film113may remain at the second portion110bpof the first wire non-overlapping with the first opening155, and may not remain at the first portion110apof the first wire overlapping with the first opening155.

FIGS. 11 and 12are views provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 1 to 6will be mainly explained below.

Referring toFIGS. 11 and 12, the semiconductor device according to some example embodiments may further include an air gap liner185extending along a profile of the first recess165and a profile of the protruding portion150pof the first hard mask pattern. The air gap liner185may be formed along the second sidewall165sbof the first recess defined by the first interlayer dielectric film160, the bottom surface of the first recess165, and the first sidewall165saof the first recess defined by the first wire110and the second wire120.

The air gap liner185may be formed along the upper surface of the first hard mask pattern150, and the sidewall and the bottom surface of the protruding portion150pof the first hard mask pattern. Further, the air gap liner185may also be formed on upper surfaces of the first wire110and the second wire120exposed by the first opening155.

The air gap liner185may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN). In the semiconductor device according to some example embodiments, it is described that the air gap liner185includes silicon carbonitride.

The second interlayer dielectric film170may be formed on the air gap liner185. Because the air gap liner185is formed along the profile of the first recess165, the width W31of the first air gap180in the first direction X1may be less than the width W11of the first recess165in the first direction X1. Further, the width W31of the first air gap180in the first direction X1may be greater than the width W21of the first opening155in the first direction X1. At least a portion of the first air gap180may be surrounded by the air gap liner185, and the rest of the first air gap180may be surrounded by the second interlayer dielectric film170.

FIG. 11illustrates that the air gap liner185is formed conformally along the profile of the first recess165and the profile of the protruding portion150pof the first hard mask pattern, but not limited hereto. For example, in the air gap liner185formed along the protruding portion150pof the first hard mask pattern, a thickness of the air gap liner185formed between the second interlayer dielectric film170and the upper surface of the first hard mask pattern150may be greater than a thickness of the air gap liner185formed on the bottom surface of the protruding portion150pof the first hard mask pattern facing the first interlayer dielectric film160.

FIGS. 13 and 14are views provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 11 and 12will be mainly explained below.

Referring toFIGS. 13 and 14, the semiconductor device according to some example embodiments may further include an insulating pattern175formed on the air gap liner185within the first recess165. The insulating pattern175may extend along a portion of the profile of the first recess165. The insulating pattern175may include a portion vertically overlapping with the first opening155and a portion overlapping with the protruding portion150pof the first hard mask pattern, but not limited hereto.

During a process of forming the second interlayer dielectric film170, the insulating pattern175may be formed on the bottom surface165bbof the first recess as a portion of the second interlayer dielectric film170is deposited within the first recess165. Therefore, according to a depositing method for forming the second interlayer dielectric film170, the insulating pattern175may include a portion vertically overlapping with the first opening155, and may not include a portion non-overlapping with the first opening155.

The insulating pattern175may be formed on a portion of the second sidewall165sbof the first recess. That is, the insulating pattern175may not be formed entirely on the second sidewall165sbof the first recess.

In the semiconductor device according to some example embodiments, the second interlayer dielectric film170or the insulating pattern175is not formed between the air gap liner185on the bottom surface of the protruding portion150pof the first hard mask pattern and the first air gap180. Further, the insulating pattern175may not be connected with the second interlayer dielectric film170. WhileFIG. 14illustrates that the insulating pattern175may not be formed on the first sidewall165saof the first recess, example embodiments are not limited hereto.

FIG. 15is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 1 to 6will be mainly explained below.

Referring toFIG. 15, in the semiconductor device according to some example embodiments, the depth D1of the first recess165may be greater than the width D2of the first recess165in the first direction X1non-overlapping with the first opening155. In other words, the width D2of the first interlayer dielectric film160undercut under the first hard mask pattern150may be less than the depth D1of the first recess165.

FIG. 16is a layout view provided to explain a semiconductor device according to some example embodiments.FIG. 17is a top view illustrating the semiconductor device ofFIG. 16.FIG. 18is a cross sectional view along line B-B ofFIG. 16. For convenience of explanation, differences that are not explained above with reference toFIGS. 1 to 6will be mainly explained below.

For reference, a cross sectional view along line A-A ofFIG. 16may be substantially similar toFIG. 3. Further, a cross sectional view cut along a portion formed with the first opening155between the second wire120and the third wire in the first direction X1may be similar toFIG. 3. Further,FIG. 17is a top view excluding the second interlayer dielectric film170on the first hard mask pattern150.

Referring toFIGS. 16 to 18, the semiconductor device according to some example embodiments may further include the second recess166and a second air gap181.

The first opening156of the first hard mask pattern150may vertically overlap with at least a portion of the second wire120. The first opening156may not overlap with the first wire110and the third wire130.

The first opening156may extend in the first direction X1and may include first sidewalls156aparallel to each other. The first opening156may include second sidewalls156bconnecting the first sidewalls156aof the first opening.

Among the parallel first sidewalls156aof the first opening, one first sidewall156amay be placed on the first interlayer dielectric film160between the first wire110and the second wire120, and the other first sidewall156aof the first opening may be placed on the first interlayer dielectric film160between the second wire120and the third wire130.

Unlike the illustration above, one of the first sidewalls156aof the first opening may be placed on the first interlayer dielectric film160, and the other first sidewall156aof the first opening may be placed on the first wire110or the third wire130.

The first recess165and the second recess166may be respectively formed within the first interlayer dielectric film160. The first recess165may be formed between the first wire110and the second wire120, and the second recess166may be formed between the second wire120and the third wire130.

The first recess165may include the first sidewall165sadefined by the first wire110and the second wire120, and the second recess166may include the first sidewall166sadefined by the second wire120and the third wire130. The first recess165and the second recess166may respectively include the second sidewalls165sb,166sbdefined by the first interlayer dielectric film160.

In the semiconductor device according to some example embodiments, a width of the first recess165in the first direction X1and a width of the second recess166in the first direction X1may be respectively greater than a width of the first opening156in the first direction X1. Further, in the semiconductor device according to some example embodiments, a width of the first recess165in the second direction Y1and a width of the second recess166in the second direction Y1may be respectively greater than a distance between the first sidewall156aof the first opening and the second wire120.

In other words, the first hard mask pattern150may include a portion protruding from the first sidewall165saof the first recess defined by the sidewall of the first wire110to the second wire120, and a portion protruding from the first sidewall166saof the second recess defined by the sidewall of the third wire130to the second wire120.

For example, a height of the first sidewall165saof the first recess defined by the first wire110may be substantially equal to a height of the first sidewall165saof the first recess defined by the second wire120. Further, a height of the first sidewall166saof the second recess defined by the third wire130may be substantially equal to a height of the first sidewall166saof the second recess defined by the second wire120.

The first air gap180may be formed between the first wire110and the second wire120within the first interlayer dielectric film160. The second air gap181may be formed between the second wire120and the third wire130within the first interlayer dielectric film160.

InFIG. 16which is a cross sectional view along line B-B, the first air gap180between the long side110aof the first wire and the long side120aof the second wire may include a first portion180aoverlapping with the first opening156and a second portion180bnon-overlapping with the first opening156. Further, the second air gap181between the long side130aof the third wire and the long side120aof the second wire may include the first portion181aoverlapping with the first opening156, and a second portion181bnon-overlapping with the first opening156. Between the long side110aof the first wire and the long side120aof the second wire, the second portion180bof the first air gap may be adjacent to the first wire110, and the first portion180aof the first air gap may be positioned between the second portion180bof the first air gap and the second wire120.

Likewise, between the long side130aof the third wire and the long side120aof the second wire, the second portion181bof the second air gap may be adjacent to the third wire130, and the first portion181aof the second air gap may be positioned between the second portion181bof the second air gap and the second wire120. In other words, the second portion180bof the first air gap may include a first region non-overlapping with the first opening156in the first direction X1and a second region non-overlapping with the first opening156in the second direction Y1. Likewise, the second portion181bof the second air gap may include a third region non-overlapping with the first opening156in the first direction X1and a fourth region non-overlapping with the first opening156in the second direction Y1.

FIG. 19is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 16 to 18will be mainly explained below.

Referring toFIG. 19, in the semiconductor device according to some example embodiments, a height of the first sidewall165saof the first recess defined by the first wire110may be less than a height of the first sidewall165saof the first recess defined by the second wire120.

Further, a height of the first sidewall166saof the second recess defined by the third wire130may be less than a height of the first sidewall166saof the second recess defined by the second wire120.

In a process of forming the first recess165and the second recess166, the first interlayer dielectric film160unexposed by the first opening156may be removed less than the first interlayer dielectric film160exposed by the first opening156. Thereby, the bottom surface of the first recess165connecting the first sidewall165saof the first recess defined by the first wire110and the second wire120may include a first portion165bbwhich is substantially planar and a second portion165cbwhich has a curved surface. Likewise, the bottom surface of the second recess166may include a first portion166bbwhich is substantially planar and a second portion166cbwhich has a curved surface.

FIG. 20is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 16 to 18will be mainly explained below.

Referring toFIG. 20, the semiconductor device according to some example embodiments may additionally include the profile of the first recess165and the air gap liner185extending along the upper surface of the first hard mask pattern150.

At least a portion of the first air gap180and at least a portion of the second air gap181may be surrounded by the air gap liner185, and the rest of the first air gap180and the rest of the second air gap181may be surrounded by the second interlayer dielectric film170, but not limited hereto. According to cases, the first opening156between the first hard mask pattern150and the second wire120may be blocked by the air gap liner185. In this case, the first air gap180and the second air gap181may be entirely surrounded by the air gap liner185.

FIG. 21is a layout view provided to explain a semiconductor device according to some example embodiments.FIG. 22is a top view illustrating the semiconductor device ofFIG. 21.FIG. 23is a cross sectional view along line B-B ofFIG. 21.FIG. 24is a cross sectional view along line C-C ofFIG. 21. For convenience of explanation, differences that are not explained above with reference toFIGS. 1 to 6andFIGS. 16 to 18will be mainly explained below.

Referring toFIGS. 21 to 24, the semiconductor device according to some example embodiments may further include a connection recess167connecting the first recess165and the second recess166, and a connection air gap182connecting the first air gap180and the second air gap181.

The first opening157of the first hard mask pattern150may vertically overlap with at least a portion of the first wire110, at least a portion of the second wire120, and at least a portion of the third wire130. The first opening157may extend in the first direction X1and may include first sidewalls156aparallel to each other. The first opening157may include second sidewalls157bconnecting the first sidewalls157aof the first opening.

The first sidewalls157aof the first opening parallel to each other may be positioned on the first wire110and the third wire130, but not limited hereto. As illustrated inFIG. 17, the first sidewalls157aof the first opening may not be positioned on the first wire110and the third wire130. Further, only one of the first sidewalls157aof the first opening may be positioned on the first wire110or the third wire130.

The second wire120may include an end portion120epincluding a short side120bof the second wire. The first opening157may be adjacent to the end portion120epof the second wire, but may not overlap with the end portion120epof the second wire.

The connection recess167may include a sidewall and a bottom surface defined by the short side120bof the second wire and the first interlayer dielectric film160. The connection recess167may connect the first recess165formed between the long side110aof the first wire and the long side120aof the second wire with the second recess166formed between the long side120aof the second wire and the long side130aof the third wire.

Accordingly, the first recess165, the second recess166and the connection recess167may be formed around the end portion120epof the second wire. In other words, at least a portion of the second wire120may be disposed within the first recess165, the second recess166, and the connection recess167. More specifically, the end portion120epof the second wire may be disposed within a recess within the first interlayer dielectric film160formed by the first recess165, the second recess166, and the connection recess167.

Because the first opening157may not overlap with the end portion120epof the second wire, the connection recess167may be covered by the first hard mask pattern150. Accordingly, the connection air gap182may be formed between the end portion120epof the second wire and the first interlayer dielectric film160. The connection air gap182may be disposed within the connection recess167.

The connection air gap182between the end portion120epof the second wire and the first interlayer dielectric film160may connect the first air gap180between the first wire110and the second wire120with the second air gap181between the second wire120and the third wire130. The first air gap180, the second air gap181, and the connection air gap182, which are connected to each other, may be similar to U-shape, for example.

FIG. 25is a view provided to explain a semiconductor device according to some example embodiments. For convenience of explanation, differences that are not explained above with reference toFIGS. 21 to 24will be mainly explained below.

Referring toFIG. 25, the semiconductor device according to some example embodiments may further include the air gap liner185extending along the profile of the first recess165, the profile of the second recess166and the profile of the connection recess167.

Further, the air gap liner185may be formed along the profile of the end portion120epof the second wire. That is, the air gap liner185may be formed on the short side120bof the second wire defining the sidewall of the connection recess167as well as on the upper surface of the second wire120exposed by the first opening157.

Unlike the illustration above, the air gap liner185may not be formed on at least a portion of the bottom surface of the first hard mask pattern150surrounding at least a portion of the sidewall and the bottom surface of the connection recess167and/or a portion of the connection air gap182.

FIG. 26is a layout view provided to explain a semiconductor device according to some example embodiments.FIG. 27is a brief cross sectional view along line D-D ofFIG. 26.

For reference, because a first region I ofFIG. 26may be substantially same as that described above with reference toFIGS. 1 to 6, following description will be made based on a second region II. Further, although the first region I is illustrated similarly toFIG. 1, the first region I may apparently be one of the various embodiments explained with reference toFIGS. 1 to 25.

Referring toFIGS. 26 and 27, the semiconductor device according to some example embodiments may further include a third interlayer dielectric film260, a second hard mask pattern250, fourth and fifth wires210,220, a fourth interlayer dielectric film270, a third recess265, and a third air gap280.

The third interlayer dielectric film260of the second region II may be the second interlayer dielectric film170of the first region I or may be formed farther from the substrate100than the second interlayer dielectric film170of the first region I. In contrast, the fourth interlayer dielectric film270of the second region H may be the first interlayer dielectric film160of the first region I or may be formed nearer to the substrate100than the first interlayer dielectric film160of the first region I.

The following will describe the third interlayer dielectric film260of the second region II as a dielectric film formed at a same level as the second interlayer dielectric film170of the first region I. Herein, the term “same level” as used refers to being formed by a same fabricating process.

The fourth wire210and the fifth wire220may be formed within the third interlayer dielectric film260of the second region II. The fourth wire210and the fifth wire220may extend longitudinally in a third direction X2. Further, the fourth wire210and the fifth wire220may be adjacent to each other in a fourth direction Y2.

The fourth wire210and the fifth wire220may include long sides210a,220aextending in the third direction X2and short sides210b,220bextending in the fourth direction Y2. The long side210aof the fourth wire may face the long side220aof the fifth wire.

The third recess265may be formed within the third interlayer dielectric film260. The third recess265may be formed between the long side210aof the fourth wire and the long side220aof the fifth wire.

The second hard mask pattern250may be formed on the third interlayer dielectric film260. The second hard mask pattern250may be formed on the fourth and fifth wires210,220. The second hard mask pattern250may include a second opening255. The second opening255may expose at least a portion of the fourth and fifth wires210,220.

The fourth interlayer dielectric film270may be formed on the second hard mask pattern250. The fourth interlayer dielectric film270may block the second opening255.

The third air gap280may be formed within the third interlayer dielectric film260. The third air gap280may be formed between the third interlayer dielectric film260and the fourth interlayer dielectric film270as the second opening255is blocked by the fourth interlayer dielectric film270.

Further, in the semiconductor device according to some example embodiments, the width W12of the third recess265in the third direction X2may be substantially equal to the width W22of the second opening255in the third direction X2.

Further, when the air gap liner or the like is not formed, the width W12of the third recess265in the third direction X2may be substantially equal to the width W32of the third air gap280in the third direction X2.

FIGS. 28 to 33Bare views illustrating intermediate stages of fabrication, provided to explain a method for fabricating a semiconductor device according to some example embodiments.FIGS. 29B and 29Care cross sectional views along lines A-A and B-B ofFIG. 29A, respectively. Further,FIGS. 30A, 31A, 32A, and 33Aare cross sectional views along line A-A ofFIG. 29A, respectively, andFIGS. 30B, 31B, 32B and 33Bare cross sectional views along line B-B ofFIG. 29A, respectively.

Referring toFIG. 28, after forming the first interlayer dielectric film160on the substrate100, the first to third wires110,120,130respectively extending in the first direction X1may be formed within the first interlayer dielectric film160. The first to third wires110,120,130may be formed adjacently in the second direction Y1. For example, the first to third wires110,120,130may be formed by making opening in the first interlayer dielectric film160, followed by forming the first to third wires110,120,130in the openings.

Next, referring toFIGS. 29A to 29C, the first hard mask pattern150may be formed on the first interlayer dielectric film160. The first hard mask pattern150may include a first opening155. The first opening155may expose at least a portion of the first interlayer dielectric film160between the first wire110and the second wire120.

The first hard mask pattern150may be formed with a dry etch process40. Even when the dry etch process of forming the first hard mask pattern150is performed, the sidewall of the first wire110and the sidewall of the second wire120may not be exposed.

Next, referring toFIGS. 30A and 30B, a plasma treatment process50may be performed with respect to the first interlayer dielectric film160exposed by the first opening155by using the first hard mask pattern150as a mask. As a result, a plasma treatment region160ptmay be formed within the first interlayer dielectric film160. Compared to other regions of the first interlayer dielectric film160, the plasma treatment region160ptmay have a lower carbon concentration. That is, the plasma treatment region160ptmay be a carbon depletion region.

The plasma treatment process50may be performed by using gas containing, e.g., ammonia (NH3). The plasma treatment process50may be an isotropic plasma treatment process. Accordingly, the isotropic plasma treatment process causes a portion of the first interlayer dielectric film160under the first hard mask pattern150, i.e., a portion of the first interlayer dielectric film160not overlapping vertically with the first opening155, also to be plasma-treated by the plasma treatment process50, e.g., as compared to a plasma-treated region via an anisotropic plasma process that includes only a region overlapping an opening.

A depth of the plasma treatment region160ptmay be less than or equal to the height of the first wire110and the height of the second wire120. Further, because the plasma treatment process50is an isotropic plasma treatment process, a depth of the plasma treatment region160ptmay be substantially equal to a width of the plasma treatment region160ptnot overlapping with the first opening155.

Referring toFIGS. 31A and 31B, the first recess165may be formed within the first interlayer dielectric film160by removing the plasma-treated first interlayer dielectric film160. The first recess165may be formed by removing the plasma treatment region160pt. The plasma treatment region160ptmay be removed, e.g., by using wet etching. The wet etching may use etchant including, e.g., hydrofluoric acid (HF). As the plasma-treated first interlayer dielectric film160includes a portion of the first interlayer dielectric film160under the first hard mask pattern150, the width W11of the first recess165in the first direction X1is greater than the width W21of the first opening155in the first direction X1.

Referring toFIGS. 32A and 32B, the air gap liner185may be formed along the profile of the first recess165. The air gap liner185may be formed along the upper surface of the first hard mask pattern150, the upper surface of the first wire110exposed by the first opening155, and the upper surface of the second wire120exposed by the first opening155.

A process of forming the air gap liner185may be a selective process. Accordingly, subsequent process may be performed without forming the air gap liner185.

Referring toFIGS. 33A and 33B, the second interlayer dielectric film170may be formed on the air gap liner185. The second interlayer dielectric film170may be formed on the first hard mask pattern150. The second interlayer dielectric film170may block, e.g., completely overlap, the first opening155where the air gap liner185is formed. As a result, the first air gap180may be formed within the first recess165, e.g., the first air gap180may be enclosed by the first recess165and the second interlayer dielectric film170.

FIGS. 34A to 35are views illustrating intermediate stages of fabrication, provided to explain a method of fabricating a semiconductor device according to some example embodiments.FIGS. 34A and 34Bmay be the views of a fabrication process which is performed afterFIGS. 29A to 29C. Further,FIG. 34Ais a cross sectional view along line A-A ofFIG. 29A, andFIG. 34Bis a cross sectional view along line B-B ofFIG. 29A.

Referring toFIGS. 34A and 34B, a portion of the first interlayer dielectric film160between the first wire110and the second wire120may be removed while the first hard mask pattern150is being formed by the dry etch process40. That is, while the first hard mask pattern150is being formed by the dry etch process40, a portion of the sidewall of the first wire110and a portion of the sidewall of the second wire120may be exposed.

Referring toFIG. 35, with a portion of the sidewall of the first wire110and a portion of the sidewall of the second wire120being exposed, the plasma treatment process50may be performed on the first interlayer dielectric film160exposed by the first opening155. Because the isotropic plasma treatment process50is performed with a portion of the first interlayer dielectric film160being removed, the depth of the plasma treatment region160ptmay be greater than the width of the plasma treatment region160ptnot overlapping the first opening155.

By way of summation and review, embodiments provide a semiconductor device that can enhance performance and reliability of a semiconductor device by forming an intermetal dielectric film including an air gap between wires. Embodiments also provide a method for fabricating a semiconductor device that can enhance reliability and performance of a semiconductor device by minimizing loss and damage of metal wires in a process of forming an air gap in the intermetal dielectric film.

That is, a recess for an air gap is formed in an undercut region under adjacent metal wires. The undercut region is formed by an isotropic plasma treatment, followed by wet etching of the intermetal dielectric (IMD) layer, to define the undercut region under the metal wires. Accordingly, damage to and loss of the metal wiring, as well as increased resistance, may be minimized, e.g., as compared to dry etching following anistropic plasma that may wear tops of the metal wires and cause wiring loss and increased resistance. In addition, since the IMD layer is removed by an isotropic plasma treatment, followed by wet etching, to define the undercut region under the metal wires, the area of the metal wiring exposed during the etching process is minimized.