Metal-insulator-metal capacitors between metal interconnect layers

An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.

BACKGROUND

This relates generally to integrated circuits, and more particularly, to integrated circuits with metal-insulator-metal capacitors.

Metal-insulator-metal capacitors are typically formed within a dielectric layer that is interposed between two metal interconnect layers. The metal-insulator-metal capacitors are formed having a bottom capacitor electrode and a top capacitor electrode within the dielectric layer. The bottom capacitor electrode is separated from an adjacent metal interconnect layer by a layer of material such as silicon nitride. The metal-insulator-metal capacitor includes contact terminals that are coupled to the bottom and top capacitor electrodes. The contact terminals are formed in a metal interconnect layer that is adjacent to the dielectric layer (e.g., adjacent to the top capacitor electrode). The metal-insulator-metal capacitor is coupled to other circuitry on the integrated circuit by forming routing paths in the adjacent metal layer between other circuitry and the contact terminals.

Metal-insulator-metal capacitors are sometimes used as decoupling capacitors. Decoupling capacitors are often used to help provide more stable power supply voltages to circuitry on an integrated circuit. Decoupling capacitors shunt high frequency noise on direct current (DC) power supply lines to ground power supply lines, thereby preventing the noise from reaching circuit components on the integrated circuit. In a scenario in which a power supply is required to switch between different modes of operation, a decoupling capacitor having a sufficient capacitance can act as an energy reserve that lessens the magnitude of undesired dips in power supply voltage during mode switching events. Decoupling capacitors formed from metal-insulator-metal capacitors may occupy a disproportionate amount of area on the integrated circuit, because regions of metal layers that are used to form the metal-insulator-metal capacitors may be reserved to form contact terminals for the metal-insulator-metal capacitors.

SUMMARY

An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. The metal interconnect layers may include conductive interconnect lines. The inter-metal dielectric layers may include conductive vias that connect the metal interconnect layers. The conductive vias and conductive interconnect lines may, for example, form interconnect structures through which signals are routed throughout the integrated circuit. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes (e.g., electrodes formed from one or more conductive layers).

The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.

The first capacitor electrode may be formed by depositing a first conductive layer over the underlying metal layer and selectively removing portions of the first conductive layer. A capacitor dielectric layer may be subsequently deposited over the first conductive layer. The second capacitor electrode may be formed by depositing a second conductive layer over the capacitor dielectric layer and selectively removing portions of the second conductive layer and the capacitor dielectric layer so that the second capacitor electrode partially overlaps an interconnect line (e.g., an interconnect line in an underlying metal interconnect layer). An etch stop layer and a dielectric material may be deposited over the second capacitor electrode. A via may then be formed by selectively removing a portion of the dielectric material over the interconnect line and depositing conductive material over exposed portions of the top capacitor electrode and the interconnect line.

DETAILED DESCRIPTION

Embodiments of the present invention relate to integrated circuits with capacitor circuitry. Integrated circuits include on-chip circuitry that is powered using external power supplies. The external power supplies may be used to supply the integrated circuits with power supply voltages. It is generally desirable to maintain the power supply voltages at constant voltage levels (e.g., to minimize power supply voltage variation).

The amount of power drawn from a power supply may vary during normal operation of an integrated circuit. To accommodate this type of changing power demand while maintaining constant power supply voltage levels, the integrated circuit may include decoupling capacitor circuitry. The decoupling capacitor circuitry may serve as a local energy storage reserve that provides instantaneous current draw. Providing current using the decoupling capacitor circuitry may help reduce power supply noise.

FIG. 1shows an integrated circuit that includes internal circuitry such as digital/analog circuitry and control circuitry4. Integrated circuit10may be formed as a memory chip, a digital signal processing circuit, a microprocessor, an application specific integrated circuit, a programmable integrated circuit, or other desired integrated circuits.

As shown inFIG. 1, integrated circuit10may include input-output (I/O) circuitry such as I/O circuitry6formed along each edge of integrated circuit10. Circuitry6may be used for driving signals off of device10and for receiving signals from other devices via I/O pins12.

Device10may include capacitors8. Capacitors8may be formed in groups. For example, capacitors8may be formed as arrays of capacitors. Capacitors8may, if desired, be used as decoupling capacitors to help reduce power supply noise. If desired, capacitors8may be used to form circuitry such as low-pass filter circuitry, high-pass filter circuitry, or other desired circuitry. For example, capacitors8that are formed as part of digital/analog circuitry4may be used to form a low-pass filter that reduces the magnitude of low-frequency components of a high-frequency data signal.

Capacitors8of varying configurations (e.g., individual capacitors or capacitor arrays of different sizes and shapes) may be formed on device10. Capacitors8may be formed in many locations (e.g. adjacent to I/O circuitry6, as an integral part of I/O circuitry6, adjacent to circuits4that are sensitive to power supply variation, overlapping with digital/analog circuitry and control circuitry4, or at any desired location on device10). Tens or hundreds of capacitors may be formed on device10, if desired.

Some of capacitors8may serve to reduce power supply variation at respective locations on device10(e.g., some of capacitors8may be decoupling capacitors). As an example, consider a scenario in which an external power source supplies a 1.2 V positive power supply voltage to device10. Device10may include communications circuitry4operating at high data rates (e.g., data rates greater than 1 Gbps). During an idle mode, communications circuitry4may draw 0.5 A of current from the power source (as an example). During a transmit mode, the communications circuitry may draw 0.7 A of current from the power source. During switching operations from the idle mode to the transmit mode, a decoupling capacitor8located adjacent to communications circuitry4on device10may serve to provide 0.2 A of current (0.7 A-0.5 A) so that communications circuitry8receives a constant positive supply voltage of 1.2 V.

Consider another scenario in which the positive power supply experiences an instantaneous voltage glitch. Decoupling capacitors8may dampen or absorb this glitch by providing instantaneous current to internal circuitry4so that the positive power supply voltage received at the local power supply terminal of circuitry4remains constant at 1.2 V (as an example). Decoupling capacitors8used to maintain constant power supply voltage while supplying the desired current draw may be referred to as ballasting circuitry.

Integrated circuit10may include interconnect layers that are formed above a substrate. The substrate layer may, for example, be formed from silicon or other semiconductor substrate materials, whereas the interconnect layers may include conductive materials such as metals (e.g., copper, aluminum, etc.). The interconnect layers can be used to route signals throughout the integrated circuit. For example, conductive paths may be formed within a given interconnect layer to route signals from a first location to a second location on integrated circuit10.

The interconnect layers may sometimes be referred to as metal layers or metal interconnect layers, because the conductive paths of the interconnect layers are often formed of metals such as copper or aluminum. Dielectric layers may be interposed between the metal interconnect layers so that signals traversing a given metal interconnect layer are isolated from signals that traverse neighboring interconnect layers (e.g., so that a given interconnect layer is insulated from adjacent interconnect layers). As an example, the dielectric layers may be formed from oxides such as silicon dioxide. The dielectric layers may sometimes be referred to as inter-metal dielectric (IMD) layers.

Capacitors8may be formed using the inter-metal dielectric layers. For example, a capacitor8may be formed as a parallel plate capacitor within an inter-metal dielectric layer that is interposed between two adjacent metal layers. Capacitors that are formed as parallel plate capacitors within the inter-metal dielectric layers are sometimes referred to as metal-insulator-metal (MIM) capacitors.FIG. 2is an illustrative cross-sectional diagram of a metal-insulator-metal capacitor formed using an inter-metal dielectric layer of device10.

As shown inFIG. 2, device10may include a substrate22over which metal interconnect layers MX and MY are formed. Circuitry such as metal-oxide-semiconductor (MOS) transistors or other circuit components may be formed within the substrate. Layers MX and MY may include conductive interconnect paths (e.g., conductive interconnect lines) such as conductive paths26,28, and30that can be used to route signals between circuitry of device10. Conductive paths26,28, and30may be formed in any desired direction within a corresponding metal layer. For example, paths28and26may be formed within metal layer MX along an axis into and out of the page, whereas path30of metal layer MY may extend beyond the right side of the page.

Dielectric layers (e.g., inter-metal dielectric layers) may be interposed between each pair of metal layers so that the metal layers are electrically isolated from each other. The dielectric layers may help prevent signals that traverse conductive paths of a given metal layer from reaching other metal layers. For example, dielectric layer IX may help isolate signals that traverse conductive path28of metal layer MX from signals on conductive path30of metal layer MY.

Metal-insulator-metal capacitor8may be formed within inter-metal dielectric layer IX. Metal-insulator-metal capacitor8may include a bottom capacitor electrode34formed from a first conductive layer, a dielectric layer36, and a top capacitor electrode32formed from a second conductive layer. Capacitor electrodes32and34may effectively form a parallel plate capacitor with dielectric layer36separating layers32and34. The capacitance of capacitor8may be proportional to the overlapping area of capacitor electrodes32and34(e.g., the capacitance of capacitor8may be increased by increasing the overlapping area of capacitor electrodes32and34). The capacitance of capacitor8may be inversely proportional to the thickness of dielectric layer36and may also be dependent on the dielectric constant of the material used to form dielectric layer36.

Bottom capacitor electrode34of capacitor8may be formed directly above and contacting path28of metal layer MX. Top capacitor electrode32may be formed to cover bottom capacitor electrode34and also cover a portion of conductive path26. Via40may be formed through inter-metal dielectric layer IX between metal layers MX and MY so that region42of top conductive layer32and region44of path26are electrically coupled together. Via40may be formed having any desired shape (e.g., by selectively removing portions of inter-metal dielectric layer IX to form a desired shape). Via40may electrically couple top capacitor32, path26of layer MX, and path30of layer MY. For example, via40may be formed using conductive materials such as copper, aluminum, etc. Path30of metal layer MY may be used to couple via40(and top capacitor electrode32) to other circuitry on device10.

By forming metal-insulator-metal capacitor8so that bottom capacitor electrode34directly contacts conductive path28and top capacitor electrode32is electrically coupled to path26, available area of metal layers MY and MX may be conserved. For example, the region of metal layer MY above capacitor8may be used to form conductive paths for routing signals. As another example, metal-insulator-metal capacitor8may be formed between existing conductive paths of a given integrated circuit layout.

Consider the scenario in which path26is a power supply path through which a positive power supply voltage is routed to circuitry throughout device10and path28is a power supply ground path. In this scenario, metal-insulator-metal capacitor8may be formed as a decoupling capacitor between the power supply path and the power supply ground path without altering the existing circuit layout (e.g., without forming separate contact terminals for top capacitor electrode32and bottom capacitor electrode34or forming additional routing paths in metal layers MX and MY).

The example ofFIG. 2in which capacitor8is formed within inter-metal dielectric layer IX is merely illustrative. If desired, device10may be formed with any number of metal layers (e.g.,2,4,6, or more) and inter-metal dielectric layers (e.g., a dielectric layer may be formed between each pair of conductive layers). As an example, additional metal and dielectric layers may be formed above and/or below metal layers MX and MY. Metal-insulator-metal capacitors8may be formed within one or more desired insulating layers.

FIGS. 3-11show illustrative steps involved in forming a metal-insulator-metal capacitor8coupled between conductive paths of a given metal layer. As shown inFIG. 3, device10may be formed with conductive paths26and28in a first metal layer MX. Paths26and28, may, for example, be used as signal routing paths for routing data signals or power supply signals throughout device10(or throughout regions of device10). Metal layer MX may be formed above region24and substrate22(e.g., a region including zero or more additional metal layers or insulating layers). As an example, circuitry such as transistors may be formed within substrate22. In this scenario, the circuitry may be coupled to paths26and28via additional signal routing paths formed from layers of region24.

As shown inFIG. 4, a conductive layer52may be formed over metal layer MX. Conductive layer52may be formed by depositing a conductive material such as tantalum nitride, titanium nitride, tungsten nitride, or other conductive materials over metal layer MX. Conductive layer52may be deposited using deposition techniques such as atomic layer deposition (ALD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other desired types of coating techniques. Conductive layer52may be formed having any desired thickness. For example, layer52may be formed of a layer of tantalum nitride with a thickness of about 200 angstroms to 400 angstroms.

As shown inFIG. 5, bottom capacitor electrode34may be formed by selectively removing portions of conductive layer52. For example, a photoresist mask may be applied to conductive layer52and an etching process may be subsequently performed to selectively remove portions of layer52(e.g., portions of layer52that are not covered by the photoresist mask). As an example, an anisotropic plasma etching process may be used (e.g., using plasma etchants such as sulfur hexafluoride, nitrogen trifluoride, dichlorodifluoromethane, etc.) to selectively etch into conductive layer52. As another example, an anisotropic wet etching process may be used (e.g., using wet etchants such as nitric acid, hydrofluoric acid, or other acids) to selectively form bottom capacitor electrode34. The photoresist mask may be subsequently removed using processes such as plasma ashing.

A dielectric layer54may be subsequently deposited over bottom capacitor electrode34and metal layer MX as shown inFIG. 6. Dielectric layer54may be deposited using any desired deposition technique. Layer54may be formed from any suitable dielectric material such as undoped silicon glass (e.g., silicon dioxide) or other oxides. Layer54be formed having any desired thickness such as about 200 angstroms (as an example). The thickness of dielectric layer54may be reduced to increase the capacitance of capacitor8that is formed by the steps ofFIGS. 3-11.

If desired, dielectric layer54may be formed of materials such as high-κ dielectric materials (e.g., chromium oxide, hafnium oxide, hafnium silicate, zirconium silicate, zirconium oxide, etc.). As an example, a layer of silicon dioxide may exhibit a dielectric constant κ of 3.9, whereas a layer of hafnium oxide may exhibit a relatively high dielectric constant κ of 25. The use of high-κ material in dielectric layer54may provide increased capacitance for a given thickness of dielectric layer54.

As shown inFIG. 7, a conductive layer56may be deposited over dielectric layer54. Conductive layer56may be formed using deposition techniques substantially similar to layer52ofFIG. 4. For example, a layer of tantalum nitride or other conductive material may be deposited over dielectric layer54using atomic layer deposition to form conductive layer56. Conductive layer56may be formed of any desired thickness such as about 500 angstroms.

In a subsequent step after depositing conductive layer56, top capacitor electrode32and capacitor dielectric layer36may be formed by selectively removing portions of conductive layer56and dielectric layer54. As shown inFIG. 8, top capacitor electrode32and capacitor dielectric layer36may be formed to overlap with conductive path26and bottom capacitor electrode34. Top capacitor electrode32and capacitor dielectric layer36may be formed from conductive layer56and dielectric layer54by applying a photoresist mask over conductive layer56and subsequently performing an etching process to selectively remove portions of conductive layer56and underlying dielectric layer36.

After forming top capacitor electrode32and capacitor dielectric layer36, an etch stop layer58may be deposited over top capacitor electrode32and metal layer MX as shown inFIG. 9. Etch stop layer58may be formed from a material that is resistant to etching such as nitrides (e.g., silicon nitride, titanium nitride, etc.).

As shown inFIG. 10, inter-metal dielectric layer IX may be subsequently formed. Inter-metal dielectric layer IX may be filled with a dielectric material60such as an oxide material (e.g., silicon dioxide). Dielectric material60may be deposited over etch stop layer58using any desired deposition technique (e.g., chemical vapor deposition or other deposition techniques). Planarization techniques such as chemical-mechanical planarization (CMP) may then be applied to remove any excessive dielectric material protruding beyond the upper surface of dielectric layer IX.

As shown inFIG. 11, a via40may then be formed that electrically couples top capacitor electrode32to conductive path26. Via40may be formed by applying a photoresist mask over dielectric layer60and performing an etching process to selectively remove a portion of inter-metal dielectric layer IX located above conductive path26. Etch stop layer58may be resistant to the etching process and may help isolate top capacitor electrode32and conductive path26from the etching process.

Portions of etch stop layer58that cover top capacitor electrode32and conductive path26may be removed during the etching process or during a subsequent etch stop removal process (e.g., an etching process that removes materials such as nitrides or other etch stop layer materials). In particular, portions of etch stop layer58over regions42and44may be removed to expose underlying portions of top capacitor electrode32and conductive path26. Via40may be subsequently filled with a conductive material such as copper, aluminum, or other conductive materials. If desired, multiple layers of different conductive materials may be used to fill vias40. The conductive material may directly contact regions42and44so that top capacitor electrode32is electrically coupled to conductive path26(e.g., so that regions42and44are electrically shorted together).

The example ofFIG. 11in which regions42and44are exposed during the etching process is merely illustrative. If desired, portions of etch stop layer58that cover regions42and44may remain after the etching process (e.g., a residual layer of etch stop layer58may remain). For example, etch stop layer58may be formed of a conductive material such as titanium nitride that is resistant to the etchant used to etch dielectric layer60. In this scenario, etch stop layer58may form part of top capacitor electrode32and may isolate top capacitor electrode32and conductive path26from the etchant while allowing top capacitor electrode32to contact via40and conductive path26.

Via40and conductive path26may collectively form a first capacitor terminal that is coupled to top capacitor electrode32. Conductive path28may form a second capacitor terminal that is coupled to bottom capacitor electrode34.

If desired, additional layers may be formed above dielectric layer IX. For example, an additional metal layer MY such as shown inFIG. 2may be formed above dielectric layer IX. In this scenario, metal layer MY may include conductive paths such as path30that contact via40. The additional layers may be formed using any suitable deposition techniques.

FIG. 12is a flowchart100of illustrative steps that may be performed to form a metal-insulator capacitor on an integrated circuit (e.g., as described in connection withFIGS. 3-11).

In step102, a metal layer having a first conductive path and a second conductive path may be selected (e.g., metal layer MX that has a first conductive path26and a second conductive path28). The first and second conductive paths may have been formed as a part of circuitry on the integrated circuit. For example, the first conductive path may have been formed as a power supply path or a data signal path and the second conductive path may have been formed as a ground supply path.

In step104, a first conductive layer may be directly deposited on the selected metal layer. The first conductive layer may be deposited to contact the first conductive path. Depositing tools may be used to deposit the first conductive layer on the selected metal layer. As an example, conductive layer52ofFIG. 4may be deposited over metal layer MX using atomic layer deposition tools.

In step106, fabrication tools such as photolithography tools may be used to form a bottom capacitor electrode from the first conductive layer (e.g., bottom capacitor electrode34as shown inFIG. 5). The bottom capacitor electrode may be formed to contact the first conductive path without contacting the second conductive path. As an example, photolithography tools may be used to apply a photoresist mask that selectively identifies regions of the first conductive layer that should be removed. In this scenario, etching tools may be used to selectively remove the identified regions of the first conductive layer so that the bottom capacitor electrode only contacts the first conductive path.

In step108, depositing tools may be used to deposit a dielectric layer over the first conductive layer (e.g., as shown inFIG. 6, dielectric layer54may be deposited over the first conductive layer and exposed regions of metal layer MX). The dielectric layer may form a capacitor dielectric layer of the metal-insulator-metal capacitor.

In step110, depositing tools may be used to deposit a second conductive layer over the capacitor dielectric layer. For example, conductive layer56may be formed over dielectric layer54as shown inFIG. 7.

In step112, photolithography tools may be used to form a top capacitor electrode by selectively removing portions of the second conductive layer and the underlying capacitor dielectric layer. For example, the photolithography tools may be used to apply a photoresist mask and subsequently perform an etching process to form top capacitor electrode32as shown inFIG. 8.

In step114, depositing tools may be used to deposit an etch stop layer over the second conductive layer and regions of the metal layer that have been exposed by the operations of step112(e.g., portions of the metal layer that have been exposed by an etching process). As an example, etch stop layer58may be formed as shown inFIG. 9.

In step116, an inter-metal dielectric layer may be formed by depositing a layer of dielectric material over the etch stop layer. If desired, polishing tools may be used to ensure that the inter-metal dielectric layer forms a planar layer (e.g., by polishing the surface of the inter-metal dielectric layer to remove irregularities). As an example, dielectric layer60may be deposited to form inter-metal dielectric layer IX as shown inFIG. 10.

In step118, a via may be formed over the second conductive path. The via may directly contact the top capacitor electrode and the second conductive path, thereby providing an electrical path between the top capacitor electrode and the second conductive path. As an example, via40ofFIG. 11may be formed that contacts region42of top capacitor electrode32and region44of conductive path26.

FIG. 13is a diagram of fabrication tools122that may be used to form metal-insulator-metal capacitors such as capacitor8on an integrated circuit. As shown inFIG. 13, fabrication tools122may include depositing tools124, polishing tools126, and photolithography tools128. If desired, fabrication tools122may include other tools desirable for fabricating integrated circuits (e.g., tools suitable for performing the steps of flowchart100ofFIG. 12).

Depositing tools124may include tools for performing atomic layer deposition (ALD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. Depositing tools124may, for example, be used to deposit conductive layers, dielectric layers, etch stop layers, or other materials on the integrated circuit. Polishing tools126may include tools for performing chemical-mechanical planarization (CMP) polishing or other polishing techniques. Photolithography tools128may be used to apply photoresist masks to the integrated circuit. Photolithography tools128may include etching tools130for selectively removing portions of the integrated circuit based on the applied photoresist masks. Etching tools130may, for example, include wet etching tools or dry etching tools. Etching tools128may be used to remove photoresist material, conductive layers, dielectric layers, or other materials from the integrated circuit.

As another suitable embodiment, metal-insulator-metal capacitors may be formed on an integrated circuit that is used to route signals between two or more different integrated circuits. The given integrated circuit that is used to route signals between two different integrated circuits may sometimes be referred to as an interposer, because the given integrated circuit may be interposed between the two different integrated circuits.FIG. 14is an illustrative device200in which an interposer202is coupled to two integrated circuits10(e.g., each integrated circuit10may be formed substantially similar to integrated circuit10ofFIG. 1). Each integrated circuit10may be formed on respective substrates. Interposer202may be formed on substrate204.

As shown inFIG. 14, interposer202may include metal layers MX and MY and inter-metal dielectric layer IX interposed between metal layers MX and MY. Interposer202may be coupled to each integrated circuit10via respective coupling paths206. As an example, coupling paths206may be formed of solder (e.g., solder balls) or other conductive materials such as copper (e.g., copper microbumps may be formed to contact integrated circuits10with interposer202). Coupling paths206may be coupled to metal layer MY.

Metal layers such as MY and MX may be used to route signals between integrated circuits10. The signals may be routed through one or more metal layers. For example, a first signal may be routed directly between integrated circuits10through metal layer MY, whereas a second signal may be routed from a first integrated circuit10through metal layer MY and via40to a second metal layer MX. In this scenario, the second signal may be routed through metal-insulator-metal capacitor8to path28before being routed to a second integrated circuit10. Metal-insulator-metal capacitors8may be used to form any desired circuit configuration within interposer202. For example, metal-insulator-metal capacitors8may be used to form filters such as high-pass or low-pass filters, may be used to form decoupling capacitors, or other desired circuitry. If desired, each signal may be routed through any suitable number of metal layers (e.g., so that available area of metal layers is efficiently utilized when forming capacitors8).

The example ofFIG. 14in which metal-insulator-metal capacitor8is formed on metal layer MX is merely illustrative. If desired, metal-insulator-metal capacitor8may be formed on any desired metal layer of interposer202. Multiple metal-insulator-metal capacitors8may be formed between any two desired conductive paths of a selected metal layer (e.g., to provide a series capacitance between the two conductive paths).

Metal-insulator-metal capacitor8may be used to form decoupling capacitors between power supply lines of an existing integrated circuit layout.FIG. 15is a top-down view of metal-insulator-metal capacitors8formed as decoupling capacitors. As shown inFIG. 15, device10may include power supply lines VCC and VSS that are used to supply power to circuitry on device10(e.g., power supply lines formed in a given metal interconnect layer). Metal-insulator-metal capacitor8may be formed to overlap power supply lines VCC and VSS. Vias40may be formed for each capacitor8to simultaneously contact a first power supply line and capacitor8(e.g., a top capacitor electrode of capacitor8), whereas each capacitor8may contact a second power supply line (e.g., a bottom capacitor electrode may contact the second power supply line).