A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

TECHNICAL FIELD

This application relates generally to analog-to-digital converters (ADCs).

BACKGROUND

A key building block of high-speed (>1 GS/s), high-resolution (>10-bits) ADC is the input buffer, and is employed to drive the ADC frontend, which comprises of a track-and-hold (T/H) circuit. T/H circuits are often implemented by a high-speed, highly linear sampling switch and on-chip sampling capacitor, which together present a switching load to the input buffer. Consequently, in addition to driving the analog input signal, the input buffer also needs to absorb and settle the voltage kickback caused by the switched capacitor load. This issue is further exacerbated in time-interleaved ND converters, in which several T/H circuits are driven in sequence by the buffer.

FIG. 1illustrates an ADC frontend10driven by an input buffer100. The input buffer100is electrically coupled to multiple T/H circuits110, which are electrically coupled in parallel with each other.FIG. 2illustrates a timing diagram200of the ADC frontend10and the corresponding input and output voltages (VIN, VOUT)210of the input buffer100. The ADC sampling frequency is denoted by “fs” and each T/H circuit110tracks for Ts=1/fs duration. At the sampling instants, the sampling switch is turned off (i.e., opened) resulting in voltage kickback as depicted in the VOUTwaveform. The signal-dependent fraction of this kickback, if not fully settled, will exhibit as non-linearity at the ADC output thereby degrading the ADC performance. As a result, additional power consumption is required in the input buffer to increase bandwidth and reduce the output impedance in order to absorb and fully settle the voltage kickback. This additional power dissipation results in higher buffer area as well as degrades the ADC figure-of-merit, both of which are undesirable.

SUMMARY

Example embodiments described herein have innovative features, no single one of which is indispensable or solely responsible for their desirable attributes. The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrative examples, however, are not exhaustive of the many possible embodiments of the disclosure. Without limiting the scope of the claims, some of the advantageous features will now be summarized. Other objects, advantages and novel features of the disclosure will be set forth in the following detailed description of the disclosure when considered in conjunction with the drawings, which are intended to illustrate, not limit, the invention.

An aspect of the invention is directed to a time-interleaved circuit, comprising: an input buffer configured to receive an input signal having an input voltage and to output an output signal having an output voltage; a plurality of track-and-hold circuits electrically coupled in parallel with each other, each track-and-hold circuit electrically coupled in series with the input buffer; and an isolation inductor electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

In one or more embodiments, the time-interleaved circuit comprises an analog-to-digital converter. In one or more embodiments, the isolation inductor is a first isolation inductor in a plurality of isolation inductors, each isolation inductor electrically coupled to the output of the input buffer and only one of the track-and-hold circuits. In one or more embodiments, each track-and-hold circuit comprises a sampling switch and a sampling capacitor.

In one or more embodiments, the isolation inductor is a first isolation inductor and the input buffer is a first input buffer, and the circuit further comprises: first and second groups of the track-and-hold circuits; a second input buffer configured to receive the input signal; and a second isolation inductor. The first isolation inductor is electrically coupled to the output of the first input buffer and an input of the first group of the track-and-hold circuits. The second isolation inductor is electrically coupled to an output of the second input buffer and an input of the second group of the track-and-hold circuits. In one or more embodiments, each track-and-hold circuit comprises a respective sampling switch and a respective sampling capacitor; the respective sampling switches in the first group of the track-and-hold circuits are electrically coupled to respective odd drive signals that cause the respective sampling switches in the first group to open on respective odd clock cycles; and the respective sampling switches in the second group of the track-and-hold circuits are electrically coupled to respective even drive signals that cause the respective sampling switches in the second group to open on respective even clock cycles. In one or more embodiments, the respective odd drive signals and the respective even drive signals are configured to cause the respective sampling switches in the first and second groups to open in a predetermined sequence such that only one sampling switch transitions to an open state in a given clock cycle.

In one or more embodiments, the circuit further comprises a third group of track-and-hold circuits; a third input buffer configured to receive the input signal; and a third isolation inductor, wherein the third isolation inductor is electrically coupled to the output of the third input buffer and an input of the third group of the track-and-hold circuits. In one or more embodiments, the circuit further comprises a fourth group of track-and-hold circuits; a fourth input buffer configured to receive the input signal; and a fourth isolation inductor, wherein the fourth isolation inductor is electrically coupled to the output of the fourth input buffer and an input of the fourth group of the track-and-hold circuits.

In one or more embodiments, the input buffer comprises a source follower amplifier. In one or more embodiments, the input buffer comprises a push-pull amplifier. In one or more embodiments, the isolation inductor has an inductance of less than or equal to about 100 pH. In one or more embodiments, the circuit is integrated into a single chip.

Another aspect of the invention is directed to a time-interleaved circuit, comprising: a first input buffer configured to receive an input signal having an input voltage and to output a first output signal having a first output voltage; a second input buffer configured to receive the input signal and to output a second output signal having a second output voltage; a first group of track-and-hold circuits electrically coupled in parallel with each other, each track-and-hold circuit in the first group electrically coupled in series with the first input buffer; a second group of track-and-hold circuits electrically coupled in parallel with each other, each track-and-hold circuit in the second group electrically coupled in series with the second input buffer; a first isolation inductor electrically coupled to the output of the first input buffer and the track-and-hold circuits in the first group; and a second isolation inductor electrically coupled to the output of the second input buffer and the track-and-hold circuits in the second group.

In one or more embodiments, each track-and-hold circuit in the first and second groups comprises a respective sampling switch and a respective sampling capacitor; the respective sampling switches in the first group of the track-and-hold circuits are electrically coupled to respective odd drive signals that cause the respective sampling switches in the first group to open on respective odd clock cycles; and the respective sampling switches in the second group of the track-and-hold circuits are electrically coupled to respective even drive signals that cause the respective sampling switches in the second group to open on respective even clock cycles. In one or more embodiments, the respective odd drive signals and the respective even drive signals are configured to cause the respective sampling switches in the first and second groups to open in a predetermined sequence such that only one sampling switch transitions to an open state in a given clock cycle.

In one or more embodiments, the first input buffer comprises a first source follower amplifier, and the second input buffer comprises a second source follower amplifier. In one or more embodiments, the first input buffer comprises a first push-pull amplifier, and the second input buffer comprises a second push-pull amplifier. In one or more embodiments, the time-interleaved circuit comprises an analog-to-digital converter. In one or more embodiments, the first and second isolation inductors each have an inductance of less than or equal to about 100 pH. In one or more embodiments, the circuit is integrated into a single chip.

In one or more embodiments, the circuit further comprises a third input buffer configured to receive the input signal and to output a third output signal having a third output voltage; a third group of track-and-hold circuits electrically coupled in parallel with each other, each track-and-hold circuit in the third group electrically coupled in series with the third input buffer; and a third isolation inductor electrically coupled to the output of the third input buffer and the track-and-hold circuits in the third group. In one or more embodiments, the circuit further comprises a fourth input buffer configured to receive the input signal and to output a fourth output signal having a fourth output voltage; a fourth group of track-and-hold circuits electrically coupled in parallel with each other, each track-and-hold circuit in the fourth group electrically coupled in series with the fourth input buffer; and a fourth isolation inductor electrically coupled to the output of the fourth input buffer and the track-and-hold circuits in the fourth group.

DETAILED DESCRIPTION

A time-interleaved (TI) circuit includes a plurality of isolation inductors that are electrically coupled to an input buffer and one or more T/H circuits. The isolation inductors reduce kickback in the output voltage of the output signal produced by the input buffer. In one embodiment, the TI circuit includes the same number of isolation inductors and T/H circuits such that each isolation inductor is electrically coupled to a respective T/H circuit. In another embodiment, the TI circuit includes only first and second isolation inductors. The first isolation inductor is electrically coupled to a first group of T/H circuits. The second isolation inductor is electrically coupled to a second group of T/H circuits. Each isolation inductor can be electrically coupled to a respective input buffer (e.g., to first and second input buffers). The driving signals for T/H circuits can cause the first and second groups to be phase-offset such that the driving signals alternately cause a sampling switch in the T/H circuit in the first group to transition to the open state and a sampling switch in the T/H circuit in the second group to transition to the open state (e.g., in a ping-pong configuration).

FIG. 3is a schematic diagram of a TI circuit30according to an embodiment. The circuit30includes an input buffer300, a plurality of T/H circuits310, and a plurality of isolation inductors320. The input buffer300is configured to receive an input signal having an input voltage VINwhich can be time-varying. The input buffer300produces an output signal having an output voltage VOUTthat can be related to the input signal and input voltage, respectively.

The T/H circuits310are electrically coupled in parallel with each other. The T/H circuits310can comprise sample-and-hold circuits or ADCs in some embodiments. Each T/H circuit310includes a sampling switch312and a sampling capacitor314. The state of each sampling switch312is controlled by a respective drive signal330. The drive signals330are configured to cause the sampling switches312to transition from a closed state to an open state. The drive signals330are phase-offset such that the sampling switches312enter the open state on different clock cycles and/or in a predetermined time sequence (e.g., as illustrated inFIG. 4). For example, drive signal Φ1can cause the corresponding sampling switch312to transition to the open state on clock cycle1, drive signal Φ2can cause the corresponding sampling switch312to transition to the open state on clock cycle2, drive signal Φ3can cause the corresponding sampling switch312to transition to the open state on clock cycle3, and drive signal Φ4can cause the corresponding sampling switch312to transition to the open state on clock cycle4. In general, drive signal ΦNcan cause the corresponding sampling switch312to transition to the open state on clock cycle N.

Each isolation inductor320is electrically coupled between a corresponding T/H circuit310and the input buffer300. For example, each isolation inductor320can be electrically coupled in series between the input buffer and the corresponding T/H circuit310. Each inductor can have an inductance of less than or equal to about 100 pH, such as about 25 pH, about 50 pH, about 75 pH, but different ranges of values may be desired for different applications. As used herein, “about” means plus or minus 10% of a given value.

FIG. 4illustrates a timing diagram400of the TI circuit30and the corresponding input and output voltages (VIN, VOUT)410of the input buffer300. At the sampling instants, when the sampling switches312turn off (i.e., close), the respective isolation inductors320isolates the subsequent voltage kickback from the input buffer300. As a result, the buffer output voltage (VOUT) exhibits significantly reduced kickback compared to the prior art (e.g.,FIG. 2). Little additional power is now needed to fully settle the signal dependent fraction of the voltage kickback. Furthermore, employing the isolation inductors320increases the tracking bandwidth due to shunt peaking, which improves tracking bandwidth especially when the input frequency is near Nyquist frequency (i.e., 0.5 fs). Since the voltage kickback is at fairly high frequency (e.g., >3 fs), the isolation inductor can have a relatively small inductance value (e.g., ≤about 100 pH, as discussed above), which results in a small increase in semiconductor die area.

FIG. 5is a schematic diagram of a TI circuit50according to an alternative embodiment. The circuit includes a first input buffer501(e.g., input buffer A), a second input buffer502(e.g., input buffer B), a first group541of T/H circuits510, a second group542of T/H circuits510, a first isolation inductor521(e.g., isolation inductor A), and a second isolation inductor522.

The first and second input buffers501,502have respective inputs that are electrically coupled to an input signal having an input voltage VINwhich can be time-varying. The first and second input buffers501,502produce respective output signals having respective output voltages VOUTA, VOUTB. Each output signal and output voltage VOUTA, VOUTBcan be related to the input signal and input voltage, respectively. The input buffers501,502are preferably identical or substantially identical to each other. Each input buffer501,502can be the same as or different than input buffer300.

The T/H circuits510in each group541,542are electrically coupled in parallel with each other. The T/H circuits510are preferably identical or substantially identical to each other. Each T/H circuit510can be the same as or different than T/H circuit310. Each T/H circuit510includes a sampling switch512and a sampling capacitor514. Each group541,542can have any number of T/H circuits510, such as about 2-30 T/H circuits, including about 5 T/H circuits, about 10 T/H circuits, about 15 T/H circuits, about 20 T/H circuits, about 25 T/H circuits, or any value or range between any two of the foregoing number of T/H circuits. Each group541,542preferably has the same number of T/H circuits510. For example, each group541,542preferably has N T/H circuits.

The state of each sampling switch512is controlled by a respective drive signal530. The drive signals530are configured to cause the sampling switches512to transition from a closed state to an open state. The drive signals530can be the same as or different than drive signals330. The drive signals530are phase-offset such that the sampling switches512enter the open state on different clock cycles and/or in a predetermined time sequence (e.g., as illustrated inFIG. 6). The T/H circuits510in the first group541are configured to receive odd drive signals531that cause the corresponding sampling switches512in the first group541of T/H circuits510to enter the hold state on odd or relative odd clock cycles. The T/H circuits510in the second group542are configured to receive even drive signals532that cause the corresponding sampling switches512in the second group542of T/H circuits510to enter the hold state on even or relative even clock cycles. A relative even or odd clock cycle can be even or odd compared to a first drive cycle (e.g., drive signal (Φ1) in the predetermined sequence where the first drive signal can be set as an odd clock cycle without regard to the absolute clock cycle.

In this configuration, the predetermined sequence alternates between T/H circuits510in the first group541and T/H circuits510in the second group542(e.g., in a ping-pong arrangement or configuration). For example, drive signal (Φ1can cause the corresponding sampling switch512(e.g., switch1) in first group541to transition to the open state on clock cycle1, drive signal Φ2can cause the corresponding sampling switch512(e.g., switch2) in second group542to transition to the open state on clock cycle2, drive signal Φ3can cause the corresponding sampling switch512(e.g., switch3) in first group541to transition to the open state on clock cycle3, and drive signal Φ4can cause the corresponding sampling switch512(e.g., switch4) in second group542to transition to the open state on clock cycle4.

The first and second isolation inductors521,522are electrically coupled to the first and second groups541,542, respectively, and the first and second input buffers501,502, respectively. For example, the first isolation inductor521is electrically coupled in series with the output of the first input buffer501. The first isolation inductor521is also electrically coupled in series with the first group541of T/H circuits510. Since the T/H circuits510in the first group541are electrically coupled in parallel with each other, the first isolation inductor521is also electrically coupled in series with each T/H circuit510in the first group541. Similarly, the second isolation inductor522is electrically coupled in series with the output of the second input buffer502. The second isolation inductor522is also electrically coupled in series with the second group542of T/H circuits510. Since the T/H circuits510in the first group541are electrically coupled in parallel with each other, the second isolation inductor522is also electrically coupled in series with each T/H circuit510in the second group542. The first and second inductors521,522are preferably identical or substantially identical to each other (e.g., having an inductance values within 10% of each other). The first and second inductors521,522can be the same as different than inductor320.

The embodiment ofFIG. 5can alleviate the linear increase of inductor semiconductor die area with the number of interleaved T/H circuits (e.g., as described above). In this implementation, the input buffer is split in two halves A and B (e.g., first and second input buffers501,502with 50% power each), with their inputs shorted. Further, the interleaved T/H circuits510are arrayed in a ping-pong configuration with T/H circuits510operating on odd clock phases or cycles are driven by the first input buffer501(bank A) while T/H circuits510operating on odd clock phases or cycles are driven the second input buffer502(bank B). This ping-pong configuration provides inherent isolation between the two groups541,542and banks A, B, respectively. In addition, the ping-pong configuration reduces the number of isolation inductors compared to the embodiment ofFIG. 3. InFIG. 5, only one isolation inductor521is coupled to the T/H circuits510in the first group541and only one isolation inductor522is coupled to the T/H circuits510in the second group542. This configuration allows the number of T/H circuits510to be increased (or decreased) using only two isolation inductors, reducing the semiconductor die area used for isolation inductors compared to the configuration illustrated inFIG. 3. However, the configuration ofFIG. 5provides the same or substantially the same advantages as described above for the configuration illustrated inFIG. 3.

In general, TI circuit50can include N input buffers, N isolation inductors, and N groups of T/H circuits510. Each input buffer is configured to receive an input signal having an input voltage and to output an output signal having a respective output voltage. Each group of T/H circuits510includes one or more T/H circuits510. When a group includes a plurality of T/H circuits510, the T/H circuits510in that group are electrically coupled in parallel with each other. A respective isolation inductor is electrically coupled to (e.g., electrically coupled in series with) the output of the respective input buffer and each T/H circuit510in the respective group of T/H circuits510.

In an alternative embodiment, TI circuit50can include only one input buffer. In this embodiment, a first output of the input buffer is electrically coupled to the first isolation inductor521and to the first group541of T/H circuits510, and a second output of the input buffer is electrically coupled to the second isolation inductor522and to the second group542of T/H circuits510. The first and second outputs of the input buffer having the same voltage VOUT, which can be related to the input signal and input voltage VIN.

FIG. 6illustrates a timing diagram600of the TI circuit50and the corresponding input and output voltages (VIN, VOUTA)610of the first input buffer501. The input and output voltages (VIN, VOUTB) of the second input buffer502are identical or substantially identical to the input and output voltages (VIN, VOUTA)610, respectively, of the first input buffer501. As can be seen, VOUTAinFIG. 6is the identical or substantially identical to VOUTinFIG. 4. In each embodiment, the buffer output voltage (VOUT, VOUTA) exhibits significantly reduced kickback compared to the prior art (e.g.,FIG. 2). For example, at the sampling instants, when the sampling switches512turn off (i.e., close), the respective isolation inductors521,522isolates the subsequent voltage kickback from the input buffers501,502, respectively. As a result, the buffer output voltage (VOUTA, VOUTB) exhibits significantly reduced kickback compared to the prior art (e.g.,FIG. 2). Little additional power is now needed to fully settle the signal dependent fraction of the voltage kickback. Furthermore, employing the isolation inductors521,522increases the tracking bandwidth due to shunt peaking, which improves tracking linearity especially when the input frequency is near Nyquist frequency (i.e., 0.5 fs). Since the voltage kickback is at fairly high frequency (e.g., >3 fs), the isolation inductors can have a relatively small inductance value (e.g., ≤about 100 pH, as discussed above), which results in nominal increase in semiconductor die area.

FIG. 7is a schematic diagram of a TI circuit70according to an embodiment. TI circuit70is the same as TI circuit50except that TI circuit70illustrates that the first and second input buffers501,502are first and second source follower amplifiers701,702.

FIG. 8is a schematic diagram of a TI circuit80according to an embodiment. TI circuit80is the same as TI circuit50except that TI circuit80illustrates that the first and second input buffers501,502are first and second push-pull amplifiers801,802.

InFIGS. 7 and 8, the TI circuits70,80include a total of M T/H circuits510(i.e., an M-way TI circuit) where M is a positive even integer. Each group541,542preferably includes the same number of T/H circuits510(i.e., M/2).

Any of circuits30,50,70, and/or80can be formed on a single (e.g., monolithic) substrate and/or integrated in a single chip.

The invention should not be considered limited to the particular embodiments described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the invention may be applicable, will be apparent to those skilled in the art to which the invention is directed upon review of this disclosure. The claims are intended to cover such modifications and equivalents.