Daisy chain cascade configuration recognition technique

Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

BACKGROUND OF THE INVENTION

A typical computer-based system comprises a system board and optionally one or more peripheral devices, such as display units and disk units. The system board often contains one or more processors, a memory subsystem and other circuitry, such as serial device interfaces, network device controllers and hard disk controllers.

The type of processors that are employed on a particular system board usually depends on the type of tasks performed by the system. For example, a system that performs a limited set of tasks, such as monitor emissions generated by an automobile engine and adjust an air/fuel mixture to ensure the engine is burning fuel completely may employ a simple specialized processor that is tailored to performing these tasks. On the other hand, a system that performs many different tasks, such as managing many users and running many different applications, may employ one or more complex processors that are general purpose in nature, configured to perform high-speed calculations and manipulate data to minimize the response time to servicing the users' requests.

The memory subsystem is a storage that holds information (e.g., instructions, data values) used by the processors. The memory subsystem typically comprises controller circuitry and one or more memory devices. The controller circuitry is usually configured to interface the memory devices with the processors and enable the processors to store and retrieve information to and from the memory devices. The memory devices hold the actual information.

Like the processors, the type of devices employed in a memory subsystem is often driven by the type of tasks performed by the computer system. For example, a computer system may have the task of having to boot without the assistance of a disk drive and execute a set of software routines that do not change often. Here, the memory subsystem may employ non-volatile devices, such as Flash memory devices, to store the software routines. Other computer systems may execute very complex tasks that require a large high-speed data store to hold large portions of information. Here, the memory subsystem may employ high-speed high-density Dynamic Random Access Memory (DRAM) devices to store the information.

Demand for Flash memory devices has continued to grow significantly because these devices are well suited in various embedded applications that require non-volatile storage. For example, Flash is widely used in various consumer devices, such as digital cameras, cell phones, USB Flash drives and portable music players, to store data used by these devices. Market demand for Flash memory has led to tremendous improvements in Flash memory technology over the past several years both in terms of speed and density. These improvements have led to the prediction that Flash memory-based devices may one day replace hard disk drives in applications that continue to use disk drives for mass storage.

SUMMARY OF THE INVENTION

Some Flash devices employ serial interfaces that are used to perform operations, such as read, write and erase operations, on memory contained in the devices. These operations are typically selected on a device using command strings that are serially fed to the devices. The command strings typically contain a command that represents the operation to be selected as well as parameters. For example, a write operation may be selected by serially feeding an information string to the device that contains a write command, the data to be written and an address in the memory where the data is to be written.

Some memory subsystems employ multiple Flash devices with serial interfaces. Here, a plurality of devices may be configured in a parallel or multi-drop arrangement, wherein each device receives commands through a signal path connected to the controller. Alternatively, the devices may be configured in a daisy chain cascade arrangement, wherein signals are transmitted from each device to the successive device in the chain. Still other configurations may employ both multi-drop and serial configurations, where some signals are received in parallel and others are transmitted through a daisy chain cascade.

In a daisy chain cascade configuration, a command string may be fed to all of the devices even though the command may only be performed on one of the devices. A first device in the daisy chain cascade receives a command string from the controller. The command string is then transmitted to each successive device by the preceding device in the daisy chain cascade, until the command is received by all devices. Each device also responds to commands addressed to it, transmitting responsive data through the daisy chain cascade to the controller.

Memory devices utilized in a daisy chain cascade may require an indication of such a configuration. For example, a Flash memory device may be suitable for operation as a single device or as one of a plurality of memory devices in a daisy chain cascade or multi-drop configuration, or may be utilized interchangeably between multiple configurations. Because these configurations require different modes of operation, a memory device operating in a daisy chain cascade must recognize that it is so configured.

Embodiments of the present invention provide systems and methods of recognizing a daisy chain cascade configuration of devices. Input circuitry receives an input signal at a device, the input signal indicating device configuration following a power-up, reset or other event associated with the device. A signal generator generates an indicator such as a pulse in response to the operation, the indicator occurring while the input signal indicates device configuration. A storage mechanism such as a state latch register stores the state of the input signal in response to the received indicator, thereby storing a state indicating configuration of the respective device. As a result, an embodiment of the present invention recognizes whether the device is connected in a daisy chain cascade configuration and provides an indication that enables the device to operate according to the configuration.

Following this operation, further embodiments permit the input circuitry to receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment. For example, the input circuitry may receive control or chip select signals. The respective device may be a memory device configured in a plurality of memory devices, such as Flash memory devices connected serially in a daisy chain cascade.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1Ais a block diagram of an exemplary device configuration comprising a plurality of single port devices configured in a serial daisy chain cascade arrangement having inputs and outputs for various signals. The devices110a-eare memory devices, each of which contains a memory (not shown) such as Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, or Flash memory cells.

Each device110comprises a serial input (SI), serial output (SO), chip select (CS#), and clock input (CLK). The input SI is used to transfer information (e.g., command, address and data information) into the device110. The output SO is used to transfer information from the device110. Input CLK receives an external clock signal to the devices110a-dand the CS# input receives a chip select signal, which enables operations at all devices simultaneously.

The ports SI and SO are connected between devices110in the daisy chain cascade arrangement such that the output SO of a device110earlier in the daisy chain cascade is coupled to the SI of the next device110in the daisy chain cascade. For example, port SO of device110ais coupled to the SI of device110b. The CLK input of each device110is fed with a clock signal from, e.g., a memory controller (not shown). The clock signal is distributed to each device110via a common link. As will be described further below, CLK is used to, among other things, latch information input to the device110at various registers contained in the device110.

The CS# input of each device is a conventional chip select that selects the device. This input is coupled to a common link that enables a chip select signal to be asserted to all of the devices110concurrently and consequently selects all of the devices110a-esimultaneously. The CS# input and CLK inputs are coupled to separate links that distribute the CS# and CLK signals, respectively, to the devices110a-e, as described above.

Information transmitted to the devices110a-emay be latched at different times of the clock signal fed to the CLK input. For example, in a single data rate (SDR) implementation, information input to the device110at the SI may be latched at either the rising or falling edge of the CLK clock signal. Alternatively, in a double data rate (DDR) implementation, both the rising and falling edges of the CLK clock signal may be used to latch information input at the SI.

The configuration of the devices110a-einFIG. 1Aincludes both a serial daisy chain cascade (e.g., input SI and output SO) and conventional multi-drop connections (e.g., CLK and CS#). Thus, the configuration may be referred to as a hybrid of daisy chain cascade and multi-drop configurations, where the advantages of each may be realized. Alternatively, embodiments of the techniques described herein may be implemented in serial, parallel, multi-drop or other connections, and combinations thereof, between devices. Refer to U.S. patent application Ser. No. 11/496,278, titled “Daisy Chain Cascading Devices,” the entire teachings of which are incorporated by reference herein, for further information regarding communication and configuration of devices in a daisy chain cascade.

FIG. 1Bis a block diagram of a plurality of devices120a-cconfigured in parallel communication with a controller (not shown). Each device120a-cincludes a serial input (SI), serial output (SO), chip select (CS#), and clock input (CLK). The input SI is used to transfer information (e.g., command, address and data information) into the device120. The output SO is used to transfer information from the device120. Input CLK receives an external clock signal to the devices120a-cand the CS# input receives a chip select signal, which enables operations at each device independently of the other devices.

The devices120a-care configured in a parallel arrangement, utilizing multi-drop connections at the communication ports SI and SO for communication with a controller. Separate CS inputs at each device120a-callow the device to be enabled individually. Therefore, a controller connected to the devices120in a multi-drop arrangement may control each device120a-cby first transmitting to its corresponding CS input, and then sending and receiving data at the corresponding ports SI and SO. For example, a controller may communicate with device120aby first selecting it with a signal at input CSO. Once the device is enabled, the controller can send commands, data and other signals to the device120aat input SI0, and receive responsive communication from the device at output SO0.

The devices ofFIGS. 1A and 1Bare illustrated as comprising a serial input SI, serial output SO, clock input CLK and chip select CS. However, as described above, these ports may serve different functions in each configuration. Memory devices comprising memory such as DRAM cells or Flash cells may be implemented as such devices. In some embodiments, an implemented memory device may not be preconfigured for serial or multi-drop operation. For example, a Flash memory device may be suitable for operation in either of the configurations ofFIGS. 1A and 1B, and may be utilized interchangeably between these two or other configurations. Because each memory device must be configured for proper operation in a daisy chain cascade or multi-drop setting, the systems ofFIGS. 1A and 1Bmust indicate their respective configurations to their respective devices.

FIG. 2is a block diagram illustrating a technique for indicating device configuration. Here, devices210a-eare configured in a serial daisy chain cascade comparable to the configuration ofFIG. 1A. However, the inputs CS at all devices210are connected to ground, thereby maintaining a constant signal at the CS input at each device210a-e. Circuitry at each device210a-ereceives the CS input and determines whether the device is configured in a daisy chain cascade arrangement during a power-up sequence of the device. If the received CS input is maintained at ground as shown, the circuitry at each device210a-edetermines that the device is enabled and configured in a daisy chain cascade.

The technique described above indicates a daisy chain cascade configuration by connecting the chip select input at each device to ground. Alternative embodiments of the devices210a-ecan include other inputs that are configured in this manner to indicate a daisy chain cascade configuration. However, the configured input is maintained at ground, and therefore cannot be used in other operations. For example, the CS input at each device210a-ecould instead receive an enable signal from a controller for enabling operations at each device. Thus, this technique for indicating a daisy chain cascade configuration requires a dedicated input.

FIG. 3is a timing diagram illustrating signals of two exemplary devices during a power up sequence. Signal Vdd is a reference voltage signal providing power to the exemplary devices, and ramps up until it reaches a reference voltage at the beginning of time t. The signal310is a CS input of an exemplary device in a daisy chain cascaded connection, such as one of the devices110a-einFIG. 1A. The signal320is a CS input of an exemplary device in a parallel connection, such as one of the devices120a-cinFIG. 1B. During the time in which Vdd ramps up, both exemplary devices may receive undetermined signals at their respective CS inputs. However, during a time t in which Vdd has reached a reference voltage, the CS input at each device may receive a signal that corresponds to whether the device is configured in a daisy chain cascade or in parallel. Here, the CS signal310in a daisy chain cascaded connection is low during time t, while the CS signal320in a parallel connection is high. Time t may be a short interval, such as a span greater than 1 microsecond, that occurs between the power ramp-up and when the device receives communication signals from a controller. The CS signals310,320may be provided to the devices by a memory controller (not shown) that controls the devices. Such a memory controller may be configured to indicate, by the state of the CS signal310,320during time t, whether the devices it controls are connected in a daisy chain cascaded configuration, in parallel, or as a single device.

Following time t, the CS signal310,320at each device may no longer indicate device configuration, as the signal state may change as determined by a controller. Signals310and320are accompanied by respective state latch signals315and325. These accompanying signals315,325represent the state of respective latches that receive the state of each CS signal310,320. The respective latches latch the inverse state of the CS signals during time t, thereby storing the inverse state of the CS signals310,320at time t. As a result, the state latch signals315,325indicate whether the respective devices are connected in a daisy chain cascade or parallel (or single device) configuration. The devices may respond to the state latch signals315,325by operating according to the indicated configuration. For example, a device receiving the “high” state latch signal315(indicating a daisy chain cascaded connection) may be enabled at all times and transmit all commands and data through a serial output. Conversely, a device receiving a “low” state latch signal325(indicating a parallel or single device connection) may be enabled by the CS signal320. Because the state latch signals315,325indicate configuration, CS signals may be used following time t to select the devices or perform other functions.

FIG. 4is a block diagram of latching circuitry400that stores the state of received signal CS during a power up sequence of a device. The circuit may be internal to a device such as one of the devices110a-e,120a-cofFIG. 1, the device being a single device controlled by a controller or as one of a plurality of devices in a daisy chain cascade or parallel configuration. The circuit includes an input buffer410, power-up circuit420, pulse generator430and state latch register440.

Input buffer410receives a CS signal and outputs a corresponding signal “chip_select” to the state latch register440and an internal logic block that receives the CS signal. The power-up circuit420receives a reference voltage Vdd and outputs a signal “pwr_ok” that is high when Vdd is ramped up. The pulse generator430receives the signal “pwr_ok” and outputs a pulse in response to a transition of “pwr_ok” to high. The state latch register440(shown in the circuit400as well as inset below the circuit400) receives the pulse and the signal “chip select,” and stores the state of signal “chip select” by latching it while the pulse is received.

The pulse is provided as an indicator, and may be a signal of any duration that accommodates this latching operation. In the present embodiment, the pulse generator430generates a pulse signal “pwr_ok_ps” in response to the device completing a power ramp-up. For a time period following the power ramp-up, the CS signal indicates whether the device is configured in a daisy chain cascade arrangement, a parallel connection, or as a single device (e.g., CS being low indicates a daisy chain cascade, while CS being high indicates a parallel or single device connection). In order for the state latch register440to store the CS signal providing this indication, the pulse generator430must enable the state latch register440during the aforementioned time period.

FIG. 5is a timing diagram illustrating signals corresponding to the circuit400ofFIG. 4. The signals are shown during a power up sequence of the device receiving a reference voltage Vdd. The signal “pwr_ok” at line530is high when Vdd has reached a predetermined voltage. This time coincides with a time t in which the input signal CS550a-bindicates whether the device is in a daisy chain cascade or parallel configuration. Signal “chip_select”551a-bprovides a signal inverted from the CS signal550a-b. Thus, a pulse generator generates a pulse signal540during time t, enabling a state latch register to latch the state of the signal “chip_select”551a-bduring this time t, as shown by the signals “state latch”552a-b.

Signals550a-552acorrespond to a device in a daisy chain cascade arrangement, while signals550b-552bcorrespond to a device in a parallel connection. As a result of latching the respective “chip_select” signals551a-bwhile they indicate the device configuration, the signals552a-bmaintain a state indicating the configuration of the respective devices.

FIG. 6is a block diagram of an alternative embodiment of latching circuitry600for storing the state of the received CS signal. The circuit may be internal to a device such as one of the devices110a-e,120a-cofFIG. 1, the device being a single device controlled by a controller or as one of a plurality of devices in a daisy chain cascade or parallel configuration. The circuit includes an input buffers610,620, pulse generator630and state latch register640, the functions of which may be comparable to the corresponding components of the circuit400ofFIG. 4. Input buffer620receives a signal “reset,” which may be transmitted to the device to reset one or more configurations at the device. The pulse generator630generates a pulse in response to the signal “reset.” The state latch register640latches the state of the signal “chip select” during the pulse, thereby storing a state corresponding to the CS signal following a device reset operation.

FIG. 7is a timing diagram illustrating signals corresponding to the circuit600ofFIG. 6. The signals are shown during a power up sequence of the device receiving a reference voltage Vdd730. Following the power up sequence, the signal “reset” is asserted. During a time t following the assertion of the signal “reset,” CS signal750a-bindicates the device configuration. In particular, CS signal750ais low, indicating a daisy chain cascade connection; while CS signal750bis high, indicating a parallel connection. The CS signals750a-bare buffered, resulting in respective “chip_select” signals751a-b. During time t, the state of the “chip_select” signals751a-bare latched by a state latch, providing respective “state_latch” signals752a-bthat maintain the latched state beyond time t. Thus, the circuit600recognizes whether the device is connected in a daisy chain cascade configuration, stores a state indicating the device configuration, and permits a related input port to receive communications after the configuration is recognized.

FIG. 8is a block diagram of an exemplary device configuration comprising a plurality of single port devices configured in a serial daisy chain cascade arrangement having inputs and outputs for various signals. The devices810a-dare memory devices, each of which contains a memory (not shown) such as Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, or flash memory cells. The latching circuitry400,600inFIGS. 4 and 6may be incorporated into each of the devices810a-d. As such, the latching circuitry400,600may latch the state of the signal CS# when it indicates that the devices810a-dare configured in a daisy chain cascade.

Each device810comprises a serial input (SI), serial output (SO), chip select (CS#), and clock input (SCLK), described above with reference toFIG. 1A. In addition, each device810comprises an input port enable (IPE) input, output port enable (OPE) input, input port enable output (IPEQ) and output port enable output (OPEQ). The IPE input receives an IPE signal to the device. The IPE signal may indicate to the device to enable the SI such that when IPE is asserted information may be serially input to the device810via the SI. Likewise, the OPE input receives an OPE signal to the device. The OPE signal is used by the device to enable the SO such that when OPE is asserted information may be serially output from the device810via the SO. The IPEQ and OPEQ are outputs that output the IPE and OPE signals, respectively, from the device. The CS# input and SCLK inputs are coupled to separate links that distribute the CS# and SCLK signals, respectively, to the devices410a-d, as described above.

The SI and SO are coupled from one device to the next in a daisy chain cascade arrangement, as described above. Moreover, the IPEQ and OPEQ of an earlier device810in the daisy chain cascade are coupled to the IPE input and OPE input, respectively, of the next device410in the daisy chain cascade arrangement. This arrangement allows IPE and OPE signals to be transferred from one device to the next (e.g., device810ato device810b) in a serial daisy chain cascade fashion.

Information transmitted to the devices810a-dmay be latched at different times of the clock signal fed to the SCLK input. For example, in a single data rate (SDR) implementation, information input to the device810at the SI may be latched at either the rising or falling edge of the SCLK clock signal. Alternatively, in a double data rate (DDR) implementation, both the rising and falling edges of the SCLK clock signal may be used to latch information input at the SI.

FIG. 9is a block diagram of serial output control logic1100that may be incorporated into each of the devices810a-dofFIG. 8. Logic1100comprises an SI input buffer1104, an IPE input buffer1106, an OPE input buffer1108, an SCLK input buffer1110, logical AND gates1112and1114, latches1116,1118,1120and1122, selectors1124and1130, logical OR gate1126and an SO output buffer1128. Buffers1104,1106,1108and1110may be conventional LVTTL buffers configured to buffer SI, IPE, OPE and SCLK signals, respectively, that are inputted to the device.

The output control logic1100controls input and output signals according to the received control signals. As described above with reference toFIG. 1, a device connected in a daisy chain cascade arrangement (e.g. device110a) operates differently from a device connected in parallel (e.g., device120a) or as a single device. Therefore, the control logic1100receives a signal indicating whether the device is configured in a daisy chain cascade, signal CASCADE. Latching circuitry400,600may be incorporated into a device with serial control logic1100. If so, the signal State_latch signal output by the latching circuitry400,600would be received by the output control logic1100as the signal CASCADE, described below.

The buffered SI signal is received by AND gate1112, which sends the signal to latch1116when IPE is asserted. Latch1116is configured to latch the information when a clock signal (SCLK) is provided by buffer1110. DATA_OUT represents the state of data read from a memory (not shown) contained in the device. AND gate1114is configured to output a state of DATA_OUT when OPE is asserted. The output of AND gate1114feeds latch1118which is configured to latch the state of DATA_OUT when a clock signal is provided by buffer1110. Buffer1106is configured to buffer the IPE signal fed to the device. The output of buffer1106is latched by latch1120. Likewise, buffer1108is configured to buffer the OPE signal fed to the device. Latch1122is configured to latch the state of OPE as output by buffer1108. Selectors1124and1130are conventional 2-to-1 multiplexers each comprising two inputs. The inputs for selector1124are selected for output from the selector1124by the above-described ID_MATCH signal. One input is fed with the latched state of DATA_OUT as maintained by latch1118. This input is selected for output from selector1124when ID_MATCH is asserted. The other input is fed with the latched state of SI as maintained by latch1116. This input is selected for output from the selector1124when ID_MATCH is not asserted.

The signal CASCADE indicates whether the device is coupled to one or more other devices in a daisy chain cascade arrangement. Illustratively, this signal is asserted if the device is coupled to one or more devices in a daisy chain cascade arrangement. For example, the signal may be asserted by the state latch440,640of respective latching circuitry400,600when indicating that the device is configured in a daisy chain cascade. Asserting the CASCADE signal causes the latched state of the IPE signal fed to the selector1130to be output from the selector1130. When CASCADE is not asserted, the logic low condition input to the selector1130is output from the selector1130. The inputs for selector1130are selected for output from the selector1130by the CASCADE signal. One input to selector1130is fed with the latched state of IPE as maintained by latch1120and the other input is tied to a logical zero. The latched state of IPE is selected for output from the selector1130when CASCADE is asserted.

Conversely, if CASCADE is not asserted, logical zero is selected for output from the selector1130. The signal IPE therefore cannot be asserted to enable the serial output of the device. As a result, output buffer1128is enabled only by the OPE, thereby controlling the serial output as indicated by the output enable signal. This configuration is suitable where the device is not connected in a daisy chain cascade.

OR gate1126provides an enable/disable signal to output buffer1128. The gate1126receives the output of selector1130and the latched state of OPE, as maintained by latch1122. Either of these outputs may be used to provide an enable signal to buffer1128to enable the buffer's output. Buffer1128is a conventional buffer that buffers output signal SO. As noted above, buffer1128is enabled/disabled by the output of OR gate1126.

Operationally, when IPE is asserted, information that is input to the device via SI is fed to latch1116. Latch1116latches this information illustratively at the first upward transition of SCLK after IPE is asserted. Likewise, latch1120latches the state of IPE at this SCLK transition. Providing that ID_MATCH is not asserted (indicating that a command is not addressed to the device), the output of latch1116is fed to buffer1128via selector1124. Likewise, the asserted IPE is transferred from buffer1106to latch1120where it is also illustratively latched by the first upward transition of SCLK. Assuming CASCADE is asserted, the latched state of IPE is provided at the output of selector1130and transferred to OR gate1126to provide an enable signal to buffer1128. The latched state of SI is then transferred from the device via buffer1128as output SO.

Illustratively, at the next upward transition of SCLK after OPE is asserted, the asserted state of OPE is latched at latch1122and the state of DATA_OUT is latched at latch1118. Providing that ID_MATCH is asserted, the latched state of DATA_OUT is selected by selector1124and applied to the input of buffer1128. Simultaneously, the latched asserted state of OPE from latch1122passes through OR gate1126to enable buffer1128which causes the latched state of DATA_OUT to be output from the device as output SO.