Method of forming features with various dimensions

A method of fabricating a semiconductor device is disclosed. The method includes forming mandrels over a material layer and forming spacers along sidewalls of mandrels, forming a patterned hard mask to cover a first region, depositing a filling layer in a second region while the patterned hard mask covers the first region. A space between two adjacent spacers in the second region is filled in by the filling layer. The method also includes recessing the filling layer to form a filling block in the space between two adjacent spacers in the second region, removing the patterned hard mask, removing mandrels and etching the material layer by using spacers and the filling block as an etch mask to form material features in the first region and the second region, respectively.

BACKGROUND

This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. Although existing methods of fabricating IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, improvements in forming smaller critical dimension features with various dimensions are desired.

DETAILED DESCRIPTION

FIG. 1is a flowchart of a method100of fabricating one or more semiconductor devices in accordance with some embodiments. The method100is discussed in detail below, with reference to a semiconductor device200, shown inFIGS. 2, 3, 4, 5, 6A, 6B, 7, 8, 9 and 10.

Referring toFIGS. 1 and 2, the method100begins at step102by forming a material layer220over a substrate210. The substrate210includes silicon. The material layer220may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a conductive material such as polysilicon, and/or other suitable materials. The material layer220may be deposited by thermal oxidation chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, or other suitable techniques.

Alternatively or additionally, the substrate210may include other elementary semiconductor such as germanium. The substrate210may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate210may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate210includes an epitaxial layer. For example, the substrate210may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate210may include a semiconductor-on-insulator (SOI) structure. For example, the substrate210may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

The substrate210may also include various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, light doped region (LDD) and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED). The substrate210may further include other functional features such as a resistor or a capacitor formed in and on the substrate.

The substrate210may also include various isolation features. The isolation features separate various device regions in the substrate210. The isolation features include different structures formed by using different processing technologies. For example, the isolation features may include shallow trench isolation (STI) features. The formation of a STI may include etching a trench in the substrate210and filling in the trench with insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench. A chemical mechanical polishing (CMP) may be performed to polish back excessive insulator materials and planarize the top surface of the isolation features.

The substrate210may also include gate stacks formed by dielectric layers and electrode layers. The dielectric layers may include an interfacial layer (IL) and a high-k (HK) dielectric layer deposited by suitable techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, or other suitable techniques. The IL may include oxide, HfSiO and oxynitride and the HK dielectric layer may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), and/or other suitable materials. The electrode layer may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide). The MG electrode420may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, any suitable materials or a combination thereof.

The substrate210may also include a plurality of inter-level dielectric (ILD) layers and conductive features integrated to form an interconnect structure configured to couple the various p-type and n-type doped regions and the other functional features (such as gate electrodes), resulting a functional integrated circuit. In one example, the substrate210may include a portion of the interconnect structure and the interconnect structure includes a multi-layer interconnect (MLI) structure and an ILD layer integrated with a MLI structure, providing an electrical routing to couple various devices in the substrate210to the input/output power and signals. The interconnect structure includes various metal lines, contacts and via features (or via plugs). The metal lines provide horizontal electrical routing. The contacts provide vertical connection between silicon substrate and metal lines while via features provide vertical connection between metal lines in different metal layers.

Referring again toFIGS. 1 and 2, the method100proceeds to step104by forming a plurality of hard mask features310over the material layer220. In some embodiments, the hard mask features310are dummy features and will be removed at a later fabrication stage. The hard mask features310are also referred to as mandrels310. A layout of the mandrels310may have various configurations. For example, the layout of the mandrels310has a non-periodic structure, in which mandrel310has various width from one mandrel310to another mandrel310and various space between two adjacent mandrels310.

In the present embodiment, the substrate210includes a first region302and a second region304. Features formed in the first region302have different dimensions than those features formed in the second region304. For example, features having a smaller pitch (e.g. for a high performance logic transistor) will be formed in the first region302while features having a larger pitch (e.g. for an I/O transistor) will be formed in the second region304. The mandrels310are oriented in the Y direction and are spaced apart from one another along the X direction which is perpendicular to the Y direction. In the present embodiment, mandrels310define various openings such that the material layer220is exposed within the openings.

The mandrel310has a first width W1, which may be a constant or alternatively be a variable that changes from one mandrel310to another mandrel310. In the first region302, two adjacent mandrels310are spaced from each other by a first distance D1. While in the second region304, two adjacent mandrels310are spaced away from each other by a second distance D2, which is different than the first distance D1. In an embodiment, the second distance D2is greater than the first distance D1. Thus, a first pitch P1in the first region302is collectively determined by a sum of the first width W1and the first distance D1. Likewise, a second pitch P2in the second region302is collectively determined by a sum of the first width W1and the second distance D2. Accordingly, second pitch P2is greater than first pitch P1.

The mandrels310may be formed by a procedure including deposition, patterning, etching, and/or a combination thereof. In some embodiments, the formation of the mandrels310may include depositing a mandrel material layer; forming a resist pattern; and etching the mandrel material layer using the resist layer as an etch mask, thereby forming the mandrel310. The mandrel material layer may include silicon oxide, silicon nitride, oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, and/or any suitable materials. In the present embodiment, the mandrel material layer includes a material which is different from the material layer220to achieve etching selectivity in subsequent etches. The mandrel material layer may include multiple layers. The mandrel material layer may be deposited by a suitable technique, such as CVD, PVD, ALD, spin-on coating, and/or other suitable technique. The resist pattern includes a resist material sensitive to a radiation beam and is formed by a lithography process. In one example, the lithography process includes coating a resist layer on the mandrel material layer, performing a lithography exposure process to the resist layer according to the IC layout and developing the exposed resist layer to form the resist pattern. The etching process includes a wet etch, a dry etch, and/or a combination there.

Referring toFIGS. 1 and 3, the method100proceeds to step106by forming spacers410along sidewalls of the mandrels310in both the first region302and the second region304. The spacers410may be formed by depositing a spacer material layer over the mandrels310, and followed by a spacer etch to etch the spacer material layer anisotropically. The spacer material layer may include silicon oxide, silicon nitride, oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, and/or any suitable materials. In the present embodiment, the spacer material layer includes a material which is different from the mandrels310and the material layer220to achieve etch selectivity in a subsequent etch. The spacer layer may be deposited by CVD, ALD, PVD, or other suitable techniques. In one embodiment, the spacer material layer is deposited by ALD to achieve conformable film coverage along the sidewalls of the mandrels310. The thickness of the spacer material layer is referred to as a second width W2. In some embodiments, the spacer material layer is etched by an anisotropic etch to form a vertical profile. The anisotropic etch may include a plasma etch in one example

The spacers410are oriented in the Y direction and spaced from each other in the X direction. In the present embodiment, a first space (or opening)420is formed between two adjacent spacers410in the first region302and has a third distance D3, which is equal to (D1−2 W2). While a second space (or opening)440is formed between two adjacent spacers410in the second region304and has a fourth distance D4, which is equal to (D2−2 W2). In an embodiment, by choosing the first distance D1and the second width W2, the third distance D3is designed to be equal to the first width W1.

Referring toFIGS. 1 and 4, the method100proceeds to step108by forming a patterned hard mask (HM)510to cover the first region302while leaving the second region304uncovered (or exposed). In some embodiments, the patterned HM510may include a patterned photoresist layer formed by a lithography process. An exemplary lithography process may include forming a photoresist layer, exposing the photoresist layer by a lithography exposure process, performing a post-exposure bake process, and developing the photoresist layer to form the patterned resist layer.

Alternatively, the patterned HM510may be formed by depositing a HM layer, forming a patterned photoresist layer over the HM layer by a lithography process and etching the HM layer through the patterned photoresist layer to form the patterned HM510. The patterned HM510layer may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, combinations thereof, and/or other suitable materials. In the present embodiment, the patterned HM510includes a material which is different from the material layer220, the mandrels310and the spacers410to achieve etching selectivity in subsequent etches. The HM layer may be deposited by CVD, ALD, PVD, thermal oxidation, spin-on coating, combinations thereof, and/or other suitable techniques.

Referring toFIGS. 1 and 5, the method100proceeds to step110by depositing a filling layer610in the second region304such that the second space440is filled in by the filling layer610. Also, as shown, filling layer610is deposited over patterned HM510is the first region302. The filling layer610may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, silicon carbide, and/or other suitable materials. The filling layer610may be deposited by CVD, ALD, PVD, thermal oxidation, spin-on coating, combinations thereof, and/or other suitable techniques. In the present embodiment, the filling layer610includes a material which is different from the material layer220and the patterned HM510to achieve etching selectivity in subsequent etches.

Referring toFIGS. 1, 6A and 6B, the method100proceeds to step112by recessing the filling layer610to expose top surfaces of the mandrels310in the second region304and the patterned HM510in the first region302. In the present embodiment, the remaining filling layer610within the second space440forms a filling block615. The etch process may include a wet etch, a dry etch, and/or a combination thereof. As an example, a wet etching solution may include HNO3, NH4OH, KOH, HF, HCl, NaOH, H3PO4, TMAH, and/or other suitable wet etching solutions, and/or combinations thereof. Alternatively, a dry etching process may implement chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr and/or CHBr3), iodine-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), and/or other suitable gases and/or plasmas, and/or combinations thereof. In some embodiments, as has been mentioned previously, the etch process is chosen to selectively etch the filling layer610without substantially etching the patterned HM510. The filling layer610is etched back in the second region304while the filling layer610overlying the patterned hard mask510is selectively removed, as shown inFIG. 6A.

Alternatively, in some embodiments, a non-selective etching back is performed such as using a chemical mechanical polishing (CMP) to removing excessive the filling layer610and the excessive patterned HM510, as shown inFIG. 6B. A depth of etching back is controlled such that top surfaces of the mandrels310are exposed in both the first and second regions,302and304, and the second space440remains filled by the filling layer610to form the filling block615.

Referring toFIGS. 1 and 7, the method100proceeds to step114by removing the patterned HM510from the first region302. The etch process may include a wet etch, a dry etch, and/or a combination thereof. As an example, a wet etching solution may include HNO3, NH4OH, KOH, HF, HCl, NaOH, H3PO4, TMAH, and/or other suitable wet etching solutions, and/or combinations thereof. Alternatively, a dry etching process may implement chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr and/or CHBr3), iodine-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), and/or other suitable gases and/or plasmas, and/or combinations thereof. As has been mentioned previously, the etch process is chosen to selectively etch the patterned HM510without substantially etching the substrate210, the mandrels310, the spacers410and the filling block615. The selective etch may include a selective wet etch, a selective dry etch, and/or a combination thereof. As a result, the first space420is revealed in the first region302while the second space440remains filled by the filling block615.

Referring toFIGS. 1 and 8, the method100proceeds to step116by removing exposed mandrels310in both of the first and second regions,302and304. The etch process may include a wet etch, a dry etch, and/or a combination thereof. As an example, a wet etching solution may include HNO3, NH4OH, KOH, HF, HCl, NaOH, H3PO4, TMAH, and/or other suitable wet etching solutions, and/or combinations thereof. Alternatively, a dry etching process may implement chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr and/or CHBr3), iodine-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), and/or other suitable gases and/or plasmas, and/or combinations thereof. In some embodiments, the mandrels310are removed by a selective etch without substantially etching the material layer220, the spacers410and the filling block615. The selective etch may include a selective wet etch, a selective dry etch, and/or a combination thereof.

As a result, adjacent spacers410in the first region302are spaced apart from each other by either the first width W1or by the third distance D3(as discussed above with respect toFIGS. 2 and 3). A third pitch P3is therefore collectively determined by a sum of the first width W1and the second width W2. Likewise, a fourth pitch P4is therefore collectively determined by a sum of the second width W2and the third distance D3. In an embodiment, the third distance D3is chosen to be same as the second width W2, thus the third pitch P3is the same as the fourth pitch P4to form a periodic (regular) pattern with a pitch being equal to (W1+W2).

As can been seen, the disclosed process reduces the pitch size in the first region302. That is, the mandrel features originally formed in the first region310had a first pitch P1(W1+D1as shown inFIG. 2) and now the later formed spacers410have either the third pitch P3(W1+W2), or the fourth pitch P4(W2+D3) both of which are smaller than the first pitch P1. It is noted that the second width W2is the width of the spacer410and is defined by spacer deposition thickness, which can be controlled precisely by deposition process condition, such as deposition time. Thus, the first pitch P1is not only reduced to the third pitch P3(or the fourth pitch P4) but also the third pitch P3(or the fourth pitch P4) inherits good width control. In other words, a smaller pitch (the third pitch P3or the fourth pitch P4) is achieved by a procedure that has more relaxed constraints as compared to a traditional lithography process to form smaller pitches.

As discussed above, step116of method100also includes removing the exposed mandrels310in the second region304. This removal of mandrel features from the second region304can occur during the same process used to remove the exposed mandrel features in the first region302. In alternative embodiments, the removal of the exposed mandrel features in the second region304occurs before or after the removal of the exposed mandrel features in the first region302. The removal of the mandrel features in the second regions results in the formation of a block feature710being formed. Block feature710includes the filling block615and the spacers410along its sidewalls. The block feature710carries the second distance D2(as discussed above with respect toFIGS. 2 and 3).

Referring toFIGS. 1 and 9, the method100proceeds to step118by etching the material layer220by using the spacers410and the block feature710as an etch mask. As a result, in the first region302, the spacers410are transferred to first material features810in the material layer220while in meantime, in the second region304, the block feature710is transferred to a second material feature820in the material layer220. In some embodiments, the etch process may include an anisotropic etch, such as a plasma anisotropic etch. Accordingly, the first and second material features,810and820, are formed with vertical profiles. Thus, in the first region302, the first material feature810carries the second width W2and the third pitch P3, or the fourth pitch P4. While in the second region, the second material feature820carries the second distance D2. After forming the first and second material features,810and820, the spacers410and the filling block710are removed by a proper etch process, as shown inFIG. 10.

It is noted that, in the first region302, the width of the first material feature810and the pitch of the first material feature810are defined by the first width W1(of the mandrel310inFIG. 2), the first distance D1(as shown inFIG. 2) and the second width W2(of the spacer410inFIG. 3). In the second region304, the width of the second material feature820is defined by the second distance D2. Therefore, by choosing various combinations of these parameters (e.g. W1, D1, W2and D2), various widths of material features in various regions of the device200are achieved with a great degree of flexibility in comparison to traditional methodologies.

Additional steps can be provided before, during, and after the method100or1000, and some of the steps described can be replaced or eliminated for other embodiments of the method.

Based on the above, the present disclosure offers methods for forming various feature size in a device. The method employs forming a patterned hard mask to define regions in the device and then depositing a filling layer to fill in a space or spaces in designated region/regions. The method also employs using the filling layer in the space or spaces as an additional etch mask to form a feature in the designated region, which has a different size comparing a feature formed without the filling layer as an additional etch mask. The method provides flexibility and feasibility in forming features with various sizes in the device.

The present disclosure provides many different embodiments of fabricating a semiconductor device that provide one or more improvements over existing approaches. In one embodiment, a method for fabricating a semiconductor device includes forming a first, a second, a third and a fourth mandrel over a material layer. The first and the second mandrels are formed over a first region of the material layer and space away by a first distance D1and the third and the fourth mandrels are formed over a second region of the material layer and space away by a second distance D2. The method also includes forming spacers along sidewalls of the first, second, third and fourth mandrels, forming a patterned hard mask to cover the first region, depositing a filling layer in the second region while the patterned hard mask covers the first region. A space between two adjacent spacers in the second region is filled in by the filling layer. The method also includes recessing the filling layer to form a filling block in the space between two adjacent spacers in the second region, removing the patterned hard mask, removing the first, second, third and fourth mandrels and etching the material layer by using spacers and the filling block as an etch mask to form material features in the first region and the second region, respectively.

In another embodiment, a method includes forming a material layer over a substrate, the substrate having a first region and a second region, forming a first pair of mandrels over the material layer in the first region and a second pair of mandrel over the material in the second region and forming spacers along sidewalls of the first and second pairs of mandrels. After forming the spacers along the sidewall of the first and second pairs of mandrels, the first pair of mandrels is separated away from each other by a first space and the second pair of mandrel is separated away from each other by a second space. The method also includes filling in the second space in the second region with a filling layer while the first space in the first region is un-filled, removing the first pair of mandrels in the first region and the second pair of mandrels in the second region and etching the material layer by using spacers and the filling layer as an etch mask to form a first material feature in the first region and a second material feature in the second region.

In yet another embodiment, a method includes forming a first mandrel and a second mandrel over a material layer. The first mandrel has a first sidewall facing a second sidewall of the second mandrel. The method also includes forming a first spacer along the first sidewall and a second spacer along the second sidewall such that a space exists between the first and second spacer, filling in the space with a filling layer, recessing the filling layer to expose top surfaces of the first and second mandrels, removing the first and second mandrels while the space is filled by the filling layer and etching the material layer by using spacers and the filling layer within the space as an etch mask to form a material feature.