Low-cost, capacitive-coupled level shifter scalable for high-voltage applications

A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit.

TECHNICAL FIELD

The present invention relates in general to a level shifter which is operable to, by way of capacitive coupling, level-shift a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential.

BACKGROUND ART

A typical level shifter is designed for level-shifting a low-voltage logic level to another low-voltage logic level, such as from a transistor-transistor logic (TTL) logic level to a complementary metal-oxide-semiconductor (CMOS) logic level, and/or vice versa; and frequently, both the digital input signal and the digital output signal are referenced to an identical ground potential. In contrast, there are some applications wherein a level shifter is required to level-shift a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential which may be either substantially higher or substantially lower than the input ground potential, and the following are several prior-art methods for designing level shifters for these applications.

One of the methods is based on pull-up resistors: the advantages include reasonably low cost; the disadvantages include dependence of ground-potential differential on transistor voltage ratings, more substantial propagation delays as ground-potential differential increases, a large mismatch of propagation delays among a plurality of level-shifter channels with varying ground-potential differentials, significant power consumption, intolerance of substantial slew rate of output ground potential relative to input ground potential, and a low signal frequency bandwidth.

Another one of the methods is based on optocouplers: the advantages include reasonably low cost, being scalable to high-voltage level-shifting, tolerance of high slew rate of output ground potential relative to input ground potential, and a reasonably wide signal frequency bandwidth; the disadvantages include relatively significant propagation delays, and subsequently a substantial mismatch of propagation delays among a plurality of level-shifter channels, and significant power consumption.

Still another one of the methods is based on digital isolators: the advantages include being scalable to high-voltage level-shifting, tolerance of high slew rate of output ground potential relative to input ground potential, reasonably short propagation delays, a reasonably good match of propagation delays among a plurality of level-shifter channels, and a reasonably wide signal frequency bandwidth; the disadvantages include high complexity and high cost, and significant power consumption.

Still another one of the methods is based on pulse transformers: the advantages include being scalable to high-voltage level-shifting, tolerance of substantial slew rate of output ground potential relative to input ground potential, and reasonably short propagation delays; the disadvantages include high cost, substantial size and weight, substantial power consumption, and a narrow signal frequency bandwidth.

Still another one of the methods is based on bootstrap high-side gate drivers: the advantages include being scalable to high-voltage level-shifting of up to hundreds of volts, tolerance of high slew rate of output ground potential relative to input ground potential, and a reasonable signal frequency bandwidth; the disadvantages include high complexity and high cost, significant propagation delays, a requirement of output ground potential being higher than input ground potential, significant power consumption, limited output voltage range, and a significant mismatch of propagation delays among a plurality of level-shifter channels.

SUMMARY OF INVENTION

Technical Problem

For a typical level shifter application, the voltage differential between the output ground potential and the input ground potential is nominally direct-current (DC). However, because of time-varying load current requirements, the output ground potential may change quickly relative to the input ground potential, thereby creating voltage transients on the output ground potential that may subsequently interfere with a signal being level-shifted. As the voltage differential increases, the output ground potential may change more quickly relative to the input ground potential. A slew rate describes the maximum rate of voltage change per unit of time. Therefore, it is imperative for a level shifter to tolerate a certain slew rate of the output ground potential relative to the input ground potential.

There are some applications that require a level shifter to possess the following features: being scalable to work with a large voltage differential between the output ground potential and the input ground potential; an ability to tolerate a substantial slew rate of the output ground potential relative to the input ground potential; a short propagation delay; an excellent match of propagation delays among a plurality of level-shifter channels; and a wide signal frequency bandwidth. And it is highly desirable if the level shifter also consumes low power and is low cost. As an example, one such application is in a battery management system (BMS), especially in active-balancing a long series-connected battery pack (a long series-connected supercapacitor pack is another good example of an application). A cell positive-terminal voltage relative to a BMS ground potential may vary from a few volts for a bottom cell in the battery pack to hundreds of volts or even over 1,000 volts for a top cell in the battery pack. A power switch driver is ground-referenced to each cell positive-terminal, and it is controlled by a controller referenced to the BMS ground potential via a level shifter. Therefore, the level shifter is required to level-shift a controller signal referenced to the BMS ground potential to a power-switch driver signal referenced to a cell positive-terminal voltage which is scalable from a few volts to possibly over 1,000 volts. When the battery pack is discharging or being charged, there may be a substantial slew rate to a cell positive-terminal voltage relative to the BMS ground potential. And for the controller to control a plurality of power switch drivers simultaneously, there must be an excellent match of propagation delays among a corresponding plurality of level-shifter channels; and the controller signals may have a wide frequency bandwidth. And it is highly desirable to use low-power and low-cost level shifters, because the number of level shifters required is equal to the number of battery cells.

None of the known prior-art level shifters for high-voltage applications possesses all of the aforementioned features.

Solution to Problem

In a first embodiment of the invention, a level shifter for level-shifting a digital input signal referenced to an input ground potential GNDINto a digital output signal referenced to an output ground potential GNDOUT, wherein GNDOUTis higher than or equal to or lower than GNDIN, comprising: a driver circuit including an input node and an output node, powered by an input power supply VINreferenced to GNDIN, and configured as inverting or non-inverting, and wherein the input node is coupled to the digital input signal, and wherein the output node toggles when the digital input signal toggles; a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled to the output node of the driver circuit, and wherein the second terminal toggles in sync with the toggling of the output node of the driver circuit; a first resistor including a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the second terminal of the capacitor; a receiver circuit including a first input node and an output node, powered by an output power supply VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the second terminal of the capacitor, and wherein the output node is coupled to the digital output signal, and wherein the digital output signal toggles when the second terminal of the capacitor toggles; and a latching feedback circuit including a first input node and an output node, powered by VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the output node of the receiver circuit, and wherein the output node is coupled to the second terminal of the resistor, and wherein the sum of the output resistance of the latching feedback circuit and the resistance of the first resistor is substantially larger than the output resistance of the driver circuit, and configured as non-inverting if the receiver circuit is non-inverting, or configured as inverting if the receiver circuit is inverting, thereby providing a positive feedback loop to latch a toggled signal from the second terminal of the capacitor to the receiver circuit.

The capacitor essentially serves as a toggling capacitor. In one embodiment, the capacitance of the capacitor is adapted to be substantially larger than the input capacitance of the first input node of the receiver circuit. In one embodiment, the receiver circuit may include a second input node for initializing or enabling the receiver circuit, and may further comprise an AND gate or a NAND gate or an OR gate or a NOR gate. In one embodiment, the latching feedback circuit also may include a second input node for initializing or enabling the latching feedback circuit, and may further comprise an AND gate or a NAND gate or an OR gate or a NOR gate. Before the level shifter functions properly, the first input node of the receiver circuit and the output node of the driver circuit are synchronized to be at an initial logic level. In one embodiment, both the output node of the driver circuit and the output node of the latching feedback circuit are preferably adapted to be field-effect-transistor (FET) complimentary output nodes.

The slew rate of GNDOUTrelative to GNDINfor the level shifter is primarily determined by the capacitance of the capacitor, and by the combined output resistance of the driver circuit and the latching feedback circuit and some additional current-limiting resistor(s).

To protect the level shifter in high-voltage applications, in one embodiment, one or more zener diodes are respectively coupled across related power supplies of the level shifter. And to protect the first input node of the receiver circuit and the output node of the latching feedback circuit and the output node of the driver circuit against any excessive voltage and/or current stress, in various embodiments, clamping diodes and/or current-limiting resistors are added to the level shifter.

In a second embodiment of the invention, a level shifter for level-shifting a digital input signal referenced to an input ground potential GNDINto a digital output signal referenced to an output ground potential GNDOUT, wherein GNDOUTis higher than or equal to or lower than GNDIN, comprising: a driver circuit including an input node and an output node, powered by an input power supply VINreferenced to GNDIN, and configured as inverting or non-inverting, and wherein the input node is coupled to the digital input signal, and wherein the output node toggles when the digital input signal toggles; a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled to the output node of the driver circuit, and wherein the second terminal toggles in sync with the toggling of the output node of the driver circuit; a receiver circuit including a first input node and an output node, powered by an output power supply VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the second terminal of the capacitor, and wherein the output node is coupled to the digital output signal, and wherein the digital output signal toggles when the second terminal of the capacitor toggles; and a latching feedback circuit including a first input node and an output node, powered by VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the output node of the receiver circuit, and wherein the output node is coupled to the second terminal of the capacitor, and wherein the output resistance of the latching feedback circuit is substantially larger than the output resistance of the driver circuit, and configured as non-inverting if the receiver circuit is non-inverting, or configured as inverting if the receiver circuit is inverting, thereby providing a positive feedback loop to latch a toggled signal from the second terminal of the capacitor to the receiver circuit.

In a third embodiment of the invention, a level shifter for level-shifting a digital input signal referenced to an input ground potential GNDINto a digital output signal referenced to an output ground potential GNDOUT, wherein GNDOUTis higher than or equal to or lower than GNDIN, comprising: a driver circuit including an input node and an output node, powered by an input power supply VINreferenced to GNDIN, and configured as inverting or non-inverting, and wherein the input node is coupled to the digital input signal, and wherein the output node toggles when the digital input signal toggles; a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled to the output node of the driver circuit, and wherein the second terminal toggles in sync with the toggling of the output node of the driver circuit; a first resistor including a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the second terminal of the capacitor; a non-inverting receiver circuit including a first input node and an output node, powered by an output power supply VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the second terminal of the capacitor, and wherein the output node is coupled both to the digital output signal and to the second terminal of the first resistor, and wherein the sum of the output resistance of the non-inverting receiver circuit and the resistance of the first resistor is substantially larger than the output resistance of the driver circuit, and wherein the digital output signal toggles when the second terminal of the capacitor toggles, and wherein the output node provides a positive feedback loop to latch a toggled signal from the second terminal of the capacitor to the non-inverting receiver circuit.

Advantageous Effects of Invention

It is an advantageous effect of the invention to achieve a level shifter which is scalable to a large voltage differential between the output ground potential and the input ground potential. This scalability is essentially limited only by the voltage rating of the toggling capacitor.

Another advantageous effect of the invention is the tolerance of a substantial slew rate of the output ground potential relative to the input ground potential. A substantial slew rate is critical in some real-world level-shifter applications.

Still another advantageous effect of the invention is the intrinsically short propagation delay of the level shifter. The short propagation delay results from the substantially instantaneous toggling of the capacitor in transmitting a signal from the output node of the driver circuit to the first input node of the receiver circuit.

Still another advantageous effect of the invention is the intrinsically excellent match of propagation delays among a plurality of level shifter channels. The is achieved by charging up a plurality of respective toggling capacitors for the plurality of level shifters to respective output ground potentials, thereby essentially eliminating the effect of ground-potential differences on the propagation delays.

Still another advantageous effect of the invention is low power consumption if the input capacitance and the input current of the first input node of the receiver circuit are minimized—which is the case for almost any CMOS or other equivalent input gate circuit. Any general-purpose input-output (I/O) with a FET complementary output node is able to drive the toggling capacitor with minimal power consumption.

Still another major advantageous effect of the invention is low cost. This is because only a capacitor (which may be rated for a high voltage if necessary) with a small capacitance is required if the input capacitance and the input current of the first input node of the receiver circuit are minimized, and because all other circuits and components of the level shifter are simple and low cost. This cost advantage may be very beneficial to successful commercialization of the invention.

Other advantages and benefits of the invention will become readily apparent upon further review of the following drawings.

MODES FOR CARRYING OUT THE INVENTION

In a first embodiment of the invention, as illustrated inFIG. 1, a level shifter100for level-shifting a digital input signal (at node150) referenced to an input ground potential GNDINto a digital output signal (at node154) referenced to an output ground potential GNDOUT, wherein GNDOUTis higher than or equal to or lower than GNDIN, comprising: a driver circuit110including an input node (at node150) and an output node (at node151), powered by an input power supply VINreferenced to GNDIN, and configured as inverting or non-inverting (depending on the requirement(s) of a specific embodiment), and wherein the input node is coupled to the digital input signal, and wherein the output node toggles when the digital input signal toggles; a capacitor101including a first terminal (at node151) and a second terminal (at node152), wherein the first terminal is coupled to the output node of the driver circuit110, and wherein the second terminal toggles in sync with the toggling of the output node of the driver circuit110; a first resistor102including a first terminal (at node152) and a second terminal (at node156), wherein the first terminal of the first resistor102is coupled to the second terminal of the capacitor101; a receiver circuit120including a first input node (coupled to node152) and an output node (at node154), powered by an output power supply VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the second terminal of the capacitor101, and wherein the output node is coupled to the digital output signal, and wherein the digital output signal toggles when the second terminal of the capacitor101toggles; and a latching feedback circuit130including a first input node (at node154) and an output node (at node156), powered by VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the output node of the receiver circuit120, and wherein the output node is coupled to the second terminal of the resistor102, and wherein the sum of the output resistance ROUT_130of the latching feedback circuit130and the resistance of the first resistor102is substantially larger than the output resistance ROUT_110of the driver circuit110, and configured as non-inverting if the receiver circuit120is non-inverting, or configured as inverting if the receiver circuit120is inverting, thereby providing a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. In one embodiment, the receiver circuit120may further include an optional second input node153for initializing or enabling the receiver circuit120. In one embodiment, the latching feedback circuit130may further include an optional second input node155for initializing or enabling the latching feedback circuit130. A few exemplary embodiments of the driver circuit110, the receiver circuit120and the latching feedback circuit130are disclosed as follows.

FIG. 2illustrates some exemplary embodiments of the driver circuit110, the receiver circuit120and the latching feedback circuit130. The driver circuit110further comprises a non-inverting buffer111A including: an input terminal and an output terminal, coupled respectively to the input node and the output node of the driver circuit110. The receiver circuit120further comprises an AND gate121A including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node153and the output node of the receiver circuit120. The latching feedback circuit130further comprises a non-inverting buffer131A including: an input terminal and an output terminal, coupled respectively to the first input node and the output node of the latching feedback circuit130. Both the AND gate121A and the buffer131A are non-inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node153is at logic low, the output of the AND gate121A is forced to be at logic low; then the output of the non-inverting buffer131A is also at logic low thereby initializing the first input node of the receiver circuit120to be at logic low. And when the second input node153is at logic high, the AND gate121A is enabled to function as a non-inverting buffer.

FIG. 3illustrates more exemplary embodiments of the driver circuit110, the receiver circuit120and the latching feedback circuit130. The driver circuit110further comprises an inverting buffer111B including: an input terminal and an output terminal, coupled respectively to the input node and the output node of the driver circuit110. The receiver circuit120further comprises a NAND gate121B including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node153and the output node of the receiver circuit120. The latching feedback circuit130further comprises an inverting buffer131B including: an input terminal and an output terminal, coupled respectively to the first input node and the output node of the latching feedback circuit130. Both the NAND gate121B and the buffer131B are inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node153is at logic low, the output of the NAND gate121B is forced to be at logic high; then the output of the inverting buffer131B is at logic low thereby initializing the first input node of the receiver circuit120to be at logic low. And when the second input node153is at logic high, the NAND gate121B is enabled to function as an inverting buffer.

FIG. 4illustrates still more exemplary embodiment of the receiver circuit120. The receiver circuit120further comprises a NOR gate121C including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node153and the output node of the receiver circuit120. Both the NOR gate121C and the buffer131B are inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node153is at logic high, the output of the NOR gate121C is forced to be at logic low; then the output of the inverting buffer131B is at logic high thereby initializing the first input node of the receiver circuit120to be at logic high. And when the second input node153is at logic low, the NOR gate121C is enabled to function as an inverting buffer.

FIG. 5illustrates still more exemplary embodiment of the receiver circuit120. The receiver circuit120further comprises an OR gate1210including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node153and the output node of the receiver circuit120. Both the OR gate1210and the buffer131A are non-inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node153is at logic high, the output of the OR gate1210is forced to be at logic high; then the output of the non-inverting buffer131A is at logic high thereby initializing the first input node of the receiver circuit120to be at logic high. And when the second input node153is at logic low, the OR gate1210is enabled to function as a non-inverting buffer.

FIG. 6illustrates still more exemplary embodiments of the receiver circuit120and the latching feedback circuit130. The receiver circuit120further comprises a non-inverting buffer121E including: an input terminal and an output terminal, coupled respectively to the first input node and the output node of the receiver circuit120. The latching feedback circuit130further comprises an AND gate131C including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node155and the output node of the latching feedback circuit130. Both the buffer121E and the AND gate131C are non-inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node155is at logic low, the output of the AND gate131C is forced to be at logic low thereby initializing the first input node of the receiver circuit120to be at logic low. And when the second input node155is at logic high, the AND gate131C is enabled to function as a non-inverting buffer.

FIG. 7illustrates still more exemplary embodiments of the receiver circuit120and the latching feedback circuit130. The receiver circuit120further comprises an inverting buffer121F including: an input terminal and an output terminal, coupled respectively to the first input node and the output node of the receiver circuit120. The latching feedback circuit130further comprises a NAND gate1310including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node155and the output node of the latching feedback circuit130. Both the buffer121F and the NAND gate1310are inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node155is at logic low, the output of the NAND gate1310is forced to be at logic high thereby initializing the first input node of the receiver circuit120to be at logic high. And when the second input node155is at logic high, the NAND gate1310is enabled to function as an inverting buffer.

FIG. 8illustrates still more exemplary embodiment of the latching feedback circuit130. The latching feedback circuit130further comprises an OR gate131E including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node155and the output node of the latching feedback circuit130. Both the buffer121E and the OR gate131E are non-inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node155is at logic high, the output of the OR gate131E is forced to be at logic high thereby initializing the first input node of the receiver circuit120to be at logic high. And when the second input node155is at logic low, the OR gate131E is enabled to function as a non-inverting buffer.

FIG. 9illustrates still more exemplary embodiment of the latching feedback circuit130. The latching feedback circuit130further comprises a NOR gate131F including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node155and the output node of the latching feedback circuit130. Both the buffer121F and the NOR gate131F are inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor101to the receiver circuit120. When the second input node155is at logic high, the output of the NOR gate131F is forced to be at logic low thereby initializing the first input node of the receiver circuit120to be at logic low. And when the second input node155is at logic low, the NOR gate131F is enabled to function as an inverting buffer.

Refer back toFIG. 1, the output node of the driver circuit110is at voltage GNDINfor logic low and at voltage VINfor logic high; while the digital output signal or the output node of the receiver circuit120or the output node of the latching feedback circuit130is at voltage GNDOUTfor logic low and at voltage VOUTfor logic high. Therefore, toggling the output node of the driver circuit110is equivalent to switching between logic low at GNDINand logic high at VIN; while toggling the digital output signal or the output node of the receiver circuit120or the output node of the latching feedback circuit130is equivalent to switching between logic low at GNDOUTand logic high at VOUT.

The functioning of a level shifter of the invention in various embodiments is based on capacitive coupling: since the voltage across the capacitor101cannot be changed instantaneously, when the output node of the driver circuit110switches from logic low at GNDINto logic high at VIN, the first terminal of the capacitor101also switches from logic low at GNDINto logic high at VIN, while the voltage at the second terminal of the capacitor101instantaneously jumps up by approximately (VIN−GNDIN) thereby sending a logic high signal to the first input node of the receiver circuit120; and vice versa, when the output node of the driver circuit110switches from logic high at VINto logic low at GNDIN, the first terminal of the capacitor101also switches from logic high at VINto logic low at GNDIN, while the voltage at the second terminal of the capacitor101instantaneously drops down by approximately (VIN−GNDIN) thereby sending a logic low signal to the first input node of the receiver circuit120. Therefore through capacitive coupling, the second terminal of the capacitor101toggles in sync with the toggling of the output node of the driver circuit110by approximately the same voltage differential of (VIN−GNDIN), and subsequently toggles the first input node of the receiver circuit120by either charging the first input node of the receiver circuit120from logic low to above a logic-high threshold voltage, or by discharging the first input node of the receiver circuit120from logic high to below a logic-low threshold voltage. Therefore, the capacitor101essentially functions as a toggling capacitor, and the level shifter is essentially edge-triggered. And since a toggling speed is essentially independent of the voltage across the capacitor101, it is a highly desirable advantage that the propagation delay of the level shifter of the invention is independent of the voltage differential between GNDOUTand GNDIN, but is primarily dependent on the propagation delays of the driver circuit110and the receiver circuit120.

However, the functioning of the aforementioned capacitive-coupling is contingent on one condition: it is imperative that the sum of the output resistance ROUT_130of the latching feedback circuit130and the resistance of the first resistor102is substantially larger than the output resistance ROUT_110of the driver circuit110, so that the output node of the latching feedback circuit130does not significantly oppose any toggling at the second terminal of the capacitor101before the latching feedback circuit130loops back to latch a toggled signal to the receiver circuit120.

For a level shifter of the invention in various embodiments to function properly after a power-up or any other reset, it is imperative that the first input node of the receiver circuit120and the output node of the driver circuit110are synchronized to be at an initial logic level, i.e., if the output node of the driver circuit110is at GNDINfor logic low initially, the first input node of the receiver circuit120is synchronized to be at GNDOUTfor logic low; and vice versa, if the output node of the driver circuit110is at VINfor logic high initially, the first input node of the receiver circuit120is synchronized to be at VOUTfor logic high.

To further assist in understanding,FIG. 10illustrates the functioning of the level shifter100as a process1000starting in step1002. Step1004is next, where the first input node of the receiver circuit120and the output node of the driver circuit110are synchronized to be at an initial logic level. Then step1006is next, where the process1000waits for the digital input signal to toggle. Then step1008is next, where the output node of the driver circuit110toggles. And instantaneously in step1010, the second terminal of the capacitor101toggles in sync with the toggling of the output node of the driver circuit110. If toggling from logic low to logic high, then step1012is next, where the capacitor101starts to charge the first input node of the receiver circuit120from logic low to above a logic-high threshold voltage while overcoming a sinking current to the output node of the latching feedback circuit130; or if toggling from logic high to logic low, then step1014is next, where the capacitor101starts to discharge the first input node of the receiver circuit120from logic high to below a logic-low threshold voltage while overcoming a sourcing current from the output node of the latching feedback circuit130. After either step1012or1014, then step1016is next, where the output node of the receiver circuit120toggles, thereby toggling the digital output signal and the first input node of the latching feedback circuit130. Then step1018is next, where the output node of the latching feedback circuit130toggles and subsequently reinforces and latches the toggled signal from the second terminal of the capacitor101to the receiver circuit120(either reaching logic high at VOUTafter steps1012and1016and1018, or reaching logic low at GNDOUTafter steps1014and1016and1018). If the digital input signal will continue to toggle, the process1000goes back from step1018to step1006and repeats; otherwise, the process1000ends in step1020.

As illustrated in the process1000, the output node of the latching feedback circuit130serves two opposite purposes one after another. At the instant when the second terminal of the capacitor101toggles, the output node of the latching feedback circuit130opposes the toggling or change in logic level. When the output node of the latching feedback circuit130loops back and toggles, the toggled signal is reinforced by positive feedback and is latched from the second terminal of the capacitor101to the receiver circuit120. Therefore in one embodiment, before the output node of the latching feedback circuit130loops back and provides positive feedback, in order to reliably toggle the first input node of the receiver circuit120, and to overcome an opposing sinking/sourcing current to/from the output node of the latching feedback circuit130, the capacitance of the capacitor101is adapted to be substantially larger than the input capacitance of the first input node of the receiver circuit120. And in another embodiment, the first input node of the receiver circuit120is preferably adapted to have a minimized input capacitance and minimized input current. And in another embodiment, the propagation delays of the receiver circuit120and the latching feedback circuit130are minimized.

Assuming the output resistance of the latching feedback circuit130is ROUT_130(please note ROUT_130may be different for logic-high output and for logic-low output), and assuming the output resistance of the driver circuit110is ROUT_110(please note ROUT_110may be different for logic-high output and for logic-low output), and assuming the resistance of the first resistor102is R102, and assuming the capacitance of the capacitor101is C101, the slew rate of GNDOUTrelative to GNDINthat can be tolerated by the level shifter100is approximately proportional to the following mathematical expression (1):

In other words, the smaller the sum of ROUT_130and ROUT_110and R102, the higher the slew rate; the smaller the C101, the higher the slew rate. Therefore, in one embodiment to improve the slew rate of GNDOUTrelative to GNDINfor the level shifter100, the sum of the output resistance of the latching feedback circuit130and the output resistance of the driver circuit110and the resistance of the first resistor102is minimized, and the capacitance of the capacitor101is minimized. In another embodiment, to further reduce the capacitance of the capacitor101, the input-power-supply amplitude of (VIN−GNDIN) may be adapted to be larger than the output-power-supply amplitude of (VOUT−GNDOUT).

And because GNDOUTrelative to GNDINmay move up and down frequently in real-world applications, the capacitor101and the output node of the driver circuit110and the output node of the latching feedback circuit130may all subsequently undergo frequent charging or discharging. Since a FET complementary output node allows current to flow in and out (for charging or discharging), in one embodiment of the driver circuit110, the output node of the driver circuit110is preferably adapted to be a FET complementary output node; likewise, in another embodiment of the latching feedback circuit130, the output node of the latching feedback circuit130is preferably adapted to be a FET complementary output node. In one embodiment, for a consistent capacitance over a certain operating voltage range and over a certain operating temperature range, and for low cost, the capacitor101is preferably adapted to be a ceramic capacitor of COG or NP0 dielectric.

A level shifter of the invention in various embodiments is primarily for ground-potential shifting, and is not primarily for signal-amplitude shifting. However, as another embodiment of the level shifter100, the digital output signal is optionally adapted to be coupled to a voltage translator (not illustrated) for further amplification or reduction of the digital output signal.

There are at least three methods to synchronize the first input node of the receiver circuit120and the output node of the driver circuit110to be at an initial logic level. The details are disclosed below.

The first method of synchronization works by toggling the output node of the driver circuit110at least twice with sufficiently wide pulse widths. If initially the output node of the driver circuit110is at GNDINfor logic low while the first input node of the receiver circuit120is at VOUTfor logic high, after a first toggling, the output node of the driver circuit110is switched to be at VINfor logic high, while the capacitor101is discharged to |VOUT−VIN|; after a second toggling, the output node of the driver circuit110is switched back to be at GNDINfor logic low, while the first input node of the receiver circuit120is synchronized to be at GNDOUTfor logic low. On the other hand, if initially the output node of the driver circuit110is at VINfor logic high while the first input node of the receiver circuit120is at GNDOUTfor logic low, after a first toggling, the output node of the driver circuit110is switched to be at GNDINfor logic low, while the capacitor101is charged to |GNDOUT−GNDIN|; after a second toggling, the output node of the driver circuit110is switched back to be at VINfor logic high, while the first input node of the receiver circuit120is synchronized to be at VOUTfor logic high. The first method of synchronization works only if the initial uncertainty of the logic level of the digital output signal is allowed for some special designs and applications. And it is imperative to have sufficiently wide pulse widths for the first input node of the receiver circuit120to settle at VOUTfor logic high or at GNDOUTfor logic low.

The second method of synchronization works by operating the second input node153(if included) of the receiver circuit120to initialize the output node of the receiver circuit120thereby, through the latching feedback circuit130, synchronizing the first input node of the receiver circuit120and the output node of the driver circuit110to be at the initial logic level. If initially the output node of the driver circuit110is at GNDINfor logic low, and if the receiver circuit120further comprises an AND gate121A (refer toFIG. 2) or a NAND gate121B (refer toFIG. 3), the second input node153is operable to be coupled to logic low thereby, through the latching feedback circuit130, synchronizing the first input node of the receiver circuit120to be at GNDOUTfor logic low. On the other hand, if initially the output node of the driver circuit110is at VINfor logic high, and if the receiver circuit120further comprises an OR gate1210(refer toFIG. 5) or a NOR gate121C (refer toFIG. 4), the second input node153is operable to be coupled to logic high thereby, through the latching feedback circuit130, synchronizing the first input node of the receiver circuit120to be at VOUTfor logic high. In one embodiment, the second input node153of the receiver circuit120is adapted to be coupled to a reset output node of any power-on reset circuit (not illustrated), such as a simple resistor-capacitor (RC) power-on reset circuit.

The third method of synchronization works by operating the second input node155(if included) of the latching feedback circuit130to initialize the output node of the latching feedback circuit130thereby synchronizing the first input node of the receiver circuit120and the output node of the driver circuit110to be at the initial logic level. If initially the output node of the driver circuit110is at GNDINfor logic low, and if the latching feedback circuit130further comprises an AND gate131C (refer toFIG. 6) or a NOR gate131F (refer toFIG. 9), the second input node155is operable to be coupled to logic low or logic high respectively thereby synchronizing the first input node of the receiver circuit120to be at GNDOUTfor logic low. On the other hand, if initially the output node of the driver circuit110is at VINfor logic high, and if the latching feedback circuit130further comprises an OR gate131E (refer toFIG. 8) or a NAND gate1310(refer toFIG. 7), the second input node155is operable to be coupled to logic high or logic low respectively thereby synchronizing the first input node of the receiver circuit120to be at VOUTfor logic high. In one embodiment, the second input node155of the latching feedback circuit130is adapted to be coupled to a reset output node of any power-on reset circuit (not illustrated), such as a simple RC power-on reset circuit.

When the voltage differential between GNDOUTand GNDINincreases substantially (such as in high-voltage applications), because the capacitor101may be charged or discharged rapidly, it is important to protect the following capacitor-101-coupled I/Os against any excessive voltage and/or current stress: the first input node of the receiver circuit120; the output node of the latching feedback circuit130; and the output node of the driver circuit110. More details are disclosed below and are accompanied byFIG. 11andFIG. 12.

In one embodiment to protect the level shifter100, the level shifter100further comprises one or more zener diodes (not illustrated), wherein each of the zener diode(s) has a zener voltage higher than a respective power supply and is coupled across the respective power supply.

As illustrated inFIG. 11, in one embodiment to protect the first input node of the receiver circuit120and the output node of the latching feedback circuit130and the output node of the driver circuit110, the level shifter100further comprises: a first diode161including an anode and a cathode, wherein the anode is coupled to the first input node of the receiver circuit120, and wherein the cathode is coupled to a reference output voltage VREF_OUT; a second diode162including an anode and a cathode, wherein the anode is coupled to a reference output ground potential GNDREF_OUT, and wherein the cathode is coupled to the first input node of the receiver circuit120; a third diode163including an anode and a cathode, wherein the anode is coupled to the output node of the driver circuit110, and wherein the cathode is coupled to a reference input voltage VREF_IN; and a fourth diode164including an anode and a cathode, wherein the anode is coupled to a reference input ground potential GNDREF_IN, and wherein the cathode is coupled to the output node of the driver circuit110. In another embodiment, VREF_OUTis preferably adapted to be higher than or equal to VOUT, and GNDREF_OUTis preferably adapted to be lower than or equal to GNDOUT, and VREF_INis preferably adapted to be higher than or equal to VIN, and GNDREF_INis preferably adapted to be lower than or equal to GNDIN. These diodes161and162and163and164are essentially clamping diodes, and may also serve as electrostatic-discharge (ESD) protection diodes. And it is highly desirable for these diodes to possess minimal diode capacitances in order not to significantly interfere with the functioning of the aforementioned capacitive-coupling.

Based on the embodiment illustrated inFIG. 11, to further protect the first input node of the receiver circuit120and the output node of the latching feedback circuit130and the output node of the driver circuit110against any excessive voltage and/or current stress, in another embodiment illustrated inFIG. 12, the level shifter100further comprises: a second resistor103, being inserted between the second terminal of the capacitor101and the first input node (at node157) of the receiver circuit120; a third resistor104, being inserted between the first terminal of the capacitor101and the output node of the driver circuit110; a fifth diode165including an anode and a cathode, wherein the anode is coupled to the output node of the latching feedback circuit130, and wherein the cathode is coupled to VREF_OUT; and a sixth diode166including an anode and a cathode, wherein the anode is coupled to GNDREF_OUT, and wherein the cathode is coupled to the output node of the latching feedback circuit130. Refer to the mathematical expression (1), assuming the resistance of the third resistor104is R104, the slew rate of GNDOUTrelative to GNDINthat can be tolerated by the level shifter100is updated to be approximately proportional to the following mathematical expression (2):

1(ROUT⁢⁢_⁢⁢130+ROUT⁢⁢_⁢110+R102+R104)⁢C101(2)
In other words, the smaller the sum of ROUT_130and ROUT_110and R102and R104, the higher the slew rate; the smaller the C101, the higher the slew rate. However, for the level shifter100to function properly, it is imperative that (ROUT_130+R102) is adapted to be substantially larger than (ROUT_110+R104).

In a second embodiment of the invention, as illustrated inFIG. 13, a level shifter200for level-shifting a digital input signal (at node250) referenced to an input ground potential GNDINto a digital output signal (at node254) referenced to an output ground potential GNDOUT, wherein GNDOUTis higher than or equal to or lower than GNDIN, comprising: a driver circuit210including an input node (at node250) and an output node (at node251), powered by an input power supply VINreferenced to GNDIN, and configured as inverting or non-inverting (depending on the requirement(s) of a specific embodiment), and wherein the input node is coupled to the digital input signal, and wherein the output node toggles when the digital input signal toggles; a capacitor201including a first terminal (at node251) and a second terminal (at node252), wherein the first terminal is coupled to the output node of the driver circuit210, and wherein the second terminal toggles in sync with the toggling of the output node of the driver circuit210; a receiver circuit220including a first input node (coupled to node252) and an output node (at node254), powered by an output power supply VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the second terminal of the capacitor201, and wherein the output node is coupled to the digital output signal, and wherein the digital output signal toggles when the second terminal of the capacitor201toggles; and a latching feedback circuit230including a first input node (at node254) and an output node (at node252), powered by VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the output node of the receiver circuit220, and wherein the output node is coupled to the second terminal of the capacitor201, and wherein the output resistance ROUT_230of the latching feedback circuit230is substantially larger than the output resistance ROUT_210of the driver circuit210, and configured as non-inverting if the receiver circuit220is non-inverting, or configured as inverting if the receiver circuit220is inverting, thereby providing a positive feedback loop to latch a toggled signal from the second terminal of the capacitor201to the receiver circuit220.

In one embodiment, the receiver circuit220may further includes a second input node253for initializing or enabling the receiver circuit220, and wherein the second input node253is operable to synchronize the first input node of the receiver circuit220and the output node of the driver circuit210to be at an initial logic level, and wherein the receiver circuit220further comprises an AND gate or a NAND gate or an OR gate or a NOR gate including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the second input node253and the output node of the receiver circuit220.

In one embodiment, the latching feedback circuit230may further includes a second input node255for initializing or enabling the latching feedback circuit230, and wherein the second input node255is operable to synchronize the first input node of the receiver circuit220and the output node of the driver circuit210to be at an initial logic level, and wherein the latching feedback circuit230further comprises an AND gate or a NAND gate or an OR gate or a NOR gate including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the second input node255and the output node of the latching feedback circuit230.

FIG. 14illustrates some exemplary embodiments of the driver circuit210, the receiver circuit220and the latching feedback circuit230. The driver circuit210further comprises a non-inverting buffer211A including: an input terminal and an output terminal, coupled respectively to the input node and the output node of the driver circuit210. The receiver circuit220further comprises an AND gate221A including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node253and the output node of the receiver circuit220. The latching feedback circuit230further comprises a non-inverting buffer231A including: an input terminal and an output terminal, coupled respectively to the first input node and the output node of the latching feedback circuit230. Both the AND gate221A and the buffer231A are non-inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor201to the receiver circuit220. When the second input node253is at logic low, the output of the AND gate221A is forced to be at logic low; then the output of the non-inverting buffer231A is also at logic low thereby initializing the first input node of the receiver circuit220to be at logic low. And when the second input node253is at logic high, the AND gate221A is enabled to function as a non-inverting buffer.

FIG. 15illustrates more exemplary embodiments of the driver circuit210, the receiver circuit220and the latching feedback circuit230. The driver circuit210further comprises an inverting buffer211B including: an input terminal and an output terminal, coupled respectively to the input node and the output node of the driver circuit210. The receiver circuit220further comprises an inverting buffer221B including: an input terminal and an output terminal, coupled respectively to the first input node and the output node of the receiver circuit220. The latching feedback circuit230further comprises a NAND gate231B including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node255and the output node of the latching feedback circuit230. Both the buffer221B and the NAND gate231B are inverting, and are operable to provide a positive feedback loop to latch a toggled signal from the second terminal of the capacitor201to the receiver circuit220. When the second input node255is at logic low, the output of the NAND gate231B is forced to be at logic high thereby initializing the first input node of the receiver circuit220to be at logic high. And when the second input node255is at logic high, the NAND gate231B is enabled to function as an inverting buffer.

Assuming the output resistance of the latching feedback circuit230is ROUT_230, and assuming the output resistance of the driver circuit210is ROUT_210, and assuming the capacitance of the capacitor201is C201, the slew rate of GNDOUTrelative to GNDINthat can be tolerated by the level shifter200is approximately proportional to the following mathematical expression (3):

1(ROUT⁢⁢_⁢⁢230+ROUT⁢⁢_⁢210)⁢C201(3)
In other words, the smaller the sum of ROUT_230and ROUT_210, the higher the slew rate; the smaller the C201, the higher the slew rate.

In one embodiment, the capacitance of the capacitor201is adapted to be substantially larger than the input capacitance of the first input node of the receiver circuit220, and the first input node of the receiver circuit220has a minimized input capacitance and minimized input current. In one embodiment, to protect I/Os, the level shifter200may further comprise one or more pairs of clamping diodes. And in one embodiment, to further protect the level shifter200, the level shifter200may further comprise one or more zener diodes, wherein each of the zener diode(s) is coupled across a respective power supply.

In a third embodiment of the invention, as illustrated inFIG. 16, a level shifter300for level-shifting a digital input signal (at node350) referenced to an input ground potential GNDINto a digital output signal (at node354) referenced to an output ground potential GNDOUT, wherein GNDOUTis higher than or equal to or lower than GNDIN, comprising: a driver circuit310including an input node (at node350) and an output node (at node351), powered by an input power supply VINreferenced to GNDIN, and configured as inverting or non-inverting (depending on the requirement(s) of a specific embodiment), and wherein the input node is coupled to the digital input signal, and wherein the output node toggles when the digital input signal toggles; a capacitor301including a first terminal (at node351) and a second terminal (at node352), wherein the first terminal is coupled to the output node of the driver circuit310, and wherein the second terminal toggles in sync with the toggling of the output node of the driver circuit310; a first resistor302including a first terminal (at node352) and a second terminal (at node354), wherein the first terminal of the first resistor302is coupled to the second terminal of the capacitor301; a non-inverting receiver circuit320including a first input node (coupled to node352) and an output node (at node354), powered by an output power supply VOUTreferenced to GNDOUT, and wherein the first input node is coupled to the second terminal of the capacitor301, and wherein the output node is coupled both to the digital output signal and to the second terminal of the first resistor302, and wherein the sum of the output resistance ROUT_320of the non-inverting receiver circuit320and the resistance of the first resistor302is substantially larger than the output resistance ROUT_310of the driver circuit310, and wherein the digital output signal toggles when the second terminal of the capacitor301toggles, and wherein the output node provides a positive feedback loop to latch a toggled signal from the second terminal of the capacitor301to the non-inverting receiver circuit320. Compared with the first or the second embodiment of the invention, the non-inverting receiver circuit320performs equivalently to the combination of a receiver circuit (120or220) and a latching feedback circuit (130or230).

In one embodiment, the non-inverting receiver circuit320may further includes a second input node353for initializing or enabling the non-inverting receiver circuit320, and wherein the second input node353is operable to synchronize the first input node of the non-inverting receiver circuit320and the output node of the driver circuit310to be at an initial logic level, and wherein the non-inverting receiver circuit320further comprises an AND gate or an OR gate including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the second input node353and the output node of the non-inverting receiver circuit320.

FIG. 17illustrates some exemplary embodiments of the driver circuit310and the non-inverting receiver circuit320. The driver circuit310further comprises a non-inverting buffer311A including: an input terminal and an output terminal, coupled respectively to the input node and the output node of the driver circuit310. The non-inverting receiver circuit320further comprises an AND gate321A including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node353and the output node of the non-inverting receiver circuit320. When the second input node353is at logic low, the output of the AND gate321A is forced to be at logic low thereby initializing the first input node of the non-inverting receiver circuit320to be at logic low. And when the second input node353is at logic high, the AND gate321A is enabled to function as a non-inverting buffer.

FIG. 18illustrates more exemplary embodiments of the driver circuit310and the non-inverting receiver circuit320. The driver circuit310further comprises an inverting buffer311B including: an input terminal and an output terminal, coupled respectively to the input node and the output node of the driver circuit310. The non-inverting receiver circuit320further comprises an OR gate321B including: a first input terminal and a second input terminal and an output terminal, coupled respectively to the first input node and the optional second input node353and the output node of the non-inverting receiver circuit320. When the second input node353is at logic high, the output of the OR gate321B is forced to be at logic high thereby initializing the first input node of the non-inverting receiver circuit320to be at logic high. And when the second input node353is at logic low, the OR gate321B is enabled to function as a non-inverting buffer.

Assuming the output resistance of the non-inverting receiver circuit320is ROUT_320, and assuming the output resistance of the driver circuit310is ROUT_310, and assuming the capacitance of the capacitor301is C301, the slew rate of GNDOUTrelative to GNDINthat can be tolerated by the level shifter300is approximately proportional to the following mathematical expression (4):

1(ROUT⁢⁢_⁢320+ROUT⁢⁢_⁢310)⁢C301(4)
In other words, the smaller the sum of ROUT_320and ROUT_310, the higher the slew rate; the smaller the C301, the higher the slew rate.

In one embodiment, the capacitance of the capacitor301is adapted to be substantially larger than the input capacitance of the first input node of the non-inverting receiver circuit320, and the first input node of the non-inverting receiver circuit320has a minimized input capacitance and minimized input current. In one embodiment, to protect I/Os, the level shifter300may further comprise one or more pairs of clamping diodes. And in one embodiment, to further protect the level shifter300, the level shifter300may further comprise one or more zener diodes, wherein each of the zener diode(s) is coupled across a respective power supply.

INDUSTRIAL APPLICABILITY

In view of the foregoing, the industrial applicability of the present invention is broad and can provide a level shifter which is scalable from low-voltage to high-voltage applications, and which can tolerate substantial slew rate of output ground potential relative to input ground potential, and which has short and easy-to-match propagation delays, and which consumes low power, and which is low-cost. Applications of such a level shifter include any level-shifting of a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, such as battery management systems, supercapacitor management systems, and so forth.

While the foregoing invention shows a number of illustrative and descriptive embodiments of the invention, it will be apparent to any person with ordinary skills in the area of technology related to the invention that various changes, modifications, substitutions and combinations can be made herein without departing from the scope or the spirit of the invention as defined by the following claims.