Failure of a processing unit that processes a plurality of information pieces is discovered in a short time. An information processing device 100 including a processing unit 1 that processes a plurality of information pieces includes: an identifier assignment unit 2 that assigns identifiers 60000 to 61023 to the plurality of information pieces 40000 to 41023, respectively; a plurality of input memories 20000 to 21023 that retain the plurality of information pieces 40000 to 41023 and the identifiers 60000 to 61023 assigned to the plurality of information pieces 40000 to 41023, respectively; a plurality of output memories 30000 to 31023 that retain the plurality of information pieces 50000 to 51023 processed by the processing unit 1 and the identifiers 70000 to 71023 assigned to the plurality of processed information pieces 50000 to 51023, respectively; an identifier verification unit 3 that verifies the identifiers 70000 to 71023 by comparing the identifiers 70000 to 71023 with the identifiers 60000 to 61023, respectively; and an error handling unit 4 that performs error handling when identifiers do not match with each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a National Stage application under 35 U.S.C. § 371 of International Application No. PCT/JP2020/000335, having an International Filing Date of Jan. 8, 2020, which claims priority to Japanese Application Serial No. 2019-004839, filed on Jan. 16, 2019. The disclosure of the prior application is considered part of the disclosure of this application, and is incorporated in its entirety into this application.

TECHNICAL FIELD

The present invention relates to an information processing device and an information processing method.

BACKGROUND ART

Some of conventional information processing devices include a single processing unit, and the processing unit processes a plurality of information pieces. Such information processing devices include a plurality of input memories and a plurality of output memories in order to process the plurality of information pieces. For example, when an information processing device processes 1024-ch information pieces (“ch” is an abbreviation for “channel”), the information processing device includes input memories for the 1024 chs and output memories for the 1024 chs.

When the processing unit is normal, the processing unit reads information of an N-th (N=0, 1, . . . , 1022, 1023) ch from an input memory for the N-th ch and, after processing the information, writes the processed information to an output memory for the N-th ch. However, when the processing unit fails, the processing unit reads information of the N-th ch from the input memory for the N-th ch and, after processing the information, erroneously writes the processed information to an output memory for an M-th (M=0, 1, . . . , 1022, 1023 and M≠N) ch in some cases. As a result, a situation may be brought about where information of the M-th ch that is different from the information supposed to be outputted is outputted to a receiver who is to receive the information of the N-th ch.

However, even when a processing unit fails as described above, there has conventionally been no means for discovering such failure in a short time. Accordingly, there has been a problem that the situation continues where information that is different from information supposed to be outputted is outputted. Particularly in digital signal processing by a DSP (Digital Signal Processor) as a processing unit (see Non-Patent Literature 1), the processing needs to be completed within a predetermined time period (latency), so a processing rate tends to be prioritized. Accordingly, conventionally, amending a processing error such as ch switching is viewed as less important.

CITATION LIST

SUMMARY OF THE INVENTION

Technical Problem

In view of such a background, the present invention addresses the challenge of discovering, in a short time, failure of a processing unit that processes a plurality of information pieces.

Means for Solving the Problem

To solve the challenge, an aspect of the invention according to claim1is an information processing device including a processing unit that processes a plurality of information pieces, including: an identifier assignment unit that assigns identifiers to the plurality of information pieces, respectively; a plurality of input memories that retain the plurality of information pieces and the identifiers assigned to the plurality of information pieces, respectively; a plurality of output memories that retain the plurality of information pieces processed by the processing unit and the identifiers assigned to the plurality of processed information pieces, respectively; and an identifier verification unit that verifies the identifiers respectively retained in the output memories, by comparing the identifiers respectively retained in the output memories with the identifiers respectively retained in the input memories, respectively.

An aspect of the invention according to claim3is an information processing method in an information processing device including a processing unit that processes a plurality of information pieces, including: by the information processing device, assigning identifiers to the plurality of information pieces, respectively; retaining the plurality of information pieces and the identifiers assigned to the plurality of information pieces in a plurality of input memories, respectively; retaining the plurality of information pieces processed by the processing unit and the identifiers assigned to the plurality of processed information pieces in a plurality of output memories, respectively; and verifying the identifiers respectively retained in the output memories, by comparing the identifiers respectively retained in the output memories with the identifiers respectively retained in the input memories, respectively.

According to the aspects of the invention according to claims1and3, by verifying an identifier retained in an output memory, it can be reliably determined whether or not an information piece to which the identifier is assigned is intended information, that is, whether or not an information piece to which the identifier is assigned is information supposed to be retained in the output memory.

Accordingly, failure of the processing unit that processes the plurality of information pieces can be discovered in a short time.

An aspect of the invention according to claim2is the information processing device according to claim1, further including an error handling unit that performs error handling when, as a result of the verification, an identifier retained in a specified output memory among the plurality of output memories does not match with an identifier retained in a specified one of the input memories that corresponds to the specified output memory.

An aspect of the invention according to claim4is the information processing method according to claim3, further including, by the information processing device, performing error handling when, as a result of the verifying, an identifier retained in a specified output memory among the plurality of output memories does not match with an identifier retained in a specified one of the input memories that corresponds to the specified output memory.

According to the aspects of the invention according to claims2and4, means for handling when failure of the processing unit is discovered can be provided.

Effects of the Invention

According to the present invention, failure of a processing unit that processes a plurality of information pieces can be discovered in a short time.

DESCRIPTION OF EMBODIMENTS

Hereinafter, an embodiment for carrying out the present invention (hereinafter, referred to as the “present embodiment”) will be described with reference to drawings.

As shown inFIG. 1, an information processing device100according to the present embodiment includes a processing unit1, input memories20000to21023, output memories30000to31023, an identifier assignment unit2, an identifier verification unit3, and an error handling unit4. In the present embodiment, a description is given, assuming that the information processing device100processes information pieces of 1024 chs.

The processing unit1processes a plurality of information pieces. In the present embodiment, a description is given, assuming that the information processing device100includes the single processing unit1. However, the present invention is also applicable when the information processing device100includes a plurality of the processing units1. For example, the processing unit1may be, but is not limited to, a microcomputer or a DSP. For example, processing by the processing unit1may be, but is not limited to, echo cancellation, codec conversion, or bandwidth compression.

The input memories20000to21023retain information pieces40000to41023of the 1024 chs inputted into the information processing device100, respectively. The information pieces40000to41023are information before processed by the processing unit1. For example, the information pieces40000to41023may be, but is not limited to, audio.

The output memories30000to31023retain information pieces50000to51023of the 1024 chs to be outputted from the information processing device100to a receiver (not shown), respectively. The information pieces50000to51023are information after processed by the processing unit1. For example, the information pieces50000to51023may be, but is not limited to, audio.

When the processing unit1is normal, the processing unit1reads an information piece of an N-th (N=0, 1, . . . , 1022, 1023) ch from an input memory for the N-th ch and, after processing the information piece, writes the processed information piece to an output memory for the N-th ch.

The identifier assignment unit2assigns identifiers60000to61023that identify the information pieces40000to41023, respectively, to the information pieces40000to41023, respectively. For example, the identifiers60000to61023may be, but are not limited to, 10-bit binary data. The input memories20000to21023include areas in which the information pieces40000to41023are retained, respectively, and areas in which the identifiers60000to61023are retained, respectively, and retain the information pieces40000to41023and the identifiers60000to61023, respectively.

When the processing unit1reads the information piece of the N-th ch from the input memory for the N-th ch, the processing unit1also reads an identifier assigned to the information piece of the N-th ch. When the processing unit1processes the information piece of the N-th ch, the processing unit1leaves the identifier assigned to the information piece of the N-th ch unchanged. The processing unit1writes the processed information piece of the N-th ch and the identifier assigned to the processed information piece of the N-th ch to the output memory for the N-th ch. The output memories30000to31023include areas in which the processed information pieces50000to51023are retained, respectively, and areas in which identifiers70000to71023assigned to the information pieces50000to51023are retained, respectively, and retain the information pieces50000to51023and the identifiers70000to71023, respectively.

The identifier verification unit3verifies the identifiers70000to71023respectively retained in the output memories30000to31023, by comparing the identifiers70000to71023with the identifiers60000to61023respectively retained in the input memories20000to21023, respectively. Specifically, the identifier verification unit3reads the identifier assigned to the processed information piece of the N-th ch from the output memory for the N-th ch, and determines whether or not the read identifier matches with the identifier that is assigned to the information piece of the N-th ch before processed and is retained in the input memory for the N-th ch (corresponding input memory). Note that the identifier verification unit3keeps track of which one of the input memories20000to21023each identifier assigned by the identifier assignment unit2is retained in.

The error handling unit4performs error handling when an identifier mismatch is found between the identifiers70000to71023and the identifiers60000to61023as a result of the verification of the identifiers70000to71023by the identifier verification unit3. Specifically, when the identifier assigned to the processed information piece of the N-th ch and read from the output memory for the N-th ch does not match with the identifier assigned to the information piece of the N-th ch before processed and retained in the input memory for the N-th ch, the error handling unit4determines that the processing unit1fails, and performs error handling. For example, the error handling can be, but is not limited to, to notify an administrator or to discard the information piece with the mismatching identifier.

An operation example will be described, with respect to an information piece41022of a 1022nd ch and an identifier61022with a value of “1111111110” assigned to the information piece41022, which are retained in a 1022nd-ch input memory21022, and an information piece41023of a 1023rd ch and an identifier61023with a value of “1111111111” assigned to the information piece41023, which are retained in a 1023rd-ch input memory21023, shown inFIG. 1.

When the processing unit1is normal, the processing unit1reads the information piece41022of the 1022nd ch and the identifier61022from the 1022nd-ch input memory21022and performs processing. After the processing, the processing unit1writes a processed information piece51022of the 1022nd ch and an identifier71022with the unchanged value of “1111111110” to a 1022nd-ch output memory31022. The identifier verification unit3reads the identifier71022assigned to the processed information piece51022of the 1022nd ch from the 1022nd-ch output memory31022, and determines whether or not the identifier71022matches with the identifier61022that is assigned to the information piece of the 1022nd ch before processed and is retained in the 1022nd-ch input memory21022. In the present case, since both the identifiers71022,61022have the value of “1111111110” and match with each other, it is determined that the processing unit1is normal. Moreover, it is determined that the processed information piece51022of the 1022nd ch retained in the 1022nd-ch output memory31022corresponds to the information piece41022of the 1022nd ch before processed retained in the 1022nd-ch input memory21022.

Similarly, the processing unit1reads the information piece41023of the 1023rd ch and the identifier61023from the 1023rd-ch input memory21023and performs processing. After the processing, the processing unit1writes a processed information piece51023of the 1023rd ch and an identifier71023with the unchanged value of “1111111111” to a 1023rd-ch output memory31023. The identifier verification unit3reads the identifier71023assigned to the processed information piece51023of the 1023rd ch from the 1023rd-ch output memory31023, and determines whether or not the identifier71023matches with the identifier61023that is assigned to the information piece of the 1023rd ch before processed and is retained in the 1023rd-ch input memory21023. In the present case, since both the identifiers71023,61023have the value of “1111111111” and match with each other, it is determined that the processing unit1is normal. Moreover, it is determined that the processed information piece51023of the 1023rd ch retained in the 1023rd-ch output memory31023corresponds to the information piece41023of the 1023rd ch before processed retained in the 1023rd-ch input memory21023.

When the processing unit1fails, it is assumed that the processed information piece51023of the 1023rd ch and the identifier71023with the value of “1111111111” assigned to the information piece51023are retained in the 1022nd-ch output memory31022, as shown inFIG. 2. The identifier verification unit3verifies the identifier71023read from the 1022nd-ch output memory31022. In the present case, the value “1111111111” of the identifier71023read from the 1022nd-ch output memory31022does not match with the value “1111111110” of the identifier61022that is assigned to the information piece41022of the 1022nd ch before processed and is retained in the 1022nd-ch input memory21022. Accordingly, the identifier verification unit3determines that the processing unit1fails. Moreover, it is determined that the processed information piece51023of the 1023rd ch retained in the 1022nd-ch output memory31022does not correspond to the information piece41022of the 1022nd ch before processed retained in the 1022nd-ch input memory21022. Accordingly, the error handling unit4performs error handling for the processed information piece51023of the 1023rd ch retained in the 1022nd-ch output memory31022.

Similarly, it is assumed that the processed information piece51022of the 1022nd ch and the identifier71022with the value of “1111111110” assigned to the information piece51022are retained in the 1023rd-ch output memory31023, as shown inFIG. 2. The identifier verification unit3verifies the identifier71022read from the 1023rd-ch output memory31023. In the present case, the value “1111111110” of the identifier71022read from the 1023rd-ch output memory31023does not match with the value “1111111111” of the identifier61023that is assigned to the information piece41023of the 1023rd ch before processed and is retained in the 1023rd-ch input memory21023. Accordingly, the identifier verification unit3determines that the processing unit1fails. Moreover, it is determined that the processed information piece51022of the 1022nd ch retained in the 1023rd-ch output memory31023does not correspond to the information piece41023of the 1023rd ch before processed retained in the 1023rd-ch input memory21023. Accordingly, the error handling unit4performs error handling for the processed information piece51022of the 1022nd ch retained in the 1023rd-ch output memory31023.

Next, processing by the information processing device100will be described with reference toFIG. 3. The present processing is started when information pieces of the 1024 chs are inputted into the information processing device100.

First, the information processing device100, through the identifier assignment unit2, assigns an individual identifier to each of the information pieces of the 1024 chs (step S1). Next, the information processing device100retains the information pieces of the 1024 chs and the identifiers respectively assigned to the information pieces in the input memories20000to21023for the 1024 chs, respectively (step S2).

Next, the information processing device100, through the processing unit1, reads the information pieces and the identifiers from the input memories20000to21023, respectively, and processes the information pieces (step S3). At the time, the processing unit1does not change the identifiers. Next, the information processing device100, through the processing unit1, writes the processed information pieces of the 1024 chs and the identifiers respectively assigned to the processed information pieces to the output memories (step S4). At the time, the processing unit1writes a processed information piece of the N-th ch and an identifier assigned to the processed information piece to an output memory for the N-th ch.

Next, the information processing device100performs loop processing with respect to a variable N (N=0, 1, . . . , 1022, 1023) in step S5(S5a, S5b) to step S8. First, the information processing device100, through the identifier verification unit3, verifies the identifier retained in the output memory for the N-th ch (step S6). Next, the information processing device100, through the identifier verification unit3, determines whether or not the verification-target identifier retained in the output memory for the N-th ch matches with an identifier retained in an input memory for the N-th ch (step S7).

When the identifiers match with each other (Yes in step S7), the information processing device100, through the identifier verification unit3, determines that the processing unit1is normal. Thereafter, the information processing device100performs the loop processing on a next identifier. When the identifiers do not match with each other (No in step S7), the information processing device100, through the identifier verification unit3, determines that the processing unit1fails. In such a case, the information processing device100, through the error handling unit4, performs error handling for a processed information piece of the N-th ch retained in the output memory for the N-th ch (step S8). Thereafter, the information processing device100performs the loop processing on a next identifier.

When the loop processing is performed on all of N, the processing by the information processing device100is terminated.

According to the present embodiment, by verifying an identifier retained in an output memory, it can be reliably determined whether or not an information piece to which the identifier is assigned is intended information, that is, whether or not an information piece to which the identifier is assigned is information supposed to be retained in the output memory.

Accordingly, failure of the processing unit1that processes a plurality of information pieces can be discovered in a short time.

Moreover, means for handling when the failure of the processing unit1is discovered can be provided.

In the present embodiment, the information processing device100is configured, through the error handling unit4, to perform error handling for the processed information piece of the N-th ch retained in the output memory for the N-th ch (see step S8inFIG. 3). However, for example, the error handling unit4may perform error handling on the information processing device100as a whole when an identifier mismatch is found with respect to even one ch.

A technique can also be implemented by combining various techniques described in the present embodiment as appropriate.

REFERENCE SIGNS LIST

100Information processing device

2Identifier assignment unit

3Identifier verification unit

4Error handling unit

60000to61023Identifiers (retained in the input memories)

70000to71023Identifiers (retained in the output memories)