Trigger to data synchronization of gigahertz digital-to-analog converters

A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

TECHNICAL FIELD

This disclosure is directed in general to radar systems. More specifically, this disclosure relates to a trigger to data synchronization of gigahertz digital-to-analog converters.

BACKGROUND

Modern radar target scene generation systems typically need to have signals between components synchronized for effective radar scene generation. One problem related to synchronization is real-time radio frequency (RF) scene generation for hardware-in-the-loop (HWIL) applications, where misalignment and uncertainty of signals can decrease fidelity and cause range, angle and fidelity errors in a radar system's interpretation of synthesized radar returns. Gigahertz digital-to-analog converters (DACs) possess characteristics that make them difficult to align to each other and to an external trigger and get deterministic timing. The problem becomes more difficult if multiple DACs are located on separate circuit cards. For example, a high-speed serial input of a DAC is often in a different clock domain than an output sample clock of the DAC. The DACs may therefore rely on internal phase-locked loops (PLLs) to generate internal clocks from an external source. This creates uncertainty regarding when each DAC is initialized due to variances in PLL stability. Additionally, the external trigger meant to synchronize the DACs outputs may be on yet another clock domain, adding to the uncertainty of trigger to analog data output timing.

SUMMARY

This disclosure provides a trigger to data synchronization of gigahertz digital-to-analog converters.

In a first embodiment, a method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at a digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

In a second embodiment, an apparatus includes a radar timing card and multiple DAC channels on one or more DAC cards. The radar timing card is configured to receive radar timing information and a synchronous clock signal and generate a timing trigger to indicate a time of transmission for radar return information. Each DAC channel is configured to receive the synchronous clock signal, receive the timing trigger, and transmit a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The apparatus is configured to use the synchronous clock signal to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

In a third embodiment, a system includes a missile stack unit, a clock synchronizer, and a closed-loop radar computer. The missile stack unit is configured to generate a system clock signal. The clock synchronizer is configured to convert the system clock signal into a synchronous clock signal. The closed-loop radar computer includes a radar timing card and multiple DAC channels on one or more DAC cards. The radar timing card is configured to receive radar timing information and the synchronous clock signal and generate a timing trigger to indicate a time of transmission for radar return information. Each DAC channel is configured to receive the synchronous clock signal, receive the timing trigger, and transmit a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The closed-loop radar computer is configured to use the synchronous clock signal to align the simultaneous transmissions of the DAC channel on the one or more DAC cards.

DETAILED DESCRIPTION

For simplicity and clarity, some features and components are not explicitly shown in every figure, including those illustrated in connection with other figures. It will be understood that all features illustrated in the figures may be employed in any of the embodiments described. Omission of a feature or component from a particular figure is for purposes of simplicity and clarity and is not meant to imply that the feature or component cannot be employed in the embodiments described in connection with that figure. It will be understood that embodiments of this disclosure may include any one, more than one, or all of the features described here. Also, embodiments of this disclosure may additionally or alternatively include other features not listed here.

The use of gigahertz digital-to-analog converters (DACs) for creating synthesized pulsed radar return signals for hardware-in-the-loop testing is challenging. Aligning multiple gigahertz DAC output channels across multiple devices and circuit cards is notoriously difficult. For example, a timing relationship between all DAC outputs and an external time trigger signal being synchronized and aligned typically needs to be deterministic and repeatable across multiple coherent processing intervals (CPIs), consisting of multiple pulse repetition intervals (PRIs). The external time trigger signal is used to align synthesized radar return data to a radar receive window.

Some previous attempts include alignment of channels by modifying sample clock signals provided to different DAC outputs. These attempts help channel-to-channel alignment but not trigger-to-channel alignment. Other previous attempts reset the DACs until a phase alignment of internal sample clock phase-locked loops (PLLs) are in phase. These attempts also help channel-to-channel alignment but not trigger-to-channel alignment. Yet other previous attempts involve a hardware solution to obtain channel-to-channel alignment by constantly reinitializing the DACs until all DACs are aligned. Once again, these attempts help channel-to-channel alignment but not trigger-to-channel alignment. Still other attempts involve resetting a high-speed serial link to each DAC to bring the DACs all up at similar times. These attempts improve channel-to-channel alignment for a single card but not trigger-to-channel alignment or even channel-to-channel alignment across multiple DAC circuit cards. Scaling of these previous attempts to many cards and channels is challenging, if not practical. This disclosure provides various techniques for triggering data synchronization of gigahertz DACs that overcome these or other issues. These techniques' are easily scaled across numerous DAC circuit cards and channels.

FIG. 1illustrates an example system100for performing a trigger to data synchronization of gigahertz digital-to-analog converters (DACs) according to this disclosure. As shown inFIG. 1, the system100includes a radar system102, a clock distribution electronics104, and a closed-loop radar return synthesizer106. The system100enables trigger-to-channel synchronization and channel-to-channel synchronization. The system100also supports deterministic timing that only needs to be calibrated once and that eliminates clock drift between components and reduces uncertainty in radar return timing.

The radar system102represents a radar system, missile system, or the like that is undergoing operation in the system100. In some embodiments, the radar system102may represent a ground-based radar system that is installed in a fixed position on land or on a ground vehicle. In other embodiments, the radar system102may represent a radar system disposed in or on an aircraft or spacecraft, such as a missile. In the example shown inFIG. 1, the radar system102represents an eight-channel radar system, although this is merely for illustration only. Other numbers of channels are possible (such as a six-channel radar system) and within the scope of this disclosure. Additionally, the use of a transmitting antenna driven by each DAC channel to form an antenna array to present the radar return scene to the radar systems antenna(s) is possible, in place of illustration which depicts the DACs driving into the radar system's receiver's electrical analog inputs.

In this example, the radar system102includes a radar system clock108and an intermediate frequency (IF) receiver110. The radar system102also includes processing circuitry, memory, or other component(s) configured to output radar timing parameters112. For example, the radar system102can generate a signal that is reflected off a target surface and can detect the reflected signal, and different information related to the generated signal can be output as the radar timing parameters112.

The radar system clock108represents a clock installed in the radar system102to maintain synchronicity between different functions within the system100. For example, the radar timing parameters112can include the current time and future timing information for when the radar system's radar return receive windows will be active. The radar system clock108can also output a system clock signal114to one or more components within the closed-loop radar return synthesizer106using clock distribution electronics104.

The clock distribution electronics104operates to ensure that the radar system102and the closed-loop radar return synthesizer106have synchronized clocks or use the same clock signal from the radar system clock108. This enables the closed-loop radar return synthesizer106to output analog signals to the radar system102at precisely the right times by maintaining the same time reference between the radar system102and the closed-loop radar return synthesizer106. For example, in one aspect of operation, the clock distribution electronics104receives a system clock signal114from the radar system102, distributes a synchronous clock signal116to the closed-loop radar return synthesizer106components.

In this example, the closed-loop radar return synthesizer106includes a radar timing card118, multiple graphics processing units (GPUs) or computer processors120, and multiple DAC cards122a-122n. The closed-loop radar return synthesizer106can receive radar timing parameters112from the radar system102and the synchronous clock signal116from the clock distribution electronics104. As described in greater detail below, the closed-loop radar return synthesizer106calculates radar return information in a timeframe that is short enough so that an output is processed as synchronized outputs over multiple channels. The number of generated radar returns that may be produced by the system100inFIG. 1may be limited only by the number and performance of the computer processors120and the required time available. Thus, the system100is scalable for testing of simple to highly-complex radar scenes. The calculations and functions performed within the system100are distributed across the components of the system100according to the capabilities of each component so as to optimize the performance of the system100as a whole.

The radar timing card118may be communicatively coupled to the radar system102via a wired or other suitable communication interface. The radar timing card118generally operates to collect radar scene information from the radar system102, such as radar waveform information and radar timing parameters112. The radar scene information is used by the closed-loop radar return synthesizer106to understand the type and timing of radar signals that are used so that the closed-loop radar return synthesizer106can generate radar return information126. After receiving the radar scene information from the radar system102, the radar timing card118can process the radar timing parameters from the radar system102and provide them to the computer processor120. Based on the radar timing parameters the computer processor120generates radar return information126. Based on the radar timing parameters112, the radar timing card118can also generate a timing trigger124to enable a transmission of information from the DAC cards122a-122n. The timing trigger124can be based on a combination of the radar timing parameters112and the synchronous clock signal116.

The trigger distribution electronics204operates to distribute the timing trigger124to the DAC cards122a-122n. The trigger distribution electronics204a-204nor the DAC cards122a-122ncan also include configurable delay logic to adjust the DAC cards122a-122ntiming trigger124to the synchronous clock signal116sampling set-up time, such that receipt of the timing trigger124by the DAC cards122a-122nis deterministic without metastability. This ensures that the receipt of the timing trigger124by the DAC cards122a-122nis deterministic and does not vary by one or more synchronous clock signal116periods.

The computer processor120represents any suitable structure configured to receive radar timing information and process radar scene information and generate tasks. For example, the computer processor120can include or represent one or more processing devices, such as one or more microprocessors, microcontrollers, digital signal processors (DSPs), application specific integrated circuits (ASICs), GPUs, field programmable gate arrays (FPGAs), or discrete circuitry. In some embodiments, the computer processor120can include commercial-off-the-shelf (COTS) central processing units (CPUs), such as CPUs from INTEL or other manufacturer. Also, in some embodiments, the computer processor120can operate according to instructions stored in a memory. The memory can also store data associated with radar scene information and radar return information. The memory represents any structure(s) capable of storing and facilitating retrieval of information (such as data, program code, and/or other suitable information on a temporary or permanent basis). The memory may represent a random access memory or any other suitable volatile or non-volatile storage device(s).

The computer processor120use the radar timing parameters112and a three-dimensional physics model of a scene and combine the information to calculate radar return information126for the radar system102. The computer processor120operates to generate digitally-synthesized signals that make up the calculated radar return information126, including an aggregate of signal characteristics, such as Doppler frequencies, phases, and signal delays. The calculated radar return information126shows what the radar system102might “see” based on the radar scene information collected by the radar timing card118. The calculated radar return can include simple or highly-complex scenes, including one or more extended targets, clutter, one or more electronic attack (EA) effects, and the like. In some embodiments, the computer processor120has suitable processing power to generate radar return information126within the time of receipt of the radar timing parameters112and when the radar system102activates its receive window for real time computing.

The DAC cards122a-122noperate to convert the digitally-synthesized signals associated with the calculated radar return information126into analog signals that the radar system102can actually receive and process. Each DAC card122a-122nis associated with a group of corresponding radar channels128a-128hof the radar system102. That is, each DAC card122a-122ngenerates analog signals to be transmitted over a subset of the radar channels128a-128h. Each DAC card122a-122nrepresents any suitable structure configured to convert digital signals into analog signals. In some embodiments, each DAC card122a-122nincludes one or more GigaHertz-sample rate DACs, although other suitable DACs are possible and within the scope of this disclosure.

In some embodiments, the DAC cards122a-122ngenerate analog signals at an intermediate frequency (IF) for injection into an interface of the radar system102. As known in the art, IF is often utilized in radar systems when going from digital-to-analog in accordance with the super heterodyne principle. In the system100, instead of the DAC cards122a-122nconverting the digital signals to analog signals at a radio frequency (RF)—only to have a receiver at the radar system102convert the analog signal back to IF—the DAC cards122a-122ncan generate each analog signal at the IF. If necessary, any RF up-conversion, down-conversion, and propagation steps can be simulated computer processor120. Of course, generating analog signals at IF is merely one example implementation. In general, the system100is frequency-independent and can simulate radar return signals or other types of signals at any suitable frequency or frequencies.

The IF receiver110receives the IF analog signals carried over the radar channels128a-128hand operates to condition (such as by attenuation or amplification) each analog signal to better accommodate the specifications of the radar system102. For example, in some tests, the radar system102can exhibit limited dynamic range. In such cases, if the analog signals from the DAC cards122a-122nare too strong, the IF receiver110can attenuate the signals. Once the analog signals are received by the IF receiver110, the radar system102can process the analog signals, interpret the calculated radar return information126contained in the signals, and make any operational adjustments as needed. Operational changes by the radar system102may then be fed back to the radar timing card118in a real-time closed-loop manner. In some embodiments, the IF receiver110is the same interface that a radar antenna would connect to when the radar system102operates in a real-world environment (not during testing).

In some embodiments, the system100can perform timing and synchronization of signals via a waveform timing alignment technique. Using this technique, the system100can achieve waveform time alignment of less than ½ the DACs' sample clock period and phase alignment limited to the phase offset resolution of the DACs used, for the analog signals transmitted across the radar channels128a-128h.

Using the components shown inFIG. 1, the system100enables full operational test coverage of the radar system102. The system100provides much greater operational flexibility over conventional analog systems. Radar and kinematic scenarios can be easily updated in the system100via simple software or data updates. For example, the system100can be readily updated to add, change, or remove radar return signals associated with one or more scatterers, weather objects, clutter, EA effects, and the like (no hardware changes are needed). Calibration of the system100is simplified and can be performed in minutes. In contrast, in a conventional analog system, a new scene might require new racks of hardware to simulate and require weeks to calibrate. The system100is fully scalable both in the frequencies used and in the number of receiver channels. Components (such as the radar timing card118, computer processor120, DAC cards122a-122n, radar channels128a-128h, and the like) can be added or removed to scale the system100as needed.

AlthoughFIG. 1illustrates one example of a system100for performing a trigger to data synchronization of gigahertz digital-to-analog converters, various changes may be made toFIG. 1. For example, the system100may include any suitable numbers of processing devices, DAC cards and, radar timing cards. In general, the makeup and arrangement of the system100are for illustration only. Components may be added, omitted, combined, rearranged, or placed in any other configuration according to particular needs.

FIG. 2illustrates example GHz-sample rate DAC cards122a-122naccording to this disclosure. As shown inFIG. 2, the clock distribution electronics104, a radar timing card202, and a plurality of trigger distribution electronics204a-204nare used to support the DAC cards122a-122n. Each of the DAC cards122a-122nincludes a minimum of one of the following: rolling sync counter210, data delay logic212, value hold logic214, data framing logic216, DAC Interface218, optional data conditioning logic220, delay calibration offset logic222, DAC channel224, and DAC sample clock206.

In this example, the system clock108generated by the radar system102is a common clock source for the DAC cards122a-122n. This provides a synchronous system where all clock signals in a synthesized radar return system are derived from a single system clock synchronous to a radar system. Here, each DAC sample clock206operates at a much higher frequency than the frequency at which the FPGA226can operate, and a high-speed DAC interface218, such as an IEEE JESD interface or similar, is utilized. The FPGA226utilizes parallel, multi-sample wide parallel buses228to provide data to the DAC interface218as the required DAC sample rates.

The radar timing card202is configured to be coupled to the radar system102, such as via one or more cables or other suitable physical or wireless interface. The radar timing card202generally operates to collect radar timing parameters from the radar system102which are used to generate a trigger signal at the appropriate time to start the presentation of radar return information by the DAC cards122a-122n. The radar timing parameters are used to understand the type and timing of radar signals that are to be tested, which allows the system100to then generate suitable radar return data126at the correct time relative to the trigger signal.

The DAC cards122a-122nsample an external timing trigger124using the distributed synchronous clock signal116. Upon receipt of an external timing trigger124at a first clock frequency and provide data to initialized high-speed DAC channels224operating at a much higher clock frequency. Rolling sync counters210, data framing logic216, value hold logic214, data delay logic212frame high-speed DAC input interface data, and additional logic translates the receipt of the timing trigger124on the trigger signal clock domain230to a trigger to data output time that remains deterministic thru multiple clock domain crossings. The timing relation of the external timing trigger signal124to the value of a rolling sync counter210determines the amount of delay from trigger distribution electronics204a-204nthat is applied to the radar return information126for an entire dwell time, where the dwell time is an amount of time that a radar system collects data for a predetermined processing interval.

Trigger-to-output and output-to-output alignment can be achieved by pushing data to the DAC channels224in a deterministic way. The time represented by each DAC data frame is an integer multiple of a rate of the external timing trigger signal124. A repeating sync counter210is implemented at a rate of the trigger clock domain130and counts to a multiple of a rate of the external timing trigger signal124and a rate of the DAC sample clock signal206. When an external trigger occurs, the value of the counter is stored. The value of the timer is used to relate trigger “time” to DAC “sample time” and then generate a delay value, which is a number of samples to delay the data within a data frame.

The radar return information126provided to the DAC cards122a-122nis shifted, resulting in a timing delay of radar return information126linearly proportional to when the timing trigger124arrived relative to the sync counter210on all data frames for the radar return information126. For example, if the data arrives when the sync counter210is at a starting value, the resulting delay would be zero samples. If the timing trigger124arrives at the end of the sync count, the data would be delayed by close to a full data frame. This approach allows for synchronization and calibration across multiple DAC cards122a-122nand DAC channels224.

A test mode can be implemented in a manner that the sync counters210can be reset upon the receipt of the external timing trigger124. This synchronizes the sync counters210of all DAC cards122a-122n. The sync counter value when the timing trigger124is received can be stored, such as in a software-readable location. If the stored sync counter trigger values for multiple FPGAs or DAC cards122a-122nare different, the trigger delays to the system can be calibrated, such as by using external hardware. The process can be repeated until all FPGAs or DAC cards122a-122nhave a same sync count trigger values and their sync counters210are fully synchronized.

At that point, all DAC outputs from trigger-to-output would be fully deterministic. The timing from trigger-to-output is measured for each DAC channel output232. The DAC output-to-output alignment can then be adjusted by sample width increments implementing sample delay logic222within the DAC cards122a-122n, and sample period precision control can be achieved by shifting data within a data frame. Course precision can be achieved by simply inserting or deleting entire data words and using a first-in-first-out (FIFO) queue as an elastic buffer. The accuracy achieved with this approach is less than or equal to one half of a period of the DAC sample clock signal206, which is sufficient for most applications.

AlthoughFIG. 2illustrates one example of Giga Hertz—sample rate DAC cards122a-122n, various changes may be made toFIG. 2. For example, as discussed above, while each of the DAC cards122a-122nincludes various components and certain numbers of components, other embodiments may include different numbers of any or all of these components. In general, the makeup and arrangement of the Giga Hertz sample rate DAC cards122a-122nare for illustration only. Components may be added, omitted, combined, or placed in any other configuration according to particular needs. For example, many FPGAs utilize internal input and output delay logic. The adjustable signal delay204a-204ncould exist within the FPGA if the appropriate FPGA component is used.

FIG. 3illustrates an example of rolling sync counters on multiple digital-to-analog converter cards are synchronized with an external trigger according to this disclosure. As shown inFIG. 3, the processing of sync counters210inFIG. 2are synchronized.

In this example, the rolling sync counters210aand210brange from zero to fifteen. First, both DAC Cards are placed in a sync mode that enables the sync counters to be reset upon receipt of the trigger300. The sync counter210aand210bon each board is initially not synchronized; the count values302are not known to be the same values at any given time. Upon receipt of the trigger300, sync counters210aand210bon both DAC Cards are reset to the same value. The value of the sync counters210aand210bare latched upon receipt of the trigger300in an accessible memory location. The values upon receipt of the first trigger300amay not be the same. Upon receipt of the second trigger300bthe sync counters210aand210bare latched again in an accessible memory location. The values on all DAC cards122a-122ncan be compared to test for synchronicity. If the values are equal, the receipt of the triggers300for all boards are synchronized. If the values are not equal, the receipt of the triggers300for boards are not synchronized. The adjustable trigger distribution electronics204a-204ncan be adjusted such that the latched triggered sync counter values are identical for all DAC cards122a-122n. Additionally, the synchronization process can be repeated to test for trigger sample metastability, and the adjustable signal delays modified to optimize trigger to trigger signal clock domain setup time to remove any metastable effects. Once all the DAC card rolling sync counters210are synchronized the latched sync counter value upon receipt of the trigger can be used to adjust the data delay logic to achieve deterministic trigger to data output timing.

AlthoughFIG. 3illustrates one example of synchronizing rolling sync counters210, various changes may be made toFIG. 3. For example, different rolling sync counter ranges and values could be used. The rolling sync counter could utilize any repeating sequence with a fixed period. In general, the counting sequence and the relationship between receipt of trigger and the data being latched is for illustration only.

FIG. 4illustrates an example of how the logic maintain deterministic trigger to output data timing according to this disclosure. As shown inFIG. 4, the latched sync counter value is used to adjust the data delay logic to achieve deterministic trigger to data output timing.

In this example, the trigger clock domain period is 4 nanoseconds and the DAC sample clock period is 0.8 nanoseconds. The data frame size has been set to 80 DAC samples, and the data frame period has been set to 64 nanoseconds. Given these parameters, the sync clock has 16 values, 0 to 15, such that incrementing 16 times at a 4 nanosecond trigger clock domain period requires the data frame period of 64 nanoseconds. The relation between the trigger clock domain and DAC clock domain precision is the quotient of the 4 nanosecond trigger clock domain period divided by the 0.8 ns DAC sample clock period, resulting in a ratio of 5 DAC sample periods for every trigger clock domain period. The trigger clock domain periods are counted using the rolling sync counters210, which are used as the reference point for both trigger and DAC data.

Once the DAC cards122a-122nare powered up and DAC interfaces are initialized, the DAC cards122a-122nare always framing and output data. Prior to receipt of DAC data, and a trigger, the DAC cards122a-122noutput null data400. Upon receipt of the DAC data, the DAC cards122a-122ncan continue to output null data400until a trigger300is received. When a trigger300is received the rolling sync counter value is latched. The ratio of trigger clock domain period to DAC sample clock period is applied to the latched value402to determine the delay value404, in number of samples, applied to the start of valid DAC data. Because the DAC sample clock206is a much higher frequency than the FPGA226can support, the DAC data path is parallelized into multiple sample wide buses. In the example shown inFIG. 4, the data frame consists of 5 data vectors, 16 samples wide each, on a16sample wide data bus. The latched rolling sync counter value is 2, resulting in a data delay value404of 10 samples. The data delay value404and the DAC data are applied to the subsequent data frame. The start of valid DAC data406, S0 (sample0), begins after the 10 null samples, starting on the eleventh sample. If the trigger300occurs later in the data frame period408, the latched rolling sync counter value402will be greater, resulting in a proportional valid sample delay value404in the DAC sample data. The result is that the valid DAC data is always provided to the DAC one frame period408from the receipt of the trigger, plus fixed propagation delays from the DAC interface218to the DAC analog output232. In this example, the frame period408is 64 nanoseconds. Therefore, the valid DAC data is always output 64 nanoseconds after receipt of the trigger300, plus fixed total propagation delay from the input of the DAC interface218to the DAC analog output232. The delay values404from the input of the DAC interface218to the DAC output are fixed overall due to all clock domains being synchronous to the system clock108.

Once the trigger-to-data output timing is fixed, the delay calibration value and DAC (if available) can be utilized to adjust the delay of individual DAC channels224to align all channels in a multi-channel system across one or more DAC cards122a-122n.

AlthoughFIG. 4illustrates one example of obtaining a fixed and deterministic trigger to DAC data output timing relationship, various changes may be made toFIG. 4. For example, different rolling sync counter210ranges and values could be used. The rolling sync counter could utilize any repeating sequence with a fixed period. In general, the counting sequence and the relationship between receipt of trigger and the data being latched is for illustration only The data frame size, data frame rate, data bus sample wide, DAC sample clock period and trigger clock period can all be adjusted to obtain optimal performance per the system requirements.

This solution may be useful for real-time pulsed radar hardware-in-the-loop simulation. It is also scalable to any number of DAC cards122a-122nand DAC channels224, which support IF injection and RF chamber applications. For example, being able to provide triggered RF return data with a deterministic and controllable time delay may be needed for the accurate real-time hardware-in-the-loop testing of pulsed radar systems with variable CPI-to-CPI timing. One example of this type of technique is described in the Applicant's co-pending patent application Ser. No. 17/033,257, which is hereby incorporated by reference in its entirety. The trigger-to-data alignment solution for synchronizing multiple DAC systems is novel due to a scalable FPGA solution that does not require specialized card circuitry, phase delay of clocks, etc. The trigger-to-data alignment solution also achieves accuracy that is practical and sufficient for real-time hardware-in-the-loop radar simulations at RF and IF. Calibration can occur once per run and be automated in seconds.

FIG. 5illustrates an example method500for performing a trigger to data synchronization of gigahertz digital-to-analog converters according to this disclosure. For ease of explanation, the method500is described as being performed using the system100ofFIG. 1. However, the method500may be used with any other suitable device or system.

As shown inFIG. 5, radar timing information and a synchronous clock signal are received step502. This may include, for example, a closed-loop radar return synthesizer106receiving radar timing parameters112from a radar system102. The radar timing parameters112can include information related to a radar pulse generated and sensed by the radar system102. This may also include the closed-loop radar return synthesizer106receiving a synchronous clock signal116. For instance, the radar system102may operate a system clock108that produces a system clock signal114, which is output to clock distribution electronics104. The clock distribution electronics104can convert the system clock signal114into the synchronous clock signals116and DAC sample clock signals. The synchronous clock signal116can be simultaneously transmitted to a radar timing card118and multiple DAC cards122a-122nof the closed loop radar return synthesizer106.

Radar return information is calculated using the computer processor120generating radar return information126, which is based on the information processed from the radar timing parameters112, at step504. The radar return information is divided into dedicated portions for DAC cards using the at the computer processor120at step506. This may include, for example, the computer processor120dividing the radar return information126in any suitable manner, such as temporally or by amount of data.

A timing trigger is generated to indicate a time of transmission for the radar return information using a radar timing card at step508. This may include, for example, generating the timing trigger124based on the radar timing parameters112received from the radar system102. The timing trigger124can indicate a current time or a future time for transmission of the radar return information126. The timing trigger is aligned for each DAC card using delay controls at step510. This may include, for example, using the trigger distribution electronics204a-204n(which are located on transmission paths for the timing trigger124), where each trigger distribution electronics204a-204ncorresponds to one of the DAC cards122a-122n. Parallel data is framed based on a trigger-to-data frame timing using a sync counter on each of the DAC cards at step512. Here, the trigger-to-data frame timing aligns frames used to transmit the radar return information126. Channel-to-channel alignment is performed on parallel data paths using adjustable delay logic at step514. This may include, for example, using the adjustable delay logic212to ensure that each DAC channel224transmits the dedicated portion of the radar return information126in unison across the multiple DAC cards122a-122n. The dedicated portion of the radar return information126is transmitted over each of the DAC channels at step516. Here, the radar return information126is simultaneously transmitted on each of the DAC channels224with a controlled and deterministic trigger to output delay.

AlthoughFIG. 5illustrates one example of a method500for generating a trigger to data synchronization of gigahertz digital-to-analog converters, various changes may be made toFIG. 5. For example, while shown as a series of steps, various steps shown inFIG. 5may overlap, occur in parallel, occur in a different order, or occur multiple times. Moreover, some steps may be combined or removed and additional steps may be added according to particular needs.

FIG. 6illustrates an example device600for performing a trigger to data synchronization of gigahertz digital-to-analog converters according to this disclosure. One or more instances of the device600(or portions thereof) may, for example, be used to at least partially implement the functionality of the system100ofFIG. 1. However, the functionality of the system100may be implemented in any other suitable manner.

As shown inFIG. 6, the device600denotes a computing device or system that includes at least one processing device602, at least one storage device604, at least one communications unit606, and at least one input/output (I/O) unit608. The processing device602may execute instructions that can be loaded into a memory610. The processing device602includes any suitable number(s) and type(s) of processors or other devices in any suitable arrangement. Example types of processing devices602include one or more microprocessors, microcontrollers, DSPs, ASICs, GPUs, FPGAs, or discrete circuitry.

The memory610and a persistent storage612are examples of storage devices604, which represent any structure(s) capable of storing and facilitating retrieval of information (such as data, program code, and/or other suitable information on a temporary or permanent basis). The memory610may represent a random access memory or any other suitable volatile or non-volatile storage device(s). The persistent storage612may contain one or more components or devices supporting longer-term storage of data, such as a read only memory, hard drive, Flash memory, or optical disc.

The communications unit606supports communications with other systems or devices. For example, the communications unit606can include a network interface card or a wireless transceiver facilitating communications over a wired or wireless network. The communications unit606may support communications through any suitable physical or wireless communication link(s).

The I/O unit608allows for input and output of data. For example, the I/O unit608may provide a connection for user input through a keyboard, mouse, keypad, touchscreen, or other suitable input device. The I/O unit608may also send output to a display or other suitable output device. Note, however, that the I/O unit608may be omitted if the device600does not require local I/O, such as when the device600can be accessed remotely or operated autonomously.

In some embodiments, the instructions executed by the processing device602can include instructions that implement all or portions of the functionality of the system100described above. For example, the instructions executed by the processing device602can include instructions for performing a trigger-to-data synchronization of gigahertz digital-to-analog converters as described above.

AlthoughFIG. 6illustrates one example of a device600for performing a trigger to data synchronization of gigahertz digital-to-analog converters, various changes may be made toFIG. 6. For example, computing devices and systems come in a wide variety of configurations, andFIG. 6does not limit this disclosure to any particular computing device or system.