Integrated circuit with offset pins

The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means. Since every second connecting pin (12) is not bent inward immediately before insertion of the connecting pins (11,12), no subsequent corrective alignment of the offset connecting pins (11, 12) is required.

This application is a 371 of PCT/EP02/68369 Jul. 26, 2002.

BACKGROUND OF THE INVENTION

The invention relates to the field of semiconductor packaging and testing, and in particular to mounting an integrated circuit that has been tested on a board, wherein the adjacent connecting pins of the integrated circuit are in an inline arrangement.

In order to keep the dimensions small for the package of a chip with multiple connecting pins (e.g., 88 pins), the connecting pins are arranged in line as close as possible. However, a minimum spacing must still be maintained since the space between associated holes on a board for insertion of the connecting pins may not be arbitrarily reduced. As the spacing of the holes and conducting lines on the board becomes closer, the process of fabricating a board becomes more complex and expensive. In addition, there is the risk that close spacing of the holes on the board will cause the connecting pins to short out during the soldering process.

One technique for increasing hole spacing on the board is to configure the connecting pins of the package by bending some of the connecting pins or, for example, by inwardly offsetting every second connecting pin. However, the advantage of greater hole spacing on the board is counteracted by the disadvantages of requiring a special test socket to test the chips and requiring an expensive packaging mechanism. Specifically, the packaging mechanism must be designed such that the connecting pins are not bent out of their precise alignment.

Therefore, there is a need for a method of testing and mounting the package on a board in such a way that simple and inexpensively produced test sockets are sufficient for testing, and similarly simple and inexpensively produced packaging mechanisms are sufficient for packaging, while at the same time achieving an offset arrangement for the connecting pins.

SUMMARY OF THE INVENTION

Briefly, according to an aspect of the invention, an integrated circuit that includes a die mounted within a package containing a plurality of input/output pins is tested by placing the integrated circuit into a test socket of automatic test equipment. Prior to the tested integrated circuit being mounted on a board, a portion of the plurality of input/output pins are bent from their inline position to an offset position.

The integrated circuit with its inline connecting pins is inserted into a test socket for testing. At least one connecting pin is bent inward using a bending tool immediately before insertion of the connecting pins of the integrated circuit into the holes of the board, in order to achieve an offset arrangement of the connecting pins.

The integrated circuit includes inline connecting pins (i.e., individuals skilled in the art frequently use the expression “dual inline”), and the integrated circuit is tested in this state. The integrated circuit to be tested is inserted into a test socket. A first advantage is that relatively inexpensive tests sockets may be utilized to test the chips. A second advantage is that even inexpensive packaging mechanisms are sufficient for storing and transporting the chips. Additionally, at least one connecting pin, preferably every second connecting pin, is bent inward by the bending tool immediately before insertion of the connecting pins of the integrated circuit into the board in order to form an offset arrangement of the connecting pins. The invention thus combines the advantages of a package in which its connecting pins are in an inline arrangement with those of a package in which its connecting pins are in an offset arrangement.

Electrical testing of the chip may thus be of a simple design since inexpensively produced test sockets are sufficient for the task. In addition, standard packaging mechanisms may be employed to package the package. Subsequent alignment of the connecting pins is simplified since the connecting pins are not bent into the offset arrangement until immediately before insertion into the board, rather than at the fabrication stage of the package.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1Ais a flow chart illustration of a method100for testing an integrated circuit, bending the pins of the integrated circuit and mounting the integrated circuit.FIGS. 1B–1Fare simplified sectional views of the integrated circuit during the steps illustrated inFIG. 1A.

Referring toFIGS. 1A–1F, in step102inline connecting pins1of an integrated circuit that includes a die (not shown) and a package2containing the die, are input to a test socket3as shown inFIG. 1B. In step104, any rework that may be required on the package2or the chip is performed. The package2is then placed in a packaging mechanism such as a guide brace4and shipped in step106. Immediately before the package2is mounted on a board5, every second connecting pin12, for example, is bent inward by a bending tool6, while the remaining connecting pins11are left unmodified. The connecting pins11and12are inserted into associated holes71–72of the board5, preferably, by the bending tool6.

FIG. 2is a top view illustration of the package2, along with the connecting pins11and12, and with the bending tool6attached.

FIG. 3is a front view illustration of the package2with the connecting pins11and12, and with the bending tool12attached. Every second connecting pin12is bent inward, while the remaining connecting pins11remain bent outward or are oriented vertically, as is the case during fabrication of the package2.

FIG. 4is a front view of the package2, with the first connecting pins11bent outward and the second connecting pins12bent inward, including dimensional details. The spacing between the vertical pins on the package is 19.05 mm. The second connecting pins12are bent 0.4 mm inward from the vertical, while the first or remaining connecting pins11are bent 0.87 mm outward.

FIG. 5is a section of the board5having first holes71for the outwardly bent first connecting pins11, and second holes72for the inwardly bent second connecting pins12. The first and second holes71and72are offset relative to each other by 1.27 mm. The spacing of the inline holes71and72is 2.54 mm. The spacing between two offset holes71and72is chosen as 1.8 mm.

The connecting pins on the package may be arranged symmetrically relative to the longitudinal center axis and the transverse center axis of the package since this symmetrical arrangement allows for the use of a symmetrical bending tool. It is then irrelevant how the bending tool is placed on the package. It is impossible to bend the connecting pins incorrectly by attaching the bending tool with the improper orientation.

The method according to the invention permits the use of packaging mechanisms suitable for the standard PSDIP package. No special packaging mechanisms are required.

While the above figures describe an approach in which every second connecting pin is bent inward once,FIG. 6illustrates another possibility. With this possibility, every second pin12is bent 90° downward, relative to the package. Every intermediate pin11, on the other hand, is first bent downward by less than 90° relative to the package, for example, by 45°, then subsequently bent by an additional angle, for example, 45°.