Chip package with near-die integrated passive device

A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.

TECHNICAL FIELD

Embodiments of the present invention generally relate to a chip package having a near-die integrated passive device, and in particular, to a chip package having an integrated passive device disposed between a redistribution layer and an integrated circuit die of the chip package.

BACKGROUND

Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems, automated teller machines, data centers, artificial intelligence system, and machine learning systems among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a package substrate, often in conjunction with a through-silicon-via (TSV) interposer substrate, to enable a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies are mounted to a die side (i.e., top surface) of the package substrate while a ball side (i.e., bottom surface) of the package substrate is mounted to a printed circuit board (PCB). The IC dies may include memory, logic or other IC devices.

Decoupling capacitors are often used in chip packages to provide stable power to the circuitry of the IC dies utilized in the chip package. Conventionally, decoupling capacitors are mounted on the top and/or bottom surface of the package substrate. However at high frequencies, power and ground routings with the package substrate can impact the functional performance of the IC dies of the chip package due to its intrinsic inductance and resistance which detrimentally effect decoupling efficiency, and ultimately, the performance of the power delivery network. Instability of the power delivery network consequently diminishes the performance of IC dies of the chip package.

Therefore, a need exists for a chip package with improved capacitive decoupling in power delivery networks.

SUMMARY

A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.

In one example, a chip package is provided that includes an integrated circuit (IC) die, a package substrate, an integrated passive device (IPD) layer, a dielectric interconnection layer, and an integrated passive device (IPD). The package substrate includes a die side and a ball side. The package substrate has build-up layers disposed on a core. Package circuitry includes routings terminating on the top and bottom surfaces of the package substrate, the routing passing through the build-up layers and core. The IPD layer includes conductive posts coupled to pillars extending below the IC die. The dielectric interconnection layer is disposed between the IC die and the build-up layers. The dielectric interconnection layer includes pillars posts coupled to the conductive posts of the IPD layer. The IPD is disposed between the IC die and the package substrate. The IPD has at least one terminal electrically coupled to the IC die.

In another example, a chip package is provided that includes an integrated circuit (IC) die, a package substrate, an integrated passive device (IPD) layer, a dielectric interconnection layer, and an integrated passive device (IPD). Package circuitry includes routings terminating on the top and bottom surfaces of the package substrate, the routing passing through the build-up layers and core. The IPD layer includes conductive posts coupled to pillars extending below the IC die. The dielectric interconnection layer is disposed between the IC die and the build-up layers. The dielectric interconnection layer includes conductive pillars coupled to the conductive posts of the IPD layer. The IPD is disposed between the IC die and the package substrate. The IPD is a capacitor that has a first terminal coupled to circuitry of the IC die and a second terminal coupled to the circuitry of the IC die.

In another example, the first terminal of the capacitor is coupled to power delivery circuitry of the IC die and the second terminal of the capacitor is coupled to the ground circuitry of the IC die.

The capacitor may be coupled directly to circuitry of the IC die. Alternatively, the capacitor may be coupled to circuitry of the IC die through conductive posts of the IPD layer.

In yet another example, a method for fabricating a chip package is provided. The method includes sandwiching an integrated passive device (IPD) between an integrated circuit (IC) die and an IPD layer; and stacking the IPD layer with a package substrate. The method defines power supply circuitry from circuitry of the package substrate, through conductive posts of the IPD layer, to circuitry of the IC die. The method also defines ground circuitry from the circuitry of the package substrate, through conductive posts of the IPD layer, to the circuitry of the IC die. The method also couples the IPD to the power supply circuitry and the ground circuitry though the circuitry of the IC die, or through the conductive posts of the IPD layer.

In one example, the method includes forming a plurality of dummy posts between the IPD and the package substrate.

In another example, the method includes connecting the IPD to the IC die prior to connecting the IPD layer to the IC die.

In another example, the method includes connecting the IPD to the IC die after connecting the IPD layer to the IC die.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.

DETAILED DESCRIPTION

Disclosed herein is a chip package and method for fabricating the same that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit (IC) die of a chip package. Positioning the integrated passive device on the IC die side of the chip package places the integrated passive device much closer to the IC die as compared to conventional designs. In that manner, communication speeds and reliability improve. Additionally, parasitic losses that occur in conventional routing of the integrated passive device to the IC die through the package substrate are beneficially eliminated.

In an example using a decoupling capacitor as the integrated passive device disposed between the package substrate and the IC die, the loop inductance between the decoupling capacitor and the IC die may improve by 8 or more percent. In some example, the loop inductance improved in excess of 30 percent. Additionally, significant improvements in the AC droop are also realized.

Beneficially, the configuration and techniques described above and further detailed below provide robust chip package with improved performance and reliability. Furthermore, the techniques described herein may be employed with little cost impact to the fabrication and assembly of the chip package.

Turning now toFIG.1A, a schematic sectional view of a chip package100is illustrated. The chip package100includes an integrated passive device (IPD)102, at least one integrated circuit (IC) die104, an integrated passive device (IPD) layer116, a dielectric interconnection layer118and a package substrate128. The dielectric interconnection layer118and IPD layer116are disposed between the package substrate128and the IC die104, and facilitates data, power and ground communication therebetween. The IC die104is disposed on the IPD layer116, and the IPD layer116is disposed on the package substrate128. An under die layer108is disposed between the IC die104and the IPD layer116, and includes pillars110for making electrical connection therebetween. The dielectric interconnection layer118is disposed between the IPD layer116and the package substrate128, and includes pillars120for making electrical connection therebetween. The chip package100may be mounted on a printed circuit board (PCB)136to form an electronic device180.

The IPD102is disposed in the IPD layer116between the IC die104and the dielectric interconnection layer118, thus making the IPD102near the IC die104rather than beginning electrically separated from the IC die104by the package substrate128as found in conventional designs. Stated differently, the IPD102is disposed in the IPD layer116between the IC die104and the closest fanout of electrical routing residing in the package substrate120or other layer disposed between the IPD102and package substrate120, such as a redistribution layer or the like. Thus making the IPD102near the IC die104rather than beginning electrically separated from the IC die104by a routing fanout.

The IPD102is a discrete, pre-formed device that is fully fabricated prior to attachment directly to the IC die104or indirectly to the IC die104through to the IPD layer116and/or dielectric interconnection layer118. Some non-exhaustive examples of an IPD102that may be disposed between the dielectric interconnection layer118and the IC die104include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others. Although in the example described with reference toFIG.1AthroughFIG.3below the IPD102is described as a decoupling capacitor, other types of IPDs may be utilized in the chip package100.

Continuing to refer toFIG.1A, the IC die104of the chip package100includes die circuitry106. The die circuitry166may include block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. The IC die104may be, but is not limited to, programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, such as high band-width memory (HBM), optical devices, processors or other IC logic structures. The IC die104may optionally include optical devices such as photo-detectors, lasers, optical sources, and the like. In the example ofFIG.1A, the IC die104is a logic die having math processor (also known as math engine) circuitry for accelerating machine-learning math operations in hardware, such as self-driving cars, artificial intelligence and data-center neural-network applications.

Optionally, the at least one IC die104may be a plurality of IC dies104. When a plurality of IC dies104are utilized, the IC dies104may be disposed in a vertical stack and/or disposed laterally side by side. It is contemplated that the IC dies104comprising the plurality of IC dies104may be the same or different types. Although only one IC die104is shown inFIG.1A, the number of IC dies104disposed in the chip package100may vary from one to as many as can fit within the chip package100.

Pillars110are formed on the contact pads exposed on the die bottom surface152of the IC die104. The pillars110are mechanically and electrically connected to conductive posts174formed in the IPD layer116. At an appropriate time during fabrication of the chip package100, the interstitial space around the pillars110may be filled with an underfill material112. The underfill material112as a top surface154in contact with the die bottom surface152of the IC die104and a bottom surface156bounded by the IPD layer116. Together, the pillars110and the underfill material112form the under die layer108. Generally, the pillars110are formed on the IC die104prior to connecting the IC die104with the IPD layer116, while the underfill material112is disposed around the pillars110at a later fabrication step. The pillars110form interconnect circuitry114of the under die layer108that connect the die circuitry106and the conductive posts174of the IPD layer116.

In one example, the pillars110are formed by plating copper on the conductive contact pads formed on the die bottom surface152of the IC die104. In other example, the pillars110may be formed using other suitable conductive material. The pillars110are also exposed through the bottom underfill surface156of under die layer108and are in contact with the conductive posts174exposed through the a top surface158of the IPD layer116that surrounds the IPD102. Optionally, die level mold compound138may be disposed on the sides to the IC die102, the interconnect layer110and the IPD layer116, to enhance securing of the IC die104within the chip package100and to facilitate handling during fabrication.

The IPD layer116includes the top surface158and a bottom surface160. The IPD layer116includes a plurality of conductive posts174disposed in a dielectric material172. The dielectric material172may be polyimide or other suitable polymer. The conductive posts174may be plated metal, such as copper, a metal filled or coated via, solder paste or other electrically conductive material suitable for signal transmission. The conductive posts174may be disposed in a hole formed through the dielectric material172, or alternatively, the conductive posts174may be formed on the pillars110then subsequently surrounded by the dielectric material172. The conductive posts174are formed through the IPD layer116and connect the pillars110of the under die layer108to the pillars120of the dielectric interconnection layer118. The dielectric material172also surrounds the IPD102to help secure the IPD102to the under die layer108and/or the IC die104. The bottom surface160of the dielectric material172may be planarized or be made flat to provide a good mounting surface for the dielectric interconnection layer118.

The dielectric interconnection layer118includes a plurality of conductive pillars120which form the circuitry of the interconnection layer118. In one example, each pillar120is plated or otherwise formed on a respective one of the conductive posts174. The pillars120are separated by a dielectric material, such as with underfill material198. The pillars120and underfill material198form the dielectric interconnection layer118. The pillars120are coupled through the DL top surface162of the dielectric interconnection layer118to the conductive posts174of the IPD layer116, which in turn are coupled to the pillars110extending from the IC die104. The pillars120are also coupled through a dielectric layer (DL) bottom surface164of the dielectric interconnection layer118to package circuitry182formed in the package substrate128.

In one example, the connected pillars110, pillars120and posts174are linearly aligned such that the electrical routings of the formed by the respectively coupled pillars110,120, and posts174passes essentially straight (i.e., linearly) from the package substrate128to the IC die104in a direction perpendicular to the top and bottom surfaces162,164of the dielectric interconnection layer118. Moreover, the coupled pillars110,120, and posts174are closer to the IC die104than any fanout of routing below the IPD102within the chip package100, such as fanouts within the package substrate128or redistribution layer (190shown inFIG.1B). In such an example, the routing through the pillars110,120, and posts174has minimal resistance and parasitic inductance, thus enhancing the performance of the chip package100.

In the main example depicted inFIG.1A, the IPD102is disposed between the DL top surface162of the dielectric interconnection layer118and bottom of the pillars110extending from the IC die104. In the enlarged detail depicted in depicted inFIG.1A, the IPD layer116includes a space126in which at least a portion of the IPD102resides. For example, a portion of the IPD102may be overlapped with the dielectric interconnection layer118and/or under die layer108, in addition to being overlapped with the IPD layer116. In other examples, the IPD102is disposed completely within the space126, such that the IPD102is completely overlapped by the IPD layer116. In the enlarged example, IPD routing176defined between the IPD102and the IC die104may be optionally formed using a conductive post122, terminating at that IPD102, that is coupled by a conductive jumper124to one of the conductive posts174residing in the IPD layer116. Alternatively, the conductive jumpers124may reside in the dielectric interconnection layer118(as illustrated inFIG.3).

The space126may be a break in the IPD layer116such that there is nothing filling the space126between the dielectric interconnection layer118and under die layer108except for the IPD102. In other examples, a portion of the dielectric material forming the dielectric interconnection layer118is missing proximate the DL top surface162such that the space126is formed at least partially in the dielectric interconnection layer118. The space126may also be filled with a potting compound to secure the IPD102in the space126.

Optionally, dummy posts178may be disposed in the dielectric interconnection layer118between the IPD102and the package substrate128. The dummy posts178are spaced commensurate with the other conductive posts174of the dielectric interconnection layer118to balance the amount of metal across the width of the dielectric interconnection layer118and chip package100which mitigates warpage and distortion. The dummy posts178may be fabricated as described above with reference to the conductive posts174. In one example, some or all of the dummy posts178are floating in that there is no signal, power or ground connection through the dummy posts178to the IPD102. In yet another example, the dummy posts178are grounded. In another example, one or more of the conductive posts174may be disposed in the dielectric interconnection layer118between the IPD102and the package substrate128to provide one or more of signal, power or ground connection directly to the IPD102from the package substrate128.

The DL bottom surface164of the dielectric interconnection layer118is disposed on a package top surface166of the package substrate128. The pillars120are exposed to the DL bottom surface164such that the pillars120may be electrically coupled to the package circuitry182terminating at a package top surface166of the package substrate128. In this manner, the pillars120are electrically coupled to and communicates with the package circuitry182of the package substrate128.

Alternatively as depicted inFIG.1B, a redistribution layer (RDL)190may be disposed between the DL bottom surface164of the dielectric interconnection layer118and the package top surface166of the package substrate128. The chip packages100depicted inFIG.1AandFIG.1Bare essentially identical except for the presence of the RDL190. The pillars120are electrically coupled to the package top surface166of the package substrate128by RDL circuitry192formed in the RDL190.

The RDL190includes a plurality of conductive layers and vias which are patterned to form the RDL circuitry192. The conductive layers and vias are separated by dielectric layers. There can be between two to seven patterned conductive layers forming the RDL circuitry192. The RDL circuitry192couples the pillars120formed through the dielectric interconnection layer118to the package circuitry182formed in the package substrate128.

In one example, the plurality of conductive layers and vias are patterned such that the routings of the RDL circuitry192fans out in a direction perpendicular to the RDL top and bottom surfaces194,196of the RDL190.

Returning back toFIG.1A, the package substrate128generally includes at least an upper build up layer130disposed on a core132. Optionally, a lower build up layer134may be disposed on the other side of the core132from the upper build up layer130. The upper build up layer130includes a plurality of conductive layers and via that are patterned to provide routing of a portion of the package circuitry182. One end of the package circuitry182formed in the upper build up layer130terminates at the package top surface166where the package circuitry182connects to the pillars120of the dielectric interconnection layer118. The other end of the package circuitry182formed in the upper build up layer130terminates at vias formed through the core132. The lower build up layer134may be fabricated similar to the upper build up layer130. At least one of the upper and lower build up layers130,134includes a fanout in the circuitry182of the package substrate128.

In examples where the package substrate128does not include a lower build up layer134, the vias formed through the core132of the package circuitry182may be connected by solder balls140to circuitry142of the PCB136that terminates at a PCB top surface170of the PCB136. In examples having a lower build up layer134, the vias formed through the core132are coupled through the patterned conductive layers and vias of lower build up layer134such that the package circuitry182terminates at a package bottom surface168. At the package bottom surface168, the package circuitry182is coupled to the circuitry142of the PCB136by the solder balls140.

Thus, routing is formed through the chip package100that allows the circuitry142of the PCB136to communicate with the die circuitry106of the IC die104. The routings allow power, ground and date to be communicated between the IC die104and the PCB136. The routings generally provide an electrically conductive path through the package circuitry182, the pillars120of the dielectric interconnection layer118, the conductive posts174of the interconnect circuitry114, and the pillars110coupled to the die circuitry106of the IC die104. The pillars120of the dielectric interconnection layer118, the conductive posts174of the interconnect circuitry114, and the pillars110are linearly aligned for fast signal transmission and low power loss. The configuration of the IPD layer116and dielectric interconnection layer118allow the IPD102to be located near the IC die104relative routing fanouts within the chip package100(that are not within the IC die104). Some of the routings include the IPD routing176. In some instance, the IPD routings176extend directly from the IPD102and the die circuitry106of the IC die104without passing through the dielectric interconnection layer118. In other examples, the IPD routings176extend directly between the IPD102and at least one or both of the pillars120of the dielectric interconnection layer118or the conductive posts174of the IPD layer116. In some examples such as when the IPD102is configured as a decoupling capacitor, the IPD routings176extend directly between the IPD102and pillars120of the dielectric interconnection layer118such that the IPD102is coupled in parallel to the die circuitry106of the IC die104. Exemplary circuit diagrams illustrating some of these examples are provided below with reference toFIGS.2and3.

FIG.2is a schematic circuit diagram200of a chip package100illustrating one example of the connections between an integrated passive device (IPD)102, an integrated circuit (IC) die104, an integrated passive device (IPD) layer116, a dielectric interconnection layer118and a package substrate128. The chip package100may be configured as described above, or have another configuration that includes the IPD102disposed between the dielectric interconnection layer118and the IC die104. Although in the example depicted inFIG.2, the IPD102is illustrated as a decoupling capacitor disposed in a power delivery network, the IPD102may be configured as another type of passive device.

As depicted inFIG.2, power (PWR) and ground (GND) are coupled to the package circuitry182of the package substrate128from the PCB136through solder balls140. The PCB136is not illustrated inFIG.2, and the solder balls140are shown with dashed lines.

PWR is connected to a die power contact pad204through the pillars110,120formed in the under die layer108and the dielectric interconnection layer118, and the conductive posts174formed in the IPD layer116. Similarly, GND is connected to a ground power contact pad204through the pillars110,120formed in the under die layer108and the dielectric interconnection layer118, and the conductive posts174formed in the IPD layer116. As described above, the routing through each interconnected set of pillars110,120and posts110is linear (i.e., straight and aligned). The die power contact pad204and the ground power contact pad204are formed on the die bottom surface152of the IC die104, and coupled to functional circuitry206residing in the die circuitry106of the IC die104. The functional circuitry206is the circuitry of the IC die104that carries out the function of the die. For example, the functional circuitry206may be logic circuits, memory circuits or other functional circuit.

A power node208is defined in the die circuitry106within the die body148. The power node208is coupled to the die power contact pad202, the functional circuitry206and a power die-IPD contact pad212. The power die-IPD contact pad212is also formed on the die bottom surface152of the IC die104. The power die-IPD contact pad212is coupled to an IPD power terminal216formed on the IPD102.

Similarly, a ground node210is defined in the die circuitry106within the die body148. The ground node210is coupled to the die ground contact pad204, the functional circuitry206and a ground die-IPD contact pad214. The ground die-IPD contact pad214is also formed on the die bottom surface152of the IC die104. The ground die-IPD contact pad214is coupled to an IPD ground terminal218formed on the IPD102.

In the example depicted inFIG.2, the IPD power and ground terminals216,218are coupled to opposite plates forming the decoupled capacitor of the IPD102. The IPD power and ground terminals216,218are coupled in parallel to the functional circuitry206of the IC die104. Thus, the IPD102functions to provide voltage stable power to the functional circuitry206of the IC die104. Additionally, as the IPD102is immediately proximate the IC die104, and connected to the functional circuitry206of the IC die104without having to be routed through the circuitry182of the package substrate128, the performance of the IC die104is enhanced.

Optionally, one or more decoupling capacitors220may be coupled to the top and/or bottom of the package substrate128. The decoupling capacitor220is coupled on parallel with IPD power and ground terminals216,218to the functional circuitry206of the IC die104.

FIG.3is a schematic circuit diagram300of a chip package100illustrating another example of the connections between an integrated passive device (IPD)102, an integrated circuit (IC) die104, an integrated passive device (IPD) layer116, an integrated passive device (IPD) layer118and a package substrate128. The chip package100may be configured as described above, or have another configuration that includes the IPD102disposed between the dielectric interconnection layer118and the IC die104. Although in the example depicted inFIG.3, the IPD102is again illustrated as a decoupling capacitor disposed in a power delivery network, the IPD102may be configured as another type of passive device.

As depicted similarly inFIG.2, power (PWR) and ground (GND) are coupled to the package circuitry182of the package substrate128from the PCB136through solder balls140. The PCB136is not illustrated inFIG.3, and the solder balls140are shown with dashed lines.

PWR is connected to a die power contact pad204through the pillars110,120formed in the under die layer108and the dielectric interconnection layer118, and the conductive posts174formed in the IPD layer116. Similarly, GND is connected to a ground power contact pad204through the pillars110,120formed in the under die layer108and the dielectric interconnection layer118, and the conductive posts174formed in the IPD layer116. As described above, the routing through each interconnected set of pillars110,120and posts110is linear (i.e., straight and aligned). The die power contact pad204and the ground power contact pad204are formed on the die bottom surface152of the IC die104, and coupled to functional circuitry206residing in the die circuitry106of the IC die104.

A power node302is defined within one of the dielectric interconnection layer118or the IPD layer116, for example using conductive posts122and jumpers124to connect the IPD102to one of the pillars120or conductive post174. The power node302is coupled to the die power contact pad202(which is connected to the functional circuitry206of the IC die104), the package circuitry182and an IPD power terminal216.

Similarly, a ground node304is within one of the dielectric interconnection layer118or the IPD layer116, for example using conductive posts122and jumpers124to connect the IPD102to one of the pillars120or the conductive posts174. The ground node304is coupled to the die ground contact pad204(which is connected to the functional circuitry206of the IC die104), the package circuitry182and an IPD ground terminal218.

Similar to the example depicted inFIG.2and described above, the IPD power and ground terminals216,218shown inFIG.3are coupled to opposite plates forming the decoupled capacitor of the IPD102. The IPD power and ground terminals216,218are coupled in parallel to the functional circuitry206of the IC die104. Thus, the IPD102functions to provide voltage stable power to the functional circuitry206of the IC die104. Additionally, as the IPD102is immediately proximate the IC die104, and connected to the functional circuitry206of the IC die104without having to be routed through the circuitry182of the package substrate128, the performance of the IC die104is enhanced.

FIG.4is a flow diagram of a method400for fabricating a chip package100having an integrated passive device (IPD)102, an integrated circuit (IC) die104, an integrated passive device (IPD) layer116, a dielectric interconnection layer118, and a package substrate128. The method400may also be utilized for fabricate other chip packages that include an IPD102disposed between an IC die104and a package substrate128.

The method400begins at operation410by sandwiching an IPD102between an IC die104and an IPD layer116. The IPD102may be connected to the IC die104before or after the IPD102is coupled to the IPD layer116. In one example when sandwiching the IPD102between the IC die104and the IPD layer116, the IPD routings176are directly coupled to the IC die104without passing through the IPD layer116. In another example when sandwiching the IPD102between the IC die104and the IPD layer116, the IPD routings176are indirectly coupled to the IC die104by first passing through the IPD layer116or other layer below the IPD102to the IC die104. From the end of the pillars110contacting the IC die104, to the end of the conductive posts174exposed through the bottom surface160of the IPD layer116, the electric routing coupled to the IC die104does not include a fanout.

During one example of operation410, the IPD102may be first coupled to the IC die104prior to being sandwiched by the IPD layer116. During another example of operation410, the IPD102may be first coupled to the IPD layer116prior to being sandwiched against the IC die104.

During one example of operation410, the IPD102may be disposed completely between the top surface158of the IPD layer116and the IC die104. During another example of operation410, the IPD102may be disposed at least partially in a space126formed in the IPD layer116, such that a portion of the IPD102is overlapped with the top surface158of the IPD layer116. During yet another example of operation410, the IPD102may be completely disposed in the space126formed in the dielectric interconnection layer118, such that the entire IPD102is overlapped with the dielectric interconnection layer118below the DL top surface162.

At operation420, the stacked assembly comprising the IC die104and the IPD layer116is stacked with a package substrate128. The stacking of the IPD layer116and the package substrate128at operation420may occur before or after the IPD sandwiching operation410. At operation420, pillars120of the dielectric interconnection layer118are electrically and mechanically coupled to the package circuitry182. After the pillars120are coupled to the package circuitry182of the package substrate128, underfill material198is dispensed between the pillars120to form the dielectric interconnection layer118.

After completion of operations410,420, power supply circuitry is defined from the circuitry182of the package substrate128, through the pillars120,174of the dielectric interconnection layer118and the IPD layer116, to the circuitry106of the IC die104. Similarly, ground circuitry is defined from the circuitry182of the package substrate128, through the pillars120,174of the dielectric interconnection layer118and the IPD layer116, to the circuitry106of the IC die104. Although not shown inFIG.3, the power and ground circuitries pass through the pillars110when passing between the IPD layer116and the IC die104.

Additionally after completion of operations410,420, the IPD102is coupled to the power supply circuitry and the ground circuitry formed though the circuitry of the chip package100. In one example, the power and ground terminals216,218of the IPD102are coupled to the power supply circuitry and the ground circuitry directly to the IC die104without passing through the pillars120of the dielectric interconnection layer118or the package substrate128. In another example, the power and ground terminals216,218of the IPD102are coupled to the power supply circuitry and the ground circuitry within the dielectric interconnection layer118and/or IPD layer116using jumpers as described above, prior to connecting to the IC die104. From the end of the pillars110contacting the IC die104, to the end of the pillars120of the dielectric interconnection layer118, the electric routing coupled to the IC die104does not include a fanout.

Although process flow of the method400depicts the IPD102as a decoupling capacitor coupled in parallel to the functional circuitry206of the IC die104as part of a power delivery network, the method400may be utilized to form chip packages having other types of IPDs. For example, the IPD102may not be connected to a power delivery network, and the IPD102may simply be connected to the functional circuitry206of the IC die104without being connected to the pillars120of the dielectric interconnection layer118or package substrate128in parallel or outside of the functional circuitry206of the IC die104.

FIG.5is another flow diagram of a method500for fabricating a chip package having an integrated passive device (IPD)102disposed between an integrated circuit (IC) die104and a dielectric interconnection layer118. The method500may also be utilized for fabricate other chip packages that include an IPD102disposed between an IC die104and a package substrate128.

The method500begins at operation510by connecting an IPD102to an IC die104to create an IC/IPD assembly. Connecting the IPD102to the IC die104includes connecting the terminals216,218of the IPD102to the circuitry106of the IC die104. In one example, the terminals216,218of the IPD102are soldered, diffusion bonded or otherwise electrically and mechanically connected to the contact pads202,204of the IC die104by the pillars110of the under die layer108that are formed in electrical communication with the contact pads202,204of the IC die104.

After connecting the IPD102to the IC die104, an IPD layer116may be disposed around the IPD102. After the IPD layer116is coupled to the IC die104, underfill material112is dispensed between the IPD layer116and the IC die104to surround the pillars110and complete the under die layer108. The underfill material112may also enhance the connection between the IPD102and the IC die104. When necessary, the bottom surface160of the IPD layer116is planarized to better allow the subsequent formation of the pillars120of the dielectric interconnection layer118on the conductive posts174. The conductive posts174are disposed through the dielectric material172can electrically and mechanically connected to the pillars110. In one example, the conductive posts174are plated on the pillars110.

In an alternative example, the IPD102may be mechanically connected to the IC die104. In such an example, the terminals216,218of the IPD102may be later connected to the circuitry106of the IC die104through the dielectric interconnection layer118and/or IPD layer116, for example utilizing jumpers, at a later operation.

At operation520, the dielectric interconnection layer118is formed on the IC/IPD assembly to create a IPDL/IC/IPD assembly. Forming the dielectric interconnection layer118includes connecting a plurality of pillars120to the conductive posts174. In one example, the pillars120are plated on the conductive posts174. The pillars120of the dielectric interconnection layer118are coupled to the circuitry114(i.e., pillars110) of the under die layer108via the conductive posts174such that the pillars120of the dielectric interconnection layer118are coupled is coupled to the circuitry106of the IC die104. In one example, the pillars120of the dielectric interconnection layer118are coupled to the terminals216,218of the IPD102through the circuitry106of the IC die104.

Optionally, forming dielectric interconnection layer118may include creating a space126that receives at least a portion of the IPD102.

In an alternative example where the IPD102is only mechanically connected to the IC die104, the terminals216,218of the IPD102are connected to the pillars120of the dielectric interconnection layer118when the dielectric interconnection layer118is formed on the IC/IPD assembly.

At operation530, the IPDL/IC/IPD assembly is mounted to a package substrate128to form a chip package100. Optionally, a redistribution layer maybe disposed between the IPDL/IC/IPD assembly and the package substrate128as illustrated inFIG.1B. Mounting the package substrate128to the IPDL/IC/IPD assembly includes mechanically and electrically connecting the pillars120of the dielectric interconnection layer118to the circuitry182of the package substrate128. The connection between the pillars120of the dielectric interconnection layer118to the circuitry182of the package substrate128may be soldered, diffusion bonded or otherwise electrically and mechanically connected to provide robust power, ground and date transfer between the circuitry182of the package substrate128and the circuitry106of the IC die104.

Also at operation530, underfill material198is dispensed between the IPD layer116and the package substrate128to surround the pillars120and complete the dielectric interconnection layer118. The underfill material112may also enhance the connection between the package substrate128and the IPD layer116.

At operation530, an array of solder balls140may also be formed on the bottom surface168of the package substrate128.

FIG.6is yet another flow diagram of a method600for fabricating a chip package having an integrated passive device (IPD)102disposed between an integrated circuit (IC) die104and a dielectric interconnection layer118. The method500may also be utilized for fabricate other chip packages that include an IPD102disposed between an IC die104and a package substrate128.

The method600begins at operation610by attaching an IPD102to an IPD layer116to form IPD/IPD layer assembly. In IPD102may be secured to the IPD layer116using adhesives or other suitable technique.

At operation620, an IC die104is attached to the IPD/IPD layer assembly. Attaching the IC die104to the IPD/IPD layer assembly includes electrically and mechanically coupling the pillars110extending from the IC die104to the conductive posts174residing in the IPD layer116. After attaching IC die104to the IPD/IPD layer assembly, underfill material112may be dispensed between the IPD layer116and the IC die104to surround the pillars110, thus forming an under die layer108with the pillars110.

At operation630, a package substrate128is assembled to the IPD/IPD layer assembly with attached the IC die104. Assembling the IPD/IPD layer assembly to the package substrate128includes electrically and mechanically coupling the pillars120extending from the IPD/IPD layer assembly to the circuitry182of package substrate128. After assembling the IPD layer116to the package substrate128, underfill material198may be dispensed between the IPD layer116and the package substrate128to surround the pillars120, thus forming a dielectric interconnection layer118with the pillars120.

At operation630, an array of solder balls140may also be formed on the bottom surface168of the package substrate.

Thus, a chip package and method for fabricating have been described that includes a near-die integrated passive device. Positioning the integrated passive device very close to the IC die avoids routing through fanouts, and improves communication speeds and reliability. Additionally, parasitic losses that occur in conventional routing of integrated passive devices to the IC die through the package substrate are eliminated. When used a part of a power delivery network, near-die integrated passive devices enable significant improvements in loop inductance and AC droop are realized.