Differential amplifier balancing system

Complementary outputs of a differential amplifier are individually peak detected and the resulting signals are applied to the amplifier differential input in a manner to cause the output peak excursions to have substantially the same direct current levels. This causes the crossover of the two outputs to occur at the midpoint of the signal swing regardless of the input signal peak-to-peak swing, at whatever level.

TECHNICAL FIELD 
This invention relates to arrangements for balancing differential amplifier 
output signals. 
BACKGROUND OF THE INVENTION 
Differential amplifiers exhibit internal effects, e.g., due to temperature 
variations or component value mismatches within manufacturing tolerances, 
that cause amplifier complementary output signals to be unbalanced in the 
sense of having significantly different direct current peak levels for 
corresponding excursions in the same direction. Similar effects may be 
produced, e.g., by temperature drifts in components in the amplifier input 
circuitry. These different levels are troublesome at least in differential 
signal operations because they cause the complementary signals to 
experience, during information state transistions, equal-amplitude 
crossings at different phases with respect to the time base of the binary 
digital signals depending upon temperature variations, signal strength, 
and internal gains of the amplifier. In the frequent cases where input 
information signal swings are in an amplitude range which is comparable to 
the magnitude of the imbalance between the complementary output signals 
those outputs may not cross at all during the transitions. 
In a C. F. Wheatley U.S. Pat. No. 3,983,502 quiescent current flow in a 
differentially driven amplifier load is reduced by degeneratively feeding 
back to the input of the amplifier a low pass filtered version of the 
differential load signal. However, this approach would appear to compress 
amplifier low frequency gain as a function of that feedback rather than 
directly correcting the amplifier output imbalance as to noncoincident 
peaks of complementary signals. 
A W. W. Brown et al. U.S. Pat. No. 4,027,152 merges differential amplifier 
outputs in a common peak detector, the output of which is used as an 
automatic gain control signal without affecting any possibile imbalance 
between the amplifier output signals. 
SUMMARY OF THE INVENTION 
The imbalance between complementary outputs of a differential amplifier is 
corrected in accordance with an illustrative embodiment of the present 
invention by separately applying peak signal information from those 
outputs to differential inputs of the amplifier in an appropriate sense to 
reduce the imbalance. In one illustrative application, the complementary 
outputs are also applied to different inputs, respectively, of a 
differential comparator to indicate information signal transition at 
approximately equal-signal level crossings of the complementary signals 
during each information state transition.

DETAILED DESCRIPTION 
The invention is illustrated in the drawing as applied to a balanced 
amplifier 10 which is utilized as a receiver in a fiber optical 
communication system. To this end an optical fiber 11 provides an 
information signal transmission path which is coupled to a photodiode 12 
for converting light pulse signals to corresponding electric voltage 
signals. Binary coded signals so received in an optical communication 
system may have widely different peak-to-peak values from time to time 
depending upon the characteristics of the optical transmission path 
coupled to fiber 11. Furthermore, within the range of those values the 
coding format usually includes one or the other of only two information 
signal states, either high or low. Otherwise different coding techniques 
may be represented by the incoming signals. Such techniques may include 
for example, non-return-to-zero, Manchester, or Miller (sometimes called 
delayed modulation or modified frequency modulation) coding. 
Photodiode 12 is connected in a potential dividing circuit including a 
negative voltage supply 13. That supply and others in the drawing, are 
schematically represented by a circled polarity sign corresponding to the 
polarity of the supply terminal connected to the electric circuit point of 
the schematic representation. A terminal of the opposite polarity is to be 
understood as being connected to ground. A voltage regulator 16 is 
connected in series with a resistor 17, the photodiode 12, and a further 
resistor 18 to ground. Capacitors 19 connect opposite terminals of the 
regulator 16 and resistor 17 to ground. Regulator 16 is, for example, of 
the type of the 78L and 79L regulators sold commercially by Motorola 
Incorporated for different supply polarities. A third regulator terminal 
is connected to ground. Binary signal state levels are developed across 
resistor 18 as light pulse signals in the fiber 11 turn the diode 12 off 
and on or otherwise control it between readily distinguishable levels of 
operation. 
Amplifier 10 has complementary, or differential, inputs and outputs. 
Signals developed across resistor 18 are applied through a lead 15 to a 
noninverting one of those inputs, and the corresponding inverting input is 
connected to ground through a resistor 20 having a resistance of 
substantially the same value as the resistance of resistor 18. Those like 
resistors are employed to enhance common mode rejection of noise in the 
vicinity of the amplifier input. One percent film resistors are 
advantageously employed. Amplifier 10 is illustratively a differential 
amplifier such as the .mu.A733 amplifier of the Signetics Corporation. All 
internal stages of such an amplifier are direct coupled. Negative and 
positive supplies 21 and 22 are coupled to amplifier 10 through voltage 
regulators 23 and 26, respectively. Only a partial schematic diagram is 
shown for the internal connections of the amplifier 10 since that is all 
that is necessary to illustrate the connections for the present invention. 
Thus, the amplifier 10 includes an input differential amplifier stage 
comprising npn transistors 27 and 28 having their base terminals 
connected, respectively, to the aforementioned inverting and noninverting 
input connections of the amplifier. Emitter terminals of these transistors 
are connected through resistors 29 and 30, respectively, to a current 
source-connected transistor 31, schematically represented by a circled 
arrow. The other terminal of that transistor is connected to the voltage 
regulator 23. Collector connections of the two transistors 27 and 28 are 
coupled (by circuits not specifically shown) through other stages of the 
amplifier to inverted and noninverted output connections, respectively, of 
the amplifier and which are otherwise designated Q and Q. 
A differential comparator 32, such as the .mu.A760 comparator of the 
Fairchild Corporation, has its differential input connections direct 
coupled to receive signals from the Q and Q signals of amplifier 10. With 
this arrangement, the comparator indicates a match when the complementary 
input signals cross one another, i.e., when they exhibit equal signal 
levels during data information state transitions between binary ONE and 
binary ZERO states. The complementary outputs of comparator 32 experience 
binary signal state changes in response to each detected match in the 
comparator. Positive and negative supplies 33 and 36 are coupled to the 
comparator through voltage regulators 37 and 38, respectively. 
Comparator 32 is advantageously one that operates over a wide range. That 
is, its range is large enough so that it is responsive to expected level 
variation in the output of amplifier 10 without the need for automatc gain 
control to confine those variations. 
The employment of separate regulators in power supply connections for 
separate components of the circuit of FIG. 1 decoupled noises, such as 
supply bus noises, by about 60 decibels in one embodiment. This quieting 
of amplifier operation improves the operating error rate of the overall 
circuit. 
As described up to this point, temperature effects and circuit element 
mismatches within manufacturing tolerances will frequently cause a 
significant shift between the Q and Q outputs of amplifier 10 so that they 
exhibit different peak values for opposite binary signal states during 
signal reception. As shown by solid lines in FIG. 2, the Q and Q outputs 
of amplifier 10 cross at a time t.sub.1, and at a certain amplitude, 
during transitions between ONE and ZERO states. In the central time 
portion of the diagram the Q signal is high and Q is low, and that is, 
assumed to represent a binary ONE. The adjacent diagram portions where Q 
is high represent binary ZEROs. Thus, the ideal situation is to have, for 
example, the Q peaks in One at the same level as the Q peaks in ZEROs. 
However, a relatively small shift between the average values of the Q and 
Q signals, shown in FIG. 2 by a dashed waveform as a drop in the Q level, 
produces a crossing of those Q and Q signals at a later phase 
corresponding to the time t.sub.2. The indicated internal effects on the 
amplifier will typically affect the two complementary outputs in opposite 
directions, but for convenience of illustration the effect has been shown 
in FIG. 2 as applied only to the Q signal. 
FIG. 3 illustrates for the shifted Q and the Q outputs of amplifier 10 the 
situation in which the aforementioned internal amplifier factors cause a 
sufficient shift in Q and Q output values so that they no longer cross a 
comon amplitude level during data transitions. 
In order to assure that the complementary outputs of amplifier 10 exhibit 
substantially the same direct current levels for peaks of opposite binary 
signal states, those Q and Q outputs are direct coupled through peak 
detectors 39 and 40, respectively, to inverting and noninverting inputs, 
respectively, of a further differential amplifier 41. Each peak detector 
is the same and advantageously includes in the series signal path thereof 
a diode 42, such as a Schottky diode poled for forward conduction toward 
amplifier 41. In addition in different shunts, thereof, there are 
capacitor 43 and a resistor 46 each connected to ground. Impedance values 
of the capacitor and resistor in each peak detector are selected to give a 
time constant which is substantially larger than the period of the signal 
of lowest data bit rate which is expected to be amplified in amplifier 10. 
In one embodiment, the time constant of each peak detector was 
approximately 10 times the period of the lowest expected data bit rate. 
The differential amplifier 41 includes two pnp transistors 47 and 48. Bases 
of the two transistors are connected to receive signals from the 
noninverting and inverting inputs, respectively, of the amplifier. 
Collectors of the same transistors are direct coupled to a low impedance 
point in an input stage of amplifier 10 to reduce sensitivity to noise of 
the feedback circuit. Such a point is at the emitter terminals of the 
transistors 27 and 28, respectively, in the amplifier 10. Thus, Q and Q 
outputs of amplifier 10 are differentially direct coupled through their 
respective peak detectors and amplifier 41 to inputs of amplifier 10 to 
reduce imbalances between those Q and Q outputs. 
Emitter terminals of transistors 47 and 48 are connected together and 
through a common resistor 49 to receive operating potential from a 
positive supply 50 by way of a voltage regulator 51. The resistance of the 
resistor 49 is selected to be large enough so that it does not appreciably 
reduce the peak detector time constants and large enough so that it 
prevents signals from amplifier 41 from causing deteriorating of the 
normal peak-to-peak output of amplifier 10. 
The result of the use of peak signal information is compensating feedback, 
as herein before described, is to adjust dynamically the balance in 
amplifier 10 without substantially affecting the amplifier gain in order 
to offset any imbalance between peak values of the Q and Q output signals 
of that amplifier. Accordingly, as in FIG. 4, the peak excursions for the 
complementry signals are substantially the same for opposite data 
information states, whether the signal swings between high and low signal 
levels of the respective states are large (Q.sub.H, Q.sub.H) or small 
(Q.sub.L, Q.sub.L). Likewise, the Q and Q signals in either case cross 
each other during each data information transition at substantially the 
same amplitude level, which level is midway in the peak-to-peak swing. 
In the illustrative embodiment, the various impedance values are not as 
critical as in many prior art amplifiers. For example, a data-unbalanced 
input signal in a 30 decibel power variation range can be tolerated. The 
reason is that the combination of the differential amplifier 10 with the 
peak compensating feedback and the differentially driven comparator 32 
allows the circuit to tolerate limited discrepancies as long as the signal 
crossing points remain in a reliable match detecting range of the 
comparator. 
Although the present invention has been described in connection with a 
particular embodiment thereof it is to be understood that additional 
embodiments, modifications, and applications thereof which will be obvious 
to those skilled in the art are included within the spirit and scope of 
the invention.