Bipolar transistor with base horizontally displaced from collector

Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to integrated circuit (IC) structures. More specifically, various embodiments of the disclosure provide a bipolar transistor with a base that is horizontally displaced from a collector.

BACKGROUND

In the microelectronics industry as well as in other industries involving construction of microscopic structures, there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. One type of transistor architecture is the bipolar transistor, also known as the bipolar junction transistor (BJT). A bipolar transistor is a transistor formed of three adjacent semiconductor regions (respectively known as emitter, base, and collector) with alternating conductivity types (e.g., N-P-N or P-N-P). Conventional approaches to form a BJT on a semiconductor substrate form an extrinsic base linked to an intrinsic base (e.g., via conventional epitaxy). Such an approach generally causes portions of the collector and extrinsic base to vertically overlap. Vertical overlap between the base and collector may lead to higher base-to-collector capacitance than is not desired in certain technical applications.

SUMMARY

Aspects of the present disclosure provide a bipolar transistor structure, including: a sub-collector on a substrate; a first collector region on a first portion of the sub-collector; a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region; a second collector region on a third portion of the sub-collector and adjacent the TI; a base on the first collector region and a portion of the TI; and an emitter on a first portion of the base above the first collector region, wherein the base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

Further aspects of the present disclosure provide a bipolar transistor structure, including: a sub-collector on a substrate; a first collector region on a first portion of the sub-collector; a trench isolation (TI) on a second portion of the sub-collector and surrounding the first collector region; a second collector region on a third portion of the sub-collector and adjacent the TI; a third collector region on a fourth portion of the sub-collector and adjacent the TI, such that the first collector region is between the second collector region and the third collector region; a set of collector contacts to the second collector region and the third collector region; a base on first collector region and a portion of the TI; a base contact to the base; an emitter on a first portion of the base above the first collector region; and an emitter contact to the emitter, wherein the base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

Yet another aspect of the present disclosure provides a bipolar transistor structure, including: a sub-collector on a substrate; a first collector region on a first portion of the sub-collector; a trench isolation (TI) on a second portion of the sub-collector and surrounding the first collector region; a second collector region on a third portion of the sub-collector and adjacent the TI; a base on first collector region and a portion of the TI; and an emitter on a first portion of the base above the first collector region, wherein the base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction, and the TI is vertically between the sub-collector and the second portion of the base to define a capacitive coupling between the sub-collector and the second portion of the base.

DETAILED DESCRIPTION

In the description herein, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made within the scope of the present teachings. The description herein is, therefore, merely illustrative.

Embodiments of the disclosure provide an integrated circuit (IC) having a bipolar transistor with collectors raised above a substrate, and a base that is horizontally displaced from the collectors. The term “horizontally displaced,” as used herein, refers to any two elements that have at least one other element horizontally between them, thus defining a horizontal separation between the two elements. A portion of the base of the bipolar transistor, in particular, may be horizontally displaced from the collector such that an insulator and/or inactive semiconductor material is between these two components. One or more contacts to the collector, in turn, can be horizontally displaced from the base in one direction and horizontally displaced from the emitter in a second, different direction. The horizontal displacement between base and collector may avoid vertical overlap of the base with the collector. To avoid horizontal overlap between the base and collector, the base may extend outwardly from the emitter parallel with portions of the collector beneath the collectors, with each component being located in different two-dimensional planes. Among other things, this configuration causes a transistor to occupy less area and volume in a structure, while allowing it to perform the same functions as conventional transistor structures. In particular, the width of the transistor is reduced by including only the emitter the base along a first horizontal direction, while the length of the transistor is substantially maintained (or also reduced) by aligning the base contact and collector contacts along the length, or other axis different from the width.

The bipolar transistor may include a bipolar junction transistor (BJT) stack configured to include, e.g., a NPN, PNP, heterojunction (HBT) NPN, or HBT PNP configuration. The structure may include a sub-collector on a substrate. A first collector region is on a first portion of the sub-collector, and a second collector region is on another portion of the sub-collector. A trench isolation is on a portion of the sub-collector between the two collector regions, thus separating the second collector region from the first collector region. A base is on the first collector region and a portion of the TI. An emitter is on the base, and part of the base extends horizontally away from the emitter in a first horizontal direction. Thus, a portion of the base is horizontally displaced from the second collector region in a horizontal direction that is orthogonal to a horizontal separation between the second collector region and the emitter. Contacts to the base similarly may be horizontally displaced from any contacts to the second collector region along one horizontal axis, and horizontally displaced from any contacts to the emitter along an orthogonal horizontal axis. Thus, the contacted base may be both horizontally and vertically separated from the collector to avoid any overlap between these two portions of the bipolar transistor. Embodiments of the disclosure thus offer lower base-to-collector capacitance in contrast to conventional bipolar transistors, in which portions of the base will vertically overlap the collector.

Bipolar transistors, such as those in embodiments of the disclosure, include multiple “P-N junctions.” The term “P-N” refers to two adjacent materials having different types of conductivity (i.e., P-type and N-type), which may be induced through dopants within the adjacent material(s). A P-N junction, when formed in a device, may operate as a diode. A diode is a two-terminal element, which behaves differently from conductive or insulator materials between two points of electrical contact. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the “forward” direction), but provides little to no conductivity in the opposite direction (i.e., the “reverse” direction). In the case of a junction between two semiconductor materials, the potential barrier will be formed along the interface between the two semiconductor materials. IC structures according to the disclosure include a base that is horizontally displaced from the emitter and a collector along respective orthogonal axes, thus avoiding overlap between the second portion of the base and the collector. In some implementations, portions of the collector and base may extend horizontally away from the emitter in parallel with each other. These structural characteristics may provide, among other things, improved operational reliability, and reduced capacitance between the base and collector terminals of the bipolar transistor.

Referring toFIGS.1-3, a bipolar transistor100(simply “transistor” hereafter) according to embodiments of the disclosure is shown.FIG.1provides a perspective view of transistor100, whileFIGS.2and3depict cross-sectional views of transistor100, viewed from the perspective indicated through view lines2-2and3-3ofFIG.1, respectively. Transistor100may be formed on a substrate102including, e.g., one or more semiconductor materials. Substrate102may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, or any other common IC semiconductor substrates. A portion or entire semiconductor substrate102may be strained. Additionally, various conductive particles (“dopants”) may be introduced into substrate102via a process known as “pre-doping” of substrate102.

Embodiments of the disclosure may include a set of trench isolations (TIs)110, formed by forming and filling trenches (not shown) with an insulating material such as oxide, to isolate various portions of substrate102from other portions of substrate102. Various portions of an IC structure, including the active semiconductor materials of transistor100and/or other devices formed on substrate102, may be disposed within an area of substrate102that is isolated by TI(s)110. According to one example, two areas of TI110material are shown, but these areas may in fact be portions of a single, larger region of TI110material and/or groups of larger TI110regions, with one portion of substrate102being horizontally between the two illustrated areas of TI110. Portions of substrate102, and materials formed thereon, may define the various terminals and components of transistor100. Various portions of substrate102may be doped and/or otherwise processed to form a conductive coupling to one terminal of transistor100. TIs110may be formed before active materials are formed within substrate102, but this is not necessarily true in all implementations. Each TI110may be formed of any currently-known or later developed substance for providing electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof.

Selected portions of substrate102may be doped to define various active components of transistor100. Such portions of substrate102may be alongside and underneath TI(s)110to provide a pathway to other doped semiconductor materials. The doping of substrate102may be P-type or N-type in a relatively low concentration, compared to other doped regions and/or materials of transistor100(e.g., BJT stack116), discussed herein. P-type dopants refer to elements introduced into substrate102to generate free holes by “accepting” electrons from a semiconductor atom and consequently “releasing” the hole. The acceptor atom must have one valence electron less than the host semiconductor. P-type dopants suitable for use in substrate102may include but are not limited to: boron (B), indium (In) and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Further alternatives include indium and gallium (Ga). Gallium (Ga) features high diffusivity in silicon dioxide (SiO2), and hence, the oxide cannot be used as a mask during Ga diffusion. N-type dopants are elements introduced into semiconductor materials to generate free electrons, e.g., by “donating” an electron to the semiconductor. N-type dopants must have one more valance electrons than the semiconductor. Common N-type donors in silicon (Si) include, e.g., phosphorous (P), arsenic (As), and/or antimony (Sb).

Various additional doped semiconductor materials may be formed on substrate102, thus defining active regions of transistor100. Specifically, transistor100includes a BJT stack116of semiconductor materials over substrate102. BJT stack116may include the same material and/or similar materials as substrate102thereunder, and/or may include silicon germanium (SiGe), or one or more compound semiconductor materials (e.g., gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon carbide (SiC), gallium nitride (GaN), and/or other compound materials with similar properties). Each of these various semiconductor or compound semiconductor materials may be formed as a single layer or film.

BJT stack116may include a collector120, which may be doped N-type or P-type and in some cases may have the same polarity as doped portions of substrate102thereunder. Collector120may have different dopants and/or doping concentrations compared to substrate102, and may be doped in situ during its deposition and growth, where applicable. Collector120may be subdivided into several portions, distinguishable from each other based on their position relative to TI(s)110and/or other components discussed herein. Otherwise, each portion of collector120may be compositionally or structurally indistinct, and/or may have a substantially uniform concentration of dopants and/or a single doping polarity. As used herein, a “substantially uniform” doping concentration refers to a structure in which no portion of the structure has a doping concentration that differs from the doping concentration in another portion of the structure by more than, e.g., approximately ten percent. In other implementations, the threshold percentage for uniformity may be less than approximately ten percent. Collector120may include a sub-collector120aon an upper surface of substrate102, thus defining a physical interface between substrate102and collector120. Collector120additionally may include, e.g., a first collector region120badjacent TI(s)110and underneath a portion of a base122of transistor100. The term “collector region,” as used herein, may refer to a layer, portion, or other area of doped semiconductor material located on an upper surface sub-collector120a, and perhaps structurally integrated with portions of sub-collector120athereunder. First collector region120band similar collector regions may be distinguished from sub-collector120asolely by their position on sub-collector120a, and not by physical interfaces and/or differences between the two components.

As discussed elsewhere herein, base122may include semiconductor material with opposite doping from collector120. Base122may be on only first collector region120band adjacent portions of TI(s)110, with other portions of collector120not having a junction with base122. A second collector region120c(FIGS.1and3only) of collector120may also be on sub-collector120aand adjacent TI(s)110, but may be horizontally displaced from first collector region120b. Second collector region120cmay be connected to first collector region120bthrough an intermediate portion120n(FIGS.1and3only) located, e.g., at least partially beneath TI(s)110(e.g., as shown inFIGS.1and3). Sub-collector120aand/or collectors120b,120cmay be formed, e.g., by epitaxial growth of each semiconductor material over substrate102, and/or by other methods including in situ doping or via tailored implantation, hybrids of epitaxial growth and/or implantation, and/or further doping techniques. Such processes may produce sub-collector120aas a layer of doped semiconductor material, with collectors120b,120cbeing formed thereover by epitaxial growth and/or removing selected portions of semiconductor material, followed by tailored implanting of dopants.

Transistor100may include base122on first collector region120bof collector120. Similar to collector120, base122may be formed of SiGe, compound semiconductor materials, etc., and may have an opposite doping type with respect to collector120, e.g., by being P-type when collector120is N-type, or vice versa. In further implementations, base122may include any currently known or later developed compound semiconductor material, e.g., GaAs, AlGaAs, SiC, GaN, etc. Base122may have a horizontal width (WB inFIG.2) that is greater than a horizontal width (Wc inFIG.2) of first collector region120bof collector120thereunder, e.g., due to being formed partially on TI(s)110adjacent first collector region120b. Base122itself may be subdivided into a first portion122aand a second portion122b. First portion122aof base122and second portion122bof base122may have the same doping polarity, but different doping concentrations. First portion122amay include, and/or in some cases may be embodied as, an intrinsic base having a lower doping concentration than second portion122b, to more easily control the flow of current from collector120to an emitter124formed on first portion122a. In this case, emitter124may be located above only first portion122a, and thus second portion122bmay have a higher doping concentration than first portion122a. Although two portions of second portion122bare shown on opposite sides of emitter124, it is understood that base122wraps around an entirety of emitter124.

The higher doping concentration in second portion122bmay increase electrical conductivity between base122and any contacts coupled to base122for controlling the flow of current through BJT stack116. As shown, second portion122bmay be vertically above sub-collector120a, with portions of TI110vertically separating sub-collector120afrom second portion122b. In this case, a capacitive coupling C may be defined across TI110, and the size of the vertical separation may be controlled to provide a desired collector-base capacitance for particular applications. In further implementations discussed herein, capacitive coupling C may be eliminated via structural modifications. Despite any differences in the doping concentration at different portions thereof, base122may have the same material composition as other layers and/or materials in BJT stack116, and thus may include SiGe.

An emitter124may be on first portion of base122a, and may have the same doping type as collector120. In this position, transmitting a current to base122may control whether current is capable of flowing from collector120to emitter124. Emitter124thus may include any material capable of being included within collector120and/or other semiconductor materials, e.g., SiGe, compound semiconductor materials, and/or other materials with similar properties. Emitter124may be doped to any desired concentration. In some cases, emitter124may have a similar doping concentration as collector120. In BJT stack116, collector120, base122, and emitter124form alternating P-N junctions because of their arrangement and doping, and thus define the three active terminals of transistor100. The doping types and concentrations of collector120, base122, and/or emitter124of BJT stack114may be controlled, e.g., by epitaxial and/or by other methods including in situ doping or via implantation, hybrids of epitaxial growth and/or implantation, and/or further doping techniques as described herein.

BJT stack116may be located alongside and/or within insulator materials. A set of spacers126may be on sidewalls of emitter124. Spacers may be formed of a nitride insulator and/or other insulator materials described elsewhere herein with respect to TI(s)110and/or other insulator materials. Spacer(s)126, once formed, electrically separate emitter124from other materials formed on base122. An inter-level dielectric (ILD) layer130may be above substrate102; including TI(s)110, and BJT stack116. ILD layer130may include the same insulating material as TI(s)110, or may include a different electrically insulating material. ILD layer130and TI(s)110nonetheless constitute different components, e.g., due to TI(s)110being formed within portions of substrate102instead of being formed thereon. ILD layer130can separate substrate102and transistor100formed thereon from various overlying layers. Such layers may include, e.g., metal level layers for interconnecting transistor100with other devices on substrate102and/or other active components of a device.

Various portions of transistor100, e.g., second collector region120cof collector120, second portion122bof base122, and/or emitter124, may include a silicide layer132for coupling of active semiconductor material to conductive material(s) thereon. Silicide layer132as known in the art could be formed on the exposed surfaces of collector120, base122, and/or emitter124before ILD layer130deposition. For example, a cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), or similar self-aligned silicide (salicide) could be formed before ILD layer130deposition. Additional metallization layers (not shown) may be formed on ILD layer130during middle-of-line and/or back-end-of-line processing.

To electrically couple various components discussed herein to such metallization layers, a collector contact134a(FIG.3only) may be formed within ILD130to second collector region120cof collector120, e.g., at silicide layer132. Similarly, one or more base contacts134b(FIG.2only) may be formed within ILD130for coupling to second portion122bof base122and/or silicide layer(s)132therein. An emitter contact134c(FIG.3only) within ILD130can be formed to emitter124, e.g., on silicide layer(s)132of emitter124. Each contact134a,134b,134cmay include any currently known or later developed conductive material configured for use in an electrical contact, e.g., copper (Cu), aluminum (Al), gold (Au), etc. Contacts134a,134b,134cmay additionally include refractory metal liners (not shown) positioned alongside ILD layer130to prevent electromigration degradation, shorting to other components, etc.

Referring toFIGS.1and4, embodiments of transistor100may position collector120and base122in a manner that is structurally distinct from conventional bipolar transistors formed on or within semiconductor material (e.g., substrate102).FIG.4illustrates a plan view of collector120including sub-collector120a, first collector region120b, and second collector120cto show their respective positions. Base122, emitter124, and portions thereof are shown in dashed lines to illustrate their position in overlying planes. As shown generally inFIGS.1and4, second collector region120cof collector120and second portion122bof base122may be horizontally displaced along a first direction (e.g., along the Y-axis). Thus, second portion122bmay not vertically overlap second collector region120cdue to their relative horizontal positions (e.g., on the Y-axis). Second collector region120cadditionally may be horizontally displaced from emitter124along a second direction that is orthogonal to the first direction (e.g., along the X-axis). The physical separation of second collector region120cfrom second portion122bof base122, and emitter124, may reduce parasitic capacitance in transistor100due to the inability for current to pass horizontally and vertically from second collector region120cto base122and/or emitter124directly through TI(s)110. Moreover, embodiments of the disclosure occupy less area or volume than conventional bipolar transistors, by aligning emitter124and second collector region120cin a horizontal direction (e.g., along X-axis) that is orthogonal to the alignment between second collector region120cand second portion122bof base122.

Referring toFIG.5embodiments of transistor100may include further physical and electrical characteristics for controlling base-to-collector capacitance, retaining a desired device area and operational reliability.FIG.5depicts a perspective view with second portion122bof base122being horizontally displaced from second collector region120c, while also being over substrate102without being above sub-collector120a. In this example configuration, second portion122bof base122protrudes horizontally away from emitter124, and substantially in parallel with second collector region120c. Thus, base122remains horizontally displaced from second collector region120cin embodiments of transistor100.

During operation, transistor100in some implementations may accommodate electric current from collector120to emitter124of greater magnitude than the amount of current delivered to base122. To account for these current levels, collector contact134ais shown to have a substantially larger physical interface (indicated, e.g., by surface area in plane X-Y) than the interface between base contact134bto base122. To allow this difference in size, second collector region120cmay occupy a larger surface area in plane X-Y than the surface area of base122, where it connects to base contact134b.

The position of TI(s)110in transistor100in some implementations may prevent capacitive coupling C (FIG.1) from being formed within transistor100. In this case, second portion122bof base122may be located above a space where TI110is formed within sub-collector120a, and thus second portion122bis not vertically above any portion of collector120. Here, the increased vertical thickness of TI110will prevent a capacitive coupling (and hence, base-collector capacitance) from being formed within transistor100. In all other respects, however, transistor100may include the same or similar structural attributes described herein relative to other implementations. That is, second portion122bof base122(and base contact134bthereto) may be horizontally separated from first collector region120bin one direction, and horizontally separated from emitter124in a second direction orthogonal to the first direction (e.g., X and Y axes as shown). Moreover, second portion122bof base122may not vertically overlap second collector region120cof collector120, even with an increased thickness of TI(s)110below second portion122bof base122.

FIGS.6and7depict perspective and plan views, respectively, of an alternative implementation of transistor100with multiple collector contacts134a(FIG.6) and base contacts134b(FIG.7). In some implementations, collector120may include a third collector region120dadjacent first collector region120b, protruding in opposition to (e.g., along X-axis in the opposite direction) second collector region120c. Here, first collector region120bof collector120is horizontally between second collector region120cand third collector region120d. Each of collectors120c,120dmay be horizontally displaced from second portion122bof base122, such that second portion122bvertically overlaps neither second collector region120cnor third collector region120d. In this case, transistor100may include multiple collector contacts134ato second collector region120cand third collector region120dof collector120, respectively. In a similar configuration, second portion122bof base122may include several protrusions extending horizontally from emitter124in opposition to each other, and two base contacts134beach may be coupled to second portion122bon one of the two protruding areas. Each collector contact134a, individually or collectively, may occupy a larger X-Y surface area than base contacts134bto second portion122b. Portions of TI110may be horizontally between second collector region120cor third collector region120d, and second portion122b. Thus, second portion122bof base122may not vertically overlap any portion of second collector region120cor third collector region120d.

FIGS.8and9depict additional implementations of a further alternative implementation of transistor100, in which second collector region120cand third collector region120dextend horizontally in parallel, and are not horizontally aligned with each other (e.g., on either the X-axis or Y-axis in plane X-Y).FIG.8depicts transistor100with a perspective view, whileFIG.9depicts a plan view of transistor100. In such implementations, first collector region120bmay be located underneath first portion122aof base122, with second collector region120cand third collector region120dof collector120protruding horizontally from first collector region120bin opposite directions. However, second collector region120cand third collector region120dmay not be in substantial alignment with each other, e.g., by extending horizontally from different lengthwise ends of first collector region120b. In this configuration, second portion122bof base122may protrude horizontally from first portion122aat a location that is opposite second collector region120c, and from first portion122aat another location that is opposite third collector region120d.

Thus, as shown in the X-Y orientation ofFIG.9, second collector region120cmay be diagonally opposite third collector region120din plane X-Y (e.g., lower right to upper left), while two areas of second portion122bmay be diagonally opposite each other (e.g., lower left to upper right). In implementations where transistor100has a different X-Y orientation, second collector region120cand third collector region120dmay be opposite each other on one axis, while two areas of second portion122bmay be opposite each other in an orthogonal axis, thus defining a cross shape or similar arrangement. In this configuration, however, second portion122bof base122may not vertically overlap second collector region120cor third collector region120dof collector120. Portions of TI(s)110are horizontally between second portion122bof base122and second collector region120cor third collector region120dof collector120. Thus, base contact134bstill may not overlap second collector region120cor third collector region120dwhen multiple collectors (e.g., second collector region120c, third collector region120d) are included.

Embodiments of the disclosure provide various technical and commercial advantages. Some advantages of the disclosure may include, e.g., providing a bipolar transistor structure with lower base-to-collector capacitance, while providing much smaller horizontal surface area as other bipolar transistor devices. Embodiments of the disclosure allow bipolar transistors to be implemented with better operational reliability, while occupying substantially less space versus conventional bipolar transistors. Without any cognizable sacrifices to operability and behavior, bipolar transistors according to embodiments of the disclosure will occupy less area and less volume on a product while continuing to perform the same functions as other bipolar transistors. The reductions in area and volume arise from aligning the base and collector contacts to the transistor in a direction orthogonal to the alignment between the collector and emitter contacts. In this arrangement, the transistor has a smaller width in one horizontal direction while having substantially the same length in another horizontal direction orthogonal to the width. These attributes can allow to related device improvements such as, e.g., smaller chip size, higher device densities, scaling advantages, etc.