CMOS sensor array with a shared structure

A CMOS sensor array includes a plurality of unit blocks. A unit block includes: N pairs of photo diode regions arranged in a first direction; 2N transfer transistors respectively corresponding to the photo diode regions, wherein each of the transfer transistors is formed at a corner of the corresponding photo diode region, and wherein for each pair of photo diode regions the two corresponding transfer transistors symmetrically oppose each other; N floating diffusion nodes, wherein each of the floating diffusion nodes is respectively arranged between a pair of photo diode regions, and wherein each of the floating diffusion nodes is shared by the two corresponding transfer transistors and the pair of photo diode regions; at least one metal line for coupling the floating diffusion nodes; a reset transistor for resetting a voltage of the floating diffusion nodes; a readout circuit including at least one transistor for sampling the floating diffusion node, wherein the reset transistor and the readout circuit are disposed between the pair of photo diode regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application No. 10-2005-0011131, filed on Feb. 7, 2005, the contents of which are herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a layout of active pixel sensor arrays and, more particularly, to a layout of a complementary metal-oxide semiconductor (CMOS) active pixel sensor array having a shared structure in which a plurality of active pixel sensors share a reset transistor and readout transistors.

2. Description of the Related Art

An active pixel sensor is a device for transforming a photo image into an electrical signal. Active pixel sensors are widely used in digital cameras, camera-mounted mobile phones, visual systems, etc.

The active pixel sensor may be broadly classified into a charge-coupled device (CCD) active pixel sensor type and a complementary metal-oxide semiconductor (CMOS) active pixel sensor type. The CCD active pixel sensor type generally exhibits less noise and better image quality than the CMOS active pixel sensor type, but the production costs and power consumption are higher for the CCD type as compared to the CMOS type. The CMOS active pixel sensor type, which may be produced using conventional semiconductor manufacturing technology, may be provided at low costs, for example, due to ease of integration with peripheral systems for amplifying and processing signals.

Typical configurations of the CMOS active pixel sensor include 3-transistor and 4-transistor configurations. According to the 4-transistor configuration, one CMOS active pixel sensor includes one photo diode and four transistors. In the 4-transistor configuration, the integrated charge that is collected by the photo diode is transferred through the four transistors. In the 3-transistor configuration, one CMOS active pixel sensor includes one photo diode and three transistors, and the integrated charge that is collected by the photo diode is transferred through the three transistors.

FIG. 1is a circuit diagram illustrating a conventional 4-transistor CMOS active pixel sensor. Referring toFIG. 1, the 4-transistor CMOS active pixel sensor100includes a photo diode PD, a transfer transistor M11, a reset transistor M12, a source follower transistor M13, and a select transistor M14.

When the reset transistor M12is turned on according to a voltage rise of a gate RG, a voltage of a sensing node, i.e., a floating diffusion node FD is increased to a driving voltage VDD. At that point, the voltage of the floating diffusion node FD is sampled as a reference voltage by means of the source follower transistor M13and the select transistor M14.

During an integration period, electron-hole pairs are generated in proportion to the light that is incident on the photo diode PD. After integration, the collected charge is transferred to the floating diffusion node FD according to a voltage rise of a gate TG of the transfer transistor M11. When the voltage of the floating diffusion node FD is decreased in proportion to the transferred charge, a source voltage of the source follower transistor M13is changed.

Finally, when the select transistor M14is turned on according to a rise of a gate SEL of the select transistor M14, the source voltage of the source follower transistor M13is output as an output signal Vout. An accepted light is sensed by a voltage difference between the reference voltage and the output signal Vout, and this process is referred to as a correlated double sampling. Correlated double sampling yields a representation of the true charge associated with each pixel.

FIG. 2is a circuit diagram illustrating a conventional 3-transistor CMOS active pixel sensor. Referring toFIG. 2, the 3-transistor CMOS active pixel sensor200includes a photo diode PD, a transfer transistor M21, a reset transistor M22and a source follower transistor M23.

In the CMOS active pixel sensor200ofFIG. 2, a dynamic driving voltage DVD is used instead of excluding the select transistor M14from the CMOS active pixel sensor100ofFIG. 1. The dynamic driving voltage DVD is increased to a high level when the floating diffusion node FD is reset and when a voltage of the floating diffusion node FD is sensed, but is generally maintained at a low level. Therefore, the select transistor M14may be substituted using the dynamic driving voltage DVD.

When the dynamic driving voltage DVD reaches the high level and a gate RG voltage of the reset transistor M22is increased to turn on the reset transistor M22, a voltage of the floating diffusion node FD is increased. At that point, the voltage of the floating diffusion node FD is sampled as a reference voltage by means of the source follower transistor M23to be outputted to an internal circuit (not shown) for processing output signals of the active pixel sensors. After the reference voltage is output, the dynamic driving voltage is decreased to the low level.

Integration and charge transfer functions take place within the CMOS active pixel sensor as described above.

Recently, a shared structure, wherein a reset transistor, source follower transistor and select transistor may be shared, has been used for the purpose Of reducing a pixel size and enhancing a fill factor. The fill factor corresponds to a ratio of an area occupied by the photo diode with respect to an area occupied by peripheral circuits for resetting and outputting a sensed signal including a reset transistor, a source follower transistor and a select transistor. In general, the shared structure has been used for increasing the area of the photo diode by sharing transistors that perform the functions of amplifying and transferring signals.

FIG. 3is a top plan view illustrating a conventional layout of a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure. The configuration of the 4-transistor CMOS active pixel sensor array ofFIG. 3is modified from the 4-transistor CMOS active pixel sensor ofFIG. 1so that a reset transistor, a source follower transistor and select transistor may be shared.

Referring toFIG. 3, the layout300of a 4-transistor CMOS active pixel sensor array includes a first photo diode region PD1, a second photo diode region PD2, a third photo diode region PD3and a fourth photo diode region PD4. The layout300of a 4-transistor CMOS active pixel sensor array further includes four transfer transistors M31, M32, M33and M34. The four photo diode regions and the four transfer transistors share a floating diffusion node FD, i.e., a drain region of the four transfer transistors forms a floating diffusion node FD.

A reset transistor M35, which resets a voltage of the floating diffusion node FD, is located between the third photo diode region PD3and the fourth photo diode region PD4. A source follower transistor M36and a select transistor M37are located between the first photo diode region PD1and the second photo diode region PD2. The source follower transistor M36performs a sampling of the voltage of the floating diffusion node FD, and the select transistor M37transfers a source voltage of the source follower transistor M36to an internal circuit (not shown). The internal circuit (not shown) may be a circuit for processing output signals of the active pixel sensors.

In the layout of the shared structure, consideration may be given to maintaining an optical symmetry of the structure and enhancing the availability and productivity of a manufacturing process. In general, there are limitations to forming the layout of the active pixel sensor array having a shared structure. For example, in a configuration in which the floating diffusion node is shared, “steps” between the pixels along object edges may occur due to the layout itself or the manufacturing process.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a complementary metal-oxide semiconductor (CMOS) active pixel sensor array having a shared structure, a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure, and a 3-transistor CMOS active pixel sensor array having a 2-pixel shared structure.

In an exemplary embodiment of the present invention, a CMOS active pixel sensor array having a shared structure includes a plurality of unit blocks. The unit block includes: N pairs of photo diode regions arranged in a first direction on a plane, where N is a natural number; 2N transfer transistors respectively correspond to the photo diode regions, wherein each of the transfer transistors is formed at a corner of the corresponding photo diode region, and wherein for each pair of photo diode regions the two corresponding transfer transistors symmetrically oppose each other; N floating diffusion nodes, wherein each of the floating diffusion nodes is respectively arranged between a pair of photo diode regions, and wherein each of the floating diffusion nodes is shared by the two corresponding transfer transistors and the corresponding pair of photo diode regions; at least one metal line coupling the N floating diffusion nodes; a reset transistor configured to reset a voltage of the floating diffusion nodes; and a readout circuit including at least one transistor configured to sample the floating diffusion node, wherein the reset transistor and the at least one transistor of the readout are disposed between the pair of photo diode regions.

The transfer transistor regions may be formed in an oblique direction with respect to the first direction on the plane, and the oblique direction may be at about a 45-degree direction with respect to the first direction on the plane.

The CMOS active pixel sensor array may further include transfer transistor gate control lines that are extended at about a 90-degree direction with respect to the first direction on the plane. The CMOS active pixel sensor array may further include reset transistor gate control lines that are extended at about a 90-degree direction with respect to the first direction on the plane. The at least one metal line coupling the N floating diffusion nodes may be extended in the first direction. The readout circuit may include a source follower transistor in which a voltage of the floating diffusion node is applied to a gate of the source follower transistor.

The readout circuit further may include a select transistor configured to output a source voltage of the source follower transistor. The CMOS active pixel sensor array may further include a select transistor gate control line that is extended at about 90 degrees with respect to the first direction on the plane.

In an exemplary embodiment of the present invention, a 4-transistor CMOS sensor array having a 4-pixel shared structure includes a plurality of unit blocks arranged in a first direction on a plane. The unit block includes four photo diode regions arranged in the first direction on the plane; four transfer transistors respectively corresponding to the photo diode regions, wherein each of the transfer transistors is formed at a corner of the corresponding photo diode region; a first floating diffusion node shared by the first and second transfer transistors as a drain region; a second floating diffusion node shared by the third and fourth transfer transistors as a drain region; a first metal line for coupling the first and second floating diffusion nodes; a source follower transistor disposed between the third and fourth photo diode regions; a second metal line coupling the second floating diffusion node and a gate of the source follower transistor; a select transistor configured to output a source voltage of the source follower transistor and disposed between a first and second photo diode region; and a third metal line for coupling a source output of the source follower transistor to the select transistor.

In an exemplary embodiment of the present invention, a 4-transistor CMOS sensor array having a 4-pixel shared structure includes a plurality of unit blocks arranged in a first direction on a plane. The unit block includes four photo diode regions arranged in the first direction on the plane; four transfer transistors respectively corresponding to the photo diode regions, wherein each of the transfer transistors is formed at a corner of the corresponding photo diode region; a first floating diffusion node shared by the first and second transfer transistors as a drain region; a second floating diffusion node shared by the third and fourth transfer transistors as a drain region; a first metal line coupling the first and second floating diffusion nodes; a source follower transistor disposed between the first and second photo diode regions; a second metal line coupling the first floating diffusion node and a gate of the source follower transistor; a select transistor configured to output a source voltage of the source follower transistor and disposed between a third and fourth photo diode region; and a third metal line coupling a source output of the source follower transistor to the select transistor.

In an exemplary embodiment of the present invention, a 3-transistor CMOS sensor array having a 2-pixel shared structure includes a plurality of unit blocks arranged in a first direction on a plane. The unit block includes two photo diode regions arranged in the first direction on the plane; two transfer transistors respectively corresponding to the photo diode regions, wherein each of the transfer transistors is formed at a corner of the corresponding photo diode region; a floating diffusion node shared by the two transfer transistors as a drain region; a first metal line coupling the first and second floating diffusion nodes; a source follower transistor located in a space between the two photo diode regions; a reset transistor disposed between the two photo diode regions, arranged next to the source follower transistor at about 90 degrees with respect to the first direction, and sharing a drain with the source follower transistor; and a metal line coupling the floating diffusion node and a gate of the source follower transistor, wherein a variable voltage is applied to the shared drain of the reset transistor and the source follower transistor.

The 3-transistor CMOS sensor array may further include a dynamic driving voltage source configured to selectively provide one of a first driving voltage or a second driving voltage to the shared drain of the reset transistor and the source follower transistor, wherein the first driving voltage is higher than the second driving voltage.

In an exemplary embodiment of the present invention, the dynamic driving voltage source provides the first driving voltage when a voltage of the floating diffusion node is reset and the voltage of the floating diffusion node is output, and the dynamic driving voltage source provides the second driving voltage except when a voltage of the floating diffusion node is reset and the voltage of the floating diffusion node is output.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Hereinafter, the exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to similar or identical elements throughout the description of the figures. As used herein, “natural numbers” are the numbers1,2,3, . . . .

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It should be noted that in some alternative implementations, the functions/actions noted in the blocks may occur out of the order presented in the flowcharts. For example, two blocks shown in succession may be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/actions involved.

FIG. 4is a top plan view illustrating a layout of a 4-transistor complementary metal-oxide semiconductor (CMOS) active pixel sensor array having a 4-pixel shared structure, according to an exemplary embodiment of the present invention. Referring toFIG. 4, the layout400of a 4-transistor CMOS active pixel sensor is formed by arranging a plurality of unit blocks. A unit block includes four photo diode regions PD1, PD2, PD3and PD4, and four transfer transistors M41, M42, M43and M44. Each of the respective transfer transistors corresponds to one of the respective photo diode regions. Although not shown as such inFIG. 4, the unit blocks are repeatedly arranged in a first direction to form an entire active pixel array. In addition, the unit blocks may be further repeatedly arranged in a direction perpendicular to the first direction to form an entire active pixel sensor array.

In an exemplary embodiment of the present invention, four pixels share the reset transistor and the readout transistors, such as the select transistor and the source follower transistor in the shared structure shown inFIG. 4. It is contemplated that other shared structures of two pixels or more than four pixels may be formed. For example, a shared structure of two pixels and four pixels may be used to maintain optical symmetry and to secure a desired performance of the active pixel sensor or, for example, the present invention may be embodied as shared structures of six pixels or eight pixels.

For example, each unit block includes the four photo diode regions PD1, PD2, PD3and PD4arranged in the first direction, and the four transfer transistors M41, M42, M43and M44corresponding to the respective photo diode regions.

The two contiguous photo diode regions in the first direction form a pair. For example, the first photo diode region PD1and the second photo diode region PD2may form one pair, and the third photo diode region PD3and the fourth photo diode region PD4may form another pair, as shown inFIG. 4.

Each of the transfer transistors may be formed respectively at one corner of the corresponding photo diode region, and a gate region of the transfer transistor may be formed in an oblique direction with respect to the first direction. A channel width of the transfer transistor may be increased by such a formation in the oblique direction. Since the transfer transistor has a role of transmitting photoelectrons integrated during an integration period to a floating diffusion node, transmission efficiency may be enhanced when the wide channel width thereof is employed.

For example, the channel width may be increased when the gate region is formed at about a 45-degree direction with respect to the first direction.

The first floating diffusion node FD1is shared between the first transfer transistor M41corresponding to the first photo diode region PD1and the second transfer transistor M42corresponding to the photo diode region PD2, as shown inFIG. 4. In addition, the second floating diffusion node FD2is shared between the third transfer transistor M43corresponding to the third photo diode region PD3and the fourth transfer transistor M44corresponding to the photo diode region PD4.

The first floating diffusion node FD1that is shared between the first transfer transistor M41and the second transfer transistor M42, and the second floating diffusion node FD2that is shared between the third transfer transistor M43and the fourth transfer transistor M44, are coupled through a metal line421. Therefore, the first floating diffusion node FD1and the second floating diffusion node FD2have a common electric potential.

A reset transistor for resetting an electric potential of the floating diffusion nodes FD1and FD2, and a readout circuit including one or more transistors may be appropriately arranged in the spaces between the photo diode regions so as to maintain the optical symmetry of the structure. For example, the shared reset transistor and the readout transistors may be arranged in the space between the two photo diode regions, or may be distributed in the spaces between the photo diode regions within the corresponding unit block and the contiguous unit block. Such a distributed arrangement may enhance the fill factor and may maintain the optical symmetry of the structure.

The reset transistor M45for resetting the second floating diffusion node FD2to a driving voltage may be disposed, for example, in the space between the third photo diode region PD3and the fourth photo diode region PD4. The reset transistor M45, by resetting the second floating diffusion node FD2to the driving voltage, may simultaneously reset the first floating diffusion node FD1having the common electric potential with the second floating diffusion node FD2.

The source follower transistor M46may be arranged in the space between the third photo diode region PD3and the fourth photo diode region PD4. As shown inFIG. 4, the second floating diffusion node FD2and a gate SF of the source follower transistor M46are coupled through the metal line417. The electric potential of the first floating diffusion node FD1and the second floating diffusion node FD2is applied to the gate SF of the source follower transistor M46.

The select transistor M47for transferring the source voltage of the source follower transistor M46to an internal circuit (not shown) may be arranged in the space between a first photo diode region and a second photo diode region of a unit block which is contiguous to the fourth photo diode region PD4in the first direction. The internal circuit (not shown) may be a circuit for processing output signals of the active pixel sensor.

In addition, the source follower transistor M46and select transistor M47are coupled in serial through a metal line422. The source voltage of the source follower transistor M46is output to the internal circuit through the select transistor M47and an output signal (Vout) line423.

The metal line421for coupling the first floating diffusion node FD1and the second floating diffusion node FD2, the metal line422for coupling the source follower transistor M46and the select transistor M47, and the Vout line423may be extended in the first direction.

Transfer transistor gate control lines for controlling voltages of gates TG1, TG2, TG3and TG4of the transfer transistors M41, M42, M43and M44, to transfer photoelectrons integrated in the corresponding photo diode regions, may comprise an electrically conductive material. For example, the electrically conducting material could be a metal. In the same way, reset transistor gate control lines for controlling a voltage of the gate RG of the reset transistor M45to reset the voltage of the floating diffusion nodes to the driving voltage, and select transistor gate control lines for controlling a voltage of the gate SEL of the select transistor M47, to output the source voltage of the select transistor M47to the internal circuit, may comprise an electrically conductive material. Any electrically conducting materials may be utilized. Hereinafter, in the interests, of clarity and brevity, the electrically conducting lines will be referred to as metal lines.

The transfer transistor gate control lines411,412,413and414for controlling the voltages of the gates TG1, TG2, TG3and TG4of the four transfer transistors M41, M42, M43and M44to transfer the photoelectrons integrated in the corresponding photo diode regions PD1, PD2, PD3and PD4to the floating diffusion nodes FD1and FD2may be extended in a second direction. The second direction may be perpendicular to the first direction.

In addition, the reset transistor gate control line415for controlling the voltage of the gate RG of the reset transistor M45to reset the voltage of the floating diffusion nodes to the driving voltage may be extended in the second direction. The select transistor gate control line416for controlling the voltage of the gate SEL of the select transistor M47to output the source voltage of the select transistor M47to the internal circuit may also be extended in the second direction.

It is preferable that the metal lines are not disposed over the photo diode regions so that shielding of the photo diode regions due to the metal lines may be reduced. For example, by arranging the metal lines outside of the upper portions of the photo diode regions that are exposed to incident light, the portion of the photo diode region exposed to the light may be increased. Although a portion of the metal lines may pass the upper portions of the photo diode regions, it is preferable that the metal lines pass corners of the photo diode regions, and shield the same area and symmetrically corresponding positions of the respective photo diode regions.

The metal lines411through417may be formed by a first metal layer deposition process, whereas the metal lines421,422and423may be formed by a second metal layer deposition process. It is to be understood that the metal lines may be formed by various processes including, but not limited to, the processes described above.

Hereinafter, certain characteristics of the active pixel sensor array having the shared structure, according to exemplary embodiments of the present invention, will be described with reference toFIGS. 3 and 4.

First, a photoelectron transfer efficiency may be enhanced by forming the gate region of the transfer transistor for transferring the photoelectrons integrated in the respective photo diode regions in the oblique direction, for example, because a channel width of the transfer transistor may be increased within the limited layout.

Second, the shielding of the photo diode region due to the metal lines may be decreased by separating the metal line421for coupling the first floating diffusion node and the second floating diffusion node and the metal line422for coupling the source voltage of the source follower transistor and the select transistor.

Third, a reduction of conversion gain may be prevented by shortening the metal line417for coupling the floating diffusion node and the gate of the source follower transistor.

Fourth, an optical symmetry of the structure may be maintained to some extent by separating active regions of the source follower transistor and the select transistor. In the conventional layout of the active pixel sensor array having a shared structure, as shown inFIG. 3, the source follower transistor and the select transistor are contiguously located. In the active pixel sensor array having a shared structure, according to the exemplary embodiment of the present invention shown inFIG. 4, however, the source follower transistor and the select transistor are separately located. Therefore, the fill factor may be enhanced while maintaining the optical symmetry of the structure.

The top plan view of the layout of the 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure, as shown inFIG. 4, illustrates an exemplary embodiment of the present invention. It is contemplated that the 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure may be embodied in various configurations. For example, the source follower transistor and the reset transistor may be arranged between the first photo diode region and the second photo diode region, and the select transistor may be arranged between the third photo diode region and the fourth photo diode region.

FIG. 5is a circuit diagram illustrating a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure, according to an exemplary embodiment of the present invention.

The circuit diagram ofFIG. 5corresponds to a unit block of the layout of the 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure ofFIG. 4. Like reference numerals refer to similar or identical components inFIG. 5andFIG. 4.

Referring toFIG. 5, the 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure includes four photo diode regions PD1, PD2, PD3and PD4, and four transfer transistors M41, M42, M43and M44. Each of the respective transfer transistors corresponds to one of the respective photo diode regions. In an exemplary embodiment of the present invention, four photo diode regions PD1, PD2, PD3and PD4, and the four transfer transistors M41, M42, M43and M44share a reset transistor M45, a source follower transistor M46and a select transistor M47.

The photo diode regions PD1, PD2, PD3and PD4and the transfer transistors M41, M42, M43and M44included in the active pixel sensor array ofFIG. 5share the reset transistor M45and the source follower transistor M46, in contrast to with the active pixel sensor100ofFIG. 1. In addition, one floating diffusion node FD is shared.

In the top plan view illustrating the layout of a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure ofFIG. 4, the first floating diffusion node FD1and the second floating diffusion node FD2are shown as separated. However, since the first floating diffusion node FD1and the second floating diffusion node FD2are coupled through the metal line421and have a common electric potential, the two nodes are represented as one floating diffusion node FD in the circuit diagram ofFIG. 5.

Operations of the active pixel sensor array having a shared structure ofFIG. 5may be described, in the interests of clarity and simplicity, by applying the operations of the 4-transistor active pixel sensor to the shared structure. For example, the reset transistor M45resets the voltage of the floating diffusion node FD to the driving voltage VDD, and the photoelectrons integrated in the first photo diode PD1, which corresponds to the first transfer transistor M41, are transferred to the floating diffusion node FD by turning on the first transfer transistor M41. The source follower transistor M46samples the voltage of the floating diffusion node FD. Finally, the select transistor M47is turned on to output the source voltage of the source follower transistor M46to the internal circuit.

The above-described operations are likewise performed for the second photo diode region PD2and the second transfer transistor M42, the third photo diode region PD3and the third transfer transistor M43, and the fourth photo diode region PD4and the fourth transfer transistor M44.

FIG. 6is a top plan view illustrating a layout of a 3-transistor CMOS active pixel sensor array having a 2-pixel shared structure, according to an exemplary embodiment of the present invention.

The layout600of the 3-transistor CMOS active pixel sensor array having a 2-pixel shared structure is formed as a shared structure from the conventional 3-transistor active pixel sensor200. That is, according to the structure ofFIG. 6, the select transistor is excluded, in contrast to the conventional 4-transistor active pixel sensor100ofFIG. 1. The function of the select transistor M13of the conventional 4-transistor active pixel sensor100ofFIG. 1is substituted using a dynamic driving voltage DVD ofFIG. 6.

Referring toFIG. 6, the layout600of the 3-transistor CMOS active pixel sensor array is formed by arranging a plurality of unit blocks. A unit block includes two photo diode regions PD1and PD2arranged in a first direction, and two transfer transistors M61and M62respectively corresponding to the photo diode regions. The unit blocks are repeatedly arranged in the first direction to form an entire active pixel array. In addition, the unit blocks may be further repeatedly arranged in a direction perpendicular to the first direction to form an entire active pixel sensor array.

Each unit block includes the two photo diode regions PD1and PD2arranged in the first direction, and the four transfer transistors M41and M42corresponding to the respective photo diode regions. Each unit block further includes a reset transistor M63and a source follower transistor M64arranged in a space between the photo diode regions.

Each of the transfer transistors may be formed at one corner of the corresponding photo diode region, and a gate region of the transfer transistor may be formed in an oblique direction with respect to the first direction. A channel width of the transfer transistor may be increased by forming the gate region of the transfer transistor at about a 45-degree direction with respect to the first direction. An effect of forming the gate region in the oblique direction may be described with reference to the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4.

The floating diffusion node FD is shared between the first transfer transistor M61corresponding to the first photo diode region PD1and the second transfer transistor M62corresponding to the photo diode region PD2.

The source follower transistor M64may be placed in a space between the first photo diode region PD1and the second photo diode region PD2. The floating diffusion node FD and a gate SF of the source follower transistor M64are coupled through a metal line621.

In addition, the reset transistor M63may be placed in the space between the first photo diode region PD1and the second photo diode region PD2. The reset transistor M63performs a function of resetting a voltage of the floating diffusion node FD to a driving voltage.

Transfer transistor gate control lines for controlling voltages of gates TG1and TG2of the transfer transistor M61and M62, to transfer photoelectrons integrated in the corresponding photo diode regions PD1and PD2, may comprise an electrically conductive material. For example, the electrically conducting material could be a metal. In the same way, reset transistor gate control lines for controlling a voltage of a gate RG of the reset transistor M63, to reset the voltage of the floating diffusion node FD to the driving voltage, may be formed with metal.

The transfer transistor gate control lines611and612for controlling the voltages of the gates TG1and TG2of the two transfer transistors M61and M62to transfer the photoelectrons integrated in the corresponding photo diode regions PD1and PD2to the floating diffusion node FD may be extended in a second direction. Preferably, the second direction may be perpendicular to the first direction as in the case of the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4.

In addition, the reset transistor gate control line613for controlling the voltage of the gate RG of the reset transistor M63to reset the voltage of the floating diffusion node to the driving voltage may be extended in the second direction. A dynamic driving voltage line614for substituting a select transistor by providing a dynamic driving voltage DVD to the source follower transistor and reset transistor may be lengthened in the second direction.

It is preferable that the metal lines are not disposed over the photo diode regions so that shielding of the photo diode regions due to the metal lines may be reduced. For example, by arranging the metal lines outside of the upper portions of the photo diode regions that are exposed to incident light, the portion of the photo diode region exposed to the light may be increased. Although a portion of the metal lines may pass the upper portions of the photo diode regions, it is preferable that the metal lines pass corners of the photo diode regions, and shield the same area and symmetrically corresponding position of the respective photo diode regions.

FIG. 7is a circuit diagram illustrating a 3-transistor CMOS active pixel sensor having a 2-pixel shared structure, according to an exemplary embodiment of the present invention.

The circuit diagram ofFIG. 7corresponds to a unit block of the 3-transistor CMOS active pixel sensor array having a 2-pixel shared structure ofFIG. 6. Like reference numerals refer to similar or identical components inFIG. 7andFIG. 6.

Referring toFIG. 7, the 3-transistor CMOS active pixel sensor array having a 2-pixel shared structure includes two photo diode regions PD1and PD2, and two transfer transistors M61and M62. Each of the respective transfer transistors corresponds to one of the respective photo diode regions. The two photo diode regions PD1and PD2, and the two transfer transistors M61and M42share the reset transistor M63and the source follower transistor M64. For example, the active pixel sensor array ofFIG. 7is formed so that the conventional 3-transistor active pixel sensor200ofFIG. 2may have a shared structure.

Operations of the active pixel sensor array having a shared structure ofFIG. 7may be described, in the interests of clarity and simplicity, by applying the operations of the 3-transistor active pixel sensor to the shared structure. For example, the reset transistor M63resets the voltage of the floating diffusion node FD to a high driving voltage when the dynamic driving voltage is increased to the high driving voltage. The photoelectrons integrated in the first photo diode PD1, which corresponds to the first transfer transistor M61, are transferred to the floating diffusion node FD by turning on the first transfer transistor M61while the dynamic driving voltage is decreased to a low driving voltage. Finally, the source follower transistor M64samples the voltage of the floating diffusion node FD and outputs the output signal Vout to the internal circuit while the dynamic driving voltage is increased to the high driving voltage.

The above-described operations are likewise performed for the second photo diode PD2and the second transfer transistor M62.

As a modification of the layout400of the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4, in another embodiment of the 4-transistor active pixel sensor array having the 4-pixel shared structure the positions of the select transistor and the source follower transistor may be changed by altering a configuration of the metal line. For example, in the 4-transistor active pixel sensor array ofFIG. 5, the select transistor M47may be coupled between the source follower transistor M46and the driving voltage VDD.

The above-described and other configurations may be employed for an efficiency of a metal line or for a reduction of noise of components by increasing a channel length of a transistor.

FIG. 8is a top plan view illustrating a layout of a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure, according to an exemplary embodiment of the present invention.

Referring toFIG. 8, photo diode regions PD1, PD2, PD3and PD4, transfer transistors M81, M82, M83and M84, a first floating diffusion node FD1and a second floating diffusion node FD2may be formed in the same way as in the layout400of the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4.

In addition, the first floating diffusion node FD1and the second floating diffusion node FD2are coupled through a metal line821to have a common electric potential, for example, in the same way as in the layout400of the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4.

A reset transistor M85for resetting the floating diffusion nodes FD1and FD2is arranged in a space between the third photo diode region PD3and the fourth photo diode region PD4, for example, as in the layout400of the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4.

The reset transistor M85, by resetting the second floating diffusion node FD2to the driving voltage, may reset the first floating diffusion node FD1having the common electric potential with the second floating diffusion node FD2.

The source follower transistor M87may be arranged in the space between the first photo diode region PD1and the second photo diode region PD2. Unlike the layout400of the 4-transistor active pixel sensor array having the 4-pixel shared structure shown inFIG. 4, the source follower transistor M87may be arranged in the space between the first photo diode region PD1and the second photo diode region PD2instead of the space between the third photo diode region PD3and the fourth photo diode region PD4.

The first floating diffusion node FD1and a gate SF of the source follower transistor M87are coupled through the metal line817. Therefore, the electric potential of the first floating diffusion node FD1and the second floating diffusion node FD2is applied to the gate SF of the source follower transistor M87.

The select transistor M86for transferring the source voltage of the source follower transistor M87to an internal circuit (not shown) may be arranged in a space between a third photo diode region and a fourth photo diode region of a unit block, which is contiguous to the first photo diode region PD1in the first direction. The internal circuit (not shown) may be a circuit for processing output signals of the active pixel sensors.

In addition, the source follower transistor M87and the select transistor M86are coupled in serial through a metal line822. The source voltage of the source follower transistor M87is output to the internal circuit through an output signal (Vout) line823.

The metal line821for coupling the first floating diffusion node FD1and the second floating diffusion node FD2, the metal line822for coupling the select transistor M86and the source follower transistor M87, and the Vout line823may be extended in the first direction.

Transfer transistor gate control lines for controlling voltages of gates TG1, TG2, TG3and TG4of the transfer transistors M81, M82, M83and M84, to transfer photoelectrons integrated in the corresponding photo diode regions, may comprise an electrically conductive material. For example, the electrically conducting material could be a metal. In the same way, reset transistor gate control lines for controlling a voltage of a gate RG of the reset transistor M85to reset the voltage of the floating diffusion node FD to the driving voltage and select transistor gate control lines for controlling a voltage of the gate SEL of the select transistor M86, to output the source voltage of the select transistor M87to the internal circuit, may be formed with metal.

The transfer transistor gate control lines811,812,813and814for controlling the voltages of the gates TG1, TG2, TG3and TG4of the four transfer transistors M81, M82, M83and M84to transfer the photoelectrons integrated in the corresponding photo diode regions PD1, PD2, PD3and PD4to the floating diffusion nodes FD1and FD2may be extended in a second direction. The second direction may be perpendicular to the first direction.

In addition, the reset transistor gate control line815for controlling the voltage of the gate RG of the reset transistor M85to reset the voltage of the floating diffusion nodes to the driving voltage may be extended in the second direction. The select transistor gate control line816for controlling the voltage of the gate SEL of the select transistor M86to output the source voltage of the select transistor M87to the internal circuit may also be extended in the second direction.

The metal lines811,812,813,814,815,816and817may be formed by a first metal layer deposition process, while the metal lines821,822and823may be formed by a second metal layer deposition process. It is to be understood that the metal lines may be formed variously using other processes.

FIG. 9is a circuit diagram illustrating a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure, according to an exemplary embodiment of the present invention.

The circuit diagram ofFIG. 9corresponds to a unit block of the layout of the 4-transistor active pixel sensor array having the 4-pixel shared structure ofFIG. 8. Like reference numerals refer to similar or identical components inFIG. 9andFIG. 8.

Referring toFIG. 9, the 4-transistor CMOS active pixel sensor array having the 4-pixel shared structure includes four photo diode regions PD1, PD2, PD3and PD4, and four transfer transistors M81, M82, M83and M84. Each of the respective transfer transistors corresponds to one of the respective photo diode regions. In an exemplary embodiment of the present invention, the four photo diode regions PD1, PD2, PD3and PD4, and the four transfer transistors M81, M82, M83and M84share a reset transistor M85, a select transistor M86and a source follower transistor M87. In the top plan view illustrating the 4-transistor active pixel sensor array having the 4-pixel shared structure ofFIG. 8, the first floating diffusion node FD1and the second floating diffusion node FD2are shown separately. However, since the first floating diffusion node FD1and the second floating diffusion node FD2are coupled through the metal line821and have a common electric potential, the two nodes are represented as one floating diffusion node FD in the circuit diagram ofFIG. 9.

Unlike the 4-transistor active pixel sensor array having the 4-pixel shared structure ofFIG. 5, the select transistor M86is arranged between the driving voltage and the source follower transistor M87inFIG. 9. The operations of the array ofFIG. 9, however, are similar or identical with the operations of the array shown inFIG. 5

For example, the reset transistor M85resets the voltage of the floating diffusion node FD to the driving voltage VDD. The photoelectrons integrated in the first photo diode PD1, which corresponds to the first transfer transistor M81, are transferred to the floating diffusion node FD by turning on the first transfer transistor M81. The select transistor M86is turned on to couple the drain of the source follower transistor M87to the driving voltage, and the source follower transistor M87samples the voltage of the floating diffusion node FD to output the source voltage of the source follower transistor M87to the internal circuit.

The above-described operations are likewise performed for the second photo diode region PD2and the second transfer transistor M82, the third photo diode region PD3and the third transfer transistor M83, and the fourth photo diode region PD4and the fourth transfer transistor M84.

Exemplary embodiments of the present invention may provide an active pixel sensor array having a shared structure that maintains an optical symmetry of the structure and simultaneously enhances availability and productivity of a manufacturing process. The active pixel sensor array having a shared structure, according to the exemplary embodiments of the present invention, may increase a fill factor.

Although the exemplary embodiments of the present invention have been described with reference to the accompanying drawings for the purpose of illustration, it is to be understood that the inventive processes and apparatus are not to be construed as limited thereby. It will be readily apparent to those of ordinary skill in the art that various modifications to the foregoing exemplary embodiments may be made without materially departing from the scope of the invention as defined by the appended claims, with equivalents of the claims to be included therein.