Inline data inspection for workload simplification

A method, computer readable medium, and system are disclosed for inline data inspection. The method includes the steps of receiving, by a load/store unit, a load instruction and obtaining, by an inspection circuit that is coupled to the load/store unit, data specified by the load instruction. Additional steps include determining that the data equals zero and transmitting the data and a predicate signal to the load/store unit, wherein the predicate signal indicates that the data equals zero. Alternative additional steps include computing a predicate value based on a comparison between the data and a threshold value and transmitting the data and the predicate value to the load/store unit, wherein the predicate value is asserted when the data is less than the threshold value and is negated when the data is not less than the threshold value.

FIELD OF THE INVENTION

The present invention relates to data inspection, and more particularly to data inspection during program instruction execution.

BACKGROUND

For deep learning applications a convolution kernel often operates on data that is sparse, meaning many of the values in the data equal zero. The sparsity can be either in the activations or in the weights. Sparsity in the activations results from rectified linear unit (ReLU) activation functions in a previous layer of the neural network. Sparsity in the weights occurs when the neural network has been pruned to increase accuracy or reduce the model size. Performing arithmetic operations on the elements having zero values is wasteful in terms of processing time and performance because the arithmetic operations do not contribute to the output. There is a need for addressing these issues and/or other issues associated with the prior art.

SUMMARY

A method, computer readable medium, and system are disclosed for inline data inspection. The method includes the steps of receiving, by a load/store unit, a load instruction and obtaining, by an inspection circuit that is coupled to the load/store unit, data specified by the load instruction. Additional steps include determining that the data equals zero and transmitting the data and a predicate signal to the load/store unit, wherein the predicate signal indicates that the data equals zero. Alternative additional steps include computing a predicate value based on a comparison between the data and a threshold value and transmitting the data and the predicate value to the load/store unit, wherein the predicate value is asserted when the data is less than the threshold value and is negated when the data is not less than the threshold value.

DETAILED DESCRIPTION

One solution to avoid performing arithmetic operations on operands (i.e., elements) having a value of zero is to inspect data that has been loaded from memory and will be used as operands for arithmetic operations. However, such an approach necessitates extra instructions to compare values and reduce the results of the comparisons over some number of operands. The number of instruction issue slots that are available to store instructions often also limits the performance of kernel execution, particularly math intensive kernels. Therefore, the extra instructions may harm the performance of the kernel if arithmetic operations are performed and, if the operations are not performed, the achievable performance improvement may be limited by the instruction fetch latency.

An inline data inspection technique eliminates execution of arithmetic operations, such as multiplication, when the input data equals zero. Therefore, in contrast with the prior art, zero detection instructions are not included in the program. In one embodiment, the inline data inspection technique eliminates execution of operations when the input data is less than a threshold value. Therefore, in contrast with the prior art, comparison instructions are not included in the program. As previously explained, because storage for instructions within a processing unit is limited, reducing the instruction footprint for a sequence of instructions is important. No additional instructions are needed to perform the zero detection or the comparisons for the input data.

FIG. 1Aillustrates a flowchart100of a method for inline data inspection, in accordance with one embodiment. Although method100is described in the context of a processing unit, the method100may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method100may be executed by a GPU (graphics processing unit), CPU (central processing unit), deep learning accelerator (DLA), or any processor capable of executing the program instructions. Furthermore, persons of ordinary skill in the art will understand that any system that performs method100is within the scope and spirit of embodiments of the present invention.

At step110, a load/store unit receives a load instruction. Inline data inspection can be implemented by a variety of instructions, including memory loads (moving data from memory to a cache or register file). It is not necessary for every instruction in an instruction set to support the inline data inspection. In one embodiment, inline data inspection for each instruction is enabled and disabled by the instruction. For example, a field in the instruction may include at least one bit that indicates whether inline data inspection is enabled. In one embodiment, the field may indicate whether inline data inspection is enabled, disabled, or determined at the time of execution.

At step120, an inspection circuit that is coupled to the load/store unit obtains data specified by the load instruction. In one embodiment, storage and/or transmission circuits within a cache or memory interface may be configured to inspect the data. At step130, the data is determined to equal zero. In one embodiment, the inspection circuit comprises a zero detection circuit that determines the data equals zero when none of the bits are asserted. In one embodiment, the inspection circuit compares the data with zero to determine whether the data equals zero.

At step140, the data and a predicate signal are transmitted to the load/store unit, where the predicate signal indicates that the data equals zero. In one embodiment, the data is stored in a destination register and a predicate value that is associated with the destination register is set or cleared according to the predicate signal. In another embodiment, the load/store unit stores the predicate value and discards the data by not storing the data in the destination register. The data may include one or more operands for a subsequent instruction.

A sequence of instructions that implements a math kernel may include the load instruction to compute the predicate value and the predicate value may be provided as an operand to a subsequent branch instruction to control execution of the branch instruction. When the branch instruction is executed, the predicate value may cause a branch to be taken, so that execution of the math kernel instructions is avoided. In other words, the predicate signal may be used to branch over a set of program instructions that perform arithmetic operations, so that the set of program instructions is not executed. In one embodiment, multiply operations are not executed when at least one of the operands (e.g., multiplier or multiplicand) equals zero.

An example application of the inline data inspection technique is for input data pruning, particularly for deep learning applications having sparse data. Conventional schemes for input data pruning require inclusion of instructions to detect input data having a value equal to zero or less than a threshold value. In contrast with the conventional schemes, when the inline data inspection technique is employed, the detection of zero and less than threshold values is performed automatically when the input data is received in response to execution of a load instruction and before the input data is stored in a register to complete execution of the load instruction. Importantly, additional instructions, specifically explicit zero detection and comparison instructions, are not included in the program to perform the data inspection.

FIG. 1Billustrates a block diagram of a parallel processing unit135that includes inline data inspection logic, in accordance with one embodiment. The parallel processing unit135includes an instruction cache105, a Load/Store unit154, a register file115, and an inspection circuit170. The instruction cache105is configured to fetch and buffer program instructions, thereby reducing latency incurred to read the instructions from memory. In one embodiment, load instructions are output from the instruction cache105to the load/store unit154. The load instructions are decoded by the load/store unit154and information is provided to a data storage190for reading the data. In one embodiment, the information includes one or more of a read address, a data width, and an enable mask. The data resource190may be a cache, register file, addressable memory, random access memory (RAM), buffer, or the like, that receives an address for at least one operand and outputs data for the at least one operand.

The inspection circuit170is coupled between the load/store unit154and the data storage190. In one embodiment, the inspection circuit170is included within the data storage190. The inspection circuit170receives the data for the at least one operand from the data storage190and computes a predicate value. The data may be represented in a floating point format, an integer format, a fixed point format, or the like. The data may include a single operand value or multiple operand values. For example, the data may include 128 bits representing 4 separate 32 bit values and the predicate that is computed for the data is shared between the 4 separate 32 bit values.

In one embodiment, the predicate value is asserted when the data equals zero and is negated when the predicate value does not equal zero. In another embodiment, the predicate value is asserted when the data is less than a threshold value and is negated when the data is not less than the threshold value (i.e., when the data is greater than or equal to the threshold value). In yet another embodiment, the predicate value is asserted when the data is less than or equal to the threshold value and is negated when the data is greater than the threshold value. In one embodiment, the data is encoded in a floating point format and the inspection circuit170compares one or more exponents of the data to determine whether the data is less than the threshold value. In one embodiment, the inspection circuit170computes statistics associated with a distribution of the data relative to the threshold value and stores the statistics. The statistics may then be used to compute and/or update the threshold value.

The inspection circuit170returns the predicate value to the load/store unit154via a predicate signal. The inspection circuit170also returns the data. The functional unit250receives the data for the at least one operand and, in one embodiment, stores the data in the register file115at a location specified by the load instruction (e.g., a destination address). Alternatively, the functional unit250receives the data for the at least one operand and, discards the data instead of storing the data in the register file115. The load/store unit154may store the predicate value within the load/store unit154or in the register file115.

Inline data inspection may be enabled using two different mechanisms. A first mechanism enables inline data inspection for individual program instructions based on the opcode or an enable field in each instruction. A second mechanism enables and disables inline data inspection by setting and clearing inline data inspection state for a sequence of one or more program instructions. In one embodiment, the inspection circuit170outputs the predicate value only when inline data inspection is enabled.

FIG. 1Cillustrates another flowchart of a method150for inline data inspection, in accordance with one embodiment. Although method150is described in the context of a processing unit, the method150may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method150may be executed by a GPU, CPU, DLA, or any processor capable of executing the program instructions. Furthermore, persons of ordinary skill in the art will understand that any system that performs method150is within the scope and spirit of embodiments of the present invention.

Operations110and120are completed as previously described in conjunction withFIG. 1A. At step135, a predicate value is computed based on a comparison between the data and a threshold value. The threshold value may be one of a fixed value or a programmed value. A fixed value may be determined through simulations and then hard-wired into the inspection circuit170. In one embodiment, a programmable threshold value may be provided with each load instruction. In another embodiment, a programmable threshold value may be stored in a configuration register and can be programmed dynamically by a dedicated program instruction. For example, in the case of a neural network, the threshold value may be determined during the training phase of the neural network. The threshold value may also be computed and/or updated by the program itself during the inference phase of the neural network. In one embodiment, the threshold value is computed to cause a predetermined portion of the data to be less than the threshold value. For example, the threshold value may be computed to cause 10% of the data to be less than the threshold value so that 10% of the data is effectively removed. In another embodiment, the threshold value is computed to cause a predetermined portion of the data to be greater than the threshold value. In yet another embodiment, the threshold value is computed to cause a predetermined portion of the data to be centered around the threshold value.

At step145, the data and the predicate value are transmitted to the load/store unit154. In one embodiment, the inspection circuit170comprises a comparison circuit that asserts the predicate value when the data is less than the threshold value and negates the predicate value when the data is not less than the threshold value. In one embodiment, the data is stored in a destination register in the register file115and a predicate value that is associated with the destination register is set or cleared according to the predicate signal. In another embodiment, the load/store unit stores the predicate value and discards the data by not storing the data in the destination register.

The predicate value may be used to control whether one or more subsequent instructions in the program are executed. Therefore, input data pruning may be performed automatically by the inspection circuit170without requiring inclusion of additional instructions, specifically without requiring explicit instructions in a program to perform zero detection or comparison to a threshold value.

FIG. 2Aillustrates a block diagram of the inspection circuit170shown inFIG. 1B, in accordance with one embodiment. The inspection circuit170includes a zero detection unit210, a threshold compare unit, and a multiplexer220. The zero detection unit210receives the data and determines if the data equals zero. The zero predicate is asserted if the data equals zero and the zero predicate is negated if the data does not equal zero.

The threshold compare unit215compares the data to a threshold value and asserts the threshold predicate if the data is less than the threshold value and negates the threshold predicate if the data is not less than the threshold value. The threshold value may be received from the load/store unit154along with the data. The threshold value may be fixed, included with the load instruction, or may be provided with a different instruction and stored in a register.

In one embodiment, the data is encoded in a floating point format and the threshold compare unit215compares one or more exponents of the data to determine whether the data is less than the threshold value and the one or more mantissa are not considered. For example, the threshold compare unit215may determine the data is less than the threshold value when the exponent has zeros in a predetermined number of most significant bit positions.

Based on a mode, the multiplexer220selects either the zero predicate or the threshold predicate for output as the predicate. In one embodiment the mode is received from the load/store unit154along with the data. The mode may be received from the load/store unit154along with the data. The mode may be fixed, included with the load instruction, or may be provided with a different instruction and stored in a register.

In one embodiment, a statistics unit218within the inspection circuit170computes statistics associated with a distribution of the data relative to the threshold value. The statistics may indicate a portion of the data for which the threshold predicate is asserted and the statistics may be stored in the statistics unit218. In one embodiment, the statistics are reset by an instruction. Statistics may be gathered for one layer of a neural network and then a threshold value may be computed for a subsequent layer based on the gathered statistics. In one embodiment, statistics may be gathered for a portion of a layer, and the gathered statistics may be used to compute a threshold value for the remaining portions of the layer. In one embodiment, based on the statistics, the statistics unit218may determine a threshold value that will cause a predetermined portion of the data to be less than the threshold value. In another embodiment, based on the statistics, the statistics unit218may determine a threshold value that will cause a predetermined portion of the data to be greater than the threshold value. In yet another embodiment, based on the statistics, the statistics unit218may determine a threshold value that will cause a predetermined portion of the data to be centered around the threshold value.

FIG. 2Billustrates fields of an instruction230that initiates inline data inspection, in accordance with one embodiment. The instruction includes an opcode field235and at least a destination register (dst reg) field250, and a read address field265. The read address field265specifies the location in the data storage where the data is stored. The opcode field235specifies the operation performed by the instruction230. In one embodiment, the operation is a load operation. The dst reg field250encodes the location in the register file115where the data that is read when the instruction230is executed will be stored. In one embodiment, the instruction230also includes predicate field245so that inline data inspection can be selectively enabled or disabled for when the instruction230is executed.

In one embodiment, a width field240specifies a width of the data (e.g., 32 bits, 64 bits, 128 bits, and the like). In one embodiment, a mode field260specifies whether the inline data inspection detects data equal to zero or data that is less than a threshold value. In one embodiment, when inline data inspection is enabled using a threshold value, the threshold field255specifies the threshold value. In one embodiment, an enable field270includes an enable mask for the data where each bit in the mask indicates whether one or more bytes or operands in the data may be ignored for computing the predicate.

In one embodiment, different opcodes are specified for a “normal” instruction and an “inline data inspection” version of the same instruction. Providing two different versions of the instruction allows a compiler or programmer to simply replace individual normal instructions with inline data inspection instructions to implement inline data inspection.

FIG. 2Cillustrates a conceptual diagram of an arithmetic operation for a tile of data, in accordance with one embodiment. A multiply operation of two vectors A and B, each of including 8 elements may be performed to compute products for an 8×8 tile. Registers P0and P2each store 4 elements of A and registers P1and P3each store 4 elements of B. If the predicate value is asserted, indicating that the data stored in P0equals zero or is less than a threshold value, then multiply operations for two of the 4×4 portions within the 8×8 tile may be avoided. Similarly, if one or more predicate values are asserted, indicating that the data stored in P2, P1, and/or P3equals zero or is less than a threshold value, then multiply operations for two of the 4×4 portions within the 8×8 tile may be avoided. In one embodiment, statistics may be gathered for one or more tiles of a neural network layer and the remaining tiles in the neural network layer may be clamped to the computed threshold value.

FIG. 2Dillustrates pseudo-code including instructions that initiate inline data inspection, in accordance with one embodiment. The FLOP3.AND instructions initialize predicate values stored in registers P4and P5in the register file115. Register P4stores the predicate value for the vector A having elements stored in registers P0and P2. The value in register P4is computed as the AND of the predicate values for registers P0and P2. Register P5stores the predicate value for the vector B having elements stored in registers P1and P3. The value in register P5is computed as the AND of the predicate values for registers P1and P3.

The LDS.128 instructions are load instructions for 128 bits data. When executed by the load/store unit154, the four load instructions read data from the data storage190and load the data into the registers P0, P1, P2, and P3in the register file115. When the four load instructions are received by the inspection circuit170, the corresponding predicate values are computed for the data to be stored in the registers P0, P1, P2, and P3. The FLOP3.OR instruction computes a tile predicate value by ORing the predicate value for vector A (stored in register P4) and the predicate value for vector B (stored in register P5). The tile predicate value is stored into register P4.

The BRANCH instruction is conditionally executed based on the tile predicate value stored in register P4. When the tile predicate value is asserted, the branch to the label NextK is taken and the instructions290are not executed. Therefore, with at least one of the vectors A and B has a predicate value that is asserted, the branch is taken and the instructions290are not executed. In one embodiment, the instructions290include one or more instructions following the branch instruction and that perform arithmetic operations using vectors A and/or B as input operands. Performing the inline data inspection to compute predicate values for the operands enables conditional execution of the instructions290. Avoiding execution of instructions that perform unnecessary arithmetic operations improves processing performance and reduces power consumption. Importantly, no additional instructions are included in the program to perform the inline data inspection and no additional instructions stored in the instruction cache105to perform the inline data inspection.

Parallel Processing Architecture

FIG. 3illustrates a parallel processing unit (PPU)300, in accordance with one embodiment. The PPU300may be configured to implement inline data inspection when instructions are executed. In one embodiment, the PPU300includes one or inspection circuits170.

In one embodiment, the PPU300is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU300is a latency hiding architecture designed to process many threads in parallel. A thread (i.e., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU300. In one embodiment, the PPU300is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU300may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

As shown inFIG. 3, the PPU300includes an Input/Output (I/O) unit305, a host interface unit310, a front end unit315, a scheduler unit320, a work distribution unit325, a hub330, a crossbar (Xbar)370, one or more general processing clusters (GPCs)350, and one or more partition units380. The PPU300may be connected to a host processor or other peripheral devices via a system bus302. The PPU300may also be connected to a local memory comprising a number of memory devices304. In one embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices.

The I/O unit305is configured to transmit and receive communications (i.e., commands, data, etc.) from a host processor (not shown) over the system bus302. The I/O unit305may communicate with the host processor directly via the system bus302or through one or more intermediate devices such as a memory bridge. In one embodiment, the I/O unit305implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus. In alternative embodiments, the I/O unit305may implement other types of well-known interfaces for communicating with external devices.

The I/O unit305is coupled to a host interface unit310that decodes packets received via the system bus302. In one embodiment, the packets represent commands configured to cause the PPU300to perform various operations. The host interface unit310transmits the decoded commands to various other units of the PPU300as the commands may specify. For example, some commands may be transmitted to the front end unit315. Other commands may be transmitted to the hub330or other units of the PPU300such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the host interface unit310is configured to route communications between and among the various logical units of the PPU300.

In one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU300for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (i.e., read/write) by both the host processor and the PPU300. For example, the host interface unit310may be configured to access the buffer in a system memory connected to the system bus302via memory requests transmitted over the system bus302by the I/O unit305. In one embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU300. The host interface unit310provides the front end unit315with pointers to one or more command streams. The front end unit315manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU300.

The front end unit315is coupled to a scheduler unit320that configures the various GPCs350to process tasks defined by the one or more streams. The scheduler unit320is configured to track state information related to the various tasks managed by the scheduler unit320. The state may indicate which GPC350a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit320manages the execution of a plurality of tasks on the one or more GPCs350.

The scheduler unit320is coupled to a work distribution unit325that is configured to dispatch tasks for execution on the GPCs350. The work distribution unit325may track a number of scheduled tasks received from the scheduler unit320. In one embodiment, the work distribution unit325manages a pending task pool and an active task pool for each of the GPCs350. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC350. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs350. As a GPC350finishes the execution of a task, that task is evicted from the active task pool for the GPC350and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC350. If an active task has been idle on the GPC350, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC350and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC350.

The work distribution unit325communicates with the one or more GPCs350via XBar370. The XBar370is an interconnect network that couples many of the units of the PPU300to other units of the PPU300. For example, the XBar370may be configured to couple the work distribution unit325to a particular GPC350. Although not shown explicitly, one or more other units of the PPU300are coupled to the host interface unit310. The other units may also be connected to the XBar370via a hub330.

The tasks are managed by the scheduler unit320and dispatched to a GPC350by the work distribution unit325. The GPC350is configured to process the task and generate results. The results may be consumed by other tasks within the GPC350, routed to a different GPC350via the XBar370, or stored in the memory304. The results can be written to the memory304via the partition units380, which implement a memory interface for reading and writing data to/from the memory304. In one embodiment, the PPU300includes a number U of partition units380that is equal to the number of separate and distinct memory devices304coupled to the PPU300. A partition unit380will be described in more detail below in conjunction withFIG. 4B.

In one embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU300. An application may generate instructions (i.e., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU300. The driver kernel outputs tasks to one or more streams being processed by the PPU300. Each task may comprise one or more groups of related threads, referred to herein as a warp. A thread block may refer to a plurality of groups of threads including instructions to perform the task. Threads in the same group of threads may exchange data through shared memory. In one embodiment, a group of threads comprises 32 related threads.

FIG. 4Aillustrates a GPC350within the PPU300ofFIG. 3, in accordance with one embodiment. As shown inFIG. 4A, each GPC350includes a number of hardware units for processing tasks. In one embodiment, each GPC350includes a pipeline manager410, a pre-raster operations unit (PROP)415, a raster engine425, a work distribution crossbar (WDX)480, a memory management unit (MMU)490, and one or more Texture Processing Clusters (TPCs)420. It will be appreciated that the GPC350ofFIG. 4Amay include other hardware units in lieu of or in addition to the units shown inFIG. 4A.

In one embodiment, the operation of the GPC350is controlled by the pipeline manager410. The pipeline manager410manages the configuration of the one or more TPCs420for processing tasks allocated to the GPC350. In one embodiment, the pipeline manager410may configure at least one of the one or more TPCs420to implement at least a portion of a graphics rendering pipeline. For example, a TPC420may be configured to execute a vertex shader program on the programmable streaming multiprocessor (SM)440. The pipeline manager410may also be configured to route packets received from the work distribution unit325to the appropriate logical units within the GPC350. For example, some packets may be routed to fixed function hardware units in the PROP415and/or raster engine425while other packets may be routed to the TPCs420for processing by the primitive engine435or the SM440.

The PROP unit415is configured to route data generated by the raster engine425and the TPCs420to a Raster Operations (ROP) unit in the partition unit380, described in more detail below. The PROP unit415may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like.

Each TPC420included in the GPC350includes an M-Pipe Controller (MPC)430, a primitive engine435, one or more SMs440, and one or more texture units445. The MPC430controls the operation of the TPC420, routing packets received from the pipeline manager410to the appropriate units in the TPC420. For example, packets associated with a vertex may be routed to the primitive engine435, which is configured to fetch vertex attributes associated with the vertex from the memory304. In contrast, packets associated with a shader program may be transmitted to the SM440.

In one embodiment, the texture units445are configured to load texture maps (e.g., a 2D array of texels) from the memory304and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM440. The texture units445implement texture operations such as filtering operations using mip-maps (i.e., texture maps of varying levels of detail). The texture unit445is also used as the Load/Store path for SM440to MMU490. In one embodiment, each TPC420includes two (2) texture units445.

The SM440comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM440is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In one embodiment, the SM440implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (i.e., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM440implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In other words, when an instruction for the group of threads is dispatched for execution, some threads in the group of threads may be active, thereby executing the instruction, while other threads in the group of threads may be inactive, thereby performing a no-operation (NOP) instead of executing the instruction. The SM440is described in more detail below in conjunction withFIG. 5.

The MMU490provides an interface between the GPC350and the partition unit380. The MMU490may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In one embodiment, the MMU490provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory304.

FIG. 4Billustrates a memory partition unit380of the PPU300ofFIG. 3, in accordance with one embodiment. As shown inFIG. 4B, the memory partition unit380includes a Raster Operations (ROP) unit450, a level two (L2) cache460, a memory interface470, and an L2 crossbar (XBar)465. The memory interface470is coupled to the memory304. Memory interface470may implement 16, 32, 64, 128-bit data buses, or the like, for high-speed data transfer. In one embodiment, the PPU300incorporates U memory interfaces470, one memory interface470per partition unit380, where each partition unit380is connected to a corresponding memory device304. For example, PPU300may be connected to up to U memory devices304, such as graphics double-data-rate, version 5, synchronous dynamic random access memory (GDDR5 SDRAM). In one embodiment, the memory interface470implements a DRAM interface and U is equal to 8.

In one embodiment, the PPU300implements a multi-level memory hierarchy. The memory304is located off-chip in SDRAM coupled to the PPU300. Data from the memory304may be fetched and stored in the L2 cache460, which is located on-chip and is shared between the various GPCs350. As shown, each partition unit380includes a portion of the L2 cache460associated with a corresponding memory device304. Lower level caches may then be implemented in various units within the GPCs350. For example, each of the SMs440may implement a level one (L1) cache. The L1 cache is private memory that is dedicated to a particular SM440. Data from the L2 cache460may be fetched and stored in each of the L1 caches for processing in the functional units of the SMs440. The L2 cache460is coupled to the memory interface470and the XBar370.

The ROP unit450includes a ROP Manager455, a Color ROP (CROP) unit452, and a Z ROP (ZROP) unit454. The CROP unit452performs raster operations related to pixel color, such as color compression, pixel blending, and the like. The ZROP unit454implements depth testing in conjunction with the raster engine425. The ZROP unit454receives a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine425. The ZROP unit454tests the depth against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ZROP unit454updates the depth buffer and transmits a result of the depth test to the raster engine425. The ROP Manager455controls the operation of the ROP unit450. It will be appreciated that the number of partition units380may be different than the number of GPCs350and, therefore, each ROP unit450may be coupled to each of the GPCs350. Therefore, the ROP Manager455tracks packets received from the different GPCs350and determines which GPC350that a result generated by the ROP unit450is routed to. The CROP unit452and the ZROP unit454are coupled to the L2 cache460via an L2 XBar465.

FIG. 5illustrates the streaming multi-processor440ofFIG. 4A, in accordance with one embodiment. As shown inFIG. 5, the SM440includes an instruction cache505, one or more scheduler units510, a register file520, one or more processing cores550, one or more special function units (SFUs)552, one or more load/store units (LSUs)554, an interconnect network580, a shared memory/L1 cache570. In one embodiment, the instruction cache105, the load/store unit154, and the register file115, shown inFIG. 1Bis the instruction cache505, the load/store unit (LSU)554, and the register file520, respectively.

As described above, the work distribution unit325dispatches tasks for execution on the GPCs350of the PPU300. The tasks are allocated to a particular TPC420within a GPC350and, if the task is associated with a shader program, the task may be allocated to an SM440. The scheduler unit510receives the tasks from the work distribution unit325and manages instruction scheduling for one or more groups of threads (i.e., warps) assigned to the SM440. The scheduler unit510schedules threads for execution in groups of parallel threads, where each group is called a warp. In one embodiment, each warp includes 32 threads. The scheduler unit510may manage a plurality of different warps, scheduling the warps for execution and then dispatching instructions from the plurality of different warps to the various functional units (i.e., cores550, SFUs552, and LSUs554) during each clock cycle.

Each dispatch unit515is configured to transmit instructions to one or more of the functional units. In the embodiment shown inFIG. 5, the scheduler unit510includes two dispatch units515that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit510may include a single dispatch unit515or additional dispatch units515.

Each SM440includes a register file520that provides a set of registers for the functional units of the SM440. In one embodiment, the register file520is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file520. In another embodiment, the register file520is divided between the different warps being executed by the SM440. The register file520provides temporary storage for operands connected to the data paths of the functional units.

Each SM440comprises L processing cores550. In one embodiment, the SM440includes a large number (e.g., 128, etc.) of distinct processing cores550. Each core550may include a fully-pipelined, single-precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. The core550may also include a double-precision processing unit including a floating point arithmetic logic unit. In one embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. Each SM440also comprises M SFUs552that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like), and N LSUs554that implement load and store operations between the shared memory/L1 cache570and the register file520. In one embodiment, the SM440includes 128 cores550,32SFUs552, and32LSUs554.

Each SM440includes an interconnect network580that connects each of the functional units to the register file520and the LSU554to the register file520, shared memory/L1 cache570. In one embodiment, the interconnect network580is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file520and connect the LSUs554to the register file and memory locations in shared memory/L1 cache570.

The shared memory/L1 cache570is an array of on-chip memory that allows for data storage and communication between the SM440and the primitive engine435and between threads in the SM440. In one embodiment, the shared memory/L1 cache570comprises 64 KB of storage capacity and is in the path from the SM440to the partition unit380. The shared memory/L1 cache570can be used to cache reads and writes. In one embodiment, the shared memory/L1 cache570includes the inspection circuit170to perform inline data inspection for load operations. In one embodiment, at least one inspection circuit170is positioned between the shared memory/L1 cache570and the LSUs554.

The PPU300described above may be configured to perform highly parallel computations much faster than conventional CPUs. Parallel computing has advantages in graphics processing, data compression, neural networks, deep learning, biometrics, stream processing algorithms, and the like.

When configured for general purpose parallel computation, a simpler configuration can be used. In this model, as shown inFIG. 3, fixed function graphics processing units are bypassed, creating a much simpler programming model. In this configuration, the work distribution unit325assigns and distributes blocks of threads directly to the TPCs420. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM440to execute the program and perform calculations, shared memory/L1 cache570to communicate between threads, and the LSU554to read and write Global memory through partition shared memory/L1 cache570and partition unit380. When configured for general purpose parallel computation, the SM440can also write commands that scheduler unit320can use to launch new work on the TPCs420.

In one embodiment, the PPU300comprises a deep learning or machine learning processor. The PPU300is configured to receive commands that specify programs for modeling neural networks and processing data according to a neural network.

In one embodiment, the PPU300comprises a graphics processing unit (GPU). The PPU300is configured to receive commands that specify shader programs for processing graphics data. Graphics data may be defined as a set of primitives such as points, lines, triangles, quads, triangle strips, and the like. Typically, a primitive includes data that specifies a number of vertices for the primitive (e.g., in a model-space coordinate system) as well as attributes associated with each vertex of the primitive. The PPU300can be configured to process the graphics primitives to generate a frame buffer (i.e., pixel data for each of the pixels of the display).

An application writes model data for a scene (i.e., a collection of vertices and attributes) to a memory such as a system memory or memory304. The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel that requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. The commands may reference different shader programs to be implemented on the SMs440of the PPU300including one or more of a vertex shader, hull shader, domain shader, geometry shader, and a pixel shader. For example, one or more of the SMs440may be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In one embodiment, the different SMs440may be configured to execute different shader programs concurrently. For example, a first subset of SMs440may be configured to execute a vertex shader program while a second subset of SMs440may be configured to execute a pixel shader program. The first subset of SMs440processes vertex data to produce processed vertex data and writes the processed vertex data to the L2 cache460and/or the memory304. After the processed vertex data is rasterized (i.e., transformed from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of SMs440executes a pixel shader to produce processed fragment data, which is then blended with other processed fragment data and written to the frame buffer in memory304. The vertex shader program and pixel shader program may execute concurrently, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. Then, the contents of the frame buffer are transmitted to a display controller for display on a display device.

The PPU300may be included in a desktop computer, a laptop computer, a tablet computer, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a hand-held electronic device, and the like. In one embodiment, the PPU300is embodied on a single semiconductor substrate. In another embodiment, the PPU300is included in a system-on-a-chip (SoC) along with one or more other logic units such as a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In one embodiment, the PPU300may be included on a graphics card that includes one or more memory devices304such as GDDR5 SDRAM. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer that includes, e.g., a northbridge chipset and a southbridge chipset. In yet another embodiment, the PPU300may be an integrated graphics processing unit (iGPU) included in the chipset (i.e., Northbridge) of the motherboard.

Various programs may be executed within the PPU300in order to implement the various layers of a neural network. For example, the device driver may launch a kernel on the PPU300to implement the neural network on one SM440(or multiple SMs440). The device driver (or the initial kernel executed by the PPU300) may also launch other kernels on the PPU300to perform other layers of the neural network. In addition, some of the layers of the neural network may be implemented on fixed unit hardware implemented within the PPU300. It will be appreciated that results from one kernel may be processed by one or more intervening fixed function hardware units before being processed by a subsequent kernel on an SM440.

Exemplary System

FIG. 6illustrates an exemplary system600in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system600may be configured to support inline data inspection.

As shown, a system600is provided including at least one central processor601that is connected to a communication bus602. The communication bus602may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). In one embodiment, the communication bus602is the system bus302shown inFIG. 3. The system600also includes a main memory604. Control logic (software) and data are stored in the main memory604which may take the form of random access memory (RAM).

The system600also includes input devices612, a graphics processor606, and a display608, i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices612, e.g., keyboard, mouse, touchpad, microphone, and the like. In one embodiment, the graphics processor606may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU).

Computer programs, or computer control logic algorithms, may be stored in the main memory604and/or the secondary storage610. Such computer programs, when executed, enable the system600to perform various functions. The memory604, the storage610, and/or any other storage are possible examples of computer-readable media.

In one embodiment, the architecture and/or functionality of the various previous figures may be implemented in the context of the central processor601, the graphics processor606, an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the central processor601and the graphics processor606, a chipset (i.e., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.

Further, while not shown, the system600may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) for communication purposes.