Hierarchical word line structure

A hierarchical word line structure for a semiconductor memory is provided that substantially eliminates coupling noise between neighboring wiring lines by driving neighboring sub-word lines by different main word lines. The hierarchical word line structure further reduces a layout size. The hierarchical word line structure uses one less transistor than a related art sub-word line driver. The word line includes a plurality of word line rows that each include a plurality of sub-word line drivers. The sub-word line drivers receive sub-word line driver enable signals among which only one signal becomes high level at a time. Each of the word line rows correspond to a main word line and a subset of the plurality of sub-word line drivers that drive neighboring sub-word lines are coupled to different respective main word lines.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a semiconductor device, and in particular, 
to a hierarchical word line structure of a semiconductor memory device. 
2. Background of the Related Art 
FIG. 1 illustrates a related art hierarchical word line structure. As shown 
in FIG. 1, the related art hierarchical word line structure includes a 
plurality of word line rows R1, R2, and R3 each including sub-word line 
drivers SWD0 through SWD3. 
For example, the first word line row R1 includes a sub-word line driver 
SWD0 connected with a pair of main word lines MWL0 and MWL0b. The sub-word 
line driver SWD0 receives a sub-word line driver enable signal SWDEN0 and 
drivers a sub-word line SWL0. A sub-word line driver SWD1 is connected 
with the main word lines MWL0 and MWL0b. The sub-word line driver SWD1 
receives a sub-word line driver enable signal SWDEN1 and drives a sub-word 
line SWL1. A sub-word line driver SWD2 is connected with the main word 
lines MWL0 and MWL0b. The sub-word line driver SWD2 receives a sub-word 
line driver enable signal SWDEN2 and drives a sub-word line SWL2. A 
sub-word line driver SWD3 is connected with the main word lines MWL0 and 
MWL0b. The sub-word line driver SWD3 receives a sub-word line driver 
enable signal SWDEN3 and drives a sub-word line SWL3. 
The main word lines MWL0 and MWL0b are complementary to each other. The 
sub-word line driver enable signals SWDEN0, SWDEN1, SWDEN2, and SWDEN3 are 
one bit signals of a row address. Among the above-described signals, only 
one signal becomes high level at a time. 
The second word line row R2 includes sub-word line drivers SWD0 through 
SWD3 connected with a pair of main word lines MWL1 and MWL1b. In the 
second word line row R2, the sub-word line drivers SWD0 through SWD3 
receive sub-word line driver enable signals SWDEN0 through SWDEN3 and 
drive sub-word lines SWL4 through SWL7. In addition, the third word line 
row R3 includes sub-word line drivers SWD0 through SWD3 connected with a 
pair of main word lines MWL2 and MWL2b for receiving sub-word line driver 
enable signals SWDEN0 through SWDEN3. 
As shown in FIG. 2, the sub-word line driver SWD0 includes a PMOS 
transistor MP1 whose gate is connected with the main word line MWL0b. The 
source of the PMOS transistor MP1 receives the sub-word line driver enable 
signal SWDEN0, and the drain is connected with the sub-word line SWL0. An 
NMOS transistor MN1 has its gate connected with the main word line MWL0b. 
The drain of the NMOS transistor MN1 is connected with the sub-word line 
SWL0, and the source is connected to ground. An NMOS transistor MN2 has 
its gate connected with the main word line MWL0. The drain of the NMOS 
transistor MN2 receives the sub-word line driver enable signal SWDEN0, and 
the source is connected with the sub-word line SWL0. The sub-word line 
drivers SWD1 through SWD3 have the same construction as the sub-word line 
driver SWD0. 
The operation of the related art hierarchical word line structure will now 
be described. When a high level signal is inputted to the main word line 
MWL0, the first word line row R1 is selected, and the NMOS transistor MN2 
of the sub-word line driver SWD0 is turned on. The main word line MWL0 is 
an upper word line. Sequentially, a low level signal is applied to the 
main word line MWL0b, and the PMOS transistor MP1 is turned on and the 
NMOS transistor MN1 is turned off. When a high level sub-word line driver 
enable signal SWDENO is applied to the sub-word line driver SWD0, a high 
level signal is outputted to the sub-word line SWL0 to drive an actual 
word line. 
However, an important factor when driving the word line is a coupling 
noise. The sub-word line that receives much coupling noise during the 
driving of the sub-word line SWL0 is sub-word line SWL2. Namely, as shown 
in FIG. 3, when the sub-word line SWL0 is driven by the sub-word line 
driver SWD0, a coupling noise can be applied to the sub-word line SWL2. 
The sub-word line SWL2 is driven by the sub-word line driver SWD2. At this 
time, the PMOS transistor MP1' and the NMOS transistor MN2' of the 
sub-word line driver SWD2 are turned on, while the NMOS transistor MN1' is 
turned off. In addition, a low level sub-word line driver enable signal 
SWDEN2 is applied to the source of the PMOS transistor MP1' and the drain 
of the NMOS transistor MN2', respectively. 
However, the related art hierarchical word line structure has various 
disadvantages because a pair of main word lines MWL0 and MWL0b and 
sub-word line driver enable signals SWDEN0, SWDEN1 or SWDEN2, SWDEN3 are 
used. A coupling noise can appear between adjacent sub-word line drivers. 
Further, an additional sub-word line driver is needed relative to a word 
line shunt method. In addition, the layout size is disadvantageously 
increased. 
SUMMARY OF THE INVENTION 
An object of the present invention to provide a hierarchical word line 
structure that substantially overcomes at least the aforementioned 
problems encountered in the related art. 
Another object of the present invention to provide a hierarchical word line 
structure that eliminates a coupling noise by driving neighboring sub-word 
lines using different main word lines. 
Yet another object of the present invention is to provide a hierarchical 
word line structure having fewer transistors to decrease a layout size. 
To achieve at least the above objects in whole or in parts, there is 
provided a word line circuit according to the present invention that 
includes a plurality of word line rows, each word line row including a 
pair of sub-word line drivers which receive sub-word line driver enable 
signals. Among the pair of sub-word line drivers, only one signal becomes 
high level at a time. Further, the word line rows correspond to each main 
word line, and pairs of sub-word line drivers for driving neighboring 
sub-word lines among the sub-word lines are coupled with another main word 
line. 
To achieve the above objects in whole or in parts, there is provided a 
hierarchical word line circuit for a semiconductor memory device according 
to the present invention that includes a plurality of word lines; and a 
plurality of word line rows, each word line row including a plurality of 
sub-word line driving units for receiving at least one sub-word line 
driver enable signals, wherein each of the word line rows correspond to 
one of the plurality of word lines, and wherein each of the plurality of 
the sub-word line driving units are coupled with different word lines of 
the plurality of word lines. 
Additional advantages, objects, and features of the invention will be set 
forth in part in the description which follows and in part will become 
apparent to those having ordinary skill in the art upon examination of the 
following or may be learned from practice of the invention. The objects 
and advantages of the invention may be realized and attained as 
particularly pointed out in the appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
FIG. 4 illustrates a hierarchical word line structure according to a first 
preferred embodiment of the present invention. As shown in FIG. 4, the 
first preferred embodiment of hierarchical word line structure includes a 
plurality of word line rows R1 through Rn that correspond with a plurality 
of main word lines MWL0b through MWLnb. Each of the word line rows R1 
through Rn includes a pair of sub-word line drivers SWD0 and SWD1, a pair 
of sub-word line drivers SWD2 and SWD3 or the like. The sub-word line 
drivers SWD0 and SWD1 receive a pair of complementary sub-word line driver 
enable signals SWDEN0 and SWDEN1. The sub-word line drivers SWD2 and SWD3 
receive a pair of complementary sub-word line driver enable signals SWDEN2 
and SWDEN3. 
The first main word line MWL0b among the main word lines MWL0b through 
MWLnb is coupled to only a pair of sub-word line drivers SWD0 and SWD1 
that are (2n+1)th drivers included in the first word line row R1. The 
remaining main word lines MWL1b, MWL2b, . . . , MWLnb are coupled to the 
pair of the (2n+1)th sub-word line drivers SWD0 and SWD1 of a 
corresponding word line row and the pair of the (2n)th sub-word line 
drivers SWD2 and SWD3 of the previous word line row, respectively. In 
addition, the pair of the (2n)th sub-word line drivers SWD2 and SWD3 
included in the last word line row Rn are coupled to the first main word 
line MWL0b. 
The sub-word line drivers SWD0 and SWD1 included in the first word line row 
R1 are coupled with the sub-word lines SWL0 and SWL1, and the sub-word 
line drivers SWD2 and SWD3 are coupled with the sub-word lines SWL6 and 
SWL7. The sub-word line drivers SWD0 and SWD1 included in the second word 
line row R2 are coupled with the sub-word lines SWL4 and SWL5. The 
sub-word line drivers SWD2 and SWD3 included in the last word line row Rn 
are coupled with the sub-word lines SWL2 and SWL3. 
As shown in FIG. 5, the sub-word line driver SWD0 includes a PMOS 
transistor MP11 has the gate coupled with the main word line MWL0b. The 
source of the PMOS transistor MP11 receives a sub-word line driver enable 
signal SWDEN0, and the drain is coupled with the sub-word line SWL0. An 
NMOS transistor MN11 has the gate coupled with the main word line MWL0b. 
The drain of the NMOS transistor MN11 is coupled with the sub-word line 
SWL0, and the source is coupled with a ground. 
Operations of the first preferred embodiment of the hierarchical word line 
structure according to the present invention will now be described. The 
main word lines MWL0b through MWLnb are driven by a low level signal, and 
the sub-word line driver enable signals SWDEN0, SWDEN1, SWDEN2, and SWDEN3 
are inputted into the sub-word line drivers SWD0 through SWD3 of each of 
the word line rows R1 through Rn, similar to the related art. When a low 
level signal is applied to the main word line MWL0b, the first word line 
row R1 is selected. At this time, the PMOS transistor MP11 is turned on, 
and the NMOS transistor MN11 is turned off. Additionally, when a high 
level sub-word line driver enable signal SWDEN0 is applied to the sub-word 
line driver SWD0, a high level signal is outputted to the sub-word line 
SWL0 to drive an actual word line. 
As shown in FIG. 6, when the sub-word line SWL0 is driven by the sub-word 
line driver SWD0, a coupling noise may arise in the sub-word line SWL6, 
which is driven by the sub-word line driver SWD2. At this time, a high 
level signal is applied to the main word line MWL1b. Consequentially, a 
PMOS transistor MP11' of the sub-word line driver SWD2 is turned off, and 
an NMOS transistor MN11' is turned on. In addition, a low level sub-word 
line driver enable signal SWDEN2 is applied to the source of the PMOS 
transistor MP11'. Therefore, a coupling noise arising in the sub-word line 
SWL6 is shunted to ground through the NMOS transistor MN11'. Thus, the 
coupling noise is substantially eliminated. 
A second preferred embodiment of the hierarchical word line structure 
according to the present invention is shown in FIG. 7. Each of the word 
line rows R1 through Rn in FIG. 7 may include one sub-word line driver 
SWD0 or SWD1. Operations of the second preferred embodiment are similar to 
the first preferred embodiment. Accordingly, a detailed description is 
omitted. 
A third preferred embodiment of a hierarchical word line structure 
according to the present invention shown in FIG. 8. Each of the word line 
rows R1 through Rn in FIG. 8 may include four sub-word line drivers SWD0 
through SWD3 or SWD4 through SWD7. Sub-word line driver enable signals 
SWDEN0 through SWDEN3 are applied to the pairs of the (2n+1)th sub-word 
line drivers SWD0 through SWD3 of each of the word line rows R1 through 
Rn. Sub-word line driver enable signals SWDEN4 through SWDEN7 are applied 
to the pairs of the (2n)th sub-word line drivers SWD4 through SWD7. 
Operations of the third preferred embodiment are similar to the first 
preferred embodiment. Accordingly, a detailed description is omitted. 
As described above, the preferred embodiments of the hierarchical word line 
structure according to the present invention have various advantages. The 
preferred embodiments avoid a narrow pitch problem of a word line wiring 
by driving neighboring sub-word lines by using different main word lines. 
Further, the preferred embodiment allows a layout size to be decreased. 
The foregoing embodiments are merely exemplary and are not to be construed 
as limiting the present invention. The present teaching can be readily 
applied to other types of apparatuses. The description of the present 
invention is intended to be illustrative, and not to limit the scope of 
the claims. Many alternatives, modifications, and variations will be 
apparent to those skilled in the art.