Non-volatile memory with capacitors using metal under signal line or above a device capacitor

A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

BACKGROUND

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory).

Memory systems can be used to store data provided by a host device, client, user or other entity. It is important that the memory system function properly so that data can be stored in the memory system and read back accurately.

DETAILED DESCRIPTION

A memory die is a semiconductor die that has a memory system implemented thereon. Typically, a memory die has a memory structure, peripheral circuits connected to the memory structure and an Input/Output (“I/O”) interface connected to the peripheral circuits and the memory structure. For purposes of this document, an I/O interface is a structure that serves as the point where signals inside the memory die meet signals outside the memory die. One embodiment of an I/O interface includes a set of I/O pads, which allow signals internal to the memory die to connect to the world outside of the memory die. In some examples, the I/O pads are connected to I/O pins of a package or to wires. In some embodiments of a memory die, the set of I/O pads of the I/O interface includes data/control I/O pads for data signals and/or control signals, power I/O pads for power, and ground I/O pads to connect to ground.

Due to active switching of the inputs and outputs of a memory die, there can be large swings in current on a power I/O pad. This change in the current on the power I/O pad can lead to distortion of other signals. For example, some memory die have a clock I/O pad, for a synchronization clock signal. The change in the current on the power I/O pad can lead to distortion of the synchronization clock signal so that the duty cycle of the synchronization clock signal is altered in a manner that prevents the synchronization clock signal from reliably synchronizing components.

In order to solve the problem associated with large swings in current on a power I/O pad, it is proposed to connect the power I/O pad to one or more capacitors. However, simply adding capacitors to the memory die may cause the memory die to increase in size, which is not desired since there is a demand for smaller memory die for smaller electronic devices. Thus, it is proposed to convert unused portions of the memory die to usable pool capacitors for the power I/O pad. This technology can also be used to provide capacitors for other I/O pads or other types of I/O interfaces. Additionally, the proposed technology can be used on semiconductors dies other than memory dies.

For example it is proposed to add capacitors to the memory die by positioning these capacitors in one or more metal interconnect layers (that are otherwise not being used) below a signal line and/or above a device capacitor.

One embodiment includes a die (e.g., a memory die) having an electrical circuit, a plurality of metal interconnect layers connected to the electrical circuit, a signal line connected to the electrical circuit, a plurality of I/O connections in communication with the electrical circuit, and one or more capacitors positioned in one or more of the metal interconnect layers below the signal line. Some implementations of the die include device capacitors formed on the top surface of the substrate such that the one or more capacitors are positioned above the device capacitors formed on the top surface of the substrate.

FIG. 1is a functional block diagram of one embodiment of a memory die300that implements the technology proposed herein for using a portion of memory die as pool capacitors for the I/O interface. The components depicted inFIG. 1are electrical circuits. In one embodiment, each memory die300includes a memory structure326, control circuitry310, and read/write circuits328. Memory structure326is addressable by word lines via a row decoder324and by bit lines via a column decoder332. The read/write circuits328include multiple sense blocks350including SB1, SB2, SBp (sensing circuitry) and allow a page (or multiple pages) of data in multiple memory cells to be read or programmed (written) in parallel. In one embodiment, each sense block include a sense amplifier and a set of latches connected to the bit line. The latches store data to be written and/or data that has been read. The sense amplifiers include bit line drivers.

Memory dies300includes I/O interface321, which is connected to control circuitry310, column decoder332, read/write circuits328and memory structure326. Commands and data are transferred between the controller and the memory die300via lines319that connect to I/O interface321. In one embodiment, I/O interface321includes a set of I/O pads.

I/O interface321can be a synchronous interface or an asynchronous interface. Examples of an I/O interface include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used. Toggle mode (e.g., Toggle Mode 2.0 JEDEC Standard or Toggle Mode 800) is an asynchronous memory interface that supports SDR and DDR with a DQS signal acting as a data strobe signal. Table 1 provides a definition of one example of a Toggle Mode Interface that can be used to implement I/O interface321. For each of the signals listed in the table below, I/O Interface has a corresponding I/O pad.

TABLE 1Signal NameTypeFunctionALEInputAddress Latch Enable controls the activatingpath for addresses to the internal addressregisters. Addresses are latched on the risingedge of WEn with ALE high.CEnChip Enable controls memory die selection.CLEInputCommand Latch Enable controls theactivating path for commands sent to thecommand register.When active high,commands are latched into the commandregister through the I/O ports on the risingedge of the WEn signal.REInputRead Enable ComplementREnInputRead Enable controls serial data out, andwhen active, drives the data onto the I/O bus.WEnInputWrite Enable controls writes to the I/O port.Commands and addresses are latched on therising edge of the WEn pulse.WPnInputWrite Protect provides inadvertent program/erase protection during power transitions.The internal high voltage generator is resetwhen the WPn pin is active low.DQSInput/OutputData Strobe acts as an output when readingdata, and as an input when writing data. DQSis edge-aligned with data read; it is center-aligned with data written.DQSnInput/OutputData Strobe complement (used for DDR)Bus[0:7]Input/OutputData Input/Output (I/O) bus inputscommands, addresses, and data, and outputsdata during Read operations. The I/O pinsfloat to High-z when the chip is deselectedor when outputs are disabled.R/BnOutputReady/Busy indicates device operation status.R/Bn is an open-drain output and does notfloat to High-z when the chip is deselected orwhen outputs are disabled. When low, itindicates that a program, erase, or randomread operation is in process; it goes highupon completion.ZQSupplyReference for ZQ calibration.VCCSupplyPower supply for memory die.VCCQSupplyI/O power for I/O signalsVPPSupplyOptional, high voltage, external power supplyVREFSupplyReference voltage, reserved fir ToggleMode DDR2VSSSupplyGround

As described above, due to active switching of the inputs and outputs of I/O Interface321, there can be large swings in current on VCCQ. This change in the current on the VCCQ can lead to distortion of other signals such as DQS. The signal DQS is supposed to have a 50% duty cycle, but due to large swings in current on VCCQ, the duty cycle may be different than 50%, which can cause a signaling problem that prevents proper communication between the memory die and controller. In order to solve this problem, it is proposed to connect the power I/O pad (e.g. the I/O pad for VCCQ or VCC) to one or more pool capacitors. However, simply adding capacitors to the memory die may cause the memory die to increase in size, which is not desired since there is a demand for smaller memory die for smaller electronic devices. Thus, it is proposed to convert unused portions of the memory die to usable pool capacitors for the power I/O pad.

Looking back atFIG. 1, control circuitry310cooperates with the read/write circuits328to perform memory operations (e.g., write, read, erase, and others) on memory structure326. In one embodiment, control circuitry310includes a state machine312, an on-chip address decoder314, a power control circuit316and a temperature sensor circuit318. State machine312provides die-level control of memory operations. In one embodiment, state machine312is programmable by software. In other embodiments, state machine312does not use software and is completely implemented in hardware (e.g., electrical circuits). In some embodiments, state machine312can be replaced by a microcontroller or microprocessor. In one embodiment, control circuitry310includes buffers such as registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters. Temperature sensor circuit318detects current temperature at memory die300.

The on-chip address decoder314provides an address interface between addresses used by controller120to the hardware address used by the decoders324and332. Power control module316controls the power and voltages supplied to the word lines and bit lines during memory operations. Power control module316may include charge pumps for creating voltages.

For purposes of this document, control circuitry310, read/write circuits328and decoders324/332comprise one embodiment of a control circuit for memory structure326. In other embodiments, other circuits that support and operate on memory structure326can be referred to as a control circuit. For example, in some embodiments, the controller can operate as the control circuit or can be part of the control circuit.

In one embodiment, memory structure326comprises a three dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells of memory structure326comprise vertical NAND strings with charge-trapping material such as described, for example, in U.S. Pat. No. 9,721,662, incorporated herein by reference in its entirety. A NAND string includes memory cells connected by a channel.

In another embodiment, memory structure326comprises a two dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates such as described, for example, in U.S. Pat. No. 9,082,502, incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included in memory structure326is not limited to the examples above. Many different types of memory array architectures or memory cell technologies can be used to form memory structure326. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure326include ReRAM memories, magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable technologies for architectures of memory structure326include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.

Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. Note that the use of “pulse” in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave.

FIG. 2is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array that can comprise memory structure326, which includes a plurality non-volatile memory cells. For example,FIG. 2shows a portion of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers with vertical columns of materials extending through the dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-300 alternating dielectric layers and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers and 110 dielectric layers. More or less than 108-300 layers can also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four “fingers” or sub-blocks by local interconnects LI.FIG. 2shows two fingers and two local interconnects LI. Below the alternating dielectric layers and word line layers is a source line layer SL. Vertical columns of materials (also known as memory holes) are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the vertical columns/memory holes is marked as MH. Note that inFIG. 2, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the vertical column/memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory array that comprises memory structure126is provided below with respect toFIG. 3A-3F.

FIG. 3Ais a block diagram explaining one example organization of memory structure326, which is divided into two planes302and304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In on embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure326to enable the signaling and selection circuits. In one embodiment, a block represents a groups of connected memory cells as the memory cells of a block share a common set of unbroken word lines and unbroken bit lines. In the structure ofFIG. 3A, Block0and Block M-1of both planes302and304are at the edge of the memory structure (or otherwise referred to as being located in an edge region/section of the memory structure).

FIGS. 3B-3Fdepict an example three dimensional (“3D”) NAND structure that corresponds to the structure ofFIG. 2and can be used to implement memory structure326ofFIG. 1.FIG. 3Bis a block diagram depicting a top view of a portion of one block from memory structure326. The portion of the block depicted inFIG. 3Bcorresponds to portion306in block2ofFIG. 3A. As can be seen fromFIG. 3B, the block depicted inFIG. 3Bextends in the direction of332. In one embodiment, the memory array has many layers; however,FIG. 3Bonly shows the top layer.

FIG. 3Bdepicts a plurality of circles that represent the vertical columns. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example,FIG. 3Bdepicts vertical columns422,432,442and452. Vertical column422implements NAND string482. Vertical column432implements NAND string484. Vertical column442implements NAND string486. Vertical column452implements NAND string488. More details of the vertical columns are provided below. Since the block depicted inFIG. 3Bextends in the direction of arrow330and in the direction of arrow332, the block includes more vertical columns than depicted inFIG. 3B

FIG. 3Balso depicts a set of bit lines415, including bit lines411,412,413,414, . . .419.FIG. 3Bshows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. For example, bit line414is connected to vertical columns422,432,442and452. In some embodiments, bit lines are positioned over the memory structure325and run along the entire length of the plane (e.g., from the top of plane302to the bottom of plane302).

The block depicted inFIG. 3Bincludes a set of local interconnects402,404,406,408and410that connect the various layers to a source line below the vertical columns. Local interconnects402,404,406,408and410also serve to divide each layer of the block into four regions; for example, the top layer depicted inFIG. 3Bis divided into regions420,430,440and450, which are referred to as fingers or sub-blocks. In the layers of the block that implement memory cells, the four regions are referred to as word line fingers that are separated by the local interconnects. In one embodiment, the word line fingers on a common level of a block connect together to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line only connects to one vertical column in each of regions420,430,440and450. In that implementation, each block has sixteen rows of active columns and each bit line connects to four rows in each block. In one embodiment, all of four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together); therefore, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

AlthoughFIG. 3Bshows each region having four rows of vertical columns, four regions and sixteen rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block.

FIG. 3Balso shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

FIG. 3Cdepicts a portion of one embodiment of a three dimensional memory structure326showing a cross-sectional view along line AA ofFIG. 3B. This cross sectional view cuts through vertical columns432and434and region430(seeFIG. 3B). The structure ofFIG. 3Cincludes four drain side select layers SGD0, SGD1, SGD2and SGD3; four source side select layers SGS0, SGS1, SGS2and SGS3; six dummy word line layers DD0, DD1, DS0, DS1, WLDL, WLDU; and ninety six data word line layers WLL0-WLL95for connecting to data memory cells. Other embodiments can implement more or less than four drain side select layers, more or less than four source side select layers, more or less than six dummy word line layers, and more or less than ninety six word lines. Vertical columns432and434are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each vertical column comprises a vertical NAND string. For example, vertical column432comprises NAND string484. Below the vertical columns and the layers listed below is substrate101, an insulating film454on the substrate, and source line SL. The NAND string of vertical column432has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement withFIG. 3B,FIG. 3Cshow vertical column432connected to Bit Line414via connector415. Local interconnects404and406are also depicted.

For ease of reference, drain side select layers SGD0, SGD1, SGD2and SGD3; source side select layers SGS0, SGS1, SGS2and SGS3; dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU; and word line layers WLL0-WLL95collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL0-DL111. For example, dielectric layers DL104is above word line layer WLL94and below word line layer WLL95. In one embodiment, the dielectric layers are made from SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WLL0-WLL95connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. A dummy word line is connected to dummy memory cells. Drain side select layers SGD0, SGD1, SGD2and SGD3are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, SGS2and SGS3are used to electrically connect and disconnect NAND strings from the source line SL.

FIG. 3Calso shows a Joint area. In one embodiment it is expensive and/or challenging to etch ninety six word line layers intermixed with dielectric layers. To ease this burden, one embodiment includes laying down a first stack of forty eight word line layers alternating with dielectric layers, laying down the Joint area, and laying down a second stack of forty eight word line layers alternating with dielectric layers. The Joint area is positioned between the first stack and the second stack. The Joint area is used to connect to the first stack to the second stack. InFIG. 3C, the first stack is labeled as the “Lower Set of Word Lines” and the second stack is labeled as the “Upper Set of Word Lines.” In one embodiment, the Joint area is made from the same materials as the word line layers. In one example set of implementations, the plurality of word lines (control lines) comprises a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a joint area between the first stack and the second stack, as depicted inFIG. 3C.

FIG. 3Ddepicts a logical representation of the conductive layers (SGD0, SGD1, SGD2, SGD3, SGS0, SGS1, SGS2, SGS3, DD0, DD1, DS0, DS1, and WLL0-WLL95) for the block that is partially depicted inFIG. 3C. As mentioned above with respect toFIG. 3B, in one embodiment local interconnects402,404,406,408and410break up the conductive layers into four regions/fingers (or sub-blocks). For example, word line layer WLL94is divided into regions460,462,464and466. For word line layers (WLL0-WLL127), the regions are referred to as word line fingers; for example, word line layer WLL126is divided into word line fingers460,462,464and466. For example, region460is one word line finger on one word line layer. In one embodiment, the four word line fingers on a same level are connected together. In another embodiment, each word line finger operates as a separate word line.

Drain side select gate layer SGD0(the top layer) is also divided into regions420,430,440and450, also known as fingers or select line fingers. In one embodiment, the four select line fingers on a same level are connected together. In another embodiment, each select line finger operates as a separate word line.

FIG. 3Edepicts a cross sectional view of region429ofFIG. 3Cthat includes a portion of vertical column432(a memory hole) that extends through the alternating conductive layers and dielectric layers. In one embodiment, the vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, vertical column432includes an inner core layer470that is made of a dielectric, such as SiO2. Other materials can also be used. Surrounding inner core470is polysilicon channel471. Materials other than polysilicon can also be used. Note that it is the channel471that connects to the bit line and the source line. Surrounding channel471is a tunneling dielectric472. In one embodiment, tunneling dielectric472has an ONO structure. Surrounding tunneling dielectric472is charge trapping layer473, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

FIG. 3Edepicts dielectric layers DLL105, DLL104, DLL103, DLL102and DLL101, as well as word line layers WLL95, WLL94, WLL93, WLL92, and WLL91. Each of the word line layers includes a word line region476surrounded by an aluminum oxide layer477, which is surrounded by a blocking oxide (SiO2) layer478. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel471, tunneling dielectric472, charge trapping layer473, blocking oxide layer478, aluminum oxide layer477and word line region476. For example, word line layer WLL95and a portion of vertical column432comprise a memory cell MC1. Word line layer WLL94and a portion of vertical column432comprise a memory cell MC2. Word line layer WLL93and a portion of vertical column432comprise a memory cell MC3. Word line layer WLL92and a portion of vertical column432comprise a memory cell MC4. Word line layer WLL91and a portion of vertical column432comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer473which is associated with the memory cell. These electrons are drawn into the charge trapping layer473from the channel471, through the tunneling dielectric472, in response to an appropriate voltage on word line region476. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).

FIG. 3Fis a schematic diagram of a portion of the memory depicted in inFIGS. 2-3E.FIG. 3Fshows physical word lines WLL0-WLL95running across the entire block. The structure ofFIG. 3Fcorresponds to portion306in Block2ofFIGS. 3A-E, including bit lines411,412,413,414, . . .419. Within the block, each bit line is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2and SGD3are used to determine which of the four NAND strings connect to the associated bit line(s). Source side selection lines SGS0, SGS1, SGS2and SGS3are used to determine which of the four NAND strings connect to the common source line. The block can also be thought of as divided into four sub-blocks SB0, SB1, SB2and SB3. Sub-block SB0corresponds to those vertical NAND strings controlled by SGD0and SGS0, sub-block SB1corresponds to those vertical NAND strings controlled by SGD1and SGS1, sub-block SB2corresponds to those vertical NAND strings controlled by SGD2and SGS2, and sub-block SB3corresponds to those vertical NAND strings controlled by SGD3and SGS3.

As described above, it is proposed to convert unused portions of the memory die to usable capacitors for the power I/O pad.FIG. 4is a block diagram of a memory die502that has converted unused portions of the memory die to usable capacitors for the power I/O pad. Memory die502may be the same structure as memory die300ofFIG. 1. Memory die502includes a three dimensional memory structure that includes two planes: Plane0(504) and Plane1(506). Plane0(504) may be the same structure as plane302ofFIG. 3A. Plane1(506) may be the same structure as plane304ofFIG. 3A. In other embodiments, more or less than two planes can be used. Plane0(504) and Plane1(506) may implement memory structure326, including any of the embodiments mentioned above.

Memory die502also includes peripheral circuit508, which can be located to the side of the memory structure (Plane0and Plane1) and/or underneath the memory structure (Plane0and Plane1). Peripheral circuit508is an electrical circuit that can include control circuitry310, read/write circuits328and/or decoders324/332. Peripheral circuit508can include any other circuit on the memory die that is used to control/operate the memory die.

As mentioned above, it is proposed to convert unused portions of the memory die to one or more usable capacitors for the power I/O pad (or other I/O pad or other type of I/O interface). In one embodiment, portions of the memory die underneath the signal lines are configured to operate as one or more capacitors.

FIG. 5depicts various layers of one embodiment of a memory die300/502.FIG. 5shows an active area AA which corresponds to the semiconductor substrate. Electrical components EC (e.g., arranged in electrical circuits) can be implemented on the top surface of active area. In one embodiment, the memory die includes at least four metal interconnect layers above the substrate (AA) and above the electrical components EC. These four metal interconnect layers are labeled inFIG. 5as MX, M0, M1, and M2. Connecting metal layers MX and M0is via V0. Connecting metal interconnect layers M1and M0is via V1. Connecting metal interconnect layers M1and M2is via V2. Metal interconnect layer MX is connected to active area AA (substrate) by connecting hole CS606(e.g. which is similar to a via). Each of the metal interconnect layers can initially be added to the device as a sheet and then patterned using standard processes known in the art.FIG. 5Ashows a signal line602in metal interconnect layer M2that is receiving a signal from an electrical component EC on active area AA by way of the electrical path CS/MX/V0/M0/V1/M1/V2and routing that signal to another location on metal interconnect layer M2.

FIG. 5also shows signal line600in metal interconnect layer M2next to signal line602. In this embodiment, there are no components implemented underneath signal600. Thus, the space below signal600and above the active area AA of the substrate is unused and available to house one or more capacitors.

FIGS. 6A-Care cross sectional views that depict various layers of memory die300/502representing three embodiments of memory die300/502in which portions of the memory die underneath the signal lines are configured to operate as one or more capacitors. LikeFIG. 5,FIG. 6Ashows signal line622on metal interconnect layer M2connected to metal interconnect layer M1by via V2. Metal interconnect layer M1is connected to metal interconnect layer M0by via V1. Metal interconnect layer M0is connected to metal interconnect layer MX by via V0. Metal interconnect layer MX is connected to active area AA by connecting hole CS626. In some embodiments, metal interconnect layers MX, M0, M1and M2(in general) are connected to peripheral circuit508, and the memory structure (e.g., Plane0504and Plane1506).

FIG. 6Aalso shows electrical components EC implemented on the top surface of active area AA (substrate). The electrical components EC can be an electrical circuit, transistors, capacitors, etc. The capacitors that are part of the electrical components EC can be standard capacitors known in the art, formed from transistors or can be ONO capacitors. Signal line622in metal interconnect layer M2is receiving a signal from (or providing a signal to) electrical components EC on active area AA by way of the electrical path CS/MX/V0/M0/V1/M1/V2and routing that signal to/from another location on metal interconnect layer M2.

FIG. 6Aalso shows signal line620implemented in metal interconnect layer M2. Signal line620can be any type of metal signal line including a single data signal, a data bus, a control signal, a power signal, a ground signal, a clock signal, or other type of signal. Signal line620connects to various portions of the peripheral circuit508and the memory structure (e.g., Plane0504and Plane1506). Positioned directly below signal line620is one or more metal components628in metal interconnect layer M0that form one or more capacitors. In one example embodiment, the capacitor includes two metal components in a single metal interconnect layer.FIG. 6Ashows the one or more capacitors implemented in metal interconnect layer M0; however, the one or more capacitors can also implemented in other metal interconnect layers, such as MX or M1. In one example implementation, the capacitor is not implemented in metal interconnect layer M1so that there is separation between the capacitor and signal line620. More details of one or more metal components628are provided below.

In one embodiment, the capacitor in metal interconnect layer M0(of a different layer) is positioned directly below the signal line620. In other embodiments, the capacitor in metal interconnect layer M0(of a different layer) is positioned directly below an area adjacent to signal line620. In another embodiment, the capacitor in metal interconnect layer M0(of a different layer) is positioned in any unused portion of the memory die outside of the memory array.

In one embodiment, memory structure326(e.g., Plane0504and Plane1506) is positioned below metal interconnect layers M2, M1, M0and MX; and above electrical components EC and active area AA (substrate).

FIG. 6Bdepicts another embodiment for implementing one or more capacitors in unused areas underneath signal lines. The embodiment ofFIG. 6Bimplements one or more capacitors in two metal interconnect layers.FIG. 6Bshows signal line622in metal interconnect layer M2is receiving a signal from (or providing a signal to) electrical components EC on active area AA by way of the electrical path CS/MX/V0/M0/V1/M1/V2and routing that signal to/from another location on metal interconnect layer M2.FIG. 6Balso shows signal line630implemented in metal interconnect layer M2. Positioned directly below signal line630is one or more metal components632in metal interconnect layer M0and one or more metal components634in metal interconnect layer MX that form one or more capacitors.FIG. 6Bshows the one or more capacitors implemented in metal interconnect layers M0and MX; however, the capacitors can implemented in any two adjacent (or nearby) metal interconnect layers. In one example, one or more metal components632form one or more capacitors in metal interconnect layer M0and one or more metal components634form one or more capacitors in metal interconnect layer MX. In another example, one or more metal components632and one or more metal components634form a capacitor that includes a first metal component in a first metal interconnect layer (e.g., M0) directly below signal line630and a second metal component in a second metal interconnect layer (e.g., MX) directly below signal line630. More details of one or more metal components632and one or more metal components634are provided below.

FIG. 6Cdepicts another embodiment for implementing one or more capacitors in unused areas underneath signal lines. The embodiment ofFIG. 6Cimplements one or more capacitors in three metal interconnect layers.FIG. 6Calso shows signal line622in metal interconnect layer M2is receiving a signal from (or providing a signal to) electrical components EC on active area AA by way of the electrical path CS/MX/V0/M0/V1/M1/V2and routing that signal to/from another location on metal interconnect layer M2.FIG. 6Calso shows signal line640implemented in metal interconnect layer M2. Positioned directly below signal line640is one or more metal components642in metal interconnect layer M1, one or more metal components644in metal interconnect layer M0, and one or more metal components646in metal interconnect layer MX that form one or more capacitors. Although one or more metal components642/644/646are depicted as being directly below signal line640, one or more metal components642/644/646can also be offset from signal line640and/or longer and/or wider than signal line640. In one example, one or more metal components642form one or more capacitors in metal interconnect layer M1, one or more metal components644form one or more capacitors in metal interconnect layer M0and one or more metal components646form one or more capacitors in metal interconnect layer MX. In another example, one or more metal components642/644/646includes a first metal component in a first metal interconnect layer and a second metal component in a second metal interconnect layer below signal line640. More details of one or more metal components642, one or more metal components644and one or more metal components646are provided below.

FIGS. 5, 6A, 6B and 6Cdescribe a set of embodiments that include an electrical circuit (e.g., peripheral circuit508), a plurality of metal interconnect layers connected to the electrical circuit (e.g., M1, M0and MX), a signal line connected to the electrical circuit (e.g., signal lines620,630,640), a plurality of I/O connections (e.g., the I/O pads of I/O Interface510) in communication with the electrical circuit, and one or more capacitors connected to a power I/O connection (e.g., power I/O pad) of the plurality of I/O connections, where the one or more capacitors are positioned in one or more of the metal interconnect layers and below the signal line.

In addition to the one or more capacitors of MX/M0/M1being below a signal line, the one or more capacitors of MX/M0/M1are positioned directly above one or more electrical components EC on the surface of the substrate (AA). For example, the one or more capacitors of MX/M0/M1are positioned directly above one or more device capacitors (which are examples of electrical components EC on the surface of the substrate). A device capacitor refers to a capacitor implemented on the surface of the substrate. The device capacitor can be a standard capacitor known in the art, a capacitor formed from one or more transistors or can be an ONO capacitor. In one embodiment, the electrical components EC on the surface of the substrate AA include a metal plate that forms a capacitor with one or more components of metal layer MX.

FIG. 7Ais a top view of a metal interconnect layer patterned into two metal components that form a capacitor. The structure ofFIG. 7Acan be used to implement any of the metals interconnect layers (e.g., M1, M0and MX) below a signal line or above a device capacitor. For example, the structure ofFIG. 7Acan be used to implement the one or more components628in metal interconnect layer M0ofFIG. 6A, the one or more components632in metal interconnect layer M0ofFIG. 6B, the one or more components634in metal interconnect layer MX ofFIG. 6B, the one or more components642in metal interconnect layer M1ofFIG. 6C, the one or more components644in metal interconnect layer M0ofFIG. 6C, and the one or more components646in metal interconnect layer MX ofFIG. 6C.

In one embodiment, the metal interconnect layer is patterned into a set of interleaved combs having interdigitated fingers. For example,FIG. 7Ashows a two interleaved metal combs702and704. Comb702includes finger702a, finger702band finger702c. Comb704includes finger704a, finger704band finger704c. Fingers702a,702b,702care interleaved with fingers704a,704b,704cto create interdigitated fingers. In one embodiment, combs702and704are metal (and can be referred to as metal members or metal components). Comb702(with its interdigitated fingers702a,702v,702c) is connected to VSS pad712(ground). Comb704(with its interdigitated fingers704a,704b,704c) is connected to VCCQ pad714(power). Comb702and comb704form a capacitor that includes two metal components (combs702and704) in a single metal interconnect layer that are shaped as interleaved combs and have interdigitated fingers.

FIGS. 8A-Cprovides more details of examples of the one or more components implementing the metal interconnect layers for the embodiment ofFIG. 6B. That is,FIGS. 8A-Cshow examples of the one or more components632of metal interconnect layer M0and the one or more components634of metal interconnect layer MX.

FIG. 8Ais a top view of two metal interconnect layers M0and MX pertaining to an embodiment where a capacitor includes a first metal component in a first metal interconnect layer below a signal lines and a second metal component in a second metal interconnect layer below the signal line. AlthoughFIG. 8Ashows the two metal interconnect layers being MX and M0, other metal interconnect layers can also be implemented. The embodiment ofFIG. 8Aincludes a metal plate802in metal interconnect layer M0and a metal plate804in interconnect layer MX. Metal plate802is connected to VSS pad806. Metal plate804is connected to VCCQ pad808. VSS pad806and VCCQ pad808are part of one embodiment of I/O interface510. Metal plate802and metal plate804form a capacitor that is connected to VCCQ.

FIG. 8Bis a top view of two metal interconnect layers M0and MX pertaining to an embodiment where a capacitor includes a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal. AlthoughFIG. 8Bshows the two metal interconnect layers being MX and M0, other metal interconnect layers can also be implemented. The embodiment ofFIG. 8Bincludes a metal mesh812in metal interconnect layer M0and a metal mesh814in interconnect layer MX. Metal mesh812is connected to VSS pad816. Metal mesh814is connected to VCCQ pad818. VSS pad816and VCCQ pad818are part of one embodiment of I/O interface510. Metal mesh812and metal mesh814form a capacitor that is connected to VCCQ.

FIG. 8Cis a top view of two metal interconnect layers M0and MX pertaining to an embodiment where a capacitor includes a first metal component in a first metal interconnect layer below a signal line (and/or above a device capacitor) and a second metal component in a second metal interconnect layer below the signal line (and/or above a device capacitor). The embodiment ofFIG. 8Calso includes capacitors having two metal components in a single metal interconnect layer. Metal interconnect layer M0includes two metal interleaved combs850and852having interdigitated fingers. Metal comb850is connected to VSS pad860. Metal comb852is connected to VCCQ pad862. VSS pad860and VCCQ pad862are part of one embodiment of I/O interface510. Metal interconnect layer MX includes two metal interleaved combs854and856having interdigitated fingers. Metal comb854is connected to VSS pad860. Metal comb856is connected to VCCQ pad862. There are four capacitors formed by the structure ofFIG. 8C: (1) a first capacitor comprising metal comb850and metal comb852, (2) a second capacitor comprising metal comb854and metal comb856, (3) a third capacitor comprising metal comb850and metal comb856, and (4) a fourth capacitor comprising metal comb852and metal comb854. AlthoughFIG. 8Bshows the two metal interconnect layers being MX and M0, other metal interconnect layers can also be implemented. Metal combs850,852,854and856are the same structure as metal combs702and704ofFIG. 7A. The first capacitor (850/852) and the second capacitor (854/856) each include two metal components in a single metal interconnect layer. The third capacitor (850/856) and the fourth capacitor (852/854) each include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line.

FIGS. 9A-Hprovides more details of examples of the one or more components implementing the metal interconnect layers for the embodiment ofFIG. 6C. That is,FIGS. 9A-Hshow examples of the one or more components642of metal interconnect layer M1, one or more components644of metal interconnect layer M0, and the one or more components646of metal interconnect layer MX.

FIG. 9Ais a top view of three metal interconnect layers M1, M0and MX for an embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line (and above a device capacitor). The embodiment ofFIG. 9Aalso includes capacitors having two metal components in a single metal interconnect layer.

Metal interconnect layer M1includes two metal interleaved combs902and904having interdigitated fingers. Metal comb902is connected to VSS pad908. Metal comb904is connected to VCCQ pad906. VSS pad906and VCCQ pad908are part of one embodiment of I/O interface510. Metal interconnect layer M0includes two metal interleaved combs914and916having interdigitated fingers. Metal comb914is connected to VSS pad908. Metal comb916is connected to VCCQ pad906. Metal interconnect layer MX includes two metal interleaved combs920and922having interdigitated fingers. Metal comb920is connected to VSS pad908. Metal comb922is connected to VCCQ pad906. Metal combs902,904,914,916,920and922are the same structure as metal combs702and704ofFIG. 7A. Metal combs902and920are in a first orientation, while metal combs904and922are in a second orientation that is opposite in direction than the first orientation. Metal comb914is in a third orientation that is −90 degrees rotated from the first orientation. Metal comb916is in a fourth orientation that is +90 degrees rotated from the first orientation.

There are seven capacitors formed by the structure ofFIG. 9A: (1) a first capacitor comprising metal comb902and metal comb904, (2) a second capacitor comprising metal comb914and metal comb916, (3) a third capacitor comprising metal comb920and metal comb922, (4) a fourth capacitor comprising metal comb902and metal comb916, (5) a fifth capacitor comprising metal comb904and metal comb914, (6) a sixth capacitor comprising metal comb914and metal comb922, and (7) a seventh capacitor comprising metal comb916and metal comb920.

FIG. 9Bis a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal lines and a second metal component in a second metal interconnect layer below the signal line (and above a device capacitor). The embodiment ofFIG. 9Balso includes capacitors having two metal components in a single metal interconnect layer. The structure ofFIG. 9Bhas different connections to VSS and VCCQ and different orientations of the combs, as compared toFIG. 9A.

Metal interconnect layer M1includes two metal interleaved combs930and932having interdigitated fingers. Metal comb930is connected to VSS pad934. Metal comb932is connected to VCCQ pad936. VSS pad934and VCCQ pad936are part of one embodiment of I/O interface510. Metal interconnect layer M0includes two metal interleaved combs942and944having interdigitated fingers. Metal comb942is connected to VSS pad934. Metal comb944is connected to VCCQ pad936. Metal interconnect layer MX includes two metal interleaved combs950and952having interdigitated fingers. Metal comb950is connected to VSS pad934. Metal comb952is connected to VCCQ pad936. Metal combs930,932,942,944,950and952are the same structure as metal combs702and704ofFIG. 7A. Metal combs930,942, and950are in one orientation. Metal combs932,944, and952are an opposite orientation to metal combs930,942, and950.

There are seven capacitors formed by the structure ofFIG. 9A: (1) a first capacitor comprising metal comb930and metal comb932, (2) a second capacitor comprising metal comb942and metal comb944, (3) a third capacitor comprising metal comb950and metal comb952, (4) a fourth capacitor comprising metal comb930and metal comb944, (5) a fifth capacitor comprising metal comb932and metal comb942, (6) a sixth capacitor comprising metal comb942and metal comb952, and (7) a seventh capacitor comprising metal comb944and metal comb950.

FIG. 9Cis a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line. The embodiment ofFIG. 9Calso includes capacitors having two metal components in a single metal interconnect layer. The structure ofFIG. 9Chas different connections to VSS and VCCQ than the structure ofFIG. 9B.

Metal interconnect layer M1includes two metal interleaved combs960and962having interdigitated fingers. Metal comb960is connected to VSS pad964. Metal comb932is connected to VCCQ pad966. VSS pad964and VCCQ pad966are part of one embodiment of I/O interface510. Metal interconnect layer M0includes two metal interleaved combs970and972having interdigitated fingers. Metal comb972is connected to VSS pad964. Metal comb970is connected to VCCQ pad966. Metal interconnect layer MX includes two metal interleaved combs980and982having interdigitated fingers. Metal comb980is connected to VSS pad964. Metal comb982is connected to VCCQ pad966. Metal combs960,962,970,972,980and982are the same structure as metal combs702and704ofFIG. 7A. Metal combs960,970, and980are in one orientation. Metal combs962,972, and982are an opposite orientation to metal combs960,970, and980.

There are seven capacitors formed by the structure ofFIG. 9A: (1) a first capacitor comprising metal comb960and metal comb962, (2) a second capacitor comprising metal comb970and metal comb972, (3) a third capacitor comprising metal comb980and metal comb982, (4) a fourth capacitor comprising metal comb960and metal comb970, (5) a fifth capacitor comprising metal comb962and metal comb972, (6) a sixth capacitor comprising metal comb970and metal comb980, and (7) a seventh capacitor comprising metal comb972and metal comb982.

FIG. 9Dis a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line. Metal interconnect layer M1includes metal mesh1002connected to VCCQ pad1010. Metal interconnect layer M0includes metal mesh1004connected to VSS pad1012. Metal interconnect layer MX includes metal mesh1006connected to VCCQ pad1010. There are two capacitors formed by the structure ofFIG. 9D: (1) a first capacitor comprising metal mesh1002and metal mesh1004and (2) a second capacitor comprising metal mesh1004and metal mesh1006. VSS pad1012and VCCQ pad1010are part of one embodiment of I/O interface510.

FIG. 9Eis a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line. Metal interconnect layer M1includes metal mesh1020connected to VSS pad1030. Metal interconnect layer M0includes metal mesh1022connected to VCCQ pad1032. Metal interconnect layer MX includes metal mesh1024connected to VSS pad1030. There are two capacitors formed by the structure ofFIG. 9E: (1) a first capacitor comprising metal mesh1020and metal mesh1022and (2) a second capacitor comprising metal mesh1022and metal mesh1024. VSS pad1030and VCCQ pad1032are part of one embodiment of I/O interface510.

FIG. 9Fis a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line. Metal interconnect layer M1includes metal plate1050connected to VCCQ pad1056. Metal interconnect layer M0includes metal plate1052connected to VSS pad1052. Metal interconnect layer MX includes metal plate1054connected to VCCQ pad1056. There are two capacitors formed by the structure ofFIG. 9F: (1) a first capacitor comprising metal plate1050and metal plate1052and (2) a second capacitor comprising metal plate1052and metal plate1054. VSS pad1058and VCCQ pad1056are part of one embodiment of I/O interface510.

FIG. 9Gis a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line. Metal interconnect layer M1includes metal plate1070connected to VSS pad1076. Metal interconnect layer M0includes metal plate1072connected to VCCQ pad1078. Metal interconnect layer MX includes metal plate1074connected to VSS pad1080. There are two capacitors formed by the structure ofFIG. 9G: (1) a first capacitor comprising metal plate1070and metal plate1072and (2) a second capacitor comprising metal plate1072and metal plate1074. VSS pad1076and VCCQ pad1078are part of one embodiment of I/O interface510.

FIG. 9His a top view of three metal interconnect layers M1, M0and MX for another embodiment where capacitors include a first metal component in a first metal interconnect layer below a signal line and a second metal component in a second metal interconnect layer below the signal line. The embodiment ofFIG. 9Halso includes capacitors having two metal components in a single metal interconnect layer. Metal interconnect layer M1includes metal plate1086connected to VSS pad1092. Metal interconnect layer M0includes metal mesh1088connected to VCCQ pad1094. Metal interconnect layer MX includes two metal interleaved metal combs1096and1098having interdigitated fingers. Metal comb1098is connected to VSS pad1092. Metal comb1098is connected to VCCQ pad1094. VSS pad1092and VCCQ pad1094are part of one embodiment of I/O interface510. There are three capacitors formed by the structure ofFIG. 9H: (1) a first capacitor comprising metal plate1086and metal mesh1088, (2) a second capacitor comprising metal mesh1088and metal comb1096, and (3) a third capacitor comprising metal comb1096and metal comb1094.

FIG. 10is a top view of three metal layers, showing the various capacitors implemented for the embodiment ofFIG. 9A. There are seven capacitors formed by the structure depicted inFIGS. 9A and 10: (1) a first capacitor C1comprising metal comb902and metal comb904, (2) a second capacitor C2comprising metal comb914and metal comb916, (3) a third capacitor C3comprising metal comb920and metal comb922, (4) a fourth capacitor C4comprising metal comb902and metal comb916, (5) a fifth capacitor C5comprising metal comb904and metal comb914, (6) a sixth capacitor C6comprising metal comb914and metal comb922, and (7) a seventh capacitor comprising metal comb916and metal comb920. There can also be an eighth capacitor comprising metal comb920or metal comb922in combination with a metal component on active area AA of the substrate (e.g., such as part of the electrical components described above).

FIGS. 7A-9Hshow various embodiments of metal components in the metal interconnect layers forming capacitors that are connected to VSS and VCCQ. One skilled in the art would know how to connect the depicted metal components to VSS and VCCQ using metal interconnect, vias and other signal lines.FIG. 11is a cross sectional view of a portion of the memory die that shows one example of connecting the depicted metal components to VSS and VCCQ.FIG. 11depicts VCCQ pad1200, VSS pad1202and signal line1204, all three of which are implemented in metal interconnect layer M2and are part of one embodiment of I/O Interface510.FIG. 11also shows M1capacitor(s)1210, M0capacitor(s)1212, and M1capacitor(s)1214. M1capacitor(s)1210comprises one or more metal components on metal interconnect layer M1that comprise one or more capacitors as discussed above. M0capacitor(s)1212comprises one or more metal components on metal interconnect layer M0that comprise one or more capacitors as discussed above. MX capacitor(s)1214comprises one or more metal components on metal interconnect layer MX that comprise one or more capacitors as discussed above.

Metal interconnect layer M1includes metal interconnect1220that connects one or more metal components1210on metal interconnect layer M1to via1224, which connects to M2bus1225, which connects to VSS pad1202; thereby, connecting a capacitor that is partially or fully implemented on metal interconnect layer M1to VSS pad1202. Metal interconnect layer M1also includes metal interconnect1222that connects one or more metal components1210on metal interconnect layer M1to via1226, which connects to M2bus1227, which connects to VCCQ pad1200; thereby, connecting a capacitor that is partially or fully implemented on metal interconnect layer M1to VCCQ pad1200. M2bus1225and M2bus1227are metal signal lines on metal interconnect layer M2.

Metal interconnect layer M0includes metal interconnect1230that connects one or more metal components1212on metal interconnect layer M0to via1234, which connects to metal interconnect1220; thereby, connecting a capacitor that is partially or fully implemented on metal interconnect layer M0to VSS pad1202. Metal interconnect layer M0also includes metal interconnect1232that connects one or more metal components1212on metal interconnect layer M0to via1236, which connects to metal interconnect1222; thereby, connecting a capacitor that is partially or fully implemented on metal interconnect layer M0to VCCQ pad1200.

Metal interconnect layer MX includes metal interconnect1240that connects one or more metal components1214on metal interconnect layer MX to via1244, which connects to metal interconnect1230; thereby connecting a capacitor that is partially or fully implemented on metal interconnect layer MX to VSS pad1202. Metal interconnect layer MX also includes metal interconnect1242that connects one or more metal components1214on metal interconnect layer MX to via1246, which connects to metal interconnect1232; thereby, connecting a capacitor that is partially or fully implemented on metal interconnect layer MX to VCCQ pad1200.FIG. 11also depicts electrical components EC implemented on the active area AA of the substrate, below the various metal layers discussed above so that the capacitors are positioned below the signal line and above electrical components (e.g., device capacitors) located on the substrate.

FIG. 12is a cross sectional view of a portion of the memory die that shows another example of connecting the depicted metal components to VSS and VCCQ.FIG. 12depicts VCCQ pad1300, VSS pad1302and signal line1304, all three of which are implemented in metal interconnect layer M2and are part of one embodiment of I/O Interface510.FIG. 12also shows M1capacitor(s)1310, M0capacitor(s)1313, and M1capacitor(s)1314. M1capacitor(s)1310includes one or more metal components on metal interconnect layer M1that comprise a portion of one or more capacitors as discussed above. M0capacitor(s)1313includes one or more metal components on metal interconnect layer M0that comprise a portion of one or more capacitors as discussed above. MX capacitor(s)1314includes one or more metal components on metal interconnect layer MX that comprise a portion of one or more capacitors as discussed above.

Metal interconnect layer M1includes metal interconnect1320that connects one or more metal components1310on metal interconnect layer M1to via1324, which connects to M2bus1325, which connects to VSS pad1302; thereby, connecting a capacitor that is partially implemented on metal interconnect layer M1to VSS pad1302. Metal interconnect layer M0includes metal interconnect1332that connects one or more metal components1313on metal interconnect layer M0to via1336, which connects to metal interconnect1322, which connects to via1326, which connects to M2bus1327, which connects to VCCQ pad1300; thereby, connecting a capacitor that is partially implemented on metal interconnect layer M0to VCCQ pad1300. Metal interconnect layer MX includes metal interconnect1340that connects one or more metal components1314on metal interconnect layer MX to via1344, which connects to metal interconnect1330, which connects to via1334, which connects to metal interconnect1320; thereby connecting a capacitor that is partially implemented on metal interconnect layer MX to VSS pad1202.FIG. 12also depicts electrical components EC implemented on the active area AA of the substrate, below the various metal layers discussed above so that the capacitors are positioned below the signal line and above electrical components (e.g., device capacitors) located on the substrate. The technology described herein can include means for connecting capacitors to I/O pads in addition to those means depicted inFIGS. 11 and 12.

The above discussion teaches a means for converting unused portions of the memory die to usable capacitors for the power I/O pad. This technology can also be used to provide capacitors for other I/O pads or other types of I/O interfaces. Additionally, the proposed technology can be used on semiconductors dies other than memory dies. This technology improves signal timing issues in the circuit (including at the interface of the memory die), without adding to the size of the memory die or taking space away from other components on the memory die.

One embodiment includes an apparatus comprising an electrical circuit; a plurality of metal interconnect layers connected to the electrical circuit; a signal line connected to the electrical circuit; a plurality of I/O connections in communication with the electrical circuit, the I/O connections include a power I/O connection; and a first capacitor connected to the power I/O connection. The first capacitor is positioned in one or more of the metal interconnect layers. The first capacitor is positioned below the signal line.

One example implementations further comprises a three dimensional non-volatile memory array (e.g., seeFIGS. 2-3F) formed above the substrate and below the metal interconnect layers. The memory array is connected to the electrical circuit. The memory array is in communication with the I/O connections.

One embodiment includes an apparatus comprising a substrate; a plurality of metal interconnect layers above the substrate; a device capacitor positioned on a top surface of the substrate and below the plurality of metal interconnect layers; a three dimensional non-volatile memory array formed above the substrate and below the metal interconnect layers; an I/O pad; and multiple capacitors connected to the I/O pad. The capacitors are positioned in the metal interconnect layers. At least one of the multiple capacitors is positioned above the device capacitor.

One embodiment includes an apparatus comprising a substrate; a plurality of metal interconnect layers above the substrate; a three dimensional non-volatile memory array formed above the substrate and below the metal interconnect layers; a peripheral circuit connected to the memory array; a plurality of I/O pads positioned above the substrate and connected to the peripheral circuit (the I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads; and a plurality of metal components positioned in the metal interconnect layers above the substrate. Pairs of the metal components form capacitors. Each pair of metal components includes one metal component connected to the power I/O pad and one metal component connected to the ground I/O pad.

For purposes of this document, I/O can refer to input only, output only, or both input and output.