DOUBLE DATA RATE OUTPUT CIRCUIT WITH RECONFIGURABLE EQUALIZER

A reconfigurable driver in an I/O circuit has a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. A gate of the first transistor receives a data signal. The control signal is an inverted, delayed version of the data signal in a first mode. The control signal turns off the second transistor in a second mode. The control circuit generates the control signal using a version of the data signal when operated in a third mode. The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

TECHNICAL FIELD

The present disclosure generally relates to driver circuits in a memory interface and more particularly to a driver circuit that includes a configurable equalizer.

BACKGROUND

Electronic device technologies have seen explosive growth over the past several years. For example, growth of cellular and wireless communication technologies has been fueled by better communications, hardware, larger networks, and more reliable protocols. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever. Wireless devices may include a high-speed bus interface for communication of signals between hardware components. For example, the high-speed bus interface may be implemented using a Peripheral Component Interconnect Express (PCIe) bus, Universal Serial Bus (USB) or Serial Advanced Technology Attachment (SATA), among others.

In certain implementations, a high-speed serial bus interface may be configurable for different modes of communication. For example, integrated circuit (IC) devices that include memory interfaces have physical layer circuits may be expected to operate in one or more high-speed data communication modes and one or more low-speed data communication modes. Different signaling voltages may be defined for high-speed and low-speed data communication modes. Increased demands for higher data rates require increasingly tight timing between circuits within the memory interface in order to ensure integrity of the data and clock signals between memory controller and memory devices. Performance, accuracy and/or reliability of data communication interfaces may depend on the flexibility and reliability of driver circuits that are expected to accommodate changes in transmission speed, supply voltage variances and other factors that can impact the operation of high-speed data links. Therefore, there is an ongoing need for improvements that provide reliable transmission of clock, data and control signals over high-speed data links.

SUMMARY

Certain aspects of the disclosure relate to systems, apparatus, methods and circuits that can be used in high-speed interfaces to provide pre-equalization or enhanced line driving capability in certain modes of operation.

In various aspects of the disclosure, a reconfigurable driver in an input/output (I/O) circuit includes a first transistor provided in a first pullup structure, the first transistor having a gate configured to receive a data signal that is propagated from an input of the driver, a second transistor provided in a second pullup structure, the second transistor having a gate coupled to a control signal, and a control circuit that generates the control signal and that has an input configured to receive the data signal, the control circuit being configured to generate the control signal using an inverted, delayed version of the data signal when the second pullup structure is operated in a first mode, and maintain the control signal in a signaling state that turns off the second transistor when the second pullup structure is operated in a second mode.

In various aspects of the disclosure, an apparatus includes means for propagating a data signal from an input of a driver in an input/output circuit to a gate of a first transistor in a first pullup structure of the driver, and means for generating a control signal that is provided to a gate of a second transistor in a second pullup structure of the driver. The means for generating the control signal may be configured to generate the control signal by inverting and delaying the data signal when the second pullup structure is operated in a first mode. The control signal can be configured to turn off the second transistor when the second pullup structure is operated in a second mode.

In various aspects of the disclosure, a method for reconfiguring a driver in an I/O circuit includes causing a data signal to be propagated from an input of the driver to a gate of a first transistor in a first pullup structure of the driver, providing a control signal to a gate of a second transistor in a second pullup structure of the driver, generating the control signal by inverting and delaying the data signal when the second pullup structure is operated in a first mode, and configuring the control signal to turn off the second transistor when the second pullup structure is operated in a second mode.

In one aspect, the second pullup structure provides one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode.

In certain aspects, the control circuit is further configured to generate the control signal by propagating a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode. The data signal may have a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode. The data signal may have a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode. The second transistor may be implemented using a thin-oxide P-type metal-oxide-semiconductor (PMOS) transistor. The first transistor may be a thin-oxide N-type metal-oxide-semiconductor (NMOS) transistor.

In certain aspects, the control signal can be configured to cause the first transistor to pull an output of the reconfigurable driver toward a high voltage level while the data signal is at a first signaling state. The control signal may be configured to cause the second transistor to pull the output of the reconfigurable driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state. The control signal may be configured to turn off the second transistor before the data signal returns to the second signaling state.

In certain aspects, the second transistor is turned off after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode. The delay may be determined by timing of the control signal generated by the control circuit when the second pullup structure is operated in the first mode.

In certain aspects, the first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a low-power double data rate synchronous dynamic random access memory.

DETAILED DESCRIPTION

The terms “computing device” and “mobile device” are used interchangeably herein to refer to any one or all of servers, personal computers, smartphones, cellular telephones, tablet computers, laptop computers, notebooks, ultrabooks, palm-top computers, personal data assistants (PDAs), wireless electronic mail receivers, multimedia Internet-enabled cellular telephones, Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a programmable processor. While the various aspects are particularly useful in mobile devices (e.g., smartphones, laptop computers, etc.), which have limited resources (e.g., processing power, battery, size, etc.), the aspects are generally useful in any computing device that may benefit from improved processor performance and reduced energy consumption.

The term “multicore processor” is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term “multiprocessor” is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

The term “system on chip” (SoC) is used herein to refer to a single integrated circuit (IC) chip that contains multiple resources and/or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio-frequency functions. A single SoC may also include any number of general purpose and/or specialized processors (digital signal processors (DSPs), modem processors, video processors, etc.), memory blocks (e.g., read only memory (ROM), random access memory (RAM), flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

Process technology employed to manufacture semiconductor devices, including IC devices is continually improving. Process technology includes the manufacturing methods used to make IC devices and defines transistor size, operating voltages and switching speeds. Features that are constituent elements of circuits in an IC device may be referred as technology nodes and/or process nodes. The terms technology node, process node, process technology may be used to characterize a specific semiconductor manufacturing process and corresponding design rules. Faster and more power-efficient technology nodes are being continuously developed through the use of smaller feature size to produce smaller transistors that enable the manufacture of higher-density ICs.

ICs typically provide multiple voltage domains for power saving purposes. For example, higher voltage domains provide power at higher voltage levels than lower voltage domains. Higher voltage domains are sometimes needed for interfacing with external devices, while core logic circuits can generally operate at the lower voltage levels available in lower voltage domains. For the purposes of this disclosure, a thick-oxide transistor may refer to a transistor that has a gate oxide thickness sufficient to enable the transistor to withstand and operate at the higher voltage levels in higher voltage domains and a thin-oxide transistor may refer to a transistor that has a gate oxide thickness that is insufficient to avoid electrical overstress when the transistor spans a higher voltage level in the higher voltage domains. In certain examples disclosed herein, a thin-oxide transistor may be rated for voltages up to 0.6 volts and a thick-oxide transistor may be rated for voltages greater than 0.6 volts and thick-oxide transistors may be used in a higher a high-voltage domain that provides power at 1.2 volts.

Advancements in process technologies tend to reduce transistor gate length and other feature sizes with IC devices. Reductions in gate length and feature sizes can increase the susceptibility of IC devices to electrostatic discharge (ESD) events. IC devices often include ESD protection circuits that can protect interface circuits during different types of ESD events. IC devices may be tested to ensure that they meet minimum industry standards regarding ESD protection. IC device qualification processes may include testing the susceptibility of the IC device to ESD events based on a human-body model (HBM) or based on a charged-device model (CDM) characterization of ESD events. Some ESD protection circuits are based on or evaluated using an HBM or a CDM. The HBM is intended to characterize the susceptibility of devices to damage from ESD events of ±1 k Volt resulting from human touching of an electronic device. The CDM is intended to characterize the susceptibility of devices to damage from ESD events of ±250 Volts that relate to sudden discharges of energy accumulated in an IC chip or package through direct contact charging or field-induced charging.

FIG.1illustrates examples of components and interconnections in a system-on-chip (SoC)100, including a memory interface/bus126, that may be suitable for implementing certain aspects of the present disclosure. The SoC100may include a number of heterogeneous processors, such as a central processing unit (CPU)102, a modem processor104, a graphics processor106, and an application processor108. Each processor102,104,106,108, may include one or more cores, and each processor/core may perform operations independent of the other processors/cores. The processors102,104,106,108may be organized in close proximity to one another (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at a much higher frequency/clock rate than would be possible if the signals were to travel off-chip. The proximity of the cores may also allow for the sharing of on-chip memory and resources (e.g., voltage rails), as well as for more coordinated cooperation between cores.

The SoC100may include system components and resources110for managing sensor data, analog-to-digital conversions, and/or wireless data transmissions, and for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources110may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and/or other similar components used to support the processors and software clients running on the computing device. The system components and resources110may also include circuitry for interfacing with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

The SoC100may further include a Universal Serial Bus (USB) or other serial bus controller112, one or more memory controllers114, and a centralized resource manager (CRM)116. The SoC100may also include an input/output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.

The processors102,104,106,108may be interconnected to the USB controller112, the memory controller114, system components and resources110, CRM116, and/or other system components via an interconnection/bus module122, which may include an array of reconfigurable logic gates and/or implement a bus architecture. Communications may also be provided by advanced interconnects, such as high-performance networks on chip.

The interconnection/bus module122may include or provide a bus mastering system configured to grant SoC components (e.g., processors, peripherals, etc.) exclusive control of the bus (e.g., to transfer data in burst mode, block transfer mode, etc.) for a set duration, number of operations, number of bytes, etc. In some cases, the interconnection/bus module122may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously.

The memory controller114may be a specialized hardware module configured to manage the flow of data to and from a memory124via the memory interface/bus126. In some examples, the memory controller114includes one or more processors configured to perform read and write operations with the memory124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. Certain aspects disclosed herein may relate to a memory124that is included in an SoC100.

Memory technologies described herein may be suitable for storing instructions, programs, control signals, and/or data for use in or by a computer or other digital electronic device. Any references to terminology and/or technical details related to an individual type of memory, interface, standard, or memory technology are for illustrative purposes only, and not intended to limit the scope of the claims to a particular memory system or technology unless specifically recited in the claim language. Mobile computing device architectures have grown in complexity, and now commonly include multiple processor cores, SoCs, co-processors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnections (e.g., buses and/or fabrics), and numerous other resources that execute complex and power intensive software applications (e.g., video streaming applications, etc.).

Certain aspects of the disclosure are applicable to input/out (I/O) circuits that provide an interface between core circuits and memory devices. The memory124may include or incorporate Synchronous Dynamic Random Access Memory (SDRAM), including Low-Power double data rate SDRAM, which may be referred to as low-power DDR SDRAM, LPDDR SDRAM or, in some instances, LPDDRi SDRAM where i describes the technology generation of the LPDDR SDRAM. In one example, the memory124may be operated in LPDDR2 SDRAM and LPDDR4X SDRAM modes of operation, which may be referred to herein as the “LP2” and “LP4X” modes, respectively.

In some implementations, the memory124may include double data rate input/output (DDRIO) circuits that enable the memory124to communicate with corresponding DDRIO circuits in the SoC100or another device coupled to the memory124. DDRIO may be configurable for multi-mode operation. In some instances, a transmitter in the DDRIO of a memory124may include multiple circuits that perform the same function at different voltage levels when the memory124supports LP2 and LP4X modes of operation. Later generations of LPDDR SDRAM designed to operate at higher operating frequencies may employ lower voltage levels in the core of an SoC or memory device to mitigate for increased power associated with the higher operating frequencies.

Bandwidth available for signaling between a memory controller114and a memory124may be limited due to the effects of channel loss and other attenuations as well distortions in waveforms caused by unmatched terminations, interference and limitations of DDRIO circuits. Signal quality may vary according to operating conditions that may be characterized as all process, voltage, and temperature (PVT) corners. Certain aspects of this disclosure relate to DDRIO equalization techniques that can offset channel losses and other distortions to enable reliable high-speed operation in systems that employ LPDDR SDRAM. In one example, pre-emphasis equalization may be used by a driver in a DDRIO circuit to overdrive signals at transitions between signaling states, thereby providing an increased data sampling time at the receiver.

FIG.2illustrates certain aspects of a parallel bus interface200that may be provided in a memory controller coupled to high-speed LPDDR memory, for example. In some implementations, line drivers in the parallel bus interface200are expected to drive a two-rank LPDDR load. As used herein, two or more memory ranks coupled in parallel to a memory controller are accessed simultaneously by asserting a single chip select signal. The parallel bus interface200provides DDRIO circuits2021-202Nthat are coupled to corresponding terminals of each memory rank. In one example, a terminal may refer to a pad in an IC device to which a connecting wire may be bonded or otherwise contacted. Each of the DDRIO circuits2021-202Nmay be configured to transmit and/or receive a data signal (DQ), a differential strobe signal (DQS) or a Command/Address signal (CA). In some implementations, a single memory rank is coupled to the DDRIO circuits2021-202N. Each DDRIO circuits2021-202Nincludes a driver2081-208Nand a receiver2101-210N. The output of each driver2081-208Nand each receiver2101-210Nis coupled to an input/output (I/O) terminal2041-204Nof the parallel bus interface200. The receivers2101-210Nmay compare signaling state of a corresponding I/O terminal2041-204Nto a reference voltage level (e.g., VRef206) in order to decode data from the parallel bus that couples the parallel bus interface200to memory.

Certain features of a DDRIO circuit300are illustrated inFIG.3. The DDRIO circuit300may correspond to one of the DDRIO circuits2021-202Nillustrated inFIG.2and may be coupled to an I/O terminal310that represents one of the I/O terminals2041-204Nillustrated inFIG.2. In particular, the illustrated DDRIO circuit300corresponds to the configuration of one of the drivers2081-208Nillustrated inFIG.2. The I/O terminal310may be coupled to a line312of a high-speed parallel bus that interconnects a memory controller and one or more memory devices. An ESD protection circuit306, which may be HBM-qualified, may be coupled to the I/O terminal310. The illustrated ESD protection circuit306includes a two diodes314,316that are reverse biased unless a current surge causes a voltage at the I/O terminal310to exceed the nominal or rated voltage of the power supply provided to the DDRIO circuit300. For the purposes of this description, the I/O terminal310may correspond to a pad in an IC device or SoC that facilitates bonding or contacting with a connecting wire or other interconnect.

The DDRIO circuit300includes multiple driver segments3021-3026and an equalizer circuit304. The number of driver segments3021-3026provided in the DDRIO circuit300may be determined by the characteristics of the line312that is to be driven and the nature and value of termination at the transmitting and/or or receiving devices. In the example of LPDDR SDRAM, the line312may be unterminated when low-power, lower-frequencies are transmitted. Lower frequency signals may be transmitted at higher voltage levels than higher frequency signals. Higher frequency signaling in LPDDR SDRAM applications may use signaling transmitted at near-ground voltage levels and line terminations may be provided.

The number of driver segments3021-3026used to drive the line312may be calculated to provide a desired current or voltage level on the line312. The number and nature of the driver segments3021-3026used to drive the line312may be selected to meet a specified or desired transition time of a signal (Padsig308) to be transmitted over the line312through the I/O terminal310. Certain LPDDR specifications require that DDRIO circuits support aggressive scaling of the voltage of (VDDA) core power rails in order to support higher power optimization. The number and type of driver segments3021-3026used to drive the line312may be dynamically selected based on mode of operation.

The multiple driver segments3021-3026in the DDRIO circuit300may be configured to support different drive strengths and on-die DQ termination (ODT) requirements. In the illustrated example, each driver segment3021-3026is calibrated to provide a pull-down impedance of 240 ohms. Pull-up may be calibrated to a nominal high output voltage (VOH) target, which may be specified with reference to the output power rail voltage (VDDIO). VOHrepresents the minimum required voltage swing for a defined mode of operation. In the example of LPDDR6 memory, VOH=0.5*VDDIOfor terminated lines and VOH=VDDIOfor unterminated lines.

The bandwidth of the DDRIO circuit300is limited by certain alternating current (AC) characteristics of the active driver segments3021-3026, the equalizer circuit304, the ESD protection circuit306and the line312coupled to the I/O terminal310, which can contribute to the I/O capacitance (CIO) measured at the I/O terminal310. CIOis typically a critical parameter and can limit AC performance at higher frequencies. The equalizer circuit304may be configured to offset certain effects of CIOand other parameters that may introduce distortion and non-linear response of the DDRIO circuit300and line312. In some examples, the equalizer circuit304may be configured to provide or approximate pre-emphasis in order to mitigate for channel loss and linear inter-symbol interference (ISI). ISI can distort signals when a pulse or an edge transmitted in a time interval (i.e., a unit interval or UI) is affected by a pulse or an edge transmitted in a preceding UI due to non-linear frequency response of the line312, for example. The equalizer circuit304may be provided to enable the DDRIO circuit300to operate at, or switch between standards-defined frequencies for LPDDR SDRAM of 6.4 GHz and 4.8 GHz, for example.

FIG.3also illustrates an interface320that includes a DDRIO circuit322in an SoC and a DDRIO circuit324in a memory device, where a line326of a parallel bus (also referred to as a channel) couples the two DDRIO circuits322,324. In the illustrated interface, a termination resistance330is provided in the driver328of the DDRIO circuit324provided in the memory device. The resistance330may be implemented as a variable resistor for which resistance can be configured to accommodate changes between low-speed, high-voltage and high-speed, low-voltage modes of operation.

FIG.4illustrates an example of a transmission path in a data communication system400that may be adapted in accordance with certain aspects of this disclosure. The data communication system400includes a transmitter402, a data communication channel410, and a receiver422. The transmitter402may be provided in a first device that is configured to transmit a data signal to a second device. The data communication channel410provides a transmission medium through which a transmitted data signal propagates from the first device to the second device. The receiver422is provided in the second device and may be configured to receive and process a received data signal434.

In one example, the transmitter402includes a data source404configured to provide a stream of data for transmission through the data communication channel410. The transmitter402further includes a transmit driver (TX406) configured to generate the transmitted data signal for transmission to the receiver422over the data communication channel410. The data communication channel410may be implemented using any type of transmission medium by which a data signal can propagate from the transmitter402to the receiver422. In certain examples, the data communication channel410includes one or more metallization traces (which may include one or more vias) on a printed circuit board (PCB), stripline, microstrip, coaxial cable, twisted pair, etc.

For the purposes of this disclosure, the illustrated receiver422includes an amplifier424, which may be implemented in a single stage or multiple stages, a clock recovery circuit428, and a data recovery circuit426. In some instances, the amplifier424may be configured to perform equalization and amplification of the received data signal434. For example, the amplifier424may be implemented as a variable gain amplifier (VGA) and may be coupled to or include a continuous time linear equalizer (CTLE). A CTLE may implement techniques for boosting the higher frequency components of the signal at the receiver in order to bring all frequency components of the signal to a similar amplitude. A clock recovery circuit428may be configured to receive a clock input436and/or to recover clock information associated with the data signal434. In one example, the clock input436is a version of a clock signal received from the transmitter402. The clock recovery circuit428may generate a data recovery clock signal442that can be used by the data recovery circuit426to sample or otherwise capture the serial data from the amplified data signal438and output recovered data430. The clock recovery circuit428may be configured to provide edges (transitions) in the data recovery clock signal442, where the edges are timed to fall within the window of stability during which data can be reliably sampled. The data recovery clock signal442may be provided in two or more phase versions that can be used directly by the data recovery circuit426.

The data signal434or the clock signal received from the transmitter402may be distorted during transmission through the data communication channel410. Distortion may arise for various reasons including impedance mismatches in the data communication channel410, interference and reflected energy. Signal distortion can make it difficult to recover the clock information and the data by the clock recovery circuit428and can limit the window of stability during which data can be reliably sampled from the amplified data signal438. In some examples, distortion in the received data signal434caused by high frequency attenuation can be addressed by the amplifier424, which may be configured to perform equalization and amplification that increases the high frequency components of the received data signal434in order to increase the data rate at which the data may be sent through the data communication channel410and reliably recovered at the receiver422.

The window of stability during which data can be reliably sampled may be visualized in an eye-diagram.FIG.5illustrates one example of an eye diagram500generated as an overlay of signaling state for bit transmissions in multiple bit transmission intervals502, which may also be referred to as UIs. In the illustrated example, a bit transmission can occur in one bit transmission interval502that spans a full cycle or half-cycle of a transmitter clock signal. A signal transition region504represents a time period of uncertainty at the boundary between two symbols where variable signal rise times prevent reliable decoding. State information may be determined reliably in a region defined by an eye opening506that encompasses the window of stability, and that represents the period of period in which signaling state is stable and the bit value can be reliably sampled and captured. The eye opening506may be used to define a region in which signal mid-point crossings do not occur. A receiver or decoder can be designed on the assumption that the eye opening506represents or delineates a window of stability in which signaling states can be reliably distinguished and in which information can be reliably sampled, demodulated or decoded from a data signal. The window of stability may be determined based on minimum and maximum voltage thresholds. The eye opening506may be narrowed along the time axis by increases in data rate and may be compressed in the voltage axis as a result of ISI and other types of interference and distortion. The eye opening506may be narrowed along the time axis when rise times or fall times for a data signal differ.

The concept of periodic sampling and overlaid display of the signal is a useful aid for the design, adaptation and configuration of systems that use clock and data recovery circuits. In some examples, clock and data recovery circuits are designed to re-create the received data-timing signal using frequent transitions detected in the received data. The eye opening506in an eye diagram500observed, simulated or computed as a basis for judging the ability of a clock and data recovery circuit to reliably recover data.

FIG.5also provides an example of an eye-diagram520that shows the combined effect of distortion and jitter on a data signal received from a high-speed serial data channel. In the illustrated example, a tradeoff between the height524and width522of the eye opening526may be needed to provide an adequate duration of time in which transitions can be reliably detected. Reductions in height524of the eye opening526may result from moving detection thresholds of the transitions of the received data signal to provide sufficient duration of time in which the data signal can be sampled. The width522of the eye opening526is determined in part by the variability in phase shift between in-phase and quadrature-phase clock signals. Increasing precision of the phase shift between in-phase and quadrature-phase clock signals can enable operation that produces an eye opening526with narrower width522and a correspondingly greater height524.

An input/output circuit provided in accordance with certain aspects of this disclosure can be configured to offset channel losses and other distortions and enable reliable high-speed operation in LPDDR systems and other types of high-speed interfaces. Channel losses and other distortions can be offset or minimized by an equalization circuit embedded in a driver circuit. In some implementations, an equalization circuit embedded in a line driver can be configured to perform dynamic voltage frequency scaling (DVFS) and/or other equalization techniques while optimizing pad capacitance. DDRIO circuits provided in accordance with certain aspects of this disclosure circuits can be used to facilitate impedance matching. For example, a driver circuit equipped with an embedded equalization circuit can be configured to help match impedance presented by an SoC or DRAM to an interconnect or link that provides a data communication channel across different voltage frequency bands, and the driver circuit can minimize channel discontinuities and maximize performance of the data communication channel.

FIG.6illustrates the structure of a conventional DDRIO circuit600, which may correspond in some respects to the DDRIO circuit300illustrated inFIG.3or to one of the DDRIO circuits2021-202Nillustrated inFIG.2. The output of the illustrated DDRIO circuit600is provided at an I/O terminal620. The illustrated DDRIO circuit600may correspond to one of the drivers2081-208Nillustrated inFIG.2. In one example, the I/O terminal620is coupled to a data or control channel of a high-speed parallel bus that interconnects a memory controller and one or more memory devices. For the purposes of this description, the term I/O terminal may refer or correspond to a pad in an IC device or SoC that facilitates bonding or contacting with a connecting wire or other interconnect.

The DDRIO circuit600includes multiple driver segments610and an equalizer block630. A first CDM-qualified ESD protection circuit606protects the driver segments610, while a second CDM-qualified ESD protection circuit636protects the equalizer block630. In the illustrated example, the first ESD protection circuit606and the driver segments610are coupled to the I/O terminal620through a first resistance608while the second ESD protection circuit636and the equalizer block630are coupled to the I/O terminal620through a second resistance638. The number of driver segments610provided in the DDRIO circuit600may be determined by the characteristics of the data or control channel that is to be driven and by the nature and value of termination at the transmitting and/or or receiving devices. In the example of LPDDR SDRAM, the line or channel may be unterminated when low-power, lower-frequencies are transmitted. Lower frequency signals may be transmitted at higher voltage levels than higher frequency signals. Higher frequency signaling in LPDDR SDRAM applications may use signaling transmitted at near-ground voltage levels and line terminations may be provided.

The number of the driver segments610used for any selected operating mode may be calculated to provide a desired current or voltage level through the I/O terminal620. In some instances, the number and nature of the driver segments610may be selected to meet a specified or desired transition time of edges in a signal (Padsig632) to be transmitted through the I/O terminal620. In some instances, the number and type of driver segments610may be dynamically selected based on the voltage level of a first power rail (VDDIO626) that supplies the input/output circuits, as measured with respect to a second power rail (VSSX628). Certain LPDDR specifications require that DDRIO circuits support aggressive core power rail voltage (VDDA) scaling to support higher power optimization and to provide for voltage levels of VDDIO626that can vary. For example, VDDIO626may supply power at 0.5 Volts for lower-speed unterminated modes and at either 0.5 Volts or 0.3 Volts for higher-speed, terminated modes.

The driver segments610may be designed or configured to provide selectable drive strengths and/or to meet on-die DQ termination requirements. In the illustrated example, each of the driver segments610includes a pullup section602and a pulldown section604. The pullup section602may include N-type metal-oxide-semiconductor (NMOS) transistors612and614and P-type metal-oxide-semiconductor (PMOS) transistors616and618, which provide independently controlled pullup structures. The pulldown section604may include NMOS transistors622and624that are configured or selected to enable the DDRIO circuit600to meet a standards defined impedance target. In the illustrated example, the NMOS transistors622and624each provide a pulldown impedance of 240Ω. In one example, a pullup structure that includes PMOS transistors616,618may be required in addition to a pullup structure that includes thin-oxide NMOS transistors612,614to meet the minimum high output voltage level at lower speeds when the high output voltage level target is set at 0.5V and VDDAof the integrated circuit device is reduced. In the latter example, the pullup structure that includes the PMOS transistors616,618may be disabled for high-speed, low output voltage target modes.

The bandwidth of the DDRIO circuit600is limited by channel loss and a channel RC constant calculated as the product of driver resistance and load capacitance (RDriver×CLoad) Each of the driver segments610, the equalizer block630and the ESD protection circuits606,636contributes to an I/O pad capacitance (CIO) added by the DDRIO circuit600to the load capacitance. For the purposes of this discussion, CIOis measured at the I/O terminal620. CIOcan limit AC performance at higher frequencies. In one example, the addition of the equalizer block630can be expected to contribute approximately 10% of the overall I/O pad capacitance in certain SoCs configured to support LPDDR6 memory operation.

The illustrated DDRIO circuit600includes seven driver segments610and an equalizer block that includes a single equalizer segment. The equalizer block630may be configured to offset certain effects of CIOand other parameters that may introduce distortion and non-linear response of the DDRIO circuit600and line or channel. In some examples, the equalizer block630may be configured to effectively increase drive prior to, or during transmission of an edge or transition in Padsig632in order to mitigate for channel loss and linear intersymbol interference (ISI). ISI can distort signals when a pulse or an edge transmitted in a time interval (i.e., a unit interval or UI) is affected by a pulse or an edge transmitted in a preceding UI. The equalizer block630may enable the DDRIO circuit600to operate at, or switch between standards specified frequencies of 6.4 GHz and 4.8 GHz, for example.

The graph640inFIG.6illustrates the effect of increased CIOattributable to the inclusion of the equalizer block630. The graph640plots the eye opening at the input to a memory device against increases in CIO. In the illustrated example, which may relate to 6.4 GHz operation, eye opening is decreased or degraded by approximately 12% when the equalizer block630increases CIOby 8%.

Certain aspects of this disclosure relate to a DDRIO circuit that includes an equalizer that is integrated into one or more driver segments of the DDRIO circuit. In one aspect, the equalizer may be enabled for certain operational modes and/or operating frequencies of the DDRIO circuit. A DDRIO circuit implemented in accordance with certain aspects of this disclosure can operate without an external or separate equalizer circuit. In one example, an equalizer that is embedded in a driver segment of the DDRIO circuit can be configured to provide pre-emphasis drive to an output signal in advance of, or during transmission of an edge or transition in the output signal. Pre-emphasis may be provided using a one-shot equalization circuit that responds to transitions in a signal received by the driver segment for transmission over a high-speed serial bus. The equalizer can be embedded in the driver segment of the DDRIO circuit without significantly affecting the I/O capacitance at a pad through which the output signal is transmitted.

FIG.7includes a schematic representation of a DDRIO driver700that includes one or more embedded, reconfigurable equalizers that may be configured in accordance with certain aspects of this disclosure. The DDRIO driver700includes multiple driver circuits provided in parallel driver segments. In the illustrated example, the driver700includes seven driver segments7061-7067, each driver segment7061-7067having an output coupled to an I/O terminal710. Each driver segment7061-7067can be configured to contribute a drive current to an output signal (Padsig714).

The illustrated driver segment7061may be representative of all of the driver segments7061-7067, although different driver segments7061-7067may controlled independently such that the drive strength of the DDRIO driver700and the I/O capacitance (CIO) of the I/O terminal710can be configured based on operational mode of the DDRIO driver700. The illustrated driver segment7061includes a one-shot circuit720and a variable pullup structure718in line driver708that can be configured to provide a pre-emphasis drive current to Padsig714in certain operational modes of the DDRIO driver700. In some instances, the one-shot circuit720responds to edges in a data signal702by generating a pulse in a pullup enable signal712when one-shot equalization is enabled. The variable pullup structure718can increase drive current provided to the Padsig714when enabled by the presence of the pulse in the pullup enable signal712. The duration, phase and other timing aspects of the pulse may be configured or calibrated during initialization or during transitions between operating modes. An enable signal704may enable or disable the operation of the one-shot circuit720and may prevent activation of the variable pullup structure718. In some operational modes, the one-shot circuit720may be configured by control signals704,730,736that may, for example, activate the variable pullup structure718and/or cause the variable pullup structure718to augment the drive provided by other pullup structures716in the line driver708by transmitting a version of the data signal702.

FIG.7illustrates an example of a one-shot circuit720that may be implemented in a DDRIO driver700in accordance with certain aspects of this disclosure. The one-shot circuit720receives the data signal702and a control signal (OneShot_Enb signal704). In the illustrated example, the data signal702is gated by OneShot_Enb signal704using an AND gate722. The data signal702is propagated through the AND gate722(as the Data_int signal732) when OneShot_Enb signal704is in a first, enabling signaling state and blocked when OneShot_Enb signal704is in a second, disabling state. When disabled, the output of the one-shot circuit720may be driven to a signaling state that disables the variable pullup structure718. The variable pullup structure718may be disabled by causing it to enter a high impedance state, for example.

Reference is also made toFIG.8, which illustrates certain aspects of the operation of the DDRIO driver700. In accordance with certain aspects of this disclosure, the OneShot_Enb signal704may be used to generate a pulse in the Data_int signal732. In one example, the OneShot_Enb signal704may be provided as an inverted delayed version of the data signal702. The schematic drawing820inFIG.8illustrates the use of delay element824to obtain the data signal702and the OneShot_Enb signal704from an output of a preamplifier that provides a base data signal822. In one example, the delay element is provided by a set of series connected gates. The timing of the data signal702and the OneShot_Enb signal704causes the output of the AND gate722to switch to a high signaling state for a short duration commencing with a rising edge802in the data signal702, as illustrated by the timing diagrams800provided inFIG.8. The OneShot_Enb signal704, being the inverted delayed of the data signal702, is in the high signaling state when the rising edge802in the data signal702occurs. The AND gate722drives Data_int signal732to the high signaling state when both the data signal702and the OneShot_Enb signal704are in the high state. After a delay (TPre804) that corresponds to the delay between the data signal702and the OneShot_Enb signal704, the OneShot_Enb signal704transitions806to a low signaling state and the AND gate722drives Data_int signal732to the low signaling state. The resultant pulse808in the Data_int signal732may be used to activate the variable pullup structure718in line driver708for a short duration of time.

The timing diagrams800also illustrate an example of the effect of pre-emphasis on Padsig714, which is transmitted by the DDRIO driver700ofFIG.7. Timing diagram812illustrates an example of Padsig714when no pre-emphasis equalization is applied. The relatively slow rising edge810in an unequalized Padsig714can negatively impact the height of the eye opening observed at a receiver. Timing diagram814illustrates the timing of a drive current or increased voltage applied to Padsig while the pulse808is present in the Data_int signal732. Timing diagram816illustrates Padsig714with an improved, faster rising edge818with added pre-emphasis equalization when the pulse808is present in the Data_int signal732.

In the illustrated example, the Data_int signal732is provided to a first input of a multiplexer726and a delay circuit724. The output734of the delay circuit724is received at one or more other inputs of the multiplexer726. In some implementations, the delay circuit724can be used to calibrate the timing of the pulse808in the Data_int signal732. For example, the delay circuit724may be configured to delay the Data_int signal732using a series of logic gates that can adjust the timing of the pulse808to match propagation delays affecting the data signal702. In the latter example, the data signal702may be coupled to the line driver708through a series of buffers that each introduce a gate delay that can be matched by the delay circuit724. The multiplexer726may respond to a control signal736that selects between the Data_int signal732and a delayed version of the Data_int signal732provided by the delay circuit724. In some implementations, the delay circuit724provides multiple delayed versions of the Data_int signal732to the multiplexer726that enable fine tuning of the timing of the pulse808with respect to edges in the data signal702.

In some implementations, the OneShot_Enb signal may be used as a control signal that can enable or disable the operation of the one-shot circuit720. In some of these implementations, the delay circuit724or an associated circuit generates pulses with different durations. The Data_int signal732in these implementations is a gated version of the data signal702. The multiplexer726receives a multi-signal output734from the delay circuit724and responds to a multi-bit control signal736by selecting an output738from among the Data_int signal732and the multiple signals output by the delay circuit724. The multiplexer726may provide a version of the data signal702or a selectable duration pre-emphasis pulse to enable the variable pullup structure718in the line driver708. In one example, the version of the data signal702may be provided to the variable pullup structure718when the line driver708is operated at lower frequencies and a pulse of desired duration may be provided to the variable pullup structure718when the line driver708is operated at higher frequencies.

In certain implementations, the delay circuit724may be configured to generate or provide versions of pulses with different durations and different widths at its output734. An output gate728responsive to an external control signal that enables or disables the variable pullup structure718regardless of the state or operation of the one-shot circuit720. For example, a controller may provide a global driver enable signal (Driver_Enableb730) for the memory interface that enables at least the variable pullup structure718in all DDRIO circuits to be disabled.

FIG.9is circuit diagram illustrating an example of a driver segment900of a DDRIO circuit that is configured in accordance with certain aspects of this disclosure. The driver segment900includes a pre-driver stage902, a main driver stage904and a control circuit906. The pre-driver stage902illustrates an interface between a low voltage core of an SoC or other IC device and the higher-voltage DDRIO circuit in which the main driver stage904is provided. The control circuit can be configured in some modes of operation to provide pre-emphasis control signaling when one-shot pre-emphasis equalization is enabled and/or to enable supplemental driving for lower speed modes of operation when power supplies in the DDRIO circuit are provided at higher voltages. The driver segment900is coupled to an input data signal910and transmits an output signal (Padsig916) through an I/O terminal960, where Padsig916is an amplified or repeated version of the input data signal910. The illustrated driver segment900includes a CDM-qualified ESD protection circuit912and an HBM-qualified ESD protection circuit908that are coupled to the I/O terminal960. The CDM-qualified ESD protection circuit912and the HBM-qualified ESD protection circuit908are coupled to one another using a resistive component914.

The main driver stage904receives a pullup data signal932and a pulldown data signal934, which are both derived from the input data signal910. The pullup data signal932and the pulldown data signal934are configured by the pre-driver stage902to drive the gates of respective pullup and pulldown drive transistors944,946without exceeding voltage limits for the pullup and pulldown drive transistors944,946. In the illustrated example, the pullup transistor944is configured to selectively pull Padsig916to the voltage (VDDIO940) of the power supply provided to the DDRIO circuit, while the pulldown transistor946is configured to selectively pull Padsig916to the ground or common voltage950of the power supply provided to the DDRIO circuit. The pullup transistor944is coupled to VDDIO940through a pullup enable transistor942, while the pulldown transistor946is coupled to the ground or common voltage950through a pulldown enable transistor948. The pullup enable transistor942and pulldown enable transistor948are gated by respective enable signals958a,958bthat can be switched off to present a high impedance to the I/O terminal960when the driver segment900is to be disabled. The pullup enable transistor942and pulldown enable transistor948present a low impedance when enabled. In some instances, one or more of the enable signals958aand/or958bmay be configured to provide a desired channel resistance in the respective pullup enable transistor942and/or pulldown enable transistor948.

The pre-driver stage902includes buffer circuits922,924that are adapted or configured to generate the pullup data signal932and the pulldown data signal934from the input data signal910. The buffer circuits922,924may operate to cause the pullup data signal932and the pulldown data signal934to switch between the core power voltage rails, which are designated as VDDA920and VSSX930inFIG.9. In LPDDR systems, VDDA920may be subject to aggressive power scaling requirements, and the voltage level of VDDA920may vary considerably to meet these scaling requirements. A buffered, in-phase version of the input data signal910is provided to the pullup transistor944, which is implemented as an NMOS transistor in the illustrated pre-driver stage902. Accordingly, the pullup transistor944is turned on and pulls Padsig916to the high signaling state when the input data signal910is in a high signaling state. A buffered, inverse version of the input data signal910is provided to the pulldown transistor946, which is implemented as an NMOS transistor in the illustrated pre-driver stage902. Accordingly, the pulldown transistor946is turned on and pulls Padsig916to the low signaling state when the input data signal910is in a low signaling state.

The pre-driver stage902includes a pass gate circuit926, which may be provided to help match delays in the pullup data signal932with delays in the pulldown data signal934. In some implementations, the pass gate circuit926may provide protection to low-voltage transistors from the voltage differentials introduced by power scaling. In some implementations, the pass gate circuit926may protect low-voltage transistors from ESD events. In one example, the pass gate circuit926in the pullup buffer circuit922may be provided to avoid leakage when power scaling or an ESD event affects two or more power rails.

A reconfigurable pullup structure952in the main driver stage904is controlled by the control circuit906. The control circuit906includes a one-shot circuit962and a gated buffer964. The input data signal910is propagated to the one-shot output signal936through the gated buffer992when a gating signal966is in a first, enabling signaling state. The gated buffer992blocks the input data signal910from the one-shot output signal936when the gating signal966is in a second, disabling signaling state. In the illustrated example, the gated buffer964operates as an inverter when enabled by the gating signal966such that an inverted version of the input data signal910is provided to an PMOS transistor956in the reconfigurable pullup structure952. The PMOS transistor956is turned on and pulls Padsig916to the high signaling state when the input data signal910is in the high signaling state and when a second PMOS transistor954is turned on by an enabling signal. In some examples, the latter enabling signal is derived from the enable signal958acoupled to the gate of the pullup enable transistor942.

In some implementations, the one-shot circuit962may produce a gating signal966that is an inverted delayed version of the input data signal910. With reference again to the timing diagrams800ofFIG.8, the input data signal910and the gating signal966data signal may correspond to the data signal702and OneShot_Enb signal704illustrated inFIG.8. In some implementations, the one-shot circuit962may be configured in accordance with the one-shot circuit720illustrated inFIG.7. In other implementations, the one-shot circuit962may be implemented as a pulse generator using a combination of circuits such as delay elements, multiplexers, flipflops and combinational logic.

According to certain aspects of this disclosure the control circuit906and the main driver stage904may cooperate to provide a combination circuit that operates in a first mode as an embedded, reconfigurable equalizer within the illustrated driver segment900and as a PMOS pull-up driver in a second mode of operation. In certain implementations, the PMOS transistors954,956in the reconfigurable pullup structure952are implemented using thin-oxide technology and can support one-shot equalization when the driver segment900is operated at higher frequencies. The PMOS transistors954,956may also be used to provide additional drive capability in order to meet nominal high output voltage (VOH) targets at lower frequencies and when VDDA920is provided at low voltage levels. In one example, the higher frequencies at which the driver segment900may refer to I/O bus clock frequencies specified for LPDDR6 or LPDDR6x memory, including frequencies of 4.8 GHz, 6.4 GHz or higher. Lower frequencies may include I/O bus clock frequencies of 200 MHz-4.3 GHz, for example. The NMOS transistors942,944may be implemented using thick-oxide technology. It is contemplated that the concepts disclosed herein can be implemented using various combinations of thick-oxide NMOS transistors, thin-oxide NMOS transistors, thick-oxide POS transistors, thick-oxide PMOS transistors.

According to one aspect, the reconfigurable pullup structure952can enable the driver segment900to support dynamic voltage frequency scaling (DVFS). According to one aspect, the reconfigurable pullup structure952can minimize or optimize pad capacitance observed at the I/O terminal960and within the driver segment900. It can be expected that a reduction in capacitance will be obtained by the elimination of separate equalizer circuits and by the use of the reconfigurable pullup structure952in equalizer mode, driver mode, and other modes. Reductions in pad capacitance can amount to 8% or more.

According to one aspect, implementation of the reconfigurable pullup structure952to be used for one-shot equalization can reduce the area of an IC or SoC allocated for a DDRIO driver by 10% or more. In certain implementations, the improvement in eye-height at the receiver resulting from the presently-disclosed one-shot equalization circuit lies between 10%-16%, with greater improvement expected in some instances.

A reconfigurable driver in an I/O circuit provided in accordance with certain aspects of this disclosure may have a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. The first transistor has a gate configured to receive a data signal that is propagated from an input of the driver. In some examples, the second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

The control circuit has an input configured to receive the data signal and is configured to generate the control signal using an inverted, delayed version of the data signal when the second pullup structure is operated in a first mode, and maintain the control signal in a signaling state that turns off the second transistor when the second pullup structure is operated in a second mode. The control circuit may be further configured to generate the control signal by propagating a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode.

The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The data signal may have a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode. The data signal may be received at a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode.

In some implementations, the control signal is configured to cause the first transistor to pull an output of the reconfigurable driver toward a high voltage level while the data signal is at a first signaling state. The control signal may be configured to cause the second transistor to pull the output of the reconfigurable driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state. The control signal may be configured to turn off the second transistor before the data signal returns to the second signaling state.

In some implementations, the second transistor is turned off after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode. The delay duration may correspond to the duration of the delay applied the control circuit to the data signal when the control signal is being generated and when the second pullup structure is operated in the first mode.

The first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a LPDDR memory. The DDRIO driver700illustrated inFIG.7shows an example in which a plurality of reconfigurable drivers is coupled to an I/O terminal710of a transmitting device in LPDDR memory.

FIG.10is a flowchart1000illustrating an example of a method for reconfiguring a driver in an I/O circuit. The method may be implemented by a controller in a driver that is coupled to data communication link. In one example, the receiver may include the driver segment900illustrated inFIG.9.

At block1002, the controller may cause a data signal to be propagated from an input of the driver to a gate of a first transistor in a first pullup structure of the driver. At block1004, the controller may cause a control signal to be propagated to a gate of a second transistor in a second pullup structure of the driver. At block1006, the controller may cause the control signal to be generated by a circuit that is configured to invert and delay the data signal when the second pullup structure is operated in a first mode. At block1008, the controller may cause the control signal to be configured to turn off the second transistor when the second pullup structure is operated in a second mode. In some implementations, the second pullup structure provides one-shot equalization to an output of the driver when the second pullup structure is operated in the first mode. In some examples, the second transistor is implemented as a thin-oxide PMOS transistor. The first transistor may be implemented as a thick-oxide NMOS transistor. In some examples, the first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a LPDDR SDRAM.

In certain implementations, the controller may cause the control signal to be generated by propagating a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode. The data signal may have a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode. The data signal may have a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode.

In certain implementations, the control signal is configured to cause the first transistor to pull an output of the driver toward a high voltage level while the data signal is at a first signaling state. The control signal may be configured to cause the second transistor to pull the output of the driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state. The control signal may be configured to turn off the second transistor before the data signal returns to the second signaling state.

In certain implementations, the control signal is configured to turn off the second transistor after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode. The delay duration may correspond to the duration of the delay applied to the data signal when the control signal is being generated and when the second pullup structure is operated in the first mode.

In one example aspects, an apparatus includes means for propagating a data signal from an input of a driver in an I/O circuit to a gate of a first transistor in a first pullup structure of the driver, and means for generating a control signal that is provided to a gate of a second transistor in a second pullup structure of the driver. The means for generating the control signal may be configured to generate the control signal by inverting and delaying the data signal when the second pullup structure is operated in a first mode. The control signal may be configured to turn off the second transistor when the second pullup structure is operated in a second mode. In some examples, the second transistor is implemented as a thin-oxide PMOS transistor. The first transistor may be implemented as a thick-oxide NMOS transistor. In some examples, the first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a LPDDR SDRAM. In one example, the second pullup structure provides one-shot equalization to an output of the driver when the second pullup structure is operated in the first mode.

In certain implementations, the means for generating the control signal is configured to propagate a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode. The data signal can have a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode. The data signal may have a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode.

In certain implementations, the control signal can be configured to cause the first transistor to pull an output of the driver toward a high voltage level while the data signal is at a first signaling state. The control signal may be configured to cause the second transistor to pull the output of the driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state. The control signal may be configured to turn off the second transistor before the data signal returns to the second signaling state.

In some implementations, the means for generating the control signal is configured to configure the control signal to turn off the second transistor after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode. The delay duration may correspond to the duration of the delay applied to the data signal when the control signal is being generated and when the second pullup structure is operated in the first mode.

Some implementation examples are described in the following numbered clauses:1. A reconfigurable driver in an input/output (I/O) circuit comprising: a first transistor provided in a first pullup structure, the first transistor having a gate configured to receive a data signal that is propagated from an input of the driver; a second transistor provided in a second pullup structure, the second transistor having a gate coupled to a control signal; and a control circuit that generates the control signal and that has an input configured to receive the data signal, the control circuit being configured to: generate the control signal using an inverted, delayed version of the data signal when the second pullup structure is operated in a first mode; and maintain the control signal in a signaling state that turns off the second transistor when the second pullup structure is operated in a second mode.2. The reconfigurable driver as described in clause 1, wherein the second pullup structure provides one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode.3. The reconfigurable driver as described in clause 1 or clause 2, wherein the control circuit is further configured to: generate the control signal by propagating a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode.4. The reconfigurable driver as described in clause 3, wherein the data signal has a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode.5. The reconfigurable driver as described in clause 4, wherein the data signal has a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode.6. The reconfigurable driver as described in any of clauses 1-5, wherein the second transistor comprises a thin-oxide P-type metal-oxide-semiconductor (PMOS) transistor.7. The reconfigurable driver as described in any of clauses 1-6, wherein the first transistor comprises a thin-oxide N-type metal-oxide-semiconductor (NMOS) transistor.8. The reconfigurable driver as described in any of clauses 1-7, wherein the control signal is configured to cause the first transistor to pull an output of the reconfigurable driver toward a high voltage level while the data signal is at a first signaling state, wherein the control signal is configured to cause the second transistor to pull the output of the reconfigurable driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state, and wherein the control signal is configured to turn off the second transistor before the data signal returns to the second signaling state.9. The reconfigurable driver as described in any of clauses 1-8, wherein the second transistor is turned off after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode, and wherein the delay is determined by timing of the control signal generated by the control circuit when the second pullup structure is operated in the first mode.10. The reconfigurable driver as described in any of clauses 1-9, wherein the first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a low-power double data rate synchronous dynamic random access memory.11. An apparatus comprising: means for propagating a data signal from an input of a driver in an input/output circuit to a gate of a first transistor in a first pullup structure of the driver; and means for generating a control signal that is provided to a gate of a second transistor in a second pullup structure of the driver, wherein the means for generating the control signal is configured to generate the control signal by inverting and delaying the data signal when the second pullup structure is operated in a first mode, and wherein the control signal is configured.12. The apparatus as described in clause 11, wherein the second pullup structure provides one-shot equalization to an output of the driver when the second pullup structure is operated in the first mode.13. The apparatus as described in clause 11 or clause 12, wherein the means for generating the control signal is configured to propagate a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode.14. The apparatus as described in clause 13, wherein the data signal has a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode.15. The apparatus as described in clause 14, wherein the data signal has a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode.16. The apparatus as described in any of clauses 11-15, wherein the second transistor comprises a thin-oxide P-type metal-oxide-semiconductor (PMOS) transistor.17. The apparatus as described in any of clauses 11-16, wherein the first transistor comprises a thin-oxide N-type metal-oxide-semiconductor (NMOS) transistor.18. The apparatus as described in any of clauses 11-17, wherein the control signal is configured to cause the first transistor to pull an output of the driver toward a high voltage level while the data signal is at a first signaling state, wherein the control signal is configured to cause the second transistor to pull the output of the driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state, and wherein the control signal is configured to turn off the second transistor before the data signal returns to the second signaling state.19. The apparatus as described in any of clauses 11-18, wherein the means for generating the control signal is configured to: configure the control signal to turn off the second transistor after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode, wherein the delay is used by the means for generating the control signal to delay the data signal when generating the control signal.20. The apparatus as described in any of clauses 11-19, wherein the first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a low-power double data rate synchronous dynamic random access memory.21. A method for reconfiguring a driver in an input/output circuit, comprising: causing a data signal to be propagated from an input of the driver to a gate of a first transistor in a first pullup structure of the driver; providing a control signal to a gate of a second transistor in a second pullup structure of the driver; generating the control signal by inverting and delaying the data signal when the second pullup structure is operated in a first mode; and configuring the control signal to turn off the second transistor when the second pullup structure is operated in a second mode.22. The method as described in clause 21, wherein the second pullup structure provides one-shot equalization to an output of the driver when the second pullup structure is operated in the first mode.23. The method as described in clause 21 or clause 22, further comprising: generating the control signal by propagating a version of the data signal to the gate of the second transistor when the second pullup structure is operated in a third mode.24. The method as described in clause 23, wherein the data signal has a higher frequency when the second pullup structure is operated in the first mode than when the second pullup structure is operated in the third mode.25. The method as described in clause 24, wherein the data signal has a frequency of at least 4.8 gigahertz when the second pullup structure is operated in the first mode.26. The method as described in any of clauses 21-25, wherein the second transistor comprises a thin-oxide P-type metal-oxide-semiconductor (PMOS) transistor.27. The method as described in any of clauses 21-26, wherein the first transistor comprises a thin-oxide N-type metal-oxide-semiconductor (NMOS) transistor.28. The method as described in any of clauses 21-27, wherein the control signal is configured to cause the first transistor to pull an output of the driver toward a high voltage level while the data signal is at a first signaling state, wherein the control signal is configured to cause the second transistor to pull the output of the driver toward the high voltage level commencing at a transition of the data signal from a second signaling state to the first signaling state, and wherein the control signal is configured to turn off the second transistor before the data signal returns to the second signaling state.29. The method as described in any of clauses 21-28, further comprising: configuring the control signal to turn off the second transistor after a delay following a transition of the data signal from a first signaling state to a second signaling state when the second pullup structure is operated in the first mode, wherein the delay is used to delay the data signal when generating the control signal when the second pullup structure is operated in the first mode.30. The method as described in any of clauses 21-29, wherein the first pullup structure and the second pullup structure are provided in one of a plurality of reconfigurable drivers coupled to an output terminal of a transmitting device in a low-power double data rate synchronous dynamic random access memory.