Data communications systems

A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of priority of United Kingdom Patent Application No. 0611508.3 filed Jun. 10, 2006 with the United Kingdom Patent Office, the content of which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention generally relates to data communications systems and in particularly to receivers for data communications systems.

BACKGROUND OF THE INVENTION

A conventional data communication system comprises a first and a second node interconnected by an intervening serial data communication channel, such as a wire link or optical fiber link. The first node typically comprises a first data processing unit (DPU) connected to a transmitter. The output of the transmitter is connected to the channel. The transmitter typically comprises a data path for supplying serial input data from the first DPU to the channel. Likewise, the receiver typically comprises a data path for supplying data received from the channel to the second DPU.

The receiver typically comprises an up channel driver connected to the channel. Similarly the transmitter typically comprises an up channel receiver connected to the channel. The up channel driver and the up channel receiver, together with the channel, constitute an up channel communication subsystem for providing communication between the receiver and the transmitter. The up channel communication subsystem is typically employed by the receiver to send control data to the transmitter. The first DPU typically supplies control signals to the transmitter. Similarly, the second DPU typically supplies control signals to the receiver. The first node also typically comprises a receiver. Likewise, the second node also typically comprises a transmitter. In each node, the transmitter and the receiver are typically integrated into a unitary transceiver. The first and second nodes may comprise server computer systems in a data communication network.

In operation, data is serially communicated between the first and second nodes via the channel. The transmitter and receiver each typically comprise a serializer-deserializer (SERDES). In operation, the SERDES in the transmitter converts parallel data words into a serial bit stream for communication on the channel. In the receiver, the SERDES converts a bit stream received from the channel into parallel data words. Each SERDES is typically implemented in one or more integrated circuits. As improvements continue to be made in semiconductor technology, the performance of such integrated circuits continues to increase. Accordingly, each successive generation of SERDES is capable of handling an increased data rate.

The receiver comprises a signal detector. The signal detector comprises an amplifier and a comparator. In operation, the output from the amplifier is compared to a threshold value Vt by the comparator. The comparator has a hysteresis between its upper and lower switching thresholds. If the hysteresis width is 2Vh, then the upper and lower switching thresholds of the comparator are Vt−Vh and Vt+Vh. Signals less than the lower threshold are determined as invalid. Signals greater than the upper threshold are determined to be valid. There is a band of uncertainty between the upper and lower thresholds where the signal cannot be determined to be good or bad. The width of this band depends on range of circuit parameters including, for example, offset voltage. U.S. Pat. No. 6,897,712 and US20050093582A1 describe examples of conventional signal detectors.

Performance improvement techniques such as Decision Feedback Equalization (DFE) are employed in many data communication system to counter losses within the channel in the interests of achieving higher data rates. A receiver for performing DFE typically comprises an automatic gain control (AGC) loop having a variable gain amplifier (VGA). US20020136251 describes an example of an AGC for use with a signal detector. WO03030356A2 describes another conventional example of an AGC. US20050009483A1 describes an example of conventional AGC calibration.

A typical receiver comprises a signal detector and a cable detector. In operation, the signal detector detects the presence and absence of valid signals on the channel. A valid or good signal is a signal having a pulse height exceeding a preset upper threshold. An invalid or bad signal is a signal having a pulse height below a preset lower threshold. Depending on circuit accuracy, there is normally a region of uncertainty between the lower and upper thresholds in which a signal cannot be declared bad or good. This region is conventionally specified by end users.

In operation, the signal detector enhances the receiver by preventing the processing of potentially unreliable signals.

Specifically, in response to detection of the received signal level falling below the lower threshold, the signal detector alerts the receiving node to stop data processing. In such a situation, the received data may not be valid for one or more of a variety of reasons, including, without limitation, excessive noise in the received signal, excessive cross talk between channels, and signal loss in the channel. The cable detector can be employed to detect whether a cable carrying the channel is unplugged or shorted.

It is increasingly difficult to integrate this functionality into receiver designs as performance increases and available silicon area reduces. There is continuing demand for increasing the data rate that the signal detector is capable of handling without adversely affecting the accuracy with which the signal detector applies the upper and lower thresholds. These thresholds are relatively small. Therefore, the signal detector typically comprises an amplifier to amplify the input signal to facilitate subsequent threshold detection. As performance increases, the power consumption, and area of the amplifier also tends to increase. It would be desirable to improve signal detection performance and simultaneously to alleviate pressure for increased silicon real estate occupancy and power.

SUMMARY OF THE INVENTION

In accordance with the present invention, there is now provided a receiver for a data communications system, the receiver comprising: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

In a preferred embodiment of the present invention, the signal detector comprises a comparator for comparing the data valid signal to the threshold. The receiver may comprise a variable signal source for setting the threshold in dependence upon the gain information from the data path.

The data path may comprise a variable gain amplifier (VGA) for amplifying the data signal, the VGA having a gain control input connected to the AGC loop, the output of the VGA being connected to the comparator, the receiver further comprising logic connected to the gain control input of the VGA for alternately varying the gain of the VGA via the AGC loop in a data processing period and setting the gain of the VGA to a reference value during a signal sensing period, the reference value being defined via the AGC loop during a calibration of the receiver. Alternatively, the data path may comprise a first variable gain amplifier (VGA) for amplifying the data signal, the first VGA having a gain control input connected to the AGC loop; and, the signal detector may comprise a second VGA for amplifying the data signal, the receiver further comprising logic for setting the contents of the register to a reference value defined via the AGC loop during a calibration of the receiver. In a particularly preferred embodiment of the present invention, there is provided circuitry for applying a preset test signal to the data path and the signal detector during calibration. The AGC loop preferably comprises decision feedback equalization.

The present invention extends to a data communications systems comprising a first data processing node and a second data processing node interconnected by a data communications channel, wherein at least one of the first and second nodes comprising a receiver as herein before described.

Viewing the present invention from another aspect, there is now provided a method for data communications, the method comprising: receiving a data signal in a data path having an automatic gain control (AGC); and, generating, using a signal detector, a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.

The present invention also extends to apparatus comprising a plurality of electronic circuits including an amplifier for receiving and amplifying a data signal and an automatic gain control (AGC) loop for controlling the gain of the amplifier wherein at least one parameter in at least one other of the plurality of electronic circuits is variable in dependence on gain information from the AGC loop.

In a preferred embodiment of the present invention, there is provided a data communications system comprising a receiver having a signal detector and a data path. The signal detector comprises a preamplifier stage. The preamplifier stage comprises a VGA. The data path comprises an AGC. In operation, gain information from the AGC of the data path is derived from a known signal from preexisting circuitry such as preexisting up channel driver and/or wrap path circuitry. The gain information is employed to control the gain of the preamplifier stage. This reduces overall circuit complexity and improves the accuracy of the signal detector.

Embodiments of the present invention to be described shortly address the problem of performing accurate signal detection on relatively high data rates, such as data rates of the order of 6 Gb/s and beyond. However good accuracy and high speed operation is difficult to achieve by conventional means. Many conventional schemes are compromised in terms of accuracy because of technology and speed constraints.

In a particularly preferred embodiment of the present invention, there is provided a receiver for a data communications system, the receiver comprising: a data path having an AGC loop receiving an input signal from a communication channel; and a signal detector receiving the input signal in parallel to the data path. In operation, the signal detector detects any loss of the input signal. The AGC is not directly involved in that detection. However, gain information from the AGC is employed to determine and control switching thresholds of the signal detector by varying the gain of a VGA within the signal detector. In particularly preferred embodiments of the present invention, the circuitry of the AGC and the VGA in the signal detector are made at least similar and preferably identical in order that they track each other well. In operation, the AGC sets its output at a known level. If the input signal to the AGC is also known, the gain of the AGC can then be determined. The AGC gain thus determined is then used to control the gain in, and therefore the switching thresholds of the signal detector. The accuracy of the signal detector is thereby improved. In another preferred embodiment of the present invention, the function of the VGA in the signal detector is integrated with the AGC in the data path in the interests of simplicity.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 1, a data communication system comprises a first data processing node5connected to a second data processing node20via a communication channel30. The channel30may be wired or wireless. The first node5comprises a first data processing unit (DPU)10connected to a transmitter15. The output of the transmitter15is connected to the channel30. The transmitter15comprises a data path48for supplying serial input data D from the first DPU10to the channel30. Likewise, the receiver25comprises a data path35for supplying data D received from the channel30the second DPU40. The first DPU10and the second DPU40may be server computer systems, for example.

In operation, the data D is serially communicated between the first node5and second node20via the channel30. The first node5and the second node20each typically comprise a serializer-deserializer (SERDES). In operation, the SERDES in the first node5converts parallel data words into a serial bit stream for communication on the channel30. In the second node20, the SERDES converts a bit stream received from the channel30into parallel data words. The SERDES in the first node5may be integral to the first DPU10or the transmitter15. Similarly, the SERDES in the second node20may integral to the second DPU40or the receiver25.

The receiver25comprises an up channel driver45connected to the channel30. Similarly the transmitter5comprises an up channel receiver50connected to the channel30. The up channel driver45and the up channel receiver47, together with the channel30, constitute an up channel communication subsystem for providing communication between the receiver25and the transmitter15. The up channel communication subsystem can be employed by the receiver25to send control data to the transmitter15. The control data can be employed, for example, to inform the transmitter15to stop sending data, to resend the last group of data, or to set driver finite impulse response (FIR) tap coefficients in the interests of optimizing signal integrity and power performance.

The first DPU10supplies control signals C to the transmitter15. Similarly, second DPU40supplies control signals C to the receiver25. It will be appreciated that the first node5may also comprise a receiver. Likewise, it will be appreciated that the second node20may also comprise a transmitter. The transmitter and receiver in such nodes may be integrated into a unitary transceiver. The channel30as shown is single ended. However, in other embodiments of the present invention, the channel30may be differential.

Referring toFIG. 2, in addition to the data path35, the receiver25further comprises a signal detector50and a cable detector55both having inputs connected to the channel30. The outputs of the signal detector50and the cable detector55are connected to validity logic60.

Referring toFIG. 3, the signal detector55comprises an amplifier70and a comparator65. The amplifier70has a gain Av. In operation, the output of the amplifier70is compared to a threshold value vt by the comparator65. The comparator65has a hysteresis between its upper and lower switching thresholds. If the hysteresis width is 2Vh, then the upper and lower switching thresholds of the comparator65are Vt−Vh and Vt+Vh. Signals less than the lower threshold are determined as invalid. Signals greater than the upper threshold are determined to be valid. There is a band of uncertainty between the upper and lower thresholds where the signal cannot be determined to be good or bad. The width of this band depends on range of circuit parameters including, for example, offset voltage.

Referring the upper and lower switching thresholds to the input provides input switching levels of (Vt−Vh)/Av and (Vt+Vh)/AV. The amplifier70allows smaller input thresholds. This is desirable for some industry specifications such as Infiniband and allows more flexibility in the design of the comparator. However, a disadvantage of this approach is that demands a close tolerance in the gain of the amplifier70for accurate switching thresholds. Additionally, this approach also requires the signal detector50to operate at the incoming data rate. The combination of analog accuracy and high speed operation is difficult to achieve. Conventional solutions have required relatively high power and relatively large circuit area.

In a preferred embodiment of the present invention, calibration information from an automatic gain control loop (AGC) in the data path35is used to set the gain of the amplifier70accurately. In particularly preferred embodiments of the present invention, a variable gain amplifier (VGA) section of the AGC provides at least some of the functionality of the amplifier70. This reduces the power and area requirements of the signal detector50.

Referring now toFIG. 4, in one preferred embodiment of the present invention, the data path35comprises a variable gain amplifier (VGA)95connected to the channel30. The gain of the VGA95is digitally set by a digital vector supplied via a gain control input. The output of the VGA95is connected to a decision feedback equalization (DFE) summer85. The output of the summer85is connected to a latch90. The output of the latch is connected to DFE logic75. The DFE logic75has outputs connected to the DFE summer75and registers80and100. The output of the register80is connected to the gain control input of the VGA95. The signal detector50comprises a variable gain amplifier (VGA)70. The gain of the VGA70is digitally set by a digital vector supplied via a gain control input. The gain control input of the VGA70is connected to the output of the register100.

In operation, the DFE logic75sets the contents of the registers80and100and supplies tap coefficients to the DFE summer85. The DFE logic75and the register80collectively form an AGC feedback loop extending from the output of the latch90to the gain control input of the VGA95. The DFE logic75comprises mixed signal circuitry for tuning the gain of the VGA95through the register80. The output of the summer85is clocked into the latch90by a clock signal CLK. In preferred embodiments of the present invention, the clock signal CLK is recovered from the received signal by a clock recovery circuit (not shown). The validity logic60generates a validity signal V indicative of the validity of the received signal in dependence on the outputs of the comparator65and the cable detector55. The DFE logic75and the validity logic60receive control signal inputs C from the second DPU40.

The receiver25ofFIG. 4has a calibration mode of operation and a normal data processing mode of operation.

The calibration mode is triggered at power-on and following a signal detection failure.

The calibration mode may be initiated by a calibration command in the form of a binary control signal300from a second DPU40. In the calibration mode, a test signal comprising a stream of pulses with defined shape, height, and pattern is fed, under the control of the second DPU40, to the input of the VGA95via the up-channel driver45or other circuitry. The test signal is utilized to set a reference gain value of the VGA95. Specifically, the gain of the VGA95is adjusted under the control of the DFE logic75until the DFE logic75detects a signal at the output of the latch90with a known offset applied to the summer85. The latch90, the summer85, and the DFE logic75effectively act as a constant amplitude sensor. The digital value in the register80corresponding to the known input and output levels represents the reference gain of the VGA95. The DFE logic75effectively comprises a comparator function having a reference set to the desired output of the VGA95. The gain of the VGA95is adjusted by the DFE logic75until the comparator function just switches. For example, if the test signal has a known amplitude of 100 mV, the DFE logic75detects 300 mV signals, then a digital value indicative of a reference gain of 3 is set in the register80. The DFE logic stores the reference gain information recorded in the register80into the register100, thereby setting the gain of the VGA70to that established by the AGC in the data path. Calibration is then completed and the receiver25is placed in the data processing mode of operation.

In the data processing mode, the value stored in the register100is fixed. Therefore, then gain of the VGA70is fixed. However, the value of stored in the register80, and therefore the gain of the VGA95, is variable and controlled by the AGC loop. The signal detector50and the data path35operate simultaneously in parallel, with the data path35receiving incoming the data signal and the signal detector50simultaneously monitoring the incoming data signal for detection of a fault. In the event that a fault is detected, the output of the receiver is disabled or otherwise flagged as invalid via the valid signal output V of the validity logic60. The signal detector50and the validity logic60continues to monitor the channel30for a predefined time period in the event that transmission of the data signal recovers. If the time period expires without recovery of the data signal, the receiver25can be powered down for repair.

It will be appreciated that VGA95and/or VGA70may be implemented by a programmable gain amplifier having a digitally controllable gain.

Referring toFIG. 5, in another embodiment of the present invention, the VGA95is common to both the data path35and the signal detector50. The simplification permits omission of the VGA70. The output of the VGA95is connected to the inputs to the comparator65and the summer85. In this arrangement, the receiver25has a signal sensing mode of operation in addition to the aforementioned calibration and data processing modes. In operation, the signal sensing and data processing modes are interleaved so that the validity of the data signal on the channel30is periodically checked.

An operating protocol for the receiver25ofFIG. 5will now be described with reference to the flow chart ofFIG. 6in combination with the signal diagram ofFIG. 7.

At power on, block200, the receiver25enters the calibration mode, block210. The calibration mode may be initiated by a calibration command in the form of a binary control signal300from a second DPU40. Normally, the control signal300is at first value. However, when the calibration mode is required, the control signal300is set to a second value. In the calibration mode, the aforementioned test signal310is fed to the input of the VGA95. The test signal310is utilized to set the reference gain value of the VGA95as hereinbefore described. The reference gain value set by the AGC is stored in the register80. Calibration is then completed. The control signal300returns to its normal state. The receiver25is then placed in the signal sensing mode, block220.

In the signal sensing mode, the data path35is effectively disabled. The gain of the VGA95is set to the reference gain value stored in the register80. The content of the register80is fixed to the reference gain value. Incoming data is received by the VGA95. The incoming data is amplified by the VGA95to produce an amplified signal. The amplified signal is supplied to the comparator65. The comparator65compares the amplified signal to a preset threshold to detect the incoming data. The output of the comparator65is supplied to the validity logic60. If, based on the output from the comparator65, the validity logic60determines that the incoming data is valid, then the receiver25is placed in the data processing mode, block230.

In the data processing mode, the comparator65is effectively disabled. The content of the register80is released so that the gain of the VGA95can be controlled by the AGC loop. The receiver25processes incoming data for a preset data processing period during which the gain of the VGA95is controlled by the DFE logic75via the register80. In the data processing period, n serial blocks of data are received, where is n is an integer. In the data processing mode, the gain of VGA95is constantly adjusted by the feedback control from the DFE logic75and the register80in the AGC loop. In the signal sensing mode, the register80is reloaded with the gain value determined during calibration which is then employed to set the gain of the VGA70to sense the incoming signal. After each nth block is received, operation of the receiver25is returned to the signal sensing mode, block220.

The signal sensing mode is periodically retriggered by the receiver25receiving a signal detection control signal320from the second DPU40. The control signal320may be similar to the aforementioned calibration control signal300. In the signal sensing mode, the signal detection process hereinbefore described is repeated, block220. If a valid signal is detected, the receiver25proceeds to receive next n blocks of data in the data processing mode of operation, block230. However, if the validity logic60detects an invalid signal at the output of the comparator65, then the data transfer is stopped, block240. If the data transfer is stopped, the last n blocks of data received are judged to be bad, block240. The validity logic60checks the connection of the channel30via the cable detector55, block250. If the cable detector55detects connection of the channel30, then the receiver25is placed back into calibration mode at block210. If however, the cable detector55detects a fault in the channel30, then the receiver25may periodically poll the channel30for a predetermined period to determine if transmission of the data signal recovers. If no such recovery is detected within the predetermined period, then the receiver25can be powered down, block260, for repair, block270. Trace330inFIG. 5exemplifies the output of the comparator65both for tests in which a signal is detected and in which no signal is detected.

In the event that the calibration mode is reactivated, the reference gain value stored in the register80may be retained or changed to a new value. Once recalibration is complete, the receiver25is placed back in the signal sensing mode. The calibration mode may be invoked for a range of reasons, such as performance variations arising through temperature and other environmental changes.

Depending on the circuit implementation, the gain of the VGA70can be defined relatively accurately. This is because the aforementioned circuitry involved in setting the digital value is all sited in the receiver25. The circuitry involved is thus subject to bias from the same sources. The accuracy with which the gain of the VGA70is defined therefore depends mainly on device matching. This can be accurately controlled by integrating all the circuitry involved on a single semiconductor chip.

In a particularly preferred embodiment of the invention, the receiver25comprises a SERDES receiver system on a chip having an AGC. The AGC is adapted in such a manner that it can provide gain information to a signal detector50of the receiver25and other subsystems on the chip. The AGC includes a VGA95. The gain information to be shared is determined by supplying the VGA95with a test signal comprising a stream of training bits with specified format and amplitude. The test signal can be generated either internally or externally to the chip. When a constant amplitude sensor in the DFE logic75senses the signal, the corresponding gain coefficient is selected and saved. Once calibration is completed, the system is ready for other signal sensing operations and data transfer. In one embodiments of the present invention hereinbefore described, after “n” packets of data are transferred, the receiver25performs a signal detecting operation. All received data is assumed to be valid provided that the subsequent signal is detected to be good. Otherwise, the receiver first checks the cable and related hardware for defects and faults. If no faults are identified, then the receiver may recalibrate and resume data transfer. Otherwise the receiver can be powered down for repair, loops while waiting for good data, or reports a fault.

In a particularly preferred example of the present invention, there is provided a data communications system comprising a receiver25having: a data path35for receiving a data input signal from a communication channel30, the data path35including a VGA95for amplifying the data signal and an AGC for controlling the gain of the VGA95; a signal detector50having a VGA70for amplifying the data signal and a comparator65for comparing the data signal with threshold value to determine the validity of the data signal; an up channel driver45or wrap path; wherein a signal source of known amplitude is employed, via the up channel driver45or wrap path, to provide an known input to the AGC in the data path such that a reference gain value for the VGA70of the signal detector50can be determined. Such reference gain information may also be employed to calibrate other circuits within the receiver25. The calibration information from the AGC may be used directly with the VGA70of the signal detector50or used for another circuit having a gain which is known relative to the VGA95of the data path35. In a preferred example of the present invention, data receipt is interleaved with periodic testing of the validity of data signal. This allows the sharing of circuit function, specifically a VGA, between the data path35and the signal detector50.

In the embodiments of the present invention hereinbefore described, gain information from the AGC in the data path25is employed to control the gain of the VGA70in the signal detector50. In other embodiments of the present invention, the gain information from the AGC may be employed to control the threshold of the comparator65in the signal detector50. In such embodiments, a digital to analogue converter (DAC) may be employed to convert the gain information in digital form to an analogue threshold level at the comparator65.

In the embodiments of the present invention hereinbefore described, the gains of VGA70and VGA95are digitally controlled. However, it will be appreciated that, in other embodiments of the present invention, the gain control inputs of VGA70and VGA95may be instead responsive to analogue control signals. It will be recognized that many functions within embodiments of the present invention may be implemented with analogue electronic circuitry. For example, in some such embodiments, the registers80and100may be implemented by sample and hold circuits. Analogue implementations of other features of the present invention will be apparent to those skilled in the art. It will be appreciated by such individuals that many variations of the preferred embodiments herein before described are possible without departing from the scope of the present invention.