Electrically alterable nonvolatile memory

An electrically erasable nonvolatile memory system comprises nonvolatile memory cells each including one transistor. A plurality of row lines are connected commonly to the control gates of the memory cells arranged in a row direction, respectively. For applying a positive voltage to a selected row line upon data-write or data-read and a negative voltage to a selected row line upon data-erase, a plurality of control circuits are provided. Each control circuit is coupled with a corresponding one of the row lines, with one of outputs of a row decoder selecting a row line and with a control terminal which is commonly coupled to the control circuits. Each control circuit is so constructed as to supply to a corresponding row line with a voltage having a prescribed level corresponding to a voltage level applied to the control terminal.

BACKGROUND OF THE INVENTION 
The invention relates to a nonvolatile memory system allowing data to 
electrically be written or erased. 
An erasable and programmable read only memory (EP-ROM) system, known to 
those skilled in the art, employs a floating gate type FET (field effect 
transistor) or an MNOS (metal nitride oxide semiconductor) type FET for 
its memory cell. It is also known that in a memory system using memory 
cells of the floating gate type, there are two known erasing methods to 
erase the contents of the memory cells; one for illuminating the contents 
of memory cells by ultraviolet rays and the other for electrically erasing 
the contents of the memory cells. The ultraviolet erasing method is 
advantageous in that a smaller number of transistors constituting memory 
cells are needed, but is disadvantageous in that a longer time is taken 
for erasing the memory contents. In this respect, it is desirable to 
employ the electrical erasing method. 
A conventional electrically alterable nonvolatile memory system employing 
the electrical erasing method will briefly be described with reference to 
FIG. 1. As shown, unit memory cells Iao, Ia1, . . . and Ibo, Ib1, . . . 
are arranged in columns of a matrix array while unit memory cells Iao, 
Ibo, . . . , and Ia1, Ib1, . . . are arranged in rows. Each memory cell, 
for example, Iao, is comprised of a series circuit including an MOS-FET 2 
and a floating gate type FET 3. For writing data into the memory cell, a 
voltage applied to the control gate of the floating type FET 3 must be 
opposite in polarity to that of a voltage applied to the same for erasing 
data stored in the memory cell. To this end, the control gate FET 3 must 
electrically be insulated from the substrate in a memory system design. In 
the circuit construction shown, the control gate of FET 3 can not be used 
when the memory system is decoded. To avoid this, the FET 2 is connected 
in series to the FET 3. In the memory cell selection, the memory cell Iao 
in this example is selected by driving a column line 4a to which a MOS FET 
5a is connected in series; and by driving a row line 6ao connected to the 
gate of the MOS FET 2. The control gate of the floating gate type FET 3 is 
connected to a control line 6b. 
FIG. 2 shows a cross sectional view of a unit memory cell. As mentioned 
above, the ultraviolet ray erasing method needs only one transistor for 
the unit memory cell while the electrical erasing method needs a couple of 
transistors 2 and 3, as shown in FIGS. 1 and 2. 
Accordingly, an object of the invention is to provide an electrically 
alterable nonvolatile memory system of a type in which the contents of 
memory cells are electrically erasable and each memory cell is comprised 
of a single transistor. 
SUMMARY OF THE INVENTION 
According to the invention, there is provided an electrically alterable 
nonvolatile memory system comprising: a plurality of nonvolatile memory 
cells arranged in a matrix array and each including one transistor; a 
plurality of column lines coupled with one of the ends of the source-drain 
paths of the memory cells arranged in a column direction; a voltage supply 
source coupled commonly with the other ends of the source-drain paths; a 
column decoder coupled with the column lines for selecting a column line; 
a plurality of row lines each connected commonly to the control gates of 
the memory cells arranged in a row direction; a row decoder coupled with 
the row lines for selecting a row line; a control terminal coupled 
commonly to the respective row lines for applying a voltage with a 
different level corresponding to data-read, data-write or data-erase of at 
least one of the memory cells; and a plurality of control circuits each 
being coupled with a corresponding one of the row lines, with one of 
output terminals of the row decoder corresponding to the corresponding row 
line and with the control terminal, for applying to a corresponding row 
line with a voltage having a prescribed level corresponding to a voltage 
level applied to the control terminal. With such a construction, the 
data-write, data-read or data-erase is made for at least one of the memory 
cells by controlling at least the voltage applied to the control terminal. 
The nonvolatile memory system according to the invention has memory cells 
each including one transistor so that the number of transistors used in 
the memory system is small. Further, data in the memory cells are 
electrically erasable, so that the erasing time of the memory data can be 
shortened. 
Other objects and features of the invention will be apparent from the 
following description taken in connection with the accompanying drawings, 
in which:

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
For ease of understanding the invention, the writing, reading and erasure 
of data will first be described by using a memory cell having a floating 
gate type FET. A term "data-write" in the specification means that a 
positive voltage is applied to the control gate of the FET in the memory 
cell and the drain thereof to cause current to flow through the channel 
and to cause impact ionization in the vicinity of the drain, thereby to 
inject electrons into the floating gate of the FET. A term "data-read" 
means to detect electrons injected into the floating gate. A term 
"data-erase" means that a negative voltage is applied to the control gate 
of the FET to cause a breakdown between the drain or source and the 
substrate of the FET to inject holes into the floating gate thereby to 
neutralize the electrons already injected or written thereinto. 
An embodiment of an electrically alterable non-volatile memory will be 
described with reference to FIG. 3. In FIG. 3, floating gate type FETs 
(referred to as FGTr) a.sub.o b.sub.o, . . . a.sub.n b.sub.o ; a.sub.o 
b.sub.1, . . . a.sub.n b.sub.1 ; a.sub.o b.sub.m, a.sub.n b.sub.m 
constitute memory cells, respectively. FGTr's a.sub.o b.sub.o, . . . 
a.sub.n b.sub.o have source-drain paths connected between one column line 
b.sub.o and a power supply source Vss (normally ground potential). FGTr's 
a.sub.o b.sub.1, . . . a.sub.n b.sub.1 have source-drain pathsconnected 
between a column line b.sub.1 and the power supply source Vss. FGTr's 
a.sub.o b.sub.m, . . . a.sub.n b.sub.m source-drain paths connected 
between a column line b.sub.m and the power supply source Vss. The 
respective column lines b.sub.o to b.sub.m are commonly connected to each 
other through transistors 7.sub.o to 7.sub.m. A write control circuit 8, 
an erase control circuit 9, and a couple of transistors 10a and 10b are 
connected in a cluster to a common connection point of column lines bo-bm. 
The connection point between transistors 10a and 10b is connected to the 
input of a sense amplifier 11 which is further connected at the output to 
an output buffer 12 for producing a read output. FGTr's a.sub.o b.sub.o, . 
. . a.sub.o b.sub.m are connected at the gates to a row line a.sub.o ; 
FGTr's a.sub.1 b.sub.o, . . . a.sub.1 b.sub.m are connected at the gates 
to a row line a.sub.1 ; FGTr's a.sub.n b.sub.o, . . . a.sub.n b.sub.m at 
the gates to a row line a.sub.n. The row lines a.sub.o to a.sub.n are 
connected through terminals 15.sub.o to 15.sub.n to control circuits 
16.sub.o to 16.sub.n, respectively. The terminals 15.sub.o to 15.sub.n are 
connected through corresponding resistors 17.sub.0 to 17.sub.n to a 
control terminal 18. A row decoder 19, which receives at the inputs row 
addresses A.sub.o to Ai.sub.n, produces outputs which in turn are applied 
through terminals 20.sub.o, . . . 20.sub.n to the control circuits 
16.sub.o, . . . 16.sub.n. A column decoder 21, which receives at the 
inputs column addresses B.sub.o, . . . Bj, produces output signals for 
application to the gates of the transistors 7.sub.o, . . . 7.sub.m. 
A structure of one memory cell, for example a.sub.o b.sub.o, is illustrated 
in FIG. 4A. As shown, a drain D (N.sup.+) formed on the surface portion of 
a substrate of P type is connected to a column line b.sub.o. A source S 
(N.sup.+) similarly formed is connected to the power supply source Vss. A 
control gate CG, disposed above the floating gate FG, is connected to the 
row line a.sub.o. 
The structural and schematic illustrations of one control circuit, for 
example 16.sub.o shown in FIG. 3 are shown in FIGS. 5A to 5C. In those 
figures, FIG. 5A shows a plan view, FIG. 5B shows a cross sectional view 
taken along line 5B--5B in FIG. 5A, and FIG. 5C shows an equivalent 
circuit of the structure shown in FIGS. 5A and 5B. As shown, a surface 
area 26 of N type is formed on the same substrate 25 as that of the memory 
cells. Another surface area 27 of P conductivity type is formed on a part 
of the surface area 26. In this structure, a diode between the terminals 
15.sub.o and 20.sub.o is designated by reference numeral 28 and a diode 
between the terminal 20.sub.o and the substrate 25 is designated by 
numeral 29. 
The operation of the memory system shown in FIG. 3 will be described. In 
writing data into a memory cell a.sub.o b.sub.o, for example, the column 
decoder 21 applies a selection signal, for example, +25 V, to the gate of 
the transistor 7.sub.o to render the transistor 7.sub.o conductive thereby 
to select the column line b.sub.o. At this time, a write voltage, for 
example, +25 V, is applied to the control terminal 18. Further, the row 
decoder 19 applies a selection signal of +25 V, for example, to the 
terminal 20.sub.o. In this case, the selection signal at the terminal 
20.sub.o is logical `1`. Since the potential +25 V is applied to the 
terminals 20.sub.o and 15.sub.o, the diode 28 is rendered OFF state, as 
seen from FIG. 5C. Accordingly, the voltage +25 V applied to the terminal 
18 is applied to the row line a.sub.o by way of the resistor 17.sub.o so 
that the row line a.sub.o is kept at +25 V. Because of the turn-on of the 
transistor 7.sub.o, the write circuit 8 applies +20 V through the column 
line b.sub.o to the drain D of the cell a.sub.o b.sub.o. Accordingly, 
impact ionization takes place between the drain and source of the cell 
a.sub.o b.sub.o and electrons are injected into the floating gate FG. At 
this point, the write operation is completed. With respect to the memory 
cells a.sub.o b.sub.1 , . . . a.sub.o b.sub.m, the write voltage of +25 V 
from the control terminal 18 is applied to the control gates of those 
cells. However, since the transistor 7.sub.1 to 7.sub.m are in OFF state, 
no write operation is performed into those transistors. If the voltage of 
the terminal 20.sub.o is logical `0`, a forward bias is applied to the 
diode 28, so that discharge current flows through the control terminal 18, 
the resistor 17.sub.o, the terminal 15.sub.o and the row decoder 19 and 
the terminal 15.sub.o has a potential of logical `0` (approximately 0 V). 
Therefore, nothing is written into the memory cell a.sub.o b.sub.o, even 
if the column line b.sub.o is selected. In other words, when the memory 
cell a.sub.o b.sub.o is selected, the terminals 20.sub.1, . . . 20.sub.n 
are at logical `0` and hence nothing is written into the memory cells 
a.sub.1 b.sub.o, . . . a.sub.n b.sub.o, even if the column line b.sub.o is 
selected. 
In reading out data stored in the memory cell a.sub.o b.sub.o, a read 
signal of +5 V, for example, is applied to the control terminal 18. A 
selection signal `1` of, for example, +5 V, for a row line a.sub.o is 
applied to the terminal 20.sub.o. Further, a selection signal for a column 
line b.sub.o is applied to the gate of the transistor 7.sub.o. In this 
case, the diodes 28 and 29 in FIG. 5C are both biased reversely. 
Accordingly, the row line a.sub.o connected to the control terminal 18 is 
kept at +5 V while the remaining row lines a.sub.1 to a.sub.n are at 0 V. 
The memory cell having electrons injected in the floating gate, that is, 
having data written, does not conduct even when +5 V is applied to the 
control gate CG. However, the memory cell having no data written conducts 
in such a case. Accordingly, data stored in the memory cell a.sub.o 
b.sub.o is detected by the sense amplifier 11 as a change of the potential 
on the column line b.sub.o, and then is read out through the output buffer 
12. 
In erasing the memory cell a.sub.o b.sub.o, for example, having data 
stored, -40 V, for example, is applied to the control terminal 18 while 
the voltage of the power supply source Vss is set to +40 V. At this time, 
since the diode 28 (FIG. 5C) is inversely biased, the -40 V applied to the 
terminal 18 is applied to the control gates of all the memory cells. By 
setting the power supply source Vss to +40 V, that is, applying +40 V to 
the source of the transistor shown in FIG. 4A, break down takes place 
under the floating gates FG of all the memory cells to produce pairs of 
electrons and holes. As a result, holes are injected into the floating 
gate FG of all the cells. At this point, the erasing operation ends. 
FIG. 6 shows voltages applied to the terminals 18 and 20.sub.o (including 
20.sub.1, . . . 20.sub.n) and the terminal 15.sub.o (including 15.sub.1, . 
. . 15.sub.n) and the voltage of the power supply source Vss in the read, 
write, and erase cycles in FIG. 3. In the read and write cycles, the 
selected cell and the non-selected cell are separately illustrated. 
A manufacturing method of the control circuit (diode circuit) shown in FIG. 
5B will be described with reference to FIGS. 7A to 7C, and FIGS. 8A and 
8B. Approximately 5.times.10.sup.12 cm.sup.-2 of phosphor are implanted 
into the P type substrate with an impurity concentration of N.sub.A 
(acceptor concentration)=2.times.10.sup.15 cm.sup.-3, with energy of 100 
KeV (FIG. 7A) by using an implantation technique. Then, it is heated for 
about 10 hours in an atmosphere at 1200.degree. C. thereby to form an N 
type diffusion layer (N well) with about 5.mu. in depth and its surface 
concentration 1.times.10.sup.16 cm.sup.-3 (FIG. 7B). Further, through PEP 
(photo engraving process) and boron diffusion (or boron implantation) a 
P.sup.+ diffusion layer is formed on a desired surface portion of the N 
well (FIG. 7C). The just-mentioned manufacturing method is applied to the 
case where the memory cell shown in FIG. 3 is of N channel type. In the 
case of the P-channel type, boron is implanted onto an N type substrate to 
form a P well. Then, phosphor is diffused or implanted onto a part of the 
surface of the P well. Additionally, the following method is also usable. 
An N type epitaxial layer with the impurity concentration approximate to 
that of a substrate is formed on the P type substrate with the impurity 
concentration of N.sub.A =2.times.10.sup.15 cm.sup.-3, for example. See 
FIG. 8A. On the wafer thus formed, an SiO.sub.2 layer is formed by thermal 
oxidation or chemical vapor deposition method. Then, the PEP and etching 
techniques are applied to the layers to leave a necessary portion of the 
epitaxial layer. Then, by the thermal oxidation and the PEP techniques, a 
P.sup.+ layer is formed on a part of the epitaxial layer surface (FIG. 
8B). In the case of the N type substrate, a P type epitaxial layer is 
formed and then an N.sup.+ layer is formed on a part of the epitaxial 
layer. For either of the methods used, the respective terminals of the 
control circuit are connected to an integration circuit including the 
memory cells shown in FIG. 3 by means of Al electrodes. 
FIG. 9 shows a connection between the circuit of the row decoder 19 and the 
control circuits 16.sub.o to 16.sub.n. For denotation of the respective 
parts, reference symbols used in FIG, 3 are used for simplicity of 
illustration. A symbol TRd designates a depression type MOS and TRe 
designates an enhancement type MOS. 
As described above referring to FIG. 4A and FIG. 6, in the erase cycle, +40 
V (Vss) is applied to the source of the memory cell to cause a breakdown 
in the memory cell illustrated in FIG. 4A. However, the breakdown is also 
caused in a manner that P.sup.+ regions are provided adjacent the drain 
and source respectively as shown in FIG. 4B and a voltage (Vss) lower than 
+40 V may be applied to the source of the memory cell. FIG. 10 shows, with 
a breakdown characteristic curve, how the breakdown voltage changes 
depending on a relation between a voltage applied to the drain of the 
memory cell of FGTr and a voltage applied to the control gate CG. In the 
memory system shown in FIG. 3, it is frequently desired not only to erase 
all the memory cells simultaneously but also to erase all the memory cells 
connected to a selected column line or connected to a selected row line. 
In this case, use of the memory cell with the structure shown in FIG. 4B 
may attain its object. 
Erasing of only the data in the memory cells coupled with a single column 
line will be described. Assuming now that the structure of the memory cell 
used is as shown in FIG. 4B, the power supply source Vss is always at 
ground potential, and only the data of the memory cells coupled with the 
column line b.sub.o are erased. In FIG. 3, the transistor 7.sub.o is made 
selectively conductive by the column decoder 21. Then, -40 V is applied to 
the control gates of the memory cells a.sub.o b.sub.o, . . . a.sub.n 
b.sub.o by applying -40 V to the control terminal 18 and +25 V is applied 
to the drains of the cells. Upon the application of the voltage, a 
breakdown takes place in the memory cells a.sub.o b.sub.o, . . . a.sub.n 
b.sub.o, so that pairs of electrons and holes are produced in the memory 
cells a.sub.o b.sub.o, . . . a.sub.n b.sub.o, thereby to inject holes into 
the floating gates FG of the cells a.sub.o b.sub.o. Accordingly, the data 
stored in the memory cells a.sub.o b.sub.o, . . . a.sub.n b.sub.o are 
erased. The memory cells belonging to the column lines b.sub.1 to b.sub.m 
is rendered nonconductive. Accordingly, no breakdown occurs in the memory 
cells and therefore the contents in the memory cells belonging to column 
lines b.sub.1 to b.sub.m are not erased. 
The erasing of the contents of only the memory cells belonging to one row 
line will be described with reference to FIG. 11. As shown in FIG. 11, the 
gates of the memory cells a.sub.o b.sub.o, . . . a.sub.o b.sub.m belonging 
to a row line a.sub.o, for example, are connected to the terminal 15.sub.o 
and the sources of the memory cells are connected to the power supply 
source Vss through a transistor 22.sub.o. Between the output terminal Q of 
a unit row decoder 19A and the common sources of the cells a.sub.o b.sub.o 
to a.sub.o b.sub.m is connected an erase circuit 9A. The drains of the 
memory cells a.sub.o b.sub.o, . . . a.sub.n b.sub.o belonging to the 
column line b.sub.o, for example, are commonly connected to the column 
line b.sub.o which is further connected through the transistor 7.sub.o to 
the sense amplifier 11 (see FIG. 3). The erase circuit 9A includes a 
depletion type transistor 35a, and enhancement type transistors 35b to 
35d. The gate of the transistor 35b is connected to the output terminal Q 
of the unit row decoder 19A and the drain of the transistor 35d is 
connected to the sources of the memory cells a.sub.o b.sub.o, . . . 
a.sub.o b.sub.m commonly connected to the row line a.sub.o. In FIG. 11, 
assume that all the memory cells belonging to the row line a.sub.o are 
selectively erased while the memory cells belonging to the remaining row 
lines are not erased. On this assumption, the output terminal Q of the 
unit row decoder 19A coupled with the row line a.sub.o is logical `1`. 
Further, the erase signal ER of the erase circuit 9A is logical `1`. When 
ER=`1`, a node Ro between the transistors 35a and 35b is logical `0`, and 
the transistor 35d is turned off. At this time, the potential of the power 
supply source Vss is increased to such an extent, for example, +25 V, that 
the breakdown takes place in the memory cells a.sub.o b.sub.o, . . . 
a.sub.o b.sub.m. At this time, -40 V has already been applied through the 
control terminal 18 to the gates of the memory cells a.sub.o b.sub.o, . . 
. a.sub.o b.sub.m belonging to the row line a.sub.o. Accordingly, a 
breakdown takes place in the source side of the memory cells a.sub.o 
b.sub.o, . . . a.sub.o b.sub.m, thus resulting in erasure of data. With 
respect to the row line not selected, for example, a.sub.m since the 
output point Q of another unit row decoder 19A is `0`, the transistor 35b 
is turned off and the output Ro becomes `1`. Accordingly, the transistor 
35d is turned on and the drain potential of the transistor 35d becomes 
approximately `0`. Therefore, a breakdown does not take place in the 
memory cells a.sub.n b.sub.o, . . . a.sub.n b.sub.m so that the data 
stored therein are not erased. 
FIG. 12A shows another embodiment of the non-volatile memory system 
according to the invention. This embodiment can simultaneously erase the 
contents of all the memory cells of the memory system, of the memory cells 
belonging to only one row line, of the memory cells belonging to one 
column line, or of only one memory cell selected. Accordingly, this 
embodiment can rewrite a part or all of the contents of the memory cells 
of the memory system. 
In FIG. 12A, a unit address decoder 19A includes transistors 36a to 36e, a 
write control circuit 8A includes transistors 36f to 36j, and a control 
circuit 16.sub.o includes transistors 36k and 36l. The same thing is true 
for a unit address decoder, a write control circuit, and a control circuit 
belonging to a row line a.sub.n. Of those transistors, the transistors 36b 
and 36g are of the depression type and the remaining ones are of the 
enhancement type. In FIG. 12A, a common connection point among the 
transistors 36a to 36d is designated by a character a; a connection point 
between the transistors 36c and 36d by a character b; a connection point 
between the transistors 36f and 36g by a character c; a connection point 
between the transistors 36i and 36j by d; a connection point between the 
transistor 36k and a resistor 17.sub.o by e. The remaining part of the 
circuit is the same as that of the circuit shown in FIG. 3, with some 
exception. For simplicity of explanation, like reference symbols are used 
to designate like portions in FIG. 3. The source of the transistor 36k is 
connected to the N-well layer 37 (FIG. 12B). A signal AE, which becomes 
`1` at the time of simultaneously erasing all the memory cells or the 
memory cells belonging to one column line, is applied to the gate of the 
transistor 36e. Further, an erase signal ER, which becomes `1` only at the 
time of the erase, is applied to the gate of the transistor 36h. 
The construction of the control circuit 16.sub.o shown in FIG. 12A is 
illustrated in FIG. 12B and the connection of it to other related circuits 
is illustrated in detail in the drawing, thus omitting the explanation of 
its details. For a better understanding of the circuit shown in FIG. 12A, 
an equivalent circuit 16.sub.o (16.sub.1, . . . 16.sub.n) in the read and 
write (program) operations will be described with reference to FIG. 12C. 
When a positive potential (+5 V in the read operation and +25 V in the 
write operation) is applied to the control terminal 18, P-channel 
transistors 36k and 36l are non-conductive, resulting in the presence of a 
diode D1 formed by a P.sup.+ region 36ld and an N-well 37. This is 
equivalent to the presence of diode D1 between an output point d between 
n-channel transistors 36i and 36j and a terminal 15.sub.o. Accordingly, 
the potential at the output point c between the transistors 36f and 36g in 
the circuit 8A becomes "0" to turn off the transistor 36i. At this time, 
the terminal d is charged by a write voltage +25 V applied to the control 
terminal 18 through the resistor 17.sub.o and the diode D1 and the 
terminal d has a potential approximate to +25 V. Upon this, the transistor 
36j is also turned off. Accordingly, the terminal 15.sub.o and the row 
line a.sub.o become +25 V. The case to select the row line a.sub.o is as 
mentioned above. In the case where the row line a.sub.o is not selected, 
the terminal c in the write control circuit 8A becomes logical `1` in 
level. Accordingly, the transistor 36i is turned on and the charge on the 
terminal 15.sub.o and the row line a.sub.o are discharged through the 
diode D1, and the terminal 15.sub.o and the row line a.sub.o become 0 V 
in potential. 
Explanation will be given of a case where data is written into the memory 
cell a.sub.o b.sub.o shown in FIG. 12A. In this case, +25 V is first 
applied to the terminals 18. Since the point d is connected to the N-well 
37, logical level `0` or `1` of the N-well 37 is determined depending upon 
the ON or OFF state of the transistor 36i, that is to say, logical level 
`0` or `1` at the terminal d. In accordance with logical level state `0` 
or `1` of the N-well 37, 0 V or 25 V may be applied to the row line 
a.sub.o. Since the example under discussion is the data write operation, 
ER=`0` and AE=`0`. Accordingly, when the row line a.sub.o is not selected, 
that is to say, when the terminal a is `0`, c (terminal)=`1` and d 
(terminal)=`0`, and a.sub.o (row line)=`0`. Accordingly, at this time, no 
data is written into the memory cell a.sub.o b.sub.o. When the row line 
a.sub.o is selected and the output point a in the unit row decoder 19A 
becomes `1`, c (terminal)=`0`, the transistor 36i is turned off and +25 V 
applied to the control terminals 18 appears at the terminal d. Therefore, 
the row line a.sub.o becomes +25 V. At this time, the column line b.sub.o 
is selected by the column decoder 21 and a write voltage +25 V is applied 
from the write circuit 8 to the column line b.sub.o. Accordingly, 
electrons are injected into the floating gate FG of the memory cell 
a.sub.o b.sub.o to perform the write operation. A transistor 10a of which 
the gate is supplied with read signal, write signal, and erase signal, is 
connected between the common connection line among the drains of the 
transistors 7.sub.o, . . . 7.sub.m, and the sense amplifier 11. In the 
write operation, the transistor 10a is turned off. 
The data-read will be described below. In this case, a logical level state 
`1` or `0` of a memory cell is detected by detecting ON or OFF state of 
the memory cell. A memory cell to which electrons are injected, that is to 
say, to which data is written, has a high threshold voltage Vth. 
Accordingly, even if +5 V is applied to the control gate CG of the memory 
cell, it is not turned on. In the case of a memory cell having no data 
written or no electrons injected, it is turned on by the application of +5 
V. At the time of data-read, the signal AE (see transistor 36e) and the 
signal ER (see transistor 36h) are `0` and the signal RWE (see transistor 
10a) is `1`. Accordingly, the transistor 10a is turned on to permit data 
appearing on a column line to reach the sense amplifier 11. In this 
data-read operation, +5 V is applied to the control terminal 18. 
When the row line a.sub.o is selected, a (terminal)=`1`, c (terminal)=`0` 
and d (terminal)=`1`. At this time, since the terminal d is connected to 
the N-well 37, a.sub.o (row line)=`1`. If the row line a.sub.o is not 
selected, a (terminal)=`0`, c (terminal)=`1` and d (terminal)=`0`. 
Accordingly, a.sub.o (row line)=`0`. The row line a.sub.o becomes `1` in 
logical level, and the column line b.sub.o is selected by the column 
decoder 21. At this time, if electrons are injected into the floating gate 
of the memory cell a.sub.o b.sub.o, the memory cell a.sub.o b.sub.o is 
turned off, so that the column line b.sub.o is charged to be `1` through 
the transistor 10b. The logical level `1` is derived through the sense 
amplifier 11 and the output buffer 12. If electrons are not injected (data 
is not written) into the floating gate FG of the memory cell a.sub.o 
b.sub.o, the memory cell a.sub.o b.sub.o is turned on, and the charge on 
the column line b.sub.o is discharged through the memory cell a.sub.o 
b.sub.o so that the column line b.sub.o becomes logical `0` and the data 
of the memory cell a.sub.o b.sub.o is derived from the output buffer 12. 
The data-erase will be described. The data-erase means that a breakdown is 
caused in the source or the drain region of the memory cell, holes of the 
pairs of electrons and holes are injected into the floating gate of the 
cell by applying a negative voltage to the control gate of the cell, and 
the electrons already injected into the floating gate at the time of 
data-write are neutralized. Such an erase is made by applying an erase 
voltage -40 V, for example, to the control terminals 18 and by selecting a 
column line and a row line. 
The explanation to follow is for a case where only the data of a single 
memory cell selected, for example, a.sub.o b.sub.o is erased. In this 
case, -40 V is applied to the control terminal 18 on the condition that 
Vss=0 V, AE=`0`, ER=`1`, RWE=`0` (see transistors 36e, 36h and 10a). Then, 
the row decoder 19 (see FIG. 3) selects the row line a.sub.o to set the 
row line a.sub.o to -40 V. At the same time, the column decoder 21 selects 
the column line b.sub.o to apply +25 V to the column line b.sub.o. Under 
this condition, the row lines other than a.sub.o are kept at 0 V and the 
column lines other than b.sub.o also are kept at 0 V. As shown in FIG. 10, 
the drain voltages for causing a breakdown in a memory cell are allowed to 
be lower as the control gate voltage negatively increases. Accordingly, a 
breakdown takes place only in the memory cell a.sub.o b.sub.o of which the 
control gate voltage is -40 V and the drain voltage is +25 V. Thus only 
the data of the cell a.sub.o b.sub.o is erased. When -40 V is applied to 
the row line a.sub.o, a (terminal)=5 V, b (terminal)=0 V, and the terminal 
ER (see transistor 36h) is `1`. Accordingly, c (terminal)=`0`, and d 
(terminal)=`1`, and +5 V appears at the terminal d. For this, the N-well 
37 is kept at +5 V. Because b (terminal)=0 V, the transistor 36k of 
P-channel type is turned on and +5 V appears at the terminal e. 
Accordingly, the transistor 36l is turned off and -40 V is applied to the 
row line a.sub.o. If the row line a.sub.o is not selected, a (terminal)=0 
V and thus the b (terminal)=+5 V, turning off the transistor 36k. As a 
result, the terminal e becomes -40 V in potential. Therefore, the 
transistor 36l is turned on and the row line a.sub.o becomes 0 V in 
potential. As described above, it is evident that voltages, for example, 
-40 V or +25 V, may selectively be applied to the row lines and the column 
lines. Therefore, data in an arbitrary memory cell is erasable. 
An explanation will be given of how the data stored in all the memory cells 
belonging to a single row line are erased. As described above, -40 V or 0 
V may selectively be applied to the row lines. A row line to which the 
memory cells desired to be erased are connected is kept at -40 V and the 
remaining row lines are kept at 0 V. Under this condition, if address 
signals to turn on all the transistors 7.sub.o to 7.sub.m are applied to 
the column decoder 21, +25 V is applied to the column lines b.sub.o to 
b.sub.m. Upon the application of +25 V, a breakdown takes place in only 
the memory cells connected to the row line to which -40 V is selectively 
applied. As a result, only the contents of the memory cells connected to a 
single row line are erased. Unlike the above-mentioned method, by setting 
the power supply source Vss to +25 V, the data of the memory cells 
belonging to a row line to which -40 V is selectively applied may be 
erased. 
Explanation will be given referring to FIG. 12A of how the data of all the 
memory cells connected to a single column line are erased. In this erase 
operation, the signal AE (transistor 36e) and the signal ER (transistor 
36h) are rendered logical `1`. At this instance, c (terminal)=0 V, d 
(terminal)=+5 V, b (terminal)=0 V, e (terminal)=+5 V, and a.sub.o (row 
line)=-40 V. At this time, -40 V of course is applied to the control 
terminal 18. Under this condition, if the column line b.sub.o is selected 
by the column decoder 21, and +25 V is applied to only the column line 
b.sub.o, a breakdown takes place in only the memory cells a.sub.o b.sub.o 
to a.sub.n b.sub.o connected to the column line b.sub.o, thereby to erase 
the data. 
Under a condition that -40 V is applied to all the row lines, when address 
signals to turn on all the transistors 7.sub.o to 7.sub.m are applied to 
the column decoder 11, all the memory cells of the memory system are 
simultaneously erased. Additionally, it is apparent that, when the row 
lines a.sub.o to a.sub.n are sustained at -40 V, if the power supply 
source Vss is set to +40 V, the data of all the memory cells are erased. 
In this case, the breakdown takes place in the source sides of the memory 
cells. 
FIG. 13 shows still another embodiment of the memory system according to 
the invention. In this embodiment, an erase circuit 9A to erase the data 
of only all the memory cells belonging to the row line a.sub.o is 
additionally provided in the circuit connected to the row line shown in 
FIG. 12A, for example, the row line a.sub.o. Accordingly, necessary 
portions alone are illustrated. The erase circuit 9A includes transistors 
39a to 39f connected as shown. The gate of the transistor 39b is connected 
to the gate of the transistor 36f and transistor 39f is connected between 
the source of the memory cell a.sub.o b.sub.o and the power supply source 
Vss. The signal ER (erase) is applied to the gate of the transistor 39c 
and the signal AE before described is supplied to the gate of the 
transistor 39d. The connection point between the transistors 39d and 39e 
is designated by f and the connection point between the source of the 
memory cell a.sub.o b.sub.o and the transistor 39f, is denoted as g. 
In FIG. 13, under a condition that AE (signal)=`0` and ER (signal)=`1`, the 
potential of the control terminals 18 is set to -40 V and the power supply 
source Vss is set to +40 V. Under this condition, one row line selected, 
for example, a.sub.o, may be set at -40 V, as mentioned above referring to 
FIG. 12A. When the row line a.sub.o is selected, the terminal a is `1` and 
the terminal f is `0`. Accordingly, the transistor 39e is turned off. 
Because of Vss=+40 V, +40 V is applied to the terminal g. Therefore, the 
breakdown takes place in all the memory cells a.sub.o b.sub.o, . . . 
a.sub.o b.sub.m connected to the row line a.sub.o. Accordingly, the data 
in those memory cells belonging to the row line a.sub.o are erased. When 
the row line a.sub.o is not selected, that is to say, the terminal a is 
`0`, the terminal f is equal to `1`, so that the transistor 39e is turned 
on and therefore the terminal g becomes 0 V in potential. As a 
consequence, the data of the memory cells a.sub.o b.sub.o, . . . a.sub.o 
b.sub.m are not erased. 
Examples of the write circuit 8 and erase circuit 9 shown in FIG. 12A are 
shown in FIG. 14. In FIG. 14, the erase circuit 19 is illustrated 
including transistors 40a to 40k connected as shown, and the write circuit 
8 is illustrated including transistors 40a to 40d, and 41a to 41e 
connected as shown. The write circuit 8 and the erase circuit 9 are 
mutually connected by a circuit including transistors 42a to 42d connected 
as shown. The connection point between the transistors 40a and 40b is 
denoted as m; the connection point between the transistors 40c and 40d as 
n; the connection point between the transistors 40e and 40f as o; the 
connection point between transistors 40h and 40i as p; and the connection 
point between the transistors 41a and 41b as q. Write data or erase data 
is applied to the gate of the transistor 40b and an erase voltage VE is 
applied to one end of the drain source path of the transistor 40k. A write 
voltage VW is applied to one end of the drain-source path of the 
transistor 41e. The other ends of the drain-source paths of the 
transistors 40k and 41e are connected to a terminal z. The gate of the 
transistor 42b is supplied with a write signal W. An inverting signal W of 
the write signal W is derived from the connection point between the 
transistors 42a and 42b. An erase signal E is applied to the gate of the 
transistor 42d. 
In reference to FIG. 14, a state that electrons are injected into the 
floating gate of a memory cell (FIG. 12A) is denoted as `0` and a state 
that no electron is injected thereinto is denoted as `1`. In reading out 
data, if electrons are injected into the floating gate of a memory cell 
selected, the memory cell is in OFF state, and the column line is charged 
to be `1`, as mentioned above relating to FIG. 12A. The sense amplifier 11 
(FIG. 12A) is provided to detect the `1` state and to produce an output 
`0`. Accordingly, it can read out a `0` state of a memory cell (a state 
that electrons are injected into the memory cell). When no electron is 
injected into a memory cell, the memory cell is turned on and charge on 
the column line is discharged so that the column line becomes a state of 
`0`. The sense amplifier 11 detects the `0` state to produce `1`. 
Accordingly, it can detect the `1` state of a memory cell (a state that no 
electron is injected into the memory cell). 
In the erase circuit 9 shown in FIG. 14, in order to erase the contents of 
a memory cell, that is, to return a `0` state (electrons are injected) to 
a `1` state (none of the electrons is injected), and the following 
settings are first made: VE=+30 V (transistor 40k), W (write signal)=`0` 
(transistor 42b), and E (erase signal)=`1` (transistor 42d). Then, `1` is 
inputted as erase data so that the voltage VE (+30 V) appears at the 
terminal P and the transistor 40k is turned on. Accordingly, VE-V.sub.TH 
(V.sub.TH is the threshold voltage of the transistor 40k) appears at the 
terminal z, and +25 V is applied to the column lines selected. As a 
result, the breakdown takes place in the memory cells connected to the 
column lines selected, so that the `0` state of the memory cells becomes 
the `1` state. At this point, the erasing operation is completed. 
Then, when `0` is inputted as erase data to the transistor 40b, the 
terminal p becomes `0` state and the transistor 40k is turned off. 
Therefore, the voltage VE is not supplied to the terminal g and the column 
lines. As a result, the logical states `1` and `0` of the memory cells 
connected to those column lines remains unchanged. In the above erasing 
operation, the terminal q becomes `0` in logical state and the transistor 
41e is turned off. Accordingly, the write circuit 8 is little affected. 
In writing data into the memory cells, or in programming the memory system, 
the following settings are first made: VW=+25 V (transistors 41e and 41a), 
W=`1` and E=`0`. Under this condition, when write data is `0` (transistor 
40b), the terminal q becomes +25 V (VW) and the transistor 41e is turned 
on. Accordingly, the terminal z has the potential VW-V.sub.TH (V.sub.TH 
is the threshold voltage of the transistor 41e), so that the selected 
column lines have potential approximate to 20 V. As a result, data-write 
is performed for the selected memory cells. In other words, the state of 
the selected memory cells becomes `0`. When the write data is `1` 
(transistor 40b), the potential of the terminal q becomes 0 V so that the 
transistor 41e is turned off. The result is that the write voltage VW is 
not applied to the column line, nothing is written into the memory cells 
belonging to the column line, and these memory cells are sustained at `1` 
state. 
FIG. 15 shows a set of waveforms of voltages at the respective portions 
when data in a memory cell or cells of the memory system according to the 
invention is erased. During period T1 the data in all the memory cells of 
the memory system are erased. During a period T2 only the contents of all 
the memory cells belonging to one column line selected are erased. During 
a period T3 only the data in the memory cells belonging to one row line 
selected are erased with 40 V of the power supply source Vss. During a 
period T4 only the data of all the memory cells belonging to one row line 
are erased with 0 V of Vss and 25 V applied to the column line. During a 
period T5 the data in one memory cell selected is erased. 
In the above mentioned embodiments, the `0` state of a memory cell 
represents a case where electrons are injected into the floating gate of a 
memory cell while the `1` state represents a case where no electron is 
injected thereinto. Those representations for the respective states are 
interchangeable to each other. Further, in the embodiment shown in FIG. 
14, the erase operation is made when the erase data is `1`, but the 
embodiment may be modified into one in which the erase operation is made 
when the erase data is `0`.