Semiconductor integrated circuit with leakage current suppressed

In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit, and more particularly, to a technique for suppressing a leakage current in a semiconductor integrated circuit. Japanese Patent Application No. 2006-277591 also relates to the semiconductor integrated circuit. The disclosure of this application is incorporated herein by reference.

2. Description of Related Art

A problem of increase in leakage current becomes important with advancement of a technique for miniaturization of a semiconductor device. The leakage current flowing unnecessarily occupies a larger portion of a total of power consumption of the semiconductor device. In order to suppress the increasing of this power consumption, various techniques are proposed in Japanese Laid Open Patent Application (JP-P2004-186666A).

FIG. 1is a circuit diagram showing a configuration of a semiconductor device100described in JP-P2004-186666A. The semiconductor device100is related to an MT-CMOS (Multi Threshold CMOS). Referring toFIG. 1, in the semiconductor device100, an N-channel transistor Q1with a high threshold voltage is arranged between a higher side power supply line Vdd and a pseudo higher side power supply line Vddv. A power source terminal of a load circuit101is connected to the pseudo higher side power supply line Vddv and includes N-channel transistors (Q4and Q5) with a low threshold voltage and P-channel transistors (Q2and Q3) with a low threshold voltage.

In this way, by controlling a signal PCNT supplied to a gate of the N-channel transistor Q1with a high threshold voltage, a leakage current of the load circuit101is reduced. In this technique, the load circuit101is provided in a specific area (for example, a functional block), and a power source for the load circuit101is supplied. As described above, the technique is known, in which a switch is arranged between the specific area and the power supply line to control the supply of the power when s supply of the power and blockage of the supply of the power to a certain specific area are switched.

In case of mixed existence of an area for which power supply can be blocked off (hereinafter, to be referred to as a blockade-possible area) and an area for which power is constantly supplied (hereinafter, to be referred to as an always-operating area), it is preferable that respective areas are laid out independently. However, since presently widespread semiconductor integrated circuit usually have complexities in configuration and operation, a layout of independent allocation of the blockade-possible area and the always-operating area is very difficult. For example, there is often a case that the constant operation area must be allocated in the blockade-possible area. In this case, the power supply line for the constant operation area is required to be achieved via an upper layer of the blockade-possible area. As a result, since the configuration of the semiconductor integrated circuit is complicated due to a multi-layer structure, so that manufacturing costs and working steps thereof will be increased.

SUMMARY

In a first embodiment of the present invention, a semiconductor integrated circuit includes a cell arrangement area provided on a semiconductor substrate to allow a plurality of basis cells to be arranged; a basic power supply line provided in an upper layer than the cell arrangement area to supply a power; a switch cell configured to control the power supply from the basis power supply line to an inside of the cell arrangement area; and an always operating cell arranged in the cell arrangement area adjacently to the switch cell, and configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

In a second embodiment of the present invention, a semiconductor integrated circuit includes a semiconductor substrate; a cell arrangement area provided on the semiconductor substrate to allow a plurality of basis cells to be arranged; a basic power supply line provided in an upper layer than the cell arrangement area; a switch cell configured to connect the basis power supply line and power supply line end portions of a plurality of basis cells arranged in the cell arrangement area; and an always operating cell arranged in the cell arrangement area adjacently to the switch cell. The switch cell blocks the power supply from the basis power supply line to the cell arrangement area in response to a control signal, and the always operating cell configured to receive the power from the switch cell without dependence on an operation of the switch cell.

According to the present invention, when a semiconductor integrated circuit having an always-operating areas and blockade-possible areas in a mixed state is configured, a semiconductor integrated circuit which can appropriately operate with preventing wires from being complicated can be provided.

In addition, increasing of manufacturing costs and work units thereof can be suppressed by preventing wires of the semiconductor integrated circuit from being complicated.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a semiconductor integrated circuit of the present invention will be described with reference to the attached drawings. In a present semiconductor integrated circuit, a circuit is formed by arranging a set of elements (hereinafter, to be referred to as a basic cell) in a specific area of a semiconductor substrate and by connecting these basic cells. Each of a plurality of the basic cells arranged on a cell arrangement area is independent and isolated from another basic cell.

FIG. 2is a block diagram showing a configuration of a semiconductor integrated circuit1according to an embodiment of the present invention. The semiconductor integrated circuit1includes switching control signal transfer cells4, signal transfer cells5, and switching cells6, and is configured of an always-operating area2and a blockade-possible area3. The always-operating area2is an area to which a power is always supplied while the semiconductor integrated circuit1is operating. The blockade-possible area3is an area that the supply of the power to the area and the blockade of the power supply to the area are switched while the semiconductor integrated circuit1is in operation.

The switching control signal transfer cell4transfers a control signal for controlling supply of power to the blockade-possible area3and blockade of the power supply. Each of the switching control signal transfer cells4is connected to a control signal transfer line7. The signal transfer cell5transfers a predetermined signal such as a data signal and an address signal to functional blocks provided in the semiconductor integrated circuit1. Each of the signal transfer cells5is connected to a signal transfer line8. The switching cell6is provided between a basic power supply line (not shown) for supplying a power and the blockade-possible area3. The switching cell6is connected to the switching control signal transfer cell4via the control signal transfer line7. The switching cell6operates in response to the control signal outputted from the switching control signal transfer cell4.

Referring toFIG. 2, the semiconductor integrated circuit1in the present embodiment may include a plurality of the blockade-possible areas3and a plurality of the always-operating areas2. For example, as shown inFIG. 2, the blockade-possible area3(hereinafter, to be referred to as a specific blockade-possible area3a) may be further provided in the blockade-possible area3of the semiconductor integrated circuit1. In addition, the always-operating area2(hereinafter, to be referred to as a specific always-operating area2a) may be further provided in the blockade-possible area3.

Referring toFIG. 2, to transfer a signal to a first signal transfer cell5in a specific always-operating area2a, the first signal transfer cell5in the always-operating area2aand a second signal transfer cell5in the always-operating area2are required to be connected each other. In this case, a high speed signal transfer can be realized by providing some signal transfer cells5between the first signal transfer cell5and the second signal transfer cell5. When the specific always-operating area2ais configured in the blockade-possible area3, the signal transfer cell5allowing a high speed signal transfer is also provided in the blockade-possible area3. When a signal is transferred via the signal transfer cell5provided in the blockade-possible area3e.g., a third signal transfer cell5, the third signal transfer cell5is required to be in operation even when the power supply to the blockade-possible area3is blocked off.

A configuration of the signal transfer cell5provided for the blockade-possible area3will be described below. In the present embodiment, even when the power supply to the blockade-possible area3is blocked off, the signal transfer cell5(or the switching control signal transfer cell4) must continuously operate, and the area of such a cell is not only an area9but also other areas. A circuit configuration described below also has a similar configuration in other areas providing the above-described signal transfer cell5.

FIG. 3is a circuit diagram exemplarily showing a configuration of the area9inFIG. 2. Referring toFIG. 3, the area9includes the signal transfer cell5, the switching cell6, and a blockade-possible area cell10. The blockade-possible area cell10is a cell for which the supply of power is blocked in response to an operation of the switching cell6. The blockade-possible area cell10includes inverters16and17, and they are connected in series. The signal transfer cell5includes inverter18and19, and they are connected in series. A signal to be supplied to a specific always-operating area2ais supplied to a second input signal terminal IN2of the signal transfer cell5, which is connected to an input of the inverter18. In addition, a second output signal terminal OUT2is connected to the signal transfer line8and transfers the signal supplied to the second input signal terminal IN2to the specific always-operating area2avia the signal transfer line8.

In addition, the area9includes a master power supply line11, a ground line12, a power supply line13in the blockade-possible area, and an uncontrolled power supply line14. The master power supply line11supplies a power outputted by a power supply unit (not shown) of the semiconductor integrated circuit1. The ground line12provides a ground potential.

As shown inFIG. 3, the switching cell6includes a switching transistor15. The switching transistor15controls the master power supply line11to be connected to or disconnected from the power supply line13in response to a control signal supplied to a gate electrode. When the switching transistor15is activated, the master power supply line11and the power supply line13are connected to each other and set to the same voltage. As mentioned above, in the present embodiment, the master power supply line11supplies a power supply voltage outputted from the power supply unit (not shown) of the semiconductor integrated circuit1. Accordingly, when the switching transistor15is activated, a circuit whose power supply terminal is connected to the power supply line13, i.e., the inverter16of the blockade-possible area cell10operates. Further, since the switching transistor15is inactivated, an operation of a circuit connected to the power supply line13stops. Based on this configuration, the switching cell6of the present embodiment controls power supply to the blockade-possible area3.

Referring toFIG. 3, the area9includes the uncontrolled power supply line14. The uncontrolled power supply line14is connected to the master power supply line11via a connection node14a. As shown inFIG. 3, one power supply terminal of the inverter18of the signal transfer cell5is connected to the uncontrolled power supply line14. Similarly, one power supply terminal of the inverter19is also connected to the uncontrolled power supply line14. Thus, the signal transfer cell5can transfer the signal supplied into the second input signal terminal IN2being independent of an operation of the switching transistor15.

The configuration of the above-mentioned signal transfer cell5, switching cell6, and blockade-possible area cell10will be described below in detail.FIG. 4a layout pattern showing a configuration of the signal transfer cell5of the present embodiment. In the present embodiment, the inverters18and19of the signal transfer cell5have the same configuration. Accordingly, in the description described below, the configuration of the inverter18will be described mainly. Referring toFIG. 4, the inverter18of the signal transfer cell5included a P-channel MOS transistor and an N-channel MOS transistor.

The P-channel MOS transistor of the inverter18is formed in an N well29on a semiconductor substrate. In the N well29, a diffusion layer23functioning as a source and a diffusion layer26functioning as a drain are formed. The diffusion layer23is connected to a power supply terminal portion21via a first contact22. The power supply terminal portion21is connected to the uncontrolled power supply line14. The diffusion layer26is connected to a gate electrode of the inverter19via a signal output terminal portion24. In addition, the N-channel MOS transistor of the inverter18includes a diffusion layer33functioning as a source and a diffusion layer35functioning as a drain. The diffusion layer33is connected to a ground supply terminal portion31via a third contact32, and the ground supply terminal portion31is connected to the ground line12. The diffusion layer35is connected to a gate electrode of the inverter19via a contact34.

As shown inFIG. 4, the signal transfer cell5of the present embodiment includes the uncontrolled power supply line14, which is electrically isolated from the blockade-possible area power supply line13. In addition, as shown inFIG. 4, when the signal transfer cell5is arranged, the uncontrolled power supply line14of the signal transfer cell5has a connection terminal14b, i.e., a protruding portion into the adjacent cell from a boundary with the adjacent cell.

FIG. 5is a layout pattern showing a configuration of the switching cell6. As described above, the switching cell6includes the switching transistor15. A case that the switching transistor15is a P-channel MOS transistor will be described below. Referring toFIG. 5, the switching transistor15of the switching cell6is formed in an N well in the substrate. The switching transistor15includes a diffusion layer36functioning as a drain, a diffusion layer37functioning as a source, and a gate electrode38. A control signal is supplied to the gate electrode38via the signal transfer line7.

As shown inFIG. 5, the uncontrolled power supply line14is included in the switching cell6. The uncontrolled power supply line14is connected to a power supply line via a power supply terminal portion39. The power supply terminal portion39is connected to a diffusion layer37via a contact40. Here, the master power supply line11(not shown) is formed in an upper layer than the uncontrolled power supply line14. The master power supply line11and the uncontrolled power supply line14are connected to each other via a connection contact41. The connection contact41connects the power supplied from the master power supply line11to the power supply terminal39. In addition, the power is supplied for the diffusion layer37via the contact40.

Referring toFIG. 5, the uncontrolled power supply line14includes a connection terminal14c. When the switching cell6is arranged, the connection terminal14cis an extending portion from the boundary with an adjacent cell into this cell and corresponds to the above-mentioned connection terminal14b.

When the switching transistor15is activated in response to the control signal supplied via the signal transfer line7, the blockade-possible area power supply line13has the same voltage as the voltage supplied from the power supply line14via the power contact40. When the switching transistor15is inactivated in response to the control signal, the power supplied to the blockade-possible area power supply line13is blocked.

FIG. 6is a layout pattern exemplarily showing a configuration of the blockade-possible area cell10. Referring toFIG. 6, the blockade-possible area cell10includes the inverters16and17. The inverter16operates in response to a power supplied between the blockade-possible area power supply line13and the ground line12. Similarly, the inverter17operates in response to the power supplied between the blockade-possible area power supply line13and the ground line12.

FIG. 7is a layout pattern exemplarily showing a layout when the signal transfer cell5and the switching cell6are arranged in adjacent to each other. Referring toFIG. 7, the connection terminal14bof the signal transfer cell5and the connection terminal14cof the switching cell6are connected to each other as a connection terminal14a. Thus, the uncontrolled power supply line14of the signal transfer cell5and the uncontrolled power supply line14of the switching cell6are connected to each other. For the uncontrolled power supply line14connected to the switching cell6, the power from the master power supply line11(not shown) is always supplied via the connection contact41.

FIG. 8is a layout pattern exemplarily showing a layout when the blockade-possible area cell10is arranged to be adjacent to the signal transfer cell5. When the blockade-possible area cell10is arranged thus, the blockade-possible area power supply line13of the blockade-possible area cell10is connected to the blockade-possible area power supply line13of the switching cell6via the signal transfer cell5. As described above, the signal transfer cell5of the present embodiment includes the blockade-possible area power supply line13independent from the uncontrolled power supply line14. When the signal transfer cell5includes the blockade-possible area power supply line13independently from the uncontrolled power supply line14, the blockade-possible area cell10adjacent to the signal transfer cell5can operate independently from the signal transfer cell5. That is to say, even when the signal transfer cell5always operates, the switching cell6can control the power supply to the blockade-possible area cell10by the switching transistor.

FIGS. 9A to 9Dare layout patterns exemplarily showing a manufacturing method of forming the signal transfer cell5of the present embodiment. Referring toFIGS. 9A to 9D, the signal transfer cell5of the present embodiment can be formed based on the blockade-possible area cell10without designing a cell of a new layout pattern from the beginning. When the signal transfer cell5of the present embodiment is formed, the layout of the blockade-possible area cell10is specified at first (FIG. 9A). Next, power supply terminals of P-channel MOS transistors in the inverters18and19of the blockade-possible area cell10are separated from the blockade-possible area power supply line13(FIG. 9B).

Then, the uncontrolled power supply line14connected to its power supply terminal is configured (FIG. 9C). Finally, when the signal formed cell5is arranged adjacently to the blockade-possible area cell10, the connection terminal14bprojecting into an adjacent cell is formed. When the adjacent cell includes the aforementioned connection terminal14c, it is preferred that the connection terminal14bis connected to the connection terminal14cto overlap it. In addition, as data of the signal transfer cell5, the data having no data of the connection terminal14cmay be stored. In this case, the connection terminal14cmay be laid out after finishing arrangements of the signal transfer cell5and the adjacent switching cell6, to connect the uncontrolled power supply line14to the switching cell6.

As described above, the signal transfer cell5of the present embodiment can be formed without designing a new cell. In addition, the switching cell6can supply the power to the signal transfer cell5, only by extending a line connected to the master power supply line11as the connection terminal14b. Accordingly, the semiconductor integrated circuit1of the present embodiment can make the always-operating area and the blockade-possible area adequately operate while preventing the configuration from being complicated.

Comparative Example

FIG. 10is a layout pattern exemplarily showing a configuration when a cell having the same configuration as that of the blockade-possible area cell10arranged in the blockade-possible area3acts as a signal transfer cell. The signal transfer cell105has the same configuration as that of the above-mentioned blockade-possible area cell10. The power is supplied to the signal transfer cell105from a power supply line121arranged in an upper layer. As shown inFIG. 10, the power supply line121is connected to an uncontrolled power supply line114formed in its lower layer via a contact122. The uncontrolled power supply line114is connected to the power supply line of the signal transfer cell105.

At this moment, a blockade-possible area power supply line113of a cell adjacent to the signal transfer cell105is required to be electrically isolated from the signal transfer cell105. In this case, to control the power supply to the cells other than the signal transfer cell105adequately, it is necessary to connect the blockade-possible area power supply lines113of the cells other than the signal transfer cell105. Here, when the semiconductor integrated circuit1is made smaller in size, it is sometimes difficult to arrange a line in the same layer as the blockade-possible area power supply line113while avoiding the signal transfer cell105. Therefore, as shown inFIG. 10, the blockade-possible area power supply lines113can be connected via connection contacts124by a connection power supply line123which is formed in an upper layer of the signal transfer cell105. However, the arrangement of cells and lines complicates the configuration of the semiconductor integrated circuit.

As described above, the semiconductor integrated circuit1of the present embodiment includes the signal transfer cell5having a different configuration from the blockade-possible area cell10in order to suppress complicating of design and increasing of work steps. The signal transfer cell5has the connection terminal14b, and is arranged adjacently to the switching cell6having the terminal connection14c. Thus, a signal transfer circuit5can be formed independently from an operation of the switching cell6without providing extra lines.

That is to say, the operation can be continued even when the signal transfer cell5is arranged in the blockade-possible area3and the power supplied to the blockade-possible area3is blocked. For this reason, in the semiconductor integrated circuit1of the present embodiment, a signal can be adequately transferred to an operating circuit by transferring the signal via the signal transfer cell5even when there is a circuit block whose operation is stopped to reduce power consumption. In addition, the semiconductor integrated circuit1can be operated adequately by forming the switching control signal transfer cell4for transferring a control signal for the switching cell6in the similar configuration to the signal transfer cell5.

The configuration of the present invention has been described by exemplarily showing the configuration in which the switching cell6is arranged between the master power supply line11and the blockade-possible area power supply line13. However, the present invention is not limited to this configuration. For example, the semiconductor integrated circuit1may include the switching cell6arranged between the ground line12and the ground supply terminal of the blockade-possible area cell10. In addition, even when the semiconductor integrated circuit1includes the switching cells6on the power supply side and the ground side, the above-mentioned effectiveness can be obtained.

A method of forming an always operating cell continuing to operate even when a power supply to a power supply blockade-possible area is blocked off, is achieved by specifying a basic cell, by specifying a power supply line of the basic cell and power supply electrode portions of transistors of the basic cell, by separating the power supply line and the power supply electrode portions while keeping a function of the power supply line in the power supply blockade-possible area, by connecting the separated power supply electrode portions to another power supply line, and by connecting a protruding portion of the basic cell to a power supply line of another cell.

Also, in a method of manufacturing a semiconductor integrated circuit having a power supply blockade-possible area in which power supply can be blocked off, an always operating cell is prepared from a basic cell. A switch cell is formed to have a transistor used to stop power supply to the power supply blockade-possible area. The always operating cell is arranged in the power supply blockade-possible area to operate without dependence on an operation of the switch cell.

The preparation of the always operating cell is achieved by specifying the basic cell to be arranged in the power supply blockade-possible area, by specifying a power supply line of the basic cell and an power supply electrode portion of the transistor of the basic cell, by separating the power supply line and the power supply electrode portion while keeping a function of the power supply line in the power supply blockade-possible area, by connecting the separated power supply electrode portion to another power supply line, and by connecting a protruding portion of the basic cell to a power supply line of another cell.

Although the present invention has been described above in connection with several embodiments thereof, it will be appreciated by those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.