Technologies for internal time syncrhonization

Technologies for internal time synchronization in a compute device are disclosed. A timestamp value from an always running timer in the compute device may be broadcast using a serial broadcast wire to other components of the compute device, such as a network interface card. The network interface card may keep a local always running timer that mirrors the always running timer and synchronized to the always running timer by monitoring the serial broadcast wire. The network interface card may take a snapshot of both a system timer on the network interface card and the local always running timer. The network interface card may oversample the local always running timer in order to capture a more precise snapshot of the local always running timer.

BACKGROUND

Time synchronization between components of a compute device is important for several applications. For example, it may be important to accurately determine the timing of sending or receiving packets that are sent or received over a network, such as in time sensitive network applications. However, the timing of the circuit that sends and receives network packets may not be directly synchronized with other components of the compute device.

The components of a compute device may be synchronized by sending messages between the various components. However, the messages may have an unknown amount of latency associated with them, leading to a relatively large uncertainty in the true timing associated with a particular message.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now toFIG. 1, an illustrative compute device100is configured to perform internal time synchronization. In use, an always running timer112of the compute device100is configured to maintain a counter indicative of a time. The always running timer112is connected to a serial broadcast wire118, which may be connected to one or more additional components of the compute device100such as a network interface card110. The illustrative always running timer112periodically samples the value of the counter and broadcasts a timestamp value based on the sampled value of the counter. Signals sent on the serial broadcast wire118may be sent using a clock that may be a relatively low frequency, such as 19.2 megahertz (MHz). The components which receive the broadcasted timestamp value, such as the network interface card110, may monitor the signal from the single-wire interface and maintain a local always running timer116that mirrors the always running timer used the sampled signal. The network interface card110may then capture a snapshot of both a system timer114on the network interface card110and the local always running timer116. The network interface card110may oversample the local always running timer116at a relatively high frequency clock rate, such as 200 MHz. Oversampling the local always running timer116will allow the network interface card110to determine the phase of the local always running timer116relative to the system timer114, and therefore capture a more precise snapshot of the local always running timer116.

The compute device100may be embodied as any type of compute device capable of managing data packets and performing the functions described herein. For example, the compute device100may be embodied as or otherwise be included in, without limitation, a server computer, an embedded computing system, a System-on-a-Chip (SoC), a multiprocessor system, a processor-based system, a consumer electronic device, a smartphone, a cellular phone, a desktop computer, a tablet computer, a notebook computer, a laptop computer, a network device, a router, a switch, a networked computer, a wearable computer, a handset, a messaging device, a camera device, and/or any other computing device. In some embodiments, the compute device100may be embodied as an Internet-of-Things device and form, potentially with other devices, a mesh network, which may operate at the edge of a cloud network, as described below in more detail in regard toFIG. 5. The illustrative compute device100includes a processor102, a memory104, an input/output (I/O) subsystem106, data storage108, the network interface card110, the always running timer112, and the serial broadcast wire118. In some embodiments, one or more of the illustrative components of the compute device100may be incorporated in, or otherwise form a portion of, another component. For example, the memory104, or portions thereof, may be incorporated in the processor102in some embodiments.

The processor102may be embodied as any type of processor capable of performing the functions described herein. For example, the processor102may be embodied as a single or multi-core processor(s), a single or multi-socket processor, a digital signal processor, a graphics processor, a microcontroller, or other processor or processing/controlling circuit. Similarly, the memory104may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory104may store various data and software used during operation of the compute device100such as operating systems, applications, programs, libraries, and drivers. The memory104is communicatively coupled to the processor102via the I/O subsystem106, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor102, the memory104, and other components of the compute device100. For example, the I/O subsystem106may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem106may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor102, the memory104, and other components of the compute device100on a single integrated circuit chip or a single multi-chip package.

The data storage108may be embodied as any type of device or devices configured for the short-term or long-term storage of data. For example, the data storage108may include any one or more memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices.

The network interface card110may be embodied as any type of interface capable of interfacing the compute device100with other compute devices, such as over a network. In some embodiments, the network interface card110may be referred to as a host fabric interface (HFI). The network interface card110may be configured to use any one or more communication technology and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, near field communication (NFC), etc.). The network interface card110may be capable of interfacing with any appropriate cable type, such as an electrical cable or an optical cable, and/or may be capable of interfacing with a wireless signal, such as through one or more antennae. The network interface card110may be located on silicon separate from the processor102, or the network interface card110may be included in a multi-chip package with the processor102, or even on the same die as the processor102. The network interface card110may be embodied as one or more add-in-boards, daughtercards, network interface cards, controller chips, chipsets, specialized components such as a field programmable gate array (FPGA) or application specific integrated circuit (ASIC), or other devices that may be used by the compute device100to connect with another compute device. In some embodiments, network interface card110may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the network interface card110may include a local processor (not shown) and/or a local memory (not shown) that are both local to the network interface card110. In such embodiments, the local processor of the network interface card110may be capable of performing one or more of the functions of the processor102described herein. Additionally or alternatively, in such embodiments, the local memory of the network interface card110may be integrated into one or more components of the compute device100at the board level, socket level, chip level, and/or other levels.

The network interface card110includes the system timer114and the local always running timer116. The system timer114may run at a relatively high frequency, such as 200 MHz, and the local always running timer116may run at a relatively low frequency, such as 19.2 MHz. It should be appreciated that the system time114and the local always running timer116are free-running and not locked to one another. The system timer114may be used as a timer in certain networking operations, such as sending and receiving data packets. Each of the system timer114and the local always running timer114has an associated timing value, which increases by one for every period of a clock cycle of the corresponding clock. The timing value of the local always running timer114may be reset to a particular value, such as when a new timestamp value of the always running timer112has been received by the network interface card110. It should be appreciated that the local always running timer116may operate based on the same clock as the always running timer112. The local always running timer116may be powered down in certain instances, such as when the network interface card110is powered down.

The always running timer112may be embodied as any type of clock to produce timing values indicative of passage of time, such as a crystal oscillator or a ceramic oscillator, an inductor-capacitor (LC) clock, a resistor-capacitor (RC) clock, etc. The always running timer112may oscillate at any frequency, such as above or below 1, 2, 5, 10, 15, 20, 30, 35, 50, 100, or 250 megahertz (MHz) or between any of those values. In the illustrative embodiment, the always running timer112oscillates at approximately 19.2 MHz. The always running timer112has an associated timing value, which increases by one for every period of the always running timer112. The timing value of the always running timer112may be stored in any manner, such as in a 64-bit register, a 32-bit register, a 16-bit register, a 10-bit register, an 8-bit register etc. The timing value of the always running timer112may always increase, or may be able to be reset to zero (or set to a specific value) by an instruction of the compute device100. In some embodiments, the clock signal used to drive the always running timer112may be provided to other components of the compute device100, such as the components to which the always running timer112broadcasts a signal through the serial broadcast wire118. In the illustrative embodiment, the always running timer112is continues to run as long as power to the compute device100is available, and the always running timer112may have a battery used exclusively for the always running timer112. In some embodiments, the always running timer112may be powered down in certain circumstances, such as when the compute device100is in a low power state such as a sleep or hibernation state or is completely turned off.

The serial broadcast wire118is configured to carry a broadcasted signal from the always running timer112to other components of the compute device100, such as the network interface card110or additional components120. In the illustrative embodiment, the serial broadcast wire118may be embodied as a single wire, including branches to each of the components to which the signal is being broadcast. The serial broadcast wire118may provide a single-ended signal relative to a ground signal, such as a ground plane or ground wire of the compute device100. Additionally or alternatively, the serial broadcast wire118may be embodied as two or more wires which may carry a differential signal. In some embodiments, the serial broadcast wire118may not even be a wire, but may be an optical fiber or other medium to carry an optical or wireless signal. Signals sent on the serial broadcast wire118may operate at a clock frequency established by the always running timer112, such as the same clock frequency which is used to drive the always running timer112.

In some embodiments, the compute device100may include other or additional components, such as those commonly found in a compute device. For example, the compute device100may also have additional components120, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), various input/output devices, etc. It should be appreciated that some or all of the additional components120may be connected to the serial broadcast wire118.

Referring now toFIG. 2, in an illustrative embodiment, the compute device100establishes an environment200during operation. The illustrative environment200includes an always running timer controller202and a network interface controller204. The various components of the environment200may be embodied as hardware, firmware, software, or a combination thereof. For example, the various modules, logic, and other components of the environment200may form a portion of, or otherwise be established by, the processor102or other hardware components of the compute device102such as the memory104. As such, in some embodiments, one or more of the components of the environment200may be embodied as circuitry or collection of electrical devices (e.g., an always running timer controller circuit202, a network interface controller circuit204, etc.). It should be appreciated that, in such embodiments, one or more of the circuit (e.g., the always running timer controller circuit202, the network interface controller circuit204, etc.) may form a portion of the processor102, the memory104, the I/O subsystem106, and/or other components of the compute device100. Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another. Further, in some embodiments, one or more of the components of the environment200may be embodied as virtualized hardware components or emulated architecture, which may be established and maintained by the processor102or other components of the compute device100.

The always running timer controller202is configured to sample values of the always running timer112, generate timestamp values based on the values of the always running timer112, and broadcast the timestamp values over the serial broadcast wire118. The always running timer controller202may add additional fields to the signal to be broadcast, such as a synchronization field and type field. The synchronization field may be one or more bits indicating a pattern that can be used to synchronize to the signal being broadcast. The pattern used for the synchronization field may be any suitable pattern, such as alternating ones and zeros. The type field may be one or more bits indicating various metadata relating to the timestamp value, such as whether the broadcasting is continuous or periodic, whether an offset value should be added to the timestamp value, and/or the like. In the illustrative embodiment, the synchronization field is 68 bits, the type field in 4 bits, and the field for the timestamp value is 64 bits. In some embodiments, the always running timer controller202may determine an offset value that is added to the timestamp value before broadcasting the timestamp value. The offset value may correspond to the time it takes for the signal of the serial broadcast wire118to reach other components of the compute device100, so that the timestamp value that is broadcast would indicate the value of the always running timer112at the time the timestamp value is received. The offset value may be determined during design of the compute device100or components of the compute device100and stored in the compute device100for use by the always running timer controller202.

The always running timer controller202includes a timestamp broadcaster206. The timestamp broadcaster206is configured to broadcast the timestamp values generated by the always running timer controller202to other components of the compute device100over the serial broadcast wire118. The timestamp broadcaster206may send timestamp values periodically, continuously, or continually. When broadcasting periodically, the timestamp broadcaster206may broadcast at any suitable interval, such as 10 microseconds, 20 microseconds, 50 microseconds, 100 microseconds, 200 microseconds, 500 microseconds, 1 millisecond, 2 milliseconds, 5 milliseconds, 10 milliseconds, etc. The timestamp broadcaster206may include a parallel to serial converter to convert a parallel bus signal (such as a 64-bit bus signal) to a serial signal for broadcasting on the serial serial-wire interface118. It should be appreciated that, in the illustrative embodiment, the timestamp broadcaster206does not need a request for a timestamp before a timestamp is broadcast, but rather the timestamp broadcaster206will continue to broadcast timestamps even without any requests. In fact, in the illustrative embodiment, the serial broadcast wire118is configured to only provide one-way transmission of information from the always running timer112to other components of the compute device100.

The network interface controller204, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to control the network interface card110, including the interaction of the network interface card110with the physical medium to which it is attached and the processing of incoming and outgoing signals which the network interface card110receives and sends. The network interface controller204may be configured to use any one or more communication technology and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, near field communication (NFC), etc.). The network interface controller204may be capable of interfacing with any appropriate cable type, such as an electrical cable or an optical cable, and/or may be capable of interfacing with a wireless signal, such as through one or more antennae. The network interface controller204includes a timer sampler208and a local always running timer controller210. It should be appreciated that the network interface controller204may use the system timer114as a clock for sending and/or receiving data using the network interface card110, while other components of the compute device100such as the processor102that are locked to the always running timer112may process packets or data that is sent and/or received on the network interface card110. The synchronization between the system timer114, the local always running timer116, and the always running timer112may allow for networking tasks to be scheduled and/or timestamped more precisely.

The timer sampler208is configured to capture a snapshot of both the system timer114and the local always running timer116. In the illustrative embodiment, the timer sampler208may capture a snapshot of both timers114and116simultaneously. Additionally or alternatively, the timer sampler208may capture a snapshot of the two timers114and116with a fixed delay that can be compensated for, such as one clock cycle. The timer sampler208may run based on a clock signal of the network interface card110, such as the same clock signal that the system timer114runs on, which may be, e.g., a 200 MHz clock. As such, the timer sampler208may simply copy the value of the system timer114to capture a precise snapshot of the system timer114. However, the local always running timer116may run based on a clock signal at a different frequency, such as 19.2 MHz. If not compensated for, merely capturing a snapshot of the value of the local always running timer116may lead to a relatively large uncertainty because of the unknown phase between the system timer114and the local always running timer116. However, by oversampling the local always running timer116, such as at a rate at least twice the frequency of the local always running timer116, the timer sampler208can precisely determine the phase of the local always running timer116and the system114. The timer sampler208saves the captured value of the system timer114and the local always running timer116, including an adjustment to the value of the local always running timer116to compensate for the phase difference. It should be appreciated that the network interface controller204may access the captured values of the local always running timer116and the system timer114at some later time and determine, based on the captured values, the current value of the local always running timer116and/or the system timer114. Since the local always running timer116and the system timer114operate a different frequencies, determining the value of each of them at some later time may require interpolation.

The local always running timer controller210is configured to control the local always running timer114. The local always running timer controller210may monitor the signal of the single-wire interface118. In the illustrative embodiment, the local always running timer controller210converts the serial signal of the serial broadcast wire118to a parallel signal before sampling the signal. Additionally or alternatively, the local always running timer controller210may sample the serial broadcast wire118directly without converting it to a parallel interface. The local always running timer controller210may read the timestamp value sent on the serial broadcast wire118and then the local always running timer controller210may update the value of the local always running timer114based on the timestamp value. In some embodiments, the local always running timer controller210may determine an offset value that is added to the timestamp value before updating the local always running timer114. The offset value may correspond to the time it takes for the signal of the serial broadcast wire118to reach the network interface controller204. The offset value may be determined during design of the compute device100or components of the compute device100and stored in the compute device100for use by the local always running timer controller210. In the illustrative embodiment, the local always running timer controller210updates the local always running timer116to have the same value as the always running timer112.

Referring now toFIG. 3, in use, the compute device100may execute a method300for broadcasting a timestamp. It should be appreciated that, in some embodiments, the operations of the method300may be performed by one or more components of the environment200of the compute device100as shown inFIG. 2. The method300begins in block302, in which, if the compute device100is to broadcast a timestamp, the method300proceeds to block304to read a timestamp value from the always running timer112. If the compute device100is not to broadcast a timestamp, the compute device100loops back to block302to continue checking if a timestamp should be broadcast. As discussed above, the compute device100may broadcast a timestamp periodically, continuously, or continually.

In block304, the compute device100reads a counter value from the always running timer112. In block306, the compute device100generates a timestamp value based on the counter value of the always running timer112. In some embodiments, the compute device100may determine an offset value that is added to the counter value to generate the timestamp value. The offset value may correspond to the time it takes for the signal of the serial broadcast wire118to reach other components of the compute device100, so that the timestamp value that is broadcast would indicate the value of the always running timer112at the time the timestamp value is received. The offset value may be determined during design of the compute device100or components of the compute device100and stored in the compute device100, so the compute device100may access the offset value in block306. In some embodiments, the timestamp value may simply be equal to the counter value of the always running timer.

In block308, the compute device100prepares a timestamp signal to be sent on the serial broadcast wire118. In the illustrative embodiment, the compute device100adds a synchronization field, a type field, and a timestamp field to the timestamp signal. The compute device100adds the synchronization field in block310. The synchronization field may be one or more bits indicating a pattern that can be used to synchronize to the timestamp signal being broadcast. The pattern used for the synchronization field may be any suitable pattern, such as alternating ones and zeros. The compute device100adds the type field to the timestamp signal in block312. The type field may be one or more bits indicating various metadata relating to the timestamp value, such as whether the broadcasting is continuous or periodic, whether an offset value should be added to the timestamp value, and/or the like. The compute device100adds the timestamp field in block314, which consists of the timestamp value generated in block306. In the illustrative embodiment, the synchronization field is 68 bits, the type field in 4 bits, and the field for the timestamp value is 64 bits. In some embodiments, the synchronization field and/or the type field may be omitted.

In block316, the compute device100converts the parallel timestamp signal prepared in block308to a serial timestamp signal. In block318, the compute device100broadcasts the serial timestamp signal on the serial broadcast wire118.

Referring now toFIG. 4, in use, the compute device100may execute a method400for receiving broadcast timestamps. It should be appreciated that, in some embodiments, the operations of the method400may be performed by one or more components of the environment200of the compute device100as shown inFIG. 2. The method400begins in block402, in which the compute device100converts the serial signal of the serial broadcast wire at the network interface card110to a parallel signal. In some embodiments, the compute device100may not convert the serial broadcast wire to a parallel signal and may sample the serial broadcast wire directly. It should be appreciated that, in the illustrative embodiment, the serial-to-parallel converter operates on the same clock frequency as the serial broadcast wire118, which may, as discussed above, be provided to various components of the compute device100including the network interface card110. In block404, the compute device100reads the parallel bus. In block406, the compute device100determines whether the synchronization pattern is present in the signal read from the parallel bus. The synchronization pattern may be any pattern composed of a series of one or more bits. In the illustrative embodiment, the synchronization pattern is 68 bits long, and may be, e.g., alternating ones and zeros.

In block408, if the synchronization pattern in not found, the method400loops back to block402to continue converting the serial signal of the serial broadcast wire118to a parallel signal. If the synchronization pattern is found, the method400proceeds to block410.

In block410, the compute device100parses the type field from the oversampled signal. The type field may be one or more bits indicating various metadata relating to the timestamp value, such as whether the broadcasting is continuous or periodic, whether an offset value should be added to the timestamp value, the amount of the offset value, and/or the like. In block412, the compute device100parses the timestamp value from the oversampled signal. The timestamp value may be any series of bits indicating a timing value, such as 64 bits in the illustrative embodiment.

In block414, the compute device100updates a local always running timer116based on the received timestamp value to mirror the value of the always running timer112. In some embodiments, the compute device100may determine an offset value that is added to the timestamp value before updating the local always running timer116. The offset value may correspond to the time it takes for the signal of the serial broadcast wire118to reach the network interface card110. The offset value may be determined during design of the compute device100or components of the compute device100and stored in the compute device100for use by the local always running timer card110. The method400may then loop back to block402to continue monitoring the serial broadcast wire118.

Referring now toFIG. 5, in use, the compute device100may execute a method500for capturing snapshots of the system timer114and the local always running timer116. The method500begins in block502, the compute device100captures a snapshot of the system timer114. In the illustrative embodiment, the compute device100simply copies a counter value of the system timer, as the component capturing the snapshot of the system timer114may operate using the same clock as the system timer114.

In block504, the compute device100captures a snapshot of the local always running timer116. To do so, the compute device100may oversample the local always running timer116in block506, such as by sampling the local always running timer116at at least twice the frequency of the local always running timer116. In the illustrative embodiment, the local always running timer116may operate at 19.2 MHz and the clock used to sample the local always running timer116may be 200 MHz.

In block508, the compute device100determines the phase of the signal of the local always running timer116based on the oversampled data. Since the compute device100oversamples the signal of the local always running timer116, the compute device100may determine a phase of the clock associated with the local always running timer116relative to a phase of the clock associated with the sampling of the local always running timer116. Determining the phase of the clock allows for precise recovery of the time of the local always running timer116and, therefore, of the time of the always running timer112.

In block510, the compute device100stores the value of the system timer114and the value of the local always running timer116, such as in a register of the network interface card110or the data storage108. It should be appreciated that the compute device100may adjust the value of the local always running timer116based on the determined phase of the local always running timer116relative to the system timer114before storing the value of the local always running timer116. Additionally or alternatively, the compute device100may store the value of the local always running timer116as captured from the local always running timer116along with the determined phase of the local always running timer116relative to the system timer114.

It should be appreciated that, although the methods400and500were described as being performed at the network interface card110, the methods400and500may also be performed at other components of the compute device100, such as one or more of the additional components120.

Referring now toFIG. 6, in some embodiments, one or more compute devices100may be embodied as Internet-of-Things devices600and form, potentially with other devices, a mesh network, which may be termed as a fog650, operating at the edge of a cloud network652. The fog650may be considered to be a massively interconnected network wherein a number of IoT devices600are in communications with each other, for example, by links604(all of which are not labeled inFIG. 6to simplify the figure and for clarify). Each of the links604may be a wire connection, a wireless connection, an optical connection, etc. This may be performed using the open interconnect consortium (OIC) standard specification 1.0 released by the Open Connectivity Foundation™ (OCF) on Dec. 23, 2015. This standard allows devices to discover each other and establish communications for interconnects. Other interconnection protocols may also be used, including, for example, the optimized link state routing (OLSR) Protocol, or the better approach to mobile ad-hoc networking (B.A.T.M.A.N.), among others.

Three types of IoT devices600are shown in the example embodiment ofFIG. 6, gateways610, data aggregators612, and sensors614, although any combinations of IoT devices600and functionality may be used. The gateways610may be edge devices that provide communications between the cloud652and the fog650, and may also provide the backend process function for data obtained from sensors614. The data aggregators612may collect data from any number of the sensors614, and perform the back end processing function for the analysis. The results, raw data, or both may be passed along to the cloud652through the gateways610. The sensors614may be full IoT devices600, for example, capable of both collecting data and processing the data. In some cases, the sensors614may be more limited in functionality, for example, collecting the data and allowing the data aggregators612or gateways610to process the data.

Communications from any IoT device600may be passed along the most convenient path between any of the IoT devices600to reach the gateways610. In these networks, the number of interconnections provide substantial redundancy, allowing communications to be maintained, even with the loss of a number of IoT devices600. Further, the use of a mesh network may allow IoT devices600that are very low power or located at a distance from infrastructure to be used, as the range to connect to another IoT device600may be much less than the range to connect to the gateways610. The fog650of the IoT devices600devices may be presented to devices in the cloud652, such as a server620, as a single device located at the edge of the cloud652, e.g., a fog650device.

EXAMPLES

Example 1 includes a compute device for internal time synchronization, the compute device comprising an always running timer; an always running timer controller to read a counter value from a counter of the always running timer; generate a timestamp value based on the counter value of the always running timer; and broadcast the timestamp value on a serial single-wire interface at a frequency of a first clock; a network interface card comprising a system timer and a local always running timer; and a network interface controller to sample a signal indicative of the timestamp value broadcasted on the serial single-wire interface; update a counter of the local always running timer based on the sampled signal; capture a snapshot of a counter of the system timer; capture a snapshot of the counter of the local always running timer, wherein to capture the snapshot of the local always running timer comprises to sample the local always running clock at a frequency of a second clock, wherein the frequency of the second clock is at least twice the frequency of the first clock; determine a phase of the local always running timer relative to the system timer; and store an indication of the snapshot of the counter of the system timer, an indication of the snapshot of the counter of the local always running timer, and an indication of the phase of the local always running timer.

Example 2 includes the subject matter of Example 1, and wherein the always running timer controller is further to convert the timestamp value from a parallel bus to the serial single-wire interface, and wherein the network interface controller is further to convert the signal from the serial single-wire interface to a parallel bus.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the always running timer controller is further to broadcast, with the timestamp value, a synchronization pattern on the serial single-wire interface, wherein the network interface controller is further to determine whether the sampled signal includes the synchronization pattern; wherein to determine the timestamp value of the signal comprises to determine the timestamp value of the signal in response to a determination that the sampled signal includes the synchronization pattern.

Example 4 includes the subject matter of any of Examples 1-3, and wherein the always running timer controller is further to access an offset value indicative of a latency of a signal over the serial single-wire interface, wherein to generate, the timestamp value comprises to add the offset value to the counter value.

Example 5 includes the subject matter of any of Examples 1-4, and wherein the network interface controller is further to access an offset value indicative of a latency of a signal over the serial single-wire interface, wherein to update the counter of the local always running timer comprises to update the counter of the local always running timer based on the offset value.

Example 6 includes the subject matter of any of Examples 1-5, and wherein the always running timer controller is further to broadcast, with the timestamp value, one or more type bits, wherein the one or more type bits indicate whether the compute device is to broadcast timestamp values continuously or periodically.

Example 7 includes the subject matter of any of Examples 1-6, and wherein the always running timer controller is further to broadcast, with the timestamp value, one or more type bits, wherein the one or more type bits indicate whether an offset value should be added to the timestamp value.

Example 8 includes the subject matter of any of Examples 1-7, and wherein to broadcast the timestamp value comprises to broadcast the timestamp value without receipt of a request for the timestamp value.

Example 9 includes the subject matter of any of Examples 1-8, and wherein to broadcast the timestamp value on the serial single-wire interface comprises to broadcast the timestamp value to each of a plurality of components of the compute device different from the always running timer.

Example 10 includes the subject matter of any of Examples 1-9, and wherein the always running timer and the network interface card are integrated onto a single chip.

Example 11 includes the subject matter of any of Examples 1-10, and wherein the always running timer and the network interface card are integrated into a single multi-chip package.

Example 12 includes the subject matter of any of Examples 1-11, and wherein to broadcast the timestamp value on the serial single-wire interface comprises to broadcast a single-ended signal on the serial single-wire interface.

Example 13 includes the subject matter of any of Examples 1-12, and wherein the always running timer is configured to power down when the compute device enters a low power state.

Example 14 includes a method for internal time synchronization of a compute device, the method comprising reading, by the compute device, a counter value from a counter of an always running timer of the compute device; generating, by the compute device, a timestamp value based on the counter value of the always running timer; broadcasting, by the compute device, the timestamp value on a serial single-wire interface at a frequency of a first clock; sampling, by the compute device, a signal indicative of the timestamp value broadcasted on the serial single-wire interface; updating, by the compute device and based on the sampled signal, a counter of a local always running timer of a network card of the compute device; capturing, by the compute device, a snapshot of a counter of a system timer of the network interface card; capturing, by the compute device, a snapshot of the counter of the local always running timer, wherein capturing the snapshot of the local always running timer comprises to sample the local always running timer at a frequency of a second clock, wherein the frequency of the second clock is at least twice the frequency of the first clock; determining, by the compute device and based on the oversampled snapshot of the counter of the local always running timer, a phase of the always running timer relative to the system timer; and storing an indication of the snapshot of the counter of the system timer, an indication of the snapshot of the counter of the local always running timer, and an indication of the phase of the local always running timer.

Example 15 includes the subject matter of Example 14, and further including converting, by the compute device, the timestamp value from a parallel bus to the serial single-wire interface; and converting, by the compute device, the signal from the serial single-wire interface to a parallel bus.

Example 16 includes the subject matter of any of Examples 14 and 15, and further including broadcasting, by the compute device and with the timestamp value, a synchronization pattern on the serial single-wire interface; determining, by the compute device, whether the sampled signal includes the synchronization pattern; wherein determining the timestamp value of the signal comprises determining the timestamp value of the signal in response to a determination that the sampled signal includes the synchronization pattern.

Example 17 includes the subject matter of any of Examples 14-16, and further including accessing, by the compute device, an offset value indicative of a latency of a signal over the serial single-wire interface, wherein generating, the timestamp value comprises adding, by the compute device, the offset value to the counter value.

Example 18 includes the subject matter of any of Examples 14-17, and further including accessing, by the compute device, an offset value indicative of a latency of a signal over the serial single-wire interface, wherein updating the counter of the local always running timer comprises updating the counter of the local always running timer based on the offset value.

Example 19 includes the subject matter of any of Examples 14-18, and further including broadcasting, by the compute device and with the timestamp value, one or more type bits, wherein the one or more type bits indicate whether the compute device is to broadcast timestamp values continuously or periodically.

Example 20 includes the subject matter of any of Examples 14-19, and further including broadcasting, by the compute device and with the timestamp value, one or more type bits, wherein the one or more type bits indicate whether an offset value should be added to the timestamp value.

Example 21 includes the subject matter of any of Examples 14-20, and wherein broadcasting the timestamp value comprises broadcasting the timestamp value without receipt of a request for the timestamp value.

Example 22 includes the subject matter of any of Examples 14-21, and wherein broadcasting the timestamp value on the serial single-wire interface comprises broadcasting the timestamp value to each of a plurality of components of the compute device different from the always running timer.

Example 23 includes the subject matter of any of Examples 14-22, and wherein the always running timer and the network interface card are integrated onto a single chip.

Example 24 includes the subject matter of any of Examples 14-23, and wherein the always running timer and the network interface card are integrated into a single multi-chip package.

Example 25 includes the subject matter of any of Examples 14-24, and wherein broadcasting the timestamp value on the serial single-wire interface comprises broadcasting a single-ended signal on the serial single-wire interface.

Example 26 includes the subject matter of any of Examples 14-25, and further including powering down the always running timer when the compute device enters a low power state.

Example 27 includes one or more computer-readable media comprising a plurality of instructions stored thereon that, when executed, causes a compute device to perform the method of any of Examples 15-26.

Example 28 includes a compute device for internal time synchronization, the compute device comprising means for reading a counter value from a counter of an always running timer of the compute device; means for generating a timestamp value based on the counter value of the always running timer; means for broadcasting the timestamp value on a serial single-wire interface at a frequency of a first clock; means for sampling a signal indicative of the timestamp value broadcasted on the serial single-wire interface; means for updating, based on the sampled signal, a counter of a local always running timer of a network card of the compute device; means for capturing a snapshot of a counter of a system timer of the network interface card; means for capturing a snapshot of the counter of the local always running timer, wherein capturing the snapshot of the local always running timer comprises to sample the local always running timer at a frequency of a second clock, wherein the frequency of the second clock is at least twice the frequency of the first clock; means for determining, based on the oversampled snapshot of the counter of the local always running timer, a phase of the always running timer relative to the system timer; and means for storing an indication of the snapshot of the counter of the system timer, an indication of the snapshot of the counter of the local always running timer, and an indication of the phase of the local always running timer.

Example 29 includes the subject matter of Example 28, and further including means for converting the timestamp value from a parallel bus to the serial single-wire interface; and means for converting the signal from the serial single-wire interface to a parallel bus.

Example 30 includes the subject matter of any of Examples 28 and 29, and further including means for broadcasting, with the timestamp value, a synchronization pattern on the serial single-wire interface; means for determining whether the sampled signal includes the synchronization pattern; wherein the means for determining the timestamp value of the signal comprises means for determining the timestamp value of the signal in response to a determination that the sampled signal includes the synchronization pattern.

Example 31 includes the subject matter of any of Examples 28-30, and further including means for accessing an offset value indicative of a latency of a signal over the serial single-wire interface, wherein the means for generating, the timestamp value comprises means for adding the offset value to the counter value.

Example 32 includes the subject matter of any of Examples 28-31, and further including means for accessing an offset value indicative of a latency of a signal over the serial single-wire interface, wherein the means for updating the counter of the local always running timer comprises means for updating the counter of the local always running timer based on the offset value.

Example 33 includes the subject matter of any of Examples 28-32, and further including means for broadcasting, with the timestamp value, one or more type bits, wherein the one or more type bits indicate whether the compute device is to broadcast timestamp values continuously or periodically.

Example 34 includes the subject matter of any of Examples 28-33, and further including means for broadcasting, with the timestamp value, one or more type bits, wherein the one or more type bits indicate whether an offset value should be added to the timestamp value.

Example 35 includes the subject matter of any of Examples 28-34, and wherein the means for broadcasting the timestamp value comprises means for broadcasting the timestamp value without receipt of a request for the timestamp value.

Example 36 includes the subject matter of any of Examples 28-35, and wherein the means for broadcasting the timestamp value on the serial single-wire interface comprises means for broadcasting the timestamp value to each of a plurality of components of the compute device different from the always running timer.

Example 37 includes the subject matter of any of Examples 28-36, and wherein the always running timer and the network interface card are integrated onto a single chip.

Example 38 includes the subject matter of any of Examples 28-37, and wherein the always running timer and the network interface card are integrated into a single multi-chip package.

Example 39 includes the subject matter of any of Examples 28-38, and wherein the means for broadcasting the timestamp value on the serial single-wire interface comprises means for broadcasting a single-ended signal on the serial single-wire interface.

Example 40 includes the subject matter of any of Examples 28-39, and wherein the always running timer is configured to power down when the compute device enters a low power state.