Method and apparatus for memory training concurrent with data transfer operations

Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first partition of a memory controller, and a training operation may be performed for a second partition of the memory controller coupled to a second memory device while the first partition of the memory controller is transferring data from the first memory device.

FIELD

This application pertains to the field of memory controllers, and more particularly, to the field of memory interconnects.

BACKGROUND

A wide range of electronic devices include graphics processing units (GPU). Some examples of devices that may include a GPU include computer systems, gaming consoles, digital video disc (DVD) players, etc. A GPU may include graphics memory controllers that interface with local graphics memory devices. In a continuing effort to increase graphics subsystem performance, interconnect speeds between the graphics memory controllers and the local graphics memory devices are increasing. Training techniques may be used on these interconnects to adjust various parameters associated with data transfers between the graphics memory controller and the local graphics memory devices in order to allow increased clock frequencies.

Training operations may include manipulating a variety of parameters which may include driver impedance, termination impedance, reference voltage levels, data strobe timing, etc. Training operations may take significant periods of time and may prevent a GPU from delivering display data to a display device for those significant periods of time. It would be desirable to allow a GPU to deliver display data to a display device while training operations are being performed.

Similar training operations may also occur with other interfaces, including system memory interfaces. It would be desirable to allow data transfers while training operations are being performed.

DETAILED DESCRIPTION

FIG. 1is a block diagram of one embodiment of an example system100including a GPU200coupled to a local graphics memory210. System100also includes a central processing unit (CPU)110, a system memory130, and an input/output hub140. A memory controller120allows communication among CPU110, system memory130, input/output hub140, and GPU200. GPU200is coupled to a display device160.

For this example system, local graphics memory210includes four separate interfaces. Local graphics memory may include a number of different graphics memory devices. For this example embodiment, there are four graphics memory devices, labeled A through D. Of course, other embodiments are possible with other numbers and configurations of interfaces and memory devices. The interconnects between local graphics memory210and GPU200may be serial interfaces, or may be parallel interfaces.

FIG. 2is a block diagram showing one embodiment of GPU200coupled to local graphics memory210. As mentioned above, for this example embodiment, local graphics memory210includes a number of graphics memory devices, labeled A through D. Graphics Processing Unit200includes a graphics memory controller220and a switching logic230. The graphics memory controller230for this example is divided into four partitions, labeled1through4. Each of the partitions corresponds to one of the graphics memory devices, and provides communication with the corresponding graphics memory devices. Switching logic230determines which of the graphics memory controller partitions is active and may determine various aspects of graphics data transfers between the graphics memory controller partitions and their associated graphics memory devices.

As used herein, the term “memory controller partition” is meant to include not only distinct portions of a single memory controller associated with corresponding memory device interfaces, but also includes multiple discrete memory controllers.

For this example embodiment, whenever it is necessary to perform training operations for the graphics memory controller partitions, switching logic230causes the graphics memory controller to perform graphics data transfers to or from only one of the graphics memory devices. For this example, the partition used is partition4which communicates with graphics memory device D over what may be referred to as reliable interface201. The term “reliable interface” is meant to include a wide range of interconnect technologies that may provide reliable operation without first requiring training operations. For example, reliable interface201may be operated at a reduced clock frequency to help ensure reliable operation.

While GPU200is performing operations while operating out of graphics memory device D over reliable interface201, one or more of the other graphics memory controller partitions may undergo training operations in anticipation of operating the associated interconnects at a high speed. Once one or more of the other graphics memory controller partitions have completed the training operations, switching logic230may allow graphics data transfers to occur using the recently trained interconnects.

For this example embodiment, once the training operations for graphics memory controller partitions1-3are completed and GPU200is performing operations out of graphics memory devices A, B, and C, reliable interface201may undergo training operations in order to allow operation at higher clock frequencies.

FIG. 3is a block diagram of one embodiment of an example system300including a graphics memory block332located within a system memory330. System300includes a CPU310coupled to a memory controller hub320, which is also coupled to system memory330and a GPU350. Memory controller hub320is further coupled to an input/output hub340. GPU350provides display data to a display device370.

This example system is similar to system100discussed above, except that graphics memory block332within system memory330is used as the reliable memory that can be used to perform graphics operations while training operations are performed on the interconnects between local graphics memory devices A, B, C, and D and GPU350. A memory controller (not shown) within the memory controller hub320may be considered to be a graphics memory controller partition for this example because for this example a portion of system memory330is used for graphics memory.

Although systems100and300are described with particular configurations, many other embodiments are possible using other system configurations. Further, many other graphics processing unit and graphics memory embodiments are possible other than the example embodiments described herein. Also, although the embodiments described herein utilize multiple partitions within a single graphics memory controller, other embodiments may use one or more discrete graphics memory controllers.

Graphics processing unit embodiments that use a reliable graphics memory interconnect while other graphics memory interconnects are being trained may be included in a wide range of electronic devices, including, but not limited to, computer systems, game consoles, DVD players, etc.

Further, although the above discussion in connection withFIGS. 1 through 3mention multiple graphics memory controller partitions and training graphics memory interconnects, the range of possible embodiments is not limited to graphics memory implementations. Other embodiments are possible where other memory controllers, including, but not limited to, system memory controllers, are divided into at least two partitions and one partition is used to perform data transfers over a reliable interconnect while another interconnect associated with a second partition is involved in training operations.

FIG. 4is a flow diagram of one embodiment of an example method for training a memory interface while allowing data transfers. The processing begins at block410, and continues at blocks420and430. The operations at blocks420and430may occur simultaneously. At block420, data transfers are performed from a first memory device to a first memory controller partition. At block430, a training operation for a second memory controller partition is performed. Processing then moves to block440, where data transfers are performed to a second memory device from the second memory controller partition.

FIG. 5is a flow diagram of one embodiment of an example method for training a graphics memory interface while allowing graphics data transfers. Processing begins at block510and moves to blocks520and530. At block520, graphics data transfers are performed from a first graphics memory device to a first graphics memory controller partition. At block530, a training operation for a second graphics memory controller partition is performed. Processing then proceeds to blocks540and550. At block540, a training operation for the first graphics memory controller is performed. At block550, graphics data transfers are performed to the second graphics memory device from the second graphics memory controller partition. Processing then moves to block560, where graphics data transfers are performed to and from the first and second graphics memory devices using the first and second graphics memory controller partitions.

FIG. 6is a flow diagram of one embodiment of an example method for training a memory interface while allowing data transfers. At610, data transfers are performed from a first memory device to a first partition while the second partition is performing a memory interconnect training operation, wherein the first partition operates at lower clock frequency than the second partition. At620, after the second partition completes the memory interconnect training operation, the first partition is operated at an increased clock frequency and a memory interconnect training operation is performed for the first partition.

Although the embodiments described herein may use any of a wide range of interconnect training techniques, one such technique may include powering up a memory controller device to a default driver and termination impedance. Clock frequencies may be set to a desired frequency. Then, a data strobe may trained to be positioned at least approximately in the middle of a valid data window. Next, a reference voltage may be trained to the middle of its window. The data strobe may then be trained again to be positioned in the middle of its window. Then, the driver impedance may be trained to fall somewhere in the middle of a range of good values. The data strobe may then again be trained to be positioned in the middle of its window. Next, the termination impedance may be trained to the middle of its window, and then the reference voltage may then again be trained. Lastly, the data strobe may then again be trained to occur approximately in the middle of the valid data window.

In the foregoing specification the claimed subject matter has been described with reference to specific example embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the subject matter as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.