Adaptive startup control for boost converter

This document discusses apparatus and methods for a boost converter start-up circuit. In an example, a start-up circuit can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter. The linear current generator can include a modified current mirror and a feedback circuit configured to provide a first representative of an output voltage of the output terminal to an input of each of a first and a second adjustable current source of the modified current mirror.

OVERVIEW

This document discusses, among other things, apparatus and methods for a boost converter start-up circuit. In an example, a start-up circuit can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter. The linear current generator can include a modified current mirror and a feedback circuit configured to provide a first representative of an output voltage of the output terminal to an input of each of a first and a second adjustable current source of the modified current mirror.

This overview is intended to provide a general overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.

DETAILED DESCRIPTION

A “boost” converter, boost regulator, or step-up converter, is configured such that a predetermined voltage at the output of the converter can be greater than a voltage at an input of the converter. In certain examples, a boost converter can provide a minimum voltage rail for applications that require higher voltages than a battery, for example, can supply.

Upon start-up of a boost converter, conditions can exist that can prevent a boost controller from entering a boost mode unless current flow between the input of the boost converter and the output of the boost converter is controlled. At the same time, it can be desirable to have the boost converter begin regulating to output voltage of the boost controller as quickly as possible.

In some situations, startup of a boost converter can result in a large input current spike. Large input current spikes can cause the boost converter to shut down. In some boost converter applications, output capacitive loading is often unknown and the range of capacitance can be wide. a start-up duration of a boost converter can be slow where a high output capacitive loading exist and current limiting is implemented to reduce the possibility of high input current spikes. In certain situations, input current limiting can also result in extended start up intervals for boost conveters coupled to small capacitive loading applications.

The present inventors have recognized, among other things, various techniques that can reduce or eliminate large input current spikes during start-up of a boost converter and can adapt to load conditions such as different output capacitances. In certain examples, improved start-up behavior can be implemented to minimize input current spikes and overshoots, including applications with low-voltage battery. In certain examples, a boost controller can include an adaptive control to provide a short start-up interval for a wide range of capacitive loads. In some examples, the boost conveter reduce current transients as the boost conveter transistions between start-up and a boost mode of operation by pulling the output voltage of the boost controller substantially equal to, or very close to, the input voltage before transistioning to the boost mode, even during heavy load conditions.

FIG. 1depicts an existing start-up circuit100for a boost converter. The start-up circuit100includes a simple current mirror101, a voltage divider102, a reference capacitor103, start-up resistor104, a reference generator105, and a comparator106. The current mirror101can limit the start-up current flowing between the input voltage (VIN) source and the load via the output voltage (VOUT) of the boost converter. The interval of the start-up circuit100can be set by the combination of the reference generator105, reference capacitor103and start-up resistor104. As the reference capacitor103charges up to a value near the scaled output voltage provided by the voltage divider102, the output (ERROR) of the comparator106can start the boost mode. Note that the start-up interval is independent of the difference between the input voltage (VIN) and the output voltage (VOUT) of the boost converter.

FIG. 2illustrates generally an example start-up circuit200for a voltage converter200including a boost converter230. The start-up circuit200can include a linear current generator211including a modified current mirror, reference sampling circuit212, and a reference stepping circuit213for controlling the rate of increase of the output voltage (VOUT) of the boost controller after the start-up interval. In certain examples, the modified current mirror of the linear current generator can provide linear start-up current and can combine drain-source voltage (VDS) and output voltage (VOUT) feedback. In certain examples, combining drain-source voltage (VDS) and output voltage (VOUT) feedback can enable time-efficient start-up while reducing input current spikes even at high load conditions.

In certain examples, the reference sampling circuit212can enable a smooth start-up regardless of the output voltage VOUTbefore the startup event occurs by providing an indication of the initial output voltage to charge the reference capacitor203.

In certain examples, the reference step circuit213can prevent high input rush current in the case of high capacitive loading of the output, and can assist in providing a fast start-up with a low capacitive loading of the output, in contrast to existing techniques. In some examples, logarithmic reference stepping, at boost start-up, can improve the output voltage (VOUT) slope over existing techniques and can reduce or eliminate input current ramp-up when the output voltage (VOUT) approaches a target value.

FIG. 3illustrates generally an example linear current generator311including a modified current mirror320for limiting current from the input supply to the load of the boost converter upon first starting up the boost converter. In certain examples, the modified current mirror320can include a first current mirror321and a second current mirror322configured to selectively couple the input voltage (VIN) of the input supply of the converter to the output of the converter. The first current mirror321can include a first sense transistor323and a first mirror transistor324. The second current mirror322can include a second sense transistor325and a second mirror transistor326. The modified current mirror320can have the control, or gate, nodes of the first current mirror transistors323,324coupled to a drain of the second mirror transistor325. In certain examples, the modified current mirror320can include a first leg327including the first sense transistor323and the second mirror transistor325, and a second leg328including the first mirror transistor324and the second sense transistor326.

In certain examples, the modified current mirror320can include first and second adjustable current sources331,332and an output voltage feedback circuit333for adjusting the adjustable current sources331,332. In certain examples, the output voltage feedback circuit333can include a voltage divider coupled to the output voltage (VOUT) of the boost converter. In certain examples, a scaled representation of the output voltage, provided by the output voltage feedback circuit333, can provide at least a portion of a setpont to adjust the first and second adjustable current sources331,332. In certain examples, the first adjustable current source331can be coupled to the first leg327of the modified current mirror320and the second adjustable current source332can be coupled to the second leg328of the modified current mirror320. The example configuration of the modified current mirror320can include both output voltage feedback and drain-to-source voltage (Vds) feedback. When the output voltage (VOUT) is initially around zero volts at start-up, the output voltage feedback can reduce or eliminate current overshoot as the modified current mirror320begins to raise the output voltage (VOUT). When the output voltage (VOUT) nears the input voltage, the Vds feedback can maintain current flow to allow the output voltage (VOUT) to continue to rise towards the input voltage (VIN). In the case of a standard current mirror, as the output voltage approaches the input voltage level, the current drops and the rise of the output voltage stalls significantly short of the input voltage resulting in large current transients as the converter transistions from starting up to the boost mode.

FIG. 4, illustrates generally an example output voltage sampling circuit412. In certain examples, the output voltage sampling circuit412can include a switch440and a charging resistor441coupled between a representation of the output voltage (VOUT) for an amplifier406and a reference capacitor403. In certain examples, the output voltage sampling circuit412can charge a reference capacitor403to a voltage representative of the output voltage (VOUT). In certain examples, the voltage across the reference capacitor403can provide a target voltage, or boost set point, for the boost converter. By sampling the output voltage (VOUT) during the startup of the boost converter, the boost mode can begin to boost the output voltage (VOUT) from a known value and can reduce transients. This can provide better performance in cases where the boost controller is disabled for short period of time and the output voltage (VOUT) does not fully discharge before the boost converter is re-enabled.

FIG. 5illustrates generally an example reference step circuit513. In certain examples, the reference step circuit513can include a comparator550configured to compare a representation of the output voltage (VOUT) to a target voltage and enable and disable a clock generator551responsive to the comparison. In an example, the output of the comparator550can provide an indication of the relative difference between the output voltage (VOUT) and a target voltage. In certain examples, as the error between the actual output voltage (VOUT) and the target voltage becomes smaller, the comparator550can enable the clock generator551. In certain examples, the clock generator551can include at least two outputs. When enabled, the clock generator551can provide, or generate, a clock signal at the outputs, In some examples, the clock generator can generate a single pulse on one or more outputs. The pulse output of the clock generator551can change the state of a first switch552and a second switch553coupled to a step capacitor554. In certain examples, the first switch552can be coupled between a reference voltage generator555and the step capacitor554and the second switch553can be coupled between the step capacitor554and a reference capacitor503. In certain examples, the first and second switches552,553alternately open and close such that in a first configuration or phase the step capacitor554is charged from the reference voltage generator555and in a second configuration or phase the step capacitor554charges the reference capacitor503to ramp the target voltage across the reference capacitor503up to a desired voltage level. In certain examples, the voltage across the reference capacitor503can provide a target voltage, or boost set point, for the boost converter and can be incrementally increased from a value representative of the input voltage (VIN) to a value representative of the desired output voltage (VOUT) after a start-up interval of the boost converter. In certain examples, the target voltage can ramp up logarithmically. Upon providing a step increase to the target voltage, the comparator550can disable the clock generator until the boost action of the converter boosts the output voltage, and the representation of the output voltage from a voltage divider502approaches the target voltage.

FIGS. 6A and 6Billustrate a comparison of current and voltage waveforms of an example linear current generator and a standard current mirror during start-up of a boost converter.FIG. 6Aillustrates the voltage waveforms601,602at the output of a boost controller using a standard current mirror601and an example linear current generator602.FIG. 6Billustrates current waveforms603,604and includes a first current waveform603associated with a standard current mirror and a second current waveform604associated with an example linear current generator as described above. In certain examples, the example linear current generator can reduce peak current at the beginning of the start up of a boost converter and can provide more current to raise the output voltage as the output voltage approaches the input voltage, compared to the standard current mirror.

FIG. 7illustrates waveforms associated with an example start-up circuit of a boost converter. A first waveform701illustrates the input voltage to the example start-up circuit of the boost converter. A second waveform702illustrates the output voltage of the example start-up circuit of the boost converter. A third waveform703illustrates a target voltage of the example start-up circuit of the boost converter. The combined waveforms illustrate the linear current start-up704and the stepped705target voltage and output voltage of the boost mode associated with an example start-up circuit as described above.

Additional Notes

In Example 1, a start-up circuit for a voltage converter can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter. In certain examples, the linear current generator can include a modified current mirror and a feedback circuit. In certain examples, the modified current mirror can include a first adjustable current source, and a second adjustable current source. In certain examples, the feedback circuit can be configured to provide a first representation of an output voltage of the output terminal to an input of each of the first and second adjustable current sources.

In Example 2, the modified current mirror of Example 1 optionally includes a first sense transistor coupled to the supply terminal, a first mirror transistor having a gate coupled to a gate of the first sense transistor, the first mirror transistor coupled to the supply terminal and the output terminal, a second sense transistor coupled in series with the first mirror transistor and the second adjustable current source, and coupled to the output terminal, and a second mirror transistor having a gate coupled to a gate of the second sense transistor, the second mirror transistor coupled in series with the first sense transistor, wherein the gate of the first sense transistor is coupled to a drain of the second mirror transistor and the first adjustable current source.

In Example 3, the start-up circuit of any one or more of Examples 1-2 optionally includes a reference capacitor configured to provide a boost set point for a boost converter, and a sampling switch configured to selectively couple a second voltage representative of the output voltage to the reference capacitor.

In Example 4, the start-up circuit of any one or more of Examples 1-3 optionally includes an adaptive reference circuit configured to step up a reference voltage of the voltage converter. In certain examples, the adaptive reference circuit can include a step circuit configured to adjust a voltage of the reference capacitor responsive to first and second clock signals, a comparator configured to compare the voltage of the reference capacitor to the second voltage representative of the output voltage, and a clock generator configured to receive an output of the comparator and to generate the first and second clock signals.

In Example 5, the step circuit of any one or more of Examples 1-4 optionally includes a step capacitor, a first step switch configured to couple a set point voltage to the step capacitor during a first state of the first clock signal, and a second step switch configured to respond to the second clock signal, the second step switch configured to couple the step capacitor to the reference capacitor during a first state of the second clock signal.

In Example 6, the first step switch of any one or more of Examples 1-5 optionally is configured to isolate the set point voltage from the step capacitor during a second state of the first clock signal.

In Example 7, the second step switch of any one or more of Examples 1-6 optionally is configured to isolate the step capacitor from the reference capacitor during a second state of the second clock signal.

In Example 8, a method of starting a voltage converter can include receiving an input voltage at an input terminal of the voltage converter, coupling the input terminal to an output terminal of the voltage converter using a modified current mirror, receiving an indication of an output voltage of the voltage converter at first and second current sources of the modified current mirror, and adjusting the first and second current sources to limit a startup charging current of the voltage converter until the output voltage is substantially equal to the input voltage.

In Example 9, the method of any one or more of Examples 1-8 optionally includes selectively coupling a second voltage representative of the output voltage to a reference capacitor, and providing a boost set point to a boost converter using a voltage of the reference capacitor.

In Example 10, the method of any one or more of Examples 1-9 optionally includes comparing the voltage of the reference capacitor to the second voltage representative of the output voltage, generating first and second clock signals using the comparison of the voltage of the reference capacitor and the second voltage representative of the output voltage, and incrementing the voltage of the reference capacitor using the first and second clock signals.

In Example 11, the incrementing the voltage of the reference capacitor of any one or more of Examples 1-10 optionally includes receiving the first clock signal at a first step switch, receiving the second clock signal at a second step switch, coupling a set point voltage to a step capacitor during a first state of the first clock signal using the first step switch, and coupling the step capacitor to the reference capacitor during a first state of the second clock signal using the second step switch.

In Example 12, the method of any one or more of Examples 1-2 optionally includes isolating the set point voltage from the step capacitor during a second state of the first clock signal.

In Example 13, the method of any one or more of Examples 1-2 optionally includes isolating the step capacitor from the reference capacitor during a second state of the second clock signal.

In Example 14, a voltage converter can include a boost converter configured to receive an input voltage and to provide a predetermined output voltage that is higher than the input voltage, and a start-up circuit configured to raise an output voltage to substantially equal the input voltage during a start-up interval of the voltage converter before the boost converter is enabled. In certain examples, the start-up circuit can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter, and a feedback circuit. In certain examples, the linear current generator can include a modified current mirror including a first adjustable current source and a second adjustable current source. IN some examples, the feedback circuit can be configured to provide a first representative of an output voltage of the output terminal to an input of each of the first and second adjustable current sources.

In Example 15, the startup circuit of Example 14 optionally is configured to limit a charging current of the voltage converter during the start-up interval using the linear current generator, to provide a sample of the output voltage as a boost set point during the start-up interval, and to incrementally raise the boost set point to a predetermined level associated with the predetermined output voltage after the boost converter is enabled.

In Example 16, the modified current mirror of any one or more of Examples 14-15 optionally includes a first sense transistor coupled to the supply terminal, a first mirror transistor having a gate coupled to a gate of the first sense transistor, the first mirror transistor coupled to the supply terminal and the output terminal, a second sense transistor coupled in series with the first mirror transistor and the second adjustable current source, and coupled to the output terminal, and a second mirror transistor having a gate coupled to a gate of the second sense transistor, the second mirror transistor coupled in series with the first sense transistor, wherein the gate of the first sense transistor is coupled to a drain of the second mirror transistor and the first adjustable current source.

In Example 17, the voltage converter of any one or more of Examples 14-16 optionally includes a reference capacitor configured to provide a boost set point for a boost converter, and a sampling switch configured to selectively couple a second voltage representative of the output voltage to the reference capacitor.

In Example 18, the voltage converter of any one or more of Examples 14-17 optionally includes an adaptive reference circuit configured to step up a reference voltage of the voltage converter. In certain examples, the adaptive reference circuit can include a step circuit configured to adjust a voltage of the reference capacitor responsive to first and second clock signals, a comparator configured to compare the voltage of the reference capacitor to the second voltage representative of the output voltage, and a clock generator configured to receive an output of the comparator and to generate the first and second clock signals.

In Example 19, the step circuit of any one or more of Examples 14-18 optionally includes a step capacitor, a first step switch configured to couple a set point voltage to the step capacitor during a first state of the first clock signal, and a second step switch configured to respond to the second clock signal, the second step switch configured to couple the step capacitor to the reference capacitor during a first state of the second clock signal.

In Example 20, the first step switch of any one or more of Examples 14-19 optionally is configured to isolate the set point voltage from the step capacitor during a second state of the first clock signal, and the second step switch of any one or more of Examples 14-19 optionally is configured to isolate the step capacitor from the reference capacitor during a second state of the second clock signal.

Example 21 can include, or can optionally be combined with any portion or combination of any portions of any one or more of Examples 1 through 20 to include, subject matter that can include means for performing any one or more of the functions of Examples 1 through 20, or a machine-readable medium including instructions that, when performed by a machine, cause the machine to perform any one or more of the functions of Examples 1 through 20.