Dynamic power control of a memory device thermal sensor

Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.

TECHNICAL FIELD

Embodiments of the invention generally relate to the field of integrated circuits and, more particularly, to systems, methods and apparatuses for the dynamic power control of a memory device thermal sensor.

BACKGROUND

Memory is frequently packaged on modules that contain several similar (or identical) integrated circuits such as dynamic random access memory (DRAM) devices. The temperature of a DRAM is largely determined by its activity level (e.g., the rate of reads and writes into the memory cells). If the temperature of the memory is too high, then the data stored in the memory may be corrupted or lost. In addition, the memory may be damaged by excessively high temperatures. Also, the thermal constraints of memory devices may limit the maximum data access rates that memory device interfaces can support.

On-die thermal sensors may be used to collect DRAM thermal data. In some systems, each DRAM may include an on-die thermal sensor to collect thermal data and to provide the collected thermal data to, for example, a memory controller. The on-die thermal sensors may be capable of triggering an event when a preprogrammed thermal threshold is reached.

In conventional systems, the on-die thermal sensors are powered on whenever the system is powered on. Since the on-die thermal sensors are always on, they are constantly consuming power. The constant consumption of power may deplete battery supplied power (e.g., in mobile applications) and may generate heat that needs to conducted away from the platform.

DETAILED DESCRIPTION

Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device power sensor. In some embodiments, a memory device includes an on-die thermal sensor and control logic to dynamically enable or disable the on-die thermal sensor. A host (e.g., a memory controller) dynamically enables or disables the thermal sensor. The amount of power consumed by the thermal sensor may be reduced because it can be dynamically disabled. As is further discussed below, the host may delay the issuance of a command to sense thermal data until the thermal sensor is ready to take an accurate reading.

FIG. 1is a high-level block diagram illustrating selected aspects of a computing system implemented according to an embodiment of the invention. System100includes processor(s)110, memory module120, and memory controller130. Processor(s)110may be any processing element including, for example, a central processing unit, an embedded processor, a partitioned processor, a multicore processor, and the like.

Memory module120includes memory devices122-128. For ease of illustration, four memory devices are shown. It is to be appreciated that embodiments of the invention may include more memory devices or fewer memory devices. Memory devices122-128may be any of a wide variety of memory devices including, for example, DRAMs, synchronous DRAMs (SDRAMs), and the like.

In some embodiments, each memory device122-128includes a corresponding on-die thermal sensor140-148. The term “on-die” refers to the disposition of a thermal sensor onto the same die as a corresponding integrated circuit (e.g., the same die as a DRAM). An on-die thermal sensor may be any of a wide range of on-die thermal sensors including, for example, a thermal diode. On-die thermal sensors140-148sense thermal data associated with memory devices122-128. The term “thermal data” broadly refers to information that provides an indication of device temperature. The term “thermal data” may also include information that indicates whether one or more temperature thresholds have been crossed.

In the illustrated embodiment, each memory device122-128also includes corresponding enable logic160-166and storage elements170-176. Enable logic160-166includes logic to dynamically enable and/or disable corresponding thermal sensors140-148. Enabling a thermal sensor includes powering on the thermal sensor. Similarly, disabling a thermal sensor includes powering off the thermal sensor. Enabling logic160-166may be implemented using almost any kind of logic suitable for enabling and/or disabling an on-die thermal sensor. An example of enabling logic160-166is further discussed below with reference toFIGS. 2-4.

As shown inFIG. 1, each memory device122-128may also include a corresponding storage element170-176. Storage elements170-176may store thermal data for corresponding thermal sensors140-148. In some embodiments, for example, the thermal sensors140-148sense the thermal data and then pass the thermal data to storage elements170-176. Storage elements170-176may be registers, collections of registers, and/or portions of registers. In some embodiments, storage elements170-176are DRAM multipurpose registers (MPRs).

In alternative embodiments, only a selected subset of memory devices122-128includes an on-die thermal senor140-148and/or enable logic160-166. For example, in some embodiments, every Nth (e.g., second, third, fourth, etc.) memory device may have an on-die thermal sensor and associated toggle logic. Alternatively, at least one memory device on each side of memory module120may include an on-die thermal sensor and associated toggle logic. In yet other embodiments, at least one memory device on memory module120includes an on-die thermal sensor and associated toggle logic.

Memory controller130provides an interface between processor110and memory module120. In some embodiments, memory controller130includes thermal throttles132, thermal sensor (TS) control logic134, and delay value136. In some embodiments, thermal throttles132provide thermal control mechanisms for module120and/or memory devices122-128. For example, thermal throttles132may limit the rate of reads and writes to memory devices122-128. TS control logic134controls thermal sensors140-148. For example, TS control logic134may include logic to control when thermal sensors140-148sense thermal data. In some embodiments, sensing thermal data, includes enabling a thermal sensor and, after an appropriate delay, instructing the thermal sensor to sense thermal data. The reason for the delay between enabling a sensor and sensing data is that, in some embodiments, a sensor setup time is appropriate so that a recently enabled sensor can stabilize itself before it takes a reading.

In some embodiments, storage element136stores the delay value138. Storage element136may be any element suitable for storing a value including, for example, a register, a collection of registers, and/or a portion of a register. Delay value138specifies a delay between when a memory device is enabled and when the thermal sensor is triggered to sense thermal data. In some embodiments, delay value138may be a fixed value that is written to storage element136by Basic Input/Output System (BIOS)180during, for example, system boot up. In other embodiments, delay value138is programmable. In such embodiments, storage element136may be, for example, a programmable register.

Memory interconnect150couples memory module120with memory controller130. In some embodiments, memory interconnect150is a multi-drop bus. In alternative embodiments, memory interconnect150is a serial interconnect.

FIG. 2is a block diagram showing selected aspects of a memory device200. Memory device200includes enable logic202and thermal sensor214. In some embodiments, enable logic202provides logic to dynamically power-on and power-off thermal sensor214. Enable logic202may include storage element204and enable circuit206. Storage element204stores enable indication208which may be received from a controller such as memory controller130shown inFIG. 1. In some embodiments, enable indication208is a signal (e.g., a command, an instruction, a bit, a collection of bits, etc.) from the controller instructing enable logic202to dynamically power-on or power-off thermal sensor214. For example, in some embodiments, enable indication208is value of a mode register (MR) bit (or bits) such as MR3. Enable circuit206includes logic to power-on/off thermal sensor214. In some embodiments, enable circuit206provides enable signal210to thermal sensor214.

In some embodiments, thermal sensor214senses thermal data after an appropriate delay time has expired. As discussed above, the purpose of the delay time is to allow thermal sensor214to stabilize before it takes a reading. Thus, the length of the delay time may depend on the set-up period of a thermal sensor. In some embodiments, the controller sends thermal data sense indication212after the delay time has expired. Thermal data sense indication212may be any signal (e.g., command, instruction, bit, collection of bits, etc.) suitable for triggering thermal sensor214to take a measurement. In some embodiments, the thermal data sense indication212is a memory interconnect impedance calibration command such as the ZQ calibration command used in double data rate (DDR) 3 technology. The memory interconnect impedance calibration period provides a quiet time in the memory device operation when (almost) no other memory device activity is occurring. The power supplies are relatively quiet during this time which makes it a suitable time for the temperature sensor to make a measurement (e.g., sense thermal data).

FIG. 3is a timing diagram illustrating selected aspects of the dynamic power control of a memory device, implemented according to an embodiment of the invention. Signal302illustrates a thermal sensor enable signal (TSE) and signal304illustrates the DRAM operation (e.g., from the perspective of the DRAM command bus). Initially, the TSE is de-asserted and the DRAM is performing normal operations (e.g., read, write, etc.) as shown by reference number306. The host (e.g., memory controller130, shown inFIG. 1) issues an MRS command at308. The MRS command includes an enable indication (e.g., a bit having an appropriate value) to power-on a thermal sensor. The enable indication is a bit (or bits) having a value that enables or disables the thermal sensor. In response to the enable indication, the TSE is asserted (310).

In some embodiments, the command bus resumes normal operation for a specified period of time (e.g., a delay time) so that the thermal sensor can stabilize before it takes a reading. In the illustrated embodiment, tTSPU is the delay time between when the thermal sensor is enabled and when the thermal sensor senses thermal data. In some embodiments tTSPU is part of a specification (e.g., a signaling specification). The value of tTSPU may be determined by the actual circuit requirements. In general, the value of tTSPU may be less than the period between temperature readings which, in the illustrated embodiment, is approximately 128 milliseconds (314).

In some embodiments, the host issues a thermal data sense indication after the specified delay time has transpired. For example, in the illustrated embodiment, the host issues a ZQ calibration command at316. The DRAM includes logic (e.g., enable logic202, shown inFIG. 2) to determine that the TSE signal is asserted and the ZQ calibration command has been issued. In some embodiments, the DRAM may attempt to sense the thermal data on every ZQ calibration command and the data but the data may not be valid unless the thermal sensor has been enabled for at least a tTSPU. In alternative embodiments, the thermal data sense indication is a different event such as a read command, a write command, or a dedicated signal.

After the ZQ calibration command, normal DRAM operations may occur (318). At an appropriate point in time, the host reads the thermal data and powers-down the thermal sensor. For example, in the illustrated embodiment, the host issues an MRS command at320. This MRS command includes a bit to disable the thermal sensor and a bit to place the DRAM in a multipurpose register (MPR) read mode. In response, the TSE signal de-asserts at322. The host reads the multipurpose registers at324. The host may return the DRAM to normal operation at326. It is to be appreciated that the sequence shown inFIG. 3may be (wholly or substantially) repeated each time the host determines that it is appropriate for the thermal sensor to sense thermal data.

FIG. 4is a flow diagram illustrating selected aspects of a method for the dynamic power control of a memory device according to an embodiment of the invention. Referring to reference number402, a memory device (e.g., a DRAM) receives an enable indication from a host such as a memory controller. The term “enable indication” refers to any signal, command, instruction, and the like from the host having the purpose of powering-on the thermal sensor. In some embodiments, the enable indication is one or more bits of a mode register set (MRS) command. For example, in some embodiments, the enable indication is the value of the MR3 bit.

Referring to process block404, the memory device receives a thermal data sense indication from the host. The term “thermal data sense indication” refers to any signal, instruction, command, and the like to trigger the thermal sensor to take a temperature reading. In some embodiments, an existing event is used to provide the thermal sense indication so that logic to provide a new command need not be added to the host. For example, in some embodiments, a memory interconnect impedance calibration command is used to provide the thermal data sense indication. This helps to ensure that the temperature measurement occurs when there is almost no memory device activity to interfere with the measurement.

The “delay period” refers to a delay between when the thermal sensor is enabled and when the temperature measurement is triggered. This delay period may provide sufficient time for the thermal sensor to stabilize so that it can take an accurate reading. In some embodiments, the signaling specification for the memory device may include a specification for the delay period (e.g., tTSPU as shown inFIG. 3).

After being enabled and having received the thermal data sense indication, the thermal sensor measures a temperature at406. The thermal sensor passes the data to a storage element (e.g., storage elements170-176) at408. The storage element may be, for example, a register, a collection of registers, or a portion of a register. In some embodiments, the storage element is one or more bits of a multipurpose register (MPR).

Referring to process block410, the memory device receives an indication to enter a register read mode. This indication may be any signal, command, instruction, value, and the like that indicates that the host is going to read a storage element (e.g., one or more registers) of the memory device. For example, in some embodiments, the indication is a value of one or more bits of an MRS command.

Referring to process block412, the memory device receives an indication to disable the thermal sensor. The indication to disable the thermal sensor may be any signal, command, instruction, value, and the like that indicates that the host is disabling the thermal sensor. In some embodiments, the indication to disable the thermal sensor is a value of one or more bits of an MRS command.

In some embodiments, two or more indications may be provided by the same command. For example, in some embodiments, the indication to enter the register read mode and the indication to disable the thermal sensor are both provided by bit values of a single MRS command. In other embodiments, the indications may be provided by different commands, signals, values, instructions, and the like.

Referring to process block414, the memory device provides the thermal data to the host. In some embodiments, providing the thermal data to the host includes the host reading one or more multipurpose registers of the memory device. In some embodiments, the host performs a memory read, while the memory device is in a register read mode, to read the multipurpose purpose registers containing the thermal data. In some embodiments,

FIG. 5is a block diagram illustrating selected aspects of an electronic system according to an embodiment of the invention. Electronic system500includes processor510, memory controller520, memory530, input/output (I/O) controller540, radio frequency (RF) circuits550, and antenna560. In operation, system500sends and receives signals using antenna560, and these signals are processed by the various elements shown inFIG. 5. Antenna560may be a directional antenna or an omni-directional antenna. As used herein, the term omni-directional antenna refers to any antenna having a substantially uniform pattern in at least one plane. For example, in some embodiments, antenna560may be an omni-directional antenna such as a dipole antenna or a quarter wave antenna. Also, for example, in some embodiments, antenna560may be a directional antenna such as a parabolic dish antenna, a patch antenna, or a Yagi antenna. In some embodiments, antenna560may include multiple physical antennas.

Radio frequency circuit550communicates with antenna560and I/O controller540. In some embodiments, RF circuit550includes a physical interface (PHY) corresponding to a communication protocol. For example, RF circuit550may include modulators, demodulators, mixers, frequency synthesizers, low noise amplifiers, power amplifiers, and the like. In some embodiments, RF circuit550may include a heterodyne receiver, and in other embodiments, RF circuit550may include a direct conversion receiver. For example, in embodiments with multiple antennas560, each antenna may be coupled to a corresponding receiver. In operation, RF circuit550receives communications signals from antenna560and provides analog or digital signals to I/O controller540. Further, I/O controller540may provide signals to RF circuit550, which operates on the signals and then transmits them to antenna560.

Processor(s)510may be any type of processing device. For example, processor510may be a microprocessor, a microcontroller, or the like. Further, processor510may include any number of processing cores or may include any number of separate processors.

Memory controller520provides a communication path between processor510and other elements shown inFIG. 5. In some embodiments, memory controller520is part of a hub device that provides other functions as well. As shown inFIG. 5, memory controller520is coupled to processor(s)510, I/O controller540, and memory530.

Memory530may include multiple memory devices. These memory devices may be based on any type of memory technology. For example, memory530may be random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), nonvolatile memory such as FLASH memory, or any other type of memory. Memory530may represent a single memory device or a number of memory devices on one or more modules. In some embodiments, at least one of the memory devices includes an on-die thermal sensor and associated enable logic532. Enable logic532supports the dynamic power control of the thermal sensor.

Memory controller520provides data through interconnect522to memory530and receives data from memory530in response to read requests. Commands and/or addresses may be provided to memory530through interconnect522or through a different interconnect (not shown). Memory controller530may receive data to be stored in memory530from processor510or from another source. Memory controller520may provide the data it receives from memory530to processor510or to another destination. Interconnect522may be a bi-directional interconnect or a unidirectional interconnect. Interconnect522may include a number of parallel conductors. The signals may be differential or single ended. In some embodiments, interconnect522operates using a forwarded, multiphase clock scheme. In some embodiments, memory controller520includes thermal sensor control logic (not shown) to dynamically control one or more thermal sensors.

Memory controller520is also coupled to I/O controller540and provides a communications path between processor(s)510and I/O controller540. I/O controller540includes circuitry for communicating with I/O circuits such as serial ports, parallel ports, universal serial bus (USB) ports and the like. As shown inFIG. 5, I/O controller540provides a communication path to RF circuits550.

FIG. 6is a bock diagram illustrating selected aspects of an electronic system according to an alternative embodiment of the invention. Electronic system600includes memory530, I/O controller540, RF circuits550, and antenna560, all of which are described above with reference toFIG. 5. Electronic system600also includes processor(s)610and memory controller620. As shown inFIG. 6, memory controller620may be on the same die as processor(s)610. Processor(s)610may be any type of processor as described above with reference to processor510. In some embodiments, memory controller620includes thermal sensor control logic (not shown) to dynamically control one or more thermal sensors. Example systems represented byFIGS. 5 and 6include desktop computers, laptop computers, servers, cellular phones, personal digital assistants, digital home systems, and the like.

Elements of embodiments of the present invention may also be provided as a machine-readable medium for storing the machine-executable instructions. The machine-readable medium may include, but is not limited to, flash memory, optical disks, compact disks-read only memory (CD-ROM), digital versatile/video disks (DVD) ROM, random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, propagation media or other type of machine-readable media suitable for storing electronic instructions. For example, embodiments of the invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).