System and method for recycling energy of static random-access memory (SRAM) write circuit

A circuit for recycling energy in bit lines (BL and BLB) of SRAM during write operation by (i) storing the charges BL and BLB to an intermediate voltage source (VLB) in a discharge phase and (ii) restoring the charges from the intermediate voltage, back to the BL or BLB in a recovery phase. The circuit includes an inductor, a pair of NMOS transistors, a series resonance node, and an energy source (VLB) in addition to the components of an SRAM input-output circuit shown as in FIG. 1. During the SRAM write operation, the BL or BLB is discharged to the energy source VLB through the pair of NMOS transistors and, the inductor and the series resonance node. The remaining energy in the BL and the BLB is discharged to ground using the write complementary write drivers.

BACKGROUND

Technical Field

The embodiments herein generally relate to an energy recycling in System On Chip (SOC), and more particularly, to a system and method for recycling the energy of a Static Random Access Memory (SRAM) circuit of the SOC during multi-voltage level SRAM write operations using magnetic fields.

Description of the Related Art

Modern electronic devices such as a notebook computer comprise a variety of memories to store information. Memory circuits include two major categories. One of such categories is volatile memories and the other is non-volatile memories. The volatile memories include random access memory (RAM), which can be further divided into two sub-categories, a static random access memory (SRAM) and a dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they may lose information that they store when they are not powered. On the other hand, the non-volatile memories can keep data stored on them.

A typical static random access memory (SRAM) cell includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary value therein, which value represents a logical data bit logic ‘1’ or a logic ‘0’. SRAM cells may include different numbers of transistors. According to the total number of transistors in the SRAM cell, the SRAM cell may be referred to as a six-transistor (6-T) SRAM, an eight-transistor (8-T) SRAM, and the like. The SRAM cells are arranged in rows and columns. The SRAM cell is selected during either a READ operation or a WRITE operation by selecting its row and column. The row and column to be selected are determined by a binary code. For example, a 64 Kb (64K Words, each word of N-bit) memory chip comprises a 16-bit binary code (address input) used to select a respective word for READ and WRITE operation.

Each column of SRAM Array is connected to both a bit-line (BL) and the inverse of BL (BLB). The SRAM cell is used to store a single bit. Both BL and BLBare used to control the operation of reading a bit from or writing a bit into the SRAM cell.

An SRAM write cycle begins by applying the data bits to be written on the data bus (Din). If a user wishes to write logic ‘0’, the user would apply a logic' 0 to the Din which in turn the IO circuit places onto bit lines, i.e. setting Bit Line (BL) to ‘0’ and Bit Line bar (BLB) to ‘1’. A logic 1 is written by placing logic 1 to Din and inverting BL and BLB.

FIG.1illustrates an exemplary commercial SRAM circuit diagram to perform a write operation (PRIOR ART). The SRAM input-output circuit102is connected with a pair of bit lines that include a Bit Line (BL)104A and a Bit Line bar (BLB)104B. The SRAM input-output circuit102includes a pre-charge circuit106, a set of Multiplexer (MUX) NMOS transistors108A and108B, complimentary write drivers110A,110B,110C and110C-D, a global control unit112, a Bit Line Pre-Charge (BLPC) signal114, a Multiplexer selection (MUXSEL) signal116, a Write Clock (WRCL) signal118, a latch124and inputs120A and120B (D and DB) that is driven by Din126A.

During the write operation of the SRAM, the BL104A or the BLB104B (high capacitive load) is discharged to logic ‘0’ through a ground node130based on Din polarity. The MUX NMOS transistors108A and108B are connected between the pair of bit lines (i.e. BL104A and BLB104B) and the complimentary write drivers110A,110B,110C and110D. The complementary write drivers110A,110B,110C and110D are operated based on the inputs D120A and the DB120B that are received from the latch124. The inputs D120A and DB120B may be generated by latching the data input Din126. The inputs D120A and DB120B are provided to the SRAM input-output circuit102to operate the complimentary write drivers110A,110B,110C and110D. The pre-charge circuit106is connected to the bit lines BL104A and BLB104B that pre-charge the BL104A and the BLB104B back to supply voltage level (i.e. VDD) after the write operation. Pre-charging the number of bit lines back to VDDmay consume an immense amount of dynamic power in SRAM.

The SRAM input-output circuit102is electrically connected with the global control unit112for obtaining timing control signals. The global control unit112includes a logic circuitry and output buffers to drive the timing control signals to a number of SRAM input-output circuits of the SRAM. The SRAM may include more than one SRAM input-output circuits. The global control unit112provides the timing control signals to the SRAM input-output circuit102for performing the write operation. The timing control signals may include the Bit Line Pre-Charge (BLPC) signal114, the Multiplexer selection (MUXSEL) signal116and the Write Clock (WRCL) signal118. The BLPC signal114may carry timing information to the pre-charge circuit106for pre-charging the BL104A or the BLB104B to a VDDvoltage level. The MUXSEL signal116may carry an address decoded signal to turn ON the set of MUX NMOS transistors108A and108B. The WRCL signal118may serve as a latch clock and gating clock for the inputs D120A and DB120B to provide the timing information of write enable to the complementary write drivers110A,110B,110C and110D. The timing information is carried by the WRCL signal118that reaches the complimentary write drivers110A,110B,110C and110D through the inputs D120A and DB120B.

During the write operation, the energy of BL104A or the BLB104B is discharged to the ground through (i) the MUX NMOS transistor108A and108B and (ii) the complementary write drivers110A,110B,110C and110D. At the end of the SRAM write operation, the pre-charge circuit106is charged back the BL104A and the BLB104B to the supply voltage (VDD) for the next operation. The pre-charge circuit106consumes significant energy from the SRAM supply voltage (VDD) to charge the BL104A and the BLB104B at the end of the SRAM write operation for the next operation. One of the major power-consuming elements in SOC is SRAM because, during the write operation, each SRAM input-output circuit102consumes dynamic significant dynamic power as all the bit lines with high capacitive load discharges during the write operation and charges back to VDDthrough the pre-charge circuit106.

One of the major power-consuming elements in SRAM is the write operation as all the bit lines with high capacitive load discharges during a write operation and need to be charged back in the recovery phase. Accordingly, there remains a need for a circuit and method for effectively recycling the energy of SRAM input-output circuits during SRAM write operation.

SUMMARY

Embodiments herein provide a circuit for recycling energy of a Static Random Access Memory (SRAM) circuit of a System-on-Chip (SOC) during multi-voltage level SRAM operations using magnetic fields. The circuit includes a pair of bit lines, a pre-charge circuit, MUX NMOS transistors, complementary write drivers, a global control unit, a local control unit, a pair of NMOS transistors and an inductor. The pair of bit lines includes a Bit Line (BL) and a Bit Line bar (BLB). The pre-charge circuit is connected to the pair of bit lines and to pre-charge the pair of bit lines and to a supply voltage level (VDD). The MUX NMOS transistors and that are connected with the pair of bit lines. The complementary write drivers are connected with the pair of bit lines and through the MUX NMOS transistors. The global control unit provides control signals with determined timing signals to discharge and charge the energy at the pair of bit lines. The local control unit generates timing sequence control signals for charging and discharging the pair of bit lines in a determined timing sequence. The pair of NMOS transistors are connected with the complementary write drivers, the MUX NMOS transistors and a series resonance node through a VL node to provide a path when the energy discharge from and chargeback to the pair of bit lines and during the SRAM operation. The inductor is connected between the series resonance node and an energy source (VLB). The Bit Line (BL) and the Bit Line bar (BLB) are charge or discharge based on a data input (Din) when SRAM operation. The complementary write drivers and the MUX NMOS transistors act as paths to discharge the pair of bit lines to a ground level (‘0’) using a ground. Along with the pair of NMOS transistors and the complementary write driver, the inductor, the series resonance node and the energy source (VLB) forms a series resonance circuit to discharge the energy from the pair of bit lines. The pair of bit lines are discharged to the energy source VLBthrough the pair of NMOS transistors, the inductor, and the series resonance node during the SRAM operation.

In some embodiments, the energy of the pair of bit lines is discharged in a discharge phase. The discharge phase includes a first phase and a second phase. In the first phase, the energy from the pair of bit lines are discharged, at the energy source VLB, less than the supply voltage (VDD) and greater than the ground (‘0’) through at least one of the MUX NMOS transistors, the pair of NMOS transistors, the complementary write drivers or the series resonance node. In the second phase, the remaining energy in the pair of bit lines is discharged to the ground level through the complementary write drivers.

In some embodiments, the energy of the pair of bit lines chargeback in a recovery phase. In the recovery phase, the pair of bit lines are charged to VDDusing the energy source VLBand the pre-charge circuit at the end of the SRAM operation.

In some embodiments, the recovery phase includes a first phase and a second phase. In the first phase, the pair of bit lines are charged to greater than the ground (‘0’) and less than the VDDusing the energy source VLB, the inductor and the series resonance node. In the second phase, the pair of bit lines are charged to VDDusing the pre-charge circuit. The pre-charge circuit charges the pair of bit lines based on a control signal BLPC that are provided from the global control unit.

In some embodiments, the timing sequence control signals provided from the local control unit include VSRB-D, VSRB-DB, VDN-D and VDN-DB. The local control unit provides the timing sequence control signals using global control signals S, the SD and the WRCL. The local control unit generates signals D and DBusing the global control signals. A MUX SEL signal is communicated to a cloud that generates a WSELBsignal. The WSELBsignal is latched to provide a WSEL signal to the MUX NMOS transistors. A discharge timing of the energy in the pair of bit lines is determined using the global control signals S and SD.

In some embodiments, the energy source VLBacts as a charge pool during the write operation of the SRAM that stores the energy greater than ground (‘0’) and less than the supply voltage (VDD). The pair of bit lines discharged to below the VDDand close to the ground and a remaining energy in the pair of bit lines is discharged to the ground using the complementary write drivers.

In some embodiments, a resonance inductor that is connected to each parallelly connected with one or more SRAM circuits. The resonance inductor comprises a lower inductance value and a lower effective ON resistance to achieve a high Q factor. The charging and discharging time of the pair of bit lines in a series resonance circuit is determined by resonance frequency.

In some embodiments, the circuit includes two pairs of PMOS transistors. The PMOS transistor is connected in parallel to the NMOS transistor that enables control of the damping of the circuit to achieve small effective ON resistance for high Q factor. The PMOS transistor receives logic low (‘0’) at a gate node as the PMOS transistor receives a VSRB-D signal from the local control unit for controlling the damping of the circuit when the NMOS transistor receives a logic high (‘1’) at a gate node. The PMOS transistor is connected in parallel to the MUX transistor to provide effective ON resistance.

In some embodiments, the PMOS transistor is connected in parallel to the NMOS transistor that enables control of the damping of the circuit to achieve small effective ON resistance for high Q factor. The PMOS transistor receives logic low (‘0’) at a gate node as the PMOS transistor receives a VSRB-DBsignal from the local control unit for controlling the damping of the circuit when the NMOS transistor receives a logic high (‘1’) at a gate node.

In some embodiments, the circuit includes a charge pump inductor that is connected between the supply voltage (VDD) and a VSRB-D drive and a VSRB-DB. A VSR-D signal goes high and turns on a series resonance path to charge and discharge the energy of the pair of bit lines using the energy source (VLB) during the SRAM operation when at least one of the VSRB-D or a VSRB-DBsignal is low based on a polarity of an input (D).

In some embodiments, the complementary write drivers provide the series resonance path to discharge the energy from the pair of bit lines during the SRAM operation when a VDN-D or a VDN-DBgoes high based on the polarity of the input D.

In some embodiments, the VSRB-D signal, the VSRB-DBsignal, the VDN-D signal and the VDN-DBsignal are generated from the local control unit based on the global signals provided from the global control unit.

In another aspect, a method for recycling energy of a Static Random Access Memory (SRAM) circuit of a System-on-Chip (SOC) during multi-voltage level SRAM operations using magnetic fields includes (i) charring a pair of bit lines to a supply voltage level (VDD) based on a data input (Din) when SRAM operation, (ii) providing control signals with determined timing signals to discharge and charge the energy at the pair of bit lines, (iii) generating timing sequence control signals for charging and discharging the pair of bit lines in a determined timing sequence and (iv) discharging the pair of bit lines to the energy source VLBbased on the data input (Din) through a pair of NMOS transistors, an inductor and a series resonance node during SRAM operation.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As mentioned, there remains a need for a circuit and a method for effectively recycling the energy during SRAM write operation.

The embodiments herein achieve this energy recycling by (i) storing the charges from Bit Line (BL) or Bit Line Bar (BLB) to an intermediate voltage source in a discharge phase and (ii) restoring the charges from the intermediate voltage, back to the BL or BLBin a recovery phase. Referring now to the drawings, and more particularly toFIG.2throughFIG.7, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.

Definition: The chargeback is that the Bit Line (BL) or Bit Line Bar (BLB) is returned to electric charge (VDD) using the energy source VLBand the pre-charge circuit at the end of the SRAM operation.

FIG.2illustrates a circuit200for recycling discharge energy of a SRAM input-output circuit102(as shown inFIG.1) to reduce power consumption during an SRAM write operation according to some embodiments herein. The circuit200includes an inductor202, a pair of NMOS transistors204A and204B, a series resonance node206and an energy source (VLB)208in addition to the components as shown in the SRAM input-output circuit102ofFIG.1. In some embodiments, the circuit200is configured in SRAM input-output circuit102ofFIG.1. The pair of NMOS transistors204A and204B are connected with the complementary write drivers110A,110B,110C and110D (as shown inFIG.1) and the series resonance node206through a VL node. The inductor202is connected between the series resonance node206and VLB208node. In some embodiments, the pair of NMOS transistors204A and204B, the complementary write drivers110A,110B,110C and110D, the inductor202, the energy source (VLB)208form a series resonance circuit to discharge the energy from the BL104A and BLB104B. The energy source (VLB)208may store energy greater than ground (0) and less than the supply voltage (VDD). In some embodiments, the energy source VLB208may at half of the supply voltage (i.e. VDD/2). In some embodiments, the pair of NMOS transistors204A and204B are LVT transistors that may provide a path along with the complementary write drivers110A,110B,110C and110D and the MUX NMOS transistors108A and108B when the energy discharge from and chargeback to BL104A and BLB104B during SRAM write operation. In some embodiments, the inductor202, the pair of NMOS transistors204A and204B, the series resonance node206and the energy source VLB208provide a series resonance path for charging and discharging the energy from the BL104A and BLB104B during the SRAM write operation.

During the SRAM write operation, the BL104A or BLB104B is discharged to the energy source VLB208through the pair of NMOS transistors204A and204B, the inductor202and the series resonance node206. In some embodiments, the energy from BL104A and104B are discharged to below the VDDand close to the ground, e.g. VDD/2. In some embodiments, remaining energy in the BL104A and the BLB104B is discharged to the ground using the complementary write drivers110B and110C. In some embodiments, the energy source VLB208acts as a charge pool during the write operation of the SRAM.

The global control unit112provides control signals with determined timing signals to discharge and charge the energy at BL104A and104B. In some embodiments, the energy is discharged in a discharge phase and chargeback in a recovery phase. In another embodiment, the discharge phase includes two phases, in the first phase, the energy from the BL104A and BLB104B is discharged, at the energy source VLB208, less than the supply voltage (VDD) and greater than the ground (0) through at least one of the MUX NMOS transistors108A and108B, the pair of NMOS transistors204A and204B, the complementary write drivers110A,110B,110C and110D or the series resonance node206. In the second phase, the remaining energy in the BL104A and the BLB104B is discharged to the ground through the complementary write drivers110B and110C. In some embodiments, the write operation of the SRAM is completed when the energy of the BL104A and BLB104B is fully discharged. The discharge timing of the energy in the BL104A and the BLB104B is determined using control signals S210and SD212. The BL104A and the BLB104B discharge full energy in the discharge phase and charges back in the recovery phase during the SRAM write operation. In the recovery phase, the BL104A and the BLB104B are charged to VDDusing the energy source VLB208and the pre-charge circuit106at the end of the SRAM write operation. In some embodiments, the recovery phase also includes two phases, in the first phase, the BL104A and BLB104B are charged to greater than the ground (0) and less than the VDD(i.e. VDD/2) using the VLB208, the inductor202and the series resonance node206. In the second phase, the BL104A and the BLB104B are charged to VDDusing the pre-charge circuit106. In some embodiments, the pre-charge circuit106charges the BL104A and the BLB104B based on the control signal BLPC114that is provided from the global control unit112.

The circuit200is electrically connected to a local control unit214that generates timing sequence control signals for charging and discharging the BL104A and BLB104B in a determined timing sequence. The timing sequence control signals include VSRB-D216A, VSRB-DB216B, VDN-D218A and VDN-DB218B. The local control unit214provides the timing sequence control signals using the control signals S210, the SD212and the WRCL118. In some embodiments, the control signals S210, the SD212and WRCL118are global control signals. The local control unit214generates signals D230A and DB230B using the global control signals. In some embodiments, the MUX SEL signal116is communicated to a cloud that generates a WSELBsignal222A. The WSELBsignal222A is latched to provide the WSEL signal222B to the MUX NMOS transistors108A and108B.

In some embodiments, the energy source VLB208is determined to store the intermediate voltage, e.g. VDD>VLB>ground. In another embodiment, the inductor202facilitates a higher amount of energy, hence a higher amount of energy is stored using the series resonance circuit. In some embodiments, without the resonance energy recovery architecture shown inFIG.2, the pre-charge circuit may charge the BL104A and the BLB104B from the ground and to the VDDwhich causes a higher energy consumption from the supply source.

With reference toFIG.2,FIG.3illustrates an exemplary circuit implementation for recycling discharge energy of the SRAM input-output circuits to reduce power consumption during the SRAM write operation according to some embodiments herein. The circuit200includes a resonance inductor302that is connected to each parallelly connected SRAM input-output circuits. The resonance inductor302includes lower inductance value and effective ON resistance to achieve a high Q factor. In some embodiments, the high operating frequency provides a high Q factor. The High capacitance load of the BL108A and the BLB108B requires lower inductance value to achieve higher operating frequency. In some embodiments, the charging and discharging time of the series resonance circuit is determined by resonance frequency (Fres), e.g.

FIG.4illustrates an alternative circuit configuration400to achieve a high Q factor by reducing series resistance of a series resonant path of the SRAM input-output circuit ofFIG.2during the SRAM write operation according to some embodiments herein. The alternative circuit configuration400includes two pairs of PMOS transistors402A,402B and404A,404B in addition to the components of the circuit200shown inFIG.2. In the discharge phase of the SRAM write operation, the NMOS transistor204A includes a voltage of VDDin a drain node of the NMOS transistor204A. The source node NMOS transistors204A includes a voltage of VLB208which causes the damping effective. The PMOS transistor402A is connected in parallel to the NMOS transistor204A that enables control of the damping of the circuit200to achieve small effective ON resistance for high Q factor. When the NMOS transistor204A receives a logic high that is ‘1’ at a gate node, the PMOS transistor402A receives logic low that is ‘0’ at a gate node because of the VSRB-D signal216A provided to the PMOS transistor402A from the local control unit214for controlling the damping of the circuit200. In some embodiments, the source-drain potential of the PMOS transistor402A is the same as the NMOS transistors204A. In some embodiments, the PMOS transistor404A and404B are connected in parallel to the MUX transistor108A and108B to achieve small effective ON resistance. In some embodiments, the PMOS transistor402B is connected in parallel with the NMOS transistor204B to perform a similar function for controlling the damping of the circuit200.

FIG.5illustrates an alternative circuit configuration500to achieve the high Q factor by increasing overdrive voltage to NMOS transistors in a series resonant path of the SRAM input-output circuit ofFIG.2according to some embodiments herein. The alternative circuit configuration500includes a charge pump inductor502that is connected between the supply voltage (VDD) and a VSRB-D drive504A and a VSRB-DB504B in addition of components of the circuit400shown inFIG.4. When either VSRB-D216A or VSRB-DB216B signal is low based on a polarity of the input D230A, the VSR-D218A signal goes high and turns on the series resonance path to charge and discharge the energy of the BL104A and the BLB104B using VLB208during the SRAM write operation. In some embodiments, the series resonance path is provided by at least one of the pair of NMOS transistor204A and204B, the complementary write drivers110A,110B,110C and110D, the series resonance node206. When the VDN-D220A or VDN-DB220B goes high based on the polarity of the input D230A, then the complementary write drivers110B or110D provides a path to discharge the energy from BL104A and BLB104B during the SRAM write operation. In some embodiments, the VSRB-D signal216A, the VSRB-DBsignal216B, the VDN-D signal220A and the VDN-DBsignal220B are generated from the local control unit214based on the global signals provided from the global control unit214.

FIG.6represents waveforms related to the SRAM input-output circuit ofFIG.2throughFIG.5for recycling discharge energy of SRAM input-output circuits to reduce power consumption during the SRAM write operation according to some embodiments herein. A set of waveforms, as depicted inFIG.6, shows the scenario where the energy discharged in a discharge phase from the BL104A and the BLB104B and stored to the VLB208and chargeback the BL104A and the BLB104B from the VLB208in a recovery phase. The set of waveforms shown in the graph includes at least one of external clock602, BLPC604, D608, MUX SEL610, WRCL612, S614, SD616, VSR-D618, VSR-DB620, VDN-D622, WSEL624or Bit lines (BL and BLB)626that are involved in the energy discharging and charging of the BL104A and the BLB104B as described inFIG.2,FIG.3, andFIG.4. A region V1628is an amount of charging of the BL104A and the BLB104B using the stored energy in the VLB208and a region V2630is an amount of charging of the BL104A and BLB104B using the supply voltage VDDusing the pre-charge circuit106.

With reference toFIG.2,FIG.7illustrates a method for recycling discharge energy of SRAM input-output circuit to reduce power consumption during an SRAM write operation according to some embodiments herein. At step702, the pair of bit lines104A and104B is charged to a supply voltage level (VDD) based on a data input (Din) when SRAM operation. At step704, control signals are provided with determined timing signals to discharge and charge the energy at the pair of bit lines104A and104B. At step706, timing sequence control signals are generated for charging and discharging the pair of bit lines104A and104B in a determined timing sequence. At step708, the pair of bit lines104A and104B is discharged to the energy source VLB208based on the data input (Din) through a pair of NMOS transistors204A and204B, an inductor202and a series resonance node206during SRAM operation.