Chip package structure using silicon interposer as interconnection bridge

A chip package structure using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a package structure, and more particularly, to a chip package structure using silicon interposer as interconnection bridge.

2. Description of the Prior Art

High level chips have been in increasing demand for product requirements like small size, high I/O count, high thermo performance, and low noise. Back-end processes such as packaging also follow the direction towards reducing the overall package size or integrating more functions in the same chip area and increase the I/O count. It is certainly a trendy development of IC to integrate two or more chips in one package known as multi-die packaging.

Modern technology of multi-die packaging packages two or more than two chips in one chip package by integration (horizontal placement) and/or stacking. As for the horizontal placement integration, conventional interconnection between chips is realized by the bottom substrate and redistribution layers (RDL), which have limitations on width/pitch ratio due to the manufacturing capability, thereby setting up the barrier to integration of multi-die structure. Inter-chip connection hence becomes costly and less efficient, for longer routes or more RDLs are needed. It is obvious that longer routes and/or more RDLs mean degeneration of SNR and performance of power consumption.

SUMMARY OF THE INVENTION

Therefore, the embodiments of the invention provide a chip package structure using silicon interposer as interconnection bridge to solve the above-mentioned problem.

According to an embodiment of the invention, a chip package structure using silicon interposer as interconnection bridge includes a fan-out package, a first semiconductor die, and a second semiconductor die. The fan-out package includes an interconnection bridge, a first connection wiring, and a second connection wiring. The interconnection bridge is embedded and packaged in a molding layer. The fan-out package has a bottom surface and a top surface opposite with each other. The first semiconductor die and the second semiconductor die are disposed and adjacent to each other on the top surface of the fan-out package. The first semiconductor die includes a plurality of first contacts and a plurality of second contacts, and the second semiconductor die includes a plurality of third contacts and a plurality of fourth contacts. The interconnection bridge is disposed correspondingly under the plurality of first contacts of the first semiconductor die and the plurality of third contacts of the second semiconductor die where the plurality of first contacts form inter-chip connection with the plurality of third contacts through the interconnection bridge. The fan-out package is disposed on the substrate via the bottom surface, and the plurality of second contacts and the plurality of fourth contacts are electrically connected to the substrate respectively through the first connection wiring and the second connection wiring.

According to the embodiment of the invention, the chip package structure further includes a first redistribution layer disposed on the top surface of the fan-out package. The first semiconductor die and the second semiconductor die are disposed on the first redistribution layer, and the plurality of second contacts and the plurality of fourth contacts are respectively connected to the first connection wiring and the second connection wiring through the first redistribution layer.

According to the embodiment of the invention, the chip package structure further includes a second redistribution layer disposed between the bottom surface of the fan-out package and the substrate. The second redistribution layer includes a plurality of contact pads. The plurality of second contacts and the plurality of fourth contacts are electrically connected to the substrate through the plurality of contact pads and respectively through the first connection wiring and the second connection wiring.

According to the embodiment of the invention, the first connection wiring and the second connection wiring are copper pillars or through molding via (TMV).

According to the embodiment of the invention, the interconnection bridge further electrically connects the substrate with at least part of the plurality of first contacts and at least part of the plurality of third contacts using through silicon via (TSV).

According to the embodiment of the invention, the interconnection bridge is a silicon interposer and is disposed partially in the molding layer, the silicon interposer is pre-made by silicon procedure before molding.

According to the embodiment of the invention, the minimum line width/line pitch ratio of the interconnection bridge is no greater than 1/1 micrometer.

According to the embodiment of the invention, the plurality of first contacts of the first semiconductor die and the plurality of third contacts of the second semiconductor die are fine pitch signal contacts. The pitch of the plurality of first contacts and the plurality of third contacts is no greater than 30 micrometers.

According to the embodiment of the invention, the plurality of second contacts of the first semiconductor die and the plurality of fourth contacts of the second semiconductor die are wide pitch power contacts or grounding contacts. The pitch of the plurality of second contacts and the plurality of fourth contacts is greater than 30 micrometers.

According to the embodiment of the invention, a protective molding layer is further disposed on the top surface of the fan-out package and covering the first semiconductor die and the second semiconductor die.

The chip package structure according to the embodiment of the invention lifts multi-dies allows easier multi-die integration or system in package (SiP) and the shortest connection route also improves the signal/consumption performance.

DETAILED DESCRIPTION

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. In the following discussion and in the claims, the terms “include” and “comprise” are used in an open-ended fashion. Also, the term “couple” is intended to mean either an indirect or direct electrical/mechanical connection. Thus, if a first device is coupled to a second device, that connection may be through a direct electrical/mechanical connection, or through an indirect electrical/mechanical connection via other devices and connections.

Please refer toFIG. 1.FIG. 1is an illustration showing cross sectional view of a first embodiment of the chip package structure using silicon interposer as interconnection bridge according to the invention. The chip package structure100according to the embodiment lifts the semiconductor dies above the fan-out package. In the first embodiment, the chip package structure100includes a fan-out package10and at least a first semiconductor die21and a second semiconductor die22. The fan-out package10includes an interconnection bridge20embedded and packaged in a molding layer13. The fan-out package10also includes a bottom surface18and a top surface19opposite with each other where the semiconductor dies are disposed on the top surface19and further disposed on a substrate50with the fan-out package10via the bottom surface18. The chip package structure according to the embodiment of the invention falls to the category of multi-die package structure, which integrates two or more than two dies in one package structure in horizontal placement. Besides the embodiment ofFIG. 1that the chip package structure100has the first semiconductor die21and the second semiconductor die22, the scope of the invention also covers chip package structures having more semiconductor dies. The first semiconductor die21and the second semiconductor die22are disposed and adjacent to each other on the top surface19of the fan-out package10. The first semiconductor die21and the second semiconductor die22can be hybrid bump design structure in such a way that the first semiconductor die21includes a plurality of first contacts211and a plurality of second contacts212and the second semiconductor die22includes a plurality of third contacts223and a plurality of fourth contacts224. In one embodiment, the plurality of first contacts211of the first semiconductor die21and the plurality of third contacts223of the second semiconductor die22are fine pitch signal contacts where the first contacts211and the third contacts223can be used as interconnection contacts between dies and preferably, but not limited to, the pitch of the first contacts211and the third contacts223is no greater than 30 micrometers. Additionally, an underfill24(UF) can further be disposed beneath the first semiconductor die21and the second semiconductor die22for improving the reliability of the contacts.

The interconnection bridge20made by advanced procedure is used for interconnection between the first semiconductor die21and the second semiconductor die22. In the first embodiment, silicon interposer with minimum line width/line pitch ratio no greater than 1/1 micrometer can be used as the interconnection bridge20, which is disposed partially in the molding layer13and is pre-made by silicon procedure before molding. The interconnection bridge20is disposed correspondingly under the plurality of first contacts211of the first semiconductor die21and the plurality of third contacts223of the second semiconductor die22in such a way that the plurality of fine-pitched first contacts211forms inter-chip connection with the plurality of fine-pitched third contacts223through the interconnection bridge20following the shortest route. As described earlier, the interconnection bridge20using silicon interposer provides minimum line width/line pitch ratio smaller than 1/1 micrometer, and therefore high I/O connection between chips can be realized without excessive routing or redistribution. It should be noted that one interconnection bridge20connecting two semiconductor dies in the embodiment should not be a limitation to the invention, and two or more interconnection bridges20can be placed in one fan-out package10as interconnection bridges of two or more semiconductor dies atop.

Please keep referring toFIG. 1. The first semiconductor die21the second semiconductor die22further have wide pitch (for example greater than 30 micrometers, but not limited to) plurality of second contacts212and plurality of fourth contacts224respectively, which may be signal contacts, power contacts, or grounding contacts with wide I/O pitch. Hence, the first semiconductor die21and the second semiconductor die22come with, but not limited to, hybrid bump design. These signal contacts with larger pitch are electrically connected to the substrate50respectively through a first connection wiring11and a second connection wiring12of the fan-out package10. In one embodiment, the plurality of second contacts212and the plurality of fourth contacts224are connected to the substrate50through the fan-out redistribution structure of the fan-out package10.

For example, the chip package structure100can further include a first redistribution layer30and a second redistribution layer40. The first redistribution layer30is disposed on the top surface19of the fan-out package10, where the first semiconductor die21and the second semiconductor die22are disposed on the first redistribution layer30. The plurality of second contacts212of the first semiconductor die21and the plurality of fourth contacts224of the second semiconductor die22are respectively connected to the first connection wiring11and the second connection wiring12through the first redistribution layer30. The second redistribution layer40is disposed between the bottom surface18of the fan-out package10and the substrate50. The second redistribution layer40includes a plurality of contact pads41, whereas the plurality of second contacts212and the plurality of fourth contacts224are electrically connected to the substrate50through the plurality of contact pads41and respectively through the first connection wiring11and the second connection wiring12.

It should be noted that in the first embodiment, the first connection wiring11and the second connection wiring12can be copper pillar structure. In addition to the signal channel between the first redistribution layer30and the second redistribution layer40, in other embodiments, one or more upper chip package structures can stack atop the chip package structure100, and the top chip package structure(s) is connected to the substrate50through the first connection wiring11and the second connection wiring12and through the contact pads41of the second redistribution layer40. For the second embodiment inFIG. 2, the first connection wiring11′ and the second connection wiring12′ can also be through mold via (TMV) structure.

Please refer toFIG. 3. The chip package structure300in a third embodiment inFIG. 3has substantially the same structure as the chip package structure100inFIG. 1, in which same component is designated with the same number. The interconnection bridge20of the third embodiment further electrically connects the substrate50using through silicon via (TSV). In other words, given the design need of package structure, at least part of the plurality of first contacts211of the first semiconductor die21and/or at least part of the plurality of third contacts223of the second semiconductor die22can be directly connected to the second redistribution layer40via the through silicon via (TSV) or further connected to the substrate50through the second redistribution layer40.

Please refer toFIG. 4. The chip package structure400in a fourth embodiment inFIG. 4has substantially the same structure as the aforementioned chip package structures100,200,300, in which same component is designated with the same number. A protective molding layer60can be further disposed on the top surface19of the fan-out package10and covers the first semiconductor die21and the second semiconductor die22for providing protection for the dies.

The chip package structure according to the embodiment of the invention lifts multi-dies above the fan-out molding package where at least two dies from the multi-dies are hybrid bump design structure which has both fine pitch and wide pitch design. The premade Si interposer is used as interconnection bridge embedded under the multi-die space for fine pitch high I/O interconnection between dies. The first RDL and the second RDL are further disposed on the top side and the bottom side of the fan-out molding package, further providing connection for the multi-dies to the substrate via the connection routing inside the fan-out molding package. The partial Si interposer interconnection bridge allows easier multi-die integration or system in package (SiP) and the shortest connection route also improves the signal/consumption performance.