Synthesizer structures and methods that reduce spurious signals

Synthesizers are provided to generate synthesizer signals in response to primary digital signal representations that are created by a signal generator. In an important feature, the synthesizers further include a signal corrector that inserts correction digital signal representations to at least partially cancel a corresponding spurious component in the primary digital signal representation and thereby provide synthesizer signals with reduced spurious content.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to synthesizers and, more particularly, to direct digital synthesizers.

2. Description of the Related Art

A direct digital synthesizer generates analog signals that correspond to input tuning words and a synthesizer clock which also determines the synthesizer's Nyquist range. Although direct digital synthesizers provide a number of advantageous features (e.g., phase-continuous switching, high frequency resolution and fast switching time), they typically generate spurious signals which unduly limit their spurious free dynamic range. This limitation continues to be the most serious deficiency of direct digital synthesizers.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to synthesizers which generate synthesizer signals with reduced spurious content.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1illustrates a synthesizer20which generates synthesizer signals in response to primary digital signal representations40that are provided by a signal generator22. In an important feature of the invention, the synthesizer further includes a signal corrector90that inserts correction digital signal representations (e.g.,56and76) to at least partially cancel a corresponding spurious component in the primary digital signal representation and thereby provide synthesizer signals with reduced spurious content.

In particular, the synthesizer20includes a primary signal generator22and a digital-to-analog converter24that are coupled together by a signal processor26. At least a first correction signal generator30is also coupled to the signal processor and a controller32provides tuning words34to the correction signal generator and commands36to the signal processor.

In operation of the synthesizer20, the primary signal generator generates a primary digital signal representation40in response to a tuning word TW from an input port41and a clock signal from a clock port42. When the primary digital signal representation is passed through the processor to the DAC24, it is converted into a corresponding analog signal at an output port44as indicated by the primary signal52in the graph50ofFIG. 2A.

Unfortunately, synthesizers generally also generate spurious signals because of imperfections in their signal generation and processing structures. As an example, inherent nonlinearities (e.g., nonlinear transfer function) in the DAC24can produce harmonics which combine with the clock signal to generate spurious signals that are the sums and differences of the harmonics and the clock signal.

In an specific example, let the clock signal be 400 MHz (so that the first Nyquist zone extends to 200 MHz) and the tuning word TW be selected to cause the primary signal52to be located at 159 MHz. The difference between the clock signal and the second harmonic of the primary signal52is 400−318=82 MHz which is shown as the first spurious signal53inFIG. 2A.

In addition, the difference between the third harmonic of the primary signal52and the clock signal is 477−400=77 MHz which is shown as the second spurious signal54inFIG. 2A. The spurious free dynamic range (SFDR) between the primary signal52and the highest of these spurious signals is shown inFIG. 2Aand is typically on the order of 50 dB.

It is generally difficult to significantly reduce the first and second spurious signals53and54. If, for example, a high-pass filter were inserted after the DAC24ofFIG. 1to reduce these spurious signals, it would unacceptably alter the amplitude of the primary signal52when its frequency was reduced by insertion of different tuning words into the input port41.

In further operation of the synthesizer20ofFIG. 1, however, the first correction signal generator30generates a first correction digital signal representation56in response to a first tuning word TW1from the controller32. When the primary digital signal representation56is passed through the processor26to the DAC24, it is converted into a corresponding analog signal at the output port44. The controller32adjusts the first tuning word TW1so that the frequency of the first correction digital signal representation56is substantially the frequency of the first spurious signal53ofFIG. 2A.

The signal processor26is configured to process the primary digital signal representation40and the correction digital signal representation56to provide a composite digital signal58that includes a phase-and-amplitude-modified version of the correction digital signal representation. Finally, the DAC24converts the composite digital signal to an analog synthesizer signal at the output port44.

Because its frequency, phase and amplitude can be adjusted by commands from the controller32, the first correction digital signal representation56can be configured to at least partially cancel a corresponding spurious component in the primary digital signal representation. In particular, it can be configured to at least partially cancel the first spurious signal53inFIG. 2Aso that it is significantly reduced as shown in the graph59ofFIG. 2B.

In a similar manner, a second correction signal generator60ofFIG. 1generates a second correction digital signal representation76in response to a second tuning word TW2from the controller32. The controller adjusts this tuning word and the phase and amplitude of the second correction digital signal representation to at least partially cancel a corresponding spurious component in the primary digital signal representation. In particular, this action at least partially cancels the second spurious signal54inFIG. 2Aso that it is also significantly reduced as shown in the graph59ofFIG. 2B.

FIG. 3Ashows that a first embodiment26A of the processor26ofFIG. 1includes a phase shifter70and an adder71. The phase shifter is coupled to process the first correction digital signal representation56and provide an adjusted first correction digital signal representation72that is then processed with the primary digital signal representation40in the adder71to provide the composite digital signal58. In one embodiment, the phase shifter70is a digital adder that receives an adjustment word73(one of commands36inFIG. 1) from the controller (32inFIG. 1) and adds it to (or subtracts it from) the first correction digital signal representation56to generate the adjusted correction digital signal representation58.

The operation of the phase shifter70can be considered in association with an embodiment of the primary and correction signal generators22,30and60ofFIG. 1. In the embodiment ofFIG. 4, a phase accumulator82(e.g., an adder and a register arranged in a loop with the register receiving the clock signal and the adder receiving the tuning word and the output of the register) drives an angle-to-amplitude mapper84(e.g., a lookup table and/or digitally-processed algorithm). The phase accumulator generates a digital ramp that repeats at an accumulator frequency that corresponds to the tuning word TW and the clock signal. The mapper84then maps the words of the digital ramp into a digital signal representation in which the signal is generally a sinusoid.

Returning attention to the phase shifter70ofFIG. 3A, it is noted that it adds the adjustment word73to (or subtracts the adjustment word from) the first correction digital signal representation56to thereby adjust the phase of the representation. Thus, it subtracts or adds an adjustment word to the words of a digital signal representation that is generated, for example, by the structure ofFIG. 4.

The adder74ofFIG. 3Apreferably has an n-bit input port indicated by an extension arrow74and a corresponding n-bit output port that mates to a similar n-bit input port in the DAC (24inFIG. 1). The adder's input port can be arranged to shift bits of one of the primary digital signal representation40and the adjusted correction digital signal representation72relative to the other to thereby modify their relative amplitudes. For example, the primary digital representation may be received into upper bits75of the adder's input port and the adjusted correction digital signal representation may be received into lower bits76.

In a specific example, the adder's input port may be 12 bits and the primary digital signal representation and the adjusted correction digital signal representation may each comprise 10 bits. In an exemplary arrangement, the primary digital signal representation may be received into the upper 10 bits of the adder's input port and the adjusted correction digital signal representation may be received into the lower 4 bits of the adder's input port (with the lower 6 bits of the adjusted correction digital signal representation thereby discarded).

The DAC24ofFIG. 1will thus convert the adjusted correction digital signal representation (72inFIG. 3A) to an analog correction signal whose amplitude is substantially reduced relative to the primary signal52ofFIG. 2A. Preferably, it is reduced so that it closely approximates the amplitude of the first spurious signal53ofFIG. 2A.

If the tuning word into the correction signal generator30ofFIG. 1is also selected so that the frequency of the analog correction signal closely matches the frequency of the first spurious signal53and the adjustment word73ofFIG. 3Ais also selected so that the phase of the analog correction signal closely opposes the phase of the first spurious signal53(i.e., they are essentially 180 degrees out of phase), then the amplitude of the first spurious signal53ofFIG. 2Awill be significantly reduced as shown inFIG. 2B.

FIG. 3Bshows another embodiment26B of the processor26ofFIG. 1that is formed by inserting a multiplier77in series with the phase shifter (70inFIG. 3A) to thereby further facilitate modification of the amplitude of the correction digital signal representation56. The multiplier alters the adjusted first correction digital signal representation72into a different adjusted first correction digital signal representation78.

In particular, the multiplier77can receive a command79(one of commands36inFIG. 1) from the controller (32inFIG. 1) that causes it to multiply the adjusted first correction digital signal representation72by a fractional number (in an embodiment, the command may be the multiplying number) so that it, in effect, reduces the representation's amplitude. For example, the fractional number can be ½ which halves the amplitude to thereby (approximately) realize a 6 dB reduction. In one embodiment, the multiplier77is simply arranged to effect successive right shifts of the bits of the representation to successively realize 6 dB reductions in amplitude.

FIG. 5is a diagram that includes portions of the synthesizer20ofFIG. 1. This diagram has been altered, however, to show that an embodiment of the controller32can be configured to directly generate the first and second tuning words TW1and TW2in response to the synthesizer's tuning word TW that enters the input port41. For example, the controller can be configured to calculate, in response to the tuning word TW, the frequencies of spurious signals53and54ofFIG. 2Athat are the sums and differences of signal harmonics and the clock signal. The controller then automatically provides the corresponding first and second tuning words to the correction signal generators30and60.

As described above, the first and second correction signal generators30and60ofFIG. 1generate first and second correction digital signal representations56and76that at least partially cancel corresponding spurious components in the synthesizer signal at the output port44. As indicated with broken lines inFIG. 1, the synthesizer20can include additional correction signal generators that are directed to at least partially cancel additional corresponding spurious components in the synthesizer signal.

With a description of the embodiments ofFIGS. 1–5completed, it is now apparent thatFIG. 1illustrates a synthesizer20which has a primary signal generator22, a signal corrector90and a DAC24wherein one embodiment of the signal corrector comprises at least one of the correction signal generators30and60, and the signal processor26. The primary signal generator22generates a primary digital signal representation with a primary frequency determined by a clock signal and a primary tuning word. The signal corrector90then inserts a correction digital signal representation to at least partially cancel a corresponding spurious component in the synthesizer signal at the output port44and thereby provide a composite digital signal58. Finally, the digital-to-analog converter24converts the composite digital signal to an analog synthesizer signal.

FIG. 6illustrates another synthesizer embodiment100which includes elements of the synthesizer20ofFIG. 1with like elements indicated by like reference numbers. The synthesizer100, however, removes the signal processor26from its location inFIG. 1and, instead, inserts correction elements of the signal processor into correction paths of each of the correction signal generators30and60. The synthesizer100then provides each of the correction paths with a respective DAC102(which is similar to the DAC24). In particular, a phase shifter and a multiplier similar to the phase shifter70and multiplier77ofFIG. 3Bare inserted between each of the correction signal generators and their respective DACs102.

In operation of the synthesizer100, the DAC24converts the primary digital representation40into a synthesizer signal as shown inFIG. 2A. In further operation of the synthesizer100, the first correction signal generator30generates a first correction digital signal representation56in response to a first tuning word TW1from the controller32. In response to commands or adjustment words from the controller32, a phase shifter70adjusts the phase of the first correction digital signal representation56to generate an adjusted correction digital signal representation104. A multiplier77alters the adjusted first correction digital signal representation104into a different adjusted first correction digital signal representation106which has a reduced representation amplitude.

Finally, a DAC102converts the signal representation106into a correction analog synthesizer signal108whose frequency (in response to the tuning word TW1) closely matches the frequency of the first spurious signal53ofFIG. 2A. In addition, the phase of the correction analog synthesizer signal108closely opposes the phase of the first spurious signal53(in response to the phase shifter70) and the amplitude of the correction analog synthesizer signal closely approximates the amplitude of the first spurious signal53(in response to the multiplier77).

Accordingly, the amplitude of the first spurious signal53will be significantly reduced when the correction analog synthesizer signal108is summed with the primary analog synthesizer signal109(out of the primary DAC24) to form the synthesizer signal at the synthesizer's output port44. In a similar manner, the second correction signal generator60can be used with its respective phase shifter, multiplier and DAC to significantly reduce the amplitude of the second spurious signal54inFIG. 2A.

In another synthesizer embodiment, the DAC102includes a reference input and the amplitude of the DAC's analog output signal corresponds to the amplitude of a reference signal110inserted into this reference input. The reference signal can be provided by the controller32and scaled to appropriately reduce the amplitude of the correction analog synthesizer signal108. Accordingly, the reference signal can be adjusted to supplement the amplitude reductions of the multiplier77or to replace the reductions of this multiplier (and thus remove the need for the multiplier).

Although the output signals of DACs (e.g., current-output DACs) can often be simply coupled together to form the synthesizer signal, the synthesizer100ofFIG. 6includes, to form a different synthesizer embodiment, a summer112which facilitates summation of the correction analog synthesizer signals, e.g.,108, and the primary analog synthesizer signal109.

As the frequency of the primary signal generator22ofFIG. 1is altered by new tuning words, the frequency, phase and amplitude of output spurious signals will change. In response, the controller32must provide corresponding tuning words to the correction signal generators and corresponding phase and amplitude commands to portions of the signal processor26to continue to reduce the spurious signals. Although the synthesizer embodiments ofFIGS. 1 and 5include the controller32, its control signals (e.g., tuning words and multiplier commands) can be supplied by various other sources (e.g., stored in a memory).

Other embodiments of the invention can be provided by appropriate structural and functional modifications. For example,FIGS. 3A and 3Bshow the first correction digital signal representation56processed to an adjusted first correction digital signal representation72which is summed with the digital signal representation40in the adder71. Other correction digital signal representations (e.g., the second correction digital signal representation76ofFIG. 1) can be similarly processed and summed into the same adder or, in a different embodiment, the correction digital signal representations can be successively summed with the digital signal representation40in a string of adders.

As another example, the phase shifter70ofFIG. 3Acan be relocated from the signal processor26A to be positioned, instead, in its corresponding correction signal generator30. In a third example, the mapper84ofFIG. 4may be configured to sufficiently modify (e.g., reduce) the amplitude of its corresponding digital signal representation so that a corresponding phase shifter (e.g, the phase shifter70ofFIG. 3A) does not overrange the signal representation as it alters it. For a fourth example, embodiments of controllers of the invention (32inFIGS. 1,5and6) can be realized with arrays of digital gates, an appropriately-programmed digital processor or combinations thereof.