Semiconductor package with improved flatness of an insulating layer formed on patterns

A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of priority to Korean Patent Application No. 10-2017-0182059, filed on Dec. 28, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package.

2. Description of Related Art

Semiconductor packages have been continuously required to be thinned and lightened in terms of a shape, and have been required to be implemented in a system in package (SiP) form requiring complexation and multi-functionality in terms of a function. In accordance with such a development trend, a fan-out wafer level package (FOWLP) has been recently prominent, and attempts to satisfy requirements of semiconductor packaging by applying several techniques to the FOWLP have been conducted.

One type of package technology suggested to satisfy the technical demand as described above is a fan-out semiconductor package. Such a fan-out semiconductor package has a compact size and may allow a plurality of pins to be implemented by redistributing connection terminals outwardly of a region in which a semiconductor chip is disposed.

SUMMARY

An aspect of the present disclosure may provide a semiconductor package in which a short-circuit of an interlayer circuit may be prevented by improving flatness of an insulating layer formed on patterns.

According to an aspect of the present disclosure, a semiconductor package may be provided, in which an insulating layer provided on patterns (particularly, wiring patterns protruding from a support member) are formed by double coating to improve final flatness of the insulating layer.

According to an aspect of the present disclosure, a semiconductor package may include: a support member having first and second surfaces opposing each other, having a cavity penetrating through the first and second surfaces, and including a wiring structure; a semiconductor chip disposed in the cavity and having an active surface having connection pads disposed thereon; a connection member including a first insulating layer disposed on the second surface of the support member, a first redistribution layer disposed on the first insulating layer, and a plurality of first vias penetrating through each of the first insulating layer and connecting the wiring structure and the connection pads to the first redistribution layer; and an encapsulant encapsulating the semiconductor chip disposed in the cavity and covering the first surface of the support member, wherein the wiring structure includes wiring patterns protruding from or concavely disposed in the second surface of the support member, and the first insulating layer includes a first insulating coating disposed on the second surface of the support member and covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

According to another aspect of the present disclosure, a semiconductor package may include: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer disposed on the first insulating layer, first vias penetrating through the first insulating layer and electrically connecting the connection pads and the first redistribution layer to each other, and a second insulating layer disposed on the first insulating layer and covering the first redistribution layer; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip, wherein the second insulating layer includes a first insulating coating disposed on the first insulating layer and covering the first redistribution layer and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating, and the first and second insulating coatings are formed of the same material.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounting surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection. In addition, representations such as “first”, “second”, and the like, are used to distinguish one component from another component, and does not limit a sequence, importance, and the like, of the corresponding components. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip-related components1020, network-related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the mainboard1010, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip-related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in oneself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not used in an exposed state, but rather is packaged and used in an electronic device, or the like, in a package state.

Semiconductor packaging is required because there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the accompanying drawings.

Fan-in Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged, andFIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring toFIGS. 3 and 4, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection member2240may be formed depending on a size of the semiconductor chip2220on the semiconductor chip2220in order to redistribute the connection pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device, andFIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

Referring toFIGS. 5 and 6, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, low melting point metal balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an outer side of the semiconductor chip2220may be covered with an encapsulant2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may further be formed on the connection member2140, and an underbump metal layer2160may further be formed in openings of the passivation layer2150. Low melting point metal balls2170may further be formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

In the present manufacturing process, the connection member2140may be formed after the encapsulant2130is formed outside the semiconductor chip2120. In this case, a process for the connection member2140is performed from the via connecting the redistribution layers and the connection pads2122of the semiconductor chip2120to each other and the redistribution layers, and the vias2143may thus have a width that becomes small as they approach the semiconductor chip (see an enlarged region).

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in the case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through low melting point metal balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

A semiconductor package in which a resin for an insulating layer may be smoothly applied even though patterns of a redistribution layer are implemented at a fine pitch will hereinafter be described in detail with reference to the accompanying drawings.

FIG. 9is a side cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure.FIG. 10is a plan view illustrating the semiconductor package illustrated inFIG. 9.

Referring toFIGS. 9 and 10, a semiconductor package100A according to the present exemplary embodiment may include a support member110having a cavity110H penetrating through first and second surfaces110A and110B opposing each other, a semiconductor chip120disposed in the cavity110H of the support member110and having an active surface having connection pads122disposed thereon and a surface opposing the active surface, an encapsulant130encapsulating the support member110and the semiconductor chip120, and a connection member140disposed on the support member110and the active surface of the semiconductor chip120.

The support member110used in the present exemplary embodiment may include a first dielectric layer111aand second and third dielectric layers111band111cdisposed on opposite surfaces of the first dielectric layer111a, respectively. In addition, the support member110may include a wiring structure connecting the first and second surfaces110A and110B to each other.

In detail, the wiring structure of the support member110may include first and second wiring patterns112aand112bdisposed on opposite surfaces of the first dielectric layer111a, respectively, third wiring patterns112cdisposed on the second dielectric layer111b, fourth wiring patterns112ddisposed on the third dielectric layer111c, first vias113apenetrating through the first dielectric layer111aand connecting the first and second wiring patterns112aand112bto each other, second vias113bpenetrating through the second dielectric layer111band connecting the first and third wiring patterns112aand112cto each other, and third vias113cpenetrating through the third dielectric layer111cand connecting the second and fourth wiring patterns112aand112cto each other. The wiring structure used in the present exemplary embodiment may provide through-vias including the first to third vias connecting the second and fourth wiring patterns disposed on the first and second surfaces110A and110B of the support member110, respectively, to each other, but may be variously modified depending on the number of dielectric layers. Since the support member110may include a large number of wiring patterns112a,112b,112c, and112d, the connection member140may further be simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the connection member140may be suppressed.

The connection member140used in the present exemplary embodiment may include a first insulating layer141adisposed on the second surface110B of the support member110and the active surface of the semiconductor chip120, a first redistribution layer142adisposed on the first insulating layer141a, first vias143apenetrating through the first insulating layer141aand connecting the first redistribution layer142aand the connection pads122of the semiconductor chip122to each other, a second insulating layer141bdisposed on the first insulating layer141aand covering the first redistribution layer142a, a second redistribution layer142bdisposed on the second insulating layer141b, second vias143bpenetrating through the second insulating layer141band connecting the first and second redistribution layers142aand142bto each other, a third insulating layer141cdisposed on the second insulating layer141band covering the second redistribution layer142b, a third redistribution layer142cdisposed on the third insulating layer141c, and third vias143cpenetrating through the third insulating layer141cand electrically connecting the second and third redistribution layers142band142cto each other. As described above, a form in which the connection member has a three-layer redistribution structure including the first redistribution layer142a, the second redistribution layer142b, and the third redistribution layer142cis illustrated. However, the connection member is not limited thereto, but may be implemented in a structure including a single redistribution layer or four or more redistribution layers. In the present specification, an “upper surface” of each of the first to third redistribution layers142a,142b, and142crefers to a surface thereof opposing a surface thereof in contact with the insulating layer on which a corresponding redistribution layer is formed regardless of a disposition direction of the semiconductor package100A, and refers to a surface thereof applied by another insulating layer.

In the present exemplary embodiment, the fourth wiring patterns112dmay be provided on the second surface110B of the support member110in a protruding form, and the first insulating layer141amay be formed on the second surface110B of the support member110. Since the fourth wiring patterns112dare formed by a printed circuit board process, the fourth wiring patterns112dmay have a thickness relatively greater than that of the redistribution layer of the connection member, and it may be difficult to secure flatness of the first insulating layer.

Conventionally, a thickness of each of the fourth wiring patterns112dof the support member110is decreased by chemical mechanical polishing (CMP) or an etchback process before the connection member is formed. On the other hand, the present disclosure may provide a method of forming the first insulating layer141ausing double coating without using such a complicated process.

As illustrated inFIG. 9, the first insulating layer141amay include a first insulating coating141a′ covering the fourth wiring patterns112dand a second insulating coating141a″ disposed on the first insulating coating141a′. The second insulating coating141a″ may have a higher level of flatness than that of the first insulating coating141a′.

The first insulating coating141a′ may have convex structures in the vicinity of the fourth wiring patterns112ddue to tension between the first insulating coating141a′ and surfaces of the fourth wiring patterns112dformed of copper before it is hardened, resulting in a large thickness deviation (that is, a low level of flatness). On the other hand, the second insulating coating141a″ applied after the first insulating coating141a′ is hardened may be formed on a surface of the first insulating coating141a′ to significantly alleviate a step. Such a process will be described below with reference toFIGS. 11A to 11D.

Since the first and second insulating coatings141a′ and141a″ improve flatness using a state of a surface to which they are applied, the first and second insulating coatings141a′ and141a″ are not limited to being formed of different materials, but may be formed of the same material for convenience of a process. For example, the first and second insulating coatings141a′ and141a″ may include a photoimagable dielectric (PID) resin. Even though the first and second insulating coatings141a′ and141a″ constituting the first insulating layer141aare formed of the same material as described above, first and second insulating coatings141a′ and141a″ are hardened at different points in time, and an interface between the first and second insulating coatings141a′ and141a″ may thus be observed by an optical microscope.

In the present exemplary embodiment, the first insulating layer141ais used to cover relatively thick patterns, and may thus have a thickness greater than those of the second and third insulating layers141band141c.

In the present exemplary embodiment, a passivation layer150may be disposed on the connection member140, and underbump metal layers160may be disposed in openings151of the passivation layer150. In addition, electrical connection structures170connected to the underbump metal layers160may be disposed on the passivation layer150.

The respective components included in the semiconductor package100A according to the present exemplary embodiment will hereinafter be described in more detail.

The support member110may maintain rigidity of the semiconductor package100A, and serve to secure uniformity of a thickness of the encapsulant130. A wiring structure may not be introduced into the support member110(seeFIG. 12), and another type of wiring structure may be introduced. The semiconductor chip120may be disposed in the cavity110H to be spaced apart from sidewalls of the support member110by a predetermined distance. Side surfaces of the semiconductor chip120may be surrounded by the support member110. However, such a form is only an example and may be variously modified to have other forms, and the support member110may perform another function depending on such a form. In some exemplary embodiments, the support member110may be omitted.

The support member110may include various dielectric layers. A material of the dielectric layer may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fabric, for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. When a material having high rigidity, such as prepreg including a glass fabric, or the like, is used as the material of the dielectric layer, the support member110may be utilized as a support member for controlling warpage of the semiconductor package100A.

The semiconductor chip120may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. In this case, the IC may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. That is, the IC may be a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a memory chip such as a volatile memory (for example, a DRAM), a non-volatile memory (for example, a ROM), a flash memory, or the like. In addition, the abovementioned elements may also be combined with each other and be disposed.

The semiconductor chip120may be formed on the basis of an active wafer. In this case, a base material of a body121of the semiconductor chip120may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body121. The connection pads122may electrically connect the semiconductor chip120to other components. A material of each of the connection pads122may be a conductive material such as aluminum (Al), or the like. A passivation layer123exposing the connection pads122may be formed on the body121, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. A lower surface of the connection pad122may have a step with respect to a lower surface of the encapsulant130through the passivation layer123. Resultantly, a phenomenon in which the encapsulant130bleeds into the lower surface of the connection pads122may be prevented to some extent. An insulating layer (not illustrated), and the like, may also be further disposed in other required positions. The semiconductor chip120may be a bare die, a redistribution layer (not illustrated) may further be formed on the active surface of the semiconductor chip120, if necessary, and bumps (not illustrated), or the like, may be connected to the connection pads122.

The encapsulant130may be provided in order to protect the support member110and an electronic component such as the semiconductor chip120, and the like. An encapsulation form of the encapsulant130is not particularly limited, but may be a form in which the encapsulant130surrounds at least portions of the support member110, the semiconductor chip120, and the like. For example, the encapsulant130may cover an upper surface of the support member110and the semiconductor chip120, and fill spaces between sidewalls of the cavity110H and the side surfaces of the semiconductor chip120. In addition, the encapsulant130may also fill at least a portion of a space between the passivation layer123of the semiconductor chip120and the connection member140. Meanwhile, the encapsulant130may fill the cavity110H to thus serve as an adhesive and reduce buckling of the semiconductor chip120depending on certain materials.

For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin and the thermoplastic resin are mixed with an inorganic filler or are impregnated together with an inorganic filler in a core material such as a glass fiber, or the like, for example, prepreg, ABF, FR-4, BT, or the like, may be used as a material of the encapsulant130. In some exemplary embodiments, a PID resin may also be used as the material of the encapsulant130.

The connection member140may redistribute the connection pads122of the semiconductor chip120. Several tens to several hundreds of connection pads122of the semiconductor chip120having various functions may be redistributed by the connection member140, and may be physically or electrically externally connected through the electrical connection structures170depending on the functions.

The first to third insulating layers141a,141b, and141cused in the connection member140may be formed of a photosensitive insulating material such as a PID resin, in addition to the insulating material described above. In the present exemplary embodiment, each of the first to third insulating layers141a,141b, and141cmay be formed of a PID resin. When the first to third insulating layers141a,141b, and141chave photosensitive properties, the first to third insulating layers141a,141b, and141cmay be formed to have a smaller thickness, and fine pitches of the first to third vias143a,143b, and143cmay be achieved more easily. The first to third insulating layers141a,141b, and141cmay be photosensitive insulating layers including an insulating resin and an inorganic filler. When the first to third insulating layers141a,141b, and141care multiple layers, materials of the first to third insulating layers141a,141b, and141cmay be the same as each other, and may also be different from each other, if necessary. When the first to third insulating layers141a,141b, and141care the multiple layers, the first to third insulating layers141a,141b, and141cmay be integrated with one another depending on a process, such that boundaries thereamong may also not be apparent. A thickness of each of the first to third insulating layers141a,141b, and141cbetween patterns except for the first to third redistribution layers142a,142b, and142cmay be approximately 1 μm to 10 μm.

The first to third redistribution layers142a,142b, and142cmay serve to redistribute the connection pads122together with the first to third vias143a,143b, and143c. Each of the first to third redistribution layers142a,142b, and142cmay include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first to third redistribution layers142a,142b, and142cmay perform various functions depending on designs of corresponding layers. For example, the first to third redistribution layers142a,142b, and142cmay include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the first to third redistribution layers142a,142b, and142cmay include via pad patterns, electrical connection structure pad patterns, and the like. Each of the first to third redistribution layers142a,142b, and142cmay have a thickness of about 0.5 μm to 15 μm.

The first to third vias143a,143b, and143cmay serve to connect (interlayer connection) the first to third redistribution layers142a,142b, and142c, the connection pads122, and the like, formed on different layers to each other in a vertical direction. Each of the first to third vias143a,143b, and143cmay include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first to third vias143a,143b, and143cmay be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of via holes. In addition, each of the first to third vias143a,143b, and143cmay have any shape known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The passivation layer150may protect the connection member140from external physical or chemical damage. The passivation layer150may have the openings151exposing at least portions of the first to third redistribution layers142a,142b, and142cof the connection member140. The number of openings151formed in the passivation layer150may be several tens to several thousands. A material of the passivation layer150is not particularly limited, but may be the insulating material described above. For example, the passivation layer150may include at least one of prepreg, AFB, FR-4, and a solder resist.

The underbump metal layers160may improve connection reliability of the electrical connection structures170to improve board level reliability of the semiconductor package100A. The underbump metal layers160may be connected to the redistribution layer142of the connection member140exposed through the openings151of the passivation layer150. The underbump metal layers160may be formed in the openings151of the passivation layer150by any known metallization method using any known conductive metal such as a metal, but are not limited thereto.

The electrical connection structure170may physically or electrically externally connect the semiconductor package100A. For example, the semiconductor package100A may be mounted on the mainboard of the electronic device through the electrical connection structures170. Each of the electrical connection structures170may be formed of a conductive material, for example, a low melting point metal, or the like. However, this is only an example, and a material of each of the electrical connection structures170is not particularly limited thereto. Each of the electrical connection structures170may be a land, a ball, a pin, or the like. The electrical connection structures170may be formed as a multilayer or single layer structure. When the electrical connection structures170are formed as a multilayer structure, the electrical connection structures170may include a copper (Cu) pillar and a low melting point metal. When the electrical connection structures170are formed as a single layer structure, the electrical connection structures170may include copper (Cu) or a low melting point alloy such as an Sn—Al—Cu alloy. However, this is only an example, and the electrical connection structures170are not limited thereto. The number, an interval, a disposition form, and the like, of electrical connection structures170are not particularly limited, but may be sufficiently modified depending on design particulars by those skilled in the art. For example, the electrical connection structures170may be provided in an amount of several tens to several thousands according to the number of connection pads122, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

When the electrical connection structures170are low melting point balls, the electrical connection structures170may cover side surfaces of the underbump metal layers160extending onto one surface of the passivation layer150, and connection reliability may be more excellent.

At least one of the electrical connection structures170may be disposed in a fan-out region. The fan-out region refers to a region except for a region in which the semiconductor chip120is disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness.

Meanwhile, although not illustrated in the drawings, a metal thin film may be formed on walls of the cavity110H, if necessary, in order to dissipate heat or block electromagnetic waves. In some exemplary embodiments, a plurality of semiconductor chips120performing functions that are the same as or different from each other may be disposed in the cavity110H, if necessary. In some exemplary embodiments, a separate passive component such as an inductor, a capacitor, or the like, may be disposed in the cavity110H. In some exemplary embodiments, a passive component, for example, a surface mounting technology (SMT) component including an inductor, a capacitor, or the like, may be disposed on a surface of the passivation layer150.

In the semiconductor package according to the exemplary embodiment described above, the first and second insulating coatings may be sequentially applied and hardened as the insulating layer covering the wiring patterns of the support member to improve flatness.

FIGS. 11A through 11Dare cross-sectional views for describing main processes of forming a redistribution layer according to an exemplary embodiment in the present disclosure.FIGS. 11A through 11Dillustrate a series of processes corresponding to an enlarged portion ofFIG. 9.

Referring toFIG. 11A, two fourth wiring patterns may be disposed on the support member110in a protruding form.

As described above, the fourth wiring patterns112dare formed by the printed circuit board process, and may thus have a relatively great thickness (for example, 10 μm or more) Therefore, in order to secure flatness by the first insulating layer141a, the thickness of each of the fourth wiring patterns112dis decreased by the CMP or the etchback process before the connection member is formed. On the other hand, in the present exemplary embodiment, the double coating may be used.

Then, as illustrated inFIG. 11B, the first insulating coating141a′ may be formed to cover the fourth wiring patterns112ddisposed on the support member110.

For example, the first insulating coating141a′ may include the PID resin. The first insulating coating141a′ formed in the present process may have the convex structures in the vicinity of the fourth wiring patterns112ddue to the tension between the first insulating coating141a′ and the surfaces of the fourth wiring patterns112dformed of copper, resulting in a large thickness deviation.

Since a thickness t of an insulating layer disposed on the fourth wiring patterns112dneeds to be sufficiently secured (see dotted lines RL) in order to sufficiently insulate interlayer circuits from each other, when the first insulating layer141afor the redistribution layer is formed by applying coating only once, a large thickness deviation Δt0may be inevitably generated in order to obtain a desired thickness t of the insulating layer. In order to prevent this, in the present process, the first insulating coating141a′ may be formed at a thickness enough to cover the fourth wiring patterns112dformed of copper, but as small as possible, as a portion of the first insulating layer141a. The first insulating coating141a′ may have a thickness deviation Δt1smaller than an existing thickness deviation Δt0. For example, the thickness deviation Δt1of the first insulating coating141a′ may be in a range of 10 to 13 μm. In addition, a minimum thickness of a portion of the first insulating coating141a′ disposed between the fourth wiring patterns112dmay be smaller than that of each of the fourth wiring patterns.

Then, as illustrated inFIG. 11C, the second insulating coating141a″ may be formed on the first insulating coating141a′ after the first insulating coating141a′ is hardened.

The second insulating coating141a″ may be formed so that the desired thickness t of the insulating layer is secured together with the first insulating coating141a′. That is, the desired thickness t of the insulating layer may be implemented by the sum of a thickness of the first insulating coating141a′ and a thickness of the second insulating coating141a″ on the fourth wiring pattern112d. Since the second insulating coating141a″ is formed on the first insulating coating141a′ formed of a material similar to that of the second insulating coating141a″, the second insulating coating141a″ may be relatively flatly formed.

In the present process, a thickness deviation of the second insulating coating141a″ may be alleviated as compared to the thickness deviation of the first insulating coating141a′. For example, the thickness deviation of the second insulating coating141a″ may have a significantly high level of flatness of 3 μm or less.

The second insulating coating141a″ may include the PID resin. As described above, even though the second insulating coating141a″ is formed of the same material as that of the first insulating coating141a′, the first and second insulating coatings141a′ and141a″ are hardened at different points in time, and the interface between the first and second insulating coatings141a′ and141a″ may thus be observed.

Then, as illustrated inFIG. 11D, the first redistribution layer142aand the first via143amay be formed on and in the second insulating coating141a″, that is, on and in the first insulating layer141a.

Since the first insulating layer141aprovides a planarized surface in spite of a step of the fourth wiring patterns112d, a short-circuit of the interlayer circuit may be prevented, and the first redistribution layer142amay be effectively formed.

FIG. 12is a side cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 12, it may be understood that a semiconductor package100B according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 9 and 10except that second and third insulating layers141band141cof a connection member140are formed in a double coating manner, similar to a first insulating layer141aof the connection member140. Components according to the present exemplary embodiment may be understood with reference to the description for the same or similar components of the semiconductor package100A illustrated inFIGS. 9 and 10unless explicitly described to the contrary.

In the present exemplary embodiment, the second and third insulating layers141band141cof the connection member140may be formed in the double coating manner, as described above. The second insulating layer141bmay include a first insulating coating141b′ disposed on the first insulating layer141aand covering the first redistribution layer142aand a second insulating coating141b″ disposed on the first insulating coating141b′ and having a higher level of flatness than that of the first insulating coating141b′. Similarly, the third insulating layer141cmay include first and second insulating coatings141c′ and141c″ formed in the double coating manner to improve flatness. The first insulating coatings141b′ and141c′ and the second insulating coatings141b″ and141c″ may include the same PID resin.

In this way, flat insulating layers that may sufficiently secure insulation between interlayer circuits without significantly increasing thicknesses of the respective insulating layers141a,141b, and141cmay be provided. As described above, the connection member140of the semiconductor package100A illustrated inFIG. 9is implemented, similar to the insulating layers of the connection member140, such that the respective insulating layers on which the redistribution layers are implemented may be formed to have an excellent level of flatness in the double coating manner.

FIG. 13is a side cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 13, it may be understood that a semiconductor package100C according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 9 and 10except that a support member110that does not have a wiring structure is used and second and third insulating layers141band141cof a connection member140are formed in a double coating manner. Components according to the present exemplary embodiment may be understood with reference to the description for the same or similar components of the semiconductor package100A illustrated inFIGS. 9 and 10unless explicitly described to the contrary.

In the present exemplary embodiment, a first insulating layer141aof the connection member140may be formed in a single layer structure, and the second and third insulating layers141band141cof the connection member140may be formed in the double coating manner. The second insulating layer141bmay include a first insulating coating141b′ disposed on the first insulating layer141aand covering the first redistribution layer142aand a second insulating coating141b″ disposed on the first insulating coating141b′ and having a higher level of flatness than that of the first insulating coating141b′. Similarly, the third insulating layer141cmay include first and second insulating coatings141c′ and141c″ formed in the double coating manner, similar to the second insulating layer141b, to improve flatness. The first insulating coatings141b′ and141c′ and the second insulating coatings141b″ and141c″ may include the same PID resin.

In the present exemplary embodiment, a form in which the first insulating layer141ais not formed in the double coating manner since protruding or concave wiring patterns are not used on a surface of a support member is illustrated, the first insulating layer141amay also be formed in the double coating manner as in the semiconductor package100B illustrated inFIG. 12. For example, the first insulating layer141amay include a first insulating coating and a second insulating coating as in the second and third insulating layers141band141cdescribed above. Here, the first insulating coating of the first insulating layer141amay cover a support member110and an active surface of a semiconductor chip120. When a bent portion exists in a region (for example, a region of an encapsulant130) between the support member110and the semiconductor chip120, the first insulating coating may contribute to planarizing the bent portion.

FIG. 14is a side cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 14, it may be understood that a semiconductor package100D according to the present exemplary embodiment has a structure similar to that illustrated in FIGS.9and10except that a support member110′ different from that of the exemplary embodiment described above is used and second and third insulating layers141band141cof a connection member140are additionally formed in a double coating manner. Components according to the present exemplary embodiment may be understood with reference to the description for the same or similar components of the semiconductor package100A illustrated inFIGS. 9 and 10unless explicitly described to the contrary.

In the present exemplary embodiment, the support member110′ may include a first dielectric layer111a′ in contact with a connection member140, first wiring patterns112a′ in contact with the connection member140and embedded in the first dielectric layer111a′, second wiring patterns112b′ disposed on the other surface of the first dielectric layer111a′ opposing one surface of the first dielectric layer111a′ in which the first wiring patterns112a′ are embedded, a second dielectric layer111b′ disposed on the first dielectric layer111a′ and covering the second wiring patterns112b′, and third wiring patterns112c′ disposed on the second dielectric layer111b′. The first to third wiring patterns112a′,112b′, and112c′ may be electrically connected to connection pads122. The first and second wiring patterns112a′ and112b′ and the second and third wiring patterns112b′ and112c′ may be electrically connected to each other through first and second vias113a′ and113b′ penetrating through the first and second dielectric layers111a′ and111b′, respectively.

In the present exemplary embodiment, since the first wiring patterns112a′ are embedded in the first dielectric layer111a′, a step generated due to a thickness of the first wiring patterns112a′ may be decreased, and a deviation of an insulating distance of the connection member140may be decreased. In addition, a difference between a distance from a first redistribution layer142aof the connection member140to a lower surface of the first dielectric layer111a′ and a distance from the first redistribution layer142aof the connection member140to the connection pad122of a semiconductor chip120may be smaller than a thickness of the first wiring pattern112a′. Therefore, a high density wiring design of the connection member140may be easy.

Meanwhile, the first wiring patterns112a′ may be somewhat concavely disposed in a lower surface of the support member110′. A first insulating layer141aused in the present exemplary embodiment may be provided in a double coating manner to remove a step due to a concave structure. In detail, the first insulating layer141amay include a first insulating coating141a′ disposed on the lower surface of the support member110′ and a second insulating coating141a″ disposed on the first insulating coating141a′ and having a higher level of flatness than that of the first insulating coating141a′. The first insulating layer141aprovided in the double coating manner described above may extend to an active surface of the semiconductor chip120to alleviate a non-uniform step between the semiconductor chip120and the support member110′.

In the present exemplary embodiment, a second insulating layer141band a third insulating layer141cof the connection member140may be formed in a double coating manner in order to planarize thickness deviations due to first and second redistribution layers142aand142bas in another exemplary embodiment described above (seeFIGS. 12 and 13).

As set forth above, according to the exemplary embodiments in the present disclosure, a semiconductor package in which an insulating layer disposed on patterns (particularly, wiring patterns protruding from a support member) are formed by double coating to improve final flatness of the insulating layer in a desired thickness range and a short-circuit between the insulating layer and a redistribution layer formed in a subsequent process is reduced may be provided.

Particularly, an insulating layer having a desired level of flatness may be formed by only double coating technology without decreasing a thickness of the wiring patterns protruding from the support member by an additional polishing process or an etchback process.