Display device including connective wirings within a display area thereof

A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches that protrude from the connection wirings in a direction perpendicular to a direction in which the connection wirings are primarily extended.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2019-0003283, filed on Jan. 10, 2019, in the Korean Intellectual Property Office, the disclosure of which is herein incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a display device and, more specifically, to a display device including connective wirings within a display area of the display device.

Discussion of the Related Art

As display devices have become larger, the non-display area that surrounds the display area has been reduced in size. While this creates a display device with a modern look, there is less available space for disposing the driving circuits and wirings for driving the pixels of the display device, which have traditionally been disposed along the non-display area.

SUMMARY

A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches that protrude from the connection wirings in a direction perpendicular to a direction in which the connection wirings are primarily extended.

A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal supplied from the pad area to the plurality of data lines. The display area includes a first area in which the plurality of connection wirings extend in a first direction, and a second area in which the plurality of connection wirings extend in a second direction that is perpendicular to the first direction.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout the specification and the drawings. In this regard, the present embodiments may have different forms than what is set forth herein.

It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. In contrast, the phrase “consisting of” precludes the addition of unlisted features or components.

It will be understood that when a layer, region, or component is referred to as being “formed on,” another layer, region, or component, it may be directly or indirectly formed on the other layer, region, or component. For example, for example, intervening layers, regions, or components may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation.

FIG. 1is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

Referring toFIG. 1, a display device10, according to an exemplary embodiment of the present disclosure, may include a display area AA in which an image is displayed, and a peripheral area PA outside of, and at least partially surrounding, the display area AA. Thus, the substrate100has the display area AA and the peripheral area PA.

A plurality of pixels PX and wirings for applying an electrical signal to the plurality of pixels PX may be disposed in the display area AA.

Each of the plurality of pixels PX may include a light-emitting device and a circuit portion for driving the light-emitting device. According to an exemplary embodiment of the present disclosure, the light-emitting device may be an organic light-emitting device, and the circuit portion may include a plurality of transistors and a capacitor, in addition to various other supporting elements.

The wirings for applying an electrical signal to the plurality of pixels PX may include a plurality of scan lines SL and a plurality of data lines DL. According to an exemplary embodiment of the present disclosure, the plurality of scan lines SL may be arranged in a plurality of rows and may transmit a scan signal to the pixels PX, and the plurality of data lines DL may be arranged in a plurality of columns and may transmit a data signal to the pixels PX. The plurality of pixels PX may be disposed in a portion where the plurality of scan lines SL and the plurality of data lines DL intersect each other.

Connection wirings200for transmitting the electrical signal supplied from a pad area PADA to the wirings connected to the pixels PX may be disposed in the display area AA. For example, the connection wirings200may be connected to the data lines DL and may transmit the data signal supplied from the pad area PADA to the data lines DL.

Meanwhile, because a length of one side of the display area AA adjacent to the pad area PADA (e.g. the vertical sides, as shown) is greater than a length of the pad area PADA (e.g. the bottom side, as shown), the connection wirings200have to be widely spread to correspond to one side of the display area AA at a position corresponding to the pad area PADA. To this end, the connection wirings200may extend in a first direction X, may be bent in a direction parallel to a second direction Y, perpendicular to the first direction X, may extend towards edges of the display area AA, and then may be bent in a direction parallel to the first direction X and may extend in the first direction X, as shown inFIG. 1. Thus, the data signal supplied from the center of one side of the display area AA may be transmitted to the data lines DL from an end of one side of the display area AA. Thus, the area of the peripheral area PA may be reduced compared to fan-out wirings according to the related art in the peripheral area PA, so that a dead space of the display device10may be reduced.

Meanwhile, the display area AA may be divided into a plurality of areas according to an extension direction of the connection wirings200. For example, the display area AA may include a first area S1in which the connection wirings200extend in the direction parallel to the first direction X, a second area S2in which the connection wirings200extend in the direction parallel to the second direction Y, and a third area S3that is the remaining area of the display area AA excluding the first area S1and the second area S2. The third area S3may be an area in which the connection wirings200are not disposed.

There may be a plurality of first areas S1and a plurality of second areas S2, and each of the plurality of first areas S1and the plurality of second areas S2may have a substantially triangular shape. For example, to prevent a short-circuit between the connection wirings200, an extension length of the connection wirings200that extend in the first direction X from the middle portion of the central, first area S1may be greater than the extension length of the connection wirings200that extend in the first direction X from edges of the first area S1. Thus, the entire shape of the first area S1may be a triangular shape. Also, because the connection wirings200may be bent in the direction parallel to the second direction Y and may extend from the central, first area, the shapes of the second areas S2at both sides of the central, first area S1may be inverted triangular shapes, and the connection wirings200may be bent in the −X-direction and may extend from the second areas S2. Thus, the first areas S1outside the second areas S2may have triangular shapes.

In the first areas S1and the second areas S2, extension directions of the connection wirings200are different from each other. As the connection wirings200may reflect light, reflection characteristics in the first areas S1and the second areas S2may be different from each other and this difference may be noticeable to a user who is viewing the display device10. As a result, the divisions within the display area AA where the first areas S1and the second areas S2meet may be recognized by a user. To reduce or prevent this phenomenon, the connection wirings200may include a plurality of branches that protrude in a direction perpendicular to the extension direction of the connection wirings200. Thus, the first areas S1and the second areas S2may include the same or similar patterns. Thus, a difference in the reflection characteristics between the first areas S1and the second areas S2may be reduced. This will be described later with reference toFIGS. 2 through 7.

The peripheral area PA may at least partially surround the display area AA. The peripheral area PA that is an area in which the pixels P are not disposed, may include the pad area PADA, to which a variety of electronic devices or printed circuit boards (PCBs) are electrically attached. A voltage line for supplying power for driving the light-emitting device may also be disposed in the peripheral area PA.

FIG. 1may be understood as a plan view illustrating the substrate100during a manufacturing process of the display device10. In an electronic device, such as a finished product display device10or a smartphone including the display device10, a portion of the substrate100may be bent back or behind the display area AA thereof so as to minimize the perceivable area of the peripheral area PA.

For example, as shown inFIG. 1, the peripheral area PA may include a bending area BA, and the bending area BA may be defined between the pad area PADA and the display area AA. In this case, the substrate100may be bent in the bending area BA so that at least some of the pad area PADA may at least partially overlap the display area AA. In this case, the bending direction of the pad area PADA is set so that the pad area PADA may be behind the display area AA. Thus, to the user, the display area AA may appear to make up most of the display device10. To this end, the substrate100may include various flexible/bendable materials.

FIG. 2is a plan view illustrating an example of a portion A ofFIG. 1, andFIG. 3is a plan view illustrating an example of a portion B ofFIG. 1. Hereinafter, exemplary embodiments of the present disclosure will be described with reference toFIGS. 1 through 3.

Referring toFIGS. 1 through 3, each of the connection wirings200may include a plurality of branches211(e.g.FIG. 3) and221(e.g.FIG. 3) that protrude in a direction perpendicular to a lengthwise direction of the connection wirings200. Hereinafter, for convenience of description, a display area will be divided into a first area S1and a second area S2.

As shown inFIG. 2, in the first area S1, the connection wirings200may extend in the direction parallel to the first direction X, and the first area S1may include first branches211that protrude in the second direction Y.

The first branches211protrude symmetrically from the connection wirings. For example, the first branches211protrude from the connection wirings that extend in the first direction X in a both-side direction perpendicular to the lengthwise direction of the connection wirings200. Also, a pair of first branches211that protrude from two adjacent connection wirings200among the connection wirings200arranged in parallel in the first area S1towards each other may be disposed in the same line. Thus, as shown inFIG. 2, in the first area S1, two adjacent connection wirings200and the first branches211that protrude towards each other may divide first unit patterns A1. However, to prevent a short-circuit between the connection wirings200, ends of the first branches211that extend from the two adjacent connection wirings200towards each other are spaced apart from each other.

Also, as shown inFIG. 3, in the second area S2, the connection wirings200may extend in the direction parallel to the second direction Y, and the second area S2may include second branches221that protrude in the first direction X.

The second branches221protrude from the connection wirings that extend in the second direction to be symmetrical to each other. Also, a pair of second branches221that protrude from two adjacent connection wirings200towards each other in the second area S2may be disposed in the same line. Thus, as shown inFIG. 3, in the second area S2, two adjacent connection wirings200and the second branches221that protrude from the two adjacent connection wirings200towards each other may divide second unit patterns A2. However, to prevent a short-circuit between the connection wirings200, ends of the second branches221that extend from the two adjacent connection wirings200towards each other are spaced apart from each other.

Thus, one first unit pattern A1in the first area S1and one second unit pattern A2in the second area S2may have similar shapes. For example, there is only a difference that, in the first unit patterns A1, a gap is formed between the first branches211that extend towards each other, and in the second unit patterns A2, a gap is formed between the second branches221that extend towards each other, and the first unit pattern A1and the second unit pattern A2may have the same areas, and a total length of the connection wirings200that surround the first unit pattern A1and the first branches211may be the same as a total length of the connection wirings200that surround the second unit pattern A2and the second branches221.

Thus, reflection characteristics of light in the first area S1and the second area S2are similar to each other. Thus, a phenomenon in which a display area is divided into the first area S1and the second area S2, according to incidence angles of light and recognized, may be prevented or minimized.

A third area S3may include first unit patterns A1or/and second unit patterns A2. Thus, a phenomenon in which a viewer may be able to distinguish the third area S3from the first area S1and the second area S2may be prevented. For example, because the third area S3is in contact with the second area S2having an inverted triangular shape and is continuous to the second area S2, when the third area S3includes the second unit patterns A2, the phenomenon in which a viewer may be able to distinguish the third area S3from the first area S1and/or the second area S2may be more effectively prevented.

When the third area S3includes the first unit patterns A1or/and the second unit patterns A2, the first unit patterns A1and/or the second unit patterns A2included in the third area S3may be in floating states.

First and second dummy patterns230and240may be further disposed inside the first unit patterns A1and the second unit patterns A2. The first and second dummy patterns230and240may be disposed between the two adjacent connection wirings200and disposed in the same layer as a layer in which the connection wirings200are disposed. InFIGS. 2 and 3, the first dummy patterns230and the second dummy patterns240are disposed inside the first unit patterns A1and the second unit patterns A2, respectively. However, the present invention is not limited thereto, and dummy patterns having a variety of numbers and shapes may be used. The dummy patterns230and240may prevent signal interference between the circuit portion and the connection wirings200from occurring, and may secure a pattern density so that the device may be more easily manufactured.

FIG. 4is a plan view illustrating another example of the portion A ofFIG. 1, andFIG. 5is a plan view illustrating another example of the portion B ofFIG. 1. Hereinafter, this will be described with reference toFIGS. 1, 4, and 5.

Referring toFIGS. 1, 4, and 5, each of the connection wirings200may include a plurality of branches211and221that protrude in the direction perpendicular to the lengthwise direction of the connection wirings200. As shown inFIG. 4, the connection wirings200that extend from the first area S1in the first direction X, may include the first branches211that protrude in the second direction Y and as shown inFIG. 5, the connection wirings200that extend from the second area S2in the second direction Y may include the second branches221that protrude in the first direction X so that reflection characteristics of light in the first area S1and the second area S2may be similar to each other and a phenomenon in which the display area is visibly divided into the first area S1and the second area S2may be prevented or minimized. Thus, only differences between what is shown inFIGS. 4 and 5as compared the above description will be described and it is to be understood that to the extent that details have been omitted for certain elements, those elements may be at least similar to corresponding elements that have already been described. Also, for convenience of description, a display area will be divided into the first area S1and the second area S2.

Referring toFIGS. 4 and 5, in the first area S1, a gap may be formed between the first branches211that extend from the two adjacent connection wirings200towards each other. In the second area S2, a gap may be formed between the second branches221that extend from the two adjacent connection wirings200towards each other. In this case, first cover patterns213that cover the gap between the first branches211may be further disposed in the first area S1, and second cover patterns223that cover the gap between the second branches221may be further disposed in the second area S2.

For example, the first cover patterns213may at least partially overlap ends of the first branches211that face each other, in the first direction X, i.e., in the same direction as the extension direction of the connection wirings200and may be apart from the ends of the first branches211that face each other, so as to prevent a short-circuit of the two adjacent connection wirings200. Also, the first cover pattern213may be connected to the first dummy patterns230or the second dummy patterns240so as to fix positions of the first cover patterns213. InFIG. 4, based on the drawings, the first cover patterns213may be disposed at a lower position than the first branches211and may be connected to the first dummy patterns230. However, the present invention is not limited thereto, and the first cover patterns213may be disposed at an upper position than the first branches211and may be connected to the second dummy patterns240based on the drawings.

Similarly, as shown inFIG. 5, the second cover patterns223may at least partially overlap ends of the second branches221in the second direction Y, i.e., in the same direction as an extension direction of the connection wirings200and may be spaced apart from the ends of the second branches221so as to prevent a short-circuit of the two adjacent connection wirings200. Also, the second cover patterns223may be connected to the first dummy patterns230or the second dummy patterns240so as to fix the positions of the second cover patterns223.

In this way, when the first cover patterns213that overlap the ends of the first branches211are further disposed in the first area S1and the second cover patterns223that overlap the ends of the second branches221are further disposed in the second area A1, shapes of the patterns included in the first area S1and the second area S2may be more similar to each other. Thus, a phenomenon in which, when the position of the gap between the first branches211in the first area S1and the position of the gap between the second branches221in the second area S2are different from each other, reflectivities of incident lights at certain angles may be different from each other, may be prevented. Thus, a phenomenon in which a display area may be divided into the first area S1and the second area S2and recognized, may be more effectively prevented. The first cover patterns213and the second cover patterns223may be disposed in the same layer as the layer in which the connection wirings200are disposed.

FIG. 6is a plan view illustrating another example of the portion A ofFIG. 1, andFIG. 7is a plan view illustrating another example of the portion B. Hereinafter, this will be described with reference toFIGS. 1, 6, and 7.

Referring toFIGS. 1, 6, and 7, each of the connection wirings200may include a plurality of first and second branches211and221that protrude in the direction perpendicular to the lengthwise direction of the connection wirings200. Also, each of the connection wirings200may include a plurality of first and second slices201and202that are spaced apart from each other in the direction parallel to the extension direction of the connection wirings200and a plurality of bridges250and252that electrically connect the plurality of slices201and202to each other (e.g. bridges250connect slices201to slices201and bridges252connect slices202to slices202). In this case, the plurality of first and second branches211and221may protrude from the plurality of slices201and202. Hereinafter, for convenience of description, a display area will be divided into the first area S1and the second area S2.

First, as shown inFIG. 6, each of the connection wirings200that extend in the first direction X in the first area S1may include the plurality of first slices201that are spaced apart from each other in the first direction X and a plurality of first bridges250that electrically connect the plurality of first slices201. The plurality of first bridges250may be disposed in a different layer from a layer in which the plurality of first slices201are disposed, and may be electrically connected to the first slices201via a contact hole C.

Also, as shown inFIG. 7, each of the connection wirings200that extend in the second direction Y may include the plurality of second slices202in the second area S2, and the plurality of second slices202may be electrically connected to each other via the contact hole C using the plurality of second bridges252.

As shown inFIG. 6, a pair of first branches211may protrude from each of the plurality of first slices201in opposite directions and may at least partially overlap ends of a pair of first branches211in which dummy bridges extend towards each other. The dummy bridges in the first area S1may be the same as the second bridges252. However, the first bridges250may be electrically connected to the first slices201via the contact hole C, whereas the second bridges252might not be connected to the first branches211and may be in insulated states. To this end, an insulating layer may be disposed between ends of the second bridges252and the pair of first branches211. Thus, the connection wirings200that extend in the first direction X in the first area S1may be prevented from being short circuited to each other via the first branches211.

Also, each of the plurality of second slices202may include the second branches221that protrude from the second slices202in the direction perpendicular to the second direction Y, and dummy bridges may be disposed at a position where they overlap ends of a pair of second branches221that extend towards each other. The first bridges250may be dummy bridges in the second area S2. The first bridges250that are dummy bridges might not be connected to the second branches221and may be in an insulated state. Thus, the connection wirings200that extend in the second direction Y may be prevented from being short circuited to each other via the second branches221.

For example, in the first area S1and the second area S2, the first bridges250and the second bridges252are disposed at the same position. However, in the first area S1, only the first bridges250might be electrically connected to the first slices201via the contact hole C, and the second bridges252are dummy bridges. On the other hand, in the second area S2, only the second bridges252might be electrically connected to the second slices202via the contact hole C, and the first bridges250are dummy bridges. Thus, the first area S1and the second area S2include patterns having the same shapes. Thus, reflection characteristics in the first area S1and the second area S2may be the same, and accordingly, a phenomenon in which a display area is visibly divided into the first area S1and the second area S2may be prevented.

The first bridge250and the second bridge252may be disposed on the connection wirings200. The first bridge250and the second bridge252may be formed of a transparent material, such as an indium tin oxide (ITO) or an opaque material. According to an exemplary embodiment of the present disclosure, the first bridge250and the second bridge252may also be disposed under the connection wirings200. According to an exemplary embodiment of the present disclosure, the first bridge250and the second bridge252may be disposed in the same layer in which a source electrode and a drain electrode of a thin-film transistor (TFT) that will be described later are disposed, or in the same layer in which a gate electrode of the TFT is disposed.

A description of the third area S3including the same patterns as those of the first area S1or the second area S2is the same as the above description.

FIG. 8is an equivalent circuit diagram of one pixel of the display device ofFIG. 1. As shown inFIG. 8, one pixel PX may include a plurality of TFTs T1, T2, T3, T4, T5, T6, and T7, a capacitor Cst, and an organic light-emitting device (OLED). The plurality of TFTs T1, T2, T3, T4, T5, T6, and T7or the capacitor Cst may be included in the circuit portion of the pixel PX. The pixel portion is electrically connected to a plurality of signal lines121,122,123,124, and171and a power supply line172.

The TFTs may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, an initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a bypass TFT T7.

The plurality of signal lines may include a scan line121for transmitting a scan signal Sn, a previous scan line122for transmitting a previous scan signal Sn−1 to the initialization TFT T4and the bypass TFT T7, an emission control line123for transmitting an emission control signal En to the operation control TFT T5and the emission control TFT T6, a data line171that intersects the scan line121and transmits a data signal Dm, and an initialization voltage line124that transmits an initialization voltage Vint for initializing the driving TFT T1.

The driving TFT T1receives the data signal Dm according to a switching operation of the switching TFT T2and supplies a driving current IOLEDto the OLED. A gate electrode G1of the driving TFT T1may be connected to a capacitor lower electrode Cst1of the capacitor Cst. A source electrode S1of the driving TFT T1may pass through the operation control TFT T5and may be connected to the power supply line172. The driving electrode D1of the driving TFT T1may pass through the emission control TFT T6and may be electrically connected to a pixel electrode of the OLED.

A gate electrode G2of the switching TFT T2may be connected to the scan line121. A source electrode S2of the switching TFT T2may be connected to the data line171. A drain electrode D2of the switching TFT T2may be connected to the source electrode S1of the driving TFT T1, may pass through the operation control TFT T5, and may be connected to the power supply line172. The switching TFT T2may be turned on according to the scan signal Sn transmitted via the scan line121and may perform a switching operation of transmitting the data signal Dm transmitted to the data line171to the source electrode S1of the driving TFT T1.

A gate electrode G3of the compensation TFT T3may be connected to the scan line121. A source electrode S3of the compensation TFT T3may be connected to the drain electrode D1of the driving TFT T1, may pass through the emission control TFT T6, and may be connected to the pixel electrode of the OLED. A drain electrode D3of the compensation TFT T3may be connected to the capacitor lower electrode Cst1of the capacitor Cst, a drain electrode D4of the initialization TFT T4and the gate electrode G1of the driving TFT T1. The compensation TFT T3may be turned on according to the scan signal Sn transmitted via the scan line121and may electrically connect the gate electrode G1to the drain electrode D1of the driving TFT T1, thereby diode-connecting the driving TFT T1.

A gate electrode G4of the initialization TFT T4may be connected to the previous scan line122. A source electrode S4of the initialization TFT T4may be connected to a drain electrode D7of the bypass TFT T7and the initialization voltage line124. A drain electrode D4of the initialization TFT T4may be connected to the capacitor lower electrode Cst1of the capacitor Cst, the drain electrode D3of the compensation TFT T3, and the gate electrode G1of the driving TFT T1. The initialization TFT T4may be turned on according to the previous scan signal Sn−1 transmitted via the previous scan line122and may perform an initialization operation of transmitting the initialization voltage Vint to the gate electrode G1of the driving TFT T1and initializing a voltage of the gate electrode G1of the driving TFT T1.

A gate electrode G5of the operation control TFT T5may be connected to the emission control line123. A source electrode S5of the operation control TFT T5may be connected to the power supply line172. A drain electrode D5of the operation control TFT T5may be connected to the source electrode S1of the driving TFT T1and the drain electrode D2of the switching TFT T2.

A gate electrode G6of the emission control TFT T6may be connected to the emission control line123. A source electrode S6of the emission control TFT T6may be connected to the drain electrode D1of the driving TFT T1and the source electrode S3of the compensation TFT T3. A drain electrode D6of the emission control TFT T6may be electrically connected to the source electrode S7of the bypass TFT T7and the pixel electrode of the OLED. The operation control TFT T5and the emission control TFT T6may be simultaneously turned on according to the emission control signal En transmitted via the emission control line123and may allow a driving voltage ELVDD to be transmitted to the OLED so that the driving IOLEDmay flow through the OLED.

A gate electrode G7of the bypass TFT T7may be connected to the previous scan line122. A source electrode S7of the bypass TFT T7may be connected to a drain electrode D6of the emission control TFT T6and the pixel electrode of the OLED. A drain electrode D7of the bypass TFT T7may be connected to the source electrode S4of the initialization TFT T4and the initialization voltage line124. The bypass TFT T7receives the previous scan signal Sn−1 transmitted via the previous scan line122from the gate electrode G7. When an electrical signal of a voltage at a certain level at which the bypass TFT T7may be turned off, is applied from the previous scan signal Sn−1, the bypass TFT T7may be in an off state so that some of the driving current Idmay be discharged as a bypass current Ibpvia the bypass TFT T7.

Even when a minimum current of the driving TFT T1that displays a black image flows as a driving current and the OLED emits light, the black image might not be properly displayed. Here, the minimum current of the driving TFT T1refers to a current having conditions on that a gate-source voltage VGS of the driving TFT T1is smaller than a threshold voltage Vth and the driving TFT T1is turned off. Thus, even when the minimum current flows as the driving current, to prevent the OLED from emitting light, the bypass TFT T7may disperse some of the current Idthat flows from the driving TFT T1as the bypass current Ibpalong other current paths than the current path toward the OLED. A smaller current than the minimum driving current (for example, a current that is equal to or smaller than 10 pA) on conditions that the driving TFT T1is turned off, may be transmitted to the OLED so that the OLED might not emit light or a degree of emission may be minimized and thus the black image may be realized.

InFIG. 8, the initialization TFT T4and the bypass TFT T7are connected to the previous scan line122. However, the present invention is not limited thereto. According to an exemplary embodiment of the present disclosure, the initialization TFT T4may be connected to the previous scan line122, may be driven according to the previous scan signal Sn−1, and the bypass TFT T7may be connected to an additional wiring and may be driven according to a signal transmitted to the wiring.

A capacitor upper electrode Cst2of the capacitor Cst may be connected to the power supply line172, and an opposite electrode of the OLED may be connected to a common voltage ELVSS. Thus, the OLED may receive the driving current IOLEDfrom the driving TFT T1and may emit light.

InFIG. 8, the compensation TFT T3and the initialization TFT T4have a dual gate electrode. However, the present invention is not limited thereto. For example, the common TFT T3and the initialization TFT T4may have one gate electrode. Also, various other modifications may be made to at least one of the remaining TFTs T1, T2, T5, T6, and T7.

FIG. 9is a layout view illustrating positions of thin-film transistors (TFTs) and a capacitor in a pixel included in the display device ofFIG. 1,FIGS. 10 through 14are layout views illustrating elements, such as a plurality of TFTs and a capacitor ofFIG. 9according to layers, andFIG. 15is a cross-sectional view illustrating some of the display device ofFIG. 1.

Hereinafter, a detailed structure of the display device ofFIG. 1will be described with reference toFIGS. 9 through 15.

FIG. 9illustrates positions of TFTs and a capacitor of each of a first pixel PX1in the first area (see S1ofFIG. 1) and a second pixel PX2in the second area (see S2ofFIG. 1), andFIGS. 10 through 14illustrate various elements, such as TFTs and a capacitor of each of the first pixel PX1and the second pixel PX2, according to layers. Also,FIG. 15that is a cross-sectional view illustrating some of the display device ofFIG. 1, for convenience, illustrates a cross-section taken along a line I-I′ that passes through an opening OP indicated only in the first pixel PX1ofFIG. 14.

As shown inFIG. 15, the display device includes a substrate100.

The substrate100may include a variety of flexible or bendable materials. For example, the substrate100may include polymer resin, such as polyethersulphone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC) and/or cellulose acetate propionate (CAP). It is to be understood that the substrate100may be modified in various ways like having a multi-layer structure including two layers including such polymer resin and a barrier layer including an inorganic material (silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON)) between the two layers.

A plurality of pixels including the first pixel PX1and the second pixel PX2may be disposed on the substrate100. A buffer layer101may be disposed in the substrate100. The buffer layer101may planarize a surface of the substrate100and/or may prevent impurities from penetrating into a semiconductor layer thereon. The buffer layer101may have a single layer structure or multi-layer structure including an inorganic insulating material such as SiOx, SiNx, and/or SiON.

The semiconductor layer may be disposed on the buffer layer101. The semiconductor layer may have various bent shapes, as shown inFIG. 10, and the first pixel PX1and the second pixel PX2may have semiconductor layers having the same shape. Hereinafter, unless otherwise specified, it may be assumed that layers of each of the first pixel PX1and the second pixel PX2have the same shape.

The semiconductor layer may include a driving channel area131athat corresponds to the driving TFT T1, a switching channel area131bthat corresponds to the switching TFT T2, compensation channel areas131c1,131c2, and131c3that correspond to the compensation TFT T3, initialization channel areas131d1,131d2, and131d3that correspond to the initialization TFT T4, an operation control channel area131ethat corresponds to the operation control TFT T5, an emission control channel area131fthat corresponds to the emission control TFT T6, and a bypass channel area131gthat corresponds to the bypass TFT T7. For example, the driving channel area131a, the switching channel area131b, the compensation channel areas131c1,131c2, and131c3, the initialization channel areas131d1,131d2, and131d3, the operation control channel area131e, the emission control channel area131f, and the bypass channel area131gmay be some of the areas of the semiconductor layer shown inFIG. 10.

The semiconductor layer may include polysilicon. The semiconductor layer may include source areas and drain areas formed by doping impurities at both sides of the channel area. Here, the impurities may be changed according to the type of a TFT and may include N-type impurities or P-type impurities. A channel area, a source area at one side of the channel area, and a drain area at the other side of the channel may be referred to collectively as an active layer. For example, the TFT may have an active layer, and the active layer may include a channel area, a source area, and a drain area.

The source area or drain area formed by doping may be interpreted as either a source electrode or drain electrode of the TFT. For example, the driving source electrode may correspond to a driving source area176ainto which an impurity is doped, near the driving channel area131ain the semiconductor layer shown inFIG. 10, and the driving drain electrode may correspond to a driving drain area177ainto which an impurity is doped, near the driving channel area131ain the semiconductor layer shown inFIG. 10.

A gate insulating layer320formed of an inorganic insulating material, such as SiOx, SiNx, or SiON, may be disposed in an upper portion of the semiconductor layer.

Conductive layers, such as the gate electrode125aare disposed on the gate insulating layer320. Various other conductive layers may be disposed on the gate insulating layer320. In this way, various conductive layers disposed on the gate insulating layer320may be referred to as a gate wiring. The gate wiring may include a scan line121, a previous scan line122, an emission control line123, and a capacitor lower electrode, as shown inFIG. 11.

The capacitor Cst may at least partially overlap the driving TFT T1. In this case, the capacitor's lower electrode may be a gate electrode125aof the driving TFT T1. Thus, the area of the capacitor Cst and the driving TFT T1may be increased, and a high-quality image may be provided. However, the present invention is not limited thereto. According to an exemplary embodiment of the present disclosure, the capacitor Cst might not overlap the driving TFT T1, and the capacitor lower electrode may be a separate independent element from the gate electrode125aof the driving TFT T1.

As shown inFIG. 11, the switching gate electrode125band the compensation gate electrodes125c1and125c2may be portions of the scan line121that intersects the semiconductor layer, or portions protruding from the scan line121, and the initialization gate electrodes125d1and125d2and the bypass gate electrode125gmay be portions of the previous scan line122that intersects the semiconductor layer, or portions protruding from the previous scan line122, and the operation control gate electrode125eand the emission control gate electrode125fmay be portions of the emission control line123that intersects the semiconductor layer, or portions protruding from the emission control line123.

A first interlayer insulating layer331may cover a gate wiring. The first interlayer insulating layer331may be formed of an inorganic insulating material, such as SiNx, SiOx, and/or SiON.

A capacitor's upper electrode127may be disposed on the first interlayer insulating layer331. However, the initialization voltage line124may be disposed in the same layer as a layer in which the capacitor upper electrode127is disposed.

As shown inFIG. 12, an opening27may be formed in the capacitor's upper electrode127. Thus, the capacitor's lower electrode and a compensation drain area177cof the compensation TFT T3may be electrically connected to each other using a connection member174to be described later.

A second interlayer insulating layer332is disposed on the capacitor upper electrode127. The second interlayer insulating layer332may be formed of an inorganic insulating material, such as SiNx, SiOx, and/or SiON.

The power supply line172may be disposed on the second interlayer insulating layer332. The power supply line172may be connected to the capacitor upper electrode127via a contact hole168formed in the second interlayer insulating layer332and may be connected to the semiconductor layer thereunder via contact holes165and169formed in the gate insulating layer320, the first interlayer insulating layer331, and the second interlayer insulating layer332.

Various conductive layers other than the power supply line172may be disposed on the second interlayer insulating layer332. For example, as shown inFIG. 13, the data line171, an initialization connection line173, the connection member174, and the drain electrode175may be formed on the second interlayer insulating layer332.

The data line171may be connected to a switching source area176bvia the contact hole164formed in the gate insulating layer320, the first interlayer insulating layer331, and the second interlayer insulating layer332.

One end of the initialization connection line173may be connected to the initialization voltage line124via the contact hole161formed in the first interlayer insulating layer331and the second interlayer insulating layer332. The other end of the initialization connection line173may be connected to the initialization source area176dvia the contact hole162formed in the gate insulating layer320, the first interlayer insulating layer331, and the second interlayer insulating layer332. The initialization drain area177dmay be a portion of the semiconductor layer into which an impurity at an opposite side to the initialization source area176dbased on the initialization channel area131dis doped.

One end of the connection member174may be connected to the compensation drain area177cand the initialization drain area177dvia the contact hole166formed in the gate insulating layer320, the first interlayer insulating layer331, and the second interlayer insulating layer332, and the other end of the connection member174may be connected to the capacitor lower electrode via the contact hole167formed in the first interlayer insulating layer331and the second interlayer insulating layer332. In this case, the other end of the connection member174may be connected to the capacitor lower electrode via an opening27formed in the capacitor upper electrode127.

The drain electrode175may be connected to the emission control drain area177fvia a contact hole163formed in the gate insulating layer320, the first interlayer insulating layer331, and the second interlayer insulating layer332. The drain electrode175may be electrically connected to the pixel electrode410. A source electrode excluding the drain electrode175may be disposed on the second interlayer insulating layer332.

A first organic insulating layer341may be disposed on the power supply line172and the drain electrode175, and the connection wirings200and the dummy patterns230and240may be formed on the first organic insulating layer341, as shown inFIG. 14. Also, a second organic insulating layer342may be disposed on the connection wirings200and the dummy patterns230and240.

The connection wirings200and the dummy patterns230and240may have a single layer structure or multi-layer structure including aluminum (Al), copper (Cu), titanium (Ti), and/or an alloy thereof.

In the first pixel PX1, the connection wirings200extend in a direction parallel to the first direction X. For example, the connection wirings200may at least partially overlap the power supply line172. The first branches211that protrude from the connection wirings200in a direction perpendicular to the lengthwise direction of the connection wirings200may at least partially overlap the initialization voltage line124in one example.

In the second pixel PX2, the connection wirings200may extend in the direction parallel to the second direction Y, and the second branches221may protrude from the connection wirings200. For example, in the second pixel PX2, the connection wirings200may at least partially overlap the initialization voltage line124, and the second branches221may at least partially overlap the power supply line172.

Thus, patterns formed by the connection wirings200and the first branches211in the first pixel PX1and patterns formed by the connection wirings200and the second branches221in the second pixel PX2are similar to each other. Thus, a phenomenon in which a display area may be divided into the first area S1and the second area S2and recognized according to an incidence angle of light, may be prevented or minimized.

The first dummy patterns230and the second dummy patterns240may prevent signal interference between the circuit portion and the connection wirings200, as described above, and may secure a pattern density, thereby providing a simplified manufacturing process.

InFIG. 14, the connection wirings200described with reference toFIGS. 2 and 3are used. However, the display device may include the connection wirings200described with reference toFIGS. 4 through 7.

A light-emitting device400may be disposed on the second organic insulating layer342, wherein the light-emitting device400may include a pixel electrode410, a common electrode430, and an intermediate layer420interposed between the pixel electrode410and the common electrode430and including an emission layer. The light-emitting device400may be an OLED, for example.

A pixel-defining layer350for covering edges of the pixel electrode410may be disposed on the second organic insulating layer342. The pixel-defining layer350may have an opening OP corresponding to each of pixels, i.e., an opening OP through which at least the center of the pixel electrode410is exposed, thereby defining a pixel. Also, the pixel-defining layer350increases a distance between the edges of the pixel electrode410and the common electrode430, thereby preventing electrical arcing from occurring therebetween. The pixel-defining layer350may be formed of an organic material, such as polyimide or hexamethyldisiloxane (HMDSO).

The intermediate layer420may be formed on the pixel electrode410exposed through the opening OP of the pixel-defining layer350. The intermediate layer420may include a small molecular weight material or polymer material. When the intermediate layer420includes a small molecular weight material, the intermediate layer420may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL) are stacked in a single or composite structure. The intermediate layer420may include various organic materials including copper phthalocyanine (CuPc), N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum)(Alq3). These layers may be formed through a method such as vacuum deposition.

When the intermediate layer420includes a polymer material, the intermediate layer420may have a structure including mostly an HTL and an EML. In this case, the HTL may include poly-3,4-alkenedioxythiophene (PEDOT), and the EML may include a poly-phenylenevinylene (PPV)-based and polyfluorene-based polymer material. The structure of the intermediate layer420is not limited to the above description but the intermediate layer420may have various different structures. For example, the intermediate layer420may include a layer integrally formed in the plurality of pixel electrodes410or may include a patterned layer to correspond to each of the plurality of pixel electrodes410.

The common electrode430may cover a display area (see AA ofFIG. 1). For example, the common electrode430may be formed as one body so as to cover the plurality of light-emitting devices400. The common electrode430may be a (semi-)transparent electrode or reflective electrode. When the common electrode430is a (semi-)transparent electrode, the common electrode430may have a layer formed of metal having a small work function, e.g., Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, (or another material having a work function within a range established by the aforementioned materials) and/or a compound thereof and a (semi-)transparent conductive layer such as ITO, IZO, ZnO or In2O3. When the common electrode430is a reflective electrode, the common electrode430may have a layer formed of Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and/or a compound thereof. The configuration and material of the common electrode430are not limited thereto, and various modifications are possible.

As described above, as connection wirings for transmitting a data signal to a data line are disposed within a display area, a dead space of a display device may be reduced. Also, reflection characteristics of light are the same or similar in the entire display area. Thus, a phenomenon in which an area in which connection wirings are disposed, becomes noticeable, may be prevented.

While various exemplary embodiments of the present disclosure have been described herein with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.