Digital processor with programmable breakpoint/watchpoint trigger generation circuit

A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or sequences of trigger events. Several trigger event detection registers generate pre-trigger signals when stored trigger values (e.g., instruction addresses or data addresses/values) match addresses/values transmitted on busses within the processor core. Sum-of-products circuits generate intermediate combinational trigger signals in accordance with user-defined combinations of the pre-trigger signals. A finite state machine generates an intermediate sequential trigger signal in response to user-defined sequences of the intermediate combinational trigger signals. Either the intermediate combinational trigger signals or the intermediate sequential trigger signal are selectively passed to an action generator, which transmits an associated breakpoint or watchpoint trigger signal to a decode stage of the processor core or other destination.

FIELD OF THE INVENTION

The present invention relates generally to digital processor devices, and more particularly to a method and structure for improving the generation of breakpoint or watchpoint trigger signals in such processor devices.

BACKGROUND OF THE INVENTION

FIG. 1is a simplified block diagram showing a conventional digital processor100including a core section110, a data and address arbitration circuit120, and on-board memory components including a RAM130and a ROM135. Core section110includes various pipeline stages and associated registers including, a fetch stage112, decode stage114, an execute stage116, and a write back stage118. As would be understood by those skilled in the art, instructions to be executed on the processor are fetched or retrieved by means of hardware included in the fetch stage112. The instructions are then decoded in the decode stage114and executed in an appropriate sequence in the execute stage116. Instructions and data are transmitted to and from core110using an instruction address bus121, an instruction value bus123, a data address bus125, and a data value bus127. Data and address bus arbitration circuit120coordinates the transmission of data and instruction values from core110to on-board memory components (e.g., a RAM130and a ROM135), which are coupled to buses121,123,125, and127through the arbitration circuit120.

FIG. 2is a simplified diagram showing a Breakpoint/Watchpoint (BWP) trigger circuit140, which is typically included in many digital processors, such as processor100, to monitor instruction addresses or data addresses/values being fetched by the processor core during program execution, and to serve as part of a debugging tool used by programmers and software engineers (developers) during the development of complex programs.

BWP trigger circuit140typically includes one or more instruction address registers147and data address/value registers149that store user-defined addresses/values, and asserts one or more BWP trigger signals (BWP TRIGGER0through BWP TRIGGER3) when an associated “BWP trigger event” occurs (i.e., an address/value stored in registers147and149matches an address/value transmitted on buses121,125, or127). BWP trigger events generally fall into two categories: instruction BWP trigger events, and data BWP trigger events. Instruction BWP trigger events occur when an instruction is executed whose address (as transmitted on bus121) matches the address stored in programmable register147. Instruction BWP trigger events can either be Break Before Make (BBM) events, or Break After Make (BAM) events. BBM events occur when all instructions preceding the instruction associated with the pre-loaded address are retired (executed) by the processor (e.g., in decoder stage114of processor core110). BAM events occur when any architectural state is changed by executing the instruction associated with the pre-loaded address (e.g., in write back stage118). Data BWP trigger events occur when a data address transmitted on bus125and/or a data value transmitted on bus127matches the address/value stored in programmable register149.

The addresses/values stored in programmable registers147and149are typically set by a program developer as part of an interactive debugging operation used to scrutinize a program's execution. When the address of the code being fetched (or address/value of data being read/written) matches with the address/value stored in programmable registers147or149, then one or more associated BWP triggers are transmitted to either the core110(referred to herein as “breakpoint triggers”) or to an external system (“watchpoint triggers”). Thus, BWP trigger circuit140facilitates the software development process by allowing the developer to control core110(e.g., by executing a halt or trap) when a user-defined breakpoint trigger event occurs (e.g., at a specific processor state), or to generate an external signal indicating a specific processor state when a user-defined watchpoint trigger event occurs.

While conventional BWP trigger circuit140provides developers with a useful debugging tool, it is not flexible enough to generate BWP triggers in response to a complex sequence of trigger events. As discussed above, BWP trigger circuit140asserts associated BWP triggers when an instruction address or data address/value transmitted on an associated bus matches the values stored in registers147and149. However, as software programs become more complex, developers may wish to generate BWP triggers when a complex sequence of trigger events occurs (e.g., when a specific sequence of instructions are called/executed), something that is not possible with conventional BWP trigger circuit140.

What is needed is a BWP trigger circuit that provides a developer the option of generating BWP triggers in response to complex combinations of trigger events.

SUMMARY OF THE INVENTION

The present invention is directed to a digital processor including a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or sequences of instruction and/or data addresses/values utilized in the processor core, thereby facilitating substantially more flexible debugging operations for developing complex software programs than is possible using conventional BWP trigger circuits. In particular, the BWP trigger circuit includes a plurality of trigger event detection registers that generate pre-trigger signals in response to user-defined trigger events, and a programmable trigger logic circuit that generates intermediate (combinational) trigger signals in response to user-defined combinations of the pre-trigger signals, and/or generates an intermediate (sequential) trigger signal in response to a user-defined sequences of either the pre-trigger signals or the combinational trigger signals. The intermediate trigger signals are then passed to an action generator, which asserts an associated BWP trigger (e.g., a “halt” breakpoint command that is transmitted to a decoder stage of the processor core). Accordingly, the programmable BWP trigger circuit of the present invention facilitates highly flexible debugging operations during the development of a software program by allowing a developer to define a wide range of trigger event combinations and/or sequences for the generation of BWP triggers.

In accordance with an aspect of the present invention, the trigger event detection registers store binary trigger values (i.e., instruction addresses and/or data addresses/values), and monitor instruction addresses and/or data addresses/values transmitted on associated bus lines in the processor core. In one embodiment, the trigger event detection registers include instruction registers that store an instruction address trigger value (i.e., an instruction address or ranges of addresses) and monitor instruction address busses coupled to fetch and write back stages of the processor core, and data registers that store data addresses and data values (or ranges of addresses/values) and monitor data address/value busses coupled to the write back stage of the processor core. The data registers also include an optional mask register for masking unwanted data values. During a debugging operation, when a trigger event occurs (i.e., when an instruction address and/or data address/value transmitted on associated bus lines match the instruction address/range and/or data address/value/range stored in an associated trigger event detection registers), then the associated trigger event detection register asserts its pre-trigger signal (e.g., generates a logic 1). Conversely, each instruction register or data register that does not detect a trigger event maintains its associated pre-trigger signal in a de-asserted state (e.g., generates a logic 0).

In accordance with another aspect of the present invention, programmable trigger logic circuit includes one or more combinational function generators that generate intermediate (combinational) trigger signals in response to a set of pre-trigger signals generated by an associated group of trigger event detection registers. In one embodiment, each function generator is a 16-bit sum-of-products (SOP) circuit that is controlled by four pre-trigger signals. Each 16-bit SOP circuit implements a user-defined logic function of the four pre-trigger signals by storing sixteen bit values provided by the user/developer. During a debugging operation, the pre-trigger signals applied to each 16-bit SOP circuit address one of the sixteen stored bit values, which is generated at the SOP output terminal as a combinational trigger signal. When the bit value addressed by the four pre-trigger signals is a logic 1, then the combinational trigger signal is a logic 1. Conversely, when the bit value addressed by the four pre-trigger signals is a logic 0, then the combinational trigger signal is a logic 0.

In accordance with another aspect of the present invention, programmable trigger logic circuit includes one or more programmable state machines that generate intermediate (sequential) trigger signals in response to user-defined sequences of combinational trigger signals generated by an associated group of function generators. In one embodiment, the programmable state machine is a finite state machine defining four states, and receives four combinational trigger signals from four associated function generators. Each state includes a register for storing a user-defined two-bit value corresponding to the four combinational trigger signals. During a debugging operation, the combinational trigger signals are applied to the first state of the finite state machine. When the combinational trigger signal corresponding to the two-bit value stored by the first state is asserted, control is passed to the second state, and so on until a final state is reached. When the combinational trigger signal corresponding to the two-bit value stored by the final state is asserted, the sequential trigger signal associated with the finite state machine is asserted (e.g., logic 1).

In accordance with yet another aspect of the present invention, a user-programmable output circuit passes either the combinational trigger signals or the sequential trigger signal to the action generator for generation of the associated BWP trigger.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 3is a block diagram showing a simplified processor300in accordance with an embodiment of the present invention. Processor300includes a core310that communicates via a bus320with on-board memory components (e.g., a RAM330and a ROM335). Core310includes a program memory311for storing instructions associated with a developer's software program, a fetch stage312for fetching (retrieving) instructions to be executed, a decode stage314for decoding the fetched instructions, an execute stage316for executing the instructions is an appropriate order, a data memory318for temporarily storing data acted upon by execute stage316, and a write back stage319for writing data and instructions back to preceding sections of core310and to the on-board memory components. Instructions and data are transmitted to and from core310using bus320, which includes an instruction address bus321, an instruction value bus323, a data address bus325, and a data value bus327, portions of which are indicated in core310for descriptive purposes. An arbitration circuit (not shown) may be utilized in conjunction with bus320to facilitate communication between core310and the on-board memory. The operation of core310is generally known in the art and is beyond the scope of the present invention; therefore, a detailed description of core310is omitted for brevity.

In accordance with an aspect of the present invention, processor300also includes an on-chip debug support (OCDS) circuit340, which in the disclosed embodiment is incorporated into core310, but can be physically located away from the core area in some embodiments. The purpose of the OCDS circuit340is to generate breakpoint (BP) trigger signals (indicated as being directed to decode stage314) and watchpoint (WP) trigger signals (which are directed outside of core310) in response to user-defined trigger events occurring within core310, and also in response to external trigger events generated outside of core310. Of particular relevance to the present invention are the user-defined trigger events occurring within core310, and more particularly the instruction addresses and data addresses/values utilized in core310during program operation. In the embodiment shown inFIG. 3, OCDS circuit340receives first instruction address signals from fetch stage312via a first instruction bus portion321-BBM, and second instruction address signals from write back stage319via a second instruction bus portion321-BAM. OCDS circuit340also receives data address signals from write back stage319via a portion of data address bus325that is designated325-WB, and data value signals from write back stage319via a portion of data value bus327that is designated327-WB. The operation of OCDS circuit340to generate trigger signals in response to the data and instruction events transmitted via these busses is described below in additional detail. While other operations of OCDS circuit340are briefly mentioned below, a detailed discussion of OCDS circuit340operations in response to other (i.e., non-data and non-instruction based) trigger events occurring within core310, and in response to the external triggers, is omitted for brevity.

FIG. 4is a simplified block diagram showing OCDS circuit340in additional detail according to an embodiment of the present invention. OCDS circuit340includes a programmable trigger generator (PROG TRIGGER GEN) circuit410, an action generator (ACTION GEN) circuit420, and a performance measurement block430. Programmable trigger generator410and action generator420are discussed in detail below. Performance measurement block430includes counters that can be used for multiple purposes, such as measuring the time taken by core310to complete a given task, caching performance analysis information associated with for a given application, measuring MMU performance, and verifying architectural features. Because the operation of performance measurement block430is peripheral to the operation of trigger generator410and action generator circuit420, a detailed description of measurement block430is omitted for brevity.

Referring to the left side ofFIG. 4, programmable trigger generator410includes one or more programmable trigger generator (PTG) banks412-1through412-4, and an optional programmable trigger prioritization circuit415. Programmable trigger generator (PTG) banks412-1through412-4generate several trigger signals TS0–TS15in response to user-defined combinations or sequences of instruction addresses and/or data addresses/values processed transmitted on instruction address bus321, data address bus325-WB, and data value bus327-WB, respectively (note that “instruction address bus321” includes instruction addresses passed on both address bus321-BBM from fetch stage312and address bus321-BAM from write back stage319; seeFIG. 3). Because two or more of multiple trigger signals TS0–TS15can be generated simultaneously, a programmable trigger prioritization circuit415is provided to select an output programmable trigger (PROG TRIGGER) signal from such simultaneously asserted multiple trigger signals TS0–TS15according to predetermined hard-wired priority (although a user-programmable priority circuit may be used). As discussed in additional detail below, the output programmable trigger signal transmitted to action generator420includes an action identification that defines the action to be taken in response to the associated trigger signal TS0–TS15.

Action generator circuit420includes a trigger selection (e.g., multiplexing) circuit422and an action/trigger switch circuit425. Trigger selection circuit422passes either one of the external triggers or the programmable trigger (received from trigger generator410) to action/trigger switch425according to a predetermined priority. Each trigger passed to action/trigger switch425includes an action identification (ID)that corresponds to an associated BP trigger or WP trigger, and also includes source identification data and signals that specify whether the action is associated with a BBM or BAM action. Action/trigger switch425decodes the action ID associated with each trigger received from trigger selection circuit422, and asserts the associated BWP trigger that is transmitted either to core310(i.e., in the case of a BP trigger) or to an external pin of processor300(in the case of a WP trigger). For example, when a programmable trigger generated by programmable trigger generator410is passed by trigger selection circuit422having an action ID corresponding to a “trap” or “halt” breakpoint trigger action, then action/trigger switch asserts a TRAP signal or a HALT CPU signal that is passed to decoder314of core310(seeFIG. 1). Similarly, a programmable trigger having an action ID corresponding to a “breakout” or “suspend output” watchpoint trigger action, then action/trigger switch asserts a BREAKOUT PIN signal or a SUSPEND OUTPT signal that is passed to an appropriate register or other destination located outside of core310. Similar trigger actions are taken with respect to external triggers, such as a debug instruction, an external break-in signal, or a Move value To a Core Register (MTCR) or Move value FROM a Core Register (MFCR) instruction.

FIG. 5is a block diagram showing a portion of programmable trigger generator410in additional detail. In particular,FIG. 5shows the main circuit blocks associated with PTG bank412-1, which is representative of PTG banks412-2through412-4(seeFIG. 4). In accordance with an embodiment of the present invention, PTG bank412-1includes a trigger event detection (TED) circuit510and a programmable trigger logic circuit520. Similar to conventional BWP trigger circuits, TED circuit510monitors instruction addresses, data addresses, and data values transmitted on instruction address bus321, data address bus325-WB, and data value bus327-WB, respectively, and generates pre-trigger signals PT0through PT15when user-defined addresses/values are transmitted on these busses. In particular, TED circuit510is programmed by a developer to store predetermined instruction addresses, data addresses, and data values. During debug operations, the stored addresses/values are compared with instruction addresses, data addresses, and data values transmitted on busses321,325-WB, and327-WB, respectively. When the transmitted addresses/values match (or are within a range defined by) the stored addresses/values, an associated pre-trigger signal is generated that is passed to programmable trigger logic circuit520. Programmable trigger logic circuit520is also programmed by the developer to selectively detect logical combinations of pre-trigger signals and/or sequences thereof, and to generate associated triggers TE0through TE3when the user-defined logical combinations and/or sequences occur. Triggers TE0through TE3are then passed to programmable trigger prioritization circuit415(discussed above), which passes one of these triggers (or a trigger from another PTG bank) to action generator420(seeFIG. 4).

FIG. 6is a block diagram showing TED circuit510and programmable trigger logic circuit520of PTG bank412-1according to a specific embodiment of the present invention.

Referring to the left side ofFIG. 6, TED circuit510includes instruction register circuit610that monitors instruction addresses transmitted on instruction address (INST ADDR) bus321, and data register circuit620that monitors data addresses transmitted on data address (DATA ADDR) bus325-WB and data values transmitted on data value bus327-WB. Note that in dual pipeline processors, an additional instruction address bus associated with instructions passed from the fetch stage, as well as from the write back stage, to the decode stage on the second pipeline may also be monitored by instruction registers610using known techniques.

Instruction register circuit610includes a first register611for storing a first instruction address INST-ADD0and an optional upper range instruction address INST-ADD0-U. In a single-address operating mode, first register611asserts a pre-trigger signal PT0when an address transmitted on instruction address bus321matches instruction address INST-ADD0(in this mode upper range address INST-ADD0-U is empty or disabled). Alternatively, in a multiple-address operating mode, first register611asserts pre-trigger signal PT0when an address transmitted on instruction address bus321falls within a range defined by instruction addresses INST-ADD0and INST-ADD0-U. Similarly, instruction register circuit610includes a second register615for storing a second instruction address INST-ADD1and an optional upper range instruction address INST-ADD1-U, and generates a pre-trigger signal PT1when an address transmitted on instruction address bus321matches instruction address INST-ADD1(or falls within the range defined by INST-ADD1and INST-ADD1-U).

Similar to instruction register circuit610, data register circuit620includes a first register621for storing a first data address DATA-ADD0and a first upper range address DATA-ADD0-U, and a second register625for storing a second data address DATA-ADD1and a second upper range address DATA-ADD1-U. In addition, first register621also stores a first data value DATA-VAL0and an optional first mask value MASK0, and second register625also stores a second data value DATA-VAL1and an optional second mask value MASK1. Mask values MASK0and MASK1facilitate masking a portion or all of data values DATA-VAL0and DATA-VAL1, thereby causing data register circuit620to operate in essentially the same manner as instruction register610(described above). In particular, first register621generates a pre-trigger signal PT2when a data address transmitted on data address bus325-WB matches data address DATA-ADD0(or falls within the range defined by DATA-ADD0and DATA-ADD0-U), and second register625generates a pre-trigger signal PT3when a data address transmitted on data address bus325-WB matches data address DATA-ADD1(or falls within the range defined by DATA-ADD1and DATA-ADD1-U). Some or all of the data values DATA-VAL0and DATA-VAL1can also be included in these comparison processes by associated use of mask values MASK0and MASK1. For example, first register621can be programmed to match a particular data address transmitted on data address bus325-WB and four bits of a data value transmitted on data value bus327-WB by storing the desired data address as DATA-ADD0, storing the four bits in DATA-VAL0, and setting mask value MASK0to mask all but these four bits.

Referring to the right side ofFIG. 6, the four pre-trigger signals PT0through PT3generated by TED circuit510are transmitted to four 16-bit function generators (FGs)630-1through630-3of programmable trigger logic circuit520. 16-bit FGs630-1through630-4are programmable combinational logic circuits that generate intermediate (combinational) triggers CT0through CT3according to programmed functions of pre-triggers PT0through PT3. In other words, combinational triggers CT0through CT3can be expressed as:

where f0, f1, f2, and f3are any logical function of PT0, PT1, PT2and PT3. Combinational triggers CT0through CT3that are either passed to a programmable state machine640, or selectively converted by output switch circuit650to generate triggers TE0through TE3. As discussed in additional detail below, programmable state machine640is programmed to generate a sequential trigger signal ST when a programmed sequence of combinational triggers is satisfied. When programmable state machine640is utilized, output switch circuit650generates an associated trigger (e.g., TE0) in response to sequential trigger signal ST (in this case, three unused triggers, e.g., TE1through TE3, are disabled or otherwise unused).

FIG. 7is a simplified diagram depicting a 16-bit sum-of-products circuit700that serves as 16-bit FG630-1according to a specific embodiment of the present invention. In particular, SOP circuit700includes sixteen registers REG0through REG15that store an associated bit (i.e., 0 or 1). Each register is coupled to input terminals of a first set of two-input MUXs, each designated M1, that are controlled by pre-trigger PT3. The output terminals of MUXs M1are connected to input terminals of a second set of two-input MUXs, each designated M2, that are controlled by pre-trigger PT2. Similarly, the output terminals of MUXs M2are connected to input terminals of two-input MUXs M3, which are controlled by pre-trigger PT1, and the output terminals of MUXs M3are connected to input terminals of two-input MUX M4, which is controlled by pre-trigger PT0. By storing appropriate values in registers REG0through REG15, 16-bit SOP circuit700is capable of implementing any logical function of pre-trigger signals PT0through PT3. For example, to define CT0=(PT0or PT1) and (PT2or PT3), then CT0would be TRUE (i.e. binary value 1) in all the cases set forth in Table 1 (below):

To assert combinational trigger signal CT0under the conditions set forth in Table 1, a logic 1 is stored in each register REG5through REG7, REG9through REG11, and REG13through REG15. One of these logic 1 values is, in effect, passed from its associated register through the series of MUXes shown inFIG. 7when any of the combinations of pre-triggers shown in Table 1 is satisfied. Those of ordinary skill in the art will recognize that sum-of-products circuits other than the specific arrangement shown inFIG. 7can be used to provide a similar programmable function, so SOP circuit700is therefore not intended to be limiting.

Referring briefly toFIG. 6, each of the combinational trigger signals CT0through CT1is applied to output switch650, and also to programmable state machine640.

FIG. 8is a finite state machine diagram representation depicting programmable state machine640according to an embodiment of the present invention. State machine640includes four states: start point SP, first intermediate point IP0, second intermediate point IP1, and end point EP. Of course, state machine640can be implemented with any arbitrary number of states. Each state is assigned a two-bit code (i.e., having a value of zero to three) that identifies one of the four combinational trigger signals CT0through CT3, and passes control to an associated next sequential state when the combinational trigger signal identified by the stored two-bit code is asserted. For example, assuming start point SP stores the two-bit code “00”, control is retained by start point SP until combinational trigger signal CT0is asserted, at which point control is passed on path810from start point SP to first intermediate point IP0. Subsequently, control is retained by first intermediate point IP0until a combinational trigger signal matching the two-bit code associated with first intermediate point IP0is asserted, at which point control is passed on path820from second intermediate point IP0to second intermediate point IP1. Next, control is retained by second intermediate point IP1until a combinational trigger signal matching the two-bit code associated with second intermediate point IP1is asserted, at which point control is passed on path830from second intermediate point IP1to end point EP. Finally, after control is passed to end point EP, control is retained until a combinational trigger signal matching the two-bit code associated with end point EP is asserted, at which point sequential trigger signal ST is asserted (i.e., passed to output switch650; seeFIG. 6), and control is returned on path840to start point EP.

If fewer than four states are desired, then end point EP is loaded with the same two-bit code as the last state of the dependency. For example, to generate sequential trigger signal ST in response to a single state sequence (e.g., when combinational trigger signal CT2is asserted), then the two-bit codes for SP, IP0, IP1, and EP should be loaded with the digital values 2, 2, 2, and 2, respectively. This setting results in the direct passage of control from start point SP to end point EP along path850when combinational trigger signal CT2is asserted. Similarly, to generate sequential trigger signal ST in response to the sequence of CT2followed by CT1, the two-bit codes for SP, IP0, IP1, and EP should be loaded with the digital values 2, 1, 1, and 1, respectively. This setting results in the passage of control from start point SP to first intermediate point IP0when combinational trigger signal CT2is asserted, and then the passage of control from intermediate point IP0directly to end point EP along path860when combinational trigger signal CT1is subsequently asserted. Finally, to generate sequential trigger signal ST in response to the sequence of CT2followed by CT1and CT1followed CT3(i.e., CT2->CT1->CT3), the two-bit codes for SP, IP0, IP1, and EP should be loaded with the digital values 2, 1, 3, and 3, respectively.

Referring again toFIG. 6, output switch650is user-programmed to generate a predetermined set of trigger signals in response to corresponding combinational trigger signals CT0through CT3or in response to sequential trigger signal ST. For example, output switch650may be programmed to generate trigger TE0in response to combinational trigger signal CT0, with trigger TE0including an action ID associated with a “CPU halt” breakpoint trigger operation. Alternatively, output switch650may be programmed to generate trigger TE0in response to sequential trigger signal ST, with trigger TE0including an action ID associated with an “enable data trace” watchpoint trigger operation. The thus-generated triggers are then passed to action generator420(seeFIG. 4) in the manner described above.

As set forth above, by providing a programmable BWP trigger circuit, a developer is able to selectively generate BWP trigger signals under a wide range of trigger events, both combinational and sequential, thereby facilitating greatly enhanced debugging operations during the development of a software program.

Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention. For example, any number of banks can be utilized to generate any number of trigger signals. Further, each bank can include any number of registers for generating pre-trigger signals based upon instruction addresses/values and data addresses/values. Function generators other than SOP circuits may be utilized. Moreover, the 16-bit SOP circuits described above for generating combinational trigger signals may be replaced, for example, with four-bit SOP circuits addressed by two pre-trigger signals, or 256-bit SOP circuits addressed by eight pre-trigger signals (it is noted, however, that the use of 256-bit SOP circuits may be impractical in some arrangements). Similarly, state machines other than those described herein may be utilized to identify sequences of trigger events. In yet other alternative embodiments, programmable trigger circuit410may omit programmable state machine640, and only provide the combinational trigger signals from function generators630-1through630-4. Alternatively, programmable trigger circuit410may omit function generators630-1through630-4, and only provide a state machine driven by pre-trigger signals (which is functionally implemented in the disclosed embodiment by programming function generators630-1through630-4to “pass through” a corresponding pre-trigger signal).