High voltage input circuit for a differential amplifier

A differential input circuit (FIG. 3A) is disclosed. The circuit includes a first input terminal (drain of 310) and a second input terminal (drain of 312). A first input transistor (310) has a first control terminal and has a current path coupled to the first input terminal. A second input transistor (312) has a second control terminal and has a current path coupled to the second input terminal. A third transistor (306) has a third control terminal and has a current path between a first differential input terminal (Vin+) and the first control terminal. A fourth transistor (308) has a fourth control terminal and has a current path between a second differential input terminal (Vin−) and the second control terminal.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate to a high voltage input stage for a complementary metal oxide semiconductor (CMOS) differential amplifier.

High voltage differential amplifiers using relatively low voltage transistors require protection for differential input terminals to avoid gate oxide stress. Circuits of the prior art have typically used diode clamps to limit peak-to-peak voltage across differential input terminals. These diode clamps, however, conduct high currents under forward bias. Moreover, they increase input capacitance, may slow operation due to forward bias recovery time, and increase noise.

Referring toFIG. 1, there is a high voltage differential amplifier circuit of the prior art. Here, and in the following discussion the differential amplifier may be an operational amplifier or other balanced amplifier for amplifying difference signals. The circuit includes back-to-back diodes102and104connected between differential input terminals Vin+ and Vin−. The input terminals are connected directly to the gate terminals of low voltage p-channel input transistors106and108. A common source terminal of p-channel transistors106and108is connected to current source100. The drain terminals of p-channel transistors106and108are connected to negative and positive input terminals of differential amplifier110, respectively. In operation, peak-to-peak voltage between input terminals Vin+ and Vin− is limited to a diode drop of approximately 0.7 V plus a voltage developed across the parasitic resistance of the forward biased diode. The circuit of FIG.1, therefore, protects low voltage p-channel transistors106and108at the expense of high forward bias diode current, high capacitance, and additional noise.

Referring next toFIG. 2, there is another high voltage differential amplifier circuit of the prior art. This circuit includes p-channel switch transistors202and204and p-channel input transistors206and208, having control gates coupled to respective input terminals Vin+ and Vin−. Current sources200are coupled to the respective common source terminals of the p-channel transistors. Drain terminals of p-channel transistors206and208are coupled to negative and positive input terminals of differential amplifier210, respectively. In operation, when input terminal Vin− is held to 0 V, for example, p-channel transistors and204and208remain on. A high positive voltage applied to input terminal

Vin+ turns off p-channel transistors202and206. In this condition, the common source and bulk terminals of p-channel transistors202and206are driven high by current source200. P-channel transistor204remains on and drives the common drain terminal of p-channel transistors202and204high. The drain terminal of p-channel transistor206is essentially floating. Thus, there is insufficient voltage across the gate oxide of p-channel transistors202and206to damage gate oxide. However, there are several disadvantages to this circuit. First, transconductance of the input terminals is reduced by resistance of p-channel switch transistors202and204. This increases noise and offset voltage and decreases bandwidth of the differential amplifier.

While the preceding approaches protect low voltage input transistors, the present inventors recognize that still further improvements are possible. Accordingly, the preferred embodiments described below are directed toward improving upon the prior art.

BRIEF SUMMARY OF THE INVENTION

In a preferred embodiment of the present invention, a differential input circuit is disclosed. The circuit includes first and second input terminals. A first input transistor has a first control terminal and has a current path coupled to the first input terminal. A second input transistor has a second control terminal and has a current path coupled to the second input terminal. A third transistor has a third control terminal and has a current path between a first differential input terminal and the first control terminal. A fourth transistor has a fourth control terminal and has a current path between a second differential input terminal and the second control terminal.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiments of the present invention provide significant advantages over differential input circuits of the prior art as will become evident from the following detailed description.

Referring toFIG. 3A, there is a circuit diagram of a first embodiment of a high voltage differential amplifier circuit of the present invention. Here and in the following discussion, the same reference numerals are used in the drawing figures to indicate substantially the same circuit elements. The circuit includes differential amplifier314having output terminal Vout. The differential amplifier may be an operational amplifier configured as a linear amplifier, integrator, or other special purpose amplifier as is known in the art. The differential amplifier314has first (−) and second (+) input terminals. A first p-channel input transistor310has a current path coupled to the first (−) input terminal. A second p-channel input transistor312has a current path coupled to the second (+) input terminal. The first and second input transistors are preferably balanced and have substantially the same threshold voltage and are oriented to compensate for any slight misalignment during fabrication. N-channel transistor306has a current path coupled between a first differential input terminal (Vin+) and a control terminal of the first input transistor310. N-channel transistor308has a current path coupled between a second differential input terminal (Vin−) and a control terminal of the second input transistor312. N-channel transistors306and308are preferably balanced, high voltage transistors. Here, high voltage means that the transistors can withstand a higher gate-to-drain voltage than input transistors310and312. This is preferably accomplished by fabricating transistors306and308as drain extended n-channel transistors as is known in the art. Alternatively, n-channel transistors306and308may be fabricated with a thicker gate dielectric than transistors310and312. A current source300is coupled between supply voltage terminal

VDD and a common source terminal of input transistors310and312. The current source is preferably a p-channel current mirror circuit as is know in the art. A reference voltage circuit301is formed between the common source terminal of input transistors310and312and a common gate terminal of transistors306and308. Diode302is coupled between the control terminal of input transistor310and the control terminal of transistor306. Diode304is coupled between the control terminal of input transistor312and the control terminal of transistor308.

Operation of the circuit ofFIG. 3Awill now be explained with reference toFIGS. 3B and 3C.FIG. 3Bshows the circuit ofFIG. 3Awith representative voltages when differential input terminals Vin+ and Vin− are each held at 0 V. Here and in the following discussion, the internal voltages are for the purpose of explanation only and are shifted upward by the lesser of Vin+ and Vin−. For example, if Vin+ and Vin− are both 1.0 V, the control terminals of n-channel transistors306and308will be 4.0 V, and the common source terminal of input transistors310and312will be 2.0 V. Current source300produces 1.0 V at the common source terminal of input transistors310and312. Reference voltage circuit301adds 2.0 V to this to produce 3.0 V at the common gate terminal of transistors306and308. Transistors306and308preferably have a threshold voltage of less than 1.0 V and are both on, thereby applying the voltage at differential input terminals Vin+ and Vin− to the control terminals of input transistors310and312, respectively.FIG. 3Cshows the circuit ofFIG. 3Awith representative voltages when differential input terminals Vin+ and Vin− are held at 15 V and 0 V, respectively. This relatively high differential voltage would normally damage low voltage input transistors310and312if applied directly to their control gates. Transistor306charges the control terminal of input transistor310to approximately 3.7 V by subthreshold leakage. In this condition transistors306and310are both off. Diode302conducts the subthreshold leakage current through transistor306by to clamp the gate of transistor310at approximately 3.7 V. Thus, the high differential voltage advantageously turns off switching transistor306when it exceeds a predetermined value, thereby protecting input transistor310.

Turning now toFIG. 4A, there is a circuit diagram of a second embodiment of a high voltage differential amplifier circuit of the present invention. The circuit includes differential amplifier314having output terminal Vout. The differential amplifier314has first (−) and second (+) input terminals. A first p-channel input transistor316has a current path coupled to the first (−) input terminal. A second p-channel input transistor318has a current path coupled to the second (+) input terminal. The first and second input transistors are preferably balanced and have substantially the same threshold voltage and are oriented to compensate for any slight misalignment during fabrication. N-channel transistor306has a current path coupled between a first differential input terminal (Vin+) and a control terminal of the first input transistor316. N-channel transistor308has a current path coupled between a second differential input terminal (Vin−) and a control terminal of the second input transistor318. N-channel transistors306and308are preferably balanced, high voltage transistors as previously described. A current source300is coupled between supply voltage terminal VDD and a common source terminal of input transistors316and318. The current source is preferably a p-channel current mirror circuit as is know in the art. Input transistors316and318preferably have a higher magnitude threshold voltage than transistors306and308so that reverence voltage circuit301(FIG. 3A) is unnecessary. The common source terminal of input transistors316and318is coupled to the common gate terminal of transistors306and308. Diode302is coupled between the control terminal of input transistor316and the common gate terminal. Diode304is coupled between the control terminal of input transistor318and the common gate terminal.

Operation of the circuit ofFIG. 4Awill now be explained with reference toFIGS. 4B and 4C.FIG. 4Bshows the circuit ofFIG. 4Awith representative voltages when differential input terminals Vin+ and Vin− are each held at 0 V. Current source300produces 1.0 V at the common source terminal of input transistors316and318. Transistors306and308preferably have a threshold voltage of less than 1.0 V and are both on, thereby applying the voltage at differential input terminals Vin+ and Vin− to the control terminals of input transistors316and318, respectively.FIG. 4Cshows the circuit ofFIG. 4Awith representative voltages when differential input terminals Vin+ and Vin− are held at 15 V and 0 V, respectively. This relatively high differential voltage would normally damage low voltage input transistors316and318if applied directly to their control gates. Transistor306charges the control terminal of input transistor310to approximately 1.7 V by subthreshold leakage. In this condition transistors306and316are both off. Diode302conducts the subthreshold leakage current through transistor306to clamp the gate of transistor316at approximately 1.7 V. Thus, the high differential voltage advantageously turns off switching transistor306when it exceeds a predetermined value, thereby protecting input transistor316. This embodiment of the present invention offers substantially the same advantages over high voltage differential input circuits of the prior art as the embodiment ofFIG. 3A. In addition, this embodiment avoids the need for reference voltage circuit301, thereby reducing circuit complexity.

Turning now toFIG. 5A, there is a circuit diagram of a third embodiment of a high voltage differential amplifier circuit of the present invention. The circuit includes differential amplifier314having output terminal Vout. The differential amplifier314has first (−) and second (+) input terminals. A first p-channel input transistor310has a current path coupled to the first (−) input terminal. A second p-channel input transistor312has a current path coupled to the second (+) input terminal. The first and second input transistors are preferably balanced and have substantially the same threshold voltage and are oriented to compensate for any slight misalignment during fabrication. N-channel transistor306has a current path coupled between a first differential input terminal (Vin+) and a control terminal of the first input transistor310. N-channel transistor308has a current path coupled between a second differential input terminal (Vin−) and a control terminal of the second input transistor312. N-channel transistors306and308are preferably balanced, high voltage transistors as previously described. A current source300is coupled between supply voltage terminal VDD and a common source terminal of input transistors310and312. The current source is preferably a p-channel current mirror circuit as is know in the art. Current source321is connected to supply voltage terminal VDD and provides current through reference voltage circuit315to the current path of p-channel transistor320to supply voltage terminal VSS. The control gate of transistor320is connected to the common source terminal of p-channel input transistors310and312. Diode302is coupled between the control terminal of input transistor310and reference voltage315. Diode304is coupled between the control terminal of input transistor312and reference voltage315.

Referring toFIG. 5B, there is a voltage and current diagram showing operation of the circuit ofFIG. 5Aas input terminal Vin− is held at 0 V and input terminal Vin+ increases from 0 V to 8 V. The voltage at the gate terminal of transistor306is substantially constant at approximately 3.3 V as determined by current source321and reference voltage circuit315. Voltage at the gate terminal of input transistor310follows the voltage at differential input voltage terminal Vin+ from 0 V to approximately 3.2 V. At this point, transistors306and310are both off. Subthreshold leakage current through transistor306increases with current through diode302to approximately 180 pA with little change as Vin+ increases to 8.0 V. This embodiment of the present invention offers the advantages of the previous embodiments. Additionally, current source321and reference voltage circuit315increase the gate voltage of n-channel transistors306and308to reduce their on resistance.

Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling within the inventive scope as defined by the following claims. For example, in the circuits ofFIGS. 3A and 4Aare shown with p-channel input transistors. Alternative embodiments of the present invention may include n-channel or bipolar input transistors Likewise, transistors306and308may be p-channel transistors or bipolar transistors in alternative designs. Other combinations will be readily apparent to one of ordinary skill in the art having access to the instant specification.