PACKAGE HAVING THICK GLASS CORE WITH HIGH ASPECT RATIO VIAS

Embodiments disclosed herein include package substrates for electronic packaging applications. In an embodiment, a package substrate comprises a first glass layer, where the first glass layer comprises a first via through the first glass layer, and the first via has an hourglass shaped cross-section. The package substrate may further comprise a second glass layer over the first glass layer, where the second glass layer comprises a second via through the second glass layer, and where the second via has the hourglass shaped cross-section. In an embodiment, the first via is electrically coupled to the second via.

TECHNICAL FIELD

Embodiments of the present disclosure relate to electronic packages, and more particularly to package substrates with core layers that include vias and vertical planes for improved performance.

BACKGROUND

Microelectronic packages utilize through package vias to enable power and signal connectivity between the die and socket or printed circuit board. For the most advanced packages, the package substrate stack-up comprises a core that is made out of glass-fiber reinforced epoxy or copper clad laminate (CCL). In the client and server space, using a thick core is necessary to reduce the package warpage. Creating small diameter and fine pitch vias across such thick cores is challenging. This leads to excessive parasitics, substantial impedance discontinuities and low via density in the core. This further results in low integration density, low frequency bandwidth, and low bandwidth density for signals transitioning between the first level and second level interconnects.

EMBODIMENTS OF THE PRESENT DISCLOSURE

As noted above, existing through core vias are formed with mechanical drilling processes. This results in relatively large via diameters and pitches. This results in low integration density, low frequency bandwidth, and low bandwidth density for signals transitioning between the first level and second level interconnects. Accordingly, embodiments disclosed herein include package core substrates that are manufactured out of a material that can be patterned with a laser exposure and etching process. The laser exposure creates a morphological change in the core substrate. The morphological change can then be used to selectively etch away portions of the core substrate to form through holes. Vias may then be disposed into the holes to provide connections between opposing surfaces of the core substrate. In an embodiment, the core substrate may be glass, ceramic, silicon, or any other non-conductive semiconductor material.

The laser-assisted etching process allows for the formation of crack free, high-density via holes into the core substrate. Whereas existing through core vias have diameters of 100 μm or larger and pitches of 250 μm or larger, the laser-assisted etching process may enable via diameters that are approximately 50 μm or smaller and pitches that are approximately 40 μm or larger. The via diameters may be approximately 10 μm or smaller without a mask, or approximately 5 μm or smaller or 2 μm or smaller when a hardmask is used. The thickness of the core may also be between approximately 100 μm and 1,000 μm. Though it is to be appreciated that embodiments may also apply to larger and/or smaller via diameters, via pitches, and core substrate thicknesses.

In addition to the formation of through core vias, the laser-assisted etching process may also be harnessed to provide alternative functionalities within the core substrate. For example, materials other than conductive materials may be disposed in the via holes, or the via holes may be left voided in the final structure (e.g., to function as a fluidic pathway). Additionally, the laser exposure may be tuned to provide different structural features within the core. For example, blind vias may be formed partially through the thickness of the core substrate.

In yet another embodiment, high aspect ratio vias may be made through the core substrate using a multi-layered approach. For example, a plurality of core substrate layers may be adhered to each other in order to provide a thicker overall core. The vias may be made through each core substrate layer before adhering the layers together. As such, each portion of the overall via requires a smaller aspect ratio compared to forming a single via through a single thicker core substrate.

Referring now toFIGS.1A-1D, a series of cross-sectional illustrations depicting a process for forming a via in a core substrate105using a laser-assisted etching process is shown, in accordance with an embodiment. As shown inFIG.1A, the core substrate105is exposed by a laser170. The laser170may be irradiated over both a first surface106and a second surface107. However, as will be described in greater detail below, the laser170may only irradiate a single surface in of the core substrate105in other embodiments.

In an embodiment, the core substrate105may comprise a material that is capable of forming a morphological change as a result of the exposure by the laser170. For example, in the case of a glass core substrate105, the morphological change may result in the conversion of an amorphous crystal structure to a crystalline crystal structure. While glass is used as an example here, it is to be appreciated that the core substrate105may also comprise ceramic materials, silicon, or other non-conductive semiconductor materials. In an embodiment, the core substrate105may have a thickness between the first surface106and the second surface107that is between 200 μm and 1,000 μm. However, it is to be appreciated that larger or smaller thicknesses may also be used for the core substrate105in other embodiments.

Referring now toFIG.1B, a cross-sectional illustration of the core substrate105after the morphological change has occurred is shown, in accordance with an embodiment. As shown, an exposed region111is provided through a thickness of the core substrate105. In an embodiment, the exposed region111may have sidewalls112that are sloped. That is, the sidewalls112may not be substantially vertical (with respect to the first surface106and the second surface107). In a particular embodiment, the exposed region111may have an hourglass shaped cross-section that results from exposure from laser exposure on both the first surface106and the second surface107. As used herein, an hourglass shaped cross section may refer to a shape that starts with a first width on a first end, decreases in width while moving away from the first end until reaching a minimum width between the first end and a second end, and increasing in width while moving from the minimum width in the middle towards the second end. That is, the shape may have a middle region that is narrower in width than the widths of the opposing ends. In an embodiment, the sidewalls112may have a slope that is approximately 10° or less away from vertical. While shown with sloped sidewalls112, it is also to be appreciated that embodiments may include substantially vertical sidewalls depending on the laser parameters and the material of the core substrate105.

Referring now toFIG.1C, a cross-sectional illustration of the core substrate105after the exposed region111is removed to form a hole115through the core substrate105is shown, in accordance with an embodiment. In an embodiment, the hole115may be formed with an etching process that is selective to the exposed region111over the remainder of the core substrate105. The etch selectivity of the exposed region111to the remainder of the core substrate105may be 10:1 or greater, or 50:1 or greater. That is, while selective to the exposed region111, some portion of the core substrate105may also be etched, resulting in the thickness of the core substrate105being slightly reduced. In an embodiment, the etchant may be a wet etching chemistry.

Referring now toFIG.1D, a cross-sectional illustration of the core substrate105after a via117is formed in the hole115is shown, in accordance with an embodiment. In an embodiment, the via117may be deposited with a plating process or any other suitable deposition process. The via117may be a conductive material, such as copper. A conductive via117may be used to provide electrical connections through the core substrate105. However, materials that are not conductive may be deposited into the holes in order to provide structural features or to provide other functionalities. In yet another embodiment, the hole115may remain unfilled in order to provide features such as liquid cooling channels.

In an embodiment, the via117may have a maximum diameter that is approximately 100 μm or less, approximately 50 μm or less, or approximately 10 μm or less. The pitch between individual vias117in the core substrate105may be between approximately 10 μm and approximately 100 μm in some embodiments. The small diameters and pitch (compared to traditional plated through hole (PTH) vias that typically have diameters that are 100 μm or larger and pitches that are 100 μm or larger) allow for improved performance of the package substrate due, in part, to the increase in via density. Additionally, while completely filled vias117are described herein, it is to be appreciated that in some embodiments, the holes115may not be completely filled. In such embodiments, the vias117may be similar in structure (but smaller) than a PTH. Such vias117may have a non-conductive core material in some embodiments.

InFIGS.1A-1Donly a single cross-section of the core substrate105is shown for simplicity. However, it is to be appreciated that the shape of the vias117may take substantially any form. This is because the laser providing the morphological change in the core substrate105may be moved in a controllable manner. Examples of various plan views of a vias217in a core substrate205are shown inFIGS.2A-2F.

Referring now toFIG.2A, a plan view illustration of a core substrate205with a plurality of circular vias217is shown, in accordance with an embodiment. The individual circular vias217may be arranged in any pattern to provide desired routing or the like through the core substrate205.

Referring now toFIG.2B, a plan view illustration of a core substrate205with a plurality of rectangular vias217is shown, in accordance with an embodiment. As shown, the rectangular vias217may have widths and lengths that are substantially equal to each other. For example, the rectangular vias217may be substantially square in shape. In other embodiments, the rectangular vias217may have a width that is different than the length.

Referring now toFIG.2C, a plan view illustration of a core substrate205with a via217that is extended along one direction is shown, in accordance with an embodiment. Such a via217may be referred to herein as a “via plane” or simply a “plane”. The via plane217may have a thickness through the core substrate205that is substantially uniform, while also being extended in a direction, as opposed to having a width and length that are substantially uniform.

Referring now toFIG.2D, a plan view illustration of a core substrate205with a via217that is extended along one direction is shown, in accordance with an additional embodiment. Similar to the embodiment shown inFIG.2C, the via217forms a plane. However, the ends of the via217may be rounded surfaces218. The rounded surfaces may be the result of the shape of the laser irradiation. That is, the focus of the laser may be substantially circular in some embodiments.

Referring now toFIG.2E, a plan view illustration of a core substrate205with a pair of vias217A and217B is shown, in accordance with an embodiment. As shown, the vias217Aand217Bmay be extended to form a pair of planes through the core substrate205. In an embodiment, the vias217Aand217Bmay be oriented so that they intersect each other. In an embodiment, the via217Amay be substantially orthogonal to the via217B.

Referring now toFIG.2F, a plan view illustration of a core substrate205with a pair of vias217Aand217Bis shown, in accordance with an additional embodiment. In an embodiment,FIG.2Fmay be substantially similar to the core substrate205inFIG.2E, with the exception of the via217Aand the via217Bintersecting at a non-orthogonal angle. Particularly, the via217Amay be oriented to the via217at any angle between parallel and orthogonal.

The laser-assisted etching process for patterning the core substrate may also be used to fabricate features that are not through core vias. For example, a method for forming a pair of blind vias is shown inFIGS.3A-3C. As used herein, a blind via may refer to a hole or trench that opens at a first surface of the core substrate, but does not pass entirely through a thickness of the core substrate. In the embodiment illustrated inFIGS.3A-3C, the blind vias are substantially aligned with each other. However, it is to be appreciated that embodiments may also comprise offset blind vias.

Referring now toFIG.3A, a cross-sectional illustration of a core substrate305is shown, in accordance with an embodiment. In an embodiment, the core substrate305may comprise a material that undergoes a morphological change when exposed to a laser. For example, the core substrate305may comprise glass or the like. As shown inFIG.3A, a laser370is used to expose a first surface306and a second surface307of the core substrate305. The laser exposure results in morphological changes occurring in the exposed regions311Aand311B. Unlike the embodiments described above, the exposed regions311Aand311Bdo not merge together. That is, an unmodified portion of the core substrate305remains between the exposed regions311Aand311B.

Referring now toFIG.3B, a cross-sectional illustration of the core substrate305after an etching process is shown, in accordance with an embodiment. As shown, the etching process results in the removal of the exposed regions311Aand311Bto form holes315Aand315B. The etching process may utilize an etching chemistry that selectively removes the exposed regions311Aand311Bover the unmodified regions of the core substrate305. The etching process may be a wet etching process in some embodiments.

Referring now toFIG.3C, a cross-sectional illustration of the core substrate305after vias317Aand317Bare disposed in the holes315Aand315Bis shown, in accordance with an embodiment. The vias317Aand317Bmay comprise any material composition that can be deposited into the holes315Aand315B. In a particular embodiment, the vias317Aand317Bcomprise conductive material, such as copper.

As shown, inFIG.3C, the vias317Aand317Bare blind vias. That is, they do not pass through an entire thickness of the core substrate305. Additionally, the vias317Aand317Bare aligned with each other so that a centerline of the via317Ais substantially coincident with a centerline of the via317B. However, it is to be appreciated that in other embodiments, the vias317Aand317Bmay not be aligned with each other.

Referring now toFIGS.4A-4C, a series of cross-sectional illustrations depicting a process for forming a blind via on a single surface of the core substrate is shown, in accordance with an embodiment. In contrast to the embodiments above where the laser is exposed to both surfaces of the core substrate, the embodiment shown inFIGS.4A-4Cincludes exposing only a single surface of the core substrate.

Referring now toFIG.4A, a cross-sectional illustration of a core substrate405is shown, in accordance with an embodiment. The core substrate405may comprise a material that is morphologically changed by exposure from a laser470, such as glass. As shown, the laser470exposes the first surface406of the core substrate405to form an exposed region411. In the case of glass, the exposed region may include a morphological change that includes a change from an amorphous crystal structure to a crystalline crystal structure. In some embodiments, the second surface407of the core substrate405may not be exposed to the laser470.

Referring now toFIG.4B, a cross-sectional illustration of the core substrate405after the exposed region411is removed with an etching process is shown, in accordance with an embodiment. In an embodiment, the etching process includes a wet etching process that selectively removes the exposed region411over the unexposed portions of the core substrate405. In an embodiment a blind hole415is provided into, but not through the core substrate405.

Referring now toFIG.4C, a cross-sectional illustration of the core substrate405after a via417is disposed in the hole415is shown, in accordance with an embodiment. In an embodiment, the via417may be a conductive material, such as copper or the like. In other embodiments, the hole415may be filled with a nonconductive via417to provide different structural features in the core substrate405.

Additional embodiments may also include the forming a through core via by exposing only a single side of the core substrate. A process for forming such a through core via is shown inFIGS.5A-5C. As shown inFIG.5A, a laser570is used to expose a portion511of the core substrate505. The laser parameters may be adjusted in order to make a morphological change through the entire thickness of the core substrate505.

Referring now toFIG.5B, a cross-sectional illustration of the core substrate505after the exposed region511is etched away to form a through hole515is shown, in accordance with an embodiment. As shown, the through hole515may have tapered sidewalls to form an hourglass shape. The hourglass shape may be the result of the wet etching process. Particularly, since the wet etching chemistry contacts both surfaces of the core substrate505, the width of the via hole515decreases toward the center of the core substrate505. As shown, the etching process may not entirely clear the exposed region511, and remnants of the exposed region511may be provided along the sidewalls of the hole515.

Referring now toFIG.5C, a cross-sectional illustration of the core substrate505after a via517is disposed in the hole515is shown, in accordance with an embodiment. In an embodiment, the via517may be a conductive material, such as copper. Alternative embodiments may include a via517that comprises a nonconductive material in order to provide alternative structures within the core substrate505.

While several examples of laser-assisted patterning are provided above, it is to be appreciated that embodiments are not limited to structures fabricated with such processes. For example, vias, blind vias, trenches, and the like may also be formed with a lithographic process. For example, a photo-definable glass may be used as the core substrate. In such embodiments, the photo-definable glass may be exposed to actinic radiation that provides a chemical change in the glass that leaves the exposed regions susceptible to an etchant.

Referring now toFIGS.6A and6B, perspective view illustrations of a core substrate605are shown, in accordance with various embodiments. InFIG.6A, a plurality of vias617and a plurality of via planes619are embedded in the core substrate605. Rows of the vias617may be alternated with via planes619in some embodiments. Both the vias617and the via planes619may be fabricated in the core substrate605using laser-assisted etching processes, such as those described in greater detail above. Additionally, it is to be appreciated that the via planes619and the vias617may have different thicknesses through the core substrate605. For example, the vias617may pass entirely through a thickness of the core substrate605, and the via planes619may be blind features. Additionally, while shown as having vertical sidewalls, it is to be appreciated that the vias617and via planes619may have sloped sidewalls. For example, the vias617and via planes619may have hourglass shaped cross-sections.

Referring now toFIG.6B, a perspective view illustration of a core substrate605is shown, in accordance with an additional embodiment. The core substrate605may be similar to the core substrate605inFIG.6A, with the exception of the via planes619. Instead of all of the via planes619being parallel to each other, one of the via planes619intersects the other via planes619. Particularly, via plane619E intersects the via planes619A.

Referring now toFIGS.7A-7D, cross-sectional illustrations of electronic packages700are shown in accordance with additional embodiments. As shown, the electronic packages700comprise a package substrate701. The package substrate701comprises a core substrate705with vias717(or via planes) that are formed with a laser-assisted etching process.

Referring now toFIG.7A, a cross-sectional illustration of an electronic package700with a package substrate701that comprises a core substrate705with buildup layers731above and below the core substrate705is shown, in accordance with an embodiment. In an embodiment, the core substrate705may be a material that is capable of being morphologically modified by a laser to provide an etch selectivity to the remainder of the core substrate705. As such, using a laser-assisted etching process, such as those described above, allows for the formation of vias717through the core substrate705. For example, the core substrate705may comprise glass, ceramic, silicon, or other nonconductive semiconductors. The vias717may be electrically coupled to traces733, pads, or vias732in overlying or underlying buildup layers731.

In an embodiment, the electronic package700may further comprise one or more dies740. The dies740may be electrically coupled to the conductive features in the core substrate705. For example, solder balls741or the like may be used to couple the dies740to the package substrate701. Additionally, solder balls734, sockets, or the like may be used to couple the package substrate701to a board (not shown).

Referring now toFIG.7B, a cross-sectional illustration of an electronic package700is shown, in accordance with an additional embodiment. The electronic package700inFIG.7Bmay be substantially similar to the electronic package700inFIG.7A, with the exception of the lower buildup layer being omitted. As such, the core substrate705may be directly coupled to the solder balls734, sockets, or the like.

Referring now toFIG.7C, a cross-sectional illustration of an electronic package700is shown, in accordance with an additional embodiment. In an embodiment, the electronic package700inFIG.7Cmay be substantially similar to the electronic package700inFIG.7A, with the exception of the construction of the core substrate705. Instead of having a single glass layer forming the core substrate, a traditional core layer703is provided with patches of the core substrate705embedded therein. For example, the traditional core layer703may comprise glass-fiber reinforced epoxy or a CCL, and the patches of the core substrate705may comprise glass, ceramic, silicon, or other nonconductive semiconductor materials.

Referring now toFIG.7D, a cross-sectional illustration of an electronic package700is shown, in accordance with an additional embodiment. In an embodiment, the electronic package700inFIG.7Dmay be substantially similar to the electronic package700inFIG.7C, with the exception of the bottom buildup layer731being removed. Instead, the solder balls734may be directly coupled to the traditional core layer703and the core substrate705.

In the embodiments described above, the vias are formed through an entire thickness of the core substrate that comprises a single layer. That is the core substrate has a substantially large thickness. However, extending the thickness of the core substrate results in the need to form high aspect ratio vias. In order to ease the manufacturing complexity, additional embodiments include a plurality of core substrate layers that are adhered together. The vias in each of the core substrate layers have a lower aspect ratio and can be combined to form high aspect ratio features. Examples of such embodiments are shown inFIGS.8A-8E.

Referring now toFIG.8A, a cross-sectional illustration of a plurality of core substrate layers8081-8084is shown, in accordance with an embodiment. Each core substrate layer808may include through layer vias817and trenches819. The trenches819may extend into and out of the plane ofFIG.8Ain order to form via planes, or the like. Each core substrate layer808may have a thickness that is approximately 200 μm or less, approximately 100 μm or less, or approximately 50 μm or less. As such, the aspect ratios of the vias817and the trenches819are reduced compared to instances where a single thick core substrate is used. While four core substrate layers808are shown inFIG.8A, it is to be appreciated that embodiments may include two or more core substrate layers808.

The vias817and trenches819may be fabricated using a laser-assisted etching process, similar to one or more of the processes described in greater detail above. That is, the material for the core substrate layers808may be a material that can be morphologically changed as a result of laser exposure. For example, the core substrate layers808may comprise glass, ceramics, silicon, or other non-conductive semiconductor materials. The laser assisted etching process may result in sidewalls of the vias817and trenches819that are sloped. For example, sloped surfaces of the vias817and the trenches819may have a slope (away from vertical) that is approximately 10° or less. In the illustrated embodiment, the cross-sectional shapes of the vias817and the trenches819are hourglass shaped.

Referring now toFIG.8B, a cross-sectional illustration of a core substrate805is shown, in accordance with an embodiment. In an embodiment, the core substrate805is formed from a plurality of substrate layers8081-8084. The individual core substrate layers808may be bonded together with a hybrid bonding process. For example, the interface between layers808may include glass-to-glass bonding in addition to metal-to-metal bonding. In such an embodiment, the vias817in each layer808may be directly coupled to each other with no intervening material. Similarly, the glass of each layer808may be directly coupled to each other with no intervening material.

Since the vias817and trenches819are formed individually in each layer808, the cross-section of the combined structure is unique. Instead of a single hourglass shaped cross-section, embodiments include a through core via with a cross-section comprising a plurality of repeating hourglass shaped sections. For example, inFIG.8B, each through core via includes four hourglass shaped sections that are directly stacked on each other.

Referring now toFIG.8C, a cross-sectional illustration of a core substrate805is shown, in accordance with an additional embodiment. The core substrate805may be substantially similar to the core substrate805inFIG.8B, with the exception of the bonding between the individual layers808. Instead of a direct hybrid bonding, a bonding layer is provided between each layer808. In an embodiment, the bonding layer comprises a plurality of interconnects851. The interconnects851may be solder balls, copper pillars, or the like. The interconnects851provide electrical coupling between the vias817and trenches819of different layers808. In the illustrated embodiment, an interconnect851is provided between all vias817and trenches819. However, it is to be appreciated that the interface between some vias817and some trenches819may omit an interconnect851. In an embodiment, the interconnects851may be surrounded by an underfill material852. The underfill material852may also provide an adhesive force to mechanically couple the layers808together.

Referring now toFIG.8D, a cross-sectional illustration of a core substrate805is shown, in accordance with an additional embodiment. The core substrate805inFIG.8Dmay be substantially similar to the core substrate805inFIG.8B, with the exception of the addition of lateral routing traces853included in the layers808. The traces853may provide signal routing and/or power delivery. The traces853may also be formed with laser-assisted etching processes. For example, the processing used to form blind features described above may also be used to form traces853that are embedded in the surfaces of the layers808.

Referring now toFIG.8E, a cross-sectional illustration of a core substrate805is shown, in accordance with an additional embodiment. The core substrate805inFIG.8Emay be substantially similar to the core substrate805inFIG.8C, with the exception of the addition of lateral routing traces853included in the layers808. Additionally,FIG.8Eshows that not all vias817and trenches819need to be connected to each other by an interconnect851.

Referring now toFIG.9, a cross-sectional illustration of an electronic package990is shown, in accordance with an embodiment. In an embodiment, the electronic package990comprises a board991, such as a printed circuit board (PCB). The board991is coupled to a package substrate901by interconnects992. The interconnects992may comprise solder balls, sockets, or any other suitable interconnect architecture.

The package substrate901comprises a core substrate905. The core substrate905is a material that can be patterned with a laser-assisted patterning process. For example, vias919, trenches, or the like may be formed by exposing the core substrate905to a laser, etching the exposed region, and depositing a material in the resulting hole, similar to embodiments described in greater detail above. The core substrate905may comprise glass, ceramic, silicon, or other nonconductive semiconductors. In an embodiment, the core substrate905is a monolithic structure, similar to the embodiments described inFIGS.1A-7Dabove. In other embodiments, the core substrate905is comprised of a plurality of stacked layers (e.g., a plurality of glass layers), similar to the embodiments described inFIGS.8A-8Eabove.

In an embodiment, the package substrate901may also comprise one or more buildup layers931. The buildup layers931may be above and/or below the core substrate905. The buildup layers931may be connected to one or more dies940by first level interconnects993. The first level interconnects993may be solder balls, copper bumps, or the like. The dies940may be any sort of die, such as a compute die, a graphics die, a memory die, or the like.

FIG.10illustrates a computing device1000in accordance with one implementation of the invention. The computing device1000houses a board1002. The board1002may include a number of components, including but not limited to a processor1004and at least one communication chip1006. The processor1004is physically and electrically coupled to the board1002. In some implementations the at least one communication chip1006is also physically and electrically coupled to the board1002. In further implementations, the communication chip1006is part of the processor1004.

The processor1004of the computing device1000includes an integrated circuit die packaged within the processor1004. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package that comprises a package substrate with a core that is patterned with a laser-assisted etching process, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip1006also includes an integrated circuit die packaged within the communication chip1006. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be part of an electronic package that comprises a package substrate with a core that is patterned with a laser-assisted etching process, in accordance with embodiments described herein.

Example 1: a package substrate, comprising: a first glass layer, wherein the first glass layer comprises a first via through the first glass layer, and wherein the first via has an hourglass shaped cross-section; and a second glass layer over the first glass layer, wherein the second glass layer comprises a second via through the second glass layer, wherein the second via has the hourglass shaped cross-section, and wherein the first via is electrically coupled to the second via.

Example 2: the package substrate of Example 1, wherein the first via directly contacts the second via.

Example 3: the package substrate of Example 2, wherein the first glass layer directly contacts the second glass layer.

Example 4: the package substrate of Examples 1-3, wherein the first via is electrically coupled to the second via by an interconnect between the first via and the second via.

Example 5: the package substrate of Example 4, wherein an underfill is provided between the first glass layer and the second glass layer.

Example 6: the package substrate of Examples 1-5, wherein the first via and the second via are via planes.

Example 7: the package substrate of Example 1-6, wherein the first glass layer and the second glass layer each have a first thickness that is approximately 100 μm or less.

Example 8: the package substrate of Example 7, wherein the first via and the second via each have a diameter that is approximately 50 μm or less.

Example 9: the package substrate of Examples 1-8, wherein the hourglass shaped cross-section has sidewalls that are angled at 10° or less from a vertical orientation.

Example 10: the package substrate of Examples 1-9, wherein the first glass layer and the second glass layer are photo-definable glass materials.

Example 11: the package substrate of Examples 1-10, further comprising: a trace embedded in the first glass layer.

Example 12: the package substrate of Examples 1-11, further comprising: a plurality of glass layers in addition to the first glass layer and the second glass layer, and a plurality of vias through the plurality of glass layers.

Example 13: the method of forming a package substrate, comprising: forming first vias through a first glass layer, wherein the first vias are formed by exposing the first glass layer to a laser, etching exposed portions of the first glass layer to form holes, and depositing a via material in the holes; forming second vias through a second glass layer, wherein the second vias are formed by exposing the second glass layer to the laser, etching exposed portions of the second glass layer to form holes, and depositing a via material in the holes; and securing the first glass layer to the second glass layer, wherein the first vias are electrically coupled to the second vias.

Example 14: the method of Example 13, wherein the first vias and the second vias comprise an hourglass shaped cross-section.

Example 15: the method of Example 13 or Example 14, wherein the first glass layer directly contacts the second glass layer.

Example 16: the method of Examples 13-15, wherein the first vias are electrically coupled to the second vias by interconnects.

Example 17: an electronic system, comprising: a board; a package substrate coupled to the board, wherein the package substrate comprises: a core substrate with a plurality of glass layers and a plurality of vias through the plurality of glass layers; and a buildup layer over the core substrate; and a die coupled to the package substrate.

Example 18: the electronic system of Example 17, wherein the plurality of vias each have an hourglass shaped cross-section.

Example 19: the electronic system of Example 17 or Example 18, wherein the plurality of glass layers are in direct contact with each other.

Example 20: the electronic system of Examples 17-19, wherein an underfill is provided between each of the plurality of glass layers.