Storage device and operating method thereof

A storage device includes a memory controller suitable for outputting a program command or a read command; and a memory device suitable for performing a program operation in response to the program command, and immediately performing a read operation when the read command is received during the program operation.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean patent application number 10-2015-0063233, filed on May 6, 2015, the entire disclosure of which is herein incorporated by reference in its entirety.

BACKGROUND

Field of Invention

Various exemplary embodiments relate generally to a storage device and an operating method thereof, and more particularly, to a read operation and a program operation of a storage device.

Description of Related Art

A storage device includes a memory controller and a memory device. The storage device is controlled by a host. A memory system includes the host and the storage device.

The host communicates with the storage device through an interface protocol, such as peripheral component interconnect Express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), serial attached SCSI (SAC), universal serial bus (USB), multi-media card (MMC), enhanced Small Disk Interface (ESDI), integrated drive electronics (IDE), and so forth.

A memory controller controls the overall operations of the storage device and exchanges commands, data and addresses between the host and the memory device.

The memory device performs program, read and/or erase operations in response to the commands, the data and the addresses provided from the memory controller.

SUMMARY

Various embodiments are directed to a storage device stopping a program operation and performing a read operation when the storage device receives a read command during the program operation.

According to an embodiment, a storage device includes a memory controller suitable for outputting a program command or a read command; and a memory device suitable for performing a program operation in response to the program command, and performing a read operation immediately when the read command is received during the program operation.

According to an embodiment, a method of operating a storage device may include inputting program data to a first latch unit in response to a program command; temporarily pausing the inputting of the program data, and transferring the program data in the first latch unit to a second latch unit immediately when a read command is received during the inputting of the program data; and performing a read operation using the first latch unit.

According to an embodiment, a method of operating a storage device may include inputting program data to a first latch unit in response to a program command; transferring the program data in the first latch unit to a second latch unit immediately when a read command is received during the inputting of the program data; and performing a read operation using the first latch unit, during the inputting of the program data to the second latch unit.

According to an embodiment, a memory device may include a peripheral circuit suitable for performing program and read operations in response to program and read commands, respectively; and a control logic suitable for controlling the peripheral circuit to be immediately responsive to the read command during the program operation.

DETAILED DESCRIPTION

Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the drawings, thicknesses and lengths of components may be exaggerated for convenience. In the following description, a detailed explanation of related functions and constitutions may be omitted for simplicity and conciseness. Like reference numerals refer to like elements throughout the specification and drawings.

FIG. 1a diagram illustrating a storage device according to an embodiment.

Referring toFIG. 1, a storage device1000may include a memory controller100and a memory device200.

The memory controller100may control overall operations of the storage device1000, and exchange commands, data and addresses between a host and the memory device200. For example, when the memory controller100receives a command for a program operation, the memory controller100may output a program command CMD_P, data DATA and an address ADD to the memory device200. When the memory controller100receives a command for a read operation, the memory controller100may output a read command CMD_R to the memory device200. Even when the memory device200is performing a program operation, the memory controller100may output the read command CMD_R to the memory device200.

When the read command CMD_R is received during the program operation, the memory device200may temporarily stop performing the program operation and perform a read operation, or may perform the program operation and the read operation at the same time.

The memory device200may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), or flash memory. A memory device200that uses flash memory will be used as an example, below.

FIG. 2is a diagram illustrating the memory device shown inFIG. 1.

Referring toFIG. 2, the memory device200may include a memory cell array210in which data is stored, a peripheral circuit220configured to perform a program operation, a read operation or an erase operation on the memory cell array210, and a control logic230configured to control the peripheral circuit220.

The memory cell array210may include a plurality of memory blocks, and each of the memory blocks may include a plurality of memory cells.

The peripheral circuit220may include a voltage generator221, a row decoder222, a page buffer unit223, a column decoder224and an input/output circuit225.

The voltage generator221may generate a program voltage Vpgm or a read voltage. Vread in response to a program signal PGM or a read signal READ. The voltage generator221may also generate various other voltages for various operations.

The row decoder222may transfer voltages output from the voltage generator221to a selected memory block in response to a row address RADD. For example, the row decoder222may transfer the program voltage Vpgm or the read voltage Vread to word lines WL coupled to the selected memory block.

The page buffer unit223may include a plurality of page buffers PB. Each of the page buffers PB may be coupled to each of the bit lines BL that are coupled to the memory blocks. The page buffers PB included in the page buffer unit223may commonly operate in response to page buffer control signals PBSIG.

The column decoder224may transfer data applied through column lines CL to the page buffers PB through page lines PL in response to a column address CADD.

The input/output circuit225may input or output the data DATA in response to an input/output signal IN/OUT. For example, the input/output circuit225may transfer externally input data DATA to the column decoder224through the column lines CL, or externally output the data DATA provided through the column lines CL.

The control logic230may control the peripheral circuit220in response to the program command CMD_P and the address ADD, or the read command CMD_R. The control logic230may control the peripheral circuit220so that the peripheral circuit220may perform a read operation in response to a current read command CMD_R after all program data is input and resume program operation in response to a previous program command CMD_P after completing the read operation when the read command CMD_R is currently provided to the control logic230during input of program data in response to the previous program command CMD_P. Alternatively, the control logic230may control the peripheral circuit220so that the peripheral circuit220may temporarily stop input of the program data, perform a read operation in response to a current read command CMD_R, and then perform a program operation in response to a previous program command CMD_P after completing the read operation when the read command CMD_R is currently provided to the control logic230during the input of program data in response to the previous program command CMD_P. Alternatively, the control logic230may control the peripheral circuit220so that the peripheral circuit220may input the program data in response to a previous program command CMD_P and perform the read operation in response to a current read command CMD_R at the same time, and then perform a program operation in response to the previous program command CMD_P after completing the read operation and the input of the program data when the read command CMD_R is currently provided to the control logic230during the input of the program data in response to the previous program command CMD_P.

FIG. 3is a diagram illustrating a page buffer shown inFIG. 2.

Referring toFIG. 3, since all of the page buffers PB included in the page buffer unit223may be the same, only one of the page buffers PB is described as an example.

The page buffer PB may include two or more latch units LAT1and LAT2. The first latch unit LAT1may be a main latch unit, and the second latch unit LAT2may be a cache latch unit.

The page buffer PB in response to the page buffer signal PBSIG may input the data DATA transferred through the page line PL to one of the first and second latch units LAT1and LAT2, or output data from one of the first and second latch units LAT1and LAT2to the page line PL. In addition, the page buffer PB may transfer the data between the first and second latch units LAT1and LAT2in response to the page buffer signal PBSIG.

A method of operating the above-described memory device when a read command is currently input during a program operation in response to a previous program command is described below.

FIG. 4is a flowchart illustrating an operating method according to a first embodiment.

Referring toFIG. 4, when the control logic230receives the program command CMD_P at step S41, the control logic230may control the peripheral circuit220to input program data to the page buffer unit223at step S42.

When the control logic230receives the read command CMD_R at step S43while the program data is being input in response to the program command CMD_P of step S41, the control logic230may suspend a read operation until all program data is input. For example, it may be determined whether the input of the program data for the program command CMD_P of step S41is completed at step S44.

When the input of the program data is not completed as a result of determination at step S44(NO), the control logic230may continue to control the peripheral circuit220to input program data to the page buffer unit223.

When the input of the program data is completed as the result of determination at step S44(YES), the control logic230at step S45may control the peripheral circuit220to temporarily pause the program for the program command CMD_P of step S41. Subsequently at step S46, the control logic230may control the peripheral circuit220to perform the read operation on the selected memory block in response to the read command CMD_R of step S43. The read operation may include reading the selected memory block to temporarily store the read data in the page buffer unit223, and outputting the data temporarily stored in the page buffer unit223through the page lines PL. When the read operation for the read command CMD_R of step S43is completed, the control logic230at step S47may control the peripheral circuit220to resume the paused program operation for the program command CMD_P of step S41.

FIG. 5is a diagram illustrating an operating time according to a first embodiment.

Referring toFIG. 5, program data may be input in response to the program command CMD_P.FIG. 5exemplarily shows the program data including program data DATA1to DATA8which may vary according to design. Even when the read command CMD_R is input while the program data DATA1to DATA8are being input, the read operation may not be performed until the input of all program data DATA1to DATA8is completed.

When the input of all program data DATA1to DATA8is completed, the program operation for the program command CMD_P may be temporarily paused. The pause may last for a first time section PGM_S. After the first time section PGM_S, voltages for a read operation may be set in response to the read command CMD_R, and the read operation of the selected memory block may be performed for a second time section tR. The read operation may include reading memory cells included in the selected memory block and inputting the read data to the page buffer unit223.

When all data read from the selected memory block is input to the page buffer unit223, the data of the page buffer unit223may be output through the page lines PL. Subsequently, the paused program operation for the program command CMD_P may be resumed. The program operation may be performed for a third time section tPROG.

According to the first embodiment, the total operating time may include a program data input time, a program pause time, a read voltage setting time, a read operating time, a read data output time and a program operating time.

In accordance with the first embodiment of the present invention, even when a read command is received while program data for a program operation is being input to the page buffer unit223, a read operation may not be performed until all program data is input to the page buffer unit223.

FIG. 6is a diagram illustrating an operating method according to a second embodiment.

Referring toFIG. 6, when the control logic230receives the program command CMD_P at step S61, the control logic230may control the peripheral circuit220to input program data to the page buffer unit223at step S62.

After all program data is completely input with absence of the read command CMD_R (“NO” at step S63), a program operation may be performed at step S67in response to the program command CMD_P of step S61.

When the control logic230receives the read command CMD_R while the program data is being input to the page buffer unit223in response to the program command CMD_P of step S41(“YES” at step S63), the input of the program data may be temporarily paused at step S64to immediately perform a read operation at step S65in response to the read command CMD_R of step S63The read operation may be performed to read memory cells included in a selected page of a first memory block. The read operation may be completed after all read data input to the page buffer unit223is output.

Upon the completion of the read operation, the paused input of program data may be resumed at step S66, and the program data may be input to the page buffer unit223. When all program data is input to the page buffer unit223, the program operation of a second memory block may be performed at step S67.

The first memory block of the read operation and the second memory block of the program operation may be the same or different. Hereinafter, a description is made in reference to an example in which the first and second memory blocks are different.

FIG. 7is a diagram illustrating an operating time according to a second embodiment.

Referring toFIG. 7, program data may input in response to the program command CMD_P.FIG. 7exemplarily shows the program data including program data DATA1to DATA8, which may vary according to design.

When the read command CMD_R is input while the program data DATA1to DATA8are being input, the input of the program data may be temporarily paused, voltages for a read operation may be set in response to the read command CMD_R, and the read operation of a selected memory block may be performed for a fourth time section tR. The read operation may include reading the memory cells included in the selected memory block and inputting the read data to the page buffer unit223.

When all data read from the selected memory block is input to the page buffer unit223, the data of the page buffer unit223may be output through the page lines PL to complete the read operation.

When the read operation is completed, the paused input of the program data may be resumed. For example as shown inFIG. 7, when the read command CMD_R is received after a part DATA1to DATA3of the program data DATA1to DATA8are input to the page buffer unit223, all the remaining data DATA4to DATA8may be input to the page buffer unit223after the read operation is completed. When all program data DATA1to DATA8are input, a program operation for the program command CMD_P may be performed with the input program data for a fifth time section tPROG.

According to the second embodiment, the total operating time may include a program data input time, a read voltage setting time, a read operating time, a read data output time and a program operating time.

In accordance with the second embodiment of the present invention, when a read command is received while program data for a program operation is being input to the page buffer unit223, the program data input process may be paused, and a read operation may be performed. Therefore, the read operation may be performed before the program operation.

FIGS. 8A to 8Fare diagrams illustrating data transfer according to the second embodiment.

Referring toFIG. 8A, a memory cell array210may include a plurality of memory blocks. For example, the first memory block may be selected for the read operation, and the second memory block may be selected for the program operation. In response to the program command CMD_P, the program data DATA1to DATA3may be sequentially input to the first latch unit LAT1of the page buffer PB (see step S62ofFIG. 6).

Referring toFIG. 8B, the input of the program data may be paused according to the interrupted input read command CMD_R (see step S63ofFIG. 6), and the data DATA1to DATA3of the first latch unit LAT1may be transferred to the second latch unit LAT2.

Referring toFIG. 8C, the read operation CMD_R may be performed to the first memory block selected for the read operation. The read data may be output via the first latch unit LAT1. When all read data is output via the first latch unit LAT1, the read operation may be completed.

Referring toFIG. 8D, when the read operation is completed, the data DATA1to DATA3temporarily transferred to the second latch unit LAT2may be transferred back to the first latch unit LAT1.

Referring toFIG. 8E, the paused input of the program data may be resumed, so that the remaining program data DATA4to DATA8may be input to the first latch unit LAT1.

Referring toFIG. 8F, when all program data is input to the first latch unit, the program operation may be performed to the second memory block with the program data DATA1to DATA8of the first latch unit.

FIG. 9is a flowchart illustrating an operating method according to a third embodiment.

Referring toFIG. 9, when the control logic230receives the program command CMD_P at step S91, the control logic230may control the peripheral circuit220to input program data to the page buffer unit223at step S92.

After all program data is completely input with absence of the read command CMD_R (“NO” at step S93), a program operation may be performed at step S97in response to the program command CMD_P of step S91.

When the control logic230receives the read command CMD_R while the program data is being input to the page buffer unit223in response to the program command CMD_P of step S91(“YES” at step S93), both of a read operation for the read command CMD_R and the input of the program data for the program command CMD_P may be concurrently performed at step S95, which may reduce the total operating time. The read operation performed at step S95may include reading selected memory cells and inputting the read data to the page buffer unit223. After completion of both of the read command CMD_R and the input of the program data for the program command CMD_P, the read data of the page buffer unit223may be output at step S96, and a program operation of the selected memory block may be performed with the program data of the page buffer unit223at step S97.

FIG. 10is a diagram illustrating an operating time according to a third embodiment.

Referring toFIG. 10, program data may be input in response to the program command CMD_P.FIG. 10exemplarily shows the program data including program data DATA1to DATA8, which may vary according to design.

When the read command CMD_R is input while the program data DATA1to DATA8are being input, voltages for a read operation may be set in response to the read command CMD_R, and the read operation of the selected memory block may be performed for a sixth time section tR with continuation of the input of the program data. The read operation performed for the sixth time section tR may include sensing data from selected memory cells. The program data, for example DATA4to DATA8shown inFIG. 10may be input to the page buffer unit223during the read operation, or for the sixth time section tR.

When all the data read from the selected memory block is input to the page buffer unit223, the read data may be output through the page lines PL, thereby completing the read operation.

Upon completion of the read operation, a program operation may be performed for a seventh time section tPROG in response to the program command CMD_P with the program data of the page buffer unit223.

As described above, according to the third embodiment, the total operating time may include a program data input time, a read voltage setting time, a read data output time and a program operating time.

In accordance with the third embodiment of the present invention, when a read command is received while program data for a program operation is being input to the page buffer unit223, both of the program data input process and the read operation may be concurrently performed so that the read operation may be performed before the program operation, and the operating time may be reduced.

FIGS. 11A to 11Fare diagrams illustrating data transfer according to the third embodiment.

Referring toFIG. 11A, the memory cell array210may include a plurality of memory blocks. For example, the first memory block may be selected for the read operation, and the second memory block may be selected for the program operation. In response to the program command CMD_P, the program data DATA1to DATA3may be sequentially input to the first latch unit LAT1of the page buffer PB (see step S92ofFIG. 9).

Referring toFIG. 11B, the input of the program data may be paused according to the interrupted input read command CMD_R (see step S93ofFIG. 9), and the data DATA1to DATA3of the first latch unit LAT1may be transferred to the second latch unit LAT2.

Referring toFIG. 11C, the read operation CMD_R may be performed to the first memory block selected for the read operation. The read data may be input to the first latch unit LAT1. Concurrently, the program data DATA4to DATA8may be input to the second latch unit LAT2. Therefore, all program data DATA1to DATA8may be input to the second latch unit LAT2without pause of the input of the program data even while the read operation is performed in response to the interrupted input read command CMD_R.

Referring toFIG. 11D, when all read data is input to the first latch unit LAT1and the program data DATA4to DATA8are input to the second latch unit LAT2, the read data of the first latch unit LAT1may be output, thereby completing the read operation.

Referring toFIG. 11E, upon the completion of the read operation, all of the program data DATA1to DATA8of the second latch unit LAT2may be transferred to the first latch unit LAT1.

Referring toFIG. 11F, when the all program data is transferred to the first latch unit LAT1, a program operation may be performed to the second memory block with the program data of the first latch unit LAT1.

According to various embodiments of the present invention, when a memory device receives a read command during a program operation, the memory device may immediately perform a read operation, so that the operating time required for the read operation and the program operation may be reduced to improve performance of a storage device including the memory device.