Process of etching an oxide layer

A dry etching process for etching an oxide layer on a substrate in which a plasma is created in a gaseous mixture containing C.sub.4 F.sub.8 and C.sub.2 F.sub.6. The dry etch process is useful for etching an oxide layer stopping on a silicon nitride layer on a semiconductor wafer of an integrated circuit structure as it eliminates resist blistering without sacrificing high selectivity to nitride, via wall angle, and/or etch uniformity.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates to the manufacturing of semiconductor devices and 
more particularly to an improved process for etching openings in oxide 
layers. 
2. Description of the Related Art 
Conventionally, in order to form metal contacts to semiconductor devices 
and active components thereof, such as gate contacts, source/drain 
diffusion region contacts, and/or strap contacts in logic applications, or 
bit line contacts in a DRAM, and so forth, a via or opening is etched 
through a dielectric layer so that an upper metal layer can be 
interconnected with a lower conductive layer. A conventional scheme for 
accomplishing this metallization involves forming a nitride etch stop 
layer on the feature which is to acquire a metal contact, followed by 
depositing a dielectric oxide layer, and then a photoresist is formed on 
the oxide layer which is imagewise-exposed and developed to define the 
desired pattern of openings to be etched through the underlying oxide 
layer. In order to form the contact openings, the oxide layer must be 
etched selectively to the underlying nitride etch stop layer. Then the 
exposed nitride layer is removed (e.g., by hot H.sub.3 PO.sub.4), and then 
a liner (e.g., Ti/TiN) and contact metal (e.g., tungsten) is deposited in 
the openings followed by surface planarizing of the device and removal of 
the resist. 
The step of selectively etching the oxide to nitride is conventionally 
performed by creating a plasma in an etching chamber in a fluorocarbon 
etchant gas that has a high C/F ratio, often in combination with hydrogen 
or carbon monoxide gas, where the fluorocarbon etching gas often is 
introduced as mixed with an inert carrier gas. The selectivity to nitride 
is generally achieved by mechanism of in-situ deposition of a polymer film 
on the patterned masking resist that defines the pattern of vias or 
openings in the oxide layer. The deposited polymer film ultimately causes 
a transition in the procedure from net etching to net deposition once the 
nitride layer becomes exposed. The amount of deposition of this polymer 
film on the resist during etching of the vias or openings is dependent on 
the particular exposed material. Specifically, the deposition is thinnest 
on the oxide layer material being etched, thicker on the exposed nitride, 
and thickest on the photoresist material used to define the contact 
openings. For certain advanced semiconductor applications, such as 
self-aligned contacts, octafluorocyclobutane (C.sub.4 F.sub.8) gas is the 
only etchant gas that can provide adequate selectivity to nitride, which 
is thought attributable to the manner in which the cyclic C.sub.4 F.sub.8 
molecule breaks down and recombines as a polymer in a plasma. 
However, in the high polymerizing chemistries used to achieve selectivity 
to nitride, such as pure C.sub.4 F.sub.8 , a drawback encountered is that 
the polymer deposited on the photoresist can form an impervious barrier to 
gas diffusion. In particular, the plasma by-products of pure C.sub.4 
F.sub.8 polymerize very efficiently, which, while responsible for the 
favorable high selectivity property of this gas, also is responsible for 
the creation of a very dense film of deposited polymer on the resist. This 
poses a problem because vapor is released either from the oxide or as a 
chemical by-product from the resist, or both, during the dry etch process. 
As a consequence, vapor pressure builds beneath the polymer film where it 
is trapped, and this gaseous build-up can only be released by explosive 
popping of the resist, resulting in blistering. Blistering refers to gross 
peeling of the resist from the wafer during a highly selective oxide etch. 
The resist blistering reduces process yield and final test yield in the 
semiconductor product, and contaminates the reactor. Also, while it was 
generally understood in the field that higher C/F ratios or inclusion of 
hydrogen-containing gases in the etchant mixture increase selectivity to 
nitride, those modifications would aggravate the resist blistering 
problem. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a dry etch process for 
etching an oxide layer on a substrate with high etch selectivity to the 
substrate. 
It is another object of the present invention to provide a dry etch process 
for etching an oxide layer stopping on a silicon nitride layer on a 
semiconductor wafer of an integrated circuit structure which eliminates 
resist blistering without sacrificing high selectivity to nitride, via 
wall angle, and/or etch uniformity. 
These and other objects, advantages, and benefits are achieved in the 
present invention by a dry etching process for etching an oxide layer on a 
substrate in which a plasma is created in a gaseous mixture containing 
C.sub.4 F.sub.8 and C.sub.2 F.sub.6. C.sub.4 F.sub.8, i.e., 
octafluorocyclobutane, also is known by its refrigerant name Freon-C318. 
C.sub.2 F.sub.6, i.e., perfluoroethane, also is known by its refrigerant 
name Freon-116. 
The invention solves the resist blistering problem by generating a 
permeable polymer film on the photoresist during dry etching of an oxide 
layer, in which the permeable polymer film allows diffusion and outgassing 
of vapor molecules to relieve pressure build-up in the resist and thereby 
prevent resist blistering. 
In one preferred embodiment of this invention, the dry etch process is used 
in the fabrication of integrated circuits using silicon nitride etch stop 
layers in the etching of vias or openings through a dielectric oxide using 
a patterned photoresist mask. The process is conducted in a reactive-ion 
etch reactor and employs a gaseous etchant mixture comprised of C.sub.4 
F.sub.8, C.sub.2 F.sub.6, and a carrier gas (e.g., Ar, He, Ne, Kr, or Xe). 
In one preferred embodiment, the C.sub.4 F.sub.8 and C.sub.2 F.sub.6 are 
used in a C.sub.4 F.sub.8 /C.sub.2 F.sub.6 mixing ratio, by volume, 
ranging from about 1/2 to about 3/1, respectively. In a preferred 
embodiment, the gaseous etchant mixture is comprised of 10 to 20 vol. % of 
the combined amount of C.sub.4 F.sub.8 and C.sub.2 F.sub.6 and 90 to 80 
vol. % of inert gas. 
The specific process parameters, such as RF power, substrate temperature, 
chamber pressure, and gas flow rate, effect the formation of a permeable 
(i.e., porous) polymer on silicon nitride but not on the oxide, thereby 
resulting in a high etch rate selectivity of the oxide over the nitride of 
about 20:1 without blistering of the resist. Moreover, desired selectivity 
requirements as between the oxide layer and the silicon nitride used as an 
etch stop are met by the present invention without tradeoff in other 
requirements such as the via wall angle. 
Other advantages of the invention include avoidance of contamination to the 
workpiece and reactor from resist blistering. Additionally, the inventive 
process also produces a fluoropolymer film on the photoresist during the 
step of dry etching the oxide layer which has a low dielectric constant, 
for example, a K value of less than 2. Furthermore, the inventive etch 
process reduces the amount of polymer formed on the resist to help avoid 
resist delamination, while still providing the desired selectivity to 
nitride. 
In addition to eliminating blistering, this invention also provides a 
technique for modulating the across wafer uniformity. With pure C.sub.4 
F.sub.8, the oxide etch rate profile for a patterned wafer was observed to 
be center fast. A pure C.sub.2 F.sub.6 chemistry, on the other hand, 
demonstrates an edge fast uniformity rate. A combination of both 
chemistries, as used in this invention, gives a hybrid profile. Therefore, 
the plasma cracking patterns and flow dynamics of the different gases 
C.sub.4 F.sub.8 and C.sub.2 F.sub.6 can be used to control the uniformity 
pattern on the wafer. This pattern cannot usually be controlled strictly 
by gas chemistry alone, but requires some type of hardware modification. 
For instance, the gas delivery can be changed from a single nozzle to a 
shower head configuration. Therefore, with a proper gas flow ratio C.sub.4 
F.sub.8 and C.sub.2 F.sub.6, the uniformity of the process can be 
enhanced. 
For purposes of this invention, the terminology "silicon nitride" or 
"nitride" layer is used generally to refer to a layer of Si.sub.x N.sub.y, 
where x and y are each greater in value than zero and the ratio x:y may or 
may not be stoichiometric, as well as to various silicon oxynitride films 
(Si.sub.x N.sub.y O.sub.z,). For instance, the silicon nitride can be 
Si.sub.3 N.sub.4. 
For purposes of this invention, the terminology "oxide"layer is used 
generally to refer to a layer of silicon dioxide, and the silicon dioxide 
may undoped or doped, for example, with boron, phosphorus, or both, to 
form for example, borophosphosilicate glass (BPSG), and phosphosilicate 
glass (PSG). The silicon dioxide layers may be grown or deposited by 
conventional techniques. 
For purposes of this invention, the terminology "resist," "photoresist," or 
"photosensitive layer" are used interchangeably and generally refer to 
film-forming materials sensitive to radiation, which alters their chemical 
properties sufficiently so that a pattern can be delineated in them. 
Positive or negative photoresist materials can be used in the practice of 
this invention. 
As used herein, the terminology "opening" or "via " can refer to any type 
of opening through any type of oxide layer at any stage of processing. 
These and other objects and features of the invention will become more 
fully apparent from the several drawings and description of the preferred 
embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION 
Referring now to the drawings, and particularly FIG.'s 1-3, there is shown 
a representative portion of a semiconductor structure in enlarged views at 
several stages of fabrication of a logic device involving an oxide etch. 
The drawings are not necessarily to scale, as the thicknesses of the 
various layers are shown for visual clarity and should not be interpreted 
in a limiting sense unless otherwise indicated herein. 
Referring to FIG. 1, a silicon substrate 100, a gate electrode 102, a 
source/drain diffusion region 103, and conductor 104 to be used for a 
strap contact, are shown. A gate insulating film 111 and sidewall spacers 
112 are provided for the gate electrode 102 by conventional techniques. 
Other common elements of these logic devices that are not involved in 
oxide layer etch procedure of this invention are omitted to simplify the 
illustration. Also, the depiction of all these devices in a common figure 
is merely provided as part of an overview of the invention, as the 
principles of this invention can be applied independently to any one of 
these scenarios. 
A silicon nitride layer 105 of approximately 500 to 750 .ANG. thickness is 
deposited over the surface topography. The silicon nitride layer 105 can 
be formed by conventional methods such as plasma-enhanced chemical vapor 
deposition (PECVD). Next, an oxide layer 106 of approximately 9,000 to 
12,000 .ANG. total thickness is formed on silicon nitride layer 105. The 
silicon oxide layer can be formed by conventional methods such as CVD 
TEOS. The silicon oxide layer 106 also can contain impurities as BPSG, 
PSG, or