Substrate with die area having same CTE as IC

A package for mounting an integrated circuit chip includes a body having at least a first region, the size of the integrated circuit chip, and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.

FIELD OF THE INVENTION
 The present invention relates generally to the field of microelectronic
 fabrication and assembly and, more specifically, to methods and devices
 which reduce or eliminate bending moments and reduce stresses in an
 integrated circuit chip/package system which result from mis-matched
 coefficients of thermal expansion (CTE) for the various system components
 and/or from adhesive curing during assembly. More specifically, the
 present invention relates to assembly techniques for stabilizing and
 forming semiconductor chips/package systems, by matching the CTEs of the
 various components, by providing differential CTE control within the
 components, and/or by offsetting CTE-induced bending moments with nulling
 bending moments.
 BACKGROUND OF THE INVENTION
 The electronic microcircuit, or "chip," in which a large number of
 electrical circuit components are diffused, for example, onto the surface
 of a 1 to 4 cm.sup.2 chip of silicon or germanium, has become an integral
 and indispensable part of our industrial technology. The industrial
 significance of this technology is so great that continuous efforts are
 being made to improve chip performance, reliability and service life.
 The delicate structure and very small size of these chips, however, have
 created unusually novel and difficult technical problems. These problems,
 generally caused by physical phenomena that are well known on a
 macroscopic scale, e.g., coefficients of thermal expansion (CTE), heat
 dissipation, adhesive shrinkage, flexural moduli, and the like
 nevertheless create entirely new and often undesirable sets of effects
 when they manifest themselves in the microscopic domain of the electronic
 chip.
 Illustratively, a typical chip is mounted on and is electrically coupled to
 a supporting substrate. The substrate, in turn, is secured to a printed
 circuit board. Thus, the substrate not only serves the intermediate
 function of coupling electrical signals taken from conductors on the
 printed circuit board to the chip for processing, but also takes output
 signals from the chip and applies these output signals to other printed
 circuit board conductors for further processing.
 Because a chip, when energized, generates a considerable amount of heat,
 which can be on the order of 50 to 100 watts emanating from a chip with an
 area of 1 to 4 cm.sup.2, the CTE for the chip and that of its substrate
 can produce a number of very damaging effects. Controlling this heat,
 generated in so concentrated an area, in a manner that avoids chip failure
 through overheating is a problem that has not yet been solved in a fully
 satisfactory way.
 For instance, one source of thermally related chip failure resides in the
 fact that the electrical characteristics of the circuit components that
 are diffused or otherwise impressed on the chip can vary markedly with
 changes in chip dimensions. These chip dimension changes caused, for
 example, by thermal expansion of the chip can make the expanded chip
 produce useless and, perhaps, damaging output signals. These undesired
 thermal expansion effects can also cause the central portion of a chip,
 secured at its margins to a substrate, to curve, bend or bow. This curving
 frequently causes at least some of the electrical connections between the
 chip and its underlying substrate to separate and disconnect from each
 other. Largely for these reasons, chip performance is degraded.
 Unquestionably, this destruction of circuit continuity through a thermal
 expansion induced electrical connection failure is a CTE consequence that
 must be at least minimized if it can not be fully avoided.
 Other destructive effects that are attributable to thermally induced
 curving include chip cracking and breaking. In this circumstance, chips
 crack and break in large measure because tensile stresses are established
 in the outermost surface of the chips as the chips are bent. These
 stresses, should they exceed the fracture strength of the chip, will cause
 the chip to crack or break. Thermal effects are not limited to the chip,
 but also appear in the substrate and in other chip packaging materials.
 A substrate is a structure that is assembled by stacking together two to
 fifteen or more layers of substrate materials, at least two of these
 layers being of different compositions. The materials from which each of
 these layers are formed tend to be quite diverse, some layers, for
 instance, being metal (e.g., copper, nickel or gold), other illustrative
 layers being an epoxy resin and glass compound. The CTE for these
 individual layers, each being considerably different, invite an
 uncontrolled bending or thermally induced substrate surface distortion
 that is applied not only to the chip during circuit operation, but also to
 the substrate through the high temperatures that are required in substrate
 manufacture.
 Preferably, the substrate surfaces that support the chip and establish
 electrical contact between the chip and the printed circuit board should
 be "flat" in all conditions of operation. Indeed, if the substrate itself
 is not sufficiently "flat", it will prove impossible to establish
 electrical contact between the chip and substrate.
 There are, moreover, other ways in which the desired degree of substrate
 flatness can be destroyed, apart from CTE-related effects. One of these
 non-CTE related losses in flatness is found in the inability to control
 completely individual layer thickness in the layer manufacturing process.
 These individual layer thickness variations depart from standard or
 preferred thicknesses not only among different production lots, but also
 in different portions or areas of the same layer. These variations in
 individual layer thickness can contribute to localized variations in the
 coefficient of thermal expansion (CTE) within a substrate, which may
 contribute to warping of the substrate.
 To establish some standard for judging flatness in these microscopic
 circumstances, and thus to distinguish acceptable variations in flatness
 from those that are industrially not acceptable, several criteria have
 been established. First, "flatness" for the purpose of chip mounting and
 packaging has been defined as the ratio of the maximum high to low
 deviation per unit area and has developed into an industry practice in
 which the maximum acceptable deviation from flatness is 2.5 .mu.m.
 Further, there are other industrially accepted standards for warpage, or
 loss in flatness for an entire chip package and the chip package
 components, in which warpage of more than 6 to 8 mils over the entire chip
 package is industrially unacceptable. This is a goal that is difficult to
 achieve, but it is a goal nevertheless, that the chip packaging industry
 must meet, in spite of the fact that thickness deviations in a given
 substrate layer can be as much as .+-.15%.
 In an attempt to solve or at least to cope with these curvature or bending
 problems, the chip packaging industry has moved in two entirely opposite
 directions. Ceramic substrates of about 40 mils or greater in thickness
 have been used. These thick substrates are so massive, relative to the
 supported chip, that chip bending does not occur.
 The other, opposite, industrial approach has been to use substrates that
 are essentially thin films, e.g., about 2 mils or less in thickness. These
 thin substrate films deform and absorb almost all of the compressive
 stresses, surface irregularities and the like, thus leaving the chip in an
 essentially flat, un-deformed condition, similar to the way in which
 "blister" or "shrink-wrap" packaging conforms itself to the shape of the
 packaged item.
 In passing, it also should be noted that there are sources of chip warpage
 other than those described above. One illustrative non-thermally or
 production related source of warpage is a consequence of the adhesive
 underfill that is applied between opposing surfaces of the chip and the
 corresponding substrate area to secure the chip to the substrate and to
 stabilize the electrical connections between the chip and its substrate.
 The electrical connections in this substrate area directly under the chip,
 often referred to as the die area, usually are soldered joints. In this
 respect, the solder on these joints, over time, is subject to a
 deterioration that weakens and destroys the electrical connections within
 the die area. This deterioration in the soldered joints has a number of
 sources, one of these sources being a fatigue that is induced through
 relative movement between the chip and its substrate. Although filling the
 volume within the die area between the soldered joints with an adhesive
 (usually an epoxy resin cement) bonds the chip to the substrate and
 reduces relative movement as a source of the soldered joint deterioration,
 the adhesive does produce some undesirable side effects. For instance, on
 curing or hardening, the adhesive becomes a further locus of undesirable
 structural stress. The cured adhesive shrinks, placing the soldered joints
 in compression and through these compressive forces thereby applies still
 another curving movement to the chip and the substrate.
 Clearly, these techniques for coping, with greater or lesser success, with
 curving or bending moments, whatever their source, in massive substrates
 of about 40 mils or more in thickness or in thin film substrates of about
 2 mils or less nevertheless fail to suggest any solution for corresponding
 problems among intermediate range substrates with thicknesses greater than
 2 mils and thinner than 40 mils.
 Substrates in this intermediate range are too thin to force the chip to
 maintain a suitable degree of flatness. These intermediate range
 substrates are also too thick to absorb all of the bending moments,
 whatever the source, to enable the relatively thicker chip to structurally
 dominate the combination and maintain an all-important chip flatness. It
 has been found, in fact, that substrates in this intermediate range are
 excellent vehicles for transmitting bending stresses to their respective
 chips, thereby aggravating the chip bending stress difficulties summarized
 above. Nevertheless, in spite of these structural limitations, there is a
 significant commercial demand for chip substrates in this intermediate
 thickness range.
 To complete a chip package, the chip usually is mounted in the center of
 the substrate. A ring to stiffen the chip and substrate combination often
 is bonded or secured to the substrate by means of an adhesive that is
 applied to the margin of the substrate, essentially enclosing the chip
 within the ring's center either before or after mounting the chip. The
 ring forms a frame around the chip with the inner perimeter of the ring
 being spaced from the corresponding edges of the chip and the height of
 the ring being somewhat greater than that of the chip. In this way, a lid,
 or cover, joined to that surface of the ring opposite to the ring surface
 that is bonded to the substrate, is spaced above the corresponding die
 area of the chip, leaving a gap between the upper surface of the chip and
 the opposing, die area surface of the lid that later is filled with a
 thermally conducting material.
 The CTE, adhesive shrinkage, flatness irregularities and other sources of
 warping, bending and distortion considered above apply with essentially
 equal force to the ring and to the lid. Accordingly, to produce a
 marketable chip package these undesirable stress and bending effects,
 particularly for chips that have substrates with thicknesses greater than
 2 mils and thinner than 40 mils, and more particularly between 5 mils and
 25 mils, should be avoided, or at least controlled and reduced in order to
 maintain chip and chip component flatness within the acceptable degree of
 flatness that is defined in relevant industrial practice and standards.
 SUMMARY OF THE INVENTION
 The present invention relates to assembly techniques and the resulting
 products which are thermally stable, have high structural integrity, and
 compensate for thermal stresses that occur between the various components
 of the package. This is accomplished, in-part, by designing the package so
 that the coefficient of thermal expansion (CTE) of a stiffening ring which
 is mounted on the package substrate matches the CTE of the substrate and
 optional lid. Further, the particular adhesives used to bond the
 stiffening ring are chosen to match their CTE to that of the substrate,
 ring and lid. Moreover, the substrate is designed so that its CTE, at
 least in-part, matches that of the chip, and also that of the stiffening
 ring.
 I Adhesive Encapsulation
 For example, chip package bending can be significantly reduced by forming
 one or more slots or holes in the lid. This slot, or slots, establish
 fluid communication with the void space surrounding the chip that is
 formed in the die area between the chip, the substrate, the lid and the
 margin between the edges of the chip and the inner walls of the ring. An
 adhesive is injected through the hole into this void space. In this way,
 the chip is potted, or encapsulated, in the adhesive simultaneously with
 being underfilled. Bonding the chip to the entire support structure
 effectively integrates the structure of the chip into the more massive
 substrate, ring and lid combination. Thus, in a large measure, the bonded
 chip is protected from bending under any one or more of the thermal and
 mechanical influences noted above.
 Similarly, either independently of or in conjunction with the slot in the
 lid, one or more slots or holes also can be formed in the substrate, the
 ring, or both, also to communicate with the void space that surrounds the
 chip. An adhesive introduced through a hole in the substrate or the ring
 alleviates the chip bending problem in the same manner as the adhesive
 admitted through the slot in the lid. It has been found preferable,
 however, to flow the adhesive into the void space only from one or two
 slots. Flowing the adhesive into the void space from more than two slots
 can produce bubbles in the adhesive, particularly under the chip, a most
 undesirable result.
 II Selectively Stacked Substrate Layers
 Turning now to the substrate, it has been mentioned that a substrate can be
 formed by stacking from two to fifteen or more layers, at least two of
 these layers each being of different materials. In this respect, the
 dominant layers affecting warping occur at the outer surfaces of the
 substrate. Through a salient feature of the invention, however, it has
 been found that by using in the outer layers those materials over which
 the thickness and flatness can be most carefully controlled, e.g., a layer
 of copper, and adding, successively inward toward the center those layers
 that exhibit progressively greater production tolerance, warping effects
 can be markedly reduced, e.g., the warpage in one instance has been
 reduced, through the practice of this feature of the invention from about
 400 .mu.m to under 150 .mu.m.
 By stacking the substrate layers in this manner, the overall warping of the
 substrate is avoided to provide a substrate from which the undesirable
 bending phenomenon has been generally eliminated, at least within the
 range of temperatures that are ordinarily encountered in chip operation.
 This principle of the invention, moreover, has application not only to the
 substrate, but also can be applied to the ring and lid structures, as
 appropriate.
 III Unit Area Composition Control
 Recall that control of individual layer thickness can vary as much as
 .+-.15% from the desired thickness. These thickness irregularities create
 further bending in the substrate, or other chip package components as
 described above. In addition, the various layers may contain differing
 compositions at different points in the layer. This might occur as a
 result of patterning of a metal layer to form discrete conductive
 pathways. A chip package, manufactured in accordance with a process that
 further characterizes the invention, however, will provide valuable
 reductions in bending stress. In accordance with this feature of the
 invention, chip package components (of which the substrate is
 illustrative) are divided into small unit areas. The unit area composition
 in each layer progressively toward the outer surface of the component is
 analyzed to determine if all of the portions of the layers that are equal
 in distance from the plane of symmetry in the substrate under each unit
 area contain essentially equal amounts of the same materials. Respective
 layers are adjusted and controlled to produce a chip package component in
 which quantities of the same materials that are in each opposing layer
 within a unit area are approximately equal in amount, thereby providing a
 structure that has a generally low warpage throughout.
 IV Die Area CTE Control
 Through careful analysis of CTE mechanisms in the microcosm of chip package
 technology, and in accordance with another feature of the invention, it
 has been found from the standpoint of maintaining chip flatness through
 the range of expected operating temperatures, that the CTE of the
 substrate immediately under the die is very important. If there is a CTE
 mismatch within the die area of the substrate and the overlaying chip,
 undesirable and potentially destructive bending or electrical contact
 shearing stresses will be applied to the chip and chip-substrate
 electrical connections. A salient feature of the invention, however,
 overcomes this difficulty by approximating the CTE of the substrate die
 area to that of the chip, while matching the average CTE of the chip
 package, and more particularly, the average CTE of the substrate, to the
 CTE of the circuit board to which the packaged microchip is attached.
 This feature of the invention reduces relative differences in CTE between
 the substrate and the chip, thereby avoiding the differential in thermal
 expansion that produces bending stresses in the chip, solder joint
 shearing and fatigue. Thus, the chip and the die areas of the substrate,
 both enjoying generally the same CTE, expand and contract together as the
 temperatures change. By expanding and contracting together, relative
 movement between chip and die area of the substrate that in the prior art
 forced the chip to curve or to bend and applied shearing forces to solder
 joints is eliminated. Further, by matching the average CTE of the
 substrate and the associated chip package to the CTE of the printed
 circuit board, relative movement and the concomitant bending stresses and
 shearing forces between the chip package and the printed circuit board are
 also reduced.
 V Selective CTE Adjustment
 To further cope with bending stresses of thermal origin, the invention also
 provides for an unusual technique that selectively adjusts the CTE of one
 layer of material to approximate that of another layer. A structure of
 this character has two or more grooves, recesses, or holes, of any
 predetermined and desired shape, formed in a matrix layer. These holes, or
 loci, are filled with another material that has a CTE which is
 significantly different from the matrix layer CTE. On heating, the
 material in the holes expands at a rate and extent that is unlike the
 surrounding matrix in which the loci are formed. Although this
 differential expansion creates matrix layer stresses, at least in the
 vicinity of each of the loci, the aggregate effect of the expanded hole
 filler material, pressing against the surrounding portions of the matrix,
 increases the actual CTE of the matrix layer. Through an appropriate
 selection of the number and arrangement of the loci formed in the matrix
 and choice in filler material (or materials), within limits, the matrix
 layer or portions of that layer can be adjusted to produce a predetermined
 CTE.
 The opposite result also can be achieved through the practice of the
 invention by fitting the matrix holes with an appropriate substance that
 adheres to the surfaces of the holes. Thus, on application of a
 temperature appropriate to a degree in which the matrix hole filling
 substance shrinks (in comparison with the matrix) the force applied by the
 substance to the matrix contracts the matrix to a greater degree than that
 of a matrix that has not been treated in accordance with the invention.
 Consequently, the matrix that is so treated takes on CTE shrinkage
 characteristics that can differ markedly from the CTE of the basic matrix
 material.
 Applying this feature of the invention to the chip package, the substrate
 layers can be provided with a selected number and distribution of holes in
 the die area. These holes, filled with materials that have different CTE's
 than the surrounding matrix, approximate the aggregate CTE of the die area
 matrix in order to approach the CTE of the overlaying chip. Toward the
 periphery of the matrix, and under the ring, however, a different
 combination of matrix holes and filler materials are chosen to enable the
 aggregate CTE for this portion of the matrix layer to approach the CTE of
 the overlaying ring. Through proper selection of the number of holes,
 their distribution in the layers and the filler material for these holes
 it is now possible through the practice of the invention to adjust the
 matrix CTE, and thereby generally relieve both chip bending and bending
 stresses.
 VI Chip Package Lid CTE Adjustment
 It will be recalled, moreover, that the chip is a very concentrated source
 of heat, a heat that must be dissipated if the chip is to continue to
 function properly or, in extreme situations, to function at all. A
 thermally conductive interface can be applied to the die area between the
 chip and the overlaying lid to conduct heat from the chip to the die area
 of the lid in order to spread heat generated in the chip over a large
 portion of the surface area of the lid. A typical interface suitable for
 use with the invention is described in J. G. Ameen et al. U.S. Pat. No.
 5,545,473 granted Aug. 13, 1996 and titled "Thermally Conductive
 Interface."
 In those situations in which the chip is to be bonded to the die area of
 the lid, once more the stresses and bending effects imposed by differences
 between the chip CTE and the lid CTE become important. Ordinarily, chip
 package lids are formed from copper or aluminum. Alternatively, a
 combination of aluminum and silicon carbide or copper and silicon carbide
 or other low CTE reinforcement could be used. In accordance with another
 salient characteristic of the invention, it has been noted, for example,
 that aluminum has a CTE of 23 PPM/.degree.C. Consequently, by manipulating
 the ratio of aluminum to silicon carbide in different portions of the lid,
 any predetermined CTE in a spectrum that extends from 23 PPM/.degree.C.
 for pure aluminum to 3.7 PPM/.degree.C. for pure silicon carbide can be
 prepared.
 With this knowledge, a high silicon carbide and low aluminum concentration
 composition can be established in the die area for the lid in order to
 match the CTE of the chip that is bonded to the adjoining portion of the
 lid. The marginal portions of the lid that are bonded to the ring,
 however, are of a different aluminum/silicon carbide proportions. In this
 instance, the relative concentrations of aluminum and silicon carbide in
 the marginal portions of the lid are selected such that the average CTE of
 the lid matches the average CTE of the substrate/die combination. Through
 this technique, relative movement between the chip and the die area of the
 lid, the ring and the portion of the lid that is bonded to the ring and
 consequent bending as a function of thermal expansion is avoided, enabling
 each of the chip package components to remain essentially flat, while
 lowering stress on the die or adhesive interface.
 The desired concentrations of aluminum and silicon carbide (to name just
 two of the possible materials) can be prepared in several ways. One of
 these techniques that also characterize the invention provides a porous
 shape with the same dimensions as the outside dimensions of the ring. The
 shape has a thickened central core of porous silicon carbide with
 dimensions about equal to the die area. One or more peripheral recesses at
 the margin of the shape establish a concentration of silicon carbide which
 matches, in part, the CTE of the ring. Molten aluminum is essentially
 dissolved in the porous silicon carbide matrix, the relative proportions
 of aluminum and silicon carbide varying over the span of the shape to
 match the respective CTE of each of the underlaying components. In this
 way, the lid's peripheral CTE approximates a predetermined value (e.g.,
 the CTE of the ring). Thus, through the practice of this feature of the
 invention, a lid is provided with very diverse thermal expansion
 characteristics, these characteristics matching the CTE of the lid die
 area to that of the chip and the peripheral CTE of the lid to that of the
 ring.
 VII CTE Cancellation
 An additional feature of the invention counterbalances, or cancels, the
 bending moments that otherwise would be applied by the substrate to the
 chip, thereby eliminating relative movement between the substrate and the
 chip and thus avoiding the associated bending of the chip that this
 relative movement would cause. In this characteristic embodiment of the
 invention, electrically inactive components or passive electrical
 components (e.g., capacitors, resistors and inductors) that have the same
 CTE or a CTE that is similar to that of the active chip are coupled to the
 exposed die area surface of the substrate on the side of the substrate
 that is opposite to the side to which the electrically active chip is
 coupled. Because the electrically active chip and the electrically passive
 or inactive elements both enjoy essentially the same CTE, the thermal
 expansions of both chips are about equal. Relative movements of these
 chips with respect to the substrate, although equal, are on opposite sides
 of the substrate, thereby effectively cancelling any chip-related bending
 moments that otherwise would occur. In this situation, the electrically
 active chip remains suitably flat.
 A further embodiment of this feature of the invention provides for the
 insertion of a stiffener in the die area of the substrate to prevent that
 portion of the substrate from bending relative to the chip mounted
 directly over that portion of the substrate, through the range of device
 operating temperatures. So mounted, the stiffener generally overcomes the
 undesirable substrate warping in the chip die area.
 Thus, in accordance with the principles of the invention, there is provided
 method and apparatus for overcoming the potentially destructive effects of
 relative movements among chip package components. The scope of the
 invention is limited, however, only through the claims appended hereto.

EXAMPLE 1
 A fine dispersion was prepared by mixing 281.6 g TiO.sub.2 (TI Pure R-900,
 Du Pont Company) into a 20% (w/w) solution of a flame retarded
 dicyanamide/2-methylimidazole catalyzed bisphenol-A based polyglycidyl
 ether (Nelco N-4002-5, Nelco Corp.) in MEK. The dispersion was constantly
 agitated so as to insure uniformity. A swatch of expanded PTFE was then
 dipped into the resin mixture. The web was dried at 165.degree. C. for 1
 min. under tension to afford a flexible composite. The partially-cured
 adhesive composite thus produced comprised of 57 weight percent TiO.sub.2,
 13 weight percent PTFE and 30 weight percent epoxy adhesive. Several plies
 of the adhesive sheet were laid up between copper foil and pressed at 600
 psi in a vacuum-assisted hydraulic press at temperature of 225.degree. C.
 for 90 min. then cooled under pressure. This resulted in a copper laminate
 having dielectric constant of 19.0, and withstood a 30 sec. solder shock
 at 280.degree. C. at an average ply thickness of 100 mm (0.0039"(3.9 mil))
 dielectric laminate thickness.
 EXAMPLE 2
 A fine dispersion was prepared by mixing 386 g SiO.sub.2 (HW-11-89,
 Harbison Walker Corp.) which was pretreated with phenyltrimethoxysilane
 (04330, Huls/Petrarch) into a manganese catalyzed solution of 200 g
 bismaleimide triazine resin (BT206OBJ, Mitsubishi Gas Chemical) and 388 g
 MEK. The dispersion was constantly agitated so as to insure uniformity. A
 swatch of 0.0002" thick expanded PTFE was then dipped into the resin
 mixture, removed, and then dried at 165.degree. C. for 1 min. under
 tension to afford a flexible composite. Several plies of this prepreg were
 laid up between copper foil and pressed at 250 psi in a vacuum-assisted
 hydraulic press at temperature of 225.degree. C. for 90 min. then cooled
 under pressure. This resulting dielectric thus produced comprised of 53
 weight percent SiO.sub.2, 5 weight percent PTFE and 42 weight percent
 adhesive, displayed good adhesion to copper, dielectric constant (at 10
 GHz) of 3.3 and dissipation factor (at 10 GHz) of 0.005.
 EXAMPLE 3
 A fine dispersion was prepared by mixing 483 g SiO.sub.2 (HW-11-89) into a
 manganese-catalyzed solution of 274.7 g bismaleimide triazine resin
 (BT2060BJ, Mitsubishi Gas Chemical) and 485 g MEK. The dispersion was
 constantly agitated so as to insure uniformity. A swatch of 0.0002" thick
 expanded PTFE was then dipped into the resin mixture, removed, and then
 dried at 165.degree. C. for 1 min. under tension to afford a flexible
 composite. Several plies of this prepreg were laid up between copper foil
 and pressed at 250 psi in a vacuum-assisted hydraulic press at temperature
 of 225.degree. C. for 90 minutes then cooled under pressure. The resulting
 dielectric thus produced comprised of 57 weight percent SiO.sub.2, 4
 weight percent PTFE and 39 weight percent adhesive, displayed good
 adhesion to copper, dielectric constant (at 10 GHz) of 3.2 and dissipation
 factor (at 10 GHz) of 0.005.
 EXAMPLE 4
 A fine dispersion was prepared by mixing 15.44 kg TiO.sub.2 powder (TI Pure
 R-900, DuPont Company) into a manganese-catalyzed solution of 3.30 kg
 bismaleimide triazine resin (BT206OBH, Mitsubishi Gas Chemical) and 15.38
 kg MEK. The dispersion was constantly agitated so as to insure uniformity.
 A swatch of 0.0004" TiO.sub.2 -filled expanded PTFE (filled according to
 the teachings of Mortimer U.S. Pat. No. 4,985,296, except to 40% loading
 of TiO.sub.2 and the membrane was not compressed at the end) was then
 dipped into the resin mixture, removed, and then dried at 165.degree. C.
 for 1 min. under tension to afford a flexible composite. The partially
 cured adhesive composite thus produced comprised of 70 weight percent
 TiO.sub.2, 9 weight percent PTFE and 21 weight percent adhesive. Several
 plies of this prepreg were laid up between copper foil and pressed at 500
 psi in a vacuum-assisted hydraulic press at temperature of 220.degree. C.
 for 90 minutes then cooled under pressure. This resulting dielectric
 displayed good adhesion to copper, dielectric constant of 10.0 and
 dissipation factor of 0.008.
 EXAMPLE 5
 A fine dispersion was prepared by mixing 7.35 kg SiO.sub.2 (ADMATECHS
 SO-E2, Tatsumori LTD) with 7.35 kg MEK and 73.5 g of coupling agent,
 i.e.,3-glycidyloxypropyltri-methoxysilane (Dynasylan GLYMO (Petrach
 Systems). SO-E2 is described by the manufacture as having highly spherical
 silica having a particle diameter of 0.4 to 0.6 mm, a specific surface
 area of 4-8 m.sup.2 /g, a bulk density of 0.2-0.4 g/cc (loose).
 To this dispersion was added 932 g of a 50% (w/w) solution of a cyanated
 phenolic resin, Primaset PT-30 (Lonza Corp.). In (MEK) methylethylketone,
 896 g of a 50% (w/w) solution of RSL 1462 (Shell Resins, Inc.(CAS
 #25068-38-6)) in MEK, 380 g of a 50% (w/w) solution of BC-58 (Great Lakes,
 Inc.) in MEK, 54 g of 50% solution of bisphenol A (Aldrich Company) in
 MEK, 12.6 g Irganox 1010 (Ciba Geigy), 3.1 g of a 0.6% solution of
 Manganese 2-ethylhexanoate (Mn HEX-CEM (OMG Ltd.), and 2.40 kg MEK. This
 dispersion was subjected to ultrasonic agitation through a Misonics
 continuous flow cell for about 20 minutes at a rate of about 1-3
 gal./minute. The fine dispersion thus obtained was further diluted to an
 overall bath concentration of 11.9% solids (w/w).
 The fine dispersion was poured into an impregnation bath. A expanded
 polytetrafluoroethylene web having the node fibril structure of FIGS. 19
 and 20, and the following properties:

Frazier 20.55
 Coverage 9 g/m.sup.2
 Ball Burst 3.2 lbs.
 Thickness 6.5 mil.
 Mean Flow Pore Size 9.0 microns
 The Frazier number relates to the air permeability of the material being
 assayed. Air permeability is measured by clamping the web in a gasketed
 fixture which is provided in circular area of approximately 6 square
 inches for air flow measurement. The upstream side was connected to a flow
 meter in line with a source of dry compressed air. The downstream side of
 the sample fixture was open to the atmosphere. Testing is accomplished by
 applying a pressure of 0.5 inches of water to the upstream side of the
 sample and recording the flow rate of the air passing through the in-line
 flowmeter (a ball-float rotameter that was connected to a flow meter.
 The Ball Burst Strength is a test that measures the relative strength of
 samples by determining the maximum at break. The web is challenged with a
 1 inch diameter ball while being clamped between two plates. The
 Chatillon, Force Gauge Ball/Burst Test was used. The media is placed taut
 in the measuring device and pressure affixed by raising the web into
 contact with the ball of the burst probe. Pressure at break is recorded.
 The web described above was passed through a constantly agitated
 impregnation bath at a speed at or about 3 ft./min, so as to insure
 uniformity. The impregnated web is immediately passed through a heated
 oven to remove all or nearly all the solvent, and is collected on a roll.
 Several plies of this prepeg were laid up between copper foil and pressed
 at 200 psi in a vacuum-assisted hydraulic press at temperature of
 220.degree. C. for 90 minutes and then cooled under pressure. This
 resulting dielectric displayed good adhesion to copper, dielectric
 constant (10 GHz) of 3.0 and dissipation factor of 0.0085 (10 GHz).
 The physical properties of the particulate filler used in Example 4 and
 Example 7 are compared below.

Property Tatsumori (ADMATECHS) Harbison Walker
 Manufacture Vapor Metal Combustion Amorphous Fused Silica
 Technique
 Designation Silica SO-E2 HW-11-89
 Median Particle 0.5 micron 5 micron
 Size
 Shape Spherical Irregular, jagged
 Surface Area 6-10 m.sup.2 /g 10 m.sup.2 /g
 Bulk Density 0.47 g/cc 1.12 g/cc
 Specific Density 2.26 g/cc 2.16 g/cc
 EXAMPLE 6
 An ePTFE matrix containing an impregnated adhesive filler mixture, based on
 SiO.sub.2 prepared from the vapor combustion of molten silicon is prepared
 as follows. Two precursor mixtures were initially prepared. One being in
 the form of a slurry containing a silane treated silica similar to that of
 Example 5 and the other an uncatalyzed blend of the resin and other
 components.
 Mixture I
 The silica slurry is a 50/50 blend of the SO-E2 silica of Example 5 in MEK,
 where the silica contains a coated of silane which is equal to 1% of the
 silica weight. To a five gallon container, 17.5 pounds of MEK and 79 grams
 of silane were added and the two components mixed to ensure uniform
 dispersion of the silane in the MEK. Then, 17.5 pounds of the silica of
 Example 5 were added. Two five gallon containers of the MEK-silica-silane
 mixture were added to a reaction vessel, and the contents, i.e., the
 slurry, was recirculated through an ultrasonic disperser for approximately
 one hour to break up any silica agglomerates that may be present. The
 sonication was completed and the contents of the reaction vessel were
 heated to approximately 80.degree. C. for approximately one hour, while
 the contents were continuously mixed. The reacted mixture was then
 transferred into a ten gallon container.
 Mixture II
 The desired resin blend product is an MEK based mixture containing an
 uncatalyzed resin blend (the adhesive) contains approximately 60% solids,
 where the solid portion is an exact mixture of 41.2% PT-30 cyanated
 phenolic resin, 39.5% RSL 1462 epoxy resin, 16.7% BC58 flame retardant,
 1.5% Irganox 1010 stabilizer, and 1% bisphenol A co-catalyst, all
 percentages by weight.
 Into a ten gallon container, 14.8 pounds of PT-30 and 15-20 pounds of MEK
 were added and stirred vigorously to completely solvate the PT-30. Then 6
 pounds of BC58 were measured and added to the MEK/PT-30 solution and
 vigorously agitated to solvate the BC58. The stabilizer, 244.5 grams of
 Irganox 1010 and bisphenol A, 163 grams were added. The ten gallon
 container was reweighed and 14.22 pounds of RSL 1462 were added.
 Additional MEK was added to bring the mixture weight to 60 pounds. The
 contents were then vigorously agitated for approximately 1 to 2 hours, or
 as long is necessary to completely dissolve the solid components.
 The desired product is a mixture of the silica treated with a silane, the
 uncatalyzed resin blend, and MEK in which 68% by weight of the solids are
 silica, and the total solids are between 5% and 50% by weight of the
 mixture. The exact solids concentration varies from run to run, and
 depends in part on the membrane to be impregnated. The catalyst level is
 10 ppm relative to the sum of the PT-30 and RSL1462.
 The solid contents of mixtures I and II were determined to verify the
 accuracy of the precursors and compensate for any solvent flash that had
 occurred. Then mixture I was added to a ten gallon container to provide 12
 pounds of solids, e.g., 515 solids content, 23.48 pounds of mixture I.
 Then mixture II was added to the container to provide 5.64 pounds of
 solids, e.g., 59.6% solids, 9.46 pounds of mixture II. the manganese
 catalyst solution (0.6% in mineral spirits), 3.45 grams, was added to the
 mixture of mixture I and mixture II and blended thoroughly to form a high
 solids content mixture.
 The bath mixture for impregnating an ePTFE matrix, 28% solids mixture, was
 prepared by adding sufficient MEK to the high solids content mixture to a
 total weight of 63 pounds.
 Thereafter, an ePTFE matrix was impregnated with this bath mixture to form
 a dielectric material.
 EXAMPLE 7
 A fine dispersion was prepared by mixing 26.8 grams Furnace Black (Special
 Schwarz 100, Degussa Corp., Ridgefield Park, N.J.) and 79 grams of
 coupling agent (Dynaslan GLYMO CAS #2530-83-8;
 3-glycidyloxypropyl-trimethoxysilane (Petrach Systems). The dispersion was
 subjected to ultrasonic agitation for 1 minute, then added to a stirring
 dispersion of 17.5 pounds SiO.sub.2 (SO-E2) in 17.5 pounds MEK which had
 previously been ultrasonically agitated. The final dispersion was heated
 with constant overhead mixing for 1 hour at reflux, then allowed to cool
 to room temperature.
 Separately, an adhesive varnish was prepared by adding the following: 3413
 grams of a 57.5% (w/w) mixture of Primaset PT-30 in MEK, 2456 grams of a
 76.8% (w/w/) mixture of RSL 1462 in MEK, 1495 grams of a 53.2% (w/w)
 solution of BC58 (Great Lakes, Inc.) in MEK, 200 grams of 23.9% (w/w)
 solution of bisphenol A (Aldrich Company) in MEK, 71.5 grams Irganox 1010,
 3.21 grams of a 0.6% (w/w) solution of Mu HEX-CEM (OMG Ltd.) in mineral
 spirits, and 2.40 kg MEK.
 In a separate container, 3739 grams of the dispersion described above was
 added, along with 0.0233 grams of Furnace Black (Special Schwarz 100,
 Degussa Corp., Ridgefield Park, N.J.), 1328 of the adhesive varnish
 described above and 38.3 pounds MEK. This mixture was poured into an
 impregnation bath, and an ePTFE web was passed through the impregnation
 bath at a speed at or about 3 ft/min. This dispersion was constantly
 agitated so as to insure uniformity. The impregnated web is immediately
 passed through a heated oven to remove all or nearly all the solvent, and
 is collected on a roll.
 Several piles of this prepeg were laid up between copper foil and pressed
 at 200 psi in a vacuum-assisted hydraulic press at temperatures of
 200.degree. C. for 90 minutes then cooled under pressure. This resulting
 dielectric displayed good adhesion to copper.
 EXAMPLE 8
 An adhesive varnish was prepared by adding the following: 3413 grams of a
 57.5% (w/w) solution of Primaset PT-30 (PMN P-88-1591)) in MEK, 2456 grams
 of a 76.8% (w/w) solution of RSL 1462 in MEK, 1495 grams of a 53.2% (w/w)
 solution of BC58 (Great Lakes, Inc.) in MEK, 200 grams of 23.9% (w/w)
 solution of bisphenol A (Aldrich Company) in MEK, 71.5 grams Irganox 1010,
 3.21 grams of a 0.6% (w/w) solution of Mn HEX-CEM in mineral spirits, and
 2.40kg MEK.
 In a separate container, 1328 grams of the adhesive varnish described
 above, 42.3 pounds MEK, 6.40 grams of Furnace Black (Special Schwarz 100,
 Degussa Corp., Ridgefield, N.J.) and 1860.9 grams SiO.sub.2 (SO-E2). This
 mixture was poured into an impregnation bath, and an ePTFE web was passed
 through the impregnation bath at a speed at or about 3 ft/min. The
 dispersion was constantly agitated so as to insure uniformity. The
 impregnated web is immediately passed through a heated oven to remove all
 or nearly all the solvent, and is collected on a roll.
 Several piles of this prepeg were laid up between copper foil and pressed
 at 200 psi in a vacuum-assisted hydraulic press at temperature of
 220.degree. C. for 90 minutes then cooled under pressure. This resulting
 dielectric displayed good adhesion to copper.
 Although the invention has been described in conjunction with specific
 embodiments, it is evident that many alternatives and variations will be
 apparent to those skilled in the art in light of the foregoing description
 and annexed drawings. Accordingly, the invention is intended to embrace
 all of the alternatives and variations that fall within the spirit and
 scope of the appended claims.