Narrow channel width effect modification in a shallow trench isolation device

A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

BACKGROUND

An integrated circuit (IC) is formed by creating one or more devices (e.g., circuit components) on a semiconductor substrate. Each device is separated from the other devices using an isolation feature such as a shallow trench isolation (STI) structure. However, some devices have detrimental narrow channel width effects, such as different threshold voltage (Vt) behavior with different gate width devices. This is because the oxygen (O) elements in shallow trench isolation (STI) oxide materials can diffuse into the gate stack and influence the Vt of the CMOS or other device. This phenomenon leads to perplexity for an IC designer to design a circuit with different dimension devices.

As such, there is a need for a narrow channel width effect modification in a shallow trench isolation (STI) device.

DETAILED DESCRIPTION

FIG. 1is a flowchart of a method100making an integrated circuit.FIGS. 2,3band4-6are sectional views of at least a portion of a semiconductor structure200during various manufacturing stages.FIG. 3ais a sectional view of at least a portion of the semiconductor structure during a manufacturing stage in another embodiment. The method100and the semiconductor structure200are collectively described with reference toFIG. 1throughFIG. 6.

Referring toFIGS. 1 and 2, the method100begins at step102by providing a semiconductor substrate210. The semiconductor substrate210includes silicon. Alternatively, the substrate210includes germanium or silicon germanium. In other embodiments, the substrate210may use another semiconductor material, such as diamond, silicon carbide, gallium arsenic, GaAsP, AlInAs, AlGaAs, GaInP, or other proper combination thereof. Furthermore, the semiconductor substrate may be a bulk semiconductor such as bulk silicon. The bulk silicon may further include an epitaxy silicon layer.

In other examples, a dielectric material layer may be incorporated into the semiconductor substrate210and present underlying well structures of the semiconductor substrate for proper isolation effect. In one embodiment, the dielectric insulator layer includes a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, or wafer bonding. In another embodiment, the dielectric material layer may also be formed on the substrate by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and/or other processes. Chemical mechanical polishing (CMP) and/or other methods may be employed to attain a desired thickness of the insulator layer. Moreover, although not limited by the scope of the present disclosure, the insulator layer may include oxide, silicon oxide, silicon nitride, silicon oxynitride, low k materials, air gap, combinations thereof, and/or other materials.

Still referring toFIGS. 1 and 2, the method100proceeds to step104by forming a hard mask layer on the semiconductor substrate210. In one embodiment, a pad silicon oxide layer212is formed on the silicon substrate210. The pad silicon oxide layer212is formed by a thermal oxidation process. In one example, the pad silicon oxide layer212has a thickness about 90 angstroms. In another example, the pad silicon oxide212may have a thickness ranging between about 50 angstroms and about 200 angstroms. Then, a silicon nitride layer214is formed on the pad silicon oxide layer212. The silicon nitride layer214can be formed by a low pressure chemical vapor deposition (LPCVD) process. For example, the precursor including dichlorosilane (DCS or SiH2Cl2), bis(tertiarybutylamino)silane (BTBAS or C8H22N2Si), and disilane (DS or Si2H6) is used in the CVD process to form the silicon nitride layer214. In one example, the silicon nitride layer214has a thickness of about 800 angstroms. In another example, the silicon nitride layer214may have a thickness ranging between about 400 angstroms and about 1500 angstroms. The silicon nitride layer is used as the hard mask for subsequent etching and implanting processes. Alternatively, other dielectric material may be used as the hard mask. For example, silicon oxynitride may be formed as the hard mask.

Still referring toFIGS. 1 and 2, the method100proceeds to step106by etching the hard mask layer to form one or more openings defining isolation regions on the semiconductor substrate210. A photolithography process and an etching process are used to pattern the hard mask layer such as the silicon nitride layer214. An exemplary photolithography process may include photoresist patterning, etching, and photoresist stripping. The photoresist patterning may further include processing steps of photoresist coating, soft baking, mask aligning, exposing pattern, post-exposure baking, developing photoresist, and hard baking. Photolithography patterning may also be implemented or replaced by other proper methods, such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. The etching process may include a wet etching or dry etching process. In one example, a dry etching process used to etch the silicon nitride includes a chemistry including fluorine-containing gas. In furtherance of the example, the chemistry of the dry etch includes CF4, SF6, or NF3. As another example of the wet etching process to the silicon nitride layer, the etchant includes a phosphoric acid (H3PO4) solution. In another example, a hydrofluoric acid (HF) or buffered HF may be used to etch the silicon dioxide layer212to expose the semiconductor substrate210within the openings defined by the silicon nitride layer214.

Still referring toFIGS. 1 and 2, the method100proceeds to step108by etching the semiconductor substrate such as the silicon substrate using the patterned silicon nitride214as a hard mask, to form one or more trenches216in the substrate, as illustrated in theFIG. 2. In one example, the trenches216may have a thickness of about 0.25 microns for isolation purposes. In another example, the trenches216may have a thickness less than about 1 micron. In one embodiment, a dry etching process is used to etch the substrate and form the trenches. For example, implemented is a dry etching process with a chlorine based etching chemical to form the trenches. In another example, the dry etching process includes fluorine-containing gas, such as CF4, SF6, or NF3. Additionally, a wet etching process may be further applied to form the trenches with a proper profile. For example, a potassium hydroxide (KOH) solution may be applied to further etch the silicon substrate after the trench dry etching process.

Referring toFIGS. 1 and 3a, the method100proceeds to step110by filling the trenches with a dielectric material to form trench isolation features218, referred to as shallow trench isolation (STI) as well. The trench isolation features218include silicon oxide. The silicon oxide can be filled in the trenches by a CVD process. In various examples, the silicon oxide can be formed by a high density plasma chemical vapor deposition (HDPCVD). The silicon oxide may be alternatively formed by a high aspect ratio process (HARP). In another embodiment, the trench isolation features218may include a multi-layer structure. In furtherance of the embodiment, the trench isolation features218include other suitable materials, such as silicon nitride, silicon oxynitride, low k materials, air gap, or combinations thereof, to form the trench isolation features. For example, the trench isolation features218include a thermal oxide lining layer to improve the trench interface. In another example, the trenches are filled with a thermal silicon oxide lining layer and a HDPCVD silicon oxide layer. In another example, the trenches may have a multi-layer structure with a thermal oxide liner layer, a CVD silicon nitride layer, and a CVD silicon oxide layer. As one example illustrated inFIG. 3b, since the pad silicon oxide212and trench isolation features218both include silicon oxide material, the pad silicon oxide212and trench isolation features are collectively labeled by a numeral218. The trench isolation features ofFIG. 3bare continuously used as an example, for simplicity, in the subsequent processing steps associated withFIGS. 4-6.

The trench-filling dielectric material can be additionally formed on the silicon nitride layer214while it fills in the trenches216. Still referring toFIGS. 1 and 3a/3b, the method100proceeds to step112by planarizing the semiconductor substrate after the trenches are filled with one or more dielectric materials. In one embodiment, a chemical mechanical polishing (CMP) process is applied to the semiconductor substrate to remove excessive portions of the trench-filling dielectric material and to form a global planarized surface. As one example, the CMP process can use the silicon nitride layer214as a polishing stop layer so that the CMP process can properly stop at the silicon nitride layer214. Other process may be used to achieve the similar polishing effect. For example, an etch-back process may be used to remove the excessive trench-filling dielectric material and form a global planarized surface. In an embodiment, the silicon nitride layer214will be about 500 angstroms. The method100may include an annealing process applied to the trench isolation features218in the semiconductor substrate. The annealing process uses an annealing temperature ranging between about 800° C. and about 1100° C. In one example, the annealing process may be implemented before the CMP process. Alternatively or additionally, the annealing process may be implemented after the CMP process.

Referring toFIGS. 1 and 4, the method100proceeds to step114by performing a nitrogen (N) ion implantation process to nitrogenize the top surface oxide in the shallow trench isolation region218of the structure200which reduces oxygen (O) concentration in shallow trench isolation area218and forms a SiON to stop diffusion of oxygen. During the ion implantation process, the silicon nitride layer214is used as a hard mask to protect the active regions in the semiconductor substrate210from damage or contamination. A dopant used in the ion implantation includes nitrogen (N). In another embodiment, the dopant used in the ion implantation includes silicon (Si). The dopant concentration implanted in the trench isolation features ranges between about 5×1014cm−2and about 5×1015cm−2. In an embodiment, the ion implanting energy is tuned such that the dopant can be substantially implanted in the trench isolation features. For example, the dopant is distributed in a portion of or a full span of the trench isolation features in vertical direction. In one example, the ion implantation process utilizes nitrogen implantation with an implanting energy ranging between about 20 keV and about 25 keV and a doping concentration ranging between about 5×1014cm−2and about 5×1015cm−2. In an embodiment, the silicon implantation may have an implanting energy of about 70 keV and a doping concentration of about 5×1015cm−2. In an embodiment, a nitrogen-containing portion is formed on the top portion of the a shallow trench isolation feature, such as the features218shown inFIGS. 4-6. As such, in an embodiment, the top potion of the shallow trench isolation area218is doped with nitrogen at a nitrogen concentration range of approximately 1×1020cm−3-1×1021cm−3where the trench is approximately 2900 angstroms having approximately 200 angstroms above a top level of the substrate210. In an embodiment, the nitrogen may be concentrated and distributed at a range of approximately 200-400 angstroms below the top surface of the shallow trench isolation feature218. During the ion implantation at this step, the silicon nitride214is used as a natural hard mask self-aligned with the active regions such that the active regions of the semiconductor substrate are protected from the ion implantation and the damage thereof. As mentioned above, other suitable dielectric materials may be used as a hard mask for trench etching and the ion implantation.

It is noted that heat energy may be added during the ion implantation. It should be understood that the ion implantation may take place using one or more implants and the different implants may be the same or different doping concentrations and the same or different implanting energies. For example, nitrogen (N) may be implanted in a single ion implant step with an implanting energy of about 20 keV and a doping concentration of about 5×1014cm−2. In another example, nitrogen (N) may be implanted in a single ion implant step with an implanting energy of about 20 keV and a doping concentration of about 5×1015cm−2. In yet another example, nitrogen (N) may be implanted in a single ion implant step with an implanting energy of about 25 keV and a doping concentration of about 5×1015cm−2. In another embodiment, nitrogen (N) may be implanted in two ion implant steps where the first ion implant has an implanting energy of about 25 keV and a doping concentration of about 5×1015cm−2and the second ion implant has an implanting energy of about 20 keV and a doping concentration of about 5×1014cm−2. In another example, nitrogen (N) may be implanted in two ion implant steps where the first ion implant has an implanting energy of about 25 keV and a doping concentration of about 5×1015cm−2and the second ion implant has an implanting energy of about 20 keV and a doping concentration of about 5×1015cm−2. In yet another embodiment, nitrogen (N) may be implanted in two ion implant steps where the first ion implant has an implanting energy of about 25 keV and a doping concentration of about 5×1015cm−2and the second ion implant has an implanting energy of about 25 keV and a doping concentration of about 5×1015cm−2. As should be readily understood by those having ordinary skill in the art, other steps, other implanting energies and other doping concentrations may be used with the present disclosure.

Referring toFIGS. 1 and 5, the method100proceeds to step116by forming a capping layer220on the semiconductor substrate210covering the silicon nitride mask214and the trench isolation features218. The capping layer220includes silicon nitride. In another embodiment, the capping layer220may include other suitable materials such as silicon oxide. In various embodiments, the capping layer220includes silicon nitride formed by a low pressure CVD (LPCVD), or a silicon nitride formed by a plasma enhanced CVD (PECVD), or tetraethyl orthosilicate formed by a CVD process, or a silicon oxide formed by a high aspect ratio process (HARP). Other processes such as, low pressure chemical vapor deposition (LPSiN), plasma enhanced chemical vapor deposition (PESiN) or tetraethoxysilane Si(OC2H5)4, also TEtraethyl OrthoSilicate (TEOS) may be used to form the capping layer220. The capping layer220includes a thickness of about 800 angstroms. In another embodiment, the capping layer220has a thickness ranging between about 800 angstroms and about 1500 angstroms.

Still referring toFIGS. 1 and 5, the method100proceeds to step118by performing an annealing process to the semiconductor structure200after the capping layer is formed thereon. The annealing process is applied to the semiconductor substrate with the capping layer220for preventing implant-ions out diffusion. Thus, the annealing forms silicon oxy nitride (SiON) on the surface region above the semiconductor substrate210. As such, the additional nitrogen (N) ion implanting, capping layer220and thermal annealing treatment in the shallow trench isolation (STI) process will (1) nitrogenize the top surface of the STI oxide, (2) further reduce the oxygen (O) diffusion from STI oxide to gate stack, and (3) improve the narrow channel effect such as the uniformity of Vt with different width devices.

In one embodiment, the annealing process is implemented in a rapid thermal annealing (RTA) tool. In another embodiment, the annealing process is applied to the semiconductor structure200with an annealing temperature ranging between about 1000° C. and about 1100° C. In another embodiment, the annealing process is applied to the semiconductor structure200with an annealing duration ranging between about 10 minutes and about 30 minutes. In an embodiment, the annealing chamber is nitrogenized to remove oxygen from the chamber. In an embodiment, the annealing is performed at a pressure of about 1.3 atm.

Referring toFIGS. 1 and 6, the method100proceeds to step120by removing the capping layer220and the silicon nitride mask214from the semiconductor structure200. The etching process may include a wet etching or a dry etching process. In one example of the semiconductor structure with a silicon nitride capping layer and a silicon nitride mask layer, both the capping layer and the hard mask layer are removed by one etching process. For example, silicon nitride can be etched away by a phosphoric acid solution. In another example of the silicon oxide capping layer and the silicon nitride hard mask layer, the silicon oxide layer is etched away by a hydrofluoric acid (HF) or buffered HF and the silicon nitride layer is etched away by a phosphoric acid solution. In another example, the silicon oxide capping layer is removed by a CMP process and the silicon nitride mask layer is removed by a wet etching process using a phosphoric acid solution.

Although embodiments of the present disclosure have been described in detail, those skilled in the art should understand that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. For example, the ion implantation process to the trench isolation features may be performed before the CMP process step112. In another embodiment, another ion implantation process is additionally applied to the trench isolation features218to nitrogenize the top surface oxide in shallow trench isolation (STI).

Although not shown, other processing steps may present to form various doped regions, such as source and drain regions, and device features, such as gate stacks and multilayer interconnection (MLI). In one example, a gate feature is formed on the semiconductor substrate210. The gate feature may include a gate dielectric, a gate electrode, a silicide contact layer, and gate spacers. The gate dielectric includes silicon oxide, silicon oxynitride, high-k material, or combinations thereof. The gate electrode may include doped polysilicon, metal, metal silicide, other conductive material, or combinations thereof. The silicide contact layer includes nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. The gate spacers may have a multilayer structure and may include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

The semiconductor structure200also includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and silicide. In one example, a damascene process is used to form copper related multilayer interconnection structures. In another embodiment, tungsten is used to form tungsten plugs in the contact holes.

The semiconductor structure200further includes doped source and drain regions and light doped drain regions of either an n-type dopant or a p-type dopant formed by a conventional doping process such as ion implantation. N-type dopant impurities employed to form the doped regions may include phosphorus, arsenic, and/or other materials. P-type dopant impurities may include boron, indium, and/or other materials.

The present disclosure is not limited to applications in which the semiconductor structure200has a gate structure or a MOS transistor, and may be extended to any integrated circuit. For example, in other embodiments, the semiconductor structure200may include a memory device, a sensor device, and/or other microelectronic devices (collectively referred to herein as microelectronic devices). In another embodiment, the semiconductor structure200may include FinFET transistors. Of course, aspects of the present disclosure are also applicable and/or readily adaptable to any type of transistor, including single-gate transistors, double-gate transistors, and other multiple-gate transistors, and may be employed in many different applications, including sensor cells, memory cells, logic cells, and others.

The semiconductor structure200serves as only one example of a device within which various aspects ofFIGS. 1-6may be implemented. The semiconductor structure200and the method of making the same may be used in other semiconductor devices having high k and metal gate features, a strained semiconductor substrate, a hetero-semiconductor device, or a stress-free isolation structure.

Thus, the present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

In the present disclosure, the performing of the ion implantation may include implanting G, Si, N, Ar, F, and As. The forming of the hard mask pattern may include forming a silicon nitride layer. The forming of the hard mask pattern may further include patterning the silicon nitride layer. The disclosed method may further include performing a thermal process to the semiconductor substrate after the performing of the ion implantation. The performing of the thermal process may include performing an annealing process with an annealing temperature ranging between about 1000° C. and about 1100° C. The disclosed method may further include forming a capping film on the semiconductor substrate after the performing of the ion implantation and before the performing of the thermal process. The forming of the capping film may include forming a dielectric material selected from the group consisting of low pressure chemical vapor deposition silicon nitride (LPSiN), plasma enhance chemical vapor deposition silicon nitride (PESiN), and tetraethyl orthosilicate (TEOS) and silicon oxide by high aspect ratio process (HARP oxide). The disclosed method may further include removing the hard mask pattern after the performing of the ion implantation.

The present disclosure also provides another embodiment of a method of manufacturing a semiconductor structure. The method includes forming a thermal silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on the thermal silicon oxide layer; patterning the silicon nitride layer and thermal silicon oxide layer to form silicon nitride mask defining openings exposing portions of the semiconductor substrate; forming trenches in the semiconductor substrate within the openings; filling the trenches with a dielectric material, resulting in shallow trench isolation (STI) features; performing an ion implantation to the STI features using the silicon nitride mask to protect active regions of the semiconductor substrate; thereafter forming a capping film on the semiconductor substrate; thereafter performing a thermal annealing process to the semiconductor substrate; and thereafter removing the capping film and the silicon nitride mask.

In the disclosed method, the performing of the ion implantation may include applying an implantation energy ranging between about 20 keV and about 25 keV and an implantation dose ranging between about 5×1014cm−2and about 5×1015cm−2. The disclosed method may further comprises a second ion implantation to the STI features after the removing of the capping film and the silicon nitride. The performing of the ion implantation may include implanting a species selected from the group consisting of Si, N, Ge, Ar, F, As, and combinations thereof. The performing of the thermal annealing process may include applying an annealing process of a temperature ranging between about 1000° C. and about 1100° C. and a processing duration ranging between about 10 minutes and about 30 minutes. The disclosed method may further include planarizing the semiconductor substrate after the filling of the trenches and before the performing of the ion implantation.

The present disclosure also provides another embodiment of a method of manufacturing a semiconductor structure. The method includes forming a shallow trench isolation feature having a dielectric material in a silicon substrate within an opening of a silicon nitride layer on the silicon substrate; ion implanting the STI feature using the silicon nitride layer as a hard mask to protect active regions of the silicon substrate; forming a capping film on the silicon substrate; annealing the STI; and removing the capping film and the silicon nitride layer.

In the disclosed method, the dielectric material of the STI may include a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The ion implanting may include implanting a species selected from the group consisting of Si, N, Ge, Ar, F, and As. The disclosed method may further include implanting silicon to the STI after the removing of the capping film and the silicon nitride layer.