Highly efficient micro LED in low current range, method of fabricating the same, and display including the same

Various embodiments may provide a highly efficient micro light-emitting diode (LED) in a low current range, a method of fabricating the same, and a display including the same. The micro LED includes a first conductive type semiconductor layer and a second conductive type semiconductor layer and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a single quantum well structure. The single quantum well structure may be formed so that a ratio of a conduction band offset of any one of the first conductive type semiconductor layer or the second conductive type semiconductor layer and a valence band offset of the other of the first conductive type semiconductor layer or the second conductive type semiconductor layer becomes greater than 0 and less than 1.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application Nos. 10-2020-0026672 filed on Mar. 3, 2020 and 10-2021-0000512 filed on Jan. 4, 2021 in the Korean intellectual property office, the disclosures of which are herein incorporated by reference in their entireties.

TECHNICAL FIELD

Various embodiments relate to a highly efficient micro light-emitting diode (LED) in a low current range, a method of fabricating the same, and a display including the same.

BACKGROUND OF THE INVENTION

In general, a display functions to implement an image based on an electrical signal. To this end, the display includes a pixel array having a plurality of pixels, and outputs image light through each of the pixels. In this case, each of the pixels includes a color filter for displaying desired color light from white light or blue light. However, phosphors within each of the pixels may cause a light loss in each pixel. Accordingly, there is a difficulty in lowering power of each pixel and there is a problem in that efficiency of each pixel is degraded.

SUMMARY

Various embodiments provide a highly efficient micro LED in a low current region, a method of fabricating the same, and a display including the same.

Various embodiments provide a micro LED for which lower power is implemented, a method of fabricating the same, and a display including the same.

According to various embodiments, a micro light-emitting diode (LED) includes a first conductive type semiconductor layer and a second conductive type semiconductor layer and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a single quantum well structure. The single quantum well structure may be formed so that a ratio of a conduction band offset of any one of the first conductive type semiconductor layer or the second conductive type semiconductor layer and a valence band offset of the other of the first conductive type semiconductor layer or the second conductive type semiconductor layer becomes greater than 0 and less than 1.

According to various embodiments, a method of fabricating a micro LED includes preparing a first conductive type semiconductor layer, stacking, on the first conductive type semiconductor layer, an active layer having a single quantum well structure, and stacking a second conductive type semiconductor layer on the active layer. The single quantum well structure may be formed so that a ratio of a conduction band offset of any one of the first conductive type semiconductor layer or the second conductive type semiconductor layer and a valence band offset of the other of the first conductive type semiconductor layer or the second conductive type semiconductor layer becomes greater than 0 and less than 1.

According to various embodiments, a display includes an integrated circuit device in which a driving circuit is wired and a plurality of micro light-emitting diodes (LEDs) mounted on one surface of the integrated circuit device. Each of the micro LEDs includes a first conductive type semiconductor layer and a second conductive type semiconductor layer and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer and having a single quantum well structure. The single quantum well structure may be formed so that a ratio of a conduction band offset of any one of the first conductive type semiconductor layer or the second conductive type semiconductor layer and a valence band offset of another of the first conductive type semiconductor layer or the second conductive type semiconductor layer becomes greater than 0 and less than 1.

According to various embodiments, efficiency of the micro LED can be improved by forming the active layer of the micro LED as a single quantum well structure. In this case, since the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVin the single quantum well structure of the active layer is set to be greater than 0 and less than 1, efficiency of the micro LED in a low current region can be improved. Accordingly, a lower power of the micro LED can also be implemented.

DETAILED DESCRIPTION

Hereinafter, various embodiments of this document are described with reference to the accompanying drawings.

FIG.1is a diagram illustrating a display100according to a first embodiment.

Referring toFIG.1, the display100according to a first embodiment may include an integrated circuit (IC) device110and a plurality of micro light-emitting diodes (LEDs) (hereinafter referred to as “micro LEDs”)120,130, and140.

The IC device110may support the micro LEDs120,130, and140. Furthermore, the IC device110may provide a driving signal to the micro LEDs120,130, and140. At this time, the IC device110may implement an image through the micro LEDs120,130, and140based on the driving signal. In this case, one axis X that penetrates one surface S1of the IC device110may be defined. For example, the one surface S1of the IC device110may be disposed on a plane perpendicular to the one axis X. The IC device110may include at least one of a driving circuit (not illustrated) or a protection layer117. The driving circuit may be wired within the IC device110. Furthermore, the driving circuit may be connected to the micro LEDs120,130, and140in the one surface S1of the IC device110. The protection layer117may protect the one surface S1of the IC device110. Although not illustrated, the protection layer117may expose some of the driving circuit in the one surface S1of the IC device110.

The micro LEDs120,130, and140may be mounted on the one surface S1of the IC device110. In this case, the micro LEDs120,130, and140may be attached to the one surface S1of the IC device110. Furthermore, the micro LEDs120,130, and140may output an image. At this time, each of the micro LEDs120,130, and140may generate light having a predetermined wavelength based on the driving signal of the IC device110. Accordingly, an image may be implemented by a combination of lights generated from the micro LEDs120,130, and140.

For example, the micro LEDs120,130, and140may include a plurality of first micro LEDs120, a plurality of second micro LEDs130, and a plurality of third micro LEDs140. The first micro LEDs120, the second micro LEDs130, and the third micro LEDs140may be arranged in a predetermined pattern in the one surface S1of the IC device110. In this case, the first micro LEDs120, the second micro LEDs130, and the third micro LEDs140may be attached to the one surface S1of the IC device110. To this end, each of the first micro LEDs120includes a first adhesion layer121, and may be attached to the one surface S1of the IC device110through the first adhesion layer121. Likewise, each of the second micro LEDs130includes a second adhesion layer131, and may be attached to the one surface S1of the IC device110through the second adhesion layer131. Each of the third micro LEDs140includes a third adhesion layer141, and may be attached to the one surface S1of the IC device110through the third adhesion layer141. The first micro LEDs120may generate light having a predetermined first wavelength. The second micro LEDs130may generate light having a predetermined second wavelength. The third micro LEDs140may generate light having a predetermined third wavelength. For example, the light having the first wavelength may be a red (R) light, the light having the second wavelength may be a green (G) light, and the light having the third wavelength may be a blue (B) light.

FIG.2is a diagram illustrating a display200according to a second embodiment.

Referring toFIG.2, the display200according to a second embodiment may include an IC device210and a plurality of micro LEDs (hereinafter referred to as “micros LED”)220,230, and240.

The IC device210may support the micro LEDs220,230, and240. Furthermore, the IC device210may provide a driving signal to the micro LEDs220,230, and240. At this time, the IC device210may implement an image through the micro LEDs220,230, and240based on the driving signal. In this case, one axis X that penetrates one surface S2of the IC device210may be defined. For example, the one surface S2of the IC device210may be disposed on a plane perpendicular to the one axis X. The IC device210may include at least one of a driving circuit (not illustrated) or a protection layer217. The driving circuit may be wired within the IC device210. Furthermore, the driving circuit may be connected to the micro LEDs220,230, and240in the one surface S2of the IC device210. The protection layer217may protect the one surface S2of the IC device210. Although not illustrated, the protection layer217may expose some of the driving circuit in the one surface S2of the IC device210.

The micro LEDs220,230, and240may be mounted on the one surface S2of the IC device210. In this case, some micro LEDs220,230, and240may be stacked on the one surface S2of the IC device210. Furthermore, the micro LEDs220,230, and240may output an image. At this time, each of the micro LEDs220,230, and240may generate light having a predetermined wavelength based on the driving signal of the IC device210. Accordingly, an image may be implemented by a combination of lights generated from the micro LEDs220,230, and240.

For example, the micro LEDs220,230, and240may include a plurality of first micro LEDs220, a plurality of second micro LEDs230, and a plurality of third micro LEDs240. The first micro LEDs220may be arranged in a predetermined pattern on the one surface S2of the IC device210. Furthermore, the second micro LEDs230may be stacked on the first micro LEDs220, and the third micro LEDs240may be stacked on the second micro LEDs230. To this end, each of the first micro LEDs220includes a first adhesion layer221, and may be attached to the one surface S2of the IC device210through the first adhesion layer221. Each of the second micro LEDs230includes a second adhesion layer231, and may be attached to the first micro LED220through the second adhesion layer231. Each of the third micro LEDs240includes a third adhesion layer241, and may be attached to the second micro LED230through the third adhesion layer241. The first micro LEDs220may generate light having a predetermined first wavelength. The second micro LEDs230may generate light having a predetermined second wavelength. The third micro LEDs240may generate light having a predetermined third wavelength. For example, the light having the first wavelength may be a red (R) light. The light having the second wavelength may be a green (G) light. The light having the third wavelength may be a blue (B) light.

FIG.3is a diagram illustrating a micro LED300(e.g., the micro LEDs120,130, and140ofFIG.1or the micro LEDs220,230, and240ofFIG.2) according to various embodiments.FIG.4is a diagram for describing a single quantum well (SQW) structure of an active layer330ofFIG.3.FIGS.5A,5B,6,7A,7B,8, and9are diagrams for describing operating characteristics of the micro LED300according to various embodiments.

Referring toFIG.3, the micro LED (hereinafter referred to as a “micro LED”)300according to various embodiments may include a first conductive type semiconductor layer310, a second conductive type semiconductor layer320, and the active layer330.

The first conductive type semiconductor layer310and the second conductive type semiconductor layer320may be stacked with the active layer330interposed therebetween. In this case, the first conductive type semiconductor layer310may be disposed, and the second conductive type semiconductor layer320may be stacked on the first conductive type semiconductor layer310in one axis X. Furthermore, any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320may be configured to inject holes into the active layer330, and the other of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320may be configured to inject electrons into the active layer330.

For example, the first conductive type semiconductor layer310may include a first support layer311and a first barrier layer313. In this case, the first support layer311is disposed. The first barrier layer313is stacked on the first support layer311in the one axis X, and may come into contact with the active layer330. Furthermore, the second conductive type semiconductor layer320may include a second barrier layer323and a second support layer325. In this case, the second barrier layer323is disposed on the active layer330, and may come into contact with the active layer330. The second support layer325may be stacked on the second barrier layer323in the one axis X.

According to one embodiment, the first conductive type semiconductor layer310may be a p type semiconductor layer, and the second conductive type semiconductor layer320may be an n type semiconductor layer. In such a case, the first conductive type semiconductor layer310may be configured to inject holes into the active layer330, and the second conductive type semiconductor layer320may be configured to inject electrons into the active layer330. For example, in the first conductive type semiconductor layer310, the first support layer311may be composed of a gallium-phosphor compound (GaP), and the first barrier layer313may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP). For example, in the second conductive type semiconductor layer320, the second barrier layer323may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP), and the second support layer325may be composed of a gallium-arsenic compound (GaAs).

According to another embodiment, the first conductive type semiconductor layer310may be an n type semiconductor layer, and the second conductive type semiconductor layer320may be a p type semiconductor layer. In such a case, the first conductive type semiconductor layer310may be configured to inject electrons into the active layer330, and the second conductive type semiconductor layer320may be configured to inject holes into the active layer330. For example, in the first conductive type semiconductor layer310, the first support layer311may be composed of a gallium-arsenic compound (GaAs), and the first barrier layer313may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP). For example, in the second conductive type semiconductor layer320, the second barrier layer323may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP), and the second support layer325may be composed of a gallium-phosphor compound (GaP).

The active layer330may be disposed between the first conductive type semiconductor layer310and the second conductive type semiconductor layer320. In this case, the active layer330may be disposed between the first conductive type semiconductor layer310and the second conductive type semiconductor layer320, on the first conductive type semiconductor layer310. Furthermore, the active layer330may absorb holes and electrons from the first conductive type semiconductor layer310and the second conductive type semiconductor layer320, respectively. At this time, the active layer330may generate light having a predetermined wavelength according to which the electrons and the holes injected from the first conductive type semiconductor layer310and the second conductive type semiconductor layer320, respectively, are combined. For example, the active layer330may be composed of an indium-gallium-phosphor compound (InGaP).

According to various embodiments, the active layer330may have a single quantum well (SQW) structure as illustrated inFIG.4. In this case, the first conductive type semiconductor layer310and the second conductive type semiconductor layer320may be composed of the same material, and thus the micro LED300may have a symmetrical structure. Alternatively, the first conductive type semiconductor layer310and the second conductive type semiconductor layer320may be composed of different materials, and thus the micro LED300may have an asymmetrical structure. In the SQW structure, a conduction band offset ΔECfor absorbing electrons from any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320may be defined. Furthermore, in the SQW structure, a valence band offset ΔEVfor absorbing holes from any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320may be defined. In this case, the SQW structure of the active layer330may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVis greater than 0 and less than 1.

According to one embodiment, the first conductive type semiconductor layer310may be a p type semiconductor layer, and the second conductive type semiconductor layer320may be an n type semiconductor layer. In such a case, the first conductive type semiconductor layer310may be configured to inject holes into the active layer330, and the second conductive type semiconductor layer320may be configured to inject electrons into the active layer330. Furthermore, in the SQW structure of the active layer330, a conduction band offset ΔECof the second conductive type semiconductor layer320and a valence band offset ΔEVof the first conductive type semiconductor layer310may be defined. In this case, the SQW structure of the active layer330may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1.

According to another embodiment, the first conductive type semiconductor layer310may be an n type semiconductor layer, and the second conductive type semiconductor layer320may be a p type semiconductor layer. In such a case, the first conductive type semiconductor layer310may be configured to inject electrons into the active layer330, and the second conductive type semiconductor layer320may be configured to inject holes into the active layer330. Furthermore, in the SQW structure of the active layer330, a conduction band offset ΔECof the first conductive type semiconductor layer310and a valence band offset ΔEVof the second conductive type semiconductor layer320may be defined. In this case, the SQW structure of the active layer330may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1.

According to various embodiments, quantum efficiency (or internal quantum efficiency (IQE)) of the micro LED300can be improved. In order to check such improvement, as illustrated inFIG.5A, the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVmay be adjusted in implementing the SQW structure of the active layer330. In this case, the first conductive type semiconductor layer310and the second conductive type semiconductor layer320may be composed of the same material, and thus the micro LED300may have a symmetrical structure. In this case, as illustrated inFIG.5B, the lower the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEV, the better quantum efficiency of the micro LED300is. This may more significantly appear in a low current region. That is, since the SQW structure of the active layer330is formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1, quantum efficiency of the micro LED300can be significantly improved in a low current region.

According to various embodiments, as illustrated inFIG.6, quantum efficiency of the micro LED300in a low current region may be higher than quantum efficiency of the existing micro LED (not illustrated) in a low current region. In this case, each of the micro LED300and the existing micro LED may be implemented to have a symmetrical structure. The existing micro LED may include an active layer (not illustrated) having a multi-quantum well (MQW) structure. As illustrated inFIG.6, the micro LED300can secure the same quantum efficiency in a current reduced by 2500 times, compared to the existing micro LED. That is, since the active layer330having the SQW structure is included, quantum efficiency of the micro LED300can be significantly improved in a low current region.

According to various embodiments, although the first conductive type semiconductor layer310and the second conductive type semiconductor layer320are composed of different materials, quantum efficiency of the micro LED300can be improved. In order to check such improvement, as illustrated inFIG.7A, the first conductive type semiconductor layer310and the second conductive type semiconductor layer320may be composed of different materials, and the micro LED300may be implemented so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1 in the SQW structure of the active layer330. Even in such a case, as illustrated inFIG.7B, high quantum efficiency can be achieved with respect to the micro LED300. In particular, quantum efficiency of the micro LED300can be significantly improved in a low current region.

According to various embodiments, as illustrated inFIG.8, quantum efficiency of the micro LED300in a low current region may be higher than quantum efficiency of the existing micro LED (not illustrated) in a low current region. In this case, each of the micro LED300and the existing micro LED may be implemented to have an asymmetrical structure. The existing micro LED may include an active layer (not illustrated) having an MQW structure. That is, since the active layer330having the SQW structure is included, quantum efficiency of the micro LED300can be significantly improved in a low current region.

According to various embodiments, as illustrated inFIG.9, an increase in the density of holes within the active layer330can be checked by analyzing a mechanism for quantum efficiency of the micro LED300through a carrier density distribution within the active layer330of the micro LED300. That is, quantum efficiency of the micro LED300can be improved according to which the SQW structure of the active layer330causes an increase in the density of holes within the active layer330.

The micro LED300according to various embodiments may be fabricated according to a semiconductor fabrication scheme.

First, the first conductive type semiconductor layer310may be prepared. For example, the first conductive type semiconductor layer310may include the first support layer311and the first barrier layer313. In this case, the first support layer311may be disposed, and the first barrier layer313may be stacked on the first support layer311in the one axis X and come into contact with the active layer330. According to one embodiment, the first conductive type semiconductor layer310may be a p type semiconductor layer. For example, in the first conductive type semiconductor layer310, the first support layer311may be composed of a gallium-phosphor compound (GaP), and the first barrier layer313may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP). According to another embodiment, the first conductive type semiconductor layer310may be an n type semiconductor layer. For example, in the first conductive type semiconductor layer310, the first support layer311may be composed of a gallium-arsenic compound (GaAs), and the first barrier layer313may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP).

Next, the active layer330may be stacked on the first conductive type semiconductor layer310. For example, the active layer330may be composed of an indium-gallium-phosphor compound (InGaP).

Next, the second conductive type semiconductor layer320may be stacked on the active layer330. The second conductive type semiconductor layer320may include the second barrier layer323and the second support layer325. In this case, the second barrier layer323may be disposed on the active layer330and come into contact with the active layer330, and the second support layer325may be stacked on the second barrier layer323in the one axis X. According to one embodiment, the second conductive type semiconductor layer320may be an n type semiconductor layer. For example, in the second conductive type semiconductor layer320, the second barrier layer323may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP), and the second support layer325may be composed of a gallium-arsenic compound (GaAs). According to another embodiment, the second conductive type semiconductor layer320may be a p type semiconductor layer. For example, in the second conductive type semiconductor layer320, the second barrier layer323may be composed of at least any one of an aluminum-gallium-indium-phosphor compound (AlGaInP) or an aluminum-indium-phosphor compound (AlInP), and the second support layer325may be composed of a gallium-phosphor compound (GaP).

According to various embodiments, as illustrated inFIG.4, the active layer330may have the SQW structure. In the SQW structure, the conduction band offset ΔECfor absorbing electrons from any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320may be defined. Furthermore, in the SQW structure, the valence band offset ΔEVfor absorbing holes from any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320may be defined. In this case, the SQW structure of the active layer330may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1.

According to one embodiment, the first conductive type semiconductor layer310may be a p type semiconductor layer, and the second conductive type semiconductor layer320may be an n type semiconductor layer. In such a case, the first conductive type semiconductor layer310may be configured to inject holes into the active layer330, and the second conductive type semiconductor layer320may be configured to inject electrons into the active layer330. Furthermore, in the SQW structure of the active layer330, a conduction band offset ΔECof the second conductive type semiconductor layer320and a valence band offset ΔEVof the first conductive type semiconductor layer310may be defined. In this case, the SQW structure of the active layer330may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1.

According to another embodiment, the first conductive type semiconductor layer310may be an n type semiconductor layer, and the second conductive type semiconductor layer320may be a p type semiconductor layer. In such a case, the first conductive type semiconductor layer310may be configured to inject electrons into the active layer330, and the second conductive type semiconductor layer320may be configured to inject holes into the active layer330. Furthermore, in the SQW structure of the active layer330, a conduction band offset ΔECof the first conductive type semiconductor layer310and a valence band offset ΔEVof the second conductive type semiconductor layer320may be defined. In this case, the SQW structure of the active layer330may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1.

According to various embodiments, efficiency of the micro LED120,130,140,220,230,240,300can be improved by forming the active layer330of the micro LED120,130,140,220,230,240,300as the SQW structure. In this case, since the SQW structure of the active layer330is formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECand the valence band offset ΔEVbecomes greater than 0 and less than 1, efficiency of the micro LED120,130,140,220,230,240,300in a low current region can be improved. Accordingly, lower power of the micro LED120,130,140,220,230,240,300can also be implemented.

The micro LED120,130,140,220,230,240,300according to various embodiments may include the first conductive type semiconductor layer310, the second conductive type semiconductor layer320, and the active layer330disposed between the first conductive type semiconductor layer310and the second conductive type semiconductor layer320and having the SQW structure.

According to various embodiments, the SQW structure may be formed so that the ratio ΔEC/ΔEVof the conduction band offset ΔECof any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320and the valence band offset ΔEVof the other of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320becomes greater than 0 and less than 1.

According to various embodiments, the active layer330may be disposed between the first conductive type semiconductor layer310and the second conductive type semiconductor layer320, on the first conductive type semiconductor layer310.

According to one embodiment, the first conductive type semiconductor layer310may inject holes into the active layer330, and the second conductive type semiconductor layer320may inject electrons into the active layer330.

According to one embodiment, the SQW structure may be formed so that the ratio ΔEC/ΔEVof a conduction band offset ΔECof the second conductive type semiconductor layer320and a valence band offset ΔEVof the first conductive type semiconductor layer310becomes greater than 0 and less than 1.

According to another embodiment, the first conductive type semiconductor layer310may inject electrons into the active layer330, and the second conductive type semiconductor layer320may inject holes into the active layer330.

According to another embodiment, the SQW structure may be formed so that the ratio ΔEC/ΔEVof a conduction band offset ΔECof the first conductive type semiconductor layer310and a valence band offset ΔEVof the second conductive type semiconductor layer320becomes greater than 0 and less than 1.

According to various embodiments, the active layer330may generate light having a predetermined wavelength by a combination of electrons and holes injected from the first conductive type semiconductor layer310and the second conductive type semiconductor layer320, respectively.

According to various embodiments, the active layer330may be composed of an indium-gallium-phosphor compound (InGaP).

According to one embodiment, the micro LED120,130,140,220,230,240,300may have a symmetrical structure according to which the first conductive type semiconductor layer310and the second conductive type semiconductor layer320are composed of the same material.

According to another embodiment, the micro LED120,130,140,220,230,240,300may have an asymmetrical structure according to which the first conductive type semiconductor layer310and the second conductive type semiconductor layer320are composed of different materials.

A method of fabricating the micro LED120,130,140,220,230,240,300according to various embodiments may include the steps of preparing the first conductive type semiconductor layer310, stacking, on the first conductive type semiconductor layer310, the active layer330having the SQW structure, and stacking the second conductive type semiconductor layer320on the active layer330.

According to various embodiments, the SQW structure may be formed so that the ratio ΔEC/ΔEVof a conduction band offset ΔECof any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320and a valence band offset ΔEVof the other of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320becomes greater than 0 and less than 1.

According to one embodiment, when the micro LED120,130,140,220,230,240,300operates, the first conductive type semiconductor layer310may inject holes into the active layer330, and the second conductive type semiconductor layer320may inject electrons into the active layer330.

According to one embodiment, the SQW structure may be formed so that the ratio ΔEC/ΔEVof a conduction band offset ΔECof the second conductive type semiconductor layer320and a valence band offset ΔEVof the first conductive type semiconductor layer310becomes greater than 0 and less than 1.

According to another embodiment, when the micro LED120,130,140,220,230,240,300operates, the first conductive type semiconductor layer310may inject electrons into the active layer330, and the second conductive type semiconductor layer320may inject holes into the active layer330.

According to another embodiment, the SQW structure may be formed so that the ratio ΔEC/ΔEVof a conduction band offset ΔECof the first conductive type semiconductor layer310and a valence band offset ΔEVof the second conductive type semiconductor layer320becomes greater than 0 and less than 1.

According to various embodiments, the active layer330may generate light having a predetermined wavelength by a combination of electrons and holes injected from the first conductive type semiconductor layer310and the second conductive type semiconductor layer320, respectively.

According to various embodiments, the active layer330may be composed of an indium-gallium-phosphor compound (InGaP).

According to one embodiment, the micro LED120,130,140,220,230,240,300may have a symmetrical structure according to which the first conductive type semiconductor layer310and the second conductive type semiconductor layer320are composed of the same material.

According to another embodiment, the micro LED120,130,140,220,230,240,300may have an asymmetrical structure according to which the first conductive type semiconductor layer310and the second conductive type semiconductor layer320are composed of different materials.

The display100,200according to various embodiments may include the IC device110,210in which the driving circuit is wired, and the plurality of micro LEDs120,130,140,220,230,240, and300mounted on the one surface S1, S2of the IC device110,210.

According to various embodiments, each of the micro LEDs120,130,140,220,230,240, and300may include the first conductive type semiconductor layer310, the second conductive type semiconductor layer320, and the active layer330disposed between the first conductive type semiconductor layer310and the second conductive type semiconductor layer320and having the SQW structure.

According to various embodiments, the SQW structure may be formed so that the ratio ΔEC/ΔEVof a conduction band offset ΔECof any one of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320and a valence band offset ΔEVof the other of the first conductive type semiconductor layer310or the second conductive type semiconductor layer320becomes greater than 0 and less than 1.

According to various embodiments, the micro LEDs120,130,140,220,230,240, and300may generate lights having different wavelengths.

According to one embodiment, each of the micro LEDs120,130,140,220,230,240, and300may be attached to the one surface S1, S2of the IC device110,210.

According to another embodiment, each of the micro LEDs120,130,140,220,230,240, and300may be stacked on the one surface S1, S2of the IC device110,210.

Various embodiments of this document and the terms used in the embodiments are not intended to limit the technology described in this document to a specific embodiment, but should be construed as including various changes, equivalents and/or alternatives of a corresponding embodiment. Regarding the description of the drawings, similar reference numerals may be used in similar elements. An expression of the singular number may include an expression of the plural number unless clearly defined otherwise in the context. In this document, an expression, such as “A or B”, “at least one of A or/and B”, “A, B or C” or “at least one of A, B and/or C”, may include all of possible combinations of listed items together. Expressions, such as “a first,” “a second,” “the first” and “the second”, may modify corresponding elements regardless of the sequence and/or importance, and are used to only distinguish one element from the other element and do not limit corresponding elements. When it is described that one (e.g., first) element is “(operatively or communicatively) connected to” or “coupled with” the other (e.g., second) element, one element may be directly connected to the other element or may be connected to the other element through another element (e.g., third element).

According to various embodiments, each of elements (e.g., module or program) may include a single entity or a plurality of entities. According to various embodiments, one or more of the aforementioned elements or operations may be omitted or one or more other elements or operations may be added. Alternatively or additionally, a plurality of elements (e.g., modules or programs) may be integrated into a single element. In such a case, the integrated element may perform one or more functions of each of the plurality of elements identically with or similarly to a function performed by a corresponding element of the plurality of elements before they are integrated. According to various embodiments, operations performed by a module, a program or other elements may be executed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be executed in different order or may be omitted, or one or more operations may be added.

As described above, although the embodiments have been described in connection with the limited embodiments and the drawings, those skilled in the art may modify and change the embodiments in various ways from the description. For example, proper results may be achieved although the aforementioned descriptions are performed in order different from that of the described method and/or the aforementioned elements, such as the system, configuration, device, and circuit, are coupled or combined in a form different from that of the described method or replaced or substituted with other elements or equivalents.

Accordingly, other implementations, other embodiments, and the equivalents of the claims fall within the scope of the claims.