A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed.

BACKGROUND

1. Field of Invention

One or more embodiments of the invention relate generally to the field of non-volatile memory devices and more particularly, to resistive random access memory devices.

2. Description of Related Art

Computer systems are generally employed in numerous configurations to provide a variety of computing functions. Processing speeds, system flexibility, and size constraints are typically considered by design engineers tasked with developing computer systems and system components. Computer systems generally include a plurality of memory devices which may be used to store programs and data and which may be accessible to other system components such as processors or peripheral devices. Such memory devices may include volatile and non-volatile memory devices.

Non-volatile memory devices may include read-only memory (ROM), magnetic storage, flash memory, etc. One type of non-volatile memory is resistive random access memory (RRAM). Various types of RRAM may be used, such as unipolar switching RRAM and bipolar switching RRAM. However, each type of RRAM may have different applications and some types of RRAM may be unusable in certain memory architectures.

DETAILED DESCRIPTION

As discussed in further detail below, embodiments of the present invention include a bipolar switching resistive random access memory (RRAM) cell having built-in “on” state rectifying current-voltage (IV) characteristics such that the memory cell may be used without an external selection device. As used herein, the term “built-in” refers to characteristics (or devices) internal to the bipolar switching resistive random access memory (RRAM) cell, as opposed to characteristics provided by a device external to the memory cell. The bipolar switching RRAM cell may be used in smaller memory architectures, such as 4F2 cross-point architectures. In one embodiment, the bipolar switching RRAM cell may include a metal/solid electrolyte/semiconductor stack. In other embodiments, the bipolar switching RRAM cell may include a metal/solid electrolyte/insulator/electrode stack. In either embodiment, a metal filament may be formed in the solid electrolyte to form a device having rectifying IV characteristics.

FIG. 1is a two-dimensional schematic diagram of a portion of a memory array10having memory cells12constructed in accordance with embodiments of the present invention. The memory array10includes access lines (e.g., wordlines) AL(0)-AL(M) and intersecting data lines (e.g., bitlines) DL(0)-DL(N).

The memory array10includes a memory cell12located at each intersection of an access line AL and a data line DL. The memory cells12may include resistive memory elements14that may be formed in accordance with the embodiments discussed below inFIGS. 2A and 2Band5A and5B. Each memory element14may be coupled to a data line, and the data lines are connected to a data line drive16(e.g., one or more data line drivers/sense amplifiers). A row of the memory cells12include those memory elements14whose terminals are commonly coupled (e.g., to a given access line AL). The access lines may be coupled to an access line driver18. Thus, to activate a row of memory cells12, one or more of the access lines may be activated via the access line driver18, and the corresponding data lines may be read.

In certain embodiments, the memory array10may be constructed using a 4F2 cross-point architecture, such that each data line and adjacent space occupies a width of 2F and each access line and adjacent space occupies a width of 2F, wherein F is the lithographic-resolution limit (e.g., the photolithographic-resolution limit or minimum feature size achievable). In other embodiments, the memory array10may be constructed using an 8F2, 6F2, or other architecture. In such a 4F2 cross-point architecture, the digit line and the access line may be formed perpendicular to each other in a “cross-point” arrangement. However, a conventional 4F2 resistive random access memory array requires a diode selection device to prevent cross-talk between adjacent memory cells and rows of memory cells, thus limiting the application of 4F2 architectures to unipolar memory cells having such diode selection devices.

FIGS. 2A and 2Bdepict cross-sections of a bipolar switching memory cell20having built-in “on” state rectifying IV characteristics in accordance with an embodiment of the present invention.FIG. 2Adepicts the memory cell20in an “off” state andFIG. 2Bdepicts the memory cell20in an “on” state. The bipolar switching memory cell20may be formed from a stack having a metal22, a solid electrolyte24, and a semiconductor26.

As shown inFIG. 2A, in the “off” state the memory cell20does not have any conducting element in the solid electrolyte24. To switch the memory cell20to the “on” state, a positive voltage may be applied to the metal22. The minimum required positive voltage to switch the memory cell20may be referred to as “Vset.” A conducting filament28may be formed through a reduction-oxidation (redox) reaction, in the solid electrolyte24, from metal ions of the metal22. The filament28makes contact with the semiconductor26, forming a Schottky diode30with the semiconductor26. As explained below, in the “on” state ofFIG. 2B, the Schottky diode30provides the memory cell20with rectifying IV characteristics, enabling the use of such cells20in a 4F2 architecture without external selection devices for the cells. In some embodiments, the filament28may be a metal filament or may be a conduction path with low resistance having metallic behavior.

To switch the memory cell20to the “off” state shown inFIG. 2A, a negative voltage may be applied on the metal22. The applied negative voltage is above the redox voltage threshold (referred to as Vreset) of the filament28. At this threshold voltage, the conducting filament28may dissolve through the redox reaction, returning the solid electrolyte24to an insulating state.

In some embodiments, the metal22may include Ag, Cu, Ni, Zn, or any other suitable metal, or a material that provides an ion source to form the conductive filament28. The solid electrolyte24may include a doped chalcogenide glass of formula AxBy, where B is selected from among S, Se and Te and mixtures thereof, and where A includes at least one element from Group iii-A (B, Al, Ga, In, Tl), group IV-A (C, Si, Ge, Sn, Pb), Group V-A (N, P, As, Sb, Bi), or group VII-A (F, Cl, Br, I, At) of the periodic table and with the dopant being selected from among the noble metals and transition metals including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni. For example, such solid electrolytes may include AsxS1-x—Ag, GexSe1-x—Ag, GexS1-x—Ag, AsxS1-x—Cu, GexSe1-x—Cu, GexS1-x—Cu, GexTe1-x—Cu, SnxSe, wherein x=0.1 to 0.5, or other doped chalocogenide glasses with Ag, Cu, Zn or with modifiers of halogens, halides or hydrogen (note: x=0.1 to 0.5). In other embodiments, the solid electrolyte24may include undoped or doped oxides with such as MoOx, TaOx, ZrOx, HfOx, TiOx, MgOx, NbOx, AlOx, GdOx, NiOx, GeO2, As2O3, Ag2O, Cu(1,2)O, WOxor other suitable transition metal oxides. In other embodiments, the solid electrolyte24may include any suitable rare earth metal oxide, SiOx, high resistivity amorphous or crystalline Si, ZnxCd(1-x)S, amorphous C, CuC, or Cu2S. Additionally, the semiconductor26may include GaP, Ge, GaSe, InP, GaAs, InGaP, ZnTe, Si, Ge, ZnS, SiC, GaTe, InGaAs, SrTiO3 (STO), or PrCaMnO (PCMO), In other embodiments, the semiconductor26may include a semiconductor silicide such as Ca3Si4, CrSix, RU2Si3, or any suitable silicide.

Additionally, various combinations of the metal22and semiconductor26may provide for different barrier heights of the Schottky diode28. Table 1 lists different combinations of the metal22and semiconductor26, and the corresponding barrier height of the Schottky diode28:

FIG. 3depicts an IV graph32illustrating the IV characteristics of the memory cell20in accordance with an embodiment of the present invention. The IV graph32illustrates absolute voltage (V) on the x-axis and current (I) on the y-axis. As shown inFIG. 3, a first IV curve34depicts the IV characteristics for switching the memory cell20from the “off” state shown inFIG. 2Ato the “on” state depicted inFIG. 2B.FIG. 3also includes a second IV curve36depicting the rectifying IV characteristics for the memory cell20in the “on” state shown inFIG. 2B

As shown in the first IV curve34, the memory cell20has no conductivity and no current until Vset is reached (illustrated at point38). Once the applied positive voltage reaches Vset, the filament28forms and current flows in the memory cell20(illustrated by region40of the IV curve34).

As shown in the second IV curve36, in the “on” state the memory cell20has rectifying IV characteristics. Thus, to switch the memory cell20from the “on” state to the “off” state, a negative voltage sufficient to overcome the redox threshold voltage (Vreset) is applied to the memory cell20. As the applied negative voltage increases, the redox reaction dissolves the filament28and returns the memory cell20to the “off” state (as shown by region44of the IV curve36). As also shown inFIG. 3, Vt (illustrated by point42) is the threshold voltage for the rectifying behavior to allow current to flow in the memory cell20.

FIG. 4is a two-dimensional schematic diagram of a portion of a memory array50having bipolar switching memory cells20constructed in accordance with embodiments of the present invention. As shown inFIG. 4, the memory cells20do not include any external selection device. Operations of the memory array50will be described with reference to a selected memory cell52. As described above, to switch the memory cell52to an “on” state, a voltage (V1) larger than Vset may be applied to the selected memory cell52, such by biasing the digitline DL(1). The adjacent digitlines DL(0) and DL(2) may be biased to a lesser voltage V2. Thus, the voltage V2may be applied to the memory cells54adjacent the selected memory52. In such an operation, the access line AL(1) may held at 0 volts, and access lines AL(0) and AL(2) may be biased to V2.

The voltage V2may be smaller than both Vt (the redox threshold voltage) and Vset (the switch “on” voltage) for the memory cells20. Thus, due to the rectifying IV characteristics of the “on” state of the memory cells20and the high resistance of the “off” state of the memory cells20, the adjacent memory cells54experience minimal or no disturb and minimal leakage current during the operation on the selected memory cell52.

When switching the selected memory cell52to the “off” state, a negative voltage above the redox threshold voltage (Vreset) may be applied to the selected memory cell52. Here again, the adjacent digit lines may be biased to a voltage V2that is less than the threshold Vt, minimizing or preventing any disturb and minimizing leakage current in the adjacent memory cells54. Finally, when reading the selected memory cell52, the voltage V1may be larger than the rectifying threshold voltage (Vt) and smaller than Vset. Again, the adjacent digit lines DL(0) and DL(2) may be biased to a voltage V2smaller than Vt, minimizing or preventing any disturb and minimizing leakage current in the adjacent memory cells54.

In some embodiments, a memory cell may be formed from a metal/solid electrolyte/insulator/electrode stack.FIGS. 5A and 5Bdepict a bipolar switching memory cell60having built-in “on” state rectifying IV characteristics in accordance with another embodiment of the present invention.FIG. 5Adepicts the memory cell60in an “off” state andFIG. 5Bdepicts the memory cell60in an “on” state. The bipolar switching memory cell60may be formed from a stack having a metal62, a solid electrolyte64, insulator tunnel barrier66, and an electrode68. The insulator tunnel barrier64may include one or multiple tunnel barriers.

As shown inFIG. 5A, in the “off” state the memory cell60does not have any conducting element in the solid electrolyte64. To switch the memory cell60to the “on” state, a positive voltage may be applied to the metal62. As noted above, the minimum positive voltage to switch the memory cell60“on” may be referred to as “Vset.” A conducting metal filament70may be formed, through a redox reaction, in the solid electrolyte64from metal ions of the metal62. The metal filament70makes contact with the insulator tunnel barrier66, forming a metal-insulator-metal (MIM) device72with the insulator tunnel barrier66and the electrode68. As explained below, the MIM device72provides the memory cell60with rectifying IV characteristics, similar to the Schottky diode described above inFIGS. 2A and 2B.

As mentioned above, in some embodiments the memory cell60may include multiple insulating tunnel barriers66. In such an embodiment, when switched to the “on” state, the metal filament70may form a metal-insulator-insulator-metal (MIIM) device having a first insulator and second insulator between the metal62and electrode68. In other embodiments, the memory cell60may include an insulating crested barrier, such that the metal filament70may form a metal-crested barrier-metal electrode device.

To switch the memory cell60to the “off” state shown inFIG. 5A, a negative voltage may be applied to the metal62. The negative voltage is applied above the redox voltage threshold (referred to as Vreset) for the metal filament70. The conducting metal filament70may dissolve via the redox reaction, returning the solid electrolyte to an insulator between the metal62and the electrode68.

In some embodiments, the metal62may include Ag, Cu, Ni, Zn, or any other suitable metal or a material that provides an ion source to form the conductive filament28. The solid electrolyte64may include a doped chalcogenide glass of formula AxBy, where B is selected from among S, Se and Te and mixtures thereof, and where A includes at least one element from Group iii-A (B, Al, Ga, In, Tl), group IV-A (C, Si, Ge, Sn, Pb), Group V-A (N, P, As, Sb, Bi), or group VII-A (F, Cl, Br, I, At) of the periodic table and with the dopant being selected from among the noble metals and transition metals including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni. For example, such solid electrolytes may include AsxS1-x—Ag, GexSe1-x—Ag, GexS1-x—Ag, AsxS1-x—Cu, GexSe1-x—Cu, GexS1-x—Cu, GexTe1-x—Cu, SnxSe, wherein x=0.1 to 0.5, or other doped chalocogenide glasses with Ag, Cu, Zn or with modifiers of halogens, halides or hydrogen (note: x=0.1 to 0.5). In other embodiments, the solid electrolyte64. In other embodiments, the solid electrolyte64may include undoped or doped oxides with such as MoOx, TaOx, ZrOx, HfOx, TiOx, MgOx, NbOx, AlOx, GdOx, NiOx, GeO2, As2O3, Ag2O, Cu(1,2)O, WOxor other suitable transition metal oxides. In other embodiments, the solid electrolyte24may include any suitable rare earth metal oxide, SiOx, high resistivity amorphous or crystalline Si, ZnxCd(1-x)S, amorphous C, CuC, or Cu2S. Additionally, in some embodiments the semiconductor26may include GaP, Ge, GaSe, InP, GaAs, InGaP, ZnTe, Si, Ge, ZnS, SiC, GaTe, InGaAs, SrTiO3 (STO), or PrCaMnO (PCMO). The tunnel barrier66may include SiO2, Si3N4, HfO2, ZrO2, or SrTiOxand may have a thickness of about 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or up to 10 nm.

In some embodiments, the electrode may be an oxidizable electrode and may include Ag, AgI, AgS, AgxSe, AgxTe, AgyI, CuI2, CuO, CuS, CuSe, CuTe, CuAsTe and CuAsSe, Cu2SSe, Cu2SeS, Cu2TeS, and Cu2TeSe, or Cu2CdSnSe4. The electrode may be of the formula Ax(MB2)1-x, where A is Cu or Ag or Zn; B is S or Se; and M is a transition metal such as Ta, V or Ti. Additionally, in some embodiments, the electrode may be ZnS, ZnSe, ZeTe or suitable Zn compounds.

FIG. 6depicts an IV graph76illustrating the IV characteristics of the memory cell60in accordance with an embodiment of the present invention. The IV graph76illustrates voltage (V) on the x-axis and current (I) on the y-axis. As shown inFIG. 6, a first IV curve78depicts the IV characteristics for switching the memory cell60from the “off” state shown inFIG. 5Ato the “on” state depicted inFIG. 5B.FIG. 6also includes a second IV curve80depicting the rectifying IV characteristics for the memory cell60in the “on” state shown inFIG. 2B. The second IV curve80depicts a first threshold voltage (Vt1) for the metal-insulator-metal (MIM) device72and a second threshold voltage (Vt2) for the metal-insulating tunnel barrier-electrode structure of the memory cell60.

As shown in the first IV curve78, the memory cell60has no conductivity and no current until Vset is applied (illustrated at point82). Once the applied positive voltage reaches Vset, the metal filament70forms and current flows in the memory cell60(illustrated by region84of the IV curve78).

As shown in the second IV curve80, in the “on” state the memory cell60exhibits rectifying IV characteristics of the MIM device72. To switch the memory cell60from the “on” state to the “off” state, a negative voltage sufficient to overcome the redox threshold voltage (Vreset) is applied to the memory cell60(illustrated by point92). As the applied negative voltage increases, the redox reaction dissolves the metal filament70and returns the memory cell60to the “off” state (as shown by region88of the IV curve36). Additionally, the memory cell60may have a second threshold voltage (Vt2) that corresponds to the current conduction for the metal/insulating tunnel barrier/metal electrode structure (illustrated by point90). During switching of the memory cell60to the “off” state, the applied negative voltage may be greater than the second threshold voltage (Vt2) in magnitude.

FIG. 7is a two-dimensional schematic diagram of a portion of a memory array96having memory cells60constructed in accordance with embodiments of the present invention. The operation of the memory array96may be similar to the operation of the memory array50described above inFIG. 4. For example, the MIM device72may provide similar rectifying IV characteristics as the Schottky diode30of the memory cell20depicted inFIGS. 2A and 2B. As described above, to switch a selected memory cell98to an “on” state, a voltage (V1) may be larger than Vset may be applied to the selected memory cell98, such as by biasing the digit line DL(1). The adjacent digit lines DL(0) and DL(2) may be biased to a lesser voltage V2, and such voltage is applied to the adjacent memory cells100. The voltage V2is smaller than both Vt1(the threshold voltage for the MIM device72) and Vset (the switch “on” voltage) for the memory cells60. Thus, the adjacent memory cells100may experience minimal or no disturb and may produce minimal leakage current.

When switching the selected memory cell98to the “off” state, a negative voltage above the redox threshold voltage (Vreset) may be applied to the selected memory cell98. Again, in such an operation the adjacent digitlines may be biased to a voltage V2that is less than the threshold voltage Vt1and the threshold voltage Vt2, minimizing or preventing any disturb and minimizing leakage current of the adjacent memory cells100. Similarly, a read operation of the selected memory cell98may result in minimal or no disturb and minimal leakage current in the manner described above.

FIG. 8is a block diagram that depicts a processor-based system, generally designated by reference numeral102, having a non-volatile memory104constructed in accordance one or more of the embodiments discussed above. For example, the system102may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, etc. In a typical processor-based system, one or more processors106, such as a microprocessor, control the processing of system functions and requests in the system102.

The system102typically includes a number of components. For example, the system102includes a power supply108. For instance, if the system102is a portable system, the power supply108may advantageously include permanent batteries, replaceable batteries, and/or rechargeable batteries. The power supply108may also include an AC adapter, so the system102may be plugged into a wall outlet, for instance. The power supply108may also include a DC adapter such that the system102may be plugged into a vehicle cigarette lighter, for instance.

Various other devices may be coupled to the processor106depending on the functions that the system102performs. For instance, an input device110may be coupled to the processor106. The user interface110may include buttons, switches, a keyboard, a light pen, a mouse, and/or a voice recognition system, for instance. A display112may also be coupled to the processor106. The display112may include an LCD display, a CRT, LEDs, and/or an audio display, for example. Furthermore, an RF sub-system/baseband processor114may also be coupled to the processor106. The RF sub-system/baseband processor114may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). One or more communication ports116may also be coupled to the processor106. The communication port116may be adapted to be coupled to one or more peripheral devices118such as a modem, a printer, a computer, or to a network, such as a local area network, remote area network, intranet, or the Internet, for instance.

The processor106generally controls the system102by implementing software programs stored in the memory. The memory is operably coupled to the processor106to store and facilitate execution of various programs. For instance, the processor106may be coupled to a volatile memory120which may include Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM).

As mentioned above, the processor106may also be coupled to the non-volatile memory104. The non-volatile memory104may include RRAM constructed in accordance with the embodiments depicted above inFIGS. 2A and 2Band/orFIGS. 5A and 5B. Additionally, the non-volatile memory104may include a read-only memory (ROM), such as an EPROM, and/or res memory to be used in conjunction with the volatile memory. Additionally, the non-volatile memory104may include magnetic storage such as a tape drives, hard disks and the like.