Semiconductor device and fabrication method of semiconductor device

A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and fabrication method thereof.

2. Description of the Related Art

For electric power converting apparatuses used in electric vehicles (EV), etc., the most widely used insulated gate semiconductor devices have lower power consumption and are easily driven in a voltage-controlled manner. Insulated gate semiconductor devices are known as an insulated gate field effect transistor (metal oxide semiconductor field effect transistor (MOSFET)), an insulated gate bipolar transistor (IGBT), etc.

In the present description and the accompanying drawings, “n” and “p” prefixes of layers and regions indicate that the majority of carriers is an electron and a hole, respectively. “+” and “−” appended to an “n” or a “p” indicate that the impurity concentration is higher and lower, respectively, than layers and regions without “+” and “−”.

FIG. 17is a cross-sectional view of a conventional semiconductor device. For example, MOSFET of a trench gate structure will be described as a conventional insulated gate semiconductor device. A p-type base region102is disposed on a surface of a semiconductor substrate forming an n−-type drift region101. A trench103is disposed penetrating the base region102and reaching the drift region101. A gate electrode105is disposed inside the trench103via a gate insulating film104. An n+-type source region106is selectively disposed on a surface layer of the base region102so as to be in contact with the trench103. A source electrode108contacts the base region102and the source region106. The source electrode108is electrically insulated from the gate electrode105by an interlayer insulating film107. A drain electrode109is disposed on the backside of the semiconductor substrate.

Such a semiconductor device operates as follows. The source electrode108is in a state of being connected to the ground or of having a negative voltage applied thereto. The drain electrode109is in a state of having a positive voltage applied thereto. If a voltage lower than a threshold value is applied to the gate electrode105, no current flows between the source and the drain since a p-n junction, made up of the base region102and the drift region101, is inversely-biased. Therefore, the semiconductor device remains in the off-state. On the other hand, if a voltage exceeding the threshold value is applied to the gate electrode105, in the p-type base region102, a region in contact with the trench103beneath the source region106is inverted to become an n-type channel region. This causes an electron leaving the source electrode108to travel to the drain electrode109through an n-type region consisting of the channel region and the drift region101and current flows between the source and the drain, whereby the semiconductor device is turned on.

As such a semiconductor device, an apparatus is proposed that is configured as an insulated gate field effect transistor having a semiconductor substrate of a first conductivity type forming a drain region; a channel region of a second conductivity formed on a principal surface of the semiconductor substrate; a source region formed in the channel region; a gate insulating film and a gate electrode disposed across the source region and the drain region; and a source electrode in contact with a window surrounded by the gate electrode, where in the channel region of the window surrounded by the gate electrode, a recess portion is formed deeper than a channel region surface immediately under the gate insulating film, having a width reaching at least immediately under an end of the gate electrode. A back gate region is introduced into a bottom side region of the recess portion, and a source region of a silicide layer or a metal layer is disposed in the recess portion such that only the channel region and the back gate region are in contact with an inner surface of the source region (see, e.g., Japanese Laid-open Patent Publication No. 3197054).

A method of fabricating the conventional insulated gate semiconductor device depicted inFIG. 17will be described. The p-type base region102is first formed on the surface of the semiconductor substrate forming the n−-type drift region101. The trench103is then formed that penetrates the base region102and reaches the drift region101. The gate electrode105is formed inside the trench103via the gate insulating film104. The n+-type source region106is selectively formed on the surface layer of the base region102so as to be in contact with the trench103. The interlayer insulating film107, formed of a film such as phosphosilicate glass (PSG), is selectively formed on the surface of the semiconductor substrate to cover a surface of the gate electrode105. The source electrode108is formed that contacts the base region102and the source region106exposed on the surface of the semiconductor substrate. The drain electrode109in contact with the drift region101is formed on the backside of the semiconductor substrate. This completes the MOSFET of the trench gate structure depicted inFIG. 17.

However, in conventional insulated gate semiconductor devices such as MOSFET and IGBT, a parasitic element such as a parasitic bipolar transistor and a parasitic thyristor are incidentally formed in addition to original constituent elements of the semiconductor devices. Such a parasitic element is likely to operate at abnormal times such as when an overcurrent flows in the semiconductor devices. It is problematic that the operation of the parasitic element adversely affects the operation of the original semiconductor devices.

For example, in the semiconductor device depicted inFIG. 17, a parasitic bipolar transistor121is formed that is made up of the drift region101, the base region102, and the source region106. If an abnormal current such as overcurrent flows in the semiconductor device and a voltage drop in a channel region exceeds a forward voltage of a silicon diode, which is 0.7 V (because a built-in voltage of the diode is 0.6 V), the parasitic bipolar transistor121operates causing latch-up and short circuit. The operation of the parasitic bipolar transistor121cannot be controlled by controlling the voltage applied to the gate electrode105. Therefore, destruction may occur if the semiconductor device exceeds a safe operation range.

A semiconductor device that avoids such a problem is known where size reduction is achieved by forming the source region106to have a narrower width, for example. However, the current density in a semiconductor device fabricated in this way is increased by the size reduction and the parasitic bipolar transistor121becomes more likely to operate. Another approach is known where the base region102of a semiconductor device is formed having a higher impurity concentration. However, a semiconductor device fabricated in this way becomes unable to sufficiently invert the channel region in the on-state. Therefore, the on-voltage problematically increases. Such a problem also occurs in IGBT of the trench gate structure.

To solve the problems of the conventional technologies described above, an object of the present invention is to provide a semiconductor device and fabrication method thereof capable of controlling the influence of a parasitic element. Another object of the present invention is to provide a semiconductor device and fabrication method thereof capable of preventing the on-voltage from increasing.

SUMMARY OF THE INVENTION

It is an object of the present invention to at least solve the above problems in the conventional technologies.

According to one aspect of the present invention, a semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the accompanying drawings, exemplary embodiments according to the present invention are explained in detail below. With respect to the embodiments and drawings, like components are given the same reference numerals and redundant explanations are omitted.

FIG. 1is a cross-sectional view of a semiconductor device according to the embodiment. The semiconductor device depicted inFIG. 1has a p-type (second-conductivity-type) base region2disposed on a surface of a semiconductor substrate forming an n−-type (first-conductivity-type) drift region1. The base region2has an impurity concentration that is higher than that of the drift region1. On a surface of the semiconductor substrate, a trench3that penetrates the base region2to reach the drift region1is disposed. In the trench3, a gate electrode5is disposed via a gate insulating film4. A surface of the gate electrode5is covered by an interlayer insulating film7. The drift region1corresponds to a first semiconductor region. The base region2corresponds to a second semiconductor region.

A first recess portion6is selectively disposed in the surface layer of the base region2. The base region2has an uneven surface shape made up of the first recess portion6and a projecting portion without the first recess portion6. The first recess portion6is in contact with the trench3. The channel region11is a region of the base region2in contact with the trench3under the first recess portion6. The bottom surface of the first recess portion6is disposed deeper from the substrate surface than an interface between the gate electrode5and the interlayer insulating film7disposed on the upper end of the gate electrode5(hereinafter, “upper end of the gate electrode5”). The reason is as follows. As described later, a source electrode8is embedded inside the first recess portion6. Therefore, the bottom surface of the first recess portion6is an interface between the source electrode8and the base region2. If the bottom surface of the first recess portion6is positioned shallower from the substrate surface than the upper end of the gate electrode5, the source electrode8disposed in the first recess portion6is not formed adjacently to the gate electrode5via the gate insulating film4. As a result, the semiconductor device does not operate.

Preferably, the first recess portion6is disposed at a depth equal to or greater than 0.05 μm and equal to or less than 1 μm from the upper end of the gate electrode5. The reason is as follows. If a first distance d is a depth from the upper end of the gate electrode5to the bottom surface of the first recess portion6and is less than 0.05 μm, the source electrode8disposed in the first recess potion6is located adjacent to the gate electrode5via the gate insulating film4at a shorter distance. Therefore, the operation of the semiconductor device becomes unstable. On the other hand, if the first distance d is greater than 1 μm, the protruding portion of the base region2is no longer formed since the width of the first recess portion6is broadened corresponding to the depth of the first recess portion6. This is attributable to a process of forming the first recess portion6.

The source electrode8is in contact with the protruding portion of the base region2and is embedded inside the first recess portion6. Therefore, the source electrode8is disposed to cover the base region2along the unevenness formed on the surface of the base region2. The source electrode8is electrically insulated from the gate electrode5by the interlayer insulating film7. Although not depicted, a p+-type contact region having an impurity concentration higher than that of the base region2may be disposed in a surface layer of the protruding portion of the base region2so as to be in contact with the first recess portion6. The source electrode8corresponds to a second electrode. A drain electrode9is disposed on the backside of the semiconductor substrate.

A method of fabricating such a semiconductor device will be described.FIGS. 2 to 5are cross-sectional views of a semiconductor device and depict a fabrication method thereof according to the first embodiment. First, as depicted inFIG. 2, the p-type base region2is laid by an epitaxial growth method, for example, on the surface of the semiconductor substrate forming the n−-type drift region1. For example, photolithography is used for forming the trench3that penetrates the base region2to reach the drift region1. The gate insulating film4made up of a thin silicon dioxide film (SiO2) is then formed on the side surface and the bottom surface of the trench3by a thermal oxidation method, for example. The gate electrode5is formed inside the trench3via the gate insulating film4by embedding polysilicon (Poly-Si), for example.

As depicted inFIG. 3, an impurity region16is then formed in the surface layer of the base region2by introducing an impurity into a region deeper than the upper end of the gate electrode5. The impurity region16is formed with an impurity concentration higher than that of the base region2so as to be in contact with the trench3. Preferably, the impurity region16is formed with a depth equal to or greater than 0.05 μm and equal to or less than 1 μm from the upper end of the gate electrode5. A reason is that the protruding portion of the base region2cannot be formed as described above. Another reason is that the impurity concentration of the surface of the impurity region16becomes lower than the impurity concentration of the base region2if the impurity region16is formed deeper than 1 μm from the upper end of the gate electrode5. The conductivity type of the impurity region16may be the n-type or the p-type. The impurity may be introduced by using a thermal diffusion method or an ion implantation method. For example, the n+-type impurity region16may be formed in the surface of the p-type base region by ion implantation of phosphorus (P), etc. If a contact region (not depicted) is disposed in the surface layer of the base region2, the impurity region16is formed with an impurity concentration higher than the contact region.

As depicted inFIG. 4, the impurity region16is then removed by etching using a mixed acid or aqueous potassium hydroxide solution (KOH) containing hydrofluoric acid (HF) and nitric acid (HNO3), for example. The base region2is not removed and remains because of the impurity concentration lower than the impurity region16. Since the gate insulating film4is formed on the sidewall of the trench3, the gate insulating film4and the gate electrode5are not removed. Therefore, only the impurity region16can be removed by simply performing the etching without selectively forming, for example, a mask on the surface of the base region2. As a result, the first recess portion6in contact with the trench3can be formed in the surface layer of the base region2such that the protruding portion of the base region2remains. The etching may be wet etching or dry etching.

As depicted inFIG. 5, the interlayer insulating film7, for example, a PSG film, is selectively formed on the surface of the semiconductor substrate to cover the surface of the gate electrode5. For example, a plating method is used for forming the source electrode8that is embedded inside the first recess portion6to be in contact with the base region2exposed on the substrate surface. The source electrode8may be formed by using a chemical vapor deposition (CVD) method or a sputtering method instead of the plating method. Nickel (Ni), tungsten (W), aluminum (Al), etc., may be used as a metal material for the source electrode8.

The source electrode8may have a configuration in which multiple metal electrode layers are laid. In this case, the metal electrode layers forming the source electrode8may be laid with formation methods and metal materials variously changed. For example, a tungsten electrode layer may be laid by using the CVD method for the source electrode8embedded inside the first recess portion6and an aluminum electrode layer may be laid subsequently by using the sputtering method or the plating method for the source electrode8formed on the substrate surface. Preferably, at least the metal electrode layer of the bottom layer is formed as a tungsten electrode layer by using the CVD method. This enables a metal material of the source electrode8to be accurately embedded in corners, etc., of the bottom surface of the first recess portion6. Therefore, for example, problems such as peeling of the source electrode8can be prevented.

The drain electrode9in contact with the drift region1is formed on the backside of the semiconductor substrate. This completes the MOSFET of the trench gate structure depicted inFIG. 1.

As described above, according to the first embodiment, the first recess portion6deeper than the upper end of the gate electrode5is formed in the surface layer of the base region2without disposing a source region (the source region106ofFIG. 17). The source electrode8is embedded inside the first recess portion6. Therefore, a parasitic bipolar transistor (parasitic element) consisting of the drift region1, the base region2, and the source region is not formed in the semiconductor device. The semiconductor device operates in a conventional manner. Therefore, the influences of the parasitic element can be controlled. As a result, the semiconductor device can be prevented from being destroyed when an abnormal current flows in the semiconductor device. Since a parasitic element is not formed in the semiconductor device, it is not necessary to increase the impurity concentration of the base region when the semiconductor device is miniaturized. As a result, the channel region can be inverted sufficiently without increasing the on-voltage. Therefore, the on-voltage can be prevented from increasing. In the surface layer of the base region2, the impurity region16is formed deeper than the upper end of the gate electrode5with an impurity concentration higher than the base region2. As a result, only the impurity region16formed on the surface layer of the base region2can be removed by etching and the first recess portion6deeper than the upper end of the gate electrode5can be formed in the surface layer of the base region2. By embedding the source electrode8inside the first recess portion6, the semiconductor device can be fabricated without forming a parasitic element.

FIGS. 6 and 7are cross-sectional views of a semiconductor device and depict a fabrication method thereof according to a second embodiment. In the fabrication method according to the first embodiment, the etching may be performed by using the interlayer insulating film7as a mask to form the first recess portion6.

In the second embodiment, as is the case with the first embodiment, the base region2, the trench3, the gate insulating film4, and the gate electrode5are formed on the surface of the semiconductor substrate forming the drift region1(seeFIG. 2). As depicted inFIG. 6, the interlayer insulating film7is selectively formed on the surface of the semiconductor substrate. The interlayer insulating film7has an opening17that exposes a portion of the surface of the base region2. The interlayer insulating film7covers the gate electrode5. As depicted inFIG. 7, the etching is performed by using the interlayer insulating film7as a mask to remove the base region2exposed from the opening17. In this case, the base region2is removed to the same depth as the impurity region (seeFIGS. 3 and 4) formed in the surface of the base region2in the first embodiment. As a result, the first recess portion6is formed in the same way as the first embodiment. The interlayer insulating film7remaining on the surface of the protruding portion of the base region2is removed to leave only the interlayer insulating film7covering the gate electrode5. The source electrode8is then formed as is the case with the first embodiment. This leads to the same state as that of a semiconductor device fabricated as depicted inFIG. 5. The subsequent process is performed in the same way as the first embodiment to complete the semiconductor device depicted inFIG. 1. Other arrangements are the same as the first embodiment.

As described above, according to the second embodiment, the same effects as the first embodiment can be achieved.

FIGS. 8 and 9are cross-sectional views of a semiconductor device and depict a fabrication method thereof according to a third embodiment. In the fabrication method according to the first embodiment, the etching may be performed by using a photoresist as a mask to form the first recess portion6.

In the third embodiment, as is the case with the first embodiment, the base region2, the trench3, the gate insulating film4, and the gate electrode5are formed on the surface of the semiconductor substrate forming the drift region1(seeFIG. 2). As depicted inFIG. 8, a resist make18is selectively formed on the surface of the semiconductor substrate. The resist mask18has an opening19that exposes a portion of the surface of the base region2. As depicted inFIG. 9, the etching is performed by using the resist mask18as a mask to remove the base region2exposed from the opening19. In this case, the base region2is removed to the same depth as the impurity region (seeFIGS. 3 and 4) formed in the surface of the base region2in the first embodiment. As a result, the first recess portion6is formed in the same way as the first embodiment. The resist mask18is removed completely. This leads to the same state as that of a semiconductor device fabricated as depicted inFIG. 4. The subsequent process is performed in the same way as the first embodiment (seeFIG. 5) to complete the semiconductor device depicted inFIG. 1. Other arrangements are the same as the first embodiment. Further, the mask used to form the first recess portion6is not limited to the resist mask18and another material resistant to etching solution may be used.

As described above, according to the third embodiment, the same effects as the first embodiment can be achieved.

FIG. 10is a cross-sectional view of a semiconductor device according to a fourth embodiment. In the semiconductor device depicted inFIG. 10, a p-type base region22is selectively disposed on a surface layer of a semiconductor substrate acting as an n−-type drift region21. The base region22has an impurity concentration higher than that of the drift region21. The drift region21corresponds to a first semiconductor region. The base region22corresponds to a second semiconductor region.

A second recess portion26is formed in the surface layer of the base region22. Therefore, the base region22has an uneven surface shape made up of the first recess portion6and a protruding portion without the first recess portion6. In the surface of the semiconductor substrate, a gate electrode25is disposed via a gate insulating film24to cover the protruding portion of the base region22and to project into the second recess portion26. Therefore, the second recess portion26is disposed to occupy a portion of a region under the gate electrode25. Preferably, a second distance w from a sidewall of the second recess portion26to a plane encompassing an end of the gate electrode25projecting into the second recess portion26is equal to or greater than 0.05 μm and equal to or less than 1 μm. The reason is the same as the reason of disposing the first recess portion (seeFIG. 1) such that the first distance is achieved in the first embodiment. A channel region31is a region of the base region22in contact with the gate insulating film24under the gate electrode25. The gate insulating film24corresponds to an insulating film. The gate electrode25corresponds to a first electrode.

A source electrode28is embedded inside the second recess portion26and is in contact with the base region22. The source electrode28is electrically insulated from the gate electrode25by an interlayer insulating film27. The source electrode28corresponds to a second electrode. A drain electrode29is disposed on the backside of the semiconductor substrate.

A method of fabricating such a semiconductor device will be described.FIGS. 11 to 15are cross-sectional views of the semiconductor device according to the fourth embodiment and depict a fabrication method thereof. First, as depicted inFIG. 11, the p-type base region22is selectively formed, by ion implantation of boron (B), for example, on the surface layer of the semiconductor substrate forming the n−-type drift region21. An impurity region36is then formed by selectively introducing an impurity into the surface layer of the base region22. The impurity region36is formed to have an impurity concentration higher than that of the base region22. The conductivity type of the impurity region36may be the n-type or the p-type. The formation method of the impurity region36is the same as the formation method of the impurity region of the first embodiment.

As depicted inFIG. 12, an insulating film forming the gate insulating film24is formed on the surface of the semiconductor substrate by a thermal oxidation method, for example. The gate electrode25is formed on the surface of the gate insulating film24to cover portions of the base region22and the impurity region36by a sputtering method, for example. The gate electrode25is formed such that an end of the gate electrode25on the side of the impurity region36overlaps an end of the impurity region36by a width equal to or greater than 0.05 μm and equal to or less than 1 μm. The surface of the semiconductor substrate is covered by the interlayer insulating film27made up of a PSG film, for example. As depicted inFIG. 13, portions of the gate insulating film24and the interlayer insulating film27are removed by, for example, photolithography to expose a portion of the surface of the impurity region36.

As depicted inFIG. 14, the impurity region36is then removed by etching to form the second recess portion26in the surface layer of the base region22. The etching conditions are the same as the first embodiment. As a result, the second recess portion26can be formed that occupies the region under the gate electrode25with the second distance w equal to or greater than 0.05 μm and equal to or less than 1 μm. As depicted inFIG. 15, the source electrode28is embedded inside the second recess portion26. The formation method of the source electrode28is the same as the first embodiment. The drain electrode29in contact with the drift region21is formed on the backside of the semiconductor substrate. This completes the MOSFET of the planar structure depicted inFIG. 10.

As described above, according to the fourth embodiment, the second recess portion26is disposed in the surface layer of the base region22to occupy a portion of the region under the gate electrode25without disposing the source region. The source electrode28is embedded inside the second recess portion26. As a result, the same effects as the first embodiment can be acquired. The impurity region36having an impurity concentration higher than that of the base region22is formed in the surface layer of the base region22and the gate electrode25is formed to cover a portion of the impurity region36. As a result, the etching can be performed to form the second recess portion26occupying a portion of the region under the gate electrode25in the surface layer of the base region22, and the same effects as the first embodiment can be achieved.

FIG. 16is a conceptual diagram schematically depicting a cross-section of a semiconductor device of the embodiments. The semiconductor device of the trench gate structure was fabricated according to the fabrication method according to the first embodiment. First, a trench43was formed that penetrates a base region42to reach a drift region (not depicted). A depth and a width of the trench43were set to 5 μm and 1.2 μm, respectively. The distance between the trenches43was set to 2.8 μm. A gate electrode45was formed inside the trench43via a gate insulating film44. An impurity region (not depicted) was formed in the surface layer of the base region42.

Etching was then performed. It was found that the etching can remove only the impurity region (not depicted) formed in the surface layer of the base region42to form a first recess portion46as depicted inFIG. 16. A plating method was subsequently used for plating of nickel to form a source electrode48. It was found that the source electrode48can be embedded inside the first recess portion46as depicted inFIG. 16. The source electrode48and the gate electrode45were insulated by an interlayer insulating film47. The operation of the semiconductor device fabricated in this way was then checked. It was found that the semiconductor device operates in the same way as conventional semiconductor devices.

In the embodiments described above, IGBT of the trench gate structure may be formed by disposing a p-type collector region having an impurity concentration higher than that of a drift region, between the drift region and a backside electrode. In this case, a parasitic thyristor (parasitic element) consisting of the collector region, the drift region, the base region, and the emitter region is not formed. Therefore, the same effects as the embodiments described above can be acquired. The backside electrode is a collector electrode. The collector electrode corresponds to a third electrode. The collector region corresponds to a third semiconductor region.

Although the present invention has been described with an example of a circuit having a configuration in which one semiconductor device is disposed on a semiconductor substrate, the present invention is applicable not only to the embodiments described above but also to an integrated circuit (IC) having a configuration in which a plurality of semiconductor devices is disposed on the same substrate. The n-type and the p-type of the regions of the semiconductor device may be configured to be entirely reversed.

According to the invention described above, the second recess portion is disposed in the surface layer of the second semiconductor region to occupy a portion of a region under the first electrode without disposing the source region. The second electrode is embedded inside the second recess portion. Therefore, a parasitic bipolar transistor (parasitic element) consisting of the first semiconductor region, the second semiconductor region, and the source region is not formed in the semiconductor device. The semiconductor device operates in a conventional manner.

According to the invention, an emitter region is not disposed in the surface layer of the second semiconductor region. Therefore, a parasitic thyristor (parasitic element) consisting of the third semiconductor region, the first semiconductor region, the second semiconductor region, and the emitter region is not formed. The semiconductor device operates in a conventional manner.

According to the invention, since no parasitic element is formed in the semiconductor device, it is not necessary to increase the impurity concentration of the second semiconductor region when the semiconductor device is reduced in size. Therefore, the channel region can be inverted sufficiently without increasing the on-voltage.

According to the invention, in the surface layer of the second semiconductor region, the impurity region is formed deeper than the upper end of the first electrode and has an impurity concentration higher than the second semiconductor region. As a result, only the impurity region can be removed by etching and the first recess portion deeper than the upper end of the first electrode can be formed in the surface layer of the second semiconductor region. By embedding the second electrode inside the first recess portion, the semiconductor device can be fabricated without forming a parasitic element.

According to the invention, in the surface layer of the second semiconductor region, the impurity region is formed of an impurity concentration higher than that of the second semiconductor region and the first electrode is formed to cover a portion of the impurity region. As a result, only the impurity region can be removed by etching and the second recess portion occupying a portion of a region under the first electrode can be formed in the surface layer of the second semiconductor region. By embedding the second electrode inside the second recess portion, the semiconductor device can be fabricated without forming a parasitic element.

As described above, the semiconductor device and the method of fabricating the semiconductor device according to the present invention are useful in the fabrication of high-power semiconductor devices and are particularly suitable in the fabrication of insulated gate semiconductor devices such as MOSFET and IGBT.

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-037535, filed on Feb. 23, 2010, the entire contents of which are incorporated herein by reference.