Switching frequency control apparatus and control method thereof

A switch frequency control apparatus comprises a timer coupled between a bias voltage and ground, wherein the timer comprises a first input configured to receive a ramp, a second input configured to receive a threshold voltage and an output configured to be connected to an input of a PWM circuit, wherein the output of the timer is used for setting either a constant on-time or a constant off-time of a power converter and a threshold generator coupled between the bias voltage and ground, wherein the threshold generator is configured to receive a plurality of control signals of the power converter and generate the threshold voltage based upon a duty cycle of the power converter.

TECHNICAL FIELD

The present invention relates to a control scheme of a power converter, and, in particular embodiments, to a power converter employing a constant on-time control scheme or a constant off-time control scheme with a constant switching frequency under various operating conditions.

BACKGROUND

As technologies further advance, a variety of electronic devices, such as mobile phones, tablet PCs, digital cameras, MP3 players and/or the like, have become popular. Each electronic device requires direct current power at a substantially constant voltage which may be regulated within a specified tolerance even when the current drawn by the electronic device may vary over a wide range. In order to maintain the voltage within the specified tolerance, a power converter (e.g., a switching dc/dc converter) coupled to the electronic device provides very fast transient responses, while keeping a stable output voltage under various load transients.

Hysteretic-based power converter control schemes such as the constant on-time scheme or the constant off-time scheme can enable power converters to provide fast transient responses. A buck converter employing the constant on-time control scheme may only comprise a feedback comparator and an on-timer. In operation, the feedback circuit of the power converter (e.g., buck converter) directly compares a feedback signal with an internal reference. When the feedback signal falls below the internal reference, the high-side switch of the power converter is turned on and remains on for the on-timer duration. As a result of turning on the high side switch, the inductor current of the power converter rises. The high-side switch of the power converter turns off when the on-timer expires, and does not turn on until the feedback signal falls below the internal reference again. In summary, when the constant on-time control scheme is employed in a power converter, the on-time of the high-side switch of the power converter is terminated by the on-timer. The off-time of the high-side switch of the power converter is terminated by the feedback comparator. Similarly, a boost converter employing a constant off-time control scheme can achieve fast transient responses.

The power converters employing the constant on-time control scheme or the constant off-time control scheme are simple to design. However, the constant on-time control scheme and the constant off-time control scheme have an unwanted application issue. Under different operating conditions, the switching frequency of the constant on/off time controlled power converter varies in a wide range. Such a switching frequency variation is not preferable in many applications.

It would be desirable to provide an apparatus and/or a method for enabling the power converters employing the constant on-time control scheme or the constant off-time control to have a fixed switching frequency under a variety of operating conditions.

SUMMARY

In particular embodiments, a control scheme of a constant on/off time controlled power converter may achieve a fixed switching frequency under a variety of operating conditions.

In accordance with an embodiment, an apparatus comprises a timer coupled between a bias voltage and ground, wherein the timer comprises a first input configured to receive a ramp, a second input configured to receive a threshold voltage and an output configured to be connected to an input of a PWM circuit, wherein the output of the timer is used for setting either an on-time or an off-time of a power converter and a threshold generator coupled between the bias voltage and ground, wherein the threshold generator is configured to receive a plurality of control signals of the power converter and generate the threshold voltage based upon a duty cycle of the power converter.

In accordance with another embodiment, a method comprises generating a ramp using a bias voltage of a power converter, generating a threshold voltage proportional to either a duty cycle or one minus a duty cycle of the power converter, comparing the ramp with the threshold voltage using a comparator and terminating or initiating a PWM signal of the power converter based upon a comparing result generated by the comparator.

In accordance with yet another embodiment, a converter comprises a high-side switch and a low-side switch connected in series, an inductor connected to a common node of the high-side switch and the low-side switch and a control apparatus configured to generate gate drive signals for the high-side switch and the low-side switch, wherein the control apparatus comprises a timer for setting either an on-time or an off-time of the converter and a threshold generator configured to receive the gate drive signals of the converter and generate a threshold voltage based upon a duty cycle of the converter.

An advantage of a preferred embodiment of the present disclosure is generating a ramp threshold proportional to the duty cycle (D) of a step-down power converter or one minus the duty cycle (1-D) of a step-up power converter. As a result having this ramp threshold, the power converter can achieve a fixed or an almost fixed switching frequency under different operating conditions.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present disclosure will be described with respect to preferred embodiments in a specific context, namely a constant off-time/on-time controlled power converter operating in a fixed switching frequency or an almost fixed switching frequency under various operating conditions. The invention may also be applied, however, to a variety of power converters. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

FIG. 1illustrates a block diagram of a control apparatus of a power converter in accordance with various embodiments of the present disclosure. The power converter100is step-up power converter (also known as a boost converter). Alternatively, the power converter100is a step-down power converter (also known as a buck converter). The operation of the power converter100is controlled by a control apparatus180.

As shown inFIG. 1, the power converter100includes a first switch S1, a second switch S2, an inductor L and an output capacitor Co. In some embodiments, the power converter100is implemented as a step-up power converter. The first switch S1and the second switch S2are connected in series between an output terminal VOUT and ground. The inductor L is connected between the common node of the first switch S and the second switch S2and an input terminal VIN.

In alternative embodiments, the power converter100is implemented as a step-down power converter. The first switch S1and the second switch S2are connected in series between the input terminal VIN and ground. The inductor L is connected between the common node of the first switch S1and the second switch S2, and the output capacitor Co.

Throughout the description, when the power converter100is implemented as a step-down power converter, the first switch S1may be alternatively referred to as a high-side switch of the power converter100, and the second switch S2may be alternatively referred to as a low-side switch of the power converter100. A ratio of the turn-on time of the first switch S1to the switching period of the power converter100is a duty cycle (D) of the step-down power converter.

Throughout the description, when the power converter100is implemented as a step-up power converter, the first switch S1may be alternatively referred to as a low-side switch of the power converter100, and the second switch S2may be alternatively referred to as a high-side switch of the power converter100. A ratio of the turn-on time of the first switch S1to the switching period of the power converter100is a duty cycle (D) of the step-up power converter. A ratio of the turn-off time of the first switch S1to the switching period of the power converter100is an off-time duty cycle (I-D) of the step-up power converter.

In some embodiments, the power converter100is implemented as a constant on-time power converter when the first switch S1, the second switch S2and the inductor L form a step-down power converter. In alternative embodiments, the power converter100may be implemented as a constant off-time power converter when the first switch S1, the second switch S2and the inductor L form a step-up power converter.

The first switch S1and the second switch S2are implemented as n-type transistors as shown inFIG. 1. The gate of the first switch S1and the gate of the second switch S2are controlled by the control apparatus180.

It should be noted that the power converter100shown inFIG. 1is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the first switch S1may be implemented as a p-type transistor. Furthermore, the switch of the power converter100(e.g., the first switch S1) may be implemented as a plurality of n-type transistors connected in parallel.

In some embodiments, when the power converter100is implemented as a step-down power converter, the control apparatus180may apply a constant on-time control scheme to the power converter100. In addition, under different operation conditions, the control apparatus180may determine the on-time of the high-side switch of the step-down power converter through comparing a ramp signal with a threshold voltage. The ramp signal is generated by charging a capacitor using a constant current source. The threshold voltage is generated by a threshold voltage generator. In order to have a constant switching frequency or an almost fixed switching frequency, the threshold voltage is proportional to the duty cycle (D) of the step-down power converter.

In alternative embodiments, when the power converter100is implemented as a step-up power converter, the control apparatus180may apply a constant off-time control scheme to the power converter100. The control apparatus180may determine the off-time of the low-side switch of the step-up power converter through comparing a ramp signal with a threshold voltage. The ramp signal is generated by charging a capacitor using a constant current source. The threshold voltage is generated by a threshold voltage generator. In order to have a constant switching frequency, the threshold voltage is proportional to one minus the duty cycle (1−D) of the step-up power converter.

As shown inFIG. 1, the control apparatus180is configured to receive a plurality of signals such as FB, which is proportional to the output voltage VOUT. Furthermore, depending on different applications and design needs, the control apparatus180may be configured to receive other suitable signals such as the input voltage VIN. Based upon the output voltage VOUT and/or the input voltage VIN, the control apparatus180generates two gate signals for controlling the operation of the power converter100. The detailed operation of the control apparatus180will be described below withFIGS. 2-9.

FIG. 2illustrates a detailed block diagram of the control apparatus of the power converter shown inFIG. 1in accordance with various embodiments of the present disclosure. The control apparatus180of the power converter100comprises a feedback control apparatus202, an on/off time generation apparatus204, a pulse width modulation (PWM) circuit206, a control logic apparatus208and a driver circuit210.

In some embodiments, the feedback control apparatus202is employed to monitor the output voltage of the power converter100(shown inFIG. 1). The input signal FB of the feedback control apparatus202is a voltage signal proportional to the output voltage of the power converter100. The input signal REF of the feedback control apparatus202is a predetermined reference voltage. In some embodiments, the input signal REF is equal to 0.8 V.

As shown inFIG. 2, the on/off time generation apparatus204is configured to receive a high-side gate drive signal HSON, a low-side gate drive signal LSON, a bias voltage VCC. In alternative embodiments, the on/off time generation apparatus204may be configured to receive other suitable control signals such as a PWM signal. The high-side gate drive signal HSON and the low-side gate drive signal LSON are generated by the control logic apparatus208as shown inFIG. 2. The PWM signal is generated by the PWM circuit206.

Depending on different applications and design needs, the on/off time generation apparatus204may be implemented either as an on-time generation apparatus or an off-time generation apparatus. For example, when the power converter100is a step-down power converter, the on/off time generation apparatus204is implemented as an on-time generation apparatus. Throughout the description, the on/off time generation apparatus204is alternatively referred to as the on-time generation apparatus204when the power converter100is a step-down power converter.

According to the operating principle of constant on-time power converters, the feedback control apparatus202is employed to turn on the high-side switch S1when the detected output voltage FB is below a predetermined reference (e.g., VREF inFIG. 2). More particularly, the turn-on signal of the high-side switch S1is generated through applying a logic high signal to a first input of the PWM circuit206(e.g., a set input of a latch). After the high-side switch S1has been turned on, the turn-off of the high-side switch Q1is determined by the on-time generation apparatus204. The turn-off signal of the high-side switch S1is generated through applying a logic high signal to a second input of the PWM circuit206(e.g., a reset input of a latch). The detailed operation principle of the on-time generation apparatus204will be described below with respect toFIG. 7.

In some embodiments, the power converter100is a step-up power converter, the on/off time generation apparatus204is implemented as an off-time generation apparatus. Throughout the description, the on/off time generation apparatus204is alternatively referred to as the off-time generation apparatus204when the power converter100is a step-up power converter.

According to the operating principle of constant off-time power converters, the off-time generation apparatus204is employed to turn on the low-side switch S1when the off-time timer times out. The turn-on signal of the low-side switch S1is generated through applying a logic high signal to a first input of the PWM circuit206(e.g., a set input of a latch). After the low-side switch S1has been turned on, the turn-off of the low-side switch S1is determined by the feedback control apparatus202. The turn-off signal of the low-side switch S1is generated through applying a logic high signal applied to a second input of the PWM circuit206(e.g., a reset input of a latch). The detailed implementation of the feedback control apparatus202will be described below with respect toFIG. 6.

The control logic apparatus208has an input connected to an output of the PWM circuit206. In some embodiments, the control logic apparatus208is employed to generate the high-side drive signal HSON and the low-side drive signal LSON based upon the output signal/signals of the PWM circuit206. Furthermore, the control logic apparatus208may be used to produce special features for the high-side drive signal HSON and the low-side drive signal LSON. For example, the control logic apparatus208may insert small amount of time between the high-side drive signal HSON and the low-side drive signal LSON. The small amount of time is known as the dead-time between the high-side drive signal HSON and the low-side drive signal LSON.

The control logic apparatus208has two outputs. A first output provides a gate drive signal for the high-side switch. The first output signal of the control logic apparatus208is defined as HSON as shown inFIG. 2. A second output provides a gate drive signal for the low-side switch. The second output signal of the control logic apparatus208is defined as LSON as shown inFIG. 2.

The driver circuit210is employed to provide high speed and high current drive capability for the power converter100. In some embodiments, the driver circuit210may further comprise a level-shifting circuit for driving an n-channel high-side switch (e.g., the high-side switch S1).

The driver apparatus210has two outputs. A first output is connected to the gate of the high-side switch. The first output signal of the driver circuit210is defined as HSDRV as shown inFIG. 2. A second output is connected to the gate of the low-side switch. The second output signal of the driver circuit210is defined as LSDRV as shown inFIG. 2.

FIG. 3illustrates a schematic diagram of a first implementation of the on/off time generation apparatus shown inFIG. 2in accordance with various embodiments of the present disclosure. In some embodiments, the power converter100is implemented as a step-up power converter350as shown inFIG. 3. The on/off time generation apparatus is implemented as an off-time generation apparatus204.

As shown inFIG. 3, the off-time generation apparatus204includes a current source302, a capacitor Cr, a switch Qr, a comparator304and a threshold voltage generation apparatus301. As shown inFIG. 3, the current source302, the capacitor Cr, the switch Qr and the comparator304form an off-time timer apparatus303.

As shown inFIG. 3, the current source is coupled to the bias voltage VCC. In some embodiments, the current level of the current source302is proportional to the bias voltage VCC. More particularly, the current level of the current source302is equal to the bias voltage VCC divided by a predetermined resistor R. The current source302is used to charge the capacitor Cr. As shown in the timing diagram310, from the time instant t0to the time instant t1, the voltage across Cr is a voltage ramp.

The voltage across the capacitor Cr is fed into a non-inverting input of the comparator304. The inverting input of the comparator304is connected to the threshold voltage generation apparatus301. The gate of the switch Qr is controlled by a signal RST. In some embodiments, the signal RST is the same as or synchronized to the gate drive signal of the low-side switch S1.

In operation, prior to the time instant t0, the low-side switch S1is turned on, a logic level “1” and a logic level “0” are applied to the set input and the reset input of a latch respectively (shown inFIG. 6). The latch generates a logic level “1” and applies this signal to the gate of the low-side switch S1as well as the gate of the switch Qr. The logic level “1” turns on the switch Qr. As a result of turning on the switch Qr, the voltage across the capacitor Cr equal to about zero.

At the time instant t0, the feedback control apparatus202turns off the low-side switch S1. In response to the turn-off of the low-side switch S1, the latch generates a logic level “0” and applies this signal (RST) to the gate of the switch Qr. The logic level “0” turns off the switch Qr. As a result of turning off the switch Qr, the current source302starts to charge the capacitor Cr in a linear manner from the time instant t0to the time instant t1.

The voltage across the capacitor Cr (VCAP) is compared with the threshold voltage at the comparator304. After the voltage across the capacitor Cr reaches the voltage VTH generated by the threshold voltage generation apparatus301, the output of the comparator304generates a logic level “1” at the time instant t1. The logic level “1” turns on the low-side switch S1at the time instant t1through the latch. The output of the latch is RST, which generates a logic level “1” at the time instant t1. The logic level “1” of RST turns on the switch Qr. The turned-on switch Qr discharges the capacitor Cr and maintains the voltage across the capacitor Cr equal to about zero. After the capacitor Cr has been discharged, the output of the comparator304generates a logic level “0” at the time instant t2.

As shown inFIG. 3, the voltage (VCAP) across the capacitor Cr is a voltage ramp from the time instant t0to the time instant t1. The voltage ramp is in sync with the off-time of the low-side switch S1. In other words, the voltage ramp starts from zero and linearly rises during the turn-off time of the low-side switch S1.

As shown inFIG. 3, the threshold voltage VTH is proportional to one minus the duty cycle (1-D) of the power converter100. The detailed structure of the threshold voltage generation apparatus301will be described below with respect toFIG. 5.

The relationship between the threshold voltage VTH and the duty cycle of the power converter100helps to maintain a constant switching frequency under various operating conditions. More particularly, as the load of the power converter100varies, the duty cycle of the power converter100may vary accordingly to maintain a regulated output voltage. Without having a threshold voltage VTH proportional to one minus the duty cycle (1-D) of the power converter100, the switching frequency of the power converter100may fluctuate under different loading conditions. By employing the threshold voltage VTH proportional to one minus the duty cycle (1-D) of the power converter100, the power converter100may maintain a stable switching frequency under various loading conditions.

As shown inFIG. 3, the turn-off time of the low-side switch S1is from the time instant t0to the time instant t1. The off-time of the low-side switch S1satisfies the following equations:

Equation (2) can be simplified as the flowing equation:
TOFF=Cr·K·R·(1−D)  (3)

Furthermore, the switching period is given by the following equation:

The switching period can be expressed as the following by replacing the off-time in Equation (4) with the off-time in Equation (3).
TSW=Cr·K·R=τ(5)

The switching frequency is given by the following equation:

As shown by Equation (6) above, the switching frequency of the power converter100is kept constant regardless of the duty variations. One advantageous feature of having the threshold voltage VTH shown inFIG. 3is the switching frequency of the power converter100is kept constant or maintained in a narrow range under a variety of loading conditions. Such an almost constant switching frequency helps to improve the performance of the power converter100. For example, with the constant or almost constant switching frequency, the power converter100is able to operate in some high-end power applications such as telecommunication power systems.

FIG. 4illustrates a schematic diagram of a second implementation of the on/off time generation apparatus shown inFIG. 2in accordance with various embodiments of the present disclosure. The on/off time generation apparatus204shown inFIG. 4is similar to that shown inFIG. 3except that the power converter100is implemented as a step-down power converter450. Since the power converter100is implemented as a step-down power converter, the on/off time generation apparatus204is implemented as an on-time generation apparatus. The structure of the on-time generation apparatus204shown inFIG. 4is similar to the structure of the off-time generation apparatus204shown inFIG. 3, and hence is not discussed herein.

In operation, prior to the time instant t0, the high-side switch S1is turned off and the low-side switch S2is turned on, a logic level “0” and a logic level “1” are applied to the set input and the reset input of a latch (e.g., latch206shown inFIG. 7). The output of the latch generates a logic level “0” and applies this signal to an inverter (e.g., inverter710shown inFIG. 7). A logic level “1” is generated at the output of the inverter. The logic level “1” functions as RST, which is applied to the gate of the switch Qr. The logic level “1” turns on the switch Qr. As a result of turning on the switch Qr, the voltage across the capacitor Cr equal to about zero.

At the time instant t0, the feedback control apparatus202turns on the high-side switch S1. In response to the turn-on of the high-side switch S1, a logic level “0” is generated at RST. The logic level “0” turns off the switch Qr. As a result of turning off the switch Qr, the current source302starts to charge the capacitor Cr in a linear manner from the time instant t0to the time instant t1.

The voltage (VCAP) across the capacitor Cr is compared with the threshold voltage VTH at the comparator304. After the voltage across the capacitor Cr reaches the voltage of the threshold voltage generation apparatus301, the output of the comparator304generates a logic level “1” at the time instant t1. The logic level “1” turns off the high-side switch S1at the time instant t1. In response to the turn-off of the high-side switch S1, a logic level “1” is generated at RST at the time instant t1. The logic level “1” of RST turns on the switch Qr. The turned-on switch Qr discharges the capacitor Cr and maintains the voltage across the capacitor Cr equal to about zero. After the capacitor Cr has been discharged, the output of the comparator304generates a logic level “0” at the time instant t2.

As shown inFIG. 4, the threshold voltage VTH is proportional to the duty cycle (D) of the power converter100. The detailed structure of the threshold voltage generation apparatus301will be described below with respect toFIG. 5.

The relationship between the threshold voltage VTH and the duty cycle of the power converter100helps to maintain a constant switching frequency under various operating conditions. More particularly, as the load of the power converter100varies, the duty cycle of the power converter100may vary accordingly to maintain a regulated output voltage. Without having a threshold voltage proportional to the duty cycle (D) of the power converter100, the switching frequency of the power converter100may fluctuate under different loading conditions. By employing the threshold voltage proportional to the duty cycle (D) of the power converter100, the power converter100may maintain a stable switching frequency under various loading conditions.

As shown inFIG. 4, the turn-on time of the high-side switch S1is from the time instant t0to the time instant t1. The on-time of the high-side switch S1satisfies the following equations:

Equation (8) can be simplified as the flowing equation:
TON=Cr·K·R·D(9)

Furthermore, the switching period is given by the following equation:

The switching period can be expressed as the following by replacing the on-time in Equation (10) with the on-time in Equation (9).
TSW=Cr·K·R=τ(11)

The switching frequency is given by the following equation:

As shown by Equation (12) above, the switching frequency of the power converter100is kept constant regardless of the duty variations. One advantageous feature of having the threshold voltage shown inFIG. 4is the switching frequency of the power converter100is kept constant or maintained in a narrow range under different loading conditions. Such an almost constant switching frequency helps to improve the performance of the power converter100. For example, with the almost constant switching frequency, the power converter100is able to operate in some high-end power applications such as telecommunication power systems and the like.

FIG. 5illustrates a schematic diagram of a first implementation of the threshold voltage generator apparatus shown inFIGS. 3-4in accordance with various embodiments of the present disclosure. The threshold voltage generation apparatus301comprises a first switch Q1and a second switch Q2connected in series between the bias voltage VCC and ground. The threshold voltage generation apparatus301further comprises a filtering circuit502connected to a common node of the first switch Q1and the second switch Q2. As shown inFIG. 5, the threshold voltage VTH is generated at an output of the filtering circuit502.

As shown inFIG. 5, a gate of the first switch Q1is controlled by the high-side gate drive signal of the power converter. As shown inFIG. 5, the high-side gate drive signal HSON is applied to the gate of the first switch Q1through an inverter504. It should be noted that the first switch Q1is a p-type transistor. The inverter504is employed to convert the high-side gate drive signal HSON into a suitable signal for driving the p-type transistor. A gate of the second switch Q2is controlled by the low-side gate drive signal LSON of the power converter.

The filtering circuit502comprises a resistor divider formed by resistors R1and R2, a control switch Q3and a capacitor CTH1. As shown inFIG. 5, the resistor divider and the control switch Q3are connected in series between the common node of the first switch Q1and the second switch Q2, and ground. The control switch Q3is controlled by both the high-side gate drive signal HSON and the low-side gate drive signal LSON. As shown inFIG. 5, the high-side gate drive signal HSON and the low-side gate drive signal LSON are applied to the gate of the control switch Q3through an OR gate506.

In operation, the control switch Q3is employed to disable the discharge path of the capacitor CTH1when both the high-side switch and the low-side switch of the power converter100are off. More particularly, the control switch Q3is used to hold the threshold voltage at a suitable level during the discontinuous conduction mode (DCM) operation of the power converter100. In some embodiments, the gate of the control switch Q3may be controlled by an adjustable gate drive voltage. More particularly, the adjustable gate drive voltage is of a high drive voltage when at least one of the high-side switch or the low-side switch of the power converter100is on. The adjustable gate drive voltage is of a low drive voltage (a voltage approximately equal to the turn-on threshold of the control switch Q3) when both the high-side switch and the low-side switch of the power converter100are off. Such an adjustable gate drive voltage helps to improve the response of the threshold voltage generation apparatus301.

In operation, the first switch Q1and the second switch Q2are controlled by the gate drive signals of the power switches S1and S2, respectively. In alternative embodiments, the first switch Q1and the second switch Q2are controlled by suitable control signals that are logically equivalent to the gate drive signals of the power switches S1and S2. When the power switches S1and S2are part of a step-up converter, the switch Q1and the switch Q2form a similar step-up converter. Throughout the filtering circuit502, the output voltage of the threshold voltage generation apparatus301can be given by the following equation:

On the other hand, when the power switches S1and S2are part of a step-down converter, the switch Q1and the switch Q2form a similar step-down converter. Throughout the filtering circuit502, the output voltage of the threshold voltage generation apparatus301can be given by the following equation:

As indicated by Equation (13), the output voltage of the threshold voltage generation apparatus301is proportional to one minus the duty cycle (1−D) of the power converter100when the power converter100functions as a step-up power converter. As indicated by Equation (14), the output voltage of the threshold voltage generation apparatus301is proportional to the duty cycle (D) of the power converter100when the power converter100functions as a step-down power converter.

One advantageous feature of having the threshold voltage generation apparatus301powered by the bias voltage VCC is the voltage stress on the switches (e.g., switch Q1) is controllable. In some conventional approaches, the threshold voltage generation apparatus301may be powered by the input voltage of the power converter100. The input voltage may vary in a wide range, which may cause excessive voltage stress on the switches of the threshold voltage generation apparatus301.

FIG. 6illustrates a schematic diagram of a step-up power converter employing the constant off-time control scheme in accordance with various embodiments of the present disclosure. The step-up power converter600includes a first switch S1, a second switch S2, an inductor L and an output capacitor C. As shown inFIG. 6, the first switch S1and the second switch S2are connected in series between the output terminal VOUT and ground. The inductor L is connected between the common node of the first switch S1and the second switch S2, and the input terminal VIN.

The control circuit of the step-up power converter600comprises a feedback control apparatus202, an off-time generation apparatus204, a PWM circuit206, a control logic apparatus208and a driver circuit210. As shown inFIG. 6, the feedback control apparatus202comprises a current sense apparatus602, an error amplifier604and a comparator606.

As shown inFIG. 6, the current flowing through the low-side switch S1is detected and fed into the current sense apparatus602. The current sense apparatus602converts the detected current signal into a suitable voltage signal. The output of the current sense apparatus602is fed into the non-inverting input of the comparator606. The operating principle of the current sense apparatus is well known, and hence is not discussed herein.

The non-inverting input of the error amplifier604is configured to receive a predetermined reference voltage VREF. In some embodiments, the predetermined reference voltage VREF is equal to 0.8 V. The inverting input of the error amplifier604is configured to receive a voltage signal FB proportional to the output voltage of the power converter. As shown inFIG. 6, the voltage signal FB is obtained through a voltage divider formed by RB1and RB2. The output of the error amplifier604is fed into the inverting input of the comparator606. The output of the comparator606is fed into a reset input of the PWM circuit206.

The off-time generation apparatus204includes the off-time threshold voltage generation apparatus301and the off-time timer apparatus303. As shown inFIG. 6, the off-time threshold voltage generation apparatus301is configured to receive the off-time duty cycle (1−D) and the bias voltage VCC. The output of the off-time threshold voltage generation apparatus301is fed into the off-time timer apparatus303. Furthermore, the off-time timer apparatus303also receives the bias voltage VCC and the PWM signal generated from the PWM circuit206. The structures of the off-time timer apparatus303and the off-time threshold voltage generation apparatus301are discussed in detail above with respect toFIGS. 3 and 5respectively and hence are not discussed again herein.

In some embodiments, the PWM circuit206is implemented as an R-S latch as shown inFIG. 6. Throughout the description, the PWM circuit206may be alternatively referred to as the latch206. The set input of the latch206is connected to the output of the off-time generation apparatus204. The reset input of the latch206is connected to the output of the comparator606. The output of the latch206is connected to the gates of the switches S1and S2through the control logic apparatus208and the driver circuit210.

In response to the output of the latch206, the control logic apparatus208generates the high-side gate drive signal HSON for the high-side switch S2and the low-side gate drive signal LSON for the low-side switch S1. The driver circuit210receives HSON and LSON signals and generates LSDRV signal applied to the gate of the low-side switch S1and HSDRV signal applied to the gate of the high-side switch S2.

A timing diagram601illustrates the operation principle of the step-up power converter600. At the time instant t1, the ramp voltage VCAP reaches the threshold voltage VTH. As discussed above with respect toFIG. 3, at the time instant t1, the output of the off-time generation apparatus204generates a logic level “1” and sends this logic level “1” to the set input of the latch206. According to the operating principle of the R-S latch, the output of the off-time generation apparatus204determines the turn-on edge or the leading edge of the PWM signal. In response to the logic state change of the PWM signal, the LSON and HSON signals change their logic states accordingly at the time instant t1.

As shown inFIG. 6, the logic level “1” of LSON is applied to the gate of S1through the driver circuit210. As a result of the turn-on of S1, the sense current VCS increase in a linear manner from the time instant t1to the time instant t2. From the time instant t1to the time instant t2, the PWM signal is of a logic high state, which turns on the switch Qr of the ramp generation circuit shown inFIG. 3. As a result, the ramp capacitor is discharged and the voltage VCAP is approximately equal to zero.

At the time instant t2, the sensed current signal VCS reaches the output voltage VCTRL of the error amplifier604. The output of the comparator606generates a logic level “1” and sends this logic level “1” to the reset input of the latch206. According to the operating principle of the R-S latch, the output of the comparator606determines the turn-off edge or the trailing edge of the PWM signal. In response to the logic state change of the PWM signal, the LSON and HSON signals change their logic states accordingly at the time instant t2.

As shown inFIG. 6, the logic level “O0” of LSON and the logic level “1” of HSON are applied to the gates of S1and S2respectively through the driver circuit210. As a result of the turn-off of S1and the turn-on of S2, the sense current VCS drops to zero and the current source (shown inFIG. 3) charges the ramp capacitor in a linear manner from the time instant t2to the time instant t3. At the time instant t3, the ramp voltage VCAP reaches the threshold voltage VTH again. The step-up power converter600enters into a new switching period.

FIG. 7illustrates a schematic diagram of a step-down power converter employing the constant on-time control scheme in accordance with various embodiments of the present disclosure. The control circuit of the step-down power converter700is similar to that shown inFIG. 6except that the feedback control apparatus202only comprises a comparator702and an inverter710is employed to generate the RST signal. Furthermore, the output (PUMP) of the comparator702is fed into the set input of the latch206. The output of the on-time generation apparatus204is fed into the reset input of the latch206.

As shown inFIG. 7, the input of the inverter710is configured to receive the output of the latch206. The inverter710generates a signal TON/RST and applies this signal to the RST input of the on-time timer apparatus303.

A timing diagram701illustrates the operation principle of the step-down power converter700. At the time instant t1, the output voltage VFB reaches the reference voltage VREF. The comparator702generates a logic level “1” at PUMP and sends this logic level “1” to the set input of the latch206. According to the operating principle of the R-S latch, the output of the comparator702determines the turn-on edge or the leading edge of the PWM signal. In response to the logic state change of the PWM signal, the LSON and HSON signals change their logic states accordingly at the time instant t1.

As shown inFIG. 7, the logic level “1” of HSON is applied to the gate of S1through the driver circuit210. From the time instant t1to the time instant t2, the TON/RST signal is of a logic low state, which turns off the switch Qr of the ramp generation circuit shown inFIG. 4. As a result, the current source (shown inFIG. 4) charges the ramp capacitor Cr in a linear manner from the time instant t1to the time instant t2.

At the time instant t2, the ramp voltage VCAP reaches the threshold voltage VTH. The output TOUT of the on-time timer apparatus303generates a logic level “1” and sends this logic level “1” to the reset input of the latch206. According to the operating principle of the R-S latch, the output of the on-time timer apparatus303determines the turn-off edge or the trailing edge of the PWM signal. In response to the logic state change of the PWM signal, the LSON and HSON signals change their logic states accordingly at the time instant t2.

As shown inFIG. 7, the logic level “O0” of HSON and the logic level “1” of LSON are applied to the gates of S1and S2respectively through the driver circuit210. As a result of the turn-off of S1and the turn-on of S2, the feedback voltage VFB drops in a linear manner from the time instant t2to the time instant t3. At the time instant t3, the feedback voltage VFB reaches the reference voltage VREF again. The step-down power converter700enters into a new switching period.

FIG. 8illustrates a schematic diagram of a second implementation of the threshold voltage generation apparatus shown inFIGS. 3-4in accordance with various embodiments of the present disclosure. The structure of the threshold voltage generation apparatus801is similar to the threshold voltage generation apparatus301shown inFIG. 5except that the filtering circuit is implemented as a two-stage filter. The first stage of the filtering circuit comprises resistors R1, R2and capacitor CTH1. The second stage of the filter stage of the filtering circuit comprises resistor R3and capacitor CTH2. As shown inFIG. 8, the first stage and the second stage are connected in cascade.

One advantageous feature of having the two-stage filter is the filtering circuit shown inFIG. 8provides more design flexibility, thereby improving the performance of the threshold voltage generation apparatus801.

FIG. 9illustrates a schematic diagram of a third implementation of the threshold voltage generation apparatus shown inFIGS. 3-4in accordance with various embodiments of the present disclosure. The structure of the threshold voltage generation apparatus901is similar to the threshold voltage generation apparatus301shown inFIG. 5except that the filtering circuit comprises a plurality of filter stages. The first stage of the filter comprises resistors R1, R2and capacitor CTH1. The second stage of the filter comprises resistor R3and capacitor CTH2. The nth stage of the filter comprises resistor Rn and capacitor CTHn. As shown inFIG. 9, the plurality of filter stages is connected in cascade.

One advantageous feature of having the plurality filter stages is the filter circuit shown inFIG. 9provides more design flexibility, thereby improving the performance of the threshold voltage generation apparatus901.

FIG. 10illustrates a flow chart of a method for controlling the power converter shown inFIG. 2in accordance with various embodiments of the present disclosure. This flowchart shown inFIG. 10is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated inFIG. 10may be added, removed, replaced, rearranged and repeated.

At step1002, a bias voltage is used to generate a ramp signal. More particularly, a current source is generated by the bias voltage. The current level of the current source is proportional to the bias voltage. The current source is used to charge a ramp capacitor.

At step1004, a threshold voltage is generated by a threshold voltage generation apparatus. When the power converter is implemented as a step-up converter, the threshold voltage is proportional to one minus the duty cycle (1−D) of the step-up converter. On the other hand, when the power converter is implemented as a step-down converter, the threshold voltage is proportional to the duty cycle (D) of the step-down converter.

At step1006, the ramp voltage and the threshold voltage are compared at a comparator. More particularly, the ramp voltage is fed into a non-inverting input of the comparator. The threshold voltage is fed into an inverting input of the comparator.

At step1008, after the ramp voltage reaches the threshold voltage, the output of the comparator generates a logic state change, which terminates or initiates a PWM signal of the power converter. In some embodiments, when the power converter is implemented as a step-up converter, the logic state change of the comparator terminates the off-time signal and initiates a PWM signal of the step-up converter. In alternative embodiments, when the power converter is implemented as a step-down converter, the logic state change of the comparator terminates the on-time signal (e.g., the PWM signal) of the step-down converter.