Refresh circuitry for phase change memory

A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and on other programmable resistive materials, and methods for refreshing such devices.

2. Description of Related Art

Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between amorphous and crystalline states by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state, referred to as set herein, is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.

It has been observed that some phase change memory cells in the reset state experience a decrease in resistance over time to below a threshold value used to distinguish between the reset and set states, resulting in data retention problems and bit errors for those memory cells. For example, a memory cell in which the active region has been reset to a generally amorphous state may over time develop a distribution of crystalline regions in the active region. If these crystalline regions connect to form a low resistance path through the active region, when the memory cell is read a lower resistance state will be detected and result in a data error. See, Gleixner, “Phase Change Memory Reliability”, 22nd NVSMW, 2007.

One attempt at addressing the data retention problems caused by the decrease in resistance over time is to maintain a relatively large read margin between the set and reset states. However, a relatively large read margin typically requires a slow set operation and a high reset current in order to obtain the large difference in resistance between the set and reset states. The relatively slow set operation and high reset current limit the operational speed of the device, restricting the use of phase change based memory circuits as high speed memory.

Thus, integrated circuits employing phase change based memory circuits typically also include other types of memory circuits in order to fulfill the memory performance requirements for the various functions of the integrated circuit. These different types of memory circuits are embedded at various locations in the integrated circuit, and typically include SRAM and DRAM memory circuits in order to provide high access speed memory for the integrated circuit. However, integration of different types of memory circuits for the various memory applications in an integrated circuit can be difficult and result in highly complex designs.

It has also been proposed to address the data retention problems by periodically refreshing phase change memory cells to offset any change in resistance that may occur over time.

One approach is to periodically read the resistance of each memory cell in the array to determine when to selectively perform a refresh operation on that particular memory cell. See, U.S. Patent Application Publication No. US 2008/0117704 entitled “Resistive Memory Including Selective Refresh Operation” by Happ et al, and U.S. Pat. No. 6,768,665 entitled “Refreshing Memory Cells of a Phase Change Material Memory Device” by Parkinson et al.

Another approach is to perform a refresh operation when the phase change memory has been accessed a number of times larger than a predetermined number. See, U.S. Patent Application Publication No. US 2008/0170431 entitled “Driving Method and System for a Phase Change Memory” by Sheu et al.

Another approach is to apply stress to a dummy set of memory cells based on the number of read and write operations performed on a main array of memory cells, and detecting changes in the resistance of the dummy set to determine when to refresh the main array of memory cells. See, U.S. Patent Application No. 2006/0158948 entitled “Memory Device” by Fuji.

It is therefore desirable to provide phase change based memory devices and methods for operating such devices which address the data retention issues discussed above and result in improved data storage performance.

SUMMARY OF THE INVENTION

A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array.

The memory device includes bias circuitry to establish low and high resistance states in the memory array and in the reference array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than a minimum resistance of the high resistance state for the memory array.

The device further includes sense circuitry to read the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory array.

As a result of the lower minimum resistance for the partial reset state for the reference array, the data retention performance of the reference array is worse than that of the memory array and is used as an early predictor of bit errors in the memory array and the need to perform refresh operation.

The reference array has a small number of memory cells compared to that of the memory array. In one example, the reference array may have on the order of 100 memory cells, while the memory array may have millions or billions of memory cells.

As a result of the relatively small number of memory cells in the reference array, the detection of bit errors in the data in the reference array can be carried out much more quickly than detecting bit errors directly in the memory array. Additionally, the complexity of control and sensing circuitry needed to detect the bit errors is greatly simplified.

Since the probability of a bit error occurring in any particular memory cell is preferably small, the reference array also provides a more relevant statistical predictor of possible bit errors in the memory array than can be achieved using a single reference cell.

Methods for operating memory devices comprising a memory array of phase change cells and a reference array of phase change cells are also disclosed herein.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to FIGS.1to8A-8E.

In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline phases.FIG. 1is an example distribution of the resistance for a number of memory cells each comprising a phase change memory element having one of two states (storing a single bit of data). The phase change memory elements of the memory cells are programmable to a high resistance reset (erased) state102and a lower resistance set (programmed) state100(storing a single bit of data), each corresponding to a non-overlapping resistance range.

The change from the high resistance state102to the lower resistance state100is generally a lower current operation in which current heats the phase change material above a transition temperature to cause transition from the amorphous to the crystalline phase. The change from the lower resistance state100to the higher resistance state102is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous phase.

The difference between the highest resistance R1of the lower resistance state100and the lower resistance R2of the high resistance reset state102defines a read margin101used to distinguish cells in the lower resistance state100from those in the high resistance state102. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the lower resistance state100or to the high resistance state102, for example by measuring whether the resistance of the memory cell is above or below a threshold resistance value RSA103within the read margin101.

In order to reliably distinguish between the reset state102and the set state100, it is important to maintain a relatively large read margin101. However, it has been observed that some phase change memory cells in the reset state102can experience an erratic “tailing bit” effect in which the resistance of the memory cell decreases over time to below the threshold resistance value RSA103, resulting in data retention problems and bit errors for those memory cells. The rate of reduction in resistance depends upon a number of factors, including variations in structure across the array, manufacturing defects in the cells and environmental conditions to which the device is exposed.

Furthermore, in order to meet high speed memory requirements such as those typically required of DRAM and SRAM, phase change based memory circuits must operate at high set and reset operational speeds and use less operational current. These high set and reset speeds and low operational current reduce the difference in resistance between the states100and102, which further increases the possibility of data retention problems and bit errors.

FIG. 2is a block diagram of a first embodiment of an integrated circuit210including a memory array212of phase change memory cells and a reference array250of phase change memory cells. The memory cells of the arrays212,250include an access device such as a diode or transistor, and a phase change memory element.

As described in more detail below, the integrated circuit210includes a controller234which controls the application of bias circuitry voltage & current sources236to establish low and high resistance states in the memory cells of the memory array212and in the memory cells of the reference array250.

The high resistance state for the reference array250is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array212. As a result, over time the data retention performance of the reference array250is worse than that of the memory array212, and bit errors in the reference array250can be used as an early predictor of bit errors in the memory array212and the need to perform a refresh operation. Thus, upon determination of a difference between a current data set stored in the reference array250and an expected data set, a refresh operation of the memory cells of the memory array212is performed.

The reference array250has a small number of memory cells compared to that of the memory array212, and thus can be read much more quickly and easily. In one example, the reference array212may have 100 or more memory cells, while the memory array212may have millions or billions of memory cells. As a result of the relatively small number of memory cells in the reference array212, the detection of bit errors in the data in the reference array250can be carried out much more quickly than attempting to detect bit errors directly in the memory array212. Additionally, the complexity of control and sensing circuitry needed to detect the bit errors is greatly simplified.

Also, since the probability of a bit error occurring in any particular memory cell is preferably small, the memory cells in the reference array250provides a more relevant statistical predictor of possible bit errors in the memory array212than can be achieved using a single reference cell.

A word line decoder214is coupled to and in electrical communication with a plurality of word lines216arranged along rows in the memory array212and reference array250. A bit line (column) decoder is in electrical communication with a plurality of bit lines220arranged along columns in the memory array212and reference array250. Addresses are supplied on bus222to word line decoder and drivers214and bit line decoder218. Sense circuitry and data-in structures in block224, including sense amplifier circuitry for the memory array212and reference array250, are coupled to bit line decoder218via data bus226. Data is supplied via a data-in line228from input/output ports on integrated circuit, to data-in structures in block224. Other circuitry230may be included on integrated circuit210, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array212. Data is supplied via a data-out line232from the sense amplifiers in block224to input/output ports on integrated circuit210, or other data destinations internal or external to integrated circuit210.

A controller234, implemented in this example using a bias arrangement state machine, controls the application of bias circuitry voltage & current sources236to apply bias arrangements such as read, program, erase, erase verify, program verify, and refresh to the memory cells of the memory array212and the reference array250. The characteristics of the signals sent from the controller234determine the array212,250to be accessed as well as the operation to be performed. Controller234may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller234comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller234. As described in more detail below, the controller234implements a refresh mode to refresh the memory cells of the memory array212and reference array250in response to a refresh command from the reference array sense circuitry of block224, the refresh command indicating a difference between a current data set stored in the reference array and an expected data set.

The memory array212and reference array250can be arranged in different units of the same array to share bit lines and/or word lines, for example different banks, blocks, or sections of the same array. Alternatively, the memory array212and the reference array can be implemented in physically separate arrays.

In operation each of the memory cells in the arrays212,250store data represented by the resistance of the corresponding memory element. The data value may be determined, for example, by comparison of voltage or current on a bit line for a selected memory cell to that of a suitable reference current or voltage by sense amplifiers in sense circuitry224.

Reading or writing to a memory cell of arrays212,250, therefore, can be achieved by applying bias arrangements to provide appropriate voltages and/or current pulses to word lines and bit lines so that current flows through the selected memory cell. The level and duration of the pulses applied is dependent upon the array212,250, and also the operation to be performed. The level and durations of the pulses applied can be determined empirically for each embodiment. The various modes of operation for the memory array212and reference array250are explained in more detail below.

Memory Array

In biasing arrangements for a reset (erase) operation for a memory cell in the memory array212, word line decoder214facilitates providing a word line with a suitable voltage pulse to turn on the access transistor of the memory cell. Bit line decoder218facilitates supplying a voltage pulse to a bit line of suitable amplitude and duration to induce a current to flow through the memory element, the current raising the temperature of the active region of the memory element above the transition temperature of the phase change material and also above the melting temperature to place the active region in a liquid state. The current is then terminated, for example by terminating the voltages on the bit line and word line, resulting in a relatively quick quenching time as the active region cools, thereby setting the phase change material to a resistance within a resistive value associated with the memory array higher resistance reset state302as shown inFIG. 3.

In biasing arrangements for a set (program) operation for a memory cell in the memory array212, word line decoder214facilitates providing a word line with a suitable voltage pulse to turn on the access transistor of the memory cell. Bit line decoder224facilitates supplying a voltage pulse to a bit line of suitable amplitude and duration to induce a current to flow through the memory element, the current sufficient to raise the temperature of the active region above the transition temperature and cause a transition of at least a portion of the active region from the amorphous phase into the crystalline phase, this transition lowering the resistance of the memory element and setting the resistance of the phase change material within a resistive value range associated with the memory array lower resistance set state300.

The difference between the highest resistance R1of the memory array lower resistance set state300and the lower resistance R2of the memory array higher resistance reset state302defines a memory array read margin301used to distinguish cells of the memory array212in the lower resistance set state300from those in the higher resistance reset state302.

In a read operation for a memory cell in the memory array212, word line decoder214facilitates providing a word line with a suitable voltage pulse to turn on the access transistor of the memory cell. Bit line decoder218facilitates supplying a voltage pulse to a bit line of suitable amplitude and duration to induce a current to flow through the memory element that does not result in the memory element undergoing a change in resistive state. The current on the bit line and through the memory cell is dependent upon the resistance of the memory element and thus the data value stored. Thus, the data value stored in the memory cell may be determined by detecting whether the resistance of the memory cell corresponds to the high resistance state302or low resistance state300, for example by comparison of a voltage or current on the corresponding bit line with a suitable voltage or current corresponding to RSAby sense amplifiers of sense circuitry212.

In a refresh mode of the memory array212, the control circuitry in controller234executes a procedure described in more detail below.

Reference Array

The reference array250stores a predetermined data set consisting of the memory cells of the array250written to high and low resistance states312and310. As can be seen inFIG. 3, the distribution312for the “partial reset” state312for the reference array250has a minimum resistance R2REFless than the minimum resistance R2of the distribution302for the reset, high resistance state for the memory array212.

As discussed below, changes over time in the data set stored in the reference array250caused by bit errors in the memory cells of the reference array250are used to determine when to perform a refresh operation on both the memory array212and reference array250.

The write mode to store the predetermined data set in the reference array250includes set and partial reset operations for the phase change memory cells. The predetermined data set stored in the reference array250in the illustrated embodiment is a checkerboard pattern of alternating high and low resistance states between adjacent memory cells in the reference array250. Alternatively, other techniques can be used for the arrangement of high and low resistance states for the memory cells in the reference array250for the data set.

In biasing arrangements for a partial reset operation for a memory cell in the reference array250, word line decoder214facilitates providing a word line with a suitable voltage pulse to turn on the access transistor of the memory cell. Bit line decoder218facilitates supplying a voltage pulse to a bit line of suitable amplitude and duration to induce a current to flow through the memory element, the current raising the temperature of the active region of the memory element above the transition temperature of the phase change material and also above the melting temperature to place the active region in a liquid state. The current is then terminated, for example by terminating the voltages on the bit line and word line, resulting in a relatively quick quenching time as the active region cools, thereby setting the phase change material to a resistance within a resistive value associated with the reference array higher resistance partial reset state312as shown inFIG. 3.

Resistances in the distribution312for the partial reset state for the memory cells in the reference array250are achieved by causing the active region of the phase change memory elements of the memory cells of the reference array250to have a different mixture of crystalline and amorphous phase material, and/or a smaller active region size, than the phase change memory elements of the memory cells of the memory array212in the reset state.

For example, in a reset operation of a memory cell in the memory array212a first reset pulse adapted to achieve the full reset state represented by the distribution302may be applied, and in a reset operation of a memory cell in the reference array250a second reset pulse adapted to achieve the partial reset state as represented by distribution312may be applied, the first and second reset pulses having different values for at least one of pulse width, pulse height and shape of the trailing edge of the pulse. To achieve the different distributions302,312for the reset and partial reset states, the second reset pulse may have for example a smaller pulse width and/or a longer pulse tail to provide slower quenching time than that of the first reset pulse.

Alternatively, the reset pulses having the same pulse shapes may be applied to both the memory array212and reference array250, and the different distributions302and312for the reset and partial reset states may be achieved by differences in the cell structures of the arrays212,250, such as providing features in the cells to obtain different amounts of current density and thus resulting in differences in resistance.

In biasing arrangements for a set (program) operation for a memory cell in the reference array250, word line decoder214facilitates providing a word line with a suitable voltage pulse to turn on the access transistor of the memory cell. Bit line decoder224facilitates supplying a voltage pulse to a bit line of suitable amplitude and duration to induce a current to flow through the memory element, the current sufficient to raise the temperature of the active region above the transition temperature and cause a transition of at least a portion of the active region from the amorphous phase into the crystalline phase, this transition lowering the resistance of the memory element and setting the resistance of the phase change material within a resistive value range associated with the reference array lower resistance set state310.

In the illustrated embodiment the reference array lower resistance set state310and the memory array lower resistance set state300correspond to the same resistive value range. Alternatively, the states300and310may correspond to different resistive value ranges.

The difference between the highest resistance R1of the reference array lower resistance set state310and the lower resistance R2REFof the reference array higher resistance reset state312defines a reference array read margin315used to distinguish cells of the reference array250in the lower resistance set state310from those in the higher resistance partial reset state312.

In a read mode of the reference array250the resistance state of the memory cells are read, and bit errors due to changes in the resistance over time are used to determine when to perform a refresh operation on the memory array212.

In a read operation for a memory cell in the reference array250, word line decoder214facilitates providing a word line with a suitable voltage pulse to turn on the access transistor of the memory cell. Bit line decoder218facilitates supplying a voltage pulse to a bit line of suitable amplitude and duration to induce a current to flow through the memory element that does not result in the memory element undergoing a change in resistive state. The current on the bit line and through the memory cell is dependent upon the resistance of the memory element and thus the data value stored. Thus, the data value stored in the memory cell may be determined by detecting whether the resistance of the memory cell corresponds to the high resistance state302or low resistance state300, for example by comparison of a voltage or current on the corresponding bit line with a suitable voltage or current corresponding to RSAby sense amplifiers of sense circuitry212.

FIG. 4illustrates an embodiment of sense circuitry224for the integrated circuit210, which can be used to determine if the data set in the reference array250is different from the expected predetermined data set, and if so to generate a refresh command signal to the controller234which initiates the refresh operation process of the memory array212and reference array250.

InFIG. 4the reference array250is coupled by bit lines220through bit line decoder218to an input of sense amplifier410. An RSAreference source420is coupled to the other input of the sense amplifier410, and a sense enable signal SEN is coupled to the sense amplifier410. During a read operation of a memory cell of the reference array250, the sense amplifier410is responsive to the difference at its inputs to generate an output signal indicating the resistive state of the memory element and thus indicating the data value stored in the memory cell. The output signal of the sense amplifier410is provided to checksum generator430.

During the read process of the reference array250, the checksum generator430computes a checksum435using the data values of the data set read from the memory cells of the reference array250, and supplies the computed checksum435to comparator440.

The checksum generator430may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the checksum generator430comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the checksum generator430

The circuitry224also includes a register400storing a parameter405which represents the predetermined data set for the reference array, and provides this parameter405to the comparator440as part of the process described below. In the illustrated embodiment the parameter405is the expected checksum405which corresponds to the predetermined data set.

The comparator440compares the computed checksum435and the expected checksum405, and generates a refresh command signal REFRESH CMD450if the computed checksum435and the expected checksum are different405. The controller234is responsive to the refresh command signal REFRESH CMD450to then perform a refresh operation of the memory array212and the reference array250.

FIG. 5is an embodiment of a process500which can be executed by the controller234using the circuitry234ofFIG. 4to determine when to perform a refresh operation of the memory array212and the reference array250.

InFIG. 5, the process500is executed upon receiving a refresh check command. Until the refresh check command is received, the process loops in blocks510and520.

Upon receiving the refresh check command (block520), the controller234causes a read process of the data set stored in the reference array250using the sense amplifiers of block410, and causes the computation of the checksum435from the stored data set by the checksum generator430of the sense circuitry224(block530).

Next, the computed checksum435and the expected checksum405stored in the register400are compared by comparator440(block540). If the expected checksum405and the computed checksum435match at block540, then the data stored in reference array250is determined to correspond to the predetermined data set and a refresh operation is not required. The process500loops back to block510to await another refresh check command.

It the expected checksum405and the computed checksum435do not match at block540, then the reference array250has bit errors and the comparator440generates the refresh command signal REFRESH CMD450. The process500the continues to block550.

At block550, the controller234is responsive to the REFRESH CMD450to cause a refresh operation to be performed on the memory array212and the reference array250. The controller234causes the application of appropriate read bias arrangements to read the resistance of the memory cells, and if necessary causes the application of appropriate bias arrangements to refresh the resistance of the corresponding memory elements to offset any change in resistance that may have occurred between refresh cycles.

Alternative techniques for determining bit errors in the reference array250may also be used. For example, in embodiments in which the reference array250stores a checkerboard pattern, bit errors may be determined by detecting consecutive memory cells having the same resistance state using logic circuitry.

FIG. 6is an example top view layout showing the relative sizes and locations of the reference array250and memory array212. Alternatively, the relative sizes and locations of the arrays250,212may be different.

FIG. 7illustrates a schematic diagram of an embodiment of a portion of respective memory cells of the memory array212and the reference array250. In the illustrated embodiment the memory array212and the reference array250share the bit lines220. Alternatively, other configurations may be used, such as sharing the word lines216.

The memory array212includes memory cells701,702,703,704having respective memory elements711,712,713,714. The reference array250includes memory cells721,722,723,724having respective memory elements721,722,723,724.

The arrays212,250include a plurality of word lines216including word lines216a,216b,216c,216dextending in parallel in a first direction, and a plurality of bit lines220including bit lines220a,220bextending in parallel in a second direction perpendicular to the first direction.

Sources of each of the four access transistors illustrated in the memory array212are connected in common to source line796athat terminates in a source line termination circuit795, such as a ground terminal. In another embodiment the sources of the access devices are not electrically connects, but independently controllable.

Sources of each of the four access transistors illustrated in the reference array250are connected in common to source line796bthat terminates in a source line termination circuit795.

The source line termination circuit795may include bias circuits such as voltage and current sources, and decoding circuits for applying bias arrangements other than ground to the source lines796in some embodiments.

Reading or writing to the memory cells of the arrays212,250can be achieved by applying appropriate bias arrangements discussed above. The memory cells of the arrays212,250are distinguished by their address to determine the characteristics of the signals sent by the controller234to couple the bias circuitry to apply pulses to operate the memory cells of the arrays212,250.

To achieve the different high resistance states302and312for the memory array212and reference array250, the active regions of the phase change memory elements of the memory cells of the reference array250have a different mixture of crystalline and amorphous phase material, or a smaller active region, than phase change memory elements of the memory cells of the memory array212in the reset state302.

For example, to achieve the different high resistance states302and312for the memory array212and reference array250, in a reset operation of a memory cell in the memory array212a first reset pulse may be applied, and in a reset operation of a memory cell in the reference array250a second reset pulse may be applied, the first and second reset pulses having different values for at least one of pulse width, pulse height, and shape of the trailing edge of the pulse.

Alternatively, reset pulses having the same pulse shapes may be applied to both the memory array212and reference array250, and the different distributions302and312for the reset and set states may be achieved by differences in the cell structures of the arrays212,250, such as providing features in the cells to obtain different amounts of current density and thus resulting in differences in resistance.

The predetermined data set stored in the reference array250in the illustrated embodiment is a checkerboard pattern of alternating high and low resistance states between adjacent memory cells in the reference array250. Thus, in the illustrated embodiment the memory elements731,734are programmed to the set state310, and the memory elements732,733are programmed to the partial reset state312.

It will be understood that the memory array212and reference array250are not limited to the array configuration illustrated inFIG. 7, and other array configurations can also be used including implementing different configurations for each of the arrays212and250.

In the illustrated embodiment ofFIG. 7, the memory array212and reference array250include field effect transistor access devices. Alternatively, other access devices such as diodes or bipolar junction transistors may be used, including using different types of access devices for the two arrays212,250.

In the embodiments described above, the reference array250and the memory array212are arranged at different locations within a single memory array to share common control circuitry and bias circuitry. Alternatively, the reference array250and the memory array212may be arranged in separate arrays, and may also each have separate control circuitry and bias circuitry.

In some embodiments the memory cells of the reference array250and the memory cells of the memory array212have memory elements with the same physical configuration. Alternatively, the memory cells of the arrays250,212may comprise various types of memory elements having different physical configurations.

FIGS. 8A-8Eshow representative prior art memory cell structures which may be implemented in the memory cells of the arrays250,212.

FIG. 8Ais a simplified cross-sectional view illustrating a first configuration for memory element820coupled to first and second electrodes812,814. The first electrode812may, for example, be coupled to a terminal of an access device such as a diode or transistor, while the second electrode814may be coupled to a bit line.

A dielectric spacer813having a width815separates the first and second electrodes812,814. The phase change material of memory element920extends across the dielectric spacer813and contacts the first and second electrodes812,814, thereby defining an inter-electrode path between the first and second electrodes812,814having a path length defined by the width815of the dielectric spacer813. In operation, as current passes between the first and second electrodes812,814and through the memory element920, the active region818of the phase change material of the memory element920heats up more quickly than the remainder of the memory element920.

FIG. 8Bis a simplified cross-sectional view illustrating a second configuration for memory element920coupled to first and second electrodes822,824. The phase change material of the memory element920has an active region828and contacts the first and second electrodes822,824at top and bottom surfaces823,829respectively. The memory element920has a width821the same as that of the first and second electrodes822,824.

FIG. 8Cis a simplified cross-sectional view illustrating a third configuration for memory element920coupled to first and second electrodes832,834, the phase change material of memory element920having an active region838. The first and second electrodes832,834are separated by dielectric spacer835. The first and second electrodes832,834and the dielectric spacer835have a sidewall surface831. The phase change material of memory element920is on the sidewall surface831and extends across the dielectric spacer835to contact the first and second electrodes832,834.

FIG. 8Dis a simplified cross-sectional view illustrating a fourth configuration for memory element920coupled to first and second electrodes842,844. The phase change material of memory element920has an active region848and contacts the first and second electrodes842,844at top and bottom surfaces843,849respectively. The memory element920has a width841less than that of the first and second electrodes842,844.

FIG. 8Eis a simplified cross-sectional view illustrating a fifth configuration for memory element920coupled to first and second electrodes854,852. The first electrode854has a width851less than width853of the second electrode852and memory element920. Because of the difference between width851and width853, in operation the current density in the phase change material of memory element920is largest in the region adjacent the first electrode854, resulting in the active region858having a “mushroom” shape as shown in the Figure.

Embodiments of the memory cells described herein include phase change based memory materials, including chalcogenide based materials and other materials, for the programmable resistance memory elements. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VIA of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IVA of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky U.S. Pat. No. 5,687,112, cols. 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4and GeSb4Te7(Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.

Chalcogenides and other phase change materials are doped with impurities in some embodiments to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, e.g., U.S. Pat. No. 6,800,504, and U.S. Patent Application Publication No. U.S. 2005/0029502.

Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ge2Sb2Te5.

Other programmable resistive memory materials may be used in other embodiments of the invention, including other materials that use different crystal phase changes to determine resistance, or other memory materials that use an electrical pulse to change the resistance state. Examples include materials for use in resistance random access memory (RRAM) such as metal-oxides including tungsten-oxide (WOx), NiO, Nb2O5, CuO2, Ta2O5, Al2O3, CoO, Fe2O3, HfO2, TiO2, SrTiO3, SrZrO3, (BaSr)TiO3. Additional examples include materials for use in magnetoresistance random access memory (MRAM) such as spin-torque-transfer (STT) MRAM, for example at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O5, NiOFe2O3, MgOFe2, EuO, and Y3Fe5O12. See, for example, US Publication No 2007/0176251 entitled “Magnetic Memory Device and Method of Fabricating the Same”, which is incorporated by reference herein. Additional examples include solid electrolyte materials used for programmable-metallization-cell (PMC) memory, or nano-ionic memory, such as silver-doped germanium sulfide electrolytes and copper-doped germanium sulfide electrolytes. See, for example, N. E. Gilbert et al., “A macro model of programmable metallization cell devices,” Solid-State Electronics 49 (2005) 1813-1819, which is incorporated by reference herein.

An exemplary method for forming chalcogenide material uses PVD-sputtering or magnetron-sputtering method with source gas(es) of Ar, N2, and/or He, etc. at the pressure of 1 mTorr˜100 mTorr. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimater can be used simultaneously. An exemplary method for forming chalcogenide material using chemical vapor deposition (CVD) is disclosed in US Publication No 2006/0172067 entitled “Chemical Vapor Deposition of Chalcogenide Materials”, which is incorporated by reference herein. Another exemplary method for forming chalcogenide material using CVD is disclosed in Lee, et al., “Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50 nm Generation, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 102-103.

A post-deposition annealing treatment in a vacuum or in an N2 ambient is optionally performed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges from 100° C. to 400° C. with an anneal time of less than 30 minutes.