PCB having embedded IC and method for manufacturing the same

A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit.

CLAIM OF PRIORITY

This application claims the benefit of the earlier filing date, pursuant to 35 USC 119(a), to that patent application entitled “PCB Having Embedded IC And Method For Manufacturing The Same,” filed in the Korean Intellectual Property Office on May 4, 2007 and assigned Serial No. 2007-43755, the contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-layer printed circuit board (multi-layer PCB), and more particularly to a PCB having an embedded integrated circuit (IC) and method for manufacturing the same.

2. Description of the Related Art

A printed circuit board (PCB) has been employed in various electric appliances. Particularly, a multi-layer PCB having a structure including insulating layers and conductive patterns layer repeatedly and alternately stacked on each other has been applied to electric appliances of super-slimness/super-small size, such as a portable terminal, a desktop computer, etc.

FIG. 1is a view illustrating a multi-layer PCB according to the conventional art.

As shown inFIG. 1, the conventional multi-layer PCB has a structure including a plurality of insulating layers30˜34and a plurality of conductive pattern layers40˜45alternately stacked, and a plurality of contact-holes (via holes)50formed in the insulating layers30˜34, and an integrated embedded circuit board10. The integrated circuit10is disposed in an interior of a core insulating layer30among the insulating layers30˜34, and has a plurality of bumps11for electric connection to external devices, and an insulating layer12on a surface thereof.

However, the conventional multi-layer PCB has only one embedded integrated circuit, and cannot have a plurality of embedded integrated circuits.

FIG. 2is a view illustrating a multi-layer PCB according to the conventional art. The multi-layer PCB has two integrated circuits10and20arranged side by side, which are embedded in a core insulating layer30.

However, the conventional multi-layer PCB as shown inFIG. 2has two integrated circuits arranged side by side so that there is a disadvantage in that the whole size (area) thereof is too large.

FIG. 3is a view illustrating a conventional multi-layer PCB according to the conventional art. Two PCBs are manufactured, which have core insulating layers30and30-1having embedded printed circuits10and20, respectively, and then the two core insulating layers are again manufactured as one PCB through a lamination process.

However, the conventional multi-layer PCB as shown inFIG. 3uses two core insulating layers and has an insulating layer interposed between them so as to connect the two core insulating layers with each other. Therefore, there is a disadvantage in that the whole thickness of the multi-layer PCB is too thick.

SUMMARY OF THE INVENTION

The present invention provides a PCB having an embedded integrated circuit, which can realize size-reduction as well as slimness of the PCB when more than two integrated circuits are embedded therein.

Also, the present invention provides a PCB having an embedded integrated circuit, which can realize size-reduction as well as slimness of the PCB when more than two integrated circuits are embedded therein.

In accordance with an aspect of the present invention, a multi-layer PCB includes: a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-holes formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit. The multi-layer PCB further includes a conductive pattern layer disposed between a lower surface of the first integrated circuit and a lower surface of the second integrated circuit. The first insulating layer is a core insulating layer.

In accordance with another aspect of the present invention, a method of manufacturing a multi-layer PCB, includes forming a first conductive pattern layer and a second conductive pattern layer on upper and lower surfaces of a first insulating layer, respectively, forming a first hole for receiving a first integrated circuit in the first insulating layer by removing the first conductive pattern layer of a predetermined area for receiving the first integrated circuit and the first insulating layer; arranging the first integrated circuit in the first hole in such a manner that a lower surface of the first integrated circuit makes contact with the second conductive pattern layer; stacking a second insulating layer and a third conductive pattern layer on the first conductive pattern layer and an upper surface of the first integrated circuit; attaching an adhesive tape on the second conductive pattern layer of a predetermined area for receiving a second integrated circuit; stacking a third insulating layer and a fourth conductive pattern layer on the second conductive pattern layer including the adhesive tape; cutting the fourth conductive pattern layer and the third insulating layer along a rim of the adhesive tape; forming a second hole for receiving the second integrated circuit in the third insulating layer by removing the adhesive tape, the third insulating layer formed on the adhesive tape, and the fourth conductive pattern layer; arranging the second integrated circuit in the second hole in such a manner that a lower surface of the second integrated circuit makes contact with the second conductive pattern layer; stacking a fourth insulating layer and a fifth conductive pattern layer on the fourth conductive pattern layer and an upper surface of the second integrated circuit; and forming a plurality of contact-holes in the second insulating layer and the fourth insulating layer so as to allow inter-layer electric connection.

The core insulating layer may be material of FR4, and the second to fourth insulating layers may be made from an ajinomoto build-up film (ABF).

The method of manufacturing a multi-layer PCB further includes: stacking a fifth insulating layer, a sixth insulating layer, a sixth conductive pattern layer, and a seventh conductive pattern layer on a lower part of the second insulating layer and an upper part of the fourth insulating layer; and forming a plurality of contact-holes in the fifth insulating layer and the sixth insulating layer so as to allow inter-layer electric connection.

In accordance with another aspect of the present invention, a method of manufacturing a multi-layer PCB includes the steps of: forming a first conductive pattern layer on an upper surface of a first insulating layer, and then forming a first hole for receiving a first integrated circuit on the first insulating layer by removing the first conductive pattern layer of a predetermined area for receiving the first integrated circuit and the first insulating layer; attaching a first adhesive tape having a size equal to a size of a predetermined area for receiving a second integrated circuit on a lower surface of the first insulating layer so as to block off the first hole; arranging the first integrated circuit in the first hole in such a manner that a lower surface of the first integrated circuit is attached to the first adhesive tape; stacking a second insulating layer and a third conductive pattern layer on the first conductive pattern layer and an upper surface of the first integrated circuit; stacking a third insulating layer and a third conductive pattern layer on the second conductive pattern layer including the first adhesive tape; cutting the third conductive pattern layer and the second insulating layer along a rim of the first adhesive tape; forming a second hole for receiving the second integrated circuit in the third insulating layer by removing the first adhesive tape, the third insulating layer formed on the first adhesive tape, and the third conductive pattern layer; arranging the second integrated circuit in the second hole in such a manner that a lower surface of the second integrated circuit makes contact with a lower surface of the first integrated circuit; stacking a fourth insulating layer and a fourth conductive pattern layer on the third conductive pattern layer and an upper surface of the second integrated circuit; and forming a plurality of contact-holes in the second insulating layer and the fourth insulating layer so as to allow inter-layer electric connection.

The method of manufacturing a multi-layer PCB further includes: stacking a fifth insulating layer, a sixth insulating layer, a fifth conductive pattern layer, and a sixth conductive pattern layer on a lower part of the second insulating layer and an upper part of the fourth insulating layer; and forming a plurality of contact-holes in the fifth insulating layer and the sixth insulating layer so as to allow inter-layer electric connection.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention are now described with reference to the accompanying drawings. For the purposes of clarity and simplicity, a detailed description of known functions and configurations incorporated herein will be omitted as it may make the subject matter of the present invention rather unclear.

FIG. 4is a sectional view illustrating the construction of a multi-layer PCB100according to one embodiment of the present invention.

Referring toFIG. 4, the multi-layer PCB100according to the present embodiment has a structure including a plurality of insulating layers130˜135and a plurality of conductive pattern layers140˜146alternatively stacked and two insulating layers130and132adjacent to each other among the insulating layers130˜135having integrated circuits110and120which are embedded (laid, received) therein, respectively. Also, the insulating layers130˜135have a plurality of contact-holes (via holes160) for allowing inter-layer electric connection, and two conductive pattern layers adjacent to each other are electrically connected with each other through the contact-holes.

The integrated circuits110and120have a plurality of connection bumps111and121for electric connection to external devices and insulating layers112and122formed on an upper surface thereof. The integrated circuits110and120are stacked while having a conductive pattern layer141formed between them. At this time, the integrated circuits110and120are arranged in such a manner that rear surfaces (the other surfaces) of the respective integrated circuits face each other.

In the multi-layer PCB100according to the present embodiment, two insulating layers130and132, which have embedded integrated circuits110and120, respectively, are stacked adjacently to each other while having a conductive pattern layer141disposed between them. Therefore, the multi-layer PCB100can have a smaller thickness in comparison with a structure including two core insulating layers stacked while having a conventional conductive layer disposed between them.

FIGS. 5A to 5Lare views illustrating a process of manufacturing the above-described multi-layer PCB ofFIG. 4.

FIG. 5Ashows a process of coating conductive pattern layers140and141on upper and lower surfaces of a core insulating layer130. For example, a core insulating layer130having material of FR4 is prepared, the upper and lower surfaces of the core insulating layer130are coated by a copper foil, and then the copper foil is patterned through a typical photolithography process. Accordingly, the first and second conductive pattern layers140and141can be formed. The conductive pattern layers may be made of metal material such as tin, chromium, titan, nickel, zinc, cobalt, gold, etc. as well as copper.

FIG. 5Bshows a process of forming a hole110afor receiving the first integrated circuit on the core insulating layer130. The hole110acan be formed by perforating the first conductive pattern layer140coated on the upper surface of the core insulating layer (the first insulating layer)130and the core insulating layer130through a typical drilling process. The hole110ahas a plan equal to the plan of an integrated circuit received therein, and has a size larger than the integrated circuit.

FIG. 5Cshows a process of arranging the first integrated circuit110in the hole in such a manner that a lower surface (rear surface) of the first integrated circuit110makes contact with the second conductive pattern layer141. The first integrated circuit110has a plurality of connection bumps111for electric connection to external devices and an insulating layer112, which are disposed on the upper surface thereof.

FIG. 5Dshows a process of building-up the second insulating layer131and the third conductive pattern layer142on the whole upper surface of the first integrated circuit110after arranging the first integrated circuit110in the hole. The second insulating layer131can be formed through a typical lamination process, for example, through deposition of an insulating layer made from an ajinomoto build-up film (ABF). The third conductive pattern layer142is coated by a copper foil and then can be patterned through a typical photolithography process, similar to the first and second conductive pattern layers140and141.

FIG. 5Eshows a process of attaching an adhesive tape150on the second conductive pattern layer141making contact with the lower surface of the first integrated circuit110. The adhesive tape150is used to make it easier to form a hole for receiving the second integrated circuit in a subsequent process. Therefore, the adhesive tape150is attached while having a size large enough to receive the second integrated circuit. The adhesive tape150can be easily attached or detached as necessary.

FIG. 5Fshows a process of building-up the third insulating layer132and the fourth conductive pattern layer143on the upper surface of the second conductive pattern layer141including an upper part of the adhesive tape150.

The third insulating layer132can be formed through a typical lamination process, for example, through deposition of an insulating layer made from an ajinomoto build-up film (ABF). The third conductive pattern layer142is coated by a copper foil, and then can be patterned through a typical photolithography process, similar to the first and second conductive pattern layers140and141.

FIG. 5Gshows a process of cutting a rim (edge) of the second hole120awhen forming the second hole120afor receiving the second integrated circuit on the third insulating layer132. The rim of the second hole120acan be cut by perforating the fourth conductive pattern layer143and the third insulating layer132through a typical drilling process.

FIG. 5Hshows a process of forming the second hole120afor receiving the second integrated circuit in the third insulating layer132by removing the adhesive tape150, the third insulating layer132formed on the adhesive tape150, and the fourth conductive pattern layer143. By taking off the adhesive tape150, the third insulating layer132and the fourth conductive pattern layer143, which are disposed at the upper part of the adhesive tape150, can be simultaneously removed. Accordingly, the second hole120acan be easily formed. The second hole120ahas a plan equal to the plan of an integrated circuit received therein, and has a size larger than that of the integrated circuit.

FIG. 5Ishows a process of arranging the second integrated circuit120in the second hole120ain such a manner that the lower surface (rear surface) of the second integrated circuit120makes contact with the second conductive pattern layer141. The second integrated circuit120has a plurality of connection bumps121for electric connection to external devices and an insulating layer122on an upper surface thereof.

FIG. 5Jshows a process of arranging the second integrated circuit120in the hole, and then building-up the fourth insulating layer133and the fifth conductive pattern layer144on the upper part of the second integrated circuit120. The fourth insulating layer133can be formed through a typical lamination process, for example, through deposition of an insulating layer made from an ajinomoto build-up film (ABF). The fifth conductive pattern layer144is coated by a copper foil, and then can be patterned through a typical photolithography process, in a manner similar to that of the first to fourth conductive pattern layers140˜143.

FIG. 5Kshows a process of forming a plurality of contact-holes160for allowing inter-layer electric connection in the second insulating layer131and the fourth insulating layer133. For example, the contact-hole160can be formed through a photolithography process. The photolithography process includes a process of applying photoresist (not shown) on the third and fifth conductive pattern layers142and144, a process of exposing a predetermined contact-hole forming area by using a mask so as to allow a photoresist pattern to be engraved thereon, a process of developing the exposed area, and process of etching the third and fifth conductive pattern layers142and144and the second and fourth insulating layers131and133by using the remaining photoresist.

FIG. 5Lshows a process of building-up the fifth and sixth insulating layers134and135, and the sixth and seventh conductive pattern layers145and146on the lower part of the second insulating layer131and the upper part of the fourth insulating layer133, and then forming a plurality of contact-holes160for allowing inter-layer electric connection in the fifth insulating layer134and the sixth insulating layer135. The fifth and sixth insulating layers134and135can be formed by depositing an insulating layer through a typical lamination process (e.g., an ajinomoto build-up film (ABF), in a manner similar to that of the second to fourth insulating layers131˜133. The sixth and seventh conductive pattern layers145and146are coated by a copper foil, and then can be patterned through a typical photolithography process, as the first to fifth conductive pattern layers140˜144are.

FIG. 6is a sectional view illustrating the construction of a multi-layer PCB200according to another embodiment of the present invention.

Referring toFIG. 6, the multi-layer PCB200according to the present embodiment has a structure including a plurality of insulating of layers230˜235and a plurality of conductive pattern layers240˜245alternatively stacked, and includes an insulating mono-layer having two integrated circuits210and220embedded (laid, received) therein. Also, a plurality of insulating layers230˜235have a plurality of contact-holes (via holes260) for allowing inter-layer electric connection, and two conductive pattern layers adjacent to each other are electrically connected with each other through the contact-holes.

The integrated circuits210and220have a plurality of connection bumps211and221for electric connection to external devices and insulating layers212and222, which are formed on an upper surface thereof. The integrated circuits210and220are stacked in such a manner that rear surfaces (surfaces of the other side) of the respective integrated circuits make contact with each other.

In the multi-layer PCB200according to the present embodiment, two integrated circuits210and220are stacked in such a manner that their rear surfaces make contact with each other so that they are arranged in an insulating mono-layer (referred to as an insulating mono-layer because a conductive pattern layer isn't interposed between the insulating layers230and232and two insulating layers make contact with each other). Therefore, the multi-layer PCB200has a smaller thickness in comparison with a conventional structure including an integrated circuit arranged in two core insulating layers and an insulating layer interposed between the two layers.

FIGS. 7A to 7Mare views illustrating a method for manufacturing the above-described multi-layer PCB as shown inFIG. 6.

FIG. 7Ashows a process of coating a conductive pattern layer240on an upper surface of a core insulating layer (the first insulating layer)230. For example, a core insulating layer230having material of FR4 is prepared, an upper surface of the core insulating layer230is coated by a copper foil, and then the copper foil is patterned through a typical photolithography process. Accordingly, the first conductive pattern layer240can be formed.

FIG. 7Bshows a process for forming a hole210afor receiving the first integrated circuit on the core insulating layer230, and then attaching the first adhesive tape250for supporting the integrated circuit on a lower surface of the core insulating layer230. The hole210acan be formed by perforating the first conductive pattern layer240coated on the upper surface of the core insulating layer (the first insulating layer)230and the core insulating layer230through a typical drilling process. The hole210ahas a plan equal to a plan of an integrated circuit received therein, and has a size larger than the integrated circuit. The lower part of the hole210ais blocked off by the first adhesive tape250, and the first adhesive tape250can be easily attached or detached as necessary.

FIG. 7Cshows a process of arranging the first integrated circuit210in the hole in such a manner that the lower surface (rear surface) of the first integrated circuit210makes contact with the first adhesive tape250. The first integrated circuit210has a plurality of connection bumps211for electric connection to external devices and an insulating layer212on an upper surface thereof.

FIG. 7Dshows a process of arranging the first integrated circuit210in the hole, and then building-up the second insulating layer231and the second conductive pattern layer241on whole upper part of the first integrated circuit210. The second insulating layer231can be formed through a typical lamination process, for example, through deposition of an insulating layer made from an ajinomoto build-up film (ABF). The second conductive pattern layer141is coated by a copper foil, and then can be patterned through a typical photolithography process, similarly to the first conductive pattern layer140.

FIG. 7Eis a process of removing the first adhesive tape250attached on the lower part of the core insulating layer230.

FIG. 7Fis a process of attaching the second adhesive tape251on the lower surface of the first integrated circuit210and a part of the core insulating layer230. The second adhesive tape251is used to make it easier to form a hole for receiving the second integrated circuit to be formed in a subsequent process. The second adhesive tape251is attached while having a size large enough to receive the second integrated circuit. The second adhesive tape251can be easily attached or detached. Meanwhile, in the present embodiment, the first adhesive tape250is attached to the whole lower surface of the core insulating layer230in step7b, and then the first integrated circuit210is arranged on the first adhesive tape250. Then, the first adhesive tape250is removed in the step7e, and then the second adhesive tape251is again attached in step7f. However, if the core insulating layer and the integrated circuit can be stably fixed, the process of attaching or detaching the first adhesive tape can be omitted, and the second adhesive tape used in order to form a hole for receiving the second integrated circuit can be directly attached.

FIG. 7Gshows a process of building-up the third insulating layer232and the third conductive pattern layer242on whole upper surface of the core insulating layer230, including an upper part of the second adhesive tape251. The third insulating layer232can be formed through a typical lamination process such as an ajinomoto build-up film (ABF) process. The third conductive pattern layer242is coated by a copper foil, and then can be patterned through a typical photolithography process, similar to the first and second conductive pattern layers240and241.

FIG. 7Hshows a process of cutting a rim (edge) of the hole220afor forming the second hole220afor receiving the second integrated circuit on the third insulating layer232. The rim of the second hole220acan be cut by perforating the third conductive pattern layer242of an edge of the second adhesive tape251and the third insulating layer232through a typical drilling process. The hole110ahas a plan equal to the plan of an integrated circuit received therein, and has a size larger than the integrated circuit.

FIG. 7Iillustrates a process of forming a hole220afor receiving the second integrated circuit on the third insulating layer232by removing the second adhesive tape251the third insulating layer232formed on the second adhesive tape251, and the third conductive pattern layer242. By taking off the adhesive tape251, the third insulating layer232and the third conductive pattern layer242can be simultaneously removed. Accordingly, the second hole220acan be easily formed. The hole210ahas a plan equal to the plan of an integrated circuit received therein, and has a size larger than the integrated circuit.

FIG. 7Jshows a process of arranging the second integrated circuit220in the second hole in such a manner that the lower surface (rear surface) of the second integrated circuit220makes contact with the lower surface of the first integrated circuit210and the core insulating layer230. The second integrated circuit220has a plurality of connection bumps221for electric connection to external devices and an insulating layer222on an upper surface thereof.

FIG. 7Kshows a process of building-up the fourth insulating layer233and the fourth conductive pattern layer243on the upper part of the second integrated circuit220after arranging the second integrated circuit220in the hole. The fourth insulating layer233can be formed through a typical lamination process, such as an ajinomoto build-up film (ABF). The fourth conductive pattern layer243is coated by a copper foil, and then can be patterned through a typical photolithography process, similar to the first to third conductive pattern layers240˜243.

FIG. 7Lshows a process of forming a plurality of contact-holes260for allowing inter-layer electric connection in the second insulating layer231and the fourth insulating layer233. For example, the contact-hole260can be formed through a photolithography process. The photolithography process includes a process of applying photoresist (not shown) on the second and fourth conductive pattern layers241and243, a process of exposing a predetermined contact-hole forming area by using a mask so as to allow a photoresist pattern to be engraved thereon, a process of developing the exposed part, and process of etching the second and fourth conductive pattern layers241and243and the second and fourth insulating layers231and233by using remaining photoresist.

FIG. 7Mshows a process of building-up the fifth and sixth insulating layers234and235, and the fifth and sixth conductive pattern layers244and245on the lower part of the second insulating layer231and the upper part of the fourth insulating layer233, respectively, and then forming a plurality of contact-holes260for electric connection to external devices in fifth insulating layer234and the sixth insulating layer235. The fifth and sixth insulating layers234and235can be formed through a typical lamination process, for example, an ajinomoto build-up film (ABF), similar to the second to fourth insulating layers231˜233. The fifth and sixth conductive pattern layers244and245are coated by a copper foil and then can be patterned through a typical photolithography process, similar to the first to fourth conductive pattern layers240˜243.

While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the number of embedded integrated circuits, the number or material of insulating layers and conductive pattern layers can be changed as necessary. Accordingly, the scope of the invention is not to be limited by the above-described embodiments but by the claims and the equivalents thereof.

As described above, in the multi-layer PCB according to an embodiment of the present invention, because two insulating layers having an embedded integrated circuit, are stacked adjacently to each other while having a conductive pattern layer disposed between them, the multi-layer PCB can be a smaller thickness thereof in comparison with a conventional structure including two core insulating layers stacked while having a conductive layer disposed between them.

Moreover, in the multi-layer PCB according to another embodiment of the present invention, because two integrated circuits are stacked in such a manner that respective rear surfaces thereof make contact with each other so as to be arranged in an insulating mono-layer, it can be possible to further reduce the thickness of the multi-layer PCB in comparison with a conventional structure where an integrated circuit is arranged in two core insulating layers, and then an insulating layer is interposed between them

Furthermore, in a method for manufacturing a multi-layer PCB according to the present invention, an easily attachable or detachable adhesive tape is attached on the lower part of a predetermined area for receiving an integrated circuit, an insulating layer and a conductive pattern layer are formed thereon, and then the insulating layer formed on the adhesive tape and the conductive pattern layer are removed through a lift-off process. Therefore, a hole for receiving an integrated circuit can be easily formed.