Semiconductor package and method of manufacturing the same

A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0176504, filed on Dec. 27, 2019, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of inventive concepts relate to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including a via structure with improved electrical characteristics and a method of manufacturing the same.

An integrated circuit chip may be realized in the form of a semiconductor package so as to be appropriately applied to an electronic product. In a typical semiconductor package, a semiconductor chip may be mounted on a printed circuit board (PCB) and may be electrically connected to the PCB through bonding wires or bumps. High-performance, high-speed and small electronic components have been increasingly demanded with the development of an electronic industry. Thus, a wafer-level package and a panel-level package are being studied.

SUMMARY

Embodiments of inventive concepts may provide a semiconductor package including a via structure with improved electrical characteristics and reliability and a method of manufacturing the same.

In an embodiment, a method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer provided in the first via hole and covering a top surface of the first encapsulation layer, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer. The semiconductor chip may be electrically connected to the redistribution layer.

In an embodiment, a method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The semiconductor chip may be electrically connected to the redistribution layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer provided in the first via hole and covering a top surface of the first encapsulation layer, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A sidewall of the via structure may have a first surface and a second surface. The first surface of the sidewall of the via structure may be inclined with respect to a top surface of the second substrate. The second surface of the sidewall of the via structure may be inclined with respect to each of the first surface of the sidewall of the via structure and the top surface of the second substrate.

In an embodiment, a semiconductor package may include a lower insulating layer including an under-bump metal layer, a solder ball on a bottom surface of the lower insulating layer and connected to the under-bump metal layer, a first substrate on a top surface of the lower insulating layer and the first substrate including a redistribution layer, a second substrate including a semiconductor chip electrically connected to the redistribution layer and an interconnection layer, the second substrate having a through-hole exposing the redistribution layer in a region surrounding the semiconductor chip, a first encapsulation layer covering the second substrate and having a first via hole, a second encapsulation layer covering the first encapsulation layer and having a second via hole in the first via hole, a via structure filling the second via hole, and an upper insulating layer covering a portion of the via structure and a top surface of the second encapsulation layer. The first encapsulation layer may fill the through-hole. A diameter of the second via hole may be less than a diameter of the first via hole. A sidewall of the via structure may have a first surface and a second surface. The first surface of the sidewall of the via structure may be inclined with respect to a top surface of the second substrate. The second surface of the sidewall of the via structure may be inclined with respect to each of the first surface of the sidewall of the via structure and the top surface of the second substrate.

DETAILED DESCRIPTION

Semiconductor packages and methods of manufacturing the same according to some embodiments of inventive concepts will be described more fully hereinafter with reference to the accompanying drawings.

FIG. 1is a cross-sectional view illustrating a semiconductor package according to some embodiments of inventive concepts.

Referring toFIG. 1, a semiconductor package according to some embodiments of inventive concepts may include a lower insulating layer200, a first substrate300, a second substrate400, a molding layer500, and an upper insulating layer600. The second substrate400may include a semiconductor chip100. The semiconductor package according to some embodiments of inventive concepts may be a fan-out wafer-level package (FOWLP) or a fan-out panel-level package (FOPLP). In some embodiments, the semiconductor package may be one of unit packages obtained by dividing a package structure including a plurality of the semiconductor chips100through a singulation process (e.g., a dicing process using a dicing saw). In certain embodiments, the semiconductor package may have a structure in which fan-out packages are stacked, unlikeFIG. 1.

A solder ball201may be provided on a bottom surface of the lower insulating layer200. The solder ball201may be provided in plurality, and the plurality of solder balls201may be arranged in a first direction D1. For example, the first direction D1may be parallel to a top surface of the lower insulating layer200. Hereinafter, a top surface of a component may be defined as a surface facing a second direction D2, and a bottom surface of the component may be defined as a surface facing a direction opposite to the second direction D2. For example, the top surface of the lower insulating layer200may be a surface facing the semiconductor chip100, and the bottom surface of the lower insulating layer200may be a surface opposite to the top surface. For example, the second direction D2may be perpendicular to the top surface of the lower insulating layer200. In other words, the first direction D1and the second direction D2may be perpendicular to each other. Each of the solder balls201may be electrically connected to an external terminal (e.g., a terminal of a main board of an electronic device). The lower insulating layer200may include an under-bump metal layer203. The under-bump metal layer203may be surrounded by the lower insulating layer200. A width of the under-bump metal layer203in the first direction D1may decrease as a height or level in the second direction D2increases. The under-bump metal layer203may be electrically connected to the first substrate300.

The first substrate300may include at least one or more redistribution layers (RDL). For example, referring toFIG. 1, the first substrate300may include first to third redistribution layers310,330and350. A design of a connection position with the external terminal may be more flexible with the first to third redistribution layers310,330and350. However, embodiments of inventive concepts are not limited thereto. In certain embodiments, the semiconductor package may include a different number of the redistribution layers.

The first redistribution layer310may be provided on the top surface of the lower insulating layer200. In other words, the first redistribution layer310may be disposed between the lower insulating layer200and the second redistribution layer330. The first redistribution layer310may include a first insulating layer311, a first redistribution pattern313, and a first conductive via315. For example, the first redistribution pattern313may be located at a lower level than the top surface of the lower insulating layer200. The first redistribution pattern313may be electrically connected to the under-bump metal layer203. The first conductive via315may be provided on the first redistribution pattern313and may be electrically connected to the first redistribution pattern313. The first conductive via315may be surrounded by the first insulating layer311.

The second redistribution layer330may be provided on a top surface of the first redistribution layer310. In other words, the second redistribution layer330may be disposed between the first redistribution layer310and the third redistribution layer350. The second redistribution layer330may include a second insulating layer331, a second redistribution pattern333, and a second conductive via335. For example, the second redistribution pattern333may be located at a lower level than the top surface of the first redistribution layer310. The second redistribution pattern333may be provided in plurality, and at least one of the plurality of second redistribution patterns333may be electrically connected to the first conductive via315. The second conductive via335may be provided on the second redistribution pattern333and may be electrically connected to the second redistribution pattern333. The second conductive via335may be surrounded by the second insulating layer331.

The third redistribution layer350may be provided on a top surface of the second redistribution layer330. In other words, the third redistribution layer350may be disposed between the second redistribution layer330and the second substrate400. The third redistribution layer350may include a third insulating layer351, a third redistribution pattern353, and a third conductive via355. For example, the third redistribution pattern353may be located at a lower level than the top surface of the second redistribution layer330. The third redistribution pattern353may be provided in plurality, and at least one of the plurality of third redistribution patterns353may be electrically connected to the second conductive via335. The third conductive via355may be provided on the third redistribution pattern353and may be electrically connected to the third redistribution pattern353. The third conductive via355may be surrounded by the third insulating layer351. In addition, the third conductive via355may be provided in plurality, some of the plurality of third conductive vias355may be electrically connected to connection pads110of the semiconductor chip100, and others of the plurality of third conductive vias355may be electrically connected to the second substrate400.

A width of each of the first to third conductive vias315,335and355in the first direction D1may decrease as a height or level in the second direction D2increases. Each of the first to third insulating layers311,331and351may include an insulating material. For example, each of the first to third insulating layers311,331and351may include an inorganic material (e.g., silicon oxide, silicon nitride, and/or silicon oxynitride) and/or a polyamide-based polymer material. The first to third redistribution patterns313,333and353and the first to third conductive vias315,335and355may include a conductive material. The first to third redistribution patterns313,333and353and the first to third conductive vias315,335and355may include, for example, copper (Cu), a copper alloy, or aluminum (Al). Here, the copper alloy may mean an alloy obtained by mixing copper with a very small amount of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Al, or Zr.

In some embodiments, the first to third redistribution patterns313,333and353and the first to third conductive vias315,335and355may be formed through a plurality of damascene processes or dual damascene processes. Even though not shown in the drawings, barrier patterns may be provided between the first to third redistribution patterns313,333and353and the first to third insulating layers311,331and351and between the first to third conductive vias315,335and355and the first to third insulating layers311,331and351, respectively. For example, the barrier patterns may include at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, or WN.

The second substrate400may include the semiconductor chip100and first and second burying layers410and430. However, embodiments of inventive concepts are not limited thereto. In certain embodiments, the semiconductor package may include a different number of the burying layers. The second substrate400may be, for example, an embedded trace substrate (ETS).

For example, the semiconductor chip100may be a logic chip, a memory chip, or an application processor chip. The semiconductor chip100may be disposed in a through-hole TH penetrating the first and second burying layers410and430and may be surrounded by the first and second burying layers410and430, when viewed in a plan view. The semiconductor chip100may be spaced apart from the first and second burying layers410and430with a portion of the through-hole TH interposed therebetween, when viewed in a cross-sectional view. The semiconductor chip100may have a bottom surface100badjacent to the first substrate300, and a top surface100topposite to the bottom surface100b. For example, the bottom surface100bof the semiconductor chip100may be an active surface, and the top surface100tof the semiconductor chip100may be a non-active surface. The connection pad110may be provided on the bottom surface100bof the semiconductor chip100. The connection pad110may be provided in plurality, and the plurality of connection pads110may be arranged in the first direction D1. The number, a pitch and/or arrangement of the connection pads110may be changed depending on the numbers, pitches and/or arrangement of the first to third redistribution patterns313,333and353and the number, a pitch and/or arrangement of the solder balls201. For example, the connection pads110may be arranged more densely than the solder balls201. The semiconductor chip100may be electrically connected to the solder balls201through the connection pads110and the first to third redistribution patterns313,333and353and the first to third conductive vias315,335and355of the first substrate300. In addition, the semiconductor package according to some embodiments of inventive concepts may further include a passivation layer (not shown) covering the bottom surface100bof the semiconductor chip100and a portion of a bottom surface of the connection pad110. In certain embodiments, an interposer and an underfill material may be disposed between the semiconductor chip100and the connection pad110, unlikeFIG. 1.

The first burying layer410may be provided on a portion of a top surface of the third redistribution layer350. In other words, the first burying layer410may be disposed between the first substrate300and the second burying layer430. The first burying layer410may include a first burying insulating layer411, a first conductive pattern413, a first buried via415, and a second conductive pattern417. In some embodiments, the first and second conductive patterns413and417may correspond to interconnection layers. The first conductive pattern413may be provided on the top surface of the third redistribution layer350and may be electrically connected to the third conductive via355. The first buried via415may be provided on the first conductive pattern413. The first buried via415may be surrounded by the first burying insulating layer411. For example, the second conductive pattern417may be located at a higher level than a top surface of the first burying insulating layer411. The first conductive pattern413, the first buried via415and the second conductive pattern417may be electrically connected to each other.

The second burying layer430may be provided on a top surface of the first burying layer410. In other words, the second burying layer430may be disposed between the first burying layer410and the molding layer500. The second burying layer430may include a second burying insulating layer431, a second buried via433, and a third conductive pattern435. In some embodiments, the third conductive pattern435may correspond to an interconnection layer. The second buried via433may be provided on the second conductive pattern417. The second buried via433may be surrounded by the second burying insulating layer431. For example, the third conductive pattern435may be located at a higher level than a top surface of the second burying insulating layer431. The second buried via433and the third conductive pattern435may be electrically connected to each other and may be electrically connected to the first conductive pattern413, the first buried via415, and the second conductive pattern417.

A width of each of the first and second buried vias415and433in the first direction D1may increase as a height or level in the second direction D2increases. The first and second burying insulating layers411and431may include an insulating material. In some embodiments, the first and second burying insulating layers411and431may include substantially the same material as the first to third insulating layers311,331and351of the first substrate300. In certain embodiments, the first and second burying insulating layers411and431may include a different insulating material from those of the first to third insulating layers311,331and351of the first substrate300. For example, the first and second burying insulating layers411and431may include a thermosetting resin (e.g., an epoxy resin), a thermoplastic resin (e.g., polyimide), or an insulating material in which the resin is impregnated into a core material (e.g., an inorganic filler and/or a glass fiber (or glass cloth or glass fabric)), e.g., prepreg, an Ajinomoto build-up film (ABF), FR-4, or bismaleimide triazine (BT). The first conductive pattern413, the first buried via415, the second conductive pattern417, the second buried via433and the third conductive pattern435may include a conductive material. For example, the first conductive pattern413, the first buried via415, the second conductive pattern417, the second buried via433and the third conductive pattern435may include copper (Cu), a copper alloy, or aluminum (Al).

The molding layer500may cover the semiconductor chip100and the second substrate400. In addition, the molding layer500may fill the through-hole TH around the semiconductor chip100. The molding layer500may include a first portion510covering the top surface100tof the semiconductor chip100and a top surface of the second burying layer430and extending in the first direction D1, and a second portion530filling the through-hole TH and extending in the second direction D2. In other words, the semiconductor chip100may be spaced apart from the first and second burying layers410and430with the second portion530of the molding layer500interposed therebetween. For example, the molding layer500may include an insulating polymer (e.g., an epoxy-based polymer) or an Ajinomoto build-up film (ABF).

A via structure VS penetrating the molding layer500may be provided. The via structure VS may include an upper conductive via501and an upper conductive pad503. A width of the upper conductive via501in the first direction D1may increase as a height or level in the second direction D2increases. In other words, a sidewall VSs of the via structure VS may have a gradient with respect to the top surface of the first substrate300and the top surface of the second substrate400. The upper conductive pad503may be provided in plurality, and one or some of the plurality of upper conductive pads503may not be connected to the upper conductive via501. The via structure VS and a method of manufacturing the same will be described in more detail with reference toFIGS. 2 to 11.

The upper insulating layer600may cover the molding layer500and a portion of the upper conductive pad503of the via structure VS. The upper insulating layer600may have an opening601exposing another portion of the upper conductive pad503. A width of the opening601in the first direction D1may increase as a height or level in the second direction D2increases.

A method of manufacturing a semiconductor package according to some embodiments of inventive concepts may include forming a first substrate300including first to third redistribution layers310,330and350, providing a second substrate400including a semiconductor chip100and first to third conductive patterns413,417and435on the first substrate300to electrically connect the semiconductor chip100to the first to third redistribution layers310,330and350of the first substrate300, forming a molding layer500covering the second substrate400, and forming a via structure VS penetrating the molding layer500.

The first substrate300including the first to third redistribution layers310,330and350, the lower insulating layer200including the under-bump metal layer203, and the solder balls201may be formed on a carrier substrate. Thereafter, the carrier substrate may be removed, and the second substrate400including the semiconductor chip100may be formed on the top surface of the first substrate300. In other words, the top surface of the first substrate300may be in contact with the bottom surface100bof the semiconductor chip100.

A process of forming the through-hole TH penetrating the second substrate400may be performed between the process of forming the second substrate400and the process of forming the molding layer500. More particularly, the through-hole TH may penetrate the first and second burying layers410and430adjacent to the semiconductor chip100. The through-hole TH may be formed to surround the semiconductor chip100. Thereafter, the molding layer500may be formed to fill the through-hole TH.

The formation of the via structure VS penetrating the molding layer500will be described later in detail with reference toFIGS. 4 to 10.

FIG. 2is an enlarged view of a portion ‘A’ ofFIG. 1to illustrate a via structure of a semiconductor package according to some embodiments of inventive concepts.

Referring toFIG. 2, the molding layer500and the via structure VS are illustrated. The molding layer500may include a first encapsulation layer ENC1and a second encapsulation layer ENC2. The via structure VS may include the upper conductive via501, the upper conductive pad503, and a seed layer SD.

The first encapsulation layer ENC1may cover the top surface of the second burying insulating layer431and at least a portion of a top surface435tof the third conductive pattern435. The top surface435tof the third conductive pattern435may be substantially flat. In addition, the top surface435tof the third conductive pattern435may be substantially parallel to the top surface of the second burying insulating layer431. A space surrounded by a sidewall ENC1sof the first encapsulation layer ENC1may be defined as a first via hole VH1. The sidewall EN1sof the first encapsulation layer ENC1may have a gradient with respect to the top surface435tof the third conductive pattern435. In other words, a width of the first via hole VH1in the first direction D1may increase as a height or level in the second direction D2increases. The first encapsulation layer ENC1may be an adhesive insulating film. For example, the first encapsulation layer ENC1may include an insulating resin RS and a plurality of fillers FL in the insulating resin RS. The insulating resin RS may include, for example, a polymer material such as epoxy or polyimide. The fillers FL may include, for example, an inorganic material such as silica. The fillers FL may be atypical and may be randomly dispersed in the insulating resin RS. However, embodiments of inventive concepts are not limited thereto. In certain embodiments, the first encapsulation layer ENC1may not include the fillers FL but may include only the insulating resin RS.

The second encapsulation layer ENC2may cover the sidewall ENC1sand a top surface of the first encapsulation layer ENC1. A space surrounded by a sidewall ENC2sof the second encapsulation layer ENC2may be defined as a second via hole VH2. Here, the sidewall ENC2sof the second encapsulation layer ENC2may be a surface which is not in contact with the first encapsulation layer ENC1. At the same level, a diameter of the second via hole VH2may be less than a diameter of the first via hole VH1. The sidewall ENC2sof the second encapsulation layer ENC2may be in contact with the sidewall VSs of the via structure VS. In other words, a profile of the sidewall ENC2sof the second encapsulation layer ENC2may be substantially the same as a profile of the sidewall VSs of the via structure VS. A width W1(W2) of the second encapsulation layer ENC2in the first direction D1may be constant in the first via hole VH1. The width W1(W2) of the second encapsulation layer ENC2in the first direction D1may range from about 5 μm to about 20 μm. InFIG. 2, the width W1, in the first direction D1, of the second encapsulation layer ENC2provided at a left side of the via structure VS may be substantially equal to the width W2, in the first direction D1, of the second encapsulation layer ENC2provided at a right side of the via structure VS. However, the second encapsulation layers ENC2respectively provided at the left and right sides of the via structure VS may be connected to each other to surround the via structure VS, when viewed in a plan view. In addition, under a level of the top surface of the first encapsulation layer ENC1, the width W1or W2of the second encapsulation layer ENC2in the first direction D1may be constant as a level in the second direction D2increases. The second encapsulation layer ENC2may include, for example, a photo-imageable dielectric resin. For example, the second encapsulation layer ENC2may include at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), a phenolic polymer, or a benzocyclobutene-based polymer (BCB).

The seed layer SD may conformally cover the top surface435tof the third conductive pattern435exposed by the second via hole VH2, the sidewall ENC2sof the second encapsulation layer ENC2exposed by the second via hole VH2, and a portion of the top surface of the second encapsulation layer ENC2. The seed layer SD may be spaced apart from the first encapsulation layer ENC1with the second encapsulation layer ENC2interposed therebetween. A space surrounded by a sidewall of the seed layer SD may be defined as a third via hole VH3. Here, the sidewall of the seed layer SD may be a surface which is not in contact with the second encapsulation layer ENC2. A bottom surface of the third via hole VH3may be spaced apart from the top surface435tof the third conductive pattern435in the second direction D2. At the same level, a diameter of the third via hole VH3may be less than the diameter of the second via hole VH2. The seed layer SD may be disposed between the upper conductive via501and the second encapsulation layer ENC2and between the upper conductive pad503and the second encapsulation layer ENC2. The seed layer SD may assist the formation of the upper conductive via501and the upper conductive pad503. For example, the seed layer SD may increase uniformity of plating and may function as initial nucleation sites. For example, the seed layer SD may include at least one of copper (Cu), nickel (Ni), silver (Ag), gold (Au), aluminum (Al), tungsten (W), platinum (Pt), palladium (Pd), or any alloy thereof. In particular, the seed layer SD may include platinum (Pt).

The upper conductive via501and the upper conductive pad503may be provided on the seed layer SD. The upper conductive via501may fill the third via hole VH3. A width of the upper conductive via501in the first direction D1may increase as a height or level in the second direction D2increases. The upper conductive pad503may be provided on the upper conductive via501and the seed layer SD and may extend in the first direction D1. In addition, a portion of the top surface of the upper conductive pad503may be exposed by the opening601of the upper insulating layer600. The upper conductive via501and the upper conductive pad503may include, for example, copper (Cu), a copper alloy, or aluminum (Al).

A profile of the sidewall VSs of the via structure VS will be described hereinafter in detail. The sidewall VSs of the via structure VS may have a first surface S1, a second surface S2, and a third surface S3. More particularly, the first surface S1may be inclined with respect to the top surface435tof the third conductive pattern435. The second surface S2may be inclined with respect to each of the first surface S1and the top surface435tof the third conductive pattern435. An acute angle between the second surface S2and the top surface435tof the third conductive pattern435may be greater than 0 degree. An acute angle between the first surface S1and the top surface435tof the third conductive pattern435may be greater than the acute angle between the second surface S2and the top surface435tof the third conductive pattern435. The third surface S3may be substantially parallel to the top surface435tof the third conductive pattern435and the first direction D1in which the upper conductive pad503extends.

The sidewall VSs of the via structure VS may be spaced apart from the first encapsulation layer ENC1with the second encapsulation layer ENC2interposed therebetween. In the first via hole VH1, a distance between the first surface S1and the first encapsulation layer ENC1in the first direction D1may be equal to the width W1or W2of the second encapsulation layer ENC2in the first direction D1. In other words, the distance between the first surface S1and the first encapsulation layer ENC1in the first direction D1may be constant in the first via hole VH1. In addition, a distance between the third surface S3and the first encapsulation layer ENC1in the second direction D2may be constant. However, a distance between the second surface S2and the first encapsulation layer ENC1may not be constant. For example, a corner of the first encapsulation layer ENC1may be the closest to the second surface S2.

According to the embodiments of inventive concepts, the via structure VS may have the first surface S1and the second surface S2which have different gradients with respect to the top surface435tof the third conductive pattern435, and thus a cross-sectional area of the via structure VS may be increased. As a result, an electrical resistance of the via structure VS may be reduced. In addition, stress may be dispersed at a contact portion of the upper conductive via501and the upper conductive pad503of the via structure VS, and thus it is possible to prevent a crack from occurring at the contact portion. In other words, electrical characteristics and reliability of the semiconductor package may be improved by the via structure VS according to the embodiments of inventive concepts.

The via structure VS according to the embodiments of inventive concepts may be applied to various semiconductor packages having different structures from the structure illustrated inFIGS. 1 and 2. In particular, the via structure VS according to the embodiments of inventive concepts may be variously applied to semiconductor packages using an Ajinomoto build-up film (ABF) as a molding member.

FIG. 3is an enlarged view of a portion ‘B’ ofFIG. 2to illustrate a portion of a via structure of a semiconductor package according to some embodiments of inventive concepts.

Referring toFIG. 3, the sidewall ENC1sof the first encapsulation layer ENC1may be compared with the sidewall ENC2sof the second encapsulation layer ENC2. The sidewall ENC1sof the first encapsulation layer ENC1and the sidewall ENC2sof the second encapsulation layer ENC2may include concave portions DT1and concave portions DT2, respectively. An average depth of the concave portions DT1of the sidewall ENC1sof the first encapsulation layer ENC1may be greater than an average depth of the concave portions DT2of the sidewall ENC2sof the second encapsulation layer ENC2. In addition, at least one of the fillers FL of the first encapsulation layer ENC1may include a protrusion FLp protruding from the sidewall ENC1sof the first encapsulation layer ENC1. Thus, a surface roughness of the sidewall ENC1sof the first encapsulation layer ENC1may be greater than a surface roughness of the sidewall ENC2sof the second encapsulation layer ENC2.

FIGS. 4 to 10are enlarged views corresponding to the portion ‘A’ ofFIG. 1to illustrate a method of manufacturing a via structure of a semiconductor package according to some embodiments of inventive concepts.

Referring toFIG. 4, a first dielectric layer DL1may be formed on the top surface of the second burying insulating layer431and the top surface435tof the third conductive pattern435. The first dielectric layer DL1may completely cover the top surface435tof the third conductive pattern435. For example, the first dielectric layer DL1may include an insulating resin RS and a plurality of fillers FL in the insulating resin RS.

Referring toFIGS. 4 and 5, the first dielectric layer DL1may be processed to form a first encapsulation layer ENC1having a first via hole VH1. The processing of the first dielectric layer DL1may be performed by a laser process. More particularly, the processing of the first dielectric layer DL1may be performed by an etching process such as a drilling process, a laser ablation process, or a laser cutting process. At this time, predetermined alignment algorithm may be used to determine a laser processing position (i.e., a formation position of the first via hole VH1) on the first dielectric layer DL1.

The first via hole VH1may be defined by a portion of the top surface435tof the third conductive pattern435and a sidewall ENC1sof the first encapsulation layer ENC1. The portion of the top surface435tof the third conductive pattern435may be exposed by the first via hole VH1. The sidewall ENC1sof the first encapsulation layer ENC1may have a gradient with respect to the top surface435tof the third conductive pattern435. In other words, a width of the first via hole VH1in the first direction D1may increase as a height or level in the second direction D2increases. The gradient of the sidewall ENC1sof the first encapsulation layer ENC1may be substantially constant. In other words, the first encapsulation layer ENC1may have a single corner at an upper portion of the first via hole VH1.

After the formation of the first encapsulation layer ENC1, a desmear process may further be performed on the portion of the top surface435tof the third conductive pattern435and the sidewall ENC1sof the first encapsulation layer ENC1. Residues of the first dielectric layer DL1, which remain on the top surface435tof the third conductive pattern435, may be removed through the desmear process. In addition, portions of the fillers FL, which protrude from the sidewall ENC1sof the first encapsulation layer ENC1, may be removed through the desmear process. However, after the desmear process, some of the fillers FL of the first encapsulation layer ENC1may include protrusions FLp protruding from the sidewall ENC1sof the first encapsulation layer ENC1. The surface roughness of the sidewall ENC1sof the first encapsulation layer ENC1likeFIG. 3may be formed through the desmear process.

Referring toFIG. 6, a second dielectric layer DL2may be formed on the third conductive pattern435and the first encapsulation layer ENC1. The second dielectric layer DL2may include a photosensitive material. In other words, the second dielectric layer DL2may be a photosensitive material layer. The second dielectric layer DL2may fill the first via hole VH1. A top surface DL2tof the second dielectric layer DL2may be concave in a partial region. The concave region of the top surface DL2tof the second dielectric layer DL2may overlap with the first via hole VH1in the second direction D2. The second dielectric layer DL2may be formed by a coating process.

Thereafter, an exposure process may be performed on a partial region of the second dielectric layer DL2. An exposure region PLR of the second dielectric layer DL2may be a specific region in the first via hole VH1. In other words, laser light DIL may be incident on the specific region in the first via hole VH1. A side surface PLRs of the exposure region PLR may be spaced apart from the sidewall ENC1sof the first encapsulation layer ENC1. The side surface PLRs of the exposure region PLR may have a gradient with respect to the top surface435tof the third conductive pattern435. The gradient of the side surface PLRs of the exposure region PLR may be substantially the same as the gradient of the sidewall ENC1sof the first encapsulation layer ENC1.

The exposure process may be performed by, for example, a laser direct imaging (LDI) exposure apparatus or an ultraviolet direct imaging (UVDI) exposure apparatus. The exposure process by the LDI exposure apparatus or the UVDI exposure apparatus may be performed without a photomask. For example, the LDI exposure apparatus or the UVDI exposure apparatus may determine a position of the exposure region on the basis of predetermined coordinates without a photomask. At this time, alignment algorithm which is substantially the same as the alignment algorithm used to form the first via hole VH1inFIG. 5may be used to determine the position of the exposure region. The exposure process using the LDI exposure apparatus or the UVDI exposure apparatus may have high speed, high accuracy and excellent alignment characteristics as compared with a general exposure process using a photomask. An edge of a wafer may be contracted or expanded in a heat treatment process performed on the wafer (or a panel) including a semiconductor package. However, the LDI exposure apparatus or the UVDI exposure apparatus may determine the position of the exposure region matched with the contracted or expanded wafer, and thus the alignment characteristic thereof may be excellent. In addition, the exposure process using the LDI exposure apparatus or the UVDI exposure apparatus may use the same alignment algorithm as the laser process of forming the first via hole VH1, and thus the alignment characteristic may be more improved.

The LDI exposure apparatus may use a single-wavelength laser. For example, a wavelength of the laser light DIL used in the LDI exposure apparatus may be selected from a range of 380 nm to 420 nm. Meanwhile, the laser light DIL used in the UVDI exposure apparatus may have a wavelength band. For example, the UVDI exposure apparatus may use the laser light DIL having a wavelength band of 300 nm to 500 nm. In addition, for example, the laser light DIL used in the UVDI exposure apparatus may have a peak at a specific wavelength in the wavelength band. Referring again toFIG. 2, a profile of a sidewall VSs of a via structure VS to be formed later may be controlled depending on a wavelength and an intensity of the laser light DIL used in the exposure process. Hereinafter,FIGS. 6 to 10illustrate a case in which the exposure process is performed by the LDI exposure apparatus, andFIG. 11illustrates a case in which the exposure process is performed by the UVDI exposure apparatus.

Referring toFIGS. 6 and 7, the second dielectric layer DL2exposed by the exposure process may be developed to form a second encapsulation layer ENC2having a second via hole VH2. A sidewall ENC2sof the second encapsulation layer ENC2may be substantially the same as the side surface PLRs of the exposure region illustrated inFIG. 6. The second via hole VH2may be defined by a portion of the top surface435tof the third conductive pattern435and the sidewall ENC2sof the second encapsulation layer ENC2. The portion of the top surface435tof the third conductive pattern435may be exposed by the second via hole VH2. The sidewall ENC2sof the second encapsulation layer ENC2may have a gradient with respect to the top surface435tof the third conductive pattern435. In other words, a width of the second via hole VH2in the first direction D1may increase as a height or level in the second direction D2increases. A central axis of the second via hole VH2may be substantially the same as a central axis of the first via hole VH1. Thus, a width W1(W2) of the second encapsulation layer ENC2in the first direction D1may be substantially constant in the first via hole VH1. The width W1(W2) of the second encapsulation layer ENC2in the first direction D1may be minimized by the exposure process using the LDI exposure apparatus or the UVDI exposure apparatus. Thus, a degree of freedom of a position design of the via structure VS (seeFIG. 2) to be formed later may be increased, and it is possible to prevent a crack from occurring at the sidewall ENC2sof the second encapsulation layer ENC2.

The sidewall ENC2sof the second encapsulation layer ENC2may have surfaces having different gradients with respect to the top surface435tof the third conductive pattern435. In more detail, a first surface S1may be inclined with respect to the top surface435tof the third conductive pattern435, and a second surface S2may be inclined with respect to each of the first surface S1and the top surface435tof the third conductive pattern435. An acute angle between the second surface S2and the top surface435tof the third conductive pattern435may be greater than 0 degree. An acute angle between the first surface S1and the top surface435tof the third conductive pattern435may be greater than the acute angle between the second surface S2and the top surface435tof the third conductive pattern435. In other words, the second encapsulation layer ENC2may have two corners in the second via hole VH2. The gradient of the second surface S2may be due to the concave portion of the top surface DL2tof the second dielectric layer DL2inFIG. 6. In addition, a top surface of the second encapsulation layer ENC2may be defined as a third surface S3. The third surface S3may be substantially parallel to the first direction D1in which the top surface435tof the third conductive pattern435extends.

After the formation of the second encapsulation layer ENC2, a plasma treatment process may further be performed on the portion of the top surface435tof the third conductive pattern435. Residues of the second dielectric layer DL2, which remain on the top surface435tof the third conductive pattern435, may be removed through the plasma treatment process.

Referring toFIG. 8, a seed metal layer PSD may be formed to conformally cover the top surface435tof the third conductive pattern435and the sidewall ENC2sand the top surface of the second encapsulation layer ENC2. A space surrounded by the seed metal layer PSD may be defined as a third via hole VH3. A thickness of the seed metal layer PSD may be substantially constant. Thus, a profile of a sidewall of the seed metal layer PSD may be substantially the same as a profile of the sidewall ENC2sof the second encapsulation layer ENC2. The seed metal layer PSD may be formed by, for example, a sputtering process. Since the seed metal layer PSD is formed by the sputtering process, the thin seed metal layer PSD may be easily formed to easily realize a fine pattern. In addition, the sputtering process may not use a harmful material and thus may be environmentally friendly.

Referring toFIG. 9, a photoresist pattern PR may be formed on the seed metal layer PSD outside the third via hole VH3. An open hole OP may be surrounded by the photoresist pattern PR. A conductive material CM may fill the third via hole VH3through the open hole OP and then may fill at least a portion of the open hole OP. The photoresist pattern PR may be formed by a photolithography process. The conductive material CM may be formed on the seed metal layer PSD by a plating process. For example, the plating process may be performed by an electroplating method or an electroless plating method. The seed metal layer PSD and the conductive material CM may completely fill the second via hole VH2. The seed metal layer PSD may assist growth of the conductive material CM. A top surface of the conductive material CM may be located at a higher level than the topmost surface of the seed metal layer PSD. In addition, the top surface of the conductive material CM may be located at a lower level than a top surface of the photoresist pattern PR. The photoresist pattern PR may be removed after the formation of the conductive material CM.

Referring toFIGS. 9 and 10, an upper portion of the conductive material CM and a portion of the seed metal layer PSD may be etched to form a via structure VS. The via structure VS may include a seed layer SD, an upper conductive via501, and an upper conductive pad503. In the via structure VS, the upper conductive pad503may completely overlap with the seed layer SD in the second direction D2. A profile of a sidewall VSs of the via structure VS may be substantially the same as a profile of the seed layer SD and a profile of the sidewall ENC2sof the second encapsulation layer ENC2. In more detail, the sidewall VSs of the via structure VS may have first and second surfaces S1and S2having different gradients with respect to the top surface435tof the third conductive pattern435, and a third surface S3on the top surface of the second encapsulation layer ENC2.

Referring again toFIG. 2, an upper insulating layer600may be formed on the second encapsulation layer ENC2and the via structure VS. A portion of the upper insulating layer600may be patterned to form an opening601exposing a portion of the upper conductive pad503. A width, in the first direction D1, of the opening601of the upper insulating layer600may increase as a height or level in the second direction D2increases.

FIG. 11is an enlarged view of the portion ‘A’ ofFIG. 1to illustrate a via structure of a semiconductor package according to some embodiments of inventive concepts. Hereinafter, the descriptions to substantially the same features and components as mentioned above with reference toFIGS. 1 to 10will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG. 11, a sidewall VSs of the via structure VS may have a first surface S1, a second surface S2c, and a third surface S3. More particularly, the first surface S1may be inclined with respect to the top surface435tof the third conductive pattern435. Here, a gradient of the first surface S1may be substantially constant. The third surface S3may be substantially parallel to the top surface435tof the third conductive pattern435and the first direction D1in which the upper conductive pad503extends.

The second surface S2cmay be a curved surface connected to the first surface S1and the third surface S3. The second surface S2cmay have a curved profile in a cross-sectional view ofFIG. 11. A curvature of the second surface S2cmay be less than a curvature of the corner of the first encapsulation layer ENC1. When the exposure process is performed by the UVDI exposure apparatus having the wavelength band inFIG. 6, the second surface S2chaving the curved profile may be formed. In other words, at least a portion of the sidewall ENC2sof the second encapsulation layer ENC2may be formed in a curved surface by the laser light having a wide wavelength band, and thus a portion of the sidewall VSs of the via structure VS may be formed in a curved surface.

FIG. 12is a cross-sectional view illustrating a semiconductor package according to some embodiments of inventive concepts. Hereinafter, the descriptions to substantially the same features and components as mentioned above with reference toFIGS. 1 to 11will be omitted for the purpose of ease and convenience in explanation.

Referring toFIG. 12, a semiconductor package according to some embodiments of inventive concepts may have a package-on-package (PoP) structure. In other words, a second semiconductor package20may be provided on a first semiconductor package10. The first semiconductor package10may be the same as the semiconductor package described with reference toFIG. 1.

The second semiconductor package20may include an upper substrate700, a first upper semiconductor chip810, a second upper semiconductor chip830, and an upper molding layer850covering the first and second upper semiconductor chips810and830. For example, the upper molding layer850may include substantially the same insulating material as the molding layer500of the first semiconductor package10.

The upper substrate700may be spaced apart from the upper insulating layer600of the first semiconductor package10in the second direction D2. A fourth conductive pattern730and a fifth conductive pattern750may be provided on the upper substrate700. The fourth conductive pattern730may be provided on a bottom surface of the upper substrate700and may be electrically connected to the upper conductive pad503of the first semiconductor package10through a package connection member710including a conductive material. The package connection member710may be, for example, a solder ball. The fifth conductive pattern750may be provided on a top surface of the upper substrate700. The fifth conductive pattern750may be electrically connected to the first upper semiconductor chip810through a first wire811and may be electrically connected to the second upper semiconductor chip830through a second wire831. However, embodiments of inventive concepts are not limited thereto. In certain embodiments, the fifth conductive pattern750may be electrically connected to the first and second upper semiconductor chips810and830by at least one of other various methods.

UnlikeFIG. 12, an additional interposer substrate may further be provided between the first semiconductor package10and the second semiconductor package20. In addition, unlikeFIG. 12, adhesive layers may further be provided between the upper substrate700and the first upper semiconductor chip810and between the first upper semiconductor chip810and the second upper semiconductor chip830, respectively.

According to the embodiments of inventive concepts, the cross-sectional area of the via structure may be increased to improve the electrical characteristics of the semiconductor package.

In addition, according to the embodiments of inventive concepts, it is possible to prevent a crack from occurring at the via structure by stress, and thus the reliability of the semiconductor package may be improved.

Furthermore, in the method of manufacturing the via structure of the semiconductor package according to the embodiments of inventive concepts, the seed layer may be formed by the sputtering process, and thus a fine pattern may be formed by an environmentally friendly method.

While inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.