Semiconductor devices, nonvolatile memory devices including the same, electronic systems including the same, and methods for fabricating the same

A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2020-0103707, filed on Aug. 19, 2020 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the entire contents of which are herein incorporated by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor devices. More specifically, the present disclosure relates to semiconductor devices including an element isolation film.

2. Description of the Related Art

With the tendency of electronic products to be light, thin, short and small, there is an increasing demand for high integration of semiconductor devices. Since the size of components included in the semiconductor devices (e.g., transistors) also decreases as semiconductor devices are gradually highly integrated, there may be a problem of an occurrence of leakage current. Therefore, it may be advantageous to control the leakage current of a semiconductor device to improve the performance and reliability of the semiconductor device.

On the other hand, there is a demand for a semiconductor device capable of storing a high capacity of data in an electronic system that uses data storage. Accordingly, a way which may increase the data storage capacity of the semiconductor device is being researched. For example, as one of various methods for increasing the data storage capacity of the semiconductor device, a semiconductor device that includes three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed.

SUMMARY

Aspects of the present invention provide a semiconductor device in which leakage current is controlled to improve reliability and performance.

Aspects of the present invention also provide a nonvolatile memory device including a semiconductor device in which leakage current is controlled and reliability and performance are improved.

Aspects of the present invention also provide an electronic system including a semiconductor device in which leakage current is controlled and reliability and performance are improved.

Aspects of the present invention also provide a method for fabricating a semiconductor device in which leakage current is controlled and reliability and performance are improved.

According to an aspect of the present disclosure, a semiconductor device comprising a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.

According to another aspect of the present disclosure, a semiconductor device comprising a substrate including an element isolation trench that defines an active region; an element isolation film that includes an insulating liner extending along a profile of the element isolation trench, an etching blocking liner on the insulation liner, and a gap fill insulating film that is in the element isolation trench on the etching blocking liner; a gate electrode on the active region; a source/drain region in the active region between the element isolation film and the gate electrode; and an isolation contact in the element isolation film. The isolation contact extends in the gap fill insulating film in a vertical direction intersecting an upper face of the substrate and comes into contact with the etching blocking liner.

According to another aspect of the present disclosure, a nonvolatile memory device that includes a first substrate of a peripheral circuit region, and a second substrate of a cell region, the nonvolatile memory device comprising a first circuit element and a second circuit element on the first substrate; an element isolation film that separates the first circuit element and the second circuit element in the first substrate; an isolation contact that extends in a vertical direction intersecting an upper face of the first substrate, in the element isolation film; a plurality of word lines sequentially stacked on the second substrate; a channel structure that intersects the plurality of word lines, on the second substrate; and a bit line connected to the channel structure. The isolation contact is configured to have a voltage applied thereto.

However, aspects of the present invention are not restricted to the examples set forth herein. The above and other aspects of the present invention will become more apparent to one of ordinary skill in the art to which the present invention pertains by referencing the detailed description of the present invention given below.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to some embodiments will be explained referring toFIGS.1to8.

FIG.1is a layout diagram for explaining the semiconductor device according to some embodiments.FIG.2is a schematic cross-sectional view taken along a line A-A′ ofFIG.1.FIGS.3aand3bare various enlarged views of a region R1ofFIG.2.

Referring toFIGS.1,2, and3a, the semiconductor device according to some embodiments may include a first substrate100, an element isolation film110, first to third circuit elements TR1, TR2and TR3, an interlayer insulation film150, a gate contact142, a source/drain contact144and an isolation contact146. For convenience of explanation, the gate contact142is now shown inFIG.1.

The first substrate100may include, but is not limited to, a base substrate, and an epitaxial layer grown on the base substrate. For example, the first substrate100may include only the base substrate without the epitaxial layer. The first substrate100may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate or the like, and may be an SOI (Semiconductor On Insulator) substrate. Hereinafter, the first substrate100will be explained as a silicon substrate as an example.

In some embodiments, the first substrate100may be doped with a first conductive type. For example, when each of the first to third circuit elements TR1, TR2and TR3to be described later is an n-type transistor, the first substrate100may include p-type impurities. Although not shown, the first substrate100may also include wells doped with the first conductive type.

The element isolation film110may define a plurality of active regions105A,105B,105C and105D inside the first substrate100. For example, an element isolation trench110tdefining a plurality of active regions105A,105B,105C and105D may be formed in the first substrate100. The element isolation film110may be in (e.g., may fill) the element isolation trench110t. The element isolation film110may surround each active region105A,105B,105C and105D. In some embodiments, a depth at which the element isolation trench110tis formed may be about 3000 Angstroms (Å) to about 5000 Å.

The plurality of active regions105A,105B,105C and105D may be separated from each other by the element isolation film110. For example, the plurality of active regions105A,105B,105C and105D may include a first active region105A and a second active region105B arranged along a first direction X. The element isolation film110between the first active region105A and the second active region105B extends in a second direction Y intersecting the first direction X, and may separate the first active region105A and the second active region105B. Additionally or alternatively, for example, the plurality of active regions105A,105B,105C and105D may include a third active region105C arranged together with the first active region105A along a second direction Y, and a fourth active region105D arranged together with the second active region105B along the second direction Y. The element isolation film110between the first active region105A and the third active region105C, and between the second active region105B and the fourth active region105D may extend in the first direction X, separate the first active region105A and the third active region105C, and separate the second active region105B and the fourth active region105D.

The element isolation film110may define an isolation region105I in the first substrate100on a lower face of the element isolation film110. That is, as shown inFIGS.2and3a, the isolation region105I may be a region of the first substrate100which is defined below the element isolation film110and overlaps the element isolation film110in the vertical direction. Here, the vertical direction means a direction that intersects the upper face of the first substrate100. For example, the isolation region105I may be defined in the first substrate100between the first active region105A and the second active region105B.

InFIGS.2and3a, although the side face of the element isolation film110is shown to have an inclination, this is only a feature of the process of forming the element isolation film110, and the present invention is not limited thereto.

In some embodiments, the element isolation film110may be formed of a multi-films. For example, the element isolation film110may include an insulating liner112, an etching blocking liner114and a gap fill insulating film116, which are sequentially stacked in the element isolation trench110t. The insulating liner112may extend along the profiles of the side face and the lower face of the element isolation trench110tin a conformal manner. The etching blocking liner114may be formed on the insulating liner112. The etching blocking liner114may extend along the profile of the insulating liner112in a conformal manner. The gap fill insulating film116may be formed on the etching blocking liner114. The gap fill insulating film116may be in (e.g., may fill) the region of the element isolation trench110tthat remains after the insulating liner112and the etching blocking liner114are formed.

The insulating liner112, the etching blocking liner114and the gap fill insulating film116may include, for example, but are not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof.

In some embodiments, the etching blocking liner114may include a material having an etching selectivity relative to the insulating liner112and the gap fill insulating film116. For example, when the insulating liner112and the gap fill insulating film116include silicon oxide, the etching blocking liner114may include at least one of silicon nitride, silicon carbonitride, silicon oxycarbonitride and a combination thereof. As an example, the insulating liner112and the gap fill insulating film116may include silicon oxide, and the etching blocking liner114may include silicon nitride.

The first to third circuit elements TR1, TR2and TR3may be placed on the active region105A,105B,105C and105D. For example, the first circuit element TR1and the second circuit element TR2may be placed on the first active region105A, and the third circuit element TR3may be placed on the second active region105B.

The first circuit element TR1may include a first gate dielectric film132A, a first gate electrode134A, a first source/drain region120A and a second source/drain region120B. The first gate electrode134A may extend in one direction (e.g., the second direction Y) on the first active region105A. The first gate dielectric film132A may be interposed between the first substrate100and the first gate electrode134A. The first source/drain region120A may be formed in the first active region105A on one side of the first gate electrode134A. The second source/drain region120B may be formed in the first active region105A on the other (e.g., an opposite) side of the first gate electrode134A.

The first source/drain region120A may be adjacent to the element isolation film110. For example, the first source/drain region120A may be formed in the first active region105A between the first gate electrode134A and the element isolation film110.

In some embodiments, the first source/drain region120A may be a drain region of the first circuit element TR1, and the second source/drain region120B may be a source region of the first circuit element TR1. For example, when the first circuit element TR1is an n-type transistor, a voltage relatively higher than that of the second source/drain region120B may be applied to the first source/drain region120A. As an example, a voltage of about 5 volts (V) may be applied to the first source/drain region120A, and a voltage of 0 V may be applied to the second source/drain region120B. In contrast, when the first circuit element TR1is a p-type transistor, a voltage relatively lower than that of the second source/drain region120B may be applied to the first source/drain region120A.

The second circuit element TR2may include a second gate dielectric film132B, a second gate electrode134B, a second source/drain region120B and a third source/drain region120C. The second gate electrode134B may extend in one direction (e.g., the second direction Y) on the first active region105A. As an example, the second gate electrode134B may extend alongside (e.g., in parallel with) the first gate electrode134A. The second gate dielectric film132B may be interposed between the first substrate100and the second gate electrode134B. The second source/drain region120B may be formed in the first active region105A on one side of the second gate electrode134B. The third source/drain region120C may be formed in the first active region105A on the other (e.g., an opposite) side of the second gate electrode134B.

In some embodiments, the first circuit element TR1and the second circuit element TR2may share a second source/drain region120B. For example, the second source/drain region120B may be formed in the first active region105A between the first gate electrode134A and the second gate electrode134B.

The third source/drain region120C may be adjacent to the element isolation film110. For example, the third source/drain region120C may be formed in the first active region105A between the second gate electrode134B and the element isolation film110.

In some embodiments, the second source/drain region120B may be a source region of the second circuit element TR2, and the third source/drain region120C may be a drain region of the second circuit element TR2. For example, when the second circuit element TR2is an n-type transistor, a voltage relatively higher than that of the second source/drain region120B may be applied to the third source/drain region120C. As an example, a voltage of about 5 V may be applied to the third source/drain region120C, and a voltage of 0 V may be applied to the second source/drain region120B. In contrast, when the second circuit element TR2is a p-type transistor, a voltage relatively lower than that of the second source/drain region120B may be applied to the third source/drain region120C.

The third circuit element TR3may include a third gate dielectric film132C, a third gate electrode134C and a fourth source/drain region120D. The third gate electrode134C may extend in one direction (e.g., the second direction Y) on the second active region105B. As an example, the third gate electrode134C may extend alongside (e.g., in parallel with) the first gate electrode134A and the second gate electrode134B. The third gate dielectric film132C may be interposed between the first substrate100and the third gate electrode134C. The fourth source/drain region120D may be formed in the second active region105B on one side of the third gate electrode134C.

The fourth source/drain region120D may be adjacent to the element isolation film110. For example, the fourth source/drain region120D may be formed in the second active region105B between the third gate electrode134C and the element isolation film110. In some embodiments, the fourth source/drain region120D may be a drain region of the third circuit element TR3.

The first to third gate dielectric films132A,132B and132C may include, for example, but are not limited to, silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, but is not limited to, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

In some embodiments, the first to third circuit elements TR1, TR2and TR3may be high-voltage transistors. For example, the first to third circuit elements TR1, TR2and TR3may each include, but are not limited to, thick first to third gate dielectric films132A,132B and132C of about 200 Å or more.

In some embodiments, the first to third circuit elements TR1, TR2and TR3may be high-voltage transistors. For example, although a high voltage of about 5 V to about 100 V may be applied to the first to third gate electrodes134A,134B and134C, the present invention is not limited thereto.

The first to fourth source/drain regions120A,120B,120C and120D may be doped with a second conductive type different from the first conductive type, respectively. For example, the first to fourth source/drain regions120A,120B,120C and120D may each include n-type impurities.

In some embodiments, the first to fourth source/drain regions120A,120B,120C and120D may each include low-concentration impurity regions122A,122B,122C and122D and high-concentration impurity regions124A,124B,124C and124D. The high-concentration impurity regions124A,124B,124C and124D may be formed inside the low-concentration impurity regions122A,122B,122C and122D. The low-concentration impurity regions122A,122B,122C and122D may surround the high-concentration impurity regions124A,124B,124C and124D.

The low-concentration impurity regions122A,122B,122C and122D and the high-concentration impurity regions124A,124B,124C and124D may be doped with the second conductive type, respectively. At this time, the doping concentration of the high-concentration impurity regions124A,124B,124C and124D may be higher than the doping concentration of the low-concentration impurity regions122A,122B,122C and122D.

Although not shown, the first to third circuit elements TR1, TR2and TR3may further include a gate spacer which covers the side faces of the first to third gate electrodes134A,134B and134C, respectively. Further, although not shown, the first to third circuit elements TR1, TR2and TR3may further include a gate capping pattern which covers the upper faces of the first to third gate electrodes134A,134B and134C, respectively. Although not shown, the first to third circuit elements TR1, TR2and TR3may further include an etching blocking film which covers first to fourth source/drain regions120A,120B,120C and120D, the gate spacer, and the gate capping pattern.

The interlayer insulating film150may be formed on the first substrate100. The interlayer insulating film150may be on (e.g., may cover) the first substrate100, the element isolation film110, and the first to third circuit elements TR1, TR2and TR3.

In some embodiments, the first to third circuit elements TR1, TR2and TR3may be formed at the same level. As used herein, “same level” means that the circuit elements are formed by the same fabricating process.

The gate contact142may be connected to each of the first to third gate electrodes134A,134B and134C. For example, the gate contact142may extend in the vertical direction intersecting the upper face of the first substrate100and penetrate the interlayer insulating film150. The gate contacts142may be electrically connected to the respective first to third gate electrodes134A,134B and134C to apply voltage to the respective first to third gate electrodes134A,134B and134C.

The gate contact142may include, but is not limited to, metals such as, for example, aluminum (Al), copper (Cu) or tungsten (W).

The source/drain contact144may be connected to the respective first to fourth source/drain regions120A,120B,120C and120D. For example, the source/drain contact144may vertically extend and penetrate the interlayer insulating film150. The source/drain contact144may be electrically connected to the respective first to fourth source/drain regions120A,120B,120C and120D to apply the voltage to the respective first to fourth source/drain regions120A,120B,120C and120D.

The source/drain contact144may include, for example, but is not limited to, metals such as aluminum (Al), copper (Cu) or tungsten (W). In some embodiments, the gate contact142and the source/drain contact144may be formed at the same level. For example, the gate contact142and the source/drain contact144may include the same material.

The isolation contact146may be placed on the element isolation film110. The isolation contact146may vertically overlap the element isolation film110. Further, at least a part of the isolation contact146may be placed in the element isolation film110. For example, the isolation contact146may vertically extend, penetrate the interlayer insulating film150and extend to the inside of the element isolation film110.

In some embodiments, a plurality of isolation contacts146may be placed around each of the plurality of active regions105A,105B,105C and105D. For example, as shown inFIG.1, some of the plurality of isolation contacts146may be interposed between the first active region105A and the second active region105B. Also, some others of the plurality of isolation contacts146may be interposed between the first active region105A and the third active region105C. The number and arrangement of the isolation contacts146shown inFIG.1are only examples, and the present invention is not limited thereto.

In some embodiments, the isolation contacts146interposed between the first active region105A and the second active region105B may be arranged (e.g., aligned with each other) along the second direction Y, and the isolation contacts146interposed between the first active region105A and the third active region105C may be arranged (e.g., aligned with each other) along the first direction X.

In some embodiments, the isolation contact146may be spaced apart from the lower face of the element isolation film110. For example, as shown inFIG.3a, the lower face of the isolation contact146may be spaced apart from the lower face of the element isolation film110by DT1. In some embodiments, a spaced distance DT1of the isolation contact146from the lower face of the element isolation film110may be about 100 Å to about 4000 Å. Accordingly, the lower face of the isolation contact146may contact the element isolation film110, and the isolation contact146thus may not penetrate the lower face of the element isolation film110.

In some embodiments, the isolation contact146may penetrate the gap fill insulating film116and come into contact with the etching blocking liner114. For example, the lower face of the isolation contact146may come into contact with the upper face of the etching blocking liner114extending along the lower face of the element isolation trench110t. The etching blocking liner114may be used as an etching blocking film in the etching process of forming a contact hole (e.g., the third contact hole146tofFIG.20) to form the isolation contact146.

In some embodiments, the isolation contact146may not completely penetrate the etching blocking liner114. For example, the lower face of the isolation contact146may be spaced apart from the lower face of the element isolation film110by the insulating liner112and the etching blocking liner114. As an example, the spaced distance DT1of the isolation contact146from the lower face of the element isolation film110may be the sum of the thickness of the insulating liner112and the thickness of the etching blocking liner114.

In some embodiments, a width W11of the isolation contact146may be smaller than a width of the element isolation film110. In such a case, the isolation contact146may be spaced apart from the side face of the element isolation film110. In some embodiments, the width W11of the isolation contact146may be smaller than the width of the gap fill insulating film116. In such a case, the isolation contact146may be spaced apart from the side face of the etching blocking liner114.

A voltage may be applied to the isolation contact146. The voltage applied to the isolation contact146may form an electric field in the isolation region105I to form a potential barrier. When the isolation contact146is spaced apart from the lower face of the element isolation film110, the insulating liner112and/or the etching blocking liner114may function as a dielectric film.

For example, when the first circuit element TR1is an n-type transistor, the first source/drain region120A including n-type impurities may function as a drain region of the first circuit element TR1. At this time, a ground voltage or a negative (−) voltage may be applied to the isolation contact146. As an example, a voltage of 0 V to about −5 V may be applied to the isolation contact146. As a result, the leakage current generated from the first source/drain region120A toward the isolation region105I may be reduced. In contrast, when the first circuit element TR1is a p-type transistor, the first source/drain region120A including p-type impurities may function as the drain region of the first circuit element TR1. At this time, a ground voltage or a positive (+) voltage may be applied to the isolation contact146.

In some embodiments, the spaced distance DT1of the isolation contact146from the lower face of the element isolation film110may be smaller than a spaced distance DT2of the isolation contact146from the side face of the element isolation film110. In such a case, the electric field formed on the lower face (the isolation region105I) of the element isolation film110may be stronger than the electric field formed on the side face of the element isolation film110.

The isolation contact146may include, for example, but is not limited to, metals such as aluminum (Al), copper (Cu) or tungsten (W). In some embodiments, the isolation contact146may be formed at the same level as the gate contact142and the source/drain contact144. For example, the gate contact142, the source/drain contact144and the isolation contact146may include the same material.

Referring toFIGS.1,2and3b, in the semiconductor device according to some embodiments, at least a part of the isolation contact146may be placed inside (e.g., by penetrating an upper surface of) the etching blocking liner114.

For example, a part of the etching blocking liner114extending along the lower face of the element isolation trench110tmay include a first trench114textending from its upper face. The lower part of the isolation contact146may be formed inside the first trench114t. This allows the lower face of the isolation contact146to be formed lower than the upper face of the etching blocking liner114extending along the lower face of the element isolation trench110t. Unlike the example shown, in some embodiments, the isolation contact146may completely penetrate (i.e., penetrate both upper and lower surfaces of) the etching blocking liner114.

FIG.4is a cross-sectional view for explaining the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to3bwill be briefly explained or omitted.

Referring toFIG.4, in the semiconductor device according to some embodiments, the element isolation film110may be formed of a single film.

For example, the element isolation film110may not include the insulating liner112, the etching blocking liner114and the gap fill insulating film116ofFIG.2. In some embodiments, the isolation contact146may be spaced apart from the lower face of the element isolation film110.

FIG.5is a layout diagram for explaining the semiconductor device according to some embodiments.FIG.6is a schematic cross-sectional view taken along a line B-B′ ofFIG.5.FIGS.7aand7bare various enlarged views of a region R2ofFIG.6. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to4will be briefly explained or omitted.

Referring toFIGS.5to7a, in the semiconductor device according to some embodiments, the isolation contact146may come into contact with the isolation region105I.

For example, the isolation contact146may extend in the vertical direction intersecting the upper face of the first substrate100and penetrate the interlayer insulating film150and the element isolation film110.

In some embodiments, a contact impurity region160may be formed inside the isolation region105I. The contact impurity region160may be doped with the first conductive type. For example, the contact impurity region160may include p-type impurities.

The isolation contact146may be placed on the contact impurity region160. The isolation contact146may vertically overlap the contact impurity region160. The isolation contact146may penetrate the element isolation film110and come into contact with the contact impurity region160. The isolation contact146may come into contact with the contact impurity region160and apply a voltage to the isolation region105I.

For example, when the first circuit element TR1is an n-type transistor, the first source/drain region120A including n-type impurities may function as the drain region of the first circuit element TR1. At this time, a ground voltage or a negative (−) voltage may be applied to the contact impurity region160by the isolation contact146. As an example, a voltage of 0 V to about −5 V may be applied to the isolation contact146. As a result, the leakage current generated from the first source/drain region120A toward the isolation region105I may be reduced. In contrast, when the first circuit element TR1is a p-type transistor, the first source/drain region120A including p-type impurities may function as the drain region of the first circuit element TR1. At this time, a ground voltage or a positive voltage (+) may be applied to the contact impurity region160by the isolation contact146.

In some embodiments, the contact impurity region160may form an ohmic contact with the isolation contact146. As long as the contact impurity region160forms ohmic contact with the isolation contact146, the doping concentration of the contact impurity region160may be relatively low.

In some embodiments, the contact impurity region160may form a plurality of isolation regions spaced apart from each other. For example, each contact impurity region160may surround the isolation contact146from a planar view point. As an example, as shown inFIG.5, each contact impurity region160may surround one or more isolation contacts146.

In some embodiments, a width W12of the contact impurity region160may be greater than the width W11of the isolation contact146, as shown inFIG.7a. As a result, in the process of forming the isolation contact146, the isolation contact146may stably come into contact with the contact impurity region160.

Referring toFIGS.5,6and7b, in the semiconductor device according to some embodiments, at least a part of the isolation contact146may be placed inside (e.g., by penetrating an upper surface of) the contact impurity region160.

For example, the contact impurity region160may include a second trench160textending from its upper face. The lower part of the isolation contact146may be formed inside the second trench160t. As a result, the lower face of the isolation contact146may be formed lower than the upper face of the contact impurity region160.

FIG.8is a layout diagram for explaining the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.5to7bwill be briefly explained or omitted.

Referring toFIG.8, in the semiconductor device according to some embodiments, the contact impurity region160may surround each of the active regions105A,105B,105C and105D.

For example, a part of the contact impurity region160may extend in the second direction Y between the first active region105A and the second active region105B. Another part of the contact impurity region160may extend in the first direction X between the first active region105A and the third active region105C.

As the semiconductor devices are gradually highly integrated, the effects of leakage currents are gradually increasing. For example, as the width of the element isolation film gradually decreases, the leakage current (hereinafter, referred to as isolation leakage current) generated from the transistor adjacent to the element isolation film along the surface of the element isolation film may increase.

In order to prevent/impede this problem, although a high-concentration impurity region may be formed on the lower face of the element isolation film to form a potential barrier, there is a problem of a decrease in breakdown voltage of the transistor adjacent to the element isolation film. For example, when the first source/drain region120A includes impurities of the second conductive type (e.g., an n-type), impurities of the first conductive type (e.g., a p-type) may be doped in the isolation region105I at high concentration to form a potential barrier. However, the impurities of the first conductive type (e.g., the p-type) formed in the isolation region105I may be diffused toward the first source/drain region120A to lower the breakdown voltage of the first circuit element TR1.

In contrast, the semiconductor device according to some embodiments may control the isolation leakage current by not forming an impurity region in the isolation region105I, or by simply forming a low-concentration impurity region. Specifically, the semiconductor device according to some embodiments may form a potential barrier in the isolation region105I through the isolation contact146which is formed in the element isolation film110and to which a voltage is applied. This makes it possible to provide a semiconductor device in which the leakage current is effectively controlled and the reliability and performance are improved.

The nonvolatile memory devices according to some embodiments will be explained below referring toFIGS.1to13.

FIG.9is a schematic block diagram for explaining the nonvolatile memory device according to some embodiments.FIG.10is a schematic cross-sectional view for explaining the nonvolatile memory device according to some embodiments.FIGS.11and12are various enlarged views of a region R3ofFIG.10. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to8will be briefly explained or omitted.

Referring toFIG.9, the nonvolatile memory device1100according to some embodiments may include a first structure1100F, and a second structure1100S on the first structure1100F.

In some embodiments, the first structure1100F may be placed next to the second structure1100S. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be a memory cell structure that includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure1100S, each memory cell string CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT placed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be variously modified according to the embodiments.

In some embodiments, the upper transistors UT1and UT2may include a string selection transistor, and the lower transistors LT1and LT2may include a ground selection transistor. The first and second gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be the gate electrodes of the memory cell transistors MCT, and the first and second gate upper lines UL1and UL2may be the gate electrodes of the upper transistors UT1and UT2, respectively.

In some embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground selection transistor LT2connected in series. The upper transistors UT1and UT2may include a string selection transistor UT1and an upper erase control transistor UT2connected in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT2may be used in an erase operation for erasing the data stored in the memory cell transistors MCT, using a gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection wirings1115that extend from the inside of the first structure1100F to the second structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection wirings1125that extend from the inside of the first structure1100F to the second structure1100S.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor among a plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. In some embodiments, the logic circuit1130may be connected to the decoder circuit1110through the isolation contact146. Accordingly, the logic circuit1130may control the element isolation film (e.g., film110). For example, the logic circuit1130may apply a voltage to the isolation region (e.g., region105I ofFIG.2) of the decoder circuit1110.

Referring toFIG.10, the nonvolatile memory device according to some embodiments may include a peripheral circuit region PERI and a cell region CELL.

The peripheral circuit region PERI may include a first substrate100, an interlayer insulating film150, a plurality of circuit elements TR1, TR2TR3,220aand220bformed on the first substrate100, first metal layers144,146,230aand230bconnected to each of the plurality of circuit elements TR1, TR2, TR3,220aand220b, and second metal layers240,240aand240bformed on the first metal layers144,146,230aand230b.

In some embodiments, the first to third circuit elements TR1, TR2and TR3may provide a decoder circuit (e.g., decoder circuit1110ofFIG.9) in the peripheral circuit region PERI. In some embodiments, the fourth circuit element220amay provide a logic circuit (e.g., logic circuit1130ofFIG.9) in the peripheral circuit region PERI. In some embodiments, a fifth circuit element220bmay provide a page buffer (e.g., page buffer1120ofFIG.9) in the peripheral circuit region PERI.

Although only the first metal layers144,146,230aand230band the second metal layers240,240aand240bare shown and explained in the present specification, the present invention is not limited thereto, and at least one or more metal layers may be further formed on the second metal layers240,240aand240b. At least some of one or more metal layers formed on the second metal layers240,240aand240bmay be formed of aluminum or the like having a lower resistance than copper which forms the second metal layers240,240aand240b.

In some embodiments, the first metal layers144,146,230aand230bmay be formed of tungsten having a relatively high resistance, and the second metal layers240,240aand240bmay be formed of copper having a relatively low resistance.

The interlayer insulating film150may be placed on the first substrate100to cover the plurality of circuit elements TR1, TR2, TR3,220aand220b, the first metal layers144,146,230aand230b, and the second metal layers240,240aand240b.

The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate310and a common source line320. A plurality of word lines (331to338; collectively,330) may be stacked on the second substrate310along a vertical direction Z intersecting the upper face of the second substrate310. Insulating layers3301may be alternatingly stacked between the word lines330. The string selection line (e.g., UL1and UL2ofFIG.9) and the ground selection line (e.g., LL1and LL2ofFIG.9) may be placed at each of the upper part and the lower part of the word lines330, and the plurality of word lines330may be placed between the string selection line and the ground selection line.

A channel structure CH may extend in the vertical direction Z and penetrate the word lines330, the string selection lines, and the ground selection line. As shown inFIGS.11and12, the channel structure CH may include a semiconductor pattern390and an information storage film392.

The semiconductor pattern390may extend in the third direction Z. Although the semiconductor pattern390is shown as a cup shape, this is only an example, and the semiconductor pattern390may also have various shapes such as a cylindrical shape, a square barrel shape, and a solid filler shape. The semiconductor pattern390may include, for example, but is not limited to, semiconductor materials such as single crystal silicon, polycrystalline silicon, organic semiconductor material and carbon nanostructure.

The information storage film392may be interposed between the semiconductor pattern390and the word lines330. For example, the information storage film392may extend along the side faces of the semiconductor pattern390.

In some embodiments, the information storage film392may be formed of multi-films. For example, the information storage film392may include a tunnel insulating film392a, a charge storage film392band a blocking insulating film392cwhich are sequentially stacked on the semiconductor pattern390. The tunnel insulating film392amay include, for example, a silicon oxide or a high-k material (for example, aluminum oxide (Al2O3) and hafnium oxide (HfO2)) having a higher dielectric constant than the silicon oxide. The charge storage film392bmay include, for example, silicon nitride. The blocking insulating film392cmay include, for example, a silicon oxide or a high-k material having a higher dielectric constant than the silicon oxide. In some embodiments, the information storage film392may further include a gate insulating film392dthat extends along the surface of each word line330.

In some embodiments, the channel structure CH may further include a filling pattern394. The filling pattern394may be formed to fill the inside of the cup-shaped semiconductor pattern390. The filling pattern394may include, but is not limited to, insulating materials, for example, silicon oxides.

The common source line320may be formed to be connected to the semiconductor pattern390of the channel structure CH.

As shown inFIG.11, in some embodiments, the channel structure CH may penetrate the common source line320and be buried in the second substrate310. The common source line320may penetrate a part of the information storage film392and be connected to the side faces of the semiconductor pattern390.

As shown inFIG.12, in some embodiments, at least a part of the common source line320may be buried in the second substrate310. The common source line320may be formed, for example, from a second substrate310by a selective epitaxial growth (SEG) process. The channel structure CH may penetrate a part of the information storage film392and be connected to the upper face of the common source line320.

The channel structure CH may be electrically connected to the first metal layer350cand the second metal layer360c(FIG.10). For example, the first metal layer350cmay be a bit line contact, and the second metal layer360cmay be a bit line (e.g., BL ofFIG.9). In some embodiments, the bit line360cmay extend along one direction (e.g., the second direction Y) parallel to the upper face of the second substrate310. In some embodiments, the bit line360cmay be electrically connected to a fifth circuit element220bthat provides a page buffer (e.g., page buffer1120ofFIG.9) in the peripheral circuit region PERI.

The word lines330may extend along a direction (e.g., the first direction X) parallel to the upper face of the second substrate310, and may be connected to the plurality of cell contact plugs340. The word lines330and the cell contact plugs340may be connected to each other with pads provided by extension of at least some of the word lines330with different lengths. A first metal layer350band a second metal layer360bmay be connected sequentially to the upper part of the cell contact plugs340connected to the word line330.

In some embodiments, the cell contact plugs340may be electrically connected to the first to third circuit elements TR1, TR2and TR3that provide a decoder circuit (e.g., decoder circuit1110ofFIG.9) in the peripheral circuit region PERI. As an example, the first metal layer350bconnected to the cell contact plug340may be connected to the first metal layer350dby the second metal layer360b. The first metal layer350dmay be connected to the second metal layer240through a connection contact plug345. As a result, the first to third circuit elements TR1, TR2and TR3may be electrically connected to the word lines330. For example, the first circuit element TR1may be electrically connected to a part of the word lines330, the second circuit element TR2may be electrically connected to another part/one of the word lines330, and the third circuit element TR3may be electrically connected to still another part/one of the word lines330.

In some embodiments, the operating voltages of the first to third circuit elements TR1, TR2and TR3may differ from the operating voltage of a fifth circuit element220bthat provides the page buffer (e.g., page buffer1120ofFIG.9). As an example, the operating voltage of the fifth circuit element220bmay be greater than the operating voltage of the first to third circuit elements TR1, TR2and TR3.

The common source line contact plug380may be electrically connected to the common source line320. The common source line contact plug380is formed of a conductive material such as metal, metal compound or polysilicon, and a first metal layer350amay be formed on the common source line contact plug380.

In some embodiments, a lower insulating film201that covers the lower face of the first substrate100may be formed below the first substrate100, and a first I/O pad205may be formed on the lower insulating film201. The first I/O pad205is connected to at least one of a plurality of circuit elements TR1, TR2, TR3,220aand220bplaced in the peripheral circuit region PERI through the first I/O contact plug203, and may be separated from the first substrate100by the lower insulating film201. Further, a side insulating film is placed between the first I/O contact plug203and the first substrate100, and may electrically separate the first I/O contact plug203and the first substrate100.

In some embodiments, an upper insulating film301that covers the upper face of the second substrate310may be formed over the second substrate310, and a second I/O pad305may be placed on the upper insulating film301. The second I/O pad305may be connected to at least one of a plurality of circuit elements TR1, TR2, TR3,220aand220bplaced in the peripheral circuit region PERI through the second I/O contact plug303.

In some embodiments, the second substrate310, the common source line320and the like may not be placed in the region in which the second I/O contact plug303is placed. Also, the second I/O pad305may not overlap the word lines330in the vertical direction Z. The second I/O contact plug303is separated from the second substrate310in a direction (e.g., the first direction X) parallel to the upper face of the second substrate310, penetrates the interlayer insulating film315of the cell region CELL, and may be connected to the second I/O pad305.

In some embodiments, the first I/O pad205and the second I/O pad305may be selectively formed. As an example, the nonvolatile memory device according to some embodiments includes only the first I/O pad205placed on the first substrate100or may include only the second I/O pad305placed on the second substrate310. Or, the nonvolatile memory device according to some embodiments may include both the first I/O pad205and the second I/O pad305.

In some embodiments, the isolation contact146may be electrically connected to the first I/O pad205or the second I/O pad305through the first I/O contact plug203or the second I/O contact plug303. As a result, a voltage may be applied to the isolation contact146.

FIG.13is a schematic cross-sectional view for explaining the nonvolatile memory device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to12will be briefly explained or omitted.

Referring toFIG.13, the nonvolatile memory device according to some embodiments may have a C2C (chip to chip) structure.

The C2C structure may mean a structure in which an upper chip including the cell region CELL is manufactured on the first wafer, a lower chip including the peripheral circuit region PERI is manufactured on the second wafer different from the first wafer, and then, the upper chip and the lower chip are connected to each other by a bonding way. As an example, the bonding way may mean a way of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding way may be a Cu—Cu bonding way, and the bonding metal may also be formed of aluminum or tungsten.

In some embodiments, the peripheral circuit region PERI and the cell region CELL may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

The word line bonding region WLBA may be defined as a region in which a plurality of cell contact plugs340and the like is placed. The lower bonding metals271band272bmay be formed on the second metal layer240of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals271band272bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals371band372bof the cell region CELL by the bonding way. The lower bonding metals271band272band the upper bonding metals371band372bmay be formed of aluminum, copper, tungsten, or the like. The cell contact plugs340may be connected to the peripheral circuit region PERI through the upper bonding metals371band372bof the cell region CELL and the lower bonding metals271band272bof the peripheral circuit region PERI in the word line bonding region WLBA.

The bit line bonding region BLBA may be defined as a region in which the channel structure CH, the bit line360cand the like are placed. The bit line360cmay be electrically connected to the fifth circuit element220bin the bit line bonding region BLBA. As an example, the bit line360cis connected to the upper bonding metals371cand372cin the cell region CELL, and the upper bonding metals371cand372cmay be connected to the lower bonding metals271cand272cconnected to the fifth circuit element220b.

A common source line contact plug380may be placed in the external pad bonding region PA. The common source line contact plug380is formed of a conductive material such as metal, metal compound or polysilicon, and may be electrically connected to the common source line320. A first metal layer350aand a second metal layer360amay be sequentially stacked over the common source line contact plug380. As an example, the region in which the common source line contact plug380, the first metal layer350a, and the second metal layer360aare placed may be defined as the external pad bonding region PA. Also, I/O pads205and305may be placed in the external pad bonding region PA.

A metal pattern of the uppermost metal layer exists as a dummy pattern in each of the external pad bonding region PA and the bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI, or the uppermost metal layer may be empty.

The nonvolatile memory device according to some embodiments may form a lower metal pattern273ahaving the same shape as the upper metal pattern372aof the cell region CELL on the uppermost metal layer of the peripheral circuit region PERI to correspond to the upper metal pattern372aformed on the uppermost metal layer of the cell region CELL, in the external pad bonding region PA. The lower metal pattern273aformed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to another contact in the peripheral circuit region PERI. Similarly, an upper metal pattern having the same shape as the lower metal pattern272dof the peripheral circuit region PERI may be formed on the upper metal layer of the cell region CELL to correspond to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA.

Also, in the bit line bonding region BLBA, an upper metal pattern372dhaving the same shape as the lower metal pattern272dof the peripheral circuit region PERI may be formed on the uppermost metal layer of the cell region CELL to correspond to the lower metal pattern272dformed on the uppermost metal layer of the peripheral circuit region PERI. The contact may not be formed on the upper metal pattern372dformed on the uppermost metal layer of the cell region CELL.

Hereinafter, a method for fabricating a semiconductor device according to some embodiments will be explained referring toFIGS.1to24.

FIGS.14to20are intermediate step diagrams for explaining the method for fabricating the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to13will be briefly described or omitted.

Referring toFIG.14, a preliminary gate dielectric film132L, a gate electrode film134L and a sacrificial film170are sequentially formed on the first substrate100.

The preliminary gate dielectric film132L may include, for example, silicon oxide, silicon oxynitride, silicon nitride, and high-k materials having a higher dielectric constant than silicon oxide.

The sacrificial film170may include, for example, but is not limited to, silicon oxides. As an example, the sacrificial film170may include PEOX (Plasma Enhance Oxide).

Referring toFIG.15, an element isolation trench110tis formed in the first substrate100.

The element isolation trench110tmay define a plurality of active regions105A,105B,105C and105D in the first substrate100. Further, the element isolation trench110tmay define the isolation region105I in the first substrate100on the lower face of the element isolation trench110t.

Referring toFIG.16, an insulating liner112, an etching blocking liner114and a gap fill insulating film116are sequentially formed in the element isolation trench110t.

The insulating liner112may extend along the profiles of the side face of the lower face of the element isolation trench110tin a conformal manner. The etching blocking liner114may extend along the profile of the insulating liner112in a conformal manner. The gap fill insulating film116may fill the region of the element isolation trench110tthat remains after the insulating liner112and the etching blocking liner114are formed.

In some embodiments, the etching blocking liner114may include a material having an etching selectivity with respect to the insulating liner112and the gap fill insulating film116. As an example, the insulating liner112and the gap fill insulating film116may include silicon oxide, and the etching blocking liner114may include silicon nitride.

Referring toFIG.17, a part of the etching blocking liner114is removed.

For example, the recess process of the etching blocking liner114may be performed. In some embodiments, since the insulating liner112and the gap fill insulating film116may include a material having an etching selectivity with respect to the etching blocking liner114, the etching blocking liner114may be selectively removed.

Referring toFIG.18, a flattening process is performed.

For example, an insulating film that fills the region from which the etching blocking liner114is removed may be formed. Subsequently, the flattening process may be performed. The flattening process may include, but is not limited to, for example, a chemical mechanical polishing (CMP) process. As a result, the element isolation film110that fills the element isolation trench110tmay be formed.

In some embodiments, the sacrificial film170may be removed by the flattening process. As a result, the upper face of the gate electrode film134L, the upper face of the insulating liner112and the upper face of the gap fill insulating film116may be exposed.

Referring toFIG.19, the first to third circuit elements TR1, TR2and TR3and the interlayer insulating film150are formed on the first substrate100.

The first to third circuit elements TR1, TR2and TR3may be formed on the active regions105A,105B,105C and105D. For example, the first circuit element TR1and the second circuit element TR2may be placed on the first active region105A, and the third circuit element TR3may be placed on the second active region105B.

Subsequently, an interlayer insulating film150that covers the first to third circuit elements TR1, TR2and TR3may be formed on the first substrate100.

Referring toFIG.20, a first contact hole142t, a second contact hole144tand a third contact hole146tare formed in the interlayer insulating film150.

The first contact hole142tmay penetrate the interlayer insulating film150to expose the first to third gate electrodes134A,134B and134C. The second contact hole144tmay penetrate the interlayer insulating film150to expose the first to fourth source/drain regions120A,120B,120C and120D of the first to fourth source/drain regions. The third contact hole146tmay penetrate the interlayer insulating film150to expose the element isolation film110.

In some embodiments, the third contact hole146tmay penetrate the interlayer insulating film150and the gap fill insulating film116to expose the etching blocking liner114. Since the etching blocking liner114may include a material having an etching selectivity with respect to the gap fill insulating film116, the etching blocking liner114may be used as an etching blocking film in the process of forming the third contact hole146t.

The third contact hole146tmay be formed at the same time as the first contact hole142tand/or the second contact hole144t, and may alternatively be formed before the first contact hole142tand/or the second contact hole144tare formed or after the first contact hole142tand/or the second contact hole144tare formed.

The gate contact142may fill the first contact hole142t. Therefore, the gate contact142may be connected to each of the first to third gate electrodes134A,134B and134C. The source/drain contact144may fill the second contact hole144t. Thus, the source/drain contact144may be connected to the respective first to fourth source/drain regions120A,120B,120C and120D. The isolation contact146may fill the third contact hole146t. Therefore, at least a part of the isolation contact146may be placed in the element isolation film110.

FIGS.21to24are intermediate step diagrams for explaining the method for fabricating the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to20will be briefly described or omitted. For reference,FIG.21is a diagram for explaining the step afterFIG.15.

Referring toFIG.21, a contact impurity region160is formed in the isolation region105I.

For example, a contact impurity region160may be formed in a portion of the isolation region105I exposed by the element isolation trench110t. Formation of the contact impurity region160may include, but is not limited to, for example, an ion implantation process.

Referring toFIG.22, the element isolation film110is formed in the element isolation trench110t.

Although the element isolation film110is shown as only being formed of a single film inFIG.22, this is merely an example. For example, the element isolation film110may, of course, be formed of multi-films.

Referring toFIG.23, the first to third circuit elements TR1, TR2and TR3and the interlayer insulating film150are formed on the first substrate100. Since formation of the first to third circuit elements TR1, TR2and TR3and the interlayer insulating film150is similar to that explained above referring toFIG.19, detailed explanation thereof will not be provided below.

Referring toFIG.24, a first contact hole142t, a second contact hole144tand a third contact hole146tare formed in the interlayer insulating film150. Since the formation of the first contact hole142tand the second contact hole144tis similar to that explained above referring toFIG.20, detailed explanation thereof will not be provided below.

In some embodiments, the third contact hole146tmay penetrate the element isolation film110to expose the contact impurity region160. The third contact hole146tmay be formed at the same time as the first contact hole142tand/or the second contact hole144t, and may alternatively be formed before the first contact hole142tand/or the second contact hole144tare formed or after the first contact hole142tand/or the second contact hole144tare formed.

Subsequently, referring toFIG.6, the gate contact142, the source/drain contact144aand the isolation contact146are formed. Since formation of the gate contact142, the source/drain contact144and the isolation contact146is similar to that explained above usingFIG.2, detailed explanation thereof will not be provided below.

Hereinafter, the nonvolatile memory devices according to some embodiments will be explained referring toFIGS.1to28.

FIG.25is a schematic block diagram for explaining an electronic system according to some embodiments.FIG.26is a schematic perspective view for explaining the electronic system according to some embodiments.FIGS.27and28are various schematic cross-sectional views taken along a line “I-I” ofFIG.26. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to24will be briefly explained or omitted.

Referring toFIG.25, an electronic system1000according to some embodiments may include a semiconductor (e.g., nonvolatile memory) device1100, and a controller1200that is electrically connected to the semiconductor device1100. The electronic system1000may be a storage device that includes a single or multiple semiconductor devices1100, or an electronic device that includes the storage device. For example, the electronic system1000may be an SSD device (solid state drive device) including a single or multiple semiconductor devices1100, a USB (Universal Serial Bus), a computing system, a medical device or a communication device.

The semiconductor device1100may be a nonvolatile memory device (e.g., a NAND flash memory device), and may be, for example, the nonvolatile memory device described above referring toFIGS.9to13. The semiconductor device1100may communicate with the controller1200through an I/O pad1101that is electrically connected to the logic circuit1130. The I/O pad1101may be electrically connected to the logic circuit1130through the I/O connection wiring1135extending from the inside of the first structure1100F to the second structure1100S. The I/O connection wiring1135, for example, may be the first I/O contact plug203or the second I/O contact plug303which is described above with reference toFIGS.9to13. In some embodiments, the isolation contact146may be connected to the I/O pad1101through the I/O connection wiring1135. For example, as described above, the isolation contact146may be connected to the logic circuit1130. Accordingly, the isolation contact146may be controlled by the controller1200and a voltage may be applied to the isolation contact146.

The controller1200may include a processor1210, a NAND controller1220, and a host interface (I/F)1230. In some embodiments, the electronic system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control the operation of the overall electronic system1000including the controller1200. The processor1210may operate in accordance with a predetermined firmware, and may control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221that processes communication with the semiconductor device1100. Control commands for controlling the semiconductor device1100, data to be recorded in the memory cell transistor MCT of the semiconductor device1100, data to be read from the memory cell transistors MCT of the semiconductor device1100, and the like may be sent through the NAND interface1221. The host interface1230may provide a communication function between the electronic system1000and an external host. When receiving the control commands from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

Referring toFIG.26, the electronic system2000according to some embodiments may include a main substrate2001, a main controller2002mounted on the main substrate2001, one or more semiconductor packages2003, and a DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the main controller2002by wiring patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including the plurality of fins coupled to an external host. In the connector2006, the number and arrangement of the plurality of fins may vary depending on the communication interface between the electronic system2000and the external host. In some embodiments, the electronic system2000may communicate with an external host in accordance with any one of interfaces such as M-Phy for a USB (Universal Serial Bus), a PCI-Express (Peripheral Component Interconnect Express), a SATA, (Serial Advanced Technology Attachment), and an UFS (Universal Flash Storage). In some embodiments, the electronic system2000may operate by a power supplied from an external host through the connector2006. The electronic system2000may further include a PMIC (Power Management Integrated Circuit) that distributes the power supplied from the external host to the main controller2002and the semiconductor package2003.

The main controller2002may record data in the semiconductor package2003or read data from the semiconductor package2003, and may improve the operating speed of the electronic system2000.

The DRAM2004may be a buffer memory for reducing a speed difference between the semiconductor package2003, which is a data storage space, and the external host. The DRAM2004included in the electronic system2000may also operate as a kind of cache memory, and may also provide a space for temporarily storing data in the control operation of the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the main controller2002may further include a DRAM controller for controlling the DRAM2004in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bthat are spaced apart from each other. The first and second semiconductor packages2003aand2003bmay be semiconductor packages including a plurality of semiconductor chips2200, respectively. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300placed on each lower face of the semiconductor chips2200, a connection structure2400that electrically connects the semiconductor chips2200and the package substrate2100, and a molding layer2500that covers the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be a printed circuit board that includes package upper pads2130. Each semiconductor chip2200may include an I/O pad2210. The I/O pad2210may correspond to the I/O pad1101ofFIG.25. Each of the semiconductor chips2200may include memory blocks3210and channel structures3220. The memory blocks3210may correspond to the memory block ofFIG.10, and the channel structures3220may correspond to the channel structure CH ofFIG.10. Each of the semiconductor chips2200may include the nonvolatile memory device explained above usingFIGS.9to13.

In some embodiments, the connection structure2400may be a bonding wire that electrically connects the I/O pad2210and the package upper pads2130. Therefore, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by the bonding wire way, and may be electrically connected to the package upper pads2130of the package substrate2100. In some embodiments, in the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may also be electrically connected to each other by a connection structure including a through silicon via (TSV), in place of the bonding wire type of connection structure2400.

In some embodiments, the main controller2002and the semiconductor chips2200may also be included in a single package. In some embodiments, the main controller2002and the semiconductor chips2200are mounted on another interposer substrate different from the main substrate2001, and the main controller2002and the semiconductor chips2200may also be connected to each other by the wirings formed on the interposer substrate.

Referring toFIG.27, in the semiconductor package2003, the package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body portion2120, package upper pads (2130ofFIG.26) placed on the upper face of the package substrate body portion2120, lower pads2125placed on the lower face of the package substrate body portion2120or exposed through the lower face, and internal wirings2135that electrically connect the upper pads2130and the lower pads2125inside the package substrate body portion2120. The upper pads2130may be electrically connected to the connecting structures2400. The lower pads2125may also be connected to the wiring patterns2005of the main substrate2100of the electronic system2000through the conductive connections2800, as inFIG.26.

Each of the semiconductor chips2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200sequentially stacked on the semiconductor substrate3010. The semiconductor substrate3010may correspond to the first substrate100ofFIG.10. The first structure3100may correspond to the peripheral circuit region PERI ofFIG.10, and the second structure3200may correspond to the cell region CELL ofFIG.10.

For example, the second structure3200may include a second substrate310, a plurality of word lines330, a channel structure CH, and a plurality of cell contact plugs340. In some embodiments, as shown, the first structure3100may include an element isolation film110and an isolation contact146. Each of the semiconductor chips2200may further include an I/O pad (pad2210ofFIG.26) that is electrically connected to the first structure3100.

Referring toFIG.28, in the semiconductor package2003A, each of the semiconductor chips2200may include a first structure3100and a second structure3200bonded by a wafer bonding way. For example, the first structure3100may correspond to the peripheral circuit region PERI ofFIG.13, and the second structure3200may correspond to the cell region CELL ofFIG.13.

The semiconductor chips2200ofFIGS.27and28may be electrically connected to each other by connection structures in the form of bonding wires (structures2400ofFIG.26). However, in some embodiments, the semiconductor chips inside the single semiconductor package, such as the semiconductor chips2200ofFIGS.27and28, may be electrically connected to each other by a connecting structure including the through silicon via (TSV).