FORMATION OF BAND-EDGE CONTACTS

Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor structures, and more particularly formation of band-edge contacts.

BACKGROUND OF THE DISCLOSURE

Integrated circuits, such as microprocessors, digital signal processors, and memory devices are made up of literally millions of transistors coupled together into functional circuits.

FIG. 1illustrates an nFET100formed using a MIS (Metal-Insulator Semiconductor) contacts. nFET100includes a silicon substrate110having a gate120disposed thereon. A pair of source/drain regions130are disposed on opposite sides of gate120. The source and drain regions include heavily doped epitaxially grown portions132of silicon substrate110, an insulting layer134, and a metal contact136. Insulting layer134such as a TiO2layer acts as an insulating layer to depin the metal to the doped silicon portions132.

FIG. 2illustrates another approach for forming an nFET200, which includes a silicon substrate210having a gate220disposed thereon. A pair of source/drain regions230are disposed on opposite sides of gate220. The source and drain regions include epitaxially grown single crystal portions232of silicon substrate210such as a III-V epitaxial deposition, and a metal contact236.

SUMMARY OF THE DISCLOSURE

The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method which includes, for example, providing an intermediate semiconductor structure having a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

In another embodiment, a method includes, for example, providing an intermediate semiconductor structure having a substrate having a first plurality of gates having first source/drain regions adjacent the first plurality of gates and a second plurality of gates having second source/drain regions adjacent the second plurality of gates, depositing a first non-epitaxial layer on the plurality of first source/drain regions, depositing a second non-epitaxial layer on the plurality of second source/drain regions, depositing a first metal layer on the first non-epitaxial layer, depositing a second metal layer on the second non-epitaxial layer, forming first metal alloy contacts from the deposited first non-epitaxial layer and first metal layer on the first source/drain regions by annealing the deposited first non-epitaxial layer and the first metal layer, and forming second metal alloy contacts from the deposited second non-epitaxial layer and second metal layer on the source/drain regions by annealing the deposited second non-epitaxial layer and the second metal layer.

In another embodiment, a method includes, for example, providing an intermediate semiconductor structure having a substrate and a gate thereon and source/drain regions adjacent the gate, and depositing a non-epitaxial layer on the source/drain regions.

In another embodiment, a semiconductor structure includes, for example, a semiconductor substrate having a gate disposed thereon, a pair of source/drain regions formed on opposite sides of and extending beneath the gate, the pair of source/drain regions having an n-type or p-type conductivity, and metal alloy contacts disposed on the source/drain regions, the metal alloy contacts formed from an annealed non-epitaxial layer and metal layer disposed on the pair of source/drain regions.

Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the present disclosure are described in detail herein and are considered a part of the claims.

DETAILED DESCRIPTION OF THE DISCLOSURE

The present disclosure and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the disclosure in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the present disclosure, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying concepts will be apparent to those skilled in the art from this disclosure. Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.

FIG. 3illustrates an nFET300according to an embodiment of the present disclosure. For example, nFET300may generally include silicon substrate310having a gate320disposed thereon. A pair of source/drain regions330are disposed on opposite sides of gate320. The source and drain regions include an epitaxially grown portions332of silicon substrate310, and a III-V metal alloy337. As described in greater detail below, III-V metal alloy337may be formed from a non-epitaxially grown III-V layer disposed on the epitaxially grown portions332, and a metal layer disposed on non-epitaxially grown III-V layer, which are annealed to form a III-V metal alloy337.

As will be appreciate from the description below, features of the present disclosure may include self-aligned and non-epitaxial contacts, self-aligned and non-epitaxial process that reduces process complexity, lower SBH from about 0.4 eV to less than about 0.1 eV (about 5 times the reduction in contact resistivity), independent control of SBH for nFETs and pFETs (Band-Edge through FLP), and opportunity to use a single metal for nFETs and N/P FETs (reduce process complexity).

FIGS. 4-15diagrammatically illustrate a method for use in forming nFETs and pFETs according to embodiments of the present disclosure. In this embodiment, an annealing process results in contacts for the pFETs and the nFETs being formed at the same time.

With reference toFIG. 4,FIG. 4illustrates a cross-sectional view of an intermediate semiconductor structure400having, for example, a substrate410such as a bulk semiconductor substrate, a first gate430and a second gate470disposed on or over substrate410, first spacers disposed440along sides of first gate430, second spacers480disposed along sides of first gate470, first source/drain regions430and second source/drain regions470. First source/drain regions430may include first sources/drains432such as a Si/SiGe doped portions of substrate410, and second sources/drains472may include a Si doped portion of substrate410.

For example, intermediate structure400may be formed using conventional processes as know in the art. The bulk semiconductor substrate may be operable for forming, as described below, nFET structures and pFET structures such as transistors. It will be appreciated that the process may include first forming nFET structures, then pFET structures, or vice-versa. The plurality of gates may be “dummy” gates, in that they may be later removed and replaced with metal gates in a replacement gate process. In other embodiments, the intermediate semiconductor structure may include metal gates. Substrate410may be formed from silicon or any semiconductor material including, but not limited to, silicon (Si), germanium (Ge), a compound semiconductor material, a layered semiconductor material, a silicon-on-insulator (SOI) material, a SiGe-on-insulator (SGOI) material, and/or a germanium-on-insulator (GOI) material, or other suitable semiconductor material or materials. As one skilled in the art will understand, where, as in the present example, a semiconductor material is used, many gates may be formed, is repeated a large number of times across the substrate such as a wafer.

As shown inFIG. 5, a non-epitaxial Ge layer500is deposited on the intermediate structure ofFIG. 4and may include deposition over the source/drain regions. Deposited layer500may be formed by an atomic layer deposition (ALD), a chemical vapor deposition (CVD), a physical vapor deposition PVD, or other suitable deposition process. Deposited layer500may be about 1 nanometer thick to about 10 nanometers thick. A low temperature conformal oxide550is deposited on layer500. Layer550such as a conformal oxide layer such as atomic layer deposited silicon oxide, may be about 5 nanometers thick to about 10 nanometers thick and may serve as a protective oxide for subsequent processing such as etching. As described below, deposited layer500are used for forming the sources/drains of the nFETs.

As shown inFIG. 6, a fill material600such as a low temperature amorphous silicon or flowable amorphous silicon is deposited on the structure ofFIG. 5. Fill material600may be subject to a chemical mechanical planarization (CMP) process resulting in fill material600disposed between the gates such as in cavities between the gates. A patterned hard masks650(only one of which is shown inFIG. 6) is deposited on fill material600. For example, patterned hard mask600may be formed from deposition of a SiN layer using conventional lithography and etching techniques.

Portions of fill material600are remove such as an amorphous silicon removal process (similar to a typical PC pull or other suitable process) to expose portions of conformal oxide550and non-epitaxial Ge layer500corresponding to the nFET regions in the intermediate structure ofFIG. 6. Thereafter, portions of the conformal oxide550in the nFET regions is removed, e.g., a dilute HF removal process or other suitable removal process to remove the protective oxide, followed by removal of portions of the non-epitaxial Ge layer500in the nFET regions, e.g., a dilute H2O2removal process or other suitable process, resulting in the structure shown inFIG. 7. For example, remaining non-epitaxial Ge layer510, remaining conformal oxide portions560, and remaining fill material portions610, and hard masks650being disposed over the pFET regions.

As shown inFIG. 8, a non-epitaxial III-V layer700is deposited on the structure ofFIG. 7, forming a layer on the source/drain regions of the nFET regions. Thereafter, a protective layer750such as a low temperature conformal protective oxide is deposited on non-epitaxial III-V layer700. An optical dispersive layer (ODL) or other suitable layer such as an optical planarization layer (OPL) may be deposited over the structure and portions removed as is known in the art to formed masks800over the source/drain regions in the nFET regions. Masks800may have a depth of about 20 nanometers or other suitable depth.

As shown inFIG. 9, masks800may be used in an etch process to remove portions of the protective layer750(FIG. 8) and portions of the non-epitaxial III-V layer700(FIG. 8) resulting in remaining protective layer portion751and remaining non-epitaxial III-V layer portions760.

Hard masks650such as SiN hard masks are removed such as using a hot phosphorus process, remaining fill material portions610is removed such as an amorphous silicon removal that may be similar to a typical PC pull resulting in the structure, and an etch process to remove masks800resulting in the structure shown inFIG. 10.

With reference toFIG. 11, an optical dispersive layer (ODL) or other suitable layer such as an optical planarization layer (OPL) may be deposited over the structure and portions removed as is known in the art to form masks900over the sources/drains in the pFET regions and the nFET regions. Masks900may have a depth of about20nanometers or other suitable depth.

An etch process is performed on the structure ofFIG. 11to remove portions of the remaining protective layer560and to remove portions of the remaining non-epitaxial III-V layer510resulting in further remaining non-epitaxial III-V layer portion520and further remaining protective layer portion570as shown inFIG. 12. Thereafter, hard masks900may be removed such as using an etch process.

The remaining conformal protective oxide layer570(FIGS. 12) and770(FIG. 12) are removed such as using a dilute HF process to remove the protective oxide on the nFET regions and the pFET regions. Thereafter, a metal layer1000is deposited resulting in the structure ofFIG. 13. The deposited metal layer may be a Ti/TiN which may be deposited on both the nFET and pFET regions. As will be appreciated, a technique of the present disclosure may result in using a single step and a single metal layer that is optimized for use in both the nFET and pFET region.

The structure ofFIG. 13is annealed such that the Ti/TiN forms an alloy with the remaining III-V portions520(FIG. 12) and the remaining Ge portion720to form, as shown inFIG. 14, p-contacts1100in contact with the Si/SiGe sources/drains432, and n-contacts1200in contact with the Si sources/drains472. Such a technique of the present disclosure enables an integration flow that is able to pin contacts to silicon conduction band (EC) and silicon valence band (EV) independently.

A metal layer such as tungsten is deposited followed by a chemical mechanical planarization (CMP) process resulting in metal contacts1300and1400.

FIGS. 16-21diagrammatically illustrate methods for use in forming nFETs and pFETs according to embodiments of the present disclosure. In this embodiment, a first annealing process results in contacts for the pFETs, followed by a second annealing process resulting in contact for the nFETs.

In this embodiment, initially an intermediate structure (e.g., may be the same as shown inFIG. 4) upon with a non-epitaxial Ge layer2500is deposited on the intermediate structure deposition over the source/drain regions for forming nFETs and pFETs followed by a metal layer2550deposited on non-epitaxial Ge layer2500resulting in the structure ofFIG. 16. Deposited layer2500may be formed by an atomic layer deposition (ALD), a chemical vapor deposition (CVD), a physical vapor deposition PVD, or other suitable deposition process. Deposited layer2500may be about 5 nanometers thick. The deposited metal layer may be a Ti/TiN (POR) which may be deposited on the nFET and pFET regions.

The structure ofFIG. 16is annealed such that the Ti/TiN and the non-epitaxial Ge layer2500forms a metal alloy3100as shownFIG. 17.

As shown ifFIG. 18, a suitable protective pattern is deposited followed by deposition a non-epitaxial III-V layer2700is deposited on the intermediate structure deposition over the source/drain regions for forming nFETs and on the protective patterning followed by a protective layer2750such as an oxide layer deposited on non-epitaxial III-V layer2700.

With reference toFIG. 19, operable application of masks2800, removal of portions of the protective layer2750(FIG. 18), non-epitaxial III-V layer2700(FIG. 18), and the protective patterning, and operably application of masks2850may be performed.

As shown inFIG. 20, a metal layer2900such as titanium nitride is operably deposited, operably followed by a metal fill3400.

The structure ofFIG. 21is annealed to form metal alloy contacts3200.

FIGS. 22-26diagrammatically illustrate a method for use in forming nFETs and pFETs according to an embodiment of the present disclosure. In this embodiment, a single annealing process results in formation of metal alloy contacts for the nFETs and the pFETs at the same time.

In this embodiment, initially an intermediate structure (e.g., may be the same as shown inFIG. 4) upon with a non-epitaxial Ge layer4500is deposited on the intermediate structure deposition over the source/drain regions for forming nFETs and pFETs followed by a metal layer4550deposited on non-epitaxial Ge layer4500resulting in the structure ofFIG. 22. Deposited layer4500may be formed by an atomic layer deposition (ALD), a chemical vapor deposition (CVD), a physical vapor deposition PVD, or other suitable deposition process. Deposited layer4500may be about 5 nanometers thick. The deposited metal layer may be a Ti/TiN (POR) which may be deposited on the nFET and pFET regions.

As shown ifFIG. 23, a suitable protective pattern is deposited followed by deposition a non-epitaxial III-V layer4700is deposited on the intermediate structure deposition over the source/drain regions for forming nFETs and on the protective patterning followed by deposition of a metal layer4900such as titanium, and then a protective layer4750such as an oxide layer deposited on non-epitaxial III-V layer4700.

The structure ofFIG. 25is annealed to form metal contact5100and5200. As shown inFIG. 26, metal fill4400may be applied in the cavities above the metal alloy contacts.

FIG. 27illustrates a flowchart of a method6000according to an embodiment of the present disclosure. Method6000may include at6100providing an intermediate semiconductor structure having a substrate and a gate thereon and source/drain regions adjacent the gate, at6200depositing a non-epitaxial layer on the source/drain regions, at6300deposing a metal layer on the non-epitaxial layer, and at6400forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

FIG. 28illustrates a flowchart of a method7000according to an embodiment of the present disclosure. Method7000includes at7100providing an intermediate semiconductor structure having a substrate having a first plurality of gates having first source/drain regions adjacent the first plurality of gates and a second plurality of gates having second source/drain regions adjacent the second plurality of gates, at7200depositing a first non-epitaxial layer on the plurality of first source/drain regions, at7300depositing a second non-epitaxial layer on the plurality of second source/drain regions, at7400depositing a first metal layer on the first non-epitaxial layer, at7500depositing a second metal layer on the second non-epitaxial layer, at7600forming first metal alloy contacts from the deposited first non-epitaxial layer and first metal layer on the first source/drain regions by annealing the deposited first non-epitaxial layer and the first metal layer, and at7700forming second metal alloy contacts from the deposited second non-epitaxial layer and second metal layer on the source/drain regions by annealing the deposited second non-epitaxial layer and the second metal layer.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the present disclosure and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.