Organic EL drive circuit and organic EL display device using the same organic EL drive circuit

A first input terminal and a second input terminal of an organic EL drive circuit IC are arranged on both sides of the organic EL drive circuit IC, which are contiguous to sides of a plurality of IC's having identical circuit constructions to the organic EL drive circuit IC and arranged contiguously to the organic EL drive circuit IC, and a first output terminal and a second output terminal of the organic EL drive circuit IC are provided similarly. When a plurality of IC's are arranged along a column line of an organic EL display panel, it is possible to send a reference current generated by one of the IC or a current corresponding to the reference current to other IC's arranged on left or right sides of the one IC and the other IC's can receive the current sent from the first or second output terminal of the one IC through first or second input terminals of the other IC's, which are provided on sides of the other IC's adjacent to the one IC, and use the currents as reference currents thereof by reference current selector circuits thereof.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an organic EL drive circuit and an organic EL display device using the same organic EL drive circuit and, in particular, to an organic EL drive circuit and an organic EL display device, which can reduce unevenness of luminance on a display screen of an organic EL panel of the organic EL display device used in a portable telephone set, etc., due to difference in characteristics between column driver IC's, can reduce manufacturing cost of the column driver IC's and, particularly, is suitable for high luminance color display.

2. Description of the Related Art

An organic EL display panel of an active or passive type organic EL display device for use in a portable telephone set including 396 (132×3) terminal pins (column pins) for column lines (anode side drive lines of organic EL elements or data lines) and 162 terminal pins for row lines has been proposed. These numbers of the terminal pins for column lines and row lines tends to be increasing.

With such increase of the number of terminal pins, a plurality of column driver IC's becomes necessary on, particularly, the column line side. For example, in a full color QVGA, the number of terminal pins for each of the three primary colors becomes 120, so that a total of 360 terminal pins are necessary, that is, three column driver IC's are presently necessary. Therefore, there is a problem that unevenness of luminance appears on a display screen of an organic EL display device, due to difference in characteristics between column driver IC's and, particularly, due to variation of drive currents of the column driver IC's.

For example, U.S. Pat. No. 6,747,417 (corresponding to JP2003-288045A) discloses a technique for solving the above problem, by restricting unevenness of drive currents between column driver IC's by utilizing the fact that values of integrated paired resistors are substantially equal.

Since, however, the constructions of the reference current generator circuits of the master column driver IC and the slave column driver IC of the U.S. Pat. No. 6,747,417 are different, these column driver IC's shall be manufactured separately, resulting in that the manufacturing cost of the driver IC's becomes high.

On the other hand, the size of organic EL display panel tends to be increased and a large size organic EL display panel requires three or more column driver IC's. Further, the increase of the number of terminal pins makes unevenness of drive currents of terminal pins considerable. Therefore, in order to improve unevenness of drive currents, highly precise drive currents are required. As to the drive current control utilizing the paired resistors, since unevenness of resistance values of the paired resistors influences the drive currents, the use of paired resistors can not respond to the present request of further reduction of luminance unevenness.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an organic EL drive circuit, which is capable of reducing luminance unevenness on a display screen of an organic EL display panel due to difference in characteristics between column driver IC's for driving the organic EL display panel and of reducing the fabrication cost of column driver IC's.

Another object of the present invention is to provide an organic EL display device capable of reducing luminance unevenness on a display screen of an organic EL display panel due to difference in characteristics between column driver IC's for driving the organic EL display panel and of reducing the fabrication cost of column driver IC's.

According to the present invention, in order to achieve the above objects, an integrated organic EL drive circuit or an organic EL display device using the same organic EL drive circuit, which is constructed with driver IC's and generates drive currents, which are to be supplied to terminal pins of the organic EL display device, on the basis of a reference current is featured by comprising a first and second input terminals provided for inputting currents, which are in phase with a reference current supplied externally of the driver IC's and have current values each corresponding to that of the reference current, a first and second output terminals, a reference current selector circuit for selecting one of the current inputted through the first input terminal, the current inputted through the second input terminal and the reference current, a current inverter circuit for inverting the one current selected by the reference current selector circuit with respect to the reference current and a current mirror circuit having an input side transistor and a first and second output side transistors and responsive to an output current of the current inverter circuit supplied to the input side transistor to generate currents having values corresponding to the value of the reference current in the first and second output side transistors and supply the currents to the first and second output terminals, respectively.

The driver IC is rectangular in plan view and the first and second input terminals thereof are arranged on respective sides of the rectangular IC, which face to sides of similar driver IC's when the latter driver IC's are provided adjacent to the driver IC. Similarly, the first and second output terminals of the driver IC are provided on sides thereof, respectively, such that the output terminals face to sides of similar driver IC'S.

Since, in the present invention, the first and second input terminals of the driver IC are arranged on respective sides of the rectangular IC, which face to sides of similar driver IC's when the latter driver IC's are provided adjacent to the driver IC and the first and second output terminals of the driver IC are provided on sides of the similar IC's, it is possible, when a plurality of driver IC's are arranged adjacently along a column line side of an organic EL display panel, to send the reference current generated in one of the driver IC (master driver IC) or a current corresponding to the reference current to a right side IC (slave driver IC), a left side IC (slave driver IC) or the both side driver IC's through the first and second output terminals. Each of the slave driver IC's arranged adjacent to the master driver IC can receive the current from the first or second output terminal of the master driver IC through one of a first input terminal and/or a second input terminal provided on sides thereof facing to the sides of the master driver IC and utilize it as a reference current thereof by a reference current selector circuit thereof.

In such case, since the input terminals and the output terminals of each driver IC are provided in adjacent sides thereof, terminal connecting lines between the IC's are short and variation of currents outputted from these IC's becomes negligibly small.

Therefore, current values of reference currents of the adjacently arranged IC's can be made substantially equal to the value of the reference current generated by the master driver IC, so that it is possible to reduce luminance unevenness on a screen of the organic EL display device due to difference in characteristics between the column driver IC's, which drive the organic EL display panel. Further, the master driver IC and the slave driver IC may have identical constructions and a number of driver IC's can be arranged in close relation to each other. Therefore, the manufacturing cost of the column driver IC can be reduced.

Incidentally, the column driver in this specification may be a driver IC for driving data line of the organic EL panel of the active matrix type or a driver IC for driving column lines of the organic EL panel of the passive matrix type.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

InFIG. 2, a reference numeral10depicts an organic EL display device of active matrix type and reference numerals11,12and13depict column driver IC's of an organic EL drive circuit of the organic EL display device.

The column driver IC's11to13have organic EL drive circuits having identical circuit constructions and are arranged closely to each other. In order to select one of a current supplied externally of an IC and a current generated in the IC and supply the selected current to an inner circuit thereof as a reference current, each of these column driver IC's includes a reference current generator circuit1, a reference current selector circuit2, a pair of output terminals for transmitting the reference current to one of adjacent IC's and a pair of input terminals for receiving the reference current from one of adjacent IC's.

Incidentally, inFIG. 2, the column driver IC12is a master driver IC and the driver IC's11and13arranged on both sides of the master driver IC are slave driver IC's.

As shown by the driver IC12as an example inFIG. 1, each of the driver IC's11to13includes the reference current generator circuit1, the reference current selector circuit2, a white balance regulator circuit3and a reference current distributor type D/A converter circuit4, etc. The reference current distributor type D/A converter circuit4includes D/A conversion blocks4a. . .4i. . .4nprovided correspondingly to respective terminal pins of the organic EL panel.

The reference current distributor type D/A converter circuit4is constructed with a current mirror circuit including an input side transistor TNA and the D/A conversion blocks4a. . .4i. . .4neach including a plurality of output side transistors and a corresponding number of switch circuits (not shown) connected in series with the respective output side transistors. The current mirror circuit constitutes a current switching D/A converter circuit. Thus, a reference drive current for driving the input side transistor TNA is distributed to the respective D/A conversion blocks4a. . .4i. . .4n. The D/A conversion blocks4a. . .4i. . .4ncorresponding to respective terminal pins of the organic EL display panel generate analog currents corresponding to values of a display data DAT by converting the display data DAT supplied thereto by ON/OFF controlling the switch circuits according to the display data DAT.

Incidentally, output terminals P1. . . Pi . . . Pn inFIG. 1are output terminals of the driver IC12provided correspondingly to the terminal pins of the organic EL display panel5, respectively, and reset switches SW are provided correspondingly to the respective output terminals P1. . . Pi . . . Pn.

The white balance regulator circuit3is provided for each of R, G and B colors and data corresponding to each of R, G and B colors, which is stored in a register7, is set in a D/A conversion block3aof the white balance regulator circuit3. The white balance regulator circuits3generate white balance regulated reference drive currents by converting the data of the respective R, G and B colors. The circuit construction from the reference current generator circuit1to the reference current distributor type D/A converter circuit is provided for each of R, G and B colors. Since the circuit constructions for the R, G and B colors are identical, an operation thereof is similar.

Incidentally, the data for R, G and B colors supplied externally to an MPU9as input data is temporarily stored in a non-volatile memory of the MPU9and set in the register7by transferring it to the register7.

Returning toFIG. 2, input terminals12ato12c(shown by black square mark inFIG. 2) of the driver IC12. The input terminals12aand12care provided on the side of the driver IC12adjacent to the driver IC11and the input terminal12bis provided on the side of the driver IC12adjacent to the driver IC13. Output terminals12dand12eare output terminals (white square mark inFIG. 2) of the driver IC12. The output terminal12dis provided on the side of the driver IC11and the output terminal12eis provided on the side of the driver IC12adjacent to the driver IC13. Positions of one of the opposite sides of the driver IC12, at which the input terminal and the output terminal are provided, are reversed with respect to positions of the other side of the driver IC12.

That is, the input terminal12bof the driver IC12corresponds in position to the output terminal13dof the driver IC13and the output terminal12eof the driver IC12corresponds in position to the input terminal13aof the driver IC13. The input terminal12aof the driver IC12corresponds in position to the output terminal11eof the driver IC11and the output terminal12dof the driver IC12corresponds in position to the input terminal11bof the driver IC11. Therefore, the output terminals (white square marks) and the input terminals (black square marks) of the adjacent driver IC's are arranged in the corresponding positional relations.

Therefore, the output terminal12dof the driver IC12is adjacent to the input terminal11bof the driver IC11and connected thereto by a short wiring line14. The output terminal12eof the driver IC12is adjacent to the input terminal13aof the driver IC13and connected thereto by a short wiring line15.

Incidentally, the input terminals11c,12cand13creceive signals SEL for setting the driver IC's11,12and13to a master IC or a slave IC. Since there is no corresponding relation between the adjacent driver IC's, terminal pins provided in arbitrary sides of the driver IC's may be assigned. Further, the rectangular driver IC is arranged such that a major side thereof extends along the terminal pins arranged in the column direction of the organic EL display panel5, unlike the usual IC. It should be noted inFIG. 2, that an input terminal12f(seeFIG. 1) for a clock CLK, which is necessary to set the setting signals SEL, is not shown inFIG. 2.

As shown inFIG. 2, the D/A conversion blocks4ato4nof the reference current distributor type D/A converter circuit4are responsive to the display data DAT from the MPU7through the registers6to generate drive currents (usually, sink currents) corresponding to display luminance every moment by amplifying the reference drive current, which is supplied from the D/A conversion block3aof the white balance regulator circuit3, correspondingly to the display data. The thus generated drive currents are sent to pixel circuits5aof the active matrix type organic EL panel5through output terminals P1. . . Pi . . . Pn on the side of column line (data line) to charge capacitors C of the pixel circuits5aand drives organic EL elements5bof the pixel circuits5a.

As shown inFIG. 1andFIG. 2, each of the reference current generator circuits1includes a reference current source1aand a current inverter circuit1band a reference current selector circuit2is provided between the reference current source1aand the current inverter circuit1b.

The reference current selector circuit2is responsive to the setting signals SEL from a control circuit8to select one of an internally generated reference current Iref, a current Ir from a preceding IC and a current Ir from a succeeding IC as the reference current.

This circuit is constructed with analog switches (transmission gates)2ato2cand a shift register2d. The shift register2dis constructed with three flip-flop (FF) circuits connected in series. Incidentally, the setting signal SEL is set in the shift register2das 3-bit data, correspondingly to the shift clock CL, as to be described later.

The analog switches2aand2bare provided correspondingly to the respective input terminals12aand12band one ends of the analog switches are connected to the respective input terminals12aand12b. One end of the analog switch2cis connected to the reference current source1aand receives the reference current Iref from the reference current source1a. The other ends of the analog switches2ato2care connected commonly to an input terminal of the current inverter circuit1b.

An input terminal of an initial stage flip-flop of the shift register2dis connected to the input terminal12cand Q outputs of the flip-flops are supplied to non inversion side input terminals and Q-outputs (inverted Q outputs) thereof are supplied to the inversion input terminals as ON/OFF control signals for the analog switches2ato2c. Among the analog switches2ato2c, an analog switch corresponding to a flip-flop set to data “1” is driven. The initial stage flip-flop of the shift register2dcorresponds to the analog switch2a, the next stage flip-flop corresponds to the analog switch2band the last stage flip-flop corresponds to the analog switch2c. The analog switch corresponding to the flip-flop, which is set to “1”, is turned ON and the analog switch driven by the flip-flop set to “0” is turned OFF.

The shift register2dis responsive to a shift clock CL from a clock input terminal2f(not shown inFIG. 2) to store the 3-bit data in the flip-flops by sequentially shifting the data “1” inputted to the initial stage flip-flop. Thus, the setting signals SEL are set in the respective driver IC's to thereby the selection of the state of the driver IC's, master or slave. Incidentally, the shift register2dis reset to “0” in an initial state.

When the analog switch2ais ON and the other analog switches are OFF, the setting signal SEL=“001” is set in the shift register2d. When the analog switch2bis ON and the other analog switches are OFF, the setting signal SEL=“010” is set in the shift register2d. When the analog switch2cis ON and the other analog switches are OFF, the setting signal SEL=“100” is set in the shift register2d. The 3-bit data is sent from the control circuit8to the input terminal12ctogether with the shift clock CL.

Incidentally, the 3-bit data for selecting the reference current is simultaneously inputted from the control circuit8to the input terminals11cand13cof the respective driver IC's11and12.

When the initial stage flip-flop is set to “1” and the analog switch2ais turned ON, the reference current selector circuit2of the driver IC12selects the current Ir supplied from the preceding stage driver IC11to the input terminal12athrough the analog switch2a. In such case, the driver IC becomes a slave driver IC. When the next stage flip-flop is set to “1” and the analog switch2bis turned ON, the reference current selector circuit2of the driver IC12selects the current Ir supplied from the succeeding stage driver IC13to the input terminal12bthrough the analog switch2b. In such case, the driver IC12becomes a slave driver IC. When the last stage flip-flop is set to “1” and the analog switch2cis turned ON, the reference current selector circuit2of the driver IC12selects the reference current Iref from the reference current source1athrough the analog switch2c. Thus, the driver IC12becomes a master driver IC. Incidentally, the reference current source1ais driven by a power source line +Vcc.

The current selected by the reference current selector circuit2is supplied to the current inverter circuit1b. The current inverter circuit1bis constructed with a current mirror circuit including an input side N channel MOS transistor TN1and an output side N channel MOS transistor TN2. The diode-connected transistor TN1has a drain connected to output terminals of the analog switches2ato2cand a source grounded.

The N channel MOS transistor TN2has a drain connected to a drain of an input side transistor TPa and a source grounded.

Therefore, either the reference current Iref of the reference current source1aor the current Ir, which is in phase to the reference current Iref and discharged from one of the input terminals12aand12b, is inputted to the current inverter circuit1b. The current inverter circuit1bgenerates a sink current (inverted current) as a mirror circuit and supplies the mirror current to the drain of the input side transistor TPa of the white balance regulator circuit3.

The white balance regulator circuit3duplicates the mirror current and supplies the duplicated mirror currents to the output terminals12dand12eand the reference current distributor type D/A converter circuit4. The white balance regulator circuit3is a current switching D/A converter constructed with a current mirror circuit composed of the D/A converter block3aincluding a diode-connected, input side P channel MOS transistor TPa, two output side P channel MOS transistors TP1and TP2and a plurality of output side transistors. The switch circuits (not shown) are connected in series to the output side transistors of the D/A converter block3a, respectively. The transistors TP1and TP2supply the currents Ir each corresponding to the reference current to the driver IC's11and13, which are the slave driver IC's.

Sources of the output side transistors TP1and TP2and sources of the output side transistors TPc to TPm of the D/A conversion block3aare connected to the power source line +Vcc, voltage of which is higher than the voltage of the power source line +VDD. Drains of the transistors TP1and TP2are connected to the output terminals12dand12e, respectively.

The D/A conversion block3ais responsive to the data stored in the register7to generate a reference drive signal Iro, white balance of which is regulated, by converting the data. The reference drive current is supplied to the reference current distributor type D/A converter circuit4.

Channel width (gate width) ratio of the input side transistors TPa to each of the transistors TP1and TP2is 1:1. The reference currents Ir, each of which is substantially equal to the reference current Iref and is in phase with the reference current Iref, are outputted from drains of the transistors TP1and TP2to the output terminals12dand12eas discharge currents, respectively. The transistors TP1and TP2are arranged preceding to the D/A converter circuit3awith respect to the input side transistor TPa. Therefore, it is possible to generate a current Ir substantially equal to the reference current Iref with high precision.

Each D/A conversion block4is constructed with a plurality of output side transistors weighted correspondingly to weights of an 8-bit display data and switch circuits (not shown) connected in series with the weighted output side transistors, as a current switching D/A converter circuit. The switch circuits connected in series with the output side transistors and corresponding to the weights are ON/OFF controlled according to the display data in the register6and generate an analog current value, which is a total output currents of the output side transistors thus selected. The total current is outputted to the respective output terminals P1. . . Pi . . . Pn as the drive currents.

As to the generation of the reference current, which is the base for generating the drive current, the driver IC12becomes the master driver IC and the driver IC's11and13become the slave driver IC's by the setting of the 3-bit data of the setting signal SEL.

The output terminal12dof the driver IC12is connected to the input terminal11bof the slave driver IC11through a wiring line14(seeFIG. 2) and the output terminal12eof the driver IC12is connected to the input terminal13aof the slave driver IC13through a wiring line15(seeFIG. 2). The wiring lines14and15for connecting terminals of the adjacent driver IC's are very short.

Therefore, the drain current of the transistor TP1of the master driver IC12through the output terminal12dand the wiring line14, which is very short, to the input terminal11bof the slave driver IC11.

The output terminals12aand12bare grounded. Incidentally, the output currents of the transistors TP1and TP2are in the order of μA, a total power consumption is not substantially increased even when these currents flow to the ground GND. The output terminals11a,11dand11eof the slave driver IC11and the output terminals13b,13dand13eof the slave driver IC13are also grounded.

Since the driver IC12is the mater driver IC, there is no current from the input terminal12a. Therefore, the setting signal SEL=“100” supplied from the control circuit8is stored in the shift register2d. Thus, the reference current source1ais selected and the reference current Iref is inputted to the current inverter circuit1b.

On the other hand, the slave driver IC11receives the setting signal SEL=“010” from the control circuit8. The setting signal is stored in the shift register2d. Therefore, the input terminal11bis selected and the current inverter circuit1breceives not the reference current Iref from the reference current source1aof the slave driver IC11but the current Ir corresponding to the reference current Iref from the drain of the transistor TP1of the master driver IC12through the input terminal11band the analog switch2b.

The slave driver IC13is responsive to the setting signal SEL=“001” from the control circuit8to store it in the shift register2d. Therefore, the input terminal13ais selected and the current inverter circuit1breceives the current Ir corresponding to the reference current Iref from the drain of the transistor TP2of the driver IC12through the input terminal13aand the analog switch2c.

Therefore, the driver IC's11and13supply the currents Ir, each of which corresponds to the reference current Iref from the reference current source1aof the reference current generator circuit1and is in phase with the reference current Iref, to their inner circuits, respectively. The input side P channel MOS transistors TPa of the white balance regulator circuits3of the slave driver IC's11and13are driven by the current Ir through the current inverter circuits1bof the slave driver IC's11and13as in the driver IC12, respectively.

As a result, the white balance regulator circuits3of the slave driver IC's11and13generate the reference drive currents Iro in the D/A converter circuits3aon the basis of the respective reference currents Ir and the reference current distributor type D/A converter circuits4are driven by the reference drive currents Iro, respectively. Therefore, the drive currents to be supplied to the terminal pins of the organic EL display panel5are generated by the driver IC's11and13.

As described, since on the basis of the reference current Iref of the reference current generator circuit1aof the driver IC12, the drive currents each of which is substantially equal to the reference current Iref, are generated by the slave driver IC's11and13arranged on both sides of the driver IC12through the identical circuits and the short wiring lines14and15, the variation of drive currents is reduced.

In the described embodiment, the current inverter circuit1btakes in the form of the current mirror circuit. However, the current inverter circuit may be substituted by a general current inverting amplifier constructed with an operational amplifier, etc. In any case, it is not necessary to make the input current of the current inverter circuit1bequal to the output current thereof. It is enough that, in each driver IC, currents each corresponding to the reference current Iref of the reference current source1aof the master driver IC are obtained at the input and output terminals.

The circuit for outputting the reference current Ir to the output terminals12dand12eis not limited to the white balance regulator circuit. For example, any current mirror circuit having an input side transistor driven by the reference current Iref or the reference current Ir and output side transistors for generating the reference currents Ir can be used in lieu of the white balance regulator circuit.

The white balance regulator circuit3is provided for each of R, G and B colors. Instead of the three white balance regulator circuits3, it is possible to provide a single white balance regulator circuit3for the three primary colors and a single current mirror circuit including three D/A converter circuits3afor the three primary colors. In such case, it is possible to use the circuit construction from the reference current generator circuit1to the white balance regulator circuit3commonly for the R, G and B colors.

Further, the input terminals12aand the output terminal12dare provided on one side (left side inFIG. 2) of the driver IC12and the input terminal12band the output terminal12eare provided on the other side (right side inFIG. 2) thereof. The input and output terminals provided on a side of each of the adjacent driver IC's, which faces to the one side of the driver IC12, and the input and output terminals provided on a side of the other adjacent driver IC, which faces to the other side of the driver IC12, are arranged in positions reversed with respect to those of the input and output terminals of the driver IC12so that the input terminal and the output terminals of the driver IC12face to the output terminal and the input terminal of each adjacent driver IC, respectively. However, the facing relation of positions of the terminals on the side of each adjacent driver IC with respect to the driver IC12may not be necessary although the length of the wiring line between the terminals of the driver IC's increases slightly or the wiring lines cross each other. Therefore, it is not necessary to arrange the terminals of the driver IC's in such the way that the terminals of one driver IC face the terminals of other driver IC's when the driver IC's are arranged adjacently.

In this embodiment, the reference current selector circuit2is responsive to the master/slave setting signal SEL from the control circuit8to select either the internal reference current Iref or the externally inputted current Ir. However, the reference current selector circuit2may select the reference current Iref or the current Ir by forming a contact wiring pattern in a layer, in which a ROM is formed, such that the reference current selector circuit2can be connected to a contact on the side to be selected at the same time when data is written in the ROM. In such case, the reference current selector circuit2can be made as a selector current, which is selected in the mask option processing of the fabrication steps when data is written in the ROM. Therefore, in such case, there is no need of inputting bit data for selection to the reference current selector circuit2. Further, there is no need of a hardware circuit including special logic circuit, etc., in this wiring connection. Alternatively, the reference current selector circuit may be constructed such that it includes fuses in respective wiring lines and the fuses are selectively cut in the fabrication step of the drive circuit.

Incidentally, so long as that the reference current selector circuit2selects, as the reference current thereof, either the reference current Iref of the reference current source1athereof or the externally supplied current Ir according to the data setting, it is possible, when the driver IC's are assembled to the display device and a display is made on the display device, to operate the slave driver IC's by separating them from the master driver IC after the reference current Iref of each driver IC is selected while watching unevenness of luminance on the display screen.

As described, in the present embodiment, the three driver IC's are provided in the organic EL display device. However, it is possible to send the current Ir of the driver IC11to a slave driver IC, which is provided preceding to the driver IC11, by connecting the output terminal11aof the driver IC to an input terminal of the slave driver IC. Similarly, it is possible to send the current Ir of the driver IC13to a slave driver IC provided succeeding to the driver IC13. In such case, the slave driver IC can operate as the slave driver IC as well as the master driver IC. An output terminal of the slave driver IC is not grounded.

Therefore, the present invention can be applied to an organic EL display device having four or more driver IC's. Only one of the driver IC's11and13can be used as the slave driver IC.

Further, the described embodiment is constructed with mainly MOS FET's. However, it can be constructed with mainly bipolar transistors. Further, the N channel transistors (or npn type transistors) may be replaced by P channel (or pnp) transistors and the P channel (or pnp) transistors may be replaced by N channel (npn) transistors.