Memory testing method and apparatus

A method of testing memory devices includes issuing a command to a Flash memory device, simultaneously monitoring at least one data bit of each Flash memory device for a ready indication, and then verifying the command was performed successfully in each Flash memory device. The command can be an erase command, a write command, or the like. The simultaneous monitoring can be performed by simultaneously asserting signals on output enable nodes of the memory devices, and monitoring bidirectional tester channels dedicated for this purpose. A test fixture includes memory device receptacles, a tester interface, and conductive paths to couple the tester interface to the memory device receptacles. The conductive paths include paths for dedicated bidirectional tester channels and shared bidirectional tester channels.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices, and in particular, the present invention relates to the testing of memory devices.

BACKGROUND OF THE INVENTION

Memory devices are typically manufactured many at a time. After manufacture, they are typically packaged and tested. Many current mechanisms for testing memory devices rely on a set of serial operations performed one at a time using expensive memory testers. One such mechanism is illustrated byFIGS. 1A and 1B.

FIG. 1Ais a prior art memory test configuration. Memory testing configuration100includes tester110and memory devices102,104, and106. Memory tester110includes bidirectional channels and drive-only channels. Bidirectional tester channels are channels that can source and sink data, and drive-only tester channels are channels that only source data, and do not sink data. Drive-only channels include channels112,114,116,118, and122. Each of these drive-only channels drive inputs on memory devices being tested. For example, drive-only channels112,114and116drive “output enable” nodes of memory devices102,104, and106, respectively. Drive-only channel118drives the “write enable” node on each of the memory devices in parallel. Drive-only channel122includes multiple physical channels, and drives the address bus.

Bidirectional tester channel120includes “n” physical channels, and is coupled to the data bus of each device to form a shared data bus. This configuration shares the data bus across all memory devices being tested, and allows the bidirectional tester channels to be time shared among multiple memory devices being tested.

FIG. 1Bshows an example sequence of operations performed by the memory test configuration of FIG.1A. The sequence ofFIG. 1Binclude operations152,154,156,158,160, and162. Operation150represents the memory command being tested. For example, operation152can be a “write” command during which data is written to a location being tested. The data is written to all three memory devices in parallel by virtue of the shared data bus and write enable signal as described above. During operations154,156, and158, the status of memory devices102,104, and106, respectively, is read. The time taken to read the status registers is shown at164.

Operation160repeats operations154,156, and158until all three memory devices report a status that indicates the command issued in operation152is complete. When all three memory devices report the appropriate status, operation162verifies that operation152was successfully executed. For example, for the case where operation152is a write command, operation162is a read operation that reads the data from the appropriate location, and compares it with the data written in operation152.

One drawback of the configuration ofFIG. 1Ais shown by the serial polling of status shown at164. The time taken by serial polling increases as more memory devices are added to the test, and the total time increases further for each time the polling sequence is repeated in operation160.

SUMMARY OF THE INVENTION

The above mentioned problems and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

In one embodiment, a method of testing memory devices includes issuing a command to a Flash memory device, simultaneously monitoring at least one data bit of each Flash memory device for a ready indication, and then verifying the command was performed successfully in each Flash memory device. The command can be an erase command, a write command, or the like. The simultaneous monitoring can be performed by simultaneously asserting signals on output enable nodes of the memory devices, and monitoring bidirectional tester channels dedicated for this purpose.

In another embodiment, a test fixture includes memory device receptacles, a tester interface, and conductive paths to couple the tester interface to the memory device receptacles. The conductive paths include paths for dedicated bidirectional tester channels and shared bidirectional tester channels.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is one memory testing system of the present invention.FIG. 2shows memory tester210and memory devices202,204, and206. Memory tester210can be any type of memory tester, including commercially available models from manufacturers such as Advantest. Memory devices202,204, and206can be any type of memory device. In some embodiments, memory devices202,204, and206are “Flash” memory devices that hold their state when power is off.

FIG. 2shows three memory devices labeled MEM1, MEM2, and MEMrto signify that “r” memories are present and coupled to memory device tester210. Each memory includes “i” address bits that are driven in parallel by drive-only channel212of memory device tester210. Output enable pins of each memory device are driven separately by drive-only tester channels. For example, the output enable pin of memory device202is driven by drive-only channel220, the output enable pin of memory device204is driven by drive-only channel222, and the output enable pin of memory device206is driven by drive-only channel224. Write enable pins of each memory device are coupled to shared drive-only channel218.

Each memory includes “n” data bits that communicate with memory device tester210on bidirectional channels214and216. A subset of the “n” data bits are coupled to a shared data bus. This subset includes “m” data bits from each memory device coupled to bidirectional channel216. Another subset of data bits on each memory device is coupled to memory device tester210using dedicated bidirectional channels214.

The term “dedicated,” as used herein, refers to a tester channel dedicated to a single node of a single memory device. As shown inFIG. 2, each of the “r” memory devices has “n-m” data bits coupled to dedicated bidirectional tester channels, for a total of r(n-m) dedicated bidirectional tester channels. By sharing some bidirectional tester channels, and dedicating the others, the total test time can be reduced. This is explained in more detail with reference to FIG.4. The embodiment ofFIG. 2shows the data bus of width “n” being split into two buses of arbitrary size. The embodiment ofFIG. 3, discussed below, shows an eight bit data bus split such that one data bit on each memory device is coupled to a dedicated tester channel, and seven data bits are coupled to shared bidirectional tester channels.

FIG. 3is another memory testing system of the present invention. Memory testing system300includes memory device tester310and memory devices302,304, and306. As discussed with reference toFIG. 2, “r” memory devices are present and coupled to memory device tester310. Each memory device has an eight-bit data bus shown as DQ[0. . .7]. Seven bits of the eight-bit data bus are coupled to share bidirectional tester channels316. The remaining one data bit of each memory device is coupled to a dedicated tester channel, shown inFIG. 3as314. As a result, the total number of dedicated tester channels in memory testing system300is equal to the number of memory devices being tested.

The output enable nodes of each memory device are driven by a separate drive-only tester channel, allowing them to be asserted simultaneously or separately. The address bits of each memory device are coupled to a shared address bus, such that each memory device receives the same address from memory device tester310. The write enable nodes of each memory device are also coupled to a shared drive-only tester channel, to allow parallel write operations to occur during testing.

In some embodiments, other nodes exist on the memory devices, and these nodes are driven by shared or dedicated, bidirectional or drive-only, tester channels. For example, in some embodiments, chip enable nodes exist on memory devices, and these nodes are driven in parallel by a shared drive-only tester channel.

FIG. 4shows operations performed by memory testing systems in accordance with the present invention. Sequence400includes operations402,404,406, and408. Operation402occurs when a memory device tester issues a command to devices under test. For example, this can correspond to memory device tester310issuing a command such as a write command or an erase command to memory devices302,304, and306(FIG.3).

In operation404, the memory device tester asserts the output enable signals simultaneously. Referring now back toFIG. 3, when the output enable signals are asserted for each memory device, each memory device drives eight bits of data onto the data bus connected to its DQ[0. . .7] nodes. Each memory device drives seven bits onto a shared data bus, and also drives a single data bit onto a dedicated bidirectional tester channel. Memory device tester310can separately monitor the state of each bit coupled to a dedicated bidirectional tester channel. This is shown by operation406in FIG.4.

Operation406corresponds to a memory device tester simultaneously monitoring the state of bidirectional tester channels dedicated to specific memory devices. This is in contrast to a serial polling operation that polls each memory device in sequence. In the embodiment ofFIG. 4, rather than serial polling, a subset of data from each memory device is monitored in parallel. The time taken by operation406is shown at410. The length of time410is controlled by the memory device tester, and is only as long as necessary to verify that each memory device is ready to continue. After completion of operation406, operation408is utilized to verify that the memory devices properly executed the command issued in operation402.

The method apparatus of the present invention is useful for any type of memory that can be tested in the manner described. A specific example using a Flash memory device is now presented. The example is for explanatory purposes only, and should not be construed as the only way to practice the invention. In a Flash memory device, a block of addresses is erased by issuing an “erase” command prior to performing a write command. To test the proper operation of the erase command, a memory device tester can issue the erase command and then verify, through a series of reads, that the correct addresses have been erased.

Flash memory devices include a status register that incorporates a “ready” bit. The ready bit is asserted by the memory device when a command executed by the memory device has finished. For example, when a Flash memory device receives an erase command, the ready bit is cleared, and is then asserted when the erase operation is complete. Prior memory testing systems, such as that described with reference toFIG. 1, serially read the status register in each memory device under test until all ready bits are asserted. The method and apparatus of the present invention, in contrast, simultaneously monitors the ready bit from each memory device using dedicated bidirectional tester channels.

When the ready bit is asserted by all of the memory devices under test, the operation is verified by the memory tester. Continuing the current example of an erase command, the memory tester sequentially asserts the output enable signals of the different memory devices under test to verify that the appropriate memory locations have been cleared.

FIG. 5is a perspective view of a test fixture in accordance with the present invention. Test fixture500includes printed circuit board520, tester interface514, and memory device receptacles502,504,506,508,510, and512. Six memory device receptacles are shown inFIG. 5, but this is not a limitation of the present invention. The memory device receptacles are electrically coupled to tester interface514by conductive paths530. Conductive paths530implement the signal paths shown inFIG. 3between the memory devices and the memory device tester. As such, some of conductive paths530are utilized for dedicated tester channels, and other conductive paths530are utilized for shared tester channels.

In the embodiment ofFIG. 5, tester interface514includes a connector coupled to ribbon cable522. In other embodiments, tester interface514is an interface other than a connector coupled to a ribbon cable. For example, in some embodiments tester interface514is a card edge connector, and test fixture500is a board that slides into a slot to be held in a chassis. The memory device receptacles shown in the embodiment ofFIG. 5include cavities to accept packaged parts. Any type of receptacle can be utilized to couple memory devices to printed circuit board520. For example, the memory device receptacles can be zero insertion force (ZIF) sockets that hold pin grid array devices, or can be single in-line memory module (SIMM) connectors.

FIG. 6shows a processing system in accordance with the present invention. System600includes processor602, memory604, and tester interface606. System600can also include many other devices such as memory controllers, input/output devices, and others. These other devices are omitted fromFIG. 6to accentuate the items remaining in the figure. Processor602can be a microprocessor, digital signal processor, embedded processor, microcontroller, or the like. Tester interface606serves as an interface to a memory device tester such as memory device tester310(FIG.3). System600can be included within a memory device tester, or can be a computer system separate from a memory device tester. For example, processor602can be a microprocessor in an industrial computer and tester interface606can be a general purpose interface bus (GPIB) interface to communicate with a stand-alone tester. Processor602is a processor capable of executing software that embodies any of the methods of the present invention, and memory604is a computer-readable medium capable of storing the software.

Conclusion

A memory testing system and method therefor have been described. A method of testing memory devices includes issuing a command to a Flash memory device, simultaneously monitoring at least one data bit of each Flash memory device for a ready indication, and then verifying the command was performed successfully in each Flash memory device. The command can be an erase command, a write command, or the like. The simultaneous monitoring can be performed by simultaneously asserting signals on output enable nodes of the memory devices, and monitoring bidirectional tester channels dedicated for this purpose. A test fixture includes memory device receptacles, a tester interface, and conductive paths to couple the tester interface to the memory device receptacles. The conductive paths include paths for dedicated bidirectional tester channels and shared bidirectional tester channels.