Bus interface system for power extraction

The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

FIELD OF THE DISCLOSURE

This disclosure relates generally to a digital bus interface system for power extraction.

BACKGROUND

A digital bus interface system is used to communicate data between components within an electronic device, such as a computer, a radio frequency (RF) front-end module, a cellular telephone, a tablet, a camera, and/or the like. The digital bus interface system generally includes at least one master integrated circuitry (IC) and one or more slave ICs. The master IC and the slave ICs are connected by bus lines and the master IC coordinates the transfer of data along the bus lines. The slave ICs perform commands (e.g., read and write commands) as coordinated by the master IC. Generally, the size of the digital bus interface system increases as more bus lines are provided in the digital bus interface system. The increase is due to the number of wires which must be routed between the master IC and slave ICs, and the number of pins for the master/slave ICs that must be dedicated to the bus lines. In modern communication systems, the space is at a premium and running multiple bus lines between a master IC and a slave IC may be spatially inefficient.

To reduce the number of bus lines, it is desirable to design a digital bus interface system that supplies power over a single bus line as well as communication. In addition, there is also a need to keep time efficiency and low noise level of the digital bus interface system.

SUMMARY

The present disclosure relates to a bus interface system, which includes a bus line, master integrated circuitry (IC), and slave IC. The bus line has a low state and a high state. The master IC is coupled to the bus line and configured to generate a data signal and transmit the data signal along the bus line. Herein, the data signal is a pulse width modulation (PWM) waveform having a high level and a low level. The bus line is in the high state when the data signal is at the high level, and the bus line is in the low state when the data signal is at the low level. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor to store power from the data signal on the bus line and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

In one embodiment of the bus interface system, the slave IC further includes an edge detection circuit, a reverse current detection circuit, a digital control circuit, and a field effect transistor (FET). Herein, the edge detection circuit is coupled to the bus line and configured to provide an edge detection signal, which is based on a voltage level of the bus line, to the digital control circuit. The reverse current detection circuit is coupled to the bus line and configured to provide a current detection signal, which is based on current direction on the bus line, to the digital control circuit. The digital control circuit is configured to receive the edge detection signal and the current detection signal, and configured to provide a control signal to open or close the FET. And the FET is coupled to the supply capacitor and the bus line.

In one embodiment of the bus interface system, the FET is a p-type FET (PFET) with an ON channel resistance between 1 and 3 ohms.

In one embodiment of the bus interface system, when the bus line transitions from the low state to the high state, the digital control circuit utilizes the edge detection signal from the edge detection circuit to turn on the FET. And when the bus line transitions from the high state to the low state, the digital control circuit utilizes the current detection signal from the reverse current detection circuit to turn off the FET.

In one embodiment of the bus interface system, when the bus line is in the low state, the FET is open to isolate the supply capacitor from the bus line. And when the bus line is in the high state, the FET is closed to provide a charging path between the bus line and the supply capacitor.

In one embodiment of the bus interface system, the slave IC further includes at least one Electromagnetic interference (EMI) suppression capacitor, which is coupled in shunt with respect to the bus line to remove voltage spikes from the data signal on the bus line.

In one embodiment of the bus interface system, the at least one EMI suppression capacitor has a smaller capacitance than the supply capacitor.

In one embodiment of the bus interface system, the slave IC further includes a diode, wherein an anode of the diode is coupled to the bus line and a cathode of the diode is coupled to the supply capacitor.

In one embodiment of the bus interface system, the slave IC further includes an edge detection circuit, a digital control circuit, and a FET. Herein, the edge detection circuit is coupled to the bus line and configured to provide an edge detection signal, which is based on a voltage level of the bus line, to the digital control circuit. The digital control circuit includes a digital counter and a control block. The control block is configured to provide a control block signal that responds to a counting number of the digital counter. The digital control circuit is configured to provide a control signal to open or close the FET. The control signal is based on the edge detection signal and the control block signal. And the FET is coupled to the supply capacitor and the bus line.

In one embodiment of the bus interface system, when the bus line transitions from the low state to the high state, the digital control circuit utilizes the edge detection signal from the edge detection circuit to turn on the FET. When the counting number of the digital counter reaches a threshold, the digital control circuit utilizes the control block signal to turn off the FET.

In one embodiment of the bus interface system, the counting number of the digital counter reaches the threshold before the bus line transitions from the high state to the low state.

In one embodiment of the bus interface system, the slave IC further includes a reverse current detection circuit. Herein, the reverse current detection circuit is coupled to the bus line and configured to provide a current detection signal, which is based on current direction on the bus line, to the digital control circuit.

In one embodiment of the bus interface system, when the slave IC transitions from an idle mode to a telegram mode, the digital control circuit utilizes the current detection signal from the reverse current detection circuit to turn off the FET.

In one embodiment of the bus interface system, the slave IC further includes an auxiliary standby circuit, which is configured to provide an auxiliary path between the supply capacitor and the bus line.

In one embodiment of the bus interface system, when the slave IC is in a telegram mode, the digital control circuit is configured to activate the reverse current detection circuit and disable the auxiliary standby circuit. When the slave IC is in an idle mode, the digital control circuit is configured to disable the reverse current detection circuit and activate the auxiliary standby circuit.

In one embodiment of the bus interface system, the master IC comprises a data modulator and a switch circuit. Herein, the data modulator is coupled between a power supply and ground and configured to provide a first path from the power supply and the bus line. The switch circuit is coupled between the power supply and the bus line, and configured to form a second path between the power supply and the bus line. The second path has a lower impedance than the first path. A combination of the data modulator and the switch circuit is configured to provide the data signal to the bus line.

In one embodiment of the bus interface system, the master IC further includes at least one EMI suppression capacitor, which is coupled in shunt with respect to the bus line to remove voltage spikes from the data signal on the bus line.

In one embodiment of the bus interface system, the master IC further includes at least one shunt capacitor, which is coupled in shunt between the power supply and the data modulator to reduce ripple variations.

In one embodiment of the bus interface system, the switch circuit includes a FET. Herein, a drain of the FET and a source of the FET are coupled to the bus line and the power supply, respectively. The FET has an ON channel resistance between 0.2 and 0.5 ohms.

In one embodiment of the bus interface system, the master IC includes a data modulator. The data modulator is coupled between a power supply and ground and configured to provide the data signal to the bus line. A slew rate dV/dt on the bus line is constant, when the bus line transitions from the low state to the high state or when the bus line transitions from the high state to the low state.

It will be understood that for clear illustrations,FIGS. 1-6may not be drawn to scale.

DETAILED DESCRIPTION

FIG. 1illustrates an exemplary bus interface system10according to one embodiment of the present disclosure. The bus interface system10includes master integrated circuitry (IC)12, slave IC14, and a bus line16. The bus line16is configured to transmit data as well as charge between the master IC12and the slave IC14.

In detail, the master IC12may include a data modulator18, a switch circuit20, one or more shunt capacitors22, and one or more first electromagnetic interference (EMI) suppression capacitors24. For simplicity and clarity, the master IC12does not show other circuits, such as a voltage regulation circuit, a read mode data receiver, and digital control circuitry. Herein, the data modulator18is coupled between a master power supply VIO and ground, configured to receive an UP input signal and a DN input signal, and configured to provide a first data signal D1to the bus line16. The switch circuit20is coupled between the master power supply VIO and the bus line16, and configured to form a low-resistance (between 0.2 and 0.5 ohms) path between the master power supply VIO and the bus line16. The switch circuit20is configured to receive an UP_2input signal and the DN input signal, and configured to add a second data signal D2to the bus line16.

A combination of the data modulator18and the switch circuit20is configured to generate a combined data signal SDATA transmitted along the bus line16. The combined data signal SDATA is a combination of the first data signal D1and the second data signal D2. When the combined data signal SDATA is at a high level, the bus line16is at a high state. When the combined data signal SDATA is at a low level, the bus line16is at a low state. The combined data signal SDATA may be a pulse width modulation (PWM) waveform, and may define data pulses to represent different logical values (e.g. bit values, logical symbols). The shunt capacitors22are coupled in shunt between the master power supply VIO and the data modulator18to reduce ripple variations. The first EMI suppression capacitor24is coupled in shunt with respect to the bus line16to provide high frequency filtering that removes voltage spikes from the combined data signal SDATA. The capacitance of each shunt capacitor22may be between 1 of and 10 μf. The capacitance of the first EMI suppression capacitor24may be between 0 and 40 pf.

In one embodiment, the data modulator18may be formed by a first P-type field effect transistor (PFET)26and a first N-type FET (NFET)28. The first PFET26and the first NFET28are coupled in series between the master power supply VIO and ground. A source of the first PFET26is coupled to the master power supply VIO, a gate of the first PFET26is configured to receive the UP input signal, and a drain of the first PFET26is coupled to a drain of the first NFET28. A gate of the first NFET28is configured to receive the DN input signal, and a source of the first NFET28is coupled to ground. The bus line16is coupled to a joint point between the drain of the first PFET26and the drain of the first NFET28, at which the first data signal D1is provided. Herein, the first PFET26and the first NFET28are moderately sized FETs. A width of the first PFET26is between 480 and 550 μm, and a length of the first PFET26is between 0.3 and 0.4 μm. A width of the first NFET28is between 150 and 250 μm, and a length of the first NFET28is between 0.5 and 0.6 μm.

In addition, the switch circuit20may be formed by a first inverter30, a second inverter32, a third inverter34, a first NAND gate36, a second NAND gate38, a third NAND gate40, and a second PFET42. Inputs of the first and second inverters30and32are configured to receive the UP_2input signal and the DN input signal, respectively. Outputs of the first and the second inverters30and32are coupled to inputs of the first NAND gate36. The second NAND gate38and the third NAND gate40form an SR latch, such that a first input of the second NAND gate38is an inverted S input of the SR latch, a first input of the third NAND gate40is an inverted R input of the SR latch, and an output of the second NAND gate38is a Q output of the SR latch. The inverted S input of the SR latch composed of the second and third NAND gates38and40is coupled to an output of the first NAND gate36and the inverted R input of the SR latch composed of the second and third NAND gates38and40is coupled to the output of the second inverter32. The Q output of the SR latch composed of the second and third NAND gates38and40is coupled to a gate of the second PFET42through the third inverter34. The master power supply VIO is coupled to a source of the second PFET42, and the bus line16is coupled to a drain of the second PFET42, at which the second data signal D2is provided. Herein, the second PFET42is a large FET. A width of the second PFET42is between 8 and 12 mm, and a length of the second PFET42is between 0.15 and 0.2 μm. A low resistance path may be formed between the master power supply VIO to the bus line16through the second PFET42with a low ON channel resistance between 0.2 ohms and 0.5 ohms.

In the switch circuit20, the second PFET42and the third inverter34may be replaced by a NFET, which is coupled between the master power supply VIO and the bus line16and configured to receive signals from the Q output of the SR latch composed of the second and third NAND gates38and40. Further, in some applications, the switch circuit20is not included in the master IC12, such that the combined data signal SDATA is based on the first data signal D1from the data modulator18.

The slave IC14may include one or more second EMI suppression capacitors44, an edge detection circuit46, a digital control circuit48, a third PFET50, a diode52, a reverse current detection circuit54, and a supply capacitor56. For simplicity and clarity, the slave IC14does not show other circuits, such as an auxiliary charging path, a write mode data receiver, and a read mode bus driver.

The second EMI suppression capacitor44is coupled in shunt with respect to the bus line16to provide high frequency filtering that removes voltage spikes from the combined data signal SDATA. The edge detection circuit46is coupled to the bus line16and configured to provide an edge detection signal EDS to the digital control circuit48. The edge detection signal EDS is based on a voltage level of the bus line16. In other words, the edge detection signal EDS is based on the state of the bus line16(details in the following paragraphs). A source and a drain of the third PFET50are coupled to the bus line16and a slave supply port P1, respectively. An anode and a cathode of the diode52are coupled to the bus line16and the slave supply port P1, respectively. Two inputs of the reverse current detection circuit54are coupled to the bus line16and the slave supply port P1, respectively. The reverse current detection circuit54is configured to detect the current through the third PFET50and provide a current detection signal CDS to the digital control circuit48.

The digital control circuit48is configured to generate a control signal CS, which is based on the edge detection signal EDS from the edge detection circuit46and the current detection signal CDS from the reverse current detection circuit54, to turn on or turn off the third PFET50. The supply capacitor56is coupled between the slave supply port P1and ground, and allowed to store power from the combined data signal SDATA on the bus line16. Herein, a slave supply voltage VDD is provided by the supply capacitor56at the slave supply port P1. The supply capacitor56may have a capacitance between 0.1 μf and 0.5 μf

In one embodiment, the edge detection circuit46may be formed by a free running oscillator (FRO)58, a fourth inverter60, a first D type flip-flop (DFF)62, a second DFF64, and a fourth NAND gate66. The FRO58is coupled to clock inputs of the first DFF62and the second DFF64. An input of the fourth inverter60is coupled to the bus line16, and an output of the fourth inverter60is coupled to reset inputs of the first DFF62and the second DFF64. In addition, a D input of the first DFF62is coupled to the bus line16, and a Q output of the first DFF62is coupled to both a D input of the second DFF64and a first input of the fourth NAND gate66. An inverted Q output of the second DFF64is coupled to a second input of the fourth NAND gate66. An output of the fourth NAND gate66provides the edge detection signal EDS to the digital control circuit48.

In addition, the digital control circuit48may be formed by a first multiplexer (MUX)68, a fifth NAND gate70, a sixth NAND gate72, a fifth inverter74, a power-on-reset (POR) circuit76, a control block78, and a NOR gate80. The first MUX68has a “1” input coupled to the output of the fourth NAND gate66, a “0” input coupled to ground, and a switch control coupled to an output of the POR circuit76. Further, the output of the POR circuit76is also coupled to the control block78, and an input of the POR circuit76is coupled to the slave supply port P1. The control block78is coupled to the slave supply port P1, and configured to provide a control block signal CBS, which is based on signals from the POR circuit76, to a first input of the NOR gate80. A second input of the NOR gate80is configured to receive the current detection signal CDS from the reverse current detection circuit54. The fifth NAND gate70and the sixth NAND gate72form an SR latch, such that a first input of the fifth NAND gate70is an inverted S input of the SR latch, a first input of the sixth NAND gate72is an inverted R input of the SR latch, and an output of the fifth NAND gate70is a Q output of the SR latch. The inverted S input of the SR latch composed of the fifth and sixth NAND gates70and72is coupled to an output of the first MUX68and the inverted R input of the SR latch composed of the fifth and sixth NAND gates70and72is coupled to an output of the NOR gate80. The Q output of the SR latch composed of the fifth and sixth NAND gates70and72is coupled to the fifth inverter74. The fifth inverter74is configured to provide the control signal CS to a gate of the third PFET50. Herein, if the fifth inverter74is not included in the digital control circuit48, the third PFET50may be replaced by an NFET, which is coupled between the bus line16and the slave supply port P1, and configured to receive signals from the Q output of the SR latch composed of the fifth and sixth NAND gates70and72.

FIGS. 2A-2Dillustrate timing diagrams of the bus interface system10shown inFIG. 1within a telegram. At any time, in which the bus line16transitions from a low state into a high state within a telegram, the master IC12will set the DN input signal low to turn off the first NFET28and will set the UP input signal low to turn on the first PFET26. The first EMI suppression capacitor24in the master IC12and the second EMI suppression capacitor44in the slave IC14will then linearly ramp up based upon the current provided by the first PFET26and the total capacitance of the first and second EMI suppression capacitors24and44. In one embodiment, the target rise time is 6 ns, the total capacitance of the first and second EMI suppression capacitors24and44is 40 pf, and the programmed current of the first PFET26is 13.5 mA.

The master IC12will then set the UP_2input signal low after a time delay, which may be approximately 10 ns. This low UP_2input signal will set the SR latch composed of the second and third NAND gates38and40, such that the Q output of the SR latch composed of the second and third NAND gates38and40is high. The third inverter34will then drive the gate of the second PFET42low to turn on the second PFET42, so that a low impedance path is formed from the master power supply VIO to the bus line16. The second PFET42has a low ON channel resistance, which may be between 0.2 and 0.5 ohms. It is important that the UP_2input signal is set low before the third PFET50in the slave IC14turns on. If the third PFET50turns on before the UP_2input signal turns low, then the rising waveform may be distorted.

When the bus line16moves from a high state to a low state, the master IC12will set the DN input signal, the UP input signal and the UP_2input signal back to high. When the DN input signal goes high, the second inverter32will go low and reset the SR latch composed of the second and third NAND gates38and40, such that the Q output of the SR latch composed of the second and third NAND gates38and40will go low. This causes the third inverter34to go high and thus turn off the second PFET42. In addition, when the UP input signal goes high, the first PFET26will be turned off. Consequently, the bus line16is released from the master power supply VIO.

At the same time, when the DN input goes high, the first NFET28is turned on to provide a controlled down current from the bus line16to ground. The voltage of on the bus line16will not fall at first, because the third PFET50of the slave IC14is still active and will hold the bus line16at the voltage level of the supply capacitor56. After a few nanoseconds (due to the response time of the reverse current detection circuit54), the reverse current detection circuit54of the slave IC14will turn off the third PFET50and disconnect the bus line16from the supply capacitor56(more details in the following paragraphs). At this point the current pulled to ground by the first NFET28and the total capacitance of the first and second EMI suppression capacitors24and44, will result in a linear ramp to ground. In one embodiment, the target fall time is 6 ns, the total capacitance of the first and second EMI suppression capacitors24and44is 40 pf, and the programmed current of the first NFET28is 13.5 mA.

At the slave IC14side, when the bus line16transitions from a low state into a high state within a telegram, the edge detection circuit46will activate the FRO58at a threshold VTHof about 50% of the voltage level of the master power supply VIO on the bus line16. The FRO58provides a clock signal with 50% duty cycle. The fourth inverter60will go low and release the reset of the first and second DFFs62and64. Consequently, on the first falling edge of the FRO58, the combination of the first DFF62, the second DFF64, and the fourth NAND gate66is configured to provide the edge detection signal EDS with a low state. The edge detection signal EDS is generated 10 to 20 ns after the voltage level of the bus line16rises to 50% of the voltage level of the master power supply VIO.

The edge detection signal EDS will pass through the first MUX68to the inverted S input of the SR latch formed by the fifth and sixth NAND gates70and72. When the edge detection signal EDS goes low, then the Q output of the SR latch formed by the fifth and sixth NAND gates70and72goes high. The fifth inverter74then drives the gate of the third PFET50low to turn on the third PFET50. Herein, the third PFET50may be a moderately large FET. A width of the third PFET50is between 1.5 and 2.5 mm, and a length of the third PFET50is between 0.15 and 0.2 μm. The third PFET50may have an ON channel resistance between 1 and 3 ohms. When the third PFET50turns on, a fairly low RC charging time constant is formed by the ON channel resistance of the third PFET50and the supply capacitor56. This allows the supply capacitor56to recover significant change from the bus line16on almost any time interval, in which the bus line16is in a high state. The supply capacitor56remains connected with the bus line16through the third PFET50with the low ON channel resistance as long as the bus line16remains in a high state.

When the bus line16transitions from a high state back to a low state, a controlled current is pulled from the bus line16to ground by the master IC12. This current will result in a voltage across the third PFET50, which is detected by the reverse current detection circuit54. The reverse current detection circuit54is then configured to provide the current detection signal CDS, which is high, to the second input of the NOR gate80. Consequently, the inverted R input of the SR latch formed by the fifth and sixth NAND gates70and72is pulled low by the NOR gate80, and the Q output of the SR latch formed by the fifth and sixth NAND gates70and72will go low. The fifth inverter74inverts the Q output of the SR latch formed by the fifth and sixth NAND gates70and72, and provides a high output to turn off the third PFET50. The turned-off third PFET50releases the supply capacitor56from the bus line16to avoid losing excessive charge from the supply capacitor56. As such, the voltage on the bus line can ramp down to zero. At this point, the slave IC14is waiting for the next low to high transition of the bus line to repeat the process.

In addition, when the master power supply VIO first applies to the bus line16, the supply capacitor56in the slave IC14will begin at zero volts. The master IC12provides a current from the master power supply VIO through the first PFET26to the bus line16. Initially, the diode52in the slave IC14provides a path to begin charging the supply capacitor56. The POR circuit76of the digital control circuit48holds a low output until the slave supply voltage VDD provided by the supply capacitor56has risen to a voltage level that is sufficient to operate the control block78. With the low output of the POR circuit76, the first MUX68selects the “0” input that is tied to ground and passes this to the inverted S input of the SR latch formed by the fifth and sixth NAND gates70and72. This causes the Q output of the S-R latch formed by the fifth and sixth NAND gates70and72to go high and the output of the fifth inverter74to go low. Consequently, the third PFET50is turned on and configured to provide a low resistance path from the bus line16to the supply capacitor56.

FIG. 3illustrates an alternative bus interface system10A according to one embodiment of the present disclosure. Compared to the bus interface system10, the bus interface system10A has a same master IC12, but an alternative slave IC14A. Herein, the slave IC14A further includes a digital counter82coupled between the output of the FRO58and the control block78. The digital counter82determines when to turn off the third PFET50and disconnect the bus line16from the supply capacitor56within a telegram.

FIGS. 4A-4Dillustrate timing diagrams of the bus interface system10A shown inFIG. 4within a telegram. The digital counter82counts the pulse number of the FRO58. Once the digital counter82reaches its predetermined count, the digital counter82is configured to force the control block78to generate a high-state output to the NOR gate80to turn off the third PFET50. The time, at which the third PFET50is turned off, will occur before the bus line16transitions from a high state to a low state. In other words, the third PFET50will be turned off before the reverse current detection circuit54senses the reversed current. Notice that, if the third PFET50turns on outside of a telegram, then the third PFET50remains on and only turns off when the reverse current detection circuit54senses the reversed current through the third PFET50.

In the bus interface system10A, the turn-off delay encountered due to the response time of the reverse current detection circuit54is avoided during a telegram. This turn-off delay may adversely affect the desired pulse width modulation of the combined data signal SDATA. Outside of a telegram (ex. in idle times, there is no data signal transmitted along the bus line16), the third PFET50must be ON to maintain power to the slave IC14A. A start of a new telegram will be detected by the reverse current detection circuit54, when the first falling edge of the voltage level on the bus line16(current pulled from the bus line16to ground through the first NFET28) after a previous telegram has completed. Thus, the first falling edge at the start of a telegram will have an added turn-off delay due to the response time of the reverse current detection circuit54, and all other falling edges of the voltage level on the bus line16during the telegram will not experience added turn-off delay. The turn-off delay has a negligible effect outside of the telegram as there is no PWM signal present.

In the bus interface system10, the slave IC14must always provide power to the reverse current detection circuit54, because in the idle times when the bus line16is high, the slave IC14must be ready to respond to the master IC12pulling current from the bus line16to ground to drive the bus line16low. Thus, a standby current, (ex. about 12 uA) will exist in the reverse current detection circuit54, when the bus interface system10is in the idle times. However, for some applications, this level of the standby current is not acceptable.FIG. 5illustrates an exemplary bus interface system10B, in which the standby current is reduced or eliminated. Compared to the bus interface system10, the bus interface system10B has a same master IC12, but an alternative slave IC14B. The slave IC14B further includes an auxiliary standby circuit84, which includes a Schmitt trigger86, a second MUX88, a seventh NAND gate90, an eighth NAND gate92, a sixth inverter94, a first resistor96, and a fourth PFET98. During the idle times, the auxiliary standby circuit84is configured to conduct a path from the supply capacitor56to the bus line16, such that there is substantially no current in the reverse current detection circuit54.

In detail, a first input of the Schmitt trigger86is coupled to the bus line16, and an output of the Schmitt trigger86is coupled to the control block78. The second MUX88has a “1” input coupled to the control block78, a “0” input coupled to ground, and a switch control coupled to the output of the POR circuit76. The seventh NAND gate90and the eighth NAND gate92form an SR latch, such that a first input of the seventh NAND gate90is an inverted S input of the SR latch, a first input of the eighth NAND gate92is an inverted R input of the SR latch, and an output of the seventh NAND gate90is a Q output of the SR latch. The inverted S input of the SR latch composed of the seventh and eighth NAND gates90and92is coupled to an output of the second MUX88and the inverted R input of the SR latch composed of the seventh and eighth NAND gates90and92is coupled to the output of the Schmitt trigger86. In addition, the Q output of the SR latch composed of the seventh and eighth NAND gates90and92is couple to a gate of the fourth PFET98through the sixth inventor94. A drain of the fourth PFET98is coupled to the bus line16, and a source of the fourth PFET98is coupled to the supply capacitor56though the first resistor96.

After the slave IC14enters the idle times, the control block78will pull its output to the NOR gate80high. This will reset the SR latch formed by the fifth and sixth NAND gates70and72and turn off the third PFET50through the fifth inverter74. As such the path from the bus line to the supply capacitor56through the third PFET50is open. Meanwhile, the control block78will also disable the reverse current detection circuit54(Herein, the control block78is also coupled to the reverse current detection circuit54) to eliminate the standby current. In addition, the control block78will pull the “1” input of the second MUX88low, which will set the SR latch formed by the seventh and eighth NAND gates90and92. Consequently, the Q output of the SR latch formed by the seventh and eighth NAND gates90and92will go high and the output of the sixth inverter94will go low. The fourth PFET98will be turned on and conduct a path between the supply capacitor56and the bus line16within the idle times.

When the next telegram comes, the voltage level on the bus line16transitions from high to low (current pulled from the bus line16to ground through the first NFET28). Once the voltage level on the bus line16drops to less than 0.8 to 0.9 times the slave supply voltage VDD provided by the supply capacitor56, the output of the Schmitt trigger86will go low. Consequently, the Q output of the SR latch formed by the seventh and eighth NAND gates90and92will go low and the output of the sixth inverter94will go high. The fourth PFET98is turned off, so that there is no path for current pulled from the supply capacitor56to ground through the first NFET28. The control block78will also respond to the output of the Schmitt trigger86going low by re-activating the reverse current detection circuit54and pulling the output to the NOR gate80low. Then, the bus interface system10B operates the same as the bus interface system10for the coming telegram.

FIG. 6illustrates an alternative bus interface system10C according to one embodiment of the present disclosure. Compared to the bus interface system10, the bus interface system10C has a same slave IC14, but an alternative master IC12C. The alternative master IC12C includes the shunt capacitors22, the EMI suppression capacitors24, an alternative data modulator18C, and an initialization circuit100. Herein, the data modulator18C may be functioning as a constant slew rate driver. The constant slew rate refers to a substantially constant dV/dt (slew rate) at the joint point of the fifth PFET102and the second NFET104(the bus line16). The data modulator18C is coupled between the master power supply VIO and ground, configured to receive the UP input signal, the DN input signal, an EN enable signal, and an INIT initial signal, and configured to provide the first data signal D1to the bus line16. The initialization circuit100is coupled to the bus line16and active when the bus interface system10C is initially started. The initialization circuit100is configured to receive the INIT initial signal and configured to provide an initial data signal D3to the bus line16. The combined data signal SDATA transmitted along the bus line16is based on the initial data signal D3when the bus interface system10C is initially started; while the combined data signal SDATA is based on the first data signal D1from the alternative data modulator18C when the bus interface system10C is in normal operation.

In one embodiment, the data modulator18C may be formed by a fifth PFET102, a second NFET104, a sixth PFET106, a third NFET108, a feedback capacitor110, a seventh inverter112, an AND gate114, an OR gate116, a second resistor118, and a third resistor120. The fifth PFET102and the second NFET104are coupled in series between the master power supply VIO and ground. A source of the fifth PFET102is coupled to the master power supply VIO, a drain of the fifth PFET102is coupled to a drain of the second NFET104, and a source of the second NFET104is coupled to ground. The bus line16is coupled to a joint point between the drain of the fifth PFET102and the drain of the second NFET104, at which the first data signal D1is provided. Herein, the fifth PFET102and the second NFET104are moderately large FETs. A width of the fifth PFET102is between 8 and 12 mm, and a length of the fifth PFET102is between 0.15 and 0.2 μm. A width of the second NFET104is between 1.5 and 2.5 mm, and a length of the second NFET104is between 0.3 and 0.4 μm.

In addition, the sixth PFET106and the third NFET108are coupled between a gate of the fifth PFET102and a gate of the second NFET104. A source of the sixth PFET106is coupled to the gate of the fifth PFET102, a drain of the sixth PFET106is coupled to a drain of the third NFET108, and a source of the third NFET108is coupled to the gate of the second NFET104. The feedback capacitor110is coupled between the joint point of the fifth PFET102and the second NFET104and a joint point of the sixth PFET106and the third NFET108. A gate of the sixth PFET106is configured to receive the UP input signal, and a gate of the third NFET108is configured to receive the DN input signal. Herein, the sixth PFET106and the third NFET108are small FETs. A width of the sixth PFET106is between 30 and 50 μm, and a length of the sixth PFET106is between 0.15 and 0.2 μm. A width of the third NFET108is between 15 and 25 μm, and a length of the third NFET108is between 0.2 and 0.25 μm.

Further, the DN input signal and the EN enable signal are received at inputs of the AND gate114, and an output of the AND gate114is coupled to the gate of the second NFET104. The AND gate114is also coupled to the master power supply VIO through a second resistor118to form a current path. The UP input signal, an inverted EN enable signal, and the INIT initial signal are received at inputs of the OR gate116, and an output of the OR gate116is coupled to the gate of the fifth PFET102. The OR gate116is also coupled to ground through a third resistor120to form another current path.

The initialization circuit100may be formed by a seventh PFET122and an eighth inverter124. The master power supply VIO is coupled to a source of the seventh PFET122, and the bus line16is coupled to a drain of seventh PFET122, at which the third data signal D3is provided. The INIT initial signal is coupled to a gate of the seventh PFET122through the eighth inverter124. Herein, the seventh PFET122is a moderate FET. A width of the seventh PFET122is between 480 and 550 μm, and a length of the seventh PFET122is between 0.3 and 0.4 μm. In the initialization circuit100, the seventh PFET122and the eighth inverter124may be replaced by a NFET, which is configured to receive the INIT initial signal.

When the bus interface system10C is initially started, the INIT initial signal is set high to activate the initialization circuit100. As such, the initialization circuit100is configured to charge up the supply capacitor56initially. The INIT initial signal will be high for about 200 μs and then set low for the remaining operations. After the initial period, when the bus line16transitions from a low state into a high state within a telegram, the master IC12C will set the DN input signal low to turn off the third NFET108and the second NFET104, and will set the UP input signal low to turn on the sixth PFET106. Herein, when the bus interface system10C starts to operate, the EN enable signal is always high until the bus interface system10C is off. As such, setting the UP input signal low will also turn on the fifth PFET102. When the bus line16moves from a high state to a low state, the master IC12C will set the DN input signal and the UP input signal back to high. When the DN input signal goes high, the third NFET108and the second NFET104are turned on. When the UP input signal goes high, the sixth PFET106and the fifth PFET102are turned off.

The feedback capacitor110is configured to limit current swings at the joint point of the fifth PFET102and the second NFET104. The sixth PFET106and the third NFET108serve as a switching element to selectively couple the feedback capacitor110either to the gate of the fifth PFET102or the gate of the second NFET104. Since the gate of the fifth PFET102or the second NFET104will have an essentially constant voltage during the transition time in order to obtain the constant dV/dt (slew rate) at the joint point of the fifth PFET102and the second NFET104, the second resistor118/the third resistor120may function as a current source. A voltage across the second resistor118/third resistor120and thus the current through the second resistor118/third resistor120are essentially constant. When the second NFET104and the third NFET108are off, a current path (with current1) will be formed from the feedback capacitor110through the sixth PFET106and the third resistor120to ground. When the fifth PFET102and the sixth PFET106are off, a current path (with current2) will be formed from the master power supply VIO through the second resistor118and the third NFET108back to the feedback capacitor110. The current1/the current2then flows through the feedback capacitor110and forces the dV/dt at the joint point of the fifth PFET102and the second NFET104to be constant.

The second and third resistors118and120will not provide standby current to the data modulator18C. Instead, the second and third resistors118and120will only draw current when the UP input signal and/or DN input signal is transitioning and has zero turn on time.