Level-shifter circuit properly operable with low voltage input

A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor integrated circuits functioning as level-shifter circuits, and particularly relates to a semiconductor integrated circuit functioning as a level-shifter circuit that operates stably at high speed even with a low voltage input.

2. Description of the Related Art

Level-shifter circuits are used for the purpose of converting a signal having a predetermined voltage to a signal having a higher voltage level. A typical level-shifter circuit is disclosed in Japanese Patent Laid-open Application No. 6-37624, for example.

FIG. 1is a circuit diagram showing a typical construction of a level-shifter circuit.

The level-shifter circuit ofFIG. 1includes PMOS transistors11and12, NMOS transistors13and14, and an inverter15. An incoming signal IN is applied to the gate of the NMOS transistor14, and is also inverted by the inverter15to be applied to the gate of the NMOS transistor13. The incoming signal IN being HIGH (VL) makes the NMOS transistors13and14nonconductive and conductive, respectively, resulting in the PMOS transistors11and12being conductive and nonconductive, respectively. Accordingly, an output signal OUT is set to 0 V. If the incoming signal IN is LOW (0 V), the NMOS transistors13and14are conductive and nonconductive, respectively, resulting in the PMOS transistors11and12being nonconductive and conductive, respectively. In this case, therefore, the output signal OUT is set at VH. In this manner, the incoming potential level ranging between 0 and VLis shifted to a range between 0 and VH.

The transistors11through14that control the output signal OUT are designed for high-potential operations so as to properly operate at a potential range between 0 and VH. In general, high-speed signal transition requires the operating range of an incoming signal IN to be set at an increasingly lower potential level as the technology improves. In such a case, since the transistors13and14are designed for high-potential operations corresponding to the potential range boosted by the level shift, the potential level VLthat is relatively low may not be able to turn on or off the transistors at sufficient speed. In some cases, the transistors may fail to be sufficiently conductive.

Accordingly, there is a need for a level-shifter circuit that can stably operate at high speed even when the incoming signal is set at a potential level significantly lower that the operating potential range of the circuit-component transistors.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a level-shifter circuit that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.

Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a level-shifter circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor integrated circuit, including first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.

In the semiconductor integrated circuit functioning as a level-shifter circuit as described above, the substrate-bias potential of the first field-effect transistor is controlled by the incoming signal. The substrate-bias potential is set at an elevated level to lower the threshold when the first field-effect transistor is turned on. The lowering of the threshold makes it possible to achieve a high-speed switching-on operation of the first field-effect transistor even when the signal level of the incoming signal is relatively low. This insures that the transition of the output signal is stable and high speed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2is a circuit diagram showing a first embodiment of a level-shifter circuit according to the present invention.

A level-shifter circuit20ofFIG. 2includes PMOS transistors21and22, NMOS transistors23and24, an inverter25, and an NMOS transistor26. An incoming signal IN is applied to the gate of the NMOS transistor24, and is also inverted by the inverter25to be applied to the gate of the NMOS transistor23. The incoming signal IN being HIGH (VL) makes the NMOS transistors23and24nonconductive and conductive, respectively, resulting in the PMOS transistors21and22being conductive and nonconductive, respectively. Accordingly, an output signal OUT is set to 0 V. If the incoming signal IN is LOW (0 V), the NMOS transistors23and24are conductive and nonconductive, respectively, resulting in the PMOS transistors21and22being nonconductive and conductive, respectively. In this case, therefore, the output signal OUT is set at VH. In this manner, the incoming potential level ranging between 0 and VLis shifted to a range between 0 and VH.

In the circuit construction ofFIG. 2, the NMOS transistor26is provided in the level-shifter circuit20. The NMOS transistor26has a first node thereof (i.e., a drain node or a source node) coupled to the well of the NMOS transistor24, and has a second node (i.e., a source node or a drain node) and gate node thereof coupled to the incoming signal IN.

In the level-shifter circuit20, a potential at the gate of the NMOS transistor26rises from LOW to HIGH at the start of a conductive state of the NMOS transistor24, i.e., at the negative transition of the output signal OUT responding to the transition from LOW to HIGH of the incoming signal IN. As the gate level exceeds the threshold of the NMOS transistor26, the NMOS transistor26is turned on, resulting in an electric current running between the drain and the source. A potential at the first node coupled to the well of the NMOS transistor24is thus brought closer to the potential of the incoming signal applied to the second node. Since the second node of the NMOS transistor26is coupled to the gate thereof, the NMOS transistor26becomes nonconductive in response to the approaching of the first-node potential to the second-node potential within a predetermined range. In this manner, the first node of the NMOS transistor26is maintained at a predetermined potential.

The first node of the NMOS transistor26is coupled to the well of the NMOS transistor24. It follows that a substrate-bias potential Vbs of the NMOS transistor24(i.e., the potential of the well) is set at a predetermined potential lifted off the ground potential.

When the conductive state of the NMOS transistor24comes to an end, i.e., when the output signal is about to rise in response to the transition from HIGH to LOW of the incoming signal IN, the NMOS transistor26coupled to the well of the NMOS transistor24is turned off while maintaining the potential at its first node. Since the well of the NMOS transistor24is connected to the first node of the NMOS transistor26, the substrate-bias potential Vbs is sustained at the predetermined potential.

In this manner, the bias potential of the NMOS transistor24is in a floating state and always maintained at the predetermined potential. This means that the threshold is always kept at a reduced level.

FIG. 3is an example of the substrate-bias potential Vbs. At the negative transition of the output signal OUT, the substrate-bias potential Vbs does not rise to the level of the incoming-signal high potential VLbecause the second node is set to the same potential as the gate node. InFIG. 3, the waveform of the substrate-bias potential Vbs is illustrated for the positive transition of the output signal OUT and for the negative transition of the output signal OUT. As shown inFIG. 3, the substrate-bias potential Vbs is always maintained at a predetermined potential. Since the substrate-bias potential Vbs is always in existence as a positive potential, the threshold of the NMOS transistor24is in a lowered state all the time. As a result, the output signal OUT is output at higher speed than in the conventional circuit construction. InFIG. 3, waveforms illustrated by solid lines are those of the first embodiment of the present invention shown inFIG. 2, and waveforms illustrated by dotted lines are those of the related-art construction shown in FIG.1.

FIG. 4is a chart showing an output signal waveform of the level-shifter circuit20according to the first embodiment. As shown inFIG. 4, the output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition than a related-art output signal waveform shown by dotted lines. Here, the waveform of the substrate-bias potential Vbs shown in FIG.3and the output signal waveform ofFIG. 4are simulated waveforms obtained by a circuit simulator. Waveforms that will be shown hereafter are also obtained by use of the circuit simulator.

FIG. 5is a circuit diagram showing a second embodiment of the level-shifter circuit of the present invention. InFIG. 5, the same elements as those ofFIG. 2are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.

A level-shifter circuit20A ofFIG. 5includes a NMOS transistor27newly provided in addition to the construction of the first embodiment shown in FIG.2. The NMOS transistor27has a first node thereof coupled to the well of the NMOS transistor23, and has a second node thereof and a gate node thereof commonly coupled to an inverse of the incoming signal IN that is output from the inverter25.

In the first embodiment shown inFIG. 2, the threshold of the NMOS transistor24that pulls down the output signal OUT is lowered, thereby making faster the negative transition of the output signal OUT. In addition, the second embodiment shown inFIG. 5is further provided with a function to lower the threshold of the NMOS transistor23, which drives the PMOS transistor22that pulls up the output signal OUT. This makes it possible to achieve faster signal transition not only for the negative transition of the output signal OUT but also for the positive transition of the output signal OUT.

FIG. 6is a chart showing an output signal waveform of the level-shifter circuit20A of the second embodiment. As shown inFIG. 6, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.

FIG. 7is a circuit diagram showing a third embodiment of the level-shifter circuit of the present invention. InFIG. 7, the same elements as those ofFIG. 2are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.

A level-shifter circuit20B ofFIG. 7includes a NMOS transistor26B that replaces the NMOS transistor26of the first embodiment shown in FIG.2. The second node of the NMOS transistor26B has a different coupling than that of the NMOS transistor26. In the third embodiment, the second node of the NMOS transistor26B is coupled to the output of the inverter25.

The output of the inverter25changes from HIGH to LOW with a predetermined time delay after the transition from LOW to HIGH of the incoming signal IN. When the gate node of the NMOS transistor26B is raised to HIGH by the incoming signal IN, therefore, the second node of the NMOS transistor26B still remains at the HIGH level. Because of this, lowering of the threshold occurs only for the duration of the delay time of the inverter25, thereby achieving high-speed switching. The output of the inverter25subsequently becomes LOW, so that the well of the NMOS transistor24coupled to the first node of the NMOS transistor26B is pulled down to the LOW level. In this manner, the threshold is set in the zero-biased state while the NMOS transistor24is conductive. This prevents the flowing of an excessive through current.

FIG. 8is a chart showing an output signal waveform of the level-shifter circuit20B of the third embodiment. As shown inFIG. 8, an output signal waveform of the present invention illustrated by solid lines exhibits a faster change at the negative signal transition than a related-art output signal waveform shown by dotted lines. As described above, the threshold is set in the zero-bias state during the LOW period of the output signal. This makes it possible to switch off the NMOS transistor24at high speed at the positive signal transition, thereby further enhancing the speed of positive signal transition compared with the first embodiment.

FIG. 9is a circuit diagram showing a fourth embodiment of the level-shifter circuit of the present invention. InFIG. 9, the same elements as those ofFIG. 7are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.

A level-shifter circuit20C ofFIG. 9includes a NMOS transistor27C newly provided in addition to the construction of the third embodiment shown in FIG.7. The NMOS transistor27C has a first node thereof coupled to the well of the NMOS transistor23, and has a second node thereof and a gate node thereof commonly coupled to an inverse of the incoming signal IN that is output from the inverter25.

In the third embodiment shown inFIG. 7, the threshold of the NMOS transistor24that pulls down the output signal OUT is lowered, thereby making faster the negative transition of the output signal OUT. In addition, the fourth embodiment shown inFIG. 9is further provided with a function to lower the threshold of the NMOS transistor23, which drives the PMOS transistor22that pulls up the output signal OUT. This makes it possible to achieve faster signal transition not only for the negative transition of the output signal OUT but also for the positive transition of the output signal OUT.

FIG. 10is a chart showing an output signal waveform of the level-shifter circuit20C of the fourth embodiment. As shown inFIG. 10, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.

FIG. 11is a circuit diagram showing a fifth embodiment of the level-shifter circuit of the present invention. InFIG. 11, the same elements as those ofFIG. 2are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.

A level-shifter circuit20D ofFIG. 11includes a NMOS transistor26D that replaces the NMOS transistor26of the first embodiment shown in FIG.2. The second node of the NMOS transistor26D has a different coupling than that of the NMOS transistor26. In the fifth embodiment, the second node (i.e., source node) of the NMOS transistor26D is coupled to the ground potential Vss.

When the output signal OUT is about to rise in response to the change from HIGH to LOW of the incoming signal, i.e., when the NMOS transistor24is about to become nonconductive, the NMOS transistor26D coupled to the well commences its switching-off operation. As a result, positive charge (i.e., positive holes) is accumulated in the well of the NMOS transistor24, which leads to an increase in the well potential (i.e., the substrate-bias potential Vbs). When the NMOS transistor26D is fully nonconductive, the substrate-bias potential Vbs of the NMOS transistor24is thus at a raised level. The threshold is thus at a lowered level.

Thereafter, the incoming signal changes from LOW to HIGH, resulting in the output signal OUT being pulled down. In this case, the output signal exhibits a faster change than in the related-art construction because the threshold of the NMOS transistor24has been held at the lowered level up to this point. When the NMOS transistor26D subsequently becomes conductive, the drain potential drops to the source potential coupled to the ground potential. This brings the threshold of the NMOS transistor24down to the zero-bias level, thereby preventing the occurrence of an excessive through current.

FIG. 12is a chart showing an example of a substrate-bias potential Vbs according to the fifth embodiment. At the positive transition of the output signal OUT, the substrate-bias potential Vbs is initially set to zero since the NMOS transistor26D has been conductive up to this point. In this case, therefore, the threshold is relatively high, so that the NMOS transistor24will be switched off at high speed in response to the change from HIGH to LOW of the incoming signal IN. At the negative transition of the output signal OUT, the substrate-bias potential Vbs has been held at an elevated level because of the nonconductive state of the NMOS transistor26D. In this case, thus, the threshold is relatively low, so that the NMOS transistor24will be switched on at high speed in response to the change from LOW to HIGH of the incoming signal.

FIG. 13is a chart showing an output signal waveform of the level-shifter circuit20D of the fifth embodiment. As shown inFIG. 13, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.

FIG. 14is a circuit diagram showing a sixth embodiment of the level-shifter circuit of the present invention. InFIG. 14, the same elements as those ofFIG. 11are referred to by the same numerals, and a description thereof will be omitted unless it is necessary.

A level-shifter circuit20E ofFIG. 14includes a NMOS transistor27E newly provided in addition to the construction of the fifth embodiment shown in FIG.11. The NMOS transistor27E has a drain node thereof coupled to the well of the NMOS transistor23, and has a source node thereof coupled to the ground potential, with a gate node thereof coupled to an inverse of the incoming signal IN that is output from the inverter25.

In the fifth embodiment shown inFIG. 11, the threshold of the NMOS transistor24that pulls down the output signal OUT is lowered, thereby making faster the negative transition of the output signal OUT. In addition, the sixth embodiment shown inFIG. 14is further provided with a function to lower the threshold of the NMOS transistor23, which drives the PMOS transistor22that pulls up the output signal OUT. This makes it possible to achieve faster signal transition not only for the negative transition of the output signal OUT but also for the positive transition of the output signal OUT.

FIG. 15is a chart showing an output signal waveform of the level-shifter circuit20E of the sixth embodiment. As shown inFIG. 15, an output signal waveform of the present invention illustrated by solid lines exhibits faster signal transition, with respect to both positive signal transition and negative signal transition, than a related-art output signal waveform shown by dotted lines.

FIG. 16is a circuit diagram showing a seventh embodiment of the level-shifter circuit of the present invention. InFIG. 16, the same elements as those ofFIG. 2are referred to by the same numerals.

In a level-shifter circuit20F ofFIG. 16, the well of the NMOS transistor24is directly coupled to the incoming signal IN. Such a direct coupling of the substrate to the incoming signal potential may destroy the NMOS transistor24, and, thus, careful circuit design is required. If the potential VLof the incoming signal IN is sufficiently lowered through scaling, direct coupling may be used to boost the substrate bias by coupling the well of the NMOS transistor24to the incoming signal IN as shown in FIG.16. This achieves high-speed signal transition of the output signal by lowering the threshold of the NMOS transistor24at the time of switching-on.

FIG. 17is a chart showing an output signal waveform of the level-shifter circuit20E of the seventh embodiment. As shown inFIG. 17, an output signal waveform of the present invention illustrated by solid lines exhibits a faster change in the negative signal transition than a related-art output signal waveform shown by dotted lines.