SEMICONDUCTOR PACKAGE IN A SOURCE-DOWN CONFIGURATION BY USE OF VERTICAL CONNECTORS

A semiconductor package includes: a leadframe having a die carrier and at least one first lead connected with the die carrier; a semiconductor transistor die connected with the die carrier and having a first surface and a second surface opposite to the first surface, a source pad disposed on the first surface, and a drain pad disposed on the second surface, the first surface facing a bottom side of the semiconductor package and the second surface facing a top side of the package; and a clip. The source pad is connected with the clip by at least one electrical connector.

TECHNICAL FIELD

The present disclosure is related to a semiconductor package, in particular to a semiconductor transistor package in a source-down configuration.

BACKGROUND

Discrete power semiconductor packages are usually designed with a collector/drain down concept. That means the backside of the semiconductor transistor die (collector/drain contact) is attached to the leadframe and the frontside interconnect (emitter/source/sense/gate) is connected to the lead contacts, e.g., SMD (surface mount device) lead or THT (through-hole technology) pin. In this configuration certain electrical and thermal disadvantages have to be faced.

In particular, a drain down package concept requires full isolation between the die pad and the application heatsink which can be a cost adder at system level. This isolation has in many application issues in terms of EMV or even capacitive power losses (lower efficiency, higher heat dissipation). Furthermore a drain down package concept has limitations in terms of Rds(On)and parasitics (lower electrical performance on system level). These disadvantages could be overcome for discrete power devices using a source down package concept leading to big advantages within the application. Source Down for (SMD) surface mount devices is currently very successful in the low voltage class up to 100V, and the demand is increasing in the field of high voltage devices e.g. 650V & 1200V or even above. In the field of WBG (wide band gap) devices e.g. SiCMOS and GaN, the efficiency of the components are no longer sufficient to meet the upcoming requirements on system level. Improvements on WBG devices on system level can easier be paid off with a cost adder on package level.

SUMMARY

An aspect of the present disclosure is related to a semiconductor package comprising a leadframe comprising a die carrier and at least one first lead connected with the die carrier, a semiconductor transistor die connected with the die carrier and comprising a first surface and a second surface opposite to the first surface, a source pad disposed on the first surface and a drain pad disposed on the second surface, wherein the first surface faces a bottom side of the semiconductor package and the second surface faces a top side of the package, and a clip wherein the source pad is connected with the clip by at least one electrical connector.

DETAILED DESCRIPTION

As employed in this specification, the terms “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” are not meant to mean that the elements or layers must directly be contacted together; intervening elements or layers may be provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively. However, in accordance with the disclosure, the above-mentioned terms may, optionally, also have the specific meaning that the elements or layers are directly contacted together, i.e., that no intervening elements or layers are provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively.

Further, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) “indirectly on” the implied surface with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer. However, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may, optionally, also have the specific meaning that the part, element or material layer be located (e.g., placed, formed, deposited, etc.) “directly on”, e.g., in direct contact with, the implied surface.

FIGS.1,2and3show an example of a semiconductor package with a single gauge leadframe and vertical wires between the source pad12.1and the clip.

More specifically, the semiconductor package10ofFIGS.1,2and3comprise a leadframe11comprising a die carrier11.1and a plurality of first leads11.2connected with the die carrier11.1. The semiconductor package10further comprises a semiconductor transistor die12which is connected with the die carrier11.1. The semiconductor die12can, for example, be one or more of a vertical transistor die, a MOSFET die, and an IGBT die. Furthermore the semiconductor die12can be fabricated from Si, or from a wide bandgap semiconductor material like SiC or GaN.

The semiconductor transistor die12can in particular comprise a power semiconductor transistor die. Here, the term “power semiconductor transistor die” may refer to a semiconductor die providing at least one of high voltage blocking or high current-carrying capabilities. A power semiconductor die may be configured for high currents having a maximum current value of a few Amperes, such as e.g. 10 A, or a maximum current value of up to or exceeding 100 A. Similarly, voltages associated with such current values may have values of a few Volts to a few tens or hundreds or even thousands of Volts.

The semiconductor transistor die12comprises a first surface and a second surface opposite to the first surface, a source pad12.1disposed on the first surface and a drain pad disposed on the second surface, wherein the semiconductor transistor die12is connected with the drain pad to the die carrier11.1. The source pad12.1faces a bottom side of the package and the drain pad faces a top side of the package so that the package is configured in a source-down mode. The down side of the package can be the mounting side of the package, the device being thus an SMD (surface mount device.

The semiconductor package10further comprises a clip13wherein the source pad12.1is connected with the clip by electrical connectors14, in particular vertical electrical connectors14. In the example as shown inFIGS.1,2and3the electrical connectors14are given by electrical wires14, in particular vertical electrical wires14. Exemplary details of the electrical wires14and other examples of electrical connectors14are shown and explained in connection withFIGS.7A to7D.

As can be seen inFIGS.2and3, the electrical wires14can be arranged in the form of a matrix like arrangement along equally spaced rows and columns. The number, the spatial dimensions of the electrical wires14and their distances from each other can be specifically chosen to create a desired thermal resistance between the source pad12.1and the clip13. It may be desired, for example, to provide a good or satisfactory electrical transition between the source pad12.1and the clip13on the one hand, but on the other hand to provide a thermal resistance between the source pad12.1and the clip13that is higher than the thermal resistance between the drain pad and the die carrier, e.g. 2 times, or 5 times, or 10 times higher than the thermal resistance between the drain pad and the die carrier. This can be used to protect a printed circuit board, to which the package is connected with its clip, from too high temperatures. For example, whereas an expected chip temperature can be in a range from 175° C. to 200° C., adjusting the thermal resistance between the source pad and the clip can be done so that the temperature of the PCB will be limited to a range of Tmax in a range of 100° ° C. to 150° C.

The semiconductor package further comprises an encapsulant15covering the die carrier11, the semiconductor die12, and at least partially covering the clip13.

The encapsulant15may be comprised of a conventional mold compound like, for example, a resin material, in particular an epoxy resin material. Moreover, the encapsulant15can be applied in different aggregate states as, for example, in liquid form, as pellets, or as a granulate. Moreover, the encapsulant15can be made of a thermally conductive material to allow efficient heat dissipation to external application heat sinks. The material of the encapsulant15can, in particular, comprise a resin like an epoxy resin material filled with particles like, for example, SiO or other ceramic particles, or thermally conductive particles like, for examples, Al2O3, BN, AlN, Si3N4, diamond, or any other thermally conductive particles. The encapsulant15can also be made of a plateable mold compound.

The semiconductor transistor die12may further comprise a gate pad12.2and a source-sense pad12.3, both being disposed on the first main face. The gate pad12.2can be connected to a second lead11.3and the source/sense pad12.3can be connected to a third lead11.4. The second and third leads11.3and11.4may comprise inner portions which are located in the same plane as the chip carrier11.1and outer portions which are located in the plane of the clip13. The second and third leads11.3and11.4may be components of the lead frame11, as are the first leads11.2and the chip carrier11.1.

As shown inFIG.3, the die carrier11.1has a basically rectangular shape, but has a rectangular recess at one of its4corners, in which the inner portions of the second and third leads11.3and11.4are arranged. The gate pad12.2and the source sense pad12.3can be connected to the inner portions of the second and third leads11.3and11.4by bonding wires.

As shown inFIG.2, the clip13also has a basically rectangular shape, but it also has a rectangular recess at one of its four corners, in which the outer portions of the second and third leads11.3and11.4are arranged. The clip13has an outer section13A which is not embedded by the encapsulant15and extends to the outside from the encapsulant15like the outer portions of the second and third leads11.3and11.4.

The second and third leads11.3and11.4also have bent portions that connect the inner and outer portions of the second and third leads11.3and11.4with each other and are located within the encapsulant15.

The plurality of first leads11.2comprise outer end portions and portions that lie in a plane above the plane of the die carrier11.1. These portions are interconnected by bent portions. The first leads11.2may be located entirely outside the encapsulant. The first leads11.2may be connected to a lateral bar which can be arranged inside the encapsulant15.

The plurality of first leads11.2are located on a first side of the encapsulant15and the external portion13A of the clip13and the second and third leads11.3and11.4are located on a second side of the encapsulant15opposite to the first side.

As already mentioned above, the leadframe of the example ofFIGS.1to3is a single gauge leadframe. “Gauge” is to do with the thickness of the die carrier provided for the package. Single gauge means a thickness of 0.5 mm of the die carrier and dual gauge means a thickness of 1.2 mm of the die carrier wherein these thickness values are mot to be understood in any way restrictive. In the following an example of a semiconductor package having a dual gauge leadframe will be shown.

FIGS.4,5and6show alternative examples of semiconductor packages with a dual gauge leadframe in a side view (FIG.4), the semiconductor package ofFIG.4in a perspective view (FIG.5), and a semiconductor package with a single gauge leadframe and wire loops as vertical connectors.

The semiconductor package20ofFIG.4is similar to the semiconductor package10so that the same reference signs were used for the same parts. The only difference to the semiconductor package10is that it comprises a dual gauge leadframe21which means that the leadframe21comprises a die carrier21.1which comprises a thickness which is more than twice the thickness of the carrier11.1of the leadframe11. This increased thickness allows for improved dissipation of excess heat from the package due to improved internal heat spreading.

The semiconductor package30ofFIG.6is similar to the semiconductor package10ofFIG.1so that the same reference signs were used for the same parts. The only difference to the semiconductor package10is the plurality of electrical connectors34which in this case are comprised of a plurality of wire loops, in particular vertical wire loops34.

The electrical wire loops34can be arranged in the form of a matrix like arrangement along equally spaced rows and columns. The number, the spatial dimensions of the electrical wire loops34and their distances from each other can be specifically chosen to create a desired thermal resistance between the source pad12.1and the clip13as was already explained above in connection with the electrical wires14of the semiconductor package10.

The semiconductor packages10,20, or30can be applied to standard discrete power packages, e.g., TO263, TO252, or TOLL, as well as through-hole devices (THD), e.g., TO252 or TO247.

The semiconductor packages of the present disclosure can be applied for one or both of top-side cooling and down side cooling. In particular, for top side cooling it is possible to expose the die carrier to the outside on top of the package, in particular for the semiconductor package20ofFIG.4. In this case the encapsulant15would not cover the die carrier on the top side. Another application is double-side cooling (DSC), in which both drain and source contacts would be exposed.

In order to provide system-in-package (SiP) solutions, it is also possible to combine any one of the source-down semiconductor die configurations of the present disclosure with a source-up semiconductor die configuration in one package. Alternatively or in combination, it is also possible to integrate a driver device, for example by placing the driver device onto one of the leads of the leadframe.

FIGS.7A to7Cshow three different types of electrical connectors to be connected between the source pad12.1and the clip, namely vertical wires (FIG.7A), vertical wire loops (FIG.7B), and stacked stud bumps (FIG.7C).

According toFIG.7A, the electrical connectors are provided by vertical electrical wires14. The electrical wires14can be fabricated, e.g., by nail head bonding in which case nail head14.1is at first deposited onto the upper main surface of the source pad12.1of the semiconductor transistor die12. Subsequently a vertical wire14.2will be bonded on top of the nail head14.1. After fabricating the plurality of vertical wires14, a clip13will be applied on top of the plurality of vertical wires14. Alternatively, the vertical wires14could be connected to the source pad21.1using other methods such as solder or a conductive glue.

As was explained above, the vertical wires14can be fabricated to adjust a desired value of the thermal resistance between the source pad12.1and the clip13. The available parameters therefore are the wire size (diameter), the wire length, the nail head width (at the bottom), and the wire pitch (distance between wires). For limiting the temperature of the PCB to a range from 100° C.-150° C. board the following range are expected to be adequate and sufficient.Wire size: 25 μm-100 μmWire length: 100 μm-2000 μmNail head width: 100 μm-200 μmWire pitch: 110 μm-250 μm.

If it is not desired to adjust the temperature resistance between the source pad and the clip, the above parameter ranges can be applied in combination or separately.

According toFIG.7B, the at least one electrical connector is provided by vertical electrical wire loops34as was shown in the example of a semiconductor package30inFIG.3. The two joints of each one of the wire loops34with the source pad12.1can be fabricated, e.g., by nail head bonding like with the vertical wires14ofFIG.7A. Alternatively, the wire loops34could be connected to the source pad21.1using other methods such as solder or a conductive glue.

According toFIG.7C, the at least one electrical connector is provided by stacked stud bumps44. A minimal height of each one of the stacked stud bumps44can be in the order of 100 μm.

According toFIG.7D, the at least one electrical connector is provided by a single piece of wire54. The joints of the single piece of wire54with the source pad12.1can be fabricated, e.g., by nail head bonding like with the vertical wires14ofFIG.7A.

In the following specific Examples of the present disclosure are described.

Example 1 is a semiconductor package, comprising a leadframe comprising a die carrier and at least one first lead connected with the die carrier, a semiconductor transistor die connected with the die carrier and comprising a first surface and a second surface opposite to the first surface, a source pad disposed on the first surface and a drain pad disposed on the second surface, wherein the first surface faces a bottom side of the semiconductor package and the second surface faces a top side of the semiconductor package, and a clip wherein the source pad is connected with the clip by at least one electrical connector.

Example 2 is the semiconductor package according to Example 1, wherein the source pad is connected with the clip by a plurality of electrical connectors.

Example 3 is the semiconductor package according to Example 2, wherein the plurality of electrical connectors comprise a plurality of wires connected between the source pad and the clip.

Example 4 is the semiconductor package according to Example 2, wherein the plurality of electrical connectors comprises a plurality of wire loops connected between the source pad and the clip.

Example 5 is the semiconductor package according to 2, wherein the plurality of electrical connectors comprises a plurality of stacked stud bumps connected between the source pad and the clip.

Example 6 is the semiconductor package according to Example 1, wherein the at least one electrical connector comprises a single piece of wire.

Example 7 is the semiconductor package according to any one of the preceding Examples, further comprising a gate pad disposed on the first surface and connected to a second lead.

Example 8 is the semiconductor package according to Example 7, further comprising a source/sense pad disposed on the first surface and connected to a third lead.

Example 9 is the semiconductor package according to any one of the preceding Examples, further comprising an encapsulant at least partially covering the die carrier, the semiconductor die and the clip.

Example 10 is the semiconductor package according to Example 9, wherein the clip comprises an external portion which is not covered by the encapsulant, and the at least one first lead is located on a first side of the encapsulant and the external portion of the clip is located on a second side of the encapsulant opposite to the first side.

Example 11 is the semiconductor package according to Examples 8 to 10, wherein the at least one first lead is located on a first side of the encapsulant and the second and third leads are located on a second side of the encapsulant opposite to the first side.

Example 12 is the semiconductor package according to any one of the preceding Examples, wherein the semiconductor package is configured as a surface mount device.

Example 13 is the semiconductor package according to any one of the preceding Examples, wherein the at least one electrical connector is connected to the source pad via nail contacts.

Example 14 is the semiconductor package according to any one of the preceding Examples, wherein the at least one electrical connector is configured so that a thermal resistance between the source pad and the clip is higher than a thermal resistance between the drain pad and the die carrier.

Example 15 is the semiconductor package according to Example 14, wherein the at least one electrical connector is configured so that a thermal resistance between the source pad and the clip is 2 or more times, 5 or more times, or 10 or more times higher than the thermal resistance between the drain pad and the die carrier.

Example 16 is the semiconductor package according to any one of the preceding examples, wherein the leadframe is configured as a single gauge leadframe.

Example 17 is the semiconductor package according to any one of Examples 1 to 15, wherein the leadframe is configured as a dual gauge leadframe.