Processor with inter-execution unit instruction issue

A processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units coupled to the instruction storage memory. A first of the execution units is configured to execute instructions provided from the instruction storage memory via a first instruction path, and to execute instructions provided by a second of the execution units via a second instruction path. The second of the execution units is configured to execute instructions provided from the instruction storage memory, and to provide instructions for execution to the first of the execution units via the second instruction path. The instruction merge unit is configured to merge the instructions provided via the first and second instruction paths into a stream of instructions to be executed by the first execution unit.

BACKGROUND

Microprocessors (processors) are instruction execution devices that are applied, in various forms, to provide control, communication, data processing capabilities, etc. to an incorporating system. Processors include execution units to provide data manipulation functionality. Exemplary execution units may provide arithmetic operations, logical operations, floating point operations etc. Processors invoke the functionality of the execution units in accordance with the requirements of the instructions executed by the processor.

SUMMARY

A processor and execution units providing inter-execution unit instruction issue are disclosed herein. In one embodiment, a processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units that are coupled to the instruction storage memory. A first of the execution units is configured to execute instructions provided from the instruction storage memory via a first instruction path, and to execute instructions provided by a second of the execution units via a second instruction path. The second of the execution units is configured to execute instructions provided from the instruction storage memory, and to provide instructions for execution to the first of the execution units via the second instruction path. The instruction merge unit is configured to merge the instructions provided via the first and second instruction paths into a stream of instructions to be executed by the first execution unit.

In another embodiment, a processor includes a primary execution unit, and a secondary execution unit coupled to the primary execution unit. The secondary execution unit is configured to provide instructions to the primary execution unit for execution by the primary execution unit in conjunction with execution of a given instruction by the secondary execution unit.

In a further embodiment, a processor includes a processor core, an instruction store, and a merge unit. The processor core includes a first execution unit and a second execution unit. The first execution unit includes registers and function logic, and is configured to execute instructions. The instruction store is configured to store instructions for execution by the first execution unit. The second execution unit includes registers and function logic, and is configured to: execute instructions, and to provide instructions to the first execution unit for execution in conjunction with an instruction executed by the second execution unit. The merge unit is coupled to the first execution unit and the second execution unit. The merge unit is configured to assign a priority value to each of the instruction store and the second execution unit, and to insert instructions from the instruction store and the second execution unit into a stream of instructions to be executed by the first execution unit in accordance with the assigned priorities. The merge unit is also configured to assert a wait signal to the first execution unit in conjunction with inserting an instruction from the second execution unit into the instruction stream to enable execution of the instruction from the second execution unit by the first execution unit.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. Further, the term “software” includes any executable code capable of running on a processor, regardless of the media used to store the software. Thus, code stored in memory (e.g., non-volatile memory), and sometimes referred to as “embedded firmware,” is included within the definition of software. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be based on Y and any number of other factors.

DETAILED DESCRIPTION

In conventional processor architectures, interaction between processing units is typically limited to data/status transfer and issuance of instructions from a CPU to coprocessor. In such architectures, transfer of data and/or status between execution units is accomplished via execution of dedicated data movement instructions, such as load and store. Because coprocessors may be restricted to an instruction set focused on a particular application, such floating point computation, graphics computation, etc., functionality not supported by the coprocessor is provided by a CPU that executes instructions provided from instruction storage such as cache or instruction memory. However, requiring the execution of additional instructions to transfer data and/or status between execution units increases processor power consumption, program execution time, and storage. Similarly, limited execution interaction between execution units unnecessarily limits overall processor performance and increases power consumption by requiring that CPU support of a coprocessor be initiated from an instruction stream provided from memory.

Embodiments of the processor disclosed herein include execution units that are capable of accessing functionality in other execution units by issuing instructions directly from one execution unit to another. For example, an execution unit dedicated to vector processing can issue logical operation instructions to a different execution that supports such operations in situations where logical operations are needed to support a vector operation. Thus, in some embodiments of the present disclosure, functionality of each execution unit can be limited to reduce hardware cost, but overall processor performance improved by allowing the execution units to access needed functionality provided by other execution units. Embodiments further improve performance by allowing execution units to directly access registers of other execution units without use of dedicated data movement instructions. For example, operands to be processed in an instruction executed by one execution unit can be accessed in registers of a different execution unit in the course of execution of the instruction. Similarly, a result of execution of the instruction can be stored in a register of a different execution in the course of execution of the instruction.

FIG. 1shows a block diagram of a processor100in accordance with various embodiments. The processor100includes a plurality of execution units102,104,106,108. Other embodiments may include a different number of execution units. The processor100also includes an instruction fetch unit110, a data access unit112, and one or more instruction decode units114. Some embodiments further include one or more instruction buffers116. In some embodiments of the processor100, two or more of the execution units102-108may be components of a single processor core. The processor100may also include other components and sub-systems that are omitted fromFIG. 1in the interest of clarity. For example, the processor100may include data/instruction storage resources, such as random access memory, communication interfaces and peripherals, timers, analog-to-digital converters, clock generators, debug logic, etc.

One or more of the execution units102-108can execute a complex instruction. For example, an execution unit (EU)102-108may be configured to execute a fast Fourier transform (FFT) instruction, execute a finite impulse response (FIR) filter instruction, an instruction to solve a trigonometric function, an instruction to evaluate a polynomial, an instruction to compute the length of a vector, etc. The execution units102-108allow complex instructions to be interrupted prior to completion of the instruction's execution. While an execution unit (e.g., EU108) is servicing an interrupt, other execution units (EU102-106) continue to execute other instructions. The execution units102-108may synchronize operation based on a requirement for a result and/or status generated by a different execution unit. For example, an execution unit102that requires a result value from execution unit104may stall until the execution unit104has produced the required result. In some embodiments, one execution unit (e.g.,102) may serve as a primary execution for the processor100, and other execution units (e.g.,104-108) may serve as secondary execution units.

To facilitate efficient execution of complex and other data manipulation and processing instructions, an execution unit (e.g.,108) can access data and/or functionality of a different one or more of the execution units102-106as part of or in conjunction with execution of the instruction. For example, in executing an instruction, the execution unit104may access operands stored in execution unit102, and/or store a result of processing the operands in execution unit102. Similarly, an execution unit (e.g.,104) can execute status dependent instructions and instruction sequences based on status stored in different ones of the execution units (e.g.,102). Thus, a status dependent program flow control instruction executed by the execution unit104can be predicated on status stored in a different execution unit without requiring addition instructions to transfer the status to execution unit104. An execution unit (e.g.,104) can access functionality of a different execution unit (e.g.,102) by issuing instructions to the execution unit102for execution. The instructions issued by execution104may be stored in execution unit104for issuance that is triggered by execution, in execution unit104, of an instruction requiring the functionality provided by execution of the stored instructions in execution unit102. Such instruction issuance may be triggered by a dedicated field of the instruction executed by execution unit104, or by information stored in execution unit104indicating that and when stored instructions are to be issued to execution unit102. For example, a state machine controlling execution of a given instruction in execution unit104may be arranged to issue stored instructions at a predetermined state of execution of the given instruction. Providing such interaction directly between execution units102-108allows processor components, such as memories, bus interfaces, etc. that are not involved in the interaction to stay in the current power state or to transition to a reduced power state, thereby reducing overall processor power consumption, without reduction in processor functionality.

The instruction fetch unit110retrieves instructions from storage (not shown) for execution by the processor100. The instruction fetch unit110may provide the retrieved instructions to a decode unit114. The decode unit114examines instructions, locates the various control sub-fields of the instructions, and generates decoded instructions for execution by the execution units102-108. Instruction dispatch logic may be associated with the decode unit114. As shown inFIG. 1, multiple execution units may receive decoded instructions from an instruction decoder114. In some embodiments, an instruction decoder114may be dedicated to one or more execution units. Thus, each execution unit102-108may receive decoded instructions from an instruction decoder114coupled to only that execution unit, and/or from an instruction decoder114coupled to a plurality of execution units102-108. Some embodiments of the processor100may also include more than one fetch unit110, where a fetch unit110may provide instructions to one or more instruction decoder114.

Embodiments of the processor100may also include one or more instruction buffers116. The instruction buffers116store instructions for execution by the execution units102-108. An instruction buffer116may be coupled to one or more execution units102-108. An execution unit may execute instructions stored in an instruction buffer116, thereby allowing other portions of the processor100, for example other instruction buffers116, the instruction fetch unit110, an instruction storage (not shown), etc., to be maintained in a low-power or inoperative state. An execution unit may lock or freeze a portion of an instruction buffer116, thereby preventing the instructions stored in the locked portion of the instruction buffer116from being overwritten. Execution of instructions stored in an instruction buffer116(e.g., a locked portion of an instruction buffer116) may save power as no reloading of the instructions from external memory is necessary, and may speed up execution when the execution unit executing the instructions stored in the instruction buffer116is exiting a low-power state. An execution unit may call instructions stored in a locked portion of an instruction buffer116and return to any available power mode and/or any state or instruction location. The execution units102-108may also bypass an instruction buffer116to execute instructions not stored in the instruction buffer116. For example, the execution unit104may execute instructions provided from the instruction buffer116, instructions provided by the instruction fetch unit110that bypass the instruction buffer116, and/or instructions provided by an execution unit102,106-108.

The instruction buffers116may also store, in conjunction with an instruction, control or other data that facilitate instruction execution. For example, information specifying a source of an instruction execution trigger, trigger conditions and/or trigger wait conditions, instruction sequencing information, information specifying whether a different execution unit or other processor hardware is to assist in instruction execution, etc. may be stored in an instruction buffer116in conjunction with an instruction.

The data access unit112retrieves data values from storage (not shown) and provides the retrieved data values to the execution units102-108for processing. Similarly, the data access unit112stores data values generated by the execution units102-108in a storage device (e.g., random access memory external to the processor100, register of a peripheral device, etc.). Some embodiments of the processor100may include more than one data access unit112, where each data access unit112may be coupled to one or more of the execution units102-108.

The execution units102-108may be configured to execute the same instructions, or different instructions or any mix of same and different instructions. For example, given an instruction set that includes all of the instructions executable by the execution units102-108, in some embodiments of the processor100, all or a plurality of the execution units102-108may be configured to execute all of the instructions of the instruction set. Alternatively, some execution units102-108may execute only a sub-set of the instructions of the instruction set, or may execute a different instruction set. At least one of the execution units102-108is configured to execute a complex instruction that requires a plurality of instruction cycles to execute.

Each execution unit102-108is configured to control access to the resources of the processor100needed by the execution unit to execute an instruction. For example, each execution unit102-108can enable power to an instruction buffer116if the execution unit is to execute an instruction stored in the instruction buffer116while other instruction buffers, and other portions of the processor100, remain in their current power state, which can be a low-power state. Thus, each execution unit102-108is able to independently control access to resources of the processor100(power, clock frequency, etc.) external to the execution unit needed to execute instructions, and to operate independently from other components of the processor100.

FIG. 2shows a block diagram for an execution unit108in accordance with various embodiments. The block diagram and explanation thereof may also be applicable to embodiments of the execution units102-106. The execution unit108includes function logic202, registers204, and instruction execution logic210. The function logic202includes the arithmetic, logical, and other data manipulation resources for executing the instructions relevant to the execution unit108. For example, the function logic may include adders, multipliers, shifters, logical functions, etc. for integer, fixed point, and/or floating point operations in accordance with the instructions to be executed by the execution unit108.

The registers204include data registers206and status registers208. The data registers206store operands and/or pointers to operand to be processed by, and results produced by, the function logic202. The data registers may also store addresses, control information, configuration information, etc. The number and/or size of registers included in the data registers206may vary across embodiments. For example, one embodiment may include 16 16-bit data registers, and another embodiment may include a different number and/or width of registers. The status registers208include one or more registers that store state information (condition codes) produced by operations performed by the function logic202and/or store instruction execution and/or execution unit state information. State information stored in a status register208may include a zero result indicator, a carry indicator, result sign indicator, overflow indicator, interrupt enable indicator, instruction execution state, etc.

The instruction execution logic210controls the sequencing of instruction execution in the execution unit108. The instruction execution logic210may include one or more state machines that control the operations performed by the function logic202and transfer of data between the registers204, the function logic202, other execution units102-106, the data access unit112, and/or other components of the processor100in accordance with an instruction being executed. For example, the instruction execution logic210may include a state machine or other control system that sequences the multiple successive operations of a complex instruction being executed by the execution unit108.

As part of sequencing instruction execution, the instruction execution logic210can initiate and control issuance of instructions to the execution unit102and/or other execution units (e.g., execution units102-106). The instruction execution logic210includes stored instructions212that the instruction execution logic210may issue to the execution unit102or a different execution unit to, for example, support execution of an instruction being executed by execution unit108. For example, if execution of an instruction in execution unit108requires some particular operations that can only be performed by execution unit102, in addition to operations that can be performed by execution unit108, then the stored instructions212may include instructions that instruction execution logic210causes to be issued to execution unit102for performance of the particular operations. To optimize performance, the instruction execution logic210may issue the instructions with timing that results in generation of result by the different execution unit at or prior to a state of execution (or execution pipeline state) of the execution unit108in which the result is needed. Information applied by the instruction execution logic210to direct instruction issue may be derived from a field of an instruction being executed by the execution unit108, included in a state machine, provided by previously executed instructions, or otherwise stored in or provided to the instruction execution logic210.

The stored instructions212may be stored in volatile or non-volatile memory, registers, or coded in programmable or fixed logic circuitry. Instructions may be stored at any time prior issuance. For example, instructions may be pre-programmed at manufacture, loaded at run-time, etc. In some embodiments, the stored instructions212may be located outside the issuing execution unit.

Similarly, the instruction execution logic210controls access of registers204of other execution units as part of instruction execution sequencing. Registers of execution units to be accessed in executing an instruction may be identified by a field of the instruction being executed, coded into an instruction execution state machine, or stored in a register or memory of the execution unit108at any time prior register access.

The execution unit108also includes resource control logic214. The resource control logic214requests access to the various resources (e.g., storage, power, clock frequency, etc.) of the processor100that the execution unit108uses to execute an instruction. By requesting processor resources independently for each execution unit102-108, the power consumed by the processor100may be reduced by placing only components of the processor100required for instruction execution by an active execution unit102-108in an active power state. Furthermore, execution units102-108not executing instructions may be placed in a low-power state to reduce the power consumption of the processor100.

FIG. 3shows an instruction300executable by at least one of the execution units of the processor100. The instruction300includes a field302specifying inter-execution unit instruction issue in accordance with various embodiments. Information provided in the EUIA field302may directly or indirectly (e.g., via pointer) specify whether an instruction is to be issued, to what execution unit the instruction is to issued, what instruction is to be issued, timing of instruction issue, and/or parameters of an instruction to be issued, etc. Some embodiments of the instruction300may include more than one EUIA field302where each EUIA field302is directed to issuance of one or more instructions to an execution unit.

FIGS. 4A-4Bshow an example of execution interoperation including inter-execution unit instruction issue in accordance with various embodiments. InFIGS. 4A-4B, instructions Instr_m1to Instr_m4are fetched and executed by execution unit (EU)102, which may be the CPU of the processor100. Instruction EU_Instr_n1is fetched next and directed to EU104for execution. EU104transitions through execution states EU_Instr_n.1.1to EU_Instr_n1.7while executing instruction EU_Instr_n1. EU104issues the instructions Instr_m5_EU to Instr_m8_EU to EU102for execution. For example, EU104may issue the instructions Instr_m5_EU to Instr_m8_EU from stored instructions212in conjunction with execution state EU_Instr_n1.7. The instructions Instr_m5_EU to Instr_m8_EU may, for example, cause EU102to further process a result of execution of the instruction EU_Instr_n1while allowing instruction memories, bus components, etc. of the processor100to remain in a reduced power state. EU104next executes instruction EU_Instr_n2and issues instructions Instr_m9_EU to Instr_m10_EU for execution by EU102, and finally executes instructions EU_Instr_n3and issues instructions Instr_m11_EU to Instr_m13_EU for execution by EU102.

FIG. 5shows a block diagram of execution units102,104in the processor100and data exchanges performed during execution unit interoperation in accordance with various embodiments. The execution unit104, for example, can transfer data between the function logic202of the execution unit104and the registers204of the execution unit102, and/or transfer data between the registers204of the execution unit102and the registers204of the execution unit104. Such data transfers may be performed during instruction execution without additional cycle overhead, as would be required to transfer data between execution units using a different instruction (e.g., a load or store instruction). The transfers include providing data and/or status to the function logic202from the data registers206and/or status registers208, and/or providing processing results and/or status to data registers206and/or status registers208.

FIG. 5also shows that the execution units102,104can transfer data directly between the registers204of the different execution units. Accordingly, the execution units can perform a context switch by moving register contents from one execution unit to another. Thus, if the execution unit102needs to store context for an interrupt service, task switch, etc., and the registers of execution unit104are not in use, then the execution unit102can transfer the contents one or more of the registers204of the execution unit102to registers204of the execution unit104. Registers of the execution unit104may be cleared in conjunction with the transfer to avoid residual data. Moving the contents of the registers204of the execution unit104to the registers202of the execution102restores the context. Thus, embodiments of the processor100reduce the energy and time expended in context switching by reducing the memory accesses required to store and restore register contents.

FIG. 6shows a block diagram of execution units102,104in the processor100providing inter-execution unit instruction issue in accordance with various embodiments. InFIG. 6, the execution unit104includes stored instructions212. The execution unit104may be triggered to issue instructions to the execution unit102by execution of a particular instruction in the execution unit104that requires operations not provided by the execution unit104. The particular instruction may specify the instructions to be issued, destination, parameters, etc., or such information may have been previously stored in the execution unit104. InFIG. 6, the instructions issued by the execution unit104are routed to the instruction fetch unit110, and are interleaved with instructions provided from an instruction memory, decoded by the instruction decode unit114, and provided to the execution unit102for execution. In the embodiment ofFIG. 6, the execution unit104may issue each instruction to the execution unit102individually.

FIG. 7shows a block diagram of an alternative arrangement of execution units102,104in the processor100providing inter-execution unit instruction issue in accordance with various embodiments. In the embodiment ofFIG. 7, instructions issued by the execution unit104are directed to the instruction fetch/store unit702and stored (e.g., in a fetch buffer or cache). Thus, the execution unit104may issue a number of instructions for execution by the execution unit102, rather than issuing instructions individually as in the embodiment ofFIG. 6. The instructions issued by the execution unit104are output by the fetch unit702and interleaved with instructions provided from instruction memory via the fetch unit110, decoded by the decode unit114, and provided to the execution unit102for execution. Instructions stored in the fetch/store unit702may be repeatedly issued therefrom as needed to the execution unit102thereby reducing processor100energy consumption. Repeated issue of instructions from the instruction fetch/store unit702may be controlled by the execution unit104.

In some embodiments of the processor100, an execution unit may indirectly issue instructions for execution by a different execution unit. For example, referring toFIG. 7, the execution unit104may provide an address value and number of instructions (or other information indicating what instructions are being issued) to the fetch unit702. The fetch unit702may retrieve the instructions from storage, if the instructions are not already stored in the fetch unit702, and provide the instructions to the execution unit102as described with regard toFIG. 7.

FIG. 8shows a block diagram of a portion of the processor100including a merge unit802that manages integration of instructions issued from different instruction sources in accordance with various embodiments. The merge unit802is coupled to the execution units102,104and the instruction fetch unit110. The merge unit802manages the merger of instructions provided from multiple instruction paths. InFIG. 8, one instruction path provides instructions to execution unit102from an instruction memory, and another instruction path provides instructions by issued by execution unit104to execution unit102.

The merge unit802may apply a variety of techniques to manage the merger or interleaving of instructions provided via the different instruction paths. In one embodiment, the merger unit802may control the fetch unit110and/or the execution unit104, and cause instructions to be provided to execution unit102from either instruction path. The merger unit802receives information from the execution unit102that indicates the execution state of execution102. For example, execution unit102may indicate to the merge unit802whether the execution unit102is stalled, in a wait condition that inhibits execution of instructions from one or the other instruction path, etc. The execution unit104may indicate to the merger unit802that execution unit104is ready to issue instructions to execution unit102.

Based on the information received from the execution units102,104the merge unit802may control the execution units102,104and the fetch unit110to direct instructions from a selected instruction source (e.g., instruction memory, execution unit102, etc.) to execution unit102via the instruction path used by the source to provide instructions. For example, if the execution unit102is in a stalled state or is idle waiting for a time interval to expire or an event to occur, then the merge unit802may indicate to the execution unit104that instructions may be issued to the execution unit102. In some embodiments, if execution unit104indicates to the merge unit802that the execution unit104is ready to issue instructions to the execution unit102, then the merge unit802may assert a control signal to the execution unit102that causes the execution unit102to enter a stalled or idle state. Thereafter, the merge unit802may direct the execution unit104to issue instructions to the execution unit102.

In some embodiments of the processor100, the merge unit802may assign a priority to each instruction path or instruction source, and enable instructions to the execution unit102from each instruction path in accordance with the assigned priorities. For example, based on the assigned priorities, the merge unit802may allow instructions from a lower priority instruction path to be provided to the execution unit102only if no instructions are available via a higher priority instruction path, or the execution unit102is not enabled (e.g., idle or stalled) to execute instructions provided via the higher priority instruction paths.

The merge unit may also issue an interrupt to the execution unit102, the service of which causes the execution unit102to execute instructions provided via a particular instruction path. The merge unit802may issue such an interrupt to the execution unit102when the execution unit104indicates that instructions are to be issued to the execution unit102by the execution unit104. Alternatively, the merge unit802may assert a wait signal to the execution unit102that causes the execution unit102to stall or enter an idle state with respect execution of instructions from one instruction path (e.g., instructions from the instruction memory), and allows instructions issued by execution unit104to be executed.

In some embodiments, merge unit802may analyze the instructions provided via an instruction path to determine how many instructions from the path should be executed in sequence. For example, the instructions may include a field that specifies how many instructions are to be atomically executed, where atomic execution refers to execution without interruption. Similarly, the instruction source (e.g., execution unit104) may indicate to the merge unit802how many instructions issued from the instruction source are to be executed without interruption.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, while various operations and functions of the processor100have been described with reference to particular execution units, it is to be understood that the described operations and functions are not limited to any particular execution units. It is intended that the following claims be interpreted to embrace all such variations and modifications.