Semiconductor devices and methods of manufacturing thereof

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

BACKGROUND

The present disclosure generally relates to semiconductor devices, and particularly to methods of making a non-planar transistor device.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in the context of forming a gate-all-around (GAA) field-effect-transistor (FET) device, and in particular, in the context of forming a replacement gate of a GAA FET device. In some embodiments, after forming a fin including a number of first semiconductor layers and a number of second semiconductor layers, which serve as sacrificial layers and channel layers, respectively, a connected (or interfacial) layer is formed over the fin. The connected layer may present a certain etching selectivity with respect to respective materials of the first and second semiconductor layers. Next, a dummy gate structure is formed over the fin, followed by a pull-back process that etches end portions of the sacrificial (first semiconductor) layers of the fin and end portions of the dummy gate structure more quickly than the connected layer (along a lengthwise direction of the fin). The respective etched portions (of the sacrificial layers and the dummy gate structure) are then filled with inner spacers. Next, source/drain structures are formed on opposite sides of the dummy gate structure, with an interlayer dielectric (ILD) overlaying them. Upon forming the ILD, the dummy gate structure is removed to form a gate trench. Next, the sacrificial layers are removed to extend the gate trench. An active gate structure is next formed in the gate trench to wrap around each of the channel layers.

An active gate structure formed by the above described method can provide various advantages in advanced technology nodes. In general, a dummy gate structure is replaced with an active gate structure, and thus, the active gate structure may inherit the dimensions and profiles of the dummy gate structure (as formed). The existing technologies, however, face various issues, when forming the dummy gate structure over a fin that have first and second semiconductor layers formed of different materials. For example, the interface between the dummy gate structure and the fin is relatively rough (which may in turn result in forming one or more voids after the dummy gate structure is replaced). This may be partially due to the different materials of the first and second semiconductor layers having respective interfacial reaction with the dummy gate structure. By overlaying the fin with the disclosed connected layer that may “integrate” such different materials of the first and second semiconductor layers, the above-identified issues may be avoided. Further, the dummy gate structure can have a relatively smooth interface contacting the fin (or the connected layer), which can enhance overall performance of the formed device (e.g., by increasing controllability of the active gate structure that replaces the dummy gate structure).

FIG. 1illustrates a perspective view of an example GAA FET device100, in accordance with various embodiments. The GAA FET device100includes a substrate102and a number of nanostructures (e.g., nanosheets, nanowires, etc.)104above the substrate102. The semiconductor layers104are vertically separated from one another. Isolation regions106are formed on opposing sides of a protruded portion of the substrate102, with the nanostructures104disposed above the protruded portion. A gate structure108wraps around each of the nanostructures104(e.g., a full perimeter of each of the nanostructures104). Source/drain structures are disposed on opposing sides of the gate structure108, e.g., source/drain structure110shown inFIG. 1. An interlayer dielectric (ILD)112is disposed over the source/drain structure110.

FIG. 1depicts a simplified GAA FET device, and thus, it should be understood that one or more features of a completed GAA FET device may not be shown inFIG. 1. For example, the other source/drain structure opposite the gate structure108from the source/drain structure110and the ILD disposed over such a source/drain structure are not shown inFIG. 1. Further,FIG. 1is provided as a reference to illustrate a number of cross-sections in subsequent figures. As indicated, cross-section A-A is cut along a longitudinal axis of the gate structure108(e.g., in the X direction); cross-section B-B is cut along a longitudinal axis of one of the semiconductor layers104; cross-section C-C, which is parallel with cross-section B-B, is cut between two adjacent ones of the semiconductor layers104; and cross-section D-D, which is perpendicular to the cross-section A-A, is cut along a longitudinal axis of the semiconductor layers104and in a direction of a current flow between the source/drain structures (e.g., in the Y direction). Subsequent figures refer to these reference cross-sections for clarity.

FIG. 2illustrates a flowchart of a method200to form a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method200can be used to form a FinFET device, a GAA FET device (e.g., GAA FET device100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a gate-all-around (GAA) transistor device, or the like. It is noted that the method200is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method200ofFIG. 2, and that some other operations may only be briefly described herein. In some embodiments, operations of the method200may be associated with cross-sectional views of an example GAA FET device at various fabrication stages as shown inFIGS. 3, 4A, 4B, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8, 9A, 9B, 9C, 9D, 9E, 10A, 10B, 10C,10D,10E,11A,11B,11C,11D,11E,11F,11G,11H,11I,11J, and11K, respectively, which will be discussed in further detail below.

In brief overview, the method200starts with operation202of providing a substrate. The method200continues to operation204of forming a fin structure including a number of first semiconductor layers and a number of second semiconductor layers. The method200continues to operation206of forming an isolation structure. The method200continues to operation208of forming a connected layer over the fin structure. The method200continues to operation210of forming a dummy gate structure. The method200continues to operation212of removing portions of the fin structure. The method200continues to operation214of etching portions of the first semiconductor layers and portions of the dummy gate structure. The method200continues to operation216of forming inner spacers. The method200continues to operation218of removing the first semiconductor layers and forming an active gate structure.

As mentioned above,FIGS. 3-11Keach illustrate, in a cross-sectional view, a portion of a GAA FET device300at various fabrication stages of the method200ofFIG. 2. The GAA FET device300is similar to the GAA FET device100shown inFIG. 1, but with certain features/structures/regions not shown, for the purposes of brevity. For example, the following figures of the GAA FET device300do not include source/drain structures (e.g.,110ofFIG. 1). It should be understood the GAA FET device300may further include a number of other devices (not shown in the following figures) such as inductors, fuses, capacitors, coils, etc., while remaining within the scope of the present disclosure.

Corresponding to operation202ofFIG. 2,FIG. 3is a cross-sectional view of the GAA FET device300including a semiconductor substrate302at one of the various stages of fabrication. The cross-sectional view ofFIG. 3is cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG. 1).

Corresponding to operation204ofFIG. 2,FIG. 4Ais a cross-sectional view of the GAA FET device300including a number of first semiconductor layers410and a number of second semiconductor layers420formed on the substrate302at one of the various stages of fabrication. Still corresponding to operation204ofFIG. 2,FIG. 4Bis a cross-sectional view of the GAA FET device300including a different number of the first semiconductor layers410and the same number of second semiconductor layers420formed on the substrate302at one of the various stages of fabrication. The cross-sectional views ofFIGS. 4A-Bare each cut in a direction2extending along the Y direction, respectively. The sidewalls of the acte of the GAA FET device300(e.g., cross-section A-A indicated inFIG. 1).

Referring first toFIG. 4A, the first semiconductor layers410and the second semiconductor layers420are alternatingly disposed on top of one another (e.g., along the Z direction) to form a first stack. For example, one of the second semiconductor layers420is disposed over one of the first semiconductor layers410then another one of the first semiconductor layers420is disposed over the second semiconductor layer410, so on and so forth. Similarly, inFIG. 4B, the first semiconductor layers410and the second semiconductor layers420are alternatingly disposed on top of one another (e.g., along a vertical direction) to form a second stack.

The first and second stacks may include any number of alternately disposed first and second semiconductor layers410and420, respectively. For example inFIG. 4A, the first stack includes 4 first semiconductor layers410, with 3 second semiconductor layers420alternatingly disposed therebetween and with one of the first semiconductor layers410being the topmost semiconductor layer. For example inFIG. 4B, the second stack includes 3 first semiconductor layers410, with 2 second semiconductor layers420alternatingly disposed therebetween and with one of the second semiconductor layer420being the topmost semiconductor layer. It should be understood that the GAA FET device300can include any number of first semiconductor layers and any number of second semiconductor layers, with either one of the first or second semiconductor layers being the topmost semiconductor layer, while remaining within the scope of the present disclosure. Thus, in most of the following discussion, the stack shown inFIG. 4Awill be used as a representative example.

The semiconductor layers410and420may have respective different thicknesses. Further, the first semiconductor layers410may have different thicknesses from one layer to another layer. The second semiconductor layers420may have different thicknesses from one layer to another layer. The thickness of each of the semiconductor layers410and420may range from few nanometers to few tens of nanometers. The first layer of the stack may be thicker than other semiconductor layers410and420. In an embodiment, each of the first semiconductor layers410has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each of the second semiconductor layers420has a thickness ranging from about 5 nm to about 20 nm.

The two semiconductor layers410and420have different compositions. In various embodiments, the two semiconductor layers410and420have compositions that provide for different oxidation rates and/or different etch selectivity between the layers. In an embodiment, the first semiconductor layers410include silicon germanium (Si1-xGex), and the second semiconductor layers include silicon (Si). In an embodiment, each of the semiconductor layers420is silicon that may be undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed when forming the layers420(e.g., of silicon).

In various embodiments, the semiconductor layers420may be intentionally doped. For example, when the GAA FET device300is configured in n-type (and operates in an enhancement mode), each of the semiconductor layers420may be silicon that is doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the GAA FET device300is configured in p-type (and operates in an enhancement mode), each of the semiconductor layers420may be silicon that is doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb). In another example, when the GAA FET device300is configured in n-type (and operates in a depletion mode), each of the semiconductor layers420may be silicon that is doped with an n-type dopant instead; and when the GAA FET device300is configured in p-type (and operates in a depletion mode), each of the semiconductor layers420may be silicon that is doped with a p-type dopant instead. In some embodiments, each of the semiconductor layers410is Si1-xGexthat includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the semiconductor layers410of Si1-xGexin molar ratio. Furthermore, the first semiconductor layers410may include different compositions among them, and the second semiconductor layers420may include different compositions among them.

Either of the semiconductor layers410and420may include other materials, for example, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. The materials of the semiconductor layers410and420may be chosen based on providing differing oxidation rates and/or etch selectivity.

The semiconductor layers410and420can be epitaxially grown from the semiconductor substrate302. For example, each of the semiconductor layers410and420may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and/or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate302extends upwardly, resulting in the semiconductor layers410and420having the same crystal orientation with the semiconductor substrate302.

Upon growing the semiconductor layers410and420on the semiconductor substrate302(as a stack), the stack may be patterned to form one or more fin structures (e.g.,401). Each of the fin structures is elongated along a lateral direction (e.g., the Y direction), and includes a stack of patterned semiconductor layers410-420interleaved with each other. The fin structure401is formed by patterning the semiconductor layers410-420and the semiconductor substrate302using, for example, photolithography and etching techniques. For example, a mask layer (which can include multiple layers such as, for example, a pad oxide layer and an overlying pad nitride layer) is formed over the topmost semiconductor layer (e.g.,410inFIG. 4A, or420inFIG. 4B). The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer may act as an adhesion layer between the topmost semiconductor layer410(or the semiconductor layer420in some other embodiments) and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example.

The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer and pad nitride layer to form a patterned mask.

The patterned mask can be subsequently used to pattern exposed portions of the semiconductor layers410-420and the substrate302to form trenches (or openings), thereby defining the fin structures401between adjacent trenches. When multiple fin structures are formed, such a trench may be disposed between any adjacent ones of the fin structures. In some embodiments, the fin structure401is formed by etching trenches in the semiconductor layers410-420and substrate302using, for example, reactive ion etch (ME), neutral beam etch (NBE), the like, or combinations thereof. The etch may be anisotropic. In some embodiments, the trenches may be strips (when viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches may be continuous and surround the fin structure401.

Corresponding to operation206ofFIG. 2,FIG. 5Ais a cross-sectional view of the GAA FET device300including one or more isolation structures502, at one of the various stages of fabrication. The cross-sectional view ofFIG. 5Ais cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG. 1). Also corresponding to the same operation206,FIGS. 5B and 5Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG. 1), respectively.

The isolation structure502, which can includes multiple portions, may be formed between adjacent fin structures, or next to a single fin structure. The isolation structure502, which are formed of an insulation material, can electrically isolate neighboring fin structures from each other. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other insulation materials and/or other formation processes may be used. In an example, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP) process, may remove any excess insulation material and form a top surface of the insulation material and a top surface of a patterned mask (not shown) defining the fin structure401. The patterned mask may also be removed by the planarization process, in various embodiments.

Next, the insulation material is recessed to form the isolation structure502, as shown inFIG. 5A, which is sometimes referred to as a shallow trench isolation (STI). The isolation structure502is recessed such that the fin structure401protrudes from between neighboring portions of the isolation structure502. The top surface of the isolation structures (STIs)502may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or combinations thereof. The top surface of the isolation structure502may be formed flat, convex, and/or concave by an appropriate etch. The isolation structure502may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation structure502. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation structure502.

As mentioned above, each of the first semiconductor layers410and second semiconductor layer420of the fin structure401is elongated along a lateral direction (e.g., the Y direction). For example inFIG. 5B, the second semiconductor layer420extends along the Y direction, with portions of the isolation structure502disposed next to the sides of the second semiconductor layer420along the X direction. For example inFIG. 5C, the first semiconductor layer410extends along the Y direction, with portions of the isolation structure502disposed next to the sides of the first semiconductor layer410along the X direction.

Corresponding to operation208ofFIG. 2,FIG. 6Ais a cross-sectional view of the GAA FET device300including a connected layer602, at one of the various stages of fabrication. The cross-sectional view ofFIG. 6Ais cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG. 1). Also corresponding to the same operation208,FIGS. 6B and 6Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG. 1), respectively.

As shown inFIG. 6A, the connected layer602may be (e.g., conformally) formed to overlay the fin structure401and the isolation structure502. For example, the connected layer602overlays a top surface of the fin structure401and extends along sidewalls of the fin structure401, and further extends along the X direction, for example, to overlay the top surface of the isolation structure502. As such, the connected layer602extends along sidewalls of each of the first semiconductor layers410and each of the second semiconductor layers420(that extend along the Y direction), as illustrated inFIGS. 6B and 6C.

In some embodiments, the connected layer602may be formed with a relatively thin thickness (e.g., from about 2 angstroms (Å) to about 50 (Å)) to smooth the surfaces of the fin structure401, which may be constituted by multiple different materials. As such, a structure (e.g., a dummy gate structure, and a corresponding active gate structure) overlaying the fin structure401can be in better contact with the surfaces of the fin structure401, which can significantly limit the odds of forming voids along the surfaces of the fin structure401. Further, in some embodiments, the connected layer602may include one or more materials that have a certain etching selectivity with respect to the materials of the first and second semiconductor layers,410and420, and the lower portion of a dummy gate structure. Accordingly, in one or more subsequent fabrication stages (e.g., etching portions of the first semiconductor layers and/or the dummy gate structure to form inner spacers), the first semiconductor layers and the dummy gate structure may each present a curvature-based profile, which will be discussed in further detail below.

In some embodiments, the connected layer602may be formed by treating the fin structure401having the first and second semiconductor layers410and420. The treatment can include oxidizing, nitridizing, and/or sulfurizing the fin structure401. As such, the connected layer602may include one or more treated materials of the first and second semiconductor layers410and420. In an example where the first semiconductor layers410include SiGe and the second semiconductor layers420include Si, the connected layer602may include at least one of SiGeO or SiO (e.g., through an oxidizing treatment). In the same example, the connected layer602may include at least one of SiGeN or SiN (e.g., through a nitridizing treatment). Continuing with the same example, the connected layer602may include at least one of SiGeS or SiS (e.g., through a sulfurizing treatment).

For example, the connected layer602may be formed by performing an in-situ or ex-situ plasma process on the fin structure401. In such a plasma process, passivation gases, such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof, can be used. Moreover, the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof to reach a certain condition. As a non-limiting example, a source power of 10 watts to 3000 watts, a bias power of 0 watts to 3000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 standard cubic centimeters per minute to 5000 standard cubic centimeters per minute may be used in the plasma process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges can also be contemplated.

In another example, the connected layer602may be formed by performing an ex-situ chemical/wet process on the fin structure401. In such a chemical/wet process, passivation gases, such as ozone (O3), carbon dioxide (CO2), and other suitable passivation gases and combinations thereof, can be used, with assistive etch chemicals, such as sulfuric acid (H2SO4), ammonia (NH3), and other suitable assistive etch chemicals and combinations thereof as well as solvents such as deionized water, alcohol, acetone, and other suitable solvents and combinations thereof.

In some other embodiments, the connected layer602may be formed by depositing a material over the fin structure401. In such a case, the connected layer602may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or combinations thereof. The deposition can include CVD, PECVD, ALD, FCVD, or combinations thereof.

Corresponding to operation210ofFIG. 2,FIG. 7Ais a cross-sectional view of the GAA FET device300including a dummy gate structure702, at one of the various stages of fabrication. The cross-sectional view ofFIG. 7Ais cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG. 1). Also corresponding to the same operation210,FIGS. 7B and 7Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG. 1), respectively.

Next, the dummy gate structure702is formed over the fin structure401and the isolation structure502, with the connected layer602disposed therebetween. The dummy gate structure702can extend along a lateral direction (e.g., the X direction) perpendicular to the lateral direction along which the fin structure401extends. The dummy gate structure702may be placed where an active (e.g., metal) gate structure is later formed, in various embodiments. In some embodiments, the dummy gate structure702is placed over a portion of fin structure401, with the connected layer602sandwiched therebetween. Such an overlaid portion of the fin structure401is later formed as a conduction channel, which includes portions of the second semiconductor layers420and portions of the first semiconductor layers410that are each replaced with an active gate structure. As such, the active gate structure can wrap around each of the portions of the second semiconductor layers420, which will be discussed in further detail below.

In some embodiments, the dummy gate structure702can include one or more Si-based or SiGe-based materials that are similar (or having similar etching rates) as the first semiconductor layers410such as, for example, SiGe. The dummy gate structure702may be deposited by CVD, PECVD, ALD, FCVD, or combinations thereof. Although the dummy gate structure702is shown as being formed as a single-piece in the illustrated embodiment ofFIG. 7A, it should be understood that the dummy gate structure702can be formed to have multiple portions, each of which may include respective different materials. For example, the dummy gate structure702may include a lower portion that extends from the isolation structure502to around a top surface of the connected layer602, and an upper portion that further extends from the lower portion. In such embodiments, the lower portion of the dummy gate structure702can include the above-mentioned material that has a similar etching rate as the first semiconductor layers410(e.g., SiGe), and the upper portion of the dummy gate structure702can include a material that has a certain etching selectivity with respect to the fin structure401or is unfavorable to epitaxially grow source/drain structures.

Corresponding to operation212ofFIG. 2,FIG. 8is a cross-sectional view of the GAA FET device300in which portions of the fin structure401that are not overlaid by the dummy gate structure702are removed, at one of the various stages of fabrication. The cross-sectional view ofFIG. 8is cut in the lengthwise direction of a fin structure of the GAA FET device300(e.g., cross-section D-D indicated inFIG. 1).

The dummy gate structure702can serve as a mask to etch the non-overlaid portions of the fin structure401, which results in the fin structure401having one or more alternatingly stacks including remaining portions of the semiconductor layers410and420. As a result, along the Z direction, newly formed sidewalls of each of the fin structures401are aligned with sidewalls of the dummy gate structure702. For example inFIG. 8, semiconductor layers810and820are the remaining portions of the semiconductor layers410and420overlaid by the dummy gate structure702, respectively. In some embodiments, the semiconductor layers810and820may sometimes be referred to as nanostructures (e.g., nanosheets)810and820, respectively.

Corresponding to operation214ofFIG. 2,FIG. 9Ais a cross-sectional view of the GAA FET device300in which end portions of the nanostructures810(along the Y direction) are etched, at one of the various stages of fabrication. The cross-sectional view ofFIG. 9Ais cut in the lengthwise direction of a fin structure of the GAA FET device300(e.g., cross-section D-D indicated inFIG. 1). Also corresponding to the same operation214,FIGS. 9B and 9Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG. 1), respectively.

As shown inFIG. 9A, respective end portions of each of the nanostructures810are removed. The end portions of the nanostructures810can be removed (e.g., etched) using a “pull-back” process to pull the nanostructures810back by a pull-back distance. In an example where the semiconductor layers820include Si, and the semiconductor layers810include SiGe, the pull-back process may include a hydrogen chloride (HCl) gas isotropic etch process, which etches SiGe without attacking Si. As such, the Si layers (nanostructures)820may remain intact during this process. Consequently, recess901can be formed. Further, in various embodiments, the material of the nanostructures810(and the material of at least the lower portion of the dummy gate structure702) have a certain etching selectivity with respect to the connected layer602. For example, the pull-back process may etch the nanostructures810(and at least the lower portion of the dummy gate structure702) more quickly than the connected layer602, which can cause the recess901to present one or more curvature-based profiles at its ends. In various embodiments, the difference of etching rates between the nanostructures810(and the dummy gate structure702) and the connected layer602may be adjusted by varying the molar ratio of Ge in the nanostructures810, when first growing the semiconductor layers410.

For example inFIG. 9B, the nanostructure820may remain intact, while end portions of the dummy gate structure702(along the Y direction) and end portions of the connected layer602(along the Y direction) are etched. Further, as the dummy gate structure702is etched faster than the connected layer602, the recess901can present a first curvature-based profile903(e.g., at each end of a remaining portion of the dummy gate structure702that is about coplanar with one of the nanostructures820). The first curvature-based profile903may include a single arc that inwardly curves toward the remaining dummy gate structure702. As such, the profile903and the sidewall of the nanostructure820(or the connected layer602) extending along the Y direction may form an angle, θ1. In some embodiments, the angle θ1is less than 90 degrees.

For example inFIG. 9C, different from the nanostructure820, the nanostructures810may be concurrently etched, while etching the end portions of the dummy gate structure702(along the Y direction) and the end portions of the connected layer602(along the Y direction). Further, as the dummy gate structure702and nanostructure820are etched faster than the connected layer602, the recess901can present a second curvature-based profile905(e.g., at each end of respective remaining portions of the dummy gate structure702and one of the nanostructures810that are about coplanar with such nanostructure810). The second curvature-based profile905may include multiple arcs that each inwardly curve toward either the remaining dummy gate structure702or the remaining nanostructure810. As such, each arc of the profile905and the sidewall of the nanostructure810(or the connected layer602) extending along the Y direction may form two angles, θ2and θ3. In some embodiments, the angles θ2and θ3are each less than 90 degrees.

FIG. 9Dillustrates another embodiment to form the recess901, in which the connected layer602may remain substantially intact during the pull-back process. As such, the connected layer602may wholly extend the sidewalls of the nanostructure820, when compared to the embodiment ofFIG. 9Bwhere the connected layer602may partially extend the sidewalls of the nanostructure820.FIG. 9Eillustrates yet another embodiment to form the recess901, in which the connected layer602may be etched during the pull-back process but in a slower etching rate, when compared to the embodiment ofFIG. 9B. For example inFIG. 9E, only end portions of the connected layer602(along the Y direction) are partially etched, which causes the connected layer602to present a tapered profile. Specifically, the tapered profile may have a varying thickness, at the portion not exposed by the remaining dummy gate structure702. The thickness can gradually decrease from the portion of the connected layer602at around the end of the remaining dummy gate structure702toward the end of the connected layer602.

Corresponding to operation216ofFIG. 2,FIG. 10Ais a cross-sectional view of the GAA FET device300including an inner spacer1002, at one of the various stages of fabrication. The cross-sectional view ofFIG. 10Ais cut in the lengthwise direction of a fin structure of the GAA FET device300(e.g., cross-section D-D indicated inFIG. 1). Also corresponding to the same operation216,FIGS. 10B and 10Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG. 1), respectively.

The inner spacer1002is formed along respective etched ends of the nanostructures810. Thus, the inner spacer1002(e.g., their respective inner sidewalls) may follow the curvature-based profile (e.g.,903,905) of the recess901. For example inFIG. 10Bwhere the inner spacer1002follows the curvature-based profile903shown inFIG. 9B, a first group of the inner spacer1002can present a first curvature-based profile1003that is similar to the profile903. Each of the first group of the inner spacer1002may be laterally aligned with a corresponding one of the nanostructures820. For example inFIG. 10Cwhere the inner spacer1002follows the curvature-based profile905shown inFIG. 9C, a second group of the inner spacer1002can present a second curvature-based profile1005that is similar to the profile905. Each of the second group of the inner spacer1002may be laterally aligned with a corresponding one of the nanostructures810.

In some embodiments, the inner spacer1002can be formed conformally by chemical vapor deposition (CVD), or by monolayer doping (MLD) of nitride followed by spacer RIE. The inner spacer1002can be deposited using, e.g., a conformal deposition process and subsequent isotropic or anisotropic etch back to remove excess spacer material on the sidewalls of the stacks of the fin structure401and on a surface of the semiconductor substrate302. The inner spacer1002can be formed of silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5) appropriate to the role of forming an insulating gate sidewall spacers of transistors.

FIGS. 10D and 10Eillustrate other embodiments of the profile of the inner spacer1002. As shown inFIG. 10D, the inner spacer1002follows the profile of the recess901, as shown inFIG. 9D. As such, the inner spacer1002may be separated from the nanostructure820with the intact connected layer602. As shown inFIG. 10E, the inner spacer1002follows the profile of the recess901, as shown inFIG. 9E. As such, the inner spacer1002may be separated from the nanostructure820with the tapered connected layer602. Although the sidewalls of the nanostructure820are not exposed by the tapered connected layer602in the illustrated embodiment ofFIG. 10E, it should be understood that portions (e.g., one or more end portions) of the sidewalls of the nanostructure820may be in direct contact with the inner spacer1002, while remaining within the scope of the present disclosure.

Corresponding to operation218ofFIG. 2,FIG. 11Ais a cross-sectional view of the GAA FET device300including an active gate structure1100, at one of the various stages of fabrication. The cross-sectional view ofFIG. 11Ais cut in the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG. 1). Also corresponding to the same operation218,FIGS. 11B and 10Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG. 1), respectively.

Subsequently to forming source/drain structures on the sides of the fin structure401(along the Y direction) and an ILD overlaying the source/drain structures, both of which are not shown for purposes of clarity of illustration, the dummy gate structure702(or at least its lower portion that is formed of the similar material as the nanostructures810), the nanostructures810, and selectively at least a portion of the connected layer602may be concurrently removed. In various embodiments, the dummy gate structure702(or at least its lower portion) and the nanostructures810can be removed by applying a selective etch (e.g., a hydrochloric acid (HCl)), while leaving the nanostructures820substantially intact. After the removal of the dummy gate structure702, a gate trench, exposing respective sidewalls of each of the nanostructures820that face the X direction, may be formed. After the removal of the nanostructures810to further extend the gate trench, respective bottom surface and/or top surface of each of the nanostructures820may be exposed. Consequently, a full circumference of each of the nanostructures820can be exposed. Next, the active gate structure1100is formed to wrap around each of the nanostructures820.

The active gate structure1100is formed in the extended gate trench by filling with at least a gate dielectric and a gate metal. Thus, the active gate structure1100can inherit the dimensions and profiles of the gate trench, which are defined by the formed inner spacer1002, the removed dummy gate structure702, the removed nanostructures810, and selectively the removed portion of the connected layer602.FIG. 11Billustrates an embodiment where the connected layer602is wholly removed, after removing the dummy gate structure702shown inFIG. 10B. As such, each of a number of first gate sections of the active gate structure1100can present a first curvature-based profile1103at its respective ends that extend along the X direction. Each of the first gate sections is laterally aligned with a corresponding one of the nanostructures820. The first curvature-based profile1103can follow the profile1003of the inner spacer1002and further extends toward the nanostructure820through the wholly removed connected layer602. On the other hand, the connected layer602may not remain along the nanostructures810. For example inFIG. 11C, each of a number of second gate sections of the active gate structure1100can present a second curvature-based profile1105at its respective ends that extend along the X direction. Each of the second gate sections is laterally aligned with a corresponding one of the removed nanostructures810. The second curvature-based profile1105can follow the profile1005of the inner spacer1002.

In various embodiments, the active gate structure1100and the inner spacer1002may be characterized with one or more critical dimensions (CDs). For example inFIG. 11B, the active gate structure1100can be characterized with CD4and CD5, which correspond to lengths of the sidewalls of the active gate structure1100extending along the Y direction, respectively; and the inner spacer1002can be characterized with CDdand CDe, which correspond to lengths of the sidewalls of the inner spacer1002extending along the Y direction, respectively. The sidewalls of the active gate structure1100, having CD4and CD5, respectively, are connected to each other through the inwardly curved arc (e.g., profile1103). Accordingly, CD4is greater than CD5. In a non-limiting example, CD4and CD5may each range from about 2 nanometers (nm) to about 300 nm. The sidewalls of the inner spacer1002, having CDdand CDe, respectively, are connected to each other through the inwardly curved arc (e.g., profile1103). Accordingly, CDdis greater than CDe. In a non-limiting example, CDdand CDemay each range from about 0.3 nanometers (nm) to about 15 nm. Further, the profile1103can inherit the profile903(FIG. 9B), and thus, the angle θ1present between the sidewall of the nanostructure820extending along the Y direction and the profile1103can be reserved. In some embodiments, the angle θ1is less than 90 degrees. For example, the angle θ1may range from about 30 degrees to about 88 degrees.

For example inFIG. 11C, the active gate structure1100can be characterized with CD1, CD2, and CD3, which correspond to lengths of different portions of the active gate structure1100extending along the Y direction, respectively; and the inner spacer1002can be characterized with CDa, CDb, and CDc, which correspond to different portions of the inner spacer1002extending along the Y direction, respectively. The portion of the active gate structure1100, having CD1, may be located between respective middle points of the middle arcs on its opposite sides; the portion of the active gate structure1100, having CD2, may be located between junctions of the adjacent arcs on its opposite sides; and the portion of the active gate structure1100, having CD3, may be located between respective end points of the side arcs. In some embodiments, CD2is greater than CD1and CD3is greater than CD1. In a non-limiting example, CD1, CD2and CD3may each range from about 2 nanometers (nm) to about 300 nm. The portion of the active gate structure1100, having CD1, may be located between respective middle points of the middle arcs on its opposite sides; the portion of the active gate structure1100, having CD2, may be located between junctions of the adjacent arcs on its opposite sides; and the portion of the active gate structure1100, having CD3, may be located between respective end points of the side arcs. In some embodiments, CD2is greater than CD1and CD3is greater than CD1. In a non-limiting example, CD1, CD2, and CD3may each range from about 2 nanometers (nm) to about 300 nm. The portion of the inner spacer1002, having CDc, may be extended from the middle point of the middle arc; the portion of the inner spacer1002, having CDb, may be extended from the junction of the adjacent arcs; and the portion of the inner spacer1002, having CDa, may be extended from the end point of the side arc. In some embodiments, CDais greater than CDband CDcis greater than CDb. In a non-limiting example, CDa, CDb, and CDcmay each range from about 0.3 nanometers (nm) to about 15 nm. Further, the profile1105can inherit the profile905(FIG. 9C), and thus, the angles θ2and θ3can be reserved. In some embodiments, the angles θ2and θ3are each less than 90 degrees. For example, the angles θ2and θ3may each range from about 30 degrees to about 88 degrees.

The active gate structure1100includes a gate dielectric and a gate metal, in some embodiments. The gate dielectric can wrap around each of the nanostructures820, e.g., the top and bottom surfaces and sidewalls facing the X direction). The gate dielectric may be formed of different high-k dielectric materials or a similar high-k dielectric material. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may include a stack of multiple high-k dielectric materials. The gate dielectric can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the gate dielectric may optionally include a substantially thin oxide (e.g., SiOx) layer, which may be a native oxide layer formed on the surface of each of the nanostructures820.

The gate metal can wrap around each of the nanostructures820with the gate dielectric disposed therebetween. Specifically, the gate metal can include a number of gate metal sections abutted to each other along the Z direction. Each of the gate metal sections can extend not only along a horizontal plane (e.g., the plane expanded by the X direction and the Y direction), but also along a vertical direction (e.g., the Z direction). As such, two adjacent ones of the gate metal sections can adjoin together to wrap around a corresponding one of the nanostructures820, with the gate dielectric disposed therebetween.

The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multi-layers thereof, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals that may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.

FIGS. 11D-Killustrate various other embodiments where the connected layer602is partially removed from or remains substantially intact along the sidewalls of the nanostructures820, after forming the active gate structure1100. For example inFIG. 11D, the whole remaining portion of the connected layer602that is not exposed by the remaining dummy gate structure702(when forming the recess901inFIG. 9B), may remain. InFIG. 11E, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and the active gate structure1100, and the tapered portions on the same side of the nanostructure820are tapered toward e

ach other. InFIG. 11F, one or more non-tapered portions of the connected layer602may remain. Specifically, each of such non-tapered portions is disposed between the nanostructure820and the inner spacer1002. InFIG. 11G, the whole connected layer602may remain. InFIG. 11H, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and combination of a portion of the active gate structure1100and the inner spacer1002. The tapered portions on the same side of the nanostructure820are tapered toward each other. InFIG. 11I, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and the inner spacer1002, and the tapered portions on the same side of the nanostructure820are tapered away from each other. InFIG. 11J, the whole connected layer602may remain. Different form the embodiment ofFIG. 11G, the connected layer602may present a tapered profile toward its both ends. InFIG. 11K, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and combination of a portion of the active gate structure1100and the inner spacer1002. Each of the tapered portions has its ends tapered away from each other.

In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction. The gate structure comprises a plurality of first gate sections and a plurality of second gate sections. The plurality of first gate sections are laterally aligned with the plurality of semiconductor layers, respectively. The plurality of second gate sections are each vertically disposed between adjacent ones of the plurality of semiconductor layers. The semiconductor device includes an inner spacer comprising a first group and a second group. Each of the first group of the inner spacer contacts an end of a corresponding one of the plurality of first gate sections in a first curvature-based profile, and each of the second group of the inner spacer contacts an end of a corresponding one of the plurality of second gate sections in a second curvature-based profile.

In yet another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a fin structure extending along a first lateral direction. The fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another. The method includes forming a connected layer overlaying the fin structure. The method includes forming a dummy gate structure over a portion of the fin structure with the connected layer disposed between the dummy gate structure and the fin structure. The dummy gate structure extends along a second lateral direction perpendicular to the first lateral direction. The method includes removing portions of the fin structure that are not overlaid by the dummy gate structure. The method includes etching, along the first lateral direction, respective end portions of each of the first semiconductor layers, respective end portions of at least lower portions of the dummy gate structure, and end portions of the connected layer. A respective remaining portion of each of the first semiconductor layers and a respective remaining portion of each of the lower portions of the dummy gate structure each present a curvature-based profile. The method includes forming inner spacers that fill the etched end portions of the first semiconductor layers and the etched end portions of the dummy gate structure. The method includes replacing respective remaining portions of the first semiconductor layers and the dummy gate structure with an active gate structure.