Blocks and bits sequence reversing device using barrel shift

A bit sequence reversing device for reversing a sequence of data having a plurality of blocks, each block having a predetermined number of bits. The bit sequence reversing device includes a block reversing unit for reversing a sequence of at least two of the blocks; and a plurality of bit reversing units, each corresponding to one of the blocks, each of the bit reversing units reversing a sequence of the bits in the corresponding block. The block reversing unit includes a barrel shift unit. The barrel shift unit includes first and second input latch circuits for receiving the data; a series of left shift registers, connected to the first input circuit, for shifting the output of the first input latch circuit on the left direction, a series of right shift registers, connected to the second input circuit, for shifting the output of the second input latch circuit on the right direction; a first output control circuit, connected to a post-stage of one of the left shift registers, for selectively outputting data thereof; and a second output control circuit, connected to a post-stage of one of the right shift registers, for selectively outputting data thereof. The bit sequence reversing device reduces execution time without increasing the structural elements thereof, and since the reversing operation of blocks is adjusted, various types of reversing operations are possible.

BACKGROUND OF THE INVENTION 
1) Field of the Invention 
The present invention relates to a bit sequence reversing device for 
reversing a sequence of data having a plurality of blocks, each of which 
has a predetermined number of bits. 
2) Description of the Related Art 
In a microcomputer system having a plurality of large scale integrated 
circuits (LSI's), there is usually a difference between the data formats 
(i.e., the data pins) thereof. For example, a 32-bit microprocessor (MPU) 
has data pins D.sub.0, D.sub.1, . . . , and D.sub.31 which have the 
following weights: 
##EQU1## 
In this case, the data pin D.sub.0 represents a least significant bit 
(LSB) and the data pin D.sub.31 represents a most significant bit (MSB). 
Conversely, a peripheral circuit such as a 32-bit memory control unit 
(MCU) has data pins D.sub.0 ', D.sub.1 ', . . . and D.sub.31 ' which have 
the following weights: 
##EQU2## 
In this case, the data pin D.sub.0 ' represents an MSB, and D.sub.31 ' 
represents an LSB. Therefore, when data of the MCU is fetched by the MPU, 
the MPU has to reverse the bit sequence of the fetched data to conform to 
the data format of the MPU. This reversion is called "endian conversion". 
In the prior art, the above-mentioned reversion of a bit sequence is 
carried out by pure software in the MPU. According to this software, it is 
possible to reverse not only all the bits of data (i.e., one word), but 
also a required half word (16 bits) or a required byte (8 bits). However, 
this requires a large number of programming steps which invites a long 
execution time. 
In order to reduce such a long execution time, hardware for reversing all 
the 32-bits of data may be provided in the MPU. In this case, however, it 
is impossible to adapt the hardware to reverse a half word (16 bits) or a 
byte (8 bits). 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a bit sequence 
reversing device which has a short execution time and can be easily 
modified to carry out various types of reversing operations such as a 
one-word reversing operation, a half-word reversing operation, and a 
one-byte reversing operation. 
According to the present invention, in a bit sequence reversing device for 
reversing a sequence of data having a plurality of blocks, each having a 
predetermined number of bits, at least two of the blocks are reversed by a 
block reversing unit, and all the bits of each block are then reversed by 
a plurality of bit reversing units. 
In the present invention, since a bit sequence operation is carried out 
mainly by hardware, an execution time for a reversing operation can be 
reduced. Also, since the reversion of any blocks can be voluntarily 
carried out, various types of reversing operations can be easily carried 
out.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
In FIG. 1, which illustrates a general microcomputer system, reference 
numeral 102 designates a 32-bit microprocessor (MPU), and 102 designates a 
32-bit memory control unit (MCU). Note that other peripheral circuits are 
of course present, but the illustration thereof is omitted. The MPU 101 
has data pins D.sub.0, D.sub.1, . . . , and D.sub.31 which have the 
following weights: 
##EQU3## 
Also, the MCU 102 has data pins D.sub.0 ', D.sub.1 ', . . . , and D.sub.31 
' which have the following weights: 
##EQU4## 
Therefore, when data of the MCU 102 is fetched by the MPU 101, the MPU 101 
has to carry out a bit reversing operation as illustrated in FIGS. 2A, 2B, 
and 2C. 
For example, if all of the 32 bits (one word) are required in the MPU 101, 
the MPU 101 carries out a bit reversing operation as illustrated in FIG. 
2A. That is, all of the blocks A, B, C, and D, each of which includes 8 
bit data, are reversed, and also the bit sequences of the blocks A, B, C, 
and D are reversed. 
If only 16 bits (half word) are required in the MPU 101, the MPU 101 
carries out a bit reversing operation as illustrated in FIG. 2B. That is, 
the blocks C and D are reversed, and also the bit sequences of the blocks 
C and D are reversed. 
If only 8 bits (one byte) are required in the MPU 101, the MPU 101 carries 
out a bit reversing operation as illustrated in FIG. 2C. That is, only the 
bit sequence of the block D is reversed. 
The above-mentioned three types of reversing operations are carried out in 
the MPU 101 as illustrated in FIG. 3 which includes an embodiment of the 
bit sequence reversing device according to the present invention. In FIG. 
3, reference numeral 1 designates an external input/output interface with 
peripheral circuits such as the MCU 102 and 2 designates an instruction 
decoder for decoding an instruction on a data bus SD which is also 
connected to the external input/output interface 1. Upon receipt of 
instructions from the instruction decoder 1, a microprogram control 
circuit 3 generates various control signals such as CS1.sub.in, C0 to C11, 
C0' to C11', PRE, CS2.sub.in, CS.sub.out, and the like, which are supplied 
to various units within the MPU 101. 
Also, reference numeral 4 designates a register file including various 
registers, 5 a barrel shift unit, 6 a bit reversing unit, 7 an 
arithmetic-logic unit (ALU), and 8 a clock generator for generating 
various clock signals such as CLK to synchronize the operation of the 
units within the MPU 101. 
Further, reference numeral 9 designates a precharging transistor formed by 
a depletion type transistor for precharging a data bus RD. In this case, 
since the data bus RD is a 32-bit bus, 32 of the precharging transistors 
are required, but only one transistor is illustrated for simplification. 
The bit sequence reversing device according to the present invention is 
constituted by the barrel shift unit 5 which serves as a block reversing 
circuit and the bit reversing unit 6. 
The barrel shift unit 5 of FIG. 3 is explained with reference to FIG. 4. 
That is, the barrel shift unit 5 includes an input latch circuit 51 for 
receiving 32-bit data from the data bus SD, a 16-bit left shift register 
52 for shifting the output data of the input latch circuit 51 in the left 
direction by 16 bits (i.e., two blocks), an 8-bit left shift register 53 
for shifting the output data of the 16-bit left shift register 52 in the 
left direction by 8 bits (i.e., one block), and a left output control 
circuit 54 for outputting the output data of the 8-bit left shift register 
53 to the data bus RD. Also, the barrel shift unit 5 includes an input 
latch circuit 51' for receiving 32-bit data from the data bus SD, an 8-bit 
right shift register 52' for shifting the output data of the input latch 
circuit 51' in the right direction by 8 bits (i.e., one block), a 16-bit 
right shift register 53' for shifting the output data of the 8-bit right 
shift register 52 in the right direction by 16 bits (i.e., two blocks), 
and a right output control circuit 54' for outputting the output data of 
the 16-bit right shift register 53' to the data bus RD. 
The elements 54 to 57 and 51' to 54' of the barrel shift unit 5 are 
explained with reference to FIGS. 5 through 11. 
In FIG. 5A and 5B which are a detailed circuit diagram of the input latch 
circuits 51 and 51' of FIG. 4, the circuits 51 and 51' are simultaneously 
enabled by an output of a combination of an AND circuit G.sub.1 and an 
inverter I.sub.1 when both of the control signal CS1.sub.in and the clock 
signal CLK are high. The input latch circuit 51 includes thirty-two 
latches LA.sub.0 through LA.sub.31 each of which is formed by an inverter 
I.sub.2, a clocked-inverter G.sub.2, and inverters I.sub.3 and I.sub.4. 
Similarly, the input latch circuit 51' includes thirty-two latches 
LA.sub.0 ' through LA.sub.31 ' each of which is formed by an inverter 
I.sub.2 ', clocked-inverter G.sub.2 ', and inverters I.sub.3 ' and I.sub.4 
'. Thus, the input latch circuit 51 latches four left block data LBK.sub.0 
to LBK.sub.3 from the data bus SD, and the input latch circuit 51' latches 
four right block data RBK.sub.0 to RBK.sub.3 from the data bus SD. In this 
case, each of the block data is 8-bit data, and the left block data 
LBK.sub.0 to LBK.sub.3 are the same as the right block data RBK.sub.0 to 
RBK.sub.3, respectively. 
In FIG. 6, which is a detailed circuit diagram of the 16-bit left shift 
unit 52 of FIG. 4, inputs IN.sub.0, IN.sub.1, . . . , and IN.sub.7, i.e., 
the left block LBK.sub.0 of the input latch circuit 51 and inputs 
IN.sub.16, IN.sub.17, . . . , and IN.sub.23, i.e., the left block 
LBK.sub.2 of the input latch circuit 51 are connected by switches SW.sub.0 
to outputs OUT.sub.0, OUT.sub.1, . . . , and OUT.sub.7, respectively, 
which form a left block LBK.sub.0 '. Similarly, inputs IN.sub.8, IN.sub.9, 
. . . , and IN.sub.15, i.e., the left block LBK.sub.1 of the input latch 
circuit 51 and inputs IN.sub.24, IN.sub.25, . . . , and IN.sub.31, i.e., 
the left block LBK.sub.3 of the input latch circuit 51 are connected by 
switches SW.sub.1 to outputs OUT.sub.8, OUT.sub.9, . . . , and OUT.sub.15, 
respectively, which form a left block LBK.sub. 1 '. Also, inputs 
IN.sub.16, IN.sub.17, . . . , and IN.sub.23, i.e., the left block 
LBK.sub.2 of the input latch circuit 51 and the ground terminal are 
connected by switches SW.sub.3 to outputs OUT.sub.16, OUT.sub.17, . . . , 
and OUT.sub.18, respectively, which form a left block LBK.sub.2 '. 
Similarly, inputs IN.sub.24, IN.sub.25, . . . , and IN.sub.31, i.e., the 
left block LBK.sub.3 of the input latch circuit 51 and the ground terminal 
are connected by switches SW.sub.3 to outputs OUT.sub.24, OUT.sub.25, . . 
. , and OUT.sub.31, respectively, which form a left block LBK.sub.3 '. 
The switches SW0 to SW3, each of which is formed by two enhancement-type 
transistors Q.sub.1 and Q.sub.2, are controlled by the control signal C0 
to C3, respectively, supplied from the microprogram control circuit 3. 
That is, when the control signal Ci (i=0-3) is low, the left block 
LBK.sub.i (i=0-3) becomes the left block LBK.sub.i (i=0-3), i.e., no left 
shift operation is carried out. Conversely, when the control signal C0 or 
C1 is high, the left block LBK.sub.2 or LBK.sub.3 becomes the left block 
LBK.sub.0 ' or LBK.sub.1 ', i.e., a 16-bit left shift operation is carried 
out. Also, when the control signal C2 or C3 is high, the left block 
LBK.sub.2 ' or LBK.sub.3 ' is grounded. 
In FIG. 7, which is a detailed circuit diagram of the 8-bit left shift unit 
53 of FIG. 4, inputs IN.sub.0, IN.sub.1, . . . , and IN.sub.7, i.e., the 
left block LBK.sub.0 ' of the 16-bit left shift unit 52 and inputs 
IN.sub.8, IN.sub.9, . . . , and IN.sub.15, i.e., the left block LBK.sub.1 
' of the 16-bit left shift unit 52 are connected by switches SW4 to 
outputs OUT.sub.0, OUT.sub.1, . . . , and OUT.sub.7, respectively, which 
form a left block LBK.sub.0 ". Similarly, inputs IN.sub.8, IN.sub.9, . . . 
, and IN.sub.15, i.e., the left block LBK.sub.1 ' of the 16-bit left shift 
unit 52 and inputs IN.sub.16, IN.sub.17, . . . , and IN.sub.23, i.e., the 
left block LBK.sub.2 ' of the 16-bit left shift unit 52 are connected by 
switches SW5 to outputs OUT.sub.8, OUT.sub.9, . . . , and OUT.sub.10, 
respectively, which form a left block LBK.sub.1 ". Similarly, inputs 
IN.sub.17, IN.sub.18, . . . , and IN.sub.23, i.e., the left block 
LBK.sub.2 ' of the 16-bit left shift unit 52 and inputs IN.sub.24, 
IN.sub.25, . . . , and IN.sub.31, i.e., the left block LBK.sub.3 ' of the 
16-bit left shift unit 52 are connected by switches SW6 to outputs 
OUT.sub.16, OUT.sub.17, . . . , and OUT.sub.23, respectively, which form a 
left block LBK.sub.2 ". Also, inputs IN.sub.24, IN.sub.25, . . . , and 
IN.sub.31, i.e., the left block LBK.sub.3 of the 16-bit left shift unit 52 
and the ground terminal are connected by switches SW7 to outputs 
OUT.sub.24, OUT.sub.25, . . . , and OUT.sub.31, respectively, which form a 
left block LBK.sub.3 '. 
The switches SW4 to SW7, each of which is also formed by two 
enhancement-type transistors Q.sub.1 and Q.sub.2, are controlled by the 
control signal C4 to C7, respectively, supplied from the microprogram 
control circuit 3. 
That is, when the control signal Ci (i=4-7) is low, the left block 
LBK.sub.i (i=4-7) becomes the left block LBK.sub.i " (i=4-7), i.e., no 
left shift operation is carried out. Conversely, when the control signal 
C4, C5, or C6 is high, the left block LBK.sub.1 ', LBK.sub.2 ' or 
LBK.sub.3 ' becomes the left block LBK.sub.0 ", LBK.sub.1 " or LBK.sub.2 
", i.e., an 8-bit left shift operation is carried out. Also, when the 
control signal C7 is high, the left block LBK.sub.3 " is grounded. 
In FIG. 8, which is a detailed circuit diagram of the left output control 
circuit 54 of FIG. 4, a NOR circuit G.sub.8 and an enhancement type 
transistor Q.sub.8 are connected between each bit of the left block 
LBK.sub.0 " of the 8-bit left shift unit 53 and a corresponding bit of the 
data bus RD; a NOR circuit G.sub.9 and an enhancement-type transistor 
Q.sub.9 are connected between each bit of the left block LBK.sub.1 " of 
the 8-bit left shift unit 53 and a corresponding bit of the data bus RD; a 
NOR circuit G.sub.10 and an enhancement-type transistor Q.sub.10 are 
connected between each bit of the left block LBK.sub.2 " of the 8-bit left 
shift unit 53 and a corresponding bit of the data bus RD; and a NOR 
circuit G.sub.10 and an enhancement-type transistor Q.sub.10 are connected 
between each bit of the left block LBK.sub.3 " of the 8-bit left shift 
unit 53 and a corresponding bit of the data bus RD. 
The NOR circuits G.sub.8, G.sub.9, G.sub.10, and G.sub.11 are controlled by 
the control signals C8, C9, C10, and C11, respectively. 
That is, when the control signal Ci (i=8-11) is low, the NOR circuits Gi 
(i=8-11) generate low potential signals, so that the transistors Qi 
(i=8-11) are in a high-impedance state. Conversely, when the control 
signal Ci (i=8-11) is high, the NOR circuits Gi (i=8-11) generate inverted 
signals of the left block LBK.sub.i (i=8-11), so that the transistors Qi 
(i=8-11) generate data of the left block LBK.sub.i (i=8-11) and transmit 
them to the corresponding bits of the data bus RD. 
In FIG. 9, which is a detailed circuit diagram of the 8-bit right shift 
unit 52' of FIG. 4, inputs IN.sub.0, IN.sub.2, . . . , and IN.sub.7, i.e., 
the right block RBK.sub.0 of the input latch circuit 51' and the ground 
terminal connected by switches SW0' to outputs OUT.sub.0, OUT.sub.1, . . . 
, and OUT.sub.7, respectively, which form a right block RBK.sub.0 '. Also, 
inputs IN.sub.8, IN.sub.9, . . . , and IN.sub.15, i.e., the right block 
RBK.sub.1 of the input latch circuit 51' and inputs IN.sub.0, IN.sub.1, . 
. . , and IN.sub.7, i.e., the right block RBK.sub.0 of the input latch 
circuit 51' are connected by switches SW1' to outputs OUT.sub.8, 
OUT.sub.9, . . . , and OUT.sub.15, respectively, which form a right block 
RBK.sub.1 '. Similarly, inputs IN.sub.16, IN.sub.17, . . . , and 
IN.sub.23, i.e., the right block RBK.sub.2 of the input latch circuit 51' 
and inputs IN.sub.8, IN.sub.9, . . . , and IN.sub.15, i.e., the right 
block RBK.sub.1 of the input latch circuit 51' are connected by switches 
SW2' to outputs OUT.sub.16, OUT.sub.17, . . . , and OUT.sub.23, 
respectively, which form a right block RBK.sub.2. Similarly, inputs 
IN.sub.24, IN.sub.25, . . . , and IN.sub.31, i.e., the right block 
RBK.sub.2 of the input latch circuit 51' and inputs IN.sub.16, IN.sub.17, 
. . . , and IN.sub.23, i.e., the right block RBK.sub.2 of the input latch 
circuit 51' are connected by switches SW3' to outputs OUT.sub.24, 
OUT.sub.25, . . . , and OUT.sub.31, respectively, which form a right block 
RBK.sub.3 '. 
The switches SW0' to SW1' each of which is also formed by two 
enhancement-type transistors Q.sub.1 and Q.sub.2, are controlled by the 
control signal C0' to C3', respectively, supplied from the microprogram 
control circuit 3. 
That is, when the control signal C0' is high, the right block RBK.sub.3 ' 
is grounded. Also, when the control signal Ci' (i=0-3) is low, the right 
block RBK.sub.i (i=0-3) becomes the right block RBK.sub.i, (i=0-3), i.e., 
no right shift operation is carried out. Conversely, when the control 
signal C0', C1', or C2' is high, the right block RBK.sub.1, RBK.sub.2 or 
RBK.sub.3 becomes the right block RBK.sub.0, RBK.sub.1 ' or RBK.sub.2 ', 
i.e., an 8-bit right shift operation is carried out. 
In FIG. 10, which is a detailed circuit diagram of the 16-bit right shift 
unit 53' of FIG. 4, inputs IN.sub.0, IN.sub.1, . . . , and IN.sub.7, i.e., 
the right block RBK.sub.0 ' of the 8-bit right shift unit 52' and the 
ground terminal are connected by switches SW4' to outputs OUT.sub.0 ', 
OUT.sub.1, . . . , and OUT.sub.7 ', respectively, which form a right block 
RBK.sub.0 ". Similarly, inputs IN.sub.8, IN.sub.9, . . . , and IN.sub.15, 
i.e., the right block RBK.sub.1 ' of the 8-bit right shift unit 52' and 
the ground terminal are connected by switches SW5' to outputs OUT.sub.8 ', 
OUT.sub.9 ', . . . , and OUT.sub.15 ', respectively, which form a right 
block RBK.sub.1 ". Similarly, inputs IN.sub.16, IN.sub.17, . . . , and 
IN.sub.23, i.e., the right block RBK.sub.2 ' of the 8-bit left shift unit 
52' and inputs IN.sub.0, IN.sub.1, . . . , and IN.sub.7, i.e., the right 
block RBK.sub.0 ' of the 8-bit right shift unit 52' are connected by 
switches SW6' to outputs OUT.sub.16 ', OUT.sub.17 ', . . . , and 
OUT.sub.23 ', respectively, which form a right block RBK.sub.2 ". 
Similarly, inputs IN.sub.24, IN.sub.25, . . . , and IN.sub.31, i.e., the 
right block RBK3' of the 8-bit right shift unit 52' and inputs IN.sub.8, 
IN.sub.9, . . . , and IN.sub.15, i.e., the right block RBK' of the 8-bit 
right shift unit 52' are connected by switches SW7' to outputs OUT.sub.24 
', OUT.sub.25 ', . . . , and OUT.sub.31 ', respectively, which form a 
right block RBK.sub.3 ". 
The switches SW4' to SW7' each of which is formed by two enhancement-type 
transistors Q.sub.1 and Q.sub.2, are controlled by the control signal C4' 
to C7', respectively, supplied from the microprogram control circuit 3. 
That is, when the control signal Ci' (i=4-7) is low, the right block 
RBK.sub.i ' (i=4-7) becomes the right block RBK.sub.i " (i=4-7), i.e., no 
left shift operation is carried out. Conversely, when the control signal 
C4' or C5' the right block RBK.sub.0 " or RBK.sub.1 " is grounded. Also, 
when the control signal C6' or C7' is high, the right block RBK.sub.2 ' or 
RBK.sub.3 ' becomes the right block RBK.sub.0 " or RBK.sub.1 ", i.e., a 
16-bit right shift operation is carried out. 
In FIG. 11, which is a detailed circuit diagram of the right output control 
circuit 54' of FIG. 4, a NOR circuit G.sub.8 ' and an enhancement-type 
transistor Q.sub.8 ' are connected between each bit of the right block 
RBK.sub.0 " of the 16-bit right shift unit 53' and a corresponding bit of 
the data bus RD; a NOR circuit G.sub.9 ' and an enhancement-type 
transistor Q.sub.9 ' are connected between each bit of the right block 
RBK.sub.1 " of the 16-bit right shift unit 53 and a corresponding bit of 
the data bus RD; a NOR circuit G.sub.10 ' and an enhancement-type 
transistor Q.sub.10 ' are connected between each bit of the right block 
RBK.sub.2 " of the 16-bit right shift unit 53' and a corresponding bit of 
the data bus RD; and a NOR circuit G.sub.10 ' and an enhancement-type 
transistor Q.sub.10 ' are connected between each bit of the right block 
RBK.sub.3 " of the 16-bit right shift unit 53' and a corresponding bit of 
the data bus RD. 
The NOR circuits G.sub.8 ', G.sub.9 ', G.sub.10 ', and G.sub.11 ' are 
controlled by the control signals C8', C9', C10', and C11', respectively. 
That is, when the control signal Ci' (i=8-11) is low, the NOR circuits Gi 
(i=8-11) generate low potential signals, so that the transistors Qi, 
(i=8-11) are in a high-impedance state. Conversely, when the control 
signal Ci, (i=8-11) is high, the NOR circuits Gi' (i=8-11) generate 
inverted signals of the right block RBK.sub.i (i=8-11), so that the 
transistors Qi' (i=8-11) generate data of the right block RBK.sub.i 
(i=8-11) and transmit them to the corresponding bits of the data bus RD. 
The operation of the barrel shift unit 5 of FIG. 4 will be explained with 
reference to FIGS. 12A through 12H. 
That is, when the clock signal CLK is generated from the clock generator 8 
(FIG. 3) as shown in FIG. 12A and the control signal CS1.sub.in is 
generated from the microprogram control circuit 3 (FIG. 3) as shown in 
FIG. 12B, the input latch circuits 51 and 51' are simultaneously enabled 
at time t.sub.1 as shown in FIG. 12C, so that the input latch circuits 51 
and 51' latch the same data from the data bus SD. On the other hand, the 
precharging signal PRE is made low as shown in FIG. 12D, and all the bits 
of the data bus RD are precharged at V.sub.cc. Then, at time t.sub.2, when 
the microprogram control circuit 3 generates the control signals C0 to C3 
and C0' to C3' as shown in FIG. 12E, the 16-bit left shift unit 52 and the 
8-bit right shift unit 52' are operated. After that, at time t.sub.3, when 
the microprogram control circuit 3 generates the control signals C4 to C7 
and C4' to C7' as shown in FIG. 12F, the 8-bit left same shift unit 53 and 
the 16-bit right shift unit 53, are operated. Further, at time t.sub.4, 
when the microprogram control same circuit 3 generates the control signals 
C8 to C11 and C8' to C11' as shown in FIG. 12G, the left output control 
circuit 54 and the right output control circuit 54' are operated. As a 
result, an OR logic between the outputs of the left output control circuit 
54 and the right output control circuit 54' is obtained at the data bus RD 
as shown in FIG. 12H. Note that the precharging signal PRE is made high to 
put the data bus RD in a floating state before the determination of the 
control signals C8 to C11 (C8' to C11'). 
Thus, according to the left output control circuit 54 and the right output 
control circuit 54, the data RD.sub.j of the j-th bit of the data bus RD 
is defined by 
EQU RD.sub.j =(LB.sub.j .multidot.C.sub.j)U(RB.sub.j .multidot.C.sub.j ') 
where LB.sub.j is the j-th bit of the left output control circuit 54; 
C.sub.j is one of the control signals C8 to C11 applied to the j-th bit NOR 
circuit of the left output control circuit 54; 
RB.sub.j is the j-th bit of the right output control circuit 54'; and 
C.sub.j is one of the control signals C8' to C11' applied to the j-th bit 
NOR circuit of the right output control circuit 54'. 
The control signals C0 to C11 (C0' to C11') are changed in accordance with 
the conversion of one word as shown in FIG. 2A, the conversion of a half 
word as shown in FIG. 2B, and the conversion of a byte as shown in FIG. 
2C. 
For example, in order to reverse the sequence of blocks for the conversion 
of one word as shown in FIG. 2A, the control signals C0 to C11 (C0' to 
C11') are given as shown in FIGS. 13A through 13E. That is, the sequence 
of blocks A, B, C, and D are latched in the input latch circuits 51 and 
51' as shown in FIG. 13A. First, when "1", "1", "0", and "0" are given as 
the control signals C0, C1, C2, and C3, respectively, the 16-bit left 
shift unit 52 generates the sequence of blocks C, D, C, and D, as shown in 
FIG. 13B. Also, when "1", "1", "1", and "1" are given as the control 
signals C0', C1', C2', and C3', respectively, the 8-bit right shift unit 
52' generates the sequence of blocks 0 (all bits are zero), A, B, and C, 
as shown in FIG. 13B. Second, when "1", "1", "1", and "1" are given as the 
control signals C4, C5, C6, and C7, respectively, the 8-bit left shift 
unit 53 generates the sequence of blocks D, C, D, and O, as shown in FIG. 
13C. Also, when "1", "1", "0", and "1" are given as the control signals 
C4', C5', C6', and C7', respectively, the 16-bit right shift unit 53, 
generates the sequence of blocks O, O, B, and A as shown in FIG. 13C. 
Third, when "1", "1", "0", and "1" are given as the control signals C8, 
C9, C10, and C11, respectively, the left output control circuit 54 
generates the sequence of blocks D, C, O, and O, as shown in FIG. 13D. 
Also, when "1", "1", "1", and "1" are given as the control signals C8', 
C9', C10', and C11', respectively, the right control circuit 54' generates 
the sequence of blocks O, O, B, and A as shown in FIG. 13D. As a result, 
the sequence of blocks D, C, B, and A is obtained at the data bus SD as 
shown in FIG. 13E. 
Also, in order to reverse the sequence of blocks for the conversion of a 
half word as shown in FIG. 2B, the control signals C0 to C11 (C0' to C11') 
are also given as shown in FIGS. 14A through 14E. That is, the sequence of 
blocks A, B, C, and D are latched in the input latch circuits 51 and 51' 
as shown in FIG. 14A. First, when "0", "0", "0", and "0" are given as the 
control signals C0, C1, C2, and C3, respectively, the 16-bit left shift 
unit 52 generates the sequence of blocks A, B, C and D, as shown in FIG. 
14B. Also, when "1", "1", "1", and "1" are given as the control signals 
C0', C1', C2' and C3', the 8-bit right shift unit 52' generates the 
sequence of blocks 0 (all bits are zero), A, B, and C, as shown in FIG. 
14B. Second, when "0", "0", "1", and "1" are given as the control signals 
C4, C5, C6, and C7, respectively, the 8-bit left shift unit 53 generates 
the sequence of blocks A, B, D, and O, as shown in FIG. 14C. Also, when 
"0", "0", "0", and "0" are given as the control signals C4', C5', C6', and 
C7', respectively, the 16-bit right shift unit 53' generates the sequence 
of blocks O, A, O, and C, as shown in FIG. 14C. Third, when "0", "0", "1", 
and "1" are given as the control signals C8, C9, C10, and C11, 
respectively, the left output control circuit 54 generates the sequence of 
blocks A, B, D, and O, as shown in FIG. 14D. Also, when "0", "0", "1", and 
"1" are given as the control signals C8', C9', C10', and C11', 
respectively, the right control circuit 54' generates the sequence of 
blocks O, A, O, and C, as shown in FIG. 14D. As a result, the sequence of 
blocks A, B, D, and C is obtained at the data bus SD as shown in FIG. 14E. 
Further, in order to reverse the sequence of blocks for the conversion of a 
byte as shown in FIG. 2C, the control signals C0 to C11 (C0' to C11') are 
also given as shown in FIGS. 15A through 15E. That is, the sequence of 
blocks A, B, C, and D are latched in the input latch circuits 51 and 51' 
as shown in FIG. 15A. First, when "0", "0", "0", and "0" are given as the 
control signals C0, C1, C2, and C3, respectively, the 16-bit left shift 
unit 52 generates the sequence of blocks A, B, C, and D, as shown in FIG. 
15B. Also, when "1", "1", "1", and "1" are given as the control signals 
C0', C1', C2', and C3', the 8-bit right shift unit 52' generates the 
sequence of blocks O, A, B, and C, as shown in FIG. 15B. Second, when "1", 
"1", "1", and "1" are given as the control signals C4, C5, C6, and C7, 
respectively, the 8-bit left shift unit 53 generates the sequence of 
blocks A, B, C, and D, as shown in FIG. 15C. Also, when "0", "0", "1", and 
"0" are given as the control signals C4', C5', C6', and C7', respectively, 
the 16-bit right shift unit 53, generates the sequence of blocks O, A, O, 
and O, as shown in FIG. 15C. Third, when "1", "1", "1", and "1" are given 
as the control signals C8, C9, C10, and C11, respectively, the left output 
control circuit 54 generates the sequence of blocks A, B, C, and D, as 
shown in FIG. 15D. Also, when "0", "0", "0", and "0" are given as the 
control signals C8', C9', C10', and C11', respectively, the right control 
circuit 54' generates the sequence of blocks O, A, O, and O, as shown in 
FIG. 15D. As a result, the sequence of blocks A, B, C, and D is obtained 
at the data bus SD as shown in FIG. 15E. 
Note that the control signals C0 to C11 (C0' to C11') are not limited to 
the values as shown in FIGS. 13A through 13E, 14A through 14E, and 15A 
through 15E. 
In FIG. 16, which is a detailed block circuit diagram of the bit reversing 
unit 6 of FIG. 3, the bit reversing unit 6 includes four bit reversing 
circuits 60, 61, 62, and 63 which are simultaneously operated in response 
to the control signal CS2.sub.in and CS.sub.out, and the clock signal CLK. 
The reversed blocks of data from the barrel shift unit 5 are supplied to 
the bit reversing circuits 60, 61, 62, and 63, each of which reverses the 
sequence of 8 bits within one block. 
In FIG. 17, which is a detailed circuit diagram of the bit reversing 
circuit such as 60 of FIG. 16, the bit reversing circuit 60 includes eight 
latches LA.sub.100, LA.sub.101, . . . , and LA.sub.107 which have the same 
configuration as the latches of FIG. 5, and eight output circuits each of 
which has an NOR circuit such as G.sub.100 and an enhancement-type 
transistor such as Q.sub.100. Crossed-connections are provided between the 
eight latches and the output control circuits, so that the latches 
LA.sub.100, LA.sub.101, . . . , and LA.sub.107 are connected to the output 
control circuits (G.sub.107, Q.sub.107), (G.sub.106, Q.sub.106), . . . , 
(G.sub.100, Q.sub.100), respectively. 
The operation of the bit reversing circuit 60 of FIG. 17 is explained with 
reference to FIGS. 18A through 18E. That is, when the clock signal CLK is 
supplied from the clock generator 8 (FIG. 3) as shown in FIG. 18A and the 
clock signal CS2.sub.in is supplied from the microprogram control circuit 
3 as shown in FIG. 18B, the non-reversed data of one block on the data bus 
RD which is already block-reversed by the barrel shift unit 5 is latched 
by the latches LA.sub.100, LA.sub.101, . . . , and LA.sub.107, as shown in 
FIGS. 18C and 18D. Thereafter, when the clock signal CS.sub.out is 
supplied from the microprogram control circuit 3 as shown in FIG. 18E, the 
output control circuits (G.sub.100, Q.sub.100), (G.sub.101, Q.sub.101), . 
. . , and (G.sub.107, Q.sub.107) generate reversed bits of data and 
transmit them to the data bus RD. 
Thus, the reversing operation of bits is carried out simultaneously within 
each block. 
Note that, if the reversing operation of bits is directly carried out 
without providing the reversing means of blocks such as the barrel shift 
register, the above-mentioned crossed-connections are very complex, which 
remarkably increases the area they occupy. 
As explained above, according to the present invention, since the 
conversion of bits is carried out by two-stepped configurations, i.e., a 
block reversing configuration and a bit reversing configuration, the 
execution time can be reduced without increasing the hardware. Also, since 
the reversing operation of blocks is adjusted, various types of reversing 
operations such as a one-word reversing operation, a half-word reversing 
operation, a byte reversing operation and the like are possible.