Interconnection and manufacturing method thereof

An interconnection includes first and second conductive layers, first and second dielectric layers, a stop layer, and first and second adhesion layers is provided. The first conductive layer is disposed over a semiconductor substrate. The first dielectric layer is over the first conductive layer, and the first dielectric layer includes a via hole. The second dielectric layer is disposed over the first dielectric layer. The stop layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the stop layer include a trench. The second conductive layer is located in the via hole and the trench to electrically connect with the first conductive layer. The first adhesion layer is located on sidewalls of the trench. The second adhesion layer is located between the second conductive layer and the first adhesion layer and between the second conductive layer and the first dielectric layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of this growth, functional density of the devices has generally increased by the device feature size.

In order to meet the requirements for smaller sizes and higher packing densities, electronic devices begin to incorporate a multilayer interconnection structure including interconnections and electrodes with inter-insulating layers disposed therebetween.

DETAILED DESCRIPTION

FIG. 1is a flowchart illustrating a manufacturing method of an interconnection according to some embodiments of the disclosure.FIG. 2AthroughFIG. 2Oare schematic cross-sectional views illustrating a manufacturing process of an interconnection according to some embodiments of the disclosure.

Referring toFIG. 1andFIG. 2A, in step S01, a first conductive layer200, an etch stop layer300a, and a first dielectric layer400are formed over a semiconductor substrate100in sequential order. The semiconductor substrate100is a substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or there upon. In some embodiments, the semiconductor substrate100is a silicon substrate with or without an epitaxial layer, a silicon-on-insulator substrate containing a buried insulator layer, or a substrate with a silicon germanium layer. In some embodiments, the semiconductor substrate100includes a substrate102, a dielectric layer104, an active device106, and a contact108. The active device106is disposed on the substrate102. In some embodiments, the active device106includes a metal-oxide semiconductor (MOS) transistor. In some alternative embodiments, the active device106may include fin field effect transistors (FinFET). The dielectric layer104is disposed over the substrate102and covers the active device106. In some embodiments, the dielectric layer104includes silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant (low-k) material with a dielectric constant lower than 4, for example. A method of forming the dielectric layer includes, for example, spin-coating, CVD, a combination thereof, or the like. The first conductive layer200is disposed over the semiconductor substrate100. The first conductive layer200includes copper, copper alloys, nickel, aluminum, manganese, magnesium, silver, gold, tungsten, a combination of thereof or the like, for example. Other suitable conductive materials may also be adapted for the first conductive layer200. The first conductive layer200may be formed by, for example, electro-chemical plating process, CVD, Plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), PVD, a combination thereof, or the like. It should be noted that in some embodiments, the dielectric layer104includes the contact108buried therein to render electrical connection between the first conductive layer200and the active device106of the semiconductor substrate100. The contact108includes copper, copper alloys, nickel, aluminum, manganese, magnesium, silver, gold, tungsten, a combination of thereof or the like, for example. The contact108is formed by, for example, electro-chemical plating process, CVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a combination thereof, or the like.

The etch stop layer300ais formed over the first conductive layer200to protect the first conductive layer200in the subsequent processes. The etch stop layer300aincludes, for example, silicon carbide, silicon nitride, SiCN, and SiOCN. In some embodiments, the etch stop layer300ais formed by spin-coating, CVD, PVD, or ALD.

Subsequently, a first dielectric layer400ais formed over the etch stop layer300a. In some embodiments, a material of the first dielectric layer400ais different from the material of the etch stop layer300a. For example, the first dielectric layer400aincludes a low dielectric constant (low-k) material, a nitride such as silicon nitride, an oxide such as silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof. Specifically, the low-k material has a dielectric constant of less than about 4 or even less than about 3. For example, the first dielectric layer400amay have a k value of less than about 2.5, and hence is sometimes referred to as an extra low-k (ELK) dielectric layer. In some embodiments, the low-k material includes a polymer based material, such as benzocyclobutene (BCB), FLARE®, or SILK®; or a silicon dioxide based material, such as hydrogen silsesquioxane (HSQ) or SiOF. In some alternative embodiments, the first dielectric layer400amay be made of tetraethylorthosilicate (TEOS) materials. Furthermore, in some embodiments, the first dielectric layer400amay include multiple dielectric materials. The formation method of the first dielectric layer400aincludes, for example, spin-coating, CVD, and ALD.

In some embodiments, a first hard mask layer410ais further formed over the first dielectric layer400a. The first hard mask layer410amay be formed of metallic materials, such as Ti, TiN, Ta, TaN, Al, and the like. In some other embodiments adapting non-metal hard mask scheme, non-metallic materials such as SiO2, SiC, SiN, and SiON may be used. The first hard mask layer410amay be formed by, for example, electro-chemical plating process, CVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), PVD, a combination thereof, or the like. Further, in some alternative embodiments, an antireflection layer (not illustrated) is first formed on the first dielectric layer400a. Subsequently, the first hard mask layer410ais then formed on the antireflection layer. The antireflection layer may be referred to as a bottom anti-reflective coating (BARC). The antireflection layer is a nitrogen-free anti-reflective coating (NFARC) layer. In detail, the NFARC layer includes materials containing, for example, carbon and oxygen.

Referring toFIG. 1andFIG. 2B, in step S02, a photolithographic and etching process is performed on the first hard mask layer410aso that a patterned first hard mask layer410bis formed. Subsequently, with the aid of the patterned first hard mask layer410bas a mask, the first dielectric layer400ais being etched to render a first dielectric layer400bincluding a via hole V formed therein.

Referring toFIG. 1andFIG. 2D, in step S03, a dummy material500bis filled into the via hole V. In some embodiments, the dummy material500bmay include a plug substantially filling the via hole V. Alternatively, in some other embodiments, the dummy material500bmay include a liner located substantially over the bottom and sidewalls of the via hole V. In detail, as illustrated inFIG. 2C, dummy material500ais disposed over the first hard mask layer410aand is filled into the via hole V. The dummy material500amay include one or more layers made of photoresist materials, polymer materials, or dielectric materials. In some embodiments, a material of the dummy material500aand the material of the first dielectric layer400bare different. For example, the dummy material500aincludes silicon, polysilicon, silicon dioxide (SiO2), tetraethylorthosilicate (TEOS) oxide, silicon nitride (SixNy; x and y are greater than 0), borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), low-k dielectric, and/or other suitable materials. The dummy material500amay be formed, for example, by selective epitaxial growth (SEG), CVD, PECVD, ALD, PVD, electrophoresis, spin-on coating, or other suitable processes. Subsequent to the deposition of the dummy material500a, part of the dummy material500aand the first hard mask layer410bare removed so as to render the dummy material500blocated solely in the via hole V, as illustrated inFIG. 2D. The method for removing the excessive dummy material includes, for example, etching, chemical mechanical polishing (CMP), or other suitable polishing methods.

Referring toFIG. 1andFIG. 2E, in step S04, a stop layer310ais formed over the dummy material500band the first dielectric layer400b. A material of the stop layer310amay be the same as or different from the material of the etch stop layer300a. For example, the stop layer310aincludes silicon carbide, silicon nitride, SiCN, SiOCN, and other suitable material in some embodiments. In some embodiments, the stop layer310amay be formed by spin-coating, CVD, PVD, or ALD. Similar to that of the etch stop layer300a, the stop layer310amay also serve the function of protecting the first dielectric layer400band the dummy material500bfrom the subsequent processes.

Referring toFIG. 1andFIG. 2F, in step S05, in some embodiments, a second dielectric layer600ais formed over the stop layer310a. A material of the second dielectric layer600ais identical as the material of the first dielectric layer400b. In alternative embodiments, the material of the second dielectric layer600ais different from the material of the first dielectric layer400band is different from the material of the stop layer310a. Therefore, in some embodiments, the second dielectric layer600aincludes a low dielectric constant (low-k) material, an extra low-k (ELK) material, a nitride such as silicon nitride, an oxide such as silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS), or a combination thereof. Similar to that of the first dielectric layer400b, the second dielectric layer600amay also include multiple dielectric materials. The formation method of the second dielectric layer600aincludes, for example, spin-coating, CVD, PVD, and ALD.

In some alternative embodiments, a second mask layer610ais further formed over the second dielectric layer600a. The second mask layer610amay adapt the same material or different material as compared to the first hard mask layer410a. For example, in some embodiments, the second hard mask layer610amay be formed of metallic materials, such as Ti, TiN, Ta, TaN, Al, and the like. In some other embodiments adapting non-metal hard mask scheme, non-metallic materials such as SiO2, SiC, SiN, and SiON may be used. The second hard mask layer610amay be formed by, for example, electro-chemical plating process, CVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), PVD, a combination thereof, or the like. Further, in some alternative embodiments, an antireflection layer is first formed on the second dielectric layer600a. Subsequently, the second hard mask layer610ais then forming on the antireflection layer. The antireflection layer may be referred to as a bottom anti-reflective coating (BARC). The antireflection layer is a nitrogen-free anti-reflective coating (NFARC) layer. In detail, the NFARC layer includes materials containing, for example, carbon and oxygen.

Referring toFIG. 1andFIG. 2G, in step S06, a photolithographic and etching process is performed to form a patterned second hard mask layer610b. Subsequently, with the aid of the patterned second hard mask layer610bas a mask and the stop layer310aas an etching stop layer, the second dielectric layer600ais being etched to render a second dielectric layer600b. Referring toFIG. 2H, subsequently, the stop layer310aexposed by the second dielectric layer600bis etched to complete the formation of a trench T. In some embodiments, the trench T exposes part of the first dielectric layer400band the dummy material500b. Depending on the materials of the second dielectric layer600aand the stop layer310a, the etching of the second dielectric layer600aand the stop layer310amay be conducted by a same etchant or different etchants. That is, the etching of the second dielectric layer600aand the stop layer310a(as illustrated inFIG. 2GandFIG. 2H) may be performed by a single process or multiple processes. Since the stop layer310ais a thin layer while a high etching selectivity ratio of the stop layer310ato the second dielectric layer600bcan be achieved by the selection of the etchant, the trench T has a planar bottom surface. In some embodiments, the trench T has a planar bottom surface and only a small tiger teeth-like recess402is formed on the sidewalls of the trench T which extends into a portion of the first dielectric layer400b, as illustrated inFIG. 2H.

Referring toFIG. 1,FIG. 2J, in step S07, a first adhesion layer710bis formed on sidewalls SWTof the trench T. In some embodiments, the first adhesion material layer710ais not only formed on the sidewalls SWTof the trench T but also filled in the small tiger teeth-like recess402. In other words, a thickness T3of the first adhesion material layer710bmay be greater than a width of the small tiger teeth-like recess402. Specifically, referring toFIG. 2I, a first adhesion material layer710ais formed over the second hard mask layer610b, in the trench T, and in the small tiger teeth-like recess402. In some embodiments, a material of the first adhesion material layer710ais different from the material of the first dielectric layer400band is different from the material of the second dielectric layer600b. On the other hand, in some embodiments, the material of the first adhesion material layer710ais the same as the material of the stop layer310b. In some alternative embodiments, the material of the first adhesion material layer710ais different from the material of the stop layer310b. Specifically, in some embodiments, the material of the first adhesion material layer710aincludes insulating materials. For example, the insulating materials for the first adhesion material layer710ainclude, SiN, SiON, SiCON, other suitable materials, or combinations thereof. The method for forming the first adhesion material layer710aincludes CVD, PVD, and ALD, for example. Referring toFIG. 2IandFIG. 2J, the first adhesion material layer710ais etched by an anisotropic etching process to expose the dummy material500band the first dielectric layer400b, so as to render the first adhesion layer710blocated on sidewalls SWTof the trench T.

Referring toFIG. 1andFIG. 2K, in step S08, the dummy material500bis removed from the via hole V. The dummy material500bmay be removed by plasma etch, chemical etch, thermal burn-out, and/or other suitable processes. For example, the dummy material500bmay be removed by an oxygen-containing plasma environment. The dummy material500bmay also be removed by a plasma environment which may include reactant gases such as hydrochloric acid (HCl), hydrogen bromide (HBr), sulfur dioxide (SO2), chlorine (Cl2), sulfur hexafluoride (SF6), perfluorocarbons, and/or other reactants. Alternatively, the dummy material500bmay be removed by chemical etch which may include phosphoric acid (H3PO4), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H2SO4), hydrogen peroxide (H2O2), de-ionized water, and/or other chemicals. As illustrated inFIG. 2K, the trench T constitute a larger opening as compared to the via hole V. Alternatively speaking, a width of the trench T is larger than a width of the via hole V.

Referring toFIG. 1andFIG. 2M, in step S09, a second adhesion layer720bis formed on a sidewall SWAof the first adhesion layer710band on sidewalls SWVof the via hole V. Specifically, referring toFIG. 2L, a second adhesion material layer720ais formed over the second hard mask layer610and in the trench T and the via hole V. A material of the second adhesion material layer720ais the same as or different from the material of the first dielectric layer400b. Similarly, the material of the second adhesion material layer720ais the same as or different from the material of the second dielectric layer600b. On the other hand, in some embodiments, the material of the second adhesion material layer720ais the same as the material of the stop layer310b. In some alternative embodiments, the material of the second adhesion material layer720ais different from the material of the stop layer310b. Similar to the first adhesion material layer710b, the second adhesion material layer720aalso includes insulating materials. In some embodiments, the second adhesion material layer720aincludes SiN, SiON, SiCON, other suitable materials, or combinations thereof. The method for forming the second adhesion material layer710aincludes CVD, PVD, and ALD, for example. In some embodiments, the second adhesion material layer720ais formed by ALD so as to provide a good via critical dimension control. As such, the via and trench process window may be enlarged while the electrical property of the semiconductor device may be enhanced.

Referring toFIG. 2M, the second adhesion material layer720ais patterned or etched by an anisotropic etching process, so as to form second adhesion layer720bon a sidewall SWAof the first adhesion layer710band on sidewalls SWVof the via hole V. Subsequent to the formation of the second adhesion layer720b, the etch stop layer300aexposed by the via hole V is removed to render etch stop layer300b. The etch stop layer300bexposes the first conductive layer200for electrical connection in the subsequent processes. It should be noted that the materials of the first adhesion layer710band the second adhesion layer720bmay be the same or different. In some embodiments, the first adhesion layer710band the second adhesion layer720bconstitute an insulation layer700a. The insulation layer700amay be single or multi-layered. For example, in a case where the materials of the first adhesion layer710band the second adhesion layer720bare the same, the insulation layer700ais a single-layered structure. Alternatively, in some alternative embodiments where the materials of the first adhesion layer710band the second adhesion layer720bare different, these two layers constitute the insulation layer700awhich has a multi-layered structure. On the other hand, In some alternative embodiments, the insulation layer700aincludes a first portion P1, a second portion P2, and a third portion P3. In some alternative embodiments, the insulation layer700aincludes the first portion P1and the second portion P2without the third portion P3. The first portion P1of the insulation layer700ais located on the sidewall SWVof the via hole V, and the second portion P2of the insulation layer700ais located on the sidewall SWTof the trench T. The third portion P3of the insulation layer700ais located over the first dielectric layer and extends in a horizontal direction. Moreover, the third portion P3connects the first portion P1and the second portion P2. As illustrated inFIG. 2M, the second portion P2of the insulation layer700aincludes the first adhesion layer710band the second adhesion layer720bwhile the first portion P1and the third portion P3respectively include the second adhesion layer720b. In other words, in some embodiments, a thickness T2of the second portion P2is greater than a thickness Ti of the first portion P1. Similarly, the thickness T2of the second portion P2is also greater than the width of the small tiger teeth-like recess402.

Referring toFIG. 1andFIG. 2O, in step S10, a second conductive layer800bis filled into the trench T and the via hole V to electrically connect with the first conductive layer200and to render an interconnection10. In some embodiments, since the thickness T2of the second portion P2of the insulation layer700ais greater than the width of the small tiger teeth-like recess402, the second conductive layer800bis not filled into the small tiger teeth-like recess402.

Referring toFIG. 2N, in detail, a second conductive material800ais formed over the second hard mask layer610band is filled into the trench T and the via hole V. A material of the second conductive material800amay be the same as or different from the material of the first conductive layer200. For example, the second conductive material800amay include, copper, copper alloys, nickel, aluminum, manganese, magnesium, silver, gold, tungsten, a combination of thereof or the like. Similar to that of the first conductive layer200, the second conductive material800amay be formed by, for example, electro-chemical plating process, CVD, PECVD, ALD, PVD, a combination thereof, or the like. Referring toFIG. 2NandFIG. 2O, a portion of the second conductive material800a, the second hard mask layer610b, a portion of the insulation layer700a, and a portion of the second dielectric layer600bare removed to form the second conductive layer800blocated in the trench T and the via hole V, a insulation layer700band a second dielectric layer600c. The removing process may be achieved by chemical etching, CMP, or other suitable processes. In some embodiments, a barrier layer or a glue layer (not illustrated) may be formed between the second conductive layer800band the insulation layer700bto prevent the migration of the material of the second conductive layer800bto the insulation layer700b, the first dielectric layer400b, and the second dielectric layer600c. In some embodiments, a material of the barrier layer includes tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW) or a combination thereof. Other materials listed above may be used for the barrier layer or the glue layer depending on the material of the second conductive layer800b. Referring toFIG. 2O, after the removing process is completed, the insulation layer700bincludes a first adhesion layer710cand a second adhesion layer720c. The first adhesion layer710cis located on sidewalls SWTof the trench T. The second adhesion layer720cis located between the second conductive layer800band the first adhesion layer710cand between the second conductive layer800band the first dielectric layer400b.

In some embodiments, the second conductive layer800bmay be divided into a first conductive portion810band a second conductive portion820b. The first conductive portion810bis located in the via hole V and the second conductive portion820bis located in the trench T. As mentioned above, a width of the trench T is greater than a width of the via hole V, and thus a width W2of the second conductive portion820bis greater than a width W1of the first conductive portion810b. In some embodiments, the first conductive portion810bconstitute a via and the second conductive portion820bconstitute a conductive line. For example, the via extends along a vertical direction while the conductive line extends along a horizontal direction.

Alternatively, in some embodiments, the first dielectric layer400band the second dielectric layer600cmay be viewed as a single dielectric layer900. In other words, the stop layer310bis buried in the dielectric layer900, and the second conductive layer800bpenetrates through the dielectric layer900. Moreover, as mentioned above, the first adhesion layer710cand the second adhesion layer720cconstitute the insulation layer700bin some embodiments. Referring toFIG. 2O, the first portion P1of the insulation layer700bis located between a portion of the dielectric layer900and the first conductive portion810bof the second conductive layer800b. On the other hand, the second portion P2of the insulation layer700bis located between another portion of the dielectric layer900, the stop layer310b, and the second conductive portion820bof the second conductive layer800b. Moreover, the third portion P3of the insulation layer700bis located under the second conductive portion (conductive line)820band connects the first portion P1of the insulation layer700band the second portion P2of the insulation layer700b.

Referring toFIG. 1andFIG. 2O, in the present disclosure, since the via hole V is formed first and the trench T is then formed, by adapting the stop layer310awith a small thickness (a thin layer) and a specific selection of the etchant (a high etching selectivity ratio of the stop layer310ato the first dielectric layer400b), the loading effect of the device may be reduced. Moreover, as mentioned above, in the interconnection10, the trench T has a substantially planar bottom surface. Even though the small tiger teeth-like recess402are located on sidewalls SWTof the trench T, the size thereof is small enough to be neglected. As a matter of fact, since the insulation layer700bis filled into the tiger teeth-like recess402, the electrical property of the second conductive layer800bfilled in the trench T and the via hole V in the subsequent process would not be compromised. Further, since an insulation layer700bis formed after the formation of the via hole V and the trench T, the process window for the via hole V and the trench T may be enlarged. Consequently, the tuning of the device may be easily achieved, the electrical property of the semiconductor device may be improved, and the yield of the semiconductor device may be enhanced.

The present disclosure is not limited to applications in which the semiconductor device includes MOSFETs or FinFETs, and may be extended to other integrated circuit having a dynamic random access memory (DRAM) cell, a single electron transistor (SET), and/or other microelectronic devices (collectively referred to herein as microelectronic devices).

In accordance with some embodiments of the present disclosure, an interconnection includes a first conductive layer, a first dielectric layer, a second dielectric layer, a stop layer, a second conductive layer, a first adhesion layer, and a second adhesion layer. The first conductive layer is disposed over a semiconductor substrate. The first dielectric layer is disposed over the first conductive layer, and the first dielectric layer includes a via hole. The second dielectric layer is disposed over the first dielectric layer. The stop layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the stop layer include a trench. The second conductive layer is located in the via hole and the trench to electrically connect with the first conductive layer. The first adhesion layer is located on sidewalls of the trench. The second adhesion layer is located between the second conductive layer and the first adhesion layer and between the second conductive layer and the first dielectric layer.

In accordance with alternative embodiments of the present disclosure, an interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, and an insulation layer. The first conductive layer is disposed over a semiconductor substrate. The dielectric layer is disposed over the first conductive layer. The second conductive layer penetrates through the dielectric layer to electrically connect with the first conductive layer. The insulation layer is located between the dielectric layer and the second conductive layer, and a material of the insulation layer and a material of the dielectric layer are different.

In accordance with yet alternative embodiments of the present disclosure, a manufacture method of an interconnection is as below. A first conductive layer and a first dielectric layer are sequentially formed over a semiconductor substrate. A via hole is formed in the first dielectric layer. A dummy material is filled into the via hole. A stop layer and a second dielectric layer are sequentially formed over the first dielectric layer and the dummy material. A trench is formed in the second dielectric layer and the stop layer. A dummy material is removed from the via hole. At least one adhesion layer is formed on sidewalls of the via hole and sidewalls of the trench. A second conductive layer is filled in the via hole and the trench to electrically connect with the first conductive layer.