Battery protection device and chip for protecting battery including a select circuit to select a voltage for a gate control signal

A chip configured to protect a battery includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to a third logic control signal. The select circuit is configured to select the second or third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

TECHNICAL FIELD

The present disclosure relates to a battery protection device and chip therein, and more particularly, to a battery protection device and chip therein without using diode.

DISCUSSION OF THE BACKGROUND

Conventionally, the battery is protected by operating transistors and diodes to turn off when the overcharging or an over-discharging occurs. However, the threshold voltage of the diode limits the operations of the battery protection. Therefore, preventing the problem caused by the threshold voltage of the diode becomes an important issue in this field.

SUMMARY

One aspect of the present disclosure provides a chip, configured to protect a battery. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second voltage or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to generate a third logic control signal. The select circuit is configured to select the second voltage or the third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

In some embodiments, the first voltage is provided by a cathode of a battery, the second voltage is provided by an anode of the battery, the third voltage is provided by an anode of a charger in a charging mode, and the third voltage is provided by an anode of a load in a discharging mode. The anode of the battery is coupled to a first source/drain of the power transistor.

In some embodiments, in the charging mode, a cathode of the charger is coupled to the cathode of the battery, and the anode of the charger is couple to a second source/drain of the power transistor.

In some embodiments, in the discharging mode, a cathode of the load is coupled to the cathode of the battery, and the anode of the load is coupled to a second source/drain of the power transistor.

In some embodiments, the chip further includes a logic control circuit, a mode detect circuit, an overcharging detect circuit, and an over-discharging detect circuit. The logic control circuit is configured to generate the first logic control signal and the second logic control signal according to a first detect signal, a second detect signal, and a third detect signal. The mode detect circuit is configured to generate the first detect signal according to the second voltage and the third voltage, so as to indicate the charging mode or the discharging mode being presented. The overcharging detect circuit is configured to generate the second detect signal according to the first voltage and the second voltage, so as to indicate whether the overcharging occurs. The over-discharging detect circuit is configured to generate the third detect signal according to the first voltage and the second voltage, so as to indicate whether the over-discharging occurs.

In some embodiments, the invert circuit includes a first transistor and a second transistor. The first transistor has a first source, a first drain, and a first gate. The second transistor has a second source, a second drain, and a second gate. The first transistor is P-type transistor, and the second transistor is N-type transistor. The first gate and the second gate are configured to receive the second logic control signal, the first source is configured to receive the first voltage, the second source is configured to receive the third voltage, the first drain is coupled to the second drain, and the first drain and the second drain are configured to generate the third logic control signal.

In some embodiments, the select circuit includes a third transistor and a fourth transistor. The third transistor has a third source, a third drain, and a third gate. The fourth transistor has a fourth source, a fourth drain, and a fourth gate. The third transistor and the fourth transistor are N-type transistor. The third gate is configured to receive the second logic control signal, the fourth gate is configured to receive the third logic control signal, the third source is coupled to the fourth source, the third drain is configured to receive the third voltage, the fourth drain is configured to receive the second voltage, and the third source and the fourth source is configured to transmit the second voltage or the third voltage to the buffer circuit.

In some embodiments, the buffer circuit includes a fifth transistor and a sixth transistor. The fifth transistor has a fifth source, a fifth drain, and a fifth gate. The sixth transistor has a sixth source, a sixth drain, and a sixth gate. The fifth transistor is P-type transistor, and the sixth transistor is N-type transistor. The fifth gate and the sixth gate are configured to receive the first logic control signal, the fifth source is configured to receive the first voltage, the sixth source is configured to receive the second voltage or the third voltage, the fifth drain is coupled to the sixth drain, and the fifth drain and the sixth drain are configured to generate the gate control signal.

In some embodiments, when the overcharging occurs, and the switch circuit generates the gate control signal having a voltage equal to the third voltage to turn off the power transistor, wherein the third voltage is lower than the second voltage.

In some embodiments, when the over-discharging occurs, and the switch circuit generates the gate control signal having a voltage equal to the second voltage to turn off the power transistor, wherein the second voltage is lower than the third voltage.

Another aspect of the present disclosure provides a battery protection device, including a power transistor and a chip. The power transistor has a control gate, first source/drain coupled to an anode of a battery, and a second source/drain coupled to an anode of a load in a discharging mode. The first source/drain is further coupled to an anode of a charger in a charging mode. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to transmit a first voltage or one of a second voltage and a third voltage as a gate control signal to the control gate according to a first logic control signal. The switch circuit is configured to transmit the second voltage or the third voltage to the buffer circuit according to a second logic control signal. When the charger disconnects from the power transistor, the buffer circuit is further configured to continuously transmit the gate control signal to the control gate to prevent the power transistor being turned off.

In some embodiments, the switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert the second logic control signal to generate a third logic control signal. The select circuit is configured to select the second voltage or the third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal.

In some embodiments, the invert circuit includes a first transistor and a second transistor. The first transistor has a first source, a first drain, and a first gate. The second transistor has a second source, a second drain, and a second gate. The first transistor is P-type transistor, and the second transistor is N-type transistor. The first gate and the second gate are configured to receive the second logic control signal, the first source is configured to receive the first voltage, the second source is configured to receive the third voltage, the first drain is coupled to the second drain, and the first drain and the second drain are configured to generate the third logic control signal.

In some embodiments, the select circuit includes a third transistor and a fourth transistor. The third transistor has a third source, a third drain, and a third gate. The fourth transistor has a fourth source, a fourth drain, and a fourth gate. The third transistor and the fourth transistor are N-type transistor. The third gate is configured to receive the second logic control signal, the fourth gate is configured to receive the third logic control signal, the third source is coupled to the fourth source, the third drain is configured to receive the third voltage, the fourth drain is configured to receive the second voltage, and the third source and the fourth source is configured to transmit the second voltage or the third voltage to the buffer circuit.

In some embodiments, the buffer circuit includes a fifth transistor and a sixth transistor. The fifth transistor has a fifth source, a fifth drain, and a fifth gate. The sixth transistor has a sixth source, a sixth drain, and a sixth gate. The fifth transistor is P-type transistor, and the sixth transistor is N-type transistor. The fifth gate and the sixth gate are configured to receive the first logic control signal, the fifth source is configured to receive the first voltage, the sixth source is configured to receive the second voltage or the third voltage, and the fifth drain and the sixth drain are coupled to the control gate, and configured to transmit the gate control signal.

In some embodiments, the chip further includes a logic control circuit, a mode detect circuit, an overcharging detect circuit, and an over-discharging detect circuit. The logic control circuit is configured to generate the first logic control signal and the second logic control signal according to a first detect signal, a second detect signal, and a third detect signal. The mode detect circuit is configured to generate the first detect signal according to the second voltage and the third voltage, so as to indicate the charging mode or the discharging mode being presented. The overcharging detect circuit, is configured to generate the second detect signal according to the first voltage and the second voltage, so as to indicate whether the overcharging occurs in the charging mode. The over-discharging detect circuit is configured to generate the third detect signal according to the first voltage and the second voltage, so as to indicate whether the over-discharging occurs in the discharging mode.

In some embodiments, the first voltage is provided by a cathode of a battery, the second voltage is provided by the anode of the battery, the third voltage is provided by the anode of the charger in the charging mode, and the third voltage is provided by the anode of the load in the discharging mode.

In some embodiments, the third voltage in the discharging mode is higher than the third voltage in the charging mode, the third voltage is lower than the second voltage in the charging mode, and the third voltage is higher than the second voltage in the discharging mode.

In some embodiments, when the overcharging occurs in the charging mode, the switching transmits the gate control signal having a voltage equal to the third voltage to turn off the power transistor.

In some embodiments, when the over-discharging occurs in the discharging mode, the switch circuit transmits the gate control signal having a voltage equal to the second voltage to turn off the power transistor.

DETAILED DESCRIPTION

FIG.1is a schematic diagram of a battery protection device10according to some embodiments of the present disclosure. The battery protection device10is coupled to a battery BA and a load LA. InFIG.1, the battery BA and the battery protection device10are in a discharging mode. The battery BA is configured to provide a current I1from a cathode CD1of the battery BA to a cathode CD2of the load LA, and to receive the current I1by an anode AD1of the battery BA.

The battery protection device10is configured to prevent an over-discharging from occurring in the discharging mode. When the over-discharging occurs, the battery protection device10is configured to stop the current I1being provided to the load LA, so as to protect the battery BA and the load LA from over-discharging.

The battery protection device10is further configured to prevent an overcharging in a charging mode. Please refer toFIG.2.FIG.2is a schematic diagram of a battery protection device10in the charging mode according to some embodiments of the present disclosure.

InFIG.2, the battery BA and the battery protection device10are in the charging mode. A charger CA is configured to provide a current I2from a cathode CD3of the charger CA to the cathode CD1, and to receive the current I2by an anode AD3of the charger CA.

When the overcharging occurs, the battery protection device10is configured to stop the current I2being provided to the battery BA, so as to protect the battery BA and the load LA from overcharging.

Please refer toFIG.1andFIG.2together. The battery protection device10includes a chip100and a power transistor200. The chip100is configured to generate a gate control signal CDO according to a voltage VDD, a voltage VSS, and a voltage Vm. A control gate CG of the power transistor200is configured to receive the gate control signal CDO. A source/drain (S/D) SD1of the power transistor200is coupled to the anode AD1, and an S/D SD2of the power transistor200is coupled to a node N1. The power transistor200is configured to transmit the current I1in the discharging mode and the current I2in the discharging mode. The power transistor200is further configured to be turned off by the gate control signal CDO when the over-discharging and/or the overcharging occur.

The voltage VDD is provided by the cathode CD1, and the voltage VSS is provided by the anode AD1. The voltage VDD is higher than the voltage VSS, and the difference between the voltage VDD and the voltage VSS is associated with the electromotive force provided by the battery BA.

The voltage Vm is transmitted through the node N1. In the discharging mode, the anode AD2is coupled to the node N1. In the charging mode, the anode AD2and the anode AD3are coupled to the N1. Alternatively stated, the voltage Vm is provided by the anode AD2in the discharging mode, and provided by the anode AD3in the charging mode. Therefore, the voltage Vm in the charging mode is different from the voltage Vm in the discharging mode.

Reference is made toFIG.3.FIG.3is a schematic diagram of a chip100according to some embodiments of the present disclosure. The chip100includes a buffer circuit110, a switch circuit,120, a logic control circuit130, a mode detect circuit140, an overcharging detect circuit150, and an over-discharging detect circuit160.

The buffer circuit110is configured to receive a logic control signal SC1generated by the logic control circuit130and the voltage VDD. The buffer circuit110is further configured to receive the voltage VSS or the voltage Vm transmitted from the switch circuit120. The buffer circuit110generates the gate control signal CDO according to the logic control signal SC1, the voltage VDD, the voltage VSS, and the voltage Vm.

The switch circuit120is configured to receive the voltage VSS, the voltage Vm, and a logic control signal SC2generated by the logic control circuit130. The switch circuit120is further configured to transmit the voltage VSS or the voltage Vin to the buffer circuit110according to the logic control signal SC2.

The logic control circuit130is configured to receive a detect signal SD1generated by the mode detect circuit140, a detect signal SD2generated by the overcharging detect circuit150, and a detect signal SD3generated by the over-discharging detect circuit160. The logic control circuit130is further configured to generate the logic control signal SC1and the logic control signal SC2according to the detect signal SD1, the detect signal SD2, and the detect signal SD3.

The mode detect circuit140is configured to receive the voltage VSS and the voltage Vm, and further configured to generate the detect signal SD1according to the voltage VSS and the voltage Vm. More specifically, the mode detect circuit140is configured detect whether the charging mode or the discharging mode is presented by comparing the voltage VSS to the voltage Vm. When the voltage VSS is higher than the voltage Vm, the battery BA and the battery protection device100are in the charging mode. When the voltage VSS is lower than the voltage Vm, the battery BA and the battery protection device100are in the discharging mode. The mode detect circuit140generates the detect signal SD1to indicate that the charging mode or the discharging mode is presented.

The overcharging detect circuit150is configured to receive the voltage VDD and the voltage VSS, and further configured to generate the detect signal SD2according to the voltage VDD and the voltage VSS. More specifically, in the charging mode, the overcharging detect circuit150is configured to detect whether the overcharging occurs by comparing the voltage VDD to the voltage VSS. When a difference between the voltage VDD and the voltage VSS is higher than a first predetermined threshold, the overcharging is occurs, and the overcharging detect circuit150generates the detect signal SD2to indicate the overcharging occurring.

The over-discharging detect circuit160is configured to receive the voltage VDD and the voltage VSS, and further configured to generate the detect signal SD3according to the voltage VDD and the voltage VSS. More specifically, in the discharging mode, the over-discharging detect circuit160is configured to detect whether the over-discharging occurs by comparing the voltage VDD to the voltage VSS. When a difference between the voltage VDD and the voltage VSS is lower than a second predetermined threshold, the over-discharging occurs, and the over-discharging detect circuit160generates the detect signal SD3to indicate the over-discharging occurring.

Reference is made toFIG.4.FIG.4is a schematic diagram of the buffer circuit110, the switch circuit120, and the power transistor200according to some embodiments of the present disclosure.

In some embodiments, the buffer circuit110is an inverter. The buffer circuit110inverts the logic control signal SC1to generate the gate control signal CDO. When the logic control signal SC1has a digital high level, the gate control signal CDO is generated to have a digital low level. The digital low level is voltage VSS or the voltage Vm depending on the operation of the switch circuit140. In some embodiments, the digital high level is equal to the voltage VDD. In some embodiments, the digital low level is equal to the voltage VSS.

The buffer circuit110includes a P-type metal-oxide-semiconductor (PMOS) transistor T1and an N-type metal-oxide-semiconductor (NMOS) transistor T2. The PMOS transistor T1has a gate G1, a source S1, and a drain D1. The NMOS transistor T2has a gate G2, a source S2, and a drain D2. The gate G1and the gate G2are configured to receive the logic control signal SC1. The source S1is configured to receive the voltage VDD. The source S2is coupled to the switch circuit140. The drain D1is coupled to the drain D2, and the drain D1and the drain D2are configured to generate the gate control signal CDO.

When the logic control signal SC1has the digital high level to turn on the NMOS transistor T2and turn off the PMOS transistor T1, the gate control signal CDO is pulled down to the voltage VSS or the voltage Vm. When the logic control signal SC1has the digital low level to turn off the NMOS transistor T2and turn on the PMOS transistor T1, the gate control signal CDO is pulled up to the voltage VDD.

In some embodiments, the switch circuit120includes an invert circuit141and a select circuit142. The invert circuit141includes a PMOS transistor T3and a NMOS transistor T4, and the select circuit142includes a NMOS transistor T5and a NMOS transistor T6.

The PMOS transistor T3has a gate G3, a source S3, and a drain D3. The NMOS transistor T4has a gate G4, a source S4, and a drain D4. The gate G3and the gate G4are configured to receive the logic control signal SC2. The source S3is configured to receive the voltage VDD. The source S4is configured to receive the voltage Vm. The drain D3is coupled to the drain D4, and the drain D3and the drain D4are configured to generate a logic control signal SC3.

When the logic control signal SC2has the digital high level to turn on the NMOS transistor T4and turn off the PMOS transistor T3, the logic control signal SC3is pulled down to the voltage Vm. When the logic control signal SC2has the digital low level to turn off the NMOS transistor T4and turn on the PMOS transistor T3, the logic control signal SC3is pulled up to the voltage VDD.

The NMOS transistor T5has a gate G5, a source S5, and a drain D5. The NMOS transistor T6has a gate G6, a source S6, and a drain D6. The gate G5is configured to receive the logic control signal SC3, and the gate G6is configured to receive the logic control signal SC2. The drain D5is configured to receive the voltage VSS. The drain D6is configured to receive the voltage Vm. The source S5is coupled to the source S6, and the source S5and the source S6are configured to transmit the voltage VSS or the voltage Vm to the source S2of the NMOS transistor T2of the buffer circuit110.

When the logic control signal SC2has the digital high level and the logic control signal SC3has the voltage Vm, the NMOS transistor T5is turned off and the NMOS transistor T6is turned on. Therefore, the voltage Vm is transmitted to the source S2of the NMOS transistor T2of the buffer circuit110. When the logic control signal SC2has the digital low level and the logic control signal SC3has the voltage VDD, the NMOS transistor T5is turned on and the NMOS transistor T6is turned off. Therefore, the voltage VSS is transmitted to the source S2of the NMOS transistor T2of the buffer circuit110.

Based on the battery protection device10shown inFIG.1toFIG.4, the operations in the charging mode and the discharging mode are summarized and shown inFIG.5andFIG.6.

InFIG.5, an operating chart OC1in the charging mode is provided according to some embodiments of the present disclosure. InFIG.6, an operating chart OC2in the discharging mode is provided according to some embodiments of the present disclosure.

Reference is made toFIG.5. In the charging mode, the voltage VSS is higher than the voltage Vm. The charger CA is connected with the battery, the load LA, and the batter protection device10. When there is no overcharging occurring, the current I2is transmitted from the S/D SD1to the S/D SD2through the power transistor200. In this condition, the logic control signal SC1has the digital low level, and the gate control signal CDO has the voltage VDD. The S/D SD1and the S/D SD2have the voltage VSS and the voltage Vm, respectively. The gate control signal CDO keeps the power transistor200being turned on, so as to keep the current I2being transmitted. In some embodiments, the logic control signal SC2and the logic control signal SC3have digital high level and the voltage Vm, respectively.

When the overcharging occurs, the logic control signal SC2and the logic control SC3respectively have the digital high level and the voltage Vm, so as to transmit the voltage Vm to the source S2of the NMOS transistor T2. The logic control signal SC1has the digital high level, and the gate control signal CDO has the voltage Vm. The power transistor200is turned off by the gate control signal CDO.

When the charger CA is disconnected from the battery BA in the charging mode, the battery protection device10is further configured to prevent the load LA from losing the power. In other words, when the charger CA is removed from the load LA and the battery BA, the battery protection device10is further configured to maintain the current provided to the load LA. In this condition, the voltage Vm rises to be higher than the voltage VSS due to disconnecting the charger CA. The mode detect circuit140detects the rising of voltage Vm, and indicates the logic control circuit130to generate the logic control SC1and the logic control signal SC2having the digital high level. Meanwhile, the gate control signal CDO is generated to have the voltage Vm. Therefore, the S/D SD2of power transistor200also has the voltage Vm (which is higher than the voltage VSS now), and the current I1is transmitted from the SD/SD2to the S/D SD1through the power transistor200. The load LA is still being powered on during disconnecting the charger CA.

Reference is made toFIG.6. In the discharging mode, the voltage VSS is lower than the voltage Vm. The charger CA is disconnected from the battery, the load LA, and the batter protection device10. When there is no over-discharging occurring, the current I1is transmitted from the S/D SD2to the S/D SD1through the power transistor200. In this condition, the logic control signal SC1has the digital low level, and the gate control signal CDO has the voltage VDD. The S/D SD1and the S/D SD2have the voltage VSS and the voltage Vm, respectively. The gate control signal CDO keeps the power transistor200being turned on, so as to keep the current I1being transmitted. In some embodiments, the logic control signal SC2and the logic control signal SC3have digital low level and the voltage VDD, respectively.

When the over-discharging occurs, the logic control signal SC2and the logic control SC3respectively have the digital high low and the voltage VDD, so as to transmit the voltage VSS to the source S2of the NMOS transistor T2. The logic control signal SC1has the digital low level, and the gate control signal CDO has the voltage VSS. The power transistor200is turned off by the gate control signal CDO.

When the charger CA is re-connected to the battery BA in the discharging mode, the battery protection device10is further configured to prevent the load LA from losing the power. In other words, when the charger CA is re-connected to the load LA and the battery BA, the battery protection device10is further configured to maintain the current provided to the load LA. In this condition, the voltage Vm drops to be lower than the voltage VSS due to re-connecting the charger CA. The mode detect circuit140detects the dropping of voltage Vm, and indicates the logic control circuit130to generate the logic control SC1and the logic control signal SC2having the digital high level and the digital low level, respectively. Meanwhile, the gate control signal CDO is generated to have the voltage VSS. Therefore, the S/D SD2of power transistor200has the voltage Vm (which is lower than the voltage VSS now), and the current I2is transmitted from the SD/SD1to the S/D SD2through the power transistor200. The load LA is still being powered on during re-connecting the charger CA.

In some conventional approaches, the battery protection chip uses diodes to connect the system low levels, in which the system low levels have different voltage levels. Due to the property of the diodes, when the voltage difference between the opposite sides of the diode is not greater than the threshold of the diode, the diode presents an open circuit. Therefore, in some situations, the system low levels cannot be switched properly, or cannot be transmitted through the diode.

Furthermore, in the other conventional approaches, when the charger is removed from the load, the load loses the power to shut down immediately. The load, such as a cell phone, may be broken due to the hard shutdown.

Compared to the above conventional approaches, the battery protection device10provided by the present disclosure uses a power transistor200without any diode to control the current I1/I2provided to the load LA. Because the power transistor200can be turned on and off immediately without the threshold according to the gate control signal CDO, the battery protection device10can avoid the abovementioned problem in the conventional approaches.

One aspect of the present disclosure provides a chip, configured to protect a battery. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second voltage or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to generate a third logic control signal. The select circuit is configured to select the second voltage or the third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

Another aspect of the present disclosure provides a battery protection device, including a power transistor and a chip. The power transistor has a control gate, first source/drain coupled to an anode of a battery, and a second source/drain coupled to an anode of a load in a discharging mode. The first source/drain is further coupled to an anode of a charger in a charging mode. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to transmit a first voltage or one of a second voltage and a third voltage as a gate control signal to the control gate according to a first logic control signal. The switch circuit is configured to transmit the second voltage or the third voltage to the buffer circuit according to a second logic control signal. When the charger disconnects from the power transistor, the buffer circuit is further configured to continuously transmit the gate control signal to the control gate to prevent the power transistor being turned off.