Infrared remote control receiver (IRCR) having semiconductor signal processing device therein

Disclosed is an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated using CMOS devices fabrication processes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an infrared remote control receiver (IRCR), and more particularly to an IRCR with a semiconductor signal processing device, which is designed to be fabricated using complementary metal oxide semiconductor (CMOS) fabrication processes.

2. Description of the Related Art

An IRCR includes a semiconductor signal processing device having an amplifier therein. Noise reduction characteristic of such an amplifier is an important factor to determine sensitivity of an IRCR. Conventional amplifier in a semiconductor signal processing device of an IRCR is typically fabricated using bipolar junction transistor (BJT) fabrication processes or bipolar complementary metal oxide semiconductor (BiCMOS) fabrication processes to obtain an excellent noise reduction characteristic. A semiconductor signal processing device with an amplifier, which is fabricated by using BJT fabrication processes, is excellent in noise reduction characteristic but is disadvantageous in terms of adjustment of small currents less than 1 nA. Further, an amplifier in a semiconductor signal-processing device must have a large capacitor to stably process signals of several tens of KHz signal band. Accordingly, in the case of fabricating such a semiconductor signal processing device with an amplifier using BJT fabrication processes, the semiconductor signal processing device occupies a large area in a chip and consumes a large amount of powers. Accordingly, the signal processing device has a large chip size. Further, a microcomputer electrically connected to the signal processing device in an IRCR is mostly fabricated using CMOS fabrication processes. Accordingly, it is difficult to combine such a microcomputer mostly fabricated using CMOS fabrication processes and a signal processing device designed to be fabricated using BJT fabrication processes into a single chip because their fabrication processes are not compatible.

Further, an envelope signal detecting circuit in a conventional semiconductor signal processing device of an IRCR generally detects an envelope signal in one direction, a positive direction or a negative direction. However, to improve signal detection efficiency, bi-directionally detected differential envelope signals are needed. To bi-directionally detect envelope signals, two envelope signal-detecting circuits are needed and therefore configuration of such semiconductor signal processing device becomes complicated.

SUMMARY OF THE INVENTION

It is a feature of an embodiment of the present invention to provide an infrared remote control receiver (IRCR) with a semiconductor signal processing device designed to be fabricated using CMOS fabrication processes and being excellent in noise reduction characteristic.

It is another feature of an embodiment of the present invention to provide an IRCR with a semiconductor signal processing device capable of stably amplifying signals when external signals out of allowed ranges is input thereto.

It is further another feature of an embodiment of the present invention to provide an IRCR with a semiconductor signal processing device having an envelope signal detecting circuit with high envelope signals detection efficiency.

It is yet further another feature of an embodiment of the present invention to provide an IRCR with a semiconductor signal processing device capable of stably generating a pulse signal even when a low voltage signal is input thereto.

In accordance with the present invention, there is provided an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated only using CMOS devices fabrication processes.

Preferably, the semiconductor signal processing device may comprise (a) an amplifier for receiving the output of the photo diode and amplifying the received output, (b) a variable gain amplifier for receiving an output of the amplifier and amplifying the noise components and original signal components in the received output signal from the amplifier with different gains, (c) a filter for passing carrier frequency components from output signal of the variable gain amplifier circuit, (d) an envelope signal detecting circuit for abstracting envelope signals from the output of the filter, (e) a hysteresis comparator for comparing the envelope signals output from the envelope signal detecting circuit and generating the pulse signal corresponding to the remote control signal, and (f) an automatic gain controller for receiving outputs of the envelope signal detecting circuit and separately transmitting a signal with the original signal components and a signal with the noise components to the variable gain amplifier circuit.

Preferably, the amplifier may comprise (a) a first capacitor having a first end for receiving the output signal of the photo diode and a second end connected to a first node, (b) a second capacitor having a first end for receiving a reference voltage and a second end connected to a second node, (c) a first operational amplifier having a first input terminal connected to the first node, a second input terminal connected to the second node, and a third input terminal for receiving a common mode feed back signal, wherein the first operational amplifier amplifies signal difference between a high frequency signal input to the first input terminal and a reference signal input to the second input terminal, generates a first output signal and a second output signal and transmits the first and second output signals to a third node and a fourth node, respectively, (d) a common mode feed back circuit for receiving the first output signal and the second output signal of the first operational amplifier from the third node and the fourth node, respectively, generating the common mode feed back signal and transmitting the common mode feed back signal to the third input terminal of the first operational amplifier, (e) a third capacitor connected between the first node and the third node, (f) a first MOS transistor controlled by a predetermined voltage and connected in parallel to the third capacitor, (g) a fourth capacitor connected between the second node and the fourth node; and (h) a second MOS transistor connected in parallel to the fourth capacitor and controlled by a predetermined voltage.

Preferably, the amplifier may comprise (a) a first capacitor having a first end receiving the output signal of the photo diode and a second end connected to a first node, (b) a second capacitor having a first end receiving a reference voltage and a second end connected to a second node, (c) a first operational amplifier for amplifying a high frequency signal and a reference signal, generating a first and second output signals and transmitting the first and second output signals to a third and fourth nodes, respectively, the first operational amplifier having a first input terminal connected to the first node, a second input terminal connected to the second node and a third input terminal receiving a common mode feed back signal, (d) a common mode feed back circuit for receiving the first output signal of the first operational amplifier from the third node, receiving the second output signal of the first operational amplifier from the fourth node, generating the common mode feed back signal and transmitting the common mode feed back signal to the third input terminal of the first operational amplifier, (e) a third capacitor connected to the first node and the third node, (f) a gm cell having a first input terminal connected to the third node, a second input terminal connected to the fourth node, a first output terminal connected to the first node and a second output terminal connected to the second node; and (g) a fourth capacitor connected between the second node and the fourth node.

In accordance with another aspect of the present invention, there is provided an envelope signal detecting circuit comprising an amplifier for amplifying an input signal, and an envelope signal abstracting unit for generating a first envelope signal after receiving an output signal of the amplifier, wherein a minimum voltage level of the output signal of the amplifier is maintained greater than a first reference voltage.

In accordance with further another aspect of the present invention, there is provided an envelope signal detecting circuit comprising an amplifier for amplifying an input signal, a first envelope signal abstracting unit for generating a first envelope signal by receiving an output signal of the amplifier, and a second envelope signal abstracting unit for generating a second envelope signal by receiving an output of the first envelope signal abstracting circuit, wherein the minimum voltage of the output signal of the amplifier is maintained greater than a first reference voltage.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 2002-87413, filed on Dec. 30, 2002, and entitled: “Infrared Remote Control Receiver With Semiconductor Signal Processing Device Designed With Only CMOS PROCESS,” is incorporated by reference herein in its entirety.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. Like reference numerals refer to like elements throughout the drawings.

FIG. 1illustrates an infrared remote control receiver (IRCR) in accordance with the present invention.

Referring toFIG. 1, an IRCR comprises a photo diode20for converting an optical signal to an electrical signal, a semiconductor signal processing device10for eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission system, and a microcomputer30for performing a remote control operation which is ordered by a user by receiving and decoding the pulse signal from the semiconductor signal processing device10.

The semiconductor signal processing device10comprises an amplifier100which receives a signal from the photo diode20and amplifies the received signal, a variable gain amplifier200which amplifies the amplified signal output from the amplifier100with different gains for original signal components and noise components, a filter300which receives outputs of the variable gain amplifier200and transmits only carrier frequency components in the received output signal of the variable gain amplifier200, an envelope signal detecting circuit400which abstracts envelope signals from output signals of the filter300, a hysteresis comparator600which receives the envelope signals output from the envelope signal detecting circuit400, compares the received envelope signals with each other and generates a pulse signal corresponding to a remote control signal, an automatic gain controller500which receives outputs of the envelope signal detecting circuit400and separately transmitting a signal consisted of the original signal components and a signal consisted of the noise components in the output signals of the envelope signal detecting circuit400to the variable gain amplifier200, and a trimming circuit700which receives a high current signal from an external terminal of the semiconductor remote control receiver10and adjusts center frequency of the filter300.

The operation of the IRCR shown inFIG. 1will be described below.

A remote control signal, an optical signal, transmitted from a remote control signal transmission device (not shown) is received by the photo diode20in the remote control receiver and is converted to an electrical signal by the photo diode20. The amplifier100amplifies the electrical signal output from the photo diode20and the amplified signal is transmitted to the variable gain amplification circuit200, which amplifies signal components (original signal) and noise components (noise signal) in the amplified signal with different gains. The filter300filters the signals output from the variable gain amplification circuit200, so that only carrier frequency components pass the filter300and the other components are blocked. The outputs of the filter300are input to an envelope signal detecting circuit400in which envelope signals are abstracted. The abstracted envelope signals are input to a hysteresis comparator600in which the envelope signals are compared with each other and from which a pulse signal corresponding to the remote control signal is generated. The pulse signal output from the hysteresis comparator600is input to an automatic gain controller500which makes the variable gain amplification circuit200to separately or differently adjust gains of the original signal and the noise signal. The pulse signal DOUT output from the hysteresis comparator600is transmitted to the microcomputer30. The microcomputer30performs a remote control operation, which is instructed by a user by receiving the remote control signal from the semiconductor signal processing device10. Then, the trimming circuit700receives a high current signal from an external option pin of the semiconductor signal processing device10and adjusts the center frequency of the filter300by trimming a resistor forming the trimming circuit700using a fusing or Zener zapping method.

FIG. 2illustrates the amplifier of the semiconductor signal processing device shown inFIG. 1, wherein the semiconductor signal processing device has a high pass amplifier designed using MOS switches. The amplifier comprises a high pass amplifier110and a common mode feedback circuit120. The amplifier further comprises a capacitor C2having a first end to which a photo diode voltage signal SPD is applied and a second end connected to a node N3, and a capacitor C3having a first end to which a reference voltage VREF1is applied and a second end connected to a node N4. The amplifier yet further comprises an operational amplifier111having a first input terminal connected to the node N3, a second input terminal connected to the node N4and a third input terminal for receiving a common mode feedback signal CMFBO. The operational amplifier111amplifies signal difference between a high frequency signal OPIN1input to the first input terminal and a reference signal OPIN2input to the second input terminal, generates a first and second output signals OPOUT1, OPOUT2and transmits the output signals OPOUT1, OPOUT2to nodes N5and N6, respectively. The amplifier yet further comprises a common mode feedback circuit120which receives the first and second output signals OPOUT1, OPOUT2of the operational amplifier111through the nodes N5and N6, respectively, generates the common mode feedback signal CMFBO and transmits it to the third input terminal of the operational amplifier111, a first capacitor-transistor combination circuit being comprised of a capacitor C4and a MOS transistor NM1which are connected in parallel to each other between the node N3and the node N5and a second capacitor-transistor combination circuit being comprised of a capacitor C5and a MOS transistor NM2which are connected in parallel to each other between the node N4and a node N6, wherein a predetermined voltage VCR1is commonly applied to gate electrodes of the MOS transistors NM1and NM2.

The operation of the amplifier shown inFIG. 2will be described below.

The amplifier shown inFIG. 2acts both as a high pass filter and an amplifier for amplifying the photo diode voltage signal SPD. The NMOS transistors NM1, NM2have their own gates to which a predetermined voltage signal VCR1is applied, and act as resistors by being operated in linear region. The NMOS transistors NM1, NM2have the same size. Further, capacitances of the capacitors C2and C4are the same as capacitances of the capacitors C3and C5, respectively. Gain of the amplifier100is determined by capacitance ratio of the capacitor C2to the capacitor C4. If the NMOS transistors NM1and NM2have the same resistance RM, high pass frequency is determined by the resistance RM of the NMOS transistors NM1, NM2and the capacitors C2and C4. The common mode feedback circuit120receives the first and second outputs OPOUT1, OPOUT2of the operational amplifier111and generates the common mode feedback signal CMFBO. The amplifier100has transmission characteristic explained below.

Given that “SPD” designates the photo diode voltage signal and “s” designates complex operator, current IC2flowing through the capacitor C2is obtained by multiplying the complex operator s, capacitance of the capacitor C2and voltage of the photo diode voltage signal SPD. That is, IC2=s×C2×SPD. Further, voltage of the output voltage signal OPOUT1is expressed as an equation below.

Accordingly, gain G of the amplifier100is obtained by an equation below.

Assuming that s>>1/(RM×4), the gain G≈(C2/C4).

A high pass pole frequency fp is expressed as follows:

In an application field of low operating speed, resistance, which determines pole frequency of an amplifier, ranges about several MΩ. Accordingly, in the case of implementing such amplifier having high resistance of several MΩ by an integrated circuit, the amplifier occupies a large area on a chip. However, as shown inFIG. 2, in the case of implementing resistors by NMOS transistors NM1, NM2, the amplifier occupies a small area. Further, as shown inFIG. 2, by arranging a capacitor-transistor combination circuits between the first input terminal and the first output terminal of the operational amplifier111and between the second input terminal and the second output terminal of the operation amplifier111, respectively, the amplifier100may differentially operate.

FIG. 3illustrates an amplifier of a semiconductor signal processing device with a high pass amplifier in accordance with the present invention, wherein the amplifier shown inFIG. 3additionally comprises a direct current (DC) level adjusting circuit at an input stage of the amplifier shown inFIG. 2and is designed using MOS switches.

The DC level adjusting circuit130comprises a PMOS transistor PM1having a source to which a power supply voltage VDD is applied, a gate electrode connected to a node N1, and a drain electrode connected to a node N2. The DC level adjusting circuit130further comprises a resistor R1having a first end to which a power supply voltage VDD is applied and a second end connected to the node N2, an operational amplifier131which has a first input terminal connected to the node N2, a second input terminal connected to a ground voltage VSS and an output terminal connected to the node N1, and a capacitor C1connected to the node N1and the ground voltage VSS, wherein the photo diode voltage signal SPD is applied to the node N2.

The operation of the amplifier shown inFIG. 3will be described below.

First, the operation of the DC level adjusting circuit130will be described. Generally, as environment light is brighter, DC of a photo diode in the IRCR increases. Such increased current of the photo diode happens to be greater than an allowed input current of the amplifier. Accordingly, the DC level adjusting circuit130is needed to adjust the DC level input to an input terminal of the amplifier circuit. The photo diode voltage signal SPD is an electrical signal output from a photo diode (not shown) in an IRCR. If an IRCR is in bright environment, DC current flowing through a photo diode in the IRCR increases but voltage of the photo diode voltage signal SPD applied to the node N2decreases. If voltage applied to the node N2becomes below zero, an output of the first operational amplifier112, i.e. voltage of the node N1, becomes logic “low” level, and the MOS transistor PM1is turned, so that voltage of the node N2is pulled up and becomes greater than zero. By the DC level adjusting circuit130, input impedance R1with respect to an infrared optical signal becomes R1, and input impedance with respect to DC signal of the photo diode becomes zero. Accordingly, even if DC flowing through the photo diode (not shown) increases to a level greater than an allowed level, gain of the infrared optical signal may not be decreased.

Accordingly, even though the input signal to the amplifier is greater than allowed range, the amplifier may safely amplify the input signal due to the DC level adjusting circuit130.

FIG. 4illustrates the operational amplifier111, which is shown inFIG. 2andFIG. 3, in detail. The operation amplifier111comprises a PMOS transistor PM3with a source to which a power supply voltage VDD is applied, a drain connected to a node N7and a gate to which a bias voltage VBIAS1is applied, a PMOS transistor PM4with a source to which a power supply voltage is applied, a drain connected to a node N8, and a gate to which the bias voltage VBIAS1is applied, an NMOS transistor NM3with a drain connected to a node N7, a source connected to a node N9and a gate to which a first input signal OPIN1of the operational amplifier is input, an NMOS transistor NM4with a drain connected to the node N8, a source connected to the node N9and a gate to which a second input signal OPIN2of the operational amplifier is input, a current source Ib1connected between the node N9and a ground voltage VSS, a PMOS transistor PM5with a source connected to the node N7, a gate connected to a node N11and a drain connected to a node N10, a PMOS transistor PM6with a source connected to the node N8, a gate and a drain which are connected to the node N11, an NMOS transistor NM5with a drain connected to the node N10, a gate to which a bias voltage VBIAS2is applied, an NMOS transistor NM7with a drain connected to the source of the NMOS transistor NM5, a drain connected to a ground voltage VSS and a gate connected to a node N12, an NMOS transistor NM6with a drain connected to the node N11, a gate to which a bias voltage VBIAS2is input and an NMOS transistor NM8with a drain connected to the source of the NMOS transistor NM6, a source connected to a ground voltage VSS and a gate connected to the node N12, wherein the common mode feed back signal CMFBO is applied to the node N12and the first output signal OPOUT1and the second output signal OPOUT2of the operational amplifier111are output from the nodes N10and N11, respectively.

As shown inFIG. 4, the operational amplifier111receives two input signals OPIN1, OPIN2and one common mode feed back signal CMFBO, amplifies voltage difference between the two input signals OPIN1and OPIN2, and generates two output signals OPOUT1, OPOUt2. As the input signal OPIN2, a reference voltage, a half power supply voltage VDD/2, is used and the input signal OPIN2is applied to the operational amplifier111through a capacitor (not shown). As the input signal OPIN1, the photo diode voltage signal SPD, is input through a capacitor (not shown) to the operational amplifier111. Further, when the operational amplifier normally operates, the two output signals OPOUT1, OPOUT have about a half power supply voltage VDD/2.

If voltage levels of the two output signals OPOUT1, OPOUT2of the operational amplifier111become greater than the half power supply voltage VDD/2, voltage level of the common mode feed back signal CMFBO increases by the common mode feed back circuit. Further, if voltage level of the common mode feed back circuit increases, voltage levels of the two output signals OPOUT1, OPOUT2are lowered.

If voltage levels of the two output signals OPOUT1, OPOUT2of the operational amplifier111are lower than the half power supply voltage VDD/2, voltage level of the common mode feed back signal CMFBO is lowered by the operation of the common mode feed back circuit. Further, if voltage level of the common mode feed back signal CMFBO is lowered, voltage levels of the two output signals OPOUT1, OPOUT2of the operational amplifier111increase.

FIG. 5illustrates the common mode feed back circuit120shown inFIG. 2andFIG. 3, wherein the common mode feed back circuit120comprises a common mode signal generator121and a common mode amplifier122.

The common mode signal generator121comprises a PMOS transistor PM7with a source connected to a power supply voltage VDD, a gate and drain commonly connected to a node N13, a PMOS transistor PM18with a source connected to a power supply voltage VDD, a gate connected to a node N13and a drain connected to a node N14, an NMOS transistor NM9with a drain connected to the node N13, a source connected to a node N15and a gate to which the first output signal OPOUT1of the operational amplifier is applied, an NMOS transistor NM10with a gate and drain commonly connected to the node N14and a source connected to a node N15, a current source Ib2connected between the node N15and a ground voltage VSS, an NMOS transistor N11with a gate and drain commonly connected to the node N14and a source connected to a node N16, an NMOS transistor NM12with a drain connected to the node N13, a source connected to a node N16and a gate to which the second output signal OPOUT2of the operational amplifier is applied, and a current source Ib3connected between the node N16and a ground voltage VSS, wherein an output voltage Vcmo of the common mode signal generator121is generated from the node N14.

The common mode amplifier122comprises a current source Ib4connected between a power supply voltage VDD and a node N17, a PMOS transistor PM9with a source connected to the node N17and a gate connected to the node N14, an NMOS transistor NM13with a gate and drain commonly connected to the drain of the PMOS transistor PM9and a source connected to a ground voltage VSS, a PMOS transistor PM10with a source connected to the node N17, a drain connected to a node N18and a gate to which a reference voltage VREF2is applied, and an NMOS transistor NM14with a gate and drain commonly connected to the drain of the PMOS transistor PM10and a source connected to a ground voltage VSS, wherein the common mode feed back signal CMFBO is generated from the node N18.

The operation of the common mode feed back circuit120will be described below.

The total amount of a current flowing through the drain of the NMOS transistor NM9and a current flowing through the drain of the NMOS transistor NM12is the same as an amount of a current flowing through the drain of the PMOS transistor PM7. An output current Icmo of the common mode signal generator125is obtained by subtracting a current flowing through the drain of the NMOS transistor NM10and a current flowing through the drain of the NMOS transistor NM11from a current flowing through the drain of the PMOS transistor PM8. Further, an output voltage Vcmo of the common mode signal generator125equals to the output current Icmo of the current mode signal generator125times an output impedance of the common mode signal generator125. Assuming that transconductances gm of the transistors NM9, NM10, NM11and NM12are the same, a drain current ID9of the transistor NM9is expressed as an equation, ID9=gm×((OPOUT1−Vcmo)/2), a drain current of the transistor NM10is expressed as an equation, ID10=gm×((Vcmo−OPOUT1)/2), a drain current ID11of the NMOS transistor NM11is expressed as an equation, ID11=gm×((Vcmo−OPOUT2)/2), and a drain current ID12of the NMOS transistor NM12is expressed as an equation, ID12=gm×((OPOUT2−Vcmo)/2). An medium value VCMof the first and second input signals OPOUT1, OPOUT2is expressed as an equation, VCM=(OPOUT1+OPOUT2)/2, and the output current Icmo of the common mode signal generator125is obtained by a following equation.
Icmo=ID9−I10−ID11+ID12=gm×(VCM−Vcmo)

On the other hand, if the output impedance of the common mode signal generator125is Rout, the output voltage Vcmo of the common mode signal generator125is expressed as an equation, Vcmo=Icmo×Rout=gm×Rout×(VCM−Vcmo). Accordingly, the Vcmo is obtained by a following equation.
Vout=(gm×Rout×VCM)/(1+gm×Rout)
Whengm×Rout>>1, Vout≈VCM

The common mode feed back circuit shown inFIG. 5does not include passive elements such as resistors but only comprises MOS transistors. Accordingly, the common mode feed back circuit in accordance with the present invention occupies a small area on a chip.

FIG. 6illustrates an amplifier with a high pass amplifier designed using a gm cell in accordance with the present invention. A gm cell142receives a first and second output signals OPOUT1, OPOUT2of an operational amplifier111and generates two output signals which are transmitted to a first and second input nodes N3, N4of the operational amplifier111.

To process signals of low frequency band of several tens of kHz, a feed back resistor having high feed back resistance is needed. Accordingly, if the feed back resistor is implemented by a passive element, chip size of a semiconductor signal processing device is greatly increased. As shown inFIG. 6, in the case of implementing the feed back resistor by a gm cell operating at sub-threshold voltage, chip size of a signal processing device is reduced. Further, the high pass amplifier using a gm cell stably saturates its output signal and the output signal is not folded and distorted even in the case that a high voltage signal is input thereto. Accordingly, in the case of using amplifiers at a plurality of stages, such a high pass amplifier using a gm cell may be arranged at a later stage to amplify pre-amplified signals by fore stages of amplifiers without signal distortion.

FIG. 7illustrates a high pass amplifier with a DC level adjusting circuit and using a gm cell as a resistor. The amplifier ofFIG. 7includes all the elements shown inFIG. 6and further includes a DC level adjusting circuit130arranged at an input stage of the amplifier shown inFIG. 6. Circuit configuration and the operation of DC level adjusting circuit130are described above with reference toFIG. 3, so that explanation about the DC level adjusting circuit130is omitted here with reference toFIG. 7.

FIG. 8illustrates a gm cell used in the high pass amplifiers shown inFIG. 6andFIG. 7.

The gm cell with reference toFIG. 8comprises a current source Ib81connected between a power supply voltage VDD and a node N81, a PMOS transistor PM81with a source connected to the node N81, a drain connected to a node N83and a gate to which a first input signal GMCI1is applied, a PMOS transistor PM82with a source connected to the node N81, a drain connected to a node N84and a gate to which a second input signal GMCI1is applied, a current source Ib82connected between a power supply voltage VDD and the node N82, a PMOS transistor PM83with a source connected to the node N82, a drain connected to the node N83and a gate to which the first input signal GMCI1is applied, a PMOS transistor PM84with a source connected to the node N82, a drain connected to the node N84and a gate to which the second input signal GMCI2is applied, an NMOS transistor NM85with a drain connected to the node N83, a source connected to a ground voltage GND and a gate connected to the node N85, an NMOS transistor NM86with a drain connected to the node N84, a source connected to a ground GND and a gate connected to the node N85, and a common mode feed back circuit810which receives a first output signal GMCO1and a second output signal GMCO2from the node N84and the node N83, respectively and generates a common mode feed back signal which is transmitted to the node N85.

InFIG. 8, the first input signal GMCI1and the second input signal GMCI2correspond to the first output signal OPOUT1and the second output signal OPOUT2, respectively, of the operational amplifier111inFIG. 6andFIG. 7. Accordingly, the first output signal GMCO1is transmitted to the node N3inFIG. 6and the second output signal GMCO2is transmitted to the node N4inFIG. 7. The gm cell shown inFIG. 8generates a current Io which is proportional to signal difference between the first and second input signals GMCI1, GMCI2, and the current lo is expressed as an equation, Io=gm×(GMCI1−GMCI2).

InFIG. 6andFIG. 7, respectively, assuming that the input stage of the operational amplifier111is in a virtual ground state and a resistor is used instead of the gm cell142, a current flowing through the resistor is obtained by dividing the output voltage OPOUT1by resistance of the resistor. If the resistor is replaced with a gm cell, an output current I of the gm cell is expressed as an equation, I=gm×OPOUT1. Here, even if the output voltage OPOUT1is replaced with the output voltage OPOUT2, the output current I is the same. Accordingly, by using a gm cell as shown inFIG. 2, a resistor with high resistance of MΩ can be implemented.

FIG. 9illustrates an envelope signal detecting circuit in accordance with a first embodiment of the present invention.FIG. 9is a detailed circuit diagram of the envelope signal detecting circuit400shown inFIG. 2. Referring toFIG. 9, an envelope signal detecting circuit comprises a high pass amplifier910, an envelope signal abstracting unit920and a comparator930.

The high pass amplifier910comprises an operational amplifier912which has a first input terminal for receiving an input signal Vin through a capacitor C11and a second input terminal for receiving a reference voltage VREF3, amplifies voltage difference between the input signal Vin and the reference voltage VREF3, generates and transmits its amplified output signals to a node N91. The high pass amplifier910further comprises a capacitor C12connected between the first input terminal and an output terminal of the operational amplifier912, and an NMOS transistor NM91which has a gate to which a control voltage Vcr is applied and is connected between both ends of the capacitor C12.

The envelope signal abstracting unit920comprises an operational amplifier922having a first input terminal for receiving an output signal SAMPO of the high pass amplifier910and a second input terminal connected to a node N92, and for amplifying voltage difference between the output signal SAMPO of the high pass amplifier910and a first envelope signal EVNO1which is a voltage of the node N91. The envelope signal abstracting unit920further comprises an NMOS transistor NM92with a gate connected to the output terminal of the operational amplifier922and a source connected to the node N92, a current source Ib91connected between a power supply voltage VDD and the drain of the NMOS transistor NM92for supplying currents, a capacitor C13connected between the node N92and a ground voltage VSS and a current source Ib92connected between the node N92and a ground voltage VSS.

The operation of the envelope signal detecting circuit in accordance with a first embodiment of the present invention will be described below with reference toFIG. 9andFIG. 10.

The high pass amplifier910is a characterized element of the present invention. The high pass amplifier910serves as a high pass filter and as an amplifier for amplifying an input signal Vin and generating an output signal SAMPO. Since a predetermined control voltage Vcr is applied to the gate of the NMOS transistor NM91, the NMOS transistor NM91is operated both in a linear region and a saturation region.

Gain of the high pass amplifier910is determined by the capacitance ratio of the capacitor C11to the capacitor C12. If resistance of the NMOS transistor NM91is RM, high pass frequency is determined by the capacitors C11, C12and the resistance RM of the NMOS transistor NM91. When the output signal SAMPO of the high pass amplifier910, I.e. voltage of the node N91, is getting lowered than the reference voltage VREF3input to the second input terminal of the operational amplifier912, the NMOS transistor NM91is turned on and the output signal SAMPO of the high pass amplifier910becomes the same level as the reference voltage VREF3. That is, a minimum voltage of the output signal SAMPO of the high pass amplifier910is not lowered below the reference voltage VREF3. As a result, as shown inFIG. 10, virtual ground, ac ground, level of the output signal SAMPO of the high pass amplifier910changes based on voltage level of the output signal SAMPO. Since, the virtual ground voltage increases by the high pass amplifier910, even though low input signal is input, envelope signals detection efficiency is improved.

The envelope signal abstracting unit920receives the output signal SAMPO of the high pass amplifier910and generates a first envelope signal ENVO1. The operational amplifier922amplifies voltage difference between the output signal SAMPO of the high pass amplifier910and voltage of the node N91, and controls a current flowing through the NMOS transistor NM92. The current of the NMOS transistor NM92charges a capacitor C13and pulls up voltage of the node N92. The current source Ib92determines discharging speed for discharging a voltage of the charged capacitor C13.

The comparator930receives the first envelope signal ENVO1, compares it with a reference voltage VREF4and generates a pulse signal DOUT. As shown inFIG. 10, in the range that the first envelope signal ENVO1is greater than the reference voltage VREF4, the pulse signal DOUT has a logic “high” level, and when the envelope signal ENVO1is lower than the reference voltage VREF4, the pulse signal DOUT has a logic “low” level.

FIG. 11illustrates an envelope signal detecting circuit in accordance with a second embodiment of the present invention, wherein the envelope signal detecting circuit comprises a high pass amplifier910, a first envelope signal abstracting element920, a second envelope signal abstracting element940and a comparator930. The high pass amplifier910comprises an operational amplifier912having a first input terminal for receiving an input signal Vin through a capacitor C11and a second input terminal for receiving a reference voltage VREF3, amplifying voltage difference between the input signal Vin and the reference voltage VREF3and outputting an output signal SAMPO to a node N91. The high pass amplifier910further comprises a capacitor C12connected between the first input terminal and an output terminal of the operational amplifier912, and an NMOS transistor NM91connected between both ends of the capacitor C12and having a gate to which a control voltage Vcr is applied.

The first envelope signal abstracting unit920comprises an operational amplifier922having a first input terminal for receiving the output signal SAMPO of the high pass amplifier910and a second input terminal connected to a node N92and amplifying voltage difference between the output signal SAMPO of the high pass amplifier910and a voltage of the node N92, an NMOS transistor N92with a gate connected to an output terminal of the operational amplifier922and a source connected to the node N92, a current source Ib91connected between a power supply voltage VDD and a drain of the NMOS transistor N92and supplying a current, a capacitor C13connected between the node N92and a ground voltage VSS and a current source Ib92connected between the node N92and a ground voltage VSS. The first envelope signal abstracting unit920generates a first envelope signal ENVO1and transmits it to the node N92.

The second envelope signal abstracting unit940comprises an operation amplifier942having a first input terminal for receiving the first envelope signal EVNO1output from the first envelope signal abstracting unit920and a second input terminal connected to a node N93, and amplifying voltage difference between the first envelope signal EVNO1and a voltage of the node N93, an NMOS transistor NM93with a gate connected to an output terminal of the operational amplifier942and a source connected to the node N93, a current source Ib93connected between a power supply voltage VDD and a drain of the NMOS transistor NM93and supplying a current, a capacitor C14connected between the node N93and a ground voltage VSS and a current source Ib94connected between the node N93and a ground voltage VSS. The second envelope signal abstracting unit940generates a second envelope signal ENVO2and transmits it to the node N93.

The operation of the envelope signal detecting circuit in accordance with the second embodiment of the present invention will be described below with reference toFIG. 11andFIG. 12.

The high pass amplifier910operates in the same way as the high pass amplifier shown inFIG. 9. The first envelope signal abstracting unit920operates in the same way as the envelope signal abstracting unit920shown inFIG. 9. Accordingly, explanation about the operation of the high pass amplifier910and the first envelope signal abstracting unit920of the envelope signal detecting circuit in accordance with the second embodiment of the present invention will be omitted.

The second envelope signal abstracting unit940receives the first envelope signal ENVO1which is an output signal of the first envelope signal abstracting unit920, and generates a second envelope signal ENVO2. The operational amplifier942amplifies voltage difference between the first envelope signal ENVO1and a voltage of the node N93and control currents of the NMOS transistor NM93. The current of the NMOS transistor NM93charges the capacitor C14to pull up the voltage of the node N93. The current source Ib94determines discharging speed of the charged capacitor C14.

The comparator930receives the first envelope signal ENVO1and the second envelope signal ENVO2as input signals, compares them and outputs a pulse signal DOUT. As shown inFIG. 12, when the first envelope signal ENVO1has a voltage grater than a voltage of the second envelope signal ENVO2, the pulse signal DOUT has a logic “high” level, and when the first envelope signal ENVO1has a voltage less an a voltage of the second envelope signal ENVO2, the pulse signal DOUT has a logic “low” level.

Since the envelope signal detecting circuit in accordance with the second embodiment of the present invention shown inFIG. 11has the high pass amplifier910, a minimum voltage of the output signal SAMPO of the high pass amplifier910is not lowered below the reference voltage VREF3. As a result, virtual ground level of the output signal SAMPO of the high pass amplifier910changes based on voltage level of the output signal SAMPO. Since the virtual ground voltage increases by the high pass amplifier910, envelope signals detection efficiency is improved even when a low input signal is applied thereto.

On the other hand, distance between a remote control receiver and a remote control transmission device determines the size of a burst signal received by the remote control receiver. Accordingly, pulse width of the pulse signal DOUT, which is an output of the comparator, changes based on the distance between the receiver and transmission device. However, since the envelope signal detecting circuit in accordance with the second embodiment of the present invention uses the second envelope signal ENVO2, which is an output of the second envelope signal abstracting unit940, as the reference voltage of the comparator930, the pulse width of the pulse signal DOUT is constant.

As described above, the IRCR in accordance with the present invention has the signal processing device, which is designed using only CMOS process and has a good noise reduction characteristic. Further, the IRCR of the present invention may stably amplify input signals even if the input signals has a large current out of allowed ranges to be input to the amplifier. Further, the signal processing device has a smaller size than conventional semiconductor signal processing devices. The IRCR of the present invention includes an envelope signal detecting circuit with high envelope signals detection efficiency. The envelope signal detecting circuit in accordance with the present invention may stably generate a pulse signal even if a lower signal is input.