A phase inverter generates two signals 180.degree. out-of-phase at microwave frequencies in response to an input microwave signal incorporating a semiconductor substrate such as gallium arsenide, a transistor having a drain, source and gate electrode, an ion-implanted resistor coupled between the drain electrode and a voltage source, a second ion-implanted resistor coupled between the source electrode and ground potential, a compensation network such as a capacitor coupled between the source electrode and ground potential, and a biasing network for establishing a bias voltage on the gate electrode. The phase inverter which may be monolithic overcomes the problem of the size of quarter wavelength slot lines to generate signals with 180.degree. phase relationship.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to phase inverters and, more particularly, to a 
microwave phase inverter. 
2. Description of the Prior Art 
The advantages of push-pull amplifier circuits, i.e., cancellation of even 
harmonics at the output, reduced susceptibility to power supply ripple 
voltages, etc., are well known. In the past few years, push-pull microwave 
field effect transistor amplifiers have been fabricated in a hybrid 
format. That is, individual transistors and capacitors were interconnected 
on a supporting substrate which contained metallization for 
interconnection at microwave frequencies. These circuits have typically 
used slot-microstrip tees to provide two input signals that are 
180.degree. out-of-phase for the push-pull amplifier. One example of a 
push-pull power amplifier using slot lines is described in U.S. Pat. No. 
4,097,814 which issued on June 27, 1978 to M. Cohn and is assigned to the 
assignee herein. Because the slot line tee employs .lambda./4 slot lines, 
it is relatively large and requires photoengraving and registration on 
both sides of the substrate, which is difficult to achieve in monolithic 
integrated circuits. 
A split-load phase inverter as shown in FIG. 1 is a common circuit which is 
used at lower frequencies to provided phase inversion for push-pull 
amplifiers. The split-load phase inverter has two resistors, one coupled 
to the source and one coupled to the drain of a field effect transistor 
which are equal in value to provide equal output voltages which are 
180.degree. out-of-phase. The gain of a split-load phase inverter 
approaches unity if the transconductance, g.sub.m times the value of the 
resistance R in ohms is much much greater than one. 
It is therefore desirable to provide a monolithic microwave split-load 
phase inverter. 
It is further desirable to provide a split-load phase inverter on a gallium 
arsenide substrate incorporating ion-implanted resistors. 
It is further desirable to provide a monolithic microwave split-load phase 
inverter having a compensation network to balance the source-to-ground 
capacitance with the drain-to-ground capacitance at microwave frequencies. 
SUMMARY OF THE INVENTION 
A phase inverter for generating two output signals 180.degree. out-of-phase 
from an input signal is described comprising a semiconductor substrate 
such as a gallium arsenide semi-insulating substrate having an active 
region therein, a field effect transistor in the active region having a 
drain-and-source electrode and a gate electrode therebetween, an 
ion-implanted resistor coupled between the drain electrode and a voltage 
terminal, an ion-implanted resistor coupled between the source electrode 
and a ground terminal, an input signal coupled to the gate electrode, a 
bias network coupled to the gate electrode, and output terminals coupled 
to the drain-and-source electrodes for coupling out the first and second 
signals respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to the drawing and in particular to FIG. 1, a split-load phase 
inverter circuit 10 is shown. An input signal is coupled over line 11 to 
the gate of a field effect transistor 12. The drain of field effect 
transistor 12 is coupled through a resistor 13 to a voltage source 
V.sub.DS. The drain is also coupled over line 14 to an output terminal to 
provide an output signal E.sub.2. The source of field effect transistor 12 
is coupled over line 15 to an output terminal to provide an output signal 
E.sub.1. The source is also coupled through resistor 16 to ground 
potential over line 17. 
In operation, transistor 12 conducts current in response to the voltage on 
its gate, causing current to pass through transistor 12. The current 
passing through transistor 12 will cause a voltage E.sub.1 to occur across 
resistor 16 and a voltage E.sub.2 to occur across resistor 13. As the 
current increases through transistor 12, voltage E.sub.1 will increase and 
voltage E.sub.2 will decrease. Since the same current causes the voltage 
drop across resistors 13 and 16, the output voltages will be 180.degree. 
out-of-phase with respect to each other. Typically, the value of resistor 
13 will equal the value of resistor 16 so that the amplitude of the 
voltage swings of signals E.sub.1 and E.sub.2 will be equal. 
FIG. 2 shows a schematic diagram of a microwave split-load phase inverter 
20 providing anti-phase input signals to push-pull amplifier 33. 
Typically, the drain-to-ground capacitance and the source-to-ground 
capacitance of transistor 12 are not equal and the difference in reactance 
becomes significant at microwave frequencies, causing the outputs on lines 
14 and 15 to be unbalanced. Compensation network 21 is added to equalize 
the output impedances on lines 14 and 15. The nature of compensation 
network 21 is heavily dependent upon the field effect transistor 
configuration and hence will vary depending upon the field effect 
transistor used; however it may for some transistors be a shunt 
capacitance 22 shown in FIG. 2. Compensation network 21 is coupled between 
line 15 and line 17. 
The signal at line 14 is coupled through impedance transforming network 23 
and over line 24 to the gate of transistor 25. The signal at line 15 is 
coupled through impedance transforming network 26 and over line 27 to the 
gate of transistor 28. The source of transistors 25 and 28 are coupled to 
ground potential via line 17. The drain of transistor 25 is coupld over 
line 29 to an output terminal and to voltage V.sub.DS. The drain of 
transistor 28 is coupled over line 31 to an output terminal and to voltage 
V.sub.DS. The signals on lines 29 and 31 are 180.degree. out-of-phase and 
represent the output of push-pull amplifier 33. 
Impedance transforming networks 23 and 26 in combination with transistors 
25 and 28 provide a large resistive load to the output of inverter circuit 
10. The large resistive load increases the effective resistance at the 
drain and source of transistor 12. The drain of transistor 12 sees an 
effective resistance of resistor 13 in parallel with impedance 
transforming network 23 and transistor 25. The source of transistor 12 
sees an effective resistance of resistor 16 in parallel with impedance 
transforming network 26 and transistor 28. The effective resistance, 
R.sub.eff, must be large in order to avoid excessive loss of gain. Phase 
inverter circuit 20 approaches unity gain when the transconductance 
g.sub.m times the effective resistance R.sub.eff is much much greater than 
one. Typically, transistors 12, 25 and 28 have a transconductance in the 
range from 80 to 100. This requires that the effective resistance 
R.sub.eff must be greater than 50 ohms. Impedance transforming networks 23 
and 26 function to transform the relatively low gate-to-source input 
impedance of transistors 25 and 28, respectively, up to the order of 50 to 
100 ohms. 
Referring to FIG. 3, a monolithic microwave phase inverter 37 is shown. A 
semiconductor substrate 40 which may be, for example, silicon, indium 
phosphide or gallium arsenide which may be semi-insulating, having active 
regions 41 through 45 on upper surface 38. Active regions 42 and 45 are 
spaced apart with active region 43 positioned between active regions 42 
and 44. In active region 43, a metal semiconductor field effect transistor 
46 is formed, which may be N channel, having a gate electrode 48, a drain 
electrode 49 and a source electrode 50. Active region 42 contains an 
ion-implanted resistor 52. Active region 44 contains an ion-implanted 
resistor 54. Alternatively, resistors 52 and 54 may be thin film 
resistors. Drain electrode 49 extends from active region 43 over to 
ion-implanted resistor 52 to make connection with one side of 
ion-implanted resistor 52. Source electrode 50 extends from active region 
43 over to ion-implanted resistor 54 and makes contact with one side of 
ion-implanted resistor 54. Adjacent to active region 42 is active region 
45 containing metallization 56 having vias 57 through 59 connecting 
metallization 56 to metallization 60 on the lower surface 39 of substrate 
40. Above metallization 56 is mounted a thin film capacitor 61 having a 
dielectric 51 and an upper electrode 53 which is coupled by means of an 
air bridge of metallization or gold-bond wire 78B to the other side of 
resistor 52. 
Metallization 62 is positioned adjacent and extends over active region 44 
and is coupled to one side of resistor 54. Metallization 62 has vias 63 
through 65 which couple metallization 62 to metallization 60 on the lower 
surface 39 of substrate 40. Metallization 62 may have fingers 67 and 68 
which are positioned between fingers 69 and 70 extending from source 
electrode 50 to form an interdigitated capacitor 71. Interdigitated 
capacitor 71 forms a compensation network so that the drain-to-ground 
capacitance and source-to-ground capacitance of transistor 46 are 
substantially equal or balanced. Alternatively, capacitor 71 may be an 
overlay capacitor which is well-known in the art. Drain electrode 49 and 
source electrode 50 may be rectangular in shape with gate electrode 48 
therebetween, rectangular in shape and parallel to the edges of the 
drain-and-source electrodes. Gate electrode 48 may extend colinearly 
beyond active region 43 and across active region 41 to an input terminal. 
The width of metallization 48 beyond active region 43 may be adjusted to 
provide a predetermined impedance with substrate 40 and metallization 60 
on the lower surface 39 of substrate 40. Active region 41 may contain 
ion-implanted resistors 73 and 74 which may be positioned on either side 
of metallization 48 and coupled to metallization 48. The other end of 
resistor 74 may be coupled to metallization 62. The other end of resistor 
73 may be coupled by means of air bridge or gold-bond wire to the top 
electrode of capacitor 75 having a bottom electrode coupled to 
metallization 56. The upper electrodes of capacitors 75 and 61 are also 
coupled to a source of voltage, V.sub.DS, over gold-bond wires 76 and 78A, 
V.sub.DS may be in the range from 5 to 10 volts. Resistors 73 and 74 are 
positioned between ground and voltage, V.sub.DS, to provide a bias voltage 
to the gate electrode of transistor 46. Alternatively, resistors 73 and 74 
may be thin film resistors. Capacitors 61 and 75 function to bypass high 
frequencies to ground metallization 56. 
Electrode 49 may extend as metallization 80 having a predetermined width to 
provide a characteristic impedance with respect to substrate 40 and 
metallization 60. Likewise, source electrode 50 may extend as 
metallization 81 having a predetermined width to provide a predetermined 
impedance. Metallizations 80 and 81 function as outputs from the phase 
inverter 37 wherein the phase of the output signals are 180.degree. 
shifted with respect to each other. 
FIG. 3 is bisected by line IV--IV to produce FIG. 4, a cross-section of the 
monolithic microwave phase inverter 37. The semi-insulating semi-conductor 
substrate 40 having active regions 41 through 45 on upper surface 38 are 
spaced co-linearly across upper surface 38. Active region 43, positioned 
between active regions 42 and 44 contains a metal semi-conductor field 
effect transistor 46. This MOSFET 46 comprising gate electrode 48, drain 
electrode 49 and source electrode 50, is bounded by active region 42 and 
active region 44. Active region 42 contains ion-implanted resistor 52 and 
active region 44 contains ion-implanted resistor 54. Alternatively, 
resistors 52 and 54 may be thin film resistors. Note, that the drain 
electrode 49 of the MOSFET 46 is positioned, touching the side wall of 
resistor 52 and that the source electrode 50 of the MOSFET 46 is also 
positioned against the side wall of ion-implanted resistor 54. Adjacent to 
active region 42 is active region 45. Active region 45 contains thin film 
capacitor 61 resting upon metallization 56. Thin film capacitor 61 
comprises dielectric 51 and upper electrode 53. This thin film capacitor 
61 is coupled by means of an air bridge of metallization or gold-bond wire 
78B from the upper electrode 53 to the ion-implanted resistor 52. Active 
region 44 contains ion-implanted resistor 54. Ion-implanted reistor 54 is 
positioned between source electrode 50 and metallization 62. Metallization 
62 rests upon the upper surface 38 of the semi-insulating semi-conductor 
substrate 40. Metallization 62 contains via hole 64 which contacts base 
metallization 60 on lower surface 39 of the semi-insulating semi-conductor 
40. Metallization 62 is also positioned adjacent and extends over active 
region 44 and is therefore coupled to one side of resistor 54. 
A phase inverter circuit has been described for generating two output 
signals of equal amplitude having 180.degree. out-of-phase relationship 
from an input signal at microwave frequencies wherein the phase inverter 
circuit is fabricated on a semiconductor substrate such as gallium 
arsenide having a single field effect transistor such as a metal 
semiconductor field effect transistor with ion-implanted resistors coupled 
to the source and drain and to ground and a voltage supply, respectively. 
An ion-implanted resistor from ground to the gate electrode and from the 
gate electrode to a voltage source provides a means of providing a bias 
voltage to the gate. 
The phase inverter shown in FIG. 3 has the advantage of requiring only one 
power supply since the source electrode of transistor 46 is biased above 
ground potential by a source resistor 54. The drain power supply, 
V.sub.DS, with a voltage divider network shown by ion-implanted resistors 
73 and 74 allows a negative gate bias to be derived.