POWER AMPLIFIER

A power amplifier includes a first power transistor configured to amplify a first input radio-frequency (RF) signal and output a first output RF signal; a first transistor comprising a control terminal, a first terminal receiving a first voltage, and a second terminal supplying a first bias current to the first power transistor; a second power transistor configured to amplify a second input RF signal and output a second output RF signal; a second transistor comprising a control terminal, a first terminal receiving a second voltage, and a second terminal supplying a second bias current to the second power transistor; a signal detection circuit configured to detect a first value corresponding to a magnitude of either the first output RF signal or the second output RF signal; and a power supply voltage control circuit configured to adjust the first voltage and/or the second voltage in response to the first value.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 USC 119 (a) of Korean Patent Application Nos. 10-2023-0061588 filed on May 12, 2023, and 10-2023-0124048 filed on Sep. 18, 2023, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to a power amplifier.

2. Description of Related Art

Wireless communication systems apply various digital modulation and demodulation schemes according to the evolution of communication standards. The existing code-division multiple access (CDMA) communication system adopts the quadrature phase-shift keying (QPSK) method, and the existing wireless LAN following the IEEE communication standard adopts the orthogonal frequency-division multiplexing (OFDM) method. In addition, the long-term evolution (LTE) and LTE Advanced (LTE+ or LTE-A) standards, which are recent 3GPP standards, adopt QPSK, quadrature amplitude modulation (QAM), and OFDM schemes.

Transmitting devices used in wireless communication systems include a power amplifier that amplifies radio-frequency (RF) signals to increase a transmission distance.

If the voltage in the power amplifier exceeds a predetermined threshold level, a problem may occur in the power amplifier. To prevent this problem, the power amplifier may include a protection circuit. For example, in an AMR (absolute maximum rating) condition—that is, Pin (input power)=15 dBm, load VSWR (voltage standing wave ratio) 10:1, and all-phase condition—it may be necessary to protect the power amplifier. In other words, excessive current may flow under conditions where an excessive input RF signal is applied and the load changes significantly. At this time, a breakdown voltage or higher is applied to an element included in the power amplifier (for example, a power transistor), which may cause damage to the element.

SUMMARY

In one general aspect, power amplifier includes a first power transistor configured to amplify a first input radio-frequency (RF) signal and output a first output RF signal; a first transistor including a control terminal, a first terminal configured to receive a first voltage, and a second terminal configured to supply a first bias current to the first power transistor; a second power transistor configured to amplify a second input RF signal and output a second output RF signal; a second transistor including a control terminal, a first terminal configured to receive a second voltage, and a second terminal configured to supply a second bias current to the second power transistor; a signal detection circuit configured to detect a first value corresponding to a magnitude of either the first output RF signal or the second output RF signal; and a power supply voltage control circuit configured to adjust a third voltage in response to the first value, the third voltage being either one or both of the first voltage and the second voltage.

The power supply voltage control circuit may be further configured to decrease the third voltage in response to the first value being greater than a predetermined value, and either one or both of the first transistor and the second transistor may be configured to decrease either one or both of the first bias current and the second bias current in response to the third voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a first node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the third voltage may be a voltage at the first node where the first resistor and the second resistor are connected to each other.

The third transistor may be configured to turn on and decrease the third voltage in response to the first value being greater than a predetermined value.

The signal detection circuit may be further configured to detect an envelope of the first output RF signal or the second output RF signal and output the detected envelope as the first value.

The signal detection circuit may include an electrostatic discharge protection circuit including a plurality of diodes connected in series between an RF signal output terminal and the ground, the RF signal output terminal being a terminal of the first power transistor configured to output the first output RF signal or a terminal of the second power transistor configured to output the second output RF signal; and an envelope detection circuit configured to receive a first signal from a second node where two diodes of the plurality of diodes are connected to each other, detect an envelope of the first signal, and output the detected envelope of the first signal as the first value.

The envelope detection circuit may include a first diode having an anode connected to the second node; a capacitor connected between a cathode of the first diode and the ground; a third resistor having one end connected to the cathode of the first diode; and a fourth resistor connected between another end of the third resistor and the ground, and the control terminal of the third transistor may be connected to the other end of the third resistor.

The signal detection circuit may be further configured to detect a value corresponding to the magnitude of the first output RF signal as the first value, and the power supply voltage control circuit may be further configured to adjust the second voltage in response to the first value.

The power supply voltage control circuit may be further configured to decrease the second voltage in response to the first value being greater than a predetermined value, and the second transistor may be configured to decrease the second bias current in response to the second voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first terminal of the second transistor may be connected to the node where the first resistor and the second resistor are connected to each other.

The signal detection circuit may be further configured to detect a value corresponding to the magnitude of the second output RF signal as the first value, and the power supply voltage control circuit may be further configured to adjust the first voltage and the second voltage in response to the first value.

The power supply voltage control circuit may be further configured to decrease the first voltage and the second voltage in response to the first value being greater than a predetermined value, the first transistor may be configured to decrease the first bias current in response to the first voltage decreasing, and the second transistor may be configured to decrease the second bias current in response to the second voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first terminal of the first transistor and the first terminal of the second transistor may be connected to the node where the first resistor and the second resistor are connected to each other.

The signal detection circuit may be further configured to detect a value corresponding to the magnitude of the second output RF signal as the first value, and the power supply voltage control circuit may be further configured to adjust the second voltage in response to the first value.

The signal detection circuit may be further configured to decrease the second voltage in response to the first value being greater than a predetermined value, and the second transistor may be configured to decrease the second bias current in response to the second voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first terminal of the second transistor may be connected to the node where the first resistor and the second resistor are connected to each other.

The signal detection circuit may be further configured to detect a value corresponding to the magnitude of the second output RF signal as the first value, and the power supply voltage control circuit may be further configured to adjust the first voltage in response to the first value.

The power supply voltage control circuit may be further configured to decrease the first voltage in response to the first value being greater than a predetermined value, and the first transistor may be configured to decrease the first bias current in response to the first voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first terminal of the first transistor may be connected to the node where the first resistor and the second resistor are connected to each other.

The signal detection circuit may be further configured to detect a value corresponding to the magnitude of the first output RF signal as the first value, and the power supply voltage control circuit may be further configured to adjust the first voltage and the second voltage in response to the first value.

The power supply voltage control circuit may be further configured to decrease the first voltage and the second voltage in response to the first value being greater than a predetermined value, the first transistor may be configured to decrease the first bias current in response to the first voltage decreasing, and the second transistor may be configured to decrease the second bias current in response to the second voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first terminal of the first transistor and the first terminal of the second transistor may be connected to the node where the first resistor and the second resistor are connected to each other.

The signal detection circuit may be further configured to detect a value corresponding to the magnitude of the first output RF signal as the first value, and the power supply voltage control circuit may be further configured to adjust the first voltage in response to the first value.

The power supply voltage control circuit may be further configured to decrease the first voltage in response to the first value being greater than a predetermined value, and the first transistor may be configured to decrease the first bias current in response to the first voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a node; and a third transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first terminal of the first transistor may be connected to the node where the first resistor and the second resistor are connected to each other.

The second input RF signal may be the first output RF signal.

In another general aspect, a power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal and output an output RF signal; a first transistor including a control terminal, a first terminal configured to receive a first voltage, and a second terminal configured to supply a bias current to the power transistor; a signal detection circuit configured to detect a first value corresponding to a magnitude of the output RF signal; and a power supply voltage control circuit configured to adjust the first voltage in response to the first value.

The power supply voltage control circuit may be further configured to decrease the first voltage in response to the first value being greater than a predetermined value, and the first transistor may be configured to decrease the bias current in response to the first voltage decreasing.

The power supply voltage control circuit may include a first resistor connected to a first power supply voltage; a second resistor having one end connected to the first resistor at a first node; and a second transistor including a control terminal configured to receive the first value, a first terminal connected to another end of the second resistor, and a second terminal connected to a ground, and the first voltage may be a voltage at the first node where the first resistor and the second resistor are connected to each other.

The first terminal of the first transistor may be connected to the first node.

The second transistor may be configured to turn on and decrease the first voltage in response to the first value being greater than a predetermined value.

The signal detection circuit may be further configured to detect an envelope of the output RF signal as the first value.

The signal detection circuit may include an electrostatic discharge protection circuit including a plurality of diodes connected in series between an RF signal output terminal and the ground, the RF signal output terminal being a terminal of the power transistor configured to output the output RF signal; and an envelope detection circuit configured to receive a first signal from a second node where two diodes of the plurality of diodes are connected to each other, detect an envelope of the first signal, and output the detected envelope of the first signal as the first value.

The envelope detection circuit may include a first diode having an anode connected to the second node; a capacitor connected between a cathode of the first diode and the ground; a third resistor having one end connected to the cathode of the first diode; and a fourth resistor connected between another end of the third resistor and the ground, and the control terminal of the second transistor may be connected to the other end of the third resistor.

Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

FIG.1illustrates a power amplifier1000A according to an example.

As shown inFIG.1, the power amplifier1000A may include a power transistor100_1, a bias circuit200A_1, a capacitor C1, a power transistor100_2, a bias circuit200A_2, a capacitor C2, and a matching network300.

The power transistor100_1, the bias circuit200A_1, and the capacitor C1may constitute a first stage amplifier, and the power transistor100_2, the bias circuit200A_2, and the capacitor C2may constitute a second stage amplifier. The first stage amplifier may be a driver amplifier, and the second stage amplifier may be a power amplifier.

The power transistor100_1may include an input terminal and an output terminal. The input terminal may be the base of the power transistor100_1, and the output terminal may be the collector of the power transistor100_1. The power transistor100_1may amplify a power of an input RF signal RFIN1input to the input terminal (for example, the base) and output the amplified power to the output terminal (for example, the collector). InFIG.1, the RF signal output from the output terminal of the power transistor100_1is indicated as “output RF signal RFOUT1”. An emitter of the power transistor100_1may be connected to a ground, and although not shown inFIG.1, a resistor may be connected between the emitter of the power transistor100_1and the ground. In addition, the collector of the power transistor100_1may be connected to a power supply voltage VCC1, and the power transistor100_1may be operated by the power supply voltage VCC1. Although not shown inFIG.1, an inductor that performs an RF choke function may be connected between the collector of the power transistor100_1and the power supply voltage VCC1.

The power transistor100_1may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Although the power transistor100_1is shown as an n-type transistor inFIG.1, it may be replaced with a p-type transistor.

The capacitor C1is a coupling capacitor, and may be connected to the input terminal (for example, the base) of the power transistor100_1. That is, the input RF signal RFIN1may be input to one end of the capacitor C1, and the other end of the capacitor C1may be connected to the base of the power transistor100_1. The capacitor C1may perform a function of blocking a direct current (DC) component in the input RF signal RFIN1.

The bias circuit200A_1may receive a reference current IREF1and a power supply voltage VBAT1from an external source. The bias circuit200A_1may generate a bias current IBIAS1_Arequired by the power transistor100_1using the reference current IREF1and the power supply voltage VBAT1. The bias current IBIAS1_Ais supplied to the input terminal (for example, the base) of the power transistor100_1, and a bias level (a bias point) of the power transistor100_1may be set by the bias current IBIAS1_A. The power supply voltage VBAT1may be a voltage supplied from a battery.

The power transistor100_2may include an input terminal and an output terminal. The input terminal may be the base of the power transistor100_2, and the output terminal may be the collector of the power transistor100_2. The power transistor100_2may amplify a power of an input RF signal RFIN2input to the input terminal (for example, the base) and output the amplified power to the output terminal (for example, the collector). InFIG.1, the RF signal output from the output terminal of the power transistor100_2is indicated as “output RF signal RFOUT2”. An emitter of the power transistor100_2may be connected to the ground, and although not shown inFIG.1, a resistor may be connected between the emitter of the power transistor100_2and the ground. In addition, the collector of the power transistor100_2may be connected to a power supply voltage VCC2, and the power transistor100_2may be operated by the power supply voltage VCC2. Although not shown inFIG.1, an inductor that performs an RF choke function may be connected between the collector of the power transistor100_2and the power supply voltage VCC2. The power supply voltage VCC2and the power supply voltage VCC1may be provided from the same source or different sources.

The power transistor100_2may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Although the power transistor100_2is shown as an n-type transistor inFIG.1, it may be replaced with a p-type transistor.

The matching network300may be connected between the output terminal (for example, the collector) of the power transistor100_1and the input terminal (for example, the base) of the power transistor100_2. The matching network300performs impedance matching between the output RF signal RFOUT1and the input terminal of the power transistor100_2. The matching network300may be implemented by any one or any combination of any two or more of a resistor, an inductor, and a capacitor.

The capacitor C2is a coupling capacitor and may be connected between the matching network300and the input terminal (for example, the base) of the power transistor100_2. The output RF signal RFOUT1may be input to the input terminal (the base) of the power transistor100_2through the matching network300and the capacitor C2. From an RF signal perspective, the output RF signal RFOUT1of the first stage amplifier may be the input RF signal RFIN2of the second stage amplifier. The capacitor C2may perform a function of blocking a direct current (DC) component in the input RF signal RFIN2.

When an excessive peak voltage is applied to an element (for example, the power transistor100_1) included in the power amplifier1000A (that is, in an abnormal state), the power amplifier1000A according to an example performs a protection operation.

To perform this protection operation, the power amplifier1000A according to an example may further include a signal detection circuit400A and a power supply voltage control circuit500A.

The signal detection circuit400A may receive the output RF signal RFOUT1and detect the magnitude of the output RF signal RFOUT1. The magnitude of the output RF signal RFOUT1may correspond to the peak voltage of the output RF signal RFOUT1or may correspond to the power of the output RF signal RFOUT1. The signal detection circuit400A may generate a detection voltage VDET1corresponding to the magnitude of the output RF signal RFOUT1. In more detail, the signal detection circuit400A may detect the envelope of the output RF signal RFOUT1and generate and output the detection voltage VDET1corresponding to the detected envelope. The specific configuration and operation of the signal detection circuit400A will be described in detail with respect toFIG.3.

The power supply voltage control circuit500A may receive a power supply voltage VBAT2from an external source and receive the detection voltage VDET1from the signal detection circuit400A. The power supply voltage VBAT2may be supplied from a battery and may be the same voltage as or a different voltage from the power supply voltage VBAT1. The power supply voltage control circuit500A uses the power supply voltage VBAT2and the detection voltage VDET1to generate a control power supply voltage VBAT2_CTRL, and the generated control power supply voltage VBAT2_CTRLmay be output to the bias circuit200A_2. That is, the power supply voltage control circuit500A can adjust (change) the control power supply voltage VBAT2_CTRL, which is a power supply voltage to be supplied to the bias circuit200A_2, in response to the detection voltage VDET1.

As an example, the control power supply voltage VBAT2_CTRLmay have two voltage levels. When the detection voltage VDET1has a value higher than a predetermined voltage level, the power supply voltage control circuit500A may generate the control power supply voltage VBAT2_CTRLhaving a first voltage level. When the detection voltage VDET1has a value less than the predetermined voltage level, the power supply voltage control circuit500A may generate the control power supply voltage VBAT2_CTRLhaving a second voltage level. The first voltage level may be a voltage level lower than the second voltage level. When the output RF signal RFOUT1is excessive, the detection voltage VDET1has a value above the predetermined voltage level, so hereinafter, the control power supply voltage VBAT2_CTRLhaving the first voltage level is referred to as “abnormal control power supply voltage VBAT2_CTRL_ABNORMAL”. When the output RF signal RFOUT1is not excessive, the detection voltage VDET1has a value below the predetermined voltage level, so hereinafter, the control power supply voltage VBAT2_CTRLhaving the second voltage level is referred to as “normal control power supply voltage VBAT2_CTRL_NORMAL”.

The bias circuit200A_2may receive the control power supply voltage VBAT2_CTRLfrom the power supply voltage control circuit500A and receive a reference current IREF2from an external source. The bias circuit200A_2may generate a bias current IBIAS2_Arequired by the power transistor100_2using the control power supply voltage VBAT2_CTRLand the reference current IREF2. The bias current IBIAS2_Ais supplied to the input terminal (for example, the base) of the power transistor100_2, and a bias level (a bias point) of the power transistor100_2may be set by the bias current IBIAS2_A.

When the control power supply voltage VBAT2_CTRLis the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL, the bias circuit200A_2may generate an abnormal bias current IBIAS2_A_ABNORMAL. When the control power supply voltage VBAT2_CTRLis the normal control supply power voltage VBAT2_CTRL_NORMAL, the bias circuit200A_2may generate a normal bias current IBIAS2_A_NORMAL. The abnormal bias current IBIAS2_A_ABNORMALhas a lower current value than the normal bias current IBIAS2_A_NORMAL. Due to the abnormal bias current IBIAS2_A_ABNORMALhaving a low current value, the power transistor100_2performs an amplification operation with a low gain, and the power amplifier1000A may be protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS2_A_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS2_A_ABNORMALis 0 mA, the power transistor100_2does not perform an amplification operation, so the power amplifier1000A may be protected from an excessive peak voltage.

FIG.2is a circuit diagram showing an example of the bias circuit200A_1ofFIG.1.

As shown inFIG.2, the bias circuit200A_1may include a transistor Q1, a transistor Q2, a transistor QB1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a capacitor C3.

The transistors Q1, Q2, QB1may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the transistors Q1, Q2, QB1are shown as n-type transistors inFIG.2, they may be replaced with p-type transistors. Since the bases of the transistors Q1, Q2, QB1serve as control terminals, the term “control terminal” may be used. Since the collectors of the transistors Q1, Q2, QB1are one terminal of the transistor, the term “first terminal” or “second terminal” may be used. In addition, since the emitters of the transistors Q1, Q2, QB1are also one terminal of the transistor, the term “second terminal” or “first terminal” may be used.

A base and a collector of the transistor Q1may be connected to each other in a diode-connected structure, and the collector of the transistor Q1may receive the reference current IREF1through the resistor R1. The transistor Q1serves to sink a current I2from the reference current IREF1. The reference current IREF1may be a current source.

A base and a collector of the transistor Q2may be connected to each other in a diode-connected structure, and the collector of the transistor Q2may be connected to the emitter of the transistor Q1. An emitter of the transistor Q2may be connected to a ground through the resistor R2.

A collector of the transistor QB1may be connected to the power supply voltage VBAT1through the resistor R3, and a base of the transistor QB1may be connected to the base of the transistor Q1. In addition, an emitter of the transistor QB1may be connected to the input terminal (for example, the base) of the power transistor100_1through the resistor R4. A current flowing through the emitter of the transistor QB1is the bias current IBIAS1_Adescribed with respect toFIG.1. The collector of the transistor QB1is a terminal that receives the power supply voltage VBAT1, and the emitter of the transistor QB1is a terminal that supplies the bias current IBIAS1_Ato the power transistor100_1.

The capacitor C3may be connected between the base of the transistor QB1and the ground. The capacitor C3may stabilize a base voltage of the transistor QB1and reduce an impedance of the transistor QB1.

The reference current IREF1is divided into a current I1and the current I2, and the current I1may be input to the base of the transistor QB1. Accordingly, the bias current IBIAS1_Amay be determined corresponding to the current I1. The bias current IBIAS1_Amay also be determined corresponding to the base voltage of the transistor QB1.

FIG.3is a circuit diagram showing internal configurations of the signal detection circuit400A, the power supply voltage control circuit500A, and the bias circuit200A_2ofFIG.1.

As shown inFIG.3, the signal detection circuit400A according to an example may include an electrostatic discharge (ESD) protection circuit410A and an envelope detection circuit420A.

The electrostatic discharge protection circuit410A may be connected to the point where power is supplied from an external source and may block an excessive voltage or current. Since the power supply voltage VCC1is supplied from an external source to the output terminal of the power transistor100_1, the electrostatic discharge protection circuit410A may be connected between the output terminal (for example, the collector) of the power transistor100_1and a ground. As shown inFIG.3, the electrostatic discharge protection circuit410A according to an example may include a plurality of forward-biased diodes D_F and a plurality of reverse-biased diodes D_R. When an excessive voltage or current is input, the plurality of forward-biased diodes D_F or the plurality of reversed-biased diodes D_R are turned on. Accordingly, the power transistor100_1may be protected. The plurality of forward-biased diodes D_F include a plurality of diodes connected in series in a forward direction, and the plurality of reversed-biased diodes D_R include a plurality of diodes connected in series in a reverse direction. InFIG.3, a node where at least two diodes are connected to each other among the plurality of forward-biased diodes D_F is indicated as “node N1”.

The envelope detection circuit420A may detect the envelope of the RF signal corresponding to the output RF signal RFOUT1and may generate the detection voltage VDET1corresponding to the detected envelope. As shown inFIG.3, the envelope detection circuit420A according to an example may include a diode D1, a capacitor C4, a resistor R5, and a resistor R6.

An anode of the diode D1may be connected to the node N1, and the capacitor C4may be connected between a cathode of the diode D1and the ground. One end of the resistor R5may be connected to the cathode of the diode D1, and the resistor R6may be connected between the other end of the resistor R5and the ground. The voltage at the node where the resistor R5and the resistor R6are connected to each other corresponds to the detection voltage VDET1described above.

When an electrostatic discharge (ESD) is applied to the electrostatic discharge protection circuit410A, the plurality of forward-biased diodes D_F or the plurality of reversed-biased diodes D_R may be turned on. At this time, since the current flows to the ground, the electrostatic discharge protection circuit410A operates and the power transistor100_1can be protected. A voltage (potential) of the node N1may be equal to a voltage of the ground.

When an ESD is not applied to the electrostatic discharge protection circuit410A, the electrostatic discharge protection circuit410A does not operate. In other words, the plurality of forward-biased diodes D_F and the plurality of reversed-biased diodes D_R are turned off. Even when an ESD is not applied, damage to devices may occur due to an excessive RF signal input and an excessive load mismatch. To prevent this, the power amplifier1000A according to one example performs a protection operation.

When the electrostatic discharge protection circuit410A does not operate (that is, the plurality of forward-biased diodes D_F and the plurality of reversed-biased diodes D_R do not turn on), an RF signal corresponding to the output RF signal RFOUT1may appear (be generated) at the node N1. When the electrostatic discharge protection circuit410A does not operate, a voltage swing of the output RF signal RFOUT1is equally distributed across the plurality of forward-biased diodes D_F, and the voltage swing level appears differently depending on the location of the node N1. That is, an RF signal corresponding to the output RF signal RFOUT1may appear at the node N1. Hereinafter, the RF signal appearing at the node N1is referred to as the “detection RF signal” and it is indicated as “RFOUT1_DET” inFIG.3. When the plurality of forward-biased diodes D_F and the plurality of reversed-biased diodes D_R are in the off state, a current does not flow, so the electrostatic discharge protection circuit410A has an infinite impedance (that is, is in an open state). Due to this infinite impedance, the detection RF signal RFOUT1_DETmay not affect the output RF signal RFOUT1.

The detection RF signal RFOUT1_DETis input to the envelope detection circuit420A. The diode D1and the capacitor C4of the envelope detection circuit420A operate as a rectifier circuit. That is, the envelope of the detection RF signal RFOUT1_DETmay be detected by the diode D1and the capacitor C4. The detected envelope is divided by the resistor R5and the resistor R6, and the detection voltage VDET1corresponding to the detected envelope may be generated. That is, the envelope detection circuit420A converts the detection RF signal RFOUT1_DETinto the detection voltage VDET1. The level of the detection voltage VDET1may be adjusted by the values of the resistor R5and the resistor R6.

When the magnitude of the input RF signal RFIN1increases, the magnitude of the output RF signal RFOUT1also increases. When the magnitude of the output RF signal RFOUT1increases, the magnitude of the detection RF signal RFOUT1_DETalso increases. Due to an increase in the magnitude of the detection RF signal RFOUT1_DET, the detection voltage VDET1also increases. In other words, the detection voltage VDET1increases in proportion to the magnitude of the input RF signal RFIN1.

FIG.4Ais a graph showing an example of the input RF signal RFIN1ofFIG.1, andFIG.4Bis a graph showing simulation results of the detection voltage VDET1ofFIG.1for the input RF signal RFIN1ofFIG.4A.

When the input RF signal RFIN1is S410ainFIG.4A, the detection voltage VDET1is S410binFIG.4B. When the input RF signal RFIN1is S420ainFIG.4A, the detection voltage VDET1is S420binFIG.4B. In other words, the detection voltage VDET1may increase in proportion to the magnitude (power) of the input RF signal RFIN1.

As shown inFIG.3, the power supply voltage control circuit500A according to an example may include a transistor Q3, a resistor R7, and a resistor R8.

The transistor Q3may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the transistor Q3is shown as an n-type transistor inFIG.3, it may be replaced with a p-type transistor. Since the base of the transistor Q3serves as a control terminal, the term “control terminal” may be used. Since the collector of the Q3is one terminal of the transistor, the term “first terminal” or “second terminal” may be used. In addition, since the emitter of the transistor Q3is also one terminal of the transistor, the term “second terminal” or “first terminal” may be used.

The base of the transistor Q3may be connected to the other end of the resistor R5and may receive the detection voltage VDET1. That is, the base of the transistor Q3may be connected to the node where the resistor R5and the resistor R6are connected to each other. The emitter of the transistor Q3may be connected to the ground. The collector of the transistor Q3may be connected to the power supply voltage VBAT2through the resistor R8and the resistor R7.

One end of the resistor R7may be connected to the power supply voltage VBAT2, and the resistor R8may be connected between the other end of the resistor R7and the collector of the transistor Q3. The voltage at the node where the resistor R7and the resistor R8are connected to each other is the control power supply voltage VBAT2_CTRLdescribed above. The control power supply voltage VBAT2_CTRLmay change depending on whether the transistor Q3is turned on. Since the detection voltage VDET1is input to the base of the transistor Q3, the transistor Q3may be turned on or off depending on the level of the detection voltage VDET1.

When the detection voltage VDET1is above a predetermined level, the transistor Q3turns on. When the detection voltage VDET1is above the predetermined level, the output RF signal RFOUT1is excessive (abnormal). That is, this is a case in which the protection operation is performed. When performing a protection operation, the magnitude of the output RF signal RFOUT1may be set in advance, and the level of the corresponding detection voltage VDET1may be adjusted according to the values of the resistor R5and the resistor R6.

When the transistor Q3is turned on, the control power supply voltage VBAT2_CTRLmay have the first voltage level. That is, the control power supply voltage VBAT2_CTRLbecomes the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL. The abnormal control power supply voltage VBAT2_CTRL_ABNORMALmay have a value expressed by Equation 1 below.

In Equation 1 above, it is assumed that the collector-emitter voltage of the transistor Q3is 0 V when the transistor Q3is turned on.

When the detection voltage VDET1is below the predetermined level, the transistor Q3turns off. When the detection voltage VDET1is less than the predetermined level, the output RF signal RFOUT1is not excessive (normal). That is, this is a case in which the protection operation is not performed.

When the transistor Q3is turned off, the control power supply voltage VBAT2_CTRLmay have the second voltage level. That is, the control power supply voltage VBAT2_CTRLbecomes the normal control power voltage VBAT2_CTRL_NORMAL. The normal control power supply voltage VBAT2_CTRL_NORMALmay have a value expressed by Equation 2 below.

In Equation 2 above, IR7represents the current flowing through the resistor R7when the transistor Q3is turned off.

FIG.5is a graph showing a simulation result of the control power supply voltage VBAT2_CTRLOfFIG.1.

InFIG.5, the horizontal axis represents the input RF signal RFIN1, and the vertical axis represents the control power supply voltage VBAT2_CTRL. In the simulation ofFIG.5, it is assumed that the power supply voltage VBAT2is 3.8 V.

When the input RF signal RFIN1is less than −2 dBm, the transistor Q3is turned off. This is a normal operating state in which the protection operation is not performed. Referring to S510inFIG.5, the control power supply voltage VBAT2_CTRLhas a minimum value of 3.557 V and is less than 3.8 V.

The protection operation begins when the input RF signal RFIN1exceeds −2 dBm, and current begins to flow to the transistor Q3. That is, when the input RF signal RFIN1is more than −2 dBm, the transistor Q3is turned on, and the control power supply voltage VBAT2_CTRLdecreases (becomes lower). Referring to S520inFIG.5, the control power supply voltage VBAT2_CTRLhas a value of 0.35 V. Although it is not clearly shown in the graph ofFIG.5, 0.35 V is confirmed when taking a picture of the S520part in the simulation.

According to the simulation result ofFIG.5, the normal control power supply voltage VBAT2_CTRL_NORMALmay have a value from 3.557 V to less than 3.8 V, and the abnormal control power supply voltage VBAT2_CTRL_ABNORMALmay have a value of 0.35 V. Accordingly, the abnormal control power supply voltage VBAT2_CTRL_ABNORMALhas a lower value than the normal control power supply voltage VBAT2_CTRL_NORMAL. In other words, when the protection operation is performed, the transistor Q3is turned on, which causes the control power supply voltage VBAT2_CTRLto decrease (become lower).

As shown inFIG.3, the bias circuit200A_2according to an example may include a transistor Q4, a transistor Q5, a transistor QB2, a resistor R10, a resistor R11, a resistor R12, and a capacitor C5.

The transistors Q4, Q5, QB2may be implemented by various types of transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the transistors Q4, Q5, QB2are shown as n-type transistors inFIG.3, they may be replaced with p-type transistors. Since the bases of the transistors Q4, Q5, QB2serve as control terminals, the term “control terminal” may be used. Since the collectors of the transistors Q4, Q5, QB2are one terminal of the transistor, the term “first terminal” or “second terminal” may be used. In addition, since the emitters of the transistors Q4, Q5, QB2are also one terminal of the transistor, the term “second terminal” or “first terminal” may be used.

A base and a collector of the transistor Q4may be connected to each other in a diode-connected structure, and the collector of the transistor Q4may receive the reference current IREF2through the resistor R10. The transistor Q4serves to sink a current I4from the reference current IREF2. The reference current IREF2may be a current source.

A base and a collector of the transistor Q5may be connected to each other in a diode-connected structure, and the collector of the transistor Q5may be connected to the emitter of the transistor Q4. An emitter of the transistor Q5may be connected to the ground through the resistor R11.

A collector of the transistor QB2may receive the control power supply voltage VBAT2_CTRL. That is, the collector of the transistor QB2may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB2may be connected to the base of the transistor Q4. An emitter of the transistor QB2may be connected to the input terminal (for example, the base) of the power transistor100_2through the resistor R12. The current flowing through the emitter of the transistor QB2is the bias current IBIAS2_Adescribed with respect toFIG.1. The collector of the transistor QB2is a terminal that receives the control power supply voltage VBAT2_CTRL, which is a power supply voltage, and the emitter of the transistor QB2is a terminal that supplies the bias current IBIAS2_Ato the power transistor100_2.

The capacitor C5can be connected between the base of the transistor QB2and the ground. The capacitor C5may stabilize a base voltage of the transistor QB2and reduce an impedance of the transistor QB2.

The reference current IREF2is divided into a current I3and the current I4, and the current I3may be input to the base of the transistor QB2. Accordingly, the bias current IBIAS2_Amay be determined corresponding to the current I3. Also, the bias current IBIAS2_Amay be determined corresponding to the base voltage of the transistor QB2.

The bias current IBIAS2_Amay change based on the control power supply voltage VBAT2_CTRL. When the control power supply voltage VBAT2_CTRLdecreases (becomes lower), the bias current IBIAS2_Aalso decreases. As an example, when the control power supply voltage VBAT2_CTRLis lower than a predetermined threshold voltage, the transistor QB2does not operate (that is, the transistor QB2is turned off), which may cause the bias current IBIAS2_Ato be 0 mA.

When the control power supply voltage VBAT2_CTRLis the normal control power supply voltage VBAT2_CTRL_NORMAL, the transistor QB2receives a normal power voltage. Due to this, the bias current IBIAS2_Aalso has a normal value. In other words, the bias circuit200A_2generates the normal bias current IBIAS2_A_NORMAL. Due to the normal bias current IBIAS2_A_NORMAL, the power transistor100_2may perform a normal amplification operation.

When the transistor Q3is turned on due to an excessive output RF signal RFOUT1, the control power supply voltage VBAT2_CTRLbecomes the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL. The transistor QB2receives the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL, which reduces the bias current IBIAS2_A. In other words, the bias circuit200A_2generates the abnormal bias current IBIAS2_A_ABNORMAL. Due to the abnormal bias current IBIAS2_A_ABNORMAL, the peak voltage applied to the power transistor100_2does not exceed a breakdown voltage. Through this, the power amplifier1000A may be protected from excessive RF signals.

As described above, the power amplifier1000A according to an example performs the protection operation only when the output RF signal RFOUT1is excessive (that is, abnormal) and does not perform the protection operation otherwise. That is, the transistor Q3ofFIG.3is turned on only when the output RF signal RFOUT1is excessive (that is, abnormal); otherwise it remains turned off. Since the transistor Q3does not continuously turn on and off, spurs due to oscillation may not occur.

FIG.6illustrates a power amplifier1000A′ according to another example.

The power amplifier1000A′ ofFIG.6is the same as the power amplifier1000A ofFIGS.1to3except that the signal detection circuit400A inFIGS.1and3is changed to the signal detection circuit400A′ inFIG.6. Accordingly, overlapping descriptions are omitted.

As shown inFIG.6, in the signal detection circuit400A′ according to another example, the electrostatic discharge protection circuit410A ofFIG.3is replaced with a capacitor C6. One end of the capacitor C6may be connected to the collector of the power transistor100_1, and the other end of capacitor C6may be connected to the anode of the diode D1. The capacitor C6couples and outputs a portion of the output RF signal RFOUT1to the anode of the diode D1as a detection RF signal RFOUT1_DET′.

The capacitor C6outputs the detection RF signal RFOUT1_DET′ as a coupled signal to the envelope detection circuit420A. In other words, the detection RF signal RFOUT1_DET′ is input to the anode of the diode D1. The envelope detection circuit420A detects an envelope of the detection RF signal RFOUT1_DET′ and generates a detection voltage VDET1corresponding to the detected envelope.

FIG.7illustrates a power amplifier1000B according to another example.

As shown inFIG.7, the power amplifier1000B according to another example may include a power transistor100_1, a bias circuit200B_1, a capacitor C1, a power transistor100_2, a bias circuit200B_2, a capacitor C2, and a matching network300. Since the power amplifier1000B ofFIG.7is similar to the power amplifier1000A ofFIG.1, overlapping descriptions may be omitted.

The bias circuit200B_1may receive a control power supply voltage VBAT12_CTRLfrom a power supply voltage control circuit500B and may receive the reference current IREF1from an external source. The bias circuit200B_1may generate a bias current IBIAS1_Brequired by the power transistor100_1using the control power supply voltage VBAT12_CTRLand the reference current IREF1. The bias current IBIAS1_Bis supplied to the input terminal (for example, the base) of the power transistor100_1, and the bias level (a bias point) of the power transistor100_1may be set by the bias current IBIAS1_B.

The bias circuit200B_2may receive the control power supply voltage VBAT12_CTRLfrom the power supply voltage control circuit500B and may receive a reference current IREF2from an external source. The bias circuit200B_2may generate a bias current IBIAS2_Brequired by the power transistor100_2using the control power supply voltage VBAT12_CTRLand the reference current IREF2. The bias current IBIAS2_Bis supplied to the input terminal (for example, the base) of the power transistor100_2, and the bias level (a bias point) of the power transistor100_2may be set by the bias current IBIAS2_B.

When an excessive peak voltage is applied to an element (for example, the power transistor100_2) included in the power amplifier1000B (that is, in an abnormal state), the power amplifier1000B according to another example performs a protection operation. To perform this protection operation, the power amplifier1000B according to another example may further include a signal detection circuit400B and the power supply voltage control circuit500B.

The signal detection circuit400B may receive the output RF signal RFOUT2and detect the magnitude of the output RF signal RFOUT2. The magnitude of the output RF signal RFOUT2may correspond to the peak voltage of the output RF signal RFOUT2or may correspond to the power of the output RF signal RFOUT2. The signal detection circuit400B may generate a detection voltage VDET2corresponding to the magnitude of the output RF signal RFOUT2. In more detail, the signal detection circuit400B may detect the envelope of the output RF signal RFOUT2and generate and output the detection voltage VDET2corresponding to the detected envelope. That is, the signal detection circuit400B ofFIG.7is similar to the signal detection circuit400A ofFIG.1except that it receives the output RF signal RFOUT2. The specific configuration and operation of the signal detection circuit400B will be described in detail with respect toFIG.8.

The power supply voltage control circuit500B may receive a power supply voltage VBATfrom an external source and receive the detection voltage VDET2from the signal detection circuit400B. The power supply voltage VBATmay be supplied from a battery. The power supply voltage control circuit500B uses the power supply voltage VBATand the detection voltage VDET2to generate a control power supply voltage VBAT12_CTRL, and the generated control power supply voltage VBAT12_CTRLmay be output to the bias circuit200B_1and the bias circuit200B_2. That is, the power supply voltage control circuit500B can adjust (change) the control power supply voltage VBAT12_CTRL, which is a power supply voltage to be supplied to the bias circuit200B_1and the bias circuit200B_2, in response to the detection voltage VDET2.

Similar to the control power supply voltage VBAT2_CTRLofFIG.1, the control power supply voltage VBAT12_CTRLofFIG.7may have two voltage levels. When the detection voltage VDET2has a value higher than a predetermined voltage level, the power supply voltage control circuit500B may generate the control power supply voltage VBAT12_CTRLhaving a third voltage level. When the detection voltage VDET2has a value less than the predetermined voltage level, the power supply voltage control circuit500B may generate the control power supply voltage VBAT2_CTRLhaving a fourth voltage level. The third voltage level may be a voltage level lower than the fourth voltage level. When the output RF signal RFOUT2is excessive, the detection voltage VDET2has a value above the predetermined voltage level, so hereinafter, the control power supply voltage VBAT12_CTRLhaving the third voltage level is referred to as “abnormal control power supply voltage VBAT12_CTRL_ABNORMAL”. When the output RF signal RFOUT2is not excessive, the detection voltage VDET2has a value below the predetermined voltage level, so hereinafter, the control power supply voltage VBAT12_CTRLhaving the fourth voltage level is referred to as “normal control power supply voltage VBAT12_CTRL_NORMAL”.

When the control power supply voltage VBAT12_CTRLis the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL, the bias circuit200B_1may generate an abnormal bias current IBIAS1_B_ABNORMAL. When the control power supply voltage VBAT12_CTRLis the normal control supply power voltage VBAT12_CTRL_NORMAL, the bias circuit200B_1may generate a normal bias current IBIAS1_B_NORMAL. The abnormal bias current IBIAS1_B_ABNORMALhas a lower current value than the normal bias current IBIAS1_B_NORMAL. Due to the abnormal bias current IBIAS1_B_ABNORMALhaving a low current value, the power transistor100_1performs an amplification operation with a low gain, and the power amplifier1000B may be protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS1_B_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS1_B_ABNORMALis 0 mA, the power transistor100_1does not perform an amplification operation, so the power amplifier1000B may be protected from an excessive peak voltage.

When the control power supply voltage VBAT12_CTRLis the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL, the bias circuit200B_2may generate an abnormal bias current IBIAS2_B_ABNORMAL. When the control power supply voltage VBAT12_CTRLis the normal control supply power voltage VBAT12_CTRL_NORMAL, the bias circuit200B_2may generate a normal bias current IBIAS2_B_NORMAL. The abnormal bias current IBIAS2_B_ABNORMALhas a lower current value than the normal bias current IBIAS2_B_NORMAL. Due to the abnormal bias current IBIAS2_B_ABNORMALhaving a low current value, the power transistor100_2performs an amplification operation with a low gain, and the power amplifier1000B may be protected from an excessive peak voltage. That is, not only the power transistor100_1but also the power transistor100_2performs an amplification operation with a low gain, and the power amplifier1000B may be further protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS2_B_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS2_B_ABNORMALis 0 mA, the power transistor100_2does not perform an amplification operation, so the power amplifier1000B may be protected from an excessive peak voltage.

FIG.8is a circuit diagram showing internal configurations of the bias circuit200B_1, the signal detection circuit400B, the power supply voltage control circuit500B, and the bias circuit200B_2ofFIG.7.

As shown inFIG.8, the bias circuit200B_1may include a transistor Q1, a transistor Q2, a transistor QB1, a resistor R1, a resistor R2, a resistor R4, and a capacitor C3. Since the bias circuit200B_1ofFIG.8is similar to the bias circuit200A_1ofFIG.2except for the connection relationship of the transistor QB1, overlapping descriptions may be omitted.

A collector of the transistor QB1may receive the control power supply voltage VBAT12_CTRL. That is, the collector of the transistor QB1may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB1may be connected to a base of the transistor Q1. An emitter of the transistor QB1may be connected to the input terminal (for example, the base) of the power transistor100_1through the resistor R4. The current flowing through the emitter of the transistor QB1is the bias current IBIAS1_Bdescribed with respect toFIG.7above. The collector of the transistor QB1is a terminal that receives the control power supply voltage VBAT12_CTRL, which is a power supply voltage, and the emitter of the transistor QB1is a terminal that supplies the bias current IBIAS1_Bto the power transistor100_1.

As shown inFIG.8, the signal detection circuit400B according to another example may include an electrostatic discharge (ESD) protection circuit410B and an envelope detection circuit420B. The signal detection circuit400B ofFIG.8is similar to the signal detection circuit400A ofFIG.3except that it detects the magnitude of the output RF signal RFOUT2and generates the detection voltage VDET2. Accordingly, overlapping descriptions may be omitted.

Since the power supply voltage VCC2is supplied from an external source to the output terminal of the power transistor100_2, the electrostatic discharge protection circuit410B may be connected between the output terminal (for example, the collector) of the power transistor100_2and the ground. As shown inFIG.8, the electrostatic discharge protection circuit410B according to another example may include a plurality of forward-biased diodes D_F and a plurality of reversed-biased diodes D_R. When an excessive voltage or current is input, the plurality of forward-biased diodes D_F or the plurality of reversed-biased diodes D_R is turned on. Accordingly, the power transistor100_2may be protected. The plurality of forward-biased diodes D_F includes a plurality of diodes connected in series in a forward direction, and the plurality of reversed-biased diodes D_R includes a plurality of diodes connected in series in a reverse direction. InFIG.8, a node where at least two diodes are connected to each other among the plurality of forward-biased diodes D_F is indicated as “node N2”.

The envelope detection circuit420B may detect the envelope of the RF signal corresponding to the output RF signal RFOUT2and may generate the detection voltage VDET2corresponding to the detected envelope. As shown inFIG.8, the envelope detection circuit420B according to another example may include a diode D1, a capacitor C4, a resistor R5, and a resistor R6.

An anode of the diode D1may be connected to the node N2, and the voltage at the node where the resistor R5and the resistor R6are connected to each other corresponds to the detection voltage VDET2described above. When the electrostatic discharge protection circuit410B does not operate (that is, the plurality of forward-biased diodes D_F and the plurality of reversed-biased diodes D_R do not turn on), an RF signal corresponding to the output RF signal RFOUT2may appear (that is, be generated) at the node N2. InFIG.8, the RF signal appearing at the node N2is indicated as “detection RF signal RFOUT2_DET.”

Since the electrostatic discharge protection circuit410B has an infinite impedance (that is, it is in an open state), the detection RF signal RFOUT2_DETmay not affect the output RF signal RFOUT2.

The detection RF signal RFOUT2_DETis input to the envelope detection circuit420B. The diode D1and the capacitor C4of the envelope detection circuit420B operate as a rectifier circuit. That is, the envelope of the detection RF signal RFOUT2_DETmay be detected by the diode D1and the capacitor C4. The detected envelope is divided by the resistor R5and the resistor R6, and the detection voltage VDET2corresponding to the detected envelope may be generated. That is, the envelope detection circuit420B converts the detection RF signal RFOUT2_DETinto the detection voltage VDET2. The level of the detection voltage VDET2may be adjusted by the values of the resistor R5and the resistor R6.

When the magnitude of the input RF signal RFIN2increases, the magnitude of the output RF signal RFOUT2also increases. When the magnitude of the output RF signal RFOUT2increases, the magnitude of the detection RF signal RFOUT2_DETalso increases. Due to an increase in the magnitude of the detection RF signal RFOUT2_DET, the detection voltage VDET2also increases. In other words, the detection voltage VDET2increases in proportion to the magnitude of the input RF signal RFIN2.

As shown inFIG.8, the power supply voltage control circuit500B may include a transistor Q3, a resistor R7, and a resistor R8.

A base of the transistor Q3may be connected to the other end of the resistor R5and may receive the detection voltage VDET2. That is, the base of the transistor Q3may be connected to the node where the resistor R5and the resistor R6are connected to each other. An emitter of the transistor Q3may be connected to the ground. A collector of the transistor Q3may be connected to the power supply voltage VBATthrough the resistor R8and the resistor R7.

One end of the resistor R7may be connected to the power supply voltage VBAT, and the resistor R8may be connected between the other end of the resistor R7and the collector of the transistor Q3. The voltage at the node where the resistor R7and the resistor R8are connected to each other is the control power supply voltage VBAT12_CTRLdescribed above. The control power supply voltage VBAT12_CTRLmay change depending on whether the transistor Q3is turned on. Since the detection voltage VDET2is input to the base of the transistor Q3, the transistor Q3may be turned on or off depending on the level of the detection voltage VDET2.

When the detection voltage VDET2is above a predetermined level, the transistor Q3turns on. When the detection voltage VDET2is above the predetermined level, the output RF signal RFOUT2is excessive (abnormal). That is, this is a case in which the protection operation is performed. When performing a protection operation, the magnitude of the output RF signal RFOUT2may be set in advance, and the level of the corresponding detection voltage VDET2may be adjusted according to the values of the resistor R5and the resistor R6.

When the transistor Q3is turned on, the control power supply voltage VBAT12_CTRLmay have the third voltage level. That is, the control power supply voltage VBAT12_CTRLbecomes the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL. Similar to Equation 1 above, the abnormal control power supply voltage VBAT12_CTRL_ABNORMALmay have a value expressed by Equation 3 below.

In Equation 3 above, it is assumed that the collector-emitter voltage of the transistor Q3is 0 V when the transistor Q3is turned on.

When the detection voltage VDET2is below the predetermined level, the transistor Q3turns off. When the detection voltage VDET2is less than the predetermined level, the output RF signal RFOUT2is not excessive (normal). That is, this is a case in which the protection operation is not performed.

When the transistor Q3is turned off, the control power supply voltage VBAT12_CTRLmay have the fourth voltage level. That is, the control power supply voltage VBAT12_CTRLbecomes the normal control power voltage VBAT12_CTRL_NORMAL. Similar to Equation 2 above, the normal control power supply voltage VBAT12_CTRL_NORMALmay have a value expressed by Equation 4 below.

In Equation 4 above, IR7represents the current flowing through the resistor R7when the transistor Q3is turned off.

Referring to Equations 3 and 4 above, the abnormal control power supply voltage VBAT12_CTRL_ABNORMALhas a lower value than the normal control power supply voltage VBAT12_CTRL_NORMAL. When the protection operation is performed, the transistor Q3is turned on, which causes the control power supply voltage VBAT12_CTRLto decrease (become lower). That is, the third voltage level is a voltage level lower than the fourth voltage level.

As shown inFIG.8, the bias circuit200B_2may include a transistor Q4, a transistor Q5, a transistor QB2, a resistor R10, a resistor R11, a resistor R12, and a capacitor C5.

A collector of the transistor QB2may receive the control power supply voltage VBAT12_CTRL. That is, the collector of the transistor QB2may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB2may be connected to the base of the transistor Q4. An emitter of the transistor QB2may be connected to the input terminal (for example, the base) of the power transistor100_2through the resistor R12. The current flowing through the emitter of the transistor QB2is the bias current IBIAS2_Bdescribed with respect toFIG.7. The collector of the transistor QB2is a terminal that receives the control power supply voltage VBAT12_CTRL, which is a power supply voltage, and the emitter of the transistor QB2is a terminal that supplies the bias current IBIAS2_Bto the power transistor100_2.

InFIG.8, the bias current IBIAS1_Band the bias current IBIAS2_Bmay change based on the control power supply voltage VBAT12_CTRL. When the control power supply voltage VBAT12_CTRLdecreases (becomes lower), the bias current IBIAS1_Band the bias current IBIAS2_Balso decrease. As an example, when the control power supply voltage VBAT12_CTRLis lower than a predetermined threshold voltage, the transistor QB1and the transistor QB2do not operate (that is, the transistor QB1and the transistor QB2are turned off), which may cause the bias current IBIAS1_Band the bias current IBIAS2_Bto be 0 mA.

When the control power supply voltage VBAT12_CTRLis the normal control power supply voltage VBAT12_CTRL_NORMAL, the transistor QB1and the transistor QB2receive a normal power voltage. Due to this, the bias current IBIAS1_Band the bias current IBIAS2_Balso have a normal value. In other words, the bias circuit200B_1generates the normal bias current IBIAS1_B_NORMALand the bias circuit200B_2generates the normal bias current IBIAS2_B_NORMAL. Due to the normal bias current IBIAS1_B_NORMALand the normal bias current IBIAS2_A_NORMAL, the power transistor100_1and the power transistor100_2may perform a normal amplification operation.

When the transistor Q3is turned on due to an excessive output RF signal RFOUT2, the control power supply voltage VBAT12_CTRLbecomes the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL. The transistor QB1and the transistor QB2receive the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL, which reduces the bias current IBIAS1_Band the bias current IBIAS2_B. In other words, the bias circuit200B_1generates the abnormal bias current IBIAS1_B_ABNORMALand the bias circuit200B_2generates the abnormal bias current IBIAS2_B_ABNORMAL. Due to the abnormal bias current IBIAS1_B_ABNORMALand the abnormal bias current IBIAS2_B_ABNORMAL, the peak voltages applied to the power transistor100_1and the power transistor100_2do not exceed a breakdown voltage. Through this, the power amplifier1000B may be protected from excessive RF signals.

The power amplifier1000B according to another example performs the protection operation only when the output RF signal RFOUT2is excessive (that is, abnormal) and does not perform the protection operation otherwise. That is, the transistor Q3ofFIG.8is turned on only when the output RF signal RFOUT2is excessive (that is, abnormal); otherwise it remains turned off. Since the transistor Q3does not continuously turn on and off, spurs due to oscillation may not occur.

InFIG.8, the electrostatic discharge protection circuit410B may be replaced with a capacitor. That is, as described with respect toFIG.6, the electrostatic discharge protection circuit410B may be replaced with a capacitor that couples and outputs a portion of the output RF signal RFOUT2to the anode of the diode D1as a detection RF signal.

FIG.9illustrates a power amplifier1000C according to another example.

As shown inFIG.9, the power amplifier1000C according to another example may include a power transistor100_1, a bias circuit200C_1, a capacitor C1, a power transistor100_2, a bias circuit200C_2, a capacitor C2, and a matching network300. Since the power amplifier1000C ofFIG.9is similar to the power amplifier1000A ofFIG.1and the power amplifier1000B ofFIG.7, overlapping descriptions may be omitted.

The bias circuit200C_1may receive a reference current IREF1and a power supply voltage VBAT1from an external source. The bias circuit200C_1may generate a bias current IBIAS1_Crequired by the power transistor100_1using the reference current IREF1and the power supply voltage VBAT1. The bias current IBIAS1_Cis supplied to the input terminal (for example, the base) of the power transistor100_1, and the bias level (a bias point) of the power transistor100_1may be set by the bias current IBIAS1_C.

The bias circuit200C_2may receive a control power supply voltage VBAT2_CTRL′ from a power supply voltage control circuit500C and may receive a reference current IREF2from an external source. The bias circuit200C_2may generate a bias current IBIAS2_Crequired by the power transistor100_2using the control power supply voltage VBAT2_CTRL′ and the reference current IREF2. The bias current IBIAS2_Cis supplied to the input terminal (for example, the base) of the power transistor100_2, and the bias level (a bias point) of the power transistor100_2may be set by the bias current IBIAS2_C.

When an excessive peak voltage is applied to an element (for example, the power transistor100_2) included in the power amplifier1000C (that is, in an abnormal state), the power amplifier1000C according to another example performs a protection operation. To perform this protection operation, the power amplifier1000C according to another example may further include a signal detection circuit400C and the power supply voltage control circuit500C.

The signal detection circuit400C may receive the output RF signal RFOUT2and detect the magnitude of the output RF signal RFOUT2. The magnitude of the output RF signal RFOUT2may correspond to the peak voltage of the output RF signal RFOUT2or may correspond to the power of the output RF signal RFOUT2. The signal detection circuit400C may generate a detection voltage VDET2corresponding to the magnitude of the output RF signal RFOUT2. In more detail, the signal detection circuit400C may detect the envelope of the output RF signal RFOUT2and generate and output the detection voltage VDET2corresponding to the detected envelope. That is, the signal detection circuit400C ofFIG.9is similar to the signal detection circuit400B ofFIG.7. The specific configuration and operation of the signal detection circuit400C will be described in detail with respect toFIG.10.

The power supply voltage control circuit500C may receive a power supply voltage VBAT2from an external source and receive the detection voltage VDET2from the signal detection circuit400C. The power supply voltage control circuit500C uses the power supply voltage VBAT2and the detection voltage VDET2to generate a control power supply voltage VBAT2_CTRL′, and the generated control power supply voltage VBAT2_CTRL′ may be output to the bias circuit200C_2. That is, the power supply voltage control circuit500C can adjust (change) the control power supply voltage VBAT2_CTRL′, which is a power supply voltage to be supplied to the bias circuit200C_2, in response to the detection voltage VDET2.

Similar to the control power supply voltage VBAT2_CTRLofFIG.1, the control power supply voltage VBAT2_CTRL′ ofFIG.9may have two voltage levels. When the detection voltage VDET2has a value higher than a predetermined voltage level, the power supply voltage control circuit500C may generate the control power supply voltage VBAT2_CTRL′ having a fifth voltage level. When the detection voltage VDET2has a value less than the predetermined voltage level, the power supply voltage control circuit500C may generate the control power supply voltage VBAT2_CTRL′ having a sixth voltage level. The fifth voltage level may be a voltage level lower than the sixth voltage level. When the output RF signal RFOUT2is excessive, the detection voltage VDET2has a value above the predetermined voltage level, so hereinafter, the control power supply voltage VBAT2_CTRL′ having the fifth voltage level is referred to as “abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′”. When the output RF signal RFOUT2is not excessive, the detection voltage VDET2has a value below the predetermined voltage level, so hereinafter, the control power supply voltage VBAT2_CTRL′ having the sixth voltage level is referred to as “normal control power supply voltage VBAT2_CTRL_NORMAL′”.

When the control power supply voltage VBAT2_CTRL′ is the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′, the bias circuit200C_2may generate an abnormal bias current IBIAS2_C_ABNORMAL. When the control power supply voltage VBAT2_CTRL′ is the normal control supply power voltage VBAT2_CTRL_NORMAL′, the bias circuit200C_2may generate a normal bias current IBIAS2_C_NORMAL. The abnormal bias current IBIAS2_C_ABNORMALhas a lower current value than the normal bias current IBIAS2_C_NORMAL. Due to the abnormal bias current IBIAS2_C_ABNORMALhaving a low current value, the power transistor100_2performs an amplification operation with a low gain, and the power amplifier1000C may be protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS2_C_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS2_C_ABNORMALis 0 mA, the power transistor100_2does not perform an amplification operation, so the power amplifier1000C may be protected from an excessive peak voltage.

FIG.10is a circuit diagram showing internal configurations of the bias circuit200C_1, the signal detection circuit400C, the power supply voltage control circuit500C, and the bias circuit200C_2ofFIG.9.

As shown inFIG.10, the bias circuit200C_1may include a transistor Q1, a transistor Q2, a transistor QB1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a capacitor C3. Since the bias circuit200C_1ofFIG.10is the same as the bias circuit200A_1ofFIG.2, a detailed description may be omitted.

The signal detection circuit400C may include an electrostatic discharge (ESD) protection circuit410C and an envelope detection circuit420C. Since the specific configuration and operation of the signal detection circuit400C are the same as those of the signal detection circuit400B ofFIG.8, a detailed description may be omitted. The electrostatic discharge protection circuit410C may include a plurality of forward-biased diodes D_F and a plurality of reverse-biased diodes D_R, and a detection RF signal RFOUT2_DETmay be output from the node N2. In addition, the envelope detection circuit420C may include a diode D1, a capacitor C4, a resistor R5, and a resistor R6. At the node where the resistor R5and the resistor R6are connected to each other, the detection voltage VDET2may be generated (output).

As shown inFIG.10, the power supply voltage control circuit500C may include a transistor Q3, a resistor R7, and a resistor R8.

A base of the transistor Q3may be connected to the other end of the resistor R5and may receive the detection voltage VDET2. That is, the base of the transistor Q3may be connected to the node where the resistor R5and the resistor R6are connected to each other. An emitter of the transistor Q3may be connected to the ground. A collector of the transistor Q3may be connected to the power supply voltage VBAT2through the resistor R8and the resistor R7.

One end of the resistor R7may be connected to the power supply voltage VBAT2, and the resistor R8may be connected between the other end of the resistor R7and the collector of the transistor Q3. The voltage at the node where the resistor R7and the resistor R8are connected to each other is the control power supply voltage VBAT2_CTRL′ described above. The control power supply voltage VBAT2_CTRL′ may change depending on whether the transistor Q3is turned on. Since the detection voltage VDET2is input to the base of the transistor Q3, the transistor Q3may be turned on or off depending on the level of the detection voltage VDET2.

When the detection voltage VDET2is above a predetermined level, the transistor Q3turns on. When the detection voltage VDET2is above the predetermined level, the output RF signal RFOUT2is excessive (abnormal). That is, this is a case in which the protection operation is performed. When performing a protection operation, the magnitude of the output RF signal RFOUT2may be set in advance, and the level of the corresponding detection voltage VDET2may be adjusted according to the values of the resistor R5and the resistor R6.

When the transistor Q3is turned on, the control power supply voltage VBAT2_CTRL′ may have the fifth voltage level. That is, the control power supply voltage VBAT2_CTRL′ becomes the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′. The abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′ may have the same value as VBAT2_CTRL_ABNORMALexpressed by Equation 1 above.

When the detection voltage VDET2is below the predetermined level, the transistor Q3turns off. When the detection voltage VDET2is less than the predetermined level, the output RF signal RFOUT2is not excessive (normal). That is, this is a case in which the protection operation is not performed.

When the transistor Q3is turned off, the control power supply voltage VBAT2_CTRL′ may have the sixth voltage level. That is, the control power supply voltage VBAT2_CTRL′ becomes the normal control power voltage VBAT2_CTRL_NORMAL′. The abnormal control power supply voltage VBAT2_CTRL_NORMAL′ may have the same value as VBAT2_CTRL_NORMALexpressed by Equation 2 above.

The abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′ has a lower value than the normal control power supply voltage VBAT2_CTRL_NORMAL′. When the protection operation is performed, the transistor Q3is turned on, which causes the control power supply voltage VBAT2_CTRL′ to decrease (become lower). That is, the fifth voltage level is a voltage level lower than the sixth voltage level.

As shown inFIG.10, the bias circuit200C_2may include a transistor Q4, a transistor Q5, a transistor QB2, a resistor R10, a resistor R11, a resistor R12, and a capacitor C5.

A collector of the transistor QB2may receive the control power supply voltage VBAT2_CTRL′. That is, the collector of the transistor QB2may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB2may be connected to the base of the transistor Q4. An emitter of the transistor QB2may be connected to the input terminal (for example, the base) of the power transistor100_2through the resistor R12. The current flowing through the emitter of the transistor QB2is the bias current IBIAS2_Cdescribed with respect toFIG.9. The collector of the transistor QB2is a terminal that receives the control power supply voltage VBAT2_CTRL′, which is a power supply voltage, and the emitter of the transistor QB2is a terminal that supplies the bias current IBIAS2_Cto the power transistor100_2.

InFIG.10, the bias current IBIAS2_Cmay change based on the control power supply voltage VBAT2_CTRL′. When the control power supply voltage VBAT2_CTRL′ decreases (becomes lower), the bias current IBIAS2_Calso decreases. As an example, when the control power supply voltage VBAT2_CTRL′ is lower than a predetermined threshold voltage, the transistor QB2does not operate (that is, the transistor QB2is turned off), which may cause the bias current IBIAS2_Cto be 0 mA.

When the control power supply voltage VBAT2_CTRL′ is the normal control power supply voltage VBAT2_CTRL_NORMAL′, the transistor QB2receives a normal power voltage. Due to this, the bias current IBIAS2_Calso has a normal value. In other words, the bias circuit200C_2generates the normal bias current IBIAS2_C_NORMAL. Due to the normal bias current IBIAS2_C_NORMAL, the power transistor100_2may perform a normal amplification operation.

When the transistor Q3is turned on due to an excessive output RF signal RFOUT2, the control power supply voltage VBAT2_CTRL′ becomes the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′. The transistor QB2receives the abnormal control power supply voltage VBAT2_CTRL_ABNORMAL′, which reduces the bias current IBIAS2_C. In other words, the bias circuit200C_2generates the abnormal bias current IBIAS2_C_ABNORMAL. Due to the abnormal bias current IBIAS2_C_ABNORMAL, the peak voltage applied to the power transistor100_2does not exceed a breakdown voltage. Through this, the power amplifier1000C may be protected from excessive RF signals.

The power amplifier1000C according to another example performs the protection operation only when the output RF signal RFOUT2is excessive (that is, abnormal) and does not perform the protection operation otherwise. That is, the transistor Q3ofFIG.10is turned on only when the output RF signal RFOUT2is excessive (that is, abnormal); otherwise it remains turned off. Since the transistor Q3does not continuously turn on and off, spurs due to oscillation may not occur.

InFIG.10, the electrostatic discharge protection circuit410C may be replaced with a capacitor. That is, as described with respect toFIG.6, the electrostatic discharge protection circuit410C may be replaced with a capacitor that couples and outputs a portion of the output RF signal RFOUT2to the anode of the diode D1as a detection RF signal.

FIG.11illustrates a power amplifier1000D according to another example.

As shown inFIG.11, the power amplifier1000D according to another example may include a power transistor100_1, a bias circuit200D_1, a capacitor C1, a power transistor100_2, a bias circuit200D_2, a capacitor C2, and a matching network300. Since the power amplifier1000D ofFIG.11is similar to the power amplifier1000A ofFIG.1, the power amplifier1000B ofFIG.7, and the power amplifier1000C ofFIG.9, overlapping descriptions may be omitted.

The bias circuit200D_1may receive a control power supply voltage VBAT1_CTRLfrom a power supply voltage control circuit500D and may receive the reference current IREF1from an external source. The bias circuit200D_1may generate a bias current IBIAS1_Drequired by the power transistor100_1using the control power supply voltage VBAT1_CTRLand the reference current IREF1. The bias current IBIAS1_Dis supplied to the input terminal (for example, the base) of the power transistor100_1, and the bias level (a bias point) of the power transistor100_1may be set by the bias current IBIAS1_D.

The bias circuit200D_2may receive a reference current IREF2and a power supply voltage VBAT2from an external source. The bias circuit200D_2may generate a bias current IBIAS2_Drequired by the power transistor100_2using the reference current IREF2and the power supply voltage VBAT2. The bias current IBIAS2_Dis supplied to the input terminal (for example, the base) of the power transistor100_2, and the bias level (a bias point) of the power transistor100_2may be set by the bias current IBIAS2_D.

When an excessive peak voltage is applied to an element (for example, the power transistor100_2) included in the power amplifier1000D (that is, in an abnormal state), the power amplifier1000D according to another example performs a protection operation. To perform this protection operation, the power amplifier1000D according to another example may further include a signal detection circuit400D and the power supply voltage control circuit500D.

The signal detection circuit400D may receive the output RF signal RFOUT2and detect the magnitude of the output RF signal RFOUT2. The magnitude of the output RF signal RFOUT2may correspond to the peak voltage of the output RF signal RFOUT2or may correspond to the power of the output RF signal RFOUT2. The signal detection circuit400D may generate a detection voltage VDET2corresponding to the magnitude of the output RF signal RFOUT2. In more detail, the signal detection circuit400D may detect the envelope of the output RF signal RFOUT2and generate and output the detection voltage VDET2corresponding to the detected envelope. That is, the signal detection circuit400D ofFIG.11is similar to the signal detection circuit400B ofFIG.7and the signal detection circuit400C ofFIG.9. The specific configuration and operation of the signal detection circuit400D will be described in detail with respect toFIG.12.

The power supply voltage control circuit500D may receive a power supply voltage VBAT1from an external source and receive the detection voltage VDET2from the signal detection circuit400D. The power supply voltage control circuit500D uses the power supply voltage VBAT1and the detection voltage VDET2to generate a control power supply voltage VBAT1_CTRL, and the generated control power supply voltage VBAT1_CTRLmay be output to the bias circuit200D_1. That is, the power supply voltage control circuit500D can adjust (change) the control power supply voltage VBAT1_CTRL, which is a power supply voltage to be supplied to the bias circuit200D_1, in response to the detection voltage VDET2.

The control power supply voltage VBAT1_CTRLofFIG.11may have two voltage levels. When the detection voltage VDET2has a value higher than a predetermined voltage level, the power supply voltage control circuit500D may generate the control power supply voltage VBAT1_CTRLhaving a seventh voltage level. When the detection voltage VDET2has a value less than the predetermined voltage level, the power supply voltage control circuit500D may generate the control power supply voltage VBAT1_CTRLhaving an eighth voltage level. The eighth voltage level may be a voltage level lower than the seventh voltage level. When the output RF signal RFOUT2is excessive, the detection voltage VDET2has a value above the predetermined voltage level, so hereinafter, the control power supply voltage VBAT1_CTRLhaving the seventh voltage level is referred to as “abnormal control power supply voltage VBAT1_CTRL_ABNORMAL”. When the output RF signal RFOUT2is not excessive, the detection voltage VDET2has a value below the predetermined voltage level, so hereinafter, the control power supply voltage VBAT1_CTRLhaving the eighth voltage level is referred to as “normal control power supply voltage VBAT1_CTRL_NORMAL”.

When the control power supply voltage VBAT1_CTRLis the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL, the bias circuit200D_1may generate an abnormal bias current IBIAS1_D_ABNORMAL. When the control power supply voltage VBAT1_CTRLis the normal control supply power voltage VBAT1_CTRL_NORMAL, the bias circuit200D_1may generate a normal bias current IBIAS1_D_NORMAL. The abnormal bias current IBIAS1_D_ABNORMALhas a lower current value than the normal bias current IBIAS1_D_NORMAL. Due to the abnormal bias current IBIAS1_D_ABNORMALhaving a low current value, the power transistor100_1performs an amplification operation with a low gain, and the power amplifier1000D may be protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS1_D_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS1_D_ABNORMALis 0 mA, the power transistor100_1does not perform an amplification operation, so the power amplifier1000D may be protected from an excessive peak voltage.

FIG.12is a circuit diagram showing internal configurations of the bias circuit200D_1, the signal detection circuit400D, the power supply voltage control circuit500D, and the bias circuit200D_2ofFIG.11.

As shown inFIG.12, the bias circuit200D_1may include a transistor Q1, a transistor Q2, a transistor QB1, a resistor R1, a resistor R2, a resistor R4, and a capacitor C3. Since the bias circuit200D_1ofFIG.12is similar to the bias circuit200B_1ofFIG.8, overlapping descriptions may be omitted.

A collector of the transistor QB1may receive the control power supply voltage VBAT1_CTRL. That is, the collector of the transistor QB1may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB1may be connected to a base of the transistor Q1. An emitter of the transistor QB1may be connected to the input terminal (for example, the base) of the power transistor100_1through the resistor R4. The current flowing through the emitter of the transistor QB1is the bias current IBIAS1_Ddescribed with respect toFIG.11above. The collector of the transistor QB1is a terminal that receives the control power supply voltage VBAT1_CTRL, which is a power supply voltage, and the emitter of the transistor QB1is a terminal that supplies the bias current IBIAS1_Dto the power transistor100_1.

The signal detection circuit400D may include an electrostatic discharge (ESD) protection circuit410D and an envelope detection circuit420D. Since the specific configuration and operation of the signal detection circuit400D are the same as those of the signal detection circuit400B ofFIG.8and the signal detection circuit400C ofFIG.10, detailed descriptions may be omitted. The electrostatic discharge protection circuit410D may include a plurality of forward-biased diodes D_F and a plurality of reverse-biased diodes D_R, and a detection RF signal RFOUT2_DETmay be output from the node N2. In addition, the envelope detection circuit420D may include a diode D1, a capacitor C4, a resistor R5, and a resistor R6. At the node where the resistor R5and the resistor R6are connected to each other, the detection voltage VDET2may be generated (output).

As shown inFIG.12, the power supply voltage control circuit500D may include a transistor Q3, a resistor R7, and a resistor R8.

A base of the transistor Q3may be connected to the other end of the resistor R5and may receive the detection voltage VDET2. That is, the base of the transistor Q3may be connected to the node where the resistor R5and the resistor R6are connected to each other. An emitter of the transistor Q3may be connected to the ground. A collector of the transistor Q3may be connected to the power supply voltage VBAT1through the resistor R8and the resistor R7.

One end of the resistor R7may be connected to the power supply voltage VBAT1, and the resistor R8may be connected between the other end of the resistor R7and the collector of the transistor Q3. The voltage at the node where the resistor R7and the resistor R8are connected to each other is the control power supply voltage VBAT1_CTRLdescribed above. The control power supply voltage VBAT1_CTRLmay change depending on whether the transistor Q3is turned on. Since the detection voltage VDET2is input to the base of the transistor Q3, the transistor Q3may be turned on or off depending on the level of the detection voltage VDET2.

When the detection voltage VDET2is above a predetermined level, the transistor Q3turns on. When the detection voltage VDET2is above the predetermined level, the output RF signal RFOUT2is excessive (abnormal). That is, this is a case in which the protection operation is performed. When performing a protection operation, the magnitude of the output RF signal RFOUT2may be set in advance, and the level of the corresponding detection voltage VDET2may be adjusted according to the values of the resistor R5and the resistor R6.

When the transistor Q3is turned on, the control power supply voltage VBAT1_CTRLmay have the seventh voltage level. That is, the control power supply voltage VBAT1_CTRLbecomes the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL. Similar to Equation 1 and Equation 3 above, the abnormal control power supply voltage VBAT1_CTRL_ABNORMALmay have a value expressed by Equation 5 below.

When the detection voltage VDET2is below the predetermined level, the transistor Q3turns off. When the detection voltage VDET2is less than the predetermined level, the output RF signal RFOUT2is not excessive (normal). That is, this is a case in which the protection operation is not performed.

When the transistor Q3is turned off, the control power supply voltage VBAT1_CTRLmay have the eighth voltage level. That is, the control power supply voltage VBAT1_CTRLbecomes the normal control power voltage VBAT1_CTRL_NORMAL. Similar to Equation 2 and Equation 4 above, the normal control power supply voltage VBAT1_CTRL_NORMALmay have a value expressed by Equation 6 below.

Referring to Equations 5 and 6 above, the abnormal control power supply voltage VBAT1_CTRL_ABNORMALhas a lower value than the normal control power supply voltage VBAT1_CTRL_NORMAL. When the protection operation is performed, the transistor Q3is turned on, which causes the control power supply voltage VBAT1_CTRLto decrease (become lower). That is, the seventh voltage level is a voltage level lower than the eighth voltage level.

As shown inFIG.12, the bias circuit200D_2may include a transistor Q4, a transistor Q5, a transistor QB2, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a capacitor C5. Since the bias circuit200D_2ofFIG.12is similar to the bias circuit200A_2ofFIG.3except for the connection relationship of the transistor QB2, overlapping descriptions may be omitted.

A collector of the transistor QB2may be connected to the power supply voltage VBAT2through the resistor R13, and a base of the transistor QB2may be connected to the base of the transistor Q4. An emitter of the transistor QB2may be connected to the input terminal (for example, the base) of the power transistor100_2through the resistor R12. The current flowing through the emitter of the transistor QB2is the bias current IBIAS2_Ddescribed with respect toFIG.11. The collector of the transistor QB2is a terminal that receives the power supply voltage VBAT2, and the emitter of the transistor QB2is a terminal that supplies the bias current IBIAS2_Dto the power transistor100_2.

InFIG.12, the bias current IBIAS1_Dmay change based on the control power supply voltage VBAT1_CTRL. When the control power supply voltage VBAT1_CTRLdecreases (becomes lower), the bias current IBIAS1_Dalso decreases. As an example, when the control power supply voltage VBAT1_CTRLis lower than a predetermined threshold voltage, the transistor QB1does not operate (that is, the transistor QB1is turned off), which may cause the bias current IBIAS1_Dto be 0 mA.

When the control power supply voltage VBAT1_CTRLis the normal control power supply voltage VBAT1_CTRL_NORMAL, the transistor QB1receives a normal power voltage. Due to this, the bias current IBIAS2_Dalso has a normal value. In other words, the bias circuit200D_1generates the normal bias current IBIAS1_D_NORMAL. Due to the normal bias current IBIAS1_D_NORMAL, the power transistor100_1may perform a normal amplification operation.

When the transistor Q3is turned on due to an excessive output RF signal RFOUT2, the control power supply voltage VBAT1_CTRLbecomes the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL. The transistor QB1receives the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL, which reduces the bias current IBIAS1_D. In other words, the bias circuit200D_1generates the abnormal bias current IBIAS1_D_ABNORMAL. Due to the abnormal bias current IBIAS1_D_ABNORMAL, the peak voltage applied to the power transistor100_1does not exceed a breakdown voltage. Through this, the power amplifier1000D may be protected from excessive RF signals.

The power amplifier1000D according to another example performs the protection operation only when the output RF signal RFOUT2is excessive (that is, abnormal) and does not perform the protection operation otherwise. That is, the transistor Q3ofFIG.12is turned on only when the output RF signal RFOUT2is excessive (that is, abnormal); otherwise it remains turned off. Since the transistor Q3does not continuously turn on and off, spurs due to oscillation may not occur.

InFIG.12, the electrostatic discharge protection circuit410D may be replaced with a capacitor. That is, as described with respect toFIG.6, the electrostatic discharge protection circuit410D may be replaced with a capacitor that couples and outputs a portion of the output RF signal RFOUT2to the anode of the diode D1as a detection RF signal.

FIG.13illustrates a power amplifier1000E according to another example.

As shown inFIG.13, the power amplifier1000E according to another example may include a power transistor100_1, a bias circuit200E_1, a capacitor C1, a power transistor100_2, a bias circuit200E_2, a capacitor C2, and a matching network300. Since the power amplifier1000E ofFIG.13is similar to the power amplifier1000A ofFIG.1, the power amplifier1000B ofFIG.7, the power amplifier1000C ofFIG.9, and the power amplifier1000D ofFIG.11, overlapping descriptions may be omitted.

The bias circuit200E_1may receive a control power supply voltage VBAT12_CTRL′ from a power supply voltage control circuit500E and may receive a reference current IREF1from an external source. The bias circuit200E_1may generate a bias current IBIAS1_Erequired by the power transistor100_1using the control power supply voltage VBAT12_CTRL′ and the reference current IREF1. The bias current IBIAS1_Dis supplied to the input terminal (for example, the base) of the power transistor100_1, and the bias level (a bias point) of the power transistor100_1may be set by the bias current IBIAS1_D.

The bias circuit200E_2may receive the control power supply voltage VBAT12_CTRL′ from the power supply voltage control circuit500E and may receive a reference current IREF2from an external source. The bias circuit200E_2may generate a bias current IBIAS2_Erequired by the power transistor100_2using the control power supply voltage VBAT12_CTRL′ and the reference current IREF2. The bias current IBIAS2_Eis supplied to the input terminal (for example, the base) of the power transistor100_2, and the bias level (a bias point) of the power transistor100_2may be set by the bias current IBIAS2_E.

When an excessive peak voltage is applied to an element (for example, the power transistor100_1) included in the power amplifier1000E (that is, in an abnormal state), the power amplifier1000E according to another example performs a protection operation. To perform this protection operation, the power amplifier1000E according to another example may further include a signal detection circuit400E and the power supply voltage control circuit500E.

The signal detection circuit400E may receive the output RF signal RFOUT1and detect the magnitude of the output RF signal RFOUT1. The magnitude of the output RF signal RFOUT1may correspond to the peak voltage of the output RF signal RFOUT1or may correspond to the power of the output RF signal RFOUT1. The signal detection circuit400E may generate a detection voltage VDET1corresponding to the magnitude of the output RF signal RFOUT1. In more detail, the signal detection circuit400E may detect the envelope of the output RF signal RFOUT1and generate and output the detection voltage VDET1corresponding to the detected envelope. The specific configuration and operation of the signal detection circuit400E will be described in detail with respect toFIG.14.

The power supply voltage control circuit500E may receive a power supply voltage VBATfrom an external source and receive the detection voltage VDET1from the signal detection circuit400E. The power supply voltage control circuit500E uses the power supply voltage VBATand the detection voltage VDET1to generate a control power supply voltage VBAT12_CTRL′, and the generated control power supply voltage VBAT12_CTRL′ may be output to the bias circuit200E_1and the bias circuit200E_2. That is, the power supply voltage control circuit500E can adjust (change) the control power supply voltage VBAT12_CTRL′, which is a power supply voltage to be supplied to the bias circuit200E_1and the bias circuit200E_2in response to the detection voltage VDET1.

The control power supply voltage VBAT12_CTRL′ ofFIG.13may have two voltage levels. When the detection voltage VDET1has a value higher than a predetermined voltage level, the power supply voltage control circuit500E may generate the control power supply voltage VBAT12_CTRL′ having a ninth voltage level. When the detection voltage VDET1has a value less than the predetermined voltage level, the power supply voltage control circuit500E may generate the control power supply voltage VBAT12_CTRL′ having a tenth voltage level. The ninth voltage level may be a voltage level lower than the tenth voltage level. When the output RF signal RFOUT1is excessive, the detection voltage VDET1has a value above the predetermined voltage level, so hereinafter, the control power supply voltage VBAT12_CTRL′ having the ninth voltage level is referred to as “abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′”. When the output RF signal RFOUT1is not excessive, the detection voltage VDET1has a value below the predetermined voltage level, so hereinafter, the control power supply voltage VBAT12_CTRL′ having the tenth voltage level is referred to as “normal control power supply voltage VBAT12_CTRL_NORMAL′”.

When the control power supply voltage VBAT12_CTRL′ is the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′, the bias circuit200E_1may generate an abnormal bias current IBIAS1_E_ABNORMAL. When the control power supply voltage VBAT12_CTRL′ is the normal control supply power voltage VBAT12_CTRL_NORMAL′, the bias circuit200E_1may generate a normal bias current IBIAS1_E_NORMAL. The abnormal bias current IBIAS1_E_ABNORMALhas a lower current value than the normal bias current IBIAS1_E_NORMAL. Due to the abnormal bias current IBIAS1_E_ABNORMALhaving a low current value, the power transistor100_1performs an amplification operation with a low gain, and the power amplifier1000E may be protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS1_E_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS1_E_ABNORMALis 0 mA, the power transistor100_1does not perform an amplification operation, so the power amplifier1000E may be protected from an excessive peak voltage.

When the control power supply voltage VBAT12_CTRL′ is the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′, the bias circuit200E_2may generate an abnormal bias current IBIAS2_E_ABNORMAL. When the control power supply voltage VBAT12_CTRL′ is the normal control supply power voltage VBAT12_CTRL_NORMAL′, the bias circuit200E_2may generate a normal bias current IBIAS2_E_NORMAL. The abnormal bias current IBIAS2_E_ABNORMALhas a lower current value than the normal bias current IBIAS2_E_NORMAL. Due to the abnormal bias current IBIAS2_E_ABNORMALhaving a low current value, the power transistor100_2performs an amplification operation with a low gain, and power amplifier1000E may be protected from an excessive peak voltage. That is, not only the power transistor100_1but also the power transistor100_2performs an amplification operation with a low gain, and the power amplifier1000E may be further protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS2_E_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS2_E_ABNORMALis 0 mA, the power transistor100_2does not perform an amplification operation, so the power amplifier1000E may be protected from an excessive peak voltage.

FIG.14is a circuit diagram showing internal configurations of the bias circuit200E_1, the signal detection circuit400E, the power supply voltage control circuit500E, and the bias circuit200E_2ofFIG.13.

As shown inFIG.14, the bias circuit200E_1may include a transistor Q1, a transistor Q2, a transistor QB1, a resistor R1, a resistor R2, a resistor R4, and a capacitor C3. Since the bias circuit200E_1ofFIG.14is similar to the bias circuit200B_1ofFIG.8, overlapping descriptions may be omitted.

A collector of the transistor QB1may receive the control power supply voltage VBAT12_CTRL′. That is, the collector of the transistor QB1may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB1may be connected to a base of the transistor Q1. An emitter of the transistor QB1may be connected to the input terminal (for example, the base) of the power transistor100_1through the resistor R4. The current flowing through the emitter of the transistor QB1is the bias current IBIAS1_Edescribed with respect toFIG.13above. The collector of the transistor QB1is a terminal that receives the control power supply voltage VBAT12_CTRL′, which is a power supply voltage, and the emitter of the transistor QB1is a terminal that supplies the bias current IBIAS1_Eto the power transistor100_1.

The signal detection circuit400E may include an electrostatic discharge (ESD) protection circuit410E and an envelope detection circuit420E. Since the specific configuration and operation of the signal detection circuit400E are the same as those of the signal detection circuit400A ofFIG.3, detailed descriptions may be omitted. The electrostatic discharge protection circuit410E may include a plurality of forward-biased diodes D_F and a plurality of reverse-biased diodes D_R, and a detection RF signal RFOUT1_DETmay be output from the node N1. In addition, the envelope detection circuit420E may include a diode D1, a capacitor C4, a resistor R5, and a resistor R6. At the node where the resistor R5and the resistor R6are connected to each other, the detection voltage VDET1may be generated (output).

As shown inFIG.14, the power supply voltage control circuit500E may include a transistor Q3, a resistor R7, and a resistor R8.

A base of the transistor Q3may be connected to the other end of the resistor R5and may receive the detection voltage VDET1. That is, the base of the transistor Q3may be connected to the node where the resistor R5and the resistor R6are connected to each other. An emitter of the transistor Q3may be connected to the ground. A collector of the transistor Q3may be connected to the power supply voltage VBATthrough the resistor R8and the resistor R7.

One end of the resistor R7may be connected to the power supply voltage VBAT, and the resistor R8may be connected between the other end of the resistor R7and the collector of the transistor Q3. The voltage at the node where the resistor R7and the resistor R8are connected to each other is the control power supply voltage VBAT12_CTRL′ described above. The control power supply voltage VBAT12_CTRL′ may change depending on whether the transistor Q3is turned on. Since the detection voltage VDET1is input to the base of the transistor Q3, the transistor Q3may be turned on or off depending on the level of the detection voltage VDET1.

When the detection voltage VDET1is above a predetermined level, the transistor Q3turns on. When the detection voltage VDET1is above the predetermined level, the output RF signal RFOUT1is excessive (abnormal). That is, this is a case in which the protection operation is performed. When performing a protection operation, the magnitude of the output RF signal RFOUT1may be set in advance, and the level of the corresponding detection voltage VDET1may be adjusted according to the values of the resistor R5and the resistor R6.

When the transistor Q3is turned on, the control power supply voltage VBAT12_CTRL′ may have the ninth voltage level. That is, the control power supply voltage VBAT12_CTRL′ becomes the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′. The abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′ may have the same value as VBAT12_CTRL_ABNORMALexpressed by Equation 3 above.

When the detection voltage VDET1is below the predetermined level, the transistor Q3turns off. When the detection voltage VDET1is less than the predetermined level, the output RF signal RFOUT1is not excessive (normal). That is, this is a case in which the protection operation is not performed.

When the transistor Q3is turned off, the control power supply voltage VBAT12_CTRL′ may have the tenth voltage level. That is, the control power supply voltage VBAT12_CTRL′ becomes the normal control power voltage VBAT12_CTRL_NORMAL′. The normal control power supply voltage VBAT12_CTRL_NORMAL′ may have the same value as VBAT12_CTRL_NORMALexpressed by Equation 4 above.

The abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′ has a lower value than the normal control power supply voltage VBAT12_CTRL_NORMAL′. When the protection operation is performed, the transistor Q3is turned on, which causes the control power supply voltage VBAT12_CTRL′ to decrease (become lower). That is, the ninth voltage level is a voltage level lower than the tenth voltage level.

As shown inFIG.14, the bias circuit200E_2may include a transistor Q4, a transistor Q5, a transistor QB2, a resistor R10, a resistor R11, a resistor R12, and a capacitor C5.

A collector of the transistor QB2may receive the control power supply voltage VBAT12_CTRL′. That is, the collector of the transistor QB2may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB2may be connected to the base of the transistor Q4. An emitter of the transistor QB2may be connected to the input terminal (for example, the base) of the power transistor100_2through the resistor R12. The current flowing through the emitter of the transistor QB2is the bias current IBIAS2_Edescribed with respect toFIG.13. The collector of the transistor QB2is a terminal that receives the control power supply voltage VBAT12_CTRL′, which is a power supply voltage, and the emitter of the transistor QB2is a terminal that supplies the bias current IBIAS2_Eto the power transistor100_2.

InFIG.14, the bias current IBIAS1_Eand the bias current IBIAS2_Emay change based on the control power supply voltage VBAT12_CTRL′. When the control power supply voltage VBAT12_CTRL′ decreases (becomes lower), the bias current IBIAS1_Eand the bias current IBIAS2_Ealso decrease. As an example, when the control power supply voltage VBAT12_CTRL′ is lower than a predetermined threshold voltage, the transistor QB1and the transistor QB2do not operate (that is, the transistor QB1and the transistor QB2are turned off), which may cause the bias current IBIAS1_Eand the bias current IBIAS2_Eto be 0 mA.

When the control power supply voltage VBAT12_CTRL′ is the normal control power supply voltage VBAT12_CTRL_NORMAL′, the transistor QB1and the transistor QB2receive a normal power voltage. Due to this, the bias current IBIAS1_Eand the bias current IBIAS2_Ealso have a normal value. In other words, the bias circuit200E_1generates the normal bias current IBIAS1_E_NORMALand the bias circuit200E_2generates the normal bias current IBIAS2_E_NORMAL. Due to the normal bias current IBIAS1_E_NORMALand the normal bias current IBIAS2_E_NORMAL, the power transistor100_1and the power transistor100_2may perform a normal amplification operation.

When the transistor Q3is turned on due to an excessive output RF signal RFOUT1, the control power supply voltage VBAT12_CTRL′ becomes the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′. The transistor QB1and the transistor QB2receive the abnormal control power supply voltage VBAT12_CTRL_ABNORMAL′, which reduces the bias current IBIAS1_Eand the bias current IBIAS2_E. In other words, the bias circuit200E_1generates the abnormal bias current IBIAS1_E_ABNORMAL, and the bias circuit200E_2generates the abnormal bias current IBIAS2_E_ABNORMAL. Due to the abnormal bias current IBIAS1_E_ABNORMALand the abnormal bias current IBIAS2_E_ABNORMAL, the peak voltages applied to the power transistor100_1and the power transistor100_2do not exceed a breakdown voltage. Through this, the power amplifier1000E may be protected from excessive RF signals.

The power amplifier1000E according to another example performs the protection operation only when the output RF signal RFOUT1is excessive (that is, abnormal) and does not perform the protection operation otherwise. That is, the transistor Q3ofFIG.14is turned on only when the output RF signal RFOUT1is excessive (that is, abnormal); otherwise it remains turned off. Since the transistor Q3does not continuously turn on and off, spurs due to oscillation may not occur.

InFIG.14, the electrostatic discharge protection circuit410E may be replaced with a capacitor. That is, as described with respect toFIG.6, the electrostatic discharge protection circuit410E may be replaced with a capacitor that couples and outputs a portion of the output RF signal RFOUT1to the anode of the diode D1as a detection RF signal.

FIG.15illustrates a power amplifier1000F according to another example.

As shown inFIG.15, the power amplifier1000F according to another example may include a power transistor100_1, a bias circuit200F_1, a capacitor C1, a power transistor100_2, a bias circuit200F_2, a capacitor C2, and a matching network300. Since the power amplifier1000F ofFIG.15is similar to the power amplifier1000A ofFIG.1, the power amplifier1000B ofFIG.7, the power amplifier1000C ofFIG.9, the power amplifier1000D ofFIG.11, and the power amplifier1000E ofFIG.13, overlapping descriptions may be omitted.

The bias circuit200F_1may receive a control power supply voltage VBAT1_CTRL′ from a power supply voltage control circuit500F and may receive the reference current IREF1from an external source. The bias circuit200F_1may generate a bias current IBIAS1_Frequired by the power transistor100_1using the control power supply voltage VBAT1_CTRL′ and the reference current IREF1. The bias current IBIAS1_Fis supplied to the input terminal (for example, the base) of the power transistor100_1, and the bias level (a bias point) of the power transistor100_1may be set by the bias current IBIAS1_F.

The bias circuit200F_2may receive a reference current IREF2and a power supply voltage VBAT2from an external source. The bias circuit200F_2may generate a bias current IBIAS2_Frequired by the power transistor100_2using the reference current IREF2and the power supply voltage VBAT2. The bias current IBIAS2_Fis supplied to the input terminal (for example, the base) of the power transistor100_2, and the bias level (a bias point) of the power transistor100_2may be set by the bias current IBIAS2_F.

When an excessive peak voltage is applied to an element (for example, the power transistor100_1) included in the power amplifier1000F (that is, in an abnormal state), the power amplifier1000F according to another example performs a protection operation. To perform this protection operation, the power amplifier1000F according to another example may further include a signal detection circuit400F and the power supply voltage control circuit500F.

The signal detection circuit400F may receive the output RF signal RFOUT1and detect the magnitude of the output RF signal RFOUT1. The magnitude of the output RF signal RFOUT1may correspond to the peak voltage of the output RF signal RFOUT1or may correspond to the power of the output RF signal RFOUT1. The signal detection circuit400F may generate a detection voltage VDET1corresponding to the magnitude of the output RF signal RFOUT1. In more detail, the signal detection circuit400F may detect the envelope of the output RF signal RFOUT1and generate and output the detection voltage VDET1corresponding to the detected envelope. The specific configuration and operation of the signal detection circuit400F will be described in detail with respect toFIG.16.

The power supply voltage control circuit500F may receive a power supply voltage VBAT1from an external source and receive the detection voltage VDET1from the signal detection circuit400F. The power supply voltage control circuit500F uses the power supply voltage VBAT1and the detection voltage VDET1to generate a control power supply voltage VBAT1_CTRL′, and the generated control power supply voltage VBAT1_CTRL′ may be output to the bias circuit200F_1. That is, the power supply voltage control circuit500F can adjust (change) the control power supply voltage VBAT1_CTRL′, which is a power supply voltage to be supplied to the bias circuit200F_1, in response to the detection voltage VDET1.

The control power supply voltage VBAT1_CTRL′ ofFIG.15may have two voltage levels. When the detection voltage VDET1has a value higher than a predetermined voltage level, the power supply voltage control circuit500F may generate the control power supply voltage VBAT1_CTRL′ having an eleventh voltage level. When the detection voltage VDET1has a value less than the predetermined voltage level, the power supply voltage control circuit500F may generate the control power supply voltage VBAT1_CTRL′ having a twelfth voltage level. The eleventh voltage level may be a voltage level lower than the twelfth voltage level. When the output RF signal RFOUT1is excessive, the detection voltage VDET1has a value above the predetermined voltage level, so hereinafter, the control power supply voltage VBAT1_CTRL′ having the eleventh voltage level is referred to as “abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′”. When the output RF signal RFOUT1is not excessive, the detection voltage VDET1has a value below the predetermined voltage level, so hereinafter, the control power supply voltage VBAT1_CTRL′ having the twelfth voltage level is referred to as “normal control power supply voltage VBAT1_CTRL_NORMAL′”.

When the control power supply voltage VBAT1_CTRL′ is the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′, the bias circuit200F_1may generate an abnormal bias current IBIAS1_F_ABNORMAL. When the control power supply voltage VBAT1_CTRL′ is the normal control supply power voltage VBAT1_CTRL_NORMAL′, the bias circuit200F_1may generate a normal bias current IBIAS1_F_NORMAL. The abnormal bias current IBIAS1_F_ABNORMALhas a lower current value than the normal bias current IBIAS1_F_NORMAL. Due to the abnormal bias current IBIAS1_F_ABNORMALhaving a low current value, the power transistor100_1performs an amplification operation with a low gain, and the power amplifier1000F may be protected from an excessive peak voltage. As an example, the abnormal bias current IBIAS1_F_ABNORMALmay be 0 mA. When the abnormal bias current IBIAS1_F_ABNORMALis 0 mA. the power transistor100_1does not perform an amplification operation, so the power amplifier1000F may be protected from an excessive peak voltage.

FIG.16is a circuit diagram showing internal configurations of the bias circuit200F_1, the signal detection circuit400F, the power supply voltage control circuit500F, and the bias circuit200F_2ofFIG.15.

As shown inFIG.16, the bias circuit200F_1may include a transistor Q1, a transistor Q2, a transistor QB1, a resistor R1, a resistor R2, a resistor R4, and a capacitor C3. Since the bias circuit200F_1ofFIG.16is similar to the bias circuit200B_1ofFIG.8and the bias circuit200D_1ofFIG.12, overlapping descriptions may be omitted.

A collector of the transistor QB1may receive the control power supply voltage VBAT1_CTRL′. That is, the collector of the transistor QB1may be connected to the node where the resistor R7and the resistor R8are connected to each other. A base of the transistor QB1may be connected to a base of the transistor Q1. An emitter of the transistor QB1may be connected to the input terminal (for example, the base) of the power transistor100_1through the resistor R4. The current flowing through the emitter of the transistor QB1is the bias current IBIAS1_Fdescribed with respect toFIG.15above. The collector of the transistor QB1is a terminal that receives the control power supply voltage VBAT1_CTRL′, which is a power supply voltage, and the emitter of the transistor QB1is a terminal that supplies the bias current IBIAS1_Fto the power transistor100_1.

The signal detection circuit400F may include an electrostatic discharge (ESD) protection circuit410F and an envelope detection circuit420F. Since the specific configuration and operation of the signal detection circuit400F are the same as those of the signal detection circuit400A ofFIG.3, detailed descriptions may be omitted. The electrostatic discharge protection circuit410F may include a plurality of forward-biased diodes D_F and a plurality of reverse-biased diodes D_R, and a detection RF signal RFOUT1_DETmay be output from the node N1. In addition, the envelope detection circuit420F may include a diode D1, a capacitor C4, a resistor R5, and a resistor R6. At the node where the resistor R5and the resistor R6are connected to each other, the detection voltage VDET1may be generated (output).

As shown inFIG.16, the power supply voltage control circuit500E may include a transistor Q3, a resistor R7, and a resistor R8.

A base of the transistor Q3may be connected to the other end of the resistor R5and may receive the detection voltage VDET1. That is, the base of the transistor Q3may be connected to the node where the resistor R5and the resistor R6are connected to each other. An emitter of the transistor Q3may be connected to the ground. A collector of the transistor Q3may be connected to the power supply voltage VBAT1through the resistor R8and the resistor R7.

One end of the resistor R7may be connected to the power supply voltage VBAT1, and the resistor R8may be connected between the other end of the resistor R7and the collector of the transistor Q3. The voltage at the node where the resistor R7and the resistor R8are connected to each other is the control power supply voltage VBAT1_CTRL′ described above. The control power supply voltage VBAT1_CTRL′ may change depending on whether the transistor Q3is turned on. Since the detection voltage VDET1is input to the base of the transistor Q3, the transistor Q3may be turned on or off depending on the level of the detection voltage VDET1.

When the detection voltage VDET1is above a predetermined level, the transistor Q3turns on. When the detection voltage VDET1is above the predetermined level, the output RF signal RFOUT1is excessive (abnormal). That is, this is a case in which the protection operation is performed. When performing a protection operation, the magnitude of the output RF signal RFOUT1may be set in advance, and the level of the corresponding detection voltage VDET1may be adjusted according to the values of the resistor R5and the resistor R6.

When the transistor Q3is turned on, the control power supply voltage VBAT1_CTRL′ may have the eleventh voltage level. That is, the control power supply voltage VBAT1_CTRL′ becomes the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′. The abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′ may have the same value as VBAT1_CTRL_ABNORMALexpressed by Equation 5 above.

When the detection voltage VDET1is below the predetermined level, the transistor Q3turns off. When the detection voltage VDET1is less than the predetermined level, the output RF signal RFOUT1is not excessive (normal). That is, this is a case in which the protection operation is not performed.

When the transistor Q3is turned off, the control power supply voltage VBAT1_CTRL′ may have the twelfth voltage level. That is, the control power supply voltage VBAT1_CTRL′ becomes the normal control power voltage VBAT1_CTRL_NORMAL′. The normal control power supply voltage VBAT1_CTRL_NORMAL′ may have the same value as VBAT1_CTRL_NORMALexpressed by Equation 6 above.

The abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′ has a lower value than the normal control power supply voltage VBAT1_CTRL_NORMAL′. When the protection operation is performed, the transistor Q3is turned on, which causes the control power supply voltage VBAT1_CTRL′ to decrease (become lower). That is, the eleventh voltage level is a voltage level lower than the twelfth voltage level.

As shown inFIG.16, the bias circuit200F_2may include a transistor Q4, a transistor Q5, a transistor QB2, a resistor R10, a resistor R11, a resistor R12, and a capacitor C5. Since the bias circuit200F_2ofFIG.16is similar to the bias circuit200D_2ofFIG.12, overlapping descriptions may be omitted.

A collector of the transistor QB2may be connected to the power supply voltage VBAT2through the resistor R13, and a base of the transistor QB2may be connected to the base of the transistor Q4. An emitter of the transistor QB2may be connected to the input terminal (for example, the base) of the power transistor100_2through the resistor R12. The current flowing through the emitter of the transistor QB2is the bias current IBIAS2_Fdescribed with respect toFIG.15. The collector of the transistor QB2is a terminal that receives the power supply voltage VBAT2, and the emitter of the transistor QB2is a terminal that supplies the bias current IBIAS2_Fto the power transistor100_2.

InFIG.16, the bias current IBIAS1_Fmay change based on the control power supply voltage VBAT1_CTRL′. When the control power supply voltage VBAT1_CTRL′ decreases (becomes lower), the bias current IBIAS1_Falso decreases. As an example, when the control power supply voltage VBAT1_CTRL′ is lower than a predetermined threshold voltage, the transistor QB1does not operate (that is, the transistor QB1is turned off), which may cause the bias current IBIAS1_Fto be 0 mA.

When the control power supply voltage VBAT1_CTRL′ is the normal control power supply voltage VBAT1_CTRL_NORMAL′, the transistor QB1receives a normal power voltage. Due to this, the bias current IBIAS1_Falso has a normal value. In other words, the bias circuit200F_1generates the normal bias current IBIAS1_F_NORMAL

Due to the normal bias current IBIAS1_F_NORMAL, the power transistor100_1may perform a normal amplification operation.

When the transistor Q3is turned on due to an excessive output RF signal RFOUT1, the control power supply voltage VBAT1_CTRL′ becomes the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′. The transistor QB1receives the abnormal control power supply voltage VBAT1_CTRL_ABNORMAL′, which reduces the bias current IBIAS1_F. In other words, the bias circuit200F_1generates the abnormal bias current IBIAS1_F_ABNORMAL. Due to the abnormal bias current IBIAS1_F_ABNORMAL, the peak voltage applied to the power transistor100_1does not exceed a breakdown voltage. Through this, the power amplifier1000F may be protected from excessive RF signals.

The power amplifier1000F according to another example performs the protection operation only when the output RF signal RFOUT1is excessive (that is, abnormal) and does not perform the protection operation otherwise. That is, the transistor Q3ofFIG.16is turned on only when the output RF signal RFOUT1is excessive (that is, abnormal); otherwise it remains turned off. Since the transistor Q3does not continuously turn on and off, spurs due to oscillation may not occur.

InFIG.16, the electrostatic discharge protection circuit410F may be replaced with a capacitor. That is, as described with respect toFIG.6, the electrostatic discharge protection circuit410F may be replaced with a capacitor that couples and outputs a portion of the output RF signal RFOUT1to the anode of the diode D1as a detection RF signal.

As described above, according to at least one aspect, by adjusting the bias current in response to the magnitude of the output RF signal, the power amplifier may be protected from excessive RF signals.