Imaging panel and method for producing same

Provided is an X-ray imaging panel and a method for producing the same with improved productivity. An imaging panel 1 has an active area and a terminal area on a substrate 101. In the terminal area, there are provided: a first conductive layer 100; a terminal first insulating film 103 that is formed with the same material as that of a first insulating film in the active area, and has a first opening; a second conductive layer 1701 that is formed with the same material as that of a conductive film in the active area, and overlaps with the first conductive layer 100 at a position where the first opening is provided; and a cover layer provided at the position where the first opening is provided, so as to be arranged between the first conductive layer 100 and the second conductive layer 1701. The first conductive layer 100 is formed with the same material as that of any one of a gate electrode and a source electrode of a thin film transistor as well as a lower electrode in the active area. The cover layer is formed with the same material as that of at least one element arranged in an upper layer with respect to one element made of the same material as that of the first conductive layer 100 among the source electrode, the lower electrode, and a bias line in the active area.

TECHNICAL FIELD

The present invention relates to an imaging panel and a method for producing the same.

BACKGROUND ART

An X-ray imaging device that picks up an X-ray image with an imaging panel that includes a plurality of pixel portions is known. In such an X-ray imaging device, for example, projected X-rays are converted into charges by photodiodes. Converted charges are read out when thin film transistors (hereinafter also referred to as TFTs) are caused to operate, the TFTs being provided in the pixel portions. With the charges being read out in this way, an X-ray image is obtained. JP-A-2013-46043 discloses such an imaging panel. The photodiode in the configuration disclosed in JP-A-2013-46043 has a PIN structure in which an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer are laminated. On the photodiode, an upper electrode formed with a transparent conductive film is provided; and under the photodiode, a lower electrode containing a metal such as aluminum is provided. The upper electrode is connected with a common electrode line for supplying a bias voltage.

SUMMARY OF THE INVENTION

By the way, it is desirable that gate electrodes and source electrodes of thin film transistors, and terminals connected with bias lines for supplying a bias voltage are produced simultaneously in the process of producing the active area where the thin film transistors and the photodiodes are provided. However, in a case where conductive films used in pad portions of the terminals are made of the same materials as those used for forming the bias lines, electrodes of photodiodes, etc. formed in the active area, it is likely in some cases that the conductive films that are to become the pad portions of the terminals would disappear in an etching step in which the bias lines, the electrodes, etc. in the active area.

It is an object of the present invention to provide an X-ray imaging panel and a method for producing the same in which terminals are surely formed at the same time when an active area is produced, thereby enabling to improve the production efficiency.

An imaging panel of the present invention that solves the above-described problems is an imaging panel that generates an image based on scintillation light that is obtained from X-rays transmitted through an object, and the imaging panel includes a substrate and has an active area and a terminal area on the substrate, and further includes, in the active area: a thin film transistor formed on the substrate; a first insulating film provided on the thin film transistor; a lower electrode provided on the first insulating film; a photoelectric conversion layer that is provided on the lower electrode and converts the scintillation light into charges; an upper electrode provided on the photoelectric conversion layer; a second insulating film arranged on the upper electrode so as to have separation to have a contact hole; a conductive film that is arranged on the second insulating film and is connected with the upper electrode through the contact hole; and a bias line that is arranged on the second insulating film and is connected with the conductive film. The imaging panel still further includes, in the terminal area: a first conductive layer that is provided on the substrate and is connected with a gate electrode or a source electrode of the thin film transistor; a terminal first insulating film that is made of the same material as that of the first insulating film or the second insulating film, and is arranged so as to have separation on a part of the first conductive layer to have a first opening; a second conductive layer that is made of the same material as that of the conductive film, is provided above the terminal first insulating film, and overlaps with the first conductive layer at a position where the first opening is provided; and a cover layer that is arranged between the first conductive layer and the second conductive layer so as to overlap with the first conductive layer and the second conductive layer at the position where the first opening is provided, wherein the first conductive layer is made of the same material as that of any one element of the gate electrode, the source electrode, and the lower electrode, and the cover layer is made of the same material as that of at least one element arranged in an upper layer with respect to the element made of the same material as that of the first conductive layer, among the source electrode, the lower electrode, and the bias line.

According to the present invention, terminals are surely formed at the same time when an active area is produced, which enables to improve the production efficiency.

MODE FOR CARRYING OUT THE INVENTION

An imaging panel according to one embodiment of the present invention is an imaging panel that generates an image based on scintillation light that is obtained from X-rays transmitted through an object, and the imaging panel includes a substrate and has an active area and a terminal area on the substrate, and further includes, in the active area: a thin film transistor formed on the substrate; a first insulating film provided on the thin film transistor; a lower electrode provided on the first insulating film; a photoelectric conversion layer that is provided on the lower electrode and converts the scintillation light into charges; an upper electrode provided on the photoelectric conversion layer; a second insulating film arranged on the upper electrode so as to have separation to have a contact hole; a conductive film that is arranged on the second insulating film and is connected with the upper electrode through the contact hole; and a bias line that is arranged on the second insulating film and is connected with the conductive film. The imaging panel still further includes, in the terminal area: a first conductive layer that is provided on the substrate and is connected with a gate electrode or a source electrode of the thin film transistor; a terminal first insulating film that is made of the same material as that of the first insulating film or the second insulating film, and is arranged so as to have separation on a part of the first conductive layer to have a first opening; a second conductive layer that is made of the same material as that of the conductive film, is provided above the terminal first insulating film, and overlaps with the first conductive layer at a position where the first opening is provided; and a cover layer that is arranged between the first conductive layer and the second conductive layer so as to overlap with the first conductive layer and the second conductive layer at the position where the first opening is provided, wherein the first conductive layer is made of the same material as that of any one element of the gate electrode, the source electrode, and the lower electrode, and the cover layer is made of the same material as that of at least one element arranged in an upper layer with respect to the element made of the same material as that of the first conductive layer, among the source electrode, the lower electrode, and the bias line (the first configuration).

According to the first configuration, the imaging panel has an active area and a plurality of terminal areas. In the terminal area, the first conductive layer, the terminal first insulating film, the second conductive layer, and the cover layer are provided on the substrate. The first conductive layer is formed with the same material as that of the gate electrode, the source electrode, or the lower electrode in the active area, and the terminal first insulating film is formed with the same material as that of the first insulating film in the active area. The second conductive layer is provided above the terminal first insulating film, is formed with the same material as that of the conductive film in the active area, and overlaps with the first conductive layer at a position where the first opening is provided. The cover layer is formed with the same material as that of at least one element arranged in an upper layer with respect to the element made of the same material as that of the first conductive layer, among the source electrode, the lower electrode, and the bias line. The cover layer is arranged between the first conductive layer and the second conductive layer so as to overlap with the first conductive layer and the second conductive layer at the position where the first opening is provided. In other words, the first conductive layer, the cover layer, and the second conductive layer are connected at the position where the first opening is provided. For this reason, it is unlikely that the first conductive layer would disappear, in the etching carried out for forming at least an element in the active area made of the same material as that of the cover layer. This makes it easier to produce the terminal area simultaneously when the active area is formed, thereby enabling to improve the production efficiency of the imaging panel. Further, the first conductive layer, the cover layer, and the second conductive layer are connected at the position where the first opening is provided, that is, at the same position when viewed in a plan view. Therefore, connection defects can be decreased, as compared with a case where the first conductive layer, the cover layer, and the second conductive layer are connected at different positions.

The first configuration may be further characterized in that, in a case where the first conductive layer is made of the same material as that of the source electrode, the cover layer is composed of a lower electrode layer made of the same material as that of the lower electrode, and a bias line layer made of the same material as that of the bias line (the second configuration).

According to the second configuration, the first conductive layer made of the same material as that of the source electrode is covered with the cover layer including the lower electrode layer and the bias line layer. Etching carried out when the lower electrode and the bias line in the active area are formed therefore does not cause the first conductive layer to disappear.

The first configuration may be further characterized in that, in a case where the first conductive layer is made of the same material as that of the gate electrode, the cover layer is composed of at least two layers of a lower electrode layer made of the same material as that of the lower electrode, a bias line layer made of the same material as that of the bias line, and a source layer made of the same material as that of the source electrode (the third configuration).

According to the third configuration, the first conductive layer made of the same material as that of the gate electrode is covered with the cover layer composed of at least two layers of the lower electrode layer, the bias line layer, and the source layer. It is therefore unlikely that the first conductive layer would disappear in etching carried out for forming the source electrode, the lower electrode, and the bias line in the active area.

Any one of the first to third configurations may be further characterized in that a plurality of terminals are provided in the terminal area, and in the terminal area, the first conductive layer in an area where at least one of the terminals is provided is connected with the gate electrode, and the first conductive layer in an area where another one of the terminals is provided is connected with the source electrode (the fourth configuration).

According to the fourth configuration, a plurality of terminals can be simultaneously produced in the step of forming the active area, which makes it possible to improve the production efficiency of the imaging panel.

Any one of the first to fourth configurations may be further characterized in that the gate electrode and the source electrode of the thin film transistor, the lower electrode, as well as the bias line contain one same material (the fifth configuration).

According to the fifth configuration, the lower electrode layer and the bias line layer made of the same material as that of the lower electrode and the bias line, respectively, are arranged on the first conductive layer so as to overlap. Etching carried out when the lower electrode and the bias line are formed therefore does not cause the first conductive layer to disappear.

An imaging panel producing method according to one embodiment of the present invention is a method for producing an imaging panel that generates an image based on scintillation light that is obtained from X-rays transmitted through an object, and the method includes the steps of, in an active area on a substrate: forming a thin film transistor; forming a first insulating film on the thin film transistor; forming, on a drain electrode of the thin film transistor, a first contact hole that passes through the first insulating film, and forming a lower electrode conductive film that covers the first insulating film; etching the lower electrode conductive film, so as to form a lower electrode on the first insulating film so that the lower electrode is connected with the drain electrode through the first contact hole; forming a photoelectric conversion layer on the lower electrode, and forming an upper electrode on the photoelectric conversion layer; forming a second insulating film that covers the upper electrode, and forming a second contact hole that pass through the second insulating film; forming a bias line conductive film above the second insulating film, and etching the bias line conductive film, so as to form a bias line to which a bias voltage is applied; and forming a conductive film that is connected with the upper electrode through the second contact hole. In the method, the step of forming the thin film transistor or the step of forming the lower electrode includes a sub-step of forming a first conductive layer in a terminal area on the substrate, the first conductive layer being made of the same material as that of any one element of the gate electrode and the source electrode of the thin film transistor, and the lower electrode; the step of forming the first insulating film or the step of forming the second insulating film includes a sub-step of forming a terminal first insulating film that is made of the same material as that of the first insulating film or the second insulating film and has a first opening on a part of the first conductive layer; the step of forming the conductive film includes a sub-step of forming a second conductive layer that is made of the same material as that of the conductive film and overlaps with the first conductive layer above the terminal first insulating film, at a position where the first opening is provided; and the step of forming at least one element arranged in an upper layer with respect to the element made of the same material as that of the first conductive layer, the at least one element being among the source electrode, the lower electrode, and the bias line, includes a sub-step of forming a cover layer that is made of the same material as that of the at least one element, and is arranged at a position where the first opening is provided, so as to be interposed between the first conductive layer and the second conductive layer (the first producing method).

According to the first producing method, in the terminal area, the first conductive layer, the terminal first insulating film, the second conductive layer and the cover layer are provided on the substrate. The first conductive layer is made of the same material as that of the gate electrode, the source electrode, or the lower electrode in the active area, and the terminal first insulating film is formed with the same material as that of the first insulating film in the active area. The second conductive layer is provided above the terminal first insulating film, is formed with the same material as that of the conductive film in the active area, and overlaps with the first conductive layer at a position where the first opening is provided. The cover layer is formed with the same material as that of at least one element arranged in an upper layer with respect to the element made of the same material as that of the first conductive layer, among the source electrode, the lower electrode, and the bias line. The cover layer is arranged between the first conductive layer and the second conductive layer so as to overlap with the first conductive layer and the second conductive layer at the position where the first opening is provided. In other words, the first conductive layer, the cover layer, and the second conductive layer are connected at the position where the first opening is provided.

For this reason, it is unlikely that the first conductive layer would disappear, in the etching carried out for forming at least an element in the active area made of the same material as that of the cover layer. This makes it easier to produce the terminal area simultaneously when the active area is formed, thereby enabling to improve the production efficiency of the imaging panel. Further, the first conductive layer, the cover layer, and the second conductive layer are connected at the position where the first opening is provided, that is, at the same position when viewed in a plan view. Therefore, connection defects can be suppressed, as compared with a case where the first conductive layer, the cover layer, and the second conductive layer are connected at different positions.

The first producing method may be further characterized in that the first conductive layer contains such a material that, in etching that is carried out in the step of forming the element arranged in an upper layer with respect to the element made of the same material as that of the first conductive layer, among the source electrode, the lower electrode, and the bias line, an etch selectivity of the material with respect to the former element is high (the second producing method).

With the second producing method, the first conductive layer does not disappear in the etching carried in the step of forming an element arranged in an upper layer with respect to a layer where the first conductive layer is provided, among the source electrode, the lower electrode, and the bias line layer.

A lowermost layer in the cover layer in contact with the first conductive layer may contain such a material that, in etching that is carried out in the step of forming an element arranged in an upper layer with respect to an element made of the same material as that of the lowermost layer among the source electrode, the lower electrode, and the bias line, an etch selectivity of the material with respect to the former element is high (the third producing method).

With the third producing method, in the etching carried in the step of forming an element arranged in an upper layer with respect to the lowermost layer in the cover layer, among the source electrode, the lower electrode, and the bias line layer, the lowermost layer does not disappear, and the first conductive layer does not disappear, either.

The third producing method may be further characterized in that the cover layer includes a source layer that is formed in the step in which the source electrode of the thin film transistor is formed and is made of the same material as that of the source electrode, and a bias line layer that is formed in the step in which the bias line is formed and is made of the same material as that of the bias line. In the terminal area, in the step of forming the second insulating film, a terminal second insulating film that is made of the same material as that of the second insulating film, covers the terminal first insulating film, and has a second opening inside the first opening, is formed; the source layer is connected with the first conductive layer at the first opening; the terminal first insulating film is formed on a part of the source layer; the bias line layer is formed on the terminal second insulating film, and is connected with the source layer at the second opening; and the second conductive layer is connected with the first conductive layer at the second opening, which overlaps with the first opening, via the cover layer (the fourth producing method).

According to the fourth producing method, the second opening in the terminal second insulating film is provided inside the first opening in the terminal first insulating film. This makes it possible to surely connect the first conductive layer and the second conductive layer at a position where the first opening and the second opening overlap, via the source layer and the bias line layer.

The fourth producing method may be further characterized in that the source electrode and the source layer are formed by laminating a first material that exhibits a high etch rate in etching carried out when the lower electrode is formed, and a second material that exhibits a low etch rate in the etching; the second insulating film and the terminal second insulating film have a thickness greater than that of the film of the first material; and the bias line and the bias line layer are formed with a plurality of layers containing the first material, and the bias line and the bias line layer have a thickness greater than that of the film of the first material in the source electrode and the source layer (the fifth producing method).

According to the fifth producing method, the first material in the source layer is easily etched in the etching carried out when the lower electrode is formed, but the thickness of the terminal second insulating film and the bias line layer is greater than the thickness of the film of the first material in the source layer. In a case where the terminal first insulating film is formed so as to overlap with a part of the source layer, even if the first material in the source layer disappear in the etching carried out when the lower electrode is formed and clearance is formed between the terminal first insulating film and the source layer, the clearance portion can be covered with the terminal second insulating film. Besides, a part of the terminal second insulating film and the second opening can be surely covered with the bias line layer, which makes it possible to allow second conductive layer to be surely connected with the first conductive layer, via the bias line layer and the source layer at the second opening.

The first producing method may be further characterized in that the element not used for forming the cover layer, among the source electrode, the lower electrode, and the bias line, has a laminate structure obtained by laminating a plurality of materials, and in etching carried out in the step of forming the said element, an etch selectivity of the lowermost layer of the laminate structure with respect to elements provided in a lower layer with respect to the said element is low (the sixth producing method).

According to the sixth producing method, the material in the lowermost layer among the materials of the element not used for forming the cover layer is more easily etched as compared with an element provided in a lower layer with respect to the said element, and the time required for etching the same is short. It is therefore unlikely that the first conductive layer, which is to become the cover layer and the pad portion, would disappear.

The following description describes embodiments of the present invention in detail, while referring to the drawings. Identical or equivalent parts in the drawings are denoted by the same reference numerals, and the descriptions of the same are not repeated.

FIG. 1is a schematic diagram showing an X-ray imaging device in the present embodiment. The X-ray imaging device1000includes an imaging panel1and a control unit2. The control unit2includes a gate control unit2A and a signal reading unit2B. X-rays are irradiated from the X-ray source3to an object S, and X-rays transmitted through the object S are converted into fluorescence (hereinafter referred to as scintillation light) by a scintillator1A provided above the imaging panel1. The X-ray imaging device1000acquires an X-ray image by picking up the scintillation light with the imaging panel1and the control unit2.

FIG. 2is a schematic diagram showing a schematic configuration of the imaging panel1. As shown inFIG. 2, a plurality of source lines10, and a plurality of gate lines11intersecting with the source lines10are formed in the imaging panel1. The gate lines11are connected with the gate control unit2A, and the source lines10are connected with the signal reading unit2B.

The imaging panel1includes TFTs13connected to the source lines10and the gate lines11, at positions at which the source lines10and the gate lines11intersect. Further, photodiodes12are provided in areas surrounded by the source lines10and the gate lines11(hereinafter referred to as pixels). In each pixel, scintillation light obtained by converting X-rays transmitted through the object S is converted by the photodiode12into charges according to the amount of the light.

The gate lines11in the imaging panel1are sequentially switched by the gate control unit2A into a selected state, and the TFT13connected to the gate line11in the selected state is turned ON. When the TFT13is turned ON, a signal according to the charges obtained by the conversion by the photodiode12is output through the source line10to the signal reading unit2B.

FIG. 3Ais an enlarged plan view of one pixel portion of the imaging panel1shown inFIG. 2. As shown inFIG. 3A, in the pixel surrounded by the gate lines11and the source lines10, a lower electrode14a, a photoelectric conversion layer15, and an upper electrode14bthat compose the photodiode12are arranged so as to overlap with one another. Further, a bias line16is arranged so as to overlap with the gate line11and the source line10when viewed in a plan view. The bias line16supplies a bias voltage to the photodiode12. The TFT13includes a gate electrode13aintegrated with the gate line11, a semiconductor active layer13b, a source electrode13cintegrated with the source line10, and a drain electrode13d. In the pixel, a contact hole CH1for connecting the drain electrode13dand the lower electrode14awith each other is provided. Further, in the pixel, a transparent conductive film17is provided so as to overlap with the bias line16, and a contact hole CH2for connecting the transparent conductive film17and the upper electrode14bwith each other is provided.

Here,FIG. 3Bshows a cross section of the pixel shown inFIG. 3A, taken along a line A-A. As shown inFIG. 3B, the TFT13is formed on the substrate101. The substrate101is a substrate having insulating properties, for example, a glass substrate, a silicon substrate, a plastic substrate having heat-resisting properties, a resin substrate, or the like.

Further, on the substrate101, the gate electrode13aintegrated with the gate line11is formed. The gate electrode13aand the gate line11are made of, for example, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), molybdenum nitride (MoN), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), an alloy of any of these metals, or a metal nitride of these metals. In the present embodiment, the gate electrode13aand the gate line11have a laminate structure in which a metal film made of molybdenum nitride and a metal film made of aluminum are laminated in this order. Regarding thicknesses of these metal films, for example, the metal film made of molybdenum nitride has a thickness of 100 nm, and the metal film made of aluminum has a thickness of 300 nm.

A gate insulating film102is provided on the substrate101, and covers the gate electrode13a. The gate insulating film102may be formed with, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide nitride (SiOxNy) (x>y), or silicon nitride oxide (SiNxOy) (x>y). In the present embodiment, the gate insulating film102is formed with a laminate film obtained by laminating silicon oxide (SiOx) and silicon nitride (SiNx) in the order, and regarding the thicknesses of these films, the film of silicon oxide (SiOx) has a thickness of 50 nm, and the film of silicon nitride (SiNx) has a thickness of 400 nm.

The semiconductor active layer13b, as well as the source electrode13cand the drain electrode13dconnected with the semiconductor active layer13bare formed on the gate electrode13awith the gate insulating film102being interposed therebetween.

The semiconductor active layer13bis formed in contact with the gate insulating film102. The semiconductor active layer13bis made of an oxide semiconductor. For forming the oxide semiconductor, for example, the following material may be used: InGaO3(ZnO)5; magnesium zinc oxide (MgxZn1-xO); cadmium zinc oxide (CdxZn1-xO); cadmium oxide (CdO); InSnZnO (containing indium (In), tin (Sn), and zinc (Zn)); material based on indium (In)-aluminum (Al)-zinc (Zn)-oxygen (O); or an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) at a predetermined ratio. Further, as an oxide semiconductor, “amorphous” materials, and “crystalline” materials (including polycrystalline materials, microcrystalline materials, and c-axis alignment crystalline materials) are applicable. In the case of the laminate structure, any combination is applicable (any particular combination is not excluded). In the present embodiment, the semiconductor active layer13bis made of an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) at a predetermined ratio, and has a thickness of, for example, 70 nm. By applying a semiconductor active layer13b, and an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O), off-leakage current of the TFT13can be reduced, as compared with amorphous silicon (a-Si). When off-leakage current of the TFT13is small, off-leakage current of the photoelectric conversion layer15is reduced, whereby quantum efficiency (QE) of the photoelectric conversion layer15is improved, which results in that the X-ray detection sensitivity can be improved.

The source electrode13cand the drain electrode13dare formed in contact with the semiconductor active layer13band the gate insulating film102. The source electrode13cis integrated with the source line10. The drain electrode13dis connected with the lower electrode14athrough the contact hole CH1.

The source electrode13cand the drain electrode13dare formed in the same layer, and are made of, for example, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or alternatively, an alloy of any of these, or a metal nitride of any of these. Further, as the material for the source electrode13cand the drain electrode13d, the following material may be used: a material having translucency such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide (ITSO) containing silicon oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), or titanium nitride; or a material obtained by appropriately combining any of these.

The source electrode13cand the drain electrode13dmay be, for example, a laminate of a plurality of metal films. More specifically, the source electrode13c, the source line10, and the drain electrode13dhave a laminate structure in which a metal film made of molybdenum nitride (MoN), a metal film made of aluminum (Al), and a metal film made of molybdenum nitride (MoN) are laminated in this order. Regarding the thicknesses of the films, the metal film in the lower layer, which is made of molybdenum nitride (MoN), has a thickness of 100 nm, the metal film made of aluminum (Al) has a thickness of 500 nm, and the metal film in the upper layer, which is made of molybdenum nitride (MoN), has a thickness of 50 nm.

A first insulating film103is provided so as to cover the source electrode13cand the drain electrode13d. The first insulating film103may have a single layer structure made of silicon oxide (SiO2) or silicon nitride (SiN), or a laminate structure obtained by laminating silicon nitride (SiN) and silicon oxide (SiO2) in this order.

On the first insulating film103, a second insulating film104is formed. The second insulating film104is made of an organic transparent resin, for example, acrylic resin or siloxane-based resin, and has a thickness of, for example, 2.5 μm.

On the drain electrode13d, the contact hole CH1, passing through the second insulating film104and the first insulating film103, is formed.

The lower electrode14aconnected with the drain electrode13dthrough the contact hole CH1is formed on the second insulating film104. The lower electrode14ais formed with, for example, a metal film made of molybdenum nitride (MoN), and has a thickness of, for example, 200 μm.

Further, the photoelectric conversion layer15, whose width in X-axis direction is smaller than that of the lower electrode14a, is formed on the lower electrode14a. The photoelectric conversion layer15has a PIN structure that is obtained by laminating an n-type amorphous semiconductor layer151, an intrinsic amorphous semiconductor layer152, and a p-type amorphous semiconductor layer153in the order.

The n-type amorphous semiconductor layer151is made of amorphous silicon doped with an n-type impurity (for example, phosphorus). The n-type amorphous semiconductor layer151has a thickness of, for example, 30 nm.

The intrinsic amorphous semiconductor layer152is made of intrinsic amorphous silicon. The intrinsic amorphous semiconductor layer152is formed in contact with the n-type amorphous semiconductor layer151. The intrinsic amorphous semiconductor layer has a thickness of, for example, 1000 nm.

The p-type amorphous semiconductor layer153is made of amorphous silicon doped with a p-type impurity (for example, boron). The p-type amorphous semiconductor layer153is formed in contact with the intrinsic amorphous semiconductor layer152. The p-type amorphous semiconductor layer153has a thickness of, for example, 5 nm.

On the p-type amorphous semiconductor layer153, the upper electrode14bis formed. The upper electrode14bhas a smaller width in the X-axis direction than that of the photoelectric conversion layer15. The upper electrode14bis made of, for example, indium tin oxide (ITO), and has a thickness of, for example, 70 nm.

A third insulating film105is formed so as to cover the photodiode12. The third insulating film105is, for example, an inorganic insulating film made of silicon nitride (SiN), and has a thickness of, for example, 300 nm.

In the third insulating film105, a contact hole CH2is formed at such a position that the contact hole CH2overlaps with the upper electrode14b. On the third insulating film105, in an area thereof except for the contact hole CH2, a fourth insulating film106is formed. The fourth insulating film106is formed with an organic transparent resin made of, for example, acrylic resin or siloxane-based resin, and has a thickness of, for example, 2.5 μm.

On the fourth insulating film106, the bias line16is formed. Further, on the fourth insulating film106, the transparent conductive film17is formed so as to overlap with the bias line16. The transparent conductive film17is in contact with the upper electrode14bat the contact hole CH2. The bias line16is connected to the control unit2(seeFIG. 1). The bias line16applies a bias voltage through the contact hole CH2to the upper electrode14b, the bias voltage being input from the control unit2. The bias line16has a laminate structure that is obtained by laminating, for example, a metal film made of molybdenum nitride (MoN), a metal film made of aluminum (Al), and a metal film made of titanium (Ti) in this order. The films of molybdenum nitride (MoN), aluminum (Al), and titanium (Ti) have thicknesses of, for example, 100 nm, 300 nm, and 50 nm, respectively.

On the fourth insulating film106, a fifth insulating film107is formed so as to cover the transparent conductive film17. The fifth insulating film107is an inorganic insulating film made of, for example, silicon nitride (SiN), and has a thickness of, for example, 200 nm.

On the fifth insulating film107, a sixth insulating film108is formed. The sixth insulating film108is made of, for example, an organic transparent resin such as acrylic resin or siloxane-based resin, and has a thickness of, for example, 2.0 μm.

FIGS. 4A and 4Bare enlarged plan views of a part of an area outside the pixel area (hereinafter referred to as an “active area”) of the imaging panel1.FIG. 4Ashows an area (G terminal area) where the following are provided: a terminal (hereinafter referred to as a G terminal)31for connecting the gate electrode13aand the gate line11shown inFIG. 3Awith the gate control unit2A (seeFIG. 1); and a contact (S-G contact)40A for connecting the G terminal31and the gate line11.

FIG. 4Bshows the following areas: an area where a terminal (hereinafter referred to as an “S terminal”)32for connecting the source electrode31cand the source line10shown inFIG. 3Awith the signal reading part2B (seeFIG. 1), and a terminal (hereinafter referred to as a “B terminal”)33for connecting the bias line16shown inFIG. 3Awith the control unit2, are provided; and an area (SB terminal area) where a contact (hereinafter referred to as an “S-B contact”)40B for connecting the B terminal33with the bias line16is provided.

FIG. 5Ais a cross-sectional view of the G terminal31taken along line B-B, as well as the S terminal32and the B terminal33taken along line B′-B′ shown inFIGS. 4A and 4B.FIG. 5Bis a cross-sectional view of the S-G contact40A shown inFIG. 4A, taken along line C-C, andFIG. 5Cis a cross-sectional view of the S-B contact40B shown inFIG. 4B, taken along line D-D. The following description describes the configurations of the G terminal31, the S terminal32, the B terminal33, the S-G contact40A, and the S-B contact40B, while referring toFIGS. 5A to 5C.

As shown inFIG. 5A, the G terminal31, the S terminal32, and the B terminal33(hereinafter referred to as terminals31to33, respectively) have a common structure.

More specifically, each of the terminals31to33has such a configuration that a gate insulating film102is arranged on the substrate101. The gate insulating film102is integrally provided with the gate insulating film102provided in the active area (seeFIG. 3B).

On the gate insulating film102, a source layer100is arranged. The source layer100is formed with the same material as that for the source electrode13cand the source line10provided in the active area (seeFIG. 3A).

On the source layer100, the first insulating film103is arranged so as to have separation so that the contact hole CH3(CH3a, CH3b, CH3b) is provided. The first insulating film103in each of the terminals31to33is formed integrally with the first insulating film103provided in the active area (seeFIG. 3B).

On the first insulating film103, a lower electrode layer1401connected with the source layer100through the contact hole CH3is arranged. The lower electrode layer1401is formed with the same material as that of the lower electrode14aprovided in the active area (seeFIG. 3B).

On the lower electrode layer1401and the first insulating film103, the third insulating film105is arranged. The third insulating film105in each of the terminals31to33is integrally formed with the third insulating film105provided in the active area (seeFIG. 3B).

On the third insulating film105, a bias line layer1601connected with the lower electrode layer1401at the contact hole CH3is arranged. The bias line layer1601is formed with the same material as that of the bias line16provided in the active area (seeFIG. 3B).

On the bias line layer1601, a transparent conductive film1701is arranged. The transparent conductive film1701is formed with the same material as that of the transparent conductive film17provided in the active area (seeFIG. 3B).

On the transparent conductive film1701, outside the contact hole CH3, the fifth insulating film107is arranged so as to have separation. The fifth insulating film107in each of the terminals31to33is integrally formed with the fifth insulating film107provided in the active area (seeFIG. 3B).

As shown inFIG. 4A, the source layer100in the G terminal31is connected with the gate line11at the S-G contact40A. As shown inFIG. 5B, in the S-G contact40A, a gate layer110amade of the same material as that of the gate line11is arranged on the substrate101, and a gate insulating film102is arranged on the gate layer110aso as to have separation so that a contact hole CH4ais formed. On the gate insulating film102, a source layer100aconnected with the gate layer110athrough the contact hole CH4ais arranged. The source layer100ais formed with the same material as that of the source layer100.

On the source layer100a, the first insulating film103is arranged so as to cover the source layer100a. On the first insulating film103, the following are laminated in the stated order: the second insulating film104; the third insulating film105; the fourth insulating film106; the fifth insulating film107; and the sixth insulating film108. The first insulating film103, the second insulating film104, the third insulating film105, the fourth insulating film106, the fifth insulating film107, and the sixth insulating film108in the S-G contact40A are formed with the same materials as those of the first insulating film103, the second insulating film104, the third insulating film105, the fourth insulating film106, the fifth insulating film107, and the sixth insulating film108arranged in the active area, respectively (seeFIG. 3B).

As shown inFIG. 4B, the source layer100in the B terminal33is connected with the bias line16at the S-B contact40B. In the S-B contact40B, as shown inFIG. 5C, the source layer100aand the transparent conductive film160aformed with the same material as that of the bias line16are connected through a contact hole CH4b. On the source layer100a, the following are laminated in the stated order: the first insulating film103; the second insulating film104; the third insulating film105; the fourth insulating film106; the fifth insulating film107; and the sixth insulating film108. The contact hole CH4bpasses through the first insulating film103, the second insulating film104, the third insulating film105, the fourth insulating film106, and the fifth insulating film107, on the source layer100a. The first insulating film103, the second insulating film104, the third insulating film105, the fourth insulating film106, the fifth insulating film107, and the sixth insulating film108in the S-B contact40B are formed with the same materials as those of the first insulating film103, the second insulating film104, the third insulating film105, the fourth insulating film106, the fifth insulating film107, and the sixth insulating film108arranged in the active area, respectively (seeFIG. 3B).

(Method for Producing Imaging Panel1)

Next, the following description describes a method for producing the imaging panel1.FIGS. 6A to 6Uare cross-sectional views that respectively show steps in the process for producing the TFT area where the TFT13is provided, and the terminal area where the terminals31to33are provided, in the active area of the imaging panel1.

As shown inFIG. 6A, a metal film made of molybdenum nitride and a metal film made of aluminum are formed on the substrate101in the stated order by, for example, sputtering. Photolithography and wet etching are carried out so that the metal film is patterned. Through these steps, the gate electrode13ais formed in the TFT area. Simultaneously when the gate electrode13ais formed, the gate line11(seeFIG. 3A) is formed. Then, the gate insulating film102obtained by laminating silicon oxide (SiOx) and silicon nitride (SiNx) in the order is formed so as to cover the gate electrode13a. Thereafter, on the gate insulating film102, the semiconductor layer130formed with amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) at a predetermined ratio is formed.

Subsequently, photolithography and dry etching are carried out so that the semiconductor layer130is patterned, whereby the semiconductor active layer13bis formed in the TFT area and the semiconductor layer130in the terminal area is removed. Thereafter, films of molybdenum nitride (MoN), aluminum (Al), and molybdenum nitride (MoN) are laminated in the order by, for example, sputtering on the gate insulating film102in the TFT area and the terminal area so as to cover the semiconductor active layer13b. Then, photolithography and wet etching are carried out so that these metal films are patterned. Through these steps, in the TFT area, the source electrode13cand the drain electrode13dare formed so as to be separated from each other on the semiconductor active layer13b, whereby the TFT13is formed. Further, in the terminal area, the source layer100is formed on the gate insulating film102. Then, the first insulating film103made of silicon nitride (SiN) is formed so as to cover the TFT13and the source layer100by, for example, plasma CVD (seeFIG. 6B).

Subsequently, a heat treatment at about 350° C. is applied to an entire surface of the substrate101, and photolithography and wet etching are carried out so that the first insulating film103is patterned. Through these steps, a contact hole CH1is formed on the drain electrode13din the TFT area, and an opening103ain the first insulating film103is formed on the source layer100in the terminal area (seeFIG. 6C).

Next, the second insulating film104made of acrylic resin or siloxane-based resin is formed on the first insulating film103by, for example, slit coating (seeFIG. 6D).

Then, an opening104aof the second insulating film104is formed by photolithography on the contact hole CH1in the TFT area, and the second insulating film104in the terminal area is removed (seeFIG. 6E).

Subsequently, a metal film140made of molybdenum nitride (MoN) is formed in the TFT area and the terminal area by, for example, sputtering so as to cover the second insulating film104in the TFT area (seeFIG. 6F).

Then, photolithography and wet etching are carried out so that the metal film140is patterned. Through these steps, on the second insulating film104in the TFT area, there is formed the lower electrode14athat is connected with the drain electrode13dthrough the contact hole CH1. Further, on the first insulating film103in the terminal area, there is formed the lower electrode layer1401that is connected with the source layer100through the opening103a. Here, as the lower electrode layer1401is formed in the terminal area, the source layer100in the terminal area is not etched by the wet etching carried out when the lower electrode14ais formed, resulting in that the source layer100in the terminal area does not disappear. Subsequently, the n-type amorphous semiconductor layer151, the intrinsic amorphous semiconductor layer152, and the p-type amorphous semiconductor layer153are formed in the stated order by, for example, plasma CVD, so as to cover the lower electrode14aand the lower electrode layer1401. Then, on the p-type amorphous semiconductor layer153, a transparent conductive film240made of, for example, ITO is formed (seeFIG. 6G).

Thereafter, photolithography and dry etching are carried out so as to pattern the transparent conductive film240. Through these steps, the upper electrode14bis formed on the p-type amorphous semiconductor layer153in the TFT area, and the p-type amorphous semiconductor layer153, the intrinsic amorphous semiconductor layer152, the n-type amorphous semiconductor layer153, and the transparent conductive film240in the terminal area are removed (seeFIG. 6H).

Subsequently, photolithography and dry etching are carried out so that the p-type amorphous semiconductor layer153, the intrinsic amorphous semiconductor layer152, and the n-type amorphous semiconductor layer153are patterned. Through these steps, in the TFT area, the photoelectric conversion layer15having a width in the X-axis direction that is smaller than that of the lower electrode14aand that is greater than that of the upper electrode14bis formed (seeFIG. 6I).

Next, the third insulating film105made of silicon nitride (SiN) is formed in the TFT area and the terminal area by, for example, plasma CVD, so as to cover the photoelectric conversion layer15(seeFIG. 6J).

Thereafter, photolithography and wet etching are carried out so that the third insulating film105is patterned. Through these steps, the contact hole CH2passing through the third insulating film105is formed on the upper electrode14bin the TFT area. Further, an opening105ain the third insulating film105is formed at a position that overlaps with the opening103a, on the lower electrode layer1401in the terminal area. Through these steps, a contact hole CH3including the opening103aand the opening105ais formed in the terminal area (seeFIG. 6K).

Subsequently, the fourth insulating film106made of acrylic resin or siloxane-based resin is formed so as to cover the third insulating film105by, for example, slit coating (seeFIG. 6L).

Thereafter, photolithography and wet etching are carried out so that the fourth insulating film106is patterned. Through these steps, an opening106ain the fourth insulating film106is formed on the contact hole CH2in the TFT area, and the fourth insulating film106in the terminal area is removed (seeFIG. 6M).

Next, a metal film160is formed by laminating molybdenum nitride (MoN), aluminum (Al), and titanium (Ti) in this order by, for example, sputtering, so as to cover the fourth insulating film106in the TFT area, as well as the third insulating film105in the terminal area (seeFIG. 6N).

Then, photolithography and wet etching are carried out so that the metal film160is patterned. Through these steps, the bias line16is formed in the TFT area, and the bias line layer1601connected with the lower electrode layer1401at the contact hole CH3is formed in the terminal area (seeFIG. 6O). As the bias line layer1601connected with the lower electrode layer1401is formed in the terminal area, the source layer100in the terminal area is covered with the lower electrode layer1401and the bias line layer1601. As a result, the source layer100in the terminal area is not etched by wet etching carried out for forming the bias line16, and therefore, does not disappear.

Subsequently, the transparent conductive film170made of ITO is formed by, for example, sputtering so as to cover the fourth insulating film106and the bias line16in the TFT area, as well as the third insulating film105and the bias line layer1601in the terminal area (seeFIG. 6P).

Then, photolithography and dry etching are carried out so as to pattern the transparent conductive film170. Through these steps, the transparent conductive film17that is connected with the bias line16in the TFT area and connected with the upper electrode14bthrough the contact hole CH2is formed. Further, in the terminal area, the transparent conductive film1701is formed, which is connected with the bias line layer1601at the contact hole CH3(seeFIG. 6Q).

Next, the fifth insulating film107made of silicon nitride (SiN) is formed by, for example, plasma CVD so as to cover the transparent conductive films17,1701in the TFT area and the terminal area (seeFIG. 6R).

Then, photolithography and wet etching are carried out so that the fifth insulating film107is patterned. Through these steps, an opening107ain the fifth insulating film107is formed in an area where the contact hole CH3is provided, on the transparent conductive film1701in the terminal area (seeFIG. 6S).

Subsequently, the sixth insulating film108made of acrylic resin or siloxane-based resin is formed on the fifth insulating film107by, for example, slit coating (seeFIG. 6T).

Thereafter, photolithography and dry etching are carried out to the sixth insulating film108so that parts of the sixth insulating film108in the terminal area are removed (seeFIG. 6U).

What is described above is the method for producing the imaging panel1in Embodiment 1. In the present embodiment, the terminals31to33have a common structure. In the terminal area where these terminals are formed, in the contact hole CH3on the source layer100that is to become a pad portion, a laminate of the lower electrode layer1401, the bias line layer1601, and the transparent conductive film1701is arranged a layer covering the pad portion. Since the source layer100contains the same material as that of the lower electrode14aor that of the bias line16, in a case where the surface of the source layer100is not covered with the lower electrode layer1401or the bias line layer1601, the source layer100is etched by wet etching carried out when the lower electrode14aor the bias line16is formed. The source layer100in the terminal area is covered with the lower electrode layer1401and the bias line layer1601in Embodiment 1 as mentioned above, and this allows the source layer100not to disappear, even if wet etching is carried out when the lower electrode14aor the bias line16is formed. This makes it possible to surely form each terminal in the process for producing the TFT area.

Moreover, each of the terminals31to33in the present embodiment has such a configuration that the source layer100, the lower electrode layer1401, the bias line layer1601, and the transparent conductive film1701are formed so as to be laminated in one contact hole CH3. In other words, in each of these terminals, these layers are connected in one common contact hole. In contrast, for example, in a case where contact holes for achieving the connection between the source layer100and the lower electrode layer1401, the connection between the lower electrode layer1401and the bias line layer1601, and the connection between the bias line layer1601and the transparent conductive film1701are provided at different positions, respectively, each layer has reconnection. In this case, it is likely that the reconnections of the layers would cause connection defects in the terminals. In the present embodiment, however, since there are not such reconnections of the layers, it is unlikely that connection defects would occur in the terminals.

Here, operations of the X-ray imaging device1000shown inFIG. 1are described. First, X-rays are emitted from the X-ray source3. Here, the control unit2applies a predetermined voltage (bias voltage) to the bias line16(seeFIG. 3Aand the like). X-rays emitted from the X-ray source3are transmitted through an object S, and are incident on the scintillator1A. The X-rays incident on the scintillator1A are converted into fluorescence (scintillation light), and the scintillation light is incident on the imaging panel1. When the scintillation light is incident on the photodiode12provided in each pixel in the imaging panel1, the scintillation light is changed to charges by the photodiode12in accordance with the amount of the light. A signal according to the charges obtained by converting of the photodiode12is read out through the source line10to the signal reading unit2B (seeFIG. 2and the like) when the TFT13(seeFIG. 3Aand the like) is in the ON state according to a gate voltage (positive voltage) that is output from the gate control unit2A through the gate line11. Then, an X-ray image in accordance with the signal thus read out is generated in the control unit2.

Modification Example

The G terminal31, the S terminal32, and the B terminal33in Embodiment 1 described above are described with reference to an exemplary configuration in which the source layer100is provided in the pad portion of the terminal, but the configuration may be such that a gate layer made of the same material as that of the gate electrode13ais used in place of the source layer100.

FIG. 7is a cross-sectional view showing the structure of the G terminal311, the S terminal312, and the B terminal313in the present modification example. InFIG. 7, the same constituent members as those in Embodiment 1 are denoted by the same reference symbols as those in Embodiment 1.

As shown inFIG. 7, each of the G terminal311, the S terminal312, and the B terminal313in the present modification example has such a configuration that a gate layer110made of the same material as that of the gate electrode13aand the gate line11is arranged on the substrate101, and the gate insulating film102is arranged on the gate layer110so as to have separation. On the gate insulating film102, the first insulating film103is arranged, and an opening CHa that passes through the gate insulating film102and the first insulating film103is formed therein. The lower electrode layer1401is arranged on the first insulating film103so as to be in contact with the gate layer110through the contact hole CH31. The third insulating film105having the opening105aat a position that overlaps with the opening CHa is arranged on the first insulating film103and the lower electrode layer1401, whereby a contact hole CH31composed of the openings CHa and105ais formed. Further, the bias line layer1601that is connected with the lower electrode layer1401at the contact hole CH31is arranged on the third insulating film105. On the third insulating film105, the transparent conductive film1701is arranged so as to cover the bias line layer1601, and the fifth insulating film107is arranged on the transparent conductive film1701, on an outer side with respect to the contact hole CH31.

In the present modification example, after the gate layer110is formed, the gate insulating film102is formed so as to cover the gate layer110, and a metal film that will form the source electrode13cand the drain electrode13dis formed on the gate insulating film102. As to the metal film that will form the source electrode13cand the drain electrode13d, parts thereof provided in the terminal area are removed by wet etching carried out when the source electrode13cand the drain electrode13dare formed. Here, the wet etching does not cause the gate layer110to disappear, because the gate insulating film102is provided on the gate layer110.

Incidentally, in this case, the gate layer110and the gate line11are formed with the same material, which makes a contact for connecting the G terminal311and the gate line11unnecessary. On the other hand, the S terminal312is connected to an S-G contact that is similar to the S-G contact40A shown inFIG. 5B, so that the gate layer110in the S terminal312and the source line10are connected. The B terminal313is connected to a contact (G-B contact) that connects the gate layer110and the bias line16with each other.

FIG. 8is a cross-sectional view showing a structure of the G-B contact. As shown inFIG. 8, at the G-B contact40C, the gate layer110bmade of the same material as that of the gate line11, and the transparent conductive film160bmade of the same material as that of the bias line16are connected through a contact hole CH4c. On the gate layer110b, the following are laminated in the stated order: the gate insulating film102; the first insulating film103; the second insulating film104; the third insulating film105; the fourth insulating film106; the fifth insulating film107; and the sixth insulating film108. On the gate layer110b, the contact hole CH4cpasses through the gate insulating film102, the first insulating film103, the second insulating film104, the third insulating film105, the fourth insulating film106, and the fifth insulating film107.

In the present modification example, the gate layer110in each of the terminals311to313, that is, the pad portion, is covered with a cover layer that includes the lower electrode layer1401and the bias line layer1601. Even if the same material as that of the lower electrode14aor the bias line16is contained in the gate layer110, it is unlikely that the gate layer110would disappear due to wet etching carried out when the lower electrode14aor the bias line16is formed. Besides, as the gate layer110is provided in a layer lower than the source layer100, connection portions of the gate layer110, the lower electrode layer1401, the bias line16, and the transparent conductive film1701are provided in a lower layer as compared with Embodiment 1. This enables to make it unlikely that the connection portions would be influenced by scars and the like that occur in the imaging panel production process.

The S terminal and the B terminal in the present embodiment have a structure common to the S terminal32and the B terminal33(seeFIG. 5A) in Embodiment 1 described above, and the G terminal has a structure different from those of the S terminal and the B terminal.

FIG. 9is a cross-sectional view of the G terminal in the present embodiment. As shown inFIG. 9, the G terminal321in the present embodiment has a terminal structure similar to that in the above-described modification example of Embodiment 1. More specifically, in the G terminal321, the gate layer110is used in the pad portion. In this case, as the gate layer110and the gate line11are formed with the same material, the G terminal321does not need a contact for connection with the gate line11.

The embodiments of the present invention are thus described above, but the above-described embodiments are merely examples for implementing the present invention. The present invention, therefore, is not limited to the above-described embodiments, and the above-described embodiments can be appropriately varied and implemented without departing from the spirit and scope of the invention. The following description describes modification examples.

(1) The present modification example relates to a cover layer having a structure different from that in the modification example of Embodiment 1 described above (seeFIG. 7), and constituent members that are different from those in Modification Example of Embodiment 1 described above are principally described in the following description.

FIG. 10is a cross-sectional view showing an exemplary structure of a G terminal, an S terminal and a B terminal in the present modification example. The G terminal341, the S terminal342, and the B terminal343in the present modification example further include a source layer100cmade of the same material as that of the source electrode13c, the drain electrode13d, and the and source line10, so that the source layer110cserves as a cover layer of the gate layer110that is to become a pad portion, and further, is interposed between the gate layer110and the lower electrode layer1401. The source layer100cis formed on the gate insulating film102, and is connected with the gate layer110through the opening102aprovided in the gate insulating film102. The opening102ain the gate insulating film102is formed by photolithography and dry etching after the gate insulating film102is formed.

The first insulating film103is provided on the gate insulating film102and the source layer100c, on an outer side with respect to the opening102a, and has an opening103aat a position that overlaps with the opening102a. The lower electrode layer1401is provided on the first insulating film103so as to be connected with the source layer100cat the opening103a. On the first insulating film103and the lower electrode layer1401, the third insulating film105having an opening105aat a position that overlaps with the openings102aand103ais arranged. A contact hole CH32is formed with the openings102a,103a, and105a.

In the present modification example as well, the pad portion formed with the gate layer110is covered with the cover layer that includes the source layer100c, the lower electrode layer1401, and the bias line layer1601, and the pad portion is therefore prevented from disappearing due to the etching in the process of forming the active area.

Incidentally, the above-described gate layer100has such a structure that molybdenum nitride (MoN) and aluminum (Al) are laminated in the upper layer and the lower layer, respectively, but the structure may be such that tungsten (W) and tantalum nitride (TaN) are laminated in the upper layer and the lower layer, respectively. Further, the above-described source layer100chas such a structure that molybdenum nitride (MoN), aluminum (Al), and molybdenum nitride (MoN) are laminated in the upper layer, the intermediate layer, and the lower layer, respectively, but the structure may be such that copper (Cu) and titanium (Ti) are laminated in the upper layer and the lower layer, respectively. Still further, the above-described bias line layer1601has such a structure that molybdenum nitride (MoN), aluminum (Al), and molybdenum nitride (MoN) are laminated in the upper layer, the intermediate layer, and the lower layer, respectively, but the structure may be such that molybdenum niobium (MoNb), an alloy of aluminum (Al) and neodymium (Nd), and molybdenum niobium (MoNb) are laminated in the upper layer, the intermediate layer, and the lower layer, respectively. In this case, as the etching for the gate layer100, dry etching with use of a mixture of chlorine-based gas and fluorine-based gas is carried out; and as the etching for the source layer100c, wet etching with use of acid-mixed liquid, and dry etching with use of a chlorine-based gas is carried out. Further, as the etching for the lower electrode layer1401and the bias line layer1601, wet etching with use of acid-mixed liquid similar to that for the source layer is carried out.

(2) The present modification example is described with reference to an example in which the G terminal, the S terminal, and the B terminal are formed by a method different from that used in Modification Example of Embodiment 1 described above (seeFIG. 7). The following description principally describes configurations different from those in Modification Example of Embodiment 1 described above.

In Modification Example of Embodiment 1 described above, the gate layer110shown inFIG. 7has such a structure that molybdenum nitride (MoN) and aluminum (Al) are laminated; in the present modification example, titanium (Ti) is used in place of molybdenum nitride (MoN) in the upper layer. Further, in the step in which the gate insulating film102is formed after the gate layer110is formed, and thereafter the source electrode13cand the drain electrode13dare formed (seeFIG. 6C), wet etching is carried out with etching liquid in which acetic acid, nitric acid, and phosphoric acid are used. As the etch selectivity of titanium (Ti) with respect to molybdenum nitride (MoN) and aluminum (Al) used in the source electrode13cand the drain electrode13dis high, wet etching does not cause the gate layer110to disappear.

Incidentally, in a case where the same gate layer110as that in in Modification Example of Embodiment 1 described above is used, molybdenum nitride (MoN), aluminum (Al), and titanium (Ti) may be laminated in the upper layer, the intermediate layer, and the lower layer, respectively, and wet etching and dry etching may be carried out for forming the source electrode13cand the drain electrode13d, so that the gate layer110would not disappear. In this case, the film of titanium (Ti) provided in a lower layer preferably has a thickness of 80 nm or less.

In other words, when the source electrode13cand the drain electrode13dare formed, the films of molybdenum nitride (MoN) and aluminum (Al) provided in the upper layer and the intermediate layer, respectively, are wet-etched with etching liquid with use of, for example, acetic acid, nitric acid, and phosphoric acid. Thereafter, titanium (Ti) formed in the lower layer is dry-etched with use of, for example, chlorine-based gas. In dry etching, the etch selectivity of molybdenum nitride (MoN) in the upper layer of the gate layer110with respect to titanium (Ti) is high. Further, the film of titanium (Ti) in the lower layer, used in the source electrode13cand the drain electrode13d, is thin and the etching time for this film is short. Dry etching therefore does not cause the pad portion formed with the gate layer110to disappear.

(3) Modification Example of Embodiment 1 described above (seeFIG. 7) is described with reference to an exemplary configuration in which the lower electrode layer is included in the cover layer in each of the G terminal, the S terminal, and the B terminal. The present modification example is described with reference to an exemplary configuration in which a source layer made the same material as that of the source electrode13c, the drain electrode13d, and the source line10is provided in place of the lower electrode layer. The following description principally describes configurations different from those in Modification Example of Embodiment 1 described above.

FIG. 11is a cross-sectional view showing an exemplary structure of a G terminal, an S terminal and a B terminal in the present modification example. The G terminal351, the S terminal352, and the B terminal353in the present modification example have a configuration in which a source layer100dconnected with the gate layer110via the opening102aof the gate insulating film102is provided on the gate layer110that is to become a pad portion.

Each of the source electrode13c, the drain electrode13d, and the source line10has a laminate structure obtained by laminating molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and titanium (Ti) in the lower layer.

The source layer100dis formed with titanium (Ti) in the lower layer, as the wet etching carried out when the lower electrode14ais formed causes molybdenum nitride (MoN) in the upper layer and aluminum (Al) in the intermediate layer to disappear.

In other words, after the source layer100dformed with molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and titanium (Ti) in the lower layer is formed on the gate insulating film102, the first insulating film103having the opening103aat a position that overlaps with the opening102ais formed on the source layer100d. Thereafter, a metal film140(seeFIG. 6F) that is to become the lower electrode14is formed on the first insulating film103, and the metal film140in the terminal area is wet-etched with etching liquid with use of, for example acetic acid, nitric acid, and phosphoric acid. Here, molybdenum nitride (MoN) in the upper layer and aluminum (Al) in the intermediate layer in the source layer100ddisappear. On the other hand, titanium (Ti) in the lower layer remains, since the etch selectivity of titanium with respect to molybdenum nitride (MoN) and aluminum (Al) is high. The pad portion formed with the gate layer110therefore does not disappear, either.

Further, this wet etching causes an end portion of the first insulating film103on the opening103aside is side-etched, whereby the end portion of the first insulating film103on the opening103aside overhangs.

The third insulating film105has an opening105ainside the opening103aof the first insulating film103. In a case where the opening105aof the third insulating film105is formed on an outer side with respect to the opening103aof the first insulating film103, disconnection between the bias line layer1601and the transparent conductive film1701tends to occur at the overhanging part. The above-described configuration, therefore, makes it possible to prevent disconnection between the bias line layer1601and the transparent conductive film1701.

Incidentally, the third insulating film105preferably has a thickness greater than the sum of the thicknesses of the upper layer and the intermediate layer that disappear in the source layer100d. This configuration makes it possible to prevent disconnection between the bias line layer1601and the transparent conductive film1701. Further, the films of molybdenum nitride (MoN), aluminum (Al), and molybdenum nitride (MoN) that form the bias line layer1601preferably have a thickness greater than the sum of the thicknesses of the films of molybdenum nitride (MoN) and aluminum (Al) of the source layer100dbefore the etching. This configuration makes it possible to prevent disconnection between the bias line layer1601and the transparent conductive film1701more surely.

This example is described with an exemplary configuration in which titanium (Ti) is contained in the source electrode13c, the drain electrode13d, the source line10, and the source layer100d, but the configuration may be such that an alloy containing tantalum (Ta), tungsten (W), and titanium (Ti), an alloy containing tantalum (Ta), or an alloy containing tungsten (W) may be contained in place of titanium (Ti).

(4) In Modification Example (3) described above, the source electrode13c, the drain electrode13d, and the source line10have a laminate structure obtained by laminating molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and titanium (Ti) in the lower layer; on the other hand, the present modification example is described with reference to an exemplary configuration in which titanium (Ti) is laminated in the upper layer.

FIG. 12is a cross-sectional view showing an exemplary structure of the G terminal, the S terminal, and the B terminal in the present modification example. The G terminal361, the S terminal362, and the B terminal363in the present modification example have a configuration in which a source layer100econnected with the gate layer110via the opening102ain the gate insulating film102is provided on the gate layer110. The source layer100ehas a laminate structure obtained by laminating titanium (Ti) in the upper layer, aluminum (Al) in the intermediate layer, and titanium (Ti) in the lower layer.

In this case, after the source layer100eis formed, the first insulating film103having the opening103aat a position that overlaps with the opening102ais formed on the source layer100e. Thereafter, a metal film140(seeFIG. 6F) that is to become the lower electrode14ais formed on the first insulating film103, and the metal film140in the terminal area is wet-etched. The metal film140is formed with molybdenum nitride (MoN), and is etched with etching liquid with use of, for example acetic acid, nitric acid, and phosphoric acid. As the etch selectivity of titanium (i) in the upper layer of the source layer100ewith respect to molybdenum nitride is high in wet etching, the source layer100edoes not disappear, and the pad portion formed with the gate layer110does not disappear, either.

This example is described with an exemplary configuration in which titanium (Ti) is contained in the source electrode13c, the drain electrode13d, the source line10, and the source layer100e, but the configuration may be such that an alloy containing tantalum (Ta), tungsten (W), and titanium (Ti), an alloy containing tantalum (Ta), or an alloy containing tungsten (W) may be contained in place of titanium (Ti).

Further, the metal film140that is to become the lower electrode14amay have such a configuration that molybdenum nitride (MoN) is laminated in the upper layer and titanium (Ti) is laminated in the lower layer, while molybdenum nitride (MoN) is used in place of titanium (Ti) in the upper layer and the lower layer of the source layer100e. The lower layer of the metal film140preferably has a thickness of 80 nm or less.

In this case, molybdenum nitride (MoN) in the upper layer of the metal film140is wet-etched with an etching liquid with use of, for example, acetic acid, nitric acid, and phosphoric acid, and thereafter, dry etching with use of, for example, chlorine-based gas is carried out, whereby titanium (Ti) in the lower layer in the metal film140is removed. In dry etching, the etch selectivity of molybdenum nitride (MoN) in the upper layer of the source100ewith respect to titanium (Ti) is high. Further, the film of titanium (Ti) in the lower layer in the metal film140is thin, and etching of the same requires only short time. The etching of the metal film140, therefore, does not cause the source layer100eto disappear, thereby not causing the pad portion formed with the gate layer110to disappear.

(5) Modification Example of Embodiment 1 described above (seeFIG. 7) is described with reference to an exemplary configuration in which the bias line layer is included as a cover layer that covers the pad portion formed with the gate layer110, in the G terminal, the S terminal, and the B terminal. The present modification example is described with reference to an exemplary configuration in which the source layer made of the same material as that of the source electrode13c, the drain electrode13d, and the source line10is included in the cover layer, in place of the bias line layer. The following description principally describes configurations different from those in Modification Example of Embodiment 1 described above.

FIG. 13is a cross-sectional view showing an exemplary structure of the G terminal, the S terminal, and the B terminal in the present modification example. Each of the G terminal371, the S terminal372, and the B terminal373in the present modification example has a configuration in which a source layer100fconnected with the gate layer110via the opening102ain the gate insulating film102is provided on the gate layer110.

The materials used for forming the source electrode13c, the drain electrode13d, and the source line10are identical to those in Modification Example of Embodiment 1, and the source layer100fhas a laminate structure obtained by laminating molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and molybdenum nitride (MoN) in the lower layer.

The first insulating film103having the opening103aat a position that overlaps with the opening102ais provided on the source layer100f. On the first insulating film103, a lower electrode layer1401fconnected with the source layer100fat the opening103ais provided. The lower electrode layer1401fis formed with the same material as that for the lower electrode14a, and in the present modification example, the lower electrode layer1401fis made of titanium (Ti).

On the lower electrode layer1401f, the third insulating film105having an opening105ainside the opening103a. The openings102a,103a, and105aare formed so as to overlap with one another when viewed in a plan view. On the third insulating film105, the transparent conductive film1701connected with the source layer100fthrough the opening105ais arranged, and the fifth insulating film107is provided on an outer side with respect to the contact hole CH35on the transparent conductive film1701.

In this case, when the lower electrode14ais formed, in the step shown inFIG. 6F, the metal film140that is to become the lower electrode14ais dry-etched with chlorine-based gas, whereby the lower electrode14ais formed in the TFT area and the lower electrode layer1401fis formed in the terminal area.

Thereafter, through the steps shown inFIGS. 6K to 6M, the fifth insulating film107having the opening105ais formed on the lower electrode layer1401f. Then, the same step as that shown inFIG. 6Nis carried out so that the transparent conductive film160that is to become the bias line16is formed, and the transparent conductive film160is wet-etched with etching liquid with use of, for example, acetic acid, nitric acid, and phosphoric acid. Through these steps, the bias line16is formed in the TFT area, and the transparent conductive film160in the terminal area is removed. Here, as the etch selectivity of titanium (Ti) in the lower electrode layer1401fwith respect to molybdenum nitride (MoN) in the conductive film160is high in wet etching, the lower electrode layer1401fdoes not disappear. In other words, the etching carried out when the active area is formed does not cause the cover layer to disappear, and does not cause the pad portion formed with the gate layer110to disappear, either.

This example is described with reference to an exemplary configuration in which titanium (Ti) is contained in the lower electrode14aand the lower electrode layer1401f, but the configuration may be such that an alloy containing tantalum (Ta), tungsten (W), and titanium (Ti), an alloy containing tantalum (Ta), or an alloy containing tungsten (W) may be contained in place of titanium (Ti).

Further, in the above-described example, molybdenum nitride (MoN) may be used in place of titanium (Ti), to form the metal film140that is to become the lower electrode14aand the lower electrode layer1401f. Further, molybdenum nitride (MoN), aluminum (Al), and titanium (Ti) may be laminated in the upper layer, the intermediate layer, and the lower layer, respectively, for forming the transparent conductive film160that is to become the bias line16. The lower layer in the transparent conductive film160preferably has a thickness of 80 nm or less.

In this case, when the metal film140that is to become the lower electrode14ais wet-etched and the bias line16is formed, etching is carried out with etching liquid with use of, for example, acetic acid, nitric acid, and phosphoric acid. Through these steps, molybdenum nitride (MoN) and aluminum (Al) in the upper and intermedium layers, respectively, in the transparent conductive film160are removed. Thereafter, dry etching with use of chlorine-based gas is carried out, whereby titanium (Ti) in the lower layer is removed. The etch selectivity of molybdenum nitride (MoN) in the upper layer in the lower electrode layer1401fwith respect to titanium (Ti) is high in dry etching. Further, the film of titanium (Ti) in the lower layer in the transparent conductive film160is thin, and etching of the same requires only short time. The etching carried out for forming the bias line16, therefore, does not cause the lower electrode layer1401fto disappear. The etching carried out for forming the active area, therefore, does not cause the cover layer to disappear, and does not cause the pad portion formed with the gate layer110to disappear, either.

(6) The above-described embodiments and modification examples are described with reference to an exemplary configuration in which two or more layers are provided in the cover layer, but at least one layer may be provided in the cover layer. The following description will describe the exemplary configuration.

FIG. 14is a cross-sectional view showing an exemplary structure of a G terminal, an S terminal and a B terminal in the present modification example. In FIG.14, the same constituent members as those in Embodiment 1 are denoted by the same reference symbols as those in Embodiment 1. In the G terminal381, the S terminal382, and the B terminal383shown inFIG. 14, a bias line layer1601ais provided as a cover layer on the gate layer110that is the pad portion; and the gate layer110, the bias line layer1601a, and the transparent conductive film1701are connected in the contact hole CH33.

The gate layer110is formed with the same material as that of the gate electrode13a, with molybdenum nitride (MoN) and aluminum (Al) laminated in the upper layer and the lower layer, respectively.

The bias line layer1601a is formed with the same material as that of the bias line16, and in the present example, it has a structure obtained by laminating molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and molybdenum nitride (MoN) in the lower layer.

The terminal structure in the present modification example can be produced simultaneously in the step of producing the active area, as is the case with Embodiment 1 described above. In this case, as is the case with the step shown inFIG. 6A, the gate layer110is formed, and thereafter, the gate insulating film102and the semiconductor layer130are formed so as to cover the gate layer110. Then, as is the case with the step shown inFIG. 6B, the semiconductor layer130is patterned and the semiconductor layer130in the terminal area is removed. Thereafter, a metal film for forming the source electrode13cand the drain electrode13dis formed on the gate insulating film102, and the metal film provided in the terminal area is removed by wet etching carried out when the source electrode13cand the drain electrode13dare formed. Here, as the gate insulating film102is provided on the gate layer110, the wet etching does not cause the gate layer110to disappear.

Further, as is the case with the steps shown inFIGS. 6D and 6E, the first insulating film103is formed on the gate insulating film102, and the second insulating film104is formed on the first insulating film103, but the second insulating film104formed in the terminal area is removed by wet etching.

Next, as is the case with the step shown inFIG. 6F, the metal film140for forming the lower electrode14in the TFT area is formed in the terminal area as well, but the metal film140in the terminal area is removed by wet etching carried out for forming the lower electrode14. Here, as the gate layer110is covered with the gate insulating film102and the first insulating film103, this wet etching does not cause the gate layer110to disappear.

Thereafter, as is the case with the steps shown inFIGS. 6G to 6I, the photoelectric conversion layer15and the upper electrode14bare formed in the TFT area, but the etching carried out for forming these does not cause the gate layer110to disappear, as the gate layer110is covered with the gate insulating film102and the first insulating film103.

Further, thereafter, as is the case with the step shown inFIG. 6K, the third insulating film105is formed on the first insulating film103, and the third insulating film105is patterned by photolithography and wet etching. Through these steps, the contact hole CH33passing through the third insulating film105, the first insulating film103, and the gate insulating film102is formed in the terminal area, on the gate layer110.

As is the case with the steps shown inFIGS. 6L to 6N, the fourth insulating film106is formed in the TFT area, and the metal film160for forming the bias line16is formed in the TFT area and the terminal area. The metal film160is patterned by photolithography and wet etching, and the bias line16is formed on the fourth insulating film106in the TFT area. Here, the bias line layer1601aconnected with the gate layer110through the contact hole CH33is formed in the terminal area.

Thereafter, steps identical to those shown inFIGS. 6O to 6Sare carried out, whereby the transparent conductive film1701is formed on the bias line layer1601ain the terminal area, and the fifth insulating film107is formed on an outer side with respect to the contact hole CH33, on the transparent conductive film1701.

Incidentally, the above-described example is described with reference to an exemplary configuration in which the bias line layer1601ais provided as the cover layer, but the configuration may be such that a lower electrode layer or the source layer is provided in place of the bias line layer. In a case where the lower electrode layer is provided as the cover layer, the lower electrode layer may be formed with such a material that the etching carried out for forming the bias line16does not cause the lower electrode layer to disappear. For example, in a case where the bias line16has a structure obtained by laminating molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and molybdenum nitride (MoN) in the lower layer, the lower electrode14may be formed with a laminate of molybdenum nitride (MoN) in the upper layer and titanium (Ti) in the lower layer. Molybdenum nitride (MoN) provided in the upper layer of the lower electrode layer is removed by the wet etching carried out for forming the bias line16, but titanium (Ti) in the lower layer is not removed, because the etch selectivity of titanium (Ti) with respect to molybdenum nitride (MoN) is high in the wet etching, thereby resulting in that the pad portion does not disappear.

Further, in a case where the source layer is provided as a cover layer, the source layer may be formed with such a material that the etching carried out for forming the lower electrode14and the bias line16does not cause the source layer to disappear. For example, the following case is assumed: the bias line16has a structure obtained by laminating molybdenum nitride (MoN), aluminum (Al), and molybdenum nitride (MoN) in the upper layer, the intermediate layer, and the lower layer, respectively, and the lower electrode14is made of molybdenum nitride (MoN). In such as case, titanium (Ti), aluminum (Al), and titanium (Ti) may be laminated in the upper layer, the intermediate layer, and the lower layer, respectively, as materials for the source electrode13c. The etch selectivity of titanium (Ti) provided in the upper layer of the source layer with respect to molybdenum nitride (MoN) is high in wet etching carried out when the lower electrode14and the bias line16are formed, thereby resulting in that the pad portion does not disappear.

In the exemplary terminal structure shown inFIG. 14, only the bias line layer1601ais provided as the cover layer, but alternatively, the configuration may be such that only the lower electrode layer is provided.FIG. 15is a cross-sectional view showing an exemplary terminal structure in which only the lower electrode layer is provided in the cover layer. InFIG. 15, the same constituent members as those in Embodiment 1 are denoted by the same reference symbols as those inFIG. 14.

In the G terminal391, the S terminal392, and the B terminal393shown inFIG. 15, a lower electrode layer1401gis provided as a cover layer on the source layer100that is the pad portion; and the gate layer110, the lower electrode layer1401g, and the transparent conductive film1701are connected in the contact hole CH34.

In this example, the lower electrode14has a laminate structure obtained by laminating molybdenum nitride (MoN) and titanium (Ti) in the upper layer and the lower layer, respectively. The lower electrode layer1401gis formed in the step of forming the lower electrode14, with the same material as that of the lower electrode14, but the lower electrode layer1401gis finally formed with titanium (Ti) alone, as a result of the etching carried out when the lower electrode14is formed. The following description describes a method for producing this terminal structure.

In this case, steps identical to those shown inFIGS. 6A to 6Fare carried out, whereby the lower electrode layer1401gconnected with the source layer100through the opening103ain the first insulating film103is formed in the terminal area. The lower electrode layer1401gformed here has a structure obtained by laminating molybdenum nitride (MoN) and titanium (Ti) in the upper layer and the lower layer, respectively, as is the case with the lower electrode14.

Thereafter, steps identical to those shown inFIGS. 6G to 6Nare carried out, whereby the metal film160for forming the bias line16is formed in the TFT area and the terminal area; then, wet etching is carried out with respect to the metal film160in the step shown inFIG. 6O, which causes the bias line16to be formed in the TFT area, and causes the metal film160in the terminal area to be removed. The metal film160has a structure obtained by laminating molybdenum nitride (MoN) in the upper layer, aluminum (Al) in the intermediate layer, and molybdenum nitride (MoN) in the lower layer.

Here, the top of the source layer100, which is the pad portion, is covered with the lower electrode layer1401g, and the wet etching with respect to the metal film160causes the metal film160in the terminal area to be removed, while causing molybdenum nitride (MoN) provided in the upper layer of the lower electrode layer1601gto be removed. Titanium (Ti) provided in the lower layer of the lower electrode layer1601gremains, because the etch selectivity of the same with respect to molybdenum nitride (MoN) is high in wet etching. The source layer100, which is the pad portion, is therefore covered with the lower electrode layer1401gformed with titanium (Ti), thereby not disappearing in the etching step for forming the bias line16. Thereafter, steps identical to those shown inFIG. 6Q to 6Uare carried out, whereby the G terminal391, the S terminal392, and the B terminal393are formed.

Incidentally, molybdenum nitride (MoN) in the lower layer of the metal film160described above may be replaced with titanium (Ti). In this case, the metal film160is wet-etched, whereby molybdenum nitride (MoN) in the upper layer and aluminum (Al) in the intermediate layer are etched, and thereafter, dry etching with chlorine-based gas is carried out, whereby titanium (Ti) in the lower layer of the metal film160is etched. Here, the source layer100, which is the pad portion, is covered with the lower electrode layer1401g. The etch selectivity of molybdenum nitride (MoN) provided in the upper layer of the lower electrode layer1401gwith respect to titanium (Ti) in the lower layer of the metal film160is high in dry etching. Further, the film of titanium (Ti) in the lower layer of the metal film160is thin, and etching of the same requires only short time. Consequently, the lower electrode layer1401gdoes not disappear.

The above-described example shown inFIG. 15is described with reference to an exemplary configuration in which the lower electrode layer1401gis provided as a cover layer, but the configuration may be such that a bias line layer is provided in place of the lower electrode layer, or such that the lower electrode layer1401gand the bias line layer are provided. In the case where the bias line layer is formed in place of the lower electrode layer, though the illustration is omitted, the source layer100, which is to become the pad portion, is covered with the first insulating film103before the lower electrode14is formed. The etching carried out when the lower electrode14is formed therefore does not cause the pad portion to disappear.

(7) The above-described embodiments and modification examples are described with reference to an exemplary configuration in which the gate layer or the source layer is used for forming the pad portion, but the members for the pad portion are not limited to these. For example, a lower electrode layer formed with the same material as that for the lower electrode may be used for the pad portion.FIG. 16is a cross-sectional view showing the G terminal, the S terminal, and the B terminal in a case where a lower electrode layer is used for forming the pad portion. As shown inFIG. 16, in each of the G terminal3101, the S terminal3102, and the B terminal3103according to the present modification example, the lower electrode layer1401is provided on the first insulating film103, and the third insulating film105having the opening105ais provided on the lower electrode layer1401. On the third insulating film105, the conductive film1701connected with the lower electrode layer1401through the opening105ais provided. As the lower electrode layer1401is covered with the bias line layer1601, the etching carried out when the bias line16is formed does not cause the lower electrode layer1401to disappear.

(8) The above-described modification examples are described with reference to an exemplary configuration in which aluminum (Al) is contained in the material for the gate electrode, the source electrode, and the bias line in order to reduce the resistance, but the material used for reducing the resistance is not limited to aluminum (Al). For example, in place of aluminum (Al), the following material may be contained: copper (Cu); an alloy containing silver (Ag) and aluminum (Al); or an alloy containing copper (Cu) or silver (Ag).