Fan-out semiconductor package

A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2017-0161754 filed on Nov. 29, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a fan-out semiconductor package.

2. Description of Related Art

Semiconductor packages are consistently being thinned and lightened through variations in their shapes, and are increasingly being relied upon to provide complex functionalities including system in package (SiP) functionalities.

One type of package technology suggested to satisfy the technical demands described above is a fan-out semiconductor package. Such a fan-out semiconductor package has a compact size and may allow a plurality of pins to be implemented by redistributing connection terminals outwardly of a region in which a semiconductor chip is disposed.

Meanwhile, in the case of such a fan-out semiconductor package, materials forming the semiconductor chip, the redistribution layer, and the like are different from each other. As a result, a defect such as warpage due to a difference in a coefficient of thermal expansion (CTE) may occur.

SUMMARY

An aspect of the present disclosure may provide a fan-out semiconductor package that exhibits reduced warpage by having a slot.

According to an aspect of the present disclosure, a slot filled with a different material may be formed in at least one of a core member or a passivation layer of the fan-out semiconductor package.

According to an aspect of the present disclosure, a fan-out semiconductor package may include a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip, and a connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced apart from the through-hole and penetrating through at least a portion of the core member or the passivation layer.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or stylized for clarity.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below across various signal lines1090.

The electronic device1000may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device1000is not limited thereto, and may be any other electronic device processing data.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the mainboard1010, such as a camera1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, and may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in itself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not generally used by itself, but is instead packaged and used in an electronic device, or the like, in a packaged state.

A reason why semiconductor packaging generally is used is that there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard may advantageously be provided by the packaging.

A semiconductor package manufactured by packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor packages and the fan-out semiconductor packages will be described hereinafter in more detail with reference to the drawings.

Fan-in Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating a fan-in semiconductor package before and after being packaged.

FIG. 4is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222are significantly small, it is difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection member2240may be formed (depending on a size of the semiconductor chip2220) on the semiconductor chip2220in order to redistribute the connection pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photo imageable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside a footprint or area of the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the footprint or area of the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not always be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a fan-in semiconductor package mounted on an interposer substrate and ultimately mounted on a mainboard of an electronic device.

FIG. 6is a schematic cross-sectional view illustrating a fan-in semiconductor package embedded in an interposer substrate and ultimately mounted on a mainboard of an electronic device.

Referring to the drawings, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device while being mounted on the interposer substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an outer side of the semiconductor chip2220may be covered with a molding material2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in which the fan-in semiconductor package2200is embedded, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an outer side or periphery of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, the connection member2140may extend under both the semiconductor chip2120and the encapsulant2130. A passivation layer2150may further be formed on the connection member2144, and an underbump metal layer2160may further be formed in openings of the passivation layer2150. Solder balls2170may further be formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on or in the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the footprint or area of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the footprint of the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in the case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a fan-out semiconductor package mounted on a mainboard of an electronic device

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is conceptually different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

FIG. 9is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package.

FIGS. 10A and 10Bare schematic plan views taken along lines I-I′ and II-II′ of the fan-out semiconductor package ofFIG. 9.

Referring toFIGS. 9, 10A, and 10B, a fan-out semiconductor package100A according to an exemplary embodiment may include a core member110having a through-hole110H, a semiconductor chip120disposed in the through-hole110H of the core member110and having an active surface having connection pads122disposed thereon and an inactive surface opposing the active surface, an encapsulant130encapsulating at least portions of the core member110and the semiconductor chip120, a connection member140disposed on the core member110and the active surface of the semiconductor chip120, a passivation layer150disposed on the connection member140, an underbump metal layer160disposed in openings151of the passivation layer150, and electrical connection structures170disposed on the passivation layer150and connected to the underbump metal layer160.

The fan-out semiconductor package100A may have a first slot SL1disposed in the core member110at the outside of the through-hole110H and a second slot SL2formed in the passivation layer150. The first and second slots SL1and SL2may be filled with a material different from that of the core member110or the passivation layer150around the first and second slots SL1and SL2. In the fan-out semiconductor package100A, coefficients of thermal expansion of the core member110, the semiconductor chip120, the encapsulant130, and the connection member140can be different from each other, such that the coefficients of thermal expansion of an upper portion and a lower portion of the core member110may be asymmetric with each other, and a defect such as warpage may thus occur. However, an occurrence of stress due to a difference in the coefficients of thermal expansion may be alleviated by forming the first slot SL1in the core member110and the second slot SL2in the passivation layer150, thereby reducing an occurrence of warpage.

The first slot SL1may be disposed in the core member110and filled with a material different from that of the core member110. The first slot SL1may be filled with the encapsulant130as illustrated, but is not limited thereto. The first slot SL1may penetrate through at least a portion of the core member110, and may penetrate through the entire thickness of the core member110as illustrated. In this case, a lower surface of the first slot SL1may be in contact with the connection member140. The first slot SL1may have various shapes such as one or more rectangular shape(s), curved quadrangular shape(s), cross shape(s), line shape(s), and the like on a plane as illustrated inFIG. 10A. A shape and a layout of the first slot SL1are not limited to those illustrated in the drawings, and may be variously changed according to exemplary embodiments. In particular, the first slot SL1may be disposed in a region in which stress (e.g., caused by thermal expansion) is relatively heavily concentrated in the fan-out semiconductor package100A.

The second slot SL2may be formed in the passivation layer150and have a form which is externally (and downwardly) opened. That is, an inner portion of the second slot SL2may be filled with air. The second slot SL2may penetrate through at least a portion of the passivation layer150, and may penetrate through the entire thickness of the passivation layer150as illustrated. In this case, a third (or other lowermost) insulating layer141cof the connection member140may be exposed through an end portion of the second slot SL2. According to exemplary embodiments, the second slot SL2may also be partially extended into the insulating layers141a,141b, and/or141cof the connection member140. The second slot SL2may have various shapes such as one or more rectangular shape (s), curved quadrangular shape(s), cross shape(s), line shape(s), and the like on a plane as illustrated inFIG. 10B. A shape and a layout of the second slot SL2are not limited to those illustrated in the drawings, and may be variously changed according to exemplary embodiments. In particular, the second slot SL2may be disposed in a region in which stress is relatively heavily concentrated in the fan-out semiconductor package100A.

The respective components included in the fan-out semiconductor package100A according to the exemplary embodiment will be described hereinafter in more detail.

The core member110may further improve rigidity of the fan-out semiconductor package100A depending on certain materials, and serve to secure uniformity of a thickness of an encapsulant130. When through-wirings, or the like, are formed in the core member110, the fan-out semiconductor package100A may be utilized as a package-on-package (POP) type package. The core member110may have the through-hole110H. The semiconductor chip120may be disposed in the through-hole110H to be spaced apart from the core member110by a predetermined distance. Side surfaces of the semiconductor chip120may be surrounded by the core member110. However, such a form is only an example and may be variously modified to have other forms, and the core member110may perform another function depending on such a form.

The core member110may include an insulating layer111. An insulating material may be used as the material of the insulating layer111. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass fiber, a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Such a core member110may serve as a support member.

The first slot SL1may be disposed in the core member110. As illustrated inFIG. 10A, the first slot SL1may be disposed around a body121of the semiconductor chip120. The first slot SL1may include slots SL1adisposed at corners of the fan-out semiconductor package100A, rectangular slots SL1bdisposed in one column at both sides of the semiconductor chip120, slots SL1cdisposed in an elongated line shape at both sides of the semiconductor chip120different from both sides of the semiconductor chip120at which the rectangular slots SL1bare disposed, and cross-shaped slots SL1ddisposed between the semiconductor chip120and the slots SL1c. However, such a layout of the first slot SL1is an example and may be disposed in consideration of materials, tendency of warpage, and the like of the components in the fan-out semiconductor package100A. For example, the first slot SL1may be disposed at high density in a region in which a volume of the core member110is relatively large. The first slot SL1may be disposed to penetrate through the entirety (e.g., entire thickness) of the core member110or may be disposed to penetrate through at least a portion of the core member110(e.g., at least a portion of a thickness of the core member). For example, according to exemplary embodiments, the first slot SL1may be disposed to be recessed from an upper surface of the core member110by only a predetermined depth. In particular, in the case in which the first slot SL1penetrates through the entirety of the core member110, the first slot SL1may be formed in the same process as a process of forming the through-hole110H. As a result, the first slot SL1may have the same depth as that of the through-hole110H.

The semiconductor chip120may be an integrated circuit (IC) providing several hundreds to several millions of elements or more integrated in a single chip. In this case, the IC may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. That is, the IC may be a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a memory chip such as a volatile memory (for example, a DRAM), a non-volatile memory (for example, a ROM), a flash memory, or the like. In addition, the above-mentioned elements may also be combined with each other and be disposed in the semiconductor chip120.

The semiconductor chip120may be formed on the basis of an active wafer. In this case, a base material of a body121may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on or in the body121. The connection pads122may electrically connect the semiconductor chip120to other components. A material of each of the connection pads122may be a conductive material such as aluminum (Al), or the like. A passivation layer123exposing the connection pads122may be formed on the body121, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. A lower surface of the connection pad122may have a step with respect to a lower surface of the encapsulant130through the passivation layer123. Resultantly, a phenomenon in which the encapsulant130bleeds into the lower surface of the connection pads122may be prevented to some extent. An insulating layer (not illustrated), and the like, may also be further disposed in other appropriate positions. The semiconductor chip120may be a bare die, a redistribution layer (not illustrated) may further be formed on the active surface of the semiconductor chip120, if desired, and bumps (not illustrated), or the like, may be connected to the connection pads122.

The encapsulant130may protect the core member110, the semiconductor chip120, and the like. An encapsulation form of the encapsulant130is not particularly limited, and may be a form in which the encapsulant130surrounds at least portions of the core member110, the semiconductor chip120, and the like. For example, the encapsulant130may cover the core member110and the inactive surface of the semiconductor chip120, and fill spaces between walls of the through-hole110H and the side surfaces of the semiconductor chip120, and the first slot SL1. In addition, the encapsulant130may also fill at least a portion of a space between the passivation layer123of the semiconductor chip120and the connection member140. The encapsulant130may fill the through-hole110H to thus serve as an adhesive and reduce buckling of the semiconductor chip120, depending on certain materials. In addition, the encapsulant130optionally fills the first slot SL1, such that stress in the fan-out semiconductor package100A may be alleviated and adhesion with the core member110may be increased.

A material of the encapsulant130is not particularly limited. For example, an insulating material may be used as the material of the encapsulant130. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler, or impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Alternatively, a PID resin may also be used as the insulating material.

The connection member140may redistribute the connection pads122of the semiconductor chip120. Several tens to several hundreds of connection pads122of the semiconductor chip120having various functions may be redistributed by the connection member140, and may be physically or electrically externally connected through the electrical connection structures170depending on the functions. The connection member140may include a first insulating layer141adisposed on the core member110and the active surface of the semiconductor chip120, a first redistribution layer142adisposed on the first insulating layer141a, a first via143aconnecting the first redistribution layer142aand the connection pads122of the semiconductor chip120to each other, a second insulating layer141bdisposed on the first insulating layer141a, a second redistribution layer142bdisposed on the second insulating layer141b, a second via143bpenetrating through the second insulating layer141band connecting the first and second redistribution layers142aand142bto each other, a third insulating layer141cdisposed on the second insulating layer141b, a third redistribution layer142cdisposed on the third insulating layer141c, and a third via143cpenetrating through the third insulating layer141cand connecting the second and third redistribution layers142band142cto each other. The first to third redistribution layers142a,142b, and142cmay be electrically connected to each other and to connection pads122.

An insulating material may be used as a material of each of the insulating layers141a,141b, and141c. In this case, a photosensitive insulating material such as a photo imageable dielectric (PID) resin may also be used as the insulating material. That is, the insulating layers141a,141b, and141cmay be photosensitive insulating layers. When the insulating layers141a,141b, and141chave photosensitive properties, the insulating layers141a,141b, and141cmay be formed to have a smaller thickness, and fine pitches of the via layers143a,143b, and143cmay be achieved more easily. The insulating layers141a,141b, and141cmay be photosensitive insulating layers including an insulating resin and an inorganic filler. When the insulating layers141a,141b, and141care multiple layers, the materials of the insulating layers141a,141b, and141cmay be the same as each other, and may alternatively be different from each other, if appropriate. When the insulating layers141a,141b, and141care multiple layers, the insulating layers141a,141b, and141cmay be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent. In some cases, a larger number of insulating layers than those illustrated in the drawing may be formed.

The redistribution layers142a,142b, and142cmay serve to substantially redistribute the connection pads122. A material of each of the redistribution layers142a,142b, and142cmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers142a,142b, and142cmay perform various functions depending on designs of their corresponding layers. For example, the wiring layers112a,112b, and112cmay include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers142a,142b, and142cmay include via pad patterns, electrical connection structure pad patterns, and the like.

The vias143a,143b, and143cmay electrically connect the redistribution layers142a,142b, and142c, and the connection pads122, or the like, formed on different layers to each other, resulting in an electrical path in the fan-out semiconductor package100A. A material of each of the vias143a,143b, and143cmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias143a,143b, and143cmay be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias143a,143b, and143cmay have any of a variety of shapes such as a tapered shape, a cylindrical shape, and the like.

The passivation layer150may protect the connection member140from external physical or chemical impacts. The passivation layer150may have openings151exposing at least portions of the third (or lowermost) redistribution layer142cof the connection member140. The number of openings151formed in the passivation layer150may be several tens to several thousands. The passivation layer150may have a second slot SL2exposing at least portions of the third insulating layer141cof the connection member140. A material of the passivation layer150is not particularly limited. For example, an insulating material may be used as the material of the passivation layer150. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler, or impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Alternatively, a solder resist may also be used.

The second slot SL2may have a form which is externally opened. The second slot SL2may be disposed around the electrical connection structures170and between the electrical connection structures170as illustrated inFIG. 10B. The second slot SL2may be spaced apart from the electrical connection structures170so as not to contact the electrical connection structures170. The second slot SL2may include curved rectangular slots SL2adisposed at corners of the fan-out semiconductor package100A, rectangular slots SL2bdisposed in one column at both sides of the passivation layer150, slots SL2cdisposed in an elongated line shape at both sides of the passivation layer150different from sides of the passivation layer150at which the rectangular slots SL2bare disposed, and cross-shaped slots SL2ddisposed between the electrical connection structures170. However, such a layout of the second slot SL2is an example and may be disposed in consideration of materials, tendency of warpage, and the like of the components in the fan-out semiconductor package100A. For example, the second slot SL2may be disposed at high density in a region in which a volume of the passivation layer150is relatively large. In addition, the second slot(s) SL2need not be disposed in the same form as the first slot SL1, and may be disposed at (or centered at) the same position in a vertical direction or may be disposed to be shifted by a predetermined interval relative to the first slot(s) SL1. The second slot SL2may be disposed to penetrate through the entirety of the passivation layer150or may be disposed to penetrate through at least a portion of the thickness of the passivation layer150. For example, according to exemplary embodiments, the second slot SL2may be disposed to be recessed from a lower surface of the passivation layer150by only a predetermined depth. Alternatively, the second slot SL2may have a relative deep depth and may also be extended to at least portions of the insulating layers141a,141b, and141cof the connection member140including the third (or lowermost) insulating layer141c.

The underbump metal layer160may improve connection reliability of the electrical connection structures170to improve board level reliability of the fan-out semiconductor package100A. The underbump metal layer160may be connected to the third redistribution layer142cof the connection member140exposed through the openings151of the first passivation layer150. The underbump metal layer160may be formed in the openings151of the passivation layer150by a metallization method using a conductive metal such as a metal, but is not limited thereto.

The electrical connection structures170may physically or electrically externally connect the fan-out semiconductor package100A. For example, the fan-out semiconductor package100A may be mounted on the mainboard of the electronic device through the electrical connection structures170. Each of the electrical connection structures170may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection structures170is not limited thereto. Each of the electrical connection structures170may be a land, a ball, a pin, or the like. The electrical connection structures170may be formed as a multilayer or single layer structure. When the electrical connection structures170are formed as a multilayer structure, the electrical connection structures170may include a copper (Cu) pillar and a solder. When the electrical connection structures170are formed as a single layer structure, the electrical connection structures170may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structures170are not limited thereto.

The number, an interval, a disposition form, and the like, of electrical connection structures170are not particularly limited, and may be sufficiently modified depending on design particulars. For example, the electrical connection structures170may be provided in an amount of several tens to several thousand according to the number of connection pads122, or may be provided in an amount of several tens to several thousand or more or several tens to several thousand or less. When the electrical connection structures170are solder balls, the electrical connection structures170may cover side surfaces of the underbump metal layer160extending onto one surface of the passivation layer150, and connection reliability may be more excellent.

At least one of the electrical connection structures170may be disposed in a fan-out region. The fan-out region is a region outside of a footprint region in which the semiconductor chip120is disposed. The fan-out package may have greater reliability than that of a fan-in package, may implement a plurality of I/O terminals, and may easily perform 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness.

Meanwhile, although not illustrated in the drawings, a metal thin film may be formed on the walls of the through-hole110H in order to dissipate heat or block electromagnetic waves. In addition, a plurality of semiconductor chips120performing functions that are the same as or different from each other may be disposed in the through-hole110H or in another through-hole formed in the core member110. In addition, a separate passive component such as an inductor, a capacitor, or the like, may be disposed in the through-hole110H or in another through-hole formed in the core member110. In addition, a passive component, for example, a surface mounted technology (SMT) component including an inductor, a capacitor, or the like, may be disposed on a surface of the passivation layer150.

FIGS. 11 and 12are schematic cross-sectional views illustrating another example of a fan-out semiconductor package.

Referring toFIG. 11, a fan-out semiconductor package100B according to another exemplary embodiment may include only a slot SL disposed in the core member110at the outside of the through-hole110H (and no slot disposed in the passivation layer150). The slot SL may be filled with a material different from that of the core member110. For example, the slot SL may be filled with the encapsulant130, or may be filled with a material different from that of the encapsulant130, for example, a metal material. Referring toFIG. 12, a fan-out semiconductor package100C according to another exemplary embodiment may include only a slot SL formed in the passivation layer150(and no slot disposed in the core member110). The slot SL may be filled with a material different from that of the passivation layer150. For example, the slot SL may be filled with air, or may be filled with an insulating material different from that of the passivation layer150.

The first and second slots SL1and SL2ofFIG. 9are not necessarily disposed together as in the fan-out semiconductor packages100B and100C described with reference toFIGS. 11 and 12, and at least one of the first or second slot SL1and SL2may be disposed. In addition, a material filling the first and second slots SL1and SL2may also be variously changed according to the exemplary embodiments such that different materials may fill the first and second slots SL1and SL2.

FIG. 13is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring toFIG. 13, in a fan-out semiconductor package100D according to another exemplary embodiment, a core member110may include a first insulating layer111ain contact with a connection member140, a first wiring layer112ain contact with the connection member140and embedded in the first insulating layer111a, a second wiring layer112bdisposed on the other surface of the first insulating layer111aopposing one surface of the first insulating layer111ain which the first wiring layer112ais embedded, a second insulating layer111bdisposed on the first insulating layer111aand covering the second wiring layer112b, and a third wiring layer112cdisposed on the second insulating layer111b. The first to third wiring layers112a,112b, and112cmay be electrically connected to connection pads122and/or the underbump metal layer160. The first and second wiring layers112aand112band the second and third wiring layers112band112cmay be electrically connected to each other through first and second vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively.

When the first wiring layer112ais embedded in the first insulating layer111a, a step generated due to a thickness of the first wiring layer112amay be significantly reduced, and an insulating distance of the connection member140may thus become constant. That is, a difference between a distance from a first redistribution layer142aof the connection member140to a lower surface of the first insulating layer111aand a distance from the first redistribution layer142aof the connection member140to the connection pad122of a semiconductor chip120may be smaller than a thickness of the first wiring layer112a. Therefore, a high density wiring design of the connection member140may be easy.

The lower surface of the first wiring layer112aof the core member110may be disposed on a level above a lower surface of the connection pad122of a semiconductor chip120. In addition, a distance between a redistribution layer142aof the connection member140and the first redistribution layer112aof the core member110may be greater than that between the first redistribution layer142aof the connection member140and the connection pad122of the semiconductor chip120. The reason is that the first wiring layer112amay be recessed into the first insulating layer111a. As described above, when the first wiring layer112ais recessed into the first insulating layer111a, such that the lower surface of the first insulating layer111aand the lower surface of the first wiring layer112ahave a step therebetween, a phenomenon in which a material of the encapsulant130bleeds to pollute the first wiring layer112amay be prevented. The second redistribution layer112bof the core member110may be disposed between an active surface and an inactive surface of the semiconductor chip120. The core member110may be formed at a thickness corresponding to that of the semiconductor chip120. Therefore, the second wiring layer112bformed in the core member110may be disposed on a level between the active surface and the inactive surface of the semiconductor chip120.

Thicknesses of the wiring layers112a,112b, and112cof the core member110may be greater than those of the redistribution layers142a,142b, and142cof the connection member140. Since the core member110may have a thickness equal to or greater than that of the semiconductor chip120, the wiring layers112a,112b, and112cmay be formed at large sizes depending on a scale of the core member110. On the other hand, the redistribution layers142a,142b, and142cof the connection member140may be formed at sizes relatively smaller than those of the wiring layers112a,112b, and112cfor thinness.

A material of each of the insulating layers111aand111bis not particularly limited. For example, an insulating material may be used as the material of the insulating layers111aand111b. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler, or impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Alternatively, a PID resin may also be used as the insulating material.

The wiring layers112a,112b, and112cmay serve to redistribute the connection pads122of the semiconductor chip120. A material of each of the wiring layers112a,112b, and112cmay be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers112a,112b, and112cmay perform various functions depending on designs of their corresponding layers. For example, the wiring layers112a,112b, and112cmay include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the wiring layers112a,112b, and112cmay include via pads, wire pads, connection terminal pads, and the like.

The vias113aand113bmay electrically connect the wiring layers112a,112b, and112cformed on different layers to each other, resulting in an electrical path in the core member110. A material of each of the vias113aand113bmay be a conductive material. Each of the vias113aand113bmay be completely filled with a conductive material, or a conductive material may also be formed along a wall of each of the via holes. In addition, each of the vias113aand113bmay have any of a variety of shapes such as a tapered shape, a cylindrical shape, and the like. When holes for the first vias113aare formed, some of the pads of the first wiring layer112amay serve as a stopper, and it may thus be advantageous in a process that each of the first vias113ahas the tapered shape having a width of an upper surface that is greater than that of a lower surface. In this case, the first vias113amay be integrated with pad patterns of the second wiring layer112b. In addition, when holes for the second vias113bare formed, some of the pads of the second wiring layer112bmay serve as a stopper, and it may thus be advantageous in a process that each of the second vias113bhas the tapered shape having a width of an upper surface that is greater than that of a lower surface. In this case, the second vias113bmay be integrated with pad patterns of the third wiring layer112c.

The fan-out semiconductor package100D may have a first slot SL1penetrating through at least portions of the first and second insulating layers111aand111bof the core member110at the outside or spaced apart from a periphery of the through-hole110H, and a second slot SL2formed in the passivation layer150. Each of the first and second slots SL1and SL2may be filled with a material different from a material of each of the first and second insulating layers111aand111band the passivation layer150around the first and second slots SL1and SL2. The first slot SL1may be particularly formed in a region in which the wiring layers112a,112b, and112care not disposed, but are not limited thereto. According to exemplary embodiments, a depth of the first slot SL1may be variously changed. For example, the first slot SL1may be disposed to penetrate through only the second insulating layer111bso as to be extended from an upper surface of the second insulating layer111bto a first level LB1.

A full description about other components of the fan-out semiconductor package100D is not provided here, and reference can instead be made to the description of the first and second slots SL1and SL2described with reference toFIGS. 9, 10A, and 10Babove for more detailed information about the fan-out semiconductor package100D and its component parts.

FIG. 14is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.

Referring toFIG. 14, in a fan-out semiconductor package100E according to another exemplary embodiment, a core member110may include a first insulating layer111a, a first wiring layer112aand a second wiring layer112bdisposed on opposite surfaces of the first insulating layer111a, respectively, a second insulating layer111bdisposed on the first insulating layer111aand covering the first wiring layer112a, a third wiring layer112cdisposed on the second insulating layer111b, a third insulating layer111cdisposed on the first insulating layer111aand covering the second wiring layer112b, and a fourth wiring layer112ddisposed on the third insulating layer111c. The first to fourth wiring layers112a,112b,112c, and112dmay be electrically connected to connection pads122. Since the core member110may include a large number of wiring layers112a,112b,112c, and112d, a connection member140may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the connection member140may be suppressed. Meanwhile, the first to fourth wiring layers112a,112b,112c, and112dmay be electrically connected to each other through first to third vias113a,113b, and113ceach penetrating through the first to third insulating layers111a,111b, and111c.

The first insulating layer111amay have a thickness greater than those of the second insulating layer111band the third insulating layer111c. The first insulating layer111amay be basically relatively thick in order to maintain rigidity, and the second insulating layer111band the third insulating layer111cmay be introduced in order to form a larger number of wiring layers112cand112d. Similarly, the first vias113apenetrating through the first insulating layer111amay have a diameter greater than those of second vias113band third vias113ceach penetrating through the second insulating layer111band the third insulating layer111c. The first insulating layer111amay include an insulating material different from those of the second insulating layer111band the third insulating layer111c. For example, the first insulating layer111amay be, for example, prepreg including a core material, a filler, and an insulating resin, and the second insulating layer111band the third insulating layer111cmay be an ABF or a PID film including a filler and an insulating resin. However, the materials of the first insulating layer111aand the second and third insulating layers111band111care not limited thereto.

A lower surface of the third wiring layer112cof the core member110may be disposed on a level below a lower surface of the connection pad122of a semiconductor chip120. In addition, a distance between a first redistribution layer142aof the connection member140and the third wiring layer112cof the core member110may be smaller than that between the first redistribution layer142aof the connection member140and the connection pad122of the semiconductor chip120. The reason is that the third wiring layer112cmay be disposed on the second insulating layer111bin protruding form, resulting in being in contact with the connection member140. The first wiring layer112aand the second wiring layer112bof the core member110may be disposed between an active surface and an inactive surface of the semiconductor chip120. The core member110may be formed at a thickness corresponding to that of the semiconductor chip120. Therefore, the first wiring layer112aand the second wiring layer112bformed in the core member110may be disposed on a level between the active surface and the inactive surface of the semiconductor chip120.

Thicknesses of the wiring layers112a,112b,112c, and112dof the core member110may be greater than those of the redistribution layers142a,142b, and142cof the connection member140. Since the core member110may have a thickness equal to or greater than that of the semiconductor chip120, the wiring layers112a,112b,112c, and112dmay also be formed at larger sizes. On the other hand, the redistribution layers142a,142b, and142cof the connection member140may be formed at relatively small sizes for thinness.

The fan-out semiconductor package100E may have a first slot SL1penetrating through at least portions of the first to third insulating layers111a,111b, and111cof the core member110at the outside or spaced apart from a periphery of the through-hole110H, and a second slot SL2formed in the passivation layer150. Each of the first and second slots SL1and SL2may be filled with a material different from a material of each of the first to third insulating layers111a,111b, and111cor the passivation layer150around the first and second slots SL1and SL2. In a case in which the first slot SL1is filled with the encapsulant130, a region between the first slot SL1and the third wiring layer112cbelow the first slot SL1may also be filled with the encapsulant130. The first slot SL1may be particularly formed in a region in which the wiring layers112a,112b,112c, and112dare not disposed, but are not limited thereto. According to exemplary embodiments, a depth of the first slot SL1may be variously changed. For example, the first slot SL1may be disposed to penetrate through only the third insulating layer111cso as to extend from an upper surface of the third insulating layer111cto a first level LB1, or may penetrate through only the first and third insulating layers111aand111cso as to be extended from the upper surface of the third insulating layer111cto a second level LB2.

A full description about other components of the fan-out semiconductor package100E is not provided here, and reference can instead be made to the description of the first and second slots SL1and SL2described with reference toFIGS. 9, 10A, and 10Babove for more detailed about the fan-out semiconductor package100E and its component parts.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward amounting surface of the fan-out semiconductor package in relation to cross sections shown in the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to a direction opposite to the lower direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection provided by direct contact between two components. In addition, “electrically connected” refers to concepts including a physical connection and a physical disconnection that nonetheless provides electrically connectivity. It can be understood that when an element is referred to with “first” and “second”, the element is not limited thereby. The terms “first” and “second” may be used only for a purpose of distinguishing one element from another element, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

As set forth above, according to the exemplary embodiments, the fan-out semiconductor package of which the warpage is reduced may be provided by forming the slot filled with the different material in at least one of the core member or the passivation layer.