Semiconductor package and manufacturing method of semiconductor package

A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

BACKGROUND

Stacked dies are commonly used in Three-Dimensional (3D) integrated circuits. Through the stacking of dies, the footprint (form factor) of semiconductor packages is reduced. In addition, the metal line routing in the dies is significantly simplified through the formation of stacked dies.

In some conventional applications, a plurality of dies is stacked to form a die stack. The total count of the stacked dies may sometimes reach eight or more. The stacked dies are encapsulated in encapsulating material, and a redistribution structure may then be disposed over the stacked dies for electrical connection. However, with different configuration of the stacked dies, the layout of the redistribution structure need to be modified accordingly, which complicates the manufacturing process of the semiconductor package.

DETAILED DESCRIPTION

FIG. 1toFIG. 7illustrate schematic cross sectional views of various stages in a manufacturing process of a semiconductor package in accordance with some embodiments. In exemplary embodiments, the manufacturing process of the semiconductor package disclosed herein may be part of a wafer level packaging process. In some embodiments, one semiconductor device is shown to represent plural semiconductor devices of the wafer, and one single package is shown to represent plural semiconductor packages obtained the following semiconductor manufacturing process. The manufacturing process of the semiconductor package in the disclosure may include the following steps.

In some embodiments, at least one lower semiconductor device110is provided on a carrier101as it is shown inFIG. 4. In accordance with some embodiments of the present disclosure, the lower semiconductor device110may be a memory die, which may be a Dynamic Random Access Memory (DRAM) die, a Negative-AND (NAND) die, a Static Random Access Memory (SRAM) die, a Double-Data-Rate (DDR) die, or the like. The lower semiconductor device110may also be a logic device die or an integrated passive device die (with no active devices therein). The lower semiconductor device110may be a single memory die or a memory die stack. The respective steps of forming the lower semiconductor device110and the conductive pillars120thereon are illustrated in the process flow shown inFIG. 1toFIG. 3.

In some embodiments, the carrier101may be a glass carrier or any suitable carrier for the manufacturing process of the semiconductor package. In some embodiments, the carrier101may be coated with a de-bonding layer (e.g. the de-bonding layer104shown inFIG. 10). The material of the de-bonding layer may be any material suitable for de-bonding the carrier101from the above layers disposed thereon. For example, the de-bonding layer may be a ultra-violet (UV) curable adhesive, a heat curable adhesive, an optical clear adhesive or a light-to-heat conversion (LTHC) adhesive, or the like, although other types of de-bonding layer may be used. In addition, the de-bonding layer may be also adapted to allow light or signal to pass through. It is noted that the materials of the de-bonding layer and the carrier101are merely for illustration, and the disclosure is not limited thereto.

With reference now toFIG. 1, in some embodiments, a lower semiconductor device110′ in a wafer form is firstly provided. The wafer-form lower semiconductor device110′ includes a plurality of lower semiconductor device units, which can be diced into a plurality of lower semiconductor device110in the sequential process. For the sake of clarity and simplicity, one of the lower semiconductor device units is illustrated inFIG. 1andFIG. 2. Accordingly, throughout the description, the lower semiconductor device110′ can denote one of the lower semiconductor device units. In some embodiments, the lower semiconductor device110′ includes a substrate116, a plurality of electrical terminals112disposed on the substrate116, and a plurality of redistribution lines114electrically connected to the plurality of electrical terminals112. In some embodiments, the substrate116may be formed of semiconductor material with good thermal conductivity, such as silicon, etc. In some embodiments, active devices (not shown) such as transistors and/or diodes are formed at the top surfaces of the substrate116.

In some embodiments, the electrical terminals112may be metal pillars or metal pads, etc. The electrical terminals112are electrically coupled to the integrated circuits (not shown) inside the lower semiconductor device110′. In some embodiments, the electrical terminals112may be copper pillars, and may also include other conductive/metallic materials such as aluminum, nickel, or the like. In the present embodiment, the electrical terminals112may be offset from the center of the lower semiconductor device110′. In accordance with some exemplary embodiments of the present disclosure, the lower semiconductor device110′ may further include a passivation layer118disposed on the redistribution lines114and having a plurality of openings1181for revealing a part of the redistribution lines114. In some embodiments, the passivation layer118may be formed of a polymer such as polybenzoxazole (PBO) or polyimide in accordance with some exemplary embodiments.

With reference now toFIG. 2, a plurality of conductive pillars120are formed on the lower semiconductor device110′. In accordance with some embodiments of the present disclosure, the conductive pillars120are disposed along a direction parallel to a side (e.g. the right side) of the lower semiconductor device110′ as it is shown inFIG. 8andFIG. 9, and are electrically connected to the electrical terminals112respectively. In some embodiments, the conductive pillars120are offset from the center of the lower semiconductor device110′. In the present embodiment, multiple columns of the conductive pillars120arranged along the direction parallel to the (right) side of the lower semiconductor device110′ are illustrated herein, but the disclosure is not limited thereto. The number of the conductive pillars120(or the number of the columns of the conductive pillars120) is in accordance with the number of the electrical terminals112. In some embodiments, the conductive pillars120are formed in the openings1181of the passivation layer118to contact, and electrically connected to, the redistribution lines114exposed by the openings1181of the passivation layer118. Accordingly, the electrical terminals112are electrically connected to the plurality of conductive pillars120through the redistribution lines114respectively.

The formation of conductive pillars120may include the following steps. Firstly, a seed layer is formed. The seed layer may include a titanium layer and a copper layer over the titanium layer, and the seed layer may extend into the openings1181of the passivation layer118to contact, and electrically coupling to, the redistribution lines114. Then, a mask layer is formed over the seed layer, and is then patterned to form openings, through which some portions of the seed layer are exposed. Then, the conductive pillars120are formed in openings of the mask layer through plating. The mask layer is then removed. In accordance with some embodiments of the present disclosure, after the removal of the mask layer, the portions of the seed layer not directly underlying the conductive pillars120are removed in an etching process. The remaining portions of the seed layer thus become the bottom portions of the conductive pillars120. Throughout the description, the conductive pillars120refer to the portions of the plated material and the seed layer protruding higher than the top surface of the passivation layer118. The portions of the plated conductive material and the seed layer extending into the openings1181of the passivation layer118may be referred to as vias, which connect the overlying conductive pillars120to the underlying redistribution lines114.

Then, in some embodiments, the lower semiconductor device110′ may be flipped over and a thinning process may be optionally performed on a back surface of the substrate116of the lower semiconductor device110′. The thinning process may be, for example, a mechanical grinding or CMP process whereby chemical etchants and abrasives are utilized to react and grind away the substrate116of the lower semiconductor device110′. However, while the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the lower semiconductor device110′. For example, a series of chemical etches may alternatively be utilized. This process and any other suitable process may alternatively be utilized, and all such processes are fully intended to be included within the scope of the embodiments.

With reference now toFIG. 3, the lower semiconductor device110′ may be disposed on a tape carrier102by attaching the (ground) back surface of the lower semiconductor device110′ to the tape carrier102. In some embodiments, the lower semiconductor device110′ may be attached to the tape carrier102through the adhesive on the tape carrier102itself or through, for example, a die attach film (DAF). The tape carrier102bearing the lower semiconductor device110′ may further include a frame structure, which may be a metal ring intended to provide support and stability for the structure during the sequential process. In some embodiments, the tape carrier102may be made of, for example, polymer material with flexibility. In some embodiments, a singularizing process is performed to the lower semiconductor device110′ on the tape carrier102to form a plurality of lower semiconductor devices110independent from one another. One of the lower semiconductor devices110is illustrated inFIG. 3for the sake of clarity and simplicity. In an embodiment, the singularizing process may be performed by using a saw blade200to slice through the lower semiconductor device110′. Thereby, one unit of the lower semiconductor device110′ is separated from another to form a plurality of the lower semiconductor device110.

However, as one of ordinary skill in the art will recognize, utilizing a saw blade to singularize the lower semiconductor device110′ is merely one illustrative embodiment and is not intended to be limiting. Alternative methods for singularizing the lower semiconductor device110′, such as utilizing one or more etches to separate lower semiconductor device110′ and form the lower semiconductor devices110, may alternatively be utilized. These methods and any other suitable methods may alternatively be utilized for singularizing process.

FIG. 8illustrates a schematic top view of an intermediate stage in a manufacturing process of a semiconductor package in accordance with some embodiments. With reference now toFIG. 4andFIG. 8, at least one of the lower semiconductor devices110is then provided on the carrier101. In the embodiment shown inFIG. 8, a plurality of the lower semiconductor devices110(two are illustrated but not limited thereto) are provided. For example, the lower semiconductor devices110may include a first lower semiconductor device110aand a second lower semiconductor device110b, which are arranged in a side by side manner as it is shown inFIG. 8. In the present embodiment, a plurality of first electrical terminals112aof the first lower semiconductor device110amay be offset from the center of the first lower semiconductor device110a, and a plurality of second electrical terminals112bof the second lower semiconductor device110bmay be offset from the center of the second lower semiconductor device110b. In some embodiments, the first electrical terminals112aare disposed along a long side (e.g. an upper side) of the first lower semiconductor device110a, and the second electrical terminals112bare disposed along a long side (e.g. a lower side) of the second lower semiconductor device110b.

For example, the first electrical terminals112aare disposed along the upper side of the first lower semiconductor device110a, while no first electrical terminal112ais formed either close to the center or on the lower side of the first lower semiconductor device110a. The second electrical terminals112b, on the other hand, are disposed on the second lower semiconductor device110balong the lower side of the second lower semiconductor device110b, while no second electrical terminal112bis formed either close to the center or on the upper side of second lower semiconductor device110b. However, the embodiment is merely for illustration and is not intended to limit the arrangement of the electrical terminals112a,112b.

In some embodiments, the first conductive pillars120a, which are disposed on the first lower semiconductor device110aand electrically connected to the first electrical terminals112a, are arranged along a first direction D1parallel to a (short) side (e.g. a right side) of the first lower semiconductor device110a. Accordingly, the first direction D1is perpendicular to the long side where the first electrical terminals112aare disposed. Similarly, the second conductive pillars120b, which are disposed on the second lower semiconductor device110band electrically connected to the second electrical terminals112b, are arranged along a second direction D2parallel to a (short) side (e.g. a right side) of the second lower semiconductor device110b. Accordingly, the second direction D2is perpendicular to the long side where the second electrical terminals112bare disposed. In some embodiments, the first direction D1is substantially collinear with the second direction D2. Namely, the arrangement of the first conductive pillars120aand the second conductive pillars120bare substantially collinear with one another.

In accordance with some embodiments of the disclosure, the first lower semiconductor device110aand the second lower semiconductor device110bare arranged in a side by side manner with a gap P1exist therebetween. For example, the gap P1may range between about 50 μm to about 100 μm. Therefore, a shortest distance P1between the first conductive pillar120athat is closest to the second lower semiconductor device110aand the second conductive pillar120bthat is closest to the first lower semiconductor device110ais substantially longer than a gap P2between any adjacent two of the first conductive pillars120a. Moreover, the shortest distance P1between the first conductive pillar120athat is closest to the second lower semiconductor device110aand the second conductive pillar120bthat is closest to the first lower semiconductor device110ais substantially longer than a gap P3between any adjacent two of the second conductive pillars120b. In some embodiments, the gaps P2between the first conductive pillars120aand the gaps P3between the second conductive pillars120bmay not necessarily be the same, but the shortest distance P1should be substantially longer than the greatest gap P2and/or gap P3. In some embodiments, the shortest distance P1is substantially greater than 50 μm.

FIG. 9illustrates a schematic top view of an intermediate stage in a manufacturing process of a semiconductor package in accordance with some embodiments. It is noted that the semiconductor package shown inFIG. 9contains many features same as or similar to the semiconductor package disclosed earlier withFIG. 1toFIG. 4andFIG. 8. For purpose of clarity and simplicity, detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components. It should be understood that some components of the semiconductor package are omitted or illustrated in a perspective manner inFIG. 8andFIG. 9to better illustrate the underlying structure. The main differences between the semiconductor package shown inFIG. 9and the semiconductor package shown inFIG. 8are described as follows.

With reference now toFIG. 4andFIG. 9, in the present embodiment, one of the lower semiconductor devices110is provided on the carrier101. In accordance with some embodiments of the disclosure, at least some of the electrical terminals112are disposed along a side (e.g. the right side) of the lower semiconductor device110, while no electrical terminal112is formed either close to the center or on the left side of the lower semiconductor device110. Some of the electrical terminals112may be disposed along two opposite sides (e.g. the upper side and the lower side) of the lower semiconductor device110that is connected to the (right) side of the lower semiconductor device110. However, the embodiment is merely for illustration and is not intended to limit the arrangement of the electrical terminals112. In one of the implementation ofFIG. 9, a length of the lower semiconductor device110may be about 7 mm, and a width of the lower semiconductor device110may be equal to or less than about 7 mm, for example. On the other hand, in one of the implementation ofFIG. 8, a length of the first lower semiconductor device110aor the second lower semiconductor device110bmay be about 7 mm, while a width of the first lower semiconductor device110aor the second lower semiconductor device110bmay be equal to or less than about 3.5 mm, for example.

In some embodiments, the conductive pillars120are disposed along a direction parallel to a side (e.g. the right side) of the lower semiconductor device110. In some embodiments, the conductive pillars120are offset from a center of the lower semiconductor device110. In accordance with some embodiments of the disclosure, the layout of the conductive pillars120shown inFIG. 9is the substantially same as the configuration of the layout of the conductive pillars120a,120bshown inFIG. 8even through the arrangements of the lower semiconductor devices are different inFIG. 8andFIG. 9. Accordingly, the gap P1, corresponding to the shortest distance P1inFIG. 8, between adjacent two of the conductive pillars120is substantially greater than the gap P2/P3, corresponding to the gap P2/P3inFIG. 8, between any other adjacent two of the conductive pillars120. In one of the implementation, the gap P1between adjacent two of the conductive pillars120located in the middle of the lower semiconductor device110is substantially greater than the gap P2/P3between any other adjacent two of the conductive pillars120that are not located in the middle of the lower semiconductor device110. It is noted that the longest gap P1may not necessarily located in the middle of the lower semiconductor device110. The location of the gap P1shown inFIG. 9is corresponding to the location of the shortest distance P1inFIG. 8. In some embodiments, the gap P1inFIG. 9is substantially the same as the shortest distance P1inFIG. 8, and the gap P2/P3inFIG. 9are substantially the same as the gap P2/P3inFIG. 8.

With such configuration, the semiconductor packages with different arrangement of the lower semiconductor device and different layout of electrical terminals can adopt the same process for forming the redistribution structure electrically connected to conductive pillars since the locations of conductive pillars are the same. Therefore, the manufacturing process of the semiconductor package can be simplified and can be applied to different designs and configurations of the lower semiconductor devices. Accordingly, the production cost of the semiconductor package can be reduced and the productivity of the semiconductor package can be increased.

With reference now toFIG. 4,FIG. 8andFIG. 9, a dummy die130is disposed on a side of the lower semiconductor device110/110a/110b. In some embodiments, an upper surface of the dummy die130is substantially coplanar with an upper surface of the lower semiconductor device110. It is noted that the process shown inFIG. 4toFIG. 7can be applied to both the arrangements shown inFIG. 8andFIG. 9. Therefore, the “lower semiconductor device110” hereinafter may be referred to the first lower semiconductor device110aand the second lower semiconductor device110bshown inFIG. 8and may also be referred to the lower semiconductor device110shown inFIG. 9. Similarly, the “conductive pillars120” hereinafter may be referred to the first conductive pillars120aand the second conductive pillars120bshown inFIG. 8and may also be referred to the conductive pillars120shown inFIG. 9.

In accordance with some embodiments of the disclosure, the dummy die130may be a blank die dicing from a dummy wafer with no active devices (such as transistors and diodes) and passive devices (such as resistors, capacitors, and inductors) formed therein. The dummy die130may be formed of a rigid material. In some embodiments, the dummy die130may be formed of a metal or a metal alloy, a semiconductor material, or a dielectric material. For example, when including metal, the dummy die130may be formed of copper, aluminum, nickel, or the like. When formed of a semiconductor material, the dummy die130may be a silicon die, which may be the same type of die on which active devices are formed. When formed of a dielectric material, the dummy die130may be formed of ceramic. In addition, the material of the dummy die130may be homogenous. In accordance with some exemplary embodiments, the dummy die130is formed of silicon, with a p-type or an n-type impurity doped in the dummy die130. In accordance with alternative embodiments, no p-type impurity and n-type impurity are doped in the dummy die130.

With reference now toFIG. 5,FIG. 8andFIG. 9, an upper semiconductor device140is disposed on the lower semiconductor device110and the dummy die130, and reveals a portion (e.g. the right portion) of the lower semiconductor device110where the conductive pillars120are disposed. In some embodiments, the conductive pillars120are disposed on a side of the lower semiconductor device110offset from the center. Therefore, for not interfering with the conductive pillars120, the upper semiconductor device140is disposed offset from the center of the lower semiconductor device110to reveal the (right) portion of the lower semiconductor device110where the conductive pillars120are disposed. In some embodiments, the upper semiconductor device140is disposed offset from an (right) edge of the lower semiconductor device110for a clearance C1about 350 μm to leave room for the conductive pillars120. Accordingly, a part of the upper semiconductor device140may be cantilevered over the lower semiconductor device110, and the dummy die130may be disposed underneath the cantilevered part of the upper semiconductor device140to provide support and prevent the upper semiconductor device140from cracking. It is noted that, in some embodiments, the dummy die130may be omitted according to the size of the upper semiconductor device140. In some embodiments, a width W1of the dummy die130may be about 1.2 mm, and a length L1of the dummy die130may be about 7 mm, for example. The size of the dummy die130can be adjusted according to the sizes of the upper semiconductor device140and the lower semiconductor device110.

With reference now toFIG. 6, an encapsulating material150is formed on the carrier101and encapsulates encapsulating the lower semiconductor device110, the plurality of conductive pillars120, the dummy die130and the upper semiconductor device140. In some embodiments, the encapsulating material150is a single-layered encapsulating material, which may include a molding compound formed by a molding process. The material of the encapsulating material150may include epoxy or other suitable resins. For example, the encapsulating material150may be epoxy resin containing chemical filler. In some embodiments, the encapsulating material150is formed over the upper semiconductor device140and covers the top surfaces of the conductive pillars120and the top surface of the upper semiconductor device140, so as to form an encapsulated semiconductor device on the carrier101as it is shown inFIG. 6.

In some embodiments, a thinning process is performed on a top surface of the encapsulated semiconductor device. Accordingly, the encapsulating material150is ground to reveal the conductive pillars120and a plurality of the electrical terminals142of the upper semiconductor device140. In some embodiments, the thinning process may be, for example, a mechanical grinding or CMP process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulating material150. The resulting structure is shown inFIG. 6. After the thinning process is performed, the top surfaces of electrical terminals142of the upper semiconductor device140and the conductive pillars120are substantially level with the top surface of the encapsulating material150as shown inFIG. 6. However, while the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the encapsulating material150. For example, a series of chemical etches may alternatively be utilized. This process and any other suitable process may alternatively be utilized, and all such processes are fully intended to be included within the scope of the embodiments.

In some embodiment, the top surface of the encapsulating material150are ground and polished until the conductive pillars120and the electrical terminals142of the upper semiconductor device140are revealed. In some embodiments, the tips of the conductive pillars120and/or the tips of the electrical terminals142may also be ground to obtain a substantially planar surface. Accordingly, a ground surface of the encapsulating material150is substantially coplanar with the top surfaces of the conductive pillars120and the electrical terminals142of the upper semiconductor device140.

With reference now toFIG. 7, a redistribution structure160is formed over and electrically connected to the upper semiconductor device140and the conductive pillars120. In some embodiments, the redistribution structure160is formed on the encapsulating material150and the upper semiconductor device140. The redistribution structure160is electrically connected to the conductive pillars120and the electrical terminals142of the upper semiconductor device140. Namely, the conductive pillars120are electrically connected to the electrical terminals142of the upper semiconductor device140through the redistribution structure160. In some embodiments, a plurality of dielectric layers and a plurality of redistribution circuit layers may be stacked on top of one another alternately to form the redistribution structure160shown inFIG. 7. In some embodiments, the material of the dielectric layers of the redistribution structure160may include organic polymer such as, but not limited to, polyimide, etc. The material of the redistribution circuit layers may include copper, or any other suitable materials. In some embodiments, the redistribution circuit layer may be formed by a plating process. However, the disclosure does not limit the material and the manufacturing process of the dielectric layers and the redistribution circuit layers of the redistribution structure160.

In accordance with some embodiments of the disclosure, a plurality of conductive bumps170may be disposed on the redistribution structure160. In some embodiments, at least one integrated passive device (IPD) may also be mounted on the redistribution structure160. The conductive bumps170and the integrated passive device (if any) are electrically connected to the redistribution structure160. The formation of the conductive bumps170may include placing solder ball on the redistribution structure160, and then reflowing the solder ball. In alternative embodiments, the formation of the conductive bumps170may include performing a plating process to form solder material on the redistribution structure160, and then reflowing the solder material. The conductive bumps170may also include conductive pillars, or conductive pillars with solder caps, which may also be formed through plating. The integrated passive device132may be fabricated using standard wafer fabrication technologies such as thin film and photolithography processing, and may be mounted on the redistribution structure160through, for example, flip-chip bonding or wire bonding, etc.

Then, the carrier101shown inFIG. 6may be removed. In some embodiments, the carrier101is detached from the encapsulated semiconductor device, by causing an adhesive thereon to lose or reduce adhesion. The adhesive is then removed along with the carrier101. For example, the adhesive may be exposed to UV light, so that the adhesive loses or reduces adhesion, and hence the carrier101and the adhesive can be removed. At the time, a semiconductor package100may be substantially formed.

FIG. 10toFIG. 16illustrate schematic cross sectional views of various stages in a manufacturing process of a semiconductor package in accordance with some embodiments. It is noted that the semiconductor package with the arrangement illustrated inFIG. 8orFIG. 9may also be formed by other manufacturing process such as the process illustrate inFIG. 10toFIG. 16. Accordingly, the manufacturing process of the semiconductor package100′ shown inFIG. 10toFIG. 16contains many features same as or similar to the manufacturing process of the semiconductor package100disclosed earlier withFIG. 1toFIG. 9. For purpose of clarity and simplicity, detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components. The main differences between the manufacturing process of the semiconductor package100′ shown inFIG. 10toFIG. 16and the manufacturing process of the semiconductor package100shown inFIG. 1toFIG. 9are described as follows.

It is noted that the process shown inFIG. 10toFIG. 16can be applied to both the arrangements shown inFIG. 8andFIG. 9. Therefore, the “lower semiconductor device110” hereinafter may be referred to the first lower semiconductor device110aand the second lower semiconductor device110bshown inFIG. 8and may also be referred to the lower semiconductor device110shown inFIG. 9. Similarly, the “conductive pillars120” hereinafter may be referred to the first conductive pillars120aand the second conductive pillars120bshown inFIG. 8and may also be referred to the conductive pillars120shown inFIG. 9.

With reference now toFIG. 10, in accordance with some embodiments of the disclosure, the lower semiconductor device110and the dummy die130may first be disposed on the carrier101through, for example, a die attach film (DAF)103before the conductive pillars120are formed on the lower semiconductor device110. In some embodiments, a passivation layer118′ of the lower semiconductor device110may firstly cover a top surface of the redistribution lines114, and a passivation layer132′ may be optionally provided on a top surface of the dummy die130. In some embodiments, the carrier101may be a glass carrier or any suitable carrier for the manufacturing process of the semiconductor package. In some embodiments, the carrier101may be coated with a de-bonding layer104. The material of the de-bonding layer104may be any material suitable for de-bonding the carrier101from the above layers disposed thereon. For example, the de-bonding layer104may be a ultra-violet (UV) curable adhesive, a heat curable adhesive, an optical clear adhesive or a light-to-heat conversion (LTHC) adhesive, or the like, although other types of de-bonding layer may be used. In addition, the de-bonding layer104may be also adapted to allow light or signal to pass through. It is noted that the materials of the de-bonding layer104and the carrier101are merely for illustration, and the disclosure is not limited thereto.

With reference now toFIG. 11, in some embodiments, the lower semiconductor device110and the dummy die130are encapsulated in a first encapsulating material152. The first encapsulating material152may be a molding compound, a molding underfill, a resin, or the like in accordance with some embodiments. In some embodiments, the first encapsulating material152is dispensed as a fluid and then being compressed and cured, for example, in a thermal curing process. The first encapsulating material152fills the gaps between the lower semiconductor device110and the dummy die130. After the encapsulating process, the top surface of the first encapsulating material152may cover the top surfaces of the lower semiconductor device110and the dummy die130. Then, a thinning process such as a mechanical grinding, a CMP and/or a combination of both is performed to planarize the first encapsulating material152and reveal the redistribution lines114underneath as it is shown inFIG. 11. After the thinning process, top surfaces of the first encapsulating material152, the passivation layer118′, the redistribution lines114, and the dummy die130(or the passivation layer132′, if any) are substantially coplanar with one another.

With reference now toFIG. 12, in some embodiments, a dielectric layer180is formed over the first encapsulating material152, the lower semiconductor device110and the dummy die130. In some embodiments, the dielectric layer180may be formed of a polymer such as PBO, polyimide, BCB, or the like. The dielectric layer180is then patterned to form a plurality of openings182exposing a part of the underlying redistribution lines114.

With reference now toFIG. 13, in some embodiments, the conductive pillars120are then formed in the openings182with similar process described above, such that the conductive pillars120extends through the dielectric layer182via the openings182to contact, and electrically coupling to, the redistribution lines114.

With reference now toFIG. 14, in some embodiments, the upper semiconductor device110are attached to the dielectric layer180through, for example, a DAF141. Accordingly, the dielectric layer180is disposed between the lower semiconductor device110and the upper semiconductor device110. In some embodiments, the upper semiconductor device140may include the electrical terminals142embedded in the respective passivation layer144, which may be formed of a polymer such as PBO, polyimide, BCB, or the like.

With reference now toFIG. 15, in some embodiments, the upper semiconductor device140and the conductive pillars120are encapsulated in a second encapsulating material154. For example, the second encapsulating material154may be a molding compound, a molding underfill, a resin, or the like. Then, optionally, a thinning process such as a mechanical grinding, CMP or a combination of both is performed to planarize the second encapsulating material154, the upper semiconductor device140and the conductive pillars120, so that top surfaces of the electrical terminals142and the conductive pillars120are revealed. In the resulting structure, conductive pillars120penetrate through second encapsulating material154.

With reference now toFIG. 15, in some embodiments, with similar process described above, the redistribution structure160is formed over and electrically connected to the upper semiconductor device140and the conductive pillars120. In some embodiments, the redistribution structure160is formed on the second encapsulating material154and the upper semiconductor device140. The redistribution structure160is electrically connected to the conductive pillars120and the electrical terminals142of the upper semiconductor device140. Then, with similar process described above, the conductive bumps170may be disposed on a the redistribution structure160. In some embodiments, at least one IPD may also be mounted on the redistribution structure160. The conductive bumps170and the integrated passive device (if any) are electrically connected to the redistribution structure160. Then, the carrier101shown inFIG. 15may be removed. In some embodiments, the carrier101is detached from the encapsulated semiconductor device, by causing an adhesive thereon to lose or reduce adhesion. At the time, a semiconductor package100′ may be substantially formed.

Based on the above discussions, it can be seen that the present disclosure offers various advantages. It is understood, however, that not all advantages are necessarily discussed herein, and other embodiments may offer different advantages, and that no particular advantage is required for all embodiments.

In accordance with some embodiments of the disclosure, a semiconductor package includes a first lower semiconductor device, a second lower semiconductor device, a plurality of first conductive pillars, a plurality of second conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The first lower semiconductor device and the second lower semiconductor device are disposed in a side by side manner. The plurality of first conductive pillars are disposed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. The plurality of second conductive pillars are disposed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. The upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and reveals a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed. The encapsulating material encapsulates the first lower semiconductor device, the second lower semiconductor device, the plurality of first conductive pillars, the plurality of second conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over and electrically connected to the upper semiconductor device, the plurality of first conductive pillars and the plurality of second conductive pillars.

In accordance with some embodiments of the disclosure, a semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device, wherein a gap between adjacent two of the plurality of the conductive pillars is substantially greater than a gap between any other adjacent two of the plurality of the conductive pillars. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over and electrically connected to the upper semiconductor device and the plurality of conductive pillars.

In accordance with some embodiments of the disclosure, a manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.