Semiconductor memory apparatus with a write voltage level detection

A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2016-0121539, filed on Sep. 22, 2016, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor integrated circuit, and, more particularly, to a semiconductor memory apparatus.

2. Related Art

Semiconductor memory apparatuses are configured to store data and output stored data.

As semiconductor memory apparatuses trend toward large capacity and high speed operation, semiconductor memory apparatuses are being developed to normally store a large amount of data through one operation.

SUMMARY

In an embodiment, a semiconductor memory apparatus may include: a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation; and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

In an embodiment, a semiconductor memory apparatus may include: a write voltage detection circuit suitable for detecting a voltage level of a write voltage and generating a detection signal; a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to the detection signal; and a driving circuit suitable for driving data when activated in response to a write enable signal, the write cancel signal, and the rewrite signal, and transferring the driven data to a data storage region.

In an embodiment, a semiconductor memory apparatus may include: a plurality of driving circuits suitable for being applied with a write voltage and transferring data to a data storage region; a write voltage detection circuit suitable for detecting a voltage level of the write voltage and generating a detection signal; and a write control circuit suitable for simultaneously activating the plurality of driving circuits or first activating some of the plurality of driving circuits and activating remaining driving circuits after activating the plurality of driving circuits, in response to a write enable signal, a rate control signal, a rate enable signal, and the detection signal.

DETAILED DESCRIPTION

Hereinafter, a semiconductor memory apparatus will be described below with reference to the accompanying drawings through various examples of embodiments.

As shown inFIG. 1, a semiconductor memory apparatus in accordance with an embodiment may include a write voltage detection circuit100, a write control circuit200, first to eighth driving circuits310,320,330,340,350,360,370and380, and a data storage region400.

The write voltage detection circuit100may generate a detection signal Det by detecting, based on a specified level, the voltage level of a write voltage V_wt consumed when data is stored in the semiconductor memory apparatus, that is, in a write operation. For example, the write voltage detection circuit100may enable the detection signal Det when the voltage level of the write voltage V_wt becomes lower than a target level. The write voltage V_wt may be a driving voltage which is applied to the first to eighth driving circuits310,320,330,340,350,360,370and380.

The write control circuit200may generate a first write cancel signal WT_c1, a second write cancel signal WT_c2, a first rewrite signal Re_wt1, a second rewrite signal Re_wt2, and a third rewrite signal Re_wt3in response to a rate control signal Rate_ctrl, a rate enable signal Rate_en, the detection signal Det, and a write enable signal WT_en. For example, the write control circuit200may enable one of the first and second write cancel signals WT_c1and WT_c2in response to the rate control signal Rate_ctrl when the rate enable signal Rate_en is enabled, and generate the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3by delaying the write enable signal WT_en. The write enable signal WT_en may be a signal which is enabled in a write operation. The rate enable signal Rate_en and the rate control signal Rate_ctrl may be signals which are inputted from a controller or the output signals of a circuit for setting the circumstances of the semiconductor memory apparatus, that is, a mode register set or a fuse circuit. Further, the write control circuit200may generate at least one of the first to third rewrite signals Re_wt1, Re_wt2, and Re_wt3in response to the detection signal Det. Further yet, the write control circuit200may generate at least one rewrite control signal Re_wt1, Re_wt2, and Re_wt3in response to a voltage level of the write voltage V_wt in a write operation.

The write control circuit200may include a write cancel control circuit210and a rewrite control circuit220.

The write cancel control circuit210may enable one of the first and second write cancel signals WT_c1and WT_c2in response to the rate enable signal Rate_en, the rate control signal Rate_ctrl, and the detection signal Det. For example, the write cancel control circuit210may enable one of the first and second write cancel signals WT_c1and WT_c2in response to the rate control signal Rate_ctrl when the rate enable signal Rate_en is enabled and the detection signal Det is enabled. In detail, the write cancel control circuit210may enable the first write cancel signal WT_c1when the rate enable signal Rate_en and the detection signal Det are enabled and the rate control signal Rate_ctrl is enabled. The write cancel control circuit210may enable the second write cancel signal WT_c2when the rate enable signal Rate_en and the detection signal Det are enabled and the rate control signal Rate_ctrl is disabled.

The rewrite control circuit220may generate the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3in response to the first and second write cancel signals WT_c1and WT_c2and the write enable signal WT_en. For example, the rewrite control circuit220may generate and output the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3by selectively delaying the write enable signal WT_en in response to the first and second write cancel signals WT_c1and WT_c2being enabled. In detail, the rewrite control circuit220may sequentially enable the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3after a predetermined time passes from a time of a write operation by delaying the write enable signal WT_en when the first write cancel signal WT_c1of the first and second write cancel signals WT_c1and WT_c2is enabled. In other words, the rewrite control circuit220may sequentially enable at least one of the first to third rewrite signals Re_wt1, Re_wt2, and Re_wt3in response to the first and second write cancel signals WT_c1and WT_c2and the write enable signal WT_en. Meanwhile, the rewrite control circuit220may simultaneously enable the first and third rewrite signals Re_wt1and Re_wt3by delaying the write enable signal WT_en when the second write cancel signal WT_c2of the first and second write cancel signals WT_c1and WT_c2is enabled.

Each of the first and fifth driving circuits310and350among the first to eighth driving circuits310,320,330,340,350,360,370and380may be activated in response to the write enable signal WT_en, drive data, and transfer the driven data to the data storage region400. For example, each of the first and fifth driving circuits310and350may drive data when the write enable signal WT_en is enabled, and transfer the driven data to the data storage region400.

Each of the second and sixth driving circuits320and360among the first to eighth driving circuits320,320,330,340,360,360,370and380may be activated in response to the write enable signal WT_en, the first and second write cancel signals WT_c1and WT_c2, and the first rewrite signal Re_wt1. Further, each of the second and sixth driving circuits320and360may drive data upon activation, and transfer the driven data to the data storage region400. For example, each of the second and sixth driving circuits320and360may be activated in response to the write enable signal WT_en and the first rewrite signal Re_wt1, drive data upon activation, and transfer the driven data to the data storage region400. Each of the second and sixth driving circuits320and360may be deactivated when the first rewrite signal Re_wt1is disabled and even one of the first and second write cancel signals WT_c1and WT_c2is enabled, and does not perform a driving operation upon deactivation. In detail, each of the second and sixth driving circuits320and360may be activated when the write enable signal WT_en is enabled in the state in which both the first and second write cancel signals WT_c1and WT_c2are disabled. Each of the second and sixth driving circuits320and360may be deactivated even though the write enable signal WT_en is enabled in the state in which one of the first and second write cancel signals WT_c1and WT_c2is enabled in the write operation. Each of the second and sixth driving circuits320and360may be activated when the first rewrite signal Re_wt1is enabled even in the state in which one of the first and second write cancel signals WT_c1and WT_c2is enabled.

Each of the third and seventh driving circuits330and370among the first to eighth driving circuits330,320,330,340,370,360,370and380may drive data in response to the write enable signal WT_en, the first write cancel signal WT_c1, and the second rewrite signal Re_wt2, and transfer the driven data to the data storage region400. For example, each of the third and seventh driving circuits330and370may be activated in response to the write enable signal WT_en and the second rewrite signal Re_wt2, drive data upon activation, and transfer the driven data to the data storage region400. Each of the third and seventh driving circuits330and370may be deactivated when the first write cancel signal WT_c1is enabled, and does not perform a driving operation upon deactivation. In detail, each of the third and seventh driving circuits330and370may be activated when the write enable signal WT_en is enabled in the state in which the first write cancel signal WT_c1is disabled. Each of the third and seventh driving circuits330and370may be deactivated even though the write enable signal WT_en is enabled, in the state in which the first write cancel signal WT_c1is enabled. Each of the third and seventh driving circuits330and370may be activated when the second rewrite signal Re_wt2is enabled, even in the state in which the first write cancel signal WT_c1is enabled.

Each of the fourth and eighth driving circuits340and380among the first to eighth driving circuits340,320,330,340,380,360,370and380may be activated in response to the write enable signal WT_en, the first and second write cancel signals WT_c1and WT_c2and the third rewrite signal Re_wt3. Further, each of the fourth and eighth driving circuits340and380may drive data upon activation, and transfer the driven data to the data storage region400. For example, each of the fourth and eighth driving circuits340and380may be activated in response to each of the write enable signal WT_en and the third rewrite signal Re_wt3, drive data upon activation, and transfer the driven data to the data storage region400. Each of the fourth and eighth driving circuits340and380may be deactivated when the third rewrite signal Re_wt3is disabled and even one of the first and second write cancel signals WT_c1and WT_c2is enabled, and does not perform a driving operation upon deactivation. In detail, each of the fourth and eighth driving circuits340and380may be activated when the write enable signal WT_en is enabled in the state in which both the first and second write cancel signals WT_c1and WT_c2are disabled. Each of the fourth and eighth driving circuits340and380may be deactivated even though the write enable signal WT_en is enabled, in the state in which one of the first and second write cancel signals WT_c1and WT_c2is enabled. Each of the fourth and eighth driving circuits340and380may be activated when the third rewrite signal Re_wt3is enabled, even in the state in which one of the first and second write cancel signals WT_c1and WT_c2is enabled.

As shown inFIG. 2, the write cancel control circuit210may include first to third inverters IV1, IV2and IV3, and first and second NAND gates ND1and ND2. The first inverter IV1is inputted with the rate control signal Rate_ctrl. The first NAND gate ND1is inputted with the rate control signal Rate_ctrl, the detection signal Det, and the rate enable signal Rate_en. The second inverter IV2is inputted with the output signal of the first NAND gate ND1, and outputs the first write cancel signal WT_c1. The second NAND gate ND2is inputted with the output signal of the first inverter IV1, the detection signal Det, and the rate enable signal Rate_en. The third inverter IV3is inputted with the output signal of the second NAND gate ND2, and outputs the second write cancel signal WT_c2.

The write cancel control circuit210in accordance with an embodiment, configured as mentioned above, enables the first write cancel signal WT_c1in response to the rate control signal Rate_ctrl, when both the detection signal Det and the rate enable signal Rate_en are enabled. The write cancel control circuit210enables the second write cancel signal WT_c2when the rate control signal Rate_ctrl is disabled in the state in which the detection signal Det and the rate enable signal Rate_en are enabled. The write cancel control circuit210disables both the first and second write cancel signals WT_c1and WT_c2regardless of the rate control signal Rate_ctrl when even one of the detection signal Det and the rate enable signal Rate_en is disabled.

As shown inFIG. 3, the rewrite control circuit220may include first to third delay circuits221,222and223and an output selection circuit224.

The first delay circuit221may generate the first rewrite signal Re_wt1in response to the first and second write cancel signals WT_c1and WT_c2and the write enable signal WT_en. For example, the first delay circuit221may output the first rewrite signal Re_wt1by delaying the write enable signal WT_en, when even one of the first and second write cancel signals WT_c1and WT_c2is enabled.

The second delay circuit222may generate the second rewrite signal Re_wt2in response to the first write cancel signal WT_c1and the first rewrite signal Re_wt1. For example, the second delay circuit222may output the second rewrite signal Re_wt2by delaying the first rewrite signal Re_wt1, when the first write cancel signal WT_c1is enabled.

The third delay circuit223may delay the second rewrite signal Re_wt2and output a resultant signal when the first write cancel signal WT_c1is enabled.

The output selection circuit224may output one of the first rewrite signal Re_wt1and the output signal of the third delay circuit223, as the third rewrite signal Re_wt3, in response to the second write cancel signal WT_c2. For example, the output selection circuit224may output the output signal of the third delay circuit223as the third rewrite signal Re_wt3when the second write cancel signal WT_c2is disabled, and output the first rewrite signal Re_wt1as the third rewrite signal Re_wt3when the second write cancel signal WT_c2is enabled.

In the rewrite control circuit220in accordance with an embodiment, configured as mentioned above, as shown inFIG. 6A, if the first write cancel signal WT_c1is enabled and the second write cancel signal WT_c2is disabled, the first to third delay circuits221,222and223may sequentially delay the write enable signal WT_en and sequentially output the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3. In the rewrite control circuit220, as shown inFIG. 6B, if the first write cancel signal WT_c1is disabled and the second write cancel signal WT_c2is enabled, only the first delay circuit221among the first to third delay circuits221,222and223may delay the write enable signal WT_en, and the output signal of the first delay circuit221may be outputted as the first and third rewrite signals Re_wt1and Re_wt3.

As shown inFIG. 4, the second driving circuit320may include a first driver enable circuit321and a first driver322.

The first driver enable circuit321may generate a first driver enable signal Dr_en1in response to the first and second write cancel signals WT_c1and WT_c2, the write enable signal WT_en, and the first rewrite signal Re_wt1. For example, the first driver enable circuit321enables the first driver enable signal Dr_en1when the write enable signal WT_en is enabled, if both the first and second write cancel signals WT_c1and WT_c2are disabled. The first driver enable circuit321disables the first driver enable signal Dr_en1even though the write enable signal WT_en is enabled, if even one of the first and second write cancel signals WT_c1and WT_c2is enabled. The first driver enable circuit321enables the first driver enable signal Dr_en1when the first rewrite signal Re_wt1is enabled, in the case where even one of the first and second write cancel signals WT_c1and WT_c2is enabled.

The first driver enable circuit321may include first and second NOR gates NOR1and NOR2, a third NAND gate ND3, and fourth and fifth inverters IV4and IV5. The first NOR gate NOR1is inputted with the first and second write cancel signals WT_c1and WT_c2. The third NAND gate ND3is inputted with the write enable signal WT_en and the output signal of the first NOR gate NOR1. The fourth inverter IV4is inputted with the output signal of the third NAND gate ND3. The second NOR gate NOR2is inputted with the output signal of the fourth inverter IV4and the first rewrite signal Re_wt1. The fifth inverter IV5is inputted with the output signal of the second NOR gate NOR2, and outputs the first driver enable signal Dr_en1.

The first driver322drives inputted data Data_in in response to the first driver enable signal Dr_en1, and outputs driven data Data_out. For example, the first driver322drives the inputted data Data_in when the first driver enable signal Dr_en1is enabled, and outputs the driven data Data_out.

As shown inFIG. 5, the third driving circuit330may include a second driver enable circuit331and a second driver332.

The second driver enable circuit331may generate a second driver enable signal Dr_en2in response to the first write cancel signal WT_c1, the write enable signal WT_en, and the second rewrite signal Re_wt2. For example, the second driver enable circuit331enables the second driver enable signal Dr_en2when the write enable signal WT_en is enabled, if the first write cancel signal WT_c1is disabled. The second driver enable circuit331disables the second driver enable signal Dr_en2even though the write enable signal WT_en is enabled, if the first write cancel signal WT_c1is enabled. The second driver enable circuit331enables the second driver enable signal Dr_en2when the second rewrite signal Re_wt2is enabled, in the case where the first write cancel signal WT_c1is enabled.

The second driver enable circuit331may include a third NOR gate NOR3, a fourth NAND gate ND4, and sixth and seventh inverters IV6and IV7. The fourth NAND gate ND4is inputted with the write enable signal WT_en and the first write cancel signal WT_c1. The sixth inverter IV6is inputted with the output signal of the fourth NAND gate ND4. The third NOR gate NOR3is inputted with the output signal of the sixth inverter IV6and the second rewrite signal Re_wt2. The seventh inverter IV7is inputted with the output signal of the third NOR gate NOR3, and outputs the second driver enable signal Dr_en2.

The second driver332drives inputted data Data_in in response to the second driver enable signal Dr_en2, and outputs driven data Data_out. For example, the second driver332drives the inputted data Data_in when the second driver enable signal Dr_en2is enabled, and outputs the driven data Data_out.

The first driving circuit310and the fifth driving circuit350which are activated when the write enable signal WT_en is enabled may be configured in the same manner with the exception that only the designations of input and output signals thereof are different.

The fourth driving circuit340, the sixth driving circuit360and the eighth driving circuit380may be configured in the same manner as the second driving circuit320with the exception that only the designations of input and output signals thereof are different.

The seventh driving circuit370may be configured in the same manner as the third driving circuit330with the exception that only the designations of input and output signals thereof are different.

The operation of the semiconductor memory apparatus in accordance with the embodiment, configured as mentioned above, will be described below.

First, descriptions will be made for an operation in which all driving circuits are simultaneously activated by, for example, the write control circuit400and data is transferred to a data storage region in a write operation.

The write cancel control circuit210disables both the first and second write cancel signals WT_c1and WT_c2when even one of the rate enable signal Rate_en and the detection signal Det is disabled.

The rewrite control circuit220disables all of the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3when both the first and second write cancel signals WT_c1and WT_c2are disabled. Thus, the write control circuit200, may disable at least one write cancel signal WT_c1and WT_c2and at least one rewrite signal Re_wt1, Re_wt2, and Re_wt3when the detection signal Det is disabled.

All of the first to eighth driving circuits310,320,330,340,350,360,370and380are activated when the write enable signal WT_en is enabled, if all of the first and second write cancel signals WT_c1and WT_c2and the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3are disabled. The activated first to eighth driving circuits310,320,330,340,350,360,370and380drive data, and transfer the driven data to the data storage region400.

Summarizing these, in the write operation, the case where all the driving circuits310,320,330,340,350,360,370and380are simultaneously activated and perform driving operations corresponds to the case where even one of the rate enable signal Rate_en and the detection signal Det is enabled. That is to say, even in any case, the case where all the driving circuits310,320,330,340,350,360,370and380are simultaneously activated by the write control circuit200in response to the write enable signal WT_en and perform driving operations corresponds to the case where the rate enable signal Rate_en is disabled to allow all the driving circuits310,320,330,340,350,360,370and380to operate simultaneously or the case where the detection signal Det is disabled, that is, the write voltage V_wt used in writing is higher than the target level to perform a normal write operation. In one example, the write control circuit200may control the driving circuits310,320,330,340,350,360,370, and380to be simultaneously activated regardless of the rate control signal Rate_ctrl when the rate enable signal Rate_en is disabled.

Second, descriptions will be made for an operation in which some of the first to eighth driving circuits310,320,330,340,350,360,370and380are activated and operate first, and the remainder are activated and operate thereafter, in response to the write enable signal WT_en, the rate control signal Rate_ctrl, the rate enable signal Rate_en, and the detection signal Det. This corresponds to the case where the rate enable signal Rate_en is enabled and the detection signal Det is enabled with the write voltage V_wt lower than the target level. In this regard, the semiconductor memory apparatus in accordance with the embodiment discloses a technology that the first to eighth driving circuits310,320,330,340,350,360,370and380are sequentially activated by the unit of a pair of driving circuits or one half of the first to eighth driving circuits310,320,330,340,350,360,370and380is activated first and the other half of the first to eighth driving circuits310,320,330,340,350,360,370and380is activated thereafter. However, it is to be noted that the number of driving circuits to be activated first is not limited specifically.

The semiconductor memory apparatus in accordance with the embodiment may be configured such that, if the rate control signal Rate_ctrl is enabled in the state in which both the rate enable signal Rate_en and the detection signal Det are enabled, the first write cancel signal WT_c1of the first and second write cancel signals WT_c1and WT_c2is enabled and pairs of driving circuits are sequentially activated.

In detail, if the rate control signal Rate_ctrl is enabled in the state in which both the rate enable signal Rate_en and the detection signal Det are enabled, the write cancel control circuit210enables the first write cancel signal WT_c1of the first and second write cancel signals WT_c1and WT_c2.

The rewrite control circuit220sequentially enables the first to third rewrite signals Re_wt1, Re_wt2and Re_wt3by delaying the write enable signal WT_en, when the first write cancel signal WT_c1is enabled, as inFIG. 6A. In other words, the write control circuit200may enable at least one rewrite signal Re_wt1, Re_wt2, and Re_wt3after at least one of the write cancel signals WT_c1and WT_c2is enabled, when the detection signal Det is enabled.

The first and fifth driving circuits310and350which are controlled by only the write enable signal WT_en are activated when the write enable signal WT_en is enabled, drive data, and transfer the driven data to the data storage region400.

The second to fourth driving circuits320,330and340and the sixth to eighth driving circuits360,370and380which are controlled by the first write cancel signal WT_c1are deactivated due to the first write cancel signal WT_c1which is enabled, even though the write enable signal WT_en is enabled.

The second and sixth driving circuits320and360which are deactivated due to the enabled first write cancel signal WT_c1are activated again in response to the first rewrite signal Re_wt1which is generated by delaying the write enable signal WT_en. The activated second and sixth driving circuits320and360drive data, and transfer the driven data to the data storage region400.

The third and seventh driving circuits330and370which are deactivated due to the enabled first write cancel signal WT_c1are activated again in response to the second rewrite signal Re_wt2which is generated by delaying the first rewrite signal Re_wt1. The activated third and seventh driving circuits330and370drive data, and transfer the driven data to the data storage region400.

The fourth and eighth driving circuits340and380which are deactivated due to the enabled first write cancel signal WT_c1are activated again in response to the third rewrite signal Re_wt3which is generated by delaying the second rewrite signal Re_wt2. The activated fourth and eighth driving circuits340and380drive data, and transfer the driven data to the data storage region400.

Summarizing these, the write control circuit200of the semiconductor memory apparatus in accordance with an embodiment may sequentially activate pairs of driving circuits and sequentially transfer data to the data storage region400, if the rate control signal Rate_ctrl is enabled in the case where the rate enable signal Rate_en is enabled and the detection signal Det is enabled. In other words, the semiconductor memory apparatus in accordance with an embodiment may sequentially activate pairs of driving circuits and sequentially transfer data to the data storage region400, if the write voltage V_wt becomes lower than the target level in the state in which the rate enable signal Rate_en and the rate control signal Rate_ctrl are enabled, in a write operation. Further still, the write control circuit200may enable at least one write cancel signal WT_c1and WT_c2when the write voltage V_wt becomes lower than the target level, and the write control circuit200may generate at least one rewrite signal Re_wt1, Re_wt2, and Re_wt3after the write voltage V_wt becomes lower than the target level.

The write control circuit200of the semiconductor memory apparatus in accordance with an embodiment may be configured such that, if the rate control signal Rate_ctrl is disabled in the state in which both the rate enable signal Rate_en and the detection signal Det are enabled, the second write cancel signal WT_c2of the first and second write cancel signals WT_c1and WT_c2is enabled, and one half of the driving circuits are activated first and the other half of the driving circuits are activated thereafter.

In detail, if the rate control signal Rate_ctrl is disabled in the state in which both the rate enable signal Rate_en and the detection signal Det are enabled, the write cancel control circuit210enables the second write cancel signal WT_c2of the first and second write cancel signals WT_c1and WT_c2.

The rewrite control circuit220simultaneously enables the first and third rewrite signals Re_wt1and Re_wt3by delaying the write enable signal WT_en, when the second write cancel signal WT_c2is enabled, as inFIG. 6B.

The second driving circuit320, the fourth driving circuit340, the sixth driving circuit360, and the eight driving circuit380are inputted with the enabled second write cancel signal WT_c2, and are deactivated even though the write enable signal WT_en is enabled.

The first and fifth driving circuits310and350which are controlled by only the write enable signal WT_en and the third and seventh driving circuits330and370which are not controlled by the second write cancel signal WT_c2are activated when the write enable signal WT_en is enabled, drive data, and transfer the driven data to the data storage region400.

The second driving circuit320and the sixth driving circuit360which are deactivated due to the enabled second write cancel signal WT_c2even though the write enable signal WT_en is enabled are activated in response to the first rewrite signal Re_wt1which is generated by delaying the write enable signal WT_en. The activated second and sixth driving circuits320and360drive data, and transfer the driven data to the data storage region400.

The fourth driving circuit340and the eighth driving circuit380which are deactivated due to the enabled second write cancel signal WT_c2even though the write enable signal WT_en is enabled are activated in response to the third rewrite signal Re_wt3which is generated by delaying the write enable signal WT_en. The activated fourth and eighth driving circuits340and380drive data, and transfer the driven data to the data storage region400. Because the first and third rewrite signals Re_wt1and Re_wt3are signals which are enabled simultaneously, the second driving circuit320, the fourth driving circuit340, the sixth driving circuit360, and the eighth driving circuit380are simultaneously activated.

Summarizing these, the write control circuit200of the semiconductor memory apparatus in accordance with the embodiment may activate simultaneously one half of the driving circuits310,330,350and370and transfer data to the data storage region400, and activate thereafter the other half of the driving circuits320,340,360and380and transfer data to the data storage region400, if the rate control signal Rate_ctrl is disabled in the case where the rate enable signal Rate_en is enabled and the detection signal Det is enabled. In other words, the semiconductor memory apparatus in accordance with an embodiment may activate simultaneously one half of the driving circuits and transfer data to the data storage region400, and then activate the other half of the driving circuits and transfer data to the data storage region400, if the write voltage V_wt becomes lower than the target level in the state in which the rate enable signal Rate_en and the rate control signal Rate_ctrl are enabled, in a write operation.

As is apparent from the above descriptions, the semiconductor memory apparatus in accordance with the embodiment may be configured in such a manner that, if the voltage level of the voltage used in a write operation is lower than a target level, some of a plurality of driving circuits are activated first and the remainder are activated thereafter, whereby data may be transferred normally to a data storage region.

While various embodiments have been described above, it will be understood by those skilled in the art that the embodiments described are examples only. Accordingly, the semiconductor memory apparatus described herein should not be limited based on the described embodiments.