Phase interpolator

A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

TECHNICAL FIELD

This disclosure relates generally to electronic circuits, and in particular but not exclusively, relates to phase interpolators.

BACKGROUND INFORMATION

In many data communication configurations, no separate clock signal is communicated between a transmitter of a data stream and a receiver of the data stream. This requires recovering the clock from the data stream at the receiving end in order to then recover the data. This problem often arises when transferring digital data across one or more clock timing domains. It is not unusual to transmit digital data between clock timing domains having nearly the same underlying frequency clock, but different or varying phases with respect to each other.

The receiving end can derive a sampling signal from the data stream, and then use the sampling signal to sample the received data at sample times that produce optimal data recovery. In this way, data recovery errors can be minimized. Precision timing control techniques are desirable to achieve and maintain optimal sampling times, especially when the received data stream has high data rates, such as multi-gigabit-per-second data rates. Such timing control includes control of the phase and frequency of a sampling signal used to sample the received data signal.

As received data rates increase into the multi-gigabit-per-second range, the difficulty to effectively control the sampling phase in the receiver correspondingly increases. This problem is further aggravated at multi-gigabit frequencies since the data eye width (the period of time during which the received data is valid for sampling) decreases with increasing frequency.

Phase interpolators are often used to precisely position the sampling phase at the center of the received data eye. To maximize the setup and hold time margin, the sampling clock should be positioned with high precision and jitter minimized. Additionally, since chip performance is becoming limited by power delivery, reducing power consumption of a phase interpolator helps achieve high performance sampling.

DETAILED DESCRIPTION

FIG. 1is a functional block diagram illustrating a phase interpolator (“PI”)100, in accordance with an embodiment of the invention. The illustrated embodiment of PI100includes a phase mixer105, a delay lock loop (“DLL”)110, a multiplexer (“MUX”)115, a decoder120, a control circuit125, and compensation logic130.

Phase interpolation is used to extract a number of intermediate phases from a clock signal. PI100implements a phase interpolation function, which may be used in connection with a variety of applications. For example, PI100may be used to precisely position a sampling phase at the center of an eye width of a received data stream.

Referring toFIG. 2, a clock signal200is illustrated. Clock signal200is divided into eight evenly spaced phase intervals205(only one is labeled) ranging from 0° to 45°, 45° to 90°, 90° to 135°, 135° to 180°, 180° to 225°, 225° to 270°, 270° to 315°, and 315° to 360°. Phase delayed signals210(only a portion are labeled) having phase intervals205may be generated from clock signal200using a DLL, such as DLL110. Accordingly, in one embodiment, DLL110generates eight DLL clock signals (DLL_CLK_0, DLL_CLK_45, DLL_CLK_90, DLL_CLK_135, DLL_CLK_180, DLL_CLK_225, DLL_CLK_270, and DLL_CLK_315) from clock signal200each having a different phase delay. It should be appreciated that DLL110may generate more or less DLL clock signals and phase intervals205between the DLL clock signals need not be uniform. However, if it is desired to extract a greater number of phase delayed signals from clock signal200beyond that reasonably extractable from DLL110, then phase interpolation between the DLL clock signals may be used to achieve greater phase granularity.

Phase interpolation implemented by PI100may be used to extract phase delayed signals215having finer phase intervals220than the coarse phase intervals205. In the illustrated embodiment, eight phase delayed signals215having uniformly spaced phase intervals220are illustrated; however, it should be appreciated that other embodiments may interpolate more or less phase delayed signals215having uniformly or non-uniformly spaced phase intervals220.

In general, to achieve uniformly spaced phase intervals220from phase interpolation, the two signals being interpolated should have overlapping waveforms. For example, if interpolation is used to extract finer spaced phase delayed signals between DLL_CLK_135and DLL_CLK_180, then the phase of leading edge230of DLL_CLK_135should overlap the phase of lagging edge235of DLL_CLK_180. Accordingly, in one embodiment, the number of coarse phase delay signals210generated by DLL110is selected based on the rise time of signal200to achieve overlapping edges.

Returning toFIG. 1, the illustrated components of PI100are interconnected as follows. Control circuit125is coupled to decoder120to provide decoder120with a phase interpolator select (“PISEL”) signal. The PISEL signal is output by control circuit125to select the specific weighted phase delayed signal (“PHOUT”) output from phase mixer105. In the illustrated embodiment, the PISEL signal is a 6-bit binary coded signal. Control circuit125may be a state machine, a processor running executable code, or otherwise.

Decoder120is further coupled to phase mixer105and MUX115. Decoder120decodes the PISEL signal, and in response, outputs a MUXSEL0signal and a MUXSEL1signal to MUX115and a phase mixer select (“PMSEL”) signal to phase mixer105. The MUXSEL0signal selects which one of the DLL clock signals is forwarded to the output of MUX115as the phase input signal (PHIN0) to phase mixer105. Correspondingly, the MUXSEL1signal selects which one of the DLL clock signals is forwarded to the output of MUX115as the phase input signal (PHIN1) to phase mixer105. An exemplary coding of the PISEL signal and the MUXSEL0and MUXSEL1signals is listed in table405, illustrated inFIG. 3A.

The PMSEL signal is coupled into phase mixer105from decoder120to configure internal circuitry of phase mixer105for selective interpolation between PHIN0and PHIN1. In one embodiment, the PMSEL signal sets weighting factors for how the two signals PHIN0and PHIN1are combined to generate a weighted phase delayed signal (PHOUT) output from phase mixer105. In other words, the PMSEL signal determines the amount of interpolation between the phases of PHIN0and PHIN1by setting the weighting factors α and β when combining the phase delays of the two signals PHIN0and PHIN1. Phase mixer105generates weighted phase delayed signal PHOUT by mixing a weighted combination of PHIN0and PHIN1. In one embodiment, the output phase of the weighted phase delayed signal PHOUT is related to the phases of the input signals PHIN0and PHIN1accordingly to relation 1,
∠PHOUT=α·(∠PHIN0)+β·(∠PHIN1)  (Relation 1)
where ∠PHOUT represents the phase of PHOUT, ∠PHIN0represents the phase of PHIN0, ∠PHIN1represents the phase on PHIN1, and wherein α+β=1. In one embodiment, phase mixer105generates PHOUT having ∠PHOUT via weighted phase interpolation between ∠PHIN0and ∠PHIN1.

Compensation logic130is coupled to phase mixer105to provide compensation signals NBIAS and PBIAS thereto. The NBIAS and PBIAS signals are coupled into phase mixer105to compensate for changes in a variety of factors (e.g., operating temperature, process technology (e.g., transistor types, sizes, and materials), operation voltage, etc.) to maintaining relatively constant phase interpolation (e.g., size of phase intervals210) despite changes in these factors. In one embodiment, the PBIAS signal is coupled into phase mixer105to regulate the conductivity of various pull up paths within phase mixer105while the NBIAS signal regulates the conductivity of various pull down paths within phase mixer105.

FIG. 4is a flow chart illustrating a process400for operation of PI100, in accordance with an embodiment of the invention. The order in which some or all of the process blocks appear should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.

In a process block405, power is applied to PI100and/or PI100is reset. In a process block410, compensation logic130generates the PBIAS and NBIAS signals for biasing the pull up and pull down paths within phase mixer105. The PBIAS and NBIAS signals are generated by compensation logic130to maintain a relatively constant magnitude of PHOUT despite fluctuations in the operating voltage and temperature of PI100. Additionally, the PBIAS and NBIAS signals are used to compensate for different process technologies with which embodiments of PI100may be implemented. Compensation logic130may be implemented external to DLL110, as illustrated or may be physically implemented internal to DLL110as a subcomponent thereof. In one embodiment, the NBIAS signal is derived from a charge pump output of DLL110. Alternatively, PBIAS and NBAIS may simply be generated by application of fixed voltages.

In a process block415, DLL110generates the DLL clock signals from clock signal200. In the illustrated embodiment, DLL110generates eight DLL clock signals DLL_CLK_0, DLL_CLK_45, DLL_CLK_90, DLL_CLK_135, DLL_CLK_180, DLL_CLK_225, DLL_CLK_270, and DLL_CLK_315having evenly spaced phase delays 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. In other embodiments, DLL110may generate more or less DLL clock signals from clock signal200. It should be appreciated that in some embodiments, the generation of the DLL clock signals and the generation of the PBIAS and NBIAS compensation signals may occur simultaneously. Accordingly, process blocks410and415may occur contemporaneously.

In a process block420, control circuit125sets the PISEL signal to select a coarse phase interval and to select the interpolated phase within the coarse phase interval. In one embodiment, the PISEL signal is coded such that the three most significant bits (“MSB”) are used to select the coarse phase interval (e.g., any of phase intervals205) while the three least significant bits (“LSB”) are used to select the interpolated phase (e.g., any of phase delayed signals215) between the selected coarse phase interval. In essence, the three MSBs act as a coarse phase adjustment and the three LSBs act as a fine phase adjustment.

In a process block425, the three MSBs <5:3> of the PISEL signal are decoded by decoder120to generate the MUXSEL0and MUXSEL1signals. The MUXSEL0signal configures MUX115to select which one of the DLL signals is passed through MUX115as the PHIN0signal. The MUXSEL1signal configures MUX115to select which one of the DLL signals is passed through MUX115as the PHIN1signal. The two PHIN0and PHIN1signals are output from MUX115to phase mixer105. Although MUX115is illustrated as a single 8×2 multiplexer block, it should be appreciated that MUX115may represent two separate and physically independent 4×1 multiplexers.

In a process block430, the three LSBs <2:0> of the PISEL signal are decoded by decoder120to generate the PMSEL signal. The PMSEL signal is coupled into phase mixer105to select the interpolated phase between PHIN0and PHIN1. In one embodiment, the PMSEL signal is a thermometer coded signal as illustrated inFIG. 3B(discussed below). In a process block435, phase mixer105interpolates between PHIN0and PHIN1according to the PMSEL signal and generates the weighted phase delayed signal PHOUT.

FIG. 5is a functional block diagram illustrating a phase mixer500, in accordance with an embodiment of the invention. Phase mixer500is one possible embodiment of phase mixer105illustrated inFIG. 1. The illustrated embodiment of phase mixer500includes multiplexers M0through M7(collectively MUXs505), current drivers (“CDs”) L0through L7(collectively CDs510), and an output driver515. CDs510may also be referred to as current driver legs.

The components of phase mixer500are interconnected as follows. MUXs505each include two input ports, an output port, and a control port. One of the input ports of each MUX505is coupled to MUX115to receive PHIN0while the other input port is coupled to MUX115to receive PHIN1. The control port of each MUX505is coupled to receive one bit of the PMSEL signal. In the illustrated embodiment, the PMSEL signal is an 8-bit signal, each bit corresponding to the control port of one of MUXs505. The control port of each MUX505selects which input port is coupled to the output port in response to the PMSEL signal.

CDs510each include an input port (IN1), an output port (O1), a Pbias port (PB1), and an Nbias port (NB1). The output ports of MUXs505are each coupled to corresponding input ports IN1. Pbias ports PB1are coupled to receive the PBIAS signal from compensation logic130and Nbias ports NB1are coupled to receive the NBIAS signal from compensation logic130. Output ports O1of CDs510are coupled to a single node N1.

Output driver515includes an input port (IN2), an output port (O2), a Pbias port (PB2), and an Nbias port (NB2). Input port IN2is coupled to node N1and therefore to output ports O1of all CDs510. Pbias port PB2and Nbias port NB2are coupled to receive the PBIAS and NBIAS signals from compensation logic130, respectively.

During operation, each MUX505selectively passes one of the PHIN0and PHIN1signals to its corresponding CD510based on the PMSEL signal. Accordingly, some CDs510may receive PHIN0having a first phase (∠PHIN0) and some CDs501may receive PHIN1having a second phase (∠PHIN1). In one embodiment, the PMSEL signal is a thermometer coded signal, as illustrated inFIG. 3B. In the illustrated embodiment, each bit position of the PMSEL signal controls one of MUXs505and therefore determines whether each CD510is coupled to receive PHIN0having a phase ∠PHIN0or PHIN1having a phase ∠PHIN1.

CDs510each output a phase delayed current that is combined with the phase delayed current from the other CDs510at node N1. The combined phase delayed currents generate the weighted phase delayed signal PHOUT having a phase ∠PHOUT interpolated from a weighted combination of the phases ∠PHIN0and ∠PHIN1. Accordingly, if the PMSEL signal is such that a majority of CDs510receive PHIN0, then the interpolated phase ∠PHOUT of PHOUT will be closer to PHIN0. If the PMSEL signal is such that a majority of CDs510receive PHIN1, then the interpolated phase ∠PHOUT of PHOUT will be closer to PHIN1.

In one embodiment, CDs510are designed such that the following relations are true,

∠⁢⁢PHOUT=α·(∠⁢⁢PHIN⁢⁢0)+β·(∠⁢⁢PHIN⁢⁢1)(Relation⁢⁢2)∠⁢⁢PHOUT=xN·(∠⁢⁢PHIN⁢⁢0)+yN·(∠⁢⁢PHIN⁢⁢1)(Relation⁢⁢3)α=xN(Relation⁢⁢4)β=yN(Relation⁢⁢5)x+y=N(Relation⁢⁢6)
where N equals the total number of CDs510(eight illustrated inFIG. 5), x represents the number of CDs510coupled to receive PHIN0via MUXs505, and y represents the number of CDs510coupled to receive PHIN1via MUXs505. Accordingly, α and β are selectable weighting factors for combining ∠PHIN0and ∠PHIN1according to the selected value of the PMSEL signal. In one embodiment, the output drive strengths of CDs510are designed such that the phase delayed currents output by CDs510can be selectively combined at node N1to create substantially equal phase interpolated intervals220between ∠PHIN0and ∠PHIN1.

FIG. 6is a circuit diagram illustrating a current driver (“CD”) leg600, in accordance with an embodiment of the invention. CD leg600is one possible embodiment of CDs510illustrated inFIG. 5. The illustrated embodiment of CD leg600includes four transistors T1, T2, T3, and T4coupled in series between a high voltage rail VCC and a low voltage rail GND. Transistors T1and T2are positive metal oxide semiconductor (“PMOS”) transistors and transistors T3and T4are negative metal oxide semiconductor (“NMOS”) transistors. The gates of T2and T3are coupled together forming an inverter-like structure between input port IN1and output port O1. The gate of transistor T1is coupled to PBIAS port PB1to receive the PBIAS signal from compensation logic130. The gate of transistor T4is coupled to Nbias port NB1to receive the NBIAS signal from compensation logic130.

Transistor T1acts to control the conductivity of the pull up path605in response to the PBIAS signal. Similarly, transistor T4acts to control the conductivity of the pull down path610in response to the NBIAS signal. By controlling the conductivity of the pull up and pull down paths, the PBIAS and NBIAS signals can compensate for fluctuations in operation temperature and voltage, and different fabrication process technologies, to maintain the drive current at output port O1substantially constant across these changing factors. For example, if the operation temperature of PI100increases during operation, then compensation logic130may decrease the voltage of the PBIAS signal and increase the voltage of NBIAS signal to maintain a constant magnitude of the phase delayed current at output port O1.

As mentioned above, in some embodiments, CDs510are configured to generate substantially equal interpolated phase intervals220in response to a weighted thermometer coding of the PMSEL signal. Table 1 below illustrates example relative sizes of transistors T1and T4to achieve substantially equivalent interpolated phase intervals220using a weighted thermometer coding for the PMSEL signal.

TABLE 1CD LEGT4 RELATIVE SIZET1 RELATIVE SIZEL01x1.6xL10.75x1.2xL20.75x1.2xL30.9x1.4xL41.1x1.8xL51.6x2.6xL63.0x4.8xL75.5x8.8x
Table 1 illustrates example relative sizes of transistors T1and T4for an operational frequency approximately equal to 3.2 GHz of clock signal200.

As illustrated, CD leg600may be fabricated using standard complimentary metal oxide semiconductor (“CMOS”) technology. As such, CD leg600consumes little power, and that power that it does consume is primarily consumed during switching (dynamic power consumption). In other words, CD leg600consumes little static power, due to its CMOS compatibility. Accordingly, PI100provides a low power, high frequency, phase interpolation function. Prior art phase interpolates are typically implemented using differential signaling and therefore consume substantially more power than PI100(both dynamic and static power consumption), as well as, appropriately designing the relative sizes of the transistors in pull up path605and pull down path610.

In one embodiment, CDs510are matched current drivers. CDs510are matched in the sense that the magnitude of the combined current through node N1when node N1is being pulled down via pull down paths610of each CD510is substantially equivalent to the magnitude of the combined current through node N1when node N1is being pulled up via pull up paths605of each CD510. In other words, in this embodiment, the rise time and fall time of phase delayed signals215generated by phase mixer105are substantially symmetric, since the magnitude of the combined drive current through node N1generated by CDs510is substantially equal during the rising and falling stages of the weighted phase delayed signal PHOUT. In one embodiment, matching the rising and falling times of PHOUT can be achieved via appropriate bias of the PBIAS and NBIAS signals.

In the illustrated, CD leg600includes shunt capacitors C1and C2coupled across the gate and source of transistors T1and T4, respectively. These shunt capacitors reduce jitter on PHOUT by filtering noise on high voltage rail VCC and low voltage rail GND. If a noise spike is propagated on high voltage rail VCC, then shunt capacitor C1will pass that noise spike onto the gate of transistor T1thereby maintaining a constant gate-source voltage Vgs on transistor T1and maintaining the conductivity of pull up path605relatively constant. Similarly, if a noise spike is propagated on low voltage rail GND, then shunt capacitor C2will pass that noise spike onto the gate of transistor T4thereby maintaining a constant gate-source voltage Vgs on transistor T4and maintaining the conductivity of pull down path610relatively constant. In this manner, shunt capacitors C1and C2act to isolate output port O1from noise propagated on the voltage rails and bias ports PB1and NB1.

FIG. 7is a circuit diagram illustrating compensation logic700for generating the PBIAS signal, in accordance with an embodiment of the invention. The illustrated embodiment of compensation logic700is one possible embodiment for compensation logic130illustrated inFIG. 1. The illustrated embodiment of compensation logic700includes a comparator705and transistors T5, T6, T7, and T8coupled in series between the high voltage rail VCC and the low voltage rail GND. The negative input of comparator705is coupled to receive a voltage equal to half the voltage supplied by the high voltage rail (i.e., VCC/2). A simply voltage divider circuit may be used to generate VCC/2. The positive input of comparator705is coupled to an intermediate node N2between the drains of transistor T6and T7. The gate of transistor T5is coupled to the output of comparator705, the gate of transistor T6is coupled to the low voltage rail, the gate of transistor T7is coupled to the high voltage rail, and the gate of transistor T8is coupled to receive the NBIAS signal from the charge pump (not illustrated) of DLL110. A capacitor C3is further coupled between the output of comparator705and the high voltage rail VCC.

FIG. 8Ais a functional block diagram illustrating a system800for implementing an embodiment of the invention coupled to communicate with each other. System800includes two devices805and810. Devices805and810may represent any processing devices including computers, network elements (e.g., switches, routers, etc.), portable communication devices (e.g., cell phone) and the like. Device805includes a data processing unit820(e.g., microprocessor, central processing unit, etc.), a transmitter825, and random access memory (“RAM”)830. Device810includes a data processing unit820, RAM830, a receiver835, a sampler840, and PI100. RAMs830may include RAM types such as dynamic RAM (“DRAM”), synchronous DRAM (“SDRAM”), double data rate SDRAM (“DDR SDRAM”), static RAM (“SRAM”), and the like.

As illustrated, device805transmits a data stream815output from transmitter825to device810. Data stream815is received by receiver835and sampled by sampler840. Sampler840samples the received data stream815at specified sample times or sample phases to extract sampled data, and forwards the sampled data to data processing unit820. PI100is coupled to sampler840to precisely set the sampling phase of sampler840.

Referring to timing diagram850illustrated inFIG. 8B, to optimize recovery of data from data stream815, the sample time or sample phase ‘S’ should be centered in the middle of the eye width (“EW”) of the received data stream815. Clock signal200may be extracted from received data stream815or independently generated by device810. However, since the rising or falling edge of clock signal200typically will not fall at the center of the EW, PI100is used to generate intermediate phases for precisely aligning the sample phase S of sampler840with the center of the EW of received data stream815.

FIG. 9is a flow chart illustrating a process900for aligning the sampling phase S with the center of the EW of data stream815, in accordance with an embodiment of the invention. In a process block905data stream815is received at device810. In a process block910, PI100adjusts the sampling phase S to one direction (e.g., left) until data stream815is no longer validly sampled (decision block915). At the point where received data stream815is no longer validly sampled by sampler840, the current phase setting of PI100is set as the left phase boundary of the EW (process block920). In a process block925, PI100adjusts the sampling phase S to the other direction (e.g., right) until data stream815is no longer validly sampled (decision block930). At the point where received data stream815is again no longer validly sampled by sampler840, the current phase setting of PI100is set as the right phase boundary of the EW (process block935). The optimal sampling phase is then set at the midway point between the right and left phase boundaries of the EW. Process900may be periodically re-executed during communication sessions between devices805and810to compensate for relative phase drifts between the two devices.