Printed wiring board, semiconductor device, and method for manufacturing printed wiring board

A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.

This application is based on Japanese patent application No. 2009-171638 the content of which is incorporated hereinto by reference.

BACKGROUND

1. Technical Field

The present invention relates to a printed wiring board, a semiconductor device, and a method for manufacturing a printed wiring board.

2. Background Art

Electronic components such as semiconductor chip or semiconductor package are incorporated into various electronic instruments, and have increasingly been reduced in size and weight in recent years. In particular, electronic components to be incorporated into portable instruments such as mobile phone are required to be excellent in reliability after being mounted on printed wiring board, in terms of temperature cycle resistance, resistance against bending of board, impact resistance and so forth.

Japanese Laid-Open Patent Publication No. 2-268483 discloses a structure having a connection portion of a through-hole land and an interconnect, formed wider than the width of interconnect. According to the description of this publication, disconnection at land may be avoidable even if positional accuracy of the through-hole should degrade to some degree.

SUMMARY

The present inventor has recognized as follows. It is difficult for the technique disclosed in Japanese Laid-Open Patent Publication No. 2-268483 to prevent damages (disconnection of interconnects, cracking, and so forth) from occurring at wirings which are drawn out from the lands outermostly arranged in a mounting area for semiconductor package or other electronic components, ascribable to stress applied to the printed wiring board.

In one embodiment, there is provided a printed wiring board which includes: a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of the lands. A connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.

The present inventor has recognized as follows. On a printed wiring board, a portion where thermal stress or mechanical stress may most heavily be concentrated is a portion in the vicinity of a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area, and in particular in a portion along the outer circumferences of the outermost lands.

According to the embodiment, since the connection portion of at least one of the outermost lands and the wiring is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area, so that the wiring may no longer necessarily be disposed at the portion where the thermal stress or mechanical stress may most heavily be concentrated. Accordingly, the wiring connected to the specific land may be suppressed from being damaged (such as causing disconnection of interconnect, or cracking).

In another embodiment, there is provided a semiconductor device which includes: a printed wiring board including: a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of said lands, a connection portion of said specific land and said wiring connected to said specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of said outermost lands formed in said mounting area; and a semiconductor chip or a semiconductor package as said electronic component connected to said plurality of lands in said mounting area.

In yet another embodiment, there is provided a method for manufacturing a printed wiring board which includes forming a plurality of lands on a printed wiring board arranged in a mounting area allowing therein mounting of an electronic component, and forming an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of the lands, wherein the forming an wiring, the wiring is formed so that a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.

According to the embodiment, the wiring connected to the land, arranged outermostly in the mounting area of the electronic component may be suppressed from being damaged (such as causing disconnection of interconnect, or cracking).

DETAILED DESCRIPTION

Before describing of the present invention, the related art will be explained in detail with reference toFIG. 6toFIG. 8in order to facilitate the understanding of the present invention.

FIG. 6is a plan view illustrating a printed wiring board100of a comparative example, representing a mounting area100aand interconnect pattern therearound, in a semiconductor package such as BGA (Ball Grid Array) package109(seeFIG. 7) or LGA (Land Grid Array) package (not illustrated).FIG. 7is a sectional view illustrating a state of the printed wiring board100illustrated inFIG. 6, having the BGA package109mounted thereon by soldering (reflow mounting).

As illustrated inFIG. 6, the printed wiring board100has a plurality of lands102arranged thereon corresponding to a layout of terminals of a semiconductor package to be mounted on the printed wiring board100. More specifically, a mounting area100ahas a plurality of lands102arranged therein.

The printed wiring board100has a solder resist layer103formed on the surface thereof. Each land102has an NSMD (No Solder Mask Defined) structure. More specifically, in the solder resist layer103, solder resist openings104are formed at positions respectively corresponding to the lands102, and the individual lands102are exposed on the top surface side (the side more closer to the viewer inFIG. 6, and the upper side inFIG. 7) through the solder resist openings104. Diameter of each solder resist opening104is set slightly larger (typically larger by approximately 0.1 to 0.15 mm) than that of the land102.

From each land102, an wiring105is drawn out, and extended outward from the mounting area100a.

Out of the individual lands102in the mounting area100a, those outermostly arranged will be referred to as outermost lands hereinafter. Again out of the outermost lands, four lands arranged at the corners of the mounting area100awill be referred to as corner lands108hereinafter. A portion where the wiring105drawn out from the outermostly arranged land102and the inner circumference of the solder resist opening104corresponded to the land102cross with each other, will be referred to as an wiring-resist intersection106hereinafter.

A land-circumscribing line107illustrated inFIG. 6is a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area100a. In other words, the land-circumscribing line107may also be understood as a closed curve which collectively surrounds, by the shortest path, the outermost connection portions which are connection portions outermostly arranged, out of all connection portions of the semiconductor package and the printed wiring board10. Note that the land-circumscribing line107is also a boundary line between the mounting area100aand a region outside thereof.

In the structure illustrated inFIG. 6, each connection portion113of each outermostly arranged land102and each wiring105falls on the land-circumscribing line107. Also each wiring-resist intersection106falls on the land-circumscribing line107.

As illustrated inFIG. 7, the BGA package109has a body portion110, and solder balls111respectively provided to terminals (not illustrated) of the body portion110. In the state illustrated inFIG. 7, by heating the solder balls111on the BGA package109at or above the melting point thereof so as to cause reflow, the solder balls111are soldered onto the lands102, and thereby the BGA package109is mounted by soldering onto the printed wiring board100. For more details, in this state, the solder balls111are fused with solder paste (not illustrated) printed on the lands102.

Since the printed wiring board100and the semiconductor package (illustrated as the BGA package109inFIG. 7), after the above-described mounting by soldering, may be exposed to various environments, so that the terminals of the semiconductor package may be applied typically with thermal stress or mechanical stress.

In general, the printed wiring board100has a thermal expansion coefficient larger than that of the semiconductor package. Since the semiconductor package and the printed wiring board100are bonded with each other at the positions of the individual lands102in the mounting area100a, so that warping of the printed wiring board100may be limited by the contribution of the semiconductor package having a thermal expansion coefficient smaller than that of the printed wiring board100. However, the limitation is not effected on the region outside the mounting area100a. As a consequence, a portion of the printed wiring board100where the thermal stress may most heavily be concentrated resides in a portion along the outer circumferences of the outermost lands102, out of all portions in the vicinity of the land-circumscribing line107which is the boundary between the mounting area100aand the region outside thereof. More particularly, a portion along the inner circumference of the solder resist opening104may distinctively be applied with the thermal stress. Still more particularly, portions along the corner lands108, which are positioned mostly away from the center of the mounting area100a, out of all outermost lands102, may distinctively be applied with the thermal stress.

On the other hand, also for the case where the printed wiring board100is applied with mechanical stress (tensile stress or compressive stress) typically as a result of dropping, the mechanical stress may most heavily be applied to the portion along the outermost lands102, out of all portions in the vicinity of the outermost line107, similarly to the case of thermal stress.

In the printed wiring board100configured as illustrated inFIG. 6, each connection portion113of each outermost land102and each wiring105falls on the land-circumscribing line107. Also each wiring-resist intersection106of each wiring105connected to each outermost land102falls on the land-circumscribing line107. The wirings105connected to the outermost lands102extend outward from the mounting area100a.

Accordingly, the printed wiring board100repetitively applied with thermal stress, or applied with a large mechanical stress may cause cracking or disconnection112at the connection portion113of the outermost land102and the wiring105, or at the wiring-resist intersection106on the wiring105, typically as illustrated inFIG. 8.

As described in the above, the structure illustrated inFIG. 6has been difficult to suppress damages (disconnection, crack112(FIG. 8) and so forth), which possibly occur in the wirings105extended from the lands102outermostly arranged in the mounting area100aof a semiconductor package or other electronic components, due to stress applied to the printed wiring board100. Also the technique described in Japanese Laid-Open Patent Publication No. 2-268483 suffers from the same problem.

Embodiments of the present invention will be explained below, referring to the attached drawings. Note that any similar constituents will be given the same reference numerals or symbols in all drawings, and explanations therefor will not be repeated.

FIG. 1is a plan view of a printed wiring board1according to a first embodiment, and illustrates a mounting area1aallowing therein mounting of an electronic component, and the region therearound.FIG. 2is a sectional view of a semiconductor device30according to the first embodiment.FIGS. 3A to 3DandFIGS. 4A to 4Care sectional views illustrating a series of steps of manufacturing the printed wiring board according to the first embodiment.

The printed wiring board1according to this embodiment has a plurality of lands2arranged in the mounting area1aallowing therein mounting of an electronic component (a semiconductor package31(FIG. 2), for example), and wirings5respectively connected to at least one specific land (corner lands7, for example) out of outermost lands2which are outermostly arranged ones out of all lands2. Connection portions11of the specific lands and the wirings5connected to the specific lands fall inside a closed curve (a land-circumscribing line10) which collectively surrounds, by the shortest path, all outermost lands6formed in the mounting area1a.

The semiconductor device of this embodiment has the printed wiring board1according to this embodiment, and a semiconductor chip or a semiconductor package (semiconductor package31(FIG. 2), for example) as an electronic component connected to the plurality of lands2in the mounting area1a.

A method for manufacturing a printed wiring board of this embodiment

includes forming a plurality of lands2on a printed wiring board1arranged in a mounting area1aallowing therein mounting of an electronic component, and forming an wiring5respectively connected to a specific land which is at least one of the outermost lands6(corner lands7, for example) arranged outermostly out of the lands2, in the forming an wiring5, the wiring5is formed so that a connection portion of the specific land and the wiring5connected to the specific land is positioned inside a closed curve (the land-circumscribing line10) which collectively surrounds, by the shortest path, all of the outermost lands6formed in the mounting area.

Details will be given below.

First, a configuration of the printed wiring board1illustrated inFIG. 1will be explained.

As illustrated inFIG. 1andFIG. 2, the printed wiring board1has a plurality of lands2arranged corresponding to a layout of the terminals (not illustrated) of the electronic component (the semiconductor package31(FIG. 2), for example) to be mounted on the printed wiring board1. More specifically, on the printed wiring board1, a plurality of lands2are arranged in the mounting area1aallowing therein mounting of the electronic component.

In this embodiment, the lands2are arranged typically only on one surface of the printed wiring board1. The lands2are typically arranged so as to form a matrix pattern.

The printed wiring board1has a solder resist layer3on each of the top and back surfaces thereof. The individual lands2have an NSMD (No Solder Mask Defined) structure. In other words, in the solder resist layer3, solder resist openings4are formed at positions respectively corresponding to the lands2, and the individual lands2are exposed on the top surface side (the side more closer to an observer inFIG. 1, and the upper side inFIG. 2) in the solder resist openings4. Diameter of each solder resist opening4is set slightly larger (typically larger by approximately 0.1 to 0.15 mm) than that of each land2.

Note now that the lands2outermostly arranged in the mounting area1awill be referred to as outermost lands6hereinafter. Again out from the outermost lands6, four lands2arranged at the corners of the mounting area1awill be referred to as corner lands7hereinafter. In this embodiment, the corner lands7are the specific lands. In this embodiment, the outermost lands6other than the corner lands7are the second specific lands. The lands2other than the outermost lands6will now be referred particularly to as normal lands8.

The printed wiring board1further has wirings5,9respectively connected to at least one land2. In this embodiment, for example, an independent wiring5is connected to each of the corner lands7. On the other hand, an independent wiring9is connected to each of the normal lands8.

The land-circumscribing line10illustrated inFIG. 1is a closed curve which collectively surrounds, by the shortest path, all of the outermost lands6formed in the mounting area1a. In other words, the land-circumscribing line10may also be understood as a closed curve which collectively surrounds, by the shortest path, the outermost connection portions, which are outermostly-arranged connection portions out of all connection portions of the semiconductor package31and the printed wiring board1. The land-circumscribing line10is also the boundary line of the mounting area1aand the region outside thereof.

Each portion where the wiring5drawn out from the corner land7and the inner circumference of the solder resist opening4corresponded to the corner land7cross with each other, will be referred to as an wiring-resist intersection12hereinafter.

In this embodiment, the connection portions11of the corner lands7and the wirings5connected to the corner lands7fall inside the land-circumscribing line10. In addition, also the wiring-resist intersections12fall inside the land-circumscribing line10.

Each wiring5connected to each corner land7is specifically routed, typically so as to originate from the connection portion11, to run once in the direction away from the land-circumscribing line10, to be folded back at a folded portion13, to run through a gap14between the corner land7and the outermost land6adjacent to the corner land7(the gap14is preferably in the middle position thereof), and to extend outward beyond the land-circumscribing line10. More specifically, each folded portion13typically falls on a middle point of four lands2which include one corner land7and three lands2(two of which are the outermost lands6, and the residual one is the normal land8) adjacent to the corner land7.

The printed wiring board1further has vias15respectively connected to the outermost lands6other than the corner lands7, and internal wirings16respectively connected to the vias15. The internal wirings16are positioned lower than the land2, and one end of each individual internal wiring16is positioned right under the correspondent outermost land6. The outermost lands6other than the corner lands7are connected through the vias15to the internal wirings16right under the outermost lands6.

The exposed surface of each individual land2has an electroless plating17(seeFIG. 4C) formed thereon, so that the surface is protected by the electroless plating17.

The printed wiring board1has, typically as illustrated inFIG. 2, four metal layers represented by first layer21to fourth layer24. For example, the lands2and the wirings5,9are configured by the first layer21out of four metal layers, and the internal wiring16is configured by the second layer22or the third layer23(second layer22, for example).

The printed wiring board1further has, typically as illustrated inFIG. 2, a core substrate25(typically provided between the second layer22and the third layer23), and a prepreg26(independently between the first layer21and the second layer22, and between the third layer23and the fourth layer24, for example).

Next, a configuration of the semiconductor device30illustrated inFIG. 2will be explained.

As illustrated inFIG. 2, the semiconductor device30typically has the printed wiring board1configured as illustrated in the above, and the semiconductor package31connected to the lands2of the printed wiring board1.

The semiconductor package31has a body portion32having semiconductor elements (not illustrated) incorporated therein, a plurality of terminals (not illustrated) formed on the body portion32, and solder balls33respectively attached to the terminals. The semiconductor package31is typically a BGA package.

The individual lands2of the printed wiring board1are respectively corresponded to the individual terminals of the semiconductor package31.

The individual terminals of the semiconductor package31are respectively connected through the solder balls33to the correspondent lands2of the printed wiring board1.

Next, as an exemplary method for manufacturing a printed wiring board of this embodiment, a method for manufacturing a general build-up board will be explained below.

First, as illustrated inFIG. 3A; a substrate41is obtained. The substrate41has four metal layers represented by the above-described first layer21to fourth layer24, and the core substrates25and prepregs26interposed in between. The second layer22and the third layer23of the substrate41are preliminarily patterned in preceding processes.

Next, as illustrated inFIG. 3B, laser via holes42are formed so as to penetrate through the first layer21at predetermined portions, using a micro laser piercing machine (not illustrated). Each laser via hole42is formed through the prepreg26to a depth enough to reach the second layer22laid thereunder. Similarly, the a laser via hole43are formed so as to penetrate through the fourth layer24and another prepreg26at predetermined positions, to a depth enough to reach the third layer23laid thereabove.

Next, as illustrated inFIG. 3C, a plating44is filled in the laser via holes42to form the vias. In other words, portions of the plating44which extend through the prepreg26between the first layer21and the second layer22compose the vias15. On the other hand, portions of the plating44buried in the first layer21compose a part of the lands2. Similarly, a plating44is filled in the laser via holes43to form the vias45. In this way, the first layer21and the second layer22are electrically connected with each other, and the fourth layer24and the third layer23are electrically connected with each other. The plating44is typically a copper plating.

Next, as illustrated inFIG. 3D, the first layer21and the fourth layer24are respectively processed into predetermined patterns. More specifically, masks having openings according to predetermined patterns are formed independently over the first layer21and the fourth layer24by photolithography, and the first layer21and the fourth layer24are then etched through the opening into predetermined patterns. The pattern of the first layer21contains the patterns of the lands2and the wirings5,9.

Next, as illustrated inFIG. 4A, a solder resist is coated so as to cover the first layer21, to thereby form the solder resist layer3which covers the entire top surface of the printed wiring board1(FIG. 1,FIG. 2). Similarly, the solder resist is coated so as to cover the fourth layer24, to thereby form the solder resist layer3which covers the entire back surface of the printed wiring board1.

Next, as illustrated inFIG. 4B, the solder resist layer3on the top surface is processed by light exposure and development, into a predetermined pattern so as expose the lands2and the peripheries thereof. In other words, the solder resist openings4and so forth are formed.

Next, as illustrated inFIG. 4C, the individual lands2are subjected to surface treatment. More specifically, the surfaces of the individual lands2are typically covered with an electroless plating17for the purpose of protection of the exposed lands2. The electroless plating17is typically a Ni/Au plating. The Ni/Au plating is configured by forming a Ni (nickel) plating over the lands2, and then by forming an Au (gold) plating over the Ni plating.

The printed wiring board1may be obtained in this way.

Next, a method for manufacturing a semiconductor device of this embodiment will be explained.

For example, a solder is printed over the lands2of the printed wiring board1, the semiconductor package31is placed thereon, and the solder balls33on the semiconductor package31are allowed to reflow under heating at a temperature not lower than the melting point of the solder, to thereby bond the solder balls33to the correspondent lands2of the printed wiring board1. Accordingly, the semiconductor device30illustrated inFIG. 2may be obtained. More specifically, the solder balls33in this state are bonded while being fused with the solder (not illustrated) printed over the lands2, and the individual terminals of the semiconductor chip31are connected to the correspondent lands2, while placing the solder balls33and the solder (not illustrated) printed on the lands2in between.

Next, operations will be explained.

If the printed wiring board1, having the semiconductor chip31such as a BGA package mounted thereon, is applied with stress (thermal stress or mechanical stress), the stress is concentrated particularly in portions in the vicinity of the land-circumscribing line10, which represents the boundary between the mounting area1aand the region outside thereof, and particularly heavily in portions along the outer circumferences of the outermost lands6. Still more particularly, the stress may heavily be concentrated on the corner lands7positioned mostly away from the center of the mounting area1a.

In this embodiment, each connection portion11between each corner land7and each wiring5falls inside the land-circumscribing line10. Also each wiring-resist intersection12falls inside the land-circumscribing line10. Accordingly, the wirings5may no longer necessarily be disposed at the portion where the thermal stress or mechanical stress may most heavily be concentrated, and thereby the wirings5may be suppressed from being damaged (such as causing disconnection of interconnect, or cracking). This is because the mounting area1ais limited in warping of the printed wiring board1, by the contribution of the semiconductor chip31having a thermal expansion coefficient smaller than that of the printed wiring board1, and may therefore be applied with a less amount of thermal stress than the portions along the outer circumferences of the outermost lands6, out of the regions in the vicinity of the land-circumscribing line10. This is also because the printed wiring board1, applied with mechanical stress such as warping, may warp around the land-circumscribing line10assumed as a line of support, so as to concentrate the stress in the portions along the outermost lands6, but the warping of the printed wiring board1may be limited in the mounting area1aby the contribution of the semiconductor chip31, so that the mounting area1amay consequently be applied with a less amount of mechanical stress than the portions along the outer circumferences of the outermost lands6, among the regions in the vicinity of the land-circumscribing line10.

According to the first embodiment as described in the above, since the printed wiring board1has a plurality of lands2arranged in the mounting area1aallowing therein mounting of the semiconductor chip31(FIG. 2), and the wiring5respectively connected to the corner lands7, and since the connection portions11of the corner lands7and the wirings5connected to the corner lands7fall inside the land-circumscribing line10which collectively surrounds, by the shortest path, all outermost lands6formed in the mounting area1a, so that the wirings5may no longer necessarily be disposed at the portion where the thermal stress or mechanical stress may most heavily be concentrated. Accordingly, the wirings5connected to the corner lands7may be suppressed from being damaged (such as causing disconnection of interconnect, or cracking).

The wirings5connected to the corner lands7may be suppressed from being damaged, also because the wiring-resist intersections12of the wirings5connected to the corner lands7are positioned inside the land-circumscribing line10.

Each wiring5connected to each corner land7is specifically routed so as to run between the corner land7to which the wiring5is connected and the outermost land6adjacent to the corner land7, and to extend outward beyond the land-circumscribing line10. For more details, the wiring5is routed typically so as to originate from the connection portion11, to run once in the direction away from the land-circumscribing line10, to be folded back, to run through a gap14between the corner land7and the outermost land6adjacent to the corner land7, and to extend outward beyond the land-circumscribing line10. In other words, wirings5are routed across the land-circumscribing line10, but are routed away from the portions along the outer circumference of the outer most land6out of the portions in the vicinity of the land-circumscribing line10, so that the wirings5may be suppressed from being damaged. The wirings5may be suppressed from being damaged, also by the contribution of a fact that the portions of the wirings5across the land-circumscribing line10are covered with the solder resist layer3.

The outermost lands6other than the corner lands7are connected to the vias15, and also the internal wirings16positioned lower than the outermost lands6are connected to the vias15. The displacement of the printed wiring board1due to stress-induced warping is smaller in the depth-wise center portion thereof, than in the surficial portion thereof. Since the internal wirings16are positioned below the lands2which serve as the connection portions between the semiconductor package31and the printed wiring board1, so that the displacement of the printed wiring board1due to stress-induced warping may be smaller than in the case where the wirings are positioned in the surficial layer (in the same layer with the lands2). In addition, the internal wirings16are covered with the solder resist layer3and the prepreg26. Accordingly, the internal wirings16may be suppressed from being damaged, even when the printed wiring board1is applied with the stress.

FIG. 5is a plan view of a printed wiring board50of a second embodiment, and illustrates the mounting area1aallowing therein mounting of a BGA package or an LGA package as the semiconductor chip, and the portions therearound.

The printed wiring board50of this embodiment is configured similarly to the printed wiring board1of the first embodiment, except for the points explained below.

First, the printed wiring board50has no internal wirings16nor vias15, instead wirings53are connected to the outermost lands6other than the corner lands7.

Connection portions11between the outermost lands6other than the corner lands7and the wirings53are positioned inside the land-circumscribing line10. Each connection portion11between each outermost land6other than the corner lands7and each wiring53is positioned typically on the outer circumference of the outermost land6, at a portion thereof faced to the adjacent outermost land (corner land7, for example).

The wiring53is extend outward beyond the land-circumscribing line10, while being routed so that an wiring-resist intersection54, where the wiring53crosses the inner circumference of the solder resist opening4corresponded to the outermost land6to which the wiring53is connected, falls inside the land-circumscribing line10. More specifically, the wiring53is routed so as to run through a gap55(and preferably the center thereof) between the outermost land6to which the wiring53is connected and the adjacent outermost land6(corner land7, for example).

In this embodiment, each corner land7has no wiring5connected thereto, but instead has an wiring51connected thereto. The route of each wiring51is similar to the route of the wiring5from the connection portion11to the folded portion13in the first embodiment. Accordingly, the entire portion of the wiring51falls inside the land-circumscribing line10. The wiring51typically has a width nearly equal to the diameter of the corner land7at the connection portion11, and is narrowed towards the end51a. Each wiring51is connected, at around the end51athereof, to a via52. In other words, the portion around the end51aof each wiring51configures a via land. Each via52is further connected with an unillustrated internal wiring similar to the internal wiring16illustrated inFIG. 1. In other words, the via52is connected with the internal wiring positioned lower than the corner land7.

In this embodiment, all outermost lands6including the corner lands7represent the specific lands.

According to the above-described second embodiment, effects similar to those in the above-described first embodiment may be obtained, with respect to the wiring53connected to the outermost lands6other than the corner lands7, and also with respect to the wirings51connected to the corner lands7.

Since the via52is connected to the wiring51rather than the land2, so that it is no longer necessary to pierce the land2to form the via. Accordingly, there is no need of using an expensive micro laser piercing machine, and thereby cost of manufacturing the printed wiring board50may be reduced as compared with the first embodiment. While the vias15in the above-described first embodiment were connected to all outermost lands6other than the corner lands7, the vias52in this embodiment are connected only to the wiring51which are connected to the corner lands7, so that this embodiment needs a smaller number of vias to be formed as compared with the first embodiment (for example, the first embodiment needs the vias for each of eight lands2, whereas the second embodiment needs vias for each of four wirings51).

In the above-described embodiments, each of the printed wiring boards1,50may have a single mounting area1a, or may have two or more mounting areas1a. Each mounting area1amay have a plurality of lands2formed therein.

While the above-described embodiments dealt with the case where each of the printed wiring boards1,50had the mounting area1aonly on one surface thereof, and a plurality of lands2formed in the mounting area1a, each of the printed miring board1,50may alternatively have a mounting area1aon each of the top and back surfaces thereof, and a plurality of lands2may be formed in each mounting area1a.

While the above-described first embodiment dealt with the exemplary case where the internal wirings16were connected to the outermost lands6other than the corner lands7, also the wirings connected to the outermost lands6other than the corner lands7may alternatively be routed similarly to the wirings5connected to the corner lands7. More specifically, each wiring connected to the outermost land6other than the corner land7may be routed typically so as to originate from the connection portion, to run once in the direction away from the land-circumscribing line10, to be folded back at the folded portion, to run through a gap (and preferably the center thereof) between the outermost land6and the adjacent outermost land6(corner land7, for example), and to extend outward beyond the land-circumscribing line10.

Alternatively, in the first embodiment, the outermost lands6other than the corner lands7may be connected with the wirings53described in the second embodiment.

Still alternatively, the corner lands7may sequentially be connected with the wirings51, the vias52and the internal wirings as described in the second embodiment, and the outermost lands6other than the corner lands7may sequentially be connected with the vias15and the internal wirings16as described in the first embodiment.

While the above-described embodiments dealt with the case where the semiconductor package31, as the electronic component, was mounted on the mounting area1aof the printed wiring board1, an unpackaged semiconductor chip may alternatively be mounted in place of the semiconductor package31. Still alternatively, an electronic component other than the semiconductor package31or the semiconductor chip (capacitor, for example) may be mounted.

It is apparent that the present invention is not limited to the above embodiments, that may be modified and changed without departing from the scope and spirit of the invention.