Method of forming an array of elevationally-extending strings of programmable memory cells and method of forming an array of elevationally-extending strings of memory cells

A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

TECHNICAL FIELD

Embodiments disclosed herein pertain to methods of forming an array of elevationally-extending strings of programmable memory cells and to methods of forming an array of elevationally-extending strings of memory cells.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate.

NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass methods of forming an array of elevationally-extending strings of programmable transistors and/or memory cells, for example an array of NAND or other memory cells having peripheral control circuitry under the array (e.g., CMOS under-array). Embodiments of the invention encompass so-called “gate-last” or “replacement-gate” processing. Example embodiments are described with reference toFIGS. 1-19which may be considered as a “gate-last” or “replacement-gate” process.

FIGS. 1 and 2show a substrate construction10in process of a method of forming an array12of elevationally-extending strings of transistors and/or memory cells. Substrate construction10comprises a base substrate11having any one or more of conductive/conductor/conducting (i.e., electrically herein), semiconductive/semiconductor/semiconducting, or insulative/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS. 1 and 2-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within an array (e.g., array12) of elevationally-extending strings of memory cells may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. In this document, a “sub-array” may also be considered as an array.

Substrate construction10comprises a lower stack18comprising vertically-alternating insulative tiers20and wordline tiers22directly above an example conductively-doped semiconductor material16(e.g., conductively-doped polysilicon). Conductive material16may comprise a part of control circuitry (e.g., peripheral-under-array circuitry) used to control read and write access to the transistors and/or memory cells that will be formed within array12. Lower-stack insulative tiers20comprise insulative lower-stack first material24(e.g., silicon dioxide). Lower-stack wordline tiers22comprise lower-stack second material26that is of different composition from that of lower-stack first material24(e.g., silicon nitride, and regardless which may be wholly or partially sacrificial). Lower channel openings25have been formed (e.g., by dry anisotropic etching) into alternating tiers20,22, and may have individual bases21within material16.

By way of example only, lower channel openings25are shown as being arranged in groups or columns of staggered rows of four openings25per row. Any alternate existing or future-developed arrangement and construction may be used. Use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles. Other circuitry that may or may not be part of peripheral circuitry may be between conductively-doped semiconductor material16and stack18.

Referring toFIG. 3, lower-stack memory cell material30has been formed within lower channel openings25laterally across individual bases21and along sidewalls of lower channel openings25. In the context of this document, “memory cell material” is any material that comprises operative material in a finished memory cell construction including, by way of examples only, any one or more of gate material, source/drain material, charge-blocking material, charge-storage material, charge-passage material, gate dielectric, and channel material. In one embodiment, memory cell material30comprises at least one of (a) lower-stack charge-blocking material or (b) lower-stack charge-storage material (e.g., floating gate material such as doped or undoped silicon or charge-trapping material such as silicon nitride, metal dots, etc.). In one such embodiment, the memory cell material comprises (a). In one such embodiment, the memory cell material comprises (b). In one such embodiment, the memory cell material comprises (a) and (b). Memory cell material30may be formed by, for example, deposition of a thin layer thereof over lower stack18and within individual lower channel openings25followed by planarizing such back at least to an elevationally-outermost surface of stack18.

Referring toFIG. 4, a portion (e.g, a laterally-central portion and/or a radially-central portion) of lower-stack memory cell material30that is laterally across individual bases21in individual lower channel openings25has been removed. By way of example, such may occur by maskless anisotropic etching of material30using one or more etching chemistries, and which may be conducted in lieu of first removing such material from being over horizontal surfaces atop lower stack18as shown inFIG. 3.

Referring toFIG. 5, sacrificial covering material27(e.g., aluminum oxide and/or photoresist) has been formed in a lowest portion of individual lower channel openings25to cover individual bases21of individual lower channel openings25. In one embodiment and as shown, remaining volume of lower channel openings25(e.g. after the example processing shown byFIG. 4) is filled (i.e., completely) with sacrificial covering material27radially inside lower-stack memory cell material30. In one embodiment and as shown, covering material27is formed to have a planar top surface23. Lower-stack memory cell material30may also have a planar top surface19, and that is elevationally-coincident with top surface23of lower-stack memory cell material30.

Referring toFIG. 6, an upper stack35has been formed above lower stack18. Upper stack35comprises vertical-alternating insulative tiers20and wordline tiers22. In one embodiment, upper-stack insulative tiers20comprise insulative upper-stack first material24(that may be of the same or different composition from lower-stack first material24) and upper-stack wordline tiers22comprise upper-stack second material26(that may be of the same or different composition from that of lower-stack second material26) that is of different composition from that of upper-stack first material24. Only a few tiers20,22in each of the upper and lower stacks are shown although likely many more (e.g., dozens, hundreds, etc.) would be in each stack, and the stacks need not have the same number of tiers relative one another.

Referring toFIG. 7, upper channel openings37have been formed into upper stack35to lower channel openings25to form interconnected channel openings47individually comprising one of individual lower channel openings25and individual of upper channel openings37. Upper channel openings37may be considered as comprising individual bases39. In one embodiment and as shown, upper channel openings37have been formed (e.g., by dry anisotropic etching) to sacrificial covering material27to thereby have upper channel opening bases39which comprise covering material27. In one embodiment and as shown, covering material27has been elevationally recessed to less-than-fill lower channel openings25radially inward of lower-stack memory cell material30.

In one embodiment, covering material27is formed to initially have a planar top surface23(FIG. 5) which is subsequently rendered to be non-planar as-shown, for example by over-etching into sacrificial material27as shown inFIG. 7. In one embodiment and as shown, a laterally-central portion28(e.g., a radially-central portion) of covering-material bases39of upper channel openings37is formed to have a top surface that is lower than a top surface of laterally-outer portions33(e.g., a radially-outer portion) of covering material27. In one embodiment and as shown, the top surface of laterally-central portion28is not horizontal and in one such embodiment as shown is curved. In one embodiment, the top surfaces of laterally-outer portions33are not horizontal, and in one such embodiment are curved.

Referring toFIG. 8, upper-stack memory cell material30has been formed across individual bases39and along sidewalls of individual upper channel openings37. Upper-stack memory cell material30may be of the same or different composition(s) as lower-stack memory cell material30. Regardless, in one embodiment, upper-stack memory cell material30comprises at least one of (c) upper-stack charge-blocking material or (d) upper-stack charge-storage material (e.g., floating gate material such as doped or undoped silicon or charge-trapping material such as silicon nitride, metal dots, etc.). In one such embodiment, the memory cell material comprises (c). In one such embodiment, the memory cell material comprises (d). In one such embodiment, the memory cell material comprises (c) and (d). Upper-stack memory cell material30may be formed by, for example, deposition of a thin layer thereof over upper stack35and within individual upper channel openings37followed by planarizing such back at least to an elevationally-outermost surface of stack35.

Referring toFIG. 9, a portion of upper-stack memory cell material30that is laterally across individual bases39in individual upper channel openings37has been removed (e.g., by maskless anisotropic etching).

Referring toFIG. 10, sacrificial covering material27(not shown) has been removed from interconnected channel openings47(e.g., by wet or dry selective etching).

Transistor channel material36has been formed in an upper portion (i.e., at least) of interconnected channel openings47elevationally along vertically-alternating tier20,22in upper stack35(i.e., at least). In one embodiment and as shown, transistor channel material36has been formed concurrently in both upper channel openings37and lower channel openings25of interconnected channel openings47. Example channel materials36include appropriately-doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Example thickness for each of materials30,32,34, and36are 25 to 100 Angstroms. Interconnected channel openings47are shown as comprising a radially-central solid dielectric material38(e.g., spin-on-dielectric, silicon dioxide, and/or silicon nitride). Alternately, and by way of example only, the radially-central portion within interconnected channel openings47may include void space(s) (not shown) and/or be devoid of solid material (not shown).

Referring toFIGS. 12 and 13, horizontally-elongated (FIG. 12) trenches40have been formed (e.g., by anisotropic etching) into upper stack35and lower stack18and in one embodiment to conductively-doped semiconductor material16(i.e., at least to material16). Lateral edges of trenches40may at least in part be used to define lateral edges of wordlines (e.g., access or control-gate lines, and not shown inFIGS. 12 and 13) to be formed subsequently as described below.

Referring toFIG. 14, upper-stack second material26(not shown) and lower-stack second material26(not shown) of wordline tiers22have been etched selectively relative to insulative upper-stack first material24and selectively relative to insulative lower-stack first material24. An example etching chemistry, where second material26comprises silicon nitride and first material24comprises silicon dioxide is liquid or vapor etching with H3PO4as a primary etchant.

Referring toFIG. 15, control-gate material48(i.e., conductive material) has been formed into wordline tiers22through trenches40to be elevationally between insulative upper-stack first material24of upper-stack alternating tiers20and to be elevationally between insulative lower-stack first material24of lower-stack alternating tiers20. Any suitable conductive material may be used, for example one or both of metal material and/or conductively-doped semiconductor material.

Referring toFIGS. 16, 17, and 17a, control-gate material48has been removed from individual trenches40. Such has resulted in formation of wordlines29and elevationally-extending strings49of individual programmable transistors and/or memory cells56. In one embodiment and as shown, strings49are formed to be vertical or within 10° of vertical. Approximate locations of programmable transistors and/or memory cells56are indicated with brackets inFIG. 17Aand some with dashed outlines inFIGS. 16 and 17, with transistors and/or memory cells56being essentially ring-like or annular in the depicted example. Control-gate material48has terminal ends50(FIG. 17A) corresponding to control-gate regions52of individual transistors and/or memory cells56. Control-gate regions52in the depicted embodiment comprise individual portions of individual wordlines29.

A charge-blocking region (e.g., charge-blocking material30) is between charge-storage material32and individual control-gate regions52. A charge block may have the following functions in a memory cell: In a program mode, the charge block may prevent charge carriers from passing out of the charge-storage material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate, and in an erase mode the charge block may prevent charge carriers from flowing into the charge-storage material from the control gate. Accordingly, a charge block may function to block charge migration between the control-gate region and the charge-storage material of individual memory cells. An example charge-blocking region as shown comprises insulator material30. By way of further examples, a charge-blocking region may comprise a laterally (e.g., radially) outer portion of the charge-storage material (e.g., material32) where such charge-storage material is insulative (e.g., in the absence of any different-composition material between an insulative charge-storage material32and conductive material48). Regardless, as an additional example, an interface of a charge-storage material and conductive material of a control gate may be sufficient to function as a charge-blocking region in the absence of any separate-composition-insulator material30. Further, an interface of conductive material48with material30(when present) in combination with insulator material30may together function as a charge-blocking region, and as alternately or additionally may a laterally-outer region of an insulative charge-storage material (e.g., a silicon nitride material32).

Referring toFIGS. 18 and 19, an insulative-material lining55has been formed in individual trenches40over and elevationally along sidewalls of such trenches (e.g., silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, combinations of these, etc.). Another material57(dielectric and/or silicon-containing such as poly silicon) has been formed in individual trenches40elevationally along and spanning laterally between insulative-material lining55.

Further, “directly above” and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Additionally, “metal material” is any one or combination of an elemental metal, a mixture or an alloy of two or more elemental metals, and any conductive metal compound.

Herein, “selective” as to etch, etching, removing, removal, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

In some embodiments, a method of forming an array of elevationally-extending strings of memory cells comprises forming a lower stack comprising vertically-alternating insulative tiers and wordline tiers. The lower-stack insulative tiers comprise insulative lower-stack first material. The lower-stack wordline tiers comprise lower-stack second material that is of different composition from that of the lower-stack first material. Lower channel openings are in the lower stack. Lower-stack memory cell material is formed laterally across a base and along sidewalls of individual of the lower channel openings. A portion of the lower-stack memory cell material that is laterally across individual of the bases in the individual lower channel openings is removed. Sacrificial covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. An upper stack is formed above the lower stack. The upper stack comprises vertically-alternating insulative tiers and wordline tiers. The upper-stack insulative tiers comprise insulative upper-stack first material. The upper-stack wordline tiers comprise upper-stack second material that is of different composition from that of the upper-stack first material. Upper channel openings are formed into the upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. Upper-stack memory cell material is formed laterally across a base and along sidewalls of individual of the upper channel openings. A portion of the upper-stack memory cell material that is laterally across individual of the bases in the individual upper channel openings is removed. After the removing of the portion of the upper-stack memory cell material, the sacrificial covering material is removed from the interconnected channel openings. After the removing of the sacrificial covering material, transistor channel material is formed in an upper portion of the interconnected channel openings elevationally along the vertically-alternating tiers in the upper stack. After forming the transistor channel material, the upper-stack second material and the lower-stack second material of the wordline tiers are replaced with control-gate material. The control-gate material has terminal ends corresponding to control-gate regions of individual memory cells. The wordline tiers are formed to comprise charge-storage material between the transistor channel material and the control-gate regions, insulative charge-passage material between the transistor channel material and the charge-storage material, and a charge-blocking region between the charge-storage material and individual of the control-gate regions.

In some embodiments, a method of forming an array of elevationally-extending strings of memory cells comprises forming a lower stack comprising vertically-alternating insulative tiers and wordline tiers. The lower-stack insulative tiers comprise insulative lower-stack first material. The lower-stack wordline tiers comprise lower-stack second material that is of different composition from that of the lower-stack first material. Lower channel openings are in the lower stack. Formed is at least one of (a): lower-stack charge-blocking material in individual of the lower channel openings and laterally across a base and along sidewalls of the individual lower channel openings, or (b): lower-stack charge-storage material in the individual lower channel openings and laterally across the base and along the sidewalls of the individual lower channel openings. A portion of the at least one of (a) and (b) that is laterally across individual of the bases in the individual lower channel openings is removed. After removing the portion of at least one of (a) and (b), remaining volume of the lower channel openings is filled with sacrificial covering material. An upper stack is formed above the lower stack. The upper stack comprises vertically-alternating insulative tiers and wordline tiers. The upper-stack insulative tiers comprise insulative upper-stack first material. The upper-stack wordline tiers comprise upper-stack second material that is of different composition from that of the upper-stack first material. Upper channel openings are formed into the upper stack to the sacrificial covering material in the individual lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. Formed is at least one of (c): upper-stack charge-blocking material in individual of the upper channel openings and laterally across a base and along sidewalls of the individual upper channel openings, or (d): upper-stack charge-storage material in the individual upper channel openings and laterally across the base and along the sidewalls of the individual upper channel openings. A portion of the at least one of (c) and (d) that is laterally across individual of the bases in the individual upper channel openings is removed. After the removing the portion of the at least one of (c) and (d), the sacrificial covering material is removed from the interconnected channel openings. Transistor channel material is formed in an upper portion of the interconnected channel openings elevationally along the vertically-alternating tiers in the upper stack. After forming the transistor channel material, the upper-stack second material and the lower-stack second material of the wordline tiers are replaced with control-gate material. The control-gate material has terminal ends corresponding to control-gate regions of individual memory cells. The wordline tiers are formed to comprise charge-storage material between the transistor channel material and the control-gate regions, insulative charge-passage material between the transistor channel material and the charge-storage material, and a charge-blocking region between the charge-storage material and individual of the control-gate regions.