Echo cancellation device and echo cancellation method thereof applied in communication device

An echo cancellation device and an echo cancellation method thereof applied in a communication device are provided. The echo cancellation device includes an echo canceller and a combine circuit. The echo canceller obtains a plurality of delayed signals from a local signal of the communication device, and the delayed signals are divided into a plurality of delayed signal groups. The echo canceller selectively ignores at least one of the delayed signal groups, and the echo canceller generates an echo cancellation signal with the others of the delayed signal groups. The combine circuit is coupled to an interface circuit of the communication device to receive a received signal. The combine circuit cancels an echo component of the received signal with the echo cancellation signal to generate a cancelled signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwanese application no. 109146423, filed on Dec. 28, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a communication device; particularly, the disclosure relates to an echo cancellation device and an echo cancellation method thereof applied in a communication device.

Description of Related Art

A local communication device may transmit a local signal to a far end device through a communication channel, and receive a far end signal sent by the far end device through the communication channel. Specifically speaking, an interface circuit of the local communication device may transmit the local signal output by a transmitter circuit to the communication channel and receive the far end signal from the communication channel. The interface circuit of the local communication device may output a received signal corresponding to the far end signal to a receiver circuit of the local communication device. Generally speaking, the far end device is also configured with an interface circuit to establish a connection with the local communication device through the communication channel. During transmission of the local signal of the local communication device to the far end device, if an impedance of the communication channel does not match an impedance of the interface circuit (the interface circuit of the local communication device and/or the interface circuit of the far end device), an echo signal will be generated. That is, the received signal output by the interface circuit includes an echo component (noise). The echo component of the received signal requires to be cancelled.

SUMMARY

The disclosure provides an echo cancellation device and an echo cancellation method thereof adapted for a communication device to cancel an echo component of a received signal on the premise of reducing the number of calculations as much as possible.

In an embodiment of the disclosure, an echo cancellation device includes an echo canceller and a combine circuit. The echo canceller is configured to obtain a plurality of delayed signals from a local signal of the communication device, where the delayed signals are divided into a plurality of delayed signal groups. The echo canceller selectively ignores at least one of the delayed signal groups, and the echo canceller generates an echo cancellation signal with the others of the delayed signal groups. The combine circuit is coupled to the echo canceller to receive the echo cancellation signal. The combine circuit is coupled to an interface circuit of the communication device to receive a received signal. The combine circuit cancels an echo component of the received signal with the echo cancellation signal to generate a cancelled signal.

In an embodiment of the disclosure, an echo cancellation method includes the following. A plurality of delayed signals are obtained from a local signal of the communication device by an echo canceller, where the delayed signals are divided into a plurality of delayed signal groups. At least one of the delayed signal groups is selectively ignored, and an echo cancellation signal is generated with the others of the delayed signal groups by the echo canceller. A received signal is received from an interface circuit of the communication device, and an echo component of the received signal is cancelled with the echo cancellation signal to generate a cancelled signal by a combine circuit.

Based on the foregoing, according to the embodiment of the disclosure, the communication device and the echo cancellation method thereof may selectively ignore at least one delayed signal group of the delayed signal groups, and generates the echo cancellation signal with the other delayed signal groups of the delayed signal groups. Therefore, the communication device cancels the echo component of the received signal on the premise of reducing the number of calculations as much as possible.

DESCRIPTION OF THE EMBODIMENTS

The term “coupling (or connection)” used throughout the whole specification of the present application (including the appended claims) may refer to any direct or indirect connection means. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device may be directly connected to the second device, or the first device may be indirectly connected through other devices or some connection means to the second device. The terms “first”, “second”, and similar terms mentioned throughout the whole specification of the present application (including the appended claims) are merely used to name discrete elements or to differentiate among different embodiments or ranges, instead of limiting an upper bound or lower bound of the number of elements or the sequence of elements. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts. Reference may be mutually made to related descriptions of elements/components/steps using the same reference numerals or the same terms in different embodiments.

FIG.1is a schematic circuit block diagram of a communication device100according to an embodiment of the disclosure. The communication device100as shown inFIG.1may establish a connection with a far end device10through a communication channel20. Depending on design requirements, the communication channel20may include wires or other communication media. The wire of the communication channel20may be, for example (but not limited to), a 1000BASE-T cable, a 1000BASE-TX cable, or other communication cables. Depending on design requirements, in some embodiments, the far end device10may analogized with reference to the related description to the communication device100, so the implementation of the far end device10will not be repeatedly described.

In the embodiment as shown inFIG.1, the communication device100includes a transmitter circuit TX, an interface circuit110, an echo cancellation device120, and a receiver circuit RX. The interface circuit110is coupled to the transmitter circuit TX to receive a local signal x(n). The echo cancellation device120is coupled to the interface circuit110and the transmitter circuit TX to receive a received signal R(n) and the local signal x(n). The receiver circuit RX is coupled to the echo cancellation device120to receive a cancelled signal d(n).

Depending on different design requirements, the implementation of the echo cancellation device120may be hardware, firmware, software (i.e., program) or a combination of more than one of the three. In terms of the hardware form, the echo cancellation device120may be implemented in a logic circuit on an integrated circuit. Relevant functions of the echo cancellation device120may be implemented as hardware utilizing hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages. For example, the relevant functions of the echo cancellation device120may be implemented in various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASIC), digital signal processors (DSP), field programmable gate arrays (FPGA), and/or other processing units. In terms of the software and/or firmware form, the relevant functions of the echo cancellation device120may be implemented as programming codes. For example, the echo cancellation device120may be implemented with general programming languages (e.g., C, C++, or assembly language) or other suitable programming languages. The programming codes may be recorded/stored in a recording medium. The controller, microcontroller, or microprocessor may read and execute the programming codes from the recording medium, so as to realize the relevant functions of the echo cancellation device120.

The interface circuit110may transmit the local signal x(n) of the transmitter circuit TX of the communication device100through the communication channel20to the far end device10. The echo cancellation device120may obtain a plurality of delayed signals (delayed elements) from the local signal x(n), where the delayed signals may be divided into a plurality of delayed signal groups. The far end device10may transmit a far end signal11through the communication channel20to the communication device100. The interface circuit110may receive a far end signal s(n) corresponding to the far end signal11from the communication channel20, where the far end signal s(n) is the far end signal11passing through the channel. The interface circuit110may output the received signal R(n) corresponding to the far end signal s(n) to the echo cancellation device120.

During the process where the transmitter circuit TX transmits the local signal x(n) to an interface circuit of the far end device10, if an impedance of the transmission wire (the communication channel20) does not match an impedance of the interface circuit (the interface circuit110of the communication device100and/or the interface circuit of the far end device10), an echo signal will be generated in the transmission path. The echo signal (noise) will be returned to the communication device100and form an echo component of the received signal R(n). Generally speaking, components of the far end signal s(n) include the far end signal11and a far end echo, and components of the received signal R(n) include the far end signal s(n) and a near end echo. The echo cancellation device120is required for cancelling the echo component of the received signal R(n). Depending on design requirements, the echo cancellation device120may be configured with an adjustable finite impulse response (FIR) filter, least mean square (LMS) filter and/or other filters.

It is assumed herein that the echo cancellation device120may obtain N delayed signals x1, x2, . . . , xN(not shown inFIG.1) from the local signal x(n), where the N delayed signals x1to xNmay be divided into B delayed signal groups X1, X2, . . . , XB(not shown inFIG.1). Depending on design requirements, the N and the B may be arbitrary integers. The echo cancellation device120may selectively ignore at least one delayed signal group of the delayed signal groups X1to XB, and the echo cancellation device120generates an echo cancellation signal y(n) (not shown inFIG.1) taking the other delayed signal groups of the delayed signal groups X1to XBas tap input groups. The echo cancellation device120cancels the echo component of the received signal R(n) with the echo cancellation signal y(n) to generate the cancelled signal d(n) to the receiver circuit RX.

FIG.2is a schematic diagram of impulse response curves of the echo component of the received signal R(n) (FIG.2relates to an impulse response of the echo component of the received signal R(n)) as shown inFIG.1with the communication channel20of different lengths according to an embodiment of the disclosure. The horizontal axis of the impulse response curves as shown inFIG.2is related to tap coefficient groups (corresponding coefficient groups) H1to HN, for example, the tap coefficient groups H1, H2, H3, H4, and H5as shown inFIG.2. With reference toFIG.1andFIG.2, an impulse response curve310as shown inFIG.2is an impulse response curve of the received signal R(n) where the communication channel20is a short wire. In the impulse response curve310, an impulse311indicates a near end echo, and an impulse312indicates a far end echo. An impulse response curve320as shown inFIG.2is an impulse response curve of the received signal R(n) where the communication channel20is a long wire. In the impulse response curve320, an impulse321indicates a near end echo, and an impulse322indicates a far end echo.

Assuming herein that the echo cancellation device120may obtain 160 delayed signals x1to x160(not shown) (i.e., N=160) from the local signal x(n), where the delayed signals x1to x160may be equally divided into 5 delayed signal groups X1, X2, X3, X4, and X5(not shown) (i.e., B=5), then each of the delayed signal groups includes 160/5=32 delayed signals, and the tap coefficient groups H1to H5correspond to the delayed signal groups X1to X5. Where the echo cancellation device120does not ignore any of the delayed signal groups X1to X5, the echo cancellation device120takes the delayed signal groups X1to X5as tap input groups, and the echo cancellation device120may calculate the echo cancellation signal y(n) (not shown inFIG.1) with Formula 1 below. In Formula 1, a coefficient h[(b−1)*N/B]+krepresents a kthtap coefficient in a bthtap coefficient group Hb, namely a tap coefficient of a kthdelayed signal x[(b−1)*N/B]+kin a bthdelayed signal group Xb. That is, the echo cancellation device120may generate the echo cancellation signal y(n) taking all of the delayed signal groups X1to X5as tap input groups.
y(n)=Σb=1BHb*Xb=Σb=1BΣk=1N/Bh[(b−1)*N/B]+k*x[(b−1)*N/B]+kFormula 1

It can be observed from the impulse response curve310as shown inFIG.2that, where the communication channel20is a short wire, the echo cancellation device120may selectively ignore calculation of the echo cancellation signal for the delayed signal group X4and (or) X5, so that the communication device100may effectively reduce the number of calculations without affecting the echo cancellation. By analogy, it can be observed from the impulse response curve320as shown inFIG.2that, where the communication channel20is a long wire, the echo cancellation device120may selectively ignore calculation of the echo cancellation signal for the delayed signal group X2and (or) X3, so that the communication device100may effectively reduce the number of calculations without affecting the echo cancellation. That is, with the property that echo impulse responses are mostly sparse, the echo cancellation device120may ignore calculation of the echo cancellation signal for a corresponding sparse portion to reduce the number of calculations. The portion where the impulse response is sparsely distributed is related to length information of the channel. The echo cancellation device120may determine to ignore calculation of the echo cancellation signal for the corresponding sparse portion according to the wire length.

In the embodiment as shown inFIG.1, the echo cancellation device120may dynamically determine to be ignore which of the delayed signal groups X1to X5according to a length of the communication channel20. Taking the impulse response curve310(the communication channel20being a short wire) as an example, the echo cancellation device120may dynamically determine to ignore one (or more) delayed signal group of the delayed signal groups X2, X4, and X5. Taking the impulse response curve320(the communication channel20being a long wire) as an example, the echo cancellation device120may dynamically determine to ignore one (or more) delayed signal group of the delayed signal groups X2, X3, and X4.

FIG.3is a schematic circuit block diagram showing the interface circuit110as shown inFIG.1according to an embodiment of the disclosure. In the embodiment as shown inFIG.3, the interface circuit110includes a hybrid circuit111and an analog-to-digital converter (ADC)112. The hybrid circuit111is adapted for transmitting the local signal x(n) to the communication channel20and receiving the far end signal11through the communication channel20. The analog-to-digital converter112is coupled to the hybrid circuit111to receive the far end signal11. The analog-to-digital converter112is configured to convert the far end signal11into the received signal R(n).

FIG.4is a schematic circuit block diagram showing the echo cancellation device120as shown inFIG.1according to an embodiment of the disclosure. In the embodiment as shown inFIG.4, the echo cancellation device120includes an echo canceller121and a combine circuit122. The echo canceller121may obtain N delayed signals x1to xN(not shown inFIG.4) from the local signal x(n), where the delayed signals x1to xNmay be equally divided into B delayed signal groups X1to XB, and each delayed signal group includes N/B delayed signals. For example, the echo canceller121may obtain 160 delayed signals x1to x160from the local signal x(n), where the delayed signals x1to x160may be equally divided into 5 delayed signal groups X1to X5, and each delayed signal group includes 160/5=32 delayed signals. The delayed signal group X1includes the delayed signals x1to x32, the delayed signal group X2includes the delayed signals x33to x65, the delayed signal group X3includes the delayed signals x65to x96, the delayed signal group X4includes the delayed signals x97to x128, and the delayed signal group X5includes the delayed signals x129to x160.

FIG.5is a schematic flow chart of an echo cancellation method of a communication device according to an embodiment of the disclosure. With reference toFIG.4andFIG.5, in step S210, the interface circuit110may transmit the local signal x(n) of the communication device100through the communication channel20to the far end device10. In step S220, the echo canceller121may obtain a plurality of delayed signals (delayed elements) from the local signal x(n) of the communication device100. It is assumed herein that, in step S220, the echo canceller121obtains N delayed signals x1, x2, . . . , xN(not shown inFIG.4) from the local signal x(n), where the N delayed signals x1to xNare divided into B delayed signal groups X1, X2, . . . , XB(not shown inFIG.4). Depending on design requirements, the N and the B may be arbitrary integers. In step S230, the interface circuit110of the communication device100may receive the far end signal11sent by the far end device10through the communication channel20, that is, receive the far end signal s(n) from the communication channel20, to output the received signal R(n) corresponding to the far end signal s(n) to the echo cancellation device120.

In step S240, the echo canceller121may selectively ignore at least one of the delayed signal groups X1to XB, and the echo canceller121may generate the echo cancellation signal y(n) taking the other groups of the delayed signal groups X1to XBas tap input groups. For example, the echo canceller121may adaptively adjust a filter coefficient according to an echo noise (a residual echo) e(n) after echo cancellation. The echo noise e(n) may be a difference between the cancelled signal d(n) and the far end signal s(n). That is, e(n)=d(n)−s(n). According to the echo noise e(n), the echo canceller121may generate the echo cancellation signal y(n) with the tap input groups. The combine circuit122is coupled to the echo canceller121to receive the echo cancellation signal y(n). In step S250, the combine circuit122is coupled to the interface circuit110of the communication device100to receive the received signal R(n). In step S250, the combine circuit122may cancel the echo component of the received signal R(n) with the echo cancellation signal y(n) to generate a cancelled signal d(n) to the receiver circuit RX.

Taking the embodiment as shown inFIG.2as an example, the echo canceller121may dynamically determine to ignore which of the delayed signal groups X1to X5according to the length of the communication channel20. Where the communication channel20is a short wire (the impulse response curve310as shown inFIG.2), the echo canceller121may selectively ignore one (or more) of the delayed signal groups X2, X4, and X5(e.g., ignore the delayed signal group X5). By analogy, where the communication channel20is a long wire (the impulse response curve320as shown inFIG.2), the echo canceller121may selectively ignore one (or more) of the delayed signal groups X2, X3, and X4(e.g., ignore the delayed signal group X2).

FIG.6is a schematic circuit block diagram showing the echo canceller121as shown inFIG.5according to an embodiment of the disclosure. In the embodiment as shown inFIG.6, the echo canceller121includes an insertion loss detection circuit700and an echo cancelling circuit800. The insertion loss detection circuit700is coupled to the interface circuit110to receive the received signal R(n). The insertion loss detection circuit700may examine a power loss of the received signal R(n) to determine length information S/L of the communication channel20.

The echo cancelling circuit800is coupled to the insertion loss detection circuit700to receive the length information S/L. The echo cancelling circuit800may obtain a plurality of delayed signals x1to xN (e.g., x1to x160) (not shown inFIG.6) from the local signal x(n), where the delayed signals x1to xN may be equally divided into B delayed signal groups X1to XB (e.g., X1to X5), and each delayed signal group includes NB delayed signals. The echo cancelling circuit800may selectively ignore at least one of the delayed signal groups X1to XB according to the length information S/L, and take the other groups of the delayed signal groups X1to XB as a plurality of tap input groups. The echo cancelling circuit800may generate the echo cancellation signal y(n) with the tap input groups. Depending on design requirements, the echo cancelling circuit800may include a least mean square (LMS) filter800and/or other filters. The echo cancelling circuit800may adaptively adjust the filter coefficient according to the echo noise e(n). According to the echo noise e(n), the echo cancelling circuit800may generate the echo cancellation signal y(n) with the tap input groups.

Take the embodiment as shown inFIG.2as an example, the echo cancelling circuit800may determine the length of the communication channel20according to the length information S/L, and further dynamically determine to ignore which of the delayed signal groups X1to X5. Where the length information S/L indicates that the communication channel20is a short wire (the impulse response curve310as shown inFIG.2), the echo cancelling circuit800may selectively ignore one (or more) of the delayed signal groups X2, X4, and X5(e.g., ignore the delayed signal group X5). By analogy, where the length information S/L indicates that the communication channel20is a long wire (the impulse response curve320as shown inFIG.2), the echo cancelling circuit800may selectively ignore one (or more) of the delayed signal groups X2, X3, and X4(e.g., ignore the delayed signal group X2).

That is, with the property that echo impulse responses are mostly sparse, the echo cancelling circuit800may ignore calculation of the echo cancellation signal for the corresponding sparse portion to reduce the number of calculations. The portion where the impulse response is sparsely distributed is related to the length information of the channel. According to the length information S/L (wire length information) provided by the insertion loss detection circuit700, the echo cancelling circuit800may determine to ignore calculation of the echo cancellation signal for the corresponding sparse portion.

FIG.7is a schematic circuit block diagram showing the insertion loss detection circuit700as shown inFIG.6according to an embodiment of the disclosure. In the embodiment as shown inFIG.7, the insertion loss detection circuit700includes a high-pass filter710, a power calculating circuit720, a power calculating circuit730, and a calculating circuit740. The high-pass filter710is coupled to the interface circuit110to receive the received signal R(n). The high-pass filter710may extract a high-frequency component of the received signal R(n) to the power calculating circuit720. The power calculating circuit720is coupled to the high-pass filter710to receive the high-frequency component of the received signal R(n). The power calculating circuit720may calculate a high-band power PH of the high-frequency component. The power calculating circuit730is coupled to the interface circuit110to receive the received signal R(n). The power calculating circuit730may calculate a full-band power PF of the received signal R(n).

The calculating circuit740is coupled to the power calculating circuit720to receive the high-band power PH. The calculating circuit740is coupled to the power calculating circuit730to receive the full-band power PF. With the high-band power PH and the full-band power PF, the calculating circuit740may calculate a power loss rate (i.e., PH/PF). The calculating circuit740may determine the length information S/L according to the power loss rate PH/PF. As the power loss decreases, the PH/PF increases and the length of the communication channel20decreases. The calculating circuit740may compare, for example (but not limited to), the power loss rate PH/PF with a threshold THR. The threshold THR may be determined depending on design requirements. When the PH/PF is greater than the threshold THR, the calculating circuit740may determine that the communication channel20is a short wire, and notify the echo cancelling circuit800of the determination result through the length information S/L. On the contrary, when PH/PF is less than the threshold THR, the calculating circuit740may determine that the communication channel20is a long wire.

FIG.8is a schematic circuit block diagram showing the echo cancelling circuit800as shown inFIG.6according to an embodiment of the disclosure. In the embodiment as shown inFIG.8, the echo cancelling circuit800includes a buffer device810, a plurality of calculating circuits (e.g., calculating circuits820_1,820_2, . . . ,820_(B-M-1),820_(B-M) as shown inFIG.8) and an accumulator830. The buffer device810may buffer the local signal x(n) to output a plurality of delayed signals of the local signal x(n). For example, the buffer device810may obtain N delayed signals x1to xN(not shown inFIG.8) from the local signal x(n), where the N delayed signals x1to xNmay be divided into B delayed signal groups X1to XB, and each delayed signal group X includes N/B delayed signals x. Assuming the buffer device810may obtain 160 delayed signals x1to xNfrom the local signal x(n) (i.e., N=160), where the delayed signals x1to x160may be equally divided into 5 delayed signal groups X1to X5(i.e., B=5), then the delayed signal group X1includes the delayed signals x1to x32, the delayed signal group X2includes the delayed signals x33to x65, the delayed signal group X3includes the delayed signals x65to x96, the delayed signal group X4includes the delayed signals x97to x128, and the delayed signal group X5includes the delayed signals x129to x160.

The calculating circuits820_1to820_(B-M) are coupled to the buffer device810to respectively receive one (or more) corresponding delayed signal group of the delayed signal groups X1to XB. Each of the calculating circuits820_1to820_(B-M) takes one of the delayed signal groups X1to XBas the corresponding tap input group. Each of the calculating circuits820_1to820_(B-M) multiplies each tap input (delayed signal) in the corresponding tap input group by a corresponding coefficient (tap coefficient) to generate a corresponding product of each tap input. Each of the calculating circuits820_1to820_(B-M) accumulates the corresponding products to generate a corresponding accumulation result to the accumulator830.

Notably, the buffer device810generates the B delayed signal groups X1to XB, but the number B-M of the calculating circuits820_1to820_(B-M) is less than the number B of the delayed signal groups X1to XB, where M is an integer greater than zero. M is the number of delayed signal groups to be omitted. Delayed signal groups XM, XM′, and XB-Mas shown inFIG.8represent different groups of the delayed signal groups X1to XBgenerated by the buffer device810. For implementation details of at least one calculating circuit (e.g.,820_(B-M-1)) of the calculating circuits820_1to820_(B-M), reference may be made to description related to the calculating circuit820_2by analogy, and for implementation details of the other calculating circuits (e.g.,820_(B-M)) of the calculating circuits820_1to820_(B-M), reference may be made to description related to the calculating circuit820_1by analogy.

For example, the calculating circuit820_1may receive the delayed signal group X1(as the corresponding tap input group) from the buffer device810. The calculating circuit820_1may multiply each tap input (delayed signal) in the delayed signal group X1by the corresponding coefficient (tap coefficient) to generate the corresponding product. The calculating circuit820_1may accumulate the corresponding products corresponding to the delayed signal group X1to generate a corresponding accumulation result S1to the accumulator830. For example, the calculating circuit820_1may calculate the corresponding accumulation result S1with Formula 2 below. In Formula 2, a coefficient hkrepresents a tap coefficient corresponding to a kthdelayed signal xk(tap input) in the delayed signal group X1(corresponding tap input group).
S1=Σk=1N/Bhk*xkFormula 2

For another example, the calculating circuit820_2may receive two or more delayed signal groups from the buffer device810, such as the delayed signal group X2and another delayed signal group X2′. Depending on design requirements, the delayed signal group X2′ may be a delayed signal group that may be selectively ignored according to the wire length, and the delayed signal group X2may be another delayed signal group that may be selectively ignored according to the wire length. The calculating circuit820_2may select a corresponding delayed signal group from the delayed signal groups (e.g., the delayed signal groups X2and X2′) as the corresponding tap input group according to the length information S/L of the insertion loss detection circuit700.

Taking the embodiment as shown inFIG.2as an example, assuming that the echo cancelling circuit800may dynamically determine to ignore one of the delayed signal groups X2and X5according to the length of the communication channel20, then the delayed signal group X2′ as shown inFIG.8may be the delayed signal group X5. Where the communication channel20is a short wire (the impulse response curve310as shown inFIG.2), the calculating circuit820_2may select the delayed signal group X2as the corresponding tap input group, and then multiply each tap input (delayed signal) in the corresponding tap input group by the corresponding coefficient to generate the corresponding product (i.e., ignore the delayed signal group X5). The calculating circuit820_2may accumulate the corresponding products of the delayed signal group X2(corresponding tap input group) to generate a corresponding accumulation result S2to the accumulator830. For calculation of the corresponding accumulation result S2by the calculating circuit820_2, reference may be made to the description related to the calculation of the corresponding accumulation result S1by the calculating circuit820_1by analogy, so the same will not be repeatedly described.

Where the communication channel20is a long wire (the impulse response curve320as shown inFIG.2), the calculating circuit820_2may select the delayed signal group X5(i.e., X2′ as shown inFIG.8) as the corresponding tap input group, and then multiply each tap input (delayed signal) in the corresponding tap input group by the corresponding coefficient to generate the corresponding product (i.e., ignore the delayed signal group X2). The calculating circuit820_2may accumulate the corresponding products of the delayed signal group X5(corresponding tap input group) to generate the corresponding accumulation result S2to the accumulator830.

The accumulator830is coupled to the calculating circuits820_1to820_(B-M) to receive the corresponding accumulation results (e.g., S1and S2). The accumulator830may accumulate the corresponding accumulation results to generate the echo cancellation signal y(n) to the combine circuit122.

FIG.9is a schematic circuit block diagram showing the calculating circuit820_2as shown inFIG.8according to an embodiment of the disclosure.FIG.10is a schematic circuit block diagram showing the calculating circuit820_1as shown inFIG.8according to an embodiment of the disclosure. For implementation details of at least one of the calculating circuits as shown inFIG.8, reference may be made to the description related to the calculating circuit820_2as shown inFIG.9by analogy, and for implementation details of the other calculating circuits of the calculating circuits as shown inFIG.8, reference may be made to the description related to the calculating circuit820_1as shown inFIG.10by analogy.

In the embodiment as shown inFIG.9, the calculating circuit820_2includes a multiplexer821, a multiplier822, and an accumulator823. The multiplexer821is coupled to the buffer device810to receive the delayed signal group X2and the delayed signal group X2′. The multiplexer821may select one delayed signal group from the delayed signal group X2and the delayed signal group X2′ as a corresponding tap input group XX according to the length information S/L of the insertion loss detection circuit700. The multiplier822is coupled to the multiplexer821to receive the corresponding tap input group XX. The multiplier822may multiply each tap input (delayed signal) in the corresponding tap input group XX by a corresponding coefficient in a corresponding coefficient group (tap coefficient group) H9to generate a corresponding product in a corresponding product group H9X (tap product group). The accumulator823is coupled to the multiplier822to receive the corresponding products of the corresponding product group H9X. The accumulator823may accumulate each tap product in the tap product group (corresponding product group H9X) to generate the corresponding accumulation result S2to the accumulator830.

The calculating circuit820_2as shown inFIG.9further includes a coefficient calculating circuit824. The coefficient calculating circuit824may calculate the corresponding coefficient group (tap coefficient group) H9with the corresponding tap input group XX and the echo noise e(n) after echo cancellation, and provide the corresponding coefficient group H9to the multiplier822. In the embodiment, the calculation and algorithm of the coefficient calculating circuit824are not limited. Depending on design requirements, in some embodiments, the coefficient calculating circuit824may calculate the tap coefficient with conventional algorithms or other algorithms.

In the embodiment as shown inFIG.10, the calculating circuit820_1includes a multiplier825, an accumulator826, and a coefficient calculating circuit827. The coefficient calculating circuit827may take delayed signal group X1as the tap input group. The coefficient calculating circuit827may calculate a corresponding coefficient group (tap coefficient group) H10with the delayed signal group X1and the echo noise e(n) after echo cancellation, and provide the corresponding coefficient group H10to the multiplier825. For the coefficient calculating circuit827as shown inFIG.10, reference may be made to the description related to the coefficient calculating circuit824as shown inFIG.9by analogy, so the same will not be repeatedly described herein. The multiplier825is coupled to the buffer device810to receive the delayed signal group X1. The multiplier825may multiply each tap input (delayed signal) in the delayed signal group X1by a corresponding coefficient in the corresponding coefficient group (tap coefficient group) H10to generate a corresponding product in a corresponding product group (tap product group) H10X. The accumulator826is coupled to the multiplier825to receive the corresponding products of the corresponding product group H10X. The accumulator826may accumulate each tap product in the tap product group (corresponding product group H10X) to generate the corresponding accumulation result S1to the accumulator830.

In summary of the foregoing, in the communication device100and the echo cancellation method thereof according to the description in the foregoing embodiments, through the length information of the channel provided by the insertion loss detection circuit700, the echo cancelling circuit800may ignore the calculation of the echo cancellation signal corresponding to the sparse portion of the echo impulse response, and therefore selectively ignore at least one delayed signal group of the delayed signal groups X1to XB, and generate the echo cancellation signal y(n) taking the other delayed signal groups as the tap input groups. Therefore, the communication device100cancels the echo component of the received signal R(n) on the premise of reducing the number of calculations as much as possible, so as to generate the cancelled signal d(n) to the receiver circuit RX.