Circuit and method for sensing a capacitance

A transconductance amplifier mirror circuit is connected to an electrode for sensing the capacitance of the electrode with reference to ground, or the capacitance between the electrode and another electrode. A voltage level change is produced on the electrode connected to the transconductance amplifier mirror circuit to cause the transconductance amplifier mirror circuit to supply charges to or drain charges from a charge calculation circuit. The charge amount variation is converted to a signal for calculating the sensed capacitance.

FIELD OF THE INVENTION

The present invention is related to a circuit and method for sensing a capacitance.

BACKGROUND OF THE INVENTION

Conventionally, for sensing a capacitance of a capacitor, the capacitor is first charged to a certain voltage and then shunt to a reference capacitor for charge balance therebetween, by which the amount of charges transferred to the reference capacitor can be used to calculate the capacitance of the sensed capacitor based on the capacitance of the reference capacitor. However, this method requires to wait for a long time before the charge balance process finishes, and is thus applied only to the circuits with slower response speed.

For some applications, there is a need of a circuit and method for sensing a capacitance with faster response speed.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a circuit and method for sensing a capacitance between two electrodes.

Another objective of the present invention is to provide a circuit and method for sensing a capacitance of an electrode with reference to ground.

According to the present invention, a circuit for sensing a capacitance between two electrodes includes a switching circuit to change the voltage level of the first one of the two electrodes, a transconductance amplifier mirror circuit to detect the voltage variation at the second one of the two electrodes to cause a charge amount variation, and a charge calculation circuit to generate a sensed signal responsive to the charge amount variation.

According to the present invention, a circuit for sensing a capacitance of an electrode with reference to ground includes a switching circuit to change the voltage level of the electrode, a transconductance amplifier mirror circuit to detect the voltage variation at the electrode to cause a charge amount variation, and a charge calculation circuit to generate a sensed signal responsive to the charge amount variation.

According to the present invention, a method for sensing a capacitance between two electrodes includes changing the voltage level of the first one of the two electrodes, maintaining the voltage level of the second one of the two electrodes at a reference voltage to cause a charge amount variation responsive to the voltage variation at the second electrode, and generating a sensed signal responsive to the charge amount variation.

According to the present invention, a method for sensing a capacitance of an electrode with reference to ground includes changing the voltage level of the electrode, maintaining the voltage level of the electrode at a reference voltage to cause a charge amount variation responsive to the voltage variation at the electrode, and generating a sensed signal responsive to the charge amount variation.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a circuit diagram of a first embodiment according to the present invention, in which a circuit for sensing the capacitance Cm between electrodes10and12includes a switching circuit14, a transconductance amplifier mirror circuit16, a charge calculation circuit22and a measure unit24. In this embodiment, the switching circuit14includes switches S1and S2both connected to the electrode10to switch the voltage of the electrode10to a higher voltage level or a lower voltage level, for example, a supply voltage VDD and a ground voltage GND as shown inFIG. 1. A sensing switch S3is connected between the other electrode12and the transconductance amplifier mirror circuit16, controlled to connect the first output port of the transconductance amplifier mirror circuit16to the electrode12. The transconductance amplifier mirror circuit16includes two common input transconductance amplifiers18and20, one of the common input ports is applied with a reference voltage VREF that lies between the supply voltage VDD and the ground voltage GND, and the transconductance amplifier18has its another common input port connected to its output port that is as the first output port of the transconductance amplifier mirror circuit16connected to the sensing switch S3. The transconductance amplifier20has its output port as the second output port of the transconductance amplifier mirror circuit16connected to the charge calculation circuit22, and the charge calculation circuit22includes a capacitor Cint connected between the output port of the transconductance amplifier20and the ground GND, and an initialization switch S4connected between the output ports of the transconductance amplifiers18and20. To sense the capacitance Cm, the switch S4is first turned on for a time period to initialize the voltage Vo of the capacitor Cint to the reference voltage VREF. A switch S5is connected between the charge calculation circuit22and the measure unit24, and during the switch S5is on, the measure unit24may convert the voltage Vo of the capacitor Cint into a digital signal. At the beginning of sensing the capacitance Cm, the voltage V1of the electrode10is changed responsive to the switching of the switches S1and S2in the switching circuit14. When the voltage V1falls down, the transconductance amplifier mirror circuit16will try to maintain the voltage V2of the electrode12at the reference voltage VREF, and thus the transconductance amplifier18will supply charges to the electrode12responsive to the difference between the voltage V2and the reference voltage VREF, and responsive to the variation of the voltage V2, the transconductance amplifier20also supplies charges to the charge calculation circuit22. Since the transconductance amplifiers18and20are in a common input configuration, the amount of charges supplied by the transconductance amplifier20to the charge calculation circuit22will be proportional to the amount of charges supplied by the transconductance amplifier18to the electrode12. The charge calculation circuit22stores the received charges on the capacitor Cint. At the end of sensing the capacitance Cm, the voltage Vo of the capacitor Cint will be related to the capacitance Cm, and the switch S5is turned on for the measure unit24to convert the voltage Vo into a digital signal. Due to connections of hardware circuitry or wire routing on a printed circuit board (PCB), there may be parasitic capacitances Cp1and Cp2on the electrodes10and12, respectively that are not possessed by the electrodes10and12themselves. However, the transconductance amplifier mirror circuit16has a feedback mechanism that sets the voltage of the parasitic capacitor Cp2at the reference voltage VREF before and after sensing the capacitance Cm, thereby preventing the charge calculation circuit22from being affected by the parasitic capacitances Cp1and Cp2.

FIG. 2is a circuit diagram of a second embodiment according to the present invention, whose operational modes and principles are similar to those of the embodiment depicted inFIG. 1. In this embodiment, the initialization switch S4and the capacitor Cint in the charge calculation circuit26are shunt to each other between the output port of the transconductance amplifier20and the ground GND. Therefore, when the switch S4is turned on prior to sensing the capacitance Cm, the voltage Vo of the capacitor Cint is initialized to the ground voltage GND.

FIG. 3is a timing diagram for the circuits depicted inFIGS. 1 and 2. The switches S1and S2are controlled by two non-overlapping clocks. In the initial phase P0, the switches S2, S3and S4are turned on to set the voltage V1of the electrode10to the supply voltage VDD, and the voltage V2of the electrode12to the reference voltage VREF, and initialize the voltage Vo of the capacitor Cint either to the reference voltage VREF as shown inFIG. 1or to the ground voltage GND as shown inFIG. 2. In the phase P1that follows, the switch S1is turned on and thus pulls down the voltage V1of the electrode10to the ground voltage GND, resulting in the voltage V2of the electrode12decreasing along with the voltage V1, causing the capacitor Cm undergoing a charge amount variation
Q=(VDD−GND)×Cm.[Eq-1]
As soon as the transconductance amplifier mirror circuit16detects the decrease in the voltage V2, the transconductance amplifier18supplies charges to the capacitor Cm to sustain the voltage V2at the reference voltage VREF, and responsive thereto, the transconductance amplifier20also supplies a proportional amount of charges to the capacitor Cint. If the transconductance Gms of the transconductance amplifier18is equal to the transconductance Gmi of the transconductance amplifier20, the amount of charges Q supplied from the transconductance amplifier20to the capacitor Cint will also be equal to (VDD−GND)×Cm. The phase P1may be carried out by only once, or once more again after a phase P2, in which the switch S2is turned on to pull the voltage V1back to the supply voltage VDD, and the voltage V2will be still maintained at the reference voltage VREF, in order to change the voltage V2to charge the capacitor Cint for a second time. If this process is repeated for many times, the capacitor Cint will be charged for many times and undergo a stepwise variation of the voltage Vo. In the final phase P3, the switch S5is turned on for the measure unit24to measure the variation of the voltage Vo. From the well known equation Q=CV, it can be obtained that the amount of charges Q supplied from the transconductance amplifier20to the capacitor Cint is either (Vo−VREF)×Cint for the embodiment ofFIG. 1or (Vo−GND)×Cint for the embodiment ofFIG. 2. By substituting either Q=(Vo−VREF)×Cint or Q=(Vo−GND)×Cint into the equation Eq-1, the capacitance Cm can be calculated therefrom. In different embodiments with Gms:Gmi=m:n, each time the amount of charges Q supplied to the capacitor Cint will be (m/n)×(VDD−GND)×Cm.

FIG. 4is a circuit diagram of a third embodiment according to the present invention, which has the same circuit as that ofFIG. 1except that the capacitor Cint in the charge calculation circuit28is connected between the output port of the transconductance amplifier20and the voltage source VDD. Prior to sensing the capacitance Cm, the initialization switch S4is turned on to initialize the voltage Vo of the capacitor Cint to the reference voltage VREF. At the beginning of sensing the capacitance Cm, the voltage V1of the electrode10changes responsive to the switching of the switches S1and S2in the switching circuit14. When the voltage V1is pulled high, in order to sustain the voltage V2at the reference voltage VREF, the transconductance amplifier18will drain charges from the electrode12responsive to the difference between the voltage V2and the reference voltage VREF, and the transconductance amplifier20will also drain a proportional amount of charges from the charge calculation circuit28responsive to the variation of the voltage V2, thereby changing the amount of charges on the capacitor Cint. At the end of sensing the capacitance Cm, the switch S5is turned on, so that the voltage Vo of the capacitor Cint will be the sensed signal related to the capacitance Cm. The sensed signal Vo is then converted by the downstream measure unit24into a digital signal.

FIG. 5is a circuit diagram of a fourth embodiment according to the present invention, which has the same circuit ofFIG. 4except that the initialization switch S4is shunt to the capacitor Cint between the voltage source VDD and the output port of the transconductance amplifier20. Therefore, turn-on of the switch S4before sensing the capacitance Cm will initialize the voltage Vo of the capacitor Cint to the supply voltage VDD.

FIG. 6is a timing diagram for the circuits depicted inFIGS. 4 and 5. The switches S1and S2are controlled by two non-overlapping clocks. In the phase P0for initialization, the switches S1, S3and S4are turned on to set the voltage V1of the electrode10to the ground voltage GND, and the voltage V2of the electrode12to the reference voltage VREF, and initialize the voltage Vo of the capacitor Cint either to the reference voltage VREF as shown inFIG. 4or to the supply voltage VDD as shown inFIG. 5. In the phase P1that follows, the switch S2is turned on to pull high the voltage V1to the supply voltage VDD, causing the voltage V2of the electrode12to increase along with the voltage V1of the electrode10. As soon as the transconductance amplifier mirror circuit16detects the increase in the voltage V2, the transconductance amplifier18will drain charges from the electrode12to pull the voltage V2back to the reference voltage VREF, and thus the transconductance amplifier20will drain a proportional amount of charges from the capacitor Cint, where the proportionality is determined by the ratio of the transconductance values between the transconductance amplifiers18and20. The phase P1may be carried out by only once, or once more again after a phase P2, in which the switch S1is turned on to pull the voltage V1back to the ground voltage GND, and the voltage V2will be maintained at the reference voltage VREF, in order to change the voltage V2to discharge the capacitor Cint for a second time. If this process is repeated for many times, the voltage Vo will vary stepwise. In the final phase P3, the switch S5is turned on for the measure unit24to measure the variation of the voltage Vo. Once the amount of charges drained from the capacitor Cint is known, the capacitance Cm can be calculated accordingly.

FIG. 7is a circuit diagram of a fifth embodiment according to the present invention, which is a combination of the embodiments shown inFIGS. 2 and 5, andFIG. 8is a timing diagram for the circuit depicted inFIG. 7. In this embodiment, the switches S1and S2in the switching circuit14are controlled by two non-overlapping clocks to carry out the charging step ofFIG. 2and the discharging step ofFIG. 5in different phases, and then the charge amount variations are summed up to calculate the capacitance Cm. To start with, the switches S4in the charge calculation circuit32are turned on in the phase P0to initialize the capacitors Cint1and Cint2, so that the voltage at the positive terminal of the capacitor Cint1is set to the ground voltage GND, and the voltage at the positive terminal of the capacitor Cint2is set to the supply voltage VDD. Meanwhile, the switch S3is turned on to charge the electrode12so that the voltage V2equals to the reference voltage VREF. In the subsequent phase P1, the switches S2and S6are turned on so that the voltage V1of the electrode10is pulled high to the supply voltage VDD, causing the transconductance amplifier mirror circuit16to discharge the capacitor Cint2. In the phase P2that follows, the switches S1and S5are turned on so that the voltage V1of the electrode10is pulled down to the ground voltage GND, causing the transconductance amplifier mirror circuit16to charge the capacitor Cint1. Afterward, an analog adder34adds the terminal voltages of the capacitors Cint1and Cint2to produce a summed voltage Vsum, which is related to the capacitance Cm. In the final phase P3, the switch S7is turned on for the downstream measure unit24to convert the summed voltage Vsum into a digital signal to calculate the capacitance Cm.

FIG. 9is a circuit diagram of a sixth embodiment according to the present invention, for sensing the capacitance Cs of an electrode38with reference to ground GND, and as is well known, the ground GND can be regarded as a large grounded electrode40as shown inFIG. 9. In this embodiment, the circuit for sensing the capacitance Cs includes a switching circuit36and a charge calculation circuit42, in addition to the transconductance amplifier mirror circuit16and the measure unit24as depicted in the above embodiments. The switching circuit36includes a switch S1connected to the electrode38, and when the switch S1is on, the voltage V1of the electrode38will be pulled down to a lower voltage level, for example, the ground voltage GND as shown inFIG. 9. A sensing switch S3is connected between the electrode38and the transconductance amplifier mirror circuit16, and when the switch S3is on, the transconductance amplifier mirror circuit16may supply charges to the electrode38as illustrated by the embodiment ofFIG. 1, thereby sustaining the voltage V1at the reference voltage VREF, and responsive thereto, the transconductance amplifier mirror circuit16will supply a proportional amount of charges to the charge calculation circuit42. The charge calculation circuit42includes a capacitor Cint and an initialization switch S4shunt to each other between the output port of the transconductance amplifier20and the ground GND. The switch S4is turned on prior to sensing the capacitance Cs, to initialize the voltage Vo of the capacitor Cint to the ground voltage GND. A switch S5is connected between the charge calculation circuit42and the measure unit24, and the measure unit24is configured for converting the voltage Vo of the capacitor Cint into a digital signal. Due to connections of hardware circuitry or wire routing on a PCB, there may be a parasitic capacitance Cp1on the electrodes38that is not possessed by the electrode38itself, and the parasitic capacitance Cp1may result in offset charges to hinder the sensing of the capacitance Cs. However, as the offset value caused by the parasitic capacitance Cp1during the sensing of the capacitance Cs is a fixed value in this circuit, the measure unit24may deduct the offset value to minimize the influence of the parasitic capacitance Cp1imparted on the sensitivity.

FIG. 10is a timing diagram for the circuit depicted inFIG. 9. In the initial phase P0, the switch S4is turned on to initialize the voltage Vo of the capacitor Cint to the ground voltage GND. In the phase P1that follows, the switch S1is turned on to remove charges from the capacitor Cs, thereby pulling down the voltage V1to the ground voltage GND. In the subsequent phase P2, the switch S1is turned off and the switch S3is turned on, so that the transconductance amplifier mirror circuit16will identify the voltage V1is not equal to the reference voltage VREF, which causes the transconductance amplifier18to supply charges to the capacitor Cs, and thereby the transconductance amplifier20to supply a proportional amount of charges to the capacitor Cint. Charging the capacitor Cs from the ground voltage GND to the reference voltage VREF results in a charge amount variation
Q=(VREF−GND)×Cs.   [Eq-2]
If the transconductance amplifiers18and20have a same transconductance, the amount of charges supplied to the capacitor Cint will be equal to the amount of charges Q calculated by the equation Eq-2. The phases P1and P2may be carried out by only once or repeated for many times. In the final phase P3, the switch S5is turned on, and the measure unit24measures the variation of the voltage Vo to measure the amount of charges supplied from the transconductance amplifier mirror circuit16to the capacitor Cint, and subtracts the offset charges Qoff=(VREF−GND)×Cp1caused by the parasitic capacitance Cp1from the measured amount of charges to calculate the capacitance Cs.

FIG. 11is a circuit diagram of a seventh embodiment according to the present invention, which is similar to the embodiment ofFIG. 9. A switching circuit44includes the switch S2connected to the electrode38, controlled to switch the voltage V1of the electrode38to a higher voltage level, for example, the supply voltage VDD as shown inFIG. 11. The sensing switch S3is connected between the electrode38and the transconductance amplifier mirror circuit16, and when the switch S3is on, the transconductance amplifier mirror circuit16may drain charges from the electrode38as illustrated by the embodiment ofFIG. 4to sustain the voltage V1at the reference voltage VREF, and responsive thereto, the transconductance amplifier mirror circuit16will drain a proportional amount of charges from a charge calculation circuit46. The charge calculation circuit46includes the capacitor Cint and the switch S4shunt to each other between the output port of the transconductance amplifier20and the voltage source VDD. The initialization switch S4will be turned on before sensing the capacitance Cs, to initialize the voltage Vo of the capacitor Cint to the supply voltage VDD. The switch S5is connected between the charge calculation circuit46and the measure unit24, and the measure unit24is configured for converting the voltage Vo of the capacitor Cint into a digital signal and deducting the offset value caused by the parasitic capacitance Cp1.

FIG. 12is a timing diagram for the circuit depicted inFIG. 11. In the starting phase P0, the switch S4is turned on to initialize the voltage Vo of the capacitor Cint to the supply voltage VDD. In the phase P1that follows, the switch S2is turned on to pull high the voltage V1of the capacitor Cs to the supply voltage VDD. Then, in the phase P2, the switch S2is turned off and the switch S3is turned on, so that the transconductance amplifier mirror circuit16will identify the voltage V1is not equal to the reference voltage VREF, which will cause the transconductance amplifier18to drain charges from the capacitor Cs, and thereby the transconductance amplifier20to drain a proportional amount of charges from the capacitor Cint. Discharging the capacitor Cs from the supply voltage VDD to the reference voltage VREF results in a charge amount variation
Q=(VREF−VDD)×Cs.   [Eq-3]
If the transconductance amplifiers18and20have a same transconductance, the amount of charges that flow out from the capacitor Cint will be equal to the amount of charges Q calculated by the equation Eq-3. The phases P1and P2may be carried out by only once or repeated for many times. In the final phase P3, the switch S5is turned on, and the downstream measure unit24measures the variation of the voltage Vo to measure the amount of charges drained from the capacitor Cint by the transconductance amplifier mirror circuit16, and deducts the offset charges Qoff=(VREF−VDD)×Cp1caused by the parasitic capacitance Cp1to calculate the capacitance Cs.

FIG. 13is a circuit diagram of an eighth embodiment according to the present invention, which is a combination of the embodiments depicted inFIGS. 9 and 11, andFIG. 14is a timing diagram for the circuit depicted inFIG. 13. This embodiment controls the switches S1-S3and S5-S6to carry out the charging step ofFIG. 9and the discharging step ofFIG. 11in different phases, and sums up the charge amount variations to calculate the capacitance Cs. In the starting phase P0, the switches S4in the charge calculation circuit50are turned on to initialize the capacitors Cint1and Cint2, so that the voltage at the positive terminal of the capacitor Cint1is set to the ground voltage GND, and the voltage at the positive terminal of the capacitor Cint2is set to the supply voltage VDD. In the following phase P1, the switch S1is turned on to pull down the voltage V1of the capacitor Cs to the ground voltage GND. In the subsequent phase P2, the switches S3and S5are turned on so that the transconductance amplifier mirror circuit16will charge the capacitors Cs and Cint1simultaneously. Then, the switch S2is turned on in the phase P3to pull high the voltage V1of the capacitor Cs to the supply voltage VDD. In the phase P4that follows, the switches S3and S6are turned on so that the transconductance amplifier mirror circuit16will discharge the capacitors Cs and Cint2simultaneously. Afterward, an analog adder52sums up the terminal voltages of the capacitors Cint1and Cint2to produce a summed voltage Vsum. In the final phase. P5, the switch S7is turned on for the downstream measure unit24to measure the summed voltage Vsum to calculate the capacitance Cs.

In the foregoing embodiments, the transconductance amplifier mirror circuit16is implemented by two independent transconductance amplifiers18and20in a common input configuration. However, in order to prevent two independent transconductance amplifiers from being affected by offset voltage effect caused by the manufacturing process thereof, it is feasible to implement the transconductance amplifier mirror circuit16by sharing a common input stage. For example, as shown inFIG. 15, a transconductance amplifier mirror circuit16includes a comparator54as its input stage to compare the voltage V2of the electrode12(or the voltage V1of the electrode38) with the reference voltage VREF to generate an error signal to control two PMOS transistors having a size ratio of m:n. The comparator54and the size-m PMOS transistor establish a transconductance amplifier having a transconductance Gms, and the comparator54and the size-n PMOS transistor establish a transconductance amplifier having a transconductance Gmi. The transconductance amplifier mirror circuit16ofFIG. 15is applicable to the embodiments that are only required to charge the capacitor Cint, such as those depicted inFIGS. 1,2, and9. In another embodiment as shown inFIG. 16, a transconductance amplifier mirror circuit16includes a comparator54to generate an error signal to control two NMOS transistors having a size ratio of m:n, in which the comparator54and the size-m NMOS transistor establish a transconductance amplifier having a transconductance Gms, and the comparator54and the size-n NMOS transistor establish a transconductance amplifier having a transconductance Gmi. This transconductance amplifier mirror circuit16is suitable for the embodiments that are only required to discharge the capacitor Cint, such as those depicted inFIGS. 4,5, and11.FIG. 17is a circuit diagram of a balanced type transconductance amplifier mirror circuit incorporating the PMOS transistors ofFIG. 15and the NMOS transistors ofFIG. 16, in which a switch SP controls to operate with the PMOS transistors, and a switch SN controls to operate with the NMOS transistors. Alternatively, as shown inFIG. 18, two comparators56and58are used for controlling the charging process of the PMOS transistors and the discharging process of the NMOS transistors, respectively. In an embodiment, the comparators56and58ofFIG. 18have different reference voltages VREF in order to increase the voltage variation during the charging or discharging process and thereby increase the amount of charges to be calculated and hence the sensitivity. The embodiments ofFIGS. 17 and 18are applicable to the embodiments that are required to charge and discharge the capacitor Cint, such as those depicted inFIGS. 7 and 13. Each of the comparators54,56, and58may be implemented by an operational amplifier, an operational transconductance amplifier, or an error amplifier. The control unit60shown inFIGS. 15-18is needed only when the capacitance Cm is measured, as in the embodiments ofFIGS. 1,2,4,5and7, for the purpose of keeping the voltage V2of the electrode12at the reference voltage VREF before the switches in the switching circuit14are switched, so that not only is the voltage V2prevented from being offset and hence compromising the accuracy of the sensing result while the electrode12is charged or discharged, but also circuit stability in a noisy operation environment is ensured. As the aforesaid problems do not exist in the embodiments ofFIGS. 9,11, and13where it is the capacitance Cs to be sensed, the control unit60is not required in such embodiments.

A capacitive touch panel includes a plurality of electrodes and a protective layer for protecting the electrodes, in which each of the electrodes has a self capacitance with reference to ground, and the electric lines between the electrodes give rise to mutual capacitance. When an electrical conductor, e.g. a human finger, approaches a capacitive touch panel, the self capacitance of the electrode being approached increases, but the mutual capacitance between the electrode being approached and the neighboring electrodes decreases. The sensing methods illustrated by the embodiments ofFIGS. 1,2,4,5and7are suitable for sensing the mutual capacitance between the electrodes of a capacitive touch panel, and the sensing methods illustrated by the embodiments ofFIGS. 9,11and13are suitable for sensing the self capacitance of each electrode of a capacitive touch panel.FIG. 19is an embodiment for applications of the present invention to a capacitive touch panel, using the transconductance amplifier mirror circuit16to operate with a mixed mode sensing to the self capacitance and the mutual capacitance of the electrodes of the capacitive touch panel. InFIG. 19, each capacitance of the capacitor array Cm1, Cm2, Cm3, . . . , CmX represents a mutual capacitance established between two electrodes, and each of the capacitors Cm1, Cm2, Cm3, . . . , CmX has one of its electrodes connected to a common terminal A, and the other electrode individually connected to a multiplexer62having X input ports. Depending on the different sensing methods, the sensing circuits of the present invention may be identified as two separate blocks, a mutual mode sensor64and a self mode sensor66. The multiplexer62is connected to the mutual mode sensor64, and the common terminal A is connected to the self mode sensor66. Cp1, Cp2, Cp3, . . . , CpX denote the parasitic capacitances with reference to ground at the common terminal A on the capacitors Cm1, Cm2, Cm3, . . . , CmX, respectively. In the PCB routing, the capacitance of the common terminal A with reference to ground is established by the capacitances Cp1, Cp2, Cp3, . . . , CpX, which jointly form what appears to be a large area electrode. The self mode sensor66can sense the self capacitance of this large area electrode for proximity sensing. Then, by the switching of the multiplexer62, the mutual mode sensor64can sense each mutual capacitance Cm1, Cm2, Cm3, . . . , CmX for location sensing.