Electro-optical device and electronic apparatus

An electro-optical device comprises: a first data line extending in a first direction; a second data line extending in the first direction and arranged so as to be at least partially overlapped with the first data line; a first scanning line and a second scanning line extending in a second direction intersecting the first direction; a first transistor electrically connected to the first data line and electrically connected to the first scanning line; a first pixel electrode electrically connected to the first transistor; a second transistor electrically connected to the second data line and electrically connected to the second scanning line; and a second pixel electrode electrically connected to the second transistor.

BACKGROUND

1. Technical Field

The present invention relates to, for example, a technical field of an electro-optical device, such as a liquid crystal device, and an electronic apparatus including the electro-optical device, such as a liquid crystal projector.

2. Related Art

This type of electro-optical device has an active matrix driving configuration by including pixel electrodes and scanning lines, data lines and a pixel switching Thin Film Transistor (TFT) for selectively driving the pixel electrodes on a substrate. In the active matrix driving, scanning signals are supplied from the scanning lines so as to control the operations of the pixel switching TFTs, and image signals are supplied to the data lines at timings when the TFTs are turned on and driven so as to realize an image display.

For example, JP-A-2005-156574 discloses technology for improving the resolution of a displayed image by assembling two display panels in a liquid crystal display device. In addition, JP-A-7-311387 discloses technology for displaying a high-resolution image by supplying different image signals to respective pixels corresponding to odd-numbered rows and even-numbered rows of the scanning lines.

However, in the technology disclosed in JP-A-2005-156574, since the two display panels need to be assembled, the internal structure of the device becomes complicated or the size of the device is increased. In the technology disclosed in JP-A-7-311387, the scanning lines of the odd-numbered rows and the even-numbered rows are independently controlled, but, from the instantaneous viewpoint, only writing to pixels on a single scanning line is performed. Since the number of pixels and the scanning speed (in other words, the driving frequency) is increased in order to increase the resolution, the writing time of an image signal to each pixel may not be shortened.

SUMMARY

An advantage of some aspects of the invention is that it provides an electro-optical device capable of displaying a high-resolution image while ensuring the writing time of an image signal to each pixel, and an electronic apparatus including the electro-optical device.

According to an aspect of the invention, there is provided an electro-optical device including, on a substrate, lower layer side data lines extending in a first direction; upper layer side data lines extending on an upper layer side of the lower layer side data lines in the first direction and arranged so as to be at least partially superposed on the lower layer side data lines in plan view on the substrate; first and second scanning lines extending in a second direction intersecting the first direction; first transistors provided in correspondence with intersections of the lower side data lines and the first scanning lines, and each including a first semiconductor layer having a first source region electrically connected to each of the lower layer side data lines, a first channel region, and a first drain region, and a first gate electrode arranged so as to face the first channel region and electrically connected to each of the first scanning lines; a first pixel electrode electrically connected to the first drain region; second transistors provided in correspondence with intersections of the upper layer side data lines and the second scanning lines, and each including a second semiconductor layer having a second source region electrically connected to each of the upper layer side data lines, a second channel region, and a second drain region, and a second gate electrode arranged so as to face the second channel region and electrically connected to each of the second scanning lines; and a second pixel electrode electrically connected to the second drain region.

In the electro-optical device of the invention, for example, wirings such as scanning lines and data lines or electronic elements such as pixel switching transistors are laminated on the substrate as necessary so as to be insulated from each other with an insulating film interposed therebetween such that circuits for driving pixel electrodes are configured and image electrodes are arranged on an upper layer side thereof. At the time of the operation of the electro-optical device, for example, the switching operations of the pixel switching TFTs electrically connected to the pixel electrodes are controlled through the scanning lines and image signals are supplied through the data lines such that voltages according to the image signals are applied to the pixel electrodes through the TFT. Accordingly, it is possible to realize an image display in a display region (also called “image display region”) in which the plurality of pixel electrodes are arranged. In addition, the display region may be called “pixel region” or “pixel array region”.

In the invention, in particular, the data lines for supplying the image signals to the pixels include the lower layer side data lines and the upper layer side data lines. Here, both the lower layer side data lines and the upper layer side data lines extend in the first direction, and the upper layer side data lines are arranged so as to be at least partially superposed on the lower layer side data lines in plan view on the substrate. Such data lines may be completely superposed on each other or may be slightly deviated from each other. Alternatively, the contour of one data line may be at least partially larger or smaller than the contour of the other data line. Since the conductive layer of the data line or the like is generally formed of a non-transparent material such as aluminum, a non-opening region in which display light is not transmitted or reflected may be partially configured in most cases. In the invention, by arranging the lower layer side data lines and the upper layer side data lines so as to be superposed on each other, it is possible to reduce a ratio of the non-opening region occupied in the image display region so as to improve an aperture ratio (that is, a ratio of an opening region occupied in the image display region (a ratio of a region, in which display light can be transmitted, occupied in the image display region)). As a result, it is possible to display a bright sharp image.

The first transistor of the invention is arranged on the intersection of the lower layer side data lines and the first scanning line and includes the first semiconductor layer and the first gate electrode. The first semiconductor layer includes the first source region, the first channel region and the first drain region, and the first gate electrode is arranged so as to face the first channel region. The first transistor may have a double gate structure.

In the invention, in particular, the first source region is electrically connected to the lower layer side data lines. Accordingly, the image signal applied to the lower layer side data lines is supplied to the first transistor. The upper layer side data lines are not electrically connected to the first transistor.

The first scanning line is electrically connected to the first gate electrode and ON/OFF of the first transistor can be adequately switched and controlled according to the supply timing of the scanning signal. In detail, the first transistor is turned on and driven at the timing when the scanning signal of a high level is supplied, and the image signal applied from the lower layer side data lines to the first source region is output from the first drain region.

The first drain region is electrically connected to the first pixel electrode. The image signal output from the first drain region is applied to the first pixel electrode by turning on and driving the first transistor at the timing when the scanning signal is supplied to the first gate electrode.

The second transistor of the invention is arranged on the intersection of the upper layer side data lines and the second scanning line and includes the second semiconductor layer and the second gate electrode. The second semiconductor layer includes the second source region, the second channel region and the second drain region, and the second gate electrode is arranged so as to face the second channel region. The second transistor may have a double gate structure.

In the invention, in particular, the second source region is electrically connected to the upper layer side data lines. Accordingly, the image signal applied to the upper layer side data lines is supplied to the second transistor. The lower layer side data lines are not electrically connected to the second transistor.

The second scanning line is electrically connected to the second gate electrode and ON/OFF of the second transistor can be adequately switched and controlled according to the supply timing of the scanning signal. In detail, the second transistor is turned on and driven at the timing when the scanning signal of a high level is supplied, and the image signal applied from the upper layer side to the second source region is output from the second drain region.

The second drain region is electrically connected to the second pixel electrode. The image signal output from the second drain region is applied to the second pixel electrode by turning on and driving the second transistor at the timing when the scanning signal is supplied to the second gate electrode.

Although the first gate electrode and the second gate electrode are electrically connected to the first scanning line and the second scanning line, respectively, in particular, if the first gate electrode and the second gate electrode are electrically connected to one first scanning line and second scanning line, respectively, the ON/OFF of the plurality of first transistors and second transistors arranged in the image display region may be simultaneously switched. In this case, it is possible to simultaneously write different image signals to the pixels configuring one pixel array.

By arranging the first and second transistors in which both the first and second scanning lines extending in the second direction are electrically connected to the respective gate electrodes, the plurality of pixels is configured in the image display region. The image signals are supplied to a series of pixels having the above configuration through the two data lines (that is, the upper side and lower side data lines).

As described above, since the lower layer side data lines and the upper layer side data lines are electrically connected to the first source region and the second source region, it is possible to simultaneously supply different image signals. Accordingly, the pixels corresponding to the first transistor and the second transistor can simultaneously display images based on different image signals. As a result, even when the number of pixels in the image display region is increased, since different image signals can be simultaneously supplied to the plurality of pixels the writing time per individual pixel is not shortened or it is possible to reduce the amount shortened to a minimum. As a result, it is possible to realize an electro-optical device capable of displaying an image with high resolution.

In the electro-optical device of the invention, the first and second scanning lines may be adjacent to each other.

The second transistor is arranged in correspondence with the second pixel adjacent to the first pixel, which is the pixel corresponding to the first transistor, in the first direction or the second direction in plan view on the substrate. As a result, since different image signals can be simultaneously supplied to the plurality of adjacent pixels, it is possible to improve the resolution of the display image.

The electro-optical device may further include a shield layer arranged between the plurality of lower layer side data lines and the plurality of upper layer side data lines and held at a predetermined potential.

Since the lower layer side data lines and the upper layer side data lines are independently formed, different image signals are basically applied. Accordingly, if the shield layer is not present, coupling is generated by an electric field generated based on a potential difference between the lower layer side data lines and the upper layer side data lines, and the image signals applied to the lower layer side data lines and the upper layer side data lines are mutually influenced and disturbed. In this aspect, by forming the shield layer held at the predetermined potential between the lower layer side data lines and the upper layer side data lines, it is possible to block the electric field generated between the lower layer side data lines and the upper layer side data lines and to efficiently suppress coupling. In addition, the predetermined potential may be a fixed potential such as a ground potential or a potential of a constant potential power source or a rectangular-wave potential such as a potential of a counter electrode. As a result, it is possible to suppress coupling between the lower layer side data lines and the upper layer side data lines and to realize an electro-optical device capable of displaying a high-quality image.

The shield layer may be formed at least partially wider than the plurality of lower layer side data lines and the plurality of upper layer side data lines in plan view on the substrate.

In this aspect, by forming the shield layer with a large width, it is possible to more efficiently prevent coupling between the lower layer side data lines and the upper layer side data lines. The electric field generated between the lower layer side data lines and the upper layer side data lines is prone to generate a horizontal component, in particular, in the vicinity of the ends of the lower layer side data lines and the upper layer side data lines. Since such a horizontal electric field component comes around the outside of the shield layer if the shield layer is not formed with a sufficiently large width, it is difficult to sufficiently suppress coupling between the lower layer side data lines and the upper layer side data lines. In this aspect, the shield layer is formed wider than the lower layer side data line and the upper layer side data line such that an electric field coming around the outside of the shield layer is sufficiently reduced. As a result, it is possible to suppress coupling between the lower layer side data lines and the upper layer side data lines with more certainty and to realize a higher quality of the display image.

If the effect of the shield layer can be sufficiently obtained, the shield layer may be formed with a small width. In this case, since the opening region of the pixel is not narrowed by the shield layer, it is possible to improve a degree of freedom in design.

The electro-optical device may further include conductive layers arranged on an upper layer side of the lower layer side data lines, and each of the conductive layers may be electrically connected to the first source region through a first contact hole and may be electrically connected to each of the lower layer side data lines through a second contact hole such that the first source region is electrically connected to each of the lower layer side data lines.

In this aspect, when the first source region is electrically connected to the lower layer side data lines, the conductive layer formed on the upper layer side of the lower layer side data lines is interposed. At this time, the conductive layer and the first source region are electrically connected through the first contact hole and the conductive layer and the lower layer side data lines are electrically connected through the second contact hole.

Here, since the upper layer side data lines are formed on the upper layer side of the lower layer side data lines, the distance between the upper layer side data lines and the second source region is prone to be greater than the distance between the lower layer side data lines and the first source region. That is, the electric resistance value between the upper layer side data lines and the second source region is prone to be longer than the electric resistance value between the lower layer side data lines and the first source region. If the electric resistance values of the path for applying the image signals are different, a difference in supply timing or amplitude of the image signal between the first transistor and the second transistor occurs.

In this aspect, by electrically connecting the first source region and the lower layer side data lines through the conductive layer (by intentionally setting the distance between the first source region and the lower layer side data lines to be large), the electric resistance value between the first source region and the lower layer side data lines can be approximated to the electric resistance value between the second source region and the upper layer side data lines. As a result, it is possible to reduce the difference in supply timing or amplitude of the image signal between the first transistor and the second transistor and to make the display characteristics of the image of the first pixel and the second pixel uniform.

In the aspect in which the above-described relay layer is included, the first contact hole may include a plurality of contact holes, and the plurality of contact holes may be at least partially superposed on each other in plan view on the substrate.

In this aspect, the first contact hole formed when the lower layer side data lines are electrically connected to the first source region includes the plurality of contact holes and the plurality of contact holes is arranged so as to be at least partially superposed on each other. Here, the contact hole is buried by a conductive material, but, in most cases, the conductive material is, for example, a non-transparent metal such as aluminum. In this case, since the contact hole filled with the non-transparent material does not transmit light, a non-opening region in which display light is not transmitted may be partially configured in the image display region. Accordingly, if the plurality of contact holes is formed so as not to be superposed on each other, the area of the non-opening area is increased and thus an aperture ratio of the image display region is lowered. In this case, by arranging the plurality of formed contact holes to be superposed on each other, it is possible to markedly reduce the area of the non-opening region and to improve the aperture ratio of the image display region. As a result, it is possible to realize an electro-optical device capable of displaying a bright sharp image.

In the electro-optical device of the invention, each of the upper layer side data lines and the second source region may be electrically connected through a plurality of contact holes, and the plurality of contact holes may be at least partially superposed on each other in plan view on the substrate.

In this aspect, the plurality of contact holes formed when the upper layer side data lines are electrically connected to the second source region is arranged so as to be at least partially superposed on each other. By arranging the plurality of contact holes as described above, similarly to the above-described aspect, it is possible to markedly reduce the area of the non-opening region and to improve the aperture ratio of the image display region. As a result, it is possible to realize an electro-optical device capable of displaying a bright sharp image.

Although the upper layer side data lines and the second source region may be connected through a single contact hole, practically, it is difficult to secure good conductivity by the single contact hole when another component needs to be formed between the upper layer side data line and the second source region or when the film thickness of the insulating layer formed between the layers is thick. Accordingly, in most cases, the plurality of contact holes needs to be formed.

In the electro-optical device of the invention, the first pixel electrode and the first drain region, and the second pixel electrode and the second drain region may be electrically connected through a plurality of contact holes, and the plurality of contact holes may be arranged so as to be at least partially superposed on each other in plan view on the substrate.

In this aspect, the plurality of contact holes formed when the first pixel electrode and the first drain region, and the second pixel electrode and the second drain region are electrically connected is arranged so as to be at least partially superposed on each other. By arranging the plurality of contact holes as described above, similarly to the above-described aspect, it is possible to markedly reduce the area of the non-opening region and to improve the aperture ratio of the image display region. As a result, it is possible to realize an electro-optical device capable of displaying a bright sharp image.

The electro-optical device of the invention may further include a first capacitive electrode formed on a lower layer side of the first pixel electrode with a first capacitive insulating film interposed therebetween and a second capacitive electrode formed on a lower layer side of the second pixel electrode with a second capacitive insulating film interposed therebetween.

In this aspect, since each of the first transistor and the second transistor has the storage capacitor, it is possible to improve the storage characteristics (that is, characteristics in which the pixel electrodes store the supplied image signals). Although the storage capacitor is formed by interposing the capacitive insulating film between two capacitive electrodes, in this aspect, in particular, one capacitive electrode is configured to become the pixel electrode. That is, by interposing the first capacitive insulating film and the second capacitive insulating film between the first capacitive electrode and the second capacitive electrode, the first pixel electrode and the second pixel electrode form storage capacitors. By using the pixel electrode as one electrode forming the storage capacitor, it is possible to suppress complication of the lamination structure on the substrate and to provide the storage capacitor with an efficient layout.

In this case, the first capacitive insulating film and the second capacitive insulating film may be simultaneously formed from the same insulating film and the first capacitive electrode and the second capacitive electrode may be simultaneously formed from the same conductive film.

According to this aspect, since the capacitive insulating films and the capacitive electrodes among the components of the storage capacitors formed in the first transistor and the second transistor are respectively formed from the same films, it is possible to simplify the lamination structure on the substrate. As a result, it is possible to easily realize simplification or high accuracy of the process of manufacturing the electro-optical device.

According to another aspect of the invention, there is provided an electronic apparatus including the above-described electro-optical device (including the various aspects).

According to the electronic apparatus of the invention, since the above-described electro-optical device of the invention is included, it is possible to realize various electronic apparatuses capable of performing a high-quality image display, such as a projection type display device, a television set, a cellular phone, an electronic organizer, a word processor, a viewfinder-type or direct-view monitor type video tape recorder, a workstation, a videophone, a POS terminal, a touch-panel-equipped device. As the electronic apparatus of the invention, for example, it is possible to realize an electrophoretic device such as electronic paper, an electronic emission device (Field Emission Display and conduction Electron-Emitter Display), and a display device using the electrophoretic device and the electronic emission device.

The operation and the other advantages of the invention will be apparent from the following modes.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, embodiments of the invention will be described with reference to the drawings. In the following embodiments, for example, a TFT active matrix driving type liquid crystal device, in which a driving circuit is built, will be described as an example of an electro-optical device of the invention.

Liquid Crystal Device

First Embodiment

First, the overall configuration of a liquid crystal device according to the present embodiment will be described with reference toFIGS. 1 and 2.

FIG. 1is a schematic plan view showing components formed on a TFT array substrate10and the configuration of the liquid crystal device when viewed from the side of a counter substrate20andFIG. 2is a cross-sectional view taken along line II-II ofFIG. 1.

InFIGS. 1 and 2, the liquid crystal device according to the present embodiment includes the TFT array substrate10and the counter substrate20which face each other. The TFT array substrate10is, for example, a transparent substrate such as a quartz substrate or a glass substrate. The counter substrate20is also, for example, a substrate formed of the same material as the TFT array substrate10. A liquid crystal layer50is sealed between the TFT array substrate10and the counter substrate20, and the TFT array substrate10and the counter substrate20are adhered by a sealing material52provided on the circumference of an image display region10ain which an electro-optical operation is performed.

The sealing material52is used to adhere both substrates, is formed of ultraviolet curable resin or thermoset resin, is applied on the TFT array substrate10in a manufacturing process and is cured by ultraviolet ray irradiation, heating, or the like. In addition, for example, in the sealing material52, gap materials56for maintaining a gap between the TFT array substrate10and the counter substrate20(a gap between the substrates), such as glass fiber or glass beads, are dispersed.

On the inside of the sealing material52, in parallel to the sealing material, a light-shielding frame light-shielding film53defining a frame region of the image display region10ais provided on the side of the counter substrate20. A portion or the whole of the frame light-shielding film53may be provided on the side of the TFT array substrate10as a built-in light-shielding film.

A demultiplexer7, scanning line driving circuits104, an external circuit connection terminal102and the like are formed on the circumference of the image display region10aon the TFT array substrate10.

On the inside of the sealing material52on the TFT array substrate10in plan view, the demultiplexer7is placed along one side of the image display region10aalong one side of the TFT array substrate10so as to cover the frame light-shielding film53.

The scanning line driving circuits104are provided along two sides adjacent to one side of the TFT array substrate10so as to cover the frame light-shielding film53. In order to electrically connect the two scanning line driving circuits104provided on both sides of the image display region10a, a plurality of wirings105is provided along the remaining side of the TFT array substrate10so as to cover the frame light-shielding film53.

Vertical conductor terminals106are placed on the TFT array substrate10in regions facing four corners of the counter substrate20in plan view, and vertical conductor materials are electrically connected to the terminals106between the TFT array substrate10and the counter substrate20in correspondence with the vertical conductor terminals106.

InFIG. 2, a lamination structure including the pixel switching TFTs or the wirings such as the scanning lines and the data lines are formed on the TFT array substrate10. In the image display region10a, pixel electrodes9are provided in a matrix on an upper layer side of the pixel switching TFTs or the wirings such as the scanning lines and the data lines. In the present embodiment, in particular, the pixel electrodes9are formed as transparent electrodes formed of an ITO film. An alignment film16is formed on the pixel electrodes9.

A light-shielding film23is formed on a surface of the counter substrate20opposed to the TFT array substrate10. The light-shielding film23is formed of, for example, a metal film, resin, or the like having a light-shielding property and is patterned in, for example, a lattice shape in the image display region10aon the counter substrate20. A counter electrode21formed of an ITO film is, for example, solidly formed on the light-shielding film23(on the lower side of the light-shielding film23inFIG. 2) so as to face the plurality of pixel electrodes9, and an alignment film22is formed on the counter electrode21(on the lower side of the counter electrode21inFIG. 2).

The liquid crystal layer50is formed of, for example, liquid crystal in which one type or various types of nematic liquid crystal is mixed, and is in a predetermined alignment state between a pair of alignment films (that is, the alignment films16and22). By applying voltages at the time of the driving of the liquid crystal device, a liquid crystal retention capacity is formed between the pixel electrodes9and the counter electrode21.

Although not shown herein, on the TFT array substrate10, a precharge circuit for supplying a precharge signal having a predetermined voltage level to the plurality of data lines prior to the image signals, an inspection circuit or the like for inspecting the quality, defect or the like of the liquid crystal device during manufacture or before shipment may be formed.

Next, the electrical configuration of the liquid crystal device according to the present embodiment will be described with reference toFIG. 3.FIG. 3is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device according to the present embodiment.

InFIG. 3, the electro-optical device100includes the demultiplexer7, the scanning line driving circuits104and driving signal lines171formed on the TFT array substrate10. An image signal supplying circuit500as an external circuit is electrically connected to an image signal terminal102vof external circuit connection terminals102on the TFT array substrate10.

Each of the scanning line driving circuits104has a shift register and supplies to a scanning signal Gi (i=1, . . . , m) to a scanning line11a. In detail, each of the scanning line driving circuits104selects m scanning lines11in predetermined order described below, sets the scanning signal to the selected scanning line11to a H level corresponding to a selection voltage, and sets the scanning signals to the other scanning lines to an L level corresponding to a non-selection voltage.

The image signal supplying circuit500is configured separately with the TFT array substrate10and is electrically connected to the TFT array substrate10through the image signal terminal102vat the time of a display operation. The image signal supplying circuit500outputs an image signal having a voltage according to the grayscale of the pixel electrode9to the pixel electrode9corresponding to the scanning line11selected by the scanning line driving circuit104and the data line6selected by the demultiplexer7.

In the image display region10a, the data lines6are formed so as to extend along a Y direction. Here, the data lines6include n (n is a natural number of 2 or more) upper layer side data lines6aand lower layer side data lines6b. The upper layer side data lines6aare placed on the TFT array substrate10in plan view so as to be superposed on the lower layer side data lines6b. In the following description, “data lines6” indicates both the upper layer side data line6aand the lower layer side data lines6b.

An image data signal Sij is supplied from the image signal supplying circuit500to the data lines6through the demultiplexer7. Here, the demultiplexer7includes a plurality of transistors77. Each of the transistors77includes an upper layer side transistor77acorresponding to the upper layer side data lines6aand a lower layer side transistor77bcorresponding to the lower layer side data lines6b.

The driving signal lines171are connected to the gate electrodes of the transistors77so as to drive the transistors77at timings based on driving signals DRV supplied from the driving signal lines171.

The gate electrodes of a pair of transistors77connected to a pair of data lines6(that is, the upper layer side data lines6aand the lower layer side data lines6b) superposed when viewed on the TFT array substrate10in plan view are electrically connected to one common driving signal line171. Accordingly, the pair of transistors is driven at the same timing.

Six driving signal lines171are connected to the gate electrodes of six pairs of transistors77, respectively. For example, the driving signals are sequentially supplied from the upper side of the6driving signal lines171so as to sequentially drive the6pairs of transistors77by pair.

The image data signals Sij respectively corresponding to the upper layer side data lines6aand the lower layer side data lines6bare supplied from the image signal supplying circuit500in synchronization with timings when the transistors77are driven. In detail, the image data signal Si1corresponding to the upper layer side data lines6aand the image data signal Si2corresponding to the lower layer sides data line6b, which are different from each other, are supplied from the image signal supplying circuit500to the pixels connected to the upper layer side data lines6aand the lower layer side data lines6b, respectively.

From the scanning line driving circuit104, m (m is a natural integer of 2 or more) scanning lines11extend along an X direction. Each of the scanning lines11is electrically connected to the gate electrodes of the TFTs30so as to the drive the TFTs30placed on the scanning lines11based on a supply timing of the scanning signal. The source regions of the TFTs30each having the gate electrode connected onto the odd-numbered scanning lines11are electrically connected to the upper layer data lines6a. The source regions of the TFTs30each having the gate electrode connected onto the even-numbered scanning lines11are electrically connected to the lower layer side data lines6b.

In the image display region10a, the pixels are arranged in a matrix in correspondence with intersections of the data lines6and the scanning lines11. One pixel includes the pixel electrode9(seeFIG. 2) forming a liquid crystal element with the counter electrode20and the liquid crystal50interposed therebetween, the pixel switching TFT30and a storage capacitor70.

The gate electrode of the TFT30is electrically connected to the scanning lines11such that the switching of the TFT30is controlled according to the scanning signal. When the TFT30is turned on and driven, the image data signal Sij supplied to the source region electrically connected to the data lines6is supplied from the drain region of the TFT30to the pixel electrode9.

One electrode configuring the storage capacitor70is electrically connected to a common potential line91. The common potential line91extends to a peripheral region so as to be connected to a connection terminal102c. The connection terminal102cis a portion of the external connection terminal102(seeFIG. 1). In addition, the connection terminal102cis held at an LCCOM voltage by a power supply circuit which is built in an external device connected to the external connection terminal102so as to output the LCCOM voltage.

Although, in the present embodiment, the image signal supplying circuit500is connected to the portion102vof the external connection terminal102as the external circuit so as to input the image data signal, the data signal supplying circuit for outputting the image data signal may be formed on the TFT array substrate10. That is, the image signal supplying circuit500may be assembled in the liquid crystal device as the data signal supplying circuit.

Now, various control signals input to or output from the inside of the liquid crystal device according to the present embodiment will be described in detail with reference toFIG. 4A to 4Cin addition toFIG. 3.FIGS. 4A to 4Care timing charts illustrating input/output timings of various control signals input to or output from the inside of the liquid crystal device according to the first embodiment of the invention.

First, the supply timing of the scanning signal Gm supplied from the scanning line driving circuit104to the pixels through the scanning lines11will be described with reference toFIG. 4A.

Among the m scanning lines11, the scanning signal Gm is supplied to two neighboring scanning lines11at the same timing. That is, the pixels placed on the two continuous scanning lines11are driven at the same time. In detail, the scanning signals G1and G2, G3and G4, . . . , Gm-1and Gm are applied from the scanning lines11in this order at predetermined timings in a pulsed manner.

Next, the timings when the driving signals DRV are supplied from the driving signal lines171to the transistors77of the demultiplexer7and the potential written to the pixels arranged in the image display region will be described with reference toFIGS. 4B and 4C.

While the scanning signals G1and G2are supplied to the scanning lines11(see a period1inFIGS. 4A to 4C), the driving signals DRV1, DRV2, . . . , DRV6are supplied to six driving signal lines171in this order.

As shown inFIG. 3, when the driving signal DRV1is supplied, the transistors77corresponding to the pixels100(11) and100(21) are driven such that the pixels100(11) and100(21) reach a writable state. Simultaneously, since the driving signal DRV1is supplied to the transistors77corresponding to the pixels belonging to another data line group, such as the pixel100(17) and100(27), these pixels reach a writable state.

Subsequently, when the driving signal DRV2is supplied, the transistors77corresponding to the pixels100(12) and100(22) are driven such that the pixels100(12) and100(22) reach a writable state. Simultaneously, since the driving signal DRV2is supplied to the transistors77corresponding to the pixels belonging to another data line group, such as the pixel100(18) and100(28), these pixels reach a writable state. The image data signal Sij supplied from the data line driving circuit is applied to the pixels in the writable state. By this operation, when the writing is finished with respect to all the pixels of the image display region10a, the above operation is repeated and a display image is updated in every field. The image data signal Sij written to the pixels is held until writing is performed in a next field.

Next, the lamination structure formed on the TFT array substrate10in the image display region10aof the liquid crystal device according to the present embodiment will be described in detail with reference toFIGS. 5 to 7.

FIG. 5is a schematic diagram perspectively showing a positional relationship between electrodes and wirings placed for performing an electro-optical operation in the image display region10aof the liquid crystal device according to the present invention.FIGS. 6 and 7are cross-sectional views taken along line VI-VI and VII-VII ofFIG. 5. InFIGS. 5 to 7, the scale of each layer or each member is differentiated from each other in order that each layer or each element has a size capable of being identified in the view. In order to facilitate the understanding of the shown contents, a portion of the structure shown inFIGS. 5 to 7is partially omitted.

In supplementary description,FIG. 6is a cross-sectional view showing a lamination structure of the pixels (that is, the pixels in which the TFT30is connected to the lower layer side data lines6b) corresponding to the odd-numbered scanning lines11of the m scanning lines11inFIG. 3.FIG. 7is a cross-sectional view showing a lamination structure of the pixels (that is, the pixels in which the TFT30is connected to the upper layer side data lines6a) corresponding to the even-numbered scanning lines11of the m scanning lines11inFIG. 3.

First, the lamination structure of the pixels corresponding to the odd-numbered scanning lines11of the m scanning lines11will be described with reference toFIGS. 5 and 6.

The scanning lines11are formed on the TFT array substrate10. Here, the scanning lines11are formed on the TFT array substrate10so as to extend in the X direction in plan view. The scanning lines11are formed of a light-shielding conductive material, for example, tungsten (W), titanium (Ti), titanium nitride (TiN) or the like and shield light incident from the rear side (that is, a lower side ofFIG. 5) of the TFT array substrate10so as to prevent the wirings, the elements or the like formed on the upper layer side of the scanning lines11from being exposed to light. In the present embodiment, in particular, in order to suppress generation of leaked current and deterioration in the retention characteristics of the TFTs due to exposure of the semiconductor layer of the TFT30to light, the scanning lines11are formed on the TFT array substrate10wider than a region, in which the TFT30is formed, in plan view. By widely forming the scanning lines11, the semiconductor layers of the TFTs may be mostly or completely shielded from returning light such as light emitted from another liquid crystal device and transmitted through a synthetic optical system in rear surface reflection of the TFT array substrate10, a double plate type projector, or the like. As a result, at the time of the operation of the liquid crystal device, generated light leak current is reduced and a contrast ratio of a display image is improved so as to realize a high-quality image display.

The TFT30is formed on the upper layer side of the scanning lines11with a first interlayer insulating film12interposed therebetween. The TFT30is arranged on the TFT array substrate10in every pixel so as to correspond to the intersection of the scanning lines11formed so as to extend in the X direction and the data lines6formed so as to extend in the Y direction in plan view.

The TFT30includes a semiconductor layer30aand a gate electrode30bformed on an upper layer side thereof with a gate insulating film13interposed therebetween. Here, the semiconductor layer30aincludes a source region30a1, a channel region30a2and a drain region30a3(seeFIG. 6). A Lightly Doped Drain (LDD) region is formed in an interface of the channel region30a2and the source region30a1or the channel region30a2and the drain region30a3.

The gate electrode30bis formed on the upper layer side of the semiconductor layer30aso as to face the channel region30a2with the gate insulating film13interposed therebetween. The gate electrode30bis electrically connected to the scanning lines11through a contact hole51formed in the interlayer insulating film12and the gate insulating film13(seeFIG. 5).

The source region30a1is electrically connected to the lower layer side data lines6bformed on the upper layer side of the source region30athrough a contact hole32formed in the gate insulating film13and the second interlayer insulating film14. The lower layer side data lines6bare formed of a light-shielding conductive material, for example, aluminum (Al), and shields light incident from the upper side (that is, an upper side ofFIG. 5) of the TFT array substrate10so as to prevent the wirings, the elements or the like formed on the lower layer side of the lower layer side data lines6bfrom being exposed to light. As a result, the TFT30may be mostly or completely shielded from returning light such as light emitted from another liquid crystal device and transmitted through a synthetic optical system in rear surface reflection of the TFT array substrate10, a double plate type projector, or the like. Thus, it is possible to realize a high-quality image display.

The drain region30a3is electrically connected to a first relay layer41through a contact hole35formed in the gate insulating film13and the second interlayer insulating film14. Here, the first relay layer41is formed on the same layer as the lower layer side data lines6b. The first relay layer41is formed of the same material as the lower layer side data lines6band is, for example, formed on the same layer as the lower layer side data lines6bsimultaneously with the lower layer side data lines by patterning a conductive layer solidly formed on the second interlayer insulating layer14.

A second relay layer42is formed on the upper layer side of the first relay layer7and is electrically connected to the first relay layer41through a contact hole36formed in a third interlayer insulating film15.

A third relay layer43is formed on the upper layer side of the second relay layer42and is electrically connected to the second relay layer42through a contact hole37formed in a fourth interlayer insulating film16.

The pixel electrode9is formed on the upper layer side of the third relay layer43and is electrically connected to the third relay layer43through a contact hole38formed in a fifth interlayer insulating film17and a sixth interlayer insulating film18. The pixel electrode9is electrically connected to the drain region30a3of the TFT30through the first relay layer41, the second relay layer42and the third relay layer43. As a result, the image signal is supplied to the pixel electrode9at a timing when the TFT30is turned on and driven.

A capacitive electrode71is formed on a lower layer side of the pixel electrode9with a capacitive insulating film72. That is, the capacitive insulating film72is interposed between the pixel electrode9and the capacitive electrode71so as to form the storage capacitor70.

In the present embodiment, in particular, both the pixel electrode9and the capacitive electrode71are formed of Indium Tin Oxide ITO). Since ITO is a transparent conductive material, the capacitive electrode can be widely formed in an opening region and the storage capacitor70having a large capacitive value can be formed.

FIG. 8is a schematic diagram showing the region in which the capacitive electrode71is placed on the TFT array substrate10together with the data lines6and the scanning lines11. InFIG. 8, for convenience of description, the data lines6and the scanning lines11formed on the lower layer side of the capacitive electrode71are perspectively shown, and the scale of each layer or each member is differentiated from each other in order that each layer or each member has a size capable of being identified in the view.

The data lines6and the scanning lines11extend in the Y direction and the X direction, respectively. The pixels are divided by the data lines6and the scanning lines11. The capacitive electrode71has an opening region5ain each pixel and the opening region5ais formed such that the contact hole38is positioned therein. Since the opening region5ais formed wider than the contact hole38, although the pixel electrode9and the third relay layer43are electrically connected through the contact hole38, the pixel electrode9and the third relay layer43can be safely connected with the capacitive electrode71without short-circuiting.

As described above, since the capacitive electrode71is formed of ITO which is the transparent conductive material, as shown inFIG. 8, the capacitive electrode can be formed over the wide range of the image display region. As a result, the storage capacitor70having the large capacitive value can be formed and the retention characteristics of the pixel can be improved.

In the present embodiment, since the data lines6are doubly formed, the lamination structure in the vicinity of the TFT array substrate10may become complicated. In this case, by forming the storage capacitor70on the pixel electrode side having a relatively simple lamination structure, it is possible to easily add the storage capacitor70. In particular, by using the pixel electrode as one electrode configuring the storage capacitor, it is possible to efficiently suppress the complication of the lamination structure.

A shield layer8is formed on the upper layer side of the lower layer side data lines6bwith the third interlayer insulating film15interposed therebetween. The shield layer8is formed so as to suppress or prevent the lower layer side data line6bfrom being coupled with the upper layer side data lines6aformed on the upper layer side of the shield layer8with the fourth interlayer insulating film16(that is, disturbance of the image signal applied by an electric field generated by an electric potential difference between the upper layer side data lines6aand the lower layer side data lines6b) interposed therebetween.

As shown inFIG. 5, the shield layer8is formed wider than the data lines6in a non-opening region excluding the intersection of the data lines6and the scanning line11. Since the electric field generated between the upper layer side data lines6aand the lower layer side data lines6bhas more or less a component of a surface direction parallel to the TFT array substrate10, a portion thereof comes around the end of the shield layer8. Even in this case, by forming the shield layer8so as to be sufficiently larger than the upper layer side data lines6aand the lower layer side data lines6b, it is possible to efficiently reduce the electric field coming around the end.

The upper layer side data lines6aare not electrically connected to the pixel corresponding to the odd-numbered scanning lines11of the m scanning lines11.

Subsequently, the lamination structure of the pixel corresponding to the even-numbered scanning lines11of the m scanning lines11will be described with reference toFIGS. 5 and 7. The description of the common wirings, the elements and the like as the lamination structure of the pixel corresponding to the odd-numbered scanning lines11of the m scanning lines11will be appropriately omitted and are denoted by the same reference numerals.

The source region30a1is electrically connected to a fourth relay layer44formed on the upper layer side of the source region30athrough a contact hole32formed in the gate insulating film13and the second interlayer insulating film14. The fourth relay layer44is electrically connected to a fifth relay layer45formed on the upper layer side of the third interlayer insulating film15through a contact hole33. The fifth relay layer45is electrically connected to the upper layer side data lines6aformed on the upper layer side of the fourth interlayer insulating film16through a contact hole34.

The upper layer side data lines6aare formed of a light-shielding conductive material, for example, aluminum (Al) or the like, similarly to the lower layer side data lines6b. The upper layer side data lines also shield light incident from the upper side (that is, an upper side ofFIG. 7) of the TFT array substrate10so as to prevent the wirings, the elements or the like formed on the lower layer side of the upper layer side data lines6afrom being exposed to light. As a result, the TFT30may be mostly or completely shielded from returning light such as light emitted from another liquid crystal device and transmitted through a synthetic optical system in rear surface reflection of the TFT array substrate10, a double plate type projector, or the like. Thus, it is possible to realize a high-quality image display. In the present embodiment, in particular, since the semiconductor layer30aof the TFT30can be doubly shielded from light in conjunction with the upper layer side data lines6a, it is possible to obtain an excellent light-shielding property.

Similarly toFIG. 6, the shield layer8is formed on the lower layer side of the upper layer side data lines6a. The shield layer8is formed so as to suppress or prevent the upper layer side data line6afrom being coupled with the lower layer side data lines6bformed on the lower layer side of the shield layer8with the third interlayer insulating film15(that is, disturbance of the image signal applied by an electric field generated by an electric potential difference between the upper layer side data lines6aand the lower layer side data lines6b) interposed therebetween.

The lower layer side data lines6bare not electrically connected to the pixel corresponding to the even-numbered scanning lines11of the m scanning lines11.

The other lamination structure of the pixel corresponding to the even-numbered scanning lines11of the m scanning lines11is equal to the lamination (seeFIG. 6) of the pixel corresponding to the odd-numbered scanning lines11of the m scanning lines11(seeFIGS. 5 and 6).

As described above, according to the electro-optical device according to the present embodiment, by doubly forming the data lines, it is possible to markedly improve writing efficiency to the pixel and to realize high quality of a display image.

Second Embodiment

Next, the structure of a liquid crystal device according to a second embodiment will be described with reference toFIG. 9. Since the liquid crystal device of the second embodiment has the schematic plan view, the cross-sectional view and the circuit diagram shown inFIGS. 1 to 4Cin common with the first embodiment, the description thereof will be omitted and the planar structure and the lamination structure on the TFT array substrate10will be mainly described.

FIG. 9is a cross-sectional view on the TFT array substrate corresponding toFIG. 6of the first embodiment, in the present embodiment. InFIG. 9, the scale of each layer or each member is differentiated from each other in order that each layer or each member has a size capable of being identified in the view. In order to facilitate the understanding of the shown contents, a portion of the structure shown inFIGS. 9 and 10is partially omitted.

The source region30a1is electrically connected to a sixth relay layer46formed on the upper layer side through a contact hole39formed in the gate insulating film13, the second interlayer insulating film14and the third interlayer insulating film15. The sixth relay layer46is electrically connected to the lower layer side data line6bformed on the lower layer side through a contact hole40formed in the third interlayer insulating layer. That is, the present embodiment is different from the above-described first embodiment in that the source region30a1is electrically connected to the lower layer side data line6bthrough the sixth relay layer46.

Since the upper layer side data lines6aare arranged at a position further from the source region30a1than the lower layer side data lines6b, if an electrical connection is performed through a single contact hole, an electric resistance value between the upper layer side data lines6aand the source region30a1is prone to be greater than an electric resistance value between the lower layer side data lines6band the source region30b. If a difference in electric resistance value is present, a difference in supply timing or amplitude of the image signal is generated depending on which of the data lines6is connected to the source region30a(that is, whether the data line connected to the source region30ais the upper layer side data lines6aor the lower layer side data lines6b).

In the liquid crystal device according to the present embodiment, by intentionally connecting the lower layer side data lines6barranged at a position close to the TFT30to the source region30a1through the sixth relay layer46, the electric resistance value between the lower layer side data lines6band the source region30a1is increased. As a result, the difference between the electric resistance value between the upper layer side data lines6athe source region30a1and the electric resistance value between the lower layer side data lines6band the source region30a1can be reduced or solved.

Third Embodiment

Next, the structure of a liquid crystal device according to a third embodiment will be described with reference toFIGS. 10 and 11.FIGS. 10 and 11are a cross-sectional view on the TFT array substrate corresponding toFIGS. 6 and 7of the first embodiment, in the present embodiment. Since the liquid crystal device of the third embodiment has the schematic plan view, the cross-sectional view and the circuit diagram shown inFIGS. 1 to 4Cin common with the first embodiment, the description thereof will be omitted and the lamination structure on the TFT array substrate10will be mainly described.

First, the lamination structure of the pixel corresponding to the odd-numbered scanning line11of the m scanning lines11will be described with reference toFIG. 10.

The source region30a1is electrically connected to a seventh relay layer19′ formed on the upper layer side through a contact hole39′ formed in the gate insulating film13and the second interlayer insulating film14. The seventh relay layer19′ is electrically connected to an eighth relay layer19″ formed on the upper layer side through a contact hole39″ formed in the third interlayer insulating layer15. In addition, the eighth relay layer19″ is electrically connected to the lower layer side data line6bformed on the lower layer side through a contact hole40formed in the third interlayer insulating film15. That is, the present embodiment is different from the above-described second embodiment in that the relay layer for electrically connecting the source region30a1to the lower layer side data line6bis divided into two steps.

Here, if the pixel electrode9and the drain region30a3are directly connected, since the film thickness of the insulating film (that is, the gate insulating film13, the second interlayer insulating film14and the third interlayer insulating film) present between both layers is large, it is difficult to realize good electrical connection. That is, since the pixel electrode9and the drain region30a3are formed on the separated layers, if they are directly connected through one deep contact hole, a defect is generated in the contact hole originally having good conductivity in the manufacturing process thereof and thus the conductivity of the contact hole deteriorates. Accordingly, as in the present embodiment, by providing two relay layers (that is, the seventh relay layer19′ and the eighth relay layer19″), it is possible to realize good electrical connection using the shallow contact holes (that is, the contact holes39′ and39″).

In the present embodiment, in particular, the contact holes39′ and39″ and the contact holes35and36are formed on the TFT array substrate10so as to be superposed on each other in plan view (that is, form a so-called stack contact structure). By arranging the position where the contact holes are formed as described above, it is possible to reduce the area of the non-opening region and to improve an aperture ratio of the image display region. As a result, it is possible to realize a liquid crystal device capable of displaying a bright sharp image.

Next, the lamination structure of the pixel corresponding to the even-numbered scanning line11of the m scanning lines11will be described with reference toFIG. 11.

In the lamination structure shown inFIG. 11, as compared with the lamination structure of the same portion of the first embodiment (seeFIG. 7), the contact holes32and33and the contact holes35and36are formed on the TFT array substrate10so as to be superposed on each other in plan view (that is, form a so-called stack contact structure). As a result, as described with reference toFIG. 10, it is possible to reduce the area of the non-opening region and to improve an aperture ratio of the image display region.

Electronic Apparatus

Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic apparatuses will be described.

FIG. 12is a plan view showing the configuration example of a projector. Hereinafter, a projector, which uses the present liquid crystal device as a light valve, will be described.

As shown inFIG. 12, a lamp unit1102including a white light source such as a halogen lamp and the like is provided inside the projector1100. A projected light emitted from the lamp unit1102is separated into three primary colors of R, G, and B by four mirrors1106and two dichroic mirrors1108disposed inside a light guide1104and the three primary colors are incident to the liquid crystal panels1110R,1110B, and1110G as the light valves corresponding to each of the primary colors.

The configuration of each of the three liquid crystal panels1110R,1110B, and1110G is equal to that of the above-described liquid crystal device, and the liquid crystal panels are driven by primary color signals of R, G, and B supplied from the image signal supply circuit. The light modulated by such liquid crystal panels is incident into a dichroic prism1112from three directions. In the dichroic prism1112, the light of R and B is refracted at an angle of 90 degrees and the light of G goes straight. Therefore, an image of each color is synthesized, whereby a color image is projected onto a screen or the like through a projector lens1114.

Here, when attention is focused on a display image by each of the liquid crystal panels1110R,1110B, and1110G, the display image by the liquid crystal panel1110G is needed to be horizontally mirror-inversed with respect to the display images by the liquid crystal panels1110R and1110B.

Further, since light corresponding to each of the primary colors R, G and B is incident to each of the liquid crystal panels1110R,1110B, and1110G by the dichroic mirrors1108, there is no need to provide a color filter.

In addition to the electronic apparatus described inFIG. 12, there are a mobile personal computer, a cellular phone, a liquid crystal television set, a viewfinder-type or direct-view monitor type video tape recorder, a car navigation system, a pager, an electronic organizer, an electronic calculator, a word processor, a workstation, a videophone, a POS terminal, a touch-panel-equipped device. In addition, the invention is applicable to various electronic apparatuses.

In addition, the invention may also be applied to a reflective liquid crystal device (LCOS), a plasma display panel (PDP), a field emission type display (FED, SED), an organic EL display, a digital micromirror device (DMD), an electrophoresis device, and the like, in addition to the liquid crystal device described in the above-mentioned embodiments.

The invention is not limited to the above-described embodiments and may be appropriately changed without departing from the scope of the invention as read from the claims and the overall specification and an electro-optical device having such changes and an electronic apparatus including the electro-optical device are included in the technical range of the invention.

The entire disclosure of Japanese Patent Application No. 2009-225301, filed Sep. 29, 2009 is expressly incorporated by reference herein.