Array substrate and display device

An array substrate includes gate lines, source lines, switching components, position detecting electrodes, a light blocking portion, and position detecting lines. The position detecting electrodes are disposed in a layer lower than the gate lines and the source lines to detect input positions at which the position input operation is performed with a position input body based on electrostatic capacitances between the position input body and the position detecting electrodes. The light blocking portion is disposed in a layer lower than channel regions of the switching components and opposite the channel regions with a lower insulating film between the light blocking portion and the channel regions. The position detecting lines are formed from sections of a conductive film from which the light blocking portion is formed and coupled to the position detecting electrodes.

TECHNICAL FIELD

The present invention relates to an array substrate and a display device.

BACKGROUND

A liquid crystal display device includes an active-matrix substrate, an opposed substrate, and a liquid crystal layer. The liquid crystal layer is between the active-matrix substrate and the opposed substrate. The liquid crystal display device includes a touch surface on an active-matrix substrate side. The active-matrix substrate includes a substrate, pixel electrodes, a common electrode, touch detecting electrodes, and signal lines on a liquid crystal layer side of the substrate. The touch detecting electrodes detect contact with the touch surface. The signal lines are coupled to the touch detecting electrodes, respectively. The pixel electrodes, the common electrode, and the touch detecting electrodes overlap one another when viewed in plan. The touch detecting electrodes are closer to the substrate than the pixel electrodes and a common electrode.

In the active-matrix substrate included in the display device including a touchscreen, the signal lines coupled to the touch detecting electrodes and a black matrix are formed from different films, that is, the display device including the touchscreen tends to have a larger number of films. The number of photomasks required for production of the active-matrix substrate increases and thus a production cost may increase.

SUMMARY

The technology described herein was made in view of the above circumstances. An object is to reduce the number of photomasks.

An array substrate according to the technology described herein includes gate lines, source lines, switching components, position detecting electrodes, a light blocking portion, and position detecting lines. The source lines cross the gate lines. The switching components include gate electrodes, channel regions, source regions, and drain regions. The gate electrodes are coupled to the gate lines. The channel regions are disposed in a layer lower than the gate electrodes and opposite the gate electrodes with a gate insulating film between the gate electrodes and the channel regions. The channel regions are formed from a semiconductor film. The source regions are coupled to the source lines and first ends of the channel regions. The drain regions are coupled to second ends of the channel regions. The position detecting electrodes are disposed in a layer lower than the gate lines and the source lines to detect input positions at which the position input operation is performed with a position input body based on electrostatic capacitances between the position input body and the position detecting electrodes. The light blocking portion is disposed in a layer lower than the channel regions and opposite the channel regions with a lower insulating film between the light blocking portion and the channel regions. The position detecting lines are formed from sections of a conductive film from which the light blocking portion is formed and coupled to the position detecting electrodes.

An array substrate according to the technology described herein includes gate lines, source lines, switching components, position detecting lines, and position detecting electrodes. The source lines cross the gate lines. The switching components include gate electrodes, channel regions, source regions, and drain regions. The gate electrodes are coupled to the gate lines. The channel regions are disposed in a layer lower than the gate electrodes and opposite the gate electrodes with a gate insulating film between the gate electrodes and the channel regions. The channel regions are formed from a semiconductor film. The source regions are coupled to the source lines and first ends of the channel regions. The drain regions are coupled to second ends of the channel regions. The position detecting electrodes are coupled to the position detecting lines to detect input positions at which position input operation is performed with a position input body based on electrostatic capacitances between the position input body and the position detecting electrodes. The position detecting electrodes are formed by reducing resistances of sections of a semiconductor film and in a layer lower than the gate lines and the source lines.

A display device according to the technology described herein includes the array substrate described above and an opposed substrate opposite the array substrate.

According to the technology described herein, the number of photomasks can be reduced.

DETAILED DESCRIPTION

First Embodiment

A first embodiment will be described in detail with reference toFIGS.1to15. In this section, a liquid crystal panel10(a display panel) will be described. In the drawings, X-axes, Y-axes, and Z-axes may be present. The axes in each drawing correspond to the respective axes in other drawings.

FIG.1is a plan view schematically illustrating the liquid crystal panel10. As illustrated inFIG.1, the liquid crystal panel10according to this embodiment has a vertically-long rectangular overall shape in a plan view. A short-side direction, a long-side direction, and a thickness direction of the liquid crystal panel10are along the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively. The liquid crystal panel10displays images using illumination light emitted by a backlight (a lighting device) on an opposite side from a display surface on which the images are displayed (a user side), that is, behind the liquid crystal panel10. The liquid crystal panel10includes a display area AA (a pixel area) on an inner side of a screen and a non-display area NAA (a frame area) having a frame shape to surround the display area AA on an outer side of the screen. InFIG.1, the display area AA is surrounded by a chain line.

As illustrated inFIG.1, the liquid crystal panel includes a pair of glass substrates11and12being substantially transparent and having light transmissivity. The substrates11and12include a CF substrate11(an opposed substrate) and an array substrate12(an active-matrix substrate, a component substrate). The array substrate12has a long dimension greater than a long dimension of the CF substrate11. The array substrate12includes an end portion at one of ends with respect to the long-side direction. The end portion is not opposite the CF substrate11. A driver13(a signal source) and a flexible circuit board14are mounted on the end portion. The driver13includes an LSI chip that includes an internal driver circuit. The driver13is mounted in a mounting area of the array substrate12using the chip-on-glass (COG) technology. The driver13process various signals transmitted by the flexible circuit board14. The flexible circuit board14includes multiple traces (not illustrated) formed on a substrate that is made of a synthetic resin material (such as a polyimide resin) having insulating properties and flexibility. The flexible circuit board14includes a first end and a second end coupled to the array substrate12and an external control circuit board (a signal source), respectively. Various signals output by the control circuit board are transmitted to the liquid crystal panel10via the flexible circuit board14.

The liquid crystal panel10according to this embodiment has a display function for displaying the images and a touchscreen function for detecting input positions at which a user performs position input operation based on the displayed images. The liquid crystal panel10includes a touchscreen pattern for performing the touchscreen function. The touchscreen pattern is integrally formed (using the in-cell technology). The touchscreen pattern uses so-called projected capacitive technology, that is, a self-capacitance method for detection. As illustrated inFIG.1, the touchscreen pattern includes multiple touch electrodes31(position detecting electrodes) arranged in a matrix within a plate surface of the liquid crystal panel10. The touch electrodes31are disposed in the display area AA of the liquid crystal panel10. The display area AA of the liquid crystal panel10is about equal to a touch area in which input positions are detectable (a position input area). The non-display area NAA is about equal to a non-touch area in which input positions are not detectable (a non-position input area). When the user moves a position input body closer to the surface of the liquid crystal panel10(the display surface) to perform position input operation based on a viewed image in the display area AA of the liquid crystal panel10, an electrostatic capacitance appears between the position input body and the touch electrode31. The position input body is an electric conductor such as a finger of the user and a stylus used by the user. The electrostatic capacitance at the touch electrode31adjacent to the position input body varies as the position input body approaches. The electrostatic capacitance at the touch electrode31defers from an electrostatic capacitance at the touch electrode31that is farther from the position input body. The input position is detectable based on the difference. Each touch electrode31has a rectangular shape when viewed in plan. Length of edges are some millimeters (e.g., about 2 mm to 6 mm). The touch electrode31is significantly larger than a pixel, which will be described later, when viewed in plan. The touch electrode31is disposed to straddle multiple pixels in the X-axis direction and the Y-axis direction. Dividing openings31A (dividing slits) are provided between the touch electrodes31adjacent to each other in the X-axis direction and between the touch electrodes31adjacent to each other in the Y-axis direction. The dividing openings31A includes first dividing openings31A1that extend in the X-axis direction and second dividing openings31A2that extend in the Y-axis direction. The dividing openings31A form a grid when viewed in plan.

FIG.2is a schematic cross-sectional view of the liquid crystal panel10. As illustrated inFIG.2, in the liquid crystal panel10, the CF substrate11is disposed on the rear side, that is, closer to the backlight and the array substrate is disposed on the front side, that is, closer to the display side on which the images are displayed (closer to the user). The front plat surface of the array substrate12is defined as an input surface12A on which position input operation is performed with the position input body such as the finger of the user and the stylus used by the user. Polarizing plates are bonded to outer surfaces of the CF substrate11and the array substrate12. Protective films may be bonded to outer surfaces of the polarizing plates. Namely, the position input body is less likely to directly touch the input surface12A of the array substrate12.

As illustrated inFIG.2, the liquid crystal panel10includes a liquid crystal layer15and a sealant16. The liquid crystal layer15is between the substrates11and12. The sealant16is between outer edge sections of the substrates11and12. The liquid crystal layer15includes liquid crystal molecules that are substances having optical characteristics that vary according to application of an electric field. The sealant16extend an entire periphery of the outer edge sections of the substrates11and12to surround and seal the liquid crystal layer15. The sealant16has a frame shape (a closed ring shape) when viewed in plan. A cell gap is provided between the substrates11and12. The cell gap is equal to a thickness of the liquid crystal layer15and maintained with the sealant16. The sealant16is disposed in the non-display area NAA. The CF substrate11and the array substrate12include various films that are laminated on inner surfaces of the glass substrates.

FIG.3is a plan view of the liquid crystal panel10illustrating arrangement of the pixels in the display area AA. As illustrated inFIG.3, TFTs20(switching components, thin film transistors) and pixel electrodes21connected to the TFTs20are arranged in a matrix on the array substrate12in the display area AA. Gate lines22(scan lines) and source lines23(data lines, signal lines) are disposed in a grid to surround the TFTs20and the pixel electrodes21. The gate lines22extend substantially in the X-axis direction for an entire length of the display area AA. Scan signals are input to ends of the gate lines22. The source lines23extend substantially in the Y-axis direction for an entire length of the display area AA. Image signals from the driver13are input to ends of the source lines23. The gate lines22are coupled to gate electrodes20A of the TFTs20. The source lines23are coupled to source regions20B of the TFTs20. The pixel electrodes21are coupled to drain regions20C of the TFTs20. The TFTs20are driven based on various signals supplied to the gate lines22and the source lines23. Application of voltages to the pixel electrodes21is controlled according to driving of the TFTs20.

As illustrated inFIG.3, the pixel electrodes21are disposed in vertically-long rectangular areas defined by the gate lines22and the source lines23. The pixel electrodes21bend with respect to the long-side direction (a longitudinal direction) of the pixel electrodes21. Specifically, the pixel electrodes21include long edges that are slightly angled relative to the Y-axis direction and bent once at about the middle so that each of the pixel electrodes has a shallow V shape with an obtuse vertex. The pixel electrodes21include bending portions21A at about the middle with respect to the longitudinal direction. Each pixel electrode21is sandwiched between two of the gate lines22with respect to the Y-axis direction (the long-side direction) and between two of the source lines23with respect to the X-axis direction (the short-edge direction). Each source line23between the pixel electrodes21that are adjacent to each other with respect to the X-axis direction is parallel to the long edges of the pixel electrodes21and repeatedly bent in zigzag along the long edges of the pixel electrodes21. Each pixel electrode21includes multiple slits21B (five inFIG.2) that extend in the long-edge direction (the Y-axis direction) of the pixel electrode21. The CF substrate11includes a black matrix24(an inter-pixel light blocking portion) illustrated with chain double-dashed lines inFIG.3. The black matrix24includes voids that are opposite to the pixel electrodes21, respectively. Namely, the black matrix24has a grid shape. The black matrix24are opposite the TFTs20, the gate lines22, and the source lines23. The CF substrate11includes spacers illustrated with a chain double-dashed line inFIG.3to maintain the thickness of the liquid crystal layer15(the cell gap). The spacers25are disposed opposite intersections between the gate lines22and the source lines23when viewed in plan.

FIG.4is a plan view of a section of the liquid crystal panel10includes the TFT20and therearound. A configuration of the TFT20will be described in detail with reference toFIG.4. As illustrated inFIG.4, the TFT20is disposed adjacent to the pixel electrode21to which the TFT20is coupled below the pixel electrode21with respect to the Y-axis direction. The TFT20includes the gate electrode20A that is branched off of the gate line22. The gate electrode20A is branched off of the gate line22around the intersection between the gate line22and the source line23to extend in the Y-axis direction. The TFT20includes the source region20B that is coupled to the source line23. The source region20B is coupled to a portion of the source line23away from the intersection between the source line23and the gate line22on an upper side inFIG.4. The source region20B extends in the X-axis direction. The TFT20includes the drain regions20C that is disposed away from the source region20B with respect to the Y-axis direction. The drain region20C extends in the X-axis direction. An end of the drain region20C on an opposite side to the source region20B is coupled to the pixel electrode21. The TFT20is disposed in a layer upper than the gate electrode20A (on a liquid crystal layer15side) and opposite the gate electrode20A. The TFT20includes a channel region20D that continues to the source region20B and the drain region20C. Namely, the TFT20is a top-gate type transistor. The channel region20D is between the source region20B and the drain region20C. A first end of the channel region20D continues to the source region20B. A second end of the channel region20D continues to the drain region20C. When the TFT20is drive according to the scan signal supplied to the gate line22and the gate electrode20A, the image signal (the voltage) supplied to the source line23is transmitted to the drain region20C from the source region20B via the channel region20D. As a result, the pixel electrode21is charged to a potential based on the image signal.

As illustrated inFIG.4, light blocking portions26are provided on a lower layer side (an input surface12A side) relative to the channel regions20D of the TFTs20having the configuration described above, that is, on an opposite side from the gate electrode20A. The light blocking portions26are opposite the channel regions20D. Each light blocking portion26has a horizontally-long shape when viewed in plan such that the light blocking portion26extends in the X-axis direction (an extending direction in which the gate lines22extend). The light blocking portion26is separated from the source line23, that is, in an island configuration. The light blocking portions26block light that may illuminate the channel regions20D from behind. The light may be ambient light that may enter from the input surface12A side. Because the light toward the channel regions20D is blocked by the light blocking portions26, variations in characteristics of the TFTs20, which may occur when the channel regions20D are illuminated with the light, can be reduced.

FIG.5is a cross-sectional view of the liquid crystal panel10along line A-A inFIG.3. As illustrated inFIG.5, multiple color filters27are arranged in a matrix on the CF substrate11in the display area AA. The color filters27are opposite the pixel electrodes21on the array substrate, respectively. The color filters27include red (R), green (G), and blue (B) color filters repeatedly arranged in a predetermined sequence. Each color filter27and corresponding one of the pixel electrodes21opposite the color filter27are configured as a pixel, which is a display unit. The black matrix24is disposed between the adjacent color filters27to reduce color mixture. An overcoat film28is formed on inner surfaces of the color filter27for planarization. The spacers25are formed on an inner surface of the overcoat film28. The spacers25project from the inner surface of the CF substrate11in the Z-axis direction toward the array substrate12. Tips of the spacers25are in contact with or adjacent to the innermost surface of the array substrate12. Alignment films are formed on the innermost surfaces of the substrates11and12to contact the liquid crystal layer15. The alignment films are for alignment of the liquid crystal molecules included in the liquid crystal layer15.

FIG.6is a cross-sectional view of the liquid crystal panel along line B-B inFIG.4. Films on the inner surface of the array substrate12will be described in detail with reference toFIGS.5and6. Specifically, as illustrated inFIGS.5and6, a first metal film F1, a first interlayer insulating film F2(a lower insulating film), at least a semiconductor film F3, a second interlayer insulating film F4(a gate insulating film), a second metal film F5, a third interlayer insulating film F6, a third metal film F7, a fourth interlayer insulating film F8, a planarization film F9, a first transparent electrode film F10, a fifth interlayer insulating film F11, a second transparent electrode film F12, and the alignment film are disposed in this sequence from the lower side (the glass substrate side).

The first metal film F1, the second metal film F5, and the third metal film F7are single-layer film made of one kind of metal that may be selected from copper, titanium, aluminum, molybdenum, and tungsten, multilayer films made of different kinds of metal, or alloys. The first metal film F1, the second metal film F5, and the third metal film F7have conductivities. As illustrated inFIGS.5and6, the light blocking portions26are formed from the first metal film F1. The gate lines22and the gate electrodes20A of the TFTs20are formed from the second metal film F5. The source lines23and intermediate electrodes29, which will be described later, are formed from the third metal film F7. The first transparent electrode film F10and the second transparent electrode film F12may be made of a transparent electrode material such as indium tin oxide (ITO) and indium zinc oxide (IZO). A common electrode30, which will be described later, is formed from the first transparent electrode film F10. The pixel electrodes21are formed from the second transparent electrode film F12.

The semiconductor film F3is an oxide semiconductor film made of an oxide semiconductor material. The source regions20B, the drain regions20C, and the channel regions20D of the TFTs20are formed from the semiconductor film F3. The material of the semiconductor film F3may be an In—Ga—Zn—O-based semiconductor (such as indium gallium zinc oxide). The In—Ga—Zn—O-based semiconductor is a ternary oxide including indium (In), gallium (Ga), and zinc (Zn). A ratio of In, Ga, and Zn (composition ratio) may be but not limited to, 2:2:1, 1:1:1, or 1:1:2. The In—Ga—Zn—O-based semiconductor may be an amorphous semiconductor or a crystalline semiconductor. For the crystalline semiconductor, a crystalline In—Ga—Zn—O-base semiconductor having a C axis that is substantially perpendicular to a layer surface is preferable.

The semiconductor film F3includes resistance-reduced portions and resistance-not-reduced section. Resistances of sections of the semiconductor film F3are reduced through a resistance reducing process performed in production and defined as the resistance-reduced portions. InFIGS.5and6, the resistance-reduced portions of the semiconductor film F3are shaded. The resistivity of each resistance-reduced portion of the semiconductor film F3may be in a range from 1/10000000000 to 1/100, which is significantly less than the resistivity of the resistance-non-reduced section, that is, the resistance-reduced portions function as conductors. The source regions20B and the drain regions20C of the TFTs20may be formed from the resistance-reduced portions of the semiconductor film F3. In the resistance-non-reduced sections of the semiconductor film F3, electric charges are transferrable under specific conditions (when the scan signals are supplied to the gate electrodes20A). In the resistance-reduced portions, electric charges are always transferrable. Namely, the resistance-reduced portions function as conductors. The channel regions20D of the TFTs20are formed from the resistance-non-reduced sections of the semiconductor film F3.

Steps in the production of the array substrate12prior to the resistance reducing process will be briefly described. The semiconductor film F3is formed and patterned. The second interlayer insulating film F4and the second metal film F5are consecutively formed. The second interlayer insulating film F4and the second metal film F5are collectively patterned. With remaining sections of the second interlayer insulating film F4and the second metal film F5(the gate lines22and the gate electrodes20A) used as a mask, the resistance reducing process is performed on the semiconductor film F3. The resistance reducing process is performed exclusively on sections of the semiconductor film F3not covered with the remaining sections of the second interlayer insulating film F4and the second metal film F5(non-opposite sections, exposed sections). The resistance reducing process is not performed on sections of the semiconductor film F3covered with the remaining sections of the second interlayer insulating film F4and the second metal film F5(opposite sections, non-exposed sections). Examples of the resistance reducing process include plasma processing using NH3gas, N2gas, or He gas and annealing processing.

The first interlayer insulating film F2, the second interlayer insulating film F4, the third interlayer insulating film F6, the fourth interlayer insulating film F8, and the fifth interlayer insulating film F11are made of oxide silicon or silicon oxide (SiO2) or silicon nitride (SiNx), which is a kind of inorganic insulating materials (inorganic resin materials). The planarization film F9is made of PMMA (acrylic resin), which is a kind of organic insulating materials (organic resin materials). As illustrated inFIGS.5and6, the first interlayer insulating film F2is disposed between the first metal film F1and the semiconductor film F3to insulate the first metal film F1from the semiconductor film F3. The second interlayer insulating film F4is disposed between the semiconductor film F3and the second metal film F5to insulate the semiconductor film F3from the second metal film F5. Gaps between the gate electrodes20A and the channel regions20D are maintained constant with sections of the second interlayer insulating film F4opposite the gate electrodes20A. The third interlayer insulating film F6is disposed between the semiconductor film F3and the third metal film F7and between the second metal film F5and the third metal film F7to insulate the semiconductor film F3and the second metal film F5from the third metal film F7. Sections of the third interlayer insulating film F6between the intersections of the gate lines22formed from the second metal film F5and the source lines23formed from the third metal film F7insulate the gate lines22from the source lines23. Therefore, the third interlayer insulating film F6may be referred to as an interline insulating film.

As illustrated inFIGS.5and6, the third interlayer insulating film F6includes first pixel contact holes CH1at positions opposite both the drain regions20C of the TFTs20and the pixel electrodes21. The intermediate electrodes29formed from the third metal film F7are disposed opposite the first pixel contact holes CH1. The intermediate electrodes29having island shapes are disposed opposite the first pixel contact holes CH1and coupled to the drain regions20C of the TFTs20via through the first pixel contact holes CH1. The fourth interlayer insulating film F8and the planarization film F9are disposed between the third metal film F7and the first transparent electrode film F10to insulate the third metal film F7from the first transparent electrode film F10. The fifth interlayer insulating film F11is disposed between the first transparent electrode film F10and the second transparent electrode film F12to insulate the first transparent electrode film F10from the second transparent electrode film F12. The fifth interlayer insulating film F11functions as an interelectrode insulating film. The fourth interlayer insulating film F8, the planarization film F9, and the fifth interlayer insulating film F11include second pixel contact holes CH2at positions opposite both sections of the pixel electrodes21and the intermediate electrodes29. The pixel electrodes21are coupled to the intermediate electrodes through the second pixel contact holes CH2. The drain regions20C of the TFTs20are electrically connected to the pixel electrodes21via the intermediate electrodes29that are disposed between the drain regions20C and the pixel electrodes21. Because the drain regions20C are covered with the intermediate electrodes29formed from the third metal film F7, the intermediate electrodes29function as etching stopper during patterning the first transparent electrode film F10to form the common electrode30. Therefore, the drain regions20C are less likely to be overly etched. The third interlayer insulating film F6includes source line contact holes CH3at positions opposite both the source regions20B of the TFTs20and the source lines23. The source lines23are coupled to the source regions20B through the source line contact holes CH3. The spacers25are opposite the source line contact holes CH3.

Next, the common electrode30will be described with reference toFIGS.5to7.FIG.7is a plan view illustrating a pattern of the first transparent electrode film F10(the common electrode30) included in the array substrate12. InFIG.6, sections of the first transparent electrode film F10are shaded. As illustrated inFIGS.5to7, the common electrode30is a solid pattern that spreads in at least an about entire area of the display area on the array substrate12. The common electrode30is disposed under all of the pixel electrodes21with the fifth interlayer insulating film F11between the common electrode30and the pixel electrodes21. The common electrode30includes voids at positions opposite the intermediate electrodes29and the pixel contact holes CH1and CH2to connect the pixel electrodes21in an upper layer to the intermediate electrodes29in a lower layer. A common voltage signal (a reference voltage signal) is supplied to the common electrode30and a potential of the common electrode30is held at a common potential (a reference potential). When the TFTs20are driven and the pixel electrodes21are charged to potentials defined by image signals transmitted by the source lines23, potential differences are created between the pixel electrodes21and the common electrode30. Fringe electric fields (orthogonal electric fields) including components parallel to the plate surface of the array substrate and components normal to the plate surface of the array substrate12may be created between the common electrode30and opening edges of the slits21B of the pixel electrodes21. Using the fringe electric fields, orientations of the liquid crystal molecules in the liquid crystal layer15can be controlled and thus predefined images can be displayed based on the orientations of the liquid crystal molecules. Namely, the liquid crystal panel10that includes the array substrate12according to this embodiment operates in fringe field switching (FFS) mode.

Next, the touch electrodes31will be described with reference toFIGS.5,6and8to15where appropriate.FIG.8is a plan view illustrating patterns of the first metal film F1and the semiconductor film F3included in the array substrate12. InFIG.8, sections of the first metal film F1and the semiconductor film F3are shaded with different shading patterns.FIG.9is a plan view illustrating patterns of the semiconductor film F3and the second metal film F5included in the array substrate12. InFIG.9, sections of the semiconductor film F3and the second metal film F5are shaded with different shading patterns.

As illustrated inFIGS.5,8, and9, the touch electrodes31are disposed in a layer of the array substrate12different from the common electrode30(the first transparent electrode film F10). Specifically, large portions of the touch electrodes31are formed from the resistance-reduced portions32that are prepared by reducing the resistances of sections of the semiconductor film F3. The resistance-reduced portions32extend in the X-axis direction to straddle multiple pixel electrodes21that are arranged in the X-axis direction. The resistance-reduced portions32are arranged at intervals in the Y-axis direction. Between the resistance-reduced portions32adjacent to each other in the Y-axis direction, corresponding one of the gate lines22is disposed. Namely, the resistance-reduced portions32do not straddle (or overlap) the gate lines22. If the semiconductor film F3from which the resistance-reduced portions32are formed include sections that are opposite the gate lines22that are formed from the second metal film F5, the sections may be masked by the gate lines and thus the resistance reducing process may not be performed on the sections, that is, the resistances of the sections may not be reduced (conductivity of the sections may not be increased). The number of the resistance-reduced portions32included in one touch electrode31is equal to the number of the pixel electrodes21that are arranged in the Y-axis direction in an area in which the touch electrode31is formed.

As illustrated inFIGS.8and9, each resistance-reduced portion32extends in the X-axis direction and straddles multiple pixel electrodes21. The resistance-reduced portion32includes a narrow section that crosses corresponding one of the source lines23(a joint section32B, which will be described later). Specifically, each resistance-reduced portion32includes multiple pixel electrode opposite sections32A and the joint section32B. The pixel electrode opposite sections32A are opposite at least sections of the pixel electrodes21that are arranged in the X-axis direction. The joint section32B is coupled to the pixel electrode opposite sections32A that are adjacent to each other. The pixel electrode opposite sections32A have a bent shape that bends along the pixel electrodes21when viewed in plan. The pixel electrode opposite sections32A are opposite large areas of the pixel electrodes21. A dimension of the pixel electrode opposite sections32A in the X-axis direction is greater but a dimension in the Y-axis direction is less in comparison to the pixel electrodes21. The pixel electrode opposite sections32A do not include slits such as slits of the pixel electrodes21. The expression “pixel opposite sections” is used because the pixel opposite sections32A are sections of the resistance-reduced portions32that are opposite the pixel electrodes21. However, the expression does not exclude a configuration that the pixel electrode opposite sections32A include sections that are not opposite the pixel electrodes21(e.g., sections opposite the slits21B). The number of the pixel electrode opposite sections32A included in each resistance-reduced portion32is equal to the number of the pixel electrodes21that are arranged in the X-axis direction in an area in which the touch electrodes31are formed. As illustrated inFIG.5, the pixel electrode opposite sections32A formed from the semiconductor film F3are opposite the pixel electrodes21formed from the second transparent electrode film F12with the third interlayer insulating film F6, the fourth interlayer insulating film F8, the planarization film F9, and the fifth interlayer insulating film F11between the pixel electrode opposite sections32A and the pixel electrodes21.

As illustrated inFIGS.8and9, each joint section32B extends from one of the pixel electrode opposite sections32A that are adjacent to each other in the X-axis direction toward another one of the pixel electrode opposite sections32A to cross the corresponding source line23that is disposed between the adjacent pixel electrode opposite sections32A. A dimension of the joint section32B in the Y-axis direction (an extending direction in which the source line23extends) is less in comparison to the pixel electrode opposite sections32A. Specifically, the dimension of the joint section32B in the Y-axis direction is slightly greater than a width of the gate line22or the source line23. The joint section32B is disposed opposite the bending portion21A of the pixel electrode21with respect to the Y-axis direction and coupled to the middle sections of the pixel electrode opposite sections32A with respect to the longitudinal direction. The number of the joint sections32B included in each resistance-reduced portion32is less than the number of the pixel electrode opposite sections32A in the resistance-reduced portion32by one. The joint sections32B formed from the semiconductor film F3are opposite the source lines formed from the third metal film F7with the third interlayer insulating film F6between the joint sections32B and the source lines23.

As illustrated inFIG.10, the touch electrodes31include (inter-resistance-reduced portion shorting portions) that are coupled to the resistance-reduced portions32to cause short-circuit between the resistance-reduced portions32that arranged in the Y-axis direction.FIG.10is a schematic view illustrating a configuration of the touch electrode31in the liquid crystal panel10. InFIG.10, the source lines23are not illustrated for better visibility. Further,FIG.10illustrates the planar shape of the resistance-reduced portion with exaggeration, which is simple vertically-long rectangular. The coupling portions33extend in the Y-axis direction as a whole to straddle multiple resistance-reduced portions32that are arranged in the Y-axis direction and the gate lines22between the resistance-reduced portions32that are adjacent to each other in the Y-axis direction. Each coupling portion33straddles all of the resistance-reduced portions32included in one touch electrode31. The couple portion33is coupled to the all of the resistance-reduced portions32. Therefore, the all of the resistance-reduced portions32in one touch electrode31are maintained at the same potential. Each coupling portion33does not straddle the touch electrodes31that are adjacent to each other in the Y-axis direction. Namely, the coupling portion33does not exist in the first dividing opening31A1between the touch electrodes31that are adjacent to each other in the Y-axis direction.

As illustrated inFIGS.8and9, a large portion of each coupling portion33is between the pixel electrodes21that are adjacent to each other in the X-axis direction. The large portion of the coupling portion33are opposite the source line23. The coupling portions33are formed from the first metal film F1that is a conductive film from which the light blocking portions26are formed. Therefore, the coupling portions33are opposite the source lines23that are formed from the third metal film F7with the first interlayer insulating film F2and the third interlayer insulating film F6between the coupling portion33and the source lines23(seeFIG.5). The coupling portions33cross the joint sections32B that are included in the resistance-reduced portions32. The first interlayer insulating film F2is between the coupling portions33and the joint sections32B (the semiconductor film F3).

As illustrated inFIGS.8and9, sections of the coupling portions33crossing the gate lines22are curved toward the left to go around the TFTs20. The curved sections are not opposite the source lines23. As illustrated inFIG.11, the coupling portions33include coupling portion-side contacts33A in the curved sections. The coupling portion-side contacts33A are coupled to the resistance-reduced portions32.FIG.11is a plan view illustrating sections of patterns of the first metal film F1and the semiconductor film F3at the coupling portions33and therearound in the liquid crystal panel10. InFIG.11, sections of the first metal film F1and the semiconductor film F3are shaded with different shading patterns. The coupling portion-side contacts33A are formed by widening sections of the coupling portions33. The resistance-reduced portions32include first resistance-reduced portion-side contacts32C that are disposed opposite the coupling portion-side contacts33A and coupled to the coupling portion-side contacts33A. The first resistance-reduced portion-side contacts32C project downward inFIG.11from the pixel electrode opposite sections32A in the Y-axis direction. Distal ends of the first resistance-reduced portion-side contacts32C having a greater width are opposite the coupling portion-side contacts33A. The coupling portion-side contacts33A and the first resistance-reduced portion-side contacts32C are positioned opposite the joints between the source lines23and the source regions20B (the source line contact holes CH3) or the joints between the pixel electrodes21and the drain regions20C (the pixel contact holes CH1, CH2). The first interlayer insulating film F2between the coupling portion-side contacts33A that are formed from the first metal film F1and the first resistance-reduced portion-side contacts32C that are formed from the semiconductor film F3include coupling portion contact holes CH4as illustrated inFIGS.11and12. The coupling portion-side contacts33A are coupled to the first resistance-reduced portion-side contacts32C through the coupling portion contact holes CH4.FIG.12is a cross-sectional view of the liquid crystal panel10along line C-C inFIG.11. The coupling portion contact holes CH4are opposite both the coupling portion-side contacts33A and the first resistance-reduced portion-side contacts32C. Further, the spacers25are opposite sections of the coupling portion-side contacts33A and the first resistance-reduced portion-side contacts32C.

As illustrated inFIG.10, the array substrate12includes touch lines34(position detecting lines) coupled to the touch electrodes31having the configuration described above. The touch lines34extend in the Y-axis direction for substantially an entire length of the display area AA. Touch signals (position detecting signals) output by the driver13are input to ends of the touch lines34. The touch lines34are selectively coupled to specified touch electrodes31of the touch electrodes31that are arranged in the Y-axis direction in the display area AA. Each touch line34is coupled to all of the resistance-reduced portions32included in the touch electrode31that is a target to be connected. According to the configuration, the touch signals transmitted through the touch line34are supplied to all of the resistance-reduced portions32in the touch electrode31. Each touch line34straddles the touch electrodes31that are adjacent to each other in the Y-axis direction and cross the first dividing opening31A1between the touch electrodes31that are adjacent to each other in the Y-axis direction.

As illustrated inFIGS.8and9, a large portion of each touch line34is between the pixel electrodes21that are adjacent to each other in the X-axis direction. The large portion of the touch line34are opposite the source line23. The touch lines34are formed from the first metal film F1that is the conductive film from which the light blocking portions and the coupling portions33are formed. Therefore, the touch lines34are opposite the source lines23that are formed from the third metal film F7with the first interlayer insulating film F2and the third interlayer insulating film F6between the touch lines34and the source lines23(seeFIG.5). The first interlayer insulating film F2is between the touch lines34and the gate lines22(the second metal film F5) that are crossed by the touch lines34. The touch lines34cross the joint sections32B that are included in the resistance-reduced portions32. The first interlayer insulating film F2is between the touch lines34and the joint sections32B (the semiconductor film F3).

As illustrated inFIGS.8and9, the touch lines34are routed similarly to the coupling portions33in the display area AA. More specifically, sections of the touch lines34crossing the gate lines22are curved toward the left inFIGS.8and9to go around the TFTs20. The curved sections of the touch lines34are not opposite the source lines23. As illustrated inFIG.13, the touch lines34include touch line-side contacts34A in the curved sections. The touch line-side contacts34A are coupled to the resistance-reduced portions32.FIG.13is a plan view of the liquid crystal panel10illustrating patterns of the first metal film F1and the semiconductor film F3around the touch lines34. InFIG.13, sections of the first metal film F1and the semiconductor film F3are shaded with different shading patterns. The touch line-side contacts34A are formed by widening sections of the touch lines34. The resistance-reduced portions32include second resistance-reduced portion-side contacts32D that are disposed opposite the touch line-side contacts34A and coupled to the touch line-side contacts34A. The second resistance-reduced portion-side contacts32D extend downward inFIG.13from the pixel electrode opposite sections32A. The second resistance-reduced portion-side contacts32D include distal ends having a greater width and being opposite the touch line-side contacts34A. The touch line-side contacts34A and the second resistance-reduced portion-side contacts32D are positioned opposite the joints between the source lines23and the source regions20B (the source line contact holes CH3), the joints between the pixel electrodes21and the drain regions20C (the pixel contact holes CH1, CH2), or the joints between the resistance-reduced portions32and the coupling portions33(the coupling portion contact holes CH4) (seeFIGS.8and9). As illustrated inFIGS.6and13, the first interlayer insulating film F2between the touch line-side contacts34A that are formed from the first metal film F1and the second resistance-reduced portion-side contacts32D that are formed from the semiconductor film F3includes touch line contact holes CH5. The touch line-side contacts34S are coupled to the second resistance-reduced portion-side contacts32D through the touch line contact holes CH5. The touch line contact holes CH5are opposite both the touch line-side contacts34A and the second resistance-reduced portion-side contacts32D. Further, the spacers25are opposite sections of the touch line-side contacts34A and the second resistance-reduced-portion-side contacts32D. The touch lines34are in pattern (a planar shape) similar to the pattern of the coupling portions33except that the touch lines34cross the first dividing openings31A1. The touch lines34include touch line-side dummy contacts that are opposite the second resistance-reduced portion-side contacts32D of the resistance-reduced portions32included in the touch electrodes31that are targets to be coupled. The touch line-side dummy contacts are in planar pattern similar to the pattern of the touch line-side contacts34A.

As illustrated inFIG.10, the array substrate12includes dummy touch lines35(dummy position detecting lines) that are not coupled to any touch electrodes31. The dummy touch lines35extend in the Y-axis direction for substantially an entire length of the display area AA. Common signals (reference voltage signals) output by the driver13are input to ends of the dummy touch lines35. Each dummy touch line35is disposed between the touch electrodes31that are adjacent to each other in the X-axis direction and in the second dividing opening31A2.

As illustrated inFIGS.8and9, a large portion of each dummy touch line35is disposed between the pixel electrodes21that are adjacent to each other in the X-axis direction. The large portion of the dummy touch line35are opposite the source line23. The dummy touch lines35are formed from the first metal film F1that is a conductive film from which the light blocking portions26, the coupling portions33, and the touch lines34are formed. The dummy touch lines35are opposite the source lines23that are formed from the third metal film F7with the first interlayer insulating film F2and the third interlayer insulating film F6between the dummy touch lines35and the source lines23(seeFIG.5). The first interlayer insulating film F2is between the dummy touch lines35and the gate lines22(the second metal film F5). The dummy touch lines35cross the gate lines22. The dummy touch lines35are disposed in the second dividing openings31A2between the touch electrodes31that are adjacent to each other in the X-axis direction. Namely, the dummy touch lines35do not cross the joint sections32B included in the resistance-reduced portions32.

As illustrated inFIGS.8and9, the dummy touch lines35are routed similarly to the coupling portions33and the touch lines34in the display area AA. More specifically, sections of the dummy touch lines35crossing the gate lines22are curved toward the left inFIGS.8and9to go around the TFTs20. The curved sections are not opposite the source lines23. As illustrated inFIG.14, the dummy touch lines35include dummy touch line-side dummy contacts35A in the curved sections. The dummy touch line-side dummy contacts35A are not opposite the resistance-reduced portions32.FIG.14is a plan view illustrating patterns of the first metal film F1and the semiconductor film F3around the dummy touch line35in the liquid crystal panel10. InFIG.14, sections of the first metal film F1and the semiconductor film F3are shaded with different shading patterns. The dummy touch line-side dummy contacts35A are formed by widening sections of the dummy touch lines35. The resistance-reduced portions32include resistance-reduced portion-side dummy contacts32E that are disposed opposite the dummy touch line-side dummy contacts35A. The resistance-reduced portion-side dummy contacts32E are not coupled to the dummy touch line-side dummy contacts35A. The resistance-reduced portion-side dummy contacts32E project downward inFIG.14in the Y-axis direction from the pixel electrode opposite sections32A. Ends of the resistance-reduced portion-side dummy contacts32E having a greater width are opposite the dummy touch line-side dummy contacts35A. The dummy touch line-side dummy contacts35A and resistance-reduced portion-side dummy contacts32E are positioned opposite joints between the source lines23and the source regions20B (the source line contact holes CH3), joints between the pixel electrodes21and the drain regions20C (the pixel contact holes CH1, CH2), joints between the resistance-reduced portions32and the coupling portions33(the coupling portion contact holes CH4), or joints between the resistance-reduced portions32and the touch lines34(the touch line contact holes CH5) (seeFIGS.8and9). As illustrated inFIG.15, the first interlayer insulating film F2is between the dummy touch line-side dummy contacts35A that are formed from the first metal film F1and the resistance-reduced portion-side dummy contacts32E that are formed from the semiconductor film F3. The first interlayer insulating film F2insulates the dummy touch line-side dummy contacts35A from the resistance-reduced portion-side dummy contacts32E.FIG.15is a cross-sectional view of the liquid crystal panel along line D-D inFIG.14. The spacers25are opposite sections of the dummy touch line-side dummy contacts35A and the resistance-reduced portion-side dummy contacts32E. The dummy touch lines35are in planar pattern (planar shape) similar to the pattern of the touch lines34except that the dummy touch lines35are disposed in the second dividing openings31A2.

This embodiment includes the configurations described above. Next, functions, operation, and effects will be described. In this embodiment, as illustrated inFIG.5, the common electrode30and the touch electrodes31are disposed in different layers in the array substrate12, that is, structurally and electrically independent from each other. The common electrode30exclusively receives the common voltage signals. The touch electrodes31exclusively receive the touch signals. In comparison to a configuration in which the common electrode includes divided portions and perform both the display function a function to generate electric fields between the common electrode and the pixel electrodes21) and the position detecting function, variations in potential of the common electrode30is less likely to occur. Further, sufficient amounts of a display period (a period to generate the electric fields between the pixel electrodes21and the common electrode30) and a position detecting period can be obtained. Therefore, image display can be performed with higher quality and position detection can be performed with higher sensitivity.

As illustrated inFIG.5, large portions of the touch electrodes31are formed from the semiconductor film F3and the second layer from the lower side (the input surface12A side) following the first metal film F1among the conductive films included in the array substrate12. Namely, the touch electrodes31are located in a layer lower than the gate lines22and the source lines23. The touch electrodes31are closer to the position input body that approaches the input surface12A during the position input than the gate lines22and the source lines23. The electric fields generated by the gate lines22and the source lines23are less likely to affect the electrostatic capacitance between the position input body and the touch electrodes31. The common electrode30is formed from the first transparent electrode film F10and in the second layer from the upper side (the liquid crystal layer15side) following the second transparent electrode film F12among the conductive films in the array substrate12. The orientation of the liquid crystal molecules in the liquid crystal layer15is properly controlled by the electric fields between the common electrode30and the pixel electrodes21. Therefore, the images are displayed with higher quality.

As illustrated inFIG.6, the touch lines34are formed from the first metal film F1that is the conductive film from which the light blocking portions26are formed. Namely, the touch lines34and the light blocking portions26can be patterned using the same photomask in the production of the array substrate12. The touch electrodes31are formed from the semiconductor film F3from which the channel regions20D of the TFTs20are formed. Namely, the touch electrodes31and the channel regions20D can be patterned using the same photomask in the production of the array substrate12. Therefore, the number of photomasks required for the production of the array substrate12can be reduced. This is preferable for reduction in production cost of the liquid crystal panel10. The touch lines34that are formed from the first metal film F1and the touch electrodes31that are formed from the semiconductor film F3are in the layers lower than the gate lines (the second metal film F5) and the source lines23(the third metal film F7) and adjacent to each other. Therefore, higher reliability can be achieved in connection between the touch lines34and the touch electrodes31.

As illustrated inFIGS.8and9, each touch electrode31includes multiple resistance-reduced portions32and the coupling portion33. The resistance-reduced portions32include the sections of the semiconductor film F3having the reduced resistances. The coupling portion33crosses the gate line22. The coupling portion33is coupled to the resistance-reduced portions32that are adjacent to each other. The coupling portions33are formed from the first metal film F1that is the conductive film different from the second metal film F5and the semiconductor film F3. With the coupling portions33, the resistance-reduced portions32with the gate lines22disposed therebetween are maintained at the same potential. According to the configuration, potential differences are less likely to be created among the resistance-reduced portions32. This is preferable for expansion of the touch electrodes31in the Y-axis direction. Further, the coupling portions33can be formed by patterning the first metal film F1using the same photomask with which the touch lines34are patterned in the production of the array substrate12. Therefore, the number of the photomasks can be further reduced.

As illustrated inFIG.10, the touch lines34are coupled to the resistance-reduced portions32in the touch electrodes31, respectively. The potential differences are less likely to be created between the resistance-reduced portions32in the touch electrodes31.

As illustrated inFIGS.8and9, the resistance-reduced portions32in the touch electrodes31include the sections that extend in the X-axis direction, which is equal to the extending direction in which the gate lines22extend, and cross the source lines23. The sections having the less width are defined as the joint sections32B. In comparison to a configuration in which the resistance-reduced portions have a constant width in the Y-axis direction, parasitic capacitances between the source lines23and the resistance-reduced portions are reduced. Further, parasitic capacitances between the resistance-reduced portions32and touch lines34to which the resistance-reduced portions32in the touch electrodes31that are different from the touch electrodes31that include the resistance-reduced portions32are coupled are reduced. Therefore, proper levels of sensitivity can be achieved in position detection.

As illustrated inFIGS.8and9, the coupling portions33, the touch lines34, and the dummy touch lines35are opposite the source lines23with the first interlayer insulating film F2and the third interlayer insulating film F6between the source lines23and other components, that is, the coupling portions33, the touch lines34, and the dummy touch lines35. In comparison to a configuration in which the coupling portions and the touch lines are not opposite the source lines23, areas occupied by the coupling portions33, the touch lines34, and the source lines23can be reduced. This is advantageous for increasing aperture ratios. If the dummy touch lines are not opposite the source lines23, difference in load may be created between the source lines23that are opposite the touch lines34and the source lines23that are between the adjacent touch electrodes31and are not opposite the touch lines34. Because the dummy touch lines35are included in this embodiment, differences in load are less likely to be created between the source lines23that are opposite the touch lines34and the source lines23that are between the adjacent touch electrodes31. This improves the display quality.

As described above, the array substrate12in this embodiment includes the gate lines22, the source lines23, the TFTs20(the switching components), the touch electrodes31, the light blocking portions26, and the touch lines34(the position detecting lines). The source lines23cross the gate lines22. The TFTs20include the gate electrodes20A, the channel regions20D, the source regions20B, and the drain regions20C. The gate electrodes20A are coupled to the gate lines22. The channel regions20D are formed from the semiconductor film F3. The channel regions20D are in the layer lower than the gate electrodes20A and opposite the gate electrodes20A with the second interlayer insulating film F4(the gate insulating film) between the gate electrodes20A and the channel regions20D. The source regions20B are coupled to the source lines23and the first ends of the channel regions20D. The drain regions20C are coupled to the second ends of the channel regions20D. The touch electrodes31detect input positions at which the position input operation is performed with the position input body based on the electrostatic capacitances between the position input body and the touch electrodes31. The touch electrodes31are in the layer lower than the gate lines22and the source lines23. The light blocking portions26are in the layer lower than the channel regions20D with the first interlayer insulating film F2(the lower insulating film) between the channel regions20D and the light blocking portions26. The light blocking portions26are opposite the channel regions20D. The touch lines34are coupled to the touch electrodes31. The touch lines34are formed from the first metal film F1that is the conductive film from which the light blocking portions26are formed.

When the signals transmitted through the gate lines22are supplied to the gate electrodes20A, the TFTs20turn on. The signals transmitted through the source lines23are supplied from the source regions20B to the drain regions20C via the channel regions20D. Because the light blocking portions26are disposed in the layer lower than the channel regions20D that are formed from the semiconductor film F3and opposite the channel regions20D with the first interlayer insulating film F2between the channel regions20D and the light blocking portions26, the light from the lower layer side toward the channel regions20D are blocked by the light blocking portions26. According to the configuration, variations in characteristics of the TFTs20resulting from the light applied to the channel regions20D can be reduced.

The touch electrodes31detect the input positions at which the position input operation is performed with the position input body using the signals supplied through the touch lines34based on the electrostatic capacitances between the position input body and the touch electrodes31. The touch electrodes31are in the layer lower than the gate lines22and the source lines23. If the surface of the array substrate12on an opposite side from the surface on which the components are disposed is configured as an input surface through which the position input operation is performed with the position input body, the tough electrodes31may be closer to the position input boy than the gate lines22and the source lines23. Therefore, the electric fields created by the gate lines and the source lines23are less likely to affect the electrostatic capacitances between the position input body and the touch electrodes31. This improves the sensitivity in position detection.

The touch lines34are formed from the first metal film F1that is the conductive film from which the light blocking portions26. In the production, the touch lines34and the light blocking portions26can be produced through patterning using the same photomask. Namely, this configuration is advantageous for reducing the number of photomasks. The touch lines34and the touch electrodes31are in the layers lower than the gate lines22and the source lines23. The touch lines34and the touch electrodes31are closer to each other. Therefore, the reliability in connection is high.

The TFTs20include the channel regions20D that are formed from the sections of the semiconductor film F3. The touch electrodes31include the resistance-reduced portions32that are formed from the sections of the semiconductor film F3with the reduced resistances. The touch electrodes31are formed from the semiconductor film F3from which the channel regions20D are formed. In the production, the touch electrodes31and the channel regions20D are produced through patterning using the same photomask. This is advantageous for reducing the number of the photomasks. The resistances of the sections of the semiconductor film F3not opposite the gate electrodes20A are reduced by performing resistance-reducing process on the semiconductor film F3using the gate electrodes20A opposite the channel regions20D as a photomask.

The array substrate12according to this embodiment includes the gate lines22, the source lines23, the TFTs20, the touch lines34, and the touch electrodes31. The source lines23cross the gate lines22. The gate electrodes20A are coupled to the gate lines22. The TFTs20include the gate electrodes20A, the channel regions20D, the source regions20B, and the drain regions20C. The gate electrodes20A are coupled to the gate lines22. The channel regions20D are in the layer lower than the gate electrodes20A with the second interlayer insulating film F4between the gate electrodes20A and the channel regions20D. The channel regions20D are formed from the semiconductor film F3. The source regions20B are coupled to the source lines23and the first ends of the channel regions20D. The drain regions20C are coupled to the second ends of the channel regions20D. The touch electrodes31are coupled to the touch lines34. The touch electrodes31detect the input positions at which the position input operation is performed with the position input body based on the electrostatic capacitances between the position input body and the touch electrodes31. The touch electrodes31include the resistance-reduced portions32formed by reducing the resistances of the sections of the semiconductor film F3. The resistance-reduced portions32are in the layer lower than the gate lines22and the source lines23.

When the signals transmitted through the gate lines22are supplied to the gate electrodes20A, the TFTs20turn on. The signals transmitted through the source lines23are supplied from the source regions20B to the drain regions20C via the channel regions20D. The light blocking portions26are disposed in the layer lower than the channel regions20D that are formed from the semiconductor film F3with the first interlayer insulating film F2with the light blocking portions26and the channel regions20D. The light blocking portions26are opposite the channel regions20D. Therefore, the light from the lower layer side toward the channel regions20D are blocked by the light blocking portions26. This reduces the variations in characteristics of the TFTs20resulting from the light applied to the channel regions20D.

The touch electrodes31detect the input positions at which the position input operation is performed with the position input body using the signals supplied through the touch lines34based on the electrostatic capacitances between the position input body and the touch electrodes31. The touch electrodes31are in the layer lower than the gate lines22and the source lines23. If the surface of the array substrate12on an opposite side from the surface on which the components are disposed is configured as an input surface through which the position input operation is performed with the position input body, the tough electrodes31may be closer to the position input boy than the gate lines22and the source lines23. Therefore, the electric fields created by the gate lines and the source lines23are less likely to affect the electrostatic capacitances between the position input body and the touch electrodes31. This improves the sensitivity in position detection.

The touch electrodes31are formed from the semiconductor film F3from which the channel regions20D are formed. In the production, the touch electrodes31and the channel regions20D are produced through patterning using the same photomask. This is advantageous for reducing the number of the photomasks. The resistances of the sections of the semiconductor film F3not opposite the gate electrodes20A are reduced by performing resistance-reducing process on the semiconductor film F3using the gate electrodes20A opposite the channel regions20D as a photomask.

The resistance-reduced portions32are arranged at intervals such that each gate line22is between the adjacent resistance-reduced portions32. Each touch electrode31crosses the corresponding gate line22and is coupled to the adjacent resistance-reduced portions32. The touch electrodes include the coupling portions33that are formed from the first metal film F1that is the conductive film different from the semiconductor film F3and the second metal film F5that is the conductive film from which the gate lines22are formed. If the semiconductor film is patterned so that the touch electrodes21are opposite the gate lines22, the resistances of the sections of the semiconductor film opposite the gate lines22cannot be reduced through the resistance reducing process. Because the coupling portions33that are formed from the first metal film F1that is the conductive film different from the semiconductor film F3and the second metal film F5that is the conductive film from which the gate lines22are formed cross the respective gate lines22and are coupled to the adjacent resistance-reduced portions32, the resistance-reduced portions32sandwiching the respective gate lines22are maintained at the same potential. According to the configuration, the potential differences are less likely to be created among the resistance-reduced portions32. This is advantageous for expanding the areas in which the touch electrodes31are formed.

The coupling portions33are formed from the first metal film F1that is the conductive film from which the touch lines34are formed. Because the coupling portions33are formed from the first metal film F1that is the conductive film from which the touch lines34are formed, the coupling portions and the touch lines34are formed through the patterning using the same photomask in the production. This is advantageous for further reducing the number of the photomasks.

Each touch line34is coupled to multiple resistance-reduced portions32included in the target touch electrode31. According to the configuration, the signals transmitted through the touch line34are supplied to the resistance-reduced portions32in the target touch electrode31, respectively. Therefore, the potential differences are less likely to be created among the resistance-reduced portions32.

At least sections of the coupling portions33are opposite the source lines23with the first interlayer insulating film F2and the third interlayer insulating film F6, which are insulating films, between the sections of the coupling portions33and the source lines23. In comparison to a configuration in which the coupling portions are not opposite the source lines23, the areas occupied by the coupling portions33and the source lines23can be reduced. This is advantageous for increasing the aperture ratios.

The pixel electrodes21are arranged to sandwich the source lines23, respectively. The pixel electrodes21are coupled to the drain regions20C of the TFTs20. The resistance-reduced portions32include the pixel electrode opposite sections32A and the joint sections32B. The pixel opposite sections32A are opposite at least the sections of the pixel electrodes21, respectively, with the insulating films including the third interlayer insulating film F6, the fourth interlayer insulating film F8, the planarization film F9, and the fifth interlayer insulating film F11between the sections of the pixel electrodes21and the pixel electrode opposite sections32A. The joint sections32B cross the respective source lines23. The joint sections32B are coupled to the adjacent pixel electrode opposite sections32A. Each joint section32B has the dimension in the extending direction in which the source lines23extend less than the dimension of each pixel electrode opposite section32A. When the TFTs20turn on, the pixel electrodes21are charged to the potentials based on the signals transmitted through the source lines23. The pixel electrode opposite sections32A of the resistance-reduced portions32are connected by the joint sections32B of the resistance-reduced portions32. The joint sections32B cross the source lines23. The dimension of each joint section32B in the extending direction in which the source lines23extend is less than each pixel electrode opposite section32A. In comparison to a configuration in which the dimension of each resistance-reduced portion in the extending direction in which the source lines23extend is constant, the parasitic capacitances between the source lines23and the resistance-reduced portions32are reduced. This improves the sensitivity in the position detection.

At least the sections of the touch lines34are opposite the source lines23with the insulating films including the first interlayer insulating film F2and the third interlayer insulating film F6between the sections of the touch lines34and the source lines23. In comparison to a configuration in which the touch lines are not opposite the source lines23, the areas occupied by the touch lines34and the source lines23can be reduced. This is advantageous for improving the aperture ratios.

The touch electrodes31are arranged at intervals to sandwich the source lines23, respectively. The dummy touch lines35(the dummy position detecting lines) are disposed opposite the source lines23between the adjacent touch electrodes31with the insulating films including the first interlayer insulating film F2and the third interlayer insulating film F6between the dummy touch lines35and the source lines23. The dummy touch lines35are not coupled to any touch electrodes31. If the dummy touch lines are not provided, differences in load may be created between the source lines23that are opposite the touch lines34and the source lines23that are between the touch electrodes31and not opposite the touch lines34. Because the dummy touch lines35are disposed opposite the source lines23between the adjacent touch electrodes31with the insulating films including the first interlayer insulating film F2and the third interlayer insulating film F6between the source lines23and the dummy touch lines35, the differences in load are less likely to be created between the source lines23that are opposite the touch lines34and the source lines23that are between the touch electrodes31and not opposite the touch lines34. This improves the display quality.

The pixel electrodes21and the common electrode30are provided. The pixel electrodes21are coupled to the drain regions20C of the TFTs20. The common electrode30are opposite the pixel electrodes21with the fifth interlayer insulating film F11that is the insulating film between the pixel electrodes21and the common electrode30. The pixel electrodes21and the common electrode30are in the layers upper than the gate lines22and the source lines23. According to the configuration, when the TFTs20turn on, the pixel electrodes21are charged to the potentials based on the signals that are transmitted through the source lines23. The electric fields based on the potentials at the pixel electrodes21are created between the pixel electrodes21and the common electrode30. When the array substrate12is used in the liquid crystal panel10, the images are displayed using the electric fields created between the pixel electrodes21and the common electrode30. The common electrode30are provided separately from the touch electrodes31. In comparison to a configuration in which the common electrode includes segments and the has a function for creating electric fields between the segments and the pixel electrodes21and a function for detecting positions, the potential at the common electrode30is less likely to vary. Further, sufficient periods are obtained for creating the electric fields between the pixel electrodes21and the common electrode30and for detecting the positions. According to the configuration, proper display quality can be achieved for displaying the images and proper sensitivity is obtained for detecting the positions.

The liquid crystal panel10according to this embodiment includes the array substrate12described above and the CF substrate11(the opposed substrate). The CF substrate11is opposite the array substrate12. According to the liquid crystal panel10, the number of the photomasks required for production of the array substrate12can be reduced and thus the production cost can be reduced.

Second Embodiment

A second embodiment will be described with reference toFIGS.16to18. The second embodiment includes. Components, functions, and effects similar to those of the first embodiment previously described will not be described.

A driver according to this embodiment supply two kinds of touch signals illustrated inFIG.16to touch lines coupled to touch electrodes131disposed in a display area, respectively. The two kinds of the touch signals are opposite in phase with each other.FIG.16is a diagram illustrating waveforms of the touch signals supplied from the driver to the touch electrodes131. InFIG.16, the horizontal axis represents time t. InFIG.16, the vertical axis represents amplitude of the touch signals with symbols (+, −) that indicate polarities. Specifically, the touch signals output by the driver to the touch lines include first touch signals and second touch signals. The first touch signals has the waveform on the upper side inFIG.16. The second touch signals has the waveform on the lower side inFIG.16. The first touch signals and the second touch signals are opposite in phase with each other, that is, the polarities of the first touch signals and the second touch signals at the same timing are opposite to each other. Specifically, at time t1, the polarity of the first touch signal is positive whereas the polarity of the second touch signal is negative. At time t2(λ/2 after time t1), the polarity of the first touch signal is negative whereas the polarity of the second touch signal is positive.

As illustrated inFIGS.17and18, the driver supplies the touch signals to the touch electrodes131so that the phases of the touch signals supplied to the touch electrodes131adjacent to each other in the X-axis direction in the display area are opposite to each other and the phases of the touch signals supplied to the touch electrodes131adjacent to each other in the Y-axis direction in the display area are opposite to each other.FIG.17illustrates the polarities of the touch electrodes131at time t1illustrated inFIG.16.FIG.18illustrates the polarities of the touch electrodes131at time t2illustrated inFIG.16. Specifically, the first touch signals are supplied from the driver to the touch lines couple to a first group of the touch electrodes131and the second touch signals are supplied from the driver to the touch lines coupled to a second group of the touch electrodes131adjacent to the first grope of the position detection electrodes in the X-axis direction. Similarly, the first touch signals are supplied from the driver to the touch lines couple to a first group of the touch electrodes131and the second touch signals are supplied from the driver to the touch lines coupled to a second group of the touch electrodes131adjacent to the first grope of the position detection electrodes in the Y-axis direction. At time t1and time t1, the touch electrodes131with the positive polarity and the touch electrodes131with the negative polarity are in zigzag arrangement in a plan view.

Parasitic capacitances are created between the touch electrodes131and the common electrode. If variations in potential of the touch electrodes131occur, the variations may result in variations in potential of the common electrode. In this embodiment, the touch signals in opposite phase are supplied from the driver to the touch lines coupled to the adjacent touch electrodes131. Therefore, effects of the variations on the common electrode are cancelled. Because the variations in potential of the common electrode are less likely to occur and thus proper display quality is achieved.

The embodiment described above includes the driver (a signal supply) that is coupled to the touch lines to supply the touch signals (the position detecting signals) to the touch lines. The touch electrodes131are arranged at intervals. The driver supplies the touch signals in opposite phases to the touch lines coupled to the adjacent touch electrodes131, respectively. In comparison to a configuration in which the driver supplies the touch signals in the same phase to all of the touch lines, the potential of the common electrode is less likely to vary when the parasitic capacitances are created between the touch electrodes131and the common electrode. This improves the display quality.

Other Embodiments

The technology described herein is not limited to the embodiments described above and illustrated by the drawings. For example, the following embodiments will be included in the technical scope of the present invention.

(1) Each touch electrode31,131may include multiple coupling portions33. If so, it is preferable that the coupling portions33are separated from each other in the X-axis direction in the resistance-reduced portion32(e.g., ones at the edges of the resistance-reduced portion32and one at the middle of the resistance-reduced portion32).

(2) The coupling portions33may not be coupled to all of the resistance-reduced portions32included in the touch electrodes31,131. The coupling portions33may be coupled to some of the resistance-reduced portions32included in the touch electrodes31,131. In such a configuration, the resistance-reduced portions32may be grouped such that each group includes multiple resistance-reduced portions32. The number of the coupling portions33may be set equal to the number of groups of the resistance-reduced portions32and the coupling portions33may be coupled to the groups of the resistance-reduced portions32, respectively.

(3) The coupling portions33may be omitted if the touch lines34are coupled to all of the resistance-reduced portions32included in the target touch electrodes31,131.

(4) The touch lines34may not be coupled to all of the resistance-reduced portions32included in the target touch electrodes31,131. The touch lines34may be coupled to some of (or one of) the resistance-reduced portions32. In such a configuration, the touch signals can be supplied to the resistance-reduced portions32that are not coupled to the touch lines34via the resistance-reduced portions32that are coupled to the touch lines34.

(5) Multiple touch lines34may be coupled to each touch electrode31,131.

(6) The layouts of the coupling portions33and the touch lines34in the forming areas of the touch electrodes31,131may be altered where appropriate.

(7) The number, the layouts, and the width of the joint sections32B included in the resistance-reduced portions32may be altered where appropriate. For example, the joint sections32B may be coupled to edge sections of the pixel electrode opposite sections32A at ends of the pixel electrode opposite section32A with respect to the Y-axis direction. The joint sections32B may be coupled to multiple sections of the pixel electrode opposite sections32A. The sections may be at intervals in the Y-axis direction.

(8) The light blocking portions26may be coupled to the gate electrodes20A of the TFTs20so that the light blocking portions26may function as second gate electrodes. Namely, each TFT20may have a double-gate configuration.

(9) The light blocking portions26may be omitted.

(10) The touch electrodes31,131may be formed from a conductive film that is different from the semiconductor film F3. The conductive film may have light transmissivity. In such a case, a third transparent electrode film may be formed on the array substrate12and the touch electrodes31,131may be formed by patterning the third transparent electrode film.

(11) In the second embodiment, the same kind of touch signals may be supplied to the touch lines coupled to the touch electrodes131that are arranged in the X-axis direction and different kinds of tough signals may be supplied to the touch lines coupled to the touch electrodes that are adjacent to each other in the Y-axis direction. Similarly, the same kind of touch signals may be supplied to the touch lines coupled to the touch electrodes131that are arranged in the Y-axis direction and different kinds of tough signals may be supplied to the touch lines coupled to the touch electrodes that are adjacent to each other in the X-axis direction.

(12) The coupling portions33may not be opposite the source lines23.

(13) The touch lines34may not be opposite the source lines23.

(14) The dummy touch lines35may not be opposite the source lines23.

(15) The pixel electrodes21may be formed from the first transparent electrode film F10and the common electrode30may be formed from the second transparent electrode film F12. In such a configuration, the common electrode30may include slits for orientation control.

(16) The planar shape of each pixel electrode21may be altered where appropriate. The routing of the source lines23may be altered along with the alteration of the planar shape of the pixel electrode21where appropriate. The number and the planer shape of the slits21B in the pixel electrodes21may be altered where appropriate.

(17) More than one driver13and more than one flexible circuit board14may be provided.

(18) The flexible circuit board14may be mounted on the array substrate12using the film-on-glass (FOG) technology. The driver13may be mounted on such a flexible circuit board14using the chip-on-film (COF) technology.

(19) The touchscreen pattern may use a mutual capacitance method instead of the self-capacitance method.

(20) The planar shape of the liquid crystal panel may be other than the vertically-long rectangular shape (e.g., a horizontally-long rectangular shape, a square shape, a trapezoidal shape, a circular shape, and an oval shape).

(21) The liquid crystal panel10may display images in TN mode, VA mode, or IPS mode rather than FFS mode.

(22) The liquid crystal panel10may be a reflective-type panel or a semi-transmissive-type panel. If the liquid crystal panel10is the reflective-type panel, the backlight is not required.

(23) Amorphous silicon or polysilicon (LTPS) rather than the oxide semiconductor film may be used for the semiconductor film F3.

(24) A display panel that is a different type of display panel from the liquid crystal panel10(e.g., an organic EL display panel, and a microcapsule-type electrophoretic display (EPD)) may be used.