3-D DRAM structures and methods of manufacture

Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

TECHNICAL FIELD

Embodiments of the present disclosure pertain to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the disclosure provide dynamic random-access memory with bridged word lines and/or etch stop layers.

BACKGROUND

Electronic devices, such as personal computers, workstations, computer servers, mainframes and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. There are two major types of random-access memory cells, dynamic and static, which are well-suited for use in electronic devices. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values, but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short periods of time. Static random-access memories (SRAM) are so named because they do not require periodic refreshing.

DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with nonarray devices

In 3D memory devices word lines of the unit cell layers should be connected. However, the active layers of the unit cells should not be connected. Additionally, the lengths of the capacitors need to be controlled without the effects of variation during selective removal processes interfering. The length of the capacitor is longer than the gate length of the cell transistor. The longer selective removal length gives rise to larger variations in length due to variable removal rates. Therefore, there is a need in the art for memory devices and methods of forming memory devices that include one or more of connected word lines, separate active regions or etch controls.

SUMMARY

One or more embodiments of the disclosure are directed to memory devices comprising a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active along the third direction. A conductive bridge extends along the second direction and connects each conductive layer to one or more adjacent conductive layer.

Additional embodiments of the disclosure are directed to memory devices comprising a plurality of pairs of active regions spaced along a first direction, a second direction and a third direction. A plurality of bit lines extend along the third direction between the pairs of active regions spaced in the first direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions. The at least one side being located along the third direction relative to the active region. A conductive bridge extends along the second direction connecting each conductive layer to one or more adjacent conductive layer.

Further embodiments of the disclosure are directed to methods of forming a memory device. A stack of films comprising a sacrificial layer and a channel layer is patterned to form a pair of pre-bridge stacks separated along a first direction and an isolated film stack extending along the first direction. The pre-bridge stacks are formed on either side of the isolated film stack, along a second direction, creating an opening between the pre-bridge stacks and openings outside the pre-bridge stacks, along the first direction, and a gap between the isolated film stack and an adjacent film stack along the second direction. The channel layer is removed from the pre-bridge stacks and is recessed into the isolated film stack through the openings to form recessed channel layers in the isolated film stack. The openings and recessed channel layers are filled with a dielectric. A trench is formed in the isolated film stack along the second direction. The trench is formed between the pair of pre-bridge stacks along the first direction. A portion of the sacrificial layer is removed from the isolated film stack through the trench to form a recessed sacrificial layer with a recessed sacrificial layer surface and a word line opening, and expose a surface of the channel layer. A gate oxide layer is formed in the word line opening on the surface of the channel layer exposed through the trench. A conductive layer is deposited in the word line opening on the gate oxide layer. The trench is filled with a dielectric. A slit pattern is formed through the sacrificial layer and channel layer. The slit pattern is formed on opposite sides of the location that the trench was formed and outside of the conductive layer in the word line opening. The slit pattern exposes a sidewall of the channel layer and a sidewall of the sacrificial layer. A portion of channel layer is removed through the slit pattern to form a capacitor opening exposing a face of the sacrificial layer and recessed channel layer. A capacitor is formed in the capacitor opening adjacent the recessed channel layer.

DETAILED DESCRIPTION

As used herein, the term “dynamic random access memory” or “DRAM” refers to a memory cell that stores a datum bit by storing a packet of charge (i.e., a binary one), or no charge (i.e., a binary zero) on a capacitor. The charge is gated onto the capacitor via an access transistor, and sensed by turning on the same transistor and looking at the voltage perturbation created by dumping the charge packet on the interconnect line on the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. The DRAM device is formed of an array of DRAM cells.

Traditionally, DRAM cells have recessed high work-function metal structures in buried word line structure. In a DRAM device, a bitline is formed in a metal level situated above the substrate, while the word line is formed at the polysilicon gate level at the surface of the substrate. In the buried word line (bWL), a word line is buried below the surface of a semiconductor substrate using a metal as a gate electrode.

In one or more embodiments, memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density, which is proportional to the number of multi-pair films. The DRAM device of one or more embodiments has vertical bit lines, minimizing bit line capacitance and reducing the burden of capacitor capacitance.

Some embodiments advantageously provide memory devices and methods of forming memory devices with increased device density. Some embodiments provide devices where the active region of each unit cell is separated horizontally by insulators between each active region. Some embodiments provide word lines for each cell at the same row and the same stack level connected through a bridge. In some embodiments, the bridge is smaller than the width of the gate. In some embodiments, one side of the active is connected with a capacitor and the other side is connected with a bit line.

Some embodiments provide memory devices and methods of forming memory devices with improved integration to fabricate 3D DRAM. In some embodiments, the length of the capacitors is controlled to eliminate or minimized variations due to selective removal processes of the sacrificial layers. In some embodiments, the length of the capacitor is longer than the gate length of the cell transistor.

FIG.1illustrates a generic three-dimensional structure of a 3D DRAM device10in accordance with one or more embodiment of the disclosure. The device10has a three-dimensional array of active regions arranged into rows, columns and layers. The conventions used herein, the rows are referred to as the X-axis or first direction20; the columns are referred to as the Y-axis or second direction30, and the layers are referred to as the Z-axis or third direction40. The angle25between the first direction20and second direction30is any suitable angle in the range of 30° to 150°, or in the range of 45° to 135°, or in the range of 60° to 120°, or in the range of 75° to 105°, or in the range of 85° to 95°. The angle35between the first direction20and the third direction30is any suitable angle in the range of 30° to 150°, or in the range of 45° to 135°, or in the range of 60° to 120°, or in the range of 75° to 105°, or in the range of 85° to 95°. The angle45between the second direction30and the third direction40is any suitable angle in the range of 30° to 150°, or in the range of 45° to 135°, or in the range of 60° to 120°, or in the range of 75° to 105°, or in the range of 85° to 95°. In some embodiments, each of angles25,35and45are in the range of 85° to 95°.

FIGS.2A through2Cillustrated three arrangements of active regions115, conductive layers120and bridges130connecting adjacent conductive layers120. InFIG.2A, the conductive layers120and bridge130are on the bottom of the active regions115. As used in this specification, the terms “top”, “bottom”, “above”, “below”, and the like, refer to a physical orientation along the Z-axis or third direction40and should not be taken as limiting the scope of the disclosure to any particular orientation related to the normal pull of gravity. InFIG.2B, the conductive layers120and bridge130are on the top of the active regions115. InFIG.2C, the conductive layers120and bridges130are both above and below the active region115.

FIG.3illustrates a parallel projection view of a memory device100in accordance with one or more embodiment of the disclosure.FIG.4illustrates an isometric schematic view of a 3D memory device100. The device100illustrated has a total of six bit lines170and twelve word lines160. A total thirty-six active regions115are connected with conductive layers120and bridges130. The embodiment shown inFIG.3shows two unit cells105on either side of, and each unit cell105including a portion of, a bit line170. Each of the unit cells105of some embodiments independently store data.

Referring toFIGS.3and4, the memory device100of some embodiments comprises a plurality of active regions115spaced along a first direction20(as shown inFIGS.3and4), a second direction30(as shown inFIG.4) and a third direction40(as shown inFIG.4). The active region115of some embodiments comprises a transistor. The active region115of some embodiments comprises a stack of material layers (not shown) including a charge tunneling layer, a charge trapping layer and a charge blocking layer. The skilled artisan will understand the process for forming a transistor, and for purposes of drawing clarity, the individual layers are not illustrated.

A plurality of conductive layers120are arranged so that at least one conductive layer120is adjacent to at least one side of each of the active regions115along the third direction40. As used in this manner, the term “adjacent to” means next to, in direct contact with or with a minimal number of components or distance between the stated components. For example, the conductive layer120illustrated inFIG.3is adjacent to the active region115with a gate oxide140layer between.

In some embodiments, at least some of the active regions115have one conductive layer120adjacent thereto, as illustrated inFIGS.2A,2B and4. In some embodiments, each of the active regions115has a conductive layer120on either side of the active region115, along the third direction, as shown inFIGS.2C and3. As used in this manner, the arrangement of components along a specified direction means that the stated components are aligned along that direction. For example, the conductive layers120on either side of the active region115, as shown inFIG.3, means that the conductive layers120are aligned along the third direction40(the Z-axis direction) with the active region115.

A conductive bridge130extends along the second direction20. The conductive bridge130connects the conductive layer120to one or more adjacent conductive layers. The conductive bridges130shown inFIG.4illustrate the connections to multiple adjacent conductive layers120. The conductive bridges130form a connection between the conductive layers120along the second direction20, the Y-axis direction.

In some embodiments, as shown inFIG.3, a gate oxide140is positioned between the active region115and the conductive layer120. The gate oxide140can be any suitable dielectric material including low-k and high-k dielectric materials. In some embodiments, the gate oxide140comprises one or more of silicon oxide, silicon nitride or silicon oxynitride.

The memory device100of some embodiments includes a capacitor180on a side of the active region115along the first direction20. The capacitor180is electrically separated from the conductive layers120and the conductive bridges130. Stated differently, the capacitor180is not in direct contact with the conductive layers120or the conductive bridge130.

The capacitor180of some embodiments comprises a lower electrode182, a high-k dielectric184and an upper electrode186. The lower electrode182is in contact with the active region115. The high-k dielectric184is adjacent to the lower electrode182and on an opposite side of the lower electrode182than the active region115. The upper electrode186is adjacent to the high-k dielectric184and on an opposite side from the lower electrode182. In some embodiments, the high-k dielectric184directly contacts the lower electrode182. In some embodiments, the upper electrode186directly contacts the high-k dielectric184.

In some embodiments, a doped layer117is between the active region115and the lower electrode182along the first direction20. The doped layer117can be any suitable material known to the skilled artisan. In some embodiments, the doped layer117comprises titanium nitride.

In some embodiments, the active region119includes a source/drain region119adjacent to the bit line170. The source/drain region119can be formed by any suitable technique known to the skilled artisan.

The memory device100of some embodiments further comprises a bit line170extending along the third direction40. The bit line170is adjacent to the active regions115that are spaced along the third direction40(as shown inFIG.4). The bit line170of some embodiments is in direct contact with the active region115. In some embodiments, the bit line170is spaced from the active region115by a conductive material.

For uniformity of measurements and size relationships, the length of any given component is measured along the first direction20(the X-axis direction), the width is measured along the second direction30(the Y-axis direction) and the height is measured along the third direction40(the Z-axis direction).

In some embodiments, the length of the active region115along the first direction20is in the range of 50 nm to 300 nm, or in the range of about 75 nm to about 200 nm, or in the range of about 100 nm to about 150 nm, or in the range of about 110 nm to about 130 nm. In some embodiments, a source/drain region119is located at the end of the active region115adjacent the bit line170, and the source/drain region119is included in the overall length of the active region115. In some embodiments, a doped layer117is located at the end of the active region115adjacent the capacitor180and the doped layer117is included in the overall length of the active region. In some embodiments, both a doped layer117and a source/drain region119are included in the active region115length.

In some embodiments, the width of the active region115along the second direction30is in the range of 50 nm to 300 nm, or in the range of about 75 nm to about 200 nm, or in the range of about 100 nm to about 150 nm, or in the range of about 110 nm to about 130 nm.

In some embodiments, the length of the capacitor180along the first direction20is in the range of 200 nm to 1500 nm, or in the range of about 300 nm to about 1000 nm, or in the range of about 400 nm to about 750 nm, or in the range of about 450 nm to about 550 nm. In some embodiments, the width of the capacitor180along the second direction30is in the range of 50 nm to 300 nm, or in the range of about 75 nm to about 200 nm, or in the range of about 100 nm to about 150 nm, or in the range of about 110 nm to about 130 nm.

In some embodiments, the length of the conductive layer120along the first direction20is in the range of 50 nm to 200 nm, or in the range of 75 nm to 150 nm, or in the range of 90 nm to 125 nm. In some embodiments, the width of the conductive layer120along the second direction30is in the range of 40 nm to 250 nm, or in the range of 50 nm to 200 nm, or in the range of 75 nm to 150 nm, or in the range of 90 nm to 125 nm.

In some embodiments, the conductive layer120is spaced along the first direction20from the bit line170. In one or more embodiments, the space between the conductive layer120and the bit line170along the first direction20is in the range of 5 nm to 20 nm, or in the range of 8 nm to 15 nm, or about 10 nm. In some embodiments, the conductive layer120is spaced along the first direction20from the capacitor180. In one or more embodiments, the space between the conductive layer120and the capacitor180along the first direction20is in the range of 5 nm to 20 nm, or in the range of 8 nm to 15 nm, or about 10 nm.

In some embodiments, the conductive bridge130has a length along the first direction20in the range of 5 nm to 180 nm, or in the range of 5 nm to about 180 nm, or in the range of 10 nm to 150 nm, or in the range of 15 nm to 100 nm, or in the range of 20 nm to 80 nm, or in the range of 30 nm to 70 nm, or in the range of 40 nm to 60 nm. In some embodiments, the conductive bridge130has a length that is smaller than the length of the active region115. In some embodiments, the conductive bridge130has a length that is smaller than the length of the conductive region120. In some embodiments, a length of the conductive bridge130along the first direction20is in the range of 10% to 90% of the length of the conductive layer120. In some embodiments, the length of the conductive bridge130along the first direction20is in the range of 20% to 80%, or 30% to 70% or 40% to 60% of the length of the conductive layer120.

In some embodiments, the width of the conductive bridge130along the second direction30is in the range of 50 nm to 200 nm, or in the range of 60 nm to 150 nm, or in the range of 70 nm to 125 nm, or in the range of 90 nm to 110 nm. The width of the conductive bridge130of some embodiments is the same as the spacing between the rows of unit cells105.

In some embodiments, the bit line170has a length along the first direction20in the range of 50 nm to 150 nm, or in the range of 60 nm to 130 nm, or in the range of 70 nm to 110 nm, or in the range of 75 nm to 90 nm. In some embodiments, the bit line170has a width along the second direction30in the range of 50 nm to 150 nm, or in the range of 60 nm to 130 nm, or in the range of 70 nm to 110 nm, or in the range of 75 nm to 90 nm.

In some embodiments, each layer of the unit cell105has a height along the third direction40in the range of 10 nm to 50 nm, or in the range of 15 nm to 30 nm, or in the range of 20 nm to 25 nm.

In some embodiments, the memory device100includes a plurality of pairs of active regions spaced in the first direction20.FIG.3illustrates an embodiment with a pair of active regions115on either side of a bit line170along the first direction20. Stated differently, in some embodiments, a plurality of bit lines170extend along the third direction40between the pairs of active regions115spaced in the first direction20. As shown inFIG.3, the bit line170and the two active regions115(forming the pair of active regions) are aligned along the first direction20(the X-axis direction).

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing.

FIGS.5through19illustrate one or more methods for forming the memory device100illustrated inFIGS.3and4. For ease of description, each ofFIGS.6through13are broken into 5 views. Each of the numbered views, the views without an appended letter (e.g.,FIG.6), show a view looking down the third direction40(Z-axis) at a plane formed by the first direction20(X-axis) and second direction30(Y-axis). Each of the ‘A’ views (e.g.,FIG.6A) and ‘B’ views (e.g.,FIG.6B) show the electronic device looking along the second direction30(Y-axis) at a plane formed by the first direction20(X-axis) and third direction40(Z-axis). The ‘A’ views are a slice of the device of the corresponding numbered view taken along line A-A. The ‘B’ views are a slice of the device of the corresponding numbered view taken along line B-B. The ‘C’ views (e.g.,FIG.6C) and ‘D’ views (e.g.,FIG.6D) show the electronic device viewed along the first direction20(X-axis) at a plane formed by the second direction30(Y-axis) and third direction40(Z-axis). The ‘C’ views are a slice of the device of the corresponding numbered view taken along line C-C. The ‘D’ views are a slice of the device of the corresponding numbered view taken along line D-D. Each ofFIGS.14-19shows a view of the electronic device similar to the ‘B’ views ofFIGS.6-13. The illustration inFIGS.14-19show a slice of the electronic device looking along the second direction30(Y-axis) at a plane formed by the first direction20(X-axis) and third direction40(Z-axis).

FIG.5shows a substrate200with a stack201of layers formed thereon. The layers of the stack201are formed generally in the plane formed by the first direction (X-axis) and the second direction (Y-axis) with a thickness (shown from top to bottom of the printed page) along the third direction (Z-axis), and each layer is at a greater height along the third direction40(Z-axis) than the layer below.

The stack201of layers illustrated comprises sacrificial layers202alternating with channel layers204and insulator layers206. In the illustrated embodiment, each of the channel layers204is sandwiched between sacrificial layers202. During the process, the active region115will be located where the channel layers204are and the sacrificial layers202will be replaced with word lines125made up of conductive layers120and bridges130. With a sacrificial layer202above and below the channel layers204, there will be word lines125both above and below the active region125, as shown inFIG.3. If the channel layers204only had a sacrificial layer202below the active region115, there would be one word line formed below the active region115, as shown inFIG.4.

FIGS.6and6A-6Dillustrate the electronic device after patterning the stack201to form an isolated film stack260and a pair of pre-bridge stacks261. The isolated film stack260extends along the first direction20(X-axis) as shown inFIGS.6,6B and6D. As used in this manner, the term “extends along” means that the longer axis of the stated component is the stated axis or direction. For example, extending along the first direction means that the component has a longer axis in the X-direction. For a stack of films, the longer axis is considered for an individual film, not the entire stack of films which could be much larger than the eight layers illustrated.

The pre-bridge stacks261are formed on either or both sides265of the isolated film stack260and extend along the second direction30(Y-axis). The pre-bridge stacks261create an opening263between the pre-bridge stacks261and openings264outside the pre-bridge stacks261, along the first direction20(X-axis). The openings264form a gap along the second direction30(Y-axis) between the isolated film stack260and an adjacent isolated film stack.

Patterning can be done by any suitable technique known to the skilled artisan. For example, in some embodiments, patterning the stack201comprises forming a patterned hard mask (not shown) on the top of the stack201, followed by etching the film stack201(e.g., by an anisotropic etch) through openings in the patterned hard mask. The top view illustrated inFIG.6shows the device after etching leaving a pattern262in the insulator layer206. The patterned hard mask of some embodiments is a negative of the pattern formed so that open areas in the hard mask result in removal of the film stack.

The pair of film stacks261are separated along the first direction20(X-axis) to create an opening263between the pair of film stacks261. In some embodiments, the patterning process creates openings264outside the pair of films stacks261. The skilled artisan will recognize that the illustrated process isolates the pair of film stacks261in the first direction20(X-axis). The width of the film stacks261, along the first direction20(X-axis) of some embodiments is about the same as the width of the bridges160. The distance between the pair of film stacks261, which is the width along the first direction20of the opening261, is the distance between bridges160, along the first direction20.

FIGS.7and7A-7Dillustrate the electronic device after removal of the channel layer204from the pre-bridge stacks261and recessing the channel layer204into the isolated film stack260to form recessed channel layers270in the isolated film stack260. The removal process occurs through opening263and openings264and leaves an opening271where the channel layers204were removed. The channel layer204can be removed by any suitable technique known to the skilled artisan. In some embodiments, removal of the channel layer204is done by a dry process or oxidation process.FIG.7Ashows that the etch process removes the channel layers204from the pre-bridge stacks261to form openings271in the pre-bridge stacks261.FIGS.7C and7Dshow that the etch process removes a portion of the channel layers204to form recessed channel layers270in the sides265of the isolated film stack260with openings271. The sides265of the isolated film stack260are shown inFIG.7Das dotted lines. The center portion of the isolated film stack260shown inFIG.7Bis unchanged.

The process of recessing the channel layer204forms the inner edge of the active region115, as shown inFIG.3. As used in this manner, the term “inner edge” means the edge of the active region closest to the bit line170along the first direction20. The term “outer edge” means the edge of the active region115furthest from the bit line170along the first direction. The distance between the inner edge and outer edge of the active region115is the length of the active region115.

FIGS.8and8A-8Dillustrate the electronic device after filling the openings264,265,271with a dielectric material280. In some embodiments, the dielectric material is an oxide fill. The dielectric material280(also referred to as the oxide fill) is deposited through openings264,265, filling fill opening271. In some embodiments, the dielectric material280is deposited with an overburden and then planarized such that the dielectric material is substantially coplanar with the top surface of the isolated film stack260. In one or more embodiments, the oxide fill comprises one or more of oxides, carbon doped oxides, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon oxide (SiO), silicon nitride (SiN), silicon oxide/silicon nitride, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH). The dielectric material280may be deposited by any technique known to one of skill in the art, including, but not limited to, atomic layer deposition or chemical vapor deposition.

FIGS.9and9A-9Dillustrate the electronic device after forming a trench290in the isolated film stack260. The trench290is formed along the second direction30(Y-axis) and is positioned between the pair of pre-bridge stacks261, along the first direction20. The trench290separates the isolated film stack260into two isolated film stack sections260a,260b. In the following descriptions, the isolated film stack260is used to describe both isolated film stack sections260a,260bunless otherwise specifically stated. Ultimately, the bit line170will be formed in the trench290so that two unit cells105are formed. The trench290can be formed by any suitable technique known to the skilled artisan. For example, in some embodiments, a patterned mask is applied followed by etching.

The C-C line illustrated inFIGS.10through13is different than those ofFIGS.6through9. The portion illustrated inFIGS.6through9remains unchanged in the processes described inFIGS.10through13.FIGS.10and10A-10Dillustrate the electronic device after removing a portion of the sacrificial layer202from the isolated film stack260. The sacrificial layer202is removed through the trench290to form a recessed sacrificial layer300. Recessing the sacrificial layer202to form the recessed sacrificial layer300exposes at least one surface301and an end face303of the recessed channel layers270. In the illustrated embodiment, the recessed channel layer270has two surfaces301,302and the end face303. When the sacrificial layer202is recessed, the surface305of the sacrificial layer202moves away from the trench290in the first direction20and forms a word line opening304. The word line opening304is bounded by the surface305of the recessed sacrificial layer300, the surfaces301,302of the recessed channel layer270and the trench290. The sacrificial layer202can be recessed by any suitable technique known to the skilled artisan.

FIGS.11and11A-11Dillustrate the electronic device after forming a gate oxide layer140in the word line opening304. The gate oxide layer140is deposited through the trench290by any suitable technique known to the skilled artisan. The illustrated embodiment shows the gate oxide layer140as a conformal layer with a uniform shape. However, the skilled artisan will recognize that this is merely for illustrative purposes and that the gate oxide layer140can form in an isotropic manner so that the gate oxide layer140has a rounded appearance. In some embodiments, the gate oxide layer140is selectively deposited as a conformal layer on the surface of the recessed channel layer270. The gate oxide layer140of some embodiments forms on the end surface303of the recessed channel layer270. In some embodiments, the gate oxide layer140formed on the end surface271is removed by an anisotropic etch process to expose the end surface303and leave the gate oxide layer140on the surfaces301,302. In some embodiments, the gate oxide140is formed by oxidation of the semiconductor surface.

In one or more embodiments, the gate oxide layer140comprises a gate oxide material. In one or more embodiments, the gate oxide layer140comprises one or more of silicon oxynitride (SiON), silicon oxide, or a high-K dielectric material. While the term “silicon oxide” may be used to describe the gate oxide layer140, the skilled artisan will recognize that the disclosure is not restricted to a particular stoichiometry. For example, the terms “silicon oxide” and “silicon dioxide” may both be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. The same is true for the other materials listed in this disclosure, e.g. silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, and the like.

FIGS.12and12A-12Dillustrate the electronic device after depositing an optional liner325and a conductive layer120in the word line opening304. The conductive layer120has an outer end121and an inner end122that is closer to the trench290than the outer end121. The conductive layer120forms a word line and bridges130in the electronic device on the gate oxide layers140. The illustrated embodiment shows the optional liner325as a conformal layer with a uniform shape. However, the skilled artisan will recognize that this is merely for illustrative purposes and that the optional liner325can form in an isotropic manner. The cross sectional view ofFIGS.12A and12Dillustrates the bridges130and the view ofFIGS.12B and12Cillustrates the conductive layers120.

In one or more embodiments, the word line metal112comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). The conductive layer120(word line metal) is deposited using any one of a number of methods known to one of skill in the art, including, but not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the bridge section (shown inFIG.12D) is filled with the word line metal.

“Atomic layer deposition” or “cyclical deposition” as used herein refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or portion of the substrate, is exposed separately to the two or more reactive compounds which are introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere and/or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface, or material on the substrate surface, are exposed simultaneously to the two or more reactive compounds so that any given point on the substrate is substantially not exposed to more than one reactive compound simultaneously. As used in this specification and the appended claims, the term “substantially” used in this respect means, as will be understood by those skilled in the art, that there is the possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and that the simultaneous exposure is unintended.

In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g. aluminum precursor) is pulsed into the reaction zone followed by a first time delay. Next, a second precursor or compound B (e.g. oxidant) is pulsed into the reaction zone followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compound or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process so that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive compounds are alternatively pulsed until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B and purge gas is a cycle. A cycle can start with either compound A or compound B and continue the respective order of the cycle until achieving a film with the predetermined thickness.

In an embodiment of a spatial ALD process, a first reactive gas and second reactive gas (e.g., nitrogen gas) are delivered simultaneously to the reaction zone but are separated by an inert gas curtain and/or a vacuum curtain. The substrate is moved relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

As used herein, “chemical vapor deposition” refers to a process in which a substrate surface is exposed to precursors and/or co-reagents simultaneous or substantially simultaneously. As used herein, “substantially simultaneously” refers to either co-flow or where there is overlap for a majority of exposures of the precursors.

Plasma enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to cost efficiency and film property versatility. In a PECVD process, for example, a hydrocarbon source, such as a gas-phase hydrocarbon or a vapor of a liquid-phase hydrocarbon that have been entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiated gas, typically helium, is also introduced into the chamber. Plasma is then initiated in the chamber to create excited CH-radicals. The excited CH-radicals are chemically bound to the surface of a substrate positioned in the chamber, forming the desired film thereon. Embodiments described herein in reference to a PECVD process can be carried out using any suitable thin film deposition system. Any apparatus description described herein is illustrative and should not be construed or interpreted as limiting the scope of the embodiments described herein.

FIGS.13and13A-13Dillustrate the electronic device after filling the trench290with a dielectric230. In some embodiments, the dielectric230forms an electrical boundary on the inner side of the word line. The dielectric material is deposited using any one of a number of methods known to one of skill in the art, including, but not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The dielectric material can be the same composition as any of the other insulating materials in the electronic device. In some embodiments, the dielectric230is the same material as dielectric material280. In some embodiments, the dielectric230is etch selective relative to the dielectric material280. In some embodiments, prior to filling the trench with dielectric230, the inner end of the recessed channel layer270is doped to form a source/drain region119.

Each ofFIGS.14-19shows a view of the electronic device taken along line B-B ofFIG.13. Each of these Figures is a view along the second direction30at a slice taken in a plane formed by the first direction20and the third direction40.FIG.14illustrates the electronic device after forming a slit pattern340through the recessed sacrificial layer300and the recessed channel layer270to form the slit pattern340. The slit pattern340is formed on the opposite sides of the location where the trench290was filled with dielectric230. As used in this manner, “opposite sides” means that one slit is formed to one side of the dielectric230in the first direction20and the other slit is formed on the other side of the dielectric230in the first direction20. The slit pattern340is formed outside of the conductive layer120formed in the word line opening. As used in this manner, the term “outside of” means that the slit pattern340is formed on an opposite side of the conductive layer120than the dielectric230. In the illustration ofFIG.14, the dielectric230is in the center of the drawing, the conductive layers120are to the left and right of the dielectric230and the slit patterns340are on the left edge and right edge of the drawing; opposite sides of the dielectric230and outside of the conductive layers120. The slit pattern340exposes the sidewall346of the recessed channel layer270and the sidewall342of the recessed sacrificial layer300.

FIG.15shows the electronic device after a portion of the recessed channel layer270is removed through the slit pattern340to move the sidewall346of the recessed channel layer270toward the conductive layer120. This process recesses the recessed channel layer270from the slit pattern340side. The portion of the recessed channel layer270can be removed by any suitable technique known to the skilled artisan. Removing the portion of the recessed channel layer270forms the active region115and a capacitor opening350. The active region115has an outer end116adjacent the capacitor opening350and an inner end118adjacent the dielectric230. This process may also be referred to as a “pull back” process. In one or more embodiments, the channel layer270comprises poly-silicon and the process shown inFIG.15is a poly-silicon pull back.

FIG.16shows the electronic device after an optional gas phase doping process. The gas phase doping process forms a doped layer117on the outer edge of the active region115. In some embodiments, doping is performed during deposition of the active region material using a dopant source. For example, a phosphorous doped silica glass (PSG) or boron phosphorous doped glass (BPSG) and diffused into the material. In some embodiments, the doped layer117is in the range of 1 to 20 nm thick (measured from the outer edge of the active region115toward the bit line).

FIG.17shows an expanded view of region17ofFIG.16showing the capacitor opening350. As shown inFIG.18, in some embodiments, a capacitor180is formed in the capacitor opening350adjacent the recessed channel layer115. In some embodiments, the capacitor180is formed by first depositing a lower electrode186in the capacitor opening350. The lower electrode186, also referred to as a bottom electrode or bottom contact, can be formed by any suitable technique known to the skilled artisan. In some embodiments, the lower electrode186is a conformal film deposited by atomic layer deposition. In one or more embodiments, the lower electrode186comprises a material selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In some embodiments, the capacitor comprises a bottom electrode, a capacitor dielectric and a top electrode. In some embodiments, the capacitor comprises a double layer. For example, the top electrode and a titanium nitride plus silicon germanium double layer.

A high-K dielectric184is deposited on the lower electrode186within the capacitor opening350. The high-K dielectric184of some embodiments comprises hafnium oxide. In some embodiments, the high-K dielectric184is deposited as a conformal film by atomic layer deposition. A top electrode182is formed in the capacitor opening350within the high-K dielectric184. The top electrode182, also referred to as a top contact or upper electrode, can be formed by any suitable technique known to the skilled artisan. In one or more embodiments, the top electrode182comprises a conductive material comprising one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). in some embodiments, a dielectric188is deposited to fill any open space remaining in the capacitor opening350after formation of the top electrode182. The dielectric188of some embodiments separates the individual unit cells from adjacent unit cells to prevent shorting.

FIG.19illustrates region17of another embodiment of the disclosure in which the capacitor opening350is widened prior to forming the capacitor to create a widened capacitor opening351. The capacitor opening350can be widened by any suitable technique known to the skilled artisan. After the capacitor opening350has been widened, a capacitor180is formed within, as shown inFIG.20. The capacitor opening of some embodiments is widened by a percentage of a thickness of the isolation layer (layer between active regions). In some embodiments, the capacitor is widened by an amount in the range of 10% to 80% of the thickness of the isolation layer (measured as the combination of top and bottom widening). In some embodiments, the capacitor is widened by an amount in the range of 20% to 75%, or in the range of 30% to 60%. The capacitor opening350of some embodiments is widened in the second direction30(Y-axis) and the third direction40(Z-axis). In some embodiments, the capacitor opening350is widened using a dilute HF (˜1% HF in water) wet etch. In some embodiments, widening the capacitor opening results in an increase in capacitor surface area in the range of 1% to 85%, or in the range of 5% to 80%, or in the range of 10% to 75%, or in the range of 20% to 60%.

FIG.21illustrates a partial view of region21ofFIG.16.FIG.22shows the electronic device after forming a bit line hole360(also referred to as a bit line opening) between the recessed channel layers that form the active region115. In some embodiments, the electronic device is patterned to form the plurality of bit line holes360. The bit line hole360can be formed by any suitable process known to the skilled artisan. In some embodiments, the bit line hole360is formed by positioned a patterned hard mask and etching the dielectric230through the hard mask.

In the illustrated embodiment, a source/drain region119is formed on the inner end of the active region115. In some embodiments, the source/drain region119is formed by exposing the end face303to a dopant gas. The source/drain region119can be formed by any suitable technique known to the skilled artisan.

FIG.22illustrates the partial view of region21ofFIG.16after depositing a bit line365in the bit line hole360. In the illustrated embodiment, the bit line365includes an optional bit line liner370(also referred to as a bit line barrier layer) and a bit line metal375.

The optional bit line liner370can be made of any suitable material deposited by any suitable technique known to the skilled artisan. In some embodiments, the bit line liner370is conformally deposited in the plurality of bit line holes360and deposited on an exposed surface of the dielectric231and the end face303(or exposed surface) of the active material115. In the illustrated embodiment, the bit line liner370is deposited on the source/drain region119at the inner end of the active material115. The bit line liner370can be any suitable material including, but not limited to, titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the optional bit line liner370comprises or consists essentially of titanium nitride (TiN). As used in this manner, the term “consists essentially of” means that the composition of the film is greater than or equal to about 95%, 98%, 99% or 99.5% of the stated species. In some embodiments, the optional bit line liner370comprises or consists essentially of tantalum nitride (TaN). In some embodiments, the bit line liner370is a conformal layer. In some embodiments, the bit line liner370is deposited by atomic layer deposition.

In some embodiments, the bit line metal375comprises or consists essentially of one or more of tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W). The bit line metal375can be deposited by any suitable technique known to the skilled artisan and can be any suitable material. In one or more embodiments, forming the bit line metal375further comprises forming a bit line metal seed layer (not shown) prior to depositing the bit line metal375.

Some embodiments of the disclosure are directed to electronic devices incorporating an etch stop layer (ESL) for improved process controls.FIGS.24through33show cross-sectional schematic views of an electronic device similar to that illustrated inFIG.3. The skilled artisan will recognize the similarities between the process described inFIGS.26-33with the process described inFIGS.5-23. The view ofFIG.24is taken along the second direction30(Y-axis) looking at a plane formed by the first direction20(X-axis) and third direction40(Z-axis).FIG.25shows an expanded view of region25fromFIG.24.

In the illustrated embodiment, an etch stop layer410is adjacent to the outer end116of the active region115. The etch stop layer410is adjacent to the lower electrode186of the capacitor along the third direction40(Z-axis) and adjacent to the outer end116of the active region115along the third direction40(Z-axis). The etch stop layer410of some embodiments is adjacent the doped layer117along the third direction40(Z-axis) and the outer end116of the active region115along the third direction40(Z-axis). In some embodiments, the etch stop layer410is adjacent the doped layer117and the lower electrode186of the capacitor along the third direction40(Z-axis). In some embodiments, the etch stop layer410is substantially absent from a region between the outer end116of the active region115(and/or the doped region117) and the capacitor186, along the first direction20. As used in this manner, the term “substantially absent” means that the etch stop layer410occupies less than 25%, 20%, 10% or 5% of the area between the active region115and the lower electrode186along the first direction20(X-axis).

One or more embodiments of the disclosure are directed to methods of manufacturing the electronic device ofFIG.24.FIG.26shows an embodiment of the electronic device in which a trench290has been formed through a stack of alternating sacrificial layers202and replacement channel layers420. The replacement channels420of some embodiments are the same material as the channel layers204shown inFIGS.5-23. In some embodiments, the replacement channel layers420are a different material than the channel layers204shown inFIGS.5-23. The material of the replacement channel layers420does not affect the process flow described.

After forming the trench290, as shown inFIG.26, the replacement channel layers420are recessed to form recessed replacement channel layers420as shown and opening425between adjacent sacrificial layers202(if there are two) in the third direction40(Z-axis). The replacement channel layers are recessed to a depth sufficient to form an active material of a predetermined length in the final electronic device. In the illustrated embodiment, the opening425is bounded along the first direction20(X-axis) by the inner end422of the recessed replacement channel layers420and the trench290, and bounded along the third direction40(Z-axis) by the exposed surfaces203of the sacrificial layers202above and below.

After forming the openings425, as shown inFIG.27, an etch stop layer410is formed on the exposed sacrificial surfaces203of the sacrificial layers202and the inner end422of the recessed replacement channel layers420. A portion432of the etch stop layer410is on the surface203of the sacrificial layer202, and an end wall411of the etch stop layer410is formed on the inner end422of the recessed replacement channel layers420. The opening425remains and is bounded by the etch stop layer410. The size of the opening425of some embodiments, increases, decreases or remains the same after forming the etch stop layer410. The etch stop layer410can be any suitable material formed by any suitable process known to the skilled artisan. The etch stop layer410of some embodiments is a material that is etch selective relative to the sacrificial layers202and the replacement channel layers420. In some embodiments, the etch stop layer410is a conformal film deposited by atomic layer deposition.

In some embodiments, the opening425is widened by any suitable technique known to the skilled artisan before depositing the etch stop layer410. The size of the opening425can be tuned to provide an active material115with predetermined dimensions.

FIG.28shows the electronic device ofFIG.27after depositing an active material115within the opening425within the etch stop layer410. The active material115forms a pair of channel layers204on opposite sides of the trench290along the first direction20(X-axis).

FIG.29shows the electronic device ofFIG.28after removing a portion of the sacrificial layer202to form a recessed sacrificial layer300, similar to that shown inFIG.10B.

In some embodiments, the sacrificial layer202is recessed to a depth less than the depth that the replacement channel layers420were recessed to prior to forming the etch stop layer410. In some embodiments, the sacrificial layer202is recessed to a depth less than the depth sufficient so that the end wall411portion of the etch stop layer410on the surface422of the recessed replacement channel layer420is not exposed. In some embodiments, the surface305of the recessed sacrificial layer300is in the range of 5 nm to 20 nm closer to the trench290than the end wall411of the etch stop layer410, along the first direction20(X-axis). In some embodiments, the surface305of the recessed sacrificial layer300is in the range of 5 nm to 20 nm closer to the trench290than the outer end116of the active material115, along the first direction20(X-axis).

In some embodiments, as shown inFIG.29, a portion432of the etch stop layer410on the surface203of the sacrificial layer202is removed. In some embodiments, the portion432of the etch stop layer410is removed at the same time as recessing the sacrificial layer202to form the recessed sacrificial layer300. In some embodiments, removing the portion432of the etch stop layer410is done separately from recessing the sacrificial layer202so that the recessed sacrificial layer300is formed followed by removal of the portion432of the etch stop layer410.

FIG.30shows the electronic device ofFIG.29after forming the gate oxide140on the active material115, forming the optional liner325in the opening435formed with the recessed sacrificial layer300, and forming the conductive layer120within the optional liner325.

FIG.31shows the electronic device ofFIG.30after filling trench290with dielectric230, forming a slit pattern340and removing the replacement channel layers420through the slit pattern340, in one or more processes similar to that described with respect toFIGS.13-16. After removing the replacement channel layers420, capacitor opening350is formed. The inner end352of the capacitor opening350(end furthest from the slit pattern) is bounded by the end wall431of the etch stop layer410.

FIG.32shows the electronic device ofFIG.31after removing the end wall411of the etch stop layer410from the inner end352of the capacitor opening350. Removing the etch stop layer410exposes the outer end116of the active material115. In some embodiments, portions of the etch stop layer410remain above and below (relative to the third direction40) the inner end352of the capacitor opening350. In some embodiments, portions of the etch stop layer410straddle the interface between the outer end116of the active material115and the capacitor opening350.

FIG.33shows the electronic device ofFIG.32after doping the outer end116of the active material115through capacitor opening350to form the doped layer117. The process of some embodiments proceeds as illustrated and described with respect toFIGS.16through23, with the etch stop layer410remaining in the final device, as shown inFIG.24. In some embodiments, the capacitor opening350is widened similarly to that discussed with respect toFIGS.19and20.

FIG.34shows an electronic device500according to one or more embodiment of the disclosure. The device500is similar to the device ofFIG.3with the addition of an etch stop material410form along the third direction40(Z-axis). The etch stop material410extends through the device500at a position equivalent to the inner end352of the capacitor opening350. The etch stop material410of some embodiments comprises a dielectric material to prevent electrical shorting. The etch stop material410passes through the insulator layers206and recessed sacrificial layer300. In some embodiments, the etch stop material410interrupts the continuity of the insulator layers206and recessed sacrificial layer300along the first direction20(X-axis).

Some embodiments of the disclosure are directed to methods of forming the electronic device500.FIGS.35-39provide cross-sectional views illustrating a method according to one or more embodiment. The process of forming the device500is similar to that illustrated inFIGS.5-23and several points along the process are illustrated to point out the differences.

FIG.35shows a stack of films similar to that ofFIG.5with an etch stop layer (ESL) opening405formed through the stack along the third direction40(Z-axis). The ESL opening405is filled with an etch stop material410. The etch stop material410can be any suitable material deposited by any suitable technique known to the skilled artisan. In some embodiments, as shown in the Figures, the ESL opening405is formed on opposite sides, in the first direction20(X-axis), of the point where the trench290will be formed.

FIG.36shows the electronic device ofFIG.35after processes analogous to those ofFIGS.9,9A-9D,10and10A-10D. The trench290of some embodiments is formed about midway between two ESL openings405, along the first direction20(X-axis).

The sacrificial layer202is etched to form the recessed sacrificial layer300. In some embodiments, the etch process moves the surface305of the recessed sacrificial layer300away from the trench290by a distance less than the distance from the trench290to the ESL opening405. In some embodiments, the etch process moves the surface305to the etch stop material410.

FIG.37shows the electronic device ofFIG.36after processes analogous to those ofFIGS.11-13(including the A-D subfigures). The conductive layer120, optional liner325, gate oxide140and dielectric230are formed. The illustrated embodiment also includes formation of the source/drain region119on the inner end of the active material115.

FIG.38shows the electronic device ofFIG.37after processes analogous to those ofFIGS.14-16(including the A-D subfigures). Slit patterning340and etching processes create the capacitor opening350. The sidewall346of the recessed channel layer, which is the inner wall of the capacitor opening350, is moved to the etch stop material410in the ESL opening405.

FIG.39shows the electronic device ofFIG.38after removing the etch stop material410through the capacitor opening350. The outer end116of the active material115is optionally doped to form the doped region119. The process flow of some embodiments concludes with formation of the capacitor following analogous processes to those described inFIGS.17-20, and bit line375following analogous processes to those described inFIGS.21-23.