Multirate communication apparatus and method of controlling line-configuration of multirate communication apparatus

There is provided the multirate communication apparatus including: an interface board to connect with a plurality of lines of different bit rates and processing transmission signals of the lines having a first line capacity; a port to mount a transmission module to transmit and receive the transmission signals; a line identifying unit to identify a line type of the transmission module mounted in the port; a plurality of signal processor to process transmission signals having a second line capacity obtained by dividing the first line capacity by a predetermined number; and a line-configuration controller to control a configuration of lines processed in respective the signal processor, based on an identification result of the line identifying unit; wherein the signal processor processes the transmission signals in accordance with the line type of the transmission module mounted in the port, base on a control by the line-configuration controller.

FIELD

The embodiments discussed herein are related to a multirate communication apparatus and a method of controlling line-configuration of the multirate communication apparatus. The multirate communication apparatus is one of a multi service provisioning platform (MSPP) apparatus that processes data of a plurality of types, such as synchronous optical network/synchronous digital hierarchy (SONET/SDH) data and Ethernet data.

BACKGROUND

Networks have been changed in that subscribers use broadband networks and services are diversified. Networks that transfer signals from various access networks accommodating subscriber lines have changed from SONET/SDH networks to Internet protocol (IP) networks. MSPP apparatuses corresponding to such diversified services have been developed.

In some cases, an MSPP apparatus is required to process signals transmitted using different protocols. As a solution for such a case, a technique is used in which a SONET/SDH frame is used and asynchronous transfer mode (ATM) signals, plesiochronous digital hierarchy (PDH) signals, and Ethernet signals are multiplexed in the payload section of the frame based on SONET/SDH (for example, refer to Japanese Laid-open Patent Publication No. 2001-186188).

There is a configuration of an MSPP apparatus including interface boards that individually interface with lines corresponding to respective services using, for example, SONET/SDH, Ethernet, and PDH, so as to provide multiservice. With such a configuration, in general, each of the interface boards is provided in advance with circuits (such as photoelectrical conversion circuits and signal termination circuits) that process signals corresponding to the bit rate of the lines accommodated. Therefore, in order to accommodate lines of a bit rate different from the lines having been accommodated after an apparatus is operated, it is necessary to replace the interface board.

Small form factor (SFF) and small form factor pluggable (SFP) which is a related technique to SFF have been developed to facilitate size reduction and standardization of transmission modules such as optical transceivers that transmit and receive signals (optical signals) from the above-mentioned access networks or the like. Communication device manufacturers and communication companies played a central role in establishing SFF in order to carry out size reduction and standardization of transmission modules. SFP has been established to produce pluggable transmission modules that conform to SFF.

Recently, transmission modules conforming to SFP are used in MSPP apparatuses, and thus, it is easy to change the bit rate of a line connected to a port of an interface board. Accordingly, there is an increasing need for an MSPP apparatus capable of mounting a transmission module conforming to SFP and accommodating lines of different bit rates in one port. The transmission modules mentioned hereinafter are transmission modules conforming to SFP.

SUMMARY

According to an aspect of the embodiment, there is provided a multirate communication apparatus including an interface board to connect with a plurality of lines of different bit rates and processing transmission signals of the lines having a first line capacity; a port to mount a transmission module to transmit and receive the transmission signals; a line identifying unit to identify a line type of the transmission module mounted in the port; a plurality of signal processor to process transmission signals having a second line capacity obtained by dividing the first line capacity by a predetermined number; and a line-configuration controller to control a configuration of lines processed in respective the signal processor, based on an identification result of the line identifying unit; wherein the signal processor processes the transmission signals in accordance with the line type of the transmission module mounted in the port, base on a control by the line-configuration controller.

DESCRIPTION OF EMBODIMENTS

An MSPP apparatus accommodated in a SONET/SDH network is required to be able to accommodate and process lines of different bit rates at one port. However, an interface board that includes a plurality of ports and processes a plurality of line signals has a limitation on the capacity of signals interfaced to other boards in the apparatus. In addition, a signal processor that is provided on the interface board and processes the line signals is required to include circuits that process line signals of a plurality of types. Furthermore, physical limitations on the interface board, for example, the limitation on the mounting area for a signal processor depending on the board size and the limitation on the number of ports that are mounted, cause limitations on the type and number of line signals to be accommodated in a signal processor that generates capacity-limited interface signals. There is also a limitation on the number of signal processors mounted on the interface board. Thus, for the capacity-limited signal processors mounted on the interface board, it becomes an issue to efficiently accommodate line capacity on the basis of the bit rate of the lines to be processed and the number of lines, and to cope with lines of different bit rates.

Details of embodiments will be described below with reference to the accompanying drawings. The same or similar components in the drawings will be represented by the same reference numerals.

FIG. 1is a diagram illustrating, in outline, a multirate communication apparatus. Reference numeral1represents a multirate communication apparatus. For example, the multirate communication apparatus1has a shelf structure as the apparatus structure, and has a structure that allows a plurality of interface boards101to10n(reference numeral100is used to represent the interface boards collectively), which accommodate lines and process transmission signals of the line (it may be referred to as line signals), and a common-part board200, which processes various common signals of the apparatus, to be implemented. Although not illustrated in the drawings, a back wiring board that connects the signals from the interface board100and the common part board200is provided.

For example, the processing capability of the interface board100for processing line signals is equivalent to the line capacity of synchronous transport signal level 192 (STS-192), and four lines (4▪ STS-48) of optical carrier level 48 (OC-48) each having a bit rate of 2.4 Gbps are accommodated. The line signals terminated at the interface board100are added and dropped at the common part board200in units of predetermined channels (for example, STS-1) and are transferred from the interface board100. Since the number of signal lines connecting the common part board200and the interface board100and the signal rate are restricted, the interface board100is interfaced to the common part board200in STS-48 units via the back wiring board. Thus, the interface board100having a line capacity equivalent to STS-192 processes transmission signals using four signal processors in which a line capacity equivalent to STS-48 is set as a processor. The interface board100includes ports30that connect with the lines. The number of ports30that are mounted on the interface board100is limited on the basis of the size relationship between the interface board100and the ports30. When the lines are connected to the port30, transmission modules60, which terminate the signals transmitted through the lines, are mounted on the ports30. The transmission module60is a plug-in type and is mounted by being inserted into the port30. Although transmission cables are connected to the transmission modules60, these are not illustrated in the drawings. The opposite transmission apparatus and so on are connected via the transmission cables. Since the number of ports mounted on the interface board100is limited, the line capacity processed at the interface board100differs depending on the bit rate (line speed) of the transmission modules60mounted in the ports30.

Typically, the interface board100includes a signal processing circuit that processes line signals corresponding to the bit rate (line speed) of the transmission module60mounted in the port30. The four signal processors that each process the line capacity equivalent to STS-192 in line capacity units equivalent to STS-48 are equipped with signal processing circuits that correspond, in advance, to the type of the lines depending on the combinations of the type of the lines (for example, OC-48, OC-12, or OC-3) processed by the signal processor and number of lines (number of ports). In the interface board100, the ports connecting with the lines processed by the four signal processors and the respective signal processors are grouped (Groups A, B, C, and D). Below, the combinations of the type and number of line processed by these groups will be referred to as group configurations.

First Embodiment

As an example of improving the accommodation efficiency of the line signals of the interface board100, the bit rate (line speed) of the transmission module60mounted in the reference port among the plurality of ports30is detected, and a group configuration of the interface board100is selected from the types defined in advance (Types 1, 2, and 3, which will be described in detail below). Depending on the selected type, the line signals from the ports30are controlled such as to be connected to any one of the signal processors.

FIG. 2is a diagram illustrating, in outline, the interface board. Reference numerals31to312represent ports (reference numeral30is used to represent the ports collectively). Reference numeral41represents a line switch. Reference numerals51to54represent signal processors (reference numeral50is used to represent the signal processors collectively). Reference numerals61to612represent transmission modules (reference numeral60is used to represent the transmission modules collectively), and optical cables are connected to each transmission module. Reference numeral71represents a line identifying unit, and reference numeral72represents a line-configuration controller. The number of ports30and the number of signal processors50are determined on the basis of the function of the interface board100and are not limited to those in the embodiment.

The interface board100is capable of processing signals of, for example, a line capacity of STS-192. Then, according to the inter-board interface condition of the back wiring board of the multirate communication apparatus1and the condition of the signal processing of the common-part board200, the interface board100divides the processing of the line capacity of STS-192 into four groups (Groups A, B, C, and D) according to the line capacity of STS-48, and processes the line signals equivalent to STS-48 at each of the signal processors51,52,53, and54.

FIG. 2indicates the interface board100mounted on the multirate communication apparatus1in an operating state. Illustrated is a case in which the bit rate of the transmission module61mounted in the reference port (port31) is detected, and Type 1 (which is described in detail below) is selected as the group configuration since the bit rate is determined as 2.4 Gbps. The relationships between the signal processors51to54and the ports31to312in Type 1 are indicated as Groups A, B, C, and D. Groups A, B, C, and D are, respectively, a group of ports31accommodating the line signals processed by the signal processor51, a group of ports32accommodating the line signals processed by the signal processor52, a group of ports33to36(not illustrated) accommodating the line signals processed by the signal processor53, and a group of ports37to312accommodating the line signals processed by the signal processor54.

The line identifying unit71determines the type, for example, bit rate, of the transmission module mounted in the port30. Product identification information, which is referred to as a physical inventory, such as the product name, product figure number, manufacturer's number, of the transmission module is stored in the transmission module60. The line identifying unit71identifies the type of the transmission module by reading out the physical inventory of the transmission module60.

The line-configuration controller72selects the group configuration of the interface board100among the types (Types 1, 2, or 3) provided in advance on the basis of the type of the transmission module61mounted in the reference port, for example, port31. The line switch41is controlled according to the selected type in order to configure the ports assigned to the group. On the basis of the type (bit rate) of the transmission module identified by the line identifying unit71, the signal processing circuit of the signal processor50is controlled to be adapted to the type of the transmission module mounted in the corresponding port. For example, if the bit rate of the transmission module61of the port31is 2.4 Gbps (OC-48), the line-configuration controller72controls the signal processor51such that the signal from the port31transmitted via the line switch41is processed at the STS-48 signal processing circuit. Since the bit rate of the transmission module61of the port31is, 2.4 Gbps (OC-48), control is carried out such that Type 1 is selected for the group configuration (which will be described in detail below), and port31is assigned to Group A, port32to Group B, ports33(to36) to Group C, and ports37to312to Group D. The signal processor51of Group A, the signal processor52of Group B, the signal processor53of Group C, and the signal processor54of Group D each process signals of a line capacity equivalent to STS-48.

Furthermore, to describe the interface board100, the type of the line accommodated in the port30is presumed to be as follows. (Details will be described below. The presumed case, however, is that the group configuration is Pattern P13inFIG. 7.) In other words, OC-48 is accommodated in Groups A and B respectively, OC-12 is accommodated in Group C, and OC-3 is accommodated in Group D, respectively. The transmission module61mounted in the port31converts the received OC-48 optical signals to STS-48 electric signals at the transmission module61. The line switching circuit41connects the STS-48 signals from the transmission module61to the signal processor51on the basis of the control by the line-configuration controller72corresponding to the above-described Type 1. STS-48 signals are terminated at the signal processing circuit for STS-48, which is included in the signal processor51, and are transferred to another board via the back wiring board. Also for the transmission module62mounted in the port32, the received OC-48 optical signals are converted to STS-48 electric signals at the transmission module62and, via the line switching circuit41, are terminated at the signal processing circuit for STS-48 included in the signal processor52. The OC-12 optical signals received at the transmission module63mounted in the port33are converted to STS-12 electric signals at the transmission module63and, via the circuit switch41, terminated at the signal processing circuit for STS-12 included in the signal processor53. The OC-3 optical signals received at the transmission module67mounted in the port37are converted to STS-3 electric signals at the transmission module67and are terminated at the signal processing circuit for STS-3, which is included in the signal processor54, via the circuit switch41.

FIG. 3is a diagram illustrating the group configurations.

At the interface board100, the number and signal speed of the signals interfacing another board (e.g., the common board200illustrated inFIG. 1) are limited. Consequently, at the signal processor50that generates these interface signals, the signal processing capacity is limited. For example, when a line capacity equivalent to STS-192 is processed at one interface board100, four signal processors50that process a line capacity equivalent to STS-48 are provided. In this case, one signal processor50is capable of processing a maximum line capacity that is equivalent to STS-48. Thus, if the lines processed at the signal processor50are STS-48, only one line is accommodated; if the line is STS-12, four lines are accommodated; and if the line is STS-3, 16 lines are accommodated. However, the limited number of ports30to be mounted causes the number of lines processed at the signal processor50to also be limited.

At one interface board100, when a plurality of line types (for example, OC-48, C-12, and OC-3) is accommodated, the combinations of the type and number of lines processed at the signal processor50are set in advance, and the signal processor50is provided with signal processing circuits capable of processing the respective type and number of lines.

The group configuration in which the combinations of the type and number of lines processed at the signal processor50is defined as one group will be described below.

For example, the interface board100is capable of processing a signal having a line capacity of STS-192 and processes line signals equivalent to STS-48 with the signal processor50, which divides the signal into four groups (Groups A, B, C, and D) in STS-48 units.

The interface board100has, for example, twelve ports30, which are referred to as ports31to312(31,32,33, -,38,39,310,311, and312).

As for the group configuration of the interface board100, four types, i.e., Type 0, Type 1, Type 2, and Type 3, will be described.

Type 0 processes the signals of the ports31to33, the ports34to36, the ports37to39, and the ports310to312in Groups A, B, C, and D, respectively.

Type 1 processes the signals of the port31, the port32, the ports33to36, and the ports37to312in Groups A, B, C, and D, respectively.

Type 2 processes the signals of the ports31to34, the ports35to37, the ports38to310, and the ports311and312in Groups A, B, C, and D, respectively.

Type 3 processes the signals of the ports31to35, the ports36to39, the ports310and311, and the port312in Groups A, B, C, and D, respectively.

FIG. 4is a diagram illustrating, in outline, the Type 0 group configuration. The circuit switch41is controlled by the line-configuration controller72such that the signals via the ports31to33are connected to the signal processor51, the signals via the ports34to36are connected to the signal processor52, the signals via the ports37to39are connected to the signal processor53, and the signals via the ports310to312are connected to the signal processor54.

Each of the signal processors51to54includes a signal processing circuit that enables processing of any one of STS-48, STS-12, and STS-3 and a signal processing circuit that enables processing of either STS-12 or STS-3, with control of the line-configuration controller72.

FIG. 5is a diagram illustrating the line accommodation of the Type 0 group configuration. For the combinations of the lines, e.g., the three types, i.e., OC-48, OC-12, and OC-3, that are processed in the interface board100, patterns of pattern types P01to P04are set in advance, and the state of the ports of the patterns is illustrated.

P01is a pattern in which OC-48 is accommodated in each of Groups A to D. Since the line processing capacity of the signal processor50is OC-48, one port in each of Groups A to D is used.

P02is a pattern in which OC-48 is accommodated in each of Groups A to C, and OC-3 is accommodated in Group D. One port in each of Groups A to C is used to accommodate OC-48, and three ports in Group D are used to accommodate OC-3.

P03is a case in which OC-48 is accommodated in each of Groups A and B, OC-12 is accommodated in Group C, and OC-3 is accommodated in Group D. One port in each of Groups A and B is used to accommodate OC-48; three ports in Group C are used to accommodate OC-12; and three ports in Group D are used to accommodate OC-3.

P04is a case in which OC-48 is accommodated in Group A, and OC-3 is accommodated in each of Groups B to D. One port in Group A is used to accommodate OC-48, and three ports in each of Groups B to D are used to accommodate OC-3.

Therefore, as for P02to P04, according to Type 0, a single group is only able to accommodate a maximum of three lines of OC-12 or OC-3, thus preventing the maximum use of the processing ability of the signal processor50. Therefore, in this embodiment, Types 1 to 3 are used.

FIG. 6is a diagram illustrating, in outline, the Type 1 group configuration. The line switch41is controlled by the line-configuration controller72to connect the signals via the port31to the signal processor51, to connect the signals via the port32to the signal processor52, to connect the signals via the ports33to36to the signal processor53, to connect the signals via the ports37to312to the signal processor54.

Each of the signal processors51and52includes a signal processing circuit that is capable of processing any one of STS-48, STS-12, and STS-3 with the control of the line-configuration controller72; the signal processor53includes a signal processing circuit that is capable of processing one of STS-48, STS-12, and STS-3 and a signal processing circuit that is capable of processing either STS-12 or STS-3, with the control of the line-configuration controller72; the signal processor54includes a signal processing circuit that is capable of processing any one of STS-48, STS-12, and STS-3, a signal processing circuit that is capable of processing either STS-12 or STS-3, and a signal processing circuit that is capable of processing STS-3 with the control of the line-configuration controller72.

FIG. 7is a diagram illustrating the line accommodation of the Type 1 group configuration. Pattern types P11to P14are set in advance as patterns for the combinations of the lines, for example, three line types, i.e., OC-48, OC-12, and OC-3, processed in the interface board100, and the state of the ports of each pattern is illustrated.

P11is a pattern in which OC-48 is accommodated in each of Groups A to D. Since the line processing capacity of the signal processor50is OC-48, one port in each of Groups A to D is used.

P12is a pattern in which OC-48 is accommodated in each of Groups A to C, and OC-3 is accommodated in Group D. One port in each of Groups A to C is used to accommodate OC-48, and six ports in Group D are used to accommodate OC-3.

P13is a case in which OC-48 is accommodated in each of Groups A and B, OC-12 is accommodated in Group C, and OC-3 is accommodated in Group D. One port in each of Groups A and B is used to accommodate OC-48; four ports in Group C are used to accommodate OC-12; and six ports in Group D are used to accommodate OC-3.

P14is a pattern in which OC-48 is accommodated in Group A, and OC-3 is accommodated in each of Groups B to D. One port in Group A is used to accommodate OC-48, and a total of 11 ports in Groups B to D is used to accommodate OC-3.

Accordingly, Type 1 is a useful configuration when it is presumed that OC-48 is accommodated in the port31or the ports31and32.

FIG. 8is a diagram illustrating, in outline, the Type 2 group configuration. The line switch41is controlled by the line-configuration controller72to connect the signals via the ports31to34to the signal processor51, to connect the signals via the ports35to37to the signal processor52, to connect the signals via the ports38to310to the signal processor53, to connect the signals via the ports311and312to the signal processor54.

Each of the signal processors51to54includes a signal processing circuit that is capable of processing any one of STS-48, STS-12, and STS-3 and a signal processing circuit that is capable of processing either STS-12 or STS-3, with the control of the line-configuration controller72.

FIG. 9is a diagram illustrating the line accommodation of the Type 2 group configuration. Pattern types P21to P24are set in advance as patterns for the combinations of the lines, for example, three line types, i.e., OC-48, OC-12, an OC-3, processed in the interface board100and the state of the ports is illustrated.

P21is a pattern in which OC-48 is accommodated in each of Groups A to D. Since the line processing capacity of the signal processor50is OC-48, one port in each of Groups A to D is used.

P22is a pattern in which OC-12 is accommodated in each of Groups A to D. Four ports in each of Group A are used to accommodate OC-12; three ports in each of Groups B and C are used to accommodate OC-12; and two ports in Group D are used to accommodate OC-12.

P23is a pattern in which OC-12 is accommodated in Group A, an OC-3 is accommodated in each of Groups B to D. Four ports in Group A are used to accommodate OC-12; three ports in each of Groups B and C are used to accommodate OC-3; and two ports in Group D are used to accommodate OC-3.

P24is a pattern in which OC-12 and OC-3 are accommodated in Group A, and OC-3 is accommodated in each of Groups B to D. One port in Group A is used to accommodate OC-12, and a total of 11 ports in Groups A to D are used to accommodate OC-3.

Accordingly, Type 2 is a useful configuration when it is presumed that OC-12 is accommodated in the port31, and OC-12 or OC-3 is accommodated in other ports.

FIG. 10is a diagram illustrating, in outline, the Type 3 group configuration. The line switch41is controlled by the line-configuration controller72to connect the signals via the ports31to35to the signal processor51, to connect the signals via the ports36to39to the signal processor52, to connect the signals via the ports310and311to the signal processor53, to connect the signals via the port312to the signal processor54.

The signal processor51includes a signal processing circuit that is capable of processing any one of STS-48, STS-12, and STS-3, a signal processing circuit that is capable of processing either STS-12 or STS-3, and signal processing circuit that is capable of processing STS-3, with the control of the line-configuration controller72; each of the signal processors52and53includes a signal processing circuit that is capable of processing any one of STS-48, STS-12, and STS-3 and a signal processing circuit that is capable of processing either STS-12 or STS-3, with the control of the line-configuration controller72; and the signal processor54includes a signal processing circuit that is capable of processing any one of STS-48, STS-12, and STS-3, with the control of the line-configuration controller72.

FIG. 11is a diagram illustrating the line accommodation of the Type 3 group configuration. Pattern types P31to P34are set in advance as patterns for the combinations of the lines, for example, three line types, i.e., OC-48, OC-12, an OC-3, processed in the interface board100, and the state of the ports is illustrated.

P31is a pattern in which OC-48 is accommodated in each of Groups A to D. Since the line processing capacity of the signal processor50is OC-48, one port in each of Groups A to D is used.

P32is a case in which OC-12 is accommodated in each of Groups A and B, and OC-3 is accommodated in each of Groups C and D. Four ports in each of Groups A and B are used to accommodate OC-12; two ports in Group C are used to accommodate OC-3; and one port in Group D is used to accommodate OC-3.

P33is a pattern in which OC-12 is accommodated in Group A, and OC-3 is accommodated in each of Groups B to D. Four ports in Group A are used to accommodate OC-12; four ports in Group B are used to accommodate OC-3; two ports in Group C are used to accommodate OC-3; and one port is used to accommodate OC-3 for Group D.

P34is a pattern in which OC-3 is accommodated in each of Groups A to D. All ports in Groups A to D are used to accommodate OC-3.

Accordingly, Type 3 is a useful configuration when it is presumed that OC-3 is accommodated in the port31, and OC-3 and OC-12 are mixed, with a larger proportion of OC-3.

As described above, by changing the group configuration of the interface board100depending on the type of the lines accommodated in the interface board100, efficiency may be improved in the aspects of the line capacity processed at the interface board and the number of lines accommodated in the interface board100.

Therefore, in order for the configurations of the signal processors50to correspond to Types 1 to 3, the signal processor51has the configuration of the signal processor51illustrated inFIG. 10, the signal processor52has the configuration of the signal processor52illustrated inFIG. 10, the signal processor53has the configuration of the signal processor53illustrated inFIG. 6, and the signal processor54has the configuration of the signal processor54illustrated inFIG. 6.

FIG. 12is a diagram illustrating, in outline, the signal processor. The configuration of the signal processor54illustrated inFIG. 6is provided for description.

Reference numeral501represents an STS-48/12/3 selecting circuit. Reference numeral502represents an STS-48 signal processing circuit, reference numeral503represents an STS-12 signal processing circuit, and reference numeral504represents an STS-3 signal processing circuit. Reference numeral505represents a signal multiple-separation circuit.

The STS-48/12/3 selecting circuit501selects, on the basis of the control of the line-configuration controller72, the circuit to process the line signals transmitted and received at the port30.

The STS-48 signal processing circuit502terminates the signal of STS-48. The STS-12 signal processing circuit503terminates the STS-12 signals. The STS-3 signal processing circuit504terminates the STS-3 signals.

The signal multiple-separation circuit505carries out, on the basis of the control of the line-configuration controller72, multiple processing and separation processing of STS-48, STS-12, and STS-3 signals.

As the configuration of the signal processor50, a circuit that commonly processes the line signals of any one of STS-48/12/3 is provided, and it is possible to provide means for terminating the line signals of any one of STS-48/12/3 and for carrying out multiple separation of the line signals, on the basis of the control of the line-configuration controller72.

FIG. 13is a diagram illustrating a database relating to the group configuration, included in the line-configuration controller72. This is a database of the port numbers associated with Types 1, 2, and 3 of the group configurations illustrated inFIGS. 6 to 11, group symbols representing the groups to which the ports belong, and information related to the signal processing circuits processing signals of lines that are possibly accommodated in the ports.

The line-configuration controller72controls, with reference to the database, the line switch41and the signal processor50in accordance with the type of the transmission module60mounted in the port30.

For example, when the group configuration is set to Type 1, the lines accommodated in the port having the port number1is any one of OC-48, OC-12, and OC-3, and thus the line-configuration controller72selects the signal processing circuit in accordance with the type (bit rate) of the transmission module60mounted in the port having the port number1. For example, when the group configuration is set to Type 2, the lines accommodated in the port having the port number6is either OC-12 or OC-3, and thus the line-configuration controller72selects the signal processing circuit in accordance with the type (bit rate) of the transmission module60mounted in the port having the port number6.

FIG. 14is a diagram illustrating the setting flow of the group configuration. A reference port is provided in advance in the ports30on the interface board100, and the group configuration is set on the basis of the type (bit rate) of the transmission module60mounted in the reference port. Here, the reference port is referred to as a first port (port31).

S11. The line identifying unit71, illustrated inFIG. 2, monitors whether or not the transmission module60is mounted in the first port on the basis of the information on the physical inventory read out from the transmission module60. When the transmission module60is mounted, Step S12is carried out.

S12. The line identifying unit71determines whether or not the line type of the transmission module60mounted in the first port is OC-48 on the basis of the information on the physical inventory read out from the transmission module60. When it is OC-48, Step S14is carried out, whereas, when it is not OC-48, Step S13is carried out.

S13. The line identifying unit71determines whether or not the line type of the transmission module60mounted in the first port is OC-12 on the basis of the information on the physical inventory read out from the transmission module60. When it is OC-12, Step S15is carried out, whereas, when it is not OC-12, i.e., when it is OC-3, Step S16is carried out.

S14. The line-configuration controller72, illustrated inFIG. 2, determines that the line accommodated in the transmission module mounted in the first port is OC-48 on the basis of the information sent from the line identifying unit71. Consequently, the line-configuration controller72selects the Type 1 group configuration and controls the line switch41, as illustrated inFIG. 6, on the basis of the database illustrated inFIG. 13, such as to connect the signals via the port31to the signal processor51, to connect the signals via the port32to the signal processor52, to connect the signals via the ports33to36to the signal processor53, and to connect the signals via the ports37to312to the signal processor54.

In Step S14, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information (bit rate) of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the port to the signal processing circuit corresponding to the bit rate.

S15. The line-configuration controller72determines that the line accommodated in the transmission module mounted in the first port is OC-12 on the basis of the information sent from the line identifying unit71. Consequently, the line-configuration controller72selects the Type 2 group configuration and controls the line switch41, as illustrated inFIG. 8, on the basis of the database illustrated inFIG. 13, such as to connect the signals via the ports31to34to the signal processor51, to connect the signals via the ports35to37to the signal processor52, to connect the signals via the ports38to310to the signal processor53, and to connect the signals via the ports311and312to the signal processor54.

In Step S15, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information (bit rate) of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the port to the signal processing circuit corresponding to the bit rate.

S16. The line-configuration controller72determines that the line accommodated in the transmission module mounted in the first port is OC-3 on the basis of the information sent from the line identifying unit71. Consequently, the line-configuration controller72selects the Type 3 group configuration and controls the line switch41, as illustrated inFIG. 10, on the basis of the database illustrated inFIG. 13, such as to connect the signals via the ports31to35to the signal processor51, to connect the signals via the ports36to39to the signal processor52, to connect the signals via the ports310and311to the signal processor53, and to connect the signals via the port312to the signal processor54.

In Step S16, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information (bit rate) of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the ports to the signal processing circuits corresponding to the bit rate.

According to this embodiment, it is possible to accommodate lines of different types in one port, and it is possible to set the group configuration to which the port belongs according to the type (bit rate) of the lines accommodated in the reference port among the ports provided on the interface board. Consequently, the line capacity processed at the interface board may be improved.

In the above-described embodiment, the number of ports (for example, 12) provided on the interface board, a first line capacity (for example, equivalent to STS-192) accommodated and processed in the interface board, the number of groups (for example, four) that process the line signals of a second line capacity (for example, equivalent to STS-48) obtained by dividing the first line capacity, and the number of ports belonging to each group are determined by the size of the circuits installed on the interface board, the signal processing architecture (interface condition between the interface board and the common board, etc.) of the multirate communication apparatus accommodating the interface board. It is possible, however, to apply the above-described multirate communication apparatus and the method of controlling the line-configuration of the multirate communication apparatus.

Second Embodiment

InFIG. 1, depending on the use of the multirate communication apparatus1, the type of the interface board100mounted on this apparatus differs. For example, when used for a high-speed network to which OC-192, etc., is transmitted, there is a tendency in which the lines of the OC-192 are accommodated in the interface board100, which accommodates the lines of the high-speed network, and many relatively high-speed lines, such as OC-48, are used as the lines accommodated in the other interface boards100. When used for an intermediate/low speed network to which OC-48 is transmitted, there is a tendency in which the lines of OC-192 are not accommodated in the interface board100, and may relatively low-speed lines, such as OC-12 and OC-3, are used as the lines accommodated in the interface board100. Thus, the slot in which the interface board100that is capable of identifying the characteristics of such use of the multirate communication apparatus1is installed is set as a reference slot.

In this embodiment, the capacity of the lines accommodated in the interface board100may be increased by setting the reference slot to the slot in which the interface board100is installed, and adding a condition for setting the group configuration in accordance with the type of the lines installed in the reference slot.

FIG. 15is a diagram (2) illustrating, in outline, an interface board. SimilarFIG. 2, the interface board100mounted on the multirate communication apparatus1in an operating state is illustrated. The transmission modules61,62, and63to612are mounted in the ports31,32, and33to312, respectively, of the interface board100and are operated. Furthermore, the functions described below are added to the line-configuration controller72of the interface board100, illustrated inFIG. 2.

The interface board100inFIG. 15sends the physical inventory information of the interface board100to the common board20. The line-configuration controller72inFIG. 15receives from the common board20the line information of the interface board100installed in the reference slot, and carries out setting control for the group configuration.

The common board20receives the physical inventory information from the interface board100installed in the common slot, and sends the line information of the interface board100installed in the common slot to each interface board100.

FIG. 16is a diagram (2) illustrating the setting flow of the group configuration. A reference port is provided in advance in the ports30on the interface board100, and the group configuration is set on the basis of the type (bit rate) of the transmission module60mounted in the reference port. Here, the reference port is referred to as a first port (port31). The interface board100is installed in the reference slot.

S21. The line identifying unit71, illustrated inFIG. 15, monitors whether or not the transmission module60is mounted in the first port on the basis of the information on the physical inventory read out from the transmission module60. When the transmission module60is mounted, Step S22is carried out.

S22. The line identifying unit71determines whether or not the line type of the transmission module60mounted in the first port is OC-48 on the basis of the information on the physical inventory read out from the transmission module60. When it is OC-48, Step S23is carried out, whereas, when it is not OC-48, Step S24is carried out.

S23. The line-configuration controller72receives from the common board20the line information of the interface board100installed in the reference slot and determines whether or not the line of the interface board100installed in the reference slot is OC-192. When it is OC-192, Step S26is carried out, whereas when it is not OC-192, Step S27is carried out.

S24. The line identifying unit71determines whether or not the line type of the transmission module60mounted in the first port is OC-12 on the basis of the information on the physical inventory read out from the transmission module60. When it is OC-12, Step S25is carried out, whereas, when it is not OC-12, Step S30is carried out.

S25. The line-configuration controller72receives from the common board20the line information of the interface board100installed in the reference slot and determines whether or not the line of the interface board100installed in the reference slot is OC-192. When it is not OC-192, Step S28is carried out, whereas when it is OC-192, Step S29is carried out.

S26. The line-configuration controller72, illustrated inFIG. 15, determines on the basis of the information sent from the line identifying unit71, that the line accommodated in the transmission module mounted in the first port is OC-48, and the interface board mounted in the reference slot accommodates the OC-192 lines. Consequently, the line-configuration controller72selects the Type 1 group configuration and controls the line switch41, as illustrated inFIG. 6, such as to connect the signals via the port31to the signal processor51, to connect the signals via the port32to the signal processor52, to connect the signals via the ports33to36to the signal processor53, and to connect the signals via the ports37to312to the signal processor54.

In Step S26, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the ports to the signal processing circuits corresponding to the bit rate.

S27. The line-configuration controller72determines on the basis of the information sent from the line identifying unit71, that the line accommodated in the transmission module mounted in the first port is OC-48, and the interface board mounted in the reference slot does not accommodate the OC-192 lines; therefore, Group B of the Type 1 group configuration is set to a group configuration to which many ports being. The line-configuration controller72controls the line switch41, such as to connect the signals via the port31to the signal processor51, to connect the signals via the ports32to34to the signal processor52, to connect the signals via the ports35to38to the signal processor53, and to connect the signals via the ports39to312to the signal processor54.

In Step S27, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information (bit rate) of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the ports to the signal processing circuits corresponding to the bit rate.

S28. The line-configuration controller72determines on the basis of the information sent from the line identifying unit71, that the line accommodated in the transmission module mounted in the first port is OC-12, and the interface board mounted in the reference slot does not accommodate the lines OC-192. Consequently, the line-configuration controller72selects the Type 2 group configuration and controls the line switch41, as illustrated inFIG. 8, such as to connect the signals via the ports31to34to the signal processor51, to connect the signals via the ports35to37to the signal processor52, to connect the signals via the ports38to310to the signal processor53, and to connect the signals via the ports311and312to the signal processor54.

In Step S28, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information (bit rate) of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the ports to the signal processing circuits corresponding to the bit rate.

S29. The line-configuration controller72determines on the basis of the information sent from the line identifying unit71, that the line accommodated in the transmission module mounted in the port31is OC-12, and the interface board mounted in the reference slot accommodates the lines OC-192; therefore, sets a group configuration in which many ports belong to Group B of the Type 2 group configuration. The line-configuration controller72controls the line switch41such as to connect the signals via the ports31to34to the signal processor51, to connect the signals via the ports35to38to the signal processor52, to connect the signals via the ports39to311to the signal processor53, and to connect the signals via the port312to the signal processor54.

In Step S29, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information (bit rate) of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the ports to the signal processing circuits corresponding to the bit rate.

S30. The line-configuration controller72determines that the line accommodated in the transmission module mounted in the port31is OC-3 on the basis of the information sent from the line identifying unit71. Consequently, the line-configuration controller72selects the Type 3 group configuration and controls the line switch41, as illustrated inFIG. 10, such as to connect the signals via the ports31to35to the signal processor51, to connect the signals via the ports36to39to the signal processor52, to connect the signals via the ports310and311to the signal processor53, and to connect the signals via the port312to the signal processor54.

In Step S30, the line-configuration controller72controls the signal processor50, as illustrated inFIG. 12, on the basis of the information of the type of the transmission module mounted in each port sent from the line identifying unit71such as to connect the signals via the ports to the signal processing circuits corresponding to the bit rate.

According to this embodiment, it is possible to accommodate lines of different types in one port, and it is possible to set the group configuration to which the port belongs according to the type (bit rate) of the lines accommodated in the reference port among the ports provided on the interface board and the type of the lines accommodated in the interface board mounted in the reference slot of the multirate communication apparatus. Consequently, the line capacity processed at the interface board may be improved.

In the above-described embodiment, the number of ports (for example, 12) provided on the interface board, a first line capacity (for example, equivalent to STS-192) accommodated and processed in the interface board, the number of groups (for example, four) that process the line signals of a second line capacity (for example, equivalent to STS-48) obtained by dividing the first line capacity, the number of ports belonging to each group, an the line (for example, OC-192) accommodate in the interface board mounted in the reference slot are determined by the size of the circuits installed on the interface board, the signal processing architecture (interface condition between the interface board and the common board, etc.) of the multirate communication apparatus accommodating the interface board. It is possible, however, to apply the above-described multirate communication apparatus and the method of controlling the line-configuration of the multirate communication apparatus.

Third Embodiment

InFIG. 2, by providing a signal processing circuits of Ethernet and Ethernet over SONET (EoS) circuits that expand Ethernet signals on a SONET signal format in the signal processors51to54, the interface board100installs a transmission module of Ethernet in the transmission module60, and it is possible to process the Ethernet signals. The signal processors provided with such EoS circuits are represented as signal processors81to84(illustrated inFIGS. 18 and 19).

FIG. 17is a diagram (2) illustrating a group configuration of the interface board100that processes the Ethernet signals.

For example, the interface board100includes 12 ports31to312and carries out the processing of the line signals of STS-192 at four groups (Groups A to D) with processing of the line signals equivalent to STS-48 at each of the signal processors. This condition is the same as that illustrated inFIG. 3.

FIG. 18is a diagram illustrating, in outline, Type 11 group configuration in the interface board100that processes the Ethernet signals. The line switch41is controlled such that the signals via the ports31and32are connected to the signal processor81, the signals via the ports33and34are connected to the signal processor82, the signals via the ports35and36are connected to the signal processor83, and the ports37to312are connected to the signal processor84.

The signal processors81to83are each provided with a signal processing circuit that is capable of processing the signals of either 1000BASE or 100BASE; and the signal processor84is provided with a signal processing circuit that is capable of processing the signals of either 1000BASE or 100BASE and a signal processing circuit that is capable of processing the signals of 100BASE. Here, a signal processing circuit that is capable of processing the signals of 100BASE is also capable of processing the signals of 10BASE.

FIG. 19is a diagram illustrating, in outline, Type 12 group configuration in the interface board100that processes the Ethernet signals. The line switch41is controlled such that the signals via the ports31and32are connected to the signal processor81, the signals via the ports33and34are connected to the signal processor82, the signals via the ports35to38are connected to the signal processor83, and the ports39to312are connected to the signal processor84.

The signal processors81and82are each provided with a signal processing circuit that is capable of processing the signals of either 1000BASE or 100BASE; and the signal processors83and84are each provided with a signal processing circuit that is capable of processing the signals of either 1000BASE or 100BASE and a signal processing circuit that is capable of processing the signals of 100BASE. Here, a signal processing circuit that is capable of processing the signals of 100BASE is also capable of processing the signals of 10BASE.

FIG. 20is a diagram illustrating, in outline, Type 13 group configuration in the interface board100that processes the Ethernet signals. The line switch41is controlled such that the signals via the ports31to33are connected to the signal processor81, the signals via the ports34to36are connected to the signal processor82, the signals via the ports37to39are connected to the signal processor83, and the ports310to312are connected to the signal processor84.

The signal processors81to84are each provided with a signal processing circuit that is capable of processing the signals of either 1000BASE or 100BASE and a signal processing circuit that is capable of processing the signals of 100BASE. Here, a signal processing circuit that is capable of processing the signals of 100BASE is also capable of processing the signals of 10BASE.

According to this embodiment, for the interface board that processes Ethernet signals, it is possible to accommodate lines of different bit rates in one port according to a flow chart (not shown) similar to the flow chart illustrated inFIG. 4in the first embodiment. It is possible to set the group configuration to which the port belongs to according to the type (bit rate) of the lines accommodated in the reference port among the ports provided on the interface board. Consequently, the line capacity processed at the interface board may be improved.

In the above-described embodiment, the number of ports (for example, 12) provided on the interface board, a first line capacity (for example, equivalent to STS-192) accommodated and processed in the interface board, the number of groups (for example, four) that process the line signals of a second line capacity (for example, equivalent to STS-48) obtained by dividing the first line capacity, the number ports belonging to each port are determined by the size of the circuits installed on the interface board, the signal processing architecture (interface condition between the interface board and the common board, etc.) of the multirate communication apparatus accommodating the interface board. It is possible, however, to apply the above-described multirate communication apparatus and the method of controlling the line-configuration of the multirate communication apparatus.

In the above-described embodiments, since it is possible to provide control so that line signals are processed in accordance with the line type of the transmission module mounted on the interface board, it is possible to accommodate lines of different bit rates in one port, and also it is possible to control the configuration of the lines accommodated in the interface board in accordance with the bit rate of the lines accommodated. Therefore, it is possible to improve the accommodation efficiency of the lines processed at the interface board.