Amplifier assembly including variable gain amplifier, parallel programmable amplifiers, and AGC

An amplifier assembly receives an input signal including multiple frequency channels. A first stage amplifier amplifies the input signal, to produce at an output thereof an amplified first signal including the multiple frequency channels. A plurality of second stage amplifiers have their respective inputs coupled to an output of the first stage amplifier. Each second stage amplifier amplifies the amplified first signal, to produce at its respective output a respective second amplified signal including the multiple frequency channels. The first stage amplifier and the second stage amplifiers are variable gain amplifiers, and are constructed on a common Integrated Circuit (IC) substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to variable gain amplifier (VGA) assemblies and components thereof, gain control in such assemblies, and applications of the same.

2. Related Art

VGA assemblies are known in the art. What is needed is a more linear, lower noise, less costly amplifier assembly for providing variable amplifier gain in a variety of applications, such as those including multiple tuners for cable television and data signal applications.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to an amplifier assembly and components/modules used therein, gain control in the amplifier assembly, and associated methods. In an embodiment, an amplifier assembly receives an input signal including multiple frequency channels. The amplifier assembly includes a first stage amplifier that amplifies the input signal, to produce at an output thereof an amplified first signal including the multiple frequency channels. A plurality of second stage amplifiers have their respective inputs coupled to an output of the first stage amplifier. Each second stage amplifier amplifies the amplified first signal, to produce at its respective output a respective second amplified signal including the multiple frequency channels. The first stage amplifier and the second stage amplifiers are variable gain amplifiers, and are constructed on a common Integrated Circuit (IC) substrate.

In another embodiment, an amplifier assembly comprises: an IC substrate; a first stage Variable Gain Amplifier (VGA) configured to have a gain controlled in response to one or more gain control signals; a plurality of parallel second stage Variable Gain Amplifiers (VGAs) having their respective inputs coupled to an output of the VGA; an AGC module configured to generate the one or more control signals responsive to a power of an amplified signal produced by the first stage VGA; a control interface coupled to the first stage VGA, each of the second stage VGAs, and the AGC module; and wherein the first stage VGA, each of the second stage VGAs, and the control interface, and at least a portion of the AGC module are all constructed on the IC substrate.

According to another embodiment, a system for processing an input signal including multiple television (TV) channels, comprises: an amplifier assembly configured to produce, from the input signal, multiple amplified output signals in parallel with each other, each amplified output signal including the multiple TV channels; multiple tuners, each tuner corresponding to a respective one of the multiple amplified signals, each tuner configured to select a subset of the multiple TV channels in the corresponding amplified signal, and to produce a corresponding tuned signal including the selected subset of TV channels; and multiple demodulators, each demodulator corresponding to a respective one of the tuned signals, each demodulator configured to demodulate at least one of the selected subset of TV channels in the corresponding tuned signal, to produce a corresponding demodulated TV signal.

Other embodiments of the present invention are apparent from the ensuing description.

DETAILED DESCRIPTION OF THE INVENTION

In a Community Antenna Television (CATV) system (also referred to as cable TV), a plurality of signals are frequency division multiplexed onto one or more coaxial cables. The CATV system has a downstream band or aggregate signal (headend-to-user) and an upstream band or aggregate signal (user-to-headend). In the downstream band, there can be approximately 135 channels having frequencies that range from 50 MHz to 860 MHz. The individual downstream channels represent different television signals that can be a mixture of analog television signals or digital signals. The analog television signals are preferably NTSC or PAL compliant television signals. The digital television signals carry digital video or cable modem data (e.g. internet traffic), and are typically modulated using 64 QAM or 256 QAM. Other outputs include a buffered version of an input (bypass function) and out-of-band (OOB) control signals.

While the amplitude of each signal varies as a function of the information being transmitted on that channel, the amplitude of the combined signal on the cable will vary not only as a function of the amplitude of each of the individual signals, but also as a function of the phase and amplitude relationship of each channel with respect to the others. Thus, the overall amplitude of the signal will be time varying as the phase and amplitude of each of the individual signals line up. As an example, an amplifier used in a tuner, that receives the downstream signal has to have good distortion performance when 135 channels, each at 0 Decibel-milliVolts (dBmV), are fed to the amplifier input. When the input level is increased to +15 dBmV on each channel, the amplifier must attenuate the input level back down to the same output level as in the case when all channels were at 0 dBmV, while maintaining good distortion performance.

FIG. 1is a block diagram of an exemplary amplifier assembly102for use in a tuner for CATV, for example. Amplifier assembly102includes a VGA amplifier module104, AGC control circuitry or module106for controlling a gain of the VGA amplifier module, a process monitor108. Amplifier assembly102also includes a control interface (CI)109for controlling and monitoring amplifier module104, AGC module106, and process monitor108, over a control bus110. An external controller112controls and receives status information from amplifier assembly102, over an external control bus114coupled to CI109. External control bus114may be a digital control bus including serial data lines and a clock line, for example. CI109may be an analog or digital controller, and control bus110may be an analog or digital control bus.

Amplifier module104receives a signal114including downstream channels spanning 54-860 MHz, for example. Signal114may include TV channels formatted according to NTSC, PAL, or SECAM standards, for example. Signal114may also include channels carrying digital data. Amplifier module104amplifies receive signal114in accordance with a gain of the amplifier module and divides or power-splits the resulting amplified receive signal, to produce a plurality of individual, separate amplified receive signals118(l)-118(n). Amplifier assembly102produces signals118(l)-118(n) in parallel with one another. Each signal118(i) represents an amplified version of receive signal114. Each of amplified signals118is associated with its own gain, and thus, may have a different power level than the other of amplified signals118. The interchangeable terms “gain” and “gain value” as used herein are general, and are intended to include positive, negative or zero gain. Thus, an amplifier having a gain may amplify a signal at a first power level, to produce an amplified signal at a second power level. The second power level may be greater than, less than, or equal to the first power level, depending on whether the gain is positive, negative, or zero, respectively.

In response to a power level of one of amplified signals118(e.g., signal118(2)), AGC module106generates one or more gain control signals120that collectively control the gain of amplifier module104, and thus the power levels of output signals118. As a power level of receive signal114varies, AGC module106adjusts the gain of amplifier module104so as to maintain the individual power levels of amplified signals118at substantially constant respective power levels.

FIG. 2is a block diagram of an example arrangement of amplifier assembly102, expanding onFIG. 1. Amplifier assembly102includes various circuit elements constructed on an integrated circuit (IC) substrate or chip202, depicted in dashed-line. Such on-chip circuit elements are depicted within the dashed-line202. Amplifier assembly102also includes various circuit elements external to IC substrate202, depicted outside of the dashed-line202.

Amplifier module104includes a first stage amplifier204followed by a plurality of, for example, five, parallel second stage amplifiers206for generating corresponding, separate parallel amplified signals118. In an exemplary arrangement, first stage amplifier204is a VGA including an array of variable gain stages arranged in parallel with each other, each having an individual gain controlled responsive to a corresponding one of gain control signals120.

In the arrangement ofFIG. 2, VGA204is a differential amplifier, including differential inputs and differential outputs. A pair of differential signal lines208carry receive signal114to the differential inputs of VGA204. Amplifier assembly102includes a resistor204acoupled between input lines208, external to IC chip202. Together, resistor204aand input attenuation of VGA204(not shown inFIG. 2, but discussed below), set an input impedance of amplifier assembly102. VGA204includes one or more gain control inputs205for receiving corresponding gain control signals120. In an arrangement, gain control signals120include bias or control currents. In an alternative arrangement, gain control signals include bias or control voltages.

VGA204amplifies receive signal114according to a gain of the VGA set by gain control signals120, and produces an intermediate amplified receive signal210. A pair of differential signal lines212, coupled between the differential output of VGA204and respective differential inputs of each of second stage amplifiers206, carry amplified signal210to the second stage amplifiers. Thus, each of parallel amplifiers206is fed with signal energy from a common input, e.g., the output of VGA204/lines212. Also, a termination circuit or output load207(described below in connection withFIG. 7) couples output lines212to a power supply rail of amplifier assembly102.

Each of second stage amplifiers206has a gain that is programmable through CI109. Thus, each of second stage amplifiers206is also a VGA. Programmable gain registers214, coupled to CI109and respective gain control inputs of second stage amplifiers206, hold respective gain values that program the gains of the corresponding amplifiers206. Each amplifier206(i) further amplifies amplified receive signal210in accordance with its respective gain set by the programmable gain in corresponding gain register214(i), to produce respective amplified signal118(i). As depicted inFIG. 2, each amplifier118(i) is a differential amplifier, and each amplified signal118(i) is a differential signal. Termination circuits or output loads207′(l)-207′(n) (where each of the loads207′ is similar to load207) couple respective outputs of amplifiers206(l)-206(n) to a power supply rail of amplifier assembly102. The output of each second stage amplifiers206(i) is configured for driving its own load, for example, an individual tuner coupled to the output. Thus, amplifier assembly102is configured to drive multiple loads (such as tuners) in parallel.

In an arrangement, a first sub-plurality of second stage amplifiers206(for example, outside amplifiers206(l) and206(n)) have a common gain, that is, a programmed first gain, and a second sub-plurality of second stage amplifiers206(for example, inner amplifiers206(2) through206(n−1)) have a common second gain, that is, a programmed second gain. In this arrangement, the second gain is less than the first gain. For example, a ratio of the programmed first gain to the program second gain may be in a range of ratios of between 1:1 to 2:1.

Amplifier assembly102also includes AGC control circuitry or module106coupled between the output of second stage amplifier206(2) and gain control inputs205of VGA204. In an alternative arrangement, ACG module106is coupled between the output of VGA204(e.g., to lines212) and gain control inputs205. AGC control circuitry106includes, in series, a power detector216, a comparator module218, and an AGC controller module220.

Power detector216detects a power level of output signal206(2), and provides a detected power indicator230, that is, a power level signal230, to comparator module218. Power detector216detects the combined power of all of the frequency channels in output signal206(2) (which are the frequency channels in input signal114). Therefore, power level signal230is representative of this combined power. Comparator module218includes a tri-level AGC window comparator222, an upper threshold register224, a lower threshold register226, and a middle or target threshold register228. Threshold registers224,226and228provide respective upper (high), lower (low) and target power thresholds224a,226aand228ato respective comparison inputs of comparator222. Thresholds224a-228amay be programmed through CI109. Target threshold228amay be half-way between thresholds224aand226a, closer to threshold226a, or closer to threshold224a, as desired.

Comparator222receives power level signal230at a comparison input of the comparator. Comparator222compares power level signal230to thresholds224a,226aand228a, to produce a comparison result signal232. Comparison result signal232indicates where the detected power of signal118(2) (that is, power level signal230) is in relation to thresholds224a-228a. Together, upper threshold224aand lower threshold226adefine an AGC window.

Controller module220includes a controller233that receives comparison result signal232and a clock234generated by a clock generator236. Controller233generates a set of control signals238responsive to comparison result232, and provides the control signals to a decoder and switch matrix240(also referred to as switch matrix240). A signal generator242, including an off-chip capacitor244, generates a set of ramp and reference signals246, and provides the ramp and reference signals to decoder and switch matrix240. Decoder and switch matrix240generates gain control signals120in response to signals246and control signals238.

CI109can assert control over, and collect status information from, controller module220, through control interface registers249. For example, CI109can command clock generator236to either start or stop generating clock234. CI109can access status information in controller233indicative of a present gain setting of VGA204. CI109can command controller233to set the gain of VGA204to any desired gain value. In normal AGC operation, controller module220adjusts the gain of VGA204responsive to comparison result232. However, CI109can command controller233to hold the gain of VGA204fixed at a desired gain value, that is, controller233can be commanded to be non-responsive to comparison result signal232. Essentially, this disables AGC operation in amplifier assembly102. Since the gains of VGA204and second-stage parallel amplifiers206may be controlled through CI109, an alternative arrangement of the amplifier assembly omits AGC module106. In such an arrangement, the gain of the VGA module is controlled exclusively by CI109.

In yet another mode of gain control operation, the output of power detector216can be turned off, and an external control voltage250can be substituted for the output of power detector216. In other words, external control voltage250replaces signal230.

In an arrangement, clock generator236is a relaxation oscillator based on alternately charging an on-chip capacitor (not shown inFIG. 2) with a reference current Iref and discharging the capacitor with a current 2Iref. This action produces a 50% duty-cycle triangle wave on a terminal of the capacitor. The control signals for the charge/discharge action are actually the clock output square wave.

The frequency of clock234can be tuned by changing the charge/discharge current to the capacitor. An example frequency tuning range is approximately 1.25 kHz to 80 kHz. An additional frequency tuning factor of 2× can be obtained by either reducing the on-chip capacitor in half, or making the capacitor 2× larger.

Oscillator236also includes a synchronous reset capability which does not produce glitches (i.e., undesired narrow pulse width outputs) on clock234when a RESET signal from CI109is asserted (e.g., set to a logic “1”). Likewise, when the RESET signal is set to logic “0,” no glitch occurs. This is performed by logic circuitry within oscillator236. This no-glitch action insures that the last-held-state of controller233, when controller233is implemented as a stage machine, is maintained at reset and seamlessly restarted when reset is finished. The purpose of this feature is to allow for clock-free operation of the state machine (e.g., controller233), except when checking for gain corrections via an external controller (e.g., controller112). This was done in case relaxation oscillator236produces spurious signals on its output234.

Amplifier assembly102also includes process monitor108. In response to commands issued over CI bus110, process monitor108selectively couples various ones of its process monitor outputs to the CI bus110.

Amplifier assembly102also includes a bandgap voltage reference circuit260. The bandgap voltage reference circuit260produces multiple voltages, including a first fixed voltage that does not vary with temperature, power supply voltage VDD or process variations. An example fixed voltage is approximately 1.2 Volts (V). Circuit260also produces a second voltage that increases proportional to absolute temperature (PTAT), but does not change with VDD or process variations.

Circuit260may produce bias currents based on the fixed and PTAT voltages. For example, the fixed voltage is applied across various resistors (both on- and off-chip202) to create correspondingly fixed bias currents used by various sub-circuits within the IC chip. In general, the bias currents on the order of 200 μA are sent to each sub-circuit. Each sub-circuit then mirrors the currents, sometimes at fixed ratios (either up or down) to get the current(s) needed in each sub-circuit.

Likewise, the PTAT voltage is applied across various resistors (both on- and off-chip202) to create PTAT bias currents used by various sub-circuits within the chip. The PTAT currents would increase at temperature increases.

A substantial portion of the circuits of amplifier assembly102are constructed on IC chip202. However, input load resistor204a, capacitor244, and output load circuit207are external to IC chip202. A general advantage of using such external or off-chip components is that relatively cheaper off-chip components have relatively more accurate parameter values (e.g., resistance, capacitance, inductance, and so on) as compared to corresponding internal or on-chip components. For example, low-cost off-chip components typically have 5% tolerances for resistors and 10% tolerances for capacitors and inductors. Even tighter tolerances can be achieved for slightly more expensive off-chip components.

In alternative arrangements of the present invention, input resistor204ais on-chip. In yet another arrangement, output load circuit207is on-chip. Similarly, capacitor244may be provided on-chip. The parameter accuracy of the on-chip components in such arrangements may be achieved in a variety of ways. For example, switched resistor banks with calibration routines may be used to select a best-valued on-chip resistor among multiple resistors, and so on. In the case of an on-chip version of external capacitor244, which is a large capacitance capacitor, capacitor multipliers may be used.

In another alternative arrangement of amplifier assembly102, parallel second-stage amplifiers206are omitted whereby the output of VGA204drives subsequent processing stages.

FIG. 3is a block diagram of an example arrangement300of VGA204. In the example arrangement depicted inFIG. 3, VGA204includes a plurality of individual gain stages302arranged in parallel with each other. Each gain stage302(i) receives a corresponding gain control signal120(i). Each gain stage302(i) includes a variable gain amplifier304(i) having a gain controlled responsive to the corresponding gain control signal120(i). In the example arrangement ofFIG. 3, VGA204includes an array of seventy (70) variable gain stages302, however, any number of gain stages from 1-to-n may be used. If only one gain stage is used, then AGC module106generates only one corresponding gain control signal120(i).

VGA204includes an input node310coupled to differential signal lines208. Gain stages302have their respective inputs312coupled to input node310. Similarly, their respective outputs314are coupled to an output summing node316that combines together the respective gain stage outputs. Summing node316may be a wire-OR, for example, or any other circuit that combines together the gain stage outputs. Summing node316may include multiple sub-combining nodes for combining subsets of the outputs of gain stages302. In an arrangement, input node310, each of the inputs312and outputs314, each gain stage302(i), and summing node316are differential. However, these elements are depicted as being single-ended inFIG. 3. In VGA204, gain stages302are considered to be arranged in parallel for at least the reason that their respective inputs are coupled to common input node310, and thus, all of the gain stages are fed, with signal energy, from the common input node. Furthermore, the respective outputs of the gain stages are combined together at summing node316.

In operation, each gain stage302(i) amplifies receive signal114in accordance with its individual gain (g(i)) set by corresponding gain control signal120(i) to produce a corresponding amplified receive signal presented at its output314(i). Summing node316combines together all of these individual amplified signals to produce composite or aggregate amplified signal210. Together, the array of parallel gain stages302establishes an aggregate gain of VGA204that is equal to a sum of all of the individual gains of gain stages302. The aggregate gain is controlled in accordance with gain control signals120.

In the arrangement depicted inFIG. 3, VGA204includes a first subset316of non-attenuated gain stages, including gain stages302(1)-302(20). First subset gain stages316have substantially equal respective maximum gains. Amplifier array204also includes a second subset320of attenuated gain stages, including gain stages302(21)-302(70). In an example arrangement, second subset gain stages320have progressively decreasing maximum gains in the direction302(21)-302(70). In another example arrangement, VGA204includes a third subset of constant-attenuated gain stages, e.g., gain stages304(71)-304(90), added to the bottom of the structure depicted inFIG. 3. All of the third subset of gain stages have fixed, constant attenuation.

FIG. 4is a block diagram of an example arrangement of an attenuated gain stage in the second subset or group of attenuated gains stages320. Attenuated gain stage302(i) includes an attenuator402(i) followed by amplifier304(i). Attenuator402(i) may provide fixed or, alternatively, programmable attenuation.

FIG. 4Ais a block diagram of another example arrangement of an attenuated gain stage. In the arrangement ofFIG. 4A, a tap-point or junction404(i) between attenuator402′(i) and amplifier304(i) of attenuated gain stage302(i) is coupled to a next attenuated gain stage302(i+1), and so on. The attenuator reference numeral402′ includes the prime suffix (′) to indicate that the attenuator is shared between gain stages. The use of the attenuated gain stage ofFIG. 4Ain VGA204leads to a another parallel arrangement of attenuated gain stages, as depicted inFIG. 4B.

FIG. 4Bis a block diagram of such a parallel arrangement410of attenuated gain stages. In arrangement410, the attenuated gain stages are cascaded in parallel with each other such that the attenuated gain stages share attenuators. Arrangement410includes an attenuation ladder412coupled between input node310(not shown inFIG. 4B) and the inputs of the amplifiers of the attenuated gain stages. Attenuation ladder412includes a string of series connected attenuators402′. Successive amplifiers304(i),304(i+1), and so on, have their respective inputs fed from corresponding successive taps404(i),404(i+1), and so on, of attenuation ladder412. That is, each attenuator402′(i) feeds both the input to amplifier304(i) and also the input to attenuator402′(i+1) of next gain stage302(i+1), and so on. Thus, the successive taps are associated with increasing attenuation. In this arrangement, attenuated gain stage302(i+1) includes attenuator402′(i), attenuator402′(i+1), and amplifier304(i+1) connected in series with one another. Similarly, attenuated gain stage302(i+2) includes attenuator402′(i), attenuator402′(i+1), attenuator402′(i+2), and amplifier304(i+2) connected in series with each other, and so on.

FIG. 4Cis a block diagram of a differential arrangement420of VGA204, using the attenuation ladder configuration described above in connection withFIG. 4B. In arrangement420, input node310, amplifiers304, attenuators402′, and output combining node316are all differential. Attenuation ladder412includes cascaded attenuators402′. Each attenuator402′(i) includes resistors422(i),424(i) and426(i) connected together as depicted inFIG. 4C. Together, external input resistor204aand internal attenuators,402′(for example, attenuation ladder412) set or control the input impedance of amplifier assembly102, that is, the impedance seen looking into the amplifier assembly along input lines208.

FIG. 5is a block diagram of a single-ended (that is, non-differential) arrangement500of VGA204. The amplifier arrangement ofFIG. 5includes a resistor ladder502, including resistors504, coupled between input node310, specifically between node506and ground. Amplifiers304(21)-304(70) in the attenuated gain stages have their respective inputs tied to corresponding successive taps of resistor ladder502. In an alternative arrangement, the individual taps of resistor ladder502are coupled to outputs of amplifiers320, instead of to the inputs of the amplifiers.

FIG. 6is a block diagram of another example arrangement of attenuated gain stage302(i). As depicted inFIG. 6, attenuated gain stage302(i) includes amplifier304(i) followed by attenuator402(i).

In still another arrangement of VGA204, attenuators are omitted, so that the parallel attenuated gain stages are simply amplifiers (e.g., FETs) sized smaller than the amplifiers of the parallel non-attenuated gain stages. Since the gain of an amplifier is proportional to its size, the smaller amplifiers provide less gain. The attenuated gain stage amplifiers have progressively decreasing sizes, and therefore, progressively decreasing maximum gains.

In each of the arrangements of VGA204depicted inFIGS. 3,4B,4C and5, all of the gain stages are considered to be arranged in parallel with each other for at least the reason that they are fed from a common input node. Also, their individual outputs are combined together to produce an aggregate output, e.g., amplified signal210.

In still another arrangement of the VGA, the attenuated gain stages may be omitted. In such an arrangement, all of the parallel gain stages have substantially the same maximum gain.

FIG. 7is a circuit diagram of an example differential gain stage amplifier304(i) used in the present invention, for example, in amplifier array204. As depicted inFIG. 7, a pair of differentially configured amplifier transistors708aand708bhave their respective gate terminals connected to complimentary differential nodes of input312(i). The drains of transistors708aand708bare coupled to respective complimentary sides of output314(i). Termination circuit207(also referred to as an output load circuit, and mentioned above in connection withFIG. 2) couples the drains of transistors708aand708b(and sources of corresponding differential transistors in all of the other amplifiers304) to a power supply rail PS, at power supply voltage VDD, for example. Specifically, in termination circuit207, the drain of transistor708ais connected to power supply rail PSthrough series connected resistor709aand inductor710a, and a ferrite bead711aconnected in parallel with the series resistor and inductor. Ferrite bead711ahas the effect of a large value inductor in parallel with a large resistor. Also, the drain of transistor708bis similarly coupled to rail PSthrough resistor709b, inductor710b, and ferrite bead711b.

The respective source-drain paths of transistors708aand708bare connected together and to a current mirror712, at a common terminal713. Current mirror712includes a diode configured transistor714coupled to a gain control input terminal715(part of gain inputs205) of amplifier304(i), and also to a gate of a transistor716, which has its source-drain path connected between terminal713and ground. Thus, transistor716operates as the tail current transistor, and thus as a current source, for differential transistors708. In operation, gain control signal120(i), applied to current mirror712, controls a current720flowing through the source-drain path of tail transistor716. The differential gain (g(i)) of amplifier304(i) is controlled responsive to a magnitude of current720. Thus, gain control signal120(i) controls the gain (g(i)) of amplifier304(i) and corresponding gain stage302(i). In a typical arrangement, transistor714is a fraction, for example, one-eighth, the size of transistor716. Thus, tail current720is a multiple, for example, eight times as large as, of control current120(i).

Referring again toFIG. 2, each second stage amplifier206(i) may include a differential amplifier that is similar to the amplifier depicted inFIG. 7. As mentioned above, each second stage amplifier206(i) has its differential output coupled to respective termination circuit207′(i). Also, each termination circuit207′(i) is substantially the same as termination circuit207depicted inFIG. 7. However, the component values used in each circuit207′(i) may differ from the component values used in the other circuits207′, and from the component values used in circuit207.

FIG. 8is a gain response curve for gain stage302(i) and gain stage304(i). That is,FIG. 8is a plot of gain stage gain (g(i)) versus the amplitude of corresponding gain control signal120(i). In the present invention, gain control signal120(i) is a current signal I(i). A given gain control signal120(i) can set the gain of corresponding gain stage302(i) to a minimum gain (e.g., zero gain), a maximum respective gain for that gain stage, or may cause the gain to change between its minimum value (e.g., zero) and the maximum value.

In the present invention, a gain change between the minimum and maximum gain levels for a given gain stage302(i) is achieved according to (that is, follows) a ramp function. That is, the gain changes (e.g., increases or decreases) gradually over a time interval. In accordance with the ramp function, the gain changes smoothly and continuously to avoid abrupt, discontinuous gain changes.

FIG. 9is an illustration of such a smooth and continuous ramp-shaped gain change for a given gain stage302(i). Specifically,FIG. 9is an example combined plot for (i) gain versus time, and correspondingly, (ii) gain control current I(i) versus time, for gain stage302(i). In the plot ofFIG. 9, gain stage302(i) undergoes a gain change (i.e., increase) from zero gain at time t1to its respective maximum gain at time t2in response to gain control current I(i). The gain change is continuous, that is, does not have discrete gain level steps or jumps. Also, the gain change is smooth. For example, the slope of the gain change is continuous, and thus, does not exhibit discontinuities. The gain may increase monotonically over time, such as linearly or exponentially. However, the gain change may also include non-monotonic portions, as long as they are smooth and continuous.

FIG. 10is combined plot similar toFIG. 9, but for a decrease in gain. That is,FIG. 10is an illustration of an exemplary smooth and continuous ramp-shaped gain change (decrease) over time for a gain stage302(i) of the VGA ofFIG. 3.

FIG. 10Ais an illustrative example of how the aggregate gain of first stage amplifier204, e.g., amplifier array204, may be changed in the present invention. In this illustrative example, the aggregate gain of amplifier array204is decreased from a maximum aggregate gain to an intermediate aggregate gain. InFIG. 10A, each gain stage302(i) is depicted as a triangle. Dark-shaded triangles depict gain stages that are fully ON, that is, operated at their respective maximum gains. In contrast, triangles that are not shaded (that is, un-shaded triangles) depict gain stages that are fully OFF, that is, gain stages set to zero gain. Triangles filled with cross-hatches indicate gain stages that are in the process of having their respective gains changed, for example, either increased or decreased. Also, the process of changing aggregate gain depicted inFIG. 10Aproceeds from a first step “Step1” depicted at the top ofFIG. 10A, to a final step “Step5” depicted at the bottom of theFIG. 10A.

Initially, in Step1, the aggregate gain of amplifier array204is at a maximum aggregate gain level. In this state, all of non-attenuated gain stages316(i.e., gain stages302(1)-302(20)) are set to or operating at their respective maximum gains. Concurrently, all of the attenuated gain stages320(i.e., gain stages302(21)-302(70)) are set to or operated at zero gain. Thus, in Step1, gain stages302(1) through302(20) represent first gain stages among the set of gain stages302that are set to their respective maximum gains. Similarly, gain stages302(21) through302(70) represent second gain stages of the gain stages302that are set to zero gain. Note here that the terms “first gain stages” and “second gain stages” refer to gain stages of VGA204only, and are not to be confused with “first stage amplifier204” and “second stage amplifiers206” discussed above in connection withFIG. 2, for example.

In Step2, the gain of one of the first gain stages is decreased to zero gain according to a ramp function and the gain of one of the second gain stages is increased to its respective maximum gain according to the ramp function. More specifically, the gain of gain stage302(1) is decreased to zero gain according to the ramp function and the gain of gain stage302(21) is increased to its respective maximum gain according to the ramp function. The gain increase operation and the gain decrease operation may be performed concurrently, or alternatively, sequentially, that is one after the other.

After the gain changes of Step2, the amplifier array204is configured as depicted in Step3ofFIG. 10A. Namely, gain stages302(2) through302(21) are set to the respective maximum gains (and thus, represent a new set of first gain stages that are fully ON), while gain stages302(1) and302(22)-302(70) are set to zero gain (and thus, represent a new set of second gain stages that are fully OFF).

In step4, a further decrease in aggregate gain is achieved by decreasing the gain of gain stage302(2) to zero and increasing the gain of gain stage302(22) to its respective maximum. These gain changes may be performed concurrently or sequentially.

After the gain change of Step4, amplifier array204is configured as depicted in Step5. The aggregate gain of amplifier array204in Step5is less than the aggregate gain of amplifier array204in Step1. This is because the sum of the maximum gains of the gain stages turned ON in Step5(i.e., gain stages302(3)-302(22)) is less than the sum of the maximum gains of the gain stages turned ON in Step1(i.e., gain stages302(1)-302(20)). State otherwise, the sum of the maximum gains of gain stages302(20)-302(21) is less than the sum of the maximum gains of gain stages302(1)-302(2).

During the gain change process depicted inFIG. 10A, a contiguous set of gain stages (e.g., twenty gain stages) are maintained in their fully ON states. This contiguous set of ON gain stages is dynamic, and “slides” to the right across the full set of gain stages302depicted inFIG. 10A. If the aggregate gain is further decreased to a point where the lower twenty attenuated gain stages, e.g., gain stages302(51)-302(70)), are ON, then any further decrease in gain is achieved by sequentially turning OFF gain stage302(51), then gain stage302(52), and so on until none of the gain stages remain ON.

The process for increasing aggregate gain is essentially opposite from the process for decreasing aggregate gain. That is, higher numbered gain stages are sequentially turned fully ON, while lower numbered gain stages are sequentially turned fully OFF. In this case, the contiguous set of ON gain stages would slide to the left inFIG. 10Aas the aggregate gain is increased.

FIG. 10Bis an example plot of power control signal230versus time corresponding to an example receive signal scenario. The example plot ofFIG. 10Bserves as a useful illustration of the operation of VGA204and AGC module106with respect to power level signal230and thresholds224a-228a. An initial assumption is that at a time t0, the power of receive signal114, the aggregate gain of VGA204, and the resulting power of amplified receive signal118(2) are such that power level signal230is between upper threshold224aand lower threshold226a, as depicted inFIG. 10B. It is also assumed that at periodic time intervals tsample, controller module220(more specifically, controller233) polls or “samples” comparison result signal232.

Beginning at a time t0, a slow increase in the power of receive signal114causes a correspondingly slow increase in amplified signals210and118(2), and power detector level signal230. AGC module106maintains the gain of amplifier204at a fixed level as power signal230rises. Eventually, power signal230rises to a level that is greater than upper threshold224a, as indicated at1050inFIG. 10B. At a next sample time1052, controller module220polls comparison result signal232, which indicates the over-threshold condition at1050. In response to this over-threshold condition, controller module220generates gain control signals120to decrease the gain of VGA204continuously and smoothly, and correspondingly, power level signal230, until the power level signal passes below target threshold228a.

At a sample time1054, controller module220becomes informed that power level signal230has crossed, e.g., dropped below, target threshold228a. In response to this condition, controller module220generates gain control signals120such that the gain of amplifier204remains fixed. That is, controller module220stops changing the gain amplifier204because power signal230is at or near the target threshold228a. Controller module220will cause the gain of amplifier204to remain at this fixed level until power level signal230again becomes either too high (i.e., above upper threshold224a) or too low (i.e., below lower threshold226a). Controller module220causes the gain of VGA204to decrease in a smooth and continuous manner between points1050and1054. This results in the smooth and continuous downward slope of power level signal230depicted inFIG. 10B. In an example arrangement, controller module220causes the gain of VGA204to decrease according to the process discussed above in connection withFIG. 10A, that is, by sequentially turning OFF and ON gain stages in the amplifier array204. The smooth and continuous gain change arrangement produces a correspondingly smooth and continuous change in the power levels of signals210and118.

The smooth and continuous change of power level signal230depicted inFIG. 10Bincludes small stair-steps or “wiggles” having sloped falling edges. This results from smooth and continuous gain changes having corresponding stair-steps. These stair-steps result from pauses between incremental gain changes. For example, with reference again toFIG. 10A, gain is changed in the following manner. In Step2, the gain of VGA204is decreased an incremental amount, smoothly and continuously according to a ramp function. Then, in step3, the gain of VGA204remains constant for a short period of time, that is, the gain remains level. Then, in Step4, the gain of VGA204is decreased again an incremental amount, smoothly and continuously according to a ramp function. Steps2,3and4repeat until power level signal230crosses target threshold228a. The pause between successive incremental gain changes is discussed below in connection withFIG. 20.

FIG. 11is a block diagram expanding on controller module220and portions of comparator module218, discussed above in connection withFIG. 2. Depicted inFIG. 11are various low-level control signals not specifically depicted inFIG. 2. As mentioned above, controller module220generates gain control signals120responsive to comparison result signal232. Controller233of controller module220provides a comparator control signal1102to comparator222. At periodic time intervals, controller233asserts comparator control signal1102, thus causing comparator222to produce comparison result signal232at these time intervals. Thereafter, controller233polls comparison result signal232to determine whether the gain of VGA204should be either changed or maintained at a current or present level, as mentioned above in connection withFIG. 10B. In the present invention, the periodic time intervals (e.g., the time between successive polling operations) are programmable in duration, and should correspond to the rate at which the power level of input signal114is expected to vary. Exemplary time intervals may be between 1 millisecond and 1 minute, or even longer. More typical time intervals are in the range of 1-10 milliseconds. In an arrangement, controller233is a state-machine based controller clocked by clock234. However, controller233may be any digital or analog controller.

Controller233also provides signal generator control signals1104to signal generator242, and receives a ramp status signal1106from the signal generator. Signal generator242includes a ramp generator and a reference signal generator (not shown separately inFIG. 11). The ramp generator generates complimentary ramp signals1108(VRAM_P) and1110(VRAM_N) on command, that is, in response to a ramp trigger signal in control signals1104. The reference signal generator generates reference signals1112(VREF_HI) and1114(VREF_LO) having complimentary fixed signal values or amplitudes. For example, signal1112is a fixed high voltage, while signal1114is a fixed relatively low voltage. Signals1108-1114are provided to decoder and switch matrix240.

Controller233also generates control signals238for controlling decoder and switch matrix240. Control signals238include an address pointer1116indicating which of the gain stages302of VGA204should be fully ON, that is, operating at their respective maximum gains, at any given time. Controller233also generates a set of digital control signals1120for controlling various functions of decoder and switch matrix240. For example, signals1120indicate whether the gain of VGA204should be increased or decreased, and when such a change should occur. Responsive to (i) control signals1116and1120, (ii) ramp signals1108and1110when generated, and (iii) reference signals1112and1114, decoder and switch matrix240generates gain control signals120as appropriate to either change (i.e. increase or decrease) or maintain at a constant level the gain of VGA204.

FIG. 12is a block diagram of a representative portion1200(i) of decoder and switch matrix240. Portion1200(i) is repeated within decoder and switch matrix240for each of gain stages302(i). Portion1200(i) includes a switch1204(i) that receives signals1108-1114and a control signal1206(i) derived responsive to control signals238(that is,1116and1120). In response to control signal1206(i), switch1204(i) connects either (i) ramp signals1108and1110, or (ii) reference signals1112and1114, to the inputs of a differential driver1210(i). Differential drive1210(i) generates gain control signal120(i) responsive to its switched inputs.

More specifically, responsive to control signals238, switch1204(i) may be placed in any one of four different configurations. In a first configuration, switch1204(i) connects reference signals1112and1114to differential driver1210(i) such that gain control signal120(i) has a static maximum amplitude that drives or sets the gain of corresponding gain stage302(i) to a maximum value.

In a second configuration, switch1204(i) connects reference signals1112and1114to differential driver1210(i), in a manner that is inverted with respect to the first configuration, such that gain control signal120(i) has a static minimum amplitude that sets the gain of corresponding gain stage302(i) to a minimum value.

In a third configuration, switch1204(i) connects ramp signals1108and1110to differential driver1210(i) such that gain control signal120(i) has an amplitude that follows a rising or increasing ramp function. For example, gain control signal120(i) has an amplitude that increases over a time interval continuously and smoothly from the minimum amplitude to the maximum amplitude. As a result, the gain of corresponding gain stage302(i) increases over the time interval continuously and smoothly from the minimum gain to the maximum gain for that gain stage.

In a fourth configuration, switch1204(i) connects ramp signals1108and1110to differential driver1210(i), in a manner that is inverted with respect to the third configuration, such that gain control signal120(i) has an amplitude that follows a falling or decreasing ramp function. For example, gain control signal120(i) has an amplitude that decreases over a time interval continuously and smoothly from the maximum amplitude to the minimum amplitude. As a result, the gain of corresponding gain stage302(i) decreases over the time interval continuously and smoothly from the maximum gain to the minimum gain for that gain stage.

When the aggregate gain of amplifier array204is to be maintained at a present value, first gain stages among gain stages302of VGA204are set to their respective maximum gains, while second gain stages among gain stages302of VGA204are set to zero gain. This type of arrangement was described above in connection with Steps1,3and5ofFIG. 10A. To effect such an arrangement:

(i) first switches (among switches1204) corresponding to the first gain stages of VGA204are set to their first configurations, so as to produce corresponding gain control signals at their maximum fixed amplitudes; and

(ii) second switches (among switches1204) corresponding to the second gain stages of VGA204are set to their second configurations, so as to produce corresponding gain control signals at their minimum fixed amplitudes.

When an aggregate gain change is required, the gain of one of the first gain stages is decreased to zero and the gain of one of the second amplifiers is increased to its maximum gain. This arrangement was described above in connection with Steps2and4ofFIG. 10A. To achieve this, the switch corresponding to the one of the first gain stages (to be turned OFF) is placed into its third configuration and the switch corresponding to the one of the second amplifiers to be turned ON is placed in its fourth configuration. Then, the amplitudes of the gain control signals corresponding to these switches will ramp-up (e.g., increase) and ramp-down (e.g., decrease) as a function of ramp signals1108and1110. In turn, the gains of the corresponding gain stages will ramp-up and ramp-down.

FIG. 13is a block diagram of an example arrangement of power detector216. Also depicted inFIG. 13are exemplary signal waveforms corresponding to various portions of the power detector circuit. Power detector216includes an envelope detector1302followed by a low pass filter. The low pass filter includes a resistor (R) and a capacitor (C). Power detector216produces power level signal230at a voltage level (PDET) that is proportional to the amplitude or power level of amplified signal118(2).

FIG. 14is a circuit diagram of an example arrangement of comparator222. Comparator222includes an upper threshold comparator1402for comparing power level signal230to upper threshold224a, to produce an upper threshold result232a. Upper threshold result232aindicates whether power level signal230is above or below upper threshold224a. Comparator222includes a target threshold comparator1404for comparing power level signal230to target threshold228a, to produce a target threshold result232b. Result232bindicates whether power level signal230is above or below target threshold228a. Comparator222also includes a lower threshold comparator1406for comparing power signal230to lower threshold226a, to produce a lower threshold comparison result232c. Result232cindicates whether power level signal230is above or below lower threshold226a. Comparison result signal232comprises the set of comparison results232a-232c.

FIG. 15is a circuit diagram of an example arrangement of a ramp generator1500of signal generator242. Also depicted inFIG. 15are exemplary signal waveforms corresponding to various nodes in the circuit1500(for example, waveforms corresponding to signals1108(VRAMP_P),1110(VRAM_N), and VRAMP). Ramp generator1500includes a first stage1502. First stage1502include a ramp generator switch1504coupled to a positive input of an operational transconductance amplifier (OTA) through a resistive voltage divider including resistors R10and R11. A current source I1is connected between the positive input of OTA1508and a power supply rail at voltage VDD. OTA1508is configured as a voltage follower amplifier having a current output. First stage1502also includes capacitor244(CEXT) connected between an output terminal or node1514of OTA1508and ground. Switch1504is selectively opened or closed (i.e., either disconnected from ground or connected to ground) responsive to a ramp trigger signal, which is one of control signals1104from controller233.

Assume initially that switch1504is open. When controller233closes switch1504, a voltage VSW at the positive input of OTA1508becomes 0.5 volts. Then, when controller233opens switch1104, the voltage VSW instantaneously jumps up to 1.5 volts. However, the output of OTA1508, that is, the voltage VRAMP at node1514rises relatively slowly from 0.5 volts because the current produced by OTA1508charges capacitor244. OTA1508has a differential voltage input and a current output (or even a differential voltage output). OTA1508is advantageous in this application because it produces a slow, smooth and continuous, linear voltage change at its output due to the large capacitance of capacitor244. When controller233opens switch1504, the voltage VSW instantaneously drops to 0.5 volts. However, the voltage VRAMP at node1514drops slowly from 1.5 volts down to 0.5 volts because of a discharge effect caused by capacitor244. Any circuit that produces such a step voltage at the OTA input can be used in the present invention.

Ramp generator1500includes a second stage1520coupled to output node1514. Second stage1520includes an optional first voltage follower amplifier1522for generating signal1108(VRAMP_P) and a second amplifier1524for generating signal1110(VRAMP_N). Thus, complimentary ramp signals1108and1110can be made to ramp-up or ramp-down on command by selectively opening and closing switch1504.

The capacitance of capacitor244controls the slew time of ramp signal VRAMP (and correspondingly, the slew rates of ramp signals1108VRAM_P) and1110(VRAMP_N)). The example slew time depicted inFIG. 15is one milliseconds (ms). However a range of slew times, for example, between one ms and ten ms, may be used in the present invention. The capacitance of capacitor244is relatively large, for example, in the range of ten (10) nanoFarads. Thus, it is advantageous to have capacitor244off-chip, so as to correspondingly reduce the size of IC chip202.

FIG. 16is a circuit diagram of an example arrangement of a reference signal generator1600of signal generator242. Reference signal generator1600includes the following components connected in series and between a power supply rail at voltage VDD and ground: a current source1602and resistors1604-1610. Reference signal1112(VREF_HI) is tapped-off between current source1602and resistor1604. Signal1114(VREF_LO) is tapped-off between resistors1608and1610.

Reference signal generator1600also includes a ramp window comparator1618including first and second comparators1622and1624. First and second comparators1622and1624compare the voltage VRAMP, generated at the output of OTA1508(discussed in connection withFIG. 15), to respective tapped voltages VREF2and VREF1. Voltages VREF2and VREF1are tapped-off between resistors1604and1606, and between1606and1608, respectively. Comparators1622and1624generate ramp state signal1106indicating whether VRAMP (and correspondingly, whether signals1108and1110) has settled to a static value, that is, finished slewing, after switch1504has either opened or closed. After controller233commands ramp generator1502to generate ramp VRAMP, by toggling switch1504either open or closed, the controller monitors ramp state signal1106to determine when the ramp has finished slewing to its final high or low fixed voltage.

V. Process Monitor

FIG. 16Ais a circuit/block diagram of an example arrangement of process monitor108, mentioned above in connection withFIGS. 1 and 2. The component values and transistor characteristics of a typical IC chip vary from one chip to another. Although ratios between one component and another match well on-chip, absolute values can vary widely. Process monitor108measures the absolute value of unit sample resistors and transistors. If a particular resistor or transistor measures high by a certain percentage, then all other resistors and transistors of that type will also measure high by the same amount. This information can be used to adjust the gain of an amplifier on the chip (for example, any of amplifiers204and206on IC chip202) to a desired value, or to determine the true, corrected gain of such an amplifier. At any given time during the operation of amplifier assembly102, the gain value of VGA204can be read through CI109. Also, process information about process variations corresponding to IC chip202can be collected from process monitor108. Based on the gain value, and the process information, gain correction factors can be derived, and then applied to any of amplifiers204and206to compensate for the process variations.

Process monitor108includes the following circuits: a bias circuit1650, a sense circuit module1651, a multiplexer1652, an amplifier1653, a latched-comparator1655, and a digital-to-analog converter (DAC)1658.

Bias circuit1650produces a set of controlled, predetermined bias currents1660. Responsive to bias currents1660and a select signal1661, sense circuit module1651produces various sensed signals1663indicative of process parameters of IC chip202, and provides the sensed signals to multiplexer1652. Responsive to a multiplexer select signal1664, multiplexer1652provides a selected one of sensed signals1663to the group of circuits1653,1655, and1658. A value of the selected sensed signal is determined using circuits1653,1655and1658.

Bias circuit1650produces bias currents1660based on either CTAT (constant-to-absolute temperature, which remains constant as temperature changes) or PTAT (proportional-to-absolute temperature, which increases linearly with absolute (Kelvin) temperature). In addition, each current of bias currents1660is based on a particular resistor type, such as an external (off-chip, and assumed to have a very low temperature coefficient), poly-high (high sheet-rho polysilicon, on-chip) or poly-low (low sheet-rho polysilicon, on-chip). “Poly” means polysilicon, and “sheet-rho” refers to resistivity per unit area of the IC chip. Each type of current is labeled accordingly: “CTAT Ext_R,” “PTAT poly_high,” or “CTAT poly-high.” Other on-chip resistors, such as diffused resistors, can be used.

FIG. 16Bis a circuit diagram of an example arrangement of sense circuit module1651. Also depicted inFIG. 16Bis a portion of bias circuit1650. Module1651includes a plurality of process monitor or sense circuits1670-1680for monitoring/sensing process-dependent parameters of IC chip or substrate202. Module1651also includes a temperature monitor1682. Switches S1-S5, controlled by signal1661, apply appropriate ones of bias currents1660to various diode-connected transistors and grounded resistors of sense circuits1670-1682. In response, sense circuits1670-1682produce sensed signals1663having values that provide information about process variations and temperature of IC chip202. In the arrangement depicted inFIG. 16B, sensed signals1663are voltages. In an alternative arrangement, the sensed signals may be currents. Alternatively, a mix of voltages and currents may be generated.

Monitor or sense circuit1670monitors or senses an NMOS conductivity (k) of IC chip or substrate202. Sense circuit1670produces a sensed signal nmos_k indicative of the NMOS conductivity.

Sense circuit1672monitors a PMOS conductivity of IC chip202. Sense circuit1672produces a signal pmos_k indicative of the PMOS conductivity.

In sense circuits1670and1672, transistors M1and M2are relatively small MOS transistors running at high current density, in a diode-connected set-up. This causes their VGS to be much larger than the transistor threshold voltage (VTH, indicated in labels “vt” and “Vt” inFIG. 16B). Thus, this configuration provides information about the transconductance parameter, k, of the transistors on the IC chip. Since VGS is large for these devices, a two-resistor voltage divider is used to reduce the sense voltage to within the same range of the other sense circuits.

Sense circuit1674monitors an NMOS transistor threshold (vt) of IC chip202. Sense circuit1674produces a signal nmos_vt indicative of the NMOS threshold.

In sense circuits1674and1676, transistors M3and M4are also diode-connected, and are large devices running at low current density. This causes these device to have a VGS near their VTH.

Sense circuit1678monitors a resistivity per unit area, poly-low sheet-rho of IC chip202. Sense circuit1678produces a signal pl_rho indicative of the resistivity per unit area, poly-low sheet-rho of IC chip202.

Sense circuit1680monitors a resistivity per unit area, poly-high sheet-rho of IC chip202. Sense circuit1680produces a signal ph_rho indicative of the resistivity per unit area, poly-high sheet-rho of IC chip202.

In sense circuits1678and1680, two resistors, R5and R6are 3.75K ohm poly-low and poly-high resistors (respectively) that are biased at a fixed current (external R, CTAT). The voltage across these resistors is proportional to the sheet-rho of each resistor.

Sense circuit1682monitors a temperature of IC chip202, and produces a signal therm indicative of this temperature. In sense circuit1682, resistor R7is used to determine chip temperature. This is done by connecting either poly-high/CTAT or poly-high/PTAT reference current to this resistor. Since the reference current is based on a poly-high resistor in both cases, the effects of process variation on the poly-high resistor is removed, leaving only CTAT vs. PTAT variations (i.e. temperature variations).

Referring again toFIG. 16A, multiplexer1652, amplifier1653, comparator1655and DAC1658cooperate with CI109to determine the values of the various sensed signals1663. Multiplexer1652selects any one of sensed signals1663, responsive to control signal1664. Amplifier1653scales the selected sensed signal, and presents the scaled, selected sensed signal to latching comparator1655. Amplifier1653has an output voltage range between 0.5 and 1.5 volts, approximately, which is the same as the output range of DAC1658. Comparator1655is in a latch mode when its clock input is a logic “1,” and in a track (or transparent) mode when its clock input is a logic “0.” At the same time, switches S1-S5apply bias current(s) to the sense circuit(s) that produce(s) the selected sensed signal(s).

IC109applies an input vref to DAC1658. Namely, an input of “000000” produces 0.5 volts at the DAC output, while “111111” produces 1.5 volts. DAC1658applies its output to a comparison input of comparator1655. Comparator1655compares the DAC output voltage to the selected scaled sensed signal from the corresponding sense circuit, and produces comparison result output comp_out. CI109accesses or reads the value of comp_out. Comparator1655uses a successive-approximation-register (SAR) algorithm to determine the value, e.g., voltage, of the sensed signal by comparing the sense signal against the DAC output voltage with 6-bit resolution. The SAR operation is controlled through CI109(e.g., by external controller112), which sets the DAC input bits (and hence its output voltage) and clocks the comparator. If the output of the comparator is a logic “1” after clocking, the sensed signal or voltage (at the scaling amplifier output) was larger than the DAC voltage (and vice-versa).

Multiplexer1652, amplifier1653, comparator1655and DAC1658cooperate with CI109to determine the values of the various sensed signals1663. Any other circuit may be used to perform this function. In an alternative arrangement, sense module1651generates sensed signals1663as digital signals, for example, using an analog-to-digital converter (ADC) on the output of each sense circuit in module1651, and presents the digital signals to CI109. In this arrangement, circuits1652,1653,1655and1658may be omitted.

VI. Method Flow Charts

FIG. 17is a flowchart of an example method1700of controlling gain that may be performed in amplifier assembly102. An initial step1704includes setting a gain of a VGA module, for example, amplifier module104. For example, this step includes setting an initial gain of first stage amplifier204, e.g., amplifier array204, in accordance with gain control signals120, and setting initial gains of second stage amplifiers206to programmed gain values. The gains may be set to any desired gain values. For the purposes of gain changes that may occur in subsequent steps of method1700, amplifiers206can be considered to have relatively fixed gain set to initial values in step1704, as compared to VGA204, which has a relatively dynamic gain.

A next step1710includes amplifying a receive signal to produce an amplified signal. For example, this step includes amplifying receive signal114with amplifier array204and second stage amplifier206(2) to produce amplified signal118(2).

A next step1715includes detecting a power level of the amplified receive signal generated in step1710. For example, power detector216detects the power level/amplitude of signal118(2), to produce power level signal230. Power level signal230is indicative of the power level of receive signal114, and amplified signals210and118.

A next step1720includes determining whether the power level of the amplified signal (as indicated by the detected amplified signal) is between an upper threshold (e.g., threshold224a) and a lower threshold (e.g., threshold226a) defining an AGC window. Step1720includes further steps1722and1724. Step1722includes comparing the detected power level (“DPL”) to the upper threshold, and step1724includes comparing the detected power level to the lower threshold. If the detected power level of the amplified signal is between the upper and lower thresholds, that is, within the AGC window, then flow proceeds back to step1710through a delay or wait step1724a. Step1724acorresponds to a programmable time interval, and may be included in step1724. Steps1720and1724amay be performed under the control of controller module220.

If the power level of the amplified signal is not between the upper and lower thresholds, that is, within the AGC window, then flow proceeds to a next step1725. Step1725includes changing the gain of the VGA module so as to drive the power level of the amplified signal in a direction toward a target threshold (e.g., threshold228a) intermediate the upper and lower thresholds. Step1725includes changing the gain until the power level of the amplified signal crosses the target threshold. The gain change is smooth and continuous, in accordance with a ramp function.

Step1725includes further steps1730and1735. Step1730includes decreasing the gain when comparison step1722indicates the power level of the amplified signal is above the upper threshold. Step1735includes increasing the gain when comparison step1724indicates the amplified signal power level signal is below the lower threshold. Step1725may be performed under the control of controller module220. For example, controller220generates control signals120so as to change the gain of amplifier array204, and thus, the gain of amplifier module104.

After the gain change of step1725, flow proceeds back to step1710through a delay or wait step1737(similar to wait step1724a), and the process described above repeats. Step1737corresponds to a programmable time interval, and may be included in both of steps1730and1735.

In an alternative arrangement of method1700, the gains of both amplifiers204and206may be changed in step1725.

The example gain change scenarios discussed above in connection withFIGS. 10A and 10Bmay be achieved in accordance with method1700. For example, at sample time1052inFIG. 10B(corresponding to step1722in method1700), controller module220determines or becomes aware that the gain of VGA204needs to be reduced. In response, controller module220reduces the gain of VGA204between times1052and1054(corresponding to step1730of method1700), that is, until the power level signal crosses target threshold228a. Controller module220reduced the gain of VGA204in accordance with the gain change scenario ofFIG. 10A. Then, as depicted inFIG. 10B, controller module220waits until a next sample time (corresponding to wait step1737in method1700), before again polling comparison result signal232to test whether another gain change is required.

Frequent AGC induced gain changes can sometimes cause disruptive amplitude changes in an AGC controlled output signal. For example, the frequent AGC induced gain changes can sometimes disrupt the operation of circuits or processors, such as demodulators, that process the AGC controlled output signal. The present invention advantageously reduces the frequency of AGC induced gain changes compared to conventional AGC systems. In the present invention, this advantageous effect arises from a combination of (i) polling comparison result signal232at spaced time intervals (e.g., every tsample) to determine if a gain change is required, and (ii) maintaining power level signal230at or near target threshold228a, within an AGC window, and then only changing the gain when the power level signal is outside of the AGC window. Either one of these techniques taken alone can reduce the frequency of gain changes, but together these techniques even further reduce the frequency of gain changes.

FIG. 18is a flow chart expanding on initial gain setting step1704, as performed in amplifier assembly102. Step1704includes a further step1802, wherein controller module220generates gain control signals120such that (i) first gain stages among gain stages302in VGA204are set to their respective maximum gains, and (ii) second gain stages among gain stages302in VGA204are set to zero gain. The control signals120corresponding to the first gain stages of VGA204have fixed maximum amplitudes, and the control signals corresponding to the second gain stages of VGA204have fixed minimum amplitudes. With reference again toFIG. 2, in step1802, CI109commands controller module220to cause the gain of VGA204to be set to the desired value.

FIG. 19is a flow chart expanding on gain change step1725, as performed in amplifier assembly102. It is assumed that before step1725is executed, VGA204is configured to have an aggregate gain as a result of first gain stages thereof being set to their respective maximum gains and second gain stages thereof being set to zero gain. A step1905includes sequentially decreasing the gains of one or more of the first gain stages to zero gain according to a ramp function. A step1910includes sequentially increasing the gains of one or more of the second gain stages, corresponding to the one or more of the first gain stages, to their respective maximum gains according to the ramp function. Steps1905and1910may be performed concurrently. Alternatively, steps1905and1910may be performed in series with each other and such that step1905precedes step1910, or alternatively, in a reverse order. Method1900may be performed to either increase the aggregate gain (as would be the case in step1730) or decrease the aggregate gain (as would be the case in step1735).

FIG. 20is a flow chart of a low-level example method2000expanding on gain change step1725and focusing on operations performed by elements of controller module220during the gain change. As mentioned above, step1725, and thus, method2000, is invoked when step1720indicates an aggregate gain change is required. For example, when controller233determines, in response to comparison result232, that an aggregate gain change is required.

It is assumed that before method2000begins, step1704set the aggregate gain of VGA204to an initial value. In this condition, first gain stages among gain stages302of VGA204are set to their maximum gains and second gain stages among gain stages302of VGA204are set to their minimum gains, so as to set the aggregate gain of VGA204to the initial value. More specifically, in switch matrix240:

(i) first switches (among switches1204) corresponding to the first gain stages are set to their first configurations, and thus, the corresponding first gain control signals are set to their maximum amplitudes; and

(ii) second switches (among switches1204) corresponding to the second gain stages are set to their second configurations, and thus, the corresponding second gain control signals are set to their minimum amplitudes.

In a first step2005, controller233receives comparison result signal232. In response, controller233indicates to switch matrix240, via signals238, the direction of the required gain change, and thus, which gain stage among the first gain stages is to be turned OFF, and which gain stage among the second gain stages is to be turned ON. Essentially, in response to comparison result232, controller233selects which gain stages are to be turned OFF and ON to effect the gain change.

In a next step2010, responsive to control signals238, switch matrix240sets:(i) the switch corresponding to the gain stage to be turned OFF to either its third or fourth configuration, as appropriate; and(ii) the switch corresponding to the gain stage to be turned ON to either its fourth or third configuration, as appropriate.

Essentially, the gain control signals corresponding to these two switches are connected to the output of the ramp generator, and are thus are ready to be driven by a ramp signal.

In a next step2015, controller233triggers ramp generator1502to generate the ramp signals1108and1110according to the ramp function, e.g., by toggling switch1504. In response to ramp signals1108and1110, the gain control signals corresponding to the switches coupled to ramp generator1502turn OFF and ON their corresponding gain stages.

In a next step2020, controller233monitors ramp state signal1106to determine when ramp signals1108and1110have settled to their final fixed values, that is, when the ramp has finished slewing. When this occurs, controller233sets:(i) the switch corresponding to the gain stage just turned OFF to either its first or second configuration, as appropriate; and(ii) the switch corresponding to the gain stage just turned ON to either its second or first configuration, as appropriate.

Essentially, the gain control signals corresponding to these two switches are now connected to the output of the reference signal generator, and are thus held at respective fixed amplitudes.

In a next step2025, controller233determines if a further gain change is required. That is, controller233determines if power level signal230has still not crossed target threshold238a. The time delay involved in performing this step contributes to the pause between successive incremental gain changes discussed above in connection withFIGS. 10B and 10A.

If step2025indicates no further gain change is required, then method2000stops. On the other hand, if step2025indicates a further gain change is required, then flow proceeds back to step2005, and the gain change process repeats. In this manner, method2000changes gain one step at a time, that is, in each iteration through steps2005-2025, until the power level signal230is at or near target threshold238a.

FIG. 21is a flow chart of another method of controlling the gain of VGA204, in amplifier assembly102. VGA204includes gain stages302connected in parallel with each other and that collectively establish an aggregate gain of the VGA. The VGA receives gain control signals120, each for controlling a gain of a corresponding one of parallel gain stages302.

In a first step2105, VGA204amplifies receive signal114in accordance with the aggregate gain to produce an amplified output signal210.

In a next step2110, power detector216produces detected power230indicative of a power of amplified signal210produced by the VGA. In a next step2115, comparator module218produces comparison result signal232indicative of a relative relationship between the detected power signal and thresholds224a-228a.

In a next step2120, ramp generator1502generates ramp signals1108and1110on command.

In a next step2125, reference signal generator1600generates reference signals1112and1114having fixed amplitudes.

In a next step2130, controller module220generates gain control signals120responsive to comparison result signal232, reference signals1112and1114, and ramp signals1108and1110(when the ramp signals are generated). Controller module220generates gain control signals120such that amplified output signal210maintains a substantially constant amplitude as the power of receive signal114varies over time.

FIG. 22is a block diagram of an example system2200, such as a CATV set-top box, in which amplifier assembly102may be used. Amplifier assembly102provides amplified signals118(1)-118(n) to corresponding individual tuners2204(1)-2204(2). Each signal118(i) includes a plurality of CATV channels, as mentioned above. Each tuner2204(i) selects a subset only, for example, one, of the many frequency channels presented in corresponding signal118(i). Each tuner2204(i) produces a signal2206(i) including the selected channel only.

Tuners2204(1)-2204(n) provide signals2206(1)-2206(n) to corresponding ones of demodulators2210(1)-2210(n), as depicted inFIG. 22. Each demodulator2210(i) demodulates the selected channel presented in its corresponding signal2206(i). Amplifier assembly102, tuners2204and demodulators2210may be all controlled by a controller, such as controller112discussed in connection withFIG. 2(but not shown inFIG. 22).

Due to the AGC operation of amplifier assembly102, as described above, each tuner-demodulator pair (2204(i)-2210(i)) advantageously receives a corresponding signal118(i) having (i) the plurality of frequency channels present in signal114, and (ii) a substantially constant aggregate power level, under fluctuating amplitude conditions of input signal114. The smooth and continuous gain change operation of amplifier assembly102advantageously avoids abrupt, disruptive power level discontinuities in signals118, and thus in signals2206. As a result, the gain changes in amplifier assembly102are transparent to demodulators2210. For example, demodulators2210can maintain a successful “lock” on, or tracking of, signals2206during gain changes in amplifier assembly102that compensate for substantial fluctuations in the power of input signal114. Another advantage of the amplifier assembly is that AGC induced gain changes are less frequent than in conventional systems, for the reasons mentioned above in connection withFIG. 17.

Another advantage is that the AGC operation of amplifier assembly102is autonomous, that is, the AGC in amplifier assembly operates without the need of any feedback signal, such as a receive power indicator, from either tuners2204or demodulators2210. Another advantage is that the power levels of signals118may be controlled individually using only one component in the system, namely, amplifier assembly102. Thus, each signal118(i) delivers the required power to each tuner-demodulator pair, and this required power may differ substantially between the tuner-demodulator pairs.

Further benefits of the invention include, at least, and by way of example and not by limitation, the following:

High bandwidth (i.e. good frequency performance).

Low distortion, especially for large composite channel signals found in cable TV. This is due to connecting the amplifier outputs to VDD via external inductors or ferrites and due to using a resistors and attenuators in the front end of the amplifier assembly (e.g., in the VGA).

Only enough gain reduction is used at the first amplifier stage of the amplifier assembly to insure the largest input signal condition can be met. This allows use of fewer gain stages in the VGA. Gain reduction is achieved through turning OFF gain stages.

Low noise figure.

Good input match (even at different gain settings).

Minimized distortion as the gain is changed. This is accomplished by fully turning OFF or ON all unused gain stages.

Power consumption is lowered as sequential gain stages of the VGA are turned OFF.

Noise figure degradation vs. gain reduction is less than 1:1 for lower gain settings, since attenuation comes at the output after the first 18 dB (done by turning OFF gain stages). This is important when the input signal level is high.

Increased AGC control range: More than 30 dB at 860 MHz and more than 35 dB at lower frequencies.

At a minimum, application is to cable modems, set-top box receivers and analog TV tuners.

Gain in one arrangement is controlled by a combination of selecting amplifiers connected to a tapped resistor ladder and by turning ON and OFF amplifier forming part of gain stages.

IC chip has been designed to use low-cost digital CMOS process. However this is not a limitation as other semiconductor processes could be used including bipolar (including SiGe), BiCMOS or Gallium Arsenide (GaAs) MESFET.

The present invention has been described above with the aid of circuit modules, functional building blocks, and method steps illustrating the performance of specified functions and relationships thereof. The boundaries of these circuit modules, functional building blocks and method steps have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One skilled in the art will recognize that these circuit modules, functional building blocks and modules can be implemented by discrete components including digital and/or analog circuits, application specific integrated circuits, processors executing appropriate software, hardware, firmware and the like or any combination thereof. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.