Electronic device and method for fabricating the same

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent document claims priority and benefits of Korean Patent Application No. 10-2014-0182569, entitled “ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME” and filed on Dec. 17, 2014, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

Recently, as electronic appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, semiconductor devices capable of storing information in various electronic appliances such as a computer, a portable communication device, and so on have been demanded in the art, and research has been conducted for the semiconductor devices. Such semiconductor devices include semiconductor devices which can store data using a characteristic that they are switched between different resistant states according to an applied voltage or current, for example, an RRAM (resistive random access memory), a PRAM (phase change random access memory), an FRAM (ferroelectric random access memory), an MRAM (magnetic random access memory), an E-fuse, etc.

SUMMARY

The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory capable of simplifying a process and improving the characteristic of a variable resistance element.

In one aspect, an electronic device is provided to include a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.

Implementations of the above electronic device may include one or more the following.

The barrier layer surrounds a part of the sidewall and the bottom of the metal wiring. The metal wiring, in addition to the portion formed in the groove of the barrier layer, includes a second portion formed over the interlayer dielectric layer, and the barrier layer includes an extension protruding above the interlayer dielectric layer to surround sidewalls of the second portion of the metal wiring. The barrier layer comprises a metal layer. The barrier layer comprises tantalum, and the metal wiring comprises copper. The metal wiring, in addition to the portion formed in the groove of the barrier layer, includes a second portion formed over the interlayer dielectric layer, and the device further includes an insulating layer in which the second portion of the metal wiring is formed. The electronic device may further comprising an insulating layer formed over the interlayer dielectric layer and having an air gap around the metal wiring. The electronic device may further comprising a bottom electrode contact between the substrate and the variable resistance element. The electronic device may further comprising: a source line contact formed in the interlayer dielectric layer to be adjacent to the variable resistance element and the top electrode; another barrier layer formed in the interlayer dielectric layer over the source line contact, and having a groove; and another metal wiring including a portion formed in the groove of another barrier layer and including another portion formed over the interlayer dielectric layer.

The electronic device may further include a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory unit in the microprocessor.

The electronic device may further include a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the resistance variable element is part of the cache memory unit in the processor.

The electronic device may further include a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the auxiliary memory device or the main memory device in the processing system.

The electronic device may further include a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the storage device or the temporary storage device in the data storage system.

The electronic device may further include a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory or the buffer memory in the memory system.

In another aspect, a method for fabricating an electronic device including a semiconductor memory, the method comprising: forming a variable resistance element over a substrate; burying a first interlayer dielectric layer between the variable resistance elements; burying a top electrode contact in a part of a contact hole formed through the first interlayer dielectric layer, such that the top electrode contact is in contact with the variable resistance element; forming a mold layer over the top electrode contact and the first interlayer dielectric layer; etching the mold layer to form a damascene structure; burying a metal wiring in the damascene structure; etching the mold layer to form a barrier layer on the sidewall and bottom of the metal wiring; and burying a second interlayer dielectric layer between the metal wirings.

In the other aspect, a method for fabricating an electronic device including a semiconductor memory, the method comprising: forming a first interlayer dielectric layer over a substrate, the first interlayer dielectric layer including a bottom electrode contact; forming a variable resistance element over the first interlayer dielectric layer such that the variable resistance element is in contact with the bottom electrode contact; burying a second interlayer dielectric layer between the variable resistance elements; burying a top electrode contact in a part of a contact hole formed through the second interlayer dielectric layer, such that the top electrode contact is in contact with the variable resistance element; burying a source line contact in a part of a contact hole formed through the first and second interlayer dielectric layers between the variable resistance elements, such that the source line contact is in contact with the substrate; forming a mold layer over the top electrode contact, the source line contact, and the second interlayer dielectric layer; etching the mold layer to form damascene structures; burying first and second metal wirings in the respective damascene structures; etching the mold layer to form a barrier layer on the sidewalls and bottoms of the first and second metal wirings; and burying a third interlayer dielectric layer between the first and second metal wirings.

In another aspect, an electronic device comprising a semiconductor memory including an array of unit cells, wherein each unit cell comprises: a substrate; a bottom electrode contact formed over the substrate through a first interlayer dielectric layer; variable resistance element formed over the first interlayer dielectric layer through a second interlayer dielectric layer, the variable resistance element being electrically coupled to the substrate through the bottom electrode contact and exhibiting different resistance states for storing data; a top electrode contact formed over the variable resistance element in the second interlayer dielectric layer; a metal wiring formed over the top electrode to be electrically coupled to the variable resistance element through the top electrode contact; and a barrier layer formed over the top electrode and surrounding at least a portion of the metal wiring.

Implementations of the above method may include one or more of the following.

The barrier layer is formed to surround the lower portion of the metal wiring. The barrier layer is formed to surround the entire metal wiring. The barrier layer has a variable thickness such that the top critical dimension of the metal wiring surrounded by the barrier layer is equal to the bottom critical dimension of the metal wiring surrounded by the barrier layer.

In another aspect, there is provided a method for fabricating an electronic device including a semiconductor memory. The method comprising: forming a first interlayer dielectric layer over a substrate; forming contact holes through the first interlayer dielectric layer; forming contact plugs to fill in corresponding parts of the contact holes; forming a mold layer over the contact plugs and the first interlayer dielectric layer; etching the mold layer to form damascene structures; forming metal wirings in the damascene structures; etching the mold layer to form barrier layers, each barrier layer forming on the sidewall and bottom of a corresponding metal wiring; and forming a second interlayer dielectric layer to fill spaces between the metal wirings.

Implementations of the above method may include one or more of the following.

The mold layer comprises a conductive material. The mold layer comprises a metal layer. The bottom surface of the damascene structure is positioned at a lower level than the top surface of the first interlayer dielectric layer. The etching of the mold layer includes performing a blanket etch process. The etching of the mold layer is performed such that the top surface of the barrier layer is positioned at the same level as the top surface of the first interlayer dielectric layer. The etching of the mold layer including inducing the mold layer to be re-deposited. The barrier layer surrounds at least a part of sidewalls of the metal wirings. The second interlayer dielectric layer has an air gap between the metal wirings. The mold layer includes a material capable of functioning as a seed layer of the metal wirings. The metal wirings include a material having a great etch selectivity with respect to the mold layer.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below in detail with reference to the accompanying drawings.

FIGS. 1 to 4are cross-sectional views of exemplary semiconductor devices in accordance with first to fourth implementations.

As illustrated inFIG. 1, a semiconductor device in accordance with a first implementation may include a first interlayer dielectric layer102, a contact hole (not illustrated), a contact plug103, a barrier layer104, a second interlayer dielectric layer105, and a metal wiring106. The first interlayer dielectric layer102may be formed over the substrate101having a predetermined structure formed therein. The contact hole may be formed through the first interlayer dielectric layer102. The contact plug103may be buried in a part of the contact hole. The barrier layer104may be formed over the contact plug103and buried in the remaining part of the contact hole. The second interlayer dielectric layer105may be formed over the first interlayer dielectric layer102including the barrier layer. The metal wiring106may be formed through the second interlayer dielectric layer105, and partially embedded in the barrier layer104.

The contact plug103, the barrier layer104, and the metal wiring106may include a conductive material. For example, the conductive material may include a metal containing material. The contact plug103may include tungsten (W), for example. The metal wiring106may include copper (Cu), for example. The barrier layer104may serve as a diffusion barrier and a seed layer for forming the metal wiring106. The barrier layer104may be formed to cover some portion of the sidewalls of the metal wiring106as well as the bottom of the metal wiring106. The barrier layer104may include tantalum (Ta), for example. In the first implementation, since the barrier layer104is locally formed only around the bottom portion of the metal wiring106, it is possible to minimize the increase in resistance of the metal wiring caused by the thickness of the barrier layer.

As illustrated inFIG. 2, a semiconductor device in accordance with a second implementation may include a first interlayer dielectric layer202, a contact hole (not illustrated), a contact plug203, a barrier layer204and206, a second interlayer dielectric layer205, and a metal wiring207. The first interlayer dielectric layer202may be formed over the substrate201having a predetermined structure formed therein. The contact hole may be formed through the first interlayer dielectric layer202. The contact plug203may be buried in a part of the contact hole. The barrier layer204and206may be formed over the contact plug203and buried in the remaining part of the contact hole. The second interlayer dielectric layer205may be formed over the first interlayer dielectric layer202including the barrier layer204. The metal wiring207may be formed through the second interlayer dielectric layer205, and partially embedded in the barrier layer204.

The contact plug203, the barrier layer204and206, and the metal wiring207may be formed of or include the same material as those of the first implementation. In the second implementation, since the barrier layer204and206is formed on the sidewalls of the metal wiring207as well as the bottom portion of the metal wiring207, it is possible to prevent a problem which may be caused due to diffusion between the adjacent metal wirings. Furthermore, since the barrier layer206formed on the sidewalls of the metal wiring has a smaller thickness than the barrier layer204formed at the bottom portion of the metal wiring, it is possible to minimize the increase in resistance of the metal wiring caused by the thickness of the barrier layer.

As illustrated inFIG. 3, a semiconductor device in accordance with a third implementation may include the same structure as that ofFIG. 2. Reference numerals ofFIG. 3may represent the same regions as those ofFIG. 2.

In the third implementation, the barrier layer306formed on the sidewalls of the metal wiring may have a thickness which gradually increases toward the bottom of the metal wiring307. The thickness of the barrier layer306may be gradually increased in such a manner that the top critical dimension (CD) of the metal wiring including the barrier layer306is equal to the bottom CD of the metal wiring including the barrier layer306. Please note that the area of the metal wiring does not decrease even with to the increase of the thickness of the barrier layer306, while the thickness of the barrier layer306may increase along the slope of the metal wiring. Thus, it is possible to prevent diffusion of the metal wiring without an increase of resistance depending on the area of the metal wiring.

As illustrated inFIG. 4, a semiconductor device in accordance with a fourth implementation may include a first interlayer dielectric layer402, a contact hole (not illustrated), a contact plug403, a barrier layer404and407, a metal wiring408, and a second interlayer dielectric layer406. The first interlayer dielectric layer402may be formed over the substrate401having a predetermined structure formed therein. The contact hole may be formed through the first interlayer dielectric layer402. The contact plug403may be buried in a part of the contact hole. The barrier layer404and407may be formed over the contact plug403and buried in the remaining part of the contact hole. The metal wiring408may be partially embedded in the barrier layer404. The second interlayer dielectric layer406may include an air gap between the metal wirings408.

In the fourth implementation, the barrier layer407formed on the sidewalls of the metal wiring may have the same structure as that ofFIG. 2. However, other implementations are also possible. For example, the barrier layer407may have the same structure as that ofFIG. 1 or 3.

In the fourth implementation, since the second interlayer dielectric layer406includes the air gap405between the adjacent metal wirings408, the insulation between the metal wirings408may be improved.

FIGS. 5A to 5Fare cross-sectional views illustrating an example of a method for fabricating the semiconductor device in accordance with the first implementation.FIGS. 5A to 5Fillustrate the method for fabricating the semiconductor device in accordance with the first implementation as shown inFIG. 1. However, the semiconductor devices having the barrier layer structure in accordance with the second to fourth implementations those are shown inFIGS. 2 to 4can be formed through the same method.

As illustrated inFIG. 5A, a first interlayer dielectric layer12may be formed over a substrate11. The substrate11may include a semiconductor substrate.

The first interlayer dielectric layer12may include an insulating material. The first interlayer dielectric layer12may include any one single layer including oxide, nitride, or oxynitride or a stacked structure thereof.

Then, a contact hole13may be formed to expose portions of the substrate11through the first interlayer dielectric layer12.

Then, a contact plug14may be buried in a part of the contact hole13. The contact plug14may include a conductive material. The contact plug14may include tungsten (W), for example. The contact plug14may be formed through the following series of processes: a conductive material is buried in the contact hole13, a planarization process is performed to expose the first interlayer dielectric layer12such that the adjacent conductive materials are isolated from each other, and a part of the conductive material is recessed to form a groove13A at the top of the conductive material. The planarization process may include a chemical mechanical polishing process or etch-back process, for example. Furthermore, the etching process may be performed under a condition of maximizing an etch selectivity between the conductive material and the insulating material, such that the damage of the first interlayer dielectric layer12is minimized during the process of forming the groove13A.

As illustrated inFIG. 5B, a mold layer15may be formed over the first interlayer dielectric layer12and the contact plug14. The mold layer15may be formed to perform a damascene process for forming a metal wiring during a subsequent process. In the present implementation, since a material capable of serving as a seed layer of the metal wiring is used for the mold layer15, an additional process for forming a barrier layer can be omitted, thereby increasing a process margin. Furthermore, since a barrier layer is not additionally formed after a damascene structure is formed, it is possible to prevent the reduction in CD of the metal wiring depending on the thickness of the barrier layer and the increase in resistance of the metal wiring.

The mold layer15may include a conductive material. The mold layer15may include tantalum (Ta), for example. The mold layer15may not only serve as a sacrificial layer for forming a damascene structure, but also serve as a seed layer during a metal wiring deposition process and a barrier layer for preventing diffusion of the metal wiring.

As illustrated inFIG. 5C, the mold layer15(refer toFIG. 5B) may be etched to form a damascene structure16. The etched mold layer will be represented by reference numeral15A. In the present implementation, the etching target may be adjusted such that the bottom surface of the damascene structure16is positioned at a lower level than the top surface of the first interlayer dielectric layer12.

As illustrated inFIG. 5D, a metal wiring17may be buried in the damascene structure16. The metal wiring17may be formed through the following series of processes: a conductive material is formed on the surface of the resultant structure so as to fill the damascene structure16, and the adjacent metal wirings17are electrically isolated from each other. The isolation process may be performed by etching or polishing the conductive material formed on the surface using a blanket etch process (for example, etch-back process) or a chemical mechanical polishing process, until the mold layer15A is exposed. The metal wiring17may include a conductive material. The metal wiring17may include copper (Cu), for example. Since the mold layer15A serves as a seed layer when the metal wiring17is formed, the deposition process can be easily performed. Furthermore, as the mold layer15A serves as a seed layer, a seed layer can be omitted when the metal wiring17is formed. Thus, a process margin can be secured. In addition, since the metal wiring17is buried in the entire damascene structure16, it is possible to prevent the decrease of resistance depending on the area (CD) of the metal wiring17.

As illustrated inFIG. 5E, the mold layer15A (refer toFIG. 5D) may be etched to form a barrier layer15B. At this time, the etching target may be adjusted to such an extent that the top surface of the barrier layer15B is positioned at the same level as the top surface of the first interlayer dielectric layer12. Since the metal wiring17has a structure that protrudes in a pillar shape and is partially embedded in the barrier layer15B, the etching process can be stably performed while a collapse is prevented.

Since Cu applied as the metal wiring17is a material having a great etch selectivity with respect to the mold layer, the metal wiring17is hardly damaged when the mold layer is etched. Thus, without a mask process, the mold layer can be sufficiently etched through an etch-back process. Furthermore, since the barrier layer15B does not reduce the region of the metal wiring17, it is possible to minimize the decrease in resistance of the metal wiring17due to the barrier layer15B.

In the second implementation as discussed with regard toFIG. 2, when the mold layer is etched, the etched material may be induced to be re-deposited. Thus, as illustrated inFIG. 2, the barrier layer206may also be formed on the sidewalls of the metal wiring. Furthermore, in the third implementation as discussed with regard toFIG. 3, when the mold layer is etched, the metal wiring may be applied as an etch mask to form the barrier layer306having a thickness which gradually increases toward the bottom.

As illustrated inFIG. 5F, a second interlayer dielectric layer18may be buried between the metal wirings17. The second interlayer dielectric layer18may include the same material as the first interlayer dielectric layer12. The second interlayer dielectric layer18may include an insulating material. The second interlayer dielectric layer18may include any single layer including oxide, nitride, or oxynitride or a stacked structure thereof.

In the fourth implementation as discussed with reference toFIG. 4, when the second interlayer dielectric layer406is formed, a material having poor step coverage may be used to form an air gap405between the metal wirings408.

FIG. 6is a cross-sectional view of an exemplary semiconductor device in accordance with a fifth implementation.

As illustrated inFIG. 6, the semiconductor device in accordance with the fifth implementation may include a first interlayer dielectric layer502, a bottom electrode contact503, a variable resistance element507, a top electrode contact508, a second interlayer dielectric layer509, a source line contact510, a barrier layer511, first and second metal wirings512and513, and a third interlayer dielectric layer514. The first interlayer dielectric layer502may be formed over a substrate501having a predetermined structure formed therein. The bottom electrode contact503may be formed through the first interlayer dielectric layer502so as to be in contact with the substrate501. The variable resistance element507may be formed over the bottom electrode contact503. The top electrode contact508may be formed to be in contact with the variable resistance element507. The second interlayer dielectric layer509may be buried in spaces between adjacent variable resistance elements507and in spaces between adjacent top electrode contacts508. The source line contact510may be formed through the first and second dielectric layers502and509between the variable resistance elements507so as to be in contact with the substrate. The barrier layer511may be formed over the top electrode contact508and the source line contact510. The first and second metal wirings512and513may be partially embedded in the respective barrier layers511. The third interlayer dielectric layer514may be buried between the metal wirings512and513.

The predetermined structure may include various access elements for controlling the supply of voltage or current to the variable resistance element507, for example, a transistor, or a diode and the like.

The first to third interlayer dielectric layers502to504may include any single layer including oxide, nitride, or oxynitride or a stacked structure thereof.

The bottom electrode contact503may be formed under the variable resistance element, and serve as a path for supplying a voltage or current to the variable resistance element. The bottom electrode contact503may include various conductive materials, for example, metal or metal nitride.

The variable resistance element507may include a material having a characteristic switched between different resistance states, according to a voltage or current applied to the variable resistance element507. The variable resistance element507may include various materials used for RRAM, PRAM, FRAM, or MRAM and the like. For example, the various materials may include a transition metal oxide, a metal oxide such as a perovskite-based material, a phase change material such as a chalcogenide-based material, a ferrodielectric material, or a ferromagnetic material. The variable resistance element507may have a single-layer structure or a multilayer structure which includes two or more layers so as to exhibit a variable resistance characteristic.

For example, the variable resistance element507may include a magnetic tunnel junction (MTJ) structure which includes a first magnetic layer504, a second magnetic layer506, and a tunnel barrier layer505interposed between the first and second magnetic layers504and506.

The first and second magnetic layers504and506may have a single-layer structure or multilayer structure including various ferromagnetic materials, for example, Fe—Pt alloy, Fe—Pd alloy, Co—Pd alloy, Co—Pt alloy, Co—Fe alloy, Fe—Ni—Pt alloy, Co—Fe—Pt alloy, or Co—Ni—Pt alloy. Any one of the first and second magnetic layers504and506may have a variable magnetization direction and serve as a free layer or storage layer, and the other of the first and second magnetic layers504and506may have a pinned magnetization direction and serve as a pinned layer or reference layer. The tunnel barrier layer505may change the magnetization direction of the free layer through electron tunneling. The tunnel barrier layer505may have a single-layer structure or multilayer structure including an oxide such as Al2O3, MgO, CaO, SrO, TiO, VO, or NbO.

When the magnetization directions of the first and second magnetic layers504and506are parallel to each other, the variable resistance element507may be set in a low-resistance state, and store data ‘0’, for example. On the other hand, when the magnetization directions of the first and second magnetic layers504and506are anti-parallel to each other, the variable resistance element507may be set in a high-resistance state, and store data ‘1’, for example. The variable resistance element507may further include various layers for securing the characteristic of the MTJ structure, in addition to the MTJ structure.

In another example, the variable resistance element507may include a metal oxide which contains oxygen vacancies of which the resistance can be changed through the behavior of the oxygen vacancies.

The top electrode contact508may serve to electrically couple the first metal wiring512and the variable resistance element507, and simultaneously serve as an electrode for the variable resistance element507. The top electrode contact508may be formed of or include the same material as the bottom electrode contact503.

The source line contact510may be formed between the variable resistance elements507, and electrically couple the switching element and the second metal wiring513. The source line contact510may be arranged so as to deviate from a plurality of variable resistance elements507by a predetermined distance.

The barrier layer511may be simultaneously formed on the top electrode contact508and the source line contact510. The barrier layer511may serve as a seed layer for depositing the first and second metal wirings512and513, and serve as an anti-diffusion layer for preventing diffusion of the first and second metal wirings512and513. The barrier layer511may include a metal material. The barrier layer511may include tantalum, for example. The barrier layer511may be buried in the second interlayer dielectric layer509, and surround the bottom and a part of the sidewall of the first and second metal wirings512and513.

The first and second metal wirings512and513may be partially embedded in the barrier layer511, and formed in a line type so as to be in contact with the top electrode contact508and the source line contact510, respectively. The first and second metal wirings512and513may be formed on the same line so as to be spaced at a predetermined interval from each other.

In the fifth implementation, since the barrier layer511is locally formed only at the bottoms of the first and second metal wirings512and513, it is possible to minimize the increase in resistance of the metal wiring depending on the thickness of the barrier layer. Although the electronic device ofFIG. 6has been illustrated that the barrier layer has the structure ofFIG. 1, present implementation is not limited thereto. For example, the electronic device may include the structures of the barrier layer and the metal wiring, illustrated inFIGS. 2 to 4.

FIGS. 7A to 7Jare cross-sectional views illustrating a method for fabricating the semiconductor device in accordance with the fifth implementation.

As illustrated inFIG. 7A, a substrate31having a predetermined structure formed therein may be prepared, the predetermined structure including a switching element (not illustrated) and the like. The switching element may serve to select a specific unit cell from a plurality of unit cells included in a semiconductor device, and include a transistor, or a diode and the like. One end of the switching element may be electrically coupled to a bottom electrode contact to be described below, and the other end of the switching element may be electrically coupled to a source line through a source line contact to be described below.

Then, a first interlayer dielectric layer32may be formed over the substrate31. The first interlayer dielectric layer32may include any single layer including oxide, nitride, or oxynitride or a stacked structure thereof.

A contact hole (not illustrated) may be formed to expose the substrate31through the first interlayer dielectric layer32. The contact hole may be formed through the following process: a mask pattern (not illustrated) is formed over the first interlayer dielectric layer32and the first interlayer dielectric layer32is etched using the mask pattern as an etch barrier such that the substrate31is exposed.

Then, a bottom electrode contact33may be buried in the contact hole. The bottom electrode contact33may serve to couple the substrate31to a variable resistance element that will be formed in a subsequent process. The bottom electrode contact33may be formed through the following series of processes: a conductive material is formed on the surface of the resultant structure so as to fill the contact hole, an isolation process is performed to electrically isolate the adjacent bottom electrode contacts33from one another, and the conductive material is recessed by a predetermined thickness. The isolation process may be performed by etching or polishing the conductive material formed on the surface using a blanket etch process (for example, etch-back process) or a chemical mechanical polishing process, until the first interlayer dielectric layer32is exposed. The bottom electrode contact33may include a semiconductor layer or metallic layer.

As illustrated inFIG. 7B, a variable resistance element37may be formed over the bottom electrode contact33.FIG. 7Billustrates that the variable resistance element37has the same CD as the bottom electrode contact33. However, other implementations are also possible. For example, the CD of the variable resistance element37may be adjusted to be greater or smaller than the CD of the bottom electrode contact33. The variable resistance element37may further include an electrode layer (not illustrated) at the top and bottom thereof.

The variable resistance element37may have a characteristic switched between different resistance states (or different resistance values), according to a bias applied through the top electrode or/and bottom electrode (for example, voltage or current). Such a characteristic allows the variable resistance element37to be utilized in various fields. For example, the variable resistance element37may be used as a data storage for storing data.

The variable resistance element37may exhibit a variable resistance characteristic through a bias applied through the top electrode or/and bottom electrode. For example, the variable resistance element37may include a phase change material. The phase change material may include a chalcogen compound. The phase change material may change to an amorphous state or crystal state according to an external stimulus (for example, voltage or current), and have a characteristic of switching between different resistance states. Furthermore, the variable resistance element37may include a metal oxide. The metal oxide may include a transition metal oxide (TMO), or a perovskite-based oxide and the like. The metal oxide may contain vacancies therein, and have a characteristic switched between different resistance states through formation and disappearance of a conductive path depending on the behavior of the vacancies, caused by an external stimulus. Furthermore, the variable resistance element37may have a stacked structure including two magnetic layers34and36and a tunnel barrier layer35interposed therebetween. The stacked structure having the tunnel barrier layer interposed between the two magnetic layers may be referred to as a magnetic tunnel junction (MTJ). For example, when the magnetization directions of the two magnetic layers34and36are equal to each other (or parallel to each other), the variable resistance element37may have a low resistance state, and when the magnetization directions of the two magnetic layers34and36are different from each other (or anti-parallel to each other), the variable resistance element37may have a high resistance state. However, the present implementation is not limited thereto, and the variable resistance element37may include any materials as long as they can satisfy a variable resistance characteristic switched between different resistance states according to a bias applied to the top electrode or/and bottom electrode thereof.

Then, a spacer (not illustrated) may be formed on the sidewalls of the variable resistance element37.

As illustrated inFIG. 7C, a second interlayer dielectric layer38may be formed over the first interlayer dielectric layer32. The second interlayer dielectric layer38may be formed with a sufficient thickness to fill the space between the variable resistance elements37. For example, the second interlayer dielectric layer38may be formed in such a manner that the top surface of the second interlayer dielectric layer38is set at a higher level than the top surface of the variable resistance element37. The height of the second interlayer dielectric layer38may be determined in consideration of the height of a top electrode contact that will be formed in a subsequent process. The second interlayer dielectric layer38may be formed of or include the same material as the first interlayer dielectric layer32. The second interlayer dielectric layer38may include any single layer including oxide, nitride, or oxynitride or a stacked structure thereof.

Then, a top electrode contact39may be formed through the second interlayer dielectric layer38over the variable resistance element37, and coupled to the variable resistance element37. The top electrode contact39may be formed by the following process: the second interlayer dielectric layer38is etched to form a contact hole exposing the top surface of the variable resistance element37and a conductive material is buried in the contact hole. The top electrode contact39may serve to electrically couple the variable resistance element37to a first metal wiring to be formed through a subsequence process, and simultaneously serve as an electrode for the variable resistance element37. The top electrode contact39may be formed of or include the same material as the bottom electrode contact33. For example, the top electrode contact39may include tungsten (W), for example.

As illustrated inFIG. 7D, a source line contact40may be formed through the first and second interlayer dielectric layers32and38between the variable resistance elements37so as to be in electrically contact with the substrate. The source line contact40may serve to electrically couple the switching element to a second metal wire. The source line contact40may be arranged so as to deviate from a plurality of variable resistance elements37by a predetermined distance.

As illustrated inFIG. 7E, the top electrode contact39and the source line contact40may be partially recessed to form grooves41. At this time, the etching process may be performed under a condition of maximizing an etch selectivity between a conductive material and an insulating material, such that the damage of the second interlayer dielectric layer38is minimized.

As illustrated inFIG. 7F, a mold layer42may be formed over the top electrode contact39, the source line contact40, and the second interlayer dielectric layer38. The mold layer42may serve as a sacrificial layer for performing a damascene process for forming a metal wiring during a subsequent process. In the present implementation, since the mold layer42is formed of or includes a material capable of serving as a seed layer of the metal wiring, an additional process for a barrier layer can be omitted, thereby increasing a process margin. Thus, it is possible to prevent the reduction in CD of the metal wiring depending on the thickness of the barrier layer and to prevent the increase in resistance of the metal wiring depending on the reduction in CD of the metal wiring.

The mold layer42may include a conductive material. The mold layer15may include tantalum (Ta), for example. The mold layer42may not only serve as a sacrificial layer for forming the damascene structure, but also serve as a seed layer during a deposition process for the metal wiring and a barrier layer for preventing diffusion of the metal wiring.

As illustrated inFIG. 7G, the mold layer42(refer toFIG. 7F) may be etched to form damascene structures43. The etched mold layer will be represented by reference numeral42A. In the present implementation, the etching target may be adjusted such that the bottom surfaces of the damascene structures43are positioned at a lower level than the top surface of the second interlayer dielectric layer38.

As illustrated inFIG. 7H, first and second metal wirings44and45may be buried in the damascene structure43. The first and second metal wirings44and45may be formed through the following series of processes: a conductive material is formed on the surface of the resultant structure so as to fill the damascene structure43, and an isolation process is performed to electrically isolate the adjacent metal wirings44and45. The isolation process may be performed by etching or polishing the conductive material formed on the surface using a blanket etch process (for example, etch-back process) or a chemical mechanical polishing process, until the mold layer42A is exposed.

The first and second metal wirings44and45may include a conductive material. For example, the first and second metal wirings44and45may include Cu. Since the mold layer42A serves as a seed layer when the first and second metal wirings44and45are formed, the deposition process can be easily performed. Furthermore, as the mold layer42A serves as a seed layer, a seed layer can be omitted when the first and second metal wirings44and45are formed. Thus, a process margin can be secured. In addition, since the first and second metal wirings44and45are buried in the entire damascene structure43, it is possible to prevent the decrease of resistance depending on the area (CD) of the first and second metal wirings44and45.

As illustrated inFIG. 7I, the mold layer42A (refer toFIG. 7H) may be etched to form a barrier layer42B. At this time, the etching target may be adjusted such that the top surface of the barrier layer42B is positioned at the same level as the top surface of the second interlayer dielectric layer38. Since the first and second metal wirings44and45have a structure that protrudes in a pillar shape and is partially embedded in the barrier layer42B, the etching process can be stably performed and a collapse is prevented.

Since Cu applied as the first and second metal wirings44and45is a material having a great etch selectivity with respect to the mold layer, the first and second metal wirings44and45are hardly damaged when the mold layer is etched. Thus, without a mask process, the mold layer can be sufficiently etched through an etch-back process. Furthermore, since the barrier layer42B does not reduce the regions of the first and second metal wirings44and45, it is possible to minimize the decrease in resistance of the first and second metal wirings44and45due to the barrier layer42B.

In another implementation, when the mold layer is etched, the etched material may be induced to be re-deposited. Thus, as illustrated inFIG. 2, the barrier layer206may also be formed on the sidewalls of the metal wiring. Furthermore, when the mold layer is etched, the metal wiring may be applied as an etch mask to form the barrier layer306having a thickness which gradually increases toward the bottom.

As illustrated inFIG. 7J, a third interlayer dielectric layer46may be buried between the first and second metal wirings44and45. The third interlayer dielectric layer46may include the same material as the second interlayer dielectric layer38. The third interlayer dielectric layer46may include an insulating material. The third interlayer dielectric layer46may include any single layer including oxide, nitride, or oxynitride or a stacked structure thereof.

In another implementation, when the second interlayer dielectric layer406is formed, a material having poor step coverage may be used to form an air gap405between the metal wirings408.

In accordance with the implementations, it is possible to simplify the process and to improve the characteristic of the variable resistance element.

The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a range of devices or systems.FIGS. 8-12provide some examples of devices or systems that can implement the memory circuits disclosed herein.

FIG. 8is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 8, a microprocessor1000may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor1000may include a memory unit1010, an operation unit1020, a control unit1030, and so on. The microprocessor1000may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit1010is a part which stores data in the microprocessor1000, as a processor register, register or the like. The memory unit1010may include a data register, an address register, a floating point register and so on. Besides, the memory unit1010may include various registers. The memory unit1010may perform the function of temporarily storing data for which operations are to be performed by the operation unit1020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit1010may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory unit1010may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the memory unit1010may become easy and the reliability and yield of the memory unit1010may be improved. As a consequence, operating characteristics of the microprocessor1000may be improved.

The operation unit1020may perform four arithmetical operations or logical operations according to results that the control unit1030decodes commands. The operation unit1020may include at least one arithmetic logic unit (ALU) and so on.

The control unit1030may receive signals from the memory unit1010, the operation unit1020and an external device of the microprocessor1000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor1000, and execute processing represented by programs.

The microprocessor1000according to the present implementation may additionally include a cache memory unit1040which can temporarily store data to be inputted from an external device other than the memory unit1010or to be outputted to an external device. In this case, the cache memory unit1040may exchange data with the memory unit1010, the operation unit1020and the control unit1030through a bus interface1050.

FIG. 9is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring toFIG. 9, a processor1100may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor1100may include a core unit1110which serves as the microprocessor, a cache memory unit1120which serves to storing data temporarily, and a bus interface1130for transferring data between internal and external devices. The processor1100may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The core unit1110of the present implementation is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit1111, an operation unit1112and a control unit1113.

The memory unit1111is a part which stores data in the processor1100, as a processor register, a register or the like. The memory unit1111may include a data register, an address register, a floating point register and so on. Besides, the memory unit1111may include various registers. The memory unit1111may perform the function of temporarily storing data for which operations are to be performed by the operation unit1112, result data of performing the operations and addresses where data for performing of the operations are stored. The operation unit1112is a part which performs operations in the processor1100. The operation unit1112may perform four arithmetical operations, logical operations, according to results that the control unit1113decodes commands, or the like. The operation unit1112may include at least one arithmetic logic unit (ALU) and so on. The control unit1113may receive signals from the memory unit1111, the operation unit1112and an external device of the processor1100, perform extraction, decoding of commands, controlling input and output of signals of processor1100, and execute processing represented by programs.

The cache memory unit1120is a part which temporarily stores data to compensate for a difference in data processing speed between the core unit1110operating at a high speed and an external device operating at a low speed. The cache memory unit1120may include a primary storage section1121, a secondary storage section1122and a tertiary storage section1123. In general, the cache memory unit1120includes the primary and secondary storage sections1121and1122, and may include the tertiary storage section1123in the case where high storage capacity is required. As the occasion demands, the cache memory unit1120may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit1120may be changed according to a design. The speeds at which the primary, secondary and tertiary storage sections1121,1122and1123store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections1121,1122and1123are different, the speed of the primary storage section1121may be largest. At least one storage section of the primary storage section1121, the secondary storage section1122and the tertiary storage section1123of the cache memory unit1120may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit1120may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the cache memory unit1120may become easy and the reliability and yield of the cache memory unit1120may be improved. As a consequence, operating characteristics of the processor1100may be improved.

Although it was shown inFIG. 9that all the primary, secondary and tertiary storage sections1121,1122and1123are configured inside the cache memory unit1120, it is to be noted that all the primary, secondary and tertiary storage sections1121,1122and1123of the cache memory unit1120may be configured outside the core unit1110and may compensate for a difference in data processing speed between the core unit1110and the external device. Meanwhile, it is to be noted that the primary storage section1121of the cache memory unit1120may be disposed inside the core unit1110and the secondary storage section1122and the tertiary storage section1123may be configured outside the core unit1110to strengthen the function of compensating for a difference in data processing speed. In another implementation, the primary and secondary storage sections1121,1122may be disposed inside the core units1110and tertiary storage sections1123may be disposed outside core units1110.

The bus interface1130is a part which connects the core unit1110, the cache memory unit1120and external device and allows data to be efficiently transmitted.

The processor1100according to the present implementation may include a plurality of core units1110, and the plurality of core units1110may share the cache memory unit1120. The plurality of core units1110and the cache memory unit1120may be directly connected or be connected through the bus interface1130. The plurality of core units1110may be configured in the same way as the above-described configuration of the core unit1110. In the case where the processor1100includes the plurality of core unit1110, the primary storage section1121of the cache memory unit1120may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the secondary storage section1122and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130. The processing speed of the primary storage section1121may be larger than the processing speeds of the secondary and tertiary storage section1122and1123. In another implementation, the primary storage section1121and the secondary storage section1122may be configured in each core unit1110in correspondence to the number of the plurality of core units1110, and the tertiary storage section1123may be configured outside the plurality of core units1110in such a way as to be shared through the bus interface1130.

The processor1100according to the present implementation may further include an embedded memory unit1140which stores data, a communication module unit1150which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit1160which drives an external memory device, and a media processing unit1170which processes the data processed in the processor1100or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor1100may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units1110and the cache memory unit1120and with one another, through the bus interface1130.

The embedded memory unit1140may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), a memory with similar functions.

The memory control unit1160is to administrate and process data transmitted between the processor1100and an external storage device operating according to a different communication standard. The memory control unit1160may include various memory controllers, for example, devices which may control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit1170may process the data processed in the processor1100or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit1170may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 10is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 10, a system1200as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations for data. The system1200may include a processor1210, a main memory device1220, an auxiliary memory device1230, an interface device1240, and so on. The system1200of the present implementation may be various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor1210may decode inputted commands and processes operation, comparison, etc. for the data stored in the system1200, and controls these operations. The processor1210may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device1220is a storage which can temporarily store, call and execute program codes or data from the auxiliary memory device1230when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device1220may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the main memory device1220may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the main memory device1220may become easy and the reliability and yield of the main memory device1220may be improved. As a consequence, operating characteristics of the system1200may be improved.

Also, the main memory device1220may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device1220may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device1230is a memory device for storing program codes or data. While the speed of the auxiliary memory device1230is slower than the main memory device1220, the auxiliary memory device1230can store a larger amount of data. The auxiliary memory device1230may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device1230may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the auxiliary memory device1230may become easy and the reliability and yield of the auxiliary memory device1230may be improved. As a consequence, operating characteristics of the system1200may be improved.

Also, the auxiliary memory device1230may further include a data storage system (see the reference numeral1300ofFIG. 10) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device1230may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral1300ofFIG. 10) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device1240may be to perform exchange of commands and data between the system1200of the present implementation and an external device. The interface device1240may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 11is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 11, a data storage system1300may include a storage device1310which has a nonvolatile characteristic as a component for storing data, a controller1320which controls the storage device1310, an interface1330for connection with an external device, and a temporary storage device1340for storing data temporarily. The data storage system1300may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device1310may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on.

The controller1320may control exchange of data between the storage device1310and the interface1330. To this end, the controller1320may include a processor1321for performing an operation for, processing commands inputted through the interface1330from an outside of the data storage system1300and so on.

The interface1330is to perform exchange of commands and data between the data storage system1300and the external device. In the case where the data storage system1300is a card type, the interface1330may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system1300is a disk type, the interface1330may be compatible with interfaces, such as IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface1330may be compatible with one or more interfaces having a different type from each other.

The temporary storage device1340can store data temporarily for efficiently transferring data between the interface1330and the storage device1310according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device1340for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The temporary storage device1340may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the storage device1310or the temporary storage device1340may become easy and the reliability and yield of the storage device1310or the temporary storage device1340may be improved. As a consequence, operating characteristics and data storage characteristics of the data storage system1300may be improved.

FIG. 12is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring toFIG. 12, a memory system1400may include a memory1410which has a nonvolatile characteristic as a component for storing data, a memory controller1420which controls the memory1410, an interface1430for connection with an external device, and so on. The memory system1400may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory1410for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory1410may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the memory1410may become easy and the reliability and yield of the memory1410may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system1400may be improved.

Also, the memory1410according to the present implementation may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller1420may control exchange of data between the memory1410and the interface1430. To this end, the memory controller1420may include a processor1421for performing an operation for and processing commands inputted through the interface1430from an outside of the memory system1400.

The interface1430is to perform exchange of commands and data between the memory system1400and the external device. The interface1430may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface1430may be compatible with one or more interfaces having a different type from each other.

The memory system1400according to the present implementation may further include a buffer memory1440for efficiently transferring data between the interface1430and the memory1410according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory1440for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The buffer memory1440may include a variable resistance element formed over a substrate; a top electrode formed over the variable resistance element; an interlayer dielectric layer buried between the variable resistance element and the top electrode, and including a contact hole to expose the top electrode; a barrier layer formed over the top electrode so as to fill a part of the contact hole, and having a groove; and a metal wiring connected to the groove of the barrier layer. Through this, a fabrication process of the buffer memory1440may become easy and the reliability and yield of the buffer memory1440may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system1400may be improved.

Moreover, the buffer memory1440according to the present implementation may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory1440may not include the semiconductor devices according to the implementations, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

Features in the above examples of electronic devices or systems inFIGS. 8-12based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

Only a few implementations and examples are described. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.