Structure for reducing pre-charge voltage for static random-access memory arrays

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

BACKGROUND

The invention relates generally to a read pre-charge level of SRAM cells, and more specifically, to memory cell arrangements of SRAM cell groups. The invention relates further to a related design structure.

SRAM cells are often arranged in a domino-logic structure in which two or more SRAM (static random access memory) cells are connected in parallel to local bit-lines. An amplifier between local bit-lines and a shared global bit-line helps to separate the local bit-lines from the global bit-line. Typically, both, the local and the global bit-lines may be pre-charged high before a read operation, and may be discharged, or “pulled-down,” to ground during a read operation. This may enable a higher read rate than detecting the status of the global bit-line directly. A particular cell may be selected for reading by activating the cell's word line. If the discharged local bit-line is the one that is coupled to the global bit-line, a discharge of the local bit-line may activate logic that discharges the global bit-line.

Using this mechanism for detecting a status of a SRAM cell, it may not be required to pre-charge a local bit-line and/or a global bit-line to the full amount of Vdd (also known as the power supply voltage). In other words, a full swing pre-charge may not be required.

Other documents have been dealt with this area. E.g., U.S. Pat. No. 8,947,970 B2 discloses “a memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted.”

US Patent Application 2010/0296354-A1 discloses a static random access memory which includes “a memory cell connected to a pair of bitlines and supplied with the power supply voltage from a first power supply[,] a pre-charge circuit connected with the pair of bitlines . . . and a voltage reducing circuit connected between the precharge circuit and the first power supply.”

However, a problem related to the global bit-line remains. The global bit-lines build an intrinsic capacitor. Because a plurality of the above-mentioned amplifiers may be connected to the global bit-line, the global bit-line requires a lot of pre-charging power during a read operation of SRAM cells. As the SRAM cell may be pre-charged in a first phase of a read operation and discharged in an evaluation phase, depending on the SRAM cells content, about 50% of global bit-lines are charged and/or discharged during every memory cycle. A power equivalent to the operation frequency times the effective capacitor of the global bit-lines times the power supply voltage (Vdd) times the pre-charge voltage may be required. This may contribute enormously to the power consumption of an SRAM array. Because SRAM cells are often used as level-1 or level-2 caches in processors, the power consumption of these SRAM arrays contributes significantly to the power consumption of the processor.

Hence, there may be a need for a reduction of the amount of power required to pre-charge the global bit-lines in the first phase of a read operation.

SUMMARY

This need may be addressed by a memory cell arrangement of Static Random-Access Memory (SRAM) cell groups, and design structure according to the independent claims.

According to one aspect of the present invention, a memory cell arrangement of SRAM cell groups may be provided. In each of the groups, multiple SRAM cells may be connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers may be connected to a shared global bit-line which may be connected to a pre-charge circuit. The pre-charge circuit may be adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit may include a limiter circuit. The limiter circuit may include a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage. An evaluation and translation circuit may be connected to the pre-charge regulator circuit and the global bit-line to compensate for leakage current of the global bit-line without changing its voltage level.

According to another aspect of the present invention, a design structure may be provided. The design structure may be tangibly embodied in a machine-readable storage medium used in a design process of a memory cell arrangement of SRAM cell groups. The design structure may have elements that, when processed in a semiconductor manufacturing facility, may produce a memory cell arrangement of SRAM cell groups in which in each of the groups multiple SRAM cells may be connected to an input of a local read amplifier by at least one common local bit-line, and in which outputs of the amplifiers are connected to a shared global bit-line. The shared global bit-line may be connected to a pre-charge circuit, and the pre-charge circuit may be adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit may comprise a limiter circuit which may comprise a pre-charge regulator circuit which may be connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the shared global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

The proposed memory cell arrangement of SRAM cell groups may offer a couple of advantages and technical effects:

The proposed memory cell arrangement of SRAM cell groups is not dependent on any specific SRAM cell design. For example, six transistor 1-bit SRAM cells may be used as well as 8-transistor 1-bit SRAM cells. Typically, field effect transistors (FET) may be used. They may be p-type FETs or n-type FETs or a combination of both. The inventive concept may also be applied to bipolar based SRAM cells. The pre-charge level of the shared global bit-line may not depend on any switching threshold of a CMOS inverter and may thus not be fixed but may be programmable depending on environmental parameters, e.g., the power supply voltage, the temperature of the chip, or the operating frequency. Thus, the pre-charge level may stay constant even if the power supply voltage may change. Thus, the pre-charge level of the shared global bit-line may depend only on a reference voltage Vref, which may allow for a lower pre-charge level even if the power supply voltage may increase. This may result in an even higher power saving.

Additionally, no history effects have to be dealt with because the shared global bit-line keeper part of the evaluation and translation circuits maintains the pre-charge level. Moreover, the pre-charge level may be controlled for each shared global bit-line independently. The global bit-lines may be single-ended global bit-lines.

Because of a decoupling of the pre-charge circuit and the SRAM cells, there are no dependencies to the SRAM cell characteristics.

It may also be noted that the pre-charge level of the global bit-line may be lower than the power supply voltage minus a threshold value of, e.g., a CMOS inverter and, in particular, below half of Vdd. A clear effect is that more power can be saved during operation if compared to known technologies.

In the following, additional embodiments of the memory cell arrangement of SRAM cell groups will be described.

According to one preferred embodiment of the memory cell arrangement of SRAM cell groups, the programmable pre-charge voltage is below half of a value of a power supply voltage Vdd. This has the advantage of a higher power saving effect if compared to technologies able to reduce the pre-charge level of the shared global bit-line to half of Vdd. The lower a pre-charge level of the global bit-line may be with a stable operation, the more power may be saved. A skilled person will appreciate that every additional milliwatt of saved power is instrumental in making SRAM cells in SRAM chips or as part of processors more efficient.

According to another preferred embodiment of the memory cell arrangement of SRAM cell groups, the pre-charge regulator circuit may comprise a 1st p-FET connected with its source to the power supply voltage Vdd and its drain to a first terminal of a pre-charge switch. This pre-charge switch may be connected with its second terminal to the shared global bit-line. A 1st n-FET may be connected with its source to the first terminal of the pre-charge switch, wherein a drain of the 1st n-FET may be connected to a gate of the 1st p-FET as well as to a first terminal of a first programmable resistor which is connected with its second terminal to the power supply voltage Vdd. A gate of the 1st n-FET may be connected to a voltage Vref signal.

It may be noted that the first resistor may be interpreted as an equivalent circuit diagram for a transistor or FET having a preset voltage connected to its gate. Thus, this may be seen as a programmable resistor.

It may also be noted that the voltage Vref may define to which level the shared global bit-line may be pre-charged before a second part of a read cycle of an activated—e.g., by the associated word line—SRAM cell.

According to another preferred embodiment of the memory cell arrangement of SRAM cell groups, the evaluation and translation circuit may comprise a 2nd n-FET which may be connected with its source to the shared global bit-line and with its drain to a first terminal of a second programmable resistor which may be connected with its second terminal to the power supply voltage Vdd. A gate of the 2nd n-FET may be connected to the Vref signal, and a global bit-line out terminal may be connected to the drain of the 2nd n-FET.

Similar to the first resistor, the second resistor may be seen as an equivalent circuit diagram for a transistor or FET having a preset voltage connected to its gate. Thus, this may also be seen as a programmable resistor.

According to an additional embodiment of the memory cell arrangement of SRAM cell groups, the Vref signal may be adapted for controlling a pre-charge level of the shared global bit-line. Thus, the pre-charge level may be controllable independently of the power supply voltage. The pre-charge level of the shared global bit-line can be controlled independently such that a lowest possible pre-charge level may be used which ensures a stable operation of the SRAM cell read operation.

According to an advantageous embodiment of the memory cell arrangement of SRAM cell groups, the pre-charge regulator circuit may comprise a 2nd p-FET connected with its drain to the shared global bit-line and its source to the power supply voltage Vdd. A gate of a 2nd p-FET may be connected to a drain of a 3rd p-FET transistor which source may be connected to the power supply voltage Vdd. A drain of a 4th p-FET may also be connected to the gate of the second p-FET and which source may be connected to the power supply voltage Vdd. A 3rd n-FET may also be connected with its drain to the gate of the 2nd p-FET and with its source to a drain of a 4th n-FET which source may be connected to the shared global bit-line.

A gate of the 4th n-FET and a gate of the 3rd p-FET may together be connected to a global bit-line pre-charge line GPCHG. A gate of the 3rd n-FET may be connected to a Vref line, and the gate of the 4th p-FET is connected to a Vbias-p line.

With this, the pre-charge regulator circuit is active during a “high” phase and inactive during a “low” phase of GPCHG. If the pre-charge regulator circuit is active, the 6th p-FET is controlled such that the more the voltage level of the global bit-line deviates from the pre-charge level set by means of the reference voltage Vref, the more current the 6thp-FET supplies to the global bit-line. When the programmed pre-charge level is reached, the current drive capability of the 6th p-FET is largely reduced. In this state, the 6th p-FET will only compensate for the shared global bit-line leakage to keep the pre-charged level constant. If the pre-charge regulator circuit is inactive, the 6th p-FET is turned off.

According to one permissive embodiment of the memory cell arrangement of SRAM cells a drain of a 5th n-FET may be connected to the shared global bit-line and connected with its source connected to ground. A gate of the 5th n-FET may be connected to a voltage Vbias-n signal adapted for keeping the pre-charge regulator circuit and the evaluation and translation circuit in stable working conditions. This circuit may ensure a stable charge level of the shared global bit-line even in the case if no or only weak leak currents are present.

According to one additional embodiment of the memory cell arrangement of SRAM cell groups, the evaluation and translation circuit may comprise a 6th n-FET connected with its source to the shared global bit-line and with its drain to the global bit-line out. A 5th p-FET may be connected with its drain to the global bit-line out terminal and with its source to the power supply voltage Vdd. A 6th p-FET may be connected with its source to the power supply voltage Vdd, and with its drain to a source of a 7th p-FET which is connected with its drain to the global bit-line out terminal.

Furthermore, a gate of the 7th p-FET may be connected to a drain of an 8th p-FET which may be connected with its source to the power supply voltage Vdd. And, the gate of the 7th p-FET may also be connected to a drain of a 7th n-FET which may be connected with its source to ground.

In this embodiment, the Vref signal may be connected to a gate of the 6th n-FET, the Vbias-p signal may be connected to a gate of the 6th p-FET, and an inverted signal of the global bit-line pre-charge signal GPCHGN may be connected to a gate of the 5th p-FET.

This embodiment may be seen as a first implementation of the evaluation and translation circuit. The 6th n-FET may separate the shared global bit-line which has a high capacity and the global bit-line out line which has a low capacity compared to the shared global bit-line.

The 7th p-FET, the 8th p-FET and the 7th n-FET may be seen as a feedback circuit that interrupts the path from Vdd through the 6th and 7th p-FET to the a global bit-line out (terminal) in order to prevent a cross-current from Vdd to the pull-down device when a read amplifier tries to discharge the shared global bit-line and thus, to save power and accelerate the evaluation phase.

With the 6th n-FET connected with its source to the shared global bit-line and with its drain to the global bit-line out terminal, a separation between the shared global bit-line and the global bit-line out terminal may be achieved. This way, the shared global bit-line may allow a much lower pre-charge level than detectable at the global bit-line out terminal. The evaluation and translation circuit may enable the pre-charge level translation.

According to another embodiment of the memory cell arrangement of SRAM cell groups, the evaluation and translation circuit may comprise an 8th n-FET which may be connected with its source to the shared global bit-line and with its drain to a source of a 9th n-FET, which is connected with its drain to a 9th p-FET, which may be connected with its source to the power supply voltage Vdd. A 10th p-FET may be connected with its source to the power supply voltage Vdd and with its drain to the drain of the 9th p-FET. An 11th p-FET may be connected with its source to the power supply voltage Vdd and with its gate to the drain of the 9th n-FET.

A drain of the 11th p-FET may be connected to the global bit-line out terminal, a drain of a 10th n-FET and a drain of an 11th n-FET may be connected to the global bit-line out terminal and, a source of the 10th n-FET and a source of the 11th n-FET may be connected to ground Vss.

The Vref signal may be connect to a gate of the 9th n-FET, the Vbias-p signal may be connected to a gate of the 9th p-FET, an inverted signal of the global bit-line pre-charge signal GPCHGN may be connected to a gate of the 10th p-FET, and the global bit-line pre-charge signal GPCHG may be connected to a gate of the 10th n-FET, wherein the Vbias-n signal may be connected to a gate of the 11th n-FET.

This embodiment may represent a second, alternative implementation of the evaluation and translation circuit. It may be faster than the first embodiment of the evaluation and translation circuit (as discussed above). The first embodiment may save more power and may be less complex.

According to another embodiment of the memory cell arrangement of SRAM cell groups, the evaluation and translation circuit may comprise a 12th n-FET which may be connected with its source to the shared global bit-line and with its drain to a source of a 13th n-FET; this 13th n-FET may be connected with its drain to a 12th p-FET which may be connected with its source to the power supply voltage Vdd.

A 13th p-FET may be connected with its source to the power supply voltage Vdd and with its drain to the drain of the 12th p-FET. A 14th p-FET may be connected with its source to the power supply voltage Vdd and with its gate to the drain of the 13th n-FET. A 14th n-FET may be connected with its drain to a drain of the 14th p-FET and with its source to a drain of a 15th n-FET which is connected with its source to ground. A 16th n-FET may be connected with its drain to the drain of the 14th p-FET and with its source to ground.

An inverter, which may be connected with its input to the drain of the 14th FET and with its output to the global bit-line out terminal, may also be part of this embodiment. Also, a 15th p-FET may be connected with it source to the power supply voltage Vdd and with its drain to the drain of the 14 p-FET and which is connected with its gate to the global bit-line out terminal. A gate of the 14th n-FET may also be connected to the global bit-line out terminal.

The Vref signal may be connected to a gate of the 13th n-FET, the Vbias-p signal may connected to a gate of the 12th p-FET, an inverted signal of the global bit-line pre-charge signal GPCHGN may be connected to a gate of the 13th p-FET, the global bit-line pre-charge signal GPCHG may be connected to a gate of the 16th n-FET, and the Vbias-n signal may be connected to a gate of the 15th n-FET.

This embodiment may represent a third alternative for the evaluation and translation circuit. It may represent a good compromise between the first implementation and the second implementation, as its operational speed may be in-between the first and the second implementation of the evaluation and translation circuit, as discussed above. On the other side, it may save more power than the second implementation embodiment of the evaluation and translation circuit. Thus, a designer may have a choice between different options of the same basic principle, namely reducing the pre-charge level of the shared global bit-line as much as possible in a given environment.

According to a further optional embodiment of the memory cell arrangement of SRAM cell groups, at least one out of the group comprising the reference voltage Vref, the Vbias-n signal, or the Vbias-p signal may be controlled by a process-voltage-temperature circuit in order to reflect actual operating parameters. This may have the advantage that real operation parameters may be used to operate the memory cell arrangement of SRAM cell at a defined low power consumption operation point.

According to one permissive embodiment of the design structure, the design structure may comprise a net-list which may describe the memory cell arrangement of SRAM cell groups. This net-list may be required for automatic production systems for the memory cell arrangement of SRAM cells.

And according to another permissive embodiment of the design structure, the design structure may include at least one set of test data, characterization data, verification data, or design specifications.

DETAILED DESCRIPTION

The term ‘group multiple SRAM cells’ may denote a plurality of Static Random-Access Memory (SRAM) cells connected to a common output line, aka the local bit-line. The local bit-line may be shared by a plurality of SRAM cells and may be connected to an input of a local bit-line amplifier.

The term ‘local read amplifier’ may denote the above-mentioned local bit-line amplifier which may be located between a common local bit-line and a global bit-line.

The term ‘local bit-line’ may denote the common output line for a plurality of SRAM cells connecting the plurality of SRAM cells to a local read amplifier.

The term ‘global bit-line’ or also “shared global bit-line” may denote a line connected to a plurality of read amplifiers or local read amplifiers. A characteristic of the global bit-line may be its comparatively high parasitic capacity due to its size and the comparable high number of local read amplifiers connected to it.

The term ‘pre-charge circuit’ may denote a circuit comprising a plurality of electronic components to pre-charge a bit line of any kind before a read cycle of an SRAM connected directly or indirectly to the global bit-line. In a first phase of a read cycle, the global bit-line may be pre-charged and potentially discharged during a second phase of a read cycle depending on the logical level of the bit read out of the SRAM cell. More details are explained in reference toFIG. 1.

The term ‘pre-charge regulator circuit’ may refer to a circuit comprising a plurality of electronic components arranged and connected to each other in order to ensure a pre-charging of the global bit-line before or during a first phase of a read operation may occur.

The term ‘evaluation and translation circuit’ may denote a plurality of electronic components arranged and connected to each other in order to ensure a detection of the stored bit in a selected SRAM cell even if the pre-charging is below a full swing pre-charge level. An additional task of the evaluation and translation circuit may also be to translate the comparatively low charge level of the global bit-line to stable and detectable levels and signals for down-stream electronic components.

The term ‘programmable pre-charge voltage’ may denote a voltage adjustable to a certain pre-definable and/or self-adjustable level. For example, the global bit-line may be pre-charged before reading with the programmable pre-charge voltage. The term ‘net-list’ may denote the connectivity of an electronic design. For example, a single net-list may be a list of all the component terminals that should be electrically connected together for the circuit to work. Net-lists usually convey connectivity information and provide nothing more than instances, nets, and perhaps some attributes.

In the following, a detailed description of the figures will be given. All instructions in the figures are schematic. Firstly, a diagram of groups of SRAM cells connected to a local bit-line and a global bit-line is shown. Afterwards, several alternative embodiments of the inventive memory cell arrangement of SRAM cell groups will be described.

FIG. 1shows an example of SRAM cells connected to a shared global bit-line. Each SRAM cell106may be connected in groups to a common local bit-line LBL108. The local bit-lines108may each be connected to a respective local read amplifier104. The output of the local read amplifier104may be connected to a shared global bit-line102. A skilled person would understand that the parasitic capacity116of a single ended global bit-line102is not to be underestimated, especially in the case in which a larger number of local read amplifiers104would be connected to the shared global bit-line.

An additional p-FET P0may act as a pre-charge circuit together with a keeper/leakage compensation circuit118. The additional p-FET P0may be connected to a power supply voltage Vdd110. If an inverted global bit-line pre-charge signal GPCHGN112is connected to the gate of P0, in particular with a transition from “1” to “0”112a, the global bit-line voltage may show a transition114if a read “0” is performed, and a transition117if a read “1” is performed. It may be clear that a coincidence switching of a plurality of such instances, as shown inFIG. 1, may generate huge transient current peaks, and may require a comparability high average AC power.

FIG. 2shows a design of the inventive memory cell arrangement of SRAM cell groups, in accordance with various embodiments of the present disclosure. As already discussed in the context ofFIG. 1, local read amplifiers104deliver their output signals to a shared global bit-line102having a parasitic or intrinsic capacity116. The inputs of the local read amplifiers104are connected to local bit-lines108which are again connected to the 1-bit SRAM cells (not shown). Additionally, a pre-charge regulator circuit202and an evaluation and translation circuit204are shown.

The pre-charge regulator circuit202includes a first p-FET P1connected with its source to power supply voltage Vdd110, and with its drain to a 1st terminal of a switch206—shown as an equivalent circuit—which receives a global bit-line pre-charge signal GPCHG214,214a. A second terminal of switch206is connected to the shared global bit-line102. On the other side, a source of a 1st n-FET N1is connected to the first terminal of switch206. A drain of the 1st n-FET is connected to a gate of the 1st p-FET P1as well as to a first terminal of a resistor208. The second terminal of resistor208is connected to the power supply line110. Details of the resistor208are explained in the subsequent figures.

Beside the pre-charge regulator circuit202, an evaluation and translation circuit204is shown. The evaluation and translation circuit204includes a 2nd n-FET N2which is connected with its source to the shared global bit-line102and with its drain to a second resistor210which may represent an equivalent circuit for details that are explained in the subsequent figures. The second resistor210may also be connected to the power supply voltage Vdd110. A global bit-line output signal GBLout212is available at the drain of the 2nd n-FET N2. The gate of the 1st n-FET N1and the gate of the 2nd n-FET N2are together connected to a voltage Vref which is instrumental for setting the pre-charge level of the shared global bit-line102.

A skilled person will understand that the 2nd n-FET N2is connected between the shared global bit-line102and the global bit-line output signal GBLout212. One of the tasks of the evaluation and translation circuit is to translate or transform the relatively low voltage of the shared global bit-line102to normal “0” and “1” levels, so that it can be interpreted as a logical “0” and a logical “1” from subsequent circuits. It may be clear that with these circuits202and204, the pre-charge level on the shared global bit-line102, as shown inFIG. 2, may be much lower than achievable with existing technologies. The pre-charge level may be stabilized by the evaluation and translation circuit204, which can basically be seen as a replica of the pre-charge regulator circuit202. The evaluation and translation circuit204also compensates a bit-line leakage current without changing the bit-line level. Additionally, the evaluation and translation circuit204provides for logic levels (Vdd/Vss) to downstream logic (see above). An optional bleeder device—to be explained below—may be used to further stabilize the bit-line level.

FIG. 3shows an embodiment of the inventive pre-charge regulator circuit302, in accordance with various embodiments of the present disclosure. The pre-charge regulator circuit302may be connected to the evaluation and translation circuit204. A p-FET P2is connected with its drain to the shared global bit-line102and its source to the power supply voltage Vdd110. The shared global bit-line102may have a parasitic or intrinsic capacitance116. A gate of p-FET P2is connected to a drain of a p-FET P3. The p-FET P3's source may be connected to the power supply voltage Vdd110.FIG. 3also shows p-FET P4, which has a drain that is also connected to the gate of the p-FET P2and which has a source that is connected to the power supply voltage Vdd110. The connection304may be interpreted as the global bit-line pre-charge GPCHG control line. An n-FET N3is also connected with its drain to the gate of the p-FET P2and with its source to a drain of an n-FET N4. The n-FET N4's source is connected to the shared global bit-line102. Moreover, a gate of the n-FET N4and a gate of p-FET P3are together connected to a global bit-line pre-charge line GPCHG, a gate of the n-FET N3is connected to the reference voltage Vref line, and the gate of the p-FET P4is connected to a Vbias-p line. The p-FET P4may be seen as an equivalent to the first resistor208ofFIG. 2.

Additionally, to stabilize the shared global bit-line level an n-FET N5may be connected with its drain to the shared global bit-line102and with its source to ground Vss302. The gate of n-FET N5may receive a bias voltage Vbias-n in order to control the stabilization effect on the shared global bit-line and in order to keep the pre-charge regulator circuit and the evaluation and translation circuit in stable working conditions.

FIG. 4shows a first embodiment of the evaluation and translation circuit404as part of the limiter circuit. The evaluation and translation circuit404may be connected to the pre-charge regulator circuit202. An n-FET N6is connected with its source to the shared global bit-line102and with its drain the global bit-line out terminal212. Accordingly, the shared global bit-line102and the signal at the global bit-line out terminal212may be separated from each other. The global bit-line102and the global bit-line out terminal212may show different voltage levels for a logical “0,” or a logical “1.” The global bit-line102may have a parasitic capacitance116.

As can be seen inFIG. 4, p-FET P5is connected with its drain to the global bit-line out terminal212and with its source to the power supply voltage Vdd110. p-FET P6is connected with its source to the power supply voltage Vdd110and with its drain to a source of a p-FET P7which is connected with its drain to the global bit-line out terminal212. A gate of the p-FET P7is connected to a drain of a p-FET P8which is connected with its source to the power supply voltage Vdd110. The gate of the p-FET P7is also connected to a drain of an n-FET N7which is connected with its source to ground Vss,302. Moreover, the reference voltage Vref signal is connected to a gate of the n-FET N6, the Vbias-p signal is connected to a gate of the p-FET P6, and an inverted signal of the global bit-line pre-charge signal GPCHGN is connected to a gate of the p-FET P5.

With this setup, the p-FETs P7and P8and the n-FET N7build a sort of a feedback loop402as part of the keeper part of the evaluation and translation circuit404. This interrupts the path from Vdd through p-FET P6and p-FET P7to the global bit-line out212in order to prevent a cross-current from Vdd to the pull-down device when a read amplifier tries to discharge the shared global bit-line and thus, to save power and accelerate the evaluation phase.

Again, p-FET P6may be seen as an equivalent to the second resistor210ofFIG. 2. The combination of the pre-charge regulator202ofFIG. 3and the evaluation and translation circuit404ofFIG. 4enable a fast and power saving implementation of the inventive concept.

It may also be noted that the reference voltage Vref may be controlled with a so-called PVT circuit (process voltage temperature) that may reflect the current status of the SRAM cell arrangement. If, for example, the power supply voltage Vdd110may be higher than expected, the pre-charge level of the shared global bit-line102does not have to go up as well. It may stay at the low level as defined by the reference voltage Vref. In the traditional technologies, the pre-charge level may go up with an increasing power supply voltage Vdd110. A comparable concept may apply to the Vbias-p and Vbias-n signal levels.

FIG. 5shows a second embodiment of the evaluation and translation circuit504. The evaluation and translation circuit504may be connected to a pre-charge regulator circuit202. For this,FIG. 5shows that the evaluation and translation circuit504comprises an n-FET N8which is connected with its source to the global bit-line102and with its drain to a source of an n-FET N9which is connected with its drain to a p-FET P9which is connected with its source to the power supply voltage Vdd110. A p-FET P10is connected with its source to the power supply voltage Vdd110and with its drain to the drain of the p-FET P9. A p-FET P11is connected with its source to the power supply voltage Vdd110and with its gate to the drain of the n-FET N9. The connection between the p-FET P11gate and the n-FET N9drain make an “Eval” line502.

A drain of the p-FET P11is connected to the global bit-line out terminal212. A drain of an n-FET N10and a drain of an n-FET N11are connected to the global bit-line out terminal212. A source of n-FET N10and a source of the n-FET N11are connected to ground Vss302.

The reference voltage Vref signal is connected to a gate of the n-FET N9. The bias voltage Vbias-p signal is connected to a gate of the p-FET P9. An inverted signal of the global bit-line pre-charge signal GPCHGN is connected to a gate of the 10th p-FET transistor, and the global bit-line pre-charge signal GPCHG is connected to a gate of the n-FET N10. The bias voltage Vbias-n signal is connected to a gate of the n-FET N11.

This embodiment of the evaluation and translation circuit504may be faster than the first embodiment of the evaluation translation circuit204, however, it may save less power than the first embodiment. Also here, the shared global bit-line102is separated from the global bit-line out signal212. Again, p-FET P9may be seen as the equivalent to the second resistor210ofFIG. 2.

FIG. 6shows a third implementation of the evaluation and translation circuit604of the general layout of the evaluation and translation circuit204according toFIG. 2. The evaluation and translation circuit604may be connected to a pre-charge regulator circuit202. The evaluation and translation circuit604comprises here an n-FET N12which is connected with its source to the global bit-line102and with its drain to a source of an n-FET N13. The n-FET N13may be connected with its drain to a drain of a p-FET P12which is connected through its source to the power supply voltage Vdd110.

A p-FET P13is connected with its source to the power supply voltage Vdd110and with its drain to the drain of the p-FET P12. A p-FET P14is connected through its source to the power supply voltage Vdd and through its gate to the drain of the n-FET N13, making an “Eval.” Line602. An n-FET N14is connected with its drain to a drain of the p-FET P14and with its source to a drain of an n-FET N15which is connected with its source to ground Vss302.

An n-FET N16is connected with its drain to the drain of the p-FET P14and with its source to ground Vss302. An inverter702is connected with its input to the drain of the p-FET P14and with its output to the global bit-line out terminal212. A p-FET P15is connected through its source to the power supply voltage Vdd110and through its drain to the drain of the p-FET P14. The p-FET P15may be connected through its gate to the global bit-line out terminal212. A gate of the n-FET N14is also connected to the global bit-line out terminal212.

The reference voltage Vref signal is connected to a gate of the n-FET N13, an inverted signal of the Vbias-p signal is connected to a gate of the p-FET P12, an inverted signal of the global bit-line pre-charge signal GPCHGN is connected to a gate of the p-FET P13, and the global bit-line pre-charge signal GPCHG is connected to a gate of the n-FET N16. Finally, the Vbias-n signal is connected to a gate of the n-FET N15.

It may be noted that the speed of this evaluation and translation circuit604is in between the first embodiment of the evaluation and translation circuit404according toFIG. 4and the second embodiment of the evaluation and translation circuit504according toFIG. 5. However, the power saving enhancements may be higher if compared to the second evaluation and translation circuit embodiment according toFIG. 5.

FIG. 7illustrates multiple such design structures including an input design structure720that is preferably processed by a design process710. Design structure720may be a logical simulation design structure generated and processed by design process710to produce a logically equivalent functional representation of a hardware device. Design structure720may also or alternatively comprise data and/or program instructions that when processed by design process710, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure720may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure720may be accessed and processed by one or more hardware and/or software modules within design process710to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 1 through 6. As such, design structure720may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.