Radio communication device and radio communication method

A radio communication device has an analog control loop unit to generate an analog control signal that adjusts a phase of a voltage control oscillation signal, a digital control loop unit to generate a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and a phase opposite to a phase of the analog control signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal including the reception signal, an automatic offset controller to generate a correction signal in response to an error between a frequency of the reception signal and a frequency of the voltage control oscillation signal, and a setting code adjuster to adjust the frequency setting code signal, wherein gain of the digital control loop unit is higher than gain of the analog control loop unit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2014-169763, filed on Aug. 22, 2014, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the present disclosure relate to a radio communication device and a radio communication method.

BACKGROUND

There has been proposed a receiver including a digital PLL circuit that automatically corrects offsets of a phase and a frequency between a transmitter and a receiver, based on offset amounts of the phase and the frequency between the transmitter and the receiver, the offset amounts being detected by an angle arithmetic circuit after an RF reception signal including FSK data is frequency-converted and then is A/D converted.

This type of conventional receiver detects the offset amounts of the phase and the frequency by mutually using an in-phase signal and a quadrature signal so that a circuit scale increases. A circuit scale of the digital PLL circuit including, for example, the angle arithmetic circuit is also large so that reduction of power consumption is difficult to achieve.

DETAILED DESCRIPTION

According to one embodiment, a radio communication device comprising:

an analog control loop unit to generate an analog control signal that adjusts a phase of a voltage control oscillation signal, in synchronization with a phase of a reception signal;

a digital control loop unit to generate a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and a phase opposite to a phase of the analog control signal;

a voltage controlled oscillator to generate the voltage control oscillation signal, based on the analog control signal and the digital control signal;

a data slicer to generate a digital signal including the reception signal digitally demodulated, based on a comparison between the digital control signal and a threshold value;

an automatic offset controller to generate a correction signal in response to an error between a frequency of the reception signal and a frequency of the voltage control oscillation signal, based on a time difference between timing with which the digital control signal is equivalent to the threshold value and previously determined reference timing; and

a setting code adjuster to adjust the frequency setting code signal based on the correction signal,

wherein gain of the digital control loop unit is higher than gain of the analog control loop unit.

Embodiments of the present disclosure will be described below with reference to the drawings. A distinguishing configuration and operation thereof in a receiver to be provided in a radio communication device, will be mainly described in each of the following embodiments, but the receiver may include an omitted configuration and operation thereof in the following descriptions. Note that, the scope of the present embodiments includes the omitted configuration and the operation. The radio communication device according to each of the following embodiments may include only the receiver, or may include a configuration, such as a transmitter, other than the receiver. The radio communication device may be a stationary communication device or a portable radio terminal.

First Embodiment

FIG. 1is a block diagram of a schematic configuration of a receiver1in a radio communication device according to a first embodiment. The receiver1inFIG. 1includes an analog control loop unit2, a digital control loop unit3, a voltage controlled oscillator4, and a data slicer5. The receiver1inFIG. 1is used, for example, when a PSK signal is received.

The analog control loop unit2generates an analog control signal VMIXfor adjusting a phase of a voltage control oscillation signal, in synchronization with a phase of a reception signal received by an antenna6.

The digital control loop unit3generates a digital control signal Dctlhaving a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal FCW. The digital control loop unit3can offset a shift of the phase of the voltage control oscillation signal, and generates the digital control signal Dctlhaving a phase opposite to a phase of the analog control signal VMIX.

The analog control loop unit2controls a frequency of the voltage control oscillation signal to track the reception signal, whereas the digital control loop unit3blocks the control and controls the frequency of the voltage control oscillation signal to track the setting frequency determined by the reference signal and the frequency setting code signal. As a result of the performance of this type of reciprocal control, the analog control signal VMIXgenerated by the analog control loop unit2and the digital control signal Dctlgenerated by the digital control loop unit3become differential signals each having a mutually opposite phase.

The voltage controlled oscillator (VCO)4generates the voltage control oscillation signal (hereinafter, referred to as a VCO signal) based on the analog control signal VMIXand the digital control signal Dctl.

The data slicer5compares the digital control signal Dctlto a predetermined threshold value in synchronization with the reference signal CLKsymbolfrom a first reference signal source20and generates a digital signal in response to the reception signal. The digital signal is a signal including the reception signal demodulated digitally, and thus there is no need to provide an additional digital demodulator.

The analog control loop unit2includes a low noise amplifier11, a frequency converter12, and a low pass filter13. The low noise amplifier11amplifies the reception signal from the antenna6. The frequency converter12generates a phase difference signal between the reception signal and the VCO signal. The low pass filter13removes an unnecessary high frequency component included in an output signal of the frequency converter12, and generates the analog control signal VMIX.

The digital control loop unit3includes the first reference signal source20, a time-to-digital converter (TDC)21, a digital differentiator22, a digital subtractor23, an integrator24, a loop gain control unit (a second loop gain control unit)25, a loop filter26, a channel selection filter27, an automatic offset control unit28, and a setting code adjuster29.

The time-to-digital converter21detects the phase of the VCO signal in synchronization with a reference signal FREFfrom a second reference signal source21.

The digital differentiator22performs differential processing to an output signal of the time-to-digital converter21so as to convert a signal indicating the phase of the VCO signal into a frequency signal.

The digital subtractor23detects a difference between an output signal of the digital differentiator22and the frequency setting code signal FCW so as to generate a frequency error signal.

The integrator24converts the frequency error signal generated by the digital subtractor23, into a phase error signal. The phase error signal is input to the loop gain control unit25.

The loop gain control unit25operates as a type II ADPLL, for example. Loop gain of the type II ADPLL attenuates with a second-order gradient toward the high frequency side. Therefore, the loop filter26is arranged at a subsequent stage of the loop gain control unit25. The loop filter26removes a frequency component higher than the reception signal in the receiver1and performs smoothing so as to generate the digital control signal Dctl.

The channel selection filter27is coupled to a subsequent stage of the loop filter26, and suppresses a disturbing wave component included in the digital control signal Dctl. The disturbing wave component to be suppressed is mainly a disturbing wave component in proximity to a channel selection frequency. The digital control signal Dctlthat has passed through the channel selection filter27is input to the data slicer5.

The digital control loop unit3includes an all digital (AD) PLL. Descriptions of an operation principle of the ADPLL will be omitted. The setting frequency FVCOin the digital control loop unit3is expressed by Expression (1) below:
FVCO=FCW×Fref(1)
where Frefrepresents the frequency of the reference signal.

The receiver1inFIG. 1synchronizes the setting frequency FVCOexpressed by Expression (1) with a carrier frequency of the reception signal so as to perform channel selection. However, for example, in a case where BPSK modulation has been performed to the reception signal, the phase shifts by ±n/2 so that inconsistency occurs between the control operation of the analog control loop unit2that performs tracking with respect to the phase and the control operation of the digital control loop unit3that retains a phase constant. Thus, the receiver1inFIG. 1sets loop gain of the digital control loop unit3sufficiently higher than loop gain of the analog control loop unit2. Accordingly, the receiver1inFIG. 1demodulates and digitally converts the PSK modulation signal, and additionally improves tolerance against a disturbing wave superimposed on the modulation signal.

When the reception signal to which the BPSK modulation has been performed (a BPSK signal) and the VCO signal are input to the frequency converter12, the analog control loop unit2drives the analog control signal VMIXtoward the plus side in a case where the phase of the VCO signal delays by n/2 in comparison to the phase of the reception signal, and drives the analog control signal VMIXtoward the minus side in a case where the phase of the VCO signal advances by n/2, so as to cause the phase of the VCO signal to track the phase of the reception signal Data.

Meanwhile, the digital control loop unit3performs the operation for blocking the operation of the analog control loop unit2. Furthermore, the digital control loop unit3has gain higher than the gain of the analog control loop unit2so that the digital control signal Dctlhas a phase exactly opposite to the phase of the analog control signal VMIX. As a result, the analog control signal VMIXand the digital control signal Dctlbecome the differential signals each having a mutually opposite (reverse) phase. The digital control signal Dctlis determined to be 1(+n/2) when operating toward the plus side, and the digital control signal Dctlis determined to be 0(−n/2) when operating toward the minus side, so that the BPSK signal can be demodulated.

The digital control signal Dctlis input to the voltage controlled oscillator4and the data slicer5. The data slicer5is a digital comparator that operates with a reference clock that has synchronized with a symbol rate of the reception signal, and can correctly determine 1(+n/2) and 0(−n/2) of the digital control signal Dctlwhen a threshold value is set to be at an appropriate level.

The digital control signal Dctlis also input to the automatic offset control unit28. The automatic offset control unit28generates a correction signal in response to an error between the frequency of the reception signal and the frequency of the VCO signal, based on a time difference between timing with which the digital control signal Dctlis equivalent to the threshold value of the data slicer5and previously determined reference timing. Here, the reference timing is previously determined timing in design, and is, more specifically, timing with which an eye pattern acquired from the digital control signal Dctlis a predetermined amount or more (for example, maximally opens).

The setting code adjuster29adjusts the frequency setting code signal based on the correction signal.

The receiver1according to the present embodiment originally has no concept of an in-phase signal and a quadrature signal, and can demodulate the reception signal to which the FSK/BPSK modulation has been performed, correcting a frequency offset between a transmitter and the receiver with only one of signal paths. This is because the digital control signal Dctlfor the signal demodulation, includes information on the frequency and the phase.

FIG. 2Ais a signal waveform chart of the digital control signal Dctland the analog control signal VMIXaccording to the first embodiment in a case where the frequency offset is present between the transmitter and the receiver that transmits and receives the BPSK signal, respectively, and in a case where the frequency offset is not present.FIG. 2Bis a signal waveform chart of the setting frequency FVCOin the digital control loop unit3.

A solid line waveform inFIG. 2Ais an ideal signal waveform, and intersects the threshold value of the data slicer5at a substantially center point of amplitude of the digital control signal Dctl. In a case where the BPSK modulation is performed, the digital control signal Dctlintersects the threshold value of the data slicer5at a boundary of a symbol and another symbol in terms of the reference timing.

However, when the frequency offset is present between the transmitter and the receiver, for example, the frequency shifts from the ideal signal waveform as a broken line waveform and the shift of the frequency gradually accumulates so as to be a phase error. That is, the frequency offset is present so that the phase error being an integrated value thereof increases.

Therefore, the automatic offset control unit28detects an increase of the phase error for each symbol, namely, a differential value of the digital control signal Dctlso as to regard the differential value as the correction signal. Then, the setting code adjuster29adds the correction signal to an input code signal for frequency setting, input to the receiver1, so as to adjust the frequency setting code signal. The adjusted frequency setting code signal is input to the digital subtractor23. Accordingly, the setting frequency FVCOof the digital control loop unit3gradually comes close to a desired frequency FRF, as illustrated inFIG. 2B. Therefore, the frequency of the VCO signal of the voltage controlled oscillator4and the frequency of the reception signal can be synchronized.

In this manner, according to the first embodiment, the automatic offset control unit28is provided so as to generate the correction signal in response to the error between the frequency of the reception signal and the frequency of the VCO signal, based on the time difference between the timing with which the digital control signal Dctlis equivalent to the threshold value of the data slicer5and the reference timing. Thus, feedback control is performed to the digital control signal Dctlwith the correction signal so that the frequency of the reception signal coincide with and the frequency of the VCO signal. Therefore, the frequency offset between the transmitter and the receiver can be canceled.

According to the present embodiment, the frequency offset can be corrected without a digital PLL circuit including an IQ demodulator and an angle arithmetic circuit so that a circuit scale can be reduced and power consumption can be also reduced.

Furthermore, the receiver1inFIG. 1performs the digital conversion by using the time-to-digital converter21inside the digital control loop unit3so that an A/D converter that is originally required to be at a subsequent stage of the frequency converter12is not required and an internal configuration can be simplified.

The receiver1inFIG. 1has tolerance significantly high against the disturbing wave in comparison to a conventional, analog synchronous FSK/PSK receiver1. The higher the loop gain of the digital control loop unit3increases than the loop gain of the analog control loop unit2, the more surely the oscillation frequency of the voltage controlled oscillator4can be prevented from being attracted into a disturbing frequency even when the disturbing wave having large power is present.

Furthermore, the loop gain of the digital control loop unit3is higher in the low frequency (the carrier frequency) side and is lower in the high frequency (the disturbing frequency) side so that an unnecessary component due to the disturbing wave can be suppressed by a gain difference therebetween.

The receiver1inFIG. 1can generate the digital signal digitally demodulated by the data slicer5and no additional digital demodulator is required so that the internal configuration of the receiver1can be simplified.

Second Embodiment

A second embodiment to be described below includes an internal configuration of an automatic offset control unit28specified.

FIG. 3is a block diagram of an internal configuration of a receiver1in a radio communication device according to the second embodiment. The receiver1inFIG. 3is similar to that inFIG. 1except the internal configuration of the automatic offset control unit28different from that inFIG. 1.

The automatic offset control unit28inFIG. 3includes an edge detector31and a loop gain control unit (a first loop gain control unit)32. The edge detector31detects the time difference between the timing with which the digital control signal Dctlis equivalent to the threshold value of the data slicer5and the reference timing, for each symbol, so as to output an error signal in response to the time difference. The loop gain control unit32generates a correction signal based on the error signal. More specifically, the loop gain control unit32multiplies the error signal by predetermined gain so as to generate the correction signal. The setting code adjuster29adds the correction signal to the input code signal for frequency setting so as to generate the frequency setting code signal.

In this manner, an automatic frequency correction loop includes the edge detector31, the loop gain control unit32, the setting code adjuster29, the digital control loop unit3, and the voltage controlled oscillator4. The loop can be regarded as a frequency-locked loop (FLL). Even when the frequency offset between the transmitter and the receiver varies due to an external factor, the receiver1according to the present embodiment can correct the frequency offset, tracking the variation, by using the loop.

FIG. 4Ais a signal waveform chart of the digital control signal Dctland the analog control signal VMIXaccording to the second embodiment in a case where the frequency offset is present between the transmitter and the receiver that transmits and receives the BPSK signal, respectively, and in a case where the offset is not present.FIG. 4Bis a signal waveform chart of the setting frequency FVCOin the digital control loop unit3.

The edge detector31outputs the error signal for each symbol, and thus can adjust the frequency offset for each symbol. Therefore, as illustrated inFIG. 4A, the phase error that occurs due to the accumulation of the frequency offset, is smaller in comparison to that inFIG. 2A.

Note that, the edge detector31can detect the time difference described above by using any of a preamble section and a data section for each symbol.

Here, a loop band of the automatic offset control unit28is made lower than a loop band of the digital control loop unit3. Accordingly, the frequency offset correction between the transmitter and the receiver by the automatic offset control unit28is gently performed so that the operation can be stabilized.

In this manner, according to the second embodiment, the automatic offset control unit28includes the edge detector31and the loop gain control unit32inside so that the correction signal can be generated for each symbol and the frequency offset adjustment can be performed for each symbol.

Third Embodiment

A third embodiment to be described below is to perform phase offset adjustment.

FIG. 5is a block diagram of an internal configuration of a receiver1in a radio communication device according to the third embodiment. The receiver1inFIG. 5is similar to that inFIG. 3except an internal configuration of an automatic offset control unit28different from that inFIG. 3. In more detail, an internal configuration of a loop gain control unit32in the automatic offset control unit28inFIG. 5is different from that inFIG. 3.

The edge detector31in the automatic offset control unit28inFIG. 5detects the time difference between the timing with which the digital control signal Dctlintersects the threshold value of the data slicer5and the reference timing. The time difference can be regarded as the phase error between the transmitter and the receiver. The edge detector31detects the amount of the phase error and the polarity, generates a DN signal having a pulse width being the amount of the phase error in a case where the phase has advanced, and generates an UP signal having a pulse width being the amount of the phase error when the phase has delayed.

The loop gain control unit32in the automatic offset control unit28inFIG. 5includes a proportion path unit32a, an integral path unit32b, and adder36. The proportion path unit32aincludes a multiplier33. The integral path unit32bincludes a multiplier34and an integrator35. The adder36adds an output signal of the proportion path unit32aand an output signal of the integral path unit32b. The edge detector31supplies the DN signal and the UP signal to the multipliers33and34.

The multiplier33in the proportion path unit32aoutputs a frequency offset amount based on the DN signal and the UP signal. The integrator35in the integral path unit32bintegrates a frequency offset amount acquired by the multiplier34so as to output a phase offset amount. The adder36adds an output signal of the multiplier33and an output signal of the integrator35. An output signal of the adder36is a signal including both of the frequency offset amount and the phase offset amount. The setting code adjuster29adds the signal to the input code signal for frequency setting so that the frequency setting code signal is generated.

The digital control loop unit3adjusts the digital control signal Dctlwith the frequency setting code signal so that the frequencies and the phases of the reception signal and the VCO signals can be individually synchronized.

FIG. 6Ais a signal waveform chart of the digital control signal Dctland the analog control signal VMIXaccording to the third embodiment in a case where the frequency offset is present between the transmitter and the receiver that transmits and receives the BPSK signal, respectively, and in a case where the frequency offset is not present.FIG. 6Bis a signal waveform chart of the UP signal and the DN signal.FIG. 6Cis a signal waveform chart of the setting frequency FVCOin the digital control loop unit3.

A solid line waveform indicates an actual signal waveform and a broken line waveform indicates an ideal signal waveform inFIG. 6A. Since the phase delays at the beginning in comparison to that of the ideal signal waveform, the UP signal is output so that the offset adjustment for the frequency and the phase is performed. After that, this time, the phase advances in comparison to that of the ideal signal waveform so that the DN signal is output. By performing this type of control individually, it is possible to synchronize the frequencies and the phases of the reception signal and the VCO signal.

In this manner, according to the third embodiment, the proportion path and the integral path are provided in the loop gain control unit32inside the automatic offset control unit28so that the frequency offset amount and the phase offset amount can be detected. Therefore, the frequency shift and the phase shift between the transmitter and the receiver can be corrected.

Fourth Embodiment

A fourth embodiment to be described later is to accelerate shift correction for the frequency and the phase between the transmitter and the receiver.

FIG. 7is a block diagram of an internal configuration of a receiver1in a radio communication device according to the fourth embodiment. The receiver1inFIG. 7includes the receiver1inFIG. 5additionally added with a multiplier36and an adder37. The multiplier36multiplies the correction signal output from the automatic offset control unit28, by predetermined gain. The adder37supplies a signal including an output signal of the multiplier36and the digital control signal Dctloutput from the loop gain control unit25, added, to the voltage controlled oscillator4. The multiplier36and the adder37correspond to an adjusting unit.

By providing the multiplier36and the adder37, it is possible to promptly reflect the correction signal generated by the automatic offset control unit28, in the digital control signal Dctlso that the control operation of the voltage controlled oscillator4can be accelerated.

FIG. 8Ais a signal waveform chart of the digital control signal Dctland the analog control signal VMIXaccording to the fourth embodiment in a case where the frequency offset is present between the transmitter and the receiver that transmits and receives the BPSK signal, respectively, and in a case where the frequency offset is not present.FIG. 8Bis a waveform chart of the UP signal and the DN signal.FIG. 8Cis a signal waveform chart of the setting frequency FVCOin a digital control loop unit3.

With comparison betweenFIGS. 8A to 8CandFIGS. 6A and 6C, according to the fourth embodiment, the frequency shift and the phase shift between the transmitter and the receiver can be corrected in a shorter time than that according to the third embodiment.

In this manner, according to the fourth embodiment, the correction signal output from the automatic offset control unit28can be promptly reflected in the digital control signal Dctlthrough the multiplier36and the adder37, and the control operation of the voltage controlled oscillator4can be accelerated so that the frequency shift and the phase shift between the transmitter and the receiver can be more promptly corrected.

Fifth Embodiment

The configuration and operation of the receiver1have been described in each of the first to fourth embodiments described above. In a fifth embodiment to be described below, an exemplary hardware configuration of a radio communication device including any of the configurations of the receivers1according to the first to fourth embodiments and additionally including a transmitter, will be described below. A receiver1in the radio communication device according to the fifth embodiment, includes any of the first to fourth embodiments described above, and thus the detailed descriptions thereof will be omitted.

FIG. 9is a block diagram of a schematic configuration of the radio communication device71according to the fifth embodiment. The radio communication device71inFIG. 9includes a baseband unit72, an RF unit73, and an antenna unit74.

The baseband unit72includes a control circuit75, a transmission processing circuit76, and a reception processing circuit77. Each of the circuits inside the baseband unit72performs digital signal processing.

The control circuit75performs, for example, processing of a media access control (MAC) layer. The control circuit75may perform processing of a host network hierarchy of the MAC layer. The control circuit75may perform processing relating to multi-input multi-output (MIMO). For example, the control circuit75may perform, for example, propagation path estimation processing, transmission weight calculation processing, and stream separation processing.

The transmission processing circuit76generates a digital transmission signal. The reception processing circuit77performs processing of analyzing a preamble and a physical header, for example, after performing demodulation and decoding.

The RF unit73includes a transmitting circuit78and a receiving circuit79. The transmitting circuit78includes a transmission filter not illustrated that extracts a signal in a transmission band, a mixer not illustrated that upconverts the signal that has passed through the transmission filter, into a radio communication frequency by using the oscillation signal of the VCO4, and a preamplifier not illustrated that amplifies the signal that has been upconverted. The receiving circuit79has a configuration similar to that of the receiver1according to any of the first to the fourth embodiment described above. That is, the receiving circuit79includes the TDC21, an ADPLL unit80, a reception RF unit81, and the VCO4.

The ADPLL unit80includes, for example, the digital differentiator22, the digital subtractor23, the integrator24, the loop gain control unit25, the loop filter26, the channel selection filter27, the automatic offset control unit28, and the setting code adjuster29inFIG. 1. The reception RF unit81includes, for example, the low noise amplifier11, the frequency converter12, and the low pass filter13inFIG. 1. The VCO4is shared by the transmitting circuit78and the receiving circuit79in the RF unit73inFIG. 9, but a separate VCO may be provided for each circuit.

In a case where transmission and reception of a radio communication signal are performed through the antenna unit74, a switch that couples any one of the transmitting circuit78and the receiving circuit79, to the antenna unit74, may be provided in the RF unit73. When this type of switch is provided, the antenna unit74can be coupled to the transmitting circuit78during the transmission, and the antenna unit74can be coupled to the receiving circuit79during the reception.

The transmission processing circuit76inFIG. 9outputs only one-channel transmission signal, but may separately output an I signal and a Q signal, depending on a radio communication system. A block configuration of a radio communication device71in this case is, for example, illustrated inFIG. 10. The radio communication device71inFIG. 10is different from that inFIG. 9in a configuration between the transmission processing circuit76and the transmitting circuit78.

The transmission processing circuit76generates a double-channel digital baseband signal (hereinafter, referred to as a digital I signal and a digital Q signal).

A DA conversion circuit82that converts the digital I signal into an analog I signal, and a DA conversion circuit83that converts the digital Q signal into an analog Q signal, are provided between the transmission processing circuit76and the transmitting circuit78. The transmitting circuit78upconverts the analog I signal and the analog Q signal by using a mixer not illustrated.

The RF unit73and the baseband unit72illustrated in each ofFIGS. 9 and 10may be made on one chip, or the RF unit73and the baseband unit72may be individually made on a separate chip. The RF unit73and the baseband unit72may partially include a discrete component, and the remaining may include one or a plurality of chips.

Furthermore, the RF unit73and the baseband unit72may include a software radio configurable with software. In this case, a digital signal processing processor is used so that functions of the RF unit73and the baseband unit72are at least achieved with the software. In this case, a bus, the processor, and an external interface unit are provided inside the radio communication device71illustrated in each ofFIGS. 9 and 10. The processor and the external interface unit are coupled through the bus, and firmware operates in the processor. The firmware can be updated with a computer program. The processor operates the firmware so that processing operation of the RF unit73and the baseband unit72illustrated in each ofFIGS. 9 and 10can be performed.

The radio communication devices71inFIGS. 9 and 10include only the single antenna unit74, but the number of the antennas is not particularly limited. For example, a transmission antenna unit74and a reception antenna unit74may be separately provided or an I signal antenna unit74and a Q signal antenna unit74may be separately provided. When only one antenna unit74is provided, a transmission-and-reception changeover switch at least switches the transmission and the reception.

The radio communication devices71illustrated inFIGS. 9 and 10can be applied to a stationary radio communication device71, such as an access point, a wireless router, or a computer, can be applied to a portable radio terminal, such as a smartphone or a mobile phone, can be applied to peripheral equipment, such as a mouse or a keyboard, that performs radio communication with a host device, can be applied to a card-typed member including a radio function built therein, or can be applied to a wearable terminal that performs radio communication of biological information. A radio system of the radio communication between the radio communication devices71illustrated inFIG. 9 or 10are not particularly limited. The radio system is applicable to third generation or later cellular communication, a wireless LAN, Bluetooth (registered trademark), and near-field radio communication.

FIG. 11illustrates exemplary performance of radio communication between a PC84being a host device and a mouse85being peripheral equipment. Both of the PC84and the mouse85include the radio communication device71illustrated inFIG. 9 or 10built therein. The mouse85uses power of a built-in battery so as to perform the radio communication, and is required to perform the radio communication with power consumption as low as possible because a space in which the battery is built is limited. Accordingly, it is preferable to perform the radio communication by using a radio system capable of low consumption radio communication, such as Bluetooth Low Energy defined in a standard of Bluetooth (registered trademark) 4.0.

FIG. 12illustrates exemplary performance of radio communication between a wearable terminal86and a host device (for example, the PC84). The wearable terminal86is to be worn on a body of a person, and various examples thereof may include a seal type to be worn on a body, an eyeglasses type and an earphone type to be worn on a body except arms, and a pacemaker to be inserted inside a body, in addition to a type to be worn on an arm illustrated inFIG. 12. Both of the wearable terminal86and the PC84inFIG. 12also include the radio communication device71illustrated inFIG. 9 or 10built therein. Note that, examples of the PC84include a computer and a server. The above radio system capable of the radio communication with low power consumption, such as Bluetooth Low Energy, is also preferably adopted because the wearable terminal86is worn on a body of a person and a space for a built-in battery is limited.

When the radio communication is performed between the radio communication devices71illustrated inFIG. 9 or 10, the type of information to be transmitted and received through the radio communication is not limited. Note that, the radio system is preferably varied between a case where information including a large amount of data, such as moving image data, is transmitted and received and a case where information including a small amount of data, such as operation information of the mouse85, is transmitted and received. Thus, there is a need to perform the radio communication in an optimum radio system in accordance with the amount of information to be transmitted and received.

Furthermore, when the radio communication is performed between the radio communication devices71illustrated inFIG. 9 or 10, a notifying unit that notifies a user of an operation state of the radio communication, may be provided. Specific examples of the notifying unit may include display of the operation state on a display device including LEDs, notification of the operation state by vibration of a vibrator, and notification of the operation state from audio information by a speaker or a buzzer.

The receivers1described in the embodiments described above, may at least partially include hardware or include software. When the configuration including the software is provided, a program for achieving a function of the at least partial receivers1may be stored in a storage medium, such as a flexible disk or a CD-ROM, and then may be read and performed by a computer. The storage medium is not limited to a detachably attachable storage medium, such as a magnetic disk or an optical disc, and may be a non-removable storage medium, such as a hard disk or a memory.

The program for achieving the function of the at least partial receivers1, may be distributed through a communication line, such as the Internet, (including radio communication). Furthermore, the program that has been encrypted, modulated, or compressed, may be distributed through a wired line or a wireless line, such as the Internet, or may be stored in a storage medium and then may be distributed.