Semiconductor packages incorporating alternating conductive bumps

A semiconductor package includes a first semiconductor chip having a plurality of first through-electrodes and a plurality of first upper connection pads respectively connected to the plurality of first through-electrodes, where the plurality of first upper connection pads are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and having a plurality of second lower connection pads on a lower surface of the second semiconductor chip, and a plurality of connection members, each including a pillar and a conductive bump, the plurality of connection members electrically connecting respective ones of the first upper connection pads and the second lower connection pads to each other. Conductive bumps of adjacent connection members, among the plurality of connection members, are alternately disposed at different levels with respect to the upper surface of the first semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2019-0131415, filed on Oct. 22, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package.

With rapid advances in the electronics industry and user demand, electronic devices have been miniaturized and have become lighter. Also, semiconductor packages used in the electronic devices not only benefit from being miniaturized and lightened but also from being highly efficient and having higher capacity. To this end, continuous research and development has been conducted into semiconductor chips including through-silicon vias (TSVs) and stacked semiconductor packages.

SUMMARY

Example embodiments provide semiconductor packages that have improved reliability and are capable of achieving miniaturization, high performance, and high capacity.

According to an example embodiment, a semiconductor package includes a first semiconductor chip having at least two first through-electrodes and at least two first upper connection pads that are respectively connected to the at least two first through-electrodes and that are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and having at least two second lower connection pads on a lower surface of the second semiconductor chip, a first connection member between the first semiconductor chip and the second semiconductor chip and including a first pillar and a first conductive bump, the first connection member electrically connecting one of the at least two first upper connection pads and one of the at least two second lower connection pads to each other, and a second connection member that is adjacent the first connection member and including a second pillar and a second conductive bump, the second connection member electrically connecting another one of the at least two first upper connection pads and another one of the at least two second lower connection pads to each other. A first level of the first conductive bump and a second level of the second conductive bump are different.

According to an example embodiment, a semiconductor package includes a first semiconductor chip having a plurality of first through-electrodes and a plurality of first upper connection pads respectively connected to the plurality of first through-electrodes, where the plurality of first upper connection pads are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and having a plurality of second lower connection pads on a lower surface of the second semiconductor chip, and a plurality of connection members, each including a pillar and a conductive bump, the plurality of connection members electrically connecting respective ones of the first upper connection pads and the second lower connection pads to each other. Conductive bumps of adjacent connection members, among the plurality of connection members, are alternately disposed at different levels with respect to the upper surface of the first semiconductor chip.

According to an example embodiment, a semiconductor package includes a first semiconductor chip having a first through-electrode, a first upper connection pad connected to the first through-electrode, a second through-electrode, and a second upper connection pad connected to the second through-electrode, wherein the first upper connection pad and the second upper connection pad are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and having a first lower connection pad and a second lower connection pad on a lower surface of the second semiconductor chip, a first connection member including a first conductive bump having a lower surface facing the first semiconductor chip and an upper surface opposite the lower surface, a first auxiliary pillar on the lower surface of the first conductive bump and contacting the first upper connection pad, and a first pillar on the upper surface of the first conductive bump and contacting the first lower connection pad, a second connection member including a second conductive bump having a lower surface facing the first semiconductor chip and an upper surface opposite the lower surface, a second pillar on the lower surface of the second conductive bump and contacting the second upper connection pad, and a second auxiliary pillar on the upper surface of the second conductive bump and contacting the second lower connection pad, and an insulating layer between the first semiconductor chip and the second semiconductor chip and on the first connection member and the second connection member. The first conductive bump is at a level that is lower than a level of the second conductive bump.

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described with reference to the accompanying drawings. Like numbers refer to like elements throughout. Thus, the same or similar numbers may be described with reference to other drawings even if they are neither mentioned nor described in the corresponding drawing. Also, elements that are not denoted by reference numbers may be described with reference to other drawings.

FIG. 1is a cross-sectional view of a semiconductor package1aaccording to an example embodiment.

Referring toFIG. 1, a semiconductor package1aaccording to an example embodiment may include a first semiconductor chip100, a second semiconductor chip200, a third semiconductor chip300, and a fourth semiconductor chip400. The second to fourth semiconductor chips200,300, and400may be sequentially stacked on the first semiconductor chip100. In addition, a plurality of connection members140,240,340, and440may be respectively disposed between the first to fourth semiconductor chips100,200,300, and400to be electrically connected to each other or to be electrically connected to a base die or a base substrate (for example,600inFIG. 9). In addition, the first to fourth semiconductor chips100,200,300, and400may be attached to each other by insulating layers250,350, and450, respectively disposed therebetween. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, the elements should not be limited by these terms; rather, these terms are only used to distinguish one element from another element. Thus, a first element discussed could be termed a second element without departing from the scope of the present inventive concepts.

For example, an external connection member140may be disposed below the first semiconductor chip100, a lower connection member240may be disposed between the first semiconductor chip100and the second semiconductor chip200, an intermediate connection member340may be disposed between the second semiconductor chip200and the third semiconductor chip300, and an upper connection member440may be disposed between the third semiconductor chip300and the fourth semiconductor chip400. The first to fourth semiconductor chips100,200,300, and400may be electrically connected to each other through the lower connection member240, the intermediate connection member340, and the upper connection member440, respectively disposed therebetween, and through-electrodes130,230, and330respectively disposed therein. The external connection member140may have a structure different from structures of the lower connection member240, the intermediate connection member340, and the upper connection member440.

The lower connection member240may include a first lower connection member240-1and a second lower connection member240-2disposed adjacent to each other between the first semiconductor chip100and the second semiconductor chip200. Each of the first and second lower connection members240-1and240-2may include a pillar242and a conductive bump248electrically connecting the first semiconductor chip100and the second semiconductor chip200to each other. The conductive bumps248of the first lower connection member240-1and the second lower connection member240-2may be disposed on different levels with respect to each other, and may be alternately disposed. Similarly, the intermediate connection member340may include a first intermediate connection member340-1and a second intermediate connection member340-2, and the upper connection member440may include a first upper connection member440-1and a second upper connection member440-2. Hereinafter, the above-described first lower, middle, and upper connection members240-1,340-1, and440-1will be described as a “first connection member,” and the above-described second lower, intermediate, and upper connection members240-2,340-2, and440-2will be described as a “second connection member.”

The first to fourth semiconductor chips100,200,300, and400may be logic chips or memory chips. For example, all of the first to fourth semiconductor chips100,200,300, and400may be the same type of memory chips, or a portion of the first to fourth semiconductor chips100,200,300, and400may be a memory chip, and another portion thereof may be a logic chip.

The memory chip may be, for example, a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a nonvolatile memory chip such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In example embodiments, each of the first to fourth semiconductor chips100,200,300, and400may be a high-bandwidth memory (HBM) DRAM. In addition, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor.

Although the semiconductor package1a, in which the first to fourth semiconductor chips100,200,300, and400are stacked, is illustrated as an example inFIG. 1, the number of semiconductor chips, stacked in the semiconductor package1a, is not limited thereto. For example, two, three, or five or more semiconductor chips may be stacked in the semiconductor package1a.

The first semiconductor chip100may include a first semiconductor substrate110, a first semiconductor element layer120, a first through-electrode130, a first lower connection pad131, and a first upper connection pad132, and an external connection member140.

The first semiconductor substrate110may have an upper surface and a lower surface opposing each other. The first semiconductor substrate110may include a first semiconductor element layer120formed on a lower surface side of the first semiconductor substrate110. The first through-electrode130may penetrate through the first semiconductor substrate110and may extend from the upper surface of the first semiconductor substrate110toward the lower surface thereof, and may be connected to a first wiring structure, not illustrated, provided in the first semiconductor element layer120or may be directly connected to the lower connection pad131through the first semiconductor element layer120. In some embodiments, the first lower connection pad131, disposed on the first semiconductor element layer120, may be electrically connected to the first through-electrode130through the wiring structure, not illustrated, in the first semiconductor element layer120.

The first semiconductor substrate110may include, for example, silicon. In some embodiments, the first semiconductor substrate110may include a semiconductor element such as germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the first semiconductor substrate110may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate110may include a buried oxide layer. The first semiconductor substrate110may have a conductive region, for example, a well doped with impurities or a structure doped with impurities. In addition, the first semiconductor substrate110may have various isolation structures such as a shallow trench isolation (STI) structure.

The first semiconductor element layer120may be formed to include a first wiring structure, not illustrated, for connecting a plurality of individual elements to other wirings formed in the first semiconductor substrate110. The first wiring structure, not illustrated, may include a metal wiring layer and/or a via plug.

The first through-electrode130may extend from the upper surface of the first semiconductor substrate110toward the lower surface thereof, and may extend in and/or through the first semiconductor element layer120. At least a portion of the first through-electrode130may have a pillar shape.

The first lower connection pad131may be disposed on the first semiconductor element layer120, and may be electrically connected to a first wiring structure, not illustrated, in the first semiconductor element layer120or may be directly connected to the first through-electrode130. The first lower connection pad131may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold.

Although not illustrated inFIG. 1, a first lower passivation layer may be formed on the first semiconductor element layer120to protect a first wiring structure, not illustrated, in the first semiconductor element layer120and other structures below the first wiring structure from external impact or humidity. The first lower passivation layer may expose at least a portion of an upper surface of the first lower connection pad131.

The first upper connection pad132may be disposed on the upper surface of the first semiconductor substrate110and may be electrically connected to the first through-electrode130. The first upper connection pad132may include the same material as the first lower connection pad131. In addition, a first upper passivation layer (or a first rear surface passivation layer)133may be formed on the upper surface of the first semiconductor substrate110to be on and/or cover the upper surface of the first semiconductor substrate110and to surround a portion of a side surface of the first through-electrode130. It will be understood that “an element A surrounds an element B” (or similar language) as used herein means that the element A is at least partially around the element B but does not necessarily mean that the element A completely encloses the element B.

The external connection member140may be disposed on the first lower connection pad131. The external connection member140may be used to electrically connect the semiconductor package1ato an external base substrate (for example,600inFIG. 9). At least one of a control signal, a power signal, and a ground signal for operations of the first to fourth semiconductor chips100,200,300, and400may receive a data signal to be stored in the first to fourth semiconductor chips100,200,300, and400from an external entity or may provide data, stored in the first to fourth semiconductor chips100,200,300, and400, to the external entity. For example, the external connection member140may include a pillar, a ball structure, or a solder.

The second semiconductor chip200may be mounted on an upper surface of the first semiconductor chip100. The second semiconductor chip200may be electrically connected to the first semiconductor chip100through the lower connection member240interposed between the upper surface of the first semiconductor chip100and a lower surface of the second semiconductor chip200.

A first insulating layer250may be interposed between the lower surface of the second semiconductor chip200and the upper surface of the first semiconductor chip100to attach the second semiconductor chip200onto the first semiconductor chip100. The first insulating layer250may protrude from side surfaces of the first semiconductor chip100and the second semiconductor chip200in a peripheral direction of the first semiconductor chip100and the second semiconductor chip200. Further, although not illustrated inFIG. 1, a portion of the protruding first insulating layer250may be on and/or cover portions of the side surfaces of the first semiconductor chip100and the second semiconductor chip200.

The third semiconductor chip300may be mounted on an upper surface of the second semiconductor chip200, and may be electrically connected to the second semiconductor chip200through the intermediate connection member340interposed between the upper surface of the second semiconductor chip200and the lower surface of the third semiconductor chip300. In addition, a second insulating layer350may be interposed between a lower surface of the third semiconductor chip300and an upper surface of the second semiconductor chip200.

The fourth semiconductor chip400may be mounted on an upper surface of the third semiconductor chip300, and may be electrically connected to the third semiconductor chip300through the upper connection member440interposed between the upper surface of the third semiconductor chip300and a lower surface of the fourth semiconductor chip. In addition, a third insulating layer450may be interposed between the lower surface of the fourth semiconductor chip400and the upper surface of the third semiconductor chip300.

The second semiconductor chip200may include a second semiconductor substrate210, a second semiconductor element layer220, a second through-electrode230, a second lower connection pad231, and a second upper connection pad232, a second upper passivation layer233, and a lower connection member240.

The third semiconductor chip300may include a third semiconductor substrate310, a third semiconductor element layer320, a third through-electrode330, a third lower connection pad331, a third upper connection pad332, a third upper passivation layer333, and an intermediate connection member340.

The fourth semiconductor chip400may include a fourth semiconductor substrate410, a fourth semiconductor element layer420, a fourth lower connection pad431, and an upper connection member440. Unlike the first to third semiconductor chips100,200, and300, the fourth semiconductor chip400may not have a through-electrode.

The lower connection member240may include a pillar242and a conductive bump248. In the first lower connection member240-1, the pillar242may be disposed above the conductive bump248(e.g., between the conductive bump248and the second semiconductor chip200). In the second lower connection member240-2, the pillar242may be disposed below the conductive bump248(e.g., between the conductive bump248and the first semiconductor chip100). Accordingly, the conductive bumps248of the first and second connection members240-1and240-2may be disposed on different levels with respect to each other. Similarly, the intermediate connection member340and the upper connection member440may include first connection members340-1and440-1and second connection members340-2and440-2, respectively. The term “pillar” used herein to describe, for example, a structure of a connection member such as lower connection member240is not intended to limit the shape of the structure. The pillar242can be any shape that extends between adjacent surfaces to contact one or more of the adjacent surfaces.

The first to third insulating layers250,350, and450(hereinafter, may be described as an “insulating layer”) may be a non-conductive film (NCF), and may include an adhesive resin. The adhesive resin may be a thermosetting resin. For example, the adhesive resin may include at least one of a bisphenol type epoxy resin, a noblock type epoxy resin, a phenol resin, a urea resin, a melamine resin, an unsaturated polyester resin, and a resorcinol resin. The insulating layer may further include a flux in the non-conductive film (NCF) besides the adhesive resin. The flux may be classified into a resin-based flux, an organic-based flux, and an inorganic-based flux. A main flux, used in electronic devices, is a resin-based flux. Main materials of the resin-based flux may be, for example, rosin, modified rosin, a synthetic resin, and the like. A flux may be classified into a rosin activated (RA) rosin, a rosin mildly activated (RMA) flux, and a rosin (R) flux depending on the degree of activation.

Since the second to fourth semiconductor chips200,300, and400may have the same or similar technical features as the first semiconductor chip100, detailed descriptions of the second to fourth semiconductor chips200,300, and400will be omitted.

The semiconductor package1amay further include a molding member150on and/or surrounding side surfaces of the first to fourth semiconductor chips100,200,300, and400and side surfaces of the first to third insulating layers250,350, and450. In an example embodiment, the molding member150may be on and/or cover the upper surface of the fourth semiconductor chip400, but is not limited thereto. In some embodiments, the molding member150may expose the upper surface of the fourth semiconductor chip400outwardly of the semiconductor package1a. The molding member150may include, for example, an epoxy mold compound (EMC) or the like.

FIG. 2is a partially enlarged view of region “A” inFIG. 1.

Referring toFIG. 2, in a first connection member240-1, a first conductive bump248-1may be disposed on an upper surface of a first upper connection pad132and a pillar242-1may be disposed on an upper surface of the first conductive bump248-1. On the other hand, in a second connection member240-2, a second conductive bump248-2may be disposed on a lower surface of a second lower connection pad231and a second pillar242-2may be disposed on a lower surface of the second conductive bump248-2.

For example, the semiconductor package1aaccording to an example embodiment may include the first upper connection pad132disposed on the upper surface of the first semiconductor chip (100inFIG. 1) and connected to a first through-electrode130, the second lower connection pad231disposed on the lower surface of the second semiconductor chip (200inFIG. 1) and connected to the second through-electrode230, and first and second connection members240-1and240-2electrically connecting the first upper connection pad132and the second lower connection pad231to each other. The first connection member240-1may include a first conductive bump248-1, disposed on an upper surface of the first upper connection pad132, and a pillar242-1disposed on an upper surface of the first conductive bump248-1, and the second connection member240-2may include a second conductive bump248-2, disposed on a lower surface of the second lower connection pad231, and a second pillar242-2disposed on a lower surface of the second conductive bump248-2. Accordingly, the first conductive bumps248-1and the second conductive bumps248-2may be disposed on different levels with respect to each other.

The above-described first and second pillars may be collectively referred to as a pillar242-1and242-2. The pillar242-1and242-2may have a height PH1of 5 to 13 μm, a distance W between the pillar242-1and242-2(which may be referred to as a distance W between a first connection member and a second connection member) may be 18 μm or less or 8 μm or less. The pillar242-1and242-2may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or combinations thereof. In an example embodiment, the pillars242-1and242-2may include copper (Cu) or a copper-alloy, but the inventive concepts of the present disclosure are not limited thereto.

In the case of a semiconductor package in which a plurality of semiconductor chips, including through-electrodes, are stacked to achieve miniaturization and high performance of an electronic device, fine-pitch conductive bumps, disposed adjacent to each other, are brought into contact with each other to cause a short-circuit in a reflow process or a thermal compression bonding process in which semiconductor chips are attached.

Since the semiconductor package according to the present disclosure includes the first conductive bumps248-1and the second conductive bumps248-2disposed on different levels with respect to each other, protrusions S1and S2of the first conductive bumps248-1and the second conductive bumps248-2may be alternately disposed to prevent a short circuit from occurring even when a conductive bump are transformed in a reflow process or a thermal compression bonding process.

FIG. 3is a partially enlarged schematic view of a portion of a semiconductor package1baccording to an example embodiment.FIG. 3is an enlarged view of a portion corresponding toFIG. 2. InFIG. 3, the same reference numerals as those inFIG. 2denote the same components. The semiconductor package1baccording toFIG. 3includes components similar to the components of the semiconductor package1adescribed with reference toFIG. 1, except for the structure illustrated inFIG. 3.

Referring toFIG. 3, a first pillar242-1may include a first support layer244-1, disposed to be in contact with a lower surface of a second lower connection pad231, and a first contact layer243-1disposed to be in contact with a lower surface of the first support layer244-1and an upper surface of a first conductive bump248-1. In addition, a second pillar242-2may include a second support layer244-2, disposed to be in contact with an upper surface of a first upper connection pad132, and a second contact layer243-2disposed to be in contact with an upper surface of the second support layer244-2and a lower surface of a second conductive bump248-2.

The above-described first and second support layers244-1and244-2may be collectively referred to as a support layer244-1and244-2. The support layer244-1and244-2may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or combinations thereof. In example embodiments, the support layer244-1and244-2may include copper (Cu) or a copper-alloy, and thus, rigidity of the pillar242-1and242-2, adjusting the level of the conductive bump248-1and248-2, may be improved.

The above-described first and second contact layers243-1and243-2may be collectively referred to the contact layer243-1and243-2. The contact layer243-1and243-2may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), Gold (Au), or combinations thereof. In example embodiments, the contact layer243-1and243-2may include nickel (Ni) or a nickel-alloy. Accordingly, excessive generation of an intermetallic compound, caused by reaction between the conductive bump248-1and248-2and the support layer244-1and244-2, may be reduced and/or suppressed to prevent voids from being formed in the conductive bump248-1and248-2and to prevent the conductive bump248-1and248-2from extending to side surfaces of the support layer244-1and244-2.

FIG. 4is a partially enlarged schematic view of a portion of a semiconductor package1caccording to an example embodiment.FIG. 4is an enlarged view of a portion corresponding toFIG. 2. InFIG. 4, the same reference numerals as those inFIG. 2denote the same components. The semiconductor package1caccording toFIG. 4includes components similar to the components of the semiconductor package1adescribed with reference toFIG. 1, except for the structure illustrated inFIG. 4.

Referring toFIG. 4, a first pillar242-1may include a first base layer245-1disposed to be in contact with a lower surface of a second lower connection pad231, a first support layer244-1disposed to be in contact with a lower surface of the first base layer245-1, and a first contact layer243-1disposed to be in contact with the a lower surface of the first support layer244-1and an upper surface of a first conductive bump248-1. In addition, a second pillar242-2may include a second base layer245-2disposed to be in contact with an upper surface of a first upper connection pad132, a second support layer244-2disposed to be in contact with an upper surface of the second base layer245-2, and a second contact layer243-2disposed to be in contact with an upper surface of the support layer244-2and a lower surface of a second conductive bump248-2.

The base layers245-1and245-2may form stable bonding between the support layers244-1and244-2and the connection pads231and132. In example embodiments, the base layers245-1and245-2may include, for example, nickel (Ni), copper (Cu), palladium (Pd), cobalt (Co), platinum (Pt), gold (Au), and/or combinations thereof. For example, the base layers245-1and245-2may include nickel or an alloy of nickel, but the inventive concepts of the present disclosure are not limited thereto. Heights of the base layers245-1and245-2may be appropriately selected depending on compositions, heights, and the like of the support layers244-1and244-2.

FIG. 5is a partially enlarged schematic view of a portion of a semiconductor package1daccording to an example embodiment.FIG. 5is an enlarged view of a portion corresponding toFIG. 2. InFIG. 5, the same reference numerals as those inFIG. 2denote the same components. The semiconductor package1daccording toFIG. 5includes components similar to the components of the semiconductor package1adescribed with reference toFIG. 1, except for the structure illustrated inFIG. 5.

Referring toFIG. 5, a first connection member240-1may include a first auxiliary pillar241-1disposed on an upper surface of a first upper connection pad132and disposed to be in contact with a lower surface of a first conductive bump248-1, a first conductive bump248-1disposed to be in contact with an upper surface of the first auxiliary pillar241-1, and a first pillar242-1disposed to be in contact with an upper surface of the first conductive bump248-1and a lower surface of a second lower connection pad231. On the other hand, a second connection member240-2may include a second auxiliary pillar241-2disposed on the lower surface of the second lower connection pad231and disposed to be in contact with an upper surface of a second conductive bump248-2, a second conductive bump248-2disposed to be in contact with a lower surface of the second auxiliary pillar241-2, and a second pillar242-2disposed to be in contact with a lower surface of the second conductive bump248-2and the upper surface of the first upper connection pad132.

For example, the first connection member240-1and the second connection member240-2may further include the auxiliary pillars241-1and241-2disposed to be opposite the pillars242-1and242-2with respect to the conductive bumps248-1and248-2, respectively.

The auxiliary pillars241-1and241-2may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), and/or combinations thereof. In example embodiments, the auxiliary pillars241-1and241-2may include nickel (Ni) or a nickel-alloy. Accordingly, excessive generation of an intermetallic compound, caused by reaction between the conductive bumps248-1and248-2and the connection pads132and231, may be reduced and/or suppressed to prevent voids from being formed in the conductive bumps248-1and248-2.

A height PH2of each of the auxiliary pillars241-1and241-2may be less than a height PH1of each of the pillars242-1and242-2. For example, the height PH2of each of the auxiliary pillar241-1and241-2may be approximately 1 to 3 μm.

FIG. 6is a partially enlarged schematic view of a portion of a semiconductor package1eaccording to an example embodiment.FIG. 6is an enlarged view of a portion corresponding toFIG. 2. InFIG. 6, the same reference numerals as those inFIG. 2denote the same components. The semiconductor package1eaccording toFIG. 6includes components similar to the components of the semiconductor package1adescribed with reference toFIG. 1, except for the structure illustrated inFIG. 6.

Referring toFIG. 6, a first connection member240-1may include a first auxiliary pillar241-1, disposed on a lower surface of a first conductive bump248-1, and a first pillar242-1disposed to be in contact with an upper surface of the first conductive bump248-1. The first pillar242-1may include a first support layer244-1, disposed to be in contact with a lower surface of a second lower connection pad231, and a first contact layer243-1disposed on a lower surface of the first support layer244-1and the upper surface of the first conductive bump248-1. A second connection member240-2may include a second auxiliary pillar241-2, disposed to be in contact with an upper surface of a second conductive bump248-2, and a second pillar242-2disposed to be in contact with a lower surface of the second conductive bump248-2. The second pillar242-2may include a second support layer244-2, disposed to be in contact with an upper surface of a first upper connection pad132, and a second contact layer243-2disposed to be in contact with an upper surface of the second support layer244-2and a lower surface of the second conductive bump248-2.

Since technical features of the contact layers243-1and243-2and the support layers244-1and244-2are the same and/or similar as described with reference toFIG. 3, descriptions thereof will be omitted.

FIG. 7is a partially enlarged schematic view of a portion of a semiconductor package if according to an example embodiment.FIG. 7is an enlarged view of a portion corresponding toFIG. 2. InFIG. 7, the same reference numerals as those inFIG. 2denote the same components. The semiconductor package if according toFIG. 7includes components similar to the components of the semiconductor package1adescribed with reference toFIG. 1, except for the structure illustrated inFIG. 7.

Referring toFIG. 7, a first connection member240-1may include a first auxiliary pillar241-1, disposed to be in contact with a lower surface of the first conductive bump248-1, and a first pillar242-1disposed to be in contact with an upper surface of the first conductive bump248-1. The first pillar242-1may include a first base layer245-1, disposed to be in contact with a lower surface of a second lower connection pad231, a first support layer244-1disposed to be in contact with a lower surface of the first base layer245-1, and a first contact layer243-1disposed to be in contact with a lower surface of the first support layer244-1and an upper surface of the first conductive bump248-1.

A second connection member240-2may include a second auxiliary pillar241-2, disposed to be in contact with an upper surface of a second conductive bump248-2, and a second pillar242-2disposed to be in contact with a lower surface of the second conductive bump248-2. The second pillar242-2may include a second base layer245-2disposed to be in contact with an upper surface of a first upper connection pad132, a second support layer244-2disposed to be in contact with an upper surface of the second base layer245-2, and a second contact layer243-2disposed to be in contact with an upper surface of the second support layer244-2and a lower surface of the second conductive bump248-2.

Since technical features of the contact layers243-1and243-2and the support layers244-1and244-2are the same as described with reference toFIG. 4, descriptions thereof will be omitted.

FIG. 8is a cross-sectional view of a semiconductor package2aaccording to an example embodiment.

Referring toFIG. 8, the semiconductor package2aaccording to an example embodiment may include a base die500. The base die500may include a base die substrate510, an interlayer insulating layer520, a base through-electrode530, a base connection pad531, a base upper connection pad532, and a rear surface passivation layer533. The base through-electrode530may penetrate from a lower surface to an upper surface of the base die substrate510and may extend in and/or through the interlayer insulating layer520. A plurality of wiring structures, not illustrated, may be formed in the interlayer insulating layer520, and may be electrically connected to the base through-electrode530.

A base connection member540may be mounted on a lower surface of the base die500. The base connection member540may be disposed on a base connection pad531disposed on a lower surface of the base die500. The technical features of the base connection member540are similar to those of the external connection member140inFIG. 1. In addition, the first and second external connection members140-1and140-2, connecting the first semiconductor chip100and the base die500to each other, have the same structure as the above-described first and second connection members (e.g.,240-1,240-2, etc.).

First to fourth semiconductor chips100,200,300, and400may be stacked on the upper surface of the base die500in an upward direction of the base die500. An external connection member140may be interposed between a base upper connection pad532on an upper surface of the base die500and a first lower connection pad131on a lower surface of the first semiconductor chip100. The external connection member140may have technical features similar to those of the second to fourth connection members240,340, and440.

A base insulating layer550may be interposed between the base die500and the first semiconductor chip100. Side surfaces of the base insulating layer550may be covered with a first molding member150.

The base die500may be a dummy semiconductor chip, for example, not including individual devices included in the first to fourth semiconductor chips100,200,300, and400. The base die500may be a buffer die which may receive at least one of a control signal, a power signal, and a ground signal for operations of the first to fourth semiconductor chips100,200,300, and400from an external entity through the base through-electrode530and the interlayer insulating layer520, may receive a data signal to be stored in the first to fourth semiconductor chip100,200,300, and400from an external entity through the base through-electrode530and the interlayer insulating layer520, and/or may provide data, stored in the first to fourth semiconductor chip100,200,300, and400, to an external entity through the base through-electrode530and the interlayer insulating layer520.

The first to fourth semiconductor chip100,200,300, and400may be stacked on the base die500having a through-electrode530having the same or similar structure as the first to fourth semiconductor chips100,200,300, and400. Accordingly, connection members140,240,340, and440of the first to fourth semiconductor chips100,200,300, and400are surrounded by a first molding member150and are not exposed outwardly of the semiconductor package2a. As a result, damage may be prevented during movement or storage of the semiconductor package2a.

For example, the semiconductor package2a, illustrated inFIG. 8, may include a base die500(hereinafter, may be referred to as a “substrate”), a plurality of semiconductor chips100,200,300, and400mounted on the base die500and stacked in one direction, inter-chip insulating layers250,350, and450, respectively disposed between the plurality of semiconductor chips100,200,300, and400, and base insulating layers550between a lowermost semiconductor chip100, among the plurality of semiconductor chips100,200,300, and400, and the base die500. A horizontal width of the base die500may be greater than a horizontal width of each of the first to fourth semiconductor chip100,200,300, and400. The first molding member150may be on and/or cover side surfaces of the plurality of semiconductor chips100,200,300, and400, side surfaces of the inter-chip insulating layers250,350, and450and the base insulating layers550, and an upper surface of the base die500. Among the elements illustrated inFIG. 8, components having the same reference numerals inFIG. 1are similar to those shown inFIG. 1, and thus, descriptions thereof will be omitted.

FIG. 9is a cross-sectional view of a semiconductor package2baccording to an example embodiment.

Referring toFIG. 9, the semiconductor package2baccording to an example embodiment may include a base substrate600and first to fourth semiconductor chips100,200,300, and400mounted on the base substrate600and sequentially stacked on an upper surface of the base substrate600.

The base substrate600may be or include, for example, a printed circuit board, a ceramic substrate, or an interposer. When the base substrate600is a printed circuit board, the base substrate600may include a substrate body610, a lower pad611, an upper pad612, and solder resist layers, not illustrated, disposed on a lower surface and an upper surface of the substrate body610. An internal wiring, not illustrated, may be disposed in the substrate body610to electrically connect the lower pad611and the upper pad612to each other. The lower pad611and the upper pad612may be portions exposed by the solder resist layers disposed on the lower surface and the upper surface of the substrate body610among the circuit wirings patterned after coating a copper (Cu) foil on the lower surface and the upper surface of the substrate body610, respectively.

When the base substrate600is an interposer, the base substrate600may include a substrate body610, formed of a semiconductor material, and a lower pad611and an upper pad612, respectively disposed on a lower surface and an upper surface of the substrate body610. The substrate body610may be formed from, for example, a silicon wafer. In addition, an internal wiring, not illustrated, may be formed on the lower surface, the upper surface, or inside of the substrate body610. In addition, a through-via, not illustrated, may be formed in the substrate body610to electrically connect the lower pad611and the upper pad612.

An external connection terminal620may be attached to the lower surface of the base substrate600. The external connection terminal620may be attached onto, for example, the lower pad611. The external connection terminal620may be, for example, a solder ball or a bump. The external connection terminal620may electrically connect the semiconductor package2bto an external device. At least a portion of the external connection terminals620may be disposed in a fan-out region, not overlapping the first to fourth semiconductor chips100,200,300, and400in a vertical direction.

A first molding member150and a second molding member640may be disposed on the base substrate600. The first molding member150may surround at least side surfaces of the first to fourth semiconductor chips100,200,300, and400. The second molding member640may surround at least a side surface of the first molding member150and may not be in direct contact with the side surfaces of the first to fourth semiconductor chips100,200,300, and400. The first and second molding members150and640may be formed of, for example, an epoxy mold compound.

An underfill material layer630may be formed between the base substrate600and the first semiconductor chip100. The underfill material layer630may be interposed between the base substrate600and the first semiconductor chip100to surround a side surface of the external connection member140. The underfill material layer630may be formed of, for example, an epoxy resin. The underfill material layer630may be a portion of the second molding member640formed in a molded underfill (MUF) manner. Among the elements illustrated inFIG. 9, components having the same reference numerals inFIG. 1are similar to those shown inFIG. 1, and thus, descriptions thereof will be omitted.

FIG. 10is a cross-sectional view of a semiconductor package2caccording to an example embodiment.

Referring toFIG. 10, the semiconductor package2caccording to an example embodiment may include a main semiconductor chip700, attached onto a base substrate600, and a semiconductor package including first to fourth semiconductor chips100,200,300, and400sequentially stacked on the base substrate600, such as semiconductor package1aillustrated inFIG. 1. ThoughFIG. 10illustrates the embodiment of semiconductor package1aon the base substrate600, it will be understood that other semiconductor packages including stacked semiconductor chips, such as those shown with regard to semiconductor packages1b,1c,1d,1e, and1fmay be incorporated in semiconductor package2cwithout deviation from the inventive concepts.

The main semiconductor chip700may be a processor unit. The main semiconductor chip700may be, for example, a microprocessor unit (MPU) or a graphics processor unit (GPU). The main semiconductor chip700may be a package in which a normal operation is verified, for example, a known good package (KGP). A main connection terminal720may be attached to a lower surface of a main body710of the main semiconductor chip700.

An underfill material layer630may be formed in a space between the base substrate600and the first semiconductor chip100and a space between the base substrate600and the main semiconductor chip700.

The second molding member640may cover an upper surface of the base substrate600, a side surface and an upper surface of the main semiconductor chip700, and at least a side surface of a first molding member surrounding the first to fourth semiconductor chips100,200,300, and400.

In some embodiments, the underfill material layer630disposed between the base substrate600and the first semiconductor chip100and between the base substrate600and the main semiconductor chip700may be a portion of the second molding member640.

FIGS. 11 to 18are schematic cross-sectional views illustrating a method of manufacturing a semiconductor package according to an example embodiment.

Referring toFIG. 11, a first semiconductor wafer W1is prepared. The semiconductor wafer W1may include a plurality of first semiconductor chips100divided into scribe lanes SL. A first semiconductor chip100includes a first semiconductor substrate110, a first semiconductor element layer120, and a first through-electrode130. The first semiconductor substrate110may have a first upper surface101and a first lower surface102opposing each other. The first semiconductor element layer120may be formed on the first upper surface101of the first semiconductor substrate110. The first through-electrode130may be formed to extend into the first semiconductor substrate110through the first semiconductor element layer120from the first upper surface101of the first semiconductor substrate110.

The first semiconductor element layer120may include a system LSI, a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, or an RRAM, and may be formed to include a plurality of wiring structures for connecting a plurality of individual elements to other wirings formed in the first semiconductor substrate110.

The first through-electrode130may extend into the first semiconductor substrate110from the first upper surface101of the first semiconductor substrate110. At least a portion of the first through-electrode130may have a pillar shape. The first through-electrode130may include a barrier layer, formed on a pillar-shaped surface, and a buried conductive layer filling inside of the barrier layer. A via insulating layer may be interposed between the first semiconductor substrate110and the first through-electrode130. The via insulating layer may be formed of, for example, an oxide, a nitride, a carbide, a polymer, or combinations thereof.

The first through-electrode130may be formed of conductive materials penetrating through the first semiconductor substrate110having a portion removed in a subsequent process. For example, the first through-electrode130may include a barrier layer and a buried conductive layer inside of the barrier layer. In some embodiments, for example, the first through-electrode130may be formed as a portion of a barrier layer, a buried conductive layer filling the barrier layer, and a metal wiring layer and/or a via plug.

Referring toFIG. 12, a first lower connection pad131is formed on the first semiconductor substrate110to be electrically connected to the first through-electrode130, and an external connection member140may be formed on the first lower connection pad131. In example embodiments, the first lower connection pad131may be omitted.

The external connection member140may be a common conductive bump. To form the external connection member140, a mask pattern, not illustrated, having an opening, not illustrated, exposing a portion of the first lower connection pad131, may be formed on the first semiconductor element layer120. Then, the external connection member140may be formed on a portion of the first lower connection pad131exposed by the mask pattern. The external connection member140may be formed by an electroplating process. The mask pattern, not illustrated, may be removed and a thermal compression bonding process may be performed to form the external connection member140having a convex shape.

Referring toFIG. 13, the first semiconductor wafer W1, on which the external connection member140is formed, is attached to a first carrier substrate10. The first carrier substrate10may include a first support substrate12and a first adhesive material layer14. The first semiconductor wafer W1may be attached to the first carrier substrate10such that an external connection member140faces the first carrier substrate10. The external connection member140may be covered with the first adhesive material layer14. A portion of the first semiconductor element layer120adjacent the first upper surface101of the first semiconductor substrate110, exposed by the external connection member140, may be in contact with the first adhesive material layer14.

Referring toFIG. 14, a portion of the first semiconductor substrate110is removed to expose the first through-electrode130. The first through-electrode130may be exposed to a first lower surface102of the first semiconductor substrate110. Since the first through-electrode130is exposed to the first lower surface102of the first semiconductor substrate110, the first through-electrode130may have a shape penetrating through the first semiconductor substrate110. Optionally, a portion of the first semiconductor substrate110may be removed such that the first through-electrode130protrudes further than the first lower surface102.

A portion of the first semiconductor substrate110may be removed using a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof to expose the first through-electrode130.

Referring toFIG. 15, a first rear surface passivation layer133may be formed to cover an exposed surface of the first semiconductor wafer W1, for example, the first lower surface102of the first semiconductor substrate110. The first rear surface passivation layer133may be formed by, for example, a spin coating process or a spray process. The first rear surface passivation layer133may be formed of, for example, an insulating polymer. To form the first rear surface passivation layer133, an insulating polymer layer may be formed to cover the first lower surface102of the semiconductor substrate110and the exposed first through-electrode130, and then a portion of the insulating polymer layer may be removed by an etch-back process to expose the first through-electrode130.

Referring toFIG. 16, a first upper connection pad132is formed to be electrically connected to the portion of the first through-electrode130exposed by the first rear surface passivation layer133. Optionally, the first upper connection pad132may be omitted so as not to be formed. A pillar242is formed on the first upper connection pads132, but is not formed on the first upper connection pads132on opposite sides adjacent to the first upper connection pads132on which the pillar242is formed. For example, the pillar242is formed on the first upper connection pads132to have a stepping stone. For example, the pillar242may be formed on every other one of the first upper connection pads132. The pillar242may be formed by performing, once or several times, a process of performing electroplating after forming a photoresist layer, not illustrated, on the first rear surface passivation layer133and etching a photoresist layer, not illustrated, on the first upper connection pad132.

The semiconductor wafer (W1inFIG. 15) may be cut along the scribe lanes (SL inFIG. 15) using a sawing blade, not illustrated, to be divided into a plurality of first semiconductor chips100. The divided first semiconductor chips100may be disposed side by side in a horizontal direction.

Referring toFIG. 17, second semiconductor chips200may be prepared to be stacked on the first semiconductor chip100. To prepare the second semiconductor chips200, a second semiconductor wafer, not illustrated, may processed similarly to the first semiconductor wafer W1illustrated inFIGS. 11 to 16. The processed second semiconductor wafer, not illustrated, may be divided to prepare the second semiconductor chips200.

The second semiconductor wafer may be a semiconductor wafer including individual homogenous elements formed through the same or similar process as the first semiconductor wafer W1. For example, a plurality of second semiconductor chips200may be attached to the second carrier substrate20in the form of the second semiconductor wafer connected to each other, and may then be cut to be divided into the second semiconductor chips200. The second semiconductor chip200may include a second semiconductor substrate210, a second semiconductor element layer220, a second through-electrode230, a second lower connection pad231, a pillar242, and a conductive bump248. The second carrier substrate20may include a second support substrate22and a second adhesive material layer24.

In particular, a pillar242and a conductive bump248may be formed below the second semiconductor chips200. The pillar242and the conductive bump248may be formed on a lower surface of the second lower connection pad231. The pillar242, formed below the second semiconductor chips200, may be disposed to correspond to first upper connection pads132(e.g., of the first semiconductor chip100), on which the pillar242is not formed, among the first upper connection pads132of the above-described first semiconductor chips100. For example, the pillar242is formed on the second lower connection pad231by a method similar to the method of manufacturing the first semiconductor chips100, but is not formed on the second lower connection pad231on opposite sides adjacent to the second lower connection pad231on which the pillar242is formed. For example, the pillar242is formed on the second lower connection pads231in the form of a stepping stone. For example, the pillar242is formed on every other one of the second lower connection pads231.

Referring toFIG. 18, second semiconductor chips200, third semiconductor chips300, and fourth semiconductor chips400may be sequentially stacked on the first semiconductor chips100. The third to fourth semiconductor chips300and400may be prepared in the same or similar manner as the second semiconductor chips200. In addition, the third to fourth semiconductor chips300and400may be prepared while lower surfaces of the third to fourth semiconductor chips300and400are provided with pillars and conductive bumps.

After the first to fourth semiconductor chips100,200,300, and400are stacked, insulating layers250,350, and450may be attached to upper surfaces of underlying semiconductor chips by performing a reflow process and/or a thermal compression bonding process, respectively.

A first molding member150may be formed on the first carrier substrate10to be on and/or cover the first to fourth semiconductor chips100,200,300, and400. The first molding member150may be formed to be on and/or cover side surfaces of the first to third semiconductor chips100,200, and300and a side surface and an upper surface of the fourth semiconductor chip400. The first molding member150may cover side surfaces of the insulating layers250,350, and450disposed between the first to fourth semiconductor chips100,200,300, and400. The first molding member150may include, for example, an epoxy mold compound (EMC). Then, a semiconductor wafer may be cut along scribe lane SL to be divided into semiconductor packages, each including the first to fourth semiconductor chips100,200,300, and400corresponding to each other.

As described above, according to example embodiments, fine-pitch bumps may be disposed on different levels with respect to each other to provide a semiconductor package that has improved reliability and is capable of achieving miniaturization, high performance, and high capacity.