Frequency margin testing of bladed servers

A frequency margin testing blade is adapted for use in a bladed server. The testing blade is further adapted to provide one or more output clock signals for use as clock inputs to one or more server blades internal to the bladed server in which the testing blade is installed and/or one or more server blades external to the bladed server in which the testing blade is installed.

FIELD OF THE INVENTION

The present invention relates generally to frequency margin testing.

BACKGROUND

Bladed servers are comprehensive computing systems that include processors, memory, network connections and associated electronics, all on a single motherboard called a blade. This high-density technology addresses the current trend among large computing centers to reduce space requirements while lowering their total cost of ownership. A server blade, along with storage, networking and other blades, are typically installed in a rack-mountable enclosure that houses multiple blades that share common resources such a cabling, power supplies and cooling fans.

In the design and manufacture of electronic components, it is common to perform testing to help detect or identify material, process and design weaknesses of the components. Such testing is desirable as it helps ensure the delivery of high-quality and reliable products to the end consumer.

One common test is frequency margin testing of the CPU (central processing unit) or bus (also referred to as runway) clock inputs. A component may work satisfactorily at nominal clock frequencies, but a dip or rise in the frequency or amplitude may cause a marginal component to fail. Such dips or rises are a part of normal operating conditions due to such factors as electromagnetic interference or line noise, drift or loss of reference clocks, or variations in components.

Frequency margin testing is generally accomplished using automated tester equipment to provide a variable external clock input. Often, these stationary testers are expensive, with some as much as $40,000 each. Additionally, such stationary testers are generally impracticable in the field.

For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative apparatus and methods for frequency margin testing of bladed servers.

SUMMARY

The various embodiments described herein facilitate frequency margin testing, particularly in bladed servers. The various embodiments facilitate such testing by providing a frequency margin testing blade adapted for use in a bladed server having at least one server blade. The testing blade is further adapted to provide one or more output clock signals for use as clock inputs to one or more server blades internal to the bladed server in which the testing blade is installed and/or one or more server blades external to the bladed server in which the testing blade is installed.

Embodiments of the invention include apparatus and methods of varying scope.

DESCRIPTION OF PREFERRED EMBODIMENTS

The various embodiments include apparatus and methods for frequency margin testing of bladed servers and their various components. Such testing is facilitated using a frequency margin blade or testing blade in accordance with an embodiment of the invention. The testing blades of various embodiments utilize substantially the same form factor as other blades of the bladed server, i.e., the testing blades of the various embodiments may be inserted in an available slot of the bladed server or may be swapped with a non-essential blade of the bladed server if there are no available slots. An example of a standard form factor utilized in bladed systems includes the cPCI (compact Peripheral Component Interconnect) form factor. This is one industry-standard for the connection and communication of computer devices. These standards often specify bus communication protocols as well as physical connectivity and pin layout for the various power supplies and signal types.

FIG. 1is a block diagram of a bladed server100in accordance with an embodiment of the invention. The bladed server100includes a chassis102housing at least one server blade104to provide server functionality. The bladed server100further typically includes one or more storage blades106for storage of data or other information and at least one network blade108for communication of the bladed server100across a computer network, such as a local area network (LAN) or wide area network (WAN). The bladed server100further includes a testing blade150in accordance with an embodiment of the invention. The testing blade150may be permanently installed in the bladed server100. However, it is contemplated that the testing blade150will be more advantageous as a portable device In this manner, one testing blade150may be used to individually test multiple bladed servers.

Each blade of the bladed server100is coupled to a backplane110. The backplane110may be referred to as a midplane depending upon the location of the backplane110to the orientation of the blades, i.e., whether it is located opposite or adjacent a bulkhead of the blades. However, for consistency, the term backplane will be used herein regardless of its location relative to the orientation of the blades. The backplane110provides communication channels and power inputs for each of the blades of the bladed server100.

For frequency margin testing, the testing blade150is coupled to a test executive170. A test executive is typically an application for automated sequencing of test programs. These test programs typically provide a user interface for the testing process, log test data and determine whether a particular test has passed or failed. However, the test executive170may represent a user interface for manual input to the testing blade150.

The test executive170may be capable or adapted to perform testing other than frequency margin testing involving the testing blade150. As such, it is preferred that the testing blade150pass commands and data from the test executive170to other blades of the bladed server100unaltered until the test executive170invokes the testing blade150. Invoking the testing blade150can be through a special escape sequence or other data pattern that signals the testing blade150that frequency margin testing is desired. This escape sequence should not be passed through to other blades.

One or more output clock signals123a,123bare generated by the testing blade150. The output clock signals may be provided to one or more of a server blade104of the chassis102containing the testing blade150, e.g., clock signal123a, or of an external server blade (not shown), such as a server blade104of another chassis102, e.g., clock signal123b.

FIG. 2is functional block schematic of a testing blade250in accordance with an embodiment of the invention. The testing blade250includes a faceplate or bulkhead202as a signal interface and a connector204for coupling to a communication bus or backplane. The bulkhead202for most blades typically includes status indicators. These status indicators are often in the form of LEDs (light-emitting diodes) providing state indication, e.g., active, disconnected, failed, etc., or LCDs (liquid crystal displays) providing alphanumeric, graphical or other indications, e.g., error codes, analog readings, histograms or text messages. For one embodiment, the testing blade250includes an LED indicator230and an LCD indicator232.

The testing blade250further includes a microcontroller unit or processor206, coupled to the connector204, for controlling the operation of the testing blade250. Some communications from the processor206may pass through a UART (universal asynchronous receiver/transmitter)210for providing asynchronous data at a data output226of the bulkhead202. The data output226may be used for communication with other blades of a bladed server. A data input228of the bulkhead202may be used for commands and data from a test executive or other user interface. A memory244may be used to store commands and data values, such as discrete desired clock characteristics, such as frequencies and amplitudes, or data used to derive the desired clock characteristics, such as an initial value, an end value and an increment value or ramp rate. Access port229may be provided to externally sample a ground potential used by the testing blade250.

For the embodiment depicted inFIG. 2, one or more clock signals223are generated in response to a desired frequency and, optionally, a desired amplitude received at the testing blade250. The desired frequency and amplitude may be received from a test executive or other user interface, and stored in the memory244. One or more of the clock signals223, e.g.,2231-223n, may be provided through ports2241-224n, respectively, for use as clock inputs to a device (not shown inFIG. 2) to be tested, such as a clock input to a server blade. These clock signals223may, for example, be provided to one or more server blades of a bladed server containing the testing blade250as well as one or more server blades of other bladed servers. An additional clock signal223, e.g.,2230, may be utilized as a feedback signal for control of the clock signals223at or near desired frequency and amplitude. The clock signal2230or another one of the clock signals223may also be provided to an access port227through a buffer234for direct sampling by a user. Each of the clock signals2230-223nshould have substantially the same characteristics of frequency and amplitude. Accordingly, they may be deemed to be a single clock signal223split to multiple locations.

For one embodiment, the clock signal2230is compared against the desired frequency and amplitude by first generating values indicative of the frequency and amplitude of the sensed clock signal2230. For example, the clock signal2230may be provided to an integrator/ramp generator236and a peak detector238in series for generating an analog signal, e.g., a voltage signal, indicative of the frequency of the clock signal2230. In addition, the clock signal2230may be provided to a peak detector240for generating an analog signal indicative of the amplitude of the clock signal2230.

These analog signals may then be converted to digital signals, such as by an analog-to-digital converter242, for use by a processor206. The analog-to-digital converter242may further be multiplexed for converting a selected one of the analog signals into a corresponding digital signal for use by the processor206in response to a channel select signal243. Alternatively, a dedicated analog-to-digital converter242may be provided for each analog signal. The resulting digital signals are indicative of the frequency and amplitude of the output clock signals223.

The digital signals or values representative of the frequency and amplitude of the clock signals223are provided to the processor206for comparison to the desired clock signal characteristics. The processor206generates a control signal, for each characteristic of the clock signals223, indicative of any desire to modify that characteristic. For example, if the comparison indicated that the sensed frequency was less than the desired frequency, the processor206would generate a control signal indicative of a desire to increase the frequency of the clock signals223. It is noted that the control signal indicative of a desire to modify a characteristic may indicate that no modification is required.

For one embodiment, a potentiometer208provides a first control signal209in response to input received from the processor206. The first control signal209is indicative of any desire to modify the frequency of the clock signals223. The first control signal219is provided to a first OpAmp (operational amplifier), such as frequency OpAmp212, for use in controlling the frequency of the output clock signals223. The potentiometer208is preferably a digital potentiometer for receiving a digital control signal from the processor206and providing a variable voltage output.

The output of the OpAmp212is provided to an oscillator, such as the voltage-controlled oscillator (VCO)214, for generation of an intermediate clock signal215having a frequency. The OpAmp212provides signal isolation and current sourcing between the potentiometer208and the VCO214. The output of the VCO214may be passed through a buffer218for signal isolation and provided to a clock driver222for control of the frequency output of the clock driver222. The output of the VCO214may be synchronized with a reference clock216.

The potentiometer208, also in response to the comparison of the characteristics of the sensed clock signal223to the desired characteristics, further provides a second control signal211for control of the amplitude of the output clock signals223. The second control signal211may be passed through a second OpAmp, such as amplitude OpAmp220, for signal isolation and current sourcing. The second control signal211is then provided to the clock driver222for control of the gain of the clock driver222, and hence the amplitude of the resulting clock signals223.

As depicted inFIG. 2, the potentiometer208includes a first potentiometer208afor generating the first control signal for controlling the output clock signal frequency and a second potentiometer208bfor generating the second control signal for controlling the output clock signal amplitude. For another embodiment, the oscillator for generating the intermediate clock signal215may be a numerically controlled oscillator (NCO). While VCOs rely on a voltage signal as their control signal, NCOs utilize a digital signal. Thus, using an NCO as the oscillator would permit variation of the intermediate clock signal215directly by the processor206without a digital-to-analog conversion.

The clock driver222generates the output clock signals223in response to the intermediate clock signal215and, optionally, the amplitude control signal211. A clock driver transforms an input clock signal into an output clock signal having appropriate voltages, or amplitude, for a target receiving device. A clock driver thus provides an output clock signal having the frequency characteristics of an input clock signal, such as the intermediate clock signal215, adjusted by some gain factor, such as in response to the amplitude control signal211. The clock driver222should thus be chosen to provide an appropriate output clock signal for the desired target devices, such as server blades. For one embodiment, the amplitude of the output clock signals223is substantially constant, thus not requiring an amplitude control signal211.

FIG. 3is a flowchart showing testing of a bladed server in accordance with an embodiment of the invention. At305, the test executive invokes the testing blade. For one embodiment, this involves sending an escape sequence to a data input of the testing blade. At310, commands and data are provided to the testing blade from the test executive to instruct the testing blade to adjust the frequency and, optionally, the amplitude of the output clock signals for testing of the bladed server or individual server blades at operating clock characteristics that are lower or higher than nominal conditions. While it is possible to manually provide data and commands to the testing blade such that a user or administrator acts as the test executive, it is preferred that the test executive be automated to sequence the testing blade through a variety of operating conditions without further user interaction.

At315, the testing blade varies the characteristics of the output clock signal in response to the data and commands provided by the test executive. A typical test sequence might be to vary the output clock signal from −10% of nominal to +10% of nominal, such as by 1% increments. In general, the testing blade generates an output clock signal having a frequency and an amplitude. For varying the frequency of the output clock signal, the frequency is sensed and a value indicative of the frequency is generated. This value is then compared to a value indicative of the desired frequency. Based on this comparison, the frequency of the output clock signal is then modified as necessary. For varying the amplitude of the output clock signal, the amplitude is sensed and a value indicative of the amplitude is generated. This value is then compared to a value indicative of the desired amplitude. Based on this comparison, the amplitude of the output clock signal is then modified as necessary.

At320, the testing blade gathers and/or displays information related to the operation of the bladed server at the various clock signal characteristics, such as measured operating conditions, desired settings, any error or status codes generated by the blades, etc. By adjusting the clock signal characteristics provided to one or more server blades, operation at marginal conditions may assist in identifying and exposing latent failures of the bladed server's components. In addition, during design phases, such testing can provide guidance on component selection to facilitate improvements in device quality and reliability.

FIG. 4is a flowchart showing testing of a bladed server in accordance with a further embodiment of the invention. At405a signal is received at the testing blade indicative of a desired frequency and/or amplitude of a clock signal. The signal is indicative of a desired frequency of a clock signal for use by the bladed server that is different than a nominal clock signal frequency for use by the bladed server. The desired amplitude of the clock signal for use by the bladed server may also be different than a nominal clock signal amplitude for use by the bladed server. At410, an output clock signal is generated at the testing blade. The clock signal will have a frequency and an amplitude.

At415, the frequency and/or amplitude of the output clock signal is sensed. In response to the sensing of the frequency and/or amplitude, a value indicative of the sensed frequency and/or amplitude, respectively, is generated. At425, the value indicative of the sensed frequency and/or the value indicative of the sensed amplitude are compared with a value indicative of a desired frequency and/or a value indicative of a desired amplitude, respectively. At430, the frequency and/or amplitude of the output clock signal is then modified, as needed, in response to the comparison.

A frequency margin testing blade is adapted for use in a bladed server. The testing blade is further adapted to provide one or more output clock signals for use as clock inputs to one or more server blades internal to the bladed server in which the testing blade is installed and/or one or more server blades external to the bladed server in which the testing blade is installed.