A duty-cycle distortion self-correcting delay line has an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal. The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.

FIELD OF THE INVENTION

The present disclosure relates to very-large-scale integration (VLSI) complementary metal-oxide-semiconductor (CMOS) digital circuit clock signal delay lines.

BACKGROUND

Very-large-scale integration (VLSI) is a method of producing an integrated circuit having a very large number of transistors. Complementary metal-oxide-semiconductor (CMOS) is one technique for making integrated circuits such as microprocessors, memory, and digital logic circuits. Many digital logic circuits are implemented using p-type metal-oxide-semiconductor logic (PMOS) and n-type metal-oxide-semiconductor logic (NMOS) which respectively use p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs).

Typical synchronous digital logic circuits employ a clock signal to synchronize circuit actions. A typical clock signal takes the form of a square wave having a fixed duty cycle and frequency, wherein the duty cycle designates the ratio of the pulse width to the pulse period, and a clock pulse designates a single period of the square wave. Circuits synchronized to the clock signal respond to one or more “transition edges”, which may include either the rising edge, the falling edge, or both the rising and falling edges of the clock signal square wave. When a circuit is responsive to both the rising and falling edges, it is said to operate at a double data rate (DDR).

A delay line is a common design technique used to adjust clock or data edges in a digital circuit. A delay line is typically a regular structure comprising a chain of delay elements such as buffers. The signal is delayed by the length of the delay element thus enabling adjustment of the transition edge or edges to the desired timing window. Usually, the amount of adjustment is process, voltage, and temperature dependent, and therefore delay lines are sometimes programmable wherein the effective number of delay elements in the chain can be adjusted via external controls. The length of a delay line may be expressed in terms of the number of delay elements engaged, or “delay taps”.

Duty cycle distortion (DCD) is a variance between the duty cycle of a clock pulse at the destination as compared to the duty cycle at the source. DCD occurs when the propagation delay of the rising edge is different from the propagation delay of the falling edge. DCD can be a result of aging including a degradation of device performance over time due to effects such as electro-migration (EM) or negative bias temperature instability (NBTI). The speeds of aging for PMOS and NMOS transistors are non-symmetrical and are dependent of the state of the transistors. For example, a metal-oxide-semiconductor (MOS) ages faster when it is “on” than when it is “off”.

Duty cycle distortion is a concern when the delay line is used on a clock signal and both rising and falling edges are used, as in a double data rate interface. In such a case, a delay line is typically used to adjust the clock edges to align with data edges within the budgeted timing window. If DCD is too large (i.e., propagation delay of the rising edge is very different from that of falling edge), it may not be possible to align both rising and falling edges of the clock to data. In order to meet the timing specification, DCD must be minimized.

A single delay element in a delay line can be designed with minimal DCD—that is, the propagation delay of a rising edge is equal to the propagation delay of a falling edge within predefined tolerances—and is thus said to be balanced, for a particular process corner (meaning an extreme of possible circuit fabrication parameters). It is, however, difficult to maintain minimal DCD across all process corners. For example, if a delay element is balanced in the slow-slow (SS) or fast-fast (FF) process corner, DCD usually increases in the fast-slow (FS) or slow-fast (SF) process corners. Furthermore, DCD can accumulate and become very large as the delay line becomes longer. For example, a 0.5 picosecond DCD in a single delay element can add up to hundreds of picoseconds when the delay line is hundreds of elements long.

Moreover, due to the non-symmetrical nature of the aging effect for PMOS and NMOS transistors, a perfectly balanced delay line may still develop DCD over time.

It remains desirable, therefore, to develop improved techniques for reducing duty cycle distortion in digital circuit clock signal delay lines.

SUMMARY

Embodiments disclosed herein overcome or ameliorate disadvantages of prior methods, provide additional capabilities or advantages, or provide alternative means for producing desirable results.

A duty-cycle distortion self-correcting delay line may have an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal.

The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.

Each additional delay element in the programmable delay lines may be selectively engaged in a ring pattern such that a number of delay elements in any one of the programmable delay lines differs from a number of delay elements in any other one of the programmable delay lines by one at most.

The general outline provided above enables a better understanding of the detailed description of embodiments which follows. Such embodiments include additional features and advantages, and it will be appreciated by persons of ordinary skill in the art that the particular embodiments described below may be modified or built upon to perform the same functions and provide the same results set forth herein while not departing from the spirit and scope of the subject matter set forth in the appended claims.

DETAILED DESCRIPTION

Particular embodiments will now be described in a context of delay lines for digital circuit clock signals. It will be appreciated by persons of ordinary skill in the art, however, that the principles set forth herein may be applied to adapt the embodiments to any related or similar context.

A programmable delay line may be implemented in many different ways.FIGS. 1,2, and3illustrate three different implementations of programmable delay lines.

For example,FIG. 1shows a programmable delay line100having a chain of multiplexers110serving as delay elements, each of which receives a signal from buffer120which receives a signal from data signal input130, and a control signal140. The chain of multiplexers110outputs to a data signal output150. The control signal140controls a number of one or more consecutive multiplexers110immediately preceding the data signal output150to select the input connected to the preceding multiplexer110as opposed to the input connected to buffer120. Thus, the control signal140controls the length of the sub-chain of multiplexers110which receives and propagates signal from buffer120to the data signal output150.

FIG. 2shows another programmable delay line200having an array of delay elements210connected in a chain to an data signal input220. A control signal230controls a multiplexer240connected to a data signal output250to select as input the output of one of the array of delay elements210. Thus, the control signal230controls the length of the sub-chain of delay elements210which a signal from data signal input220traverses before reaching multiplexer240and data signal output250.

FIG. 3shows yet another programmable delay line300similar to programmable delay line100. Programmable delay line300has a chain of multiplexers310each receiving a signal from a corresponding buffer320connected in a chain to an data signal input330. Each multiplexer310also receives a control signal340. The control signal340controls a number of one or more consecutive multiplexers310immediately preceding the data signal output350to select the input connected to the preceding multiplexer310as opposed to the input connected to its corresponding buffer320. Thus, the control signal340controls the length of the sub-chain of multiplexers310and corresponding buffers320which receives and propagates signal from data signal input330to data signal output350. Programmable delay line300is thus similar to programmable delay line100, except in that each multiplexer310is associated with a corresponding buffer320which bears the load of the corresponding multiplexer310, while in programmable delay line100, the single buffer120bears the load of the entire chain of multiplexers110selectively connected to the buffer120by the control signal140.

The techniques disclosed herein are not restricted to any specific implementation of programmable delay line. The technique converts or employs any type of delay line into one that may automatically minimize duty cycle distortion in any process, temperature, and voltage corners.

A balanced programmable delay line400adapted for self-correcting duty cycling distortion is shown inFIG. 4. The balanced programmable delay line400has a data signal input402, an data signal output404, and an even number 2N of delay lines405including a first delay line406, a second delay line408, and so on, up to a 2N−1th delay line410, and finally a 2Nth delay line412. Each delay line405may receive a control signal403for selectively engaging a number of elements, or taps, in each delay line405, as described above.

The balanced programmable delay line400further has an even number 2N of inverting elements413including a first inverting element414, a second inverting element416, and so on, up to a 2N−1th inverting element418, and finally a 2Nth inverting element420.

The first inverting element414may be connected to the data signal input402and the first delay line406, and precede the first delay line406in a path between the data signal input402and the data signal output404, the second inverting element416may be connected to and follow the first delay line406and be connected to and precede the second delay line408in the path between the data signal input402and the data signal output404, and so forth, up to the 2N−1th inverting element418which is connected to and follows a 2N−2th delay line (not shown) and is connected to and precedes the 2N−1th delay line410, and a 2Nth inverting element420which is connected to and follows the 2N−1th delay line410and is connected to and precedes the 2Nth delay line412which is connected to the data signal output404. Thus, each inverting element413may be connected to and precede a corresponding delay line405in the path from the data signal input402to the data signal output404.

In the balanced programmable delay line400, a signal received at data signal input402is propagated to the data signal output404as follows. The signal is inverted by the first inverting element414, passed with delay by the first delay line406, inverted by the second inverting element416, passed with delay by the second delay line408, and so on, until it is received and inverted by the 2N−1th inverting element418, and then passed with delay by the 2N−1th delay line410, and then inverted by the 2Nth inverting element420, and then passed with delay by the 2Nth delay line412, and then passed to data signal output404. Half of the delay lines405receive the uninverted signal, while the other half of the delay lines405receive the inverted signal. As such, if the data signal input402is a square wave pulse of a clock signal, for example, one half of the delay lines405propagate a rising edge, and the other half of the delay lines405propagate a falling edge. Consequently, the respective duty cycle distortions in the first and second halves of the delay lines405are opposite and thus cancel each other out.

As indicated above, in balanced programmable delay line400each inverting element413may be connected to and precede a corresponding delay line405in the path from the data signal input402to the data signal output404. Alternatively, as shown inFIG. 5, each inverting element413in balanced programmable delay line500may be connected to and follow a corresponding delay line405in the path between the data signal input402and the data signal output404, and balanced programmable delay line500is otherwise identical to balanced programmable delay line400, and possesses substantially the same functionality and produces substantially the same result as balanced programmable delay line400. In all the embodiments of balanced programmable delay line400described herein, therefore, it will be understood that the inverting elements413may be connected to and follow a corresponding delay line405as in the case of balanced programmable delay line500, as opposed to being connected to and preceding the corresponding delay line405as in balanced programmable delay line400, and thus such alternative will not be repeated in connection with each embodiment for the sake of efficient description.

In all the embodiments of balanced programmable delay line400described herein, it will be understood that the balanced programmable delay line400may have any even number of delay lines405and corresponding inverting elements413, including only two delay lines406,408and two corresponding inverting elements414,416as in the embodiment shown inFIG. 6, and thus such alternatives will not be repeated in connection with each embodiment for the sake of efficient exposition.

In general, control signal403controls the number of delay taps engaged in each delay line405. The control signal403may be configured to engage only the same number of delay taps in each delay line405, or it may be configured to engage a first number of delay taps in one delay line405which is different from a second number of delay taps in another delay line405. In general, if control signal403is configured to engage a number of delay taps which is not evenly divisible by 2N, wherein the balanced programmable delay line400has 2N delay lines405, then one or more of the delay lines405may have engaged a number of delay taps which is different from a number of delay taps engaged in another delay line405.

As shown inFIG. 7, control signal403(not shown) may be configured so as to engage each additional delay tap in the balanced programmable delay line400in a ring sequence.FIG. 7shows a number of configurations of balanced programmable delay line400wherein a different number of delay taps are engaged. (Some of the elements shown inFIG. 4are omitted fromFIG. 7for clearer illustration of these configurations, but the various configurations of the balanced programmable delay line400shown inFIG. 7should be understood as including the omitted elements nevertheless.) The configurations include a first configuration702with one delay tap engaged, a second configuration704with two delay taps engaged, a third configuration706having three delay taps engaged, a fourth configuration708having four delay taps engaged, a fifth configuration710having five delay taps engaged, and a sixth configuration712having six delay taps engaged. The delay taps may be engaged in a sequence beginning with the first delay tap722in the first delay line406, the second delay tap724in the second delay line408, up to a 2Nth delay tap726in the 2Nth delay line412, and then return to activate a 2N+1th delay tap728in the first delay line406, a 2N+2th delay tap730in the second delay line408, up to a 4Nth delay tap732in the 2Nth delay line412, and so on. By following this pattern, a difference in the number of delay taps engaged between any two delay lines405is at most one.

Similarly, if, as shown inFIG. 6, balanced programmable delay line400has only two delay lines406,408and two corresponding inverting elements414,416, then the control signal403may be configured so as to engage each additional delay tap in programmable delay lines406,408alternatingly.

If a number of engaged delay taps of a first half of the delay lines receiving an uninverted signal is equal to a number of engaged delay taps of a second half of the delay lines receiving an inverted signal, then the respective duty cycle distortions of the first and second halves of the delay lines405are opposite and thus cancel each other out.

If, however, a first number of engaged delay taps of a first half of the delay lines receiving an uninverted signal is unequal to a second number of engaged delay taps of a second half of the delay lines receiving an inverted signal, and in particular the first number differs from the second number by one, then the duty cycle distortion may include a contribution by the additional delay element. Otherwise, the duty cycle distortion which remains may be due to a difference in loading at the end of each delay line or a difference in transition time (slew rate) at the beginning of each delay line.

Each one of inverting elements413may be implemented in any suitable way, and in particular may include any inverting circuit element whose selection may depend on design parameters. For example, as shown inFIG. 8, each inverting element413may be implemented as an inverter, such that first inverting element414, second inverting element416, and so on, up to 2N−1th inverting element418, and lastly 2Nth inverting element420, are implemented as first inverter802, second inverter804, and so on, up to 2N−1th inverter806, and lastly 2Nth inverter808.

As noted above, duty cycle distortion may be caused in part by aging of the delay lines including the delay taps. As such, if the balanced programmable delay line400receives a signal at data signal input402which is constantly toggling, and thus the delay lines405receive signals which are likewise constantly toggling, they will experience equal or substantially similar aging and their respective contributions to the duty cycle distortion will remain equal or substantially similar and thus continue to cancel out over time. If, however, the signal received at data signal input402is not constantly toggling, and instead remains high or low for extended or substantially unequal periods of time, such as when the balanced programmable delay line400is idle, for example, then the respective aging experienced by a first half of the delay lines405held in an uninverted state may be different from the aging experienced by a second half of the delay lines405held in an inverted state, thus resulting afterward in imperfect cancellation of the duty cycle distortion. This may result at least in part from the non-symmetrical nature of aging effects on PMOS and NMOS transistors, with the result that duty cycle distortion for different delay lines405starts to diverge if they stay at constant but opposite states for extended periods of time.

Thus,FIG. 9shows a balanced programmable delay line900which is identical to balanced programmable delay line400except as follows. In the programmable delay line900, each inverting element413is implemented as an XNOR gate, such that first inverting element414, second inverting element416, and so on, up to 2N−1th inverting element418, and lastly 2Nth inverting element420, are implemented as first XNOR gate902, second XNOR gate904, and so on, up to 2N−1th XNOR gate906, and lastly 2Nth XNOR gate908. In addition to receiving data signal input402and sending data signal output404, the programmable delay line900also has an anti-aging signal input910connected to one of the inputs of each of the XNOR gates902,904,906,908.

When the anti-aging input910is not asserted (is held low), the XNOR gates902,904,906,908function identically to inverting elements, such as inverters802,804,806,808, and thus alternating uninverted and inverted signals are propagated across the delay lines405, as is the case generally in balanced programmable delay line400. When the anti-aging input910is asserted (is held high), the XNOR gates902,904,906,908pass the signal at their respective inputs, and thus the respective signals propagated across the delay lines405are the same. In this way, by asserting the anti-aging input910while the balanced programmable delay line900is idle, for example, any aging experienced by the respective delay lines405may be the same, and thus a difference in the respective duty cycle distortions is avoided.

A balanced programmable delay line may be implemented using any desired components or designs to provide the functionality described herein. For example, a balanced programmable delay line may be implemented with an anti-aging circuit, as described above, wherein the inverting elements are implemented as XOR gates instead of XNOR gates.

Thus, as shown inFIG. 10, balanced programmable delay line1000may be identical to balanced programmable delay line900except as follows. In the programmable delay line1000, each inverting element413is implemented as an XOR gate, such that first inverting element414, second inverting element416, and so on, up to 2N−1th inverting element418, and lastly 2Nth inverting element420, are implemented as first XOR gate1002, second XOR gate1004, and so on, up to 2N−1th XOR gate1006, and lastly 2Nth XOR gate1008. In addition to receiving input402and sending data signal output404, the programmable delay line1000also has an anti-aging signal input910connected to an inverting element, which may be an inverter1001, which is then connected to one of the inputs of each of the XOR gates1002,1004,1006,1008.

When the anti-aging input910is not asserted (is held low), the inverter1001output is held high, and thus the XOR gates1002,1004,1006,1008function identically to inverting elements, such as inverters802,804,806,808, and thus alternating uninverted and inverted signals are propagated across the delay lines405, as is the case generally in balanced programmable delay line400. When the anti-aging input910is asserted (is held high), the inverter1001output is held low, the XOR gates1002,1004,1006,1008pass the signal at their respective inputs, and thus the respective signals propagated across the delay lines405are the same. Thus, as in the case of balanced programmable delay line900, by asserting the anti-aging input910while the balanced programmable delay line1000is idle, for example, any aging experienced by the respective delay lines405may be the same, and thus a difference in the respective duty cycle distortions is avoided.

In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments of the invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof.

Embodiments of the invention can be represented as a software product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the invention. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described invention can also be stored on the machine-readable medium. Software running from the machine-readable medium can interface with circuitry to perform the described tasks.

The above-described embodiments are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art. The scope of the claims should not be limited by the particular embodiments set forth herein, but should be construed in a manner consistent with the specification as a whole.