Spectrum profile control for a PLL and the like

Frequency spectrum spreading of a timing recovery circuit, such as a PLL, is controlled by periodically calculating each value for a divisor, M, of a fractional divider in the feedback path of the PLL. The fractional divider divides the output signal of a voltage-controlled oscillator (VCO) of the PLL by the divisor, M, and the value for divisor, M, is periodically updated based on a spreading profile. The output of the fractional divider and a reference clock signal are provided to a phase detector of the PLL so as to cause the PLL to slew the output frequency of the PLL in accordance with the spreading profile.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to phase-locked loop (PLL) circuits, and, more particularly, to controlling a profile of the PLL circuit's output frequency spectrum.

2. Description of the Related Art

In many electronics applications, digital circuits are employed that operate with one or more clock signals. Personal computers commonly employ a processor that may operate based on a clock having a frequency of 350 MHz or more. However, at such high frequencies, these digital circuits may radiate signals as electromagnetic energy, and these electromagnetic emissions may interfere with the operation of surrounding equipment. Since these emissions are based upon clock signals, high emitted energy “spikes” occur at these clock signal frequencies and their harmonics. Consequently, equipment is often shielded to prevent or minimize these emissions within certain frequency ranges, or operation is modified to spread the emitted energy over a wider frequency range, thereby decreasing the energy at any given frequency. One technique for modifying the operation of a digital circuit is to vary the clock frequency over a range of frequencies such that the average frequency is the desired clock frequency, but the emitted energy is now “spread” over the range of frequencies. Such variation of the clock is termed “spread spectrum” and reduces the interference from high energy spikes at the clock frequency.

A synthesizer generating one or more clock signals often employs a phase-locked loop (PLL). A PLL is a circuit that generates a periodic output signal that has a constant phase and frequency with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL, which is described in Floyd M. Gardner, “Charge-Pump Phase-Lock Loops”IEEE Trans. Commun.,vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference. In many applications, the frequency of the output signal is higher than the frequency of the input signal.

In a conventional charge-pump phase-locked loop, a phase detector (PD) compares the phase θINof the input reference clock signal to the phase θOUTof a feedback signal derived from the PLL output. Based on the comparison, the PD generates an error signal: either an UP signal (when θINleads θOUT) or a DOWN signal (when θOUTleads θIN), where the error signal indicates the difference between θINand θOUT. A charge pump generates an amount of charge equivalent to the error signal from the PD, where the sign of that charge indicates the direction of UP or DOWN. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the capacitance in a loop filter. As such, the loop filter operates as an integrator that accumulates the net charge from the charge pump. The resulting loop-filter voltage VLFis applied to a voltage-controlled oscillator (VCO). A voltage-controlled oscillator is a device that generates a periodic output signal, whose frequency is a function of the VCO input voltage. Input and feedback dividers may be placed in the input and feedback paths, respectively, if the frequency of the output signal is to be either a fraction or a multiple of the frequency of the input signal.

One method of spread spectrum to vary a clock frequency employs modification of the feedback divider used to control the output clock frequency of the PLL. The feedback divider typically divides the output signal of the VCO by a fixed number N to generate a signal close, in frequency, to the input reference clock signal. By varying the value of N, the divided output of the VCO applied to the phase detector also varies the output frequency of the VCO. Spread spectrum techniques of the prior art typically vary the frequency in discrete steps by reading successive values for N from a table stored in memory and supplying the successive values of N to the feedback divider.

SUMMARY OF THE INVENTION

The present invention relates to a phase-locked loop (PLL) circuit that employs spectrum spreading of the PLL output signal frequency. Frequency spectrum spreading of the PLL is controlled by periodically calculating each value for a divisor, M, of a fractional divider in the feedback path of the PLL. The fractional divider divides the output signal of a voltage-controlled oscillator (VCO) of the PLL by the divisor, M, and the value for the divisor, M, is periodically updated based on a spreading profile. The output of the fractional divider and a reference clock signal are provided to a phase detector of the PLL so as to cause the PLL to slew the output frequency of the PLL in accordance with the spreading profile.

In accordance with exemplary embodiments of the present invention, a signal generator circuit calculates, in real time, a divisor value in accordance with a spreading profile characterized by a function. A fractional divider divides an output signal of the signal generator circuit by the divisor value. The signal generator adjusts, based on the divided output signal and a reference signal, a frequency of the output signal of the signal generator circuit; and one or more new divisor values are subsequently calculated in accordance with the spreading profile so as to slew the frequency of the output signal of the signal generator without discontinuities in the slewed frequency.

DETAILED DESCRIPTION

FIG. 1shows a block diagram of phase-locked loop (PLL)100having spread spectrum control and operating in accordance with an exemplary embodiment of the present invention. PLL100comprises voltage-controlled oscillator (VCO)101, fractional divider102, phase detector (PD)103, charge pump (CP)104, loop filter (LF)105, and spreading profile controller106. PLL100tends to synchronize the frequency fVCOof the output signal VCOOUTprovided by VCO101to a frequency that is a multiple of the frequency fREFof the reference clock REF_CLK.

Loop-filter voltage VLFis a control voltage applied to VCO101to set the frequency of the output signal provided by VCO101. VCO101might be implemented as an inductor-capacitor (LC) oscillator having a fixed inductor value and a variable capacitor value. Other types of VCOs well-known in the art, such as crystal or ring oscillator VCOs, might be employed for VCO101. The output signal VCOOUTof VCO101is provided as the output signal of PLL100.

The output signal VCOOUTof VCO101is also provided to fractional divider102, which divides the output signal of VCO101by a divisor, M, to generate a feedback clock signal FB_CLK having phase θOUT. M may be i) an integer or iii) an integer plus a non-integer fraction. Consequently, the frequency fVCOof the signal provided by VCO101is related to the frequency fREFof the reference clock REF_CLK by fVCO=fREF*M.

In accordance with exemplary embodiments of the present invention, spreading profile controller106generates a desired value MDESfor the divisor, M, according to a spreading profile, such as a triangular profile, as described subsequently. Spreading profile controller106receives one or more spreading parameters, an “ON” signal indicating spreading is enabled, a select signal to select one of a plurality of spreading profiles, and either the reference clock signal REF_CLK or feedback clock signal FB_CLK. For preferred embodiments of the present invention, spreading profile controller106receives the feedback clock signal FB_CLK to allow for proper timing between generation of the divisor, M, and the fractional division of the VCO output signal VCOOUT. Spreading profile controller106generates a sequence of desired values for MDESin real time in accordance with a specified input function that defines the spreading profile by one or more spreading parameters, such as modulation rate, modulation depth, and contour coefficients. For example, if varying the frequency up and down linearly, the slope and direction (up/down in frequency or about a mean) might be provided as spreading parameters. The spreading profile defines slewing of the VCO's output signal frequency across a predefined range of frequencies. Spreading profile controller106might be implemented with a microprocessor, state machine, or other form of processor.

PD103compares the phase θINof the input reference clock signal REF_CLK to the phase θOUTof feedback clock signal FB_CLK from fractional divider102. Based on the comparison, PD103generates an either an UP signal (when θINleads θOUT) or a DOWN signal (when θOUTleads θIN), where the error signal indicates the magnitude of the difference between θINand θOUT. CP104generates an amount of charge equivalent to the error signal from PD103, where the sign of that charge corresponds to the direction of UP or DOWN. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the capacitance of loop filter105. The loop filter may have a relatively simple design, comprising a capacitor in parallel with the series combination of a resistor R and a relatively large capacitor. Loop filter105accumulates the net charge from CP104to generate the loop-filter voltage VLFthat sets the frequency of the output signal of VCO101.

FIG. 2shows an exemplary embodiment of spreading profile controller106and fractional divider102. As shown inFIG. 2, divisor M generator201of spreading profile controller106receives a signal “ON” to enable spreading, one or more spreading parameters including the nominal value for M, MNOM, and the FB_CLK signal for timing generation of values for the divisor, M, that is synchronized to the feedback clock signal. Synchronizing the generation of values for the divisor, M, to the feedback clock signal allows for updating the phase accumulation for the fractional accumulation technique, described subsequently. Divisor M generator201might instead receive the reference clock signal REF_CLK for timing generation of values for the divisor, M, if other means are employed to update the phase accumulation. Divisor M generator201generates a desired value MDESfor the divisor, M, according to a spreading profile, which desired value MDES. The difference between the current and desired value for M is then applied to combiner202of spreading profile controller106. The desired value MDESis represented as an integer and a fraction with a given precision.

Since the desired value MDESmight not be an integer, the divider in the feedback path is a fractional divider. Various types of fractional dividers are known in the art and may be employed for the present invention. In the exemplary embodiment ofFIG. 2, a fractional accumulation technique is employed for fractional division of the VCO's output signal. In the fractional accumulation technique, an integer counter is employed to divide the input signal by two integers N and D. In the counter, multiple phases of the divided VCO output signal might be available. For example, since a counter is implemented as a series of coupled registers, the values of each register correspond to a particular phase of the counter sequence. If a counter has N is 4, then each register of the counter provides a 90 degree phase-shifted version of the counter's output sequence. In general, if the counter divides by N, there are N replicas of the divided signal shifted in phase with respect to one another by 2π/N.

To obtain a fractional divider, the frequency of the digital signal is divided by two different non-zero integers N and D. The divisions by N and D are alternately performed, as appropriate; an average division between these two values is thus obtained. The resulting signal thus actually corresponds to the input digital signal, the frequency of which is divided by a fractional number comprised between N and D. The resulting signal exhibits a phase error which is all the greater as values N and D are distant from each other. The phase error (also termed jitter) of the resulting signal is proportional to the period of the input signal multiplied by the difference between values N and D. Since N and D are integers, the minimum jitter corresponds to the minimum interval between these two values, which is 1, yielding alternating division between N and (N+1).

Another factor is the resolution of the fractional component of the divisor, which is related to the number K of clock cycles over which the fractional divider generates the average fractionally divided signal. The resolution, K, is also the phase error per clock cycle division. By accumulating the phase error (phase accumulation), the point where the phase accumulation exceeds 360 degrees is where the division by N is reset to division by (N+1). For example, if the VCO output signal is to be divided by 2.5, each clock cycle a division of the signal by two is performed and the phase accumulation is advanced by 180 degrees. The phase accumulation is updated by adding 180 degrees for each clock cycle. Once the phase accumulation passes 0 degrees (i.e., goes through 360 degrees), the signal is then divided by 3.

Returning toFIG. 2, to divide by a value MDESthat is represented by an integer and a fraction, the integer value FBDIV of MDESis employed as the value for N of the counter, and the value of the fraction is converted to a phase value PH_ACCUM. Dividing the input signal by the integer FBDIV instead of the whole value MDEScreates a phase error between the actual and desired divided input signal. The phase error might then be corrected for by advancing or delaying the phase of the output signal. Consequently, the phase error is tracked and accumulated as PH_ACCUM for each clock cycle. The phase value PH_ACCUM is employed to address a specific phase of the counter to provide a shifted phase of the divided input signal that corresponds to the fractional division of the input signal at the current clock instant. Since the integer and/or fractional part of MDESincreases or decreases as MDESis updated on each clock cycle, the values of FBDIV and PH_ACCUM are updated to account for the phase error from the update of MDESin addition to the tracked phase error for the fractional division. Once the value of PH_ACCUM crosses the 0 value, the counter value is increased by 1 to divide by FBDIV+1.

Spreading profile controller106includes an accumulator comprising combiner202(which may be implemented as an adder) and register203. Fractional divider102comprises counter204. Counter204is an integer counter that counts to FBDIV, and the phase of the output of counter204may be selected via PH_ACCUM to implement the fractional accumulation technique described above. The current value of MDESand the previous integer and phase values, FBDIV and PH_ACCUM, corresponding to the previous value of MDESfrom register203, are combined by combiner202to generate updated values for FBDIV and PH_ACCUM. The updated values for FBDIV and PH_ACCUM from combiner202are provided to register203. The updated values for FBDIV and PH_ACCUM from register203are provided to counter204. Consequently, counter204performs fractional division of VCOOUTby MDESto provide θOUT.

The following Verilog pseudo code might be employed to implement a phase accumulation fractional divider.

While the exemplary embodiment of the present invention is described having a fractional divider that employs a phase accumulation technique to perform a fractional division of an input signal, the present invention is not so limited. One skilled in the art may extent the teachings herein to other implementations for fractional dividers.

Jitter performance of PLL100is a function of the noise added by the variable feedback value for M and the loop response of the PLL. While PLL100is in a locked state, the average output frequency of the PLL is a multiple of the fractional feedback value of the divisor, M.

FIG. 3shows an exemplary triangular spreading profile generated by spreading profile controller106for the PLL of FIG.1. The exemplary triangular spreading profile varies the frequency of the VCO output signal from a nominal frequency fNOMdown to a minimum frequency fMIN. In practice, since the value for M is changed at discrete intervals and because the value for M has a finite-length digital representation, the spreading profile is quantized.FIG. 4shows an exemplary quantized triangular spectrum control profile for the PLL of FIG.1. In general, the frequency steps of the quantized triangular spectrum control profile might be smoothed by the loop filter response of the PLL, although additional filtering might be applied.

To create the quantized triangular spreading profile ofFIG. 4, an algorithm steps down the value of M from a nominal M value (MMAX) by a given amount, termed the step size or slope value, until the minimum value (MMIN) for M is reached, and then steps up M by the slope value until the nominal M value MMAXis reached. The process is then repeated. The amplitude of the spreading is set by the minimum value for M, which might be expressed as a fractional M value. For example, for a 30-MHz reference clock signal REF_CLK and an M value of 20, the nominal PLL output frequency might be 600 MHz. If a 0.5% down spread is desired, then the minimum value for M is 20−(20*0.005)=19.9. The minimum value for M, MMIN, and the slope value might be pre-computed and stored in a register, or, if the spreading profile were programmable, then MMINand slope value might be generated in real time based on a set of input parameters. The modulation rate of the spreading profile is the rate at which the frequency is slewed, where the modulation rate is related to the slope value as in equation (1):

WhileFIGS. 3 and 4illustrate down spreading, up spreading might be accomplished by setting the maximum value of M greater than the nominal value for M. In addition, a spreading algorithm might include the features of i) turning spreading “on” and “off” and ii) holding the value of M at a lower (or upper) limit.

FIG. 5shows an exemplary method for implementing the quantized triangular spreading profile of FIG.4. At step501, an optional test determines whether spreading is enabled, or “ON” and whether the spreading profile controller should generate M values so as to cause the PLL to slew the output frequency in accordance with the spreading profile. If the test of step501determines that spreading is not “ON,” then the method advances to step508. At step508, the method suspends calculating divisor values. From step508, the method returns to step501, essentially waiting for spreading to be enabled. If the test of step501determines that spreading is “ON,” the method advances to step502.

At step502, a test determines whether the value for M is at the lower limit for the value. If the test of step502determines that M is not at the lower limit, the method advances to step503. At step503, the method updates the value for M as (the previous value for M) minus (the slope value). At step503, the updated value for M is provided, for example, to the fractional (feedback) divider of the PLL. At step504, a test determines whether the updated value for M is at the lower limit. If the test of step504determines M is not at the lower limit, the method returns to step503.

If either i) the test of step502or ii) the test of step504determines that M is at the lower limit, the method advances to step505. At step505, an optional step holds the value of M at the lower limit value for either i) a predefined period of time (if the frequency is being spread) or ii) an indeterminate period of time (if the center frequency is being shifted to a new value). From step505, the method advances to step506. At step506the method updates the value for M as (the previous value for M) plus (the slop value). At step506, the updated value for M is provided, for example, to the fractional divider. At step507, a test determines whether the updated value for M is at the upper limit. If the test of step507determines M is not at the upper limit, the method returns to step506. If the test of step507determines M is at the upper limit, the method returns to step501.

The following Verilog pseudo code might be employed to implement a triangular spreading profile control state machine.

While the exemplary embodiment of the present invention is described using a triangular spreading profile, the present invention is not so limited. One skilled in the art may extent the teachings herein to other spreading profiles, such as sinusoidal or similarly periodic signals, that may be modeled with a linear function. In addition, while the exemplary embodiment is described employing a single spreading profile, one skilled in the art may extend the teachings herein to include two or more spreading profiles. Other embodiments of the present invention may allow for switching between the two or more spreading profiles.

While the exemplary embodiment of the present invention is described for a PLL, the present invention is not so limited. One skilled in the art may extent the teachings herein to other types of signal generators, such as clock generators or timing recovery circuits employing, for example, delay-locked loops (DLLs).

The present invention may allow for the following advantages. A given implementation allows for a programmable spreading profile that may be changed on demand for a given application. In addition, the output frequency of a PLL, or similar reference signal generator/timing recovery circuits, may be varied according to a given spreading profile without need for storing the M values for the feedback divider in memory.

While the exemplary embodiments of the present invention have been described with respect to processes of circuits, the present invention is not so limited. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented in the digital domain as processing steps in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller or general purpose computer.