Interface structure of wafer test equipment

A wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board. The probe card includes an interposer on an upper surface thereof, a ceramic multi-layer substrate positioned below the interposer, and a plurality of needles positioned below the ceramic multi-layer substrate on a lower surface thereof opposite the upper surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2008-0111874, filed on Nov. 11, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The inventive concept relates to wafer test equipment used for electrical testing of a wafer, and, more particularly, to an interface structure between a tester head and a probe card that is configured to be directly connected to a wafer under test.

During a manufacturing process, semiconductor devices are functionally tested to determine whether they operate within normal operating parameters or whether they are defective. For example, when a plurality of semiconductor chips are manufactured on a common wafer, it can be determined at that time whether the certain ones of the semiconductor chips are normal or defective through electrical die sort (EDS) testing, prior to dicing of the chips into individual components.

Test equipment used for electrical testing of the wafer is commonly referred to in industry as a “tester”. The tester interfaces with a device under test (DUT) via a tester head, a performance board, and a probe card of a probe station.

A tester head includes a densely arranged plurality of signal terminals connected to a plurality of test channels. The test channels are thereby connected to the DUT to conduct electrical testing of the wafer. A plurality of needles are arranged in a lowermost portion of the probe card so that the probe card can be made to be in electrical contact with the semiconductor chip that is the DUT.

In this manner, the tester and the probe card of the probe station are used to conduct electrical testing of the wafer. Accordingly, the normal or defective status, for example, ‘pass’, ‘repair’, or ‘reject’ status of a plurality of chips on a wafer can be determined.

SUMMARY

An interface structure of wafer test equipment includes a configuration that is constructed and arranged to stably supply power and provide normal signal transfer characteristics during an electrical testing process of a wafer, while significantly reducing the weight and size of the probe card.

In one aspect, a wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board. The probe card includes an interposer on an upper surface thereof, a ceramic multi-layer substrate positioned below the interposer, and a plurality of needles positioned below the ceramic multi-layer substrate on a lower surface thereof opposite the upper surface.

In one embodiment, the performance board and the probe card are electrically connected at a plurality of connection contact points at a lower surface of the universal block printed circuit board at a lower portion of the performance board, and the connection contact points correspond with interposer terminals of the interposer of the probe card on the upper surface of the probe card.

In another embodiment, the universal block printed circuit board has a matrix structure including a plurality of blocks of printed circuit patterns and each block includes the connection contact points that are provided on the lower surfaces of the printed circuit patterns.

In another embodiment, the normal signal lines and the connection contact points are directly connected to each other according to a 1:1 signal transfer ratio, and the power signal lines and the connection contact points are connected to each other according to a 1:N signal transfer ratio, where N is a whole number greater than 1.

In another embodiment, the probe card has a configuration that varies in accordance with the part type of a semiconductor device that is to be tested.

In another embodiment, the performance board and the probe card are removably secured to each other via levers of a ZIF connector at an outer portion of the probe card that surrounds the interposer.

In another embodiment, the probe card further comprises a support surrounding the ceramic multi-layer substrate; and the levers of the ZIF connector are positioned on the support.

In another embodiment, the power signal lines in the cable assembly are soldered directly to an upper surface of the universal printed circuit board of the performance board.

In another embodiment, the power signal lines in the cable assembly are connected to a conductive layer in a middle portion of the universal block printed circuit board.

In another embodiment, the normal signal lines in the cable assembly are soldered directly to an upper surface of the universal printed circuit board of the performance board

In another embodiment, the normal signal lines in the cable assembly are connected to a conductive layer in a middle portion of the universal block printed circuit board,

In another embodiment, the normal signal lines in the cable assembly are connected through the universal block printed circuit board.

In another embodiment, ground lines surround the outer portions of the power signal lines and the normal signal lines in the cable assembly, and are connected to ground conductive layers, respectively, formed on an upper surface and a lower surface of the universal block printed circuit board.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1is a cross-sectional view of an interface structure of wafer test equipment according to an embodiment of the inventive concept.

Referring toFIG. 1, the interface structure of the wafer test equipment in accordance with the present embodiment includes a performance board300constructed and arranged to be connected to a tester head200. A universal block printed circuit board400that directly connects a normal signal line, such as data, address and control signal lines, and directly connects a power signal line that is divided into multiple paths is provided under the performance board300.

The tester head200further includes a cable assembly500that passes through a center portion of the performance board300and is directly soldered to the universal block printed circuit board400in a perpendicular direction. The cable assembly500is not wired from an external location to a center portion via the power signal lines and normal signal lines used for electrical testing of a wafer, but rather, is directly wired from the tester head200to the universal block printed circuit board400along the relatively shortest distance between them as shown by dashed line E ofFIG. 1. Accordingly, a shortest transfer path of the power signal lines and normal signal lines is provided, thereby providing for reliable transmission of the signals during high-speed testing of a semiconductor device.

The interface structure of the wafer test equipment further includes a probe card100that is attachable/detachable to/from the performance board300provided on the universal block printed circuit board400. The probe card100comprises a plurality of interposers130positioned on an uppermost portion of the probe card100, a ceramic multi-layer substrate120positioned below the interposers130, a plurality of needles140positioned below the ceramic multi-layer substrate120, and a support150surrounding the outer portions of the ceramic multi-layer substrate120. The support150is suitably formed of a lightweight metal material, for example, stainless steel or aluminum.

Contemporary probe cards commonly comprise a printed circuit board. However, according to the present embodiment, the universal block printed circuit board400positioned below the performance board300comprises a printed circuit board and the probe card100that is attachable/detachable to/from the performance board200does not include a printed circuit board. As a result, the weight of the probe card100is reduced by about ⅕, and the size of the probe card100is reduced by about ¼, improving manual handling of the probe card100by an operator. In a conventional case where the probe card typically includes a printed circuit board, it is more difficult for the operator to manually handle the relatively large weight and size of the probe card. This increases the burden on an operator's body and operator's health during repeated handling. By reducing the size and weight of the probe card100, manual handling of the probe card100can be performed in a more ergonomic fashion, without requiring the assistance of an additional carrying unit, thereby increasing operational efficiency during a testing process.

In addition, since the universal block printed circuit board400is adaptable to electrically connect and test a variety of types of semiconductor devices, different types of semiconductor devices can be tested by simply changing the configuration of the ceramic multi-layer substrate120included in the probe card100.

Meanwhile, in the interface structure of the wafer test equipment according to the current embodiment of the inventive concept, the performance board300and the probe card100are physically connected to each other via levers110and410of ZIF sockets at the edge, or outer portions, of the probe card100and the universal block printed circuit board400of the performance board300. The performance board400and the probe card100are electrically connected at a plurality of connection contact points430at a bottom portion of the universal block printed circuit board400below the performance board300where they contact a terminal of the interposer130positioned at a top surface of the probe card100. Locking means210and310are provided at the tester head200and the performance board300to secure them to each other. In this manner, the probe card can be removably secured to the performance board300.

FIG. 2is a bottom view of the universal block printed circuit board400ofFIG. 1.

Referring toFIG. 2, the universal block printed circuit board400is configured as a matrix structure including a plurality of blocks of printed circuit patterns420and associated connection contact points430that are used for external connection. The connection contact points430are provided under the printed circuit patterns420. A plurality of levers410of a ZIF connector are positioned on the support150along the boundary portion of the printed circuit patterns420and physically connect and retain the universal block printed circuit board400and the probe card100ofFIG. 1. Although the universal block printed circuit board400in the present example embodiment includes an array of nine printed circuit patterns420for descriptive convenience and understanding, the number of the printed circuit patterns420may vary, and the printed circuit patterns420can also have various modifications of arrangement, other than a matrix type of arrangement, as needed.

FIG. 3is a cross-sectional view illustrating a path for connecting a plurality of normal signal lines510and a plurality of power signal lines520of a tester head to a semiconductor chip.FIG. 4is an extended cross-sectional view of a portion D ofFIG. 3for explaining a multi paths structure of the power signal lines520.

Referring toFIGS. 3 and 4, the cable assembly500that is directly soldered to the universal block printed circuit board400from the tester head200includes a plurality of power signal lines520and a plurality of normal signal lines510. As illustrated inFIG. 4, the normal signal lines510are not divided into multiple paths in the printed circuit patterns420included in the universal block printed circuit board400but rather are directly connected to a plurality of connection contact points432by a ratio of 1:1. Meanwhile, the power signal lines520are divided into multiple paths in a conductive layer422of the printed circuit patterns420included in the universal block printed circuit board400and are connected to a plurality of connection contact points434by a ratio of 1:N. InFIG. 4, the number N of the connection contact points434for each power signal line is 5, however the number N can be adjusted according to the needs of a designer, for example, where N is less than or equal to 10.

In a case where the power signal lines520are divided into multiple paths and are arranged in a direction parallel to the interposers130, the power signal lines520have a relatively small inductance as compared to the normal signal lines510that are not divided into multiple paths and are connected in serial to the connection contact points432. Accordingly, the smaller the inductance, the smaller the resulting impedance, and thus the power signals can be stably transmitted on the power signal lines520. Further, the interface structure of the wafer test equipment according to the current embodiment of the inventive concept is connected to the universal block printed circuit board400while the power signal lines520and the normal signal lines510respectively maintain the shortest distance relative to the tester head200in a perpendicular direction. Accordingly, when a DUT is a product that operates at high speed, test signals can be more reliably transmitted.

FIG. 5is a perspective view illustrating the cable assembly500and the universal block printed circuit board400that are connected to each other, in accordance with an embodiment of the present inventive concept.

Referring toFIG. 5, the power signal lines520directly connected from the tester head200to the universal block printed circuit board400are divided into multiple paths in the printed circuit patterns420of the universal block printed circuit board400and thus the connection contact points434are formed. Meanwhile, the normal signal lines510are directly connected to the connection contact points432of the universal block printed circuit board400by a ratio of 1:1.

FIGS. 6 through 8are cross-sectional views illustrating various structures in which a normal signal line510of the cable assembly500is soldered in the universal block printed circuit board400according to an embodiment of the inventive concept.

Referring toFIGS. 6 and 8, signal lines512,512A, and512B included in the normal signal line510are surrounded by ground lines514. The ground lines514are connected to ground conductive layers424and426, respectively, positioned on an upper surface and a lower surface of the printed circuit patterns420included in the universal block printed circuit board400. The printed circuit patterns420included in the universal block printed circuit board400may further include a ground conductive layer428that connects the ground conductive layer424formed on the upper surface and the conductive layer426formed on the lower surface.

Meanwhile, the connection between the normal signal lines512,512A, and512B and the printed circuit patterns420included in the universal block printed circuit board400may be such that the normal signal line512is soldered on an upper surface of the printed circuit patterns420as illustrated in B1ofFIG. 6, or that the normal signal line512A is soldered in a middle portion of the printed circuit patterns420as illustrated in B2ofFIG. 7, or that the normal signal line512B is connected to the connection contact point432through the printed circuit patterns420as illustrated in B3ofFIG. 8. Accordingly, the normal signal lines512,512A, and512B are directly through-connected to the connection contact points432of the printed circuit patterns420included in the universal block printed circuit board400, and are then connected to a DUT through the interposers130included in the probe card100.

FIGS. 9 and 10are cross-sectional views illustrating a structure in which the power signal lines520of the cable assembly500are soldered in the universal block printed circuit board400according to an embodiment of the inventive concept.

Referring toFIGS. 9 and 10, like the normal signal lines510, signal lines522and522A included in the power signal lines520of the cable assembly500are surrounded by ground lines524. The ground lines524are connected to upper and lower ground conductive layers424and426, respectively, formed in the printed circuit patterns420included in the universal block printed circuit board400. Accordingly, the power signal lines520obtain a wide ground area during a connection process, thereby preventing deterioration of the power signal transmission characteristics due to noise. A connection ground line428is formed in the printed circuit patterns420of the universal block printed circuit board400.

Meanwhile, the power signal lines522and522A may be electrically connected to the upper surface of the printed circuit patterns420of the universal block printed circuit board400and be divided into three paths in a ground middle conductive layer422formed in the printed circuit patterns420as shown in C1ofFIG. 9. Also, the power signal lines522and522A may be connected to the ground middle conductive layer422in the printed circuit patterns420and be divided into three paths as shown in C2ofFIG. 10. Accordingly, the power signal lines522and522A are divided into multiple paths and are connected to connection contact points434of the printed circuit patterns420in the universal block printed circuit board400, and then to a DUT through the interposers130. The power signal lines522and522athat are arranged parallel in the interface structure of the wafer test equipment according to the current embodiment of the inventive concept significantly reduce impedance of the interface structure of the wafer test equipment, thereby improving the signal transmission characteristics.

According to the inventive concept, first, the size and weight of the probe card that requires manual handling is reduced. This is achieved, in part, by including the relatively heavy printed circuit board as a universal printed circuit board block that forms part of the test head. Accordingly, the weight of the probe card can be reduced, such as reduced by ⅕, and the size thereof can be reduced, such as reduced by ¼, during an actual testing process, so that the probe card is more suited for manual handling by an operator in ergonomic fashion.

Second, a tester divides power signal lines transmitted to semiconductor chips of a wafer that is a DUT into multiple paths in the universal block printed circuit board and increases the number of contact points, thereby reducing power impedance and achieving a more stable power transmission during an electrical test process of the wafer.

Third, a path for connecting the power signal lines and the normal signal lines to the DUT via the printed circuit board of the probe card is designed as the shortest distance from the tester head to the universal block printed circuit board in a perpendicular direction, thereby achieving more stable signal transmission characteristics and increasing reliability of high-speed electrical testing of a semiconductor device.