Memory device with redundant IO circuit

A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal.

BACKGROUND

Generally, semiconductor devices include memory devices. In the manufacture of memory devices, defects frequently exist. Such defects typically affect a number of memory elements in the memory devices. To prevent rejection of an entire chip due to the presence of the defective memory elements, semiconductor memory devices typically have some components for substituting or repairing the defective memory elements, in order to increase manufacturing process yield.

DETAILED DESCRIPTION

In the following description, specific details are presented to provide a thorough understanding of the embodiments of the present disclosure. Persons of ordinary skill in the art will recognize, however, that the present disclosure can be practiced without one or more of the specific details, or in combination with other components. Well-known implementations or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the present disclosure.

Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1is a schematic diagram illustrating a memory device100according to some embodiments of the present disclosure. In some embodiments, the memory device100includes a memory array120, a plurality of input/output (IO) circuits GIO0-GION−1, a redundant IO circuit REDGIO and a redundant IO control unit160. For illustration, the redundant IO circuit REDIO shown inFIG. 1is disposed next to the IO circuit GION−1. The redundant IO circuit REDIO is configured to replace any failed IO circuit among the IO circuits GIO0-GION−1.

The number and/or the location of the redundant IO circuit REDIO are given for illustrative purposes. Various numbers and/or locations of the redundant IO circuit REDIO are within the contemplated scope of the present disclosure. For example, in various embodiments, an additional redundant IO circuit (not shown) is further disposed between the IO circuit GIOKand the IO circuit GIOK+1. For illustration, the additional redundant IO circuit is configured to replace any failed IO circuit among the IO circuits GIO0-GIOK, and the redundant IO circuit REDIO is configured to replace any failed IO circuit among the IO circuits GIOK+1-GION−1. For another example, in some alternative embodiments, more than two redundant IO circuits are implemented in series with the IO circuits GIO0-GION−1.

In some embodiments, the memory array120includes a plurality of memory cell units, which, for convenience of illustration, are not shown in figures. The memory cell units are arranged, for illustration, in memory columns and memory rows. Accordingly, each of memory cell units is able to be accessed based on row address and column address.

In some embodiments, the IO circuits GIO0-GION−1are associated with different memory columns and correspond to different column addresses. Explained in a different way, each of the IO circuits GIO0-GION−1is associated with one of the memory columns and corresponds to a column address. For illustration, there are total N columns of the IO circuits GIO0-GION−1, and N is a positive integer. The IO circuit GIO0corresponds to a first memory column of the memory array120and the column address corresponding to the IO circuit GIO0is “0000000”. The IO circuit GIO1corresponds to a second memory column of the memory array120and the column address corresponding to the IO circuits GIO1is “0000001.” The IO circuit GIO2corresponds to a third memory column of the memory array120and the column address corresponding to the IO circuit GIO2is “0000010”. The rest is deduced by analogy, and thus they are not further detailed herein.

The redundant IO circuit REDGIO is associated with a redundant memory column (not shown) in the memory array120. If one of the IO circuits GIO0-GION−1is failed, for example, when the IO circuit is disconnected from its memory column, or when the memory column connected to the IO circuit is not accessible, the redundant IO circuit REDGIO is configured to substitute or replace the failed IO circuit, as will be detailed below with reference toFIG. 2. After the failed IO circuit is replaced, the memory column originally connected with the failed IO circuit is accessible again. Accordingly, the function of the failed IO circuit is taken over by, for example, a next IO circuit, and a yield rate of the memory device100increases, compared to that of the memory device100without replacing the failed IO circuit. Alternatively stated, the memory device100is configured with column redundancy, for the failed IO circuit.

For illustration, there are total one hundred of IO circuits GIO0-GIO99, i.e., N=100. The column address corresponding to the IO circuit GIO99is, for example, “1100011.” The column address of the redundant IO circuit REDGIO would be set to be, for example, “1100100,” which is different from all column addresses of the IO circuits GIO0-GIO99.

In some embodiments, the column address of the failed IO circuit is recorded as a failure column address. In further embodiments, the failure column address is detected and/or identified during a testing procedure, or a packaging procedure, after the memory device100is manufactured. In some other embodiments, the failure column address is dynamically detected and/or identified by a monitoring system while the memory device100is operating.

The redundant IO circuit REDGIO is configured to be controlled by the redundant IO control unit160. In some embodiments, the redundant IO control unit160receives a shutdown signal SD and a failure column address signal FADIO, and based on which, controls the redundant IO circuit REDGIO accordingly. For illustration, when the shutdown signal SD is set at a low level, a shutdown mode of the memory device100is deactivated. In contrast, when the shutdown signal SD is set at a high level, the shutdown mode of the memory device100is activated. The failure column address signal FADIO indicates a failure column address of the IO circuits GIO0-GION−1.

For convenience of illustration hereinafter, logic “0” indicates a low level, and logic “1” indicates a high level. The indications are given for illustrative purposes. Various indications are within the contemplated scope of the present disclosure.

In some embodiments, the failure column address signal FADIO and the shutdown signal SD are provided by an external source200, including, for example, a memory driver (not shown) or a system processor (not shown) that is capable of accessing the memory device100. According to the failure column address of a failed IO circuit of the IO circuits GIO0-GION−1, which is indicated by the failure column address signal FADIO, the redundant IO control unit160configures the redundant IO circuit REDGIO to substitute the failed IO circuit.

In some embodiments, the memory device100further includes a memory array controller122, a global IO controller140and an address programming module180. For illustration, the memory array controller122is configured to control and/or manage operations of the memory array120. In some embodiments, the operations of the memory array120include, for example, a writing procedure, a reading procedure, an over-writing procedure and/or a data-erasing procedure of the memory cells. In some embodiments, the global IO controller140is configured to control and/or manage operations of the IO circuits GIO0-GION−1.

In some embodiment, the address programming module180is coupled to the IO circuits GIO0-GION−1, the redundant IO circuit REDGIO and the redundant IO control unit160. In some embodiments, the redundant IO control unit160configures the redundant IO circuit REDGIO by adjusting a connection configuration of the address programming module180. Details of adjusting the connection configuration of the address programming module180are discussed below with reference toFIG. 2.

In some embodiments, the memory device100has a shutdown mode. During the shutdown mode, some components and functions of the memory device100are turned off or suspended, to reduce leakage current and power consumption of the memory device100. In some embodiments, the array controller122and the global IO controller140are able to be temporarily turned off during the shutdown mode.

Reference is made toFIG. 2.FIG. 2is a schematic diagram illustrating the IO circuits GIO0-GION−1, the redundant IO circuit REDGIO, the redundant IO control unit160and the address programming module180of the memory device100inFIG. 1according to some embodiments of the present disclosure. For convenience of illustration, the IO circuits GIO0-GIO2are given inFIG. 2for illustration, and the IO circuits GIO3-GION−1are not shown inFIG. 2. Configurations and operations associated with the IO circuits GIO3-GION−1are similar to, or correspond to, those associated with the IO circuits GIO0-GIO2, as will be discussed below, and thus they are not further detailed.

In some embodiments, the redundant IO control unit160includes a latch circuit162and a decoding circuit164. For illustration, the latch circuit162receives the failure column address signal FADIO and the shutdown signal SD. When the shutdown signal SD is set to logic “0” indicating the shutdown mode being deactivated, the failure column address signal FADIO is received by the latch circuit162, and the latch circuit162passes the failure column address signal FADIO to the decoding circuit164. The decoding circuit164is configured to set up voltage levels of control address lines F0-F6and reversed control address lines FB0-FB6according to the failure column address signal FADIO from the latch circuit162.

In some embodiments, the control address lines F0-F6and the reversed control address lines FB0-FB6have respective logics that are associated with the failure column address signal FADIO. For illustration, the failure column address signal FADIO is represented by “0000001.” Accordingly, the control address lines F1-F6are set at logic “0,” and the control address line F0is set at logic “1.” The reversed control address lines FB0-FB6are set at logics that are opposite to those of the control address lines F0-F6. Accordingly, the reversed control address lines FB1-FB6are set at logic “1,” and the reversed control address line FB0is set at logic “0.”

In some embodiments, during the shutdown mode, the external source200stops providing the failure column address signal FADIO to the redundant IO control unit160. Alternatively stated, during the shutdown mode, the redundant IO control unit160does not receive the failure column address signal FADIO from the external source200. The latch circuit162is configured to latch and keep the previously received failure column address signal FADIO during the shutdown mode. According to the latched failure column address signal FADIO, the decoding circuit164sets up voltage levels of the control address lines F0-F6and the reversed control address lines FB0-FB6. In some other embodiments, the redundant IO control unit160includes other storage circuit, which replaces the latch circuit162, for storing the failure column address signal FADIO.

The configuration of the redundant IO control unit160illustrated above is given for illustrative purposes. Various circuits and/or units to implement the redundant IO control unit160are within the contemplated scope of the present disclosure.

The number of the control address lines F0-F6, the reversed control address lines FB0-FB6, and digits (e.g., “0000001”) representing the column addresses discussed above inFIG. 2are given for illustrative purposes. Various numbers of control address lines, reversed control address lines and digits representing the column addresses are within the contemplated scope of the present disclosure.

When the shutdown signal SD is at logic “1” indicating the shutdown mode being activated, the latch circuit162is triggered to latch the previously received failure column address signal FADIO. In some embodiments, during the shutdown mode of the memory device100, the external source200, including, for example, the memory driver (not shown) or the system processor (not shown), will stop providing the failure column address signal FADIO to the redundant IO control unit160. With the latch circuit162as discussed above, the failure column address signal FADIO is able to be kept in the redundant IO control unit160when the failure column address signal FADIO is not provided to the redundant IO control unit160.

In some embodiments, the failure column address signal FADIO latched in the latch circuit162is provided to the decoding circuit164. According to the latched failure column address signal FADIO, the decoding circuit164is able to set up voltage levels of the control address lines F1-F6and the reversed control address lines FB0-FB6. As a result, the voltage levels of the control address lines F1-F6and the reversed control address lines FB0-FB6will not be lost or floated during the shutdown mode. Alternatively stated, the voltage levels of the control address lines F0-F6and the reversed control address lines FB0-FB6are maintained by the redundant IO control unit160during the shutdown mode.

In some embodiments, the address programming module180as illustrated inFIG. 2includes address programming units VP0-VPR. For convenience of illustration, the address programming units corresponding to the IO circuits GIO3-GION−1are not shown inFIG. 2, and the address programming units VP0-VP2shown inFIG. 2are given for illustration.

For illustration inFIG. 2, the address programming units VP0-VP2are coupled to the IO circuits GIO0-GIO2and the redundant IO control unit160. Each one of the IO circuits GIO0-GIO2is coupled to IO address lines A0-A6. According to the respective column addresses of the IO circuits GIO0-GIO2, each one of the address programming units VP0-VP2connects the corresponding IO address lines A0-A6with the corresponding control address lines, which are selected from the control address lines F0-F6and the reversed control address lines FB0-FB6. For example inFIG. 2, the address programming unit VP0connects the corresponding IO address lines A0-A6to the reversed control address lines FB0, FB1, FB2, FB3, FB4, FB5and FB6. The address programming unit VP1connects the corresponding IO address lines A0-A6to the control address line F0and the reversed control address lines FB1, FB2, FB3, FB4, FB5and FB6.

For illustration of the IO circuit GIO0, when the column address is “0000000,” the IO address lines A0-A6are connected to the reversed control address lines FB0-FB6. For illustration of the IO circuit GIO1, when the column address is “0000001,” the IO address line A0is connected to the control address line F0, and the IO address lines A1-A6are connected to the reversed control address lines FB1-FB6. For illustration of the IO circuit GIO2, when the column address is “0000010,” the IO address line A1is connected to the control address line F1, and the IO address lines A0and A2-A6are connected to the reversed control address lines FB0and FB2-FB6.

The address programming unit VPR is coupled to the redundant IO circuit REDGIO and the redundant IO control unit160. The redundant IO circuit REDGIO is coupled to IO address lines A0-A6. According to the column address of the redundant IO circuit REDGIO, the address programming unit VPR connects the IO address lines A0-A6that are associated with the redundant IO circuit REDGIO, with the corresponding control address lines, which are selected from the control address lines F0-F6and the reversed control address lines FB0-FB6. For example with reference toFIG. 2, when the column address is “1100100,” the address programming unit VPR connects the IO address lines A0, A1, A3, A4to the reversed control address lines FB0, FB1, FB3, FB4, and connects the IO address lines A2, A5, A6to the control address lines F2, F5, F6.

In some embodiments, each one of the IO circuits GIO0-GIO2and the redundant IO circuit REDGIO includes a shifter. For illustration, the IO circuit GIO0includes a shifter SF0, the IO circuit GIO1includes a shifter SF1, the IO circuit GIO2includes a shifter SF2, and the redundant IO circuit REDGIO includes a shifter SFR. The shifters SF0-SF2are coupled in series, in some embodiments, according to an order of the column addresses of the IO circuits GIO0-GIO2. The shifter SFR is coupled in series to the shifter in the previous IO circuit, for example, the IO circuit GION−1(not shown).

For illustration inFIG. 2, each one of the shifters SF0-SF2and SFR has a shift input Sin and a shift output Sout. The shift output Sout of the shifter SF0is coupled to the shift input Sin of the shifter SF1. The shift output Sout of the shifter SF1is coupled to the shift input Sin of the shifter SF2. The rest is deduced by analogy, and thus they are not further detailed herein.

In some embodiments, the shifters SF0-SF2are configured to determine whether at least one of the IO circuits GIO0-GIO2corresponds to the failure column address signal FADIO. In various embodiments, the shifters SF0-SF2are configured to detect the voltage levels of the IO address lines A0-A6associated therewith. Based on the detection result, whether at least one the IO circuits GIO0-GIO2correspond to the failure column address signal FADIO is determined. For illustration, when all voltage levels of the IO address lines A0-A6are at a high level detected by the shifter SF0, the shifter SF0is then determined to correspond to the failure column address signal FADIO. This indicates that the IO circuit GIO0is failed.

As discussed above, the failure column address signal FADIO indicates the failure column address. According to the failure column address, a corresponding shifter of the shifters SF0-SF2and SFR is configured to generate a hit signal at the shift output Sout.

For illustration, when the failure column address is “0000010,” the shifter SF2corresponds to the failure column address, which indicates that the IO circuit GIO2is failed. Accordingly, the shifter SF2generates a hit signal, while the shifters SF0and SF1do not generate any hit signal. The shifter SF2then passes the hit signal through the shift output Sout to an immediate next shift input Sin. Alternatively stated, the hit signal is then shifted through subsequent shifters, for example, of the IO circuits GIO3-GION−1following the failed IO circuit GIO2. In some embodiments, the hit signal is shifted until the hit signal reaches the shifter SFR of the redundant IO circuit REDGIO. The hit signal, generated at the shifter SF2, is shifted through the shifters of the IO circuits GIO3-GION−1one by one to the shifter SFR. Accordingly, the shifters, subsequent to the shifter SF2, also generate the hit signal.

In one exemplary operation, if an access request is received to read/write at the failure column address “0000010,” a next column at the column address “0000011” responds to the access request. In another exemplary operation, if another access request is received to read/write at the failure column address “0000011,” a next column at the column address “0000100” responds to the access request.

Based on the above discussion, the failed IO circuit is skipped, while the IO circuit immediate next to the failed IO circuit is configured to operate for substituting the failed IO circuit. Consequently, the redundant IO circuit REDGIO is configured to operate as a backup for substituting the last presented IO circuit, for example, the IO circuit GION−1.

As discussed above, the voltage levels of the control address lines F0-F6and the reversed control address lines FB0-FB6are maintained by the redundant IO control unit160during the shutdown mode. In some embodiments, the shifters SF0-SF2and SFR remain activated during the shutdown mode. Accordingly, the shifter chain including the shifters SF0-SF2and SFR is able to keep the hit signal during the shutdown mode. When the memory device100is resumed from the shutdown mode, the shifter chain does not require additional time to re-generate the hit signal. As a result, when the memory device100is resumed from the shutdown mode, the IO circuits including the IO circuits GIO0-GIO2and the redundant IO circuit REDGIO are ready to perform a data accessing with column redundancy.

Reference is made toFIG. 3.FIG. 3is a schematic diagram illustrating a circuitry configuration of the redundant IO control unit160inFIG. 2, according to some embodiments of the disclosure.

For illustration inFIG. 3, the latch circuit162latches the failure column address signal FADIO during the shutdown mode. In some embodiments, the shutdown signal SD is set at logic “1” during the shutdown mode. In response to the shutdown signal SD of logic “1,” the latch circuit162is triggered to latch the failure column address signal FADIO. When the shutdown signal SD transits to logic “0,” the latch circuit162passes the failure column address signal FADIO to the decoding circuit164in response to the shutdown signal SD of logic “0.”

In some embodiments, the failure column address signal FADIO is converted into an address word F[6:0] and a reversed address word FB[6:0] as illustrated inFIG. 3. Based on the address word F[6:0] and the reversed address word FB[6:0], the decoding circuit164sets up the voltage levels of control address lines F0-F6and reversed control address lines FB0-FB6.

In some embodiments, the latch circuit162includes a tri-state inverting buffer BF1, an inverter INV1and a tri-state inverting buffer BF2.

For illustration, the tri-state inverting buffer BF1has an input end, an output end and a control end. The input end of the tri-state inverting buffer BF1is configured to receive the failure column address signal FADIO. The control end of the tri-state inverting buffer BF1is configured to receive a reversed shutdown signal SDB. In some embodiments, the redundant IO control unit160further includes an inverter INV0. The inverter INV0is configured to invert the shutdown signal SD to generate the reversed shutdown signal SDB.

For illustration, the inverter INV1has an input end and an output end. The input end of the inverter INV1is coupled to the output end of the tri-state inverting buffer BF1.

In some embodiments, the tri-state inverting buffer BF2has an input end, an output end and a control end. The input end of the tri-state inverting buffer BF2is coupled to the output end of the inverter INV1. The output end of the tri-state inverting buffer BF2is coupled to the input end of the inverter INV1. The control end of the tri-state inverting buffer BF2is configured to receive the shutdown signal SD.

For illustration, when the shutdown mode of the memory device100is deactivated, the shutdown signal SD is set at logic “0” and the reversed shutdown signal SDB is set at logic “1.” The tri-state inverting buffer BF1is enabled by the reversed shutdown signal SDB. The tri-state inverting buffer BF2is disabled by the shutdown signal SD. With the enabled tri-state inverting buffer BF1, the failure column address signal FADIO passes through the first tri-state inverting buffer BF1and the inverter INV1. The address word F[6:0] corresponding to the failure column address signal FADIO is generated accordingly.

When the shutdown mode of the memory device100is activated, the shutdown signal SD is set to logic “1” and the reversed shutdown signal SDB is set to logic “0.” The tri-state inverting buffer BF1is disabled by the reversed shutdown signal SDB. The tri-state inverting buffer BF2is enabled by the shutdown signal SD. Accordingly, the failure column address signal FADIO is latched by the tri-state inverting buffer BF2and the inverter INV1. As a result, the failure column address signal FADIO is maintained in the latch circuit162during the shutdown mode of the memory device100.

In some embodiments, the redundant IO control unit160further includes an inverter INV2. The inverter INV2has an input that is coupled to the output of the inverter INV1, and an output that is coupled to the decoding circuit164. The inverter INV2is configured to invert the address word F[6:0] to generate the reversed address word FB[6:0].

The circuitry configuration of the redundant IO control unit160inFIG. 3is given for illustrative purposes. Various configurations of the redundant IO control unit160are within the contemplated scope of the present disclosure. For example, in various embodiments, the redundant IO control unit160includes logical components to latch the failure column address signal FADIO in response to the shutdown signal SD of logic “0,” which is opposite to what is discussed above.

Reference is made toFIG. 4.FIG. 4is a schematic diagram illustrating a circuitry configuration of one of the shifters inFIG. 2, according to some embodiments of the present disclosure. In some embodiments, the circuitry configuration inFIG. 4is applied in each one of the shifters as illustrated inFIG. 2.

In some embodiments, the shifter includes NAND gates NAND1, NAND2, NAND3, NAND4and NAND5, a NOR gate NOR1and an inverter INV3. For illustration, the NAND gate NAND1is coupled to the IO address lines A0-A2, the NAND gate NAND2is coupled to the IO address lines A3-A4, and the NAND gate NAND3is coupled to the IO address lines A5-A6. Inputs of the NOR gate NOR1are coupled to the outputs of the NAND gates NAND1, NAND2, NAND3. Inputs of the NAND gate NAND4are coupled to the output of the NOR gate NOR1and an enabling signal FEN which, in some embodiments, is generated by the redundant IO control unit160. The input of the inverter INV3is coupled to the shift input Sin. Inputs of the NAND gate NAND5are coupled to the outputs of the NAND gate NAND4and the inverter INV3. The output of the NAND gate NAND5is coupled to the shift output Sout.

Based on the configurations as discussed above, the shift output Sout is set at logic “1” when the shift input Sin is set at logic “1.” Moreover, the shift output Sout is also set at logic “1” when all of the IO address lines A0-A6and the enabling signal FEN are set at logic “1.” For illustration, when all of the IO address lines A0-A6and the enabling signal FEN being set at logic “1,” the present shifter corresponds to the failure column address signal FADIO, and the present shifter is able to generate the hit signal at the shift output Sout, as discussed above.

For another illustration, when the shift input Sin is set at logic “1,” the immediate previous shifter corresponds to the failure column address signal FADIO. The present shifter is able to pass the hit signal to the immediate next shifter by setting the shift output Sout at logic “1.”

The circuitry configuration of the shifter inFIG. 4is given for illustrative purposes. Various configurations of the shifter are within the contemplated scope of the present disclosure.

FIG. 5is a flowchart of a method500illustrating operations of the memory device100inFIG. 1, according to some embodiments of the present disclosure. The method500is given for illustration with reference toFIG. 1andFIG. 2. Various memory devices in which the method500is able to be applied are within the contemplated scope of the present disclosure.

In operation S502, the shutdown signal SD and the failure column address signal FADIO are provided, for example, to the redundant IO control unit160. The failure column address signal FADIO corresponds to a failed IO circuit of the IO circuits GIO0-GION−1. The failed IO circuit corresponds to one of the memory columns in the memory array120.

In operation S504, a hit signal is generated by the shifter of the failed IO circuit corresponding to the failure column address signal FADIO.

In operation S506, the hit signal is shifted through subsequent shifters following the shifter of the failed IO circuit, to the shifter SFR of the redundant IO circuit REDGIO.

In operation S508, according to the failure column address signal FADIO, an IO circuit substitutes the failed IO circuit for accessing data of the memory column. In some embodiments, the IO circuit is immediate next to the failed IO circuit of the IO circuits GIO1-GION−1. For illustration, a first immediate next IO circuit substitutes the failed IO circuit, and responds to an access request to the failed IO circuit. A second immediate next IO circuit substitutes the first immediate next IO circuit, and responds to an access request to the first immediate next IO circuit, and so on. The redundant IO circuit REDGIO substitutes the last IO circuit, for example, GION−1, and responds to an access request to the last IO circuit. Effectively, the redundant IO circuit REDGIO is configured to substitute the failed IO circuit.

In some embodiments, when the shutdown mode of the memory device100is activated, operation S510is performed. In operation S510, the failure column address signal FADIO is latched, for example, by the latch circuit162, according to the shutdown signal SD. In some other embodiments, the failure column address signal FADIO is stored by a storage circuit, for example, a register, a memory and/or a flash memory.

In operation S512, the shifters SF0-SFR of the IO circuits GIO0-GION−1and the redundant IO circuit REDGIO are kept activated. Accordingly, the shifter chain including the shifters SF0-SFR is able to keep the hit signal during the shutdown mode. As a result, in some embodiments, when the memory device100is resumed from the shutdown mode, the method500is not required to repeat operation S504and/or S506for re-establishing the hit signal in the shifter chain.

In some embodiments, when the shutdown mode of the memory device100is deactivated, operation S514is performed. In operation S514, it is determined whether a new failure column address signal FADIO which is different from the previously latched failure column address signal FADIO is received, for example, by the redundant IO control unit160.

If a new failure column address signal FADIO is received by the redundant IO control unit160, operation S504is performed again, in which a hit signal corresponding to the new failure column address signal FADIO is generated accordingly. The operations subsequent to operation S504are performed again accordingly.

If no new failure column address is received, operation S508is performed again, in which the same IO circuit still substitutes the failed IO circuit. With the failure column address signal FADIO being latched by the latch circuit162and the shifters SF0-SFR are kept activated during the shutdown mode, the shifters SF0-SFR are able to keep the hit signal during the shutdown mode being activated. When the memory device100is resumed from the activated shutdown mode, the shifters SF0-SFR do not require additional time to re-generate the hit signal, and as a result, the IO circuits GIO0-GION−1and the redundant IO circuit REDGIO are ready to perform data accessing.

In some embodiments, a device is disclosed that includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to storage the failure column address signal.

Also disclosed is method that includes the operations below. A failure column address signal is provided to a redundant IO control unit of a memory device. The failure column address signal corresponds to a failed IO circuit of the memory device. A shutdown signal for activating or deactivating a shutdown mode of the memory device is provided. During the activated shutdown mode, the failure column address signal is stored by a storage circuit of the redundant IO control unit in response to the shutdown signal.

A circuit including a redundant IO control unit is also disclosed. The redundant IO control unit is configured to control a redundant IO circuit in a memory device. In response to a failure column address signal, the redundant IO control unit is configured to substitute a failed IO circuit of a plurality of IO circuits in the memory device. The redundant IO control unit includes a storage circuit configured to store the failure column address signal during a shutdown mode.