SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHODS THEREOF

A semiconductor structure includes a substrate and an interconnect. The substrate has a semiconductor device. The interconnect is disposed over the substrate and electrically coupled to the semiconductor device, and includes a metallization layer and a capping layer. The metallization layer is disposed over the substrate and includes a via portion and a line portion connecting to the via portion. The capping layer covers the line portion, where the line portion is sandwiched between the via portion and the capping layer, and the capping layer includes a plurality of sub-layers.

BACKGROUND

Developments in shrinking sizes of semiconductor devices and electronic components such as integrated circuits (ICs) make the integration of more devices and components into a given volume possible and lead to high integration density of various semiconductor devices and/or electronic components. Semiconductor processing for fabrications of the semiconductor devices and ICs continues to evolve towards increasing device-density, higher numbers of active devices (mainly transistors) of ever decreasing device dimensions. The resistance performance of the interconnect and/or redistribution layer has become particularly challenging because of the abovenamed increase in the device density.

DETAILED DESCRIPTION

In addition, terms, such as “first”, “second” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

It should be appreciated that the following embodiment(s) of the disclosure provides applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiment(s) discussed herein is merely illustrative and is related to a semiconductor structure including an interconnect with a capping layer disposed over a metallization pattern thereof for suppressing surface scattering effect, and is not intended to limit the scope of the disclosure. In accordance with some embodiments, a capping layer is disposed on a surface of a metallization pattern inside an interconnect of the semiconductor structure, where the capping layer is able to suppress the surface scattering effect of the metallization pattern (e.g. made of Cu) so to reduce the resistivity of the Cu metallization pattern, thereby improving the performance of the semiconductor structure. In the case, the capping layer is a two-dimensional material of a layered structure. In accordance with some alternative embodiments, an additional capping layer is disposed on a sidewall of the Cu metallization pattern to suppress the surface scattering effect, thereby further reducing the resistivity of the Cu metallization pattern and improving the electric performance. In addition, with such additional capping layer, a barrier layer and/or a liner disposed between the Cu metallization pattern and a dielectric structure/layer inside the interconnect can be omitted, thus that an overall volume of the Cu metallization pattern is increased, which also further reduced the resistivity of the Cu metallization pattern.

The semiconductor structure illustrated in the following embodiments may be applied to a semiconductor die or chip (such as a system-on-a-chip (SoC), a system-on-integrated-chip (SoIC), or the like) for illustrative purposes only, and is not intended to limit the scope of the disclosure.FIG.1,FIG.2,FIG.3,FIG.4,FIG.5,FIG.6,FIG.7,FIG.8,FIG.9,FIG.11, andFIG.12are schematic cross-sectional views showing a method of manufacturing a semiconductor structure in accordance with some embodiments of the disclosure.

Referring toFIG.1, in some embodiments, a method of forming a semiconductor structure1000(as shown inFIG.12) includes following steps. First, an initial structure illustrated inFIG.1is provided. The initial structure includes a substrate200and a stack structure disposed on the substrate200, and a patterned resist layer108disposed on the stack structure, for example. As shown inFIG.1, the stack structure may be sandwiched between the patterned resist layer108and the substrate200.

In some embodiments, as shown inFIG.1, the substrate200includes a wide variety of devices (also referred to as semiconductor devices) formed in a semiconductor substrate202. The devices may include active components, passive components, or a combination thereof. The devices may include integrated circuits devices. The devices may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. The functions of the devices may include memory, processors, sensors, amplifiers, power distribution, input/output circuitry, or the like.

For example, the semiconductor substrate202includes a bulk semiconductor, a crystalline silicon substrate, a doped semiconductor substrate (e.g., p-type semiconductor substrate or n-type semiconductor substrate), a semiconductor-on-insulator (SOI) substrate, or the like. In certain embodiments, the semiconductor substrate202includes one or more doped regions or various types of doped regions, depending on design requirements. In some embodiments, the doped regions are doped with p-type and/or n-type dopants. For example, the p-type dopants are boron or BF2and the n-type dopants are phosphorus or arsenic. The doped regions may be configured for an n-type metal-oxide-semiconductor (NMOS) transistor or a p-type MOS (PMOS) transistor. The substrate200may be a wafer, such as a silicon wafer. Generally, the SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. Other substrates, such as a multi-layered or gradient substrate may also be used. In some alternative embodiments, the semiconductor substrate202includes a semiconductor substrate made of other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, gallium phosphide, indium phosphide, indium arsenide and indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP and GaInAsP or combinations thereof.

As shown inFIG.1, the devices such as a PMOS transistor30and a NMOS transistor40may be formed in the semiconductor substrate202. In some embodiments, more than one isolation structures204are formed in the semiconductor substrate202for separating the PMOS transistor30and the NMOS transistor40. In certain embodiments, the isolation structures204are trench isolation structures. In other embodiments, the isolation structures204includes local oxidation of silicon (LOCOS) structures. In some embodiments, the insulator material of the isolation structures204includes silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. For example, the low-k dielectric material generally having a dielectric constant lower than 3.9. In one embodiment, the insulator material may be formed by chemical vapor deposition (CVD) such as high-density plasma CVD (HDP-CVD) and sub-atmospheric CVD (SACVD) or formed by spin-on. In certain embodiments, the devices (such as the PMOS transistor30and the NMOS transistor40) and the isolation structures204are formed in the substrate200during the front-end-of-line (FEOL) processes. In one embodiment, the PMOS transistor30and the NMOS transistor40are formed following the complementary MOS (CMOS) processes. The number and configurations of the devices formed in the semiconductor substrate202should not be limited by the embodiments or drawings of this disclosure. It is understood that the number and configurations of the devices may have different material or configurations depending on product designs.

In some embodiments, the PMOS transistor30includes a gate structure310and source/drain regions320located at two opposite sides of the gate structure310, where the gate structure310is formed on an n-well region330, and the source/drain regions320are formed in the n-well region330. In one embodiment, the gate structure310includes a gate electrode312, a gate dielectric layer314and a gate spacer316. The gate dielectric layer314may spread between the gate electrode312and the semiconductor substrate202, and may or may not further cover a sidewall of the gate electrode312. The gate spacer316may laterally surround the gate electrode312and the gate dielectric layer314. In one embodiment, the source/drain regions320include doped regions of p-type dopant that are formed in the n-well region330by ion implantation. In an alternative embodiment, the source/drain regions320include epitaxial structures formed in and protruding from a surface of the semiconductor substrate202, that are formed by epitaxial growth.

In some embodiments, the NMOS transistor40includes a gate structure410and source/drain regions420located at two opposite sides of the gate structure410, where the gate structure410is formed on an p-well region430, and the source/drain regions420are formed in the p-well region430. In one embodiment, the gate structure410includes a gate electrode412, a gate dielectric layer414and a gate spacer416. The gate dielectric layer414may spread between the gate electrode412and the substrate202, and may or may not further cover a sidewall of the gate electrode412. The gate spacer416may laterally surround the gate electrode412and the gate dielectric layer414. In one embodiment, the source/drain regions420include doped regions of n-type dopant that are formed in the p-well region430by ion implantation. In an alternative embodiment, the source/drain regions420include epitaxial structures formed in and protruding from a surface of the substrate202, that are formed by epitaxial growth.

As illustrated inFIG.1, for example, the substrate200further includes a dielectric layer206stacked on the semiconductor substrate202and a plurality of contact plugs208penetrating through the dielectric layer206to electrically connect to the PMOS transistor30and the NMOS transistor40. In certain embodiments, the dielectric layer206and the contact plugs208are also formed in the structure200during the FEOL processes. The dielectric layer206may laterally surround the gate structures310,410and cover the source/drain regions320,420for providing protections to the devices formed in/on the substrate202. Some of the contact plugs208may penetrate through the dielectric layer206in order to establish electrical connection with the source/drain regions320,420, while others of the contact plugs208(not shown) may penetrate through the dielectric layer206to establish electrical connection with the gate electrodes (e.g. the gate electrodes312,412) of the gate structures310,410, in order to provide terminals for electrical connections to later-formed components (e.g. an interconnect or interconnect structure) or external components.

The dielectric layer206may be referred to as an interlayer dielectric (ILD) layer, while the contact plugs208may be referred to as metal contacts or metallic contacts. For example, the contact plugs208electrically connected to the source/drain regions320,420are referred to as source/drain contacts, and the contact plugs208electrically connected to the gate electrodes312,412are referred to as gate contacts. In some embodiments, the contact plugs208may include copper (Cu), copper alloys, nickel (Ni), aluminum (Al), manganese (Mn), magnesium (Mg), silver (Ag), gold (Au), tungsten (W), a combination of thereof, or the like. The contact plugs208may be formed by, for example, plating such as electroplating or electroless plating, CVD such as plasma enhanced CVD (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), a combination thereof, or the like. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc.

In some embodiments, the dielectric layer206includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbide oxynitride, spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), polyimide, and/or a combination thereof. In alternative embodiments, the dielectric layer206include low-k dielectric materials. For example, the low-k dielectric material generally having a dielectric constant lower than 3.9. Examples of low-k dielectric materials may include BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, Flare, SILK® (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF), and/or a combination thereof. It is understood that the dielectric layer206may include one or more dielectric materials. For example, the dielectric layer206include a single-layer structure or a multilayer structure. In some embodiments, the dielectric layer206is formed to a suitable thickness by CVD such as flowable chemical vapor deposition (FCVD), HDP-CVD, and SACVD, spin-on, sputtering, or other suitable methods.

A seed layer (not shown) may be optionally formed between the dielectric layer206and the contact plugs208. That is, for example, the seed layer covers a bottom surface and sidewalls of the contact plugs208. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the contact plugs208includes copper layer and the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer is formed using, for example, PVD or the like. In one embodiment, the seed layer may be omitted.

In addition, an additional barrier layer or adhesive layer (not shown) may be optionally formed between the contact plugs208and the dielectric layer206. Owing to the additional barrier layer or adhesive layer, it is able to prevent the seed layer and/or the contact plugs208from diffusing to the underlying layers and/or the surrounding layers. The additional barrier layer or adhesive layer may include Ti, TiN, Ta, TaN, a combination thereof, a multilayer thereof, or the like, and may be formed using CVD, ALD, PVD, a combination thereof, or the like. In an alternative embodiment of which the seed layer is included, the additional barrier layer or adhesive layer is interposed between the dielectric layer206and the seed layer, and the seed layer is interposed between the contact plugs208and the additional barrier layer or adhesive layer. In one embodiment, the additional barrier layer or adhesive layer may be omitted.

For example, the stack structure is disposed on an illustrated top surface of the substrate200. As shown inFIG.1, the stack structure may include a first dielectric material layer102m, a second dielectric material layer104m, and a hard mask material layer106m, as shown inFIG.1. The stack structure may be referred to as a stack of multiple material layers, where more or less material layers may be included in the stack structure based on the design requirement and demand, the disclosure is not limited thereto.

As shown inFIG.1, the first dielectric material layer102mand the second dielectric material layer104mmay be sequentially stacked on the substrate200to cover the PMOS transistor30and the NMOS transistor40. For example, the first dielectric material layer102mis disposed on (e.g. in contact with) illustrated top surfaces of the contact plugs208and the dielectric layer206, and the second dielectric material layer104mis disposed on (e.g. in contact with) an illustrated top surface of the first dielectric material layer102m. In some embodiments, the first dielectric material layer102mand the second dielectric material layer104mhave different materials. For example, the first dielectric material layer102mincludes a silicon carbide (SiC) layer, a silicon nitride (Si3N4) layer, an aluminum oxide layer, or the like. For example, the second dielectric material layer104mincludes a silicon-rich oxide (SRO) layer. In some embodiments, the second dielectric material layer104mis referred to as an inter-metal dielectric (IMD) layer which may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. It should be noted that the low-k dielectric materials are generally dielectric materials having a dielectric constant lower than 3.9. In some alternative embodiments, the first dielectric material layer102mand the second dielectric material layer104mhave different etching selectivities. In the case, the first dielectric material layer102mmay be referred to as an etching stop layer to prevent the underlying elements (e.g. the contact plugs208and the dielectric layer206) from damage caused by the over-etching.

As shown inFIG.1, the hard mask material layer106mand the patterned resist layer108may be sequentially stacked on the second dielectric material layer104m. For example, the hard mask material layer106mis disposed on (e.g. in contact with) an illustrated top surface of the second dielectric material layer104m, and the patterned resist layer108is disposed on (e.g. in contact with) an illustrated top surface (e.g. a surface106t) of the hard mask material layer106m. The hard mask material layer106mmay be a hard mask utilized to help pattern the first dielectric material layer102mand the second dielectric material layer104m(not shown inFIG.1but illustrated and discussed below with respect toFIG.2throughFIG.4). In some embodiments, the hard mask material layer106mincludes an inorganic dielectric material, such as SiON, SiN, SiC, SiOC, SiCN, or a combination thereof. The hard mask material layer106mmay be formed by any suitable method, such as CVD. The hard mask material layer106mmay have a thickness of about 10 nm to about 100 nm, although other suitable thickness may alternatively be utilized.

As shown inFIG.1, the patterned resist layer108may correspond to a conductive feature (e.g. the contact plugs208) to be connected with a later-formed conductive feature (e.g. a metallization structure ML1inFIG.7). The structure of the metallization structure ML1will be discussed in greater detail later in conjunction withFIG.5throughFIG.7. The later-formed conductive feature may be a metallization pattern such as a redistribution wire/line/via, a connector such as a conductive connector, the like; the disclosure is not limited thereto. That is, the patterned resist layer108includes a plurality of openings O1(each may be referred to as a hole (such as a through hole or an opening hole) or a recess) disposed directly over the contact plugs208, for example. In some embodiments, positioning locations of the openings O1are respectively within a positioning location of a respective one of the contact plugs208in a vertical projection on the substrate200along a stacking direction Z of the first dielectric material layer102mand the second dielectric material layer104m. For illustrative purposes, the number of the openings O1shown inFIG.1does not limit the disclosure, and may be designated and selected based on the demand and layout design.

The patterned resist layer108may be a photosensitive material utilized to help pattern the hard mask material layer106m(not shown inFIG.1but illustrated and discussed below with respect toFIG.2throughFIG.4). The patterned resist layer108may be formed to a thickness of between about 10 nm and about 200 nm, although other suitable thickness may alternatively be utilized. The patterned resist layer108may be a positive resist material or a negative resist material, that is suitable for a patterning process such as a photolithography process with a mask or a mask-less photolithography process (for instance, an electron-beam (e-beam) writing or an ion-beam writing), and may be formed by any suitable method, such as spin-coating or the like. However, other suitable materials and methods of forming the patterned resist layer108may alternatively be utilized.

Referring toFIG.1andFIG.2together, in some embodiments, the hard mask material layer106mand the second dielectric material layer104mare patterned by using the patterned resist layer108as a mask. In the case, using the patterned resist layer108as the patterning mask, a portion of the hard mask material layer106mis removed to form the hard mask material layer106m′. As shown inFIG.2, the openings O1may further extend into the hard mask material layer106m′. For example, the openings O1completely penetrate through the hard mask material layer106m′. Thereafter, using the patterned resist layer108and the hard mask material layer106m′ together as the patterning mask, a portion of the second dielectric material layer104mis removed to form the second dielectric material layer104m′, for example. As shown inFIG.2, the openings O1may further extend into the second dielectric material layer104m′. For example, the openings O1partially penetrate the second dielectric material layer104m′. In some embodiments, the openings O1extends into the second dielectric material layer104m′ until reaching to a position which is about ½ to about ⅓ of a thickness of the second dielectric material layer104m′. However, the disclosure is not limited thereto.

The patterned resist layer108may be consumed during the patterning processes, thus the patterned resist layer108amay have a thickness less than the thickness of the patterned resist layer108. The patterning process may include an etching process, such as a dry etching, a wet etching or a combination thereof. For example, the patterning process includes an anisotropic etching process. After the formation of the second dielectric material layer104m′, the patterned resist layer108amay be removed. The removal process may include ashing process, such as using O2ashing, N2ashing, H2ashing, CO2ashing, or the like, although any other suitable patterning processes may alternatively be utilized. The removal process may include a dry etching, a wet etching or a combination thereof. Alternatively, the removal process may be performed by a dry chemical etch with a plasma source and an etchant gas.

Referring toFIG.3, in some embodiments, a patterned resist layer110is formed on the hard mask material layer106m′, after the removal of the patterned resist layer108. For example, the patterned resist layer110is disposed on (e.g. in contact with) an illustrated top surface (e.g. the surface106t) of the hard mask material layer106m′. The patterned resist layer110may correspond to the openings O1formed in the hard mask material layer106m′ and the second dielectric material layer104m′. That is, the patterned resist layer110includes a plurality of openings O2(each may be referred to as a hole (such as a through hole or an opening hole) or a recess) disposed directly over the openings O1, for example. As shown inFIG.3, a portion of the surface106tof the second dielectric material layer106m′ and the openings O1may be exposed by the openings O2. In some embodiments, positioning locations of the openings O1are respectively within a positioning location of a respective one of the openings O2in the vertical projection on the substrate200along the stacking direction Z of the first dielectric material layer102mand the second dielectric material layer104m′. That is, a size of the openings O2is greater than a size of the opening O1, for example.

For illustrative purposes, the number of the openings O2shown inFIG.3does not limit the disclosure, and may be designated and selected based on the demand and layout design. The formation and material of the patterned resist layer110are substantially identical to or similar to the process and material of forming the patterned resist layer108as described inFIG.1; except that, the patterned resist layer110has a pattern different from that of the patterned resist layer108, and thus are not repeated herein.

Referring toFIG.3andFIG.4together, in some embodiments, the hard mask material layer106m′, the second dielectric material layer104m′ and the first dielectric material layer102mare patterned by using the patterned resist layer110as a mask. In the case, using the patterned resist layer110as the patterning mask, a portion of the hard mask material layer106m′ is removed to form the hard mask layer106a. As shown inFIG.4, the openings O2may further extend into the hard mask layer106a. For example, the openings O2completely penetrate through the hard mask layer106a(so to remove the openings O1to form the hard mask layer106a). Thereafter, using the patterned resist layer110and the hard mask layer106atogether as the patterning mask, a portion of the second dielectric material layer104m′ and a portion of the first dielectric material layer102mare removed to form the second dielectric layer104aand the first dielectric layer102a. As shown inFIG.4, a plurality of openings O3may be formed in the second dielectric layer104aand the first dielectric layer102a. For example, the openings O3completely penetrate through the second dielectric layer104aand the first dielectric layer102a. As shown inFIG.4, surfaces208tof the contact plugs208are accessibly revealed by the openings O3, for example.

The openings O3each may include a trench hole OT1and a via hole OV1underlying and spatially communicated to the trench hole OT1. For example, the trench holes OT1are formed in the second dielectric layer104aand extend from an illustrated top surface of the second dielectric layer104ato a position inside the second dielectric layer104a. For example, the via holes OV1are formed in the second dielectric layer104aand the first dielectric layer102aand extend from the position inside the second dielectric layer104ato an illustrated bottom surface of the first dielectric layer102a. The position may be about ½ to about ⅓ of a thickness of the second dielectric layer104a; however, the disclosure is not limited thereto. In some embodiments, the openings O3includes a dual damascene structure. The formation of the openings O3is not limited to the disclosure. The formation of opening O3(with the dual damascene structure) can be formed by any suitable forming process, such as a via first approach or a trench first approach.

As shown inFIG.4, a size W2of the trench holes OT1may be greater than a size W1of the via holes OV1. In some embodiments, a sidewall S1of each of the via holes OV1is a slant sidewall, seeFIG.4. In alternative embodiments, the sidewall S1of each of the via holes OV1is a vertical sidewall (not shown). In some embodiments, a sidewall S2of each of the trench holes OT1is a vertical sidewall, seeFIG.4. In alternative embodiments, the sidewall S2of each of the trench holes OT1is a slant sidewall (not shown). The sidewall S1of one via hole OV1and the sidewall S2of a respective one trench hole OT1may be collectively referred to as a sidewall of one opening O3.

For illustrative purposes, the number of the openings O3shown inFIG.4does not limit the disclosure, and may be designated and selected based on the demand and layout design. The number of the openings O3may be controlled by adjusting the number of the openings O2formed in the patterned resist layer110. The profile of the trench holes OT1may be controllable by adjusting the profile of the openings O2formed in the patterned resist layer110, and the profile of the trench holes OT1may be controllable by adjusting the profile of the openings O1formed in the patterned resist layer108.

The patterned resist layer110may be consumed during the patterning processes, thus the patterned resist layer110amay have a thickness less than the thickness of the patterned resist layer110. The patterning process may include an etching process, such as a dry etching, a wet etching or a combination thereof. For example, the patterning process includes an anisotropic etching process.

After the formation of the second dielectric layer104aand the first dielectric layer102a, the patterned resist layer110amay be removed immediately (not shown) or may be removed in a later sequentially process (such as a planarization inFIG.7). The removal process may include ashing process, such as using O2 ashing, N2 ashing, H2 ashing, CO2 ashing, or the like, although any other suitable patterning processes may alternatively be utilized. The removal process may include a dry etching, a wet etching or a combination thereof. Alternatively, the removal process may be performed by a dry chemical etch with a plasma source and an etchant gas.

Referring toFIG.5, in some embodiments, a barrier material112mand a liner material114mare sequentially formed over the structure depicted inFIG.4. As shown inFIG.5, the barrier material112mmay be conformally formed over the substrate200. For example, the barrier material112mfurther extends into the openings O2and the openings O3so to line at least the openings O2and the openings O3. In some embodiments, the barrier material112mis in (physical) contact with sidewalls (e.g. S1and S2) of the openings O3, sidewalls of the openings O2, the surface208tof the contact plugs208exposed by the openings O3, and an illustrated top surface of the patterned resist layer110. Thereafter, the liner material114mmay be conformally formed over the barrier material112m. For example, the liner material114mfurther extends into the openings O2and the openings O3to cover the barrier material112m. In some embodiments, the liner material114mis in (physical) contact with an illustrated top surface of the barrier material112m. In other words, the liner material114mmay at least line the barrier material112minside the openings O3. Herein, when a layer is described as conformal or conformally formed, it indicates that the layer has a substantially equal thickness extending along the region on which the layer is formed.

In some embodiments, the barrier material112mincludes a material to prevent the later-formed conductive feature (e.g. the metallization structure ML1inFIG.7) from diffusing (e.g., Cu diffusion) to the underlying layers and/or the surrounding layers. The barrier material112mmay include a metal nitride such as TaN, TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, a combination thereof, a multilayer thereof, or the like. In some embodiments, the barrier material112mcan be formed using CVD, ALD, PVD, a combination thereof, or the like. In certain embodiments, the barrier material112mincludes TaN or TiN, although any other suitable materials and processes may alternatively be utilized. The barrier material112mmay have a thickness T112of about 1 nm to about 50 nm, although other suitable thickness may alternatively be utilized. In further alternative embodiments, the barrier material112mincludes a bi-layer structure of Ta/TaN layers or Ti/TiN layers.

In some embodiments, the liner material114mincludes a material to enhance the adhesion between two adjacent layers, such as between the barrier material112mand the later-formed conductive feature (e.g. the metallization structure ML1inFIG.7) for preventing delamination. The liner material114mmay include Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu alloy, a combination thereof, a multilayer thereof, or the like. In some embodiments, the liner material114mcan be formed using PVD, CVD (such as PECVD), and ALD. In certain embodiments, the liner material114mincludes Ta or Ti, although any other suitable materials and processes may alternatively be utilized. The liner material114mmay have a thickness T114of about 1 nm to about 50 nm, although other suitable thickness may alternatively be utilized. The liner material114mmay include a bi-layer structure of Ta/TaN layers or Ti/TiN layers.

Referring toFIG.6, in some embodiments, a seed layer material116mand a conductive material118mare sequentially formed over the liner material114m. As shown inFIG.6, the seed layer material116mmay be disposed on (e.g., in contact with) the liner material114m. In some embodiments, the seed layer material116mis conformally formed on the liner material114mand extends into the openings O3formed in the first dielectric laye102aand the second dielectric layer104a. The openings O3are completely covered by (e.g., lined with) the seed layer material116m, for example. In other words, the seed layer material116mmay at least line the liner material114minside the openings O3.

In some embodiments, the seed layer material116mis formed on the liner material114min a manner of a blanket layer made of metal or metal alloy materials, the disclosure is not limited thereto. In some embodiments, the seed layer material116mis referred to as a metal layer, which can be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer material116mincludes titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the seed layer material116mmay include a titanium layer and a copper layer over the titanium layer. The seed layer material116mmay be formed using, for example, sputtering, PVD, or the like. The seed layer material116mmay have a thickness T116of about 1 nm to about 50 nm, although other suitable thickness may alternatively be utilized.

Thereafter, the conductive material118mmay be disposed on (e.g., in contact with) the seed layer material116m. In some embodiments, the openings O3are filled with the conductive materials118mover the seed layer material116m. In some embodiments, a material of the conductive material118mincludes a suitable conductive material, such as metal and/or metal alloy. For example, the conductive material118mcan be aluminum (Al), aluminum alloys, copper (Cu), copper alloys, or combinations thereof (e.g. AlCu), the like, or combinations thereof. In some embodiments, the conductive material118mis formed by plating process or any other suitable method, which the plating process may include electroplating or electroless plating, or the like. In alternative embodiments, the conductive material118mmay be formed by deposition. The disclosure is not limited thereto.

Referring toFIG.6andFIG.7together, in some embodiments, a planarization process is performed to remove excessive amounts of the conductive material118m, the seed layer material116, the liner material114m, and the barrier material112mover a plane including an illustrated top surface (e.g. a surface104at) of the second dielectric layer104a, thereby forming a barrier layer112a, a liner layer114a, a seed layer116a, and a conductive feature118a. As shown inFIG.7, a surface118atof the conductive feature118a, a surface116atof the seed layer116a, a surface114atof the liner layer114a, and a surface112atof the barrier layer112amay be substantially leveled with the surface104atof the second dielectric layer104a. For example, the surface118atof the conductive feature118a, the surface116atof the seed layer116a, the surface114atof the liner layer114a, and the surface112atof the barrier layer112aare substantially coplanar to the surface104atof the second dielectric layer104a. The planarization process may include a grinding process, a chemical-mechanical polishing (CMP) process, an etching process, the like, or combinations thereof. During the planarizing process, the second dielectric layer104amay also be planarized. After planarizing, a cleaning process may be optionally performed, for example to clean and remove the residue generated from the planarizing process. However, the disclosure is not limited thereto, and the planarizing process may be performed through any other suitable method.

In some embodiments, the conductive feature118a, the seed layer116a, the liner layer114a, and the barrier layer112aare collectively referred to as a metallization structure ML1(or a metallization or conductive layer, or a metallization or conductive pattern), and the first dielectric layer102aand the second dielectric layer104aare collectively referred to as a dielectric structure DL1(or a dielectric layer). For example, the metallization structure ML1penetrates through the dielectric structure DL1and is in contact with the conductive plugs208(e.g., the surfaces208t). That is, the metallization structure ML1is physically and electrically connected to the PMOS transistor30and the NMOS transistor40embedded in the substrate200through the conductive plugs208, for example. In some embodiments, the metallization structure ML1interconnects the (semiconductor) devices included in the substrate200for electrically communication therebetween. The metallization structure ML1may be substantially coplanar with the dielectric structure DL1at two opposite sides of the dielectric structure DL1along the stacking direction Z.

As shown inFIG.7, the metallization structure ML1may be formed in a form of a plurality of segments. For example, each segment of the metallization structure ML1is disposed in a respective one opening O3. In some embodiments, a line portion T1of each segment of the metallization structure ML1is located at the trench hole OT1of one opening O3, and a via portion V1of each segment of the metallization structure ML1is located at the via hole OV1of the opening O3. In some embodiments, for each segment of the metallization structure located in one opening O3, the line portion T1is physically and electrically connected to the via portion V1. In some embodiments, the line portion T1extends laterally along the X-Y plane, while the via portion V1extends vertically along the stacking direction Z. The via portion V1may electrically couple two adjacent conductive features (e.g., the line portion V1and the contact plugs208) along the stacking direction Z. As shown inFIG.7, the via portion V1may penetrate through the first dielectric layer102a.

The line portion T1may also be referred to as a trench portion, a trace portion, or a line portion of the metallization structure ML1. The via portion V1may also be referred to as a through via portion of the metallization structure ML1. As shown inFIG.7, the line portion T1may have a substantially vertical sidewall, and the via portion V1may have a slant sidewall. However, the disclosure is not limited thereto; alternatively, the line portion T1and the via portion V1independently may have a substantially vertical sidewall or a slant sidewall.

Referring toFIG.8, in some embodiments, a material layer120mis formed over the metallization structure ML1. For example, the material layer120mis disposed on (e.g., in contact with) an illustrated top surface of the metallization structure ML1being coplanar to an illustrated top surface of the dielectric structure DL1. In some embodiments, the material layer120mis formed by forming a blanket of an initial capping material over the illustrated top surface of the metallization structure ML1and the illustrated top surface of the dielectric structure DL1by a deposition process (such as PVD, ALD, or CVD) or a plating process (such as electroplating or electroless plating). In some embodiments, the initial capping material includes a transition metal selected from the groups IVB, VB, or VIB of the periodic table. For example, the initial capping material includes Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, Co, Rh, Ir, Ni, Pd, Pt, or the like. In some embodiments, the initial capping material includes Ta. In the embodiment of which the technology node is N5or beyond, the material layer120mhas a thickness T120mof about 0.7 nm to about 25 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120mmay be in a range of about 1 nm to about 15 nm. In an alternative embodiment (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the material layer120mmay have a thickness T120mof about 3.5 nm to about 50 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120mmay be in a range of about 5 nm to about 50 nm. The material layer120mmay be referred to as a capping material layer.

Referring toFIG.8andFIG.9, in some embodiments, a thermal treatment is performed on the material layer120mto form a capping layer120a. For example, the capping layer120ais disposed on (e.g., in contact with) the illustrated top surface (including the surfaces118at,116at,114atand112at) of the metallization structure ML1. In some embodiments, the capping layer120acovers the illustrated top surface (including the surfaces118at,116at,114atand112at) of the metallization structure ML1and further extends onto the illustrated top surface (e.g. the surface104at) of the dielectric structure DL1. As shown inFIG.9, the capping layer120amay completely cover the illustrated top surfaces of the metallization structure ML1and the dielectric structure DL1. However, the disclosure is not limited thereto. In some embodiments, the capping layer120a, the metallization structure ML1and the dielectric structure DL1together constitute a build-up layer L1A included in an interconnect structure (e.g., an interconnect300A of the semiconductor structure1000ofFIG.12). Owing to the capping layer120a, the surface scattering effect occurred at the illustrate top surface of the metallization structure ML1is suppressed, thereby improving the Rs (line resistance) performance. Therefore, the device performance of the semiconductor structure1000is enhanced.

In some embodiments, the capping layer120ais made of transition metal dichalcogenides or the like. In some embodiments, the transition metal dichalcogenides are represented by a general formula, MXn1, where M is a transition metal selected from the groups IVB, VB, or VIB of the periodic table, X is one element selected from a group consisting of sulfur (S), selenium (Se), and tellurium (Te), and n1 is in a range of 0.5-2. The material of the capping layer120amay be referred to as a two-dimensional (2D) material. However, the disclosure is not limited thereto; in some alternative embodiments, a non-limiting example of the transition metal dichalcogenides is represented by a general formula, Tan2Sn3, where n2 is in a range of 1-2, and n3 is in a range of 2-5. For example, the capping layer120aincludes TaS2, Ta2S5, or a combination of TaS2and Ta2S5. In the embodiments of which the capping layer120aincludes TaS2, Ta2S5, or the combination of TaS2and Ta2S5, the material of the capping layer120afurther includes TaO2. However, the disclosure is not limited thereto.

In the embodiment of which the technology node is N5or beyond, the capping layer120ahas a thickness T120aof about 0.7 nm to about 25 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120amay be in a range of about 1 nm to about 15 nm. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the capping layer120amay have a thickness T120aof about 3.5 nm to about 50 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120amay be in a range of about 5 nm to about 50 nm. The thickness T120aof the capping layer120amay be substantially the same as the thickness T120mof the material layer120m. For example, the thickness T120aof the capping layer120ais identical to the thickness T120mof the material layer120m.

In some embodiments, the thermal treatment is performed in a manner with a CVD tool, such as a cold wall CVD chamber. In the embodiments of which the capping layer120aincludes TaS2, the thermal treatment is a PECVD process for reacting the material layer120mwith a precursor (involving sulfur) to obtain the capping layer120a, and is performed in a cold wall CVD chamber at a pressure in a range from about 10 mTorr to about 760 mTorr, at a temperature in a range from about 400° C. to about 800° C., at a power in a range from about 200 watts (W) to about 450 watts, with a gas flow including from about 35 standard cubic centimeters per minute (sccm) to about 65 sccm of dimethyl disulfide (DMDS) (serving as a precursor) and from about 1 sccm to about 100 sccm of a carrier gas. However, the disclosure is not limited thereto. For example, the carrier gas includes Ar or the like.

In alternative embodiments, the thermal treatment is performed in a manner with a furnace tool. In the embodiments of which the capping layer120aincludes TaS2, the thermal treatment is a heating process for reacting the material layer120mwith a precursor (involving sulfur) to obtain the capping layer120a, and is performed in a furnace at a pressure in a range from about 10 mTorr to about 760 mTorr, at a temperature in a range from about 400° C. to about 800° C., at a power in a range from about 60 watts W to about 100 watts, with a gas flow including from about 5 sccm to about 15 sccm of H2S (serving as a precursor) and from about 5 sccm to about 15 sccm of Ar. That is, the embodiments of which the capping layer120aincludes TaS2, the thermal treatment performed on the material layer120mis a sulfidation process.

The capping layer120amay include one or more than one sub-layer. In some embodiments, the capping layer120aincludes a single layer structure, such as having only one sub-layer. In alternative embodiments, the capping layer120aincludes a layered structure, such as having more than one sub-layer. As shown inFIG.9, the capping layer120amay include a plurality of sub-layers, such as sub-layers120-1,120-2and120-3. In some embodiments, each of the sub-layers120-1,120-2and120-3is a monolayer structure having a thickness ranging approximately from 0.7 nm to 5 nm. For example, the sub-layers120-1may have a thickness T120-1of about 0.7 nm to about 5 nm, the sub-layers120-2may have a thickness T120-2of about 0.7 nm to about 5 nm, and the sub-layers120-3may have a thickness T120-3of about 0.7 nm to about 5 nm. Only three sub-layers included in the capping layer120aare shown inFIG.9for illustrative purposes, however the disclosure is not limited thereto. In certain embodiments of which the technology node is N5or beyond, the number of the sub-layers included in the capping layer120ais one to five layers. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the number of the sub-layers included in the capping layer120ais more than five layers.

In some embodiments, materials of the sub-layers120-1,120-2and120-3include the material of the capping layer120aas aforementioned, and thus are not repeated herein. For example, the material of the capping layer120ais a homogenous material throughout, where the materials of the sub-layers120-1,120-2and120-3are identical to each other.

The capping layer120amay include a flat structure. As shown inFIG.9, for example, in the cross-sectional view, a top surface120atof the capping layer120ais flat and planar. In other words, the sub-layers120-1,120-2and120-3individually may be a conformal layer having a substantially constant thickness with a high degree of coplanarity. Alternatively, in the cross-sectional view, the top surface (e.g., a surface S3) of the capping layer120amay be in a concave-and-convex form (in periodic order), where the sub-layers120-1,120-2and120-3independently may be a layer having a substantially constant thickness, as shown inFIG.10A. However, the disclosure is not limited thereto; the capping layer120amay include a waving structure. In the cross-sectional view, the top surface (e.g., a surface S4) of the capping layer120amay be in a wave-form (in a non-periodic order), where at least one of the sub-layers120-1,120-2and120-3may be a layer having a non-constant thickness, as shown inFIG.10B.

Referring toFIG.11, in some embodiments, a build-up layer L2A, a build-up layer L3A and a build-up layer L4A are sequentially formed over the build-up layer L1A to form the interconnect300A over the substrate200. The interconnect300A may be referred as an interconnect structure, a redistribution layer or a redistribution structure of the semiconductor structure1000, which provides routing functions for the devices formed in the substrate200of the semiconductor structure1000. Owing to the interconnect300A, the devices formed in the substrate200can be electrically coupled and electrically communicated to each other and/or to external components.

The build-layer layer L2A is disposed on (e.g., in contact with) the build-layer layer L1A, as shown inFIG.11. For example, the build-up layer L2A includes a dielectric structure DL2(including a first dielectric layer102band a second dielectric layer104bstacked thereon), a metallization structure ML2(including a barrier layer112b, a liner layer114b, a seed layer116b, and a conductive feature118b), and a capping layer120acovering the dielectric structure DL2and the metallization structure ML2. In some embodiments, the metallization structure ML2penetrates through the dielectric structure DL2to electrically couple to the metallization structure ML1of the build-up layer L1A. As shown inFIG.11, the surface120atof the capping layer120aof the build-up layer L1A may be covered by the dielectric structure DL2(e.g. the first dielectric layer102b), where a sidewall of the capping layer120aof the build-up layer L1A may be free from the dielectric structure DL2(e.g. the first dielectric layer102b). That is, the sidewall of the capping layer120aof the build-up layer L1A is substantially aligned with a sidewall of the dielectric structure DL2and a sidewall of the dielectric structure DL1, for example. In some embodiments, the dielectric structure DL2and the metallization structure ML2of the build-up layer L2A are sandwiched between the capping layer120aof the build-up layer L2A and the capping layer120aof the build-up layer L1A. Owing to the capping layer120a, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structure ML2is suppressed, thereby improving the Rs (line resistance) performance. The device performance of the semiconductor structure1000is enhanced. The formation and material of the first dielectric layer102b, the second dielectric layer104b, the barrier layer112b, the liner layer114b, the seed layer116b, and the conductive feature118bare substantially identical to or similar to the process and material of forming the first dielectric layer102a, the second dielectric layer104a, the barrier layer112a, the liner layer114a, the seed layer116a, and the conductive feature118aas described inFIG.1throughFIG.7, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

The build-layer layer L3A is disposed on (e.g., in contact with) the build-layer layer L2A, as shown inFIG.11. For example, the build-up layer L3A includes a dielectric structure DL3(including a first dielectric layer102cand a second dielectric layer104cstacked thereon), a metallization structure ML3(including a barrier layer112c, a liner layer114c, a seed layer116c, and a conductive feature118c), and a capping layer120acovering the dielectric structure DL3and the metallization structure ML3. In some embodiments, the metallization structure ML3penetrates through the dielectric structure DL3to electrically couple to the metallization structure ML2of the build-up layer L2A. As shown inFIG.11, an illustrated top surface of the capping layer120aof the build-layer layer L2A may be covered by the dielectric structure DL3(e.g. the first dielectric layer102c), where a sidewall of the capping layer120aof the build-layer layer L2A may be free from the dielectric structure DL3(e.g. the first dielectric layer102c). That is, the sidewall of the capping layer120aof the build-layer layer L2A is substantially aligned with a sidewall of the dielectric structure DL3and the sidewall of the dielectric structure DL2, for example. In some embodiments, the dielectric structure DL3and the metallization structure ML3of the build-up layer L3A are sandwiched between the capping layer120aof the build-up layer L3A and the capping layer120aof the build-up layer L2A. Owing to the capping layer120a, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structure ML3is suppressed, thereby improving the Rs (line resistance) performance. The device performance of the semiconductor structure1000is enhanced. The formation and material of the first dielectric layer102c, the second dielectric layer104c, the barrier layer112c, the liner layer114c, the seed layer116c, and the conductive feature118care substantially identical to or similar to the process and material of forming the first dielectric layer102a, the second dielectric layer104a, the barrier layer112a, the liner layer114a, the seed layer116a, and the conductive feature118aas described inFIG.1throughFIG.7, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

The build-layer layer L4A is disposed on (e.g., in contact with) the build-layer layer L3A, as shown inFIG.11. For example, the build-up layer L4A includes a dielectric structure DL4(including a first dielectric layer102dand a second dielectric layer104dstacked thereon), a metallization structure ML4(including a barrier layer112d, a liner layer114d, a seed layer116d, and a conductive feature118d), and a capping layer120acovering the dielectric structure DL4and the metallization structure ML4. In some embodiments, the metallization structure ML4penetrates through the dielectric structure DL4to electrically couple to the metallization structure ML3of the build-up layer L3A. As shown inFIG.11, an top illustrated surface of the capping layer120aof the build-layer layer L3A may be covered by the dielectric structure DL4(e.g. the first dielectric layer102d), where a sidewall of the capping layer120aof the build-layer layer L3A may be free from the dielectric structure DL4(e.g. the first dielectric layer102d). That is, the sidewall of the capping layer120aof the build-layer layer L3A is substantially aligned with a sidewall of the dielectric structure DL4and the sidewall of the dielectric structure DL3, for example. In some embodiments, the dielectric structure DL4and the metallization structure ML4of the build-up layer L4A are sandwiched between the capping layer120aof the build-up layer L4A and the capping layer120aof the build-up layer L3A. Owing to the capping layer120a, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structure ML4is suppressed, thereby improving the Rs (line resistance) performance. The device performance of the semiconductor structure1000is enhanced. The formation and material of the first dielectric layer102d, the second dielectric layer104d, the barrier layer112d, the liner layer114d, the seed layer116d, and the conductive feature118dare substantially identical to or similar to the process and material of forming the first dielectric layer102a, the second dielectric layer104a, the barrier layer112a, the liner layer114a, the seed layer116a, and the conductive feature118aas described inFIG.1throughFIG.7, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

For illustration purpose, four build-up layers are included in the interconnect300A ofFIG.11; however, the disclosure is not limited thereto. The number of the build-up layer included in the interconnect300A is not limited in the disclosure, and may be selected based on the demand and design layout. That is, the number of the build-up layer included in the interconnect300A may be one or more than one as long as the interconnect300A can provide a sufficient routing function to the devices (e.g.,30and/or40) included in the substrate200.

Referring toFIG.12, in some embodiments, after the formation of the interconnect300A, a passivation layer400, a plurality of under-bump metallurgy (UBM) patterns500, and conductive terminals600are sequentially formed over the interconnect300A to form the semiconductor structure1000. As shown inFIG.12, a top illustrated surface of the capping layer120aof the build-up layer L4A may be covered by the passivation layer400, where a sidewall of the capping layer120aof the build-up layer L4A may be free from the passivation layer400. That is, the sidewall of the capping layer120aof the build-up layer L4A is substantially aligned with a sidewall of the passivation layer400and the sidewall of the dielectric structure DL4, for example. In some embodiments, the UBM patterns500penetrate through the passivation layer400to electrically couple the metallization structure ML4of the build-up layer L4A. In some embodiments, the conductive terminals600are disposed over the UBM patterns500to electrically couple the metallization structure ML4of the build-up layer L4A through the UBM patterns500. Due to the UBM patterns500, the adhesion between the conductive terminals600and the interconnect300A is enhanced. For example, at least some of the conductive terminals600are electrically connected to the devices (e.g.30and/40) included in the substrate200through the interconnect300A.

For example, the passivation layer400is disposed on (e.g., in contact with) the interconnect300A (e.g. on an outermost surface300tof the interconnect300A). The outermost surface300tof the interconnect300A may be a surface120atof the capping layer120aincluded in the build-up layer L4A, as shown inFIG.12. In some embodiments, the passivation layer400is extended on the surface120atof the capping layer120aincluded in the build-up layer L4A. In some embodiments, the passivation layer400accessibly reveals the capping layer120aincluded in the build-up layer L4A through a plurality of openings (not labeled) formed in the passivation layer400for electrically connecting the metallization structure ML4included in the build-up layer L4A to the later-formed connectors. In some embodiments, the passivation layer400is formed by, but not limited to, forming a blanket layer of dielectric material over the outermost surface300tof the interconnect300A to completely cover the capping layer120aincluded in the build-up layer L4A and patterning the dielectric material blanket layer to form the passivation layer400with the openings exposing the portions of the capping layer120aincluded in the build-up layer L4A underneath thereto. The material of the passivation layer400may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In some embodiments, the dielectric material blanket layer is formed by suitable fabrication techniques such as spin-on coating, CVD, (e.g. PECVD), or the like. In some embodiments, the passivation layer400is referred to as a protective layer of the interconnect300A for providing protection thereto.

In some embodiments, the UBM patterns500are disposed on the passivation layer400and further extended into the openings formed in the passivation layer400. The UBM patterns500are in (physically) contact with the capping layer120aincluded in the build-up layer L4A for electrically connecting the interconnect300A, as shown inFIG.12. In the disclosure, the UBM patterns500facilitate electrical connections between the interconnect300A and the conductive terminals600. However, the disclosure is not limited thereto; alternatively, the UBM patterns500may be omitted based on the design layout and demand. The material of the UBM patterns500may include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed in a manner of a mono-layer or a multi-layer (e.g. with different materials in any two or more stacked layers in one UBM pattern500) by an electroplating process and an etching process. The number of the UBM patterns500is not limited in the disclosure, and corresponds to the numbers of the later-formed conductive elements.

In some embodiments, the conductive terminals600are attached to the UBM patterns500through a solder flux. In some embodiments, the conductive terminals600are disposed on the UBM patterns500by ball placement process or reflow process. The conductive terminals600are, for example, micro-bumps, chip connectors (e.g. controlled collapse chip connection (C4) bumps), ball grid array (BGA) balls, solder balls or other connectors. The number of the conductive terminals600is not limited to the disclosure, and may be designated and selected based on the numbers of the openings formed in the passivation layer400. When solder is used, the solder may include either eutectic solder or non-eutectic solder. The solder may include lead or be lead-free, and may include Sn—Ag, Sn—Cu, Sn—Ag—Cu, or the like. In one embodiment, the conductive terminals600are referred to as conductive connectors for connecting with another package or a circuit substrate (e.g. organic substrate such as printed circuit board (PCB)). In an alternative embodiment, the conductive terminals600are referred to as conductive terminals for inputting/outputting electric and/or power signals. In a further alternative embodiment, the conductive terminals600are referred to as conductive terminals for connecting with one or more than one semiconductor dies independently including active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.), other components such as one or more than one integrated passive device (IPDs), or combinations thereof. The disclosure is not limited thereto.

The capping layers120aof the disclosure each are a continuous layer, for example. However, the disclosure is not limited thereto. Alternatively, a capping layer of the disclosure may be a discontinuous layer with a plurality of segments separated from one another, see a semiconductor structure2000ofFIG.15.

FIG.13throughFIG.15are schematic cross-sectional views showing a method of manufacturing a semiconductor structure in accordance with some alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, electrical connections, etc.) of the same elements would not be repeated herein.

Referring toFIG.13, in some embodiments, a material layer120nis selectively formed over is formed over the metallization structure ML1, following the process as described inFIG.7. For example, the material layer120nis disposed on (e.g., in contact with) the illustrated top surface (including the surfaces118at,116at,114atand112at) of the metallization structure ML1being coplanar to the illustrated top surface of the dielectric structure DL1. In some embodiments, the material layer120nis free from the dielectric structure DL1. As shown inFIG.13, the material layer120nmay not cover (e.g. not extend onto) the surface S104atof the second dielectric layer104a, for example. A material of the material layer120nis substantially identical to or similar to the material of the material layer120mas previously described inFIG.8, and thus are not repeated herein for brevity. In some embodiments, the material layer120nincludes Ta. In the embodiment of which the technology node is N5or beyond, the material layer120nhas a thickness T120nof about 0.7 nm to about 25 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120nmay be in a range of about 1 nm to about 15 nm. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the material layer120nmay have a thickness T120nof about 3.5 nm to about 50 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120nmay be in a range of about 5 nm to about 50 nm. The material layer120nmay be referred to as a capping material layer.

Referring toFIG.14, in some embodiments, a thermal treatment is performed on the material layer120nto form a capping layer120b. For example, the capping layer120bis disposed on (e.g., in contact with) the illustrated top surface (including the surfaces118at,116at,114atand112at) of the metallization structure ML1. In some embodiments, the capping layer120bonly covers the illustrated top surface (including the surfaces118at,116at,114atand112at) of the metallization structure ML1. As shown inFIG.14, the capping layer120bmay completely cover the illustrated top surfaces of the metallization structure ML1and may not cover (or extend onto) the dielectric structure DL1. In some embodiments, the capping layer120b, the metallization structure ML1and the dielectric structure DL1together constitute a build-up layer L1B included in an interconnect structure (e.g., an interconnect300B of the semiconductor structure2000ofFIG.15). Owing to the capping layer120b, the surface scattering effect occurred at the illustrate top surface of the metallization structure ML1is still suppressed, thereby improving the Rs (line resistance) performance. Therefore, the device performance of the semiconductor structure2000is enhanced. The formation and material of the capping layer120bare substantially identical to or similar to the process and material of forming the capping layer120aas described inFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

In the embodiment of which the technology node is N5or beyond, the capping layer120bhas a thickness T120bof about 0.7 nm to about 25 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120bmay be in a range of about 1 nm to about 15 nm. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the capping layer120bmay have a thickness T120aof about 3.5 nm to about 50 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T120bmay be in a range of about 5 nm to about 50 nm. The thickness T120bof the capping layer120bmay be substantially the same as the thickness T120nof the material layer120n. For example, the thickness T120bof the capping layer120bis identical to the thickness T120nof the material layer120n.

The capping layer120bmay include one or more than one sub-layer. In some embodiments, the capping layer120bincludes a single layer structure, such as having only one sub-layer. In alternative embodiments, the capping layer120bincludes a layered structure, such as having more than one sub-layer. As shown inFIG.14, the capping layer120bmay include a plurality of sub-layers, such as sub-layers120-1,120-2and120-3. Only three sub-layers included in the capping layer120bare shown inFIG.14for illustrative purposes, however the disclosure is not limited thereto. In certain embodiments of which the technology node is N5or beyond, the number of the sub-layers included in the capping layer120bis one to five layers. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the number of the sub-layers included in the capping layer120bis more than five layers. The details of the sub-layers120-1,120-2and120-3have been previously described inFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

In alternative embodiments, the capping layer120bmay be formed by performing a patterning process on the structure depicted inFIG.9, prior the formation of the build-up layers stacked thereon for forming the interconnect. During the pattering process, a portion of the capping layer120a(ofFIG.9) is removed to form the capping layer120b(ofFIG.14). The patterning process may include photolithography and etching processes. The etching process may include dry etching, wet etching, or a combination thereof.

Referring toFIG.15, in some embodiments, a build-up layer L2B, a build-up layer L3B and a build-up layer L4B are sequentially formed over the build-up layer L1B to form the interconnect300B over the substrate200. The interconnect300B may be referred as an interconnect structure, a redistribution layer or a redistribution structure of the semiconductor structure2000, which provides routing functions for the devices formed in the substrate200of the semiconductor structure2000. Owing to the interconnect300B, the devices formed in the substrate200can be electrically coupled and electrically communicated to each other and/or to external components. In some embodiments, the build-up layer L2B, the build-up layer L3B and the build-up layer L4B of the interconnect300B inFIG.15are similar to the build-up layer L2A, the build-up layer L3A and the build-up layer L4A of the interconnect300A inFIG.12, the difference is that, in each of the build-up layer L2B, the build-up layer L3B and the build-up layer L4B, the capping layer120ais substituted by a capping layer120b. The details of the capping layer120bhave been previously described inFIG.13andFIG.14; thus, are not repeated herein for brevity. Owing to the capping layers120b, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structures ML2, ML3and ML4is still suppressed, thereby improving the Rs (line resistance) performance. The device performance of the semiconductor structure2000is enhanced.

In some embodiments, after forming the interconnect300B, the process ofFIG.12is performed to sequentially form a passivation layer400, a plurality of UBM patterns500and a plurality of conductive terminals600over the interconnect300B. Up to here, the semiconductor structure2000is manufactured. In some embodiments, the passivation layer400is disposed on (e.g., in contact with) an outermost surface300t(including a surface120btand a surface104dt) of the interconnect300B. In some embodiments, the UBM patterns500penetrate through the passivation layer400to electrically couple the metallization structure ML4of the build-up layer L4B. In some embodiments, the conductive terminals600are disposed over the UBM patterns500to electrically couple the metallization structure ML4of the build-up layer L4B through the UBM patterns500. Due to the UBM patterns500, the adhesion between the conductive terminals600and the interconnect300B is enhanced. For example, at least some of the conductive terminals600are electrically connected to the devices (e.g.30and/40) included in the substrate200through the interconnect300B. However, the disclosure is not limited thereto; alternatively, the UBM patterns500may be omitted based on the design layout and demand.

As shown inFIG.15, a sidewall and the surface120btof the capping layer120bof the build-up layer L1B may be covered by the dielectric structure DL2(e.g. the first dielectric layer102b). That is, the sidewall of the capping layer120bof the build-up layer L1B is not aligned with a sidewall of the dielectric structure DL2and a sidewall of the dielectric structure DL1, for example. As shown inFIG.15, a sidewall and an illustrated top surface of the capping layer120bof the build-layer layer L2B may be covered by the dielectric structure DL3(e.g. the first dielectric layer102c). That is, the sidewall of the capping layer120bof the build-layer layer L2B is not aligned with a sidewall of the dielectric structure DL3and the sidewall of the dielectric structure DL2, for example. As shown inFIG.15, a sidewall and a top illustrated surface of the capping layer120bof the build-layer layer L3B may be covered by the dielectric structure DL4(e.g. the first dielectric layer102d). That is, the sidewall of the capping layer120bof the build-layer layer L3B is not aligned with a sidewall of the dielectric structure DL4and the sidewall of the dielectric structure DL3, for example. As shown inFIG.15, a sidewall and a top illustrated surface of the capping layer120bof the build-up layer L4B may be covered by the passivation layer400. That is, the sidewall of the capping layer120bof the build-up layer L4B is not aligned with a sidewall of the passivation layer400and the sidewall of the dielectric structure DL4, for example.

The capping layer of the disclosure has a good barrier property for preventing a later-formed conductive feature from diffusing (e.g., Cu diffusion) to the underlying layers and/or the surrounding layers and a good liner property for enhancing the adhesion between two adjacent layers. Owing to such capping layer, a liner layer may be substituted by the capping layer disclosed herein, see a semiconductor structure3000ofFIG.19and a semiconductor structure4000ofFIG.20. However, the disclosure is not limited thereto. Alternatively, owing to such capping layer, a liner layer and a barrier layer may be substituted by the capping layer disclosed herein, see a semiconductor structure5000ofFIG.21and a semiconductor structure6000ofFIG.22.

FIG.16throughFIG.19are schematic cross-sectional views showing a method of manufacturing a semiconductor structure in accordance with some alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, electrical connections, etc.) of the same elements would not be repeated herein.

Referring toFIG.16, in some embodiments, a barrier material112mand a material layer122mare sequentially formed over the structure depicted inFIG.4. As shown inFIG.16, the barrier material112mmay be conformally formed over the substrate200. For example, the barrier material112mis extended into the openings O3(including the trench hole OT1and the via hole OV1) to be in (physical) contact with the contact plugs208. The formation, material and positioning configuration of the barrier material112mhave been previously described inFIG.5, and thus are not repeated herein. Thereafter, a material layer122mmay be conformally formed over the barrier material112m. For example, the material layer122mfurther extends into the openings O2formed in the hard mask layer106aand the patterned resist layer110and the openings O3formed in the first dielectric layer102aand the second dielectric layer104ato cover the barrier material112m. In some embodiments, the material layer122mis in (physical) contact with an illustrated top surface of the barrier material112m. In other words, the material layer122mmay at least line the barrier material112minside the openings O3.

A material of the material layer122mis substantially identical to or similar to the material of the material layer120mas previously described inFIG.8, and thus are not repeated herein for brevity. In some embodiments, the material layer122mincludes Ta. In the embodiment of which the technology node is N5or beyond, the material layer122mhas a thickness T122mof about 0.7 nm to about 25 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T122mmay be in a range of about 1 nm to about 15 nm. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the material layer122mmay have a thickness T122mof about 3.5 nm to about 50 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T122mmay be in a range of about 5 nm to about 50 nm. The material layer122mmay be referred to as a capping material layer.

Referring toFIG.17, in some embodiments, a thermal treatment is performed on the material layer122mto form a capping layer122. For example, the capping layer122is disposed on (e.g., in contact with) the illustrated top surface of the barrier material112m. The formation and material of the capping layer122are substantially identical to or similar to the process and material of forming the capping layer120aas described inFIG.9in conjunction withFIG.10AandFIG.10Bor the process and material of forming the capping layer120bas described inFIG.13in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity. In the embodiment of which the technology node is N5or beyond, the capping layer122has a thickness T122of about 0.7 nm to about 25 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T122may be in a range of about 1 nm to about 15 nm. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the capping layer122may have a thickness T122of about 3.5 nm to about 50 nm, although other suitable thickness may alternatively be utilized. For example, the thickness T122may be in a range of about 5 nm to about 50 nm. The thickness T122of the capping layer122may be substantially the same as the thickness T122mof the material layer122m. For example, the thickness T122of the capping layer122is identical to the thickness T122mof the material layer122m.

The capping layer122may include one or more than one sub-layer. In some embodiments, the capping layer122includes a single layer structure, such as having only one sub-layer. In alternative embodiments, the capping layer122includes a layered structure, such as having more than one sub-layer. As shown inFIG.17, the capping layer122may include a plurality of sub-layers, such as sub-layers122-1,122-2and122-3. In some embodiments, each of the sub-layers122-1,122-2and122-3is a monolayer structure having a thickness ranging approximately from 0.7 nm to 5 nm. For example, the sub-layers122-1may have a thickness T122-1of about 0.7 nm to about 5 nm, the sub-layers122-2may have a thickness T122-2of about 0.7 nm to about 5 nm, and the sub-layers122-3may have a thickness T122-3of about 0.7 nm to about 5 nm. Only three sub-layers included in the capping layer122are shown inFIG.17for illustrative purposes, however the disclosure is not limited thereto. In certain embodiments of which the technology node is N5or beyond, the number of the sub-layers included in the capping layer122is one to five layers. In alternative embodiments (not shown), as the technology node is N7, N10, N16, N20and so on (e.g. a larger critical dimension), the number of the sub-layers included in the capping layer122is more than five layers.

In some embodiments, materials of the sub-layers122-1,122-2and122-3include the material of the capping layer122as aforementioned, and thus are not repeated herein. For example, the material of the capping layer122is a homogenous material throughout, where the materials of the sub-layers122-1,122-2and122-3are identical to each other. The capping layer122may include a flat structure or a waving structure as substantially identical to or similar to the capping layer120adescribed inFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

Referring toFIG.18, in some embodiments, after the formation of the capping layer122a, the processes ofFIG.6throughFIG.9are performed to form a barrier layer112a, a capping layer122a(including the sub-layers122-1,122-2and122-3), a seed layer116a, a conductive feature118a, and a capping layer120a. For example, the barrier layer112, the capping layer122a, the seed layer116aand the conductive feature118aare collectively referred to as a metallization structure ML1′ (or a metallization or conductive layer, or a metallization or conductive pattern), and the first dielectric layer102aand the second dielectric layer104aare collectively referred to as a dielectric structure DL1(or a dielectric layer). For example, the metallization structure ML1′ penetrates through the dielectric structure DL1and is in contact with the conductive plugs208(e.g., the surfaces208t). That is, the metallization structure ML1′ is physically and electrically connected to the PMOS transistor30and the NMOS transistor40embedded in the substrate200through the conductive plugs208, for example. In some embodiments, the metallization structure ML1′ interconnects the (semiconductor) devices included in the substrate200for electrically communication therebetween. The metallization structure ML1′ may be substantially coplanar with the dielectric structure DL1at two opposite sides of the dielectric structure DL1along the stacking direction Z. As shown inFIG.18, the capping layer120amay completely cover the illustrated top surfaces of the metallization structure ML1′ and the dielectric structure DL1, where the illustrated top surface of the metallization structure ML1′ may be leveled with and coplanar to the illustrated top surface of the dielectric structure DL1. However, the disclosure is not limited thereto. For example, the material of the capping layer122ais the same as the material of the capping layer120a. For example, the thickness of the capping layer122ais the same as the thickness of the capping layer120a.

In some embodiments, the capping layer120a, the metallization structure ML1′ and the dielectric structure DL1together constitute a build-up layer L1C included in an interconnect structure (e.g., an interconnect300C of the semiconductor structure3000ofFIG.19). Owing to the capping layer120a, the surface scattering effect occurred at the illustrate top surface of the metallization structure ML1′ is suppressed, thereby improving the Rs (line resistance) performance. Owing to the capping layer122a, the surface scattering effect occurred at a sidewall of the metallization structure ML1′ is suppressed, thereby improving the Re (via resistance) performance. Therefore, the device performance of the semiconductor structure3000is enhanced. The details of the barrier layer112a, the conductive feature118a, and the capping layer120ahave been previously described inFIG.6throughFIG.9in conjunction withFIG.10AandFIG.10B, and the details of the capping layer122aare substantially identical to or similar to the details of the capping layer122as described inFIG.17; thus, are not repeated herein for simplicity.

Referring toFIG.19, in some embodiments, a build-up layer L2C, a build-up layer L3C and a build-up layer L4C are sequentially formed over the build-up layer L1C to form the interconnect300C over the substrate200. The interconnect300C may be referred as an interconnect structure, a redistribution layer or a redistribution structure of the semiconductor structure3000, which provides routing functions for the devices formed in the substrate200of the semiconductor structure3000. Owing to the interconnect300C, the devices formed in the substrate200can be electrically coupled and electrically communicated to each other and/or to external components.

The build-layer layer L2C is disposed on (e.g., in contact with) the build-layer layer L1C, as shown inFIG.19. For example, the build-up layer L2C includes a dielectric structure DL2(including a first dielectric layer102band a second dielectric layer104bstacked thereon), a metallization structure ML2′ (including a barrier layer112b, a capping layer122b, a seed layer116b, and a conductive feature118b), and a capping layer120acovering the dielectric structure DL2and the metallization structure ML2′. In some embodiments, the metallization structure ML2′ penetrates through the dielectric structure DL2to electrically couple to the metallization structure ML1′ of the build-up layer L1C. In some embodiments, the dielectric structure DL2and the metallization structure ML2′ of the build-up layer L2C are sandwiched between the capping layer120aof the build-up layer L2C and the capping layer120aof the build-up layer L1C. Owing to the capping layer120a, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structure ML2′ is suppressed, thereby improving the Rs (line resistance) performance. Owing to the capping layer122b, the surface scattering effect occurred at a sidewall of the metallization structure ML2′ is suppressed, thereby improving the Re (via resistance) performance. The device performance of the semiconductor structure3000is enhanced. The formation and material of the first dielectric layer102b, the second dielectric layer104b, the barrier layer112b, the seed layer116b, and the conductive feature118bare substantially identical to or similar to the process and material of forming the first dielectric layer102a, the second dielectric layer104a, the barrier layer112a, the liner layer114a, the seed layer116a, and the conductive feature118aas described inFIG.1throughFIG.7, the details of the capping layer122bare substantially identical to or similar to the details of the capping layer122aas described inFIG.16throughFIG.18, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity. For example, the material of the capping layer122bis the same as the material of the capping layer120a. For example, the thickness of the capping layer122bis the same as the thickness of the capping layer120a.

The build-layer layer L3C is disposed on (e.g., in contact with) the build-layer layer L2C, as shown inFIG.19. For example, the build-up layer L3C includes a dielectric structure DL3(including a first dielectric layer102cand a second dielectric layer104cstacked thereon), a metallization structure ML3′ (including a barrier layer112c, a capping layer122c, a seed layer116c, and a conductive feature118c), and a capping layer120acovering the dielectric structure DL3and the metallization structure ML3′. In some embodiments, the metallization structure ML3′ penetrates through the dielectric structure DL3to electrically couple to the metallization structure ML2′ of the build-up layer L2C. In some embodiments, the dielectric structure DL3and the metallization structure ML3′ of the build-up layer L3C are sandwiched between the capping layer120aof the build-up layer L3C and the capping layer120aof the build-up layer L2C. Owing to the capping layer120a, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structure ML3′ is suppressed, thereby improving the Rs (line resistance) performance. Owing to the capping layer122c, the surface scattering effect occurred at a sidewall of the metallization structure ML3′ is suppressed, thereby improving the Re (via resistance) performance. The device performance of the semiconductor structure3000is enhanced. The formation and material of the first dielectric layer102c, the second dielectric layer104c, the barrier layer112c, the seed layer116c, and the conductive feature118care substantially identical to or similar to the process and material of forming the first dielectric layer102a, the second dielectric layer104a, the barrier layer112a, the liner layer114a, the seed layer116a, and the conductive feature118aas described inFIG.1throughFIG.7, the details of the capping layer122care substantially identical to or similar to the details of the capping layer122ahave been previously described inFIG.16throughFIG.18, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity. For example, the material of the capping layer122cis the same as the material of the capping layer120a. For example, the thickness of the capping layer122cis the same as the thickness of the capping layer120a.

The build-layer layer L4C is disposed on (e.g., in contact with) the build-layer layer L3C, as shown inFIG.19. For example, the build-up layer L4C includes a dielectric structure DL4(including a first dielectric layer102dand a second dielectric layer104dstacked thereon), a metallization structure ML4′ (including a barrier layer112d, a capping layer122d, a seed layer116d, and a conductive feature118d), and a capping layer120acovering the dielectric structure DL4and the metallization structure ML4′. In some embodiments, the metallization structure ML4′ penetrates through the dielectric structure DL4to electrically couple to the metallization structure ML3′ of the build-up layer L3C. In some embodiments, the dielectric structure DL4and the metallization structure ML4′ of the build-up layer L4C are sandwiched between the capping layer120aof the build-up layer L4C and the capping layer120aof the build-up layer L3C. Owing to the capping layer120a, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structure ML4′ is suppressed, thereby improving the Rs (line resistance) performance. Owing to the capping layer122d, the surface scattering effect occurred at a sidewall of the metallization structure ML4′ is suppressed, thereby improving the Re (via resistance) performance. The device performance of the semiconductor structure3000is enhanced. The formation and material of the first dielectric layer102d, the second dielectric layer104d, the barrier layer112d, the seed layer116d, and the conductive feature118dare substantially identical to or similar to the process and material of forming the first dielectric layer102a, the second dielectric layer104a, the barrier layer112a, the liner layer114a, the seed layer116a, and the conductive feature118aas described inFIG.1throughFIG.7, the details of the capping layer122dare substantially identical to or similar to the details of the capping layer122ahave been previously described inFIG.16throughFIG.18, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity. For example, the material of the capping layer122dis the same as the material of the capping layer120a. For example, the thickness of the capping layer122dis the same as the thickness of the capping layer120a. In some embodiments, the capping layer122a,122b,122c, and122dindependently are referred to as a capping liner or a capping liner layer.

For illustration purpose, four build-up layers are included in the interconnect300C ofFIG.19; however, the disclosure is not limited thereto. The number of the build-up layer included in the interconnect300C is not limited in the disclosure, and may be selected based on the demand and design layout. That is, the number of the build-up layer included in the interconnect300C may be one or more than one as long as the interconnect300C can provide a sufficient routing function to the devices (e.g.,30and/or40) included in the substrate200.

In some embodiments, after forming the interconnect300C, the process ofFIG.12is performed to sequentially form a passivation layer400, a plurality of UBM patterns500and a plurality of conductive terminals600over the interconnect300C. Up to here, the semiconductor structure3000is manufactured. In some embodiments, the passivation layer400is disposed on (e.g., in contact with) an outermost surface300t(including a surface120at) of the interconnect300C. In some embodiments, the UBM patterns500penetrate through the passivation layer400to electrically couple the metallization structure ML4′ of the build-up layer L4C. In some embodiments, the conductive terminals600are disposed over the UBM patterns500to electrically couple the metallization structure ML4′ of the build-up layer L4C through the UBM patterns500. Due to the UBM patterns500, the adhesion between the conductive terminals600and the interconnect300C is enhanced. For example, at least some of the conductive terminals600are electrically connected to the devices (e.g.30and/40) included in the substrate200through the interconnect300C. However, the disclosure is not limited thereto; alternatively, the UBM patterns500may be omitted based on the design layout and demand.

FIG.20is a schematic cross-sectional view of a semiconductor structure in accordance with some alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, electrical connections, etc.) of the same elements would not be repeated herein. In some embodiments, the semiconductor structure4000ofFIG.20and the semiconductor structure3000ofFIG.19are similar; and the difference is that, the semiconductor structure4000substitutes the interconnect300C with an interconnect300D.

In some embodiments, the interconnect300D includes a build-up layer L1D, a build-up layer L2D, a build-up layer L3D and a build-up layer L4D. The interconnect300D may be referred as an interconnect structure, a redistribution layer or a redistribution structure of the semiconductor structure4000, which provides routing functions for the devices formed in the substrate200of the semiconductor structure4000. Owing to the interconnect300D, the devices formed in the substrate200can be electrically coupled and electrically communicated to each other and/or to external components. In some embodiments, the build-up layer LID, the build-up layer L2D, the build-up layer L3D and the build-up layer L4D of the interconnect300D inFIG.20are similar to the build-up layer L1C, the build-up layer L2C, the build-up layer L3C and the build-up layer L4C of the interconnect300C inFIG.19, the difference is that, in each of the build-up layer LID, the build-up layer L2D, the build-up layer L3D and the build-up layer L4D, the capping layer120ais substituted by a capping layer120b. The details of the capping layer120bhave been previously described inFIG.13andFIG.14; thus, are not repeated herein for brevity. For example, the material of each of the capping layers122a,122b,122cand122dis the same as the material of the capping layer120b. For example, the thickness of each of the capping layers122a,122b,122cand122dis the same as the thickness of the capping layer120b. Owing to the capping layers120b, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structures ML1′, ML2′, ML3′ and ML4′ is still suppressed, thereby improving the Rs (line resistance) performance. Owing to the capping layers122a-122d, the surface scattering effect occurred at the sidewalls of the metallization structures ML1′, ML2′, ML3′ and ML4′ is suppressed, thereby improving the Re (via resistance) performance. The device performance of the semiconductor structure4000is enhanced.

FIG.21is a schematic cross-sectional view of a semiconductor structure in accordance with some alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, electrical connections, etc.) of the same elements would not be repeated herein. In some embodiments, the semiconductor structure5000ofFIG.21and the semiconductor structure3000ofFIG.19are similar; and the difference is that, the semiconductor structure5000substitutes the interconnect300C with an interconnect300E.

In some embodiments, the interconnect300E includes a build-up layer L1E, a build-up layer L2E, a build-up layer L3E and a build-up layer L4E. As shown inFIG.21, the build-up layer L1E, the build-up layer L2E, the build-up layer L3E and the build-up layer L4E are electrically coupled to each other and are stacked over the substrate200in order. The interconnect300E may be referred as an interconnect structure, a redistribution layer or a redistribution structure of the semiconductor structure5000, which provides routing functions for the devices formed in the substrate200of the semiconductor structure5000. Owing to the interconnect300E, the devices formed in the substrate200can be electrically coupled and electrically communicated to each other and/or to external components. In some embodiments, the build-up layer L1E, the build-up layer L2E, the build-up layer L3E and the build-up layer L4E of the interconnect300E inFIG.21are similar to the build-up layer L1C, the build-up layer L2C, the build-up layer L3C and the build-up layer L4C of the interconnect300C inFIG.19, the difference is that, there is no barrier layers112a,112b,112e,112din interconnect300E.

In some embodiments, a capping layer120a, a metallization structure ML1″ and a dielectric structure DL1together constitute the build-up layer L1E, where the metallization structure ML1″ includes a capping layer122a, a seed layer116aand a conductive feature118a, and the dielectric structure DL1includes a first dielectric layer102aand a second dielectric layer104a. As shown inFIG.21, the capping layer120amay cover illustrated top surfaces of the metallization structure ML1″ and the dielectric structure DL1, where the illustrated top surfaces of the metallization structure ML1″ and the dielectric structure DL1may be leveled with and coplanar to each other. Owing to the capping layers120aand122a, the surface scattering effect occurred at the illustrate top surface and a sidewall of the metallization structure ML1″ is suppressed, thereby improving the Rs (line resistance) and Re (via resistance) performances. With the omission of the barrier layer112ain the openings O3, an overall volume of the conductive feature118aoccupying in the openings O3is increased, thereby decreasing the resistance of the conductive feature118aincluded in the metallization structure ML1″ and thus further improving the Rs (line resistance) performance. The device performance of the semiconductor structure5000is enhanced. The formation and material of the first dielectric layer102a, the second dielectric layer104a, the seed layer116a, and the conductive feature118ahave been previously described inFIG.1throughFIG.7, the details of the capping layer122ahave been previously described inFIG.16throughFIG.18, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

In some embodiments, a capping layer120a, a metallization structure ML2″ and a dielectric structure DL2together constitute the build-up layer L2E, where the metallization structure ML2″ includes a capping layer122b, a seed layer116band a conductive feature118b, and the dielectric structure DL2includes a first dielectric layer102band a second dielectric layer104b. As shown inFIG.21, the capping layer120amay cover illustrated top surfaces of the metallization structure ML2″ and the dielectric structure DL2, where the illustrated top surfaces of the metallization structure ML2″ and the dielectric structure DL2may be leveled with and coplanar to each other. Owing to the capping layers120aand122b, the surface scattering effect occurred at illustrate top and bottom surfaces and a sidewall of the metallization structure ML2″ is suppressed, thereby improving the Rs (line resistance) and Re (via resistance) performances. With the omission of the barrier layer112b, an overall volume of the conductive feature118bis increased, thereby decreasing the resistance of the conductive feature118bincluded in the metallization structure ML2″ and thus further improving the Rs (line resistance) performance. The device performance of the semiconductor structure5000is enhanced. The formation and material of the first dielectric layer102b, the second dielectric layer104b, the seed layer116b, and the conductive feature118bhave been previously described inFIG.1throughFIG.7, the details of the capping layer122bhave been previously described inFIG.19, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

In some embodiments, a capping layer120a, a metallization structure ML3″ and a dielectric structure DL3together constitute the build-up layer L3E, where the metallization structure ML3″ includes a capping layer122c, a seed layer116cand a conductive feature118c, and the dielectric structure DL3includes a first dielectric layer102cand a second dielectric layer104c. As shown inFIG.21, the capping layer120amay cover illustrated top surfaces of the metallization structure ML3″ and the dielectric structure DL3, where the illustrated top surfaces of the metallization structure ML3″ and the dielectric structure DL3may be leveled with and coplanar to each other. Owing to the capping layers120aand122c, the surface scattering effect occurred at illustrate top and bottom surfaces and a sidewall of the metallization structure ML3″ is suppressed, thereby improving the Rs (line resistance) and Rc (via resistance) performances. With the omission of the barrier layer112e, an overall volume of the conductive feature118eis increased, thereby decreasing the resistance of the conductive feature118cincluded in the metallization structure ML3″ and thus further improving the Rs (line resistance) performance. The device performance of the semiconductor structure5000is enhanced. The formation and material of the first dielectric layer102c, the second dielectric layer104c, the seed layer116c, and the conductive feature118chave been previously described inFIG.1throughFIG.7, the details of the capping layer122chave been previously described inFIG.19, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity.

In some embodiments, a capping layer120a, a metallization structure ML4″ and a dielectric structure DL4together constitute the build-up layer L4E, where the metallization structure ML4″ includes a capping layer122d, a seed layer116dand a conductive feature118d, and the dielectric structure DL4includes a first dielectric layer102dand a second dielectric layer104d. As shown inFIG.21, the capping layer120amay cover illustrated top surfaces of the metallization structure ML4″ and the dielectric structure DL4, where the illustrated top surfaces of the metallization structure ML4″ and the dielectric structure DL4may be leveled with and coplanar to each other. Owing to the capping layers120aand122d, the surface scattering effect occurred at illustrate top and bottom surfaces and a sidewall of the metallization structure ML4″ is suppressed, thereby improving the Rs (line resistance) and Rc (via resistance) performances. With the omission of the barrier layer112d, an overall volume of the conductive feature118dis increased, thereby decreasing the resistance of the conductive feature118dincluded in the metallization structure ML4″ and thus further improving the Rs (line resistance) performance. The device performance of the semiconductor structure5000is enhanced. The formation and material of the first dielectric layer102d, the second dielectric layer104d, the seed layer116d, and the conductive feature118dhave been previously described inFIG.1throughFIG.7, the details of the capping layer122dhave been previously described inFIG.19, and the details of the capping layer120ahave been previously described inFIG.8andFIG.9in conjunction withFIG.10AandFIG.10B; thus, are not repeated herein for brevity. For example, the material of each of the capping layers122a,122b,122cand122dis the same as the material of the capping layer120a. For example, the thickness of each of the capping layers122a,122b,122cand122dis the same as the thickness of the capping layer120a.

For illustration purpose, four build-up layers are included in the interconnect300E ofFIG.21; however, the disclosure is not limited thereto. The number of the build-up layer included in the interconnect300E is not limited in the disclosure, and may be selected based on the demand and design layout. That is, the number of the build-up layer included in the interconnect300E may be one or more than one as long as the interconnect300E can provide a sufficient routing function to the devices (e.g.,30and/or40) included in the substrate200.

FIG.22is a schematic cross-sectional view of a semiconductor structure in accordance with some alternative embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, electrical connections, etc.) of the same elements would not be repeated herein. In some embodiments, the semiconductor structure6000ofFIG.22and the semiconductor structure5000ofFIG.21are similar; and the difference is that, the semiconductor structure6000substitutes the interconnect300E with an interconnect300F.

In some embodiments, the interconnect300F includes a build-up layer L1F, a build-up layer L2F, a build-up layer L3F and a build-up layer L4F. The interconnect300F may be referred as an interconnect structure, a redistribution layer or a redistribution structure of the semiconductor structure6000, which provides routing functions for the devices formed in the substrate200of the semiconductor structure6000. Owing to the interconnect300F, the devices formed in the substrate200can be electrically coupled and electrically communicated to each other and/or to external components. In some embodiments, the build-up layer L1F, the build-up layer L2F, the build-up layer L3F and the build-up layer L4F of the interconnect300F inFIG.22are similar to the build-up layer L1E, the build-up layer L2E, the build-up layer L3E and the build-up layer L4E of the interconnect300E inFIG.21, the difference is that, in each of the build-up layer L1F, the build-up layer L2F, the build-up layer L3F and the build-up layer L4F, the capping layer120ais substituted by a capping layer120b. The details of the capping layer120bhave been previously described inFIG.13andFIG.14; thus, are not repeated herein for brevity. For example, the material of each of the capping layers122a,122b,122cand122dis the same as the material of the capping layer120b. For example, the thickness of each of the capping layers122a,122b,122cand122dis the same as the thickness of the capping layer120b. Owing to the capping layers120b, the surface scattering effect occurred at illustrate top and bottom surfaces of the metallization structures ML1″, ML2″, ML3″ and ML4″ is still suppressed, thereby improving the Rs (line resistance) performance. Owing to the capping layers122a-122d, the surface scattering effect occurred at the sidewalls of the metallization structures ML1″, ML2″, ML3″ and ML4″ is suppressed, thereby improving the Re (via resistance) performance. The device performance of the semiconductor structure6000is enhanced.

FIG.23is a schematic cross-sectional view showing an application of a semiconductor structure in accordance with some embodiments of the disclosure. The elements similar to or substantially the same as the elements described previously will use the same reference numbers, and certain details or descriptions (e.g. the materials, formation processes, positioning configurations, electrical connections, etc.) of the same elements would not be repeated herein. Referring toFIG.23, in some embodiments, a component assembly SC including a first component C1and a second component C2disposed over the first component C1is provided. The first component C1may be or may include a circuit structure, such as a mother board, a package substrate, another printed circuit board (PCB), a printed wiring board, an interposer, and/or other carrier that is capable of carrying integrated circuits. In some embodiments, the second component C2mounted on the first component C1is similar to one of the semiconductor structures1000,2000,3000,4000,5000, and60. For example, one or more the semiconductor structures (e.g.,1000,2000,3000,4000,5000, and6000) may be electrically coupled to the first component C1through a plurality of terminals CT. The terminals CT may be the conductive terminals600as described inFIG.12,FIG.15,FIG.19,FIG.20,FIG.21, andFIG.22.

In some embodiments, an underfill UF is formed between the gap of the first component C1and the second component C2to at least laterally cover the terminals CT. Alternatively, the underfill UF is omitted. The underfill UF may be any acceptable material, such as a polymer, epoxy resin, molding underfill, or the like, for example. In one embodiment, the underfill may be formed by underfill dispensing, a capillary flow process, or any other suitable method. Owing to the underfill UF, a bonding strength between the first component C1and the second component C2is enhanced.

Besides, the capping layer and/or the additional capping layer can further adopted to an integrated Fan-Out (InFO) package, an InFO package having a Package-on-Package (PoP) structure, a chip-on-wafer-on-substrate (CoWoS) package, a flip chip package of an InFO package, or the like, a metallic feature (such as a through-insulator-via, a through-molding-via, a through-dielectric-via, a through-substrate-via, a metallic line/wire/via) included therein is covered by the capping layer and/or the additional capping layer of the disclosure for suppressing the surface scattering effect and thus reducing the resistivity, thereby improving the performance thereof.

In above embodiments, the capping layers120a,120b,122are formed in a two-step process. However, the disclosure is not limited thereto; alternatively, the capping layers120a,120b,122may be directly formed in one-step process, such as directly through ALD process or CVD process. In the embodiments of which the capping layers120a,120b,122is a TaS2being formed in the one-step process, the tantalum precursor includes tantalum dimethylamide (PDMAT), tantalum ethoxide, tantalum chloride, or a combination thereof, while the sulfur precursor includes DMDS or H2S.

In above embodiments, the line portion and the via portion of each of the metallization layers of the disclosure may be formed by a dual damascene process, e.g., in one step. However, the disclosure is not limited thereto. Alternatively, the line portion and the via portion of each of the metallization layers of the disclosure may be formed in different steps, where the trench portion and the via portion may independently formed with or without a capping liner. For example, the sub-layers of the capping liner for the line portion and the respective one via portion are different. A number of sub-layers of the capping liner for the line portion may be less than a number of sub-layers of the capping liner for the respective one via portion. A number of sub-layers of the capping liner for the line portion may be greater than a number of sub-layers of the capping liner for the respective one via portion. For example, the sub-layers of the capping liner for the line portion and the respective one via portion are the same. A number of sub-layers of the capping liner for the line portion may be equal to a number of sub-layers of the capping liner for the respective one via portion.

In accordance with some embodiments, a semiconductor structure includes a substrate and an interconnect. The substrate has a semiconductor device. The interconnect is disposed over the substrate and electrically coupled to the semiconductor device, and includes a metallization layer and a capping layer. The metallization layer is disposed over the substrate and includes a via portion and a line portion connecting to the via portion. The capping layer covers the line portion, where the line portion is sandwiched between the via portion and the capping layer, and the capping layer includes a plurality of sub-layers.

In accordance with some embodiments, a semiconductor structure includes a substrate and an interconnect structure. The substrate has a semiconductor device. The interconnect structure is disposed over the substrate and electrically coupled to the semiconductor device, and includes a dielectric structure, a conductive structure, a first capping layer, and a second capping layer. The conductive structure is disposed in the dielectric structure. The first capping layer is disposed between the dielectric structure and the conductive structure, and the first capping layer has a first layered structure. The second capping layer is disposed over the conductive structure, and the second capping layer has a second layered structure.

In accordance with some embodiments, a method of manufacturing a semiconductor structure includes the following steps: providing a substrate having a semiconductor device; and forming an interconnect over the substrate, the interconnect being electrically coupled to the semiconductor device, wherein forming the interconnect comprises: disposing, over the substrate, a metallization layer comprising a via portion and a line portion connecting to the via portion; forming a first capping material over the line portion of the metallization layer; and performing a thermal treatment on the first capping material to form a first capping layer having a plurality of first sub-layers over the metallization layer, the first capping layer covering the line portion, and the line portion being sandwiched between the via portion and the first capping layer.