Fabric-based high speed serial crossbar switch for ATE

A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M “fabric” speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver.

FIELD OF THE INVENTION

This invention relates to a test system for testing semiconductor devices such as Integrated Circuits (ICs), and more particularly in one embodiment, to the testing of High Speed Serial (HSS) inputs and outputs of a Device Under Test (DUT) by converting them to lower speed parallel signals and providing a path that allows an output to be selectively looped back to one or more inputs.

BACKGROUND OF THE INVENTION

Increases in IC speed have resulted in a new class of ICs with HSS inputs and outputs. These HSS inputs and outputs currently operate at speeds of 622 Mbits/sec to 2-6 Gbits/sec, and next generation HSS inputs and outputs may reach speeds of 10-13 Gbits/sec. There are at least two different types of interfaces requiring HSS inputs and outputs. One type of interface is for communications, where a HSS differential input/output pair is referred to as a “lane,” and wherein a clock might be embedded in the signal. The second type of interface requiring HSS inputs and outputs is found in memory devices communicating with a processor through a HSS memory interface. These memory interfaces may include a forwarded clock that is sent separate from, but along with, the data being transmitted.

As shown in the simplified exemplary stressed eye pattern100ofFIG. 1, as the amount of jitter present in a HSS signal increases, a HSS data transition102may change (i.e. move left or right in time) and the eye104may begin to close. In addition, the eye104may also begin to close depending on the high or low voltage levels106and108, respectively, of the HSS signal. Note that the eye104might have a width of as little as 150-500 picoseconds, so it doesn't take much jitter or other limitations to the bandwidth of the transmission medium to cause a device to have difficulty receiving the HSS signal. Circuitry is therefore often built into the transmit and receive circuitry of HSS interfaces to improve data transmission and reception. Pre-emphasis circuitry is normally used in the transmit circuit to boost signal levels, and equalization is used in the receive circuit to open up the eye and ensure that data can be received.

It is desirable to test the characteristics of the HSS interfaces on Automatic Test Equipment (ATE). Such tests are designed to determine whether these HSS interfaces are working properly—not necessarily to verify the data that is passing through, but rather that the interface circuitry in each HSS interface can detect and process data transitions even at the limits of jitter and voltage level requirements.

For example, as illustrated inFIG. 2a, by injecting data-dependent jitter or changing the high or low voltage levels (see reference character200) of a HSS signal202generated within the ATE204and destined for a HSS input206of a DUT208, the eye of the input signal can be closed up to a certain extent, and it can be determined whether the receiver in the HSS input is capable of receiving the data being sent even with the degraded input signal. Although in one embodiment of the present invention, detection logic238in the DUT208is able to detect if the signal was received properly, in another embodiment the DUT then sends the received HSS signal202back to the ATE204on line226. In the latter case, the ATE204then detects the serial bit stream and compares it to the generated bit stream at device speeds using detection logic228to determine if the signals were received and properly transmitted back to the ATE by the DUT208.

One way to generate HSS test signals is by using a Linear Feedback Shift Register (LFSR)222to generate a Pseudo Random Bit Stream (PRBS)224which is then sent to the DUT208. Note that the LFSR222ofFIG. 2ais merely symbolic, and does not represent an actual digital circuit. Actual LFSRs, not shown inFIG. 2a, are well-understood by those skilled in the art. The DUT208then generates a HSS output226based on the received PRBS224. LFSRs222are advantageous because they provide a simple means to generate a serial bit stream, and provide enough data transitions to enable the ATE204to recover the embedded clock (if any) from the data stream and test for data-dependent jitter. Another type of signal that can test data-dependent jitter is the IEEE 802.3ae compliant Continuous Jitter test pattern (CJpat), which is designed to exercise clock recovery circuits and get as much data-dependent jitter out of a short waveform as possible. Signals read from memory can also be used to test data-dependent jitter.

As illustrated in the example ofFIG. 2b, conventional ATE systems210may also test HSS signals by providing a path that allows a HSS output212from the DUT214(generated using a LFSR or other logic230) to be selectively switched or looped back to a single HSS input216of the DUT. This is often called loopback. These loopback tests are designed to simulate various levels of jitter and voltage levels, so that when the DUT214generates a signal218that is received into the ATE210, the signal is sent back out to the DUT with some added jitter or changed voltage levels (see reference character220) to stress the receiver of the HSS input216and determine whether it is working properly. The DUT214receives the loopback signal and performs comparisons (see reference character232) to determine if the signals were transmitted and received properly by the DUT. Note that testing at device speeds limits the type of circuits that can be used to implement the loopback circuitry. The transmitter of a HSS output212can also be tested in a limited manner in the ATE210by measuring the voltage levels coming out of the transmitter, and measuring current and output jitter at Direct Current (DC) voltage levels.

It is desirable in the loopback configuration ofFIG. 2bto have the capability to loop back any HSS output from the DUT214to any HSS input of the DUT. Conventional mechanisms for doing this utilize analog or high speed digital switches234. However, analog switching presents loading problems as the signals are passed through multiple relays, and output driving problems if a single signal is to be routed to multiple DUT inputs. High speed digital solutions require complex, special purpose, high speed circuitry. In either case, a switching network to switch these signals directly requires a large bandwidth and is very costly. In addition, such loopback configurations are only capable of looping back a single DUT HSS output to a single DUT HSS input.

Note that one alternative to the loopback circuitry ofFIG. 2bis a single wire. However, single wire loopback circuits do not allow for the test signal to be applied to a selectable HSS input or multiple HSS inputs, do not allow for jitter or signal levels to be adjusted (i.e. they are limited by any adjustments that can be made by the transmitter of the DUT), and also require more Built-In Self Test (BIST) capabilities in the DUT.

Therefore, there is a need for loopback circuitry that is capable of connecting a DUT HSS output to multiple DUT HSS inputs, and doing so at lower speeds to enable its implementation in a wider variety of lower cost devices with reduced pin counts.

SUMMARY OF THE INVENTION

The present invention is directed to a loopback module that utilizes fabric-based switching to loop back one DUT output HSS signal to one or multiple DUT input HSS signals while reducing or eliminating signal degradations due to variable loading, path length variations and bandwidth reductions on the signals. In addition, embodiments of the present invention provide the ability to connect and switch in memory or other devices to provide data to the DUT input HSS signals using the fabric-based switch, and utilize a parallel rather than serial (i.e. more expensive) PRBS generator/receiver.

In the loopback module of the present invention, each of N differential HSS digital data input channels, each one lane wide and transmitted at a particular data rate, is received and sent to a serial to parallel converter, whose output is an M-bit wide parallel input. By doing so, the effective data rate is reduced or divided down by M to 1/M “fabric” speeds. If the differential HSS digital data input channels contain an embedded clock, the channels are received into clock/data recovery circuits before being sent to the serial to parallel converters to extract the clock embedded in the data, along with the serial data itself.

The M-bit wide parallel input is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit wide parallel inputs to any of Q M-bit wide parallel outputs by effectively utilizing one multiplexer for each parallel output data. Memory can also be connected to the crossbar switch, and parallel data to/from the memory can be transferred from/to the switch at fabric speeds. The memory data can then be switched in crossbar fashion to any channel or combination of channels, and be reconstructed as HSS data, or HSS data from a HSS digital data input channel can be stored in parallel fashion in the memory.

Each parallel output data of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output representing the regeneration of a HSS digital data input channel, or HSS digital data from another source such as the memory. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver. In addition, an optional First In First Out buffer (FIFO) may be placed on the parallel inputs or parallel outputs of the crossbar switch to temporarily store data when input/output speed mismatches are introduced. A parallel PRBS generator may also be switched in crossbar fashion to any channel or combination of channels to enable PRBS data to be generated and forced onto the parallel outputs.

In other embodiments, a processor or pattern generator (an engine that operates sequentially on pattern instructions at lower clock speeds) could optionally be connected to the crossbar switch and switched in crossbar fashion to any channel or combination of channels to provide data on parallel outputs. In addition, the processor could be employed as a control engine to write to control registers and configure the loopback module and the crossbar switch in the same way that a processor is used to configure a digital pin in a tester.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the present invention are directed to a loopback module that utilizes fabric-based switching to loop back one DUT output HSS signal to one or multiple DUT input HSS signals while reducing or eliminating signal degradations due to variable loading, path length variations and bandwidth reductions on the signals. In addition, embodiments of the present invention provide the ability to connect and switch in memory or other devices to provide data to the DUT input HSS signals using the fabric-based switch, and utilize a parallel rather than serial (i.e. more expensive) PRBS generator/receiver.

A high-level block diagram of an exemplary test system300capable of incorporating embodiments of the present invention is illustrated inFIG. 3. InFIG. 3, the modules302may be functional units such as a digital pincard, an analog card, a Device Power Supply (DPS), Arbitrary Waveform Generator (AWG), or a loopback module316according to embodiments of the present invention. The physical connections to the modules302and316may be obtained through a module connection enabler304that includes a switch matrix network306. The switch matrix network306may include logic, traces, and pins. The system controller308is typically the point of interaction for a user. The system controller308provides a gateway to the site controllers310and synchronization of the site controllers310in a multi-site/multi-DUT environment. The system controller308and multiple site controllers310may operate in a master-slave configuration. The system controller308controls the overall system operation and determines that functions that a particular site controller310should perform. Each site controller310is itself sufficient to test a DUT312. The site controller310controls and monitors the operation of various modules302and316within a test site314. A test site314is a collection of modules that service the testing of a single DUT312. A site controller310can control one or multiple test sites314.

The overall platform consists of a hardware and software framework that provides interfaces through which various hardware and software modules can be employed. The architecture is a modularized system with module control software and a communication library that allows module-to-module, site controller to module, site controller-to-site controller, and system controller to site controller communication.

The loopback module316advantageously provides the test system300with a cost-effective and flexible capability to test DUTs with multiple HSS inputs and outputs by looping back any one of the HSS outputs to one or multiple HSS inputs.

FIG. 4illustrates a block diagram of an exemplary loopback module400according to embodiments of the present invention. InFIG. 4, each of N (e.g. 16) differential HSS digital data input channels402, each one lane wide and transmitted at a particular data rate (e.g. 6.4 Gbits/sec), are sent to a serial to parallel converter410, which generates an M-bit wide parallel input412(e.g. 40 bits wide) from M sequential serial bits of the input channel402. By doing so, the effective data rate is reduced or divided down by M (e.g. divided by 40) to 1/M “fabric” speeds (e.g. 160 MHz, which is 1/40thof 6.4 Gbits/sec). Logic operating at these fabric speeds can advantageously be implemented in relatively inexpensive standard digital logic such as a Field Programmable Gate Array (FPGA). If the differential HSS digital data input channels402contain an embedded clock, the channels are received into clock/data recovery circuits404before being sent to the serial to parallel converters410. Each clock/data recovery circuit404extracts a clock406(e.g. 6.4 GHz) embedded in the data, along with the serial data itself408at a particular rate (e.g. 6.4 Gbits/sec).

Note that if the serial to parallel and parallel to serial conversions could not be handled within an FPGA due to speed limitations of the FPGA, and as a result had to be performed in discrete circuitry outside the FPGA, many FPGA Input/Outputs (I/Os) would be required to receive the parallel data into the FPGA. However, FPGA speeds have now improved to the point where they can handle the serial to parallel conversion at the full device or clock rate (e.g. 6.4 Gbits/sec).

Each M-bit wide parallel input412is then sent to a non-blocking crossbar switch414, which is able to route any of the N M-bit wide parallel inputs412to any of Q (e.g. 16) M-bit wide parallel outputs416through the appropriate use of registers and multiplexers. The crossbar switch414effectively includes a multiplexer426(e.g. a 40-bit wide 16:1 multiplexer) for each parallel output416. This is especially useful in DUTs having a particular serial test output port intended to be switched into a number of DUT inputs. The present invention allows for any number of the DUT inputs to receive the test output.

There are several advantages to this switching approach. A HSS digital data input channel402can be routed simultaneously to more than one output416without developing loading problems. Particularly in this case, there are no switch-setting dependent loading effects on the HSS digital data input channel402. Also, because the crossbar switch414operates at fabric speeds, the crossbar switch can be implemented in relatively inexpensive standard digital logic such as an FPGA. Note that without the conversion to fabric speeds, expensive high speed digital switches or expensive and bandwidth and fanout-prohibitive high speed analog switching would have to be employed.

Each M-bit wide parallel output416of the crossbar switch414is sent to a multiplexer438through an optional First In First Out buffer (FIFO)428. The FIFO428may be placed on the parallel inputs412or parallel outputs416of the crossbar switch414(preferably in the lower “fabric” speed domain) to temporarily store data when input/output speed mismatches are introduced. For example, a speed mismatch of 100 ppm in frequency may be introduced to test the DUT's capability to handle slight frequency differences.

A memory444may also be employed to store parallel data and send the parallel data to multiplexer438. In addition, HSS data from a HSS digital data input channel402can be converted to parallel data, routed through the crossbar313, and stored in parallel fashion into the memory444at fabric speeds.

A parallel PRBS generator430may also be employed to generate M-bit wide parallel PRBS data to be sent to multiplexer438. In a parallel PRBS generator430, which is a device well-understood by those skilled in the art, the M-bit parallel equivalent of a high speed LFSR output waveform is computed at each low speed (fabric rate) clock cycle (as opposed to computing those same M bits serially at the high speed serial clock rate). In the parallel PRBS generator430, an LFSR with particular feedback taps (the particular feedback taps being chosen to represent a particular Boolean algebra equation) generates a bit stream that has a maximum length of 2^n−1, where n is the number of stages in the LFSR. This bit stream continuously repeats as the LFSR is clocked. A starting point in the 2^n−1 cyclical bit stream can be established by pre-loading the appropriate ones and zeros in the LFSR registers (flip-flops) as a seed. A standard seed436can be used to ensure that the PRBS generator430always starts at the same place.

Depending on how multiplexer438is switched, parallel to serial converter418will receive either the M-bit wide parallel output416, an M-bit wide parallel output from memory444, or an M-bit wide parallel output from PRBS generator430. The output of the parallel to serial converter418is a HSS output420. Each HSS output420is fed into a jitter generator circuit422, and then to an output driver424(which may then send the signal to a HSS input of the DUT).

Each M-bit wide parallel input412is also sent to a PRBS detector440, which includes a PRBS generator454as described above and comparison logic456. The purpose of the PRBS detector440is to detect errors in the received M-bit wide parallel input412. This is accomplished by comparing the received M-bit wide parallel input412with a PRBS generated in the PRBS generator454. However, before this comparison can be made by comparison logic456, the PRBS generator454must be aligned to the same point in its 2^n−1 cyclical pattern that the received M-bit wide parallel input412is at. This is accomplished by choosing the last M bits of the received data as a seed458, and then generating the next M bits with the PRBS generator454and comparing them to the next 40 bits of received data on the M-bit wide parallel input412. As the PRBS generator454continues to run, this comparison is made on an ongoing basis to the received data. The seed458is only entered into the PRBS generator454once, just before the first compare cycle.

In other embodiments, a processor or pattern generator446(an engine that operates sequentially on pattern instructions at lower clock speeds) could optionally be applied to multiplexer438or connected to the crossbar switch414and switched in crossbar fashion to any channel or combination of channels to provide data on parallel outputs416. In addition, the processor446could be employed in communication with a control engine448to write to control registers and configure the loopback module400and the crossbar switch414in the same way that a processor is used to configure a digital pin in a tester.

In still further embodiments in which the loopback module400is contained within a single FPGA (except for the jitter generator circuits422and drivers424), an external memory450and external FPGA452could optionally be connected to the crossbar switch414and switched in crossbar fashion to any channel or combination of channels to provide data on parallel outputs416, or to store input data received into the main FPGA.

FIG. 5illustrates a logic diagram of an exemplary non-blocking crossbar switch500according to embodiments of the present invention described above, which is able to route any of the N M-bit parallel input data502to any of Q (e.g. 16) parallel output data504through the appropriate use of registers and multiplexers. The crossbar switch500effectively includes a multiplexer506(e.g. a 40-bit wide 16:1 multiplexer) for each parallel output504.

FIG. 6illustrates a block diagram of a crossbar switch and differential driver and receiver circuits for the inputs and outputs of the loopback module according to embodiments of the present invention described above. InFIG. 6, differential driver and receiver pairs600and602, respectively, provide the interfaces to the loopback module. A Precision Measurement Unit (PMU)618may be coupled to each signal of each differential pair to measure the characteristics of each signal. A jitter injection circuit604is present on each output, and may be fed by an AWG606. A Clock Data Recovery (CDR) circuit616(which normally recovers the embedded clock from an input signal that has an embedded clock) cleans up jitter present on received signals. A PRBS generator608is coupled into the crossbar switch610. Additionally, memory612is coupled to every driver600and receiver602, and a PRBS comparator (a PRBS detector which contains both a PRBS generator and a comparison circuit)614is also coupled to every receiver.