Fast/slow acting current limited for inverter power supply

Inverter power supply control circuitry that protects power supply components from relatively quick-changing over-current conditions and that provides regulation of the power supply's output current upon relatively slow-changing load conditions.

BACKGROUND OF THE INVENTION 
In the prior art it is known to provide regulated DC power to a load using 
an inverter power supply--see the publication "Power Supplies for 
Computers and Peripherals," S. Davis, Computer Design, July, 1972, Pages 
55 through 65. Generally, a filtered DC input voltage is inverted to a 
bi-directional DC signal that is coupled to a center tap of an input 
winding of an output or coupling transformer via switching transistors. 
Control circuitry is coupled to the output winding of the coupling 
transformer to regulate the output voltage across the load. Additionally, 
current sensing circuitry on the output side of the coupling transformer 
may be utilized to provide overload or short circuit protection for 
variations in loading--see the publication "Here Are More Protective 
Circuits," A. Annunziato, Electronic Design 10, May 13, 1971, Pages 64 
through 67, with particular reference to FIG. 12. However, it is desirable 
that such inverter power supplies include both fast-acting and slow-acting 
reactions to fast-changing and slow-changing variations in loading. 
SUMMARY OF THE INVENTION 
In the present invention, a variable-amplitude, pulse-width-modulator (PWM) 
current signal from an inverter power supply's switching transistors is 
sampled by a transformer-coupled current detector that generates a 
corresponding sample voltage v.sub.s level. This sample voltage v.sub.s is 
coupled to a slow-acting current limiting circuit and to a voltage 
regulator. The voltage regulator is referenced to a feedback voltage 
v.sub.fb, from the power supply's load circuit generating a control 
voltage v.sub.c. The control voltage v.sub.c is, in turn, coupled back to 
the PWM that controls the duty cycle of the switching transistors and, in 
turn, the duty cycle of the PWM current signal. Slow changes in the 
feedback voltage v.sub.fb or the sample voltage v.sub.s cause appropriate 
slow changes in the control voltage v.sub.c, which maintains, via a 
corresponding change in the duty cycle of the switching transistors, a 
regulated output voltage at the power supply's load. A fast change in the 
sample voltage v.sub.s is detected by a fast-acting current limiting 
circuit to cause a fast change in the control voltage v.sub.c and a 
corresponding fast change in the duty cycle of the PWM current signal and 
a corresponding change in the regulated output voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
With particular reference to FIG. 1 there is illustrated a portion of an 
inverter power supply in which the control circuitry 10 of the present 
invention is incorporated. A high voltage, unregulated DC voltage V.sub.IN 
is coupled to the primary winding of sampling transformer T.sub.1 and is 
then coupled to the center tap of the primary winding of output or 
coupling transformer T.sub.2. The end terminals of the primary winding of 
output transformer T.sub.2 are, in turn, coupled to switching transistors 
Q.sub.S1 and Q.sub.S2. Switching transistors Q.sub.S1 and Q.sub.S2, which 
are controlled by the pulse-width-modulator (PWM) 12, couple a pulse width 
modulated current signal to the secondary winding of output transformer 
T.sub.2. The output circuitry 14 samples the output current flowing 
through the load 16 providing a feedback voltage v.sub.fb. This feedback 
voltage v.sub.fb is coupled to control circuitry 10, which is coupled to 
the secondary winding of sampling transformer T.sub.1, and which, in turn, 
generates a control voltage v.sub.c. Control voltage v.sub.c is, in turn, 
coupled to the PWM 12 for controlling the duty cycle or pulse width of the 
switching transistors Q.sub.S1 and Q.sub.S2 and, in turn, the load or 
output voltage V.sub.OUT. The present invention is directed toward the 
control circuitry 10. 
With particular reference to FIG. 2 there is presented a schematic 
illustration of the control circuitry 10 of the present invention. A 
variable-amplitude, variable duty cycle current signal i.sub.d is sampled 
by a transformer-coupled current detector 20 that generates a 
corresponding sample voltage v.sub.s level. This sample voltage v.sub.s is 
representative of the power supply's output current for steady state 
operation. This sample voltage v.sub.s is coupled to a slow-acting current 
limiting circuit 22 and to a voltage regulator 24. The voltage regulator 
24 is referenced to a fixed-level reference voltage v.sub.r2 and to a 
variable feedback voltage v.sub.fb, from, e.g., the power supply's output 
circuitry 14, for generating a control voltage v.sub.c. The control 
voltage v.sub.c is, in turn, coupled back to the PWM 12 that controls the 
duty cycle of the switching transistors Q.sub.S1 and Q.sub.S2 and, in 
turn, the duty cycle of the PWM current signal i.sub.s =i.sub.s1 +i.sub.s2 
that flows through the primary winding of the output transformer T.sub.2. 
Slow changes in the feedback voltage v.sub.fb or the sample voltage 
v.sub.s cause appropriate slow changes in the control voltage v.sub.c, 
which maintains, via a corresponding change in the duty cycle of the 
switching transistors Q.sub.S1 and Q.sub.S2, a regulated output voltage 
V.sub.OUT at the power supply's load 16. A fast change in the sample 
voltage v.sub.s is detected by a fast-acting current limiting circuit 26 
to cause a fast change in the control voltage v.sub.c and a corresponding 
fast change in the duty cycle of the PWM current signal i.sub.s and a 
corresponding change in the regulated output voltage V.sub.OUT. 
Current detector 20 is comprised of a current transformer T.sub.1, 
rectifying diode CR.sub.1 and resistor R.sub.1. The current signal 
i.sub.d, which flows through the primary winding of current transformer 
T.sub.1, is converted to a sample voltage v.sub.s across resistor R.sub.1, 
which is, in turn, coupled at node N.sub.0 to slow-acting current limiter 
22 and to fast-acting current limiter 26. 
Slow-acting current limiter 22 is comprised of: (1) a peak detector 
including diode CR.sub.2, resistor R.sub.2 and capacitor C.sub.1 that at 
node N.sub.1 converts the pulse sample voltage v.sub.s to an equivalent DC 
voltage v.sub.i level; (2) a summing node N.sub.1 which compares the 
voltage v.sub.i to a fixed or constant level reference voltage v.sub.r1 
generating an error voltage v.sub.e1 ; and (3) an error amplifier E.sub.c 
which generates the amplified error voltage v.sub.ae1 which, in turn, 
couples the amplified error voltage v.sub.ae1 to voltage regulator 24 via 
diode CR.sub.3. 
Voltage regulator 24 is comprised of: (1) a summing node N.sub.2 which 
generates an error voltage v.sub.e2 from a fixed or constant level 
reference voltage v.sub.r2, amplified error voltage v.sub.ae1 and a 
variable feedback voltage v.sub.fb from, e.g., output circuitry 14; (2) 
error amplifier E.sub.v which generates the amplified error voltage 
v.sub.ae2 ; and, (3) rectifying diode CR.sub.4 which couples the rectified 
amplified error voltage v.sub.ae2 to node N.sub.4 which is coupled to a 
fixed or constant level reference voltage E.sub.1 by resistor R.sub.3. 
Fast-acting current limiter 26 is comprised of zener diode CR.sub.5, 
rectifier diode CR.sub.6, NPN transistor Q.sub.1, resistors R.sub.4 and 
R.sub.5, and capacitor C.sub.2. Whenever the sample voltage v.sub.s at 
node N.sub.0 exceeds the zener voltage of zener diode CR.sub.5 and the 
base-emitter voltage drop of transistor Q.sub.1, transistor Q.sub.1 is 
switched ON discharging capacitor C.sub.2 to ground therethrough. This 
forward biases rectifier diode CR.sub.6 causing control voltage v.sub.c at 
node N.sub.4 to quickly drop toward ground through transistor Q.sub.1. The 
decreasing control voltage v.sub.c at PWM 12 decreases the duty cycle of 
the switching transistors Q.sub.S1 and Q.sub.S2 forcing the PWM current 
signal i.sub.s to a lower safe level. Note that in the configuration 
shown, an increase in the control voltage v.sub.c will provide a 
corresponding increase in the duty cycle of the switching transistors 
Q.sub.S1 and Q.sub.S2.