PRINTED CIRCUIT BOARD

A printed circuit board has a copper clad laminate and a plurality of holes. The copper clad laminate for dissipating heats generated from a chip when the chip operates has a plurality of solder paste disposed areas. The plurality of holes situate on the copper clad laminate and each of the holes does not communicate with others, wherein the plurality of holes are nonconductors. Each of the solder paste disposed areas is surrounded by the plurality of holes and each solder paste disposed areas is surrounded by at least two holes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a printed circuit board (PCB), particularly to a printed circuit board having a copper clad laminate with a plurality of grooves for improving the contact yield of solder paste for Bottom Termination Components.

2. Description of the Related Art

With the rapid development of electronic devices and consumer demand for electronic products to be high performance and compact and slim, the requirement for dissipating heats from a chip within an electronic device is also growing. Surface Mount Technology (SMT) is a method of soldering an electronic chip to a printed circuit board. Hereafter, a QFN (Quad Flat No-leads) chip is used as an example. To achieve good thermal efficiency, sufficient amount of solder paste and ensuring solder joint reliability are key issues for QFN chips. However, due to the excellent heat dissipating ability of copper, the soldering temperature drops rapidly during the course of the surface mount technology procedure, which causes the QFN chip to float and cold soldering of the perimeter I/O (Input/Output) of the QFN chip. As a result, the contact area between the thermal pad area of the QFN chip and the printed circuit board is less than 50%, and the reliability of the QFN chip is consequently decreased. Accordingly, there is a need for improvement.

Further, although prior art US2002/0050380 discloses solder-applied areas are surrounded by through holes, the disadvantage of US2002/0050380 is that applying solder resist and through holes would reduce the contact area between the thermal pad of the QFN chip and solder resist would generate void during the course of SMT procedure; i.e. US2002/0050380 cannot provide sufficient amount of solder paste and ensuring solder joint reliability for QFN chips. Thus, an improvement is required.

SUMMARY OF THE INVENTION

It is a major objective of the present invention to provide a printed circuit board having a copper clad laminate with a plurality of holes by which the contact yield of solder paste in the printed circuit board can be improved.

To achieve the above objective, the printed circuit board of the present invention includes a copper clad laminate and a plurality of holes. The copper clad laminate is used for dissipating heats generated from a chip. The copper clad laminate includes a plurality of solder paste disposed areas. The plurality of holes situate on the copper clad laminate. Each of the holes does not communicate with others, wherein the plurality of holes are nonconductors. Each of the solder paste disposed areas is surrounded by the plurality of holes and each of the solder paste disposed areas is surrounded by at least two holes.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Hereafter, the technical content of the present invention will be better understood with reference to preferred embodiments. Please refer toFIG. 1which is a schematic diagram of a printed circuit board in an embodiment of the present invention andFIGS. 2A to 2Dwhich show different representations regarding solder paste disposed areas surrounded by a plurality of holes.

As shown inFIG. 1, the printed circuit board1of the present invention includes a copper clad laminate10and a plurality of grooves20, wherein the plurality of grooves20situate on the copper clad laminate10, such that the copper clad laminate10can be mounted to a chip90through a Surface Mount Technology. In the present embodiment, the copper clad laminate10is a thermal plate of a QFN (Quad Flat No-leads) chip. The chip90is a QFN chip, but the present invention is not limited thereto. The chip90can also be other types of Bottom Termination Components. The grooves20are nonconductors, wherein each of the grooves20does not communicate with others.

As shown inFIG. 1, in the present embodiment, the copper clad laminate10includes a plurality of solder paste disposed areas11. The plurality of grooves20are dispersedly arranged around the plurality of solder paste disposed areas11. The plurality of solder paste disposed areas11are solder joints of thermal pads for the QFN (Quad Flat No-leads) chip. In the present embodiment, each of the solder paste disposed areas11are surrounded by at least two grooves20a.As shown inFIG. 1, each of the solder paste disposed areas11from a top view looks like a rectangle, and the grooves20are dispersed in each side of the rectangle. Each of the grooves20has a gap therebetween, such that the solder paste disposed areas11are in communication with the copper clad laminate10through the gap, but the present invention is not limited thereto. Actually, as shown inFIG. 2AtoFIG. 2D, the solder paste disposed areas11from a top view may look like any geometric shape, such as round, triangle, or polygonal shape. The plurality of grooves20are dispersed around the plurality of sides in the geometric shape, and each of the grooves20are not in communication with each other, such that the solder paste disposed areas11can be in communication with the copper clad laminate10through the gap. It should be noted here that the number of the solder paste disposed areas11in the present embodiment is 8, and the solder paste disposed areas11are arranged in parallel in four rows on the copper clad laminate10, but the present invention is not limited thereto. The number and arrangement of the solder paste disposed areas11vary depending on the design of the chip90. In addition, the shape of the grooves20is not particularly limited. The grooves20may be of other geometries, such as an arc shown as the grooves20ainFIG. 1.

Hereafter, please still refer toFIG. 1. Also refer toFIGS. 3A and 3Bwhich are cross sectional views before and after the printed circuit board being mounted to a chip.

As shown inFIGS. 3A and 3B, when the surface mount technology is processed, the solder paste80situates on the solder paste disposed areas11. Through the design that the grooves20situate on the copper clad laminate10, the solder paste80is limited onto the solder paste disposed areas11. The solder paste80will not collapse when heated, which increases the contact yield between the chip90and the copper clad laminate10when the solder paste80is in contact with the chip90. According to an embodiment of the present invention, when the surface mount technology is implemented, a fixture having a plurality of circular openings may be placed on the copper clad laminate10, where the circular openings correspond to the respective solder paste disposed areas11, to facilitate the placement of the solder paste80in the solder paste disposed areas11. The solder paste80is kept in a spherical shape as shown inFIGS. 3A and 3Bso that the solder paste80does not collapse when heated, and thus the contact yield between the chip90and the copper clad laminate10can be improved.

Please refer toFIG. 4, which is a schematic diagram of a printed circuit board in another embodiment of the present invention, andFIGS. 5 to 6, which present cross-sectional views of a printed circuit board according to another embodiment of the present invention and a cross sectional view of the printed circuit board according to another embodiment of the present invention with a QIN chip mounted on it.

As shown inFIG. 4,FIG. 5andFIG. 6, in the present embodiment, the printed circuit board1aof the present invention includes a copper clad laminate10aand a plurality of grooves20a.The copper clad laminate10a.includes a plurality of solder paste disposed areas11, a copper layer12and a laminate layer13. The laminate layer13is situated beneath the copper layer12and has at least one via hole131. As shown inFIG. 5andFIG. 6, the at least one via hole131is covered with copper and fulfilled with resin or copper such that the horizontal level of the opening of the at least one via hole131is equal to the top surface of the copper layer12. The reason for ensuring that the horizontal level of the opening of the at least one via hole131is equal to the top surface of the copper layer12is to increase the contact area between the copper layer12and the QFN chip90to overcome the defects of the prior art related to reliability issues caused by the inadequate contact area between the copper layer12and the QFN chip90.

As shown inFIG. 4andFIG. 5, the plurality of grooves20are situate on the copper layer12and each of the solder paste disposed areas11are surrounded by at least two of the grooves20a.The grooves20aare employed for allowing gas yielded during the SMT (surface mount technology) procedure to escape via the grooves20aand thus prevent the formation of voids. Further, the grooves20aalso are applied for increasing soldering temperature to ensure solder joint reliability and as shown inFIG. 5, a depth of the groove20aequals to or is less than the height of the copper layer12. For example, according to an embodiment of the present invention, when the copper layer12comprises 0.5 OZ copper metal, the height of the copper clad laminate10aand the depth of each of the grooves20awill be approximately larger than 1.4 mil and less than 2 mil. In addition, each of the grooves20adoes not communicate with any other and is separated by a gap. The gaps are employed for thermal relief and then heat is not trapped between the QFN chip90and the printed circuit board1. As shown inFIG. 5andFIG. 6, in the present embodiment, the height of the grooves20ais equal to the height of the copper layer12, and solder paste100is situated on the solder paste disposed area11. It is noted that the grooves20acan be circular, triangular, rectangular, or polygonal in shape.

The design of the grooves20,20anot only maintains a sufficient temperature during the course of the SMT procedure to prevent insufficient soldering but also maintains an adequate contact area for the copper layer12and the QFN chip90to protect the QFN chip90from overheating while the QFN chip90operates. Moreover, through the design that the grooves20,20asituate on the copper clad laminate10,10ain the present invention, the position of the solder paste80is limited to the solder paste disposed areas11, such that in the process of the surface mount technology to the printed circuit board1,1a,the amount of sufficient solder of the chip90is increased, and the contact yield between the chip90and the copper clad laminate10,10ais improved.

It should be noted that the described embodiments are only for illustrative and exemplary, and that various changes and modifications may be made to the described embodiments without departing from the scope of the invention as disposed by the appended claims.