Method for processing a wafer and method for dicing a wafer

In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.

TECHNICAL FIELD

Various embodiments relate generally to a method for processing a wafer, and a method for dicing a wafer.

BACKGROUND

Today, fabrication of semiconductor dies or chips commonly includes so-called dicing, i.e. separation of the individual dies or chips from a substrate, typically a wafer substrate or, short, wafer. In the production lines, dicing currently is achieved by means of mechanical sawing of the substrate. Recently, plasma dicing has appeared for the separation of the dies of a wafer, especially for dicing of very small chips on a wafer. Plasma dicing generally involves etching of the wafer.

However, during the etch process, metallizations provided on the wafer, such as, for example backside metallizations of the chips may be slightly etched or impurities may diffuse into the metallizations, metal material may be “kicked out” from the metallization during etching and contaminate the etch chamber, or an uncontrolled polymerization may occur, which may lead to changed etching rates and/or stability characteristics.

SUMMARY

In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.

DESCRIPTION

Note that in this specification, references to various features (e.g., region, layer, process, steps, stack, characteristics, material, etc.) included in “one aspect”, “one embodiment”, “example aspect”, “an aspect”, “another aspect”, “some aspect”, “various aspects”, “other aspects”, “alternative aspect”, and the like are intended to mean that any such features are included in one or more aspects of the present disclosure, but may or may not necessarily be combined in the same aspects. Various aspects of the disclosure are provided for methods, and various aspects of the disclosure are provided for devices or manufactures. It will be understood that basic properties of the methods also hold for the devices or manufactures and vice versa. Therefore, for sake of brevity, duplicate description of such properties may be omitted.

Note that in this specification, references to “at least one of” may mean any combination. For example, at least one of object A and object B may be object A, object B, or both objects A and B.

The word “over”, used herein to describe forming a feature, e.g. a layer, “over” a side or surface, may be used to mean that the feature, e.g. the layer may be formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.

Although the description is illustrated and described herein with reference to certain aspects, the description is not intended to be limited to the details shown. Modifications may be made in the details within the scope and range equivalents of the claims.

Wafers may commonly be used in the fabrication of integrated circuits (ICs) or chips. A wafer may include a plurality of die regions or integrally-formed dies. The die regions or dies may be separated by a separation process such as sawing. Separation of the dies may also be referred to as dicing.

Usually, dicing may be carried out along so-called dicing streets (sometimes also referred to as sawing streets or scribe lines) running between the dies and may result in the removal of the wafer material and/or destruction of any structures located in those dicing streets. The region of a wafer that will be affected (e.g. destroyed) by the dicing may also be referred to as a kerf region of the wafer.

Recently, plasma dicing has appeared for the separation of the dies of a wafer, especially for dicing of very small chips on a wafer. Plasma dicing generally involves etching of the wafer. However, during the etch process, metallizations provided on the wafer, such as, for example backside metallizations of the chips may be slightly etched or impurities may diffuse into the metallizations, metal material may be “kicked out” from the metallization during etching and contaminate the etch chamber, or an uncontrolled polymerization may occur, which may lead to changed etching rates and/or stability characteristics.

Various embodiments may provide methods for protecting a metallization (for example, one more surfaces of the metallization, e.g. a top surface and/or one or more sidewalls of the metallization) of a chip or wafer, for example a backside-metallization of a chip or wafer, during a plasma etching process, for example a plasma etching process used for dicing a wafer.

FIG. 1shows a schematic plan view of a wafer for illustrating various aspects of this disclosure. Wafer100may include a plurality of die regions101separated by kerf regions103located between the die regions101. The number of die regions101may be arbitrary. As shown inFIG. 1, the die regions101may have a quadratic shape, however the die regions101may also have a rectangular shape, or any other shape in general. As shown inFIG. 1, the die regions101may be arranged in a rectangular array, however the die regions101may also be arranged differently. As shown inFIG. 1, the wafer100may have a circular shape, however the wafer100may also have a rectangular or quadratic shape, or any other shape in general.

The term “kerf region” as used herein may be understood to refer to a region of a wafer that may be at least partially removed or destroyed in a die separation or dicing process. For example, in accordance with various aspects, the kerf region103shown inFIG. 1may illustratively include or correspond to one or more dicing streets or scribe lines of the wafer100(in other words, a line or lines along which the wafer100may be diced (e.g. cut, e.g. by means of sawing, laser cutting, or plasma etching)). In accordance with some aspects, the kerf region103may be located at least partially between the die regions101of the wafer100. The number of die regions of the wafer100may be arbitrary in accordance with various aspects.

The die region101or the plurality of die regions of the wafer100may have any shape, for example a quadratic or rectangular shape in accordance with some aspects, however any other shape may be possible as well in accordance with some aspects.

In accordance with some aspects, the die regions may be arranged in a rectangular array, e.g. similar to the array shown inFIG. 1. However, in accordance with other aspects, the die regions may be arranged differently.

FIG. 2shows a method200for processing a wafer in accordance with various embodiments. As shown in202, a wafer including at least one die region and at least one metallization disposed over the at least one die region may be provided. As shown in204, the at least one metallization may be covered with a protecting layer. As shown in206, the wafer may be plasma etched to form at least one die.

In accordance with an embodiment, the wafer may include or may be made of a semiconductor material such as, for example, silicon, although other semiconductor materials, including compound semiconductor materials, may be possible as well, for example germanium, silicon germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, a IV-IV compound semiconductor material, or others. Alternatively or in addition, the wafer may include other materials.

In accordance with another embodiment, the at least one metallization may have been formed by forming a metallization layer over the wafer and patterning the metallization layer.

In accordance with another embodiment, the at least one metallization may be disposed over a backside of the wafer.

In accordance with another embodiment, the at least one metallization may be disposed over a front side of the wafer.

In accordance with another embodiment, forming the metallization layer may include depositing the metallization layer over the wafer.

In accordance with another embodiment, patterning the metallization layer may include etching the metallization layer.

In accordance with another embodiment, patterning the metallization layer may include a lift-off process.

In accordance with another embodiment, the at least one metallization may include or may be made of at least one of copper, aluminum, gold, silver, tin, palladium, zinc, nickel, iron, titanium, or an alloy including at least one of the aforementioned materials. In accordance with another embodiment, other suitable materials may be used for the at least one metallization.

In accordance with another embodiment, the at least one metallization may include a layer stack including one or more layers including or being made of at least one of the aforementioned materials.

In accordance with another embodiment, covering the at least one metallization with the protecting layer may include depositing the protecting layer over the wafer, and patterning the protecting layer such that the at least one metallization is encapsulated by the patterned protecting layer.

In accordance with another embodiment, the protecting layer may include or may be made of a resist material or an imide material (e.g. polyimide material).

In accordance with another embodiment, the resist material may include or be, for example, a photoresist, e.g. an organic photo resist.

In accordance with another embodiment, the protecting layer may include or be made of a hard mask material such as, for example, an oxide material, for example silicon oxide, and/or a nitride material, as e.g. silicon nitride, and/or other suitable hardmask materials.

In accordance with another embodiment, the protecting layer may include a layer stack including an oxide layer and a nitride layer.

In accordance with another embodiment, covering the at least one metallization with a protecting layer may include depositing a first protecting sub-layer to cover a surface of the at least one metallization that faces away from the wafer, depositing a second protecting sub-layer to cover the first protecting sub-layer and at least one sidewall of the at least one metallization, etching the second protecting sub-layer to form at least one spacer covering the at least one sidewall of the at least one metallization.

In accordance with another embodiment, covering the at least one metallization with a protecting layer may include depositing a first protecting sub-layer to cover a surface of the at least one metallization that faces away from the wafer, depositing a second protecting sub-layer to cover the first protecting sub-layer and sidewalls of the at least one metallization, etching the second protecting sub-layer to form spacers covering the sidewalls of the at least one metallization.

In accordance with another embodiment, at least one of the first protecting sub-layer and the second protecting sub-layer may include or consist of a nitride material or an oxide material.

In accordance with another embodiment, the plasma etching may include or may be achieved by a so-called Bosch plasma etching process, which is described, as such, for example in Laermer et al., “Method of anisotropically etching silicon” (U.S. Pat. No. 5,501,893).

In accordance with an embodiment, a Bosch plasma etching process may include: forming a hole, e.g. a channel, in a carrier (for example, a semiconductor or wafer) including at least one die, wherein forming a hole may include selectively removing carrier material, thereby forming a cavity in the carrier by removing carrier material by forming a mask, e.g. a photo-structured resist mask, over the carrier and etching the carrier using the mask (e.g. the resist mask) as an etch mask; forming a passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material by plasma etching, wherein, during etching, chemically reactive species and/or ions may be generated by electrical discharge in a reactive gas atmosphere; repeatedly alternating between the process of forming passivation material and the process of selectively etching the passivation material and further carrier material until a desired hole depth is formed in the carrier.

In accordance with another embodiment, patterning the protecting layer may include or may be achieved by a photolithography process.

In accordance with another embodiment, the method200for processing a wafer may include removing the protecting layer after plasma etching the wafer, for example by means of resist etching or ashing (e.g. in case of a resist material), or by means of etching (e.g. in case of a hard mask material such as a nitride or oxide material) or by means of any other suitable method.

In accordance with another embodiment, plasma etching the wafer may include plasma etching at least one kerf region of the wafer, for example at least one kerf region of the wafer proximate to the at least one die region of the wafer.

In accordance with another embodiment, patterning the metallization layer may include exposing the at least one kerf region (e.g. the at least one kerf region proximate the at least one die region). In other words, patterning the metallization layer may include removing the metallization layer from above the at least one kerf region.

In accordance with another embodiment, plasma etching the wafer may include dicing the wafer.

In accordance with another embodiment, the method200may further include grinding the wafer, for example before plasma etching the wafer, or after plasma etching the wafer.

FIG. 3shows a method300for processing a wafer in accordance with various embodiments. As shown in302, a wafer including a plurality of die regions, a plurality of kerf regions, and a plurality of metallizations disposed over the plurality of die regions, may be provided. A protecting layer may be deposited over the wafer, as shown in304. As shown in306, the protecting layer may be patterned such that the plurality of metallizations is encapsulated by the patterned protecting layer. The plurality of kerf regions of the wafer may be plasma etched to form a plurality of dies, as shown in308. As shown in310, the protecting layer may be removed after plasma etching the plurality of kerf regions of the wafer.

In accordance with an embodiment, the wafer may include or may be made of a semiconductor material such as, for example, silicon, although other semiconductor materials, including compound semiconductor materials, may be possible as well, for example germanium, silicon germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, a IV-IV compound semiconductor material, or others. Alternatively or in addition, the wafer may include other materials.

In accordance with another embodiment, the plurality of metallizations may have been formed by forming a metallization layer over the wafer and patterning the metallization layer.

In accordance with another embodiment, the plurality of metallizations may be disposed over a backside of the wafer.

In accordance with another embodiment, the plurality of metallizations may be disposed over a front side of the wafer.

In accordance with another embodiment, forming the metallization layer may include depositing the metallization layer over the wafer.

In accordance with another embodiment, patterning the metallization layer may include etching the metallization layer.

In accordance with another embodiment, patterning the metallization layer may include a lift-off process.

In accordance with another embodiment, the plurality of metallizations may include or may be made of at least one of copper, aluminum, gold, silver, tin, palladium, zinc, nickel, iron, titanium, or an alloy including at least one of the aforementioned materials. In accordance with another embodiment, other suitable materials may be used for the plurality of metallizations.

In accordance with another embodiment, the plurality of metallizations may include a layer stack including one or more layers including or being made of at least one of the aforementioned materials.

In accordance with another embodiment, patterning the metallization layer may include exposing the plurality of kerf regions. In other words, patterning the metallization layer may include removing the metallization layer from above the plurality of kerf regions.

In accordance with another embodiment, the protecting layer may include or may be made of a resist material or an imide material (e.g. polyimide material).

In accordance with another embodiment, the resist material may include or be, for example, a photoresist, e.g. organic photo resist.

In accordance with another embodiment, the protecting layer may include or may be made of a hardmask material such as e.g. an oxide material and/or a nitride material.

In accordance with another embodiment, the oxide material may include or be, e.g. silicon oxide.

In accordance with another embodiment, the nitride material may include or be, e.g. silicon nitride.

In accordance with another embodiment, the protecting layer may include a layer stack including an oxide layer and a nitride layer.

In accordance with another embodiment, depositing the protecting layer over the wafer may include depositing a first protecting sub-layer to cover surfaces of the plurality of metallizations that face away from the wafer, depositing a second protecting sub-layer to cover the first protecting sub-layer and sidewalls of the plurality of metallizations, etching the second protecting sub-layer to form spacers covering the sidewalls of the plurality of metallizations.

In accordance with another embodiment, at least one of the first protecting sub-layer and the second protecting sub-layer may include or consist of a hardmask material such as e.g. a nitride material or an oxide material.

In accordance with another embodiment, the plasma etching may include or may be achieved by a Bosch plasma etching process.

In accordance with another embodiment, patterning the protecting layer may include or may be achieved by a photolithography process.

In accordance with another embodiment, plasma etching the plurality of kerf regions of the wafer may include dicing the wafer.

In accordance with another embodiment, the method300may further include grinding the wafer, for example before plasma etching the plurality of kerf regions of the wafer, or after plasma etching the plurality of kerf regions of the wafer.

FIG. 4shows a method400for dicing a wafer in accordance with various embodiments. As shown in402, at least one backside metallization disposed over at least one die region of a wafer may be encapsulated with a protecting layer. The wafer may be diced by means of a plasma etch process, wherein the at least one backside metallization may be protected by the protecting layer, as shown in404.

In accordance with an embodiment, the wafer may include or may be made of a semiconductor material such as, for example, silicon, although other semiconductor materials, including compound semiconductor materials, may be possible as well, for example germanium, silicon germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, a IV-IV compound semiconductor material, or others. Alternatively or in addition, the wafer may include other materials.

In accordance with another embodiment, the at least one backside metallization may have been formed by depositing a metallization layer over the wafer and patterning the metallization layer, e.g. by etching the metallization layer, or by means of a lift-off process.

In accordance with another embodiment, the at least one backside metallization may include or may be made of at least one of copper, aluminum, gold, silver, tin, palladium, zinc, nickel, iron, titanium, or an alloy including at least one of the aforementioned materials. In accordance with another embodiment, other suitable materials may be used for the at least one backside metallization.

In accordance with another embodiment, the at least one backside metallization may include a layer stack including one or more layers including or being made of at least one of the aforementioned materials.

In accordance with another embodiment, encapsulating the at least one backside metallization may include depositing the protecting layer over the at least one backside metallization, and patterning the protecting layer.

In accordance with another embodiment, the protecting layer may include or may be made of a resist material or an imide material (e.g. polyimide material).

In accordance with another embodiment, the resist material may include or be, for example, a photoresist, e.g. an organic photo resist.

In accordance with another embodiment, the protecting layer may include or may be made of a hardmask material such as e.g. an oxide material and/or a nitride material.

In accordance with another embodiment, the oxide material may include or be, silicon oxide.

In accordance with another embodiment, the nitride material may include or be, silicon nitride.

In accordance with another embodiment, the protecting layer may include a layer stack including an oxide layer and a nitride layer.

In accordance with another embodiment, depositing the protecting layer over the wafer may include depositing a first protecting sub-layer to cover a surface of the at least one backside metallization that faces away from the wafer, depositing a second protecting sub-layer to cover the first protecting sub-layer and at least one sidewall of the at least one backside metallization, etching the second protecting sub-layer to form at least one spacer covering the at least one sidewall of the at least one backside metallization.

In accordance with another embodiment, at least one of the first protecting sub-layer and the second protecting sub-layer may include or consist of a hardmask material such as e.g. a nitride material or an oxide material.

In accordance with another embodiment, the plasma etch process may include or may be a Bosch plasma etch process.

In accordance with another embodiment, patterning the protecting layer may include or may be achieved by a photolithography process.

In accordance with another embodiment, dicing the wafer may include plasma etching at least one kerf region of the wafer, for example at least one kerf region of the wafer proximate to the at least one die region of the wafer.

In accordance with another embodiment, patterning the metallization layer may include exposing the at least one kerf region of the wafer proximate to the at least one die region. In other words, patterning the metallization layer may include removing the metallization layer from above the at least one kerf region.

In accordance with another embodiment, dicing the wafer may include plasma etching a plurality of kerf regions of the wafer, each kerf region of the plurality of kerf regions being proximate to one or more die regions of a plurality of die regions of the wafer.

In accordance with another embodiment, the method400may further include grinding the wafer, for example before dicing the wafer.

FIG. 5AtoFIG. 5Dshow schematic cross-sectional views illustrating a method for processing a wafer in accordance with an embodiment.

Referring toFIG. 5A, a wafer504including at least one die region506and at least one kerf region508proximate to the at least one die region506may be provided, e.g. on a carrier502. At least one metallization (or metallization structure)510may be disposed over the at least one die region506of the wafer504. The at least one metallization510may have been formed, for example, by depositing a metallization material over a surface504aof the wafer504, e.g. a surface504athat faces away from the carrier502, and patterning the metallization material such that the at least one metallization510is formed over the at least one die region506of the wafer504. For example, a plurality of metallizations510may have been formed, wherein each metallization510may have been formed over a respective die region506of a plurality of die regions506of the wafer504.

As shown inFIG. 5A, a protecting layer512may be formed by depositing a protecting material over the wafer504having the at least one metallization510over the at least one die region506of the wafer504, such that the protecting layer512covers a surface510aof the at least one metallization510facing away from the wafer504, sidewalls518of the metallization510, and at least one portion520of the surface504aof the wafer504over the at least one kerf region508. For example, the wafer504may include a plurality of kerf regions508, wherein each kerf region508may be located proximate or adjacent to one or more die regions506of a plurality of die regions506of the wafer504, for example between two or more neighboring die regions506of the plurality of die regions506.

Referring toFIG. 5B, the protecting layer512may be patterned such that remaining material of the protecting layer512encapsulates the at least one metallization510over the surface504aof the wafer504, while material of the protecting layer512previously covering the at least one portion520of the surface504aof the wafer504over the at least one kerf region508may be removed again from above the at least one kerf region508, such that the at least one kerf region508of the wafer504may be exposed.

According to the embodiment shown inFIG. 5B, the protecting layer512may include or consist of a resist material, e.g. a photoresist. In case of a photoresist, patterning the protecting layer512may, for example, include or be achieved by a photolithography process, which may include exposing the photoresist (e.g. using a photolithography mask) and developing the photoresist to obtain the patterned protecting layer512.

Alternatively, the protecting layer512may be patterned using other suitable processes, which may be known as such in the art.

In accordance with another embodiment, the protecting layer512may include or be made of a hard mask material such as, for example, an oxide material, for example silicon oxide, and/or a nitride material, as e.g. silicon nitride, and/or other suitable hardmask materials.

Referring toFIG. 5C, the wafer504may be etched by using a plasma etching process, e.g. a Bosch plasma etching process (alternatively, other plasma etching processes), for example by etching the wafer material in the at least one kerf region508to form at least one die (or chip)516. As shown, the at least one die516may include the at least one die region506, and the at least one metallization510disposed over the at least one die region506and encapsulated by the remaining material of the protecting layer512.

Referring toFIG. 5D, the remaining material of the protecting layer512ofFIG. 5Cencapsulating the at least one metallization510over the at least one die516may be removed to leave at least one separated single die or chip516including a metallization510on the carrier502, for example by etching or other suitable methods.

According to the embodiment shown inFIG. 5D, after removing the remaining material of the protecting layer512, the metallization510may be recessed or may have a recess with respect to the die or chip516, wherein for example a step522may become apparent between the edge of the die516and the sidewall518of the metallization510.

FIG. 6AtoFIG. 6Dshow schematic cross-sectional views illustrating a method for processing a wafer in accordance with an embodiment.

Referring toFIG. 6A, a wafer604including at least one die region606and at least one kerf region608proximate to the at least one die region606may be provided, e.g. on a carrier602. At least one metallization (or metallization structure)610may be disposed over the at least one die region606of the wafer604. The at least one metallization610may have been formed, for example, by depositing a metallization material over a surface604aof the wafer604, e.g. a surface604athat faces away from the carrier602. The metallization material may have been patterned, such that the at least one metallization610is formed over the at least one die region606of the wafer604. For example, a plurality of metallizations610may have been formed, wherein each metallization610is formed over a respective die region606of a plurality of die regions606of the wafer604.

As shown inFIG. 6A, a protecting layer612may be formed by depositing a protecting material over the wafer604having the at least one metallization610over the at least one die region606of the wafer604, such that the protecting layer612covers a surface610aof the at least one metallization610facing away from the wafer604, sidewalls618of the at least one metallization610, and at least one portion620of the surface604aof the wafer604over the at least one kerf region608. For example, the wafer604may include a plurality of kerf regions608, wherein each kerf region608may be located proximate or adjacent to a one or more die regions606of a plurality of die regions606of the wafer604, for example between two or more neighboring die regions606of the plurality of die regions606.

According to the embodiment shown inFIG. 6A, the protecting material used for forming the protecting layer612may include or consist of a hardmask material such as a nitride material, such as e.g. silicon nitride, and/or an oxide material, such as e.g. silicon oxide.

Further referring toFIG. 6A, a mask layer614may be formed over the wafer604having the protecting layer612over the at least one metallization610over the at least one die region606of the wafer604, for example by depositing a resist material (e.g. a photoresist), such that the surface of the protecting layer612deposited over the wafer604is covered by the mask layer614.

Referring toFIG. 6B, the mask layer614may be patterned such that remaining material of the mask layer614covers at least one portion of the protecting layer612that covers the surface610aof the at least one metallization610facing away from the wafer604, and at least one portion of the protecting layer612that covers the sidewalls618of the at least one metallization610, while material of the mask layer614previously covering at least one portion of the protecting layer612that covers the at least one portion620of the surface604aof the wafer604over the at least one kerf region608may be removed again from above the protecting layer612such that the at least one portion of the protecting layer612that covers the at least one portion620of the surface604aof the wafer604over the at least one kerf region608of the wafer604may be exposed.

According to the embodiment shown inFIG. 6B, the mask layer614may include or consist of a resist material, e.g. a photoresist. In case of a photoresist, patterning the mask layer614may, for example, include or be achieved by a photolithography process, which may include exposing the photoresist (e.g. using a photolithography mask) and developing the photoresist to obtain the patterned mask layer614.

Alternatively, the mask layer614may be patterned using other suitable processes, which may be known as such in the art.

Referring toFIG. 6C, the at least one portion of the protecting layer612covering the at least one portion620of the surface604aof the wafer604over the kerf region608may be removed using the patterned mask layer614, such that the at least one portion620of the surface604aof the wafer604over the at least one kerf region608is exposed again, for example between a plurality of metallizations610.

According to the embodiment shown inFIG. 6C, removing the protecting layer612covering the at least one portion620of the surface604aof the wafer604over the kerf region608may include or may be effected by etching, alternatively using other suitable methods.

Referring toFIG. 6D, the patterned mask layer614may be removed, for example by etching or other suitable methods, to leave the patterned protecting layer612over the at least one metallization610.

Referring toFIG. 6E, the wafer604may be etched by using a plasma etching process, e.g. a Bosch plasma etching process (alternatively, other plasma etching processes), for example by etching the wafer material in the at least one kerf region608to form at least one die (or chip)616. As shown, the at least one die616may include the at least one die region606, and the at least one metallization610disposed over the at least one die region606and encapsulated by the remaining material of the protecting layer612.

Referring toFIG. 6F, the patterned protecting layer612ofFIG. 6Eencapsulating the at least one metallization610over the at least one die or chip616may be removed to leave at least one separated single die or chip616including a metallization610on the carrier602, for example by etching or other suitable methods.

According to the embodiment shown inFIG. 6F, after removing the remaining material of the protecting layer612, the metallization610may be recessed or may have a recess with respect to the die or chip616, wherein a step622may become apparent between the edge of the die616and the sidewall618of the metallization610.

Various embodiments may provide a wafer including at least one die region, at least one metallization disposed over the at least one die region, and at least one protecting layer covering the at least one metallization. The at least one protecting layer may encapsulate the at least one metallization. The at least one protecting layer may be configured to protect the at least one metallization during plasma etching, for example during plasma dicing, as described herein above. The at least one protecting layer may be configured in accordance with one or more embodiments described herein above. For example, the at least one protecting layer may include or be made of a resist material (e.g. photoresist), or a hardmask material (e.g. an oxide material and/or nitride material).