Image sensor including active pixel sensor array with photoelectric conversion region

In one aspect, an image sensor is provided which includes an array of unit active pixels. Each of the unit active pixels comprises a first active area including a plurality of photoelectric conversion regions, and a second active area separated from the first active area. The first active areas are arranged in rows and columns so as to define row and column extending spacings there between, and the second active areas are located at respective intersections of the row and column extending spacings defined between the first active areas.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to image sensors. More particularly, the present invention relates to active pixel sensors in which the read-out circuitry thereof is shared by two or more sensor elements.

A claim of priority is made to Korean patent application nos. 2005-61968 and 2005-68102, filed Jul. 9, 2005, and Jul. 26, 2005, respectively, the contents of which are incorporated by reference herein in their entireties.

2. Description of the Related Art

Certain types of image sensors utilize photo detectors to capture incident light and convert the light to an electric charge capable of image processing. Examples include Complimentary Metal Oxide Semiconductor (CMOS) image sensors (CIS). CIS devices are generally characterized by analog sensing circuits coupled to CMOS control circuits. The analog sensing circuits include an array of photo detectors having access devices (e.g., transistors) for connection to word lines and bit lines. The CMOS control circuits may include a timing generator and a variety of image processing circuits, such as row decoders, column decoders, column amplifiers, output amplifiers, and so on. Generally speaking, the configuration of the CIS device is analogous to that of a CMOS memory device.

FIG. 1is a block diagram of an example of a CMOS image sensor (CIS). The CMOS image sensor ofFIG. 1generally includes an active pixel sensor (APS) array10, a timing generator20, a row decoder30, a row driver40, a correlated double sampling and digital converting (CDS) circuit50, an analog to digital converter (ADC)60, a latch circuit70, and a column decoder80.

Those of ordinary skill are well-acquainted with the operation of the CIS represented inFIG. 1, and a detailed description thereof is therefore omitted here. Generally, however, the timing generator20controls the operational timing of the row decoder30and column decoder80. The row driver40is responsive to the row decoder30to selectively activate rows of the active pixel array10. The CDS50and ADC60are responsive to the column decoder80and latch circuit70to sample and output column voltages of the active pixel array10. In this example, image data is output from the latch circuit70.

The APS array10contains a plurality of active unit pixels arranged in rows and columns. Each active unit pixel includes a photoelectric conversion device and readout circuitry for transferring charges of the photoelectric conversion device to an output line.

Reference is now made toFIG. 2which is an equivalent circuit diagram of an example of an active pixel22of the APS array10shown inFIG. 2.

A photoelectric conversion element PD (e.g., a photo-diode, a photo-gate type image element, etc.) of the active pixel22captures incident light and converts the captured light into an electric charge. The electric charge is selectively transferred from the photoelectric conversion element PD to a floating diffusion region FD via a transfer transistor TX. The transfer transistor TX is controlled by a transfer gate TG signal. The floating diffusion region FD is connected to the gate of a drive transistor Dx which functions as a source follower (amplifier) for buffering an output voltage. The output voltage is selectively transferred as an output voltage OUT by a select transistor Sx. The select transistor Sx is controlled by a row select signal SEL applied to the gate of the select transistor Sx. Finally, a reset transistor Rx is controlled by a reset signal RS to selectively reset charges accumulated in the floating diffusion region FD to a reference voltage level.

It is noted that one or more of the transistors shown inFIG. 2may be optionally omitted. For example, the floating diffusion region FD may be electrically connected to the photoelectric conversion element PD, in which case the transfer transistor TX may be omitted. As another example, the drive transistor Dx may be electrically connected to the output line OUT, in which case the selection transistor Sx may be omitted.

In an effort to increase pixel density, it is known to configure CIS devices such that the unit active pixels thereof each contain multiple photoelectric conversion elements PD which share common readout circuitry. However, conventional shared pixel CIS configurations and layouts suffer drawbacks in that the photoelectric conversion elements PD are defined by relatively small light photoelectric conversion areas. In addition, the photoelectric conversion areas are separated from one another at unequal pitches in row and/or column directions. Thus, the conversion efficiency and/or image quality of these CIS devices adversely impacted.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, an image sensor is provided which includes an active pixel array including a plurality of unit pixels located on a substrate. Each of the unit pixels comprises at least one first active area of the substrate, and second and third active areas of the substrate which are separated from each other and from the at least one first active area. The at least one first active area includes four photoelectric conversion regions.

According to another aspect of the present invention, an image sensor is provided which include an active pixel array including a plurality of unit active pixels formed on a substrate. A first unit pixel includes at least one first active area of the substrate, and second and third active areas of the substrate which are separated from each other and from the at least one first active area, where the at least one first active area includes four photoelectric conversion regions aligned in a first direction. A second unit pixel includes at least one fourth active area of the substrate, and fifth and sixth active areas of the substrate which are separated from each other and from the at least one fourth active area, where the at least one fourth active area includes four photoelectric conversion regions aligned parallel to the first direction and adjacent the four photoelectric conversion regions of the first unit pixel, respectively.

According to still another aspect of the present invention, an image sensor is provided which includes an active pixel array including an array of unit active pixels. Each of the unit active pixels includes at least one first active area and an elongate second and third active areas in a substrate, and the at least one first active area includes a four photoelectric conversion regions aligned in a first direction. The elongate second and third active areas are separated from the first active area and extend lengthwise in the first direction.

According to yet another aspect of the present invention, a system is provided which includes a processor, a memory and an image sensor connected to a data bus. The image sensor includes an active pixel array in which readout circuitry is shared by at least four photoelectric conversion regions for each unit active pixel of the active pixel array, and in which a pitch between adjacent photoelectric conversion regions is substantially the same in column and row directions of the active pixel array.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described by way of several preferred but non-limiting embodiments.

FIG. 3is a circuit diagram illustrating a shared four-pixel active pixel array (APS) according to a non-limiting embodiment of the present invention. Herein, the phrase “shared four-pixel APS” means that four photoelectric conversion elements of the APS share the same read-out circuitry. Each set of four photoelectric conversion elements and their associated read-out circuitry are referred to herein as a “unit active pixel”.

Referring toFIG. 3, the shared four-pixel APS includes a plurality of unit active pixels P arranged in rows (i, i+1, . . . ) and columns (j, j+1, j+2, j+3, . . . ). Each of the unit active pixels P is similarly configured, and accordingly, only the unit active pixel P(i, j+1) is described below.

The unit active pixel P(i, j+1) includes a set11of four photoelectric conversion elements11a,11b,11cand11d, a set15of four transfer transistors15a,15b,15cand15d, and a common floating diffusion region13. As shown inFIG. 3, the transfer transistor15aand the photoelectric conversion element11aare connected in series between the floating diffusion region13and a reference potential (e.g., ground). The transfer transistor15band the photoelectric conversion element11bare connected in series between the floating diffusion region13and the reference potential (e.g., ground). The transfer transistor15cand the photoelectric conversion element11care connected in series between the floating diffusion region13and the reference potential (e.g., ground). The transfer transistor15dand the photoelectric conversion element11dare connected in series between the floating diffusion region13and the reference potential (e.g., ground).

The transfer transistor15ais gated to and controlled by a transfer gate line TX(i)a connected to each of the unit active pixels P of the row (i). The transfer gate15bis gated to and controlled by a transfer gate line TX(i)b connected to each of the unit active pixels P of the row (i). The transfer gate15cis gated to and controlled by a transfer gate line TX(i)c connected to each of the unit active pixels P of the row (i). The transfer gate15dis gated to and controlled by a transfer gate line TX(i)d connected to each of the unit active pixels P of the row (i).

The floating diffusion region13is connected to the gate of a drive transistor17, and the drive transistor17and a select transistor19are connected in series between a reference voltage (e.g., Vdd) and an output line Vout. The select transistor19is gated to and controlled by a select line SEL(i) connected to each of the unit active pixels P of the row (i). A reset transistor18is connected between the reference voltage (e.g. Vdd) and the floating diffusion region13, and is gated to and controlled by a reset line RX(i) connected to each of the unit active pixels P of the row (i).

In operation, the photoelectric conversion elements11athrough11dof the unit active pixel P(i, j+1) capture incident light and convert the captured light into an electric charge. The photoelectric conversion elements11athrough11dmay optionally be implemented by photo-diodes or photo-gate type image elements, although other types of photoelectric conversion devices may be utilized. Under control of the transfer gate lines TX(i)a through TX(i)d, the electric charges are selectively transferred from the photoelectric conversion elements11athrough11dto the floating diffusion region13via the transfer transistors15athrough15d, respectively.

The drive transistor17connected to the floating diffusion region13functions as a source follower (amplifier) for buffering an output voltage. The select transistor19is responsive to the select line SEL(i) to selectively transfer the output voltage to the output line Vout. Finally, the reset transistor18is controlled by a reset line RX(i) to selectively reset (or bias) charges accumulated in the floating diffusion region13to the reference voltage level (e.g., Vdd).

FIG. 4is a top view illustrating the layout of active regions areas and transistor gates of a unit active pixel according to an embodiment of the present invention.

Referring toFIG. 4, each unit active pixel includes four (4) area patterns A1through A4located at the surface of a semiconductor substrate. The non-active area of the substrate may, for example, be insulating regions such as shallow trench isolation (STI) regions or local oxidation of silicon (LOCOS) regions. Alternately, the non-active areas of the substrate may, for example, be junction isolation regions such as highly counter-doped impurity regions.

The first active area pattern A1of this example contains two photoelectric conversion element regions PD1and PD2, a floating diffusion region FD, transfer gates TG1and TG2, and a reset gate RG. The photoelectric conversion regions PD1and PD2correspond to the photo conversion elements11aand11bofFIG. 3, the floating diffusion region FD corresponds to the floating diffusion region13ofFIG. 3, the transfer gates TG1and TG2correspond to gates of the transfer transistors15aand15bofFIG. 3, and the reset gate RG corresponds to the gate of the reset transistor18ofFIG. 3.

The second active area pattern A2of this example contains two photoelectric conversion element regions PD3and PD4, a floating diffusion region FD, transfer gates TG3and TG4, and a dummy gate DG. The photoelectric conversion regions PD3and PD4correspond to the photo conversion elements11cand11dofFIG. 3, the floating diffusion region FD corresponds to the floating diffusion region13ofFIG. 3, and the transfer gates TG3and TG4correspond to gates of the transfer transistors15cand15dofFIG. 3.

The floating diffusion region13of the first active area pattern A1is electrically connected to the floating diffusion region FD of the second active area pattern A2by wiring (known shown). The dummy gate DG is optionally provided to match the gate patterning layout of the first active area pattern A1.

The third active area pattern A3contains a source follower gate SFG, and the fourth active area pattern A4contains a row select gate RSG. The row select gate RSG corresponds to the gate of the select transistor19ofFIG. 3, and the source follower gate SFG corresponds to the gate of the drive transistor17ofFIG. 3.

Still referring toFIG. 4, the first active area pattern A1includes two vertically aligned active area portions a11and a12which respectively contain the photoelectric conversion elements PD1and PD2. For explanation purposes, the vertical direction is defined by the dashed line “x” ofFIG. 4, and is coincident with the column direction of the APS array shown inFIG. 3. Each of the active area portions a11and a12have multi-faceted polygonal outer peripheries. These outer peripheries are intended to approximate a circular shape in order to conform as closely as possible to the configuration of micro-lenses (not shown) positioned over the photoelectric conversion regions PD1and PD2. Also, in the example of this embodiment, the active area portions a11and a12are separated by a local spacing SL and define substantially mirror images of one another about a horizontal axis centered there between. The horizontal direction is parallel to the dashed line “y” inFIG. 4and is parallel to the row direction ofFIG. 3.

The active area portions a11and a12are connected at opposing corners by an active area portion c1of the first active area pattern A1. As shown, the active area portion c2contains at least a portion of the floating diffusion region FD. A transfer gate channel region is defined within the active area portions a11and/or c1below the first transfer gate TG1, and another transfer gate channel region is defined within the active area portions a12and/or c1below the second transfer gate TG2.

The remaining corners of the active area portions a11and a12(i.e., the corners not connected to the active area portion c) include notched or indented peripheral portions to allow for close proximity placement of portions of adjacent unit active pixels. This aspect of the embodiment will be explained in more detail later with reference toFIG. 5.

Still referring toFIG. 4, the first active area pattern A1also includes an active area extension portion b which extends outwardly in the horizontal direction from the active area portion c1. A reset gate channel region is defined within the active regions areas portions c1and/or b below the reset gate RG. Although not shown, the active area extension portion b may be connected to a reference potential (e.g., Vdd).

The second active area pattern A2includes two vertically aligned active area portions a21and a22which respectively contain the photoelectric conversion elements PD3and PD4. Again, the vertical direction is defined by the dashed line “x” ofFIG. 4, and is coincident with the column direction of the APS array shown inFIG. 3. Each of the active area portions a21and a22have multi-faceted polygonal outer peripheries which are intended to approximate a circular shape. The active area portions a21and a22are separated by the local spacing SL and define substantially mirror images of one another about a horizontal axis (parallel with the “y” or row direction) centered there between.

The active area portions a21and a22are connected at opposing corners by an active area portion c2of the second active area pattern A2. As shown, the active area portion c2contains at least a portion of the floating diffusion region FD. A transfer gate channel region is defined within the active area portions a21and/or c2below the first transfer gate TG3, and another transfer gate channel region is defined within the active area portions a22and/or c2below the second transfer gate TG4.

The remaining corners of the active area portions a21and a22(i.e., the corners not connected to the active area portion c2) include notched or indented peripheral portions to allow for close proximity placement of portions of adjacent unit active pixels. Again, this aspect of the embodiment will be explained in more detail later with reference toFIG. 5.

The first and second active area patterns A1and A2are separated by an active pixel spacing SAP and define substantially mirror images of one another about a horizontal axis (parallel with the “y” or row direction) centered there between. Preferably, referring toFIG. 4, the active pixel spacing SAP is substantially the same as the local spacing SL.

As shown inFIG. 4, the third active area pattern A3is elongate in the vertical direction and is spaced from and between the first and second active area patterns A1and A2adjacent the respective lower and upper corners thereof. Also, in this example, the left-side of the third active area pattern A3is substantially aligned vertically with the rights sides of the active area portions a11through a22.

The fourth active area pattern A4is also elongate in the vertical direction and spaced from the second active area pattern A2adjacent the lower corner thereof. In the example, the left-side of the third active area pattern A4is substantially aligned vertically with the rights sides of the active area portions a1through a22.

It is noted that the floating diffusion region FD is an example of a readout storage node region which is utilized to readout the charges accumulated by the photoelectric conversion element regions PD1through PD4. However, the invention is not limited to the use of floating diffusion regions, and other types of readout storage node regions may instead be implemented.

Further, the embodiment ofFIG. 3is intended to realize the circuit configuration ofFIG. 2. However, the invention is not limited in this respect, and other circuit configurations may instead be implemented.

Still further, the active areas A1and A2may be combined into a single area region so long as the photoelectric conversion regions PD1through PD4remain electrically isolated from one another. This may be achieved, for example, by impurity regions formed in the active area.

FIG. 5illustrates an array of the active area patterns shown inFIG. 4.

Referring collectively toFIGS. 4 and 5, the active area patterns A1/A2are vertically aligned in columns and horizontally aligned in rows. The distance between adjacent active area patterns A1/A2within the same row is defined herein as a column spacing SC. The distance between adjacent active area patterns A1/A2within the same column is defined herein as a row spacing SR. Also, as previously mentioned, the spacing between the active area portions A1and A2is defined herein as the active pixel spacing SAP, and the spacing between the active area portions a11and a12(and a21and a22) is defined herein as a local spacing SL.

The third active area patterns A3are located at the intersections of the active pixel spacings SAP and the column spacings SC. Further, the third active area patterns A3extend lengthwise in a direction of the column spacings SC. As mentioned above, and as shown inFIG. 5, the corners of the first and second active area patterns A1and A3are notched or indented to allow sufficient space for placement of the third active area patterns A3.

The fourth active area patterns A4are located at the intersections of the row spacings SR and the column spacings SC. Further, the fourth active area patterns A4extend lengthwise in a direction of the column spacings SC. Again and as shown inFIG. 5, the corners of the first and second active area patterns A1and A3are notched or indented to allow sufficient space for placement of the fourth active area patterns A4.

Preferably, the widths of the column spacings SC, row spacings SR, the active pixel spacings SAP and local spacings SL are all the same. Also, the width of each of the third and fourth active pattern areas A3and A4is preferably the same as and coincident with the width of each column spacing SC.

Within each row, the active area portion b of each active area pattern A1extends beyond the column spacing SC and between the active area portions a11and a12of an adjacent active area pattern A1. Again, the corners of the active area portions a11and a12of the active area patterns A1are notched or indented to allow sufficient space for placement of the active area extension portion b of an adjacent active area pattern A1.

The configuration of the example illustrated inFIGS. 4 and 5offers a number of advantages. For example, the column pitch P1and row pitch P2between centers PC of the photoelectric conversion regions PD can be easily equalized by appropriate design of the column spacing SC, row spacing SR, active pixel spacing SAP and local spacing SL. Further, pixel density is enhanced (i.e., the pitch is reduced) by extending the portion b of each active area pattern A1between the portions a11and a12of an adjacent active area pattern A1in the same row. Also, pixel density is further enhanced by positioning the active area patterns A2lengthwise in the column spacings SC.

The invention is not limited to the specific example ofFIGS. 4 and 5. As one example only, the reset gate RG can be placed in the third active area pattern A3rather than the first active area pattern A1. Also, the outer peripheries of the active area patterns A1and A2need not be the same as those illustrated in the examples ofFIGS. 4 and 5. As one skilled in the art will appreciate, other variations are possible without departing from the spirit and scope of the invention.

Attention is now directed toFIG. 6which illustrates a blocking pattern M positioned over the array ofFIG. 5. Referring collectively toFIGS. 4 through 6, the blocking pattern M defines a plurality of optical apertures165aligned over the portions a11through a22of the first and second active area patterns A1and A2. The blocking pattern M may be formed of, for example, an aluminum or copper layer, and functions to block light from being incident on the floating diffusion regions FD and the read-out circuitry (TG1, TG2, RG, RSG and SFG).

In a preferred example of the present embodiment, the column spacing SC, the row spacing SR, active pixel spacing SAP and the local spacing SL are all equal. In this case, the horizontal widths WR_odd and WR_even and the vertical widths WC_odd and WC_even of the blocking layer M are substantially the same.

InFIG. 6, the characters R, G and B denote red, green and blue color filter regions, respectively. As one skilled in the art will appreciate, in the example ofFIG. 6, the R, G and B color filters are arranged in a so-called Bayer pattern.

FIG. 7illustrates an example of micro-lens placement in an APS array of an embodiment of the present invention. As shown in this figure, a plurality of micro-lenses200are respectively positioned over the photoelectric conversion regions of APS array such as that described above in connection withFIGS. 4-6. The micro-lenses200function to focus and filter incident light onto the underlying photoelectric conversion regions.

InFIG. 7, reference character F denotes the focal point of each lens200, and reference character PC denotes the center of gravity of each underlying photoelectric conversion region. As illustrated in the drawing, the focal points F and centers PC may be intentionally offset in selected areas of the APS array in order to compensate for different angles in which light is incident across the surface of the APS array. For example, as shown inFIG. 7, the focal points F and centers PC may offset at left and right portions of the APS array, whereas the focal points F and center PC may be aligned at central portions of the APS array.

FIG. 8is an example showing a schematic cross-sectional view taken along line A-A′ ofFIG. 7.

Referring toFIG. 8, photoelectric conversion elements110containing a pinning layer114and a photodiode region112are formed in a n-type doped semiconductor substrate101having a p-type epitaxial layer107. In this example, a gathering layer103(which functions to decrease dark current and reduce white defects) is also formed by implantation of IV family atoms such as carbon, germanium or a combination of thereof.

An isolation region109is formed in the surface of the substrate so as to define the active area patterns (e.g., A1, A2inFIG. 4). A gate dielectric layer134is then formed at a thickness of about 5 to 100 Å on the substrate101. The gate dielectric layer134may, for example, be formed of SiO2, SiON, SiN, Al2O3, Si3N4, GexOyNz, GexSiyOz, HfO2, ZrO2, Al2O3, Ta2O5, or a combination of two or more thereof.

Gate electrodes136and gate spacers138are then formed so as to define the transfer transistor, the drive (source follower) transistor (not shown), the reset transistor (not shown) and the row select transistor (not shown). The gate electrodes136may, for example, be formed of polysilicon, W, Pt, Al, TiN, Co, Ni, Ti, Hf, Pt or a combination of two or more thereof, and the gate spacers138may, for example, be formed of SiO2, SiN or a combination thereof. A floating diffusion region120doped with n-type impurities, and a pinning layer114doped with p-type impurities are also formed as shown inFIG. 8.

Reference number170ofFIG. 8denotes one or more interlayer dielectric (ILD) layers formed over the substrate101, and reference numbers145and155denote conductive lines formed within the ILD layer170. Conductive plugs140are formed to connect the floating diffusion regions120and the conductive lines145, and conductive plugs150are formed to electrically connect the transfer gate130to the second conductive lines155.

The conductive plugs140and150, and the conductive lines145and155may, for example, be formed polysilicon and/or metals such as aluminum or copper.

Also formed in the ILD170is a blocking layer160made, for example, of aluminum, copper or other metallic material. The blocking layer160corresponds to the blocking layer M illustrated inFIG. 6. A first planarized layer180, a color filter pattern190, and a second planarized layer195are successively formed over the ILD170, and micro-lenses200are then formed over the second planarized layer195. As explained previously in connection withFIG. 7, the focal points of the micro-lenses200may be intentionally offset to compensate for different angles in which light is incident across the surface of the APS array.

FIG. 9is a timing diagram for explaining an operational example of a shared two-pixel APS array according to an embodiment of the present invention. In particular, the example presented here is a “charge summation” process in which charges from two photoelectric conversion regions are summed to obtain a single light intensity value. In this example, the color filters of the APS array are arranged in a Bayer configuration such as that illustrated inFIG. 5. Charge summation is particularly useful in a moving picture mode in which huge amounts of data are supplied from the APS array which may exceed the processing capacity of an image signal processor.

Referring toFIGS. 2,5and9collectively, the photoelectric conversion elements11in each row of the APS array simultaneously accumulate charges depending on light incident thereto. The explanation that follows is with respect to the pixel P(i, j+1) ofFIG. 2. It is assumed here that the pixel P(i, j+1) corresponds to the second column of photoelectric conversion regions shown inFIG. 5. These photoelectric conversion regions respectively have green G, blue B, green G and blue B color filters from top to bottom inFIG. 5.

At time t0, the select line SEL(i) is driven HIGH to thereby activate (open) the select transistor19. Subsequently, a clock pulse is applied to the reset line RX(i), and the reset transistor18is responsive thereto to reset the floating diffusion region13to the supply voltage (e.g., Vdd).

During time t1to t2, a signal pulse is applied to the first transfer line TX(i)a, and as a result the first transfer transistor15ais activated to transfer electrons in the photoelectric conversion element11a(green G) to the floating diffusion region13. The charges in the floating diffusion region13are applied to the gate of the drive transistor17, thus resulting in a corresponding output voltage on the output line Vout. The output line Vout is connected to the correlated double sampler CDS50(FIG. 1) which holds the voltage level of the output Vout and compares the same with a reference voltage level of the output Vout.

Then, during time t2to t3, a signal pulse is applied to the third transfer line TX(i)c, and as a result the third transfer transistor15cis activated to transfer electrons in the photoelectric conversion element11c(green G) to the floating diffusion region13. The charges in the floating diffusion region13are applied to the gate of the drive transistor17, thus resulting in a corresponding output voltage on the output line Vout.

The charges thus derived from the photoelectric conversion element11aand11care then summed to obtain a green G light intensity valued for the active unit pixel.

Then, at time t4, a clock pulse is again applied to the reset line RX(i), and again the reset transistor18is responsive thereto to reset the floating diffusion region13to the supply voltage (e.g., Vdd).

During time t5to t6, a signal pulse is applied to the second transfer line TX(i)b, and as a result the second transfer transistor15bis activated to transfer electrons in the photoelectric conversion element11b(blue B) to the floating diffusion region13. The charges in the floating diffusion region13are again applied to the gate of the drive transistors, thus resulting in a corresponding output voltage on the output line Vout.

Next, during time t16to t7, a signal pulse is applied to the fourth transfer line TX(i)d, and as a result the fourth transfer transistor15dis activated to transfer electrons in the photoelectric conversion element11d(blue B) to the floating diffusion region13. The charges in the floating diffusion region13are applied to the gate of the drive transistor17, thus resulting in a corresponding output voltage on the output line Vout.

The charges thus derived from the photoelectric conversion element11band11dare then summed to obtain a blue B light intensity valued for the active unit pixel.

The process described above is then repeated for each of the remaining rows of the APS array.

As mentioned previously, the invention is not limited to the specific example presented above in connection withFIGS. 2-9. For example, attention is directed toFIG. 10which illustrates an alternative active area pattern layout according to another embodiment of the present invention.

The active area pattern layout illustrated inFIG. 10is similar to that ofFIG. 4in that it includes four (4) active area patterns A5, A6, A7and A8. However, the extension portion b ofFIG. 4is omitted in the layout ofFIG. 10. Further, the reset gate RG is positioned over the active area pattern A7inFIG. 10, and both the source follower gate SFG and the select gate RSG are positioned over active area pattern A8inFIG. 10.

FIG. 11illustrates another alternative active area pattern layout according to another embodiment of the present invention. This embodiment also includes four (4) active area patterns A9, A10, A11and A12. The first active area pattern A9includes an active area portion c centered between four equally spaced active area portions a11, a12, a21and a22arranged in a matrix as shown inFIG. 11. The active area portions a11, a12, a21and a22respectively contain photoelectric conversion regions PD1through PD4. The active area portion c contains a common floating diffusion region FD, and transfer gates TG1through TG4are positioned between the floating diffusion region FD and the respective active area portions a11through a22.

As shown inFIG. 11, the horizontal spacing between the active area portions a11, a12, a21and a22is defined as an active pixel row spacing SAPR, and the vertical spacing is defined as an active pixel column spacing SAPC. Preferably, widths of the row spacing SR, the column spacing SC, the active pixel row spacing SAPR, and the active pixel column spacing SAPC are substantially equal.

The active regions area patterns A10, A11and A12are all elongate and extend lengthwise in the vertical (column) direction. Also, as shown inFIG. 11, the active area pattern A10is located at the intersection of the row spacing SR and the active pixel column spacing SAPC. The active area pattern A11is located at the intersection of column spacing SC and the active pixel row spacing SAPR. Finally, the active area pattern A12is located at the intersection of the row spacing SR and the column spacing SC.

Also, in the example of this embodiment, the reset gate RG is located over the active area A10, the source follower gate SFG is located over the active area A11, and the select gate RSG is located over the active area A12.

FIG. 12illustrates an exemplary processor-based system having a CMOS imager device542, where the CMOS imager device542includes an image sensor according to the above-described embodiments of the present invention. The processor-based system is exemplary of a system receiving the output of a CMOS imager device. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision system, vehicle navigation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, mobile phone, all of which can utilize embodiments of the present invention.

Referring toFIG. 12, the processor based system of this example generally includes a central processing unit (CPU)544, for example, a microprocessor that communicates with an input/output (I/O) device546over a bus552. The CMOS imager device542produces an output image from signals supplied from an active pixel array of an image sensor, and also communicates with the system over bus552or other communication link. The system may also include random access memory (RAM)548, and, in the case of a computer system may include peripheral devices such as a floppy disc drive554, a CD_ROM drive556and/or a display (not shown) which also communicate with the CPU544over the bus552. Other peripheral devices may be included such as a flash-memory card slot and the like. It may also be desirable to integrate the processor544, CMOS imager device542and memory548on a single integrated circuit (IC) chip.

Although the present invention has been described above in connection with the preferred embodiments thereof, the present invention is not so limited. Rather, various changes to and modifications of the preferred embodiments will become readily apparent to those of ordinary skill in the art. Accordingly, the present invention is not limited to the preferred embodiments described above. Rather, the true spirit and scope of the invention is defined by the accompanying claims.