Phase locked loop with reduced noise

A phase locked loop, comprising: a phase detector configured to determine a phase difference (Δφ) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. §119 of European Patent application no. 15168348.9, filed on May 20, 2015, the contents of which are incorporated by reference herein.

FIELD

The present disclosure relates to a phase locked loop with reduced quantization noise.

BACKGROUND

Phase locked loops (or PLLs) are used to generate an output signal with a defined phase relationship to an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In a digital phase locked loop, the phase detector outputs a digital signal. The output from the phase detector (indicating phase error) is received by a loop filter. The loop filter in turn provides an output signal to a frequency controlled oscillator. In an all-digital phase locked loop, the phase detector may output a digital signal, the loop filter may be a digital loop filter, and the frequency controlled oscillator may be a digitally controlled oscillator.

Phase locked loops are often required to achieve a specific noise performance. The maximum allowable phase noise may be determined by an intended application for a phase locked loop.

Sources of phase noise in a phase locked loop may include: external oscillator noise (resulting from an imperfect reference oscillator signal); frequency controlled oscillator noise, and quantization noise, arising from quantization of the phase error at the phase detector.

A phase locked loop with reduced noise is desirable.

SUMMARY

According to a first aspect, there is provided a phase locked loop, comprising:

a phase detector configured to determine a phase difference between a reference signal and a feedback signal;

a loop filter configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal;

a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal;

wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator, to reduce quantization noise from the phase detector.

The phase locked loop may have a bandwidth defined by the characteristics of the phase detector, loop filter and frequency controlled oscillator. The low pass filter may have a cut-off frequency that is greater than the bandwidth. The low pass filter may thereby suppress out-of-band quantization noise, without substantially affecting loop stability and performance.

The low-pass filter may have a cut-off frequency at least 1.2 times the bandwidth. The low-pass filter may have a cut-off frequency of at least: 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2 times the bandwidth.

The low-pass filter may have a cut-off frequency that is at least 100 kHz greater than the bandwidth. The low lass filter may have a cut-off frequency that is at least 50, 200, 300, or 500 kHz greater than the bandwidth.

The low-pass filter may comprise a first order IIR (infinite impulse response) filter. The low-pass filter may comprise a second order IIR filter. The low-pass filter may be a finite impulse response filer. The low-pass filter may be a digital filter. A first order digital IIR filter is simple and effective in some applications.

The low-pass filter may comprise a shift multiplier in a forward path thereof, for multiplying by an integer power of two. A shift multiplier may be a convenient way to provide a multiplication function.

The loop filter may comprise an integral path comprising an integrator.

The loop filter may comprise a proportional path.

The phase locked loop may be configured with: a proportional gain factor kpin the proportional path and an integral gain factor kiprior to the integrator in the integral path. Optionally, kp≦2−12; and/or ki≦2−18.

The frequency controlled oscillator may comprise a switched capacitor LC oscillator. The frequency controlled oscillator may be a digitally controlled oscillator. Alternatively, the frequency controlled oscillator may be a voltage controlled oscillator (e.g. having a varactor).

The control signal may be a digital signal.

The output signal from the phase detector may be a digital signal.

The loop filter may be a digital loop filter.

The phase locked loop may be an all-digital phase locked loop.

A transmitter or receiver is provided, comprising the phase locked loop according to the first aspect.

The receiver may be a satellite radio receiver.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1is a block diagram of a (all-) digital phase locked loop, comprising a reference phase generator110, phase detector115, loop filter120, digitally controlled oscillator (DCO)130, post divider140, control block150, time to digital converter (TDC)160, frequency divider170, feedback register180and crystal190.

The crystal190provides an output signal with a stable frequency (e.g. 60 MHz), which is used to clock the TDC160, feedback register180and the register113of the reference phase generator110.

The reference phase generator110comprises an adder111and register113, arranged to integrate an input frequency control word FCW, and provide a reference phase ramp φref.

A phase detector115compares the reference phase ramp φrefwith a feedback ramp φfbderived from the output of the DCO130, and outputs a phase error signal Δφ. The feedback ramp φfbis determined by combining (e.g. by fixed point concatenation) the output from the feedback register180and the TDC160.

The loop filter120receives the phase error signal Δφ, and performs a filtering operation. The loop filter120in this example is controlled by a control block150, which may vary the configuration of the loop filter120(e.g. depending on the set FCW). The loop filter120provides three output signals for controlling the DCO130, these being a process voltage temperature control signal PVT, an acquisition control signal ACQ, and a tracking signal TR. Each of these control signals may control a switched capacitor bank of the DCO130, so as to vary the output frequency of the DCO130. Other frequency control mechanisms, such as digital to analog converters with varactors may be used in alternative arrangements.

The output from the DCO130is received at the frequency divider170and the TDC160. The TDC measures and quantizes the timing difference between transitions of the output signal from the crystal190and the transitions in the output from the DCO130. The frequency divider170divides the output frequency of the DCO to produce a signal with reduced frequency. The output from the frequency divider170is received at the feedback register180, which accumulates a count of the transitions in the output of the divider

The post divider140receives the output from the DCO130, and divides the frequency by a factor, P, so as to provide an output signal from the phase locked loop at an appropriate frequency.

As an illustrative example, the output from the DCO130may have a frequency of around 5 GHz. The tuning range of the DCO130may be around 2.5 MHz. The post divider factor P may be 50, resulting in a phase locked loop output frequency of 100 MHz and a tuning range of 50 kHz. The PVT capacitor bank of the DCO130may have a tuning resolution of around 10 MHz, the ACQ capacitor bank may have a tuning resolution of around 0.5 to 1 MHz, and the TR capacitor bank may have a tuning resolution on the order of 10 to 50 kHz.

The DCO130and crystal190may operate in the analog domain. The DCO side of the divider170and TDC160may also operate in the analog domain. The remaining components may operate in the digital domain.

FIG. 2is a system block diagram for calculation of a phase transfer function for a phase locked loop (similar to that ofFIG. 1), comprising a phase detector115, differential gain block116, loop filter120and DCO130. The phase detector115receives an input reference phase φrefand subtracts the feedback phase φfboutput from the DCO130. The DCO130is represented by the transfer s-function ko/s (i.e. an integrator block with gain ko). The output of the phase detector115is multiplied by a differential gain factor kdat the differential gain block116. The output of the differential gain block116is provided to the loop filter120.

The loop filter120comprises a proportional path121and an integral path125. In the proportional path121, the output of the differential gain block116is multiplied (at proportional gain block122) by a proportional gain factor kp. In the integral path125, the output of the differential gain block116is first multiplied by an integral gain factor ki(at integral gain block126), and then integrated (at integrator127). The output from the proportional and integral paths121,125are summed at output summing block129, to provide the loop filter output, which is in turn received at the DCO block130.

This model can be generalised to calculate the phase noise contribution from the phase reference φrefand the noise φn,dcofrom the DCO, as shown inFIG. 3.

FIG. 3shows the same model asFIG. 2, but the loop filter120has been replaced with a single block, in which LF represents the transfer function of the loop filter120, and the DCO noise contribution φn,dcohas been included by way of a noise adding block195.

The phase transfer function for the diagram ofFIG. 3can be written as:

If the loop filter transfer function is as represented inFIG. 2, this results in:

This can be written in terms of the classical damping factor and natural frequency ωn, as:

It is directly visible from equation (3) that the loop has a low pass (LP) characteristic including the reference phase φrefand a high pass (HP) characteristic including the phase noise from the oscillator φn,dco. The bandwidth of the loop filter is defined by the cut-off frequency ω3 dBwhich depends on the natural frequency, ωnand the damping factor ξ.

Looking at equation (1), the denominator of the reference phase term φrefalways has one order less than the denominator. Hence the low pass characteristic has a −20 dB/decade slope, following the cut-off frequency, ω3 dB. The oscillator phase noise term φn,dco, however, depends on the order of the loop filter120(as is clear from equation (1)). In the example of equation (3), which is a 2ndorder system, the oscillator phase noise contribution has a 40 dB/dec slope before the cut-off frequency, ω3 dB.

FIG. 4depicts the phase noise contributions from the HP term201and the LP term202for the 2ndorder PLL system of equation (3). In the example ofFIG. 4the bandwidth, ω3 dB, of the PLL is selected so that the noise contributions from the HP term201and the low pass term202are similar at the cutoff frequency determined by the PLL bandwidth (where each term starts to roll-off).

Referring back to equation (3), the phase noise contribution to the term φreffrom the reference oscillator itself (e.g. crystal190inFIG. 1) may be neglected in the frequency range of interest because in this frequency range the reference noise contribution φrefis dominated by the quantization noise arising from the resolution of the phase detector115. This quantization noise is white noise, and is constant over frequency. Quantisation noise may be represented by the following equation:

Lquant⁡(f)=112⁢(τresTdco)2⁢12⁢π·fref(4)
where τresis the phase detector resolution, Tdcothe DCO period and frefthe reference frequency.

The noise contributions from the DCO to the term φn,dcoinclude a free running phase noise that has a slope of −30 dB/decade in the flicker noise range, and thermal noise which has a slope of −20 dB/decade above a certain frequency (e.g. between 10 kHz and 100 kHz). Since it is desirable for a phase locked loop to have a high bandwidth, only thermal noise is of interest in the following analysis.

FIG. 5shows a graph that includes DCO thermal noise221, quantization noise222and the total phase noise220of the PLL. The DCO thermal noise221reduces at −20 dB/decade in the out-of band range (i.e. at frequencies greater than the bandwidth, ω3 dB), which is the same rate of reduction as the quantization noise (which although white noise, is LP filtered). In this example, near the cut-off frequency, ω3 dB, the noise contributions from the DCO thermal noise221and quantization noise222are similar. This results in around 3 dB more total phase noise around ω3 dBthan the DCO thermal noise contribution, which would be the limiting factor for such a phase locked loop.

For a number of applications (e.g. consumer and automotive communications systems) it is very important to have an out-of-band phase noise that is as low as possible. Small changes of the phase noise level can have a high impact on the functioning of a system that includes the PLL. An improvement of 1 or 2 dB can have big impact to the complete system. In the example ofFIG. 5, any improvements of the DCO phase noise would not have a significant impact because the phase noise is dominated by the quantization noise222.

A trivial solution to the quantization noise dominating the overall phase noise of a PLL is to reduce the bandwidth ω3 dB, so that the out-of-band phase noise is in fact dominated by the DCO thermal noise.FIG. 6depicts this, showing DCO thermal noise231, quantization noise231and total phase noise230. Decreasing the bandwidth of the PLL reduces the cut-off frequency of the LP term in equation (3), which allows the phase noise contribution from the DCO to produce an undesirable peak near the cut-off frequency ω3 dB. This peak can only be avoided if the DCO phase noise is reduced, but this is very challenging in practice. The DCO design may already be at or near the physical limits of noise performance. A further disadvantage of reducing bandwidth is an increased locking and settling time of the PLL.

FIG. 7(a)shows a PLL architecture that ameliorates the above mentioned issues. The PLL ofFIG. 7is the same as that ofFIG. 2, except that an additional low pass filter250is included between the loop filter120and frequency controlled oscillator130. In other embodiments, the additional low pass filter250can be placed between the loop filter120and the phase detector115, and still provide the same benefits. The additional low pass filter250may have a cutoff frequency that is the same as, or higher than the bandwidth of the phase locked loop.

FIG. 7(b)shows an example architecture for the low pass filter250, comprising a first order infinite impulse response (IIR) filter. The forward path of the low pass filter250ofFIG. 7(b)comprises (in order) a first summing block251, multiplier252, second summing block253and unit delay254. The output from the unit delay254is fed-back to the first summing block251, where it is subtracted from the input signal to the filter250, and to the second summing block253, where it is added to the output of the multiplier252. The multiplier252applies a gain factor a to the output of the first summing block253, and passes the result to the second summing block253.

The low pass filter250ofFIG. 7(b)has the following frequency response:

The multiplier252may be a shift multiplier, and a=2−klpwhere klp is the low pass filter factor. The cut-off frequency of the low pass filter250may then be calculated as:

The overall phase transfer function for the phase locked loop ofFIG. 7(a)may then be written as:

φout=φref·kd·kp·ko·a·sT+kd·ki·ko·as3⁢T3+a·s2⁢T2+kd·kp·ko·a·sT+kd·ki·ko·a+φn,dco·s3⁢T3+a·s2⁢T2s3⁢T3+ωc·s2⁢T2+kd·kp·ko·ωc·sT+kd·ki·ko·ωc(7)
or, in terms of ξ and ωn, as:

In common with equation (3), equation (8) has low pass (LP) characteristic including the reference phase φrefand a high pass (HP) characteristic including the phase noise from the oscillator φn,dco.

FIG. 8depicts the phase noise contributions from the HP term211and the LP term212for the PLL system of equation (8).

Since the order of the denominator of the reference phase term φrefin equation (8) is 3 whereas the numerator is 1, the cut off slope of the low pass behaviour is −40 dB/decade. The suppression of the quantization phase noise is therefore stronger than the slope of the DCO thermal phase noise (at −20 dB/decade).

If the order of the additional low pass filter250inFIG. 7(b)was higher (for example second order, such as a second order IIR filter), the slope of the high pass characteristic can be increased (for example to −60 dB/dec in the case of a 2nd order low pass filter250).

The high pass characteristic of the overall phase locked loop is not changed significantly. For low frequencies the 2nd order term dominates, and the high pass characteristic is still 40 dB/dec as before, as shown inFIG. 8.

FIG. 9shows the total phase noise240for a PLL as shown inFIG. 7, along with DCO thermal noise component241and the quantization noise component242. In this example, the cut-off frequency ωcof the additional low pass filter250is 1 MHz, and the PLL bandwidth ω3 dBis 100 kHz.

For higher frequencies the slope of the phase detector quantization noise242is increased from −20 dB/decade to −40 dB/decade, which results in sufficient reduction of quantization noise for the DCO phase noise241to become the dominant source of total phase noise204.

The performance of a phase locked loop comprising an additional low pass filter has been simulated. A loop filter according to an embodiment (e.g. as shown inFIG. 7) was implemented and the phase noise contribution modeled, based on measurement results.

FIG. 10shows simulation results, comparing phase noise270from a free running (open loop) DCO with phase noise260according to the architecture ofFIG. 2(without an additional low pass filter) and phase noise273from the architecture ofFIG. 7, including the low pass filter250. For both closed loop phase noise simulations260,253, kp=2−12and ki=2−19. The reference frequency for these simulations is 55.5 MHz. For the phase noise simulation273including the low pass filter, klp=3, corresponding with a cut-off frequency ωcfor the low pass filter250of approximately 1.1 MHz. Substantial improvements in phase noise result from the inclusion of the additional filter250(e.g. around 10 dB from 3 to 7 MHz, and at least 5 dB from 800 kHz to 10 MHz).

FIG. 11shows the effect of varying the parameter klp of the additional filter250. Again, the open loop DCO phase noise270is shown, along with phase noise simulations271to276, respectively corresponding with klp values of 1 to 6. The cutoff frequencies ωccorresponding with each value of klp are shown in the table below.

As the cut-off frequency ωcgets close to the PLL bandwidth ω3 dBthe PLL may become unstable. The optimum settings for this example PLL may be klp=5, since this provides the largest improvements to phase noise above 300 kHz, and does not introduce the large peak centered just above 100 kHz that is associated with klp=6.

This disclosure shows how the out-of-band phase noise of a PLL system (such as an ADPLL) can be improved by reducing the quantization phase noise contribution from the phase detector in out-of-band frequency range by means of an additional low-pass filter before or after the loop filter. The design effort needed to implement this improvement is quite small. The configuration can be chosen such that the overall loop dynamic is hardly changed. There is no problem with stability (which may occur in more complex arrangements in which the loop filter is modified to try to increase suppression of quantization noise), provided the filter parameters are selected appropriately. According to the disclosure, the phase locked loop may be set to higher loop bandwidths without degrading the out-of-band phase noise performance. The phase locked loop described herein works well in a wide range of applications.

The disclose can be applied in the context of a linear, all digital phase locked loop, as shown inFIG. 7, or in any other controlling scheme that generates quantization noise, for example a PLL in which a bang-bang control scheme is used. A bang-bang mode may be a non-linear controlling mode in which a quantizer is used to determine a phase error (instead of an adder), and the loop filter may be updated by small constant portions accordingly.

For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, and reference signs in the claims shall not be construed as limiting the scope of the claims.