Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.

FIELD OF THE INVENTION

The present invention relates to dual damascene processes used to form copper lines and vias in the fabrication of semiconductor integrated circuits. More particularly, the present invention relates to novel dual damascene processes which are characterized by low cost and short cycle times.

BACKGROUND OF THE INVENTION

The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.

Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.

The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.

In the semiconductor industry, copper is being increasingly used as the interconnect material for microchip fabrication. The conventional method of depositing a metal conducting layer and then etching the layer in the pattern of the desired metal line interconnects and vias cannot be used with copper because copper is not suitable for dry-etching. Special considerations must also be undertaken in order to prevent diffusion of copper into silicon during processing. Therefore, the dual-damascene process has been developed and is widely used to form copper metal line interconnects and vias in semiconductor technology. In the dual-damascene process, the dielectric layer rather than the metal layer is etched to form trenches and vias, after which the metal is deposited into the trenches and vias to form the desired interconnects. Finally, the deposited copper is subjected to chemical mechanical planarization (CMP) to remove excess copper (copper overburden) extending from the trenches.

While there exist many variations of a dual-damascene process flow, the process typically begins with deposition of a silicon dioxide dielectric layer of desired thickness which corresponds to the thickness for the via or vias to be etched in the dielectric layer. Next, a thin etch stop layer, typically silicon nitride, is deposited on the dielectric layer. Photolithography is then used to pattern via openings over the etch stop layer, after which dry etching is used to etch via openings in the etch stop layer. The patterned photoresist is then stripped from the etch stop layer after completion of the etch. A remaining dielectric layer the thickness of which corresponds to the thickness of the trench for the metal interconnect lines is then deposited on the etch stop layer, and photolithography followed by dry etching is used to pattern the trenches in the remaining dielectric layer and the vias beneath the trenches. The trench etching stops at the etch stop layer, while the vias are etched in the first dielectric layer through the openings in the etch stop layer and beneath the trenches. Next, a barrier material of Ta or TaN is deposited on the sidewalls and bottoms of the trenches and vias using ionized PVD. A uniform copper seed layer is then deposited on the barrier layer using CVD. After the trenches and vias are filled with copper, the copper overburden extending from the trenches is removed and the upper surfaces of the metal lines planarized using CMP. In the dual damascene process described above, the vias and the trenches are etched in the same step, and the etch stop layer defines the bottom of the trenches. In other variations, the trench is patterned and etched after the via.

A significant advantage of the dual-damascene process is the creation of a two-leveled metal inlay which includes both via holes and metal line trenches that undergo copper fill at the same time. This eliminates the requirement of forming the trenches for the metal interconnect lines and the holes for the vias in separate processing steps. The process further eliminates the interface between the vias and the metal lines.

Another important advantage of the dual-damascene process is that completion of the process typically requires 20% to 30% fewer steps than the traditional aluminum metal interconnect process. Furthermore, the dual damascene process omits some of the more difficult steps of traditional aluminum metallization, including aluminum etch and many of the tungsten and dielectric CMP steps. Reducing the number of process steps required for semiconductor fabrication significantly improves the yield of the fabrication process, since fewer process steps translate into fewer sources of error that reduce yield.

While the traditional dual damascene process is attended by many advantages, some of the disadvantages include high cost, excessive process complexity and inordinately long process cycle time. Accordingly, a new and improved dual damascene process is needed which is characterized by low cost and a shorter cycle time.

Accordingly, an object of the present invention is to provide a new and improved method for fabricating metal lines and vias on a substrate.

Another object of the present invention is to provide a new and improved dual damascene process for semiconductor fabrication.

Still another object of the present invention is to provide a new and improved dual damascene process which is characterized by a short cycle time and low cost.

Yet another object of the present invention is to provide a dual damascene process which includes fabricating vias on a substrate followed by fabrication of metal lines in conductive communication with the vias.

A still further object of the present invention is to provide a dual damascene process which includes formation of a partial via; completion of the via and formation of a trench above the via in a single step; and filling of the via and trench with copper to complete the metal line and via on the substrate.

SUMMARY OF THE INVENTION

In accordance with these and other objects and advantages, the present invention is generally directed to novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring initially toFIGS. 1A-1N, in a first embodiment according to the novel dual damascene processes of the present invention, vias and metal lines are sequentially fabricated to form a metal line and via system1. Fabrication of the system1according to the first embodiment begins with formation of the vias, as will be hereinafter described with respect toFIGS. 1A-1G, followed by formation of the metal lines above the vias, as will be hereinafter described with respect toFIGS. 1H-1N. The dual damascene processes of the present invention provide methods which are characterized by low cost and shortened cycle times as compared to conventional dual damascene processes.

As shown inFIG. 1A, fabrication of the system1includes initial deposition of a metal conductive layer3on a substrate (not shown). A bottom etch stop layer5, which is typically SiN (silicon nitride), is deposited on the conductive layer3and has a thickness of typically about 500 angstroms. A bottom dielectric layer7, typically SiON, is then deposited on the bottom etch stop layer5and may have a thickness of typically about 600 angstroms. A top etch stop layer9, also having a thickness of typically about 500 angetroms, is then deposited on the bottom dielectric layer7. A patterned photoresist11, having multiple via etch exposure openings13which correspond positionally and dimensionally to the desired pattern for the vias to be formed in the system1, is deposited on the top etch stop layer9. Each of the via etch exposure openings13has a CD (critical dimension) size of typically about 0.38-0.40 μm.

The vies15are formed by etching through the top etch stop layer9and then the bottom dielectric layer7downwardly through the via etch exposure openings13in the patterned photoresist11, until the etching stops at the bottom etch stop layer5, as shown inFIG. 1B. The etch process may be a self-aligned etch process. Next, as shown inFIG. 1C, the patterned photoresist11is stripped from the underlying top etch stop layer9and then typically subjected to a wet cleaning process to remove photoresist residue therefrom, as is known by those skilled in the art. The portions of the bottom etch stop layer5which separate each via15from the underlying conductive layer3are then etched away to establish communication between each via15and the underlying conductive layer3, as indicated by reference numeral5ainFIG. 1D. Next, the partially fabricated system1is typically subjected to wet cleaning, CD measurement, AEI (after-etch inspection) and pre-bake prior to deposition of a barrier layer17on the sidewalls and bottom of each via15, followed by deposition of a copper seed layer19on the barrier layer17, as shown inFIG. 1E. Typically, the barrier layer17is TaN and has a thickness of about 300 angstroms. The copper seed layer19has a thickness of typically about 1,800 angstroms. Deposition of the barrier layer17and the seed layer19may be preceded and followed by charging of the processing environment with nitrogen gas. The vias15are then tilled with copper via infills22, and a copper plating layer21which is continuous with the copper via infills22is deposited on the portion of the seed layer19which was previously deposited on the bottom dielectric layer7. Finally, after charging of the processing environment with nitrogen, the copper plating layer21is subjected to CMP (chemical mechanical planarization) to planarize the copper plating layer21, as shown inFIG. 1G.

Referring next toFIGS. 1H-1N, metal lines are then formed in the system1above the copper-inlaid vias15as follows. As shown inFIG. 1H, a top dielectric layer23which may be SiON, which may include an additional overlying dielectric/hard mask layer9b, and have a thickness of typically about 600 angstroms, is initially deposited on the planarized copper plating layer21. Next, as shown inFIG. 1I, a patterned photoresist25, having multiple trench etch exposure openings27which correspond positionally and dimensionally to the desired pattern for the trenches to be etched, is deposited over the top dielectric layer23. Each of the trench etch exposure openings27has a CD of typically at least about 2.5 μm. Trenches29, each corresponding to the width and position of a corresponding one of the trench etch exposure openings27in the patterned photoresist25, are then etched beneath each opening27, through the underlying top dielectric opening23and the copper plating layer21, to the top etch stop layer9, as shown inFIG. 1J. The etch process may be a self-aligned etch process. Next, as shown inFIG. 1K, the portion of the top etch stop layer9which separates each trench29from the underlying via15is etched to establish communication between the vias15and the trenches29, as indicated by reference numeral9a. This is typically followed by wet cleaning to remove etch particles as well as CD measurement and AET (after-etching inspection). A barrier layer31is next deposited on the sidewalls and bottom of the trenches29, as well as on the upper surface of the top dielectric layer23, and a copper seed layer33is deposited on the barrier layer31, as shown inFIG. 1L. The barrier layer31is typically TaN and has a thickness of about 300 angstroms, whereas the copper seed layer33has a thickness of typically about 1,800 angetroms. Both before and after the barrier layer31and the seed layer33are deposited, the processing environment may be charged with nitrogen. The trenches29are then filled with copper trench infills36, and a copper plating layer35which is continuous with the copper trench infills36is deposited on the portion of the seed layer33which was previously deposited on the bottom dielectric layer7with the barrier layer31. Finally, as shown inFIG. 1N, the copper plating layer35is subjected to CMP (chemical mechanical planarization) to substantially planarize the copper plating layer35. Accordingly, the copper trench infills36define metal lines that connect devices (not shown) to each other in the integrated circuit off which the system1is a part, and the copper via infills22connect the metal lines to the underlying conductive layer3.

Referring next toFIGS. 2A-2J, in a second embodiment according to the methods of the present invention, a metal line and via system41is fabricated by initially depositing a bottom etch stop layer45on a conductive layer43previously deposited on a substrate (not shown) or an insulative layer (not shown), as shown inFIG. 2A. The bottom etch stop layer45is typically SiN (silicon nitride) and may be about 500 angstroms thick, or in the range of 300 Å-3000 Å. Next, a bottom dielectric layer47, typically silicon dioxide SiO2and having a thickness of about 600 angstroms, or in the range of 300 Å-2000 Å, is deposited on the bottom etch stop layer45. A top etch stop layer49is deposited on the bottom dielectric layer47, and a top dielectric layer51is deposited on the top etch stop layer49. An additional dielectric/hard mask layer49bmay be formed on the top dielectric layer51as shown inFIG. 2B. A patterned photoresist53, having multiple via etch exposure openings55corresponding the positions and dimensions of vias to be etched, is deposited over the top dielectric layer51. Each of the via etch exposure openings55has a CD of typically about 0.20 μm to about 2 μm.

As shown inFIG. 2B, each of multiple partial vias57is then etched in the top dielectric layer51. The etch process may be a self-aligned etch process. Next, as shown inFIG. 2C, a patterned photoresist59, having multipie trench etch exposure openings61corresponding positionally and dimensionally to the respective trenches to be etched, is deposited on the top dielectric layer51, with each trench etch exposure opening61disposed in communication with one or more underlying partial vias57. The CD of each trench etch exposure opening61is typically at least about 0.5 μm. As shown inFIG. 2D, partial trenches63are then etched typically using a self-aligned etch process in the top dielectric layer51, beneath the respective trench etch exposure openings61. Simultaneously, the partial vias57are etched downwardly through the top dielectric layer51in advance of the downwardly-etching partial trenches63, until the bottom ends of the partial vias57reach the top etch stop layer49. Next, as shown inFIGS. 2E and 2F, the partial trenches63are etched through the top dielectric layer51to the top etch stop layer49, at which point the partial trenches63define complete trenches67. Simultaneously, the partial vias57are etched downwardly through the top etch stop layer49and the bottom dielectric layer47, respectively, and define complete vias65when they reach and are stopped by the bottom etch stop layer45. The patterned photoresist59is then stripped from the top dielectric layer51, as further shown inFIG. 2F. As shown inFIG. 2G, the portion of the top etch stop layer49between each complete trench67and the underlying via or vias65is next etched away to expose the bottom dielectric layer47at the bottom of each trench67. In similar fashion, the portion of the bottom etch stop layer45between each complete via65and the conductive layer43is etched away to establish communication between each complete via65and the underlying conductive layer43. This is followed by wet cleaning of the system41typically using an ST-250solvent, CD measurement for the complete vias65and the complete trenches67, and pre-baking of the system41.

As shown inFIG. 2H, a barrier layer69is then deposited on the sidewalls of the complete vias65and complete trenches67, as well as on the exposed upper surface of the top dielectric layer51. A seed layer71is then deposited on the barrier layer69. In a preferred embodiment, the barrier layer69is TaN and has a thickness of typically about 300 angstroms, or in the range of 200 Å-1000 Å, whereas the seed layer71is copper and has a thickness of typically about 1,800 angstroms, or in the range of 1000 Å-3000 Å. Next, as shown inFIGS. 2H and 2I, in a single process step the complete vias65are filled with respective copper trench infills75, the complete trenches67are filled with copper trench infills74, and a copper plating layer73which is continuous with the copper trench infills74is deposited on the portion of the seed layer71which was previously deposited on the top dielectric layer51. Finally, as shown inFIG. 2J, the copper plating layer73is subjected to CMP (chemical mechanical planarization) to substantially planarize the copper plating layer73. Accordingly, the copper trench infills74define metal lines that connect devices (not shown) to each other in the integrated circuit of which the system41is a part, and the copper via infills75connect the metal lines to the underlying conductive layer43.