Graphics lighting engine including log and anti-log units

Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error.

TECHNICAL FIELD

The disclosed technology relates to three-dimensional graphics, and, more particularly, to a graphics lighting engine that includes log and anti-log units for performing lighting computations.

BACKGROUND

Shading and texture mapping are the most compute intensive and power hungry stages of the 3D graphics pipeline illustrated inFIG. 1. Power consumption in texture mapping is dissipated primarily in memory accesses. In geometry processing, lighting computation takes up to 83% of geometry transformation clock cycles.

Lighting computation determines the color intensity of each pixel within a rendered primitive. Illumination is the transport of luminous flux (measure of perceived power of light) from light sources through direct and indirect paths, and may be adjusted to reflect the varying sensitivity of the eye to different wavelengths of light. Lighting refers to the interaction between materials and light sources, thus determining the intensity of color for each pixel. Shading determines the color of a pixel based on illumination and lighting models.

A simplified and widely used model for lighting is referred to as the Phong Illumination Equation which describes reflected light intensity in terms of ambient, diffuse, and specular components and it is computed for each R, G, B component and for each light source. The equation is given as:

where the ‘a’ terms refer to ambient components of the illumination, the ‘d’ terms refer to diffuse components, and the ‘s’ terms refer to the specular components. The term kais, a weighting constant, Iais the ambient light source intensity, Iliis the intensity from each light source, kdis the diffusion weighting constant, N·L is the dot product of the surface normal with the direction of the light source, ksis the specular weighting constant, R·V is the dot product of the reflection vector of the light source about the normal to the surface with the viewing vector V, and S is the specular coefficient. This lighting model can be applied on a per-vertex basis, such as in a vertex shading block120ofFIG. 1, and on a per-pixel basis in a fragment or pixel shading block130.

The most compute-intensive part of calculating terms according to the Phong Illumination Equation is computation of the specular term, as it involves a power term. Computing the power term consumes the majority of clock cycles. The computation of a floating point number, referred to herein as the number, to the power of another floating point number, referred to herein as the power term, is very difficult to implement using standard hardware components. The best prior art methods to implement the computation of exponentiation in hardware include a software math library, table lookup of exponentiation, linear interpolation with table lookup, and Taylor/Chebyshev approximation which replaces exponentiation with a polynomial.

The best known methods of computing the Phong illumination Equation are illustrated inFIG. 2. In these methods, the specular term is transformed to the log domain, and the specular coefficient is multiplied with the transformed term in the log domain. Then the result is transformed back to decimal arithmetic using an anti-log transformation. The ambient and diffuse terms are computed outside of the log domain, which requires five separate floating point multiplications.

Log and anti-log approximations are currently implemented by using either table lookup, which can be memory intensive, or by using linear interpolation with either three intervals, which leads to a relatively high error, or more than six intervals, which adds complexity and area. Conventional multipliers used to compute the specular power term are either a full 32 b×32 b multiplier or a 24 b×24 b mantissa multiplier. The former requires increased area and hence power, and the latter results in lower precision.

Embodiments of the invention address these and other limitations of the prior art.

DETAILED DESCRIPTION

FIG. 3is a functional block diagram of a system300including a graphics engine310with a lighting accelerator unit320according to embodiments of the invention. The graphics engine310includes multiple components used for processing the graphics pipeline illustrated inFIG. 1. For example a SIMD (Single Instruction Multiple Data) datapath314provides instructions and data for operation by the graphics engine. An extended math unit312is used to perform specialized math functions that may prevent the SIMD datapath314from operating most efficiently. In other words, the extend math unit312offloads some of the more difficult processing from the SIMD datapath314.

Embodiments of the invention would typically be located in the lighting accelerator unit320of the graphics engine310ofFIG. 3, but concepts of the invention are not limited to any particular hardware location or software process.

FIG. 4is a functional block diagram illustrating a lighting accelerator unit including log and anti-log units according to embodiments of the invention. Embodiments of the invention compute all of the ambient, diffuse, and specular terms of a lighting equation in the log domain. Once converted into the log domain, terms that previously were multiplied in the arithmetic number domain may be added together, saving computation resources.

InFIG. 4, a lighting accelerator400includes a series of registers410used to store floating point numbers that represent the lighting values described above. A series of log units420convert the floating point numbers into the log domain using a series of linear equations as described in detail below. The log units420may include multiple units, as illustrated inFIG. 4, or may be embodied in one or more physical units. In the preferred embodiment five linear intervals are used in the equation for the log conversion, as described below with reference toFIG. 7. The majority of the ambient and diffuse calculations are performed in the log domain using a series of adders430,432,434,436, and438. A multiplier unit440, described with reference toFIG. 8below, performs multiplication of the specular components in the log domain, which are then added in an adder446. Then, a series of anti-log units460convert the data back into single precision numbers. As with the log units420, the anti-log units460may be separate units, an individual unit, or any combination. Different from the log units420, however, the preferred embodiment of the anti-log units460use a series of four linear intervals in its system of linear equations used to perform the anti-log function. These intervals, as well as the log intervals, represent the best tradeoff in terms of power, performance, area and accuracy. The preferred embodiment of the lighting accelerator400also includes a number of internal registers452,454, and456to internally store intermediate results.

In general, in operation of the lighting accelerator400, the ambient light source intensity, other light source intensities, weighting constants, and the specular coefficient are first input from the floating point registers410to a respective log unit420to transform the components to the log domain. The log unit420uses linear interpolation with five intervals to approximate the base-2 logarithm. Each input to the log unit420is a number between 0 and 1, or normalized to be between 0 and 1. The error of the log unit420is small (less than 0.5%) as the numbers are limited in range. Then, the ambient, diffuse, and specular terms of the Phong equation are computed using log arithmetic employing a total of six adders430,432,434,436,438and446and one multiplier440as shown inFIG. 4.

FIG. 5is a functional block diagram of a log processor500, which may be an example of the log unit420illustrated inFIG. 4. As described above, the computation in the fixed data path illustrated inFIG. 4is preferably performed using fixed point arithmetic. The output of the log processor500produces the fixed point numbers for such processing. As illustrated in the bottom ofFIG. 5, the fixed point numbers are represented as a 32-bit number with the most significant bit representing the sign, the next 8 bits representing an integer, and remaining 23 bits representing the fractional portion. Fixed-point computation reduces power and improves performance in the lighting accelerator.

The log processor500includes range selection logic510which uses the upper three bits of the mantissa of the input single precision number to determine which linear equation is to be used, as described below. An example range selection logic600is shown inFIG. 6, along with the preferred division of ranges for the log approximation. The output of the range selection510logic is used to select the appropriate constants and coefficients for the particular of the five equations being used, based on a portion of the mantissa value. Referring back toFIG. 5, the bias from the exponent of the single precision is first removed by adding it to −127 (0x81 is the hexadecimal representation) which is implemented by an incrementing block520and inversion of the Most Significant Bit (MSB). After the correct constants and coefficients are selected, the outputs are fed to a 3:2 compressor530and subsequent completion adder540. The coefficients are simply bit-shifts of the mantissa portion by a set number of bits depending on which interval the mantissa portion is a member of.

Computing exponentiation in the log domain results in a simple multiplication at the expense of accuracy. The error is minimized if the number that is input to the log unit is between 0 and 1, and can be computed quite quickly (˜4 clock cycles) using a handful of linear intervals in the preferred embodiment. Embodiments of the invention use log arithmetic to compute the exponentiation in the log units420using a base-2 log unit that is implemented using linear interpolation. Since the number input to the base-2 logarithm is between 0 and 1, the accuracy of the computation is mostly retained.

The log processor500uses five intervals which approximate the log using a linear equation. The equations for each interval are given inFIG. 7. Note that each of the coefficients of the equation are factors of 2, which may be readily implemented in digital logic using bit-shifts. Further, the coefficients have a low hamming weight. Using five interpolation levels provides very good accuracy. In practice, the range selection tool510ofFIG. 5reviews the MSBs of the mantissa, then selects the appropriate linear equation for the log approximation using the ranges illustrated inFIG. 7.

After being converted into the log domain by the log processor500, the specular calculations are operated on in the log domain by a multiplier440(FIG. 4), as described above. The multiplier440ofFIG. 4may be realized by a signed 32 b×32 b Booth-encoded fixed point multiplier with a truncated partial product tree. This unit computes the exponentiation operation of the specular lighting component in the log domain by computing the fixed point product of 8.23 bit R·V with the specular 8.23 constant ‘S’. The output 16.46 b result is truncated to a 8.16 b fixed point result, eliminating 31% of the partial-product bits (544 partial-product bits down to 376 bits).FIG. 8illustrates partial product rows and the three stages of 4:2 compressors for the reduced precision multiplier440. The 16 b integer section of the output is saturated at 8 bits and the 46 b fractional result is truncated at the 16 b boundary, eliminating the lower-order 30 bits. Partial-product bits from columns 29:25 are retained, as illustrated inFIG. 8to the right of the truncate indicator, to capture the effect of all carries that propagate across the 16 b boundary. This results in a maximum error of 2−16in the truncated result. In a preferred embodiment, the signed multiplier uses a radix-4 modified Booth encoder to generate 16 partial-product rows. These rows are merged using 3 stages of 4:2 compressors, resulting in a partial-product reduction tree made up of 177 compressors, a 29% reduction over a full 32 b×32 b signed multiplier.

FIG. 9illustrates an example embodiment of an anti-log processor900, which may be an example implementation of the anti-log unit460ofFIG. 4. The anti-log processor800takes as input a 32-bit fixed point representation, as described earlier. The anti-log processor approximates the mantissa portion of the single precision output using linear interpolation with four intervals. The equations for the anti-log unit460as well as the four interpolation levels are given inFIG. 10. The interpolation levels for the anti-log processor900are similar to those of the log processor500, described above, except that the lowest two levels of the log processor are collapsed into the lowest level of the anti-log processor, as illustrated inFIGS. 7 and 10.

Referring back toFIG. 9, the exponent for the resulting single precision number is computed by adding 127 (0x7F) to the 8 bits representing the integer portion of the fixed point input to obtain the biased negative exponent in an adder902. The mantissa portion is computed by linear interpolation as shown in the equations and using the coefficients illustrated inFIG. 10. The coefficients are computed using bit-shifts of the fractional portion of the input fixed point number and the appropriate constants are selected based on range selection logic910, which may be the same or similar logic to the range shift logic600illustrated inFIG. 6. A 4:2 compressor920adds the four inputs before passing the resulting carry and sum to a 24 b completion adder930. The completion adder930may be embodied by a quaternary tree adder, which is a highly efficient adder.

FIG. 11illustrates an example of a system1100in which embodiments of the disclosed technology may be implemented. The system1100may include, but is not limited to, a computing device such as a laptop computer, a mobile device such as a handheld or tablet computer, a communications device such as a smartphone, or an industry-specific machine such as a kiosk or ATM. The system1100includes a housing1102, a display1104, which may be in association with the housing1102, an input mechanism1106, which may also be in association with the housing1102, a processor1108within the housing1102, and a memory1110within the housing1102. The input mechanism1106may include a physical device, such as a keyboard, or a virtual device, such as a virtual keypad implemented within a touchscreen. The processor1108may perform virtually any of or any combination of the various operations described above. The illustrated processor1108may include a separate graphics processor including a lighting accelerator as described above, in a lighting unit, or such graphics capabilities may be included in the processor itself. The memory1110may store information resulting from processing performed by the processor1108.

Embodiments of the disclosed technology may be incorporated in various types of architectures. For example, certain embodiments may be implemented as any of or a combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, a graphics and/or video processor, a multicore processor, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). The term “logic” as used herein may include, by way of example, software, hardware, or any combination thereof.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the embodiments of the disclosed technology. This application is intended to cover any adaptations or variations of the embodiments illustrated and described herein. Therefore, it is manifestly intended that embodiments of the disclosed technology be limited only by the following claims and equivalents thereof.