Method and apparatus for a hybrid phase lock loop frequency synthesizer

A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a digital PLL, and a control circuit to control an output oscillator. The control circuit assigns control of the output oscillator between the analog PLL and/or the digital PLL depending on a state of lock of the analog PLL and/or the digital PLL. During a frequency acquisition mode, the digital PLL provides a coarse control of the output oscillator. During a phase capture mode, the analog PLL provides a fine control and the digital PLL provides a coarse control of the output oscillator. During the phase capture mode, the analog PLL control signal and the digital PLL control signal may be given a percentage of control over the output oscillator depending on the state of lock of the analog PLL and/or the digital PLL. During a phase lock mode, the analog PLL controls the output oscillator.

CROSS REFERENCE TO A RELATED APPLICATION

The present invention is related to U.S. patent application Ser. No. 10/993,592, entitled “HYBRID ANALOG/DIGITAL PHASE LOCK LOOP FREQUENCY SYNTHESIZER”, filed Nov. 19, 2004, which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to the field of phase lock loop frequency synthesizers and multipliers, and specifically to a hybrid phase lock loop that includes a digital phase lock loop and an analog phase lock loop.

2. Description of the Related Art

Generally, communication systems utilize various forms of phase lock loop (PLL) circuits to synchronize one or more output signals, e.g., carrier signals, to a reference signal. One conventional analog PLL includes a stable low frequency reference oscillator, e.g., a voltage controlled crystal oscillator (VCXO), coupled to a harmonic generator. A signal output of the harmonic generator provides a reference signal to an analog phase detector. A filtered version of an error signal from the analog phase detector is input to a voltage controlled oscillator (VCO). The oscillator generates an output carrier signal at a desired frequency. The phase detector adjusts (e.g., tunes) the oscillator to synchronize the frequency and phase to the error signal. Unfortunately, the analog PLL adjusts only over a narrow frequency range (i.e., tuning range) due to the limited capture range of the analog phase detector. The analog PLL can phase lock to any harmonic frequency of the reference signal that falls within the tuning range.

Conventional digital PLLs overcome many of the disadvantages of the analog PLL, such as the harmonic lock problem. A digital PLL generally includes a reference oscillator that provides a reference signal to a first digital frequency divider. An output of the first digital frequency divider is coupled to a digital frequency/phase detector. An output of the digital frequency/phase detector is coupled through a loop filter to an output oscillator. A sample of the output carrier signal generated by the output oscillator is coupled to a second digital frequency divider. A signal output of the second digital frequency divider is coupled as a feedback signal to the frequency/phase detector for comparison with the divided reference signal. The output carrier signal frequency is determined by the frequency of the reference signal multiplied by the ratio of the second digital divider to the first digital divider. Due to the wider capture range of the digital frequency/phase detector, the digital PLL provides tuning over a wide range of output carrier signal frequencies. Unfortunately, the digital implementation also encumbers the digital PLL with greater phase noise relative to the analog PLL.

Hybrid PLLs have been developed to capitalize on the benefits and avoid limitations of both the analog PLL and the digital PLL, as shown, for example, in U.S. Pat. No. 6,028,460.FIG. 1illustrates a prior art hybrid PLL frequency synthesizer100. Generally, such hybrid PLL frequency synthesizer100incorporates a hybrid PLL. The hybrid PLL includes a digital PLL105and an analog PLL103. The digital PLL105and the analog PLL103are configured to individually acquire and phase lock an output carrier signal121from an output oscillator120to a reference signal102provided by a reference oscillator101. Generally, during a frequency acquisition mode, the digital PLL105is used to acquire phase lock. Once the digital PLL105is phase locked, a switch115switches control of the hybrid PLL from the digital PLL105to the analog PLL103. The analog PLL103then phase locks the output carrier signal121to a harmonic of the reference signal102. The analog PLL103generally provides superior phase noise performance relative to the digital PLL105.

The digital PLL105includes a digital divider111, a digital phase detector113, and a charge pump114. The digital divider111digitally divides a sample of the output carrier signal121to the same frequency as the reference signal102. The digitally divided signal is coupled to the digital phase detector113for frequency/phase comparison to the reference signal102. The digital phase detector113provides phase control signals to the charge pump114. The charge pump114provides a digital PLL control signal to a switch115. When the digital PLL105is switched in control of the hybrid PLL, the switch115provides the digital control signal to a loop filter117. The loop filter117filters the digital PLL control signal before being coupled to the output oscillator120.

The analog PLL103includes a harmonic multiplier107to multiply the reference signal102to the same frequency of the output carrier signal121, or to a down converted version thereof. An analog phase detector109generates an analog control signal indicative of a phase comparison between the multiplied reference signal and a sample of output carrier signal121. When the analog PLL103is switched in control of the hybrid PLL, the switch115provides the analog PLL control signal from the analog phase detector109to the loop filter115. The loop filter115filters the analog PLL control signal before being coupled to the output oscillator120.

Generally, the hybrid PLL requires the switch115to alternate complete PLL control between the analog PLL103and the digital PLL105depending on whether the frequency synthesizer100is in an acquisition mode or is in a steady state phase locked mode. Therefore, depending upon the state of switch115, the hybrid PLL is controlled only by the analog PLL103or the digital PLL105.

Once the analog PLL103is phase locked, the digital PLL105monitors the phase and frequency lock after switching control of the hybrid PLL to the analog PLL103. If large frequency and/or phase perturbations of the analog PLL103are sensed, then switch115switches control of the hybrid PLL completely from the analog PLL103to the digital PLL105. Under such conditions, the digital PLL105takes complete control of the hybrid PLL to reacquire phase lock. Once phase lock is reacquired, the switch115switches control of the hybrid PLL completely from the digital PLL105to the analog PLL103.

Generally, the digital phase detector113generates digital signals, e.g., pulse shaped waveforms, having pulse widths associated with the time difference, i.e., skew, between such waveforms. For example, the digital signals are coupled to the charge pump114. Based on the pulse widths, the charge pump114provides the digital PLL control signal to the output oscillator120via the loop filter115.

Generally, the digital phase detector113provides the digital control signals to the charge pump113in the form of digital pump up or pump down signals depending on whether the reference signal102is leading or lagging the output signal121in phase. For example, the digital phase detector113provides the digital pump up signals when the reference signal102leads the output signal121in phase. Conversely, the digital phase detector113provides the digital pump down signals when the reference signal102lags the output signal121in phase.

Unfortunately, the phase detector113and the charge pump114have response limitations, i.e., bandwidth constraints. The narrower the phase difference between the reference signal102and the output signal121, the narrower the pulse widths of the digital pump up signals and digital pump down signals. Under conditions when the phase of the reference signal102and the output signal121is within a predetermined range of phase variance, the pump up signals and the digital pump down signals generally become too narrow to cause a response by the charge pump114. Accordingly, under such conditions, the charge pump114transitions to a non-responsive state which drops the gain of the digital PLL105to virtually zero.

Generally, under conditions when the charge pump114provides such a zero or null output to the output oscillator120, the digital PLL105is considered to be in a dead band state. The dead band state corresponds to a zone of operation in which the loop gain of the digital PLL105is essentially zero. The loss of digital PLL105gain within the dead band may be referred to as the dead band effect.

Depending on the digital implementation, the dead band effect may be a significant detriment. Typically, digital PLL designers go to great lengths to avoid the dead band effect because the dead band effect leads to greater phase noise. The phase noise is detrimentally affected especially close in frequency to the output signal121(i.e., at small offset frequencies from the output signal121), for which the digital PLL105has little control due to minimal loop gain.

Solutions for overcoming the dead band effect include narrowing the dead band. However, narrowing the dead band typically causes an increase in circuitry complexity and cost, e.g., a more responsive charge pump114. Other solutions include using the pulse width differences between the digital pump up signals and the digital pump down signals to adjust the charge pump114, or providing a slight phase/frequency offset to slightly unbalance the digital PLL105away from the dead band. The phase/frequency offset provides some loop gain, thereby allowing the digital PLL105to exert some control over the hybrid PLL100. Unfortunately, providing the phase/frequency offset is difficult to implement, requires specialized circuitry, drifts over temperature, and generally exacerbates phase noise and spurious signal issues.

SUMMARY OF THE INVENTION

One embodiment of the present invention is a frequency synthesizer that includes an analog phase lock loop configured to generate a first control signal based on a reference signal and an output signal from an output oscillator and a digital phase lock loop configured to generate a second control signal based on the reference signal and the output signal. The frequency synthesizer also includes a control circuit configured to monitor a phase difference between the output signal and the reference signal and assign control of the output signal to the first control signal and to the second control signal based on a comparison of the phase difference to a coarse phase value and a fine phase value.

Another embodiment of the present invention is a frequency synthesizer that includes an analog phase lock loop configured to generate a first control signal based on a reference signal and an output signal from an output oscillator and a digital phase lock loop configured to generate a second control signal based on the reference signal and the output signal. The frequency synthesizer further includes a control circuit configured to assign control of the output signal based on the phase difference between the output signal and the reference signal and establish a dead band state when the phase difference is within a predetermined phase range. The control circuit assigns control of the output signal to the first control signal when the digital phase lock loop is in the dead band state. The control circuit assigns proportional control of the output signal between the first control signal and the second control signal when the phase difference is within a capture range of the analog phase lock loop and within a capture range of the digital phase lock loop. The control circuit assigns control to the second control signal when the when the phase difference is greater than the capture range of the analog phase lock loop.

Another embodiment of the present invention is a method of generating an output carrier signal with an oscillator. The method includes generating a first control signal based on a reference signal and the output carrier signal with an analog phase lock loop, generating a second control signal based on the reference signal and the output carrier signal with a digital phase lock loop, and detecting a phase difference between the output carrier signal and the reference signal. The method further includes assigning control of the output signal to the first control signal and to the second control signal based upon a comparison of the phase difference to a first phase limit and a second phase limit. The first phase limit is smaller than the second phase limit.

DETAILED DESCRIPTION

In general, a hybrid frequency synthesizer is described herein. The hybrid frequency synthesizer includes an analog PLL and a digital PLL. The analog PLL provides an analog PLL control signal. The digital PLL provides a digital PLL control signal. The analog and/or digital PLL control signals provide overall phase and frequency control of an output oscillator. The output oscillator provides an output signal. Dependent upon operational states of the hybrid frequency synthesizer, the analog PLL and the digital PLL share control of the output oscillator and therefore share control of the output signal. A control circuit monitors a state of lock of the analog PLL and the digital PLL, assigns control of the output oscillator to the analog PLL and/or digital PLL, and conditions the loop gain and/or bandwidth parameters of the analog PLL and digital PLL as needed.

Through the control circuit and the analog PLL and digital PLL control signals, the analog PLL and the digital PLL share joint or separate control of the output oscillator with respect to operational states of the hybrid frequency synthesizer. For example, during one or more frequency acquisition states, the digital PLL controls the phase and the frequency of the output oscillator. During the one or more frequency acquisition states, the loop elements are configured to adjust loop gain and/or bandwidth parameters and condition the digital PLL control signal, accordingly to allow for fast frequency acquisition. During one or more phase capture modes, the digital PLL and the analog PLL share proportional control of the output oscillator. The loop elements are configured to adjust loop gain and/or bandwidth parameters accordingly for both the analog PLL and digital PLL to provide for rapid phase lock during the phase capture modes. During one or more steady state phase lock conditions, the analog PLL controls the phase and frequency control of the output oscillator. The loop elements are configured to adjust loop gain and/or bandwidth parameters accordingly to provide for a lower phase noise at the steady state phase lock conditions. During the steady state phase lock conditions the digital PLL is set to a base mode output to minimize noise.

The PLL control signals provide rapid, accurate, and robust acquisition while maintaining low noise operation. Because the digital PLL retains some measure of coarse input control of the output oscillator, the hybrid frequency synthesizer maintains lock over a wider range of conditions than a single analog PLL. In addition, the phase relationship between the reference signal and the output carrier signal can be maintained. Furthermore, although in some embodiments the analog PLL frequency locks accurately, the analog PLL may lose phase lock, in which case phase lock may be reacquired rapidly with the aid of the digital PLL. As the control circuit automatically assigns control of the output oscillator to the digital PLL and/or analog PLL, adjusts loop bandwidth and/or loop gain for the different modes between acquisition and locked states, the control circuit therefore configures the hybrid frequency synthesizer for optimum phase noise characteristics without sacrificing rapid acquisition and robust operation.

FIG. 2is a high level schematic illustration of one embodiment of a hybrid frequency synthesizer200, andFIGS. 3A–Dare high level schematic illustrations of alternative embodiments of a frequency multiplier224of the analog phase lock loop ofFIG. 2, in accordance with the invention. The hybrid frequency synthesizer200includes a reference oscillator202, the frequency multiplier224, an analog phase detector226, a divider219, a loop filter216A, and a control circuit214. The hybrid frequency synthesizer200also includes a frequency divider206, a digital frequency synthesizer205, a loop filter216B, an output oscillator217, and a digital output logic circuit230. An output signal227from the output oscillator217is coupled to an input of the digital logic circuit230. The digital logic circuit230is configured to direct the output signal227as an output signal250to external circuits (not shown) such as output buffer circuits, output dividers, etc. The reference oscillator202may be virtually any type of reference signal source such as a frequency generator, an oscillator, a voltage controlled oscillator (VCO), and a voltage controlled crystal oscillator (VCXO). The reference oscillator202may be operated by one or more input signals X1and X2. In one configuration, the reference oscillator202may include an analog dividing circuit, a down converter circuit, and the like. In another embodiment of the present invention, the reference oscillator202is replaced with an external reference clock.

In one configuration, the hybrid frequency synthesizer200includes an analog phase lock loop (PLL)240and a digital PLL242. It will be appreciated that the analog PLL240and the digital PLL242may comprise various components, however for clarity the description will focus on one configuration. The analog PLL240includes the reference oscillator202, the frequency multiplier224, the analog phase detector226, the divider219, the loop filter216A, and the output oscillator217. The analog PLL240provides an analog PLL control signal213to the output oscillator217. The analog PLL control signal213controls the output oscillator217and therefore the phase and frequency of the output signal227. In one configuration, the analog PLL control signal213provides fine control of the output signal227, i.e., provides fine adjustment to the frequency and/or phase of the output signal227relative to a digital PLL control signal212described herein.

The digital PLL242includes the reference oscillator202, the frequency divider206, the digital frequency divider207, a digital frequency/phase detector209, a charge pump211, the loop filter216B, and the output oscillator217. The digital PLL242provides the digital PLL control signal212to the output oscillator217. The digital PLL control signal212controls the output oscillator217and therefore the phase and frequency of the output signal227. In one configuration, the digital PLL control signal212provides coarse control of the output signal227, i.e., provides coarse adjustment to the frequency and/or phase of the output signal227relative to the analog PLL control signal213.

The control circuit214is configured to allocate overall PLL control of the output oscillator217and therefore the phase and frequency of the output signal227between the analog PLL control signal213and the digital PLL control signal212. In one configuration, the control circuit214assigns overall control of the output signal227to the analog PLL control signal213and/or to the digital PLL control signal212with respect to one or more operational states of the hybrid frequency synthesizer200as described further below.

In one embodiment of the analog PLL240, the reference signal203is coupled to the frequency multiplier224. The frequency multiplier224provides a multiple signal228in response to the reference signal203. In one configuration, the frequency multiplier224is configured to multiply the reference signal203to generate the multiple signal228, e.g., 1Fs, 2Fs, 3Fs. . . NFs. The frequency multiplier224may be any type of frequency multiplier device such as one or more fixed or programmable frequency doublers in a cascade, frequency up converters, and the like. The multiple signal228is coupled to an input of the analog phase detector226. A portion of the output signal227is processed by the divider219to form a divided signal220. The divided signal220is coupled to another input of the analog phase detector226. The analog phase detector226generates the analog PLL control signal213in response to mixing the multiple signal228and the divided signal220. The divider219may be virtually any type of divider circuit or device configured to divide the output signal227. For example, the divider219may be a fixed or a programmable digital divider circuit, an analog dividing circuit, a down converter circuit, and the like.

As illustrated inFIG. 3B, in one configuration, the frequency multiplier224may be configured as a frequency multiplier224B. The frequency multiplier224B includes a divider302coupled to an impulse generator303. The divider302may be virtually any type of digital frequency device such as a programmable digital frequency divider, a fixed digital frequency divider, a non-integer divider, a counter circuit, and the like. The impulse generator303includes an output coupled to an input of the analog phase detector226. The impulse generator303generates a very narrow width output pulse in response to the reference signal203. The narrow pulse generates a multiple signal228B having a plurality of harmonic frequencies of the reference signal203, e.g., Fs, 2Fs, 3Fs. . . NFs, where N is a harmonic number, as illustrated inFIG. 3A. The narrow pulse is sufficiently narrow in time to generate a large number of harmonics with substantially equal amplitude. The impulse generator303may include one or more impulse devices such as a comb generator circuit, a step recovery diode circuit, and the like, to provide the harmonics.

As illustrated inFIG. 3C, in one embodiment, the frequency multiplier224may be configured as frequency multiplier224C. The frequency multiplier224C includes a cascade of frequency multiplier devices304coupled to the divider302. The combination of the frequency multiplier devices304and the divider302is configured to multiply and divide the reference signal203to a multiple signal228C. One configuration of frequency multiplier devices304includes analog mixers configured as frequency doublers.

As illustrated inFIG. 3D, in one configuration, the frequency multiplier224may be configured as a frequency multiplier224D. The frequency multiplier224D may include a delay locked loop (DLL) circuit301and the divider302. The combination of the DLL circuit301and the divider302is configured to generate both integer and non-integer multiples of the reference signal203input thereto. The DLL circuit301may be virtually any type of DLL apparatus and circuit that may be used to advantage.

Referring toFIG. 2andFIGS. 3A–D, the analog phase detector226may be a mixer configured to mix the divided signal220and the multiple signal228together to generate the analog PLL control signal213. The analog PLL control signal213is generated by the analog phase detector226in response to a phase difference and a frequency difference between the divided signal220and the multiple signal228. The analog phase detector226may be virtually any mixer type or circuit configured to mix the multiple signal228and the divided signal220together. In one configuration, the frequency multiplier224and the analog phase detector226are configured such that phase difference between the divided signal220and the multiple signal228is about zero degrees or 90 degrees or multiples thereof.

The analog PLL control signal213may be virtually any type of PLL control signal type that may be used to advantage. For example, in one embodiment, the analog PLL control signal213is configured as a voltage signal Ve. An amplitude and frequency of the voltage signal Ve indicates the phase difference and the frequency difference between the divided signal220and the multiple signal228. The analog PLL control signal213is provided to an input of the control circuit214for processing as described further herein. For clarity, the analog PLL control signal213is described herein in terms of a voltage signal. However, other types of PLL control signals, such as current signals, are contemplated.

Referring toFIG. 2, in one embodiment of the digital PLL242, the digital frequency synthesizer205includes the frequency divider206, the digital frequency divider207, a digital frequency/phase detector209, and the charge pump211. A sample of the output signal227is coupled to an input of the digital frequency divider207. The frequency divider206is configured to generate a divided reference signal204in response to the reference signal203. The divided reference signal204is coupled to an input of the digital frequency/phase detector209. The frequency divider206and the digital frequency divider207may be virtually any type of digital frequency device such as a programmable digital frequency divider, a fixed digital frequency divider, a non-integer divider, a counter circuit, and the like.

The digital frequency divider207is configured to provide a digitally divided signal208having a similar frequency to that of the divided reference signal204to an input of the digital frequency/phase detector209. The digital frequency/phase detector209determines a phase difference and a frequency difference between the digitally divided signal208and the divided reference signal204received thereto. The digital frequency/phase detector209is configured to generate an error signal210in response to such frequency and phase differences. The error signal210is coupled to an input of the charge pump211. The charge pump211is configured to generate the digital PLL control signal212in response to the error signal210. The digital PLL control signal212is coupled to an input of the loop filter216B for conditioning as described further herein.

In one operational embodiment, the analog PLL240and the digital PLL242are configured to separately or jointly control the output oscillator217and therefore the output signal227relative to one or more operational states of the hybrid frequency synthesizer200. For example, during a frequency acquisition state of the hybrid frequency synthesizer200where the phase difference between the output signal227and the reference signal203is outside the phase lock capture range of the analog PLL240, the control circuit214assigns the digital PLL242with coarse control of the output oscillator217. During a phase lock capture where the phase difference between the output signal227and the reference signal203is within the phase lock capture range of the analog PLL240and the digital PLL242, the analog PLL240and the digital PLL242proportionally control the output oscillator217. During a phase lock state when the analog PLL240is in a phase locked state and the output signal227is within the capture range of the analog PLL240, the analog PLL240provides control of the output oscillator217. Thus, depending on the phase difference between the output signal227and the reference signal203, the control circuit214assigns control only to the digital PLL242, or only the analog PLL240, or proportional control to both the digital PLL242and the analog PLL240.

In one operational embodiment, with reference to the analog PLL240, the analog phase detector226mixes the multiple signal228to the divided signal220to generate the analog PLL control signal213. A portion of the output signal227is coupled to an input of the divider219. The divider219provides the divided signal220to the analog phase detector226. The control circuit214monitors the phase lock state of the analog PLL240via the analog control signal213. The control circuit214may also monitor the phase lock state of the analog PLL240using a phase detector output signal221from the digital PLL242. The analog PLL control signal213is coupled to a fine input of the output oscillator217via the loop filter216A to control the phase and the frequency of the output signal227. The fine input of the output oscillator217generally provides more accurate control of the output signal227relative to a coarse control input of the output oscillator217. Thus, the analog PLL control signal213finely controls the phase and frequency of the output oscillator217.

With respect to the digital PLL242, the divided reference signal204and a portion of the output signal227are coupled to the digital frequency synthesizer205. The digital frequency synthesizer205generates the digital PLL control signal212and a digital phase signal221in response to the phase difference between the reference signal203and the portion of the output signal227coupled thereto. The control circuit214monitors the phase lock state of the digital PLL242via the digital control signal212and/or the digital phase signal221. The digital PLL control signal212is coupled to a coarse input of the output oscillator217via the loop filter216B to control the phase and the frequency of the output signal227. The digital PLL control signal212coarsely controls the output oscillator217relative to the fine input. Therefore, as both the analog PLL control signal213and the digital control signal212are coupled to the output oscillator217and jointly or independently control output oscillator217, the control circuit214can rapidly assign control of the output oscillator217to the analog PLL240, the digital PLL242, or both.

FIG. 4is a high level schematic illustration of one embodiment of the control circuit214ofFIG. 2, in accordance with the invention. The control circuit214includes an analog PLL lock detector402, a digital PLL lock detector408, a charge pump control circuit404, and a loop filter control circuit403. The analog PLL lock detector402is configured to determine one or more lock states of the analog PLL240. In one embodiment, the analog PLL lock detector402determines a phase and a frequency lock state of the analog PLL240in response to a voltage level Ve of the analog PLL control signal213. In another embodiment, the analog PLL lock detector402determines the phase and the frequency lock state of the analog PLL240in response to a current level of the analog PLL control signal213.

The digital PLL lock detector408is configured to determine one or more lock states of the digital PLL242. In one embodiment, the digital PLL lock detector408determines a phase and a frequency lock state of the digital PLL242in response to a current level Ie of the digital PLL control signal212. In another embodiment, the digital PLL lock detector408determines the phase and the frequency lock state of the digital PLL242in response to a voltage level of the digital PLL control signal212. In one configuration, the digital frequency/phase detector209(SeeFIG. 2) couples phase/frequency lock data, e.g., a digital word of virtually any length, indicative of a phase/frequency lock state of the digital PLL242, to the digital PLL lock detector408via the digital phase signal221. The digital PLL lock detector408processes such digital phase/frequency lock data to determine a phase and a frequency lock state of the digital PLL242. In other embodiments, the digital PLL lock detector408determines the phase and frequency lock state of the digital PLL242in response to a pulse width of the output signal210of the digital frequency/phase detector209and/or a pulse width of the digital PLL control signal212.

In one embodiment, the digital PLL lock detector408monitors the state of phase lock of the analog PLL240. For example, when the digital PLL lock detector408determines that the digital PLL242is phase locked, the analog PLL is also considered phase locked. In another embodiment, the digital frequency/phase detector209is configured with a dead band condition. The dead band condition is defined herein as the predefined range where the output of the phase detector209of the digital PLL242is unable to respond to small phase differences between the divided reference signal204and the digitally divided signal208. The gain of the digital PLL242is virtually zero within the dead band condition. Conversely, when the digital PLL lock detector408determines that the digital PLL242is not phase locked, and is not in the dead band condition, the analog PLL is considered not phase locked. Therefore, in this configuration, the digital PLL lock detector408monitors the analog PLL240by associating phase lock conditions of the digital PLL242to the analog PLL240.

In one operational embodiment, the control circuit214assigns the control of the output oscillator217between the analog PLL240and the digital PLL242relative to one or more operational states of the hybrid frequency synthesizer200. For example, when the hybrid frequency synthesizer200is in a frequency acquisition mode, the control circuit214assigns the control of the output oscillator217to the digital PLL242. When the hybrid frequency synthesizer200is in a phase capture mode, the control circuit214assigns proportional control of the output oscillator217to the digital PLL242and the analog PLL240. When the hybrid frequency synthesizer200is in a phase locked mode, the control circuit214assigns proportional control of the output oscillator217to the analog PLL240and sets the digital PLL242to a base output mode.

In one operational embodiment, during the phase capture mode, the control circuit214varies such proportional PLL control between the digital PLL control signal212and the analog PLL control signal213relative to changing operational states of the hybrid frequency synthesizer200. For example, the further away the analog PLL240is from a phase locked state, the control circuit214assigns a greater portion of the overall PLL control to the digital PLL control signal212and less control to the analog PLL control signal213. Conversely, the closer the analog PLL240is to the phase locked state, the control circuit214assigns a reduced portion of the overall PLL control to the digital PLL control signal212and a greater portion to the analog PLL control signal213.

In one embodiment, the charge pump211is controlled by the charge pump control circuit404. The charge pump control circuit404generates a charge pump control signal222in response to the digital phase signal221and/or a digital lock state signal412from the digital PLL lock detector408. In one embodiment, the proportional control of the digital PLL242is implemented by controlling the charge pump211via the charge pump control signal222with respect to the digital phase signal221and/or the digital lock state signal412. For example, the further the analog PLL240is from the phase lock state, the parameters of the charge pump211are adjusted such that the digital PLL control signal212is large relative to the analog PLL control signal213, thereby giving the digital PLL242a larger portion of the overall PLL control. Conversely, in the phase lock state, the parameters of the charge pump211may be adjusted such that the digital PLL control signal212is set to a base output condition configured to give the analog PLL240control of the output oscillator217

In one embodiment, the filter control circuit403adjusts the loop gain/bandwidth of the analog PLL240and the digital PLL242relative to one or more operational states of the hybrid frequency synthesizer200. The filter control circuit403receives input from the digital phase signal221and the analog PLL lock detector402via an analog lock signal410. The filter control circuit403also receives input from the digital PLL lock detector408via a digital lock signal414. The filter control circuit403may use the digital phase signal221, the analog lock signal410, and the digital lock signal414, and combinations thereof, to determine the lock states of the analog PLL240and the digital PLL242and to determine their loop gain/bandwidth settings.

In one configuration, in response to the digital phase signal221, the analog lock signal410, and the digital lock signal414, the filter control circuit403adjusts the loop gain of the analog PLL240and the digital PLL242via scaling the analog PLL control signal213and the digital PLL control signal212. For example, scaling the response of the analog PLL control signal213sets the analog PLL240loop gain. The response of the analog PLL240may be controlled via the filter control circuit403adjusting parameters of the loop filter216A via a filter control signal225. Similarly, the filter control circuit403adjusts the loop gain of the digital PLL242by scaling the response of the digital PLL control signal212. The response of the digital PLL242may be controlled via the filter control circuit403adjusting parameters of the loop filter216B via the filter control signal229as described herein.

For example, during the frequency acquisition mode, the digital PLL242is responsible for an initial frequency acquisition and an initial phase lock of the output signal227. In one embodiment, the digital PLL242is configured to set the output oscillator217such that the analog PLL240may frequency and phase lock the divided signal220to a desired harmonic of the reference signal203(SeeFIGS. 2 and 3). To provide a faster frequency acquisition, the loop gain of the analog PLL240may be scaled down (e.g., decreased loop gain) by adjusting the loop filter216A, and the loop gain of the digital PLL242may be scaled up (e.g., increased loop gain), such that the digital PLL242is dominant in phase lock control.

When the output signal227approaches a predetermined steady state phase lock condition, the filter control circuit403may set the analog PLL240, via loop filter216A, to a steady state loop gain/bandwidth setting, and adjust the digital PLL242, via loop filter216B, to a base gain/bandwidth state. If such steady state condition is interrupted, the filter control circuit403may adjust the loop gain/bandwidth of the digital PLL242and the analog PLL240to allow the digital PLL242to rapidly regain dominant loop control until the predetermined phase lock condition is met. Subsequently, once the steady state phase lock condition is met, the filter control circuit403sets the loop gains/bandwidths of the analog PLL240and the digital PLL242to enable the analog PLL240to regain dominant loop control, and sets the digital PLL242to the base gain state.

FIG. 5Ais a high level schematic illustration of one embodiment of the loop filter216A ofFIG. 2, in accordance with the invention. The loop filter216A includes an input resistor503A, a filter control circuit502A, and a plurality of switched resistors504A. The loop filter216A is configured as a low pass to average the analog PLL control signal213coupled thereto. The capacitance C1and the resistance between the input of R1and the input of C1determine the bandwidth of the loop filter216A. The loop filter216A is configured to adjust analog loop gain and/or bandwidth with respect to operational states of the hybrid frequency synthesizer200. The loop filter216A may be a low pass filter of virtually any order. In one configuration, the loop filter216A may be configured as an integrator circuit.

The switched resistors504A are controlled by the filter control circuit502A via the filter control signal225. The filter control circuit502A may be virtually any device or circuit configured to operate the switched resistors504A. For example, the filter control circuit502A may be a differential transistor circuit, an operational amplifier circuit, and the like, configured to operate the switched resistors504A.

FIG. 5Bis a high level schematic illustration of one embodiment of the loop filter216B ofFIG. 2, in accordance with the invention. The loop filter216B includes an input resistor503B, a filter control circuit502B, and a plurality of switched resistors504B. The loop filter216B is configured as a low pass to average the digital PLL control signal212coupled thereto. The capacitance C1and the resistance between the input of R1and the input of C1determine the bandwidth of the loop filter216B. The loop filter216B is configured to configure digital loop gain and/or bandwidth with respect to operational states of the hybrid frequency synthesizer200. The loop filter216B may be a low pass filter of virtually any order. In one configuration, the loop filter216B may be configured as an integrator circuit.

The switched resistors504B are controlled by the filter control circuit502B via a filter control signal229. The filter control circuit502B may be virtually any device or circuit configured to operate the switched resistors504B. For example, the filter control circuit502B may be a differential transistor circuit, an operational amplifier circuit, and the like, configured to operate the switched resistors504B.

In an alternate embodiment of the invention, certain functions of the control circuit214can be included in the digital frequency/phase detector209. In this alternate embodiment, the digital frequency/phase detector209may be configured to establish a predefined dead band condition. The predefined dead band condition, DB, may be established at a predetermined phase difference between the divided reference signal204and the digitally divided signal208where the digital frequency/phase detector209and the charge pump211force the loop gain of the digital PLL to virtually zero.

During the frequency acquisition mode where the phase difference between the reference signal203and the output signal227is large, the digital PLL242has dominant control of the output oscillator217. As the digital PLL242forces the output signal227towards phase lock, the phase difference between the divided reference signal204and the digitally divided signal208narrows. When the dead band condition is met, the loop gain of the digital PLL242transitions to virtually zero causing the analog PLL240to automatically gain full control of the output oscillator217.

If conditions are disturbed such that the phase difference between the divided reference signal204and the digitally divided signal208widens such that the dead band condition is not met, the loop gain of the digital PLL242returns to its normal state, automatically giving the digital PLL242control of the output oscillator217.

In summary, the hybrid frequency synthesizer200includes the analog PLL240to provide the analog PLL control signal213and the digital PLL242to provide the digital PLL control signal212. Depending upon the phase between the reference signal203and the output signal227, the analog PLL control signal213and/or the digital PLL242provide phase and frequency control of the output oscillator217and therefore the output signal227. When the phase difference is outside the capture range of the analog PLL240, the digital PLL242coarsely controls the phase lock. When the phase difference is within the capture range of the analog PLL240and the digital PLL242, the analog PLL240and the digital PLL242proportionally share control of the output oscillator217with respect to operational states of the hybrid frequency synthesizer200. When the analog PLL240is phase locked, the analog PLL240finely controls the output oscillator217.

FIG. 6is a high level flow diagram of one embodiment of a method600of controlling the hybrid frequency synthesizer200ofFIG. 2, in accordance with the invention. The method600may be entered into at step601when, for example, the hybrid frequency synthesizer200is configured by a user thereof to generate the output signal227. At step602, the control circuit214initializes the loop parameters of the analog PLL240, assigns control of the output oscillator217to the digital PLL242, and sets the loop filter216B to a frequency acquisition mode to allow the digital PLL242faster response.

At step604, the control circuit214receives the digital PLL control signal212indicative of a phase/frequency lock state of the digital PLL242and the analog PLL control signal213indicative of a phase lock state of the analog PLL240.

At step606, the control circuit214determines the phase lock state of the analog PLL240and the digital PLL242. For example, the control circuit214may determine the lock state of the analog PLL240by monitoring the analog PLL control signal213with analog PLL lock detector402(FIG. 4). The control circuit214may determine the lock state of the analog PLL240by monitoring digital PLL control signal212with the digital lock detector408(FIG. 4) and/or by monitoring the phase detector output signal221, for example. The control circuit214determines the lock state of the digital PLL242by monitoring the digital PLL control signal212with the digital lock detector408and/or by monitoring the phase detector output signal221.

If at step608, the method600determines that the output signal227is within a phase lock capture range of the analog PLL240, the method600proceeds to step614described below. If at step608, the method600determines that the output signal227is not within the phase lock capture range of the analog PLL240, the method600returns to step602.

At step614, if the analog PLL240is phase locked, then the method600proceeds to step616described below. If however, the analog PLL240is not phase locked then the method600proceeds to step612. At step612, the control circuit214assigns proportional control of the output oscillator217to both the analog PLL240and the digital PLL242. For example, the digital PLL242provides a coarse control of the output oscillator217via the digital PLL control signal212. The analog PLL240provides fine control of the output oscillator217via the analog PLL control signal213. At step610, the loop filters216A and216B are set to provide loop gain/bandwidths of the analog PLL240and the digital PLL242, respectively, that allow for rapid phase lock capture of the output signal227. For example, the further the phase lock state of the analog PLL240is from phase lock the loop filters216A and216B will be adjusted to provide the digital PLL242with more gain relative to the analog PLL240. Conversely, the closer the analog PLL240is to a phase lock condition, the loop filters216A and216B will be adjusted to provide the analog PLL240with more gain relative to the digital PLL242.

At step616, when the analog PLL240is phase locked, the control circuit214assigns control over the frequency and the phase of the output signal227to the analog PLL240. At step618, the method600sets the digital PLL242to a base mode. In one embodiment, the base mode may be a dead band state of the digital PLL242where the gain of the digital PLL242is desensitized. The base mode may also be the control circuit214adjusting the output signal210to a predetermined pulse width output. At step620, the method600configures the loop parameters, such as loop gain, of the analog PLL240relative to a phase locked condition for lower phase noise. At step622, if the method600is finished, then the method600proceeds to step624and ends. If however, the method600is not finished, the method600proceeds to step606.

An advantage of the hybrid frequency synthesizer200is that the control circuit214provides rapid, accurate, and robust acquisition while maintaining low noise operation. Because the digital PLL242monitors and retains some measure of control over the output oscillator217, the hybrid frequency synthesizer200maintains lock over a wider range of conditions than a single analog PLL. In addition, the phase relationship between the reference signal203and the output signal227can be maintained. Furthermore, although in some embodiments the analog PLL240frequency locks very well, the analog PLL240may lose phase lock, in which case phase lock may be reacquired rapidly with the aid of the digital PLL242. The control circuit214automatically adjusts loop bandwidth and/or loop gain for the different modes between acquisition and locked states. Further, in one configuration, the digital PLL242is configured to include a predefined dead band condition. Once the predefined dead band condition is initiated, the control circuit214assigns control of the hybrid PLL to the analog PLL240and desensitizes the control contribution of the digital PLL242. The control circuit214therefore provides optimal noise characteristics for the hybrid frequency synthesizer200without sacrificing rapid acquisition and robust operation.

A further advantage of the hybrid frequency synthesizer200is that the PLL loop bandwidth and/or gain can be automatically adjusted for the different modes between acquisition, locked states, and one or more dead band conditions. The loop parameters therefore provide optimal noise characteristics for the hybrid frequency synthesizer200without sacrificing rapid acquisition and robust operation.

The invention has been described above with reference to specific embodiments. Persons skilled in the art, however, will understand that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims.