Vertical device 4F2 EEPROM memory

EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating gate memory cells to form NOR and NAND architecture memory cell strings, segments, and arrays. These memory cell architectures allow for improved high density memory devices or arrays with integral select gates that can take advantage of the features semiconductor fabrication processes are generally capable of and allow for appropriate device sizing for operational considerations. The memory cell architectures also allow for mitigation of disturb and overerasure issues by placing the floating gate memory cells behind select gates that isolate the memory cells from their associated bit lines and/or source lines.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and in particular the present invention relates to EEPROM memory devices.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.

Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a memory array which includes a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Each of the cells within an EEPROM memory array can be electrically programmed in a random basis by charging the floating gate. The charge can also be randomly removed from the floating gate by an erase operation. Charge is transported to or removed from the individual floating gates by specialized programming and erase operations, respectively.

Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.

The memory cells of both an EEPROM memory array and a Flash memory array are typically arranged into either a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).

A problem in floating gate memory cell arrays is the issue of overerased memory cells. A floating gate memory cell is structurally similar to a MOSFET transistor, with a control gate separated from a channel, source, and drain by an insulator. In addition, embedded in the insulator is an isolated floating gate. As in a MOSFET transistor, current flows when the floating gate memory cell/transistor is selected or activated, charge trapped on the floating gate affects the amount of current flow in the floating gate transistor, effectively raising or lowering its threshold. In programming or erasing a floating gate memory cell, charge is transported to or from the electrically insulated floating gate of the floating gate transistor. If too much charge is removed from the floating gate of the floating gate transistor/memory cell it will flow current even when it is not selected. Floating gate transistors in this overerased state can affect current flow on shared bitlines and/or memory strings and thus potentially corrupt data read from other memory cells these common bitlines and/or memory strings.

In addition, as integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. In floating gate memory arrays in particular, the channel length of the floating gate memory cells that make up the memory array and spacing between memory cells in the strings have a large effect on the number of memory cells that can be placed in a given area and thus a direct impact on the density of the array and size of the resulting memory device.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and architecture for producing a more closely spaced and, thus, higher density floating gate memory array with improved overerasure handling properties.

SUMMARY OF THE INVENTION

The above-mentioned problems with producing a more closely spaced and higher density floating gate memory array with improved overerasure handling properties and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

EEPROM memory devices and arrays, in accordance with embodiments of the present invention, facilitate the utilization of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating gate memory cells to form NOR and NAND architecture memory cell strings, segments, and arrays. These memory cell architectures allow for improved high density memory devices or arrays with integral select gates that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and allow for appropriate device sizing for operational considerations. The memory cell architectures also allow for mitigation of disturb and overerasure issues by placing the floating gate memory cells behind select gates that isolate the memory cells from their associated bit lines and/or source lines.

For one embodiment, the invention provides a memory device comprising a NOR architecture floating gate memory array formed on a substrate having a plurality of pillars and associated intervening trenches, and a plurality of memory cell structures. Each memory cell structure having a floating gate memory cell, wherein the floating gate memory cell is formed vertically on a first sidewall of a trench, and a select gate, wherein the select gate is formed on a second sidewall of the trench and wherein the select gate is coupled to the floating gate memory cell by a source and drain region formed at the bottom of the trench.

For another embodiment, the invention provides a floating gate memory cell structure comprising a substrate, having two raised areas, defining a trench therebetween. A floating gate memory cell is formed vertically on a first sidewall of the trench, and a select gate memory cell is formed vertically on a second sidewall of the trench. Where the floating gate memory cell is coupled to the select gate by source and drain region formed at the bottom of the trench.

For yet another embodiment, the invention provides a method of forming a floating gate memory cell structure comprising forming two raised areas on a substrate, the raised areas defining an associated intervening trench. Forming a floating gate memory cell on a first sidewall of the trench and a select gate on a second sidewall of the trench, and forming a source and drain region at the bottom of the associated intervening trench.

For a further embodiment, the invention provides a NAND architecture floating gate memory cell string comprising a substrate, having two or more raised areas, defining trenches therebetween. A plurality of floating gate memory cells are formed vertically on the sidewalls of the trenches, wherein the plurality of floating gate memory cells are coupled in a serial string by source/drain regions formed at the top of the two or more raised areas and at the bottom of the one or more trenches. A first floating gate memory cell is coupled to a first select gate, where the first select gate is formed vertically on a sidewall of a selected trench.

For yet a further embodiment, the invention provides a memory device comprising a NAND architecture memory array formed on a substrate having a plurality of pillars and associated intervening trenches. The memory array having a plurality of floating gate memory cells formed vertically on the sidewalls of the plurality of pillars and trenches, wherein the plurality of floating gate memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches. A first floating gate memory cell of each string of the array is coupled to a first vertical select gate and a last floating gate memory cell of each NAND architecture memory string is coupled to a second vertical select gate. The memory device also comprises a control circuit, a row decoder, a plurality of word lines coupled to the row decoder, a plurality of select lines, at least one bitline, and at least one source line. Wherein each word line is coupled to one or more control gates of one or more floating gate memory cells, where each of the one or more floating gate memory cells is from a differing string of the plurality of NAND architecture memory strings. Each select line is coupled to one or more select gates. The at least one bitline is coupled to a drain of the first select gate of each string of the plurality of NAND architecture memory strings. And the at least one source line is coupled to a source of the second select gate of each string of the plurality of NAND architecture memory strings.

For another embodiment, the invention provides a method of forming a NAND architecture memory cell string comprising forming one or more raised areas on a substrate, the raised areas defining associated intervening trenches, forming a plurality of floating gate memory cells on the sidewalls of the one or more raised areas, forming one or more source/drain regions on the top of the one or more raised areas and at the bottom of the one or more associated intervening trenches, and forming a first vertical select gate coupled to a first floating gate memory cell of the NAND architecture memory string and a second vertical select gate coupled to a last floating gale memory cell of the NAND architecture memory string.

Other embodiments are also described and claimed.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The terms wafer and substrate used previously and in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims and equivalents thereof.

EEPROM memory devices and arrays, in accordance with embodiments of the present invention, facilitate the utilization of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating gate memory cells to form NOR and NAND architecture memory cell segments and arrays. These memory cell architectures allow for improved high density memory devices or arrays with integral select gates that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and allow for appropriate device sizing for operational considerations. The memory cell architectures also allow for mitigation of disturb and overerasure issues by placing the floating gate memory cells behind select gates that isolate the memory cells from their associated bit lines and/or source lines.

As stated above, as integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. In many cases, the feature sizes of the devices are limited by the device characteristics before the minimum feature size that the process is capable of is reached. In both NAND and NOR architecture EEPROM memory arrays, as the channel length is reduced and the spacing between memory cells in the strings are reduced, a minimum size is reached that is primarily dictated by the operational characteristics of the floating gate memory cell devices that make up the memory array. As a result, the maximum density of an array of memory cells is limited even if the process technology can attain even smaller features and/or channel lengths. In particular, this is an issue in higher capacity memory types where small changes in the memory cell footprint (e.g., memory cell channel widths) and the cell density in the array can have a large effect on the overall array size and the resulting storage capacity.

As stated above, programming a floating gate memory cell involves the insertion and storage of charge on the memory cell's floating gate. Typically, a floating gate memory cell electrically operates as an enhancement type MOS transistor, requiring a positive voltage applied across the gate and channel to flow current. The presence, or lack thereof, of a trapped charge on the floating gate of the floating gate transistor/memory cell alters the threshold voltage characteristics of this transistor and thus the amount of current the transistor will flow at a given gate channel voltage. The effective threshold voltage of the floating gate transistor memory cell increases with storage of electrons on the floating gate and decreases with the removal of stored charge. Reading floating gate memory cells in EEPROM memory arrays is then accomplished by accessing a memory cell with selected read voltage levels on the control gate and source line. The stored data is then typically sensed from the amount of current the floating gate memory cell flows through the coupled bit line.

In programming floating gate memory cells in EEPROM memory arrays, electrons are typically transferred to the floating gate of the memory cell by one of Fowler-Nordheim tunneling (FN-Tunneling) or channel hot electron injection (HEI). Other forms of programming floating gate memory cells, such as, substrate enhanced hot electron injection (SEHE), are also known and utilized. FN-Tunneling is typically accomplished by applying a positive control gate voltage on the floating gate memory cell with respect to its substrate or surrounding P-well to tunnel inject electrons to the floating gate. Channel hot electron injection (HEI) is typically accomplished by applying a positive voltage on the control gate and drain of the floating gate memory cell and a low voltage or ground on the source to inject electrons to the floating gate. In many cases the programming voltages are iteratively pulsed and the memory cell read to check the programming process and more accurately program the floating gate memory cell.

Erasure of the floating gate memory cells of EEPROM memory arrays is typically accomplished by conventional tunneling or negative voltages applied to the control gate voltages with respect to the substrate or surrounding isolation P-well. Alternatively, other forms of erasure, such as, substrate enhanced band to band tunneling induced hot hole injection (SEBBHH) can also be used for floating gate memory cell erasure. To ensure uniformity, in many cases the EEPROM memory programs all the floating gate memory cells in the data segment to be erased before applying the voltages to erase the memory cells. As with programming, the erasure voltages are typically iteratively pulsed and the memory cells checked after each pulse to verify erasure and return of the floating gate memory cells to an un-programmed threshold voltage state.

Unfortunately, it is possible, during an erasure process, for too much charge to be removed from the floating gate of a floating gate memory cell transistor placing it in to an “overerased” state. In such cases, enough charge is removed that the threshold voltage of the floating gate memory cell transistor is altered so that it operates as a depletion mode device, requiring a negative control gate-channel voltage to be applied to shut off current flow. In this state, the floating gate memory cell transistor will flow a current even when it has not been selected by the memory, unless a negative voltage is applied to the control gate with respect to the source. This “overerased” state and the resulting current flow when the overerased floating gate memory cell is unselected can interfere with attempts to read the values of other floating gate memory cells that share the common bit lines with it, corrupting the read data.

Complicating the issue of overerasure in floating gate memory cells is that not all floating gate memory cells erase (remove charge from their floating gates) at the same rate of speed. Typically, one or more “fast erasing” memory cells will erase more quickly than the others of the group of cells selected for erasure. To minimize the possibility of inadvertently overerasing this group of fast erasing floating gate memory cells most EEPROM and Flash memory devices/arrays typically utilize the complex and time consuming iterative erase voltage pulse-memory cell verify process noted above to erase its floating gate memory cells.

FIG. 1Adetails a chart of a distribution of threshold voltages100of floating gate memory cells in a given array, showing distribution bell curves of the threshold voltages of floating gate memory cells placed in a programmed102and erased104state as might be typical of a floating gate memory device.FIG. 1Aalso details a number of erased cells that have been inadvertently placed in an overerased (depletion mode)106state.FIG. 1Bdetails a bit line10of a memory array112and the current flow114through an overerased floating gate memory cell116that has not been selected/activated for reading.

An additional issue that can affect the memory cells of an EEPROM or Flash memory array is “disturb.” Disturb typically happens when the elevated voltages used to program or erase a floating gate memory cell segment or erase block “disturb” the programmed values stored in other floating gate memory cells corrupting them and causing errors when they are later read. These inadvertently disturbed cells typically share common word lines, bit lines, or source lines with the memory cells that are being programmed or erased.

By constructing their floating gate memory cells vertically and isolating them with select gates, embodiments of the present invention allow for increases in memory array cell density and improved utilization of process minimum feature size capabilities, while maintaining the size of the memory cell channel to allow for appropriate device operation. In addition, by increasing the available surface area for transistors and incorporating select gates, which are also constructed in a vertical manner, embodiments of the present invention mitigate issues with overerasure and disturb, allowing for greater reliability and faster programming and erasure.

As previously stated, the two common types of EEPROM and Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the similarity each basic memory cell configuration has to the corresponding logic gate design. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix similar to RAM or ROM. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines (word lines) and their drains are coupled to column bit lines. The source of each floating gate memory cell is typically coupled to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line coupled to their gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current from the coupled source line to the coupled column bit lines depending on their programmed states. A column page of bit lines is selected and sensed, and individual data words are selected from the sensed data words from the column page and communicated from the memory.

An EEPROM or Flash NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word lines. However each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. This allows a NAND array architecture to have a higher memory cell density than a comparable NOR array, but with the cost of a generally slower access rate and programming complexity.

A NAND architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each floating gate memory cell of the series coupled string, restricted only by the memory cells of each string that are selected to be read. This places the current encoded stored data values of the row of selected memory cells on the column bit lines. A column page of bit lines is selected and sensed, and then individual data words are selected from the sensed data words from the column page and communicated from the memory device.

FIGS. 2A,2B, and2C show a simplified planar NOR floating gate memory array of a EEPROM or Flash memory device of the prior art.FIG. 2Adetails a top view of a planar NOR architecture floating gate memory array200, a side view of the planar NAND floating gate memory array200is detailed in FIG.2B. InFIGS. 2Aand2B, floating gate memory cells202are coupled together in a NOR architecture memory array having bit lines212, source lines214, and word lines206. The bit lines212and source lines214are formed locally from N+ doped regions deposited in the substrate208. Each floating gate memory cell202has a gate-insulator stack formed between the N+ doped regions of a bit line212and a source line214, utilizing the N+ doped regions as a drain and source respectively. The gate-insulator stack is made of a tunnel insulator on top of a substrate208, a floating gate formed on the tunnel insulator, an intergate/interpoly insulator formed over the floating gate, and a control gate206(typically formed integral to the word line206, also known as a control gate line) formed over the intergate/interpoly insulator.FIG. 2Cdetails an equivalent circuit schematic220of the NOR architecture floating gate memory array200, showing floating gate memory cells202coupled to the bit lines, source lines, word lines, and substrate connection222.

FIGS. 3A,3B, and3C show a simplified planar NAND floating gate memory array of a EEPROM or Flash memory device of the prior art.FIG. 3Adetails a top view of a planar NAND floating gate memory string304of a NAND architecture floating gate memory array300, a side view of the planar NAND floating gate memory string304is detailed in FIG.3B. InFIGS. 3A and 3B, a series of floating gate memory cells302are coupled together in a series NAND string304(typically of 8, 16, 32, or more cells). Each floating gate memory cell302has a gate-insulator stack that is made of a tunnel insulator on top of a substrate308, a floating gate formed on the tunnel insulator, an intergate/interpoly insulator formed over the floating gate, and a control gate306(typically formed in a control gate line, also known as a word line) formed over the intergate/interpoly insulator. N+ doped regions are formed between each gate insulator stack to form the source and drain regions of the adjacent floating gate memory cells, which additionally operate as connectors to couple the cells of the NAND string304together. Select gates310, that are coupled to gate select lines, are formed at either end of the NAND floating gate string304and selectively couple opposite ends of the NAND floating gate string304to a bit line contact312and a source line contact314.FIG. 3Cdetails an equivalent circuit schematic320of the NAND architecture floating gate memory string304, showing floating gate memory cells302and substrate connection322.

Embodiments of the present invention utilize vertical floating gate memory cells and vertical gate structures. Methods of forming vertical memory cells are detailed in U.S. Pat. No. 5,936,274, titled “High density flash memory”, issued Aug. 10, 1999, which is commonly assigned. Methods of forming vertical split control gates are detailed U.S. Pat. No. 6,150,687, titled “Memory cell having a vertical transistor with buried source/drain and dual gates”, issued Nov. 21, 2000, and U.S. Pat. No. 6,072,209, titled “Four F2folded bit line DRAM cell structure having buried bit and word lines”, issued Jun. 6, 2000, which are also commonly assigned.

FIGS. 4A-4Cdetail vertical floating gate memory cells and select gates for a NOR architecture floating gate memory array in accordance with embodiments of the present invention.FIG. 4Adetails a side view of a simplified vertical NOR architecture memory cell structure404, a side view of a vertical NOR memory array400is detailed in FIG.4B.FIG. 4Cdetails an equivalent circuit schematic420of the vertical NOR architecture floating gate memory array400, showing floating gate memory cells402and substrate connection422. It is noted that the NOR architecture floating gate memory array400can be utilized in both EEPROM or Flash memories arrays and devices. As can be seen fromFIGS. 4A and 4B, in a single vertical NOR architecture memory cell structure404, two vertically formed transistors occupy the area that a single planar floating gate transistor would occupy (an area of 4F squared when viewed from above, each transistor having an area of 2F squared). Where “F” is the minimum resolvable photolithographic dimension in the particular process technology.

InFIG. 4A, a vertically formed floating gate memory cell402and select gate410are coupled together in series in a vertical NOR architecture memory cell structure404. In creating the vertical NOR architecture memory cell structure404a trench430is formed in a substrate408. The vertical floating gate memory cell402and select gate410are then formed on the sidewalls of the trench430. The vertical floating gate memory cell402has a gate-insulator stack made of a tunnel insulator420formed on the surface of the sidewall, a floating gate422(typically of polysilicon) formed on the tunnel insulator420, an intergate/interpoly insulator424formed over the floating gate422, and a control gate406(typically formed in a control gate line, also known as a word line) formed over the intergate/interpoly insulator424. In one embodiment, the substrate trench430is formed by patterning a masking material that is layered over the substrate408and anisotropically etching the trenches430. The gate-insulator stack of the floating gate memory cell402is formed in one embodiment by successive layering of each of the materials of the gate insulator stack over the trench430, followed by a mask and directional etch of the deposit of each layer to leave only the material deposited on the sidewall of the trench430. In another embodiment, differing layers of the gate-insulator stack are formed and then masked and directionally etched in a single step.

The vertical select gate410has a gate-insulator stack made of an insulator442formed on the opposite sidewall of the trench430with a control gate444formed over the insulator442. The gate-insulator stack of the select gate410is formed by successive layering of each of the materials of the gate insulator stack over the trench430, as with the vertical floating gate memory cell402, but skips the depositing of the tunnel insulator420and floating gate422layers. In one embodiment of the present invention the tunnel insulator420and the floating gate422of the floating gate memory cell402are formed and then the intergate/interpoly insulator424/control gate406of the floating gate memory cell402and the insulator442/control gate444of the select gate410are formed consecutively.

N+ doped regions426are formed at the raised areas at the top and at the bottom of the trenches430to form the source and drain regions for the vertical floating gate memory cell/gate-insulator stack402and select gate410. The N+ regions also couple the memory cell402and select gate410together to form the vertical NOR memory structure404and additionally couple the vertical NOR architecture memory cell structure404to the bit line412and source line414. It is noted that the N+ source/drain regions426may be formed before or after the formation of the floating gate memory cell402and select gate410gate-insulator stacks.

InFIG. 4B, a vertical NOR architecture floating gate memory array400is formed from a series of vertical NOR architecture memory cell structures404. Each vertical NOR architecture memory cell structures404having a vertically formed floating gate memory cell402and a coupled select gate410, wherein the drain of the select gate is coupled to a bit line412and the source of the floating gate402is coupled to a source line414.

In creating the vertical NOR architecture floating gate memory array400a series of substrate pillars428are formed in a substrate408with trenches430located between them. The vertical floating gate memory cells402and select gates410are then formed on the sidewalls of the pillars428within the trenches430to form the vertical NOR architecture memory cell structures404. The vertical floating gate memory cells402and select gates410are formed in an alternating pattern (floating gate-select gate, select gate-floating gate, floating gate-select gate, etc.) such that each pillar428has either select gates410or floating gates formed on its sidewalls.

N+ doped regions426are formed at the top of the pillars428and at the bottom of the trenches430to form the source and drain regions. The N+ regions at the bottom of the trenches430couple the memory cell402and select gate410of each vertical NOR architecture memory cell structure404together. The N+ regions at the tops of the pillars428couple the drain of the select gate410and the source of the floating gate memory cell402of each vertical NOR architecture memory cell structure404to the bit lines412and source lines414respectively, so that the N+ regions on the top of the pillars428are coupled to either a source line414or a bit line412. It is again noted that the N+ source/drain regions426may be formed before or after the formation of the floating gate memory cell402and select gate410gate-insulator stacks.

It is also noted that isolation regions, typically formed of an oxide insulator, can be used between adjacent rows of vertical NOR architecture memory cell structures404to isolate each row from its neighbors. These isolation regions can be extended into the substrate408to allow the formation of P-wells, where each P-well contains a single row of vertical NOR architecture memory cell structures404that can be biased in isolation from the other rows of the array400. It is also noted that the control gate/word address lines406and select lines440can cross these isolation regions so that each control gate/word address line406and select line440controls the operation of multiple floating gate memory cells402and select gates410, respectively, across multiple rows of vertical NOR architecture memory cell structures404.

As stated above,FIG. 4Cdetails an equivalent circuit schematic420of the vertical NOR architecture floating gate memory array400, showing floating gate memory cells402and substrate connection422. The vertical floating gate memory cells402and select gates410are formed in an alternating pattern (floating gate-select gate, select gate-floating gate, floating gate-select gate, etc.) so that the drain of the select gate410and the source of the floating gate memory cell402of each vertical NOR architecture memory cell structure404is coupled to a bit line412or a source line414respectively.

In the vertical NOR architecture floating gate memory array400ofFIGS. 4A-4C, the channel length of each floating gate memory cell402and select gate410in a vertical NOR architecture memory cell structure404is determined by the depth of the trenches430and not by the minimum feature size. Due to the vertical form of the vertical NOR architecture floating gate memory array400and vertical NOR architecture memory cell structures404of embodiments of the present invention, a NOR architecture floating gate memory array can be produced that contain a vertical floating gate memory cell402and a coupled select gate410in the space that would be utilized by a single conventional planar floating gate memory cell.

The addition of a select gate410coupled between the bit line412and the drain of each floating gate memory cell402allows for the floating gate memory cell402to be isolated from the bit line412and thus has advantages in both programming and erasing the floating gate memory cells402of the vertical NOR architecture floating gate memory array400. In erasing, the coupled select gate410allows for avoidance of overerasure issues with floating gate memory cells402by isolating each memory cell402behind a select gate410so that, even if a floating gate memory cell402is overerased into depletion mode, it will not corrupt the reading of other memory cells402on its bit line412by flowing current. As the possibility of corruption of data reads due to overerasure is mitigated, this allows for the NOR architecture floating gate memory array400to speed up its erasure processes by using larger erase pulses (in time or voltage) or even utilizing only a single erase pulse. In addition, by allowing the increase of erasure pulse time and voltage, the number of erasure verifications required are reduced or even eliminated. The coupled select gate410also allows for the isolated erasure of one or more floating gate memory cells402allowing erasure of individual floating gate memory cells402, one or more selected data words, data segments, or erase blocks.

In programming, the coupled select gate410allows for mitigation of programming disturb of floating gate memory cells402in the array400by the select gate410isolating the memory cells402from the bit line412. This allows for longer and higher voltage programming pulses to be used without increasing the possibility of disturb issues.

FIGS. 5A-5Ddetail vertical floating gate cells, vertical select gates, and NAND architecture floating gate memory strings in accordance with embodiments of the present invention.FIG. 5Adetails a side view of a simplified vertical NAND architecture floating gate memory string504with vertical select gates510.FIG. 5Bdetails an equivalent circuit schematic520of the vertical NAND architecture floating gate memory string504, showing floating gate memory cells502and substrate connection534.FIG. 5Cdetails a side view of a simplified vertical NAND architecture floating gate memory array500andFIG. 5Ddetails an equivalent circuit schematic of one embodiment of the present invention. Again, as can be seen fromFIGS. 5A and 5C, in a vertical NAND architecture memory string504, two vertically formed transistors occupy the area that each planar transistor would occupy (an area of 4F squared when viewed from above, each transistor having an area of 2F squared). Where “F” is the minimum resolvable photolithographic dimension in the particular process technology. Since each transistor can store a single bit of data the data storage density is one bit for each 2F squared unit area. Thus, for example, if F=0.1 micron then the storage density is 0.5 Giga bit per square centimeter.

InFIG. 5A, a series of vertically formed floating gate memory cells502are coupled together in a series floating gate NAND string504(typically of 8, 16, 32, or more cells). In the vertical NAND floating gate memory array string504ofFIGS. 5A-5D, a series of substrate pillars528are formed in a substrate508with trenches530located between them. The vertical floating gate memory cells502are then formed on the sidewalls of the pillars528within the trenches530. Each vertical floating gate memory cell502is formed on the sidewalls of the substrate pillars528(for two floating gate memory cells502per trench530) and has a gate-insulator stack made of a tunnel insulator520formed on the surface of the sidewall, a floating gate522(typically of polysilicon) formed on the tunnel insulator520, an intergate/interpoly insulator524formed over the floating gate522, and a control gate506(typically formed in a control gate line, also known as a word line) formed over the intergate/interpoly insulator524.

In one embodiment the substrate pillars528and trenches530are formed by patterning a masking material that is layered over the substrate508and anisotropically etching the trenches530. The gate-insulator stack of each floating gate memory cell502are formed in one embodiment by successive layering of each of the materials of the gate insulator stack over the pillars528and trenches530, followed by a mask and directional etch of the deposit of each layer to leave only the material deposited on the sidewall of the pillars528. In another embodiment, differing layers of the gate-insulator stack are formed and then masked and directionally etched in a single step.

N+ doped regions526are formed at the top of the substrate pillars528and at the bottom of the trenches530between each vertical floating gate memory cell/gate-insulator stack502to form the source and drain regions of the adjacent floating gate memory cells502and couple the memory cells502together to form the vertical NAND architecture memory string504. It is noted that the N+ source/drain regions526may be formed before or after the formation of the floating gate memory cells/gate-insulator stack502.

Select gates510, that are coupled to gate select lines, are formed at either end of the NAND floating gate memory string504and selectively couple opposite ends of the NAND floating gate memory string504to a bit line contact512and a source line contact514. The vertical select gates510have a gate-insulator stack made of an insulator542formed on a sidewall with a control gate544formed over the insulator542. The gate-insulator stack of the select gates510are formed by successive layering of each of the materials of the gate insulator stack over the pillars528and trenches530, as with the vertical floating gate memory cell502, but skips the depositing of the tunnel insulator520and floating gate522layers. The N+ regions526also couple the first and last memory cell502of the vertical NAND architecture floating gate string504to the select gates510and additionally couple the vertical NAND architecture floating gate string504to the bit line512and source line514.

As stated above,FIG. 5Bdetails an equivalent circuit schematic of the vertical NAND architecture floating gate memory array500, showing the vertical floating gate memory cells502, select gates510, bit line512and source line514connections, and substrate connection534, in accordance with embodiments of the present invention. As can be seen, the schematic provides the same equivalent circuit as that of a conventional planar NAND architecture floating gate memory string.

InFIG. 5C, a section of vertical NAND architecture floating gate memory array500of one embodiment of the present invention is formed from a series of vertical NAND architecture floating gate memory cell strings504. InFIG. 5C, each pair of adjacent vertical NAND architecture floating gate memory cell strings504in the vertical NAND architecture floating gate memory array500are coupled through vertical select gates510to a common bit line512by a N+ doped region526formed at the top of a pillar528.

It is also noted that isolation regions, typically formed of an oxide insulator, can be used between vertical NAND architecture floating gate memory cell strings504to isolate each string504from its neighbors. These isolation regions can be extended into the substrate508to allow the formation of P-wells, where each P-well contains a single vertical NAND architecture floating gate memory cell string504that can be biased in isolation from the other strings or rows of the array500. It is also noted that the control gate/word address lines506and select lines540can cross these isolation regions so that each control gate/word address line506and select line540controls the operation of floating gate memory cells502and select gates510respectively across multiple rows of vertical NAND architecture floating gate memory cell strings504.

As stated above,FIG. 5Ddetails an equivalent circuit schematic of the vertical NAND architecture floating gate memory array ofFIG. 5C, showing floating gate memory cells502and adjacent sting504connection.

In the vertical NAND architecture floating gate memory array500ofFIGS. 5A-5D, the channel length of each floating gate memory cell502and select gate510in a vertical NAND architecture memory string504is determined by the depth of the pillars528and trenches530and not by the minimum feature size. Due to the vertical form of the NAND architecture floating gate memory array500and NAND architecture memory strings504of embodiments of the present invention, a vertical NAND architecture floating gate memory array string504and select gates510can be produced that typically has twice the density for a given string horizontal run length than a corresponding planar NAND architecture floating gate memory array string.

The addition of a select gates510coupled between the bit line512, source line514, and the floating gate memory cells502of the vertical NAND architecture memory string504allows for the floating gate memory cells502of the vertical NAND architecture memory string504to be isolated from the bit line512and/or source line514and thus has advantages in both programming and erasing the vertical NAND architecture memory string504. In erasing, the coupled select gates510allows for avoidance of overerasure issues with floating gate memory cells502by isolating each vertical NAND architecture memory string504behind one or more select gates510so that even if the floating gate memory cells502of the vertical NAND architecture memory string504are overerased into depletion mode operation they will not corrupt the reading of other memory cells502on other vertical NAND architecture memory strings504that are coupled to its bit line512. As the possibility of corruption of data reads due to overerasure is mitigated, this allows for the vertical NAND architecture floating gate memory array500to speed up erasure processes by using larger erase pulses or even a single erase pulse and by reducing or eliminating erasure verification. The coupled select gates510also allow for the isolated erasure of one or more floating gate memory cells502allowing erasure of individual floating gate memory cells502, individual vertical NAND architecture memory strings504, one or more selected data words, or erase blocks. In programming, the coupled select gates510allow for mitigation of programming disturb of floating gate memory cells502in the array500by the select gates510isolating the memory cells502of the vertical NAND architecture memory strings504from the bit line512and the source line514. This allows for longer and higher voltage programming pulses to be used without an increased issue with of disturb problems.

FIGS. 6A-6Cdetail three dimensional views of vertical floating gate cells602and vertical select gates610of a vertical NAND floating gate memory array600in accordance with embodiments of the present invention at several mid-fabrication stages. It is noted that a formation process that is similar to the NAND process may be utilized for formation of a vertical NOR floating gate memory array400with the exception of placement and number of the select gates610and bit line and source line contacts. As stated above, in creating the vertical NAND floating gate memory array600, a series of substrate pillars628are formed in a substrate608with trenches630located between them. The vertical floating gate memory cells602and select gates610are then formed on the sidewalls of the pillars628within the trenches630. Between successive rows of substrate pillars628, isolation regions632have been formed on the faces of the pillars628that are not utilized to form floating gate memory cells602or select gates610to isolate each row of vertical NAND floating gate memory strings604from the neighboring rows. These isolation regions632are typically formed of an oxide insulator.

As stated above, in creating each floating gate memory cell gate-insulator stack602, a tunnel insulator620is formed on the surface of the sidewall, a floating gate622is formed on the tunnel insulator620, an intergate/interpoly insulator624is formed over the floating gate622, and a control gate606is formed over the intergate/interpoly insulator624. In creating each select gate gate-insulator stack610, an insulator642is formed on the surface of the sidewall, and a control gate644is formed over the insulator642.

InFIG. 6A, the trenches630have been already formed by masking and anisotropically/directionally etching the trenches630in the substrate608. N+ doped regions626have been formed at the top of the unformed substrate pillars628and at the bottom of the trenches630to form the source/drain regions of the floating gate memory cells602. The gate-insulator stack of each floating gate memory cell602have been partially formed on the sidewalls of the trenches630. In each trench630, with the exception of the pillar628on which the select gates610are to be formed, are formed the tunnel insulator620, the floating gate622, and the intergate/interpoly insulator624, by successive depositing, masking, and directional etching of layers of material.

InFIG. 6B, the pillars628are formed and the space between each pillar in successive rows of NAND architecture floating gate memory strings604are filled with an oxide to form isolation regions632. In forming the pillars628, the rows of NAND architecture floating gate memory strings604are masked and directionally etched. This masking and etching process also divides the floating gate layer into individual floating gates622.

InFIG. 6C, the control gates/word lines606and select gates610/select lines640are formed. In forming the control gates/word lines606and select gates610/select lines640, successive layers of insulator and polysilicon which will form the control gates/word lines606and select gates610/select lines640is deposited over the pillars628, trenches630, and partially formed gate-insulator stacks of the floating gale memory cells602of the memory array600. A layer of masking material is then formed over the polysilicon layer and patterned. The excess masking material is removed and the memory array600is anisotropically/directionally etched to remove the undesired portions of the deposited polysilicon and form the control gates/word lines606and select gates610/select lines640on the sidewalls of the pillars628and trenches630.

It is noted that the isolation regions632between the vertical NAND architecture floating gate strings604can be extended into the substrate608to allow the formation of P-wells, where each P-well contains a single NAND string604and can be biased in isolation from the other strings604of the array600. It is also noted that the control gates/word lines606and select gates610/select lines640cross these isolation regions632so that each control gate/word address line606controls the operation of floating gate memory cells602and each select line640the operation of select gates610across multiple NAND memory strings604.

InFIGS. 6A-6C, the substrate608of the vertical NAND architecture floating gate memory array600is P-doped. A substrate connection can be utilized that can allow for biasing of the P-doped substrate608. It is noted that other forms of substrate doping, substrate biasing, and substrate types and regions (including, but not limited to silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor) in embodiments of the present invention are possible and should be apparent to those skilled in the art with the benefit of the present invention.

As noted above the programming of the floating gate memory cells of the vertical NAND and NOR architecture memory structures, strings, and arrays of embodiments of the present invention can be accomplished by conventional tunnel injection of electrons with a positive gate voltage with respect to the substrate or P-well. In another embodiment of the present invention, programming is accomplished by channel hot electron injection (HEI). Erasure of the floating gate memory cells of embodiments of the present invention can accomplished by conventional tunneling or negative voltages applied to the control gate voltages with respect to the substrate or P-well. In alternative embodiments of the present invention, substrate enhanced hot electron injection (SEHE) can be utilized for floating gate memory cell programming and/or substrate enhanced band to band tunneling induced hot hole injection (SEBBHH) for floating gate memory cell erasure.

FIG. 7illustrates a functional block diagram of a memory device700that can incorporate the vertical NAND architecture floating gate memory array500or vertical NOR architecture floating gate memory cell array400of the present invention. The memory device700is coupled to a processor710. The processor710may be a microprocessor or some other type of controlling circuitry. The memory device700and the processor710form part of an electronic system720. The memory device700has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The memory device includes an array of vertical floating gate memory cells and select gates730. In one embodiment, the memory cells are vertical floating gate memory cells and the memory array730are arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a wordline while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connection of the cells to the bitlines depends on whether the array is a NAND architecture or a NOR architecture.

An address buffer circuit740is provided to latch address signals provided on address/data bus762. Address signals are received and decoded by a row decoder744and a column decoder746to access the memory array730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the size of address input on the address/data bus762depends on the density and architecture of the memory array730. That is, the size of the input address increases with both increased memory cell counts and increased bank and block counts. It is noted that other address input manners, such as through a separate address bus, are also known and will be understood by those skilled in the art with the benefit of the present description.

The memory device700reads data in the memory array730by sensing voltage or current changes in the memory array columns using sense/buffer circuitry750. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array730. Data input and output buffer circuitry760is included for bi-directional data communication over a plurality of data connections in the address/data bus762with the processor/controller710. Write circuitry755is provided to write data to the memory array.

Control circuitry770decodes signals provided on control connections772from the processor710. These signals are used to control the operations on the memory array730, including data read, data write, and erase operations. The control circuitry770may be a state machine, a sequencer, or some other type of controller.

Since the vertical floating gate memory cells of the present invention use a CMOS compatible process, the memory device700ofFIG. 7may be an embedded device with a CMOS processor.

The memory device illustrated inFIG. 7has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of memories are known to those skilled in the art.

It is also noted that other vertical NAND and NOR architecture floating gate memory strings, arrays, and memory devices in accordance with embodiments of the present invention are possible and should be apparent to those skilled in the art with benefit of the present disclosure.

Conclusion

EEPROM memory devices and arrays have been described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating gate memory cells to form NOR and NAND architecture memory cell strings, segments, and arrays. These memory cell architectures allow for an improved high density memory devices or arrays with integral select gates that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and allow for appropriate device sizing for operational considerations. The memory cell architectures also allow for mitigation of disturb and overerasure issues by placing the floating gate memory cells behind select gates that isolate the memory cells from their associated bit lines and/or source lines.