Display device having grooves surrounding pixel areas

A display device includes an inorganic insulating layer having a groove surrounding pixel areas, a first thin film transistor in a first pixel area of a substrate, a second thin film transistor in a second pixel area of the substrate, a first electrode layer overlapping a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor, an organic material layer disposed in the groove, a data line extending over the organic material layer in a second direction, and a first connecting line extending across the organic material layer in a first direction, disposed between the first electrode layer and the data line, and overlapping the first electrode layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and benefits of Korean Patent Application No. 10-2019-0176140 under 35 U.S.C. § 119, filed in the Korean Intellectual Property Office on Dec. 27, 2019, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

One or more embodiments relate to a foldable display device that may be folded or curved.

2. Description of the Related Art

Display devices have been used for various purposes. As the thickness and weight of display devices have been reduced, the utilization range of display devices has increased. Research into flexible display devices such as foldable display devices, rollable display devices, etc., in addition to flat type display devices, has been conducted.

SUMMARY

One or more embodiments may include a high-resolution display device that may be flexible while being robust to external shock. However, the above technical features are exemplary, and the scope of the disclosure is not limited thereto.

According to an embodiment, a display device may include a substrate including a display area including display elements, the display area including pixel areas each of which may include a first pixel area and a second pixel area that may be adjacent to each other in a first direction, an inorganic insulating layer including a groove surrounding the pixel areas, and a first thin film transistor including a first semiconductor layer on the first pixel area of the substrate, and a first gate electrode on the first semiconductor layer. The display device may include a second thin film transistor including a second semiconductor layer on the second pixel area of the substrate, and a second gate electrode on the second semiconductor layer. The display device may include a first electrode layer disposed on the first gate electrode and overlapping the first gate electrode and the second gate electrode, an organic material layer disposed in the groove, a data line extending across the organic material layer in a second direction, and a first connecting line extending across the organic material layer in the first direction, disposed between the first electrode layer and the data line, and overlapping the first electrode layer.

The first semiconductor layer and the second semiconductor layer may be symmetrical with each other with respect to a boundary line between the first pixel area and the second pixel area.

The inorganic insulating layer may include inorganic patterns corresponding to the pixel areas, and the organic material layer may be disposed between the inorganic patterns and may include holes corresponding to the inorganic patterns.

The data line may overlap at least a portion of the first connecting line.

The display device may further include a power line extending across the organic material layer in a direction substantially parallel with the data line. The power line and the data line may be disposed on a same layer. The first connecting line may be electrically connected to the first electrode layer, and the power line may be electrically connected to the first connecting line.

The display device may further include a node electrode disposed between the first electrode layer and the first connecting line. The node electrode may include an end electrically connected to the first gate electrode, and another end electrically connected to the first semiconductor layer.

The first connecting line may overlap the end of the node electrode, and the end of the node electrode overlapping the first connecting line may overlap the first electrode layer.

The display device may further include a second connecting line extending across the organic material layer in a direction substantially parallel with the first connecting line, wherein the second connecting line and the first connecting line may be disposed on a same layer, and at least a portion of the second connecting line may be disposed between the data line and the another end of the node electrode in a plan view.

A voltage applied to the first connecting line may be different from a voltage applied to the second connecting line.

Each of the display elements may include a pixel electrode, an opposite electrode facing the pixel electrode, and an emission layer disposed between the pixel electrode and the opposite electrode, wherein at least two organic insulating layers may be disposed between the data line and the pixel electrode.

The pixel electrode may overlap the organic material layer.

The groove in a first row and the groove in a second row adjacent to the first row may be offset from each other as much as the first pixel area.

According to another embodiment, a display device may include a substrate including a first pixel area and a second pixel area adjacent to the first pixel area in a first direction, a first driving thin film transistor in the first pixel area of the substrate, a second driving thin film transistor in the second pixel area of the substrate, a first electrode layer overlapping a first gate electrode of the first driving thin film transistor and a second gate electrode of the second driving thin film transistor, the first electrode layer being disposed on the first gate electrode and the second gate electrode, a data line extending in the first pixel area in a second direction, a first connecting line extending in the first direction, disposed between the first electrode layer and the data line, and overlapping the first electrode layer, and an inorganic insulating layer disposed between the substrate and the first connecting line and including a groove surrounding the first pixel area and the second pixel area, wherein an organic material may be filled in the groove.

The display device may further include a third driving thin film transistor in a third pixel area adjacent to the first pixel area in the first direction, and a second electrode layer disposed on a third gate electrode of the third driving thin film transistor and overlapping the third gate electrode, wherein the groove may be disposed between the first driving thin film transistor and the third driving thin film transistor, and the first connecting line may be electrically connected to the first electrode layer and the second electrode layer across the groove.

The display device may further include a first switching thin film transistor in the first pixel area, and a node electrode disposed between the first electrode layer and the first connecting line. The node electrode may include an end electrically connected to the first gate electrode of the first driving thin film transistor, and another end connected to a semiconductor layer of the first switching thin film transistor.

The first connecting line may overlap the end of the node electrode, and the end of the node electrode overlapping the first connecting line may overlap the first electrode layer.

The display device may further include a second connecting line extending substantially parallel with the first connecting line, wherein the first connecting line and the second connecting line may be disposed on a same layer, and at least a portion of the second connecting line may be disposed between the data line and the another end of the node electrode in a plan view.

The display device may further include a second switching thin film transistor in the first pixel area, the second switching thin film transistor including an end electrically connected to the semiconductor layer of the first switching thin film transistor, and another end electrically connected to the second connecting line, and a conductive layer electrically connected to a semiconductor layer of the second switching thin film transistor and overlapping the semiconductor layer between two channel regions of the second switching thin film transistor, wherein the conductive layer and the node electrode may be disposed on a same layer.

The display device may further include a third switching thin film transistor in the first pixel area, the third switching thin film transistor being electrically connected to the first driving thin film transistor and an organic light-emitting diode, a fourth switching thin film transistor in a fourth pixel area adjacent to the first pixel area in the second direction, and a third connecting line extending in the second direction, wherein the groove may be disposed between the third switching thin film transistor and the fourth switching thin film transistor, and the third connecting line may be electrically connected to a semiconductor layer of the third switching thin film transistor and a semiconductor layer of the fourth switching thin film transistor across the groove.

The display device may further include a display element in the first pixel area, the display element including a pixel electrode and an opposite electrode facing the pixel electrode, wherein at least two organic insulating layers may be disposed between the data line and the pixel electrode.

The pixel electrode may overlap the groove.

DETAILED DESCRIPTION OF THE EMBODIMENTS

While such terms as “first,” “second,” etc., may be used to describe various elements, such elements are not to be limited to the above terms. The above terms are used only to distinguish one element from another.

It is to be understood that terms such as “including,” “having,” and “comprising” are intended to indicate the existence of the features, numbers, steps, actions, elements, parts, or combinations thereof disclosed herein, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, elements, parts, or combinations thereof may exist or may be added.

It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, region, or element, it may be directly or indirectly formed on the other layer, region, or element. For example, intervening layers, regions, or elements may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of elements in the drawings may be arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, “A and/or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.” Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. The phrase “at least one of A and B” denotes A, B, or A and B.

A line “extending in a first direction or a second direction” may denote extending in the first direction or the second direction in zig-zags or in a curve, as well as extending straightly in the first direction or the second direction.

The phrase “in a plan view” may denote viewing a target portion from the top, and the phrase “in a cross-sectional view” may denote viewing of a cross-section of the target portion that may be vertically cut from a lateral direction. As used herein, a first element “overlapping” a second element may denote that the first element may be located on, over, under, facing, or covering the second element, as would be understood by those of ordinary skill in the art.

FIGS. 1A and 1Bare schematic perspective views of a display device that is unfolded according to an embodiment.FIGS. 2A and 2Bare schematic cross-sectional views of a display device in a folded state according to an embodiment.FIGS. 3A and 3Bare cross-sectional views of a display device according to an embodiment.

The display device according to an embodiment may be folded or curved. The display device may be provided in various shapes, for example, may have a rectangular plate shape having two pairs of sides which are substantially parallel with each other. In case that the display device is provided in a rectangular plate shape, a pair of sides may be longer than another pair of sides. In the embodiment, the display device has a rectangular shape having a pair of long sides and a pair of short sides for convenience of description. A direction in which the short sides extend is denoted as a first direction D1, a direction in which the long sides extend is denoted as a second direction D2, and a direction perpendicular to the extending directions of the long sides and the short sides is denoted as a third direction D3.

The display device according to the embodiment is not limited to the above example, and may have various shapes. For example, the display device may be provided in various shapes, for example, a polygonal shape of closed type including straight sides, a circular shape or an elliptical shape including a curved side, a semi-circular shape or a semi-elliptical shape including straight and curved sides, etc. In an embodiment, in case that a display device has a straight line side, at least some of corners in each shape may have curved lines. For example, in case that a display device has a rectangular shape, a point where adjacent straight lines meet each other may be substituted with a curved line having a curvature. For example, a vertex portion of the rectangular shape may include a curved side having opposite ends connected to two adjacent straight sides and having a curvature. Here, the curvature may vary depending on a location of the vertex. For example, the curvature may be changed according to a location from which the curved line starts and a length of the curved line.

Referring toFIGS. 1A, 1B, 2A, and 2B, the display device may include a display panel10. The display panel10may include a display area DA and a peripheral area PA on an outer portion of the display area DA. The display area DA may be an area in which pixels PX may be arranged to display images. The peripheral area PA surrounds the display area DA and may be a non-display area, in which pixels may not be arranged.

Various electronic devices such as a printed circuit board, etc. may be electrically attached to the peripheral area PA, and a voltage line for supplying electric power to drive display elements, etc. may be in the peripheral area PA. For example, a scan driver for providing each of the pixels PX with a scan signal, a data driver for providing each pixel PX with a data signal, supply lines (clock signal lines, carry signal lines, driving voltage lines, etc.) for supplying signals input to the scan driver and the data driver, main power lines, etc. may be in the peripheral area PA.

The display panel10may be at least partially flexible and may be folded at a portion that may be flexible. For example, the display panel10may include a foldable area FA that may be flexible and foldable and non-foldable areas NFA1and NFA2that may be provided on at least one side of the foldable area FA and may not be foldable. In the disclosure, an area that may not be foldable may be referred to as a non-foldable area for convenience of description, but one or more embodiments are not limited thereto, and the expression “non-foldable” may denote the case in which the area has less flexibility than the foldable area FA, and the case in which the area may not be foldable but flexible, as well as the case in which the area may not be flexible but rigid. The display panel10may display images on the display area DA in the foldable area FA and the non-foldable area NFA (NFA1and NFA2).

InFIG. 1A, the first and second non-foldable areas NFA1and NFA2have similar areas to each other and one foldable area FA may be between the first and second non-foldable areas NFA1and NFA2for convenience of description, but one or more embodiments are not limited thereto. For example, the first and second non-foldable areas NFA1and NFA2may have different areas from each other. Also, as shown inFIG. 1B, one or more foldable areas FA may be provided. Non-foldable areas NFA1, NFA2, and NFA3may be spaced from one another with foldable areas FA1and FA2therebetween. Each of the foldable areas FA, FA1, and FA2may be folded about a folding line FL, FL1, or FL2, and each of the folding lines FL, FL1, and FL2may be provided in plural lines. The folding lines FL, FL1, and FL2may be respectively provided in the foldable areas FA, FA1, and FA2in the first direction D1, in which the foldable areas FA, FA1, and FA2extend, and accordingly, the display panel10may be folded at the foldable areas FA, FA1, and FA2.

InFIGS. 1A and 1B, the folding lines FL, FL1, and FL2extend across centers of the foldable areas FA, FA1, and FA2, and each of the foldable areas FA, FA1, and FA2may be line-symmetrical about the folding line FL, FL1, or FL2. However, one or more embodiments are not limited thereto. For example, the folding lines FL, FL1, and FL2may be provided asymmetrically in the foldable areas FA, FA1, and FA2. The foldable areas FA, FA1, and FA2and the folding lines FL, FL1, and FL2of the foldable areas FA, FA1, and FA2may overlap an area displaying images on the display panel10, and in case that the display panel10is folded, the area displaying the image may be folded.

In another embodiment, the display panel10may entirely correspond to the foldable areas FA, FA1, and FA2. For example, in case that the display device is rollable, the display panel10may entirely correspond to the foldable areas FA, FA1, and FA2.

The display panel10may be unfolded to be flat as shown inFIGS. 1A and 1B. In an embodiment, the display panel10may be folded as shown inFIG. 2A, and thus, the display area DA may be folded about the folding line FL such that opposite sides of the display area face each other. In another embodiment, the display panel10may be folded about the folding line FL as shown inFIG. 2B, and thus, the display area DA may face outside. Here, the term “fold” denotes that an original shape may not be fixed, but may be transformed into another form, and includes folded along one or more certain lines, e.g., folding lines FL, curved, or rolled. Therefore, in an embodiment of the disclosure, the display area may be folded such that surfaces of two non-foldable areas NFA1and NFA2face each other substantially parallel with each other, but one or more embodiments are not limited thereto, and the display area may be folded so that two non-foldable areas NFA1and NFA2form a certain degree angle (e.g., an acute angle or an obtuse angle) with the foldable area FA therebetween.

Referring toFIG. 3A, the display device1may include an optical functional layer50on the display panel10, and the optical functional layer50and the display panel10may be covered by a window60. The window60may be bonded to an element thereunder, e.g., the optical functional layer50, via an optical clear adhesive (OCA). The display device1may be provided in various electronic devices such as a mobile phone, a tablet PC, a laptop computer, a smart watch, etc. As shown inFIG. 3B, the display device1may further include an input sensing layer40between the display panel10and the optical functional layer50.

The input sensing layer40may obtain coordinate information generated according to an external input, e.g., a touch event. The input sensing layer40may include a sensing electrode (e.g., a touch electrode) and signal lines (e.g., trace lines) connected to the sensing electrode. In an embodiment, the input sensing layer40may be on (e.g., directly on) the display panel10. That the input sensing layer40may be on (e.g., directly on) the display panel10denotes that an additional adhesive material layer may not be provided between the input sensing layer40and the display panel10, and elements of the input sensing layer40may be patterned (e.g., directly patterned) on the display panel10. In another embodiment, the input sensing layer40may be obtained through a separate process from that of the display panel10and may be bonded onto the display panel10via a transparent adhesive material layer, etc.

The optical functional layer50may include a structure of a black matrix and color filters. The color filters may be arranged taking into account a color of light emitted from each of the pixels in the display panel10. The optical functional layer50may function as an anti-reflection layer that reduces a reflectivity of light (e.g., external light) incident to the display panel10from outside via the window60.

The window60may cover and protect the optical functional layer50, the input sensing layer40, and/or the display panel10. The window60may be on the display panel10without an intervening polarization layer between the display panel10and the window60. According to the embodiment, the foldable display device that may be foldable while having an external light reflection preventing function may be implemented by including the optical functional layer50including the color filter instead of a rigid polarization layer (for example, a retarder and a polarizer) and/or a planarization layer including organic insulating layers in the display panel10.

The window60may be provided to be larger than the input sensing layer40, the optical functional layer50, and the display panel10, and thus, a side of the window60may protrude more than sides of the input sensing layer40, the optical functional layer50, and the display panel10. The window60may include a transparent material. The window60may be flexible. For example, the window60may include a polymer resin such as a polyether sulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc., or a combination thereof. The window60may be coupled onto the input sensing layer40and the optical functional layer50by using a transparent adhesive material layer, etc. The window60may include a light-transmitting area61that may correspond to the display area DA and a light-blocking area62that may correspond to the peripheral area PA.

FIG. 4is a schematic equivalent circuit diagram of one pixel PX in a display panel according to an embodiment.

Referring toFIG. 4, a pixel PX may include signal lines SL1, SL2, SL3, EL, and DL, an initialization voltage line VIL, and a power voltage line PL. In another embodiment, at least one of the signal lines SL1, SL2, SL3, EL, and DL, the initialization voltage line VIL, and/or the power voltage line PL may be shared by neighboring pixels.

The signal lines may include a first scan line SL1configured to transfer a first scan signal GW, a second scan line SL2configured to transfer a second scan signal GI, a third scan line SL3configured to transfer a third scan signal GB, an emission control line EL configured to transfer a light-emitting control signal EM, and a data line DL configured to transfer a data signal DATA. The third scan line SL3may be the second scan line SL2of a different (e.g., next) row and the third scan signal GB may be the second scan signal GI of a different (e.g., next) row.

The power voltage line PL may be configured to transfer a first power voltage ELVDD to a first transistor T1, and the initialization voltage line VIL may be configured to transfer an initialization voltage VINT to the pixel PX for initializing the first transistor T1and an organic light-emitting diode OLED.

A pixel circuit PC of the pixel PX may include first to seventh transistors T1to T7and a capacitor Cst. The first to seventh transistors T1to T7may each include a thin film transistor.

The first transistor T1may be electrically connected to the power voltage line PL via the fifth transistor T5and may be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6. The first transistor T1may act as a driving transistor and may receive the data signal DATA to supply a driving current Ioled to the organic light-emitting diode OLED according to a switching operation of the second transistor T2.

The second transistor T2may be electrically connected to the first scan line SL1and the data line DL, and may be turned on according to the first scan signal GW transferred through the first scan line SL1to perform a switching operation for transferring to a node N the data signal DATA that may be transferred through the data line DL.

The third transistor T3may be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3may be turned on according to the first scan signal GW transferred through the first scan line SL1to diode-connect the first transistor T1.

The fourth transistor T4may be turned on according to the second scan signal GI transferred through the second scan line SL2and may be configured to transfer an initialization voltage VINT from the initialization voltage line VIL to a gate electrode of the first transistor T1to initialize a gate voltage of the first transistor T1.

The fifth transistor T5and the sixth transistor T6may be simultaneously turned on according to the emission control signal EM transferred through the emission control line EL to form a current path through which the driving current Ioled flows from the power voltage line PL towards the organic light-emitting diode OLED.

The seventh transistor T7may be turned on according to the third scan signal GB transferred through the third scan line SL3and may be configured to transfer the initialization voltage VINT from the initialization voltage line VIL to the organic light-emitting diode OLED to initialize the organic light-emitting diode OLED. The seventh transistor T7may be omitted.

InFIG. 4, the fourth transistor T4may be electrically connected to the second scan line SL2and the seventh transistor T7may be electrically connected to the third scan line SL3. In another embodiment, the seventh transistor T7and the fourth transistor T4may be electrically connected to the second scan line SL2.

The capacitor Cst may be electrically connected to the power voltage line PL and the gate electrode of the first transistor T1to store and maintain a voltage corresponding to a difference between voltages at opposite ends to maintain the voltage applied to the gate electrode of the first transistor T1.

The organic light-emitting diode OLED may include a pixel electrode and an opposite electrode, and the opposite electrode may receive a second power voltage ELVSS. The organic light-emitting diode OLED may receive the driving current Ioled from the first thin film transistor T1to emit light, and thus may display images.

FIG. 5is a schematic diagram showing locations of thin film transistors and a capacitor in each of two adjacent pixels according to an embodiment.FIGS. 6A to 6Iare schematic plan views showing elements such as thin film transistors, the capacitor, and a pixel electrode shown inFIG. 4according to layers.FIGS. 7 to 9are schematic cross-sectional views of the pixel taken along line I-I′, line II-II′, and line III-III′ ofFIG. 5.

Referring toFIGS. 5 to 9, the display panel10according to the embodiment may include a substrate100, pixels PX on the substrate100, and an encapsulation layer400.

An inorganic insulating layer including a groove GV between pixel areas PXA and an organic material layer180filling the groove GV may be on the substrate100. Connecting lines151to156may be on the organic material layer180on the substrate100, and the connecting lines151to156may cross the organic material layer180in the first direction D1and/or the second direction D2.

The pixel area PXA may be an area in which a pair of pixels PX may be arranged and may include a first pixel area SPA1at the left and a second pixel area SPA2at the right. Hereinafter, a pixel in the first pixel area SPA1may be referred to as a first pixel PXL and a pixel in the second pixel area SPA2may be referred to as a second pixel PXR. A pixel circuit of the first pixel PXL in the first pixel area SPA1and a pixel circuit of the second pixel PXR in the second pixel area SPA2may be symmetrical with each other based on a virtual boundary line BL that may partition the pixel area PXA.FIGS. 5 to 6Ifurther show a part of an adjacent pixel area PXA.

Each ofFIGS. 6A to 6Ishows an arrangement of lines, electrodes, semiconductor layers, etc. at a same layer, and insulating layers may be located among the layers shown inFIGS. 6A to 6I. Hereinafter, descriptions will be provided with reference toFIGS. 5 to 9together.

The substrate100may include various materials such as a metal material, a plastic material, etc., or a combination thereof. In an embodiment, the substrate100may include a flexible substrate. As shown inFIGS. 7 to 9, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104, which may be sequentially stacked on each other. The first and second base layers101and103may each include a polymer resin. For example, the first and second base layers101and103may each include a polymer resin such as a polyether sulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc., or a combination thereof. The above polymer resin may be transparent. The first barrier layer102and the second barrier layer104may prevent infiltration of external impurities may each have a single-layered or multi-layered structure including an inorganic material such as silicon nitride and/or silicon oxide.

The buffer layer110may be on the second barrier layer104of the substrate100. The buffer layer110may block impurities or moisture that may infiltrate through the substrate100. The buffer layer110may include an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride, and may have a single-layered or multi-layered structure.

A semiconductor layer ACT may be on the buffer layer110for each pixel area PXA. The semiconductor layer ACT may include a first semiconductor layer ACT1in the first pixel area SPA1and a second semiconductor layer ACT2in the second pixel area SPA2. The first semiconductor layer ACT1and the second semiconductor layer ACT2may be connected to each other. The first semiconductor layer ACT1and the second semiconductor layer ACT2may be integrally provided with each other. InFIG. 6A, a portion between the first semiconductor layer ACT1and the second semiconductor layer ACT2may be denoted as a third semiconductor layer ACT3. The semiconductor layer ACT in the pixel area PXA may be separated from a semiconductor layer in another pixel area PXA with the groove GV therebetween.

The semiconductor layer ACT may include amorphous silicon, polycrystalline silicon, an organic semiconductor material, or a combination thereof. Each of the first semiconductor layer ACT1and the second semiconductor layer ACT2may have variously curved shapes, in which a semiconductor layer ACTa of the first transistor T1, a semiconductor layer ACTb of the second transistor T2, a semiconductor layer ACTc of the third transistor T3, a semiconductor layer ACTd of the fourth transistor T4, a semiconductor layer ACTe of the fifth transistor T5, a semiconductor layer ACTf of the sixth transistor T6, and a semiconductor layer ACTg of the seventh transistor T7may be connected to one another.

As shown inFIG. 6A, each of the first semiconductor layer ACT1and the second semiconductor layer ACT2may include a channel region131aof the first transistor T1, a channel region131bof the second transistor T2, channel regions131c1and131c2of the third transistor T3, channel regions131d1and131d2of the fourth transistor T4, a channel region131eof the fifth transistor T5, a channel region131fof the sixth transistor T6, and a channel region131gof the seventh transistor T7. For example, the channel region in each of the first to seventh transistors T1to T7may be a part of the semiconductor layer ACT. Because the channel region131aof the first transistor T1may be curved and elongated, a driving range of a gate voltage applied to the gate electrode may be increased. The channel region131aof the first transistor T1may have various shapes, e.g., ‘’, ‘’, ‘S’, ‘M’, ‘W’, etc.

The semiconductor layer of each of the first to seventh transistors T1to T7may include source and drain regions at opposite sides of the channel region. As shown inFIG. 6A, each of the first semiconductor layer ACT1and the second semiconductor layer ACT2may include a source region176aand a drain region177aof the first transistor T1, a source region176band a drain region177bof the second transistor T2, a source region176cand a drain region177cof the third transistor T3, a source region176dand a drain region177dof the fourth transistor T4, a source region176eand a drain region177eof the fifth transistor T5, a source region176fand a drain region177fof the sixth transistor T6, and a source region176gand a drain region177gof the seventh transistor T7. In some cases, the source region and the drain region may be interpreted as a source electrode and a drain electrode of a transistor. For example, a source electrode and a drain electrode of the first transistor T1may respectively correspond to the source region176aand the drain region177adoped with impurities around the channel region131ain the semiconductor layer ACT shown inFIG. 6A. According to embodiments, locations of the source region and the drain region may be changed.

The source region176aof the first transistor T1may be connected to the drain region177bof the second transistor T2and the source region176eof the fifth transistor T5. The drain region177aof the first transistor T1may be connected to the source region176cof the third transistor T3and the drain region177fof the sixth transistor T6. The drain region177cof the third transistor T3may be connected to the drain region177dof the fourth transistor T4. The source region176dof the fourth transistor T4may be connected to the drain region177gof the seventh transistor T7. The third transistor T3may be a dual-thin film transistor including two channel regions131c1and131c2, and a region between the channel regions131c1and131c2may be a region doped with impurities and may locally correspond to a source region of a dual-thin film transistor and a drain region of another dual-thin film transistor. The fourth transistor T4may be a dual-thin thin film transistor including two channel regions131d1and131d2, and a region between the channel regions131d1and131d2may be a region doped with impurities and may locally correspond to a source region of a dual-thin film transistor and a drain region of another dual-thin film transistor.

At a boundary between the first pixel area SPA1and the second pixel area SPA2, the source region176dof the fourth transistor T4and the drain region177gof the seventh transistor T7in the first pixel PXL may be connected to the source region176dof the fourth transistor T4and the drain region177gof the seventh transistor T7in the second pixel PXR.

A first gate insulating layer111may be on the semiconductor layer ACT. The first gate insulating layer111may include inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof. The first gate insulating layer111may have a single-layered or multi-layered structure including the above materials.

As shown inFIG. 6B, in the first pixel area SPA1and the second pixel area SPA2, a gate electrode125aof the first transistor T1, a gate electrode125bof the second transistor T2, gate electrodes125c1and125c2of the third transistor T3, gate electrodes125d1and125d2of the fourth transistor T4, a gate electrode125eof the fifth transistor T5, a gate electrode125fof the sixth transistor T6, and a gate electrode125gof the seventh transistor T7may be on the first gate insulating layer111. The gate electrode125aof the first transistor T1may function as a lower electrode of the capacitor Cst.

A first scan line121, a second scan line122, and an emission control line123, which may be at the same layer and may include the same material as those of the gate electrodes of the first to seventh transistors T1to T7, may extend in the first direction D1on the first gate insulating layer111, and may cross the first pixel area SPA1and the second pixel area SPA2.

The first scan line121may include a 1-1 scan line121ain the first pixel area SPA1and a 1-2 scan line121bin the second pixel area SPA2. The 1-1 scan line121aand the 1-2 scan line121bmay be connected to each other. For example, the first scan line121may include the 1-1 scan line121ain the first pixel PXL and the 1-2 scan line121bin the second pixel PXR provided integrally with each other.

The second scan line122may include a 2-1 scan line122ain the first pixel area SPA1and a 2-2 scan line122bin the second pixel area SPA2. The 2-1 scan line122aand the 2-2 scan line122bmay be connected to each other. For example, the second scan line122may include the 2-1 scan line122ain the first pixel PXL and the 2-2 scan line122bin the second pixel PXR provided integrally with each other.

The emission control line123may include a first emission control line123ain the first pixel area SPA1and a second emission control line123bin the second pixel area SPA2. The first emission control line123aand the second emission control line123bmay be connected to each other. For example, the emission control line123may include the first emission control line123ain the first pixel PXL and the second emission control line123bin the second pixel PXR provided integrally with each other.

The gate electrode125bof the second transistor T2and the gate electrodes125c1and125c2of the third transistor T3may be portions of the first scan line121overlapping the semiconductor layer ACT or portions protruding from the first scan line121. The gate electrodes125d1and125d2of the fourth transistor T4and the gate electrode125gof the seventh transistor T7may be portions of the second scan line122overlapping the semiconductor layer ACT or portions protruding from the second scan line122. The gate electrode125eof the fifth transistor T5and the gate electrode125fof the sixth transistor T6may be portions of the emission control line123overlapping the semiconductor layer ACT or portions protruding from the emission control line123. The gate electrode125aof the first transistor T1may be of an island type overlapping the channel region131aof the first and the semiconductor layer ACT1and ACT2. The third transistor T3and the fourth transistor T4may be dual-thin film transistors each including two gate electrodes.

The gate electrodes of the first to seventh transistors T1to T7may have a single-layered or multi-layered structure including one or more selected from aluminum (Al), platinum (Pt), palladium (Pd), argentum (Ag), magnesium (Mg), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

The first scan line121, the second scan line122, and the emission control line123in the pixel area PXA may be separated from the first scan line121, the second scan line122, and the emission control line123in another pixel area PXA.

A second gate insulating layer112may be on the gate electrodes of the first to seventh transistors T1to T7. The second gate insulating layer112may each include inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof. The second gate insulating layer112may have a single-layered or multi-layered structure including the above materials.

As shown inFIG. 6C, an electrode voltage layer127extends on the second gate insulating layer112in the first direction D1and may extend across the first pixel area SPA1and the second pixel area SPA2. The electrode voltage layer127may include a first portion127athat may overlap the gate electrode125aof the first transistor T1in the first pixel area SPA1, and a second portion127bthat may overlap the gate electrode125aof the first transistor T1in the second pixel area SPA2. The first portion127amay function as an upper electrode of the capacitor Cst in the first pixel PXL, and the second portion127bmay function as an upper electrode of the capacitor Cst in the second pixel PXR. For example, the capacitor Cst may share the gate electrode125aof the first transistor T1as a lower electrode and may overlap the first transistor T1. Each of the first portion127aand the second portion127bin the electrode voltage layer127may include an opening128.

The electrode voltage layer127may have a single or multi-layered structure including one or more materials from aluminum (Al), platinum (Pt), palladium (Pd), argentum (Ag), magnesium (Mg), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

The electrode voltage layer127in the pixel area PXA may be separated apart from the electrode voltage layer127in another pixel area PXA.

A first shielding electrode129may be further on the second gate insulating layer112. The first shielding electrode129may include the same material as that of the electrode voltage layer127. The first shielding electrode129may overlap the source/drain region176c/177cbetween the two channel regions131c1and131c2of the third transistor T3in each of the first pixel PXL and the second pixel PXR. The first shielding electrode129may be at the boundary between the first pixel area SPA1and the second pixel area SPA2and may be shared by the first pixel PXL and the second pixel PXR. The first shielding electrode129may prevent the third transistor T3in each of the first pixel PXL and the second pixel PXR from being affected by light incident from outside and/or other electrical signals.

A first interlayer insulating layer113may be on the electrode voltage layer127and the first shielding electrode129. The first interlayer insulating layer113may include inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof. The first interlayer insulating layer113may have a single-layered or multi-layered structure including the above materials.

As shown inFIG. 6D, a node electrode141, a second shielding electrode143, a first connecting electrode145, and a second connecting electrode147may be on the first interlayer insulating layer113. The node electrode141, the second shielding electrode143, the first connecting electrode145, and the second connecting electrode147may each have a single-layered or multi-layered structure including one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), argentum (Ag), magnesium (Mg), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

The node electrode141may be in each of the first pixel area SPA1and the second pixel area SPA2. An end of the node electrode141may be connected to the gate electrode125aof the first transistor T1via a contact hole12in the second gate insulating layer112and the first interlayer insulating layer113. Another end of the node electrode141may be connected to the drain region177cof the third transistor T3and the drain region177dof the fourth transistor T4via a contact hole11in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The second shielding electrode143may be in each of the first pixel area SPA1and the second pixel area SPA2. An end of the second shielding electrode143may be connected to the source region176dof the fourth transistor T4and the drain region177gof the seventh transistor T7via contact holes13in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113. The second shielding electrode143may overlap the source/drain region176d/177dbetween the two channel regions131d1and131d2of the fourth transistor T4. The second shielding electrode143may prevent the fourth transistor T4from being affected by the light incident from outside and/or other electrical signals.

The first connecting electrode145may be in each of the first pixel area SPA1and the second pixel area SPA2. An end of the first connecting electrode145may be connected to the drain region177eof the fifth transistor T5via contact holes14in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113, and another end of the first connecting electrode145may be connected to the upper electrode127of the capacitor Cst via a contact hole15in the first interlayer insulating layer113.

The second connecting electrode147may be at the boundary between the first pixel area SPA1and the second pixel area SPA2and may be shared by the first pixel PXL and the second pixel PXR. An end of the second connecting electrode147may overlap the first shielding electrode129and may be connected to the first shielding electrode129via a contact hole16in the first interlayer insulating layer113. Another end of the second connecting electrode147overlaps the electrode voltage layer127and may be connected to the electrode voltage layer127via a contact hole17in the first interlayer insulating layer113.

A second interlayer insulating layer114may be on the node electrode141, the second shielding electrode143, the first connecting electrode145, and the second connecting electrode147. The second interlayer insulating layer114may include inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The second interlayer insulating layer114may have a single-layered or multi-layered structure including the above materials.

FIG. 6Eshows a stack structure of conductive layers shown inFIGS. 6A to 6D. As shown inFIG. 6E, the groove GV surrounding the pixel area PXA may be provided in the buffer layer110, the first and second gate insulating layers111and112, and the first and second interlayer insulating layers113and114. Hereinafter, the buffer layer110, the first and second gate insulating layers111and112, and the first and second interlayer insulating layers113and114may be collectively referred to as an inorganic insulating layer IL. The groove GV may denote a trench formed in the inorganic insulating layer IL. In an embodiment, the inorganic insulating layer IL may be divided by the groove GV into inorganic patterns of island shapes in units of pixel area PXA.

The groove GV may be provided between adjacent pixel areas PXA and may surround each pixel area PXA. The groove GV may include an opening111ain the first gate insulating layer111, an opening112ain the second gate insulating layer112, an opening113ain the first interlayer insulating layer113, and an opening114ain the second interlayer insulating layer114. The groove GV may further include an opening110ain the buffer layer110. However, one or more embodiments are not limited thereto, and the groove GV may be variously modified. For example, the buffer layer110may not include an opening or the buffer layer110may not be partially or entirely removed but may remain.

The openings110a,111a,112a,113a, and114ain the inorganic insulating layer IL may overlap one another. InFIGS. 7 to 9, the opening110ain the buffer layer110, the opening111ain the first gate insulating layer111, the opening112ain the second gate insulating layer112, the opening113ain the first interlayer insulating layer113, and the opening114ain the second interlayer insulating layer114may have inner side surfaces coinciding with one another. In another embodiment, the inner side surfaces of the openings110a,111a,112a,113a, and114amay not coincide with one another, and the openings110a,111a,112a,113a, and114amay have different sizes from one another.

A width W of the groove GV may be about a few μm. For example, the width W of the groove GV in the inorganic insulating layer IL may be about 5 μm to about 10 μm. The substrate100may be exposed by the groove GV of the inorganic insulating layer IL.

The groove GV may be obtained by a mask process. In the mask process, a dry etching may be performed.

Contact holes21a,21b,22a,22b,23,24a,24b,25,26,27, and28for making a conductive layer formed on the second interlayer insulating layer114in contact with a lower conductive layer (e.g., a semiconductor layer, gate electrode, an upper electrode of the capacitor, etc.) may be in at least one of the first and second gate insulating layers111and112and the first and second interlayer insulating layers113and114. The contact holes21a,21b,22a,22b,23,24a,24b,25,26,27, and28may be obtained simultaneously with the forming of the groove GV in the mask process for forming the groove GV.FIG. 6Eonly shows locations corresponding to the contact holes21a,21b,22a,22b,23,24a,24b,25,26,27, and28and insulating layers are omitted for convenience of description and disclosure.

As shown inFIG. 6F, the organic material layer180may be filled in the groove GV of the inorganic insulating layer IL. The organic material layer180may at least partially fill the groove GV of the inorganic insulating layer IL. The organic material layer180may not completely fill the groove GV. Also, the organic material layer180may not fill portions of the groove GV. However, the organic material layer180may completely fill the groove GV in order to absorb external shock. In some embodiments, the organic material layer180may extend to an upper surface of the inorganic insulating layer IL. An upper surface of the organic material layer180may have a convex shape due to characteristics of the organic material layer.

An angle between the upper surface of the organic material layer180and the upper surface of the inorganic insulating layer IL may be about 45 degrees or less. In case that an inclination of a boundary where the upper surface of the inorganic insulating layer IL and the upper surface of the organic material layer180meet each other is not gradual, a conductive material may not be removed but may remain at the boundary while the connecting lines151to156may be formed by patterning the conductive layer. In the above case, the remaining conductive material may cause a short with other conductive layers. Therefore, the upper surface of the organic material layer180may have a gradual (slow) inclination with respect to the upper surface of the inorganic insulating layer IL.

The organic material layer180may include one or more materials selected from the group consisting of acryl, metacryl, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarilate, and hexamethyldisiloxane.

The organic material layer180surrounds the pixel area PXA along with the groove GV, and thus, may partition the pixels PX in units of pixel area PXA. Accordingly, propagation of stress or cracks due to folding of the display panel10to other pixel areas may be prevented.

As shown inFIG. 6G, connecting lines150may be on the second interlayer insulating layer114. A third connecting electrode157may be further on the second interlayer insulating layer114. The connecting lines150may include conductive lines extending across the groove GV and the organic material layer180in the first direction D1or the second direction D2. The connecting lines150may include soft lines each including a material with a high elongation rate. The connecting lines150and the third connecting electrode157may include a single-layered or multi-layered structure including magnesium (Mg), aluminum (Al), copper (Cu), titanium (Ti), etc., or a combination thereof. In an embodiment, the connecting lines150and the third connecting electrode157may each have a multi-layered structure including Ti/Al/Ti.

The connecting lines150may include a first scan connecting line151, a second scan connecting line152, an initialization voltage connecting line153, a power voltage connecting line154, an emission control connecting line155, and a semiconductor layer connecting line156.

The first scan connecting line151may extend in the first direction D1while overlapping the first scan line121and may be arranged across the first pixel area SPA1and the second pixel area SPA2. The first scan connecting line151may be connected to the first scan line121via the contact holes21aand21bin the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114.

The second scan connecting line152may extend in the first direction D1while overlapping the second scan line122and may be arranged across the first pixel area SPA1and the second pixel area SPA2. The second scan connecting line152may be connected to the second scan line122via the contact holes22aand22bin the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114.

The initialization voltage connecting line153may extend in the first direction D1across the first pixel area SPA1and the second pixel area SPA2. The initialization voltage connecting line153may be connected to a portion where the first semiconductor layer ACT1of the first pixel PXL and the second semiconductor layer ACT2of the second pixel PXR may be connected, for example, the third semiconductor layer ACT3, via the contact hole23in the first gate insulating layer111, the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114. The initialization voltage connecting line153may include a protrusion153pprotruding in the second direction D2in each of the first pixel area SPA1and the second pixel area SPA2.

The power voltage connecting line154may extend in the first direction D1while overlapping the electrode voltage layer127and may cross the first pixel area SPA1and the second pixel area SPA2. The power voltage connecting line154may have a curved shape partially surrounding the opening128without overlapping the opening128in the electrode voltage layer127. The power voltage connecting line154may be connected to the electrode voltage layer127via the contact holes24aand24bin the first interlayer insulating layer113and the second interlayer insulating layer114.

The emission control connecting line155may extend in the first direction D1while overlapping the emission control line123and may cross the first pixel area SPA1and the second pixel area SPA2. The emission control connecting line155may be connected to the emission control line123via the contact hole25in the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114at the boundary between the first pixel area SPA1and the second pixel area SPA2.

The semiconductor layer connecting line156may extend in the second direction D2(or in a direction between the first direction D1and the second direction D2) across the upper portion of the organic material layer180in the groove GV. An end of the semiconductor layer connecting line156may be connected to the source region176gof the seventh transistor T7via the contact hole26in the first gate insulating layer111, the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114. Another end of the semiconductor layer connecting line156may be connected to the drain region177fof the sixth transistor T6via the contact hole27in the first gate insulating layer111, the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114. As shown inFIGS. 5 and 9, an end and another end of the semiconductor layer connecting line156may be at different pixel areas PXA with the groove GV therebetween to connect the semiconductor layers of adjacent pixels PX to each other in the second direction D2.

The third connecting electrode157may be further on the second interlayer insulating layer114. The third connecting electrode157may be connected to the source region176bof the second transistor T2via the contact hole28in the first gate insulating layer111, the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114. The third connecting electrode157may be in each of the first pixel area SPA1and the second pixel area SPA2.

Each of the first scan connecting line151, the second scan connecting line152, the power voltage connecting line154, and the emission control connecting line155may extend across the upper portion of the organic material layer180in the groove GV to connect the first scan lines121, the second scan lines122, the electrode voltage layers127, and the emission control lines123in the pixel areas PXA adjacent to each other in the first direction D1. For example, each of the first scan connecting line151, the second scan connecting line152, the power voltage connecting line154, and the emission control connecting line155may connect the first scan lines121, the second scan lines122, the electrode voltage layers127, and the emission control lines123of the pixels PX in the same row, which may be divided in units of the pixel areas PXA. The power voltage connecting line154may be connected to the pixels PX in the pixel areas PXA adjacent to one another in the first direction D1to apply the first power voltage ELVDD. The initialization voltage connecting line153may extend across the upper portion of the organic material layer180surrounding the pixel area PXA to be connected to the pixels PX in the pixel areas PXA adjacent to one another in the first direction and may apply the initialization voltage VINT to the pixels PX.

Before forming the conductive layers shown inFIG. 6Dor before forming the conductive layers shown inFIG. 6G, a dehydrogenation annealing process may be performed on the semiconductor layer after forming the contact holes. A driving range of a driving transistor may be increased due to the annealing process.

A protective layer115may be on the connecting lines150and the third connecting electrode157. The protective layer115may have a single-layered or multi-layered structure including an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc., or a combination thereof.

In an embodiment, the protective layer115may function as a planarization layer together with organic insulating layers that will be described later. A contact hole in the inorganic layer may have a smaller size than that of a contact hole in an organic layer. In the foldable display device having the island type pixel group structure according to the embodiment, an integration ratio of the pixel circuit for high resolution and high radio frequency (e.g., 120 Hz) driving may be increased by providing an inorganic planarization layer.

The protective layer115may not cover the organic material layer180. For example, the protective layer115may be provided as an insulation pattern of an island type in each pixel area PXA due to the groove GV. A first insulating layer116may be further on the protective layer115.

As shown inFIG. 6H, data lines161and a power voltage line163may be on the first insulating layer116. The data lines161and the power voltage line163extend in the second direction D2across the organic material layer180among the pixel areas PXA to be connected to the pixels PX adjacent to one another in the second direction D2.

The data lines161may include a first data line161E and a second data line161O. In each of the first pixel area SPA1and the second pixel area SPA2, the first data line161E and the second data line161O may be separated substantially parallel with each other. The first data line161E may be at a left side of the first pixel area SPA1and a right side of the second pixel area SPA2in a plan view. The second data line161O may be at a right side of the first pixel area SPA1and a left side of the second pixel area SPA2.

The pixels PX in even-numbered rows may be connected to the first data line161E, and the pixels PX in odd-numbered rows may be connected to the second data line161O.FIG. 5shows an example, in which the first pixel PXL in the first pixel area SPA1and the second pixel PXR in the second pixel area SPA2may be connected to the first data line161E. For example, the pixels PX shown inFIG. 5may be the pixels in the even-numbered row. The data lines161may be connected to the third contact electrode157via a contact hole31in the protective layer115and a contact hole31′ in the first insulating layer116. Because the third connecting electrode157may be connected to the source region176bof the second transistor T2, the first data line161E or the second data line161O may be connected to the second transistor T2via the third connecting electrode157.

The first data line161E may overlap the source region176aof the first transistor T1, and the second data line161O may overlap the drain region177aof the first transistor T1. The first data line161E and the second data line161O may overlap the electrode voltage layer127and the power voltage connecting line154.

The power voltage line163may overlap the electrode voltage layer127and may be substantially parallel with the data lines161. The power voltage line163may be connected to the power voltage connecting line154via a contact hole32in the protective layer115and a contact hole32′ in the first insulating layer116. Because the power voltage connecting line154may be connected to the electrode voltage layer127, the power voltage line163may have a mesh structure due to the power voltage163extending in the second direction D2and the electrode voltage layer127and the power voltage connecting line154extending in the first direction D1.

In case that an electric potential of the gate electrode125ain the first transistor T1is affected by a voltage variation in the data lines161, a coupling may be caused between the data lines161and the gate electrode125aof the first transistor T1. Also, because the node electrode141may be connected to the gate electrode125aof the first transistor T1, in case that the node electrode141is affected by the voltage variation in the first data line161E or the second data line161O, the electric potential of the gate electrode125ain the first transistor T1may be also affected.

According to the embodiment, the initialization voltage connecting line153to which a constant voltage, e.g., an initialization voltage VINT, may be applied, may be at a layer between the gate electrode125aof the first transistor T1and the data line161in a cross-sectional view as shown inFIG. 7(a part of the initialization voltage connecting line153that may be a protrusion153pof the initialization voltage connecting line153is shown inFIG. 7). The protrusion153pof the initialization voltage connecting line153may be located between an end of the node electrode141and the first data line161E in a plan view as shown inFIG. 5. For example, according to the embodiment, the initialization voltage connecting line153may be on a layer between the data lines161and the node electrode141in order to reduce affection to the electric potential of the gate electrode125aof the first transistor T1due to the voltage variation in the data lines161, and thus, the display device may display high-quality images with precise luminance.

According to an embodiment, as shown inFIG. 8, the electrode voltage layer127and the power voltage connecting line154, to which the first power voltage ELVDD may be applied, may be on layers between the gate electrode125aof the first transistor T1and the data lines161, and thus, the electric potential of the gate electrode125aof the first transistor T1may be prevented or reduced from being affected by the voltage variation in the data lines161. Thus, the display device may display high-quality images with precise luminance. Also, the electrode voltage layer127and the power voltage connecting line154may overlap the data lines161, and thus, the gate electrode125aof the first transistor T1may be shielded.

Each of the data lines161and the power voltage line163may have a single-layered or multi-layered structure including one or more selected from aluminum (Al), platinum (Pt), palladium (Pd), argentum (Ag), magnesium (Mg), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In an embodiment, each of the data lines161and the power voltage line163may each have a multi-layered structure including Ti/Al/Ti.

A fourth connecting electrode165may be further on the first insulating layer116. The fourth connecting electrode165may be connected to the semiconductor layer connecting line156via a contact hole33in the protective layer115and a contact hole33′ in the first insulating layer116. The fourth connecting electrode165may include the same material as that of the power voltage line163. For example, the fourth connecting electrode165may have a single or multi-layered structure including one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), argentum (Ag), magnesium (Mg), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In an embodiment, the fourth connecting electrode165may have a multi-layered structure including Ti/Al/Ti.

A mask process for forming the contact hole in the protective layer115and a mask process for forming a contact hole in the first insulating layer116may be separately performed. The contact holes31′,32′, and33′ in the first insulating layer116may respectively overlap the contact holes31,32, and33in the protective layer115.

A second insulating layer117and a third insulating layer118may be sequentially on the data lines161, the power voltage line163, and the fourth connecting electrode165.

The first insulating layer116, the second insulating layer117, and the third insulating layer118may each be a planarization layer and an organic insulating layer. For example, the first to third insulating layers116,117, and118may each include an organic insulating material such as a general universal polymer (polymethylmethacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenol groups, acryl-based polymer, imide-based polymer, siloxane-based polymer, aryl ether-based polymer, amide-based polymer, fluoride-based polymer, p-xylene-based polymer, vinyl alcohol-based polymer, and blends thereof. In an embodiment, the first and third insulating layers116and118may include organic insulating layers including polyimide, and the second insulating layer117may include an organic insulating layer including siloxane.

In case that the organic light-emitting diode OLED has an uneven structure due to steps among the conductive layers under the organic light-emitting diode OLED, a reflective color band due to the reflection of light emitted from the organic light-emitting diode OLED may be recognized. According to the embodiment, at least two or more organic insulating layers may be provided between the organic light-emitting diode OLED and the thin film transistors, and thus, lower layers of the organic light-emitting diode OLED may be planarized to address the above issue.

The foldable display device according to an embodiment may include the window60of a thin plastic material and may not include a polarization layer between the display panel10and the window60, as shown inFIG. 3. According to the foldable display device of an embodiment, the lower layer of the organic light-emitting diode OLED may be planarized due to the organic insulating layers, and external light reflection may be reduced without using an additional polarization layer.

InFIGS. 7 to 9, two organic insulating layers, for example, the second and third insulating layers117and118, may be between the organic light-emitting diode OLED and the thin film transistor. However, in another embodiment, three or more organic insulating layers may be between the organic light-emitting diode OLED and the thin film transistor.

A display element, for example, the organic light-emitting diode OLED, may be on the third insulating layer118. The organic light-emitting diode OLED may include a first electrode310, for example, a pixel electrode, an intermediate layer320, and a second electrode330, for example, an opposite electrode.

As shown inFIG. 6I, the first electrode310of the organic light-emitting diode OLED may be on the third insulating layer118. The first electrode310in the first pixel area SPA1and the first electrode310in the second pixel area SPA2may be offset from each other. A center of the first electrode310in the first pixel area SPA1and a center of the first electrode310in the second pixel area SPA2may be offset from each other.

The first electrode310may partially extend to a neighboring pixel area that may be adjacent to the pixel area of the first electrode310with the groove GV therebetween. For example, inFIG. 6I, the first electrode310in the first pixel area SPA1may be in the first pixel area SPA1, and may partially extend to the upper portion of the organic material layer180and a second pixel area in another pixel area PXA. The first electrode310in the second pixel area SPA2may be in the second pixel area SPA2, and may partially extend to the first pixel area SPA1and the upper portion of the organic material layer180.

The first electrode310in the first pixel area SPA1or the first electrode310in the second pixel area SPA2may partially overlap the first shielding electrode129. Accordingly, the first electrode310in the first pixel area SPA1or the first electrode310in the second pixel area SPA2may overlap the source/drain region176c/177cbetween the two channel regions131c1and131c2of the third transistor T3in each of the first pixel PXL and the second pixel PXR. For example, the first electrode310in the first pixel area SPA1or the first electrode310in the second pixel area SPA2may function as a shielding layer with the first shielding electrode129, in order to prevent the third transistor T3in each of the first pixel PXL and the second pixel PXR from being affected by the light incident from outside and/or other peripheral electrical signals.

The first electrode310may be connected to the fourth connecting electrode165via a contact hole40in the second insulating layer117and a contact hole40′ in the third insulating layer118as shown inFIG. 9. Accordingly, the first electrode310may be connected to the sixth transistor T6via the semiconductor connecting line156on the second interlayer insulating layer114and the fourth connecting electrode165on the first insulating layer116.

A mask process for forming the contact hole in the second insulating layer117and a mask process for forming the contact hole in the third insulating layer118may be separately performed. The contact hole40′ in the third insulating layer118may overlap the contact hole40in the second insulating layer117.

The first electrode310may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, or aluminum zinc oxide (AZO), or a combination thereof. In another embodiment, the first electrode310may include a reflective layer including argentum (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode310may further include a layer including ITO, IZO, ZnO, or In2O3, or a combination thereof, on and/or under the reflective layer.

A fourth insulating layer119may be on the third insulating layer118. The fourth insulating layer119may include an opening corresponding to each pixel, for example, an opening OP for exposing at least a central portion of the first electrode310. The opening OP in the fourth insulating layer119may define an emission area EA of a pixel. For example, the fourth insulating layer119may correspond to other regions than the emission area EA, for example, non-emission area, and the pixel circuit PC may overlap the emission area EA and/or the non-emission area.

The fourth insulating layer119may increase a distance between an edge of the first electrode310and the second electrode330on the first electrode310to prevent generation of arc at the edge of the first electrode310. The fourth insulating layer119may include an organic material, for example, polyimide (PI), hexamethyldisiloxane (HMDSO), etc., or a combination thereof. A size of the emission area EA may vary depending on a color of light emitted from the pixel.

The intermediate layer320may include an emission layer. The emission layer may include a polymer or low-molecular weight organic material emitting a light (e.g., a color light). In an embodiment, the intermediate layer320may further include a first functional layer under the emission layer and/or a second functional layer on the emission layer. The first functional layer and/or the second functional layer may include a layer formed integrally throughout the first electrodes310or patterned to correspond to each of the first electrodes310.

The first functional layer may have a single-layered or multi-layered structure. For example, in case that the first functional layer includes a polymer material, the first functional layer may include a hole transport layer (HTL) having a single-layered structure, and may include poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT), polyaniline (PANI), or a combination thereof. In case that the first functional layer includes a low-molecular weight material, the first functional layer may include a hole injection layer (HIL) and an HTL.

The second functional layer may be optional. For example, in case that the first functional layer and the emission layer include a polymer material, the second functional layer may be formed in order to improve characteristics of the organic light-emitting diode. The second functional layer may have a single-layered or multi-layered structure. The second functional layer may include an electron transport layer (ETL) and/or an electron injection layer (EIL).

The second electrode330may face the first electrode310with the intermediate layer320therebetween. The second electrode330may include a conductive material having a low work function. For example, the second electrode330may include a (semi-)transparent layer including argentum (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. As another example, the second electrode330may further include a layer including ITO, IZO, ZnO, or In2O3, or a combination thereof on the (semi-)transparent layer including the above material.

The second electrode330may be provided integrally with respect to the organic light-emitting diodes OLED to face the first electrodes310, and may be on the intermediate layer320and the fourth insulating layer119.

The encapsulation layer400may be on the second electrode330to protect the display panel10against external impurities or moisture. The encapsulation layer400may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.FIGS. 7 to 9show that the encapsulation layer400may include first and second inorganic encapsulation layers410and430and an organic encapsulation layer420between the first and second inorganic encapsulation layers410and430. In another embodiment, a stacking order and the number of organic and inorganic encapsulation layers may vary.

The first and second inorganic encapsulation layers410and430may each include one or more inorganic insulating materials from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, etc. The organic encapsulation layer420may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyl disiloxane, an acryl-based resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or a combination thereof. Because the first inorganic encapsulation layer410may be formed along a structure thereunder, the first inorganic encapsulation layer410may have an uneven upper surface. The organic encapsulation layer420may have a sufficient thickness enough to cover the first inorganic encapsulation layer410. An upper surface of the organic encapsulation layer420may be substantially flat throughout the entire display area DA. The second inorganic encapsulation layer430may extend to an outer portion of the organic encapsulation layer420to contact the first inorganic encapsulation layer410, and the organic encapsulation layer420may not be exposed to outside.

FIG. 10is a schematic plan view showing a relationship between pixel areas PXA and connecting lines150according to an embodiment.FIG. 10shows the connecting lines150in the display area DA, patterns of the groove GV and the organic material layer180, and arrangement of the emission areas EA.

The display area DA of the substrate100may include the pixel areas PXA, and each of the pixel areas PXA may include the first pixel area SPA1and the second pixel area SPA2. The inorganic insulating layer IL (seeFIG. 7) including inorganic patterns of island types in the pixel areas PXA may be on the display area DA of the substrate100. The inorganic patterns may be surrounded by the groove GV.

The organic material layer180may be among the inorganic patterns and may include holes (openings). Each of the holes in the organic material layer180may correspond to each of the pixel areas PXA. The groove GV and the organic material layer180in the display area DA may have lattice structures.

The display panel10according to an embodiment may include the pixels PX in the display area DA. The pixels PX may include first color pixels PX1emitting first color light, second color pixels PX2emitting second color light, and third color pixels PX3emitting third color light. The first color pixels PX1, the second color pixels PX2, and the third color pixels PX3may be repeatedly arranged according to a certain pattern in the first direction D1and the second direction D2. In an embodiment, the first color pixels PX1may include red pixels, the second color pixels PX2may include green pixels, and the third color pixels PX3may include blue pixels. In another embodiment, the first color pixels PX1may include red pixels, the second color pixels PX2may include blue pixels, and the third color pixels PX3may include green pixels.

Referring toFIG. 10, the organic light-emitting diode OLED in each of the first color pixels PX1may include a first emission area EA1, the organic light-emitting diode OLED in each of the second color pixels PX2may include a second emission area EA2, and the organic light-emitting diode OLED in each of the third color pixels PX3may include a third emission area EA3.

In each of rows1R,2R,3R . . . , the first emission area EA1of the first color pixel PX1, the second emission area EA2of the second color pixel PX2, the third emission area EA3of the third color pixel PX3, and the second emission area EA2of the second color pixel PX2may be repeatedly arranged in zig-zags in the first direction D1.

In an odd-numbered column1M,3M . . . , the first emission area EA1of the first color pixel PX1and the third emission area EA3of the third color pixel PX3may be alternately arranged in the second direction D2. In an even-numbered column, the second emission area EA2of the second color pixel PX2may be repeatedly arranged in the second direction D2. For example, in a first column1M, the first emission area EA1of the first color pixel PX1and the third emission area EA3of the third color pixel PX3may be alternately arranged in the second direction D2. In a second column2M that may be adjacent to the first column1M, the second emission area EA2of the second color pixel PX2may be repeatedly arranged in the second direction D2. In a third column3M adjacent to the second column2M, the third emission area EA3of the third color pixel PX3and the first emission area EA1of the first color pixel PX1may be alternately arranged in the second direction D2, opposite the first column1M.

The first emission area EA1of the first color pixel PX1, the second emission area EA2of the second color pixel PX2, and the third emission area EA3of the third color pixel PX3may have different areas from one another. In an embodiment, the third emission area EA3of the third color pixel PX3may have an area greater than that of the first emission area EA1of the first color pixel PX1. Also, the third emission area EA3of the third color pixel PX3may have an area greater than that of the second emission area EA2of the second color pixel PX2. Also, the first emission area EA1of the first color pixel PX1may have an area greater than that of the second emission area EA2of the second color pixel PX2. In another embodiment, the third emission area EA3of the third color pixel PX3may have an area equal to that of the first emission area EA1of the first color pixel PX1. However, one or more embodiments are not limited thereto. For example, the first emission area EA1of the first color pixel PX1may be greater than the second emission area EA2of the second color pixel PX2and the third emission area EA3of the third color pixel PX3.

The first to third emission areas EA1, EA2, and EA3may each have a polygonal shape such as a rectangular shape, an octagonal shape, etc., a circular shape, an elliptical shape, etc., and the polygonal shape may have rounded vertices.

In each of the rows1R,2R,3R . . . , the pixel areas PXA may each include a pair of color pixels arranged therein may be separated by the groove GV, and the pixels PX in the pixel areas PXA may be connected to one another by the connecting lines150. The pixel area PXA in an odd-numbered row and the pixel area PXA in an even-numbered row may be offset from each other as much as the first pixel area SPA1or the second pixel area SPA2. Accordingly, in the pixel area PXA of the odd-numbered rows1R,3R, . . . , the first color pixel PX1or the third color pixel PX3may be in the first pixel area SPA1and the second color pixel PX2may be in the second pixel area SPA2. In the pixel area PXA of the even-numbered rows2R, . . . , the second color pixel PX2may be in the first pixel area SPA1and the first color pixel PX1or the third color pixel PX3may be in the second pixel area SPA2.

FIG. 11is a schematic diagram showing locations of thin film transistors and a capacitor in each of two adjacent pixels according to another embodiment.FIG. 12Ais a partially enlarged schematic view of a left capacitor ofFIG. 11, andFIG. 12Bis a schematic cross-sectional view of the left capacitor taken along line IV-IV′ ofFIG. 12A. Because the embodiment illustrated with reference toFIG. 11is the same as the embodiment ofFIG. 5except for a shape of the node electrode141, descriptions about the same elements as those ofFIG. 5are omitted.

An end of the node electrode141inFIG. 5may have a size corresponding to the opening128in the first portion of the electrode voltage layer127aor the second portion of the electrode voltage layer127b. The node electrode141shown inFIGS. 12A and 12Bmay include a first protrusion141p1and a second protrusion141p2that may expand to the periphery of the opening128in the first electrode voltage layer127a. The first protrusion141p1and the second protrusion141p2of the node electrode141may overlap the first electrode voltage layer127a. The power voltage connecting line154may overlap the first protrusion141p1and the second protrusion141p2of the node electrode141. Accordingly, the capacitor Cst may be formed by a stacked structure, for example, the gate electrode125aof the first transistor T1and the electrode voltage layer127a, the electrode voltage layer127aand the first and second protrusions141p1and141p2of the node electrode141, the first and second protrusions141p1and141p2of the node electrode141and the power voltage connecting line154, and thus, a capacitance of the capacitor Cst may be ensured.

FIG. 13is a schematic diagram showing locations of thin film transistors and a capacitor in each of two adjacent pixels according to another embodiment.FIGS. 14A to 14Hare schematic plan views showing elements such as thin film transistors, the capacitor, and a pixel electrode shown inFIG. 13according to layers.FIG. 15is a schematic cross-sectional view of the pixels taken along lines V-V′, VI-VI′, and VII-VII′ ofFIG. 13. InFIG. 15, layers arranged after the second insulating layer117are omitted for convenience of disclosure. Hereinafter, elements different from those ofFIG. 5will be described, and descriptions about the same elements as those ofFIG. 5will be omitted.

Referring toFIGS. 13 and 14A, the semiconductor layer ACT may be on the buffer layer110of the substrate100in units of the pixel area PXA. The semiconductor layer ACT may include the first semiconductor layer ACT1of the first pixel area SPA1, the second semiconductor layer ACT2of the second pixel area SPA2, and the third semiconductor layer ACT3where the first semiconductor layer ACT1and the second semiconductor layer ACT2may be connected.

In the semiconductor layer ACT ofFIG. 14A, a distance D between a semiconductor layer ACTg of the first semiconductor layer ACT1and a semiconductor layer ACTg of the second semiconductor layer ACT2in the first direction D1may be greater than a distance between the semiconductor layer ACTg of the first semiconductor layer ACT1and the semiconductor layer ACTg of the second semiconductor layer ACT2in the first direction D1shown inFIG. 5. A gate insulating layer111may be on the semiconductor layer ACT.

Referring toFIGS. 13 and 14B, the gate electrodes125a,125b,125c,125d,125e,125f, and125gof the first to seventh transistors T1to T7, the first scan line121, the second scan line122, and the emission control line123may be on the first gate insulating layer111. The second scan line122may include a 2-1 scan line122ain the first pixel area SPA1and a 2-2 scan line122bin the second pixel area SPA2. The second scan line122may further include a protrusion122pat a boundary between the first pixel area SPA1and the second pixel area SPA2. A second gate insulating layer112may be on the gate electrodes of the first to seventh transistors T1to T7.

Referring toFIGS. 13 and 14C, the electrode voltage layer127and the first shielding electrode129may be on the second gate insulating layer112. Each of the first portion127aand the second portion127bin the electrode voltage layer127may include an opening128. A first interlayer insulating layer113may be on the electrode voltage layer127and the first shielding electrode129.

Referring toFIGS. 13 and 14D, the node electrode141, the first connecting electrode145, and the second connecting electrode147may be on the first interlayer insulating layer113. A fifth connecting electrode142, a sixth connecting electrode144, a seventh connecting electrode146, an eighth connecting electrode148, and a ninth connecting electrode149may be further provided on the first interlayer insulating layer113.

The node electrode141may be connected to the drain region177cof the third transistor T3, the drain region177dof the fourth transistor T4, and the gate electrode125aof the first transistor T1via the contact holes11and12. The first connecting electrode145may be connected to the drain region177eof the fifth transistor T5via the contact hole14. The first connecting electrode145may overlap the upper electrode127of the capacitor Cst. The second connecting electrode147may be connected to the first shielding electrode129and the electrode voltage layer127via the contact holes16and17.

The fifth connecting electrode142may be in each of the first pixel area SPA1and the second pixel area SPA2. The fifth connecting electrode142may be connected to the source region176gof the seventh transistor T7via the contact hole51in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The sixth connecting electrode144may be at the boundary between the first pixel area SPA1and the second pixel area SPA2. The sixth connecting electrode144may overlap the protrusion122pof the second scan line122, and may be connected to the protrusion122pof the second scan line122via the contact hole52in the second gate insulating layer112and the first interlayer insulating layer113.

The seventh connecting electrode146may be at the boundary between the first pixel area SPA1and the second pixel area SPA2, and may extend in the first direction D1. The seventh connecting electrode146may overlap the third semiconductor layer ACT3where the first semiconductor layer ACT1and the second semiconductor layer ACT2may be connected. The seventh connecting electrode146may be connected to the third semiconductor layer ACT3via the contact hole53in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113, and thus, may be connected to the source region176dof the fourth transistor T4and the drain region177gof the seventh transistor T7in each of the first pixel PXL and the second pixel PXR.

The eighth connecting electrode148may be each of the first pixel area SPA1and the second pixel area SPA2. The eighth connecting electrode148may be connected to the source region176bof the second transistor T2via the contact hole54in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The ninth connecting electrode149may be adjacent to the boundary between the first pixel area SPA1and the second pixel area SPA2. The ninth connecting electrode149may be connected to the drain region177fof the sixth transistor T6via the contact hole55in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The second interlayer insulating layer114may cover the conductive layers on the first interlayer insulating layer113.

Before forming the conductive layers shown inFIG. 14Dand after forming the contact holes in the inorganic insulating layer IL, a dehydrogenation annealing process may be performed on the semiconductor layer. A driving range of a driving transistor may be increased due to the annealing process.

FIGS. 14E and 14Falso show the conductive layers shown inFIGS. 14A to 14D. Referring toFIGS. 13 and 14E, contact holes21a,21b,22c,23a,23b,24c,24d,24e,25,26a,27a, and28a, through which the conductive layers on the second interlayer insulating layer114may be in contact with lower conductive layers, may be in at least one of the first to fourth gate insulating layers111,112,113, and114in the pixel area PXA.FIG. 14Eonly shows locations corresponding to the contact holes21a,21b,22c,23a,23b,24c,24d,24e,25,26a,27a, and28aand insulating layers are omitted for convenience of description and disclosure.

Referring toFIGS. 13 and 14F, after forming the contact holes21a,21b,22c,23a,23b,24a,24b,24c,25,26a,27a, and28ain the pixel area PXA, the groove GV surrounding the pixel area PXA may be formed in the inorganic insulating layer IL. The organic material layer180may be filled in the groove GV in the inorganic insulating layer IL. For example, a mask process for forming the groove GV may be separately performed from the mask process for forming the contact holes21a,21b,22c,23a,23b,24c,24d,24e,25,26a,27a, and28a.

In an embodiment, a process of forming the groove GV may be performed simultaneously with a second mask process for removing the inorganic insulating layer IL on a bending area of the substrate100. In order to reduce an area of the peripheral area PA recognized by a user, the substrate100may include the bending area in the peripheral area PA. The bending area may be a separate area from the foldable area FA, and may be, in the peripheral area PA, between a pad area at a side of the substrate100and the display area DA. The substrate100may be bent at the bending area, and the pad area may at least partially overlap the display area DA. A bending direction may be set such that the pad area may not block the display area DA, but may be located behind the display area DA. Accordingly, the user may recognize that the display area DA occupies most of the display device. Pads in the pad area may be electrically connected to a soft film on which a driver chip may be arranged. The organic material layer may be filled in a region of the bending area, from which the inorganic insulating layer IL may be removed.

Referring toFIGS. 13 and 14G, the connecting lines150and the third connecting electrode157may be on the second interlayer insulating layer114. The connecting lines150may include a first scan connecting line151, a second scan connecting line152, an initialization voltage connecting line153, a power voltage connecting line154, an emission control connecting line155, and a semiconductor layer connecting line156.

The second scan connecting line152may be connected to the second scan line122via the contact hole22cin the second gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114at the boundary between the first pixel area SPA1and the second pixel area SPA2.

As shown inFIG. 15, the initialization voltage connecting line153may overlap the seventh connecting electrode146, and may be connected to the seventh connecting electrode146via the contact holes23aand23bin the second interlayer insulating layer114.

As shown inFIG. 14G, the power voltage connecting line154may include a first protrusion154p1and a second protrusion154p2protruding in the second direction D2. The power voltage connecting line154may be connected to the first connecting electrode145via the contact holes24cand24din the second interlayer insulating layer114, and may be connected to the second connecting electrode147via a contact hole24ein the second interlayer insulating layer114.

As shown inFIG. 14GandFIG. 15, an end of the semiconductor layer connecting line156may be connected to the fifth connecting electrode142via the contact hole26ain the second interlayer insulating layer114and thus may be connected to the source region176gof the seventh transistor T7. Another end of the semiconductor layer connecting line156may be connected to the ninth connecting electrode149via the contact hole27ain the second interlayer insulating layer114, and thus may be connected to the drain region177fof the sixth transistor T6.

As shown inFIG. 15, the third connecting electrode157may be connected to the eighth connecting electrode148via the contact hole28ain the second interlayer insulating layer114, and thus may be connected to the source region176bof the second transistor T2.

The protective layer115may be on the connecting lines150and the third connecting electrode157. The protective layer115may not cover the organic material layer180. The first insulating layer116may be further on the protective layer115. A mask process for forming the contact hole in the protective layer115and a mask process for forming a contact hole in the first insulating layer116may be separately performed.

Referring toFIGS. 13 and 14H, the data lines161, the power voltage line163, and the fourth connecting electrode165may be on the first insulating layer116. As shown inFIGS. 7 to 9, the second insulating layer117and the third insulating layer118may be sequentially on the data lines161, the power voltage line163, and the fourth connecting electrode165ofFIG. 14H. The organic light-emitting diode OLED may be on the third insulating layer118. The encapsulation layer400may be on the organic light-emitting diode OLED.

The embodiment illustrated with reference toFIG. 13may be different from the embodiment ofFIG. 5, in that the mask process for forming the groove GV by removing the inorganic insulating layer IL and the mask process for forming the contact holes by removing the first and second gate insulating layers111and112and the first and second interlayer insulating layers113and114in the pixel area PXA may be separately performed, as shown inFIGS. 14E and 14F.

According to a limitation in a hole depth in the mask process for forming the contact holes, as shown inFIG. 15, the seventh connecting electrode146, the eighth connecting electrode148, and the ninth connecting electrode149may be additionally on the first interlayer insulating layer113, and each of the initialization voltage connecting line153, the third connecting electrode157, and the semiconductor layer connecting line156may not be in contact (e.g., direct contact) with the semiconductor layer, but may be connected to the semiconductor layer thereunder via each of the seventh connecting electrode146, the eighth connecting electrode148, and the ninth connecting electrode149.

FIG. 16is a schematic diagram showing locations of thin film transistors and a capacitor in each of two adjacent pixels according to another embodiment.FIGS. 17A to 17Fare schematic plan views showing elements such as thin film transistors, the capacitor, and a pixel electrode shown inFIG. 16according to layers.FIGS. 18 to 20are schematic cross-sectional views of the pixels taken along lines VIII-VIII′, IX-IX′, and X-X′ ofFIG. 16. InFIG. 15, layers arranged after the first insulating layer115are omitted for convenience of disclosure. Hereinafter, elements different from those ofFIG. 5will be described, and descriptions about the same elements as those ofFIG. 5will be omitted.

Referring toFIGS. 16 and 17A, the semiconductor layer ACT may be on the buffer layer110of the substrate100in units of the pixel area PXA. The semiconductor layer ACT may include the first semiconductor layer ACT1in the first pixel area SPA1and the second semiconductor layer ACT2in the second pixel area SPA2. The first semiconductor layer ACT1and the second semiconductor layer ACT2may be separated from each other. The gate insulating layer111may be on the semiconductor layer ACT. The first semiconductor layer ACT1and the second semiconductor layer ACT2may be symmetrical with each other.

Referring toFIGS. 16 and 17B, the gate electrodes125a,125b,125c,125d,125e,125f, and125gof the first to seventh transistors T1to T7, the first scan line121, the second scan line122, and the emission control line123may be on the first gate insulating layer111. The second gate insulating layer112may be on the gate electrodes of the first to seventh transistors T1to T7.

Referring toFIGS. 16 and 17C, the electrode voltage layer127may be on the second gate insulating layer112. Each of the first portion127aand the second portion127bin the electrode voltage layer127may include the opening128. The electrode voltage layer127may further include a protrusion127pprotruding from each of the first portion127aand the second portion127bin the second direction D2. The protrusions127pmay overlap the source/drain region176c/177cbetween the two channel regions131c1and131c2of the third transistor T3in each of the first pixel PXL and the second pixel PXR. For example, the protrusions127pmay act as shielding portions that may prevent the third transistor T3in each of the first pixel PXL and the second pixel PXR from being affected by light incident from outside and/or other electrical signals. The first interlayer insulating layer113may be on the electrode voltage layer127.

FIG. 17Dshows the conductive layers shown inFIGS. 17A to 17Caltogether. Referring toFIGS. 16 and 17D, contact holes71,72,73a,73b,74,75,76,77,78a,78b,79a, and79b, through which the conductive layers on the first interlayer insulating layer113may be in contact with lower conductive layers, may be formed in at least one of the first and second gate insulating layers111and112and the first interlayer insulating layer113in the pixel area PXA.FIG. 17Donly shows locations corresponding to the contact holes71,72,73a,73b,74,75,76,77,78a,78b,79a, and79band insulating layers may be omitted for convenience of description and disclosure.

The groove GV surrounding the pixel areas PXA may be formed in the buffer layer110, the first and second gate insulating layers111and112, and the first interlayer insulating layer113. In an embodiment, the mask process for forming the groove GV may be separately performed from the mask process for forming the contact holes71,72,73a,73b,74,75,76,77,78a,78b,79a, and79b. The groove GV may be obtained through two mask processes, for example, a mask process for removing the inorganic insulating layer after forming the first gate insulating layer111and a mask process for removing the inorganic insulating layer after forming the first interlayer insulating layer113. In another embodiment, the groove GV may be simultaneously obtained with the mask process for forming the contact holes71,72,73a,73b,74,75,76,77,78a,78b,79a, and79b. The organic material layer180may be filled in the groove GV in the inorganic insulating layer IL.

Referring toFIGS. 16 and 17E, the connecting lines150and connecting electrodes may be on the first interlayer insulating layer113.

The connecting lines150may include a first scan connecting line151′, a second scan connecting line152′, the initialization voltage connecting line153, the emission control connecting line155, and the semiconductor layer connecting line156.

The first scan connecting line151′ may extend in the first direction D1across the upper portion of the organic material layer180that may surround the pixel area PXA. An end of the first scan connecting line151′ may be connected to the 1-1 scan line121aor the 1-2 scan line121bin the pixel area PXA via the contact hole71in the second gate insulating layer112and the first interlayer insulating layer113. Another end of the first scan connecting line151′ may be connected to the 1-1 scan line121aor the 1-2 scan line121bin the pixel area PXA adjacent thereto in the first direction D1via the contact hole71in the second gate insulating layer112and the first interlayer insulating layer113. An end and another end of the first scan connecting line151′ may be in different pixel areas PXA with the groove GV therebetween, in order to connect the first scan lines121in adjacent pixels PX in the first direction D1.

The second scan connecting line152′ may extend in the first direction D1across the upper portion of the organic material layer180that may surround the pixel area PXA. An end of the second scan connecting line152′ may be connected to the 2-1 scan line122aor the 2-2 scan line122bin the pixel area PXA via the contact hole72in the second gate insulating layer112and the first interlayer insulating layer113. Another end of the second scan connecting line152′ may be connected to the 2-1 scan line122aor the 2-2 scan line122bin the pixel area PXA adjacent thereto in the first direction D1via the contact hole72in the second gate insulating layer112and the first interlayer insulating layer113. An end and another end of the second scan connecting line152′ may be in different pixel areas PXA with the groove GV therebetween, in order to connect the second scan lines122in adjacent pixels PX in the first direction D1.

The initialization voltage connecting line153may extend in the first direction D1across the first pixel area SPA1and the second pixel area SPA2. The initialization voltage connecting line153may be connected to the source region176dof the fourth transistor T4and the drain region177gof the seventh transistor T7in each of the first pixel PXL and the second pixel PXR via the contact holes73aand73bin the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The emission control connecting line155may extend in the first direction D1while overlapping the emission control line123, and may be arranged across the first pixel area SPA1and the second pixel area SPA2. The emission control connecting line155may be connected to the emission control line123via the contact hole74in the second gate insulating layer112and the first interlayer insulating layer113at the boundary between the first pixel area SPA1and the second pixel area SPA2.

The semiconductor layer connecting line156may extend in the second direction D2across an upper portion of the organic material layer180surrounding the pixel area PXA. An end of the semiconductor layer connecting line156may be connected to the source region176gof the seventh transistor T7via the contact hole75in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113. Another end of the semiconductor layer connecting line156may be connected to the drain region177fof the sixth transistor T6via the contact hole76in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113. An end and another end of the semiconductor layer connecting line156may be in different pixel areas PXA with the groove GV therebetween, in order to connect the semiconductor layers in adjacent pixels PX in the second direction D2.

The third connecting electrode157may be connected to the source region176bof the second transistor T2via the contact hole77in the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

A node connecting electrode158may include a first node connecting electrode158aand a second node connecting electrode158b. The first node connecting electrode158amay be connected to the gate insulating layer125aof the first transistor T1via the contact hole78ain the second gate insulating layer112and the first interlayer insulating layer113. The second node connecting electrode158bmay be connected to the drain region177cof the third transistor T3and the drain region177dof the fourth transistor T4via the contact hole78bin the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The power voltage connecting electrode159may include a first power voltage connecting electrode159aand a second power voltage connecting electrode159b. The first power voltage connecting electrode159amay be connected to the electrode voltage layer127via the contact hole79ain the first interlayer insulating layer113. The second power voltage connecting electrode159bmay be connected to the drain region177eof the fifth transistor T5via the contact hole79bin the first gate insulating layer111, the second gate insulating layer112, and the first interlayer insulating layer113.

The protective layer115may be on the connecting lines150and the connecting electrodes. The protective layer115may not cover the organic material layer180. The first insulating layer116may be further on the protective layer115. A mask process for forming the contact hole in the protective layer115and a mask process for forming a contact hole in the first insulating layer116may be separately performed.

Referring toFIGS. 16 and 17F, the data line161, the power voltage line163, the fourth connecting electrode165, and the node electrode167may be on the first insulating layer116.

The power voltage line163may be connected to the first power voltage connecting electrode159aand the second power voltage connecting electrode159bvia the contact holes32aand32bin the protective layer115and contact holes32a′ and32b′ in the first insulating layer116.

The node electrode167may be connected to the first node connecting electrode158aand the second node connecting electrode158bvia the contact holes34aand34bin the protective layer115and contact holes34a′ and34b′ in the first insulating layer116.

As shown inFIGS. 7 to 9, the second insulating layer117and the third insulating layer118may be sequentially on the data line161, the power voltage line163, the fourth connecting electrode165, and the node electrode167ofFIG. 17F. The organic light-emitting diode OLED may be on the third insulating layer118. An encapsulation layer400may be on the organic light-emitting diode OLED.

According to the embodiment illustrated with reference toFIG. 16, the conductive layers shown inFIGS. 17B and 17Cmay be formed by using low-resistive metal and connected to the connecting lines ofFIG. 17E, and thus, the mask processes may be reduced as compared with the embodiments illustrated inFIGS. 5 and 13, without providing the connecting conductive layers as shown inFIGS. 6D and 14D. The conductive layers shown inFIGS. 17B and 17Cmay have a single-layered structure including a low-resistive metal material such as aluminum (Al), aluminum alloy (Al-alloy), or copper (Cu), or a combination thereof, or a multi-layered structure including one or more metal selected from platinum (Pt), palladium (Pd), argentum (Ag), magnesium (Mg), aurum (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), and tungsten (W). For example, the conductive layers shown inFIGS. 17B and 17Cmay each have a single-layered structure including aluminum alloy, or a multi-layered structure including aluminum alloy/TiN, TiN/aluminum alloy/TiN, etc.

FIG. 21is a schematic cross-sectional view of a display device according to an embodiment,FIG. 22is a schematic diagram showing a relationship between a black matrix and an emission area inFIG. 21, andFIG. 23is a schematic diagram showing a relationship between a color filter and the emission area ofFIG. 21.

Referring toFIG. 21, a black matrix BM and a color filter CF may be on the encapsulation layer400as optical functional layers. As shown inFIG. 22, the black matrix BM may surround the emission areas EA and may correspond to other regions than the openings OP in the fourth insulating layer119. As shown inFIG. 23, the color filter CF may at least correspond to the emission areas EA. The color filter CF may include a first color filter CF1selectively transmitting first color light, a second color filter CF2selectively transmitting second color light, and a third color filter CF3selectively transmitting a third color light. The first color filter CF1, the second color filter CF2, and the third color filter CF3may be arranged adjacent to one another in a certain pattern. The black matrix BM may correspond to boundaries among the first color filter CF1, the second color filer CF2, and the third color filter CF3. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3may partially overlap the black matrix BM.

Although not shown in the drawings, an input sensing layer may be further provided between the black matrix BM and the color filter CF, and the encapsulation layer400.

According to one or more embodiments, pixel groups may be provided as islands by using the groove and the organic material layer, and the pixel groups of the island type may be connected by using flexible connecting lines to provide the foldable display device of a high resolution, which may be robust against internal shock. According to one or more embodiments, some of the connecting lines for connecting the pixel groups may be used as the shielding layer for preventing the coupling (cross-talk) between the gate node of the driving thin film transistor and the data line, and thus, the display device of high image quality may be provided. Also, according to one or more embodiments, a structure for shielding a floating node between the two channel regions of the thin film transistor having the double-gate structure may be provided, and thus, leakage of the thin film transistor may be reduced.

According to one or more embodiments, the inorganic insulating layer including the groove and the organic material layer filling the groove may be provided in the regions among the pixels, and thus, the high resolution display device that may be robust against the external shock and flexible may be implemented. However, the scope of the disclosure is not limited to the above effects.