Source/drain zones with a delectric plug over an isolation region between active regions and methods

Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

FIELD

The present disclosure relates generally to source/drain zones and in particular the present disclosure relates to source/drain zones with a dielectric plug over an isolation region between active regions and methods.

BACKGROUND

Flash memory devices (e.g., NAND, NOR, etc.) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory may include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

In a NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a data line, such as a bit line. A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line.

Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, e.g., source to drain, between a pair of select lines, e.g., a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line. For example, each drain select gate may be coupled to a data line by a contact.

In order for memory manufacturers to remain competitive, memory designers are constantly trying to increase the density of memory devices. Increasing the density of a flash memory device generally requires reducing the spacing between memory cells in adjacent columns and between adjacent data lines respectively coupled to those columns. However, reduced spacing may increase the likelihood that the contacts that couple data lines to drain select gates may be misaligned. Misaligned contacts may cause shorts to occur between adjacent data lines and thus shorts to occur between adjacent columns of memory cells.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing methods for forming contacts that couple data lines to drain select gates.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term semiconductor can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

FIG. 1is a simplified block diagram of a NAND flash memory device100in communication with a processor130as part of an electronic system, according to an embodiment. The processor130may be a memory controller or other external host device.

Memory device100includes an array of memory cells104formed in accordance with embodiments of the disclosure. That is, memory array104may include source/drain zone having active regions that may be coupled to contacts that may be coupled to data lines, such as bit lines. A source/drain zone is a portion of the memory array104in which source/drain regions of select gates may be formed for one or more strings of memory cells. The source/drain zone may include an isolation region and a dielectric plug, e.g., a nitride plug, between adjacent active regions. The dielectric plug may extend below upper surfaces of the adjacent active regions. The dielectric plug may have a lower removal rate (e.g., etch rate) than the isolation regions for a particular isotropic removal (e.g., etch) chemistry, e.g., isopropyl alcohol and ammonium bifluoride (NH4HF2), ammonium fluoride (NH4F) and phosphoric acid (H3PO4), etc. The dielectric plug may act to reduce the likelihood of shorts that may occur between a misaligned contact and an adjacent active region.

A row decoder108and a column decoder110are provided to decode address signals. Address signals are received and decoded to access memory array104.

Memory device100also includes input/output (I/O) control circuitry112to manage input of commands, addresses, and data to the memory device100as well as output of data and status information from the memory device100. An address register114is in communication with I/O control circuitry112, and row decoder108and column decoder110, to latch the address signals prior to decoding. A command register124is in communication with I/O control circuitry112and control logic116to latch incoming commands. Control logic116controls access to the memory array104in response to the commands and generates status information for the external processor130. The control logic116is in communication with row decoder108and column decoder110to control the row decoder108and column decoder110in response to the addresses.

Control logic116is also in communication with a cache register118. Cache register118latches data, either incoming or outgoing, as directed by control logic116to temporarily store data while the memory array104is busy writing or reading, respectively, other data. During a write operation, data are passed from the cache register118to data register120for transfer to the memory array104; then new data is latched in the cache register118from the I/O control circuitry112. During a read operation, data is passed from the cache register118to the I/O control circuitry112for output to the external processor130; then new data is passed from the data register120to the cache register118. A status register122is in communication with I/O control circuitry112and control logic116to latch the status information for output to the processor130.

Memory device100receives control signals at control logic116from processor130over a control link132. The control signals may include at least a chip enable CE#, a command latch enable CLE, an address latch enable ALE, and a write enable WE#. Memory device100receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor130over a multiplexed input/output (I/O) bus134and outputs data to processor130over I/O bus134.

For example, the commands are received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and are written into command register124. The addresses are received over input/output (I/O) pins [7:0] of bus134at I/O control circuitry112and are written into address register114. The data are received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry112and are written into cache register118. The data are subsequently written into data register120for programming memory array104. For another embodiment, cache register118may be omitted, and the data are written directly into data register120. Data are also output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins may be used in the various embodiments.

FIG. 2is a schematic of a NAND memory array200, e.g., as a portion of memory array104, in accordance with another embodiment. Memory array200includes access lines, such as word lines2021to202N, and intersecting data lines, such as bit lines2041to204M. For ease of addressing in the digital environment, the number of word lines202and the number of bit lines204are each some power of two, e.g., 256 word lines202by 4,096 bit lines204. The bit lines204may be coupled to global data lines, such as global bit lines (not shown), in a many-to-one relationship.

Memory array200is arranged in rows (each corresponding to a word line202) and columns (each corresponding to a bit line204). Each column may include a string, such as one of NAND strings2061to206M. Each NAND string206is coupled to a common source line216and includes memory cells2081to208N, each located at an intersection of a word line202and a bit line204. The memory cells208represent non-volatile memory cells for storage of data. The memory cells208of each NAND string206are connected in series, e.g., source to drain, between a source select line214and a drain select line215.

Source select line214includes a source select gate210, e.g., a field-effect transistor (FET), at each intersection between a NAND string206and source select line214, and drain select line215includes a drain select gate212, e.g., a field-effect transistor (FET), at each intersection between a NAND string206and drain select line215. In this way, the memory cells208of each NAND string206are connected between a source select gate210and a drain select gate212.

A source of each source select gate210is connected to common source line216. The drain of each source select gate210may be connected to the source of the memory cell208of the corresponding NAND string206. For example, the drain of source select gate2101may be connected to the source of memory cell2081of the corresponding NAND string2061. Therefore, each source select gate210selectively couples a corresponding NAND string206to common source line216. A control gate220of each source select gate210is connected to source select line214.

The drain of each drain select gate212is connected to the bit line204for the corresponding NAND string at a contact228(e.g., that may be called a drain contact), such as a data-line contact, e.g., a bit-line contact. For example, the drain of drain select gate2121may be connected to the bit line2041for the corresponding NAND string2061at contact2281. The source of each drain select gate212may be connected to the drain of the last memory cell208Nof the corresponding NAND string206. For example, the source of drain select gate2121may be connected to the drain of memory cell208Nof the corresponding NAND string2061. Therefore, each drain select gate212selectively couples a corresponding NAND string206to a corresponding bit line204. A control gate222of each drain select gate212is connected to drain select line215.

Typical construction of memory cells208includes a source230and a drain232, a charge-storage structure234(e.g., a floating gate, charge trap, etc.) that can store a charge that determines a data value of the cell, and a control gate236, as shown inFIG. 2. Memory cells208have their control gates236coupled to (and in some cases from) a word line202. A column of the memory cells208is a NAND string206coupled to a given bit line204. A row of the memory cells208are those memory cells commonly coupled to a given word line202.

Although the examples ofFIGS. 1 and 2were discussed in conjunction with NAND flash, the embodiments described herein are not limited to NAND flash, but can include other flash architectures, such as NOR flash, etc.

FIG. 3is a cross-section illustrating an aligned contact3281and a misaligned contact3282, according to the prior art. For example, contacts328may be referred to as data-line contacts, e.g., bit-line contacts, or drain contacts. Contact3281is substantially vertically aligned (e.g., vertically aligned) with an active region3301. An isolation region3351may isolate active region3301from an active region3302. Isolation region3351may electrically isolate, at least in part, contact3281from active region3302.

An isolation region3352may isolate an active region3303from active region3302. Contact3282was intended to be substantially vertically aligned (e.g., vertically aligned) with active region3302, but, e.g., owing to processing errors, overlaps isolation region3352. This misalignment may give rise to an electrical short between active region3303and active region3302due to the portion340of contact3282coming in contact with active region3302. Note that the portions of active regions330shown inFIG. 3may be source/drains (e.g., drains) of drain select gates respectively formed over active regions330.

Contacts3281and3282may respectively couple data lines through active regions3301and3303to the drain select gates that are respectively formed over active regions3301and3303. The drain select gates that are respectively formed over active regions3301and3303may selectively couple the data lines respectively coupled to contacts3281and3282to strings of memory cells respectively formed over active regions3301and3303.

A drain select gate may be formed over active region3302and may be coupled to a string of memory cells formed over active region3302. A contact (e.g., located in a plane parallel to the face plane ofFIG. 3and thus not shown) may couple a data line through active region3302to the drain select gate formed over active region3302so that the drain select gate formed over active region3302selectively couples the data line to the string of memory cells formed over active region3302. Therefore, due to its misalignment, contact3282may electrically short the data line coupled thereto, and thus the string of memory cells formed over active region3303, to the string of memory cells formed over active region3302and to the data line selectively coupled to the string of memory cells formed over active region3302by the drain select gate formed over active region3302.

Contacts3281and3282may be respectively formed in openings3451and3452that may terminate at a dielectric348over a dielectric350, as shown inFIG. 3. For example, openings345may be formed in a dielectric formed over dielectric348. Dielectric348may be a nitride and dielectric350may be an oxide. It is intended that openings3451and3452be respectively substantially vertically aligned (e.g., vertically aligned) with an active regions3301and3303but, e.g., owing to processing errors, opening3452overlaps isolation region3352so that opening3452is misaligned with active region3303.

A protective liner355may be formed in openings3451and3452. Portions of dielectric348and dielectric350under openings3451and3452may then be removed through openings3451and3452, stopping at active regions3301and3303so that opening3451exposes active region3301and opening3452exposes a portion of active region3303and a portion of isolation region3352, owing to the misalignment of opening3452. Protective liner355may extend to dielectric348, as shown inFIG. 3.

Subsequently, a clean operation (e.g., a clean-up etch) may be performed, e.g., using a wet etch, such as an isotropic wet etch, to remove native oxide that may form on the exposed surfaces of active regions3301and3303for improving electrical contact between contacts3281and3282and active regions3301and3303. For example, etchant, e.g., having the particular isotropic removal chemistry, may be introduced through openings345.

The etch may remove a portion of isolation region3351and a portion of dielectric350to form a region3601that may extend from opening3451into isolation region3351, in that isolation region335kand dielectric350may etch at about the same rate as the native oxide when exposed to the etchant that removes the native oxide. In other words, the etch that removes the native oxide may be selective to isolation region3351and dielectric350, as well as the native oxide.

However, due to the fact that misaligned opening3452overlaps isolation region3352, the etch may remove a portion of isolation region3352, a portion of dielectric348, and a portion of active region3302to form a region3602that extends from opening3452into active region3302. Openings3451and3452may be filled with a conductor365that also fills regions3601and3602to form contacts3281and3282, where contact3281includes a portion370formed by the conductor365in region3601and contact3282includes the portion340formed by the conductor365in region3602.

FIG. 4is a top plan view of a memory array400, such as a portion of memory array104inFIG. 1and memory array200inFIG. 2.FIG. 4is intended to show where the various cross-sections discussed below are taken and how the various cross-sections relate to the overall layout of memory array400. Memory array may400include a plurality of active regions410, extending along a column direction. An isolation region415, such as a shallow trench isolation (STI) region, extending in the column direction, may be between active regions410. For example, active regions410may alternate and an isolation region may be between and successively adjacent to active regions410.

One or more columns of (e.g., one or more strings of memory cells coupled in series) may be formed over each active region410. For example, a string of memory cells may be over each active region410within a memory-cell region, such as a string region420, of memory array400. String region420may be between a select-gate, such as a drain-select-gate, region425of memory array400, denoted by the indicia SG1, and a select-gate, such as a source-select-gate, region430of memory array400, denoted by the indicia SG2.

A select gate, such as a drain select gate, may be formed over each active region410within drain-select-gate region425, and a select gate, such as a source select gate, may be formed over each active region410within source-select-gate region430. The drain select gate over a respective active region410may be coupled to (e.g., in series with) one end of a string of memory cells formed over the respective active region410in string region420, and the source select gate over the respective active region410may be coupled to (e.g., in series with) an opposite end of the string of memory cells formed over the respective active region410in string region420.

For some embodiments, the strings of memory cells in string region420that are formed over every other active region410, e.g., formed over active regions4101, may be selectively coupled to contacts4401through the drain select gates within drain-select-gate region425formed over active regions4101. In other words, the strings of memory cells that are formed over alternate active regions410may be selectively coupled to contacts4401. For example, contacts4401may be coupled to active regions4101.

An active region4102and an isolation region415on either side of that active region4102may be between a pair of active regions4101. As such, active regions4102are alternating active regions. For some embodiments, the strings of memory cells in string region420that are formed over active regions4102may be coupled to contacts4402through the drain select gates within drain-select-gate region425formed over active regions4102. For example, contacts4402may be coupled to active regions4102. Contacts440may be staggered. For example, contacts4401may be offset from contacts4402. Contacts440may be referred to as data-line contacts, e.g., bit-line contacts, or drain contacts.

Source/drains, e.g., drains, may be formed in respective ones of active regions4101and4102within a source/drain zone445. For example, drain regions of select gates may be formed for one or more strings of memory cells in source/drain zone445. Contacts4401and4402may be coupled to respective ones of the drains in active regions4101and4102of source/drain zone445. Drain-select-gate region425may be between source/drain zone445and string region420, so that the drain select gates may be between contacts440and the strings of memory cells.

For some embodiments, drain select gates within another select gate region, such as a drain-select-gate region450denoted by the indicia SG3, may be respectively formed over active regions410and may be coupled to contacts4401and4402. The drain select gates in drain-select-gate region450over active regions4101and4102may respectively selectively couple strings of memory cells in a string region (not shown) on the other side of source/drain zone445from string region420to contacts4401and4402.

The strings of memory cells of string region420over active regions4101and4102may be coupled to a source line455within a source/drain zone460through the source select gates within source-select-gate region430formed over active regions410. For example, a source region may be formed in source/drain zone460. For some embodiments, source line455may be coupled to source/drains, e.g., sources, of the source select gates within source/drain zone460, where the sources are formed in the active regions410in source/drain zone460.

For some embodiments, source/drain zone460may be between source-select-gate region430and another select gate region, such as a source-select-gate region470, denoted by the indicia SG4. Select gates, such as source select gates, of source-select-gate region470formed over the active regions410may be coupled to strings of memory cells formed over extensions of active regions410(not shown) on the other side of source-select-gate region470in another string area (not shown) on the other side of source-select-gate region470.

FIGS. 5A-5Fshow a cross-section viewed along line A-A inFIG. 4during various stages of fabrication.FIG. 6Ashows a cross-section viewed along lines B-B, C-C, and D-D inFIG. 4during a stage of fabrication.FIGS. 6B-6Fshow a cross-section viewed along lines B-B and C-C inFIG. 4during various stages of fabrication.FIGS. 6G-6Hshow a cross-section viewed along line B-B inFIG. 4during various stages of fabrication.FIGS. 7A-7Gshow a cross-section viewed along line E-E inFIG. 4during various stages of fabrication.FIG. 8shows a cross-section viewed along line C-C during a stage of fabrication.FIGS. 9A-9Cshow a cross-section viewed along line D-D inFIG. 4during various stages of fabrication.FIG. 11shows a cross-section viewed along lines B-B and C-C inFIG. 4during a stage of fabrication.FIG. 12shows a cross-section viewed along line A-A inFIG. 4during a stage of fabrication.

FIGS. 5A,6A, and7A correspond to substantially the same stage of fabrication and depict their respective cross-sections after several processing steps have occurred. Note that the cross-sections viewed along lines B-B, C-C, and D-D inFIG. 4may have the structure depicted inFIG. 6A.

In general, for some embodiments, a dielectric504(e.g., a tunnel dielectric) may be formed over a semiconductor500, as shown inFIGS. 5A and 6A. Semiconductor500may be comprised of silicon, e.g., monocrystalline silicon, that may be conductively doped to have p-type conductivity, e.g., to form a p-well, or n-type conductivity, e.g., to form an n-well. Dielectric504is generally formed of one or more dielectric materials. For example, dielectric504may be formed from an oxide, e.g., silicon oxide, an oxynitride, e.g., silicon oxynitride, etc.

A charge-storage structure508may be formed over dielectric504, as shown inFIGS. 5A and 6A. Charge-storage structure508is generally formed of one or more materials capable of storing a charge. Charge-storage structure508may be a floating gate formed from a conductor. The conductor may comprise, consist of, or consist essentially of conductively doped polysilicon and/or may comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide, or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) are generally recognized as refractory metals.

For other embodiments, charge-storage structure508may be a charge trap. For example, the charge trap may be a dielectric, e.g., a high-dielectric-constant (high-K) dielectric, such as alumina (Al2O3), with embedded conductive particles (e.g., nano-dots), such as embedded metal particles or embedded nano-crystals (e.g., silicon, germanium, or metal crystals), a silicon-rich dielectric, or SiON/Si3N4. Other charge-storage structures are also known.

A dielectric512may be formed over charge-storage structure508, as shown inFIGS. 5A and 6A. Dielectric512may be generally formed of one or more dielectric materials. For some embodiments, dielectric512may comprise, consist of, or consist essentially of one or more dielectrics, such as silicon oxide, nitride, oxynitride, oxide-nitride-oxide (ONO), high dielectric constant (high-K) dielectrics, such as alumina, hafnia (HfO2), zirconia (ZrO2), praeseodymium oxide (Pr2O3), or other dielectrics.

One or more sacrificial materials may be formed over dielectric512. In the example ofFIGS. 5A and 6A, a sacrificial material514, such as an oxide, e.g., silicon dioxide, may be formed over dielectric512. A sacrificial material516, such as polysilicon, nitride, etc., may then be formed over sacrificial material514. In general, sacrificial materials514and516are different materials and may be chosen to protect and/or pattern underlying layers while allowing their subsequent selective removal.

Openings520, such as trenches, may then be formed, as shown inFIG. 6A, by patterning sacrificial material516and removing portions of sacrificial material514, dielectric512, charge-storage structure508, dielectric504, and semiconductor500exposed by the patterned sacrificial material516. For example, for some embodiments, a mask (not shown), e.g., imaging resist, such as photo-resist, may be formed over sacrificial material516and patterned to define regions of sacrificial material516, sacrificial material514, dielectric512, charge-storage structure508, dielectric504, and semiconductor500for removal. The regions defined for removal are subsequently removed, e.g., by etching, to form openings520that may terminate within semiconductor500. For example, openings520may expose a surface525of semiconductor500located within semiconductor500at a level (e.g., vertical level) below an upper surface528of semiconductor500.

Openings520define active regions410, such as active regions4101and4102, therebetween under dielectric504within semiconductor500, as shown inFIG. 6A. That is, active regions410are portions of semiconductor500. Each active region410may form a channel region for a corresponding column of memory cells, e.g., a string of series coupled memory cells, to be formed thereover. In other words, during operation of one or more memory cells of a column of memory cells, such as a string of memory cells, a channel can be formed in the corresponding active region410. The memory cells formed over each active region may include dielectric512(e.g., as an interlayer dielectric), charge-storage structure508, and dielectric504(e.g., as a tunnel dielectric).

A dielectric532may be deposited in openings520, e.g., over exposed surface525, and possibly over sacrificial material516, such as by blanket deposition, to form isolation regions415from dielectric532between the active regions410, as shown inFIG. 6A. Dielectric532may then be removed from sacrificial material516, e.g., by chemical mechanical planarization (CMP), exposing an upper surface of sacrificial material516so that the upper surfaces of isolation regions415are substantially flush (e.g., flush) with the upper surface of sacrificial material516. For example, dielectric532may substantially (e.g., completely) fill openings520.

For some embodiments, the processing steps described above in conjunction withFIGS. 5A and 6Amay form the cross-sections ofFIGS. 5A and 6Aand the cross-section ofFIG. 7A, which illustrates an isolation region415.

For some embodiments, a mask710, e.g., imaging resist, such as photo-resist, may be formed over each isolation region415, as shown inFIG. 7Afor a given isolation region415. Mask710may be patterned to define regions of each isolation region415for removal. For example, the regions defined for removal may correspond to string region420, source/drain zone445, and source/drain zone460, whereas the regions protected by patterned mask710may correspond to drain-select-gate regions425and450, respectively denoted by indicia SG1and SG3, and to source-select-gate regions430and470, respectively denoted by indicia SG2and SG4, as shown inFIG. 7B.

Subsequently, the regions defined for removal are removed, such as by etching (e.g., an etch-back), stopping within the isolation region415, as shown inFIG. 7B. Portions of the isolation region415corresponding to string region420, source/drain zone445, and source/drain zone460are removed, leaving the portions of the isolation region415corresponding to drain-select-gate regions425and450and source-select-gate regions430and470substantially intact. For example, the removal process may form openings720,724, and728within the portions of the isolation region415respectively corresponding to string region420, source/drain zone445, and source/drain zone460, as shown inFIG. 7B. In other words, the removal process may recess the portions of the isolation region415respectively corresponding to string region420, source/drain zone445, and source/drain zone460to form the openings720,724, and728.

FIG. 6Bshows that the removal process may remove portions of the isolation regions between active regions410to form openings720/724, where openings720are in the cross-section viewed along line B-B (in source/drain zone445) inFIG. 4and openings724are in the cross-section viewed along line C-C (in string region420) inFIG. 4. Note that the cross-sections viewed along lines B-B and C-C inFIG. 4may both have the structure depicted inFIG. 6B. For some embodiments, openings720/724may be tapered (e.g., becoming narrower toward their bottoms) so as to leave remaining portions of isolation regions415adjacent to the sidewalls of openings720/724, and thus sidewalls of charge-storage structure508, dielectric504, and at least a portion of dielectric512(FIG. 11).

For some embodiments, openings720/724may pass through sacrificial materials516and514, through dielectric512, through charge-storage structure508, through dielectric504, and extend to a level (e.g., vertical level) below the upper surface528of semiconductor500, and thus of active regions410. This means that the removal process may terminate in each isolation region at a level (e.g., vertical level) below the upper surface528of active regions410. In other words, the portions of each isolation415in source/drain zone445and string region420may be recessed below the upper surface528of active regions410.

A dielectric530may be formed over sacrificial material516inFIGS. 5B and 6C. Note that the cross-sections viewed along line B-B in source/drain zone445inFIG. 4and line C-C in string region420inFIG. 4may have the structure depicted inFIG. 6C. Dielectric530may also be formed over isolation regions415inFIG. 6Cwithin openings720/724, and may thus overfill openings720/724. For example, the dielectric530may be over the upper surfaces of sacrificial material516and within openings720/724over the sides of sacrificial materials516and514, the sides of dielectric512, the sides of charge-storage structure508, and the sides of dielectric504and over the recessed portions of each isolation region415, as shown inFIG. 6C.

For embodiments, where openings720/724may be tapered so as to leave remaining portions of isolation regions415adjacent to the sidewalls of charge-storage structure508, dielectric504, and at least a portion of dielectric512, the remaining portions of the isolation solation regions415may be between dielectric530and sidewalls of charge-storage structure508, dielectric504, and at least a portion of dielectric512. This is shown inFIG. 11, for example.

Dielectric530may also be formed over the isolation region415ofFIG. 7Bafter removing mask710, as shown inFIG. 7C. Dielectric530may be formed in the openings720,724, and728within the portions of the isolation region415respectively corresponding to string region420, source/drain zone445, and source/drain zone460, as shown inFIG. 7C. For example, dielectric530may overfill openings720,724, and728and extend over the upper surfaces of isolation region415that correspond to drain-select-gate regions425and450, respectively denoted by indicia SG1and SG3, and to source-select-gate regions430and470, respectively denoted by indicia SG2and SG4.

Dielectric530may be further formed over the structure ofFIG. 6A, e.g., in drain-select-gate region425, corresponding to the cross-section inFIG. 6Aviewed along line D-D inFIG. 4, as shown inFIG. 9A. For example, dielectric530may be formed over the upper surfaces of isolation regions415and the upper surfaces of portions of sacrificial material516.

Recall that the portion of mask710over drain-select-gate region425inFIGS. 7A and 7Bcauses the structure inFIG. 6A, corresponding to drain-select-gate region425(the cross-section viewed along D-D inFIG. 4), to remain substantially as shown inFIG. 6Aduring the removal of the portions of the isolation region415inFIG. 7Bcorresponding to string region420, source/drain zone445, and source/drain zone460and during the removal inFIG. 6Bof the portions of isolation regions415in string region420(the cross-section viewed along line C-C inFIG. 4) and of the portions of isolation region415in source/drain zone445(the cross-section viewed along line B-B inFIG. 4). As such,FIG. 9Ashows the structure in drain-select-gate region425(the cross-section viewed along line D-D) at a stage of fabrication following the stage of fabrication depicted inFIG. 6Band inFIG. 7B.

Dielectric530is generally formed of one or more dielectric materials. For some embodiments, dielectric530may be formed from a material having a lower removal rate than the isolation regions415for a particular isotropic removal chemistry. For example, the dielectric530may be formed from a material that etches about 10 times (e.g., at least 10 times) slower than isolation regions415, such as about 10 times (e.g., at least 10 times) slower than oxide using a particular etchant selective to oxide. For example, dielectric530may be formed from nitride.

Subsequently, dielectric530and sacrificial material516may be removed, e.g., by etching, to expose sacrificial material514, as shown inFIGS. 5C and 6D. Note that the cross-sections viewed along lines B-B and C-C inFIG. 4may both have the structure depicted inFIG. 6D. For example, the removal process may recess portions of dielectric530over isolation regions415in string region420(the cross-section viewed along line C-C inFIG. 4) and in source/drain zone445(the cross-section viewed along line B-B inFIG. 4) below upper surfaces of adjacent portions of sacrificial material514that are over active regions410, as shown inFIG. 6D.

The removal process may remove dielectric530from over the portions of the isolation region415inFIG. 7D, corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470. In other words, the removal process recesses dielectric530within openings720,724, and728to a vertical level below the upper surfaces of the portions of each isolation region415corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470.

For example, the removal process forms solid dielectric (e.g., nitride) plugs630from the dielectric530over the recessed portion of each isolation region415in source/drain zone445and solid dielectric (e.g., nitride) plugs635from the dielectric530over the recessed portion of each isolation region415in string region420, as shown inFIGS. 6D and 7D, and forms solid dielectric (e.g., nitride) plugs640from the dielectric530over the recessed portion of each isolation region415in source/drain zone460, as shown inFIG. 7D. In other words, a dielectric plug630is formed in opening724, a dielectric plug635is formed in opening720, and dielectric plug640is formed in opening728, as shown inFIG. 7D.

The removal process may also remove dielectric530and the portions of sacrificial material516between isolation regions415in drain-select-gate region425inFIG. 9B, stopping on or within sacrificial material514inFIG. 9B(e.g., in drain-select-gate region425) to expose sacrificial material514. For example, the removal of the portions of sacrificial material516between isolation regions415may form openings910in drain-select-gate region425that terminate at or within sacrificial material514. Sacrificial material514may then be removed, e.g., by etching, stopping on or within dielectric512, thereby exposing dielectric512, as shown inFIGS. 5D,6E, and9C. Note that source/drain zone445and string region420(the cross-sections viewed along lines B-B and C-C inFIG. 4) may both have the structure depicted inFIG. 6E.

Portions of isolation regions415may also be removed, e.g., by etching, as shown inFIGS. 7E, and9C. For example, the portions of isolation regions415may be removed (e.g., recessed) inFIG. 7Eto a level of the upper surfaces of dielectric plugs630,635, and640respectively within openings720,724, and728so that the upper surfaces of dielectric plugs630,635, and640may be substantially flush (e.g., flush) with the upper surfaces of the portions of each isolation region415corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470. As shown in the example ofFIG. 9C, the portions of isolation regions415may be removed (e.g., recessed) to a level of the upper surface of dielectric512so that the upper surface of dielectric512is substantially flush (e.g., flush) with the upper surfaces of the of the isolation regions415in drain-select gate region425.

A conductor550may then be formed over dielectric512, as shown inFIGS. 5D,6F, and9C. Conductor550may also be over isolation regions415inFIG. 9Cand over dielectric plugs630/635inFIG. 6F. Note that source/drain zone445and string region420(the cross-sections viewed along lines B-B and C-C inFIG. 4) may both have the structure depicted inFIG. 6F.

For other embodiments, a dielectric1110may be formed over dielectric512and dielectric plugs630/635, as shown inFIG. 11. Dielectric1110may be generally formed of one or more dielectric materials. For some embodiments, dielectric1110may be an oxide such a silicon dioxide. Alternatively, dielectric1110may be a nitride.

Note that dielectric plugs630/635may be tapered (e.g., becoming narrower toward their respective bottoms), and portions of isolation regions415may be between dielectric plugs630/635and the sidewalls of charge-storage structure508, dielectric504, and at least a portion of dielectric512. Portions of isolation region415may also be between sides of a tapered dielectric plug630/635and the active regions4101and4102. For example, a portion of isolation region415between sides of a dielectric plug630/635and the active regions4101and4102may be tapered, becoming narrower toward its upper surface and the upper surface of the dielectric plug630/635.

A dielectric1115may then be formed over dielectric1110. Dielectric1115may be generally formed of one or more dielectric materials. For some embodiments, dielectric1115may be a high-dielectric-constant (high-K) dielectric, such as alumina, hafnia (HfO2), or zirconia (ZrO2) with a K of about 20, or praeseodymium oxide (Pr2O3) with a K of about 30. Alternatively, dielectric1115may be an oxide.

A conductor1120, such as tantalum, may then be formed over dielectric1115. Conductor550may then be formed over conductor1120. Conductor1120may serve as a transition conductor between dielectric1115, e.g., when dielectric1115is a high-K dielectric, and conductor550.

Conductor550is generally formed of one or more conductive materials. For example, conductor550may comprise, consist of, or consist essentially of conductively doped polysilicon and/or may comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material.

Conductor550(or the stack inFIG. 11including dielectrics1110and1115, conductor1120, and conductor550) may be formed over the portions of each isolation region415corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470and dielectric plugs630,635, and640, as shown inFIG. 7Efor just conductor550. For some embodiments, conductor550may be in direct contact with the upper surfaces of the portions of each isolation region415corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470and the upper surfaces of dielectric plugs630,635, and640.

For other embodiments, dielectric1110may be in direct contact with the upper surfaces of the portions of each isolation region415corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470and the upper surfaces of dielectric plugs630,635, and640. Dielectric1115may then be over dielectric1110. Conductor1120may be over dielectric1115, and conductor550may be over conductor1120. In other words, a stack including conductor1120over dielectric1115over dielectric1110may be between conductor550and dielectric plugs630,635, and640and the portions of isolation region415corresponding to drain-select-gate regions425and450and to source-select-gate regions430and470inFIG. 7E.

Conductor550may then be patterned and portions thereof removed, e.g., etched, to produce one or more individual access lines, such as one or more word lines555, in string region420, drain select lines560in drain-select-gate regions425and450, and source select lines565in source-select-gate regions430and470, as shown inFIGS. 5E,7F and9C.

Memory cells570may be located over active regions410in string region420, as shown inFIGS. 5E,6F, and11. Memory cells570may be located above and substantially vertically aligned (e.g., vertically aligned), on a one-to-one basis, with active regions410, as shown inFIGS. 6F and 11.FIGS. 6F and 11may each depict a row of memory cells570that may be commonly coupled to a single word line555. A memory cell570may include dielectric504(e.g., as a tunnel dielectric), charge-storage structure508over dielectric504, dielectric512(e.g., as an interlayer dielectric) over charge-storage structure508, and a control gate (e.g., as a portion of or coupled to a word line555) over dielectric512, as shown inFIGS. 5E and 6F.

Alternatively, e.g., in the example ofFIG. 11, a memory cell570may include dielectric504(e.g., as a tunnel dielectric), charge-storage structure508over dielectric504, dielectrics512,1110, and1115, e.g., forming a blocking dielectric, such as an interlayer dielectric, over charge-storage structure508, conductor1120over dielectric1115, and conductor550over conductor1120. In the example ofFIG. 11, conductor550may form a word line555, and conductor1120may be referred to as a control gate electrode of memory cells570. For example, the control gate of the memory cell570may be a portion of or may be coupled to word line555.

FIG. 5Edepicts a string of series-coupled memory cells570within string region420, e.g., of a column. This string of series-coupled memory cells570may be between and coupled in series with a drain select gate572at one end of the string, e.g., within drain-select-gate region425, and a source select gate574at an opposite end of the string, e.g., within source-select-gate region430. A drain select gate576may be within drain-select-gate region450, and a source select gate578may be within source-select-gate region470, as shown inFIG. 5E.

FIG. 9Cdepicts a row of drain select gates572within drain-select-gate region425. Drain select gates572may be located above and substantially vertically aligned (e.g., vertically aligned), on a one-to-one basis, with active regions410, as shown inFIG. 9C.

Drain select gates572and576may include dielectric504(e.g., as a gate dielectric) and a control gate (e.g., as a portion of or coupled to a drain select line560). Source select gates574and578may include dielectric504(e.g., as a gate dielectric) and a control gate (e.g., as a portion of or coupled to a source select line565).

Openings581may be formed through conductor550and through dielectric512, charge-storage structure508, and dielectric504within string region420inFIG. 5E, stopping on or within an active region410. In other words, portions of conductor550, dielectric512, charge-storage structure508, and dielectric504within string region420are removed to form openings581, thus defining the memory cells570.

Openings720may be formed through conductor550within source/drain zone445and source/drain zone460inFIG. 7F, stopping on or within dielectric530so as to expose dielectric plug630in source/drain zone445and dielectric plug640in source/drain zone460. That is, portions of conductor550are removed to form openings720. Openings580and720may be contiguous, e.g., contiguous portions of single openings (e.g., trenches) that may respectively span the cross-sections viewed along lines A-A and E-E inFIG. 4. For example, the single openings may at least extend from the cross-section viewed along line E-E inFIG. 4to the cross-section viewed along line A-A inFIG. 4in a direction substantially perpendicular to lines A-A and E-E (e.g., to the column direction) and substantially parallel to lines B-B, C-C, and D-D (e.g., to the row direction).

A portion of conductor550within source/drain zone445may also be removed from dielectric plugs630and dielectric512inFIG. 6G. For example, the conductor550may be removed from the structure inFIG. 6Fcorresponding to source/drain zone445(the cross-section inFIG. 6Gviewed along line B-B inFIG. 4), exposing portions of dielectric plugs630and dielectric512. Alternatively, for other embodiments, dielectrics1110and1115, conductor1120, and conductor550may be removed from the structure inFIG. 11, corresponding to a source/drain zone445, to produce a structure similar to that inFIG. 6G, but with tapered dielectric plugs630. For these embodiments, a portion of an isolation415may be between a given dielectric plug630and the active regions4101and4102on either side of that dielectric plug630and the isolation region415.

For some embodiments, openings580and openings720may be formed through conductor550and the portion of conductor550within source/drain zone445may be removed from dielectric plugs630and dielectric512while portions of conductor550are removed in string region420(FIGS. 5E and 7F) to form word lines555from remaining portions of conductor550in string region420. For example, openings580and openings720may be formed and the portion of conductor550within source/drain zone445may be removed from dielectric plugs630and dielectric512substantially concurrently with (e.g., concurrently with) the formation of word lines555.

For other embodiments (e.g., where a stack including conductor1120over dielectric1115over dielectric1110may be under conductor550), openings580and openings720may be formed through conductor550, conductor1120, and dielectrics1115and1110. The portions of conductor550, conductor1120, and dielectrics1115and1110within source/drain zone445may be removed from dielectric plugs630and dielectric512while portions of conductor550, conductor1120, and dielectrics1115and1110are removed in string region420to form word lines555from remaining portions of conductor550in string region420. For example, openings580and openings720may be formed and the portions of conductor550, conductor1120, and dielectrics1115and1110within source/drain zone445may be removed from dielectric plugs630and dielectric512substantially concurrently with (e.g., concurrently with) the formation of word lines555.

Dielectric512, charge-storage structure508, and dielectric504may also be removed from active regions410inFIG. 6G, exposing active regions410, so that portions of dielectric plugs630extend above upper surfaces of active regions410. For example, dielectric512, charge-storage structure508, and dielectric504may be removed from the structure inFIG. 6Fin source/drain zone445(the cross-section viewed along line B-B inFIG. 4), as shown inFIG. 6G.

However, the structure inFIG. 6Fcorresponding to the cross-section in string region420viewed along line C-C inFIG. 4is protected and remains substantially as shown inFIG. 6F. Recall that the cross-sections viewed along lines B-B (source/drain zone445) and C-C (string region420) inFIG. 4may have the structure depicted inFIG. 6F.FIG. 8is a cross-section viewed along line C-C inFIG. 4at a stage of fabrication following that depicted inFIG. 6Ffor the cross-section viewed along line C-C inFIG. 4, whereasFIG. 6Gis a cross-section viewed along line B-B inFIG. 4at a stage of fabrication following that depicted inFIG. 6Ffor the cross-section viewed along line B-B inFIG. 4.

A dielectric582may be formed over conductor550, e.g., over word lines555, drain select lines560, and source select lines565, within openings580inFIG. 5Fand over conductor550, and within openings720inFIG. 7G. Dielectric582may line openings580. For example, dielectric582may be over the sides of conductor550, dielectric512, charge-storage structure508, and dielectric504and may be over active region410at the bottom of openings580, as shown inFIG. 5F. Dielectric582may line openings720. For example, dielectric582may be over the sides of conductor550and may be over dielectric plugs630and640at the bottom of openings720, as shown inFIG. 7G. Dielectric582may be over the sides of word lines555and over dielectric plug635between word lines555inFIG. 7G.

Dielectric582may be formed over active regions410and over dielectric plugs630inFIG. 6H. Dielectric582may be formed over conductor550, and thus word lines555, inFIG. 8and over conductor550, and thus drain select line560, inFIG. 9C.

For some embodiments, the dielectric plugs635inFIG. 8may be tapered as shown inFIG. 11with a portion of isolation region415between a tapered dielectric plug635and active regions4101and4102, dielectric504, charge-storage structure508, and at least a portion of dielectric512. In addition, the stack inFIG. 11, including dielectrics1110and1115and conductor1120, may be between the dielectric plugs635, and thus dielectrics512, and the conductor550, and thus the word line555, inFIG. 8. A portion of isolation region415may be between sides of a dielectric plug630and the active regions4101and4102, e.g., a manner similar to that shown below the upper surfaces active regions4101and4102inFIG. 11.

Dielectric582is generally formed of one or more dielectric materials. For example, dielectric582may be formed from an oxide.

For some embodiments, dielectric582may have a low conformability, e.g., dielectric582may be a plasma enhanced TEOS (tetraethylorthosilicate) or silane oxide. Dielectric582may pinch off adjacent to a top of each of openings581before openings581can be completely filled with dielectric582. Dielectric582may thus close openings581adjacent to the tops thereof. However, dielectric582may extend into openings581, e.g., partially into openings581, before pinching off. Openings581may have a relatively high aspect (height-to-width) ratio that acts to promote pinching off of dielectric582.

The pinched-off openings581may form air-containing gaps, such as air gaps583, between the memory cells570in string region420, as shown inFIG. 5F. Note that the memory cells570inFIG. 12may form a string (e.g., a NAND string) of series-coupled, memory cells between drain select gate572and source select gate574.

It will be understood that the air gaps as defined herein may contain one or more gaseous components other than, or in addition to, ambient air. For example, an air gap as defined herein may contain oxygen, nitrogen, argon, neon or other gas compatible (e.g., inert) with the surrounding structures, or a gas containing a mixture of one or more such gaseous components. For one or more embodiments, the gas contained in an air gap of the present disclosure may further be below atmospheric pressure.

A dielectric584may be formed over dielectric582inFIGS. 5F,6H,7G,8and9C. Dielectric584is generally formed of one or more dielectric materials. For example, dielectric584may be formed from a nitride.

A dielectric586may be formed over dielectric584inFIGS. 5F,6H,7G,8, and9C. Dielectric586is generally formed of one or more dielectric materials, and one example for dielectric586would be a doped silicate glass. Examples of doped silicate glasses include BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass). Another example for dielectric586would be TEOS (tetraethylorthosilicate).

Openings588and590may be formed in dielectric586respectively in source/drain zone460and source/drain zone445, passing through dielectrics584and582and stopping on or within active regions410, as shown inFIGS. 5F and 6H. For some embodiments, a protective liner, such as a dielectric liner592, may be formed over the sides of openings588and590and the bottom of openings588and590. For example, dielectric liner592may be formed over dielectric586on the sides of openings588and590and over active region410at the bottom of openings588and590. The portion of dielectric liner592at the bottom of openings588and590may be subsequently removed to re-expose active region410.

Dielectric liner592is generally formed of one or more dielectric materials. For some embodiments, dielectric liner592may be formed from a material that etches about 10 times (e.g., at least 10 times) slower than isolation regions415, such about 10 times (e.g., at least 10 times) slower than oxide. For example, dielectric liner592may be formed from a nitride.

An opening788may be formed in dielectric586in source/drain zone460, passing through dielectrics584and582and stopping on or within dielectric plug640, as shown inFIG. 7G. For some embodiments, a protective liner, such as a dielectric liner792, may be formed over the sides of opening788and the bottom of opening788. For example, dielectric liner792may be formed over dielectric586on the sides of opening788and over dielectric plug640at the bottom of opening788. The portion of dielectric liner792at the bottom of opening788may be subsequently removed to re-expose dielectric plug640.

Dielectric liner792is generally formed of one or more dielectric materials. For some embodiments, dielectric liner792may be formed from a material that etches about 10 times (e.g., at least 10 times) slower than isolation regions415, such as about 10 times (e.g., at least 10 times) slower than oxide. For example, dielectric liner792may be formed from a nitride.

For some embodiments, openings588and788may be contiguous, e.g., contiguous portions of a single opening (e.g., trench) that may span the cross-sections viewed along lines A-A and E-E inFIG. 4. For example, the single opening may at least extend from the cross-section viewed along line E-E inFIG. 4to the cross-section viewed along line A-A inFIG. 4in a direction substantially perpendicular to lines A-A and E-E (e.g., to the column direction) and substantially parallel to lines B-B, C-C, and D-D (e.g., to the row direction). For some embodiments, each opening590may be a discrete opening, such as a discrete hole.

A conductor594may be formed, e.g., deposited, in openings590, e.g., over dielectric liner592and over (e.g., in direct physical contact with) active regions4101, to form contacts4401that electrically contact (e.g., by direct physical contact with) a respective active region4101, as shown inFIGS. 5F and 6H. Conductor594may be also formed, e.g., deposited, in opening588, e.g., over dielectric liner592and over (e.g., in direct physical contact with) active regions4101, as shown inFIG. 5F, and active regions4102(not shown).

Conductor594may be also formed, e.g., deposited, in opening788, e.g., over dielectric liner792and over (e.g., in direct physical contact with) dielectric plug640, as shown inFIG. 7G. For example, the conductor594may be deposited within the trench formed by contiguous openings588and788to form source line455that electrically contacts (e.g., by direct physical contact with) active regions410, as shown inFIG. 5Ffor a region4101. Note that source line455may also contact dielectric plug640, as shown inFIG. 7G.

For some embodiments, source line455may span the cross-sections viewed along lines A-A and E-E inFIG. 4. For example, source line455may at least extend from the cross-section viewed along line E-E inFIG. 4to the cross-section viewed along line A-A inFIG. 4in a direction substantially perpendicular to lines A-A and E-E (e.g., to the column direction) and substantially parallel to lines B-B, C-C, and D-D (e.g., to the row direction).

Conductor594may be blanket deposited to fill openings588,590, and788and may possibly extend over dielectric586. Conductor594may then be removed from dielectric586, e.g., by CMP, exposing an upper surface of dielectric586so that the upper surfaces of contacts4401and the upper surface of source line455may be substantially flush (e.g., flush) with the upper surface of dielectric586, as shown inFIGS. 5F,6H, and7G. Note that contacts4402(FIG. 4) may be formed in electrical contact (e.g., by direct physical contact with) active regions4102in a plane parallel to the face plane ofFIG. 6Hin a similar (e.g., the same) manner, e.g., from conductor594.

Conductor594may be generally formed of one or more conductive materials. For example, conductor594may comprise, consist of, or consist essentially of a metal or metal-containing layer and may be aluminum, copper, a refractory metal, or a refractory metal silicide layer. In some embodiments, conductor594may contain multiple metal-containing layers, e.g., a titanium nitride (TiN) barrier layer formed over (e.g., in direct physical contact with) an active region410and dielectric plug640(FIG. 7G), a titanium (Ti) adhesion layer formed over the barrier layer, and a tungsten (W) layer formed over the adhesion layer.

For some embodiments a stack including dielectrics1110and1115and conductor1120, as discussed in conjunction withFIG. 11, may be formed over dielectric512inFIG. 5D. Subsequently conductor550may be formed over conductor1120.

FIG. 12illustrates a cross-section taken along line A-A inFIG. 4, according to other embodiments, and corresponds to a stage of fabrication following the stage of fabrication depicted inFIG. 5D. For some embodiments, a protective material1210, e.g., a dielectric, such as nitride, carbon, etc., may be formed over conductor550, e.g., for protecting conductor550, conductor1120, dielectrics1115,1110, and512, charge-storage structure508, and dielectric504during the subsequent processing.

Portions of protective material1210, conductor550, conductor1120, dielectrics1115,1110, and512, charge-storage structure508, and dielectric504are then removed, as shown inFIG. 12, stopping at a level (e.g., a vertical level), corresponding to above, below, or at the upper surface of an active region, such as an active region4101, to form openings1215,1217, and1220through protective material1210, conductor550, conductor1120, dielectrics1115,1110, and512, charge-storage structure508, and dielectric504, terminating at the level corresponding to above, below, or at the upper surface of active region4101.

A dielectric1225, e.g., having a low conformability, such as plasma enhanced TEOS (tetraethylorthosilicate) or silane oxide, is then formed in openings1215and1220. Dielectric1225may pinch off adjacent to a top of each of openings1217before openings1217can be completely filled with dielectric1225. Dielectric1225may thus close openings1217adjacent to the tops thereof. However, dielectric1225may extend into openings1217, e.g., partially into openings1217, before pinching off. Openings1217may have a relatively high aspect (height-to-width) ratio that acts to promote pinching off of dielectric1225.

The pinched-off openings1217may form air-containing gaps, such as air gaps1230, that define memory cells570in string region420, as shown inFIG. 12. Note that the memory cells570inFIG. 12may form a string (e.g., a NAND string) of series-coupled, memory cells between drain select gate572and source select gate574, where the air gaps1230are between the memory cells570in each string.

Openings1215and1220may have a lower aspect ratio than openings1217so that dielectric1225does not pinch off, but instead forms on the sides of openings1215and1220, thus leaving openings1215and1220open at the top. Dielectric1225forms spacers1227on the sidewalls of drain select gate576and source select gate578and at least one of the sidewalls of drain select gate572and source select gate574, as shown inFIG. 12. Note that drain select gates572and576and source select gates574and578may include dielectrics1110and1115and conductor1120between dielectric512and conductor550in the example ofFIG. 12.

A dielectric1230, such as nitride, (e.g., that may be referred to as a barrier) may then be formed over dielectric1225. For example, dielectric1230may be formed over the spacers1227and over active region4101at the bottom of openings1215and1220adjacent to spacers1227. A dielectric1250, such as a conformal oxide, may then be formed over dielectric1230.

Openings1255and1257may then be formed through dielectric1250, stopping at or within active region4101and thus exposing active region4101. Source line455may then be formed in opening1255, e.g., as described above in conjunction withFIG. 5F, and a contact4401may be formed in opening1257, e.g., as described above in conjunction withFIG. 5F.

Prior to forming contacts440and source line455, a clean operation (e.g., a clean-up etch, such as an isotropic etch) may be performed, e.g., using a wet etch, to remove native oxide that may form on the exposed surfaces of active regions410for improving electrical contact between contacts440and active regions410and between source line455and active regions410. For example, the wet etchant may be applied to the exposed surfaces of active regions410through openings588,590, and788ofFIG. 5For openings1255and1257ofFIG. 12. The chemistry of the clean-up etchant may be the particular isotropic removal chemistry.

Source/drains, e.g., drains598, may be formed in active regions410within source/drain zone445, e.g., in portions of the active regions410shown inFIG. 6H, so that contacts440electrically contact the source/drains. These source/drains are coupled one-to-one to the drain select gates572that are shown inFIG. 9Cand one-to-one to contacts440.

For some embodiments, in source/source/drain zone445, dielectric plug630and an isolation region415may be between active regions4101and4102, where the dielectric plug630extends below upper surfaces of active regions4101and4102, as shown inFIGS. 6H and 10. For example, as shownFIG. 6H, isolation regions415are recessed below the upper surfaces of active regions410for some embodiments, so that their upper surfaces are below the upper surfaces of active regions410. A dielectric plug630is over each isolation region415and may extend from the upper surface of a respective isolation region415to above the upper surfaces of active regions410.

For some embodiments, each dielectric plug630may cover substantially an entire (e.g., the entire) upper surface of an underlying portion of a respective isolation region415, as shown inFIGS. 6H and 7G. For example, each dielectric plug630may substantially fill (e.g., fill) an entire region over a respective isolation region415, e.g., where the region over the respective isolation region415may extends from the upper surface of the respective isolation region415to a level above the upper surfaces of adjacent active regions4101and4102. For other embodiments, each dielectric plug630may directly contact the upper surface of a respective underlying isolation region415and/or may directly contact a side of an adjacent active region4101and a side of an adjacent active region4102. For still other embodiments, dielectric plugs630may be tapered and a portion of an isolation region415may be between a tapered dielectric plug and a side of an adjacent active region4101and a side of an adjacent active region4102(seeFIG. 10, for example).

FIG. 10shows a portion of source/source/drain zone445, i.e., a portion of the cross-section ofFIG. 6H, where a contact4401is misaligned as a result of an opening590being misaligned. The misalignment causes the opening590and contact4401to overlap an active region4101and an adjacent isolation region415. However, the portion of opening590that overlaps isolation region415extends into dielectric plug630so that opening590exposes a portion of that dielectric plug630.

In contrast, in the prior art ofFIG. 3, the misaligned opening3452exposes isolation region3352, where isolation region3352and isolation region415may have about the same etch rate as oxide, for example. Note that the dielectric plugs630inFIG. 10replace the upper portion of isolation regions3351and3352inFIG. 3, so that a dielectric plug630is exposed instead of the upper portion of isolation region3352.

During the clean operation that removes the native oxide that may form on the active regions, the exposed isolation region3352in the prior art can be etched by etchant (e.g., wet etchant) that is introduced through misaligned opening3452. That is, the isolation region3351and dielectric348inFIG. 3may etch at about the same rate as the native oxide when exposed to the etchant that removes the native oxide. This can cause an adjacent active region, e.g., active region3302inFIG. 3, to be exposed by misaligned opening3452, as discussed above in conjunction withFIG. 3.

The region3602may extend from misaligned opening3452to active region3302inFIG. 3. Region3602may be filled with a conductor, e.g., conductor365inFIG. 3, during the formation of contact3282inFIG. 3, causing an electrical short between contact3282and active region active region3302. The portion340of contact3282that forms in region3602may be in contact with active region3302, causing the short.

However, the presence of the dielectric plugs630over the isolation regions415in the disclosed embodiments, as shown inFIG. 6Hand inFIG. 10, so that a misaligned opening590exposes a dielectric plug630instead of an isolation region415, may act to substantially eliminate (e.g., acts to eliminate) a short that may occur between a contact and an active region due to the misalignment of the opening and thus the contact. This is because the etch that removes the native oxide on the active region4101that is exposed the misaligned opening590is substantially unselective to the dielectric530, and thus dielectric plugs630, that is also exposed by the misaligned opening590. For example, dielectric plugs630have a lower etch rate, e.g., about 10 times less (e.g., at least 10 times less) than the etch rate of the oxide. For embodiments, where dielectric plugs630are nitride, the etch that removes the native oxide may be substantially selective to oxide and not to nitride.

When the clean operation is performed, e.g., by introducing an etchant, such as a wet etchant having the particular isotropic removal chemistry, through the misaligned opening590, for removing native oxide from active region4101, the dielectric plug630overlapped by the misaligned opening590may remain substantially intact, e.g., the dielectric plug630remains substantially unetched, as shown inFIG. 10. This prevents the etchant from reaching active region4102on the other side of the dielectric plug630overlapped by the misaligned opening590. That is, the presence of the dielectric plug630acts to substantially prevent the formation of the region340inFIG. 3that would otherwise form in the prior art.

Note that the source/drain zone445inFIGS. 6H and 10may include active regions4101and4102, each having a source/drain598formed therein. A contact4401may be electrically coupled to the source/drain598in each active region4101, and a contact4402may be electrically coupled to the source/drain598in each active region4102. An isolation region415may be formed between successively adjacent active regions4101and4102, where an upper surface of each isolation region415may be below the upper surfaces of active regions4101and4102. A dielectric plug630may be substantially vertically aligned (e.g., vertically aligned) with and over each active region4101and4102, extending substantially vertically (e.g., vertically) from the upper surface of each isolation region415so that an upper surface of each dielectric plug630is above the upper surfaces of active regions4101and4102.

FIG. 8shows a row of memory cells570in string region420, where each memory cell is over an active region410of semiconductor500. A dielectric plug635is between adjacent memory cells570. An isolation region415within semiconductor500is under each dielectric plug635so that the each isolation region415is substantially vertically aligned (vertically aligned) with a respective dielectric plug635.

For some embodiments, a dielectric plug635may cover substantially an entire (e.g., the entire) upper surface of an underlying isolation region415. For example, each dielectric plug635may substantially fill (e.g., fill) an entire region over a respective isolation region415, e.g., where the region over the respective isolation region415extends from the upper surface of the respective isolation region415to a level of the upper surfaces of dielectric512, e.g., to a bottom surface of conductor550, and thus word line555. For other embodiments, each dielectric plug635may directly contact the upper surface of a respective underlying isolation region415, the bottom surface of word line555, a side of an adjacent active region4101, and a side of an adjacent active region4102.

The upper surfaces of dielectric plugs635plugs may be substantially flush with (e.g., flush with) the upper surfaces of dielectric512of memory cells570, as shown inFIG. 8. Isolation regions415may be recessed below the upper surfaces active regions410in string region420.

For other embodiments, dielectric plugs635may be tapered and a portion of an isolation region615may be between a tapered dielectric plug635and a side of an adjacent active region4101and a side of an adjacent active region4102, as shown inFIGS. 10 and 11. The isolation region615may also be between the tapered dielectric plug635and sides of dielectric504, charge-storage structure508, and at least a portion of a side of dielectric512, as shown inFIG. 11.

FIGS. 5F,7G,9C, and12show that drain-select-gate region425is substantially devoid (e.g. devoid) of any underlying dielectric530, meaning that there is substantially no (e.g., no) dielectric530under drain select gates572. This is the result of the masking inFIG. 7B.FIG. 7Galso shows that drain-select-gate region450, and thus drain select gate576(FIG. 5F), and source-select-gate regions430and470, and thus source select gates574and578(FIG. 5F) are substantially devoid (e.g. devoid) of any underlying dielectric530. This is the result of the masking inFIG. 7B.

In the region between adjacent active regions4101and4102, portions of an isolation region415underlie (e.g., are in direct contact with) drain select lines560in drain-select-gate regions425and450and source select lines565in source-select-gate regions430and470, as shown inFIGS. 7G and 9C. This is the result of the masking inFIG. 7B. For example, an isolation region415between adjacent active regions4101and4102, and thus between adjacent drain select gates572, in drain-select-gate region425may extend to a level of the upper surfaces of dielectric512and thus to a bottom surface of a drain select line560, as shown inFIGS. 7G and 9C.

An upper surface of an isolation region415in source/drain zone445may be recessed below upper surfaces of the active regions410in source/drain zone445, as shown inFIG. 6H. However, for other embodiments, the upper surface of an isolation region415in source/drain zone445may be substantially flush (e.g., flush) with the upper surfaces of the active regions410in source/drain zone445, as shown inFIG. 10.

For some embodiments, the upper surface of the dielectric plug630in source/drain zone445may be at substantially the same level (e.g., the same level) as the upper surfaces of the isolation region415respectively in drain-select-gate regions425and450, e.g., the upper surface of the dielectric plug630may be substantially flush with (e.g., flush with) the upper surfaces of the isolation region415respectively in drain-select-gate regions425and450, as shown inFIG. 7G.

The upper surface of an isolation region415in string region420may be recessed below the upper surfaces of that isolation region in drain-select-gate regions425and450, as shown inFIG. 7G. The upper surface of a dielectric plug635formed over the recessed upper surface of the isolation region415in string region420may be at substantially the same level (e.g., the same level) as the upper surfaces of the isolation region415in drain-select-gate regions425and450, as shown inFIG. 7G. For example, the upper surface of the dielectric plug635may be substantially flush with (e.g., flush with) the upper surfaces of region415in drain-select-gate regions425and450.

In string region420, dielectric530, and thus dielectric plug635, may be between isolation region415and word lines555, e.g., dielectric plug635may be in direct contact with word lines555, as shown inFIG. 7G. Dielectric plug630may be over isolation region415in source/drain zone445and dielectric plug640may be over isolation region415in source/drain zone460, as shown inFIG. 7G. Note that the portion of the isolation region415in drain-select-gate region425that extends drain select line560is between dielectric plug630and dielectric plug635.

The use of the term “substantially” herein accounts for routine process variations. For example, industrial processes, and thus structures produced thereby, are not exact, and minor variations may occur. For example the term “substantially fills” may account for a region not being exactly, e.g., completely filled, e.g., due to voids may be present in a material disposed in a trench so that the trench is not exactly full. For example, the term “substantially flush” may refer to surfaces that are flush to within routine variations of the processes that create the surfaces. For example, when elements are at substantially the same level they are at the same level to within routine variations of the processes that create the elements.

CONCLUSION