Microprocessor with duplicate registers for processing interrupts

A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, a data bus, a register bus and an address bus. Data signals are routed between the various blocks of the microprocessor by selectively interconnecting the three buses in response to control signals provided by ALU and control programmable logic arrays (PLA). The ALU and control PLA's decode program instructions loaded in instruction register (IR) to provide the appropriate control signals for executing each instruction. The microprocessor also includes three general purpose registers, an arithmetic logic unit (ALU) with two temporary registers and zero and carry flags, serial data bus circuitry including a format generator and two data registers, direct I/O data direction and data registers, a stack pointer counter, a twelve-bit program counter register, a temporary program counter register and associated incrementer, and a temporary address register. Because of the unique architecture of the microprocessor, all instructions can be executed in four or less clock cycles. Moreover, the program counter register, general purpose registers and zero and carry flags are duplicated, and, during interrupts, the microprocessor switches over to the duplicate program counter register, duplicate general purpose registers and duplicate zero and carry flags. As a result, interrupts are processed quickly and efficienty merely by switching back and forth between the program counter register, general purpose registers and zero and carry flags and their duplicates. Since instruction execution time is minimized, the microprocessor can be operated at slower speeds to conserve power drain, while maintaining the through-put necessary for accommodating high-speed, cellular type supervisory signalling. Thus, a microprocessor embodying the present invention can be advantageously utilized in any application where both low power consumption and fast data manipulation are required.

RELATED PATENT APPLICATIONS 
The instant application is related to the following patent applications 
filed the same date as and assigned to the same assignee as the instant 
application: Ser. No. 182,306 now U.S. Pat. No. 4,390,963, by Larry C. 
Puhl et al., entitled "Interface Adapter Architecture" Ser. No. 187,304, 
by Larry C. Puhl et al., entitled "Micrprocessor Controlled Radiotelephone 
Transceiver"; Ser. No. 187,305, by Larry C. Puhl et al., entitled 
"Keyboard and Display Interface Adapter Architecture"; and Ser. No. 
187,303, now U.S. Pat. No. 4,369,516, by John P. Byrns, entitled 
"Self-Clocking Data Transmission System and Method Therefor". The instant 
application is also related to U.S. Pat. No. 4,312,074 by Kenneth A. Felix 
and James A. Pautler, entitled "Improved Method and Apparatus for 
Detecting a Data Signal Including Repeated Data Words", and U.S. Pat. No. 
4,302,845 by John P. Byrns and Michael J. McClaughry, entitled 
"Phase-Encoded Data Signal Demodulator", both of which were filed on Feb. 
7, 1980, and are assigned to the instant assignee. By reference thereto, 
the foregoing related patent applications are incorporated in their 
entirety into the instant application. 
BACKGROUND OF THE INVENTION 
The present invention relates generally to microprocessors, and more 
particularly to an architecture of a microprocessor that is particularly 
well adapted for controlling cellular radiotelephone transceivers. 
As radiotelephone systems increase in size and complexity to accommodate 
greater numbers of mobile and portable radiotelephones operating in 
geographic areas including several large cities or even several states, it 
is necessary that the control circuitry of these radiotelephones becomes 
increasingly sophisticated. For example, in cellular radiotelephone 
systems, mobile and portable radiotelephones must be capable of 
transmitting and receiving high speed, supervisory signals on dedicated 
signalling radio channels and also on voice radio channels during 
conversations. Prior radiotelephone control circuitry, such as that 
described in U.S. Pat. Nos. 3,458,664 and 3,571,519, does not have the 
capacity for processing these high speed, supervisory signals required to 
be received and transmitted during normal operation in such cellular 
radiotelephone systems. Conventional microprocessors have been integrated 
into some prior radiotelephones, such as the radiotelephone in U.S. Pat. 
No. 4,122,304, for providing additional telephone type features, such as 
automatic telephone number dialing, to radiotelephone subscribers in the 
present day improved mobile telephone system (IMTS) provided and operated 
by many telephone companies. However, conventional microprocessors lack 
the capacity to accommodate the high speed, supervisory signalling 
encountered in cellular radiotelephone systems, while at the same time 
monitoring and controlling other portions of the radiotelephone, such as 
the transmitting and receiving circuitry, a keyboard, and a telephone 
number display. Moreover, conventional microprocessors having high speed 
processing capability consume excessive amounts of power, rendering them 
impractical for use in battery operated mobile and portable 
radiotelephones. 
SUMMARY OF THE INVENTION 
Accordingly, it is an object of the present invention to provide an 
improved microprocessor that provides both high speed processing 
capability and relatively low power consumption. 
It is another object of the present invention to provide an improved 
microprocessor having a self-clocking serial data bus for accommodating a 
number of peripheral devices. 
It is yet another object of the present invention to provide an improved 
microprocessor utilizing duplicate registers to enhance the processing of 
interrupts. 
According to the present invention, an improved microprocessor includes a 
data bus having a plurality of data bus lines, an instruction register 
coupled to the data bus lines, a programmable logic array for decoding the 
instruction register signals to provide a plurality of control signals, a 
register bus having a plurality of register bus lines, an address bus 
having a plurality of address bus lines, a program counter register 
switchably coupled to the address bus lines and including a duplicate 
program counter register switchably coupled to the address bus lines in 
place of the program counter register during interrupts, a temporary 
program counter register switchably coupled to the address bus lines and 
register bus lines and including incrementing circuitry for incrementing 
the temporary program counter register signals by one in response to the 
programmable logic array control signals, a plurality of general purpose 
registers switchably coupled to the register bus lines and including 
duplicate general purpose registers switchably coupled to the register bus 
lines in place of the general purpose registers during interrupts, and 
arithmetic logic circuitry having a first input register coupled to the 
data bus lines and a second input register coupled to the register bus 
lines and combining the first and second register signals according to 
predetermined combinatorial functions selected by programmable logic array 
control signals. The arithmetic logic circuitry performs both arithmetic 
and logical functions, such as, for example, binary addition and binary 
ANDing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to FIG. 1, there is illustrated a block diagram of a 
radiotelephone 100 suitable for use in cellular radiotelephone systems of 
the type described in U.S. Pat. No. 3,906,166 and in a developmental 
cellular system application, filed by Motorola and American 
Radio-Telephone Service, Inc. under Docket No. 18262 with the Federal 
Communications Commission in February, 1977. The radiotelephone 100 
provides the same type of fully automatic telephone service to a mobile or 
portable operator that is provided to land line subscribers. 
Radiotelephone service is provided over a wide geographical area by 
dividing the area into a number of cells. Each cell typically has a base 
station which provides a supervisory signalling radio channel and a number 
of voice channels. Calls are placed to, and originated by, radiotelephones 
over the supervisory signalling channel in each of the cells. Upon 
completion of the supervisory signalling, the radiotelephone is assigned a 
voice channel and switches from the signalling channel to the voice 
channel for the duration of the cell. In the event that a radiotelephone 
leaves a cell and enters another cell, the radiotelephone is automatically 
switched over to an available voice channel in the new cell. The 
supervisory signals carried on the signalling channel, and on voice 
channels for handing off a radiotelephone as it changes cells, are 
provided by digital signals encoded in a suitable format, such as 
Manchester Coding, and transmitted at a relatively high speed, such as 10 
kHz. The format and transmission of the digital signals is described in 
more detail in the aforementioned co-pending applications Ser. Nos. 
119,605 and 119,350, now U.S. Pat. Nos. 4,312,074 and 4,302,845. 
In order to accommodate the high speed supervisory signalling in such 
cellular radiotelephone systems, the radiotelephone 100 includes a 
microprocessor 101 together with peripheral devices 103-112, a synthesized 
radio unit 120, serial number and telephone number memories 130 and 131, a 
telephone number display 140, a keyboard 150 and status indicating LED's 
160. Microprocessor 101, embodying the present invention, is responsive to 
a control program stored in a read-only memory (ROM) 103 for receiving 
data signals from the radio unit 120 by way of synchronization unit 106 
(described in detail in co-pending application Ser. No. 119,350, now U.S. 
Pat. No. 4,302,845) and data interface unit 105 for storage in random 
access memory (RAM) 104, and transmitting to radio unit 120 supervisory 
data signals stored in RAM 104 by way of data interface unit 105. 
Microprocessor 101 is also coupled to radio unit 120 directly by four 
control signals 114, one for powering up the radio unit, two for 
controlling the frequency synthesizer and one for sensing audio signals 
applied to microphone 122, and also by way of serial data bus 113 and 
interface adapters 107-109 (described in further detail in co-pending 
application Ser. No. 187,306, now U.S. Pat. No. 4,390,963. Microprocessor 
101 is coupled to interface adapters 107-109 by serial data bus 113, which 
includes two forward data signal lines and a reverse data signal line 
(described in further detail in co-pending application Ser. No. 187,303, 
now U.S. Pat. No. 4,369,516. Data signals applied to the forward data 
signal lines are received by interface adapters 107-109 and applied to 
radio unit 120. Interface adapter 107 provides audio control signals to 
the receiver of radio unit 120 for selecting one of two received audio 
signals if the radio unit includes two antennas 121 for space diversity 
purposes, controlling the volume of the received audio signal, and muting 
the received audio signal to provide a conventional squelch type function. 
Interface adapter 108 provides audio control signals to the transmitter of 
radio unit 120 for controlling the RF power of the transmitted signal, 
muting the transmitted audio signal and powering up the transmitting 
circuitry. Interface adapter 109 applies an eight-bit frequency control 
signal to the frequency synthesizer of radio unit 120 for determining the 
transmitting and receiving frequencies thereof. The frequency control 
signal applied to the frequency synthesizer can be expanded to up to 
fourteen bits by utilizing two direct control signals 114 from the 
microprocessor 101 to select between seven high order bits and seven low 
order bits. Radio unit 120 can be any conventional radio unit suitable for 
cellular system operation, such as the radio described in Motorola 
Instruction Manual 68P81039E25, published by Motorola Service 
Publications, Schaumburg, Ill., 1979. The radiotelephone described in the 
aforementioned instruction manual is a frequency synthesized radio 
specially adapted for cellular radio telephone systems. 
Microprocessor 101 is also coupled by way of the serial data bus 113 to 
interface adapters 110 and 111 for accessing a serial number and telephone 
number assigned to the radiotelephone 100. The serial number and telephone 
number of the radiotelephone 100 are stored in separate memories 130 and 
131, respectively, so that each may be changed simply by replacing one 
memory with another. The serial number and telephone number may include a 
plurality of digits which are each stored in successive locations of these 
memories. In order to access each digit of the serial number or telephone 
number, the microprocessor 101 transmits an address data signal by way of 
the serial data bus 113 to interface adapter 110. The address signal 
received by interface adapter 110 is applied to the serial number memory 
130 and telephone number memory 131. The address signal includes one bit 
for selecting between the serial number memory 130 and telephone number 
memory 131 and five bits for selecting the particular digit of the serial 
number or telephone number. The digit of the serial number or telephone 
number need out from the addressed serial number memory 130 or telephone 
number memory 131 is applied to interface adapter 111 which occupies the 
readout digit to the serial data bus 113 for transmission back to the 
microprocessor 101. 
Microprocessor 101 is also coupled by way of the serial data bus 113 to a 
keyboard and display interface adapter 112 (described in further detail in 
co-pending application Ser. No. 187,305). The keyboard and display 
interface adapter 112 provides for the display of eight digits of an 
entered telephone number in display 140, scans the keyboard 150 for 
activated keys and activates status indicating LED's 160, one indicating 
that the radiotelephone is in the roam mode, another that the 
radiotelephone is in use, another that no service is available to the 
radiotelephone and the last that the radiotelephone is locked preventing 
unauthorized use. The keyboard and display interface adapter 112 scans the 
keys of the keyboard 150, monitors off-hook switch 170 and applies a data 
signal to the serial data bus 113 indicating which keys are found to be 
activated and whether the off-hook switch 170 is activated or not. The 
keyboard and display interface adapter 112 also receives data signals 
transmitted by the microprocessor 101 on the serial data bus 113 for 
display in the telephone number display 140 or for activating one of the 
four status LED's 160. 
The radio unit 120 of the radiotelephone 100 may be either a mobile unit as 
described in the aforementioned Motorola Instruction Manual 68P81039E25 or 
a hand-held portable unit of the type described in U.S. Pat. Nos. 
3,906,166 and 3,962,553, and illustrated in U.S. Pat. No. D234,605. The 
microprocessor 101 and associated peripheral devices 103-112 are of the 
type that may readily be integrated into a semiconductive substrate, such 
as CMOS, and provided individually or together on an integrated circuit. 
The microprocessor 101 and related peripheral devices 103-112 have been 
architectured such that the high priority supervisory signals received and 
transmitted by radio unit 120 are handled on a high speed interrupt basis 
by data interface unit 105 and synchronization unit 106, while the lower 
priority control signals for the radio unit 120, display unit 140, 
keyboard 150 and status LED's 160 are handled on a lower speed basis by 
way of the serial data bus 113 interface adapters 107-112. Since the 
serial data bus 113 is self-clocking and independent of the speed of 
transmission, interface adapters 107-112 can be physically located remote 
from microprocessor 101 without any degradation in performance. Thus, 
interface adapters 107-109 may be located in the radio unit, if desired, 
and the keyboard and display interface adapter 112 may be located on the 
same printed circuit board as the telephone number display 140 and 
keyboard 150, both being physically separated from the printed circuit 
board on which microprocessor 101 is located. Further details as to the 
exact description and construction of the transmitting and receiving 
circuitry in a typical radio unit 120 can be found in the aforementioned 
Motorola Instruction Manual 68P81039E25. 
Referring to FIG. 2, there is illustrated a general block diagram of a 
microprocessor 200 embodying the present invention. Microprocessor 200 is 
an eight-bit microprocessor that may be constructed on an integrated 
circuit utilizing conventional silicon gate CMOS technology to provide 
relatively low power consumption. Microprocessor 200 is architectured such 
that the bit manipulations required by high speed supervisory signalling, 
such as that required in cellular type radiotelephone systems, can be 
quickly and efficiently accommodated. Thus, microprocessor 200 can be 
advantageously utilized in any application where both low power 
consumption and fast data manipulations are required. 
The architecture of microprocessor 200 is organized around three buses, 
data bus 210, register bus 220, and address bus 230. Data signals are 
routed between the various blocks of microprocessor 200 by selectively 
interconnecting the three buses 210, 220 and 230 in response to control 
signals provided by ALU and control programmable logic arrays (PLA) 202. 
PLA's 202 decode program instructions loaded in instruction register (IR) 
201 to provide the appropriate control signals for executing each 
instruction in Table I hereinbelow. The various control signals provided 
by PLA's 202 are described in further detail hereinbelow with reference to 
FIGS. 3A and 3B and FIG. 4. 
Microprocessor 200 also includes three general purpose registers 216, R0, 
R1 and R2, an arithmetic logic unit (ALU) 213 with two temporary registers 
211 and 212, T1 and T2, and zero and carry flags 214, serial data bus 
circuitry 260 including format generator 237 and registers 235 and 236, a 
special purpose register 232, R3, a stack pointer counter 203, a 
twelve-bit program counter register 222, a temporary program counter 
register 204 and associated incrementer 206, and a temporary address 
register 221, T3. All of the registers in microprocessor 200 are latching 
type registers since a full clock cycle interval is allowed for transfers 
between registers. 
The unique architecture of the inventive microprocessor 200 insures that 
instructions are executed in a minimum number of clock cycles. For 
example, the loading of the instruction register 201 with the next 
instruction from memory via data bus 210 can occur at the same time that 
the results of the last instruction are being written by way of the 
register bus 220 into the appropriate register. As a result of the unique 
architecture of the microprocessor 200, all instructions in Table I 
hereinbelow can be completed in four or less clock cycles. Thus, the 
inventive microprocessor 200 can be operated at slower speeds to reduce 
power consumption, while maintaining the through-put necessary for 
accommodating high-speed, cellular type supervisory signalling. 
Another feature of the unique architecture of microprocessor 200 is that 
interrupts are serviced in a minimum number of clock cycles because 
general purpose registers 216, condition flags 214 and program counter 
register 222 include primary and duplicate registers (indicated by primes 
in FIG. 2). Thus, the primary set of registers 216 and 222 and flags 214 
is used during normal operation, and the duplicate set is used during 
interrupts. By utilizing duplicate registers 216 and 222 and duplicate 
condition flags 214, a considerable amount of processing time is saved 
since microprocessor 200 does not have to store the contents of the 
registers and condition flags before transferring to the interrupt service 
subroutines. Thus, during an interrupt, the duplicate registers 216 and 
222 and duplicate conditions flags 214 are used by microprocessor 200, 
while the contents of the primary registers and flags remain unchanged. 
After processing the interrupt, microprocessor 200 switches back to the 
primary registers 216 and 222 and flags 214, returning to normal operation 
in at most two clock cycle intervals. 
Another feature of the unque architecture of microprocessor 200 is that the 
R0, R1, R2 and R3 registers 216 and 231 may be directly controlled by the 
control program in ROM 103 in FIG. 1. Of the R0, R1 and R2 registers 216, 
the R1 and R2 registers are multipurpose registers which can be used as 
address pointer or data registers, and the R0 register is a single purpose 
register which can be used as a data register only. R3 registers 231 is 
also a special purpose register, whose four least significant bits are 
used for page addressing when accessing data from ROM 103 or RAM 104 in 
FIG. 1 and whose four most significant bits are used to control the four 
direct I/O lines 240. 
Another feature of the unique architecture of microprocessor 200 is that 
seven levels of subroutine nesting are allowed. For each level of nesting, 
the subroutine return addresses are saved in a stack, addressed by stack 
pointer counter 103 and located in the upper sixteen bytes of page zero of 
RAM 104 in FIG. 1. These locations of RAM are reserved for access only by 
jump to subroutine JSR and return from subroutine RTS instructions (see 
Table I hereinbelow). When using the rest of the instruction set of 
microprocessor 200, accessing these locations of RAM will result in 
activation of the I/O enable line to data interface unit 105 rather than 
the RAM enable line to RAM 104 in FIG. 1. This operation of microprocessor 
200 is utilized to uniquely address up to sixteen different I/O devices, 
such as data interface unit 105 in FIG. 1, when the I/O enable lline is 
activated. 
The unique architecture of microprocessor 200 also provides for two 
condition flags 214, the zero flag and carry flag. The zero flag is set to 
a binary one state if the result of an arithmetic operation in ALU 213 is 
zero, and it is otherwise cleared to a binary zero state. The carry flag 
has a binary one state if a carry has resulted from an arithmetic 
operation in ALU 213 or if a high order binary one bit has been shifted 
out of ALU 213 during a shift operation. Microprocessor 200 includes four 
conditional jump instructions, JEQ, JNE, JCC, JCS (see Table I 
hereinbelow), for responding to the binary zero or one state of the zero 
and carry flags 214. 
According to another unique feature of the architecture of microprocessor 
200, serial data bus circuitry 260 provides bidirectional communications 
between microprocessor 200 and a number of interface adapters 107-112 in 
FIG. 1 by way of serial data bus 250. Sixteen-bit data signals are loaded 
into registers 235 and 236 and applied according to a self-clocking 
transmission scheme by format generator 237 to serial data bus 250 for 
transmission to the interface adapters. The particular interface adapter 
addressed by the sixteen-bit data signal transmits a return data signal on 
the serial data bus 250, which is loaded into register 236 while the last 
eight bits of the sixteen-bit data signal are being transmitted. Data 
transmission on the serial data bus 250 is completely under control of 
microprocessor 200, which polls the various interface adapters on a time 
available basis. Since the self-clocking transmission scheme is 
insensitive to speed and timing variations, microprocessor 200 can 
interrupt data transmission on the serial data bus 250 for long periods of 
time (seconds, minutes, etc.) without affecting the transmission or 
reception of the data signals. The data bus circuitry 260 and the 
self-clocking transmission scheme are described in further detail in the 
aforementioned co-pending application, Ser. No. 187,303, now U.S. Pat. No. 
4,369,516. 
Referring to FIGS. 3A and 3B taken together, there is illustrated a more 
detailed block diagram of microprocessor 200, showing the specific control 
signals applied to each block by PLA's 202. PLA's 202 decode the signals 
from instruction register 201 to provide arithmetic control signals and 
address and data routing control signals. The circuitry of PLA's 202 is 
described in more detail with reference to FIG. 4 hereinbelow. The 
function of the various input and output signals of microprocessor 200 is 
described in Table IV hereinbelow. 
ALU 213 operates on signals from T1 register 212 and T2 register 211 in 
accordance with selected arithmetic and logical combining functions. For 
example, the ALU can be shifted left SLEN, shifted right SREN, perform 
additions ADD, perform logical ANDing AND, or perform logical exclusive 
ORing XOR. The T1 and T2 register 212 is enabled to receive signals from 
register bus 220 by the TICKEN signal, while the T2 register 211 is 
enabled to receive signals from the data bus 210 by the T2CKEN signal. The 
output of the ALU 213 is applied to register bus 220 in response to the 
ALUOUTEN signal. 
Some instructions require the ALU input from T2 register 211 to be 
modified. The .phi.SEL control signal forces the ALU input from T2 
register 211 to be all zero, the 1SEL control signal forces the ALU input 
from T2 register 211 to be all ones, the BNSEL control signal causes the 
contents of the T2 register 211 to be logically complemented. Some 
instructions require that the carry input to the ALU 213 be a binary one. 
This is done by setting the ALUCIN control signal to a binary one state. 
The timing for ALU 213 is such that the inputs are latched in registers 211 
and 212 during one clock cycle and the ALU output is loaded into RAM 216 
during the next clock cycle. This timing scheme simplifies the design of 
registers 211 and 212 and RAM 216, because they need not have master/slave 
operation. Master/slave operation is not required since, in effect, 
registers 211 and 212 are the master part, and RAM 216 is the slave part 
of a composite master/slave register. Another advantage of this 
configuration is that a maximum amount of time is allowed for propagation 
delay through ALU 213, since data is presented to ALU 213 during one clock 
cycle and used during the next clock cycle. However, this unique timing 
feature of ALU 213 does not increase the number of clock cycles required 
for implementing an ALU instruction since the data bus 210 and register 
bus 220 are separate, allowing the loading of RAM 216 by way of the 
register bus 220 to overlap the loading of instruction register 201 with 
the next instruction from ROM 103 in FIG. 1 via the data bus 210. 
Carry and zero flag flip-flops 214 receive a carry signal from ALU 213 and 
a register bus zero signal from NAND gate 291, respectively. The carry 
flag flip-flop is set in response to the SETC signal and enabled by the 
CARRYEN signal, while the zero flag flip-flop is enabled by the ZEROEN 
signal. The carry flag flip-flop is set by the SEC instruction, cleared by 
the CLC instruction and tested when executing the JCC and JCS jump 
instructions (see Table I hereinbelow). The zero flag flip-flop is tested 
when executing the JEQ and JNE jump instructions. 
The R0, R1 and R2 registers 216 are provided in a 6.times.8 RAM register 
file, which is clocked by the R3CK signal. Selection between the R0, R1 
and R2 registers is determined in response to the IR0-IR3 signals from 
instruction register latch 201. The selected register R0, R1 or R2 is 
applied to the register bus 220 in response to the RAMOUTEN signal. When 
an interrupt is executed, the duplicate R0', R1' and R2' registers are 
selected in response to the INT signal and used instead of the R0, R1 and 
R2 registers. 
Serial data bus generator 260 receives two eight-bit data signals from the 
register bus 220 in response to the CK3B signal for transmission by means 
of the serial data bus lines, TD, CD and RD, to various interface adapters 
107-112 in FIG. 1. Serial data bus generator 260 includes two registers 
235 and 236 and a format generator 237 as illustrated in FIG. 2. Data is 
serially shifted out of the two registers and applied to the serial data 
bus by the format generator in response to the CK3B signal. Since the 
serial data bus is self-clocking, the speed at which the data signals are 
applied to the serial data bus can be varied. Thus, it is not critical 
that microprocessor 200 provide the CK3B signal at regular intervals. 
The clock and interrupt control signals necessary for each of the blocks of 
the microprocessor are provided by block and interrupt control logic 280. 
The frequency of operation of the microprocessor is determined by the OSCA 
and OSCB signals which may be supplied by a clock source 102 in FIG. 1 
that may typically be a crystal oscillator. The clock and interrupt 
control logic includes a divider for dividing the OSCA/B signal to provide 
an .phi./2 signal to the various blocks of the microprocessor and .phi./2 
and .phi./4 signals which are coupled to data interface unit 105 and 
synchronization unit 106 in FIG. 1. The clock and interrupt control 
circuitry is responsive to the IRQ signal for providing the INT signal 
during interrupts, the RESET signal for resetting the various circuitry of 
microprocessor 200 to an initial state, the RSST signal for resetting the 
ST10 and the ST20 signals and the MSKCLK signal for masking and unmasking 
interrupts. Further details of the circuitry in the clock and interrupt 
control logic are provided hereinbelow with reference to FIG. 7. 
The program counter register 222 is loaded in response to the PCCK clock 
signal with the contents of the temporary program counter register 204 by 
way of increment 206 . During interrupts the PCCK clock signal is disabled 
and the INTPCCK clock signal is enabled for loading and interrupt program 
counter register 222 with the contents of the temporary program counter 
204. Thus, switching between the program counter register and interrupt 
program counter register 222 is accomplished by controlling the PCCK and 
INTPCCK clock signals. Disabling the PCCK clock signal saves the contents 
of the program counter register 222 until the PCCK signal is re-enabled at 
the end of the interrupt. Signals from the program counter register and 
interrupt program counter register 222 are applied to the address bus by 
the PCTOADRS signal and INT signal, respectively, and routed back to the 
temporary program counter register 204 to be incremented by incrementer 
206 to provide the next instruction address. However, if the next 
instruction address is to be modified, signals from the register bus 220 
are coupled to the temporary program counter register 204 in response to 
the ABTOTPL, HIRTNJAM, or HIPCJAM signals. The program counter register 
signals are normally incremented by one to provide the next instruction 
address. However, during jump instructions, transfer to and from interrupt 
instructions and transfer to and from subroutine instructions (see Table I 
hereinbelow), the next instruction address is modified by loading the 
temporary program counter register 204 by way of the register bus 220. 
The T3 temporary address register 221 is loaded from the register bus 220 
in response to the T3CKEN signal. Eight bits of the T3 register 221 and 
four bits from the R3 data rights 231 are applied to the address bus 230 
in response to the T3TOADRS for addressing various peripherals, such as 
ROM 103, RAM 104 and data interface unit 105 in FIG. 1. 
The stack pointer counter 203 is incremented and decremented depending on 
the state of IR1 from instruction register latch 201 when enabled by the 
SPCKEN signal. Because the stack pointer counter 203 can be both 
incremented and decremented, the stack pointer can be changed without the 
need for additional instructions for incrementing or decrementing the 
stack pointer in ALU 213. The stack pointer counter 203 points to a 
sixteen-byte stack at addresses 0E0 to 0FF (in hexadecimal) in RAM 104 in 
FIG. 1, which contains return addresses that are loaded into the program 
counter register 222 when returning from subroutines. When gated to the 
address bus 230 by the SPTOADRS signal, the stack pointer 203 addresses 
two eight-bit locations in RAM 104 in FIG. 1 for storing a thirteen-bit 
return address for each of seven possible levels of subroutine nesting. 
The operation of stack pointer counter 203 aids in reducing the number of 
execution cycles for the jump to subroutine JSR and return from subroutine 
RTI instructions. Stack pointer counter 203 is a four-bit up/down counter. 
Thus, since stack pointer counter 203 can be both incremented and 
decremented without using data bus 210 or register bus 220, both the data 
bus 210 and register bus 220 are available for other operations during the 
time that stack pointer counter 203 is being incremented or decremented. 
Thus, the data bus 210 and register bus 220 can be used for storing the 
subroutine return address into RAM 104 in FIG. 1, while decrementing the 
stack pointer counter 203 during a jump to subroutine JSR instruction. 
The R3 data direction register 232 and R3 data register 231 are utilized to 
provide four direct I/O signals from microprocessor 200. Four bits of the 
R3 data register 231 contain the binary states of signals to be applied to 
the direct I/O signals, and four bits contain the high order bits 
associated with temporary address register 221. The binary state of the 
signals loaded into R3 data direction register 232 determine whether or 
not the direct I/O signals are inputs or outputs. If a binary one bit is 
loaded into data direction register 232, the corresponding direct I/O 
signal is an output and the binary state from the corresponding bit of 
data register 231 is applied thereto. The binary states of the direct I/O 
signal and the address bits in R3 data register 231 are applied to the 
register bus 220 in response to the R3RD signal. 
The page logic 285, described in further detail with reference to FIG. 5 
hereinbelow, controls the state of address bus signal A12 for selecting a 
particular page of memory in ROM 103 or RAM 104 in FIG. 1. The state of 
the A12 signal is applied to RB4 of the register bus 220 in response to 
the HIRTNRD signal. 
The RAM and I/O enable logic 290, described in further detail with 
reference to FIG. 6 hereinbelow, is responsive to the RAMEN signal for 
providing either the RAM enable signal or the I/O enable signal depending 
on the address applied to address bus 230. The RAM enable signal is 
applied to RAM 104, while the I/O enable signal is applied to the data 
interface unit 105 in FIG. 1. 
Referring to FIG. 4, there is illustrated a detailed circuit diagram for 
the ALU and control PLA's 202 in FIG. 3A. In FIG. 4, the control PLA 403 
and ALU PLA 401 may be any conventional programmable logic array loaded in 
accordance with hexadecimal data in Tables V and VI, respectively, 
hereinbelow. 
The control PLA 403 and ALU PLA 401 are responsive to the CLK and CLKD 
clock signals for reading out signals stored at locations addressed by the 
IR0L-IR7L signals from instruction register 201 in FIG. 3A. The signals 
applied to the rows of the AND array (see Table V) of the ALU PLA 401 are 
IR0L, IR1L, IR2L ANDed with IR3L, IR4L, IR5L, IR6L and IR7L. Similarly, 
the signals applied to the rows of the AND array (see Table VIA) of the 
control PLA 403 are ST20L, ST10L, IR7L, IR6L, IR5L, IR4L, IR2L ANDed with 
IR3L, IR1L and IR0L. The read-out control signals from PLA 401 (from rows 
of the OR array in Table V) are loaded into latch 402, while the read-out 
control signals from PLA 403 (from rows of the OR array in Table VIB) are 
loaded into latch 404 (rows 1-11 in Table VIB) and latch 405 (rows 12-22 
in Table VIB). The control signals from latches 402, 404 and 405 are 
applied to blocks of microprocessor 200 as indicated in FIGS. 3A and 3B. 
Several additional control signals are provided by gating circuitry 410 
depending upon the particular instruction being executed and the binary 
state of the carry and zero flags. 
Referring to FIG. 5, there is illustrated in more detail the page logic 285 
in FIG. 3A. Flip-flop 501 stores the page bit which is applied together 
with the INT signal to A12 of the address bus by NOR gate 511. Thus, 
during interrupts, A12 is forced to a binary zero state by the INT signal. 
The page bit from flip-flop 501 is applied to RB4 of the register bus via 
gate 512 in response to the HIRTNRD signal. The page bit of flip-flop 501 
is loaded by RB4 via gate 513 and transmission gates 514 when both the 
RSST and HIRTNJAM signals have a binary one state. The page bit in 
flip-flop 501 is recirculated via transmission gates 514 when the RSST 
signal has a binary zero state. When the RSST signal has a binary one 
state and the HIRTNJAM signal has a binary zero state, the page bit in 
flip-flop 501 is loaded from flip-flop 502. At the same time that the page 
bit in flip-flop 501 is loaded with RB4, flip-flop 502 is likewise loaded 
with RB4 via transmission gates 520. Flip-flop 502 is loaded with IR4 from 
the instruction register when both the PAGCLK signal and the RSST signal 
have a binary one state. Otherwise, the output of flip-flop 502 is 
recirculated by transmission gates 520. 
Referring to FIG. 6, there is illustrated in more detail the RAM and I/O 
enable logic 290 in FIG. 3A. The RAM enable signal is provided by the 
microprocessor when accessing either RAM 104 or data interface unit 105 in 
FIG. 1. Depending on the binary state of the address bus lines AB4-AB11 
and the SPTOADRS signal, either the RAM enable signal is provided or the 
I/O enable signal is provided. If AB4-AB7 all have a binary one state, 
AB8-AB11 all have a binary zero state and the SPTOADRS signal has a binary 
zero state, then gate 602 provides a binary one state of the I/O enable 
signal. When the I/O enable signal has a binary one state, up to sixteen 
I/O devices, such as data interface unit 105 in FIG. 1, can be addressed 
by the low order bits of the address bus, AB0-AB3, applied thereto. The 
subroutine return address stack in RAM 104 in FIG. 1 is also assigned to 
the same addresses as the I/O devices. Thus, when the contents of the 
stack pointer counter 203 in FIG. 3A are applied to the address bus in 
response to the binary one state of the SPTOADRS signal, the I/O enable 
signal from gate 602 is forced to a binary zero state and the RAM enable 
signal is provided with a binary one state by gate 601 since gate 603 is 
also forced to a binary zero state by the binary one state of the SPTOADRS 
signal. For all other addresses, the RAM enable signal is provided with a 
binary one state by gate 601. 
Referring to FIG. 7, there is illustrated in more detail the clock and 
interrupt control circuitry 280 in FIG. 3B. The external clock signals 
OSCA and OSCB, provided typically by a crystal oscillator or other 
suitable clock source, are coupled by appropriate circuitry to divider 
701. The first two stages of divider 701 provide the .phi./2 and .phi./4 
clock signals which are coupled to selected peripheral devices. The 
operating frequency of the microprocessor can be changed by strapping gate 
702 to one of the four stages of the divider 701. Thus, the microprocessor 
clock frequency can be made slower to reduce power dissipation depending 
on the timing requirements of a particular system. In the preferred 
embodiment of the present invention, gate 702 is coupled to the fourth 
stage of divider 702, providing 0.24 MHz clock signal when the OSCA/B 
clock signals have a nominal frequency of 3.84 MHz. Gate 702 provides 
clock signal CLK, which is coupled to gates 704 and 705 to provide clock 
signal .phi.2 and coupled by gates 704 and 703 to provide a delayed clock 
signal CLKD. The various clock signals are distributed throughout the 
blocks of microprocessor 200 in FIGS. 3A and 3B. 
Flip-flop 710 is coupled to a reset signal for providing via gate 711 an 
initial reset signal POR for initializing all of the registers, latches 
and flip-flops in the various blocks of microprocessor 200 in FIGS. 3A and 
3B. Circuitry is typically coupled to the reset signal that provides a 
momentary pulse whenever the microprocessor power supply is turned on. The 
POR signal also causes a predetermined address to be loaded into the 
program counter register 22 in FIG. 3B for causing the microprocessor to 
execute an initialization routine stored thereafter. 
Flip-flops 720 and 721 are each arranged as master/slave flip-flops for 
providing up to four states for each instruction, where each state 
corresponds to a clock cycle interval. For an instruction requiring four 
clock cycle intervals, the ST10 signal from flip-flop 720 has a binary one 
state during the second and third clock cycle intervals, and the ST20 
signal from flip-flop 721 has a binary one state during the third and 
fourth clock cycle intervals. Both flip-flops 720 and 721 are reset to the 
binary zero state via NAND gate 722 and 723 by the RSST signal. The RSST 
signal has a binary one state during the last cycle interval of each 
instruction, resetting the ST10 and ST20 signals to the binary zero state 
for the following instruction. 
A peripheral device may cause the microprocessor to execute an interrupt by 
placing a momentary binary zero state on the IRQ signal bus. The IRQ 
signal bus is coupled to each peripheral device that is serviced by the 
interrupt subroutine of the microprocessor, such as the data interface 
unit 105 in FIG. 1. The binary zero state on the IRQ signal bus is coupled 
via gates 734 and 735 to flip-flop 730, causing the INT signal to have a 
binary one state. Gate 735 is enabled by the RSST signal during the last 
clock cycle interval of each instruction. In addition, gate 735 is 
disabled by the output of interrupt mask flip-flop 737, providing for the 
masking of interrupts under program control. The INT signal from flip-flop 
730 is maintained at a binary one state by way of gate 736 and 734 until 
an RTI instruction (see Table I hereinbelow) is executed. The RTI 
instruction results in a binary one state of the MSKCLK signal which by 
way of gate 739 causes the INT signal from flip-flop 730 to be reset to 
the binary zero state. If it is desired to mask interrupts by setting the 
interrupt mask flip-flop 737, an SEI instruction is executed, setting the 
output of the interrupt mask flip-flop 737 to a binary zero state by way 
of gate 738. The output of the interrupt mask flip-flop 737 is maintained 
at a binary zero state by way of gate 740. If it is desired to remove the 
masking of interrupts, the output of the interrupt mask flip-flop 737 can 
be set to a binary one state by executing a clear interrupt instruction 
CLI. In order to return from an interrupt subroutine, execution of the CLI 
or SEI instruction resets the interrupt flip-flop 730 by way of gate 739 
and also provides a reset signal INTPCRESET from flip-flop 733 for 
resetting the interrupt program counter register 222 in FIG. 3B to address 
001. Flip-flop 731 provides an interrupt signal INTD that is delayed by 
one clock cycle from the INT signal provided by flip-flop 730. 
During the execution of an interrupt, the alternate registers 222 and 216 
and alternate carry and zero flags 214 in FIG. 1 are utilized by the 
microprocessor. Switching from the program counter register to the 
interrupt program counter register 222 in FIG. 3B is accomplished by 
flip-flop 732 which, in response to the INT signal, enables the INTPCCK 
signal and disables the PCCK signal. Thus, during interrupts, the 
interrupt program counter register 222 in FIG. 3B is clocked by the 
INTPCCK signal, while the disabled PCCK signal holds the program counter 
register 222 in FIG. 3B in the latched state. The contents of the program 
counter register are saved until the end of the interrupt, when the 
INTPCCK signal is disabled and the PCCK signal is re-enabled. 
Flip-flop 750 is initially reset by the POR signal and enables the R3DDRCK 
signal so that the data direction register 232 in FIG. 3A may be loaded to 
define which of the direct I/O signals are inputs and outputs. Once the 
data direction register has been loaded, flip-flop 750 changes state and 
enables the R3DRCK signal for loading the R3 data register 231. Gates 
751-754 decode the direct I/O instructions, providing the R3CK signal at 
the output of gate 751 and the R3RD signal at the output of gate 752. The 
contents of the lower half of the R3 data register 231 in FIG. 3A and the 
state of the direct I/O signals is applied to the register bus 220 in FIG. 
3A in response to the R3RD signal from gate 752. The R3CK signal from gate 
751 is the clock signal for the R0, R1 and R2 registers 216 in FIG. 3B. 
The instruction repertoire of the microprocessor is shown in Tables I, II 
and III hereinbelow. The microprocessor has six addressing modes, 
immediate, direct, pointer, inherent, extended and register, each of which 
is described in Table III. These addressing modes gives the microprocessor 
a great amount of flexibility, resulting in more efficient and simpler 
control programs. A control program is included in Table VII, hereinbelow, 
which is loaded into ROM 103 in FIG. 1 for enabling the microprocessor to 
control the operation of a portable radiotelephone in a cellular 
radiotelephone system of the type described in the aforementioned Motorola 
Instruction Manual 68P81039E25 and in the aforementioned Motorola 
developmental cellular system application. 
The microprocessor in FIGS. 3A and 3B can be constructed of conventional 
integrated circuit devices, such as the CMOS devices described in the CMOS 
Integrated Circuits Book, published by Motorola Semiconductor Products, 
Inc., Austin, Tex., 1978. Furthermore, the microprocessor in FIGS. 3A and 
3B can be constructed with electrical circuit devices suitable for 
integration into a semiconductive substrate, such as CMOS, and provided in 
a single integrated circuit device. 
In summary, a unique microprocessor has been described that is 
architectured to efficiently process high speed supervisory signalling, 
while also minimizing power consumption. Instruction execution times are 
minimized through the use of data, address and register buses for allowing 
instruction overlap, a stack pointer counter having incrementing and 
decrementing capability, an arithmetic logic unit having separate input 
registers and duplicate program counter registers, general purpose 
registers and zero and carry flags for use during interrupts. The unique 
processor further includes a self-clocking serial data bus for 
bidirectional communications to peripheral units on a low priority basis. 
Since the initiation and timing of the data communications on the serial 
data bus can be varied under program control, the microprocessor can 
accommodate high speed supervisory signalling on a high priority interrupt 
basis, while handling the data communications on the serial data bus on a 
time available basis. Thus, the inventive microprocessor is a very 
powerful signal processor and controller that can be advantageously 
utilized in any application where both low power consumption and fast data 
manipulation are required. 
TABLE I 
__________________________________________________________________________ 
BASIC INSTRUCTIONS 
NMEMONIC 
FUNCTION HEXADECIMAL FORMATS 
__________________________________________________________________________ 
ADD Add B0-BB 
AND AND D0-DB 
BIT Bit test C0,C4,C8,CC 
CLC Clear carry 4D 
CLI Clear interrupt mask 
2D 
CLR Clear 8D,8F,01,05,09 
CMP Compare A0,A4,A8,AC 
COM Complement (1's) 
ED,EE,EF,61,65,69 
DEC Decrement AD,AE,AF,21,25,29 
INC Increment 9D,9E,9F,11,15,19 
JCC Jump if carry clear 
02 
JCS Jump if carry set 
00 
JEQ Jump if equal zero 
40 
JMI Jump indirect BD,BE,BF,31,35,39 
JMP Jump unconditional 
03 
JNE Jump if not equal zero 
42 
JSR Jump to subroutine 
43 
LDA Load immediate or from RAM 
80-8C 
LOD Load from ROM 91,92,93,95,96,97,99,9A,9B 
ORA Inclusive or F0-FC 
PAG Load A.sub.12 address bit 
6D = SET,7D = RESET 
ROL Rotate left CD,CE,CF,41,45,49 
ROR Rotate right DD,DE,DF,51,55,59 
RTI Return from interrupt 
2D 
RTS Return from subroutine 
0D 
SDO Send data to serial data bus 
71,75,79 
SEC Set carry 5D 
SEI Set interrupt xask 
3D 
SNO Test serial bus activity 
1D 
STA Store accumulator 
C1-CB 
SUB Subtract A1-AB 
XOR Exclusive OR E0-EC 
__________________________________________________________________________ 
TABLE II 
______________________________________ 
REGISTER-TO-REGISTER INSTRUCTIONS 
All register-to-register instructions are two bytes long 
and are coded according to the table below: 
______________________________________ 
Source R0 R1 R2 R3 
______________________________________ 
1st Byte 90 94 98 9C 
Destination R0 R1 R2 R3 OP CODE 
______________________________________ 
2nd Byte 80 84 88 8C LDA 
A0 A4 A8 AC CMP 
B0 B4 B8 BC ADD 
C0 C4 C8 CC BIT 
D0 D4 D8 DC AND 
E0 E4 E8 DC XOR 
F0 F4 F8 FC ORA 
______________________________________ 
TABLE III 
ADDRESS MODES 
Immediate 
The second byte of the instruction contains the operand. 
Direct 
The second byte of the instruction contains the low 8 bits of the memory 
address. The high 4 bits are determined by the contents of the least 
significant 4 bits of R3. 
Pointer 
R1 or R2 contains the low 8 bits of the memory address. The high 4 bits are 
determined by the contents of the least significant 4 bits of R3. 
Inherent 
Does not require memory address. 
Extended 
First and second byte of instruction combines to form a 12-bit address for 
both conditional and unconditional jumps. 
First Byte: OP3, OP2, A.sub.11, A.sub.10, A.sub.9, A.sub.8, OP1, OP0 
Second Byte: A.sub.7, A.sub.6, A.sub.5, A.sub.4, A.sub.3, A.sub.2, A.sub.1, 
A.sub.0 
Register-to-Register 
The operation is between the designated source and designation registers 
with the result going into the destination register. 
TABLE IV 
MPU SIGNAL DESCRIPTION 
ROM ENABLE--Strobes external ROM. 
RAM ENABLE--Strobes external RAM. 
I/O ENABLE--Strobes external I/O. 
A.sub.0 -A.sub.12 --Address outputs which are used to address peripherals. 
DIO.sub.0 -DIO.sub.3 --Software programmable I/O lines directly controlled 
by the contents of R3. 
TD, CD, RD--True data, complement data and return data signal lines of 
self-clocking serial data bus. 
RESET--Low level resets the processor. 
OSCA, OSCB--Crystal Inputs, nominal frequency=3.84 MHz 
IRQ--This level sensitive input requests that an interrupt sequence be 
generated within the microprocessor. After completing the current 
instruction, the microprocessor will switch control and use the interrupt 
registers, the interrupt program counter, and the interrupt condition 
codes. Interrupts can be masked in the microprocessor if desired. 
.phi.2--This output is the system clock and is used. for strobing/clocking 
ROM, RAM and other I/O 
D.sub.0 -D.sub.7 --Bi-Directional Data Bus 
R/W--The Read/Write line is an output which signals peripherals and memory 
devices whether the MPU is in a Read (binary one) or Write (binary zero) 
state. The normal standby state of this signal is Read (binary one). 
.phi./2--This output has a frequency of 1/2 the frequency of OCSA/B. 
.phi./4--This output has a frequency of 1/4 the frequency of OSCA/B. 
V.sub.DD --+V supply connection. 
V.sub.SS --Ground connection. 
TABLE V 
______________________________________ 
ALU PLA AND ARRAY 
1 1 A 5 B 0 6 9 7 
0 4 0 0 0 2 8 2 0 
0 2 0 A 4 8 0 0 8 
1 5 A 0 A 2 A A 7 
1 9 8 8 A 5 2 8 0 
0 2 0 7 1 8 4 1 F 
0 2 2 0 3 9 6 0 0 
1 1 1 7 C 6 1 F 8 
0 D 0 0 0 6 1 F B 
1 2 2 7 E 1 E 2 4 
0 0 C 1 F 9 8 C 6 
1 F 2 6 0 6 7 2 1 
0 E 5 F 5 F D 7 8 
1 1 0 0 C 0 2 8 7 
OR ARRAY 
1 F F 8 0 0 0 0 0 
1 C 0 7 F 8 0 0 4 
1 0 0 6 0 0 0 0 4 
0 0 0 0 0 0 0 0 1 
0 0 0 0 0 0 0 0 2 
0 0 0 0 0 6 0 0 0 
1 2 0 7 F 8 6 2 0 
0 1 0 0 0 0 0 9 8 
0 0 0 1 C 0 0 0 0 
0 0 0 0 3 8 0 0 0 
0 F 0 0 0 0 7 0 0 
1 0 0 6 0 1 8 0 0 
0 0 0 0 0 1 0 C 0 
0 2 0 0 0 2 6 0 0 
______________________________________ 
TABLE VIA 
__________________________________________________________________________ 
CONTROL PLA -AND ARRAY 
__________________________________________________________________________ 
0 0 4 0 0 0 1 4 8 E 0 0 0 0 3 0 0 0 0 1 E 
1 0 0 1 8 0 0 0 7 1 F E 3 F C F 9 8 7 E 
1 
1 1 E 1 0 1 F E 0 7 0 0 0 0 0 5 8 7 8 1 
E 
2 E 0 E F E 0 0 C 8 0 0 2 3 F 8 6 0 0 2 
0 
E F F F F F E 0 0 0 0 0 0 0 0 0 0 0 0 0 
0 
0 0 0 0 0 0 0 1 F F F F F F F F F F F F 
F 
0 3 2 F C 2 8 1 3 4 0 1 1 C 2 0 0 0 1 C 
0 
3 4 0 0 2 5 0 2 0 0 5 2 8 2 8 2 C 9 8 1 
0 
0 0 0 1 8 2 5 1 3 5 0 0 9 0 2 6 0 0 1 C 
0 
0 0 2 8 5 4 4 2 0 0 A 9 0 D 4 0 3 0 0 0 
8 
0 0 0 1 8 2 5 0 2 0 0 5 9 0 2 3 0 6 0 8 
5 
0 0 2 4 4 C 8 B 4 0 0 0 2 C 0 0 0 0 1 0 
0 
0 0 1 1 8 3 8 0 6 3 0 0 7 F C 5 8 7 8 0 
0 
0 2 0 0 7 C 2 2 1 0 0 0 0 0 0 2 1 8 7 C 
0 
2 0 0 1 B F E B 9 0 0 F 0 0 3 8 6 0 0 0 
0 
1 5 4 2 0 0 0 0 6 F 9 0 0 8 C 0 0 2 C 6 
1 
0 8 8 0 0 0 0 1 0 0 0 F 0 0 2 0 6 0 0 0 
0 
1 4 0 1 B E 8 2 0 0 6 0 7 7 1 C 0 5 2 8 
2 
__________________________________________________________________________ 
TABLE VIB 
__________________________________________________________________________ 
CONTROL PLA OR ARRAY 
__________________________________________________________________________ 
3 A 0 F 0 0 0 0 3 1 0 C 1 C 2 1 F 8 4 0 0 
0 1 C 0 0 1 7 9 0 4 0 0 0 0 0 0 0 0 0 1 
E 
0 0 0 0 3 8 0 1 0 8 0 E 0 0 0 0 7 8 0 0 
0 
3 F F 0 0 0 0 1 F F F F C 0 0 0 0 0 0 0 
0 
1 9 8 3 0 1 6 D 8 4 0 0 0 0 0 0 0 0 0 1 
E 
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
0 
0 4 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
0 
0 4 0 1 8 0 0 0 4 1 F 0 3 0 0 4 0 0 0 8 
1 
1 9 8 2 0 1 6 D 8 4 0 0 0 0 0 0 0 0 0 1 
E 
1 8 0 2 4 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 
0 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
0 
0 0 0 0 0 0 8 2 0 0 0 0 0 0 0 0 0 0 0 0 
0 
0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
0 
1 9 C 2 0 1 7 9 8 4 0 0 0 0 0 0 0 0 1 1 
E 
0 4 0 0 0 0 0 2 1 0 E 1 0 0 7 8 0 0 0 0 
0 
1 8 0 3 8 0 0 0 5 0 0 0 2 F F 0 0 0 0 4 
0 
0 0 0 0 0 0 0 0 3 0 0 E 1 8 2 8 7 8 4 2 
0 
2 0 0 C 0 0 0 1 E 0 0 0 3 F C 0 0 0 6 0 
0 
0 1 E 0 0 1 7 0 2 5 0 0 1 0 0 4 0 7 8 1 
E 
1 9 8 2 C 1 6 D 8 4 0 0 0 C 0 0 0 0 0 1 
E 
0 0 0 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 
0 
0 0 0 0 0 0 0 0 5 1 E 0 0 0 0 C 0 0 4 0 
1 
__________________________________________________________________________ 
##SPC1##