Printed circuit board

A printed circuit board includes: an insulation material including a cavity formed therein; a first electronic element disposed in the cavity and including a groove; and a second electronic element disposed in the groove of the first electronic element.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2018-0163382, filed on Dec. 17, 2018, the entire disclosure of which is hereby incorporated by reference for all purposes.

BACKGROUND

The following description relates to a printed circuit board.

2. Description of Background

An amount of data managed by an electronic device increases to realize various functions of the electronic device. As a result, the number of electronic components required in the electronic device has been various and increasing. As the number of electronic components included in the electronic device increases, the number of necessary passive components may also increase.

SUMMARY

In one general aspect, a printed circuit board includes: an insulation material including a cavity formed therein; a first electronic element disposed in the cavity and including a groove; and a second electronic element disposed in the groove of the first electronic element.

The first electronic element may include a dielectric layer having internal electrodes formed therein and an insulating layer laminated on the dielectric layer, and the groove may pass through the insulating layer.

The groove may expose a surface of the dielectric layer.

The groove may pass through a part of the insulating layer.

The first electronic element may include a pair of external electrodes disposed on a surface of first electronic element, and a width of the groove may be equal to or less than a distance between the pair of external electrodes.

The external electrodes may not overlap the groove in a thickness direction of the printed circuit board.

The printed circuit board may include an adhesive member adhering to the second electronic element disposed on a bottom surface of the groove.

The adhesive member may correspond to an external electrode of the second electronic element.

A thickness of the first electronic element may be greater than a thickness of the second electronic element.

A thickness of the second electronic element may be equal to or greater than a thickness of the groove.

A surface of the second electronic element may protrude from a surface of the insulation material.

The insulation material may include a first layer having the cavity formed therein and a second layer laminated on the first layer, and the first electronic element may be in contact with a surface of the second layer.

The printed circuit board may include a buildup layer laminated on the insulation material and filling the cavity.

The printed circuit board may include: a first via passing through the buildup layer and electrically connected to the first electronic element; and a second via passing through the buildup layer and electrically connected to the second electronic element.

A thickness of the first via may be greater than a thickness of the second via.

The printed circuit board may include: a filling layer filling the cavity; and a buildup layer laminated on the filling layer and the insulation material.

The printed circuit board may include: a circuit disposed on the filling layer; and a via passing through the filling layer and configured to electrically connect the circuit to the first electronic element or the second electronic element.

The printed circuit board may include a through via passing through the insulation material in a thickness direction of the printed circuit board.

The second electronic element may include a plurality of electronic elements.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating a printed circuit board according to an example.

Referring toFIG. 1, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300.

The insulating material100is a plate-like structure made of a nonconductive material. The insulating material100may be made of a material including a resin and the resin included in the insulating material100may be selected from a variety of thermosetting resins, thermoplastic resins, and the like such as an epoxy resin, a polyimide (PI) resin, a BT resin, a liquid crystal polymer (LCP), or the like. However, the material of the insulating material100is not limited thereto. Particularly, the insulating material100may be a prepreg (PPG) or an ABF film.

The insulating material100may include a fiber reinforcing material or a filler. The fiber reinforcing material may include glass fiber, and the glass fiber may be at least one of a glass filament, a glass fiber, and a glass fabric which are classified depending on thickness. The prepreg may have a structure in which an epoxy resin is impregnated into glass fiber. The filler may be an inorganic filler or an organic filler.

The insulating material100has a cavity110. That is, the cavity110opened to an upper surface of the insulating material100is formed in the insulating material100. The cavity110may be opened to an upper surface of the insulating material100, but may not be opened to a side surface thereof. The cavity110may partially penetrate the insulating material100in a thickness direction, not the entire insulating material100. The cavity110may have a rectangular parallelepiped shape.

The first electronic element200may be located within the cavity110and may contact a bottom surface of the cavity110. The first electronic element200may be a passive device such as a capacitor. In this case, the first electronic element200may be a multi-layer ceramic capacitor (MLCC).

The first electronic element200may include a dielectric layer210including an internal electrode211(211in (a) to (d) ofFIG. 10), an insulating layer220stacked on the dielectric layer210, and an external electrode230. A groove221may be formed on an upper surface of the first electronic element200.

The dielectric layer210may be formed of a ceramic material. The internal electrode211is formed in the dielectric layer210. The dielectric layer210may be formed by repeatedly alternately laminating a dielectric sheet and the internal electrode211. The dielectric sheet may be a ceramic sheet. The internal electrode211may be formed of a material including a metal such as nickel (Ni). The internal electrode211may be cured after a nickel paste is applied. The internal electrode211may include a positive electrode and a negative electrode.

The insulating layer220may be laminated on the dielectric layer210and may be formed of a material including a resin such as an epoxy resin. A thickness of the insulating layer220is less than a thickness of the dielectric layer210.

The groove221may be formed in the insulating layer220. As shown inFIG. 1, the groove221may be formed at the center of the insulating layer220and an upper surface of the dielectric layer210may be exposed by the groove221.

A pair of external electrodes230may be formed to cover the dielectric layer210and the insulating layer220and may be electrically connected to the internal electrode211. When the internal electrode211includes a positive electrode and a negative electrode, one of the pair of external electrodes230may be connected to the internal electrode211of the positive electrode and the other may be connected to the internal electrode211of the negative electrode. The external electrode230electrically connects the first electronic element200to an external structure.

The pair of external electrodes230may be spaced apart from each other. The pair of external electrodes230may be positioned at both ends of the first electronic element200to cover an upper surface of the insulating layer220, a side surface of the dielectric layer210and a bottom surface of the dielectric layer210.

A width of the groove221in the insulating layer220may be the same as a distance between the pair of external electrodes230and the external electrode230may not cover the groove221.

(a) to (d) ofFIG. 10are diagrams illustrating a method for manufacturing a first electronic element.

Referring to (a) ofFIG. 10, a dielectric layer210is provided by repeatedly alternately laminating a dielectric sheet and an internal electrode. Here, the dielectric layer210may be sintered. The plurality of internal electrodes211are arranged to be vertically spaced apart from each other. A part of the plurality of internal electrodes211is exposed to one side surface of the dielectric layer210to be a positive electrode and the rest is exposed to the other side surface of the dielectric layer210to form a negative electrode.

Referring to (b) ofFIG. 10, an insulating layer220is formed on the dielectric layer210.

Referring to (c) ofFIG. 10, a groove221is formed in the insulating layer220. The groove221of the insulating layer220may be formed through laser processing, photolithography, or the like.

Referring to (d) ofFIG. 10, a pair of external electrodes230are formed to surround an upper surface of the insulating layer220, a side surface of the dielectric layer210, and a lower surface of the dielectric layer210. One of the pair of external electrodes230is in contact with a positive electrode, and the other is in contact with a negative electrode. The external electrode230does not cover the groove221.

Referring back toFIG. 1, the second electronic element300is located within the cavity110and is in contact with the first electronic element200. The second electronic element300may be inserted into the groove221and formed on or adjacent to the upper surface of the first electronic element200.

The second electronic element300may be a passive device such as a capacitor. The second electronic element300may be a multi-layer ceramic capacitor (MLCC). The second electronic element300may include a dielectric layer310including internal electrodes therein and an external electrode320formed on a surface of the dielectric layer310to be electrically connected to the internal electrode.

The second electronic element300may be inserted into the groove221of the insulating layer220when the groove221is formed in the insulating layer220of the first electronic element200. A lower part of the second electronic element300may be surrounded by the insulating layer220. A thickness of the second electronic element300may be equal to or greater than a thickness of the groove221. The upper surface of the second electronic element300may be protruded from the upper surface of the first electronic element200, but may not be protruded from the upper surface of the cavity110. The upper surface of the second electronic element300may be located on the same plane as the upper surface of the insulating material100and the cavity110.

The second electronic element300may not be in contact with the external electrode230of the first electronic element200. Particularly, the external electrode320of the second electronic element300is spaced apart or isolated from the external electrode230of the first electronic element200.

A size of the second electronic element300may be smaller than that of the first electronic element200. Particularly, a thickness of the second electronic element300may be less than a thickness of the first electronic element200. A width of the second electronic element300may be less than a width of the first electronic element200. A width of the second electronic element300may be smaller than a width of the groove221of the insulating layer220.

An adhesive member Ad may be formed on a bottom surface of the groove221of the first electronic element200to be in contact with the second electronic element300. As shown inFIG. 1, when the dielectric layer210of the first electronic element200is exposed through the groove221of the insulating layer220, the adhesive member Ad is formed on an upper surface of the dielectric layer210of the first electronic element200. The adhesive member Ad may be formed corresponding to an area of a lower surface of the second electronic element300. The adhesive member Ad may be formed of a non-conductive material having adhesiveness.

(a) to (f) ofFIG. 9are diagrams illustrating an arrangement of a first electronic element200and a second electronic element300. The first electronic element200and the second electronic element300are passive elements having the same structure and each of the first electronic element200and the second electronic element300has a pair of external electrodes at both ends thereof. In each electronic element, a line connecting the pair of external electrodes is referred to as an external electrode connecting line.

As shown in (a) ofFIG. 9, the external electrode connecting line of the first electronic element200may be perpendicular to the external electrode connecting line of the second electronic element300. This arrangement is possible when a long width of the second electronic element300is less than a short width of the first electronic element200. InFIG. 9(a), a circular mark on the external electrode is a contact portion of a first via V1or a second via V2.

As shown in (b) ofFIG. 9, the external electrode connecting line of the first electronic element200may be positioned on the same plane as the external electrode connecting line of the second electronic element300.

As shown in (c) ofFIG. 9, the external electrode connecting line of the first electronic element200may be positioned obliquely to the external electrode connecting line of the second electronic element300.

As shown in (d) to (f) ofFIG. 9, the second electronic element300may be formed in plural. That is, a plurality of second electronic elements300may be located on one first electronic element200. In this case, the plurality of second electronic elements300are inserted into one groove221of the first electronic element200. Alternatively, the groove221of the first electronic element200may be formed in plural to correspond to the plurality of second electronic elements300. The second electronic element300may be formed of three or more.

An arrangement of the first electronic element200and the second electronic element300according to (a) to (f) ofFIG. 9may be determined depending on the size of the first electronic element200and the second electronic element300or the like.

The printed circuit board may further include a buildup layer, a circuit, an inner via IV, a through via PV (seeFIGS. 13 and 14), and the like.

The buildup layer may be formed on an upper surface and/or a lower surface of the insulating material100and made of a material including a resin. The resin included in the buildup layer may be at least one selected from thermosetting resins, thermoplastic resins and the like, particularly at least one selected from an epoxy resin, a polyimide (PI) resin, a BT resin, a liquid crystal polymer (LCP), or the like. However, the material of the buildup layer is not limited thereto.

The buildup layer may include a fiber reinforcing material or a filler. As a specific buildup layer, a prepreg (PPG) and an ABF film may be used. The buildup layer may be made of the same material as or different from that of the insulating material100.

The buildup layer on an upper surface of the insulating material100may be referred to as a first buildup layer410and the buildup layer on a lower surface of the insulating material100may be referred to as a second buildup layer420.

The first buildup layer410may be stacked on an upper surface of the insulating material100and may fill the cavity110. Filling the inside of the cavity110means that after the first and second electronic elements200and300are inserted into the cavity110, the remaining space of the cavity110is filled with the first buildup layer410. By filling the cavity110with the first buildup layer410, the first electronic element200and the second electronic element300may be fixed.

The second buildup layer420may be laminated on a lower surface of the insulating material100with the same thickness as the first buildup layer410. Each of the first buildup layer410and the second buildup layer420may be formed to be thinner than the insulating material100.

A circuit provides a path for transmitting an electrical signal and is formed of at least one selected from copper, silver, palladium, aluminum, nickel, titanium, gold, platinum.

A circuit formed on an upper surface of the insulating material100may be referred to as a first circuit C1and a circuit formed on an upper surface of the first buildup layer410may be referred to as a second circuit C2. After the first circuit C1is formed on the upper surface of the insulating material100, the first buildup layer410is formed on the insulating material100and the second circuit C2is formed on the first buildup layer410. A part of the second circuit C2may be located on upper surfaces of the first electronic element200and the second electronic element300.

The first circuit C1and the second circuit C2may be electrically connected through an inner via IV. The second circuit C2and the first electronic element200may be electrically connected through a first via V1and the first via V1may pass through the first buildup layer410to be in contact with the external electrode230of the first electronic device200. The second circuit C2and the second electronic element300may be electrically connected through a second via V2and the second via V2may pass through the first buildup layer410to be in contact with the external electrode320of the second electronic element300. A thickness of the first via V1may be greater than a thickness of the second via V2. A part of the first via V1may be located inside the cavity110.

A circuit formed on a lower surface of the insulating material100may be referred to as a third circuit C3and a circuit formed on an upper surface of the second buildup layer420may be referred to as a fourth circuit C4. The third circuit C3and the fourth circuit C4may be electrically connected through an inner via IV. Although all the first to fourth circuits C1to C4are shown inFIG. 1, some of them may be omitted if necessary.

A through via PV passes through the insulating material100to electrically connect the first circuit C1and the third circuit C3, as shown inFIG. 13.

Each of the first via V1, the second via V2, the inner via IV and the through via PV may be formed of at least one material chosen from copper (Cu), silver (Ag), palladium (Pd), aluminum (Al) nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt), and may be formed of the same metal as the circuit.

FIG. 2toFIG. 8are diagrams illustrating printed circuit boards of various examples. Hereinafter, in the description of the various printed circuit boards, description of contents overlapping with the printed circuit board described above may be omitted.

Referring toFIG. 2, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300, which are the same as the printed circuit board ofFIG. 1.

In this example, the printed circuit board includes a filling layer120filling a cavity110instead of filling the cavity with a first buildup layer410. The first buildup layer410is formed on upper surfaces of the insulation material100and the filling layer120. The filling layer120may be formed of the same material as the first buildup layer410and may not be integrated with the first buildup layer410to form a bonding interface. The filling layer120may also be formed of a material different from a material of the first buildup layer410. The first electronic element200and the second electronic element300may be fixed by the filling layer120.

A total height of the first electronic element200and the second electronic element300may be less than a height of the cavity110. An upper surface of the second electronic element300may be positioned lower than an upper surface of the insulating material100.

A first circuit C1is formed on an upper surface of the insulating material100and on an upper surface of the filling layer120, and the first circuit C1is electrically connected to the first electronic element200and/or the second electronic element300. That is, a via V1′ connecting the first circuit C1and the first electronic element200may be in contact with an external electrode230of the first electronic element200through the filling layer120. A via V2′ connecting the first circuit C1and the second electronic element300may be in contact with the external electrode320of the second electronic element300through the filling layer120. The via V1′ for connecting the first circuit C1to the first electronic element200and the via V2′ for connecting the first circuit C1and the second electronic element300are all formed inside the cavity110. A thickness of the via V1′ connecting the first circuit C1and the first electronic element200may be greater than a thickness of the via V2′ connecting the first circuit C1and the second electronic element300.

The first circuit C1and the second circuit C2may be electrically connected through an inner via IV. The inner via IV may have a stack via structure with the via V1′ connecting the first circuit C1and the first electronic element200. The inner via IV may also have a stack via structure with the via V2′ connecting the first circuit C1and the second electronic element300.

Referring toFIG. 3, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300, wherein the first electronic element200includes a dielectric layer210, an insulating layer220and an external electrode230and the insulating layer220has a groove221formed therein.

In this example, a width of a groove221is smaller than a distance between a pair of external electrodes230, unlike the printed circuit board ofFIG. 1. The groove221may be formed at a central portion between the pair of external electrodes230. A width of the groove221may be the same as a width of the second electronic element300. In this case, a surface of the second electronic element300(or the external electrode320of the second electronic element300) may be in contact with the insulating layer220.

Referring toFIG. 4, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300, wherein the first electronic element200includes a dielectric layer210, an insulating layer220and an external electrode230, and wherein the insulating layer220has a groove221formed therein.

Unlike the printed circuit board ofFIG. 1, a thickness of a groove221is less than that of the insulating layer220. In this example, the groove221penetrates a part of the thickness of the insulating layer220. An upper surface of the dielectric layer210is not exposed through a bottom surface of the groove221and the insulating layer220is also formed on the bottom surface of the groove221. An adhesive member Ad is formed on the insulating layer220on the bottom surface of the groove221.

Referring toFIG. 5, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300, wherein the first electronic element200includes a dielectric layer210, an insulating layer220and an external electrode230, and wherein the insulating layer220has a groove221formed therein and an adhesive member Ad is formed on a bottom surface of the groove221.

In this example, an area of the adhesive member Ad is smaller than that of the printed circuit board inFIG. 1. The adhesive member Ad may be formed to have a smaller area than a lower surface of the second electronic element300. The adhesive member Ad may be formed corresponding to the external electrode320located on a lower surface of the second electronic element300.

Referring toFIG. 6, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300.

In this example, a thickness of the second electronic element300may be equal to or less than a thickness of the groove221. An upper surface of the second electronic element300may be located below an upper surface of the first electronic element200. Particularly, when the upper surface of the second electronic element300is located on the same plane as the upper surface of the first electronic element200, a thickness of a first via V1electrically connecting the second circuit C2and the first electronic element200may be the same as that of a second via V2electrically connecting the second circuit C2and the second electronic element300. Also, when an upper surface of the second electronic element300is located below an upper surface of the first electronic element200, a thickness of the second via V2may be greater than the thickness of the first via V1.

Referring toFIG. 7, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300.

In this example, an upper surface of the second electronic element300is protruded from an upper surface of a cavity110. That is, the upper surface of the second electronic element300is positioned higher than the upper surface of the insulating material100. In this case, the upper surface of the second electronic element300is located lower than an upper surface of the first buildup layer410. A thickness of a first via V1is greater than a thickness of a second via V2and a part of the first via V1is located inside the cavity110, while the entire second via V2is located on the cavity110.

Referring toFIG. 8, a printed circuit board includes an insulating material100, a first electronic element200, and a second electronic element300, wherein the insulating material100includes a plurality of layers.

The insulating material100may include a first layer111and a second layer112. A cavity110is formed in the first layer111and the cavity110is entirely passed through the first layer111in a vertical direction. The second layer112is laminated under the first layer111to expose an upper surface of the second layer112through the cavity110. That is, the first electronic element200is in contact with the upper surface of the second layer112.

The insulating material100may include three or more layers. In this case, the cavity110may be formed only on one layer, and the other layers may be sequentially stacked on the one layer. Other features other than that the insulating material100including a plurality of layers are the same as those described with reference toFIG. 1.

(a) to (c) ofFIG. 11are diagrams illustrating a method for manufacturing the printed circuit board ofFIG. 1.

Referring to (a) ofFIG. 11, a cavity110is formed in an insulating material100. The cavity110penetrates a part of the insulating material100. A first circuit C1and a third circuit C3may be formed on upper and lower surfaces of the insulating material100, respectively.

Referring to (b) ofFIG. 11, a first electronic element200and a second electronic element300are inserted into the cavity110. The first electronic element200is first inserted and then the second electronic element300is inserted into a groove221of the first electronic element200. Alternatively, the second electronic element300may be inserted into the cavity110after the second electronic element300is inserted into the groove221of the first electronic element200.

Referring to (c) ofFIG. 11, a first buildup layer410is stacked on an upper surface of the insulating material100, and the first buildup layer410may fill up the cavity110. A second circuit C2is formed on the first buildup layer410. The second circuit C2includes a first via V1connecting the first electronic element200and the second circuit C2and a second via V2connecting the second electronic element300and the second circuit C2.

An inner via IV is formed in the first buildup layer410to connect the first circuit C1and the second circuit C2. The second buildup layer420may be laminated on a lower surface of the insulating material100. A fourth circuit C4may be formed in the second buildup layer420. An inner via IV connecting the third circuit C3and the fourth circuit C4is formed in the second buildup layer420.

(a) to (f) ofFIG. 12are diagrams illustrating a method for manufacturing the printed circuit board ofFIG. 8.

Referring to (a) ofFIG. 12, a cavity110is formed in a first layer111of an insulating material100, and a tape T is attached to a bottom surface of the first layer111. The cavity110is covered by the tape T. A circuit may be formed on an upper surface of the first layer111, but it is not shown in the drawing.

Referring to (b) ofFIG. 12, a first electronic element200and a second electronic element300are inserted into the cavity110. The first electronic element200is first inserted and then the second electronic element300is inserted into a groove221of the first electronic element200. Alternatively, the second electronic element300may be inserted into the cavity110after the second electronic element300is inserted into the groove221of the first electronic element200. The tape T may support the first electronic element200.

Referring to (c) ofFIG. 12, a first buildup layer410including a metal layer411is stacked on the first layer111and may fill the inside of the cavity110.

Referring to (d) ofFIG. 12, the tape T is removed. The first electronic element200and the second electronic element300may be fixed by the first buildup layer410after the tape T is removed.

Referring to (e) ofFIG. 12, a second layer112is stacked under the first layer111and a second buildup layer420including a metal layer421is stacked on a lower surface of the second layer112. A circuit may be formed on a bottom surface of the second layer112before the second buildup layer420is stacked on the bottom surface of the second layer112.

Referring to (f) ofFIG. 12, the metal layer411of the first buildup layer410is patterned to become a circuit C2, and the metal layer421of the second buildup layer420is also patterned to become a circuit C4.

FIG. 13andFIG. 14are diagrams illustrating a package using a printed circuit board according to an example.

Referring toFIG. 13, a package may include a printed circuit board on which an electronic component is mounted and an electronic element is embedded on the printed circuit board. The electronic component mounted on the printed circuit board may be an active component, an IC or the like, and a first electronic element200and a second electronic element300embedded in the printed circuit board may be passive components. Each of the first electronic element200and the second electronic element300may be formed in plural.

Although the printed circuit board with reference toFIG. 1is used in the package with reference toFIG. 13andFIG. 14, any printed circuit board according to the various examples shown inFIG. 2toFIG. 8may be applied.

Referring toFIG. 13, a first buildup layer410is stacked on an upper surface of an insulating material100, a second buildup layer420is stacked on a lower surface of the insulating material100, and a plurality of buildup layers510may be stacked on the first buildup layer410, and a plurality of buildup layers520may be stacked under the second buildup layer420. The number of buildup layers may be variously determined as needed. Solder resists610and620are stacked on the outermost buildup layers. The solder resists610and620partially expose the outermost circuits CA and CB.

The electronic component E may be flip-chip mounted on the outermost circuit CA exposed by the solder resist610with a soldering member S such as solder. An underfill U may be formed in the gap between the electronic component E and the printed circuit board caused by a height of the soldering member S. The electronic component E may be a CPU, but is not limited thereto.

As shown inFIG. 14, a package may include an interposer I. The interposer I is mounted on a printed circuit board, and an underfill U may be formed in a gap below the interposer I.

The interposer I is mounted on the outermost circuit CA exposed by the solder resist610with a soldering member S such as solder and a plurality of electronic components E1and E2are mounted on the interposer I. The interposer I may be formed of a silicon material. The electronic component E1may be an application-specific integrated circuit (ASIC), a graphics processing unit (GPU) or the like, and the electronic component E2may be a high bandwidth memory (HBM), but is not limited thereto. On the other hand, the plurality of electronic components E1and E2may be integrally molded on the interposer I by a molding material M such as an epoxy molding compound (EMC).

If this printed circuit board having such electronic elements is used, the parasitic inductance and impedance may be reduced and the power integrity may be increased because a distance between the electronic component and the electronic element is reduced. In addition, since electronic elements are embedded in the printed circuit board, the space occupied by the electronic components on the printed circuit board may be increased. An overall thickness of the package may also be reduced.