External observation and control of data in a computing processor

A processor access module receives a data command from an agent located externally of a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. Alternatively, the processor access module receives a data command from the agent and performs a cache operation on the cache memory based on the data command to store a computer program into the cache memory. The processor access module then receives a boot command from the agent and boots the computing processor to initiate execution of the computer program.

BACKGROUND

1. Field of the Invention

The present invention relates generally to systems and methods of accessing data in a computing processor. More particularly, the present invention relates to accessing data in a cache memory of a computing processor to externally observe and control the data.

2. Background Art

Some prior art computing processors, such as a microprocessor, include a cache memory to reduce the access time to data during execution of computing instructions. In such a computing processor, the computing processor accesses data in a main memory external to the computing processor and stores the data into the cache memory. Because the access time to the data in the cache memory is faster than the access time to the data in the main memory, the computing processor subsequently accesses the data in the cache memory instead of the main memory. Further, if the computing processor modifies the data in the cache memory, the computing processor eventually stores the modified data into the main memory to maintain consistency between the data in the main memory and the data in the cache memory.

In these computing processors, data in the cache memory is not readily accessible externally of the computing processor. Although the computing processor can access the data in the cache memory, the data in the cache memory cannot be externally observed or controlled without executing computing instructions in the computing processor to make the data externally accessible. Moreover, the computing processor must access the computing instructions from the cache memory or the main memory before executing the computing instructions, which delays access to the data in the cache memory.

In light of the above, there exists a need for an improved system and method of externally accessing data in a cache memory of a computing processor.

SUMMARY OF THE INVENTION

A processor access module addresses the need for an improved system and method of externally accessing data in a cache memory of a computing processor. The processor access module receives a data command from an agent external to the computing processor and performs a cache operation on the cache memory based on the data command to access data in the cache memory. In this way, data in the cache memory of the computing processor is externally observable and controllable.

In a method in accordance with one embodiment of the present invention, a data command is received from an agent external to a computing processor. Access to a cache memory in the computing processor is obtained in response to the data command, and a cache operation is performed on the cache memory based on the data command. In another embodiment, a computer program product includes computer program code for performing the method.

A system, in accordance with one embodiment of the present invention, includes a slave bus controller and a cache operation controller. The slave bus controller is configured to receive a data command from an agent external to a computing processor. The cache operation controller is configured to obtain access to a cache memory in the computing processor in response to the data command and to perform a cache operation on the cache memory based on the data command.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A processor access module, in accordance with one embodiment, receives a data command from an agent external to a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. The cache operation may involve storing data into the cache memory or retrieving data from the cache memory. In another embodiment, the processor access module stores a computer program into the cache memory based on the data command. In this embodiment, the processor access module receives a boot command from the agent and boots the computing processor in response to the boot command to initiate execution of the computer program stored in the cache memory.

FIG. 1depicts an exemplary computing environment100in which a processor access module145, in accordance with one embodiment of the present invention, can be practiced. The exemplary computing environment100includes an exemplary computing processor105, a main memory140, and an agent165external to the computing processor105. The computing processor105, the main memory140, and the agent165are coupled in communication with each other via a computer bus135. The agent165provides commands to the computing processor105for accessing data in the computing processor105(i.e., retrieving data from the computing processor105or storing data or a computer program into the computing processor105), as is described more fully herein. For example, the agent165can be another computing processor105coupled in communication with the computer bus135. In one embodiment, the computing processor105is embodied in an integrated circuit. For example, the computing processor105can be a microprocessor, a microcontroller, an embedded processor, or an embedded controller, among other possibilities.

The exemplary computing processor105shown inFIG. 1includes an execution unit110and a collection of processor registers120coupled in communication with the execution unit110. The execution unit110executes computing instructions in the computing processor105and the processor registers120store data for the execution unit110. The exemplary computing processor105also includes a cache controller125, a master bus controller130, a cache memory access controller170, and a cache memory185. The cache controller125is coupled in communication with the execution unit110, the master bus controller130, and the cache memory access controller170. Further, the master bus controller130is coupled in communication with the computer bus135, and the cache memory access controller170is coupled in communication with the cache memory185. The cache memory access controller170controls access from the cache controller125to the cache memory185, as is described more fully herein.

The cache controller125receives a data request from the execution unit110and accesses data in the main memory140or the cache memory185, or both, based on the data request. In one exemplary computing processor105, the cache controller125stores data from the data request into the main memory140via the master bus controller130or into the cache memory185via the cache memory access controller170. In another exemplary computing processor105, the cache controller125retrieves data from the main memory140via the master bus controller130or from the cache memory185via the cache memory access controller170and provides the data to the execution unit110. In still another exemplary computing processor105, the cache controller125retrieves data from the main memory140via the master bus controller130and stores the data into the cache memory185via the cache memory access controller170.

The exemplary computing processor105also includes a configuration registers access controller180and a collection of configuration registers195. The configuration registers195store control and status information for the computing processor105. In one exemplary computing processor105, the configuration registers access controller180is coupled in communication with the execution unit110and the configuration registers195. In this exemplary computing processor105, the configuration registers access controller180controls access from the execution unit110to the configuration registers195, as is described more fully herein.

The processor access module145processes commands received from the agent165and performs operations on the cache memory185based on the commands. In this way, the agent165can externally observe and control data in the cache memory185without the need for executing computing instructions in the execution unit110. In one embodiment, the processor access module145includes a cache operation controller (cache op controller)150and a slave bus controller155. The cache operation controller150is coupled in communication with the cache memory access controller170and the slave bus controller155is coupled in communication with the computer bus135. In this embodiment, the cache memory access controller170controls access from both the cache controller125and the cache operation controller150to the cache memory185. In one further embodiment, the cache operation controller150is further coupled in communication with the slave bus controller155. In another further embodiment, the cache operation controller150is coupled in communication with the configuration registers access controller180, and the slave bus controller155is coupled in communication with the configuration registers access controller180.

The slave bus controller155receives commands from the agent165via the computer bus135. In one embodiment, the slave bus controller155receives a data command from the agent165and provides the data command to the cache operation controller150. In response to receiving the data command from the slave bus controller155, the cache operation controller150performs a cache operation on the cache memory185based on the data command, as is described more fully herein. In another embodiment, the slave bus controller155receives a data command from the agent165, obtains access to the configuration registers195from the configuration registers access controller180, and stores the data command into the configuration registers195via the configuration registers access controller180. In this embodiment, the cache operation controller150performs a cache operation on the cache memory185based on the data command stored in the configuration registers195, as is described more fully herein.

The cache operation controller150performs cache operations on the cache memory185based on the data commands. In one embodiment, the cache operation controller150receives a data command from the slave bus controller155, obtains access to the cache memory185from the cache memory access controller170in response to receiving the data command, and performs a cache operation on the cache memory185via the cache memory access controller170based on the data command. The cache operation may involve storing data from the data command into the cache memory185or retrieving data from the cache memory185and providing the data to the agent165or some other destination via the slave bus controller155. Alternatively, the cache operation may involve modifying one or more attribute fields of a cache line in the cache memory185, such as a valid bit or a dirty bit. Further, the cache operation may involve modifying a cache line tag in the cache memory185.

In another embodiment, the cache operation controller150monitors the configuration registers195, detects a data command stored in the configuration registers195, obtains access to the cache memory185via the cache memory access controller170, and performs a cache operation on the cache memory185based on the data command. In this embodiment, the cache operation can include storing data from the configuration registers195(e.g., data in the data command stored in the configuration registers195) into the cache memory185or retrieving data from the cache memory185and storing the data into the configuration registers195.

In one embodiment, the cache operation controller150is capable of performing one or more of the cache operations defined by the MIPS32 Instruction Set Architecture (ISA). The MIPS32 ISA is described in “MIPS32™ Architecture for Programmers, Volume II: The MIPS32™ Instruction Set,” Document Number MD00086, Revision 0.95, Mar. 12, 2001, which is incorporated herein by reference. For example, the cache operation controller150can perform a cache fill operation based on the data command to fill the cache memory185with data from the main memory140at a memory address of the main memory140specified in the data command. As a further example, the data can include a computer program.

In one embodiment, the configuration registers access controller180allows the execution unit110to access the configuration registers195when the execution unit110is executing computing instructions and allows the slave bus controller155and the cache operation controller150to access the configuration registers195when the execution unit110is not executing computing instructions. In another embodiment, the execution unit110sets a run bit in the configuration registers195to indicate that the execution unit110is executing a computing instruction and clears the run bit to indicate that the execution unit110is not executing a computing instruction. In this embodiment, the configuration registers access controller180prevents the cache operation controller150and the slave bus controller155from accessing the configuration registers195when the run bit is set.

In one further embodiment, the cache memory access controller170allows the cache controller125to access the cache memory185and prevents the cache operation controller150from accessing the cache memory185when the execution unit110is executing computing instructions. In this embodiment, the cache memory access controller170prevents the cache controller125from accessing the cache memory185and allows the cache operation controller150to access the cache memory185when the execution unit110is not executing computing instructions.

In another further embodiment, the cache memory access controller170allows the cache controller125to the access cache memory185and prevents the cache operation controller150from accessing the cache memory185when the run bit is set. In this embodiment, the cache memory access controller170prevents the cache controller125from accessing the cache memory185and allows the cache operation controller150to access the cache memory185when the run bit is clear.

In one embodiment, the slave bus controller155receives a boot command from the agent165via the computing bus135and boots the computing processor105in response to receiving the boot command. In a further embodiment, the slave bus controller155stores the boot command into the configuration registers195via the configuration registers access controller180to boot the computing processor105. In this further embodiment, the slave bus controller155sets a reset bit in the configuration registers195to boot the computing processor105, and the computing processor105clears the reset bit once the computing processor105is booted. In various embodiments, the execution unit110initiates execution of a computer program (i.e., computing instructions) stored in the cache memory185in response to the computing processor105being booted. In one embodiment, the boot command indicates a memory address of the computer program stored in the cache memory185. In this embodiment, the computing processor105initiates execution of the computer program at the memory address in response to the computing processor105being booted.

In various embodiments, the processor access module145can include more than one cache operation controller150, cache memory access controller170, and cache memory185. For example, the processor access module145may include one cache operation controller150dedicated to a data cache memory185in the computing processor105and another cache operation controller150dedicated to an instruction cache memory185in the computing processor105. In a further embodiment, the cache operation controller150and the slave bus controller155can access the data cache memory185when the execution unit110is executing computing instructions. In this way, the execution unit110and the agent165can share data in the data cache memory185when the execution unit110is executing computing instructions.

Although the exemplary computing processor105depicted inFIG. 1includes the cache operation controller150and the slave bus controller155, it is to be appreciated that the cache operation controller150or the slave bus controller155, or both, can be external to the computing processor105in various embodiments. For example, the computing processor105may be contained in an integrated circuit of one computer chip, and the slave bus controller155can be contained in an integrated circuit of another computer chip.

In one embodiment, the processor access module145is a hardware module. Examples of a hardware module include a combinational logic circuit, a sequential logic circuit, a programmable logic device, and a computing device, among others. In another embodiment, the processor access module145includes one or more software modules. Examples of a software module include a computer program, a software routine, binary code, and firmware, among others. Another example of a software module is a computer program product, such as a compact disc read-only memory (CD-ROM) or a memory storage device, containing computer program code. In still another embodiment, the processor access module145includes both hardware and software modules.

FIG. 2depicts a flow chart for a method of accessing data in the computing processor105(FIG. 1), in accordance with an embodiment of the present invention. In step200, the agent165(FIG. 1) external to the computing processor105generates a data command for performing a cache operation on the cache memory185(FIG. 1) of the computing processor105. It is to be appreciated that step200is optional in the present invention and that an entity external to the computing processor105other than the agent165can generate the data command in various embodiments.

In step205, the slave bus controller155receives the data command from the agent165via the computing bus135(FIG. 1). In one embodiment, the slave bus controller155provides the data command to the cache operation controller150(FIG. 1). In another embodiment, the slave bus controller155stores the data command into the configuration registers195(FIG. 1) via the configuration registers access controller180(FIG. 1). In this embodiment, the cache operation controller150monitors, detects, and accesses the data command in the configuration registers195via the configuration registers access controller180. In one embodiment, the cache operation controller150obtains access to the configuration registers195by sending an access request to the configuration registers access controller180and receiving an access grant from the configuration registers access controller180in response to the access request.

In step210, the cache operation controller150obtains access to the cache memory185in response to the data command (e.g., in response to receiving the data command from the slave bus controller155or in response detecting the data command in the configuration registers195). In one embodiment, the cache operation controller150obtains access to the cache memory185by sending an access request to the cache memory access controller170(FIG. 1) and receiving an access grant from the cache memory access controller170in response to the access request.

In step215, the cache operation controller150performs a cache operation on the cache memory185(FIG. 1) based on the data command. In one embodiment, the cache operation controller150performs the cache operation on the cache memory185by storing data from the data command into the cache memory185via the cache memory access controller170. In a further embodiment, the cache operation controller150provides an acknowledgement to the slave bus controller155indicating that the data is stored in the cache memory185.

In another embodiment, the cache operation controller150performs the data command by retrieving data from the cache memory185via the cache memory access controller180and providing the data to the slave bus controller155. In this embodiment, the slave bus controller155provides the data received from the cache operation controller150to the main memory140via the computer bus135. In still another embodiment, the cache operation controller150performs the cache operation on the cache memory185by retrieving data from the main memory140via the slave bus controller155and the computer bus135, and storing the data into the cache memory185via the cache memory access controller170.

In another embodiment, the cache operation controller170performs the cache operation on the cache memory185by retrieving a block of data, such as a computer program, from the main memory140via the slave bus controller155and computer bus135and storing the computer program in to the cache memory185via the cache memory access controller170. In yet another embodiment, the cache operation controller150performs the cache operation on the cache memory185by retrieving a block of data from the cache memory185via the cache memory access controller170and storing the block of data into the main memory140via the slave bus controller155and the computer bus135. In still another embodiment, the processor access module145repeats steps200-215to retrieve a computer program (e.g., data) from the main memory140via the slave bus controller155and computer bus135and stores the computer program (e.g., data) into the cache memory185via the cache memory access controller170.

FIG. 3depicts a portion of a method for accessing data in the computing processor105(FIG. 1), in accordance with another embodiment of the present invention. It is to be appreciated that the method depicted inFIG. 3is a continuation of the method depicted inFIG. 2after the processor access controller145(FIG. 1) has stored a computer program into the cache memory185(FIG. 1) in step215. In step300, the slave bus controller155(FIG. 1) receives a boot command from the agent165(FIG. 1) via the computing bus135(FIG. 1).

In step305, the slave bus controller155boots the computing processor105in response to receiving the boot command from the agent165. In one embodiment, the slave bus controller155stores the boot command into the configuration registers195(FIG. 1) via the configuration registers access controller180(FIG. 1) to boot the computing processor105. In a further embodiment, the slave bus controller155boots the computing processor105by setting a reset bit in the configuration registers195. In this further embodiment, the computing processor105clears the reset bit once the computing processor105is booted. Also in step305, the computing processor105initiates execution of the computer program in the cache memory185in response to the computing processor105being booted.