DATA LATCH CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE

A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-204613, filed Dec. 16, 2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a data latch circuit and a semiconductor storage device.

BACKGROUND

Bit density of flash memory continuously increases by the use of multi-level cells (MLCs) and three-dimensional stacking. As the bit density thereof increases, the area of peripheral circuits also increases. Among the peripheral circuits, a data latch circuit (also referred to as a page buffer) occupies the largest area. When the data latch circuit cannot be made smaller, it becomes difficult to reduce the size of the flash memory chip.

DETAILED DESCRIPTION

Embodiments provide a data latch circuit and a semiconductor storage device capable of being miniaturized.

In general, according to one embodiment, a data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

Hereinafter, embodiments of a data latch circuit and a semiconductor storage device will be described with reference to the drawings. In the following description, main components of the data latch circuit and the semiconductor storage device will be mainly described. The data latch circuit and the semiconductor storage device may have components and functions not shown in the drawings or not described in this specification. The following description is not intended to exclude the components or the functions not shown in the drawings or not described in this specification.

First Embodiment

FIG.1is a block diagram showing a schematic configuration of a semiconductor storage device1including a data latch circuit10according to a first embodiment. The semiconductor storage device1inFIG.1shows a schematic configuration of flash memory. The semiconductor storage device1according to the embodiment is applicable to various types of semiconductor memory other than the flash memory. More specifically, the semiconductor storage device1according to the embodiment is applicable to a nonvolatile memory such as MRAM (Magnetoresistive Random Access Memory) and is also applicable to volatile memory such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Additionally, the flash memory may be a NAND flash memory or a NOR flash memory, and the semiconductor storage device1according to the embodiment is applicable to both the NAND flash memory and the NOR flash memory. In the following description, an example in which the semiconductor storage device1according to the embodiment is applied to the flash memory will be mainly described.

The semiconductor storage device1inFIG.1includes a plurality of memory modules2, a serial conversion unit3, an I/O signal processing unit4, a high voltage generation circuit5, a low voltage generation circuit6, a synchronization control unit7, a row control unit8, and a column control unit9.

Each of the memory modules2includes a memory cell array11, a row decoder12, a sense amplifier & data latch unit13, a transfer data latch unit14, and a column decoder15.

The memory cell array11has a configuration in which a plurality of strings, having a plurality of NAND flash memory cells provided therein in the form of a cascode connection, are located in a two-dimensional configuration. The row decoder12decodes a row address signal and drives a corresponding word line.

The sense amplifier & data latch unit13writes data to the memory cell array11and reads the data from the memory cell array11via a bit line BL. The sense amplifier & data latch unit13includes the data latch circuit (DL)10, according to the embodiment, which is configured to store the data to be written to the memory cell array11and to store the data read from the memory cell array11.

The transfer data latch unit14temporarily stores the data to be written to the memory cell array11or the data read from the memory cell array11. The transfer data latch unit14also includes the data latch circuit10according to the embodiment.

The column decoder15performs predetermined operation processing including decoding processing for the data to be written to the memory cell array11or the data to be read from the memory cell array11.

The serial conversion unit3converts the data read from the memory cell array11into serial data, and supplies the converted data to the I/O signal processing unit4. Further, the serial conversion unit3converts the serial data to be written, transmitted from the I/O signal processing unit4, into parallel data and sends the same to the column decoder15.

The I/O signal processing unit4performs high-speed serial communication with a controller16. The high voltage generation circuit5boosts power supply voltage VDD supplied from the outside, thereby generating high-voltage VPGM, VERA, VPASS, and the like to be used when data is written to or erased from the memory cell.

The low voltage generation circuit6generates a reference voltage, a clock signal, a low power supply voltage, and the like to be used in the semiconductor storage device1.

The synchronization control unit7performs timing control, sequence control, parameter control for each block in the semiconductor storage device1.

The row control unit8controls the timing of driving a word line in each memory cell array11. The column control unit9controls the timing of driving a bit line in each memory cell array11.

As described above, the data latch circuit10according to the embodiment is provided in the sense amplifier & data latch unit13and the transfer data latch unit14in the semiconductor storage device1inFIG.1. The data latch circuit10according to the embodiment may be provided in a place other than the sense amplifier & data latch unit13and the transfer data latch unit14.

The flash memory having the block configuration shown inFIG.1is currently the lowest cost non-volatile memory, and is generally used as a large-capacity storage in various applications. In the block configuration shown inFIG.1, components other than the memory cell array11may be referred to as peripheral circuits. The data latch circuit10occupies most of the area of the peripheral circuits. The data latch circuit10, which is used as a temporary storage place, is configured to temporarily store the data to be written to the memory cell array11and the data read from the same.

In the flash memory configured to change from a planar structure to a three-dimensional structure, the bit density thereof is improved by increasing the number of bits per cell, implementing a multi-level cell (MLC), and increasing the number of stacked word lines. Here, as the bit density thereof increases, the area of the peripheral circuit increases.

When the ratio of the area of the peripheral circuit to the total area of the flash memory chip becomes large, the number of bits per wafer is reduced, and bit costs increase. As a solution to reduce the area of the flash memory chip, proposed are a CUA (CMOS Under Array) structure, in which the peripheral circuit is disposed below the memory cell array11, and a CBA (CMOS Bonded Array) structure, in which a wafer having the memory cell array11disposed thereon and a wafer having the peripheral circuit disposed thereon are bonded together. In both the CUA structure and the CBA structure, when the area of the peripheral circuit is larger than that of the memory cell array11, the area of the flash memory chip increases.

Therefore, the semiconductor storage device1according to the embodiment is characterized in that the area of the data latch circuit10in the peripheral circuit is reduced. Hereinafter, first, a circuit configuration of a general-purpose data latch circuit100according to a comparative example will be described.

FIG.2is a circuit diagram of the data latch circuit100according to the comparative example. The data latch circuit100inFIG.2includes eight transistors Q1to Q8. Among the eight transistors Q1to Q8, four transistors are referred to as NMOS transistors Q1to Q4, and the remaining four transistors are referred to as PMOS transistors Q5to Q8.

A drain of the transistor Q1is connected to a gate of the transistor Q2, a drain of the transistor Q3, a drain of the transistor Q7, and a gate of the transistor Q8. A drain of the transistor Q2is connected to a gate of the transistor Q1, a drain of the transistor Q4, a gate of the transistor Q7, and a drain of the transistor Q8. Sources of the transistors Q1and Q2are connected to a reference voltage VSS node (for example, a ground node).

A word line WL1is connected to a gate of the transistor Q3, and a word line WL2is connected to a gate of the transistor Q4. Only one of the word lines WL1and WL2goes to a high level. Sources of the transistors Q3and Q4are connected to a bit line BL.

In this manner, the data latch circuit100inFIG.2includes two word lines WL1and WL2and one bit line BL.

A source of the transistor Q5is connected to a power supply voltage VDD node, a drain of the transistor Q5is connected to a source of the transistor Q7, and a control signal Vctl is input to a gate of the transistor Q5. A source of the transistor Q6is connected to the power supply voltage VDD node, a drain of the transistor Q6is connected to a source of the transistor Q8, and a control signal Vctl is input to the gate of the transistor Q7. When the control signal Vctl is a low level, both the transistors Q5and Q6are turned ON. In this case, when either the word line WL1or the WL2goes to a high level, the nodes n1and n2store the data on the bit line BL.

As shown inFIG.2, the data latch circuit100according to the comparative example is formed of eight transistors Q1to Q8. Accordingly, as the number of data latch circuits100increases, the number of transistors increases by a multiple of 8, which results in increasing the area of the semiconductor storage device1.

FIG.3Ais a diagram showing characteristics of the data latch circuit10according to the first embodiment, andFIG.3Bis a circuit diagram of the data latch circuit10according to the first embodiment.

As shown inFIG.3A, the data latch circuit10according to the first embodiment has a configuration in which a first transistor group21including the transistors Q5and Q6, a second transistor group22including the transistors Q7and Q8, and VDD are omitted from the data latch circuit100according to the comparative example ofFIG.2. Further, the data latch circuit10according to the first embodiment includes PMOS transistors Q3aand Q4ainstead of the NMOS transistors Q3and Q4inFIG.2.

As described above, the data latch circuit10according to the first embodiment includes two NMOS transistors Q1and Q2and two PMOS transistors Q3aand Q4a.

As shown inFIG.3B, the drain of the transistor Q1is connected to the gate of the transistor Q2and a source of the transistor Q3a. This connection node is referred to as a node n1. The drain of the transistor Q2is connected to the gate of the transistor Q1and a source of the transistor Q4a. This connection node is referred to as a node n2.

The sources of the transistors Q1and Q2are connected to the ground node. A gate of the transistor Q3ais connected to the word line WL1and a gate of the transistor Q4ais connected to the word line WL2. The drains of the transistors Q3aand Q4aare connected to the bit line.

FIG.4Ais a diagram showing operation of the data latch circuit10according to the first embodiment. The data latch circuit10according to the first embodiment performs data write operation, data storage operation, and data read operation. Two word lines WL1and WL2do not go to the low level at the same time. When one of the word lines WL1and WL2goes to the high level, the data write operation is performed. For example, when the word line WL1is the low level and the word line WL2is the high level, the transistor Q3ais turned ON and the transistor Q4ais turned OFF. Accordingly, the voltage of the bit line BL is transmitted to the node n1via the transistor Q3a. For example, when the bit line BL has low voltage, the node n1also becomes low voltage, and when the bit line BL has high voltage, the node n1also becomes high voltage. The node n2becomes inverted logical voltage to the node n1. The transistors Q1and Q2perform operation of storing the voltage of the nodes n1and n2.

In the data storage operation, the two word lines WL1and WL2are both set to voltage levels slightly lower than the power supply voltage VDD. The bit line BL is set to VDD. The voltage level slightly lower than the power supply voltage VDD is, for example, a voltage level lower than the power supply voltage VDD by 5 to 30%. More specifically, the voltage levels of the gates of the transistors Q3aand Q4ain a period during which the data is stored in the nodes n1and n2are lowered by any percentage in a range of 5 to 30% of the high voltage levels of the gates of the transistors Q3aand Q4awhen the data is written to the nodes n1and n2. The reason for setting the word lines WL1and WL2to the voltage levels slightly lower than the power supply voltage VDD during the data storage period is to allow leakage current to flow through the transistors Q3aand Q4a, the gates of which are connected to the word lines WL1and WL2, respectively.

For example, when the node n1has the low voltage, the transistor Q1is turned ON, and the voltage of the node n1is stored at low voltage from the ground voltage VSS node via the transistor Q1, as shown by a dashed arrow line y1inFIG.4A. On the other hand, the transistor Q2is turned OFF, and the voltage of the node n2is stored at high voltage by leakage current flowing from the bit line BL through the transistor Q4a, as shown by a dashed arrow line y2inFIG.4A.

In this manner, the word lines WL1and WL2are set to the voltage level slightly lower than the power supply voltage VDD and the bit line BL is set to VDD. Here, when the node n1has high voltage, the voltage level of the node n1is maintained by leakage current flowing from the bit line BL through the transistor Q3a. Further, when the node n2has high voltage, the voltage level of the node n2is maintained by the leakage current flowing from the bit line BL through the transistor Q4a.

FIG.4Bis a diagram showing the voltage of the word lines WL1and WL2, and the bit line BL when the data latch circuit10inFIG.4Areads data, writes the same, and stores the same.FIG.4Bshows an example in which the word line WL1is accessed. Here, when the word line WL2is accessed, a voltage relationship between the word lines WL1and WL2inFIG.4Bis reversed.

When the data latch circuit10reads the data stored in the nodes n1and n2via the transistor Q3a, the word line WL1is set to the ground voltage VSS (for example, 0 V) and the word line WL2is set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V). Further, the bit line BL is pre-charged to the power supply voltage VDD in advance. Accordingly, the data stored in the nodes n1and n2are read in the bit line BL via the transistor Q3a.

When the data latch circuit10writes the data to the nodes n1and n2via the transistor Q3a, the word line WL1is set to the ground voltage VSS (for example, 0 V), and the word line WL2is set to the power supply voltage VDD. When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0 V). Accordingly, the data of “0” is stored in the nodes n1and n2via the transistor Q3a. Meanwhile, when the data to be written is 1, the bit line BL is set to the power supply voltage VDD.

When the data latch circuit10stores the data in the nodes n1and n2, the word lines WL1and WL2are set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V), and the bit line BL is set to the power supply voltage VDD.

FIG.5is a diagram showing storage characteristics of the semiconductor storage device1according to the first embodiment. A horizontal axis inFIG.5is the voltage level of the node n2, and a vertical axis inFIG.5is the voltage level of the node n1. A curve w1inFIG.5shows a change in the voltage level of the node n1with respect to the voltage of the node n2, and a curve w2shows a change in the voltage level of the node n2with respect to the voltage of the node n1. As shown inFIG.5, it can be seen that the nodes n1and n2are stable at two points p1and p2and have good storage characteristics. In the point p1, the voltage level of the node n1is the power supply voltage VDD. In the point p2, the voltage level of the node n2is the power supply voltage VDD.

FIG.6is a layout diagram of the data latch circuit10according to the first embodiment, andFIG.7is a cross-sectional view showing a stacking position of each layer inFIG.6. As shown inFIG.7, the data latch circuit10according to the first embodiment is formed by stacking a plurality of layers having different layer heights, and includes a plurality of contacts CT0and CT1configured to electrically connect the respective layers.FIG.6shows a planar structure in which the plurality of layers having different layer heights are viewed in the stacking direction. The layout diagram and the cross-sectional view of the data latch circuit10according to the first embodiment are not necessarily limited to those shown inFIGS.6and7. Black and gray circles inFIG.6represent the contacts.

In the examples ofFIGS.6and7, a first diffusion region D1and a second diffusion region D2are located in the lowest layer. The first diffusion region D1and the second diffusion region D2may be referred to as active regions. The first diffusion region D1and the second diffusion region D2are located apart from each other in a first direction X. A source region and a drain region of the transistors Q1and Q2are formed in the first diffusion region D1. A source region and a drain region of the transistors Q3aand Q4aare formed in the second diffusion region D2. The first diffusion region D1and the second diffusion region D2are formed by implanting impurity ions such as boron (B), phosphorus (P), and arsenic (As) into a semiconductor substrate and thermally diffusing the same therein.

A first gate layer G1connected to the gate of the transistor Q3aand a second gate layer G2connected to the gate of the transistor Q4aare located on the second diffusion region D2via an insulating layer. A third gate layer G3connected to the gate of the transistor Q1and a fourth gate layer G4connected to the gate of the transistor Q2are located on the first diffusion region D1via an insulating layer.

The first to fourth gate layers G1to G4are located at the same layer height. More specifically, each of the first to fourth gate layers G1to G4extends in a second direction Y. Further, the first to fourth gate layers G1to G4are located apart from each other in the first direction X.

A first metal layer M1is located on the first to fourth gate layers G1to G4via an insulating layer. The first metal layer M1is made of tungsten (W), copper (Cu), aluminum (Al), and the like. The first metal layer M1includes a first wiring layer WR1, a second wiring layer WR2, a third wiring layer WR3, and a fourth wiring layer WR4, each of which extends in the first direction X. Here, the first to fourth wiring layers WR1to WR4are located apart from each other in the second direction Y.

The first wiring layer WR1is the bit line BL connected to the drain of the transistor Q3aand the drain of the transistor Q4a. The second wiring layer WR2is connected to the drain of the transistor Q1, the fourth gate layer G4, and the source of the transistor Q3a. The third wiring layer WR3is connected to the drain of the transistor Q2, the third gate layer G3, and the source of the transistor Q4a.

The fourth wiring layer WR4is connected to the source regions of the transistors Q1and Q2in the first diffusion region D1.

A second metal layer M2is located on the first metal layer M1via an insulating layer. The second metal layer M2is made of tungsten (W), copper (Cu), aluminum (Al), and the like.

The second metal layer M2has a fifth wiring layer WR5. The fifth wiring layer WR5is set to the ground voltage VSS (first reference voltage). The fifth wiring layer WR5is located above the first diffusion region D1and extends in the second direction Y. The fifth wiring layer WR5is connected to the fourth wiring layer WR4. Therefore, the fourth wiring layer WR4is set to the ground voltage VSS. Further, since the fourth wiring layer WR4is connected to the source regions of the transistors Q1and Q2in the first diffusion region D1, these source regions are also set to the ground voltage VSS.

The first diffusion region D1, the second diffusion region D2, the first to fourth gate layers G1to G4, and the first to fourth wiring layers WR1to WR4inFIG.6are arranged line-symmetrically.

FIG.8is a layout diagram in which a plurality of data latch circuits10having the layout arrangement inFIG.6are located in the two-dimensional direction. InFIG.8, the plurality of data latch circuits10having the layout arrangement inFIG.6are located in the first direction X and the second direction Y. The plurality of data latch circuits10located in the second direction Y share the word lines WL1and WL2. The plurality of data latch circuits10located in the first direction X share the bit line BL.

The layout arrangements shown inFIGS.6and8are only examples, and various modifications thereof can be considered. For example, it is possible to adopt a point-symmetrical layout configuration.

FIG.9Ais a layout diagram of a first modification of the data latch circuit10according to the first embodiment, andFIG.9Bis a layout diagram of a second modification thereof. BothFIGS.9A and9Bhave a point-symmetrical layout arrangement with respect to a center position of a layout region.FIG.9Bhas a configuration in which the layout arrangement inFIG.9Ais shifted to the left or right by a half cycle. In the following description, details of the layout arrangement inFIG.9Awill be described, and description of the layout arrangement inFIG.9Bwill be omitted. A hierarchical relationship between the plurality of layers shown inFIGS.9A and9Bis the same as that ofFIG.7.

In the layout arrangement inFIG.9A, the first diffusion region D1, the second diffusion region D2, the third diffusion region D3, and the fourth diffusion region D4are located apart from each other in the second direction Y in the lowest layer. Each of the first to fourth diffusion regions D1to D4extends in the first direction X. The first gate layer G1, the second gate layer G2, the third gate layer G3, and the fourth gate layer G4are located apart from each other in the second direction Y above the first to fourth diffusion regions D1to D4.

The first gate layer G1overlaps the second diffusion region D2in the stacking direction. The second gate layer G2overlaps the third diffusion region D3in the stacking direction. The third gate layer G3overlaps the first diffusion region D1in the stacking direction. The fourth gate layer G4overlaps the fourth diffusion region D4in the stacking direction.

The first metal layer M1is located above the first to fourth gate layers G1to G4. In the first metal layer M1, the second to ninth wiring layers WR2to WR9are located apart from each other in the first direction X. Each of the second to fifth wiring layers WR2to WR5extends in the second direction Y.

The second wiring layer WR2is the word line WL1and is connected to the first gate layer G1. The third wiring layer WR3is the word line WL2and is connected to the second gate layer G2. The fourth wiring layer WR4is connected to the drain region of the transistor Q1in the first diffusion region D1, the source region of the transistor Q3ain the second diffusion region D2, and the fourth gate layer G4. The fifth wiring layer WR5is connected to the third gate layer G3, the source region of the transistor Q4ain the third diffusion region D3, and the drain region of the transistor Q2in the fourth diffusion region D4. The sixth wiring layer WR6is connected to the source region of the transistor Q1in the first diffusion region D1. The seventh wiring layer WR7is connected to the drain region of the transistor Q3ain the second diffusion region D2. The eighth wiring layer WR8is connected to the drain region of the transistor Q2in the fourth diffusion region D4. The ninth wiring layer WR9is connected to the drain region of the transistor Q4ain the third diffusion region D3.

The second metal layer M2is located above the first metal layer M1that includes the second to fifth wiring layers WR2to WR5. The second metal layer M2includes a first wiring layer WR1, a tenth wiring layer WR10, and an eleventh wiring layer WR11. The first wiring layer WR1is the bit line BL, and the tenth wiring layer WR10and the eleventh wiring layer WR11are wiring layers set to the ground voltage VSS.

The first wiring layer WR1is located between the second diffusion region D2and the third diffusion region D3. The tenth wiring layer WR10is located close to the first diffusion region D1. The eleventh wiring layer WR11is located close to the fourth diffusion region D4.

The first wiring layer WR1is connected to the seventh wiring layer WR7and is also connected to the ninth wiring layer WR9. The tenth wiring layer WR10is connected to the sixth wiring layer WR6. The eleventh wiring layer WR11is connected to the eighth wiring layer WR8.

FIG.10Ais a layout diagram in which a plurality of data latch circuits10having the layout arrangement inFIG.9Aare located in the first direction X and the second direction Y.FIG.10Bis a layout diagram in which a plurality of data latch circuits10having the layout arrangement inFIG.9Bare located in the first direction X and the second direction Y.

BothFIGS.10A and10Bhave a point-symmetrical layout arrangement of the units ofFIGS.9A and9B, and have a layout arrangement that is line-symmetric with respect to an axis extending in the second direction Y.

As described above, the data latch circuit10according to the first embodiment is formed of four transistors Q1, Q2, Q3a, and Q4a, thereby significantly reducing the circuit area thereof compared to the data latch circuit100according to the comparative example shown inFIG.2. Data is stored in the nodes n1and n2, and the voltage slightly lower than the power supply voltage VDD is applied to the word lines WL1and WL2during the data storage period, and as such, the data can be stably stored in the nodes n1and n2using the leakage current from the bit line BL. The data latch circuit10according to the first embodiment may be located in a line-symmetrical layout as shown inFIG.6, and it is also possible to have a point-symmetrical layout arrangement as shown inFIG.9AorFIG.9B.

Second Embodiment

Although the data latch circuit10according to the first embodiment includes two word lines WL1and WL2and one bit line BL, each of which is connected to a corresponding component thereof, the same can also have a configuration including one word line WL and two bit lines BL and bBL, each of which is connected to a corresponding component thereof.

FIG.11Ais a diagram showing characteristics of a data latch circuit10aaccording to a second embodiment, andFIG.11Bis a circuit diagram of the data latch circuit10aaccording to the second embodiment.

One word line WL and two bit lines BL and bBL, each of which is connected to a corresponding component of the data latch circuit10a, are provided in the data latch circuit10aaccording to the second embodiment. The common word line WL is connected to the gates of the transistors Q3aand Q4a. The bit line BL is connected to the drain of the transistor Q3a, and the bit line bBL is connected to the drain of the transistor Q4a. The bit lines BL and bBL have logic levels that are inverted with respect to each other. A connection relationship between other transistors Q1to Q4ais the same as that ofFIGS.3A and3B.

FIG.11Cis a diagram showing the voltage of the word line WL, the bit line BL and bBL when the data latch circuit10ainFIG.11Breads data, writes the same, and stores the same.

When the data latch circuit10areads the data stored in the nodes n1and n2, the word line WL is set to the ground voltage VSS (for example, 0 V). The bit lines BL and bBL are pre-charged to the power supply voltage VDD in advance. Accordingly, the data stored in the nodes n1and n2are read in the bit lines BL and bBL via the transistors Q3aand Q4ain the inverted logic.

When the data is written to the nodes n1and n2, the word line WL is set to the ground voltage VSS (for example, 0 V). When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0 V) and the bit line bBL is set to the power supply voltage VDD. Accordingly, the transistors Q1and Q2perform the operation of storing the data of “0”. Meanwhile, when the data to be written is 1, the voltage levels of the bit lines BL and bBL are inverted to those inFIG.11C.

When the data is stored in the nodes n1and n2, the word line WL is set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V), and the bit lines BL and bBL are set to the power supply voltage VDD.

FIG.12is a layout diagram of the data latch circuit10aaccording to the second embodiment. A hierarchical relationship between the plurality of layers shown inFIG.12is the same as that ofFIG.7.

In the layout arrangement inFIG.12, the first diffusion region D1, the second diffusion region D2, and the third diffusion region D3are located in the lowest layer. The first diffusion region D1and the second diffusion region D2are located apart from each other in the second direction Y. The third diffusion region D3is located apart from the first diffusion region D1and the second diffusion region D2in the first direction X.

The first gate layer G1, the second gate layer G2, and the third gate layer G3are located on the first to third diffusion regions D1to D3. The first to third gate layers G1to G3are located at the same layer height. The first gate layer G1is a word line. The first gate layer G1overlaps the first diffusion region D1and the second diffusion region D2in the stacking direction. The first gate layer G1is a layer connected to the gates of the transistors Q3aand Q4a.

The second gate layer G2and the third gate layer G3overlap the third diffusion region D3in the stacking direction. The second gate layer G2is a layer connected to the gate of the transistor Q1. The third gate layer G3is a layer connected to the gate of the transistor Q2.

The first metal layer M1is located on the first to third gate layers G1to G3. The first metal layer M1includes the first wiring layer WR1, the second wiring layer WR2, the third wiring layer WR3, the fourth wiring layer WR4, and the fifth wiring layer WR5. Here, the first to fifth wiring layers WR1to WR5respectively extend in the first direction X and are located apart from each other in the second direction Y.

The first wiring layer WR1is the bit line BL, and the second wiring layer WR2is the bit line bBL. The first wiring layer WR1overlaps the first diffusion region D1and the third diffusion region D3in the stacking direction. The first wiring layer WR1is connected to the drain region of the transistor Q3ain the first diffusion region D1. The second wiring layer WR2overlaps the second diffusion region D2and the third diffusion region D3in the stacking direction. The second wiring layer WR2is connected to the drain region of the transistor Q4ain the second diffusion region D2.

The third wiring layer WR3overlaps the first diffusion region D1and the third diffusion region D3in the stacking direction. The third wiring layer WR3is connected to the source region of the transistor Q3ain the first diffusion region D1, the drain region of the transistor Q1in the third diffusion region D3, and the third gate layer G3.

The fourth wiring layer WR4overlaps the second diffusion region D2and the third diffusion region D3in the stacking direction. The fourth wiring layer WR4is connected to the source region of the transistor Q4ain the second diffusion region D2, the second gate layer G2in the third diffusion region D3, and the drain region of the transistor Q2in the third diffusion region D3.

The fifth wiring layer WR5overlaps the third diffusion region D3in the stacking direction. The fifth wiring layer WR5is connected to the source regions of the transistors Q1and Q2in the third diffusion region D3.

The second metal layer M2is located on the first to fifth wiring layers WR1to WR5. The second metal layer M2includes the sixth wiring layer WR6. The sixth wiring layer WR6is set to the ground voltage VSS. The sixth wiring layer WR6is connected to the fifth wiring layer WR5.

FIG.13is a layout diagram in which a plurality of data latch circuits10ahaving the layout arrangement inFIG.12are located in the two-dimensional direction. InFIG.13, the plurality of data latch circuits10aare arranged line-symmetrically with respect to axes ax1and ax2extending in the second direction Y.

The layout arrangement shown inFIG.12is only an example, and various modifications thereof can be considered. For example, it is possible to adopt a point-symmetrical layout arrangement.

FIG.14Ais a layout diagram of a first modification of the data latch circuit10aaccording to the second embodiment, andFIG.14Bis a layout diagram of a second modification thereof. BothFIGS.14A and14Bhave a point-symmetrical layout arrangement with respect to the center position of the layout region. Hereinafter, details of the layout arrangement inFIG.14Awill be described, and description of the layout arrangement inFIG.14Bwill be omitted. A hierarchical relationship between the plurality of layers shown inFIGS.14A and14Bis the same as that ofFIG.7.

In the layout arrangement inFIG.14A, the first diffusion region D1, the second diffusion region D2, the third diffusion region D3, and the fourth diffusion region D4are located apart from each other in the second direction Y in the lowest layer. Each of the first to fourth diffusion regions D1D4extends in the first direction X. The first gate layer G1, the second gate layer G2, the third gate layer G3, and the fourth gate layer G4are located apart from each other in the second direction Y on the first to fourth diffusion regions D1to D4.

The first gate layer G1overlaps the second diffusion region D2in the stacking direction. The second gate layer G2overlaps the third diffusion region D3in the stacking direction. The third gate layer G3overlaps the first diffusion region D1in the stacking direction. The fourth gate layer G4overlaps the fourth diffusion region D4in the stacking direction.

The first metal layer M1is located on the first to fourth gate layers G1to G4. In the first metal layer M1, the third to ninth wiring layers WR3to WR9are located apart from each other in the first direction X. Each of the third to ninth wiring layers WR3to WR9extends in the second direction Y.

The third wiring layer WR3is connected to the first gate layer G1and the second gate layer G2. The fourth wiring layer WR4is connected to the first diffusion region D1, the second diffusion region D2, and the fourth diffusion region D4. The fifth wiring layer WR5is connected to the first diffusion region D1, the third diffusion region D3, and the fourth diffusion region D4. The sixth wiring layer WR6is connected to the first diffusion region D1. The seventh wiring layer WR7is connected to the second diffusion region D2. The eighth wiring layer WR8is connected to the fourth diffusion region D4. The ninth wiring layer WR9is connected to the third diffusion region D3.

The second metal layer M2is located on the first metal layer M1including the third to ninth wiring layers WR3to WR9. In the second metal layer M2, the first wiring layer WR1, the second wiring layer WR2, the tenth wiring layer WR10, and the eleventh wiring layer WR11are located apart from each other in the second direction Y. The first wiring layer WR1is the bit line BL, and the second wiring layer WR2is the bit line bBL. The tenth wiring layer WR10and the eleventh wiring layer WR11are layers set to the ground voltage VSS.

The tenth wiring layer WR10is connected to the sixth wiring layer WR6. The first wiring layer WR1is connected to the seventh wiring layer WR7. The eleventh wiring layer WR11is connected to the eighth wiring layer WR8. The second wiring layer WR2is connected to the ninth wiring layer WR9.

FIG.15Ais a layout diagram in which a plurality of data latch circuits10ahaving the layout arrangement inFIG.14Aare located in the first direction X and the second direction Y.FIG.15Bis a layout diagram in which a plurality of data latch circuits10ahaving the layout arrangement inFIG.14Bare located in the first direction X and the second direction Y.

BothFIGS.15A and15Bhave a point-symmetrical layout arrangement in the units ofFIGS.14A and14B, and also have a line-symmetrical layout arrangement with respect to an axis extending in the second direction Y.

As described above, the data latch circuit10aaccording to the second embodiment is formed of four transistors Q1to Q4ain the same manner as that of the first embodiment, thereby significantly reducing the circuit area thereof compared to the data latch circuit100according to the comparative example shown inFIG.2. The data latch circuit10aaccording to the second embodiment may have the point-symmetrical layout arrangement as shown inFIG.12, or may have the line-symmetrical layout arrangement as shown inFIG.14AorFIG.14B.

Third Embodiment

In the first and second embodiments described above, the data latch circuit10including four transistors Q1to Q4ais described. Here, it is also possible to provide a data latch circuit10bincluding six transistors. Two additional transistors determine whether to supply the power supply voltage VDD to the data latch circuit10b. That is, the two additional transistors make it possible to determine whether the data latch circuit10bperforms the data storage operation or the data read operation.

FIG.16Ais a diagram showing characteristics of the data latch circuit10baccording to a third embodiment, andFIG.16Bis a circuit diagram of the data latch circuit10baccording to the third embodiment. The data latch circuit10baccording to the third embodiment has a configuration in which the second transistor group22including the transistors Q7and Q8is omitted from the data latch circuit100according to the comparative example inFIG.2. The transistors Q1to Q4are NMOS transistors, and the transistors Q5and Q6are PMOS transistors.

As shown inFIG.16B, the source of the transistor Q5is connected to the power supply voltage VDD node. The drain of the transistor Q5is connected to the drain of the transistor Q1, the gate of the transistor Q2, and the drain of the transistor Q3. The source of the transistor Q6is connected to the power supply voltage VDD node, and the drain of the transistor Q6is connected to the drain of the transistor Q2, the gate of the transistor Q1, and the drain of the transistor Q4.

The common control signal Vctl is input to the gates of the transistors Q5and Q6. In the data storage operation, Vctl is set to a voltage level slightly lower than the power supply voltage VDD. The voltage level slightly lower than the power supply voltage VDD is, for example, a voltage level lower than the power supply voltage VDD by 5 to 30%. The reason for setting the gate voltage Vctl of the transistors Q5and Q6to the voltage level slightly lower than the power supply voltage VDD during the data storage period is to allow leakage current to flow through the transistors Q5and Q6.

From the data storage state, one of the word lines WL1and WL2is set to a high level and the other one is set to a low level, thereby making it possible to turn on one of the transistor Q3and Q4and to read the state of either the node n1or the node n2in the bit line.

When a high-level control signal is input to the gates of the transistors Q5and Q6, the transistors Q5and Q6are turned OFF. In this state, one of the word lines WL1and WL2is set to the high level and the other one is set to the low level, thereby making it possible to turn on one of the transistors Q3and Q4and to write data of the bit line to the node n1and the node n2.

When a low-level control signal is input to the gates of the transistors Q5and Q6, the transistors Q5and Q6are turned ON, and the drains of the transistors Q1and Q2become the power supply voltage VDD. This operation can also be used as a function of initializing the states of the node n1and the node n2.

FIG.16Cis a diagram showing the voltage of the word lines WL1and WL2, the bit line BL, and the control signal Vctl when the data latch circuit10binFIG.16Breads data, writes the same, and stores the same.FIG.16Cshows an example in which the word line WL1is accessed. When the word line WL2is accessed, a voltage relationship between the word lines WL1and WL2inFIG.16Cis inverted.

When the data latch circuit10breads the data stored in the nodes n1and n2via the transistor Q3, the word line WL1is set to the power supply voltage VDD and the word line WL2is set to the ground voltage VSS. Further, the bit line BL is pre-charged to the power supply voltage VDD in advance. Additionally, the control signal Vctl is set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7). Accordingly, the data stored in the nodes n1and n2are read in the bit line BL via the transistor Q3.

When the data latch circuit10bwrites the data to the nodes n1and n2via the transistor Q3, the word line WL1is set to the power supply voltage VDD, and the word line WL2is set to the ground voltage VSS (for example, 0 V). When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0 V). Further, the control signal Vctl is set to the power supply voltage VDD. Accordingly, the data of “0” is stored in the nodes n1and n2via the transistor Q3. Meanwhile, when the data to be written is 1, the bit line BL is set to the power supply voltage VDD.

When the data latch circuit10bstores the data in the nodes n1and n2, the word lines WL1and WL2are set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V), and the bit line BL is set to the power supply voltage VDD. Additionally, the control signal Vctl is set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V).

FIG.17is a layout diagram of the data latch circuit10baccording to the third embodiment. The third embodiment has a configuration in which a plurality of layers having different layer heights are stacked with each other, and a plurality of contacts configured to electrically connect the respective layers are provided. A hierarchical relationship between the respective layers forming the data latch circuit10binFIG.17is the same as that ofFIG.7.

In the layout arrangement inFIG.17, the first diffusion region D1, the second diffusion region D2, and the third diffusion region D3are located in the lowest layer. The first diffusion region D1and the second diffusion region D2are located apart from each other in the second direction Y. The third diffusion region D3is located apart from the first diffusion region D1and the second diffusion region D2in the first direction X.

The first gate layer G1, the second gate layer G2, the third gate layer G3, the fourth gate layer G4, and the fifth gate layer G5are located on the first to third diffusion regions D1to D3. The first to fifth gate layers G1to G5extend in the second direction Y, are located apart from each other in the first direction X, and are located at the same layer height.

The first gate layer G1is the word line WL1and is connected to the gate of the transistor Q3. The first gate layer G1overlaps the third diffusion region D3in the stacking direction. The second gate layer G2is the word line WL2and is connected to the gate of the transistor Q4. The second gate layer G2overlaps the third diffusion region D3in the stacking direction.

The third gate layer G3is connected to the gate of the transistor Q1. The fourth gate layer G4is connected to the gate of the transistor Q2. The fifth gate layer G5is connected to the gates of the transistors Q5and Q6.

The second to eleventh wiring layers WR2to WR11are located on the first to fifth gate layers G1to G5. The second to eleventh wiring layers WR2to WR11extend in the second direction Y, and are located apart from each other in the first direction X.

The second wiring layer WR2is a layer set to the power supply voltage (second reference voltage) VDD. The third wiring layer WR3is connected to the drain region of the transistor Q5in the first diffusion region D1. The fourth wiring layer WR4is connected to the drain region of the transistor Q6in the second diffusion region D2. The third wiring layer WR3and the fourth wiring layer WR4are located apart from each other in the second direction Y.

The fifth wiring layer WR5is a layer set to the ground voltage VSS. The sixth wiring layer WR6is connected to the gate of the transistor Q1. The seventh wiring layer WR7is connected to the source region of the transistor Q3in the third diffusion region D3. The eighth wiring layer WR8is connected to the first wiring layer WR1. The ninth wiring layer WR9is connected to the drain region of the second transistor in the third diffusion region D3. The tenth wiring layer WR10is connected to a twelfth wiring layer WR12. The eleventh wiring layer WR11is a layer set to the ground voltage VSS.

The first wiring layer WR1, the twelfth wiring layer WR12, and a thirteenth wiring layer WR13are located on the second to eleventh wiring layers WR2to WR11. The first wiring layer WR1, the twelfth wiring layer WR12, and the thirteenth wiring layer WR13extend in the first direction X and are located apart from each other in the second direction Y.

The first wiring layer WR1is the bit line BL and is connected to the eighth wiring layer WR8. The twelfth wiring layer WR12is connected to the third wiring layer WR3, the seventh wiring layer WR7, and the tenth wiring layer WR10. The thirteenth wiring layer WR13is connected to the fourth wiring layer WR4, the sixth wiring layer WR6, and the ninth wiring layer WR9.

FIG.18is a layout diagram in which a plurality of data latch circuits10bhaving the layout arrangement inFIG.17are located in the two-dimensional direction. InFIG.18, the plurality of data latch circuits10bare located line-symmetrically with respect to an axis extending in the second direction Y.

The layout arrangement shown inFIG.17is only an example, and various modifications thereof can be considered. For example, it is also possible to adopt a point-symmetrical layout arrangement.

As described above, the data latch circuit10baccording to the third embodiment is formed of six transistors Q1to Q6, thereby making it possible to reduce the circuit area thereof compared to the data latch circuit100according to the comparative example shown inFIG.2. Additionally, unlike in the first and second embodiments, it is not required to set the voltage of the word line to the voltage slightly lower than the power supply voltage VDD during the data storage period, and as such, the voltage control of the word line becomes easy.

Fourth Embodiment

Although the data latch circuit10baccording to the third embodiment includes two word lines WL1and WL2and one bit line BL, each of which is connected to a corresponding component thereof, the same may also have a configuration including one word line WL and two bit lines BL and bBL, each of which is connected to a corresponding component thereof.

FIG.19Ais a diagram showing characteristics of a data latch circuit10caccording to a fourth embodiment, andFIG.19Bis a circuit diagram of the data latch circuit10caccording to the fourth embodiment.

The data latch circuit10caccording to the fourth embodiment includes one word line WL and two bit lines BL and bBL, each of which is connected to a corresponding component thereof. The common word line WL is connected to the gates of the transistors Q3and Q4. The bit line BL is connected to the drain of the transistor Q3, and the bit line bBL is connected to the drain of the transistor Q4. The bit lines BL and bBL are mutually inverted logics. A connection relationship between other transistors Q1to Q4is the same as that ofFIGS.3A and3B.

FIG.19Cis a diagram showing the voltage of the word line WL, the bit lines BL and bBL, and the control signal Vctl when the data latch circuit10cinFIG.19Breads data, writes the same, and stores the same.

When the data latch circuit10creads the data stored in the nodes n1and n2, the word line WL is set to the power supply voltage VDD. The bit lines BL and bBL are pre-charged to the power supply voltage VDD in advance. Further, the control signal Vctl is set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V). Accordingly, the data stored in the nodes n1and n2are read in the bit lines BL and bBL via the transistors Q3and Q4in the inverted logic.

When the data latch circuit10cwrites the data to the nodes n1and n2, the word line WL is set to the power supply voltage VDD. When the data to be written is 0, the bit line BL is set to the ground voltage VSS (for example, 0 V) and the bit line bBL is set to the power supply voltage VDD. The control signal Vctl is set to the power supply voltage VDD. Accordingly, the transistors Q1and Q2perform the operation of storing the data of “0”. Meanwhile, when the data to be written is 1, the voltage levels of the bit lines BL and bBL are inverted to those inFIG.19C.

When the data latch circuit10cstores the data in the nodes n1and n2, the word line WL is set to the ground voltage VSS (for example, 0 V), and the bit lines BL and bBL are set to the power supply voltage VDD. Further, the control signal Vctl is set to voltage slightly lower than the power supply voltage VDD (for example, VDD×0.95−0.7 V).

FIG.20is a layout diagram of the data latch circuit10caccording to the fourth embodiment. A hierarchical relationship between the plurality of layers shown inFIG.20is the same as that ofFIG.7.

In the layout arrangement inFIG.20, the first diffusion region D1, the second diffusion region D2, and the third diffusion region D3are located in the lowest layer. The first diffusion region D1and the second diffusion region D2are located apart from each other in the second direction Y. The third diffusion region D3is located apart from the first diffusion region D1and the second diffusion region D2in the first direction X.

The first gate layer G1, the second gate layer G2, the third gate layer G3, the fourth gate layer G4, and the fifth gate layer G5are located on the first to third diffusion regions D1to D3. The first to fifth gate layers G1to G5extend in the second direction Y, are located apart from each other in the first direction X at the same layer height.

The first gate layer G1is the word line WL and is connected to the gate of the transistor Q3. The first gate layer G1overlaps the third diffusion region D3in the stacking direction. The second gate layer G2is also the word line WL and is connected to the gate of the transistor Q4. The second gate layer G2is the word line WL and overlaps the third diffusion region D3in the stacking direction. Since the first gate layer G1and the second gate layer G2have the same word line WL, the first gate layer G1and the second gate layer G2may be integrated into one gate layer.

The third gate layer G3is connected to the gate of the transistor Q1. The fourth gate layer G4is connected to the gate of the transistor Q2. The fifth gate layer G5is connected to the gates of the transistors Q5and Q6.

The third to twelfth wiring layers WR3to WR12are located on the first to fifth gate layers G1to G5. The third to twelfth wiring layers WR3to WR12extend in the second direction Y and are located apart from each other in the first direction X.

The third wiring layer WR3is a layer set to the power supply voltage VDD. The fourth wiring layer WR4is connected to the drain region of the transistor Q5in the first diffusion region D1. The fifth wiring layer WR5is connected to the drain region of the transistor Q6in the second diffusion region D2. The fourth wiring layer WR4and the fifth wiring layer WR5are located apart from each other in the second direction Y.

The sixth wiring layer WR6is connected to the source region of the transistor Q3in the third diffusion region D3. The seventh wiring layer WR7is connected to the drain region of the transistor Q3in the third diffusion region D3. The eighth wiring layer WR8is connected to the gate of the transistor Q1. The ninth wiring layer WR9is a layer set to the ground voltage VSS. The tenth wiring layer WR10is connected to the gate of the transistor Q2. The eleventh wiring layer WR11is connected to the drain region of the transistor Q4in the third diffusion region D3. The twelfth wiring layer WR12is connected to the source region of the transistor Q4in the third diffusion region D3.

The first wiring layer WR1, the second wiring layer WR2, the thirteenth wiring layer WR13, and a fourteenth wiring layer WR14are located on the third to twelfth wiring layers WR3to WR12. The first wiring layer WR1, the second wiring layer WR2, the thirteenth wiring layer WR13, and the fourteenth wiring layer WR14extend in the first direction X, and are located apart from each other in the second direction Y.

The first wiring layer WR1is the bit line BL and is connected to the sixth wiring layer WR6. The second wiring layer WR2is the bit line bBL and is connected to the twelfth wiring layer WR12. The thirteenth wiring layer WR13is connected to the fourth wiring layer WR4, the seventh wiring layer WR7, and the tenth wiring layer WR10. The fourteenth wiring layer WR14is connected to the fifth wiring layer WR5, the eighth wiring layer WR8, and the eleventh wiring layer WR11.

FIG.21is a layout diagram in which a plurality of data latch circuits10chaving the layout arrangement inFIG.20are located in the two-dimensional direction. The plurality of data latch circuits10cshown inFIG.21are located line-symmetrically with respect to an axis extending in the second direction Y.

The layout arrangement shown inFIG.21is only an example, and various modifications thereof can be considered. For example, it is possible to adopt a point-symmetrical layout arrangement.

As described above, since the data latch circuit10caccording to the fourth embodiment is formed of six transistors Q1to Q6, the same effect as that of the third embodiment can be obtained.

In addition, each of the above-described embodiments can be applied and used even in an environment at temperature of 50° C. or lower, room temperature, or temperature lower than the same by using immersion or the like. Each of the embodiments can also be applied and used in an extremely low temperature environment of −40° C. or lower to −196° C. of liquid nitrogen temperature.