Synthesis driven for minimum leakage with new standard cells

According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

TECHNICAL FIELD

The present disclosure generally relates to electronic circuits and, in particular embodiments, to current leakage reduction in integrated circuits.

BACKGROUND

A commonly used type of semiconductor device in digital electronics is an integrated circuit (IC) with complementary metal-oxide-semiconductor (CMOS) technology. Generally, CMOS allows for low power consumption, making it ideal for battery-powered applications and devices that involve low-power operation. In a CMOS IC, each logic gate is constructed using complementary pairs of n-type and p-type metal-oxide-semiconductor field effect transistors (MOSFETs).

Logic circuits are the building blocks of digital electronics and are used in a wide range of digital systems, such as microprocessors, memory chips, and other digital logic circuits. Logic circuits are electronic circuits that perform logic operations on one or more binary inputs to produce a binary output. Examples of logic circuits include logic gates (e.g., AND, OR, and NOT gates) and adders. These circuits can perform various operations, such as arithmetic and logic operations (e.g., addition, subtraction, multiplication, etc.).

Logic circuits can be implemented using CMOS technology, where current leakage is an important consideration, as it can lead to excess power consumption and reduced circuit reliability. Current leakage can result from subthreshold leakage, gate leakage, junction leakage, drain-induced barrier lower (DIBL), or the like.

Body biasing is a technique used to reduce current leakage in integrated circuits. In body biasing, an appropriate bias voltage is applied to the transistor, resulting in a change in the transistor's threshold voltage. In forward body biasing (FBB), the bias voltage is higher than the source voltage, causing an increase in the transistor's threshold voltage, making it harder for current to flow through the transistor when the transistor is in the OFF state, and, thus, reducing subthreshold leakage. In reverse body biasing (RBB), the bias voltage is less than the source voltage, causing a decrease in the transistor's threshold voltage, making it easier for current to flow through the transistor when it is in the ON state, and reducing the resistance and the voltage drop across the transistor and, thus, reducing junction leakage.

Although body biasing can be used in both n-channel and p-channel transistors, any reduction in current leakage from body biasing in the n-channel transistor is countered by the increased power consumption of the circuit. Further, the body biasing for the n-channel transistor requires a negative voltage source, which adds additional cost and footprint overhead to the circuit. A method, circuit, and device with reduced current leakage are, thus, desirable.

SUMMARY

Technical advantages are generally achieved by embodiments of this disclosure which describe current leakage reduction in integrated circuits.

A first aspect relates to an integrated circuit. The integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

A second aspect relates to a complementary metal-oxide-semiconductor (CMOS) logic gate. The CMOS logic gate includes a first p-channel transistor, a first n-channel transistor, a series p-channel transistor, and a shunt n-channel transistor. The first p-channel transistor is coupled between a voltage source terminal of the CMOS logic gate and an output terminal of the CMOS logic gate. The first p-channel transistor and the series p-channel transistor are configured to be body biased. The first n-channel transistor is coupled between the output terminal and reference ground. The series p-channel transistor is coupled between the output terminal and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal and reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

A third aspect relates to a device having an integrated circuit. The integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

Embodiments can be implemented in hardware, software, or in any combination thereof.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

This disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The particular embodiments are merely illustrative of specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments may be combined to form further embodiments unless noted otherwise.

Variations or modifications described in one of the embodiments may also apply to others. Further, various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

While the inventive aspects are described primarily in the context of complementary metal-oxide-semiconductor (CMOS), it should also be appreciated that these inventive aspects may also apply to other types of transistors. Further, the inventive concepts may be applied to other operating modes, not limited to a low-power mode or standby mode of a device, an integrated circuit, or a transistor.

Embodiments of this disclosure provide an improved cell architecture in integrated circuits that advantageously reduces current leakage and power consumption in low-power operating modes (e.g., sleep mode, standby mode, etc.) while maintaining the functional modes of the integrated circuit during full-power operating modes.

FIG.1illustrates a schematic of a conventional p-channel transistor102and a conventional n-channel transistor104of the metal-oxide-semiconductor type. Each transistor102,104includes a gate (G) terminal, a drain (D) terminal, and a source(S) terminal. P-channel transistor102is body biased using the bias voltage source VBBcoupled to the body of the p-channel transistor102. The source terminal of the p-channel transistor102and the drain terminal of the n-channel transistor104are coupled to a voltage source VDD. The drain terminal of the p-channel transistor and the source terminal of the n-channel transistor104are coupled to reference ground. In embodiments, the voltage of the bias voltage source VBBis greater than the voltage at the voltage source VDD.

The static power consumption (Pstatic), or leakage power, is caused by leakage current (Istatic) present in an active circuit. In a transistor coupled between voltage source VDDand reference ground, the leakage power can be represented as Pstatic=Istatic×VDD. Generally, the gate current leakage (Igate) and the subthreshold leakage current (Ioff) from the transistor in the OFF condition contribute to the leakage current (Istatic), or Istatic=Igate+Ioff. In an integrated circuit manufactured using 65 nanometers (nm) technology or greater (e.g., 90 nm, 110 nm, etc.), the contribution from the gate current leakage (Igate) is negligible and can be ignored. The subthreshold leakage current (Ioff) can be represented as

Ioff=I0×e-Vthμ⁢Vt,
where I0is a constant value that depends on various properties of the transistor (e.g., effective transistor width and length dimensions, gate oxide capacitance, carrier mobility), μ is the subthreshold swing coefficient, Vin is the threshold voltage, and Vtis the thermal voltage of the transistor.

An integrated circuit, such as an application-specific integrated circuit (ASIC), having logic gate(s) based on complementary metal-oxide-semiconductor (CMOS) technology includes one or more of each p-channel transistor102and n-channel transistor104. Generally, any combinational Boolean expression can be represented using universal gates of a logic NAND gate, a logic NOR gate, or a combination thereof.

For example, a single-input logic NOT gate can be represented using a two-input logic NAND gate or a two-input logic NOR gate with the two inputs tied together. As another example, a two-input logic AND gate can be represented using a combination of a two-input logic NAND gate and a single-input logic NOT gate, a pair of two-input logic NAND gates, or three two-input logic NOR gates. As yet another example, a logic OR gate can be represented using a combination of a two-input logic NOR gate and a single-input logic NOT gate or a combination of a two-input logic NOR gate and a two-input logic NAND gate.

Embodiments of this disclosure provide an improved architecture for the logic gate to reduce leakage current (Istatic) by implementing body biasing on the p-channel transistors and adding a series p-channel transistor to the pMOS cloud (i.e., the portion of the logic gate that includes one or more p-channel transistors) and a shunt n-channel transistor to the nMOS cloud (i.e., the portion of the logic gate that includes one or more n-channel transistors). The reduction of leakage current is advantageous to most integrated circuits, but especially so in, for example, ultra-low power ASICS.

Aspects of this disclosure, provide that the series p-channel transistor and the shunt n-channel transistor include a gate terminal coupled to a selectively controlled sleep input signal. The sleep input when at a logic high, disables the series p-channel transistor and enables the shunt n-channel transistor to advantageously reduce leakage current in the logic gate. The sleep input when at a logic low, enables the series p-channel transistor (i.e., pass-through) and disables the shunt n-channel transistor (i.e., OFF), such that the improved logic gate functionally operates identically to the conventional logic gate. These and further details are discussed in greater detail below.

FIG.2illustrates a schematic of a conventional CMOS single-input logic NOT (inverter) gate200with body biasing applied to the p-channel transistor202. A NOT gate reverses the input logic state. Logic NOT gate200includes a p-channel transistor202(e.g., pMOS) coupled in series with an n-channel transistor204(e.g., nMOS).

P-channel transistor202is coupled between the voltage source VDDand the output terminal (OUT). N-channel transistor204is coupled between the output terminal (OUT) and reference ground. The drain terminals of the p-channel transistor202and the n-channel transistor204are coupled to the output terminal (OUT). P-channel transistor202is body biased using the bias voltage source VBBcoupled to the body of the p-channel transistor202. In embodiments, the single-input of the logic NOT gate200is coupled to the gate terminals of p-channel transistor202and n-channel transistor204.

Table I illustrates the truth table for the single-input logic NOT gate200and corresponding current leakages in the different modes of operation.

When a logic low (e.g., “0”) input is applied to the logic NOT gate200, p-channel transistor202is ON and n-channel transistor204is OFF. Under this condition, the output logic (OUT) is a logic high (e.g., “1”)—the first row of Table I. The current leakage corresponding to this mode equals the gate current leakage (Igate_pMOS) from the p-channel transistors202and the subthreshold leakage current (Ioff_nMOS) contribution from the n-channel transistor204in the OFF condition, or Igate_pMOS+Ioff_nMOS.

When a logic high (e.g., “1”) input is applied to the logic NOT gate200, p-channel transistor202is OFF and n-channel transistor204is ON. Under this condition, the output logic (OUT) is a logic low (e.g., “0”)—the lowest row of Table I. The current leakage corresponding to this mode equals the gate current leakage (Igate_nMOS) from the n-channel transistors204and the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor202in the OFF condition, or Igate_nMos+Ioff_pMOS.

As the n-channel transistor204is not body biased, the subthreshold leakage current (Ioff_nMOS) contribution from the n-channel transistor204in the OFF condition is (exponentially) greater than the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor202in the OFF condition.

The third column in Table I summarizes the contributing factor to the current leakage in the logic NOT gate200in the different modes. In an integrated circuit manufactured using 65 nm technology or greater, the contribution from the gate current leakage is negligible. The fourth column in Table I, thus, summarizes the significant contributions to the current leakage in the Logic NOT gate200in the different modes. Embodiments of this disclosure provide an improved cell structure that reduces the subthreshold leakage current contribution from, for example, the n-channel transistor204in the OFF state.

FIG.3illustrates a schematic of a conventional CMOS two-input logic NAND (NOT-AND) gate300with body biasing applied to the p-channel transistors302,304. The output of the Logic NAND gate300is logic low (e.g., “0”) only when the inputs are logic high (e.g., “1”). Logic NAND gate300includes a pair of p-channel transistors302,304(e.g., pMOS) and a pair of n-channel transistors306,308(e.g., nMOS).

P-channel transistors302,304are coupled in parallel between the voltage source VDDand the output terminal (OUT). N-channel transistors306,308are coupled in series between the output terminal (OUT) and reference ground. P-channel transistors302,304are body biased using the bias voltage source VBBcoupled to the body of the p-channel transistors302,304.

In embodiments, the first input of the logic NAND gate300is coupled to the gate terminals of p-channel transistor302and n-channel transistor306. In embodiments, the second input of the logic NAND gate300is coupled to the gate terminals of p-channel transistor304and n-channel transistor308.

Table II illustrates the truth table for the two-input logic NAND gate300and corresponding current leakages in the different modes of operation.

When n-channel transistors306,308are OFF, and p-channel transistors302,304are ON, the output logic (OUT) is a logic high (i.e., “1”). This condition occurs when each input A and B is a logic low (i.e., “0”)—first row of Table II. The current leakage corresponding to this mode equals the gate current leakage (Igate_pMOS) from each of the p-channel transistors302,304and the subthreshold leakage current (Ioff_MOS) contribution from the n-channel transistor308in the OFF condition (i.e., no gate current leakage (Igate_nMos) from the n-channel transistors306,308), or 2×Igate_pMos+Ioff_nMOS. As the n-channel transistors306,308are not body biased, the subthreshold leakage current (Ioff_nMOS) contribution from the n-channel transistor306,308in the OFF condition is greater than the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor302,304in the OFF condition.

When one of the inputs is a logic high (i.e., “1”), and the other one of the inputs is a logic low (i.e., “0”), either (i) n-channel transistor306is OFF and p-channel transistor302is ON, or (ii) n-channel transistor308is OFF and p-channel transistor304is ON, the output logic (OUT) is a logic high (i.e., “1”)—second and third rows of Table II, respectively.

The current leakage corresponding to the first condition (i.e., n-channel transistor306is OFF and p-channel transistor302is ON) equals the gate current leakage (Igate_nMOS) of the n-channel transistor308, gate current leakage (Igate_pMOS) of the p-channel transistor302, and subthreshold leakage current (Ioff_nMOS) contribution from the n-channel transistor306in the OFF condition, or Igate_pMOS+Igate_nMos+Ioff_nMOS.

The current leakage corresponding to the second condition (i.e., n-channel transistor308is OFF and p-channel transistor304is ON) equals the gate current leakage (Igate_pMOS) of the p-channel transistor304and the subthreshold leakage current (Ioff_nMOS) contribution from the n-channel transistor308in the OFF condition (i.e., no gate current leakage (Igate_nMOS) from the n-channel transistors306,308), or Igate_pMOS+Ioff_nMOS.

When n-channel transistors306,308are “ON,” and p-channel transistors302,304are “OFF,” the output logic (OUT) is a logic low (i.e., “0”). This condition occurs when each input A and B is a logic high (i.e., “1”)—the lowest row of Table II. The current leakage corresponding to this mode equals the gate current leakage (Igate_nMOS) from each of the n-channel transistors306,308and the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistors302,304in the OFF condition. Thus, the total current leakage in this mode can be represented as 2×Igate_nMOS+2×Ioff_pMOS.

The fourth column in Table II summarizes the current leakage in the logic NAND gate300in the different modes. In an integrated circuit manufactured using 65 nm technology or greater, the contribution from the gate current leakage is negligible. The fifth column in Table II summarizes the significant contributions to the current leakage in the Logic NAND gate300in the different modes. Embodiments of this disclosure provide an improved cell structure that reduces the subthreshold leakage current contribution from, for example, the n-channel transistors306,308.

FIG.4illustrates a schematic of a conventional CMOS two-input logic NOR (NOT-OR) gate400with body biasing applied to the p-channel transistors402,404. The output of the Logic NOR gate400is logic high (e.g., “1”) only when the inputs are a logic low (e.g., “0”). Logic NOR gate400includes a pair of p-channel transistors402,404(e.g., pMOS) and a pair of n-channel transistors406,408(e.g., nMOS).

P-channel transistors402,404are coupled in series between the voltage source VDDand the output terminal (OUT). N-channel transistors406,408are coupled in parallel between the output terminal (OUT) and reference ground. P-channel transistors402,404are body biased using the bias voltage source VBBcoupled to the body of the p-channel transistors402,404.

In embodiments, the first input of the logic NAND gate300is coupled to the gate terminals of p-channel transistor402and n-channel transistor406. In embodiments, the second input of the logic NAND gate300is coupled to the gate terminals of p-channel transistor404and n-channel transistor408.

Table III illustrates the truth table for the two-input logic NOR gate400and corresponding current leakages in the different modes of operation.

When n-channel transistors406,408are OFF, and p-channel transistors402,404are ON, the output logic (OUT) is a logic high (i.e., “1”). This condition occurs when each input A and B is a logic low (i.e., “0”)—first row of Table III. The current leakage corresponding to this mode equals the gate current leakage (Igate_pMOS) from each of the p-channel transistors402,404and the subthreshold leakage current (Ioff_nMOS) contribution from each of n-channel transistor406,408in the OFF condition (i.e., no gate current leakage (Igate_nMOS) from the n-channel transistors406,408), or 2×Igate_pMos+2×Ioff_nMOS. As the n-channel transistors406,408are not body biased, the subthreshold leakage current (Ioff_nMOS) contribution from the n-channel transistor406,408in the OFF condition is greater than the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor402,404in the OFF condition.

When one of the inputs is a logic high (i.e., “1”), and the other one of the inputs is a logic low (i.e., “0”), either (i) n-channel transistor406is OFF and p-channel transistor402is ON, or (ii) n-channel transistor408is OFF and p-channel transistor404is ON, the output logic (OUT) is a logic low (i.e., “0”)—second and third rows of Table III, respectively.

The current leakage corresponding to the first condition (i.e., n-channel transistor406is OFF and p-channel transistor402is ON) equals the gate current leakage (Igate_nMOS) of the n-channel transistor408, gate current leakage (Igate_pMOS) of the p-channel transistor402, and the subthreshold leakage current (Ioff_pMos) contribution from the p-channel transistor404in the OFF condition, or Igate_pMOS+Igate_nMOS+Ioff_pMOS.

The current leakage corresponding to the second condition (i.e., n-channel transistor408is OFF and p-channel transistor404is ON) equals gate current leakage (Igate_nMOS) of the n-channel transistor406and the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor402in the OFF condition (i.e., no gate current leakage (Igate_pMOS) from the p-channel transistors402,404), or Igate_nMOS+Ioff_pMOS.

When n-channel transistors406,408are “ON,” and p-channel transistors402,404are “OFF,” the output logic (OUT) is a logic low (i.e., “0”). This condition occurs when each input A and B is a logic high (i.e., “1”)—the lowest row of Table III. The current leakage corresponding to this mode equals the gate current leakage (Igate_nMOS) from each of the n-channel transistors406,408and the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor404in the OFF condition. Thus, the total current leakage in this mode can be represented as 2×Igate_nMOS+Ioff_pMOS.

The fourth column in Table III summarizes the current leakage in the logic NOR gate400in the different modes. In an integrated circuit manufactured using 65 nm technology or greater, the contribution from the gate current leakage is negligible. The fifth column in Table III summarizes the significant contributions to the current leakage in the Logic NOR gate400in the different modes. Embodiments of this disclosure provide an improved cell structure that reduces the subthreshold leakage current contribution from, for example, the n-channel transistors406,408.

FIG.5illustrates a schematic of an embodiment CMOS logic NOT gate500. Logic NOT gate500includes p-channel transistors202,502(e.g., pMOS) and n-channel transistors204,504(e.g., nMOS). Logic NOT gate500may include additional components not shown. For example, logic NOT gate500may include resistors at one or more terminals of the various transistors. Logic NOT gate500may be coupled to other logic gates to produce other logic gate functions. Logic NOT gate500is similar to logic NOT gate200; however, logic NOT gate500includes an additional series p-channel transistor502with respect to the pMOS cloud (i.e., p-channel transistor202) and a shunt n-channel transistor504with respect to the nMOS cloud (i.e., n-channel transistor204). In embodiments, CMOS logic NOT gate500includes two input pins: one data input pin and one sleep input pin.

P-channel transistors202,502are coupled in series between the voltage source VDDand the output terminal (OUT). N-channel transistors204,504are coupled in parallel between the output terminal (OUT) and reference ground. The drain terminals of the p-channel transistors202,502and the n-channel transistors204,504are coupled to the output terminal (OUT). P-channel transistors202,502are body biased using the bias voltage source VBBcoupled to the body of the p-channel transistors202,502.

In embodiments, the input of the logic NOT gate500is coupled to the gate terminals of p-channel transistor202and the gate terminal of n-channel transistor204. In embodiments, the sleep input is coupled to the gate terminals of series p-channel transistor502and shunt n-channel transistor504.

Table IV illustrates the truth table for the logic NOT gate500and corresponding current leakages in the different modes of operation.

The truth table for the logic NOT gate500follows the truth table for the single-input logic NOT gate200in one mode of operation when the sleep input is set to logic low (e.g., “0”). As previously discussed, the significant contributing factor to the current leakage of the logic NOT gate200in this mode of operation is the subthreshold current leakage (Ioff_pMOS) contribution from the p-channel transistor202in the OFF condition. In logic NOT gate500, the significant contributing factor to the current leakage in this mode of operation is the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor502. As the series p-channel transistor502is a p-channel type, it can use the body biasing technique to reduce current leakage without significantly impacting the integrated circuit's power consumption. It is noted that functionally, logic NOT gate500operates similarly to logic NOT gate200in response to the sleep input being set to logic low.

In the second mode of operation, when the sleep input is set to logic high (e.g., “1”)—corresponding to the first row of Table IV—the output of logic NOT gate500differs from logic NOT gate200. As previously discussed, the significant contributing factor to the current leakage of logic NOT gate200, when the data input (i.e., A) is set to logic low, is the overall subthreshold leakage current (Ioff_nMOS) from the n-channel transistor204(i.e., Ioff_nMos), as it is in the OFF condition. In logic NOT gate500, however, when the data input is set to logic low and the sleep input is set to logic high, the gate terminals of the series p-channel transistor502and shunt n-channel transistor504are set to logic high (e.g., “1”), which results in the series p-channel transistor502turning OFF and shunt n-channel transistor504turning ON.

The turning ON of shunt n-channel transistor504, pulls the output of logic NOT gate500to a logic low (e.g., “0”), which is considered incorrect or corrupt (denoted in Table IV as “X”). Advantageously, however, the significant contributing factor to the current leakage in this mode of operation becomes the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistors202,502, which are in the OFF condition (i.e., 2×Ioff_pMos). As the p-channel transistors202,502take advantage of the body biasing technique, the subthreshold leakage current in this mode of operation is minimized (with respect to the same mode in logic NOR gate200) without significantly impacting power consumption.

FIG.6illustrates a schematic of an embodiment CMOS logic NAND gate600. Logic NAND gate600includes three p-channel transistors302,304,602(e.g., pMOS) and three n-channel transistors306,308,604(e.g., nMOS). Logic NAND gate600may include additional components not shown. For example, Logic NAND gate600may include resistors at one or more terminals of the various transistors. Logic NAND gate600may be coupled to other logic gates to produce other types of logic gate functions. Logic NAND gate600is similar to the logic NAND gate300; however, logic NAND gate600includes an additional series p-channel transistor602with respect to the pMOS cloud (i.e., p-channel transistors302,304) and a shunt n-channel transistor604with respect to the nMOS cloud (i.e., n-channel transistors306,308). In embodiments, CMOS logic NAND gate600includes three input pins: two data input pins and one sleep input pin.

P-channel transistors302,304are coupled in parallel between the voltage source VDDand series p-channel transistor702. N-channel transistors306,308are coupled in series between the output terminal and reference ground. Shunt n-channel transistor604is coupled between the output terminal and reference ground. P-channel transistors302,304,602are body biased using the bias voltage source VBBcoupled to the body of the p-channel transistors302,304,602. The drain terminals of the series p-channel transistor602and shunt n-channel transistor604and n-channel transistor306are coupled to the output terminal (OUT).

In embodiments, the first input of the logic NAND gate600is coupled to the gate terminals of p-channel transistor302and n-channel transistor306. In embodiments, the second input of the logic NAND gate600is coupled to the gate terminals of p-channel transistor304and n-channel transistor308. In embodiments, the sleep input is coupled to the gate terminals of series p-channel transistor602and shunt n-channel transistor604.

Table V illustrates the truth table for the logic NAND gate600and corresponding current leakages in the different modes of operation.

The truth table for the logic NAND gate600follows the truth table for the two-input logic NAND gate300in one mode of operation when the sleep input is set to logic low (e.g., “0”). As previously discussed, the corresponding significant contributing factor to the current leakage of the logic NAND gate300is the subthreshold current leakage (Ioff_pMOS) contribution from the p-channel transistors302,304when they are in the OFF condition. In logic NAND gate600, the significant contributing factor to the corresponding current leakage is the subthreshold current leakage (Ioff_pMOS) contribution from the p-channel transistors302,304,602.

As the p-channel transistors302,304,602are p-channel type, they can take advantage of the body biasing technique to reduce subthreshold leakage current without significantly impacting the integrated circuit's power consumption. It is noted that functionally, logic NAND gate600operates similarly to logic NAND gate300in response to the sleep input being set to logic low.

In the other three modes of operation, when the sleep input is set to logic high (e.g., “1”)—corresponding to the first three rows of Table V—the output of logic NAND gate600differs from logic NAND gate300. As previously discussed, the corresponding significant contributing factor to the current leakage of logic NAND gate300is the subthreshold leakage current (Ioff_nMos) from the n-channel transistor306or the n-channel transistor308(i.e., Ioff_nMos), when they are in the OFF condition. In logic NAND gate600, however, when the sleep input is set to logic high, the gate terminals of the series p-channel transistor602and shunt n-channel transistor604are set to logic high (e.g., “1”), which results in the p-channel transistor602turning OFF and shunt n-channel transistor604turning ON.

The turning ON of shunt n-channel transistor604, pulls the output of logic NAND gate600to a logic low (e.g., “0”), which is considered incorrect or corrupt (denoted in Table V as “X”). Advantageously, however, the significant contributing factor to the current leakage in these modes of operation becomes the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistors302,702or p-channel transistors304,602, which are in the OFF condition (i.e., 2×Ioff_pMos). As the p-channel transistors302,304, and602take advantage of the body biasing technique, the subthreshold leakage current in this mode of operation is minimized (with respect to the same mode in logic NAND gate300) without significantly impacting power consumption.

FIG.7illustrates a schematic of an embodiment CMOS logic NOR gate700. Logic NOR gate700includes three p-channel transistors402,404,702(e.g., pMOS) and three n-channel transistors406,408,704(e.g., nMOS). Logic NOR gate700may include additional components not shown. For example, Logic NOR gate700may include resistors at one or more terminals of the various transistors. Logic NOR gate700may be coupled to other logic gates to produce other types of logic gate functions. Logic NOR gate700is similar to the logic NOR gate400; however, logic NOR gate700includes an additional series p-channel transistor702with respect to the pMOS cloud (i.e., p-channel transistors402,404) and a shunt n-channel transistor704with respect to the nMOS cloud (i.e., n-channel transistors406,408). In embodiments, CMOS logic NOR gate700includes three input pins: two data input pins and one sleep input pin.

P-channel transistors402,404,702are coupled in series between the voltage source VDDand the output terminal (OUT). N-channel transistors406,408,704are coupled in parallel between the output terminal (OUT) and reference ground. P-channel transistors402,404,702are body biased using the bias voltage source VBBcoupled to the body of p-channel transistors402,404,702. The drain terminals of the n-channel transistors406,408,704and the series p-channel transistor702are coupled to the output terminal (OUT). P-channel transistor404is coupled in series between the p-channel transistor402and the series p-channel transistor702. p-channel transistor402is coupled in series between the p-channel transistor404and the voltage source VDD.

In embodiments, the first input of the logic NOR gate700is coupled to the gate terminals of p-channel transistor402and n-channel transistor406. In embodiments, the second input of the logic NOR gate700is coupled to the gate terminals of p-channel transistor404and n-channel transistor408. In embodiments, the sleep input is coupled to the gate terminals of the series p-channel transistor702and shunt n-channel transistor704.

Table VI illustrates the truth table for the logic NOR gate700and corresponding current leakages in the different modes of operation.

The truth table for the logic NOR gate700follows the truth table for the two-input logic NOR gate400in three modes of operation when the sleep input is set to logic low (e.g., “O”). As previously discussed, the corresponding significant contributing factor to the current leakage of the logic NOR gate400is the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor402or the p-channel transistor404when they are in the OFF condition. In logic NOR gate700, the corresponding significant contributing factor to the current leakage is the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistor702—the p-channel transistors402,404have a smaller drain to source voltage (VDS). As the series p-channel transistor702is a p-channel type, similar to the p-channel transistors402,404in logic NOR gate400, it can use the body biasing technique to reduce current leakage without significantly impacting the integrated circuit's power consumption. It is noted that functionally, logic NOR gate700operates similarly to logic NOR gate400in response to the sleep input being set to logic low.

In one mode of operation, when the sleep input is set to logic high (e.g., “1”)—corresponding to the first row of Table VI—the output of logic NOR gate700differs from logic NOR gate400. As previously discussed, the corresponding significant contributing factor to the current leakage of logic NOR gate400is the overall subthreshold leakage current (Ioff_nMOS) from the n-channel transistors406,408(i.e., 2×Ioff_nMos), as they are in the OFF condition. In logic NOR gate700, however, when the sleep input is set to logic high, the gate terminals of the series p-channel transistor702and shunt n-channel transistor704are set to logic high (e.g., “1”), which results in the p-channel transistor702turning OFF and shunt n-channel transistor704turning ON.

The turning ON of shunt n-channel transistor704, pulls the output of logic NOR gate700to a logic low (e.g., “0”), which is considered incorrect or corrupt (denoted in Table VI as “X”). Advantageously, however, the significant contributing factor to the current leakage in this mode of operation becomes the subthreshold leakage current (Ioff_pMOS) contribution from the p-channel transistors402,404, and702, which are in the OFF condition (i.e., 3×Ioff_pMos). As the p-channel transistors402,404, and702take advantage of the body biasing technique, the current leakage in this mode of operation is minimized (with respect to the same mode in logic NOR gate400) without significantly impacting power consumption.

FIG.8illustrates a schematic of an embodiment generic CMOS logic gate800having a pMOS cloud sub-circuit802coupled with a series p-channel transistor806and an nMOS cloud sub-circuit804coupled with a shunt n-channel transistor808, which may (or may not) be arranged as shown. CMOS logic gate800may include additional components, such as one or more resistors at one or more terminals of the CMOS logic gate800. The gate terminals of the series p-channel transistor806and shunt n-channel transistor808are coupled to the sleep input of the CMOS logic gate800. In embodiments, the sleep input of the CMOS logic gate800is configured to receive a sleep signal from, for example, a processor or a controller. In embodiments, the gate terminals of the series p-channel transistor806and shunt n-channel transistor808are configured to only receive the sleep signal.

CMOS logic gate800is a generic representation of a CMOS logic gate, where the pMOS cloud sub-circuit802represents the portion of the logic gate that includes one or more p-channel transistors and nMOS cloud sub-circuit804represents the portion of the logic gate that includes one or more n-channel transistors.

For example, p-channel transistor202and n-channel transistor204in logic NOT gate200are represented, respectively, by pMOS cloud sub-circuit802and nMOS cloud sub-circuit804in logic gate800. As another example, p-channel transistors302,304—arranged in parallel between voltage source VDDand the output terminal—and n-channel transistors306,306—arranged in series between the output terminal and reference ground in logic NAND gate300are represented, respectively, by pMOS cloud sub-circuit802and nMOS cloud sub-circuit804in logic gate800. As yet another example, p-channel transistors402,404—arranged in series between voltage source VDDand the output terminal—and n-channel transistors406,406—arranged in parallel between the output terminal and reference ground in logic NOR gate400are represented, respectively, by pMOS cloud sub-circuit802and nMOS cloud sub-circuit804in logic gate800.

It should be appreciated that the series p-channel transistor806in CMOS logic gate800may represent the series p-channel transistor502in logic NOT gate500, the series p-channel transistor602in logic NAND gate600, or the series p-channel transistor702in logic NOR gate700. It should be appreciated that the shunt n-channel transistor808in CMOS logic gate800may represent the shunt n-channel transistor504in logic NOT gate500, the shunt n-channel transistor604in logic NAND gate600, or the shunt n-channel transistor704in logic NOR gate700.

CMOS logic gate800is arranged such that when the sleep signal is set to logic low, the CMOS logic gate800functionally operates as if the series p-channel transistor806(ON) and shunt n-channel transistor808(OFF) are not part of CMOS logic gate800. CMOS logic gate800is configured such that when the sleep signal is set to logic low, the only leakage current contribution is from the subthreshold current leakage from the pMOS cloud sub-circuit802.

Further, CMOS logic gate800is arranged such that when the sleep signal is to logic high, (i) the shunt n-channel transistor808(ON) drives the output of the CMOS logic gate800to logic low (i.e., “0”) and (ii) the series p-channel transistor806(OFF) effectively blocks the electrical path from the voltage source VDDto the output terminal.

CMOS logic gate800, advantageously uses the sleep signal to remove the subthreshold leakage current contributions from n-channel transistor(s) of the nMOS cloud sub-circuit804when the n-channel transistor(s) is in the OFF condition (i.e., setting the sleep signal to logic high). Thus, by selectively enabling the sleep signal in CMOS logic gate800, the current leakage in CMOS logic gate800can be limited to only the subthreshold leakage current (Ioff_pMOS) contributions from the p-channel transistor(s) in every operating mode of CMOS logic gate800.

In embodiments, pMOS cloud sub-circuit802includes one or more p-channel transistors arranged in series, parallel, or a combinational arrangement. In embodiments, each p-channel transistor of the pMOS cloud sub-circuit802and the series p-channel transistor806are body biased using the bias voltage source VBBcoupled to the body of the series p-channel transistor806. In embodiments, nMOS cloud sub-circuit804includes one or more n-channel transistors arranged in series, parallel, or a combinational arrangement.

FIG.9illustrates a schematic of an embodiment CMOS logic AND gate900, which includes logic NOT gate500coupled to the output of the logic NAND gate600, which may (or may not) be arranged as shown. Logic AND gate900may include additional components not shown. The logic AND gate900can be represented as the inverted output (using the logic NOT gate500) of the logic NAND gate600. The output of logic NOT gate500is the output of the logic AND gate900. The input to the logic NAND gate600is the input of the logic AND gate900.

Not shown, logic AND gate900can be represented as three logic NOR gates700where the first input to the third logic NOR gate is coupled to the output of the first logic NOR gate, the second input to the third logic NOR gate is coupled to the output of the second logic NOR gate, the inputs of the first logic NOR gate are coupled to each other and is the first input of the logic AND gate, the inputs of the second NOR gate are coupled to each other and is the second input of the logic AND gate, and the output of the third logic NOR gate is the output of the logic AND gate.

Table VII illustrates the truth table for the two-input logic AND gate900and corresponding current leakages in response to the sleep signal at the gate inputs of the series p-channel transistors502,602and shunt n-channel transistors504,604being asserted (e.g., logic level high).

As shown, when the sleep signal is asserted, the output of the logic AND gate900is a logic low (i.e., “0”), regardless of the logic level of the data inputs (A, B). Although a logic low is a wrong output for the last row of the truth table (i.e., logic high for both inputs should be a logic high output), the output of the logic AND gate900in sleep mode is irrelevant, as further discussed below (e.g., the output of the multiplexer1104is set to a desired output value during sleep mode). Advantageously, during sleep mode, there is no subthreshold leakage current contribution from an n-channel transistor of the logic AND gate900, and the only contribution is from the subthreshold leakage currents from the p-channel transistors, which are body biased.

In embodiments, in response to the sleep signal being de-asserted (e.g., logic low at the gate inputs of the series p-channel transistors502,602and shunt n-channel transistors504,604), the CMOS logic AND gate900operates similar to the conventional AND gate.

FIG.10illustrates a schematic of an embodiment CMOS logic OR gate1000, which includes logic NOT gate500coupled to the output of the logic NOR gate700, which may (or may not) be arranged as shown. Logic OR gate1000may include additional components not shown. The logic OR gate1000can be represented as the inverted output (using the logic NOT gate500) of the logic NOR gate700. The output of logic NOT gate500is the output of the logic OR gate1000. The input to the logic NOR gate700is the input of the logic OR gate1000.

Table VIII illustrates the truth table for the two-input logic OR gate1000and corresponding current leakages in response to the sleep signal at the gate inputs of the series p-channel transistors502,702and shunt n-channel transistors504,704being asserted (e.g., logic level high).

As shown, when the sleep signal is asserted, the output of the logic OR gate1000is a logic low (i.e., “0”), regardless of the logic level of the data inputs (A, B). Although a logic low is a wrong output for the first row of the truth table (i.e., logic low for both inputs should be a logic high output), the output of the logic OR gate1000in sleep mode is irrelevant, as further discussed below (e.g., the output of the multiplexer1104is set to a desired output value during sleep mode). Advantageously, during sleep mode, there is no subthreshold leakage current contribution from an n-channel transistor of the logic OR gate1000, and the only contribution is from the subthreshold leakage currents from the p-channel transistors, which are body biased.

In embodiments, in response to the sleep signal being de-asserted (e.g., logic low at the gate inputs of the series p-channel transistors502,702and shunt n-channel transistors504,704), the CMOS logic OR gate1000operates similar to the conventional OR gate.

FIG.11illustrates a schematic of an embodiment integrated circuit1100. The integrated circuit1100includes one or more logic gates1102, a multiplexer1104, and a flip-flop1106, which may (or may not) be arranged as shown. The integrated circuit1100may include additional components not shown, such as a memory or a processor. In embodiments, the logic gates1102includes one or more of the logic NAND gate600, logic NOR gate700, logic NOT gate500, or a combination thereof. In embodiments, the logic gates1102includes one or more of the CMOS logic gate800.

The output of the flip-flop1106is coupled to the sleep input terminal of one or more logic gates1102and the select terminal of the multiplexer1104. In embodiments, the output of the logic gates1102is coupled to the first input of the multiplexer1104. In embodiments, the second input terminal of the multiplexer1104is coupled to a controller. The controller may be internal or external to the integrated circuit. In embodiments, the controller may be a component of a device that includes the integrated circuit1100. The controller is configured to provide a desired output value to the second input of the multiplexer1104.

The multiplexer is configured to set an output signal at the output terminal of the multiplexer1104to a signal at the first input terminal (i.e., coupled to the output of the logic gates1102) in response to the sleep signal being de-asserted (i.e., sleep signal set to a logic low). Further, the multiplexer1104is configured to set the output signal at the output terminal of the multiplexer to a signal at the second input terminal (i.e., coupled to the controller) of the multiplexer1104in response to the sleep signal being asserted (i.e., sleep signal set to a logic high). In embodiments, the output of the multiplexer1104is the output terminal of the integrated circuit1100.

The flip-flop1106provides a logic high signal to the inputs of each logic gate of the logic gates1102and the select terminal of the multiplexer1104to enter sleep mode. During sleep mode, the only leakage current contributions from the logic gates1102are the subthreshold leakage currents of the OFF p-channel transistors of the logic gates1102, which are body biased. Thus, in sleep mode, advantageously, there are no subthreshold leakage current contributions from the OFF n-channel transistors of the logic gates1102, which are not body biased. Further, as the sleep mode is only entered when there is no contribution from the subthreshold current leakage of the OFF n-channel transistors of the logic gates1102, in either sleep mode or non-sleep mode, there is no subthreshold current leakage contribution from the OFF n-channel transistors of the logic gates1102.

In sleep mode, a-priori the desired output to be provided at the second input terminal of the multiplexer1104is known, for example, based on the design specification requirements of the integrated circuit. In embodiments, the desired output value is either hardwired to reference ground (i.e., logic level low) or voltage source VDD(i.e., logic level high). In sleep mode, corresponding to the sleep signal being asserted (e.g., logic level high), the desired output value is provided at the output of the multiplexer1104. In embodiments, a controller coupled to the second input terminal of the multiplexer1104provides a desired output for the integrated circuit and allows a bypass mode for the logic gates1102—bypassing the corrupted output logic of the logic gates1102during sleep mode.

In embodiments, the sleep signal is asserted (e.g., set to logic level high) in response to the integrated circuit1100(e.g., module) or device having the integrated circuit1100being placed in sleep mode. A device with integrated circuit1100may include a sleep mode operation corresponding to a low power mode. During the low power mode, the power used by the device is reduced by disabling one or more features typically available during full power mode. For example, a mobile device may disable certain features in low power mode to preserve battery power in response to reaching a threshold battery percentage. In embodiments, the integrated circuit1100may no longer receive a clock signal in sleep mode. In embodiments, the integrated circuit1100may be powered down in sleep mode. In embodiments, the sleep signal is asserted in response to the device or integrated circuit1100being in sleep mode to reduce the leakage current and preserve power stored, for example, in a battery of the device. In embodiments, the sleep mode is enabled by the controller (e.g., processor1202), which results in the sleep signal being asserted. In embodiments, the controller enables the sleep mode based on the desired operating state of the integrated circuit1100or device1200.

As an exemplary embodiment, after the controller completes a routine, there may be a delay of 10 milliseconds (ms) until new input data is received or collected. The controller can enable sleep mode and assert the sleep signal to minimize the power consumption (i.e., leakage current) by the logic gates1102during this period. At the end of the 10 ms period, the controller is ready to run the next routine, disables sleep mode, and de-asserts the sleep signal.

For example, in an embodiment where the output of the multiplexer1104is specified to be OUT0, OUT1, where OUT0and OUT1are equal to the logic level high (non-limiting) in sleep mode, the desired output value is hardwired to voltage source VDD(i.e., logic level high).

As another example, during sleep mode, the controller determines that the desired output (i.e., OUT0, OUT1, . . . , OUTn) is ten consecutive logic high signals (non-limiting), and the controller provides this value to the second input of the multiplexer1104, which is the corresponding output signal of the multiplexer1104.

It should be appreciated that, in embodiments, the integrated circuit may include more than one combination of the logic gates1102, the multiplexer1104, and the flip-flop1106. For example, the integrated circuit1100may include an associated multiplexer1104for each logic gate of the logic gates1102.

FIG.12illustrates a block diagram of an embodiment processing system1200. As shown, the processing system1200includes a processor1202, a memory1204, an interface1206, and an integrated circuit1210, which may (or may not) be arranged as shown. Although the processing system1200is shown to have one of each component (i.e., the processor1202, the memory1204, the interface1206, and the integrated circuit1210), the number of components is not limiting and greater numbers are similarly contemplated in other embodiments. In such embodiments, the task performed by the component disclosed herein may be spread through these additional components.

The integrated circuit1210includes one or more logic gates1208—although the processing system1200is shown with three logic gates1208, the number of logic gates1208is non-limiting, and fewer or greater numbers can be included. The processing system1200may include additional components not depicted, such as long-term storage (e.g., non-volatile memory, etc.), measurement devices, feedback circuits, multiplexers, flip-flops, active and passive components, or the like.

Processor1202may be any component or collection of components adapted to perform computations or other processing-related tasks, as disclosed herein. Memory1204may be any component or collection of components adapted to store programming or instructions for execution by processor1202. In an embodiment, memory1204includes a non-transitory computer-readable medium. Interface1206may be any component or collection of components that allow the processor1202to communicate with other devices/components or a user. For example, interface1206may be adapted to allow a user or device (e.g., personal computer (PC), etc.) to interact/communicate with the processing system1200.

FIG.13illustrates a flow chart of an embodiment method1300for enabling sleep mode and asserting the sleep signal at the sleep input terminal (i.e., the gate of the series p-channel transistor and the shunt n-channel transistor, and the select terminal of the multiplexer). In embodiments, the processor1202is configured to drive one or more logic gates1208of the integrated circuit1210in the device1200into the different power modes. In embodiments, a controller or a power management unit (PMU) sets the different power modes. In embodiments, the integrated circuit1210may include multiple power domains, such as a RUN mode, a low-power, and a standby (or always-on) power domain.

The device1200may switch between the different power domains to achieve energy efficiency. The standby power domain has very low power consumption and remains ON after the device1200is powered up. This allows the device1200to enter standby mode until, for example, a user's input triggers an end to the standby mode. The low-power power domain allows the device1200to operate in low-power mode—the low-power power domain is OFF in the standby mode. This allows the device1200to perform certain functions at reduced power consumption. The RUN mode power domain is typically used for performing full-power operations when the maximum performance of the device1200is required. The RUN power domain is OFF in the low-power and standby modes.

At step1302, one or more logic gates1208begin running a routine. In embodiments, the device1200is in an idle state at step1302. In embodiments, the processor1202is configured to set the corresponding logic gates into sleep mode by asserting the sleep signal at the gate inputs of the associated series p-channel transistor806and shunt n-channel transistor808.

At step1304, in response to a delay in receiving the data inputs before processing the routine, processor1202sets the corresponding logic gates into sleep mode by asserting the sleep signal at the gate inputs of the associated series p-channel transistor806and shunt n-channel transistor808. During this step, the multiplexer1104is configured to receive the asserted sleep signal, and the output of the multiplexer1104is set to the desired output value, which is, for example, hardwired to the second input of the multiplexer1104.

At step1306, after the delay period, the data inputs are ready at the corresponding logic gates. The processor1202sets the corresponding logic gates out of sleep mode and into, for example, full power mode, and the sleep signal at the gate inputs of the associated series p-channel transistor806and shunt n-channel transistor808are de-asserted.

At step1308, at the conclusion of the routine, in embodiments, the processor1202sets the corresponding logic gates into sleep mode by asserting the sleep signal at the gate inputs of the associated series p-channel transistor806and shunt n-channel transistor808. In embodiments, the processor1202sets the device1200into an idle state. In embodiments, at the conclusion of the routine at step1308, the one or more logic gates1208being the processing of a next routine at step1302.

It is noted that all steps outlined in the flow chart are not necessarily required and can be optional. Further, changes to the arrangement of the steps, removal of one or more steps and path connections, and addition of steps and path connections are similarly contemplated.

A first aspect relates to an integrated circuit. The integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

In a first implementation form of the integrated circuit, according to the first aspect as such, the first p-channel transistor and the series p-channel transistor are coupled in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate. The first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

In a second implementation form of the integrated circuit, according to the first aspect as such or any preceding implementation form of the first aspect, a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor.

In a third implementation form of the integrated circuit, according to the first aspect as such or any preceding implementation form of the first aspect, the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor. The second p-channel transistor is configurable to be body biased. The first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate. The first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

In a fourth implementation form of the integrated circuit, according to the first aspect as such or any preceding implementation form of the first aspect, the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor. The second p-channel transistor is configurable to be body biased. The first p-channel transistor and the second p-channel transistor are arranged in parallel between a voltage source terminal of the CMOS logic gate and the series p-channel transistor. The first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

In a fifth implementation form of the integrated circuit, according to the first aspect as such or any preceding implementation form of the first aspect, the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof.

In a sixth implementation form of the integrated circuit, according to the first aspect as such or any preceding implementation form of the first aspect, the integrated circuit includes a multiplexer with a first input terminal, a second input terminal, a select terminal, and an output terminal. The first input terminal is coupled to the output terminal of the CMOS logic gate, the second input terminal is couplable to a controller, and the select terminal is coupled to the sleep signal. The multiplexer is configured to set an output signal at the output terminal of the multiplexer to a signal at the first input terminal in response to the sleep signal being de-asserted and set an output signal at the output terminal of the multiplexer to a signal at the second input terminal in response to the sleep signal being asserted. The signal at the second input terminal is a desired output value.

A second aspect relates to a complementary metal-oxide-semiconductor (CMOS) logic gate. The CMOS logic gate includes a first p-channel transistor, a first n-channel transistor, a series p-channel transistor, and a shunt n-channel transistor. The first p-channel transistor is coupled between a voltage source terminal of the CMOS logic gate and an output terminal of the CMOS logic gate. The first p-channel transistor and the series p-channel transistor are configured to be body biased. The first n-channel transistor is coupled between the output terminal and reference ground. The series p-channel transistor is coupled between the output terminal and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal and reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

In a first implementation form of the CMOS logic gate, according to the second aspect as such, the first p-channel transistor and the series p-channel transistor are coupled in series between the voltage source terminal and the output terminal. The first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground.

In a second implementation form of the CMOS logic gate, according to the second aspect as such or any preceding implementation form of the second aspect, a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor.

In a third implementation form of the CMOS logic gate, according to the second aspect as such or any preceding implementation form of the second aspect, the CMOS logic gate further includes a second p-channel transistor and a second n-channel transistor. The second p-channel transistor is configured to be body biased. The first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between the voltage source terminal and the output terminal. The first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground.

In a fourth implementation form of the CMOS logic gate, according to the second aspect as such or any preceding implementation form of the second aspect, the CMOS logic gate further includes a second p-channel transistor and a second n-channel transistor. The second p-channel transistor is configured to be body biased. The first p-channel transistor and the second p-channel transistor are arranged in parallel between the voltage source terminal and the series p-channel transistor. The first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground.

In a fifth implementation form of the CMOS logic gate, according to the second aspect as such or any preceding implementation form of the second aspect, the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof.

A third aspect relates to a device having an integrated circuit. The integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

In a first implementation form of the device, according to the third aspect as such, the first p-channel transistor and the series p-channel transistor are coupled in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate. The first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

In a second implementation form of the device, according to the third aspect as such or any preceding implementation form of the third aspect, a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor.

In a third implementation form of the device, according to the third aspect as such or any preceding implementation form of the third aspect, the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor. The second p-channel transistor is configurable to be body biased. The first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate. The first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

In a fourth implementation form of the device, according to the third aspect as such or any preceding implementation form of the third aspect, the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor. The second p-channel transistor is configurable to be body biased. The first p-channel transistor and the second p-channel transistor are arranged in parallel between a voltage source terminal of the CMOS logic gate and the series p-channel transistor. The first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground.

In a fifth implementation form of the device, according to the third aspect as such or any preceding implementation form of the third aspect, the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof.

In a sixth implementation form of the device, according to the third aspect as such or any preceding implementation form of the third aspect, the integrated circuit further includes a multiplexer having a first input terminal, a second input terminal, a select terminal, and an output terminal. The first input terminal is coupled to the output terminal of the CMOS logic gate, the second input terminal is couplable to a controller, and the select terminal is coupled to the sleep signal. The multiplexer is configured to set an output signal at the output terminal of the multiplexer to a signal at the first input terminal in response to the sleep signal being de-asserted and set an output signal at the output terminal of the multiplexer to a signal at the second input terminal in response to the sleep signal being asserted, wherein the signal at the second input terminal is a desired output value.

The specification and drawings are, accordingly, to be regarded simply as an illustration of the disclosure as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.