Semiconductor MOS transistor device

A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

TECHNICAL FIELD

The present invention relates to a semiconductor device comprising a MOS transistor, the MOS transistor having a drain region and a source region, both of a second conductivity type, disposed spaced apart from each other on a surface of a semiconductor substrate of a first conductivity type, a gate insulating film formed on the semiconductor substrate between the source region and the drain region, and a gate electrode formed on the gate insulating film, wherein the semiconductor substrate between the source region and the drain region provides a channel region. In particular, the invention relates to LOCOS offset transistors.

BACKGROUND ART

As the markets for cell phones and portable gaming machines have grown, there is a growing need for liquid crystal driving circuits. To drive liquid crystal requires high voltages for back-lighting power supply purposes, for example. Consequently, LSI implementation of liquid crystal driving circuitry requires a high withstand voltage transistor. Typical examples of high withstand voltage transistors of the CMOS (Complementary Metal Oxide Semiconductor) type include a LOCOS (LOCal Oxidation of Silicon) offset transistor (see, e.g., Patent Document 1) comprising a MOS transistor, and a masked-LDD (Lightly Doped Drain) transistor (see, e.g., Patent Document 2).

The LOCOS offset transistor is described below.

FIG. 32shows a cross section of a conventional LOCOS offset transistor.

On a surface of a P-type semiconductor substrate1, an N-drain region3dand an N-source region3sare formed spaced apart from each other. The semiconductor substrate1between the N-drain region3dand the N-source region3sprovides a channel region5. On the semiconductor substrate1between the N-drain region3dand the N-source region3s, a gate insulating film51is formed. On top of the gate insulating film51, a gate electrode53is formed. While not shown in the drawing, in the regions of the semiconductor substrate1where the N-drain region3d, the N-source region3s, and the channel region5are formed, a P-type well region is formed.

On the surface side of the N-drain region3d, an N+ drain region11dis formed spaced apart from the edges of the N-drain region3d. On the surface side of the N-source region3s, an N+ source region11sis formed spaced apart from the edges of the N-source region3s.

On the surface of the semiconductor substrate1, LOCOS oxide films15are formed for defining a region for the formation of a LOCOS offset transistor. The LOCOS oxide films15have a film thickness greater than the gate insulating film51. The LOCOS oxide films15are also formed on the surface of the N-drain region3dbetween an edge of the N-drain region3don the side of the channel region5and the N+ drain region11d, and on the surface of the N-source region3sbetween an edge of the N-source region3son the side of the channel region5and the N+ source region11s. The edges of the gate electrode53are disposed over the LOCOS oxide films15.

On the semiconductor substrate1, a silicon oxide insulating film17is formed covering the gate electrode53, the N+ drain region11d, the N+ source region11s, and the LOCOS oxide films15. On the silicon oxide insulating film17, a gate wiring19g, a drain wiring19d, and a source wiring19sare formed of a metal material. Via connection holes21formed in the silicon oxide insulating film17, the gate wiring19gis connected to the gate electrode53; the drain wiring19dis connected to the N+ drain region11d; and the source wiring19sis connected to the N+ source region11s.

With reference toFIGS. 32 through 37, a process of manufacturing the conventional LOCOS offset transistor is described.

After forming the P-type well region, which is not shown, in the P-type semiconductor substrate1, a resist pattern (not shown) is formed by a photomechanical technique. Using the pattern as a mask, phosphorus is ion-implanted under the conditions of an implantation energy of 100 KeV and a dose of 2.0×1013cm2. The resist pattern is thereafter removed and the substrate is exposed to a nitrogen atmosphere at 1000° C. for 30 minutes, whereby the implanted phosphorus is diffused and activated, forming the N-drain region3dand the N− source region3sof low concentration (seeFIG. 33).

Using an existing isolation formation technique, the LOCOS oxide films15are formed to a film thickness of 500 nm (seeFIG. 34).

After the gate insulating film51is formed to a film thickness of 80 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. Then, a resist pattern is formed using a photomechanical technique. Using the resist pattern as a mask, the polycrystalline silicon film and the gate insulating film51are sequentially removed by etching, whereby the gate electrode53is formed of the polycrystalline silicon film and the gate insulating film51is formed under the gate electrode53. Thereafter, the resist pattern is removed (seeFIG. 35). The edges of the gate electrode53are disposed on the LOCOS oxide films15.

After a resist pattern having openings in regions for forming the LOCOS offset transistor is formed, arsenic is ion-implanted under the conditions of an implantation energy of 30 KeV and a dose of 5.0×1015cm−2. The resist pattern is then removed and the substrate is exposed to a nitrogen atmosphere at 900° C. for 30 minutes, whereby the implanted arsenic is diffused and activated, forming the N+ drain region11dand the N+ source region11s, both of high concentration (seeFIG. 36). The N+ drain region11dand the low-concentration N-drain region3dthat covers around it constitute the drain region, while the N+ source region11sand the low concentration N− source region3sthat covers around it constitute the source region. Thus, in the LOCOS offset transistor, the drain region and the source region have a double diffusion structure.

Over the entire surface of the semiconductor substrate1, a silicon oxide insulating film17is deposited to a film thickness of 1000 nm. After a resist pattern is formed, predetermined locations of the silicon oxide insulating film17are removed by etching using the resist pattern as a mask, whereby connection holes21are formed at locations corresponding to the N+ drain region11d, the N+ source region11s, and the gate electrode53(seeFIG. 37).

Over the silicon oxide insulating film17, an aluminum metal film is formed and then patterned to form the gate wiring19g, the drain wiring19d, and the source wiring19s(seeFIG. 32).

The LOCOS offset transistor thus have the features that (1) the drain region and the source region have a double diffusion structure; and (2) the edges of the gate electrode53are disposed over the LOCOS oxide films15that are thicker than the gate insulating film51. Due to these two features, a high voltage LOCOS offset transistor can be obtained.

The withstand voltage of the drain region and the source region is determined by avalanche breakdown. As shown inFIG. 32, in the LOCOS offset transistor, the N+ drain region lid is surrounded by the N-drain region3dand the N+ source region11sis surrounded by the N-source region3s. Thus, the N+ drain region lid and the N+ source region11s, which have high concentrations, are not in direct contact with the P-type well. As a result, the avalanche breakdown voltage of the drain region and the source region can be increased up to about 30 V. The avalanche breakdown voltage of the drain region and the source region of a conventional MOS transistor that does not have the above two features (1) and (2) of the LOCOS offset transistor is on the order of 10 V.

It is known that in a MOS transistor, when the potential of its gate electrode is fixed to GND (ground) potential, the withstand voltage of the PN junction immediately below the gate electrode decreases. This phenomenon is referred to as the gate modulated junction withstand voltage, whereby a conventional MOS transistor breaks down at a voltage as low as 10 V. On the other hand, in the LOCOS offset transistor, since the edges of the gate electrode53overlie the LOCOS oxide films15, as shown inFIG. 32, the distance between the gate electrode53and the high-concentration N+ regions11dand11sin a direction perpendicular to the substrate can be increased. As a result, the gate-modulated junction breakdown voltage can be increased up to about 30 V.

Thus, an increase in the withstand voltage can be achieved by adopting the aforementioned two structural features; i.e., (1) the drain region and the source region are formed of the high-concentration N+ regions11d,11sand the low-concentration N− regions3d,3s, respectively; and (2) the edges of the gate electrode53are disposed over the LOCOS oxide films15.

In the following, a masked-LDD transistor is described.

FIG. 38shows a cross section of a masked-LDD transistor.

On the surface of a P-type semiconductor substrate1, an N-drain region3dand an N-source region3sare formed spaced apart from each other. On the semiconductor substrate1between the N-drain region3dand the N-source region3s, a gate insulating film51is formed. Over the gate insulating film51, a gate electrode53is formed. The semiconductor substrate1between the N-drain region3dand the N-source region3sprovides a channel region5. While not shown in the drawing, in the regions of the semiconductor substrate1where the N-drain region3d, the N-source region3s, and the channel region5are formed, a P-type well region is formed.

On the surface of the N-drain region3d, an N+ drain region11dis formed spaced apart from the edges of the N-drain region3d. On the surface of the N-source region3s, an N+ source region11sis formed spaced apart from the edges of the N-source region3s. Thus, as seen from above, the N+ drain region11dand the N+ source region11sare disposed spaced apart from the gate electrode53.

On the surface of the semiconductor substrate1, LOCOS oxide films15are formed for defining a region for the formation of the masked-LDD transistor. The LOCOS oxide films15have a film thickness greater than the gate insulating film51. Within the region for forming the masked-LDD transistor, the LOCOS oxide films15are not formed.

A silicon oxide insulating film17is formed on the semiconductor substrate1in such a manner as to cover the gate electrode53, the N+ drain region11d, the N+ source region11s, and the LOCOS oxide films15. On the silicon oxide insulating film17, a gate wiring19g, a drain wiring19d, and a source wiring19sof a metal material are formed. Via connection holes21formed in the silicon oxide insulating film17, the gate wiring19gis connected to the gate electrode53; the drain wiring19dis connected to the N+ drain region11d; and the source wiring19sis connected to the N+ source region11s.

With reference toFIGS. 38 to 43, a manufacturing process for the masked-LDD transistor is described. After the P-type well region (not shown) is formed in the P-type semiconductor substrate1, the LOCOS oxide films15are formed to a film thickness of 500 nm by an existing isolation formation technique (seeFIG. 39).

After the gate insulating film51is formed to a film thickness of 80 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. Then, a resist pattern is formed by a photomechanical technique and, using it as a mask, the polycrystalline silicon film and the gate insulating film51are sequentially removed by etching, thereby forming the gate electrode53of the polycrystalline silicon film and the gate insulating film51under the gate electrode53. Thereafter, the resist pattern is removed (seeFIG. 40).

After a resist pattern having openings at regions for forming the masked-LDD transistor is formed, phosphorus is ion-implanted under the conditions of an implantation energy of 30 KeV and a dose of 2.0×1013cm−2. The resist pattern is then removed and the substrate is exposed to a nitrogen atmosphere at 900° C. for 30 minutes, whereby the implanted phosphorus is diffused and activated, forming the N-drain region3dand the N-source region3sof low concentration (seeFIG. 41).

A resist pattern is then formed which covers the gate electrode53and portions of the N− drain region3dand the N-source region3sthat are, as seen from above, adjacent to the gate electrode53. Using that resist pattern as a mask, arsenic is ion-implanted under the conditions of an energy of 30 KeV and a dose of 5.0×1015cm−2. After the resist pattern is removed, the substrate is exposed to a nitrogen atmosphere at 900° C. for 30 minutes, whereby the implanted arsenic is diffused and activated, forming the N+ drain region11dand the N+ source region11sof high concentration (seeFIG. 42). The N+ drain region11dand the low-concentration N-drain region3dthat surrounds it constitute the drain region, while the N+ source region11sand the low-concentration N-source region3sthat surrounds it constitute the source region. Thus, in the masked-LDD transistor, the drain region and the source region have a double diffusion structure.

Thus, the masked-LDD transistor is characterized by the absence of the LOCOS oxide films15between the gate electrode53and the N-drain region3dand the N-source region3s. As will be understood from the above-described manufacturing process, the regions for the N-drain region3dand the N-source region3sare defined by resist patterns. A MOS transistor of this structure is formed by partially masking the implantation of high-concentration arsenic with such resist patterns; hence the name “masked-LDD” transistor.

To continue with the description of the manufacturing process, over the entire surface of the semiconductor substrate1, a silicon oxide insulating film17is formed to a film thickness of 1000 nm. After a resist pattern is formed, predetermined locations of the silicon oxide insulating film17are removed by etching using the resist pattern as a mask, whereby connection holes21are formed at positions corresponding to the N+ drain region11d, the N+ source region11s, and the gate electrode53(seeFIG. 43).

Over the silicon oxide insulating film17, an aluminum metal film is formed and then patterned, whereby the gate wiring19g, the drain wiring19d, and the source wiring19sare formed (seeFIG. 38).

The masked-LDD transistor differs from the LOCOS offset transistor in that the edges of the gate electrode on the sides of the drain region and the source region do not overlie the LOCOS oxide film. In a reflection of this difference, the applicable voltage (“withstand voltage”) of the masked-LDD transistor is smaller than that of the LOCOS offset transistor. On the other hand, the current driving capacity is higher for the masked-LDD transistor. Namely, the masked-LDD transistor is suitable for applications that need to permit the flow of large currents with an intermediate level of withstand voltage, and the LOCOS offset transistor is suitable for applications that need to handle high voltages even at the expense of current driving capacity.

In the foregoing description, both the drain region and the source region have the high withstand voltage capability. However, depending on device specifications, the drain region alone may have the high withstand voltage capability.

Hereafter, the common features of the masked-LDD transistor and the LOCOS offset transistor are discussed.

One common feature of the masked-LDD transistor and the LOCOS offset transistor is that the gate insulating film51has a large thickness of 80 nm. This film thickness is based on the assumed withstand voltage of 30 V; if the required withstand voltage is higher than 30 V, the film thickness is made even greater. Namely, since a high voltage is applied also to the gate electrode, the gate insulating film needs to be thick enough that it has a sufficient insulating property.

This poses an important issue with regard to both of these devices: since the gate insulating film51has the large film thickness of 80 nm, film formation takes a long process time. As a result, due to the influence of heat treatment during film formation, redistribution of the P-type well that is already formed and the channel-doping impurities for threshold voltage (Vth) adjustment occurs. Particularly, if the thickness of the gate insulating film becomes greater than about 50 nm, the oxidation time becomes extremely longer, resulting in a characteristics deviation in the completed device. This is not just the problem of the high withstand voltage transistor but it also affects other elements, such as capacitive and/or resistive elements or, in a case where another transistor for a separate use is formed on the same semiconductor substrate, such a device is also similarly affected. Thus, the problem of prolonged process time is one of the most significant factors blocking the realization of a complex/hybrid mounting.

Another problem associated with the thick gate insulating film is described with reference toFIGS. 44 to 47.

In a conventional manufacturing process for a high withstand voltage transistor, a thick gate insulating film51is formed on a semiconductor substrate1on which LOCOS oxide films15are formed. Then, a polycrystalline silicon film for forming a gate electrode53is formed over the entire surface of the wafer (seeFIG. 44). The polycrystalline silicon film is then removed by etching using a resist pattern (not shown), to form the gate electrode53(seeFIG. 45). After the thick gate insulating film51other than under the gate electrode53is removed by a wet etching technique, an N+ drain region11dand an N+ source region11sare formed by ion implantation (seeFIG. 46).

In the above manufacturing process, the thick gate insulating film51is removed except for under the gate electrode53. This is because, as shown inFIG. 45, if the thick gate insulating film51remains in the regions where the N+ drain region11dand the N+ source region11sare to be formed, the thick gate insulating film51blocks the ion implantation for forming the N+ drain region11dand the N+ source region11sand prevents their normal formation. Thus, as shown inFIG. 46, it is necessary to remove the thick gate insulating film51that remains in the planned regions for the N+ drain region11dand the N+ source region11sprior to ion implantation.

While the removal of the thick gate insulating film51is performed by wet etching, it takes a prolonged process to remove the thick gate insulating film51with its large film thickness of 80 nm.

Furthermore, the removal process results in a reduction of the LOCOS oxide films15that are already formed, such that the edges of the LOCOS oxide film15(within the broken-line circles inFIG. 46) develop a shape abnormality as indicated by recessed portions55(seeFIG. 47). This leads not just to a deviation from design dimensions but it may also lead to abnormality in electrical characteristics.

Thus, there are a number of issues associated with the formation of the thick gate insulating film, making it difficult to realize a high withstand voltage transistor and its mounting with other devices in a complex/hybrid manner.

SUMMARY

In an aspect of this disclosure, there is provided a semiconductor device comprising a MOS transistor that does not have the problems associated with the formation of a thick gate insulating film and that can be applied to high withstand voltage devices.

In another aspect, there is provided a semiconductor device comprising a MOS transistor, the MOS transistor comprising a semiconductor substrate of a first conductivity type; a drain region and a source region both of a second conductivity type disposed spaced apart from each other on a surface of the semiconductor substrate; a gate insulating film formed on the semiconductor substrate between the source region and the drain region; and a gate electrode formed on the gate insulating film. The semiconductor substrate between the source region and the drain region provides a channel region. The drain region comprises a first drain region disposed spaced apart from the gate insulating film and the channel region, and a second drain region disposed between and adjacent to the first drain region and the channel region. The gate electrode comprises a first gate electrode formed on the gate insulating film and a second gate electrode formed on the first gate electrode via a gate electrode insulating film. A gate wiring for providing a gate voltage is connected to the second gate electrode but not to the first gate electrode. The semiconductor device further comprises a field insulating film having a greater thickness than the gate insulating film, the field insulating film being disposed on the surface of the semiconductor substrate at least between the gate insulating film and the first drain region. An edge of the first gate electrode on the side of the drain region is disposed over the field insulating film.

The aforementioned MOS transistor includes the gate electrode which comprises the first gate electrode formed on the semiconductor substrate via the gate insulating film, and the second gate electrode formed on the first gate electrode via the gate electrode insulating film. The gate wiring for providing a gate voltage to the gate electrode is connected to the second gate electrode but not to the first gate electrode. In this structure, as regards the gate voltage, a voltage V2applied to the gate electrode insulating film and a voltage V1applied to the gate insulating film are determined by a capacitance value C2between the second gate electrode and the first gate electrode, and a capacitance value C1between the first gate electrode and the semiconductor substrate. Namely, even if the gate voltage applied to the gate electrode is a high voltage, the voltage V1applied to the gate insulating film can be reduced by adjusting the capacitance values C1and C2. Thus, the present invention can be applied to high withstand voltage devices to the gate electrode of which a gate voltage is applied, without using a thick gate insulating film. It is noted, however, that the semiconductor devices to which the present invention can be applied are not limited to those semiconductor devices comprising a MOS transistor having what is generally referred to as a high withstand voltage, such as 15 V or higher; the invention can be applied to semiconductor devices comprising a MOS transistor capable of high-speed operation with a low breakdown voltage.

An edge of the second gate electrode, as seen from above, may be disposed over the first gate electrode alone. In another embodiment, the device may comprise a pattern covering an edge and a side of the first gate electrode and disposed spaced apart from the second gate electrode, where the pattern is formed of the same material as and simultaneously with the second gate electrode. In these embodiments, the formation of a processing residue at the sides of the first gate electrode can be prevented, the processing residue being formed of the material for forming the second gate electrode. Thus, problems arising from the processing residue, such as electric short circuit in a wiring portion, can be prevented.

In another embodiment, the edges of the second gate electrode, as seen from above, are partly or entirely disposed outside the edges of the first gate electrode. A portion of the second gate electrode that is disposed outside the edges of the first gate electrode is disposed over the field insulating film, the portion being disposed over the first gate electrode via the gate electrode insulating film. Thus, the capacitance value between the first gate electrode and the second gate electrode can be adjusted by way of the sides of the first gate electrode.

In yet another embodiment, all of the edges of the second gate electrode, as seen from above, are disposed outside the edges of the first gate electrode, covering the edges and sides of the first gate electrode. Thus, the formation of a processing residue at the sides of the first gate electrode can be prevented, the residue being formed of the material for forming the second gate electrode. In this way, problems arising from such a processing residue, such as an electric short circuit in a wiring portion, can be prevented.

As seen from above, there may be a region over the first gate electrode that is spaced apart from the edges of the first gate electrode where the second gate electrode is not formed. In this way, the capacitance value between the first gate electrode and the second gate electrode can be increased compared with the case where the second gate electrode is formed over the entire surface of the first gate electrode, while preventing the formation of the processing residue at the sides of the first gate electrode, the residue being formed of the material for forming the second gate electrode.

In another embodiment, the device further comprises a plurality of the MOS transistors having different capacitance values between the first gate electrode and the second gate electrode. Thus, plural MOS transistors having different operating voltages can be mounted on the same semiconductor substrate in a hybrid manner.

In another embodiment, the plural MOS transistors differ from each other only in terms of the layout area of the second gate electrode. Thus, plural MOS transistors having different operating voltages can be formed without increasing the number of the manufacturing process steps.

In another embodiment, the device further comprises a capacitive element which comprises a first capacitive element electrode formed on the semiconductor substrate of the same material as and simultaneously with the first gate electrode; and a second capacitive element electrode formed on the first capacitive element electrode of the same material as and simultaneously with the second gate electrode, via an insulating film. Thus, the invention can be readily applied to analog circuits.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1shows an embodiment of the invention, (A) showing a cross section and (B) showing a plan view. The cross section (A) is taken along line A-A of (B). InFIG. 1(B), portions that are invisible as seen from above are also indicated by solid lines. InFIG. 1(A), a gate wiring and a gate contact are also schematically shown.

On the surface of a P-type semiconductor substrate (Psub)1, an N-drain region3dand an N− source region3sare formed spaced apart from each other. The semiconductor substrate1between the N− drain region3dand the N-source region3sprovides a channel region5. On the semiconductor substrate1between the N-drain region3dand the N-source region3s, a gate insulating film7is formed. The gate insulating film7, which may comprise a silicon oxide film, has a film thickness of 20 nm. While not shown in the drawings, a P-type well region is formed in the semiconductor substrate1in regions where the N− drain region3d, the N-source region3s, and the channel region5are formed.

On the gate insulating film7, a first gate electrode9is formed. The first gate electrode9, which may comprise a polycrystalline silicon film, has a film thickness of 300 nm.

On the first gate electrode9, a second gate electrode13is formed via a gate electrode insulating film11. The gate electrode insulating film11, which may comprise a silicon oxide film, has a film thickness of 20 nm. The second gate electrode13may comprise a polycrystalline silicon film; it has a film thickness of 300 nm.

On the surface of the N-drain region3d, an N+ drain region11dis formed spaced apart from the edges of the N-drain region3d. On the surface of the N-source region3s, an N+ source region11sis formed spaced apart from the edges of the N-source region3s. The N+ drain region11dand the N+ source region11shave higher concentrations of an N-type impurity than do the N-drain region3dand the N− source region3s. Thus, the drain region and the source region have a double diffusion structure.

On the surface of the semiconductor substrate1, LOCOS oxide films (field insulating film)15are formed to define a region for forming a LOCOS offset transistor. The LOCOS oxide films15have a greater film thickness than the gate insulating film7, such as 500 nm. The LOCOS oxide films15are also formed on the surface of the N− drain region3dbetween the edge of the N-drain region3don the side of the channel region5and the N+ drain region11d, and on the surface of the N− source region3sbetween the edge of the N-source region3son the side of the channel region5and the N+ source region11s. The edges of the first gate electrode9are disposed over the LOCOS oxide film15. The edges of the first gate electrode9on the side of the N+ drain region11dand on the side of the N+ source region11sare, as seen from above, spaced apart from the N+ drain region11dand the N+ source region11s, respectively.

Over the semiconductor substrate1, a silicon oxide insulating film17is formed covering the first gate electrode9, the second gate electrode13, the N+ drain region11d, the N+ source region11s, and the LOCOS oxide films15. On the silicon oxide insulating film17, a gate wiring19g, a drain wiring19d, and a source wiring19sare formed of a metal material, such as aluminum. Via connection holes21formed in the silicon oxide insulating film17, the gate wiring19gis connected to the second gate electrode13; the drain wiring19dis connected to the N+ drain region11d; and the source wiring19sis connected to the N+ source region11s. The gate wiring19gis not connected to the first gate electrode9.

FIGS. 2 through 7show sequentially a process of fabricating the LOCOS offset transistor shown inFIG. 1. In each of the figures, (A) shows a cross section and (B) shows a plan view, where the cross section of (A) is taken along line A-A of (B). In (B), portions that are invisible as seen from above are also indicated by solid lines. With reference toFIGS. 1 through 7, the manufacturing process is described.

After the P-type well region, not shown, is formed in the P-type semiconductor substrate1, a resist pattern (not shown) is formed by a photomechanical technique. Using the resist pattern as a mask, phosphorus is ion-implanted under the conditions of an implantation energy of 100 KeV and a dose of 2.0×1013cm−2. After the resist pattern is removed, the substrate is exposed to a nitrogen atmosphere at 1000° C. for 30 minutes, whereby the implanted phosphorus is diffused and activated, thus forming the N-drain region3dand the N-source region3sof low concentration (seeFIG. 2).

Using an existing isolation formation technique, the LOCOS oxide films15are formed to a film thickness of 500 nm (seeFIG. 3).

After the gate insulating film7is formed to a film thickness of 20 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. Using a photomechanical technique, a resist pattern is formed and, using the resist pattern as a mask, the polycrystalline silicon film and the gate insulating film7are successively removed by an anisotropic dry etching technique, thereby forming the first gate electrode9of the polycrystalline silicon film and the gate insulating film7only under the first gate electrode9. Thereafter, the resist pattern is removed (seeFIG. 4). The edges of the first gate electrode9are disposed over the LOCOS oxide film15. The removal of the gate insulating film7by etching may involve a wet etching technique.

After the gate electrode insulating film11is formed on the surface of the first gate electrode9to a film thickness of 20 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. Then, a resist pattern is formed by a photomechanical technique and, using the pattern as a mask, the polycrystalline silicon film and the gate electrode insulating film11are successively removed by an anisotropic dry etching technique, thereby forming the second gate electrode13of the polycrystalline silicon film and the gate electrode insulating film11only under the second gate electrode13. Thereafter, the resist pattern is removed (seeFIG. 5). The edges of the second gate electrode13, as seen from above, are disposed over the first gate electrode9. The removal of the gate electrode insulating film11by etching may involve a wet etching technique.

After a resist pattern having openings in regions for forming the LOCOS offset transistor is formed, arsenic is ion-implanted under the conditions of an implantation energy of 30 KeV and a dose of 5.0×1015cm−2. After the resist pattern is removed, the substrate is exposed to a nitrogen atmosphere at 900° C. for 30 minutes, whereby the implanted arsenic is diffused and activated, forming the N+ drain region11dand the N+ source region11sof high concentration (seeFIG. 6). The N+ drain region11dand the surrounding low concentration N-drain region3dconstitute the drain region, while the N+ source region11sand the surrounding low concentration N− source region3sconstitute the source region.

Over the entire surface of the semiconductor substrate1, the silicon oxide insulating film17, such as a laminate film consisting of an NSG (Non-doped Silicate Glass) film and a BPSG (Boro-phospho Silicate Glass) film is deposited to a film thickness of 1000 nm. After a resist pattern is formed, predetermined locations of the silicon oxide insulating film17are removed by etching, using the resist pattern as a mask, whereby the connection holes21are formed at the positions corresponding to the N+ drain region11d, the N+ source region11s, and the second gate electrode13(seeFIG. 7).

Thereafter, an aluminum metal film, for example, is formed over the silicon oxide insulating film17and then patterned to form the gate wiring19g, the drain wiring19d, and the source wiring19s(seeFIG. 1).

In the foregoing embodiment, because of the features that (1) the drain region and the source region have a double diffusion structure; and that (2) the edges of the first gate electrode9are disposed over the LOCOS oxide film15, which has a greater thickness than the gate insulating film7, the drain region and the source region can withstand a high voltage.

Furthermore, since the device has a laminated gate electrode structure comprising the first gate electrode9over which the second gate electrode13is disposed via the gate electrode insulating film11, the gate voltage applied to the second gate electrode13is divided between the gate electrode insulating film11and the gate insulating film7. Thus, the gate electrode can also withstand a high voltage. This is described with reference toFIGS. 1 and 8.

With reference toFIG. 8, how the gate voltage applied to the second gate electrode13is divided between the gate electrode insulating film11and the gate insulating film7is described.FIG. 8(A)shows a circuit diagram of the gate electrode and equations for voltages V1and V2fed to the gate insulating film7and the gate electrode insulating film11.FIG. 8(B)shows a table of voltages V1and V2with respect to various ratios of capacitance values C1to C2, where C1is the capacitance value between the first gate electrode9and the semiconductor substrate1and C2is the capacitance value between the second gate electrode13and the first gate electrode9.

When the capacitance value between the first gate electrode9and the semiconductor substrate1is C1and the capacitance value between the second gate electrode13and the first gate electrode9is C2, voltage V1applied to the gate insulating film7and voltage V2applied to the gate electrode insulating film11are calculated by the equations shown inFIG. 8.

When C1=C2, voltage V1applied to the second gate electrode13is reduced to one half the gate voltage (Vdd) applied to the second gate electrode13. This indicates that the gate insulating film thickness need only be one half the conventional thickness. Namely, it becomes possible to provide the gate electrode with the high withstand voltage capability without forming the thick gate insulating film through a long period of heat treatment.

In this embodiment, while the gate electrode insulating film11is described as comprising a single layer film of silicon oxide, the gate electrode insulating film may comprise a laminate film consisting of a silicon oxide/silicon nitride/silicon oxide (“ONO”) film. Generally, an ONO film has a higher insulating resistance than a silicon oxide single-layer film, so that a greater part of the voltage value applied to the second gate electrode13can be carried by the ONO film. Namely, the voltage applied to the gate insulating film7can be reduced. In addition, since the gate insulating film7can be obtained in the form of the silicon oxide film as is, no problem of shifting in electric characteristics due to the acquisition of hot carriers arises in principle.

The voltage V1applied to the gate insulating film7can be calculated from the equations shown inFIG. 8. By employing an ONO film for the gate electrode insulating film11, insulating resistance can be improved, i.e., the divided voltage V2can be increased. An active utilization of this fact is described below. Namely, C2is set smaller than C1. For example, when C2=C1/3, V2=21V and V1=7V when Vdd=28V as indicated by the calculation results shown inFIG. 8; i.e., only 7V is applied to the gate insulating film7in the high voltage environment where drive voltage Vdd=28V.

Furthermore, as shown inFIG. 9, by making the area of the gate insulating film7between the semiconductor substrate1and the first gate electrode9larger than the area of the gate electrode insulating film9between the first gate electrode9and the second gate electrode13, C2can be reduced. Thus, by adjusting the ratio of the area of the gate insulating film7, which is disposed between the semiconductor substrate1and the first gate electrode9, to the area of the gate electrode insulating film9disposed between the first gate electrode9and the second gate electrode13, the voltage applied to the gate insulating film7can be controlled relative to the gate voltage applied to the second gate electrode13.

The capacitance values C1and C2can also be controlled by adjusting the film thickness of the gate insulating film7and the gate electrode insulating film11, whereby the voltage applied to the gate insulating film7can be adjusted to a desired value.

Thus, the voltage applied to the gate insulating film7relative to the gate voltage applied to the second gate electrode13can be controlled either by the film type of the gate insulating film7and the gate electrode insulating film11; by the areas of the gate insulating film7and the gate electrode insulating film11; or by the film thicknesses of the gate insulating film7and the gate electrode insulating film11.

In the manufacturing process according to the foregoing embodiment ofFIG. 1, after the formation of the first gate electrode9, the polycrystalline silicon film is formed on the entire surface of the semiconductor substrate1via the gate electrode insulating film11, and then the polycrystalline silicon film is patterned by an anisotropic dry etching technique to form the second gate electrode13. As a result, a polycrystalline silicon processing residue23(indicated by a dotted pattern inFIG. 10(B)) may be formed at the sides of the first gate electrode9, as shown inFIG. 10. The polycrystalline silicon processing residue23is formed over N-regions3dand3svia an insulating film pattern which is formed of the same material as and simultaneously with the gate electrode insulating film11and the first gate electrode9.

In the present embodiment, since the polycrystalline silicon processing residue23is formed on the LOCOS oxide films15, and since the first gate electrode9and the second gate electrode13are insulated from each other, the polycrystalline silicon processing residue23does not adversely affect the transistor operation. If, however, the laminated gate electrode structure of the present invention shown inFIG. 48is applied to a conventional MOS transistor, the polycrystalline silicon processing residue23poses a shield during ion implantation for forming the N+ regions11dand11s, preventing the implantation of ions in portions indicated by the sign X. As a result, as seen from above, the N+ regions11dand11sare formed spaced apart from the first gate electrode9. Thus, the laminated gate electrode structure of the present invention cannot be adopted in conventional MOS transistor structures.

In the embodiment shown inFIG. 10, while the polycrystalline silicon processing residue23does not adversely affect transistor operation, if the polycrystalline silicon processing residue23peels off during the manufacturing process and moves over the semiconductor substrate, the polycrystalline silicon processing residue23becomes a so-called foreign matter which can cause an electrical short-circuit in wirings or a decrease in yield.

In the following, an embodiment in which the polycrystalline silicon processing residue23does not occur is described.

FIG. 11schematically shows the other embodiment.FIG. 11(A)shows a cross section andFIG. 11(B)shows a plan view, (A) showing a cross section taken along line A-A of (B). In (B), portions that are invisible as seen from above are also indicated by solid lines. In (A), a gate wiring and a gate contact are also schematically shown. Portions that perform the same functions as those of the portions shown inFIG. 1are designated with similar numerals.

In this embodiment, all of the edges of the second gate electrode13are disposed outside the edges of the first gate electrode9as seen from above, the second gate electrode13covering the sides of the first gate electrode9. Portions of the second gate electrode13that are disposed outside the edges of the first gate electrode9are disposed over the LOCOS oxide films15. Between the first gate electrode9and the second gate electrode13, a gate electrode insulating film11is formed.

Because the second gate electrode13covers the sides of the first gate electrode9, the polycrystalline silicon processing residue23(seeFIG. 10) is not formed at the sides of the second gate electrode13during the patterning of the polycrystalline silicon film by an anisotropic dry etching technique for forming the second gate electrode13. Thus, the problem of the polycrystalline silicon processing residue23can be prevented.

Furthermore, since the portions of the second gate electrode13that are disposed outside the edges of the first gate electrode9are disposed over the LOCOS oxide films15, the gate voltage applied to the second gate electrode13does not directly affect the gate insulating film7; namely, the high withstand voltage capability can be maintained.

Furthermore, since the capacitance value between the first gate electrode9and the second gate electrode13can be also adjusted by way of the sides of the first gate electrode9, a greater degree of freedom of design can be achieved.

While in the embodiment shown inFIG. 11the second gate electrode13is disposed over the entire surface of the first gate electrode9, the present invention is not limited by the embodiment.

FIG. 12schematically shows another embodiment of the invention, (A) showing a cross section and (B) showing a plan view. The cross section of (A) is taken along line A-A of (B). In (B), portions that are invisible as seen from above are also indicated by solid lines. In (A), a gate wiring and a gate contact are also schematically shown. Portions having the same functions as those of the portions shown inFIG. 1or11are designated with similar numerals. In (B), the second electrode is indicated by a dotted pattern.

In this embodiment, compared with the embodiment shown inFIG. 11, there is a region over the first gate electrode9that is spaced apart from the edges of the first gate electrode9and where the second gate electrode13is not formed. In this way, the capacitance value between the first gate electrode9and the second gate electrode13can be increased, compared with the embodiment shown inFIG. 11.

By adjusting the area of the region over the first gate electrode9where the second gate electrode13is not formed, the capacitance value between the first gate electrode9and the second gate electrode13can be set to an arbitrary value.

In the embodiment shown inFIG. 12, the region over the first gate electrode9where the second gate electrode13is not formed is rectangular and disposed at a single location. However, this is merely an example. In other embodiments, such a region may be provided at plural locations over the single gate electrode9, or its planar shape may be other than rectangular, such as circular.

While in the embodiments shown inFIGS. 11 and 12all of the edges of the second gate electrode13as seen from above are disposed outside the edges of the first gate electrode9, the edges of the second gate electrode13may be partly disposed outside the edges of the first gate electrode9, as shown inFIG. 13. InFIG. 13(B), the second gate electrode13and the polycrystalline silicon processing residue23are indicated by a dotted pattern.

In the embodiment shown inFIG. 13, the capacitance value between the first gate electrode9and the second gate electrode13can be reduced compared with the embodiment shown inFIG. 11while at the same time the development of the polycrystalline silicon processing residue23is permitted to some extent. Such a structure is effective in applications where there is not much fear of problems associated with the polycrystalline silicon processing residue23and where it is desired to reduce the voltage applied to the gate insulating film7.

FIG. 14schematically shows another embodiment, (A) showing a cross section and (B) showing a plan view. The cross section of (A) is taken along line A-A of (B). In (B), portions invisible as seen from above are also indicated by solid lines. In (A), a gate wiring and a gate contact are also schematically shown. Portions that perform the same functions as those of the embodiment ofFIG. 1are designated with similar numerals.

In the present embodiment, as in the embodiment ofFIG. 1, the second gate electrode13is formed only over the first gate electrode9. As seen from above, the edges of the second gate electrode13are disposed spaced apart from the edges of the first gate electrode9.

The present embodiment differs from the embodiment ofFIG. 1in that a polycrystalline silicon pattern27is formed that covers the edges and sides of the first gate electrode9via an insulating film pattern25. The polycrystalline silicon pattern27is disposed spaced apart from the second gate electrode13and is formed of the same material as and simultaneously with the second gate electrode13. Because the polycrystalline silicon pattern27is disposed spaced apart from the second gate electrode13, they are insulated from each other. The insulating film pattern25is formed of the same material as and simultaneously with the gate electrode insulating film11.

In this embodiment, the capacitance value between the first gate electrode9and the second gate electrode13can be reduced without developing the polycrystalline silicon processing residue23(seeFIG. 10).

While in the above embodiment the edges of the first gate electrode9on the sides of both the drain region and the source region are disposed over the LOCOS oxide films15, the edges of the first gate electrode9on the side of the drain region alone may be disposed over the LOCOS oxide film15, as shown inFIG. 15.

Furthermore, while in the above embodiment both the drain region and the source region comprise a double diffusion structure, the drain region alone may comprise the double diffusion structure, as shown inFIG. 16.

The embodiments shown inFIGS. 9 through 16can be formed by modifying the layout pattern (CAD data for photomasks) used in the exemplary manufacturing process described with reference toFIGS. 1 through 7.

If plural LOCOS offset transistors of a conventional structure for multiple gate voltages are mounted on a single semiconductor substrate in a hybrid manner, multiple problems arise.

For example, as shown inFIG. 49, when three types of LOCOS offset transistors corresponding to three gate voltage values are mounted in a hybrid manner, it has been necessary to make the film thickness of gate insulating films51-1,51-2, and51-3different for each of the LOCOS offset transistors. Specifically, in a transistor (1) that is operable with a gate voltage Vdd=30 V, the film thickness of the gate insulating film51-1may be 80 nm; in a transistor (2) that is operable with a gate voltage Vdd=22.5 V, the film thickness of the gate insulating film51-2may be 50 nm; and in a transistor (3) that is operable with a gate voltage Vdd=15 V, the film thickness of the gate insulating film51-3may be 30 nm. Thus, it has been necessary to adapt the gate insulating film to each voltage band. Fabricating such gate insulating films of three different film thicknesses on a single semiconductor substrate is thus associated with a number of problems to be solved, including the problem of extension of process flow time; the problem of an increase in the number of mask sets to be prepared; and the aforementioned problem of a decrease in the field insulating film (seeFIG. 47). For more details of such problems, reference should be made to Patent Document 3.

On the other hand, in the LOCOS offset transistor according to the present invention, the voltage applied to the gate insulating film can be controlled by adjusting the capacitance value between the semiconductor substrate and the first gate electrode and the capacitance value between the first gate electrode and the second gate electrode. Thus, plural types of LOCOS offset transistors associated with plural gate voltage values, i.e., different operating voltage bands, can be mounted on the same semiconductor substrate in a hybrid manner without having to vary the gate insulating film thickness from one transistor to another; i.e., with the individual gate insulating films having the same film thickness. With reference toFIG. 17, an embodiment is described in which three types of LOCOS offset transistors having different operating voltage bands are mounted on the same semiconductor substrate in a hybrid manner.

FIG. 17schematically shows the other embodiment, (A) showing a cross section, (B) showing a plan view, and (C) showing tables of exemplary settings of each transistor with respect to various gate voltages. The cross section in (A) is taken along line A-A of (B). In (B), portions that are invisible as seen from above are also indicated by solid lines. In (A), a gate wiring and a gate contact are also schematically shown. Portions corresponding to the parts shown inFIG. 1are designated with similar numerals.

In the present embodiment, a transistor (1) that is operable with a gate voltage Vdd=30 V, a transistor (2) that is operable with a gate voltage Vdd=22.5 V, and a transistor (3) that is operable with a gate voltage Vdd=15 V are mounted on the same semiconductor substrate1.

In these transistors (1), (2), and (3), the respective second gate electrodes13-1,13-2, and13-3have different layout areas. With regard to the other portions, such as the P-type well region formed in the semiconductor substrate1, the gate insulating film7, the first gate electrode9, and the gate electrode insulating film11, the three transistors (1), (2), and (3) are identical in terms of shape, impurity concentration, and film thickness. The planar shape of the gate electrode insulating film11differs among the transistors (1), (2), and (3), corresponding to the difference in planar shape among the second gate electrodes13-1,13-2, and13-3.

Specifically, among the transistors (1), (2), and (3), a capacitance value C1between the first gate electrode9and the semiconductor substrate1(P-type well region) is the same while a capacitance value C2between the first gate electrode9and the second gate electrode13is different. More specifically, in the transistor (1) that is operable with gate voltage Vdd=30 V, C2=C1/3; in the transistor (2) that is operable with gate voltage Vdd=22.5 V, C2=C1/2; and in the transistor (3) that is operable with gate voltage Vdd=15 V, C2=C1. Thus, in accordance with the aforementioned calculation equations shown inFIG. 8, the voltage applied to the gate insulating film7is 7.5 V for all of the three transistors (1), (2), and (3). Thus, using the gate insulating film7of the same film thickness, the same material, and the same fabrication period, a one-chip LSI can be obtained that can handle three different operating voltage bands of the applied voltage, namely, 30 V, 22.5 V, and 15 V.

Furthermore, since the three transistors (1), (2), and (3) can be formed by merely varying the layout area (CAD data) for the second gate electrode13, they can be formed by the manufacturing process described with reference toFIGS. 1 through 7. Thus, the problems described with reference toFIG. 49, such as the problem of extension of process flow time, the problem of an increase in the number of mask sets that need to be prepared, and the problem of a decrease in the field insulating film, can all be overcome.

In the embodiment shown inFIG. 17, the transistors (1), (2), and (3) are formed by varying only the layout area of the second gate electrode13-1,13-2, and13-3of the three transistors (1), (2), and (3). However, this is not the only method of varying the operating voltage bands of the LOCOS offset transistors. For example, the operating voltage bands of the LOCOS offset transistors may be made different by varying at least either the layout area, the film thickness, or the material of the gate insulating film7, the first gate electrode9, the gate electrode insulating film11, and the first gate electrode13from one another. However, in the light of the aforementioned problems described with reference toFIG. 49, it is advantageous to vary the layout area alone of the second gate electrode among the plural LOCOS offset transistors so as to vary the respective operating voltage bands.

While in the embodiment shown inFIG. 17the three transistors (1), (2), and (3) are all adapted to high voltage of 15 V and above, the LOCOS offset transistors according to the present invention can also be applied to a transistor that is operable with a low voltage of 2.5 V, for example. Thus, one, two, or all of the transistors (1), (2), and (3) may comprise transistors that are operable with low, mutually different operating voltage bands.

While in the embodiment shown inFIG. 17the transistors (1), (2), and (3) mounted on the same semiconductor substrate in a hybrid manner are all LOCOS offset transistors, it is also possible to mount a LOCOS offset transistor according to the present invention and a conventional MOS transistor on the same semiconductor substrate in a hybrid manner. Such an embodiment is described with reference toFIG. 18.

FIG. 18shows a cross section of the other embodiment. Portions that perform the same functions as those of the portions shown inFIG. 1are designated with similar numerals. Since the structure of the LOCOS offset transistor is the same as that of the embodiment ofFIG. 1, its description is omitted.

On a semiconductor substrate1, a conventional MOS transistor is formed in a different region from the region where the LOCOS offset transistor is formed.

The conventional MOS transistor includes an N+ drain region29dand an N+ source region29sthat are formed spaced apart from each other in a P-type well (not shown), which is formed on the surface side of the semiconductor substrate1. The semiconductor substrate1between the N+ drain region29dand the N+ source region29sprovides a channel region31. Over the channel region31, a gate insulating film33is located, which is formed simultaneously with a gate insulating film33of the LOCOS offset transistor. The gate insulating film33may be made of a silicon oxide film with a film thickness of 20 nm.

Over the gate insulating film33, a gate electrode35is formed. The gate electrode35is formed of the same material as and simultaneously with the first gate electrode9of the LOCOS offset transistor.

Over the semiconductor substrate1, a silicon oxide insulating film17is formed, covering the N+ drain region29d, the N+ source region29s, and the gate electrode35. Over the silicon oxide insulating film17, a gate wiring37g, a drain wiring37d, and a source wiring37sare formed of a metal material, such as aluminum. Via connection holes21formed in the silicon oxide insulating film17, the gate wiring37gis connected to the gate electrode35; the drain wiring37dis connected to the N+ drain region29d; and the source wiring37sis connected to the N+ source region29s.

FIGS. 19 through 24show schematic cross sections illustrating an example of the manufacturing process for forming the LOCOS offset transistor and the conventional MOS transistor shown inFIG. 18. With reference toFIGS. 18 through 24, the manufacturing process is described.

After the P-type well region (not shown) is formed in the P-type semiconductor substrate1, a resist pattern (not shown) is formed by a photomechanical technique. Using the pattern as a mask, phosphorus is ion-implanted under the conditions of an implantation energy of 100 KeV and a dose of 2.0×1013cm−2. After the resist pattern is removed, the substrate is exposed to a nitrogen atmosphere at 1000° C. for 30 minutes, whereby the implanted phosphorus is diffused and activated, thus forming the N-drain region3dand the N-source region3sof low concentration (seeFIG. 19).

Using an existing isolation formation technique, the LOCOS oxide films15are formed to a film thickness of 500 nm (seeFIG. 20).

After a silicon oxide film for the gate insulating films7and33is formed to a film thickness of 20 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. Then, a resist pattern is formed using a photomechanical technique. Using the pattern as a mask, the polycrystalline silicon film and the silicon oxide film are successively removed by an anisotropic dry etching technique, whereby the first gate electrode9and the gate electrode35are formed of the polycrystalline silicon film, the gate insulating film7is formed under the first gate electrode9, and the gate insulating film33is formed under the gate electrode35. Thereafter, the resist pattern is removed (seeFIG. 21). The removal of the silicon oxide film by etching for forming the gate insulating films7and33may involve a wet etching technique.

After the gate electrode insulating film11is formed to a film thickness of 20 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. Using a photomechanical technique, a resist pattern is formed and, using it as a mask, the polycrystalline silicon film and the gate electrode insulating film11are successively removed by an anisotropic dry etching technique, whereby the second gate electrode13of the polycrystalline silicon film is formed, and the gate electrode insulating film11is formed under the second gate electrode13. At this time, the polycrystalline silicon processing residue23is formed at the sides of the first gate electrode9and the gate electrode35. Thereafter, the resist pattern is removed (seeFIG. 22). The removal of the gate electrode insulating film11may involve a wet etching technique.

A resist pattern39that has openings in regions for forming the conventional MOS transistor is formed. Using the resist pattern39as a mask, the polycrystalline silicon processing residue23at the sides of the gate electrode35is removed by an isotropic etching technique, for example (seeFIG. 23).

After a resist pattern having openings at regions for forming the LOCOS offset transistor and the conventional MOS transistor is formed, arsenic is ion-implanted under the conditions of an implantation energy of 30 KeV and a dose of 5.0×1015cm−2. After the resist pattern is removed, the substrate is exposed to a nitrogen atmosphere at 900° C. for 30 minutes, whereby the implanted arsenic is diffused and activated, forming the N+ drain region11d, the N+ source region11s, the N+ drain region29d, and the N+ source region29sof high concentration (seeFIG. 24).

A silicon oxide insulating film17is deposited over the entire surface of the semiconductor substrate1to a film thickness of 1000 nm. After a resist pattern is formed, the silicon oxide insulating film17is removed by etching at predetermined positions, using the resist pattern as a mask, whereby connection holes21are formed at positions corresponding to the N+ drain region11d, the N+ source region11s, the second gate electrode13, the N+ drain region29d, the N+ source region29s, and the gate electrode35. Over the silicon oxide insulating film17, an aluminum metal film, for example, is formed and then patterned, whereby the gate wiring19g, the drain wiring19d, the source wiring19s, the gate wiring37g, the drain wiring37d, and the source wiring37sare formed (seeFIG. 18).

In this embodiment, the voltage applied to the gate insulating film7as regards the LOCOS offset transistor can be reduced by dividing the gate voltage as shown inFIG. 8. Thus, the gate insulating film7and the gate insulating film33of the conventional transistor can be formed of the same material, with the same film thickness, and simultaneously. Namely, the LOCOS offset transistor that can handle high voltage can be formed using the gate insulating film7that has the same characteristics as the gate insulating film33of the conventional transistor.

Furthermore, in the present embodiment, since the gate insulating film7of the LOCOS offset transistor and the gate insulating film33of the conventional transistor are simultaneously formed, process flow can be simplified when mounting the LOCOS offset transistor and the conventional transistor on the same semiconductor substrate in a hybrid manner, thus overcoming the aforementioned problem of extension of process flow time. In addition, since the first gate electrode9of the LOCOS offset transistor and the gate electrode35of the conventional transistor are simultaneously formed, process flow can be simplified.

FIG. 25shows a cross section of yet another embodiment of the invention. In the present embodiment, at a different position on the semiconductor substrate1from the region where a LOCOS offset transistor is formed, a capacitive element is formed. The capacitive element comprises a first capacitive element electrode formed of the same material as and simultaneously with the first gate electrode, and a second capacitive element electrode. The second capacitive element, which is disposed over the first capacitive element electrode via an insulating film, is formed of the same material as and simultaneously with the second gate electrode. In this figure, portions that perform the same functions as those of the portions shown inFIG. 1are designated with similar numerals. Since the structure of the LOCOS offset transistor is identical to that of the embodiment shown inFIG. 1, its description is omitted.

The capacitive element is formed, via LOCOS oxide films15, at a position on the semiconductor substrate1that is different from the region where the LOCOS offset transistor is formed. The capacitive element includes a first capacitive element electrode41uformed over the LOCOS oxide film15, and a second capacitive element electrode41tformed over the first capacitive element electrode41uvia a capacitive element electrode insulating film43. The first capacitive element electrode41uis formed of the same material as and simultaneously with the first gate electrode9. The capacitive element electrode insulating film43is formed of the same material as and simultaneously with the gate electrode insulating film11. The second capacitive element electrode41tis formed of the same material as and simultaneously with the second gate electrode13.

The silicon oxide insulating film17covers the first capacitive element electrode41uand the second capacitive element electrode41t. On the silicon oxide insulating film17, a first capacitive element electrode wiring45uand a second capacitive element electrode wiring45tare formed of the same material as and simultaneously with the gate wiring19g, the drain wiring19d, and the source wiring19s. Via connection holes21formed in the silicon oxide insulating film17, the first capacitive element electrode wiring45uis connected to the first capacitive element electrode41u, and the second capacitive element electrode wiring45tis connected to the second capacitive element electrode41t.

FIGS. 26 through 31show cross sections illustrating an example of a process of manufacturing the LOCOS offset transistor and the capacitive element shown inFIG. 25. With reference toFIGS. 25 through 31, the manufacturing process is described.

After a P-type well region, which is not shown, is formed in the P-type semiconductor substrate1, a resist pattern (not shown) is formed by a photomechanical technique. Using the pattern as a mask, phosphorus is ion-implanted under the conditions of an implantation energy of 100 KeV and a dose of 2.0×1013cm−2. After the resist pattern is removed, the substrate is exposed to a nitrogen atmosphere of 1000° C. and for 30 minutes, whereby the implanted phosphorus is diffused and activated, forming the N-drain region3dand the N-source region3sof low concentration (seeFIG. 26).

Then, the LOCOS oxide films15are formed by an existing isolation formation technique to a film thickness of 500 nm (seeFIG. 27).

After the gate insulating film7is formed to a film thickness of 20 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. A resist pattern is then formed by a photomechanical technique and, using it as a mask, the polycrystalline silicon film and the gate insulating film7are successively removed by an anisotropic dry etching technique, whereby the first gate electrode9and the first capacitive element electrode41uare formed of the polycrystalline silicon film and the gate insulating film7is formed under the first gate electrode9. While the gate insulating film7remains under the first capacitive element electrode41u, it is not shown. Thereafter, the resist pattern is removed (seeFIG. 28).

After a silicon oxide film for forming the gate electrode insulating film11and the capacitive element electrode insulating film43is formed to a film thickness of 20 nm, a polycrystalline silicon film is successively deposited to a thickness of 300 nm. A resist pattern is then formed by a photomechanical technique and, using it as a mask, the polycrystalline silicon film and the silicon oxide film are successively removed by an anisotropic dry etching technique, whereby the second gate electrode13and the gate electrode insulating film11are formed over the first gate electrode9, and the second capacitive element electrode41tand the capacitive element electrode insulating film43are formed over the first capacitive element electrode41u. A polycrystalline silicon processing residue23(seeFIG. 10) may be formed but not shown at the sides of the first gate electrode9and the first capacitive element electrode41u. Any polycrystalline silicon processing residue23that may be formed at the sides of the first capacitive element electrode41uis formed over the LOCOS oxide film15and therefore does not adversely affect the electric characteristics of the capacitive element. Thereafter, the resist pattern is removed (seeFIG. 29).

After a resist pattern having openings in regions for forming the LOCOS offset transistor is formed, arsenic is ion-implanted under the conditions of an implantation energy of 30 KeV and a dose of 5.0×1015cm−2. Thereafter, the resist pattern is removed and the substrate is exposed to a nitrogen atmosphere at 900° C. for 30 minutes, whereby the implanted arsenic is diffused and activated, forming the N+ drain region11dand the N+ source region11sof high concentration (seeFIG. 30).

Over the entire surface of the semiconductor substrate1, a silicon oxide insulating film17, such as a laminate film of an NSG film and a BPSG film, is deposited to a film thickness of 1000 nm. After a resist pattern is formed, the silicon oxide insulating film17at predetermined positions thereof is removed by etching, using the resist pattern as a mask, whereby connection holes21are formed at positions corresponding to the N+ drain region11d, the N+ source region11s, the second gate electrode13, the first capacitive element electrode41u, and the second capacitive element electrode41t(seeFIG. 31).

An aluminum metal film, for example, is formed over the silicon oxide insulating film17and then patterned, so as to form the gate wiring19g, the drain wiring19d, source wiring19s, the first capacitive element electrode wiring45u, and the second capacitive element electrode wiring45(seeFIG. 25).

In the present embodiment, the capacitive element comprises the first capacitive element electrode41uformed of the same material as and simultaneously with the first gate electrode9, the capacitive element electrode insulating film43formed of the same material as and simultaneously with the gate electrode insulating film11, and the second capacitive element electrode41tformed of the same material as and simultaneously with the second gate electrode13. Thus, the capacitive element can be formed on the same semiconductor substrate1in a hybrid manner without increasing the number of steps in the LOCOS offset transistor manufacturing process.

While in the present embodiment the edges of the second capacitive element electrode41tare disposed within the edges of the first capacitive element electrode41uas seen from above, the layout of the first capacitive element electrode41uand the second capacitive element electrode41tis not limited by such an embodiment.

For example, as in the layout of the first gate electrode9and the second gate electrode13of the LOCOS offset transistor shown inFIG. 12orFIG. 14as regards the capacitive element, the edges of the second capacitive element electrode41tas seen from above may be disposed outside the edges of the first capacitive element electrode41u, such that the second capacitive element electrode41tis not formed at the position where a contact for the first capacitive element electrode41uis formed. In this way, the formation of the polycrystalline silicon processing residue23(seeFIG. 10) at the sides of the first capacitive element electrode41ucan be prevented.

Alternatively, as in the layout of the first gate electrode9and the second gate electrode13of the LOCOS offset transistor shown inFIG. 13as regards the capacitive element, the edges of the second capacitive element electrode41tas seen from above may be partly disposed outside the edges of the first capacitive element electrode41u.

While the present invention has been described above with reference to particular embodiments, the shapes, arrangements, numbers, or materials used in these embodiments are exemplary. Various changes or modifications may be made within the scope of the invention recited in the claims.

The present application is based on the Japanese Priority Application No. 2007-085868 filed Mar. 28, 2007, the entire contents of which are hereby incorporated by reference.