Semiconductor device and manufacturing method thereof

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a III-V compound semiconductor layer and a manufacturing method thereof.

2. Description of the Prior Art

Because of the semiconductor characteristics, III-V semiconductor compounds may be applied in many kinds of integrated circuit devices, such as high power field effect transistors, high frequency transistors, or high electron mobility transistors (HEMTs). In the high electron mobility transistor, two semiconductor materials with different band-gaps are combined and heterojunction is formed at the junction between the semiconductor materials as a channel for carriers. In recent years, gallium nitride (GaN) based materials have been applied in the high power and high frequency products because of the properties of wider band-gap and high saturation velocity. Two-dimensional electron gas (2DEG) may be generated by the piezoelectricity property of the GaN-based materials, and the switching velocity may be enhanced because of the higher electron velocity and the higher electron density of the 2DEG. Therefore, how to further improve the electrical performance of transistors formed with III-V compound materials by modifying materials, structures and/or manufacturing methods has become a research direction for people in the related fields.

SUMMARY OF THE INVENTION

A semiconductor device and a manufacturing method thereof are provided in the present invention. A p-type doped III-V compound layer is formed in a trench of a III-V compound barrier layer, and a top surface of the p-type doped III-V compound layer is substantially coplanar with a top surface of the III-V compound barrier layer for enhancing the material quality of the p-type doped III-V compound layer, improving the electrical performance of the semiconductor device, and/or simplifying related manufacturing process steps.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench. A top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.

According to an embodiment of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A gate trench is formed in the III-V compound barrier layer. A p-type doped III-V compound layer is formed in the gate trench. A top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.

DETAILED DESCRIPTION

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The ordinal numbers, such as “first”, “second”, etc., used in the description and the claims are used to modify the elements in the claims and do not themselves imply and represent that the claim has any previous ordinal number, do not represent the sequence of some claimed element and another claimed element, and do not represent the sequence of the manufacturing methods, unless an addition description is accompanied. The use of these ordinal numbers is only used to make a claimed element with a certain name clear from another claimed element with the same name.

The term “etch” is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained. When “etching” a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is “removed”, substantially all the material layer is removed in the process. However, in some embodiments, “removal” is considered to be a broad term and may include etching.

The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer toFIG.1.FIG.1is a schematic drawing illustrating a semiconductor device101according to a first embodiment of the present invention. As shown inFIG.1, the semiconductor device101includes a III-V compound semiconductor layer20, a III-V compound barrier layer30, a gate trench TR, and a p-type doped III-V compound layer50. The III-V compound barrier layer30is disposed on the III-V compound semiconductor layer20. The gate trench TR is disposed in the III-V compound barrier layer30. The p-type doped III-V compound layer50is disposed in the gate trench TR. A top surface50T of the p-type doped III-V compound layer50and a top surface30T of the III-V compound barrier layer30are substantially coplanar. The p-type doped III-V compound layer50disposed in the gate trench TR may be used to reduce the electrical resistance of the semiconductor device101, the semiconductor device101may have positive threshold voltage accordingly, and the semiconductor device101may be regarded as a normally-off transistor and/or enhancement mode (E-mode) transistor.

In some embodiments, the semiconductor device101may further include a substrate10and a buffer layer12. The III-V compound semiconductor layer20may be disposed on the substrate10, and the buffer layer12may be disposed between the substrate10and the III-V compound semiconductor layer20in a vertical direction (such as a first direction D1shown inFIG.1), such as being disposed between a top surface10T of the substrate10and a bottom surface20B of the III-V compound semiconductor layer20. In some embodiments, the first direction D1described above may be regarded as a thickness direction of the substrate10, and the substrate10may have a top surface10T and a bottom surface10B opposite to the top surface10T in the first direction D1. The buffer layer12, the III-V compound semiconductor layer20, the III-V compound barrier layer30, and the p-type doped III-V compound layer50described above may be disposed at a side of the top surface10T. In addition, a horizontal direction substantially orthogonal to the first direction D1(such as a second direction D2shown inFIG.1and other directions orthogonal to the first direction D1) may be substantially parallel with the top surface10T and/or the bottom surface10B of the substrate10, but not limited thereto. Additionally, in this description, a distance between the bottom surface10B of the substrate10and a relatively higher location and/or a relatively higher part in the vertical direction (such as the first direction D1) may be greater than a distance between the bottom surface10B of the substrate10and a relatively lower location and/or a relatively lower part in the first direction D1. The bottom or a lower portion of each component may be closer to the bottom surface10B of the substrate10in the first direction D1than the top or upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surface10B of the substrate10in the first direction D1, and another component disposed under a specific component may be regarded as being relatively closer to the bottom surface10B of the substrate10in the first direction D1.

In some embodiments, the semiconductor device101may further include an insulation layer40, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1. The insulation layer40may be disposed on the III-V compound barrier layer30, and the insulation layer40may include an opening OP1located corresponding to the gate trench TR in the first direction D1. The gate electrode GE1, the source electrode SE1, and the drain electrode DE1may be disposed on the substrate10. In some embodiments, the gate electrode GE1may be disposed on the p-type doped III-V compound layer50and the insulation layer40in the first direction D1, and the source electrode SE1and the drain electrode DE1may be located at two opposite sides of the gate electrode GE1in a horizontal direction (such as the second direction D2), respectively, and the source electrode SE1and the drain electrode DE1may be located on the III-V compound barrier layer30in the first direction D1. In some embodiments, the gate electrode GE1, the source electrode SE1, the drain electrode DE1, the p-type doped III-V compound layer50, the insulation layer40, the III-V compound barrier layer30, and the III-V compound semiconductor layer20may constitute a transistor structure, such as a high electron mobility transistor (HEMT), but not limited thereto.

In the semiconductor device101, the top surface50T of the p-type doped III-V compound layer50and the top surface30T of the III-V compound barrier layer30are substantially coplanar. In other words, under the influences of process variations and process uniformity, the top surface50T may be slightly higher than the top surface30T or slightly lower than the top surface30T. For example, in some embodiments, a distance DS between the top surface50T of the p-type doped III-V compound layer50and a bottom surface30B of the III-V compound barrier layer30in the first direction D1may be equal to a thickness TK1of the III-V compound barrier layer30in the first direction D1with a tolerance of ±10%. Therefore, the distance DS may be greater than or equal to 0.9 times the thickness TK1and less than or equal to 1.1 times the thickness TK1.

Additionally, the gate trench TR does not penetrate through the III-V compound barrier layer30in the first direction D1. Therefore, a part of the III-V compound barrier layer30may be located between the gate trench TR and the III-V compound semiconductor layer20in the first direction D1, and a thickness TK2of the p-type doped III-V compound layer50in the first direction D1may be less than the thickness TK1of the III-V compound barrier layer30in the first direction D1. The thickness TK1of the III-V compound barrier layer30may be regarded as a distance between the top surface30T and the bottom surface30B of the III-V compound barrier layer30in the first direction D1, and the thickness TK2of the p-type doped III-V compound layer50may be regarded as a distance between the top surface50T and the bottom surface50B of the p-type doped III-V compound layer50in the first direction D1. In some embodiments, a ratio of the thickness TK2of the p-type doped III-V compound layer50to the thickness TK1of the III-V compound barrier layer30(TK2/TK1) may be less than 1 and greater than or equal to 0.8 so as to make the p-type doped III-V compound layer50closer to the interface between the III-V compound barrier layer30and the III-V compound semiconductor layer20(such as a portion where the bottom surface30B of the III-V compound barrier layer30is connected with a top surface20T of the III-V compound semiconductor layer20) for achieving the desired effects of positive threshold voltage and reducing electrical resistance and keeping the p-type doped III-V compound layer50from directly contacting the III-V compound semiconductor layer20. For example, in some embodiments, the thickness TK1of the III-V compound barrier layer30may range from 50 nanometers to 100 nanometers, and the thickness TK2of the p-type doped III-V compound layer50may range from 40 nanometers to 90 nanometers.

In some embodiments, the opening OP1and the gate trench TR may be formed by the same patterning process. Therefore, the opening OP1may be disposed corresponding to the gate trench TR in the first direction D1, a projection area of the opening OP1in the first direction D1may be substantially the same as a projection area of the gate trench TR in the first direction D1, and the projection area of the opening OP1and the projection area of the gate trench TR may overlap in the first direction D1. In some embodiments, the gate trench TR may be fully filled with the p-type doped III-V compound layer50, and the p-type doped III-V compound layer50is not disposed outside the gate trench TR or slightly disposed outside the gate trench TR. Therefore, the top surface50T of the p-type doped III-V compound layer50may be lower than a top surface40T of the insulation layer40in the first direction D1, but not limited thereto. Additionally, in some embodiments, the gate electrode GE1may be disposed on the p-type doped III-V compound layer50in the first direction D1and directly connected with the p-type doped III-V compound layer50, and a part of the gate electrode GE1may be disposed on the top surface40T of the insulation layer40in the first direction D1.

In some embodiments, the III-V compound semiconductor layer20may include gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or other suitable III-V compound semiconductor materials. The III-V compound barrier layer30may include aluminum gallium nitride, aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), aluminum nitride (AlN), or other suitable III-V compound barrier materials. The p-type doped III-V compound layer50may include p-type doped aluminum gallium nitride, p-type doped gallium nitride, or other suitable p-type doped III-V compound materials. In addition, the p-type dopant in the p-type doped III-V compound layer50may include cyclopentadienyl magnesium (Cp2Mg), magnesium, beryllium (Be), zinc (Zn), a combination of the materials described above, or other suitable p-type dopants.

In some embodiments, the III-V compound semiconductor layer20may include a gallium nitride layer, the III-V compound barrier layer30may include an aluminum gallium nitride layer, and the p-type doped III-V compound layer50may include a p-type doped aluminum gallium nitride layer and/or a p-type doped gallium nitride layer. The p-type doped aluminum gallium nitride layer in the p-type doped III-V compound layer50may be formed directly by a suitable manufacturing process (such as an epitaxial growth process) and/or formed by aluminum diffusing from the III-V compound barrier layer30to the gallium nitride layer in the p-type doped III-V compound layer50. Therefore, an atomic concentration of aluminum in the p-type doped III-V compound layer50may be lower than an atomic concentration of aluminum in the III-V compound barrier layer30. In other words, the p-type doped III-V compound layer50may include a p-type doped AlxGa1-xN layer, wherein x is less than 1 and greater than 0; or the p-type doped III-V compound layer50may include a p-type doped AlxGa1-xN layer, wherein x is less than 1 and greater than or equal to 0, and the p-type doped III-V compound layer50is a p-type doped GaN layer when x is equal to 0.

In some embodiments, the substrate10may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride substrate, a sapphire substrate, or a substrate made of other suitable materials. The buffer layer12may include gallium nitride, aluminum gallium nitride, aluminum indium nitride, or other suitable buffer materials. The gate electrode GE1, the source electrode SE1, and the drain electrode DE1may respectively include an electrically conductive metal material or other suitable electrically conductive materials. The electrically conductive metal materials mentioned above may include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), a compound of the above-mentioned materials, a stacked layer of the above-mentioned materials, or an alloy of the above-mentioned materials, but not limited thereto. The insulation layer40may include an oxide insulation material, a nitride insulation material, or other suitable insulation materials.

Please refer toFIGS.1-4.FIGS.2-4are schematic drawings illustrating a manufacturing method of a semiconductor device according to an embodiment of the present invention, andFIG.1may be regarded as a schematic drawing in a step subsequent toFIG.4. As shown inFIG.1, the manufacturing method of the semiconductor device in this embodiment may include the following steps. The III-V compound barrier layer30is formed on the III-V compound semiconductor layer20. The gate trench TR is formed in the III-V compound barrier layer30. The p-type doped III-V compound layer50is formed in the gate trench TR. The top surface50T of the p-type doped III-V compound layer50and the top surface30T of the III-V compound barrier layer30are substantially coplanar.

Specifically, the manufacturing method of the semiconductor device in this embodiment may include but is not limited to the following steps. Firstly, as shown inFIG.2, the buffer layer12, the III-V compound semiconductor layer20, and the III-V compound barrier layer30may be sequentially formed on the substrate10, and an insulation layer40is formed on the III-V compound barrier layer30. Subsequently, as shown inFIG.3, the opening OP1and the gate trench TR are formed. The opening OP1penetrates through the insulation layer40in the first direction D1, and the opening OP1is located corresponding to the gate trench TR in the first direction D1. In some embodiments, the opening OP1and the gate trench TR may be formed by a patterning process91. For example, in some embodiments, the patterning process91may include an etching step, a patterned mask layer42may be formed on the insulation layer40before the etching step, and the opening OP1and the gate trench TR may be formed by etching the insulation layer40and the III-V compound barrier layer30with the patterned mask layer42as an etching mask. As shown inFIG.3andFIG.4, after the patterning process91, the patterned mask layer42may be removed, and an epitaxial growth process92may be carried out for forming the p-type doped III-V compound layer50in the gate trench TR. In some embodiments, the epitaxial growth process92may include a selective epitaxial growth process, and the p-type doped III-V compound layer50may be formed by epitaxial growth starting from the surface of the III-V compound barrier layer30exposed by the gate trench TR without epitaxial growth starting from the insulation layer40and the top surface30T of the III-V compound barrier layer30covered by the insulation layer40. In addition, by the material selection and/or the process condition control of the epitaxial growth, the growing rate of the p-type doped III-V compound layer50from the inner sidewall of the gate trench TR may be higher than the growing rate of the p-type doped III-V compound layer50from the bottom surface of the gate trench TR. In this way, the p-type doped III-V compound layer50may be controlled to be formed in the gate trench TR and may be less likely to be formed outside the gate trench TR.

Subsequently, as shown inFIG.4andFIG.1, after the step of forming the p-type doped III-V compound layer50, the gate electrode GE1, the source electrode SE1, and the drain electrode DE1may be formed for forming the semiconductor device101. In some embodiments, the gate electrode GE1may be formed on the p-type doped III-V compound layer50and the insulation layer40, and the source electrode SE1and the drain electrode DE1may be formed on the insulation layer40, but not limited thereto. In some embodiments, the source electrode SE1and the drain electrode DE1may respectively extend to be partially located in the III-V compound barrier layer30. By the manufacturing method in this embodiment, the p-type doped III-V compound layer50may be formed self-aligned in the gate trench TR. Therefore, it is not necessary to perform an etching process to the p-type doped III-V compound layer50, and etching damage to the p-type doped III-V compound layer50and/or III-V compound barrier layer30by the etching process may be avoided. The material quality of the p-type doped III-V compound layer50may be enhanced, the electrical performance of the semiconductor device may be improved, and/or the related manufacturing process steps may be simplified accordingly.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

Please refer toFIG.5.FIG.5is a schematic drawing illustrating a semiconductor device201according to another embodiment of the present invention. As shown inFIG.5, in some embodiments, the substrate10may include a first region R1and a second region R2. The buffer layer12, the III-V compound semiconductor layer20, the III-V compound barrier layer30, and the insulation layer40described above may be disposed above the first region R1and the second region R2of the substrate10. The gate trench TR, the p-type doped III-V compound layer50, and the opening OP1described above may be disposed above the first region R1of the substrate10. The gate electrode GE1described above may be regarded as a first gate electrode disposed above the first region R1of the substrate10, and the source electrode SE1and the drain electrode DE1described above may be regarded as a first source electrode and a first drain electrode disposed above the first region R1of the substrate10. In addition, the semiconductor device201may further include a second gate electrode (such as a gate electrode GE2shown inFIG.5), a second source electrode (such as a source electrode SE2shown inFIG.5), and a second drain electrode (such as a drain electrode DE2shown inFIG.5) disposed above the second region R2of the substrate10. The gate electrode GE2may be disposed on the III-V compound barrier layer30and the insulation layer40located above the second region R2, and the gate electrode GE2may be disposed corresponding to another opening OP2in the insulation layer40. The opening OP2may expose the III-V compound barrier layer30located above the second region R2, and the gate electrode GE2may contact the III-V compound barrier layer30via the opening OP2. The source electrode SE1and the drain electrode DE2may be located at two opposite sides of the gate electrode GE2in a horizontal direction (such as the second direction D2), respectively, and the source electrode SE2and the drain electrode DE2may be located on the III-V compound barrier layer30above the second region R2in the first direction D1.

In some embodiments, the material composition of the gate electrode GE2may be similar to the material composition of the gate electrode GE1, and the material composition of the source electrode SE2and the drain electrode DE2may be similar to the material composition of the source electrode SE1and the drain electrode DE1, but not limited thereto. In some embodiments, the gate electrode GE1, the source electrode SE1, the drain electrode DE1, the p-type doped III-V compound layer50, the insulation layer40located above the first region R1, the III-V compound barrier30located above the first region R1, and the III-V compound semiconductor layer20located above the first region R1may constitute a first transistor structure T1. The gate electrode GE2, the source electrode SE2, the drain electrode DE2, the insulation layer40located above the second region R2, the III-V compound barrier30located above the second region R2, and the III-V compound semiconductor layer20located above the second region R2may constitute a second transistor structure T2. The first transistor structure T1including the p-type doped III-V compound layer50may be regarded as an E-mode transistor, and the second transistor structure T2without the gate trench TR and the p-type doped III-V compound layer50may be regarded as a depletion mode (D-mode) transistor, but not limited thereto.

Please refer toFIG.5andFIG.6.FIG.6is a schematic drawing illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention, andFIG.5may be regarded as a schematic drawing in a step subsequent toFIG.6. As shown inFIG.6, the buffer layer12, the III-V compound semiconductor layer20, the III-V compound barrier layer30, and the insulation layer40may be formed above the first region R1and the second region R2of the substrate10, and the gate trench TR, the p-type doped III-V compound layer50, and the opening OP1may be formed above the first region R1of the substrate10. The III-V compound barrier layer30on the second region R2may be completely covered by the insulation layer40during the step of forming the p-type doped III-V compound layer50for avoiding forming the p-type doped III-V compound layer50by the epitaxial growth process on the III-V compound barrier layer30above the second region R2. Subsequently, as shown inFIG.6andFIG.5, after the step of forming the p-type doped III-V compound layer50, the gate electrode GE1, the source electrode SE1, and the drain electrode DE1may be formed on the first region R1, and the gate electrode GE2, the source electrode SE2, and the drain electrode DE2may be formed on the second region R2. The gate electrode GE1may be formed above the III-V compound barrier layer30located on the first region R1and formed corresponding to the opening OP1in the first direction D1, and the gate electrode GE2may be formed above the III-V compound barrier layer30located on the second region R2and formed corresponding to the opening OP2in the first direction D1. In some embodiments, the gate electrode GE1and the gate electrode GE2may be formed concurrently by the same process (such as a film forming process of an electrically conductive layer and a patterning process performed to this electrically conductive layer) and have the same material composition accordingly, and the opening OP2may be formed in the insulation layer40after the step of forming the p-type doped III-V compound layer50and before the step of forming the gate electrode GE2. In addition, the source electrode SE1and the drain electrode DE1may be a source electrode and a drain electrode of the first transistor structure T1including the gate electrode GE1and formed above the III-V compound barrier layer30located on the first region R1. The source electrode SE2and the drain electrode DE2may be a source electrode and a drain electrode of the second transistor structure T2including the gate electrode GE2and formed above the III-V compound barrier layer30located on the second region R2. In some embodiments, the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2may be formed concurrently by the same process (such as a film forming process of an electrically conductive layer and a patterning process performed to this electrically conductive layer) and have the same material composition accordingly, but not limited thereto. In other words, at least a part of the first transistor structure T1and at least a part of the second transistor structure T2with different modes may be formed concurrently by the same process for manufacturing process simplification.

Please refer toFIG.7.FIG.7is a schematic drawing illustrating a semiconductor device102according to a second embodiment of the present invention. As shown inFIG.7, in some embodiments, a part of the p-type doped III-V compound layer50may be disposed on the insulation layer40in the first direction D1, and the p-type doped III-V compound layer50on the insulation layer40may be located between the insulation layer40and the gate electrode GE1in the first direction D1. For example, the p-type doped III-V compound layer50formed by the epitaxial growth process may be formed partly outside the gate trench TR, and a part of the p-type doped III-V compound layer50may be formed on the insulation layer40in the first direction D1accordingly, but not limited thereto. In addition, the allocation of the p-type doped III-V compound layer50in this embodiment may be applied to other embodiments of the present invention (such as being applied to the first transistor structure T1inFIG.5described above and other embodiments below) according to some design considerations.

Please refer toFIG.8.FIG.8is a schematic drawing illustrating a semiconductor device103according to a third embodiment of the present invention. As shown inFIG.8, in some embodiments, the top surface50T of the p-type doped III-V compound layer50may include a concave surface. A portion of the top surface50T (such as the bottommost portion) may be slightly lower than the top surface30T of the III-V compound barrier layer30in the first direction D1, and the distance DS between the top surface50T and the bottom surface30B of the II-v compound barrier layer30in the first direction D1may be slightly less than the thickness TK1of the III-V compound barrier layer30in the first direction D1. In some embodiments, before the step of forming the gate electrode GE1, a planarization process (such as a chemical mechanical polishing process or other suitable planarization approaches) may be performed to the p-type doped III-V compound layer50for removing the p-type doped III-V compound layer50located outside the gate trench TR (such as the p-type doped III-V compound layer50shown inFIG.7described above), and the top surface50T of the p-type doped III-V compound layer50may be influenced by the planarization process and may be a slightly concave surface accordingly. Additionally, the p-type doped III-V compound layer50with the top surface50T which is concave may be applied to other embodiments of the present invention (such as being applied to the first transistor structure T1inFIG.5described above and other embodiments below) according to some design considerations.

Please refer toFIG.9.FIG.9is a schematic drawing illustrating a semiconductor device104according to a fourth embodiment of the present invention. As shown inFIG.9, in some embodiments, a part of the p-type doped III-V compound layer50may be disposed on a sidewall of the insulation layer40in the horizontal direction (such as the second direction D2), and the top surface50T of the p-type doped III-V compound layer50may be regarded as a recess surface, but not limited thereto. In addition, the allocation of the p-type doped III-V compound layer50in this embodiment may be applied to other embodiments of the present invention (such as being applied to the first transistor structure T1inFIG.5described above and other embodiments below) according to some design considerations.

Please refer toFIG.10.FIG.10is a schematic drawing illustrating a semiconductor device105according to a fifth embodiment of the present invention. As shown inFIG.10, in some embodiments, the source electrode SE1and the drain electrode DE1may penetrate through the insulation layer40in the first direction D1, respectively, for being partly disposed in the III-V compound barrier layer30. In addition, the allocation of the source electrode SE1and the drain electrode DE1in this embodiment may be applied to other embodiments of the present invention (such as being applied to the first transistor structure T1inFIG.5described above and other embodiments below) according to some design considerations.

Please refer toFIG.11.FIG.11is a schematic drawing illustrating a semiconductor device202according to a sixth embodiment of the present invention. As shown inFIG.11, the difference between the semiconductor device202and the semiconductor device201shown inFIG.5described above is that the semiconductor device202may further include a dielectric layer62. The dielectric layer62may cover the insulation layer40, the gate electrode GE1, and the gate electrode GE2, and the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2may respectively penetrate through the dielectric layer62and the insulation layer40for being partly disposed in the III-V compound barrier layer30. The dielectric layer62may include a single layer or multiple layers of dielectric materials, such as an oxide dielectric material or other suitable dielectric materials. In some embodiments, a part of the source electrode SE1may be disposed on the dielectric layer62and located between the gate electrode GE1and the drain electrode DE1for adjusting the electric field distribution between the gate electrode GE1and the drain electrode DE1, but not limited thereto.

Please refer toFIGS.11-14.FIG.12is a schematic flow chart of a manufacturing method of the semiconductor device202according to the sixth embodiment of the present invention,FIG.13andFIG.14are schematic drawings illustrating the manufacturing method of the semiconductor device in this embodiment, andFIG.11may be regarded as a schematic drawing in a step subsequent toFIG.14. As shown inFIG.12andFIG.13, in some embodiments, step S10may be carried out for sequentially forming the buffer layer12, the III-V compound semiconductor layer20, the III-V compound barrier layer30, and the insulation layer40. The opening OP1is then formed in the insulation layer40located on the first region R1, and the gate trench TR is formed in the III-V compound barrier layer30located above the first region R1. Subsequently, step S11may be carried out for forming the p-type doped III-V compound layer50in the gate trench TR. The III-V compound barrier layer30located above the second region R2may be completely covered by the insulation layer40during the step of forming the p-type doped III-V compound layer50for avoiding forming the p-type doped III-V compound layer50by the epitaxial growth process on the III-V compound barrier layer30located above the second region R2. Subsequently, as shown inFIG.12andFIG.14, step S12may be carried out for forming the gate structure GE1and the gate structure GE2. In some embodiments, the opening OP2may be formed after the step of forming the p-type doped III-V compound layer50and before the step of forming the gate electrode GE2, but not limited thereto. As shown inFIG.12andFIG.11, after the step of forming the gate electrode GE1and the gate electrode GE2, step S13may be carried out for forming the dielectric layer62covering the gate electrode GE1, the gate electrode GE2, and the insulation layer40. After the step of forming the dielectric layer62, step S14may be carried out for forming the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2. In other words, the gate electrode and the source/drain electrode may be formed by different manufacturing processes, respectively. The gate electrode GE1and the gate electrode GE2may be formed before the step of forming the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2. The first transistor structure T1and the second transistor structure T2with different modes may be formed concurrently on the same substrate10, and at least a part of the first transistor structure T1and at least a part of the second transistor structure T2(such as the gate electrodes or the source/drain electrodes) may be formed concurrently by the same process for manufacturing process simplification. In addition, because the enhancement mode of the first transistor structure T1may be achieved by forming the gate trench TR in the III-V compound barrier layer30and forming the p-type doped III-V compound layer50in the gate trench TR, the first transistor structure T1and the second transistor structure T2with different modes may be manufactured on the same substrate10, and some material layers (such as the buffer layer12, the III-V compound semiconductor layer20, and/or the III-V compound barrier layer30) located corresponding to the first transistor structure T1and the second transistor structure T2may be formed concurrently on the same substrate10.

Please refer toFIG.15.FIG.15is a schematic drawing illustrating a semiconductor device203according to a seventh embodiment of the present invention. The difference between the semiconductor device203and the semiconductor device201shown inFIG.5described above is that the semiconductor device203may further include the dielectric layer62and a dielectric layer64. The dielectric layer62may be disposed on the insulation layer40, and the dielectric layer64may be disposed on the dielectric layer62. The source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2may respectively penetrate through the dielectric layer62and the insulation layer40in the first direction D1for contacting the III-V compound barrier layer30. The gate electrode GE1may penetrate through the dielectric layer64and the dielectric layer62in the first direction D1for being connected with the p-type doped III-V compound layer50, and the gate electrode GE2may penetrate through the dielectric layer64, the dielectric layer62, and the insulation layer40in the first direction D1for contacting the III-V compound barrier layer30. The dielectric layer64may include a single layer or multiple layers of dielectric materials, such as an oxide dielectric material or other suitable dielectric materials.

Please refer toFIGS.15-18.FIG.16is a schematic flow chart of a manufacturing method of the semiconductor device203according to the seventh embodiment of the present invention,FIG.17andFIG.18are schematic drawings illustrating the manufacturing method of the semiconductor device in this embodiment, andFIG.15may be regarded as a schematic drawing in a step subsequent toFIG.18. As shown inFIG.16andFIG.17, in some embodiments, step S20may be carried out for sequentially forming the buffer layer12, the III-V compound semiconductor layer20, the III-V compound barrier layer30, and the insulation layer40. The opening OP1is then formed in the insulation layer40located on the first region R1, and the gate trench TR is formed in the III-V compound barrier layer30located above the first region R1. Subsequently, step S21may be carried out for forming the p-type doped III-V compound layer50in the gate trench TR. The III-V compound barrier layer30located above the second region R2may be completely covered by the insulation layer40during the step of forming the p-type doped III-V compound layer50for avoiding forming the p-type doped III-V compound layer50by the epitaxial growth process on the III-V compound barrier layer30located above the second region R2. Subsequently, as shown inFIG.16andFIG.18, step S22may be carried out for forming the dielectric layer62covering the insulation layer40and the p-type doped III-V compound layer50. After the step of forming the dielectric layer62, step S23may be carried out for forming the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2. Subsequently, as shown inFIG.16andFIG.15, step S24may be carried out for forming the dielectric layer64covering the dielectric layer62, the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2. Step S25may be carried out afterward for forming the gate structure GE1and the gate structure GE2. In other words, the gate electrode and the source/drain electrode may be formed by different manufacturing processes, respectively. The gate electrode GE1and the gate electrode GE2may be formed after the step of forming the source electrode SE1, the drain electrode DE1, the source electrode SE2, and the drain electrode DE2. The first transistor structure T1and the second transistor structure T2with different modes may be formed concurrently on the same substrate10, and at least a part of the first transistor structure T1and at least a part of the second transistor structure T2(such as the gate electrodes or the source/drain electrodes) may be formed concurrently by the same process for manufacturing process simplification. In addition, because the enhancement mode of the first transistor structure T1may be achieved by forming the gate trench TR in the III-V compound barrier layer30and forming the p-type doped III-V compound layer50in the gate trench TR, the first transistor structure T1and the second transistor structure T2with different modes may be manufactured on the same substrate10, and some material layers (such as the buffer layer12, the III-V compound semiconductor layer20, and/or the III-V compound barrier layer30) located corresponding to the first transistor structure T1and the second transistor structure T2may be formed concurrently on the same substrate10.

To summarize the above descriptions, in the semiconductor device and the manufacturing method thereof according to the present invention, the p-type doped III-V compound layer may be formed in the gate trench located in the III-V compound barrier layer, and the top surface of the p-type doped III-V compound layer and the top surface of the III-V compound barrier layer may be substantially coplanar. The p-type doped III-V compound layer disposed in the gate trench may be used to reduce the electrical resistance of the semiconductor device and achieve positive threshold voltage in the semiconductor device. In addition, the p-type doped III-V compound layer may be formed in the gate trench by an epitaxial growth approach, it is not necessary to perform an etching process to the p-type doped III-V compound layer, and the negative influence of the etching process may be avoided accordingly. The material quality of the p-type doped III-V compound layer may be enhanced, the electrical performance of the semiconductor device may be improved, and/or the related manufacturing process steps may be simplified accordingly.