Hiding refresh in 1T-SRAM architecture

A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external access conditions. This includes full compatibility when sequential operations alternate between memory cells in same row and column locations within different memory banks. The device includes bi-directional buses to allow read and write operations to occur between memory banks and cache over the same bus. The refresh operations can be carried out without interference with external accesses under any conditions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor memories. Specifically, embodiments of the present invention relate to a method and apparatus for handling data storage in a semiconductor memory.

2. Related Art

A conventional DRAM (dynamic random access memory) memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM (static random access memory) cell, which typically consists of 6 transistors in a corresponding technology. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each memory refresh operation of a DRAM cell utilizes memory bandwidth. If an external access and a refresh access can be initiated at the same time, the DRAM array must be able to handle both within the allowable access cycle time so as to prevent the refresh from interfering with the external access. If, for example, the cycle time of a 100 MHz DRAM array is 10 ns, each external access may take 10 ns and each refresh may take 10 ns, the external access cycle time may be no less than 20 ns. As a result, the maximum accessing frequency of the DRAM array must be less than or equal to 50 MHz. Thus, a 100 MHz DRAM memory array is required to create a device effectively operating at 50 MHz and this is not efficient.

Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device requires an external signal to control refresh operations. External accesses to this DRAM device are delayed during refresh operations, resulting in the refresh operation not being transparent. As a result, this device cannot be fully compatible with an SRAM device.

Other conventional art schemes use multi-banking to reduce the average access time of a DRAM device. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle.

In one conventional art apparatus, an SRAM compatible device is built from DRAM. This device includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. (See U.S. Pat. No. 5,999,474 by Wingyu Leung et. al., “Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory”, Dec. 7, 1999.) This architecture, shown inFIGS. 1A and 1B, implements a write-back policy in which all write data is initially written to the SRAM cache prior to being written to the memory banks. The idea is to allow a refresh to occur when a cache hit occurs. When this architecture is required to sequentially write to two different banks at the same row and column address, a “ping-pong” effect takes place, creating continual cache misses, which creates a “blind hole”, not allowing a refresh cycle to take place.

Accordingly, it would be desirable to have a DRAM memory cell architecture that is fully compatible with pure SRAM devices and that creates an opportunity for a hidden refresh cycle to be performed when sequential cache misses occur at the same addressed location within different memory banks.

SUMMARY OF THE INVENTION

According to embodiments of the present invention, a DRAM memory cell architecture is provided that is fully compatible with pure SRAM devices and that creates an opportunity for a hidden refresh cycle to be performed when sequential cache misses occur at the same address locations within different memory banks.

In various embodiments, a memory device architecture comprising at least one bi-directional bus for reading and writing to and from a plurality of memory banks and a cache is presented. The memory device architecture also comprises a first memory bank coupled to the bus, a second memory bank coupled to the bus, a cache coupled to the bus; and a modifiable bit (M-bit) in the cache TAG for controlling write-back to the memory banks from the cache.

In one embodiment, a memory device architecture is described wherein each memory bank comprises a plurality of DRAM cells.

A memory device architecture is described, according to one embodiment, wherein the cache comprises a plurality of static random access memory (SRAM) cells. In one embodiment, the memory banks and cache have the same configuration.

A memory device architecture is described in one embodiment of the present invention wherein a refresh cycle may occur when there is no pending request to write data from the cache back to the memory bank. During a write cycle and a cache hit, according to one embodiment, input data is written into the cache and the associated M-bit is set to “1”.

A memory device architecture is described, according to one embodiment, wherein a bi-directional bus allows the memory device architecture to write data to a memory bank and read out the data from the memory bank and write to the cache in one cycle.

In one embodiment, a memory device architecture is described wherein, during a write cycle and a cache miss with the M-bit having a value of “1”, data in the cache is written back to a first memory location in the first memory bank. Input data is then written into a second memory address location in the second memory bank. The input data is then read out from the second memory address location and written to the cache at a same addressed location and the M-bit is set to “0”. Upon the next external operation accessing the same cache location, the second memory location is free for a refresh cycle since the cache and the memory bank contain the same information and there is no pending request to write back to the memory bank.

A memory device architecture is described in one embodiment wherein, during a write cycle and a cache miss with M-bit having a value of “0”, input data is written into a third memory location, the input data is then read from the third memory location and written into the cache at the same location and the M bit is set to “0.”

The present embodiments provide these advantages and others not specifically mentioned above but described in the sections to follow. Other features and advantages of the embodiments will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without some specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments.

It should be born in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing the following terms refer to the actions and processes of a computer system or similar electronic computing device. These devices manipulate and transform data that is represented as physical (electronic) quantities within the computer system's registers and memories or other such information storage, transmission or display devices. The aforementioned terms include, but are not limited to, “selecting” or “initiating” or “writing” or “reading” or “refreshing” or “comparing” or “writing back” or “reading out” or the like.

In accordance with the embodiments, a memory device architecture is designed using DRAM cells so as to be fully compatible with an SRAM device. This SRAM compatible device architecture is hereinafter referred to as one-transistor SRAM (1T-SRAM). The 1T-SRAM architecture includes multiple DRAM banks (e.g., 64) that can operate independently of each other so that operations, such as read, write, and refresh, can take place in different DRAM banks simultaneously. A mechanism is provided so that refresh access requests are simultaneously broadcast to multiple DRAM banks. The DRAM banks that receive the broadcast refresh request signal go through a refresh cycle only when there is no bank access pending.

An SRAM cache is incorporated to store the data of the most recently accessed locations. The SRAM cache may have a capacity approximately equal to the storage capacity of one of the DRAM banks.

When an access is initiated by an external circuit, an address is provided to address buffer260ofFIG. 2. Address buffer260in turn routes the address to cache tag memory270. The address identifies a DRAM bank, row and column to be accessed.

FIG. 3is an illustration of row and column locations for writing to and reading from array of memory banks210and cache220, according to one aspect of the embodiments. Each memory bank within memory bank array210is composed of columns and rows in a similar configuration as is shown by cache configuration320. For example, an address, such as bank2, row1, column2, stores cache entries of up to 256 bits from DRAM bank2, row1, column2of memory array210into row1, column2of cache220.

In the described example, cache tag memory270ofFIG. 2may retrieve the bank address stored in row1, column2of bank2and may provide it to a comparator (not shown). Cache tag memory270also may provide the modified bit (M-bit) associated with the retrieved bank address. The comparator compares the bank address retrieved from cache tag memory270with the current bank address. If a match is detected, then a cache hit exists. If comparator270does not detect a match, then a cache miss exists. In response to signals for address, read or write access, M-bit and hit or miss indication, it can be determined whether the current access is a read hit, a write hit, a read miss or a write miss.

Referring now toFIG. 4, a table400illustrating the 1T-SRAM protocol, according to the embodiments is presented. The read and write policy of one aspect of the embodiments will now be described for the read and write transactions of read hit, write hit, read miss and write miss according to embodiments of the present invention. Row1A illustrates the 1T-SRAM protocol for read access with a cache (e.g., cache220ofFIGS. 2 and 3) hit. When there is a cache hit, there is no need to check for the M-bit setting since there is no need to write data back into memory. Therefore, the 1T-SRAM protocol reads the data from cache220and all memory banks (e.g., DRAM array210ofFIG. 2) are free for a refresh cycle. At this point, nothing has been written and nothing changed, so there is no need to set the M-bit.

Row1B of table400of 1T-SRAM protocol illustrated inFIG. 4shows the protocol for write access with a cache hit according to one embodiment. Again, when there is a cache hit there is no need to check the M-bit and the 1T-SRAM protocol writes data into the data cache. With there being no write back request pending, all banks are free for a refresh cycle. Following the write-to-cache operation, the M-bit is set to 1 and the next operation on the same cache location with a cache miss will cause a write back operation.

Referring now to Row2of table400, a read access with a cache miss is shown, in accordance with an embodiment of the present invention, for which the M-bit has a value of “0”. In this embodiment, an M-bit value of “0” is indicative of the cache data and memory data being the same as of the last cycle of operation and, therefore, not requiring a write back operation. Thus, the data is read from the required memory location and written to cache. During this cycle, all memory banks, except the one from which data is being read, are free for refresh. It should be appreciated that at the conclusion of this cycle of operation, the M-bit is set to “0” and the next operation for the same cache location will free the associated memory bank for a refresh cycle.

Row3of the table400illustrates the 1T-SRAM protocol for a read access with a cache miss for which the M-bit has a value of “1” in accordance with an embodiment. In this instance, the cache and memory data are different and the cache writes back the data into memory before reading the next data from memory and writing to the cache. During this cycle, all memory banks are free for refresh with the exception of the memory bank to which the cache writes back and the memory bank from which data is being read to the cache. At the conclusion of this cycle of operation, the M-bit is set to “0” and the next operation at the same location in cache will thereby free the associated memory bank for refresh.

In Row4of the table400ofFIG. 4, the 1 T-SRAM protocol for a write access with a cache miss and an M-bit set to “0”, in accordance with one aspect of the embodiments, is illustrated. The input data is written directly to memory (e.g., memory210ofFIG. 2) and read out to the data cache. During this cycle only one memory bank is not free for a refresh so that all others can be refreshed. At the end of this cycle, the data in cache and memory are the same and the M-bit is set to “0”. Upon the next operation requiring the same cache address, a write-back to memory will not be required and the affiliated memory bank will be free for a refresh cycle.

Row5of the table400illustrates the 1T-SRAM protocol for a write access with a cache miss and M-bit equal to “1”. For this operation, the cache data is first read back into the associated memory bank location. The input data is then written directly to memory and read out from memory and written to the data cache at the same row and column location. During this cycle, all memory banks are free for refresh with the exception of the memory bank to which the cache writes back and the memory bank from which data is being written to and read from the cache. The M-bit is set to “0” and, upon the next access for the same cache location, a write-back to memory will not be required and the affiliated memory bank will be free for a refresh cycle.

It should be appreciated that this protocol assures that sequential cache to memory write-backs will not occur as a result of sequential operations involving like row and column addresses in different memory banks. Therefore, the memory banks will be free for a refresh cycle no less frequently than once following every other operation.

FIG. 5is a flow diagram500of steps performed, in accordance with one embodiment of the present invention, in a method for performing a write cycle with a cache miss and an M-bit set to 1 according to one embodiment of the present invention. Although specific steps are disclosed in flow diagram500, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited inFIG. 5.

At step510ofFIG. 5, a write cycle access is required and it is determined that the memory bank address to which the input data is to be written contains data that is different than the data at the same address in cache220(FIGS. 2 and 3). The M-bit has a value of “1” indicating that the data in cache220must be written back to memory210before other operations can be performed.

At step520ofFIG. 5, the data in cache220at the column and row of the memory being addressed is written back to that address in the memory bank within memory210(FIG. 3) from which it was originally written. The process then moves to step530.

At step530, the input data is written to the appropriate memory bank within the DRAM memory array210. At step540, it is read out to cache220at the same row and column address. As the data in memory210and cache220is now the same, the M-bit is reset to “0” as shown in step550. The next operation at a same row and column will not require the cache data to be written back to memory210and will free up the memory bank so a refresh cycle can occur.

FIG. 6is a flow diagram600of steps performed, in accordance with one embodiment of the present invention, in a method for handling a cache miss for a write operation with an M-bit equal to “0” in accordance with one embodiment of the present invention. Although specific steps are disclosed in flow diagram600, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited inFIG. 6.

At step610ofFIG. 6, a write cycle access is required and the cache tag comparator has determined that the memory bank address within memory array220(FIG. 3) to which the input data is to be written contains data that is different than the data at the same address in cache210. The M-bit has a value of “0”, however, indicating that the data in the cache need not be written back to memory.

At step620, the input data is written to the appropriate memory bank where it is combined with the data already there. The process then moves to step630where it is read out to cache210at the same row and column address. As the data in memory220and cache210is now the same, the M-bit is reset to “0” as shown in step640. The next operation at a same row and column will not require the cache data to be written back to memory220and will free up the memory bank so a refresh cycle can occur.