Power management for processing unit

Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

FIELD

Embodiments of the disclosure relate generally to electronic components and, more specifically, to managing power for a processing unit.

BACKGROUND

Today's central processing units (CPUs) have significant variability in their dynamic current consumption as a function of the application workload. Their potential current consumption is very high, while their typical current consumption is much lower. In order to provide sufficient voltage to the CPU throughout the entire range of current consumption a power delivery system typically provides a voltage with a significant voltage guard band. That is, the power delivery system provides the CPU with extra voltage to handle sudden changes in current consumption, which affect a corresponding voltage drop. While providing a large voltage guard band ensures adequate processing functionality from the CPU, it also results in higher costs, greater power consumption, and shorter product lifetime of CPUs.

DETAILED DESCRIPTION

Illustrative embodiments include but are not limited to processes, apparatuses, and systems that reduce voltage guard bands admitted to processing units of computing devices.

In providing some clarifying context to language that may be used in connection with various embodiments, the phrases “A/B” and “A and/or B” mean (A), (B), or (A and B); and the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

FIG. 1illustrates a processing and power management system (hereinafter “system”)100in accordance with various embodiments. The system100includes a main power supply104, a power management unit (PMU)108, a voltage regulator112, and a processing unit116coupled to each other as shown. The voltage regulator112may be coupled to the processing unit116through an input/output interface120that provides a power and/or signaling interface.

The PMU108may be coupled to, or integrated within, the processing unit116, and may collect information from the processing unit116and control the voltage regulator112to provide a desired voltage, as will be discussed in further detail herein.

The processing unit116is shown with multiple cores, e.g., n cores; however, in other embodiments, the processing unit116may have one or two cores.

The main power supply104may be a power source used to power all of the modules of a computing device in which the system100is implemented. For example, the main power supply104may power a display, a mass storage device, auxiliary processing units, etc. The main power supply104may be a battery, an alternating current (AC) to direct current (DC) power converter, etc.

The main power supply104may output a voltage that is much larger than an input voltage desired by the processing unit116. Accordingly, the PMU108may control the voltage regulator112to step down and regulate the voltage prior to admitting it to the processing unit116.

A desired voltage will be one that is sufficient to sustain the desired frequency of the processing unit116in order to avoid processing errors. A desired voltage will also be one that is no too high, which could result in wasted power and/or a shorter product lifetime. The power is a square function of voltage and, therefore, any power penalty may be high.

Changes in current consumption at the processing unit116may result in the voltage varying over time. Accordingly, the voltage set by the PMU108may, in certain instances, include a voltage guard band that provides the processing unit116with sufficient power to sustain a desired frequency. Embodiments of this disclosure reduce the size of the voltage guard band, which may include elimination of the voltage guard band altogether in certain situations, used to accommodate the consumed current while maintaining desired performance. As will be described, some embodiments provide for this reduction through a more precise accounting of the voltage variation provided by the consumed current. Other embodiments provide for this reduction through control of the peak current demands through detection of architectural events.

Providing a more precise accounting of the voltage variation may be done by recognizing that a current consumed by the processing unit116is comprised of a plurality of different current components with each component impacting the overall voltage variation to a different degree. Prior art designs that do not account for such variation use a maximum impact over the range of the current, thereby introducing unnecessary voltage guard band headroom.FIGS. 2 and 3provide graphs to facilitate this explanation.

FIG. 2illustrates a load line204as a function of a voltage V_pu of the processing unit116and current I in accordance with various embodiments. The current I may include a 10 amp (A) leakage current component, a 20 A idle current component (e.g., from 10 A to 30 A), and a 40 A dynamic current component (e.g., from 30 A to 70 A). The determination that these current components correspond to these ranges, which are presented merely as an example, will be discussed in further detail below.

The voltage V_vid set by the voltage regulator112may account for the voltage drop as the current increases. The V_vid may be set by the PMU108providing the voltage regulator112with a digital value, e.g., a voltage identification (VID) value, that corresponds to the voltage V_vid.

The voltage drop may be determined by the resistance R_ll of the load line times the current I. These values may be related to the V_pu by:
V—pu=V_vid−I*R—ll.Equation 1

To account for the voltage drop over the entire range of current I, a V_vid may be set at, e.g., 1.1 volts (V) (the y-intercept of the load line204). This may ensure that even at the high-end of the current I, e.g., 70 A, the corresponding V_pu will be no less than a test voltage V_test, e.g., 0.96 V, which is enough to provide a frequency sufficient for reliable processing.

Setting V_vid at 1.1 V and relying upon this load line behavior for the entire range of current from 0 A to 70 A may be sufficient to maintain desired frequency levels; however, it may be overly conservative. This may be evident through an examination of the characteristics of the various current components.

FIG. 3illustrates a load line304as a function of impedance and frequency in accordance with various embodiments. As can be seen, impedance remains virtually unchanged until a frequency of approximately 50 kilohertz (kHz). From about 50 kHz-10 megahertz (MHz) the impedance fluctuates about 3 milliohms (mΩ), and spikes to approximately 15 mΩ around 100 MHz.

The idle and leakage current components may have DC characteristics and, therefore, a very low frequency. Accordingly, as can be seen inFIG. 3, the impedance experienced at low frequencies may be steady. Thus, the PMU108may reliably determine the voltage drop from these components (using, e.g., 2 mΩ), without having to provide a significant voltage guard band to accommodate voltage variation.

The dynamic current component, on the other hand, may have AC characteristics and, therefore, a varying frequency. Assuming that the frequency of the dynamic current component stays less than 50 MHz, the impedance experienced throughout the range of frequencies may range from approximately 1 to 4 mΩ. Accordingly, for the dynamic current component, the PMU108may provide a sufficient voltage guard band to accommodate a voltage variation that corresponds to this 3 mΩ impedance variation. Thus, in accordance with various embodiments, the PMU108may determine the distinct voltage variations that correspond to the various current components and set an appropriate voltage V_vid. This determination and setting of V_vid may be done based on changing operating conditions of the processing unit116, which will, in turn, provide different concentrations of the current components.

The load line204is shown as an example. The exact behavior of a load line may be a function of the power delivery design of a particular platform and may change from system to system. The V_vid voltage setting may account for a load line of a specific arrangement.

FIG. 4illustrates the system100in which the PMU108is coupled with a power characteristic block404in accordance with some embodiments. The power characteristic block404may include power characteristics of the various current components and/or subsets thereof. The power characteristics may include information that may be used by the PMU108to facilitate a determination of the size of at least one subset of the current components, its frequency characteristics, and/or its respective voltage variation based at least in part on operating conditions of the processing unit116.

For example, power characteristics of a leakage-current subset may provide that the subset changes with a very slow frequency as a response to temperature, while power characteristics of an active-current subset may provide that the subset changes more rapidly as a function of architectural state of the processing unit108, e.g., activation of cores or functional blocks such as floating point unit, etc. As will be discussed below, these types of power characteristics may be used by the PMU108to determine an appropriate response.

As used herein, a subset of the current components may refer to a subset of all of the current components of which the total current is comprised. A subset may include one or more current components, but not all of the current components, of the total current. In some embodiments a subset may exist for each current component. In other embodiments, a subset may include one or more current components with similar power characteristics. For example, in one embodiment a subset may include idle current and leakage current as they may both have DC characteristics as discussed above. In this embodiment, another subset may include the dynamic current.

In various embodiments, the power characteristics may be determined through testing of the system100. After the system100has been tested, the power characteristics may be stored in the power characteristic block404.

In various embodiments, the power characteristics of a specific load line may be set by the platform designer using a basic input/output system (BIOS) for example.

In various embodiments, the power characteristic block404may reside in a non-volatile storage device, firmware, the processing unit116itself (e.g., in one or more fuses), etc.

FIG. 5illustrates a process for determining and setting a voltage in accordance with some embodiments. At block504, the PMU108may access the power characteristic block404to read the power characteristics for the various subsets of current components.

At block508, the PMU108may determine a magnitude for each of the subsets for a given operating condition of the processing unit116. An operating condition of the processing unit116may include a state of each core of the processing unit116, the temperature, and the activity of the processing unit116(e.g., how many processes, tasks, applications, etc. are being executed by the processing unit116). The various current components may be functions of the operating conditions of the processing unit116as defined by the power characteristics. For example, the leakage current may be a function of voltage V_pu, temperature, and the number of cores that are in a sleep state, e.g., C3, or a more dormant state; idle current may be a function of a number of cores in an operating state, e.g., C0; and dynamic current may be a function of the activity of the processing unit116.

At block512, the PMU108may determine a distinct voltage variation for a subset of the current components based at least in part on associated power characteristics. A determination of the voltage variation for a subset may be based at least in part on a magnitude of the current components of the subset and a voltage variation impact value associated with the subset. For example, in one embodiment, the PMU108may determine a voltage variation for a first subset that includes the idle current component and the leakage current component and a second subset that includes the dynamic current component. The first subset may have DC characteristics and a negligible impact value. Therefore, its resultant voltage variation may also be negligible. The second subset, having the dynamic current component, may have a measurable impact value, which may result in a measurable voltage variation attributed to the dynamic current component.

At block516, the PMU108may determine a total voltage variation for the consumed current. The total voltage variation may be an additive function of voltage variations contributed by each of the subsets of current components. In the example given above, the total voltage variation may be, essentially, the voltage variation attributable to the dynamic current component as the voltage variation attributable to the first subset is negligible.

With the total voltage variation determined, the PMU108may set an appropriate voltage V_vid to be admitted to the processing unit116by the voltage regulator112at block520.

The PMU108may then monitor the processing unit116to detect an operating condition change at block524. If a change is detected, the PMU108may loop back to block508to begin a redetermination of a voltage to set in light of the changed conditions. If no change is detected, the PMU108may continue to monitor operating conditions at block524.

In various embodiments, a response frequency of the PMU108may be limited. For example, the PMU108may respond to a change in power characteristics that occur up to 1 kHz, but may be challenged by dynamic changes that occur faster. Responding to faster events may be handled in a variety of ways. In an embodiment for which the changes are known ahead of time, e.g., a C3 exit, the PMU108may halt the change until the V_vid change completes, and then allow the change. In other embodiments, architectural events may be monitored as they occur and, once detected, the PMU108may halt the condition, change the V_vid and then allow the change to occur. Embodiments in which the architectural events are monitored may be discussed in more detail with respect toFIGS. 6-8.

FIG. 6illustrates the system100in accordance with another embodiment. In this embodiment, each of the cores of the processing unit116may be configured with a threshold current I_cc detector (“thresh I_cc detector”)604as shown.

FIG. 7illustrates a process of operating the system100with thresh I_cc detectors604in accordance with various embodiments. At block704, the PMU108may set a relatively low voltage V_vid. Referring also toFIG. 8, the low voltage V_vid may be set at approximately 1.08 V (the y-intercept for a load line804). The low voltage V_vid may be set so that a resulting V_pu is sufficient for a range of current consumed by the processing unit116through a normal workload. This range may be defined as a given percentage of total current or as the range in which the processing unit116operates for a given percentage of time. In this embodiment, the low voltage V_vid may accommodate currents up to approximately 60 A.

At block708, the thresh I_cc detectors604may detect a variety of architectural events occurring on a particular core. Architectural events may relate to activities on a particular core. For example, an architectural event may be an activation of execution unit, load port activity, etc.

At block712, a thresh I_cc detector604may determine whether the detected architectural events exceed a predetermined threshold, e.g., a predetermined percentage of the execution units operating for a predetermined period of time. Exceeding a predetermined threshold may be indicative of the respective processing core, or the processing unit116as a whole, being at risk of drawing a current over a predetermined threshold current. This condition, when viewed as an aggregate of the cores of the processing unit116, may be reflected by the load line804intersecting the voltage floor V_test at 60 A.

By monitoring the architectural events, a thresh I_cc detector604may be capable of quickly recognizing that a respective core is readying itself for processing of power-consuming instruction flows.

If the thresh I_cc detector604determines that the detected events exceed a threshold at block712, it may throttle the core to prevent the core from drawing an excessive amount of current at block716. The thresh I_cc detector604may throttle the core by instituting one or more actions that reduce an input rate of instructions, e.g., micro-ops, which the core will execute. This throttling mechanism may provide a suitably fast response to an over-current condition.

In some embodiments, the throttling provided by a thresh I_cc detector604may be a first-stage response to an over-current condition. In some of these embodiments, a second-stage response may be provided by the PMU108so that the processing unit116may operate at a high-end of its current consumption range, shown generally as section808ofFIG. 8. This may be done by the PMU108setting a high voltage V_vid at block720. Load line812ofFIG. 8may correspond to the high voltage V_vid being set at approximately 1.1 V (the y-intercept of the load line812).

It may be noted that the “high” and “low” descriptors that may be used in conjunction with the voltage V_vid have meaning only in relation to one another. No external or other constraints are intended by use of these terms.

The PMU108may initiate the second-stage response, e.g., by setting the high voltage V_vid at block720, upon a determination that the events threshold has been exceeded at block712and/or that the core has been throttled at716. The thresh I_cc detector604may communicate the detection of block712and/or the throttling action of block716to the PMU108. In some embodiments, the PMU108may make a determination not to initiate the second-stage response. This may occur, e.g., if it is determined that the threshold will most likely be exceeded only for a short time period.

If the PMU108does initiate the second-stage response, the thresh I_cc detector604that took the throttling action may unthrottle the core, at block724, once the high voltage V_vid has been set. Unthrottling of the core may be done by ceasing whatever actions were instituted to reduce the input rate of the instructions. The unthrottled core may then operate at full capacity with the higher voltage.

In this manner, the thresh I_cc detector604may provide an interim response in the time period that it takes the PMU108to ramp up the set voltage. While throttling the core may be associated with reduced operating capabilities, this condition may occur infrequently enough and for a short enough period (until the PMU108can adjust the voltage V_vid accordingly) that any performance degradation may go undetected.

If the thresh I_cc detector604determines that detected events drop below a threshold at block728, the PMU108may reset the voltage to the low voltage V_id at block704.

System100may be implemented using any suitable hardware and/or software to configure the system100as desired.FIG. 9illustrates, for one embodiment, an example system900comprising one or more processors904, system control logic908coupled to at least one of the one or more processors904, system memory912coupled to system control logic908, non-volatile memory/storage device(s)916coupled to system control logic908, and one or more communications interfaces920coupled to system control logic908.

System control logic908for one embodiment may include any suitable interface controllers to provide for any suitable interface to at least one of the one or more processors904and/or to any suitable device or component in communication with system control logic908.

System control logic908for one embodiment may include one or more memory controllers to provide an interface to system memory912. System memory912may be used to load and store data and/or instructions, for example, for system900. System memory912for one embodiment may include any suitable volatile memory, such as suitable dynamic random access memory (DRAM) for example.

System control logic908for one embodiment may include one or more input/output (I/O) controllers to provide an interface non-volatile memory/storage device(s)916, and communications interface(s)920.

Non-volatile memory/storage device(s)916may be used to store data and/or instructions, for example. Non-volatile memory/storage device(s)916may include any suitable non-volatile memory, such as flash memory for example, and/or may include any suitable non-volatile storage device(s), such as one or more hard disk drives (HDDs), one or more compact disc (CD) drives, and/or one or more digital versatile disc (DVD) drives for example.

The non-volatile memory/storage device(s)916may include a storage resource physically part of a device on which the system900is installed or it may be accessible by, but not necessarily a part of, the device. For example, the non-volatile memory/storage devices916may be accessed over a network via the communication interface(s)920.

System memory912and non-volatile memory/storage devices916may include in particular, temporal and persistent copies of power management logic924, respectively. The power management logic924may include instructions that when executed by the processing unit904result in the system900performing power management operations described in conjunction with the PMU108described herein. In some embodiments, the power management logic924may additionally/alternatively be located in the system control logic908.

Communications interface(s)920may provide an interface for system900to communicate over one or more networks and/or with any other suitable device. Communications interface(s)920may include any suitable hardware and/or firmware. Communications interface(s)920for one embodiment may include, for example, a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem. For wireless communications, communications interface(s)920for one embodiment may use one or more antennas.

For one embodiment, at least one of the one or more processor(s)904may be packaged together with logic for one or more controllers of system control logic908. For one embodiment, at least one processor of the one or more processor(s)904may be packaged together with logic for one or more controllers of system control logic908to form a System in Package (SiP). For one embodiment, at least one processor of the one or more processor(s)904may be integrated on the same die with logic for one or more controllers of system control logic908. For one embodiment, at least one processor of the one or more processors904may be integrated on the same die with logic for one or more controllers of system control logic908to form a System on Chip (SoC).

In various embodiments, computing device900may have more or less components, and/or different architectures.