Scheduling threads on different processor cores based on memory temperature

Techniques for scheduling a thread running in a computer system are disclosed. Example computer systems may include but are not limited to a multiprocessor having first and second cores, an operating system, and a memory bank for storing data. The example methods may include but are not limited to measuring a temperature of the memory bank and determining whether the thread includes a request for data stored in the memory bank, if the temperature of the memory bank exceeds a predetermined temperature. The methods may further include but are not limited to slowing down the execution of the thread upon determining if the thread includes a request for data.

REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending application, application Ser. No. 12/508,552 entitled “Core Selection For Applications Running On Multiprocessor Systems Based On Core and Application Characteristics” filed Jul. 23, 2009.

BACKGROUND

Power density in microprocessors doubles every few years, and this rate of increase is expected to continue growing. Energy consumed by the microprocessor is converted into heat, and so the growth in power density results in a corresponding rise in heat density, leading to difficulties in reliability and manufacturing costs. Localized heating occurs faster than chip-wide heating, because power dissipation is spatially non-uniform. The resulting “hot spots” further compound the rise in heat density.

Design techniques to deal with the increasing heat density and hot spot have mostly focused on the thermal package, such as heat sinks and fans. Temperature-aware design, at all system levels including the chip architecture level, has also been considered. Temperature-aware design, which makes use of power-management techniques, may directly target the spatial and temporal behavior of operating temperature.

DETAILED DESCRIPTION

The following description sets forth various examples along with specific details to provide a thorough understanding of claimed subject matter. It will be understood by those skilled in the art, however, that claimed subject matter may be practiced without some or more of the specific details disclosed herein. Further, in some circumstances, well-known methods, procedures, systems, components and/or circuits have not been described in detail in order to avoid unnecessarily obscuring claimed subject matter. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and make part of this disclosure.

The present disclosure identifies that a DRAM memory system is a major shared resource among multiple processing cores in a CMP system. When accessing this shared resource, specific cores may be assigned to a specific application, or a specific thread within an application, for execution. Each application, or thread, may generate requests for data within memory, and specifically, within a specific memory bank within the memory. Too many requests for data within a specific memory bank may result in overheating of that specific memory bank, and ultimately an operating failure of that memory bank. The operating system may slow down a specific core, or cores, which may be making too many requests to a specific memory bank, in order to prevent overheating of that specific memory bank.

In light of the present disclosure, it is recognized that it may be suboptimal to slow down specific cores in order to prevent overheating of memory banks, since the cores may still be used for other tasks which do not require access to memory banks. As a result, the present disclosure recognizes that it may be desirable to prevent overheating of memory banks without having to slow down specific cores.

The present disclosure may make use of the discovery that by scheduling applications, or threads within applications, in response to the operating temperature of memory banks used by those applications or threads, overheating of memory banks may be prevented without having to slow down specific cores.

FIG. 1illustrates a computer system arranged according to at least some embodiments of the present disclosure.FIG. 1illustrates a computer100including a processor110, memory120and one or more drives130. The drives130and their associated computer storage media may be configured to provide storage of computer readable instructions, data structures, program modules and other data for the computer100. Drives130may include an operating system140, application programs150, program modules160, and database180. Operating system140and/or application programs150, for example, may include program instructions for causing the computer100to carry out the functions and/or operations specified inFIG. 4, for example, thread scheduling algorithm152. Computer100may include user input devices190through which a user may enter commands and data. Input devices may include an electronic digitizer, a microphone, a keyboard and pointing device, commonly referred to as a mouse, trackball or touch pad. Other input devices may include a joystick, game pad, satellite dish, scanner, or the like.

These and other input devices may be coupled to processor110through a user input interface that may be coupled to a system bus or it may be connected by other interface or bus structures, such as a parallel port, game port or a universal serial bus (USB), or the like. Computer100may include peripheral output devices such as speakers, a printer, or a display202, which may be connected through an output peripheral interface194or the like.

Computer100may be configured to operate in a networking environment using logical connections to one or more computers, such as a remote computer connected to network interface196The remote computer may be a personal computer (PC), a server, a router, a network PC, a peer device or other common network node, and may include many or all of the elements described above relative to computer100.

Networking environments may include offices, enterprise-wide area networks (WAN), local area networks (LAN), intranets and the Internet. In an example, computer100may be the source machine from which data is being migrated and the remote computer may comprise the destination machine, or vice versa. Source and destination machines may not be connected by a network108or any other means, but instead, data may be migrated via any media capable of being written by the source platform and read by the destination platform or platforms. In a LAN or WLAN networking environment, computer100may be connected to the LAN or WAN through a network interface196or an adapter. In a WAN networking environment, computer100may include a modem or other means for establishing communications over the WAN, such as the Internet or network108. Other means of establishing a communications link between the computers may be used.

A computer peripheral may include any device coupled to the processor110and the memory120of the computer100through the system bus. A computer peripheral may include any device connected with the output peripheral interface, including the display202, the printer, or speakers, drives130, user input devices190such as the keyboard, the mouse, and the microphone, and the network interface196. Components of the computer peripheral may include any device within a computer peripherals which may use power and may be any device, such as speakers, lighting elements such as light emitting diodes, or backlights used to provide lighting for displays, display elements, such as LCD, LED, OLED, CRT, or Plasma displays, or semiconductor chips such as a central processing unit (CPU), a graphic processing unit (GPU), memory. According to an embodiment, computer100may be connected in a networking environment such that the processor110and/or program modules160may perform power reduction and conservation with minimal detriment to the user experience.

In some examples, methods for scheduling a thread running in a computer system may be disclosed. The computer system (e.g., computer100) may include a multiprocessor having first and second cores, an operating system, and/or a memory bank for storing data. The methods may include measuring a temperature of the memory bank and determining whether the thread includes a request for data stored in the memory bank, if the temperature of the memory bank exceeds a predetermined temperature. The methods may include slowing down the execution of the thread upon determining if the thread includes a request for data.

In further examples, methods may be described for scheduling a thread running in a computer system, where the computer system (e.g., computer100) may include a multiprocessor having first and second cores, an operating system, and first and second memory banks for storing data. The methods may include measuring a first temperature of the first memory bank and a second temperature of the second memory bank and determining if any of the first and second temperatures exceeds a predetermined temperature. The methods may include slowing down the execution of the thread upon determining if the thread includes a request for data in a memory bank whose temperature exceeds the predetermined temperature.

In other examples, methods for scheduling a thread running in a computer system may be described where the computer system (e.g., computer100) may include a multiprocessor having first and second cores, an operating system, and a memory bank for storing data. A temperature of the memory bank may exceed a predetermined temperature. The methods may include using the operating system to slow down the execution of the thread.

FIG. 2illustrates an application program being executed by an operating system arranged in accordance with at least some embodiments of the present disclosure. As shown inFIG. 2, operating system140may execute an application program150from drives130. Operating system140and/or application programs150, for example, may include program instructions for causing the computer100to carry out the functions and/or operations specified inFIG. 4. Application program150may be any application, program, portion of a program, or thread, which may be executed by operating system140in multiprocessor111. Application program150may be arranged to load data230into memory120and accesses data230from memory120using a memory controller210. Application program150may be arranged to run multiple sub-applications called threads220to accomplish a task, such as loading and accessing data230into and from memory bank122of memory120using one or more requests226. Threads220may be executed by application program150. Application program150may be arranged to divide the execution of a task into as many threads220as application programs deems necessary to accomplish that task. For example, if application program150is a word processing program with a document having multiple pages, and application program150may be configured to accomplish the task of spell checking each page of the document, application program150may divide the task of spell checking the document into multiple threads220such that each thread220may spell check a portion of the document. Each thread220may be sent to multiprocessor111for execution. When executed within the multiprocessor111, each thread220may be adapted to produce requests226for data230within memory120. The requests226may be sent to memory controller210, which may organize the requests226so that multiprocessor111may be configured to operate efficiently.

In some embodiments, as shown inFIG. 2, multiprocessor111may include processors that may simultaneously execute more than one thread220. Multiprocessor111may include multiple processors known as cores412and512, or a single processor (only one of412or512) which may run multiple threads220simultaneously, also known as a multithreaded processor.FIG. 2illustrates an example multiprocessor111including two cores412and512, but is not limited to any particular number of cores. The term “core” may be used herein to refer to any device which may process a single thread and may refer to a processor or a portion within a processor that may process a single thread. A multithreaded processor may be referred to as a processor having multiple cores. A computer100having multiple processors may be referred to herein as a computer100having multiple cores. Also present is a temperature sensor700, for example, a thermocouple or a liquid thermometer, for measuring the temperature of the memory bank122.

FIG. 3illustrates a schematic representation of an application program being divided into threads which issue requests sent to a memory controller in accordance with at least some embodiments of the present disclosure. As shown inFIG. 3, application150may be divided into multiple threads220a-220n, where n may represent the number of threads220, and wherein each thread may perform a task for application150and may be executed on, for example, multiprocessor111ofFIG. 2. The multiprocessor may be configured to receive and execute multiple threads220a-220n, individually or simultaneously, from application program150. Each thread220executed on the multiprocessor may be executed independently from each other thread220and may issue multiple requests226a1-226nofor data230stored in memory120, where the first index (a . . . n) may represent the thread220associated with the request226, and the second index (1 . . . o) may represent the number of requests226associated with a particular thread220.

Each thread220may issue requests226for data230stored in memory120, and in an example, for data230stored in memory banks122a-122mwithin memory120, where the index (a, b . . . m) may represent the number of memory banks122. Memory120may include multiple memory banks122ato122mthat may be configured to allow multiple outstanding memory requests226to proceed in parallel if they require data230from different memory banks. As a result, first memory bank122aand second memory bank122bmay be accessed simultaneously by memory controller210upon receiving a request226for data230.

Each memory bank122may be a two-dimensional array, including columns C1to Ci, where the index (1 . . . i) may represent the number of columns, and rows R1to Rj, where the index (1 . . . j) may represent the number of rows. Rows may store data in consecutive memory locations and may be, for example, approximately 1-2 kilobytes (KB) in size. The data230in a memory bank122may be accessed from a row-buffer RB, which may contain at most one row. In an example, each memory bank122may contain one row-buffer RB. The time it takes to service each request226for data230may depend on the status of each row-buffer RBand may fall into one of three categories. The first category may be row hit, where a request226may be to a row that may be currently open in each row-buffer RB, allowing the memory controller210to issue only a read or write command to the respective memory bank122, resulting in a bank access latency of tCL.

The second category may be row closed, where there may be no open row in a row-buffer RB, so that the memory controller210may need to first issue an activate command to open a required row and then a read/write command, resulting in a total latency of tRCD+tCL, where tRCDis the latency for the activate command and tCLis the latency for the read/write command. The third category may be row conflict, where a request226may be to a row different from the one currently in a respective row-buffer RB, so that the memory controller210needs to first issue a precharge command and open the required row (by activating it), and issue a read/write command for data in the required row. These accesses may incur the highest total latency of tRP+tRCD+tCL, where tRPis the latency for the row precharge (to close it), tRCDis the latency for the activate command and tCLis the latency for the read/write command.

Memory controller210may be arranged in communication with memory120and the multiprocessor and may be located anywhere along the system, including within the multiprocessor. Memory controller210may include a memory request buffer211that may be arranged to buffer the requests226and the data230while the requests226may be waiting to be serviced. Memory controller210may include a scheduler212that may be arranged to select the next request226to be serviced [6,2,3]. In some embodiments, scheduler212may have two-levels. When selecting the next request226to be serviced, the scheduler212may be configured to consider the state of the memory banks122a-122mand the state of memory buses214a-214mconnecting the memory controller210to each memory bank122, and the state of a request226. A memory command for a request226may be scheduled by the scheduler212if its scheduling does not cause any resource, such as memory banks122a-122mand address/data/system bus, conflicts and does not violate any memory timing constraints. A memory command which does not cause any conflicts may be considered to be ready.

In some embodiments, computer100may include a multiprocessor110or111, that may have multiple cores412and512, and a memory bank122, as shown inFIGS. 1,2and3.

FIG. 4illustrates a flowchart in accordance with at least some embodiments of the present disclosure. As illustrated, to prevent overheating the memory banks or to minimize power usage, the scheduling of threads may be controlled by the operating system or an application program using a thread scheduling algorithm600. Thread scheduling algorithm600may be initiated at block601. Thread scheduling algorithm600may be initiated by the operating system or an application program.

Upon initiating thread scheduling algorithm600, the temperature of the memory bank may be measured at block602. The temperature may be measured using a remote sensor on the memory bank that may measure temperature or an embedded sensor within the memory bank that may measure temperature. The sensor may be any temperature sensor, for example, a thermocouple or a liquid thermometer. The thread scheduling algorithm600may be arranged to determine if the measured temperature exceeds a predetermined temperature, at block604.

The predetermined temperature may be either the temperature beyond which the memory bank fails to operate reliably or the temperature beyond which thermal damage to the memory bank may occur; operating the memory bank, and therefore the memory, at a temperature which exceeds the predetermined temperature may be harmful to the memory and the memory bank, and may reduce the reliability of the data stored within the memory banks. Alternatively, the predetermined temperature may be the maximum temperature at which the memory bank operates reliably. When minimizing power usage, the predetermined temperature may be set by the user, or may be selected by the user, an application program or the operating system, from a sliding scale predetermined by the manufacturer, and may be, for example, indicative of various power usage levels.

If the measured temperature does not exceed a predetermined temperature, the thread scheduling algorithm600may return from block604to block602. If the temperature of the memory bank exceeds the predetermined temperature, the thread scheduling algorithm600may proceed from block604to block606. At block606the thread scheduling algorithm600may determine if the thread includes a request for data in the memory bank. If the thread is determined to include a request for data in the memory bank, and the temperature of the memory bank exceeds the predetermined temperature, then the thread scheduling algorithm600may slow down the execution of the thread, at block608. If the thread does not include a request for data in the memory bank, then the thread scheduling algorithm600may end at block610.

The thread scheduling algorithm600may slow down the execution of threads in a number of ways. In some embodiments, the first and second cores412,512(FIG. 2) may be arranged to execute first and second task sets. Each task set may include a single thread or a plurality of threads. The thread scheduling algorithm600may be adapted to slow down the execution of a thread by determining which of the first and second task sets may be expected to be completed first and scheduling the thread to run on the core executing the task set that may not be expected to be completed first.

In some embodiments, the thread scheduling algorithm600may be adapted to slow down the execution of a thread by reducing the priority of execution of the thread. For example, operating systems typically assign each thread a priority value, such as a value of 1-5 or 1-100, with a greater value corresponding to a higher priority; the higher the priority, the greater the fraction of core time devoted to execution of the thread. The amount of the reduction of the priority value, for example, may be a fraction of the priority value, such as approximately 1% to 99%, including approximately 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% and 90% of the priority value. Alternatively, the priority value may be reduced by a single priority value unit, or the priority value may be reduced to the smallest priority value.

In some embodiments, the thread scheduling algorithm600may be adapted to slow down the execution of a thread by delaying the scheduling of the thread to run on a core, for example, by delaying the scheduling of the thread to run on one of the first and second cores412,512(FIG. 2) and scheduling the thread to run on one of the first and second cores412,512(FIG. 2) after the delay. The amount of the delay may be, for example, a fraction of the time the thread would nominally take to execute, such as approximately 1% to 99%, including approximately 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% and 90%. Alternatively, the amount of the delay may be, for example, a multiple of the amount of time the thread would nominally take to execute, such as 1 to 1000 multiples of the time the thread would nominally take to execute, including approximately 2, 5, 10, 15, 20, 50, 100, 200, 500, 600, 700, 800 and 900 multiples of the time the thread would nominally take to execute.

In some embodiments, upon slowing down the execution of a thread, the thread scheduling algorithm600may be adapted to re-measure the temperature of the memory bank, for example by starting thread scheduling algorithm600again. If the temperature of the memory bank is less than the predetermined temperature, the thread scheduling algorithm600may be adapted to schedule the thread in cores without slowing down the execution of the thread.

While various embodiments of the disclosed subject matter have been described, it will be apparent to those of ordinary skill in the art that other embodiments and implementations are possible within the scope of the disclosure. Accordingly, the disclosed subject matter is not to be restricted except in light of the attached claims and their equivalents.