Method of forming a MOS transistor with a litho-less gate

The width of the gate of a MOS transistor can be formed to have nanometer-width gate sizes, which are substantially less than the minimum feature size that can be photolithographically obtained with the method that is used to fabricate the MOS transistors, in a litho-less process by utilizing a conductive side wall spacer to form the gate of the MOS transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to MOS transistor gate structures and, more particularly, to a photolithographic-less, nano-technology gate structure with very low resistivity.

2. Description of the Related Art

MOS transistors are well-known semiconductor circuit elements.FIGS. 1A-1Dshow cross-sectional views that illustrate a prior-art method of forming MOS transistors. As shown inFIG. 1A, the method utilizes a semiconductor wafer100that has been conventionally formed to have a shallow trench isolation region STI that forms a number of laterally-isolated surface regions.

As further shown inFIG. 1A, the method begins by forming a gate insulation layer110on the top surface of semiconductor wafer100, followed by the formation of an overlying polysilicon layer112. After layer112has been formed, a mask114is formed and patterned on the top surface of layer112.

Following this, as shown inFIG. 1B, the exposed regions of polysilicon layer112are etched until the exposed regions have been removed from the top surface of gate insulation layer110, thereby forming a number of polysilicon gates116. Once the etch has been completed, mask114is removed.

Next, as shown inFIG. 1C, the exposed surfaces of gate insulation layer110and the polysilicon gates116are implanted with a dopant, such as boron or phosphorous. The implant both dopes the gates116and forms lightly-doped source and drain regions120and122, respectively, in semiconductor wafer100on opposite sides of each of the gates116.

Following this, a layer of isolation material, such as a layer of oxide, is deposited on the exposed surfaces of gate insulation layer110and the polysilicon gates116. As shown inFIG. 1D, once deposited, the layer of isolation material is then anisotropically etched to form side wall spacers124that contact the side walls of the gates116.

After the side wall spacers124have been formed, the exposed surfaces of gate insulation layer110and the polysilicon gates116are again implanted with the dopant. The implant both dopes the gates116and forms heavily-doped source and drain regions126and128, respectively, in semiconductor wafer100on opposite sides of each of the gates116.

Thus, at this point in the method, a number of MOS transistors, which each have spaced-apart source and drain regions120/126and122/128, an overlying gate insulation layer110, and an overlying gate116, have been formed. Following this, the method continues with conventional steps.

One problem with the prior-art method of forming MOS transistors is that the minimum size of the widths W of the gates116is limited to the minimum feature size that is photolithographically obtainable with the fabrication process that is used to form the MOS transistors.

Thus, since the gate widths W can not be reduced below the minimum photolithographic feature size that is obtainable with the fabrication process that is used to form the MOS transistors, the minimum photolithographic feature size limits the maximum number of MOS transistors that can be formed in a defined semiconductor surface region.

As a result, to increase the packing density, there is a need for a method of forming MOS transistors which can form the widths W of the gates to have a size that is substantially less than the minimum feature size that is photolithographically obtainable with the fabrication process that is used to form the MOS transistors.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2A-2Hshow plan views that illustrate an example of a method of fabricating MOS transistors with nanometer-width gate sizes in accordance with the present invention.FIGS. 3A-3Hshow cross-sectional views taken along line3-3ofFIGS. 2A-2Hthat correspond withFIGS. 2A-2H, respectively, in accordance with the present invention.

As described in greater detail below, the present invention provides a method of forming a MOS transistor that has a nanometer-width gate size, which is substantially less than the minimum feature size that can be photolithographically obtained with the fabrication process that is used to form the MOS transistor, by utilizing a conductive side wall spacer to form the gate of the MOS transistor.

As shown inFIGS. 2A and 3A, the method utilizes a semiconductor wafer200that has been conventionally formed to have a p conductivity type, and a shallow trench isolation region STI that forms a number of laterally-isolated regions on the top surface of wafer200. In the present example, p-wafer200and shallow trench isolation region STI are formed using conventional steps.

As further shown inFIGS. 2A and 3A, the method begins by forming a gate insulation layer210on the top surface of semiconductor wafer200, followed by the formation of an overlying sacrificial layer212. Gate insulation layer210can be implemented with, for example, a layer of oxide or a layer of a high-K dielectric material, such as La2O3, Al2O3, ZrO2, or HfO2.

Sacrificial layer212, in turn, can be implemented with a material which can be rapidly etched with an etchant that has a high selectivity to the gate insulation material and a to-be-described conductive layer of material, such as polysilicon. After sacrificial layer212has been formed, a mask214is formed and patterned on the top surface of sacrificial layer212.

Next, as shown inFIGS. 2B and 3B, the exposed regions of sacrificial layer212are etched until the exposed regions have been removed from the top surface of gate insulation layer210. In accordance with the present invention, the etch forms a number of sacrificial strips216. Once the etch has been completed, mask214is removed.

After this, a layer of conductive material, such as doped polysilicon, is formed on the exposed surfaces of gate insulation layer210and the sacrificial strips216. As shown inFIGS. 2C and 3C, the layer of conductive material is then anisotropically etched to form conductive side wall spacers220.

Following the etch, once the conductive side wall spacers220have been formed, the sacrificial strips216and the conductive side wall spacers220can optionally be planarized using conventional steps. The planarization step flattens the tops of the conductive side wall spacers220.

Next, as shown inFIGS. 2D and 3D, the sacrificial strips216are wet etched until the sacrificial strips216have been removed from the top surface of gate insulation layer210. The etchant can have a high selectivity with respect to gate insulation layer210and the conductive side wall spacers220. As a result, the sacrificial strips216can be removed, thereby leaving the conductive side wall spacers220on the top surface of gate insulation layer210, without removing substantial portions of gate insulation layer210and the conductive side wall spacers220.

After the sacrificial strips216have been removed, a gate mask222is formed and patterned on gate insulation layer210and the conductive side wall spacers220. Following this, as shown inFIGS. 2E and 3E, the exposed regions of the conductive side wall spacers220are etched until the exposed regions have been removed from the top surface of gate insulation layer210. The etch converts the conductive side wall spacers220into a large number of spaced-apart conductive gates224. After this, gate mask222is removed.

One of the advantages of the present invention is that the present invention allows the widths of the MOS gate structures to be formed for nano-technology applications in a process that does not require any photolithographic steps. The widths of the conductive gates224are defined by the widths of the conductive side wall spacers220.

The widths of the conductive side wall spacers220, in turn, are a function of the thickness of the layer of conductive material which is deposited and then etched to form the conductive side wall spacers220. Thus, to reduce a width W of a conductive gate224, reduce the thickness of the layer of conductive material. To increase the width W of a conductive gate224, increase the thickness of the layer of conductive material.

Thus, in accordance with the present invention, nano-width MOS gate structures, with widths that are substantially less than could be photolithographically obtained with the fabrication process, can be formed by varying the thickness of the conductive layer that is deposited and then etched to form the conductive side wall spacers220. In addition, the heights H of the conductive gates224can be varied by varying the thickness of sacrificial layer212.

Next, as shown inFIGS. 2F and 3F, a layer of silicide material is formed on the conductive gates224and insulation layer210, and then reacted in a conventional manner to form a number of silicide layers226that surround (the top, sides, and ends of) the conductive gates224. The reaction does not form any silicide layer on insulation layer210.

Another of the advantages of the present invention is that the present invention significantly reduces the resistivities of the conductive gates224. The resistivity of a conductive gate224is a function of the amount of surface area that has been silicided. In a conventional process, only the top surfaces of the conductive gates are silicided.

However, in the present invention, not only are the top surfaces silicided, but the side wall and end wall surfaces are also silicided. In addition, in the present example, the conductive gates224are formed so that the height H is approximately 10× larger than the width W. As a result, the present invention covers substantially more gate surface area than is conventionally the case. As a result, the conductive gates224of the present invention have substantially less resistance.

Once the silicide layers226have been formed, the exposed surfaces of gate insulation layer210are implanted with a dopant, such as phosphorous or boron. The implant forms lightly-doped source and drain regions230and232, respectively, in the top surface of semiconductor wafer200on opposite sides of each conductive gate224(with channel regions lying between the source and drain regions230and232).

Following this, as shown inFIGS. 2G and 3G, a layer of isolation material is deposited on the exposed surfaces of gate insulation layer210and the conductive gates224. The layer of isolation material is then anisotropically etched to form isolation side wall spacers236that contact the silicided side walls of the conductive gates224.

After the isolation side wall spacers236have been formed, the exposed surfaces of gate insulation layer210are implanted with a dopant. The implant forms heavily-doped source and drain regions240and242, respectively, in the top surface of the semiconductor wafer200on opposite sides of each conductive gate224(with the channel regions lying between the source and drain regions230and232).

After this, as shown inFIGS. 2H and 3H, the exposed regions of isolation layer210are removed to expose the surfaces of the source and drain regions240and242. (The exposed regions of isolation layer210can be alternately removed at the same time that the isolation side wall spacers236are formed.)

Next, the exposed surfaces of the source and drain regions240and242are silicided to form silicide layers250and252, respectively. Following this, the method continues with convention steps. Thus, a method has been described that forms a MOS transistor with a nano-width gate.

A further advantage of the present invention is that the method can be practiced using current-generation fabrication processes, e.g., 0.12-micron, 0.18-micron, and larger fabrication processes. The formation of nano-width MOS gates with current-generation fabrication processes represents a significant cost savings in the manufacture of a fabrication facility.

This is because the fabrication machines which use nano-width photolithographic processes are very sensitive to vibrations. As a result, these machines must be isolated from external vibration sources, and therefore require that significant vibration dampening systems be installed at the fabrication facility. The present invention eliminates the need to use these systems because nano-width devices can be fabricated using much larger fabrication processes.

It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.