METHOD AND APPARATUS FOR FAST SEARCHING GLOBAL NAVIGATION SATELLITE SYSTEM SIGNALS

A method and apparatus for fast searching GNSS signals performed on a GNSS receiver includes the steps of receiving a signal having a known pseudo random noise code. State information of a code generator is stored when a pseudo random noise code is generated. Several NCO, including a Doppler NCO are used to search GNSS signal for several supposed Doppler’s simultaneously. A search window associated with the received signal is reviewed a first time to identify a source of the received signal. After it is determined if a source of the received signal can be identified, the state information is loaded into the code generator prior to reviewing the search window a second time etc. Search windows is shifting by all length PRN Code. The loading of state information allows sequential review of the search window without readjustment of a fast search module which speeds the process of analyzing the received signals.

FIELD OF THE INVENTION

The present disclosure relates to navigation receivers and methods of signal processing and, in particular, to fast searching Global Navigation Satellite Signals (GNSS) and further processing signals of different systems such as the Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), and GALILEO satellite system, etc.

BACKGROUND

Global Navigation Satellite Systems (GNSS) use satellites to broadcast radio signals that are acquired by receivers. The receivers use the acquired signals in order to determine the location of the receiver. GNSS signals are often searched for using code delay and Doppler offset. Defining search window S as the number of simultaneously considered delays viewed by a search unit, the simplest way to search a plurality of channels uses components comprising a code generator, multiple numerically-controlled oscillators (NCO) including a code NCO (CRNCO) and an intermediate frequency NCO (IFNCO), and a correlator. Channels are configured to search one signal for one Doppler offset and, when initializing, a different code delay needs to be set for different channels. To search for a certain Doppler offset, a channel should be re-started/reset. This method requires a great number of channels wherein each is associated with its own correlator, code generator, CRNCO and IFNCO.

SUMMARY

The present disclosure relates generally to global navigation satellite systems (GNSS) and, more particularly, to a receiver for a GNSS system. In one embodiment, an apparatus for fast searching radio navigational signals having a known pseudorandom noise (PRN) code includes an antenna for receiving signals having a known PRN code. A radio frequency path is configured to receive the radio signals from the antenna and move those signals to an intermediate frequency signal. A numerically controlled oscillator is configured to output pulses at a period of PRN elements and an analog to digital converter (ADC) is configured to sample the intermediate frequency signal. A digital mixer is configured to receive signals from the ADC and output a sampled signal at a zero frequency. A decimator is configured to receive the sampled signal at the zero frequency from the digital mixer. A correlator is configured to calculate a convolution of shifted array of inputs received from the decimator via a pair of quantization units with non-shifted array of PRN code elements and a memory unit is configured to store a result of a value output from the correlator. A code generator is configured to calculate a new element according to the pulses output from the numerically controlled oscillator. An intermediate frequency numerically controlled oscillator is configured to output an intermediate frequency for the intermediate frequency signal. A fast search numerically controlled oscillator (FSNCO) outputting pulses at a preset period. In response to the output pulses of the FSNCO: the decimator is further configured to generate a new output sample, the correlator is further configured to shift a shifted array of input samples to include the new output sample, the correlator is further configured to shift a shifted array of PRN code elements to include a current state of a PRN code generator’s output, the correlator is further configured to copy the shifted array of PRN code elements to non-shifted array of PRN code elements one time during S pulses of the numerically controlled oscillator, the correlator is further configured to calculate a new convolution value and a metric of the new convolution value, a corrector is configured to compare the metric of the new convolution value with the stored result, and, if the new convolution value is greater than the stored result, then the new convolution value is stored instead of the stored result, and a fast search module is configured to determine the availability of a signal with a known PRN code and its parameters in the received radio signal once every S*k pulses for at least one value of the stored result.

In one embodiment, a Doppler numerically controlled oscillator (DopNCO) is configured to output a Doppler phase once in S pulses of the FSNCO. In this embodiment, at least D-1 digital phase shifters, where D-1 is an even integer, rotate the new convolution value into a phase proportional to the phase at the DopNCO output. The memory unit is further configured to store D*S values. In this embodiment, for each pulse of the FSNCO the following operations are performed: in each of D-1 phase shifters, the value output from the correlator is rotated into a phase proportional to the phase of DopNCO output to generate D-1 rotated phase convolution results, obtained D-1 rotated convolution results as well as a non-rotated convolution result are added to previous values in the memory unit configured to store D*S values, and the obtained D results of adding are stored in the memory at the same address, and the metric of the new convolution value is calculated according to the result of adding the rotated/non-rotated convolution result and the previous values in the memory unit configured to store D*S values.

In one embodiment of the apparatus, at Kth period of S pulses, obtained D-1 metrics based on the obtained D-1 rotated convolution results, are input to the memory unit configured to store D*S values. Also at Kth period of S pulses, obtained metrics based on non-rotated results are input to the memory unit configured to store D*S values for storing the result, and once every S*k pulses, the availability of a signal with a known PRN code and its parameters in the received radio signals is determined.

In one embodiment of the apparatus, a reload generator stores the state of a code generator in S+1 pulse, and, at S*k+1 pulse when at the end of the incoherent period, the reload generator loads the stored state of the code generator into the code generator.

In one embodiment, the apparatus further comprises a coherent counter and a not-coherent counter, wherein the coherent counter sums convolution values for each S, and the not-coherent counter is used for S if needed and the values obtained are stored in the memory unit configured to store D*S values.

In one embodiment, the apparatus further comprises a control accumulator comprising N cyclically shift registers that are moved forward at a rate of the FSNCO, the input to the control accumulator set to 0 based on a configuration.

In one embodiment of the apparatus, addition of estimates during data sorting comprise the results of Doppler metrics during the period S*k and Doppler metrics for each offset are separately sorted.

In one embodiment, a method fast searching radio navigational signals includes the step of receiving radio signals at an antenna, the radio signals having a known PRN code. The radio signals from the antenna are transmitted to an RF path which then transmits the signals using an intermediate frequency. The intermediate frequency signal is sampled at an ADC. A digital mixer generates a sampled signal at a zero frequency based on signals received from the ADC. A shifted array of inputs is transmitted from a decimator in response to the decimator receiving the sampled signal at the zero frequency. A convolution of the shifted array inputs received from the decimator via a pair of quantization units is calculated with a non-shifted array of PRN code elements. A result of a value output from the correlator is stored in a first memory unit. A code generator calculates a new element according to pulses output from the numerically controlled oscillator. Pulses at a preset period are output from a fast search numerically controlled oscillator. A decimator generates a new output sample based on the pulses at the preset period. The correlator shifts a shifted array of input samples to include the new output sample. The correlator also shifts a shifted array of PRN code elements to include a current state of a PRN code generator’s output. The correlator also copies the shifted array of PRN code elements to non-shifted array of PRN code elements one time during S pulses of the numerically controlled oscillator. The correlator also calculates a new convolution value and a metric of the new convolution value. A corrector compares the metric of the new convolution value with the stored result, and, if the new convolution value is greater than the stored result, then the new convolution value is stored instead of the stored result. A fast search module determines the availability of a signal with a known PRN code and its parameters in the received radio signal once every S*k pulses for at least one value of the stored result.

In one embodiment, a method for fast searching GNSS signals performed on a GNSS receiver includes the steps of receiving a signal having a known pseudo random noise code. State information of a code generator is stored when a pseudo random noise is generated. The pseudo random noise is associated with the pseudo random noise code. A search window associated with the received signal is reviewed a first time to identify a source of the received signal. After it is determined if a source of the received signal can be identified, the state information is loaded into the code generator prior to reviewing the search window a second time. The loading of state information allows sequential review of the search window without re-adjustment of a fast search module which speeds the process of analyzing the received signals. In one embodiment, the search window is shifting by all length PRN code.

In one embodiment, the received signal is processed by a control accumulator using a plurality of multiplexed signals on a fast search numerically controlled oscillator frequency. One of the plurality of multiplexed signals can be zeroed. This zeroing causes the zeroed signal to be ignored in the analysis of the plurality of signals. In one embodiment, the received signal is multiplied by an intermediate frequency prior to the determining if a source of the signal can be identified. In one embodiment, a rotation angle is added to the received signal. The rotation angle can be based on a Doppler numerically controlled oscillator. The results generated while reviewing the search window can be stored in a coherent mode or a not-coherent mode. The not-coherent mode allows searching for signals with superimposed data.

In one embodiment, at the end of the incoherent period and when the coherent counter counts K periods of S pulses, all not-coherent metric are added, and the result being read by the CPU.

In one embodiment, at the end of the incoherent period and when the coherent counter counts K periods of S pulses, the availability of a signal with a known PRN code and its parameters in the received radio signals is determined among D*S not-coherent metrics, and the result being read by the CPU,

DETAILED DESCRIPTION

A method and apparatus for fast searching of satellite signals comprises a receiver receiving and processing signals transmitted from global navigation satellite system satellites.

FIG.1shows receiver110for receiving and processing satellite signals. In one embodiment, a satellite signal including pseudo random noise (“PRN”) is received by antenna100. The received signal passes through RF-path101(1) to analog to digital convertor (ADC)102(1). From ADC102(1), the converted signal is transmitted to satellite channel103(1) and Fast Search Module (FSM)104(1). Satellite channel103(1) and FSM104(1) receive a digitized signal transferred to an intermediate frequency. FSM104(1) implements signal searching based on the intermediate frequency and a reference code delay. Satellite channel103(1) processes the digitized signal from ADC102(1). It should be noted that multiple sets of RF paths101(1) to101(R), ADC102(1) to102(R), satellite channel103(1) to103(C), and FSM104(1) to104(F) can be utilized. It should be noted that in cases where multiple similar paths are shown in a figure, only one channel may be described and the other, similar paths, should be understood to be configured and function similarly to the path described.

Timing module105synchronizes control of FSM104(1) and satellite channel103. Timing module105counts out the pre-set number of clock pulses and generates interruption in central processing unit (CPU)106. CPU106controls timing module105, FSM104and satellite channel103. CPU106processes the information from FSM104and Channel103and transmits data to user108via communication module107.

FIG.2shows details of FSM104(1) shown inFIG.1. Although only the configuration and operation of FSM104(1) is described herein, additional fast search modules used in receiver110are configured and operate similarly. In one embodiment, FSM104(1) comprises the following components which interact with various signals. FSM104(1) includes a code rate numerically controlled oscillator (NCO)201(referred to as a CRNCO), code generator202, intermediate frequency NCO (IFNCO)204, reference code (reference Pseudo Random Noise (PRN) sequence) S203, decimator205, Fast Search NCO (FSNCO)206, divided fast search frequency S207, quantization unit208, quantization unit209, partial parallel correlator210, the number of “units 1” for component I S211, the number of “units 1” for component Q S212, rotation unit213, doppler NCO (DopNCO)214, rotated signal (D...2) S215, searcher216, signals from control counters S217, signal of ending the operation of the delay counter (equal to S403) S218, control counters219, packer220, memory unit221, commutator222, control accumulator223, reload generator224, divider225, corrector226, correlation signal of component I S227, correlation signal of component Q S228, signal of ending the operation of the delay counter via the initial unit; (equal to S417) S229, signal of ending the operation of the not-coherent counter S230, digital mixer231, control searcher232, signal of reading from the memory unit S233, signal of writing to the memory unit S234, and intermediate frequency signal S235.

In one embodiment, FSM104requires initialization prior to searching for a signal selected by CPU106. In one embodiment, the following operations are performed during initialization. Commutator222electrically connects to one of ADC102(1) though102(R) based on a desired signal to be analyzed. Control accumulation223is adjusted as needed. The frequency of the pseudo random noise generator (PRN) in CRNCO201is set and divider225is adjusted, if needed. Generator code202and reload generator224are adjusted, if needed. Intermediate frequency S235in the oscillator/generator IFNCO204is set. The fast search frequency in the oscillator FSNCO206is set. The Doppler frequency in the oscillator DopNCO214is set. Values for units402,405, and408are adjusted in Control Counter219. The settings in quantizers208and209are adjusted. And corrector226, packer220, and partial parallel correlator210are adjusted.

After initialization FSM104operates as follows according to an embodiment. IFNCO204, CRNCO201, and FSNCO206operate based on a signal from timing module105. IFNCO204generates intermediate frequency signal S235which is fed to digital mixer231. A fast search frequency from FSNCO206is input to control accumulation223and divider225. Then a signal from the selected ADC102is fed to control accumulation223from commutator222. If needed, in control accumulator223the input signal is set to 0. The signal from the output from control accumulator223is input to digital mixer231. The fast search frequency is divided by divider225, if necessary. Divider225then outputs the divided fast search frequency signal S207which is input to decimator205, partial parallel correlator210, and control counters219.

In digital mixer231, the signal from Control Accumulator223and IFNCO204are multiplied and input to decimator205. Decimator205receives the signals from digital mixer231and accumulates and stores them with divided fast search frequency S207. The stored signals are input to quantizers208and209. Quantizers208and209output quantized signals which are input to partial parallel correlator210.

Oscillator CRNCO201generates a code frequency which is input to reload generator224and code generator202. Code generator202generates a reference code S203which is a PRN code. Reload generator224is used for re-initialization of code generator202when necessary. Reference code signal S203is input to partial parallel correlator210. In one embodiment, code generator202can generate different code types including multiplexed code, BOC code, MBOC code, Memory Code and others. In one embodiment, unit202comprises a frequency code divider and a meander generator for generating a code.

Divided fast search frequency signal S207is fed to the input of Control Counters219. Control Counters219generates control signals S217, S218, S229and S230. Signal S217is fed to Control Searcher232, Searcher216and Packer220. Signal S218is input to DopNCO214, signal S229is input to partial parallel correlator210, and signal S230is input to CPU106.

Signals from control counters S217include the following information: delay number S401, coherent counter threshold trigger signal S406, signal of finding MAX S412, signal of ending the operation of not-coherent counter S413, searcher’s frequency S420, signal of starting accumulation process S421.

In partial parallel correlator210, the signals from output208, output209, and signal S203are used for correlating with divided fast search frequency S207. In-time-correlated signals S211and S212are output from partial parallel correlator210.

Signals S211and S212are input to corrector226. In corrector226, mathematical operations depending on the correlation time in partial parallel correlator210are produced. Signals S227and S228are output from corrector226.

Signal S218is input to DopNCO214. Based on signal S218, DopNCO214generates new rotated signals S215(D...2). Signals S227, S228and S215are input to rotation unit213. In rotation unit213, signal S215is used to rotate signals S227, S228.

Control searcher232, generates a signal S233when reading from memory unit221and generates a signal S234when writing to memory unit221. Control searcher232transmits information from memory unit221to Searcher216(1),216(2),...216(D) and communicates with memory unit221via packer220. Control searcher232generates signals S233and S234based on frequency transmitted by searcher S420, and control searcher232reads and writes to memory unit221via packer220.

Searcher216performs coherent and not-coherent actions using signals S227and S228(output from rotation unit213) for each delay number S401and the results are stored in memory unit221. Temporary results of calculations are read and written from/to memory unit221via packer220. Maximal results are also chosen and saved among all the results at the latest interval of coherent and not-coherent storing. The chosen results are metrics. CPU106reads the obtained metrics from searcher216.

In the given example, N = 2 M. Before operation, CPU106writes values in register700. The output signal from FSNCO206is fed to unit223. Using Fast Search Frequency, the value from700(1) is written to700(2), from700(2) it is written to700(3), from700(N-1) it is further written to700(N), and from700(N) it is written to700(1). The output of register700(N) is connected to the input of700(1) and to the control input of switch701. The output of commutator222is fed to the input of switch701. The output of switch701is connected to the input of Digital mixer231. When 0 is available at the output of700(N), the signal from the output of unit222is fed to the output of701. When 1 is available at the output of700(N), value “0” is fed to the output701.

FIG.7Bshows a standard operation mode. Processor106writes 0 in all registers700. A signal from commutator222is input to control accumulation unit223. In the standard operational mode, a signal from the input to the output transmitted without any change. In this mode, Divider225lets the frequency FSNCO206pass without its dividing.

FIG.7Cshows a process of operating in a non-accumulation mode. In this embodiment, the number of registers700is equal to 4 identified as registers700(1)700(2),700(3) and700(4). Processor (CPU)106writes the following values into registers700:700(1) = 0,700(2) = 1,700(3) = 0,700(4) = 1. As an example, the operational mode is described with the absence of one chip of FSNCO206. A signal from commutator222is input to control accumulation unit223. The input signal is set to zero using a chip of FSNCO206. One chip of FSNCO206is equal to zero at the output, the next chip-signal at the output is equal to the input signal and so on. In this mode, divider225divides frequency FSNCO206into 2.

Digital mixer231transfers the digitized signal passed233to the zero frequency. Frequency IFNCO204is input to digital mixer231. Frequency IFNCO204is input to cosine unit300and sine unit301of digital mixer231. The output of Cosine unit300is input to multiplier302, where it is multiplied by the output of control accumulation unit223. The output of sine unit301is input to multiplier303, where it is multiplied by the output of control accumulation unit223. The outputs of units302and303are input to decimator205.

The output of unit302is input to summing unit304, where it is added to the output signal of register306passing through switch310. The output of unit303is input to summing unit305, where it is added to the output signal of register307passing through switch311. The output of unit304is input to register306. The output of unit305is input to register307.

A sum of results from units304and305over time are stored in register306and307. In accordance with signal S207, values from registers306and307are written in buffers308and309. According to signal S207, zero from the output of switch310is input to summing unit304. And according to signal S207, zero from the output of switch311is input to summing unit305. The output of buffer308is fed to the input of quantization unit208. The output of buffer309is fed to the input of quantization unit209. If needed, the output of control accumulation unit223can be set to zero, then, the outputs of multipliers302and303are zero as well.

Returning toFIG.7B, according to signal S217, the value of registers306and307are equal to zero. The input signal of control accumulation unit223is transmitted to the output of Decimator205, and the values are stored in registers306and307.

Returning toFIG.7C, according to signal S217, the value of registers306and307are equal to zero. Then, control accumulation unit223sets values of registers306and307to zero. Due to this, in registers306and307there is a value of zero for a certain time. When this setting to a value of zero is over, values again are stored in registers306and307. The process then begins again.

FIG.4Ashows details of control counters219shown inFIG.2. Control counters219, in one embodiment, comprises the following components which interact with various signals including delay counter400, delay number S401, threshold delay counter402, coherent counter404, threshold coherent delay unit405, coherent counter threshold trigger signal S406, not-coherent counter407, threshold not-coherent delay408, not-coherent counter threshold trigger signal S409, AND gate410, AND gate411, signal searching for MAX/find MAX signal S412, signal identifying ending the operation of the not-coherent counter S413, signal identifying ending the operation of the coherent counter S414, AND gate415, signal identifying ending the operation of the delay counter S417, start of operation418, AND gate419, frequency signal from searcher S420, and start of accumulation S421.

In the process of initializing FSM104, CPU106starts control counters219and assigns threshold delay counter402, threshold coherent delay unit405, threshold not-coherent delay unit408.

After initialization delay counter400is set to 0, coherent counter404is set to 0, and not-coherent counter407is set to 0. Divided fast search frequency signal S207is input to control counters219. Signal207is also input to delay counter400, AND gate415, and AND gate419.

If S207is input to delay counter400, 1 is added to the current value. Output signal of unit400is input to threshold delay counter402. The output of unit402is connected to input of AND gate415. If the value at the input of threshold delay counter402is equal to the threshold set by CPU106, then, if S207is input to unit415, the signal of ending the operation of the delay counter S417is generated. According to signal S417, delay counter400takes value 0.

The signal of ending the operation of the delay counter S417is input to delay counter400, initial unit416, start unit418, and partial parallel correlator210. Delay number signal S401is the output of unit400. Delay number signal S401is input to searcher216. The signal of ending the operation of the delay counter S417is the same as S229.

Initial unit416blocks the first pulse of the signal of ending the operation of the delay counter S417, in order to keep zero in units404and407. Such a blocking corresponds to the initial time (seeFIGS.4B/C/D). Signal of ending the operation of the delay counter S417passed through the initial416is delay counter end signal passed through the initial is S403.

Signal S403is input to coherent counter404, AND gate416, and DopNCO unit214. Delay counter end signal passed through the initial module S403is the same as S218.

If S403is input to coherent counter404, then 1 is added to the current value. The output of unit404is input to threshold coherent delay405. The output of unit405is connected to input of AND gate416. If the value at the input of threshold coherent delay405is equal to the threshold set by CPU106, then, if S403is available at the input of unit416, the signal of ending the coherent counter operation S414is generated. According to signal S414, coherent counter404takes value 0.

Signal S414is input to coherent counter404, not-coherent counter407, AND gate411. Coherent counter threshold trigger signal S406is output from unit405. Signal S406is input to searcher216and operation AND unit410.

If S414is input to not-coherent counter407, 1 is added to the current value. The output signal of unit407is input to threshold not-coherent delay unit408. The output of unit408is connected to AND gate411. If the value at the input of threshold not-coherent delay unit408is equal to the threshold set by CPU106, then, if S414is input to unit411, the signal of ending the operation of the not-coherent counter S413is generated. According to S413, unit407takes value 0.

Signal S413is input to not-coherent counter407, searcher216and CPU106. Note that signal S413is the same as S230which is fed to CPU106. Signal S409is output from unit408. Signal S409is input to AND gate410and AND gate411. Signals S406and S409are input to AND gate410. If S406and S409are input unit410, the signal of searching for MAX S412is generated.

Signal S417is input to start unit418. The output of unit418is input to AND gate419. The output signal of unit418is input to AND gate419which does not allow S207to pass through AND419, until the first pulse of S417occurs. That is, the signal output from AND gate419occurs after delay counter400has counted up to the threshold assigned in unit402, then reset (the full cycle of the delay counter400takes place).

Signal S420is the output signal of unit419.Signal S421is fed to the output of start unit418. After initialization, S421= 1. When the first pulse of signal S417is input to start unit418, signal S421is value 1. When the second pulse of signal S417comes to unit418, signal S421is value 0. Signals S421and S420are input to searcher216.

Delay counter400counts 0 up to S-1, where S-1 is the maximal number being programmed in the threshold delay counter402.

Signals from Control Counters S217include delay number signal S401, coherent counter threshold trigger signal S406, signal searching for MAX S412, signal indicating ending the operation of the not-coherent counter S413; signal identifying frequency of searcher S420; and signal indicating start of accumulation S421.

FIGS.4B,4C, and4Doperational diagrams of control counters219for the three configuration versions:

FIG.4Bshows Example 1 in which: the threshold delay counter402= 3; the threshold coherent delay405=1; and the threshold not-coherent delay408= 1;

FIG.4Cshows Example 2 in which: the threshold delay counter402= 3; the threshold coherent delay405= 0; and the threshold not-coherent delay408= 2;

FIG.4Dshows Example 3 in which: the threshold delay counter402= 3; the threshold coherent delay405= 2; and the threshold not-coherent delay408= 0;

FIG.5shows details of partial parallel correlator210shown inFIG.2which comprises code shift register (in scheme C)500(1),500(2),500(3),500(S), component I shift register (in scheme I)501(1),501(2),501(3),501(S), reference code shift register (in scheme RC)502(1),502(2),502(3),502(S), component Q shift register (in scheme Q)503(1),503(2),503(3),503(S), multipliers504(1),504(2),504(3),504(S), multipliers,505(1),505(2),505(3),505(S), summing units506, summing units507, key508(S), key509(S)

In one embodiment, initialization of partial parallel correlator210is started by keys508and509.

In one embodiment, partial parallel correlator210operates as follows. Reference code signal S203is a bit number having values that can be 1 or 0. Quantizer208and209output the signs of values fed to the input. A bit number with values 0 and 1 is outputted at the output of units208and209.

Signal S207is input to partial parallel correlator210. Code shift registers500(1),500(2),500(3), and500(S) fix the data if signal S207is available. Reference code signal S203is input to code shift register500(1). Then the output signal from500(1) is input to shift register500(2). The output signal from shift register500(2) is input to shift register500(3). The output signal from shift register500(3) is input to shift register500(S).

Component I shift registers501(1),501(2),501(3), and501(S) and component Q shift register503(1),503(2),503(3), and503(S) fix data if S207is present. The signal output from unit208is input to shift register501(1). Then, the output signal of shift register501(1) is fed to the input of shift register501(2). The output signal from the output of shift register501(2) is fed to the input of shift register501(3). The output of shift register501(3) is input to shift register501(S). The output signal of unit209is input to component Q shift register503(1). Then, the output signal of shift register503(1) is fed to the input of shift register503(2). The output signal from the output of shift register503(2) is fed to the input of shift register503(3). The output of shift register503(3) is input to shift register503(S).

Reference code shift register502fixes data if S229(S417) is present. The output signal of500(1) is fed to the input of502(1). The output signal500(2) is fed to the input of502(2). The output signal of500(3) is fed to the input of502(3). The output signal of500(S) is fed to the input of502(S). Values in unit502does not change until next S229(S417) signal is available.

In units500,501and503, the values are moved according to signal S207. The output signals from501(1) and502(1) are input to multiplier504(1). The output signals from501(2) and502(2) are input to multiplier504(2). Similarly, the output signals from501(3) and502(3) are input to multiplier504(3). The output signals from501(S) and502(S) are input to multiplier504(S). Note that the output signal of unit504is a bit. Values of units501and502are multiplied in unit504. The output signal from unit504is input to unit506.

Part of higher digits of unit504goes through key508. If needed, part of outputs of unit504is not input to unit506. In one embodiment, whether the outputs of unit504are not input to unit506depends on the threshold written by CPU106in the threshold counter delay402.

Output signals from503(1) and502(1) are input to multiplier505(1). Output signals from503(2) and502(2) are input to multiplier505(2). Output signals from503(3) and502(3) are input to multiplier505(3). Output signals from503(S) and502(S) are input to multiplier505(S). Output signals from each of505(1),505(2),505(3) and505(S) are each a bit. Values of units503and502are multiplied in unit505. Output signal from unit505is fed to unit507.

Part of higher digits of unit505goes through key509. If needed, part of outputs of unit505is not input to unit507. In one embodiment, whether the outputs of unit505are input to unit507depends on the threshold written by CPU106in the threshold counter delay402.

The number of units 1 fed from outputs of unit504is outputted at the output of unit506. The number of units 1 fed from outputs of unit505is outputted at the output of unit507. The sum from the output of unit506is connected to the number of “units 1” for component I S211. And the sum from the output of unit507is connected to the number of “units 1” for component Q S212.

It should be noted that, in one embodiment, code shift register500is a shifted array of elements of PRN code. Component I shift register501и component Q shift register Q are a shifted array of input samples. Reference code shift register502is a non-shifted array of elements PRN code. A convolution of shifted array501and non-shifted array502is calculated in partial parallel correlator210using units504and506, the result of this convolution is signal S211.

A convolution of shifted array503and non-shifted array502is calculated in partial parallel correlator210using units505and507, the result of this convolution is signal S212.

FIG.8shows details of corrector226shown inFIG.2. Corrector226comprises X2 multiplier800, X2multiplier801, summing unit802, summing unit803, and constant804. In one embodiment, initialization of corrector226occurs as follows. Before operation, CPU106sets a value in unit804and the maximal value of a constant in unit804is equal to S.

In one embodiment, operation of corrector226occurs as follows. Signal S211is input to X2 multiplier800(output of unit506). In X2 multiplier800, the incoming number is multiplied by 2. The output signal from X2 multiplier800is input to summing unit802. In summing unit802, a constant from the output of unit804is subtracted from the value from the output of X2 multiplier800. The output of summing unit802is input to Searcher216(1) and Rotation unit213. The output of summing unit802is signal S227.

Signal S212is input to X2 multiplier801(output of unit507). In X2 multiplier801, the input value is multiplied by 2. The output of X2 multiplier801is input to constant803. In constant803, from the value of the output of unit801is subtracted the constant from the output of unit804. The output of unit803is input to searcher216(1) and Rotation unit213. The output of unit803is S228.

The signal representing the number “1” at the output506(S211) is the result of the convolution501and502, from Corrector226the mathematically correct convolution number501and502is sent to the output S227.

The signal representing the number “1” at the output507(S212) is the result of the convolution503and502, from corrector226the mathematically correct convolution number503and502comes to the output S228

When initializing FSM104, the following values are used with the components identified. Threshold counter delay402is equal to S-1 or smaller, key508and key509are on or off, and constant804is equal to S or smaller.

The expressions for outputs of Corrector226are as follows:

The following two examples show connections between S227, S228,402,508,509, and804and the tables show values of outputs and constants and contain a description of different scenarios.

The number of processed delays is S = 1023.

The threshold counter delay402= S-1 =1023-1=1022. Counter delay400counts from 0 up to 1022.

Output of506Output of800multiplied by 2Output of802Formula summing units (506)*2 -constantConstantDescription1023204610231023 * 2 - 10231023All units equal +1 are fed to the input of unit506Positive units 1023. Negative units 012- 10211 * 2 - 10231023A unit 1 is fed to the input of unit506. Value is -1021, as +1 has taken one negative unit from the sum. Positive units: 1. Negative unit 1022.5001000- 23500 * 2 - 10231023500 units are fed to the input of unit508. The value is -23, as +500 has taken -500 from the sum Positive units: 500 Negative unit 523.

Reduce the number of the processed delays by 2.

508(S)509(S)508(S-1)509(S-1) is disabled. Value504(S)504(S-1) not connected to input508. Value505(S)505(S-1) not connected to input509.

Output of506Output of800multiplied by 2Output of802Formula summing units (506)*2-constantConstantDescription1021204210211021 * 2 - 10211021All units equal +1 are fed to the input of unit506Positive units 1021. Negative units 012- 10191 * 2 - 10211021One unit 1 is fed to the input of unit506. Value is -1019, as +1 has taken one negative unit from the sum. Positive units: 1. Negative unit 1020.5001000- 21500 * 2 - 10211021500 units are fed to the input of unit508. The value is -21, as +500 has taken -500 from the sum Positive units: 500 Negative unit 521.

FIG.6shows details of searchers216(1),216(2), and216(D) as shown inFIG.2. In one embodiment, searcher216comprises components for receiving and outputting various signals including input correlation signal of component I S601, input correlation signal of component Q S602, summing unit of component I603, summing unit of component Q604; read signal component I S605, read signal component Q S606, read signal estimation S607, switch608, switch609, switch610, estimation calculation unit611, summing unit for estimation612, write signal component I S613, write signal component Q s614, write signal estimation S615, switch616, switch617, switch618, output signal of component I S619, output signal of component Q S620, output signal of estimated S621, MAX622, and switch623. Signals S619and S620are the coherent metric. Signal S621is the not-coherent metric.

In one embodiment, operation of searcher216is as follows. When Searcher216interacts with memory221, reading/writing data is implemented via packer220. In searcher216, all the operations are performed in series for signal S401which is the address for Memory unit221: S605S606S607are read from Memory221;603,604units add input and read-out data for components I, Q;611performs estimation of the obtained sums for components I, Q;612adds input and read-out estimated data; S613S614S615are written to memory221component I, Q and estimation; and622selects maximal estimated values.

All operations in searcher216are performed according to signal S420. Control searcher232implements the control of data processing in searcher216. Control searcher232generates the control of writing/reading data from memory221. According to signal read from memory S233there is reading of data from memory221. According to signal write from memory S234data are written to Memory221.

After the above operations, the reset signal S421is set equal to 1. It remains value 1 during the first and second periods of delay counter400.

During the first period of operating the delay counter400there is no signal S420, within this time period units500,501and503are filled according to signal S207, and this time period is the initial time (SeeFIGS.4B,4C, and4D). According to signal S417values from component500are re-written to component502. Further, components500501and503are filled according to signal S207, the values in component502do not change, until signal S417occurs. The result of convolution for units501502503passes through corrector226and is input to searcher216as signals S227and S228. Signal S601is the same as S227and signal S602is the same as S228.

Each value of signals S601and S602corresponds to their delay number S401. And delay counter400operates in cycles, and signals S601and S602come depending on cyclically-repeated delay number S401. Respectively, input values of signals S601and S602can be sequentially processed for each delay.

During the second period of operating delay counter400signal S421is 1. According to signal S420, signals S601and S602are sequentially processed. Component I S605, component Q S606, and estimation S607are read from memory for the current delay S401. Signal S605is fed to unit608, signal S606is fed to unit609, and signal S607is fed to610. Since signal S421is active, zero is fed to the output of units608609610.

The output signal from unit608is input to component603. The output signal from unit609is input to component604. The output signal from unit610is input to component612.

For the current value S401, signal S601is input to component603. For the current value S401, signal S602is input to component604. Values of signal S601and output608are added in unit603. Values of signal S602and output of unit609are added in unit604. Signal S619is the output of unit603. Signal S620is the output of unit604.

At S421= 1, the data read from the memory are zeroed, and a new coherent or, if needed, not-coherent convolution accumulation is started for units501,502and503.

Signals S619and S620are input to component611. The following mathematical operation is performed by component601:

The output value from unit611is input to component623. If S406=0, the output of component623= 0 as well. If S406= 1, the output signal from component611is input to component623. The output signal from component623is input to component612. Output610and output623are added in unit612. Signal S621is the output of component612.

At S406= 1, there is not-coherent accumulation of convolution results for components500501and503. Signal S619goes to input of component616. Signal S620goes to input of component617. If S406is equal to “1”, then outputs616and617are set to “0”. If S406is equal to 0, then signal S619is fed to the output of component616, and S620is fed to the output of component617. Signal S613is the output of component616. Signal S614is the output of component617. Signals S613and S614are written to memory221via packer220. If S406= 1 then coherent accumulation is zeroed for convolution501,502and (if S406= 1 then coherent accumulation is zeroed for convolution501502503). At the next period of delay counter400, signals S605and S606= 0, i.e., components I and Q are equal to 0, and coherent accumulation of convolution results in units501,502, and503starts anew.

Signal S621is input to component618. If S412=1, then the output value of unit618= 0. If S412= 0, then S621is fed to the output of component618. Signal S615is the output of component618. Signal S615is written to memory221via packer220.

If S412= 1, then not-coherent accumulation is zeroed for convolution501,502and503(if S412= 1 then not-coherent accumulation is zeroed for convolution501502503). At the next period of delay counter400, signals S607= 0, i.e., estimation unit is equal to 0, and not-coherent accumulation of convolution results in units501,502, and503starts anew.

Signals S613, S614and S615are written to memory221for the current value of delay number S401.

For each delay number S401, signal S601is added to the value from memory S605and stored in memory as signal S613. Signal S601is stored during the whole operational period of coherent counter404.

For each delay number S401, signal S602is added to the value from memory S606and stored in memory as signal S614. Signal S602is stored during the whole operational period of coherent counter404.

For each delay number S401at the output of unit611values are calculated for signals S619and S620. For each period of coherent counter404a sum of the output value from unit611and the value from memory610, this sum is stored within operation period of not-coherent counter407.

For each delay number S401at the end of operation of coherent counter404, signals S613and S614being written to Memory221are set to 0 according to S406.

For each delay number S401at the end of operation of not-coherent counter407, signal S615being written to Memory221is set to 0 according to S412.

For each delay number S401, if S412is available at the end of operating not-coherent counter407, signals S619S620S621, results of coherent and not-coherent convolution501,502and503are fed to unit MAX622.

FIG.9shows the details of MAX622shown inFIG.6. The following signals are received by MAX622: output of the component I S619, output of the component Q S620, output of estimated S621, delay number S401, find MAX S412, signal of ending not-coherent counter operation S413, searcher frequency S420,

MAX622includes components that transmit and receive various signals including control MAX900, data901(1)...901(M), buffer for sorted data902(1)...902(M), summing units903, register904, signal indicating that searching for MAX/find MAX is occurring S905, signal indicating that searching for MAX has ended S906, buffer907, signal indicating search result for a single delay, signal of sorting data S909(1), S909(2), S909(3),...S909(M), AND gate910, and sorting signal S911.

In one embodiment, MAX622operates as follows. MAX622is a sorting device to sort input data during period of component407, the sorted-out data being stored and read by CPU106after completing the operation period of component407. When initializing,901,902,904, and907are all set equal to zero.

In one embodiment, the following signals are input to MAX622: output of the component I S619, output of the component Q S620, output of the Estimation unit S621, delay number S401, signal indicating find MAX S412, signal indicating ending of operation of the not-coherent counter S413, signal identifying searcher frequency S420.

Signals S412and S420are input to component910. If S412and S420are equal to 1 (signal is available), then the output of unit 910= 1 (signal is available). The output of unit910is the same as signal S911. Signal S911is input to control MAX900.

Signals S619, S620, and S621, which were obtained within not-coherent counter407operation, come together with each delay number S401in MAX622. A search result for a single delay S908includes signals: S401, S619, S620and S621.

The following signals are input to control MAX900: output of the component I S619, output of the component Q S620, output of the estimated signal S621, delay number S401, signal of sort S911, and signal indicating ending the operation of the not-coherent counter S413.

When S911is input to control MAX900, signal S908is sorted for each signal S401. Sorting S908is implemented using signal S621. Sorting lasts the whole period of operating not-coherent counter407. Signal S909is the sorted-out values S908. Signals S909from unit900are input to unit901(1),901(2),901(3),...,901(M) and stored there. The number of sorted values is M. When sorting S908is over, value in unit901is updated if needed.

When signal S413confirming the end of operating not-coherent counter407is detected, control MAX900waits for sorting end signal S908for the last value of S401. When sorting is completed, signal S906is output. Sorted values S909are written to data901(1),901(2),901(3),...901(M).

Signal S906from control MAX900is input to the following components: buffer for sorted data902(1),902(2),902(3),...,902(M), register904, and buffer907. When sorting is completed, the value from unit901is written to buffer902(1),902(2),902(3),...902(M) according to signal S906. According to signal S906, values in units901are set to 0.

Sorting continues for the next operation period of not-coherent counter407. Data902is stored until next S906signal is received. CPU106reads values from902(1),902(2),902(3),...902(M).

Signal S905at the output of unit900is the same as signal S911.

Signal S621is input to adder903. The output of register904is input to summing units903and Buffer907. Signal S621and the output signal of unit904are added in unit903. The output of unit903is fed to the input of unit904. A sum of S621values for each delay number S401is stored in unit904during operation period of not-coherent counter407if S905(S911) is available.

According to signal S906, the stored sum S621from register904is written to unit907, and values in the register904are set to 0. When the next operation period of not-coherent counter407starts, and first signal S911arises, the input value of unit904is set to 0. A sum of not-coherent values for each signal S401is stored in register904during operation of signal S412= 1 if signal S420is available. The value from Buffer907is read by CPU106.

FIG.10shows a flow chart of a method for sorting search results for a single delay in control MAX900where the method begins at start operation1001. A sorting signal is generated at generation signal sort1002, and conditions1003(1),1003(2),1003(3),...1003(M) are checked and operations1004(1),1004(2),1004(3),...1004(M) are performed based on the conditions.

In one embodiment, the operation of sorting unit in control MAX900is in accordance with the method ofFIG.10as follows.

Data sorting in control MAX900starts if signal S911is detected. Data sorting is performed based on the output signal of the estimation unit S621. Signal S621is the input estimate. A search result for a single delay S908includes signals: S401, S619, S620and S621. Estimate 1 is signal S621from Data901(1). Estimate 2 is S621from Data901(2), and Estimate 3 is S621from Data901(3). So, Estimate M is signal S621from Data901(M).

During initialization unit901is set to 0. Once FSM104has been initialized, the signal is input to begin at start1001. From step1001the flow chart goes to step1002. At step1002, the method analyzes signal S911. If S911= 0, the flow chart loops to step1001and then it comes back to unit1002. If S911= 1, the flow chart proceeds to1003(1).

At step1003(1), condition “input estimate is greater than estimate 1” is analyzed. If this condition is not satisfied, then the method proceeds to step1003(2). If condition in step1003(1) is satisfied, the following operations are carried out: Data901(M-1) is written to Data901(M); Data901(2) is written to Data901(3); Data901(1) is written to Data901(2); S908is written to Data901(1); and then the method returns to start1001.

At step1003(2) condition “Input estimate is greater than estimate 2” is analyzed. If condition1003(2) is not satisfied, the method proceeds to step1003(3). If it is satisfied, the following operations are carried out: Data901(M-1) is written to Data901(M); Data901(2) is written to Data901(3); S908is written to Data901(2); Data901(1) does not change; and then the method returns to start1001.

At step1003(3) condition “Input estimate is greater than estimate 3” is analyzed. If condition1003(3) is not satisfied, the method proceeds to step1003(4). If it is satisfied, the following operations are carried out: Data901(M-1) is written to Data901(M); S908is written to Data901(3); Data901(2) does not change; Data901(1) does not change; and then the method returns to start1001.

At step1003(M) condition “Input estimate is greater than estimate M” is analyzed. If condition1003(M) is not satisfied, the method proceeds to start1001. If it is satisfied, the following operations are carried out: S908is written to Data901(M); Data901(3) does not change; Data901(2) does not change; Data901(1) does not change; and then the method returns to start1001.

FIG.11shows details of packer220shown inFIG.2. Packer220, in one embodiment, includes components that transmit and receive various signals including data unpacker1100, address S1101, read data S1102, read S1103, write S1104, write data S1105, and pack data1106.

In one embodiment, packer220operates as described as follows in conjunction withFIGS.11and2. In the process of signal searching in conjunction with DopNCO214, rotation units213(2)...213(D) and searchers216(1),216(2),...216(D) obtained results are written and read to/from memory221via packer220. Using signal S401as address S1101, signals S613, S614and S615pass through data packer1106and are written to memory221in one word. Write data S1105comprises data that is written to memory unit221in a similar manner.

Using signal S401as address S1101, data is read from memory221(or similarly read signal read data S1102) as one word. Signal S1102passing through data unpacker1100is unpacked to generate signals S605, S606and S607which are then transmitted to searcher216.

The results of operation of searcher216are signals S613, S614and S615which are written to memory221at address S1101. The bit number in signals S613, S614and S615can exceed bit number in the word write data S1105. As a result, signals S613, S614and S615can be packed in a different way.

For example, at the input of packer220there are integers, but in packer220they are transformed into floating format, where the floating number is mantissa and exponent, all the numbers having a common exponent. The mantissa is kept/different for each number, but the exponent is common. The exponent is chosen such that all high-order digits would lie within the mantissa.

Signals S615(1), S615(2),...S615(D) from outputs of searchers216(1),216(2),...216(D) are combined by the common exponent. Signals S613and S614from outputs of searcher216(1),216(2),...216(D) are also combined by the common exponent. The mantissa and exponents of signals S615, S613and S614obtained at data packing are fed to the output of data packer1106. In data pack1100data, read from the memory, are unpacked considering mantises, exponents and operation mode of packer220.

In one embodiment, packer220is initialized when CPU106starts operation of packer220. In one embodiment, packer220operates as follows.

S401is input to packer220. Signal S1101is the same as signal S401. Signal S1101is input to memory unit221as an address. Signal S1102is input to data unpack1100of data read from memory221. In memory unit221, S1105is input as written data from unit1106.

Signal S233(1) is input to packer220. Signal read S1103is the same as signal S233. S1103is input to memory unit221as a read. If signal S233is detected, data are read from memory unit221at address identified by signal S1101, and signal S1102goes to the input of unit1100, where they are unpacked. From data unpack1100these signals are input to: searcher216(1) which receives signals S605(1), S606(1) and S607(1); searcher216(2) which receives signals S605(2), S606(2) and S607(2); and searcher216(D) which receives signals S605(D), S606(D) and S607(D).

Signal S234(1) is input to packer220. Signal write S1104is the same as signal S234. S1104is input to memory221as a write.

In data pack1106, signals input are packed as follows: signals S613(1), S614(1) and S615(1) are output from searcher216(1); signals S613(2), S614(2) and S615(2) are output from searcher216(2); and signals S613(D), S614(D) and S615(D) are output from searcher216(D).

If signal S234is available, data packed in1106are written (write data S1105) to Memory221at address S1101write data S1105.

There are different packing and unpacking modes for storing temporary data in unit221depending on searcher216modes and the number of Doppler NCO.

Here are some examples:

Result: In this case there no need to keep data from signals S613S614S615in memory221.

Result: In this case there is no need to keep data from signal S615in memory221. In memory221there are kept only data from signals S613and S614.

3) Condition: The capacity of signal S613and signal S614has a greater priority than capacity of signal S615.

Result: To pack data from signal S613and signal S614, a lower-digit exponent and higher-digit mantissa are used. For signal S615, a higher-digit exponent and lower-digit mantissa are kept.

4) Condition: The capacity of signal S615has a greater priority than capacity of signal S613and signal S614.

Result: To pack data from signal S615, a lower-digit exponent and higher-digit mantissa are used. For signal S613and signal S614, a higher-digit exponent and lower-digit mantissa are kept.

5) Condition: In memory221there is enough space for values of signals S615, S613and S614.

FIG.12shows details of Doppler NCO214shown inFIG.2. Doppler NCO214generates rotation signal S215(D),... S215(3),S235, S215(2)... S215(D-1) Each rotation signal S215is used to generate Left Doppler or Right Doppler frequency.

Intermediate Frequency S235serves as Center Doppler frequency. Right Doppler frequency 1 generates S215(2), Left Doppler frequency 1 is generated mirror-like using signal S215(3). Right Doppler frequency D/2 generates signal S215(D-1) and Left Doppler frequency D/2 is generated mirror-like using S215(D-1).

In FSM104Doppler Frequency is generated with a step of Fdop, these frequencies include: Center Doppler; Left Doppler 1; Right Doppler 1; Left Doppler D/2; and Right Doppler D/2.

Left Doppler frequency (D/2... 1) and Right Doppler frequency (D/2... 1) change in phase available by S218(equal to S403) considering S length of shift registers500,501,502,503and unit402set by CPU106. The expression for calculation of Fdop is as follows.

where: FIFis Intermediate Frequency S235; S is the length of shift registers500,501,502,503(delay counter400counts from 0 up to S-1); and N is the bit number of Doppler NCO phase; d[N-1:0] the number written to the Doppler NCO214.

Signal S215from the output of Doppler NCO214is input to rotation unit213. Signals of component I S227and signal of component Q S228are input to rotation unit213. In each rotation unit213signals S227and S228are rotated in phase in an angle set by S215. Its own rotation signal S215(D...2) is generated for Left Doppler (D/2...1) and Right Doppler (D/2... 1), S227and S228rotate phase in a different way.

In unit213(D) signals S227and S228are rotated in phase at frequency Left Doppler D/2 (S215(D) is used) and are fed to the input of Searcher216(D).

In unit213(D-1), signals S227and S228are rotated in phase at frequency Right Doppler D/2 (S215(D-1) is used) and are fed to the input of Searcher216(D-1).

In unit213(3), signals S227and S228are rotated in phase at frequency Left Doppler 1 (S215(3) is used) and are fed to the input of Searcher216(3).

In unit213(2), signals S227and S228are rotated in phase at frequency Right Doppler 1 (S215(2) is used) and are fed to the input of Searcher216(2).

Signals S227and S228are fed to the input of Searcher216(1) at Intermediate Frequency S235.

The operation of shift registers500,501,502, and503and reload generator224will now be explained using an example including several tables showing values at different points in time. Assume, S =4, code length = 12, generated frequency CRNCO201is equal to frequency of FSNCO206. The state of code generator202is memorized as 5thchip of FSNCO206and uploaded in 13thchip of FSNCO206. Table rows500,501/503, and502show chip numbers for code chips generated by code generator202during initialization and during the steps performed to detect a signal.

Initialization of500501503DescriptionChip number generated by FSNCO206and CRNCO2011234500---------1------12---1231234501/503---------3------34---3453456502------------------------------------------------event------------

Step 1 searching for code for chip numbers of Reference Code 1 2 3 4DescriptionChip number generated by FSNCO206and CRNCO20156785002345*345645675678501/503456756786789789105021234123412341234event*state of unit202is memorized---------

Step 4 Searching for the chip numbers of Reference Code 5 6 7 8DescriptionChip number generated by FSNCO206and CRNCO201171819205006789**789108910119101112501/503456756786789789105025678567856785678event**the state of202is memorized502matches501/503------

Step 7 Searching for code of chip numbers of Reference Code 9 10 11 12DescriptionChip number generated by FSNCO206and CRNCO201293031325001011121***111212121231234501/503456756786789789105029101112910111291011129101112event*** the state of unit202is memorized---------

The table for step 9 shows that the signal was detected (steps 4-6), the sum of convolution results for registers501502503for numbers 18 22 26 of the generated chip FSNCO206and CRNCO201. Reference Code for the 5th code chip generated by code generator202matched.

The capabilities of FSM104shown inFIG.2include the following. In operation with FSM104, it is possible to get a sliding window/searching window S that determines the number of viewed code delays at the same time.

To increase sensitivity of searching or in the case of code length greater than S, it is necessary to increase search time in k times. Search time can be increased thanks to coherent accumulation. An increase in accumulation time can be also possible when information symbols imposed/overlapped on code by not-coherent accumulation are available.

If code length is greater than S, reload generator234can be also used and, after starting operation of FSM104the sliding window/search window S is moved along the whole code length, and metrics can be obtained for all delays.

With Fast Search NCO206, different numbers of delays can be set for one CODE chip. For example, two semi-chips are used for one GPS CA chip, and frequency Fast Search NCO206is twice as much as CRNCO201.

Multiplexed code is used at least as two chip by chip codes. Using fast search NCO206, control accumulation unit223and divider225, one code can be sent into searching mechanism, and the other code set to zero in the input signal. Doppler NCO214and Rotation unit213allow obtaining results for a plurality of Doppler frequencies for the searching window S.

Different operational modes of Packer220make it possible to select a preferable value: component I or component Q, or estimate during data packing/unpacking. At the end of searching period S*k, when metrics are sorted, estimates of all S are added.

Using FSM104it is possible to receive CSK-modulated signals. For example, in the process of receiving GPS CA signal using semi-chips CODE the frequency of unit Fast Search NCO206is twice as much as frequency CRNCO201, data are coherently accumulated within 2 milliseconds and S =1023, threshold not-coherent408set 0. In this case, the convolution results of all registers501,502, and503are coherently stored during 4 periods of operating delay counter400for each S, at the 4th period unit MAX622sorts metrics.

It should be noted that reload generator224remembers the state of code generator202at the 1023+1-th chip of fast search NCO206and records the memorized state of unit202so that code generator can start at once from this state in/to the 1023*4+1-th chip of fast search NCO206. Setting data make it possible to view2046GPS CA semi-chip CODE without re-adjusting FSM104.

FIG.13depicts a flow chart of method1300for fast searching global navigation satellite system signals according to an embodiment. In one embodiment, method1300is performed using navigation receiver110shown inFIG.1. At step1302, a signal is received at the receiver. The signal has a known pseudo random noise code. At step1304, state information of a code generator is stored when a pseudo random noise is generated by the code generator. The state information, in one embodiment, is the information pertaining to the code generator that is required to be input into the code generator in order to generate the same pseudo random noise previously generated. In one embodiment, the pseudo random noise generated by the code generator is associated with the pseudo random noise code of the signal. At step1306, a search window associated with the received signal is reviewed a first time. The search window, in one embodiment, comprises a string of data obtained from the received signal. As described above, the reviewing is to attempt to identify a source of the received signal (i.e., the satellite that transmitted the received signal). At step1308, it is determined if a source of the received signal can be identified. After a source is identified, the information can be used to determine the position of the receiver. At step1310, the state information previously stored in step1304is loaded into the code generator prior to reviewing the search window a second time in response to the determining. The loading of the state information into the code generator allows sequential review of the search window without re-adjustment of FSM104. In one embodiment, the received signal is processed by a control accumulator using a plurality of multiplexed signals on a fast search numerically controlled oscillator frequency. One of the plurality of multiplexed signals can be zeroed. Zeroing one of the signals causes the zeroed signal to be ignored in the analysis of the plurality of signals. In one embodiment, the received signal is multiplied by an intermediate frequency prior to the determining in step1308. In one embodiment, a rotation angle is added to the received signal. The rotation angle can be based on a Doppler numerically controlled oscillator. The results generated while reviewing the search window can be stored in a coherent mode or a not-coherent mode. The not-coherent mode allows searching for signals with superimposed data.