Intra die variation monitor using through-silicon via

An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

FIELD OF THE INVENTION

The present invention relates to methodologies and apparatus for monitoring within die variations caused by local process variability within semiconductor chips.

BACKGROUND

In the microelectronic fabrication industry, there is often a need to evaluate the effect of local process variability on individual transistors across a chip. For example, often times data pertaining to electrical properties of field effect transistors (FETs) based on variations in a process is required. More specifically, it may be required to evaluate the variation of PFET and NFET threshold voltage with respect to process environment variations experienced during fabrication. As an example, threshold voltage (Vt) may vary within a chip; for example, due to variations in gate length caused by reactive ion etching (RIE) load variation or photo resist planarization variations. In another example, a pattern density of various material stacks can modulate the rapid thermal anneal (RTA) temperature locally and may cause as much as 100 mV variation in threshold voltage (Vt) within a chip. One approach to this problem is to measure an electrical property of multiple transistors and then to characterize across chip variation based on those measurements. This approach, however, can require a very large sample size of transistors to provide adequate data for variations over many length scales. For example, the characterization does not enable an evaluation of a direction of the process environment variation on the chip.

Within chip variation impact on product power-performance and circuit functionality is increasingly important. Various structures have been developed to monitor the within chip variation, and currently the most powerful solution is to place embedded within-chip variation monitor or intra die variation monitors (IDVMON). IDVMON is a small structure containing a few key devices that can be subsequently measured; IDVMON are placed numerous times across chip, in space not used by other circuits or structures. The threshold voltage and device current may be measured for a transistor that is part of IDVMON. When a resistor is utilized the resistance variation amongst the multiple IDVMONs utilized. In addition to quantification of within-chip variation, IDVMON can also serves as a structure to debug and calibrate product line-centering by measuring the product-kerf offset. Direct measurement of across-chip variation provides detailed information for variation reduction efforts. Identical structures to monitor offset between functional blocks and provide guidelines for line centering.

Measuring the electrical properties of devices embedded in IDVMON currently requires additional CA and M1masks (contact A and metal1masks), which may result in a cost increases. The IDVMON specific CA/M1masks are used to wire IDVMON to large probe pads, which will enable test. The probe pads consume large area, particularly on M1. Therefore within chip variation monitors and product and characterization circuits cannot be wired up on the same wafer as a standard production wafer because the IDVMON CA/M1layers will consume large amount of metal wiring space. Therefore the IDVMON CA/M1is different from the POR mask. POR is a process of record mask or standard mask which utilizes standard procedures for manufacture. Wafers running with an IDVMON mask, have to be sacrificed which prevents characterizing these structures frequently in production runs.

Recently, there is a strong demand to enable a 3D VLSI chip by stacking two or more chips. 3D VLSI chips employ Through-Silicon Vias (TSVs) in the wafer. The devices used in 3D VLSI chips may have different device characteristics from those in conventional 2D VLSI chips because of the proximity effect between device and TSV, and wafer thinning effect. It is important to study the 3D process impact on device variability during development and manufacturing. The purpose of this invention is to provide an IDVMON for 3D VLSI chips development and manufacturing.

SUMMARY

The inventors have proposed a new and novel approach to allow for the use of IDVMONs without the need to utilize a separate CA/M1mask for 3D VLSI chips. More specifically, the inventors propose connecting IDVMON monitors with through silicon via (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area. By utilizing the TSV to provide access to the IDVMON, the inventors not only permit testing of the wafer without damaging the wafer to access the test probe pads, but they allow for continuous testing beyond the first CA/M1layer. The advantages of utilizing these embodiments described and claimed include: (a) no added cost (for CA/M1mask) by utilizing the invention the IDVMON may be incorporated into the production mask by placing it in locations that are not in contact with the production; (b) since the IDVMON is incorporated into the production mask, the same wafer can be utilized for both within-chip variation study and product characterization, (c) increases flexibility for product yield debug by direct monitoring of IDVMON closer to the primary die areas, (d) Enables backside probing for the IDVMON (e) allows to study the device effect because of the non-fill, TSV to device proximity, and wafer thinning effect. for 3D chip.

Through-silicon via for 3D-integration is emerging as a new technology offering. Typically TSV density is very sparse because they are mostly used for wiring between large functional blocks. The low density allows us to utilize TSV to wire up IDVMONs that may be distributed across the chip. IDVMON is used to monitor layout density pattern driven within chip variation and thus can be sparsely placed every 1-2 mm. With such a low placement density, the inventors have determined that through silicon via is an ideal choice to wire up IDVMONs for probe testing.

The detailed implementation includes the IDVMON and probe pad arrangement between TSVs with various spacing between TSV and the devices on IDVMON. The IDVMON may be included in the center of the annular TSV thereby utilizing space that otherwise goes unused.

DETAILED DESCRIPTION

Referring to the drawings,FIG. 1shows prior art embodiment of a structure100for evaluating the effect of a process environment variation across a chip102. Structure100includes a plurality of electrical structures104arranged in a non-collinear fashion for determining a magnitude and a direction of a process environment variation in the vicinity of plurality of electrical structures104. The process environment variation may include practically any environmental characteristic that varies during a particular fabrication process, e.g., etching, annealing, material deposition, ion implanting, etc. For example, a process environment variation may include a spacer etch variation, a photolithography exposure variation, a gate length variation, a variation in film deposition, and an anneal temperature gradient. While three electrical structures104A-C are shown, it is understood that any number of electrical structures104greater than or equal to three may be used. Each electrical structure is positioned at an X-coordinate and a Y-coordinate within chip102such that the three (or more) structures are not collinear. As illustrated, only electrical structures104A and104B share a Y coordinate, i.e., Y1Y2. In one embodiment, where three electrical structures104A-C are used, this results in a substantially triangulated arrangement. The triangular arrangement does not need to be any particular type of triangle, e.g., isosceles, right, etc. Electrical structures104A-C are interconnected, via interconnects110, to a plurality of probe pads106. As illustrated, electrical structures104A-C are interconnected by four probe pads106A-D, but more may be employed where more electrical structures104are used.

Electrical structures104may take the form of a variety of different electrical devices. In one embodiment, electrical structures may each include a resistor, a diode or a ring oscillator. In this case, each end (input or output) of the aforementioned devices are coupled as indicated inFIG. 1.FIG. 2Ashows another prior art embodiment employing doped polysilicon resistors120A-C. As illustrated, resistors122A-C are interconnected to probe pads106A-D.FIG. 2Bshows another prior art embodiment employing diodes122A-122C. As illustrated, diodes120A-C are interconnected to probe pads106A-D.FIG. 2Cshows another embodiment employing ring oscillators124A-C. As illustrated, ring oscillators124A-C are interconnected to probe pads106A-D, and output signals of each ring oscillator124A-C are connected to a signal probe pad126.

Turning toFIG. 3in another prior art embodiment, each electrical structure104may include a plurality of transistors. InFIG. 3, two transistors130A-B are shown, respectively. However, it is understood that any number of transistors130A-B greater than or equal to two may be used. In the transistor embodiment, each electrical structure104may include a first polarity field effect transistor (FET), e.g., a NFET130A, coupled to a second polarity FET, e.g., a PFET130B. It is understood that the position of each type FET may be switched from what is illustrated. First polarity FET130A and second polarity FET130B are each coupled to a first probe pad206A and a second probe pad206B. With this structure, independent measurement of first polarity FET130A and second polarity FET130B using only first probe pad206A and second probe pad206B is made possible. The electrical property measured may be varied depending on the particular structure provided.

With specific reference toFIG. 3, in one version of the transistor embodiment of electrical structure104, gates140and drains142of first polarity FET130A and second polarity FET130B are coupled to first probe pad206A, and sources144of first polarity FET130A and second polarity FET130B are coupled to second probe pad206B. In this case, each electrical structure104employs measurement of a threshold voltage (Vt).

As can be seen in the prior art designs the probe pads such as206A and206B are not easily accessed for testing. As stated above to access the probe pads the wafer must be sacrificed to be accessed. The issue of the probe pad location causes a conflict between ACV (across chip variation) readout in early product providing enough hardware for ramp up analysis. Functional study and variation study are not using the same hardware, and disallow non-interrupting ACV monitoring.

A most fundamental concern of the existing IDVMON approaches is a probe pad and their arrangement, because a probe pad set requires not only a large area but also blocks the wiring. This results in using unique mask sets only for IDVMON, however this approach is not preferred because the IDVMON cannot use used for the actual product routing as discussed. To enable the product mask set without sacrificing the expensive silicon area in a product, the inventors have a new and novel invention. The inventors have determined by utilizing TSV (Through Silicon Vias) the IDVMON may be tested from probe pads located on the backside of the wafer. Arranging the probe pad set on the back side overcomes the probe pad area and their arrangement concern, because the wafer back side has significantly more free space than the front side.

FIG. 4illustrates a three dimensional top view of an embodiment of the invention. IDVMON401may be located on the kerf of the wafer or other free space and on a layer determined by the designer. Lines410and420are provided to connect IDMOV401with capture pads430and440respectively. Capture pads430and440are in electrical contact with TSVs450and460. TSVs450and460are in electrical contact with capture pads435and445respectively. Capture pads435and445are located on the bottom layer of the wafer and connected via lines415and425respectively to back side probe pads470and480. In this embodiment it is noted that the probe pads470and480are significantly larger than IDVMON401itself. Although the invention requires TSVs and capture pads, the silicon overhead for TSV w/5 um diameter is <1% of conventional >50 um probe pad arrangement. In addition, some 3D technology may require dummy TSVs to improve the TSV processes. Therefore, the dummy TSVs may be used for the backside probe pad connection for the IDVMON. By either providing TSVs for the IDVMON or utilizing unused TSVs for the IDVMON the inventors have provided a means wherein the IDVMON may be monitored without damaging the product wafer. In addition, since the IDVMON is accessible via the backside probe pads, the IDVMON may be tested repeatedly as additional layers are added right up until the final layer is provided. IDVMON is preferably arranged near the TSVs430and440, which allows us to detect the TSV and IDVMON proximity effect as well as the IDVMON characteristic change during the 3D wafer thinning process.

FIG. 5illustrates a schematic diagram of multiple IDVMONs located on the front side of the wafer connected to TSVs510,512,514,516, and518on the front side of the wafer. The TSVs are connected to probe pads (not shown) on the backside of the wafer. The schematic illustrates a plurality of IDVMONs520,522,524, and526in this case FETs. While only four IDVMONs are shown, it should be clear that any number of IDVMONs may be provided based on the desires of the design engineer. Each IDVMON is electrically connected via a line to a TSV. IDVMON520is connected via line530to TSV510, in a similar manner IDVMON522is connected via line532to TSV512. In the same manner IDVMON524and526are connected via lines534and536to TSVs514and516respectively. One end of each of the IDVMONs520,522,524, and526is connected via line545to TSV505the other end of each of the IDVMONs is connected via line535to TSV518. In this manner each of the IDVMONs may be connected together and located through the wafer while allowing the TSVs to connect to a probe pad (not shown) on the backside of the wafer.

FIG. 6illustrates a cross section of a wafer with TSVs, which includes backend of line (BEOL). The illustration provides how an IDVMON620provides a connection via lines630through lines635to TSV612and TSV610. The connection via line630, in this example, includes metal1-10to connect the TSV610, where the metal10is the capture metal (or capture pad). The IDVMON620is located on Contact layer A, CA. The IDVMON620may be located on the kerf or other free space. In this example, the TSV610is coupled to a higher metal layer (metal10); however this can be connected to any other metal layer (i.e. metal1). It is important to know that stacking the metal near TSVs does not penalize the expensive silicon area, because the area cannot be used for device and their wiring. This is because the TSV blocks the wiring layers and the area cannot be used for a device to avoid a device proximity effect (device keep out zone).FIG. 6Aillustrates a cross section view of the wafer600illustrating that IDVMON620is located on the front side of the wafer600and the TSV's610and612pass through to the backside of the wafer.

FIG. 7illustrates a top down view of another embodiment of the invention. As stated earlier the IDVMON may be located in any free space the designer finds appropriate. In this embodiment annular rings are utilized for TSV710,712, and718. IDVMON720may be located within the annular ring710and IDVMON722may be located within the annular ring712. IDVMON720may be connected to TSV710by line730as IDVMON722may be connected to TSV712by line732. Line745may connect IDVMON720and722and lines735and737may connect IDVMON720and722to TSV718.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. For example, although the description assumes to use a common mask to a product for the IDVMON, the idea is applicable to use IDVMON unique mask to further reduce the silicon area overhead, Even if additional masks are used for IDVMON, the masks are significantly less expensive than those for the existing CA and M1IDVMON approach, because the TSV customization is done by using much higher metal layers (i.e. metal10). As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.