Copper interposer for reducing warping of integrated circuit packages and method of making IC packages

A stacked die integrated circuit assembly comprising: 1) a substrate; 2) a first integrated circuit die mounted on the substrate; 3) a copper interposer mounted on the first integrated circuit die; and 4) a second integrated circuit die mounted on the copper interposer. The copper interposer significantly reduces the warping of the stacked die IC assembly caused by the warping of the substrate due to thermal changes in the substrate. The copper interposer has a significantly higher coefficient of thermal expansion than a conventional silicon (Si) interposer. The higher CTE enables the copper interposer to counteract the substrate warping.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuit (IC) packages and, more specifically, to a stacked die ID package using a copper interposer to reduce warping of a substrate.

BACKGROUND OF THE INVENTION

The size of integrated circuit (IC) packages continues to decrease even as the complexity and level of circuit integration in the IC packages continue to increase. This is particularly true in the case of system-on-a-chip (SoC) devices, in which most, if not all, of an electronic appliance is integrated onto a single integrated circuit (IC) die. Thus, relatively complex devices, such as cell phones, network interface cards (NICs), communication buses, and the like, are now being implemented as a single integrated circuit or perhaps only several integrated circuits.

In addition to packing as many circuits as possible onto a single integrated circuit (IC) die, manufacturers are also packing as many IC dies as possible onto circuit board. In order to further this objective, manufactures place IC dies as close together as possible on a substrate to thereby increase IC die density. However, in some designs, manufacturers also stack IC dies vertically in order to improve the packing density of the integrated circuit dies.

In a stacked chip arrangement, a first IC die is mounted on a substrate by means of, for example, a solder ball grid array (BGA). Next, a silicon (Si) interposer mounted on top of the first IC die by means of an attachment layer, such as an adhesive layer or die attach. A second IC die is then mounted on top of the silicon interposer by means of another attachment layer (i.e., another adhesive layer/die attach). Additional IC dies and silicon interposers may subsequently be added to the stack to further improve packing density. Such a stack of IC chips may be implemented on an open substrate or within a sealed IC package.

However, as IC dies are packed more closely and lead lines become ever smaller, some well-known problems associated with IC manufacturing become aggravated. The cracking of solder joints connecting IC dies to substrates may cause a circuit board assembly to become defective. Thus, it is desirable to maintain a high level of solder joint reliability (SJR).

But, solder joints frequently crack due to thermal stresses encountered during manufacturing or during operation. Alternate cycles of heating and cooling may cause the substrate to warp, particularly as a result of shrinkage that occurs as the substrate cools. The coefficient of thermal expansion (CTE) of a silicon die is significantly less than the CTE of a substrate. The solder joints of a ball grid array connecting an IC die to a substrate are very fine. As the substrate warps, some of the solder joints may crack, thereby causing defects. This substrate warping is particularly damaging to stacked assemblies of integrated circuit dies.

There exists a need in the art for integrated circuit (IC) devices that have improved solder joint reliability. In particular, there is a need in the art to reduce warping of stacked die integrated circuit (IC) packages caused by the warping of the substrate due to thermal changes in the substrate.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior are, the present invention provides a copper interposer that reduces the warping of a stacked die integrated circuit (IC) package caused by the warping of the substrate due to thermal changes in the substrate. The copper (Cu) interposer has a significantly higher coefficient of thermal expansion (CTE) than a conventional silicon (Si) interposer. The higher CTE enables the copper interposer to counteract the substrate shrinkage more effectively.

It is a primary object of the present invention to provide a stacked die integrated circuit assembly comprising: 1) a substrate; 2) a first integrated circuit die mounted on the substrate; 3) a copper interposer mounted on the first integrated circuit die; and 4) a second integrated circuit die mounted on the copper interposer.

According to the principles of the present invention, a coefficient of thermal expansion associated with the copper interposer is more closely matched to a coefficient of thermal expansion of the substrate than a coefficient of thermal expansion of a silicon interposer.

It is another primary object of the present invention to provide a method of fabricating a stacked die integrated circuit assembly. The method comprises the steps of 1) attaching a lower surface of a first integrated circuit die to a substrate; 2) attaching a lower surface of a copper interposer to an upper surface of the first integrated circuit die; and 3) attaching a lower surface of a second integrated circuit die to an upper surface of the copper interposer.

According to one embodiment of the present invention, the lower surface of the first integrated circuit die is attached to the substrate using a solder ball grid array, the lower surface of the copper interposer is attached to the upper surface of the first integrated circuit die using a first adhesive layer, and the lower surface of the second integrated circuit die is attached to the upper surface of the copper interposer using a second adhesive layer.

The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; and the term “or” is inclusive, meaning and/or. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior uses, as well as to future uses of such defined words and phrases.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a top view of exemplary electronic assembly board100, on which is disposed a plurality of stacked die integrated circuits according to the principles of the present invention. Electronic assembly board100comprises substrate110, which provides support and electrical connections for a block of stacked die ball grid array (SDBGA) integrated circuit assemblies, which are arbitrarily labeled SDBGA1through SDBGA12, respectively. Stacked die integrated circuit (IC) assembly120, labeled SDBGA1, is a representative one of SDGA1through SDBGA12.

Stacked die IC assembly120comprises one or more silicon (Si) dies (or wafers) that are vertically stacked on substrate110. A first silicon IC die is attached to substrate110by means of a grid array of solder balls that also provide electrical connection paths between electronic pads on the lower surface of the first silicon IC die and electronic pads on the upper surface of substrate110.

A copper interposer according to the present invention is then mounted on the upper surface of the first silicon IC day by means of a die attach (or adhesive layer). Additional layers of IC dies an interposers may also be added.

The use of a copper interposer in lieu of a silicon interposer improves solder joint reliability (SJR) by reducing the warping of the substrate caused by thermal changes. The coefficient of thermal expansion (CTE) of a copper interposer (e.g., 17.7 ppm/° C.) is much greater than the CTE of a silicon interposer (e.g., 2.8 ppm/° C.). The higher CTE of copper is much closer to the CTE of a typical substrate (e.g., 18 ppm/° C.). This helps to counteract the substrate shrinkage.

FIG. 2Ais a cross-sectional view of an exemplary stacked die integrated circuit (IC) assembly120that uses only a single die according to one embodiment of the present invention. Stacked die IC assembly120comprises substrate110, silicon (Si) integrated circuit (IC) die210, and copper (Cu) interposer220. Silicon IC die210is mounted on substrate110by means of solder ball grid array201. Copper interposer220is mounted on silicon IC die210by means of adhesive layer202(i.e., a die attach layer).

Even though only a single silicon IC die is shown inFIG. 2A, copper interposer220still reduces warping of substrate110due to thermal change. Additional silicon IC dies may subsequently be mounted on the upper surface of copper interposer220.

FIG. 2Bis a cross-sectional view of an exemplary stacked die integrated circuit (IC) assembly120using two dies according to another embodiment of the present invention. Stacked die IC assembly120comprises substrate110, silicon (Si) integrated (IC) die210, copper (Cu) interposer220, and silicon (Si) integrated (IC) assembly230. As inFIG. 2A, silicon IC die210is mounted on substrate110by means of solder ball grid array201and copper interposer220is mounted on silicon IC die210by means of adhesive layer202((i.e., die attach). Furthermore, silicon IC die230is mounted on copper interposer220by means of adhesive layer203. Additional layers of copper interposers and silicon IC dies may subsequently be mounted on the upper surface of silicon IC die230.

FIG. 3illustrates the warping of an exemplary stacked die integrated circuit assembly containing PRIOR ART silicon (Si) interposer300.FIG. 4illustrates warping of an exemplary stacked die assembly containing copper interposer220according to the principles of the present invention. The components illustrated inFIGS. 3 and 4are not intended to be drawn to scale. The dotted lines inFIGS. 3 and 4are straight lines indicating the relative amounts of warping that occur with a silicon interposer and a copper interposer.FIGS. 3 and 4are intended to illustrate that there is relatively less warping (or warpage) of the substrate and integrated circuit die when copper interposer220is used (inFIG. 4) than when silicon interposer300is used (FIG. 3).

FIG. 5depicts flow diagram500, which illustrates an exemplary process for making a stacked die assembly containing a copper interposer according to the principles of the present invention. Initially, a first silicon IC die is mounted on a substrate by means of a solder ball grid array (or any other similar or suitable interconnection layer; process step505). Next, a copper interposer is mounted on the first silicon IC die by means of a die attach layer (process step510). If required, a second silicon IC die is mounted on top of the copper interposer by means of another die attach layer (process step515). Process steps510and515may then be repeated for additional layers of interposers and silicon IC dies.

Although the present invention has been described in detail, those skilled in the art will understand that various changes, substitutions, and alterations herein may be made without departing from the spirit and scope of the invention it its broadest form.