Oscillator circuit generating oscillating signal having stable cycle

An oscillator circuit includes a capacitor, a first constant current source electrically couplable to an end of the capacitor, a second constant current source electrically couplable to the end of the capacitor, a control circuit coupled to the end of the capacitor, a first reference potential, and a second reference potential to switch, in response to a comparison of a potential at the end of the capacitor with the first and second reference potentials, between a first operation to charge the capacitor by electrically coupling the first constant current source to the end of the capacitor and a second operation to discharge the capacitor by electrically coupling the second constant current source to the end of the capacitor, and a circuit configured to have an output signal thereof exhibiting a signal transition in response to timing at which the switching occurs between the first operation and the second operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-138007 filed on May 17, 2006, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to oscillator circuits, and particularly relates to an oscillator circuit which generates a signal having a cycle responsive to the charge/discharge operation of a capacitor.

2. Description of the Related Art

In DRAMs using memory capacitors to store data, there is a need to perform a restore operation (i.e., refresh operation) to retain information stored in the cells. Such restore operation includes reading cell data by successively activating word selecting lines, amplifying the data voltage by use of sense amplifiers, and restoring the amplified data to the cells. Refresh operations are periodically performed at predetermined refresh intervals with respect to the memory array or block that is subjected to a refresh operation. An electric current consumed by a refresh operation may be represented as follows.
IREF=qREF·NREF/tREF
Here, qREFrepresents the amount of electric charge that is consumed by a single refresh operation (i.e., a refresh operation for one activation of one word line), NREFrepresenting the number of refresh operations (i.e., the number of refresh operations each corresponding to one activation of one word line) performed in one cycle (i.e., in one refresh cycle), and tREFrepresenting a refresh cycle.

In order to reduce the consumed current IREF, it is desirable to prolong the refresh cycle tREF as much as possible within the time period during which the data of DRAM cells can be retained. Since the refresh cycle tREFexhibits variation from circuit to circuit, however, the refresh cycle tREFshould be determined so as to provide a margin that takes into account such a variation for the purpose of reliably ensuring that the refresh cycle tREFalways stays shorter than the data retainable period. Accordingly, in order to reduce the consumed current IREFby prolonging the refresh cycle tREFas much as possible, there is a need to suppress the variation of the refresh cycle tREFso as to perform each refresh operation at precise cycles.

qREF·NREFbecomes larger when the memory capacity is increased, resulting in an increase of an electric current necessary for refresh operations. There will also be an increase in the amount of change in the consumed current IREFresponsive to the variation of the refresh cycle tREF. In such a case, a change in the consumed current IREFresponsive to the variation of the refresh cycle tREFcannot be disregarded. There is thus a need to set the refresh cycle tREFaccurately in order to suppress an increase in current consumption as much as possible.

In the self-refresh mode of a DRAM, a refresh operation is performed at intervals responsive to a cycle of a signal generated by an oscillator inside the DRAM, rather than being performed in response to a refresh command supplied from an external source.FIG. 1is a drawing showing an example of the configuration of such oscillator (Patent Document 1 through 4).

The oscillator circuit shown inFIG. 1includes a comparator11, a constant current source12, a capacitor13, a delay circuit14, a PMOS transistor15, an NMOS transistors16, and a NAND gate17. In the state in which no electric charge is accumulated in the capacitor13(capacitance C), a potential vosc at the charge store node of the capacitor13is lower than a reference voltage vref. Accordingly, the output of the comparator11having an inverted input thereof coupled to the charge store node of the capacitor13and a non-inverted input thereof coupled to the reference voltage vref is HIGH, resulting in an oscillator circuit output pulsex being HIGH. In this state, a startup signal startz is changed to HIGH. In response, the output of the NAND gate17is changed to LOW, thereby making the NMOS transistors16nonconductive. In response to this, an electric current equal in amount to a current amount Icmp of the constant current source12flows into the capacitor13, thereby accumulating electric charge in the capacitor13.

As the potential vosc of the charge store node of the capacitor13exceeds the reference voltage vref, the output of the comparator11changes from HIGH to LOW. Subsequently, the oscillator output pulsex changes from HIGH to LOW after the passage of a delay time introduced by the delay circuit14. In response to this, the output of the NAND gate17becomes HIGH to make the NMOS transistors16conductive, so that the capacitor13is discharged to return to the original state in which no electric charge is accumulated. In response, the output of the comparator11returns to HIGH.

In the operation described above, further, the PMOS transistor15becomes conductive when the oscillator output pulsex changes from HIGH to LOW, thereby setting the output of the comparator11to HIGH. This makes sure than the oscillator output pulsex becomes a pulse signal that sustains its LOW state for a predetermined period corresponding to the delay time of the delay circuit14regardless of the response speed of the comparator11.

The operation described above is repeated so that the oscillator circuit ofFIG. 1outputs pulses at constant time intervals. The cycle (interval) of this pulse is theoretically C·vref/Icmp.

The cycle generated by an oscillator as described above tend to exhibit variation due to variations in the current source, capacitance, reference voltage, comparator offsets, etc. There is thus a need to adjust the oscillating cycle of the oscillator to a desired cycle by measuring the oscillating cycle of the oscillator by use of a tester at a testing step of a circuit (e.g., DRAM) incorporating such oscillator (see Patent Document 5). Arrangement is made in advance such that an oscillating cycle is adjustable by adjusting the current amount of the current source through cutting or leaving intact fuses, for example. The fuses may then be cut as appropriate to achieve a desired cycle based on the checking of the cycle measured by the tester.

When the oscillator circuit shown inFIG. 1is implemented as a semiconductor device, a MOS transistor is typically used as the capacitor13. In this case, the capacitance between the gate node and source/drain nodes of the MOS transistor depends on a threshold voltage Vth of the MOS transistor.

FIG. 2is a drawing showing the capacitance characteristics of a MOS transistor when the threshold voltage Vth of the MOS transistor exhibits variation. InFIG. 2, the horizontal axis represents a gate-source voltage Vgs, and the vertical axis represents a MOS capacitance Cgg. As shown inFIG. 2, when the voltage applied to the gate node (i.e., the gate-source voltage Vgs) is low, no channel is created so that the capacitance Cgg is relatively a small value. As the voltage Vgs become sufficiently large, a channel is created. In response, the capacitance Cgg becomes a relatively large value, which is responsive to the gate length and gate-film width.

In the oscillator circuit shown inFIG. 1, the voltage across the capacitor13has a voltage range from 0 V to more than vref. Namely, when the oscillator circuit is oscillating, the voltage Vgs varies in a range that includes a point at which the capacitance Cgg exhibits a large sudden change as shown inFIG. 2.

With a variation in the threshold voltage Vth of the MOS capacitor, the capacitance change relative to the change of the voltage Vgs as shown by the solid lines inFIG. 2ends up also having a variation as illustrated by dotted lines. Namely, a capacitance characteristic21in which the large capacitance appears at a relatively low voltage Vgs is observed in the case of a relatively low threshold voltage Vth. Further, a capacitance characteristic22in which the large capacitance appears at a relatively high voltage Vgs is observed in the case of a relatively high threshold voltage Vth.

As a result, the amount of electric charge required for the potential vosc of the charge store node of the capacitor13to reach a certain potential ends up varying, so that the potential vosc of the charge store node of the capacitor13exhibits variation as shown inFIG. 3. In the case of the capacitance characteristic21shown inFIG. 2, the cycle becomes relatively long, resulting in a voltage waveform23. In the case of the capacitance characteristic22shown inFIG. 2, the cycle becomes relatively short, resulting in a voltage waveform24.

As previously described, the adjustment of the cycle in response to the tester measurements can suppress, to some degree, a cycle variation caused by variation in the threshold voltage Vth. Since the adjustable range is limited, the smaller the variation, the better the outcome will be. Further, the threshold voltage Vth not only varies depending on processes, but also varies depending on temperature. Thus, the cycle also varies depending on temperature. It would be necessary to provide a plurality of adjustment means and to measure temperature at a plurality of measurement points in order to adjust such a variation in the cycle caused by temperature changes. This adds up the test cost.

Accordingly, there is a need for an oscillator circuit capable of generating an oscillating signal having a predetermined cycle that is not affected by variation in the capacitance characteristics caused by the variation of the threshold voltage Vth.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide an oscillator circuit that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.

Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by an oscillator circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.

To achieve these and other advantages in accordance with the purpose of the invention, the invention provides an oscillator circuit, which includes a capacitor, a first constant current source electrically couplable to an end of the capacitor, a second constant current source electrically couplable to the end of the capacitor, a control circuit coupled to the end of the capacitor, a first reference potential, and a second reference potential to switch, in response to a comparison of a potential at the end of the capacitor with the first and second reference potentials, between a first operation to charge the capacitor by electrically coupling the first constant current source to the end of the capacitor and a second operation to discharge the capacitor by electrically coupling the second constant current source to the end of the capacitor, and a circuit configured to have an output signal thereof exhibiting a signal transition in response to timing at which the switching occurs between the first operation and the second operation.

In an oscillator circuit according to at least one embodiment of the present invention, two current sources for charging/discharging a capacitor are provided, and the charging/discharging of the capacitor is controlled in response to a comparison of the voltage across the capacitor with first and second reference potentials. Provision is further made such that the voltage range in which the voltage across the opposite ends of the capacitor varies in response to the charging/discharging is positioned above the threshold voltage of the MOS capacitor. In other words, the voltage range in which the voltage across the capacitor varies in response to the charging/discharging operation is set such as not to include the threshold voltage of the MOS transistor. With this provision, it is possible to generate a cyclic signal that is not affected by the variation of the threshold voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 4is a drawing showing the circuit configuration of a first embodiment of an oscillator circuit according to the present invention. This oscillator circuit may be used for the purpose of controlling the refresh operation of a semiconductor memory device, for example. An oscillator circuit30shown inFIG. 4includes a comparator31, a comparator32, a constant current source33, a constant current source34, a capacitor35, a delay circuit36, a counter37, PMOS transistors38and39, NMOS transistors40through42, inverters43through45, and an AND gate46.

A startup signal startz is first changed to HIGH. In response, the NMOS transistor42becomes nonconductive, thereby starting the charging of the capacitor35through the constant current source33(with a current amount Icmp) or the discharging of the capacitor35through the constant current source34(with a current amount Icmn). It is assumed that, in the initial state, a predetermined amount of electric charge is accumulated in the capacitor35(capacitance C), so that a potential vosc at the charge store node of the capacitor35is lower than a reference voltage vrefh and higher than a reference voltage vrefl. The opposite node of the capacitor35is coupled to a ground potential. In this state, an output out1of the comparator31having an inverted input thereof coupled to the charge store node of the capacitor35and a non-inverted input thereof coupled to the reference voltage vrefh is HIGH. Further, an output out2of the comparator32having an inverted input thereof coupled to the charge store node of the capacitor35and a non-inverted input thereof coupled to the reference voltage vrefl is LOW. At this time, the two inputs into the AND gate46are both HIGH, so that an oscillator circuit output pulsex is HIGH.

It is assumed that, in this state, an output sroscz of the counter37is HIGH. The PMOS transistor39and the NMOS transistor40are thus nonconductive and conductive, respectively, so that discharge occurs from the capacitor35to the constant current source34. As the potential vosc of the charge store node drops below the reference voltage vrefl in response to a decrease in the electric charge of the capacitor35, the output out2of the comparator32changes from LOW to HIGH. As a result, the output of the AND gate46changes from HIGH to LOW, and, thereafter, the oscillator output pulsex changes from HIGH to LOW after the passage of a delay time introduced by the delay circuit36.

In response, the output sroscz of the counter37is changed to LOW. The output of the inverter45then changes from LOW to HIGH, so that a transition occurs from a state in which the output out1of the comparator31is clamped to HIGH to a state in which the output out2of the comparator32is clamped to LOW. In response, the output of the AND gate46returns from LOW to HIGH. At this time, the output sroscz of the counter37exhibits no change and stays at LOW.

Since the output sroscz of the counter37is LOW, the PMOS transistor39and the NMOS transistor40become conductive and nonconductive, respectively, so that charge from the constant current source33to the capacitor35occurs. As the potential vosc of the charge store node rises above the reference voltage vrefh in response to an increase in the electric charge of the capacitor35, the output out1of the comparator31changes from HIGH to LOW. As a result, the output of the AND gate46changes from HIGH to LOW, and, thereafter, the oscillator output pulsex changes from HIGH to LOW after the passage of a delay time introduced by the delay circuit36.

In response, the output sroscz of the counter37is changed to HIGH. The output of the inverter45then changes from HIGH to LOW, so that a transition occurs from a state in which the output out2of the comparator32is clamped to LOW to a state in which the output out1of the comparator31is clamped to HIGH. In response, the output of the AND gate46returns from LOW to HIGH. At this time, the output sroscz of the counter37exhibits no change and stays at HIGH.

The operation of the comparator31is suspended by setting an activation signal sz to LOW during when the output out1of the comparator31is clamped to HIGH. The operation of the comparator32is suspended by setting a negative-logic activation signal sx to HIGH during when the output out2of the comparator32is clamped to LOW.

The operation described above is repeated so that the potential vosc of the charge store node of the capacitor35repeatedly rises and falls between vrefl and vrefh, thereby generating a pulse signal output pulsex corresponding to such repeating operation.FIG. 5is a drawing showing the signal waveforms of the potential vosc of the charge store node, the pulse signal output pulsex, and the output sroscz of the counter37. As shown inFIG. 5, the potential vosc of the charge store node of the capacitor35falls during the HIGH period of the counter output sroscz, and rises during the LOW period of the counter output sroscz. The pulse signal output pulsex becomes LOW for a predetermined duration corresponding to the delay time of the delay circuit36at the timing at which the potential vosc switches between rising and falling. A cycle tOSC of this LOW pulse is theoretically C·(vrefh−vrefl)·(1/Icmn+1/Icmp).

The potential vosc of the charge store node of the capacitor35operates in a voltage range between vrefl and vrefh (between a potential slightly lower than vrefl and a potential slightly higher than vrefh, to be exact). The cycle tOSC is thus not affected by variation in the threshold voltage Vth if the reference voltage vrefl is set higher than the threshold voltage Vth of the MOS transistor of the capacitor35. In this manner, the present invention provides two electric current sources for charging and discharging a capacitor, and an arrangement is made such that the voltage range in which the voltage appearing across the opposite ends of the capacitor varies in response to the charging/discharging operation is positioned above the threshold voltage of the MOS transistor that constitutes the capacitor. In other words, the voltage range in which the voltage across the capacitor varies in response to the charging/discharging operation is set such as not to include the threshold voltage of the MOS transistor that constitutes the capacitor. Namely, inFIG. 2, for example, provision is made such that vrefl is positioned on the right-hand side of the threshold voltage Vth of the capacitance characteristic22. With this provision, it is possible to generate a cyclic signal that is not affected by the variation of the threshold voltage Vth.

In the following, a second embodiment of the oscillator circuit according to the present invention will be described. Even when an oscillator circuit free from the effect of the variation of the threshold voltage Vth is constructed, the capacitance inevitably exhibits variation attributable to other causes than the threshold voltage Vth. Also, there are variations in the current source, reference voltage, comparator offsets, etc., as previously described. There is thus a need to adjust the oscillating cycle of the oscillator to a desired cycle by measuring the oscillating cycle of the oscillator by use of a tester at a testing step of a circuit (e.g., DRAM) incorporating such oscillator. Arrangement is made in advance such that an oscillating cycle is adjustable by adjusting the current amount of the current source through cutting or leaving intact fuses, for example. The fuses may then be cut as appropriate to achieve a desired cycle based on the checking of the cycle measured by the tester.

FIG. 6is a drawing for explaining the configuration for measuring cycles by use of a tester. As shown inFIG. 6, a tester43is connected to pads41and42of a semiconductor chip40that may be a semiconductor memory device including the oscillator circuit30. The pad41is coupled to a node into which a startup signal startz for controlling the activation and deactivation of the oscillator circuit30is input, and the pad42is coupled to the output sroscz of the counter37of the oscillator circuit30.

FIG. 7is a drawing for explaining the method of measuring the cycle of the oscillator circuit30by use of the tester43in the configuration shown inFIG. 6. The tester43first supplies to the pad41the startup signal startz changing from LOW to HIGH, thereby activating and starting the operation of the oscillator circuit30at the timing of the LOW-to-HIGH transition of startz. In the initial state, the potential vosc (i.e., the potential at the charge store node of the capacitor35) is zero. When the oscillator circuit30starts its operation, the potential vosc rises to vrefh, and thereafter keeps rising and falling between vrefl and vrefh. The output sroscz appearing at the pad42changes as shown inFIG. 7in accordance with the changes of the potential vosc.

The arrangement that is assumed with respect toFIG. 7is that the potential vosc rises during HIGH of the output sroscz, and falls during LOW of the output sroscz, which is different from the configuration shown inFIG. 5in terms of the relationships between the output sroscz and the potential vosc. This is simply a matter of definition as to which signal in the circuit ofFIG. 4is designated as sroscz. If the output of the inverter45is designated as sroscz, the relationships between the output sroscz and the potential vosc as shown inFIG. 7are obtained.

As can be seen fromFIG. 7, the potential vosc starts rising from zero upon the start of operation of the oscillator circuit30, so that the first cycle tOSC1has a different length than the cycle tOSC appearing in the subsequent steady state. The tester43measures the timing of a change of the output sroscz (e.g., the first rise timing) by measuring a time length between a reference point and such timing of change, wherein the timing at which the startup signal startz changes from LOW to HIGH serves as the reference point. Thus, correct cycle measurement cannot be made if the first cycle tOSC1is different from the cycle in the steady state. It is thus preferable to have the first cycle equal to the steady state cycle tOSC in order to perform a correct cycle measurement without modifying the configuration of the tester43and without using complex control operations.

FIG. 8is a drawing showing the circuit configuration of a second embodiment of an oscillator circuit according to the present invention. InFIG. 8, the same elements as those ofFIG. 4are referred to by the same numerals, and a description thereof will be omitted.

An oscillator circuit30A shown inFIG. 8includes a comparator31, a constant current source33, a constant current source34, a capacitor35, a delay circuit36, a counter37, PMOS transistors38and39, NMOS transistors40and42, an AND gate46, a feedback-function-equipped comparator50, and a logic circuit51. In comparison with the oscillator circuit30shown inFIG. 4, the feedback-function-equipped comparator50is provided in place of the comparator32, and the logic circuit51is provided to replace the inverters43through45. The feedback-function-equipped comparator50performs feedback control utilizing the comparator at the time of start of operation so as to set the potential vosc to the reference voltage vrefl. The logic circuit51serves to generate control signals a1through a5for controlling various parts.

FIG. 9is a drawing showing an example of the circuit configuration of the comparator31. As shown inFIG. 9, the comparator31is implemented by using a differential amplifier, and includes PMOS transistors61and62, NMOS transistors63through65, and a constant current source66. The NMOS transistor65is turned on/off by the signal sz so as to control the activation/deactivation of the comparator31.

FIG. 10is a drawing showing an example of the circuit configuration of the feedback-function-equipped comparator50. The feedback-function-equipped comparator50shown inFIG. 10serves to provide a comparison function and a feedback control function by use of a differential amplifier, and includes a constant current source71, PMOS transistors72through78, NMOS transistors79through87, an inverter88, and an NOR gate89. The portion comprised of the constant current source71, the PMOS transistors72through74, and the NMOS transistors79and80is a differential amplifier that compares the potential vosc with the reference voltage vrefl. A path extending from the NMOS transistor82having the gate thereof connected to a node n2, passing through the NMOS transistor83, and reaching the gate of the PMOS transistor74serves as a feedback path for setting the potential vosc.

FIG. 11is a truth table showing the inputs/outputs of the logic circuit51. According to this truth table, the logic circuit51generates the control signals a1through a5so as to perform the operation for setting the potential vosc to the reference voltage vrefl at the time of start of operation and the operation for raising and lowering the potential vosc at the time of steady operation.

The operation for setting the potential vosc to the reference voltage vrefl at the start of operation will be described first. In order to set the potential vosc to the reference voltage vrefl, the startup signal startz and the ready signal readyz are set to LOW and HIGH, respectively, prior to the changing of the startup signal startz to HIGH. In this state, as shown in the truth table ofFIG. 11, the logic circuit51sets the control signals a3and a4to LOW and HIGH, respectively.

When the control signals a3and a4shown inFIG. 10are set to LOW and HIGH, respectively, the circuit will operate as follows. Since the control signal a4is set to HIGH, a switch sw1comprised of the PMOS transistor77and the NMOS transistor87becomes nonconductive, and a switch sw2comprised of the PMOS transistor78and the NMOS transistor86becomes conductive. Accordingly, a node n1is connected to a node n3, and the node n2functions as an output node of the differential amplifier. At this time, the reference voltage vrefl is on the inverted-input side, and the potential vosc is on the non-inverted-input side. Since the NMOS transistor83is conductive in this case, a feedback path is established that has the gate node of the PMOS transistor74serving as an input node and the node n2serving as an output node. As the potential vosc at the input node rises, the potential at the node n2rises due to the operation of the differential amplifier, resulting in an increase in the conductivity of the NMOS transistor82. An increase in the conductivity of the NMOS transistor82serves to lower the potential vosc. Through this feedback control, the potential vosc is adjusted equal to the reference voltage vrefl. Since the control signal a3is LOW at this time, the PMOS transistor76becomes conductive, thereby clamping the output out2of the feedback-function-equipped comparator50to HIGH.

Through the feedback control as described above, the potential vosc is adjusted equal to the reference voltage vrefl. Accordingly, a signal having its first cycle equal to the cycle tOSC is generated when the startup signal startz is changed to HIGH to start the operation of the oscillator circuit30A.

FIG. 12is a drawing for explaining the method of measuring the cycle of the oscillator circuit30A ofFIG. 8. The tester43is connected to three pads of a semiconductor chip including the oscillator circuit30A. The three pads are a pad for inputting the ready signal readyz, a pad for inputting the startup signal startz, and a pad for outputting the output signal sroscz. The tester43supplies the startup signal startz being LOW and the ready signal readyz being HIGH to the respective pads. In response, the oscillator circuit30A performs the above-described feedback control, so that the potential vosc (i.e., the potential at the charge store node of the capacitor35) rises from zero to vrefl as shown inFIG. 12.

When the startup signal startz is thereafter changed from LOW to HIGH, the oscillator circuit30A starts oscillating, so that the potential vosc starting from its initial potential vrefl keeps rising and falling between vrefl and vrefh. The output sroscz changes as shown inFIG. 12in accordance with the changes of the potential vosc.

As can be seen fromFIG. 12, the potential vosc starts rising from vrefl upon the start of operation of the oscillator circuit30A, so that the first cycle tOSC1has a length equal to the cycle tOSC appearing in the subsequent steady state. The tester measures the timing of a change of the output sroscz (e.g., the first rise timing) by measuring a time length between a reference point and such timing of change, wherein the timing at which the startup signal startz changes from LOW to HIGH serves as the reference point. In the oscillator circuit30A of the second embodiment, correct cycle measurement can be made since the first cycle tOSC1is equal to the cycle in the steady state.

In the following, the oscillating operation of the oscillator circuit30A after the startup signal startz is set to HIGH will be described in detail. When the startup signal startz is set to HIGH, the logic circuit51sets the control signal a4to LOW as shown in the truth table ofFIG. 11.

Since the control signal a4is set to LOW inFIG. 10, the switch sw1comprised of the PMOS transistor77and the NMOS transistor87becomes conductive, and the switch sw2comprised of the PMOS transistor78and the NMOS transistor86becomes nonconductive. Accordingly, the node n2is connected to the node n3, and the node n1functions as the output node of the differential amplifier. At this time, the reference voltage vrefl is on the non-inverted-input side, and the potential vosc is on the inverted-input side. The potential at the node n1that is the output of the differential amplifier is inverted by the PMOS transistor75and the NMOS transistor85to be output as an inverted output out2of the comparator50. Accordingly, the inverted output out2ofFIG. 10becomes logically equivalent to the output of the inverter44that inverts out2in the first embodiment shown inFIG. 4. The inverted output out2ofFIG. 10becomes valid when the control signal a3is HIGH, and is clamped to HIGH when the control signal a3is LOW.

Referring toFIG. 8, the circuit is now assumed in a state in which the potential vosc of the charge store node of the capacitor35is lower than the reference voltage vrefh and higher than the reference voltage vrefl. In this state, the output out1of the comparator31having its inverted input coupled to the charge store node of the capacitor35and its non-inverted input coupled to the reference voltage vrefh is HIGH. Further, the inverted output out2of the comparator50having an inverted input thereof coupled to the charge store node of the capacitor35and a non-inverted input thereof coupled to the reference voltage Vrefl is HIGH. At this time, the two inputs into the AND gate46are both HIGH, so that an oscillator circuit pulse output pulsex is HIGH.

It is assumed that, in this state, an output sroscz of the counter37is LOW. Since the startup signal startz is HIGH and the counter output sroscz is LOW, the logic circuit51sets the control signals a2and a3to HIGH as shown in the truth table ofFIG. 11. The PMOS transistor39and the NMOS transistor40are thus nonconductive and conductive, respectively, so that discharge occurs from the capacitor35to the constant current source34. As the potential vosc of the charge store node drops below the reference voltage Vrefl in response to a decrease in the electric charge of the capacitor35, the inverted output out2of the comparator50changes from HIGH to LOW. As a result, the output of the AND gate46changes from HIGH to LOW, and, thereafter, the oscillator output pulsex changes from HIGH to LOW after the passage of a delay time introduced by the delay circuit36.

In response, the output sroscz of the counter37is changed to HIGH. As shown in the truth table ofFIG. 11, the control signal a1changes from LOW to HIGH, so that a transition occurs from a state in which the output out1of the comparator31is clamped to HIGH to a state in which it is not clamped. Further, the control signal a3changes from HIGH to LOW, so that a transition occurs from a state in which the inverted output out2of the comparator50is not clamped to a state in which it is clamped to HIGH. In response, the output of the AND gate46returns from LOW to HIGH. At this time, the output sroscz of the counter37exhibits no change and stays at HIGH.

Since the output sroscz of the counter37is HIGH, the logic circuit51sets the control signals a2and a3to LOW as shown in the truth table ofFIG. 11. The PMOS transistor39and the NMOS transistor40are thus conductive and nonconductive, respectively, so that charge from the constant current source33to the capacitor35occurs. As the potential vosc of the charge store node rises above the reference voltage Vrefh in response to an increase in the electric charge of the capacitor35, the output out1of the comparator31changes from HIGH to LOW. As a result, the output of the AND gate46changes from HIGH to LOW, and, thereafter, the oscillator output pulsex changes from HIGH to LOW after the passage of a delay time introduced by the delay circuit36.

In response, the output sroscz of the counter37is changed to LOW. As shown in the truth table ofFIG. 11, the control signal a1changes from HIGH to LOW, so that a transition occurs from the state in which the output out1of the comparator31is not clamped to the state in which it is clamped to HIGH. Further, the control signal a3changes from LOW to HIGH, so that a transition occurs from the state in which the inverted output out2of the comparator50is clamped to HIGH to the state in which it is not clamped. In response, the output of the AND gate46returns from LOW to HIGH. At this time, the output sroscz of the counter37exhibits no change and stays at LOW.

The operation of the comparator31is suspended by setting an activation signal sz to LOW during when the output out1of the comparator31is clamped to HIGH. During the period in which the inverted output out2is clamped to HIGH, the operation of the comparator50is suspended by the nonconductive state of the PMOS transistor72occurring in response to the HIGH output of the NOR gate89since the control signals a3and a4are both LOW.

The operation described above is repeated so that the potential vosc of the charge store node of the capacitor35repeatedly rises and falls between vrefl and vrefh, thereby generating a pulse signal output pulsex corresponding to such repeating operation. A cycle tOSC of this pulse is theoretically C·(vrefh−vrefl)·(1/Icmn+1/Icmp).

The potential vosc of the charge store node of the capacitor35operates in a voltage range between vrefl and vrefh (between a potential slightly lower than vrefl and a potential slightly higher than vrefh, to be exact). The cycle tOSC is thus not affected by variation in the threshold voltage Vth if the reference voltage Vrefl is set higher than the threshold voltage Vth of the MOS transistor of the capacitor35.

In the first and second embodiments described above, NMOS or PMOS transistors having a predetermined bias voltage applied to their gate node may be used as the current sources (i.e., the constant current sources33,34,66,71, and so on). Further, the delay circuit36may be implemented as a circuit made by connecting inverters and capacitors alternately.

FIG. 13is a drawing showing an example of the circuit configuration of the delay circuit36. The delay circuit36ofFIG. 13includes inverters91and92and capacitors93and94. Outputs of the inverters91and92are connected to the capacitors93and94, respectively. The capacitances of the capacitors and the drive powers (output current amounts) of the inverters are adjusted as appropriate, thereby providing a delay circuit having a desired delay time.

FIG. 14is a drawing showing an example of the circuit configuration of the counter37. The counter shown inFIG. 14is a frequency divider circuit for performing a frequency division with respect to a pulse signal, and includes NAND gates101and102, a NOR gate103, inverters104through108, PMOS transistors109and110, and NMOS transistors111and112.

When the startup signal startz is LOW, the output of the NOR gate103is fixed to LOW, so that the output sroscz is fixed to HIGH. When the startup signal startz is HIGH, the NAND gates101and102as well as the NOR gate103each serve as an inverter. The NAND gate101and the inverter106constitute a first latch, and the NOR gate103and the inverter107constitute a second latch. The PMOS transistor109and the NMOS transistor111together constitute a first transfer gate, and the PMOS transistor110and the NMOS transistor112together make up a second transfer gate.

It is assumed that the output sroscz is HIGH in the initial state. The first transfer gate is in the open state so that the HIGH level of the output sroscz is stored in the first latch when the startup signal startz is HIGH and the pulse signal pulsex is HIGH. In this state, the second transfer gate is in the closed state.

The second transfer gate opens when the pulse signal pulsex is changed to LOW while the startup signal startz is HIGH, thereby causing the LOW output of the first latch storing HIGH to be stored in the second latch. As the second latch stores LOW, a LOW output is produced as the output sroscz.

As the pulse signal pulsex returns to HIGH, the first transfer gate is placed in the open state, so that the LOW level of the output sroscz is stored in the first latch. In this state, the second transfer gate is in the closed state.

The second transfer gate thereafter opens when the pulse signal pulsex is changed to LOW, thereby causing the HIGH output of the first latch storing LOW to be stored in the second latch. As the second latch stores HIGH, a HIGH output is produced as the output sroscz.

In this manner, the output sroscz changes from HIGH to LOW or from LOW to HIGH each time the pulse signal pulsex becomes LOW. With this provision, the counter output sroscz responsive to the pulse signal pulsex as shown inFIG. 5can be generated.