Vertical charge control semiconductor device with low output capacitance

In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

BACKGROUND OF THE INVENTION

Power field effect transistors, e.g., MOSFETs (metal oxide semiconductor field effect transistors), are well-known in the semiconductor industry. One type of power MOSFET is a DMOS (double-diffused metal oxide semiconductor) transistor. A cross-sectional view of a portion of a cell array of one known variety of DMOS transistors is shown inFIG. 1. As shown, an n-type epitaxial layer102overlies n-type substrate region100to which the drain contact is made. Polysilicon-filled trenches extend into the epitaxial layer102from the top surface. The polysilicon106a,106bin the trenches are insulated from the epitaxial layer by oxide layers104a,104b. Source regions108a,108bin p-type body regions110a,110bare adjacent the trenches at the top surface. A polysilicon gate114overlaps the source regions108a,b, extends over a surface portion of the body regions110a,b, and extends over a surface area of a region between the two trenches commonly referred to as the mesa drift region. Metal layer116electrically shorts source regions108a,bto body regions110a,band polysilicon106a,bin the trenches. The surface area of body regions110a,bdirectly underneath gate114defines the transistor channel region. The area between body regions110aand110bunder gate114is commonly referred to as the JFET region.

Upon applying a positive voltage to the gate and the drain, and grounding the source and the body regions, the channel region is inverted. A current thus starts to flow from the drain to the source through the drift region and the surface channel region.

A maximum forward blocking voltage, hereinafter referred to as “the breakdown voltage”, is determined by the avalanche breakdown voltage of a reverse-biased body-drain junction. The DMOS structure inFIG. 1has a high breakdown voltage due to the polysilicon-filled trenches. Polysilicon106a,bcause the depletion layer formed as a result of the reverse-biased body-drain junction to be pushed deeper into the drift region. By increasing the depletion region depth without increasing the electric field, the breakdown voltage is increased without having to resort to reducing the doping concentration in the drift region which would otherwise increase the transistor on-resistance.

A drawback of theFIG. 1structure is its high output capacitance Coss, making this structure less attractive for high frequency applications such as radio frequency (RF) devices for power amplifiers in the wireless communication base stations. The output capacitance Coss of theFIG. 1structure is primarily made up of: (i) the capacitance across the oxide between the polysilicon in the trenches and the drift region (i.e., Cox), in series with (ii) the capacitance across the depletion region at the body-drift region junction. Cox is a fixed capacitance while the depletion capacitance is inversely proportional to the body-drain bias.

The breakdown voltage of power MOSFETs is dependent not only upon the cell structure but also on the manner in which the device is terminated at its outer edges. To achieve a high breakdown voltage for the device as a whole, the breakdown voltage at the outer edges must be at least as high as that for the cells. Thus, for any cell structure, a corresponding terminating structure is needed which exhibits a high breakdown voltage.

In most amplifier circuits a significant amount of heat energy is produced in the transistor. Only 50% efficiency is typical of the best class AB RF power amplifiers available. An important factor in designing power devices for high frequency applications is thus the thermal performance of the device. Because of the different device performance requirements, the cells in power MOSFETs are densely packed resulting in concentration of heat in active regions and poor heat transfer rates. The increase in temperature resulting from the poor heat transfer rate adversely effects the device performance.

Thus, a power MOSFET device with such improved characteristics as low output capacitance, high breakdown voltage, and improved thermal performance is desired.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, MOSFET cell structures and edge termination structures, and methods of manufacturing the same, are described which among other features and advantages exhibit a substantially reduced output capacitance, high breakdown voltage, and improved thermal performance.

In one embodiment, a MOSFET comprises at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, a first trench region extending from the first surface into the first semiconductor region, and at least one floating discontinuous region along a sidewall of the first trench region.

In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, a first trench region extending from the first surface into the first semiconductor region, and a first plurality of regions along a sidewall of the first trench region.

In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, and first and second insulation-filled trench regions each extending from the first surface into the first semiconductor region. Each of the first and second insulation-filled trench regions has an outer layer of silicon of a conductivity type opposite that of the first semiconductor region. The first and second insulation-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween such that the volume of each of the first and second trench regions is greater than one-quarter of the volume of the drift region.

In another embodiment, a MOSFET comprises a first semiconductor region over a substrate. The first semiconductor region has a first surface. The MOSFET further includes first and second insulation-filled trench regions each extending from the first surface to a predetermined depth within the first semiconductor region. Each of the first and second insulation-filled trench regions has an outer layer of doped silicon material which is discontinuous along a bottom surface of the insulation-filled trench region so that the insulation material along the bottom surface of the insulation-filled trench region is in direct contact with the first semiconductor region. The outer layer of silicon material is of a conductivity type opposite that of the first semiconductor region.

In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material are insulated from the first semiconductor region.

In accordance with an embodiment of the present invention, a MOSFET is formed as follows. A first epitaxial layer is formed over a substrate. A first doped region is formed in the first epitaxial layer. The first doped region has a conductivity type opposite that of the first epitaxial layer. A second epitaxial layer is formed over the first doped region and the first epitaxial region. A first trench region is formed which extends from a surface of the second epitaxial layer through the first and second epitaxial layers and the first doped region such that the first doped region is divided into two floating discontinuous regions along sidewalls of the first trench region.

In another embodiment, a MOSFET is formed as follows. A first epitaxial layer is formed over a substrate. First and second doped regions are formed in the first epitaxial layer. The first and second doped regions have a conductivity type opposite that of the first epitaxial layer. A second epitaxial layer is formed over the first and second doped regions and the first epitaxial region. First and second trench regions are formed wherein the first trench region extends through the first and second epitaxial layers and the first doped region such that the first doped region is divided into two floating discontinuous regions along sidewalls of the first trench region, and the second trench region extends through the first and second epitaxial layers and the second doped region such that the second doped region is divided into two floating discontinuous regions along sidewalls of the second trench region.

In another embodiment, a MOSFET is formed as follows. A first trench is formed in a first semiconductor region. A first doped region is formed along a bottom of the first trench. The first trench is extended deeper into the first semiconductor region such that of the first doped region two floating discontinuous regions remain along sidewalls of the first trench.

In another embodiment, a MOSFET is formed as follows. A first semiconductor region is formed over a substrate. The first semiconductor region has a first surface. A first trench is formed which extends from the first surface to a predetermined depth within the first semiconductor region. A layer of doped silicon material is formed along sidewalls of the trench. The layer of doped silicon material is of a conductivity type opposite that of the first semiconductor region.

The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

MOSFET cell structures, edge termination structures, and methods of manufacturing the same are described in accordance with the present invention. Among other features and advantages, the cell and termination structures and methods of manufacturing the same exhibit a substantially reduced output capacitance, high breakdown voltage, and improved thermal performance.

FIG. 2shows a cross-sectional view of a power MOSFET cell array in accordance with an embodiment of the present invention. As shown, both gate terminal205and source terminal207are located along the top-side of the device, and drain terminal203is located along the bottom-side. Drain terminal203is coupled to the lightly-doped epitaxial region202through a highly doped region200serving as the drain contact. Oxide-filled trench regions204a,204bextend from the top-side to a predetermined depth in the epitaxial region202. Discontinuous floating p-type regions206a,206bare spaced along an outer sidewall of trench regions204a,b. P-type body regions208a,208bextend from the top-side into the epitaxial region adjacent trench regions204a,b. As shown, body regions208a,binclude highly-doped p+ regions210a,b, although these p+ regions may be eliminated if desired. Source regions212a,bare formed in body regions208a,bas shown.

Polysilicon gates216overlap source regions212a,b, extend over the surface area of body regions208a,band over the surface area of epitaxial region202between body regions208aand208b. Gates216are insulated from the underlying regions by gate oxide214. The surface area of body regions208a,bdirectly under gates216form the channel regions. Metal layer218overlies the top-side of the structure and forms the common source-body contact.

The area of the epitaxial region between trenches204aand204bis hereinafter referred to as drift region209. When proper biasing is applied to the gate, drain, and source terminals to turn on the device, current flows between drain terminal203and source terminal207through drain contact region200, drift regions209, the channel regions, source diffusion regions212a,b, and finally metal layer218.

ComparingFIGS. 1 and 2, it can be seen that the polysilicon106a,b(FIG. 1) in the trenches are replaced with insulating material, thus eliminating the significant contributor to the output capacitance of theFIG. 1structure, namely, Cox. By replacing the polysilicon with an insulator such as silicon-dioxide, a greater portion of the space charge region appears across an insulator rather than silicon. Because the permitivity of insulator is lower than that of silicon (in the case of silicon-dioxide, a factor of about three lower), and the area of the space charge region along its boundaries is reduced (especially when the application voltage is low), the output capacitance is significantly reduced (by at least a factor of three).

As described above, the polysilicon in the trenches of the prior artFIG. 1structure helps improve the cell breakdown voltage by pushing the depletion region deeper into the drift region. Eliminating the polysilicon would thus result in lowering the breakdown voltage unless other means of reducing the electric field are employed. Floating p regions206a,bserve to reduce the electric field. InFIG. 2, as the electric field increases with the increasing drain voltage, floating p regions206a,bacquire a corresponding potential determined by their position in the space charge region. The floating potential of these p regions causes the electric field to spread deeper into the drift region resulting in a more uniform field throughout the depth of the drift region and thus in a higher breakdown voltage. Accordingly, similar breakdown voltage characteristics to that of theFIG. 1structure is achieved but with much reduced output capacitance.

Floating p regions206a,bhave the adverse effect of reducing the width of drift regions209through which current flows when the device is in the on-state, and thus result in increased on-resistance. However, the adverse impact of the floating p regions on the on-resistance can be reduced by obtaining an optimum balance between the charge concentration in the drift region and such features of the floating p regions as size, doping concentration, and the spacing Lp between them. For example, a higher charge concentration in the drift region would require a smaller spacing Lp and vice versa. Further, because the floating p regions reduce the electric field near the surface in the channel, the channel length can be reduced to improve the on-resistance and the general performance of the device as a high frequency amplifier.

In one embodiment wherein a breakdown voltage of 80-100V is desired, epitaxial region202has a doping concentration in the range of 5×1015 to 1×1016 cm-3 and the floating p regions206a,bhave a doping concentration of about 5-10 times that of the epitaxial region.

FIGS. 3-1athrough3-1eare cross-sectional views showing an exemplary set of process steps for forming the structure inFIG. 2. InFIG. 3-1a, a first n-epitaxial layer302is deposited on a heavily-doped substrate300using conventional methods. P regions306,308are formed by implanting p-type impurities (such as Boron) through a mask304. The size of the opening in mask304is dependent upon the desired width of the trenches and the desired width of the floating p regions which are in turn dictated by the device performance targets. In one embodiment, the target width of the trench is in the range of 1-5 μm, the width of p regions306,308is at least 1 μm wider than the trench width, the lateral spacing between adjacent p regions306and308is no less than 1 μm, and n-epitaxial layer302has a doping concentration of about 2×1016 cm-3 and a thickness in the range of 2-5 μm.

InFIG. 3-1b, similar steps to those inFIG. 3-1aare carried out to from a second n-epitaxial layer316and p regions310,312. These steps can be repeated depending on the desired number of floating p regions. Alternatively, the steps inFIG. 3-1bmay be eliminated to form only a single floating p region along each trench sidewall.

InFIG. 3-1c, a final epitaxial layer320to receive the device body and source regions is deposited. While the deposition technique used in forming epitaxial regions302,316, and320is the same, the doping concentration of each epitaxial region can be varied depending on the desired characteristics of the drift region. Similarly, p regions306,308may be implanted to have a different doping concentration than p regions310,312if desired.

InFIG. 3-1d, mask330and conventional silicon trench etching techniques are used to etch through the three epitaxial layers302,316,320and through the center portion of the p regions306,308,310,312to form trenches322a,322band corresponding floating p regions306a,b,308a,b,310a,b, and312a,b. The width of the openings in mask330determines the width of the oxide trenches relative to the width of the floating p regions.

After preparation of the trench surface, a relatively thin insulator (e.g., about 300-500 Å of thermal oxide) is grown on the trench surface. Trenches322a,bare then filled with a dielectric material such as silicon-dioxide using conventional conformal coating method and/or Spin-On Glass (SOG) method. Any low k dielectric to reduce the output capacitance may be used to fill trenches322a,b. Conventional process steps used in forming self-aligned gate DMOS structures are then carried out to form the gate structure as shown inFIG. 3e.

An alternate method of manufacturing the structure inFIG. 2is described next using the simplified cross-sectional views inFIGS. 3-2athrough3-2c. InFIG. 3-2a: an initial n-epitaxial layer342is deposited on a heavily-doped substrate340; a trench344ais then formed in n-epitaxial layer342; and an implant step is then carried out to form a p region346at the bottom of trench344a, followed by a diffusion step to diffuse the p dopants further into epitaxial region342. InFIG. 3-2b: trench344ais further etched past p region346into epitaxial region342to form a deeper trench344b; and similar implant and diffusion steps to those inFIG. 3-2aare carried out to form p region348at the bottom of trench344b. InFIG. 3-2c: trench344bis etched past p region348into epitaxial layer342to form an even deeper trench344c; and trench344cis then filled with a suitable insulator. Thus, an insulator-filled trench344cand floating p regions346a,band348a,bare formed. The remaining process steps would be similar to those described in connection withFIG. 3-1e.

Referring back toFIG. 2, the vertical charge control enabled by the floating p regions allows the cells to be laterally spaced apart without impacting the electrical characteristics of the device. With the cells spaced further apart, the heat generated by each cell is distributed over a larger area and less heat interaction occurs between adjacent cells. A lower device temperature is thus achieved.

To achieve effective vertical charge control, spacing Lp (FIG. 2) between adjacent floating p regions206aand206bneeds to be carefully engineered. In one embodiment, spacing Lp is determined in accordance with the following proposition: the product of the doping concentration in the drift region and the spacing Lp be in the range of 2×1012 to 4×1012 cm-2. Thus, for example, for a drift region doping concentration of 5×1015 cm-3, the spacing Lp needs to be about 4 μm. Once an optimum spacing Lp is determined, the spacing Lc between a center axis of adjacent trenches204a,bcan be independently increased without impacting the electrical characteristics of the device.

Two ways of achieving the increased Lc spacing while keeping Lp spacing the same are shown inFIGS. 4 and 5. InFIG. 4, discontinuous floating p regions406a,balong with the source and body regions are extended across a large portion of the area between adjacent trenches to achieve a larger Lc spacing. In one embodiment, a combined width Wt of one trench (e.g.,404b) and one of the first plurality of floating regions (e.g.,406b) is greater than one-quarter of the spacing Lp. TheFIG. 4embodiment is particularly useful in technologies where the trench width Wt is tightly limited to a maximum size. If the trench width is not tightly limited, then the width of the trenches can be increased to obtain a larger Lc spacing while keeping spacing Lp the same as shown inFIG. 5.

An advantage of theFIG. 5structure over that inFIG. 4is the lower output capacitance because of the smaller floating p regions, and because a larger portion of the depletion region occurs in the wider insulation-filled trenches. Thus, the reduction in output capacitance due to the wider size of the trenches can be promoted by designing the cell structure to have a high ratio of trench insulation volume to drift region volume. A wider trench also results in improved thermal performance. In one embodiment, the volume of the insulation in the trench is at least one-quarter of the volume of the drift region. Thus, the larger the trench volume, the lower the output capacitance and the better the thermal performance of the device. However, little is gained in making the trench wider than the thickness of the die (e.g., 100 μm).

AlthoughFIGS. 2 through 5show multiple floating p regions along the trench sidewalls, the invention is not limited as such. Depending on the device performance requirements and design goals, only a single floating p region may be formed along each sidewall of the trenches.

FIG. 6shows a cross section view of a power MOSFET cell array in accordance with another embodiment of the present invention. The structure inFIG. 6is similar to that inFIG. 2except that floating p regions206a,b(FIG. 2) are eliminated and p layers (or p liners)606a,bare introduced along the outer perimeter of trenches604aand604b. Similar to floating p regions206a,b, help spread the depletion region deeper into the drift regions, thus improving the breakdown voltage. P liners606a,bare biased to the same potential as body regions608a,bsince they are in electrical contact with body regions608a,b.

InFIG. 7, as inFIG. 5, the width Wt of the oxide trench is increased to achieve improved thermal performance, while the Lp spacing is maintained at the same optimum value. A drawback of theFIG. 7structure is that p liners706a,bresult in higher output capacitance since they cause the space charge region to follow the entire contour of the trench. One approach in reducing the p liners' contribution to the output capacitance is to eliminate that portion of the p liners extending across the bottom of the trenches, as shown inFIG. 8. In this manner, the output capacitance is reduced while the same breakdown voltage is maintained since p strips806a,b(FIG. 8) spread the depletion region deeper into the drift regions.

An exemplary set of process steps for forming the structure ofFIG. 8is shown inFIGS. 9athrough9c. InFIG. 9a, a hard mask906along with conventional silicon trench etch methods are used to etch epitaxial region902to form wide trenches904a,904b. Using the same mask, p liners908are formed by implanting p-type impurities at about a 45° angle into both sidewalls and bottom of the trenches using conventional methods. InFIG. 9b, conventional silicon etch method is carried out to remove the portion of the p liners along the bottom of the trenches, leaving p strips908a,balong the sidewalls of the trenches. InFIG. 9c, a thermally-grown oxide layer910a,bis formed along the inner sidewalls and bottom of each trench. The p-type dopants in p strips908a,bare then activated using conventional methods. Conventional oxide deposition steps (e.g., SOG method) are carried out to fill the trenches with oxide, followed by planarization of the oxide surface. Conventional process steps used in forming the gate structure in self-aligned gate DMOS structures are then carried out to form the full structure as shown inFIG. 9c. Note that in theFIGS. 7 and 8structures the thermally grown oxide liners, similar to those inFIG. 9c, are present but are not shown for simplicity. The thermally grown oxide layers are included to provide a cleaner interface between the trench insulator and the p strips.

From the above, it can be seen that manufacturing of theFIG. 8structure is less complex than that of theFIG. 5structure because of the extra steps required in forming the floating p regions in theFIG. 5structure.

The doping concentration in the p liners/strips inFIGS. 6-8impacts the output capacitance of each of these structures. Highly-doped p regions lead to higher output capacitance since a higher reverse bias potential is needed to fully deplete these p regions. Thus, a low doping concentration (e.g., of about 1×1017 cm-3) would be desirable for these p regions. Note that these p regions have less effect on the output capacitance at high operating voltages.

FIGS. 10a-10cshow cross sectional views of three power MOSFET cell arrays each of which includes strips of semi-insulating material (e.g., oxygen-doped polysilicon SiPOS) along the trench sidewalls. In all three figures, wide insulation-filled trenches1004a,bare used to achieve improved thermal performance as in previous embodiments. Also, the semi-insulating strips in these structures function similar to polysilicon106a,bin the prior artFIG. 1in pushing the depletion region deeper into the drift region, thus improving the breakdown voltage.

InFIG. 10a, strips1006a,bof semi-insulating material extend along the trench sidewalls and are insulated from epitaxial region1002and body regions1008a,bby a layer of insulating material1010a,b. Strips1006a,bare in electrical contact with the top metal layer1018, and thus are biased to the same potential as the source and body regions.

InFIG. 10b, strips1020a,bof semi-insulating material are integrated in the cell array in a similar manner to those inFIG. 10aexcept that strips1020a,bare insulated from the top metal layer1018and thus are floating. During operation, the potential in the space charge region couples to the semi-insulating strips through insulation layers1010a,bto bias the strips to a corresponding mostly uniform potential.

InFIG. 10c, the insulation-filled trenches1024a,bextend all the way through epitaxial region1002and terminate in substrate1000. Semi-insulating strips1022a,bextend along the sidewalls of the trenches and electrically contact the source terminal through the top metal layer1018and the drain terminal through substrate region1000. Thus, the strips form a resistive connection between drain and source terminals. During operation, the strips acquire a linear voltage gradient with the highest potential (i.e., drain potential) at their bottom to lowest potential (i.e., source potential) at their top. Strips1022a,bare insulated from epitaxial regions1002by insulating layers1026a,b. The gate structure inFIG. 10cas well as inFIGS. 10aand10bis similar to the previous embodiments.

The semi-insulating strips in the structures ofFIGS. 10a-10cserve as an additional tool by which the electrical characteristics of the device can be optimized. Depending on the application and the design targets, one structure may be preferred over the other. The resistivity of the strips of semi-insulating material in each of theFIGS. 10a,10b,10cstructures can be adjusted and potentially varied from the top to the bottom to enable shaping of the space charge region formation in response to the applied drain-source voltage VDS.

An exemplary set of process steps for forming the structure inFIG. 10ais as follows. A hard mask is used to etch the silicon back to form wide trenches as in previous embodiments with wide trenches. A layer of thermally grown oxide having a thickness in the range of 200-1000 Å is then formed along the inner walls and bottom of the trench. About 4000 Å of conformal oxide is then deposited over the thermally grown oxide layer. Oxygen-doped polysilicon (SiPOS) is then deposited in the trench regions and etched to form strips1008a,balong the sidewalls. The trenches are then filled with insulation using conventional methods (e.g., SOG method), followed by planarization of the oxide surface. Conventional steps used in forming self-aligned gate DMOS structures are then carried out to form the full cell structure as shown inFIG. 10a.

The depth of the trenches in the different embodiments described above may vary depending on the desired device performance and the target application for the device. For example, for high breakdown voltage (e.g., greater than 70V), the trenches may be extended deeper into the epitaxial region (e.g., to a depth of about 5 μm). As another example, the trenches can be extended all the way through the epitaxial region to meet the substrate regions (as inFIG. 10c). For lower voltage applications, the p regions (e.g., the floating p regions inFIG. 2and the p strips inFIG. 8) need not extend deep into the epitaxial region since the device is not required to meet high breakdown voltages, and also to minimize the contribution of the p regions to the output capacitance.

Although the trench structures in the different embodiments described above are shown in combination with the gate structure of conventional DMOS cells, the invention is not limited as such. Two examples of other gate structures with which these trench structures may be combined are shown inFIGS. 11 and 12. These two cell structures have the benefit of lower gate to drain capacitance which in combination with the low output capacitance of the trench structures yields power devices particularly suitable for high frequency applications.

TheFIG. 11structure is similar to that inFIG. 8except that a substantial portion of the gate extending over the surface of the drift region is eliminated. Thus, the gate to drain capacitance is reduced by an amount corresponding to the eliminated portion of the gate. In theFIG. 12structure, the trench structure inFIG. 8is combined with the gate structure of a conventional UMOS cell. Thus, the advantages of the UMOS cell (e.g., low on-resistance) are obtained while the low output capacitance and improved thermal performance of the trench structure in accordance with the present invention are maintained. In one embodiment wherein theFIG. 12structure is intended for lower voltage applications (e.g., in the range 30-40V) the depth of p strips1208a,bis relatively shallow (e.g., in the range of 1.5 μm to 3 μm).

Combining the gate structures inFIGS. 11 and 12or any other gate structure with the different trench structures described above would be obvious to one skilled in this art in view of this disclosure.

In the above embodiments, the vertical charge control enabled by the resistive elements located along the insulation-filled trenches allows the cells to be laterally spaced apart without impacting the electrical characteristics of the device. With the cells spaced further apart, the heat generated by each cell is distributed over a larger area and less heat interaction occurs between adjacent cells. A lower device temperature is thus achieved.

Although the above embodiments show the drain to be located along the bottom-side of the die, the invention is not limited as such. Each of the above cell structures can be modified to become a quasi-vertically conducting structure by including a highly-doped n-type buried layer extending along the interface between the epitaxial region and the underlying highly-doped substrate region. At convenient locations, the buried layer is extended vertically to the top surface where it can be contacted to form the drain terminal of the device. In these embodiments, the substrate region may be n-type or p-type depending on the application of the MOSFET.

As mentioned earlier, edge termination structures with breakdown voltages equal to or greater than that of the individual cells are required to achieve a high device breakdown voltage. In the case of theFIG. 8structure, simulation results indicate that terminating at the outer edge of the device with a trench structure like trench804bwould result in higher electric fields due to the electric field transition up to the top surface at the outside of the outer trench. An edge termination structure which yields the same or higher breakdown voltage than the cell structure inFIG. 8is shown inFIG. 13.

InFIG. 13, the active gate over the drift region between the outer two trenches1306band1306cis eliminated allowing the drift region spacing Lt between these outer two trenches to be reduced to less than the drift region spacing Lc in the cell structures. The active gate however may be left in if obtaining the Lt spacing does not require its removal. The outer p strip1308dis not biased (i.e., is floating), and may be eliminated if desired. A conventional field plate structure1310is optionally included inFIG. 13. The termination structure inFIG. 13results in: (a) the depletion region terminating within the outer trench1306c, thus reducing the electric filed at the outside of trench1306c, and (b) the field on the inside of outer trench1306cis reduced due to short Lt spacing pushing the depletion region into the drift region.

In another embodiment, the gate structure is included between trenches1306band1306c, with spacing Lt equaling spacing Lc. In this embodiment, the p strip immediately to the right of the gate structure between trenches1306band1306c(i.e., the p strip corresponding to the strip along the left side of trench1306c) is not connected to the source and thus floats.

Other variations of theFIG. 13embodiment are possible. For example, floating guard-rings may be used on the outside of trench1306cwith or without field plate structure1310. Although cell trenches1306a,band termination trench1306care shown to be narrower than the cell trenches inFIG. 8, trenches1306a,b,c may be widened as inFIG. 8. Further, the width Wt of termination trench1306cmay be designed to be different than cell that of trenches1306a,bif desired.

FIG. 14is a cross sectional view showing another termination structure in combination with the cell structure shown inFIG. 8. As shown, the termination structure includes a termination trench1408lined with an insulation layer1410along its sidewalls and bottom. A field plate1406(e.g., from doped polysilicon) is provided over insulation layer1410in trench1408, and extends laterally over the surface and away from the active regions.

Although the above-described termination structures are shown in combination with the cell structure inFIG. 8, these and other known termination structures may be combined with any of the cell structures described above.

While the above is a complete description of the embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, the different embodiments described above are n-channel power MOSFETs. Designing equivalent p-channel MOSFETs would be obvious to one skilled in the art in light of the above teachings. Further, p+ regions, similar to p+ regions210a,bin theFIG. 2structure, may be added in the body regions of the other structures described herein to reduce the body resistance and prevent punch-through to the source. Also, the cross sectional views are intended for depiction of the various regions in the different structures and do not necessarily limit the layout or other structural aspects of the cell array. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.