Content aware decoding using shared data statistics

A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier 1 decoder, a tier 2 decoder, or a tier 3 decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

BACKGROUND

Field

Embodiments of the present disclosure generally relate to data error detection and correction, and more particularly, the use of data statistics for content aware error detection and correction.

Description of the Related Art

As data storage products requirements increase, the performance limit of a single decoder of stored data for transmission to a host have been reached. In response, many data storage products have employed pools of decoders. To improve quality of service (QoS), an individual decoder may maintain statistical information about content characteristics, as blocks of data decoded together typically have similar data characteristics. By maintaining statistical information, a decoder may be configured to decode more efficiently by predictively configuring its decoding strategy based on data statistics.

However, because the data statistics are based on the data decoded by an individual decoder, their predictive ability may be limited, resulting in, for example, missed predictions that result in “head of line blocking” scenarios that may degrade QoS.

What is needed are systems and methods that overcome these and other deficiencies.

SUMMARY

The present disclosure generally relates to content aware decoding using shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier1decoder, a tier2decoder, or a tier3decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

In one embodiment, a data storage device is disclosed that includes a non-volatile memory (NVM), and a controller coupled to the NVM that includes a plurality of decoders, a first decoder configured to receive a first codeword, the first decoder configured to generate first data statistics for the first codeword, and a second decoder configured to receive a second codeword, the second decoder configured to generate second data statistics for the second codeword. The data storage device further includes a joint data statistics module configured to receive the first and second data statistics.

In another embodiment, a controller for a data storage device is disclosed. The controller includes an I/O to one or more NVMs, and a processor configured to perform a method for content aware decoding. The method includes receiving a codeword from the one or more NVMs at a first decoder, generating data statistics for the codeword, and providing the data statistics to a joint statistics module, the joint statistics module coupled to a plurality of decoders that include the first decoder.

In another embodiment, a system for storing data is disclosed, including an NVM means, and a controller means for executing a method for content aware decoding. The method includes receiving from the NVM means at a first decoder means of a plurality of decoder means, a first codeword, decoding the first codeword at the first decoder means, and generating a first data statistic based on decoding the first codeword. The method further includes updating a joint data statistics module coupled to each of the plurality of decoder means, with the first data statistic, receiving a second a second codeword from the NVM means, and assigning the second codeword to a second decoder means of the plurality of decoder means, based on the joint data statistics module.

DETAILED DESCRIPTION

The present disclosure generally relates to content aware decoding using shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier1decoder, a tier2decoder, or a tier3decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

FIG.1is a schematic block diagram illustrating a storage system100in which data storage device106may function as a storage device for a host device104, according to certain embodiments. For instance, the host device104may utilize a non-volatile memory (NVM)110included in data storage device106to store and retrieve data. The host device104comprises a host DRAM138. In some embodiments, the storage system100may include a plurality of storage devices, such as the data storage device106, which may operate as a storage array. For instance, the storage system100may include a plurality of data storage devices106configured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for the host device104.

The data storage device106includes a controller108, NVM110, a power supply111, volatile memory112, an interface114, and a write buffer116. In some embodiments, the data storage device106may include additional components not shown inFIG.1for the sake of clarity. For example, the data storage device106may include a printed circuit board (PCB) to which components of the data storage device106are mechanically attached and which includes electrically conductive traces that electrically interconnect components of the data storage device106, or the like. In some embodiments, the physical dimensions and connector configurations of the data storage device106may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5″ data storage device (e.g., an HDD or SSD), 2.5″ data storage device, 1.8″ data storage device, peripheral component interconnect (PCI), PCI-extended (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device106may be directly coupled (e.g., directly soldered) to a motherboard of the host device104.

The interface114of the data storage device106may include one or both of a data bus for exchanging data with the host device104and a control bus for exchanging commands with the host device104. The interface114may operate in accordance with any suitable protocol. For example, the interface114may operate in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. The electrical connection of the interface114(e.g., the data bus, the control bus, or both) is electrically connected to the controller108, providing electrical connection between the host device104and the controller108, allowing data to be exchanged between the host device104and the controller108. In some embodiments, the electrical connection of the interface114may also permit the data storage device106to receive power from the host device104. For example, as illustrated inFIG.1, the power supply111may receive power from the host device104via the interface114.

The NVM110may include a plurality of memory devices or memory units. NVM110may be configured to store and/or retrieve data. For instance, a memory unit of NVM110may receive data and a message from the controller108that instructs the memory unit to store the data. Similarly, the memory unit of NVM110may receive a message from the controller108that instructs the memory unit to retrieve data. In some examples, each of the memory units may be referred to as a die. In some embodiments, a single physical chip may include a plurality of dies (i.e., a plurality of memory units). In some embodiments, each memory unit may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

In some embodiments, each memory unit of NVM110may include any type of NVM devices, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magnetoresistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of NVM devices.

The NVM110may comprise a plurality of flash memory devices or memory units. NVM Flash memory devices may include NAND or NOR based flash memory devices and may store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of blocks, which may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller108may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level.

The data storage device106also includes volatile memory112, which may be used by controller108to store information. Volatile memory112may include one or more volatile memory devices. In some embodiments, the controller108may use volatile memory112as a cache. For instance, the controller108may store cached information in volatile memory112until cached information is written to NVM110. As illustrated inFIG.1, volatile memory112may consume power received from the power supply111. Examples of volatile memory112include, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)).

The data storage device106includes a controller108, which may manage one or more operations of the data storage device106. For instance, the controller108may manage the reading of data from and/or the writing of data to the NVM110. In some embodiments, when the data storage device106receives a write command from the host device104, the controller108may initiate a data storage command to store data to the NVM110and monitor the progress of the data storage command. The controller108may determine at least one operational characteristic of the storage system100and store the at least one operational characteristic to the NVM110. In some embodiments, when the data storage device106receives a write command from the host device104, the controller108temporarily stores the data associated with the write command in the internal memory or write buffer116before sending the data to the NVM110.

The controller108includes a decoder pool150. The decoder pool150may be part of a low-density parity-check (LDPC) engine of the controller108. The decoder pool150may include one or more decoders, where each of the one or more decoders have one or more gears. Each of the one or more gears may either be a tier1, a tier2, or a tier3decoder. The exemplification of the different tiers of decoders is not intended to be limiting, but to provide an example of a possible embodiment. For example, the usage of the term “tier” may be utilized as a placeholder for different decoders specialized for different cases. Furthermore, more than or less than the exemplified tiers of decoders are contemplated.

The tier2decoder may be utilized for less intensive decoding tasks, such as for low bit error rate (BER) codewords and the tier3decoder may be utilized for more intensive decoding tasks, such as for higher BER codewords. In other embodiments, the selected decoder may be based on whether the receive codeword exceeds some certain syndrome weight threshold of the tier1decoder, the tier2decoder, or the tier3decoder. The decoder utilized may be dependent on the decoding operation as well as the current resources utilized, such as current power consumption by the other components of the data storage device. The various decoders may use a tradeoff between latency and power to correction capability, such that the tradeoff is a gear shifting scheme. For example, the tier1decoder may be a bit flipping decoder, while the tier2and the tier3decoders may be message passing decoders. In this context, a tier2decoder would be a fasteter message passing decoder while a tier3would be a stronger message passing decoder.

FIG.2is a schematic block diagram illustrating a decoder pool architecture200, according to disclosed embodiments. The decoder pool architecture200may be the decoder pool150ofFIG.1. In conventional approaches, a codeword provided to a decoder pool may be provided first to a low order decoder (e.g., tier1decoder), but if the low order decoder fails, send the codeword to a higher order decoder (e.g., tier2and/or tier3decoder). Rather than using a single tier1+tier2+tier3engine, the gears are divided into pools of independent decoders. For example, if a codeword takes a long decode latency with the tier3decoder, the tier1decoder and the tier2decoder may still decode other codewords that may have shorter decode latency than the tier3decoder. The decoder pool architecture includes a plurality of tier1decoders204a-n, a plurality of tier2decoders206a-n, and a plurality of tier3decoders208a-n. In some embodiments, the number of tier1decoders is greater than the number of tier2decoders and the number of tier2decoders is greater than the number of tier3decoders.

Furthermore, the controller, such as the controller108may be configured to determine which decoder of the plurality of decoders204a-n,206a-n,208a-nwill decode the received codeword. The received codeword may be from volatile memory, such as the volatile memory112ofFIG.1, or from the NVM, such as the NVM110ofFIG.1. For example, if the controller determines that the received codeword includes a high BER, the received codeword may be decoded by one of the plurality of tier3decoders208a-n, rather than one of the plurality of tier1decoders204a-nor one of the plurality of tier2decoders206a-n. If a codeword is sent to a lower order decoder but fails to properly decode, the tier1decoder updates a joint statistics pool (discussed below), and in some embodiments, may also update its own data statistics (discussed below), before passing the codeword to a higher-order decoder.

An Iterative Content Aware Decoder (ICAD) may be embedded with each decoder of the plurality of decoders204a-n,206a-n,208a-nof the decoder pool202. The ICAD allows for the host data statistics to be embedded in the decoder computation logic, such that the decoder works better when better host data statistics are stored. When host data statistics are not available, the data statistics are estimated for the relevant codeword. Furthermore, the ICAD works in an iterative manner, such that the ICAD iterates between decoding the codeword and re-estimating the host data statistics.

Because the host minimum data size may be larger than a flash memory unit (FMU) size, data may be stored across multiple sequential FMUs of the NVM, such as the NVM110ofFIG.1. Because data is read sequentially, codewords may hold similar host data and have similar data statistics. The ICAD may extract the data statistics and share the extracted data statistics among the decoders of the plurality of decoders204a-n,206a-n,208a-nof the decoder pool202. Furthermore, the data statistics may also be jointly estimated and shared among the decoders of the plurality of decoders204a-n,206a-n,208a-nof the decoder pool202. By jointly estimating the data statistics and sharing the joint estimated statistics across each decoder of the plurality of decoders204a-n,206a-n,208a-nof the decoder pool202, decoder latency, correction capability, and system performance may be improved. It is to be understood that the previously described example is not intended to be limiting.

FIG.3Ais an example of a set300of 4 bit words.FIG.3Bis a histogram350illustrating the 4 bit word arrangement frequency of the set300ofFIG.3A. Each four bit combination corresponds to a bit word that is a binary representation of a decimal value. For example, the four bit combination may be in a form of “abcd”, where “a”, “b”, “c”, and “d” each corresponds to either a 0 or a 1. The four bit combination may converted from binary to decimal by the following equation: (abcd)2=(a×23)+(b×22)+(c×2′)+(d×20)=(x)10, where “x” is the decimal value of the binary four bit combination. Each of the 4 bit words corresponds to a value between 0 and 15. For example, 0000 equals 0, 0110 equals 6, and 1111 equals 15.

The histogram350is a graphical representation of the frequency of each value of the 4 bit word of the set300. For example, 0000 or 0 occurs 4 times and 1111 or 15 occurs 10 times in the set300. The histogram350may be dynamically updated for each new 4 bit word of the set300. For example, the value 15 has the highest frequency, and the value 5 has the lowest frequency. When the decoder or the joint data statistics module receives a 4 bit word, where one or more of the bits are corrupted, the decoder or the joint data statistics module may utilize the histogram350to determine what the one or more bit values may be. For example, the 4 bit word x110is received by the decoder or the joint data statistics module, where “x” refers to the bit that is unknown. The 4 bit word may either be 6, where the 4 bit word is 0110, or 14, where the 4 bit word is 1110. When analyzing the histogram350, the value of 6 has a higher probability of occurring than the value of 14, such that the decoder or the joint data statistics module may estimate that the unknown bit is “0”. However, without the histogram350statistics, the best guess estimate of what the unknown bit could be would be 50% “0” and 50% “1”.

FIG.4is a schematic illustration of an ICAD logic400, according to disclosed embodiments. The ICAD logic400includes one or more symbol nodes402,404, a plurality of bit nodes406a-p, and a plurality of check nodes408a-h. The plurality of bit nodes406a-pmay be collectively referred to as the plurality of bit nodes406, and the plurality of check nodes408a-hmay be collectively referred to as the plurality of check nodes408. Each of the one or more symbol nodes402,404may be associated with about 8 bit nodes in the depicted embodiment, such that a first symbol node402is associated with bit nodes406a-hand a second symbol node404is associated with bit nodes406i-p.

In one embodiment, bits in the data are dependent. For example, in a text file, the bits are organized in bytes where each byte represents a character. In the example of a text file, the most used characters are alphanumeric, spaces and punctuation marks, while the rest of the characters are less common. This indicates that bits from the same byte are statistically dependent and knowing part of the bits within a byte increases the reliability of the other bits within the same byte. The data may be divided into groups such that all bits in a group are statistically dependent. Each group is considered as a symbol or a symbol node.

InFIG.4, the symbols are groups of 8 bits, indicated by the 8 bit nodes406a-h,406i-p. During the decoding operation performed by the ICAD, each of the one or more symbol nodes402,404sends a message to each bit node of the plurality of bit nodes406. The message may include the probability of the bit to be “0” or “1” as described inFIGS.3A and3B, above, according to the information from the other bits of the same codeword and the data statistics that reflect the probability of each symbol. The check nodes408are provided to check the values in each of the bit nodes of the plurality of bit nodes406to ensure that the bit node values are accurate. The check nodes408may include parity constraints of the codeword bits, such that the bit node values are constrained.

The probabilities may be learned during the encoding procedure, where the data is obtained without errors. However, learning the statistics during the encoding procedure may be costly as the learned statistics will need to be stored in the memory, such as the NVM110ofFIG.1, of the data storage device. By scanning the data and counting the occurrence of each symbol in the data, such as during the data statistics estimation scheme described above, probabilities are computed and stored as additional information for future reads of the data. Furthermore, the probabilities may be learned from the read data itself. The number of errors may be sufficiently low, such that probabilities with high accuracy maybe obtained. The probabilities may also be estimated during the decoding procedure. At each stage of decoding, each bit holds its probability to be “0” or “1”, as mentioned above. Given these probabilities, the probabilities for each occurrence of each symbol may be obtained.

FIG.5is a schematic block diagram illustrating an implementation of an ICAD in a decoder pool, according to disclosed embodiments. The decoder pool may be the decoder pool202ofFIG.2. Rather than having a host data statistics estimation module for each decoder of the plurality of decoders502a-n, the plurality of decoders502a-nare coupled to a joint data statistics estimation module504, such that the data statistics are jointly estimated by all of the decoders of the plurality of decoders502a-ncoupled to the joint data statistics estimation module504.

The data statistics may be jointly estimated for each decoder of the plurality of decoders502a-nby keeping a joint representation of the data statistics for all codewords of “k” bit length, where “k” refers to a numerical value of the bit length. The data statistics may be stored as a histogram, such as the histogram350ofFIG.3, in each decoder of the plurality of decoders502a-n, where the histogram is continuously updated with each codeword decoded with a “k” bit length. Each of the plurality of decoders502a-nsends the updated statistics to the joint data statistics estimation module504, where the joint data statistics module504consolidates the individual updated statistics and sends back the global statistics to each decoder of the plurality of decoders502a-n.

At each step that the individual decoder, such as the first decoder502a, passes the updated data statistics to the joint data statistics estimation module504, the decoder passes the difference from the previous estimation. For example, the difference may be exemplified as “bin1: +5, bin2: −7,” and so-forth. When the decoding of the codeword is completed, the host data associated with the decoded codeword is transferred to the target location, such as the host device, where the data statistics may be a noiseless version.

The data from each decoder may be taken using a weight that reflects the reliability, such that codewords at the beginning of the decoding operation or with high bit error rate are given a higher weight than codewords that are almost or fully decoded. Furthermore, past decoded codewords may also be taken into account with a certain weight, which may decrease with time to reflect changes in the data and to allow the data statistics to change with respect to time. The weights may account for the probability of receiving a certain bit of the codeword, as described inFIGS.3A and3B.

Referring to the flowchart700ofFIG.7, the first decoder502areceives a first codeword from the NVM, such as the NVM110ofFIG.1, at block702. The first codeword may be assigned to a tier1, a tier2, or a tier3decoder based on the characteristics of the codeword, such as the bit error rate. The first codeword is decoded by the first decoder502a,where a first data statistic for the first codeword is generated and stored by the first decoder502aat block704. After generating the first data statistic for the first codeword, the generated first data statistic is transferred to the joint data statistics estimation module504at block706. It is to be understood that the timing of sending the generated first data statistic to the joint data statistics estimation module may be a configurable or adaptive timing based on the operation or the conditions of the data storage device, such as the data storage device106ofFIG.1. At block708, the controller, such as the controller108ofFIG.1, determines if the joint data statistics estimation module504includes more than one similar data statistic. As host data is often longer than an ECC code word and is usually read sequentially, decoded ECC words of close proximity in time may have similar data statistics. If there is not a similar data statistic, the controller waits to receive and assign a second codeword to a decoder.

A second decoder502breceives the second codeword from the NVM at block702. The second codeword and the first codeword are substantially similar, such that the data statistics of the codewords is similar. The second decoder502bdecodes the second codeword and generates a second data statistic associated with the second codeword at block704. The generated second data statistic is transferred to the joint data statistics estimation module504at block706.

The joint data statistics estimation module504receives both generated first data statistic and generated second data statistic at block708. Because the first codeword and the second codeword are substantially similar, the generated first data statistic is updated by the generated second data statistic, such that the global statistics includes the generated first data statistic and the generated second data statistic at block710. Furthermore, the joint data statistics estimation module504generates a histogram utilizing the global statistics at block710.

A third codeword is retrieved from the NVM by the controller, such as the controller108ofFIG.1at block712. Based on the global statistics, the appropriate decoder of the plurality of decoders502a-nreceives the third codeword. For example, the first decoder502amay receive the third codeword based on the generated histogram and the global statistics. The third codeword is decoded, and the third data statistics are generated at block714. At block716, the controller determines if there is a mismatch between the generated third data statistics and the global statistics. If there is not a mismatch at block716, then the generated third data statistics are transferred to the joint data statistics estimation module504at block718, where the global statistics and the histogram is updated with the generated third data statistics at block710. In some examples, the first codeword, the second codeword, and the third codeword are sequential.

FIG.6is a schematic block diagram illustrating an implementation of a selective data sharing ICAD in a decoder pool, according to disclosed embodiments. Aspects of the selective data sharing ICAD in a decoder pool ofFIG.6may be similar to the aspects of the ICAD in the decoder pool described inFIG.5. Furthermore, the decoder pool may be the decoder pool202ofFIG.2. Rather than coupling each decoder of the plurality of decoders602a-nto the joint data statistics estimation module604, such as the embodiment depicted inFIG.5, each decoder of the plurality of decoders602a-nare coupled to a respective data statistics estimation module of the plurality of data statistics estimation modules606a-n. Thus, each decoder—data statistic estimation module pair, such as the first decoder602aand the first data statistics estimation module606ais coupled to the joint data statistics estimation module604.

If there is a mismatch between the data statistics of a decoder, such as the first decoder, and the global statistics of the joint data statics estimation module604, the decoder may decide to continue using the local data statistics rather than the global statistics. Similarly, the global statistics may not be updated using the local data statistics. The mismatch may be measured by correlation or by some other form of distance, such as a KL or JS divergence, and may hold different thresholds for either side. For example, there may be a case where the global statistics are updated, but not the local data statistics, or vice-versa.

Expanding on the example ofFIG.5, rather than providing the generated first data statistics, the generated second data statistics, and the generated third data statistics directly to the joint data statistics estimation module604, the generated data statistics may be stored by the relevant data statistics estimation module606a,606b.For example, the generated first data statistic and the generated second data statistic are transferred to the joint data statistics estimation module604at block706, where the joint data statistics estimation module604generates global statistics and a histogram based on the global statistics at block710.

However, due to a mismatch of the generated third data statistic and the global statistics provided to the first data statistics estimation module606aat block716, the generated third data statistics may be stored locally at block720. The first data statistics estimation module606amay then utilize the locally stored aggregated data statistic and the associated histogram rather than the global statistics and the associated histogram at block720. Each decoder of the plurality of decoders602a-nmay maintain a local data statistic, such that in the case of a mismatch, the more accurate aggregated data statistic and the associated histogram may be utilized.

Furthermore, each of the generated data statistics may be associated with a weight, such that the weight of a newly generated data statistic is weighted as more relevant than an older generated data statistic. The weight may allow for better flexibility and adaptability of the global statistic or the local data statistic to the received codewords, such that the data statistics and the associated histogram places more value on the newly generated codewords. For example, a second generated data statistic may have a greater weight associated with the generated data statistic than that of the first generated data statistic, where the first generated data statistic is generated prior to the second generated data statistic.

Referring toFIG.5andFIG.6, in certain implementations, there may be more than one joint data statistics estimation module, such that a first joint data statistics estimation module is coupled to a second statistics estimation module. Furthermore, it is to be understood that different types of decoders may require different realizations of data statistics. For example, a first decoder, such as a bit flipping decoder, may utilize a “k” bit histogram and a second decoder, such as a message passing decoder, utilizes an “n” bit histogram, where “k” and “n” are the values of the number of bits associated with each histogram. Each group of decoders of the same type (i.e., decoders utilizing “k” bit histograms) will hold a global statistics associated with the same type of data statistic. The joint data statistics estimation module504,604may be configured to store the different types of global statistics individually.

In another example, even though each decoder group mentioned above may be for different books of data statistics (i.e., decoders utilizing “k” bit histograms and decoders utilizing “n” bit histograms), the data from the same distribution may be passed between groups. In order to pass the data between the groups, adjustments may be made to the data. For example, an 8 bit histogram may be transformed to a 4 bit histogram by accumulating over all combinations that share the same 4 MSB without loss of data. In another example, 4 bit histograms may be combined with the results of an 8 bit histogram, where a certain factor is given to each group of 8 bits. In each of the 8 bits, the relevant 4 LSBs or 4 MSB may correspond to a certain value in the 4 bit histogram.

By adapting the architecture of the decoder pool to account for content aware decoding using shared data statistics, the latency of the decoding may decrease, the QoS may be improved, and the correction capability of the decoder may be improved.

In one embodiment, a data storage device is disclosed, that includes an NVM, and a controller coupled to the NVM, that includes a plurality of decoders, that includes a first decoder configured to receive a first codeword, the first decoder configured to generate first data statistics for the first codeword, and a second decoder configured to receive a second codeword, the second decoder configured to generate second data statistics for the second codeword. The data storage device further includes a joint data statistics module configured to receive the first and second data statistics.

The joint data statistics module is further configured to create an data histogram based on the first and second data statistics. The controller is configured to receive a third codeword, the third codeword being assigned to one of the plurality of decoders based on the data histogram. The first codeword and second codeword are substantially similar, and wherein the first data statistics are updated by the second data statistics in the joint data statistics module. The first decoder stores the first data statistics. The controller is configured to receive a third codeword. The first codeword, the second codeword, and the third codeword each assigned to the first decoder based on a syndrome weight or a bit error rate. The first decoder provides the third codeword to one of the plurality of decoders based on the first data statistics. Each decoder of the plurality of decoders includes one of a tier1decoder, a tier2decoder, and a tier3decoder. The controller is configured to receive a third codeword. The third codeword is assigned to one of the tier1decoder, the tier2decoder, and the tier3decoder based on the syndrome weight or the bit error rate.

In another embodiment, a controller for a data storage device is disclosed. The controller includes an I/O to one or more NVMs and a processor configured to perform a method for content aware decoding. The method includes receiving a codeword from the one or more NVMs at a first decoder, generating data statistics for the codeword, and providing the data statistics to a joint statistics module, the joint statistics module coupled to a plurality of decoders that include the first decoder.

Each decoder of the plurality of decoders includes one of a tier1decoder, a tier2decoder, and a tier3decoder. The method further includes receiving a second codeword from one or more of the NVMs and assigning the second codeword to one of the plurality of decoders based on the joint statistics module. Each one of the plurality of decoders locally maintains data statistics and provides data statistics to the joint statistics module. The method further including assigning the second codeword to one of the plurality decoders based on locally maintained data statistics. The method further including where a statistical mismatch is detected between locally maintained data statistics and the joint statistics module. The method further including where one of the joint statistics module and locally maintained data includes a histogram. The method further including where newer ones of the data statistics are weighted as more relevant than older ones of the data statistics.

In another embodiment, a system for storing data is disclosed, including an NVM means, and a controller means for executing a method for content aware decoding. The method includes receiving from the NVM means at a first decoder means of a plurality of decoder means, a first codeword, decoding the first codeword at the first decoder means, and generating a first data statistic based on decoding the first codeword. The method further includes updating a joint data statistics module coupled to each of the plurality of decoder means, with the first data statistic, receiving a second a second codeword from the NVM means, and assigning the second codeword to a second decoder means of the plurality of decoder means, based on a syndrome weight or a bit error rate.

The method further includes generating a second data statistic at the second decoder means and updating the joint data statistics module based on the second data statistics. The second data statistic is weighted as more relevant than the data statistics. Each one of the plurality of decoder means is configured to provide data statistics to the joint data statistics module. The assignment of subsequent codewords from the NVM means to one of the plurality of decoder means is based on the syndrome weight or the bit error rate.