SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

BACKGROUND

With the rapid growth of the electronics industry, the development of integrated circuits (ICs) consistently demands improvements in performance and miniaturization. Technological advances in IC materials and design have produced generations of ICs in which each generation has smaller and more complex circuits than the previous generation. A plurality of transistors and passive components (such as resistors, capacitors, and inductors) are commonly used as fundamental construction building blocks for ICs. Since the area occupied by each component is usually considered as a cost in the semiconductor manufacturing process, the dimensions and areas of the passive components are of prime consideration in the design of the IC layout. A semiconductor device free from the constraints imposed by dimensions of passive components is therefore called for.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are disclosed as follows using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations or modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

Further, it is understood that several processing steps and/or features of a device may be only briefly described. Also, additional processing steps and/or features can be added, and certain of the following processing steps and/or features can be removed or changed while still implementing the claims. Thus, it is understood that the following descriptions represent examples only, and are not intended to suggest that one or more steps or features are required.

FIG.1is a diagram illustrating a concept of area reduction in IC layout design, in accordance with some embodiments.FIG.1shows two IC layouts10and10′. In some embodiments, the IC layout10includes four regions102,104,106, and108. Two active components, such as transistors T1and T2, can be located within the regions102and104. Two passive components, such as resistors R1and R2, can be located within the regions106and108. The IC layout10′ includes four regions102,104,106, and108. A hybrid component including an active component (e.g., transistor T1) and a passive component (e.g., resistor R1) can be located at the regions102and106. Similarly, another hybrid component including an active component (e.g., transistor T2) and a passive component (e.g., resistor R2) can be located within at the regions104and108.

In some embodiments, the resistor R1may be embedded in a portion of the transistor T1and the resistor R2may be embedded in a portion of the transistor T2. The IC layout10′ includes the same number of components (i.e., two transistors and two resistors) as IC layout10, but can occupy less overall area on the semiconductor wafer. With the hybrid components introduced in the IC layout10′, an area reduction can be achieved. In some embodiments, the IC layout10′ may be one cell unit. The IC layout10′ integrated a pair of resistors and a pair of transistors into one cell unit and no extra area is required.

FIG.2illustrates a circuit that can benefit from the proposed layout design, in accordance with some embodiments.FIG.2shows a current mirror circuit20. The current mirror circuit20includes transistors T1and T2, resistors R1and R2, and a current source22. The resistor R1is electrically connected to the source terminal of the transistor T1. The resistor R2is electrically connected to the source terminal of the transistor T2. The gate terminal of the transistor T1is electrically connected to the drain terminal of the transistor T1. The current source22is electrically connected to the drain terminal of the transistor T1. The gate terminal of the transistor T1is electrically connected to the gate terminal of the transistor T2.

The current mirror circuit20can be utilized in a current-controlled oscillator (ICO), in which the resistors R1and R2can be referred to as a “source degeneration” mechanism that can reduce the noise of the ICO.

The resistors R1and R2can be selected to be the same (for example, resistor Rs) in the “source degeneration” mechanism for ICO, and can improve the noise current of the ICO by a factor “1+gm*Rs.” The parameter “gm” represents the transconductance of the transistors T1and T2, and the Rs is selected to be greater than 1/gm. In traditional layout design for the current mirror circuit20, resistors R1and R2usually occupy regions different from those for transistors T1and T2(for example, see the IC layout10ofFIG.1). The IC layout10can be considered less area-efficient. On the contrary, if the resistor R1and the transistor T1can be located within the same region110, and the resistor R2and the transistor T2can be located within the same region112, as those arranged in the IC layout10′ ofFIG.1, the area usage of the ICO on a semiconductor wafer can be reduced. The transistor T1and the resistor R1within the region110can be implemented by any one of the layout structures as shown in accordance with some embodiments of the present disclosure. The transistor T2and the resistor R2within the region112can be implemented by any one of the layout structures shown in accordance with some embodiments of the present disclosure.

FIG.3is a diagram illustrating a concept of area reduction in IC layout design, in accordance with some embodiments.FIG.3shows one IC layout10′. In some embodiments, the IC layout10′ includes two transistors T1and T2and two resistors R1and R2. The resistor R1is located adjacent to the transistor T1. The resistor R2is located adjacent to the transistor T2. The resistor R2is located adjacent to the resistor R1. One hybrid component includes an active component (e.g., transistor T2) and a passive component (e.g., resistor R2). The area “A” ofFIG.3includes one hybrid component.

FIG.4is a semiconductor device including a transistor and an embedded resistor, in accordance with some embodiments. The semiconductor device15as shown inFIG.4pertains to a semiconductor device including a transistor T2and a resistor R2. Alternatively, the semiconductor device15can also be deemed as a transistor having an embedded resistor.

In some embodiments, the semiconductor device15can correspond to a top view perspective of the IC layout10′ within the area “A” including a transistor T2and a resistor R2. The semiconductor device15includes a substrate40, an active region OD, a gate structure G2, a source conductor MD1, a drain conductor MD2, two dummy gate structures DG1and DG2, and epitaxial contacts44. In some embodiments, the active region OD includes a first type doped region41and a second type doped region42. The active region OD is disposed on the substrate40.

In some embodiments, the semiconductor device15comprises the gate structure G2, the source conductor MD1, and the drain conductor MD2disposed on the active region OD. In some embodiments, the semiconductor device15comprises a first type doped region41of the active region OD below the gate structure G2. The semiconductor device15comprises a second type doped region42of the active region OD adjacent to the first type doped region. The first type doped region41is different from the second type doped region42. In some embodiments, the first type doped region41is a p-type doped region and the second type doped region42is a n-type doped region. In some embodiments, the first type doped region41is a n-type doped region and the second type doped region42is a p-type doped region. In some embodiments, when the semiconductor device15is turned on or operated, the second type doped region42is configured to function as a resistor48. The path within the second type doped region42through which the current passes corresponds to the resistor48. The source conductor MD1is disposed on the epitaxial contacts44, and the drain conductor MD2is disposed on the epitaxial contacts44.

In some embodiments, a first dummy gate structure DG1is disposed on the second type doped region42. A second dummy gate structure DG2is disposed on the second type doped region42. The second dummy gate structure DG2is disposed between the first dummy gate structure DG1and the source conductor MD1. In some embodiments, one of the epitaxial contacts44is disposed between the first dummy gate structure DG1and the gate structure G2. In some embodiments, one of the epitaxial contacts44is disposed adjacent to an interface between a boundary of the first type doped region41and a boundary of the second type doped region42. One of the epitaxial contacts44is disposed between the first dummy gate structure DG1and the second dummy gate structure DG2. A gate contact G2cis formed on the gate structure G2. In some embodiments, the number of the dummy gate structures can be increased. The newly added dummy gate structure can be disposed between the first dummy gate structure DG1and the source conductor MD1. The number of the dummy gate structures DG1and DG2of the semiconductor device15is 2. In some embodiments, the number of the dummy gate structures may be more than 2 (e.g., the number of the dummy gate structures may be 3, 4, 5 . . . , etc.). The resistance value of the resistor48increases with the increased number of total dummy gate structures. If the number of the total dummy gate structures is increased, the current path of the resistor48is correspondingly increased. Compared to the first type doped region41, the second type doped region42has a higher resistance value when the semiconductor device15is turned on or enabled.

The present disclosure provides a semiconductor device structure achieving a low noise performance by using a simple layout design which can be compatible with the process for manufacturing semiconductor devices. The device of the present disclosure consists of a pair of resistors and transistors into an unit of the semiconductor device. The present disclosure adopts a simple layout design for multi-finger structures. The properties of the resistors R1and R2and transistors T1and T2can be controlled independently. In some embodiments, the resistance value of the n-type well resistor may be controlled by the number/size of dummy gate structures on the resistor R1/R2.

FIG.5is a layout of a semiconductor device including two transistors and two embedded resistors, in accordance with some embodiments. The layout30shown inFIG.5pertains to a semiconductor device including two transistors and two resistors. The layout30can correspond to a top view perspective of a semiconductor device including two transistors and two resistors. The layout30includes an active region OD, a gate structure G1, a gate structure G2, a source conductor MD1, two drain conductors MD2, dummy gate structures DG1, DG2, DG3, DG3, DG4, and DG5, conductors CD1and CD3, and poly structures PD1and PD2. The active region OD can also be referred to as oxide diffusion region OD. The poly structures PD1and PD2can be referred to as poly structures on OD edges, or simply “PODE.”

The source conductor MD1and the drain conductor MD2are disposed on opposite sides of the gate structure G1. In some embodiments, a conductive via V1is disposed on the source conductor MD1and a conductive via V2is disposed on the drain conductor MD2. The source conductor MD1and the drain conductor MD2are disposed on opposite sides of the gate structure G2. The length of the source conductor MD1is shorter than the length of the gate structure G1from a top view. The length of the source conductor MD1is shorter than the length of the gate structure G2from a top view. The length of the drain conductor MD2is shorter than the length of the gate structure G1from a top view. The length of the drain conductor MD2is shorter than the length of the gate structure G2from a top view. Since the lengths of the source conductor MD1and the drain conductor MD2are the same, the semiconductor device manufactured in accordance with the layout30can be referred to as a device with balanced source/drain conductors.

The drain conductor MD2includes edges e1and e2, the active region OD includes edges e3and e4, and the gate conductor G2includes edges e5and e6. The edges e3and e4of the active region OD can also be referred to as boundaries e3and e4. The edge e1of the drain conductor MD2is misaligned with the edge e3of the active region OD, and edge e2of the drain conductor MD2is misaligned with the edge e4of the active region OD. The edges e3and c4of the active region OD can be located between edges e1and e2of the drain conductor MD2. The edges e3and e4of the active region OD can be located between edges e5and e6of the gate conductor G2.

The edge e5of the gate conductor G2is misaligned with the edge e3of the active region OD, and edge e6of the gate conductor G2is misaligned with the edge e4of the active region OD. The edges e1and e2of the drain conductor MD2are both outside the area (e.g., defined by edges e3and e4) of the active region OD. The edge e1of the drain conductor MD2is misaligned with the edge e5of the gate conductor G2, and edge e2of the drain conductor MD2is misaligned with the edge e6of the gate conductor G2.

In some embodiments, the drain conductor MD2are disposed over a single active region OD. In some embodiments, the drain conductor MD2will not extend to another active region (not shown) adjacent to the active region OD depicted inFIG.5.

The source conductor MD1, the gate structures G1and G2, and the drain conductors MD2can constitute a transistor T1/T2having resistor regions electrically connected to the source of the transistor T1/T2. In some embodiments, the length of the source conductor MD1can range from 0.1 times to 0.9 times that of the drain conductor MD2from a top view. In some embodiments, the length of the source conductor MD1can range from 0.1 times to 0.9 times that of the gate structure G1from a top view.

In some embodiments, the length of the source conductor MD1(i.e., along the y-axis) can range from 3 nm to 5 μm. In some embodiments, the length of the drain conductor MD2(i.e., along the y-axis) can range from 3 nm to 5 μm. In some embodiments, the width of the gate structure G1(i.e., along the x-axis) can range from 3 nm to 10 μm. The poly structures PD1and PD2can be useful in process control during manufacturing. The dummy gate structures DG1and DG2are optional (i.e., not mandatory in the layout30) and can be useful in reducing layout dependence effects. The number of the dummy gate structures can be increased or decreased depending on user requirements.

In some embodiments, a third dummy gate structure DG3is disposed on the second type doped region42. In some embodiments, a fourth dummy gate structure DG4is disposed on the first type doped region41. In some embodiments, a connection element C2is disposed on the active region OD. The connection element C2comprises a first portion C2a, a second portion C2b, and a third portion C2c. The first portion C2ais disposed between the second dummy gate structure DG2and the third dummy gate structure DG3. The first portion C2a, the second portion C2b, and the third portion C2care integrated in one piece. The connection element C2can direct the current via the first portion C2ato the third portion C2c. The connection element C2can bypass the path within the second type doped region42below the third dummy gate structure DG3by directing the current. The connection element C2can bypass the path within the first type doped region41below the fourth dummy gate structure DG4by directing the current. The resistance value of the semiconductor device15can be reduced by directing the current through the connection element C2. The first portion C2a, the second portion C2b, and the third portion C2care interconnected. The third portion C2cis disposed between the fourth dummy gate structure DG4and the gate structure G2.

In some embodiments, from a top view, an edge e7of the first portion C2ais located outside the edge3of the active region OD. The second portion C2bis located outside the edge4of the active region OD. In some embodiments, from a top view, the edge e1of the drain conductor MD2is located outside the active region OD from a top view. The edge e5of the gate structure G2is located outside the active region OD from a top view.

In some embodiments, a connection element C1is disposed on the active region OD and on both the first type doped region41and second type doped region42. The connection element C1comprises a first portion C1a, a second portion C1b, and a third portion C1c. The first portion C1ais disposed between the second dummy gate structure DG2and the third dummy gate structure DG3. The first portion C1a, the second portion C1b, and the third portion C1care integrated in one piece. In some embodiments, the first portion C1a, the second portion C1b, and the third portion C1ccan be formed and connected by one or more operations. The first portion C1aand the third portion C1ccan extend in the same direction (i.e., along the y-axis). The second portion C1bcan extend in a direction (i.e., along the x-axis) perpendicular to that of the first portion C1aand the third portion C1c.

The connection element C1can direct the current via the first portion C1ato the third portion C1c. The connection element C1can direct the current from the second type doped region42to the first type doped region41. The connection element C1can bypass the path within the second type doped region42below the third dummy gate structure DG3by directing the current. The connection element C1can bypass the path within the first type doped region41below the fourth dummy gate structure DG4by directing the current. The resistance value of the semiconductor device15can be reduced by directing the current through the connection element C1. The first portion C1a, the second portion C1b, and the third portion C1care interconnected. The third portion C1cis disposed between the fourth dummy gate structure DG4and the gate structure G2.

FIG.6is a cross section along the dashed line B-B′ ofFIG.5, in accordance with some embodiments, showing a semiconductor structure32including a substrate40, an active region OD, gate structures G1and G2, a source conductor MD1, drain conductors MD2, dummy gate structures DG1, DG2, DG3, DG4, and DG5, conductors CD1and CD3, connection elements C1and C2, and poly structures PD1and PD2. Source/drain structure(s) or S/D structure(s) may refer to a source structure or a drain structure, individually or collectively dependent upon the context. The active region OD can also be referred to as oxide diffusion region OD. The poly structures PD1and PD2can be referred to as poly structures on OD edges, or simplified as “PODE.”

The first type doped region41and second type doped region42are formed on the substrate40. The first type doped region41is different from the second type doped region42. In some embodiments, the first type doped region41is a p-type doped region and the second type doped region42is a n-type doped region. In some embodiments, the first type doped region41is a n-type doped region and the second type doped region42is a p-type doped region.

In some embodiments, when the transistor T1is turned on or operated, the second type doped region42below the first dummy gate structure DG1and the second dummy gate structure DG2is configured to function as a resistor R1. The path within the second type doped region42through which the current passes corresponds to the resistor R1. The source conductor MD1is disposed on the second type doped region42. In some embodiments, when the transistor T2is turned on or operated, the second type doped region42below the first dummy gate structure DG1and the second dummy gate structure DG2is configured to function as a resistor R2. The path within the second type doped region42through which the current passes corresponds to the resistor R2. The gate structure G1is disposed between the source conductor MD1and the drain conductor MD2. The gate structure G2is disposed between the source conductor MD1and the drain conductor MD2. The length of the source conductor MD1is shorter than the length of the gate structure G1from a top view. The length of the source conductor MD1is shorter than the length of the gate structure G2from a top view. The length of the drain conductor MD2is shorter than the length of the gate structure G1from a top view. The length of the drain conductor MD2is shorter than the length of the gate structure G2from a top view. The lengths of the source conductor MD1and the drain conductor MD2are the same. Therefore, the semiconductor structure32manufactured in accordance with the layout30can be referred to as a device with balanced source/drain conductors.

In some embodiments, the drain conductor MD2is disposed over a single active region OD. In some embodiments, the drain conductor MD2will not extend to another active region (not shown) adjacent to the active region OD depicted inFIG.6. In some embodiments, a conductive via V1is disposed on the source conductor MD1and a conductive via V2is disposed on the drain conductor MD2.

In some embodiments, the source conductor MD1, the gate structures G1and G2, and the drain conductors MD2can constitute a transistor T1/T2having resistor regions electrically connected to the source of the transistor T1/T2. In some embodiments, the source conductor MD1can range from 0.1 times to 0.9 times that of the drain conductor MD2from a top view. In some embodiments, the source conductor MD1can range from 0.1 times to 0.9 times that of the gate structure G1from a top view.

The poly structures PD1and PD2are useful in process control during manufacturing. The dummy gate structures DG1and DG2are optional (i.e., not mandatory in the semiconductor structure32) and can be useful in reducing layout dependence effects. The total number of the dummy gate structures can be increased or decreased depending on the user requirements.

In some embodiments, when the transistor T1is turned on or operated, the current from the source conductor MD1may pass through the path below the first dummy gate structure DG1and the second dummy gate structure DG2, and pass through the connection element C1. Then, the current passes through the path/channel below the gate structure G1and passes through the drain conductor MD2of the transistor T1. The source conductor MD1, drain conductor MD2, dummy gate structures DG1to DG5, gate structures G1and G2, and poly structures PD1and PD2are formed by any suitable process including various deposition, photolithography, and/or etching processes. An exemplary photolithography process includes forming a photoresist layer (resist) overlying substrate40, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element including the resist.

In some embodiments, a third dummy gate structure DG3is disposed on the second type doped region42. In some embodiments, a fourth dummy gate structure DG4is disposed on the first type doped region41different from the second type doped region42. In some embodiments, a connection element C2is disposed on the active region OD and on both the first type doped region41and second type doped region42. The connection element C2comprises a first portion C2a, a second portion C2b, and a third portion C2c. The first portion C2ais disposed between the second dummy gate structure DG2and the third dummy gate structure DG3. The first portion C2a, the second portion C2b, and the third portion C2care integrated in one piece. The connection element C2can direct the current via the first portion C2ato the third portion C2c. The connection element C2can direct the current from the second type doped region42to the first type doped region41. The connection element C2can bypass the path within the second type doped region42below the third dummy gate structure DG3by directing the current. The connection element C2can bypass the path within the first type doped region41below the fourth dummy gate structure DG4by directing the current. The resistance value of the semiconductor device15can be reduced by directing the current through the connection element C2. The first portion C2a, the second portion C2b, and the third portion C2care interconnected. The third portion C2cis disposed between the fourth dummy gate structure DG4and the gate structure G2.

In some embodiments, a fourth dummy gate structure DG4is disposed on the first type doped region41of the transistor T1and on the second type doped region42of the resistor R1. A fourth dummy gate structure DG4is disposed on the first type doped region41of the transistor T2and on the second type doped region42of the resistor R2. In some embodiments, a connection element C1is disposed on the active region OD and on both the first type doped region41and second type doped region42. The connection element C1comprises a first portion C1a, a second portion C1b, and a third portion C1c. The first portion C1ais disposed between the second dummy gate structure DG2and the third dummy gate structure DG3. The first portion C1a, the second portion C1b, and the third portion C1care integrated in one piece. The connection element C1can direct the current via the first portion C1ato the third portion C1c. The connection element C1can direct the current from the second type doped region42to the first type doped region41. The connection element C1can bypass the path within the second type doped region42below the third dummy gate structure DG3by directing the current. The connection element C1can bypass the path within the first type doped region41below the fourth dummy gate structure DG4by directing the current. The resistance value of the semiconductor device15can be reduced by directing the current through the connection element C1. The first portion C1a, the second portion C1b, and the third portion C1care interconnected. The third portion C1cis disposed between the fourth dummy gate structure DG4and the gate structure G2.

The source/drain conductor MD1/MD2are disposed on the epitaxial contacts44. The epitaxial contacts44are epitaxially grown in the S/D region of the transistors T1/T2. In some embodiments, the source conductor MD1includes a via and a conductive contact. In some embodiments, the drain conductor MD2includes a via and a conductive contact. The active region OD can also be referred to as oxide diffusion region OD. The poly structures PD1and PD2can be referred to as poly structures on OD edges, or simplified as “PODE.”

In some embodiments, the gate structures G1and G2can be electrically connected to the same voltage reference. In some embodiments, the gate structures G1and G2can be electrically connected to different voltage references. The gate structures G1and G2can be electrically connected through upper-layered interconnections (not shown). The drain conductors MD2can be electrically connected to the same voltage reference. The drain conductors MD2can be electrically connected through upper-layered interconnections (not shown). The source conductor MD1can be electrically connected through upper-layered interconnections (not shown). With the multi-finger structure shown inFIG.6, the resistance of the equivalent resistor R1and R2constituted by the regions below the dummy gate structures DG1and DG2can be adjusted according to need. In some embodiments, the drain conductors MD2are disposed over a single active region OD. In some embodiments, the drain conductors MD2will not extend to another active region (not shown) adjacent to the active region OD depicted inFIG.6. In some embodiments, the numbers of the dummy gate structures can be adjusted in accordance with actual design needs. In some embodiments, the number of the dummy gate structures can range from 1 to 30. In some embodiments, the dimensions of the dummy gate structures can range from 3 nm to 2 μm (micrometer).

FIG.7is a layout of a semiconductor device including transistors and two embedded resistors, in accordance with some embodiments. The layout34shown inFIG.7pertains to a semiconductor device including eight transistors and two resistors. The layout34can correspond to a top view perspective of a semiconductor device including eight transistors and two resistors. The layout34includes an active region OD, gate structures G1ato G1d, gate structures G2ato G2d, a source conductor MD1, conductors MD2ato MD2d, dummy gate structures DG1. DG2, DG3, DG3, DG4, and DG5, and poly structures PD1and PD2. The active region OD can also be referred to as oxide diffusion region OD. The poly structures PD1and PD2can be referred to as poly structures on OD edges, or simply as “PODE.”

A transistor structure Tla includes gate structures G1ato G1d. A transistor structure T2aincludes gate structures G2ato G2d. The gate structure G1ais disposed between the source conductor MD1and the conductor MD1a. The conductor MD1amay function as a drain conductor of the gate structure G1a. The gate structure G1bis disposed between the source conductor MD1and the conductor MD1b. In some embodiments, the conductor MD1bmay function as a drain conductor of the gate structure G1band the conductor MD1amay function as the source conductor of the gate structure G1b. The length of the source conductor MD1ais shorter than the length of the gate structure G1afrom a top view. The length of the source conductor MD1ais shorter than the length of the gate structure G2afrom a top view. The length of the drain conductor MD2ais shorter than the length of the gate structure G1afrom a top view. The length of the drain conductor MD2ais shorter than the length of the gate structure G2afrom a top view. Since the lengths of the source conductor MD1aand the lengths of the drain conductors MD2ato MD2dare the same, the semiconductor device manufactured in accordance with the layout34can be referred to as a device with balanced source/drain conductors.

The transistor structure T2acomprises the source conductor MD1, gate structure G2a, conductor MD2a, gate structure G2b, conductor MD2b, gate structure G2c, conductor MD2c, gate structure G2d, and conductor MD2ddisposed on the active region OD. The dummy gate structure DG1is disposed between the gate structure G2aand the source conductor MD1. The transistor structure T2acomprises a first type doped region41and a second type doped region42adjacent to the first type doped region41. The first type doped region41is disposed below the gate structure G2a, the gate structure G2b, the conductor MD2c, and the gate structure G2d. The second type doped region.42of the active region OD is adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The dummy gate structure DG1is disposed on the second type doped region42. The dummy gate structure DG2is disposed on the second type doped region42. The dummy gate structure DG2is disposed between the dummy gate structure DG1and the source conductor MD1. The dummy gate structure DG3is disposed on the second type doped region42and the dummy gate structure DG4is disposed on the first type doped region41. The first portion C2a, the second portion C2b, and the third portion C2care integrated in one piece. The third portion C2cis disposed between the dummy gate structure DG4and the first gate structure G2a.

The drain conductor MD1aincludes edges e1and e2, the active region OD includes edges e3and e4, and the gate conductor G2aincludes edges e5and e6. The edges e3and e4of the active region OD can also be referred to as boundaries e3and e4. The edge e1of the drain conductor MD2ais misaligned with the edge e3of the active region OD, and edge e2of the drain conductor MD2ais misaligned with the edge e4of the active region OD. The edges e3and e4of the active region OD can be located between edges e1and e2of the drain conductor MD2a. The edges e3and e4of the active region OD can be located between edges e5and e6of the gate conductor G2a.

The edge e5of the gate conductor G2ais misaligned with the edge e3of the active region OD, and edge e6of the gate conductor G2ais misaligned with the edge e4of the active region OD. The edges e1and e2of the drain conductor MD2aare both outside the area (e.g., defined by edges e3and e4) of the active region OD. The edge e1of the drain conductor MD2ais misaligned with the edge e5of the gate conductor G2a, and edge e2of the drain conductor MD2ais misaligned with the edge e6of the gate conductor G2a.

In some embodiments, the drain conductors MD2ato MD2dare disposed over a single active region OD. In some embodiments, the drain conductor MD2ato MD2dwill not extend to another active region (not shown) adjacent to the active region OD depicted inFIG.7. In some embodiments, the drain conductor MD1ato MD1dwill not extend to another active region (not shown) adjacent to the active region OD depicted inFIG.7.

The source conductor MD1, the gate structures G1ato Gd, and the conductors MD1ato MD1dcan constitute four transistors G1ato G1dhaving resistor regions electrically connected to the source of the transistor G1a. In some embodiments, the length of the source conductor MD1acan range from 0.1 times to 0.9 times that of the drain conductor MD2afrom a top view. In some embodiments, the length of the source conductor MD1acan range from 0.1 times to 0.9 times that of the gate structure G1afrom a top view. In some embodiments, a conductive via V1is disposed on the source conductor MD1. In some embodiments, a conductive via V1ais disposed on the conductor MD1a, a conductive via V1bis disposed on the conductor MD1b, a conductive via V1cis disposed on the conductor MD1c, and a conductive via V1dis disposed on the conductor MD1d. In some embodiments, a conductive via V2ais disposed on the conductor MD2a, a conductive via V2bis disposed on the conductor MD2b, a conductive via V2cis disposed on the conductor MD2c, and a conductive via V2dis disposed on the conductor MD2d.

In some embodiments, the source conductor MD1a(i.e., along the y-axis) can range from 0.01 μm to 5 μm. In some embodiments, the length of the drain conductor MD2a(i.e., along the y-axis) can range from 0.01 μm to 5 μm. In some embodiments, the width of the gate structure G1(i.e., along the x-axis) can range from 0.001 μm to 10 μm. The poly structures PD1and PD2can be useful in process control during manufacturing. The dummy gate structures DG1and DG2are optional (i.e., not mandatory in the layout30) and can be useful in reducing layout dependence effects. The number of the dummy gate structures can be increased or decreased depending on the user requirements.

In some embodiments, a third dummy gate structure DG3is disposed on the second type doped region42. In some embodiments, a fourth dummy gate structure DG4is disposed on the first type doped region41. In some embodiments, a connection element C2is disposed on the active region OD. The connection element C2comprises a first portion C2a, a second portion C2b, and a third portion C2c. The first portion C2ais disposed between the second dummy gate structure DG2and the third dummy gate structure DG3. The first portion C2a, the second portion C2b, and the third portion C2care integrated in one piece. The connection element C2can direct the current via the first portion C2ato the third portion C2c. The connection element C2can bypass the path within the second type doped region42below the third dummy gate structure DG3by directing the current. The connection element C2can bypass the path within the first type doped region41below the fourth dummy gate structure DG4by directing the current. The resistance value of the semiconductor device15can be reduced by directing the current through the connection element C2. The first portion C2a, the second portion C2b, and the third portion C2care interconnected. The third portion C2cis disposed between the fourth dummy gate structure DG4and the gate structure G2a.

In some embodiments, from a top view, an edge e7of the first portion C2ais located outside the edge3of the active region OD. The second portion C2bis located outside the edge4of the active region OD. In some embodiments, from a top view, the edge e1of the drain conductor MD2ais located outside the active region OD from a top view. The edge e5of the gate structure G2ais located outside the active region OD from a top view.

In some embodiments, a connection element C1is disposed on the active region OD and on both the first type doped region41and second type doped region42. The connection element C1comprises a first portion C1a, a second portion C1b, and a third portion C1c. The first portion C1ais disposed between the second dummy gate structure DG2and the third dummy gate structure DG3. The first portion C1a, the second portion C1b, and the third portion C1care integrated in one piece. The connection element C1can direct the current via the first portion C1ato the third portion C1c. The connection element C1can direct the current from the second type doped region42to the first type doped region41. The connection element C1can bypass the path within the second type doped region42below the third dummy gate structure DG3by directing the current. The connection element C1can bypass the path within the first type doped region41below the fourth dummy gate structure DG4by directing the current. The resistance value of the semiconductor device15can be reduced by directing the current through the connection element C1. The first portion C1a, the second portion C1b, and the third portion C1care interconnected. The third portion C1cis disposed between the fourth dummy gate structure DG4and the gate structure G2a.

FIG.8is a flowchart of a method800of manufacturing a semiconductor device, in accordance with some embodiments. The method800is operable to form a current mirror circuit (e.g., the20current mirror circuit shown inFIG.2) that includes a transistor having an embedded resistor, as discussed in accordance with the layouts30and34ofFIGS.5and7.

In some embodiments, the operations of method800are performed in the order depicted inFIG.8. In some embodiments, the operations of method8are performed in an order other than that depicted inFIG.8and/or two or more operations of method800are performed simultaneously. In some embodiments, one or more additional operations are performed before, during, and/or after the operations of method800.

In operation802, a substrate is formed. In operation804, an active region is formed on the substrate. In some embodiments, the active region may correspond to the active region OD in accordance with some embodiments. In operation806, a first type doped region41of the active region OD is formed and a second type doped region42of the active region OD is formed adjacent to the first type doped region. In some embodiments, the first type doped region is different from the second type doped region. In operation808, a gate structure G2, a source conductor MD1, and a drain conductor MD2are formed on the active region OD. In some embodiments, the second type doped region42is is configured to function as a resistor48.

In operation810, a dummy gate structure DG1is formed on the second type doped region42and a dummy gate structure DG2is formed on the second type doped region42, and a dummy gate structure DG3is formed on the second type doped region42and a dummy gate structure DG4is formed on the first type doped region41.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, an active region on the substrate, a source conductor, a first gate structure, a first conductor, a second gate structure, a second conductor, a third gate structure, a third conductor, a fourth gate structure, a fourth conductor disposed on the active region, and a first dummy gate structure disposed between the first gate structure and the source conductor, a first type doped region of the active region, and a second type doped region of the active region adjacent to the first type doped region. The first type doped region is disposed below the the first gate structure, the second gate structure, the third conductor, and the fourth gate structure. The second type doped region of the active region is adjacent to the first type doped region, and the first type doped region is different from the second type doped region.

According to some embodiments, a method of manufacturing a semiconductor device comprises forming a substrate, forming an active region on the substrate, forming a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, wherein the first type doped region is different from the second type doped region, and forming a gate structure, a source conductor, and a drain conductor on the active region, wherein the second type doped region is configured to function as a resistor.

The methods and features of the present disclosure have been sufficiently described in the examples and descriptions provided. It should be understood that any modifications or changes without departing from the spirit of the present disclosure are intended to be covered in the protection scope of the present disclosure.

Moreover, the scope of the present application in not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the present disclosure, processes, machines, manufacture, composition of matter, means, methods or steps presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure.

Accordingly, the appended claims are intended to include within their scope processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the present disclosure.